From 320e85aa6eb3ad3da37922d179ab91b4fda0d724 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Fri, 13 May 2022 21:47:36 +0000 Subject: Agah: Add command to block power sequence This patch adds blockseq commands, which blocks PG_PP3300_S5_OD. This patch also makes the down arrow key block the PG signal as well. BUG=b:226438219 BRANCH=None TEST=None Signed-off-by: Daisuke Nojiri Change-Id: I192c3d3e70d4e2233e60d227857ba7a2fd6f0a34 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3646960 Reviewed-by: Parth Malkan --- board/agah/board.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/board/agah/board.c b/board/agah/board.c index d1cc519402..979c9a38aa 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -15,13 +15,16 @@ #include "hooks.h" #include "fw_config.h" #include "hooks.h" +#include "keyboard_scan.h" #include "lid_switch.h" #include "power_button.h" #include "power.h" #include "registers.h" #include "switch.h" +#include "system.h" #include "throttle_ap.h" #include "usbc_config.h" +#include "util.h" #include "gpio_list.h" /* Must come after other header files. */ @@ -29,6 +32,8 @@ #define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) #define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +static int block_sequence; + __override void board_cbi_init(void) { } @@ -51,6 +56,11 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); static void board_init(void) { + if ((system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) || + (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) { + CPRINTS("PG_PP3300_S5_OD block is enabled"); + block_sequence = 1; + } gpio_enable_interrupt(GPIO_PG_PP3300_S5_OD); gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL); } @@ -61,9 +71,13 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); */ static void bypass_pp3300_s5_deferred(void) { - int pg_pp3300_s5 = gpio_get_level(GPIO_PG_PP3300_S5_OD); + if (block_sequence) { + CPRINTS("PG_PP3300_S5_OD is blocked."); + return; + } - gpio_set_level(GPIO_PG_PP3300_S5_EC_SEQ_OD, pg_pp3300_s5); + gpio_set_level(GPIO_PG_PP3300_S5_EC_SEQ_OD, + gpio_get_level(GPIO_PG_PP3300_S5_OD)); } DECLARE_DEFERRED(bypass_pp3300_s5_deferred); @@ -72,3 +86,18 @@ void board_power_interrupt(enum gpio_signal signal) /* Trigger deferred notification of gpio PG_PP3300_S5_OD change */ hook_call_deferred(&bypass_pp3300_s5_deferred_data, 0); } + +static int cc_blockseq(int argc, char *argv[]) +{ + if (argc > 1) { + if (!parse_bool(argv[1], &block_sequence)) { + ccprintf("Invalid argument: %s\n", argv[1]); + return EC_ERROR_INVAL; + } + } + + ccprintf("PG_PP3300_S5_OD block is %s\n", + block_sequence ? "enabled" : "disabled"); + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(blockseq, cc_blockseq, "[on/off]", NULL); -- cgit v1.2.1 From 47e54b10c318dd5669b7edfed6c6dc9e3a7b56bb Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Mon, 20 May 2019 15:31:05 -0700 Subject: charge_manager: Make chgsup print more This patch makes chgsup command print all available charge port information. > chgsup Port --Supplier-- Prio -Avalable Power- P0 PD 1 3000mA 15000mV USBC_1_5A 4 500mA 5000mV VBUS 4 500mA 5000mV *P2 DEDICATED 0 7700mA 19500mV Left safe mode Override port = -1 BUG=None BRANCH=None TEST=See above Change-Id: I3531b445f8d79c910150db643363aa84b74aee94 Signed-off-by: Daisuke Nojiri Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3710279 Reviewed-by: Keith Short --- common/charge_manager.c | 45 ++++++++++++++++++++++++++++++++++++++------- include/charge_manager.h | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 77 insertions(+), 8 deletions(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index f8a08b7fa8..a1cc53fe59 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -79,6 +79,11 @@ __overridable const int supplier_priority[] = { }; BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT); +const char *charge_supplier_name[] = { + CHARGE_SUPPLIER_NAME +}; +BUILD_ASSERT(ARRAY_SIZE(charge_supplier_name) == CHARGE_SUPPLIER_COUNT); + /* Keep track of available charge for each charge port. */ static struct charge_port_info available_charge[CHARGE_SUPPLIER_COUNT] [CHARGE_PORT_COUNT]; @@ -1630,13 +1635,39 @@ DECLARE_CONSOLE_COMMAND(chglim, command_external_power_limit, #ifdef CONFIG_CMD_CHARGE_SUPPLIER_INFO static int charge_supplier_info(int argc, char **argv) { - ccprintf("port=%d, type=%d, cur=%dmA, vtg=%dmV, lsm=%d\n", - charge_manager_get_active_charge_port(), - charge_supplier, - charge_current, - charge_voltage, - left_safe_mode); - + int p, s; + int port_printed; + + ccprintf("\n"); + ccprintf("Port --Supplier-- Prio -Available Power-\n"); + for (p = 0; p < CHARGE_PORT_COUNT; p++) { + port_printed = 0; + for (s = 0; s < CHARGE_SUPPLIER_COUNT; s++) { + if (available_charge[s][p].current == 0 && + available_charge[s][p].voltage == 0) + continue; + if (charge_manager_get_active_charge_port() == p && + charge_manager_get_supplier() == s) + ccprintf("*"); + else + ccprintf(" "); + if (!port_printed) { + ccprintf("P%d ", p); + port_printed = 1; + } else { + ccprintf(" "); + } + ccprintf("%-10s %4d %5dmA %5dmV\n", + charge_supplier_name[s], + supplier_priority[s], + available_charge[s][p].current, + available_charge[s][p].voltage); + } + } + ccprintf("\n"); + ccprintf(" %s safe mode\n", left_safe_mode ? "Left" : "In"); + ccprintf(" Override port = P%d\n", charge_manager_get_override()); + ccprintf("\n"); return 0; } DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info, diff --git a/include/charge_manager.h b/include/charge_manager.h index b6d3c235bf..e8e09798bf 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -30,7 +30,10 @@ */ #define CHARGE_DETECT_DELAY (2*SECOND) -/* Commonly-used charge suppliers listed in no particular order */ +/* + * Commonly-used charge suppliers listed in no particular order. + * Don't forget to update CHARGE_SUPPLIER_NAME and supplier_priority. + */ enum charge_supplier { CHARGE_SUPPLIER_NONE = -1, CHARGE_SUPPLIER_PD, @@ -56,6 +59,41 @@ enum charge_supplier { CHARGE_SUPPLIER_COUNT }; +#ifdef CHARGE_MANAGER_BC12 +#define CHARGE_SUPPLIER_NAME_BC12 \ + [CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP", \ + [CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP", \ + [CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP", \ + [CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP", \ + [CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = "USBC_U1_5A", \ + [CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", \ + [CHARGE_SUPPLIER_VBUS] = "VBUS", +#else +#define CHARGE_SUPPLIER_NAME_BC12 +#endif +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 +#define CHARGE_SUPPLIER_NAME_DEDICATED \ + [CHARGE_SUPPLIER_DEDICATED] = "DEDICATED", +#else +#define CHARGE_SUPPLIER_NAME_DEDICATED +#endif +#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 +#define CHARGE_SUPPLIER_NAME_QI \ + [CHARGE_SUPPLIER_WPC_BPP] = "QI_BPP", \ + [CHARGE_SUPPLIER_WPC_EPP] = "QI_EPP", \ + [CHARGE_SUPPLIER_WPC_GPP] = "QI_GPP", +#else +#define CHARGE_SUPPLIER_NAME_QI +#endif + +#define CHARGE_SUPPLIER_NAME \ + [CHARGE_SUPPLIER_PD] = "PD", \ + [CHARGE_SUPPLIER_TYPEC] = "USBC", \ + [CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS", \ + CHARGE_SUPPLIER_NAME_BC12 \ + CHARGE_SUPPLIER_NAME_DEDICATED \ + CHARGE_SUPPLIER_NAME_QI + /* * Charge supplier priority: lower number indicates higher priority. * Default priority is in charge_manager.c. It can be overridden by boards. -- cgit v1.2.1 From 632c1037debfd9f8f6684a780563074e45945ffd Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Wed, 15 Jun 2022 10:19:58 +1000 Subject: ap_pwrseq: Initialise the ADC buffer for signal init Initialise the ADC buffer to 0 before reading the initial ADC power signal value. BUG=b:236044415 TEST=zmake build nivviks BRANCH=none Signed-off-by: Andrew McRae Change-Id: I1eafed3dffd257f8ef45b3c23aa648cf4e080a62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708573 Reviewed-by: Peter Marheine --- zephyr/subsys/ap_pwrseq/signal_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/subsys/ap_pwrseq/signal_adc.c b/zephyr/subsys/ap_pwrseq/signal_adc.c index 4b8f0e0366..eab01f2830 100644 --- a/zephyr/subsys/ap_pwrseq/signal_adc.c +++ b/zephyr/subsys/ap_pwrseq/signal_adc.c @@ -183,7 +183,7 @@ void power_signal_adc_init(void) DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_COMMA, high) }; int i, rv; - int32_t val; + int32_t val = 0; for (i = 0; i < ARRAY_SIZE(low_cb); i++) { /* -- cgit v1.2.1 From da5f8d5f0e9d39b98bf93dbebf52065b3a462e4d Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Thu, 16 Jun 2022 16:32:05 +1000 Subject: ap_pwrseq: Add some extra debug detail for init Add some more extensive debug detail for power sequence init. BUG=none TEST=zmake build nivviks BRANCH=none Signed-off-by: Andrew McRae Change-Id: Ica5ddd73a3b9817407adba93c40809e13c253e02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708574 Reviewed-by: Peter Marheine --- .../ap_pwrseq/x86_non_dsx_chipset_power_state.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c index 97268e8fe6..5d0fd8cd07 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c @@ -14,10 +14,11 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); */ enum power_states_ndsx chipset_pwr_seq_get_state(void) { + power_signal_mask_t sig = power_get_signals() & MASK_ALL_POWER_GOOD; /* * Chip is shut down. */ - if ((power_get_signals() & MASK_ALL_POWER_GOOD) == 0) { + if (sig == 0) { LOG_DBG("Power rails off, G3 state"); return SYS_POWER_STATE_G3; } @@ -25,10 +26,11 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void) * If not all the power rails are available, * then force shutdown to G3 to get to known state. */ - if ((power_get_signals() & MASK_ALL_POWER_GOOD) - != MASK_ALL_POWER_GOOD) { + if (sig != MASK_ALL_POWER_GOOD) { + LOG_INF("Not all power rails up (missing %#x)," + " forcing shutdown", + sig ^ MASK_ALL_POWER_GOOD); ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); - LOG_INF("Not all power rails up, forcing shutdown"); return SYS_POWER_STATE_G3; } @@ -56,17 +58,18 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void) LOG_DBG("All VW signals valid after %d ms", delay * 10); break; } + sig = power_get_signals(); /* * S0, all power OK, no suspend or sleep on. */ - if ((power_get_signals() & MASK_S0) == MASK_ALL_POWER_GOOD) { + if ((sig & MASK_S0) == MASK_ALL_POWER_GOOD) { LOG_DBG("CPU in S0 state"); return SYS_POWER_STATE_S0; } /* * S3, all power OK, PWR_SLP_S3 on. */ - if ((power_get_signals() & MASK_S0) == + if ((sig & MASK_S0) == (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))) { LOG_DBG("CPU in S3 state"); return SYS_POWER_STATE_S3; @@ -74,14 +77,15 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void) /* * S5, all power OK, PWR_SLP_S5 on. */ - if ((power_get_signals() & MASK_S5) == MASK_S5) { + if ((sig & MASK_S5) == MASK_S5) { LOG_DBG("CPU in S5 state"); return SYS_POWER_STATE_S5; } /* * Unable to determine state, force to G3. */ + LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", + sig); ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); - LOG_INF("Unable to determine CPU state, forcing shutdown"); return SYS_POWER_STATE_G3; } -- cgit v1.2.1 From f77d2a0d3a0e2857873a2fcd87a14d6712275f91 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Fri, 17 Jun 2022 14:55:23 +1000 Subject: ap_pwrseq: Rework check of initial AP state S5 was not being detected because not all power signals were up. Rework the checks for S0/S3/S5 so that they reflect what the state of the signals are in these states. BUG=b:234094006 TEST=zmake build nivviks BRANCH=none Signed-off-by: Andrew McRae Change-Id: I4216c6bc9e55caba7b980851ce391fc9af8b1afd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708386 Reviewed-by: Peter Marheine --- .../subsys/ap_pwrseq/include/x86_power_signals.h | 53 ++++++++++++++++++++-- .../ap_pwrseq/x86_non_dsx_chipset_power_state.c | 33 +++++++------- 2 files changed, 66 insertions(+), 20 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h index 4e1277dce7..b31117569d 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h @@ -13,6 +13,10 @@ #define IN_PCH_SLP_S4 POWER_SIGNAL_MASK(PWR_SLP_S4) #define IN_PCH_SLP_S5 POWER_SIGNAL_MASK(PWR_SLP_S5) +/* + * Define the chipset specific power signal masks and values + * matching the AP state. + */ #if defined(CONFIG_AP_X86_INTEL_ADL) /* Input state flags */ @@ -26,6 +30,15 @@ POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) | \ POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ POWER_SIGNAL_MASK(PWR_PG_PP1P05)) + +#define MASK_VW_POWER \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ + POWER_SIGNAL_MASK(PWR_SLP_SUS)) +#define VALUE_VW_POWER \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK)) + #define MASK_S0 \ (MASK_ALL_POWER_GOOD | \ POWER_SIGNAL_MASK(PWR_SLP_S0) | \ @@ -33,6 +46,20 @@ POWER_SIGNAL_MASK(PWR_SLP_SUS) | \ POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define VALUE_S0 MASK_ALL_POWER_GOOD + +#define MASK_S3 MASK_S0 +#define VALUE_S3 \ + (MASK_ALL_POWER_GOOD | \ + POWER_SIGNAL_MASK(PWR_SLP_S3)) + +#define MASK_S5 \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ + POWER_SIGNAL_MASK(PWR_SLP_S3) | \ + POWER_SIGNAL_MASK(PWR_SLP_S4) | \ + POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define VALUE_S5 MASK_S5 #elif defined(CONFIG_AP_X86_INTEL_MTL) @@ -43,19 +70,37 @@ #define MASK_ALL_POWER_GOOD \ (POWER_SIGNAL_MASK(PWR_RSMRST) | \ POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD)) + +#define MASK_VW_POWER \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK)) +#define VALUE_VW_POWER \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK)) + #define MASK_S0 \ (MASK_ALL_POWER_GOOD | \ POWER_SIGNAL_MASK(PWR_SLP_S0) | \ POWER_SIGNAL_MASK(PWR_SLP_S3) | \ POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define VALUE_S0 MASK_ALL_POWER_GOOD -#else -#warning("Input power signals state flags not defined"); -#endif +#define MASK_S3 MASK_S0 +#define VALUE_S3 \ + (MASK_ALL_POWER_GOOD | \ + POWER_SIGNAL_MASK(PWR_SLP_S3)) #define MASK_S5 \ - (MASK_ALL_POWER_GOOD | \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ + POWER_SIGNAL_MASK(PWR_SLP_S3) | \ + POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define VALUE_S5 MASK_S5 + +#else +#warning("Input power signals state flags not defined"); +#endif #endif /* __X86_POWER_SIGNALS_H__ */ diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c index 5d0fd8cd07..73d2819a2d 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c @@ -14,28 +14,28 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); */ enum power_states_ndsx chipset_pwr_seq_get_state(void) { - power_signal_mask_t sig = power_get_signals() & MASK_ALL_POWER_GOOD; + power_signal_mask_t sig = power_get_signals(); + /* - * Chip is shut down. + * Chip is shut down, G3 state. */ - if (sig == 0) { - LOG_DBG("Power rails off, G3 state"); + if ((sig & MASK_ALL_POWER_GOOD) == 0) { + LOG_DBG("All power rails off, G3 state"); return SYS_POWER_STATE_G3; } /* - * If not all the power rails are available, - * then force shutdown to G3 to get to known state. + * Not enough power rails up to read VW signals. + * Force a shutdown. */ - if (sig != MASK_ALL_POWER_GOOD) { - LOG_INF("Not all power rails up (missing %#x)," - " forcing shutdown", - sig ^ MASK_ALL_POWER_GOOD); + if ((sig & MASK_VW_POWER) != VALUE_VW_POWER) { + LOG_ERR("Not enough power signals on (%#x), forcing shutdown", + sig); ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); return SYS_POWER_STATE_G3; } /* - * All the power rails are good, so + * Enough power signals are up, so * wait for virtual wire signals to become available. * Not sure how long to wait? 5 seconds total. */ @@ -58,26 +58,27 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void) LOG_DBG("All VW signals valid after %d ms", delay * 10); break; } + /* Re-read the power signals */ sig = power_get_signals(); + /* * S0, all power OK, no suspend or sleep on. */ - if ((sig & MASK_S0) == MASK_ALL_POWER_GOOD) { + if ((sig & MASK_S0) == VALUE_S0) { LOG_DBG("CPU in S0 state"); return SYS_POWER_STATE_S0; } /* * S3, all power OK, PWR_SLP_S3 on. */ - if ((sig & MASK_S0) == - (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3))) { + if ((sig & MASK_S3) == VALUE_S3) { LOG_DBG("CPU in S3 state"); return SYS_POWER_STATE_S3; } /* - * S5, all power OK, PWR_SLP_S5 on. + * S5, some power signals on, PWR_SLP_S5 on. */ - if ((sig & MASK_S5) == MASK_S5) { + if ((sig & MASK_S5) == VALUE_S5) { LOG_DBG("CPU in S5 state"); return SYS_POWER_STATE_S5; } -- cgit v1.2.1 From 9dae5323bbc98540cc7ee76450c4286fa99d961d Mon Sep 17 00:00:00 2001 From: David Huang Date: Mon, 23 May 2022 14:21:56 +0800 Subject: agah: delay thermal sensor read in the first time Add 500 ms delay of thermal sensor first read in agah. BUG=none BRANCH=none TEST=Shutdown and power on to check system doesn't trigger thermal shutdown. Signed-off-by: David Huang Change-Id: I6b0509f0e7a05b23701d5555a82dd64afcd4c99d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3659127 Reviewed-by: Zick Wei Reviewed-by: Kenny Pan Reviewed-by: Daisuke Nojiri --- board/agah/board.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/agah/board.h b/board/agah/board.h index 7655f9a4fe..0b8253d0cc 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -92,6 +92,7 @@ #define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST #define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup @@ -132,7 +133,8 @@ /* Thermal features */ #define CONFIG_THERMISTOR #define CONFIG_TEMP_SENSOR -#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK +#define CONFIG_TEMP_SENSOR_POWER +#define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B #define CONFIG_FANS FAN_CH_COUNT -- cgit v1.2.1 From e0c1795a9ab6599419b763054e89bcf2662a1f6e Mon Sep 17 00:00:00 2001 From: David Huang Date: Tue, 7 Jun 2022 18:28:03 +0800 Subject: zephyr: Add controlled EC_CBI_WP Control EC_CBI_WP based on WP_ODL state. BUG=b:234572033 b:236067475 b:235425819 BRANCH=none TEST=Check EC_CBI_WP status enable/disable when WP_ODL enable/disable. Signed-off-by: David Huang Change-Id: If1a6b4c9ccf663894c33978864acc60bd37a2e45 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3694916 Reviewed-by: Eric Yilun Lin Tested-by: David Huang Auto-Submit: David Huang Commit-Queue: Eric Yilun Lin --- zephyr/app/ec/ec_app_main.c | 9 +++++++++ zephyr/shim/include/config_chip.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c index 12043a3c4a..17c6eeb697 100644 --- a/zephyr/app/ec/ec_app_main.c +++ b/zephyr/app/ec/ec_app_main.c @@ -11,6 +11,7 @@ #include "ap_power/ap_pwrseq.h" #include "button.h" #include "chipset.h" +#include "cros_board_info.h" #include "ec_tasks.h" #include "hooks.h" #include "keyboard_scan.h" @@ -76,6 +77,14 @@ void ec_app_main(void) hook_notify(HOOK_INIT); } + /* + * If the EC has exclusive control over the CBI EEPROM WP signal, have + * the EC set the WP if appropriate. Note that once the WP is set, the + * EC must be reset via EC_RST_ODL in order for the WP to become unset. + */ + if (IS_ENABLED(CONFIG_PLATFORM_EC_EEPROM_CBI_WP) && system_is_locked()) + cbi_latch_eeprom_wp(); + /* * Print the init time. Not completely accurate because it can't take * into account the time before timer_init(), but it'll at least catch diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 73f38a72f4..a498e6909e 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -2108,6 +2108,11 @@ extern struct jump_data mock_jump_data; #define I2C_ADDR_EEPROM_FLAGS DT_REG_ADDR(DT_NODELABEL(cbi_eeprom)) #endif +#undef CONFIG_EEPROM_CBI_WP +#ifdef CONFIG_PLATFORM_EC_EEPROM_CBI_WP +#define CONFIG_EEPROM_CBI_WP +#endif + #undef CONFIG_CBI_GPIO #ifdef CONFIG_PLATFORM_EC_CBI_GPIO #define CONFIG_CBI_GPIO -- cgit v1.2.1 From 3e581739206f58a45a68b6c4703246ebac995195 Mon Sep 17 00:00:00 2001 From: elmo_lan Date: Fri, 17 Jun 2022 14:47:59 +0800 Subject: nissa: Initial zephyr config for xivu Initial EC Zephyr config for Nissa/Xivu. BUG=b:235936531 TEST=zmake build xivu BRANCH=none Signed-off-by: elmo_lan Change-Id: I304249c9f18b20d8d2151c7f0bf6e0025104445b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708626 Reviewed-by: Elthan Huang Reviewed-by: Andrew McRae Commit-Queue: Henry Sun Reviewed-by: Peter Marheine --- zephyr/projects/nissa/BUILD.py | 16 +- zephyr/projects/nissa/CMakeLists.txt | 9 + zephyr/projects/nissa/Kconfig | 6 + zephyr/projects/nissa/prj_xivu.conf | 39 ++++ zephyr/projects/nissa/src/xivu/charger.c | 56 +++++ zephyr/projects/nissa/src/xivu/led.c | 47 ++++ zephyr/projects/nissa/src/xivu/usbc.c | 281 +++++++++++++++++++++++ zephyr/projects/nissa/xivu_generated.dts | 289 ++++++++++++++++++++++++ zephyr/projects/nissa/xivu_keyboard.dts | 32 +++ zephyr/projects/nissa/xivu_motionsense.dts | 156 +++++++++++++ zephyr/projects/nissa/xivu_overlay.dts | 319 +++++++++++++++++++++++++++ zephyr/projects/nissa/xivu_power_signals.dts | 220 ++++++++++++++++++ zephyr/projects/nissa/xivu_pwm_leds.dts | 63 ++++++ 13 files changed, 1532 insertions(+), 1 deletion(-) create mode 100644 zephyr/projects/nissa/prj_xivu.conf create mode 100644 zephyr/projects/nissa/src/xivu/charger.c create mode 100644 zephyr/projects/nissa/src/xivu/led.c create mode 100644 zephyr/projects/nissa/src/xivu/usbc.c create mode 100644 zephyr/projects/nissa/xivu_generated.dts create mode 100644 zephyr/projects/nissa/xivu_keyboard.dts create mode 100644 zephyr/projects/nissa/xivu_motionsense.dts create mode 100644 zephyr/projects/nissa/xivu_overlay.dts create mode 100644 zephyr/projects/nissa/xivu_power_signals.dts create mode 100644 zephyr/projects/nissa/xivu_pwm_leds.dts diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index a620e7b9ae..a0acb90680 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -4,7 +4,7 @@ """Define zmake projects for nissa.""" -# Nivviks and Craask, Pujjo has NPCX993F, Nereid has ITE81302 +# Nivviks and Craask, Pujjo, Xivu has NPCX993F, Nereid has ITE81302 def register_nissa_project( @@ -82,3 +82,17 @@ pujjo = register_nissa_project( ], extra_kconfig_files=[here / "prj_pujjo.conf"], ) + +xivu = register_nissa_project( + project_name="xivu", + chip="npcx9m3f", + extra_dts_overlays=[ + here / "xivu_generated.dts", + here / "xivu_overlay.dts", + here / "xivu_motionsense.dts", + here / "xivu_keyboard.dts", + here / "xivu_power_signals.dts", + here / "xivu_pwm_leds.dts", + ], + extra_kconfig_files=[here / "prj_xivu.conf"], +) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index afc96e924f..9f2452bcbc 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -49,3 +49,12 @@ if(DEFINED CONFIG_BOARD_PUJJO) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") endif() +if(DEFINED CONFIG_BOARD_XIVU) + zephyr_library_sources( + "src/xivu/led.c" + ) + project(xivu) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/xivu/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/xivu/charger.c") +endif() + diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig index 87d7bca977..d9ba0f9015 100644 --- a/zephyr/projects/nissa/Kconfig +++ b/zephyr/projects/nissa/Kconfig @@ -26,6 +26,12 @@ config BOARD_PUJJO Build Google Pujjo board. Pujjo has Intel ADL-N SoC with NPCX993FA0BX EC. +config BOARD_XIVU + bool "Google Xivu Board" + help + Build Google Xivu board. Xivu has Intel ADL-N SoC + with NPCX993FA0BX EC. + module = NISSA module-str = Nissa board-specific code source "subsys/logging/Kconfig.template.log_config" diff --git a/zephyr/projects/nissa/prj_xivu.conf b/zephyr/projects/nissa/prj_xivu.conf new file mode 100644 index 0000000000..fc46adb7f7 --- /dev/null +++ b/zephyr/projects/nissa/prj_xivu.conf @@ -0,0 +1,39 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: NPCX993 +CONFIG_BOARD_XIVU=y +CONFIG_CROS_FLASH_NPCX=y +CONFIG_CROS_SYSTEM_NPCX=y +CONFIG_SOC_SERIES_NPCX9=y +CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API=y +CONFIG_SYSCON=y +CONFIG_TACH_NPCX=n + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_PLATFORM_EC_KBLIGHT_ENABLE_PIN=y + +# TCPC+PPC: both C0 and C1 (if present) are RAA489000 +CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US=100000 +# RAA489000 uses TCPCI but not a separate PPC, so custom function is required +CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y +# type C port 1 redriver +CONFIG_PLATFORM_EC_USBC_RETIMER_ANX7483=y + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_RAA489000=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_ADC_CMP_NPCX=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n diff --git a/zephyr/projects/nissa/src/xivu/charger.c b/zephyr/projects/nissa/src/xivu/charger.c new file mode 100644 index 0000000000..baa204f825 --- /dev/null +++ b/zephyr/projects/nissa/src/xivu/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "charger/isl923x_public.h" +#include "console.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = raa489000_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Xivu does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + raa489000_hibernate(CHARGER_SECONDARY, true); + raa489000_hibernate(CHARGER_PRIMARY, true); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/src/xivu/led.c b/zephyr/projects/nissa/src/xivu/led.c new file mode 100644 index 0000000000..a0c0447419 --- /dev/null +++ b/zephyr/projects/nissa/src/xivu/led.c @@ -0,0 +1,47 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery LED control for nissa + */ +#include "common.h" +#include "ec_commands.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "led_pwm.h" + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 97; +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, + [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, + [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, + [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, + [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 1 * LED_ONE_SEC} }, + [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC}, + {EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC} }, +}; + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_RED: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); + break; + case EC_LED_COLOR_BLUE: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); + break; + case EC_LED_COLOR_AMBER: + set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); + break; + default: /* LED_OFF and other unsupported colors */ + set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); + break; + } +} diff --git a/zephyr/projects/nissa/src/xivu/usbc.c b/zephyr/projects/nissa/src/xivu/usbc.c new file mode 100644 index 0000000000..32a390e502 --- /dev/null +++ b/zephyr/projects/nissa/src/xivu/usbc.c @@ -0,0 +1,281 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/isl923x_public.h" +#include "driver/retimer/anx7483_public.h" +#include "driver/tcpm/tcpci.h" +#include "driver/tcpm/raa489000.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, + { /* sub-board */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = RAA489000_TCPC0_I2C_FLAGS, + }, + .drv = &raa489000_tcpm_drv, + /* RAA489000 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_VBUS_MONITOR, + }, +}; + +int board_is_sourcing_vbus(int port) +{ + int regval; + + tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); + return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && + port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int old_port; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + + LOG_INF("New chg p%d", port); + + /* Disable all ports. */ + if (port == CHARGE_PORT_NONE) { + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW); + raa489000_enable_asgate(i, false); + } + + return EC_SUCCESS; + } + + /* Check if port is sourcing VBUS. */ + if (board_is_sourcing_vbus(port)) { + LOG_WRN("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i == port) + continue; + + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + LOG_WRN("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + if (raa489000_enable_asgate(port, true) || + tcpc_write(port, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + LOG_WRN("p%d: sink path enable failed.", port); + charger_discharge_on_ac(0); + return EC_ERROR_UNKNOWN; + } + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return EC_SUCCESS; +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int regval; + + /* + * The interrupt line is shared between the TCPC and BC1.2 detector IC. + * Therefore, go out and actually read the alert registers to report the + * alert status. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + if (!tcpc_read16(0, TCPC_REG_ALERT, ®val)) { + /* The TCPCI Rev 1.0 spec says to ignore bits 14:12. */ + if (!(tcpc_config[0].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_0; + } + } + + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ + if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) + regval &= ~((1 << 14) | (1 << 13) | (1 << 12)); + + if (regval) + status |= PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS */ + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_LOW); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + if (port < 0 || port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return; + + raa489000_set_output_current(port, rp); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + if (port >= CONFIG_USB_PD_PORT_MAX_COUNT) + return EC_ERROR_INVAL; + + /* Disable charging. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); + if (rv) + return rv; + + /* Our policy is not to source VBUS when the AP is off. */ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + return EC_ERROR_NOT_POWERED; + + /* Provide Vbus. */ + rv = tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SRC_CTRL_HIGH); + if (rv) + return rv; + + rv = raa489000_enable_asgate(port, true); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void board_reset_pd_mcu(void) +{ + /* + * TODO(b:147316511): could send a reset command to the TCPC here + * if needed. + */ +} + +/* + * Because the TCPCs and BC1.2 chips share interrupt lines, it's possible + * for an interrupt to be lost if one asserts the IRQ, the other does the same + * then the first releases it: there will only be one falling edge to trigger + * the interrupt, and the line will be held low. We handle this by running a + * deferred check after a falling edge to see whether the IRQ is still being + * asserted. If it is, we assume an interrupt may have been lost and we need + * to poll each chip for events again. + */ +#define USBC_INT_POLL_DELAY_US 5000 + +static void poll_c0_int(void); +DECLARE_DEFERRED(poll_c0_int); +static void poll_c1_int(void); +DECLARE_DEFERRED(poll_c1_int); + +static void usbc_interrupt_trigger(int port) +{ + schedule_deferred_pd_interrupt(port); + usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); +} + +static inline void poll_usb_gpio(int port, + const struct gpio_dt_spec *gpio, + const struct deferred_data *ud) +{ + if (!gpio_pin_get_dt(gpio)) { + usbc_interrupt_trigger(port); + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); + } +} + +static void poll_c0_int (void) +{ + poll_usb_gpio(0, + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + &poll_c0_int_data); +} + +static void poll_c1_int (void) +{ + poll_usb_gpio(1, + GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + &poll_c1_int_data); +} + +void usb_interrupt(enum gpio_signal signal) +{ + int port; + const struct deferred_data *ud; + + if (signal == GPIO_SIGNAL(DT_NODELABEL(gpio_usb_c0_int_odl))) { + port = 0; + ud = &poll_c0_int_data; + } else { + port = 1; + ud = &poll_c1_int_data; + } + /* + * We've just been called from a falling edge, so there's definitely + * no lost IRQ right now. Cancel any pending check. + */ + hook_call_deferred(ud, -1); + /* Trigger polling of TCPC and BC1.2 in respective tasks */ + usbc_interrupt_trigger(port); + /* Check for lost interrupts in a bit */ + hook_call_deferred(ud, USBC_INT_POLL_DELAY_US); +} diff --git a/zephyr/projects/nissa/xivu_generated.dts b/zephyr/projects/nissa/xivu_generated.dts new file mode 100644 index 0000000000..1a4d5f044f --- /dev/null +++ b/zephyr/projects/nissa/xivu_generated.dts @@ -0,0 +1,289 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + label = "EC_VSENSE_PP1050_PROC"; + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 4>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + label = "EC_VSENSE_PP3300_S5"; + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_1: temp_sensor_1 { + label = "TEMP_SENSOR_1"; + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_2: temp_sensor_2 { + label = "TEMP_SENSOR_2"; + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 1>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpio5 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpioa 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpio6 7 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioa 3 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio7 4 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiod 3 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpio0 3 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpio7 5 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_kso_02_inv: ec_kso_02_inv { + gpios = <&gpio1 7 (GPIO_OUTPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpiof 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpio6 1 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpioe 4 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpio8 0 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpio7 2 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpioc 1 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioa 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpio7 6 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpio3 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioa 4 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioa 0 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpiob 6 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpioe 2 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpio4 0 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpioe 1 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpio9 1 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpio5 6 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpio4 3 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiod 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpio9 6 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpio4 2 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpio9 4 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpio9 7 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioa 5 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpio7 0 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpio6 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiod 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpioc 5 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpio9 5 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpio8 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpio0 1 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpio9 2 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0_0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c1_0>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c3_0>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c5_1>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c7_0>; + enum-name = "I2C_PORT_BATTERY"; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_chan0_gp45 + &adc0_chan1_gp44 + &adc0_chan4_gp41 + &adc0_chan6_gp34>; + pinctrl-names = "default"; +}; + +&i2c0_0 { + status = "okay"; + pinctrl-0 = <&i2c0_0_sda_scl_gpb4_b5>; + pinctrl-names = "default"; +}; + +&i2c1_0 { + status = "okay"; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; + pinctrl-names = "default"; +}; + +&i2c3_0 { + status = "okay"; + pinctrl-0 = <&i2c3_0_sda_scl_gpd0_d1>; + pinctrl-names = "default"; +}; + +&i2c5_1 { + status = "okay"; + pinctrl-0 = <&i2c5_1_sda_scl_gpf4_f5>; + pinctrl-names = "default"; +}; + +&i2c7_0 { + status = "okay"; + pinctrl-0 = <&i2c7_0_sda_scl_gpb2_b3>; + pinctrl-names = "default"; +}; + +&i2c_ctrl0 { + status = "okay"; +}; + +&i2c_ctrl1 { + status = "okay"; +}; + +&i2c_ctrl3 { + status = "okay"; +}; + +&i2c_ctrl5 { + status = "okay"; +}; + +&i2c_ctrl7 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/xivu_keyboard.dts b/zephyr/projects/nissa/xivu_keyboard.dts new file mode 100644 index 0000000000..d3fd354b8f --- /dev/null +++ b/zephyr/projects/nissa/xivu_keyboard.dts @@ -0,0 +1,32 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = < + &ksi0_gp31 + &ksi1_gp30 + &ksi2_gp27 + &ksi3_gp26 + &ksi4_gp25 + &ksi5_gp24 + &ksi6_gp23 + &ksi7_gp22 + &kso00_gp21 + &kso01_gp20 + &kso03_gp16 + &kso04_gp15 + &kso05_gp14 + &kso06_gp13 + &kso07_gp12 + &kso08_gp11 + &kso09_gp10 + &kso10_gp07 + &kso11_gp06 + &kso12_gp05 + >; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts new file mode 100644 index 0000000000..8870f2e94f --- /dev/null +++ b/zephyr/projects/nissa/xivu_motionsense.dts @@ -0,0 +1,156 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + lsm6dso-int = &base_accel; + lis2dw12-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + label = "LID_MUTEX"; + }; + + base_mutex: base-mutex { + label = "BASE_MUTEX"; + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <(-1) 0 0 + 0 (-1) 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + lsm6dso_data: lsm6dso-drv-data { + compatible = "cros-ec,drvdata-lsm6dso"; + status = "okay"; + }; + + lis2dw12_data: lis2dw12-drv-data { + compatible = "cros-ec,drvdata-lis2dw12"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The label "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + */ + motionsense-sensor { + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; + status = "okay"; + + label = "Base Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + }; + + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; + status = "okay"; + + label = "Lid Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts new file mode 100644 index 0000000000..1ff3022124 --- /dev/null +++ b/zephyr/projects/nissa/xivu_overlay.dts @@ -0,0 +1,319 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: lgc { + compatible = "lgc,ap18c8k", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "lsm6dso_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_interrupt"; + }; + }; + + named-gpios { + gpio_sb_1: sb_1 { + gpios = <&gpio0 2 GPIO_PULL_UP>; + no-auto-init; + }; + + gpio_sb_2: sb_2 { + gpios = <&gpiod 4 GPIO_OUTPUT>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpiof 5 GPIO_INPUT>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* + * Input GPIO when used with type-C port 1 + * Output when used with HDMI sub-board + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + gpio-en-rails-odl = &gpio_sb_1; + /* + * Sub-board with type A USB, enable. + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HPD pins for HDMI sub-board. + */ + gpio-hdmi-en-odl = &gpio_sb_3; + gpio-hpd-odl = &gpio_sb_4; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "DDR and SOC"; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "Charger"; + enum-name = "TEMP_SENSOR_2"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + /* + * BC1.2 interrupt is shared with TCPC, so + * IRQ is not specified here and handled by + * usb_c0_interrupt. + */ + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + /* + * TODO(b:211693800): port1 may not be present on some + * sub-boards. + */ + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "intersil,isl923x"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &anx7483_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + anx7483_mux_1: anx7483-mux-1 { + compatible = "analogix,anx7483"; + port = <&i2c_ec_i2c_sub_usb_c1>; + i2c-addr-flags = "ANX7483_I2C_ADDR0_FLAGS"; + }; + }; + }; + + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm6 6 0 PWM_POLARITY_NORMAL>; + frequency = <10000>; + }; + + /* + * Set I2C pins for type C sub-board to be + * low voltage (I2C5_1). + * We do this for all boards, since the pins are + * 3.3V tolerant, and the only 2 types of sub-boards + * used on nivviks both have type-C ports on them. + */ + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + lvol-io-pads = <&lvol_iof5 &lvol_iof4>; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with + * 2714 mV full-scale reading on the ADC. Apply the largest possible + * multiplier (without overflowing int32) to get the best possible + * approximation of the actual ratio, but derate by a factor of two to + * ensure unexpectedly high values won't overflow. + */ + mul = <(791261 / 2)>; + div = <(651975 / 2)>; +}; + +/* Set bus speeds for I2C */ +&i2c0_0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; +}; + +&i2c1_0 { + label = "I2C_SENSOR"; + clock-frequency = ; +}; + +&i2c3_0 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; +}; + +&i2c5_1 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; +}; + +&i2c7_0 { + label = "I2C_BATTERY"; + clock-frequency = ; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu_power_signals.dts b/zephyr/projects/nissa/xivu_power_signals.dts new file mode 100644 index 0000000000..91876f0402 --- /dev/null +++ b/zephyr/projects/nissa/xivu_power_signals.dts @@ -0,0 +1,220 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpio4 0 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpio9 4 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpio9 7 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpio6 1 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioa 4 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpio4 3 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpio7 2 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpio3 7 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300 PWROK (from ADC)"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&cmp_pp3300_s5_high>; + trigger-low = <&cmp_pp3300_s5_low>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05 PWROK (from ADC)"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&cmp_pp1p05_high>; + trigger-low = <&cmp_pp1p05_low>; + }; + + adc-cmp { + cmp_pp3300_s5_high: pp3300_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + }; + cmp_pp3300_s5_low: pp3300_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 6>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <2448>; + }; + cmp_pp1p05_high: pp1p05_high { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_GREATER"; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + }; + cmp_pp1p05_low: pp1p05_low { + compatible = "nuvoton,adc-cmp"; + io-channels = <&adc0 4>; + comparison = "ADC_CMP_NPCX_LESS_OR_EQUAL"; + threshold-mv = <945>; + }; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_s4_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; diff --git a/zephyr/projects/nissa/xivu_pwm_leds.dts b/zephyr/projects/nissa/xivu_pwm_leds.dts new file mode 100644 index 0000000000..592275ff71 --- /dev/null +++ b/zephyr/projects/nissa/xivu_pwm_leds.dts @@ -0,0 +1,63 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>, + <&pwm0 0 0 PWM_POLARITY_INVERTED>, + <&pwm1 1 0 PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <324>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 5 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +/* Enable LEDs to work while CPU suspended */ + +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; -- cgit v1.2.1 From 535dec1f109e210d741c3c57d6db794378437b5f Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 16 Jun 2022 17:03:20 +0800 Subject: corsola: enable i2c-passthrough for eeprom port This is used by CBI for query EEPROM. BUG=b:236067475 TEST=pass firmware_ECCbiEeprom BRANCH=none Change-Id: Ia427d1d7bfacedb20496edbf2ec92f2759fcfac0 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3709278 Commit-Queue: Eric Yilun Lin Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin --- zephyr/projects/corsola/src/kingler/i2c.c | 4 +++- zephyr/projects/corsola/src/krabby/i2c.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/i2c.c b/zephyr/projects/corsola/src/kingler/i2c.c index 6236d42714..4687d3ace0 100644 --- a/zephyr/projects/corsola/src/kingler/i2c.c +++ b/zephyr/projects/corsola/src/kingler/i2c.c @@ -12,6 +12,8 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) { return (i2c_get_device_for_port(cmd_desc->port) == - i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY)); + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) || + i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_EEPROM)); } #endif diff --git a/zephyr/projects/corsola/src/krabby/i2c.c b/zephyr/projects/corsola/src/krabby/i2c.c index 3b5108e115..ac6daeadb0 100644 --- a/zephyr/projects/corsola/src/krabby/i2c.c +++ b/zephyr/projects/corsola/src/krabby/i2c.c @@ -12,6 +12,8 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) { return (i2c_get_device_for_port(cmd_desc->port) == - i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY)); + i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY) || + i2c_get_device_for_port(cmd_desc->port) == + i2c_get_device_for_port(I2C_PORT_EEPROM)); } #endif -- cgit v1.2.1 From f11a46100c1de26e810b80e45b9d74fb3ae8583e Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 10 Jun 2022 15:14:12 +0800 Subject: corsola: enable EC_CBI_WP This pin is added in rev1 boards. BUG=b:236067475 TEST=pass firmware_ECCbiEeprom BRANCH=none Change-Id: Ib64a241e385c8a01ebce96a937c9c23df681f5a5 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697824 Commit-Queue: Eric Yilun Lin Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin --- zephyr/projects/corsola/gpio_kingler.dts | 4 ++++ zephyr/projects/corsola/gpio_krabby.dts | 5 ++++- zephyr/projects/corsola/gpio_steelix.dts | 4 ++++ zephyr/projects/corsola/prj.conf | 3 +++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts index 0199f985fa..ea78d94f48 100644 --- a/zephyr/projects/corsola/gpio_kingler.dts +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -5,6 +5,7 @@ / { aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; gpio-wp = &gpio_ec_wp_l; gpio-kbd-kso2 = &gpio_ec_kso_02_inv; }; @@ -85,6 +86,9 @@ ec_pen_chg_dis_odl { gpios = <&gpioe 4 GPIO_INPUT>; }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 0 GPIO_OUTPUT_LOW>; + }; gpio_ec_wp_l: ec_wp_odl { gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; }; diff --git a/zephyr/projects/corsola/gpio_krabby.dts b/zephyr/projects/corsola/gpio_krabby.dts index 7246e8a40c..70ee4b8643 100644 --- a/zephyr/projects/corsola/gpio_krabby.dts +++ b/zephyr/projects/corsola/gpio_krabby.dts @@ -7,6 +7,7 @@ / { aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; gpio-wp = &ec_flash_wp_odl; }; @@ -56,6 +57,9 @@ gpios = <&gpioe 5 GPIO_INPUT>; enum-name = "GPIO_AC_PRESENT"; }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; ec_flash_wp_odl: ec_flash_wp_odl { gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | GPIO_ACTIVE_LOW)>; @@ -183,7 +187,6 @@ <&gpioa 3 GPIO_INPUT_PULL_DOWN>, <&gpioa 6 GPIO_INPUT_PULL_DOWN>, <&gpioa 7 GPIO_INPUT_PULL_DOWN>, - <&gpioc 3 GPIO_INPUT_PULL_DOWN>, <&gpiod 7 GPIO_INPUT_PULL_DOWN>, <&gpiof 1 GPIO_INPUT_PULL_DOWN>, <&gpioh 0 GPIO_INPUT_PULL_DOWN>, diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts index 3e0375564f..8332cea379 100644 --- a/zephyr/projects/corsola/gpio_steelix.dts +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -5,6 +5,7 @@ / { aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; gpio-wp = &gpio_ec_wp_l; gpio-kbd-kso2 = &gpio_ec_kso_02_inv; }; @@ -92,6 +93,9 @@ ec_pen_chg_dis_odl { gpios = <&gpioe 4 GPIO_INPUT>; }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpio8 0 GPIO_OUTPUT_LOW>; + }; gpio_ec_wp_l: ec_wp_odl { gpios = <&gpioe 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; }; diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index b26c01461e..677ce89117 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -35,3 +35,6 @@ CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y # Optional features CONFIG_FLASH_SHELL=n + +# EEPROM +CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y -- cgit v1.2.1 From 9243deb690c4210a25478616b1e74f7b9788c6eb Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Mon, 20 Jun 2022 16:05:24 +0800 Subject: corsola: enable USB_PORT_POWER_DUMB_CUSTOM_HOOK Enable this config for all Corsolas since the custom usb_a0_interrupt is implements for all devices too. BUG=b:235552939 TEST=make krabby & kingler BRANCH=none Signed-off-by: Ting Shen Change-Id: I16c7cee828adaca1aa079ae200dabbacc6c27f10 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3713278 Reviewed-by: Eric Yilun Lin Tested-by: Ting Shen Commit-Queue: Ting Shen --- zephyr/projects/corsola/prj.conf | 1 + zephyr/projects/corsola/prj_krabby.conf | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index 677ce89117..a49660c7cf 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -27,6 +27,7 @@ CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n CONFIG_PLATFORM_EC_USB_PD_USB4=n # TODO(b/226411332): fix single task USB_CHG for Corsola CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n +CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y # Power Seq CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y diff --git a/zephyr/projects/corsola/prj_krabby.conf b/zephyr/projects/corsola/prj_krabby.conf index 741f07b436..0cd8181b6d 100644 --- a/zephyr/projects/corsola/prj_krabby.conf +++ b/zephyr/projects/corsola/prj_krabby.conf @@ -129,7 +129,6 @@ CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y -CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n CONFIG_PLATFORM_EC_USB_PD_USB4=n -- cgit v1.2.1 From 9070742e52f8fe8d955de6ca941011116245e6ef Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Mon, 20 Jun 2022 14:59:27 +0800 Subject: mithrax: Implement a new battery parameter Mithrax configure a battery parameter. BUG=b:223737611 BRANCH=none TEST=Battery can be found via EC log check and battery can be cutoff by ectool command. Signed-off-by: johnwc_yeh Change-Id: I1428df5d7e5c902aa263fa67ca44d7713c8300d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3713881 Reviewed-by: Ricky Chang Reviewed-by: Ko Ko Commit-Queue: Ricky Chang --- board/mithrax/battery.c | 29 +++++++++++++++++++++++++++++ board/mithrax/board.h | 1 + 2 files changed, 30 insertions(+) diff --git a/board/mithrax/battery.c b/board/mithrax/battery.c index 8c03169b1c..b0d8a46f9f 100644 --- a/board/mithrax/battery.c +++ b/board/mithrax/battery.c @@ -87,6 +87,35 @@ const struct board_batt_params board_battery_info[] = { .discharging_max_c = 60, }, }, + [BATTERY_C340] = { + .fuel_gauge = { + .manuf_name = "AS3FXXD3KB", + .device_name = "C340152", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .reg_addr = 0x99, + .reg_mask = 0x000C, + .disconnect_val = 0x000C, + .cfet_mask = 0x0004, + .cfet_off_val = 0x0004, + } + }, + .batt_info = { + .voltage_max = 13350, + .voltage_normal = 11985, /* mV */ + .voltage_min = 9000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 45, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = -20, + .discharging_max_c = 60, + }, + }, }; BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); diff --git a/board/mithrax/board.h b/board/mithrax/board.h index c9d2112b2c..704904ffc4 100644 --- a/board/mithrax/board.h +++ b/board/mithrax/board.h @@ -231,6 +231,7 @@ enum ioex_port { enum battery_type { BATTERY_C536, BATTERY_C490, + BATTERY_C340, BATTERY_TYPE_COUNT }; -- cgit v1.2.1 From 81e5d3a539f0868bf5da57494fc6effa69caac25 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Fri, 17 Jun 2022 16:16:29 -0700 Subject: ectool: Bypass GEC_LOCK for COMM_USB interfaces COMM_USB does arbitration through libusb and doesn't need to acquire GEC_LOCK. This patch bypasses the lock. BUG=None BRANCH=None TEST=emerge-brya -j ec-utils, deploy on Vell, run ectool to interfact with kbmcu on usb. Signed-off-by: Parth Malkan Change-Id: I667166f3834f4c2d5fdec86f3b7f415becc1442b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712030 Reviewed-by: Daisuke Nojiri --- util/ectool.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/ectool.c b/util/ectool.c index 028828ebd5..51de0c1fcc 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -11030,7 +11030,10 @@ int main(int argc, char *argv[]) /* Prefer /dev method, which supports built-in mutex */ if (!(interfaces & COMM_DEV) || comm_init_dev(device_name)) { /* If dev is excluded or isn't supported, find alternative */ - if (acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) { + + /* Lock is not needed for COMM_USB */ + if (!(interfaces & COMM_USB) && + acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) { fprintf(stderr, "Could not acquire GEC lock.\n"); exit(1); } -- cgit v1.2.1 From 7a447a5589895ab45223c514067c888fe5e32917 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 15 Jun 2022 13:40:28 -0600 Subject: power: Drop support for Braswell power sequencing We don't have any supported Braswell boards remaining, delete the unused code. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Jack Rosenthal Change-Id: Ica4ce5c53e7e8a5b727ae23e9bcd3fbc411a594f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708434 Reviewed-by: Daisuke Nojiri --- docs/configuration/ap_power_sequencing.md | 2 +- include/config.h | 3 - power/braswell.c | 324 ------------------------------ power/build.mk | 1 - util/config_allowed.txt | 1 - 5 files changed, 1 insertion(+), 330 deletions(-) delete mode 100644 power/braswell.c diff --git a/docs/configuration/ap_power_sequencing.md b/docs/configuration/ap_power_sequencing.md index c5073d5809..ba9fc89f29 100644 --- a/docs/configuration/ap_power_sequencing.md +++ b/docs/configuration/ap_power_sequencing.md @@ -15,7 +15,7 @@ states (G3, S5, S3, S0, S0iX, etc). This includes the following tasks: The AP chipset options are grouped together in [config.h]. Select exactly one of the available AP chipset options (e.g. `CONFIG_CHIPSET_APOLLOLAKE`, -`CONFIG_CHIPSET_BRASWELL`, etc). If the AP chipset support is not available, +`CONFIG_CHIPSET_COMETLAKE`, etc). If the AP chipset support is not available, select `CONFIG_CHIPSET_ECDRIVEN` to enable basic support for handling S3 and S0 power states. diff --git a/include/config.h b/include/config.h index 523d94a8a8..931ea405d7 100644 --- a/include/config.h +++ b/include/config.h @@ -1401,7 +1401,6 @@ * chip */ #undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ -#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */ #undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ #undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ #undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), @@ -6258,7 +6257,6 @@ #undef CONFIG_CHIPSET_ALDERLAKE #undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 #undef CONFIG_CHIPSET_APOLLOLAKE -#undef CONFIG_CHIPSET_BRASWELL #undef CONFIG_CHIPSET_CANNONLAKE #undef CONFIG_CHIPSET_COMETLAKE #undef CONFIG_CHIPSET_GEMINILAKE @@ -6399,7 +6397,6 @@ #if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ defined(CONFIG_CHIPSET_APOLLOLAKE) || \ - defined(CONFIG_CHIPSET_BRASWELL) || \ defined(CONFIG_CHIPSET_CANNONLAKE) || \ defined(CONFIG_CHIPSET_COMETLAKE) || \ defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \ diff --git a/power/braswell.c b/power/braswell.c deleted file mode 100644 index dd2e3a8bb5..0000000000 --- a/power/braswell.c +++ /dev/null @@ -1,324 +0,0 @@ -/* Copyright 2014 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* X86 braswell chipset power control module for Chrome EC */ - -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "ec_commands.h" -#include "gpio.h" -#include "hooks.h" -#include "lid_switch.h" -#include "lpc.h" -#include "power.h" -#include "power_button.h" -#include "system.h" -#include "timer.h" -#include "usb_charge.h" -#include "util.h" -#include "wireless.h" -#include "registers.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) - -/* Input state flags */ -#define IN_RSMRST_L_PWRGD POWER_SIGNAL_MASK(X86_RSMRST_L_PWRGD) -#define IN_ALL_SYS_PWRGD POWER_SIGNAL_MASK(X86_ALL_SYS_PWRGD) -#define IN_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) - -/* All always-on supplies */ -#define IN_PGOOD_ALWAYS_ON (IN_RSMRST_L_PWRGD) -/* All non-core power rails */ -#define IN_PGOOD_ALL_NONCORE (IN_ALL_SYS_PWRGD) -/* All core power rails */ -#define IN_PGOOD_ALL_CORE (IN_ALL_SYS_PWRGD) -/* Rails required for S5 */ -#define IN_PGOOD_S5 (IN_PGOOD_ALWAYS_ON) -/* Rails required for S3 */ -#define IN_PGOOD_S3 (IN_PGOOD_ALWAYS_ON) -/* Rails required for S0 */ -#define IN_PGOOD_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE) - -/* All PM_SLP signals from PCH deasserted */ -#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED) -/* All inputs in the right state for S0 */ -#define IN_ALL_S0 (IN_PGOOD_S0 | IN_ALL_PM_SLP_DEASSERTED) - -static int throttle_cpu; /* Throttle CPU? */ -static int forcing_shutdown; /* Forced shutdown in progress? */ - -void chipset_force_shutdown(enum chipset_shutdown_reason reason) -{ - CPRINTS("%s(%d)", __func__, reason); - report_ap_reset(reason); - - /* - * Force power off. This condition will reset once the state machine - * transitions to G3. - */ -#ifndef CONFIG_PMIC - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); -#endif - gpio_set_level(GPIO_PCH_RSMRST_L, 0); - forcing_shutdown = 1; -} - -void chipset_reset(enum chipset_shutdown_reason reason) -{ - CPRINTS("%s: %d", __func__, reason); - report_ap_reset(reason); - - /* - * Send a reset pulse to the PCH. This just causes it to - * assert INIT# to the CPU without dropping power or asserting - * PLTRST# to reset the rest of the system. The PCH uses a 16 - * ms debounce time, so assert the signal for twice that. - */ - gpio_set_level(GPIO_PCH_RCIN_L, 0); - usleep(32 * MSEC); - gpio_set_level(GPIO_PCH_RCIN_L, 1); -} - -void chipset_throttle_cpu(int throttle) -{ -#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW - throttle = !throttle; -#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */ - if (chipset_in_state(CHIPSET_STATE_ON)) - gpio_set_level(GPIO_CPU_PROCHOT, throttle); -} - -enum power_state power_chipset_init(void) -{ - /* Pause in S5 when shutting down. */ - power_set_pause_in_s5(1); - - /* - * If we're switching between images without rebooting, see if the x86 - * is already powered on; if so, leave it there instead of cycling - * through G3. - */ - if (system_jumped_to_this_image()) { - if ((power_get_signals() & IN_PGOOD_S0) == IN_PGOOD_S0) { - /* Disable idle task deep sleep when in S0. */ - disable_sleep(SLEEP_MASK_AP_RUN); - - CPRINTS("already in S0"); - return POWER_S0; - } else { - /* Force all signals to their G3 states */ - CPRINTS("forcing G3"); - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - gpio_set_level(GPIO_PCH_RSMRST_L, 0); - - /*wireless_set_state(WIRELESS_OFF);*/ - } - } - - return POWER_G3; -} - -enum power_state power_handle_state(enum power_state state) -{ - switch (state) { - case POWER_G3: - break; - - case POWER_G3S5: - /* Exit SOC G3 */ -#ifdef CONFIG_PMIC - gpio_set_level(GPIO_PCH_SYS_PWROK, 1); -#else - gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 0); -#endif - CPRINTS("Exit SOC G3"); - - if (power_wait_signals(IN_PGOOD_S5)) { - chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT); - return POWER_G3; - } - - /* Deassert RSMRST# */ - gpio_set_level(GPIO_PCH_RSMRST_L, 1); - return POWER_S5; - - case POWER_S5: - /* Check for SLP S4 */ - if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1) - return POWER_S5S3; /* Power up to next state */ - break; - - case POWER_S5S3: - - /* Call hooks now that rails are up */ - hook_notify(HOOK_CHIPSET_STARTUP); - - return POWER_S3; - - - case POWER_S3: - - /* Check for state transitions */ - if (!power_has_signals(IN_PGOOD_S3)) { - /* Required rail went away */ - chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL); - return POWER_S3S5; - } else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) { - /* Power up to next state */ - return POWER_S3S0; - } else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) { - /* Power down to next state */ - return POWER_S3S5; - } - break; - - case POWER_S3S0: - /* Enable wireless */ - - /*wireless_set_state(WIRELESS_ON);*/ - - if (!power_has_signals(IN_PGOOD_S3)) { - chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL); - - /*wireless_set_state(WIRELESS_OFF);*/ - return POWER_S3S5; - } - - /* Call hooks now that rails are up */ - hook_notify(HOOK_CHIPSET_RESUME); - - /* - * Disable idle task deep sleep. This means that the low - * power idle task will not go into deep sleep while in S0. - */ - disable_sleep(SLEEP_MASK_AP_RUN); - - /* - * Wait 15 ms after all voltages good. 100 ms is only needed - * for PCIe devices; mini-PCIe devices should need only 10 ms. - */ - msleep(15); - - /* - * Throttle CPU if necessary. This should only be asserted - * when +VCCP is powered (it is by now). - */ -#ifdef CONFIG_CPU_PROCHOT_ACTIVE_LOW - gpio_set_level(GPIO_CPU_PROCHOT, !throttle_cpu); -#else - gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu); -#endif /* CONFIG_CPU_PROCHOT_ACTIVE_LOW */ - - /* Set SYS and CORE PWROK */ - gpio_set_level(GPIO_PCH_SYS_PWROK, 1); - - return POWER_S0; - - - case POWER_S0: - - if (!power_has_signals(IN_PGOOD_ALWAYS_ON)) { - chipset_force_shutdown(CHIPSET_SHUTDOWN_POWERFAIL); - return POWER_S0S3; - } - - if (!power_has_signals(IN_ALL_S0)) { - return POWER_S0S3; - } - - break; - case POWER_S0S3: - /* Call hooks before we remove power rails */ - hook_notify(HOOK_CHIPSET_SUSPEND); - -#ifndef CONFIG_PMIC - /* Clear SYS and CORE PWROK */ - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); -#endif - /* Wait 40ns */ - udelay(1); - - /* Suspend wireless */ - - /*wireless_set_state(WIRELESS_SUSPEND);*/ - - /* - * Enable idle task deep sleep. Allow the low power idle task - * to go into deep sleep in S3 or lower. - */ - enable_sleep(SLEEP_MASK_AP_RUN); - - /* - * Deassert prochot since CPU is off and we're about to drop - * +VCCP. - */ - gpio_set_level(GPIO_CPU_PROCHOT, 0); - - return POWER_S3; - - case POWER_S3S5: - - /* Call hooks before we remove power rails */ - hook_notify(HOOK_CHIPSET_SHUTDOWN); - - /*wireless_set_state(WIRELESS_OFF);*/ - - /* Call hooks after we remove power rails */ - hook_notify(HOOK_CHIPSET_SHUTDOWN_COMPLETE); - - /* Start shutting down */ - return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3; - - case POWER_S5G3: - /* - * in case shutdown is already done by apshutdown - * (or chipset_force_shutdown()), SOC already lost - * power and can't assert PMC_SUSPWRDNACK any more. - */ - if (forcing_shutdown) { - /* Config pins for SOC G3 */ - gpio_config_module(MODULE_GPIO, 1); -#ifndef CONFIG_PMIC - gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1); -#else - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); -#endif - - forcing_shutdown = 0; - - CPRINTS("Enter SOC G3"); - - return POWER_G3; - } - - if (gpio_get_level(GPIO_PCH_SUSPWRDNACK) == 1) { - /* Assert RSMRST# */ - gpio_set_level(GPIO_PCH_RSMRST_L, 0); - - /* Config pins for SOC G3 */ - gpio_config_module(MODULE_GPIO, 1); - - /* Enter SOC G3 */ -#ifdef CONFIG_PMIC - gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - udelay(1); - gpio_set_level(GPIO_PCH_RSMRST_L, 0); -#else - gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1); -#endif - CPRINTS("Enter SOC G3"); - - return POWER_G3; - } else { - CPRINTS("waiting for PMC_SUSPWRDNACK to assert!"); - return POWER_S5; - } - } - return state; -} diff --git a/power/build.mk b/power/build.mk index 82a55c14aa..ad1b3593cb 100644 --- a/power/build.mk +++ b/power/build.mk @@ -9,7 +9,6 @@ power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=alderlake_slg4bd44540.o power-$(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540)+=intel_x86.o power-$(CONFIG_CHIPSET_APL_GLK)+=apollolake.o intel_x86.o -power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o power-$(CONFIG_CHIPSET_COMETLAKE)+=cometlake.o intel_x86.o power-$(CONFIG_CHIPSET_COMETLAKE_DISCRETE)+=cometlake-discrete.o intel_x86.o diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 933f22a83c..d6f2f2f807 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -175,7 +175,6 @@ CONFIG_CHARGE_STATE_DEBUG CONFIG_CHIPSET_ALDERLAKE CONFIG_CHIPSET_APL_GLK CONFIG_CHIPSET_APOLLOLAKE -CONFIG_CHIPSET_BRASWELL CONFIG_CHIPSET_CANNONLAKE CONFIG_CHIPSET_CEZANNE CONFIG_CHIPSET_COMETLAKE -- cgit v1.2.1 From 660a6deb8bf112747637fc34f9ce0a1ae15f80cc Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Fri, 17 Jun 2022 10:16:45 -0600 Subject: test: Fix uses of fixture as 'this' Match upstream change to replace 'this' with 'fixture' to play nicer with C++. BRANCH=none BUG=none TEST=zmake test test-drivers Cq-Depend: chromium:3711728 Signed-off-by: Yuval Peress Change-Id: I1589c9c1796164d1b80b5a6b07177b2dc2e02aa9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712000 Reviewed-by: Abe Levkoy Reviewed-by: Al Semjonovs --- zephyr/test/drivers/src/console_cmd/accelinit.c | 2 +- zephyr/test/drivers/src/console_cmd/accelread.c | 6 +- zephyr/test/drivers/src/console_cmd/accelres.c | 2 +- .../test/drivers/src/console_cmd/charge_manager.c | 4 +- zephyr/test/drivers/src/console_cmd/charge_state.c | 16 +- zephyr/test/drivers/src/host_cmd/motion_sense.c | 22 +-- .../src/integration/usbc/usb_20v_3a_pd_charger.c | 8 +- .../src/integration/usbc/usb_5v_3a_pd_sink.c | 22 +-- .../src/integration/usbc/usb_5v_3a_pd_source.c | 64 +++---- .../drivers/src/integration/usbc/usb_alt_mode.c | 8 +- .../src/integration/usbc/usb_attach_src_snk.c | 28 +-- .../src/integration/usbc/usb_malfunction_sink.c | 58 +++--- .../drivers/src/integration/usbc/usb_pd_ctrl_msg.c | 26 +-- zephyr/test/drivers/src/ppc_syv682x.c | 201 +++++++++++---------- 14 files changed, 236 insertions(+), 231 deletions(-) diff --git a/zephyr/test/drivers/src/console_cmd/accelinit.c b/zephyr/test/drivers/src/console_cmd/accelinit.c index 24538ef648..f6e2a4ae38 100644 --- a/zephyr/test/drivers/src/console_cmd/accelinit.c +++ b/zephyr/test/drivers/src/console_cmd/accelinit.c @@ -80,7 +80,7 @@ ZTEST_USER(console_cmd_accelinit, test_state_was_set) ZTEST_USER_F(console_cmd_accelinit, test_fail_3_times) { mock_init_fake.return_val = 1; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; motion_sensors[0].state = SENSOR_INITIALIZED; zassert_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"), NULL); diff --git a/zephyr/test/drivers/src/console_cmd/accelread.c b/zephyr/test/drivers/src/console_cmd/accelread.c index 8ab9407dfe..02aae54f3a 100644 --- a/zephyr/test/drivers/src/console_cmd/accelread.c +++ b/zephyr/test/drivers/src/console_cmd/accelread.c @@ -96,9 +96,9 @@ int mock_read_call_super(const struct motion_sensor_t *s, int *v) ZTEST_USER_F(console_cmd_accelread, test_read) { - current_fixture = this; + current_fixture = fixture; mock_read_fake.custom_fake = mock_read_call_super; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"), NULL); zassert_equal(1, mock_read_fake.call_count, @@ -114,7 +114,7 @@ ZTEST_USER_F(console_cmd_accelread, test_read) ZTEST_USER_F(console_cmd_accelread, test_read_fail) { mock_read_fake.return_val = 1; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"), NULL); zassert_equal(1, mock_read_fake.call_count, diff --git a/zephyr/test/drivers/src/console_cmd/accelres.c b/zephyr/test/drivers/src/console_cmd/accelres.c index 72b52b1c58..62aebf51dd 100644 --- a/zephyr/test/drivers/src/console_cmd/accelres.c +++ b/zephyr/test/drivers/src/console_cmd/accelres.c @@ -112,7 +112,7 @@ ZTEST_USER_F(console_cmd_accelres, test_set_res__bad_res_value) int rv; set_resolution_fake.return_val = EC_ERROR_INVAL; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; rv = shell_execute_cmd(get_ec_shell(), "accelres 0 0"); zassert_equal(EC_ERROR_PARAM2, rv, "Expected %d, but got %d", EC_ERROR_PARAM2, rv); diff --git a/zephyr/test/drivers/src/console_cmd/charge_manager.c b/zephyr/test/drivers/src/console_cmd/charge_manager.c index c6e4821623..e9a3a8ca29 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_manager.c +++ b/zephyr/test/drivers/src/console_cmd/charge_manager.c @@ -129,8 +129,8 @@ ZTEST_USER_F(console_cmd_charge_manager, test_chgoverride_0_from_sink) /* TODO(b/214401892): Check why need to give time TCPM to spin */ k_sleep(K_SECONDS(1)); - connect_sink_to_port(this->charger_emul, this->tcpci_emul, - &this->sink_5v_3a); + connect_sink_to_port(fixture->charger_emul, fixture->tcpci_emul, + &fixture->sink_5v_3a); zassert_equal(shell_execute_cmd(get_ec_shell(), "chgoverride 0"), EC_ERROR_INVAL, NULL); } diff --git a/zephyr/test/drivers/src/console_cmd/charge_state.c b/zephyr/test/drivers/src/console_cmd/charge_state.c index 25c03928d4..f66aa518db 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_state.c +++ b/zephyr/test/drivers/src/console_cmd/charge_state.c @@ -205,8 +205,8 @@ ZTEST_SUITE(console_cmd_charge_state, drivers_predicate_post_main, ZTEST_USER_F(console_cmd_charge_state, test_idle_on_from_normal) { /* Connect a source so we start charging */ - connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1, - this->tcpci_emul, this->charger_emul); + connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1, + fixture->tcpci_emul, fixture->charger_emul); /* Verify that we're in "normal" mode */ zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL); @@ -219,8 +219,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_idle_on_from_normal) ZTEST_USER_F(console_cmd_charge_state, test_normal_from_idle) { /* Connect a source so we start charging */ - connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1, - this->tcpci_emul, this->charger_emul); + connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1, + fixture->tcpci_emul, fixture->charger_emul); /* Verify that we're in "normal" mode */ zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL); @@ -238,8 +238,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_normal_from_idle) ZTEST_USER_F(console_cmd_charge_state, test_discharge_on) { /* Connect a source so we start charging */ - connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1, - this->tcpci_emul, this->charger_emul); + connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1, + fixture->tcpci_emul, fixture->charger_emul); /* Verify that we're in "normal" mode */ zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL); @@ -253,8 +253,8 @@ ZTEST_USER_F(console_cmd_charge_state, test_discharge_on) ZTEST_USER_F(console_cmd_charge_state, test_discharge_off) { /* Connect a source so we start charging */ - connect_source_to_port(&this->source_5v_3a, &this->source_ext, 1, - this->tcpci_emul, this->charger_emul); + connect_source_to_port(&fixture->source_5v_3a, &fixture->source_ext, 1, + fixture->tcpci_emul, fixture->charger_emul); /* Verify that we're in "normal" mode */ zassume_equal(get_chg_ctrl_mode(), CHARGE_CONTROL_NORMAL, NULL); diff --git a/zephyr/test/drivers/src/host_cmd/motion_sense.c b/zephyr/test/drivers/src/host_cmd/motion_sense.c index 07952ed285..84bd0e8132 100644 --- a/zephyr/test/drivers/src/host_cmd/motion_sense.c +++ b/zephyr/test/drivers/src/host_cmd/motion_sense.c @@ -351,7 +351,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_range_error) struct ec_response_motion_sense response; mock_set_range_fake.return_val = 1; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; zassert_equal(EC_RES_INVALID_PARAM, host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4, @@ -366,7 +366,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_range) struct ec_response_motion_sense response; mock_set_range_fake.return_val = 0; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; zassert_ok(host_cmd_motion_sense_range(/*sensor_num=*/0, /*range=*/4, /*round_up=*/false, &response), @@ -423,7 +423,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_set) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_set_offset_fake.return_val = EC_RES_ERROR; zassert_equal(EC_RES_ERROR, @@ -440,7 +440,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_offset_fail_to_get) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_set_offset_fake.return_val = EC_RES_SUCCESS; mock_get_offset_fake.return_val = EC_RES_ERROR; @@ -461,7 +461,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_get_offset) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_get_offset_fake.return_val = EC_RES_SUCCESS; mock_set_offset_fake.return_val = EC_RES_SUCCESS; @@ -529,7 +529,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_get_scale_fail) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_get_scale_fake.return_val = 1; zassert_equal(1, @@ -546,7 +546,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_scale_fail) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_set_scale_fake.return_val = 1; zassert_equal(1, @@ -563,7 +563,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_set_get_scale) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_set_scale_fake.return_val = 0; mock_get_scale_fake.return_val = 0; @@ -604,7 +604,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib_fail) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_perform_calib_fake.return_val = 1; zassert_equal(1, @@ -619,7 +619,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib_success__fail_get_offset) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_perform_calib_fake.return_val = 0; mock_get_offset_fake.return_val = 1; @@ -636,7 +636,7 @@ ZTEST_USER_F(host_cmd_motion_sense, test_calib) { struct ec_response_motion_sense response; - motion_sensors[0].drv = &this->mock_drv; + motion_sensors[0].drv = &fixture->mock_drv; mock_perform_calib_fake.return_val = 0; mock_get_offset_fake.return_val = 0; diff --git a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c b/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c index 79cbb21b96..5a7c0c96f2 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c @@ -160,7 +160,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_battery_not_charging) struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD); uint16_t battery_status; - disconnect_charger_from_port(this); + disconnect_charger_from_port(fixture); zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS, &battery_status), NULL); @@ -172,7 +172,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_charge_state) { struct ec_response_charge_state charge_state; - disconnect_charger_from_port(this); + disconnect_charger_from_port(fixture); charge_state = host_cmd_charge_state(0); zassert_false(charge_state.get_state.ac, "AC_OK not triggered"); @@ -190,7 +190,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_typec_status) { struct ec_response_typec_status typec_status; - disconnect_charger_from_port(this); + disconnect_charger_from_port(fixture); typec_status = host_cmd_typec_status(0); zassert_false(typec_status.pd_enabled, NULL); @@ -208,7 +208,7 @@ ZTEST_F(usb_attach_20v_3a_pd_charger, test_disconnect_power_info) { struct ec_response_usb_pd_power_info power_info; - disconnect_charger_from_port(this); + disconnect_charger_from_port(fixture); power_info = host_cmd_power_info(0); zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED, diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c index 1cbdda49b0..8a1bb27edf 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c @@ -115,7 +115,7 @@ ZTEST_SUITE(usb_attach_5v_3a_pd_sink, drivers_predicate_post_main, ZTEST_F(usb_attach_5v_3a_pd_sink, test_partner_pd_completed) { - zassert_true(this->snk_ext.pd_completed, NULL); + zassert_true(fixture->snk_ext.pd_completed, NULL); } ZTEST(usb_attach_5v_3a_pd_sink, test_battery_is_discharging) @@ -180,7 +180,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_battery_discharging) sbat_emul_get_ptr(DT_DEP_ORD(DT_NODELABEL(battery))); uint16_t battery_status; - disconnect_sink_from_port(this); + disconnect_sink_from_port(fixture); zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS, &battery_status), NULL); @@ -192,7 +192,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_charge_state) { struct ec_response_charge_state charge_state; - disconnect_sink_from_port(this); + disconnect_sink_from_port(fixture); charge_state = host_cmd_charge_state(0); zassert_false(charge_state.get_state.ac, "AC_OK not triggered"); @@ -210,7 +210,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_typec_status) { struct ec_response_typec_status typec_status; - disconnect_sink_from_port(this); + disconnect_sink_from_port(fixture); typec_status = host_cmd_typec_status(0); zassert_false(typec_status.pd_enabled, NULL); @@ -228,7 +228,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_power_info) { struct ec_response_usb_pd_power_info power_info; - disconnect_sink_from_port(this); + disconnect_sink_from_port(fixture); power_info = host_cmd_power_info(0); zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED, @@ -270,7 +270,7 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_goto_min) pd_dpm_request(0, DPM_REQUEST_GOTO_MIN); k_sleep(K_SECONDS(1)); - zassert_true(this->snk_ext.pd_completed, NULL); + zassert_true(fixture->snk_ext.pd_completed, NULL); } /** @@ -286,12 +286,12 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_goto_min) */ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_ping_msg) { - tcpci_snk_emul_clear_ping_received(&this->snk_ext); + tcpci_snk_emul_clear_ping_received(&fixture->snk_ext); pd_dpm_request(0, DPM_REQUEST_SEND_PING); k_sleep(K_USEC(PD_T_SOURCE_ACTIVITY)); - zassert_true(this->snk_ext.ping_received, NULL); + zassert_true(fixture->snk_ext.ping_received, NULL); } /** @@ -309,10 +309,10 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_ping_msg) */ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_alert_msg) { - tcpci_snk_emul_clear_alert_received(&this->snk_ext); - zassert_false(this->snk_ext.alert_received, NULL); + tcpci_snk_emul_clear_alert_received(&fixture->snk_ext); + zassert_false(fixture->snk_ext.alert_received, NULL); zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL); k_sleep(K_SECONDS(2)); - zassert_true(this->snk_ext.alert_received, NULL); + zassert_true(fixture->snk_ext.alert_received, NULL); } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c index 39745dd70b..95e3b47feb 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c @@ -145,7 +145,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_battery_not_charging) struct i2c_emul *i2c_emul = sbat_emul_get_ptr(BATTERY_ORD); uint16_t battery_status; - disconnect_source_from_port(this->tcpci_emul, this->charger_emul); + disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul); zassert_ok(sbat_emul_get_word_val(i2c_emul, SB_BATTERY_STATUS, &battery_status), NULL); @@ -157,7 +157,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_charge_state) { struct ec_response_charge_state charge_state; - disconnect_source_from_port(this->tcpci_emul, this->charger_emul); + disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul); charge_state = host_cmd_charge_state(0); zassert_false(charge_state.get_state.ac, "AC_OK not triggered"); @@ -175,7 +175,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_typec_status) { struct ec_response_typec_status typec_status; - disconnect_source_from_port(this->tcpci_emul, this->charger_emul); + disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul); typec_status = host_cmd_typec_status(0); zassert_false(typec_status.pd_enabled, NULL); @@ -193,7 +193,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info) { struct ec_response_usb_pd_power_info power_info; - disconnect_source_from_port(this->tcpci_emul, this->charger_emul); + disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul); power_info = host_cmd_power_info(0); zassert_equal(power_info.role, USB_PD_PORT_POWER_DISCONNECTED, @@ -222,10 +222,10 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info) ZTEST_F(usb_attach_5v_3a_pd_source, verify_dock_with_power_button) { /* Clear Alert and Status receive checks */ - tcpci_src_emul_clear_alert_received(&this->src_ext); - tcpci_src_emul_clear_status_received(&this->src_ext); - zassert_false(this->src_ext.alert_received, NULL); - zassert_false(this->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); /* Setting up revision for the full Status message */ prl_set_rev(TEST_USB_PORT, TCPCI_MSG_SOP, PD_REV30); @@ -236,40 +236,40 @@ ZTEST_F(usb_attach_5v_3a_pd_source, verify_dock_with_power_button) /* Suspend and check partner received Alert and Status messages */ hook_notify(HOOK_CHIPSET_SUSPEND); k_sleep(K_SECONDS(2)); - zassert_true(this->src_ext.alert_received, NULL); - zassert_true(this->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&this->src_ext); - tcpci_src_emul_clear_status_received(&this->src_ext); - zassert_false(this->src_ext.alert_received, NULL); - zassert_false(this->src_ext.status_received, NULL); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); /* Shutdown and check partner received Alert and Status messages */ hook_notify(HOOK_CHIPSET_SHUTDOWN); k_sleep(K_SECONDS(2)); - zassert_true(this->src_ext.alert_received, NULL); - zassert_true(this->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&this->src_ext); - tcpci_src_emul_clear_status_received(&this->src_ext); - zassert_false(this->src_ext.alert_received, NULL); - zassert_false(this->src_ext.status_received, NULL); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); /* Startup and check partner received Alert and Status messages */ hook_notify(HOOK_CHIPSET_STARTUP); k_sleep(K_SECONDS(2)); - zassert_true(this->src_ext.alert_received, NULL); - zassert_true(this->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&this->src_ext); - tcpci_src_emul_clear_status_received(&this->src_ext); - zassert_false(this->src_ext.alert_received, NULL); - zassert_false(this->src_ext.status_received, NULL); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); /* Resume and check partner received Alert and Status messages */ hook_notify(HOOK_CHIPSET_RESUME); k_sleep(K_SECONDS(2)); - zassert_true(this->src_ext.alert_received, NULL); - zassert_true(this->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&this->src_ext); - tcpci_src_emul_clear_status_received(&this->src_ext); - zassert_false(this->src_ext.alert_received, NULL); - zassert_false(this->src_ext.status_received, NULL); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index fadb595e4b..2123d26092 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -134,12 +134,12 @@ ZTEST_F(usbc_alt_mode, verify_discovery) /* The host command does not count the VDM header in identity_count. */ zassert_equal(discovery->identity_count, - this->partner.identity_vdos - 1, + fixture->partner.identity_vdos - 1, "Expected %d identity VDOs, got %d", - this->partner.identity_vdos - 1, + fixture->partner.identity_vdos - 1, discovery->identity_count); zassert_mem_equal(discovery->discovery_vdo, - this->partner.identity_vdm + 1, + fixture->partner.identity_vdm + 1, discovery->identity_count * sizeof(*discovery->discovery_vdo), "Discovered SOP identity ACK did not match"); @@ -152,7 +152,7 @@ ZTEST_F(usbc_alt_mode, verify_discovery) "Expected 1 DP mode, got %d", discovery->svids[0].mode_count); zassert_equal(discovery->svids[0].mode_vdo[0], - this->partner.modes_vdm[1], + fixture->partner.modes_vdm[1], "DP mode VDOs did not match"); } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c index 31d5c329b1..e88aedd6e3 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c @@ -605,15 +605,15 @@ static void usb_detach_test_after(void *state) ZTEST_F(usb_detach_test, verify_detach_src_snk) { - struct emul_state *fixture = &this->fixture; + struct emul_state *emul_state = &fixture->fixture; struct ec_response_usb_pd_power_info src_power_info = { 0 }; struct ec_response_usb_pd_power_info snk_power_info = { 0 }; - integration_usb_test_source_detach(fixture); - integration_usb_test_sink_detach(fixture); + integration_usb_test_source_detach(emul_state); + integration_usb_test_sink_detach(emul_state); k_sleep(K_SECONDS(10)); - isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0); + isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0); snk_power_info = host_cmd_power_info(SNK_PORT); src_power_info = host_cmd_power_info(SRC_PORT); @@ -667,15 +667,15 @@ ZTEST_F(usb_detach_test, verify_detach_src_snk) ZTEST_F(usb_detach_test, verify_detach_snk_src) { - struct emul_state *fixture = &this->fixture; + struct emul_state *emul_state = &fixture->fixture; struct ec_response_usb_pd_power_info src_power_info = { 0 }; struct ec_response_usb_pd_power_info snk_power_info = { 0 }; - integration_usb_test_sink_detach(fixture); - integration_usb_test_source_detach(fixture); + integration_usb_test_sink_detach(emul_state); + integration_usb_test_source_detach(emul_state); k_sleep(K_SECONDS(10)); - isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0); + isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0); snk_power_info = host_cmd_power_info(SNK_PORT); src_power_info = host_cmd_power_info(SRC_PORT); @@ -729,12 +729,12 @@ ZTEST_F(usb_detach_test, verify_detach_snk_src) ZTEST_F(usb_detach_test, verify_detach_sink) { - struct emul_state *fixture = &this->fixture; + struct emul_state *emul_state = &fixture->fixture; struct ec_response_usb_pd_power_info pd_power_info = { 0 }; - integration_usb_test_sink_detach(fixture); + integration_usb_test_sink_detach(emul_state); k_sleep(K_SECONDS(10)); - isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0); + isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0); pd_power_info = host_cmd_power_info(SNK_PORT); @@ -771,12 +771,12 @@ ZTEST_F(usb_detach_test, verify_detach_sink) ZTEST_F(usb_detach_test, verify_detach_source) { - struct emul_state *fixture = &this->fixture; + struct emul_state *emul_state = &fixture->fixture; struct ec_response_usb_pd_power_info pd_power_info = { SNK_PORT }; - integration_usb_test_source_detach(fixture); + integration_usb_test_source_detach(emul_state); k_sleep(K_SECONDS(10)); - isl923x_emul_set_adc_vbus(fixture->charger_isl923x_emul, 0); + isl923x_emul_set_adc_vbus(emul_state->charger_isl923x_emul, 0); pd_power_info = host_cmd_power_info(SNK_PORT); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c index c3788791e2..7c46abc34f 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c @@ -121,12 +121,12 @@ ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable) * Fail on SourceCapabilities message to make TCPM change PD port state * to disabled */ - this->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; - this->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext, - &this->actions[0]); + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; + fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); - connect_sink_to_port(this); + connect_sink_to_port(fixture); typec_status = host_cmd_typec_status(0); @@ -145,12 +145,12 @@ ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect) * Fail only few times on SourceCapabilities message to prevent entering * PE_SRC_Disabled state by TCPM */ - this->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; - this->actions[0].count = 3; - tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext, - &this->actions[0]); + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; + fixture->actions[0].count = 3; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); - connect_sink_to_port(this); + connect_sink_to_port(fixture); typec_status = host_cmd_typec_status(0); @@ -191,23 +191,23 @@ ZTEST_F(usb_malfunction_sink, test_ignore_source_cap) bool expect_hard_reset = false; int msg_cnt = 0; - this->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; - this->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext, - &this->actions[0]); + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; + fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); - tcpci_partner_common_enable_pd_logging(&this->sink, true); - connect_sink_to_port(this); - tcpci_partner_common_enable_pd_logging(&this->sink, false); + tcpci_partner_common_enable_pd_logging(&fixture->sink, true); + connect_sink_to_port(fixture); + tcpci_partner_common_enable_pd_logging(&fixture->sink, false); /* * If test is failing, printing logged message may be useful to diagnose * problem: - * tcpci_partner_common_print_logged_msgs(&this->sink); + * tcpci_partner_common_print_logged_msgs(&fixture->sink); */ /* Check if SourceCapability message alternate with HardReset */ - SYS_SLIST_FOR_EACH_CONTAINER(&this->sink.msg_log, msg, node) { + SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node) { if (expect_hard_reset) { zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET, "Expected message %d to be hard reset", @@ -239,16 +239,16 @@ ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable) * Ignore first SourceCapabilities message and discard others by sending * different messages. This will lead to PD disable. */ - this->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; - this->actions[0].count = 1; - tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext, - &this->actions[0]); - this->actions[1].action_mask = TCPCI_FAULTY_SNK_DISCARD_SRC_CAP; - this->actions[1].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&this->faulty_snk_ext, - &this->actions[1]); - - connect_sink_to_port(this); + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; + fixture->actions[0].count = 1; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); + fixture->actions[1].action_mask = TCPCI_FAULTY_SNK_DISCARD_SRC_CAP; + fixture->actions[1].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[1]); + + connect_sink_to_port(fixture); typec_status = host_cmd_typec_status(0); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c index dd4c805590..6aee4b86d8 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c @@ -166,7 +166,7 @@ ZTEST_SUITE(usb_pd_ctrl_msg_test_source, drivers_predicate_post_main, ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap) { - struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture; + struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; struct ec_response_typec_status snk_resp = { 0 }; int rv = 0; @@ -176,7 +176,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap) "SNK Returned vconn_role=%u", snk_resp.vconn_role); /* Send VCONN_SWAP request */ - rv = tcpci_partner_send_control_msg(&fixture->partner_emul, + rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul, PD_CTRL_VCONN_SWAP, 0); zassert_ok(rv, "Failed to send VCONN_SWAP request, rv=%d", rv); @@ -189,7 +189,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_vconn_swap) ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_pr_swap) { - struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture; + struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; struct ec_response_typec_status snk_resp = { 0 }; int rv = 0; @@ -201,16 +201,16 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_pr_swap) /* Ignore ACCEPT in common handler for PR Swap request, * causes soft reset */ - tcpci_partner_common_handler_mask_msg(&fixture->partner_emul, + tcpci_partner_common_handler_mask_msg(&super_fixture->partner_emul, PD_CTRL_ACCEPT, true); /* Send PR_SWAP request */ - rv = tcpci_partner_send_control_msg(&fixture->partner_emul, + rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul, PD_CTRL_PR_SWAP, 0); zassert_ok(rv, "Failed to send PR_SWAP request, rv=%d", rv); /* Send PS_RDY request */ - rv = tcpci_partner_send_control_msg(&fixture->partner_emul, + rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul, PD_CTRL_PS_RDY, 15); zassert_ok(rv, "Failed to send PS_RDY request, rv=%d", rv); @@ -255,7 +255,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_sink, verify_dr_swap) */ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_dr_swap_rejected) { - struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture; + struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; struct ec_response_typec_status typec_status = { 0 }; int rv = 0; @@ -264,7 +264,7 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_dr_swap_rejected) "Returned data_role=%u", typec_status.data_role); /* Send DR_SWAP request */ - rv = tcpci_partner_send_control_msg(&fixture->partner_emul, + rv = tcpci_partner_send_control_msg(&super_fixture->partner_emul, PD_CTRL_DR_SWAP, 0); zassert_ok(rv, "Failed to send DR_SWAP request, rv=%d", rv); @@ -359,10 +359,10 @@ ZTEST(usb_pd_ctrl_msg_test_sink, verify_get_sink_cap) */ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_mode2) { - struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture; + struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0); - tcpci_partner_send_data_msg(&fixture->partner_emul, + tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST, &bdo, 1, 0); pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX); @@ -386,17 +386,17 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_mode2) */ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_test_data) { - struct usb_pd_ctrl_msg_test_fixture *fixture = &this->fixture; + struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; uint32_t bdo = BDO(BDO_MODE_TEST_DATA, 0); - tcpci_partner_send_data_msg(&fixture->partner_emul, + tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST, &bdo, 1, 0); pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX); k_sleep(K_SECONDS(5)); zassert_equal(get_state_pe(TEST_USB_PORT), PE_BIST_TX, NULL); - tcpci_partner_common_send_hard_reset(&fixture->partner_emul); + tcpci_partner_common_send_hard_reset(&super_fixture->partner_emul); k_sleep(K_SECONDS(1)); zassert_equal(get_state_pe(TEST_USB_PORT), PE_SNK_READY, NULL); } diff --git a/zephyr/test/drivers/src/ppc_syv682x.c b/zephyr/test/drivers/src/ppc_syv682x.c index aa08c26745..86f97bbb21 100644 --- a/zephyr/test/drivers/src/ppc_syv682x.c +++ b/zephyr/test/drivers/src/ppc_syv682x.c @@ -114,14 +114,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_dead_battery) * With a dead battery, the device powers up sinking VBUS, and the * driver should keep that going. */ - zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, SYV682X_CONTROL_1_CH_SEL), NULL); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_5V, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_5V, SYV682X_CONTROL_4_NONE); zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, "Dead battery init, but CH_SEL set to 5V power path"); @@ -137,14 +138,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_vsafe0v) uint8_t reg; /* With VBUS at vSafe0V, init should set the default configuration. */ - zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, SYV682X_CONTROL_1_PWR_ENB), NULL); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V, SYV682X_CONTROL_4_NONE); zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); check_control_1_default_init(reg); } @@ -154,14 +156,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_sink_disabled) uint8_t reg; /* With sink disabled, init should do the same thing. */ - zassume_ok(syv682x_emul_set_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, + zassume_ok(syv682x_emul_set_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, SYV682X_CONTROL_1_CH_SEL), NULL); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V, SYV682X_CONTROL_4_NONE); zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); check_control_1_default_init(reg); } @@ -172,8 +175,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common) int ilim; zassert_ok(ppc_init(syv682x_port), "PPC init failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); /* @@ -181,14 +184,14 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common) * current limit according to configuration, set over-current, over- * voltage, and discharge parameters appropriately, and enable CC lines. */ - zassert_equal(gpio_emul_output_get(this->frs_en_gpio_port, - this->frs_en_gpio_pin), + zassert_equal(gpio_emul_output_get(fixture->frs_en_gpio_port, + fixture->frs_en_gpio_pin), 0, "FRS enabled, but FRS GPIO not asserted"); ilim = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; zassert_equal(ilim, CONFIG_PLATFORM_EC_USB_PD_PULLUP, "Default init, but 5V current limit set to %d", ilim); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_2_REG, ®), NULL); zassert_equal(reg, (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) | @@ -196,15 +199,15 @@ ZTEST_F(ppc_syv682x, test_syv682x_init_common) << SYV682X_DSG_RON_SHIFT) | (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT), "Default init, but CONTROL_2 is 0x%x", reg); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_3_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_3_REG, ®), NULL); zassert_equal(reg, (SYV682X_OVP_23_7 << SYV682X_OVP_BIT_SHIFT) | SYV682X_RVS_MASK, "Default init, but CONTROL_3 is 0x%x", reg); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), NULL); zassert_equal(reg & ~SYV682X_CONTROL_4_INT_MASK, SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS, @@ -217,8 +220,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_source_enable) zassert_ok(ppc_vbus_source_enable(syv682x_port, true), "VBUS enable failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, "VBUS sourcing enabled but power path disabled"); @@ -239,7 +242,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_source_oc) zassume_ok(ppc_vbus_source_enable(syv682x_port, true), "VBUS enable failed"); /* An OC event less than 100 ms should not cause VBUS to turn off. */ - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_5V, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_5V, SYV682X_CONTROL_4_NONE); msleep(50); zassert_true(ppc_is_sourcing_vbus(syv682x_port), @@ -259,7 +262,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_tsd) */ zassume_ok(ppc_vbus_source_enable(syv682x_port, true), "Source enable failed"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_TSD, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_TSD, SYV682X_CONTROL_4_NONE); msleep(1); zassert_false(ppc_is_sourcing_vbus(syv682x_port), @@ -271,7 +274,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_ovp) /* An OVP event should cause the driver to disable the source path. */ zassume_ok(ppc_vbus_source_enable(syv682x_port, true), "Source enable failed"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OVP, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OVP, SYV682X_CONTROL_4_NONE); msleep(1); zassert_false(ppc_is_sourcing_vbus(syv682x_port), @@ -289,29 +292,29 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vbus_hv_oc) */ zassume_ok(ppc_vbus_sink_enable(syv682x_port, true), "Sink enable failed"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV, SYV682X_CONTROL_4_NONE); msleep(1); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, "Power path disabled after HV_OC handled"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV, SYV682X_CONTROL_4_NONE); /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ msleep(15); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, 0, "Power path disabled after HV_OC handled"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_OC_HV, SYV682X_CONTROL_4_NONE); /* Alert GPIO doesn't change so wait for delayed syv682x interrupt */ msleep(15); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); zassert_equal(reg & SYV682X_CONTROL_1_PWR_ENB, SYV682X_CONTROL_1_PWR_ENB, @@ -327,18 +330,18 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc) * VCONN off. */ ppc_set_vconn(syv682x_port, true); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_VCONN_OCP); msleep(1); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), "VCONN disabled after initial VCONN OC"); msleep(50); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_true(reg & (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), @@ -348,8 +351,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_oc) * should turn VCONN off. */ msleep(60); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_false(reg & (SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2), @@ -367,11 +370,11 @@ ZTEST_F(ppc_syv682x, test_syv682x_interrupt_vconn_ov) * driver should then run generic CC over-voltage handling. */ ppc_set_vconn(syv682x_port, true); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_VBAT_OVP); msleep(1); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_true(reg & SYV682X_CONTROL_4_CC1_BPS, "CC1 disabled after handling VBAT_OVP"); @@ -397,10 +400,10 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_enable) "PPC is sourcing VBUS after sink enabled"); ppc_set_polarity(syv682x_port, 0 /* CC1 */); ppc_set_frs_enable(syv682x_port, true); - zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 1, - "FRS enabled, but FRS GPIO not asserted"); - zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin), + 1, "FRS enabled, but FRS GPIO not asserted"); + zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_equal( reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), @@ -420,10 +423,10 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_disable) ppc_set_polarity(syv682x_port, 0 /* CC1 */); ppc_set_frs_enable(syv682x_port, false); - zassert_equal(gpio_emul_output_get(gpio_dev, this->frs_en_gpio_pin), 0, - "FRS disabled, but FRS GPIO not deasserted"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_4_REG, - ®), + zassert_equal(gpio_emul_output_get(gpio_dev, fixture->frs_en_gpio_pin), + 0, "FRS disabled, but FRS GPIO not deasserted"); + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_4_REG, ®), "Reading CONTROL_4 failed"); zassert_equal( reg & (SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS), @@ -437,12 +440,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_frs_trigger) * An FRS event when the PPC is Sink should cause the PPC to switch from * Sink to Source. */ - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_FRS, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_FRS, SYV682X_CONTROL_4_NONE); msleep(1); zassert_true(ppc_is_sourcing_vbus(syv682x_port), "PPC is not sourcing VBUS after FRS signal handled"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_NONE); } @@ -454,8 +457,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_usb_default) zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, TYPEC_RP_USB), "Could not set source current limit"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; zassert_equal(reg & SYV682X_5V_ILIM_MASK, SYV682X_5V_ILIM_1_25, @@ -470,8 +473,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_1500ma) zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, TYPEC_RP_1A5), "Could not set source current limit"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; zassert_equal(ilim_val, SYV682X_5V_ILIM_1_75, @@ -486,8 +489,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_source_current_limit_3000ma) zassert_ok(ppc_set_vbus_source_current_limit(syv682x_port, TYPEC_RP_3A0), "Could not set source current limit"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), "Reading CONTROL_1 failed"); ilim_val = (reg & SYV682X_5V_ILIM_MASK) >> SYV682X_5V_ILIM_BIT_SHIFT; zassert_equal(ilim_val, SYV682X_5V_ILIM_3_30, @@ -503,7 +506,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_write_busy) * timeout. It is not a goal of this test to verify the frequency of * polling or the exact value of the timeout. */ - syv682x_emul_set_busy_reads(this->ppc_emul, 1000); + syv682x_emul_set_busy_reads(fixture->ppc_emul, 1000); zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, TYPEC_RP_USB), EC_ERROR_TIMEOUT, "SYV682 busy, but write completed"); @@ -514,12 +517,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_write_busy) * If the busy bit clears before the driver reaches its timeout, the * write should succeed. */ - syv682x_emul_set_busy_reads(this->ppc_emul, 1); + syv682x_emul_set_busy_reads(fixture->ppc_emul, 1); zassert_equal(ppc_set_vbus_source_current_limit(syv682x_port, TYPEC_RP_USB), 0, "SYV682 not busy, but write failed"); - syv682x_emul_set_busy_reads(this->ppc_emul, 0); + syv682x_emul_set_busy_reads(fixture->ppc_emul, 0); } ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected) @@ -528,16 +531,16 @@ ZTEST_F(ppc_syv682x, test_syv682x_dev_is_connected) zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_SRC), "Could not connect device as source"); - zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, - ®), + zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_2_REG, ®), "Reading CONTROL_2 failed"); zassert_false(reg & SYV682X_CONTROL_2_FDSG, "Connected as source, but force discharge enabled"); zassert_ok(ppc_dev_is_connected(syv682x_port, PPC_DEV_DISCONNECTED), "Could not disconnect device"); - zassert_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_2_REG, - ®), + zassert_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_2_REG, ®), "Reading CONTROL_2 failed"); zassert_true(reg & SYV682X_CONTROL_2_FDSG, "Disconnected, but force discharge disabled"); @@ -571,8 +574,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_enable_power_path) "VBUS enable failed"); zassert_ok(ppc_vbus_sink_enable(syv682x_port, true), "Sink disable failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); zassert_true(reg & SYV682X_CONTROL_1_CH_SEL, "Sink enabled, but CH_SEL set to 5V power path"); @@ -596,8 +599,8 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_disable) zassert_ok(ppc_vbus_sink_enable(syv682x_port, false), "Sink disable failed"); - zassume_ok(syv682x_emul_get_reg(this->ppc_emul, SYV682X_CONTROL_1_REG, - ®), + zassume_ok(syv682x_emul_get_reg(fixture->ppc_emul, + SYV682X_CONTROL_1_REG, ®), NULL); zassert_true(reg & SYV682X_CONTROL_1_PWR_ENB, "Sink disabled, but power path enabled"); @@ -613,11 +616,12 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit) * cleared by sink disable. */ for (int i = 0; i < 4; ++i) { - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_OC_HV, + syv682x_emul_set_condition(fixture->ppc_emul, + SYV682X_STATUS_OC_HV, SYV682X_CONTROL_4_NONE); msleep(15); } - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_NONE); zassert_not_equal(ppc_vbus_sink_enable(syv682x_port, true), EC_SUCCESS, @@ -633,7 +637,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_vbus_sink_oc_limit) ZTEST_F(ppc_syv682x, test_syv682x_set_vconn) { - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_VBAT_OVP); zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, "VBAT OVP, but ppc_set_vconn succeeded"); @@ -670,10 +674,11 @@ static int mock_read_intercept_reg_fail(struct i2c_emul *emul, int reg, ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_status) { /* Failed STATUS read should cause init to fail. */ - i2c_common_emul_set_read_fail_reg(this->ppc_emul, SYV682X_STATUS_REG); + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, + SYV682X_STATUS_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "STATUS read error, but init succeeded"); - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); } @@ -686,7 +691,7 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1) }; /* Failed CONTROL_1 read */ - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_1_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_1 read error, but init succeeded"); @@ -704,34 +709,34 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1) "succeeded"); zassert_ok(drv->reg_dump(syv682x_port), "CONTROL_1 read error, and ppc_dump failed"); - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Init reads CONTROL_1 several times. The 3rd read happens while * setting the source current limit. Check that init fails when that * read fails. */ - i2c_common_emul_set_read_func(this->ppc_emul, + i2c_common_emul_set_read_func(fixture->ppc_emul, &mock_read_intercept_reg_fail, ®_fail); reg_fail.reg_access_to_fail = SYV682X_CONTROL_1_REG; reg_fail.reg_access_fail_countdown = 3; zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_1 read error, but init succeeded"); - i2c_common_emul_set_read_func(this->ppc_emul, NULL, NULL); + i2c_common_emul_set_read_func(fixture->ppc_emul, NULL, NULL); /* Failed CONTROL_1 write */ - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_1_REG); /* During init, the driver will write CONTROL_1 either to disable all * power paths (normal case) or to enable the sink path (dead battery * case). vSafe0V in STATUS is one indication of the normal case. */ - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_VSAFE_0V, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_VSAFE_0V, SYV682X_CONTROL_4_NONE); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_1 write error, but init succeeded"); - syv682x_emul_set_condition(this->ppc_emul, SYV682X_STATUS_NONE, + syv682x_emul_set_condition(fixture->ppc_emul, SYV682X_STATUS_NONE, SYV682X_CONTROL_4_NONE); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_1 write error, but init succeeded"); @@ -740,65 +745,65 @@ ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_1) EC_SUCCESS, "CONTROL_1 write error, but VBUS source " "enable succeeded"); - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); } ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_2) { /* Failed CONTROL_2 read */ - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_2_REG); zassert_not_equal(ppc_discharge_vbus(syv682x_port, true), EC_SUCCESS, "CONTROL_2 read error, but VBUS discharge succeeded"); - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Failed CONTROL_2 write */ - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_2_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_2 write error, but init succeeded"); - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); } ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_3) { /* Failed CONTROL_3 read */ - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_3_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_3 read error, but VBUS discharge succeeded"); - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Failed CONTROL_3 write */ - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_3_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_3 write error, but init succeeded"); - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); } ZTEST_F(ppc_syv682x, test_syv682x_i2c_error_control_4) { /* Failed CONTROL_4 read */ - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_4_REG); zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, "CONTROL_2 read error, but VCONN set succeeded"); - i2c_common_emul_set_read_fail_reg(this->ppc_emul, + i2c_common_emul_set_read_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Failed CONTROL_4 write */ - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, SYV682X_CONTROL_4_REG); zassert_not_equal(ppc_init(syv682x_port), EC_SUCCESS, "CONTROL_4 write error, but init succeeded"); zassert_not_equal(ppc_set_vconn(syv682x_port, true), EC_SUCCESS, "CONTROL_4 write error, but VCONN set succeeded"); - i2c_common_emul_set_write_fail_reg(this->ppc_emul, + i2c_common_emul_set_write_fail_reg(fixture->ppc_emul, I2C_COMMON_EMUL_NO_FAIL_REG); } -- cgit v1.2.1 From 5fed947f164bcc0f94881d6343023edb7726ee6f Mon Sep 17 00:00:00 2001 From: "amber.chen" Date: Tue, 14 Jun 2022 18:46:10 +0800 Subject: taeko: remove CONFIG_CMD_POWERINDEBUG configuration remove CONFIG_CMD_POWERINDEBUG configuration BUG=b:235281906 BRANCH=main TEST=make buildall -j48 Signed-off-by: amber.chen Change-Id: Ie74e7beda4c7df42d814fe7a28f3d93bd7f41105 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705457 Reviewed-by: caveh jalali --- board/taeko/board.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/taeko/board.h b/board/taeko/board.h index a6395ffc61..67cd95d648 100644 --- a/board/taeko/board.h +++ b/board/taeko/board.h @@ -111,6 +111,8 @@ /* The lower the input voltage, the higher the power efficiency. */ #define PD_PREFER_LOW_VOLTAGE +#undef CONFIG_CMD_POWERINDEBUG + /* * Macros for GPIO signals used in common code that don't match the * schematic names. Signal names in gpio.inc match the schematic and are -- cgit v1.2.1 From bb51e6d0224eab2231730049e4950dc122f44e72 Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Mon, 13 Jun 2022 11:42:55 +0530 Subject: ap_pwrseq: s5 inactivity timeout handling current implementaion restarts the s5 inaciver timer after if expires which delays the S5 to G3 transition. Problem is seen when the S5 inactive timer expiry is not read immdediatly after it expires and instaed reading the timer remaining status which returns zero indicating timer has not started at all. Hence it starts the inactive timer again. This is solved by introducing a static global which captures the info of the timer start in S5 state and avoids restarting the timer again. BUG=b:235783840 BRANCH=main TEST=verify S5 to G3 transition time on nivviks Change-Id: I434a5885ea44b48f6b6b016fc22e56a43161b8ff Signed-off-by: Deepti Deshatty Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705456 Reviewed-by: Andrew McRae Reviewed-by: Peter Marheine Reviewed-by: Vijay P Hiremath --- .../ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index 2f38c36684..29d1ce3b1f 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -11,6 +11,7 @@ static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE); static struct k_thread pwrseq_thread_data; static struct pwrseq_context pwrseq_ctx; +static bool s5_inactive_tmr_running; /* S5 inactive timer*/ K_TIMER_DEFINE(s5_inactive_timer, NULL, NULL); @@ -221,6 +222,7 @@ static int common_pwr_sm_run(int state) rsmrst_pass_thru_handler(); if (signals_valid_and_off(IN_PCH_SLP_S5)) { k_timer_stop(&s5_inactive_timer); + s5_inactive_tmr_running = false; return SYS_POWER_STATE_S5S4; } } @@ -228,16 +230,18 @@ static int common_pwr_sm_run(int state) if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) == 0) return SYS_POWER_STATE_S5G3; else if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) > 0) { - if (k_timer_status_get(&s5_inactive_timer) > 0) - /* Timer is expired */ - return SYS_POWER_STATE_S5G3; - else if (k_timer_remaining_get( - &s5_inactive_timer) == 0) - /* Timer is not started or stopped */ + if (!s5_inactive_tmr_running) { + /* Timer is not started */ k_timer_start(&s5_inactive_timer, K_SECONDS(AP_PWRSEQ_DT_VALUE( s5_inactivity_timeout)), K_NO_WAIT); + s5_inactive_tmr_running = true; + } else if (k_timer_status_get(&s5_inactive_timer) > 0) { + /* Timer is expired */ + s5_inactive_tmr_running = false; + return SYS_POWER_STATE_S5G3; + } } break; -- cgit v1.2.1 From 1e0dfe4c67782202b20a7f7e345b116e1147571f Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Tue, 21 Jun 2022 05:14:29 +0000 Subject: Revert "kinox: add enable and disable ppc sink mode" This reverts commit e85c5bab8282346ef8ec0d9a4c480be3e0e8780f. Reason for revert: Power source have to switch adapter under S5.b:225769067#comment27 Original change's description: > kinox: add enable and disable ppc sink mode > > When Kinox is sinking power from the type-c port then enable the PPC to sink and disabled when using the barrel jack. > And the Kinox does not support the adapter change when EC is on. > > BUG=b:225769067 > BRANCH=none > TEST=Test on Kinox, > The system can power on to OS via barrel adapter or type-c adapter. > Plugin the barrel adapter the log has the "New charger is p1" and successfully disables C0 to sink path. > Plugin the Type-C 65w adapter the log has the"New charger is p0" and successfully enables C0 to sink path. > > Signed-off-by: Matt Wang > Change-Id: I7adaa113d15cd607f1be799da072386160bdcb74 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3535546 > Reviewed-by: Elmo Lan > Reviewed-by: Ricky Chang > Reviewed-by: Elthan Huang Bug: b:225769067 Change-Id: I4848b0bacea96024960997fffac10a0d315e7130 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716172 Reviewed-by: Ricky Chang Commit-Queue: Ricky Chang Tested-by: Matt Wang --- board/kinox/board.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/board/kinox/board.c b/board/kinox/board.c index a814c7a20d..0dae3b0f5e 100644 --- a/board/kinox/board.c +++ b/board/kinox/board.c @@ -11,7 +11,6 @@ #include "compile_time_macros.h" #include "console.h" #include "cros_board_info.h" -#include "fw_config.h" #include "gpio.h" #include "gpio_signal.h" #include "power_button.h" @@ -20,7 +19,7 @@ #include "switch.h" #include "throttle_ap.h" #include "usbc_config.h" -#include "usbc_ppc.h" +#include "fw_config.h" #include "gpio_list.h" /* Must come after other header files. */ @@ -40,8 +39,6 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); int board_set_active_charge_port(int port) { - int rv; - CPRINTS("Requested charge port change to %d", port); /* @@ -64,15 +61,23 @@ int board_set_active_charge_port(int port) if (board_vbus_source_enabled(port)) return EC_ERROR_INVAL; - /* Don't change the charge port */ - if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE) - return EC_ERROR_INVAL; - - /* Make sure BJ adapter is sourcing power */ - if (port == CHARGE_PORT_BARRELJACK && - gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) { - CPRINTS("BJ port selected, but not present!"); - return EC_ERROR_INVAL; + if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) { + int bj_active, bj_requested; + + if (charge_manager_get_active_charge_port() != CHARGE_PORT_NONE) + /* Change is only permitted while the system is off */ + return EC_ERROR_INVAL; + + /* + * Current setting is no charge port but the AP is on, so the + * charge manager is out of sync (probably because we're + * reinitializing after sysjump). Reject requests that aren't + * in sync with our outputs. + */ + bj_active = !gpio_get_level(GPIO_EN_PPVAR_BJ_ADP_L); + bj_requested = port == CHARGE_PORT_BARRELJACK; + if (bj_active != bj_requested) + return EC_ERROR_INVAL; } CPRINTS("New charger p%d", port); @@ -80,18 +85,11 @@ int board_set_active_charge_port(int port) switch (port) { case CHARGE_PORT_TYPEC0: gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1); - rv = ppc_vbus_sink_enable(CHARGE_PORT_TYPEC0, 1); - if (rv) { - CPRINTS("Failed to enable C0 sink path"); - return rv; - } break; case CHARGE_PORT_BARRELJACK: - rv = ppc_vbus_sink_enable(CHARGE_PORT_TYPEC0, 0); - if (rv) { - CPRINTS("Failed to disable C0 sink path"); - return rv; - } + /* Make sure BJ adapter is sourcing power */ + if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) + return EC_ERROR_INVAL; gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0); break; default: -- cgit v1.2.1 From 5374f6e199bba4cdeb2401bdda7a4aec8065db7a Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Wed, 15 Jun 2022 00:44:36 -0700 Subject: chip/stm32: Basic DMAMUX support on STM32L5 family Add declarations of DMAMUX registers, and enable clock to DMAMUX by default on L5xx series. BUG=b:192262089 TEST=USB->SPI forwarding on HyperDebug (with more CLs) BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: I6c49acc63f5b4c47ecacbbd21708c196907e6415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706577 Reviewed-by: Daisuke Nojiri --- chip/stm32/dma.c | 6 +-- chip/stm32/registers-stm32l5.h | 104 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+), 3 deletions(-) diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index ae5a83789d..940d950dff 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -254,9 +254,9 @@ void dma_test(enum dma_channel channel) void dma_init(void) { -#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) +#if defined(CHIP_FAMILY_STM32L4) STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN; -#elif defined(CHIP_FAMILY_STM32G4) +#elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5) STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN | STM32_RCC_AHB1ENR_DMAMUXEN; #else @@ -396,7 +396,7 @@ DECLARE_DMA_IRQ(7); DECLARE_DMA_IRQ(9); DECLARE_DMA_IRQ(10); #endif -#ifdef CHIP_FAMILY_STM32L4 +#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) DECLARE_DMA_IRQ(9); DECLARE_DMA_IRQ(10); DECLARE_DMA_IRQ(11); diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index 5055bc9e19..e7b8daee62 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -171,6 +171,7 @@ /*!< AHB1 peripherals */ #define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) #define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL) #define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) #define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) #define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) @@ -1227,6 +1228,7 @@ #define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U #define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) #define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK +#define STM32_RCC_AHB1ENR_DMAMUXEN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK #define STM32_RCC_AHB1ENR_FLASHEN_POS 8U #define STM32_RCC_AHB1ENR_FLASHEN_MSK (0x1UL << STM32_RCC_AHB1ENR_FLASHEN_POS) #define STM32_RCC_AHB1ENR_FLASHEN STM32_RCC_AHB1ENR_FLASHEN_MSK @@ -2433,6 +2435,108 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) #define STM32_DMA_CCR_MEM2MEM BIT(14) +/* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ +/* DMAMUX registers */ +#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) +#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) +#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) +#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) +#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) +#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) + +enum dmamux1_request { + DMAMUX_REQ_ADC1 = 5, + DMAMUX_REQ_ADC2 = 6, + DMAMUX_REQ_DAC1 = 7, + DMAMUX_REQ_DAC2 = 8, + DMAMUX_REQ_TIM6_UP = 9, + DMAMUX_REQ_TIM7_UP = 10, + DMAMUX_REQ_SPI1_RX = 11, + DMAMUX_REQ_SPI1_TX = 12, + DMAMUX_REQ_SPI2_RX = 13, + DMAMUX_REQ_SPI2_TX = 14, + DMAMUX_REQ_SPI3_RX = 15, + DMAMUX_REQ_SPI3_TX = 16, + DMAMUX_REQ_I2C1_RX = 17, + DMAMUX_REQ_I2C1_TX = 18, + DMAMUX_REQ_I2C2_RX = 19, + DMAMUX_REQ_I2C2_TX = 20, + DMAMUX_REQ_I2C3_RX = 21, + DMAMUX_REQ_I2C3_TX = 22, + DMAMUX_REQ_I2C4_RX = 23, + DMAMUX_REQ_I2C4_TX = 24, + DMAMUX_REQ_USART1_RX = 25, + DMAMUX_REQ_USART1_TX = 26, + DMAMUX_REQ_USART2_RX = 27, + DMAMUX_REQ_USART2_TX = 28, + DMAMUX_REQ_USART3_RX = 29, + DMAMUX_REQ_USART3_TX = 30, + DMAMUX_REQ_UART4_RX = 31, + DMAMUX_REQ_UART4_TX = 32, + DMAMUX_REQ_UART5_RX = 33, + DMAMUX_REQ_UART5_TX = 34, + DMAMUX_REQ_LPUART1_RX = 35, + DMAMUX_REQ_LPUART1_TX = 36, + DMAMUX_REQ_SAI1_A = 37, + DMAMUX_REQ_SAI1_B = 38, + DMAMUX_REQ_SAI2_A = 39, + DMAMUX_REQ_SAI2_B = 40, + DMAMUX_REQ_OCTOSPI1 = 41, + DMAMUX_REQ_TIM1_CH1 = 42, + DMAMUX_REQ_TIM1_CH2 = 43, + DMAMUX_REQ_TIM1_CH3 = 44, + DMAMUX_REQ_TIM1_CH4 = 45, + DMAMUX_REQ_TIM1_UP = 46, + DMAMUX_REQ_TIM1_TRIG = 47, + DMAMUX_REQ_TIM1_COM = 48, + DMAMUX_REQ_TIM8_CH1 = 49, + DMAMUX_REQ_TIM8_CH2 = 50, + DMAMUX_REQ_TIM8_CH3 = 51, + DMAMUX_REQ_TIM8_CH4 = 52, + DMAMUX_REQ_TIM8_UP = 53, + DMAMUX_REQ_TIM8_TRIG = 54, + DMAMUX_REQ_TIM8_COM = 55, + DMAMUX_REQ_TIM2_CH1 = 56, + DMAMUX_REQ_TIM2_CH2 = 57, + DMAMUX_REQ_TIM2_CH3 = 58, + DMAMUX_REQ_TIM2_CH4 = 59, + DMAMUX_REQ_TIM2_UP = 60, + DMAMUX_REQ_TIM3_CH1 = 61, + DMAMUX_REQ_TIM3_CH2 = 62, + DMAMUX_REQ_TIM3_CH3 = 63, + DMAMUX_REQ_TIM3_CH4 = 64, + DMAMUX_REQ_TIM3_UP = 65, + DMAMUX_REQ_TIM3_TRIG = 66, + DMAMUX_REQ_TIM4_CH1 = 67, + DMAMUX_REQ_TIM4_CH2 = 68, + DMAMUX_REQ_TIM4_CH3 = 69, + DMAMUX_REQ_TIM4_CH4 = 70, + DMAMUX_REQ_TIM4_UP = 71, + DMAMUX_REQ_TIM5_CH1 = 72, + DMAMUX_REQ_TIM5_CH2 = 73, + DMAMUX_REQ_TIM5_CH3 = 74, + DMAMUX_REQ_TIM5_CH4 = 75, + DMAMUX_REQ_TIM5_UP = 76, + DMAMUX_REQ_TIM5_TRIG = 77, + DMAMUX_REQ_TIM15_CH1 = 78, + DMAMUX_REQ_TIM15_UP = 79, + DMAMUX_REQ_TIM15_TRIG = 80, + DMAMUX_REQ_TIM15_COM = 81, + DMAMUX_REQ_TIM16_CH1 = 82, + DMAMUX_REQ_TIM16_UP = 83, + DMAMUX_REQ_TIM17_CH1 = 84, + DMAMUX_REQ_TIM17_UP = 85, + DMAMUX_REQ_DFSDM1_FLT0 = 86, + DMAMUX_REQ_DFSDM1_FLT1 = 87, + DMAMUX_REQ_DFSDM1_FLT2 = 88, + DMAMUX_REQ_DFSDM1_FLT3 = 89, + DMAMUX_REQ_AES_IN = 90, + DMAMUX_REQ_AES_OUT = 91, + DMAMUX_REQ_HASH_IN = 92, + DMAMUX_REQ_USBPD_TX = 93, + DMAMUX_REQ_USBPD_RX = 94, +}; + /* LPUART gets accessed as UART9 in STM32 uart module */ #define STM32_USART9_BASE STM32_LPUART1_BASE #define STM32_IRQ_USART9 STM32_IRQ_LPUART1 -- cgit v1.2.1 From 22400bd61a75cfa842127140cd03337189f256b6 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Wed, 15 Jun 2022 00:51:34 -0700 Subject: chip/stm32: SPI support on STM32L5xx The L5 series has a capable DMAMUX, unlike L4 and most others. This change enhances the SPI logic to setup the SPIMUX appropriately, if present. BUG=b:192262089 TEST=USB->SPI forwarding on HyperDebug (with more CLs) BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: I45e93816e982b4e675693f1f99a3895cc8279f7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706578 Reviewed-by: Daisuke Nojiri --- chip/stm32/spi_controller.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c index e34afde7e1..4b6876b959 100644 --- a/chip/stm32/spi_controller.c +++ b/chip/stm32/spi_controller.c @@ -19,6 +19,7 @@ #if defined(CHIP_VARIANT_STM32F373) || \ defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_FAMILY_STM32L5) || \ defined(CHIP_VARIANT_STM32F76X) #define HAS_SPI3 #else @@ -36,14 +37,26 @@ static stm32_spi_regs_t *SPI_REGS[] = { #endif }; -#ifdef CHIP_FAMILY_STM32L4 /* DMA request mapping on channels */ -static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = { +struct dma_req_t { + uint8_t tx_req; + uint8_t rx_req; +}; +#ifdef CHIP_FAMILY_STM32L4 +static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - /* SPI1 */ 1, + /* SPI1 */ { 1, 1 }, #endif - /* SPI2 */ 1, - /* SPI3 */ 3, + /* SPI2 */ { 1, 1 }, + /* SPI3 */ { 3, 3 }, +}; +#elif defined(CHIP_FAMILY_STM32L5) +static struct dma_req_t dma_req[ARRAY_SIZE(SPI_REGS)] = { +#ifdef CONFIG_STM32_SPI1_CONTROLLER + /* SPI1 */ { DMAMUX_REQ_SPI1_TX, DMAMUX_REQ_SPI1_RX }, +#endif + /* SPI2 */ { DMAMUX_REQ_SPI2_TX, DMAMUX_REQ_SPI2_RX }, + /* SPI3 */ { DMAMUX_REQ_SPI3_TX, DMAMUX_REQ_SPI3_RX }, }; #endif @@ -203,9 +216,9 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device) spi->cr1 = STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI | (spi_device->div << 3); -#ifdef CHIP_FAMILY_STM32L4 - dma_select_channel(dma_tx_option[port].channel, dma_req[port]); - dma_select_channel(dma_rx_option[port].channel, dma_req[port]); +#if defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) + dma_select_channel(dma_tx_option[port].channel, dma_req[port].tx_req); + dma_select_channel(dma_rx_option[port].channel, dma_req[port].rx_req); #endif /* * Configure 8-bit datasize, set FRXTH, enable DMA, -- cgit v1.2.1 From da4bcc79bb782234e74e3637a89c4b4c8ad50a4f Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Fri, 17 Jun 2022 13:59:27 -0700 Subject: chip/stm32/spi_controller.c: Handle read-only transactions It seemed that read-only SPI transactions (txlen == 0) did not work, possibly because a zero-length DMA transfer was attempted. Making a block conditional on txlen being nonzero enabled my HyperDebug board to perform USB->SPI forwarding of transactions involving only reading. (Also, it makes the reading and writing parts of the code look more symmetrical.) BUG=b:192262089 TEST=USB->SPI forwarding on HyperDebug (with more CLs) BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: I827c83ee6d917fc5f00fb9e42783722f0917d19a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711967 Reviewed-by: Daisuke Nojiri --- chip/stm32/spi_controller.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c index 4b6876b959..8e5b01d621 100644 --- a/chip/stm32/spi_controller.c +++ b/chip/stm32/spi_controller.c @@ -385,13 +385,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device, spi_clear_rx_fifo(spi); - rv = spi_dma_start(port, txdata, buf, txlen); - if (rv != EC_SUCCESS) - goto err_free; - + if (txlen) { + rv = spi_dma_start(port, txdata, buf, txlen); + if (rv != EC_SUCCESS) + goto err_free; #ifdef CONFIG_SPI_HALFDUPLEX - spi->cr1 |= STM32_SPI_CR1_BIDIOE; + spi->cr1 |= STM32_SPI_CR1_BIDIOE; #endif + } if (full_readback) return EC_SUCCESS; -- cgit v1.2.1 From 1aeecb1765888e216b303f096066275892effc40 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Thu, 16 Jun 2022 08:40:08 -0700 Subject: common/gpio_commands.c: set() considers GPIO reconfiguration The set() method allows manually setting the level of a named GPIO pin, provided that the pin is configured for output. Existing code considered only the compile-time configuration of the pin. With this change, if support has been selected, the method will inspect the current configuration of the particular GPIO pin. To be fair, the current state does not usually cause issues, since the set() method is not called by command_gpio_set() in case CONFIG_CMD_GPIO_EXTENDED is enabled, which allows reconfiguration of pins from input to output. On my board (HyperDebug) I do not want to enable CONFIG_CMD_GPIO_EXTENDED, since doing so causes e.g. "gpioset 1" to both reconfigure the pin to be output, and set its level. I want to keep "gpioset" for only setting 0/1, and I want it to reject operation on input-only pins. At the same time I have implemented a separate custom command which allows modifying the pin input/output and pullup configuration in the ways needed for the use case. Without this change, however, I am not able to use the standard "gpioset" command. BUG=b:192262089 TEST=Use HyperDebug to manipulate the RESET line of AndreiBoard BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: Ia66dc01fe3ca2ce4330b09431f6edc85bdeec75d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706990 Reviewed-by: Daisuke Nojiri --- common/gpio_commands.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/common/gpio_commands.c b/common/gpio_commands.c index b044524797..758a0ad8dc 100644 --- a/common/gpio_commands.c +++ b/common/gpio_commands.c @@ -67,8 +67,13 @@ static enum ec_error_list set(const char *name, int value) if (!gpio_is_implemented(signal)) return EC_ERROR_INVAL; - if (!(gpio_get_default_flags(signal) & GPIO_OUTPUT)) - return EC_ERROR_INVAL; + if (IS_ENABLED(CONFIG_GPIO_GET_EXTENDED)) { + if (!(gpio_get_flags(signal) & GPIO_OUTPUT)) + return EC_ERROR_INVAL; + } else { + if (!(gpio_get_default_flags(signal) & GPIO_OUTPUT)) + return EC_ERROR_INVAL; + } gpio_set_level(signal, value); -- cgit v1.2.1 From 66f81102e8bfdb8338c76b8f6dd991c58ca1b0c3 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Fri, 17 Jun 2022 09:36:36 +0800 Subject: it83xx: reload watchdog on system jump This ensures that a new FW image will have full watchdog period during initialization. BUG=b:235297476 BRANCH=cherry TEST=The watchdog_reload() routine is called every time the system jumps. Signed-off-by: Dino Li Change-Id: I103cb2c738b26a1000a72617706f4c30e8c952b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708382 Reviewed-by: Eric Yilun Lin Tested-by: Tommy Chung --- chip/it83xx/watchdog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c index f0e200c4ac..345a100922 100644 --- a/chip/it83xx/watchdog.c +++ b/chip/it83xx/watchdog.c @@ -93,6 +93,7 @@ void watchdog_reload(void) } } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_SYSJUMP, watchdog_reload, HOOK_PRIO_LAST); int watchdog_init(void) { -- cgit v1.2.1 From a75badd9d994ba1bef0b8c8267f464c2bf430f73 Mon Sep 17 00:00:00 2001 From: Mark Hsieh Date: Thu, 16 Jun 2022 21:43:55 +0800 Subject: nissa/joxer: Initial EC image Create the initial Zephyr EC image for the joxer variant by copying the nissa reference board EC files into a new directory named for the variant. BUG=b:236086879 TEST=zmake configure -b joxer BRANCH=none Change-Id: I0570f604dcedaeccc2817a07a5242fa63eb5264e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708989 Reviewed-by: Peter Marheine Commit-Queue: Mark Hsieh Tested-by: Mark Hsieh --- zephyr/projects/nissa/BUILD.py | 16 +- zephyr/projects/nissa/CMakeLists.txt | 10 +- zephyr/projects/nissa/Kconfig | 6 + zephyr/projects/nissa/joxer_generated.dts | 265 +++++++++++++++++ zephyr/projects/nissa/joxer_keyboard.dts | 19 ++ zephyr/projects/nissa/joxer_motionsense.dts | 157 ++++++++++ zephyr/projects/nissa/joxer_overlay.dts | 328 +++++++++++++++++++++ zephyr/projects/nissa/joxer_power_signals.dts | 223 ++++++++++++++ zephyr/projects/nissa/joxer_pwm_leds.dts | 61 ++++ zephyr/projects/nissa/prj_joxer.conf | 58 ++++ zephyr/projects/nissa/src/joxer/charger.c | 56 ++++ zephyr/projects/nissa/src/joxer/keyboard.c | 29 ++ zephyr/projects/nissa/src/joxer/usbc.c | 404 ++++++++++++++++++++++++++ 13 files changed, 1630 insertions(+), 2 deletions(-) create mode 100644 zephyr/projects/nissa/joxer_generated.dts create mode 100644 zephyr/projects/nissa/joxer_keyboard.dts create mode 100644 zephyr/projects/nissa/joxer_motionsense.dts create mode 100644 zephyr/projects/nissa/joxer_overlay.dts create mode 100644 zephyr/projects/nissa/joxer_power_signals.dts create mode 100644 zephyr/projects/nissa/joxer_pwm_leds.dts create mode 100644 zephyr/projects/nissa/prj_joxer.conf create mode 100644 zephyr/projects/nissa/src/joxer/charger.c create mode 100644 zephyr/projects/nissa/src/joxer/keyboard.c create mode 100644 zephyr/projects/nissa/src/joxer/usbc.c diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index a0acb90680..05f99d88fe 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -4,7 +4,7 @@ """Define zmake projects for nissa.""" -# Nivviks and Craask, Pujjo, Xivu has NPCX993F, Nereid has ITE81302 +# Nivviks and Craask, Pujjo, Xivu has NPCX993F, Nereid and Joxer has ITE81302 def register_nissa_project( @@ -96,3 +96,17 @@ xivu = register_nissa_project( ], extra_kconfig_files=[here / "prj_xivu.conf"], ) + +joxer = register_nissa_project( + project_name="joxer", + chip="it8xxx2", + extra_dts_overlays=[ + here / "joxer_generated.dts", + here / "joxer_overlay.dts", + here / "joxer_motionsense.dts", + here / "joxer_keyboard.dts", + here / "joxer_power_signals.dts", + here / "joxer_pwm_leds.dts", + ], + extra_kconfig_files=[here / "prj_joxer.conf"], +) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 9f2452bcbc..47f98daf9f 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -57,4 +57,12 @@ if(DEFINED CONFIG_BOARD_XIVU) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/xivu/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/xivu/charger.c") endif() - +if(DEFINED CONFIG_BOARD_JOXER) + project(joxer) + zephyr_library_sources( + "src/led.c" + "src/joxer/keyboard.c" + ) + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/joxer/usbc.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/joxer/charger.c") +endif() diff --git a/zephyr/projects/nissa/Kconfig b/zephyr/projects/nissa/Kconfig index d9ba0f9015..f0c7bb8c2f 100644 --- a/zephyr/projects/nissa/Kconfig +++ b/zephyr/projects/nissa/Kconfig @@ -32,6 +32,12 @@ config BOARD_XIVU Build Google Xivu board. Xivu has Intel ADL-N SoC with NPCX993FA0BX EC. +config BOARD_JOXER + bool "Google Joxer Board" + help + Build Google Joxer reference board. Joxer has Intel ADL-N SoC + with IT81302 EC. + module = NISSA module-str = Nissa board-specific code source "subsys/logging/Kconfig.template.log_config" diff --git a/zephyr/projects/nissa/joxer_generated.dts b/zephyr/projects/nissa/joxer_generated.dts new file mode 100644 index 0000000000..a588937f3c --- /dev/null +++ b/zephyr/projects/nissa/joxer_generated.dts @@ -0,0 +1,265 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + label = "EC_VSENSE_PP1050_PROC"; + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + label = "EC_VSENSE_PP3300_S5"; + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + label = "TEMP_SENSOR_1"; + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + label = "TEMP_SENSOR_2"; + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + label = "TEMP_SENSOR_3"; + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-name = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-name = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-name = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-name = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-name = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/projects/nissa/joxer_keyboard.dts b/zephyr/projects/nissa/joxer_keyboard.dts new file mode 100644 index 0000000000..ae104b1ead --- /dev/null +++ b/zephyr/projects/nissa/joxer_keyboard.dts @@ -0,0 +1,19 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; + frequency = <10000>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer_motionsense.dts b/zephyr/projects/nissa/joxer_motionsense.dts new file mode 100644 index 0000000000..596b3eb148 --- /dev/null +++ b/zephyr/projects/nissa/joxer_motionsense.dts @@ -0,0 +1,157 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + label = "LID_MUTEX"; + }; + + base_mutex: base-mutex { + label = "BASE_MUTEX"; + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The label "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO:(b/229577857) The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + label = "Lid Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + label = "Base Accel"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + label = "SENSOR_CONFIG_EC_S0"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + label = "SENSOR_CONFIG_EC_S3"; + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu>; + /* list of sensors in force mode */ + accel-force-mode-sensors = <&lid_accel>; + }; +}; diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts new file mode 100644 index 0000000000..158629b1e9 --- /dev/null +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -0,0 +1,328 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + }; + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l20m3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioj 7 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + }; + + /* + * Aliases used for sub-board GPIOs. + */ + aliases { + /* USB-C: interrupt input. I2C pins are on i2c_ec_i2c_sub_usb_c1 */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + named-temp-sensors { + memory { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "DDR and SOC"; + enum-name = "TEMP_SENSOR_1"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_1>; + }; + charger { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "Charger"; + enum-name = "TEMP_SENSOR_CHARGER"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_2>; + }; + ambient { + compatible = "cros-ec,temp-sensor-thermistor", + "cros-ec,temp-sensor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + label = "Ambient"; + enum-name = "TEMP_SENSOR_AMB"; + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + adc = <&adc_temp_sensor_3>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_usb_c0>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_usb_c0>; + }; + usb-muxes = <&virtual_mux_0>; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + chg { + compatible = "siliconmitus,sm5803"; + status = "okay"; + port = <&i2c_ec_i2c_sub_usb_c1>; + }; + /* + * Some sub-boards may disable all usb muxes in chain + * except virtual_mux_1 + */ + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + label = "EEPROM_CBI"; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = ; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = ; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-names = "default"; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/joxer_power_signals.dts b/zephyr/projects/nissa/joxer_power_signals.dts new file mode 100644 index 0000000000..0a3ead778b --- /dev/null +++ b/zephyr/projects/nissa/joxer_power_signals.dts @@ -0,0 +1,223 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 GPIO_OPEN_DRAIN>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = ; + comparison = ; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = ; + comparison = ; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/projects/nissa/joxer_pwm_leds.dts b/zephyr/projects/nissa/joxer_pwm_leds.dts new file mode 100644 index 0000000000..9a981b7071 --- /dev/null +++ b/zephyr/projects/nissa/joxer_pwm_leds.dts @@ -0,0 +1,61 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(324) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + frequency = <1296>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/prj_joxer.conf b/zephyr/projects/nissa/prj_joxer.conf new file mode 100644 index 0000000000..d067a1bb33 --- /dev/null +++ b/zephyr/projects/nissa/prj_joxer.conf @@ -0,0 +1,58 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# EC chip configuration: IT83102 +CONFIG_BOARD_JOXER=y +CONFIG_CROS_FLASH_IT8XXX2=y +CONFIG_CROS_SYSTEM_IT8XXX2=y +CONFIG_ESPI_IT8XXX2=y + +# Allow more time for the charger to stabilise +CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 + +# RAM savings, since this chip is tight on available RAM. +# It's useful to store a lot of logs for the host to request, but the default 4k +# is pretty large. +CONFIG_PLATFORM_EC_HOSTCMD_CONSOLE_BUF_SIZE=2048 +# Our threads have short names, save 20 bytes per thread +CONFIG_THREAD_MAX_NAME_LEN=12 +# Task stacks, tuned by experiment. Most expanded to prevent overflow, and a few +# shrunk to save RAM. +CONFIG_AP_PWRSEQ_STACK_SIZE=1408 +CONFIG_TASK_HOSTCMD_STACK_SIZE=1280 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1280 +CONFIG_TASK_PD_INT_STACK_SIZE=1280 + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y + +# TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y +# SM5803 controls power path on both ports +CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y +# SM5803 can discharge VBUS, but not via one of the available options; +# pd_power_supply_reset() does discharge. +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE=n +# The EC is put into programming mode while firmware is running +# (after releasing reset) and PD after being reset will hard-reset +# the port if a contract was already set up. If the system has no +# battery, this will prevent programming because it will brown out +# the system and reset. Inserting a delay gives the programmer more +# time to put the EC into programming mode. +CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS=2000 + +# Charger driver and configuration +CONFIG_PLATFORM_EC_CHARGER_SM5803=y +CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 + +# VSENSE: PP3300_S5 & PP1050_PROC +CONFIG_VCMP_IT8XXX2=y +CONFIG_SENSOR=y +CONFIG_SENSOR_SHELL=n +CONFIG_TACH_IT8XXX2=n diff --git a/zephyr/projects/nissa/src/joxer/charger.c b/zephyr/projects/nissa/src/joxer/charger.c new file mode 100644 index 0000000000..ff350b44da --- /dev/null +++ b/zephyr/projects/nissa/src/joxer/charger.c @@ -0,0 +1,56 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Joxer not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/projects/nissa/src/joxer/keyboard.c b/zephyr/projects/nissa/src/joxer/keyboard.c new file mode 100644 index 0000000000..9deb799d13 --- /dev/null +++ b/zephyr/projects/nissa/src/joxer/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config joxer_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_FORWARD, /* T2 */ + TK_REFRESH, /* T3 */ + TK_FULLSCREEN, /* T4 */ + TK_OVERVIEW, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config +*board_vivaldi_keybd_config(void) +{ + return &joxer_kb_legacy; +} diff --git a/zephyr/projects/nissa/src/joxer/usbc.c b/zephyr/projects/nissa/src/joxer/usbc.c new file mode 100644 index 0000000000..eeab449c32 --- /dev/null +++ b/zephyr/projects/nissa/src/joxer/usbc.c @@ -0,0 +1,404 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +#include "charge_state_v2.h" +#include "chipset.h" +#include "hooks.h" +#include "usb_mux.h" +#include "system.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { + { + .bus_type = EC_BUS_TYPE_EMBEDDED, + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it8xxx2_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, + { + /* + * Sub-board: optional PS8745 TCPC+redriver. Behaves the same + * as PS8815. + */ + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C1_TCPC, + .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + }, + .drv = &ps8xxx_tcpm_drv, + /* PS8745 implements TCPCI 2.0 */ + .flags = TCPC_FLAGS_TCPCI_REV2_0, + }, +}; + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + int vbus_voltage; + + /* If we're unable to speak to the charger, best to guess false */ + if (charger_get_vbus_voltage(port, &vbus_voltage)) { + return false; + } + + if (level == VBUS_SAFE0V) + return vbus_voltage < PD_V_SAFE0V_MAX; + else if (level == VBUS_PRESENT) + return vbus_voltage > PD_V_SAFE5V_MIN; + else + return vbus_voltage < PD_V_SINK_DISCONNECT_MAX; +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", + __func__, data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(const struct device *unused) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if (port == CHARGE_PORT_NONE) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +static void check_c1_line(void); +DECLARE_DEFERRED(check_c1_line); + +static void notify_c1_chips(void) +{ + schedule_deferred_pd_interrupt(1); + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + /* Charger is handled in board_process_pd_alert */ +} + +static void check_c1_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + notify_c1_chips(); + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); + } +} + +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c1_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c1_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); +} + +/* + * Check state of IRQ lines at startup, ensuring an IRQ that happened before + * the EC started up won't get lost (leaving the IRQ line asserted and blocking + * any further interrupts on the port). + * + * Although the PD task will check for pending TCPC interrupts on startup, + * the charger sharing the IRQ will not be polled automatically. + */ +void board_handle_initial_typec_irq(void) +{ + check_c0_line(); + check_c1_line(); +} +/* + * This must run after sub-board detection (which happens in EC main()), + * but isn't depended on by anything else either. + */ +DECLARE_HOOK(HOOK_INIT, board_handle_initial_typec_irq, HOOK_PRIO_LAST); + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the charger interrupt is cleared + * (or the IRQ is polled again), which happens in the low-priority charger task: + * the high-priority type-C handler is thus blocked on the lower-priority + * charger. + * + * To avoid that, we run charger interrupts at the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port == 1 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + } +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} -- cgit v1.2.1 From 95b3e9ab4879f356a0f14cafb4a2185538ba3f4c Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 20 Jun 2022 18:56:47 +0800 Subject: dojo: Set watchdog period to 2500ms To avoid watchdog due to race condiftion of uart tx buf flush INT and i2c large transfer (accelgyro BMI260 init) INT, extend the watchdog period to 2500ms. BUG=b:235297476 BRANCH=cherry TEST=make sure there's no ec watchdog reset during firmware-update and faft firmware_ECWatchdog pass. Signed-off-by: Tommy Chung Change-Id: Ie6a03a99bc3e87b525346bf39a07a4ba10134b92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3709282 Reviewed-by: Eric Yilun Lin --- board/dojo/board.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/dojo/board.h b/board/dojo/board.h index 734b73bac7..15de045652 100644 --- a/board/dojo/board.h +++ b/board/dojo/board.h @@ -13,6 +13,10 @@ #define CONFIG_LTO #define CONFIG_PRESERVE_LOGS +/* Watchdog period in ms */ +#undef CONFIG_WATCHDOG_PERIOD_MS +#define CONFIG_WATCHDOG_PERIOD_MS 2500 + /* * TODO: Remove this option once the VBAT no longer keeps high when * system's power isn't presented. -- cgit v1.2.1 From 19ee52c413b5a66ff02010a6b8112a37dd24ed41 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Fri, 17 Jun 2022 11:28:20 -0600 Subject: test: drivers: fix test order dependency The 'get_data_rate' function was not being initialized correctly and returning 0 if the test order was shuffled. Needed to set it to any value that's not 0. BRANCH=none BUG=b:233355058 TEST=zephyr.elf -seed=$(date +%s) Signed-off-by: Yuval Peress Change-Id: I17fb3a9d944f9dc696bbca69bd84e074565e9433 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716279 Reviewed-by: Aaron Massey --- zephyr/test/drivers/src/console_cmd/accelread.c | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/test/drivers/src/console_cmd/accelread.c b/zephyr/test/drivers/src/console_cmd/accelread.c index 02aae54f3a..1dcc4168a4 100644 --- a/zephyr/test/drivers/src/console_cmd/accelread.c +++ b/zephyr/test/drivers/src/console_cmd/accelread.c @@ -98,6 +98,7 @@ ZTEST_USER_F(console_cmd_accelread, test_read) { current_fixture = fixture; mock_read_fake.custom_fake = mock_read_call_super; + mock_get_data_rate_fake.return_val = 100; motion_sensors[0].drv = &fixture->mock_drv; zassert_ok(shell_execute_cmd(get_ec_shell(), "accelread 0"), NULL); -- cgit v1.2.1 From 28d0b75b708d3d60812bac50e6dae14599b3fe94 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 14 Jun 2022 10:54:53 -0700 Subject: third_party/boringssl: Remove unused header When compiling with C++ (and using the C stdlib), this include is not found: include/aes-gcm.h:53:10: fatal error: 'endian.h' file not found ^~~~~~~~~~ Remove the header since it's not actually used in these files. BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I2f90b42cbfd4ca5334bfa400c9124755c4b1cf0d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705695 Reviewed-by: Diana Z --- driver/fingerprint/fpc/libfp/fpc_private.c | 1 - third_party/boringssl/common/aes-gcm.c | 1 - third_party/boringssl/include/aes-gcm.h | 1 - 3 files changed, 3 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c index 7e7befcfdc..75ab9727ef 100644 --- a/driver/fingerprint/fpc/libfp/fpc_private.c +++ b/driver/fingerprint/fpc/libfp/fpc_private.c @@ -6,7 +6,6 @@ #include #include "common.h" #include "console.h" -#include "endian.h" #include "fpc_bio_algorithm.h" #include "fpc_private.h" #include "fpsensor.h" diff --git a/third_party/boringssl/common/aes-gcm.c b/third_party/boringssl/common/aes-gcm.c index edb98b88b3..8fe5f75307 100644 --- a/third_party/boringssl/common/aes-gcm.c +++ b/third_party/boringssl/common/aes-gcm.c @@ -48,7 +48,6 @@ #include "aes-gcm.h" #include "common.h" -#include "endian.h" #include "util.h" #define STRICT_ALIGNMENT 1 diff --git a/third_party/boringssl/include/aes-gcm.h b/third_party/boringssl/include/aes-gcm.h index e3ef457224..77ca52a3ed 100644 --- a/third_party/boringssl/include/aes-gcm.h +++ b/third_party/boringssl/include/aes-gcm.h @@ -50,7 +50,6 @@ #define __CROS_EC_AES_GCM_H #include "common.h" -#include "endian.h" #include "util.h" // block128_f is the type of a 128-bit, block cipher. -- cgit v1.2.1 From fb1a084cfb2dc6fabeef60072a4e6b825f7ac266 Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Fri, 17 Jun 2022 08:45:47 -0600 Subject: zephyr: test: Fix flaky panic test With shuffling enabled panic test is repeated and data is not restored to prior to test running. BUG=b:233101019 BRANCH=none TEST=zmake test test-drivers Signed-off-by: Al Semjonovs Change-Id: I968b2108e4940d1bde94846213b807faf6217305 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712001 Reviewed-by: Yuval Peress --- zephyr/test/drivers/src/panic.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/panic.c b/zephyr/test/drivers/src/panic.c index 2615c22156..f33a078253 100644 --- a/zephyr/test/drivers/src/panic.c +++ b/zephyr/test/drivers/src/panic.c @@ -20,10 +20,42 @@ #include "test/drivers/stubs.h" #include "test/drivers/test_state.h" +struct panic_test_fixture { + struct panic_data saved_pdata; +}; + +static void *panic_test_setup(void) +{ + static struct panic_test_fixture panic_fixture = {0}; + + return &panic_fixture; +} + +static void panic_before(void *state) +{ + struct panic_test_fixture *fixture = state; + struct panic_data *pdata = get_panic_data_write(); + + ARG_UNUSED(state); + + fixture->saved_pdata = *pdata; +} + +static void panic_after(void *state) +{ + struct panic_test_fixture *fixture = state; + struct panic_data *pdata = get_panic_data_write(); + + ARG_UNUSED(state); + + *pdata = fixture->saved_pdata; +} + /** * @brief Test Suite: Verifies panic functionality. */ -ZTEST_SUITE(panic, drivers_predicate_post_main, NULL, NULL, NULL, NULL); +ZTEST_SUITE(panic, drivers_predicate_post_main, panic_test_setup, panic_before, + panic_after, NULL); /** * @brief TestPurpose: Verify panic set/get reason. -- cgit v1.2.1 From 2c454f266ced344aee57c4516bf9cb473441d9fa Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 10:58:03 -0600 Subject: Skyrim: Remove early board configs Now that keyboard works and we're power sequencing just fine, remove our early board configurations. BRANCH=None BUG=None TEST=zmake build skyrim Signed-off-by: Diana Z Change-Id: I6d58db3ade9b6ef1d59891c41c6718bed3ad1a90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712021 Commit-Queue: Robert Zieba Reviewed-by: Robert Zieba --- zephyr/projects/skyrim/prj_skyrim.conf | 2 -- 1 file changed, 2 deletions(-) diff --git a/zephyr/projects/skyrim/prj_skyrim.conf b/zephyr/projects/skyrim/prj_skyrim.conf index 2a524cf442..4f9696887b 100644 --- a/zephyr/projects/skyrim/prj_skyrim.conf +++ b/zephyr/projects/skyrim/prj_skyrim.conf @@ -8,8 +8,6 @@ CONFIG_BOARD_SKYRIM=y # TODO(b/215404321): Remove later in board development CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y -CONFIG_PLATFORM_EC_KEYBOARD_DEBUG=y -CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL=y # LED CONFIG_PLATFORM_EC_LED_COMMON=n -- cgit v1.2.1 From 7836f608e55ad0c6da22ac11edcc0f2a9d523bb2 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Tue, 21 Jun 2022 10:04:18 -0700 Subject: volteer: Disable 'flashwp' console commands to save space Just preserving the build at ToT. Do not cherry pick. BRANCH=none BUG=none TEST=make BOARD=volteer -j Before: 32 bytes in flash and 21600 bytes in RAM still available on volteer RO 204 bytes in flash and 21600 bytes in RAM still available on volteer RW After: 224 bytes in flash and 21600 bytes in RAM still available on volteer RO 356 bytes in flash and 21600 bytes in RAM still available on volteer RW Change-Id: I60451257736ec7a9e913c90f8f4859ea3d7ed11d Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715437 Reviewed-by: Diana Z --- board/volteer/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/volteer/board.h b/board/volteer/board.h index 936bc9ddc5..02b07c1f1d 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -163,6 +163,7 @@ #undef CONFIG_CMD_CBI #undef CONFIG_CMD_CHARGER #undef CONFIG_CMD_CHARGE_SUPPLIER_INFO +#undef CONFIG_CMD_FLASH_WP #undef CONFIG_CMD_HASH #undef CONFIG_CMD_IDLE_STATS #undef CONFIG_CMD_INA -- cgit v1.2.1 From 74047bd2d19977c1cd0579dd60449f92bd21e78d Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 09:01:58 -0700 Subject: board/fluffy: Remove CROSS_COMPILE from makefile The CROSS_COMPILE variable is set in core/cortex-m0/build.mk so it's unnecessary to set it again here. BRANCH=none BUG=b:234181908, b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I5139b163fbee33a00c6da08461cce2c1fbfcd84b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712188 Reviewed-by: Ting Shen --- board/fluffy/build.mk | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/fluffy/build.mk b/board/fluffy/build.mk index b6761a4692..63010ac889 100644 --- a/board/fluffy/build.mk +++ b/board/fluffy/build.mk @@ -10,9 +10,4 @@ CHIP:=stm32 CHIP_FAMILY:=stm32f0 CHIP_VARIANT:=stm32f07x -# Use coreboot-sdk -$(call set-option,CROSS_COMPILE_arm,\ - $(CROSS_COMPILE_coreboot_sdk_arm),\ - /opt/coreboot-sdk/bin/arm-eabi-) - board-y=board.o -- cgit v1.2.1 From fcb67abf10d9505939a9d858d20f3024775fe9f9 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 14 Jun 2022 09:50:26 -0700 Subject: Makefile: Make sure CROSS_COMPILE is set correctly When testing a change to set the default compiler to clang for dartmonkey, I encountered an error when building with "make proj-bloonchipper": ccache: error: execv of /opt/coreboot-sdk/bin/arm-eabi-clang failed: No such file or directory In this case the CC variable (defined in Makefile.toolchain as "CC=$(CCACHE) $(CROSS_COMPILE)$(cc-name))" had CROSS_COMPILE set to "/opt/coreboot-sdk/bin/arm-eabi-" (gcc toolchain) and cc-name set to "clang", which is not correct. The problem was that the Makefile has simply expanded variables (https://www.gnu.org/software/make/manual/html_node/Flavors.html#Flavors) that reference CC before the core/$(CORE)/build.mk is included (e.g., "_tsk_lst_ro" that uses CPP, which is defined as "CPP=$(CC) -E"). This change pulls the toolchain configuration out of core/$(CORE)/build.mk into a separate core/$(CORE)/toolchain.mk file that is included earlier in the top-level Makefile, which ensures that CC is defined before it is used by the simply expanded variables. BRANCH=none BUG=b:172020503, b:234181908 TEST=make proj-bloonchipper -j TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: Ia41d2de61ee786df044d484c146d6970de183562 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706036 Reviewed-by: Denis Brockus --- Makefile | 8 ++++++++ core/cortex-m/build.mk | 13 ------------- core/cortex-m/toolchain.mk | 15 +++++++++++++++ core/cortex-m0/build.mk | 12 ------------ core/cortex-m0/toolchain.mk | 15 +++++++++++++++ core/minute-ia/build.mk | 4 ---- core/minute-ia/toolchain.mk | 7 +++++++ core/nds32/build.mk | 6 ------ core/nds32/toolchain.mk | 9 +++++++++ core/riscv-rv32i/build.mk | 4 ---- core/riscv-rv32i/toolchain.mk | 7 +++++++ 11 files changed, 61 insertions(+), 39 deletions(-) create mode 100644 core/cortex-m/toolchain.mk create mode 100644 core/cortex-m0/toolchain.mk create mode 100644 core/minute-ia/toolchain.mk create mode 100644 core/nds32/toolchain.mk create mode 100644 core/riscv-rv32i/toolchain.mk diff --git a/Makefile b/Makefile index 3a36b91125..0602fd4abf 100644 --- a/Makefile +++ b/Makefile @@ -115,6 +115,14 @@ CFLAGS_BASEBOARD= endif include chip/$(CHIP)/build.mk +# The toolchain must be set before referencing any toolchain-related variables +# (CC, CPP, CXX, etc.) so that the correct toolchain is used. The CORE variable +# is set in the CHIP build file, so this include must come after including the +# CHIP build file. +ifneq ($(BOARD), host) +include core/$(CORE)/toolchain.mk +endif + # Create uppercase config variants, to avoid mixed case constants. # Also translate '-' to '_', so 'cortex-m' turns into 'CORTEX_M'. This must # be done before evaluating config.h. diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk index bcffe16e8d..04f8e45479 100644 --- a/core/cortex-m/build.mk +++ b/core/cortex-m/build.mk @@ -6,19 +6,6 @@ # Cortex-M4 core OS files build # - -ifeq ($(cc-name),gcc) -# coreboot sdk -CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- -else -# llvm sdk -CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi- -endif - -$(call set-option,CROSS_COMPILE,\ - $(CROSS_COMPILE_arm),\ - $(CROSS_COMPILE_ARM_DEFAULT)) - # FPU compilation flags CFLAGS_FPU-$(CONFIG_FPU)=-mfloat-abi=hard ifeq ($(cc-name),gcc) diff --git a/core/cortex-m/toolchain.mk b/core/cortex-m/toolchain.mk new file mode 100644 index 0000000000..736d4c7562 --- /dev/null +++ b/core/cortex-m/toolchain.mk @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +ifeq ($(cc-name),gcc) +# coreboot sdk +CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- +else +# llvm sdk +CROSS_COMPILE_ARM_DEFAULT:=armv7m-cros-eabi- +endif + +$(call set-option,CROSS_COMPILE,\ + $(CROSS_COMPILE_arm),\ + $(CROSS_COMPILE_ARM_DEFAULT)) diff --git a/core/cortex-m0/build.mk b/core/cortex-m0/build.mk index eab2a1eb1c..37ff34873b 100644 --- a/core/cortex-m0/build.mk +++ b/core/cortex-m0/build.mk @@ -6,18 +6,6 @@ # Cortex-M0 core OS files build # -ifeq ($(cc-name),gcc) -# coreboot sdk -CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- -else -# llvm sdk -CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi- -endif - -$(call set-option,CROSS_COMPILE,\ - $(CROSS_COMPILE_arm),\ - $(CROSS_COMPILE_ARM_DEFAULT)) - # CPU specific compilation flags CFLAGS_CPU+=-mthumb ifeq ($(cc-name),clang) diff --git a/core/cortex-m0/toolchain.mk b/core/cortex-m0/toolchain.mk new file mode 100644 index 0000000000..390dd6a7f2 --- /dev/null +++ b/core/cortex-m0/toolchain.mk @@ -0,0 +1,15 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +ifeq ($(cc-name),gcc) +# coreboot sdk +CROSS_COMPILE_ARM_DEFAULT:=/opt/coreboot-sdk/bin/arm-eabi- +else +# llvm sdk +CROSS_COMPILE_ARM_DEFAULT:=arm-none-eabi- +endif + +$(call set-option,CROSS_COMPILE,\ + $(CROSS_COMPILE_arm),\ + $(CROSS_COMPILE_ARM_DEFAULT)) diff --git a/core/minute-ia/build.mk b/core/minute-ia/build.mk index b51512c16e..b32f8164ea 100644 --- a/core/minute-ia/build.mk +++ b/core/minute-ia/build.mk @@ -6,10 +6,6 @@ # Minute-IA core build # -# Select Minute-IA bare-metal toolchain -$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\ - /opt/coreboot-sdk/bin/i386-elf-) - # FPU compilation flags CFLAGS_FPU-$(CONFIG_FPU)= diff --git a/core/minute-ia/toolchain.mk b/core/minute-ia/toolchain.mk new file mode 100644 index 0000000000..8fcfc28c78 --- /dev/null +++ b/core/minute-ia/toolchain.mk @@ -0,0 +1,7 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Select Minute-IA bare-metal toolchain +$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_i386),\ + /opt/coreboot-sdk/bin/i386-elf-) diff --git a/core/nds32/build.mk b/core/nds32/build.mk index ddd65c680b..e500846c44 100644 --- a/core/nds32/build.mk +++ b/core/nds32/build.mk @@ -6,12 +6,6 @@ # Andestar v3m architecture core OS files build # -# Set coreboot-sdk as the default toolchain for nds32 -NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf- - -# Select Andes bare-metal toolchain -$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE)) - # CPU specific compilation flags CFLAGS_CPU+=-march=v3m -Os LDFLAGS_EXTRA+=-mrelax diff --git a/core/nds32/toolchain.mk b/core/nds32/toolchain.mk new file mode 100644 index 0000000000..3d685ef2b6 --- /dev/null +++ b/core/nds32/toolchain.mk @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Set coreboot-sdk as the default toolchain for nds32 +NDS32_DEFAULT_COMPILE=/opt/coreboot-sdk/bin/nds32le-elf- + +# Select Andes bare-metal toolchain +$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE)) diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk index 7e5ce0e8a7..f558a91669 100644 --- a/core/riscv-rv32i/build.mk +++ b/core/riscv-rv32i/build.mk @@ -6,10 +6,6 @@ # RISC-V core OS files build # -# Select RISC-V bare-metal toolchain -$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ - /opt/coreboot-sdk/bin/riscv64-elf-) - # Enable FPU extension if config option of FPU is enabled. _FPU_EXTENSION=$(if $(CONFIG_FPU),f,) # Enable the 'M' extension if config option of RISCV_EXTENSION_M is enabled. diff --git a/core/riscv-rv32i/toolchain.mk b/core/riscv-rv32i/toolchain.mk new file mode 100644 index 0000000000..dd45daf120 --- /dev/null +++ b/core/riscv-rv32i/toolchain.mk @@ -0,0 +1,7 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Select RISC-V bare-metal toolchain +$(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_riscv),\ + /opt/coreboot-sdk/bin/riscv64-elf-) -- cgit v1.2.1 From 1436dbc2fd042842396cd2b2de4eae490c17b682 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Tue, 21 Jun 2022 00:19:56 -0600 Subject: test: drivers: fix test order dependency The motionsense host command tests all depend of the [0]th sensor to be considered active. This wasn't the case because the state of the machine was previously defaulted to SENSOR_ACTIVE_S0_S3. When shuffling it's possible that the EC will be in S5 during execution. This change could either force the EC to be in S0/S3, or set the active mask to include S5 (which is the approach this CL took) BRANCH=none BUG=b:233355058 TEST=zephyr.elf -seed=$(date +%s) Signed-off-by: Yuval Peress Change-Id: I5bc5e7ef1950b0be5217dc348c5b29c753db819d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716280 Reviewed-by: Jack Rosenthal --- zephyr/test/drivers/overlay.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index d8c92a53ef..e7002ba4a2 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -563,6 +563,7 @@ status = "okay"; label = "BMA255"; + active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_LID"; mutex = <&mutex_bma255>; port = <&i2c_accel>; -- cgit v1.2.1 From e8108d90b640c1407e5c90489f0dbbbbb9d8e3dd Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 11:58:24 -0600 Subject: Skyrim: Remove unconnected pin This pin is NC on more recent board versions. BRANCH=None BUG=b:231996265 TEST=zmake build skyrim Signed-off-by: Diana Z Change-Id: I865a45174829ad85ae1e3a6db931935124418bab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712022 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/skyrim.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 8b4b5505ad..91f4139186 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -44,10 +44,6 @@ gpios = <&gpioa 5 GPIO_INPUT>; }; /* TODO: Add interrupt handler */ - sc_0_int_l { - gpios = <&gpio6 3 GPIO_INPUT_PULL_UP>; - }; - /* TODO: Add interrupt handler */ usb_hub_fault_q_odl { gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; }; -- cgit v1.2.1 From ba22e4d87558a0db0a3bae9e6351f6e46f6d0c83 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Mon, 20 Jun 2022 16:36:33 +1000 Subject: ap_pwrseq: eSPI: Use eSPI channel ready callback Use the eSPI channel ready callback to invalidate the virtual wire status. It appeared that the eSPI bus reset callbacks could not be guaranteed to arrive in the correct order. Also display whether a signal is invalid in the powerindebug output. BUG=b:236561037 TEST=zmake build nivviks; flash & run BRANCH=none Signed-off-by: Andrew McRae Change-Id: I261b59884ecce71678ca825d9d29d37195ac9691 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711518 Reviewed-by: Peter Marheine --- zephyr/subsys/ap_pwrseq/signal_vw.c | 18 +++++++++--------- .../ap_pwrseq/x86_non_dsx_common_pwrseq_console.c | 8 +++++--- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/signal_vw.c b/zephyr/subsys/ap_pwrseq/signal_vw.c index de2756c137..53719a9c4f 100644 --- a/zephyr/subsys/ap_pwrseq/signal_vw.c +++ b/zephyr/subsys/ap_pwrseq/signal_vw.c @@ -40,9 +40,8 @@ DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_ESPI_SIGNAL) */ static atomic_t signal_data; /* - * Mask of valid signals. If the bus is reset, this is cleared, - * and when a signal is updated the associated bit is set to indicate - * the signal is valid. + * Mask of valid signals. A signal is considered valid once an + * initial value has been received for it. */ static atomic_t signal_valid; @@ -62,11 +61,12 @@ static void espi_handler(const struct device *dev, event.evt_type); break; - case ESPI_BUS_RESET: - /* - * Clear the signal valid mask. - */ - atomic_clear(&signal_valid); + case ESPI_BUS_EVENT_CHANNEL_READY: + /* Virtual wire channel is not ready, clear valid flag */ + if (event.evt_details == ESPI_CHANNEL_VWIRE && + !event.evt_data) { + atomic_clear(&signal_valid); + } break; case ESPI_BUS_EVENT_VWIRE_RECEIVED: @@ -103,7 +103,7 @@ void power_signal_vw_init(void) /* Configure handler for eSPI events */ espi_init_callback(&espi_cb, espi_handler, - ESPI_BUS_RESET | + ESPI_BUS_EVENT_CHANNEL_READY | ESPI_BUS_EVENT_VWIRE_RECEIVED); espi_add_callback(espi_dev, &espi_cb); /* diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c index e671e46113..77f8134d10 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c @@ -42,17 +42,19 @@ static int powerindebug_handler(const struct shell *shell, size_t argc, /* Print the mask */ current = power_get_signals(); - shell_fprintf(shell, SHELL_INFO, "power in: 0x%04x\n", current); - shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%04x\n", + shell_fprintf(shell, SHELL_INFO, "power in: 0x%05x\n", current); + shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%05x\n", power_get_debug()); /* Print the decode */ shell_fprintf(shell, SHELL_INFO, "bit meanings:\n"); for (i = 0; i < POWER_SIGNAL_COUNT; i++) { power_signal_mask_t mask = POWER_SIGNAL_MASK(i); + bool valid = (power_signal_get(i) >= 0); - shell_fprintf(shell, SHELL_INFO, " 0x%04x %d %s\n", + shell_fprintf(shell, SHELL_INFO, " 0x%05x %d%s %s\n", mask, (current & mask) ? 1 : 0, + valid ? " " : "!", power_signal_name(i)); } -- cgit v1.2.1 From a6f34df08307d25e7947f685a911d329d1aa647b Mon Sep 17 00:00:00 2001 From: "arthur.lin" Date: Tue, 21 Jun 2022 15:29:28 +0800 Subject: taniks: update fan table Update fan table for power on noise. BUG=b:215033682 BRANCH=none TEST=make buildall -j Signed-off-by: arthur.lin Change-Id: I7cad59825b9eb8370def8f1230a4dca0181aca4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716175 Reviewed-by: Boris Mittelberg --- board/taniks/sensors.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/taniks/sensors.c b/board/taniks/sensors.c index d480849036..e0fd53eb01 100644 --- a/board/taniks/sensors.c +++ b/board/taniks/sensors.c @@ -387,7 +387,7 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ }, \ .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_max = C_TO_K(70), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; @@ -417,7 +417,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ }, \ .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_max = C_TO_K(70), \ } __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; -- cgit v1.2.1 From 7aa9acd43cfd52041595b038717a513cca207431 Mon Sep 17 00:00:00 2001 From: Will Tsai Date: Wed, 15 Jun 2022 17:01:14 +0800 Subject: gimble: configure fan thermal_params Temp sensor not used will lead to 'thermal SHUTDOWN' when booting the system. Due to fixture limitation, we will only use main board in factory test proccess, which means the temp sensor(FAN) on daughter board will not being used. Here increase EC_TEMP_THRESH_HALT to avoid 'thermal SHUTDOWN' in case of the daughter board is not detected only. BUG=b:236222296 TEST=make -j BOARD=gimble BRANCH=none Signed-off-by: Will Tsai Change-Id: I6823de6358d189278013b8a1621a3257cd618c5c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707331 Reviewed-by: caveh jalali --- board/gimble/sensors.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c index 0e030846db..f39b9f2de2 100644 --- a/board/gimble/sensors.c +++ b/board/gimble/sensors.c @@ -11,6 +11,8 @@ #include "driver/accel_bma422.h" #include "driver/accelgyro_bmi_common.h" #include "driver/accelgyro_lsm6dsm.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" #include "gpio.h" #include "hooks.h" #include "keyboard_scan.h" @@ -357,6 +359,19 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; __maybe_unused static const struct ec_thermal_config thermal_inductor = THERMAL_INDUCTOR; +#define THERMAL_FAN_MISSING \ + { \ + .temp_host = { \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ + [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ + }, \ + .temp_host_release = { \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ + }, \ + } +__maybe_unused static const struct ec_thermal_config thermal_fan_missing = + THERMAL_FAN_MISSING; + /* this should really be "const" */ struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, @@ -364,4 +379,24 @@ struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_2_FAN] = THERMAL_INDUCTOR, [TEMP_SENSOR_3_CHARGER] = THERMAL_INDUCTOR, }; + +struct ec_thermal_config temp_sensor_2_fan_set[] = { + [TEMP_SENSOR_2_FAN] = THERMAL_FAN_MISSING, +}; + +static void config_thermal_params(void) +{ + int rv, val; + + rv = tcpc_addr_read16_no_lpm_exit(USBC_PORT_C1, + PS8XXX_I2C_ADDR1_FLAGS, TCPC_REG_VENDOR_ID, + &val); + + if (rv != 0) { + thermal_params[TEMP_SENSOR_2_FAN] = + temp_sensor_2_fan_set[TEMP_SENSOR_2_FAN]; + } +} +DECLARE_HOOK(HOOK_INIT, config_thermal_params, HOOK_PRIO_INIT_I2C + 1); + BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 1e103abc014688f70f7c1c704e64611381fa5855 Mon Sep 17 00:00:00 2001 From: ben chen Date: Mon, 13 Jun 2022 17:01:16 +0800 Subject: moonbuggy: enable ADS control interrupt enable interrupt handle power sequence control pin 5v: ADS_5VS_V2_ADP_PRESENT_L 12v: BJ_ADP_PRESENT_L BUG=b:211546881 BRANCH=cros/main TEST=build BOARD PASS and EE check is PASS. Change-Id: Iab2d83a3b6ea2248bbae3d786ac2910c06ac1c4d Signed-off-by: Ben Chen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711519 Reviewed-by: Keith Short --- board/moonbuggy/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/moonbuggy/board.c b/board/moonbuggy/board.c index cfe0121374..b5f51efc32 100644 --- a/board/moonbuggy/board.c +++ b/board/moonbuggy/board.c @@ -382,6 +382,11 @@ static void board_init(void) */ if (board_version < 2) button_disable_gpio(BUTTON_RECOVERY); + + /* ADS GPIO interrupt enable*/ + gpio_enable_interrupt(GPIO_ADS_5VS_V2_ADP_PRESENT_L); + gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L); + } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From d9875f2d8f632e09283cfb7b1d34236d404f4b1e Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Wed, 8 Jun 2022 17:58:42 +0100 Subject: zephyr: shim: ensure static shell priority matches the task one Set the static SHELL_THREAD_PRIORITY config default and add a build check to ensure that the atual value matches the one configured in the list of intended task priorities. This ensures that the shell task is running at the intended priority even on projects that do not call shell_init_from_work(). BRANCH=none BUG=none TEST=zmake build brya Signed-off-by: Fabio Baltieri Change-Id: Ie11f18b1135aee04386105a7a87b5c4b1ef0cf8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3696146 Commit-Queue: Andrew McRae Tested-by: CH Lin Reviewed-by: Abe Levkoy Reviewed-by: CH Lin --- zephyr/Kconfig.defaults | 6 ++++++ zephyr/shim/src/console.c | 3 +++ 2 files changed, 9 insertions(+) diff --git a/zephyr/Kconfig.defaults b/zephyr/Kconfig.defaults index a92971b3c7..6c776f188d 100644 --- a/zephyr/Kconfig.defaults +++ b/zephyr/Kconfig.defaults @@ -21,4 +21,10 @@ config THREAD_MAX_NAME_LEN config SHELL_PROMPT_UART default "ec:~$ " +config SHELL_THREAD_PRIORITY_OVERRIDE + default y + +config SHELL_THREAD_PRIORITY + default 12 # track EC_SHELL_PRIO + orsource "Kconfig.defaults-$(ARCH)" diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c index f8051d8638..f47136771d 100644 --- a/zephyr/shim/src/console.c +++ b/zephyr/shim/src/console.c @@ -34,6 +34,9 @@ #error Must select only one shell backend #endif +BUILD_ASSERT(EC_TASK_PRIORITY(EC_SHELL_PRIO) == CONFIG_SHELL_THREAD_PRIORITY, + "EC_SHELL_PRIO does not match CONFIG_SHELL_THREAD_PRIORITY."); + LOG_MODULE_REGISTER(shim_console, LOG_LEVEL_ERR); static const struct device *uart_shell_dev = -- cgit v1.2.1 From 2ba12477128cca9454ead7584d479f31943403e7 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Fri, 8 Apr 2022 09:54:27 +0800 Subject: vell: Configure FRS GPIOs for PPC BUG=b:236781082 BRANCH=none TEST=buildall Signed-off-by: Devin Lu Change-Id: I28ee57ae283f0853eed134473fe525cb144dd6af Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3577314 Reviewed-by: caveh jalali Commit-Queue: Devin Lu Tested-by: Devin Lu --- board/vell/gpio.inc | 8 ++++---- board/vell/usbc_config.c | 5 +++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/board/vell/gpio.inc b/board/vell/gpio.inc index 4c5b630658..6e0239fc12 100644 --- a/board/vell/gpio.inc +++ b/board/vell/gpio.inc @@ -142,23 +142,23 @@ GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) /* GPIO02_P1 to PU */ /* GPIO03_P1 to PU */ IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_OUT_LOW) IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) IOEX(USB_C1_RT_RST_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 2), GPIO_ODR_LOW) /* GPIO03_P2 to PU */ IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C1_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C1_FRS_EN, EXPIN(IOEX_C1_NCT38XX, 0, 6), GPIO_OUT_LOW) /* GPIO07_P2 to PU */ /* GPIO02_P1 to PU */ /* GPIO03_P1 to PU */ IOEX(USB_C2_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_OUT_LOW) IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_LOW) IOEX(USB_C3_RT_RST_ODL, EXPIN(IOEX_C3_NCT38XX, 0, 2), GPIO_ODR_LOW) /* GPIO03_P2 to PU */ IOEX(USB_C3_OC_ODL, EXPIN(IOEX_C3_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C3_FRS_EN, EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_LOW) +IOEX(USB_C3_FRS_EN, EXPIN(IOEX_C3_NCT38XX, 0, 6), GPIO_OUT_LOW) /* GPIO07_P2 to PU */ diff --git a/board/vell/usbc_config.c b/board/vell/usbc_config.c index 6da618b42e..d2d759cbb4 100644 --- a/board/vell/usbc_config.c +++ b/board/vell/usbc_config.c @@ -85,21 +85,25 @@ struct ppc_config_t ppc_chips[] = { [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0_C1_PPC, .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .frs_en = IOEX_USB_C0_FRS_EN, .drv = &syv682x_drv, }, [USBC_PORT_C1] = { .i2c_port = I2C_PORT_USB_C0_C1_PPC, .i2c_addr_flags = SYV682X_ADDR1_FLAGS, + .frs_en = IOEX_USB_C1_FRS_EN, .drv = &syv682x_drv, }, [USBC_PORT_C2] = { .i2c_port = I2C_PORT_USB_C2_C3_PPC, .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .frs_en = IOEX_USB_C2_FRS_EN, .drv = &syv682x_drv, }, [USBC_PORT_C3] = { .i2c_port = I2C_PORT_USB_C2_C3_PPC, .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .frs_en = IOEX_USB_C3_FRS_EN, .drv = &syv682x_drv, }, }; @@ -110,6 +114,7 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); struct ppc_config_t ppc_chips_old_c3 = { .i2c_port = I2C_PORT_USB_C2_C3_PPC, .i2c_addr_flags = SYV682X_ADDR3_FLAGS, + .frs_en = IOEX_USB_C3_FRS_EN, .drv = &syv682x_drv, }; -- cgit v1.2.1 From c151cd1758e5c381586392b293c7b5445bdf1607 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Fri, 8 Apr 2022 09:58:36 +0800 Subject: vell: Enable PPC controlled FRS BUG=b:236781082 BRANCH=none TEST=buildall TEST=Manually, With HDMI dock + AC on dock then remove AC. HDMI stay on. Signed-off-by: Devin Lu Change-Id: I1a1d9ec893d97fbce8d045fdd95a991642224764 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3577315 Reviewed-by: caveh jalali Tested-by: Devin Lu Commit-Queue: Devin Lu --- board/vell/board.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/vell/board.h b/board/vell/board.h index eabb09d75a..b7ce13760e 100644 --- a/board/vell/board.h +++ b/board/vell/board.h @@ -53,6 +53,8 @@ #define CONFIG_IO_EXPANDER_NCT38XX #define CONFIG_IO_EXPANDER_PORT_COUNT 4 +#define CONFIG_USB_PD_FRS_PPC + #define CONFIG_USBC_RETIMER_INTEL_BB #define CONFIG_USBC_PPC_SYV682X -- cgit v1.2.1 From 0ddbf1b899f2ad68eca09f072ad5243db20e7bbe Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Tue, 21 Jun 2022 14:11:27 -0700 Subject: zephy/mtlrvp: Remove Write Protect to allow for CBI setting changes Since mtlrvp is not a user platform disable WP so that the CBI settings can be changed by the user in order to debug different hardware configs. BUG=none BRANCH=none TEST=zmake mtlrvp verify that CBI settings can be changed via kernel Signed-off-by: Brandon Breitenstein Change-Id: I126a1601c2a6bb8a595ff5ba7cfe5655be46b48e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716795 Reviewed-by: Vijay P Hiremath Reviewed-by: RAJESH KUMAR Reviewed-by: Sam Hurst --- zephyr/projects/intelrvp/mtlrvp/prj.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf index 607bf3a9d1..ecd3751b90 100644 --- a/zephyr/projects/intelrvp/mtlrvp/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -16,6 +16,8 @@ CONFIG_EEPROM=y CONFIG_EEPROM_AT24=y CONFIG_EEPROM_SHELL=n CONFIG_PLATFORM_EC_CBI_EEPROM=y +CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y # USB-C and charging # Below config are disabled to successfully compile battery conf -- cgit v1.2.1 From 55d5b28b468d1e860066d6dc0c8d6e650eac01d0 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Sat, 18 Jun 2022 00:17:18 +0000 Subject: hook: Add HOOK_POWER_SUPPLY_CHANGE This patch adds HOOK_POWER_SUPPLY_CHANGE. It triggers when there is a change in the active charge port. BUG=None BRANCH=None TEST=buildall TEST=zephyr/firmware_builder.py --metrics /tmp/tmpb1k9vctu --code-coverage build Signed-off-by: Daisuke Nojiri Change-Id: I77fda265c323e4101c8cc95ed15be714b8989c85 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716790 Commit-Queue: Tim Wawrzynczak Reviewed-by: Tim Wawrzynczak --- common/charge_manager.c | 4 +++- common/hooks.c | 1 + core/cortex-m/ec.lds.S | 4 ++++ core/cortex-m0/ec.lds.S | 4 ++++ core/host/host_exe.lds | 4 ++++ core/minute-ia/ec.lds.S | 4 ++++ core/nds32/ec.lds.S | 4 ++++ core/riscv-rv32i/ec.lds.S | 4 ++++ include/hooks.h | 5 +++++ include/link_defs.h | 2 ++ zephyr/shim/include/hook_types.h | 2 +- 11 files changed, 36 insertions(+), 2 deletions(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index a1cc53fe59..9d90aa6e19 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -1001,9 +1001,11 @@ static void charge_manager_refresh(void) if (is_pd_port(updated_old_port)) pd_set_new_power_request(updated_old_port); - if (power_changed) + if (power_changed) { + hook_notify(HOOK_POWER_SUPPLY_CHANGE); /* notify host of power info change */ pd_send_host_event(PD_EVENT_POWER_CHANGE); + } } DECLARE_DEFERRED(charge_manager_refresh); diff --git a/common/hooks.c b/common/hooks.c index 061586c4cb..ed626d2638 100644 --- a/common/hooks.c +++ b/common/hooks.c @@ -63,6 +63,7 @@ static const struct hook_ptrs hook_list[] = { {__hooks_second, __hooks_second_end}, {__hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end}, {__hooks_usb_pd_connect, __hooks_usb_pd_connect_end}, + {__hooks_power_supply_change, __hooks_power_supply_change_end}, }; /* Times for deferrable functions */ diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index f85b262c18..896e49097b 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -309,6 +309,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index ce67760cf2..3321dd1b08 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -189,6 +189,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; diff --git a/core/host/host_exe.lds b/core/host/host_exe.lds index ab8d352ecc..0261624d30 100644 --- a/core/host/host_exe.lds +++ b/core/host/host_exe.lds @@ -113,6 +113,10 @@ SECTIONS { KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; *(.rodata.deferred) __deferred_funcs_end = .; diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S index beda1dbfae..60239d3680 100644 --- a/core/minute-ia/ec.lds.S +++ b/core/minute-ia/ec.lds.S @@ -156,6 +156,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index fbc5ceaafd..084c6f6b64 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -185,6 +185,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 1e629a5779..24b2fb68ef 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -233,6 +233,10 @@ SECTIONS KEEP(*(.rodata.HOOK_USB_PD_CONNECT)) __hooks_usb_pd_connect_end = .; + __hooks_power_supply_change = .; + KEEP(*(.rodata.HOOK_POWER_SUPPLY_CHANGE)) + __hooks_power_supply_change_end = .; + __deferred_funcs = .; KEEP(*(.rodata.deferred)) __deferred_funcs_end = .; diff --git a/include/hooks.h b/include/hooks.h index e629ffbd9b..ae450085d7 100644 --- a/include/hooks.h +++ b/include/hooks.h @@ -253,6 +253,11 @@ enum hook_type { */ HOOK_USB_PD_CONNECT, + /* + * Power supply change event. + */ + HOOK_POWER_SUPPLY_CHANGE, + #ifdef TEST_BUILD /* * Special hook types to be used by unit tests of the hooks diff --git a/include/link_defs.h b/include/link_defs.h index 79b1a99159..d0558b396a 100644 --- a/include/link_defs.h +++ b/include/link_defs.h @@ -82,6 +82,8 @@ extern const struct hook_data __hooks_usb_pd_disconnect[]; extern const struct hook_data __hooks_usb_pd_disconnect_end[]; extern const struct hook_data __hooks_usb_pd_connect[]; extern const struct hook_data __hooks_usb_pd_connect_end[]; +extern const struct hook_data __hooks_power_supply_change[]; +extern const struct hook_data __hooks_power_supply_change_end[]; /* Deferrable functions and firing times*/ extern const struct deferred_data __deferred_funcs[]; diff --git a/zephyr/shim/include/hook_types.h b/zephyr/shim/include/hook_types.h index bcd1d0119c..a44a7c11c2 100644 --- a/zephyr/shim/include/hook_types.h +++ b/zephyr/shim/include/hook_types.h @@ -47,6 +47,6 @@ HOOK_POWER_BUTTON_CHANGE, HOOK_BATTERY_SOC_CHANGE, \ HOOK_TYPES_USB_SUSPEND, HOOK_TICK, HOOK_SECOND, \ HOOK_USB_PD_DISCONNECT, HOOK_USB_PD_CONNECT, \ - HOOK_TYPES_TEST_BUILD) + HOOK_POWER_SUPPLY_CHANGE, HOOK_TYPES_TEST_BUILD) #endif -- cgit v1.2.1 From 3eddb22fbd23621f0636307a4d641f4b2edf3cdd Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Tue, 21 Jun 2022 10:48:04 -0600 Subject: flash_fp_mcu: remove config for nami-kernelnext nami-kernelnext config points to nami config. BUG=b:236639739 BRANCH=None TEST= run flash_fp_mcu on bard with nami-kernelnext, check that nami config is used Signed-off-by: Josie Nordrum Change-Id: Ic0fd2252dc3247d7f87246ec1ae1d84dc9738794 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715435 Commit-Queue: Josie Nordrum Reviewed-by: Craig Hesling Tested-by: Josie Nordrum --- util/flash_fp_mcu | 4 ---- 1 file changed, 4 deletions(-) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index 75a989e1f4..cc6e41080f 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -542,10 +542,6 @@ config_nami() { readonly GPIO_PWREN=395 } -config_nami-kernelnext() { - config_nami -} - config_nocturne() { readonly TRANSPORT="SPI" readonly DEVICE="/dev/spidev32765.0" -- cgit v1.2.1 From 7217db0090365bb30fd1c876108a7437a6eba3da Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Wed, 22 Jun 2022 18:28:51 +0800 Subject: osiris: Remove unused battery Remove unused battery BUG=b:229947325 BRANCH=none TEST=make BOARD=osiris Signed-off-by: Yu-An Chen Change-Id: I954b50983a6863dca64bf0474788fa957deab956 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716417 Commit-Queue: Parth Malkan Reviewed-by: Parth Malkan --- board/osiris/battery.c | 33 --------------------------------- board/osiris/board.h | 1 - 2 files changed, 34 deletions(-) diff --git a/board/osiris/battery.c b/board/osiris/battery.c index 61c0f7f886..3a43835ec6 100644 --- a/board/osiris/battery.c +++ b/board/osiris/battery.c @@ -33,39 +33,6 @@ * address, mask, and disconnect value need to be provided. */ const struct board_batt_params board_battery_info[] = { - /* - * TODO(b:229947325): Copy kano battery AP19B8M for early support, - * It should remove before FSI. - */ - /* LGC AP19B8M Battery Information */ - [BATTERY_AP19B8M] = { - .fuel_gauge = { - .manuf_name = "LGC KT0030G024", - .ship_mode = { - .reg_addr = 0x3A, - .reg_data = { 0xC574, 0xC574 }, - }, - .fet = { - .reg_addr = 0x43, - .reg_mask = 0x0001, - .disconnect_val = 0x0, - .cfet_mask = 0x0002, - .cfet_off_val = 0x0000, - } - }, - .batt_info = { - .voltage_max = 13350, - .voltage_normal = 11610, - .voltage_min = 9000, - .precharge_current = 256, - .start_charging_min_c = 0, - .start_charging_max_c = 50, - .charging_min_c = 0, - .charging_max_c = 60, - .discharging_min_c = -20, - .discharging_max_c = 75, - }, - }, /* COSMX AP22ABN Battery Information */ [BATTERY_COSMX_AP22ABN] = { .fuel_gauge = { diff --git a/board/osiris/board.h b/board/osiris/board.h index 292a540087..ffa8995389 100644 --- a/board/osiris/board.h +++ b/board/osiris/board.h @@ -167,7 +167,6 @@ enum temp_sensor_id { }; enum battery_type { - BATTERY_AP19B8M, BATTERY_COSMX_AP22ABN, BATTERY_TYPE_COUNT }; -- cgit v1.2.1 From 4ed8f1c8eb453f9e7b306f4c9ee888da6e92d840 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Thu, 9 Jun 2022 16:11:32 -0700 Subject: tcpmv2: debug: Add console command to print CC state BUG=none BRANCH=none TEST=Manually tested on MTLRVP 'pd cc' prints correct CC state Change-Id: Ic1b4b697ed3ed99e8940fd3c1202f8325cd178ea Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3698274 Reviewed-by: Wai-Hong Tam --- common/usbc/usb_pd_console.c | 3 +++ test/usb_pd_console.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/common/usbc/usb_pd_console.c b/common/usbc/usb_pd_console.c index 6b1ea259eb..23a02b31e7 100644 --- a/common/usbc/usb_pd_console.c +++ b/common/usbc/usb_pd_console.c @@ -185,6 +185,8 @@ int command_pd(int argc, char **argv) cflush(); } else if (!strcasecmp(argv[2], "srccaps")) { pd_srccaps_dump(port); + } else if (!strcasecmp(argv[2], "cc")) { + ccprintf("Port C%d CC%d\n", port, pd_get_task_cc_state(port)); } if (IS_ENABLED(CONFIG_CMD_PD_TIMER) && @@ -203,6 +205,7 @@ DECLARE_CONSOLE_COMMAND(pd, command_pd, #endif "\n\t state" "\n\t srccaps" + "\n\t cc" #ifdef CONFIG_CMD_PD_TIMER "\n\t timer" #endif /* CONFIG_CMD_PD_TIMER */ diff --git a/test/usb_pd_console.c b/test/usb_pd_console.c index c762bebfc8..0c8ad63542 100644 --- a/test/usb_pd_console.c +++ b/test/usb_pd_console.c @@ -241,6 +241,11 @@ enum try_src_override_t tc_get_try_src_override(void) return try_src_override; } +enum pd_cc_states pd_get_task_cc_state(int port) +{ + return PD_CC_NONE; +} + static int test_command_pd_dump(void) { int argc = 3; -- cgit v1.2.1 From f3cb408576e0dde343330a46ae1738bbd9b8caf4 Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Tue, 21 Jun 2022 15:24:56 -0600 Subject: zephyr:test: Add tests for EC_CMD_HOST_EVENT command Validate permutations of EC_CMD_HOST_EVENT. BUG=b:236161217 BRANCH=none TEST=zmake test test-drivers and shuffled with arg -test="host_cmd_host_event_commands::*" Signed-off-by: Al Semjonovs Change-Id: Id8776922c5b0a09d786339a8e46c1a72e2109695 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716793 Reviewed-by: Aaron Massey Commit-Queue: Aaron Massey --- common/host_event_commands.c | 2 +- include/lpc.h | 7 + zephyr/test/drivers/CMakeLists.txt | 1 + .../drivers/src/host_cmd/host_event_commands.c | 190 +++++++++++++++++++++ 4 files changed, 199 insertions(+), 1 deletion(-) create mode 100644 zephyr/test/drivers/src/host_cmd/host_event_commands.c diff --git a/common/host_event_commands.c b/common/host_event_commands.c index 177e7cb877..2a008c6a78 100644 --- a/common/host_event_commands.c +++ b/common/host_event_commands.c @@ -114,7 +114,7 @@ static host_event_t lpc_get_all_host_event_masks(void) return or_mask; } -static void lpc_set_host_event_state(host_event_t events) +test_export_static void lpc_set_host_event_state(host_event_t events) { if (events == lpc_host_events) return; diff --git a/include/lpc.h b/include/lpc.h index 2a69cbced8..58894fa2f2 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -89,6 +89,13 @@ enum lpc_host_event_type { */ host_event_t lpc_get_host_events(void); +#ifdef TEST_BUILD +/** + * Set host events. + */ +void lpc_set_host_event_state(host_event_t events); +#endif + /** * Get host events that are set based on the type provided. * diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index 33163427b5..e5a92e4463 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -33,6 +33,7 @@ target_sources(app PRIVATE src/cros_cbi.c src/espi.c src/gpio.c + src/host_cmd/host_event_commands.c src/host_cmd/motion_sense.c src/integration/usbc/usb.c src/integration/usbc/usb_20v_3a_pd_charger.c diff --git a/zephyr/test/drivers/src/host_cmd/host_event_commands.c b/zephyr/test/drivers/src/host_cmd/host_event_commands.c new file mode 100644 index 0000000000..fec550e3c1 --- /dev/null +++ b/zephyr/test/drivers/src/host_cmd/host_event_commands.c @@ -0,0 +1,190 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include "include/lpc.h" +#include "test/drivers/test_state.h" +#include "test/drivers/utils.h" + +struct host_cmd_host_event_commands_fixture { + host_event_t lpc_host_events; + host_event_t lpc_host_event_mask[LPC_HOST_EVENT_COUNT]; +}; + +static void *host_cmd_host_event_commands_setup(void) +{ + static struct host_cmd_host_event_commands_fixture fixture = { 0 }; + + return &fixture; +} + +static void host_cmd_host_event_commands_before(void *fixture) +{ + struct host_cmd_host_event_commands_fixture *f = fixture; + + f->lpc_host_events = lpc_get_host_events(); + + for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) { + f->lpc_host_event_mask[i] = lpc_get_host_events_by_type(i); + } +} + +static void host_cmd_host_event_commands_after(void *fixture) +{ + struct host_cmd_host_event_commands_fixture *f = fixture; + + lpc_set_host_event_state(f->lpc_host_events); + + for (int i = 0; i < LPC_HOST_EVENT_COUNT; i++) { + lpc_set_host_event_mask(i, f->lpc_host_event_mask[i]); + } +} + +ZTEST_SUITE(host_cmd_host_event_commands, drivers_predicate_post_main, + host_cmd_host_event_commands_setup, + host_cmd_host_event_commands_before, + host_cmd_host_event_commands_after, NULL); + +static enum ec_status host_event_cmd_helper(enum ec_host_event_action action, + uint8_t mask, + struct ec_response_host_event *r) +{ + enum ec_status ret_val; + + struct ec_params_host_event params = { + .action = action, + .mask_type = mask, + }; + struct host_cmd_handler_args args = + BUILD_HOST_COMMAND(EC_CMD_HOST_EVENT, 0, *r, params); + + ret_val = host_command_process(&args); + + return ret_val; +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT invalid host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_invalid_cmd) +{ + enum ec_status ret_val; + struct ec_response_host_event result = { 0 }; + + ret_val = host_event_cmd_helper(0xFF, 0, + &result); + + zassert_equal(ret_val, EC_RES_INVALID_PARAM, + "Expected=%d, returned=%d", + EC_RES_INVALID_PARAM, ret_val); +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT get host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_get_cmd) +{ + enum ec_status ret_val; + struct ec_response_host_event result = { 0 }; + struct { + uint8_t mask; + enum ec_status result; + } event_get[] = { + { EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_B, EC_RES_SUCCESS }, +#ifdef CONFIG_HOSTCMD_X86 + { EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS }, +#ifdef CONFIG_POWER_S0IX + { EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS }, +#endif /* CONFIG_POWER_S0IX */ + { EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS }, + { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS }, +#endif /* CONFIG_HOSTCMD_X86 */ + { 0xFF, EC_RES_INVALID_PARAM }, + }; + + for (int i = 0; i < ARRAY_SIZE(event_get); i++) { + ret_val = host_event_cmd_helper(EC_HOST_EVENT_GET, + event_get[i].mask, &result); + zassert_equal(ret_val, event_get[i].result, + "[%d] Expected=%d, returned=%d", i, + event_get[i].result, ret_val); + } +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT set host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_set_cmd) +{ + enum ec_status ret_val; + struct ec_response_host_event result = { 0 }; + struct { + uint8_t mask; + enum ec_status result; + } event_set[] = { + { EC_HOST_EVENT_MAIN, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_B, EC_RES_ACCESS_DENIED }, +#ifdef CONFIG_HOSTCMD_X86 + { EC_HOST_EVENT_SCI_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_SMI_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_SUCCESS }, + { EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_SUCCESS }, +#ifdef CONFIG_POWER_S0IX + { EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_SUCCESS }, +#endif /* CONFIG_POWER_S0IX */ + { EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_SUCCESS }, + { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_SUCCESS }, +#endif /* CONFIG_HOSTCMD_X86 */ + { 0xFF, EC_RES_INVALID_PARAM }, + }; + + for (int i = 0; i < ARRAY_SIZE(event_set); i++) { + ret_val = host_event_cmd_helper(EC_HOST_EVENT_SET, + event_set[i].mask, &result); + zassert_equal(ret_val, event_set[i].result, + "[%d] Expected=%d, returned=%d", i, + event_set[i].result, ret_val); + } +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT clear host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_cmd) +{ + enum ec_status ret_val; + struct ec_response_host_event result = { 0 }; + struct { + uint8_t mask; + enum ec_status result; + } event_set[] = { + { EC_HOST_EVENT_MAIN, EC_RES_SUCCESS }, + { EC_HOST_EVENT_B, EC_RES_SUCCESS }, +#ifdef CONFIG_HOSTCMD_X86 + { EC_HOST_EVENT_SCI_MASK, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_SMI_MASK, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_ALWAYS_REPORT_MASK, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_ACTIVE_WAKE_MASK, EC_RES_ACCESS_DENIED }, +#ifdef CONFIG_POWER_S0IX + { EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX, EC_RES_ACCESS_DENIED }, +#endif /* CONFIG_POWER_S0IX */ + { EC_HOST_EVENT_LAZY_WAKE_MASK_S3, EC_RES_ACCESS_DENIED }, + { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, EC_RES_ACCESS_DENIED }, +#endif /* CONFIG_HOSTCMD_X86 */ + { 0xFF, EC_RES_INVALID_PARAM }, + }; + + for (int i = 0; i < ARRAY_SIZE(event_set); i++) { + ret_val = host_event_cmd_helper(EC_HOST_EVENT_CLEAR, + event_set[i].mask, &result); + zassert_equal(ret_val, event_set[i].result, + "Expected [%d] result=%d, returned=%d", i, + event_set[i].result, ret_val); + } +} -- cgit v1.2.1 From 786e5b1c32ae2faaa0b6a7fd5bd186036d9e1476 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 10 Jun 2022 15:53:50 -0600 Subject: Skyrim: Populate USB fault interrupts Fill in the information for USB fault interrupts. Any interrupt going low should trigger the fault signal to the SoC. BRANCH=None BUG=b:231996265 TEST=on skyrim, ensure SoC fault signal follows input fault signals Signed-off-by: Diana Z Change-Id: I9559eadf043c1fb47eeacd3a740bad1b5222699c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3700708 Commit-Queue: Robert Zieba Reviewed-by: Robert Zieba --- zephyr/projects/skyrim/gpio.dts | 6 ++---- zephyr/projects/skyrim/interrupts.dts | 15 +++++++++++++++ zephyr/projects/skyrim/skyrim.dts | 5 ++--- zephyr/projects/skyrim/usbc_config.c | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-) diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index a06bb070ab..27e21d8764 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -206,8 +206,7 @@ gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>; enum-name = "IOEX_EN_PP5000_USB_A0_VBUS"; }; - /* TODO: figure out interrupts */ - usb_a0_fault_odl { + ioex_usb_a0_fault_odl: usb_a0_fault_odl { gpios = <&ioex_c0_port1 6 GPIO_INPUT>; enum-name = "IOEX_USB3_A0_FAULT_L"; }; @@ -249,8 +248,7 @@ gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>; enum-name = "IOEX_EN_PP5000_USB_A1_VBUS_DB"; }; - /* TODO: figure out interrupts */ - usb_a1_fault_db_odl { + ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl { gpios = <&ioex_c1_port1 6 GPIO_INPUT>; enum-name = "IOEX_USB_A1_FAULT_DB_ODL"; }; diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index 59507f8081..3d263c455e 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -52,6 +52,16 @@ flags = ; handler = "button_interrupt"; }; + int_usb_a0_fault: a0_fault { + irq-pin = <&ioex_usb_a0_fault_odl>; + flags = ; + handler = "usb_fault_interrupt"; + }; + int_usb_a1_fault: a1_fault { + irq-pin = <&ioex_usb_a1_fault_db_odl>; + flags = ; + handler = "usb_fault_interrupt"; + }; int_usb_c0_tcpc: usb_c0_tcpc { irq-pin = <&gpio_usb_c0_tcpc_int_odl>; flags = ; @@ -82,6 +92,11 @@ flags = ; handler = "bc12_interrupt"; }; + int_usb_hub_fault: hub_fault { + irq-pin = <&gpio_usb_hub_fault_q_odl>; + flags = ; + handler = "usb_fault_interrupt"; + }; int_accel_gyro: accel_gyro { irq-pin = <&gpio_accel_gyro_int_l>; flags = ; diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 91f4139186..0b2afc83a5 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -12,7 +12,7 @@ named-gpios { /* Skyrim-specific GPIO customizations */ - usb_fault_odl { + gpio_usb_fault_odl: usb_fault_odl { gpios = <&gpio5 0 GPIO_ODR_HIGH>; }; gpio_en_pwr_s3: en_pwr_s3 { @@ -43,8 +43,7 @@ pcore_ocp_r_l { gpios = <&gpioa 5 GPIO_INPUT>; }; - /* TODO: Add interrupt handler */ - usb_hub_fault_q_odl { + gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { gpios = <&gpioe 5 GPIO_INPUT_PULL_UP>; }; gpio_pg_lpddr5_s3_od: pg_lpddr5_s3_od { diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index fe60db2a69..0f85062670 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -70,6 +70,25 @@ static void usbc_interrupt_init(void) } DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); +static void usb_fault_interrupt_init(void) +{ + /* Enable USB fault interrupts when we hit S5 */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_fault_interrupt_init, HOOK_PRIO_DEFAULT); + +static void usb_fault_interrupt_disable(void) +{ + /* Disable USB fault interrupts leaving S5 */ + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_hub_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a0_fault)); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_a1_fault)); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_fault_interrupt_disable, + HOOK_PRIO_DEFAULT); + struct ppc_config_t ppc_chips[] = { [USBC_PORT_C0] = { /* Device does not talk I2C */ @@ -405,6 +424,19 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, /* TODO: sbu_fault_interrupt from io expander */ +void usb_fault_interrupt(enum gpio_signal signal) +{ + int out; + + CPRINTSUSB("USB fault(%d), alerting the SoC", signal); + out = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) + && gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) + && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl)); + + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out); +} + /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ #define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 static void set_ac_prochot(void) -- cgit v1.2.1 From 824f1ef0231bfbe1566cb91761b476d061815c95 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 10 Jun 2022 16:56:06 -0600 Subject: Skyrim: Enable SBU fault interrupts Enable the SBU fault interrupts, and treat them as we do for guybrush with a call to the OCP module. BRANCH=None BUG=b:231996265 TEST=zmake build skyrim Signed-off-by: Diana Z Change-Id: Iaedfeee53f4b2aaec97daec44728bc78d91beb43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3700709 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/gpio.dts | 6 ++---- zephyr/projects/skyrim/interrupts.dts | 10 ++++++++++ zephyr/projects/skyrim/usbc_config.c | 12 ++++++++++-- 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index 27e21d8764..56448288a6 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -197,8 +197,7 @@ gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C0_PPC_ILIM_3A_EN"; }; - /* TODO: figure out interrupts */ - usb_c0_sbu_fault_odl { + ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { gpios = <&ioex_c0_port1 2 GPIO_INPUT>; enum-name = "IOEX_USB_C0_FAULT_ODL"; }; @@ -239,8 +238,7 @@ gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>; enum-name = "IOEX_USB_C1_PPC_ILIM_3A_EN"; }; - /* TODO: figure out interrupts */ - usb_c1_sbu_fault_odl { + ioex_usb_c1_sbu_fault_odl: usb_c1_sbu_fault_odl { gpios = <&ioex_c1_port1 2 GPIO_INPUT>; enum-name = "IOEX_USB_C1_FAULT_ODL"; }; diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index 3d263c455e..d65de0b791 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -62,6 +62,16 @@ flags = ; handler = "usb_fault_interrupt"; }; + int_usb_c0_sbu_fault: c0_sbu_fault { + irq-pin = <&ioex_usb_c0_sbu_fault_odl>; + flags = ; + handler = "sbu_fault_interrupt"; + }; + int_usb_c1_sbu_fault: c1_sbu_fault { + irq-pin = <&ioex_usb_c1_sbu_fault_odl>; + flags = ; + handler = "sbu_fault_interrupt"; + }; int_usb_c0_tcpc: usb_c0_tcpc { irq-pin = <&gpio_usb_c0_tcpc_int_odl>; flags = ; diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index 0f85062670..c4b2f953ae 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -66,7 +66,9 @@ static void usbc_interrupt_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); - /* TODO: Enable SBU fault interrupts (io expander )*/ + /* Enable SBU fault interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_sbu_fault)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_sbu_fault)); } DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); @@ -422,7 +424,13 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, charge_mv); } -/* TODO: sbu_fault_interrupt from io expander */ +void sbu_fault_interrupt(enum gpio_signal signal) +{ + int port = signal == IOEX_USB_C1_FAULT_ODL ? 1 : 0; + + CPRINTSUSB("C%d: SBU fault", port); + pd_handle_overcurrent(port); +} void usb_fault_interrupt(enum gpio_signal signal) { -- cgit v1.2.1 From bc21e2c8e9baeff73bf2b50b2247dbf0336de044 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 13:22:05 -0600 Subject: Skyrim: Fill in SoC's PD interrupt Fill in the PD interrupt from the SoC. Currently, we don't have any expected use-cases for it, so just log. BRANCH=None BUG=b:231996265 TEST=zmake build skyrim Signed-off-by: Diana Z Change-Id: I314d2114da01cb99785335cd70f64a1b69853562 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712023 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/interrupts.dts | 5 +++++ zephyr/projects/skyrim/skyrim.dts | 3 +-- zephyr/projects/skyrim/usbc_config.c | 9 +++++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index d65de0b791..14a01c8402 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -107,6 +107,11 @@ flags = ; handler = "usb_fault_interrupt"; }; + int_usb_pd_soc: usb_pd_soc { + irq-pin = <&gpio_ec_i2c_usbc_pd_int>; + flags = ; + handler = "usb_pd_soc_interrupt"; + }; int_accel_gyro: accel_gyro { irq-pin = <&gpio_accel_gyro_int_l>; flags = ; diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 0b2afc83a5..ebccda5eb9 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -21,8 +21,7 @@ gpio_pg_groupc_s0_od: pg_groupc_s0_od { gpios = <&gpiof 0 GPIO_INPUT>; }; - /* TODO: Add interrupt handler */ - ec_i2c_usbc_pd_int { + gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { gpios = <&gpioa 3 GPIO_INPUT>; }; /* TODO: Add interrupt handler */ diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index c4b2f953ae..c631e92892 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -445,6 +445,15 @@ void usb_fault_interrupt(enum gpio_signal signal) gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out); } +void usb_pd_soc_interrupt(enum gpio_signal signal) +{ + /* + * This interrupt is unexpected with our use of the SoC mux, so just log + * it as a point of interest. + */ + CPRINTSUSB("SOC PD Interrupt"); +} + /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ #define SKYRIM_AC_PROCHOT_CURRENT_MA 3328 static void set_ac_prochot(void) -- cgit v1.2.1 From f5dfa5378ab30df20ccc40d1a30d3bf635432d48 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 13:45:18 -0600 Subject: Skyrim: Enable SoC OCP and thermal interrupts Enable interrupts for SoC OCP and thermal warnings, and shutdown on each with a console print to log the scenario. BRANCH=None BUG=b:231996265 TEST=on skyrim, run a normal boot/shutdown sequence and verify neither interrupt is erroneously detected Signed-off-by: Diana Z Change-Id: Ic5af489965a6a2e88e5eba23e35d13bdfb1bdb8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712024 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/interrupts.dts | 10 ++++++++++ zephyr/projects/skyrim/power_signals.c | 29 +++++++++++++++++++++++++++++ zephyr/projects/skyrim/skyrim.dts | 6 ++---- 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index 14a01c8402..c72e468b58 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -42,6 +42,16 @@ flags = ; handler = "baseboard_set_en_pwr_pcore"; }; + int_soc_pcore_ocp: soc_pcore_ocp { + irq-pin = <&gpio_pcore_ocp_r_l>; + flags = ; + handler = "baseboard_soc_pcore_ocp"; + }; + int_soc_thermtrip: soc_thermtrip { + irq-pin = <&gpio_soc_thermtrip_odl>; + flags = ; + handler = "baseboard_soc_thermtrip"; + }; int_volume_up: volume_up { irq-pin = <&gpio_volup_btn_odl>; flags = ; diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index e85cea1f04..f23d6d01ea 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -76,9 +76,26 @@ static void baseboard_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3)); + + /* Enable thermtrip interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip)); } DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); +static void baseboard_resume(void) +{ + /* Enable Pcore OCP interrupt, which is powered in S0 */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_resume, HOOK_PRIO_DEFAULT); + +static void baseboard_suspend(void) +{ + /* Disable Pcore OCP interrupt */ + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_suspend, HOOK_PRIO_DEFAULT); + /** * b/227296844: On G3->S5, wait for RSMRST_L to be deasserted before asserting * PCH_PWRBTN_L. This can be as long as ~65ms after cold boot. Then wait an @@ -184,3 +201,15 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal) /* Chain off the normal power signal interrupt handler */ power_signal_interrupt(signal); } + +void baseboard_soc_thermtrip(enum gpio_signal signal) +{ + ccprints("SoC thermtrip reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); +} + +void baseboard_soc_pcore_ocp(enum gpio_signal signal) +{ + ccprints("SoC Pcore OCP reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); +} diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index ebccda5eb9..5fc8b52907 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -24,8 +24,7 @@ gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { gpios = <&gpioa 3 GPIO_INPUT>; }; - /* TODO: Add interrupt handler */ - soc_thermtrip_odl { + gpio_soc_thermtrip_odl: soc_thermtrip_odl { gpios = <&gpio9 5 GPIO_INPUT>; }; gpio_hub_rst: hub_rst { @@ -38,8 +37,7 @@ gpio_ec_soc_pwr_good: ec_soc_pwr_good { gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; }; - /* TODO: Add interrupt handler to shut down */ - pcore_ocp_r_l { + gpio_pcore_ocp_r_l: pcore_ocp_r_l { gpios = <&gpioa 5 GPIO_INPUT>; }; gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { -- cgit v1.2.1 From d733c6b1359b81465493c4b9414ff7ae4f470b32 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Wed, 22 Jun 2022 12:00:57 -0700 Subject: flash_ec: improve diagnostics output and stop earlier on gsc servo errors In case there is a problem for servod connecting over CCD the script keeps going using 'neither' as the CCD device type, which makes no sense. Quit the script as soon as the device type is reported as 'neither', also show the device type in the log when connection is successful. BUG=none TEST=verified that the script exits early and properly reports the device type problem when servod fails to properly connect over CCd. Signed-off-by: Vadim Bendebury Change-Id: I52d227d98a434ff9ddbd0c7aad3111a391feb1fe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3718839 Reviewed-by: Jett Rink --- util/flash_ec | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/flash_ec b/util/flash_ec index 7cb4ebcda8..7b46353c81 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -399,6 +399,9 @@ SERVO_TYPE="$(dut_control_get servo_type || :)" if [[ "${SERVO_TYPE}" =~ ^servo_v4(p1)?_with_.*$ ]]; then ACTIVE_DEVICE="$(dut_control_get active_dut_controller)" + if [[ ${ACTIVE_DEVICE} == neither ]]; then + die "Could not determine servo V4 active device" + fi else ACTIVE_DEVICE="${SERVO_TYPE}" fi @@ -1260,7 +1263,7 @@ function dut_i2c_dev() { local has_i2c_pseudo="$(dut_control_get_or_die \ "${ACTIVE_DEVICE}_i2c_pseudo_is_running")" if [[ "${has_i2c_pseudo}" == False ]]; then - error "i2c-pseudo module is not running." + error "i2c-pseudo module is not running on ${ACTIVE_DEVICE}." error "Please follow https://chromium.googlesource.com/chromiumos/platform/ec/+/HEAD/util/iteflash.md#i2c-pseudo" die "to install i2c-pseudo module." fi -- cgit v1.2.1 From 9015b4392d6a46db120ee5f59e0e13f0710bc7be Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Wed, 22 Jun 2022 17:26:14 +0000 Subject: TCPMV2: Notify AP of cable identity when connected to non-PD partners If a non-PD sink is connected to a USB-C port using a PD cable, the EC will discover the cable's identity. But, once it fails partner discovery it will set state to PE_SRC_DISABLED without notifying the AP about the cable. This CL updates the PE to notify the AP of cable discovery if the SOP' identity was discovered before source discovery failure caused by a partner not supporting USB PD. BUG=b:235534422 TEST=make try_build_boards and make runhosttests. BRANCH=None Signed-off-by: Jameson Thies Change-Id: I1e7d042cdf0fb5194c3334c8a4f8680579fe2e68 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3717919 Reviewed-by: Diana Z Reviewed-by: Abe Levkoy --- common/usbc/usb_pe_drp_sm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index baa2c98ec8..3d01a74b95 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -2336,6 +2336,17 @@ static void pe_src_discovery_run(int port) set_state_pe(port, PE_SRC_SEND_CAPABILITIES); return; } else if (!PE_CHK_FLAG(port, PE_FLAGS_PD_CONNECTION)) { + /* + * Cable identity may be discovered without a PD + * contract in place. If it has been discovered, notify + * the AP. + */ + if (pd_get_identity_discovery( + port, TCPCI_MSG_SOP_PRIME) == PD_DISC_COMPLETE) { + pd_notify_event( + port, PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + } + set_state_pe(port, PE_SRC_DISABLED); return; } -- cgit v1.2.1 From a284032df14d69a5f491b313f13deae4cf79d117 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 15:08:40 -0600 Subject: USB Mux: Add feature flag for AP mux setting Add a new feature flag to indicate when the AP is permitted to perform mux sets on a board. BRANCH=None BUG=b:208882941 TEST=on nipperkin with DNS patch, ensure feature flag is reported Signed-off-by: Diana Z Change-Id: I62c236ee43fc634f9d25d96918ce64bdc8cb2341 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712025 Reviewed-by: Abe Levkoy Commit-Queue: Abe Levkoy --- common/ec_features.c | 3 +++ include/ec_commands.h | 4 ++++ util/ectool.c | 1 + 3 files changed, 8 insertions(+) diff --git a/common/ec_features.c b/common/ec_features.c index 2147c1b48a..6b84f6d2df 100644 --- a/common/ec_features.c +++ b/common/ec_features.c @@ -149,6 +149,9 @@ uint32_t get_feature_flags1(void) #endif #ifdef CONFIG_POWER_S4_RESIDENCY | EC_FEATURE_MASK_1(EC_FEATURE_S4_RESIDENCY) +#endif +#ifdef CONFIG_USB_MUX_AP_CONTROL + | EC_FEATURE_MASK_1(EC_FEATURE_TYPEC_AP_MUX_SET) #endif ; return board_override_feature_flags1(result); diff --git a/include/ec_commands.h b/include/ec_commands.h index b11b34b5fd..6e8a3e40c9 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1518,6 +1518,10 @@ enum ec_feature_code { * The EC supports entering and residing in S4. */ EC_FEATURE_S4_RESIDENCY = 44, + /* + * The EC supports the AP directing mux sets for the board. + */ + EC_FEATURE_TYPEC_AP_MUX_SET = 45, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) diff --git a/util/ectool.c b/util/ectool.c index 51de0c1fcc..589923d574 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -913,6 +913,7 @@ static const char * const ec_feature_names[] = { [EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK] = "AP ack for Type-C mux configuration", [EC_FEATURE_S4_RESIDENCY] = "S4 residency", + [EC_FEATURE_TYPEC_AP_MUX_SET] = "AP directed mux sets", }; int cmd_inventory(int argc, char *argv[]) -- cgit v1.2.1 From 5587a305bc8a29474258b80703ec02185ca570c4 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 17 Jun 2022 15:14:30 -0600 Subject: USB Mux: Remove TODO for mux polarity The EC will be the one to handle polarity, so filter out this bit from any host command sets and use the EC's detected polarity instead. BRANCH=None BUG=b:208882941 TEST=make -j buildall Signed-off-by: Diana Z Change-Id: I2732a225307aa11681dcb2ecf29a6604756a0ca9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712026 Reviewed-by: Abe Levkoy --- common/usbc/usb_pd_host.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/common/usbc/usb_pd_host.c b/common/usbc/usb_pd_host.c index d6bd61057f..01d0d1bb7f 100644 --- a/common/usbc/usb_pd_host.c +++ b/common/usbc/usb_pd_host.c @@ -111,6 +111,7 @@ __overridable enum ec_status static enum ec_status hc_typec_control(struct host_cmd_handler_args *args) { const struct ec_params_typec_control *p = args->params; + mux_state_t mode; if (p->port >= board_get_usb_pd_port_count()) return EC_RES_INVALID_PARAM; @@ -127,12 +128,14 @@ static enum ec_status hc_typec_control(struct host_cmd_handler_args *args) case TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY: return board_set_tbt_ufp_reply(p->port, p->tbt_ufp_reply); case TYPEC_CONTROL_COMMAND_USB_MUX_SET: + /* The EC will fill in polarity, so filter flip out */ + mode = p->mux_params.mux_flags & ~USB_PD_MUX_POLARITY_INVERTED; + if (!IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL)) return EC_RES_INVALID_PARAM; - /* TODO: Check if AP wants to set usb mode or polarity */ + usb_mux_set_single(p->port, p->mux_params.mux_index, - p->mux_params.mux_flags, - USB_SWITCH_CONNECT, + mode, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(p->port))); return EC_RES_SUCCESS; default: -- cgit v1.2.1 From b4de505ca406a547282ed2ac4c06e6093f26dca4 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Wed, 22 Jun 2022 20:00:18 +0800 Subject: steelix: Add FW_CONFIG bit for from_factor Rusty shares the board with Steelix Steelix is convertible and has power LED, but Rusty is clamshell and does not have power LED so ectool led POWER query should not show "white : 0x1" We could use FW_CONFIG to distinguish this difference BUG=b:236215405 TEST=set FW_CONFIG to 0x2000 or 0x0 ectool led POWER query shows "white : 0x1" or "white : 0x0" BRANCH=none Change-Id: I8fd51b3439ab8be495c42e6cfabd0cb71287562d Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716418 Reviewed-by: Mike Lee Reviewed-by: Knox Chiou Reviewed-by: Eric Yilun Lin --- zephyr/projects/corsola/BUILD.py | 1 + zephyr/projects/corsola/cbi_steelix.dts | 31 ++++++++++++++++++ zephyr/projects/corsola/src/kingler/led_steelix.c | 38 ++++++++++++++++++----- 3 files changed, 63 insertions(+), 7 deletions(-) create mode 100644 zephyr/projects/corsola/cbi_steelix.dts diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index 83ad865cb1..0577f40004 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -77,6 +77,7 @@ register_corsola_project( here / "i2c_kingler.dts", here / "interrupts_kingler.dts", here / "cbi_eeprom.dts", + here / "cbi_steelix.dts", here / "gpio_steelix.dts", here / "npcx_keyboard.dts", here / "led_steelix.dts", diff --git a/zephyr/projects/corsola/cbi_steelix.dts b/zephyr/projects/corsola/cbi_steelix.dts new file mode 100644 index 0000000000..052bf23b5d --- /dev/null +++ b/zephyr/projects/corsola/cbi_steelix.dts @@ -0,0 +1,31 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + steelix-fw-config { + compatible = "cros-ec,cbi-fw-config"; + + /* + * FW_CONFIG field to indicate the device is clamshell + * or convertible. + */ + from_factor { + enum-name = "FROM_FACTOR"; + start = <13>; + size = <3>; + + convertible { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CONVERTIBLE"; + value = <1>; + }; + clamshell { + compatible = "cros-ec,cbi-fw-config-value"; + enum-name = "CLAMSHELL"; + value = <0>; + }; + }; + }; +}; diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c index 2d2e1431a1..f15f31c8ee 100644 --- a/zephyr/projects/corsola/src/kingler/led_steelix.c +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -10,6 +10,7 @@ #include "board_led.h" #include "common.h" +#include "cros_cbi.h" #include "led_common.h" #include "led_onoff_states.h" #include "util.h" @@ -82,6 +83,21 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, } } +static bool device_is_clamshell(void) +{ + int ret; + uint32_t val; + + ret = cros_cbi_get_fw_config(FROM_FACTOR, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", + FROM_FACTOR); + return false; + } + + return val == CLAMSHELL; +} + __override void led_set_color_battery(enum ec_led_colors color) { switch (color) { @@ -106,13 +122,17 @@ __override void led_set_color_battery(enum ec_led_colors color) __override void led_set_color_power(enum ec_led_colors color) { - switch (color) { - case EC_LED_COLOR_WHITE: - board_led_pwm_set_duty(&board_led_power_white, 100); - break; - default: + if (device_is_clamshell()) { board_led_pwm_set_duty(&board_led_power_white, 0); - break; + } else { + switch (color) { + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_power_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_power_white, 0); + break; + } } } @@ -123,7 +143,11 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) brightness_range[EC_LED_COLOR_GREEN] = 1; brightness_range[EC_LED_COLOR_AMBER] = 1; } else if (led_id == EC_LED_ID_POWER_LED) { - brightness_range[EC_LED_COLOR_WHITE] = 1; + if (device_is_clamshell()) { + brightness_range[EC_LED_COLOR_WHITE] = 0; + } else { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } } } -- cgit v1.2.1 From aa25244ef7e395a249faeefa8cfd5ccdfc7922db Mon Sep 17 00:00:00 2001 From: Sue Chen Date: Wed, 22 Jun 2022 15:44:37 +0800 Subject: Nissa: modify Amber LED RGB setting = <70, 30, 0> BUG=b:235304497 BRANCH=none TEST=check Amber LED as expected Signed-off-by: Sue Chen Change-Id: Ic62ae98fbd45d4e92863b8aa31b1b83dc75969a9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716416 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/craask_pwm_leds.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/craask_pwm_leds.dts b/zephyr/projects/nissa/craask_pwm_leds.dts index 592275ff71..c922d36f2f 100644 --- a/zephyr/projects/nissa/craask_pwm_leds.dts +++ b/zephyr/projects/nissa/craask_pwm_leds.dts @@ -25,7 +25,7 @@ color-map-blue = < 0 0 100>; color-map-yellow = < 0 50 50>; color-map-white = <100 100 100>; - color-map-amber = <100 5 0>; + color-map-amber = < 70 30 0>; brightness-range = <100 100 100 0 0 0>; -- cgit v1.2.1 From bd1b447a11ce622ac92c297dca29dd51b540d9c6 Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Mon, 20 Jun 2022 09:25:52 +0800 Subject: tentacruel: Initial zephyr config for tentacruel project Initial EC Zephyr config for tentacruel Reuse most of Krabby sources. Configure the battery/gpio/led in the later CLs. BUG=b:234409654 TEST=zmake build tentacruel --clobber BRANCH=None Signed-off-by: jeffrey_lin Change-Id: I5ca48d5547c4f483f2d97750217bc784bdc84321 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711511 Reviewed-by: Eric Yilun Lin Reviewed-by: Jacky Wang Commit-Queue: Chen-Tsung Hsieh --- zephyr/projects/corsola/BUILD.py | 20 ++ zephyr/projects/corsola/CMakeLists.txt | 12 ++ zephyr/projects/corsola/Kconfig | 6 + zephyr/projects/corsola/battery_tentacruel.dts | 12 ++ zephyr/projects/corsola/gpio_tentacruel.dts | 236 +++++++++++++++++++++ zephyr/projects/corsola/led_tentacruel.dts | 47 ++++ zephyr/projects/corsola/prj_tentacruel.conf | 7 + .../projects/corsola/src/krabby/led_tentacruel.c | 147 +++++++++++++ 8 files changed, 487 insertions(+) create mode 100644 zephyr/projects/corsola/battery_tentacruel.dts create mode 100644 zephyr/projects/corsola/gpio_tentacruel.dts create mode 100644 zephyr/projects/corsola/led_tentacruel.dts create mode 100644 zephyr/projects/corsola/prj_tentacruel.conf create mode 100644 zephyr/projects/corsola/src/krabby/led_tentacruel.c diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index 0577f40004..8585f4e3aa 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -92,3 +92,23 @@ register_corsola_project( here / "prj_steelix.conf", ], ) + + +register_corsola_project( + "tentacruel", + extra_dts_overlays=[ + here / "adc_krabby.dts", + here / "battery_tentacruel.dts", + here / "gpio_tentacruel.dts", + here / "i2c_krabby.dts", + here / "interrupts_krabby.dts", + here / "cbi_eeprom.dts", + here / "led_tentacruel.dts", + here / "motionsense_krabby.dts", + here / "usbc_krabby.dts", + ], + extra_kconfig_files=[ + here / "prj_krabby.conf", + here / "prj_tentacruel.conf", + ], +) diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt index 2bd50910ee..d9abeaca4d 100644 --- a/zephyr/projects/corsola/CMakeLists.txt +++ b/zephyr/projects/corsola/CMakeLists.txt @@ -50,5 +50,17 @@ elseif(DEFINED CONFIG_BOARD_STEELIX) "src/kingler/usb_pd_policy.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/kingler/usbc_config.c") + +elseif(DEFINED CONFIG_BOARD_TENTACRUEL) + project(tentacruel) + zephyr_library_sources("src/krabby/hooks.c" + "src/krabby/charger_workaround.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON + "src/krabby/led_tentacruel.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usb_pd_policy.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC + "src/krabby/usbc_config.c") endif() diff --git a/zephyr/projects/corsola/Kconfig b/zephyr/projects/corsola/Kconfig index b05d68acc1..e72bb70fde 100644 --- a/zephyr/projects/corsola/Kconfig +++ b/zephyr/projects/corsola/Kconfig @@ -20,6 +20,12 @@ config BOARD_STEELIX Build Google Steelix variant board. Steelix is a variant of Kingler and has MediaTek MT8186 SoC with NPCX993FA0BX EC. +config BOARD_TENTACRUEL + bool "Google Tentacruel Board" + help + Build Google Tentacruel variant board. Tentacruel is a variant of Krabby + and has MediaTek MT8186 SoC with ITE it81202-bx EC. + config VARIANT_CORSOLA_DB_DETECTION bool "Corsola Platform Runtime Daughter Board Detection" depends on PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG diff --git a/zephyr/projects/corsola/battery_tentacruel.dts b/zephyr/projects/corsola/battery_tentacruel.dts new file mode 100644 index 0000000000..05dcc4de05 --- /dev/null +++ b/zephyr/projects/corsola/battery_tentacruel.dts @@ -0,0 +1,12 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + batteries { + default_battery: c235 { + compatible = "as3gwrc3ka,c235-41", "battery-smart"; + }; + }; +}; diff --git a/zephyr/projects/corsola/gpio_tentacruel.dts b/zephyr/projects/corsola/gpio_tentacruel.dts new file mode 100644 index 0000000000..23d85bb59e --- /dev/null +++ b/zephyr/projects/corsola/gpio_tentacruel.dts @@ -0,0 +1,236 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &ec_flash_wp_odl; + }; + + named-gpios { + compatible = "named-gpios"; + + power_button_l: power_button_l { + gpios = <&gpioe 4 GPIO_INPUT>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + lid_open: lid_open { + gpios = <&gpioe 2 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + tablet_mode_l: tablet_mode_l { + gpios = <&gpioj 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + ap_ec_warm_rst_req: ap_ec_warm_rst_req { + gpios = <&gpiod 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_HIGH)>; + enum-name = "GPIO_AP_EC_WARM_RST_REQ"; + }; + ap_in_sleep_l: ap_in_sleep_l { + gpios = <&gpiob 6 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_IN_SLEEP_L"; + }; + base_imu_int_l: base_imu_int_l { + gpios = <&gpiom 3 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + lid_accel_int_l: lid_accel_int_l { + gpios = <&gpiom 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + volume_down_l: volume_down_l { + gpios = <&gpiod 5 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + volume_up_l: volume_up_l { + gpios = <&gpiod 6 GPIO_INPUT>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + gpio_ap_xhci_init_done: ap_xhci_init_done { + gpios = <&gpioj 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + ac_present: ac_present { + gpios = <&gpioe 5 GPIO_INPUT>; + enum-name = "GPIO_AC_PRESENT"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioc 3 GPIO_OUTPUT_LOW>; + }; + ec_flash_wp_odl: ec_flash_wp_odl { + gpios = <&gpioi 4 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + }; + spi0_cs: spi0_cs { + gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; + gpio_x_ec_gpio2: x_ec_gpio2 { + gpios = <&gpiob 2 GPIO_INPUT>; + }; + usb_c0_ppc_bc12_int_odl: usb_c0_ppc_bc12_int_odl { + gpios = <&gpiod 1 GPIO_INPUT>; + }; + usb_c1_bc12_charger_int_odl: usb_c1_bc12_charger_int_odl { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + ec_pmic_en_odl: ec_pmic_en_odl { + gpios = <&gpiod 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_PMIC_EN_ODL"; + }; + en_pp5000_z2: en_pp5000_z2 { + gpios = <&gpioc 6 GPIO_OUTPUT_HIGH>; + }; + gpio_en_ulp: en_ulp { + gpios = <&gpioe 3 GPIO_OUTPUT_LOW>; + }; + sys_rst_odl: sys_rst_odl { + gpios = <&gpiog 1 GPIO_ODR_LOW>; + enum-name = "GPIO_SYS_RST_ODL"; + }; + gpio_ec_bl_en_od: ec_bl_en_od { + gpios = <&gpiob 5 (GPIO_ODR_LOW | GPIO_VOLTAGE_1P8)>; + }; + ap_sysrst_odl_r: ap_ec_sysrst_odl { + gpios = <&gpioj 2 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_SYSRST_ODL"; + }; + ap_ec_wdtrst_l: ap_ec_wdtrst_l { + gpios = <&gpioc 7 (GPIO_INPUT | GPIO_VOLTAGE_1P8 | + GPIO_ACTIVE_LOW)>; + enum-name = "GPIO_AP_EC_WDTRST_L"; + }; + ec_int_l: ec_int_l { + gpios = <&gpioe 6 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + enum-name = "GPIO_EC_INT_L"; + }; + dp_aux_path_sel: dp_aux_path_sel { + gpios = <&gpiog 0 GPIO_OUTPUT_HIGH>; + }; + ec_ap_dp_hpd_odl: ec_ap_dp_hpd_odl { + gpios = <&gpioj 0 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; + }; + en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { + gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_EN_PP5000_USB_A0_VBUS"; + }; + usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo { + gpios = <&gpiof 0 GPIO_INPUT>; + }; + ec_batt_pres_odl: ec_batt_pres_odl { + gpios = <&gpioc 0 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + en_ec_id_odl: en_ec_id_odl { + gpios = <&gpioh 5 GPIO_ODR_HIGH>; + }; + entering_rw: entering_rw { + gpios = <&gpioc 5 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_en_5v_usm: en_5v_usm { + gpios = <&gpiog 3 GPIO_OUTPUT_LOW>; + }; + usb_a0_fault_odl: usb_a0_fault_odl { + gpios = <&gpioj 6 GPIO_INPUT>; + }; + gpio_ec_x_gpio1: ec_x_gpio1 { + gpios = <&gpioh 4 GPIO_OUTPUT_LOW>; + }; + gpio_ec_x_gpio3: ec_x_gpio3 { + gpios = <&gpioj 1 GPIO_OUTPUT_LOW>; + }; + gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { + gpios = <&gpioj 3 GPIO_INPUT>; + }; + gpio_packet_mode_en: packet_mode_en { + gpios = <&gpiod 4 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + }; + + /* + * aliases for sub-board GPIOs + */ + aliases { + gpio-en-hdmi-pwr = &gpio_ec_x_gpio1; + gpio-usb-c1-frs-en = &gpio_ec_x_gpio1; + gpio-usb-c1-ppc-int-odl = &gpio_x_ec_gpio2; + gpio-ps185-ec-dp-hpd = &gpio_x_ec_gpio2; + gpio-usb-c1-dp-in-hpd = &gpio_ec_x_gpio3; + gpio-ps185-pwrdn-odl = &gpio_ec_x_gpio3; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = <&int_ac_present + &int_power_button + &int_lid_open>; + }; + + unused-pins { + compatible = "unused-gpios"; + + unused-gpios = + /* pg_pp5000_z2_od */ + <&gpiod 2 GPIO_INPUT>, + /* pg_mt6315_proc_b_odl */ + <&gpioe 1 GPIO_INPUT>, + /* ec_pen_chg_dis_odl */ + <&gpioh 3 GPIO_ODR_HIGH>, + /* ccd_mode_odl */ + <&gpioc 4 GPIO_INPUT>, + /* unnamed nc pins */ + <&gpioa 3 GPIO_INPUT_PULL_DOWN>, + <&gpioa 6 GPIO_INPUT_PULL_DOWN>, + <&gpioa 7 GPIO_INPUT_PULL_DOWN>, + <&gpiod 7 GPIO_INPUT_PULL_DOWN>, + <&gpiof 1 GPIO_INPUT_PULL_DOWN>, + <&gpioh 0 GPIO_INPUT_PULL_DOWN>, + <&gpioh 6 GPIO_INPUT_PULL_DOWN>, + <&gpioi 3 GPIO_INPUT_PULL_DOWN>, + <&gpioi 5 GPIO_INPUT_PULL_DOWN>, + <&gpioi 6 GPIO_INPUT_PULL_DOWN>, + <&gpiom 6 (GPIO_INPUT_PULL_DOWN | GPIO_VOLTAGE_1P8)>, + /* spi_clk_gpg6 */ + <&gpiog 6 GPIO_INPUT_PULL_UP>, + /* spi_mosi_gpg4 */ + <&gpiog 4 GPIO_OUTPUT_LOW>, + /* spi_miso_gpg5 */ + <&gpiog 5 GPIO_OUTPUT_LOW>, + /* spi_cs_gpg7 */ + <&gpiog 7 GPIO_OUTPUT_LOW>; + }; +}; + +&pinctrl { + /* I2C property setting */ + i2c0_clk_gpb3_default: i2c0_clk_gpb3_default { + gpio-voltage = "1v8"; + }; + i2c0_data_gpb4_default: i2c0_data_gpb4_default { + gpio-voltage = "1v8"; + }; + i2c3_clk_gpf2_default: i2c3_clk_gpf2_default { + gpio-voltage = "1v8"; + }; + i2c3_data_gpf3_default: i2c3_data_gpf3_default { + gpio-voltage = "1v8"; + }; + /* SHI property setting */ + shi_mosi_gpm0_default: shi_mosi_gpm0_default { + gpio-voltage = "1v8"; + }; + shi_miso_gpm1_default: shi_miso_gpm1_default { + gpio-voltage = "1v8"; + }; + shi_clk_gpm4_default: shi_clk_gpm4_default { + gpio-voltage = "1v8"; + }; + shi_cs_gpm5_default: shi_cs_gpm5_default { + gpio-voltage = "1v8"; + }; +}; diff --git a/zephyr/projects/corsola/led_tentacruel.dts b/zephyr/projects/corsola/led_tentacruel.dts new file mode 100644 index 0000000000..42843c6cb6 --- /dev/null +++ b/zephyr/projects/corsola/led_tentacruel.dts @@ -0,0 +1,47 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + /* NOTE: &pwm number needs same with channel number */ + led_power_white: ec_led1_odl { + pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_amber: ec_led2_odl { + pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_white: ec_led3_odl { + pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + }; +}; + +/* LED1 */ +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* LED2 */ +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf new file mode 100644 index 0000000000..4949b28351 --- /dev/null +++ b/zephyr/projects/corsola/prj_tentacruel.conf @@ -0,0 +1,7 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Variant config +CONFIG_BOARD_KRABBY=n +CONFIG_BOARD_TENTACRUEL=y diff --git a/zephyr/projects/corsola/src/krabby/led_tentacruel.c b/zephyr/projects/corsola/src/krabby/led_tentacruel.c new file mode 100644 index 0000000000..e7416d6dd7 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/led_tentacruel.c @@ -0,0 +1,147 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +#include "board_led.h" +#include "common.h" +#include "led_common.h" +#include "led_onoff_states.h" +#include "util.h" + +LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); + +/*If we need pwm output in ITE chip power saving mode, then we should set + * frequency <= 324Hz. + */ +#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(324) + +static const struct board_led_pwm_dt_channel board_led_power_white = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); +static const struct board_led_pwm_dt_channel board_led_battery_amber = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_amber)); +static const struct board_led_pwm_dt_channel board_led_battery_white = + BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_white)); + +__override const int led_charge_lvl_1 = 5; +__override const int led_charge_lvl_2 = 95; + +__override struct led_descriptor + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, + [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, + [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, + [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, + [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, + {LED_OFF, 1 * LED_ONE_SEC} }, + [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, + {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, +}; + +__override const struct led_descriptor + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, + [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, + [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, + {LED_OFF, 3 * LED_ONE_SEC} }, + [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, +}; + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED, +}; + +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, + int percent) +{ + uint32_t pulse_ns; + int rv; + + if (!device_is_ready(ch->dev)) { + LOG_ERR("PWM device %s not ready", ch->dev->name); + return; + } + + pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); + + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", + ch->dev->name, percent, pulse_ns); + + rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, + ch->flags); + if (rv) { + LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); + } +} + +__override void led_set_color_battery(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_AMBER: + board_led_pwm_set_duty(&board_led_battery_amber, 100); + board_led_pwm_set_duty(&board_led_battery_white, 0); + break; + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_battery_amber, 0); + board_led_pwm_set_duty(&board_led_battery_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_battery_amber, 0); + board_led_pwm_set_duty(&board_led_battery_white, 0); + break; + } +} + +__override void led_set_color_power(enum ec_led_colors color) +{ + switch (color) { + case EC_LED_COLOR_WHITE: + board_led_pwm_set_duty(&board_led_power_white, 100); + break; + default: + board_led_pwm_set_duty(&board_led_power_white, 0); + break; + } +} + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + brightness_range[EC_LED_COLOR_AMBER] = 1; + brightness_range[EC_LED_COLOR_WHITE] = 1; + } else if (led_id == EC_LED_ID_POWER_LED) { + brightness_range[EC_LED_COLOR_WHITE] = 1; + } +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_AMBER] != 0) { + led_set_color_battery(EC_LED_COLOR_AMBER); + } else if (brightness[EC_LED_COLOR_WHITE] != 0) { + led_set_color_battery(EC_LED_COLOR_WHITE); + } else { + led_set_color_battery(LED_OFF); + } + } else if (led_id == EC_LED_ID_POWER_LED) { + if (brightness[EC_LED_COLOR_WHITE] != 0) { + led_set_color_power(EC_LED_COLOR_WHITE); + } else { + led_set_color_power(LED_OFF); + } + } + + return EC_SUCCESS; +} -- cgit v1.2.1 From 275a875a350e6f0e898a88ec82aa0b8edce5d1e6 Mon Sep 17 00:00:00 2001 From: Nick Sanders Date: Thu, 21 Apr 2022 18:01:05 -0700 Subject: tigertool: cleanup Fix serial number detect new python3.9 incompatibilities. cros lint to the extent possible BUG=b:216199797 TEST=./tigertest.py -c 10; servo_updater -b servo_v4 BRANCH=none Signed-off-by: Nick Sanders Change-Id: I2ec628389f63711a540223fc9004c9fff7155c1e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3615478 Reviewed-by: Ruben Rodriguez Buchillon --- extra/tigertool/ecusb/tiny_servo_common.py | 53 ++++++------- extra/tigertool/make_pkg.sh | 7 +- extra/usb_serial/console.py | 57 +++++++------ extra/usb_updater/servo_updater.py | 123 +++++++++++++++-------------- 4 files changed, 117 insertions(+), 123 deletions(-) diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py index e27736a9dc..726e2e64b7 100644 --- a/extra/tigertool/ecusb/tiny_servo_common.py +++ b/extra/tigertool/ecusb/tiny_servo_common.py @@ -11,15 +11,11 @@ # Note: This is a py2/3 compatible file. import datetime -import errno -import os -import re -import subprocess import sys import time -import usb import six +import usb from . import pty_driver from . import stm32uart @@ -52,20 +48,13 @@ def check_usb(vidpid, serialname=None): vidpid: string representation of the usb vid:pid, eg. '18d1:2001' serialname: serialname if specified. - Returns: True if found, False, otherwise. + Returns: + True if found, False, otherwise. """ - if serialname: - output = subprocess.check_output(['lsusb', '-v', '-d', vidpid], - **get_subprocess_args()) - m = re.search(r'^\s*iSerial\s+\d+\s+%s$' % serialname, output, flags=re.M) - if m: - return True + if get_usb_dev(vidpid, serialname): + return True - return False - else: - if subprocess.call(['lsusb', '-d', vidpid], stdout=open('/dev/null', 'w')): - return False - return True + return False def check_usb_sn(vidpid): """Return the serial number @@ -77,13 +66,15 @@ def check_usb_sn(vidpid): Args: vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - Returns: string serial number if found, None otherwise. + Returns: + string serial number if found, None otherwise. """ - output = subprocess.check_output(['lsusb', '-v', '-d', vidpid], - **get_subprocess_args()) - m = re.search(r'^\s*iSerial\s+(.*)$', output, flags=re.M) - if m: - return m.group(1) + dev = get_usb_dev(vidpid) + + if dev: + dev_serial = usb.util.get_string(dev, dev.iSerialNumber) + + return dev_serial return None @@ -98,13 +89,13 @@ def get_usb_dev(vidpid, serialname=None): vidpid: string representation of the usb vid:pid, eg. '18d1:2001' serialname: serialname if specified. - Returns: pyusb device if found, None otherwise. + Returns: + pyusb device if found, None otherwise. """ vidpidst = vidpid.split(':') vid = int(vidpidst[0], 16) pid = int(vidpidst[1], 16) - dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True) dev_list = list(dev_g) @@ -140,7 +131,8 @@ def check_usb_dev(vidpid, serialname=None): vidpid: string representation of the usb vid:pid, eg. '18d1:2001' serialname: serialname if specified. - Returns: usb device number if found, None otherwise. + Returns: + usb device number if found, None otherwise. """ dev = get_usb_dev(vidpid, serialname=serialname) @@ -173,7 +165,7 @@ def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True): if timeout: finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout) while check_usb(vidpid, serialname) != desiredpresence: - time.sleep(.01) + time.sleep(.1) if timeout: if datetime.datetime.now() > finish: raise TinyServoError('Timeout', 'Timeout waiting for USB %s' % vidpid) @@ -194,8 +186,8 @@ def do_serialno(serialno, pty): TinyServoError: on failure to set. ptyError: on command interface error. """ - cmd = 'serialno set %s' % serialno - regex = 'Serial number:\s+(\S+)' + cmd = r'serialno set %s' % serialno + regex = r'Serial number:\s+(\S+)' results = pty._issue_cmd_get_results(cmd, [regex])[0] sn = results[1].strip().strip('\n\r') @@ -221,7 +213,8 @@ def setup_tinyservod(vidpid, interface, serialname=None, debuglog=False): serialname: string serial name of device requested, optional. debuglog: chatty printout (boolean) - Returns: pty object + Returns: + pty object Raises: UsbError, SusbError: on device not found diff --git a/extra/tigertool/make_pkg.sh b/extra/tigertool/make_pkg.sh index 5a63862242..12db65afbd 100755 --- a/extra/tigertool/make_pkg.sh +++ b/extra/tigertool/make_pkg.sh @@ -3,6 +3,8 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. +set -e + # Make sure we are in the correct dir. cd "$( dirname "${BASH_SOURCE[0]}" )" || exit @@ -21,10 +23,11 @@ cp tigertest.py "${DEST}" cp README.md "${DEST}" cp -r ecusb "${DEST}" -cp -r ../../../../../chroot/usr/lib64/python2.7/site-packages/usb "${DEST}" +# Not compatible with glinux as of 4/28/2022. +# cp -r ../../../../../chroot/usr/lib64/python3.6/site-packages/usb "${DEST}" find "${DEST}" -name "*.py[co]" -delete cp -r ../usb_serial "${DEST}" -(cd build; tar -czf tigertool_${DATE}.tgz tigertool) +(cd build && tar -czf tigertool_"${DATE}".tgz tigertool) echo "Done packaging tigertool_${DATE}.tgz" diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py index d06b33ce23..7211dceff6 100755 --- a/extra/usb_serial/console.py +++ b/extra/usb_serial/console.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. @@ -19,15 +19,14 @@ import sys import termios import threading import time -import traceback import tty try: import usb -except: - print("import usb failed") - print("try running these commands:") - print(" sudo apt-get install python-pip") - print(" sudo pip install --pre pyusb") +except ModuleNotFoundError: + print('import usb failed') + print('try running these commands:') + print(' sudo apt-get install python-pip') + print(' sudo pip install --pre pyusb') print() sys.exit(-1) @@ -77,9 +76,9 @@ class Susb(): Discovers and connects to USB endpoints. Args: - vendor : usb vendor id of device - product : usb product id of device - interface : interface number ( 1 - 8 ) of device to use + vendor: usb vendor id of device + product: usb product id of device + interface: interface number ( 1 - 8 ) of device to use serialname: string of device serialnumber. Raises: @@ -89,7 +88,7 @@ class Susb(): dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) dev_list = list(dev_g) if dev_list is None: - raise SusbError("USB device not found") + raise SusbError('USB device not found') # Check if we have multiple devices. dev = None @@ -104,7 +103,7 @@ class Susb(): dev = d break if dev is None: - raise SusbError("USB device(%s) not found" % (serialname,)) + raise SusbError('USB device(%s) not found' % (serialname,)) else: try: dev = dev_list[0] @@ -112,7 +111,7 @@ class Susb(): try: dev = dev_list.next() except: - raise SusbError("USB device %04x:%04x not found" % (vendor, product)) + raise SusbError('USB device %04x:%04x not found' % (vendor, product)) # If we can't set configuration, it's already been set. try: @@ -126,7 +125,7 @@ class Susb(): self._intf = intf if not intf: - raise SusbError("Interface not found") + raise SusbError('Interface not found') # Detach raiden.ko if it is loaded. if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True: @@ -181,7 +180,7 @@ class Suart(): """ self._done = threading.Event() self._susb = Susb(vendor=vendor, product=product, - interface=interface, serialname=serialname) + interface=interface, serialname=serialname) def wait_until_done(self, timeout=None): return self._done.wait(timeout=timeout) @@ -199,7 +198,7 @@ class Suart(): # If we miss some characters on pty disconnect, that's fine. # ep.read() also throws USBError on timeout, which we discard. if not isinstance(e, (OSError, usb.core.USBError)): - print("rx %s" % e) + print('rx %s' % e) finally: self._done.set() @@ -208,19 +207,18 @@ class Suart(): while True: try: r = GetBuffer(sys.stdin).read(1) - if not r or r == b"\x03": + if not r or r == b'\x03': break if r: self._susb._write_ep.write(array.array('B', r), self._susb.TIMEOUT_MS) except Exception as e: - print("tx %s" % e) + print('tx %s' % e) finally: self._done.set() def run(self): - """Creates pthreads to poll USB & PTY for data. - """ + """Creates pthreads to poll USB & PTY for data.""" self._exit = False self._rx_thread = threading.Thread(target=self.run_rx_thread) @@ -239,18 +237,17 @@ class Suart(): Ctrl-C exits. """ -parser = argparse.ArgumentParser(description="Open a console to a USB device") +parser = argparse.ArgumentParser(description='Open a console to a USB device') parser.add_argument('-d', '--device', type=str, - help="vid:pid of target device", default="18d1:501c") + help='vid:pid of target device', default='18d1:501c') parser.add_argument('-i', '--interface', type=int, - help="interface number of console", default=0) + help='interface number of console', default=0) parser.add_argument('-s', '--serialno', type=str, - help="serial number of device", default="") + help='serial number of device', default='') parser.add_argument('-S', '--notty-exit-sleep', type=float, default=0.2, - help="When stdin is *not* a TTY, wait this many seconds after EOF from " - "stdin before exiting, to give time for receiving a reply from the USB " - "device.") - + help='When stdin is *not* a TTY, wait this many seconds ' + 'after EOF from stdin before exiting, to give time for ' + 'receiving a reply from the USB device.') def runconsole(): """Run the usb console code @@ -280,7 +277,7 @@ def main(): stdin_isatty = sys.stdin.isatty() if stdin_isatty: fd = sys.stdin.fileno() - os.system("stty -echo") + os.system('stty -echo') old_settings = termios.tcgetattr(fd) try: @@ -288,7 +285,7 @@ def main(): finally: if stdin_isatty: termios.tcsetattr(fd, termios.TCSADRAIN, old_settings) - os.system("stty echo") + os.system('stty echo') # Avoid having the user's shell prompt start mid-line after the final output # from this program. print() diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py index fa0d21670c..432ee120de 100755 --- a/extra/usb_updater/servo_updater.py +++ b/extra/usb_updater/servo_updater.py @@ -9,15 +9,15 @@ # Note: This is a py2/3 compatible file. +"""USB updater tool for servo and similar boards.""" + from __future__ import print_function import argparse -import errno import os import re import subprocess import time -import tempfile import json @@ -62,14 +62,15 @@ TEST_IMAGE_BASE_PATH = '/usr/local/' COMMON_PATH = 'share/servo_updater' -FIRMWARE_DIR = "firmware/" -CONFIGS_DIR = "configs/" +FIRMWARE_DIR = 'firmware/' +CONFIGS_DIR = 'configs/' RETRIES_COUNT = 10 RETRIES_DELAY = 1 def do_with_retries(func, *args): - """ + """Try a function several times + Call function passed as argument and check if no error happened. If exception was raised by function, it will be retried up to RETRIES_COUNT times. @@ -88,21 +89,21 @@ def do_with_retries(func, *args): try: return func(*args) except Exception as e: - print("Retrying function %s: %s" % (func.__name__, e)) + print('Retrying function %s: %s' % (func.__name__, e)) retry = retry + 1 time.sleep(RETRIES_DELAY) continue - raise Exception("'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT)) + raise Exception("'{}' failed after {} retries".format( + func.__name__, RETRIES_COUNT)) def flash(brdfile, serialno, binfile): - """ - Call fw_update to upload to updater USB endpoint. + """Call fw_update to upload to updater USB endpoint. Args: - brdfile: path to board configuration file + brdfile: path to board configuration file serialno: device serial number - binfile: firmware file + binfile: firmware file """ p = fw_update.Supdate() @@ -113,29 +114,28 @@ def flash(brdfile, serialno, binfile): # Start transfer and erase. p.start() # Upload the bin file - print("Uploading %s" % binfile) + print('Uploading %s' % binfile) p.write_file() # Finalize - print("Done. Finalizing.") + print('Done. Finalizing.') p.stop() def flash2(vidpid, serialno, binfile): - """ - Call fw update via usb_updater2 commandline. + """Call fw update via usb_updater2 commandline. Args: - vidpid: vendor id and product id of device + vidpid: vendor id and product id of device serialno: device serial number (optional) - binfile: firmware file + binfile: firmware file """ tool = 'usb_updater2' - cmd = "%s -d %s" % (tool, vidpid) + cmd = '%s -d %s' % (tool, vidpid) if serialno: - cmd += " -S %s" % serialno - cmd += " -n" - cmd += " %s" % binfile + cmd += ' -S %s' % serialno + cmd += ' -n' + cmd += ' %s' % binfile print(cmd) help_cmd = '%s --help' % tool @@ -151,27 +151,28 @@ def flash2(vidpid, serialno, binfile): if res in (0, 1, 2): return res else: - raise ServoUpdaterException("%s exit with res = %d" % (cmd, res)) + raise ServoUpdaterException('%s exit with res = %d' % (cmd, res)) def select(tinys, region): - """ + """Jump to specified boot region + Ensure the servo is in the expected ro/rw region. This function jumps to the required region and verify if jump was successful by executing 'sysinfo' command and reading current region. If response was not received or region is invalid, exception is raised. Args: - tinys: TinyServod object + tinys: TinyServod object region: region to jump to, only "rw" and "ro" is allowed """ - if region not in ["rw", "ro"]: - raise Exception("Region must be ro or rw") + if region not in ['rw', 'ro']: + raise Exception('Region must be ro or rw') - if region is "ro": - cmd = "reboot" + if region == 'ro': + cmd = 'reboot' else: - cmd = "sysjump %s" % region + cmd = 'sysjump %s' % region tinys.pty._issue_cmd(cmd) @@ -179,10 +180,10 @@ def select(tinys, region): time.sleep(2) tinys.reinitialize() - res = tinys.pty._issue_cmd_get_results("sysinfo", ["Copy:[\s]+(RO|RW)"]) + res = tinys.pty._issue_cmd_get_results('sysinfo', [r'Copy:[\s]+(RO|RW)']) current_region = res[0][1].lower() if current_region != region: - raise Exception("Invalid region: %s/%s" % (current_region, region)) + raise Exception('Invalid region: %s/%s' % (current_region, region)) def do_version(tinys): """Check version via ec console 'pty'. @@ -198,8 +199,8 @@ def do_version(tinys): # ... # Build: tigertail_v1.1.6749-74d1a312e """ - cmd = '\r\nversion\r\n' - regex = 'Build:\s+(\S+)[\r\n]+' + cmd = 'version' + regex = r'Build:\s+(\S+)[\r\n]+' results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0] @@ -219,9 +220,9 @@ def do_updater_version(tinys): # Servo versions below 58 are from servo-9040.B. Versions starting with _v2 # are newer than anything _v1, no need to check the exact number. Updater # version is not directly queryable. - if re.search('_v[2-9]\.\d', vers): + if re.search(r'_v[2-9]\.\d', vers): return 6 - m = re.search('_v1\.1\.(\d\d\d\d)', vers) + m = re.search(r'_v1\.1\.(\d\d\d\d)', vers) if m: version_number = int(m.group(1)) if version_number < 5800: @@ -310,7 +311,7 @@ def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL): cname = newname else: # Try appending ".json" to convert board name to config file. - cname = newname + ".json" + cname = newname + '.json' if not os.path.isfile(cname): raise ServoUpdaterException("Can't find config file: %s." % cname) @@ -344,26 +345,26 @@ def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL): return cname, fname, binvers def main(): - parser = argparse.ArgumentParser(description="Image a servo device") + parser = argparse.ArgumentParser(description='Image a servo device') parser.add_argument('-p', '--print', dest='print_only', action='store_true', default=False, help='only print available firmware for board/channel') parser.add_argument('-s', '--serialno', type=str, - help="serial number to program", default=None) + help='serial number to program', default=None) parser.add_argument('-b', '--board', type=str, - help="Board configuration json file", + help='Board configuration json file', default=DEFAULT_BOARD, choices=BOARDS) parser.add_argument('-c', '--channel', type=str, - help="Firmware channel to use", + help='Firmware channel to use', default=DEFAULT_CHANNEL, choices=CHANNELS) parser.add_argument('-f', '--file', type=str, - help="Complete ec.bin file", default=None) - parser.add_argument('--force', action="store_true", - help="Update even if version match", default=False) - parser.add_argument('-v', '--verbose', action="store_true", - help="Chatty output") - parser.add_argument('-r', '--reboot', action="store_true", - help="Always reboot, even after probe.") + help='Complete ec.bin file', default=None) + parser.add_argument('--force', action='store_true', + help='Update even if version match', default=False) + parser.add_argument('-v', '--verbose', action='store_true', + help='Chatty output') + parser.add_argument('-r', '--reboot', action='store_true', + help='Always reboot, even after probe.') args = parser.parse_args() @@ -384,34 +385,34 @@ def main(): with open(brdfile) as data_file: data = json.load(data_file) vid, pid = int(data['vid'], 0), int(data['pid'], 0) - vidpid = "%04x:%04x" % (vid, pid) + vidpid = '%04x:%04x' % (vid, pid) iface = int(data['console'], 0) boardname = data['board'] # Make sure device is up. - print("===== Waiting for USB device =====") + print('===== Waiting for USB device =====') c.wait_for_usb(vidpid, serialname=serialno) # We need a tiny_servod to query some information. Set it up first. tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose) if not args.force: vers = do_version(tinys) - print("Current %s version is %s" % (boardname, vers)) - print("Available %s version is %s" % (boardname, newvers)) + print('Current %s version is %s' % (boardname, vers)) + print('Available %s version is %s' % (boardname, newvers)) if newvers == vers: - print("No version update needed") + print('No version update needed') if args.reboot: select(tinys, 'ro') return else: - print("Updating to recommended version.") + print('Updating to recommended version.') # Make sure the servo MCU is in RO - print("===== Jumping to RO =====") + print('===== Jumping to RO =====') do_with_retries(select, tinys, 'ro') - print("===== Flashing RW =====") + print('===== Flashing RW =====') vers = do_with_retries(do_updater_version, tinys) # To make sure that the tiny_servod here does not interfere with other # processes, close it out. @@ -430,10 +431,10 @@ def main(): tinys.reinitialize() # Make sure the servo MCU is in RW - print("===== Jumping to RW =====") + print('===== Jumping to RW =====') do_with_retries(select, tinys, 'rw') - print("===== Flashing RO =====") + print('===== Flashing RO =====') vers = do_with_retries(do_updater_version, tinys) if vers == 2: @@ -444,13 +445,13 @@ def main(): raise ServoUpdaterException("Can't detect updater version") # Make sure the servo MCU is in RO - print("===== Rebooting =====") + print('===== Rebooting =====') do_with_retries(select, tinys, 'ro') # Perform additional reboot to free USB/UART resources, taken by tiny servod. # See https://issuetracker.google.com/196021317 for background. - tinys.pty._issue_cmd("reboot") + tinys.pty._issue_cmd('reboot') - print("===== Finished =====") + print('===== Finished =====') -if __name__ == "__main__": +if __name__ == '__main__': main() -- cgit v1.2.1 From 1290c3c2619a4f20c7c346aee6931ea0a40d944c Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Tue, 21 Jun 2022 11:42:52 -0600 Subject: test: drivers: add utility to set the power state Add a more generic set function for the chipset power level. This function only accepts steady states. BRANCH=none BUG=b:233355058 TEST=ztest test test-drivers Signed-off-by: Yuval Peress Change-Id: I1273c307efc116389cd93e33e40d80da81420d7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715440 Reviewed-by: Keith Short Commit-Queue: Keith Short --- zephyr/test/drivers/include/test/drivers/utils.h | 19 +++++++++++++++++ zephyr/test/drivers/src/utils.c | 27 ++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index 17ea860dfd..c3fe4db868 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -14,10 +14,29 @@ #include "emul/tcpc/emul_tcpci_partner_src.h" #include "extpower.h" #include "host_command.h" +#include "power.h" /** @brief Set chipset to S0 state. Call all necessary hooks. */ void test_set_chipset_to_s0(void); +/** + * @brief Set the chipset to any stable state. Call all necessary hooks. + * + * Supported states are: + *
    + *
  • POWER_G3 (same as calling test_set_chipset_to_g3())
    • + *
  • POWER_S5
    • + *
  • POWER_S4
    • + *
  • POWER_S3
    • + *
  • POWER_S0 (same as calling test_set_chipset_to_s0()
    • + *
  • POWER_S0ix (if either CONFIG_PLATFORM_EC_POWERSEQ_S0IX or + * CONFIG_AP_PWRSEQ_S0IX are enabled)
    • + *
+ * + * @param new_state The new state. Must be a steady state (see above). + */ +void test_set_chipset_to_power_level(enum power_state new_state); + /** @brief Set chipset to G3 state. Call all necessary hooks. */ void test_set_chipset_to_g3(void); diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/src/utils.c index 5ba78043b1..b46f87f83c 100644 --- a/zephyr/test/drivers/src/utils.c +++ b/zephyr/test/drivers/src/utils.c @@ -61,6 +61,33 @@ void test_set_chipset_to_s0(void) power_get_state()); } +void test_set_chipset_to_power_level(enum power_state new_state) +{ + zassert_true(new_state == POWER_G3 || new_state == POWER_S5 || + new_state == POWER_S4 || new_state == POWER_S3 || + new_state == POWER_S0 +#ifdef CONFIG_POWER_S0IX + || new_state == POWER_S0ix +#endif + , + "Power state must be one of the steady states"); + + if (new_state == POWER_G3) { + test_set_chipset_to_g3(); + return; + } + + test_set_chipset_to_s0(); + + power_set_state(new_state); + + k_sleep(K_SECONDS(1)); + + /* Check if chipset is in correct state */ + zassert_equal(new_state, power_get_state(), "Expected %d, got %d", + new_state, power_get_state()); +} + void test_set_chipset_to_g3(void) { printk("%s: Forcing shutdown\n", __func__); -- cgit v1.2.1 From e8a8bea9e165c05169d9e1b22dcc5219d0fd5627 Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Thu, 16 Jun 2022 23:08:03 +0000 Subject: TCPMV2: Update DPM Request Gating for Alert and Revision The Alert DPM request currently does not stop pd_send_alert_msg from sending Alert messages to USB PD Revision 2.0 partners. Older devices using USB PD 2.0 will reset on unknown messages like Alert which can cause unexpected behavior. This CL adds revision gating for Alert and also updates the Get_Revision gating to match the Alert and Data_Reset DPM requests. BUG=b:235925532 TEST=On a twinkie checked that Alert and Get_Revision was being sent to a USB PD 3.0 partner but neither were being sent to a USB PD 2.0 partner. BRANCH=None Signed-off-by: Jameson Thies Change-Id: I573f8c71eb75be6909c3587fcad423d03c381bd7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3710284 Reviewed-by: Diana Z Reviewed-by: Abe Levkoy --- common/usbc/usb_pe_drp_sm.c | 37 ++++++++++------------ .../src/integration/usbc/usb_5v_3a_pd_sink.c | 8 +++++ 2 files changed, 24 insertions(+), 21 deletions(-) diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index 3d01a74b95..7c7dfde6c2 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -1527,12 +1527,7 @@ test_export_static enum usb_pe_state get_state_pe(const int port) */ static bool common_src_snk_dpm_requests(int port) { - if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && - PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) { - pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT); - set_state_pe(port, PE_SEND_ALERT); - return true; - } else if (IS_ENABLED(CONFIG_USBC_VCONN) && + if (IS_ENABLED(CONFIG_USBC_VCONN) && PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) { pe_set_dpm_curr_request(port, DPM_REQUEST_VCONN_SWAP); set_state_pe(port, PE_VCS_SEND_SWAP); @@ -1619,6 +1614,7 @@ static bool common_src_snk_dpm_requests(int port) } else if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) { if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) { + PE_CLR_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET); dpm_data_reset_complete(port); return false; } @@ -1631,11 +1627,25 @@ static bool common_src_snk_dpm_requests(int port) return true; } else if (IS_ENABLED(CONFIG_USB_PD_REV30) && PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION)) { + if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) { + PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GET_REVISION); + return false; + } pe_set_dpm_curr_request(port, DPM_REQUEST_GET_REVISION); set_state_pe(port, PE_GET_REVISION); return true; + } else if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && + PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) { + if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) { + PE_CLR_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT); + return false; + } + pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_ALERT); + set_state_pe(port, PE_SEND_ALERT); + return true; } + return false; } @@ -7183,15 +7193,6 @@ __maybe_unused static void pe_get_revision_entry(int port) { print_current_state(port); - /* - * Only USB PD partners with major revision 3.0 could potentially - * respond to Get_Revision. - */ - if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30) { - pe_set_ready_state(port); - return; - } - /* Send a Get_Revision message */ send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_GET_REVISION); pe_sender_response_msg_entry(port); @@ -7204,9 +7205,6 @@ __maybe_unused static void pe_get_revision_run(int port) int ext; enum pe_msg_check msg_check; - if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30) - return; - /* Check the state of the message sent */ msg_check = pe_sender_response_msg_run(port); @@ -7251,9 +7249,6 @@ __maybe_unused static void pe_get_revision_run(int port) __maybe_unused static void pe_get_revision_exit(int port) { - if (prl_get_rev(port, TCPCI_MSG_SOP) != PD_REV30) - return; - pe_sender_response_msg_exit(port); } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c index 8a1bb27edf..830e6246e9 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c @@ -11,11 +11,15 @@ #include "emul/emul_smart_battery.h" #include "emul/tcpc/emul_tcpci_partner_snk.h" #include "tcpm/tcpci.h" +#include "test/drivers/stubs.h" #include "test/drivers/test_state.h" #include "test/drivers/utils.h" #include "timer.h" #include "usb_common.h" #include "usb_pd.h" +#include "usb_prl_sm.h" + +#define TEST_USB_PORT USBC_PORT_C0 struct usb_attach_5v_3a_pd_sink_fixture { struct tcpci_partner_data sink_5v_3a; @@ -309,6 +313,10 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_ping_msg) */ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_alert_msg) { + /* Setting partner PD Rev to 3.0 to ungate Alert DPM request */ + /* TODO(b/236975670): move to dedicated USB PD Rev 3.0 test file */ + prl_set_rev(TEST_USB_PORT, TCPCI_MSG_SOP, PD_REV30); + tcpci_snk_emul_clear_alert_received(&fixture->snk_ext); zassert_false(fixture->snk_ext.alert_received, NULL); zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL); -- cgit v1.2.1 From 400dc3285c5768cc338b205edaf20f807c979104 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Wed, 22 Jun 2022 10:27:44 -0600 Subject: test: drivers: fix get/set ec_rate tests The motionsense host command for get/set ec_rate depend on the S3/S5 default state set in devicetree. Use S3 as the power state for these tests. BRANCH=none BUG=b:233355058 TEST=zephyr.elf -seed=$(date +%s) Signed-off-by: Yuval Peress Change-Id: I9c9a0716c6bbe2c231b07cca0dd1542f8b8f1347 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3722119 Reviewed-by: Al Semjonovs --- zephyr/test/drivers/src/host_cmd/motion_sense.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/zephyr/test/drivers/src/host_cmd/motion_sense.c b/zephyr/test/drivers/src/host_cmd/motion_sense.c index 84bd0e8132..6e12b2dc11 100644 --- a/zephyr/test/drivers/src/host_cmd/motion_sense.c +++ b/zephyr/test/drivers/src/host_cmd/motion_sense.c @@ -232,6 +232,10 @@ ZTEST_USER(host_cmd_motion_sense, test_get_ec_rate) { struct ec_response_motion_sense response; + /* Set the power level to S3, the default config from device-tree is for + * 100ms + */ + test_set_chipset_to_power_level(POWER_S3); zassert_ok(host_cmd_motion_sense_ec_rate( /*sensor_num=*/0, /*data_rate_ms=*/EC_MOTION_SENSE_NO_VALUE, @@ -244,6 +248,10 @@ ZTEST_USER(host_cmd_motion_sense, test_set_ec_rate) { struct ec_response_motion_sense response; + /* Set the power level to S3, the default config from device-tree is for + * 100ms + */ + test_set_chipset_to_power_level(POWER_S3); zassert_ok(host_cmd_motion_sense_ec_rate( /*sensor_num=*/0, /*data_rate_ms=*/2000, &response), NULL); -- cgit v1.2.1 From a80a4a914013efd4117772636fffdb016e4d4b38 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Tue, 21 Jun 2022 12:42:07 -0600 Subject: test: drivers: fix test order dependency The motionsense host command depends on the sensor at index 0 to be initialized. Normally this is done by the motion sense task, but we can also do it via the console command. Add the call to the console command accelinit to initialize the sensor before each test. Note: the console command is tested in another suite so we can just assume it works here. BRANCH=none BUG=b:233355058 TEST=zephyr.elf -seed=$(date +%s) Signed-off-by: Yuval Peress Change-Id: Icc28197be7a03c2ec269bd5961bc5d62fade320d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715441 Reviewed-by: Aaron Massey --- zephyr/test/drivers/src/host_cmd/motion_sense.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/zephyr/test/drivers/src/host_cmd/motion_sense.c b/zephyr/test/drivers/src/host_cmd/motion_sense.c index 6e12b2dc11..8661343872 100644 --- a/zephyr/test/drivers/src/host_cmd/motion_sense.c +++ b/zephyr/test/drivers/src/host_cmd/motion_sense.c @@ -4,9 +4,11 @@ */ #include +#include #include #include "atomic.h" +#include "console.h" #include "driver/accel_bma2x2.h" #include "motion_sense.h" #include "motion_sense_fifo.h" @@ -68,6 +70,8 @@ static void host_cmd_motion_sense_before(void *fixture) RESET_FAKE(mock_perform_calib); FFF_RESET_HISTORY(); + zassume_ok(shell_execute_cmd(get_ec_shell(), "accelinit 0"), NULL); + atomic_clear(&motion_sensors[0].flush_pending); motion_sensors[0].config[SENSOR_CONFIG_AP].odr = 0; motion_sensors[0].config[SENSOR_CONFIG_AP].ec_rate = 1000 * MSEC; -- cgit v1.2.1 From bebafe08b77715b5c495b90c05714639e9579435 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Tue, 21 Jun 2022 12:43:14 -0600 Subject: test: drivers: fix test order dependency for motionsense dump The motionsense host command for dumping the sensor state incorrectly tested the module_flags (based on another test having set the mmap). Explicitly set the mmap flag for accelerometer presense and test both code paths. BRANCH=none BUG=b:233355058 TEST=zephyr.elf -seed=$(date +%s) Signed-off-by: Yuval Peress Change-Id: Ib8b1c45870a0236c43e4598aef24c1bb26165a9f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715442 Reviewed-by: Wai-Hong Tam --- zephyr/test/drivers/src/host_cmd/motion_sense.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/zephyr/test/drivers/src/host_cmd/motion_sense.c b/zephyr/test/drivers/src/host_cmd/motion_sense.c index 8661343872..accc4193e0 100644 --- a/zephyr/test/drivers/src/host_cmd/motion_sense.c +++ b/zephyr/test/drivers/src/host_cmd/motion_sense.c @@ -104,10 +104,15 @@ ZTEST_USER(host_cmd_motion_sense, test_dump) motion_sensors[i].xyz[1] = i + 1; motion_sensors[i].xyz[2] = i + 2; } + + /* Make sure that the accelerometer status presence bit is off */ + *host_get_memmap(EC_MEMMAP_ACC_STATUS) &= + ~(EC_MEMMAP_ACC_STATUS_PRESENCE_BIT); + + /* Dump all the sensors info */ host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result); - zassert_equal(result->dump.module_flags, MOTIONSENSE_MODULE_FLAG_ACTIVE, - NULL); + zassert_equal(result->dump.module_flags, 0, NULL); zassert_equal(result->dump.sensor_count, ALL_MOTION_SENSORS, NULL); /* @@ -123,6 +128,16 @@ ZTEST_USER(host_cmd_motion_sense, test_dump) zassert_equal(result->dump.sensor[i].data[1], i + 1, NULL); zassert_equal(result->dump.sensor[i].data[2], i + 2, NULL); } + + /* Make sure that the accelerometer status presence bit is on */ + *host_get_memmap(EC_MEMMAP_ACC_STATUS) |= + EC_MEMMAP_ACC_STATUS_PRESENCE_BIT; + + /* Dump all the sensors info */ + host_cmd_motion_sense_dump(ALL_MOTION_SENSORS, result); + + zassert_equal(result->dump.module_flags, MOTIONSENSE_MODULE_FLAG_ACTIVE, + NULL); } ZTEST_USER(host_cmd_motion_sense, test_dump__large_max_sensor_count) -- cgit v1.2.1 From 920d5ee7adf5826d29214ee6215da2cf7dc003d5 Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Tue, 21 Jun 2022 16:08:33 -0600 Subject: zephyr: tests: Add USB-PD rev 3.0 extended msg support to emul This CL adds functionality to the port partner emulator common code for sending PD revision 3 extended messages. * Add a new function for sending extended messages * Refactor the allocator function into one for extended messages and another for standard messages * Update set_header function to fill the extended bit properly BUG=b:223452169 BRANCH=None TEST=zmake test test-drivers Signed-off-by: Tristan Honscheid Change-Id: Ieadfd523a8ab0686a2ba88f2fe1e575d0e9db481 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706077 Reviewed-by: Abe Levkoy --- include/usb_pd.h | 12 ++- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 114 +++++++++++++++++++-- .../include/emul/tcpc/emul_tcpci_partner_common.h | 34 +++--- 3 files changed, 134 insertions(+), 26 deletions(-) diff --git a/include/usb_pd.h b/include/usb_pd.h index d5b6412d69..b9f891d51c 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -1140,7 +1140,7 @@ bool pd_get_partner_unconstr_power(int port); */ void pd_resume_check_pr_swap_needed(int port); -/* Control Message type */ +/* Control Message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-5 */ enum pd_ctrl_msg_type { PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */ PD_CTRL_GOOD_CRC = 1, @@ -1245,7 +1245,7 @@ enum pd_sdb_power_indicator { PD_SDB_POWER_INDICATOR_BREATHING = (3 << 3), }; -/* Extended message type for REV 3.0 */ +/* Extended message type for REV 3.0 - USB-PD Spec 3.0, Ver 1.1, Table 6-42 */ enum pd_ext_msg_type { /* 0 Reserved */ PD_EXT_SOURCE_CAP = 1, @@ -1292,7 +1292,7 @@ enum ado_extended_alert_event_type { ADO_CONTROLLER_INITIATED_WAKE = 0x4, }; -/* Data message type */ +/* Data message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-6 */ enum pd_data_msg_type { /* 0 Reserved */ PD_DATA_SOURCE_CAP = 1, @@ -1359,12 +1359,14 @@ enum cable_outlet { #define PD_DEFAULT_STATE(port) PD_STATE_SRC_DISCONNECTED #endif -/* build extended message header */ -/* All extended messages are chunked, so set bit 15 */ +/* Build extended message header with chunking */ #define PD_EXT_HEADER(cnum, rchk, dsize) \ (BIT(15) | ((cnum) << 11) | \ ((rchk) << 10) | (dsize)) +/* Build extended message header without chunking */ +#define PD_EXT_HEADER_UNCHUNKED(dsize) (dsize) + /* build message header */ #define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \ ((type) | ((rev) << 6) | \ diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 49c5278908..9bbe0eb1fa 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -15,11 +15,14 @@ LOG_MODULE_REGISTER(tcpci_partner, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include "emul/tcpc/emul_tcpci_partner_common.h" #include "emul/tcpc/emul_tcpci.h" #include "usb_pd.h" +#include "util.h" /** Length of PDO, RDO and BIST request object in SOP message in bytes */ #define TCPCI_MSG_DO_LEN 4 /** Length of header in SOP message in bytes */ #define TCPCI_MSG_HEADER_LEN 2 +/** Length of extended header in bytes */ +#define TCPCI_MSG_EXT_HEADER_LEN 2 void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data, enum pd_power_role power_role) @@ -29,17 +32,26 @@ void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data, PD_ROLE_UFP; } -struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects) +/** + * @brief Allocate space for a PD message. Do not call directly; use + * tcpci_partner_alloc_standard_msg() or + * tcpci_partner_alloc_extended_msg() depending on the type of message. + * + * @param size Size of the message in bytes, including header(s) + * + * @return Pointer to new message on success + * @return NULL on error + */ +static struct tcpci_partner_msg *tcpci_partner_alloc_msg_helper(size_t size) { struct tcpci_partner_msg *new_msg; - size_t size = TCPCI_MSG_HEADER_LEN + TCPCI_MSG_DO_LEN * data_objects; - new_msg = malloc(sizeof(struct tcpci_partner_msg)); + new_msg = calloc(1, sizeof(struct tcpci_partner_msg)); if (new_msg == NULL) { return NULL; } - new_msg->msg.buf = malloc(size); + new_msg->msg.buf = calloc(1, size); if (new_msg->msg.buf == NULL) { free(new_msg); return NULL; @@ -48,11 +60,70 @@ struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects) /* Set default message type to SOP */ new_msg->msg.type = TCPCI_MSG_SOP; new_msg->msg.cnt = size; - new_msg->data_objects = data_objects; return new_msg; } +/** + * @brief Allocate space for a standard (non-extended) message, containing the + * specified number of data objects. + * + * @param num_data_objects Number of 32-bit DOs this message contains, if data + * message. Pass 0 if control message. + * @return struct tcpci_partner_msg* if successful + * @return NULL in case of error + */ +static struct tcpci_partner_msg * +tcpci_partner_alloc_standard_msg(int num_data_objects) +{ + struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper( + TCPCI_MSG_HEADER_LEN + TCPCI_MSG_DO_LEN * num_data_objects); + + if (msg) { + msg->data_objects = num_data_objects; + } + + return msg; +} + +/** + * @brief Allocate space for an extended message, containing a payload of + * specified size + * + * @param payload_size Size of extended message payload. Do not count either + * message header. + * @return struct tcpci_partner_msg* if successful + * @return NULL in case of error + */ +static struct tcpci_partner_msg * +tcpci_partner_alloc_extended_msg(size_t payload_size) +{ + /* Currently, the emulators only support extended messages that can fit + * into a single chunk. Enforce that here. + */ + + __ASSERT(payload_size <= PD_MAX_EXTENDED_MSG_CHUNK_LEN, + "Message must fit into a single chunk"); + + struct tcpci_partner_msg *msg = tcpci_partner_alloc_msg_helper( + TCPCI_MSG_HEADER_LEN + TCPCI_MSG_EXT_HEADER_LEN + payload_size); + + if (msg) { + msg->extended = true; + + /* Update the number of data objects with the number of 4-byte + * words in the payload, rounding up. This includes the 2-byte + * Extended Message Header (USB-PD spec Rev 3.0, V1.1, + * section 6.2.1.2.1) + */ + + msg->data_objects = DIV_ROUND_UP( + payload_size + TCPCI_MSG_EXT_HEADER_LEN, 4); + } + + return msg; +} + /** * @brief Alloc and append message to log if collect_msg_log flag is set * @@ -125,7 +196,7 @@ void tcpci_partner_set_header(struct tcpci_partner_data *data, uint16_t msg_id = data->msg_id & 0x7; uint16_t header = PD_HEADER(msg->type, data->power_role, data->data_role, msg_id, msg->data_objects, - data->rev, 0 /* ext */); + data->rev, msg->extended); data->msg_id++; msg->msg.buf[1] = (header >> 8) & 0xff; @@ -311,7 +382,7 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, { struct tcpci_partner_msg *msg; - msg = tcpci_partner_alloc_msg(0); + msg = tcpci_partner_alloc_standard_msg(0); if (msg == NULL) { return -ENOMEM; } @@ -336,7 +407,7 @@ int tcpci_partner_send_data_msg(struct tcpci_partner_data *data, struct tcpci_partner_msg *msg; int addr; - msg = tcpci_partner_alloc_msg(data_obj_num); + msg = tcpci_partner_alloc_standard_msg(data_obj_num); if (msg == NULL) { return -ENOMEM; } @@ -416,7 +487,7 @@ void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data) tcpci_partner_common_hard_reset(data); - msg = tcpci_partner_alloc_msg(0); + msg = tcpci_partner_alloc_standard_msg(0); msg->msg.type = TCPCI_MSG_TX_HARD_RESET; tcpci_partner_send_msg(data, msg, 0); @@ -437,6 +508,31 @@ void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data) tcpci_partner_start_sender_response_timer(data); } +int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data, + enum pd_ext_msg_type type, uint64_t delay, + uint8_t *payload, size_t payload_size) +{ + struct tcpci_partner_msg *msg; + + msg = tcpci_partner_alloc_extended_msg(payload_size); + if (msg == NULL) { + return -ENOMEM; + } + + msg->type = type; + + /* Apply extended message header. We currently do not support + * multiple chunks. + */ + + sys_put_le16(PD_EXT_HEADER(0, 0, payload_size), &msg->msg.buf[2]); + + /* Copy in payload */ + memcpy(&msg->msg.buf[4], payload, payload_size); + + return tcpci_partner_send_msg(data, msg, delay); +} + /** * @brief Handler for response timeout * diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index 4988c48576..972c422102 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -150,10 +150,17 @@ struct tcpci_partner_msg { struct tcpci_emul_msg msg; /** Time when message should be sent if message is delayed */ uint64_t time; - /** Type of the message */ + /** Message type that is placed in the Message Header. Its meaning + * depends on the class of message: + * - for Control Messages, see `enum pd_ctrl_msg_type` + * - for Data Messages, see `enum pd_data_msg_type` + * - for Extended Messages, see `enum pd_ext_msg_type` + */ int type; /** Number of data objects */ int data_objects; + /** True if this is an extended message */ + bool extended; }; /** Identify sender of logged PD message */ @@ -279,17 +286,6 @@ struct tcpci_partner_extension_ops { */ void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev); -/** - * @brief Allocate message with space for header and given number of data - * objects. Type of message is set to TCPCI_MSG_SOP by default. - * - * @param data_objects Number of data objects in message - * - * @return Pointer to new message on success - * @return NULL on error - */ -struct tcpci_partner_msg *tcpci_partner_alloc_msg(int data_objects); - /** * @brief Free message's memory * @@ -360,6 +356,20 @@ int tcpci_partner_send_data_msg(struct tcpci_partner_data *data, uint32_t *data_obj, int data_obj_num, uint64_t delay); +/** + * @brief Send an extended PD message to the port partner + * + * @param data Pointer to TCPCI partner emulator + * @param type Extended message type + * @param delay Message send delay in milliseconds, or zero for no delay. + * @param payload Pointer to data payload. Does not include any headers. + * @param payload_size Number of bytes in above payload + * @return negative on failure, 0 on success + */ +int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data, + enum pd_ext_msg_type type, uint64_t delay, + uint8_t *payload, size_t payload_size); + /** * @brief Remove all messages that are in delayed message queue * -- cgit v1.2.1 From e933734f8c7359e2f2d20bb5affd5baf12011318 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Tue, 21 Jun 2022 11:46:45 -0600 Subject: test: Fix usb_alt_mode in-suite exec order flake The tcpci_tcpc_alert function requires a short virtual wait within the USB alternate mode test suite before connecting a port emulator in order to ensure the partner emulator attaches to the port. This was made apparent when adding a second test to the test suite. Insert this wait in the before test suite handler of the usb alt mode test. BRANCH=none BUG=b:233100881 BUG=b:219562077 TEST=zmake test test-drivers Signed-off-by: Aaron Massey Change-Id: I8c7e78146e5f634644c36269cbb2d6eb6824274c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715439 Reviewed-by: Abe Levkoy --- zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 2123d26092..b23946d0f4 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -34,6 +34,11 @@ static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture) const struct emul *tcpc_emul = fixture->tcpci_emul; struct tcpci_partner_data *partner_emul = &fixture->partner; + /* + * TODO(b/221439302) Updating the TCPCI emulator registers, updating the + * vbus, as well as alerting should all be a part of the connect + * function. + */ /* Set VBUS to vSafe0V initially. */ isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS, @@ -41,6 +46,7 @@ static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture) tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V); tcpci_tcpc_alert(0); + k_sleep(K_SECONDS(1)); zassume_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul), NULL); -- cgit v1.2.1 From 0f3c291879aec5afe7dce52e053232b108da56ee Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Mon, 20 Jun 2022 17:41:16 +1000 Subject: ap_pwrseq: Refactor exit-hardoff handling Redo the exit-hardoff handling so that the S5 inactivity timer is extended to give the AP more time to handle a button press, and also to clear the request flag when transitioning out of S5 to S4. This is avoid the situation when the request-exit-hardoff flag is set in S5, but the AP does not enter G3 because it is restarting (e.g via a cold reboot). Rename exit-hardoff to start_from_g3, and use thread-safe setting and clearing of flags. BUG=b:234572032,b:235429065 TEST=Run firmware_ECPowerButton test BRANCH=none Signed-off-by: Andrew McRae Change-Id: I8039bf9a1c28ec24dfd313c52bbc0e2aeb7e6d59 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3713882 Reviewed-by: Peter Marheine --- zephyr/subsys/ap_pwrseq/ap_power_interface.c | 2 +- .../subsys/ap_pwrseq/include/x86_common_pwrseq.h | 5 - .../include/x86_non_dsx_common_pwrseq_sm_handler.h | 4 +- .../x86_non_dsx_common_pwrseq_host_command.c | 4 +- .../x86_non_dsx_common_pwrseq_sm_handler.c | 103 +++++++++++++++------ 5 files changed, 82 insertions(+), 36 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/ap_power_interface.c b/zephyr/subsys/ap_pwrseq/ap_power_interface.c index d6dc352033..c959f4b976 100644 --- a/zephyr/subsys/ap_pwrseq/ap_power_interface.c +++ b/zephyr/subsys/ap_pwrseq/ap_power_interface.c @@ -107,7 +107,7 @@ void ap_power_exit_hardoff(void) power_state != SYS_POWER_STATE_S5G3 && power_state != SYS_POWER_STATE_S5) return; - request_exit_hardoff(true); + request_start_from_g3(); } void ap_power_init_reset_log(void) diff --git a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h index 526b0b6ca6..4d369f5497 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_common_pwrseq.h @@ -16,11 +16,6 @@ struct pwrseq_context { /* On power-on start boot up sequence */ enum power_states_ndsx power_state; - /* Indicate should exit G3 power state or not */ - bool want_g3_exit; - /* Indicate to exit G3 state or not with delay in ms*/ - uint32_t reboot_ap_at_g3_delay_ms; - }; #endif /* __X86_COMMON_PWRSEQ_H__ */ diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h index f874879f04..81f5fbd477 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h @@ -23,11 +23,11 @@ enum power_states_ndsx chipset_pwr_sm_run(enum power_states_ndsx curr_state); void init_chipset_pwr_seq_state(void); enum power_states_ndsx chipset_pwr_seq_get_state(void); -void request_exit_hardoff(bool should_exit); +void request_start_from_g3(void); enum power_states_ndsx pwr_sm_get_state(void); const char * const pwr_sm_get_state_name(enum power_states_ndsx state); void apshutdown(void); void ap_pwrseq_handle_chipset_reset(void); -void set_reboot_ap_at_g3_delay_seconds(uint32_t d_time); +void set_start_from_g3_delay_seconds(uint32_t d_time); #endif /* __X86_NON_DSX_COMMON_PWRSEQ_SM_HANDLER_H__ */ diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c index 7bacbcd8cd..0a27fd98f0 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c @@ -12,14 +12,14 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args) const struct ec_params_reboot_ap_on_g3_v1 *cmd = args->params; /* Store request for processing at g3 */ - request_exit_hardoff(true); + request_start_from_g3(); switch (args->version) { case 0: break; case 1: /* Store user specified delay to wait in G3 state */ - set_reboot_ap_at_g3_delay_seconds(cmd->reboot_ap_at_g3_delay); + set_start_from_g3_delay_seconds(cmd->reboot_ap_at_g3_delay); break; default: return EC_RES_INVALID_PARAM; diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index 29d1ce3b1f..561c789e80 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -3,6 +3,7 @@ * found in the LICENSE file. */ +#include #include #include @@ -11,9 +12,20 @@ static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE); static struct k_thread pwrseq_thread_data; static struct pwrseq_context pwrseq_ctx; -static bool s5_inactive_tmr_running; /* S5 inactive timer*/ K_TIMER_DEFINE(s5_inactive_timer, NULL, NULL); +/* + * Flags, may be set/cleared from other threads. + */ +enum { + S5_INACTIVE_TIMER_RUNNING, + START_FROM_G3, + FLAGS_MAX, +}; +static ATOMIC_DEFINE(flags, FLAGS_MAX); +/* Delay in ms when starting from G3 */ +static uint32_t start_from_g3_delay_ms; + LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); @@ -96,14 +108,28 @@ void pwr_sm_set_state(enum power_states_ndsx new_state) pwrseq_ctx.power_state = new_state; } -void request_exit_hardoff(bool should_exit) -{ - pwrseq_ctx.want_g3_exit = should_exit; -} - -static bool chipset_is_exit_hardoff(void) +/* + * Set a flag to enable starting the AP once it is in G3. + * This is called from ap_power_exit_hardoff() which checks + * to ensure that the AP is in S5 or G3 state before calling + * this function. + * It can also be called via a hostcmd, which allows the flag + * to be set in any AP state. + */ +void request_start_from_g3(void) { - return pwrseq_ctx.want_g3_exit; + LOG_INF("Request start from G3"); + atomic_set_bit(flags, START_FROM_G3); + /* + * If in S5, restart the timer to give the CPU more time + * to respond to a power button press (which is presumably + * why we are being called). This avoids having the S5 + * inactivity timer expiring before the AP can process + * the power button press and start up. + */ + if (pwr_sm_get_state() == SYS_POWER_STATE_S5) { + atomic_clear_bit(flags, S5_INACTIVE_TIMER_RUNNING); + } } void ap_power_force_shutdown(enum ap_power_shutdown_reason reason) @@ -118,9 +144,9 @@ static void shutdown_and_notify(enum ap_power_shutdown_reason reason) ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN_COMPLETE); } -void set_reboot_ap_at_g3_delay_seconds(uint32_t d_time) +void set_start_from_g3_delay_seconds(uint32_t d_time) { - pwrseq_ctx.reboot_ap_at_g3_delay_ms = d_time * MSEC; + start_from_g3_delay_ms = d_time * MSEC; } void apshutdown(void) @@ -191,15 +217,16 @@ static int common_pwr_sm_run(int state) { switch (state) { case SYS_POWER_STATE_G3: - if (chipset_is_exit_hardoff()) { - request_exit_hardoff(false); - /* - * G3->S0 transition should happen only after the - * user specified delay. Hence, wait until the - * user specified delay times out. - */ - k_msleep(pwrseq_ctx.reboot_ap_at_g3_delay_ms); - pwrseq_ctx.reboot_ap_at_g3_delay_ms = 0; + /* + * If the START_FROM_G3 flag is set, begin starting + * the AP. There may be a delay set, so only start + * after that delay. + */ + if (atomic_test_and_clear_bit(flags, START_FROM_G3)) { + LOG_INF("Starting from G3, delay %d ms", + start_from_g3_delay_ms); + k_msleep(start_from_g3_delay_ms); + start_from_g3_delay_ms = 0; return SYS_POWER_STATE_G3S5; } @@ -222,24 +249,48 @@ static int common_pwr_sm_run(int state) rsmrst_pass_thru_handler(); if (signals_valid_and_off(IN_PCH_SLP_S5)) { k_timer_stop(&s5_inactive_timer); - s5_inactive_tmr_running = false; + /* Clear the timer running flag */ + atomic_clear_bit(flags, + S5_INACTIVE_TIMER_RUNNING); + /* Clear any request to exit hard-off */ + atomic_clear_bit(flags, START_FROM_G3); + LOG_INF("Clearing request to exit G3"); return SYS_POWER_STATE_S5S4; } } - /* S5 inactivity timeout, go to S5G3 */ + /* + * S5 state has an inactivity timer, so moving + * to S5G3 (where the power rails are turned off) is + * delayed for some time, usually ~10 seconds or so. + * The purpose of this delay is: + * - to handle AP initiated cold boot, where the AP + * will go to S5 for a short time and then restart. + * - give time for the power button to be pressed, + * which may set the START_FROM_G3 flag. + */ if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) == 0) return SYS_POWER_STATE_S5G3; else if (AP_PWRSEQ_DT_VALUE(s5_inactivity_timeout) > 0) { - if (!s5_inactive_tmr_running) { - /* Timer is not started */ + /* + * Test and set timer running flag. + * If it was 0, then the timer wasn't running + * and it is started (and the flag is set), + * otherwise it is already set, so no change. + */ + if (!atomic_test_and_set_bit(flags, + S5_INACTIVE_TIMER_RUNNING)) { + /* + * Timer is not started, or needs + * restarting. + */ k_timer_start(&s5_inactive_timer, K_SECONDS(AP_PWRSEQ_DT_VALUE( s5_inactivity_timeout)), K_NO_WAIT); - s5_inactive_tmr_running = true; } else if (k_timer_status_get(&s5_inactive_timer) > 0) { /* Timer is expired */ - s5_inactive_tmr_running = false; + atomic_clear_bit(flags, + S5_INACTIVE_TIMER_RUNNING); return SYS_POWER_STATE_S5G3; } } @@ -539,7 +590,7 @@ void ap_pwrseq_task_start(void) static void init_pwr_seq_state(void) { - request_exit_hardoff(false); + atomic_clear_bit(flags, START_FROM_G3); /* * The state of the CPU needs to be determined now * so that init routines can check the state of -- cgit v1.2.1 From 0733d3918377b2ad43b1698c069c5ac0085769f7 Mon Sep 17 00:00:00 2001 From: ridden_liu Date: Fri, 24 Jun 2022 16:36:05 +0800 Subject: Banshee: modify BBR I2C frequency to 400kHz Modify BBR I2C frequency to 400kHz BUG=b:226724606 BRANCH=none TEST=EE test I2C bus rising time pass. Signed-off-by: ridden_liu Change-Id: I646d5da766c855a6010c60f47dc8965e627a9b7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721941 Reviewed-by: caveh jalali Reviewed-by: Elthan Huang --- board/banshee/i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/banshee/i2c.c b/board/banshee/i2c.c index ed92cfbf82..69220b08d6 100644 --- a/board/banshee/i2c.c +++ b/board/banshee/i2c.c @@ -40,7 +40,7 @@ const struct i2c_port_t i2c_ports[] = { /* I2C3 */ .name = "retimer0,1", .port = I2C_PORT_USB_C0_C1_MUX, - .kbps = 1000, + .kbps = 400, .scl = GPIO_EC_I2C_USB_C0_C1_RT_SCL, .sda = GPIO_EC_I2C_USB_C0_C1_RT_SDA, }, @@ -64,7 +64,7 @@ const struct i2c_port_t i2c_ports[] = { /* I2C6 */ .name = "retimer2,3", .port = I2C_PORT_USB_C2_C3_MUX, - .kbps = 1000, + .kbps = 400, .scl = GPIO_EC_I2C_USB_C2_C3_RT_SCL, .sda = GPIO_EC_I2C_USB_C2_C3_RT_SDA, }, -- cgit v1.2.1 From b0c050b3c67cc0e49b7b9d6e1cbed870fccdf212 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Thu, 23 Jun 2022 13:08:09 +1000 Subject: espi: Use VW PLTRST# instead of ESPI bus reset for reset hook The legacy EC-OS uses the virtual wire signal PLTRST# to drive the HOOK_CHIPSET_RESET hook. Align the Zephyr espi shim to also use this VW signal instead of using the espi bus reset callback. This causes the reset hook to be called in warm boot as well as cold boot. BUG=b:236902047 TEST=zmake build nivviks; flash & reboot BRANCH=none Signed-off-by: Andrew McRae Change-Id: Ib9bb2cf60d4efa895158527163d4d86cdd7e5f8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715184 Reviewed-by: Peter Marheine Reviewed-by: Wai-Hong Tam --- zephyr/shim/src/espi.c | 72 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 48 insertions(+), 24 deletions(-) diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c index 74f6b70f42..03a3eaf59b 100644 --- a/zephyr/shim/src/espi.c +++ b/zephyr/shim/src/espi.c @@ -32,6 +32,24 @@ LOG_MODULE_REGISTER(espi_shim, CONFIG_ESPI_LOG_LEVEL); +/* + * Some functions are compiled depending on combinations of + * CONFIG_PLATFORM_EC_POWERSEQ, CONFIG_AP_PWRSEQ and + * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK. + * + * Tests are compiled without CONFIG_PLATFORM_EC_POWERSEQ and + * CONFIG_AP_PWRSEQ defined, but use the lpc functions. + * + * Legacy vwire power signal handling is required + * by CONFIG_PLATFORM_EC_POWERSEQ. + * + * CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK is used to handle + * the PLTRST# vwire signal separate to the legacy power signal handling. + * + * Where !defined(CONFIG_AP_PWRSEQ) is used, the code is required either + * by the tests, or by the legacy power signal handling. + */ + /* host command packet handler structure */ static struct host_packet lpc_packet; /* @@ -95,6 +113,7 @@ static enum espi_vwire_signal signal_to_zephyr_vwire(enum espi_vw_signal signal) } } +#if defined(CONFIG_PLATFORM_EC_POWERSEQ) /* Translate a Zephyr vwire to a platform/ec signal */ static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire) { @@ -105,6 +124,7 @@ static enum espi_vw_signal zephyr_vwire_to_signal(enum espi_vwire_signal vwire) return -1; } } +#endif /* defined(CONFIG_PLATFORM_EC_POWERSEQ) */ /* * Bit field for each signal which can have an interrupt enabled. @@ -126,22 +146,12 @@ static uint32_t signal_to_interrupt_bit(enum espi_vw_signal signal) } } -/* Callback for vwire received */ -static void espi_vwire_handler(const struct device *dev, - struct espi_callback *cb, - struct espi_event event) -{ - int ec_signal = zephyr_vwire_to_signal(event.evt_details); - - if (IS_ENABLED(CONFIG_PLATFORM_EC_POWERSEQ) && - (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal))) { - power_signal_interrupt(ec_signal); - } -} - #endif /* !defined(CONFIG_AP_PWRSEQ) */ #ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK +/* + * Deferred handler for PLTRST processing. + */ static void espi_chipset_reset(void) { if (IS_ENABLED(CONFIG_AP_PWRSEQ)) { @@ -151,16 +161,35 @@ static void espi_chipset_reset(void) } } DECLARE_DEFERRED(espi_chipset_reset); +#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */ -/* Callback for reset */ -static void espi_reset_handler(const struct device *dev, +/* + * Callback for vwire received. + * PLTRST (platform reset) is handled specially by + * invoking HOOK_CHIPSET_RESET. + */ +#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \ + defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK) +static void espi_vwire_handler(const struct device *dev, struct espi_callback *cb, struct espi_event event) { - hook_call_deferred(&espi_chipset_reset_data, MSEC); +#if defined(CONFIG_PLATFORM_EC_POWERSEQ) + int ec_signal = zephyr_vwire_to_signal(event.evt_details); + if (signal_interrupt_enabled & signal_to_interrupt_bit(ec_signal)) { + power_signal_interrupt(ec_signal); + } +#endif +#if defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK) + /* If PLTRST# asserted (low) then send reset hook */ + if (event.evt_details == ESPI_VWIRE_SIGNAL_PLTRST && + event.evt_data == 0) { + hook_call_deferred(&espi_chipset_reset_data, MSEC); + } +#endif } -#endif /* CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK */ +#endif #define espi_dev DEVICE_DT_GET(DT_CHOSEN(cros_ec_espi)) @@ -558,7 +587,8 @@ static int zephyr_shim_setup_espi(const struct device *unused) espi_callback_handler_t handler; enum espi_bus_event event_type; } callbacks[] = { -#if !defined(CONFIG_AP_PWRSEQ) +#if defined(CONFIG_PLATFORM_EC_POWERSEQ) || \ + defined(CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK) { .handler = espi_vwire_handler, .event_type = ESPI_BUS_EVENT_VWIRE_RECEIVED, @@ -568,12 +598,6 @@ static int zephyr_shim_setup_espi(const struct device *unused) .handler = espi_peripheral_handler, .event_type = ESPI_BUS_PERIPHERAL_NOTIFICATION, }, -#ifdef CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK - { - .handler = espi_reset_handler, - .event_type = ESPI_BUS_RESET, - }, -#endif }; struct espi_cfg cfg = { -- cgit v1.2.1 From 02cfc94955b8087d4a0d131dd2f3e3938df349bf Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Fri, 24 Jun 2022 10:40:01 +1000 Subject: ap_pwrseq: Add test for PLTRST# ESPI handling. Add a test for PLTRST# ESPI handling. BUG=none TEST=zmake test test-ap_power BRANCH=none Signed-off-by: Andrew McRae Change-Id: I5a390eec1eff7610661e8401cf8cc526901c53d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721158 Reviewed-by: Wai-Hong Tam --- zephyr/test/ap_power/prj.conf | 1 + zephyr/test/ap_power/src/events.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/zephyr/test/ap_power/prj.conf b/zephyr/test/ap_power/prj.conf index 86c3f5082d..2229f0af32 100644 --- a/zephyr/test/ap_power/prj.conf +++ b/zephyr/test/ap_power/prj.conf @@ -54,6 +54,7 @@ CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION=y CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE=y CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD=y CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y # These items are not required. CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/test/ap_power/src/events.c b/zephyr/test/ap_power/src/events.c index de695e945f..426f879177 100644 --- a/zephyr/test/ap_power/src/events.c +++ b/zephyr/test/ap_power/src/events.c @@ -10,6 +10,8 @@ #include +#include +#include #include #include #include @@ -79,6 +81,36 @@ ZTEST(events, test_registration) ap_power_ev_remove_callback(&cb.cb); } +/** + * @brief TestPurpose: Verify reset callback from ESPI + * + * @details + * Validate that the reset callback is sent with ESPI PLTRST# + * + * Expected Results + * - The AP_POWER_RESET event is sent + */ +ZTEST(events, test_pltrst) +{ + static struct events cb; + const struct device *espi = + DEVICE_DT_GET_ANY(zephyr_espi_emul_controller); + + zassert_not_null(espi, "Cannot get ESPI device"); + + ap_power_ev_init_callback(&cb.cb, ev_handler, AP_POWER_RESET); + ap_power_ev_add_callback(&cb.cb); + + emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_PLTRST, 0); + /* + * Since the event is being sent via a deferred function, + * wait for the deferral time. + */ + k_usleep(2 * 1000); + zassert_equal(1, cb.count, "Callback not called"); + zassert_equal(AP_POWER_RESET, cb.event, "Wrong event"); +} + /** * @brief TestPurpose: Check event mask changes * -- cgit v1.2.1 From 02c753ab1c89d293c9e4c5845b1fa2d6cc9948e4 Mon Sep 17 00:00:00 2001 From: Zentaro Kavanagh Date: Fri, 24 Jun 2022 13:34:39 +0000 Subject: Revert "taniks: modify RGB mapping table for 4 zone" This reverts commit 6abe6202a5536caee467d7f665697d2bf23ac78e. Reason for revert: https://b.corp.google.com/issues/237080616 Original change's description: > taniks: modify RGB mapping table for 4 zone > > Modify RGB led mapping table for 4 zone. > > BUG=b:227522597, b:231747095 > BRANCH=none > TEST=make buildall -j > ectool rgbkbd 1 0xffffff > ectool rgbkbd 2 0xffffff > ... > ectool rgbkbd 127 0xffffff > > Signed-off-by: arthur.lin > Change-Id: I1d7ae552a0b16be048598dc2b65bd9cc385a58b4 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3653757 > Reviewed-by: Daisuke Nojiri > Commit-Queue: Daisuke Nojiri Bug: b:227522597, b:231747095 Change-Id: I9876152495a15c8aafa3a3be976294aceccb15d8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3723682 Tested-by: Daisuke Nojiri Reviewed-by: Parth Malkan Commit-Queue: Daisuke Nojiri --- board/taniks/keyboard.c | 172 ++++++++++++------------------------------------ 1 file changed, 42 insertions(+), 130 deletions(-) diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c index 99099b4661..4c055d292b 100644 --- a/board/taniks/keyboard.c +++ b/board/taniks/keyboard.c @@ -69,136 +69,48 @@ const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; #define LED(x, y) RGBKBD_COORD((x), (y)) #define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, /* 0: (null) */ - LED( 0, 0), DELM, /* 1: ~ ` */ - LED( 2, 0), LED( 4, 0), DELM, /* 2: ! 1 */ - LED( 6, 0), DELM, /* 3: @ 2 */ - LED( 0, 1), DELM, /* 4: # 3 */ - LED( 2, 1), DELM, /* 5: $ 4 */ - LED( 4, 1), LED( 6, 1), DELM, /* 6: % 5 */ - LED( 0, 2), DELM, /* 7: ^ 6 */ - LED( 2, 2), DELM, /* 8: & 7 */ - LED( 4, 2), DELM, /* 9: * 8 */ - LED( 6, 2), DELM, /* 10: ( 9 */ - LED( 0, 3), DELM, /* 11: ) 0 */ - LED( 1, 3), DELM, /* 12: _ - */ - LED( 3, 3), DELM, /* 13: + = */ - DELM, /* 14: (null) */ - LED( 5, 3), LED( 6, 3), DELM, /* 15: backspace */ - LED( 0, 0), DELM, /* 16: tab */ - LED( 2, 0), LED( 4, 0), DELM, /* 17: q */ - LED( 6, 0), DELM, /* 18: w */ - LED( 0, 1), DELM, /* 19: e */ - LED( 2, 1), DELM, /* 20: r */ - LED( 4, 1), LED( 6, 1), DELM, /* 21: t */ - LED( 0, 2), DELM, /* 22: y */ - LED( 2, 2), DELM, /* 23: u */ - LED( 4, 2), DELM, /* 24: i */ - LED( 6, 2), DELM, /* 25: o */ - LED( 0, 3), LED( 1, 3), DELM, /* 26: p */ - LED( 3, 3), DELM, /* 27: [ { */ - LED( 5, 3), DELM, /* 28: ] } */ - LED( 6, 3), DELM, /* 29: \ | */ - LED( 0, 0), DELM, /* 30: caps lock */ - LED( 2, 0), LED( 4, 0), DELM, /* 31: a */ - LED( 6, 0), DELM, /* 32: s */ - LED( 0, 1), DELM, /* 33: d */ - LED( 2, 1), DELM, /* 34: f */ - LED( 4, 1), LED( 6, 1), DELM, /* 35: g */ - LED( 0, 2), DELM, /* 36: h */ - LED( 2, 2), DELM, /* 37: j */ - LED( 4, 2), DELM, /* 38: k */ - LED( 6, 4), DELM, /* 39: l */ - LED( 0, 3), LED( 1, 3), DELM, /* 40: ; : */ - LED( 3, 3), DELM, /* 41: " ' */ - DELM, /* 42: (null) */ - LED( 5, 3), LED( 6, 3), DELM, /* 43: enter */ - LED( 1, 0), LED( 3, 0), DELM, /* 44: L-shift */ - DELM, /* 45: (null) */ - LED( 5, 0), DELM, /* 46: z */ - LED( 7, 0), DELM, /* 47: x */ - LED( 1, 1), DELM, /* 48: c */ - LED( 3, 1), DELM, /* 49: v */ - LED( 5, 1), LED( 7, 1), DELM, /* 50: b */ - LED( 1, 2), DELM, /* 51: n */ - LED( 3, 2), DELM, /* 52: m */ - LED( 5, 2), DELM, /* 53: , < */ - LED( 7, 2), DELM, /* 54: . > */ - LED( 2, 3), DELM, /* 55: / ? */ - DELM, /* 56: (null) */ - LED( 4, 3), LED( 7, 3), DELM, /* 57: R-shift */ - LED( 1, 0), LED( 3, 0), DELM, /* 58: L-ctrl */ - LED( 5, 3), LED( 6, 3), DELM, /* 59: power */ - LED( 5, 0), LED( 7, 0), DELM, /* 60: L-alt */ - LED( 1, 1), LED( 3, 1), - LED( 5, 1), LED( 7, 1), - LED( 1, 2), LED( 3, 2), DELM, /* 61: space */ - LED( 5, 2), DELM, /* 62: R-alt */ - DELM, /* 63: (null) */ - LED( 7, 2), DELM, /* 64: R-ctrl */ - DELM, /* 65: (null) */ - DELM, /* 66: (null) */ - DELM, /* 67: (null) */ - DELM, /* 68: (null) */ - DELM, /* 69: (null) */ - DELM, /* 70: (null) */ - DELM, /* 71: (null) */ - DELM, /* 72: (null) */ - DELM, /* 73: (null) */ - DELM, /* 74: (null) */ - DELM, /* 75: (null) */ - LED( 0, 4), DELM, /* 76: delete */ - DELM, /* 77: (null) */ - DELM, /* 78: (null) */ - LED( 2, 3), DELM, /* 79: left */ - LED( 4, 4), DELM, /* 80: home */ - LED( 6, 4), DELM, /* 81: end */ - DELM, /* 82: (null) */ - LED( 4, 3), DELM, /* 83: up */ - LED( 4, 3), DELM, /* 84: down */ - LED( 0, 4), DELM, /* 85: page up */ - LED( 2, 4), DELM, /* 86: page down */ - DELM, /* 87: (null) */ - DELM, /* 88: (null) */ - LED( 7, 3), DELM, /* 89: right */ - DELM, /* 90: (null) */ - LED( 0, 4), DELM, /* 91: numpad 7 */ - LED( 0, 4), DELM, /* 92: numpad 4 */ - LED( 1, 4), DELM, /* 93: numpad 1 */ - DELM, /* 94: (null) */ - LED( 2, 4), DELM, /* 95: numpad / */ - LED( 2, 4), DELM, /* 96: numpad 8 */ - LED( 2, 4), DELM, /* 97: numpad 5 */ - LED( 3, 4), DELM, /* 98: numpad 2 */ - LED( 3, 4), DELM, /* 99: numpad 0 */ - LED( 4, 4), DELM, /* 100: numpad * */ - LED( 4, 4), DELM, /* 101: numpad 9 */ - LED( 4, 4), DELM, /* 102: numpad 6 */ - LED( 5, 4), DELM, /* 103: numpad 3 */ - LED( 5, 4), DELM, /* 104: numpad . */ - LED( 6, 4), DELM, /* 105: numpad - */ - LED( 6, 4), DELM, /* 106: numpad + */ - DELM, /* 107: (null) */ - LED( 7, 4), DELM, /* 108: numpad enter */ - DELM, /* 109: (null) */ - LED( 0, 0), DELM, /* 110: esc */ - LED( 2, 0), LED( 4, 0), DELM, /* T1: back */ - LED( 6, 0), DELM, /* T2: refresh */ - LED( 0, 1), DELM, /* T3: full screen */ - LED( 2, 1), DELM, /* T4: overview */ - LED( 4, 1), LED( 6, 1), DELM, /* T5: snapshot */ - LED( 0, 2), DELM, /* T6: brightness down */ - LED( 2, 2), DELM, /* T7: brightness up */ - DELM, /* T8: (null) */ - DELM, /* T9: (null) */ - DELM, /* T10: (null) */ - LED( 4, 2), DELM, /* T11: mic mute */ - LED( 6, 2), DELM, /* T12: volume mute */ - LED( 0, 3), LED( 1, 3), DELM, /* T13: volume down */ - LED( 3, 3), DELM, /* T14: volume up */ - DELM, /* T15: (null) */ - DELM, /* 126: (null) */ - DELM, /* 127: (null) */ + DELM, + LED( 0, 0), DELM, + LED( 1, 0), DELM, + LED( 2, 0), DELM, + LED( 3, 0), DELM, + LED( 4, 0), DELM, + LED( 5, 0), DELM, + LED( 6, 0), DELM, + LED( 7, 0), DELM, + LED( 0, 1), DELM, + LED( 1, 1), DELM, + LED( 2, 1), DELM, + LED( 3, 1), DELM, + LED( 4, 1), DELM, + LED( 5, 1), DELM, + LED( 6, 1), DELM, + LED( 7, 1), DELM, + LED( 0, 2), DELM, + LED( 1, 2), DELM, + LED( 2, 2), DELM, + LED( 3, 2), DELM, + LED( 4, 2), DELM, + LED( 5, 2), DELM, + LED( 6, 2), DELM, + LED( 7, 2), DELM, + LED( 0, 3), DELM, + LED( 1, 3), DELM, + LED( 2, 3), DELM, + LED( 3, 3), DELM, + LED( 4, 3), DELM, + LED( 5, 3), DELM, + LED( 6, 3), DELM, + LED( 7, 3), DELM, + LED( 0, 4), DELM, + LED( 1, 4), DELM, + LED( 2, 4), DELM, + LED( 3, 4), DELM, + LED( 4, 4), DELM, + LED( 5, 4), DELM, + LED( 6, 4), DELM, + LED( 7, 4), DELM, + DELM, }; #undef LED #undef DELM -- cgit v1.2.1 From 6157536779a62334a16b1f1d406558ab25c6cb77 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Fri, 3 Jun 2022 17:15:22 -0600 Subject: test: Verify DisplayPort mode entry path Verify that after DisplayPort is advertised as supported by a port partner via USB alternate mode Discovery commands, the Device Policy manager should enter the mode and configure the port partner for DisplayPort alternate mode. BRANCH=none BUG=b:219562077 TEST=zmake test test-drivers Signed-off-by: Aaron Massey Change-Id: I933ad770239cae1d2b8de716504347a8701c6667 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3689787 Reviewed-by: Abe Levkoy Tested-by: Abe Levkoy --- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 31 +++++- .../include/emul/tcpc/emul_tcpci_partner_common.h | 12 +++ .../drivers/src/integration/usbc/usb_alt_mode.c | 116 ++++++++++++++++----- 3 files changed, 134 insertions(+), 25 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 9bbe0eb1fa..39f1101241 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -30,6 +30,7 @@ void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data, data->power_role = power_role; data->data_role = power_role == PD_ROLE_SOURCE ? PD_ROLE_DFP : PD_ROLE_UFP; + data->displayport_configured = false; } /** @@ -616,7 +617,33 @@ tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data, data->modes_vdos, 0); } return TCPCI_PARTNER_COMMON_MSG_HANDLED; - /* TODO(b/219562077): Support DP mode entry. */ + case CMD_ENTER_MODE: + /* Partner emulator only supports entering DP mode */ + if (data->dp_enter_mode_vdos > 0 && + (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) { + tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF, + data->dp_enter_mode_vdm, + data->dp_enter_mode_vdos, + 0); + } + return TCPCI_PARTNER_COMMON_MSG_HANDLED; + case CMD_DP_STATUS: + if (data->dp_status_vdos > 0 && + (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) { + tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF, + data->dp_status_vdm, + data->dp_status_vdos, 0); + } + return TCPCI_PARTNER_COMMON_MSG_HANDLED; + case CMD_DP_CONFIG: + if (data->dp_config_vdos > 0 && + (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) { + tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF, + data->dp_config_vdm, + data->dp_config_vdos, 0); + data->displayport_configured = true; + } + return TCPCI_PARTNER_COMMON_MSG_HANDLED; default: /* TCPCI r. 2.0: Ignore unsupported commands. */ return TCPCI_PARTNER_COMMON_MSG_HANDLED; @@ -877,6 +904,7 @@ void tcpci_partner_common_disconnect(struct tcpci_partner_data *data) tcpci_partner_clear_msg_queue(data); tcpci_partner_stop_sender_response_timer(data); data->tcpci_emul = NULL; + data->displayport_configured = false; } int tcpci_partner_common_enable_pd_logging(struct tcpci_partner_data *data, @@ -1240,4 +1268,5 @@ void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev) data->ops.rx_consumed = tcpci_partner_rx_consumed_op; data->ops.control_change = NULL; data->ops.disconnect = tcpci_partner_disconnect_op; + data->displayport_configured = false; } diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index 972c422102..c5d31694a8 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -129,6 +129,9 @@ struct tcpci_partner_data { * any status to received message. */ enum tcpci_emul_tx_status *received_msg_status; + /** Whether port partner is configured in DisplayPort mode */ + bool displayport_configured; + /* VDMs with which the partner responds to discovery REQs. The VDM * buffers include the VDM header, and the VDO counts include 1 for the * VDM header. This structure has space for the mode response for a @@ -140,6 +143,15 @@ struct tcpci_partner_data { int svids_vdos; uint32_t modes_vdm[VDO_MAX_SIZE]; int modes_vdos; + /* VDMs sent when responding to DisplayPort mode entry command */ + uint32_t dp_enter_mode_vdm[VDO_MAX_SIZE]; + int dp_enter_mode_vdos; + /* VDMs sent when responding to DisplayPort status update command */ + uint32_t dp_status_vdm[VDO_MAX_SIZE]; + int dp_status_vdos; + /* VDMs sent when responding to DisplayPort config command */ + uint32_t dp_config_vdm[VDO_MAX_SIZE]; + int dp_config_vdos; }; /** Structure of message used by TCPCI partner emulator */ diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index b23946d0f4..851f3c0da2 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -61,25 +61,9 @@ static void disconnect_partner_from_port(struct usbc_alt_mode_fixture *fixture) k_sleep(K_SECONDS(1)); } -static void *usbc_alt_mode_setup(void) +static void add_discovery_responses(struct tcpci_partner_data *partner) { - static struct usbc_alt_mode_fixture fixture; - struct tcpci_partner_data *partner = &fixture.partner; - struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; - - tcpci_partner_init(partner, PD_REV20); - partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); - - /* Get references for the emulators */ - fixture.tcpci_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); - /* The configured TCPCI rev must match the emulator's supported rev. */ - tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - fixture.charger_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - - /* Set up SOP discovery responses for DP adapter. */ + /* Add Discover Identity response */ partner->identity_vdm[VDO_INDEX_HDR] = VDO(USB_SID_PD, /* structured VDM */ true, VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT); @@ -92,6 +76,16 @@ static void *usbc_alt_mode_setup(void) partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000; partner->identity_vdos = VDO_INDEX_AMA + 1; + /* Add Discover Modes response */ + /* Support one mode for DisplayPort VID. Copied from Hoho. */ + partner->modes_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES); + partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP( + 0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK); + partner->modes_vdos = VDO_INDEX_HDR + 2; + + /* Add Discover SVIDs response */ /* Support DisplayPort VID. */ partner->svids_vdm[VDO_INDEX_HDR] = VDO(USB_SID_PD, /* structured VDM */ true, @@ -99,14 +93,63 @@ static void *usbc_alt_mode_setup(void) partner->svids_vdm[VDO_INDEX_HDR + 1] = VDO_SVID(USB_SID_DISPLAYPORT, 0); partner->svids_vdos = VDO_INDEX_HDR + 2; +} - /* Support one mode for DisplayPort VID. Copied from Hoho. */ - partner->modes_vdm[VDO_INDEX_HDR] = +static void add_displayport_mode_responses(struct tcpci_partner_data *partner) +{ + /* DisplayPort alt mode setup remains in the same suite as discovery + * setup because DisplayPort is picked from the Discovery VDOs offered. + */ + + /* Add DisplayPort EnterMode response */ + partner->dp_enter_mode_vdm[VDO_INDEX_HDR] = VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES); - partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP( - 0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK); - partner->modes_vdos = VDO_INDEX_HDR + 2; + VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE); + partner->dp_enter_mode_vdos = VDO_INDEX_HDR + 1; + + /* Add DisplayPort StatusUpdate response */ + partner->dp_status_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS); + partner->dp_status_vdm[VDO_INDEX_HDR + 1] = + /* Mainly copied from hoho */ + VDO_DP_STATUS(0, /* IRQ_HPD */ + false, /* HPD_HI|LOW - Changed*/ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + true, /* DP Enabled */ + 0, /* power low e.g. normal */ + 0x2 /* Connected as Sink */); + partner->dp_status_vdos = VDO_INDEX_HDR + 2; + + /* Add DisplayPort Configure Response */ + partner->dp_config_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG); + partner->dp_config_vdos = VDO_INDEX_HDR + 1; +} + +static void *usbc_alt_mode_setup(void) +{ + static struct usbc_alt_mode_fixture fixture; + struct tcpci_partner_data *partner = &fixture.partner; + struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; + + tcpci_partner_init(partner, PD_REV20); + partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); + + /* Get references for the emulators */ + fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + /* The configured TCPCI rev must match the emulator's supported rev. */ + tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); + fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + add_discovery_responses(partner); + add_displayport_mode_responses(partner); /* Sink 5V 3A. */ snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); @@ -162,5 +205,30 @@ ZTEST_F(usbc_alt_mode, verify_discovery) "DP mode VDOs did not match"); } +ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) +{ + /* Verify host command when VDOs are present. */ + struct ec_params_usb_pd_get_mode_request params = { + .port = TEST_PORT, + .svid_idx = 0, + }; + struct ec_params_usb_pd_get_mode_response response; + struct host_cmd_handler_args args = BUILD_HOST_COMMAND( + EC_CMD_USB_PD_GET_AMODE, 0, response, params); + + zassume_ok(host_command_process(&args), NULL); + zassume_ok(args.result, NULL); + + /* Response should be populated with a DisplayPort VDO */ + zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); + zassert_equal(response.vdo[0], + fixture->partner.modes_vdm[response.opos], NULL); + + /* DPM configures the partner on DP mode entry */ + /* Verify port partner thinks its configured for DisplayPort */ + zassert_true(fixture->partner.displayport_configured, NULL); +} + ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, usbc_alt_mode_before, usbc_alt_mode_after, NULL); -- cgit v1.2.1 From dd55312e6f8d6d6ec92ced1851ac131e89b14c1b Mon Sep 17 00:00:00 2001 From: Manoj Gupta Date: Mon, 27 Jun 2022 17:05:05 +0000 Subject: zephyr: Disable position independent code Zephyr does not handle position independent code so disable it. BUG=b:237245366 TEST=zmake build -a BRANCH=none Signed-off-by: Manoj Gupta Change-Id: I0e036b617c8ef79139df69f799b3debccacebb6f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726956 Tested-by: Manoj Gupta Reviewed-by: Jeremy Bettis Auto-Submit: Manoj Gupta Commit-Queue: Jeremy Bettis --- zephyr/CMakeLists.txt | 2 ++ zephyr/cmake/compiler/clang/compiler_flags.cmake | 3 +++ zephyr/cmake/compiler/gcc/compiler_flags.cmake | 3 +++ zephyr/cmake/linker/lld/target.cmake | 1 + 4 files changed, 9 insertions(+) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 451406c8b3..fbee307dc4 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -65,6 +65,8 @@ endif() # Set extra compiler flags. zephyr_cc_option(-mno-unaligned-access) +zephyr_cc_option(-fno-PIC) + if (DEFINED CONFIG_RISCV) zephyr_cc_option(-fsanitize=integer-divide-by-zero) zephyr_cc_option(-fsanitize-undefined-trap-on-error) diff --git a/zephyr/cmake/compiler/clang/compiler_flags.cmake b/zephyr/cmake/compiler/clang/compiler_flags.cmake index 5f97625a58..6b86a8705a 100644 --- a/zephyr/cmake/compiler/clang/compiler_flags.cmake +++ b/zephyr/cmake/compiler/clang/compiler_flags.cmake @@ -7,6 +7,9 @@ include("${ZEPHYR_BASE}/cmake/compiler/clang/compiler_flags.cmake") # Disable -fno-freestanding. set_compiler_property(PROPERTY hosted) +# Disable position independent code. +add_compile_options(-fno-PIC) + check_set_compiler_property(APPEND PROPERTY warning_extended -Wunused-variable -Werror=unused-variable -Werror=missing-braces -Werror=sometimes-uninitialized -Werror=unused-function diff --git a/zephyr/cmake/compiler/gcc/compiler_flags.cmake b/zephyr/cmake/compiler/gcc/compiler_flags.cmake index 125f909c87..b5a6d01d5f 100644 --- a/zephyr/cmake/compiler/gcc/compiler_flags.cmake +++ b/zephyr/cmake/compiler/gcc/compiler_flags.cmake @@ -5,3 +5,6 @@ # Zephyr cmake system looks into ${TOOLCHAIN_ROOT}, but we just send # this out to the copy in ${ZEPHYR_BASE}. include("${ZEPHYR_BASE}/cmake/compiler/gcc/compiler_flags.cmake") + +# Disable position independent code. +add_compile_options(-fno-PIC) diff --git a/zephyr/cmake/linker/lld/target.cmake b/zephyr/cmake/linker/lld/target.cmake index 1bbc6f479d..3f1356440e 100644 --- a/zephyr/cmake/linker/lld/target.cmake +++ b/zephyr/cmake/linker/lld/target.cmake @@ -21,6 +21,7 @@ macro(toolchain_ld_base) # Default flags zephyr_ld_options( ${TOOLCHAIN_LD_FLAGS} + -no-pie -Wl,--gc-sections --build-id=none) endmacro() -- cgit v1.2.1 From 568c2f61ffc3ec2c4b2a490546efe5833b1e7f5d Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Mon, 27 Jun 2022 11:49:10 -0600 Subject: zmake: Add flags to build boards and delete tmps The gitlab builder is running out of disk space. Add flags to build fewer things, and to delete the intermediate files and only leave the output files. Before this change zmake build of all boards took 2.1G, and 81M afterwards. BRANCH=None BUG=None TEST=make clobber TEST=zmake build --boards-only -c --delete-intermediates TEST=du -s -h build Change-Id: I507abff512ca1348681a1fd7431d5267efaf5d65 Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726959 Commit-Queue: Jack Rosenthal Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal --- .gitlab-ci.yml | 2 +- zephyr/zmake/README.md | 12 +++++++--- zephyr/zmake/zmake/__main__.py | 12 ++++++++++ zephyr/zmake/zmake/zmake.py | 50 +++++++++++++++++++++++++++++++----------- 4 files changed, 59 insertions(+), 17 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index a6e7ad4d5a..069ffca1f5 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -251,7 +251,7 @@ zephyr_boards_coverage: script: - zmake --zephyr-base "${ZEPHYR_BASE}" --modules-dir "${MODULES_DIR}" -l DEBUG build - --coverage -a + --coverage --boards-only --delete-intermediates artifacts: paths: - build/zephyr/all_builds.info diff --git a/zephyr/zmake/README.md b/zephyr/zmake/README.md index 6e2690959b..a329396038 100644 --- a/zephyr/zmake/README.md +++ b/zephyr/zmake/README.md @@ -35,7 +35,7 @@ Chromium OS's meta-build tool for Zephyr ### zmake configure -**Usage:** `zmake configure [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])` +**Usage:** `zmake configure [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | --host-tests-only | --boards-only | project_name [project_name ...])` #### Positional Arguments @@ -55,12 +55,14 @@ Chromium OS's meta-build tool for Zephyr | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} | | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. | | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds | +| `--delete-intermediates` | Delete intermediate files to save disk space | | `-a`, `--all` | Select all projects | | `--host-tests-only` | Select all test projects | +| `--boards-only` | Select all board projects (not tests) | ### zmake build -**Usage:** `zmake build [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])` +**Usage:** `zmake build [-h] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | --host-tests-only | --boards-only | project_name [project_name ...])` #### Positional Arguments @@ -80,8 +82,10 @@ Chromium OS's meta-build tool for Zephyr | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} | | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. | | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds | +| `--delete-intermediates` | Delete intermediate files to save disk space | | `-a`, `--all` | Select all projects | | `--host-tests-only` | Select all test projects | +| `--boards-only` | Select all board projects (not tests) | ### zmake list-projects @@ -102,7 +106,7 @@ Chromium OS's meta-build tool for Zephyr ### zmake test -**Usage:** `zmake test [-h] [--no-rebuild] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] (-a | --host-tests-only | project_name [project_name ...])` +**Usage:** `zmake test [-h] [--no-rebuild] [-t TOOLCHAIN] [--bringup] [--clobber] [--allow-warnings] [-B BUILD_DIR] [-c] [--extra-cflags EXTRA_CFLAGS] [--delete-intermediates] (-a | --host-tests-only | --boards-only | project_name [project_name ...])` #### Positional Arguments @@ -123,8 +127,10 @@ Chromium OS's meta-build tool for Zephyr | `-B BUILD_DIR`, `--build-dir BUILD_DIR` | Root build directory, project files will be in ${build_dir}/${project_name} | | `-c`, `--coverage` | Enable CONFIG_COVERAGE Kconfig. | | `--extra-cflags EXTRA_CFLAGS` | Additional CFLAGS to use for target builds | +| `--delete-intermediates` | Delete intermediate files to save disk space | | `-a`, `--all` | Select all projects | | `--host-tests-only` | Select all test projects | +| `--boards-only` | Select all board projects (not tests) | ### zmake testall diff --git a/zephyr/zmake/zmake/__main__.py b/zephyr/zmake/zmake/__main__.py index 23be20d54f..7054601ac1 100644 --- a/zephyr/zmake/zmake/__main__.py +++ b/zephyr/zmake/zmake/__main__.py @@ -288,6 +288,12 @@ def add_common_configure_args(sub_parser: argparse.ArgumentParser): "--extra-cflags", help="Additional CFLAGS to use for target builds", ) + sub_parser.add_argument( + "--delete-intermediates", + action="store_true", + dest="delete_intermediates", + help="Delete intermediate files to save disk space", + ) group = sub_parser.add_mutually_exclusive_group(required=True) group.add_argument( "-a", @@ -302,6 +308,12 @@ def add_common_configure_args(sub_parser: argparse.ArgumentParser): dest="host_tests_only", help="Select all test projects", ) + group.add_argument( + "--boards-only", + action="store_true", + dest="boards_only", + help="Select all board projects (not tests)", + ) group.add_argument( "project_names", nargs="*", diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py index d4af57a738..69c4239f69 100644 --- a/zephyr/zmake/zmake/zmake.py +++ b/zephyr/zmake/zmake/zmake.py @@ -198,7 +198,11 @@ class Zmake: return self._checkout.resolve() def _resolve_projects( - self, project_names, all_projects=False, host_tests_only=False + self, + project_names, + all_projects=False, + host_tests_only=False, + boards_only=False, ) -> Set[zmake.project.Project]: """Finds all projects for the specified command line flags. @@ -209,6 +213,8 @@ class Zmake: projects = set(found_projects.values()) elif host_tests_only: projects = {p for p in found_projects.values() if p.config.is_test} + elif boards_only: + projects = {p for p in found_projects.values() if not p.config.is_test} else: projects = set() for project_name in project_names: @@ -232,6 +238,8 @@ class Zmake: all_projects=False, host_tests_only=False, extra_cflags=None, + delete_intermediates=False, + boards_only=False, ): """Locate and configure the specified projects.""" # Resolve build_dir if needed. @@ -242,6 +250,7 @@ class Zmake: project_names, all_projects=all_projects, host_tests_only=host_tests_only, + boards_only=boards_only, ) for project in projects: project_build_dir = pathlib.Path(build_dir) / project.config.project_name @@ -259,6 +268,7 @@ class Zmake: allow_warnings=allow_warnings, extra_cflags=extra_cflags, multiproject=len(projects) > 1, + delete_intermediates=delete_intermediates, ) ) if self._sequential: @@ -302,6 +312,8 @@ class Zmake: all_projects=False, host_tests_only=False, extra_cflags=None, + delete_intermediates=False, + boards_only=False, ): """Locate and build the specified projects.""" return self.configure( @@ -316,6 +328,8 @@ class Zmake: host_tests_only=host_tests_only, extra_cflags=extra_cflags, build_after_configure=True, + delete_intermediates=delete_intermediates, + boards_only=boards_only, ) def test( # pylint: disable=too-many-arguments,too-many-locals @@ -331,6 +345,8 @@ class Zmake: host_tests_only=False, extra_cflags=None, no_rebuild=False, + delete_intermediates=False, + boards_only=False, ): """Locate and build the specified projects.""" if not no_rebuild: @@ -346,6 +362,8 @@ class Zmake: host_tests_only=host_tests_only, extra_cflags=extra_cflags, test_after_configure=True, + delete_intermediates=delete_intermediates, + boards_only=boards_only, ) # Resolve build_dir if needed. if not build_dir: @@ -355,6 +373,7 @@ class Zmake: project_names, all_projects=all_projects, host_tests_only=host_tests_only, + boards_only=boards_only, ) test_projects = [p for p in projects if p.config.is_test] for project in test_projects: @@ -416,7 +435,7 @@ class Zmake: def _configure( self, project, - build_dir=None, + build_dir: pathlib.Path, toolchain=None, build_after_configure=False, test_after_configure=False, @@ -426,20 +445,12 @@ class Zmake: allow_warnings=False, extra_cflags=None, multiproject=False, + delete_intermediates=False, ): # pylint: disable=too-many-arguments,too-many-locals,too-many-branches # pylint: disable=too-many-statements """Set up a build directory to later be built by "zmake build".""" try: - # Resolve build_dir if needed. - if not build_dir: - build_dir = ( - self.module_paths["ec"] - / "build" - / "zephyr" - / project.config.project_name - ) - # Clobber build directory if requested. if clobber and build_dir.exists(): self.logger.info( @@ -501,7 +512,7 @@ class Zmake: ) if not build_dir.exists(): - build_dir = build_dir.mkdir() + build_dir.mkdir() if not generated_include_dir.exists(): generated_include_dir.mkdir() processes = [] @@ -617,6 +628,16 @@ class Zmake: timeout=project.config.test_timeout_secs, ) ) + + if delete_intermediates: + outdir = build_dir / "output" + for child in build_dir.iterdir(): + if child != outdir: + logging.debug("Deleting %s", child) + if not child.is_symlink() and child.is_dir(): + shutil.rmtree(child) + else: + child.unlink() return 0 except Exception: self.failed_projects.append(project.config.project_name) @@ -711,7 +732,10 @@ class Zmake: ) job_id = "{}:{}".format(project.config.project_name, build_name) dirs[build_name].mkdir(parents=True, exist_ok=True) - build_log = open(dirs[build_name] / "build.log", "w") + build_log = open( # pylint:disable=consider-using-with + dirs[build_name] / "build.log", + "w", + ) out = zmake.multiproc.LogWriter.log_output( logger=self.logger, log_level=logging.INFO, -- cgit v1.2.1 From 9cb48657f0f58573b23eaf524c3989a43522cf98 Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Mon, 27 Jun 2022 13:02:42 -0600 Subject: zephyr:test: led control tests expect to be power S5 Flakey LED control test expects power level to be set to a soft off state BUG=none BRANCH=none TEST=zmake test test-drivers Signed-off-by: Al Semjonovs Change-Id: I9c5b9a606c8deb7d42b8f4362d705468e6976a1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727185 Reviewed-by: Yuval Peress --- zephyr/test/drivers/led_driver/src/led.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/zephyr/test/drivers/led_driver/src/led.c b/zephyr/test/drivers/led_driver/src/led.c index 5c0c9d0c01..3d029d4140 100644 --- a/zephyr/test/drivers/led_driver/src/led.c +++ b/zephyr/test/drivers/led_driver/src/led.c @@ -6,9 +6,11 @@ #include #include "ec_commands.h" #include "gpio.h" +#include "include/power.h" #include "led.h" #include "led_common.h" #include "test/drivers/test_state.h" +#include "test/drivers/utils.h" #define VERIFY_LED_COLOR(color, led_id) \ { \ @@ -27,6 +29,8 @@ ZTEST_SUITE(led_driver, drivers_predicate_post_main, NULL, NULL, NULL, NULL); ZTEST(led_driver, test_led_control) { + test_set_chipset_to_power_level(POWER_S5); + /* Exercise valid led_id, set to RESET state */ led_control(EC_LED_ID_SYSRQ_DEBUG_LED, LED_STATE_RESET); VERIFY_LED_COLOR(LED_OFF, EC_LED_ID_SYSRQ_DEBUG_LED); -- cgit v1.2.1 From 9711c893fbe53d3b2a5cab39fca3ab3511dbbfac Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 24 Jun 2022 23:39:00 -0700 Subject: ghost: Remove brya battery config This removes the experimental brya battery config from ghost. BRANCH=none BUG=b:230813416 TEST=make passes Change-Id: Iae42eed9f475e767946eda76bde92edb20790f84 Signed-off-by: Caveh Jalali Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3723553 Commit-Queue: Jack Rosenthal Reviewed-by: Jack Rosenthal --- board/ghost/battery.c | 32 +------------------------------- 1 file changed, 1 insertion(+), 31 deletions(-) diff --git a/board/ghost/battery.c b/board/ghost/battery.c index 50086b6c86..164436be9c 100644 --- a/board/ghost/battery.c +++ b/board/ghost/battery.c @@ -35,36 +35,6 @@ * address, mask, and disconnect value need to be provided. */ const struct board_batt_params board_battery_info[] = { - /* POW-TECH GQA05 Battery Information */ - [BATTERY_POWER_TECH] = { - /* BQ40Z50 Fuel Gauge */ - .fuel_gauge = { - .manuf_name = "POW-TECH", - .device_name = "BATGQA05L22", - .ship_mode = { - .reg_addr = 0x00, - .reg_data = { 0x0010, 0x0010 }, - }, - .fet = { - .mfgacc_support = 1, - .reg_addr = 0x00, - .reg_mask = 0x2000, /* XDSG */ - .disconnect_val = 0x2000, - } - }, - .batt_info = { - .voltage_max = TARGET_WITH_MARGIN(13050, 5), - .voltage_normal = 11400, /* mV */ - .voltage_min = 9000, /* mV */ - .precharge_current = 280, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 45, - .charging_min_c = 0, - .charging_max_c = 45, - .discharging_min_c = -10, - .discharging_max_c = 60, - }, - }, /* * TODO(b/233120385): verify these */ @@ -100,7 +70,7 @@ const struct board_batt_params board_battery_info[] = { }; BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); -const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_POWER_TECH; +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SWD_ATL; enum battery_present battery_hw_present(void) { -- cgit v1.2.1 From cdd87a52dcd7c6e510b3386365b4e46a1f42855e Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 24 Jun 2022 02:56:27 -0700 Subject: brya: Deprecate board ID 1 support This removes some code that supports a board version that is no longer supported. The list of header files is also adjusted. BRANCH=none BUG=b:237138941 TEST=boots on brya board ID 2 Change-Id: Id868bf53e266f9138d080633d9245b568d82da76 Signed-off-by: Caveh Jalali Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3723554 Commit-Queue: Jack Rosenthal Reviewed-by: Jack Rosenthal --- board/brya/battery.c | 5 +--- board/brya/board.c | 65 +++++------------------------------------------- board/brya/board.h | 6 +---- board/brya/gpio.inc | 33 +----------------------- board/brya/usbc_config.c | 52 ++++---------------------------------- 5 files changed, 14 insertions(+), 147 deletions(-) diff --git a/board/brya/battery.c b/board/brya/battery.c index 91faab57a3..000a483e6d 100644 --- a/board/brya/battery.c +++ b/board/brya/battery.c @@ -102,10 +102,7 @@ enum battery_present battery_hw_present(void) { enum gpio_signal batt_pres; - if (get_board_id() == 1) - batt_pres = GPIO_ID_1_EC_BATT_PRES_ODL; - else - batt_pres = GPIO_EC_BATT_PRES_ODL; + batt_pres = GPIO_EC_BATT_PRES_ODL; /* The GPIO is low when the battery is physically present */ return gpio_get_level(batt_pres) ? BP_NO : BP_YES; diff --git a/board/brya/board.c b/board/brya/board.c index c9246c197b..6b7f8a21b4 100644 --- a/board/brya/board.c +++ b/board/brya/board.c @@ -3,20 +3,18 @@ * found in the LICENSE file. */ -#include "battery.h" #include "button.h" +#include "cbi.h" #include "charge_ramp.h" #include "charger.h" #include "common.h" -#include "compile_time_macros.h" #include "console.h" -#include "gpio.h" -#include "gpio_signal.h" -#include "hooks.h" -#include "driver/accel_lis2dw12.h" #include "driver/accelgyro_lsm6dso.h" +#include "driver/accel_lis2dw12.h" #include "driver/als_tcs3400.h" #include "fw_config.h" +#include "gpio.h" +#include "gpio_signal.h" #include "hooks.h" #include "lid_switch.h" #include "power_button.h" @@ -43,10 +41,7 @@ static void board_chipset_resume(void) { /* Allow keyboard backlight to be enabled */ - if (get_board_id() == 1) - gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 1); - else - gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); + gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -55,54 +50,6 @@ static void board_chipset_suspend(void) { /* Turn off the keyboard backlight if it's on. */ - if (get_board_id() == 1) - gpio_set_level(GPIO_ID_1_EC_KB_BL_EN, 0); - else - gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); + gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); - -/* - * Explicitly apply the board ID 1 *gpio.inc settings to pins that - * were reassigned on current boards. - */ - -static void set_board_id_1_gpios(void) -{ - if (get_board_id() != 1) - return; - - gpio_set_flags(GPIO_ID_1_EC_KB_BL_EN, GPIO_OUT_LOW); -} -DECLARE_HOOK(HOOK_INIT, set_board_id_1_gpios, HOOK_PRIO_FIRST); - -/* - * Reclaim GPIO pins on board ID 1 that are used as ADC inputs on - * current boards. ALT function group MODULE_ADC pins are set in - * HOOK_PRIO_INIT_ADC and can be reclaimed right after the hook runs. - */ - -static void board_id_1_reclaim_adc(void) -{ - if (get_board_id() != 1) - return; - - /* - * GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL is on GPIO34 - * - * The TCPC has already been reset by board_tcpc_init() executed - * from HOOK_PRIO_INIT_CHIPSET. Later, the pin gets set to ADC6 - * in HOOK_PRIO_INIT_ADC, so we simply need to set the pin back - * to GPIO34. - */ - gpio_set_flags(GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL, GPIO_ODR_HIGH); - gpio_set_alternate_function(GPIO_PORT_3, BIT(4), GPIO_ALT_FUNC_NONE); - - /* - * The pin gets set to ADC7 in HOOK_PRIO_INIT_ADC, so we simply - * need to set it back to GPIOE1. - */ - gpio_set_flags(GPIO_ID_1_EC_BATT_PRES_ODL, GPIO_INPUT); - gpio_set_alternate_function(GPIO_PORT_E, BIT(1), GPIO_ALT_FUNC_NONE); -} -DECLARE_HOOK(HOOK_INIT, board_id_1_reclaim_adc, HOOK_PRIO_INIT_ADC + 1); diff --git a/board/brya/board.h b/board/brya/board.h index 8188ee68d9..88e5dc5915 100644 --- a/board/brya/board.h +++ b/board/brya/board.h @@ -83,7 +83,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 4 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_FRS_PPC @@ -147,8 +147,6 @@ #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL #define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL - /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT @@ -249,8 +247,6 @@ enum sensor_id { enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, - IOEX_ID_1_C0_NCT38XX, - IOEX_ID_1_C2_NCT38XX, IOEX_PORT_COUNT }; diff --git a/board/brya/gpio.inc b/board/brya/gpio.inc index e88d72eba8..0c6bba7a06 100644 --- a/board/brya/gpio.inc +++ b/board/brya/gpio.inc @@ -28,38 +28,7 @@ */ GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW) -/* - * GPIOE1 is an ALT function ADC INPUT on board ID 2 and a GPIO INPUT on - * board ID 1. This declaration gives us a signal name to use on board - * ID 1. - */ -GPIO(ID_1_EC_BATT_PRES_ODL, PIN(E, 1), GPIO_INPUT) - -/* - * GPIO34 is an INPUT on board ID 2 and ODR_LOW on board ID 1. - * - * Since this pin is pulled up to 3.3V through a 30.9K ohm resistor on - * board ID 2, we will leak about 0.3mW until the pin is put in ALT mode - * when MODULE_ADC configuration runs. Initializing the pin to ODR_LOW - * gives us full control on both boards. - */ -GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW) - -/* Board ID 1 IO expander configuration */ - -IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 2), GPIO_ODR_LOW) -/* GPIO03_P1 to PU */ -IOEX(ID_1_USB_C0_FRS_EN, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 4), GPIO_LOW) -IOEX(ID_1_USB_C0_OC_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH) -/* GPIO07_P1 to PU */ - -IOEX(ID_1_USB_C2_RT_RST_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) -/* GPIO03_P2 to PU */ -IOEX(ID_1_USB_C2_FRS_EN, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 4), GPIO_LOW) -IOEX(ID_1_USB_C1_OC_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH) -IOEX(ID_1_USB_C2_OC_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH) - -/* Board ID 2 IO expander configuration */ +/* IO expander configuration */ /* GPIO02_P2 to PU */ /* GPIO03_P2 to PU */ diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c index eb72412423..90d113ae51 100644 --- a/board/brya/usbc_config.c +++ b/board/brya/usbc_config.c @@ -43,8 +43,6 @@ enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, - IOEX_ID_1_C0_NCT38XX, - IOEX_ID_1_C2_NCT38XX, IOEX_PORT_COUNT }; #endif /* CONFIG_ZEPHYR */ @@ -215,18 +213,6 @@ struct ioexpander_config_t ioex_config[] = { .drv = &nct38xx_ioexpander_drv, .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, }, - [IOEX_ID_1_C0_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, - }, - [IOEX_ID_1_C2_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, - }, }; BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); #endif /* !CONFIG_ZEPHYR */ @@ -283,10 +269,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) if (me->usb_port == USBC_PORT_C0) { /* TODO: explore how to handle board id in zephyr*/ #ifndef CONFIG_ZEPHYR - if (get_board_id() == 1) - rst_signal = IOEX_ID_1_USB_C0_RT_RST_ODL; - else - rst_signal = IOEX_USB_C0_RT_RST_ODL; + rst_signal = IOEX_USB_C0_RT_RST_ODL; #else /* On Zephyr use bb_controls generated from DTS */ rst_signal = bb_controls[me->usb_port].retimer_rst_gpio; @@ -294,10 +277,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) } else if (me->usb_port == USBC_PORT_C2) { /* TODO: explore how to handle board id in zephyr*/ #ifndef CONFIG_ZEPHYR - if (get_board_id() == 1) - rst_signal = IOEX_ID_1_USB_C2_RT_RST_ODL; - else - rst_signal = IOEX_USB_C2_RT_RST_ODL; + rst_signal = IOEX_USB_C2_RT_RST_ODL; #else /* On Zephyr use bb_controls generated from DTS */ rst_signal = bb_controls[me->usb_port].retimer_rst_gpio; @@ -324,20 +304,6 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) * which powers I2C controller within retimer */ msleep(1); - if (get_board_id() == 1) { - int val; - - /* - * Check if we were able to deassert - * reset. Board ID 1 uses a GPIO that is - * uncontrollable when a debug accessory is - * connected. - */ - if (ioex_get_level(rst_signal, &val) != EC_SUCCESS) - return EC_ERROR_UNKNOWN; - if (val != 1) - return EC_ERROR_NOT_POWERED; - } } else { ioex_set_level(rst_signal, 0); msleep(1); @@ -350,10 +316,7 @@ void board_reset_pd_mcu(void) enum gpio_signal tcpc_rst; #ifndef CONFIG_ZEPHYR - if (get_board_id() == 1) - tcpc_rst = GPIO_ID_1_USB_C0_C2_TCPC_RST_ODL; - else - tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; + tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; #else tcpc_rst = GPIO_UNIMPLEMENTED; #endif /* !CONFIG_ZEPHYR */ @@ -397,13 +360,8 @@ static void board_tcpc_init(void) * been taken out of reset. */ #ifndef CONFIG_ZEPHYR - if (get_board_id() == 1) { - ioex_init(IOEX_ID_1_C0_NCT38XX); - ioex_init(IOEX_ID_1_C2_NCT38XX); - } else { - ioex_init(IOEX_C0_NCT38XX); - ioex_init(IOEX_C2_NCT38XX); - } + ioex_init(IOEX_C0_NCT38XX); + ioex_init(IOEX_C2_NCT38XX); #else gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port1))); gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_port2))); -- cgit v1.2.1 From 60530c83ebdf6d8d1b0e12003960f22a06341545 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 24 Jun 2022 23:15:29 -0700 Subject: brya: Remove MPS tuning for board ID 1 This removes code for tuning the MPS mp2964 for board ID 1. Board ID 1 is no longer in supported. BRANCH=none BUG=b:237138941 TEST=boots on brya Signed-off-by: Caveh Jalali Change-Id: I00176e47e75404dedd0634b8ad88e6a4d73abf56 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3723555 Commit-Queue: Jack Rosenthal Reviewed-by: Jack Rosenthal --- board/brya/build.mk | 1 - board/brya/tune_mp2964.c | 43 ------------------------------------------- 2 files changed, 44 deletions(-) delete mode 100644 board/brya/tune_mp2964.c diff --git a/board/brya/build.mk b/board/brya/build.mk index 674c17c1df..5ca5590ee1 100644 --- a/board/brya/build.mk +++ b/board/brya/build.mk @@ -22,5 +22,4 @@ board-y+=keyboard.o board-y+=led.o board-y+=pwm.o board-y+=sensors.o -board-y+=tune_mp2964.o board-y+=usbc_config.o diff --git a/board/brya/tune_mp2964.c b/board/brya/tune_mp2964.c deleted file mode 100644 index 198f06d8eb..0000000000 --- a/board/brya/tune_mp2964.c +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Tune the MP2964 IMVP9.1 parameters for brya */ - -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "hooks.h" -#include "mp2964.h" - -const static struct mp2964_reg_val rail_a[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ -}; -const static struct mp2964_reg_val rail_b[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ -}; - -static void mp2964_on_startup(void) -{ - static int chip_updated; - int status; - - if (get_board_id() != 1) - return; - - if (chip_updated) - return; - - chip_updated = 1; - - ccprintf("%s: attempting to tune PMIC\n", __func__); - - status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a), - rail_b, ARRAY_SIZE(rail_b)); - if (status != EC_SUCCESS) - ccprintf("%s: could not update all settings\n", __func__); -} - -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup, - HOOK_PRIO_FIRST); -- cgit v1.2.1 From 48319c2beb2eb92fa8b93f7d0d49484ce3125498 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 24 Jun 2022 22:16:22 -0700 Subject: brya: Only control KB_LB_EN when KBLIGHT is enabled This makes controlling the keyboard backlight enable GPIO conditional CONFIG_PWM_KBLIGHT. This allows full custom control over the PWM channel when KBLIGHT is not selected. BRANCH=none BUG=none TEST=boots on brya Change-Id: I6784a2d4bec7e6510d89610830eb7a564eeec2df Signed-off-by: Caveh Jalali Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3723556 Reviewed-by: Jack Rosenthal Commit-Queue: Jack Rosenthal --- board/brya/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/brya/board.c b/board/brya/board.c index 6b7f8a21b4..32c3aaed3e 100644 --- a/board/brya/board.c +++ b/board/brya/board.c @@ -41,7 +41,8 @@ static void board_chipset_resume(void) { /* Allow keyboard backlight to be enabled */ - gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); + if (IS_ENABLED(CONFIG_PWM_KBLIGHT)) + gpio_set_level(GPIO_EC_KB_BL_EN_L, 0); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -50,6 +51,7 @@ static void board_chipset_suspend(void) { /* Turn off the keyboard backlight if it's on. */ - gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); + if (IS_ENABLED(CONFIG_PWM_KBLIGHT)) + gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From ba29fdaa724aa0e585e1583ff8e5f73ef57f4eb2 Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Tue, 21 Jun 2022 19:10:12 -0600 Subject: zephyr: tests: Add Battery Capability Data Block struct definition Add a struct that models the fields of a USB-PD Battery Capability Data Block per USB Power Delivery Specification Revision 3.0, Version 1.1, table 6-47 BUG=b:223452169 BRANCH=None TEST=zmake test test-drivers Signed-off-by: Tristan Honscheid Change-Id: I31510c994a710b9d9e788c40e9be9942df265c8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715697 Reviewed-by: Abe Levkoy --- include/usb_pd.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/include/usb_pd.h b/include/usb_pd.h index b9f891d51c..2ce7bca177 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -1201,6 +1201,34 @@ enum pd_ctrl_msg_type { #define BCDB_FULL_CAP 3 #define BCDB_BATT_TYPE 4 +/* Battery Capability Data Block (BCDB) in struct format. + * See USB-PD spec Rev 3.1, V 1.3 section 6.5.5 + */ +struct pd_bcdb { + /* Vendor ID*/ + uint16_t vid; + /* Product ID */ + uint16_t pid; + /* Battery’s design capacity in 0.1 Wh (0 = no batt, 0xFFFF = unknown) + */ + uint16_t design_cap; + /* Battery’s last full charge capacity in 0.1 Wh (0 = no batt, + * 0xFFFF = unknown) + */ + uint16_t last_full_charge_cap; + /* Bit 0 indicates if the request was invalid. Other bits reserved. */ + uint8_t battery_type; +} __packed; + +/* Maximum number of different batteries that can be queried through Get Battery + * Status and Get Battery Capability requests. Indices 0 to 3 are fixed + * batteries and indices 4 to 7 are hot-swappable batteries. Not all are + * necessarily present. + * + * See USB-PD spec Rev 3.1, V 1.3 sections 6.5.4 - .5 + */ +#define PD_BATT_MAX (8) + /* * Get Battery Cap Message fields for REV 3.0 (assumes extended header is * present in first two bytes) -- cgit v1.2.1 From c398b3f2824e5e51fc9873b3f34412ab3cf909b2 Mon Sep 17 00:00:00 2001 From: Moises Garcia Date: Thu, 23 Jun 2022 14:08:46 -0700 Subject: flash_fp_mcu: Add config_skyrim BUG=b:228271993 BRANCH=NONE TEST=On skyrim device, ran /usr/local/bin/flash_fp_mcu and tested the fingerprint authentication in the UI Signed-off-by: Moises Garcia Change-Id: I48862e8b277bc24d5c48df5b75c8dc924ad4d890 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3719284 Reviewed-by: Jonathon Murphy Reviewed-by: Tom Hughes --- util/flash_fp_mcu | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index cc6e41080f..d31e3a836d 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -670,6 +670,20 @@ config_guybrush() { readonly GPIO_PWREN=259 } +config_skyrim() { + readonly TRANSPORT="UART" + + readonly DEVICE="/dev/ttyS1" + + readonly GPIO_CHIP="gpiochip768" + # FPMCU RST_ODL is on AGPIO 12 = 768 + 12 = 780 + readonly GPIO_NRST=780 + # FPMCU BOOT0 is on AGPIO 130 = 768 + 130 = 898 + readonly GPIO_BOOT0=898 + # FPMCU PWR_EN is on AGPIO 4 = 768 + 4 = 772 + readonly GPIO_PWREN=772 +} + main() { local filename="$1" -- cgit v1.2.1 From 3823427de7f1129e073bfb1fec468d8f5b7d1572 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 15:14:30 -0700 Subject: common/util: Remove __stdlib_compat from functions not in C standard library These functions are not in the C standard library, so they should not be annotated with __stdlib_compat. BRANCH=none BUG=b:234181908, b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: Iccc532764056dd22f93ffea170f2d7e422d1b6dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724166 Reviewed-by: Eric Yilun Lin --- common/util.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/util.c b/common/util.c index 7b33cc097e..f85eae5ebf 100644 --- a/common/util.c +++ b/common/util.c @@ -35,7 +35,7 @@ static int find_base(int base, int *c, const char **nptr) } /* Like strtol(), but for integers */ -__stdlib_compat int strtoi(const char *nptr, char **endptr, int base) +int strtoi(const char *nptr, char **endptr, int base) { int result = 0; int neg = 0; @@ -111,7 +111,7 @@ __stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr, #endif /* !CONFIG_ZEPHYR */ BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t)); -__stdlib_compat int parse_bool(const char *s, int *dest) +int parse_bool(const char *s, int *dest) { /* off, disable, false, no */ if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) || @@ -166,7 +166,7 @@ void reverse(void *dest, size_t len) } } -__stdlib_compat char *strzcpy(char *dest, const char *src, int len) +char *strzcpy(char *dest, const char *src, int len) { char *d = dest; if (len <= 0) -- cgit v1.2.1 From f7fd963888c90a975263bb3048d6765c60bae1be Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 13:27:28 -0700 Subject: Makefile.rules: Set C++ standard to gnu++17 "-std=gnu++17" is the C++ standard we currently use for the rest of ChromeOS. cmd_cxx_to_host was already updated to gnu++17 in https://crrev.com/c/2872429, but cmd_cxx_to_o was not. BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: Iab8adacaa8673bda7b6427745b85fd3b7550eb4e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712036 Reviewed-by: Paul Fagerburg --- Makefile.rules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.rules b/Makefile.rules index 3d79a5a65f..3ea1d08df7 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -101,7 +101,7 @@ cmd_run_fuzz = build/host/$*/$*.exe -seed=1 -runs=1 $(silent) \ cmd_exe = $(CC) $(ro-objs) $(HOST_TEST_LDFLAGS) $(LDFLAGS_EXTRA) -o $@ cmd_c_to_o = $(CC) -std=gnu11 $(C_WARN) $(CFLAGS) -MMD -MP -MF $@.d -c $< \ -MT $(@D)/$(@F) -o $(@D)/$(@F) -cmd_cxx_to_o = $(CXX) -std=c++11 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \ +cmd_cxx_to_o = $(CXX) -std=gnu++17 $(CFLAGS) $(CXXFLAGS) -MMD -MP -MF $@.d -c $< \ -MT $(@D)/$(@F) -o $(@D)/$(@F) cmd_c_to_build = $(BUILDCC) $(BUILD_CFLAGS) \ $(sort $(foreach c,$($(*F)-objs),util/$(c:%.o=%.c)) $(wildcard $*.c)) \ -- cgit v1.2.1 From c6b4e66382019fd8d16714ce9e7ee4ee64e149a0 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Sun, 26 Jun 2022 01:53:47 -0600 Subject: zephyr: test: split tests into separate binaries This is a first pass at spliting up the tests into different binaries. Doing this involved a small change in the zmake framework to pass the project name into CMake. Then, the root CMakeLists is able to add the correct subdirectory to the common sources. This will add that set of tests as a zephyr library. BRANCH=none BUG=none TEST=zmake test test-drivers-isl923x TEST=zmake test test-drivers-led_driver Signed-off-by: Yuval Peress Change-Id: Ida49ab5c4f1ec156365c854251f548eac00d2c5e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724970 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/BUILD.py | 55 ++++++++++++--- zephyr/test/drivers/CMakeLists.txt | 133 ++++++++++++++++++++----------------- zephyr/zmake/zmake/zmake.py | 1 + 3 files changed, 117 insertions(+), 72 deletions(-) diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py index c43579da2e..d8c2b6caab 100644 --- a/zephyr/test/drivers/BUILD.py +++ b/zephyr/test/drivers/BUILD.py @@ -2,17 +2,52 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -"""Register zmake project for drivers test.""" +"""Construct the drivers test binaries""" -register_host_test( - "drivers", - dts_overlays=[ - "overlay.dts", - here / "led_driver/led_pins.dts", - here / "led_driver/led_policy.dts", + +default_config = { + "dts_overlays": [ + here / "overlay.dts", ], - kconfig_files=[ - here / "led_driver/prj.conf", + "kconfig_files": [ + here / "prj.conf", ], - test_args=["-flash={test_temp_dir}/flash.bin"], + "test_args": ["-flash={test_temp_dir}/flash.bin"], +} + + +def merge_dictionary(dict_1, dict_2): + """Merge dict_1 and dict_2 and return the result""" + dict_3 = {**dict_1, **dict_2} + for key, value in dict_3.items(): + if key in dict_1 and key in dict_2: + if isinstance(value, list) or isinstance(dict_1[key], list): + dict_3[key] = value + dict_1[key] + else: + dict_3[key] = [value, dict_1[key]] + return dict_3 + + +register_host_test( + "drivers", + **default_config, +) + +register_host_test( + "drivers-isl923x", + **default_config, +) + +register_host_test( + "drivers-led_driver", + **merge_dictionary( + default_config, + { + "dts_overlays": [ + here / "led_driver" / "led_pins.dts", + here / "led_driver" / "led_policy.dts", + ], + "kconfig_files": [here / "led_driver" / "prj.conf"], + }, + ), ) diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index e5a92e4463..14608a659e 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -4,77 +4,86 @@ cmake_minimum_required(VERSION 3.13.1) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(drivers) +project(${ZMAKE_PROJECT_NAME}) -# Include the local test directory for shimmed_test_tasks.h -zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}") -zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") +zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include) zephyr_include_directories("${PLATFORM_EC}/driver/ppc/") +# Common sources target_sources(app PRIVATE - src/battery.c - src/bb_retimer.c - src/bc12.c - src/bma2x2.c - src/bmi160.c - src/bmi260.c - src/charge_manager.c - src/chargesplash.c - src/console_cmd/charge_manager.c - src/console_cmd/charge_state.c - src/console_cmd/accelinit.c - src/console_cmd/accelinfo.c - src/console_cmd/accelspoof.c - src/console_cmd/accelrate.c - src/console_cmd/accelrange.c - src/console_cmd/accelread.c - src/console_cmd/accelres.c - src/console_cmd/usb_pd_console.c - src/cros_cbi.c - src/espi.c - src/gpio.c - src/host_cmd/host_event_commands.c - src/host_cmd/motion_sense.c - src/integration/usbc/usb.c - src/integration/usbc/usb_20v_3a_pd_charger.c - src/integration/usbc/usb_5v_3a_pd_sink.c - src/integration/usbc/usb_5v_3a_pd_source.c - src/integration/usbc/usb_alt_mode.c - src/integration/usbc/usb_attach_src_snk.c - src/integration/usbc/usb_pd_ctrl_msg.c - src/integration/usbc/usb_malfunction_sink.c - src/i2c_passthru.c - src/isl923x.c - src/keyboard_scan.c - src/lid_switch.c - src/lis2dw12.c - src/ln9310.c src/main.c - src/motion_sense/motion_sense.c - src/panic.c - src/power_common.c - src/ppc_sn5s330.c - src/ppc_syv682x.c - src/ps8xxx.c - src/smart.c - src/stm_mems_common.c - src/stubs.c - src/tcpci.c - src/tcpci_test_common.c - src/tcs3400.c - src/temp_sensor.c src/test_mocks.c src/test_rules.c - src/thermistor.c - src/uart_hostcmd.c - src/usb_mux.c - src/usb_pd_host_cmd.c src/utils.c - src/vboot_hash.c - src/watchdog.c + src/stubs.c ) -add_subdirectory(isl923x) -add_subdirectory(led_driver) +if(NOT ZMAKE_PROJECT_NAME MATCHES "^test-drivers.*") + message(FATAL "Invalid project name") +endif() +string(SUBSTRING "${ZMAKE_PROJECT_NAME}" 12 -1 subproject_path) +string(REPLACE "-" "/" subproject_path "${subproject_path}") + +if(subproject_path STREQUAL "") + target_sources(app PRIVATE + src/battery.c + src/bb_retimer.c + src/bc12.c + src/bma2x2.c + src/bmi160.c + src/bmi260.c + src/charge_manager.c + src/chargesplash.c + src/console_cmd/charge_manager.c + src/console_cmd/charge_state.c + src/console_cmd/accelinit.c + src/console_cmd/accelinfo.c + src/console_cmd/accelspoof.c + src/console_cmd/accelrate.c + src/console_cmd/accelrange.c + src/console_cmd/accelread.c + src/console_cmd/accelres.c + src/console_cmd/usb_pd_console.c + src/cros_cbi.c + src/espi.c + src/gpio.c + src/host_cmd/host_event_commands.c + src/host_cmd/motion_sense.c + src/integration/usbc/usb.c + src/integration/usbc/usb_20v_3a_pd_charger.c + src/integration/usbc/usb_5v_3a_pd_sink.c + src/integration/usbc/usb_5v_3a_pd_source.c + src/integration/usbc/usb_alt_mode.c + src/integration/usbc/usb_attach_src_snk.c + src/integration/usbc/usb_pd_ctrl_msg.c + src/integration/usbc/usb_malfunction_sink.c + src/i2c_passthru.c + src/isl923x.c + src/keyboard_scan.c + src/lid_switch.c + src/lis2dw12.c + src/ln9310.c + src/motion_sense/motion_sense.c + src/panic.c + src/power_common.c + src/ppc_sn5s330.c + src/ppc_syv682x.c + src/ps8xxx.c + src/smart.c + src/stm_mems_common.c + src/tcpci.c + src/tcpci_test_common.c + src/tcs3400.c + src/temp_sensor.c + src/thermistor.c + src/uart_hostcmd.c + src/usb_mux.c + src/usb_pd_host_cmd.c + src/vboot_hash.c + src/watchdog.c + ) +else() + add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}${subproject_path}) +endif() set_compiler_property(APPEND PROPERTY coverage -O0) diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py index 69c4239f69..698cf40b2b 100644 --- a/zephyr/zmake/zmake/zmake.py +++ b/zephyr/zmake/zmake/zmake.py @@ -468,6 +468,7 @@ class Zmake: self.module_paths["ec"] / "zephyr" / "include" / "drivers" ), "ZMAKE_INCLUDE_DIR": str(generated_include_dir), + "ZMAKE_PROJECT_NAME": project.config.project_name, }, ) -- cgit v1.2.1 From 5075aa6a310a87bc4395de591f2d6930f54c7a0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:05 -0600 Subject: baseboard/trogdor/power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b91b7923cea3afdbfa00ef778f5c6532e2ce70c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727944 Reviewed-by: Jeremy Bettis --- baseboard/trogdor/power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/trogdor/power.c b/baseboard/trogdor/power.c index b539539c98..a893369ced 100644 --- a/baseboard/trogdor/power.c +++ b/baseboard/trogdor/power.c @@ -35,4 +35,4 @@ void board_chipset_shutdown_complete(void) gpio_set_level(GPIO_EN_PP3300_A, 0); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_chipset_shutdown_complete, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 71f08980c3fa9567f1b189cdc4c2308b3bc0ecbd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:38 -0600 Subject: baseboard/kalista/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I949b6e9632596edf0846599036ebbafed19711e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727911 Reviewed-by: Jeremy Bettis --- baseboard/kalista/led.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/baseboard/kalista/led.c b/baseboard/kalista/led.c index e04eecf5e3..fc4a6ec8da 100644 --- a/baseboard/kalista/led.c +++ b/baseboard/kalista/led.c @@ -15,7 +15,7 @@ #include "timer.h" #include "util.h" -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From 3352ed1d70a051011a3e32c1bba29414f625ae6b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:28 -0600 Subject: zephyr/shim/include/usbc/ppc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9323208414de93df10eae095d27caff7c23d1f0a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730852 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/ppc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/include/usbc/ppc.h b/zephyr/shim/include/usbc/ppc.h index 94aee49f36..9d7dfdd824 100644 --- a/zephyr/shim/include/usbc/ppc.h +++ b/zephyr/shim/include/usbc/ppc.h @@ -24,9 +24,9 @@ enum ppc_chips_alt_id { DT_FOREACH_STATUS_OKAY(RT1739_PPC_COMPAT, PPC_ALT_ENUM) - DT_FOREACH_STATUS_OKAY(SN5S330_COMPAT, PPC_ALT_ENUM) - DT_FOREACH_STATUS_OKAY(SYV682X_COMPAT, PPC_ALT_ENUM) - PPC_CHIP_ALT_COUNT + DT_FOREACH_STATUS_OKAY(SN5S330_COMPAT, PPC_ALT_ENUM) + DT_FOREACH_STATUS_OKAY(SYV682X_COMPAT, PPC_ALT_ENUM) + PPC_CHIP_ALT_COUNT }; extern struct ppc_config_t ppc_chips_alt[]; -- cgit v1.2.1 From 4513c56315ba1de35160f48c7f065aaa8459458f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:45 -0600 Subject: zephyr/test/drivers/src/tcpci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d4b4889c11d2d662639109e2a3761ae9ac5bbd8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730946 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/tcpci.c | 64 +++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 41 deletions(-) diff --git a/zephyr/test/drivers/src/tcpci.c b/zephyr/test/drivers/src/tcpci.c index 167744f3a9..8e7edcf786 100644 --- a/zephyr/test/drivers/src/tcpci.c +++ b/zephyr/test/drivers/src/tcpci.c @@ -138,7 +138,6 @@ ZTEST(tcpci, test_generic_tcpci_alert) test_tcpci_alert(emul, USBC_PORT_C0); } - /** Test TCPCI alert RX message */ ZTEST(tcpci, test_generic_tcpci_alert_rx_message) { @@ -277,24 +276,22 @@ ZTEST(tcpci, test_generic_tcpci_mux_init) /* Make sure that TCPC is not accessed */ i2c_common_emul_set_read_fail_reg(i2c_emul, I2C_COMMON_EMUL_FAIL_ALL_REG); - zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), - NULL); + zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); /* Set as only usb mux without TCPC for rest of the test */ set_usb_mux_not_tcpc(); /* Test fail on power status read */ i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_POWER_STATUS); - zassert_equal(EC_ERROR_INVAL, tcpci_tcpm_mux_init(tcpci_usb_mux), - NULL); + zassert_equal(EC_ERROR_INVAL, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); i2c_common_emul_set_read_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test fail on uninitialised bit set */ tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, TCPC_REG_POWER_STATUS_UNINIT); - zassert_equal(EC_ERROR_TIMEOUT, - tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); + zassert_equal(EC_ERROR_TIMEOUT, tcpci_tcpm_mux_init(tcpci_usb_mux), + NULL); /* Set default power status for rest of the test */ tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, @@ -302,13 +299,13 @@ ZTEST(tcpci, test_generic_tcpci_mux_init) /* Test fail on alert mask write fail */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ALERT_MASK); - zassert_equal(EC_ERROR_UNKNOWN, - tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); + zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux), + NULL); /* Test fail on alert write fail */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ALERT); - zassert_equal(EC_ERROR_UNKNOWN, - tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); + zassert_equal(EC_ERROR_UNKNOWN, tcpci_tcpm_mux_init(tcpci_usb_mux), + NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -317,8 +314,7 @@ ZTEST(tcpci, test_generic_tcpci_mux_init) tcpci_emul_set_reg(emul, TCPC_REG_ALERT_MASK, 0xffff); /* Test success init */ - zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), - NULL); + zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_init(tcpci_usb_mux), NULL); check_tcpci_reg(emul, TCPC_REG_ALERT_MASK, 0); check_tcpci_reg(emul, TCPC_REG_ALERT, 0); } @@ -336,8 +332,7 @@ ZTEST(tcpci, test_generic_tcpci_mux_enter_low_power) /* Make sure that TCPC is not accessed */ i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_FAIL_ALL_REG); - zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), + zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), NULL); /* Set as only usb mux without TCPC for rest of the test */ @@ -346,14 +341,12 @@ ZTEST(tcpci, test_generic_tcpci_mux_enter_low_power) /* Test error on failed command set */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_COMMAND); zassert_equal(EC_ERROR_INVAL, - tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), - NULL); + tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test correct command is issued */ - zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), + zassert_equal(EC_SUCCESS, tcpci_tcpm_mux_enter_low_power(tcpci_usb_mux), NULL); check_tcpci_reg(emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_I2CIDLE); } @@ -373,11 +366,9 @@ static void test_generic_tcpci_mux_set_get(void) /* Test fail on standard output config register read */ i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_CONFIG_STD_OUTPUT); zassert_equal(EC_ERROR_INVAL, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); zassert_equal(EC_ERROR_INVAL, - tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), - NULL); + tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL); i2c_common_emul_set_read_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -385,8 +376,7 @@ static void test_generic_tcpci_mux_set_get(void) i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_CONFIG_STD_OUTPUT); zassert_equal(EC_ERROR_INVAL, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -403,13 +393,11 @@ static void test_generic_tcpci_mux_set_get(void) exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED; mux_state = USB_PD_MUX_NONE; zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val); zassert_false(ack, "Ack from host shouldn't be required"); zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), - NULL); + tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL); zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x", mux_state, mux_state_get); @@ -419,13 +407,11 @@ static void test_generic_tcpci_mux_set_get(void) TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED; mux_state = USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED; zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val); zassert_false(ack, "Ack from host shouldn't be required"); zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), - NULL); + tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL); zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x", mux_state, mux_state_get); @@ -435,13 +421,11 @@ static void test_generic_tcpci_mux_set_get(void) exp_val &= ~TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED; mux_state = USB_PD_MUX_USB_ENABLED; zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val); zassert_false(ack, "Ack from host shouldn't be required"); zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), - NULL); + tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL); zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x", mux_state, mux_state_get); @@ -453,13 +437,11 @@ static void test_generic_tcpci_mux_set_get(void) mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED; zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), - NULL); + tcpci_tcpm_mux_set(tcpci_usb_mux, mux_state, &ack), NULL); check_tcpci_reg(emul, TCPC_REG_CONFIG_STD_OUTPUT, exp_val); zassert_false(ack, "Ack from host shouldn't be required"); zassert_equal(EC_SUCCESS, - tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), - NULL); + tcpci_tcpm_mux_get(tcpci_usb_mux, &mux_state_get), NULL); zassert_equal(mux_state, mux_state_get, "Expected state 0x%x, got 0x%x", mux_state, mux_state_get); } -- cgit v1.2.1 From 6a4ce69682da935cf62078cf7753b5c4c23bfa0e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:55 -0600 Subject: include/power/icelake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f905ac3f279a91510ef18eb8234931ad976e912 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730386 Reviewed-by: Jeremy Bettis --- include/power/icelake.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/power/icelake.h b/include/power/icelake.h index 95460ae80d..25f90dc078 100644 --- a/include/power/icelake.h +++ b/include/power/icelake.h @@ -11,13 +11,13 @@ #include "stdbool.h" /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) -- cgit v1.2.1 From ef736ad3635cb29c0b248e826217f52bb8fec77f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:58 -0600 Subject: board/elemi/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1cc50d6b12815a29129fe47cf0bd1e58da85c022 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728289 Reviewed-by: Jeremy Bettis --- board/elemi/led.c | 53 +++++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 26 deletions(-) diff --git a/board/elemi/led.c b/board/elemi/led.c index d8df9c92a0..fc29c3c67b 100644 --- a/board/elemi/led.c +++ b/board/elemi/led.c @@ -21,10 +21,10 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -#define LED_CYCLE_TIME_MS (2 * 1000) +#define LED_CYCLE_TIME_MS (2 * 1000) #define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS) -#define LED_ON_TIME_MS (1 * 1000) -#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1 * 1000) +#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS) const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, @@ -37,22 +37,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - RIGHT_PORT = 0, - LEFT_PORT -}; +enum led_port { RIGHT_PORT = 0, LEFT_PORT }; static void led_set_color_battery(int port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L : - GPIO_C1_CHARGE_LED_AMBER_L); + GPIO_C1_CHARGE_LED_AMBER_L); white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L : - GPIO_C1_CHARGE_LED_WHITE_L); + GPIO_C1_CHARGE_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -124,10 +121,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -144,14 +141,13 @@ static void led_set_battery(void) * system suspend without charging state. */ if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - + charge_get_state() != PWR_STATE_CHARGE) { suspend_ticks++; - led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ? - LED_WHITE : LED_OFF); - led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF); + led_set_color_battery( + LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF); return; } @@ -165,9 +161,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } @@ -176,17 +175,19 @@ static void led_set_battery(void) led_set_color_battery(LEFT_PORT, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 14e3240cb08cb3e9eb46a4f4e6db82f1cf09993a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:53 -0600 Subject: common/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0f045ff32df50ce5167c13f39eeb2e2382c853f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729589 Reviewed-by: Jeremy Bettis --- common/battery.c | 73 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/common/battery.c b/common/battery.c index 01478d5b52..35b0c500a9 100644 --- a/common/battery.c +++ b/common/battery.c @@ -21,8 +21,8 @@ #include "util.h" #include "watchdog.h" -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) #define CUTOFFPRINTS(info) CPRINTS("%s %s", "Battery cut off", info) /* See config.h for details */ @@ -77,9 +77,14 @@ static int check_print_error(int rv) static void print_battery_status(void) { - static const char * const st[] = {"EMPTY", "FULL", "DCHG", "INIT",}; - static const char * const al[] = {"RT", "RC", "--", "TD", - "OT", "--", "TC", "OC"}; + static const char *const st[] = { + "EMPTY", + "FULL", + "DCHG", + "INIT", + }; + static const char *const al[] = { "RT", "RC", "--", "TD", + "OT", "--", "TC", "OC" }; int value, i; @@ -92,12 +97,12 @@ static void print_battery_status(void) /* bits 4-7 are status */ for (i = 0; i < 4; i++) - if (value & (1 << (i+4))) + if (value & (1 << (i + 4))) ccprintf(" %s", st[i]); /* bits 15-8 are alarms */ for (i = 0; i < 8; i++) - if (value & (1 << (i+8))) + if (value & (1 << (i + 8))) ccprintf(" %s", al[i]); ccprintf("\n"); @@ -138,10 +143,8 @@ static void print_battery_params(void) ccprintf("%08x\n", batt->flags); print_item_name("Temp:"); - ccprintf("0x%04x = %.1d K (%.1d C)\n", - batt->temperature, - batt->temperature, - batt->temperature - 2731); + ccprintf("0x%04x = %.1d K (%.1d C)\n", batt->temperature, + batt->temperature, batt->temperature - 2731); print_item_name("V:"); ccprintf("0x%04x = %d mV\n", batt->voltage, batt->voltage); @@ -167,7 +170,7 @@ static void print_battery_params(void) batt->flags & BATT_FLAG_WANT_CHARGE ? "" : "Not "); print_item_name("Charge:"); - ccprintf("%d %%\n", batt->state_of_charge); + ccprintf("%d %%\n", batt->state_of_charge); if (IS_ENABLED(CONFIG_CHARGER)) { int value; @@ -214,10 +217,10 @@ static void print_battery_info(void) print_item_name("Time-full:"); if (check_print_error(battery_time_to_full(&value))) { if (value == 65535) { - hour = 0; + hour = 0; minute = 0; } else { - hour = value / 60; + hour = value / 60; minute = value % 60; } ccprintf("%dh:%d\n", hour, minute); @@ -226,10 +229,10 @@ static void print_battery_info(void) print_item_name(" Empty:"); if (check_print_error(battery_time_to_empty(&value))) { if (value == 65535) { - hour = 0; + hour = 0; minute = 0; } else { - hour = value / 60; + hour = value / 60; minute = value % 60; } ccprintf("%dh:%d\n", hour, minute); @@ -289,8 +292,7 @@ static int command_battery(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(battery, command_battery, - " ", +DECLARE_CONSOLE_COMMAND(battery, command_battery, " ", "Print battery info"); #ifdef CONFIG_BATTERY_CUT_OFF @@ -349,7 +351,7 @@ static enum ec_status battery_command_cutoff(struct host_cmd_handler_args *args) return rv; } DECLARE_HOST_COMMAND(EC_CMD_BATTERY_CUT_OFF, battery_command_cutoff, - EC_VER_MASK(0) | EC_VER_MASK(1)); + EC_VER_MASK(0) | EC_VER_MASK(1)); static void check_pending_cutoff(void) { @@ -384,15 +386,14 @@ static int command_cutoff(int argc, char **argv) return EC_ERROR_UNKNOWN; } -DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff, - "[at-shutdown]", - "Cut off the battery output"); +DECLARE_CONSOLE_COMMAND(cutoff, command_cutoff, "[at-shutdown]", + "Cut off the battery output"); #else int battery_is_cut_off(void) { - return 0; /* Always return NOT cut off */ + return 0; /* Always return NOT cut off */ } -#endif /* CONFIG_BATTERY_CUT_OFF */ +#endif /* CONFIG_BATTERY_CUT_OFF */ #ifdef CONFIG_BATTERY_VENDOR_PARAM __overridable int battery_get_vendor_param(uint32_t param, uint32_t *value) @@ -488,11 +489,9 @@ host_command_battery_vendor_param(struct host_cmd_handler_args *args) return rv; } DECLARE_HOST_COMMAND(EC_CMD_BATTERY_VENDOR_PARAM, - host_command_battery_vendor_param, - EC_VER_MASK(0)); + host_command_battery_vendor_param, EC_VER_MASK(0)); #endif /* CONFIG_BATTERY_VENDOR_PARAM */ - void battery_compensate_params(struct batt_params *batt) { int numer, denom; @@ -500,7 +499,7 @@ void battery_compensate_params(struct batt_params *batt) int full = batt->full_capacity; if ((batt->flags & BATT_FLAG_BAD_FULL_CAPACITY) || - (batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) + (batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY)) return; if (*remain <= 0 || full <= 0) @@ -589,20 +588,21 @@ __overridable enum battery_disconnect_state battery_get_disconnect_state(void) #ifdef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV #if CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV < 5000 || \ - CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV - #error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV" + CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV >= PD_MAX_VOLTAGE_MV +#error "Voltage limit must be between 5000 and PD_MAX_VOLTAGE_MV" #endif #if !((defined(CONFIG_USB_PD_TCPMV1) && defined(CONFIG_USB_PD_DUAL_ROLE)) || \ - (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM))) - #error "Voltage reducing requires TCPM with Policy Engine" + (defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM))) +#error "Voltage reducing requires TCPM with Policy Engine" #endif /* * Returns true if input voltage should be reduced (chipset is in S5/G3) and * battery is full, otherwise returns false */ -static bool board_wants_reduced_input_voltage(void) { +static bool board_wants_reduced_input_voltage(void) +{ struct batt_params batt; /* Chipset not in S5/G3, so we don't want to reduce voltage */ @@ -638,7 +638,7 @@ static void reduce_input_voltage_when_full(void) CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) { saved_input_voltage = max_pd_voltage_mv; max_pd_voltage_mv = - CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV; + CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV; } } else if (saved_input_voltage != -1) { /* @@ -656,8 +656,7 @@ static void reduce_input_voltage_when_full(void) if (pd_get_max_voltage() != max_pd_voltage_mv) pd_set_external_voltage_limit(port, max_pd_voltage_mv); } -DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_STARTUP, reduce_input_voltage_when_full, @@ -677,7 +676,7 @@ void battery_validate_params(struct batt_params *batt) */ if (batt->temperature > CELSIUS_TO_DECI_KELVIN(5660)) { CPRINTS("ignoring ridiculous batt.temp of %dC", - DECI_KELVIN_TO_CELSIUS(batt->temperature)); + DECI_KELVIN_TO_CELSIUS(batt->temperature)); batt->flags |= BATT_FLAG_BAD_TEMPERATURE; } -- cgit v1.2.1 From aa41ed5e250d1bec206158c3ea0ea2aa67562f26 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:56 -0600 Subject: board/zinger/runtime.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I365bfb3ae97da6c8adabb312107dccdc9fa51875 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729142 Reviewed-by: Jeremy Bettis --- board/zinger/runtime.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/board/zinger/runtime.c b/board/zinger/runtime.c index 900c7b8c2f..b59dd81225 100644 --- a/board/zinger/runtime.c +++ b/board/zinger/runtime.c @@ -106,7 +106,7 @@ static void zinger_config_hispeed_clock(void) STM32_RCC_CR |= BIT(24); /* Wait for PLL to be ready */ while (!(STM32_RCC_CR & BIT(25))) - ; + ; /* switch SYSCLK to PLL */ STM32_RCC_CFGR = 0x00288002; @@ -135,7 +135,7 @@ void runtime_init(void) * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. if we set the alarm * in the past, it will never wake up and cause a watchdog. */ -#define STOP_MODE_LATENCY 300 /* us */ +#define STOP_MODE_LATENCY 300 /* us */ #define SET_RTC_MATCH_DELAY 200 /* us */ #define MAX_LATENCY (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY) @@ -161,10 +161,10 @@ uint32_t task_wait_event(int timeout_us) while (1) { /* set timeout on timer */ if (timeout_us < 0) { - asm volatile ("wfi"); + asm volatile("wfi"); } else if (timeout_us <= MAX_LATENCY || - t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY || - !DEEP_SLEEP_ALLOWED) { + t1.le.lo - timeout_us > t1.le.lo + MAX_LATENCY || + !DEEP_SLEEP_ALLOWED) { STM32_TIM32_CCR1(2) = STM32_TIM32_CNT(2) + timeout_us; STM32_TIM_DIER(2) = 3; /* match interrupt and UIE */ @@ -177,8 +177,8 @@ uint32_t task_wait_event(int timeout_us) /* set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY, - &rtc0, 0); + set_rtc_alarm(0, timeout_us - STOP_MODE_LATENCY, &rtc0, + 0); asm volatile("wfi"); @@ -233,8 +233,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us) return evt & event_mask; } -noreturn -void __keep cpu_reset(void) +noreturn void __keep cpu_reset(void) { /* Disable interrupts */ interrupt_disable(); @@ -267,7 +266,8 @@ void exception_panic(void) "bl debug_printf\n" #endif "bl cpu_reset\n" - : : "r"("PANIC PC=%08x LR=%08x\n\n")); + : + : "r"("PANIC PC=%08x LR=%08x\n\n")); } void panic_reboot(void) @@ -286,7 +286,9 @@ enum ec_image system_get_image_copy(void) /* --- stubs --- */ void __hw_timer_enable_clock(int n, int enable) -{ /* Done in hardware init */ } +{ /* Done in hardware init */ +} void usleep(unsigned us) -{ /* Used only as a workaround */ } +{ /* Used only as a workaround */ +} -- cgit v1.2.1 From e74951d85cb86b9baef6e6c10500ba0f08e5b02c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:35 -0600 Subject: include/driver/retimer/bb_retimer.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifdf62770a7960d25b08941704789c33dd4d78df2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730251 Reviewed-by: Jeremy Bettis --- include/driver/retimer/bb_retimer.h | 66 ++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/include/driver/retimer/bb_retimer.h b/include/driver/retimer/bb_retimer.h index 6a311bd2ca..8ee5aec518 100644 --- a/include/driver/retimer/bb_retimer.h +++ b/include/driver/retimer/bb_retimer.h @@ -12,44 +12,44 @@ #include "driver/retimer/bb_retimer_public.h" /* Burnside Bridge I2C Configuration Space */ -#define BB_RETIMER_REG_VENDOR_ID 0 -#define BB_RETIMER_VENDOR_ID_1 0x8086 -#define BB_RETIMER_VENDOR_ID_2 0x8087 +#define BB_RETIMER_REG_VENDOR_ID 0 +#define BB_RETIMER_VENDOR_ID_1 0x8086 +#define BB_RETIMER_VENDOR_ID_2 0x8087 -#define BB_RETIMER_REG_DEVICE_ID 1 -#ifdef CONFIG_USBC_RETIMER_INTEL_HB +#define BB_RETIMER_REG_DEVICE_ID 1 +#ifdef CONFIG_USBC_RETIMER_INTEL_HB /* HB has no Device ID field instead it is combined with Vendor ID */ -#define BB_RETIMER_DEVICE_ID 0x0D9C8087 +#define BB_RETIMER_DEVICE_ID 0x0D9C8087 #else -#define BB_RETIMER_DEVICE_ID 0x15EE +#define BB_RETIMER_DEVICE_ID 0x15EE #endif /* Connection State Register Attributes */ -#define BB_RETIMER_REG_CONNECTION_STATE 4 -#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) -#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) -#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) -#define BB_RETIMER_USB_2_CONNECTION BIT(4) -#define BB_RETIMER_USB_3_CONNECTION BIT(5) -#define BB_RETIMER_USB_3_SPEED BIT(6) -#define BB_RETIMER_USB_DATA_ROLE BIT(7) -#define BB_RETIMER_DP_CONNECTION BIT(8) -#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) -#define BB_RETIMER_IRQ_HPD BIT(14) -#define BB_RETIMER_HPD_LVL BIT(15) -#define BB_RETIMER_TBT_CONNECTION BIT(16) -#define BB_RETIMER_TBT_TYPE BIT(17) -#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) -#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) -#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) -#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) -#define BB_RETIMER_USB4_ENABLED BIT(23) -#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x) & 0x7) << 25) -#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x) & 0x3) << 28) - -#define BB_RETIMER_REG_TBT_CONTROL 5 -#define BB_RETIMER_REG_EXT_CONNECTION_MODE 6 - -#define BB_RETIMER_REG_COUNT 7 +#define BB_RETIMER_REG_CONNECTION_STATE 4 +#define BB_RETIMER_DATA_CONNECTION_PRESENT BIT(0) +#define BB_RETIMER_CONNECTION_ORIENTATION BIT(1) +#define BB_RETIMER_RE_TIMER_DRIVER BIT(2) +#define BB_RETIMER_USB_2_CONNECTION BIT(4) +#define BB_RETIMER_USB_3_CONNECTION BIT(5) +#define BB_RETIMER_USB_3_SPEED BIT(6) +#define BB_RETIMER_USB_DATA_ROLE BIT(7) +#define BB_RETIMER_DP_CONNECTION BIT(8) +#define BB_RETIMER_DP_PIN_ASSIGNMENT BIT(10) +#define BB_RETIMER_IRQ_HPD BIT(14) +#define BB_RETIMER_HPD_LVL BIT(15) +#define BB_RETIMER_TBT_CONNECTION BIT(16) +#define BB_RETIMER_TBT_TYPE BIT(17) +#define BB_RETIMER_TBT_CABLE_TYPE BIT(18) +#define BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE BIT(19) +#define BB_RETIMER_TBT_ACTIVE_LINK_TRAINING BIT(20) +#define BB_RETIMER_ACTIVE_PASSIVE BIT(22) +#define BB_RETIMER_USB4_ENABLED BIT(23) +#define BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT(x) (((x)&0x7) << 25) +#define BB_RETIMER_TBT_CABLE_GENERATION(x) (((x)&0x3) << 28) + +#define BB_RETIMER_REG_TBT_CONTROL 5 +#define BB_RETIMER_REG_EXT_CONNECTION_MODE 6 + +#define BB_RETIMER_REG_COUNT 7 #endif /* __CROS_EC_BB_RETIMER_H */ -- cgit v1.2.1 From eb7f20994600c388bcacc59ea9d3cc6858cd186d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:50 -0600 Subject: core/cortex-m/panic-internal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iffcf85741854be63a67acc063cc030cdeb30a298 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729824 Reviewed-by: Jeremy Bettis --- core/cortex-m/panic-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m/panic-internal.h b/core/cortex-m/panic-internal.h index 1a58afa8a2..8b81502a7f 100644 --- a/core/cortex-m/panic-internal.h +++ b/core/cortex-m/panic-internal.h @@ -8,4 +8,4 @@ void exception_panic(void) __attribute__((naked)); -#endif /* __CROS_EC_PANIC_INTERNAL_H */ +#endif /* __CROS_EC_PANIC_INTERNAL_H */ -- cgit v1.2.1 From 817946730e7f9bf431825fc9d10dbe0033bf5d53 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:57 -0600 Subject: board/moli/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a05599286261834882a5ee554bfcaa8957afee9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728689 Reviewed-by: Jeremy Bettis --- board/moli/board.h | 118 ++++++++++++++++++++++++----------------------------- 1 file changed, 54 insertions(+), 64 deletions(-) diff --git a/board/moli/board.h b/board/moli/board.h index 50744db067..f1821ca758 100644 --- a/board/moli/board.h +++ b/board/moli/board.h @@ -21,11 +21,11 @@ /* HDMI CEC */ #define CONFIG_CEC #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT -#define CEC_GPIO_IN GPIO_HDMI_CEC_IN +#define CEC_GPIO_IN GPIO_HDMI_CEC_IN #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP /* USB Type A Features */ -#define USB_PORT_COUNT 4 +#define USB_PORT_COUNT 4 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -33,7 +33,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_PPC #define CONFIG_USBC_RETIMER_INTEL_BB @@ -43,18 +43,18 @@ #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* The design should support up to 100W. */ /* TODO(b/197702356): Set the max PD to 60W now and change it * to 100W after we verify it. */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -62,53 +62,53 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_ODL /* I2C Bus Configuration */ -#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_QI NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_QI NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -129,15 +129,15 @@ #define CONFIG_ADC /* Fan */ -#define CONFIG_FANS FAN_CH_COUNT -#define RPM_DEVIATION 1 +#define CONFIG_FANS FAN_CH_COUNT +#define RPM_DEVIATION 1 /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -153,7 +153,7 @@ enum adc_channel { ADC_TEMP_SENSOR_2_CPU_VR, ADC_TEMP_SENSOR_4_DIMM, ADC_VBUS, - ADC_PPVAR_IMON, /* ADC3 */ + ADC_PPVAR_IMON, /* ADC3 */ ADC_CH_COUNT }; @@ -164,28 +164,18 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; enum pwm_channel { - PWM_CH_LED_AMBER, /* PWM0 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED_BLUE, /* PWM2 */ + PWM_CH_LED_AMBER, /* PWM0 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED_BLUE, /* PWM2 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; /* * firmware config fields @@ -193,8 +183,8 @@ enum mft_channel { /* * Barrel-jack power (2 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 1 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 1 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) extern void adp_connect_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 3174adca77d34aa08364a0341ce9d3f972f84868 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:48 -0600 Subject: board/cret/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If08d2d9fb129fe7c85f87f5e2e098b485f0b5395 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728209 Reviewed-by: Jeremy Bettis --- board/cret/led.c | 47 ++++++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/board/cret/led.c b/board/cret/led.c index edfb4ac761..1a94e473c1 100644 --- a/board/cret/led.c +++ b/board/cret/led.c @@ -8,8 +8,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 10; @@ -17,23 +17,32 @@ __override const int led_charge_lvl_2 = 100; /* Cret: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 7072029b912e667b2fece0458d56e6f585a914fb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:42 -0600 Subject: chip/stm32/usb_hid.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide91394c7e61ae40c1c8953500d43c1ec81307c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729575 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_hid.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/chip/stm32/usb_hid.c b/chip/stm32/usb_hid.c index b8336fa0a0..2c52a7d61f 100644 --- a/chip/stm32/usb_hid.c +++ b/chip/stm32/usb_hid.c @@ -20,7 +20,7 @@ #include "usb_hid_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) void hid_tx(int ep) { @@ -41,17 +41,15 @@ void hid_reset(int ep, usb_uint *hid_ep_tx_buf, int tx_len, for (i = 0; i < DIV_ROUND_UP(tx_len, 2); i++) hid_ep_tx_buf[i] = 0; - ep_reg = (ep << 0) /* Endpoint Address */ | - EP_TX_VALID | - (3 << 9) /* interrupt EP */ | - EP_RX_DISAB; + ep_reg = (ep << 0) /* Endpoint Address */ | EP_TX_VALID | + (3 << 9) /* interrupt EP */ | EP_RX_DISAB; /* Enable RX for output reports */ if (hid_ep_rx_buf && rx_len > 0) { btable_ep[ep].rx_addr = usb_sram_addr(hid_ep_rx_buf); btable_ep[ep].rx_count = ((rx_len + 1) / 2) << 10; - ep_reg |= EP_RX_VALID; /* RX Valid */ + ep_reg |= EP_RX_VALID; /* RX Valid */ } STM32_USB_EP(ep) = ep_reg; @@ -73,14 +71,13 @@ static const uint8_t *report_ptr; * * @return 0 if entire report is sent, 1 if there are remaining data. */ -static int send_report(usb_uint *ep0_buf_tx, - const uint8_t *report, +static int send_report(usb_uint *ep0_buf_tx, const uint8_t *report, int report_size) { int packet_size = MIN(report_size, USB_MAX_PACKET_SIZE); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report, packet_size); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report, + packet_size); btable_ep[0].tx_count = packet_size; /* report_left != 0 if report doesn't fit in 1 packet. */ report_left = report_size - packet_size; @@ -108,8 +105,8 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, if (report_left == 0) return -1; report_size = MIN(USB_MAX_PACKET_SIZE, report_left); - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - report_ptr, report_size); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), report_ptr, + report_size); btable_ep[0].tx_count = report_size; report_left -= report_size; report_ptr += report_size; @@ -117,7 +114,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, report_left ? 0 : EP_STATUS_OUT); return report_left ? 1 : 0; } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_RECIP_INTERFACE | - (USB_REQ_GET_DESCRIPTOR << 8))) { + (USB_REQ_GET_DESCRIPTOR << 8))) { if (ep0_buf_rx[1] == (USB_HID_DT_REPORT << 8)) { /* Setup : HID specific : Get Report descriptor */ return send_report(ep0_buf_tx, report_desc, @@ -130,10 +127,9 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, EP_STATUS_OUT); return 0; } - } else if (ep0_buf_rx[0] == (USB_DIR_IN | - USB_RECIP_INTERFACE | - USB_TYPE_CLASS | - (USB_HID_REQ_GET_REPORT << 8))) { + } else if (ep0_buf_rx[0] == + (USB_DIR_IN | USB_RECIP_INTERFACE | USB_TYPE_CLASS | + (USB_HID_REQ_GET_REPORT << 8))) { const uint8_t report_type = (ep0_buf_rx[1] >> 8) & 0xFF; const uint8_t report_id = ep0_buf_rx[1] & 0xFF; int retval; @@ -142,9 +138,7 @@ int hid_iface_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx, if (!config->get_report) /* not supported */ return -1; - retval = config->get_report(report_id, - report_type, - &report_ptr, + retval = config->get_report(report_id, report_type, &report_ptr, &report_left); if (retval) return retval; -- cgit v1.2.1 From 4b77138d4f6a1fdc993739c8ee4430f346887eae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:50 -0600 Subject: baseboard/octopus/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iebed1b9a71da8962766906bb3dc46f115bd94e4f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727938 Reviewed-by: Jeremy Bettis --- baseboard/octopus/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/octopus/usb_pd_policy.c b/baseboard/octopus/usb_pd_policy.c index 3dd6ad29f5..3c02c89d4d 100644 --- a/baseboard/octopus/usb_pd_policy.c +++ b/baseboard/octopus/usb_pd_policy.c @@ -17,8 +17,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 9a1d9ca78fd9abaf7e6d4ed47483341ac65a78f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:05 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5690a5f6abff1062855c62c53c8d23ce0fa3e4bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730956 Reviewed-by: Jeremy Bettis --- .../drivers/src/integration/usbc/usb_20v_3a_pd_charger.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c b/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c index 5a7c0c96f2..afd6e5aebc 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_20v_3a_pd_charger.c @@ -26,13 +26,12 @@ static inline void connect_charger_to_port(struct usb_attach_20v_3a_pd_charger_fixture *fixture) { set_ac_enabled(true); - zassume_ok(tcpci_partner_connect_to_tcpci( - &fixture->charger_20v, fixture->tcpci_emul), + zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->charger_20v, + fixture->tcpci_emul), NULL); - isl923x_emul_set_adc_vbus( - fixture->charger_emul, - PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1])); + isl923x_emul_set_adc_vbus(fixture->charger_emul, + PDO_FIXED_GET_VOLT(fixture->src_ext.pdo[1])); /* Wait for PD negotiation and current ramp. * TODO(b/213906889): Check message timing and contents. @@ -61,9 +60,8 @@ static void *usb_attach_20v_3a_pd_charger_setup(void) /* Initialized the charger to supply 20V and 3A */ tcpci_partner_init(&test_fixture.charger_20v, PD_REV20); - test_fixture.charger_20v.extensions = - tcpci_src_emul_init(&test_fixture.src_ext, - &test_fixture.charger_20v, NULL); + test_fixture.charger_20v.extensions = tcpci_src_emul_init( + &test_fixture.src_ext, &test_fixture.charger_20v, NULL); test_fixture.src_ext.pdo[1] = PDO_FIXED(20000, 3000, PDO_FIXED_UNCONSTRAINED); -- cgit v1.2.1 From 20bcca715468f123f51e5e506695a3b1de6dc3a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:10 -0600 Subject: driver/led/is31fl3743b.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9b64fa2eec7511548600e7f1a8627409c406b214 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729996 Reviewed-by: Jeremy Bettis --- driver/led/is31fl3743b.c | 52 ++++++++++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/driver/led/is31fl3743b.c b/driver/led/is31fl3743b.c index a07b2f63f8..eed9c80acc 100644 --- a/driver/led/is31fl3743b.c +++ b/driver/led/is31fl3743b.c @@ -17,30 +17,30 @@ #define SPI(id) (&(spi_devices[id])) -#define IS31FL3743B_ROW_SIZE 6 -#define IS31FL3743B_COL_SIZE 11 -#define IS31FL3743B_GRID_SIZE (IS31FL3743B_COL_SIZE * IS31FL3743B_ROW_SIZE) -#define IS31FL3743B_BUF_SIZE (SIZE_OF_RGB * IS31FL3743B_GRID_SIZE) - -#define IS31FL3743B_CMD_ID 0b101 -#define IS31FL3743B_PAGE_PWM 0 -#define IS31FL3743B_PAGE_SCALE 1 -#define IS31FL3743B_PAGE_FUNC 2 - -#define IS31FL3743B_REG_CONFIG 0x00 -#define IS31FL3743B_REG_GCC 0x01 -#define IS31FL3743B_REG_PD_PU 0x02 -#define IS31FL3743B_REG_SPREAD_SPECTRUM 0x25 -#define IS31FL3743B_REG_RSTN 0x2f - -#define IS31FL3743B_CFG_SWS_1_11 0b0000 +#define IS31FL3743B_ROW_SIZE 6 +#define IS31FL3743B_COL_SIZE 11 +#define IS31FL3743B_GRID_SIZE (IS31FL3743B_COL_SIZE * IS31FL3743B_ROW_SIZE) +#define IS31FL3743B_BUF_SIZE (SIZE_OF_RGB * IS31FL3743B_GRID_SIZE) + +#define IS31FL3743B_CMD_ID 0b101 +#define IS31FL3743B_PAGE_PWM 0 +#define IS31FL3743B_PAGE_SCALE 1 +#define IS31FL3743B_PAGE_FUNC 2 + +#define IS31FL3743B_REG_CONFIG 0x00 +#define IS31FL3743B_REG_GCC 0x01 +#define IS31FL3743B_REG_PD_PU 0x02 +#define IS31FL3743B_REG_SPREAD_SPECTRUM 0x25 +#define IS31FL3743B_REG_RSTN 0x2f + +#define IS31FL3743B_CFG_SWS_1_11 0b0000 #define IS31FL3743B_CONFIG(sws, osde, ssd) \ ((sws) << 4 | BIT(3) | (osde) << 1 | (ssd) << 0) struct is31fl3743b_cmd { - uint8_t page: 4; - uint8_t id: 3; - uint8_t read: 1; + uint8_t page : 4; + uint8_t id : 3; + uint8_t read : 1; } __packed; struct is31fl3743b_msg { @@ -49,8 +49,8 @@ struct is31fl3743b_msg { uint8_t payload[]; } __packed; -__maybe_unused -static int is31fl3743b_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value) +__maybe_unused static int is31fl3743b_read(struct rgbkbd *ctx, uint8_t addr, + uint8_t *value) { uint8_t buf[8]; struct is31fl3743b_msg *msg = (void *)buf; @@ -81,8 +81,8 @@ static int is31fl3743b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) static int is31fl3743b_enable(struct rgbkbd *ctx, bool enable) { - uint8_t u8 = IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0, - enable ? 1 : 0); + uint8_t u8 = + IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0, enable ? 1 : 0); CPRINTS("Setting config register to 0b%pb", BINARY_VALUE(u8, 8)); return is31fl3743b_write(ctx, IS31FL3743B_REG_CONFIG, u8); } @@ -104,7 +104,7 @@ static int is31fl3743b_set_color(struct rgbkbd *ctx, uint8_t offset, return EC_ERROR_OVERFLOW; } - msg->addr = frame_offset + 1; /* Register addr base is 1. */ + msg->addr = frame_offset + 1; /* Register addr base is 1. */ for (i = 0; i < len; i++) { msg->payload[i * SIZE_OF_RGB + 0] = color[i].r; msg->payload[i * SIZE_OF_RGB + 1] = color[i].g; @@ -131,7 +131,7 @@ static int is31fl3743b_set_scale(struct rgbkbd *ctx, uint8_t offset, return EC_ERROR_OVERFLOW; } - msg->addr = frame_offset + 1; /* Address base is 1. */ + msg->addr = frame_offset + 1; /* Address base is 1. */ for (i = 0; i < len; i++) { msg->payload[i * SIZE_OF_RGB + 0] = scale.r; msg->payload[i * SIZE_OF_RGB + 1] = scale.g; -- cgit v1.2.1 From 0d97ededdb1be73cf3b90e04739742405f61bfc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:20 -0600 Subject: board/redrix/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2cff12a4ad91bec3aa83620365f91ef76f363e24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728863 Reviewed-by: Jeremy Bettis --- board/redrix/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/redrix/usbc_config.h b/board/redrix/usbc_config.h index dcaa52d7a9..0cb266046b 100644 --- a/board/redrix/usbc_config.h +++ b/board/redrix/usbc_config.h @@ -8,12 +8,8 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; #endif /* __CROS_EC_USBC_CONFIG_H */ -- cgit v1.2.1 From 0e168c6bdfc448f22a0b2543049f9a740a7922b4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:56 -0600 Subject: driver/ioexpander/tca64xxa.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70c6c2374bdf92de26ab6838a90604e827418ac1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730011 Reviewed-by: Jeremy Bettis --- driver/ioexpander/tca64xxa.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/driver/ioexpander/tca64xxa.h b/driver/ioexpander/tca64xxa.h index 2d2e6e36bc..c736c5bc2d 100644 --- a/driver/ioexpander/tca64xxa.h +++ b/driver/ioexpander/tca64xxa.h @@ -11,17 +11,17 @@ /* io-expander driver specific flag bit for tca6424a */ #define IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A IOEX_FLAGS_CUSTOM_BIT(25) -#define TCA64XXA_FLAG_VER_MASK GENMASK(2, 1) -#define TCA64XXA_FLAG_VER_OFFSET 0 +#define TCA64XXA_FLAG_VER_MASK GENMASK(2, 1) +#define TCA64XXA_FLAG_VER_OFFSET 0 -#define TCA64XXA_REG_INPUT 0 -#define TCA64XXA_REG_OUTPUT 1 -#define TCA64XXA_REG_POLARITY_INV 2 -#define TCA64XXA_REG_CONF 3 +#define TCA64XXA_REG_INPUT 0 +#define TCA64XXA_REG_OUTPUT 1 +#define TCA64XXA_REG_POLARITY_INV 2 +#define TCA64XXA_REG_CONF 3 -#define TCA64XXA_DEFAULT_OUTPUT 0xFF -#define TCA64XXA_DEFAULT_POLARITY_INV 0x00 -#define TCA64XXA_DEFAULT_CONF 0xFF +#define TCA64XXA_DEFAULT_OUTPUT 0xFF +#define TCA64XXA_DEFAULT_POLARITY_INV 0x00 +#define TCA64XXA_DEFAULT_CONF 0xFF extern const struct ioexpander_drv tca64xxa_ioexpander_drv; -- cgit v1.2.1 From 1fe8ec5250b34951f8bd4513d40132bbd925bedc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:43 -0600 Subject: core/riscv-rv32i/cpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e48948bbffe9974f1977f0990049ec3e5ba265d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729868 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/riscv-rv32i/cpu.c b/core/riscv-rv32i/cpu.c index fd18896846..a0d7778cf4 100644 --- a/core/riscv-rv32i/cpu.c +++ b/core/riscv-rv32i/cpu.c @@ -10,5 +10,5 @@ void cpu_init(void) { /* bit3: Global interrupt enable (M-mode) */ - asm volatile ("csrsi mstatus, 0x8"); + asm volatile("csrsi mstatus, 0x8"); } -- cgit v1.2.1 From 7a7dc6f8ab9ef6db4f027c2e4facdb82cd68885b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:48 -0600 Subject: zephyr/include/emul/emul_tcs3400.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I06646d67968a46af7bf9faf8c4fe2fafd761da5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730724 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_tcs3400.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/include/emul/emul_tcs3400.h b/zephyr/include/emul/emul_tcs3400.h index a026f2624a..e0b2e44c73 100644 --- a/zephyr/include/emul/emul_tcs3400.h +++ b/zephyr/include/emul/emul_tcs3400.h @@ -43,19 +43,19 @@ * light, value obtainded with 128 cycles will be two times smaller than value * obtained with 256 cycles. */ -#define TCS_EMUL_MAX_CYCLES 256 +#define TCS_EMUL_MAX_CYCLES 256 /** * Maximum gain supported by TCS3400. Value read from sensor is multiplied by * gain selected in CONTROL register. */ -#define TCS_EMUL_MAX_GAIN 64 +#define TCS_EMUL_MAX_GAIN 64 /** * Emulator units are value returned with gain x64 and 256 integration cycles. * Max value is 1024 returned when gain is x1 and 1 integration cycle. Max value * represented in emulator units is 1024 * 64 * 256 */ -#define TCS_EMUL_MAX_VALUE (1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES) +#define TCS_EMUL_MAX_VALUE (1024 * TCS_EMUL_MAX_GAIN * TCS_EMUL_MAX_CYCLES) /** Axis argument used in @ref tcs_emul_set_val @ref tcs_emul_get_val */ enum tcs_emul_axis { @@ -70,9 +70,9 @@ enum tcs_emul_axis { * Emulator saves only those registers in memory. IR select is stored sparately * and other registers are write only. */ -#define TCS_EMUL_FIRST_REG TCS_I2C_ENABLE -#define TCS_EMUL_LAST_REG TCS_I2C_BDATAH -#define TCS_EMUL_REG_COUNT (TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1) +#define TCS_EMUL_FIRST_REG TCS_I2C_ENABLE +#define TCS_EMUL_LAST_REG TCS_I2C_BDATAH +#define TCS_EMUL_REG_COUNT (TCS_EMUL_LAST_REG - TCS_EMUL_FIRST_REG + 1) /** * @brief Get pointer to TCS3400 emulator using device tree order number. -- cgit v1.2.1 From bc95860778f36ea3b7c666d93f0dc7ff0a8fa8ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:48 -0600 Subject: core/riscv-rv32i/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32625e8ccfe7230010aa2462b6586a064a5c62ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729870 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/include/fpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/riscv-rv32i/include/fpu.h b/core/riscv-rv32i/include/fpu.h index 25d83f228f..6ead0a75a6 100644 --- a/core/riscv-rv32i/include/fpu.h +++ b/core/riscv-rv32i/include/fpu.h @@ -10,4 +10,4 @@ float sqrtf(float x); -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ -- cgit v1.2.1 From 790da8dfc77206760e07af51ebe8c4bc6d371212 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:43 -0600 Subject: board/mrbland/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd505a01f99966ece12aebfd2dc304d7ad79035a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728706 Reviewed-by: Jeremy Bettis --- board/mrbland/board.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/mrbland/board.h b/board/mrbland/board.h index bac5bf0ee1..8b40f63a11 100644 --- a/board/mrbland/board.h +++ b/board/mrbland/board.h @@ -13,13 +13,13 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Switchcap */ #define CONFIG_LN9310 /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -40,7 +40,7 @@ /* I2C */ #undef I2C_PORT_TCPC0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT2_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT2_0 /* Lid accel/gyro */ #define CONFIG_ACCELGYRO_BMI160 @@ -86,10 +86,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From fa96706405179e8ee4215261323b904d2fa895a2 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Mon, 20 Jun 2022 13:28:37 +1000 Subject: sm5803: ensure clocks are not in LPM when enabling If the charger's internal clocks are running at their reduced frequency when switching is enabled, it is possible for its internal control loops to respond slower than is intended and cause incorrect behavior or possibly even damage to the charger. This change ensures that the clocks are running at full speed before enabling either sink or source mode on the charger, providing strong runtime assurance that the charger should not be damaged. BUG=b:230712704 TEST=Bus-powered devices continue to work normally when connected to Nereid, and the battery can be charged. BRANCH=none Signed-off-by: Peter Marheine Change-Id: I656605921648b72c1da7394012dc7a9a32397895 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711514 Reviewed-by: Andrew McRae --- driver/charger/sm5803.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c index 131c611842..e65bb67e75 100644 --- a/driver/charger/sm5803.c +++ b/driver/charger/sm5803.c @@ -142,6 +142,41 @@ static inline enum ec_error_list test_update8(int chgnum, const int offset, SM5803_ADDR_TEST_FLAGS, offset, mask, action); } +/* + * Ensure the charger clocks are at normal operating speed, setting them to + * that speed if not already. + * + * The SM5803 runs multiple digital control loops that are important to correct + * operation. The CLOCK_SEL_LOW register reduced their speed by about 10x, which + * is dangerous when either sinking or sourcing is to be enabled because the + * control loops will respond much more slowly. Leaving clocks at low speed can + * cause incorrect operation or even hardware damage. + * + * This function is used by the functions that enable sinking or sourcing to + * ensure the control loops are running at full speed before enabling switching + * on the charger. + */ +static int sm5803_set_full_clock_speed(int chgnum) +{ + int rv, val; + + rv = main_read8(chgnum, SM5803_REG_CLOCK_SEL, &val); + if (rv) { + goto out; + } + if (val & SM5803_CLOCK_SEL_LOW) { + rv = main_write8(chgnum, SM5803_REG_CLOCK_SEL, + val & ~SM5803_CLOCK_SEL_LOW); + } + +out: + if (rv) { + CPRINTS("%s %d: failed to set clocks to full speed: %d", + CHARGER_NAME, chgnum, rv); + } + return rv; +} + static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask, const enum mask_update_action action) { @@ -292,6 +327,11 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) return rv; if (enable) { + rv = sm5803_set_full_clock_speed(chgnum); + if (rv) { + return rv; + } + if (chgnum == CHARGER_PRIMARY) { /* Magic for new silicon */ if (dev_id >= 3) { @@ -1697,6 +1737,11 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled) if (enabled) { int selected_current; + rv = sm5803_set_full_clock_speed(chgnum); + if (rv) { + return rv; + } + rv = chg_read8(chgnum, SM5803_REG_ANA_EN1, ®); if (rv) return rv; -- cgit v1.2.1 From 90c91e97ffbffc4eceb1538e0a84b15e6778f7cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:27 -0600 Subject: common/shmalloc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I569772ac2d5e473e19a2f51ef7eff589d106e9ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729750 Reviewed-by: Jeremy Bettis --- common/shmalloc.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/common/shmalloc.c b/common/shmalloc.c index b1705b52d1..251948f1dd 100644 --- a/common/shmalloc.c +++ b/common/shmalloc.c @@ -47,8 +47,8 @@ static void shared_mem_init(void) free_buf_chain = (struct shm_buffer *)__shared_mem_buf; free_buf_chain->next_buffer = NULL; free_buf_chain->prev_buffer = NULL; - free_buf_chain->buffer_size = system_usable_ram_end() - - (uintptr_t)__shared_mem_buf; + free_buf_chain->buffer_size = + system_usable_ram_end() - (uintptr_t)__shared_mem_buf; } DECLARE_HOOK(HOOK_INIT, shared_mem_init, HOOK_PRIO_FIRST); @@ -73,8 +73,7 @@ static void do_release(struct shm_buffer *ptr) * Saninty check: verify that the buffer is in the allocated * buffers chain. */ - for (pfb = allocced_buf_chain->next_buffer; - pfb; + for (pfb = allocced_buf_chain->next_buffer; pfb; pfb = pfb->next_buffer) if (pfb == ptr) break; @@ -117,10 +116,9 @@ static void do_release(struct shm_buffer *ptr) if (pfb == free_buf_chain) { set_map_bit(BIT(1)); /* Merge the two buffers. */ - ptr->buffer_size = free_buf_chain->buffer_size + - released_size; - ptr->next_buffer = - free_buf_chain->next_buffer; + ptr->buffer_size = + free_buf_chain->buffer_size + released_size; + ptr->next_buffer = free_buf_chain->next_buffer; } else { set_map_bit(BIT(2)); ptr->buffer_size = released_size; @@ -163,8 +161,7 @@ static void do_release(struct shm_buffer *ptr) if (top == pfb->next_buffer) { /* Yes, it is. */ pfb->buffer_size += pfb->next_buffer->buffer_size; - pfb->next_buffer = - pfb->next_buffer->next_buffer; + pfb->next_buffer = pfb->next_buffer->next_buffer; if (pfb->next_buffer) { set_map_bit(BIT(5)); pfb->next_buffer->prev_buffer = pfb; @@ -179,8 +176,8 @@ static void do_release(struct shm_buffer *ptr) if (top == pfb->next_buffer) { /* The new buffer is adjacent with the one right above it. */ set_map_bit(BIT(7)); - ptr->buffer_size = released_size + - pfb->next_buffer->buffer_size; + ptr->buffer_size = + released_size + pfb->next_buffer->buffer_size; ptr->next_buffer = pfb->next_buffer->next_buffer; } else { /* Just include the new free buffer into the chain. */ @@ -373,8 +370,7 @@ static int command_shmem(int argc, char **argv) max_free = buf_room; } - for (buf = allocced_buf_chain; buf; - buf = buf->next_buffer) + for (buf = allocced_buf_chain; buf; buf = buf->next_buffer) allocated_size += buf->buffer_size; mutex_unlock(&shmem_lock); @@ -386,8 +382,7 @@ static int command_shmem(int argc, char **argv) ccprintf("Max allocated: %6d\n", max_allocated_size); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL, "Print shared memory stats"); -#endif /* CONFIG_CMD_SHMEM ^^^^^^^ defined */ +#endif /* CONFIG_CMD_SHMEM ^^^^^^^ defined */ -- cgit v1.2.1 From 947d9c587b2e1313239c853d17309da3c82dc9e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:16 -0600 Subject: board/guybrush/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8316054fd3656af356b9c9dde59a2c0fa02c384d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728440 Reviewed-by: Jeremy Bettis --- board/guybrush/led.c | 40 ++++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/board/guybrush/led.c b/board/guybrush/led.c index b17c8be488..35da8c9f9c 100644 --- a/board/guybrush/led.c +++ b/board/guybrush/led.c @@ -12,29 +12,37 @@ #include "pwm.h" /* Note PWM LEDs are active low */ -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From a9cea272de53908d11704bbb847ff87c6c11ecf0 Mon Sep 17 00:00:00 2001 From: Manoj Gupta Date: Mon, 27 Jun 2022 21:39:27 +0000 Subject: Makefile.toolchain: Disable position independent code Disable position independent code generation explicitly. This is needed since GCC will be configured to use position independent code by default. BUG=b:236984388 TEST=CQ BRANCH=none Signed-off-by: Manoj Gupta Change-Id: I9cfc3c0e47b23b0282e06fd482441f979d19622d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730964 Tested-by: Manoj Gupta Commit-Queue: Jeremy Bettis Commit-Queue: Manoj Gupta Auto-Submit: Manoj Gupta Reviewed-by: Jeremy Bettis --- Makefile.toolchain | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Makefile.toolchain b/Makefile.toolchain index c2e952d43b..b9f7c2005a 100644 --- a/Makefile.toolchain +++ b/Makefile.toolchain @@ -98,7 +98,8 @@ CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \ $(if $(TEST_ASAN),-fsanitize=address) \ $(if $(TEST_MSAN),-fsanitize=memory) \ $(if $(TEST_UBSAN),$(UBSAN_FLAGS)) \ - $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link -DTEST_FUZZ=$(EMPTY)) + $(if $(TEST_FUZZ),-fsanitize=fuzzer-no-link -fno-PIE \ + -DTEST_FUZZ=$(EMPTY)) CFLAGS_COVERAGE=$(if $(TEST_COVERAGE),--coverage \ -DTEST_COVERAGE=$(EMPTY),) CFLAGS_HOSTTEST=$(if $(TEST_HOSTTEST),-DTEST_HOSTTEST=$(EMPTY),) -Iinclude/driver @@ -123,7 +124,7 @@ HOST_CPPFLAGS=$(CFLAGS_DEFINE) $(CFLAGS_INCLUDE) $(CFLAGS_TEST) \ $(EXTRA_CFLAGS) $(CFLAGS_COVERAGE) $(CFLAGS_HOSTTEST) $(LATE_CFLAGS_DEFINE) \ -DSECTION_IS_$(BLD)=$(EMPTY) -DSECTION=$(BLD) $(CPPFLAGS_$(BLD)) ifneq ($(BOARD),host) -CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib +CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib -fno-PIC CPPFLAGS+=-Ibuiltin/ else CPPFLAGS+=-Og @@ -132,6 +133,7 @@ CPPFLAGS+= -DCHROMIUM_EC=$(EMPTY) CFLAGS=$(CPPFLAGS) $(CFLAGS_CPU) $(CFLAGS_DEBUG) $(COMMON_WARN) $(CFLAGS_y) CFLAGS+= -ffunction-sections -fshort-wchar CFLAGS+= -fno-delete-null-pointer-checks +CFLAGS+= -fno-PIC ifneq ($(cc-name),clang) CFLAGS+= -ffat-lto-objects CFLAGS+= -fconserve-stack @@ -185,7 +187,7 @@ HOST_TEST_LDFLAGS=-Wl,-T core/host/host_exe.lds -lrt -pthread -rdynamic -lm\ $(if $(TEST_ASAN), -fsanitize=address) \ $(if $(TEST_MSAN), -fsanitize=memory) \ $(if $(TEST_UBSAN), ${UBSAN_FLAGS}) \ - $(if $(TEST_FUZZ), -fsanitize=fuzzer) + $(if $(TEST_FUZZ), -fsanitize=fuzzer -no-pie) # utility function to provide overridable defaults # $1: name of variable to set -- cgit v1.2.1 From 1aa0ab45188e90f2e16286b4796bc8911d50450c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:24 -0600 Subject: board/dratini/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6b16bc0f5208aa7d682fbb3db66308e98b7b32c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728236 Reviewed-by: Jeremy Bettis --- board/dratini/led.c | 51 +++++++++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 24 deletions(-) diff --git a/board/dratini/led.c b/board/dratini/led.c index a5a8e9e158..ab29ac0344 100644 --- a/board/dratini/led.c +++ b/board/dratini/led.c @@ -24,11 +24,9 @@ #define LED_TICKS_PER_CYCLE 10 #define LED_ON_TICKS 5 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -36,7 +34,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color_battery(int port, enum led_color color) @@ -158,15 +156,14 @@ static void led_set_battery(void) */ if (!board_is_convertible()) { if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && - charge_get_state() != PWR_STATE_CHARGE) { - + CHIPSET_STATE_STANDBY) && + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; - led_set_color_battery(0, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); - led_set_color_battery(1, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE : + LED_OFF); + led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE : + LED_OFF); return; } } @@ -181,9 +178,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(0, (battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_battery( + 0, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(0, LED_OFF); } @@ -192,17 +192,19 @@ static void led_set_battery(void) led_set_color_battery(1, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; @@ -222,9 +224,10 @@ static void led_set_power(void) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY)) - led_set_color_power((power_tick % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_power( + (power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 5f63583e57a7c773ef483bfecfcdef8a2055d0ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:20 -0600 Subject: driver/tcpm/anx7447.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7832a682a1845a9d71ef296758813e4b6f436757 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730073 Reviewed-by: Jeremy Bettis --- driver/tcpm/anx7447.h | 183 +++++++++++++++++++++++++------------------------- 1 file changed, 91 insertions(+), 92 deletions(-) diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h index 30396c26b3..623a80b9c7 100644 --- a/driver/tcpm/anx7447.h +++ b/driver/tcpm/anx7447.h @@ -11,132 +11,132 @@ #define __CROS_EC_USB_PD_TCPM_ANX7447_H /* Registers: TCPC address used */ -#define ANX7447_REG_TCPC_SWITCH_0 0xB4 -#define ANX7447_REG_TCPC_SWITCH_1 0xB5 -#define ANX7447_REG_TCPC_AUX_SWITCH 0xB6 -#define VCONN_VOLTAGE_ALARM_HI_CFG 0xB7 +#define ANX7447_REG_TCPC_SWITCH_0 0xB4 +#define ANX7447_REG_TCPC_SWITCH_1 0xB5 +#define ANX7447_REG_TCPC_AUX_SWITCH 0xB6 +#define VCONN_VOLTAGE_ALARM_HI_CFG 0xB7 -#define ANX7447_REG_INTR_ALERT_MASK_0 0xC9 +#define ANX7447_REG_INTR_ALERT_MASK_0 0xC9 -#define ANX7447_REG_TCPC_CTRL_2 0xCD -#define ANX7447_REG_ENABLE_VBUS_PROTECT 0x20 +#define ANX7447_REG_TCPC_CTRL_2 0xCD +#define ANX7447_REG_ENABLE_VBUS_PROTECT 0x20 -#define ANX7447_REG_ADC_CTRL_1 0xBF -#define ANX7447_REG_ADCFSM_EN 0x20 +#define ANX7447_REG_ADC_CTRL_1 0xBF +#define ANX7447_REG_ADCFSM_EN 0x20 /* Registers: SPI address used */ -#define ANX7447_REG_INTP_SOURCE_0 0x67 - -#define ANX7447_REG_HPD_CTRL_0 0x7E -#define ANX7447_REG_HPD_MODE 0x01 -#define ANX7447_REG_HPD_OUT 0x02 -#define ANX7447_REG_HPD_IRQ0 0x04 -#define ANX7447_REG_HPD_PLUG 0x08 -#define ANX7447_REG_HPD_UNPLUG 0x10 - -#define ANX7447_REG_HPD_DEGLITCH_H 0x80 -#define ANX7447_REG_HPD_DETECT 0x80 -#define ANX7447_REG_HPD_OEN 0x40 - -#define ANX7447_REG_PAD_INTP_CTRL 0x85 - -#define ANX7447_REG_INTP_MASK_0 0x86 - -#define ANX7447_REG_TCPC_CTRL_1 0x9D -#define CC_DEBOUNCE_MS BIT(3) -#define CC_DEBOUNCE_TIME_HI_BIT BIT(0) -#define ANX7447_REG_INTP_CTRL_0 0x9E -#define ANX7447_REG_CC_DEBOUNCE_TIME 0x9F - -#define ANX7447_REG_ANALOG_CTRL_8 0xA8 -#define ANX7447_REG_VCONN_OCP_MASK 0x0C -#define ANX7447_REG_VCONN_OCP_240mA 0x00 -#define ANX7447_REG_VCONN_OCP_310mA 0x04 -#define ANX7447_REG_VCONN_OCP_370mA 0x08 -#define ANX7447_REG_VCONN_OCP_440mA 0x0C - -#define ANX7447_REG_ANALOG_CTRL_10 0xAA -#define ANX7447_REG_CABLE_DET_DIG 0x40 - -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK 0x38 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US 0x00 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US 0x08 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US 0x10 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US 0x18 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US 0x20 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US 0x28 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US 0x30 -#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US 0x38 - -#define ANX7447_REG_ANALOG_CTRL_9 0xA9 -#define ANX7447_REG_SAFE_MODE 0x80 -#define ANX7447_REG_R_AUX_RES_PULL_SRC 0x20 +#define ANX7447_REG_INTP_SOURCE_0 0x67 + +#define ANX7447_REG_HPD_CTRL_0 0x7E +#define ANX7447_REG_HPD_MODE 0x01 +#define ANX7447_REG_HPD_OUT 0x02 +#define ANX7447_REG_HPD_IRQ0 0x04 +#define ANX7447_REG_HPD_PLUG 0x08 +#define ANX7447_REG_HPD_UNPLUG 0x10 + +#define ANX7447_REG_HPD_DEGLITCH_H 0x80 +#define ANX7447_REG_HPD_DETECT 0x80 +#define ANX7447_REG_HPD_OEN 0x40 + +#define ANX7447_REG_PAD_INTP_CTRL 0x85 + +#define ANX7447_REG_INTP_MASK_0 0x86 + +#define ANX7447_REG_TCPC_CTRL_1 0x9D +#define CC_DEBOUNCE_MS BIT(3) +#define CC_DEBOUNCE_TIME_HI_BIT BIT(0) +#define ANX7447_REG_INTP_CTRL_0 0x9E +#define ANX7447_REG_CC_DEBOUNCE_TIME 0x9F + +#define ANX7447_REG_ANALOG_CTRL_8 0xA8 +#define ANX7447_REG_VCONN_OCP_MASK 0x0C +#define ANX7447_REG_VCONN_OCP_240mA 0x00 +#define ANX7447_REG_VCONN_OCP_310mA 0x04 +#define ANX7447_REG_VCONN_OCP_370mA 0x08 +#define ANX7447_REG_VCONN_OCP_440mA 0x0C + +#define ANX7447_REG_ANALOG_CTRL_10 0xAA +#define ANX7447_REG_CABLE_DET_DIG 0x40 + +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK 0x38 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US 0x00 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US 0x08 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_76US 0x10 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_152US 0x18 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_303US 0x20 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_607US 0x28 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_1210US 0x30 +#define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_2430US 0x38 + +#define ANX7447_REG_ANALOG_CTRL_9 0xA9 +#define ANX7447_REG_SAFE_MODE 0x80 +#define ANX7447_REG_R_AUX_RES_PULL_SRC 0x20 /* * This section of defines are only required to support the config option * CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND. */ /* SPI registers used for OCM flash operations */ -#define ANX7447_DELAY_IN_US (20*1000) - -#define ANX7447_REG_R_RAM_CTRL 0x05 -#define ANX7447_REG_R_FLASH_RW_CTRL 0x30 -#define ANX7447_REG_R_FLASH_STATUS_0 0x31 -#define ANX7447_REG_FLASH_INST_TYPE 0x33 -#define ANX7447_REG_FLASH_ERASE_TYPE 0x34 -#define ANX7447_REG_OCM_CTRL_0 0x6E -#define ANX7447_REG_ADDR_GPIO_CTRL_0 0x88 -#define ANX7447_REG_OCM_MAIN_VERSION 0xB4 -#define ANX7447_REG_OCM_BUILD_VERSION 0xB5 +#define ANX7447_DELAY_IN_US (20 * 1000) + +#define ANX7447_REG_R_RAM_CTRL 0x05 +#define ANX7447_REG_R_FLASH_RW_CTRL 0x30 +#define ANX7447_REG_R_FLASH_STATUS_0 0x31 +#define ANX7447_REG_FLASH_INST_TYPE 0x33 +#define ANX7447_REG_FLASH_ERASE_TYPE 0x34 +#define ANX7447_REG_OCM_CTRL_0 0x6E +#define ANX7447_REG_ADDR_GPIO_CTRL_0 0x88 +#define ANX7447_REG_OCM_MAIN_VERSION 0xB4 +#define ANX7447_REG_OCM_BUILD_VERSION 0xB5 /* R_RAM_CTRL bit definitions */ -#define ANX7447_R_RAM_CTRL_FLASH_DONE (1<<7) +#define ANX7447_R_RAM_CTRL_FLASH_DONE (1 << 7) /* R_FLASH_RW_CTRL bit definitions */ -#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN (1<<6) -#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN (1<<5) -#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN (1<<2) -#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ (1<<1) -#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE (1<<0) +#define ANX7447_R_FLASH_RW_CTRL_GENERAL_INST_EN (1 << 6) +#define ANX7447_R_FLASH_RW_CTRL_FLASH_ERASE_EN (1 << 5) +#define ANX7447_R_FLASH_RW_CTRL_WRITE_STATUS_EN (1 << 2) +#define ANX7447_R_FLASH_RW_CTRL_FLASH_READ (1 << 1) +#define ANX7447_R_FLASH_RW_CTRL_FLASH_WRITE (1 << 0) /* R_FLASH_STATUS_0 definitions */ -#define ANX7447_FLASH_STATUS_SPI_STATUS_0 0x43 +#define ANX7447_FLASH_STATUS_SPI_STATUS_0 0x43 /* FLASH_ERASE_TYPE bit definitions */ -#define ANX7447_FLASH_INST_TYPE_WRITEENABLE 0x06 -#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE 0x60 +#define ANX7447_FLASH_INST_TYPE_WRITEENABLE 0x06 +#define ANX7447_FLASH_ERASE_TYPE_CHIPERASE 0x60 /* OCM_CTRL_0 bit definitions */ -#define ANX7447_OCM_CTRL_OCM_RESET (1<<6) +#define ANX7447_OCM_CTRL_OCM_RESET (1 << 6) /* ADDR_GPIO_CTRL_0 bit definitions */ -#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP (1<<7) -#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE (1<<6) +#define ANX7447_ADDR_GPIO_CTRL_0_SPI_WP (1 << 7) +#define ANX7447_ADDR_GPIO_CTRL_0_SPI_CLK_ENABLE (1 << 6) /* End of defines used for CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND */ struct anx7447_i2c_addr { - uint16_t tcpc_addr_flags; - uint16_t spi_addr_flags; + uint16_t tcpc_addr_flags; + uint16_t spi_addr_flags; }; -#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C -#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B -#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A -#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 -#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F -#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 -#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 -#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 /* * Time TEST_R must be held high for a reset */ -#define ANX74XX_RESET_HOLD_MS 1 +#define ANX74XX_RESET_HOLD_MS 1 /* * Time after TEST_R reset to wait for eFuse loading */ -#define ANX74XX_RESET_FINISH_MS 2 +#define ANX74XX_RESET_FINISH_MS 2 int anx7447_set_power_supply_ready(int port); int anx7447_power_supply_reset(int port); @@ -149,8 +149,7 @@ extern const struct tcpm_drv anx7447_tcpm_drv; extern const struct usb_mux_driver anx7447_usb_mux_driver; void anx7447_tcpc_clear_hpd_status(int port); void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); /** * Erase OCM flash if it's not empty -- cgit v1.2.1 From 56e21ca4649093752e9086db63171d05c744498f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:30 -0600 Subject: board/wormdingler/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I22b525bb572015220011e097d9f04fab55b6f58f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729120 Reviewed-by: Jeremy Bettis --- board/wormdingler/led.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/wormdingler/led.c b/board/wormdingler/led.c index 40de6257fa..f9eab763b3 100644 --- a/board/wormdingler/led.c +++ b/board/wormdingler/led.c @@ -36,15 +36,15 @@ enum led_color { LED_RED, LED_GREEN, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, - (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_G_C0, - (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); if (color == LED_AMBER) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON); gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON); @@ -86,13 +86,13 @@ static void board_led_set_battery(void) case PWR_STATE_CHARGE: case PWR_STATE_CHARGE_NEAR_FULL: if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND | - CHIPSET_STATE_ANY_OFF)) { + CHIPSET_STATE_ANY_SUSPEND | + CHIPSET_STATE_ANY_OFF)) { if (percent <= BATTERY_LEVEL_CRITICAL) { /* battery capa <= 5%, Red */ color = LED_RED; } else if (percent > BATTERY_LEVEL_CRITICAL && - percent < BATTERY_LEVEL_NEAR_FULL) { + percent < BATTERY_LEVEL_NEAR_FULL) { /* 5% < battery capa < 97%, Orange */ color = LED_AMBER; } else { @@ -102,8 +102,8 @@ static void board_led_set_battery(void) } break; case PWR_STATE_DISCHARGE: - /* Always indicate off on when discharging */ - color = LED_OFF; + /* Always indicate off on when discharging */ + color = LED_OFF; break; case PWR_STATE_ERROR: /* Battery error, Red on 1sec off 1sec */ @@ -147,7 +147,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state) enum led_color color; if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) && - (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) + (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) return; if (state == LED_STATE_RESET) { -- cgit v1.2.1 From a45696861b8c5bffeb4bd3216bfb1148d309e884 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:31 -0600 Subject: chip/npcx/sha256_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie624376a3d881ee1748ce76921214b58b9bcadce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729431 Reviewed-by: Jeremy Bettis --- chip/npcx/sha256_chip.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/npcx/sha256_chip.h b/chip/npcx/sha256_chip.h index 3b9586d962..fba01a8dbf 100644 --- a/chip/npcx/sha256_chip.h +++ b/chip/npcx/sha256_chip.h @@ -8,7 +8,7 @@ #include "common.h" -#define NPCX_SHA256_HANDLE_SIZE 212 +#define NPCX_SHA256_HANDLE_SIZE 212 struct sha256_ctx { /* the context handle required for SHA256 API */ uint8_t handle[NPCX_SHA256_HANDLE_SIZE]; @@ -22,4 +22,4 @@ struct sha256_ctx { void SHA256_abort(struct sha256_ctx *ctx); -#endif /* __CROS_EC_SHA256_CHIP_H */ +#endif /* __CROS_EC_SHA256_CHIP_H */ -- cgit v1.2.1 From 1f37c24033121cce0eb83f2adab49407bfdb3942 Mon Sep 17 00:00:00 2001 From: Peter Chi Date: Wed, 22 Jun 2022 10:00:31 +0800 Subject: crota: add more BYD battery support BUG=b:236739228 BRANCH=none TEST=make -j BOARD=crota Signed-off-by: Peter Chi Change-Id: I73f4b5da9243d9161743276c68e8011264c602d6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716430 Commit-Queue: caveh jalali Reviewed-by: caveh jalali --- board/crota/battery.c | 31 ++++++++++++++++++++++++++++++- board/crota/board.h | 3 ++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/board/crota/battery.c b/board/crota/battery.c index 5bdf307b07..de60f74ad2 100644 --- a/board/crota/battery.c +++ b/board/crota/battery.c @@ -63,7 +63,7 @@ const struct board_batt_params board_battery_info[] = { }, }, /* BYD 13076993-009 Battery Information */ - [BATTERY_BYD] = { + [BATTERY_BYD_GSL4] = { .fuel_gauge = { .manuf_name = "BYD", .device_name = "DELL WV3K8", @@ -323,6 +323,35 @@ const struct board_batt_params board_battery_info[] = { .discharging_max_c = 70, }, }, + /* BYD 13148981-00 Battery Information */ + [BATTERY_BYD_CSL4] = { + .fuel_gauge = { + .manuf_name = "BYD", + .device_name = "DELL JGCCT", + .ship_mode = { + .reg_addr = 0x00, + .reg_data = { 0x0010, 0x0010 }, + }, + .fet = { + .mfgacc_support = 0, + .reg_addr = 0x00, + .reg_mask = 0x2000, + .disconnect_val = 0x2000, + } + }, + .batt_info = { + .voltage_max = 17400, /* mV */ + .voltage_normal = 15000, /* mV */ + .voltage_min = 12000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 60, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = 0, + .discharging_max_c = 70, + }, + }, /* Sunwoda 1002000009262 Battery Information */ [BATTERY_SWD_ATL4] = { .fuel_gauge = { diff --git a/board/crota/board.h b/board/crota/board.h index 46f3eb7755..3b0bea06dc 100644 --- a/board/crota/board.h +++ b/board/crota/board.h @@ -234,7 +234,7 @@ enum ioex_port { enum battery_type { BATTERY_ATL, - BATTERY_BYD, + BATTERY_BYD_GSL4, BATTERY_COM, BATTERY_LGC, BATTERY_SMP_ATL3, @@ -243,6 +243,7 @@ enum battery_type { BATTERY_SWD_COS3, BATTERY_SMP_ATL4, BATTERY_SMP_COS4, + BATTERY_BYD_CSL4, BATTERY_SWD_ATL4, BATTERY_SWD_COS4, BATTERY_TYPE_COUNT -- cgit v1.2.1 From 6d1c9630b9bbaeabe8ffa8c10bdea6f2706a6156 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:43 -0600 Subject: board/brya/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1c9ad4d3702e8f592135731c7dcf10faecc2cc2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728107 Reviewed-by: Jeremy Bettis --- board/brya/usbc_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brya/usbc_config.h b/board/brya/usbc_config.h index 9e7652d9a0..97b3e7f5fd 100644 --- a/board/brya/usbc_config.h +++ b/board/brya/usbc_config.h @@ -9,7 +9,7 @@ #define __CROS_EC_USBC_CONFIG_H #ifndef CONFIG_ZEPHYR -#define CONFIG_USB_PD_PORT_MAX_COUNT 3 +#define CONFIG_USB_PD_PORT_MAX_COUNT 3 #endif enum usbc_port { -- cgit v1.2.1 From f19c2cf774821cdc7744d20f89526d4e7c5be509 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:26 -0600 Subject: board/wormdingler/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic1da3e5c2d5c7720988beab3ab6766dfbde485c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729119 Reviewed-by: Jeremy Bettis --- board/wormdingler/board.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/board/wormdingler/board.h b/board/wormdingler/board.h index e6415bccce..2ec6c5a67e 100644 --- a/board/wormdingler/board.h +++ b/board/wormdingler/board.h @@ -13,13 +13,13 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Switchcap */ #define CONFIG_LN9310 /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -80,10 +80,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 9de1258568fb0b5c78b0c464cb0c35447adfe356 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:29 -0600 Subject: board/collis/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10ba0d4891771d7f18586eeef9a3edd4bf55cd9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728174 Reviewed-by: Jeremy Bettis --- board/collis/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/collis/led.c b/board/collis/led.c index 508a5eb585..6444eb6a89 100644 --- a/board/collis/led.c +++ b/board/collis/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From c2352da9a69e07efaa2b2ef61704717d4dd6e561 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:14 -0600 Subject: include/lpc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If90187409f944f0d8fc95a8badfb287802a3a9e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730347 Reviewed-by: Jeremy Bettis --- include/lpc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/lpc.h b/include/lpc.h index 58894fa2f2..eba3924b87 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -169,4 +169,4 @@ void lpc_init_mask(void); */ void lpc_s3_resume_clear_masks(void); -#endif /* __CROS_EC_LPC_H */ +#endif /* __CROS_EC_LPC_H */ -- cgit v1.2.1 From d4e422b6bbfcb434092eaed39c3849ff75e797ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:27 -0600 Subject: board/waddledoo2/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a1efea86a538a286027060d68f0366ffe98cd60 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729111 Reviewed-by: Jeremy Bettis --- board/waddledoo2/board.c | 95 +++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 53 deletions(-) diff --git a/board/waddledoo2/board.c b/board/waddledoo2/board.c index 1f7ad2da92..e3c5e49bbd 100644 --- a/board/waddledoo2/board.c +++ b/board/waddledoo2/board.c @@ -51,13 +51,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) static uint8_t new_adc_key_state; @@ -110,8 +110,8 @@ static const struct ec_response_keybd_config waddledoo2_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &waddledoo2_keybd; } @@ -152,7 +152,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -226,22 +225,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -258,8 +257,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -334,13 +333,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -400,8 +397,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -426,18 +423,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; - -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* BMA253 private data */ static struct accelgyro_saved_data_t g_bma253_data; @@ -445,11 +437,9 @@ static struct accelgyro_saved_data_t g_bma253_data; /* BMI160 private data */ static struct bmi_drv_data_t g_bmi160_data; -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* ICM426 private data */ static struct icm_drv_data_t g_icm426xx_data; @@ -633,7 +623,7 @@ void board_init(void) gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); } /* Turn on 5V if the system is on, otherwise turn it off. */ @@ -648,20 +638,19 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); void motion_interrupt(enum gpio_signal signal) { - switch (get_cbi_ssfc_base_sensor()) { - case SSFC_SENSOR_ICM426XX: - icm426xx_interrupt(signal); - break; - case SSFC_SENSOR_BMI160: - default: - bmi160_interrupt(signal); - break; - } + switch (get_cbi_ssfc_base_sensor()) { + case SSFC_SENSOR_ICM426XX: + icm426xx_interrupt(signal); + break; + case SSFC_SENSOR_BMI160: + default: + bmi160_interrupt(signal); + break; + } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; -- cgit v1.2.1 From a6b0b3554f59cc9b0c4aae9bff7dff075f2089a9 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 17:15:14 -0700 Subject: trng: Rename rand to trng_rand The declaration for rand conflicts with the standard library declaration so rename it from "rand" to "trng_rand". This has the benefit of making it obvious when we're using the true random number generator. For consistency, this also renames init_trng/exit_trng to trng_init/trng_exit. BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: Ic3305a91263c45786c051eaa5b3689e7464aa0ab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712032 Reviewed-by: Bobby Casey Reviewed-by: Jack Rosenthal --- chip/host/trng.c | 6 +++--- chip/stm32/trng.c | 22 +++++++++++----------- common/fpsensor/fpsensor.c | 26 +++++++++++++------------- common/rollback.c | 6 +++--- include/trng.h | 12 +++++------- third_party/boringssl/common/curve25519.c | 2 +- 6 files changed, 36 insertions(+), 38 deletions(-) diff --git a/chip/host/trng.c b/chip/host/trng.c index 8407aa6ea1..cb69268e34 100644 --- a/chip/host/trng.c +++ b/chip/host/trng.c @@ -21,17 +21,17 @@ static unsigned int seed; -test_mockable void init_trng(void) +test_mockable void trng_init(void) { seed = 0; srand(seed); } -test_mockable void exit_trng(void) +test_mockable void trng_exit(void) { } -test_mockable void rand_bytes(void *buffer, size_t len) +test_mockable void trng_rand_bytes(void *buffer, size_t len) { uint8_t *b, *end; diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 48d5335c53..447ccbccad 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -15,7 +15,7 @@ #include "trng.h" #include "util.h" -uint32_t rand(void) +uint32_t trng_rand(void) { int tries = 300; /* Wait for a valid random number */ @@ -28,10 +28,10 @@ uint32_t rand(void) return STM32_RNG_DR; } -test_mockable void rand_bytes(void *buffer, size_t len) +test_mockable void trng_rand_bytes(void *buffer, size_t len) { while (len) { - uint32_t number = rand(); + uint32_t number = trng_rand(); size_t cnt = 4; /* deal with the lack of alignment guarantee in the API */ uintptr_t align = (uintptr_t)buffer & 3; @@ -47,7 +47,7 @@ test_mockable void rand_bytes(void *buffer, size_t len) } } -test_mockable void init_trng(void) +test_mockable void trng_init(void) { #ifdef CHIP_FAMILY_STM32L4 /* Enable the 48Mhz internal RC oscillator */ @@ -84,7 +84,7 @@ test_mockable void init_trng(void) STM32_RNG_CR |= STM32_RNG_CR_RNGEN; } -test_mockable void exit_trng(void) +test_mockable void trng_exit(void) { STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; @@ -107,9 +107,9 @@ static int command_rand(int argc, char **argv) { uint8_t data[32]; - init_trng(); - rand_bytes(data, sizeof(data)); - exit_trng(); + trng_init(); + trng_rand_bytes(data, sizeof(data)); + trng_exit(); ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); @@ -130,9 +130,9 @@ static enum ec_status host_command_rand(struct host_cmd_handler_args *args) if (num_rand_bytes > args->response_max) return EC_RES_OVERFLOW; - init_trng(); - rand_bytes(r->rand, num_rand_bytes); - exit_trng(); + trng_init(); + trng_rand_bytes(r->rand, num_rand_bytes); + trng_exit(); args->response_size = num_rand_bytes; diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c index 12904c0b39..a491e1af84 100644 --- a/common/fpsensor/fpsensor.c +++ b/common/fpsensor/fpsensor.c @@ -472,11 +472,11 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) */ enc_info = (void *)fp_enc_buffer; enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION; - init_trng(); - rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); - rand_bytes(enc_info->encryption_salt, - FP_CONTEXT_ENCRYPTION_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); + trng_rand_bytes(enc_info->encryption_salt, + FP_CONTEXT_ENCRYPTION_SALT_BYTES); + trng_exit(); if (fgr == template_newly_enrolled) { /* @@ -485,10 +485,10 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) * value. */ template_newly_enrolled = FP_NO_SUCH_TEMPLATE; - init_trng(); - rand_bytes(fp_positive_match_salt[fgr], - FP_POSITIVE_MATCH_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(fp_positive_match_salt[fgr], + FP_POSITIVE_MATCH_SALT_BYTES); + trng_exit(); } ret = derive_encryption_key(key, enc_info->encryption_salt); @@ -647,10 +647,10 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args) sizeof(fp_template[0])); if (template_needs_validation_value(enc_info)) { CPRINTS("fgr%d: Generating positive match salt.", idx); - init_trng(); - rand_bytes(positive_match_salt, - FP_POSITIVE_MATCH_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(positive_match_salt, + FP_POSITIVE_MATCH_SALT_BYTES); + trng_exit(); } if (bytes_are_trivial(positive_match_salt, sizeof(fp_positive_match_salt[0]))) { diff --git a/common/rollback.c b/common/rollback.c index 984058c49a..3f9e176782 100644 --- a/common/rollback.c +++ b/common/rollback.c @@ -400,9 +400,9 @@ static void add_entropy_deferred(void) if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC) repeat = ROLLBACK_REGIONS; - init_trng(); + trng_init(); do { - rand_bytes(rand, sizeof(rand)); + trng_rand_bytes(rand, sizeof(rand)); if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) { add_entropy_rv = EC_RES_ERROR; goto out; @@ -411,7 +411,7 @@ static void add_entropy_deferred(void) add_entropy_rv = EC_RES_SUCCESS; out: - exit_trng(); + trng_exit(); } DECLARE_DEFERRED(add_entropy_deferred); diff --git a/include/trng.h b/include/trng.h index cea4555b41..969366ae8e 100644 --- a/include/trng.h +++ b/include/trng.h @@ -14,32 +14,30 @@ * * Not supported by all platforms. **/ -void init_trng(void); +void trng_init(void); /** * Shutdown the true random number generator. * - * The opposite operation of init_trng(), disable the hardware resources + * The opposite operation of trng_init(), disable the hardware resources * used by the TRNG to save power. * * Not supported by all platforms. **/ -void exit_trng(void); +void trng_exit(void); /** * Retrieve a 32 bit random value. * * Not supported on all platforms. **/ -#ifndef HIDE_EC_STDLIB -uint32_t rand(void); -#endif +uint32_t trng_rand(void); /** * Output len random bytes into buffer. * * Not supported on all platforms. **/ -void rand_bytes(void *buffer, size_t len); +void trng_rand_bytes(void *buffer, size_t len); #endif /* __EC_INCLUDE_TRNG_H */ diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c index 2a7fad6509..b74d3c7d97 100644 --- a/third_party/boringssl/common/curve25519.c +++ b/third_party/boringssl/common/curve25519.c @@ -27,7 +27,7 @@ #ifdef CONFIG_RNG void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) { - rand_bytes(out_private_key, 32); + trng_rand_bytes(out_private_key, 32); /* All X25519 implementations should decode scalars correctly (see * https://tools.ietf.org/html/rfc7748#section-5). However, if an -- cgit v1.2.1 From 449b52066f7be55584ea275b140513f3bc4de77b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:43 -0600 Subject: include/sha256.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If558fecc0ee88def67289b0cc472d53ecbc7fca6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730404 Reviewed-by: Jeremy Bettis --- include/sha256.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/sha256.h b/include/sha256.h index 130a666788..28ed988ebe 100644 --- a/include/sha256.h +++ b/include/sha256.h @@ -26,7 +26,7 @@ struct sha256_ctx { uint32_t tot_len; uint32_t len; uint8_t block[2 * SHA256_BLOCK_SIZE]; - uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */ + uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */ }; #endif @@ -37,4 +37,4 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx); void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, const uint8_t *message, const int message_len); -#endif /* __CROS_EC_SHA256_H */ +#endif /* __CROS_EC_SHA256_H */ -- cgit v1.2.1 From d884e8c8e73275b8f891ec6b717289ff72abce1d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:04 -0600 Subject: board/sasuke/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c17dd37f0a2c09e62f636fde3db949bbd457a37 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728895 Reviewed-by: Jeremy Bettis --- board/sasuke/battery.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/sasuke/battery.c b/board/sasuke/battery.c index ad7ea9c2fe..bfa3c979e1 100644 --- a/board/sasuke/battery.c +++ b/board/sasuke/battery.c @@ -12,7 +12,7 @@ #include "usb_pd.h" #include "util.h" -#define CHARGING_CURRENT_REDUCE 4000 +#define CHARGING_CURRENT_REDUCE 4000 /* * Battery info for all sasuke battery types. Note that the fields * start_charging_min/max and charging_min/max are not used for the charger. @@ -152,7 +152,7 @@ static void reduce_input_voltage_when_full(void) int port; if (charge_get_percent() == 100 && - chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { + chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) { saved_input_voltage = max_pd_voltage_mv; max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL; @@ -168,5 +168,4 @@ static void reduce_input_voltage_when_full(void) pd_set_external_voltage_limit(port, max_pd_voltage_mv); } } -DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 091f41f23901c1fc46877681c11b34519abe7ed6 Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Tue, 21 Jun 2022 19:33:56 -0600 Subject: zephyr: tests: Add Get_Battery_Cap support to partner emulator Add mechanism for the TCPCI Partner emulator to send a Get_Battery_Capabilities request to the TCPC, and handle its response. The response is stored in the partner emulator's state for inspection in unit tests. BUG=b:223452169 BRANCH=None TEST=zmake test test-drivers Signed-off-by: Tristan Honscheid Change-Id: I7af85c60b0d4462be2b034f69f6a7288ee422760 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715698 Reviewed-by: Keith Short --- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 120 +++++++++++++++++++++ .../include/emul/tcpc/emul_tcpci_partner_common.h | 35 ++++++ 2 files changed, 155 insertions(+) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 39f1101241..5ef5d12729 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -534,6 +534,30 @@ int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data, return tcpci_partner_send_msg(data, msg, delay); } +/** Check description in emul_common_tcpci_partner.h */ +void tcpci_partner_common_send_get_battery_capabilities( + struct tcpci_partner_data *data, int battery_index) +{ + __ASSERT(battery_index >= 0 && battery_index < PD_BATT_MAX, + "Battery index out of range"); + __ASSERT(data->battery_capabilities.index < 0, + "Get Battery Capabilities request already in progress"); + + LOG_INF("Send battery cap request"); + + /* Get_Battery_Cap message payload */ + uint8_t payload[1] = { [0] = battery_index }; + + /* Keep track which battery we requested capabilities for */ + data->battery_capabilities.index = battery_index; + int ret = tcpci_partner_send_extended_msg(data, PD_EXT_GET_BATTERY_CAP, + 0, payload, sizeof(payload)); + if (ret) { + LOG_ERR("Send battery capacity result: %d", ret); + } + tcpci_partner_start_sender_response_timer(data); +} + /** * @brief Handler for response timeout * @@ -650,6 +674,60 @@ tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data, } } +/** + * @brief Handle a received Battery Capability message from the TCPC. Save the + * contents to the emulator data struct for analysis. + * + * @param data Emulator state + * @param message Received PD message + * @return enum tcpci_partner_handler_res + */ +static enum tcpci_partner_handler_res +tcpci_partner_common_battery_capability_handler( + struct tcpci_partner_data *data, const struct tcpci_emul_msg *message) +{ + uint16_t header = sys_get_le16(&message->buf[0]); + uint16_t ext_header = sys_get_le16(&message->buf[2]); + + /* Validate message header */ + __ASSERT(PD_HEADER_TYPE(header) == PD_EXT_BATTERY_CAP, + "wrong message type"); + __ASSERT(PD_EXT_HEADER_DATA_SIZE(ext_header) == 9, + "Data size mismatch"); + + int index = data->battery_capabilities.index; + + data->battery_capabilities.index = -1; + + if (index < 0) { + LOG_ERR("Received a Battery Capability message but it was " + "never requested"); + return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; + } + + __ASSERT(index < PD_BATT_MAX, "Battery index out of range"); + + data->battery_capabilities.bcdb[index] = (struct pd_bcdb){ + .vid = sys_get_le16(&message->buf[4]), + .pid = sys_get_le16(&message->buf[6]), + .design_cap = sys_get_le16(&message->buf[8]), + .last_full_charge_cap = sys_get_le16(&message->buf[10]), + .battery_type = message->buf[12], + }; + + data->battery_capabilities.have_response[index] = true; + + LOG_INF("Saved data for battery index (%d): vid=%04x, pid=%04x, " + "cap=%u, last_cap=%u, type=%02x", + index, data->battery_capabilities.bcdb[index].vid, + data->battery_capabilities.bcdb[index].pid, + data->battery_capabilities.bcdb[index].design_cap, + data->battery_capabilities.bcdb[index].last_full_charge_cap, + data->battery_capabilities.bcdb[index].battery_type); + + return TCPCI_PARTNER_COMMON_MSG_HANDLED; +} + static void tcpci_partner_common_set_vconn(struct tcpci_partner_data *data, enum pd_vconn_role role) { @@ -786,7 +864,34 @@ static enum tcpci_partner_handler_res tcpci_partner_common_sop_msg_handler( data->recv_msg_id = PD_HEADER_ID(header); + if (PD_HEADER_EXT(header)) { + /* Extended message */ + + if (PD_HEADER_REV(header) < PD_REV30) { + LOG_ERR("Received extended message but current PD rev " + "(0x%x) does not support them.", + PD_HEADER_REV(header)); + return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; + } + + switch (PD_HEADER_TYPE(header)) { + case PD_EXT_GET_BATTERY_CAP: + /* Not implemented */ + LOG_INF("Got PD_EXT_GET_BATTERY_CAP"); + return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; + case PD_EXT_BATTERY_CAP: + /* Received a Battery Capabilities response */ + LOG_INF("Got PD_EXT_BATTERY_CAP"); + + return tcpci_partner_common_battery_capability_handler( + data, tx_msg); + default: + return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; + } + } + if (PD_HEADER_CNT(header)) { + /* Data message */ switch (PD_HEADER_TYPE(header)) { case PD_DATA_VENDOR_DEF: return tcpci_partner_common_vdm_handler(data, tx_msg); @@ -1237,9 +1342,20 @@ int tcpci_partner_connect_to_tcpci(struct tcpci_partner_data *data, data->tcpci_emul = NULL; } + /* Clear any received battery capability info */ + tcpci_partner_reset_battery_capability_state(data); + return ret; } +void tcpci_partner_reset_battery_capability_state( + struct tcpci_partner_data *data) +{ + memset(&data->battery_capabilities, 0, + sizeof(data->battery_capabilities)); + data->battery_capabilities.index = -1; +} + void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev) { k_timer_init(&data->delayed_send, tcpci_partner_delayed_send_timer, @@ -1269,4 +1385,8 @@ void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev) data->ops.control_change = NULL; data->ops.disconnect = tcpci_partner_disconnect_op; data->displayport_configured = false; + + /* Reset the data structure used to store battery capability responses + */ + tcpci_partner_reset_battery_capability_state(data); } diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index c5d31694a8..9648a03e8a 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -152,6 +152,22 @@ struct tcpci_partner_data { /* VDMs sent when responding to DisplayPort config command */ uint32_t dp_config_vdm[VDO_MAX_SIZE]; int dp_config_vdos; + struct { + /* Index of the last battery we requested capabilities for. The + * BCDB response does not include the index so we need to track + * it manually. -1 indicates no outstanding request. + */ + int index; + /* Stores Battery Capability Data Blocks (BCDBs) requested and + * received from the TCPM for later analysis. See USB-PD spec + * Rev 3.1, Ver 1.3 section 6.5.5 + */ + struct pd_bcdb bcdb[PD_BATT_MAX]; + /* Stores a boolean status for each battery index indicating + * whether we have received a BCDB response for that battery. + */ + bool have_response[PD_BATT_MAX]; + } battery_capabilities; }; /** Structure of message used by TCPCI partner emulator */ @@ -408,6 +424,25 @@ void tcpci_partner_common_send_hard_reset(struct tcpci_partner_data *data); */ void tcpci_partner_common_send_soft_reset(struct tcpci_partner_data *data); +/** + * @brief Send a Get Battery Capabilities request to the TCPM + * + * @param data Pointer to TCPCI partner emulator + * @param battery_index Request capability info on this battery. Must + * be (0 <= battery_index < PD_BATT_MAX) + */ +void tcpci_partner_common_send_get_battery_capabilities( + struct tcpci_partner_data *data, int battery_index); + +/** + * @brief Resets the data structure used for tracking battery capability + * requests and responses. + * + * @param data Emulator state + */ +void tcpci_partner_reset_battery_capability_state( + struct tcpci_partner_data *data); + /** * @brief Start sender response timer for TCPCI_PARTNER_RESPONSE_TIMEOUT_MS. * If @ref tcpci_partner_stop_sender_response_timer wasn't called before -- cgit v1.2.1 From a126286d42cf5238564f5618b67341020e339306 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:03 -0600 Subject: board/adlrvpp_mchp1727/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c881da7eaa5cede3be79e60bf43bddb63063ae9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727966 Reviewed-by: Jeremy Bettis --- board/adlrvpp_mchp1727/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/adlrvpp_mchp1727/board.c b/board/adlrvpp_mchp1727/board.c index 5d850c8e10..4b232999e0 100644 --- a/board/adlrvpp_mchp1727/board.c +++ b/board/adlrvpp_mchp1727/board.c @@ -133,6 +133,6 @@ BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT); /* SPI devices */ const struct spi_device_t spi_devices[] = { - { QMSPI0_PORT, 4, GPIO_QMSPI_CS0}, + { QMSPI0_PORT, 4, GPIO_QMSPI_CS0 }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -- cgit v1.2.1 From 01bfb01a82c1d5cd0623a9c20c1cdebb92696c62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:03 -0600 Subject: board/osiris/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91b5bb7a640e493b192877c4174c13112ca31ad0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728802 Reviewed-by: Jeremy Bettis --- board/osiris/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/osiris/led.c b/board/osiris/led.c index 7c4efdf93f..6ac4852bc2 100644 --- a/board/osiris/led.c +++ b/board/osiris/led.c @@ -21,23 +21,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 01c557447105ab719467e4bda12da28158b5ee15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:42 -0600 Subject: chip/stm32/usart_rx_interrupt-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7f297e0866e0d843a29c4f85f745d3cab2ccad82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729422 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_interrupt-stm32l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/usart_rx_interrupt-stm32l.c b/chip/stm32/usart_rx_interrupt-stm32l.c index a89d474d05..3500fe6fab 100644 --- a/chip/stm32/usart_rx_interrupt-stm32l.c +++ b/chip/stm32/usart_rx_interrupt-stm32l.c @@ -22,8 +22,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); /* * We have to check and clear the overrun error flag on STM32L because -- cgit v1.2.1 From 960d45d43f92dd49b4e90c8ababa923a90899098 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:48 -0600 Subject: driver/tcpm/it83xx_pd.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0dceab6f94a0cee3087bb5f881a1c00c6490cd1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730079 Reviewed-by: Jeremy Bettis --- driver/tcpm/it83xx_pd.h | 567 +++++++++++++++++++++++------------------------- 1 file changed, 273 insertions(+), 294 deletions(-) diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h index 9acd530e3d..c532c10cfa 100644 --- a/driver/tcpm/it83xx_pd.h +++ b/driver/tcpm/it83xx_pd.h @@ -13,202 +13,202 @@ /* USBPD Controller */ #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) -#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port))) +#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port))) -#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0) -#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) -#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6) -#define USBPD_REG_MASK_BMC_PHY BIT(4) -#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3) -#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2) -#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) -#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0) -#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x01) -#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7) -#define USBPD_REG_MASK_SOPP_ENABLE BIT(6) -#define USBPD_REG_MASK_SOP_ENABLE BIT(5) -#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) -#define USBPD_REG_MASK_DISABLE_CC BIT(4) -#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) -#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7) +#define IT83XX_USBPD_GCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0) +#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) +#define USBPD_REG_MASK_TYPE_C_DETECT_RESET BIT(6) +#define USBPD_REG_MASK_BMC_PHY BIT(4) +#define USBPD_REG_MASK_AUTO_SEND_SW_RESET BIT(3) +#define USBPD_REG_MASK_AUTO_SEND_HW_RESET BIT(2) +#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) +#define USBPD_REG_MASK_GLOBAL_ENABLE BIT(0) +#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x01) +#define USBPD_REG_MASK_SOPPP_ENABLE BIT(7) +#define USBPD_REG_MASK_SOPP_ENABLE BIT(6) +#define USBPD_REG_MASK_SOP_ENABLE BIT(5) +#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04) +#define USBPD_REG_MASK_DISABLE_CC BIT(4) +#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05) +#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7) #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6) -#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3) +#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3) #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2) #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT -#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR (BIT(5) | BIT(1)) +#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR (BIT(5) | BIT(1)) #else -#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(1) +#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(1) #endif -#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) -#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) -#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) -#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x08) -#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p)+0x09) -#define IT83XX_USBPD_PDPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x0B) -#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(7) -#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C) -#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14) -#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7) -#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) -#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) -#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) -#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) -#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE BIT(2) -#define USBPD_REG_MASK_MSG_TX_DONE BIT(1) -#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) -#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) -#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18) -#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3) -#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2) -#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2) +#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06) +#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) +#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) +#define IT83XX_USBPD_DFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08) +#define IT83XX_USBPD_UFPVDR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09) +#define IT83XX_USBPD_PDPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0B) +#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(7) +#define IT83XX_USBPD_CCADCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C) +#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14) +#define USBPD_REG_MASK_TYPE_C_DETECT BIT(7) +#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) +#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) +#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) +#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3) +#define USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE BIT(2) +#define USBPD_REG_MASK_MSG_TX_DONE BIT(1) +#define USBPD_REG_MASK_TIMER_TIMEOUT BIT(0) +#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15) +#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18) +#define USBPD_REG_MASK_SW_RESET_TX_STAT BIT(3) +#define USBPD_REG_MASK_TX_BUSY_STAT BIT(2) +#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(2) #ifdef IT83XX_PD_TX_ERROR_STATUS_BIT5 -#define USBPD_REG_MASK_TX_ERR_STAT BIT(5) +#define USBPD_REG_MASK_TX_ERR_STAT BIT(5) #else -#define USBPD_REG_MASK_TX_ERR_STAT BIT(1) +#define USBPD_REG_MASK_TX_ERR_STAT BIT(1) #endif -#define USBPD_REG_MASK_TX_START BIT(0) -#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19) -#define USBPD_REG_MASK_CABLE_ENABLE BIT(7) -#define USBPD_REG_MASK_SEND_HW_RESET BIT(6) -#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) -#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) -#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) -#define USBPD_REG_MASK_HARD_RESET_DECODE BIT(0) -#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p)+0x1C) -#define USBPD_REG_GET_SOP_TYPE_RX(mrsr) (((mrsr) >> 4) & 0x7) -#define USBPD_REG_MASK_RX_MSG_VALID BIT(0) -#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p)+0x1D) -#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p)+0x1E) -#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p)+0x1F) -#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p)+0x20) -#define IT83XX_USBPD_AGTMHLR(p) REG8(IT83XX_USBPD_BASE(p)+0x3C) -#define IT83XX_USBPD_AGTMHHR(p) REG8(IT83XX_USBPD_BASE(p)+0x3D) -#define IT83XX_USBPD_TMHLR(p) REG8(IT83XX_USBPD_BASE(p)+0x3E) -#define IT83XX_USBPD_TMHHR(p) REG8(IT83XX_USBPD_BASE(p)+0x3F) -#define IT83XX_USBPD_RDO0(p) REG32(IT83XX_USBPD_BASE(p)+0x40) -#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p)+0x5E) -#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x60) -#define IT83XX_USBPD_BMCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x64) -#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p)+0x65) -#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67) -#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) -#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4) -#define USBPD_REG_PLUG_OUT_SELECT BIT(3) -#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) -#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) -#define IT83XX_USBPD_PDQSCR(p) REG8(IT83XX_USBPD_BASE(p)+0x70) -#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1) -#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0) -#define IT83XX_USBPD_PD30IR(p) REG8(IT83XX_USBPD_BASE(p)+0x78) -#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4) -#define IT83XX_USBPD_MPD30IR(p) REG8(IT83XX_USBPD_BASE(p)+0x7A) -#define USBPD_REG_MASK_PD30_ISR BIT(7) -#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4) +#define USBPD_REG_MASK_TX_START BIT(0) +#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19) +#define USBPD_REG_MASK_CABLE_ENABLE BIT(7) +#define USBPD_REG_MASK_SEND_HW_RESET BIT(6) +#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(5) +#define IT83XX_USBPD_MTSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A) +#define IT83XX_USBPD_VDMMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B) +#define USBPD_REG_MASK_HARD_RESET_DECODE BIT(0) +#define IT83XX_USBPD_MRSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1C) +#define USBPD_REG_GET_SOP_TYPE_RX(mrsr) (((mrsr) >> 4) & 0x7) +#define USBPD_REG_MASK_RX_MSG_VALID BIT(0) +#define IT83XX_USBPD_PEFSMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x1D) +#define IT83XX_USBPD_PES0R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1E) +#define IT83XX_USBPD_PES1R(p) REG8(IT83XX_USBPD_BASE(p) + 0x1F) +#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x20) +#define IT83XX_USBPD_AGTMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3C) +#define IT83XX_USBPD_AGTMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3D) +#define IT83XX_USBPD_TMHLR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3E) +#define IT83XX_USBPD_TMHHR(p) REG8(IT83XX_USBPD_BASE(p) + 0x3F) +#define IT83XX_USBPD_RDO0(p) REG32(IT83XX_USBPD_BASE(p) + 0x40) +#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x5E) +#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x60) +#define IT83XX_USBPD_BMCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x64) +#define IT83XX_USBPD_PDMHSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x65) +#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67) +#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) +#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR BIT(4) +#define USBPD_REG_PLUG_OUT_SELECT BIT(3) +#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) +#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) +#define IT83XX_USBPD_PDQSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x70) +#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1) +#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0) +#define IT83XX_USBPD_PD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x78) +#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4) +#define IT83XX_USBPD_MPD30IR(p) REG8(IT83XX_USBPD_BASE(p) + 0x7A) +#define USBPD_REG_MASK_PD30_ISR BIT(7) +#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4) #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2) -#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port) * (port))) +#define IT83XX_USBPD_BASE(port) (0x00F03700 + (0x100 * (port) * (port))) -#define IT83XX_USBPD_PDGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0) -#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) -#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR BIT(6) -#define USBPD_REG_MASK_BIST_DATA_MODE BIT(4) -#define USBPD_REG_MASK_AUTO_BIST_RESPONSE BIT(3) -#define USBPD_REG_MASK_TX_MESSAGE_ENABLE BIT(2) -#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) -#define USBPD_REG_MASK_BMC_PHY BIT(0) -#define IT83XX_USBPD_PDCSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x01) -#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p)+0x02) +#define IT83XX_USBPD_PDGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0) +#define USBPD_REG_MASK_SW_RESET_BIT BIT(7) +#define USBPD_REG_MASK_PROTOCOL_STATE_CLEAR BIT(6) +#define USBPD_REG_MASK_BIST_DATA_MODE BIT(4) +#define USBPD_REG_MASK_AUTO_BIST_RESPONSE BIT(3) +#define USBPD_REG_MASK_TX_MESSAGE_ENABLE BIT(2) +#define USBPD_REG_MASK_SNIFFER_MODE BIT(1) +#define USBPD_REG_MASK_BMC_PHY BIT(0) +#define IT83XX_USBPD_PDCSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x01) +#define IT83XX_USBPD_PDMSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x02) #define USBPD_REG_MASK_DISABLE_AUTO_GEN_TX_HEADER BIT(7) -#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(6) -#define IT83XX_USBPD_PDCSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x03) -#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE BIT(6) -#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE BIT(5) -#define USBPD_REG_MASK_SOPPP_RX_ENABLE BIT(2) -#define USBPD_REG_MASK_SOPP_RX_ENABLE BIT(1) -#define USBPD_REG_MASK_SOP_RX_ENABLE BIT(0) -#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p)+0x04) -#define USBPD_REG_MASK_DISABLE_CC BIT(7) -#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(6) -#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) -#define USBPD_REG_MASK_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) -#define USBPD_REG_MASK_CC_SELECT_RP_1A5 BIT(3) -#define USBPD_REG_MASK_CC_SELECT_RP_3A0 BIT(2) -#define USBPD_REG_MASK_CC1_CC2_SELECTION BIT(0) -#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p)+0x05) -#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7) +#define USBPD_REG_MASK_AUTO_FRS_DISABLE BIT(6) +#define IT83XX_USBPD_PDCSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x03) +#define USBPD_REG_MASK_CABLE_RESET_RX_ENABLE BIT(6) +#define USBPD_REG_MASK_HARD_RESET_RX_ENABLE BIT(5) +#define USBPD_REG_MASK_SOPPP_RX_ENABLE BIT(2) +#define USBPD_REG_MASK_SOPP_RX_ENABLE BIT(1) +#define USBPD_REG_MASK_SOP_RX_ENABLE BIT(0) +#define IT83XX_USBPD_CCGCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x04) +#define USBPD_REG_MASK_DISABLE_CC BIT(7) +#define USBPD_REG_MASK_DISABLE_CC_VOL_DETECTOR BIT(6) +#define USBPD_REG_MASK_CC_SELECT_RP_RESERVED (BIT(3) | BIT(2) | BIT(1)) +#define USBPD_REG_MASK_CC_SELECT_RP_DEF (BIT(3) | BIT(2)) +#define USBPD_REG_MASK_CC_SELECT_RP_1A5 BIT(3) +#define USBPD_REG_MASK_CC_SELECT_RP_3A0 BIT(2) +#define USBPD_REG_MASK_CC1_CC2_SELECTION BIT(0) +#define IT83XX_USBPD_CCCSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x05) +#define USBPD_REG_MASK_CC2_DISCONNECT BIT(7) #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6) -#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3) +#define USBPD_REG_MASK_CC1_DISCONNECT BIT(3) #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2) #ifdef IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE -#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) +#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) #else -#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT BIT(1) +#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT BIT(1) #endif -#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) -#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) -#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2) -#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) -#define IT83XX_USBPD_SRCVCRR(p) REG8(IT83XX_USBPD_BASE(p)+0x08) -#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H BIT(5) -#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L BIT(4) -#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H BIT(1) -#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L BIT(0) -#define IT83XX_USBPD_SNKVCRR(p) REG8(IT83XX_USBPD_BASE(p)+0x09) -#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H BIT(6) -#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M BIT(5) -#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L BIT(4) -#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H BIT(2) -#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M BIT(1) -#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L BIT(0) -#define IT83XX_USBPD_PDFSCR(p) REG8(IT83XX_USBPD_BASE(p)+0x0C) -#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1) -#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0) -#define IT83XX_USBPD_IFS(p) REG8(IT83XX_USBPD_BASE(p)+0x12) -#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4) -#define IT83XX_USBPD_MIFS(p) REG8(IT83XX_USBPD_BASE(p)+0x13) -#define USBPD_REG_MASK_FAST_SWAP_ISR BIT(7) -#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4) -#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p)+0x14) -#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) -#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) -#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) -#define USBPD_REG_MASK_TX_ERROR_STAT BIT(3) -#define USBPD_REG_MASK_CABLE_RESET_TX_DONE BIT(2) -#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(1) -#define USBPD_REG_MASK_MSG_TX_DONE BIT(0) -#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p)+0x15) -#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p)+0x18) -#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(7) -#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT BIT(6) -#define USBPD_REG_MASK_TX_NOT_EN_STAT BIT(5) -#define USBPD_REG_MASK_CABLE_RESET BIT(3) -#define USBPD_REG_MASK_SEND_HW_RESET BIT(2) -#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(1) -#define USBPD_REG_MASK_TX_START BIT(0) -#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x19) -#define IT83XX_USBPD_MHSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x1A) -#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE BIT(5) -#define IT83XX_USBPD_MHSR1(p) REG8(IT83XX_USBPD_BASE(p)+0x1B) -#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE BIT(0) -#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p)+0x22) -#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p)+0x42) -#define IT83XX_USBPD_RDO(p) REG32(IT83XX_USBPD_BASE(p)+0x44) -#define IT83XX_USBPD_BMCDR0(p) REG8(IT83XX_USBPD_BASE(p)+0x61) -#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC BIT(5) -#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK BIT(1) -#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p)+0x67) -#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) -#define USBPD_REG_PLUG_OUT_SELECT BIT(6) -#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE BIT(5) -#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE BIT(3) -#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) -#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) -#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p)+0x70) -#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p)+0x73) -#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p)+0x74) +#define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p) + 0x06) +#define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) +#define USBPD_REG_MASK_DISCONNECT_5_1K_CC1_DB BIT(2) +#define USBPD_REG_MASK_DISCONNECT_POWER_CC1 BIT(1) +#define IT83XX_USBPD_SRCVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x08) +#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H BIT(5) +#define USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L BIT(4) +#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H BIT(1) +#define USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L BIT(0) +#define IT83XX_USBPD_SNKVCRR(p) REG8(IT83XX_USBPD_BASE(p) + 0x09) +#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H BIT(6) +#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M BIT(5) +#define USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L BIT(4) +#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H BIT(2) +#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M BIT(1) +#define USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L BIT(0) +#define IT83XX_USBPD_PDFSCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x0C) +#define USBPD_REG_FAST_SWAP_REQUEST_ENABLE BIT(1) +#define USBPD_REG_FAST_SWAP_DETECT_ENABLE BIT(0) +#define IT83XX_USBPD_IFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x12) +#define USBPD_REG_FAST_SWAP_DETECT_STAT BIT(4) +#define IT83XX_USBPD_MIFS(p) REG8(IT83XX_USBPD_BASE(p) + 0x13) +#define USBPD_REG_MASK_FAST_SWAP_ISR BIT(7) +#define USBPD_REG_MASK_FAST_SWAP_DETECT_ISR BIT(4) +#define IT83XX_USBPD_ISR(p) REG8(IT83XX_USBPD_BASE(p) + 0x14) +#define USBPD_REG_MASK_CABLE_RESET_DETECT BIT(6) +#define USBPD_REG_MASK_HARD_RESET_DETECT BIT(5) +#define USBPD_REG_MASK_MSG_RX_DONE BIT(4) +#define USBPD_REG_MASK_TX_ERROR_STAT BIT(3) +#define USBPD_REG_MASK_CABLE_RESET_TX_DONE BIT(2) +#define USBPD_REG_MASK_HARD_RESET_TX_DONE BIT(1) +#define USBPD_REG_MASK_MSG_TX_DONE BIT(0) +#define IT83XX_USBPD_IMR(p) REG8(IT83XX_USBPD_BASE(p) + 0x15) +#define IT83XX_USBPD_MTCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x18) +#define USBPD_REG_MASK_TX_DISCARD_STAT BIT(7) +#define USBPD_REG_MASK_TX_NO_RESPONSE_STAT BIT(6) +#define USBPD_REG_MASK_TX_NOT_EN_STAT BIT(5) +#define USBPD_REG_MASK_CABLE_RESET BIT(3) +#define USBPD_REG_MASK_SEND_HW_RESET BIT(2) +#define USBPD_REG_MASK_SEND_BIST_MODE_2 BIT(1) +#define USBPD_REG_MASK_TX_START BIT(0) +#define IT83XX_USBPD_MTSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x19) +#define IT83XX_USBPD_MHSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x1A) +#define USBPD_REG_MASK_SOP_PORT_DATA_ROLE BIT(5) +#define IT83XX_USBPD_MHSR1(p) REG8(IT83XX_USBPD_BASE(p) + 0x1B) +#define USBPD_REG_MASK_SOP_PORT_POWER_ROLE BIT(0) +#define IT83XX_USBPD_TDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x22) +#define IT83XX_USBPD_RMH(p) REG16(IT83XX_USBPD_BASE(p) + 0x42) +#define IT83XX_USBPD_RDO(p) REG32(IT83XX_USBPD_BASE(p) + 0x44) +#define IT83XX_USBPD_BMCDR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x61) +#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SRC BIT(5) +#define USBPD_REG_MASK_BMC_RX_THRESHOLD_SNK BIT(1) +#define IT83XX_USBPD_TCDCR(p) REG8(IT83XX_USBPD_BASE(p) + 0x67) +#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT BIT(7) +#define USBPD_REG_PLUG_OUT_SELECT BIT(6) +#define USBPD_REG_PD3_0_SNK_TX_OK_DISABLE BIT(5) +#define USBPD_REG_PD3_0_SNK_TX_NG_DISABLE BIT(3) +#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE BIT(1) +#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT BIT(0) +#define IT83XX_USBPD_CCPSR0(p) REG8(IT83XX_USBPD_BASE(p) + 0x70) +#define IT83XX_USBPD_CCPSR3_RISE(p) REG8(IT83XX_USBPD_BASE(p) + 0x73) +#define IT83XX_USBPD_CCPSR4_FALL(p) REG8(IT83XX_USBPD_BASE(p) + 0x74) #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */ /* @@ -216,7 +216,7 @@ * This setting will connect CC pin to internal PD module directly without * applying any GPIO/ALT configuration. */ -#define IT83XX_USBPD_CC_PIN_CONFIG 0x86 +#define IT83XX_USBPD_CC_PIN_CONFIG 0x86 #define IT83XX_USBPD_CC_PIN_CONFIG2 0x06 /* @@ -224,138 +224,117 @@ * detector is enabled and Vconn is dropped below 3.3v (>500us) to avoid * the potential risk of voltage fed back into Vcore. */ -#define IT83XX_USBPD_T_VCONN_BELOW_3_3V 500 /* us */ +#define IT83XX_USBPD_T_VCONN_BELOW_3_3V 500 /* us */ #ifndef CONFIG_USB_PD_TCPM_ITE_ON_CHIP -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 0 +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 0 #endif #define TASK_EVENT_PHY_TX_DONE TASK_EVENT_CUSTOM_BIT(PD_EVENT_FIRST_FREE_BIT) -#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) -#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) -#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) +#define SET_MASK(reg, bit_mask) ((reg) |= (bit_mask)) +#define CLEAR_MASK(reg, bit_mask) ((reg) &= (~(bit_mask))) +#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0) #define IS_MASK_CLEAR(reg, bit_mask) (((reg) & (bit_mask)) == 0) #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) /* macros for set */ -#define USBPD_KICK_TX_START(port) \ - SET_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_TX_START) -#define USBPD_SEND_HARD_RESET(port) \ - SET_MASK(IT83XX_USBPD_MTSR0(port), \ - USBPD_REG_MASK_SEND_HW_RESET) -#define USBPD_SW_RESET(port) \ - SET_MASK(IT83XX_USBPD_GCR(port), \ - USBPD_REG_MASK_SW_RESET_BIT) -#define USBPD_ENABLE_BMC_PHY(port) \ - SET_MASK(IT83XX_USBPD_GCR(port), \ - USBPD_REG_MASK_BMC_PHY) -#define USBPD_DISABLE_BMC_PHY(port) \ - CLEAR_MASK(IT83XX_USBPD_GCR(port), \ - USBPD_REG_MASK_BMC_PHY) -#define USBPD_START(port) \ - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \ - USBPD_REG_MASK_DISABLE_CC) -#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \ - SET_MASK(IT83XX_USBPD_MTSR0(port), \ - USBPD_REG_MASK_SEND_BIST_MODE_2) +#define USBPD_KICK_TX_START(port) \ + SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START) +#define USBPD_SEND_HARD_RESET(port) \ + SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_HW_RESET) +#define USBPD_SW_RESET(port) \ + SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_SW_RESET_BIT) +#define USBPD_ENABLE_BMC_PHY(port) \ + SET_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY) +#define USBPD_DISABLE_BMC_PHY(port) \ + CLEAR_MASK(IT83XX_USBPD_GCR(port), USBPD_REG_MASK_BMC_PHY) +#define USBPD_START(port) \ + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC) +#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \ + SET_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2) #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \ - CLEAR_MASK(IT83XX_USBPD_MTSR0(port), \ - USBPD_REG_MASK_SEND_BIST_MODE_2) -#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \ + CLEAR_MASK(IT83XX_USBPD_MTSR0(port), USBPD_REG_MASK_SEND_BIST_MODE_2) +#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \ (IT83XX_USBPD_PD30IR(port) = USBPD_REG_FAST_SWAP_DETECT_STAT) -#define USBPD_CC1_DISCONNECTED(p) \ +#define USBPD_CC1_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \ - ~USBPD_REG_MASK_CC2_DISCONNECT) -#define USBPD_CC2_DISCONNECTED(p) \ + ~USBPD_REG_MASK_CC2_DISCONNECT) +#define USBPD_CC2_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \ - ~USBPD_REG_MASK_CC1_DISCONNECT) + ~USBPD_REG_MASK_CC1_DISCONNECT) /* macros for get */ -#define USBPD_GET_POWER_ROLE(port) \ - (IT83XX_USBPD_PDMSR(port) & 1) +#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_PDMSR(port) & 1) #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \ (IT83XX_USBPD_CCGCR(port) & BIT(1)) #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \ (IT83XX_USBPD_BMCSR(port) & BIT(3)) -#define USBPD_GET_PULL_CC_SELECTION(port) \ - (IT83XX_USBPD_CCGCR(port) & 1) +#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & 1) /* macros for check */ -#define USBPD_IS_TX_ERR(port) \ +#define USBPD_IS_TX_ERR(port) \ IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_ERR_STAT) -#define USBPD_IS_TX_DISCARD(port) \ +#define USBPD_IS_TX_DISCARD(port) \ IS_MASK_SET(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_DISCARD_STAT) #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2) /* macros for set */ -#define USBPD_SW_RESET(port) \ - SET_MASK(IT83XX_USBPD_PDGCR(port), \ - USBPD_REG_MASK_SW_RESET_BIT) -#define USBPD_ENABLE_BMC_PHY(port) \ - SET_MASK(IT83XX_USBPD_PDGCR(port), \ - USBPD_REG_MASK_BMC_PHY) -#define USBPD_DISABLE_BMC_PHY(port) \ - CLEAR_MASK(IT83XX_USBPD_PDGCR(port), \ - USBPD_REG_MASK_BMC_PHY) -#define USBPD_START(port) \ - CLEAR_MASK(IT83XX_USBPD_CCGCR(port), \ - USBPD_REG_MASK_DISABLE_CC) -#define USBPD_SEND_HARD_RESET(port) \ - SET_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_SEND_HW_RESET) -#define USBPD_SEND_CABLE_RESET(port) \ - SET_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_CABLE_RESET) -#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \ - SET_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_SEND_BIST_MODE_2) +#define USBPD_SW_RESET(port) \ + SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_SW_RESET_BIT) +#define USBPD_ENABLE_BMC_PHY(port) \ + SET_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY) +#define USBPD_DISABLE_BMC_PHY(port) \ + CLEAR_MASK(IT83XX_USBPD_PDGCR(port), USBPD_REG_MASK_BMC_PHY) +#define USBPD_START(port) \ + CLEAR_MASK(IT83XX_USBPD_CCGCR(port), USBPD_REG_MASK_DISABLE_CC) +#define USBPD_SEND_HARD_RESET(port) \ + SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_HW_RESET) +#define USBPD_SEND_CABLE_RESET(port) \ + SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_CABLE_RESET) +#define USBPD_ENABLE_SEND_BIST_MODE_2(port) \ + SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2) #define USBPD_DISABLE_SEND_BIST_MODE_2(port) \ - CLEAR_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_SEND_BIST_MODE_2) -#define USBPD_KICK_TX_START(port) \ - SET_MASK(IT83XX_USBPD_MTCR(port), \ - USBPD_REG_MASK_TX_START) -#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \ + CLEAR_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_SEND_BIST_MODE_2) +#define USBPD_KICK_TX_START(port) \ + SET_MASK(IT83XX_USBPD_MTCR(port), USBPD_REG_MASK_TX_START) +#define USBPD_CLEAR_FRS_DETECT_STATUS(port) \ (IT83XX_USBPD_IFS(port) = USBPD_REG_FAST_SWAP_DETECT_STAT) -#define USBPD_CC1_DISCONNECTED(p) \ +#define USBPD_CC1_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC1_DISCONNECT) & \ - ~USBPD_REG_MASK_CC2_DISCONNECT) -#define USBPD_CC2_DISCONNECTED(p) \ + ~USBPD_REG_MASK_CC2_DISCONNECT) +#define USBPD_CC2_DISCONNECTED(p) \ ((IT83XX_USBPD_CCCSR(p) | USBPD_REG_MASK_CC2_DISCONNECT) & \ - ~USBPD_REG_MASK_CC1_DISCONNECT) + ~USBPD_REG_MASK_CC1_DISCONNECT) /* macros for get */ -#define USBPD_GET_POWER_ROLE(port) \ - (IT83XX_USBPD_MHSR1(port) & BIT(0)) +#define USBPD_GET_POWER_ROLE(port) (IT83XX_USBPD_MHSR1(port) & BIT(0)) #define USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) \ (IT83XX_USBPD_CCCSR(port) & BIT(1)) #define USBPD_GET_CC2_PULL_REGISTER_SELECTION(port) \ (IT83XX_USBPD_CCCSR(port) & BIT(1)) -#define USBPD_GET_PULL_CC_SELECTION(port) \ - (IT83XX_USBPD_CCGCR(port) & BIT(0)) -#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port) \ - (IT83XX_USBPD_SNKVCRR(port) & \ - (USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L | \ - USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M | \ - USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H)) -#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port) \ - ((IT83XX_USBPD_SNKVCRR(port) & \ - (USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L | \ - USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M | \ - USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> 4) -#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port) \ - (IT83XX_USBPD_SRCVCRR(port) & \ - (USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L | \ - USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H)) -#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port) \ - ((IT83XX_USBPD_SRCVCRR(port) & \ - (USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L | \ - USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> 4) +#define USBPD_GET_PULL_CC_SELECTION(port) (IT83XX_USBPD_CCGCR(port) & BIT(0)) +#define USBPD_GET_SNK_COMPARE_CC1_VOLT(port) \ + (IT83XX_USBPD_SNKVCRR(port) & (USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_L | \ + USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_M | \ + USBPD_REG_MASK_SNK_COMPARE_CC1_VOLT_H)) +#define USBPD_GET_SNK_COMPARE_CC2_VOLT(port) \ + ((IT83XX_USBPD_SNKVCRR(port) & \ + (USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_L | \ + USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_M | \ + USBPD_REG_MASK_SNK_COMPARE_CC2_VOLT_H)) >> \ + 4) +#define USBPD_GET_SRC_COMPARE_CC1_VOLT(port) \ + (IT83XX_USBPD_SRCVCRR(port) & (USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_L | \ + USBPD_REG_MASK_SRC_COMPARE_CC1_VOLT_H)) +#define USBPD_GET_SRC_COMPARE_CC2_VOLT(port) \ + ((IT83XX_USBPD_SRCVCRR(port) & \ + (USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_L | \ + USBPD_REG_MASK_SRC_COMPARE_CC2_VOLT_H)) >> \ + 4) /* macros for check */ -#define USBPD_IS_TX_ERR(port) \ +#define USBPD_IS_TX_ERR(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_TX_ERROR_STAT) #endif /* !defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) */ @@ -364,20 +343,20 @@ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_HARD_RESET_DETECT) #define USBPD_IS_HARD_CABLE_RESET_TX_DONE(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), \ - USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE) -#define USBPD_IS_TX_DONE(port) \ + USBPD_REG_MASK_HARD_CABLE_RESET_TX_DONE) +#define USBPD_IS_TX_DONE(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_TX_DONE) -#define USBPD_IS_RX_DONE(port) \ +#define USBPD_IS_RX_DONE(port) \ IS_MASK_SET(IT83XX_USBPD_ISR(port), USBPD_REG_MASK_MSG_RX_DONE) -#define USBPD_IS_PLUG_IN_OUT_DETECT(port)\ +#define USBPD_IS_PLUG_IN_OUT_DETECT(port) \ IS_MASK_SET(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_IN_OUT_DETECT_STAT) -#define USBPD_IS_PLUG_IN(port) \ +#define USBPD_IS_PLUG_IN(port) \ IS_MASK_CLEAR(IT83XX_USBPD_TCDCR(port), USBPD_REG_PLUG_OUT_SELECT) #if defined(CONFIG_USB_PD_TCPM_DRIVER_IT83XX) -#define USBPD_IS_FAST_SWAP_DETECT(port) \ +#define USBPD_IS_FAST_SWAP_DETECT(port) \ IS_MASK_SET(IT83XX_USBPD_PD30IR(port), USBPD_REG_FAST_SWAP_DETECT_STAT) #elif defined(CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2) -#define USBPD_IS_FAST_SWAP_DETECT(port) \ +#define USBPD_IS_FAST_SWAP_DETECT(port) \ IS_MASK_SET(IT83XX_USBPD_IFS(port), USBPD_REG_FAST_SWAP_DETECT_STAT) #endif @@ -385,16 +364,16 @@ /* Use the Zephyr names here. When upstreaming we can update this */ #include -#define IT83XX_GPIO_GPCRF4 GPCRF4 -#define IT83XX_GPIO_GPCRF5 GPCRF5 -#define IT83XX_GPIO_GPCRH1 GPCRH1 -#define IT83XX_GPIO_GPCRH2 GPCRH2 -#define IT83XX_GPIO_GPCRP0 IT8XXX2_GPIO_GPCRP0 -#define IT83XX_GPIO_GPCRP1 IT8XXX2_GPIO_GPCRP1 -#define IT83XX_IRQ_USBPD0 IT8XXX2_IRQ_USBPD0 -#define IT83XX_IRQ_USBPD1 IT8XXX2_IRQ_USBPD1 -#define IT83XX_IRQ_USBPD2 IT8XXX2_IRQ_USBPD2 -#define USB_VID_ITE 0x048d +#define IT83XX_GPIO_GPCRF4 GPCRF4 +#define IT83XX_GPIO_GPCRF5 GPCRF5 +#define IT83XX_GPIO_GPCRH1 GPCRH1 +#define IT83XX_GPIO_GPCRH2 GPCRH2 +#define IT83XX_GPIO_GPCRP0 IT8XXX2_GPIO_GPCRP0 +#define IT83XX_GPIO_GPCRP1 IT8XXX2_GPIO_GPCRP1 +#define IT83XX_IRQ_USBPD0 IT8XXX2_IRQ_USBPD0 +#define IT83XX_IRQ_USBPD1 IT8XXX2_IRQ_USBPD1 +#define IT83XX_IRQ_USBPD2 IT8XXX2_IRQ_USBPD2 +#define USB_VID_ITE 0x048d /* ITE chip supports PD features */ #define IT83XX_INTC_FAST_SWAP_SUPPORT @@ -409,14 +388,14 @@ enum usbpd_port { enum usbpd_ufp_volt_status { USBPD_UFP_STATE_SNK_OPEN = 0, - USBPD_UFP_STATE_SNK_DEF = 1, - USBPD_UFP_STATE_SNK_1_5 = 3, - USBPD_UFP_STATE_SNK_3_0 = 7, + USBPD_UFP_STATE_SNK_DEF = 1, + USBPD_UFP_STATE_SNK_1_5 = 3, + USBPD_UFP_STATE_SNK_3_0 = 7, }; enum usbpd_dfp_volt_status { - USBPD_DFP_STATE_SRC_RA = 0, - USBPD_DFP_STATE_SRC_RD = 1, + USBPD_DFP_STATE_SRC_RA = 0, + USBPD_DFP_STATE_SRC_RD = 1, USBPD_DFP_STATE_SRC_OPEN = 3, }; -- cgit v1.2.1 From a10a1e387a2f1c9f5be6f440d575d23ef29e8e8e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:14 -0600 Subject: board/taniks/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee0dfc6e8adc428270f9f4413322b7c95a6903de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729028 Reviewed-by: Jeremy Bettis --- board/taniks/usbc_config.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/board/taniks/usbc_config.c b/board/taniks/usbc_config.c index 0a1b7ff194..02a67cc5bc 100644 --- a/board/taniks/usbc_config.c +++ b/board/taniks/usbc_config.c @@ -34,13 +34,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #if 0 /* Debug only! */ -#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args) #else #define CPRINTSUSB(format, args...) #define CPRINTFUSB(format, args...) @@ -169,21 +169,20 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + &val) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); else { CPRINTS("delay 10ms to make sure PS8815 is waken from idle"); msleep(10); } - - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + &val) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -209,10 +208,11 @@ static void board_init_ps8815_detection(void) CPRINTSUSB("%s", __func__); - rv = i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x00, &val); + rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00, + &val); - db_usb_hw_pres = (rv == EC_SUCCESS)?DB_USB_PRESENT:DB_USB_NOT_PRESENT; + db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT : + DB_USB_NOT_PRESENT; if (db_usb_hw_pres == DB_USB_NOT_PRESENT) CPRINTS("DB isn't plugged or something went wrong!"); @@ -230,7 +230,7 @@ static bool board_detect_ps8815_db(void) return true; if (ec_cfg_usb_db_type() == DB_USB3_PS8815 && - db_usb_hw_pres == DB_USB_PRESENT) + db_usb_hw_pres == DB_USB_PRESENT) return true; CPRINTSUSB("No PS8815 DB"); @@ -257,8 +257,7 @@ void board_reset_pd_mcu(void) /* * delay for power-on to reset-off and min. assertion time */ - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1); gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1); @@ -274,7 +273,7 @@ void board_reset_pd_mcu(void) */ board_init_ps8815_detection(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } static void board_tcpc_init(void) @@ -385,7 +384,7 @@ __override bool board_is_dts_port(int port) __override uint8_t board_get_usb_pd_port_count(void) { - CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current()); + CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current()); if (board_detect_ps8815_db()) return CONFIG_USB_PD_PORT_MAX_COUNT; -- cgit v1.2.1 From e4b49e618b9ada6efc36491cd3390e3c5405cd69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:53 -0600 Subject: baseboard/kukui/battery_bq27541.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c7402128359d303eca1157c78c07065044579a2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727917 Reviewed-by: Jeremy Bettis --- baseboard/kukui/battery_bq27541.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/baseboard/kukui/battery_bq27541.c b/baseboard/kukui/battery_bq27541.c index 94f46b3326..465b4cea29 100644 --- a/baseboard/kukui/battery_bq27541.c +++ b/baseboard/kukui/battery_bq27541.c @@ -25,12 +25,9 @@ #define BAT_LEVEL_PD_LIMIT 85 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_CPT = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_CPT = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_CPT] = { @@ -105,7 +102,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } @@ -143,7 +140,7 @@ int charger_profile_override(struct charge_state_data *curr) rcv_cycle = 150; /* Check SOH to decrease charging voltage. */ if (!battery_full_charge_capacity(&full_cap) && - !battery_design_capacity(&design_cap)) + !battery_design_capacity(&design_cap)) soh = ((full_cap * 100) / design_cap); if (soh > 70 && soh <= 75) rcv_soh = 50; @@ -159,15 +156,13 @@ int charger_profile_override(struct charge_state_data *curr) curr->requested_voltage -= rcv; /* Should not keep charging voltage > 4250mV for 48hrs. */ - if ((curr->state == ST_DISCHARGE) || - curr->chg.voltage < 4250) { + if ((curr->state == ST_DISCHARGE) || curr->chg.voltage < 4250) { deadline_48.val = 0; - /* Starting count 48hours */ - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { + /* Starting count 48hours */ + } else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) { if (deadline_48.val == 0) deadline_48.val = get_time().val + - CHARGER_LIMIT_TIMEOUT_HOURS * HOUR; + CHARGER_LIMIT_TIMEOUT_HOURS * HOUR; /* If charging voltage keep > 4250 for 48hrs, * set charging voltage = 4250 */ @@ -177,14 +172,13 @@ int charger_profile_override(struct charge_state_data *curr) /* Should not keeep battery voltage > 4100mV and * battery temperature > 45C for two hour */ - if (curr->state == ST_DISCHARGE || - curr->batt.voltage < 4100 || - bat_temp_c < 450) { + if (curr->state == ST_DISCHARGE || curr->batt.voltage < 4100 || + bat_temp_c < 450) { deadline_2.val = 0; - } else if (curr->state == ST_CHARGE || - curr->state == ST_PRECHARGE) { + } else if (curr->state == ST_CHARGE || curr->state == ST_PRECHARGE) { if (deadline_2.val == 0) - deadline_2.val = get_time().val + + deadline_2.val = + get_time().val + CHARGER_LIMIT_TIMEOUT_HOURS_TEMP * HOUR; else if (timestamp_expired(deadline_2, NULL)) { /* Set discharge and charging voltage = 4100mV */ @@ -216,7 +210,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param, int get_battery_manufacturer_name(char *dest, int size) { - static const char * const name[] = { + static const char *const name[] = { [BATTERY_CPT] = "AS1XXXD3Ka", }; ASSERT(dest); -- cgit v1.2.1 From 9a7e943187d62b94476d608f3668d676c6b3feb4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:01 -0600 Subject: board/volmar/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e0d9fd95cd317e19f159c7b4ee05cf83c2a7024 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729077 Reviewed-by: Jeremy Bettis --- board/volmar/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/volmar/i2c.c b/board/volmar/i2c.c index 890a578788..829fb4b0ea 100644 --- a/board/volmar/i2c.c +++ b/board/volmar/i2c.c @@ -8,7 +8,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From 77c666f1fc0d623cd13e89b698ade1e5d7261592 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:52 -0600 Subject: common/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ee9e677b6d2a1d562d671bfbc2c69823293bef7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729599 Reviewed-by: Jeremy Bettis --- common/charger.c | 55 +++++++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/common/charger.c b/common/charger.c index 8dae2e71e8..e29f433509 100644 --- a/common/charger.c +++ b/common/charger.c @@ -18,7 +18,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHARGER, outstr) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* DPTF current limit, -1 = none */ static int dptf_limit_ma = -1; @@ -71,7 +71,7 @@ int charger_closest_voltage(int voltage) int charger_closest_current(int current) { - const struct charger_info * const info = charger_get_info(); + const struct charger_info *const info = charger_get_info(); /* Apply DPTF limit if necessary */ if (dptf_limit_ma >= 0 && current > dptf_limit_ma) @@ -210,41 +210,41 @@ static int command_charger(int argc, char **argv) return EC_SUCCESS; } - if (strcasecmp(argv[1+idx_provided], "input") == 0) { - d = strtoi(argv[2+idx_provided], &e, 0); + if (strcasecmp(argv[1 + idx_provided], "input") == 0) { + d = strtoi(argv[2 + idx_provided], &e, 0); if (*e) - return EC_ERROR_PARAM2+idx_provided; + return EC_ERROR_PARAM2 + idx_provided; return charger_set_input_current_limit(chgnum, d); - } else if (strcasecmp(argv[1+idx_provided], "current") == 0) { - d = strtoi(argv[2+idx_provided], &e, 0); + } else if (strcasecmp(argv[1 + idx_provided], "current") == 0) { + d = strtoi(argv[2 + idx_provided], &e, 0); if (*e) - return EC_ERROR_PARAM2+idx_provided; + return EC_ERROR_PARAM2 + idx_provided; chgstate_set_manual_current(d); return charger_set_current(chgnum, d); - } else if (strcasecmp(argv[1+idx_provided], "voltage") == 0) { - d = strtoi(argv[2+idx_provided], &e, 0); + } else if (strcasecmp(argv[1 + idx_provided], "voltage") == 0) { + d = strtoi(argv[2 + idx_provided], &e, 0); if (*e) - return EC_ERROR_PARAM2+idx_provided; + return EC_ERROR_PARAM2 + idx_provided; chgstate_set_manual_voltage(d); return charger_set_voltage(chgnum, d); - } else if (strcasecmp(argv[1+idx_provided], "dptf") == 0) { - d = strtoi(argv[2+idx_provided], &e, 0); + } else if (strcasecmp(argv[1 + idx_provided], "dptf") == 0) { + d = strtoi(argv[2 + idx_provided], &e, 0); if (*e) - return EC_ERROR_PARAM2+idx_provided; + return EC_ERROR_PARAM2 + idx_provided; dptf_limit_ma = d; return EC_SUCCESS; - } else if (strcasecmp(argv[1+idx_provided], "dump") == 0) { + } else if (strcasecmp(argv[1 + idx_provided], "dump") == 0) { if (!IS_ENABLED(CONFIG_CMD_CHARGER_DUMP) || - !chg_chips[chgnum].drv->dump_registers) { + !chg_chips[chgnum].drv->dump_registers) { ccprintf("dump not supported\n"); - return EC_ERROR_PARAM1+idx_provided; + return EC_ERROR_PARAM1 + idx_provided; } ccprintf("Dump %s registers\n", - chg_chips[chgnum].drv->get_info(chgnum)->name); + chg_chips[chgnum].drv->get_info(chgnum)->name); chg_chips[chgnum].drv->dump_registers(chgnum); return EC_SUCCESS; } else { - return EC_ERROR_PARAM1+idx_provided; + return EC_ERROR_PARAM1 + idx_provided; } } @@ -644,12 +644,16 @@ enum ec_error_list charger_set_hw_ramp(int enable) if (enable) { /* Check if this is the active chg chip. */ if (chgnum == charge_get_active_chg_chip()) - rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 1); - /* This is not the active chg chip, disable hw_ramp. */ + rv = chg_chips[chgnum].drv->set_hw_ramp( + chgnum, 1); + /* This is not the active chg chip, disable + * hw_ramp. */ else - rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 0); + rv = chg_chips[chgnum].drv->set_hw_ramp( + chgnum, 0); } else - rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, 0); + rv = chg_chips[chgnum].drv->set_hw_ramp(chgnum, + 0); } } @@ -705,8 +709,7 @@ int chg_ramp_get_current_limit(void) enum ec_error_list charger_set_vsys_compensation(int chgnum, struct ocpc_data *ocpc, - int current_ma, - int voltage_mv) + int current_ma, int voltage_mv) { if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) { CPRINTS("%s(%d) Invalid charger!", __func__, chgnum); @@ -726,7 +729,7 @@ enum ec_error_list charger_set_vsys_compensation(int chgnum, enum ec_error_list charger_is_icl_reached(int chgnum, bool *reached) { - if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) { + if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) { CPRINTS("%s(%d) Invalid charger!", __func__, chgnum); return EC_ERROR_INVAL; } -- cgit v1.2.1 From beaa8c12bbc9a08f31b6beb0f8a4e8471daec601 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:43 -0600 Subject: driver/charger/bq25710.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieae92239dc24c15c2c9625272986564c0de36740 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729961 Reviewed-by: Jeremy Bettis --- driver/charger/bq25710.c | 145 +++++++++++++++++++++-------------------------- 1 file changed, 64 insertions(+), 81 deletions(-) diff --git a/driver/charger/bq25710.c b/driver/charger/bq25710.c index 1bf9b7cc8a..470fa54b1a 100644 --- a/driver/charger/bq25710.c +++ b/driver/charger/bq25710.c @@ -22,8 +22,7 @@ #include "timer.h" #include "util.h" -#if !defined(CONFIG_CHARGER_BQ25710) && \ - !defined(CONFIG_CHARGER_BQ25720) +#if !defined(CONFIG_CHARGER_BQ25710) && !defined(CONFIG_CHARGER_BQ25720) #error Only the BQ25720 and BQ25710 are supported by bq25710 driver. #endif @@ -32,10 +31,8 @@ #endif #ifndef CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV GET_BQ_FIELD(BQ25720, \ - VMIN_AP, \ - VSYS_TH2, \ - UINT16_MAX) +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV \ + GET_BQ_FIELD(BQ25720, VMIN_AP, VSYS_TH2, UINT16_MAX) #endif #ifndef CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM @@ -69,49 +66,38 @@ * Helper macros */ -#define SET_CO1_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ257X0, \ - CHARGE_OPTION_1, \ - _field, _c, (_x)) +#define SET_CO1_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_1, _field, _c, (_x)) -#define SET_CO2(_field, _v, _x) SET_BQ_FIELD(BQ257X0, \ - CHARGE_OPTION_2, \ - _field, _v, (_x)) +#define SET_CO2(_field, _v, _x) \ + SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, _field, _v, (_x)) -#define SET_CO2_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ257X0, \ - CHARGE_OPTION_2, \ - _field, _c, (_x)) +#define SET_CO2_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_2, _field, _c, (_x)) -#define SET_CO3(_field, _v, _x) SET_BQ_FIELD(BQ257X0, \ - CHARGE_OPTION_3, \ - _field, _v, (_x)) +#define SET_CO3(_field, _v, _x) \ + SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_3, _field, _v, (_x)) -#define SET_CO3_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ257X0, \ - CHARGE_OPTION_3, \ - _field, _c, (_x)) +#define SET_CO3_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ257X0, CHARGE_OPTION_3, _field, _c, (_x)) -#define SET_CO4(_field, _v, _x) SET_BQ_FIELD(BQ25720, \ - CHARGE_OPTION_4, \ - _field, _v, (_x)) +#define SET_CO4(_field, _v, _x) \ + SET_BQ_FIELD(BQ25720, CHARGE_OPTION_4, _field, _v, (_x)) -#define SET_CO4_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ25720, \ - CHARGE_OPTION_4, \ - _field, _c, (_x)) +#define SET_CO4_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ25720, CHARGE_OPTION_4, _field, _c, (_x)) -#define SET_PO0(_field, _v, _x) SET_BQ_FIELD(BQ257X0, \ - PROCHOT_OPTION_0, \ - _field, _v, (_x)) +#define SET_PO0(_field, _v, _x) \ + SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_0, _field, _v, (_x)) -#define SET_PO0_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ257X0, \ - PROCHOT_OPTION_0, \ - _field, _c, (_x)) +#define SET_PO0_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_0, _field, _c, (_x)) -#define SET_PO1(_field, _v, _x) SET_BQ_FIELD(BQ257X0, \ - PROCHOT_OPTION_1, \ - _field, _v, (_x)) +#define SET_PO1(_field, _v, _x) \ + SET_BQ_FIELD(BQ257X0, PROCHOT_OPTION_1, _field, _v, (_x)) -#define SET_PO1_BY_NAME(_field, _c, _x) SET_BQ_FIELD_BY_NAME(BQ257X0, \ - PROCHOT_OPTION_1, \ - _field, _c, (_x)) +#define SET_PO1_BY_NAME(_field, _c, _x) \ + SET_BQ_FIELD_BY_NAME(BQ257X0, PROCHOT_OPTION_1, _field, _c, (_x)) /* * Delay required from taking the bq25710 out of low power mode and having the @@ -124,16 +110,17 @@ /* Sense resistor configurations and macros */ #define DEFAULT_SENSE_RESISTOR 10 -#define REG_TO_CHARGING_CURRENT(REG) ((REG) * \ - DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR) -#define REG_TO_CHARGING_CURRENT_AC(REG) ((REG) * \ - DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC) -#define CHARGING_CURRENT_TO_REG(CUR) ((CUR) * \ - CONFIG_CHARGER_BQ25710_SENSE_RESISTOR / DEFAULT_SENSE_RESISTOR) -#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV) - 32) +#define REG_TO_CHARGING_CURRENT(REG) \ + ((REG)*DEFAULT_SENSE_RESISTOR / CONFIG_CHARGER_BQ25710_SENSE_RESISTOR) +#define REG_TO_CHARGING_CURRENT_AC(REG) \ + ((REG)*DEFAULT_SENSE_RESISTOR / \ + CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC) +#define CHARGING_CURRENT_TO_REG(CUR) \ + ((CUR)*CONFIG_CHARGER_BQ25710_SENSE_RESISTOR / DEFAULT_SENSE_RESISTOR) +#define VMIN_AP_VSYS_TH2_TO_REG(DV) ((DV)-32) /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #ifdef CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA /* @@ -153,15 +140,15 @@ static struct mutex bq25710_perf_mode_mutex; /* Charger parameters */ static const struct charger_info bq25710_charger_info = { - .name = "bq25710", - .voltage_max = 19200, - .voltage_min = 1024, + .name = "bq25710", + .voltage_max = 19200, + .voltage_min = 1024, .voltage_step = 8, - .current_max = REG_TO_CHARGING_CURRENT(8128), - .current_min = REG_TO_CHARGING_CURRENT(64), + .current_max = REG_TO_CHARGING_CURRENT(8128), + .current_min = REG_TO_CHARGING_CURRENT(64), .current_step = REG_TO_CHARGING_CURRENT(64), - .input_current_max = REG_TO_CHARGING_CURRENT_AC(6400), - .input_current_min = REG_TO_CHARGING_CURRENT_AC(50), + .input_current_max = REG_TO_CHARGING_CURRENT_AC(6400), + .input_current_min = REG_TO_CHARGING_CURRENT_AC(50), .input_current_step = REG_TO_CHARGING_CURRENT_AC(50), }; @@ -180,8 +167,8 @@ static inline int iin_dpm_reg_to_current(int reg) if (reg == 0) return BQ25710_IIN_DPM_CODE0_OFFSET; else - return REG_TO_CHARGING_CURRENT_AC(reg * - BQ257X0_IIN_DPM_CURRENT_STEP_MA); + return REG_TO_CHARGING_CURRENT_AC( + reg * BQ257X0_IIN_DPM_CURRENT_STEP_MA); } static inline int iin_host_current_to_reg(int current) @@ -193,8 +180,7 @@ static inline int iin_host_current_to_reg(int current) static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value) { return i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline int min_system_voltage_to_reg(int voltage_mv) @@ -215,8 +201,7 @@ static inline int min_system_voltage_to_reg(int voltage_mv) static inline enum ec_error_list raw_write16(int chgnum, int offset, int value) { return i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } #if defined(CONFIG_CHARGE_RAMP_HW) || \ @@ -312,7 +297,7 @@ static int bq25710_adc_start(int chgnum, int adc_en_mask) * maps to bit[7:0] in ADCOption register. */ reg = (adc_en_mask & BQ257X0_ADC_OPTION_EN_ADC_ALL) | - BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START); + BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START); if (raw_write16(chgnum, BQ25710_REG_ADC_OPTION, reg)) return EC_ERROR_UNKNOWN; @@ -326,8 +311,8 @@ static int bq25710_adc_start(int chgnum, int adc_en_mask) /* sleep 2 ms so we time out after 2x the expected time */ msleep(2); raw_read16(chgnum, BQ25710_REG_ADC_OPTION, ®); - } while (--tries_left && (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION, - ADC_START))); + } while (--tries_left && + (reg & BQ_FIELD_MASK(BQ257X0, ADC_OPTION, ADC_START))); /* ADC reading attempt complete, go back to low power mode */ if (bq25710_set_low_power_mode(chgnum, mode)) @@ -409,8 +394,7 @@ static int bq257x0_init_prochot_option_1(int chgnum) * so the actual IDCHG limit will be the value stored in * IDCHG_VTH + 128 mA. */ - reg = SET_PO1(IDCHG_VTH, - CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA >> 9, + reg = SET_PO1(IDCHG_VTH, CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA >> 9, reg); /* Enable IDCHG trigger for prochot. */ @@ -576,8 +560,8 @@ static void bq25710_init(int chgnum) vsys = min_system_voltage_to_reg( CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV); } else { - rv |= raw_read16(chgnum, - BQ25710_REG_MIN_SYSTEM_VOLTAGE, &vsys); + rv |= raw_read16(chgnum, BQ25710_REG_MIN_SYSTEM_VOLTAGE, + &vsys); } rv |= raw_read16(chgnum, BQ25710_REG_CHARGE_OPTION_3, ®); @@ -694,7 +678,7 @@ static enum ec_error_list bq25710_get_current(int chgnum, int *current) static enum ec_error_list bq25710_set_current(int chgnum, int current) { return raw_write16(chgnum, BQ25710_REG_CHARGE_CURRENT, - CHARGING_CURRENT_TO_REG(current)); + CHARGING_CURRENT_TO_REG(current)); } /* Get/set charge voltage limit in mV */ @@ -749,9 +733,8 @@ static enum ec_error_list bq25710_get_input_current_limit(int chgnum, */ rv = raw_read16(chgnum, BQ25710_REG_IIN_DPM, ®); if (!rv) - *input_current = - iin_dpm_reg_to_current(reg >> - BQ257X0_IIN_DPM_CURRENT_SHIFT); + *input_current = iin_dpm_reg_to_current( + reg >> BQ257X0_IIN_DPM_CURRENT_SHIFT); return rv; } @@ -786,8 +769,9 @@ static int reg_adc_vbus_to_mv(int reg) * LSB => 64mV. * Return 0 when VBUS <= 3.2V as ADC can't measure it. */ - return reg ? - (reg * BQ25710_ADC_VBUS_STEP_MV + BQ25710_ADC_VBUS_BASE_MV) : 0; + return reg ? (reg * BQ25710_ADC_VBUS_STEP_MV + + BQ25710_ADC_VBUS_BASE_MV) : + 0; } #else @@ -799,8 +783,8 @@ static enum ec_error_list bq25710_get_vbus_voltage(int chgnum, int port, { int reg, rv; - rv = bq25710_adc_start(chgnum, BQ_FIELD_MASK(BQ257X0, ADC_OPTION, - EN_ADC_VBUS)); + rv = bq25710_adc_start(chgnum, + BQ_FIELD_MASK(BQ257X0, ADC_OPTION, EN_ADC_VBUS)); if (rv) goto error; @@ -895,7 +879,7 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable) /* Set InputVoltage register to BC1.2 minimum ramp voltage */ rv = raw_write16(chgnum, BQ25710_REG_INPUT_VOLTAGE, - BQ25710_BC12_MIN_VOLTAGE_MV); + BQ25710_BC12_MIN_VOLTAGE_MV); if (rv) return rv; @@ -904,8 +888,8 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable) EN_ICO_MODE, 1, option3_reg); /* 0b: Input current limit is set by BQ25710_REG_IIN_HOST */ - option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, - EN_EXTILIM, 0, option2_reg); + option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM, + 0, option2_reg); /* Charge ramp may take up to 2s to settle down */ hook_call_deferred(&bq25710_chg_ramp_handle_data, (4 * SECOND)); @@ -918,8 +902,8 @@ static enum ec_error_list bq25710_set_hw_ramp(int chgnum, int enable) * 1b: Input current limit is set by the lower value of * ILIM_HIZ pin and BQ25710_REG_IIN_HOST */ - option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, - EN_EXTILIM, 1, option2_reg); + option2_reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_2, EN_EXTILIM, + 1, option2_reg); } rv = raw_write16(chgnum, BQ25710_REG_CHARGE_OPTION_2, option2_reg); @@ -962,7 +946,6 @@ static void bq25710_chipset_startup(void) DECLARE_HOOK(HOOK_CHIPSET_STARTUP, bq25710_chipset_startup, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_RESUME, bq25710_chipset_startup, HOOK_PRIO_DEFAULT); - /* Called on AP S0 -> S0iX/S3 or S3 -> S5 transition */ static void bq25710_chipset_suspend(void) { -- cgit v1.2.1 From 6152dcbd1d90b7828642c36fc55330524b54304b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:10 -0600 Subject: board/servo_v4p1/pi3usb9201.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6d1e66c60eb9f50d4becb25f16588d0dae4f4b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728948 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/pi3usb9201.h | 38 ++++++++++++++++---------------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/board/servo_v4p1/pi3usb9201.h b/board/servo_v4p1/pi3usb9201.h index 826db8b871..34a927b3bf 100644 --- a/board/servo_v4p1/pi3usb9201.h +++ b/board/servo_v4p1/pi3usb9201.h @@ -6,35 +6,29 @@ #ifndef __CROS_EC_PI3USB9201_H #define __CROS_EC_PI3USB9201_H -enum pi3usb9201_reg_t { - CTRL_REG1, - CTRL_REG2, - CLIENT_STATUS, - HOST_STATUS -}; +enum pi3usb9201_reg_t { CTRL_REG1, CTRL_REG2, CLIENT_STATUS, HOST_STATUS }; enum pi3usb9201_dat_t { - POWER_DOWN = 0x0, - SDP_HOST_MODE = 0x2, - DCP_HOST_MODE = 0x4, - CDP_HOST_MODE = 0x6, - CLIENT_MODE = 0x8, - USB_PATH_ON = 0xe + POWER_DOWN = 0x0, + SDP_HOST_MODE = 0x2, + DCP_HOST_MODE = 0x4, + CDP_HOST_MODE = 0x6, + CLIENT_MODE = 0x8, + USB_PATH_ON = 0xe }; - /* Client Status bits */ -#define CS_DCP BIT(7) -#define CS_SDP BIT(6) -#define CS_CDP BIT(5) -#define CS_1A_CHARGER BIT(3) -#define CS_2A_CHARGER BIT(2) -#define CS_2_4A_CHARGER BIT(1) +#define CS_DCP BIT(7) +#define CS_SDP BIT(6) +#define CS_CDP BIT(5) +#define CS_1A_CHARGER BIT(3) +#define CS_2A_CHARGER BIT(2) +#define CS_2_4A_CHARGER BIT(1) /* Host Status bits */ -#define HS_USB_UNPLUGGED BIT(2) -#define HS_USB_PLUGGED BIT(1) -#define HS_BC1_2 BIT(0) +#define HS_USB_UNPLUGGED BIT(2) +#define HS_USB_PLUGGED BIT(1) +#define HS_BC1_2 BIT(0) /** * Selects Client Mode and client mode detection -- cgit v1.2.1 From 533cf5e58e0bc38e4fbd26c73a8c5f9ce512cf5e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:08 -0600 Subject: board/lantis/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie268585bbba345e11f88501c14649d42e1c0e774 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728627 Reviewed-by: Jeremy Bettis --- board/lantis/board.h | 45 +++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/board/lantis/board.h b/board/lantis/board.h index 067ff7eb94..a5f610eb3d 100644 --- a/board/lantis/board.h +++ b/board/lantis/board.h @@ -23,21 +23,22 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -68,8 +69,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -80,8 +81,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -104,21 +105,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; @@ -143,10 +139,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum ec_cfg_keyboard_layout { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1 -}; +enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 8cbae20856ee39c9ea63fcdd63742a7e3550762c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:32 -0600 Subject: common/usb_pd_dual_role.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c5401d35c8deab1f75bd202dd86402292a29341 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729772 Reviewed-by: Jeremy Bettis --- common/usb_pd_dual_role.c | 74 ++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/common/usb_pd_dual_role.c b/common/usb_pd_dual_role.c index a748f8377b..86cf0722ce 100644 --- a/common/usb_pd_dual_role.c +++ b/common/usb_pd_dual_role.c @@ -13,7 +13,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* The macro is used to prevent a DBZ exception while decoding PDOs. */ #define PROCESS_ZERO_DIVISOR(x) ((x) == 0 ? 1 : (x)) @@ -66,8 +66,8 @@ static bool pd_get_usb_comm_capable(int port) * PD_MAX_VOLTAGE_MV and PD_OPERATING_POWER_MW. And in turn, does not * use the following functions. */ -int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps, - int max_mv, uint32_t *selected_pdo) +int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps, + int max_mv, uint32_t *selected_pdo) { int i, uw, mv; int ret = 0; @@ -157,10 +157,10 @@ int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps, mv < cur_mv) prefer_cur = 1; } - /* - * pick the largest power if we don't see one staisfy - * desired power - */ + /* + * pick the largest power if we don't see one + * staisfy desired power + */ } else if (cur_uw == 0 || uw > cur_uw) { prefer_cur = 1; } @@ -225,7 +225,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv, } void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, - uint32_t *mv, int port) + uint32_t *mv, int port) { uint32_t pdo; int pdo_index, flags = 0; @@ -236,7 +236,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, int vpd_vbus_dcr; int vpd_gnd_dcr; uint32_t src_cap_cnt = pd_get_src_cap_cnt(port); - const uint32_t * const src_caps = pd_get_src_caps(port); + const uint32_t *const src_caps = pd_get_src_caps(port); int charging_allowed; int max_request_allowed; uint32_t max_request_mv = pd_get_max_voltage(); @@ -265,8 +265,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, max_request_allowed = 1; if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled()) - max_request_mv = - MIN(max_request_mv, dps_get_dynamic_voltage()); + max_request_mv = MIN(max_request_mv, dps_get_dynamic_voltage()); /* * If currently charging on a different port, or we are not allowed to @@ -275,7 +274,7 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, if (charging_allowed && max_request_allowed) { /* find pdo index for max voltage we can request */ pdo_index = pd_find_pdo_index(src_cap_cnt, src_caps, - max_request_mv, &pdo); + max_request_mv, &pdo); } else { /* src cap 0 should be vSafe5V */ pdo_index = 0; @@ -319,28 +318,28 @@ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, flags |= RDO_CAP_MISMATCH; #ifdef CONFIG_USB_PD_GIVE_BACK - /* Tell source we are give back capable. */ - flags |= RDO_GIVE_BACK; + /* Tell source we are give back capable. */ + flags |= RDO_GIVE_BACK; - /* - * BATTERY PDO: Inform the source that the sink will reduce - * power to this minimum level on receipt of a GotoMin Request. - */ - max_or_min_mw = PD_MIN_POWER_MW; + /* + * BATTERY PDO: Inform the source that the sink will reduce + * power to this minimum level on receipt of a GotoMin Request. + */ + max_or_min_mw = PD_MIN_POWER_MW; - /* - * FIXED or VARIABLE PDO: Inform the source that the sink will - * reduce current to this minimum level on receipt of a GotoMin - * Request. - */ - max_or_min_ma = PD_MIN_CURRENT_MA; + /* + * FIXED or VARIABLE PDO: Inform the source that the sink will + * reduce current to this minimum level on receipt of a GotoMin + * Request. + */ + max_or_min_ma = PD_MIN_CURRENT_MA; #else - /* - * Can't give back, so set maximum current and power to - * operating level. - */ - max_or_min_ma = *ma; - max_or_min_mw = uw / 1000; + /* + * Can't give back, so set maximum current and power to + * operating level. + */ + max_or_min_ma = *ma; + max_or_min_mw = uw / 1000; #endif if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) { @@ -381,8 +380,7 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps) /* Get max power info that we could request */ pd_find_pdo_index(pd_get_src_cap_cnt(port), - pd_get_src_caps(port), - max_mv, &pdo); + pd_get_src_caps(port), max_mv, &pdo); pd_extract_pdo_power(pdo, &ma, &mv, &unused); /* Set max. limit, but apply 500mA ceiling */ @@ -397,8 +395,7 @@ bool pd_is_battery_capable(void) bool capable; /* Battery is present and at some minimum percentage. */ - capable = (usb_get_battery_soc() >= - CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC); + capable = (usb_get_battery_soc() >= CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC); #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT /* @@ -406,9 +403,8 @@ bool pd_is_battery_capable(void) * FET may not be enabled and so attempting being a SRC may cut off * our only power source at the time. */ - capable &= (battery_get_disconnect_state() == - BATTERY_NOT_DISCONNECTED); -#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ + capable &= (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED); +#elif defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ defined(CONFIG_BATTERY_PRESENT_GPIO) /* * When battery is cutoff in ship mode it may not be reliable to @@ -443,7 +439,7 @@ bool pd_is_try_source_capable(void) * therefore allow Try.Src if we're toggling. */ new_try_src = try_src && (charge_manager_get_supplier() == - CHARGE_SUPPLIER_DEDICATED); + CHARGE_SUPPLIER_DEDICATED); #endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */ return new_try_src; -- cgit v1.2.1 From f70d0fa5c7f43feba33d60b6cc9ff04333276366 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:02 -0600 Subject: chip/mec1322/lfw/ec_lfw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I31d366fc85519dbd335048bf9feed7ce5f11d2eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729331 Reviewed-by: Jeremy Bettis --- chip/mec1322/lfw/ec_lfw.c | 47 ++++++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 1fb334e144..ea36466606 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -25,24 +25,23 @@ #include "ec_lfw.h" -__attribute__ ((section(".intvector"))) +__attribute__((section(".intvector"))) const struct int_vector_t hdr_int_vect = { - (void *)0x11FA00, /* init sp, unused, - set by MEC ROM loader*/ - &lfw_main, /* reset vector */ - &fault_handler, /* NMI handler */ - &fault_handler, /* HardFault handler */ - &fault_handler, /* MPU fault handler */ - &fault_handler /* Bus fault handler */ + (void *)0x11FA00, /* init sp, unused, + set by MEC ROM loader*/ + &lfw_main, /* reset vector */ + &fault_handler, /* NMI handler */ + &fault_handler, /* HardFault handler */ + &fault_handler, /* MPU fault handler */ + &fault_handler /* Bus fault handler */ }; /* SPI devices - from glados/board.c*/ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0}, + { CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0 }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - void timer_init() { uint32_t val = 0; @@ -71,17 +70,13 @@ void timer_init() /* Start counting in timer 0 */ MEC1322_TMR32_CTL(0) |= BIT(5); - } -static int spi_flash_readloc(uint8_t *buf_usr, - unsigned int offset, - unsigned int bytes) +static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset, + unsigned int bytes) { - uint8_t cmd[4] = {SPI_FLASH_READ, - (offset >> 16) & 0xFF, - (offset >> 8) & 0xFF, - offset & 0xFF}; + uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF, + (offset >> 8) & 0xFF, offset & 0xFF }; if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; @@ -91,8 +86,8 @@ static int spi_flash_readloc(uint8_t *buf_usr, int spi_image_load(uint32_t offset) { - uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + - CONFIG_PROGRAM_MEMORY_BASE); + uint8_t *buf = + (uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE); uint32_t i; BUILD_ASSERT(CONFIG_RO_SIZE == CONFIG_RW_SIZE); @@ -102,7 +97,6 @@ int spi_image_load(uint32_t offset) spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); return 0; - } void udelay(unsigned us) @@ -129,7 +123,6 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now) return now->le.lo >= deadline.le.lo; } - timestamp_t get_time(void) { timestamp_t ts; @@ -169,12 +162,11 @@ void fault_handler(void) MEC1322_WDG_CTL |= 1; while (1) ; - } void jump_to_image(uintptr_t init_addr) { - void (*resetvec)(void) = (void(*)(void))init_addr; + void (*resetvec)(void) = (void (*)(void))init_addr; resetvec(); } @@ -212,10 +204,8 @@ void uart_init(void) void system_init(void) { - uint32_t wdt_sts = MEC1322_VBAT_STS & MEC1322_VBAT_STS_WDT; - uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & - MEC1322_PWR_RST_STS_VCC1; + uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & MEC1322_PWR_RST_STS_VCC1; if (rst_sts || wdt_sts) MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = EC_IMAGE_RO; @@ -228,11 +218,10 @@ enum ec_image system_get_image_copy(void) void lfw_main() { - uintptr_t init_addr; /* install vector table */ - *((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect; + *((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect; /* Use 48 MHz processor clock to power through boot */ MEC1322_PCR_PROC_CLK_CTL = 1; -- cgit v1.2.1 From 259636e25d8cde7d27d166bde7c8cb8ec3db9bc7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:28 -0600 Subject: baseboard/ite_evb/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3428c269956e879944703632dcf1f40bbd3118b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727907 Reviewed-by: Jeremy Bettis --- baseboard/ite_evb/usb_pd_pdo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/baseboard/ite_evb/usb_pd_pdo.c b/baseboard/ite_evb/usb_pd_pdo.c index 24cbc8b996..0b00fe5a35 100644 --- a/baseboard/ite_evb/usb_pd_pdo.c +++ b/baseboard/ite_evb/usb_pd_pdo.c @@ -7,8 +7,9 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | \ + PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), -- cgit v1.2.1 From 750f622729ecc00e6c6e30101e871a5baf95f929 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:36 -0600 Subject: driver/als_si114x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie11107953516757d886154380c45499b0e707987 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729904 Reviewed-by: Jeremy Bettis --- driver/als_si114x.h | 125 ++++++++++++++++++++++++++-------------------------- 1 file changed, 62 insertions(+), 63 deletions(-) diff --git a/driver/als_si114x.h b/driver/als_si114x.h index 2084c55f09..52424035cc 100644 --- a/driver/als_si114x.h +++ b/driver/als_si114x.h @@ -8,75 +8,75 @@ #ifndef __CROS_EC_ALS_SI114X_H #define __CROS_EC_ALS_SI114X_H -#define SI114X_ADDR_FLAGS 0x5a - -#define SI114X_PART_ID 0x00 -#define SI114X_SEQ_ID 0x02 - -#define SI114X_INT_CFG 0x03 -#define SI114X_INT_CFG_INT_OE BIT(0) - -#define SI114X_IRQ_ENABLE 0x04 -#define SI114X_IRQ_ENABLE_PS3_IE BIT(4) -#define SI114X_IRQ_ENABLE_PS2_IE BIT(3) -#define SI114X_IRQ_ENABLE_PS1_IE BIT(2) -#define SI114X_IRQ_ENABLE_ALS_IE_INT1 BIT(1) -#define SI114X_IRQ_ENABLE_ALS_IE_INT0 BIT(0) - -#define SI114X_HW_KEY 0x07 -#define SI114X_HW_KEY_VALUE 0x17 - -#define SI114X_MEAS_RATE 0x08 -#define SI114X_ALS_RATE 0x09 -#define SI114X_PS_RATE 0x0A - -#define SI114X_PS_LED21 0x0F -#define SI114X_PS_LED3 0x10 -#define SI114X_NUM_LEDS (CONFIG_ALS_SI114X - 0x40) - -#define SI114X_PARAM_WR 0x17 -#define SI114X_COMMAND 0x18 - -#define SI114X_COMMAND_PARAM_QUERY 0x80 -#define SI114X_COMMAND_PARAM_SET 0xA0 -#define SI114X_PARAM_CHLIST 0x01 -#define SI114X_PARAM_CHLIST_EN_ALS_VIS BIT(4) -#define SI114X_PARAM_CHLIST_EN_PS3 BIT(2) -#define SI114X_PARAM_CHLIST_EN_PS2 BIT(1) -#define SI114X_PARAM_CHLIST_EN_PS1 BIT(0) -#define SI114X_PARAM_PS_ADC_COUNTER 0x0A -#define SI114X_PARAM_PS_ADC_GAIN 0x0B -#define SI114X_PARAM_PS_ADC_MISC 0x0C -#define SI114X_PARAM_PS_ADC_MISC_MODE BIT(2) -#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY BIT(2) -#define SI114X_PARAM_ALS_VIS_ADC_COUNTER 0x10 -#define SI114X_PARAM_ALS_VIS_ADC_GAIN 0x11 -#define SI114X_PARAM_ALS_VIS_ADC_MISC 0x12 - -#define SI114X_COMMAND_RESET 0x01 -#define SI114X_COMMAND_PS_FORCE 0x05 -#define SI114X_COMMAND_ALS_FORCE 0x06 - -#define SI114X_IRQ_STATUS 0x21 -#define SI114X_ALS_VIS_DATA0 0x22 - -#define SI114X_PARAM_RD 0x2E +#define SI114X_ADDR_FLAGS 0x5a + +#define SI114X_PART_ID 0x00 +#define SI114X_SEQ_ID 0x02 + +#define SI114X_INT_CFG 0x03 +#define SI114X_INT_CFG_INT_OE BIT(0) + +#define SI114X_IRQ_ENABLE 0x04 +#define SI114X_IRQ_ENABLE_PS3_IE BIT(4) +#define SI114X_IRQ_ENABLE_PS2_IE BIT(3) +#define SI114X_IRQ_ENABLE_PS1_IE BIT(2) +#define SI114X_IRQ_ENABLE_ALS_IE_INT1 BIT(1) +#define SI114X_IRQ_ENABLE_ALS_IE_INT0 BIT(0) + +#define SI114X_HW_KEY 0x07 +#define SI114X_HW_KEY_VALUE 0x17 + +#define SI114X_MEAS_RATE 0x08 +#define SI114X_ALS_RATE 0x09 +#define SI114X_PS_RATE 0x0A + +#define SI114X_PS_LED21 0x0F +#define SI114X_PS_LED3 0x10 +#define SI114X_NUM_LEDS (CONFIG_ALS_SI114X - 0x40) + +#define SI114X_PARAM_WR 0x17 +#define SI114X_COMMAND 0x18 + +#define SI114X_COMMAND_PARAM_QUERY 0x80 +#define SI114X_COMMAND_PARAM_SET 0xA0 +#define SI114X_PARAM_CHLIST 0x01 +#define SI114X_PARAM_CHLIST_EN_ALS_VIS BIT(4) +#define SI114X_PARAM_CHLIST_EN_PS3 BIT(2) +#define SI114X_PARAM_CHLIST_EN_PS2 BIT(1) +#define SI114X_PARAM_CHLIST_EN_PS1 BIT(0) +#define SI114X_PARAM_PS_ADC_COUNTER 0x0A +#define SI114X_PARAM_PS_ADC_GAIN 0x0B +#define SI114X_PARAM_PS_ADC_MISC 0x0C +#define SI114X_PARAM_PS_ADC_MISC_MODE BIT(2) +#define SI114X_PARAM_PS_ADC_MISC_MODE_NORMAL_PROXIMITY BIT(2) +#define SI114X_PARAM_ALS_VIS_ADC_COUNTER 0x10 +#define SI114X_PARAM_ALS_VIS_ADC_GAIN 0x11 +#define SI114X_PARAM_ALS_VIS_ADC_MISC 0x12 + +#define SI114X_COMMAND_RESET 0x01 +#define SI114X_COMMAND_PS_FORCE 0x05 +#define SI114X_COMMAND_ALS_FORCE 0x06 + +#define SI114X_IRQ_STATUS 0x21 +#define SI114X_ALS_VIS_DATA0 0x22 + +#define SI114X_PARAM_RD 0x2E /* Proximity sensor finds an object within 5 cm, disable light sensor */ -#define SI114X_COVERED_THRESHOLD 5 -#define SI114X_OVERFLOW 0xffff +#define SI114X_COVERED_THRESHOLD 5 +#define SI114X_OVERFLOW 0xffff /* Time to wait before re-initializing the device if access is denied */ -#define SI114X_DENIED_THRESHOLD (10 * SECOND) +#define SI114X_DENIED_THRESHOLD (10 * SECOND) /* Delay used for deferred callback when polling is enabled */ #define SI114x_POLLING_DELAY (8 * MSEC) /* Min and Max sampling frequency in mHz */ -#define SI114X_PROX_MIN_FREQ 504 -#define SI114X_PROX_MAX_FREQ 50000 -#define SI114X_LIGHT_MIN_FREQ 504 -#define SI114X_LIGHT_MAX_FREQ 50000 +#define SI114X_PROX_MIN_FREQ 504 +#define SI114X_PROX_MAX_FREQ 50000 +#define SI114X_LIGHT_MIN_FREQ 504 +#define SI114X_LIGHT_MAX_FREQ 50000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= SI114X_PROX_MAX_FREQ) #error "EC too slow for light sensor" #endif @@ -109,12 +109,11 @@ struct si114x_drv_data_t { struct si114x_typed_data_t type_data[2]; }; -#define SI114X_GET_DATA(_s) \ - ((struct si114x_drv_data_t *)(_s)->drv_data) +#define SI114X_GET_DATA(_s) ((struct si114x_drv_data_t *)(_s)->drv_data) #define SI114X_GET_TYPED_DATA(_s) \ (&SI114X_GET_DATA(_s)->type_data[(_s)->type - MOTIONSENSE_TYPE_PROX]) void si114x_interrupt(enum gpio_signal signal); -#endif /* __CROS_EC_ALS_SI114X_H */ +#endif /* __CROS_EC_ALS_SI114X_H */ -- cgit v1.2.1 From 18792bd6eef2f01ced9ac4c916fa4d55a714a327 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:59 -0600 Subject: board/scout/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5cfb474ae99a66d5f9d9b69ef9a467e667d0c01a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728918 Reviewed-by: Jeremy Bettis --- board/scout/board.c | 145 +++++++++++++++++++++++----------------------------- 1 file changed, 65 insertions(+), 80 deletions(-) diff --git a/board/scout/board.c b/board/scout/board.c index ce0ee8ceae..41b7ae48a1 100644 --- a/board/scout/board.c +++ b/board/scout/board.c @@ -37,8 +37,8 @@ #include "usb_common.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Sensors */ @@ -147,14 +147,14 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1603) -#define PWR_FRONT_LOW (5*963) -#define PWR_REAR (5*1075) -#define PWR_HDMI (5*562) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1603) +#define PWR_FRONT_LOW (5 * 963) +#define PWR_REAR (5 * 1075) +#define PWR_HDMI (5 * 562) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -212,69 +212,56 @@ static void port_ocp_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_WHITE] = { .channel = 2, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_WHITE] = { .channel = 2, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "scaler", - .port = I2C_PORT_SCALER, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "scaler", + .port = I2C_PORT_SCALER, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -342,15 +329,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -369,7 +355,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -378,8 +364,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ @@ -398,8 +384,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ @@ -650,23 +636,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1); * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -679,8 +665,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ -- cgit v1.2.1 From 63f733a1a7cce4a856c18c2d54682160a35031eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:19 -0600 Subject: board/magolor/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ica0770c1c66c40303db3029be45c3b08b7059a27 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728650 Reviewed-by: Jeremy Bettis --- board/magolor/board.h | 58 ++++++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 35 deletions(-) diff --git a/board/magolor/board.h b/board/magolor/board.h index 40391d16c6..afb30f3ad8 100644 --- a/board/magolor/board.h +++ b/board/magolor/board.h @@ -36,9 +36,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -59,7 +60,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -98,16 +99,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -125,18 +126,18 @@ #define CONFIG_CMD_ACCEL_INFO #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #ifdef BOARD_MAGOLOR -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ #endif /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -174,25 +175,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, @@ -208,11 +200,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void motion_interrupt(enum gpio_signal signal); void pen_detect_interrupt(enum gpio_signal s); -- cgit v1.2.1 From eabf9ef659b45a744b32646f6b780c038b017ff5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:24 -0600 Subject: include/charge_state_v2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If35dbe7cab1bed2d744538624ba4ad1cf0471691 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730224 Reviewed-by: Jeremy Bettis --- include/charge_state_v2.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h index 547dc6c63d..cdf6872aab 100644 --- a/include/charge_state_v2.h +++ b/include/charge_state_v2.h @@ -117,8 +117,8 @@ void board_base_reset(void); * @param curr Pointer to struct charge_state_data * @return Action to take. */ -enum critical_shutdown board_critical_shutdown_check( - struct charge_state_data *curr); +enum critical_shutdown +board_critical_shutdown_check(struct charge_state_data *curr); /** * Callback to set battery level for shutdown -- cgit v1.2.1 From c61888c116625041054c6f962676cc314c65313f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:08 -0600 Subject: board/asurada/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I57a8bffe91f18be5686509c40bf68730fe52a49f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728013 Reviewed-by: Jeremy Bettis --- board/asurada/usbc_config.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/board/asurada/usbc_config.c b/board/asurada/usbc_config.c index 63552980c3..d826500911 100644 --- a/board/asurada/usbc_config.c +++ b/board/asurada/usbc_config.c @@ -17,16 +17,13 @@ __override int syv682x_board_is_syv682c(int port) void board_usb_mux_init(void) { if (board_get_sub_board() == SUB_BOARD_TYPEC) { - ps8743_tune_usb_eq(&usb_muxes[1], - PS8743_USB_EQ_TX_12_8_DB, + ps8743_tune_usb_eq(&usb_muxes[1], PS8743_USB_EQ_TX_12_8_DB, PS8743_USB_EQ_RX_12_8_DB); - ps8743_write(&usb_muxes[1], - PS8743_REG_HS_DET_THRESHOLD, - PS8743_USB_HS_THRESH_NEG_10); - ps8743_field_update(&usb_muxes[1], - PS8743_REG_DCI_CONFIG_2, - PS8743_AUTO_DCI_MODE_MASK, - PS8743_AUTO_DCI_MODE_FORCE_USB); + ps8743_write(&usb_muxes[1], PS8743_REG_HS_DET_THRESHOLD, + PS8743_USB_HS_THRESH_NEG_10); + ps8743_field_update(&usb_muxes[1], PS8743_REG_DCI_CONFIG_2, + PS8743_AUTO_DCI_MODE_MASK, + PS8743_AUTO_DCI_MODE_FORCE_USB); } } DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); -- cgit v1.2.1 From 853acdea94d075cceee75753a4e7a38174aa6a53 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:45 -0600 Subject: common/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife6b99838a36d4a29b0922be83b95c4c1fe6cd5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729628 Reviewed-by: Jeremy Bettis --- common/fan.c | 80 ++++++++++++++++++++++++++---------------------------------- 1 file changed, 34 insertions(+), 46 deletions(-) diff --git a/common/fan.c b/common/fan.c index 636bec04f9..ee324b5031 100644 --- a/common/fan.c +++ b/common/fan.c @@ -56,7 +56,7 @@ void fan_set_count(int count) * Convert the percentage to a target RPM. We can't simply scale all * the way down to zero because most fans won't turn that slowly, so * we'll map [1,100] => [FAN_MIN,FAN_MAX], and [0] => "off". -*/ + */ int fan_percent_to_rpm(int fan, int pct) { int rpm, max, min; @@ -71,7 +71,7 @@ int fan_percent_to_rpm(int fan, int pct) return rpm; } -#endif /* CONFIG_FAN_RPM_CUSTOM */ +#endif /* CONFIG_FAN_RPM_CUSTOM */ /* The thermal task will only call this function with pct in [0,100]. */ test_mockable void fan_set_percent_needed(int fan, int pct) @@ -94,8 +94,7 @@ test_mockable void fan_set_percent_needed(int fan, int pct) /* If we want to turn and the fans are currently significantly below * the minimum turning speed, we should turn at least as fast as the * necessary start speed instead. */ - if (new_rpm && - actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 && + if (new_rpm && actual_rpm < fans[fan].rpm->rpm_min * 9 / 10 && new_rpm < fans[fan].rpm->rpm_start) new_rpm = fans[fan].rpm->rpm_start; @@ -157,8 +156,7 @@ static int cc_fanauto(int argc, char **argv) set_thermal_control_enabled(fan, 1); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto, - "{fan}", +DECLARE_CONSOLE_COMMAND(fanauto, cc_fanauto, "{fan}", "Enable thermal fan control"); /* Return 0 for off, 1 for on, -1 for unknown */ @@ -178,9 +176,8 @@ static int is_powered(int fan) static int cc_faninfo(int argc, char **argv) { - static const char * const human_status[] = { - "not spinning", "changing", "locked", "frustrated" - }; + static const char *const human_status[] = { "not spinning", "changing", + "locked", "frustrated" }; int tmp, is_pgood; int fan; char leader[20] = ""; @@ -193,11 +190,9 @@ static int cc_faninfo(int argc, char **argv) fan_get_rpm_actual(FAN_CH(fan))); ccprintf("%sTarget: %4d rpm\n", leader, fan_get_rpm_target(FAN_CH(fan))); - ccprintf("%sDuty: %d%%\n", leader, - fan_get_duty(FAN_CH(fan))); + ccprintf("%sDuty: %d%%\n", leader, fan_get_duty(FAN_CH(fan))); tmp = fan_get_status(FAN_CH(fan)); - ccprintf("%sStatus: %d (%s)\n", leader, - tmp, human_status[tmp]); + ccprintf("%sStatus: %d (%s)\n", leader, tmp, human_status[tmp]); ccprintf("%sMode: %s\n", leader, fan_get_rpm_mode(FAN_CH(fan)) ? "rpm" : "duty"); ccprintf("%sAuto: %s\n", leader, @@ -212,9 +207,7 @@ static int cc_faninfo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo, - NULL, - "Print fan info"); +DECLARE_CONSOLE_COMMAND(faninfo, cc_faninfo, NULL, "Print fan info"); static int cc_fanset(int argc, char **argv) { @@ -247,7 +240,7 @@ static int cc_fanset(int argc, char **argv) } rpm = strtoi(rpm_str, &e, 0); - if (*e == '%') { /* Wait, that's a percentage */ + if (*e == '%') { /* Wait, that's a percentage */ ccprintf("Fan rpm given as %d%%\n", rpm); if (rpm < 0) rpm = 0; @@ -273,8 +266,7 @@ static int cc_fanset(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fanset, cc_fanset, - "[fan] (rpm | pct%)", +DECLARE_CONSOLE_COMMAND(fanset, cc_fanset, "[fan] (rpm | pct%)", "Set fan speed"); static int cc_fanduty(int argc, char **argv) @@ -316,8 +308,7 @@ static int cc_fanduty(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty, - "[fan] percent", +DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty, "[fan] percent", "Set fan duty cycle"); /*****************************************************************************/ @@ -326,7 +317,7 @@ DECLARE_CONSOLE_COMMAND(fanduty, cc_fanduty, /* 0-100% if in duty mode. -1 if not */ int dptf_get_fan_duty_target(void) { - int fan = 0; /* TODO(crosbug.com/p/23803) */ + int fan = 0; /* TODO(crosbug.com/p/23803) */ if (fan_count == 0) return -1; @@ -370,8 +361,7 @@ hc_pwm_get_fan_target_rpm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM, - hc_pwm_get_fan_target_rpm, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_FAN_TARGET_RPM, hc_pwm_get_fan_target_rpm, EC_VER_MASK(0)); static enum ec_status @@ -399,7 +389,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args) return EC_RES_ERROR; /* enable the fan if rpm is non-zero */ - set_enabled(fan, (p_v1->rpm > 0) ? 1 :0); + set_enabled(fan, (p_v1->rpm > 0) ? 1 : 0); set_thermal_control_enabled(fan, 0); fan_set_rpm_mode(FAN_CH(fan), 1); @@ -407,8 +397,7 @@ hc_pwm_set_fan_target_rpm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM, - hc_pwm_set_fan_target_rpm, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_TARGET_RPM, hc_pwm_set_fan_target_rpm, EC_VER_MASK(0) | EC_VER_MASK(1)); static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args) @@ -432,8 +421,7 @@ static enum ec_status hc_pwm_set_fan_duty(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY, - hc_pwm_set_fan_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_FAN_DUTY, hc_pwm_set_fan_duty, EC_VER_MASK(0) | EC_VER_MASK(1)); static enum ec_status @@ -457,10 +445,8 @@ hc_thermal_auto_fan_ctrl(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL, - hc_thermal_auto_fan_ctrl, - EC_VER_MASK(0)|EC_VER_MASK(1)); - +DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL, hc_thermal_auto_fan_ctrl, + EC_VER_MASK(0) | EC_VER_MASK(1)); /*****************************************************************************/ /* Hooks */ @@ -471,18 +457,18 @@ DECLARE_HOST_COMMAND(EC_CMD_THERMAL_AUTO_FAN_CTRL, */ BUILD_ASSERT(CONFIG_FANS <= EC_FAN_SPEED_ENTRIES); -#define PWMFAN_SYSJUMP_TAG 0x5046 /* "PF" */ +#define PWMFAN_SYSJUMP_TAG 0x5046 /* "PF" */ #define PWM_HOOK_VERSION 1 /* Saved PWM state across sysjumps */ struct pwm_fan_state { /* TODO(crosbug.com/p/23530): Still treating all fans as one. */ uint16_t rpm; - uint8_t flag; /* FAN_STATE_FLAG_* */ + uint8_t flag; /* FAN_STATE_FLAG_* */ }; /* For struct pwm_fan_state.flag */ -#define FAN_STATE_FLAG_ENABLED BIT(0) -#define FAN_STATE_FLAG_THERMAL BIT(1) +#define FAN_STATE_FLAG_ENABLED BIT(0) +#define FAN_STATE_FLAG_THERMAL BIT(1) static void pwm_fan_init(void) { @@ -500,8 +486,8 @@ static void pwm_fan_init(void) fan_channel_setup(FAN_CH(fan), fans[fan].conf->flags); /* Restore previous state. */ - prev = (const struct pwm_fan_state *) - system_get_jump_tag(PWMFAN_SYSJUMP_TAG, &version, &size); + prev = (const struct pwm_fan_state *)system_get_jump_tag( + PWMFAN_SYSJUMP_TAG, &version, &size); if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev)) { memcpy(&state, prev, sizeof(state)); } else { @@ -513,7 +499,7 @@ static void pwm_fan_init(void) state.flag & FAN_STATE_FLAG_ENABLED); fan_set_rpm_target(FAN_CH(fan), state.rpm); set_thermal_control_enabled( - fan, state.flag & FAN_STATE_FLAG_THERMAL); + fan, state.flag & FAN_STATE_FLAG_THERMAL); } /* Initialize memory-mapped data */ @@ -553,7 +539,7 @@ DECLARE_HOOK(HOOK_SECOND, pwm_fan_second, HOOK_PRIO_DEFAULT); static void pwm_fan_preserve_state(void) { - struct pwm_fan_state state = {0}; + struct pwm_fan_state state = { 0 }; int fan = 0; if (fan_count == 0) @@ -566,8 +552,8 @@ static void pwm_fan_preserve_state(void) state.flag |= FAN_STATE_FLAG_THERMAL; state.rpm = fan_get_rpm_target(FAN_CH(fan)); - system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION, - sizeof(state), &state); + system_add_jump_tag(PWMFAN_SYSJUMP_TAG, PWM_HOOK_VERSION, sizeof(state), + &state); } DECLARE_HOOK(HOOK_SYSJUMP, pwm_fan_preserve_state, HOOK_PRIO_DEFAULT); @@ -578,9 +564,11 @@ static void pwm_fan_control(int enable) /* TODO(crosbug.com/p/23530): Still treating all fans as one. */ for (fan = 0; fan < fan_count; fan++) { set_thermal_control_enabled(fan, enable); - fan_set_rpm_target(FAN_CH(fan), enable ? - fan_percent_to_rpm(FAN_CH(fan), CONFIG_FAN_INIT_SPEED) : - 0); + fan_set_rpm_target( + FAN_CH(fan), + enable ? fan_percent_to_rpm(FAN_CH(fan), + CONFIG_FAN_INIT_SPEED) : + 0); set_enabled(fan, enable); } } -- cgit v1.2.1 From be4438a35dea77df6d9fcd9bf30a3c1c91dbc79d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:25 -0600 Subject: board/collis/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f241a3e018fc9740f0c369b4b131ce268b768f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728173 Reviewed-by: Jeremy Bettis --- board/collis/board.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/board/collis/board.c b/board/collis/board.c index fe308778a4..2a4dfd2b9d 100644 --- a/board/collis/board.c +++ b/board/collis/board.c @@ -41,7 +41,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -76,8 +76,8 @@ static const struct ec_response_keybd_config copano_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &copano_kb; } @@ -92,7 +92,6 @@ union volteer_cbi_fw_config fw_config_defaults = { static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -179,8 +178,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -207,8 +206,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -417,23 +416,22 @@ static void ps8815_reset(int port) } gpio_set_level(ps8xxx_rst_odl, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(ps8xxx_rst_odl, 1); msleep(PS8815_FW_INIT_DELAY_MS); CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__); - if (i2c_read8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -441,8 +439,8 @@ void board_reset_pd_mcu(void) { ps8815_reset(USBC_PORT_C0); usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); ps8815_reset(USBC_PORT_C1); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -- cgit v1.2.1 From df4550e58a58921d0c4daeb84031655d512cc750 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:16 -0600 Subject: chip/stm32/usb_dwc_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a66e547eb44786c7090ca4328f91f65122bfd77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729550 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_console.c | 62 ++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 34 deletions(-) diff --git a/chip/stm32/usb_dwc_console.c b/chip/stm32/usb_dwc_console.c index 0d1340fb83..b979394033 100644 --- a/chip/stm32/usb_dwc_console.c +++ b/chip/stm32/usb_dwc_console.c @@ -17,7 +17,7 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) static int last_tx_ok = 1; @@ -28,31 +28,31 @@ static int is_readonly; /* USB-Serial descriptors */ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_CONSOLE, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, + .iInterface = USB_STR_CONSOLE_NAME, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10, + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x80 | USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk IN */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 10, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk OUT */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 0 }; static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE]; @@ -61,7 +61,6 @@ static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE]; static struct queue const tx_q = QUEUE_NULL(256, uint8_t); static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); - struct dwc_usb_ep ep_console_ctl = { .max_packet = USB_MAX_PACKET_SIZE, .tx_fifo = USB_EP_CONSOLE, @@ -76,8 +75,6 @@ struct dwc_usb_ep ep_console_ctl = { .in_databuffer_max = sizeof(ep_buf_rx), }; - - /* Let the USB HW IN-to-host FIFO transmit some bytes */ static void usb_enable_tx(int len) { @@ -162,9 +159,8 @@ static void con_ep_rx(void) /* Bytes received decrement DOEPTSIZ XFERSIZE */ if (GR_USB_DOEPINT(USB_EP_CONSOLE) & DOEPINT_XFERCOMPL) { ep->out_pending = - ep->max_packet - - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); + ep->max_packet - (GR_USB_DOEPTSIZ(USB_EP_CONSOLE) & + GC_USB_DOEPTSIZ1_XFERSIZE_MASK); } /* Wake up the Rx FIFO handler */ @@ -193,8 +189,8 @@ static void tx_fifo_handler(void) if (!tx_fifo_is_ready()) return; - count = QUEUE_REMOVE_UNITS(&tx_q, - ep->in_databuffer, USB_MAX_PACKET_SIZE); + count = QUEUE_REMOVE_UNITS(&tx_q, ep->in_databuffer, + USB_MAX_PACKET_SIZE); if (count) usb_enable_tx(count); } @@ -232,7 +228,6 @@ static void ep_event(enum usb_ep_event evt) usb_enable_rx(USB_MAX_PACKET_SIZE); } - USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_event); static int usb_wait_console(void) @@ -274,8 +269,7 @@ static int usb_wait_console(void) } static int __tx_char(void *context, int c) { - struct queue *state = - (struct queue *) context; + struct queue *state = (struct queue *)context; if (c == '\n' && __tx_char(state, '\r')) return 1; @@ -308,7 +302,7 @@ int usb_puts(const char *outstr) if (is_readonly) return EC_SUCCESS; - ret = usb_wait_console(); + ret = usb_wait_console(); if (ret) return ret; -- cgit v1.2.1 From 6e7df6418cfb8e82b7a280488f3c38e441801123 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Fri, 24 Jun 2022 18:56:00 +0800 Subject: gimble: fix fan table behavior Gimble have six steps in fan table, so current_level will be 0~5. If we set current_level = 6, it will get un-expected value and set fan rpm to .rpm_max. BUG=b:236589603 BRANCH=brya TEST=verified by thermal team Signed-off-by: Scott Chao Change-Id: Ib818f16e12ed1a2b345b3fa0eadb84f1c4ffad14 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721948 Reviewed-by: caveh jalali --- board/gimble/thermal.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/gimble/thermal.c b/board/gimble/thermal.c index 25e7bf2c00..14797c9dfd 100644 --- a/board/gimble/thermal.c +++ b/board/gimble/thermal.c @@ -17,8 +17,6 @@ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) #define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) - - struct fan_step { /* * Sensor 1~4 trigger point, set -1 if we're not using this @@ -115,9 +113,9 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor) } else if (temp[temp_sensor] > prev_temp[temp_sensor]) { for (i = current_level; i < num_fan_levels; i++) { - if (temp[temp_sensor] > + if (temp[temp_sensor] >= fan_table[i].on[temp_sensor]) - current_level = i + 1; + current_level = i; else break; } -- cgit v1.2.1 From 111e3bf1b6b42a83508c39c59c4ad30d0d0131b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:33 -0600 Subject: chip/stm32/adc-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c08cd46e2d9cf025ffbfc303028237c7e789bc2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729451 Reviewed-by: Jeremy Bettis --- chip/stm32/adc-stm32f3.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 543a44ab1a..66a41a5965 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -16,9 +16,9 @@ #define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ -#define SMPR1_EXPAND(v) ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | \ - ((v) << 12) | ((v) << 15) | ((v) << 18) | \ - ((v) << 21)) +#define SMPR1_EXPAND(v) \ + ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \ + ((v) << 15) | ((v) << 18) | ((v) << 21)) #define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) /* Default ADC sample time = 13.5 cycles */ @@ -215,8 +215,9 @@ int adc_read_channel(enum adc_channel ch) adc_enable_watchdog_no_lock(); mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; } static void adc_init(void) -- cgit v1.2.1 From 82c110fdbb4e2dfd4b36c954e222851767b6b697 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:26 -0600 Subject: board/endeavour/pse.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id3e1593aade861e4a603d5b6072287c79a6bcf51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728295 Reviewed-by: Jeremy Bettis --- board/endeavour/pse.c | 81 +++++++++++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/board/endeavour/pse.c b/board/endeavour/pse.c index 671288ccf5..9983c3fa52 100644 --- a/board/endeavour/pse.c +++ b/board/endeavour/pse.c @@ -18,44 +18,44 @@ #include "timer.h" #include "util.h" -#define LTC4291_I2C_ADDR 0x2C - -#define LTC4291_REG_SUPEVN_COR 0x0B -#define LTC4291_REG_STATPWR 0x10 -#define LTC4291_REG_STATPIN 0x11 -#define LTC4291_REG_OPMD 0x12 -#define LTC4291_REG_DISENA 0x13 -#define LTC4291_REG_DETENA 0x14 -#define LTC4291_REG_DETPB 0x18 -#define LTC4291_REG_PWRPB 0x19 -#define LTC4291_REG_RSTPB 0x1A -#define LTC4291_REG_ID 0x1B -#define LTC4291_REG_DEVID 0x43 -#define LTC4291_REG_HPMD1 0x46 -#define LTC4291_REG_HPMD2 0x4B -#define LTC4291_REG_HPMD3 0x50 -#define LTC4291_REG_HPMD4 0x55 -#define LTC4291_REG_LPWRPB 0x6E - -#define LTC4291_FLD_STATPIN_AUTO BIT(0) -#define LTC4291_FLD_RSTPB_RSTALL BIT(4) - -#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) -#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) -#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) -#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) - -#define LTC4291_OPMD_AUTO 0xFF -#define LTC4291_DISENA_ALL 0x0F -#define LTC4291_DETENA_ALL 0xFF -#define LTC4291_ID 0x64 -#define LTC4291_DEVID 0x38 -#define LTC4291_HPMD_MIN 0x00 -#define LTC4291_HPMD_MAX 0xA8 - -#define LTC4291_PORT_MAX 4 - -#define LTC4291_RESET_DELAY_US (20 * MSEC) +#define LTC4291_I2C_ADDR 0x2C + +#define LTC4291_REG_SUPEVN_COR 0x0B +#define LTC4291_REG_STATPWR 0x10 +#define LTC4291_REG_STATPIN 0x11 +#define LTC4291_REG_OPMD 0x12 +#define LTC4291_REG_DISENA 0x13 +#define LTC4291_REG_DETENA 0x14 +#define LTC4291_REG_DETPB 0x18 +#define LTC4291_REG_PWRPB 0x19 +#define LTC4291_REG_RSTPB 0x1A +#define LTC4291_REG_ID 0x1B +#define LTC4291_REG_DEVID 0x43 +#define LTC4291_REG_HPMD1 0x46 +#define LTC4291_REG_HPMD2 0x4B +#define LTC4291_REG_HPMD3 0x50 +#define LTC4291_REG_HPMD4 0x55 +#define LTC4291_REG_LPWRPB 0x6E + +#define LTC4291_FLD_STATPIN_AUTO BIT(0) +#define LTC4291_FLD_RSTPB_RSTALL BIT(4) + +#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) +#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) +#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) +#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) + +#define LTC4291_OPMD_AUTO 0xFF +#define LTC4291_DISENA_ALL 0x0F +#define LTC4291_DETENA_ALL 0xFF +#define LTC4291_ID 0x64 +#define LTC4291_DEVID 0x38 +#define LTC4291_HPMD_MIN 0x00 +#define LTC4291_HPMD_MAX 0xA8 + +#define LTC4291_PORT_MAX 4 + +#define LTC4291_RESET_DELAY_US (20 * MSEC) #define I2C_PSE_READ(reg, data) \ i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) @@ -63,7 +63,7 @@ #define I2C_PSE_WRITE(reg, data) \ i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static int pse_write_hpmd(int port, int val) { @@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv) else return EC_ERROR_PARAM2; } -DECLARE_CONSOLE_COMMAND(pse, command_pse, - " ", +DECLARE_CONSOLE_COMMAND(pse, command_pse, " ", "Set PSE port power"); static int ec_command_pse_status(int port, uint8_t *status) -- cgit v1.2.1 From 2afdbf343d581fa42b9fa9b7df6c6d771da55859 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:57 -0600 Subject: include/usb_charge.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc8e4d020bbe41adfcb80dd5a83375fb0f1f561f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730429 Reviewed-by: Jeremy Bettis --- include/usb_charge.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/usb_charge.h b/include/usb_charge.h index 135258c7cf..79496aa1d2 100644 --- a/include/usb_charge.h +++ b/include/usb_charge.h @@ -14,7 +14,7 @@ #include "task.h" /* USB charger voltage */ -#define USB_CHARGER_VOLTAGE_MV 5000 +#define USB_CHARGER_VOLTAGE_MV 5000 /* USB charger minimum current */ #define USB_CHARGER_MIN_CURR_MA 500 /* @@ -65,13 +65,13 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode, #define USB_CHARGER_EVENT_BIT(x) TASK_EVENT_CUSTOM_BIT(x) #endif -#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0) -#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1) -#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2) -#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3) -#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4) -#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5) -#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6) +#define USB_CHG_EVENT_BC12 USB_CHARGER_EVENT_BIT(0) +#define USB_CHG_EVENT_VBUS USB_CHARGER_EVENT_BIT(1) +#define USB_CHG_EVENT_INTR USB_CHARGER_EVENT_BIT(2) +#define USB_CHG_EVENT_DR_UFP USB_CHARGER_EVENT_BIT(3) +#define USB_CHG_EVENT_DR_DFP USB_CHARGER_EVENT_BIT(4) +#define USB_CHG_EVENT_CC_OPEN USB_CHARGER_EVENT_BIT(5) +#define USB_CHG_EVENT_MUX USB_CHARGER_EVENT_BIT(6) /* * Define USB_CHG_PORT_TO_TASK_ID() and TASK_ID_TO_USB_CHG_PORT() macros to @@ -80,11 +80,11 @@ int usb_charge_set_mode(int usb_port_id, enum usb_charge_mode mode, */ #ifdef HAS_TASK_USB_CHG_P0 #define USB_CHG_PORT_TO_TASK_ID(port) (TASK_ID_USB_CHG_P0 + (port)) -#define TASK_ID_TO_USB_CHG_PORT(id) ((id) - TASK_ID_USB_CHG_P0) +#define TASK_ID_TO_USB_CHG_PORT(id) ((id)-TASK_ID_USB_CHG_P0) #else #define USB_CHG_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_USB_CHG_PORT(id) 0 -#endif /* HAS_TASK_USB_CHG_P0 */ +#endif /* HAS_TASK_USB_CHG_P0 */ /** * Returns true if the passed port is a power source. @@ -214,4 +214,4 @@ int board_is_sourcing_vbus(int port); */ int board_vbus_sink_enable(int port, int enable); -#endif /* __CROS_EC_USB_CHARGE_H */ +#endif /* __CROS_EC_USB_CHARGE_H */ -- cgit v1.2.1 From 0cb7aa5b745930fa24d5554e3bfbcfb6db0575e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:05 -0600 Subject: cts/common/cts_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic04639838f2be7b1942974e0224d069997011e08 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729740 Reviewed-by: Jeremy Bettis --- cts/common/cts_common.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/cts/common/cts_common.h b/cts/common/cts_common.h index 13a435e655..ec65addf6c 100644 --- a/cts/common/cts_common.h +++ b/cts/common/cts_common.h @@ -10,16 +10,16 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTL(format, args...) CPRINTS("%s:%d: "format, \ - __func__, __LINE__, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTL(format, args...) \ + CPRINTS("%s:%d: " format, __func__, __LINE__, ##args) -#define READ_WAIT_TIME_MS 100 -#define CTS_INTERRUPT_TRIGGER_DELAY_US (250 * MSEC) +#define READ_WAIT_TIME_MS 100 +#define CTS_INTERRUPT_TRIGGER_DELAY_US (250 * MSEC) enum cts_rc { - #include "cts.rc" +#include "cts.rc" }; struct cts_test { @@ -38,7 +38,7 @@ extern const int cts_test_count; * @test: List of tests to run * @name: Name of the test to be printed on EC console */ -void cts_main_loop(const struct cts_test* tests, const char *name); +void cts_main_loop(const struct cts_test *tests, const char *name); /** * Callback function called at the beginning of the main loop -- cgit v1.2.1 From 7f057c74cad21cdb033474580688bc49a8a0ad13 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:08 -0600 Subject: board/moli/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifcb650343a8c638690978169576212ec92471678 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728693 Reviewed-by: Jeremy Bettis --- board/moli/sensors.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/board/moli/sensors.c b/board/moli/sensors.c index 8992b24ac4..7ae3ee2889 100644 --- a/board/moli/sensors.c +++ b/board/moli/sensors.c @@ -51,24 +51,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_SSD] = { - .name = "SSD", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_SSD - }, - [TEMP_SENSOR_2_CPU_VR] = { - .name = "CPU VR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_CPU_VR - }, - [TEMP_SENSOR_4_DIMM] = { - .name = "DIMM", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_DIMM - }, + [TEMP_SENSOR_1_SSD] = { .name = "SSD", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_SSD }, + [TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_CPU_VR }, + [TEMP_SENSOR_4_DIMM] = { .name = "DIMM", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_DIMM }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -82,8 +76,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From 9db2d0a3dd273bbd8895d9763af6791d17925237 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:26 -0600 Subject: driver/temp_sensor/pct2075.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib1abfeba96ade26d6f1cf16f7ef0cbc58954848c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730122 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/pct2075.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/driver/temp_sensor/pct2075.c b/driver/temp_sensor/pct2075.c index a5458c72fb..e74a554186 100644 --- a/driver/temp_sensor/pct2075.c +++ b/driver/temp_sensor/pct2075.c @@ -21,7 +21,7 @@ #define PCT2075_SHIFT1 (16 - PCT2075_RESOLUTION) #define PCT2075_SHIFT2 (PCT2075_RESOLUTION - 8) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) static int temp_mk_local[PCT2075_COUNT]; @@ -35,8 +35,8 @@ static int raw_read16(int sensor, const int offset, int *data_ptr) return EC_ERROR_NOT_POWERED; #endif return i2c_read16(pct2075_sensors[sensor].i2c_port, - pct2075_sensors[sensor].i2c_addr_flags, - offset, data_ptr); + pct2075_sensors[sensor].i2c_addr_flags, offset, + data_ptr); } static int get_reg_temp(int sensor, int *temp_ptr) @@ -90,6 +90,6 @@ DECLARE_HOOK(HOOK_SECOND, pct2075_poll, HOOK_PRIO_TEMP_SENSOR); void pct2075_init(void) { -/* Incase we need to initialize somthing */ + /* Incase we need to initialize somthing */ } DECLARE_HOOK(HOOK_INIT, pct2075_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 49ad0f06984599c7cbdf1da6fdc2a3f49e88e900 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:55 -0600 Subject: test/usb_tcpmv2_compliance.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I748a3f1301bffeee4ea92193154134ad043bf025 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730552 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_compliance.h | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/test/usb_tcpmv2_compliance.h b/test/usb_tcpmv2_compliance.h index 331e3c5ee8..7ed39bcb38 100644 --- a/test/usb_tcpmv2_compliance.h +++ b/test/usb_tcpmv2_compliance.h @@ -22,18 +22,16 @@ enum mock_connect_result { MOCK_CC_DUT_IS_SNK = 1, }; - extern uint32_t rdo; extern uint32_t pdo; extern const struct tcpc_config_t tcpc_config[]; extern const struct usb_mux usb_muxes[]; - -void mock_set_cc(enum mock_connect_result cr, - enum mock_cc_state cc1, enum mock_cc_state cc2); -void mock_set_role(int drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2); +void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1, + enum mock_cc_state cc2); +void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1, + enum tcpc_cc_pull cc2); void mock_set_alert(int alert); uint16_t tcpc_get_alert_status(void); bool vboot_allow_usb_pd(void); @@ -54,20 +52,15 @@ enum pd_rev_type partner_get_pd_rev(void); #define TCPCI_MSG_SOP_ALL -1 void partner_tx_msg_id_reset(int sop); -void partner_send_msg(enum tcpci_msg_type sop, - uint16_t type, - uint16_t cnt, - uint16_t ext, - uint32_t *payload); - +void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt, + uint16_t ext, uint32_t *payload); int handle_attach_expected_msgs(enum pd_data_role data_role); - enum proc_pd_e1_attach { - INITIAL_ATTACH = BIT(0), - ALREADY_ATTACHED = BIT(1), - INITIAL_AND_ALREADY_ATTACHED = INITIAL_ATTACH | ALREADY_ATTACHED + INITIAL_ATTACH = BIT(0), + ALREADY_ATTACHED = BIT(1), + INITIAL_AND_ALREADY_ATTACHED = INITIAL_ATTACH | ALREADY_ATTACHED }; int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach); int proc_pd_e3(void); -- cgit v1.2.1 From 05805cf5e37bd5f8c79241795987b70cb049bf70 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:33 -0600 Subject: zephyr/include/emul/emul_bma255.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie3ee56150b05578cb512b948351d583040bf51bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730718 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_bma255.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/include/emul/emul_bma255.h b/zephyr/include/emul/emul_bma255.h index 158d29cf97..f5414e78b5 100644 --- a/zephyr/include/emul/emul_bma255.h +++ b/zephyr/include/emul/emul_bma255.h @@ -47,16 +47,16 @@ * Axis argument used in @ref bma_emul_set_acc @ref bma_emul_get_acc * @ref bma_emul_set_off and @ref bma_emul_get_off */ -#define BMA_EMUL_AXIS_X 0 -#define BMA_EMUL_AXIS_Y 1 -#define BMA_EMUL_AXIS_Z 2 +#define BMA_EMUL_AXIS_X 0 +#define BMA_EMUL_AXIS_Y 1 +#define BMA_EMUL_AXIS_Z 2 /** * Acceleration 1g in internal emulator units. It is helpful for using * functions @ref bma_emul_set_acc @ref bma_emul_get_acc * @ref bma_emul_set_off and @ref bma_emul_get_off */ -#define BMA_EMUL_1G BIT(10) +#define BMA_EMUL_1G BIT(10) /** * @brief Get pointer to BMA255 emulator using device tree order number. -- cgit v1.2.1 From d0d1cbe7b98f107ff35ab893d0c26054f971b43c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:16 -0600 Subject: include/keyboard_8042.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If7f0a58f87f56f1b4916e8aecb39dfd7a06f8a8e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730294 Reviewed-by: Jeremy Bettis --- include/keyboard_8042.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/keyboard_8042.h b/include/keyboard_8042.h index 6826eb98ac..a2dcaf1ee5 100644 --- a/include/keyboard_8042.h +++ b/include/keyboard_8042.h @@ -59,4 +59,4 @@ void send_aux_data_to_host_interrupt(uint8_t data); */ void send_aux_data_to_device(uint8_t data); -#endif /* __CROS_EC_KEYBOARD_8042_H */ +#endif /* __CROS_EC_KEYBOARD_8042_H */ -- cgit v1.2.1 From 6322d1ed2842c7fdbf1d17c6bceade1d5be82c2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:46 -0600 Subject: driver/charger/bq25710.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3086191751f07776581b5ed378e3c4ac3c93723c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729962 Reviewed-by: Jeremy Bettis --- driver/charger/bq25710.h | 66 ++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/driver/charger/bq25710.h b/driver/charger/bq25710.h index bb1ee1ba99..c02cc3b3a0 100644 --- a/driver/charger/bq25710.h +++ b/driver/charger/bq25710.h @@ -11,57 +11,57 @@ /* SMBUS Interface */ #define BQ25710_SMBUS_ADDR1_FLAGS 0x09 -#define BQ25710_BC12_MIN_VOLTAGE_MV 1408 +#define BQ25710_BC12_MIN_VOLTAGE_MV 1408 /* Registers */ -#define BQ25710_REG_CHARGE_OPTION_0 0x12 -#define BQ25710_REG_CHARGE_CURRENT 0x14 -#define BQ25710_REG_MAX_CHARGE_VOLTAGE 0x15 -#define BQ25710_REG_CHARGER_STATUS 0x20 -#define BQ25710_REG_PROCHOT_STATUS 0x21 -#define BQ25710_REG_IIN_DPM 0x22 -#define BQ25710_REG_ADC_VBUS_PSYS 0x23 -#define BQ25710_REG_ADC_IBAT 0x24 -#define BQ25710_REG_ADC_CMPIN_IIN 0x25 -#define BQ25710_REG_ADC_VSYS_VBAT 0x26 -#define BQ25710_REG_CHARGE_OPTION_1 0x30 -#define BQ25710_REG_CHARGE_OPTION_2 0x31 -#define BQ25710_REG_CHARGE_OPTION_3 0x32 -#define BQ25710_REG_PROCHOT_OPTION_0 0x33 -#define BQ25710_REG_PROCHOT_OPTION_1 0x34 -#define BQ25710_REG_ADC_OPTION 0x35 -#define BQ25720_REG_CHARGE_OPTION_4 0x36 -#define BQ25720_REG_VMIN_ACTIVE_PROTECTION 0x37 -#define BQ25710_REG_OTG_VOLTAGE 0x3B -#define BQ25710_REG_OTG_CURRENT 0x3C -#define BQ25710_REG_INPUT_VOLTAGE 0x3D -#define BQ25710_REG_MIN_SYSTEM_VOLTAGE 0x3E -#define BQ25710_REG_IIN_HOST 0x3F -#define BQ25710_REG_MANUFACTURER_ID 0xFE -#define BQ25710_REG_DEVICE_ADDRESS 0xFF +#define BQ25710_REG_CHARGE_OPTION_0 0x12 +#define BQ25710_REG_CHARGE_CURRENT 0x14 +#define BQ25710_REG_MAX_CHARGE_VOLTAGE 0x15 +#define BQ25710_REG_CHARGER_STATUS 0x20 +#define BQ25710_REG_PROCHOT_STATUS 0x21 +#define BQ25710_REG_IIN_DPM 0x22 +#define BQ25710_REG_ADC_VBUS_PSYS 0x23 +#define BQ25710_REG_ADC_IBAT 0x24 +#define BQ25710_REG_ADC_CMPIN_IIN 0x25 +#define BQ25710_REG_ADC_VSYS_VBAT 0x26 +#define BQ25710_REG_CHARGE_OPTION_1 0x30 +#define BQ25710_REG_CHARGE_OPTION_2 0x31 +#define BQ25710_REG_CHARGE_OPTION_3 0x32 +#define BQ25710_REG_PROCHOT_OPTION_0 0x33 +#define BQ25710_REG_PROCHOT_OPTION_1 0x34 +#define BQ25710_REG_ADC_OPTION 0x35 +#define BQ25720_REG_CHARGE_OPTION_4 0x36 +#define BQ25720_REG_VMIN_ACTIVE_PROTECTION 0x37 +#define BQ25710_REG_OTG_VOLTAGE 0x3B +#define BQ25710_REG_OTG_CURRENT 0x3C +#define BQ25710_REG_INPUT_VOLTAGE 0x3D +#define BQ25710_REG_MIN_SYSTEM_VOLTAGE 0x3E +#define BQ25710_REG_IIN_HOST 0x3F +#define BQ25710_REG_MANUFACTURER_ID 0xFE +#define BQ25710_REG_DEVICE_ADDRESS 0xFF /* ADC conversion time ins ms */ #if defined(CONFIG_CHARGER_BQ25720) -#define BQ25710_ADC_OPTION_ADC_CONV_MS 25 +#define BQ25710_ADC_OPTION_ADC_CONV_MS 25 #elif defined(CONFIG_CHARGER_BQ25710) -#define BQ25710_ADC_OPTION_ADC_CONV_MS 10 +#define BQ25710_ADC_OPTION_ADC_CONV_MS 10 #else #error Only the BQ25720 and BQ25710 are supported by bq25710 driver. #endif /* ADCVBUS/PSYS Register */ #if defined(CONFIG_CHARGER_BQ25720) -#define BQ25720_ADC_VBUS_STEP_MV 96 +#define BQ25720_ADC_VBUS_STEP_MV 96 #elif defined(CONFIG_CHARGER_BQ25710) -#define BQ25710_ADC_VBUS_STEP_MV 64 -#define BQ25710_ADC_VBUS_BASE_MV 3200 +#define BQ25710_ADC_VBUS_STEP_MV 64 +#define BQ25710_ADC_VBUS_BASE_MV 3200 #else #error Only the BQ25720 and BQ25710 are supported by bq25710 driver. #endif /* Min System Voltage Register */ -#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV 256 -#define BQ25720_VSYS_MIN_VOLTAGE_STEP_MV 100 +#define BQ25710_MIN_SYSTEM_VOLTAGE_STEP_MV 256 +#define BQ25720_VSYS_MIN_VOLTAGE_STEP_MV 100 extern const struct charger_drv bq25710_drv; -- cgit v1.2.1 From bc8f5701f751a53b95c67032f98bbae7d39f5d61 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:44 -0600 Subject: board/dojo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I76a3f7411d657598cbd6480263847d6abbff528a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728229 Reviewed-by: Jeremy Bettis --- board/dojo/board.c | 66 ++++++++++++++++++++++++------------------------------ 1 file changed, 29 insertions(+), 37 deletions(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index f539d17d2d..4d7178bfad 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -25,8 +25,8 @@ #include "system.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) uint32_t board_version; @@ -66,17 +66,20 @@ static void board_update_vol_up_key(void) * Set vol up key to T13 for KB_BL_TOGGLE_KEY_PRESENT * and board_version >= 2 */ - set_vol_up_key(vol_up_key_matrix_T13.row, vol_up_key_matrix_T13.col); + set_vol_up_key(vol_up_key_matrix_T13.row, + vol_up_key_matrix_T13.col); } else { /* * Set vol up key to T12 for KB_BL_TOGGLE_KEY_ABSENT * and board_version >= 2 */ - set_vol_up_key(vol_up_key_matrix_T12.row, vol_up_key_matrix_T12.col); + set_vol_up_key(vol_up_key_matrix_T12.row, + vol_up_key_matrix_T12.col); } } else { /* Set vol up key to T13 for board_version < 2 */ - set_vol_up_key(vol_up_key_matrix_T13.row, vol_up_key_matrix_T13.col); + set_vol_up_key(vol_up_key_matrix_T13.row, + vol_up_key_matrix_T13.col); } } @@ -109,23 +112,17 @@ static struct bmi_drv_data_t g_bmi260_data; static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t bmi260_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t bmi260_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -319,8 +316,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* USB Mux */ -static int board_ps8762_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state) { /* Make sure the PS8802 is awake */ RETURN_ERROR(ps8802_i2c_wake(me)); @@ -328,21 +324,18 @@ static int board_ps8762_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - RETURN_ERROR(ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_12DB)); + RETURN_ERROR(ps8802_i2c_field_update16( + me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL, + PS8802_USBEQ_LEVEL_UP_MASK, + PS8802_USBEQ_LEVEL_UP_12DB)); } /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - RETURN_ERROR(ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_9DB)); + RETURN_ERROR(ps8802_i2c_field_update8( + me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL, + PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_9DB)); } return EC_SUCCESS; @@ -350,11 +343,10 @@ static int board_ps8762_mux_set(const struct usb_mux *me, static int board_ps8762_mux_init(const struct usb_mux *me) { - return ps8802_i2c_field_update8( - me, PS8802_REG_PAGE1, - PS8802_REG_DCIRX, - PS8802_AUTO_DCI_MODE_DISABLE | PS8802_FORCE_DCI_MODE, - PS8802_AUTO_DCI_MODE_DISABLE); + return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX, + PS8802_AUTO_DCI_MODE_DISABLE | + PS8802_FORCE_DCI_MODE, + PS8802_AUTO_DCI_MODE_DISABLE); } static int board_anx3443_mux_set(const struct usb_mux *me, -- cgit v1.2.1 From 7fe658ee75e4c6940900aa3539a585f9b08f45e1 Mon Sep 17 00:00:00 2001 From: Zick Wei Date: Thu, 16 Jun 2022 15:24:27 +0800 Subject: agah: update thermal sensor setting Remove unused thermal sensor, and update sensor name. BUG=b:218400524 BRANCH=none TEST=make sure thermal sensor information in EC console. Signed-off-by: Zick Wei Change-Id: Id9fcc19a000fce20129554526296cc480977625d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708627 Reviewed-by: Boris Mittelberg --- board/agah/board.h | 6 ++---- board/agah/gpio.inc | 2 +- board/agah/sensors.c | 47 +++++++++-------------------------------------- 3 files changed, 12 insertions(+), 43 deletions(-) diff --git a/board/agah/board.h b/board/agah/board.h index 0b8253d0cc..559f8b2e08 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -164,17 +164,15 @@ enum adc_channel { ADC_TEMP_SENSOR_1_DDR_SOC, - ADC_TEMP_SENSOR_2_AMBIENT, + ADC_TEMP_SENSOR_2_GPU, ADC_TEMP_SENSOR_3_CHARGER, - ADC_TEMP_SENSOR_4_WWAN, ADC_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_1_DDR_SOC, - TEMP_SENSOR_2_AMBIENT, + TEMP_SENSOR_2_GPU, TEMP_SENSOR_3_CHARGER, - TEMP_SENSOR_4_WWAN, TEMP_SENSOR_COUNT }; diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index 41a8f2a4d8..989e081cb1 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -100,7 +100,6 @@ ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) /* GPIOC4/PWM2, GPI /* ADC alternate functions */ ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0) /* GPIO34/PS2_DAT2/ADC6 */ ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */ -ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0) /* GPIOE1/ADC7 */ /* KB alternate functions */ ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ @@ -129,3 +128,4 @@ UNUSED(PIN(4, 1)) /* GPIO41 */ UNUSED(PIN(5, 0)) /* GPIO50 */ UNUSED(PIN(6, 0)) /* GPIO60 */ UNUSED(PIN(C, 2)) /* GPIOC2 */ +UNUSED(PIN(E, 1)) /* GPIOE1 */ diff --git a/board/agah/sensors.c b/board/agah/sensors.c index b68984c95c..9a1180da80 100644 --- a/board/agah/sensors.c +++ b/board/agah/sensors.c @@ -19,8 +19,8 @@ struct adc_t adc_channels[] = { .factor_div = ADC_READ_MAX + 1, .shift = 0, }, - [ADC_TEMP_SENSOR_2_AMBIENT] = { - .name = "TEMP_AMBIENT", + [ADC_TEMP_SENSOR_2_GPU] = { + .name = "TEMP_GPU", .input_ch = NPCX_ADC_CH1, .factor_mul = ADC_MAX_VOLT, .factor_div = ADC_READ_MAX + 1, @@ -33,13 +33,6 @@ struct adc_t adc_channels[] = { .factor_div = ADC_READ_MAX + 1, .shift = 0, }, - [ADC_TEMP_SENSOR_4_WWAN] = { - .name = "TEMP_WWAN", - .input_ch = NPCX_ADC_CH7, - .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -51,11 +44,11 @@ const struct temp_sensor_t temp_sensors[] = { .read = get_temp_3v3_30k9_47k_4050b, .idx = ADC_TEMP_SENSOR_1_DDR_SOC, }, - [TEMP_SENSOR_2_AMBIENT] = { - .name = "Ambient", + [TEMP_SENSOR_2_GPU] = { + .name = "GPU", .type = TEMP_SENSOR_TYPE_BOARD, .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_AMBIENT, + .idx = ADC_TEMP_SENSOR_2_GPU, }, [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", @@ -63,12 +56,6 @@ const struct temp_sensor_t temp_sensors[] = { .read = get_temp_3v3_30k9_47k_4050b, .idx = ADC_TEMP_SENSOR_3_CHARGER, }, - [TEMP_SENSOR_4_WWAN] = { - .name = "WWAN", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_WWAN, - }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -86,7 +73,7 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -#define THERMAL_AMBIENT \ +#define THERMAL_GPU \ { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ @@ -98,8 +85,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; .temp_fan_off = C_TO_K(35), \ .temp_fan_max = C_TO_K(60), \ } -__maybe_unused static const struct ec_thermal_config thermal_ambient = - THERMAL_AMBIENT; +__maybe_unused static const struct ec_thermal_config thermal_gpu = + THERMAL_GPU; /* * Inductor limits - used for both charger and PP3300 regulator @@ -127,25 +114,9 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient = __maybe_unused static const struct ec_thermal_config thermal_charger = THERMAL_CHARGER; -#define THERMAL_WWAN \ - { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ - }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ - } -__maybe_unused static const struct ec_thermal_config thermal_wwan = - THERMAL_WWAN; - struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, - [TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT, + [TEMP_SENSOR_2_GPU] = THERMAL_GPU, [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, - [TEMP_SENSOR_4_WWAN] = THERMAL_WWAN, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From bc5a5a8f0848bc2161a56d09d8087d2236e3e19a Mon Sep 17 00:00:00 2001 From: Zick Wei Date: Mon, 20 Jun 2022 10:58:37 +0800 Subject: agah: add new adc channel Add adc channel for ADP_TYP, CHARGER_IADP. BUG=b:218400524 BRANCH=none TEST=EC console can read ADP_TYP, CHARGER_IADP through command: adc. Signed-off-by: Zick Wei Change-Id: I3484290303bd19966ce3560b889a8457c360c3e0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711513 Reviewed-by: Boris Mittelberg --- board/agah/board.h | 2 ++ board/agah/gpio.inc | 3 +-- board/agah/sensors.c | 14 ++++++++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/board/agah/board.h b/board/agah/board.h index 559f8b2e08..610d2c8b4b 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -166,6 +166,8 @@ enum adc_channel { ADC_TEMP_SENSOR_1_DDR_SOC, ADC_TEMP_SENSOR_2_GPU, ADC_TEMP_SENSOR_3_CHARGER, + ADC_CHARGER_IADP, + ADC_ADP_TYP, ADC_CH_COUNT }; diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index 989e081cb1..b708231cc4 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -99,7 +99,7 @@ ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) /* GPIOC4/PWM2, GPI /* ADC alternate functions */ ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0) /* GPIO34/PS2_DAT2/ADC6 */ -ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1 */ +ALTERNATE(PIN_MASK(4, 0x36), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L, GPIO45/ADC0, GPIO44/ADC1, GPIO41/ADC4 */ /* KB alternate functions */ ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ @@ -124,7 +124,6 @@ UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ UNUSED(PIN(8, 1)) /* GPIO81 */ UNUSED(PIN(9, 5)) /* GPIO95 */ UNUSED(PIN(7, 3)) /* GPIO73 */ -UNUSED(PIN(4, 1)) /* GPIO41 */ UNUSED(PIN(5, 0)) /* GPIO50 */ UNUSED(PIN(6, 0)) /* GPIO60 */ UNUSED(PIN(C, 2)) /* GPIOC2 */ diff --git a/board/agah/sensors.c b/board/agah/sensors.c index 9a1180da80..fccc85998e 100644 --- a/board/agah/sensors.c +++ b/board/agah/sensors.c @@ -33,6 +33,20 @@ struct adc_t adc_channels[] = { .factor_div = ADC_READ_MAX + 1, .shift = 0, }, + [ADC_CHARGER_IADP] = { + .name = "CHARGER_IADP", + .input_ch = NPCX_ADC_CH3, + .factor_mul = ADC_MAX_VOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + }, + [ADC_ADP_TYP] = { + .name = "ADP_TYP", + .input_ch = NPCX_ADC_CH4, + .factor_mul = ADC_MAX_VOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -- cgit v1.2.1 From 10c0f96f0e13988c8dc1d90a6ca6afe1b8d5ff28 Mon Sep 17 00:00:00 2001 From: Zick Wei Date: Tue, 21 Jun 2022 16:03:53 +0800 Subject: agah: support USBC to 100W BUG=b:215231068 BRANCH=none TEST=verified system can get 100W. Signed-off-by: Zick Wei Change-Id: Id1114a803c3fe78eb218a7b4a641e266d9b04998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716176 Reviewed-by: caveh jalali --- board/agah/board.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/agah/board.h b/board/agah/board.h index 610d2c8b4b..d4ce9f23d1 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -66,12 +66,9 @@ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ #define PD_VCONN_SWAP_DELAY 5000 /* us */ -/* - * Passive USB-C cables only support up to 60W. - */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 #define PD_MAX_VOLTAGE_MV 20000 /* -- cgit v1.2.1 From 812c70c4eed4499c148f9ce428c9058bb312e73e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:08 -0600 Subject: chip/stm32/clock-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c280bc043e29bd0675af189f6f8d15474d17375 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729464 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32f4.c | 106 +++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 52 deletions(-) diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index b30edc1fa2..bc403f8b69 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -21,12 +21,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_HSE, /* High-speed external oscillator */ - OSC_PLL, /* PLL */ + OSC_HSI = 0, /* High-speed internal oscillator */ + OSC_HSE, /* High-speed external oscillator */ + OSC_PLL, /* PLL */ }; /* @@ -35,10 +35,11 @@ enum clock_osc { * A CONFIG may be needed if other boards have different MCO * requirements. */ -#define RCC_CFGR_MCO_CONFIG ((2 << 30) | /* MCO2 <- HSE */ \ - (0 << 27) | /* MCO2 div / 4 */ \ - (6 << 24) | /* MCO1 div / 4 */ \ - (3 << 21)) /* MCO1 <- PLL */ +#define RCC_CFGR_MCO_CONFIG \ + ((2 << 30) | /* MCO2 <- HSE */ \ + (0 << 27) | /* MCO2 div / 4 */ \ + (6 << 24) | /* MCO1 div / 4 */ \ + (3 << 21)) /* MCO1 <- PLL */ #ifdef CONFIG_STM32_CLOCK_HSE_HZ /* RTC clock must 1 Mhz when derived from HSE */ @@ -48,7 +49,6 @@ enum clock_osc { #define RTC_DIV 0 #endif /* CONFIG_STM32_CLOCK_HSE_HZ */ - /* Bus clocks dividers depending on the configuration */ /* * max speed configuration with the PLL ON @@ -56,18 +56,18 @@ enum clock_osc { * For STM32F446: max 45 MHz * For STM32F412: max AHB 100 MHz / APB2 100 Mhz / APB1 50 Mhz */ -#define RCC_CFGR_DIVIDERS_WITH_PLL (RCC_CFGR_MCO_CONFIG | \ - CFGR_RTCPRE(RTC_DIV) | \ - CFGR_PPRE2(STM32F4_APB2_PRE) | \ - CFGR_PPRE1(STM32F4_APB1_PRE) | \ - CFGR_HPRE(STM32F4_AHB_PRE)) +#define RCC_CFGR_DIVIDERS_WITH_PLL \ + (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(RTC_DIV) | \ + CFGR_PPRE2(STM32F4_APB2_PRE) | CFGR_PPRE1(STM32F4_APB1_PRE) | \ + CFGR_HPRE(STM32F4_AHB_PRE)) /* * lower power configuration without the PLL * the frequency will be low (8-24Mhz), we don't want dividers to the * peripheral clocks, put /1 everywhere. */ -#define RCC_CFGR_DIVIDERS_NO_PLL (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | \ - CFGR_PPRE2(0) | CFGR_PPRE1(0) | CFGR_HPRE(0)) +#define RCC_CFGR_DIVIDERS_NO_PLL \ + (RCC_CFGR_MCO_CONFIG | CFGR_RTCPRE(0) | CFGR_PPRE2(0) | \ + CFGR_PPRE1(0) | CFGR_HPRE(0)) /* PLL output frequency */ #define STM32F4_PLL_CLOCK (STM32F4_VCO_CLOCK / STM32F4_PLLP_DIV) @@ -166,8 +166,9 @@ void clock_set_osc(enum clock_osc osc) /* Switch to HSI */ clock_switch_osc(OSC_HSI); /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY_SLOW; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Turn off the PLL1 to save power */ @@ -182,8 +183,9 @@ void clock_set_osc(enum clock_osc osc) /* Switch to HSE */ clock_switch_osc(OSC_HSE); /* optimized flash latency settings for <30Mhz clock (0-WS) */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY_SLOW; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY_SLOW; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Turn off the PLL1 to save power */ @@ -201,8 +203,9 @@ void clock_set_osc(enum clock_osc osc) * Increase flash latency before transition the clock * Use the minimum Wait States value optimized for the platform. */ - STM32_FLASH_ACR = (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) - | STM32_FLASH_ACR_LATENCY; + STM32_FLASH_ACR = + (STM32_FLASH_ACR & ~STM32_FLASH_ACR_LAT_MASK) | + STM32_FLASH_ACR_LATENCY; /* read-back the latency as advised by the Reference Manual */ unused = STM32_FLASH_ACR; /* Switch to PLL */ @@ -247,17 +250,14 @@ static void clock_pll_configure(void) i2sdiv = (vcoclock + (systemclock / 2)) / systemclock; /* Set up PLL */ - STM32_RCC_PLLCFGR = - PLLCFGR_PLLM(plldiv) | - PLLCFGR_PLLN(pllmult) | - PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | + STM32_RCC_PLLCFGR = PLLCFGR_PLLM(plldiv) | PLLCFGR_PLLN(pllmult) | + PLLCFGR_PLLP(STM32F4_PLLP_DIV / 2 - 1) | #if defined(CONFIG_STM32_CLOCK_HSE_HZ) - PLLCFGR_PLLSRC_HSE | + PLLCFGR_PLLSRC_HSE | #else - PLLCFGR_PLLSRC_HSI | + PLLCFGR_PLLSRC_HSI | #endif - PLLCFGR_PLLQ(usbdiv) | - PLLCFGR_PLLR(i2sdiv); + PLLCFGR_PLLQ(usbdiv) | PLLCFGR_PLLR(i2sdiv); } void low_power_init(void); @@ -300,22 +300,23 @@ void clock_enable_module(enum module_id module, int enable) if (enable) { STM32_RCC_AHB2ENR |= STM32_RCC_AHB2ENR_OTGFSEN; STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_OTGHSEN | - STM32_RCC_AHB1ENR_OTGHSULPIEN; + STM32_RCC_AHB1ENR_OTGHSULPIEN; } else { STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_OTGFSEN; STM32_RCC_AHB1ENR &= ~STM32_RCC_AHB1ENR_OTGHSEN & - ~STM32_RCC_AHB1ENR_OTGHSULPIEN; + ~STM32_RCC_AHB1ENR_OTGHSULPIEN; } return; } else if (module == MODULE_I2C) { if (enable) { /* Enable clocks to I2C modules if necessary */ STM32_RCC_APB1ENR |= - STM32_RCC_I2C1EN | STM32_RCC_I2C2EN - | STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; + STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | + STM32_RCC_I2C3EN | STM32_RCC_FMPI2C4EN; STM32_RCC_DCKCFGR2 = - (STM32_RCC_DCKCFGR2 & ~DCKCFGR2_FMPI2C1SEL_MASK) - | DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); + (STM32_RCC_DCKCFGR2 & + ~DCKCFGR2_FMPI2C1SEL_MASK) | + DCKCFGR2_FMPI2C1SEL(FMPI2C1SEL_APB); } else { STM32_RCC_APB1ENR &= ~(STM32_RCC_I2C1EN | STM32_RCC_I2C2EN | @@ -349,12 +350,14 @@ void clock_enable_module(enum module_id module, int enable) int32_t rtcss_to_us(uint32_t rtcss) { - return ((RTC_PREDIV_S - rtcss) * (SECOND/SCALING) / (RTC_FREQ/SCALING)); + return ((RTC_PREDIV_S - rtcss) * (SECOND / SCALING) / + (RTC_FREQ / SCALING)); } uint32_t us_to_rtcss(int32_t us) { - return (RTC_PREDIV_S - (us * (RTC_FREQ/SCALING) / (SECOND/SCALING))); + return (RTC_PREDIV_S - + (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); } void rtc_init(void) @@ -365,8 +368,8 @@ void rtc_init(void) STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_HSE); #else /* RTC clocked from the LSI, ensure first it is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); + wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION, + STM32_RCC_CSR_LSIRDY); STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI); #endif @@ -379,11 +382,10 @@ void rtc_init(void) ; /* Set clock prescalars: Needs two separate writes. */ - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | RTC_PREDIV_S; - STM32_RTC_PRER = - (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) - | (RTC_PREDIV_A << 16); + STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_S_MASK) | + RTC_PREDIV_S; + STM32_RTC_PRER = (STM32_RTC_PRER & ~STM32_RTC_PRER_A_MASK) | + (RTC_PREDIV_A << 16); /* Start RTC timer */ STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; @@ -528,8 +530,9 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, + set_rtc_alarm(0, + next_delay - STOP_MODE_LATENCY - + PLL_LOCK_LATENCY, &rtc_sleep, 0); /* Switch to HSI */ @@ -587,16 +590,15 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Num of prevented sleep: %d\n", - idle_sleep_prevented_cnt); + idle_sleep_prevented_cnt); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_LOW_POWER_IDLE */ -- cgit v1.2.1 From bd6bd3909ef1bfd1fd62a4b525a2a43cb4a1f23c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:27 -0600 Subject: include/driver/mag_bmm150.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic3d9ae47d89bdd2ab537680468241c07a8580b35 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730249 Reviewed-by: Jeremy Bettis --- include/driver/mag_bmm150.h | 146 +++++++++++++++++++++----------------------- 1 file changed, 71 insertions(+), 75 deletions(-) diff --git a/include/driver/mag_bmm150.h b/include/driver/mag_bmm150.h index 9f517f8097..a9136da1e5 100644 --- a/include/driver/mag_bmm150.h +++ b/include/driver/mag_bmm150.h @@ -11,68 +11,68 @@ #include "accelgyro.h" #include "mag_cal.h" -#define BMM150_ADDR0_FLAGS 0x10 -#define BMM150_ADDR1_FLAGS 0x11 -#define BMM150_ADDR2_FLAGS 0x12 -#define BMM150_ADDR3_FLAGS 0x13 - -#define BMM150_CHIP_ID 0x40 -#define BMM150_CHIP_ID_MAJOR 0x32 - -#define BMM150_BASE_DATA 0x42 - -#define BMM150_INT_STATUS 0x4a -#define BMM150_PWR_CTRL 0x4b -#define BMM150_SRST (BIT(7) | BIT(1)) -#define BMM150_PWR_ON BIT(0) - -#define BMM150_OP_CTRL 0x4c -#define BMM150_OP_MODE_OFFSET 1 -#define BMM150_OP_MODE_MASK 3 -#define BMM150_OP_MODE_NORMAL 0x00 -#define BMM150_OP_MODE_FORCED 0x01 -#define BMM150_OP_MODE_SLEEP 0x03 - -#define BMM150_INT_CTRL 0x4d - -#define BMM150_REPXY 0x51 -#define BMM150_LOW_POWER_nXY 3 -#define BMM150_REGULAR_nXY 9 -#define BMM150_ENHANCED_nXY 15 -#define BMM150_HIGH_ACCURACY_nXY 47 -#define BMM150_SPECIAL_nXY 75 -#define BMM150_REPZ 0x52 -#define BMM150_LOW_POWER_nZ 3 -#define BMM150_REGULAR_nZ 15 -#define BMM150_ENHANCED_nZ 27 -#define BMM150_HIGH_ACCURACY_nZ 83 -#define BMM150_SPECIAL_nZ 27 +#define BMM150_ADDR0_FLAGS 0x10 +#define BMM150_ADDR1_FLAGS 0x11 +#define BMM150_ADDR2_FLAGS 0x12 +#define BMM150_ADDR3_FLAGS 0x13 + +#define BMM150_CHIP_ID 0x40 +#define BMM150_CHIP_ID_MAJOR 0x32 + +#define BMM150_BASE_DATA 0x42 + +#define BMM150_INT_STATUS 0x4a +#define BMM150_PWR_CTRL 0x4b +#define BMM150_SRST (BIT(7) | BIT(1)) +#define BMM150_PWR_ON BIT(0) + +#define BMM150_OP_CTRL 0x4c +#define BMM150_OP_MODE_OFFSET 1 +#define BMM150_OP_MODE_MASK 3 +#define BMM150_OP_MODE_NORMAL 0x00 +#define BMM150_OP_MODE_FORCED 0x01 +#define BMM150_OP_MODE_SLEEP 0x03 + +#define BMM150_INT_CTRL 0x4d + +#define BMM150_REPXY 0x51 +#define BMM150_LOW_POWER_nXY 3 +#define BMM150_REGULAR_nXY 9 +#define BMM150_ENHANCED_nXY 15 +#define BMM150_HIGH_ACCURACY_nXY 47 +#define BMM150_SPECIAL_nXY 75 +#define BMM150_REPZ 0x52 +#define BMM150_LOW_POWER_nZ 3 +#define BMM150_REGULAR_nZ 15 +#define BMM150_ENHANCED_nZ 27 +#define BMM150_HIGH_ACCURACY_nZ 83 +#define BMM150_SPECIAL_nZ 27 #define BMM150_REP(_preset, _axis) CONCAT4(BMM150_, _preset, _n, _axis) /* Hidden registers for RHALL calculation */ -#define BMM150_REGA_DIG_X1 0x5d -#define BMM150_REGA_DIG_Y1 0x5e -#define BMM150_REGA_DIG_Z4_LSB 0x62 -#define BMM150_REGA_DIG_Z4_MSB 0x63 -#define BMM150_REGA_DIG_X2 0x64 -#define BMM150_REGA_DIG_Y2 0x65 -#define BMM150_REGA_DIG_Z2_LSB 0x68 -#define BMM150_REGA_DIG_Z2_MSB 0x69 -#define BMM150_REGA_DIG_Z1_LSB 0x6a -#define BMM150_REGA_DIG_Z1_MSB 0x6b +#define BMM150_REGA_DIG_X1 0x5d +#define BMM150_REGA_DIG_Y1 0x5e +#define BMM150_REGA_DIG_Z4_LSB 0x62 +#define BMM150_REGA_DIG_Z4_MSB 0x63 +#define BMM150_REGA_DIG_X2 0x64 +#define BMM150_REGA_DIG_Y2 0x65 +#define BMM150_REGA_DIG_Z2_LSB 0x68 +#define BMM150_REGA_DIG_Z2_MSB 0x69 +#define BMM150_REGA_DIG_Z1_LSB 0x6a +#define BMM150_REGA_DIG_Z1_MSB 0x6b #define BMM150_REGA_DIG_XYZ1_LSB 0x6c #define BMM150_REGA_DIG_XYZ1_MSB 0x6d -#define BMM150_REGA_DIG_Z3_LSB 0x6e -#define BMM150_REGA_DIG_Z3_MSB 0x6f -#define BMM150_REGA_DIG_XY2 0x70 -#define BMM150_REGA_DIG_XY1 0x71 +#define BMM150_REGA_DIG_Z3_LSB 0x6e +#define BMM150_REGA_DIG_Z3_MSB 0x6f +#define BMM150_REGA_DIG_XY2 0x70 +#define BMM150_REGA_DIG_XY1 0x71 /* Overflow */ -#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) -#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) -#define BMM150_OVERFLOW_OUTPUT (0x8000) +#define BMM150_FLIP_OVERFLOW_ADCVAL (-4096) +#define BMM150_HALL_OVERFLOW_ADCVAL (-16384) +#define BMM150_OVERFLOW_OUTPUT (0x8000) /* Min and Max sampling frequency in mHz */ #define BMM150_MAG_MIN_FREQ 781 @@ -84,8 +84,9 @@ * * To be safe, declare only 75% of the value. */ -#define __BMM150_MAG_MAX_FREQ(_preset) (750000000 / \ - (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) +#define __BMM150_MAG_MAX_FREQ(_preset) \ + (750000000 / \ + (145 * BMM150_REP(_preset, XY) + 500 * BMM150_REP(_preset, Z) + 980)) #if (__BMM150_MAG_MAX_FREQ(SPECIAL) > CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ) #error "EC too slow for magnetometer" @@ -93,34 +94,32 @@ struct bmm150_comp_registers { /* Local copy of the compensation registers. */ - int8_t dig1[2]; - int8_t dig2[2]; + int8_t dig1[2]; + int8_t dig2[2]; - uint16_t dig_z1; - int16_t dig_z2; - int16_t dig_z3; - int16_t dig_z4; + uint16_t dig_z1; + int16_t dig_z2; + int16_t dig_z3; + int16_t dig_z4; - uint8_t dig_xy1; - int8_t dig_xy2; + uint8_t dig_xy1; + int8_t dig_xy2; - uint16_t dig_xyz1; + uint16_t dig_xyz1; }; struct bmm150_private_data { /* lsm6dsm_data union requires cal be first element */ - struct mag_cal_t cal; + struct mag_cal_t cal; struct bmm150_comp_registers comp; }; #ifdef CONFIG_MAG_BMI_BMM150 #include "accelgyro_bmi_common.h" -#define BMM150_COMP_REG(_s) \ - (&BMI_GET_DATA(_s)->compass.comp) +#define BMM150_COMP_REG(_s) (&BMI_GET_DATA(_s)->compass.comp) -#define BMM150_CAL(_s) \ - (&BMI_GET_DATA(_s)->compass.cal) +#define BMM150_CAL(_s) (&BMI_GET_DATA(_s)->compass.cal) /* * Behind a BMI, the BMM150 is in forced mode. Be sure to choose a frequency * compatible with BMI. @@ -137,14 +136,11 @@ struct bmm150_private_data { int bmm150_init(struct motion_sensor_t *s); /* Command to normalize and apply temperature compensation */ -void bmm150_normalize(const struct motion_sensor_t *s, - intv3_t v, +void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data); -int bmm150_set_offset(const struct motion_sensor_t *s, - const intv3_t offset); +int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset); -int bmm150_get_offset(const struct motion_sensor_t *s, - intv3_t offset); +int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset); #endif /* __CROS_EC_MAG_BMM150_H */ -- cgit v1.2.1 From 17972ba985835cfc44e8734d490e18df8947c2af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:48 -0600 Subject: board/lindar/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf5e541da2a1c64a4a4675cc792518c91089eb4a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728625 Reviewed-by: Jeremy Bettis --- board/lindar/battery.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/lindar/battery.c b/board/lindar/battery.c index 533db6ae0d..e12d521dab 100644 --- a/board/lindar/battery.c +++ b/board/lindar/battery.c @@ -129,7 +129,9 @@ __override bool board_battery_is_initialized(void) bool batt_initialization_state; int batt_status; - batt_initialization_state = (battery_status(&batt_status) ? false : - !!(batt_status & STATUS_INITIALIZED)); + batt_initialization_state = + (battery_status(&batt_status) ? + false : + !!(batt_status & STATUS_INITIALIZED)); return batt_initialization_state; } -- cgit v1.2.1 From 344ce34306d01d62e40cb1e9bcd4b409f3db1938 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:26 -0600 Subject: board/dalboz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1017706d3783cedff0455e2e464fd91199945889 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728194 Reviewed-by: Jeremy Bettis --- board/dalboz/board.h | 91 +++++++++++++++++++--------------------------------- 1 file changed, 33 insertions(+), 58 deletions(-) diff --git a/board/dalboz/board.h b/board/dalboz/board.h index bcb60bda0b..8c8bf241b5 100644 --- a/board/dalboz/board.h +++ b/board/dalboz/board.h @@ -40,42 +40,36 @@ #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL - - /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ /* This I2C moved. Temporarily detect and support the V0 HW. */ extern int I2C_PORT_BATTERY; -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_SMP, @@ -84,10 +78,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; enum ioex_port { IOEX_C0_NCT3807 = 0, @@ -96,9 +87,7 @@ enum ioex_port { IOEX_PORT_COUNT }; -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB3_C0_DP2_HPD \ - : GPIO_DP1_HPD) +#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD) enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -107,17 +96,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -166,31 +147,25 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBC1 \ - (BIT(DALBOZ_DB_D_OPT1_USBAC)) +#define HAS_USBC1 (BIT(DALBOZ_DB_D_OPT1_USBAC)) static inline bool ec_config_has_usbc1(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1); } -#define HAS_USBC1_RETIMER_PS8740 \ - (BIT(DALBOZ_DB_D_OPT1_USBAC)) +#define HAS_USBC1_RETIMER_PS8740 (BIT(DALBOZ_DB_D_OPT1_USBAC)) static inline bool ec_config_has_usbc1_retimer_ps8740(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8740); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8740); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(DALBOZ_DB_D_OPT2_USBA_HDMI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(DALBOZ_DB_D_OPT2_USBA_HDMI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } /* These IO expander GPIOs vary with DB option. */ -- cgit v1.2.1 From 9d0a88a58dd341e525402e26989814122cbdd94f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:02 -0600 Subject: board/dooly/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I811e89995dfb9d637eb440e8af570ae0567783c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726416 Reviewed-by: Jeremy Bettis --- board/dooly/board.c | 254 +++++++++++++++++++++++----------------------------- 1 file changed, 110 insertions(+), 144 deletions(-) diff --git a/board/dooly/board.c b/board/dooly/board.c index 545ec86ebe..04e32ee4a3 100644 --- a/board/dooly/board.c +++ b/board/dooly/board.c @@ -50,8 +50,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Sensors */ static struct mutex g_accel_mutex; @@ -109,11 +109,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { .saturation.atime = TCS_DEFAULT_ATIME, }; -const mat33_fp_t screen_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t screen_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [SCREEN_ACCEL] = { @@ -190,15 +188,15 @@ DECLARE_DEFERRED(power_monitor); * that range, so we define and use a 64-bit fixed representation instead. */ typedef int64_t fp64_t; -#define INT_TO_FP64(x) ((int64_t)(x) << 32) -#define FP64_TO_INT(x) ((x) >> 32) +#define INT_TO_FP64(x) ((int64_t)(x) << 32) +#define FP64_TO_INT(x) ((x) >> 32) #define FLOAT_TO_FP64(x) ((int64_t)((x) * (float)(1LL << 32))) __override void tcs3400_translate_to_xyz(struct motion_sensor_t *s, int32_t *crgb_data, int32_t *xyz_data) { struct tcs_saturation_t *sat_p = - &(TCS3400_RGB_DRV_DATA(s+1)->saturation); + &(TCS3400_RGB_DRV_DATA(s + 1)->saturation); int32_t cur_gain = (1 << (2 * sat_p->again)); int32_t integration_time_us = @@ -208,40 +206,37 @@ __override void tcs3400_translate_to_xyz(struct motion_sensor_t *s, fp64_t result; /* Use different coefficients based on n_interval = (G+B)/C */ - fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) + - INT_TO_FP64(crgb_data[3]); + fp64_t gb_sum = INT_TO_FP64(crgb_data[2]) + INT_TO_FP64(crgb_data[3]); fp64_t n_interval = gb_sum / MAX(crgb_data[0], 1); if (n_interval < FLOAT_TO_FP64(0.692)) { const float scale = 799.797; - c_coeff = FLOAT_TO_FP64(0.009 * scale); - r_coeff = FLOAT_TO_FP64(0.056 * scale); - g_coeff = FLOAT_TO_FP64(2.735 * scale); + c_coeff = FLOAT_TO_FP64(0.009 * scale); + r_coeff = FLOAT_TO_FP64(0.056 * scale); + g_coeff = FLOAT_TO_FP64(2.735 * scale); b_coeff = FLOAT_TO_FP64(-1.903 * scale); } else if (n_interval < FLOAT_TO_FP64(1.012)) { const float scale = 801.347; - c_coeff = FLOAT_TO_FP64(0.202 * scale); - r_coeff = FLOAT_TO_FP64(-1.1 * scale); - g_coeff = FLOAT_TO_FP64(8.692 * scale); + c_coeff = FLOAT_TO_FP64(0.202 * scale); + r_coeff = FLOAT_TO_FP64(-1.1 * scale); + g_coeff = FLOAT_TO_FP64(8.692 * scale); b_coeff = FLOAT_TO_FP64(-7.068 * scale); } else { const float scale = 795.574; c_coeff = FLOAT_TO_FP64(-0.661 * scale); - r_coeff = FLOAT_TO_FP64(1.334 * scale); - g_coeff = FLOAT_TO_FP64(1.095 * scale); + r_coeff = FLOAT_TO_FP64(1.334 * scale); + g_coeff = FLOAT_TO_FP64(1.095 * scale); b_coeff = FLOAT_TO_FP64(-1.821 * scale); } /* Multiply each channel by the coefficient and compute the sum. * Note: int * fp64_t = fp64_t and fp64_t + fp64_t = fp64_t. */ - result = crgb_data[0] * c_coeff + - crgb_data[1] * r_coeff + - crgb_data[2] * g_coeff + - crgb_data[3] * b_coeff; + result = crgb_data[0] * c_coeff + crgb_data[1] * r_coeff + + crgb_data[2] * g_coeff + crgb_data[3] * b_coeff; /* Adjust for exposure time and sensor gain. * Note: fp64_t / int = fp64_t. @@ -328,8 +323,8 @@ uint16_t tcpc_get_alert_status(void) } /* Called when the charge manager has switched to a new port. */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = @@ -346,12 +341,12 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1603) -#define PWR_FRONT_LOW (5*963) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1603) +#define PWR_FRONT_LOW (5 * 963) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -416,16 +411,14 @@ static const struct { int current; } bj_power[] = { { /* 0 - 65W (also default) */ - .voltage = 19500, - .current = 3200 - }, + .voltage = 19500, + .current = 3200 }, { /* 1 - 90W */ - .voltage = 19500, - .current = 4600 - }, + .voltage = 19500, + .current = 4600 }, }; -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -470,29 +463,26 @@ static void adp_state_init(void) } DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); - #include "gpio_list.h" /* Must come after other header files. */ /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_WHITE] = { .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_WHITE] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ @@ -533,55 +523,41 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "ppc1", - .port = I2C_PORT_PPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "ppc1", + .port = I2C_PORT_PPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -637,15 +613,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -664,7 +639,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -673,8 +648,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -727,7 +702,7 @@ static void cbi_init(void) if (cbi_get_ssfc(&val) == EC_SUCCESS) ssfc = val; CPRINTS("Board Version: %d, SKU ID: 0x%08x, " - "F/W config: 0x%08x, SSFC: 0x%08x ", + "F/W config: 0x%08x, SSFC: 0x%08x ", board_version, sku_id, fw_config, ssfc); } DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); @@ -793,29 +768,23 @@ static void board_chipset_startup(void) /* set high to enable EDID ROM WP */ gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); static void board_chipset_shutdown(void) { /* set low to prevent power leakage */ gpio_set_level(GPIO_EC_EDID_WP_DISABLE_L, 0); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_PPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_PPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -842,7 +811,6 @@ static void board_tcpc_init(void) /* Enable other overcurrent interrupts */ gpio_enable_interrupt(GPIO_USB_A0_OC_ODL); gpio_enable_interrupt(GPIO_USB_A1_OC_ODL); - } /* Make sure this is called after fw_config is initialised */ DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2); @@ -965,8 +933,8 @@ void board_enable_s0_rails(int enable) unsigned int ec_config_get_bj_power(void) { - unsigned int bj = - (fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L; + unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >> + EC_CFG_BJ_POWER_L; /* Out of range value defaults to 0 */ if (bj >= ARRAY_SIZE(bj_power)) bj = 0; @@ -1021,28 +989,28 @@ unsigned int ec_ssfc_get_led_ic(void) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) /* PROCHOT_DEFER_OFF is to extend CPU prochot long enough * to pass safety requirement 30 * 2ms = 60 ms */ -#define PROCHOT_DEFER_OFF 30 +#define PROCHOT_DEFER_OFF 30 static void power_monitor(void) { @@ -1058,8 +1026,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -1087,7 +1054,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -1114,8 +1081,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -1184,8 +1150,8 @@ static void power_monitor(void) * Check whether type C is not throttled, * and is not overcurrent. */ - if (!((new_state & THROT_TYPE_C) || - usbc_0_overcurrent || usbc_1_overcurrent)) { + if (!((new_state & THROT_TYPE_C) || usbc_0_overcurrent || + usbc_1_overcurrent)) { /* * [1] Type C not in overcurrent, throttle it. */ @@ -1218,8 +1184,9 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); @@ -1302,5 +1269,4 @@ void board_backlight_enable_interrupt(enum gpio_signal signal) oz554_interrupt(signal); break; } - } -- cgit v1.2.1 From ca172e69a251dc41e56588376c4159b671621447 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:33 -0600 Subject: driver/led/max695x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If36a8f7553f9e3751277772a4b0b840c46ef6c38 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730000 Reviewed-by: Jeremy Bettis --- driver/led/max695x.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/driver/led/max695x.h b/driver/led/max695x.h index 5ed5d91e2f..6b89dd9ad0 100644 --- a/driver/led/max695x.h +++ b/driver/led/max695x.h @@ -9,36 +9,36 @@ #define __CROS_EC_MAX656X_H /* I2C interface */ -#define MAX695X_I2C_ADDR1_FLAGS 0x38 -#define MAX695X_I2C_ADDR2_FLAGS 0x39 +#define MAX695X_I2C_ADDR1_FLAGS 0x38 +#define MAX695X_I2C_ADDR2_FLAGS 0x39 /* Decode mode register */ -#define MAX695X_REG_DECODE_MODE 0x01 +#define MAX695X_REG_DECODE_MODE 0x01 /* Hexadecimal decode for digits 3–0 */ -#define MAX695X_DECODE_MODE_HEX_DECODE 0x0f +#define MAX695X_DECODE_MODE_HEX_DECODE 0x0f /* Intensity register */ -#define MAX695X_REG_INTENSITY 0x02 +#define MAX695X_REG_INTENSITY 0x02 /* Setting meduim intensity */ -#define MAX695X_INTENSITY_MEDIUM 0x20 +#define MAX695X_INTENSITY_MEDIUM 0x20 /* Scan limit register value */ -#define MAX695X_REG_SCAN_LIMIT 0x03 +#define MAX695X_REG_SCAN_LIMIT 0x03 /* Scanning digits 0-3 */ -#define MAX695X_SCAN_LIMIT_4 0x03 +#define MAX695X_SCAN_LIMIT_4 0x03 /* Configuration register */ -#define MAX695X_REG_CONFIG 0x04 +#define MAX695X_REG_CONFIG 0x04 /* Shutdown seven segment display */ -#define MAX695X_CONFIG_OPR_SHUTDOWN 0x00 +#define MAX695X_CONFIG_OPR_SHUTDOWN 0x00 /* Start seven segment display */ -#define MAX695X_CONFIG_OPR_NORMAL 0x01 +#define MAX695X_CONFIG_OPR_NORMAL 0x01 /* Digit addresses */ -#define MAX695X_DIGIT0_ADDR 0x20 -#define MAX695X_DIGIT1_ADDR 0x21 -#define MAX695X_DIGIT2_ADDR 0x22 -#define MAX695X_DIGIT3_ADDR 0x23 +#define MAX695X_DIGIT0_ADDR 0x20 +#define MAX695X_DIGIT1_ADDR 0x21 +#define MAX695X_DIGIT2_ADDR 0x22 +#define MAX695X_DIGIT3_ADDR 0x23 #endif /* __CROS_EC_MAX656X_H */ -- cgit v1.2.1 From 0c78c6eb60c368189d439ee0c922304d8d5ad9c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:12 -0600 Subject: board/waddledoo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe2246421f118cf9b4ea2c659b2d73e56bc063fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729101 Reviewed-by: Jeremy Bettis --- board/waddledoo/board.h | 51 ++++++++++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h index 37004c2efe..c7f892aaa9 100644 --- a/board/waddledoo/board.h +++ b/board/waddledoo/board.h @@ -19,7 +19,7 @@ /* Save some flash space */ #define CONFIG_CHIP_INIT_ROM_REGION -#undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CONSOLE_CMDHELP #define CONFIG_DEBUG_ASSERT_BRIEF #define CONFIG_USB_PD_DEBUG_LEVEL 2 @@ -37,9 +37,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -68,7 +69,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* USB */ #define CONFIG_BC12_DETECT_PI3USB9201 @@ -91,23 +92,22 @@ #undef PD_POWER_SUPPLY_TURN_OFF_DELAY #undef CONFIG_USBC_VCONN_SWAP_DELAY_US /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ - +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -124,13 +124,13 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -157,19 +157,14 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From 86dfacdb8f9e6886fe49d8154af8240264bc97c1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:13 -0600 Subject: util/cbi-util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27e781486081efd6d46d35495963226d6e7f6ef9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730321 Reviewed-by: Jeremy Bettis --- util/cbi-util.c | 74 +++++++++++++++++++++++++-------------------------------- 1 file changed, 33 insertions(+), 41 deletions(-) diff --git a/util/cbi-util.c b/util/cbi-util.c index fe0c4c2bce..fb38cd86e1 100644 --- a/util/cbi-util.c +++ b/util/cbi-util.c @@ -20,10 +20,10 @@ #include "cros_board_info.h" #include "crc8.h" -#define ARGS_MASK_BOARD_VERSION BIT(0) -#define ARGS_MASK_FILENAME BIT(1) -#define ARGS_MASK_SIZE BIT(2) -#define ARGS_MASK_SKU_ID BIT(3) +#define ARGS_MASK_BOARD_VERSION BIT(0) +#define ARGS_MASK_FILENAME BIT(1) +#define ARGS_MASK_SIZE BIT(2) +#define ARGS_MASK_SKU_ID BIT(3) /* TODO: Set it by macro */ const char cmd_name[] = "cbi-util"; @@ -48,40 +48,31 @@ enum { }; static const struct option opts_create[] = { - {"file", 1, 0, OPT_FILENAME}, - {"board_version", 1, 0, OPT_BOARD_VERSION}, - {"oem_id", 1, 0, OPT_OEM_ID}, - {"sku_id", 1, 0, OPT_SKU_ID}, - {"dram_part_num", 1, 0, OPT_DRAM_PART_NUM}, - {"oem_name", 1, 0, OPT_OEM_NAME}, - {"model_id", 1, 0, OPT_MODEL_ID}, - {"fw_config", 1, 0, OPT_FW_CONFIG}, - {"pcb_supplier", 1, 0, OPT_PCB_SUPPLIER}, - {"ssfc", 1, 0, OPT_SSFC}, - {"rework_id", 1, 0, OPT_REWORK_ID}, - {"size", 1, 0, OPT_SIZE}, - {"erase_byte", 1, 0, OPT_ERASE_BYTE}, - {NULL, 0, 0, 0} + { "file", 1, 0, OPT_FILENAME }, + { "board_version", 1, 0, OPT_BOARD_VERSION }, + { "oem_id", 1, 0, OPT_OEM_ID }, + { "sku_id", 1, 0, OPT_SKU_ID }, + { "dram_part_num", 1, 0, OPT_DRAM_PART_NUM }, + { "oem_name", 1, 0, OPT_OEM_NAME }, + { "model_id", 1, 0, OPT_MODEL_ID }, + { "fw_config", 1, 0, OPT_FW_CONFIG }, + { "pcb_supplier", 1, 0, OPT_PCB_SUPPLIER }, + { "ssfc", 1, 0, OPT_SSFC }, + { "rework_id", 1, 0, OPT_REWORK_ID }, + { "size", 1, 0, OPT_SIZE }, + { "erase_byte", 1, 0, OPT_ERASE_BYTE }, + { NULL, 0, 0, 0 } }; -static const struct option opts_show[] = { - {"file", 1, 0, OPT_FILENAME}, - {"all", 0, 0, OPT_SHOW_ALL}, - {NULL, 0, 0, 0} -}; +static const struct option opts_show[] = { { "file", 1, 0, OPT_FILENAME }, + { "all", 0, 0, OPT_SHOW_ALL }, + { NULL, 0, 0, 0 } }; static const char *field_name[] = { /* Same order as enum cbi_data_tag */ - "BOARD_VERSION", - "OEM_ID", - "SKU_ID", - "DRAM_PART_NUM", - "OEM_NAME", - "MODEL_ID", - "FW_CONFIG", - "PCB_SUPPLIER", - "SSFC", - "REWORK_ID", + "BOARD_VERSION", "OEM_ID", "SKU_ID", "DRAM_PART_NUM", + "OEM_NAME", "MODEL_ID", "FW_CONFIG", "PCB_SUPPLIER", + "SSFC", "REWORK_ID", }; BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT); @@ -147,8 +138,9 @@ static void print_help_show(void) static void print_help(void) { printf("\nUsage: %s [ARGS]\n" - "\n" - "Utility for CBI:Cros Board Info images.\n", cmd_name); + "\n" + "Utility for CBI:Cros Board Info images.\n", + cmd_name); print_help_create(); print_help_show(); } @@ -402,7 +394,7 @@ static int cmd_create(int argc, char **argv) } if (set_mask != (ARGS_MASK_BOARD_VERSION | ARGS_MASK_FILENAME | - ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) { + ARGS_MASK_SIZE | ARGS_MASK_SKU_ID)) { fprintf(stderr, "Missing required arguments\n"); print_help_create(); return -1; @@ -427,7 +419,7 @@ static int cmd_create(int argc, char **argv) p = cbi_set_data(p, CBI_TAG_FW_CONFIG, &bi.fw_config.val, bi.fw_config.size); p = cbi_set_data(p, CBI_TAG_PCB_SUPPLIER, &bi.pcb_supplier.val, - bi.pcb_supplier.size); + bi.pcb_supplier.size); p = cbi_set_data(p, CBI_TAG_SSFC, &bi.ssfc.val, bi.ssfc.size); p = cbi_set_data(p, CBI_TAG_REWORK_ID, &bi.rework.val, bi.rework.size); p = cbi_set_string(p, CBI_TAG_DRAM_PART_NUM, bi.dram_part_num); @@ -460,7 +452,7 @@ static void print_string(const uint8_t *buf, enum cbi_data_tag tag) name = d->tag < CBI_TAG_COUNT ? field_name[d->tag] : "???"; printf(" %s: %.*s (%u, %u)\n", name, d->size, (const char *)d->value, - d->tag, d->size); + d->tag, d->size); } static void print_integer(const uint8_t *buf, enum cbi_data_tag tag) @@ -489,12 +481,12 @@ static void print_integer(const uint8_t *buf, enum cbi_data_tag tag) v = *(uint64_t *)d->value; break; default: - printf(" %s: Integer of size %d not supported\n", - name, d->size); + printf(" %s: Integer of size %d not supported\n", name, + d->size); return; } printf(" %s: %llu (0x%llx, %u, %u)\n", name, (unsigned long long)v, - (unsigned long long)v, d->tag, d->size); + (unsigned long long)v, d->tag, d->size); } static int cmd_show(int argc, char **argv) -- cgit v1.2.1 From 943449f8ef075281ec09692c8a1a9d579176bc96 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:18 -0600 Subject: common/device_state.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59e2a724cfbe336151e5913046c919ff23821d8e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729622 Reviewed-by: Jeremy Bettis --- common/device_state.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/common/device_state.c b/common/device_state.c index 0ba94d6115..c19f5abb7f 100644 --- a/common/device_state.c +++ b/common/device_state.c @@ -7,7 +7,7 @@ #include "device_state.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /** * Return text description for a state @@ -17,8 +17,9 @@ */ static const char *state_desc(enum device_state state) { - return state == DEVICE_STATE_ON ? "on" : - state == DEVICE_STATE_OFF ? "off" : "unknown"; + return state == DEVICE_STATE_ON ? "on" : + state == DEVICE_STATE_OFF ? "off" : + "unknown"; } enum device_state device_get_state(enum device_type device) @@ -78,6 +79,5 @@ static int command_devices(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices, - "", +DECLARE_SAFE_CONSOLE_COMMAND(devices, command_devices, "", "Get the device states"); -- cgit v1.2.1 From 4607e2946ecfcd62f17d4d9fff72657ef0941eb1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:32 -0600 Subject: zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f6475a92bd775902f4ab0669da16965f69b4306 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730937 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c index bdbdd083ba..a7cdf48419 100644 --- a/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c +++ b/zephyr/test/drivers/isl923x/src/console_cmd_amon_bmon.c @@ -60,7 +60,7 @@ ZTEST(console_cmd_amon_bmon, test_isl923x_amonbmon_get_input_current) } ZTEST(console_cmd_amon_bmon, - test_isl923x_amonbmon_get_input_current_read_fail_req1) + test_isl923x_amonbmon_get_input_current_read_fail_req1) { const struct emul *isl923x_emul = ISL923X_EMUL; struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul); @@ -76,7 +76,7 @@ ZTEST(console_cmd_amon_bmon, } ZTEST(console_cmd_amon_bmon, - test_isl923x_amonbmon_get_input_current_read_fail_req3) + test_isl923x_amonbmon_get_input_current_read_fail_req3) { const struct emul *isl923x_emul = ISL923X_EMUL; struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul); @@ -90,7 +90,7 @@ ZTEST(console_cmd_amon_bmon, } ZTEST(console_cmd_amon_bmon, - test_isl923x_amonbmon_get_input_current_write_fail_req1) + test_isl923x_amonbmon_get_input_current_write_fail_req1) { const struct emul *isl923x_emul = ISL923X_EMUL; struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul); @@ -104,7 +104,7 @@ ZTEST(console_cmd_amon_bmon, } ZTEST(console_cmd_amon_bmon, - test_isl923x_amonbmon_get_input_current_write_fail_req3) + test_isl923x_amonbmon_get_input_current_write_fail_req3) { const struct emul *isl923x_emul = ISL923X_EMUL; struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul); -- cgit v1.2.1 From 1611a6e8718fd8591f01ef2c533281e0c972c90f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:38 -0600 Subject: include/dptf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc5d29926272f7c2ccd2f7eef1e2eb4257126e02 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730243 Reviewed-by: Jeremy Bettis --- include/dptf.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/dptf.h b/include/dptf.h index c34e8ea47a..82fe5f6768 100644 --- a/include/dptf.h +++ b/include/dptf.h @@ -27,10 +27,10 @@ int dptf_get_fan_duty_target(void); /** * Set/enable the thresholds. */ -void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */ - int temp, /* in degrees K */ - int idx, /* which threshold (0 or 1) */ - int enable); /* true = on, false = off */ +void dptf_set_temp_threshold(int sensor_id, /* zero-based sensor index */ + int temp, /* in degrees K */ + int idx, /* which threshold (0 or 1) */ + int enable); /* true = on, false = off */ /** * Return the ID of a temp sensor that has crossed its threshold since the last @@ -48,4 +48,4 @@ void dptf_set_charging_current_limit(int ma); */ int dptf_get_charging_current_limit(void); -#endif /* __CROS_EC_DPTF_H */ +#endif /* __CROS_EC_DPTF_H */ -- cgit v1.2.1 From fbf2f30b8efad7aa4fa1eba5b6a5f0b86cc784ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:35 -0600 Subject: board/yorp/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I45aff241231120a23d59b2c6e2d13d85049a7b39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729137 Reviewed-by: Jeremy Bettis --- board/yorp/board.c | 56 ++++++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/board/yorp/board.c b/board/yorp/board.c index 137100aec3..fb04dc1e75 100644 --- a/board/yorp/board.c +++ b/board/yorp/board.c @@ -38,10 +38,10 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static void ppc_interrupt(enum gpio_signal signal) { @@ -64,26 +64,26 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -93,11 +93,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -191,14 +189,14 @@ static void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -void board_hibernate_late(void) { - +void board_hibernate_late(void) +{ int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) @@ -220,7 +218,7 @@ static void post_old_board_warning(void) * warning. */ CPRINTS("\n\n\n ***** BOARD ID 0 is not officially supported!!! *****" - "\n\n\n"); + "\n\n\n"); } DECLARE_HOOK(HOOK_INIT, post_old_board_warning, HOOK_PRIO_INIT_I2C + 1); #endif -- cgit v1.2.1 From c0930d9c7ee9cd3cf897aa8b69bb6bcf3556ea56 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:15 -0600 Subject: board/sasuke/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0b926a27f4e9371b10baf9e34c8cf073e28dd23 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728897 Reviewed-by: Jeremy Bettis --- board/sasuke/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/sasuke/cbi_ssfc.h b/board/sasuke/cbi_ssfc.h index af47a1c2cd..7312ce8382 100644 --- a/board/sasuke/cbi_ssfc.h +++ b/board/sasuke/cbi_ssfc.h @@ -73,5 +73,4 @@ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); */ enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From e9690facd8b3228b8dde5b9764711a11eddf6b17 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:59 -0600 Subject: driver/battery/max17055.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I905232e0eba201cf4731e249df9ab2b902e7605d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729950 Reviewed-by: Jeremy Bettis --- driver/battery/max17055.h | 185 +++++++++++++++++++++++----------------------- 1 file changed, 92 insertions(+), 93 deletions(-) diff --git a/driver/battery/max17055.h b/driver/battery/max17055.h index 0f97fb90f0..d59ccd660e 100644 --- a/driver/battery/max17055.h +++ b/driver/battery/max17055.h @@ -8,105 +8,105 @@ #ifndef __CROS_EC_MAX17055_H #define __CROS_EC_MAX17055_H -#define MAX17055_ADDR_FLAGS 0x36 -#define MAX17055_DEVICE_ID 0x4010 -#define MAX17055_OCV_TABLE_SIZE 48 - -#define REG_STATUS 0x00 -#define REG_VALRTTH 0x01 -#define REG_TALRTTH 0x02 -#define REG_SALRTTH 0x03 -#define REG_AT_RATE 0x04 -#define REG_REMAINING_CAPACITY 0x05 -#define REG_STATE_OF_CHARGE 0x06 -#define REG_TEMPERATURE 0x08 -#define REG_VOLTAGE 0x09 -#define REG_CURRENT 0x0a -#define REG_AVERAGE_CURRENT 0x0b -#define REG_MIXCAP 0x0f -#define REG_FULL_CHARGE_CAPACITY 0x10 -#define REG_TIME_TO_EMPTY 0x11 -#define REG_QR_TABLE00 0x12 -#define REG_CONFIG 0x1D -#define REG_AVERAGE_TEMPERATURE 0x16 -#define REG_CYCLE_COUNT 0x17 -#define REG_DESIGN_CAPACITY 0x18 -#define REG_AVERAGE_VOLTAGE 0x19 -#define REG_MAX_MIN_TEMP 0x1a -#define REG_MAX_MIN_VOLT 0x1b -#define REG_MAX_MIN_CURR 0x1c -#define REG_CHARGE_TERM_CURRENT 0x1e -#define REG_TIME_TO_FULL 0x20 -#define REG_DEVICE_NAME 0x21 -#define REG_QR_TABLE10 0x22 -#define REG_FULLCAPNOM 0x23 -#define REG_LEARNCFG 0x28 -#define REG_QR_TABLE20 0x32 -#define REG_RCOMP0 0x38 -#define REG_TEMPCO 0x39 -#define REG_EMPTY_VOLTAGE 0x3a -#define REG_FSTAT 0x3d -#define REG_TIMER 0x3e -#define REG_QR_TABLE30 0x42 -#define REG_DQACC 0x45 -#define REG_DPACC 0x46 -#define REG_VFSOC0 0x48 -#define REG_COMMAND 0x60 -#define REG_LOCK1 0x62 -#define REG_LOCK2 0x63 -#define REG_OCV_TABLE_START 0x80 -#define REG_STATUS2 0xb0 -#define REG_IALRTTH 0xb4 -#define REG_HIBCFG 0xba -#define REG_CONFIG2 0xbb -#define REG_TIMERH 0xbe -#define REG_MODELCFG 0xdb -#define REG_VFSOC 0xff +#define MAX17055_ADDR_FLAGS 0x36 +#define MAX17055_DEVICE_ID 0x4010 +#define MAX17055_OCV_TABLE_SIZE 48 + +#define REG_STATUS 0x00 +#define REG_VALRTTH 0x01 +#define REG_TALRTTH 0x02 +#define REG_SALRTTH 0x03 +#define REG_AT_RATE 0x04 +#define REG_REMAINING_CAPACITY 0x05 +#define REG_STATE_OF_CHARGE 0x06 +#define REG_TEMPERATURE 0x08 +#define REG_VOLTAGE 0x09 +#define REG_CURRENT 0x0a +#define REG_AVERAGE_CURRENT 0x0b +#define REG_MIXCAP 0x0f +#define REG_FULL_CHARGE_CAPACITY 0x10 +#define REG_TIME_TO_EMPTY 0x11 +#define REG_QR_TABLE00 0x12 +#define REG_CONFIG 0x1D +#define REG_AVERAGE_TEMPERATURE 0x16 +#define REG_CYCLE_COUNT 0x17 +#define REG_DESIGN_CAPACITY 0x18 +#define REG_AVERAGE_VOLTAGE 0x19 +#define REG_MAX_MIN_TEMP 0x1a +#define REG_MAX_MIN_VOLT 0x1b +#define REG_MAX_MIN_CURR 0x1c +#define REG_CHARGE_TERM_CURRENT 0x1e +#define REG_TIME_TO_FULL 0x20 +#define REG_DEVICE_NAME 0x21 +#define REG_QR_TABLE10 0x22 +#define REG_FULLCAPNOM 0x23 +#define REG_LEARNCFG 0x28 +#define REG_QR_TABLE20 0x32 +#define REG_RCOMP0 0x38 +#define REG_TEMPCO 0x39 +#define REG_EMPTY_VOLTAGE 0x3a +#define REG_FSTAT 0x3d +#define REG_TIMER 0x3e +#define REG_QR_TABLE30 0x42 +#define REG_DQACC 0x45 +#define REG_DPACC 0x46 +#define REG_VFSOC0 0x48 +#define REG_COMMAND 0x60 +#define REG_LOCK1 0x62 +#define REG_LOCK2 0x63 +#define REG_OCV_TABLE_START 0x80 +#define REG_STATUS2 0xb0 +#define REG_IALRTTH 0xb4 +#define REG_HIBCFG 0xba +#define REG_CONFIG2 0xbb +#define REG_TIMERH 0xbe +#define REG_MODELCFG 0xdb +#define REG_VFSOC 0xff /* Status reg (0x00) flags */ -#define STATUS_POR BIT(1) -#define STATUS_IMN BIT(2) -#define STATUS_BST BIT(3) -#define STATUS_IMX BIT(6) -#define STATUS_VMN BIT(8) -#define STATUS_TMN BIT(9) -#define STATUS_SMN BIT(10) -#define STATUS_VMX BIT(12) -#define STATUS_TMX BIT(13) -#define STATUS_SMX BIT(14) -#define STATUS_ALL_ALRT \ - (STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \ +#define STATUS_POR BIT(1) +#define STATUS_IMN BIT(2) +#define STATUS_BST BIT(3) +#define STATUS_IMX BIT(6) +#define STATUS_VMN BIT(8) +#define STATUS_TMN BIT(9) +#define STATUS_SMN BIT(10) +#define STATUS_VMX BIT(12) +#define STATUS_TMX BIT(13) +#define STATUS_SMX BIT(14) +#define STATUS_ALL_ALRT \ + (STATUS_IMN | STATUS_IMX | STATUS_VMN | STATUS_VMX | STATUS_TMN | \ STATUS_TMX | STATUS_SMN | STATUS_SMX) /* Alert disable values (0x01, 0x02, 0x03, 0xb4) */ -#define VALRT_DISABLE 0xff00 -#define TALRT_DISABLE 0x7f80 -#define SALRT_DISABLE 0xff00 -#define IALRT_DISABLE 0x7f80 +#define VALRT_DISABLE 0xff00 +#define TALRT_DISABLE 0x7f80 +#define SALRT_DISABLE 0xff00 +#define IALRT_DISABLE 0x7f80 /* Config reg (0x1d) flags */ -#define CONF_AEN BIT(2) -#define CONF_IS BIT(11) -#define CONF_VS BIT(12) -#define CONF_TS BIT(13) -#define CONF_SS BIT(14) -#define CONF_TSEL BIT(15) -#define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS) +#define CONF_AEN BIT(2) +#define CONF_IS BIT(11) +#define CONF_VS BIT(12) +#define CONF_TS BIT(13) +#define CONF_SS BIT(14) +#define CONF_TSEL BIT(15) +#define CONF_ALL_STICKY (CONF_IS | CONF_VS | CONF_TS | CONF_SS) /* FStat reg (0x3d) flags */ -#define FSTAT_DNR 0x0001 -#define FSTAT_FQ 0x0080 +#define FSTAT_DNR 0x0001 +#define FSTAT_FQ 0x0080 /* Config2 reg (0xbb) flags */ -#define CONFIG2_LDMDL BIT(5) +#define CONFIG2_LDMDL BIT(5) /* ModelCfg reg (0xdb) flags */ -#define MODELCFG_REFRESH BIT(15) -#define MODELCFG_VCHG BIT(10) +#define MODELCFG_REFRESH BIT(15) +#define MODELCFG_VCHG BIT(10) /* Smart battery status bits (sbs reg 0x16) */ -#define BATTERY_DISCHARGING 0x40 -#define BATTERY_FULLY_CHARGED 0x20 +#define BATTERY_DISCHARGING 0x40 +#define BATTERY_FULLY_CHARGED 0x20 /* * Before we have the battery fully characterized, we use these macros to @@ -125,28 +125,27 @@ * VE. max17055 reenables empty detection when the cell voltage rises above VR. * VE ranges from 0 to 5110mV, and VR ranges from 0 to 5080mV. */ -#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) \ - (((ve_mv / 10) << 7) | (vr_mv / 40)) +#define MAX17055_VEMPTY_REG(ve_mv, vr_mv) (((ve_mv / 10) << 7) | (vr_mv / 40)) #define MAX17055_MAX_MIN_REG(mx, mn) ((((int16_t)(mx)) << 8) | ((mn))) /* Converts voltages alert range for VALRTTH_REG */ #define MAX17055_VALRTTH_RESOLUTION 20 -#define MAX17055_VALRTTH_REG(mx, mn) \ - MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION), \ +#define MAX17055_VALRTTH_REG(mx, mn) \ + MAX17055_MAX_MIN_REG((uint8_t)(mx / MAX17055_VALRTTH_RESOLUTION), \ (uint8_t)(mn / MAX17055_VALRTTH_RESOLUTION)) /* Converts temperature alert range for TALRTTH_REG */ -#define MAX17055_TALRTTH_REG(mx, mn) \ +#define MAX17055_TALRTTH_REG(mx, mn) \ MAX17055_MAX_MIN_REG((int8_t)(mx), (int8_t)(mn)) /* Converts state-of-charge alert range for SALRTTH_REG */ -#define MAX17055_SALRTTH_REG(mx, mn) \ +#define MAX17055_SALRTTH_REG(mx, mn) \ MAX17055_MAX_MIN_REG((uint8_t)(mx), (uint8_t)(mn)) /* Converts current alert range for IALRTTH_REG */ /* Current resolution: 0.4mV/RSENSE */ #define MAX17055_IALRTTH_MUL (10 * BATTERY_MAX17055_RSENSE) #define MAX17055_IALRTTH_DIV 4 -#define MAX17055_IALRTTH_REG(mx, mn) \ - MAX17055_MAX_MIN_REG( \ - (int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV), \ +#define MAX17055_IALRTTH_REG(mx, mn) \ + MAX17055_MAX_MIN_REG( \ + (int8_t)(mx * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV), \ (int8_t)(mn * MAX17055_IALRTTH_MUL / MAX17055_IALRTTH_DIV)) /* -- cgit v1.2.1 From be64b31bfad3bf881f3d75542db7f449f72c8298 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:59 -0600 Subject: driver/mag_lis2mdl.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ca2a42ad1da66a214422dbf174dfa023d4ad67f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730019 Reviewed-by: Jeremy Bettis --- driver/mag_lis2mdl.h | 72 +++++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/driver/mag_lis2mdl.h b/driver/mag_lis2mdl.h index bc823628b3..9ca433a507 100644 --- a/driver/mag_lis2mdl.h +++ b/driver/mag_lis2mdl.h @@ -16,45 +16,45 @@ * 8-bit address is 0011110Wb where the last bit represents whether the * operation is a read or a write. */ -#define LIS2MDL_ADDR_FLAGS 0x1e +#define LIS2MDL_ADDR_FLAGS 0x1e -#define LIS2MDL_STARTUP_MS 10 +#define LIS2MDL_STARTUP_MS 10 /* Registers */ -#define LIS2MDL_WHO_AM_I_REG 0x4f -#define LIS2MDL_CFG_REG_A_ADDR 0x60 -#define LIS2MDL_INT_CTRL_REG 0x63 -#define LIS2MDL_STATUS_REG 0x67 -#define LIS2MDL_OUT_REG 0x68 - -#define LIS2MDL_WHO_AM_I 0x40 - -#define LIS2MDL_FLAG_TEMP_COMPENSATION 0x80 -#define LIS2MDL_FLAG_REBOOT 0x40 -#define LIS2MDL_FLAG_SW_RESET 0x20 -#define LIS2MDL_FLAG_LOW_POWER 0x10 -#define LIS2MDL_ODR_50HZ 0x08 -#define LIS2MDL_ODR_20HZ 0x04 -#define LIS2MDL_ODR_10HZ 0x00 -#define LIS2MDL_MODE_IDLE 0x03 -#define LIS2MDL_MODE_SINGLE 0x01 -#define LIS2MDL_MODE_CONT 0x00 -#define LIS2MDL_ODR_MODE_MASK 0x8f - -#define LIS2MDL_X_DIRTY 0x01 -#define LIS2MDL_Y_DIRTY 0x02 -#define LIS2MDL_Z_DIRTY 0x04 -#define LIS2MDL_XYZ_DIRTY 0x08 -#define LIS2MDL_XYZ_DIRTY_MASK 0x0f - -#define LIS2DSL_RESOLUTION 16 +#define LIS2MDL_WHO_AM_I_REG 0x4f +#define LIS2MDL_CFG_REG_A_ADDR 0x60 +#define LIS2MDL_INT_CTRL_REG 0x63 +#define LIS2MDL_STATUS_REG 0x67 +#define LIS2MDL_OUT_REG 0x68 + +#define LIS2MDL_WHO_AM_I 0x40 + +#define LIS2MDL_FLAG_TEMP_COMPENSATION 0x80 +#define LIS2MDL_FLAG_REBOOT 0x40 +#define LIS2MDL_FLAG_SW_RESET 0x20 +#define LIS2MDL_FLAG_LOW_POWER 0x10 +#define LIS2MDL_ODR_50HZ 0x08 +#define LIS2MDL_ODR_20HZ 0x04 +#define LIS2MDL_ODR_10HZ 0x00 +#define LIS2MDL_MODE_IDLE 0x03 +#define LIS2MDL_MODE_SINGLE 0x01 +#define LIS2MDL_MODE_CONT 0x00 +#define LIS2MDL_ODR_MODE_MASK 0x8f + +#define LIS2MDL_X_DIRTY 0x01 +#define LIS2MDL_Y_DIRTY 0x02 +#define LIS2MDL_Z_DIRTY 0x04 +#define LIS2MDL_XYZ_DIRTY 0x08 +#define LIS2MDL_XYZ_DIRTY_MASK 0x0f + +#define LIS2DSL_RESOLUTION 16 /* * Maximum sensor data range (milligauss): * Spec is 1.5 mguass / LSB, so 0.15 uT / LSB. * Calibration code is set to 16LSB/ut, [0.0625 uT/LSB] * Apply a multiplier to change the unit */ -#define LIS2MDL_RATIO(_in) (((_in) * 24) / 10) +#define LIS2MDL_RATIO(_in) (((_in)*24) / 10) struct lis2mdl_private_data { /* lsm6dsm_data union requires cal be first element */ @@ -63,8 +63,8 @@ struct lis2mdl_private_data { struct stprivate_data data; #endif #ifdef CONFIG_MAG_BMI_LIS2MDL - intv3_t hn; /* last sample for offset compensation */ - int hn_valid; + intv3_t hn; /* last sample for offset compensation */ + int hn_valid; #endif }; @@ -75,15 +75,13 @@ struct lis2mdl_private_data { (&(DOWNCAST(s->drv_data, struct lis2mdl_private_data, data)->cal)) #endif - -#define LIS2MDL_ODR_MIN_VAL 10000 -#define LIS2MDL_ODR_MAX_VAL 50000 +#define LIS2MDL_ODR_MIN_VAL 10000 +#define LIS2MDL_ODR_MAX_VAL 50000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= LIS2MDL_ODR_MAX_VAL) #error "EC too slow for magnetometer" #endif -void lis2mdl_normalize(const struct motion_sensor_t *s, - intv3_t v, +void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data); extern const struct accelgyro_drv lis2mdl_drv; -- cgit v1.2.1 From 5df0f741439f7a5e3a1714de1d4c8e4cd2ba6812 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:18 -0600 Subject: baseboard/brya/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c90d26e0e7dd407665c529a8b393c6517907370 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727863 Reviewed-by: Jeremy Bettis --- baseboard/brya/cbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/brya/cbi.c b/baseboard/brya/cbi.c index ded310bffc..5bda205be1 100644 --- a/baseboard/brya/cbi.c +++ b/baseboard/brya/cbi.c @@ -10,8 +10,8 @@ #include "cros_board_info.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static uint8_t board_id; -- cgit v1.2.1 From 6e7a6ae419766b9fbb019fd977e6790c594df096 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:53 -0600 Subject: chip/npcx/spiflashfw/npcx_monitor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a430ed3361c99c680eb6f69087252c862cc7c15 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729438 Reviewed-by: Jeremy Bettis --- chip/npcx/spiflashfw/npcx_monitor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/npcx/spiflashfw/npcx_monitor.h b/chip/npcx/spiflashfw/npcx_monitor.h index f4f30454d2..5259fd205a 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.h +++ b/chip/npcx/spiflashfw/npcx_monitor.h @@ -7,11 +7,11 @@ #include -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 +#define NPCX_MONITOR_UUT_TAG 0xA5075001 +#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 /* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 +#define SPI_PROGRAMMING_FLAG 0x200C4000 struct monitor_header_tag { /* offset 0x00: TAG NPCX_MONITOR_TAG */ @@ -23,9 +23,9 @@ struct monitor_header_tag { /* offset 0x0C: The Flash address to be programmed (Absolute address) */ uint32_t dest_addr; /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; + uint8_t max_clock; /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; + uint8_t read_mode; /* offset 0x12: Reserved */ uint16_t reserved; } __packed; -- cgit v1.2.1 From 5d7f38afe8359f806a0c58439a2197062439cf35 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:21 -0600 Subject: board/servo_v4/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I800aef086b69f9713d2088bfe01451c63d2bf6de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728920 Reviewed-by: Jeremy Bettis --- board/servo_v4/board.h | 57 +++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/board/servo_v4/board.h b/board/servo_v4/board.h index 910d6caacc..a7163e563d 100644 --- a/board/servo_v4/board.h +++ b/board/servo_v4/board.h @@ -38,9 +38,10 @@ #define CONFIG_STM_HWTIMER32 #define CONFIG_HW_CRC #define CONFIG_PVD -/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet. - PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */ -#define PVD_THRESHOLD (1) +/* See 'Programmable voltage detector characteristics' in the STM32F072x8 + Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of + min:2.09V, max:2.27V. */ +#define PVD_THRESHOLD (1) /* USB Configuration */ #define CONFIG_USB @@ -60,23 +61,23 @@ #define DEFAULT_MAC_ADDR "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_EMPTY 1 -#define USB_IFACE_I2C 2 -#define USB_IFACE_USART3_STREAM 3 -#define USB_IFACE_USART4_STREAM 4 -#define USB_IFACE_UPDATE 5 -#define USB_IFACE_COUNT 6 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_EMPTY 1 +#define USB_IFACE_I2C 2 +#define USB_IFACE_USART3_STREAM 3 +#define USB_IFACE_USART4_STREAM 4 +#define USB_IFACE_UPDATE 5 +#define USB_IFACE_COUNT 6 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_EMPTY 2 -#define USB_EP_I2C 3 -#define USB_EP_USART3_STREAM 4 -#define USB_EP_USART4_STREAM 5 -#define USB_EP_UPDATE 6 -#define USB_EP_COUNT 7 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_EMPTY 2 +#define USB_EP_I2C 3 +#define USB_EP_USART3_STREAM 4 +#define USB_EP_USART4_STREAM 5 +#define USB_EP_UPDATE 6 +#define USB_EP_COUNT 7 /* Enable console recasting of GPIO type. */ #define CONFIG_CMD_GPIO_EXTENDED @@ -113,7 +114,7 @@ /* PD features */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_BOARD_PRE_INIT /* * If task profiling is enabled then the rx falling edge detection interrupts @@ -122,7 +123,7 @@ #undef CONFIG_TASK_PROFILING #define CONFIG_CHARGE_MANAGER -#undef CONFIG_CHARGE_MANAGER_SAFE_MODE +#undef CONFIG_CHARGE_MANAGER_SAFE_MODE #define CONFIG_USB_POWER_DELIVERY #define CONFIG_USB_PD_TCPMV1 #define CONFIG_CMD_PD @@ -144,22 +145,22 @@ #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK /* Variable-current Rp no connect and Ra attach macros */ -#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) -#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) +#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) +#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) /* * TODO(crosbug.com/p/60792): The delay values are currently just place holders * and the delay will need to be relative to the circuitry that allows VBUS to * be supplied to the DUT port from the CHG port. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Define PDO selection logic for SourceCap. * On a 45W PD charger, it might provide PDOs with 15V/3A and 20V/2.25A. @@ -180,8 +181,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 - +#define TIM_ADC 3 #include "gpio_signal.h" @@ -200,7 +200,6 @@ enum usb_strings { USB_STR_COUNT }; - /* ADC signal */ enum adc_channel { ADC_CHG_CC1_PD, -- cgit v1.2.1 From b0a63b36dd9c45f3cb35d8276de06dda6b4b815a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:21 -0600 Subject: include/task_filter.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cdfb11747141934aa0a71c057d14c64865f7b27 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730417 Reviewed-by: Jeremy Bettis --- include/task_filter.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/task_filter.h b/include/task_filter.h index 2cd5e8bbf8..7bd224a577 100644 --- a/include/task_filter.h +++ b/include/task_filter.h @@ -50,5 +50,4 @@ CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST #endif - #endif /* __CROS_EC_TASK_FILTER_H */ -- cgit v1.2.1 From 97100785cf100e93e13adacfdd0430968e5b74a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:21 -0600 Subject: include/crypto_api.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8aeea495fd280b3470dd01221e9977e00581bbea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730237 Reviewed-by: Jeremy Bettis --- include/crypto_api.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/crypto_api.h b/include/crypto_api.h index 8a8ccacf99..95bf0cedec 100644 --- a/include/crypto_api.h +++ b/include/crypto_api.h @@ -26,8 +26,8 @@ extern "C" { * value exceeds SHA1 size (20 bytes), the rest of the * hash is filled up with zeros. */ -void app_compute_hash(uint8_t *p_buf, size_t num_bytes, - uint8_t *p_hash, size_t hash_len); +void app_compute_hash(uint8_t *p_buf, size_t num_bytes, uint8_t *p_hash, + size_t hash_len); #define CIPHER_SALT_SIZE 16 -- cgit v1.2.1 From 39d08fb81d54e2796df959f219b7ff49b71de0a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:11 -0600 Subject: board/asurada_scp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87f556b03dab40fd391ddbc7f1b38b55d98ad272 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727994 Reviewed-by: Jeremy Bettis --- board/asurada_scp/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/asurada_scp/board.h b/board/asurada_scp/board.h index e25a26dec0..e91e8adb0e 100644 --- a/board/asurada_scp/board.h +++ b/board/asurada_scp/board.h @@ -25,8 +25,8 @@ #define CONFIG_ROM_BASE 0x0 #define CONFIG_RAM_BASE 0x58000 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) -#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \ - CONFIG_RAM_BASE) +#define CONFIG_RAM_SIZE \ + ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE) #define SCP_FW_END 0x100000 -- cgit v1.2.1 From 0fc8eb2806590cf43ad5d45b7f6f08bef044a6f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:08 -0600 Subject: chip/stm32/usart-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1fc7803b056d6a3ead530cebd93a16f854524a9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729415 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32f4.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/chip/stm32/usart-stm32f4.c b/chip/stm32/usart-stm32f4.c index 2c9e4b1f4a..9df7a6322b 100644 --- a/chip/stm32/usart-stm32f4.c +++ b/chip/stm32/usart-stm32f4.c @@ -24,14 +24,13 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) { configs[config->hw->index] = config; - /* Use single-bit sampling */ STM32_USART_CR3(config->hw->base) |= STM32_USART_CR3_ONEBIT; @@ -48,7 +47,7 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; @@ -58,12 +57,12 @@ static struct usart_hw_ops const usart_variant_hw_ops = { */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -76,12 +75,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -94,12 +93,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif -- cgit v1.2.1 From 04baae5efbe835260000c505b90a94303fe0a6b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:55 -0600 Subject: board/nucleo-f411re/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3da305ae5db7d43676cf5a0ba491d31f2dabe9bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728777 Reviewed-by: Jeremy Bettis --- board/nucleo-f411re/board.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/board/nucleo-f411re/board.c b/board/nucleo-f411re/board.c index 96e7fefb69..545a1ed472 100644 --- a/board/nucleo-f411re/board.c +++ b/board/nucleo-f411re/board.c @@ -43,22 +43,20 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* Arduino connectors analog pins */ - [ADC1_0] = {"ADC1_0", 3000, 4096, 0, STM32_AIN(0)}, - [ADC1_1] = {"ADC1_1", 3000, 4096, 0, STM32_AIN(1)}, - [ADC1_4] = {"ADC1_4", 3000, 4096, 0, STM32_AIN(4)}, - [ADC1_8] = {"ADC1_8", 3000, 4096, 0, STM32_AIN(8)}, + [ADC1_0] = { "ADC1_0", 3000, 4096, 0, STM32_AIN(0) }, + [ADC1_1] = { "ADC1_1", 3000, 4096, 0, STM32_AIN(1) }, + [ADC1_4] = { "ADC1_4", 3000, 4096, 0, STM32_AIN(4) }, + [ADC1_8] = { "ADC1_8", 3000, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -124,6 +122,5 @@ static int command_dma_help(int argc, char **argv) dma_dump(STM32_DMA2_STREAM0); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help, - NULL, "Run DMA test"); +DECLARE_CONSOLE_COMMAND(dmahelp, command_dma_help, NULL, "Run DMA test"); #endif -- cgit v1.2.1 From 1fb7929094900d34aa07124aa05e2abf6530c4c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:26 -0600 Subject: board/sasukette/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iecd0dea6126dfab1fdae353b40a9c9d84c8cbb02 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728910 Reviewed-by: Jeremy Bettis --- board/sasukette/board.c | 115 +++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 65 deletions(-) diff --git a/board/sasukette/board.c b/board/sasukette/board.c index cbc786b892..c72425fc36 100644 --- a/board/sasukette/board.c +++ b/board/sasukette/board.c @@ -41,7 +41,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -90,45 +90,35 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* BC 1.2 chips */ -const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { - { - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - .flags = PI3USB9201_ALWAYS_POWERED, - } -}; +const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { { + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + .flags = PI3USB9201_ALWAYS_POWERED, +} }; int pd_snk_is_vbus_provided(int port) { @@ -136,13 +126,11 @@ int pd_snk_is_vbus_provided(int port) } /* Charger chips */ -const struct charger_config_t chg_chips[] = { - { - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = ISL923X_ADDR_FLAGS, - .drv = &isl923x_drv, - } -}; +const struct charger_config_t chg_chips[] = { { + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = ISL923X_ADDR_FLAGS, + .drv = &isl923x_drv, +} }; /* TCPCs */ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { @@ -158,14 +146,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; /* USB Muxes */ -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, - .driver = &it5205_usb_mux_driver, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .usb_port = 0, + .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, + .driver = &it5205_usb_mux_driver, +} }; static uint32_t board_id; @@ -285,8 +271,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -359,17 +344,17 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Cpu", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Cpu", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 117b7d1980e2b70d9a2e83e99595a998f2dae1a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:36 -0600 Subject: zephyr/shim/src/cbi/cros_cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ac9d06fd9943a8f38fd7b2b665fc4bd935ecb07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730864 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/cbi/cros_cbi_ssfc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/src/cbi/cros_cbi_ssfc.c b/zephyr/shim/src/cbi/cros_cbi_ssfc.c index a2dc3ccf0a..628b4e244d 100644 --- a/zephyr/shim/src/cbi/cros_cbi_ssfc.c +++ b/zephyr/shim/src/cbi/cros_cbi_ssfc.c @@ -129,9 +129,8 @@ BUILD_ASSERT(sizeof(union cbi_ssfc) == sizeof(uint32_t), DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_BUILD_ASSERT) -static const uint8_t ssfc_values[] = { - DT_INST_FOREACH_STATUS_OKAY(CBI_SSFC_VALUE_ARRAY) -}; +static const uint8_t ssfc_values[] = { DT_INST_FOREACH_STATUS_OKAY( + CBI_SSFC_VALUE_ARRAY) }; static union cbi_ssfc cached_ssfc; -- cgit v1.2.1 From 9592fae7fb78201480845546798bc1c7faedf389 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:09 -0600 Subject: test/entropy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If0496251d6ad350168b5126092a82ae267a908ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730498 Reviewed-by: Jeremy Bettis --- test/entropy.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/entropy.c b/test/entropy.c index fb066a6c5b..5fdca3969f 100644 --- a/test/entropy.c +++ b/test/entropy.c @@ -26,7 +26,7 @@ uint32_t log2(int32_t val) int val1 = 31 - __builtin_clz(val); int val2 = 32 - __builtin_clz(val - 1); - return log2_mult * (val1 + val2)/2; + return log2_mult * (val1 + val2) / 2; } void run_test(int argc, char **argv) @@ -52,7 +52,7 @@ void run_test(int argc, char **argv) t1 = get_time(); if (i == 0) ccprintf("Got %zd bytes in %" PRId64 " us\n", - sizeof(buffer), t1.val - t0.val); + sizeof(buffer), t1.val - t0.val); for (j = 0; j < sizeof(buffer); j++) buckets[buffer[j]]++; @@ -82,7 +82,7 @@ void run_test(int argc, char **argv) ccprintf("\n"); ccprintf("Entropy: %u/1000 bits\n", - entropy * 1000 / (log2_mult * totalcount)); + entropy * 1000 / (log2_mult * totalcount)); /* We want at least 2 bits of entropy (out of a maximum of 8) */ if ((entropy / (log2_mult * totalcount)) >= 2) -- cgit v1.2.1 From 6e8bbe2cbf829a4aefe69aa62992fd1fed838fcb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:51 -0600 Subject: test/charge_manager.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f274078d3aa5ff4ac9ff93dcb9bffd900c765fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730473 Reviewed-by: Jeremy Bettis --- test/charge_manager.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/test/charge_manager.c b/test/charge_manager.c index 2a64ca3e98..574ebd8722 100644 --- a/test/charge_manager.c +++ b/test/charge_manager.c @@ -18,16 +18,11 @@ /* Charge supplier priority: lower number indicates higher priority. */ const int supplier_priority[] = { - [CHARGE_SUPPLIER_TEST1] = 0, - [CHARGE_SUPPLIER_TEST2] = 1, - [CHARGE_SUPPLIER_TEST3] = 1, - [CHARGE_SUPPLIER_TEST4] = 1, - [CHARGE_SUPPLIER_TEST5] = 3, - [CHARGE_SUPPLIER_TEST6] = 3, - [CHARGE_SUPPLIER_TEST7] = 5, - [CHARGE_SUPPLIER_TEST8] = 6, - [CHARGE_SUPPLIER_TEST9] = 6, - [CHARGE_SUPPLIER_TEST10] = 7, + [CHARGE_SUPPLIER_TEST1] = 0, [CHARGE_SUPPLIER_TEST2] = 1, + [CHARGE_SUPPLIER_TEST3] = 1, [CHARGE_SUPPLIER_TEST4] = 1, + [CHARGE_SUPPLIER_TEST5] = 3, [CHARGE_SUPPLIER_TEST6] = 3, + [CHARGE_SUPPLIER_TEST7] = 5, [CHARGE_SUPPLIER_TEST8] = 6, + [CHARGE_SUPPLIER_TEST9] = 6, [CHARGE_SUPPLIER_TEST10] = 7, }; BUILD_ASSERT((int)CHARGE_SUPPLIER_COUNT == (int)CHARGE_SUPPLIER_TEST_COUNT); BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT); @@ -39,8 +34,8 @@ static int new_power_request[CONFIG_USB_PD_PORT_MAX_COUNT]; static enum pd_power_role power_role[CONFIG_USB_PD_PORT_MAX_COUNT]; /* Callback functions called by CM on state change */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { active_charge_limit = charge_ma; } @@ -156,8 +151,8 @@ static int test_initialization(void) TEST_ASSERT(active_charge_port == CHARGE_PORT_NONE); /* Update last pair and verify a charge port has been selected */ - charge_manager_update_charge(CHARGE_SUPPLIER_COUNT-1, - board_get_usb_pd_port_count()-1, + charge_manager_update_charge(CHARGE_SUPPLIER_COUNT - 1, + board_get_usb_pd_port_count() - 1, &charge); wait_for_charge_manager_refresh(); TEST_ASSERT(active_charge_port != CHARGE_PORT_NONE); -- cgit v1.2.1 From 6c75845c315b1d687e808a2cc17ea110152799b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:16 -0600 Subject: util/comm-dev.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic76f79bfed4199bad8f40b3ca9cdcf435820d7f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730322 Reviewed-by: Jeremy Bettis --- util/comm-dev.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/util/comm-dev.c b/util/comm-dev.c index e73538b323..235c954c4b 100644 --- a/util/comm-dev.c +++ b/util/comm-dev.c @@ -27,7 +27,7 @@ static int fd = -1; #define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0])) #endif -static const char * const meanings[] = { +static const char *const meanings[] = { "SUCCESS", "INVALID_COMMAND", "ERROR", @@ -60,9 +60,8 @@ static const char *strresult(int i) /* Old ioctl format, used by Chrome OS 3.18 and older */ -static int ec_command_dev(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_dev(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { struct cros_ec_command s_cmd; int r; @@ -117,16 +116,14 @@ static int ec_readmem_dev(int offset, int bytes, void *dest) r_mem.offset = offset; r_mem.size = bytes; - return ec_command_dev(EC_CMD_READ_MEMMAP, 0, - &r_mem, sizeof(r_mem), + return ec_command_dev(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem), dest, bytes); } /* New ioctl format, used by Chrome OS 4.4 and later as well as upstream 4.0+ */ -static int ec_command_dev_v2(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_dev_v2(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { struct cros_ec_command_v2 *s_cmd; int r; @@ -164,7 +161,7 @@ static int ec_command_dev_v2(int command, int version, if (s_cmd->result != EC_RES_SUCCESS) { fprintf(stderr, "EC result %d (%s)\n", s_cmd->result, strresult(s_cmd->result)); - r = -EECRESULT - s_cmd->result; + r = -EECRESULT - s_cmd->result; } } free(s_cmd); @@ -193,8 +190,7 @@ static int ec_readmem_dev_v2(int offset, int bytes, void *dest) r_mem.offset = offset; r_mem.size = bytes; - return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0, - &r_mem, sizeof(r_mem), + return ec_command_dev_v2(EC_CMD_READ_MEMMAP, 0, &r_mem, sizeof(r_mem), dest, bytes); } @@ -204,11 +200,9 @@ static int ec_readmem_dev_v2(int offset, int bytes, void *dest) */ static int ec_dev_is_v2(void) { - struct ec_params_hello h_req = { - .in_data = 0xa0b0c0d0 - }; + struct ec_params_hello h_req = { .in_data = 0xa0b0c0d0 }; struct ec_response_hello h_resp; - struct cros_ec_command s_cmd = { }; + struct cros_ec_command s_cmd = {}; int r; s_cmd.command = EC_CMD_HELLO; @@ -256,7 +250,7 @@ int comm_init_dev(const char *device_name) if (fd < 0) return 1; - r = read(fd, version, sizeof(version)-1); + r = read(fd, version, sizeof(version) - 1); if (r <= 0) { close(fd); return 2; -- cgit v1.2.1 From 224d749b2afee28f155dbbc4d7341e2327e96f7f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:24 -0600 Subject: common/newton_fit.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie51a70c4deea5bb1c951a19df6fe20310893cd17 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729696 Reviewed-by: Jeremy Bettis --- common/newton_fit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/newton_fit.c b/common/newton_fit.c index ae81a45f07..aecc63f89f 100644 --- a/common/newton_fit.c +++ b/common/newton_fit.c @@ -32,7 +32,7 @@ static fp_t compute_error(struct newton_fit *fit, fpv3_t center) _it = (struct newton_fit_orientation *)it.ptr; e = FLOAT_TO_FP(1.0f) - - distance_squared(_it->orientation, center); + distance_squared(_it->orientation, center); error += fp_mul(e, e); } @@ -138,8 +138,8 @@ void newton_fit_compute(struct newton_fit *fit, fpv3_t bias, fp_t *radius) if (queue_is_empty(fit->orientations)) return; - inv_orient_count = fp_div(FLOAT_TO_FP(1.0f), - queue_count(fit->orientations)); + inv_orient_count = + fp_div(FLOAT_TO_FP(1.0f), queue_count(fit->orientations)); memcpy(new_bias, bias, sizeof(fpv3_t)); new_error = compute_error(fit, new_bias); -- cgit v1.2.1 From a4b255d03ad0f05b7cf61353a76acc2d74244f38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:00 -0600 Subject: board/kinox/power_detection.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I170f4fa38b575ff1441c906abed1fd76d9dd4a82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728556 Reviewed-by: Jeremy Bettis --- board/kinox/power_detection.c | 328 +++++++++++++++++++++--------------------- 1 file changed, 162 insertions(+), 166 deletions(-) diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c index 54ca591252..b48333b82c 100644 --- a/board/kinox/power_detection.c +++ b/board/kinox/power_detection.c @@ -17,215 +17,211 @@ #include "util.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /******************************************************************************/ -static const char * const adp_id_names[] = { - "unknown", - "tiny", - "tio1", - "tio2", - "typec", +static const char *const adp_id_names[] = { + "unknown", "tiny", "tio1", "tio2", "typec", }; /* ADP_ID control */ struct adpater_id_params tio1_power[] = { { - .min_voltage = 3300, - .max_voltage = 3300, - .charge_voltage = 20000, - .charge_current = 6000, - .watt = 120, - .obp95 = 1990, - .obp85 = 1780, + .min_voltage = 3300, + .max_voltage = 3300, + .charge_voltage = 20000, + .charge_current = 6000, + .watt = 120, + .obp95 = 1990, + .obp85 = 1780, }, }; struct adpater_id_params tio2_power[] = { { - .min_voltage = 0, - .max_voltage = 68, - .charge_voltage = 20000, - .charge_current = 8500, - .watt = 170, - .obp95 = 2820, - .obp85 = 916, + .min_voltage = 0, + .max_voltage = 68, + .charge_voltage = 20000, + .charge_current = 8500, + .watt = 170, + .obp95 = 2820, + .obp85 = 916, }, { - .min_voltage = 68, - .max_voltage = 142, - .charge_voltage = 20000, - .charge_current = 2250, - .watt = 45, - .obp95 = 750, - .obp85 = 670, + .min_voltage = 68, + .max_voltage = 142, + .charge_voltage = 20000, + .charge_current = 2250, + .watt = 45, + .obp95 = 750, + .obp85 = 670, }, { - .min_voltage = 200, - .max_voltage = 288, - .charge_voltage = 20000, - .charge_current = 3250, - .watt = 65, - .obp95 = 1080, - .obp85 = 960, + .min_voltage = 200, + .max_voltage = 288, + .charge_voltage = 20000, + .charge_current = 3250, + .watt = 65, + .obp95 = 1080, + .obp85 = 960, }, { - .min_voltage = 531, - .max_voltage = 607, - .charge_voltage = 20000, - .charge_current = 6000, - .watt = 120, - .obp95 = 1990, - .obp85 = 1780, + .min_voltage = 531, + .max_voltage = 607, + .charge_voltage = 20000, + .charge_current = 6000, + .watt = 120, + .obp95 = 1990, + .obp85 = 1780, }, { - .min_voltage = 384, - .max_voltage = 480, - .charge_voltage = 20000, - .charge_current = 7500, - .watt = 150, - .obp95 = 2490, - .obp85 = 2220, + .min_voltage = 384, + .max_voltage = 480, + .charge_voltage = 20000, + .charge_current = 7500, + .watt = 150, + .obp95 = 2490, + .obp85 = 2220, }, { - .min_voltage = 1062, - .max_voltage = 1126, - .charge_voltage = 20000, - .charge_current = 8500, - .watt = 170, - .obp95 = 2820, - .obp85 = 916, + .min_voltage = 1062, + .max_voltage = 1126, + .charge_voltage = 20000, + .charge_current = 8500, + .watt = 170, + .obp95 = 2820, + .obp85 = 916, }, { - .min_voltage = 2816, - .max_voltage = 3300, - .charge_voltage = 20000, - .charge_current = 6000, - .watt = 120, - .obp95 = 1990, - .obp85 = 1780, + .min_voltage = 2816, + .max_voltage = 3300, + .charge_voltage = 20000, + .charge_current = 6000, + .watt = 120, + .obp95 = 1990, + .obp85 = 1780, }, }; struct adpater_id_params tiny_power[] = { { - .min_voltage = 68, - .max_voltage = 142, - .charge_voltage = 20000, - .charge_current = 2250, - .watt = 45, - .obp95 = 750, - .obp85 = 670, + .min_voltage = 68, + .max_voltage = 142, + .charge_voltage = 20000, + .charge_current = 2250, + .watt = 45, + .obp95 = 750, + .obp85 = 670, }, { - .min_voltage = 200, - .max_voltage = 288, - .charge_voltage = 20000, - .charge_current = 3250, - .watt = 65, - .obp95 = 1080, - .obp85 = 960, + .min_voltage = 200, + .max_voltage = 288, + .charge_voltage = 20000, + .charge_current = 3250, + .watt = 65, + .obp95 = 1080, + .obp85 = 960, }, { - .min_voltage = 384, - .max_voltage = 480, - .charge_voltage = 20000, - .charge_current = 4500, - .watt = 90, - .obp95 = 1490, - .obp85 = 1330, + .min_voltage = 384, + .max_voltage = 480, + .charge_voltage = 20000, + .charge_current = 4500, + .watt = 90, + .obp95 = 1490, + .obp85 = 1330, }, { - .min_voltage = 531, - .max_voltage = 607, - .charge_voltage = 20000, - .charge_current = 6000, - .watt = 120, - .obp95 = 0x2D3, - .obp85 = 0x286, + .min_voltage = 531, + .max_voltage = 607, + .charge_voltage = 20000, + .charge_current = 6000, + .watt = 120, + .obp95 = 0x2D3, + .obp85 = 0x286, }, { - .min_voltage = 653, - .max_voltage = 783, - .charge_voltage = 20000, - .charge_current = 6750, - .watt = 135, - .obp95 = 2240, - .obp85 = 2000, + .min_voltage = 653, + .max_voltage = 783, + .charge_voltage = 20000, + .charge_current = 6750, + .watt = 135, + .obp95 = 2240, + .obp85 = 2000, }, { - .min_voltage = 851, - .max_voltage = 997, - .charge_voltage = 20000, - .charge_current = 7500, - .watt = 150, - .obp95 = 2490, - .obp85 = 2220, + .min_voltage = 851, + .max_voltage = 997, + .charge_voltage = 20000, + .charge_current = 7500, + .watt = 150, + .obp95 = 2490, + .obp85 = 2220, }, { - .min_voltage = 1063, - .max_voltage = 1226, - .charge_voltage = 20000, - .charge_current = 8500, - .watt = 170, - .obp95 = 2820, - .obp85 = 916, + .min_voltage = 1063, + .max_voltage = 1226, + .charge_voltage = 20000, + .charge_current = 8500, + .watt = 170, + .obp95 = 2820, + .obp85 = 916, }, { - .min_voltage = 1749, - .max_voltage = 1968, - .charge_voltage = 20000, - .charge_current = 11500, - .watt = 230, - .obp95 = 3810, - .obp85 = 3410, + .min_voltage = 1749, + .max_voltage = 1968, + .charge_voltage = 20000, + .charge_current = 11500, + .watt = 230, + .obp95 = 3810, + .obp85 = 3410, }, }; struct adpater_id_params typec_power[] = { { - .charge_voltage = 20000, - .charge_current = 1500, - .watt = 30, - .obp95 = 500, - .obp85 = 440, + .charge_voltage = 20000, + .charge_current = 1500, + .watt = 30, + .obp95 = 500, + .obp85 = 440, }, { - .charge_voltage = 15000, - .charge_current = 2000, - .watt = 30, - .obp95 = 660, - .obp85 = 590, + .charge_voltage = 15000, + .charge_current = 2000, + .watt = 30, + .obp95 = 660, + .obp85 = 590, }, { - .charge_voltage = 20000, - .charge_current = 2250, - .watt = 45, - .obp95 = 750, - .obp85 = 670, + .charge_voltage = 20000, + .charge_current = 2250, + .watt = 45, + .obp95 = 750, + .obp85 = 670, }, { - .charge_voltage = 15000, - .charge_current = 3000, - .watt = 45, - .obp95 = 990, - .obp85 = 890, + .charge_voltage = 15000, + .charge_current = 3000, + .watt = 45, + .obp95 = 990, + .obp85 = 890, }, { - .charge_voltage = 20000, - .charge_current = 3250, - .watt = 65, - .obp95 = 1080, - .obp85 = 960, + .charge_voltage = 20000, + .charge_current = 3250, + .watt = 65, + .obp95 = 1080, + .obp85 = 960, }, { - .charge_voltage = 20000, - .charge_current = 5000, - .watt = 100, - .obp95 = 1660, - .obp85 = 1480, + .charge_voltage = 20000, + .charge_current = 5000, + .watt = 100, + .obp95 = 1660, + .obp85 = 1480, }, }; @@ -259,14 +255,14 @@ void obp_point_85(void) struct npcx_adc_thresh_t adc_obp_point_95 = { .adc_ch = ADC_PWR_IN_IMON, .adc_thresh_cb = obp_point_95, - .thresh_assert = 3300, /* Default */ + .thresh_assert = 3300, /* Default */ }; struct npcx_adc_thresh_t adc_obp_point_85 = { .adc_ch = ADC_PWR_IN_IMON, .adc_thresh_cb = obp_point_85, .lower_or_higher = 1, - .thresh_assert = 0, /* Default */ + .thresh_assert = 0, /* Default */ }; static void set_up_adc_irqs(void) @@ -296,13 +292,13 @@ void set_the_obp(int power_type_index, int adp_type) case TIO1: case TIO2: charge_manager_update_charge( - CHARGE_SUPPLIER_PROPRIETARY, - DEDICATED_CHARGE_PORT, &pi); + CHARGE_SUPPLIER_PROPRIETARY, + DEDICATED_CHARGE_PORT, &pi); break; case TINY: - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, &pi); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, + &pi); break; } } @@ -362,18 +358,18 @@ void adp_id_deferred(void) switch (adp_type) { case TIO1: - power_type_len = sizeof(tio1_power) / - sizeof(struct adpater_id_params); + power_type_len = + sizeof(tio1_power) / sizeof(struct adpater_id_params); memcpy(&power_type, &tio1_power, sizeof(tio1_power)); break; case TIO2: - power_type_len = sizeof(tio2_power) / - sizeof(struct adpater_id_params); + power_type_len = + sizeof(tio2_power) / sizeof(struct adpater_id_params); memcpy(&power_type, &tio2_power, sizeof(tio2_power)); break; case TINY: - power_type_len = sizeof(tiny_power) / - sizeof(struct adpater_id_params); + power_type_len = + sizeof(tiny_power) / sizeof(struct adpater_id_params); memcpy(&power_type, &tiny_power, sizeof(tiny_power)); break; } @@ -405,13 +401,13 @@ static void typec_adapter_setting(void) /* Check the barrel jack is not present */ if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) { adapter_current_ma = charge_manager_get_charger_current(); - power_type_len = sizeof(typec_power) / - sizeof(struct adpater_id_params); + power_type_len = + sizeof(typec_power) / sizeof(struct adpater_id_params); memcpy(&power_type, &typec_power, sizeof(typec_power)); for (i = (power_type_len - 1); i >= 0; i--) { if (adapter_current_ma >= - power_type[i].charge_current) { + power_type[i].charge_current) { set_the_obp(i, adp_type); break; } -- cgit v1.2.1 From f3912219f0220457e8f6c35e3e64e79fcacf2853 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:41 -0600 Subject: zephyr/shim/include/usbc/tcpc_it8xxx2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3744636014e1650913776c5a8dedd96ab02dca2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730839 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_it8xxx2.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h index be275441d8..f8f77a6d18 100644 --- a/zephyr/shim/include/usbc/tcpc_it8xxx2.h +++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h @@ -8,9 +8,9 @@ #define IT8XXX2_TCPC_COMPAT ite_it8xxx2_tcpc -#define TCPC_CONFIG_IT8XXX2(id) \ - { \ - .bus_type = EC_BUS_TYPE_EMBEDDED, \ - .drv = &it8xxx2_tcpm_drv, \ - .flags = 0, \ +#define TCPC_CONFIG_IT8XXX2(id) \ + { \ + .bus_type = EC_BUS_TYPE_EMBEDDED, \ + .drv = &it8xxx2_tcpm_drv, \ + .flags = 0, \ }, -- cgit v1.2.1 From aacba027a4b794d83e382e8eb7d3592f606ab9dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:21 -0600 Subject: include/charge_state_v1.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23ee50668dad6c9ff6ef445a7e0570e3c64047bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730223 Reviewed-by: Jeremy Bettis --- include/charge_state_v1.h | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/include/charge_state_v1.h b/include/charge_state_v1.h index f5d464b655..fbf2ff4c09 100644 --- a/include/charge_state_v1.h +++ b/include/charge_state_v1.h @@ -13,24 +13,22 @@ #define CHARGER_UPDATE_PERIOD (SECOND * 10) /* Power state error flags */ -#define F_CHARGER_INIT BIT(0) /* Charger initialization */ -#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */ -#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */ -#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */ -#define F_BATTERY_MODE BIT(8) /* Battery mode */ -#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */ +#define F_CHARGER_INIT BIT(0) /* Charger initialization */ +#define F_CHARGER_VOLTAGE BIT(1) /* Charger maximum output voltage */ +#define F_CHARGER_CURRENT BIT(2) /* Charger maximum output current */ +#define F_BATTERY_VOLTAGE BIT(3) /* Battery voltage */ +#define F_BATTERY_MODE BIT(8) /* Battery mode */ +#define F_BATTERY_CAPACITY BIT(9) /* Battery capacity */ #define F_BATTERY_STATE_OF_CHARGE BIT(10) /* State of charge, percentage */ -#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */ -#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */ -#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */ +#define F_BATTERY_UNRESPONSIVE BIT(11) /* Battery not responding */ +#define F_BATTERY_NOT_CONNECTED BIT(12) /* Battery not connected */ +#define F_BATTERY_GET_PARAMS BIT(13) /* Any battery parameter bad */ -#define F_BATTERY_MASK (F_BATTERY_VOLTAGE | \ - F_BATTERY_MODE | \ - F_BATTERY_CAPACITY | F_BATTERY_STATE_OF_CHARGE | \ - F_BATTERY_UNRESPONSIVE | F_BATTERY_NOT_CONNECTED | \ - F_BATTERY_GET_PARAMS) -#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | \ - F_CHARGER_INIT) +#define F_BATTERY_MASK \ + (F_BATTERY_VOLTAGE | F_BATTERY_MODE | F_BATTERY_CAPACITY | \ + F_BATTERY_STATE_OF_CHARGE | F_BATTERY_UNRESPONSIVE | \ + F_BATTERY_NOT_CONNECTED | F_BATTERY_GET_PARAMS) +#define F_CHARGER_MASK (F_CHARGER_VOLTAGE | F_CHARGER_CURRENT | F_CHARGER_INIT) /* Power state data * Status collection of charging state machine. -- cgit v1.2.1 From 504e8beebe0af7da38b0b812133553b70dce9111 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:42 -0600 Subject: chip/npcx/config_flash_layout.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d65c1516de534737c9492fb6e1ed5492824d10c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729391 Reviewed-by: Jeremy Bettis --- chip/npcx/config_flash_layout.h | 70 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 79961548c9..168630f582 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -18,56 +18,56 @@ #define CONFIG_MAPPED_STORAGE /* Storage is memory-mapped, but program runs from SRAM */ #define CONFIG_MAPPED_STORAGE_BASE 0x64000000 -#undef CONFIG_FLASH_PSTATE +#undef CONFIG_FLASH_PSTATE #if defined(CHIP_VARIANT_NPCX5M5G) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 #elif defined(CHIP_VARIANT_NPCX5M6G) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 -#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 #elif defined(CHIP_VARIANT_NPCX7M7WB) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000 #elif defined(CHIP_VARIANT_NPCX9M3F) || defined(CHIP_VARIANT_NPCX9M6F) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 #else #error "Unsupported chip variant" #endif /* Header support which is used by booter to copy FW from flash to code ram */ #define NPCX_RO_HEADER -#define CONFIG_RO_HDR_MEM_OFF 0x0 -#define CONFIG_RO_HDR_SIZE 0x40 +#define CONFIG_RO_HDR_MEM_OFF 0x0 +#define CONFIG_RO_HDR_SIZE 0x40 -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* RO firmware in program memory - use all of program memory */ -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE /* * ROM resident area in flash used to store data objects that are not copied * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option. */ -#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE +#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE #define CONFIG_RO_ROM_RESIDENT_SIZE \ (CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE) @@ -75,10 +75,10 @@ * RW firmware in program memory - Identical to RO, only one image loaded at * a time. */ -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE +#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE #define CONFIG_RW_ROM_RESIDENT_SIZE \ (CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE) @@ -102,8 +102,8 @@ * writable flash regions are not a multiple of 64 KiB, then support * for CONFIG_FLASH_MULTIPLE_REGION must be added. */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define NPCX_ERASE_COMMAND CMD_BLOCK_64K_ERASE #if (CONFIG_WP_STORAGE_SIZE != CONFIG_EC_WRITABLE_STORAGE_SIZE) #error "NPCX flash support assumes CONFIG_WP_STORAGE_SIZE and " \ @@ -120,16 +120,16 @@ "size or add support for CONFIG_FLASH_MULTIPLE_REGION." #endif -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ /* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 +#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 /* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE /* RW image resides at start of writable region */ -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ -- cgit v1.2.1 From 2342b98c2afb8c7a49409badc614a2ae9afc190a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:35 -0600 Subject: board/careena/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie7d862ce5f412613e348607d7e14c4b53dbc0a50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728138 Reviewed-by: Jeremy Bettis --- board/careena/board.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/careena/board.h b/board/careena/board.h index 75545cfcaa..e5a847a807 100644 --- a/board/careena/board.h +++ b/board/careena/board.h @@ -17,7 +17,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -41,10 +41,7 @@ #ifndef __ASSEMBLER__ -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; enum battery_type { BATTERY_DYNAPACK_COS, -- cgit v1.2.1 From e9a46f9a08e38cfcff8a91408f4f2943adc1c0f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:32 -0600 Subject: baseboard/zork/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If25144e6d0875838d98178d24faa6de76f77a140 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727955 Reviewed-by: Jeremy Bettis --- baseboard/zork/baseboard.h | 118 +++++++++++++++++++++------------------------ 1 file changed, 56 insertions(+), 62 deletions(-) diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h index e97bcb4e45..2c9920b4de 100644 --- a/baseboard/zork/baseboard.h +++ b/baseboard/zork/baseboard.h @@ -8,22 +8,21 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H -#if (defined(VARIANT_ZORK_TREMBYLE) \ - + defined(VARIANT_ZORK_DALBOZ)) != 1 +#if (defined(VARIANT_ZORK_TREMBYLE) + defined(VARIANT_ZORK_DALBOZ)) != 1 #error Must choose VARIANT_ZORK_TREMBYLE or VARIANT_ZORK_DALBOZ #endif /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q40 /* Internal SPI flash type. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD) | CC_MASK(CC_LPC))) /* * Enable 1 slot of secure temporary storage to support @@ -92,7 +91,7 @@ #define CONFIG_CHIPSET_CAN_THROTTLE #define CONFIG_CHIPSET_RESET_HOOK -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_POWER_COMMON @@ -102,9 +101,9 @@ #define CONFIG_THROTTLE_AP #ifdef VARIANT_ZORK_TREMBYLE - #define CONFIG_FANS FAN_CH_COUNT - #undef CONFIG_FAN_INIT_SPEED - #define CONFIG_FAN_INIT_SPEED 50 +#define CONFIG_FANS FAN_CH_COUNT +#undef CONFIG_FAN_INIT_SPEED +#define CONFIG_FAN_INIT_SPEED 50 #endif #define CONFIG_LED_COMMON @@ -122,10 +121,9 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX - #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI /* * USB ID @@ -141,14 +139,14 @@ #define CONFIG_USB_PD_TCPMV2 #ifndef CONFIG_USB_PD_TCPMV2 - #define CONFIG_USB_PD_TCPMV1 +#define CONFIG_USB_PD_TCPMV1 #else - #define CONFIG_USB_PD_DECODE_SOP - #define CONFIG_USB_DRP_ACC_TRYSRC +#define CONFIG_USB_PD_DECODE_SOP +#define CONFIG_USB_DRP_ACC_TRYSRC - /* Enable TCPMv2 Fast Role Swap */ - /* Turn off until FRSwap is working */ - #undef CONFIG_USB_PD_FRS_TCPC +/* Enable TCPMv2 Fast Role Swap */ +/* Turn off until FRSwap is working */ +#undef CONFIG_USB_PD_FRS_TCPC #endif #define CONFIG_HOSTCMD_PD_CONTROL @@ -165,7 +163,7 @@ * Use a custom HPD function that supports HPD on IO expander. * TODO(b/165622386) remove this when HPD is on EC GPIO. */ -# define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM +#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM #endif #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE @@ -187,19 +185,19 @@ #define CONFIG_USB_MUX_AMD_FP5 #if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_USB_PD_PORT_MAX_COUNT 2 - #define CONFIG_USBC_PPC_NX20P3483 - #define CONFIG_USBC_RETIMER_PS8802 - #define CONFIG_USBC_RETIMER_PS8818 - #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT - #define CONFIG_USB_MUX_RUNTIME_CONFIG - /* USB-A config */ - #define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L - #define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L - /* PS8818 RX Input Termination - default value */ - #define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USBC_PPC_NX20P3483 +#define CONFIG_USBC_RETIMER_PS8802 +#define CONFIG_USBC_RETIMER_PS8818 +#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT +#define CONFIG_USB_MUX_RUNTIME_CONFIG +/* USB-A config */ +#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_CHARGE_EN_L +#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_CHARGE_EN_DB_L +/* PS8818 RX Input Termination - default value */ +#define ZORK_PS8818_RX_INPUT_TERM PS8818_RX_INPUT_TERM_112_OHM #elif defined(VARIANT_ZORK_DALBOZ) - #define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT +#define CONFIG_IO_EXPANDER_PORT_COUNT IOEX_PORT_COUNT #endif /* USB-A config */ @@ -209,13 +207,13 @@ #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP #define CONFIG_USB_PORT_POWER_SMART_INVERTED -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ #define ZORK_AC_PROCHOT_CURRENT_MA 3328 @@ -225,7 +223,7 @@ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on * Depthcharge to boot OS. */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 50000 /* Increase length of history buffer for port80 messages. */ #undef CONFIG_PORT80_HISTORY_LEN @@ -235,30 +233,30 @@ #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 -#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_EEPROM I2C_PORT_SENSOR -#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_USBA0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USBA1 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_AP_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT4_1 +#define I2C_PORT_SENSOR NPCX_I2C_PORT5_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_EEPROM I2C_PORT_SENSOR +#define I2C_PORT_AP_AUDIO NPCX_I2C_PORT6_1 #if defined(VARIANT_ZORK_TREMBYLE) - #define CONFIG_CHARGER_RUNTIME_CONFIG - #define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 - #define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 +#define CONFIG_CHARGER_RUNTIME_CONFIG +#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 +#define I2C_PORT_CHARGER_V0 NPCX_I2C_PORT2_0 +#define I2C_PORT_CHARGER_V1 NPCX_I2C_PORT4_1 +#define I2C_PORT_AP_HDMI NPCX_I2C_PORT7_0 #elif defined(VARIANT_ZORK_DALBOZ) - #define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 - #define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 +#define I2C_PORT_BATTERY_V0 NPCX_I2C_PORT2_0 +#define I2C_PORT_BATTERY_V1 NPCX_I2C_PORT7_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT2_0 #endif -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_MKBP_EVENT /* Host event is required to wake from sleep */ @@ -310,11 +308,7 @@ enum fan_channel { }; #ifdef VARIANT_ZORK_TREMBYLE -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; #endif enum sensor_id { -- cgit v1.2.1 From f4aede8d693df6b92d731c9e494565817ba534d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:20 -0600 Subject: util/comm-host.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf09b37068933a63c2ec5995e3a3857dd8133c9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730323 Reviewed-by: Jeremy Bettis --- util/comm-host.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/util/comm-host.c b/util/comm-host.c index 45d6f85a02..d7911f1d87 100644 --- a/util/comm-host.c +++ b/util/comm-host.c @@ -15,10 +15,8 @@ #include "ec_commands.h" #include "misc_util.h" - -int (*ec_command_proto)(int command, int version, - const void *outdata, int outsize, - void *indata, int insize); +int (*ec_command_proto)(int command, int version, const void *outdata, + int outsize, void *indata, int insize); int (*ec_readmem)(int offset, int bytes, void *dest); @@ -45,8 +43,8 @@ static int fake_readmem(int offset, int bytes, void *dest) if (bytes) { p.size = bytes; - c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), - dest, p.size); + c = ec_command(EC_CMD_READ_MEMMAP, 0, &p, sizeof(p), dest, + p.size); if (c < 0) return c; return p.size; @@ -73,14 +71,12 @@ void set_command_offset(int offset) command_offset = offset; } -int ec_command(int command, int version, - const void *outdata, int outsize, +int ec_command(int command, int version, const void *outdata, int outsize, void *indata, int insize) { /* Offset command code to support sub-devices */ - return ec_command_proto(command_offset + command, version, - outdata, outsize, - indata, insize); + return ec_command_proto(command_offset + command, version, outdata, + outsize, indata, insize); } int comm_init_alt(int interfaces, const char *device_name, int i2c_bus) @@ -99,13 +95,13 @@ int comm_init_alt(int interfaces, const char *device_name, int i2c_bus) dev_is_cros_ec = !strcmp(CROS_EC_DEV_NAME, device_name); /* Fallback to direct LPC on x86 */ - if (dev_is_cros_ec && (interfaces & COMM_LPC) && - comm_init_lpc && !comm_init_lpc()) + if (dev_is_cros_ec && (interfaces & COMM_LPC) && comm_init_lpc && + !comm_init_lpc()) return 0; /* Fallback to direct I2C */ if ((dev_is_cros_ec || i2c_bus != -1) && (interfaces & COMM_I2C) && - comm_init_i2c && !comm_init_i2c(i2c_bus)) + comm_init_i2c && !comm_init_i2c(i2c_bus)) return 0; /* Give up */ @@ -134,11 +130,11 @@ int comm_init_buffer(void) /* read max request / response size from ec for protocol v3+ */ if (ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info, - sizeof(info)) == sizeof(info)) { + sizeof(info)) == sizeof(info)) { int outsize = info.max_request_packet_size - - sizeof(struct ec_host_request); + sizeof(struct ec_host_request); int insize = info.max_response_packet_size - - sizeof(struct ec_host_response); + sizeof(struct ec_host_response); if ((allow_large_buffer) || (outsize < ec_max_outsize)) ec_max_outsize = outsize; if ((allow_large_buffer) || (insize < ec_max_insize)) -- cgit v1.2.1 From 9c9c3792efea7bacf298eac714a1e5a225b3f5c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:51 -0600 Subject: board/coachz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16e14a6cf9037ced9618837d23785c1aaffdcc47 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728126 Reviewed-by: Jeremy Bettis --- board/coachz/board.c | 168 +++++++++++++++++++-------------------------------- 1 file changed, 62 insertions(+), 106 deletions(-) diff --git a/board/coachz/board.c b/board/coachz/board.c index 088c958679..4b363260b2 100644 --- a/board/coachz/board.c +++ b/board/coachz/board.c @@ -36,10 +36,10 @@ #include "task.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -173,8 +173,7 @@ static void ks_change_deferred(void) proximity_detected = !(ks_attached && ks_open); CPRINTS("ks %s %s -> proximity %s", ks_attached ? "attached" : "detached", - ks_open ? "open" : "close", - proximity_detected ? "on" : "off"); + ks_open ? "open" : "close", proximity_detected ? "on" : "off"); debounced_ks_attached = ks_attached; debounced_ks_open = ks_open; @@ -191,48 +190,36 @@ static void ks_interrupt(enum gpio_signal s) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "wlc", - .port = I2C_PORT_WLC, - .kbps = 400, - .scl = GPIO_EC_I2C_WLC_SCL, - .sda = GPIO_EC_I2C_WLC_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "wlc", + .port = I2C_PORT_WLC, + .kbps = 400, + .scl = GPIO_EC_I2C_WLC_SCL, + .sda = GPIO_EC_I2C_WLC_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -240,45 +227,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, /* Base detection */ - [ADC_BASE_DET] = { - "BASE_DET", - NPCX_ADC_CH5, - ADC_MAX_VOLT, - ADC_READ_MAX + 1, - 0 - }, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -290,16 +257,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -364,11 +327,9 @@ static struct bmi_drv_data_t g_bmi260_data; bool is_bmi260_present; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -471,8 +432,8 @@ static void board_detect_motionsensor(void) /* Check base accelgyro chip */ bmi_read8(motion_sensors[LID_ACCEL].port, - motion_sensors[LID_ACCEL].i2c_spi_addr_flags, - BMI260_CHIP_ID, &val); + motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID, + &val); if (val == BMI260_CHIP_ID_MAJOR) { motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL]; motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO]; @@ -553,9 +514,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); void board_hibernate(void) { @@ -565,8 +526,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -662,8 +622,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -691,7 +650,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -715,24 +673,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From a98113a6475d2d046769af17f126d820f7474046 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:56 -0600 Subject: chip/stm32/usb-stream.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If8ad69ef16222dbed95d8ba0fd0b1d3cc90a69b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729548 Reviewed-by: Jeremy Bettis --- chip/stm32/usb-stream.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/chip/stm32/usb-stream.c b/chip/stm32/usb-stream.c index 7429832f10..f762c466a1 100644 --- a/chip/stm32/usb-stream.c +++ b/chip/stm32/usb-stream.c @@ -28,19 +28,16 @@ static size_t rx_read(struct usb_stream_config const *config) if (count > queue_space(config->producer.queue)) return 0; - return queue_add_memcpy(config->producer.queue, - (void *) address, - count, + return queue_add_memcpy(config->producer.queue, (void *)address, count, memcpy_from_usbram); } static size_t tx_write(struct usb_stream_config const *config) { uintptr_t address = btable_ep[config->endpoint].tx_addr; - size_t count = queue_remove_memcpy(config->consumer.queue, - (void *) address, - config->tx_size, - memcpy_to_usbram); + size_t count = queue_remove_memcpy(config->consumer.queue, + (void *)address, config->tx_size, + memcpy_to_usbram); btable_ep[config->endpoint].tx_count = count; @@ -127,36 +124,33 @@ void usb_stream_event(struct usb_stream_config const *config, i = config->endpoint; - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); + btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); btable_ep[i].tx_count = 0; - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); + btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); btable_ep[i].rx_count = usb_ep_rx_size(config->rx_size); config->state->rx_waiting = 0; - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ + STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ (rx_disabled(config) ? EP_RX_NAK : EP_RX_VALID)); } int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, + struct usart_config const *usart, int interface, usb_uint *rx_buf, usb_uint *tx_buf) { struct usb_setup_packet req; usb_read_setup_packet(rx_buf, &req); - if (req.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) + if (req.bmRequestType != + (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE)) return -1; - if (req.wIndex != interface || - req.wLength != 0) + if (req.wIndex != interface || req.wLength != 0) return -1; switch (req.bRequest) { -- cgit v1.2.1 From d0616ea4047a2f3c608882a66b1f0b620d04b6f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:40 -0600 Subject: include/mock/fp_sensor_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I160cb8173bd6fabcba022e99d173526f8f91cf8a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730357 Reviewed-by: Jeremy Bettis --- include/mock/fp_sensor_mock.h | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/include/mock/fp_sensor_mock.h b/include/mock/fp_sensor_mock.h index 432802348c..3de4bcadb9 100644 --- a/include/mock/fp_sensor_mock.h +++ b/include/mock/fp_sensor_mock.h @@ -28,20 +28,21 @@ struct mock_ctrl_fp_sensor { int fp_maintenance_return; }; -#define MOCK_CTRL_DEFAULT_FP_SENSOR \ -(struct mock_ctrl_fp_sensor) { \ - .fp_sensor_init_return = EC_SUCCESS, \ - .fp_sensor_deinit_return = EC_SUCCESS, \ - .fp_sensor_get_info_return = EC_SUCCESS, \ - .fp_sensor_finger_status_return = FINGER_NONE, \ - .fp_sensor_acquire_image_return = 0, \ - .fp_sensor_acquire_image_with_mode_return = 0, \ - .fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \ - .fp_enrollment_begin_return = 0, \ - .fp_enrollment_finish_return = 0, \ - .fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK, \ - .fp_maintenance_return = EC_SUCCESS \ -} +#define MOCK_CTRL_DEFAULT_FP_SENSOR \ + (struct mock_ctrl_fp_sensor) \ + { \ + .fp_sensor_init_return = EC_SUCCESS, \ + .fp_sensor_deinit_return = EC_SUCCESS, \ + .fp_sensor_get_info_return = EC_SUCCESS, \ + .fp_sensor_finger_status_return = FINGER_NONE, \ + .fp_sensor_acquire_image_return = 0, \ + .fp_sensor_acquire_image_with_mode_return = 0, \ + .fp_finger_match_return = EC_MKBP_FP_ERR_MATCH_YES_UPDATED, \ + .fp_enrollment_begin_return = 0, \ + .fp_enrollment_finish_return = 0, \ + .fp_finger_enroll_return = EC_MKBP_FP_ERR_ENROLL_OK, \ + .fp_maintenance_return = EC_SUCCESS \ + } extern struct mock_ctrl_fp_sensor mock_ctrl_fp_sensor; -- cgit v1.2.1 From b4930688879db7a220605adfb4c70e32173205d2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:21 -0600 Subject: common/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide385413aa8080385a6b632a832cf0cb35fa4785 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729562 Reviewed-by: Jeremy Bettis --- common/adc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common/adc.c b/common/adc.c index c9e3a36e57..b83a3fb98a 100644 --- a/common/adc.c +++ b/common/adc.c @@ -61,9 +61,7 @@ static int command_adc(int argc, char **argv) return EC_SUCCESS; } } -DECLARE_CONSOLE_COMMAND(adc, command_adc, - "[name]", - "Print ADC channel(s)"); +DECLARE_CONSOLE_COMMAND(adc, command_adc, "[name]", "Print ADC channel(s)"); static enum ec_status hc_adc_read(struct host_cmd_handler_args *args) { -- cgit v1.2.1 From 04c3e677e99015ea00e1e0fb44585f96e3b05273 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:06 -0600 Subject: board/spherion/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec37cae59e5c3eeea7d9ce3ef733c8eb11eadfc0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728946 Reviewed-by: Jeremy Bettis --- board/spherion/led.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/board/spherion/led.c b/board/spherion/led.c index aad85d02c1..bd41fe24cb 100644 --- a/board/spherion/led.c +++ b/board/spherion/led.c @@ -16,19 +16,26 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -61,9 +68,8 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { if (led_id == EC_LED_ID_BATTERY_LED) { brightness_range[EC_LED_COLOR_AMBER] = - MT6360_LED_BRIGHTNESS_MAX; - brightness_range[EC_LED_COLOR_BLUE] = - MT6360_LED_BRIGHTNESS_MAX; + MT6360_LED_BRIGHTNESS_MAX; + brightness_range[EC_LED_COLOR_BLUE] = MT6360_LED_BRIGHTNESS_MAX; } } -- cgit v1.2.1 From 13a4a157e88c39fe4467ee57854e156fd8b17ac6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:10 -0600 Subject: power/rk3288.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5e98e2ea2afcfcc2ab32f97720adf012fb8dad60 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730467 Reviewed-by: Jeremy Bettis --- power/rk3288.c | 42 ++++++++++++++++++------------------------ 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/power/rk3288.c b/power/rk3288.c index 851a8b4e9d..6483deec71 100644 --- a/power/rk3288.c +++ b/power/rk3288.c @@ -25,7 +25,7 @@ #include "battery.h" #include "charge_state.h" -#include "chipset.h" /* This module implements chipset functions too */ +#include "chipset.h" /* This module implements chipset functions too */ #include "clock.h" #include "common.h" #include "console.h" @@ -43,14 +43,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* masks for power signals */ #define IN_POWER_GOOD POWER_SIGNAL_MASK(RK_POWER_GOOD) #define IN_SUSPEND POWER_SIGNAL_MASK(RK_SUSPEND_ASSERTED) /* Long power key press to force shutdown */ -#define DELAY_FORCE_SHUTDOWN (8 * SECOND) +#define DELAY_FORCE_SHUTDOWN (8 * SECOND) /* * If the power key is pressed to turn on, then held for this long, we @@ -60,7 +60,7 @@ * into the inner loop, waiting for next event to occur (power button * press or power good == 0). */ -#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) +#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) /* * The hold time for pulling down the PMIC_WARM_RESET_L pin so that @@ -101,11 +101,9 @@ enum power_request_t { static enum power_request_t power_request; - /* Forward declaration */ static void chipset_turn_off_power_rails(void); - /** * Set the PMIC WARM RESET signal. * @@ -117,7 +115,6 @@ static void set_pmic_warm_reset(int asserted) gpio_set_level(GPIO_PMIC_WARM_RESET_L, asserted ? 0 : 1); } - /** * Set the PMIC PWRON signal. * @@ -161,7 +158,7 @@ static int check_for_power_off_event(void) pressed = 1; } else if (power_request == POWER_REQ_OFF) { power_request = POWER_REQ_NONE; - return 4; /* return non-zero for shudown down */ + return 4; /* return non-zero for shudown down */ } now = get_time(); @@ -294,13 +291,11 @@ static int check_for_power_on_event(void) /* check if system is already ON */ if (power_get_signals() & IN_POWER_GOOD) { if (ap_off_flag) { - CPRINTS( - "system is on, but " + CPRINTS("system is on, but " "EC_RESET_FLAG_AP_OFF is on"); return 0; } else { - CPRINTS( - "system is on, thus clear " + CPRINTS("system is on, thus clear " "auto_power_on"); /* no need to arrange another power on */ auto_power_on = 0; @@ -391,7 +386,7 @@ void chipset_reset(enum chipset_shutdown_reason reason) report_ap_reset(reason); CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms", - PMIC_WARM_RESET_L_HOLD_TIME / MSEC); + PMIC_WARM_RESET_L_HOLD_TIME / MSEC); set_pmic_warm_reset(1); usleep(PMIC_WARM_RESET_L_HOLD_TIME); set_pmic_warm_reset(0); @@ -437,16 +432,17 @@ enum power_state power_handle_state(enum power_state state) if (power_wait_signals(IN_POWER_GOOD) == EC_SUCCESS) { CPRINTS("POWER_GOOD seen"); if (power_button_wait_for_release( - DELAY_SHUTDOWN_ON_POWER_HOLD) == - EC_SUCCESS) { + DELAY_SHUTDOWN_ON_POWER_HOLD) == + EC_SUCCESS) { power_button_was_pressed = 0; set_pmic_pwron(0); /* setup misc gpio for S3/S0 functionality */ - gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT - | GPIO_INT_BOTH | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_EC_INT_L, GPIO_OUTPUT - | GPIO_OUT_HIGH); + gpio_set_flags(GPIO_SUSPEND_L, + GPIO_INPUT | GPIO_INT_BOTH | + GPIO_PULL_DOWN); + gpio_set_flags(GPIO_EC_INT_L, + GPIO_OUTPUT | GPIO_OUT_HIGH); /* Call hooks now that AP is running */ hook_notify(HOOK_CHIPSET_STARTUP); @@ -521,7 +517,7 @@ static void powerbtn_rockchip_changed(void) task_wake(TASK_ID_CHIPSET); } DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, powerbtn_rockchip_changed, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); /*****************************************************************************/ /* Console debug command */ @@ -542,7 +538,7 @@ enum power_state_t { PSTATE_COUNT, }; -static const char * const state_name[] = { +static const char *const state_name[] = { "unknown", "off", "suspend", @@ -577,6 +573,4 @@ static int command_power(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(power, command_power, - "on/off", - "Turn AP power on/off"); +DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off"); -- cgit v1.2.1 From 8f70f5ff6452ac101e02819f8e085da89b7c207e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:50 -0600 Subject: board/wheelie/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac9553ad5045022380bbc175c23c3e6862701408 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729115 Reviewed-by: Jeremy Bettis --- board/wheelie/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/wheelie/cbi_ssfc.h b/board/wheelie/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/wheelie/cbi_ssfc.h +++ b/board/wheelie/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 54018c6795b762a844b72163f3ce05028af754d0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:50 -0600 Subject: include/mock/tcpc_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5cdfc07bb16204d7d655bba48b2eb2d5b74b8ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730361 Reviewed-by: Jeremy Bettis --- include/mock/tcpc_mock.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/mock/tcpc_mock.h b/include/mock/tcpc_mock.h index f4db14efb7..861ce03434 100644 --- a/include/mock/tcpc_mock.h +++ b/include/mock/tcpc_mock.h @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - /* Mock for the TCPC interface */ +/* Mock for the TCPC interface */ #include "usb_pd_tcpm.h" #include "usb_pd.h" @@ -28,7 +28,6 @@ struct mock_tcpc_ctrl { enum tcpc_rp_value rp; enum tcpc_cc_polarity polarity; } last; - }; /* Reset this TCPC mock */ -- cgit v1.2.1 From 20bbcb4c7d7bfb488c7240fce30f6ed0cf0c0e03 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:28 -0600 Subject: core/nds32/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4911d12ff4faf9c90dd6f923821a3ef280fb7e9d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729861 Reviewed-by: Jeremy Bettis --- core/nds32/cpu.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/core/nds32/cpu.h b/core/nds32/cpu.h index 3bd5a93efc..3bc567d4ef 100644 --- a/core/nds32/cpu.h +++ b/core/nds32/cpu.h @@ -15,9 +15,9 @@ #define TASK_SCRATCHPAD_SIZE (18) /* Process Status Word bits */ -#define PSW_GIE BIT(0) /* Global Interrupt Enable */ -#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ -#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) +#define PSW_GIE BIT(0) /* Global Interrupt Enable */ +#define PSW_INTL_SHIFT 1 /* Interrupt Stack Level */ +#define PSW_INTL_MASK (0x3 << PSW_INTL_SHIFT) #ifndef __ASSEMBLER__ @@ -26,28 +26,28 @@ /* write Process Status Word privileged register */ static inline void set_psw(uint32_t val) { - asm volatile ("mtsr %0, $PSW" : : "r"(val)); + asm volatile("mtsr %0, $PSW" : : "r"(val)); } /* read Process Status Word privileged register */ static inline uint32_t get_psw(void) { uint32_t ret; - asm volatile ("mfsr %0, $PSW" : "=r"(ret)); + asm volatile("mfsr %0, $PSW" : "=r"(ret)); return ret; } /* write Interruption Program Counter privileged register */ static inline void set_ipc(uint32_t val) { - asm volatile ("mtsr %0, $IPC" : : "r"(val)); + asm volatile("mtsr %0, $IPC" : : "r"(val)); } /* read Interruption Program Counter privileged register */ static inline uint32_t get_ipc(void) { uint32_t ret; - asm volatile ("mfsr %0, $IPC" : "=r"(ret)); + asm volatile("mfsr %0, $IPC" : "=r"(ret)); return ret; } @@ -55,7 +55,7 @@ static inline uint32_t get_ipc(void) static inline uint32_t get_itype(void) { uint32_t ret; - asm volatile ("mfsr %0, $ITYPE" : "=r"(ret)); + asm volatile("mfsr %0, $ITYPE" : "=r"(ret)); return ret; } -- cgit v1.2.1 From c7eb5a5cce1aaf6a07231085e63a36c3431ee920 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:52 -0600 Subject: common/power_button_x86.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91d391bd5d39b8263dcc343bbf132b4fd71e9597 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729701 Reviewed-by: Jeremy Bettis --- common/power_button_x86.c | 43 ++++++++++++++++--------------------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/common/power_button_x86.c b/common/power_button_x86.c index fd24f7a75b..3e2cb51ef2 100644 --- a/common/power_button_x86.c +++ b/common/power_button_x86.c @@ -23,7 +23,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SWITCH, outstr) -#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args) /* * x86 chipsets have a hardware timer on the power button input which causes @@ -54,14 +54,14 @@ * to host v v * @S0 make code break code */ -#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */ -#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */ +#define PWRBTN_DELAY_T0 (32 * MSEC) /* 32ms (PCH requires >16ms) */ +#define PWRBTN_DELAY_T1 (4 * SECOND - PWRBTN_DELAY_T0) /* 4 secs - t0 */ /* * Length of time to stretch initial power button press to give chipset a * chance to wake up (~100ms) and react to the press (~16ms). Also used as * pulse length for simulated power button presses when the system is off. */ -#define PWRBTN_INITIAL_US (200 * MSEC) +#define PWRBTN_INITIAL_US (200 * MSEC) enum power_button_state { /* Button up; state machine idle */ @@ -92,18 +92,9 @@ enum power_button_state { }; static enum power_button_state pwrbtn_state = PWRBTN_STATE_IDLE; -static const char * const state_names[] = { - "idle", - "pressed", - "t0", - "t1", - "held", - "lid-open", - "released", - "eat-release", - "init-on", - "recovery", - "was-off", +static const char *const state_names[] = { + "idle", "pressed", "t0", "t1", "held", "lid-open", + "released", "eat-release", "init-on", "recovery", "was-off", }; /* @@ -139,7 +130,7 @@ static void set_pwrbtn_to_pch(int high, int init) */ #ifdef CONFIG_CHARGER if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !high && - (charge_want_shutdown() || charge_prevent_power_on(!init))) { + (charge_want_shutdown() || charge_prevent_power_on(!init))) { CPRINTS("PB PCH pwrbtn ignored due to battery level"); high = 1; } @@ -346,8 +337,8 @@ static void state_machine(uint64_t tnow) if (!IS_ENABLED(CONFIG_CHARGER) || charge_prevent_power_on(0)) { if (tnow > - (tpb_task_start + - CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) { + (tpb_task_start + + CONFIG_POWER_BUTTON_INIT_TIMEOUT * SECOND)) { pwrbtn_state = PWRBTN_STATE_IDLE; break; } @@ -366,9 +357,9 @@ static void state_machine(uint64_t tnow) #ifdef CONFIG_DELAY_DSW_PWROK_TO_PWRBTN /* Check if power button is ready. If not, we'll come back. */ if (get_time().val - get_time_dsw_pwrok() < - CONFIG_DSW_PWROK_TO_PWRBTN_US) { + CONFIG_DSW_PWROK_TO_PWRBTN_US) { tnext_state = get_time_dsw_pwrok() + - CONFIG_DSW_PWROK_TO_PWRBTN_US; + CONFIG_DSW_PWROK_TO_PWRBTN_US; break; } #endif @@ -444,7 +435,7 @@ void power_button_task(void *u) * early.) */ CPRINTS("PB task %d = %s, wait %d", pwrbtn_state, - state_names[pwrbtn_state], d); + state_names[pwrbtn_state], d); task_wait_event(d); } } @@ -533,7 +524,6 @@ static enum ec_status hc_config_powerbtn_x86(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_CONFIG_POWER_BUTTON, hc_config_powerbtn_x86, EC_VER_MASK(0)); - /* * Currently, the only reason why we disable power button pulse is to allow * detachable menu on AP to use power button for selection purpose without @@ -554,8 +544,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, power_button_pulse_setting_reset, DECLARE_HOOK(HOOK_CHIPSET_RESUME, power_button_pulse_setting_reset, HOOK_PRIO_DEFAULT); -#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */ -#define POWER_BUTTON_HOOK_VERSION 1 +#define POWER_BUTTON_SYSJUMP_TAG 0x5042 /* PB */ +#define POWER_BUTTON_HOOK_VERSION 1 static void power_button_pulse_setting_restore_state(void) { @@ -574,8 +564,7 @@ DECLARE_HOOK(HOOK_INIT, power_button_pulse_setting_restore_state, static void power_button_pulse_setting_preserve_state(void) { - system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, - POWER_BUTTON_HOOK_VERSION, + system_add_jump_tag(POWER_BUTTON_SYSJUMP_TAG, POWER_BUTTON_HOOK_VERSION, sizeof(power_button_pulse_enabled), &power_button_pulse_enabled); } -- cgit v1.2.1 From 5f08fdbbb4edc315e7436e9940f68e0e7916cf96 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:44 -0600 Subject: board/banshee/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I631ef39efb77191106c15202bf600dc93df7af78 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727999 Reviewed-by: Jeremy Bettis --- board/banshee/fw_config.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/banshee/fw_config.h b/board/banshee/fw_config.h index 6800c492ad..1771b05867 100644 --- a/board/banshee/fw_config.h +++ b/board/banshee/fw_config.h @@ -14,7 +14,6 @@ * Source of truth is the project/brya/brya/config.star configuration file. */ - enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, KEYBOARD_BACKLIGHT_ENABLED = 1 @@ -22,11 +21,11 @@ enum ec_cfg_keyboard_backlight_type { union banshee_cbi_fw_config { struct { - uint32_t sd_db : 2; - uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From 79a076288b0e20f4d452d7682cd64d4e4900b623 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:53 -0600 Subject: driver/tcpm/ite_pd_intc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ca926bb9d1df98a0358be6a5a14cfe1a6e2ba6b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730094 Reviewed-by: Jeremy Bettis --- driver/tcpm/ite_pd_intc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/tcpm/ite_pd_intc.c b/driver/tcpm/ite_pd_intc.c index 2b5a391dfe..d271d0cf87 100644 --- a/driver/tcpm/ite_pd_intc.c +++ b/driver/tcpm/ite_pd_intc.c @@ -16,8 +16,8 @@ void chip_pd_irq(enum usbpd_port port) /* check status */ if (IS_ENABLED(IT83XX_INTC_FAST_SWAP_SUPPORT) && - IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) && - IS_ENABLED(CONFIG_USB_PD_REV30)) { + IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) && + IS_ENABLED(CONFIG_USB_PD_REV30)) { /* * FRS detection must handle first, because we need to short * the interrupt -> board_frs_handler latency-critical time. -- cgit v1.2.1 From 7429e84bca0c0e8462cc4252d43c152c2260d2a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:39 -0600 Subject: board/discovery/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd2c693b109b4c4560d3ad73278720b94a783b54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728248 Reviewed-by: Jeremy Bettis --- board/discovery/board.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/board/discovery/board.c b/board/discovery/board.c index 0d4cde2e7c..74c187bf08 100644 --- a/board/discovery/board.c +++ b/board/discovery/board.c @@ -39,10 +39,8 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT); */ static struct usart_config const loopback_usart; -static struct queue const loopback_queue = - QUEUE_DIRECT(64, uint8_t, - loopback_usart.producer, - loopback_usart.consumer); +static struct queue const loopback_queue = QUEUE_DIRECT( + 64, uint8_t, loopback_usart.producer, loopback_usart.consumer); static struct usart_rx_dma const loopback_rx_dma = USART_RX_DMA(STM32_DMAC_CH6, 32); @@ -50,14 +48,9 @@ static struct usart_rx_dma const loopback_rx_dma = static struct usart_tx_dma const loopback_tx_dma = USART_TX_DMA(STM32_DMAC_CH7, 16); -static struct usart_config const loopback_usart = - USART_CONFIG(usart2_hw, - loopback_rx_dma.usart_rx, - loopback_tx_dma.usart_tx, - 115200, - 0, - loopback_queue, - loopback_queue); +static struct usart_config const loopback_usart = USART_CONFIG( + usart2_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200, + 0, loopback_queue, loopback_queue); /****************************************************************************** * Initialize board. -- cgit v1.2.1 From 125d776fbd8f88b14bda0ceb4c1f15c150b87694 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:41 -0600 Subject: chip/npcx/sib_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ca6285c1df845f4a1c2a1f648c138934e4eff15 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729434 Reviewed-by: Jeremy Bettis --- chip/npcx/sib_chip.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h index 1687c90925..bbea199e72 100644 --- a/chip/npcx/sib_chip.h +++ b/chip/npcx/sib_chip.h @@ -7,15 +7,14 @@ /* NPCX-specific SIB module for Chrome EC */ /* Super-IO index and register definitions */ -#define INDEX_SID 0x20 -#define INDEX_CHPREV 0x24 -#define INDEX_SRID 0x27 +#define INDEX_SID 0x20 +#define INDEX_CHPREV 0x24 +#define INDEX_SRID 0x27 -#define SIO_OFFSET 0x4E +#define SIO_OFFSET 0x4E /* Super-IO register write function */ -void sib_write_reg(uint8_t io_offset, uint8_t index_value, - uint8_t io_data); +void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data); /* Super-IO register read function */ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value); /* Emulate host to read Keyboard I/O */ -- cgit v1.2.1 From a3171cafb2aba073e9dfdf9c68e8332940a32627 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:45 -0600 Subject: board/lick/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If47e88088ea91e5f755fae56e684bb34bc1ce6b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728624 Reviewed-by: Jeremy Bettis --- board/lick/led.c | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/board/lick/led.c b/board/lick/led.c index a7832c5e78..21361fc64a 100644 --- a/board/lick/led.c +++ b/board/lick/led.c @@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 5d0fafb8e6a8f74f95e6b1d7f8ffd80ed6bcac24 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:58 -0600 Subject: board/banshee/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2eb1d3acd41d36c880414dfa0c291ade911d301f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728024 Reviewed-by: Jeremy Bettis --- board/banshee/sensors.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/board/banshee/sensors.c b/board/banshee/sensors.c index b4b6360984..4a8e00f7ce 100644 --- a/board/banshee/sensors.c +++ b/board/banshee/sensors.c @@ -40,7 +40,6 @@ struct adc_t adc_channels[] = { }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - /* CM32183 private data */ static struct als_drv_data_t g_cm32183_data = { /** @@ -120,8 +119,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(80), \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ @@ -152,8 +151,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_AMBIENT \ - { \ +#define THERMAL_AMBIENT \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(85), \ [EC_TEMP_THRESH_HIGH] = C_TO_K(95), \ @@ -183,8 +182,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(90), \ [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ @@ -206,8 +205,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_WWAN \ - { \ +#define THERMAL_WWAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ -- cgit v1.2.1 From 6b18e1c61f3058463c86a1b546a0b438cce6f791 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:05 -0600 Subject: test/usb_pd_int.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I916de5a57216e7bd726d8ac8d512e998dc5be369 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730540 Reviewed-by: Jeremy Bettis --- test/usb_pd_int.c | 92 +++++++++++++++++++++++++++---------------------------- 1 file changed, 45 insertions(+), 47 deletions(-) diff --git a/test/usb_pd_int.c b/test/usb_pd_int.c index 5d3cbbf0f2..c0caa67bcb 100644 --- a/test/usb_pd_int.c +++ b/test/usb_pd_int.c @@ -19,11 +19,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .driver = &mock_usb_mux_driver, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .driver = &mock_usb_mux_driver, +} }; void board_reset_pd_mcu(void) { @@ -32,71 +30,71 @@ void board_reset_pd_mcu(void) static int deferred_resume_called; void pd_deferred_resume(int port) { - deferred_resume_called = 1; + deferred_resume_called = 1; } static int num_events; uint16_t tcpc_get_alert_status(void) { - if (--num_events > 0) - return PD_STATUS_TCPC_ALERT_0; - else - return 0; + if (--num_events > 0) + return PD_STATUS_TCPC_ALERT_0; + else + return 0; } test_static int test_storm_not_triggered(void) { - num_events = 100; - deferred_resume_called = 0; - schedule_deferred_pd_interrupt(PORT0); - task_wait_event(SECOND); - TEST_EQ(deferred_resume_called, 0, "%d"); + num_events = 100; + deferred_resume_called = 0; + schedule_deferred_pd_interrupt(PORT0); + task_wait_event(SECOND); + TEST_EQ(deferred_resume_called, 0, "%d"); - return EC_SUCCESS; + return EC_SUCCESS; } test_static int test_storm_triggered(void) { - num_events = 1000; - deferred_resume_called = 0; - schedule_deferred_pd_interrupt(PORT0); - task_wait_event(SECOND); - TEST_EQ(deferred_resume_called, 1, "%d"); + num_events = 1000; + deferred_resume_called = 0; + schedule_deferred_pd_interrupt(PORT0); + task_wait_event(SECOND); + TEST_EQ(deferred_resume_called, 1, "%d"); - return EC_SUCCESS; + return EC_SUCCESS; } test_static int test_storm_not_triggered_for_32bit_overflow(void) { - int i; - timestamp_t time; - - /* - * Ensure the MSB is 1 for overflow comparison tests. - * But make sure not to move time backwards. - */ - time.val = (get_time().val + 0x100000000) | 0xff000000; - force_time(time); - - /* - * 100 events every second for 10 seconds should never trigger - * a shutdown call. - */ - for (i = 0; i < 10; ++i) { - num_events = 100; - deferred_resume_called = 0; - schedule_deferred_pd_interrupt(PORT0); - task_wait_event(SECOND); - - TEST_EQ(deferred_resume_called, 0, "%d"); - } - - return EC_SUCCESS; + int i; + timestamp_t time; + + /* + * Ensure the MSB is 1 for overflow comparison tests. + * But make sure not to move time backwards. + */ + time.val = (get_time().val + 0x100000000) | 0xff000000; + force_time(time); + + /* + * 100 events every second for 10 seconds should never trigger + * a shutdown call. + */ + for (i = 0; i < 10; ++i) { + num_events = 100; + deferred_resume_called = 0; + schedule_deferred_pd_interrupt(PORT0); + task_wait_event(SECOND); + + TEST_EQ(deferred_resume_called, 0, "%d"); + } + + return EC_SUCCESS; } void before_test(void) { - pd_set_suspend(PORT0, 0); + pd_set_suspend(PORT0, 0); } void run_test(int argc, char **argv) -- cgit v1.2.1 From ca622c590da768770b014b2a12d2f56baae1ae23 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:35 -0600 Subject: board/oak/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibde4c31a3b3ff022359347d375a4f7fad2217113 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728793 Reviewed-by: Jeremy Bettis --- board/oak/usb_pd_policy.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/board/oak/usb_pd_policy.c b/board/oak/usb_pd_policy.c index a4e62ebe88..aaa69bb322 100644 --- a/board/oak/usb_pd_policy.c +++ b/board/oak/usb_pd_policy.c @@ -18,17 +18,15 @@ #include "usb_mux.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 1); + gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1); /* Provide VBUS */ - gpio_set_level(port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN, 1); + gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1); /* notify host of power info change */ pd_send_host_event(PD_EVENT_POWER_CHANGE); @@ -39,8 +37,7 @@ int pd_set_power_supply_ready(int port) void pd_power_supply_reset(int port) { /* Disable VBUS */ - gpio_set_level(port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN, 0); + gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0); /* notify host of power info change */ pd_send_host_event(PD_EVENT_POWER_CHANGE); -- cgit v1.2.1 From 5516fe8e9b6ef262b22d79c9bb5ce3c6edc1f037 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:19 -0600 Subject: board/primus/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0552a52bdfe2e0be0eda3bd59c81623037667df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727756 Reviewed-by: Jeremy Bettis --- board/primus/board.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/board/primus/board.c b/board/primus/board.c index d0fa9f6cae..0f98512725 100644 --- a/board/primus/board.c +++ b/board/primus/board.c @@ -30,8 +30,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) #define KBLIGHT_LED_ON_LVL 100 #define KBLIGHT_LED_OFF_LVL 0 @@ -93,8 +93,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -123,7 +123,7 @@ static void keyboard_init(void) DECLARE_HOOK(HOOK_INIT, keyboard_init, HOOK_PRIO_DEFAULT); __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Need to set different input current limit depend on system state. @@ -131,15 +131,14 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ if (((max_ma == PD_MAX_CURRENT_MA) && - chipset_in_state(CHIPSET_STATE_ANY_OFF)) || - (max_ma != PD_MAX_CURRENT_MA)) + chipset_in_state(CHIPSET_STATE_ANY_OFF)) || + (max_ma != PD_MAX_CURRENT_MA)) charge_ma = charge_ma * 97 / 100; else charge_ma = charge_ma * 93 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } static void configure_input_current_limit(void) @@ -155,16 +154,16 @@ static void configure_input_current_limit(void) adapter_current_ma = charge_manager_get_charger_current(); if ((adapter_current_ma == PD_MAX_CURRENT_MA) && - chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND)) + chipset_in_or_transitioning_to_state(CHIPSET_STATE_SUSPEND)) adapter_current_ma = PD_MAX_SUSPEND_CURRENT_MA; else adapter_current_ma = adapter_current_ma * 97 / 100; charge_set_input_current_limit(MAX(adapter_current_ma, - CONFIG_CHARGER_INPUT_CURRENT), - adapter_current_mv); + CONFIG_CHARGER_INPUT_CURRENT), + adapter_current_mv); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, configure_input_current_limit, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, configure_input_current_limit, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 2fc9be2eea54071e33f92d369722e7baa3c234a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:34 -0600 Subject: include/usb_pd_tbt.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I67e5873406379e0d25b963e1fb70d699cd2aaf61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730442 Reviewed-by: Jeremy Bettis --- include/usb_pd_tbt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb_pd_tbt.h b/include/usb_pd_tbt.h index e052052813..d44a76d59f 100644 --- a/include/usb_pd_tbt.h +++ b/include/usb_pd_tbt.h @@ -106,7 +106,7 @@ enum vendor_specific_support { /* TBT Alternate Mode */ #define TBT_ALTERNATE_MODE 0x0001 -#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x) & 0xff) == TBT_ALTERNATE_MODE) +#define PD_VDO_RESP_MODE_INTEL_TBT(x) (((x)&0xff) == TBT_ALTERNATE_MODE) union tbt_mode_resp_device { struct { -- cgit v1.2.1 From 9a2cc1d0e208dba24617a2dea0273c387087920e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:34 -0600 Subject: board/servo_v4p1/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8906f6148b6b67e152845b3a4fbaf525ce06bdc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728922 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/board.c | 155 +++++++++++++++++++---------------------------- 1 file changed, 63 insertions(+), 92 deletions(-) diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c index 3284b4ef58..80a701358e 100644 --- a/board/servo_v4p1/board.c +++ b/board/servo_v4p1/board.c @@ -182,9 +182,9 @@ static void tcpc_evt(enum gpio_signal signal) update_status_fusb302b(); } -#define HOST_HUB 0 +#define HOST_HUB 0 struct uhub_i2c_iface_t uhub_config[] = { - {I2C_PORT_MASTER, GL3590_I2C_ADDR0}, + { I2C_PORT_MASTER, GL3590_I2C_ADDR0 }, }; static void host_hub_evt(void) @@ -231,8 +231,8 @@ void ext_hpd_detection_enable(int enable) #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /****************************************************************************** * Board pre-init function. @@ -276,23 +276,22 @@ void board_config_pre_init(void) /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)}, - [ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, - [ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, - [ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)}, - [ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)}, - [ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)}, + [ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) }, + [ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) }, + [ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) }, + [ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) }, + [ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) }, + [ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 /****************************************************************************** * Forward USART3 as a simple USB serial interface. @@ -301,29 +300,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); static struct usart_config const usart3; struct usb_stream_config const usart3_usb; -static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t, - usart3.producer, usart3_usb.consumer); -static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t, - usart3_usb.producer, usart3.consumer); +static struct queue const usart3_to_usb = + QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer); +static struct queue const usb_to_usart3 = + QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer); static struct usart_config const usart3 = - USART_CONFIG(usart3_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart3_to_usb, - usb_to_usart3); - -USB_STREAM_CONFIG(usart3_usb, - USB_IFACE_USART3_STREAM, - USB_STR_USART3_STREAM_NAME, - USB_EP_USART3_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart3, - usart3_to_usb) + USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart3_to_usb, usb_to_usart3); +USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM, + USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3, + usart3_to_usb) /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -332,46 +321,34 @@ USB_STREAM_CONFIG(usart3_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 9600, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG_USART_IFACE(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb, - usart4) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0, + usart4_to_usb, usb_to_usart4); +USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart4, usart4_to_usb, usart4) /* * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy * UEFI and kernel requirements (see b/183857501). */ -const struct usb_interface_descriptor -USB_IFACE_DESC(USB_IFACE_EMPTY) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_EMPTY, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, +const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_EMPTY, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = 0, .bInterfaceProtocol = 0, - .iInterface = 0, + .iInterface = 0, }; /****************************************************************************** @@ -379,40 +356,38 @@ USB_IFACE_DESC(USB_IFACE_EMPTY) = { */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4p1"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"), - [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); - - /****************************************************************************** * Support I2C bridging over USB. */ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } - +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Initialize board. @@ -547,18 +522,14 @@ void tick_event(void) DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT); struct ioexpander_config_t ioex_config[] = { - [0] = { - .drv = &tca64xxa_ioexpander_drv, + [0] = { .drv = &tca64xxa_ioexpander_drv, .i2c_host_port = TCA6416A_PORT, .i2c_addr_flags = TCA6416A_ADDR, - .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A - }, - [1] = { - .drv = &tca64xxa_ioexpander_drv, + .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A }, + [1] = { .drv = &tca64xxa_ioexpander_drv, .i2c_host_port = TCA6424A_PORT, .i2c_addr_flags = TCA6424A_ADDR, - .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A - } + .flags = IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6424A } }; #endif /* SECTION_IS_RO */ -- cgit v1.2.1 From 7055590b61d8658bcfc6cdef5e2200d46deb800b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:03 -0600 Subject: board/trogdor/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I65396436bf80ab03ca5ac6577ceade75e62b8526 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729025 Reviewed-by: Jeremy Bettis --- board/trogdor/board.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/board/trogdor/board.h b/board/trogdor/board.h index 0faa3a8bf0..73be10ebd6 100644 --- a/board/trogdor/board.h +++ b/board/trogdor/board.h @@ -19,7 +19,7 @@ #define CONFIG_I2C_DEBUG /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -27,7 +27,7 @@ #define CONFIG_PWM_KBLIGHT /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE @@ -74,12 +74,7 @@ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -89,11 +84,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 968555434afcb8ff5b5ad43f5e7a70ecac55b5dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:24 -0600 Subject: common/aes-gcm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3906ab82aa17d3f63fc2e0b7152b5525ec651514 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729583 Reviewed-by: Jeremy Bettis --- common/aes-gcm.c | 921 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 920 insertions(+), 1 deletion(-) mode change 120000 => 100644 common/aes-gcm.c diff --git a/common/aes-gcm.c b/common/aes-gcm.c deleted file mode 120000 index 3176d85ff8..0000000000 --- a/common/aes-gcm.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/common/aes-gcm.c \ No newline at end of file diff --git a/common/aes-gcm.c b/common/aes-gcm.c new file mode 100644 index 0000000000..33a0e34434 --- /dev/null +++ b/common/aes-gcm.c @@ -0,0 +1,920 @@ +/* ==================================================================== + * Copyright (c) 2008 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== */ + +#include "aes-gcm.h" +#include "common.h" +#include "util.h" + +#define STRICT_ALIGNMENT 1 + +#define OPENSSL_memcpy memcpy +#define OPENSSL_memset memset +#define CRYPTO_memcmp safe_memcmp + +#ifdef CORE_CORTEX_M +#define GHASH_ASM +#define OPENSSL_ARM +#define __ARM_ARCH__ 7 +#endif + +static inline uint32_t CRYPTO_bswap4(uint32_t x) +{ + return __builtin_bswap32(x); +} + +static inline uint64_t CRYPTO_bswap8(uint64_t x) +{ + return __builtin_bswap64(x); +} + +static inline size_t load_word_le(const void *in) +{ + size_t v; + OPENSSL_memcpy(&v, in, sizeof(v)); + return v; +} + +static inline void store_word_le(void *out, size_t v) +{ + OPENSSL_memcpy(out, &v, sizeof(v)); +} + +#define PACK(s) ((size_t)(s) << (sizeof(size_t) * 8 - 16)) +#define REDUCE1BIT(V) \ + do { \ + if (sizeof(size_t) == 8) { \ + uint64_t T = UINT64_C(0xe100000000000000) & \ + (0 - ((V).lo & 1)); \ + (V).lo = ((V).hi << 63) | ((V).lo >> 1); \ + (V).hi = ((V).hi >> 1) ^ T; \ + } else { \ + uint32_t T = 0xe1000000U & \ + (0 - (uint32_t)((V).lo & 1)); \ + (V).lo = ((V).hi << 63) | ((V).lo >> 1); \ + (V).hi = ((V).hi >> 1) ^ ((uint64_t)T << 32); \ + } \ + } while (0) + +static void gcm_init_4bit(u128 Htable[16], uint64_t H[2]) +{ + u128 V; + + Htable[0].hi = 0; + Htable[0].lo = 0; + V.hi = H[0]; + V.lo = H[1]; + + Htable[8] = V; + REDUCE1BIT(V); + Htable[4] = V; + REDUCE1BIT(V); + Htable[2] = V; + REDUCE1BIT(V); + Htable[1] = V; + Htable[3].hi = V.hi ^ Htable[2].hi, Htable[3].lo = V.lo ^ Htable[2].lo; + V = Htable[4]; + Htable[5].hi = V.hi ^ Htable[1].hi, Htable[5].lo = V.lo ^ Htable[1].lo; + Htable[6].hi = V.hi ^ Htable[2].hi, Htable[6].lo = V.lo ^ Htable[2].lo; + Htable[7].hi = V.hi ^ Htable[3].hi, Htable[7].lo = V.lo ^ Htable[3].lo; + V = Htable[8]; + Htable[9].hi = V.hi ^ Htable[1].hi, Htable[9].lo = V.lo ^ Htable[1].lo; + Htable[10].hi = V.hi ^ Htable[2].hi, + Htable[10].lo = V.lo ^ Htable[2].lo; + Htable[11].hi = V.hi ^ Htable[3].hi, + Htable[11].lo = V.lo ^ Htable[3].lo; + Htable[12].hi = V.hi ^ Htable[4].hi, + Htable[12].lo = V.lo ^ Htable[4].lo; + Htable[13].hi = V.hi ^ Htable[5].hi, + Htable[13].lo = V.lo ^ Htable[5].lo; + Htable[14].hi = V.hi ^ Htable[6].hi, + Htable[14].lo = V.lo ^ Htable[6].lo; + Htable[15].hi = V.hi ^ Htable[7].hi, + Htable[15].lo = V.lo ^ Htable[7].lo; + +#if defined(GHASH_ASM) && defined(OPENSSL_ARM) + for (int j = 0; j < 16; ++j) { + V = Htable[j]; + Htable[j].hi = V.lo; + Htable[j].lo = V.hi; + } +#endif +} + +#if !defined(GHASH_ASM) || defined(OPENSSL_AARCH64) || defined(OPENSSL_PPC64LE) +static const size_t rem_4bit[16] = { PACK(0x0000), PACK(0x1C20), PACK(0x3840), + PACK(0x2460), PACK(0x7080), PACK(0x6CA0), + PACK(0x48C0), PACK(0x54E0), PACK(0xE100), + PACK(0xFD20), PACK(0xD940), PACK(0xC560), + PACK(0x9180), PACK(0x8DA0), PACK(0xA9C0), + PACK(0xB5E0) }; + +static void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]) +{ + u128 Z; + int cnt = 15; + size_t rem, nlo, nhi; + + nlo = ((const uint8_t *)Xi)[15]; + nhi = nlo >> 4; + nlo &= 0xf; + + Z.hi = Htable[nlo].hi; + Z.lo = Htable[nlo].lo; + + while (1) { + rem = (size_t)Z.lo & 0xf; + Z.lo = (Z.hi << 60) | (Z.lo >> 4); + Z.hi = (Z.hi >> 4); + if (sizeof(size_t) == 8) { + Z.hi ^= rem_4bit[rem]; + } else { + Z.hi ^= (uint64_t)rem_4bit[rem] << 32; + } + + Z.hi ^= Htable[nhi].hi; + Z.lo ^= Htable[nhi].lo; + + if (--cnt < 0) { + break; + } + + nlo = ((const uint8_t *)Xi)[cnt]; + nhi = nlo >> 4; + nlo &= 0xf; + + rem = (size_t)Z.lo & 0xf; + Z.lo = (Z.hi << 60) | (Z.lo >> 4); + Z.hi = (Z.hi >> 4); + if (sizeof(size_t) == 8) { + Z.hi ^= rem_4bit[rem]; + } else { + Z.hi ^= (uint64_t)rem_4bit[rem] << 32; + } + + Z.hi ^= Htable[nlo].hi; + Z.lo ^= Htable[nlo].lo; + } + + Xi[0] = CRYPTO_bswap8(Z.hi); + Xi[1] = CRYPTO_bswap8(Z.lo); +} + +// Streamed gcm_mult_4bit, see CRYPTO_gcm128_[en|de]crypt for +// details... Compiler-generated code doesn't seem to give any +// performance improvement, at least not on x86[_64]. It's here +// mostly as reference and a placeholder for possible future +// non-trivial optimization[s]... +static void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) +{ + u128 Z; + int cnt; + size_t rem, nlo, nhi; + + do { + cnt = 15; + nlo = ((const uint8_t *)Xi)[15]; + nlo ^= inp[15]; + nhi = nlo >> 4; + nlo &= 0xf; + + Z.hi = Htable[nlo].hi; + Z.lo = Htable[nlo].lo; + + while (1) { + rem = (size_t)Z.lo & 0xf; + Z.lo = (Z.hi << 60) | (Z.lo >> 4); + Z.hi = (Z.hi >> 4); + if (sizeof(size_t) == 8) { + Z.hi ^= rem_4bit[rem]; + } else { + Z.hi ^= (uint64_t)rem_4bit[rem] << 32; + } + + Z.hi ^= Htable[nhi].hi; + Z.lo ^= Htable[nhi].lo; + + if (--cnt < 0) { + break; + } + + nlo = ((const uint8_t *)Xi)[cnt]; + nlo ^= inp[cnt]; + nhi = nlo >> 4; + nlo &= 0xf; + + rem = (size_t)Z.lo & 0xf; + Z.lo = (Z.hi << 60) | (Z.lo >> 4); + Z.hi = (Z.hi >> 4); + if (sizeof(size_t) == 8) { + Z.hi ^= rem_4bit[rem]; + } else { + Z.hi ^= (uint64_t)rem_4bit[rem] << 32; + } + + Z.hi ^= Htable[nlo].hi; + Z.lo ^= Htable[nlo].lo; + } + + Xi[0] = CRYPTO_bswap8(Z.hi); + Xi[1] = CRYPTO_bswap8(Z.lo); + } while (inp += 16, len -= 16); +} +#else // GHASH_ASM +void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, + size_t len); +#endif + +#define GCM_MUL(ctx, Xi) gcm_gmult_4bit((ctx)->Xi.u, (ctx)->Htable) +#if defined(GHASH_ASM) +#define GHASH(ctx, in, len) gcm_ghash_4bit((ctx)->Xi.u, (ctx)->Htable, in, len) +// GHASH_CHUNK is "stride parameter" missioned to mitigate cache +// trashing effect. In other words idea is to hash data while it's +// still in L1 cache after encryption pass... +#define GHASH_CHUNK (3 * 1024) +#endif + +#if defined(GHASH_ASM) + +#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64) +#define GCM_FUNCREF_4BIT +void gcm_init_clmul(u128 Htable[16], const uint64_t Xi[2]); +void gcm_gmult_clmul(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_clmul(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, + size_t len); + +#if defined(OPENSSL_X86_64) +#define GHASH_ASM_X86_64 +void gcm_init_avx(u128 Htable[16], const uint64_t Xi[2]); +void gcm_gmult_avx(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_avx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *in, + size_t len); +#define AESNI_GCM +size_t aesni_gcm_encrypt(const uint8_t *in, uint8_t *out, size_t len, + const void *key, uint8_t ivec[16], uint64_t *Xi); +size_t aesni_gcm_decrypt(const uint8_t *in, uint8_t *out, size_t len, + const void *key, uint8_t ivec[16], uint64_t *Xi); +#endif + +#if defined(OPENSSL_X86) +#define GHASH_ASM_X86 +void gcm_gmult_4bit_mmx(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_4bit_mmx(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len); +#endif + +#elif defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64) +#if __ARM_ARCH__ >= 7 +#define GHASH_ASM_ARM +#define GCM_FUNCREF_4BIT + +#if defined(OPENSSL_ARM_PMULL) +static int pmull_capable(void) +{ + return CRYPTO_is_ARMv8_PMULL_capable(); +} + +void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]); +void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, + size_t len); +#else +static int pmull_capable(void) +{ + return 0; +} +static void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]) +{ +} +static void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]) +{ +} +static void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) +{ +} +#endif + +#if defined(OPENSSL_ARM_NEON) +// 32-bit ARM also has support for doing GCM with NEON instructions. +static int neon_capable(void) +{ + return CRYPTO_is_NEON_capable(); +} + +void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]); +void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, + size_t len); +#else +// AArch64 only has the ARMv8 versions of functions. +static int neon_capable(void) +{ + return 0; +} +static void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]) +{ +} +static void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]) +{ +} +static void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) +{ +} +#endif + +#endif +#elif defined(OPENSSL_PPC64LE) +#define GHASH_ASM_PPC64LE +#define GCM_FUNCREF_4BIT +void gcm_init_p8(u128 Htable[16], const uint64_t Xi[2]); +void gcm_gmult_p8(uint64_t Xi[2], const u128 Htable[16]); +void gcm_ghash_p8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, + size_t len); +#endif +#endif + +#ifdef GCM_FUNCREF_4BIT +#undef GCM_MUL +#define GCM_MUL(ctx, Xi) (*gcm_gmult_p)((ctx)->Xi.u, (ctx)->Htable) +#ifdef GHASH +#undef GHASH +#define GHASH(ctx, in, len) (*gcm_ghash_p)((ctx)->Xi.u, (ctx)->Htable, in, len) +#endif +#endif + +#ifdef GHASH +// kSizeTWithoutLower4Bits is a mask that can be used to zero the lower four +// bits of a |size_t|. +static const size_t kSizeTWithoutLower4Bits = (size_t)-16; +#endif + +static void CRYPTO_ghash_init(gmult_func *out_mult, ghash_func *out_hash, + u128 *out_key, u128 out_table[16], + const uint8_t *gcm_key) +{ + union { + uint64_t u[2]; + uint8_t c[16]; + } H; + + OPENSSL_memcpy(H.c, gcm_key, 16); + + // H is stored in host byte order + H.u[0] = CRYPTO_bswap8(H.u[0]); + H.u[1] = CRYPTO_bswap8(H.u[1]); + + OPENSSL_memcpy(out_key, H.c, 16); + +#if defined(GHASH_ASM_X86_64) + if (crypto_gcm_clmul_enabled()) { + if (((OPENSSL_ia32cap_get()[1] >> 22) & 0x41) == + 0x41) { // AVX+MOVBE + gcm_init_avx(out_table, H.u); + *out_mult = gcm_gmult_avx; + *out_hash = gcm_ghash_avx; + *out_is_avx = 1; + return; + } + gcm_init_clmul(out_table, H.u); + *out_mult = gcm_gmult_clmul; + *out_hash = gcm_ghash_clmul; + return; + } +#elif defined(GHASH_ASM_X86) + if (crypto_gcm_clmul_enabled()) { + gcm_init_clmul(out_table, H.u); + *out_mult = gcm_gmult_clmul; + *out_hash = gcm_ghash_clmul; + return; + } +#elif defined(GHASH_ASM_ARM) + if (pmull_capable()) { + gcm_init_v8(out_table, H.u); + *out_mult = gcm_gmult_v8; + *out_hash = gcm_ghash_v8; + return; + } + + if (neon_capable()) { + gcm_init_neon(out_table, H.u); + *out_mult = gcm_gmult_neon; + *out_hash = gcm_ghash_neon; + return; + } +#elif defined(GHASH_ASM_PPC64LE) + if (CRYPTO_is_PPC64LE_vcrypto_capable()) { + gcm_init_p8(out_table, H.u); + *out_mult = gcm_gmult_p8; + *out_hash = gcm_ghash_p8; + return; + } +#endif + + gcm_init_4bit(out_table, H.u); +#if defined(GHASH_ASM_X86) + *out_mult = gcm_gmult_4bit_mmx; + *out_hash = gcm_ghash_4bit_mmx; +#else + *out_mult = gcm_gmult_4bit; + *out_hash = gcm_ghash_4bit; +#endif +} + +void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *aes_key, + block128_f block, int block_is_hwaes) +{ + OPENSSL_memset(ctx, 0, sizeof(*ctx)); + ctx->block = block; + + uint8_t gcm_key[16]; + OPENSSL_memset(gcm_key, 0, sizeof(gcm_key)); + (*block)(gcm_key, gcm_key, aes_key); + + CRYPTO_ghash_init(&ctx->gmult, &ctx->ghash, &ctx->H, ctx->Htable, + gcm_key); +} + +void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key, + const uint8_t *iv, size_t len) +{ + unsigned int ctr; +#ifdef GCM_FUNCREF_4BIT + void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; +#endif + + ctx->Yi.u[0] = 0; + ctx->Yi.u[1] = 0; + ctx->Xi.u[0] = 0; + ctx->Xi.u[1] = 0; + ctx->len.u[0] = 0; // AAD length + ctx->len.u[1] = 0; // message length + ctx->ares = 0; + ctx->mres = 0; + + if (len == 12) { + OPENSSL_memcpy(ctx->Yi.c, iv, 12); + ctx->Yi.c[15] = 1; + ctr = 1; + } else { + uint64_t len0 = len; + + while (len >= 16) { + for (size_t i = 0; i < 16; ++i) { + ctx->Yi.c[i] ^= iv[i]; + } + GCM_MUL(ctx, Yi); + iv += 16; + len -= 16; + } + if (len) { + for (size_t i = 0; i < len; ++i) { + ctx->Yi.c[i] ^= iv[i]; + } + GCM_MUL(ctx, Yi); + } + len0 <<= 3; + ctx->Yi.u[1] ^= CRYPTO_bswap8(len0); + + GCM_MUL(ctx, Yi); + ctr = CRYPTO_bswap4(ctx->Yi.d[3]); + } + + (*ctx->block)(ctx->Yi.c, ctx->EK0.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); +} + +int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len) +{ + unsigned int n; + uint64_t alen = ctx->len.u[0]; +#ifdef GCM_FUNCREF_4BIT + void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; +#ifdef GHASH + void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) = ctx->ghash; +#endif +#endif + + if (ctx->len.u[1]) { + return 0; + } + + alen += len; + if (alen > (UINT64_C(1) << 61) || (sizeof(len) == 8 && alen < len)) { + return 0; + } + ctx->len.u[0] = alen; + + n = ctx->ares; + if (n) { + while (n && len) { + ctx->Xi.c[n] ^= *(aad++); + --len; + n = (n + 1) % 16; + } + if (n == 0) { + GCM_MUL(ctx, Xi); + } else { + ctx->ares = n; + return 1; + } + } + + // Process a whole number of blocks. +#ifdef GHASH + size_t len_blocks = len & kSizeTWithoutLower4Bits; + if (len_blocks != 0) { + GHASH(ctx, aad, len_blocks); + aad += len_blocks; + len -= len_blocks; + } +#else + while (len >= 16) { + for (size_t i = 0; i < 16; ++i) { + ctx->Xi.c[i] ^= aad[i]; + } + GCM_MUL(ctx, Xi); + aad += 16; + len -= 16; + } +#endif + + // Process the remainder. + if (len != 0) { + n = (unsigned int)len; + for (size_t i = 0; i < len; ++i) { + ctx->Xi.c[i] ^= aad[i]; + } + } + + ctx->ares = n; + return 1; +} + +int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key, + const uint8_t *in, uint8_t *out, size_t len) +{ + unsigned int n, ctr; + uint64_t mlen = ctx->len.u[1]; + block128_f block = ctx->block; +#ifdef GCM_FUNCREF_4BIT + void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; +#ifdef GHASH + void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) = ctx->ghash; +#endif +#endif + + mlen += len; + if (mlen > ((UINT64_C(1) << 36) - 32) || + (sizeof(len) == 8 && mlen < len)) { + return 0; + } + ctx->len.u[1] = mlen; + + if (ctx->ares) { + // First call to encrypt finalizes GHASH(AAD) + GCM_MUL(ctx, Xi); + ctx->ares = 0; + } + + ctr = CRYPTO_bswap4(ctx->Yi.d[3]); + + n = ctx->mres; + if (n) { + while (n && len) { + ctx->Xi.c[n] ^= *(out++) = *(in++) ^ ctx->EKi.c[n]; + --len; + n = (n + 1) % 16; + } + if (n == 0) { + GCM_MUL(ctx, Xi); + } else { + ctx->mres = n; + return 1; + } + } + if (STRICT_ALIGNMENT && + ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) { + for (size_t i = 0; i < len; ++i) { + if (n == 0) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + } + ctx->Xi.c[n] ^= out[i] = in[i] ^ ctx->EKi.c[n]; + n = (n + 1) % 16; + if (n == 0) { + GCM_MUL(ctx, Xi); + } + } + + ctx->mres = n; + return 1; + } +#if defined(GHASH) && defined(GHASH_CHUNK) + while (len >= GHASH_CHUNK) { + size_t j = GHASH_CHUNK; + + while (j) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + store_word_le( + out + i, + load_word_le(in + i) ^ + ctx->EKi.t[i / sizeof(size_t)]); + } + out += 16; + in += 16; + j -= 16; + } + GHASH(ctx, out - GHASH_CHUNK, GHASH_CHUNK); + len -= GHASH_CHUNK; + } + size_t len_blocks = len & kSizeTWithoutLower4Bits; + if (len_blocks != 0) { + while (len >= 16) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + store_word_le( + out + i, + load_word_le(in + i) ^ + ctx->EKi.t[i / sizeof(size_t)]); + } + out += 16; + in += 16; + len -= 16; + } + GHASH(ctx, out - len_blocks, len_blocks); + } +#else + while (len >= 16) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + size_t tmp = load_word_le(in + i) ^ + ctx->EKi.t[i / sizeof(size_t)]; + store_word_le(out + i, tmp); + ctx->Xi.t[i / sizeof(size_t)] ^= tmp; + } + GCM_MUL(ctx, Xi); + out += 16; + in += 16; + len -= 16; + } +#endif + if (len) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + while (len--) { + ctx->Xi.c[n] ^= out[n] = in[n] ^ ctx->EKi.c[n]; + ++n; + } + } + + ctx->mres = n; + return 1; +} + +int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key, + const unsigned char *in, unsigned char *out, + size_t len) +{ + unsigned int n, ctr; + uint64_t mlen = ctx->len.u[1]; + block128_f block = ctx->block; +#ifdef GCM_FUNCREF_4BIT + void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; +#ifdef GHASH + void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len) = ctx->ghash; +#endif +#endif + + mlen += len; + if (mlen > ((UINT64_C(1) << 36) - 32) || + (sizeof(len) == 8 && mlen < len)) { + return 0; + } + ctx->len.u[1] = mlen; + + if (ctx->ares) { + // First call to decrypt finalizes GHASH(AAD) + GCM_MUL(ctx, Xi); + ctx->ares = 0; + } + + ctr = CRYPTO_bswap4(ctx->Yi.d[3]); + + n = ctx->mres; + if (n) { + while (n && len) { + uint8_t c = *(in++); + *(out++) = c ^ ctx->EKi.c[n]; + ctx->Xi.c[n] ^= c; + --len; + n = (n + 1) % 16; + } + if (n == 0) { + GCM_MUL(ctx, Xi); + } else { + ctx->mres = n; + return 1; + } + } + if (STRICT_ALIGNMENT && + ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) { + for (size_t i = 0; i < len; ++i) { + uint8_t c; + if (n == 0) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + } + c = in[i]; + out[i] = c ^ ctx->EKi.c[n]; + ctx->Xi.c[n] ^= c; + n = (n + 1) % 16; + if (n == 0) { + GCM_MUL(ctx, Xi); + } + } + + ctx->mres = n; + return 1; + } +#if defined(GHASH) && defined(GHASH_CHUNK) + while (len >= GHASH_CHUNK) { + size_t j = GHASH_CHUNK; + + GHASH(ctx, in, GHASH_CHUNK); + while (j) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + store_word_le( + out + i, + load_word_le(in + i) ^ + ctx->EKi.t[i / sizeof(size_t)]); + } + out += 16; + in += 16; + j -= 16; + } + len -= GHASH_CHUNK; + } + size_t len_blocks = len & kSizeTWithoutLower4Bits; + if (len_blocks != 0) { + GHASH(ctx, in, len_blocks); + while (len >= 16) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + store_word_le( + out + i, + load_word_le(in + i) ^ + ctx->EKi.t[i / sizeof(size_t)]); + } + out += 16; + in += 16; + len -= 16; + } + } +#else + while (len >= 16) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + for (size_t i = 0; i < 16; i += sizeof(size_t)) { + size_t c = load_word_le(in + i); + store_word_le(out + i, + c ^ ctx->EKi.t[i / sizeof(size_t)]); + ctx->Xi.t[i / sizeof(size_t)] ^= c; + } + GCM_MUL(ctx, Xi); + out += 16; + in += 16; + len -= 16; + } +#endif + if (len) { + (*block)(ctx->Yi.c, ctx->EKi.c, key); + ++ctr; + ctx->Yi.d[3] = CRYPTO_bswap4(ctr); + while (len--) { + uint8_t c = in[n]; + ctx->Xi.c[n] ^= c; + out[n] = c ^ ctx->EKi.c[n]; + ++n; + } + } + + ctx->mres = n; + return 1; +} + +int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len) +{ + uint64_t alen = ctx->len.u[0] << 3; + uint64_t clen = ctx->len.u[1] << 3; +#ifdef GCM_FUNCREF_4BIT + void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; +#endif + + if (ctx->mres || ctx->ares) { + GCM_MUL(ctx, Xi); + } + + alen = CRYPTO_bswap8(alen); + clen = CRYPTO_bswap8(clen); + + ctx->Xi.u[0] ^= alen; + ctx->Xi.u[1] ^= clen; + GCM_MUL(ctx, Xi); + + ctx->Xi.u[0] ^= ctx->EK0.u[0]; + ctx->Xi.u[1] ^= ctx->EK0.u[1]; + + if (tag && len <= sizeof(ctx->Xi)) { + return CRYPTO_memcmp(ctx->Xi.c, tag, len) == 0; + } else { + return 0; + } +} + +void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, unsigned char *tag, size_t len) +{ + CRYPTO_gcm128_finish(ctx, NULL, 0); + OPENSSL_memcpy(tag, ctx->Xi.c, + len <= sizeof(ctx->Xi.c) ? len : sizeof(ctx->Xi.c)); +} + +#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64) +int crypto_gcm_clmul_enabled(void) +{ +#ifdef GHASH_ASM + const uint32_t *ia32cap = OPENSSL_ia32cap_get(); + return (ia32cap[0] & (1 << 24)) && // check FXSR bit + (ia32cap[1] & (1 << 1)); // check PCLMULQDQ bit +#else + return 0; +#endif +} +#endif -- cgit v1.2.1 From 188ed72baac3aab55f153c57835f4bfeadab9518 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:52 -0600 Subject: core/minute-ia/cpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic3097e985f1c00570fd2c4c36df78550633b4e97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729848 Reviewed-by: Jeremy Bettis --- core/minute-ia/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/core/minute-ia/cpu.c b/core/minute-ia/cpu.c index cef39fe1ce..d41d7f60c8 100644 --- a/core/minute-ia/cpu.c +++ b/core/minute-ia/cpu.c @@ -7,7 +7,6 @@ #include - void cpu_init(void) { /* Nothing to do now */ -- cgit v1.2.1 From dca9d74321af5edcf8a8830eedb2023fa92c3040 Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Tue, 28 Jun 2022 03:47:38 +0000 Subject: Revert "trng: Rename rand to trng_rand" This reverts commit a6b0b3554f59cc9b0c4aae9bff7dff075f2089a9. Reason for revert: This CL breaks ec-utils-test package and affects CQ Original change's description: > trng: Rename rand to trng_rand > > The declaration for rand conflicts with the standard library declaration > so rename it from "rand" to "trng_rand". This has the benefit of making > it obvious when we're using the true random number generator. > > For consistency, this also renames init_trng/exit_trng to > trng_init/trng_exit. > > BRANCH=none > BUG=b:234181908 > TEST=./util/compare_build.sh -b all -j 120 > => MATCH > > Signed-off-by: Tom Hughes > Change-Id: Ic3305a91263c45786c051eaa5b3689e7464aa0ab > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712032 > Reviewed-by: Bobby Casey > Reviewed-by: Jack Rosenthal Bug: b:234181908,b:237344361 Change-Id: Iceae55ad9ff0e6aa98aebd474f92a98e12c287e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726597 Tested-by: Manoj Gupta Reviewed-by: Pin-yen Lin Reviewed-by: Jack Rosenthal Owners-Override: Pin-yen Lin Commit-Queue: Pin-yen Lin Tested-by: Pin-yen Lin Commit-Queue: Manoj Gupta --- chip/host/trng.c | 6 +++--- chip/stm32/trng.c | 22 +++++++++++----------- common/fpsensor/fpsensor.c | 26 +++++++++++++------------- common/rollback.c | 6 +++--- include/trng.h | 12 +++++++----- third_party/boringssl/common/curve25519.c | 2 +- 6 files changed, 38 insertions(+), 36 deletions(-) diff --git a/chip/host/trng.c b/chip/host/trng.c index cb69268e34..8407aa6ea1 100644 --- a/chip/host/trng.c +++ b/chip/host/trng.c @@ -21,17 +21,17 @@ static unsigned int seed; -test_mockable void trng_init(void) +test_mockable void init_trng(void) { seed = 0; srand(seed); } -test_mockable void trng_exit(void) +test_mockable void exit_trng(void) { } -test_mockable void trng_rand_bytes(void *buffer, size_t len) +test_mockable void rand_bytes(void *buffer, size_t len) { uint8_t *b, *end; diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 447ccbccad..48d5335c53 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -15,7 +15,7 @@ #include "trng.h" #include "util.h" -uint32_t trng_rand(void) +uint32_t rand(void) { int tries = 300; /* Wait for a valid random number */ @@ -28,10 +28,10 @@ uint32_t trng_rand(void) return STM32_RNG_DR; } -test_mockable void trng_rand_bytes(void *buffer, size_t len) +test_mockable void rand_bytes(void *buffer, size_t len) { while (len) { - uint32_t number = trng_rand(); + uint32_t number = rand(); size_t cnt = 4; /* deal with the lack of alignment guarantee in the API */ uintptr_t align = (uintptr_t)buffer & 3; @@ -47,7 +47,7 @@ test_mockable void trng_rand_bytes(void *buffer, size_t len) } } -test_mockable void trng_init(void) +test_mockable void init_trng(void) { #ifdef CHIP_FAMILY_STM32L4 /* Enable the 48Mhz internal RC oscillator */ @@ -84,7 +84,7 @@ test_mockable void trng_init(void) STM32_RNG_CR |= STM32_RNG_CR_RNGEN; } -test_mockable void trng_exit(void) +test_mockable void exit_trng(void) { STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; @@ -107,9 +107,9 @@ static int command_rand(int argc, char **argv) { uint8_t data[32]; - trng_init(); - trng_rand_bytes(data, sizeof(data)); - trng_exit(); + init_trng(); + rand_bytes(data, sizeof(data)); + exit_trng(); ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); @@ -130,9 +130,9 @@ static enum ec_status host_command_rand(struct host_cmd_handler_args *args) if (num_rand_bytes > args->response_max) return EC_RES_OVERFLOW; - trng_init(); - trng_rand_bytes(r->rand, num_rand_bytes); - trng_exit(); + init_trng(); + rand_bytes(r->rand, num_rand_bytes); + exit_trng(); args->response_size = num_rand_bytes; diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c index a491e1af84..12904c0b39 100644 --- a/common/fpsensor/fpsensor.c +++ b/common/fpsensor/fpsensor.c @@ -472,11 +472,11 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) */ enc_info = (void *)fp_enc_buffer; enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION; - trng_init(); - trng_rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); - trng_rand_bytes(enc_info->encryption_salt, - FP_CONTEXT_ENCRYPTION_SALT_BYTES); - trng_exit(); + init_trng(); + rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); + rand_bytes(enc_info->encryption_salt, + FP_CONTEXT_ENCRYPTION_SALT_BYTES); + exit_trng(); if (fgr == template_newly_enrolled) { /* @@ -485,10 +485,10 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) * value. */ template_newly_enrolled = FP_NO_SUCH_TEMPLATE; - trng_init(); - trng_rand_bytes(fp_positive_match_salt[fgr], - FP_POSITIVE_MATCH_SALT_BYTES); - trng_exit(); + init_trng(); + rand_bytes(fp_positive_match_salt[fgr], + FP_POSITIVE_MATCH_SALT_BYTES); + exit_trng(); } ret = derive_encryption_key(key, enc_info->encryption_salt); @@ -647,10 +647,10 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args) sizeof(fp_template[0])); if (template_needs_validation_value(enc_info)) { CPRINTS("fgr%d: Generating positive match salt.", idx); - trng_init(); - trng_rand_bytes(positive_match_salt, - FP_POSITIVE_MATCH_SALT_BYTES); - trng_exit(); + init_trng(); + rand_bytes(positive_match_salt, + FP_POSITIVE_MATCH_SALT_BYTES); + exit_trng(); } if (bytes_are_trivial(positive_match_salt, sizeof(fp_positive_match_salt[0]))) { diff --git a/common/rollback.c b/common/rollback.c index 3f9e176782..984058c49a 100644 --- a/common/rollback.c +++ b/common/rollback.c @@ -400,9 +400,9 @@ static void add_entropy_deferred(void) if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC) repeat = ROLLBACK_REGIONS; - trng_init(); + init_trng(); do { - trng_rand_bytes(rand, sizeof(rand)); + rand_bytes(rand, sizeof(rand)); if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) { add_entropy_rv = EC_RES_ERROR; goto out; @@ -411,7 +411,7 @@ static void add_entropy_deferred(void) add_entropy_rv = EC_RES_SUCCESS; out: - trng_exit(); + exit_trng(); } DECLARE_DEFERRED(add_entropy_deferred); diff --git a/include/trng.h b/include/trng.h index 969366ae8e..cea4555b41 100644 --- a/include/trng.h +++ b/include/trng.h @@ -14,30 +14,32 @@ * * Not supported by all platforms. **/ -void trng_init(void); +void init_trng(void); /** * Shutdown the true random number generator. * - * The opposite operation of trng_init(), disable the hardware resources + * The opposite operation of init_trng(), disable the hardware resources * used by the TRNG to save power. * * Not supported by all platforms. **/ -void trng_exit(void); +void exit_trng(void); /** * Retrieve a 32 bit random value. * * Not supported on all platforms. **/ -uint32_t trng_rand(void); +#ifndef HIDE_EC_STDLIB +uint32_t rand(void); +#endif /** * Output len random bytes into buffer. * * Not supported on all platforms. **/ -void trng_rand_bytes(void *buffer, size_t len); +void rand_bytes(void *buffer, size_t len); #endif /* __EC_INCLUDE_TRNG_H */ diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c index b74d3c7d97..2a7fad6509 100644 --- a/third_party/boringssl/common/curve25519.c +++ b/third_party/boringssl/common/curve25519.c @@ -27,7 +27,7 @@ #ifdef CONFIG_RNG void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) { - trng_rand_bytes(out_private_key, 32); + rand_bytes(out_private_key, 32); /* All X25519 implementations should decode scalars correctly (see * https://tools.ietf.org/html/rfc7748#section-5). However, if an -- cgit v1.2.1 From 6dd60d190cd8b1bd3901e35f9168a297834af578 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:59 -0600 Subject: driver/accel_kx022.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d90e7f06c4e849740ffaafbdb2cda321ca0b0ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729746 Reviewed-by: Jeremy Bettis --- driver/accel_kx022.h | 236 +++++++++++++++++++++++++-------------------------- 1 file changed, 117 insertions(+), 119 deletions(-) diff --git a/driver/accel_kx022.h b/driver/accel_kx022.h index a806568c59..b1f1cdc658 100644 --- a/driver/accel_kx022.h +++ b/driver/accel_kx022.h @@ -12,130 +12,128 @@ * 7-bit address is 001111Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define KX022_ADDR0_FLAGS 0x1e -#define KX022_ADDR1_FLAGS 0x1f -#define KX022_WHO_AM_I_VAL 0x14 +#define KX022_ADDR0_FLAGS 0x1e +#define KX022_ADDR1_FLAGS 0x1f +#define KX022_WHO_AM_I_VAL 0x14 /* Chip-specific registers */ -#define KX022_XHP_L 0x00 -#define KX022_XHP_H 0x01 -#define KX022_YHP_L 0x02 -#define KX022_YHP_H 0x03 -#define KX022_ZHP_L 0x04 -#define KX022_ZHP_H 0x05 -#define KX022_XOUT_L 0x06 -#define KX022_XOUT_H 0x07 -#define KX022_YOUT_L 0x08 -#define KX022_YOUT_H 0x09 -#define KX022_ZOUT_L 0x0a -#define KX022_ZOUT_H 0x0b -#define KX022_COTR 0x0c -#define KX022_COTR_VAL_COTC 0xAA -#define KX022_COTR_VAL_DEFAULT 0x55 -#define KX022_WHOAMI 0x0f -#define KX022_TSCP 0x10 -#define KX022_TSPP 0x11 -#define KX022_INS1 0x12 -#define KX022_INS2 0x13 -#define KX022_INS3 0x14 -#define KX022_STATUS_REG 0x15 -#define KX022_INT_REL 0x17 -#define KX022_CNTL1 0x18 -#define KX022_CNTL2 0x19 -#define KX022_CNTL3 0x1a -#define KX022_ODCNTL 0x1b -#define KX022_INC1 0x1c -#define KX022_INC2 0x1d -#define KX022_INC3 0x1e -#define KX022_INC4 0x1f -#define KX022_INC5 0x20 -#define KX022_INC6 0x21 -#define KX022_TILT_TIMER 0x22 -#define KX022_WUFC 0x23 -#define KX022_TDTRC 0x24 -#define KX022_TDTC 0x25 -#define KX022_TTH 0x26 -#define KX022_TTL 0x27 -#define KX022_FTD 0x28 -#define KX022_STD 0x29 -#define KX022_TLT 0x2a -#define KX022_TWS 0x2b -#define KX022_ATH 0x30 -#define KX022_TILT_ANGLE_LL 0x32 -#define KX022_TILT_ANGLE_HL 0x33 -#define KX022_HYST_SET 0x34 -#define KX022_LP_CNTL 0x35 -#define KX022_BUF_CNTL1 0x3a -#define KX022_BUF_CNTL2 0x3b -#define KX022_BUF_STATUS_1 0x3c -#define KX022_BUF_STATUS_2 0x3d -#define KX022_BUF_CLEAR 0x3e -#define KX022_BUF_READ 0x3f -#define KX022_SELF_TEST 0x60 -#define KX022_INTERNAL 0x7f - - -#define KX022_CNTL1_PC1 BIT(7) -#define KX022_CNTL1_WUFE BIT(1) -#define KX022_CNTL1_TPE BIT(0) +#define KX022_XHP_L 0x00 +#define KX022_XHP_H 0x01 +#define KX022_YHP_L 0x02 +#define KX022_YHP_H 0x03 +#define KX022_ZHP_L 0x04 +#define KX022_ZHP_H 0x05 +#define KX022_XOUT_L 0x06 +#define KX022_XOUT_H 0x07 +#define KX022_YOUT_L 0x08 +#define KX022_YOUT_H 0x09 +#define KX022_ZOUT_L 0x0a +#define KX022_ZOUT_H 0x0b +#define KX022_COTR 0x0c +#define KX022_COTR_VAL_COTC 0xAA +#define KX022_COTR_VAL_DEFAULT 0x55 +#define KX022_WHOAMI 0x0f +#define KX022_TSCP 0x10 +#define KX022_TSPP 0x11 +#define KX022_INS1 0x12 +#define KX022_INS2 0x13 +#define KX022_INS3 0x14 +#define KX022_STATUS_REG 0x15 +#define KX022_INT_REL 0x17 +#define KX022_CNTL1 0x18 +#define KX022_CNTL2 0x19 +#define KX022_CNTL3 0x1a +#define KX022_ODCNTL 0x1b +#define KX022_INC1 0x1c +#define KX022_INC2 0x1d +#define KX022_INC3 0x1e +#define KX022_INC4 0x1f +#define KX022_INC5 0x20 +#define KX022_INC6 0x21 +#define KX022_TILT_TIMER 0x22 +#define KX022_WUFC 0x23 +#define KX022_TDTRC 0x24 +#define KX022_TDTC 0x25 +#define KX022_TTH 0x26 +#define KX022_TTL 0x27 +#define KX022_FTD 0x28 +#define KX022_STD 0x29 +#define KX022_TLT 0x2a +#define KX022_TWS 0x2b +#define KX022_ATH 0x30 +#define KX022_TILT_ANGLE_LL 0x32 +#define KX022_TILT_ANGLE_HL 0x33 +#define KX022_HYST_SET 0x34 +#define KX022_LP_CNTL 0x35 +#define KX022_BUF_CNTL1 0x3a +#define KX022_BUF_CNTL2 0x3b +#define KX022_BUF_STATUS_1 0x3c +#define KX022_BUF_STATUS_2 0x3d +#define KX022_BUF_CLEAR 0x3e +#define KX022_BUF_READ 0x3f +#define KX022_SELF_TEST 0x60 +#define KX022_INTERNAL 0x7f + +#define KX022_CNTL1_PC1 BIT(7) +#define KX022_CNTL1_WUFE BIT(1) +#define KX022_CNTL1_TPE BIT(0) /* TSCP orientations */ -#define KX022_ORIENT_PORTRAIT BIT(2) -#define KX022_ORIENT_INVERT_PORTRAIT BIT(3) -#define KX022_ORIENT_LANDSCAPE BIT(4) -#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5) -#define KX022_ORIENT_MASK (KX022_ORIENT_PORTRAIT | \ - KX022_ORIENT_INVERT_PORTRAIT | \ - KX022_ORIENT_LANDSCAPE | \ - KX022_ORIENT_INVERT_LANDSCAPE) - -#define KX022_CNTL2_SRST BIT(7) - -#define KX022_CNTL3_OWUF_FIELD 7 - -#define KX022_INC1_IEA BIT(4) -#define KX022_INC1_IEN BIT(5) - -#define KX022_GSEL_2G (0 << 3) -#define KX022_GSEL_4G BIT(3) -#define KX022_GSEL_8G (2 << 3) -#define KX022_GSEL_FIELD (3 << 3) - -#define KX022_RES_8BIT (0 << 6) -#define KX022_RES_16BIT BIT(6) - -#define KX022_OSA_0_781HZ 8 -#define KX022_OSA_1_563HZ 9 -#define KX022_OSA_3_125HZ 0xa -#define KX022_OSA_6_250HZ 0xb -#define KX022_OSA_12_50HZ 0 -#define KX022_OSA_25_00HZ 1 -#define KX022_OSA_50_00HZ 2 -#define KX022_OSA_100_0HZ 3 -#define KX022_OSA_200_0HZ 4 -#define KX022_OSA_400_0HZ 5 -#define KX022_OSA_800_0HZ 6 -#define KX022_OSA_1600HZ 7 -#define KX022_OSA_FIELD 0xf - -#define KX022_OWUF_0_781HZ 0 -#define KX022_OWUF_1_563HZ 1 -#define KX022_OWUF_3_125HZ 2 -#define KX022_OWUF_6_250HZ 3 -#define KX022_OWUF_12_50HZ 4 -#define KX022_OWUF_25_00HZ 5 -#define KX022_OWUF_50_00HZ 6 -#define KX022_OWUF_100_0HZ 7 - -#define KX022_INC2_ZPWUE BIT(0) -#define KX022_INC2_ZNWUE BIT(1) -#define KX022_INC2_YPWUE BIT(2) -#define KX022_INC2_YNWUE BIT(3) -#define KX022_INC2_XPWUE BIT(4) -#define KX022_INC2_XNWUE BIT(5) +#define KX022_ORIENT_PORTRAIT BIT(2) +#define KX022_ORIENT_INVERT_PORTRAIT BIT(3) +#define KX022_ORIENT_LANDSCAPE BIT(4) +#define KX022_ORIENT_INVERT_LANDSCAPE BIT(5) +#define KX022_ORIENT_MASK \ + (KX022_ORIENT_PORTRAIT | KX022_ORIENT_INVERT_PORTRAIT | \ + KX022_ORIENT_LANDSCAPE | KX022_ORIENT_INVERT_LANDSCAPE) + +#define KX022_CNTL2_SRST BIT(7) + +#define KX022_CNTL3_OWUF_FIELD 7 + +#define KX022_INC1_IEA BIT(4) +#define KX022_INC1_IEN BIT(5) + +#define KX022_GSEL_2G (0 << 3) +#define KX022_GSEL_4G BIT(3) +#define KX022_GSEL_8G (2 << 3) +#define KX022_GSEL_FIELD (3 << 3) + +#define KX022_RES_8BIT (0 << 6) +#define KX022_RES_16BIT BIT(6) + +#define KX022_OSA_0_781HZ 8 +#define KX022_OSA_1_563HZ 9 +#define KX022_OSA_3_125HZ 0xa +#define KX022_OSA_6_250HZ 0xb +#define KX022_OSA_12_50HZ 0 +#define KX022_OSA_25_00HZ 1 +#define KX022_OSA_50_00HZ 2 +#define KX022_OSA_100_0HZ 3 +#define KX022_OSA_200_0HZ 4 +#define KX022_OSA_400_0HZ 5 +#define KX022_OSA_800_0HZ 6 +#define KX022_OSA_1600HZ 7 +#define KX022_OSA_FIELD 0xf + +#define KX022_OWUF_0_781HZ 0 +#define KX022_OWUF_1_563HZ 1 +#define KX022_OWUF_3_125HZ 2 +#define KX022_OWUF_6_250HZ 3 +#define KX022_OWUF_12_50HZ 4 +#define KX022_OWUF_25_00HZ 5 +#define KX022_OWUF_50_00HZ 6 +#define KX022_OWUF_100_0HZ 7 + +#define KX022_INC2_ZPWUE BIT(0) +#define KX022_INC2_ZNWUE BIT(1) +#define KX022_INC2_YPWUE BIT(2) +#define KX022_INC2_YNWUE BIT(3) +#define KX022_INC2_XPWUE BIT(4) +#define KX022_INC2_XNWUE BIT(5) /* Min and Max sampling frequency in mHz */ -#define KX022_ACCEL_MIN_FREQ 12500 -#define KX022_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) +#define KX022_ACCEL_MIN_FREQ 12500 +#define KX022_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) #endif /* __CROS_EC_ACCEL_KX022_H */ -- cgit v1.2.1 From cbe1777e3ae53dfb52429aac898f60ecc9f9a4e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:24 -0600 Subject: zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0a699e134b2f730ea22bfc99960d593e7f24a3ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730777 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c index 0839f453b5..6bac6d1302 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c @@ -12,8 +12,8 @@ #include "keyboard_raw.h" #include "power/meteorlake.h" -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) /******************************************************************************/ /* KSO mapping for discrete keyboard */ @@ -65,8 +65,7 @@ __override int board_get_version(void) * This loop retries to ensure rail is settled and read is successful */ for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { - - rv = gpio_pin_get_dt(&bom_id_config[0]); + rv = gpio_pin_get_dt(&bom_id_config[0]); if (rv >= 0) break; @@ -82,20 +81,20 @@ __override int board_get_version(void) * BOM ID [2] : IOEX[0] * BOM ID [1:0] : IOEX[15:14] */ - bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; bom_id |= gpio_pin_get_dt(&bom_id_config[2]); /* * FAB ID [1:0] : IOEX[2:1] + 1 */ - fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; fab_id |= gpio_pin_get_dt(&fab_id_config[1]); fab_id += 1; /* * BOARD ID[5:0] : IOEX[13:8] */ - board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; -- cgit v1.2.1 From 2371973f291fa61a7b9d1a9bfe1b16ecf631f349 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:39 -0600 Subject: board/boten/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7fe57fe53e6b285cca2844c6ad4eaef23384a340 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728087 Reviewed-by: Jeremy Bettis --- board/boten/board.h | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/board/boten/board.h b/board/boten/board.h index a78296e997..b1442fd5e2 100644 --- a/board/boten/board.h +++ b/board/boten/board.h @@ -26,7 +26,8 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -40,8 +41,8 @@ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ @@ -109,26 +110,17 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 5af32225ce9bfc904720330ab9db1373334a5546 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:04 -0600 Subject: zephyr/projects/nissa/src/nereid/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib43204bd2a537f1605e0e6deefb20160f68aad4e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730790 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nereid/usbc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/src/nereid/usbc.c index eeab449c32..9e12f05188 100644 --- a/zephyr/projects/nissa/src/nereid/usbc.c +++ b/zephyr/projects/nissa/src/nereid/usbc.c @@ -103,8 +103,8 @@ static void board_chargers_suspend(struct ap_power_ev_callback *const cb, fn = sm5803_disable_low_power_mode; break; default: - LOG_WRN("%s: power event %d is not recognized", - __func__, data.event); + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); return; } @@ -281,7 +281,7 @@ void board_reset_pd_mcu(void) */ } -#define INT_RECHECK_US 5000 +#define INT_RECHECK_US 5000 /* C0 interrupt line shared by BC 1.2 and charger */ -- cgit v1.2.1 From 19829c4d11a5e714a3cf03b59f714893eae0a881 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:50 -0600 Subject: board/nucleo-f072rb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d0ccc3eef63ad44859e4ce17e82da74cf7c2f61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728775 Reviewed-by: Jeremy Bettis --- board/nucleo-f072rb/board.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/board/nucleo-f072rb/board.c b/board/nucleo-f072rb/board.c index 078af171cb..17181fb600 100644 --- a/board/nucleo-f072rb/board.c +++ b/board/nucleo-f072rb/board.c @@ -21,8 +21,12 @@ void button_event(enum gpio_signal signal) * Mock interrupt handler. It's supposed to be overwritten by each suite * if needed. */ -__attribute__((weak)) void cts_irq1(enum gpio_signal signal) {} -__attribute__((weak)) void cts_irq2(enum gpio_signal signal) {} +__attribute__((weak)) void cts_irq1(enum gpio_signal signal) +{ +} +__attribute__((weak)) void cts_irq2(enum gpio_signal signal) +{ +} #endif #include "gpio_list.h" @@ -38,14 +42,12 @@ void tick_event(void) DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT); #ifdef CTS_MODULE_I2C -const struct i2c_port_t i2c_ports[] = { - { - .name = "test", - .port = STM32_I2C1_PORT, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "test", + .port = STM32_I2C1_PORT, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -57,6 +59,5 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); static void board_init(void) { gpio_enable_interrupt(GPIO_USER_BUTTON); - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From d0230b224dea4e66bff836fb18632eed94316d2e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:49 -0600 Subject: board/scarlet/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfd203655f846de45978be024ffc598a321bcf1a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728915 Reviewed-by: Jeremy Bettis --- board/scarlet/board.c | 108 +++++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 58 deletions(-) diff --git a/board/scarlet/board.c b/board/scarlet/board.c index 3d9049c983..0ea2d89c73 100644 --- a/board/scarlet/board.c +++ b/board/scarlet/board.c @@ -43,8 +43,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -68,27 +68,23 @@ static void warm_reset_request_interrupt(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, + { .name = "charger", + .port = I2C_PORT_CHARGER, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -104,22 +100,22 @@ const struct charger_config_t chg_chips[] = { /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"}, - {GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"}, - {GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"}, - {GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"}, + { GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" }, + { GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" }, + { GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" }, + { GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); #ifdef CONFIG_TEMP_SENSOR_TMP432 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */ const struct temp_sensor_t temp_sensors[] = { - {"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL, 4}, - {"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1, 4}, - {"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE2, 4}, + { "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL, 4 }, + { "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1, 4 }, + { "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE2, 4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -128,9 +124,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); * same order as enum temp_sensor_id. To always ignore any temp, use 0. */ struct ec_thermal_config thermal_params[] = { - {{0, 0, 0}, 0, 0}, /* TMP432_Internal */ - {{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */ - {{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); #endif @@ -166,11 +162,11 @@ void board_reset_pd_mcu(void) { } -enum critical_shutdown board_critical_shutdown_check( - struct charge_state_data *curr) +enum critical_shutdown +board_critical_shutdown_check(struct charge_state_data *curr) { if ((curr->batt.flags & BATT_FLAG_BAD_VOLTAGE) || - (curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH)) + (curr->batt.voltage <= BAT_LOW_VOLTAGE_THRESH)) return CRITICAL_SHUTDOWN_CUTOFF; else return CRITICAL_SHUTDOWN_IGNORE; @@ -212,11 +208,11 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int extpower_is_present(void) @@ -252,8 +248,7 @@ static void board_spi_enable(void) spi_enable(&spi_devices[0], 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -265,8 +260,7 @@ static void board_spi_disable(void) gpio_config_module(MODULE_SPI_CONTROLLER, 0); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); static void board_init(void) @@ -306,8 +300,8 @@ void board_config_pre_init(void) * Ch4: USART1_TX / Ch5: USART1_RX (1000) * Ch6: SPI2_RX / Ch7: SPI2_TX (0011) */ - STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | - (3 << 20) | (3 << 24); + STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) | + (3 << 24); } enum scarlet_board_version { @@ -335,16 +329,16 @@ struct { enum scarlet_board_version version; int expect_mv; } const scarlet_boards[] = { - { BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */ - { BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */ - { BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */ - { BOARD_VERSION_REV3, 427 }, /* 56K , 17.4K ohm */ - { BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */ - { BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */ - { BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */ - { BOARD_VERSION_REV7, 900 }, /* 56K , 56K ohm */ - { BOARD_VERSION_REV8, 1023 }, /* 47K , 61.9K ohm */ - { BOARD_VERSION_REV9, 1137 }, /* 47K , 80.6K ohm */ + { BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */ + { BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */ + { BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */ + { BOARD_VERSION_REV3, 427 }, /* 56K , 17.4K ohm */ + { BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */ + { BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */ + { BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */ + { BOARD_VERSION_REV7, 900 }, /* 56K , 56K ohm */ + { BOARD_VERSION_REV8, 1023 }, /* 47K , 61.9K ohm */ + { BOARD_VERSION_REV9, 1137 }, /* 47K , 80.6K ohm */ { BOARD_VERSION_REV10, 1240 }, /* 56K , 124K ohm */ { BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */ { BOARD_VERSION_REV12, 1457 }, /* 47K , 200K ohm */ @@ -400,11 +394,9 @@ static struct mutex g_base_mutex; static struct bmi_drv_data_t g_bmi160_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* -- cgit v1.2.1 From dc2dffd379036a6b65252b37bcfcf2934382122b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:46 -0600 Subject: chip/mec1322/dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19ecc4c3b59fe4fb77975525194e434c5d45fd54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729327 Reviewed-by: Jeremy Bettis --- chip/mec1322/dma.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c index a6c6fed5ad..14a8b4173c 100644 --- a/chip/mec1322/dma.c +++ b/chip/mec1322/dma.c @@ -14,7 +14,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) +#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args) mec1322_dma_chan_t *dma_get_channel(enum dma_channel channel) { @@ -65,7 +65,7 @@ void dma_disable_all(void) * MEC1322_DMA_INC_MEM for rx */ static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, - void *periph, void *memory, unsigned flags) + void *periph, void *memory, unsigned flags) { int xfer_size = (flags >> 20) & 0x7; @@ -99,11 +99,11 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count, */ prepare_channel(chan, count, option->periph, (void *)memory, MEC1322_DMA_INC_MEM | MEC1322_DMA_TO_DEV | - MEC1322_DMA_DEV(option->channel) | option->flags); + MEC1322_DMA_DEV(option->channel) | + option->flags); } -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) +void dma_start_rx(const struct dma_option *option, unsigned count, void *memory) { mec1322_dma_chan_t *chan; @@ -111,7 +111,7 @@ void dma_start_rx(const struct dma_option *option, unsigned count, prepare_channel(chan, count, option->periph, memory, MEC1322_DMA_INC_MEM | MEC1322_DMA_DEV(option->channel) | - option->flags); + option->flags); dma_go(chan); } -- cgit v1.2.1 From 215d69f4a635c1ea1bf5ea3fd598bbd9d4ec8175 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:32 -0600 Subject: board/careena/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d71d66eafe69387332b392452563c42ec018399 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728114 Reviewed-by: Jeremy Bettis --- board/careena/board.c | 74 ++++++++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 42 deletions(-) diff --git a/board/careena/board.c b/board/careena/board.c index e8171b1be0..6e6f26102c 100644 --- a/board/careena/board.c +++ b/board/careena/board.c @@ -26,45 +26,35 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -114,15 +104,15 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {-1, -1}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {-1, -1}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { -1, -1 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { -1, -1 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); static int board_is_support_ps8755_tcpc(void) { -- cgit v1.2.1 From 6f02b9a2c4922697ecfc7c8b5803c10c3ddaddcd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:18 -0600 Subject: include/cros_version.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53ceccc33a80ad48246c8d5aba72640fa67be5a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730236 Reviewed-by: Jeremy Bettis --- include/cros_version.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/cros_version.h b/include/cros_version.h index 47fa8d1774..ecaaebc8a1 100644 --- a/include/cros_version.h +++ b/include/cros_version.h @@ -14,8 +14,8 @@ #define CROS_EC_IMAGE_DATA_COOKIE1 0xce778899 #define CROS_EC_IMAGE_DATA_COOKIE2 0xceaabbdd #define CROS_EC_IMAGE_DATA_COOKIE3 0xceeeff00 -#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8) -#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0) +#define CROS_EC_IMAGE_DATA_COOKIE3_MASK GENMASK(31, 8) +#define CROS_EC_IMAGE_DATA_COOKIE3_VERSION GENMASK(7, 0) #define CROS_FWID_MISSING_STR "CROS_FWID_MISSING" @@ -40,4 +40,4 @@ extern const void *__image_size; * @return Number of commits in integer or 0 on error */ int ver_get_num_commits(enum ec_image copy); -#endif /* __CROS_EC_VERSION_H */ +#endif /* __CROS_EC_VERSION_H */ -- cgit v1.2.1 From aca7b2b0ac3a1816ded665261172648b5621b138 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:13 -0600 Subject: zephyr/shim/include/board_led.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I04daef9730ce1667eecc06a86504abf7cf3f3b96 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730582 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/board_led.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/include/board_led.h b/zephyr/shim/include/board_led.h index 205c96c4c3..b71a2a7fe9 100644 --- a/zephyr/shim/include/board_led.h +++ b/zephyr/shim/include/board_led.h @@ -12,13 +12,13 @@ struct board_led_pwm_dt_channel { pwm_flags_t flags; }; -#define BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(node_id) \ - { \ +#define BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(node_id) \ + { \ .dev = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ - .channel = DT_PWMS_CHANNEL(node_id), \ - .flags = DT_PWMS_FLAGS(node_id), \ + .channel = DT_PWMS_CHANNEL(node_id), \ + .flags = DT_PWMS_FLAGS(node_id), \ } #define BOARD_LED_HZ_TO_PERIOD_NS(freq_hz) (NSEC_PER_SEC / freq_hz) -#endif /* __BOARD_LED_H */ +#endif /* __BOARD_LED_H */ -- cgit v1.2.1 From 5e45646151418d121d407e032e8be38f034e09f0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:23 -0600 Subject: chip/stm32/debug_printf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12025d5808bd5466c34b46751a7a95403f81ba75 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729489 Reviewed-by: Jeremy Bettis --- chip/stm32/debug_printf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h index 6091cfc7fc..dba843985d 100644 --- a/chip/stm32/debug_printf.h +++ b/chip/stm32/debug_printf.h @@ -8,8 +8,8 @@ #define __CROS_EC_DEBUG_H #ifdef CONFIG_DEBUG_PRINTF -__attribute__((__format__(__printf__, 1, 2))) -void debug_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) void +debug_printf(const char *format, ...); #else #define debug_printf(...) #endif -- cgit v1.2.1 From da3ad9b3bdf26299ff1056bed7f9a468e1aab6aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:14 -0600 Subject: driver/als_bh1730.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5ef6ef6ed19890aa83a0ed405823daf94b2e9b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729899 Reviewed-by: Jeremy Bettis --- driver/als_bh1730.c | 46 +++++++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/driver/als_bh1730.c b/driver/als_bh1730.c index d4e3a810a5..d6ffe2bcae 100644 --- a/driver/als_bh1730.c +++ b/driver/als_bh1730.c @@ -11,8 +11,8 @@ #include "driver/als_bh1730.h" #include "i2c.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args) /** * Convert BH1730 data0, data1 to lux @@ -32,16 +32,16 @@ static int bh1730_convert_to_lux(uint32_t data0_1) else d_temp = d1_1k / data0; - if(d_temp < BH1730_LUXTH1_1K) { + if (d_temp < BH1730_LUXTH1_1K) { d0_1k = BH1730_LUXTH1_D0_1K * data0; d1_1k = BH1730_LUXTH1_D1_1K * data1; - } else if(d_temp < BH1730_LUXTH2_1K) { + } else if (d_temp < BH1730_LUXTH2_1K) { d0_1k = BH1730_LUXTH2_D0_1K * data0; d1_1k = BH1730_LUXTH2_D1_1K * data1; - } else if(d_temp < BH1730_LUXTH3_1K) { + } else if (d_temp < BH1730_LUXTH3_1K) { d0_1k = BH1730_LUXTH3_D0_1K * data0; d1_1k = BH1730_LUXTH3_D1_1K * data1; - } else if(d_temp < BH1730_LUXTH4_1K) { + } else if (d_temp < BH1730_LUXTH4_1K) { d0_1k = BH1730_LUXTH4_D0_1K * data0; d1_1k = BH1730_LUXTH4_D1_1K * data1; } else @@ -64,8 +64,8 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v) int data0_1; /* read data0 and data1 from sensor */ - ret = i2c_read32(s->port, s->i2c_spi_addr_flags, - BH1730_DATA0LOW, &data0_1); + ret = i2c_read32(s->port, s->i2c_spi_addr_flags, BH1730_DATA0LOW, + &data0_1); if (ret != EC_SUCCESS) { CPRINTF("bh1730_read_lux - fail %d\n", ret); return ret; @@ -88,8 +88,7 @@ static int bh1730_read_lux(const struct motion_sensor_t *s, intv3_t v) } } -static int bh1730_set_range(struct motion_sensor_t *s, int range, - int rnd) +static int bh1730_set_range(struct motion_sensor_t *s, int range, int rnd) { /* Range is fixed by hardware */ if (range != s->default_range) @@ -99,8 +98,8 @@ static int bh1730_set_range(struct motion_sensor_t *s, int range, return EC_SUCCESS; } -static int bh1730_set_data_rate(const struct motion_sensor_t *s, - int rate, int roundup) +static int bh1730_set_data_rate(const struct motion_sensor_t *s, int rate, + int roundup) { struct bh1730_drv_data_t *drv_data = BH1730_GET_DATA(s); @@ -118,15 +117,13 @@ static int bh1730_get_data_rate(const struct motion_sensor_t *s) } static int bh1730_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) + const int16_t *offset, int16_t temp) { return EC_SUCCESS; } -static int bh1730_get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) +static int bh1730_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { *offset = 0; @@ -141,10 +138,9 @@ static int bh1730_init(struct motion_sensor_t *s) int ret; /* power and measurement bit high */ - ret = i2c_write8(s->port, s->i2c_spi_addr_flags, - BH1730_CONTROL, - BH1730_CONTROL_POWER_ENABLE - | BH1730_CONTROL_ADC_EN_ENABLE); + ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_CONTROL, + BH1730_CONTROL_POWER_ENABLE | + BH1730_CONTROL_ADC_EN_ENABLE); if (ret != EC_SUCCESS) { CPRINTF("bh1730_init_sensor - enable fail %d\n", ret); @@ -152,15 +148,15 @@ static int bh1730_init(struct motion_sensor_t *s) } /* set timing */ - ret = i2c_write8(s->port, s->i2c_spi_addr_flags, - BH1730_TIMING, BH1730_CONF_ITIME); + ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_TIMING, + BH1730_CONF_ITIME); if (ret != EC_SUCCESS) { CPRINTF("bh1730_init_sensor - time fail %d\n", ret); return ret; } /* set ADC gain */ - ret = i2c_write8(s->port, s->i2c_spi_addr_flags, - BH1730_GAIN, BH1730_CONF_GAIN); + ret = i2c_write8(s->port, s->i2c_spi_addr_flags, BH1730_GAIN, + BH1730_CONF_GAIN); if (ret != EC_SUCCESS) { CPRINTF("bh1730_init_sensor - gain fail %d\n", ret); -- cgit v1.2.1 From 47e1bb7939d9c02f36a06cb1d157cc139faf8171 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:19 -0600 Subject: util/uut/cmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50209c26866737cedc3efc5410ba4939d19f6c85 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730658 Reviewed-by: Jeremy Bettis --- util/uut/cmd.c | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/util/uut/cmd.c b/util/uut/cmd.c index 57cf75a29e..576b596c5c 100644 --- a/util/uut/cmd.c +++ b/util/uut/cmd.c @@ -14,7 +14,7 @@ #include "lib_crc.h" #include "main.h" - /* Extracting Byte - 8 bit: MSB, LSB */ +/* Extracting Byte - 8 bit: MSB, LSB */ #define MSB(u16) ((uint8_t)((uint16_t)(u16) >> 8)) #define LSB(u16) ((uint8_t)(u16)) @@ -85,7 +85,7 @@ void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len) *--------------------------------------------------------------------------- */ void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf, - uint8_t *cmd_info, uint32_t *cmd_len) + uint8_t *cmd_info, uint32_t *cmd_len) { uint32_t i; union cmd_addr adr_tr; @@ -136,7 +136,7 @@ void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf, *--------------------------------------------------------------------------- */ void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info, - uint32_t *cmd_len) + uint32_t *cmd_len) { uint32_t i; union cmd_addr adr_tr; @@ -251,7 +251,7 @@ void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num) *--------------------------------------------------------------------------- */ void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf, - uint32_t *cmd_num) + uint32_t *cmd_num) { uint32_t cmd = 0; @@ -280,7 +280,7 @@ void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf, *--------------------------------------------------------------------------- */ void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf, - uint32_t *cmd_num) + uint32_t *cmd_num) { uint32_t cmd = 0; @@ -325,10 +325,11 @@ bool cmd_disp_sync(uint8_t *resp_buf) *--------------------------------------------------------------------------- */ bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num, - uint32_t total_size) + uint32_t total_size) { if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) { - display_color_msg(SUCCESS, + display_color_msg( + SUCCESS, "\rTransmitted packet of size %u bytes, packet " "[%u]out of [%u]", resp_size, resp_num, total_size); @@ -352,10 +353,11 @@ bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num, *--------------------------------------------------------------------------- */ bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num, - uint32_t total_size) + uint32_t total_size) { if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) { - display_color_msg(SUCCESS, + display_color_msg( + SUCCESS, "\rReceived packet of size %u bytes, packet [%u] out " "of [%u]", resp_size, resp_num, total_size); @@ -412,10 +414,11 @@ void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num) { if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) { display_color_msg(SUCCESS, - "Flash Erase of device [%u] Passed\n", dev_num); + "Flash Erase of device [%u] Passed\n", + dev_num); } else { - display_color_msg( - FAIL, "Flash Erase of device [%u] Failed\n", dev_num); + display_color_msg(FAIL, "Flash Erase of device [%u] Failed\n", + dev_num); } } @@ -433,10 +436,11 @@ void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num) { if (resp_buf[0] == (uint8_t)(UFPP_WRITE_CMD)) { display_color_msg(SUCCESS, - "Sector Erase of device [%lu] Passed\n", dev_num); + "Sector Erase of device [%lu] Passed\n", + dev_num); } else { - display_color_msg( - FAIL, "Sector Erase of device [%lu] Failed\n", dev_num); + display_color_msg(FAIL, "Sector Erase of device [%lu] Failed\n", + dev_num); } } @@ -471,11 +475,13 @@ void cmd_disp_exec_exit(uint8_t *resp_buf) void cmd_disp_exec_ret(uint8_t *resp_buf) { if (resp_buf[1] == (uint8_t)(UFPP_FCALL_RSLT_CMD)) { - display_color_msg(SUCCESS, + display_color_msg( + SUCCESS, "Execute Command Passed, execution result is [0x%X]\n", resp_buf[2]); } else { - display_color_msg(FAIL, + display_color_msg( + FAIL, "Execute Command Failed [0x%X] [0x%X], rslt=[0x%X]\n", resp_buf[0], resp_buf[1], resp_buf[2]); } -- cgit v1.2.1 From 235de53282b2aae2209a1d7ac5bb255d48646193 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:23 -0600 Subject: common/host_command_pd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If59371dd14a70f1c1a299679f2a2502468ee32c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729653 Reviewed-by: Jeremy Bettis --- common/host_command_pd.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/common/host_command_pd.c b/common/host_command_pd.c index 7d82249d21..c14c5b7a97 100644 --- a/common/host_command_pd.c +++ b/common/host_command_pd.c @@ -20,10 +20,10 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PD_HOST_CMD, format, ##args) -#define TASK_EVENT_EXCHANGE_PD_STATUS TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_HIBERNATING TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_EXCHANGE_PD_STATUS TASK_EVENT_CUSTOM_BIT(0) +#define TASK_EVENT_HIBERNATING TASK_EVENT_CUSTOM_BIT(1) /* Define local option for if we are a TCPM with an off chip TCPC */ #if defined(CONFIG_USB_POWER_DELIVERY) && !defined(CONFIG_USB_PD_TCPM_STUB) @@ -61,7 +61,7 @@ void host_command_pd_request_hibernate(void) #ifdef CONFIG_HOSTCMD_PD static int pd_send_host_command(struct ec_params_pd_status *ec_status, - struct ec_response_pd_status *pd_status) + struct ec_response_pd_status *pd_status) { return pd_host_command(EC_CMD_PD_EXCHANGE_STATUS, EC_VER_PD_EXCHANGE_STATUS, ec_status, @@ -126,8 +126,8 @@ static void pd_check_chg_status(struct ec_response_pd_status *pd_status) #endif /* Set input current limit */ - rv = charge_set_input_current_limit(MAX(pd_status->curr_lim_ma, - CONFIG_CHARGER_INPUT_CURRENT), 0); + rv = charge_set_input_current_limit( + MAX(pd_status->curr_lim_ma, CONFIG_CHARGER_INPUT_CURRENT), 0); if (rv < 0) CPRINTS("Failed to set input curr limit from PD MCU"); } @@ -201,7 +201,7 @@ static void pd_exchange_status(uint32_t ec_state) if (!first_exchange) /* Delay to prevent task starvation */ - usleep(5*MSEC); + usleep(5 * MSEC); first_exchange = 0; } while (pd_get_alert()); #endif /* USB_TCPM_WITH_OFF_CHIP_TCPC */ -- cgit v1.2.1 From 408b037346efc7d9fce0cb9003647f7b6212a6d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:08 -0600 Subject: board/stern/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01147fa7465d71e73c2b17fdea7575bfe81e2af4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728967 Reviewed-by: Jeremy Bettis --- board/stern/board.c | 83 ++++++++++++++++++++++------------------------------- 1 file changed, 35 insertions(+), 48 deletions(-) diff --git a/board/stern/board.c b/board/stern/board.c index fd3a95a987..a8ba476dff 100644 --- a/board/stern/board.c +++ b/board/stern/board.c @@ -46,8 +46,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -59,40 +59,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -100,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -157,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -239,12 +232,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -301,8 +294,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -316,8 +308,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -356,17 +347,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ /* Lid accel private data */ -- cgit v1.2.1 From e3295ad6f49e0797b9de075c1505c60f2cd8a4ed Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Mon, 27 Jun 2022 20:49:48 -0600 Subject: test: Reconfigure drivers BUILD.py to use .variant Following up on chromium:3724970. Updating the build file to use the supported variant functionality of zmake to make the tests more conformant. BRANCH=none BUG=none TEST=zmake test test-drivers-isl923x TEST=zmake test test-drivers-led_driver Signed-off-by: Yuval Peress Change-Id: I04912e56c180566bb4bac4b08d2aca828d85a3b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727783 Commit-Queue: Jack Rosenthal Reviewed-by: Jack Rosenthal --- zephyr/test/drivers/BUILD.py | 50 ++++++++++++-------------------------------- 1 file changed, 13 insertions(+), 37 deletions(-) diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py index d8c2b6caab..3c94b7d55e 100644 --- a/zephyr/test/drivers/BUILD.py +++ b/zephyr/test/drivers/BUILD.py @@ -5,49 +5,25 @@ """Construct the drivers test binaries""" -default_config = { - "dts_overlays": [ +drivers = register_host_test( + test_name="drivers", + dts_overlays=[ here / "overlay.dts", ], - "kconfig_files": [ + kconfig_files=[ here / "prj.conf", ], - "test_args": ["-flash={test_temp_dir}/flash.bin"], -} - - -def merge_dictionary(dict_1, dict_2): - """Merge dict_1 and dict_2 and return the result""" - dict_3 = {**dict_1, **dict_2} - for key, value in dict_3.items(): - if key in dict_1 and key in dict_2: - if isinstance(value, list) or isinstance(dict_1[key], list): - dict_3[key] = value + dict_1[key] - else: - dict_3[key] = [value, dict_1[key]] - return dict_3 - - -register_host_test( - "drivers", - **default_config, ) -register_host_test( - "drivers-isl923x", - **default_config, +isl923x = drivers.variant( + project_name="test-drivers-isl923x", ) -register_host_test( - "drivers-led_driver", - **merge_dictionary( - default_config, - { - "dts_overlays": [ - here / "led_driver" / "led_pins.dts", - here / "led_driver" / "led_policy.dts", - ], - "kconfig_files": [here / "led_driver" / "prj.conf"], - }, - ), +led_driver = drivers.variant( + project_name="test-drivers-led_driver", + dts_overlays=[ + here / "led_driver" / "led_pins.dts", + here / "led_driver" / "led_policy.dts", + ], + kconfig_files=[here / "led_driver" / "prj.conf"], ) -- cgit v1.2.1 From 44cfe6f1d6f32733decb63be10fe4c6cb2a91a71 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:38 -0600 Subject: include/port80.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f6a2d5318d8c984a24a22cf4f5b743ff8bea33f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730379 Reviewed-by: Jeremy Bettis --- include/port80.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/port80.h b/include/port80.h index e6212ab593..3d3a906a18 100644 --- a/include/port80.h +++ b/include/port80.h @@ -11,9 +11,9 @@ #include "common.h" enum port_80_event { - PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ - PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ - PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */ + PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ + PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ + PORT_80_IGNORE = 0xffff, /* Invalid POST CODE */ }; /** @@ -31,4 +31,4 @@ void port_80_write(int data); */ int port_80_read(void); -#endif /* __CROS_EC_PORT80_H */ +#endif /* __CROS_EC_PORT80_H */ -- cgit v1.2.1 From bd378831e77626af32dc5423f68c4a36d525363d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:04 -0600 Subject: board/servo_v4p1/ioexpanders.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic63358e410a783af7ab66cdfe8f44537bfd64c1c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728947 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/ioexpanders.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/board/servo_v4p1/ioexpanders.h b/board/servo_v4p1/ioexpanders.h index 6565992857..9ca6915818 100644 --- a/board/servo_v4p1/ioexpanders.h +++ b/board/servo_v4p1/ioexpanders.h @@ -10,10 +10,7 @@ #define BOARD_ID_DET_OFFSET 3 #define BOARD_ID_DET_PORT 1 -enum uservo_fastboot_mux_sel_t { - MUX_SEL_USERVO = 0, - MUX_SEL_FASTBOOT = 1 -}; +enum uservo_fastboot_mux_sel_t { MUX_SEL_USERVO = 0, MUX_SEL_FASTBOOT = 1 }; /* * Initialize Ioexpanders @@ -236,14 +233,14 @@ int get_dut_chg_en(void); */ int host_or_chg_ctl(int en); -#define USERVO_FAULT_L BIT(0) -#define USB3_A0_FAULT_L BIT(1) -#define USB3_A1_FAULT_L BIT(2) -#define USB_DUTCHG_FLT_ODL BIT(3) -#define PP3300_DP_FAULT_L BIT(4) -#define DAC_BUF1_LATCH_FAULT_L BIT(5) -#define DAC_BUF2_LATCH_FAULT_L BIT(6) -#define PP5000_SRC_SEL BIT(7) +#define USERVO_FAULT_L BIT(0) +#define USB3_A0_FAULT_L BIT(1) +#define USB3_A1_FAULT_L BIT(2) +#define USB_DUTCHG_FLT_ODL BIT(3) +#define PP3300_DP_FAULT_L BIT(4) +#define DAC_BUF1_LATCH_FAULT_L BIT(5) +#define DAC_BUF2_LATCH_FAULT_L BIT(6) +#define PP5000_SRC_SEL BIT(7) /** * Read any faults that may have occurred. A fault has occurred if the @@ -271,8 +268,8 @@ int host_or_chg_ctl(int en); */ int read_faults(void); -#define HOST_CHRG_DET BIT(0) -#define SYS_PWR_IRQ_ODL BIT(6) +#define HOST_CHRG_DET BIT(0) +#define SYS_PWR_IRQ_ODL BIT(6) /** * Read irqs which indicate some system event. -- cgit v1.2.1 From 73f98bfac67d92d57a07216e7188b6b86dbf6657 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:50 -0600 Subject: board/servo_v4p1/dacs.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e551765b875fcc803d286affb2df5afda50cd64 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728930 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/dacs.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/servo_v4p1/dacs.c b/board/servo_v4p1/dacs.c index 838cdbbc8b..5cf3c0c5de 100644 --- a/board/servo_v4p1/dacs.c +++ b/board/servo_v4p1/dacs.c @@ -14,17 +14,17 @@ #define CC1_DAC_ADDR 0x48 #define CC2_DAC_ADDR 0x49 -#define REG_NOOP 0 -#define REG_DEVID 1 -#define REG_SYNC 2 -#define REG_CONFIG 3 -#define REG_GAIN 4 +#define REG_NOOP 0 +#define REG_DEVID 1 +#define REG_SYNC 2 +#define REG_CONFIG 3 +#define REG_GAIN 4 #define REG_TRIGGER 5 -#define REG_STATUS 7 -#define REG_DAC 8 +#define REG_STATUS 7 +#define REG_DAC 8 -#define DAC1 BIT(0) -#define DAC2 BIT(1) +#define DAC1 BIT(0) +#define DAC2 BIT(1) static uint8_t dac_enabled; @@ -135,7 +135,6 @@ static int cmd_cc_dac(int argc, char *argv[]) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, - "dac <\"on\"|\"off\"|mv>", +DECLARE_CONSOLE_COMMAND(cc_dac, cmd_cc_dac, "dac <\"on\"|\"off\"|mv>", "Set Servo v4.1 CC dacs"); #endif -- cgit v1.2.1 From 885d9eada1b22e615ceaa2ed29f253d440cec4d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:36 -0600 Subject: util/genvif.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9cfb3ed68b9a2b1706a82061d9c4d805e50cc7ae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730625 Reviewed-by: Jeremy Bettis --- util/genvif.c | 1662 ++++++++++++++++++++++++++------------------------------- 1 file changed, 763 insertions(+), 899 deletions(-) diff --git a/util/genvif.c b/util/genvif.c index 2b1ba8c494..4ae02e47a8 100644 --- a/util/genvif.c +++ b/util/genvif.c @@ -25,14 +25,14 @@ #include "genvif.h" -#define VIF_APP_VENDOR_VALUE "Google" -#define VIF_APP_NAME_VALUE "EC GENVIF" -#define VIF_APP_VERSION_VALUE "3.2.3.0" -#define VENDOR_NAME_VALUE "Google" +#define VIF_APP_VENDOR_VALUE "Google" +#define VIF_APP_NAME_VALUE "EC GENVIF" +#define VIF_APP_VERSION_VALUE "3.2.3.0" +#define VENDOR_NAME_VALUE "Google" -#define DEFAULT_MISSING_TID 0xFFFF -#define DEFAULT_MISSING_PID 0xFFFF -#define DEFAULT_MISSING_BCD_DEV 0x0000 +#define DEFAULT_MISSING_TID 0xFFFF +#define DEFAULT_MISSING_PID 0xFFFF +#define DEFAULT_MISSING_BCD_DEV 0x0000 /* * XML namespace for VIF as of VifEditorRelease 3.2.3.0 @@ -47,11 +47,7 @@ struct vif_t vif; /* * local type to make decisions on the output for Source, Sink and DRP */ -enum dtype { - SRC = 0, - SNK, - DRP -}; +enum dtype { SRC = 0, SNK, DRP }; enum ptype { PORT_CONSUMER_ONLY = 0, @@ -309,14 +305,10 @@ const char *vif_component_name[] = { BUILD_ASSERT(ARRAY_SIZE(vif_component_name) == Component_Indexes); const char *vif_component_snk_pdo_name[] = { - NAME_INIT(Snk_PDO_Supply_Type), - NAME_INIT(Snk_PDO_APDO_Type), - NAME_INIT(Snk_PDO_Voltage), - NAME_INIT(Snk_PDO_PDP_Rating), - NAME_INIT(Snk_PDO_Op_Power), - NAME_INIT(Snk_PDO_Min_Voltage), - NAME_INIT(Snk_PDO_Max_Voltage), - NAME_INIT(Snk_PDO_Op_Current), + NAME_INIT(Snk_PDO_Supply_Type), NAME_INIT(Snk_PDO_APDO_Type), + NAME_INIT(Snk_PDO_Voltage), NAME_INIT(Snk_PDO_PDP_Rating), + NAME_INIT(Snk_PDO_Op_Power), NAME_INIT(Snk_PDO_Min_Voltage), + NAME_INIT(Snk_PDO_Max_Voltage), NAME_INIT(Snk_PDO_Op_Current), }; BUILD_ASSERT(ARRAY_SIZE(vif_component_snk_pdo_name) == Snk_PDO_Indexes); @@ -343,7 +335,7 @@ const char *vif_component_sop_svid_mode_name[] = { NAME_INIT(SVID_Mode_Recog_Value_SOP), }; BUILD_ASSERT(ARRAY_SIZE(vif_component_sop_svid_mode_name) == - SopSVID_Mode_Indexes); + SopSVID_Mode_Indexes); const char *vif_component_sop_svid_name[] = { NAME_INIT(SVID_SOP), @@ -393,7 +385,7 @@ const char *vif_product_pcie_endpoint_name[] = { NAME_INIT(USB4_PCIe_Endpoint_Class_Code), }; BUILD_ASSERT(ARRAY_SIZE(vif_product_pcie_endpoint_name) == - PCIe_Endpoint_Indexes); + PCIe_Endpoint_Indexes); const char *vif_product_usb4_router_name[] = { NAME_INIT(USB4_Router_ID), @@ -414,7 +406,6 @@ const char *vif_product_usb4_router_name[] = { }; BUILD_ASSERT(ARRAY_SIZE(vif_product_usb4_router_name) == USB4_Router_Indexes); - static bool streq(const char *str1, const char *str2) { if (str1 == NULL && str2 == NULL) @@ -479,8 +470,8 @@ static bool get_vif_field_number(struct vif_field_t *vif_field, int *value) return rv; } -__maybe_unused -static int get_vif_number(struct vif_field_t *vif_field, int default_value) +__maybe_unused static int get_vif_number(struct vif_field_t *vif_field, + int default_value) { int ret_value; @@ -528,8 +519,8 @@ static bool get_vif_bool(struct vif_field_t *vif_field, bool default_value) } /** String **/ -__maybe_unused -static bool get_vif_field_tag_str(struct vif_field_t *vif_field, char **value) +__maybe_unused static bool get_vif_field_tag_str(struct vif_field_t *vif_field, + char **value) { if (vif_field->tag_value == NULL) return false; @@ -537,8 +528,8 @@ static bool get_vif_field_tag_str(struct vif_field_t *vif_field, char **value) *value = vif_field->tag_value; return true; } -__maybe_unused -static bool get_vif_field_str_str(struct vif_field_t *vif_field, char **value) +__maybe_unused static bool get_vif_field_str_str(struct vif_field_t *vif_field, + char **value) { if (vif_field->str_value == NULL) return false; @@ -550,7 +541,6 @@ static bool get_vif_field_str_str(struct vif_field_t *vif_field, char **value) * VIF Structure Override Value Retrieve Functions *****************************************************************************/ - /***************************************************************************** * Generic Helper Functions */ @@ -561,9 +551,8 @@ static bool is_src(void) /* Determine if we are DRP, SRC or SNK */ was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[Type_C_State_Machine], - &override_value); + &vif.Component[component_index].vif_field[Type_C_State_Machine], + &override_value); if (was_overridden) { switch (override_value) { case SRC: @@ -578,15 +567,14 @@ static bool is_src(void) } if (!was_overridden) { was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[PD_Port_Type], - &override_value); + &vif.Component[component_index].vif_field[PD_Port_Type], + &override_value); if (was_overridden) { switch (override_value) { - case PORT_PROVIDER_ONLY: /* SRC */ - case PORT_DRP: /* DRP */ + case PORT_PROVIDER_ONLY: /* SRC */ + case PORT_DRP: /* DRP */ return true; - case PORT_CONSUMER_ONLY: /* SNK */ + case PORT_CONSUMER_ONLY: /* SNK */ return false; default: was_overridden = false; @@ -602,9 +590,8 @@ static bool is_snk(void) /* Determine if we are DRP, SRC or SNK */ was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[Type_C_State_Machine], - &override_value); + &vif.Component[component_index].vif_field[Type_C_State_Machine], + &override_value); if (was_overridden) { switch (override_value) { case SNK: @@ -619,15 +606,14 @@ static bool is_snk(void) } if (!was_overridden) { was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[PD_Port_Type], - &override_value); + &vif.Component[component_index].vif_field[PD_Port_Type], + &override_value); if (was_overridden) { switch (override_value) { - case PORT_CONSUMER_ONLY: /* SNK */ - case PORT_DRP: /* DRP */ + case PORT_CONSUMER_ONLY: /* SNK */ + case PORT_DRP: /* DRP */ return true; - case PORT_PROVIDER_ONLY: /* SRC */ + case PORT_PROVIDER_ONLY: /* SRC */ return false; default: was_overridden = false; @@ -643,9 +629,8 @@ static bool is_drp(void) /* Determine if we are DRP, SRC or SNK */ was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[Type_C_State_Machine], - &override_value); + &vif.Component[component_index].vif_field[Type_C_State_Machine], + &override_value); if (was_overridden) { switch (override_value) { case DRP: @@ -660,16 +645,15 @@ static bool is_drp(void) } if (!was_overridden) { was_overridden = get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[PD_Port_Type], - &override_value); + &vif.Component[component_index].vif_field[PD_Port_Type], + &override_value); if (was_overridden) { switch (override_value) { - case PORT_DRP: /* DRP */ + case PORT_DRP: /* DRP */ return true; - case PORT_CONSUMER_ONLY: /* SNK */ + case PORT_CONSUMER_ONLY: /* SNK */ return false; - case PORT_PROVIDER_ONLY: /* SRC */ + case PORT_PROVIDER_ONLY: /* SRC */ default: was_overridden = false; } @@ -683,80 +667,79 @@ static bool is_drp(void) static bool can_act_as_device(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Type_C_Can_Act_As_Device], + .vif_field[Type_C_Can_Act_As_Device], #if defined(USB_DEV_CLASS) && defined(USB_CLASS_BILLBOARD) USB_DEV_CLASS == USB_CLASS_BILLBOARD #else false #endif - ); + ); } static bool can_act_as_host(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Type_C_Can_Act_As_Host], + .vif_field[Type_C_Can_Act_As_Host], (!(IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD)))); } static bool is_usb4_supported(void) { - return get_vif_bool(&vif.Component[component_index] - .vif_field[USB4_Supported], - IS_ENABLED(CONFIG_USB_PD_USB4)); + return get_vif_bool( + &vif.Component[component_index].vif_field[USB4_Supported], + IS_ENABLED(CONFIG_USB_PD_USB4)); } static bool is_usb4_tbt3_compatible(void) { - return get_vif_bool(&vif.Component[component_index] - .vif_field[USB4_TBT3_Compatibility_Supported], - IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)); + return get_vif_bool( + &vif.Component[component_index] + .vif_field[USB4_TBT3_Compatibility_Supported], + IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE)); } static bool is_usb4_pcie_tunneling_supported(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[USB4_PCIe_Tunneling_Supported], + .vif_field[USB4_PCIe_Tunneling_Supported], IS_ENABLED(CONFIG_USB_PD_PCIE_TUNNELING)); } static bool is_usb_pd_supported(void) { - return get_vif_bool(&vif.Component[component_index] - .vif_field[USB_PD_Support], - (is_usb4_supported() || - IS_ENABLED(CONFIG_USB_PRL_SM) || - IS_ENABLED(CONFIG_USB_POWER_DELIVERY))); + return get_vif_bool( + &vif.Component[component_index].vif_field[USB_PD_Support], + (is_usb4_supported() || IS_ENABLED(CONFIG_USB_PRL_SM) || + IS_ENABLED(CONFIG_USB_POWER_DELIVERY))); } static bool is_usb_comms_capable(void) { - return get_vif_bool(&vif.Component[component_index] - .vif_field[USB_Comms_Capable], - is_usb4_supported() || - (!(IS_ENABLED(CONFIG_USB_VPD) || - IS_ENABLED(CONFIG_USB_CTVPD)))); + return get_vif_bool( + &vif.Component[component_index].vif_field[USB_Comms_Capable], + is_usb4_supported() || (!(IS_ENABLED(CONFIG_USB_VPD) || + IS_ENABLED(CONFIG_USB_CTVPD)))); } static bool is_alt_mode_controller(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Type_C_Is_Alt_Mode_Controller], + .vif_field[Type_C_Is_Alt_Mode_Controller], IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)); } static bool is_alt_mode_adapter(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Type_C_Is_Alt_Mode_Adapter], + .vif_field[Type_C_Is_Alt_Mode_Adapter], IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)); } static bool does_respond_to_discov_sop_ufp(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Responds_To_Discov_SOP_UFP], + .vif_field[Responds_To_Discov_SOP_UFP], (is_usb4_supported() || IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))); } @@ -764,7 +747,7 @@ static bool does_respond_to_discov_sop_ufp(void) static bool does_respond_to_discov_sop_dfp(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Responds_To_Discov_SOP_DFP], + .vif_field[Responds_To_Discov_SOP_DFP], (is_usb4_supported() || IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE))); } @@ -772,23 +755,21 @@ static bool does_respond_to_discov_sop_dfp(void) static bool does_support_device_usb_data(void) { return get_vif_bool(&vif.Component[component_index] - .vif_field[Device_Supports_USB_Data], - (is_usb4_supported() || - can_act_as_device())); + .vif_field[Device_Supports_USB_Data], + (is_usb4_supported() || can_act_as_device())); } static bool does_support_host_usb_data(void) { int type_c_state_machine; - if (!get_vif_field_tag_number( - &vif.Component[component_index] - .vif_field[Type_C_State_Machine], - &type_c_state_machine)) + if (!get_vif_field_tag_number(&vif.Component[component_index] + .vif_field[Type_C_State_Machine], + &type_c_state_machine)) return false; return get_vif_bool(&vif.Component[component_index] - .vif_field[Host_Supports_USB_Data], + .vif_field[Host_Supports_USB_Data], can_act_as_host()); } @@ -831,7 +812,6 @@ static bool vif_fields_present(const struct vif_field_t *vif_fields, int count) * Generic Helper Functions *****************************************************************************/ - /***************************************************************************** * VIF XML Output Functions */ @@ -874,9 +854,8 @@ static void vif_out_comment(FILE *vif_file, int level, const char *fmt, ...) fprintf(vif_file, "-->\r\n"); } -static const char vif_separator[] = - ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;" - ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"; +static const char vif_separator[] = ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;" + ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"; static void vif_out_field(FILE *vif_file, int level, const struct vif_field_t *vif_field) @@ -901,8 +880,7 @@ static void vif_out_field(FILE *vif_file, int level, fprintf(vif_file, " value=\"%s\"", vif_field->tag_value); if (vif_field->str_value) - fprintf(vif_file, ">%s\r\n", - vif_field->str_value, + fprintf(vif_file, ">%s\r\n", vif_field->str_value, vif_field->name); else fprintf(vif_file, " />\r\n"); @@ -910,8 +888,8 @@ static void vif_out_field(FILE *vif_file, int level, } static void vif_out_fields_range(FILE *vif_file, int level, - const struct vif_field_t *vif_fields, - int start, int count) + const struct vif_field_t *vif_fields, + int start, int count) { int index; @@ -925,10 +903,8 @@ static void vif_out_fields(FILE *vif_file, int level, vif_out_fields_range(vif_file, level, vif_fields, 0, count); } - - -static void vif_output_vif_component_cable_svid_mode_list(FILE *vif_file, - const struct vif_cableSVIDList_t *svid_list, int level) +static void vif_output_vif_component_cable_svid_mode_list( + FILE *vif_file, const struct vif_cableSVIDList_t *svid_list, int level) { int index; @@ -939,22 +915,22 @@ static void vif_output_vif_component_cable_svid_mode_list(FILE *vif_file, vif_out_start(vif_file, level++, "CableSVIDModeList"); for (index = 0; index < MAX_NUM_CABLE_SVID_MODES; ++index) { const struct vif_cableSVIDModeList_t *mode_list = - &svid_list->CableSVIDModeList[index]; + &svid_list->CableSVIDModeList[index]; if (!vif_fields_present(mode_list->vif_field, CableSVID_Mode_Indexes)) break; vif_out_start(vif_file, level++, "SOPSVIDMode"); - vif_out_fields(vif_file, level, - mode_list->vif_field, CableSVID_Mode_Indexes); + vif_out_fields(vif_file, level, mode_list->vif_field, + CableSVID_Mode_Indexes); vif_out_end(vif_file, --level, "SOPSVIDMode"); } vif_out_end(vif_file, --level, "CableSVIDModeList"); } -static void vif_output_vif_component_cable_svid_list(FILE *vif_file, - const struct vif_Component_t *component, int level) +static void vif_output_vif_component_cable_svid_list( + FILE *vif_file, const struct vif_Component_t *component, int level) { int index; @@ -965,24 +941,24 @@ static void vif_output_vif_component_cable_svid_list(FILE *vif_file, vif_out_start(vif_file, level++, "CableSVIDList"); for (index = 0; index < MAX_NUM_CABLE_SVIDS; ++index) { const struct vif_cableSVIDList_t *svid_list = - &component->CableSVIDList[index]; + &component->CableSVIDList[index]; if (!vif_fields_present(svid_list->vif_field, CableSVID_Indexes)) break; vif_out_start(vif_file, level++, "CableSVID"); - vif_out_fields(vif_file, level, - svid_list->vif_field, CableSVID_Indexes); + vif_out_fields(vif_file, level, svid_list->vif_field, + CableSVID_Indexes); vif_output_vif_component_cable_svid_mode_list(vif_file, - svid_list, level); + svid_list, level); vif_out_end(vif_file, --level, "CableSVID"); } vif_out_end(vif_file, --level, "CableSVIDList"); } -static void vif_output_vif_component_sop_svid_mode_list(FILE *vif_file, - const struct vif_sopSVIDList_t *svid_list, int level) +static void vif_output_vif_component_sop_svid_mode_list( + FILE *vif_file, const struct vif_sopSVIDList_t *svid_list, int level) { int index; @@ -993,22 +969,22 @@ static void vif_output_vif_component_sop_svid_mode_list(FILE *vif_file, vif_out_start(vif_file, level++, "SOPSVIDModeList"); for (index = 0; index < MAX_NUM_SOP_SVID_MODES; ++index) { const struct vif_sopSVIDModeList_t *mode_list = - &svid_list->SOPSVIDModeList[index]; + &svid_list->SOPSVIDModeList[index]; if (!vif_fields_present(mode_list->vif_field, SopSVID_Mode_Indexes)) break; vif_out_start(vif_file, level++, "SOPSVIDMode"); - vif_out_fields(vif_file, level, - mode_list->vif_field, SopSVID_Mode_Indexes); + vif_out_fields(vif_file, level, mode_list->vif_field, + SopSVID_Mode_Indexes); vif_out_end(vif_file, --level, "SOPSVIDMode"); } vif_out_end(vif_file, --level, "SOPSVIDModeList"); } -static void vif_output_vif_component_sop_svid_list(FILE *vif_file, - const struct vif_Component_t *component, int level) +static void vif_output_vif_component_sop_svid_list( + FILE *vif_file, const struct vif_Component_t *component, int level) { int index; @@ -1019,24 +995,23 @@ static void vif_output_vif_component_sop_svid_list(FILE *vif_file, vif_out_start(vif_file, level++, "SOPSVIDList"); for (index = 0; index < MAX_NUM_SOP_SVIDS; ++index) { const struct vif_sopSVIDList_t *svid_list = - &component->SOPSVIDList[index]; + &component->SOPSVIDList[index]; - if (!vif_fields_present(svid_list->vif_field, - SopSVID_Indexes)) + if (!vif_fields_present(svid_list->vif_field, SopSVID_Indexes)) break; vif_out_start(vif_file, level++, "SOPSVID"); - vif_out_fields(vif_file, level, - svid_list->vif_field, SopSVID_Indexes); - vif_output_vif_component_sop_svid_mode_list(vif_file, - svid_list, level); + vif_out_fields(vif_file, level, svid_list->vif_field, + SopSVID_Indexes); + vif_output_vif_component_sop_svid_mode_list(vif_file, svid_list, + level); vif_out_end(vif_file, --level, "SOPSVID"); } vif_out_end(vif_file, --level, "SOPSVIDList"); } -static void vif_output_vif_component_snk_pdo_list(FILE *vif_file, - const struct vif_Component_t *component, int level) +static void vif_output_vif_component_snk_pdo_list( + FILE *vif_file, const struct vif_Component_t *component, int level) { int index; @@ -1048,23 +1023,22 @@ static void vif_output_vif_component_snk_pdo_list(FILE *vif_file, vif_out_start(vif_file, level++, "SnkPdoList"); for (index = 0; index < MAX_NUM_SNK_PDOS; ++index) { const struct vif_snkPdoList_t *pdo_list = - &component->SnkPdoList[index]; + &component->SnkPdoList[index]; - if (!vif_fields_present(pdo_list->vif_field, - Snk_PDO_Indexes)) + if (!vif_fields_present(pdo_list->vif_field, Snk_PDO_Indexes)) break; vif_out_start(vif_file, level++, "SnkPDO"); vif_out_comment(vif_file, level, "Sink PDO %d", index + 1); - vif_out_fields(vif_file, level, - pdo_list->vif_field, Snk_PDO_Indexes); + vif_out_fields(vif_file, level, pdo_list->vif_field, + Snk_PDO_Indexes); vif_out_end(vif_file, --level, "SnkPDO"); } vif_out_end(vif_file, --level, "SnkPdoList"); } -static void vif_output_vif_component_src_pdo_list(FILE *vif_file, - const struct vif_Component_t *component, int level) +static void vif_output_vif_component_src_pdo_list( + FILE *vif_file, const struct vif_Component_t *component, int level) { int index; @@ -1076,23 +1050,22 @@ static void vif_output_vif_component_src_pdo_list(FILE *vif_file, vif_out_start(vif_file, level++, "SrcPdoList"); for (index = 0; index < MAX_NUM_SRC_PDOS; ++index) { const struct vif_srcPdoList_t *pdo_list = - &component->SrcPdoList[index]; + &component->SrcPdoList[index]; - if (!vif_fields_present(pdo_list->vif_field, - Src_PDO_Indexes)) + if (!vif_fields_present(pdo_list->vif_field, Src_PDO_Indexes)) break; vif_out_start(vif_file, level++, "SrcPDO"); vif_out_comment(vif_file, level, "Source PDO %d", index + 1); - vif_out_fields(vif_file, level, - pdo_list->vif_field, Src_PDO_Indexes); + vif_out_fields(vif_file, level, pdo_list->vif_field, + Src_PDO_Indexes); vif_out_end(vif_file, --level, "SrcPDO"); } vif_out_end(vif_file, --level, "SrcPdoList"); } -static void vif_output_vif_component(FILE *vif_file, - const struct vif_t *vif, int level) +static void vif_output_vif_component(FILE *vif_file, const struct vif_t *vif, + int level) { int index; @@ -1106,26 +1079,23 @@ static void vif_output_vif_component(FILE *vif_file, vif_out_start(vif_file, level++, "Component"); vif_out_comment(vif_file, level, "Component %d", index); - vif_out_fields(vif_file, level, - component->vif_field, Component_Indexes); - vif_output_vif_component_snk_pdo_list(vif_file, - component, - level); - vif_output_vif_component_src_pdo_list(vif_file, - component, - level); - vif_output_vif_component_sop_svid_list(vif_file, - component, - level); - vif_output_vif_component_cable_svid_list(vif_file, - component, - level); + vif_out_fields(vif_file, level, component->vif_field, + Component_Indexes); + vif_output_vif_component_snk_pdo_list(vif_file, component, + level); + vif_output_vif_component_src_pdo_list(vif_file, component, + level); + vif_output_vif_component_sop_svid_list(vif_file, component, + level); + vif_output_vif_component_cable_svid_list(vif_file, component, + level); vif_out_end(vif_file, --level, "Component"); } } -static void vif_output_vif_product_usb4router_endpoint(FILE *vif_file, - const struct vif_Usb4RouterListType_t *router, int level) +static void vif_output_vif_product_usb4router_endpoint( + FILE *vif_file, const struct vif_Usb4RouterListType_t *router, + int level) { int index; @@ -1136,22 +1106,23 @@ static void vif_output_vif_product_usb4router_endpoint(FILE *vif_file, vif_out_start(vif_file, level++, "PCIeEndpointList"); for (index = 0; index < MAX_NUM_PCIE_ENDPOINTS; ++index) { const struct vif_PCIeEndpointListType_t *endpont = - &router->PCIeEndpointList[index]; + &router->PCIeEndpointList[index]; if (!vif_fields_present(endpont->vif_field, PCIe_Endpoint_Indexes)) break; vif_out_start(vif_file, level++, "PCIeEndpoint"); - vif_out_fields(vif_file, level, - endpont->vif_field, PCIe_Endpoint_Indexes); + vif_out_fields(vif_file, level, endpont->vif_field, + PCIe_Endpoint_Indexes); vif_out_end(vif_file, --level, "PCIeEndpoint"); } vif_out_end(vif_file, --level, "PCIeEndpointList"); } static void vif_output_vif_product_usb4router(FILE *vif_file, - const struct vif_t *vif, int level) + const struct vif_t *vif, + int level) { int index; @@ -1163,34 +1134,32 @@ static void vif_output_vif_product_usb4router(FILE *vif_file, vif_out_start(vif_file, level++, "USB4RouterList"); for (index = 0; index < MAX_NUM_USB4_ROUTERS; ++index) { const struct vif_Usb4RouterListType_t *router = - &vif->Product.USB4RouterList[index]; + &vif->Product.USB4RouterList[index]; - if (!vif_fields_present(router->vif_field, - USB4_Router_Indexes)) + if (!vif_fields_present(router->vif_field, USB4_Router_Indexes)) break; vif_out_start(vif_file, level++, "Usb4Router"); vif_out_comment(vif_file, level, "USB4 Router %d", index); - vif_out_fields(vif_file, level, - router->vif_field, USB4_Router_Indexes); - vif_output_vif_product_usb4router_endpoint(vif_file, - router, + vif_out_fields(vif_file, level, router->vif_field, + USB4_Router_Indexes); + vif_output_vif_product_usb4router_endpoint(vif_file, router, level); vif_out_end(vif_file, --level, "Usb4Router"); } vif_out_end(vif_file, --level, "USB4RouterList"); } -static void vif_output_vif_product(FILE *vif_file, - const struct vif_t *vif, int level) +static void vif_output_vif_product(FILE *vif_file, const struct vif_t *vif, + int level) { if (!vif_fields_present(vif->Product.vif_field, Product_Indexes)) return; vif_out_start(vif_file, level++, "Product"); vif_out_comment(vif_file, level, "Product Level Content:"); - vif_out_fields(vif_file, level, - vif->Product.vif_field, Product_Indexes); + vif_out_fields(vif_file, level, vif->Product.vif_field, + Product_Indexes); vif_output_vif_product_usb4router(vif_file, vif, level); vif_out_end(vif_file, --level, "Product"); } @@ -1203,8 +1172,8 @@ static void vif_output_vif_xml(FILE *vif_file, struct vif_t *vif, int level) vif_out_fields(vif_file, level, vif->vif_app_field, VIF_App_Indexes); vif_out_end(vif_file, --level, "VIF_App"); - vif_out_fields_range(vif_file, level, - vif->vif_field, Vendor_Name, VIF_Indexes); + vif_out_fields_range(vif_file, level, vif->vif_field, Vendor_Name, + VIF_Indexes); } static int vif_output_xml(const char *name, struct vif_t *vif) @@ -1220,12 +1189,13 @@ static int vif_output_xml(const char *name, struct vif_t *vif) } vif_out_str(vif_file, level, - ""); - vif_out_start(vif_file, level++, + ""); + vif_out_start( + vif_file, level++, "VIF " - "xmlns:opt=\"http://usb.org/VendorInfoFileOptionalContent.xsd\" " - "xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" " - "xmlns:vif=\"http://usb.org/VendorInfoFile.xsd\""); + "xmlns:opt=\"http://usb.org/VendorInfoFileOptionalContent.xsd\" " + "xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" " + "xmlns:vif=\"http://usb.org/VendorInfoFile.xsd\""); vif_output_vif_xml(vif_file, vif, level); vif_output_vif_product(vif_file, vif, level); @@ -1240,7 +1210,6 @@ static int vif_output_xml(const char *name, struct vif_t *vif) * VIF XML Output Functions *****************************************************************************/ - /***************************************************************************** * VIF Structure Override from XML file functions */ @@ -1298,11 +1267,9 @@ static void ov_close(void) override_file = NULL; } - static void set_override_vif_field(struct vif_field_t *vif_field, - const char *name, - const char *tag_value, - const char *str_value) + const char *name, const char *tag_value, + const char *str_value) { char *ptr; @@ -1317,12 +1284,12 @@ static void set_override_vif_field(struct vif_field_t *vif_field, vif_field->name = name; if (tag_value && tag_value[0]) { - ptr = malloc(strlen(tag_value)+1); + ptr = malloc(strlen(tag_value) + 1); strcpy(ptr, tag_value); vif_field->tag_value = ptr; } if (str_value && str_value[0]) { - ptr = malloc(strlen(str_value)+1); + ptr = malloc(strlen(str_value) + 1); strcpy(ptr, str_value); vif_field->str_value = ptr; } @@ -1346,10 +1313,9 @@ static void ignore_comment_tag(void) int ch; while ((ch = ov_getc()) != EOF) { - if (ch == '-') { + if (ch == '-') { ovpre_getc(2); - if (ovpre_peek(0) == '-' && - ovpre_peek(1) == '>') { + if (ovpre_peek(0) == '-' && ovpre_peek(1) == '>') { /* --> */ ovpre_drop(2); break; @@ -1388,9 +1354,7 @@ static void ignore_to_end_tag(void) * * next call returns */ -static bool get_next_tag(char *name, - char *tag_value, - char *str_value) +static bool get_next_tag(char *name, char *tag_value, char *str_value) { int ch; int name_index = 0; @@ -1422,8 +1386,7 @@ static bool get_next_tag(char *name, * Ignore XML comment */ ovpre_getc(3); - if (ovpre_peek(0) == '!' && - ovpre_peek(1) == '-' && + if (ovpre_peek(0) == '!' && ovpre_peek(1) == '-' && ovpre_peek(2) == '-') { ovpre_drop(3); ignore_comment_tag(); @@ -1444,8 +1407,8 @@ static bool get_next_tag(char *name, /* Looking for a tag name */ while ((ch = ov_getc()) != EOF) { - if (ch == '_' || ch == ':' || - isalpha(ch) || isdigit(ch)) { + if (ch == '_' || ch == ':' || isalpha(ch) || + isdigit(ch)) { name[name_index++] = ch; } else { ov_pushback(ch); @@ -1459,12 +1422,9 @@ static bool get_next_tag(char *name, /* See if there is a tag_string value */ ovpre_getc(7); - if (ovpre_peek(0) == 'v' && - ovpre_peek(1) == 'a' && - ovpre_peek(2) == 'l' && - ovpre_peek(3) == 'u' && - ovpre_peek(4) == 'e' && - ovpre_peek(5) == '=' && + if (ovpre_peek(0) == 'v' && ovpre_peek(1) == 'a' && + ovpre_peek(2) == 'l' && ovpre_peek(3) == 'u' && + ovpre_peek(4) == 'e' && ovpre_peek(5) == '=' && ovpre_peek(6) == '"') { ovpre_drop(7); while ((ch = ov_getc()) != EOF) { @@ -1480,8 +1440,7 @@ static bool get_next_tag(char *name, /* /> ending the tag will conclude this tag */ ovpre_getc(2); - if (ovpre_peek(0) == '/' && - ovpre_peek(1) == '>') { + if (ovpre_peek(0) == '/' && ovpre_peek(1) == '>') { ovpre_drop(2); return true; } @@ -1510,7 +1469,7 @@ static bool get_next_tag(char *name, } static void override_vif_product_pcie_endpoint_field( - struct vif_PCIeEndpointListType_t *endpoint) + struct vif_PCIeEndpointListType_t *endpoint) { char name[80]; char tag_value[80]; @@ -1528,17 +1487,17 @@ static void override_vif_product_pcie_endpoint_field( if (i != PCIe_Endpoint_Indexes) set_override_vif_field( &endpoint->vif_field[i], - vif_product_pcie_endpoint_name[i], - tag_value, + vif_product_pcie_endpoint_name[i], tag_value, str_value); else fprintf(stderr, "VIF/Component/Usb4Router/PCIeEndpoint:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_product_pcie_endpoint_list_field( - struct vif_PCIeEndpointListType_t *endpoint_list) + struct vif_PCIeEndpointListType_t *endpoint_list) { char name[80]; char tag_value[80]; @@ -1551,16 +1510,17 @@ static void override_vif_product_pcie_endpoint_list_field( if (is_start_tag(name, "PCIeEndpoint")) override_vif_product_pcie_endpoint_field( - &endpoint_list[endpoint_index++]); + &endpoint_list[endpoint_index++]); else fprintf(stderr, "VIF/Product/Usb4Router/PCIeEndpointList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } -static void override_vif_product_usb4router_fields( - struct vif_Usb4RouterListType_t *router) +static void +override_vif_product_usb4router_fields(struct vif_Usb4RouterListType_t *router) { char name[80]; char tag_value[80]; @@ -1585,17 +1545,17 @@ static void override_vif_product_usb4router_fields( set_override_vif_field( &router->vif_field[i], vif_product_usb4_router_name[i], - tag_value, - str_value); + tag_value, str_value); else fprintf(stderr, "VIF/Component/Usb4Router:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } } static void override_vif_product_usb4routerlist_fields( - struct vif_Usb4RouterListType_t *router_list) + struct vif_Usb4RouterListType_t *router_list) { char name[80]; char tag_value[80]; @@ -1612,7 +1572,8 @@ static void override_vif_product_usb4routerlist_fields( else fprintf(stderr, "VIF/Product/USB4RouterList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } @@ -1641,19 +1602,19 @@ static void override_vif_product_fields(struct vif_Product_t *vif_product) if (i != Product_Indexes) set_override_vif_field( &vif_product->vif_field[i], - vif_product_name[i], - tag_value, + vif_product_name[i], tag_value, str_value); else fprintf(stderr, "VIF/Product:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } } -static void override_vif_component_src_pdo_fields( - struct vif_srcPdoList_t *vif_src_pdo) +static void +override_vif_component_src_pdo_fields(struct vif_srcPdoList_t *vif_src_pdo) { char name[80]; char tag_value[80]; @@ -1669,19 +1630,18 @@ static void override_vif_component_src_pdo_fields( if (streq(name, vif_component_src_pdo_name[i])) break; if (i != Src_PDO_Indexes) - set_override_vif_field( - &vif_src_pdo->vif_field[i], - vif_component_src_pdo_name[i], - tag_value, - str_value); + set_override_vif_field(&vif_src_pdo->vif_field[i], + vif_component_src_pdo_name[i], + tag_value, str_value); else fprintf(stderr, "VIF/Component/SrcPdo:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_src_pdo_list_fields( - struct vif_srcPdoList_t *vif_src_pdo_list) + struct vif_srcPdoList_t *vif_src_pdo_list) { char name[80]; char tag_value[80]; @@ -1698,12 +1658,13 @@ static void override_vif_component_src_pdo_list_fields( else fprintf(stderr, "VIF/Component/SrcPdoList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } -static void override_vif_component_snk_pdo_fields( - struct vif_snkPdoList_t *vif_snk_pdo) +static void +override_vif_component_snk_pdo_fields(struct vif_snkPdoList_t *vif_snk_pdo) { char name[80]; char tag_value[80]; @@ -1719,19 +1680,18 @@ static void override_vif_component_snk_pdo_fields( if (streq(name, vif_component_snk_pdo_name[i])) break; if (i != Snk_PDO_Indexes) - set_override_vif_field( - &vif_snk_pdo->vif_field[i], - vif_component_snk_pdo_name[i], - tag_value, - str_value); + set_override_vif_field(&vif_snk_pdo->vif_field[i], + vif_component_snk_pdo_name[i], + tag_value, str_value); else fprintf(stderr, "VIF/Component/SnkPdo:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_snk_pdo_list_fields( - struct vif_snkPdoList_t *vif_snk_pdo_list) + struct vif_snkPdoList_t *vif_snk_pdo_list) { char name[80]; char tag_value[80]; @@ -1748,12 +1708,13 @@ static void override_vif_component_snk_pdo_list_fields( else fprintf(stderr, "VIF/Component/SnkPdoList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_sop_svid_mode_fields( - struct vif_sopSVIDModeList_t *svid_mode) + struct vif_sopSVIDModeList_t *svid_mode) { char name[80]; char tag_value[80]; @@ -1771,17 +1732,17 @@ static void override_vif_component_sop_svid_mode_fields( if (i != SopSVID_Indexes) set_override_vif_field( &svid_mode->vif_field[i], - vif_component_sop_svid_mode_name[i], - tag_value, + vif_component_sop_svid_mode_name[i], tag_value, str_value); else fprintf(stderr, "VIF/Component/SOPSVIDMode:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_sop_svid_mode_list_fields( - struct vif_sopSVIDModeList_t *svid_mode_list) + struct vif_sopSVIDModeList_t *svid_mode_list) { char name[80]; char tag_value[80]; @@ -1798,12 +1759,13 @@ static void override_vif_component_sop_svid_mode_list_fields( else fprintf(stderr, "VIF/Component/SOPSVIDModeList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } -static void override_vif_component_sop_svid_fields( - struct vif_sopSVIDList_t *vif_sop_svid) +static void +override_vif_component_sop_svid_fields(struct vif_sopSVIDList_t *vif_sop_svid) { char name[80]; char tag_value[80]; @@ -1820,24 +1782,23 @@ static void override_vif_component_sop_svid_fields( int i; for (i = 0; i < SopSVID_Indexes; i++) - if (streq(name, - vif_component_sop_svid_name[i])) + if (streq(name, vif_component_sop_svid_name[i])) break; if (i != SopSVID_Indexes) set_override_vif_field( &vif_sop_svid->vif_field[i], vif_component_sop_svid_name[i], - tag_value, - str_value); + tag_value, str_value); else fprintf(stderr, "VIF/Component/SOPSVID:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } } static void override_vif_component_sop_svid_list_fields( - struct vif_sopSVIDList_t *vif_sop_svid_list) + struct vif_sopSVIDList_t *vif_sop_svid_list) { char name[80]; char tag_value[80]; @@ -1854,12 +1815,13 @@ static void override_vif_component_sop_svid_list_fields( else fprintf(stderr, "VIF/Component/SOPSVIDList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_cable_svid_mode_fields( - struct vif_cableSVIDModeList_t *vif_cable_mode) + struct vif_cableSVIDModeList_t *vif_cable_mode) { char name[80]; char tag_value[80]; @@ -1875,19 +1837,18 @@ static void override_vif_component_cable_svid_mode_fields( if (streq(name, vif_cable_mode_name[i])) break; if (i != CableSVID_Mode_Indexes) - set_override_vif_field( - &vif_cable_mode->vif_field[i], - vif_cable_mode_name[i], - tag_value, - str_value); + set_override_vif_field(&vif_cable_mode->vif_field[i], + vif_cable_mode_name[i], + tag_value, str_value); else fprintf(stderr, "VIF/Component/CableSVIDMode:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_cable_svid_mode_list_fields( - struct vif_cableSVIDModeList_t *vif_cable_mode_list) + struct vif_cableSVIDModeList_t *vif_cable_mode_list) { char name[80]; char tag_value[80]; @@ -1904,12 +1865,13 @@ static void override_vif_component_cable_svid_mode_list_fields( else fprintf(stderr, "VIF/Component/CableSVIDModeList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } static void override_vif_component_cable_svid_fields( - struct vif_cableSVIDList_t *vif_cable_svid) + struct vif_cableSVIDList_t *vif_cable_svid) { char name[80]; char tag_value[80]; @@ -1922,8 +1884,8 @@ static void override_vif_component_cable_svid_fields( if (is_start_tag(name, "CableSVIDModeList")) override_vif_component_cable_svid_mode_list_fields( - &vif_cable_svid->CableSVIDModeList[ - mode_index++]); + &vif_cable_svid + ->CableSVIDModeList[mode_index++]); else { int i; @@ -1933,18 +1895,18 @@ static void override_vif_component_cable_svid_fields( if (i != CableSVID_Indexes) set_override_vif_field( &vif_cable_svid->vif_field[i], - vif_cable_svid_name[i], - tag_value, + vif_cable_svid_name[i], tag_value, str_value); else fprintf(stderr, "VIF/Component/CableSVID:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } } static void override_vif_component_cable_svid_list_fields( - struct vif_cableSVIDList_t *vif_cable_svid_list) + struct vif_cableSVIDList_t *vif_cable_svid_list) { char name[80]; char tag_value[80]; @@ -1961,12 +1923,12 @@ static void override_vif_component_cable_svid_list_fields( else fprintf(stderr, "VIF/Component/CableSVIDList:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } -static void override_vif_component_fields( - struct vif_Component_t *vif_component) +static void override_vif_component_fields(struct vif_Component_t *vif_component) { char name[80]; char tag_value[80]; @@ -1978,16 +1940,16 @@ static void override_vif_component_fields( if (is_start_tag(name, "SrcPdoList")) override_vif_component_src_pdo_list_fields( - vif_component->SrcPdoList); + vif_component->SrcPdoList); else if (is_start_tag(name, "SnkPdoList")) override_vif_component_snk_pdo_list_fields( - vif_component->SnkPdoList); + vif_component->SnkPdoList); else if (is_start_tag(name, "SOPSVIDList")) override_vif_component_sop_svid_list_fields( - vif_component->SOPSVIDList); + vif_component->SOPSVIDList); else if (is_start_tag(name, "CableSVIDList")) override_vif_component_cable_svid_list_fields( - vif_component->CableSVIDList); + vif_component->CableSVIDList); else { int i; @@ -1996,14 +1958,14 @@ static void override_vif_component_fields( break; if (i != Component_Indexes) set_override_vif_field( - &vif_component->vif_field[i], - vif_component_name[i], - tag_value, - str_value); + &vif_component->vif_field[i], + vif_component_name[i], tag_value, + str_value); else fprintf(stderr, "VIF/Component:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } } @@ -2026,7 +1988,8 @@ static void override_vif_app_fields(struct vif_t *vif) if (i == VIF_App_Indexes) fprintf(stderr, "VIF/VIF_App:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } @@ -2055,15 +2018,14 @@ static void override_vif_fields(struct vif_t *vif) if (streq(name, vif_name[i])) break; if (i != VIF_Indexes) - set_override_vif_field( - &vif->vif_field[i], - vif_name[i], - tag_value, - str_value); + set_override_vif_field(&vif->vif_field[i], + vif_name[i], tag_value, + str_value); else fprintf(stderr, "VIF:" - " Unknown tag '%s'\n", name); + " Unknown tag '%s'\n", + name); } } @@ -2072,19 +2034,15 @@ static void override_vif_fields(struct vif_t *vif) * means VIF/VIF_App is to be set by me. */ set_override_vif_field(&vif->vif_app_field[Vendor], - vif_app_name[Vendor], - NULL, - VIF_APP_VENDOR_VALUE); + vif_app_name[Vendor], NULL, + VIF_APP_VENDOR_VALUE); - set_override_vif_field(&vif->vif_app_field[Name], - vif_app_name[Name], - NULL, - VIF_APP_NAME_VALUE); + set_override_vif_field(&vif->vif_app_field[Name], vif_app_name[Name], + NULL, VIF_APP_NAME_VALUE); set_override_vif_field(&vif->vif_app_field[Version], - vif_app_name[Version], - NULL, - VIF_APP_VERSION_VALUE); + vif_app_name[Version], NULL, + VIF_APP_VERSION_VALUE); } static int override_gen_vif(char *over_name, struct vif_t *vif) @@ -2103,8 +2061,7 @@ static int override_gen_vif(char *over_name, struct vif_t *vif) if (is_start_tag(name, "VIF")) override_vif_fields(vif); else - fprintf(stderr, - "Unknown tag '%s'\n", name); + fprintf(stderr, "Unknown tag '%s'\n", name); } ov_close(); @@ -2114,14 +2071,11 @@ static int override_gen_vif(char *over_name, struct vif_t *vif) * VIF Structure Override from XML file functions *****************************************************************************/ - /***************************************************************************** * VIF Structure Initialization Helper Functions */ -static void set_vif_field(struct vif_field_t *vif_field, - const char *name, - const char *tag_value, - const char *str_value) +static void set_vif_field(struct vif_field_t *vif_field, const char *name, + const char *tag_value, const char *str_value) { char *ptr; @@ -2135,19 +2089,18 @@ static void set_vif_field(struct vif_field_t *vif_field, vif_field->name = name; if (tag_value) { - ptr = malloc(strlen(tag_value)+1); + ptr = malloc(strlen(tag_value) + 1); strcpy(ptr, tag_value); vif_field->tag_value = ptr; } if (str_value) { - ptr = malloc(strlen(str_value)+1); + ptr = malloc(strlen(str_value) + 1); strcpy(ptr, str_value); vif_field->str_value = ptr; } } __maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field, - const char *name, - const bool val) + const char *name, const bool val) { if (val) set_vif_field(vif_field, name, "true", NULL); @@ -2155,9 +2108,9 @@ __maybe_unused static void set_vif_field_b(struct vif_field_t *vif_field, set_vif_field(vif_field, name, "false", NULL); } __maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field, - const char *name, - const char *tag_value, - const int str_value) + const char *name, + const char *tag_value, + const int str_value) { char str_str[20]; @@ -2165,9 +2118,9 @@ __maybe_unused static void set_vif_field_stis(struct vif_field_t *vif_field, set_vif_field(vif_field, name, tag_value, str_str); } __maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field, - const char *name, - const int tag_value, - const char *str_value) + const char *name, + const int tag_value, + const char *str_value) { char str_tag[20]; @@ -2175,9 +2128,9 @@ __maybe_unused static void set_vif_field_itss(struct vif_field_t *vif_field, set_vif_field(vif_field, name, str_tag, str_value); } __maybe_unused static void set_vif_field_itis(struct vif_field_t *vif_field, - const char *name, - const int tag_value, - const int str_value) + const char *name, + const int tag_value, + const int str_value) { char str_tag[20]; char str_str[20]; @@ -2369,16 +2322,17 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo, power_mw = (current_ma * voltage_mv) / 1000; set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type], - vif_component_snk_pdo_name[Snk_PDO_Supply_Type], - "0", "Fixed"); + vif_component_snk_pdo_name[Snk_PDO_Supply_Type], + "0", "Fixed"); sprintf(str, "%d mV", voltage_mv); set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Voltage], - vif_component_snk_pdo_name[Snk_PDO_Voltage], - voltage, str); + vif_component_snk_pdo_name[Snk_PDO_Voltage], + voltage, str); sprintf(str, "%d mA", current_ma); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current], - vif_component_snk_pdo_name[Snk_PDO_Op_Current], - current, str); + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Op_Current], + vif_component_snk_pdo_name[Snk_PDO_Op_Current], current, + str); } else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) { uint32_t max_voltage = (pdo >> 20) & 0x3ff; @@ -2391,20 +2345,22 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo, power_mw = power * 250; set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type], - vif_component_snk_pdo_name[Snk_PDO_Supply_Type], - "1", "Battery"); + vif_component_snk_pdo_name[Snk_PDO_Supply_Type], + "1", "Battery"); sprintf(str, "%d mV", min_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Min_Voltage], vif_component_snk_pdo_name[Snk_PDO_Min_Voltage], min_voltage, str); sprintf(str, "%d mV", max_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Max_Voltage], vif_component_snk_pdo_name[Snk_PDO_Max_Voltage], max_voltage, str); sprintf(str, "%d mW", power_mw); set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Power], - vif_component_snk_pdo_name[Snk_PDO_Op_Power], - power, str); + vif_component_snk_pdo_name[Snk_PDO_Op_Power], + power, str); } else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) { uint32_t max_voltage = (pdo >> 20) & 0x3ff; @@ -2417,20 +2373,23 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo, power_mw = (current_ma * max_voltage_mv) / 1000; set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type], - vif_component_snk_pdo_name[Snk_PDO_Supply_Type], - "2", "Variable"); + vif_component_snk_pdo_name[Snk_PDO_Supply_Type], + "2", "Variable"); sprintf(str, "%d mV", min_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Min_Voltage], vif_component_snk_pdo_name[Snk_PDO_Min_Voltage], min_voltage, str); sprintf(str, "%d mV", max_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Max_Voltage], vif_component_snk_pdo_name[Snk_PDO_Max_Voltage], max_voltage, str); sprintf(str, "%d mA", current_ma); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current], - vif_component_snk_pdo_name[Snk_PDO_Op_Current], - current, str); + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Op_Current], + vif_component_snk_pdo_name[Snk_PDO_Op_Current], current, + str); } else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_AUGMENTED) { uint32_t pps = (pdo >> 28) & 3; @@ -2449,18 +2408,21 @@ __maybe_unused static int32_t init_vif_snk_pdo(struct vif_snkPdoList_t *snkPdo, power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000; set_vif_field(&snkPdo->vif_field[Snk_PDO_Supply_Type], - vif_component_snk_pdo_name[Snk_PDO_Supply_Type], - "3", "PPS"); + vif_component_snk_pdo_name[Snk_PDO_Supply_Type], + "3", "PPS"); sprintf(str, "%d mA", pps_current_ma); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Op_Current], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Op_Current], vif_component_snk_pdo_name[Snk_PDO_Op_Current], pps_current, str); sprintf(str, "%d mV", pps_min_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Min_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Min_Voltage], vif_component_snk_pdo_name[Snk_PDO_Min_Voltage], pps_min_voltage, str); sprintf(str, "%d mV", pps_max_voltage_mv); - set_vif_field_itss(&snkPdo->vif_field[Snk_PDO_Max_Voltage], + set_vif_field_itss( + &snkPdo->vif_field[Snk_PDO_Max_Voltage], vif_component_snk_pdo_name[Snk_PDO_Max_Voltage], pps_max_voltage, str); } else { @@ -2501,17 +2463,18 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo, power_mw = (current_ma * voltage_mv) / 1000; set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type], - vif_component_src_pdo_name[Src_PDO_Supply_Type], - "0", "Fixed"); + vif_component_src_pdo_name[Src_PDO_Supply_Type], + "0", "Fixed"); set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current], - vif_component_src_pdo_name[Src_PDO_Peak_Current], - "0", "100% IOC"); + vif_component_src_pdo_name[Src_PDO_Peak_Current], + "0", "100% IOC"); sprintf(str, "%d mV", voltage_mv); set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Voltage], - vif_component_src_pdo_name[Src_PDO_Voltage], - voltage, str); + vif_component_src_pdo_name[Src_PDO_Voltage], + voltage, str); sprintf(str, "%d mA", current_ma); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Current], vif_component_src_pdo_name[Src_PDO_Max_Current], current, str); @@ -2526,20 +2489,23 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo, power_mw = power * 250; set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type], - vif_component_src_pdo_name[Src_PDO_Supply_Type], - "1", "Battery"); + vif_component_src_pdo_name[Src_PDO_Supply_Type], + "1", "Battery"); sprintf(str, "%d mV", min_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Min_Voltage], vif_component_src_pdo_name[Src_PDO_Min_Voltage], min_voltage, str); sprintf(str, "%d mV", max_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Voltage], vif_component_src_pdo_name[Src_PDO_Max_Voltage], max_voltage, str); sprintf(str, "%d mW", power_mw); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Power], - vif_component_src_pdo_name[Src_PDO_Max_Power], - power, str); + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Power], + vif_component_src_pdo_name[Src_PDO_Max_Power], power, + str); } else if ((pdo & PDO_TYPE_MASK) == PDO_TYPE_VARIABLE) { uint32_t max_voltage = (pdo >> 20) & 0x3ff; @@ -2552,21 +2518,24 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo, power_mw = (current_ma * max_voltage_mv) / 1000; set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type], - vif_component_src_pdo_name[Src_PDO_Supply_Type], - "2", "Variable"); + vif_component_src_pdo_name[Src_PDO_Supply_Type], + "2", "Variable"); set_vif_field(&srcPdo->vif_field[Src_PDO_Peak_Current], - vif_component_src_pdo_name[Src_PDO_Peak_Current], - "0", "100% IOC"); + vif_component_src_pdo_name[Src_PDO_Peak_Current], + "0", "100% IOC"); sprintf(str, "%d mV", min_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Min_Voltage], vif_component_src_pdo_name[Src_PDO_Min_Voltage], min_voltage, str); sprintf(str, "%d mV", max_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Voltage], vif_component_src_pdo_name[Src_PDO_Max_Voltage], max_voltage, str); sprintf(str, "%d mA", current_ma); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Current], vif_component_src_pdo_name[Src_PDO_Max_Current], current, str); @@ -2587,18 +2556,21 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo, power_mw = (pps_current_ma * pps_max_voltage_mv) / 1000; set_vif_field(&srcPdo->vif_field[Src_PDO_Supply_Type], - vif_component_src_pdo_name[Src_PDO_Supply_Type], - "3", "PPS"); + vif_component_src_pdo_name[Src_PDO_Supply_Type], + "3", "PPS"); sprintf(str, "%d mA", pps_current_ma); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Current], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Current], vif_component_src_pdo_name[Src_PDO_Max_Current], pps_current, str); sprintf(str, "%d mV", pps_min_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Min_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Min_Voltage], vif_component_src_pdo_name[Src_PDO_Min_Voltage], pps_min_voltage, str); sprintf(str, "%d mV", pps_max_voltage_mv); - set_vif_field_itss(&srcPdo->vif_field[Src_PDO_Max_Voltage], + set_vif_field_itss( + &srcPdo->vif_field[Src_PDO_Max_Voltage], vif_component_src_pdo_name[Src_PDO_Max_Voltage], pps_max_voltage, str); @@ -2614,157 +2586,120 @@ __maybe_unused static int32_t init_vif_src_pdo(struct vif_srcPdoList_t *srcPdo, * Init VIF Fields */ static void init_vif_fields(struct vif_field_t *vif_fields, - struct vif_field_t *vif_app_fields, - const char *board) + struct vif_field_t *vif_app_fields, + const char *board) { set_vif_field(&vif_fields[VIF_Specification], - vif_name[VIF_Specification], - NULL, - "3.18"); - - set_vif_field(&vif_app_fields[Vendor], - vif_app_name[Vendor], - NULL, - VIF_APP_VENDOR_VALUE); - - set_vif_field(&vif_app_fields[Name], - vif_app_name[Name], - NULL, - VIF_APP_NAME_VALUE); - - set_vif_field(&vif_app_fields[Version], - vif_app_name[Version], - NULL, - VIF_APP_VERSION_VALUE); - - set_vif_field(&vif_fields[Vendor_Name], - vif_name[Vendor_Name], - NULL, - VENDOR_NAME_VALUE); - - #if defined(CONFIG_USB_PD_MODEL_PART_NUMBER) + vif_name[VIF_Specification], NULL, "3.18"); + + set_vif_field(&vif_app_fields[Vendor], vif_app_name[Vendor], NULL, + VIF_APP_VENDOR_VALUE); + + set_vif_field(&vif_app_fields[Name], vif_app_name[Name], NULL, + VIF_APP_NAME_VALUE); + + set_vif_field(&vif_app_fields[Version], vif_app_name[Version], NULL, + VIF_APP_VERSION_VALUE); + + set_vif_field(&vif_fields[Vendor_Name], vif_name[Vendor_Name], NULL, + VENDOR_NAME_VALUE); + +#if defined(CONFIG_USB_PD_MODEL_PART_NUMBER) + set_vif_field(&vif_fields[Model_Part_Number], + vif_name[Model_Part_Number], NULL, + CONFIG_USB_PD_MODEL_PART_NUMBER); +#else + if (board && strlen(board) > 0) set_vif_field(&vif_fields[Model_Part_Number], - vif_name[Model_Part_Number], - NULL, - CONFIG_USB_PD_MODEL_PART_NUMBER); - #else - if (board && strlen(board) > 0) - set_vif_field(&vif_fields[Model_Part_Number], - vif_name[Model_Part_Number], - NULL, - board); - else - set_vif_field(&vif_fields[Model_Part_Number], - vif_name[Model_Part_Number], - NULL, - "FIX-ME"); - #endif - - #if defined(CONFIG_USB_PD_PRODUCT_REVISION) - set_vif_field(&vif_fields[Product_Revision], - vif_name[Product_Revision], - NULL, - CONFIG_USB_PD_PRODUCT_REVISION); - #else - set_vif_field(&vif_fields[Product_Revision], - vif_name[Product_Revision], - NULL, - "FIX-ME"); - #endif - - #if defined(CONFIG_USB_PD_TID) - set_vif_field_stis(&vif_fields[TID], - vif_name[TID], - NULL, - CONFIG_USB_PD_TID); - #else - set_vif_field_stis(&vif_fields[TID], - vif_name[TID], - NULL, - DEFAULT_MISSING_TID); - #endif - - set_vif_field(&vif_fields[VIF_Product_Type], - vif_name[VIF_Product_Type], - "0", - "Port Product"); + vif_name[Model_Part_Number], NULL, board); + else + set_vif_field(&vif_fields[Model_Part_Number], + vif_name[Model_Part_Number], NULL, "FIX-ME"); +#endif + +#if defined(CONFIG_USB_PD_PRODUCT_REVISION) + set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision], + NULL, CONFIG_USB_PD_PRODUCT_REVISION); +#else + set_vif_field(&vif_fields[Product_Revision], vif_name[Product_Revision], + NULL, "FIX-ME"); +#endif + +#if defined(CONFIG_USB_PD_TID) + set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL, + CONFIG_USB_PD_TID); +#else + set_vif_field_stis(&vif_fields[TID], vif_name[TID], NULL, + DEFAULT_MISSING_TID); +#endif + + set_vif_field(&vif_fields[VIF_Product_Type], vif_name[VIF_Product_Type], + "0", "Port Product"); set_vif_field(&vif_fields[Certification_Type], - vif_name[Certification_Type], - "0", - "End Product"); + vif_name[Certification_Type], "0", "End Product"); } /********************************************************************* * Init VIF/Component[] Fields */ static void init_vif_component_fields(struct vif_field_t *vif_fields, - enum bc_1_2_support *bc_support, - enum dtype type) -{ - #if defined(CONFIG_USB_PD_PORT_LABEL) - set_vif_field_stis(&vif_fields[Port_Label], - vif_component_name[Port_Label], - NULL, - CONFIG_USB_PD_PORT_LABEL); - #else - set_vif_field_stis(&vif_fields[Port_Label], - vif_component_name[Port_Label], - NULL, - component_index); - #endif + enum bc_1_2_support *bc_support, + enum dtype type) +{ +#if defined(CONFIG_USB_PD_PORT_LABEL) + set_vif_field_stis(&vif_fields[Port_Label], + vif_component_name[Port_Label], NULL, + CONFIG_USB_PD_PORT_LABEL); +#else + set_vif_field_stis(&vif_fields[Port_Label], + vif_component_name[Port_Label], NULL, + component_index); +#endif set_vif_field(&vif_fields[Connector_Type], - vif_component_name[Connector_Type], - "2", - "Type-C®"); + vif_component_name[Connector_Type], "2", "Type-C®"); if (is_usb4_supported()) { int router_index; set_vif_field_b(&vif_fields[USB4_Supported], - vif_component_name[USB4_Supported], - true); + vif_component_name[USB4_Supported], true); if (!get_vif_field_tag_number( - &vif.Product.USB4RouterList[0] - .vif_field[USB4_Router_ID], - &router_index)) { + &vif.Product.USB4RouterList[0] + .vif_field[USB4_Router_ID], + &router_index)) { router_index = 0; } set_vif_field_itss(&vif_fields[USB4_Router_Index], - vif_component_name[USB4_Router_Index], - router_index, - NULL); + vif_component_name[USB4_Router_Index], + router_index, NULL); } else { set_vif_field_b(&vif_fields[USB4_Supported], - vif_component_name[USB4_Supported], - false); + vif_component_name[USB4_Supported], false); } set_vif_field_b(&vif_fields[USB_PD_Support], - vif_component_name[USB_PD_Support], - is_usb_pd_supported()); + vif_component_name[USB_PD_Support], + is_usb_pd_supported()); if (is_usb_pd_supported()) { switch (type) { case SNK: set_vif_field(&vif_fields[PD_Port_Type], - vif_component_name[PD_Port_Type], - "0", - "Consumer Only"); + vif_component_name[PD_Port_Type], "0", + "Consumer Only"); break; case SRC: set_vif_field(&vif_fields[PD_Port_Type], - vif_component_name[PD_Port_Type], - "3", - "Provider Only"); + vif_component_name[PD_Port_Type], "3", + "Provider Only"); break; case DRP: set_vif_field(&vif_fields[PD_Port_Type], - vif_component_name[PD_Port_Type], - "4", - "DRP"); + vif_component_name[PD_Port_Type], "4", + "DRP"); break; } } @@ -2772,31 +2707,27 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields, switch (type) { case SNK: set_vif_field(&vif_fields[Type_C_State_Machine], - vif_component_name[Type_C_State_Machine], - "1", - "SNK"); + vif_component_name[Type_C_State_Machine], "1", + "SNK"); break; case SRC: set_vif_field(&vif_fields[Type_C_State_Machine], - vif_component_name[Type_C_State_Machine], - "0", - "SRC"); + vif_component_name[Type_C_State_Machine], "0", + "SRC"); break; case DRP: set_vif_field(&vif_fields[Type_C_State_Machine], - vif_component_name[Type_C_State_Machine], - "2", - "DRP"); + vif_component_name[Type_C_State_Machine], "2", + "DRP"); break; } set_vif_field_b(&vif_fields[Captive_Cable], - vif_component_name[Captive_Cable], - false); + vif_component_name[Captive_Cable], false); set_vif_field_b(&vif_fields[Port_Battery_Powered], - vif_component_name[Port_Battery_Powered], - IS_ENABLED(CONFIG_BATTERY)); + vif_component_name[Port_Battery_Powered], + IS_ENABLED(CONFIG_BATTERY)); *bc_support = BC_1_2_SUPPORT_NONE; if (IS_ENABLED(CONFIG_BC12_DETECT_MAX14637)) @@ -2811,27 +2742,21 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields, switch (*bc_support) { case BC_1_2_SUPPORT_NONE: set_vif_field(&vif_fields[BC_1_2_Support], - vif_component_name[BC_1_2_Support], - "0", - "None"); + vif_component_name[BC_1_2_Support], "0", "None"); break; case BC_1_2_SUPPORT_PORTABLE_DEVICE: set_vif_field(&vif_fields[BC_1_2_Support], - vif_component_name[BC_1_2_Support], - "1", - "Portable Device"); + vif_component_name[BC_1_2_Support], "1", + "Portable Device"); break; case BC_1_2_SUPPORT_CHARGING_PORT: set_vif_field(&vif_fields[BC_1_2_Support], - vif_component_name[BC_1_2_Support], - "2", - "Charging Port"); + vif_component_name[BC_1_2_Support], "2", + "Charging Port"); break; case BC_1_2_SUPPORT_BOTH: set_vif_field(&vif_fields[BC_1_2_Support], - vif_component_name[BC_1_2_Support], - "3", - "Both"); + vif_component_name[BC_1_2_Support], "3", "Both"); break; } } @@ -2839,54 +2764,43 @@ static void init_vif_component_fields(struct vif_field_t *vif_fields, /********************************************************************* * Init VIF/Component[] General PD Fields */ -static void init_vif_component_general_pd_fields( - struct vif_field_t *vif_fields, - enum dtype type) +static void init_vif_component_general_pd_fields(struct vif_field_t *vif_fields, + enum dtype type) { if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM)) { set_vif_field(&vif_fields[PD_Spec_Revision_Major], - vif_component_name[PD_Spec_Revision_Major], - "3", - NULL); + vif_component_name[PD_Spec_Revision_Major], "3", + NULL); set_vif_field(&vif_fields[PD_Spec_Revision_Minor], - vif_component_name[PD_Spec_Revision_Minor], - "1", - NULL); + vif_component_name[PD_Spec_Revision_Minor], "1", + NULL); set_vif_field(&vif_fields[PD_Spec_Version_Major], - vif_component_name[PD_Spec_Version_Major], - "1", - NULL); + vif_component_name[PD_Spec_Version_Major], "1", + NULL); set_vif_field(&vif_fields[PD_Spec_Version_Minor], - vif_component_name[PD_Spec_Version_Minor], - "3", - NULL); + vif_component_name[PD_Spec_Version_Minor], "3", + NULL); set_vif_field(&vif_fields[PD_Specification_Revision], - vif_component_name[PD_Specification_Revision], - "2", - "Revision 3"); + vif_component_name[PD_Specification_Revision], + "2", "Revision 3"); } else { set_vif_field(&vif_fields[PD_Spec_Revision_Major], - vif_component_name[PD_Spec_Revision_Major], - "2", - NULL); + vif_component_name[PD_Spec_Revision_Major], "2", + NULL); set_vif_field(&vif_fields[PD_Spec_Revision_Minor], - vif_component_name[PD_Spec_Revision_Minor], - "0", - NULL); + vif_component_name[PD_Spec_Revision_Minor], "0", + NULL); set_vif_field(&vif_fields[PD_Spec_Version_Major], - vif_component_name[PD_Spec_Version_Major], - "1", - NULL); + vif_component_name[PD_Spec_Version_Major], "1", + NULL); set_vif_field(&vif_fields[PD_Spec_Version_Minor], - vif_component_name[PD_Spec_Version_Minor], - "3", - NULL); + vif_component_name[PD_Spec_Version_Minor], "3", + NULL); set_vif_field(&vif_fields[PD_Specification_Revision], - vif_component_name[PD_Specification_Revision], - "1", - "Revision 2"); + vif_component_name[PD_Specification_Revision], + "1", "Revision 2"); } set_vif_field_b(&vif_fields[USB_Comms_Capable], @@ -2926,18 +2840,18 @@ static void init_vif_component_general_pd_fields( supports_to_dfp = can_act_as_device(); break; case SNK: - supports_to_dfp = (can_act_as_host() || - is_alt_mode_controller()); + supports_to_dfp = + (can_act_as_host() || is_alt_mode_controller()); break; case DRP: - supports_to_dfp = (can_act_as_host() && - !can_act_as_device()); + supports_to_dfp = + (can_act_as_host() && !can_act_as_device()); break; } set_vif_field_b(&vif_fields[DR_Swap_To_DFP_Supported], - vif_component_name[DR_Swap_To_DFP_Supported], - supports_to_dfp); + vif_component_name[DR_Swap_To_DFP_Supported], + supports_to_dfp); } /* @@ -2968,18 +2882,18 @@ static void init_vif_component_general_pd_fields( supports_to_ufp = can_act_as_device(); break; case SNK: - supports_to_ufp = (can_act_as_host() || - is_alt_mode_controller()); + supports_to_ufp = + (can_act_as_host() || is_alt_mode_controller()); break; case DRP: - supports_to_ufp = (can_act_as_device() && - !can_act_as_host()); + supports_to_ufp = + (can_act_as_device() && !can_act_as_host()); break; } set_vif_field_b(&vif_fields[DR_Swap_To_UFP_Supported], - vif_component_name[DR_Swap_To_UFP_Supported], - supports_to_ufp); + vif_component_name[DR_Swap_To_UFP_Supported], + supports_to_ufp); } if (is_src()) { @@ -2987,52 +2901,50 @@ static void init_vif_component_general_pd_fields( if (IS_ENABLED(CONFIG_CHARGER)) /* USB-C UP bit set */ set_vif_field_b(&vif_fields[Unconstrained_Power], - vif_component_name[Unconstrained_Power], - (src_pdo[0] & PDO_FIXED_UNCONSTRAINED)); + vif_component_name[Unconstrained_Power], + (src_pdo[0] & PDO_FIXED_UNCONSTRAINED)); else { /* Barrel charger being used */ int32_t dedicated_charge_port_count = 0; - #ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT - dedicated_charge_port_count = - CONFIG_DEDICATED_CHARGE_PORT_COUNT; - #endif +#ifdef CONFIG_DEDICATED_CHARGE_PORT_COUNT + dedicated_charge_port_count = + CONFIG_DEDICATED_CHARGE_PORT_COUNT; +#endif set_vif_field_b(&vif_fields[Unconstrained_Power], - vif_component_name[Unconstrained_Power], - (dedicated_charge_port_count > 0)); + vif_component_name[Unconstrained_Power], + (dedicated_charge_port_count > 0)); } } else { /* Not SRC capable */ set_vif_field_b(&vif_fields[Unconstrained_Power], - vif_component_name[Unconstrained_Power], - false); + vif_component_name[Unconstrained_Power], false); } set_vif_field_b(&vif_fields[VCONN_Swap_To_On_Supported], - vif_component_name[VCONN_Swap_To_On_Supported], - IS_ENABLED(CONFIG_USBC_VCONN_SWAP)); + vif_component_name[VCONN_Swap_To_On_Supported], + IS_ENABLED(CONFIG_USBC_VCONN_SWAP)); set_vif_field_b(&vif_fields[VCONN_Swap_To_Off_Supported], - vif_component_name[VCONN_Swap_To_Off_Supported], - IS_ENABLED(CONFIG_USBC_VCONN_SWAP)); + vif_component_name[VCONN_Swap_To_Off_Supported], + IS_ENABLED(CONFIG_USBC_VCONN_SWAP)); set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_UFP], - vif_component_name[Responds_To_Discov_SOP_UFP], - does_respond_to_discov_sop_ufp()); + vif_component_name[Responds_To_Discov_SOP_UFP], + does_respond_to_discov_sop_ufp()); set_vif_field_b(&vif_fields[Responds_To_Discov_SOP_DFP], - vif_component_name[Responds_To_Discov_SOP_DFP], - does_respond_to_discov_sop_dfp()); + vif_component_name[Responds_To_Discov_SOP_DFP], + does_respond_to_discov_sop_dfp()); set_vif_field_b(&vif_fields[Attempts_Discov_SOP], - vif_component_name[Attempts_Discov_SOP], - ((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) || - (type != SRC))); + vif_component_name[Attempts_Discov_SOP], + ((!IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP)) || + (type != SRC))); set_vif_field(&vif_fields[Power_Interruption_Available], - vif_component_name[Power_Interruption_Available], - "0", + vif_component_name[Power_Interruption_Available], "0", "No Interruption Possible"); set_vif_field_b(&vif_fields[Data_Reset_Supported], @@ -3044,141 +2956,137 @@ static void init_vif_component_general_pd_fields( IS_ENABLED(CONFIG_USB_PD_USB4)); set_vif_field_b(&vif_fields[Chunking_Implemented_SOP], - vif_component_name[Chunking_Implemented_SOP], - (IS_ENABLED(CONFIG_USB_PD_REV30) && - IS_ENABLED(CONFIG_USB_PRL_SM))); + vif_component_name[Chunking_Implemented_SOP], + (IS_ENABLED(CONFIG_USB_PD_REV30) && + IS_ENABLED(CONFIG_USB_PRL_SM))); - set_vif_field_b(&vif_fields[Unchunked_Extended_Messages_Supported], + set_vif_field_b( + &vif_fields[Unchunked_Extended_Messages_Supported], vif_component_name[Unchunked_Extended_Messages_Supported], false); if (IS_ENABLED(CONFIG_USB_PD_MANUFACTURER_INFO)) { char hex_str[10]; - set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port], + set_vif_field_b( + &vif_fields[Manufacturer_Info_Supported_Port], vif_component_name[Manufacturer_Info_Supported_Port], true); sprintf(hex_str, "%04X", USB_VID_GOOGLE); - set_vif_field_itss(&vif_fields[Manufacturer_Info_VID_Port], + set_vif_field_itss( + &vif_fields[Manufacturer_Info_VID_Port], vif_component_name[Manufacturer_Info_VID_Port], USB_VID_GOOGLE, hex_str); - #if defined(CONFIG_USB_PID) - sprintf(hex_str, "%04X", CONFIG_USB_PID); - set_vif_field_itss(&vif_fields[ - Manufacturer_Info_PID_Port], - vif_component_name[Manufacturer_Info_PID_Port], - CONFIG_USB_PID, hex_str); - #else - sprintf(hex_str, "%04X", DEFAULT_MISSING_PID); - set_vif_field_itss(&vif_fields[ - Manufacturer_Info_PID_Port], - vif_component_name[Manufacturer_Info_PID_Port], - DEFAULT_MISSING_PID, hex_str); - #endif +#if defined(CONFIG_USB_PID) + sprintf(hex_str, "%04X", CONFIG_USB_PID); + set_vif_field_itss( + &vif_fields[Manufacturer_Info_PID_Port], + vif_component_name[Manufacturer_Info_PID_Port], + CONFIG_USB_PID, hex_str); +#else + sprintf(hex_str, "%04X", DEFAULT_MISSING_PID); + set_vif_field_itss( + &vif_fields[Manufacturer_Info_PID_Port], + vif_component_name[Manufacturer_Info_PID_Port], + DEFAULT_MISSING_PID, hex_str); +#endif } else { - set_vif_field_b(&vif_fields[Manufacturer_Info_Supported_Port], + set_vif_field_b( + &vif_fields[Manufacturer_Info_Supported_Port], vif_component_name[Manufacturer_Info_Supported_Port], false); } set_vif_field_b(&vif_fields[Security_Msgs_Supported_SOP], - vif_component_name[Security_Msgs_Supported_SOP], - IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS)); - - #if defined(CONFIG_NUM_FIXED_BATTERIES) - set_vif_field_itss(&vif_fields[Num_Fixed_Batteries], - vif_component_name[Num_Fixed_Batteries], - CONFIG_NUM_FIXED_BATTERIES, NULL); - #elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD) - set_vif_field(&vif_fields[Num_Fixed_Batteries], - vif_component_name[Num_Fixed_Batteries], - "0", NULL); - #else - set_vif_field(&vif_fields[Num_Fixed_Batteries], - vif_component_name[Num_Fixed_Batteries], - "1", NULL); - #endif + vif_component_name[Security_Msgs_Supported_SOP], + IS_ENABLED(CONFIG_USB_PD_SECURITY_MSGS)); + +#if defined(CONFIG_NUM_FIXED_BATTERIES) + set_vif_field_itss(&vif_fields[Num_Fixed_Batteries], + vif_component_name[Num_Fixed_Batteries], + CONFIG_NUM_FIXED_BATTERIES, NULL); +#elif defined(CONFIG_USB_CTVPD) || defined(CONFIG_USB_VPD) + set_vif_field(&vif_fields[Num_Fixed_Batteries], + vif_component_name[Num_Fixed_Batteries], "0", NULL); +#else + set_vif_field(&vif_fields[Num_Fixed_Batteries], + vif_component_name[Num_Fixed_Batteries], "1", NULL); +#endif set_vif_field(&vif_fields[Num_Swappable_Battery_Slots], - vif_component_name[Num_Swappable_Battery_Slots], - "0", NULL); + vif_component_name[Num_Swappable_Battery_Slots], "0", + NULL); set_vif_field(&vif_fields[ID_Header_Connector_Type_SOP], - vif_component_name[ID_Header_Connector_Type_SOP], - "2", "USB Type-C\u00ae Receptacle"); + vif_component_name[ID_Header_Connector_Type_SOP], "2", + "USB Type-C\u00ae Receptacle"); } /********************************************************************* * Init VIF/Component[] SOP* Capabilities Fields */ -static void init_vif_component_sop_capabilities_fields( - struct vif_field_t *vif_fields) +static void +init_vif_component_sop_capabilities_fields(struct vif_field_t *vif_fields) { set_vif_field_b(&vif_fields[SOP_Capable], - vif_component_name[SOP_Capable], - can_act_as_host()); + vif_component_name[SOP_Capable], can_act_as_host()); set_vif_field_b(&vif_fields[SOP_P_Capable], - vif_component_name[SOP_P_Capable], - IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)); + vif_component_name[SOP_P_Capable], + IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)); set_vif_field_b(&vif_fields[SOP_PP_Capable], - vif_component_name[SOP_PP_Capable], - IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)); + vif_component_name[SOP_PP_Capable], + IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)); set_vif_field_b(&vif_fields[SOP_P_Debug_Capable], - vif_component_name[SOP_P_Debug_Capable], - false); + vif_component_name[SOP_P_Debug_Capable], false); set_vif_field_b(&vif_fields[SOP_PP_Debug_Capable], - vif_component_name[SOP_PP_Debug_Capable], - false); + vif_component_name[SOP_PP_Debug_Capable], false); } /********************************************************************* * Init VIF/Component[] USB Type-C Fields */ -static void init_vif_component_usb_type_c_fields( - struct vif_field_t *vif_fields, - enum dtype type) +static void init_vif_component_usb_type_c_fields(struct vif_field_t *vif_fields, + enum dtype type) { set_vif_field_b(&vif_fields[Type_C_Implements_Try_SRC], - vif_component_name[Type_C_Implements_Try_SRC], - IS_ENABLED(CONFIG_USB_PD_TRY_SRC)); + vif_component_name[Type_C_Implements_Try_SRC], + IS_ENABLED(CONFIG_USB_PD_TRY_SRC)); set_vif_field_b(&vif_fields[Type_C_Implements_Try_SNK], - vif_component_name[Type_C_Implements_Try_SNK], - false); + vif_component_name[Type_C_Implements_Try_SNK], false); { int rp = CONFIG_USB_PD_PULLUP; - #if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) - rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT; - #endif +#if defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) + rp = CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT; +#endif switch (rp) { case 0: set_vif_field(&vif_fields[RP_Value], - vif_component_name[RP_Value], - "0", "Default"); + vif_component_name[RP_Value], "0", + "Default"); break; case 1: set_vif_field(&vif_fields[RP_Value], - vif_component_name[RP_Value], - "1", "1.5A"); + vif_component_name[RP_Value], "1", + "1.5A"); break; case 2: set_vif_field(&vif_fields[RP_Value], - vif_component_name[RP_Value], - "2", "3A"); + vif_component_name[RP_Value], "2", "3A"); break; default: set_vif_field_itss(&vif_fields[RP_Value], - vif_component_name[RP_Value], - rp, NULL); + vif_component_name[RP_Value], rp, + NULL); } } @@ -3190,39 +3098,37 @@ static void init_vif_component_usb_type_c_fields( false); set_vif_field_b(&vif_fields[Type_C_Is_VCONN_Powered_Accessory], - vif_component_name[Type_C_Is_VCONN_Powered_Accessory], - false); + vif_component_name[Type_C_Is_VCONN_Powered_Accessory], + false); set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SRC], - vif_component_name[Type_C_Is_Debug_Target_SRC], - true); + vif_component_name[Type_C_Is_Debug_Target_SRC], true); set_vif_field_b(&vif_fields[Type_C_Is_Debug_Target_SNK], - vif_component_name[Type_C_Is_Debug_Target_SNK], - true); + vif_component_name[Type_C_Is_Debug_Target_SNK], true); set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Host], - vif_component_name[Type_C_Can_Act_As_Host], - can_act_as_host()); + vif_component_name[Type_C_Can_Act_As_Host], + can_act_as_host()); set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Controller], - vif_component_name[Type_C_Is_Alt_Mode_Controller], - is_alt_mode_controller()); + vif_component_name[Type_C_Is_Alt_Mode_Controller], + is_alt_mode_controller()); if (can_act_as_device()) { set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device], - vif_component_name[Type_C_Can_Act_As_Device], - true); + vif_component_name[Type_C_Can_Act_As_Device], + true); - if (is_usb_pd_supported() && - does_respond_to_discov_sop_ufp()) - set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter], + if (is_usb_pd_supported() && does_respond_to_discov_sop_ufp()) + set_vif_field_b( + &vif_fields[Type_C_Is_Alt_Mode_Adapter], vif_component_name[Type_C_Is_Alt_Mode_Adapter], IS_ENABLED(CONFIG_USB_ALT_MODE_ADAPTER)); } else { set_vif_field_b(&vif_fields[Type_C_Can_Act_As_Device], - vif_component_name[Type_C_Can_Act_As_Device], - false); + vif_component_name[Type_C_Can_Act_As_Device], + false); set_vif_field_b(&vif_fields[Type_C_Is_Alt_Mode_Adapter], vif_component_name[Type_C_Is_Alt_Mode_Adapter], false); @@ -3247,37 +3153,37 @@ static void init_vif_component_usb_type_c_fields( switch (ps) { case POWER_EXTERNAL: set_vif_field(&vif_fields[Type_C_Power_Source], - vif_component_name[Type_C_Power_Source], - "0", "Externally Powered"); + vif_component_name[Type_C_Power_Source], + "0", "Externally Powered"); break; case POWER_UFP: set_vif_field(&vif_fields[Type_C_Power_Source], - vif_component_name[Type_C_Power_Source], - "1", "UFP-powered"); + vif_component_name[Type_C_Power_Source], + "1", "UFP-powered"); break; case POWER_BOTH: set_vif_field(&vif_fields[Type_C_Power_Source], - vif_component_name[Type_C_Power_Source], - "2", "Both"); + vif_component_name[Type_C_Power_Source], + "2", "Both"); break; default: - set_vif_field_itss(&vif_fields[Type_C_Power_Source], - vif_component_name[Type_C_Power_Source], - ps, NULL); + set_vif_field_itss( + &vif_fields[Type_C_Power_Source], + vif_component_name[Type_C_Power_Source], ps, + NULL); } } set_vif_field_b(&vif_fields[Type_C_Port_On_Hub], - vif_component_name[Type_C_Port_On_Hub], - false); + vif_component_name[Type_C_Port_On_Hub], false); set_vif_field_b(&vif_fields[Type_C_Supports_Audio_Accessory], - vif_component_name[Type_C_Supports_Audio_Accessory], - false); + vif_component_name[Type_C_Supports_Audio_Accessory], + false); set_vif_field_b(&vif_fields[Type_C_Sources_VCONN], - vif_component_name[Type_C_Sources_VCONN], - IS_ENABLED(CONFIG_USBC_VCONN)); + vif_component_name[Type_C_Sources_VCONN], + IS_ENABLED(CONFIG_USBC_VCONN)); } static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields) @@ -3288,8 +3194,7 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields) if (!is_usb4_supported()) return; - set_vif_field_c(&vif_fields[USB4_Port_Header], - "USB4\u2122 Port"); + set_vif_field_c(&vif_fields[USB4_Port_Header], "USB4\u2122 Port"); vi = vif_get_max_tbt_speed(); switch (vi) { @@ -3304,8 +3209,7 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields) } set_vif_field_itss(&vif_fields[USB4_Max_Speed], - vif_component_name[USB4_Max_Speed], - vi, vs); + vif_component_name[USB4_Max_Speed], vi, vs); set_vif_field_b(&vif_fields[USB4_TBT3_Compatibility_Supported], vif_component_name[USB4_TBT3_Compatibility_Supported], @@ -3330,8 +3234,8 @@ static void init_vif_component_usb4_port_fields(struct vif_field_t *vif_fields) * Device_Gen1x1_tLinkTurnaround numericFieldType * Device_Gen2x1_tLinkTurnaround numericFieldType */ -static void init_vif_component_usb_data_ufp_fields( - struct vif_field_t *vif_fields) +static void +init_vif_component_usb_data_ufp_fields(struct vif_field_t *vif_fields) { /* * TOTO(b:172441959) Adjust the speed based on CONFIG_ @@ -3351,37 +3255,36 @@ static void init_vif_component_usb_data_ufp_fields( return; supports_usb_data = does_support_device_usb_data(); - set_vif_field_b( - &vif_fields[Device_Supports_USB_Data], - vif_component_name[Device_Supports_USB_Data], - supports_usb_data); + set_vif_field_b(&vif_fields[Device_Supports_USB_Data], + vif_component_name[Device_Supports_USB_Data], + supports_usb_data); if (supports_usb_data) { switch (ds) { case USB_2: set_vif_field_itss(&vif_fields[Device_Speed], - vif_component_name[Device_Speed], - USB_2, "USB 2"); + vif_component_name[Device_Speed], + USB_2, "USB 2"); break; case USB_GEN11: set_vif_field_itss(&vif_fields[Device_Speed], - vif_component_name[Device_Speed], - USB_GEN11, "USB 3.2 Gen 1x1"); + vif_component_name[Device_Speed], + USB_GEN11, "USB 3.2 Gen 1x1"); break; case USB_GEN21: set_vif_field_itss(&vif_fields[Device_Speed], - vif_component_name[Device_Speed], - USB_GEN21, "USB 3.2 Gen 2x1"); + vif_component_name[Device_Speed], + USB_GEN21, "USB 3.2 Gen 2x1"); break; case USB_GEN12: set_vif_field_itss(&vif_fields[Device_Speed], - vif_component_name[Device_Speed], - USB_GEN12, "USB 3.2 Gen 1x2"); + vif_component_name[Device_Speed], + USB_GEN12, "USB 3.2 Gen 1x2"); break; case USB_GEN22: set_vif_field_itss(&vif_fields[Device_Speed], - vif_component_name[Device_Speed], - USB_GEN22, "USB 3.2 Gen 2x2"); + vif_component_name[Device_Speed], + USB_GEN22, "USB 3.2 Gen 2x2"); break; } } @@ -3402,8 +3305,8 @@ static void init_vif_component_usb_data_ufp_fields( * Host_Gen2x1_tLinkTurnaround numericFieldType * Host_Suspend_Supported booleanFieldType */ -static void init_vif_component_usb_data_dfp_fields( - struct vif_field_t *vif_fields) +static void +init_vif_component_usb_data_dfp_fields(struct vif_field_t *vif_fields) { /* * TOTO(b:172438944) Adjust the speed based on CONFIG_ @@ -3426,65 +3329,63 @@ static void init_vif_component_usb_data_dfp_fields( supports_usb_data = does_support_host_usb_data(); set_vif_field_b(&vif_fields[Host_Supports_USB_Data], - vif_component_name[Host_Supports_USB_Data], - supports_usb_data); + vif_component_name[Host_Supports_USB_Data], + supports_usb_data); if (supports_usb_data) { switch (ds) { case USB_2: set_vif_field_itss(&vif_fields[Host_Speed], - vif_component_name[Host_Speed], - USB_2, "USB 2"); + vif_component_name[Host_Speed], + USB_2, "USB 2"); break; case USB_GEN11: set_vif_field_itss(&vif_fields[Host_Speed], - vif_component_name[Host_Speed], - USB_GEN11, "USB 3.2 Gen 1x1"); + vif_component_name[Host_Speed], + USB_GEN11, "USB 3.2 Gen 1x1"); break; case USB_GEN21: set_vif_field_itss(&vif_fields[Host_Speed], - vif_component_name[Host_Speed], - USB_GEN21, "USB 3.2 Gen 2x1"); + vif_component_name[Host_Speed], + USB_GEN21, "USB 3.2 Gen 2x1"); break; case USB_GEN12: set_vif_field_itss(&vif_fields[Host_Speed], - vif_component_name[Host_Speed], - USB_GEN12, "USB 3.2 Gen 1x2"); + vif_component_name[Host_Speed], + USB_GEN12, "USB 3.2 Gen 1x2"); break; case USB_GEN22: set_vif_field_itss(&vif_fields[Host_Speed], - vif_component_name[Host_Speed], - USB_GEN22, "USB 3.2 Gen 2x2"); + vif_component_name[Host_Speed], + USB_GEN22, "USB 3.2 Gen 2x2"); break; } - if (!get_vif_field_tag_bool( - &vif_fields[Type_C_Port_On_Hub], - &is_dfp_on_hub)) + if (!get_vif_field_tag_bool(&vif_fields[Type_C_Port_On_Hub], + &is_dfp_on_hub)) is_dfp_on_hub = false; set_vif_field_b(&vif_fields[Is_DFP_On_Hub], - vif_component_name[Is_DFP_On_Hub], - is_dfp_on_hub); + vif_component_name[Is_DFP_On_Hub], + is_dfp_on_hub); - set_vif_field_b(&vif_fields[Host_Contains_Captive_Retimer], + set_vif_field_b( + &vif_fields[Host_Contains_Captive_Retimer], vif_component_name[Host_Contains_Captive_Retimer], false); set_vif_field_b(&vif_fields[Host_Is_Embedded], - vif_component_name[Host_Is_Embedded], - false); + vif_component_name[Host_Is_Embedded], false); } } /********************************************************************* * Init VIF/Component[] PD Source Fields */ -static int init_vif_component_pd_source_fields( - struct vif_field_t *vif_fields, - struct vif_srcPdoList_t *comp_src_pdo_list, - int32_t *src_max_power, - enum dtype type) +static int +init_vif_component_pd_source_fields(struct vif_field_t *vif_fields, + struct vif_srcPdoList_t *comp_src_pdo_list, + int32_t *src_max_power, enum dtype type) { if (type == DRP || type == SRC) { int i; @@ -3511,78 +3412,78 @@ static int init_vif_component_pd_source_fields( sprintf(str, "%d mW", *src_max_power); set_vif_field_itss(&vif_fields[PD_Power_As_Source], - vif_component_name[PD_Power_As_Source], - *src_max_power, str); + vif_component_name[PD_Power_As_Source], + *src_max_power, str); } if (type == DRP || type == SRC) set_vif_field_b(&vif_fields[USB_Suspend_May_Be_Cleared], - vif_component_name[USB_Suspend_May_Be_Cleared], - false); + vif_component_name[USB_Suspend_May_Be_Cleared], + false); if (type == DRP || type == SRC) set_vif_field_b(&vif_fields[Sends_Pings], - vif_component_name[Sends_Pings], - false); + vif_component_name[Sends_Pings], false); - if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) && - type == DRP && + if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) && type == DRP && IS_ENABLED(CONFIG_USB_PD_FRS)) - set_vif_field(&vif_fields[ - FR_Swap_Type_C_Current_Capability_As_Initial_Sink], + set_vif_field( + &vif_fields + [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], vif_component_name - [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], + [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], "3", "3A @ 5V"); else - set_vif_field(&vif_fields[ - FR_Swap_Type_C_Current_Capability_As_Initial_Sink], + set_vif_field( + &vif_fields + [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], vif_component_name - [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], + [FR_Swap_Type_C_Current_Capability_As_Initial_Sink], "0", "FR_Swap not supported"); if (IS_ENABLED(CONFIG_USB_PD_REV30) || IS_ENABLED(CONFIG_USB_PRL_SM)) set_vif_field_b(&vif_fields[Master_Port], - vif_component_name[Master_Port], - false); + vif_component_name[Master_Port], false); if (type == DRP || type == SRC) set_vif_field_itss(&vif_fields[Num_Src_PDOs], - vif_component_name[Num_Src_PDOs], - src_pdo_cnt, NULL); + vif_component_name[Num_Src_PDOs], + src_pdo_cnt, NULL); if (type == DRP || type == SRC) { if (IS_ENABLED(CONFIG_USBC_OCP)) { int resp = 0; set_vif_field_b(&vif_fields[PD_OC_Protection], - vif_component_name[PD_OC_Protection], - true); + vif_component_name[PD_OC_Protection], + true); switch (resp) { case 0: set_vif_field(&vif_fields[PD_OCP_Method], - vif_component_name[PD_OCP_Method], - "0", "Over-Current Response"); + vif_component_name[PD_OCP_Method], + "0", "Over-Current Response"); break; case 1: set_vif_field(&vif_fields[PD_OCP_Method], - vif_component_name[PD_OCP_Method], - "1", "Under-Voltage Response"); + vif_component_name[PD_OCP_Method], + "1", "Under-Voltage Response"); break; case 2: set_vif_field(&vif_fields[PD_OCP_Method], - vif_component_name[PD_OCP_Method], - "2", "Both"); + vif_component_name[PD_OCP_Method], + "2", "Both"); break; default: - set_vif_field_itss(&vif_fields[PD_OCP_Method], - vif_component_name[PD_OCP_Method], - resp, NULL); + set_vif_field_itss( + &vif_fields[PD_OCP_Method], + vif_component_name[PD_OCP_Method], resp, + NULL); } } else { set_vif_field_b(&vif_fields[PD_OC_Protection], - vif_component_name[PD_OC_Protection], - false); + vif_component_name[PD_OC_Protection], + false); } } @@ -3592,10 +3493,10 @@ static int init_vif_component_pd_source_fields( /********************************************************************* * Init VIF/Component[] PD Sink Fields */ -static int init_vif_component_pd_sink_fields( - struct vif_field_t *vif_fields, - struct vif_snkPdoList_t *comp_snk_pdo_list, - enum dtype type) +static int +init_vif_component_pd_sink_fields(struct vif_field_t *vif_fields, + struct vif_snkPdoList_t *comp_snk_pdo_list, + enum dtype type) { int i; int32_t snk_max_power = 0; @@ -3607,15 +3508,13 @@ static int init_vif_component_pd_sink_fields( set_vif_field_c(&vif_fields[PD_Sink_Header], "PD Sink"); set_vif_field_b(&vif_fields[EPR_Supported_As_Snk], - vif_component_name[EPR_Supported_As_Snk], - false); + vif_component_name[EPR_Supported_As_Snk], false); /* Sink PDOs */ for (i = 0; i < pd_snk_pdo_cnt; i++) { int32_t pwr; - pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i], - pd_snk_pdo[i]); + pwr = init_vif_snk_pdo(&comp_snk_pdo_list[i], pd_snk_pdo[i]); if (pwr < 0) { fprintf(stderr, "ERROR: Setting SNK PDO.\n"); return 1; @@ -3627,30 +3526,27 @@ static int init_vif_component_pd_sink_fields( sprintf(str, "%d mW", snk_max_power); set_vif_field_itss(&vif_fields[PD_Power_As_Sink], - vif_component_name[PD_Power_As_Sink], - snk_max_power, str); + vif_component_name[PD_Power_As_Sink], snk_max_power, + str); set_vif_field_b(&vif_fields[No_USB_Suspend_May_Be_Set], - vif_component_name[No_USB_Suspend_May_Be_Set], - true); + vif_component_name[No_USB_Suspend_May_Be_Set], true); set_vif_field_b(&vif_fields[GiveBack_May_Be_Set], - vif_component_name[GiveBack_May_Be_Set], - IS_ENABLED(CONFIG_USB_PD_GIVE_BACK)); + vif_component_name[GiveBack_May_Be_Set], + IS_ENABLED(CONFIG_USB_PD_GIVE_BACK)); set_vif_field_b(&vif_fields[Higher_Capability_Set], - vif_component_name[Higher_Capability_Set], - false); + vif_component_name[Higher_Capability_Set], false); - set_vif_field(&vif_fields[ - FR_Swap_Reqd_Type_C_Current_As_Initial_Source], - vif_component_name - [FR_Swap_Reqd_Type_C_Current_As_Initial_Source], + set_vif_field( + &vif_fields[FR_Swap_Reqd_Type_C_Current_As_Initial_Source], + vif_component_name[FR_Swap_Reqd_Type_C_Current_As_Initial_Source], "0", "FR_Swap not supported"); set_vif_field_itss(&vif_fields[Num_Snk_PDOs], - vif_component_name[Num_Snk_PDOs], - pd_snk_pdo_cnt, NULL); + vif_component_name[Num_Snk_PDOs], pd_snk_pdo_cnt, + NULL); return 0; } @@ -3658,32 +3554,28 @@ static int init_vif_component_pd_sink_fields( /********************************************************************* * Init VIF/Component[] PD Dual Role Fields */ -static void init_vif_component_pd_dual_role_fields( - struct vif_field_t *vif_fields, - enum dtype type) +static void +init_vif_component_pd_dual_role_fields(struct vif_field_t *vif_fields, + enum dtype type) { if (!IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) || type != DRP) return; set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Src], - vif_component_name[Accepts_PR_Swap_As_Src], - true); + vif_component_name[Accepts_PR_Swap_As_Src], true); set_vif_field_b(&vif_fields[Accepts_PR_Swap_As_Snk], - vif_component_name[Accepts_PR_Swap_As_Snk], - true); + vif_component_name[Accepts_PR_Swap_As_Snk], true); set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Src], - vif_component_name[Requests_PR_Swap_As_Src], - true); + vif_component_name[Requests_PR_Swap_As_Src], true); set_vif_field_b(&vif_fields[Requests_PR_Swap_As_Snk], - vif_component_name[Requests_PR_Swap_As_Snk], - true); + vif_component_name[Requests_PR_Swap_As_Snk], true); set_vif_field_b(&vif_fields[FR_Swap_Supported_As_Initial_Sink], - vif_component_name[FR_Swap_Supported_As_Initial_Sink], - IS_ENABLED(CONFIG_USB_PD_FRS)); + vif_component_name[FR_Swap_Supported_As_Initial_Sink], + IS_ENABLED(CONFIG_USB_PD_FRS)); } /********************************************************************* @@ -3702,8 +3594,8 @@ static void init_vif_component_pd_dual_role_fields( * Num_SVIDs_Max_SOP numericFieldType * SVID_Fixed_SOP booleanFieldType */ -static void init_vif_component_sop_discovery_fields( - struct vif_field_t *vif_fields) +static void +init_vif_component_sop_discovery_fields(struct vif_field_t *vif_fields) { char hex_str[10]; @@ -3716,77 +3608,69 @@ static void init_vif_component_sop_discovery_fields( !does_respond_to_discov_sop_dfp()) return; - set_vif_field(&vif_fields[XID_SOP], - vif_component_name[XID_SOP], - "0", - NULL); + set_vif_field(&vif_fields[XID_SOP], vif_component_name[XID_SOP], "0", + NULL); set_vif_field_b(&vif_fields[Data_Capable_As_USB_Host_SOP], - vif_component_name[Data_Capable_As_USB_Host_SOP], - can_act_as_host()); + vif_component_name[Data_Capable_As_USB_Host_SOP], + can_act_as_host()); set_vif_field_b(&vif_fields[Data_Capable_As_USB_Device_SOP], - vif_component_name[Data_Capable_As_USB_Device_SOP], - can_act_as_device()); + vif_component_name[Data_Capable_As_USB_Device_SOP], + can_act_as_device()); if (does_respond_to_discov_sop_dfp() && IS_ENABLED(CONFIG_USB_PD_REV30)) { #if defined(CONFIG_USB_PD_PORT_LABEL) set_vif_field_stis(&vif_fields[DFP_VDO_Port_Number], - vif_component_name[DFP_VDO_Port_Number], - NULL, - CONFIG_USB_PD_PORT_LABEL); + vif_component_name[DFP_VDO_Port_Number], + NULL, CONFIG_USB_PD_PORT_LABEL); #else set_vif_field_itss(&vif_fields[DFP_VDO_Port_Number], - vif_component_name[DFP_VDO_Port_Number], - component_index, - NULL); + vif_component_name[DFP_VDO_Port_Number], + component_index, NULL); #endif } sprintf(hex_str, "%04X", USB_VID_GOOGLE); set_vif_field_itss(&vif_fields[USB_VID_SOP], - vif_component_name[USB_VID_SOP], - USB_VID_GOOGLE, hex_str); + vif_component_name[USB_VID_SOP], USB_VID_GOOGLE, + hex_str); - #if defined(CONFIG_USB_PID) - sprintf(hex_str, "%04X", CONFIG_USB_PID); - set_vif_field_itss(&vif_fields[PID_SOP], - vif_component_name[PID_SOP], - CONFIG_USB_PID, hex_str); - #else - sprintf(hex_str, "%04X", DEFAULT_MISSING_PID); - set_vif_field_itss(&vif_fields[PID_SOP], - vif_component_name[PID_SOP], - DEFAULT_MISSING_PID, hex_str); - #endif +#if defined(CONFIG_USB_PID) + sprintf(hex_str, "%04X", CONFIG_USB_PID); + set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP], + CONFIG_USB_PID, hex_str); +#else + sprintf(hex_str, "%04X", DEFAULT_MISSING_PID); + set_vif_field_itss(&vif_fields[PID_SOP], vif_component_name[PID_SOP], + DEFAULT_MISSING_PID, hex_str); +#endif - #if defined(CONFIG_USB_BCD_DEV) - sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV); - set_vif_field_itss(&vif_fields[bcdDevice_SOP], - vif_component_name[bcdDevice_SOP], - CONFIG_USB_BCD_DEV, hex_str); - #else - sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV); - set_vif_field_itss(&vif_fields[bcdDevice_SOP], - vif_component_name[bcdDevice_SOP], - DEFAULT_MISSING_BCD_DEV, hex_str); - #endif +#if defined(CONFIG_USB_BCD_DEV) + sprintf(hex_str, "%04X", CONFIG_USB_BCD_DEV); + set_vif_field_itss(&vif_fields[bcdDevice_SOP], + vif_component_name[bcdDevice_SOP], + CONFIG_USB_BCD_DEV, hex_str); +#else + sprintf(hex_str, "%04X", DEFAULT_MISSING_BCD_DEV); + set_vif_field_itss(&vif_fields[bcdDevice_SOP], + vif_component_name[bcdDevice_SOP], + DEFAULT_MISSING_BCD_DEV, hex_str); +#endif } /********************************************************************* * Init VIF/Component[] Battery Charging 1.2 Fields */ -static void init_vif_component_bc_1_2_fields( - struct vif_field_t *vif_fields, - enum bc_1_2_support bc_support) +static void init_vif_component_bc_1_2_fields(struct vif_field_t *vif_fields, + enum bc_1_2_support bc_support) { if (bc_support == BC_1_2_SUPPORT_CHARGING_PORT || bc_support == BC_1_2_SUPPORT_BOTH) set_vif_field(&vif_fields[BC_1_2_Charging_Port_Type], - vif_component_name[BC_1_2_Charging_Port_Type], - "1", - "CDP"); + vif_component_name[BC_1_2_Charging_Port_Type], + "1", "CDP"); } /********************************************************************* @@ -3801,24 +3685,24 @@ static void init_vif_component_bc_1_2_fields( * Port_Source_Power_Gang nonEmptyString * Port_Source_Power_Gang_Max_Power numericFieldType */ -static void init_vif_component_product_power_fields( - struct vif_field_t *vif_fields, - int32_t src_max_power, - enum dtype type) +static void +init_vif_component_product_power_fields(struct vif_field_t *vif_fields, + int32_t src_max_power, enum dtype type) { if (type == DRP || type == SRC) { char str[14]; sprintf(str, "%d mW", src_max_power); - set_vif_field_itss(&vif_fields[Product_Total_Source_Power_mW], + set_vif_field_itss( + &vif_fields[Product_Total_Source_Power_mW], vif_component_name[Product_Total_Source_Power_mW], src_max_power, str); } if (type == DRP || type == SRC) set_vif_field(&vif_fields[Port_Source_Power_Type], - vif_component_name[Port_Source_Power_Type], - "0", "Assured"); + vif_component_name[Port_Source_Power_Type], "0", + "Assured"); } static void init_remarks(struct vif_t *vif) @@ -3852,24 +3736,18 @@ static void init_remarks(struct vif_t *vif) set_vif_field_c(&vif_fields[SOP_Discover_ID_Header], "SOP Discover ID"); } - } -static int gen_vif(const char *board, - struct vif_t *vif) +static int gen_vif(const char *board, struct vif_t *vif) { int max_component_index = board_get_usb_pd_port_count(); /********************************************************************* * Initialize the vif structure */ - init_vif_fields( - vif->vif_field, - vif->vif_app_field, - board); + init_vif_fields(vif->vif_field, vif->vif_app_field, board); - for (component_index = 0; - component_index < max_component_index; + for (component_index = 0; component_index < max_component_index; component_index++) { int override_value; bool was_overridden; @@ -3878,11 +3756,10 @@ static int gen_vif(const char *board, enum bc_1_2_support bc_support = BC_1_2_SUPPORT_NONE; /* Determine if we are DRP, SRC or SNK */ - was_overridden = - get_vif_field_tag_number( - &vif->Component[component_index] - .vif_field[Type_C_State_Machine], - &override_value); + was_overridden = get_vif_field_tag_number( + &vif->Component[component_index] + .vif_field[Type_C_State_Machine], + &override_value); if (was_overridden) { switch (override_value) { case SRC: @@ -3895,20 +3772,19 @@ static int gen_vif(const char *board, } } if (!was_overridden) { - was_overridden = - get_vif_field_tag_number( - &vif->Component[component_index] - .vif_field[PD_Port_Type], - &override_value); + was_overridden = get_vif_field_tag_number( + &vif->Component[component_index] + .vif_field[PD_Port_Type], + &override_value); if (was_overridden) { switch (override_value) { - case PORT_CONSUMER_ONLY: /* SNK */ + case PORT_CONSUMER_ONLY: /* SNK */ type = SNK; break; - case PORT_PROVIDER_ONLY: /* SRC */ + case PORT_PROVIDER_ONLY: /* SRC */ type = SRC; break; - case PORT_DRP: /* DRP */ + case PORT_DRP: /* DRP */ type = DRP; break; default: @@ -3933,60 +3809,51 @@ static int gen_vif(const char *board, return 1; } - init_vif_component_fields( - vif->Component[component_index].vif_field, - &bc_support, - type); + vif->Component[component_index].vif_field, &bc_support, + type); init_vif_component_general_pd_fields( - vif->Component[component_index].vif_field, - type); + vif->Component[component_index].vif_field, type); init_vif_component_sop_capabilities_fields( - vif->Component[component_index].vif_field); + vif->Component[component_index].vif_field); init_vif_component_usb_type_c_fields( - vif->Component[component_index].vif_field, - type); + vif->Component[component_index].vif_field, type); init_vif_component_usb4_port_fields( vif->Component[component_index].vif_field); init_vif_component_usb_data_ufp_fields( - vif->Component[component_index].vif_field); + vif->Component[component_index].vif_field); init_vif_component_usb_data_dfp_fields( - vif->Component[component_index].vif_field); + vif->Component[component_index].vif_field); if (init_vif_component_pd_source_fields( - vif->Component[component_index].vif_field, - vif->Component[component_index].SrcPdoList, - &src_max_power, - type)) + vif->Component[component_index].vif_field, + vif->Component[component_index].SrcPdoList, + &src_max_power, type)) return 1; if (init_vif_component_pd_sink_fields( - vif->Component[component_index].vif_field, - vif->Component[component_index].SnkPdoList, - type)) + vif->Component[component_index].vif_field, + vif->Component[component_index].SnkPdoList, type)) return 1; init_vif_component_pd_dual_role_fields( - vif->Component[component_index].vif_field, - type); + vif->Component[component_index].vif_field, type); init_vif_component_sop_discovery_fields( - vif->Component[component_index].vif_field); + vif->Component[component_index].vif_field); init_vif_component_bc_1_2_fields( - vif->Component[component_index].vif_field, - bc_support); + vif->Component[component_index].vif_field, bc_support); init_vif_component_product_power_fields( - vif->Component[component_index].vif_field, - src_max_power, - type); + vif->Component[component_index].vif_field, + src_max_power, type); } return 0; @@ -4005,14 +3872,11 @@ int main(int argc, char **argv) DIR *vifdir; char *name; int name_size; - const char * const short_opt = "hb:o:nv:"; + const char *const short_opt = "hb:o:nv:"; const struct option long_opts[] = { - { "help", 0, NULL, 'h' }, - { "board", 1, NULL, 'b' }, - { "out", 1, NULL, 'o' }, - { "no-config", 0, NULL, 'n' }, - { "over", 1, NULL, 'v' }, - { NULL } + { "help", 0, NULL, 'h' }, { "board", 1, NULL, 'b' }, + { "out", 1, NULL, 'o' }, { "no-config", 0, NULL, 'n' }, + { "over", 1, NULL, 'v' }, { NULL } }; /* Clear the VIF structure */ -- cgit v1.2.1 From bc6243652d432c24b37bf93f7e3f5ba3848f0d70 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:51 -0600 Subject: baseboard/goroh/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id442cab241ce21145fde74a9cb9be8b3fa0f1bfe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727511 Reviewed-by: Jeremy Bettis --- baseboard/goroh/baseboard.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/baseboard/goroh/baseboard.h b/baseboard/goroh/baseboard.h index c0246e9970..42f0e0f0a8 100644 --- a/baseboard/goroh/baseboard.h +++ b/baseboard/goroh/baseboard.h @@ -73,20 +73,20 @@ #define CONFIG_KEYBOARD_BACKLIGHT #define CONFIG_PWM_KBLIGHT #define CONFIG_KBLIGHT_ENABLE_PIN -#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X +#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_PPVAR_KB_BL_X /* I2C */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_PASSTHRU_RESTRICTED #define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define I2C_PORT_EEPROM IT83XX_I2C_CH_A #define I2C_PORT_CHARGER IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_A #define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_C0 IT83XX_I2C_CH_C +#define I2C_PORT_USB_C1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define CONFIG_SMBUS_PEC @@ -128,14 +128,14 @@ #define CONFIG_USB_PD_TCPMV2 #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_DETECT_PPC -#define CONFIG_USB_PID 0x5566 /* TODO: update PID */ +#define CONFIG_USB_PID 0x5566 /* TODO: update PID */ #define CONFIG_USB_POWER_DELIVERY #define PD_MAX_CURRENT_MA 3000 #define PD_MAX_VOLTAGE_MV 20000 #define PD_OPERATING_POWER_MW 15000 #define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* USB-A */ @@ -174,13 +174,13 @@ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* GPIO name remapping */ -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 7611b439ffaf669b1b3f8466c0b972a5eae2dd5b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:32 -0600 Subject: core/nds32/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I67b8db58b85a8aae8c96455fd038a99f4da0f9a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729863 Reviewed-by: Jeremy Bettis --- core/nds32/irq_handler.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/core/nds32/irq_handler.h b/core/nds32/irq_handler.h index 7e404b5d0c..db0a932021 100644 --- a/core/nds32/irq_handler.h +++ b/core/nds32/irq_handler.h @@ -15,12 +15,12 @@ * Macro to connect the interrupt handler "routine" to the irq number "irq" and * ensure it is enabled in the interrupt controller with the right priority. */ -#define DECLARE_IRQ(irq, routine, priority) \ - static void __keep routine(void); \ - void IRQ_HANDLER(CPU_INT(irq))(void) \ - __attribute__ ((alias(STRINGIFY(routine)))); \ - const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ - __attribute__((section(".rodata.irqprio"))) \ - = {CPU_INT(irq), priority} +#define DECLARE_IRQ(irq, routine, priority) \ + static void __keep routine(void); \ + void IRQ_HANDLER(CPU_INT(irq))(void) \ + __attribute__((alias(STRINGIFY(routine)))); \ + const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ + __attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \ + priority } -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From ec567eb7ec8437231fbadae0b77cec09a10fce66 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:51 -0600 Subject: board/goroh/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e09f0a95f690a25054b9c0ec213a331d9125d50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728429 Reviewed-by: Jeremy Bettis --- board/goroh/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/goroh/led.c b/board/goroh/led.c index 63f00ef82e..f4d8e0b5fb 100644 --- a/board/goroh/led.c +++ b/board/goroh/led.c @@ -9,13 +9,10 @@ #include "pwm.h" struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Green, Red */ - [EC_LED_COLOR_RED] = { 0, 100 }, - [EC_LED_COLOR_GREEN] = { 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 0 }, - [EC_LED_COLOR_AMBER] = { 0, 0 }, + /* Green, Red */ + [EC_LED_COLOR_RED] = { 0, 100 }, [EC_LED_COLOR_GREEN] = { 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 0 }, [EC_LED_COLOR_AMBER] = { 0, 0 }, }; struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = { -- cgit v1.2.1 From 63c04b5be090a8333484703551387029cd5f1174 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:20 -0600 Subject: zephyr/shim/src/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iebfd3ac2e93edb46663737cc57f47f8252f8e3ce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730846 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/adc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/src/adc.c b/zephyr/shim/src/adc.c index 80cf60391d..aafc97cec0 100644 --- a/zephyr/shim/src/adc.c +++ b/zephyr/shim/src/adc.c @@ -18,7 +18,7 @@ LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR); #define HAS_NAMED_ADC_CHANNELS DT_NODE_EXISTS(DT_INST(0, named_adc_channels)) #if HAS_NAMED_ADC_CHANNELS -#define ADC_CHANNEL_COMMA(node_id) \ +#define ADC_CHANNEL_COMMA(node_id) \ [ZSHIM_ADC_ID(node_id)] = { \ .name = DT_LABEL(node_id), \ .dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)), \ @@ -35,8 +35,8 @@ LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR); }, \ }, #ifdef CONFIG_ADC_CHANNELS_RUNTIME_CONFIG -struct adc_t adc_channels[] = { DT_FOREACH_CHILD( - DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) }; +struct adc_t adc_channels[] = { DT_FOREACH_CHILD(DT_INST(0, named_adc_channels), + ADC_CHANNEL_COMMA) }; #else const struct adc_t adc_channels[] = { DT_FOREACH_CHILD( DT_INST(0, named_adc_channels), ADC_CHANNEL_COMMA) }; -- cgit v1.2.1 From 481eec9a15aaf174330916259e831953eff953b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:20 -0600 Subject: board/nuwani/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb71b07c8aed2bd8ef6d12a6e817260846056cb4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728787 Reviewed-by: Jeremy Bettis --- board/nuwani/led.c | 53 ++++++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/board/nuwani/led.c b/board/nuwani/led.c index 76156d66d4..a926b7e2d8 100644 --- a/board/nuwani/led.c +++ b/board/nuwani/led.c @@ -8,40 +8,43 @@ #include "led_common.h" #include "gpio.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 49d05a736626c3f2fcf94aa4efbb9145f03d6cc9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:42 -0600 Subject: board/npcx_evb_arm/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib54062d0e360427c18b54125f156b6471d41bc57 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728772 Reviewed-by: Jeremy Bettis --- board/npcx_evb_arm/board.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/board/npcx_evb_arm/board.h b/board/npcx_evb_arm/board.h index a56cec9783..31a99da62e 100644 --- a/board/npcx_evb_arm/board.h +++ b/board/npcx_evb_arm/board.h @@ -15,13 +15,14 @@ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ -#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ +#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q64 #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard */ +#define CONFIG_KEYBOARD_PROTOCOL_MKBP /* Instead of 8042 protocol of keyboard \ + */ #define CONFIG_MKBP_USE_GPIO #define CONFIG_POWER_BUTTON #define CONFIG_VBOOT_HASH @@ -38,34 +39,29 @@ #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_I2CWEDGE -#define CONFIG_UART_HOST 0 -#define CONFIG_FANS 1 +#define CONFIG_UART_HOST 0 +#define CONFIG_FANS 1 /* Optional feature - used by nuvoton */ -#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Enable SHI PU on transition to S0. Disable the PU otherwise for leakage. */ #define NPCX_SHI_CS_PU /* Enable bypass since shi outputs invalid data when across 256B boundary */ #define NPCX_SHI_BYPASS_OVER_256B /* Optional for testing */ -#undef CONFIG_PSTORE -#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#undef CONFIG_PSTORE +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ /* Single I2C port, where the EC is the master. */ -#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 -#define I2C_PORT_HOST 0 +#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 +#define I2C_PORT_HOST 0 #ifndef __ASSEMBLER__ -enum adc_channel { - ADC_CH_0 = 0, - ADC_CH_1, - ADC_CH_2, - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_FAN, -- cgit v1.2.1 From 8b9f962fc940fcbc32a5036c6bfa8f3c9e21f68d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:42 -0600 Subject: common/usb_pd_protocol.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia133a1dd35c01af9fed99d9c521eee97c792998c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729776 Reviewed-by: Jeremy Bettis --- common/usb_pd_protocol.c | 1067 +++++++++++++++++++++++----------------------- 1 file changed, 537 insertions(+), 530 deletions(-) diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c index 3f0408eedf..946abf6395 100644 --- a/common/usb_pd_protocol.c +++ b/common/usb_pd_protocol.c @@ -38,27 +38,19 @@ #include "vboot.h" /* Flags to clear on a disconnect */ -#define PD_FLAGS_RESET_ON_DISCONNECT_MASK (PD_FLAGS_PARTNER_DR_POWER | \ - PD_FLAGS_PARTNER_DR_DATA | \ - PD_FLAGS_CHECK_IDENTITY | \ - PD_FLAGS_SNK_CAP_RECVD | \ - PD_FLAGS_TCPC_DRP_TOGGLE | \ - PD_FLAGS_EXPLICIT_CONTRACT | \ - PD_FLAGS_PREVIOUS_PD_CONN | \ - PD_FLAGS_CHECK_PR_ROLE | \ - PD_FLAGS_CHECK_DR_ROLE | \ - PD_FLAGS_PARTNER_UNCONSTR | \ - PD_FLAGS_VCONN_ON | \ - PD_FLAGS_TRY_SRC | \ - PD_FLAGS_PARTNER_USB_COMM | \ - PD_FLAGS_UPDATE_SRC_CAPS | \ - PD_FLAGS_TS_DTS_PARTNER | \ - PD_FLAGS_SNK_WAITING_BATT | \ - PD_FLAGS_CHECK_VCONN_STATE) +#define PD_FLAGS_RESET_ON_DISCONNECT_MASK \ + (PD_FLAGS_PARTNER_DR_POWER | PD_FLAGS_PARTNER_DR_DATA | \ + PD_FLAGS_CHECK_IDENTITY | PD_FLAGS_SNK_CAP_RECVD | \ + PD_FLAGS_TCPC_DRP_TOGGLE | PD_FLAGS_EXPLICIT_CONTRACT | \ + PD_FLAGS_PREVIOUS_PD_CONN | PD_FLAGS_CHECK_PR_ROLE | \ + PD_FLAGS_CHECK_DR_ROLE | PD_FLAGS_PARTNER_UNCONSTR | \ + PD_FLAGS_VCONN_ON | PD_FLAGS_TRY_SRC | PD_FLAGS_PARTNER_USB_COMM | \ + PD_FLAGS_UPDATE_SRC_CAPS | PD_FLAGS_TS_DTS_PARTNER | \ + PD_FLAGS_SNK_WAITING_BATT | PD_FLAGS_CHECK_VCONN_STATE) #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static int tcpc_prints(const char *string, int port) { @@ -105,11 +97,11 @@ static const int debug_level; #define DUAL_ROLE_IF_ELSE(port, sink_clause, src_clause) (src_clause) #endif -#define READY_RETURN_STATE(port) DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, \ - PD_STATE_SRC_READY) +#define READY_RETURN_STATE(port) \ + DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_READY, PD_STATE_SRC_READY) /* Type C supply voltage (mV) */ -#define TYPE_C_VOLTAGE 5000 /* mV */ +#define TYPE_C_VOLTAGE 5000 /* mV */ /* PD counter definitions */ #define PD_MESSAGE_ID_COUNT 7 @@ -153,8 +145,9 @@ enum vdm_states { #ifdef CONFIG_USB_PD_DUAL_ROLE /* Port dual-role state */ enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] = - CONFIG_USB_PD_INITIAL_DRP_STATE}; + [0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] = + CONFIG_USB_PD_INITIAL_DRP_STATE +}; /* Enable variable for Try.SRC states */ static bool pd_try_src_enable; @@ -183,8 +176,7 @@ static bool pd_try_src_enable; * Rev 1 (VDO 1.0) - return VDM_VER10 * Rev 2 (VDO 2.0) - return VDM_VER20 */ -static const uint8_t vdo_ver[] = { - VDM_VER10, VDM_VER10, VDM_VER20}; +static const uint8_t vdo_ver[] = { VDM_VER10, VDM_VER10, VDM_VER20 }; #define VDO_VER(v) vdo_ver[v] #else #define VDO_VER(v) VDM_VER10 @@ -277,7 +269,7 @@ static struct pd_protocol { /* Attached ChromeOS device id, RW hash, and current RO / RW image */ uint16_t dev_id; - uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4]; + uint32_t dev_rw_hash[PD_RW_HASH_SIZE / 4]; enum ec_image current_image; #ifdef CONFIG_USB_PD_REV30 /* protocol revision */ @@ -298,21 +290,44 @@ static struct pd_protocol { } pd[CONFIG_USB_PD_PORT_MAX_COUNT]; #ifdef CONFIG_USB_PD_TCPMV1_DEBUG -static const char * const pd_state_names[] = { - "DISABLED", "SUSPENDED", - "SNK_DISCONNECTED", "SNK_DISCONNECTED_DEBOUNCE", +static const char *const pd_state_names[] = { + "DISABLED", + "SUSPENDED", + "SNK_DISCONNECTED", + "SNK_DISCONNECTED_DEBOUNCE", "SNK_HARD_RESET_RECOVER", - "SNK_DISCOVERY", "SNK_REQUESTED", "SNK_TRANSITION", "SNK_READY", - "SNK_SWAP_INIT", "SNK_SWAP_SNK_DISABLE", - "SNK_SWAP_SRC_DISABLE", "SNK_SWAP_STANDBY", "SNK_SWAP_COMPLETE", - "SRC_DISCONNECTED", "SRC_DISCONNECTED_DEBOUNCE", - "SRC_HARD_RESET_RECOVER", "SRC_STARTUP", - "SRC_DISCOVERY", "SRC_NEGOCIATE", "SRC_ACCEPTED", "SRC_POWERED", - "SRC_TRANSITION", "SRC_READY", "SRC_GET_SNK_CAP", "DR_SWAP", - "SRC_SWAP_INIT", "SRC_SWAP_SNK_DISABLE", "SRC_SWAP_SRC_DISABLE", + "SNK_DISCOVERY", + "SNK_REQUESTED", + "SNK_TRANSITION", + "SNK_READY", + "SNK_SWAP_INIT", + "SNK_SWAP_SNK_DISABLE", + "SNK_SWAP_SRC_DISABLE", + "SNK_SWAP_STANDBY", + "SNK_SWAP_COMPLETE", + "SRC_DISCONNECTED", + "SRC_DISCONNECTED_DEBOUNCE", + "SRC_HARD_RESET_RECOVER", + "SRC_STARTUP", + "SRC_DISCOVERY", + "SRC_NEGOCIATE", + "SRC_ACCEPTED", + "SRC_POWERED", + "SRC_TRANSITION", + "SRC_READY", + "SRC_GET_SNK_CAP", + "DR_SWAP", + "SRC_SWAP_INIT", + "SRC_SWAP_SNK_DISABLE", + "SRC_SWAP_SRC_DISABLE", "SRC_SWAP_STANDBY", - "VCONN_SWAP_SEND", "VCONN_SWAP_INIT", "VCONN_SWAP_READY", - "SOFT_RESET", "HARD_RESET_SEND", "HARD_RESET_EXECUTE", "BIST_RX", + "VCONN_SWAP_SEND", + "VCONN_SWAP_INIT", + "VCONN_SWAP_READY", + "SOFT_RESET", + "HARD_RESET_SEND", + "HARD_RESET_EXECUTE", + "BIST_RX", "BIST_TX", "DRP_AUTO_TOGGLE", "ENTER_USB", @@ -336,11 +351,10 @@ bool pd_alt_mode_capable(int port) * the port is not suspended. */ return pd_comm_is_enabled(port) && - !(pd[port].task_state == PD_STATE_SUSPENDED); + !(pd[port].task_state == PD_STATE_SUSPENDED); } -static inline void set_state_timeout(int port, - uint64_t timeout, +static inline void set_state_timeout(int port, uint64_t timeout, enum pd_states timeout_state) { pd[port].timeout = timeout; @@ -385,13 +399,16 @@ int pd_is_connected(int port) return 0; #endif - return DUAL_ROLE_IF_ELSE(port, + return DUAL_ROLE_IF_ELSE( + port, /* sink */ pd[port].task_state != PD_STATE_SNK_DISCONNECTED && - pd[port].task_state != PD_STATE_SNK_DISCONNECTED_DEBOUNCE, + pd[port].task_state != + PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* source */ pd[port].task_state != PD_STATE_SRC_DISCONNECTED && - pd[port].task_state != PD_STATE_SRC_DISCONNECTED_DEBOUNCE); + pd[port].task_state != + PD_STATE_SRC_DISCONNECTED_DEBOUNCE); } /* Return true if partner port is known to be PD capable. */ @@ -425,7 +442,6 @@ void pd_vbus_low(int port) } #endif - #ifdef CONFIG_USBC_VCONN static void set_vconn(int port, int enable) { @@ -485,12 +501,12 @@ static void handle_device_access(int port) pd[port].low_power_time = get_time().val + PD_LPM_DEBOUNCE_US; if (pd[port].flags & PD_FLAGS_LPM_ENGAGED) { tcpc_prints("Exit Low Power Mode", port); - pd[port].flags &= ~(PD_FLAGS_LPM_ENGAGED | - PD_FLAGS_LPM_REQUESTED); + pd[port].flags &= + ~(PD_FLAGS_LPM_ENGAGED | PD_FLAGS_LPM_REQUESTED); pd[port].flags |= PD_FLAGS_LPM_EXIT; - pd[port].low_power_exit_time = get_time().val - + PD_LPM_EXIT_DEBOUNCE_US; + pd[port].low_power_exit_time = + get_time().val + PD_LPM_EXIT_DEBOUNCE_US; /* * Wake to ensure we make another pass through the main task * loop after clearing the flags. @@ -696,7 +712,6 @@ static bool consume_repeat_message(int port, uint32_t msg_header) } else { return consume_sop_repeat_message(port, msg_id); } - } /** @@ -798,8 +813,7 @@ static inline void set_state(int port, enum pd_states next_state) pd_set_input_current_limit(port, 0, 0); #ifdef CONFIG_CHARGE_MANAGER typec_set_input_current_limit(port, 0, 0); - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE); #endif #ifdef CONFIG_BC12_DETECT_DATA_ROLE_TRIGGER @@ -868,7 +882,7 @@ static inline void set_state(int port, enum pd_states next_state) /* Upon entering SRC_READY, it is safe for the sink to transmit */ if (next_state == PD_STATE_SRC_READY) { if (pd[port].rev == PD_REV30 && - pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT) + pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT) sink_can_xmit(port, SINK_TX_OK); } #endif @@ -888,7 +902,7 @@ static inline void set_state(int port, enum pd_states next_state) #ifdef CONFIG_USB_PD_TCPMV1_DEBUG if (debug_level > 0) CPRINTF("C%d st%d %s\n", port, next_state, - pd_state_names[next_state]); + pd_state_names[next_state]); else #endif CPRINTF("C%d st%d\n", port, next_state); @@ -909,8 +923,8 @@ void pd_transmit_complete(int port, int status) task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TX); } -static int pd_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data, enum ams_seq ams) +static int pd_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data, enum ams_seq ams) { int evt; int res; @@ -922,9 +936,9 @@ static int pd_transmit(int port, enum tcpci_msg_type type, if (!pd_comm_is_enabled(port)) return -1; - /* Don't try to transmit anything until we have processed - * all RX messages. - */ + /* Don't try to transmit anything until we have processed + * all RX messages. + */ if (tcpm_has_pending_message(port)) return -1; @@ -951,7 +965,7 @@ static int pd_transmit(int port, enum tcpci_msg_type type, * Note: a Sink can still send Hard Reset signaling at any time. */ if ((pd[port].rev == PD_REV30) && ams == AMS_START && - (pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) { + (pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT)) { if (pd[port].power_role == PD_ROLE_SOURCE) { /* * Inform Sink that it can't transmit. If a sink @@ -967,7 +981,7 @@ static int pd_transmit(int port, enum tcpci_msg_type type, tcpm_get_cc(port, &cc1, &cc2); if (cc1 == TYPEC_CC_VOLT_RP_1_5 || - cc2 == TYPEC_CC_VOLT_RP_1_5) { + cc2 == TYPEC_CC_VOLT_RP_1_5) { /* Sink can't transmit now. */ /* Return failure, pd_task can retry later */ return -1; @@ -1004,15 +1018,15 @@ static int send_control(int port, int type) { int bit_len; uint16_t header = PD_HEADER(type, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, 0, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, 0, + pd_get_rev(port, TCPCI_MSG_SOP), 0); /* * For PD 3.0, collision avoidance logic needs to know if this message * will begin a new Atomic Message Sequence (AMS) */ - enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK) - ? AMS_START : AMS_RESPONSE; - + enum ams_seq ams = ((1 << type) & PD_CTRL_AMS_START_MASK) ? + AMS_START : + AMS_RESPONSE; bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, NULL, ams); if (debug_level >= 2) @@ -1030,7 +1044,7 @@ static int send_source_cap(int port, enum ams_seq ams) { int bit_len; #if defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \ - defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) + defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) const uint32_t *src_pdo; const int src_pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port); #else @@ -1042,12 +1056,13 @@ static int send_source_cap(int port, enum ams_seq ams) if (src_pdo_cnt == 0) /* No source capabilities defined, sink only */ header = PD_HEADER(PD_CTRL_REJECT, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, 0, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, 0, + pd_get_rev(port, TCPCI_MSG_SOP), 0); else header = PD_HEADER(PD_DATA_SOURCE_CAP, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, src_pdo_cnt, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, + src_pdo_cnt, pd_get_rev(port, TCPCI_MSG_SOP), + 0); bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, src_pdo, ams); if (debug_level >= 2) @@ -1060,21 +1075,19 @@ static int send_source_cap(int port, enum ams_seq ams) static int send_battery_cap(int port, uint32_t *payload) { int bit_len; - uint16_t msg[6] = {0, 0, 0, 0, 0, 0}; - uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP, - pd[port].power_role, - pd[port].data_role, - pd[port].msg_id, + uint16_t msg[6] = { 0, 0, 0, 0, 0, 0 }; + uint16_t header = PD_HEADER(PD_EXT_BATTERY_CAP, pd[port].power_role, + pd[port].data_role, pd[port].msg_id, 3, /* Number of Data Objects */ - pd[port].rev, - 1 /* This is an exteded message */ - ); + pd[port].rev, 1 /* This is an exteded + message */ + ); /* Set extended header */ msg[0] = PD_EXT_HEADER(0, /* Chunk Number */ 0, /* Request Chunk */ - 9 /* Data Size in bytes */ - ); + 9 /* Data Size in bytes */ + ); /* Set VID */ msg[1] = USB_VID_GOOGLE; @@ -1121,7 +1134,7 @@ static int send_battery_cap(int port, uint32_t *payload) * 10th of a Wh = Wh * 10 */ msg[3] = DIV_ROUND_NEAREST((c * v), - 100000); + 100000); } if (battery_full_charge_capacity(&c) == 0) { @@ -1130,7 +1143,7 @@ static int send_battery_cap(int port, uint32_t *payload) * 10th of a Wh = Wh * 10 */ msg[4] = DIV_ROUND_NEAREST((c * v), - 100000); + 100000); } } } @@ -1143,18 +1156,16 @@ static int send_battery_cap(int port, uint32_t *payload) return bit_len; } -static int send_battery_status(int port, uint32_t *payload) +static int send_battery_status(int port, uint32_t *payload) { int bit_len; uint32_t msg = 0; - uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS, - pd[port].power_role, - pd[port].data_role, - pd[port].msg_id, + uint16_t header = PD_HEADER(PD_DATA_BATTERY_STATUS, pd[port].power_role, + pd[port].data_role, pd[port].msg_id, 1, /* Number of Data Objects */ - pd[port].rev, - 0 /* This is NOT an extended message */ - ); + pd[port].rev, 0 /* This is NOT an extended + message */ + ); if (battery_is_present()) { /* @@ -1169,15 +1180,15 @@ static int send_battery_status(int port, uint32_t *payload) uint32_t c; if (battery_design_voltage(&v) != 0 || - battery_remaining_capacity(&c) != 0) { + battery_remaining_capacity(&c) != 0) { msg |= BSDO_CAP(BSDO_CAP_UNKNOWN); } else { /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ - msg |= BSDO_CAP(DIV_ROUND_NEAREST((c * v), - 100000)); + msg |= BSDO_CAP( + DIV_ROUND_NEAREST((c * v), 100000)); } /* Battery is present */ @@ -1217,8 +1228,9 @@ static void send_sink_cap(int port) { int bit_len; uint16_t header = PD_HEADER(PD_DATA_SINK_CAP, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, pd_snk_pdo_cnt, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, + pd_snk_pdo_cnt, + pd_get_rev(port, TCPCI_MSG_SOP), 0); bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, pd_snk_pdo, AMS_RESPONSE); @@ -1230,8 +1242,8 @@ static int send_request(int port, uint32_t rdo) { int bit_len; uint16_t header = PD_HEADER(PD_DATA_REQUEST, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, 1, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, 1, + pd_get_rev(port, TCPCI_MSG_SOP), 0); /* Note: ams will need to be AMS_START if used for PPS keep alive */ bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &rdo, AMS_RESPONSE); @@ -1250,8 +1262,8 @@ static int send_bist_cmd(int port) uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0); int bit_len; uint16_t header = PD_HEADER(PD_DATA_BIST, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, 1, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, 1, + pd_get_rev(port, TCPCI_MSG_SOP), 0); bit_len = pd_transmit(port, TCPCI_MSG_SOP, header, &bdo, AMS_START); CPRINTF("C%d BIST>%d\n", port, bit_len); @@ -1261,19 +1273,18 @@ static int send_bist_cmd(int port) #endif static void queue_vdm(int port, uint32_t *header, const uint32_t *data, - int data_cnt, enum tcpci_msg_type type) + int data_cnt, enum tcpci_msg_type type) { pd[port].vdo_count = data_cnt + 1; pd[port].vdo_data[0] = header[0]; pd[port].xmit_type = type; - memcpy(&pd[port].vdo_data[1], data, - sizeof(uint32_t) * data_cnt); + memcpy(&pd[port].vdo_data[1], data, sizeof(uint32_t) * data_cnt); /* Set ready, pd task will actually send */ pd[port].vdm_state = VDM_STATE_READY; } static void handle_vdm_request(int port, int cnt, uint32_t *payload, - uint32_t head) + uint32_t head) { int rlen = 0; uint32_t *rdata; @@ -1282,11 +1293,11 @@ static void handle_vdm_request(int port, int cnt, uint32_t *payload, if (pd[port].vdm_state == VDM_STATE_BUSY) { /* If UFP responded busy retry after timeout */ if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_BUSY) { - pd[port].vdm_timeout.val = get_time().val + - PD_T_VDM_BUSY; + pd[port].vdm_timeout.val = + get_time().val + PD_T_VDM_BUSY; pd[port].vdm_state = VDM_STATE_WAIT_RSP_BUSY; pd[port].vdo_retry = (payload[0] & ~VDO_CMDT_MASK) | - CMDT_INIT; + CMDT_INIT; return; } else { pd[port].vdm_state = VDM_STATE_DONE; @@ -1310,8 +1321,8 @@ static void handle_vdm_request(int port, int cnt, uint32_t *payload, } if (debug_level >= 2) - CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n", - port, PD_VDO_VID(payload[0]), payload[0] & 0xFFFF); + CPRINTF("C%d Unhandled VDM VID %04x CMD %04x\n", port, + PD_VDO_VID(payload[0]), payload[0] & 0xFFFF); } bool pd_is_disconnected(int port) @@ -1401,8 +1412,7 @@ void pd_execute_hard_reset(int port) /* Clear the input current limit */ pd_set_input_current_limit(port, 0, 0); #ifdef CONFIG_CHARGE_MANAGER - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE); #endif /* CONFIG_CHARGE_MANAGER */ @@ -1442,7 +1452,7 @@ static void execute_soft_reset(int port) { invalidate_last_message_id(port); set_state(port, DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCOVERY, - PD_STATE_SRC_DISCOVERY)); + PD_STATE_SRC_DISCOVERY)); CPRINTF("C%d Soft Rst\n", port); } @@ -1484,8 +1494,8 @@ static int pd_send_request_msg(int port, int always_send_request) #endif } - CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo), - supply_voltage, curr_limit); + CPRINTF("C%d Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage, + curr_limit); if (rdo & RDO_CAP_MISMATCH) CPRINTF(" Mismatch"); CPRINTF("\n"); @@ -1543,8 +1553,7 @@ static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos) * Get max power that the partner offers (not necessarily what * this board will request) */ - pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, - &max_pdo); + pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, &max_pdo); pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused); max_mw = max_ma * max_mv / 1000; @@ -1557,8 +1566,7 @@ static void pd_update_pdo_flags(int port, int pdo_cnt, uint32_t *pdos) } } -static void handle_data_request(int port, uint32_t head, - uint32_t *payload) +static void handle_data_request(int port, uint32_t head, uint32_t *payload) { int type = PD_HEADER_TYPE(head); int cnt = PD_HEADER_CNT(head); @@ -1566,14 +1574,12 @@ static void handle_data_request(int port, uint32_t head, switch (type) { #ifdef CONFIG_USB_PD_DUAL_ROLE case PD_DATA_SOURCE_CAP: - if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY) - || (pd[port].task_state == PD_STATE_SNK_TRANSITION) - || (pd[port].task_state == PD_STATE_SNK_REQUESTED) - || ((get_usb_pd_vbus_detect() == - USB_PD_VBUS_DETECT_NONE) - && (pd[port].task_state == - PD_STATE_SNK_HARD_RESET_RECOVER)) - || (pd[port].task_state == PD_STATE_SNK_READY)) { + if ((pd[port].task_state == PD_STATE_SNK_DISCOVERY) || + (pd[port].task_state == PD_STATE_SNK_TRANSITION) || + (pd[port].task_state == PD_STATE_SNK_REQUESTED) || + ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_NONE) && + (pd[port].task_state == PD_STATE_SNK_HARD_RESET_RECOVER)) || + (pd[port].task_state == PD_STATE_SNK_READY)) { #ifdef CONFIG_USB_PD_REV30 /* * Only adjust sink rev if source rev is higher. @@ -1630,18 +1636,20 @@ static void handle_data_request(int port, uint32_t head, break; case PD_DATA_BIST: /* If not in READY state, then don't start BIST */ - if (DUAL_ROLE_IF_ELSE(port, - pd[port].task_state == PD_STATE_SNK_READY, - pd[port].task_state == PD_STATE_SRC_READY)) { + if (DUAL_ROLE_IF_ELSE( + port, pd[port].task_state == PD_STATE_SNK_READY, + pd[port].task_state == PD_STATE_SRC_READY)) { /* currently only support sending bist carrier mode 2 */ if ((payload[0] >> 28) == 5) { /* bist data object mode is 2 */ pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL, AMS_RESPONSE); /* Set to appropriate port disconnected state */ - set_state(port, DUAL_ROLE_IF_ELSE(port, - PD_STATE_SNK_DISCONNECTED, - PD_STATE_SRC_DISCONNECTED)); + set_state(port, + DUAL_ROLE_IF_ELSE( + port, + PD_STATE_SNK_DISCONNECTED, + PD_STATE_SRC_DISCONNECTED)); } } break; @@ -1655,12 +1663,12 @@ static void handle_data_request(int port, uint32_t head, #ifdef CONFIG_USB_PD_REV30 case PD_DATA_BATTERY_STATUS: break; - /* TODO : Add case PD_DATA_RESET for exiting USB4 */ + /* TODO : Add case PD_DATA_RESET for exiting USB4 */ - /* - * TODO : Add case PD_DATA_ENTER_USB to accept or reject - * Enter_USB request from port partner. - */ + /* + * TODO : Add case PD_DATA_ENTER_USB to accept or reject + * Enter_USB request from port partner. + */ #endif case PD_DATA_VENDOR_DEF: handle_vdm_request(port, cnt, payload, head); @@ -1705,9 +1713,8 @@ void pd_try_vconn_src(int port) void pd_request_data_swap(int port) { - if (DUAL_ROLE_IF_ELSE(port, - pd[port].task_state == PD_STATE_SNK_READY, - pd[port].task_state == PD_STATE_SRC_READY)) + if (DUAL_ROLE_IF_ELSE(port, pd[port].task_state == PD_STATE_SNK_READY, + pd[port].task_state == PD_STATE_SRC_READY)) set_state(port, PD_STATE_DR_SWAP); task_wake(PD_PORT_TO_TASK_ID(port)); } @@ -1726,8 +1733,7 @@ static void pd_dr_swap(int port) pd[port].flags |= PD_FLAGS_CHECK_IDENTITY; } -static void handle_ctrl_request(int port, uint32_t head, - uint32_t *payload) +static void handle_ctrl_request(int port, uint32_t head, uint32_t *payload) { int type = PD_HEADER_TYPE(head); int res; @@ -1768,7 +1774,7 @@ static void handle_ctrl_request(int port, uint32_t head, * later time. */ pd_snk_give_back(port, &pd[port].curr_limit, - &pd[port].supply_voltage); + &pd[port].supply_voltage); set_state(port, PD_STATE_SNK_TRANSITION); } #endif @@ -1813,16 +1819,15 @@ static void handle_ctrl_request(int port, uint32_t head, */ if (pd[port].task_state == PD_STATE_SNK_TRANSITION) pd[port].ready_state_holdoff_timer = - get_time().val + SNK_READY_HOLD_OFF_US - + (get_time().le.lo & 0xf) * 12 * MSEC; + get_time().val + SNK_READY_HOLD_OFF_US + + (get_time().le.lo & 0xf) * 12 * MSEC; set_state(port, PD_STATE_SNK_READY); pd_set_input_current_limit(port, pd[port].curr_limit, pd[port].supply_voltage); #ifdef CONFIG_CHARGE_MANAGER /* Set ceiling based on what's negotiated */ - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, pd[port].curr_limit); #endif } @@ -1839,7 +1844,7 @@ static void handle_ctrl_request(int port, uint32_t head, * recieveing a NACK. */ usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, pd[port].polarity); + USB_SWITCH_CONNECT, pd[port].polarity); set_state(port, READY_RETURN_STATE(port)); break; @@ -1898,9 +1903,9 @@ static void handle_ctrl_request(int port, uint32_t head, const int in_contract = pd[port].flags & PD_FLAGS_EXPLICIT_CONTRACT; - set_state(port, - in_contract ? PD_STATE_SNK_READY - : PD_STATE_SNK_DISCOVERY); + set_state(port, in_contract ? + PD_STATE_SNK_READY : + PD_STATE_SNK_DISCOVERY); } } #endif @@ -1916,7 +1921,7 @@ static void handle_ctrl_request(int port, uint32_t head, /* Set usb mux to USB4 mode */ usb_mux_set(port, USB_PD_MUX_USB4_ENABLED, - USB_SWITCH_CONNECT, pd[port].polarity); + USB_SWITCH_CONNECT, pd[port].polarity); set_state(port, READY_RETURN_STATE(port)); } else if (pd[port].task_state == PD_STATE_SOFT_RESET) { @@ -1939,23 +1944,20 @@ static void handle_ctrl_request(int port, uint32_t head, } else if (pd[port].task_state == PD_STATE_SRC_SWAP_INIT) { /* explicit contract goes away for power swap */ pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT; - pd_update_saved_port_flags(port, - PD_BBRMFLG_EXPLICIT_CONTRACT, - 0); + pd_update_saved_port_flags( + port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0); set_state(port, PD_STATE_SRC_SWAP_SNK_DISABLE); } else if (pd[port].task_state == PD_STATE_SNK_SWAP_INIT) { /* explicit contract goes away for power swap */ pd[port].flags &= ~PD_FLAGS_EXPLICIT_CONTRACT; - pd_update_saved_port_flags(port, - PD_BBRMFLG_EXPLICIT_CONTRACT, - 0); + pd_update_saved_port_flags( + port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0); set_state(port, PD_STATE_SNK_SWAP_SNK_DISABLE); } else if (pd[port].task_state == PD_STATE_SNK_REQUESTED) { /* explicit contract is now in place */ pd[port].flags |= PD_FLAGS_EXPLICIT_CONTRACT; - pd_update_saved_port_flags(port, - PD_BBRMFLG_EXPLICIT_CONTRACT, - 1); + pd_update_saved_port_flags( + port, PD_BBRMFLG_EXPLICIT_CONTRACT, 1); set_state(port, PD_STATE_SNK_TRANSITION); #endif } @@ -1976,9 +1978,9 @@ static void handle_ctrl_request(int port, uint32_t head, */ pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE; set_state(port, - DUAL_ROLE_IF_ELSE(port, - PD_STATE_SNK_SWAP_SNK_DISABLE, - PD_STATE_SRC_SWAP_SNK_DISABLE)); + DUAL_ROLE_IF_ELSE( + port, PD_STATE_SNK_SWAP_SNK_DISABLE, + PD_STATE_SRC_SWAP_SNK_DISABLE)); } else { send_control(port, PD_CTRL_REJECT); } @@ -1998,7 +2000,6 @@ static void handle_ctrl_request(int port, uint32_t head, pd_dr_swap(port); } else { send_control(port, PD_CTRL_REJECT); - } break; case PD_CTRL_VCONN_SWAP: @@ -2045,8 +2046,7 @@ static void handle_ext_request(int port, uint16_t head, uint32_t *payload) } #endif -static void handle_request(int port, uint32_t head, - uint32_t *payload) +static void handle_request(int port, uint32_t head, uint32_t *payload) { int cnt = PD_HEADER_CNT(head); int data_role = PD_HEADER_DROLE(head); @@ -2091,8 +2091,7 @@ static void handle_request(int port, uint32_t head, TYPEC_CC_RP)); } set_state(port, - DUAL_ROLE_IF_ELSE(port, - PD_STATE_SNK_DISCONNECTED, + DUAL_ROLE_IF_ELSE(port, PD_STATE_SNK_DISCONNECTED, PD_STATE_SRC_DISCONNECTED)); return; } @@ -2119,8 +2118,11 @@ void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data, } /* set VDM header with VID & CMD */ - pd[port].vdo_data[0] = VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ? - 1 : (PD_VDO_CMD(cmd) <= CMD_ATTENTION), cmd); + pd[port].vdo_data[0] = VDO(vid, + ((vid & USB_SID_PD) == USB_SID_PD) ? + 1 : + (PD_VDO_CMD(cmd) <= CMD_ATTENTION), + cmd); #ifdef CONFIG_USB_PD_REV30 pd[port].vdo_data[0] |= VDO_SVDM_VERS(vdo_ver[pd[port].rev]); #endif @@ -2150,7 +2152,7 @@ static uint64_t vdm_get_ready_timeout(uint32_t vdm_hdr) /* its not a structured VDM command */ if (!PD_VDO_SVDM(vdm_hdr)) - return 500*MSEC; + return 500 * MSEC; switch (PD_VDO_CMDT(vdm_hdr)) { case CMDT_INIT: @@ -2194,18 +2196,18 @@ static void exit_tbt_mode_sop_prime(int port) return; header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role, - pd[port].data_role, pd[port].msg_id, - (int)pd[port].vdo_count, - pd_get_rev(port, TCPCI_MSG_SOP), 0); + pd[port].data_role, pd[port].msg_id, + (int)pd[port].vdo_count, + pd_get_rev(port, TCPCI_MSG_SOP), 0); - pd[port].vdo_data[0] = VDO(USB_VID_INTEL, 1, - CMD_EXIT_MODE | VDO_OPOS(opos)); + pd[port].vdo_data[0] = + VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE | VDO_OPOS(opos)); pd_transmit(port, TCPCI_MSG_SOP_PRIME, header, pd[port].vdo_data, AMS_START); usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); } static void pd_vdm_send_state_machine(int port) @@ -2243,14 +2245,11 @@ static void pd_vdm_send_state_machine(int port) if ((msg_type == TCPCI_MSG_SOP_PRIME) || (msg_type == TCPCI_MSG_SOP_PRIME_PRIME)) { /* Prepare SOP'/SOP'' header and send VDM */ - header = PD_HEADER( - PD_DATA_VENDOR_DEF, - PD_PLUG_FROM_DFP_UFP, - 0, - pd[port].msg_id, - (int)pd[port].vdo_count, - pd_get_rev(port, TCPCI_MSG_SOP), - 0); + header = PD_HEADER(PD_DATA_VENDOR_DEF, + PD_PLUG_FROM_DFP_UFP, 0, + pd[port].msg_id, + (int)pd[port].vdo_count, + pd_get_rev(port, TCPCI_MSG_SOP), 0); res = pd_transmit(port, msg_type, header, pd[port].vdo_data, AMS_START); /* @@ -2268,21 +2267,19 @@ static void pd_vdm_send_state_machine(int port) * mode. */ if (res < 0) { - header = PD_HEADER(PD_DATA_VENDOR_DEF, - pd[port].power_role, - pd[port].data_role, - pd[port].msg_id, - (int)pd[port].vdo_count, - pd_get_rev - (port, TCPCI_MSG_SOP), - 0); + header = PD_HEADER( + PD_DATA_VENDOR_DEF, pd[port].power_role, + pd[port].data_role, pd[port].msg_id, + (int)pd[port].vdo_count, + pd_get_rev(port, TCPCI_MSG_SOP), 0); if ((msg_type == TCPCI_MSG_SOP_PRIME_PRIME) && - IS_ENABLED(CONFIG_USBC_SS_MUX)) { + IS_ENABLED(CONFIG_USBC_SS_MUX)) { exit_tbt_mode_sop_prime(port); } else if (msg_type == TCPCI_MSG_SOP_PRIME) { - pd[port].vdo_data[0] = VDO(USB_SID_PD, - 1, CMD_DISCOVER_SVID); + pd[port].vdo_data[0] = + VDO(USB_SID_PD, 1, + CMD_DISCOVER_SVID); } res = pd_transmit(port, TCPCI_MSG_SOP, header, pd[port].vdo_data, AMS_START); @@ -2292,8 +2289,7 @@ static void pd_vdm_send_state_machine(int port) /* Prepare SOP header and send VDM */ header = PD_HEADER(PD_DATA_VENDOR_DEF, pd[port].power_role, - pd[port].data_role, - pd[port].msg_id, + pd[port].data_role, pd[port].msg_id, (int)pd[port].vdo_count, pd_get_rev(port, TCPCI_MSG_SOP), 0); res = pd_transmit(port, TCPCI_MSG_SOP, header, @@ -2304,7 +2300,8 @@ static void pd_vdm_send_state_machine(int port) pd[port].vdm_state = VDM_STATE_ERR_SEND; } else { pd[port].vdm_state = VDM_STATE_BUSY; - pd[port].vdm_timeout.val = get_time().val + + pd[port].vdm_timeout.val = + get_time().val + vdm_get_ready_timeout(pd[port].vdo_data[0]); } break; @@ -2366,15 +2363,14 @@ int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash, /* Search table for matching device / hash */ for (i = 0; i < RW_HASH_ENTRIES; i++) if (dev_id == rw_hash_table[i].dev_id) - return !memcmp(rw_hash, - rw_hash_table[i].dev_rw_hash, + return !memcmp(rw_hash, rw_hash_table[i].dev_rw_hash, PD_RW_HASH_SIZE); #endif return 0; } void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash, - uint32_t *current_image) + uint32_t *current_image) { *dev_id = pd[port].dev_id; *current_image = pd[port].current_image; @@ -2391,10 +2387,11 @@ __maybe_unused static void exit_supported_alt_mode(int port) for (i = 0; i < supported_modes_cnt; i++) { int opos = pd_alt_mode(port, TCPCI_MSG_SOP, - supported_modes[i].svid); + supported_modes[i].svid); - if (opos > 0 && pd_dfp_exit_mode(port, TCPCI_MSG_SOP, - supported_modes[i].svid, opos)) { + if (opos > 0 && + pd_dfp_exit_mode(port, TCPCI_MSG_SOP, + supported_modes[i].svid, opos)) { CPRINTS("C%d Exiting ALT mode with SVID = 0x%x", port, supported_modes[i].svid); usb_mux_set_safe_mode(port); @@ -2409,7 +2406,6 @@ __maybe_unused static void exit_supported_alt_mode(int port) #ifdef CONFIG_POWER_COMMON static void handle_new_power_state(int port) { - if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) { /* * The SoC will negotiate the alternate mode again when @@ -2473,8 +2469,8 @@ static void pd_update_snk_reset(void) if (pd[i].task_state == PD_STATE_SNK_DISCOVERY) { CPRINTS("C%d: Starting soft reset timer", i); - set_state_timeout(i, - get_time().val + PD_T_SINK_WAIT_CAP, + set_state_timeout( + i, get_time().val + PD_T_SINK_WAIT_CAP, PD_STATE_SOFT_RESET); } } @@ -2518,13 +2514,13 @@ void pd_set_dual_role(int port, enum pd_dual_role_states state) static int pd_is_power_swapping(int port) { /* return true if in the act of swapping power roles */ - return pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE || - pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE || - pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY || - pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE || - pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE || - pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE || - pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY; + return pd[port].task_state == PD_STATE_SNK_SWAP_SNK_DISABLE || + pd[port].task_state == PD_STATE_SNK_SWAP_SRC_DISABLE || + pd[port].task_state == PD_STATE_SNK_SWAP_STANDBY || + pd[port].task_state == PD_STATE_SNK_SWAP_COMPLETE || + pd[port].task_state == PD_STATE_SRC_SWAP_SNK_DISABLE || + pd[port].task_state == PD_STATE_SRC_SWAP_SRC_DISABLE || + pd[port].task_state == PD_STATE_SRC_SWAP_STANDBY; } /* This must only be called from the PD task */ @@ -2536,9 +2532,9 @@ static void pd_update_dual_role_config(int port) * source disconnected state). */ if (pd[port].power_role == PD_ROLE_SOURCE && - (drp_state[port] == PD_DRP_FORCE_SINK - || (drp_state[port] == PD_DRP_TOGGLE_OFF - && pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) { + (drp_state[port] == PD_DRP_FORCE_SINK || + (drp_state[port] == PD_DRP_TOGGLE_OFF && + pd[port].task_state == PD_STATE_SRC_DISCONNECTED))) { pd_set_power_role(port, PD_ROLE_SINK); set_state(port, PD_STATE_SNK_DISCONNECTED); tcpm_set_cc(port, TYPEC_CC_RD); @@ -2695,8 +2691,7 @@ void pd_comm_enable(int port, int enable) * any port in PD_SNK_DISCOVERY. */ if (enable && pd[port].task_state == PD_STATE_SNK_DISCOVERY) - set_state_timeout(port, - get_time().val + PD_T_SINK_WAIT_CAP, + set_state_timeout(port, get_time().val + PD_T_SINK_WAIT_CAP, PD_STATE_HARD_RESET_SEND); #endif } @@ -2811,25 +2806,19 @@ static void pd_send_enter_usb(int port, int *timeout) usb4_payload = get_enter_usb_msg_payload(port); - header = PD_HEADER(PD_DATA_ENTER_USB, - pd[port].power_role, - pd[port].data_role, - pd[port].msg_id, - 1, - PD_REV30, - 0); + header = PD_HEADER(PD_DATA_ENTER_USB, pd[port].power_role, + pd[port].data_role, pd[port].msg_id, 1, PD_REV30, 0); res = pd_transmit(port, TCPCI_MSG_SOP, header, &usb4_payload, - AMS_START); + AMS_START); if (res < 0) { - *timeout = 10*MSEC; + *timeout = 10 * MSEC; /* * If failed to get goodCRC, send soft reset, otherwise ignore * failure. */ - set_state(port, res == -1 ? - PD_STATE_SOFT_RESET : - READY_RETURN_STATE(port)); + set_state(port, res == -1 ? PD_STATE_SOFT_RESET : + READY_RETURN_STATE(port)); return; } @@ -2844,7 +2833,7 @@ void pd_task(void *u) uint32_t head; int port = TASK_ID_TO_PD_PORT(task_get_current()); uint32_t payload[7]; - int timeout = 10*MSEC; + int timeout = 10 * MSEC; enum tcpc_cc_voltage_status cc1, cc2; int res, incoming_packet = 0; int hard_reset_count = 0; @@ -2922,8 +2911,7 @@ void pd_task(void *u) if (!res) { struct ec_response_pd_chip_info_v1 info; - if (tcpm_get_chip_info(port, 0, &info) == - EC_SUCCESS) { + if (tcpm_get_chip_info(port, 0, &info) == EC_SUCCESS) { CPRINTS("TCPC p%d VID:0x%x PID:0x%x DID:0x%x " "FWV:0x%" PRIx64, port, info.vendor_id, info.product_id, @@ -2943,8 +2931,8 @@ void pd_task(void *u) * present. This flag is used to maintain a PD connection after a * reset by sending a soft reset. */ - pd[port].flags |= - pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW : 0; + pd[port].flags |= pd_is_vbus_present(port) ? PD_FLAGS_VBUS_NEVER_LOW : + 0; #endif /* Disable TCPC RX until connection is established */ @@ -2968,14 +2956,17 @@ void pd_task(void *u) if ((saved_flgs & PD_BBRMFLG_POWER_ROLE) == PD_ROLE_SINK) { pd_set_power_role(port, (saved_flgs & PD_BBRMFLG_POWER_ROLE) ? - PD_ROLE_SOURCE : PD_ROLE_SINK); + PD_ROLE_SOURCE : + PD_ROLE_SINK); pd_set_data_role(port, (saved_flgs & PD_BBRMFLG_DATA_ROLE) ? - PD_ROLE_DFP : PD_ROLE_UFP); + PD_ROLE_DFP : + PD_ROLE_UFP); #ifdef CONFIG_USBC_VCONN pd_set_vconn_role(port, (saved_flgs & PD_BBRMFLG_VCONN_ROLE) ? - PD_ROLE_VCONN_ON : PD_ROLE_VCONN_OFF); + PD_ROLE_VCONN_ON : + PD_ROLE_VCONN_OFF); #endif /* CONFIG_USBC_VCONN */ /* @@ -2997,9 +2988,8 @@ void pd_task(void *u) * earlier, so clear the contract flag and re-start as * default role */ - pd_update_saved_port_flags(port, - PD_BBRMFLG_EXPLICIT_CONTRACT, 0); - + pd_update_saved_port_flags( + port, PD_BBRMFLG_EXPLICIT_CONTRACT, 0); } /* * Set the TCPC reset event such that we can set our CC @@ -3026,7 +3016,8 @@ void pd_task(void *u) if (!(saved_flgs & PD_BBRMFLG_EXPLICIT_CONTRACT)) #endif /* CONFIG_USB_PD_DUAL_ROLE */ tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ? - TYPEC_CC_RP : TYPEC_CC_RD); + TYPEC_CC_RP : + TYPEC_CC_RD); #ifdef CONFIG_USBC_PPC /* @@ -3126,7 +3117,8 @@ void pd_task(void *u) * role. */ tcpm_set_cc(port, pd[port].power_role ? - TYPEC_CC_RP : TYPEC_CC_RD); + TYPEC_CC_RP : + TYPEC_CC_RD); /* Determine the polarity. */ tcpm_get_cc(port, &cc1, &cc2); @@ -3136,7 +3128,7 @@ void pd_task(void *u) } else if (cc_is_snk_dbg_acc(cc1, cc2)) { pd[port].polarity = board_get_src_dts_polarity( - port); + port); } else { pd[port].polarity = get_src_polarity(cc1, cc2); @@ -3145,9 +3137,11 @@ void pd_task(void *u) #endif /* CONFIG_USB_PD_DUAL_ROLE */ { /* Ensure CC termination is default */ - tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == - PD_ROLE_SOURCE ? TYPEC_CC_RP : - TYPEC_CC_RD); + tcpm_set_cc(port, + PD_ROLE_DEFAULT(port) == + PD_ROLE_SOURCE ? + TYPEC_CC_RP : + TYPEC_CC_RD); } /* @@ -3157,14 +3151,18 @@ void pd_task(void *u) * Otherwise, go to the default disconnected state * and force renegotiation. */ - if (pd[port].vdm_state == VDM_STATE_DONE && ( + if (pd[port].vdm_state == VDM_STATE_DONE && + ( #ifdef CONFIG_USB_PD_DUAL_ROLE - (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK && - pd[port].task_state == PD_STATE_SNK_READY) || - (pd[port].task_state == PD_STATE_SOFT_RESET) || -#endif - (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE && - pd[port].task_state == PD_STATE_SRC_READY))) { + (PD_ROLE_DEFAULT(port) == PD_ROLE_SINK && + pd[port].task_state == + PD_STATE_SNK_READY) || + (pd[port].task_state == + PD_STATE_SOFT_RESET) || +#endif + (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE && + pd[port].task_state == + PD_STATE_SRC_READY))) { typec_set_polarity(port, pd[port].polarity); tcpm_set_msg_header(port, pd[port].power_role, pd[port].data_role); @@ -3198,9 +3196,8 @@ void pd_task(void *u) if (incoming_packet) { /* Dequeue and consume duplicate message ID. */ if (tcpm_dequeue_message(port, payload, &head) == - EC_SUCCESS - && !consume_repeat_message(port, head) - ) + EC_SUCCESS && + !consume_repeat_message(port, head)) handle_request(port, head, payload); /* Check if there are any more messages */ @@ -3214,13 +3211,13 @@ void pd_task(void *u) /* if nothing to do, verify the state of the world in 500ms */ this_state = pd[port].task_state; - timeout = 500*MSEC; + timeout = 500 * MSEC; switch (this_state) { case PD_STATE_DISABLED: /* Nothing to do */ break; case PD_STATE_SRC_DISCONNECTED: - timeout = 10*MSEC; + timeout = 10 * MSEC; pd_set_src_caps(port, 0, NULL); #ifdef CONFIG_USB_PD_TCPC_LOW_POWER /* @@ -3242,10 +3239,9 @@ void pd_task(void *u) */ if (auto_toggle_supported && !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) && - !is_try_src(port) && - cc_is_open(cc1, cc2)) { + !is_try_src(port) && cc_is_open(cc1, cc2)) { set_state(port, PD_STATE_DRP_AUTO_TOGGLE); - timeout = 2*MSEC; + timeout = 2 * MSEC; break; } #endif @@ -3275,7 +3271,7 @@ void pd_task(void *u) #endif pd[port].cc_state = PD_CC_NONE; set_state(port, - PD_STATE_SRC_DISCONNECTED_DEBOUNCE); + PD_STATE_SRC_DISCONNECTED_DEBOUNCE); break; } #if defined(CONFIG_USB_PD_DUAL_ROLE) @@ -3331,7 +3327,7 @@ void pd_task(void *u) #endif break; case PD_STATE_SRC_DISCONNECTED_DEBOUNCE: - timeout = 20*MSEC; + timeout = 20 * MSEC; tcpm_get_cc(port, &cc1, &cc2); if (cc_is_snk_dbg_acc(cc1, cc2)) { @@ -3346,7 +3342,7 @@ void pd_task(void *u) } else { /* No UFP */ set_state(port, PD_STATE_SRC_DISCONNECTED); - timeout = 5*MSEC; + timeout = 5 * MSEC; break; } @@ -3354,8 +3350,8 @@ void pd_task(void *u) if (new_cc_state != pd[port].cc_state) { pd[port].cc_debounce = get_time().val + - (is_try_src(port) ? PD_T_DEBOUNCE - : PD_T_CC_DEBOUNCE); + (is_try_src(port) ? PD_T_DEBOUNCE : + PD_T_CC_DEBOUNCE); pd[port].cc_state = new_cc_state; break; } @@ -3455,7 +3451,7 @@ void pd_task(void *u) pd[port].flags |= PD_FLAGS_CHECK_PR_ROLE | PD_FLAGS_CHECK_DR_ROLE; hard_reset_count = 0; - timeout = 5*MSEC; + timeout = 5 * MSEC; set_state(port, PD_STATE_SRC_STARTUP); } @@ -3467,7 +3463,7 @@ void pd_task(void *u) case PD_STATE_SRC_HARD_RESET_RECOVER: /* Do not continue until hard reset recovery time */ if (get_time().val < pd[port].src_recover) { - timeout = 50*MSEC; + timeout = 50 * MSEC; break; } @@ -3481,7 +3477,7 @@ void pd_task(void *u) #endif /* Enable VBUS */ - timeout = 10*MSEC; + timeout = 10 * MSEC; if (pd_set_power_supply_ready(port)) { set_state(port, PD_STATE_SRC_DISCONNECTED); break; @@ -3520,13 +3516,14 @@ void pd_task(void *u) * on during debounce. */ get_time().val + - PD_POWER_SUPPLY_TURN_ON_DELAY - - (pd[port].last_state == - PD_STATE_SRC_DISCONNECTED_DEBOUNCE - ? PD_T_CC_DEBOUNCE : 0), + PD_POWER_SUPPLY_TURN_ON_DELAY - + (pd[port].last_state == + PD_STATE_SRC_DISCONNECTED_DEBOUNCE ? + PD_T_CC_DEBOUNCE : + 0), #else get_time().val + - PD_POWER_SUPPLY_TURN_ON_DELAY, + PD_POWER_SUPPLY_TURN_ON_DELAY, #endif PD_STATE_SRC_DISCOVERY); } @@ -3541,25 +3538,25 @@ void pd_task(void *u) * partner, then start NoResponseTimer. */ if (pd_capable(port)) - set_state_timeout(port, + set_state_timeout( + port, get_time().val + - PD_T_NO_RESPONSE, + PD_T_NO_RESPONSE, hard_reset_count < - PD_HARD_RESET_COUNT ? - PD_STATE_HARD_RESET_SEND : - PD_STATE_SRC_DISCONNECTED); + PD_HARD_RESET_COUNT ? + PD_STATE_HARD_RESET_SEND : + PD_STATE_SRC_DISCONNECTED); } /* Send source cap some minimum number of times */ - if (caps_count < PD_CAPS_COUNT && - next_src_cap <= now.val) { + if (caps_count < PD_CAPS_COUNT && + next_src_cap <= now.val) { /* Query capabilities of the other side */ res = send_source_cap(port, AMS_START); /* packet was acked => PD capable device) */ if (res >= 0) { - set_state(port, - PD_STATE_SRC_NEGOCIATE); - timeout = 10*MSEC; + set_state(port, PD_STATE_SRC_NEGOCIATE); + timeout = 10 * MSEC; hard_reset_count = 0; caps_count = 0; /* Port partner is PD capable */ @@ -3567,8 +3564,8 @@ void pd_task(void *u) PD_FLAGS_PREVIOUS_PD_CONN; } else { /* failed, retry later */ timeout = PD_T_SEND_SOURCE_CAP; - next_src_cap = now.val + - PD_T_SEND_SOURCE_CAP; + next_src_cap = + now.val + PD_T_SEND_SOURCE_CAP; caps_count++; } } else if (caps_count < PD_CAPS_COUNT) { @@ -3580,17 +3577,16 @@ void pd_task(void *u) if (pd[port].last_state != pd[port].task_state) set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, PD_STATE_HARD_RESET_SEND); break; case PD_STATE_SRC_ACCEPTED: /* Accept sent, wait for enabling the new voltage */ if (pd[port].last_state != pd[port].task_state) - set_state_timeout( - port, - get_time().val + - PD_T_SINK_TRANSITION, - PD_STATE_SRC_POWERED); + set_state_timeout(port, + get_time().val + + PD_T_SINK_TRANSITION, + PD_STATE_SRC_POWERED); break; case PD_STATE_SRC_POWERED: /* Switch to the new requested voltage */ @@ -3600,7 +3596,7 @@ void pd_task(void *u) set_state_timeout( port, get_time().val + - PD_POWER_SUPPLY_TURN_ON_DELAY, + PD_POWER_SUPPLY_TURN_ON_DELAY, PD_STATE_SRC_TRANSITION); } break; @@ -3608,7 +3604,7 @@ void pd_task(void *u) /* the voltage output is good, notify the source */ res = send_control(port, PD_CTRL_PS_RDY); if (res >= 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * Give the sink some time to send any messages @@ -3621,8 +3617,8 @@ void pd_task(void *u) * SRC_READY state. */ pd[port].ready_state_holdoff_timer = - get_time().val + SRC_READY_HOLD_OFF_US - + (get_time().le.lo & 0xf) * 12 * MSEC; + get_time().val + SRC_READY_HOLD_OFF_US + + (get_time().le.lo & 0xf) * 12 * MSEC; /* it's time to ping regularly the sink */ set_state(port, PD_STATE_SRC_READY); @@ -3658,8 +3654,7 @@ void pd_task(void *u) if (pd[port].flags & PD_FLAGS_UPDATE_SRC_CAPS) { res = send_source_cap(port, AMS_START); if (res >= 0) { - set_state(port, - PD_STATE_SRC_NEGOCIATE); + set_state(port, PD_STATE_SRC_NEGOCIATE); pd[port].flags &= ~PD_FLAGS_UPDATE_SRC_CAPS; } @@ -3669,12 +3664,16 @@ void pd_task(void *u) /* Send get sink cap if haven't received it yet */ if (!(pd[port].flags & PD_FLAGS_SNK_CAP_RECVD)) { if (++snk_cap_count <= PD_SNK_CAP_RETRIES) { - /* Get sink cap to know if dual-role device */ - send_control(port, PD_CTRL_GET_SINK_CAP); - set_state(port, PD_STATE_SRC_GET_SINK_CAP); + /* Get sink cap to know if dual-role + * device */ + send_control(port, + PD_CTRL_GET_SINK_CAP); + set_state(port, + PD_STATE_SRC_GET_SINK_CAP); break; } else if (debug_level >= 2 && - snk_cap_count == PD_SNK_CAP_RETRIES+1) { + snk_cap_count == + PD_SNK_CAP_RETRIES + 1) { CPRINTF("C%d ERR SNK_CAP\n", port); } } @@ -3686,7 +3685,6 @@ void pd_task(void *u) pd[port].flags &= ~PD_FLAGS_CHECK_PR_ROLE; } - /* Check data role policy, which may trigger a swap */ if (pd[port].flags & PD_FLAGS_CHECK_DR_ROLE) { pd_check_dr_role(port, pd[port].data_role, @@ -3705,8 +3703,7 @@ void pd_task(void *u) * initiate or receive a request an exchange * of VCONN Source. */ - pd_try_execute_vconn_swap(port, - pd[port].flags); + pd_try_execute_vconn_swap(port, pd[port].flags); pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE; break; } @@ -3747,28 +3744,30 @@ void pd_task(void *u) if (pd[port].last_state != pd[port].task_state) set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, PD_STATE_SRC_READY); break; case PD_STATE_DR_SWAP: if (pd[port].last_state != pd[port].task_state) { res = send_control(port, PD_CTRL_DR_SWAP); if (res < 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * If failed to get goodCRC, send * soft reset, otherwise ignore * failure. */ - set_state(port, res == -1 ? - PD_STATE_SOFT_RESET : - READY_RETURN_STATE(port)); + set_state(port, + res == -1 ? + PD_STATE_SOFT_RESET : + READY_RETURN_STATE( + port)); break; } /* Wait for accept or reject */ set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, READY_RETURN_STATE(port)); } break; @@ -3777,31 +3776,32 @@ void pd_task(void *u) if (pd[port].last_state != pd[port].task_state) { res = send_control(port, PD_CTRL_PR_SWAP); if (res < 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * If failed to get goodCRC, send * soft reset, otherwise ignore * failure. */ - set_state(port, res == -1 ? - PD_STATE_SOFT_RESET : - PD_STATE_SRC_READY); + set_state(port, + res == -1 ? + PD_STATE_SOFT_RESET : + PD_STATE_SRC_READY); break; } /* Wait for accept or reject */ set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, PD_STATE_SRC_READY); } break; case PD_STATE_SRC_SWAP_SNK_DISABLE: /* Give time for sink to stop drawing current */ if (pd[port].last_state != pd[port].task_state) - set_state_timeout(port, - get_time().val + - PD_T_SINK_TRANSITION, - PD_STATE_SRC_SWAP_SRC_DISABLE); + set_state_timeout( + port, + get_time().val + PD_T_SINK_TRANSITION, + PD_STATE_SRC_SWAP_SRC_DISABLE); break; case PD_STATE_SRC_SWAP_SRC_DISABLE: if (pd[port].last_state != pd[port].task_state) { @@ -3824,10 +3824,11 @@ void pd_task(void *u) /* Inform TCPC of power role update. */ pd_update_roles(port); - set_state_timeout(port, - get_time().val + - PD_POWER_SUPPLY_TURN_OFF_DELAY, - PD_STATE_SRC_SWAP_STANDBY); + set_state_timeout( + port, + get_time().val + + PD_POWER_SUPPLY_TURN_OFF_DELAY, + PD_STATE_SRC_SWAP_STANDBY); } break; case PD_STATE_SRC_SWAP_STANDBY: @@ -3836,7 +3837,7 @@ void pd_task(void *u) /* Send PS_RDY */ res = send_control(port, PD_CTRL_PS_RDY); if (res < 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; set_state(port, PD_STATE_SRC_DISCONNECTED); break; @@ -3844,7 +3845,7 @@ void pd_task(void *u) /* Wait for PS_RDY from new source */ set_state_timeout(port, get_time().val + - PD_T_PS_SOURCE_ON, + PD_T_PS_SOURCE_ON, PD_STATE_SNK_DISCONNECTED); } break; @@ -3895,8 +3896,8 @@ void pd_task(void *u) /* Set the CC termination and state back to default */ tcpm_set_cc(port, PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ? - TYPEC_CC_RP : - TYPEC_CC_RD); + TYPEC_CC_RP : + TYPEC_CC_RD); set_state(port, PD_DEFAULT_STATE(port)); tcpc_prints("resumed!", port); #endif @@ -3904,10 +3905,11 @@ void pd_task(void *u) } case PD_STATE_SNK_DISCONNECTED: #ifdef CONFIG_USB_PD_LOW_POWER - timeout = (drp_state[port] != - PD_DRP_TOGGLE_ON ? SECOND : 10*MSEC); + timeout = (drp_state[port] != PD_DRP_TOGGLE_ON ? + SECOND : + 10 * MSEC); #else - timeout = 10*MSEC; + timeout = 10 * MSEC; #endif pd_set_src_caps(port, 0, NULL); #ifdef CONFIG_USB_PD_TCPC_LOW_POWER @@ -3931,11 +3933,10 @@ void pd_task(void *u) */ if (auto_toggle_supported && !(pd[port].flags & PD_FLAGS_TCPC_DRP_TOGGLE) && - !is_try_src(port) && - cc_is_open(cc1, cc2) && - (drp_state[port] == PD_DRP_TOGGLE_ON)) { + !is_try_src(port) && cc_is_open(cc1, cc2) && + (drp_state[port] == PD_DRP_TOGGLE_ON)) { set_state(port, PD_STATE_DRP_AUTO_TOGGLE); - timeout = 2*MSEC; + timeout = 2 * MSEC; break; } #endif @@ -3945,11 +3946,11 @@ void pd_task(void *u) pd[port].cc_state = PD_CC_NONE; hard_reset_count = 0; new_cc_state = PD_CC_NONE; - pd[port].cc_debounce = get_time().val + - PD_T_CC_DEBOUNCE; + pd[port].cc_debounce = + get_time().val + PD_T_CC_DEBOUNCE; set_state(port, - PD_STATE_SNK_DISCONNECTED_DEBOUNCE); - timeout = 10*MSEC; + PD_STATE_SNK_DISCONNECTED_DEBOUNCE); + timeout = 10 * MSEC; break; } @@ -3983,7 +3984,7 @@ void pd_task(void *u) #endif /* Swap states quickly */ - timeout = 2*MSEC; + timeout = 2 * MSEC; break; } @@ -3994,7 +3995,7 @@ void pd_task(void *u) * CC status. */ pd[port].flags |= PD_FLAGS_LPM_REQUESTED; -#endif/* CONFIG_USB_PD_TCPC_LOW_POWER */ +#endif /* CONFIG_USB_PD_TCPC_LOW_POWER */ break; case PD_STATE_SNK_DISCONNECTED_DEBOUNCE: @@ -4008,16 +4009,16 @@ void pd_task(void *u) } else { /* No connection any more */ set_state(port, PD_STATE_SNK_DISCONNECTED); - timeout = 5*MSEC; + timeout = 5 * MSEC; break; } - timeout = 20*MSEC; + timeout = 20 * MSEC; /* Debounce the cc state */ if (new_cc_state != pd[port].cc_state) { - pd[port].cc_debounce = get_time().val + - PD_T_CC_DEBOUNCE; + pd[port].cc_debounce = + get_time().val + PD_T_CC_DEBOUNCE; pd[port].cc_state = new_cc_state; break; } @@ -4032,14 +4033,14 @@ void pd_task(void *u) * If TRY_SRC is enabled, but not active, * then force attempt to connect as source. */ - pd[port].try_src_marker = get_time().val - + PD_T_DRP_TRY; - pd[port].try_timeout = get_time().val - + PD_T_TRY_TIMEOUT; + pd[port].try_src_marker = + get_time().val + PD_T_DRP_TRY; + pd[port].try_timeout = + get_time().val + PD_T_TRY_TIMEOUT; /* Swap roles to source */ pd_set_power_role(port, PD_ROLE_SOURCE); tcpm_set_cc(port, TYPEC_CC_RP); - timeout = 2*MSEC; + timeout = 2 * MSEC; set_state(port, PD_STATE_SRC_DISCONNECTED); /* Set flag after the state change */ pd[port].flags |= PD_FLAGS_TRY_SRC; @@ -4060,8 +4061,8 @@ void pd_task(void *u) #if defined(CONFIG_CHARGE_MANAGER) typec_curr = usb_get_typec_current_limit( pd[port].polarity, cc1, cc2); - typec_set_input_current_limit( - port, typec_curr, TYPE_C_VOLTAGE); + typec_set_input_current_limit(port, typec_curr, + TYPE_C_VOLTAGE); #endif #ifdef CONFIG_USBC_PPC @@ -4088,7 +4089,7 @@ void pd_task(void *u) pd[port].flags |= PD_FLAGS_TS_DTS_PARTNER; set_state(port, PD_STATE_SNK_DISCOVERY); - timeout = 10*MSEC; + timeout = 10 * MSEC; hook_call_deferred( &pd_usb_billboard_deferred_data, PD_T_AME); @@ -4099,47 +4100,49 @@ void pd_task(void *u) pd[port].flags |= PD_FLAGS_CHECK_IDENTITY; if (get_usb_pd_vbus_detect() == - USB_PD_VBUS_DETECT_NONE) { + USB_PD_VBUS_DETECT_NONE) { /* * Can't measure vbus state so this is the * maximum recovery time for the source. */ if (pd[port].last_state != pd[port].task_state) - set_state_timeout(port, get_time().val + - PD_T_SAFE_0V + - PD_T_SRC_RECOVER_MAX + - PD_T_SRC_TURN_ON, - PD_STATE_SNK_DISCONNECTED); + set_state_timeout( + port, + get_time().val + PD_T_SAFE_0V + + PD_T_SRC_RECOVER_MAX + + PD_T_SRC_TURN_ON, + PD_STATE_SNK_DISCONNECTED); } else { #ifndef CONFIG_USB_PD_VBUS_DETECT_NONE /* Wait for VBUS to go low and then high*/ if (pd[port].last_state != - pd[port].task_state) { + pd[port].task_state) { snk_hard_reset_vbus_off = 0; - set_state_timeout(port, - get_time().val + - PD_T_SAFE_0V, - hard_reset_count < - PD_HARD_RESET_COUNT ? - PD_STATE_HARD_RESET_SEND : - PD_STATE_SNK_DISCOVERY); + set_state_timeout( + port, + get_time().val + PD_T_SAFE_0V, + hard_reset_count < + PD_HARD_RESET_COUNT ? + PD_STATE_HARD_RESET_SEND : + PD_STATE_SNK_DISCOVERY); } if (!pd_is_vbus_present(port) && !snk_hard_reset_vbus_off) { /* VBUS has gone low, reset timeout */ snk_hard_reset_vbus_off = 1; - set_state_timeout(port, - get_time().val + - PD_T_SRC_RECOVER_MAX + - PD_T_SRC_TURN_ON, - PD_STATE_SNK_DISCONNECTED); + set_state_timeout( + port, + get_time().val + + PD_T_SRC_RECOVER_MAX + + PD_T_SRC_TURN_ON, + PD_STATE_SNK_DISCONNECTED); } if (pd_is_vbus_present(port) && snk_hard_reset_vbus_off) { /* VBUS went high again */ set_state(port, PD_STATE_SNK_DISCOVERY); - timeout = 10*MSEC; + timeout = 10 * MSEC; } /* @@ -4152,8 +4155,8 @@ void pd_task(void *u) break; case PD_STATE_SNK_DISCOVERY: /* Wait for source cap expired only if we are enabled */ - if ((pd[port].last_state != pd[port].task_state) - && pd_comm_is_enabled(port)) { + if ((pd[port].last_state != pd[port].task_state) && + pd_comm_is_enabled(port)) { #if defined(CONFIG_USB_PD_TCPM_TCPCI) || defined(CONFIG_USB_PD_TCPM_STUB) /* * If we come from hard reset recover state, @@ -4176,58 +4179,64 @@ void pd_task(void *u) */ int batt_soc = usb_get_battery_soc(); - if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC || + if (batt_soc < + CONFIG_USB_PD_RESET_MIN_BATT_SOC || battery_get_disconnect_state() != - BATTERY_NOT_DISCONNECTED) + BATTERY_NOT_DISCONNECTED) pd[port].flags |= - PD_FLAGS_SNK_WAITING_BATT; + PD_FLAGS_SNK_WAITING_BATT; else pd[port].flags &= - ~PD_FLAGS_SNK_WAITING_BATT; + ~PD_FLAGS_SNK_WAITING_BATT; #endif if (pd[port].flags & - PD_FLAGS_SNK_WAITING_BATT) { + PD_FLAGS_SNK_WAITING_BATT) { #ifdef CONFIG_CHARGE_MANAGER /* * Configure this port as dedicated for * now, so it won't be de-selected by * the charge manager leaving safe mode. */ - charge_manager_update_dualrole(port, - CAP_DEDICATED); + charge_manager_update_dualrole( + port, CAP_DEDICATED); #endif CPRINTS("C%d: Battery low. " - "Hold reset timer", port); - /* - * If VBUS has never been low, and we timeout - * waiting for source cap, try a soft reset - * first, in case we were already in a stable - * contract before this boot. - */ + "Hold reset timer", + port); + /* + * If VBUS has never been low, and we + * timeout waiting for source cap, try a + * soft reset first, in case we were + * already in a stable contract before + * this boot. + */ } else if (pd[port].flags & - PD_FLAGS_VBUS_NEVER_LOW) { - set_state_timeout(port, - get_time().val + - PD_T_SINK_WAIT_CAP, - PD_STATE_SOFT_RESET); - /* - * If we haven't passed hard reset counter, - * start SinkWaitCapTimer, otherwise start - * NoResponseTimer. - */ + PD_FLAGS_VBUS_NEVER_LOW) { + set_state_timeout( + port, + get_time().val + + PD_T_SINK_WAIT_CAP, + PD_STATE_SOFT_RESET); + /* + * If we haven't passed hard reset + * counter, start SinkWaitCapTimer, + * otherwise start NoResponseTimer. + */ } else if (hard_reset_count < - PD_HARD_RESET_COUNT) { - set_state_timeout(port, - get_time().val + - PD_T_SINK_WAIT_CAP, - PD_STATE_HARD_RESET_SEND); + PD_HARD_RESET_COUNT) { + set_state_timeout( + port, + get_time().val + + PD_T_SINK_WAIT_CAP, + PD_STATE_HARD_RESET_SEND); } else if (pd_capable(port)) { /* ErrorRecovery */ - set_state_timeout(port, - get_time().val + - PD_T_NO_RESPONSE, - PD_STATE_SNK_DISCONNECTED); + set_state_timeout( + port, + get_time().val + + PD_T_NO_RESPONSE, + PD_STATE_SNK_DISCONNECTED); } #if defined(CONFIG_CHARGE_MANAGER) /* @@ -4247,17 +4256,17 @@ void pd_task(void *u) /* Check if CC pull-up has changed */ tcpm_get_cc(port, &cc1, &cc2); - if (typec_curr != usb_get_typec_current_limit( - pd[port].polarity, cc1, cc2)) { + if (typec_curr != + usb_get_typec_current_limit(pd[port].polarity, cc1, + cc2)) { /* debounce signal by requiring two reads */ if (typec_curr_change) { /* set new input current limit */ - typec_curr = - usb_get_typec_current_limit( - pd[port].polarity, - cc1, cc2); + typec_curr = usb_get_typec_current_limit( + pd[port].polarity, cc1, cc2); typec_set_input_current_limit( - port, typec_curr, TYPE_C_VOLTAGE); + port, typec_curr, + TYPE_C_VOLTAGE); } else { /* delay for debounce */ timeout = PD_T_DEBOUNCE; @@ -4275,7 +4284,7 @@ void pd_task(void *u) hard_reset_count = 0; set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, PD_STATE_HARD_RESET_SEND); } break; @@ -4284,11 +4293,11 @@ void pd_task(void *u) if (pd[port].last_state != pd[port].task_state) set_state_timeout(port, get_time().val + - PD_T_PS_TRANSITION, + PD_T_PS_TRANSITION, PD_STATE_HARD_RESET_SEND); break; case PD_STATE_SNK_READY: - timeout = 20*MSEC; + timeout = 20 * MSEC; /* * Don't send any traffic yet until our holdoff timer @@ -4343,15 +4352,14 @@ void pd_task(void *u) * initiate or receive a request an exchange * of VCONN Source. */ - pd_try_execute_vconn_swap(port, - pd[port].flags); + pd_try_execute_vconn_swap(port, pd[port].flags); pd[port].flags &= ~PD_FLAGS_CHECK_VCONN_STATE; break; } /* If DFP, send discovery SVDMs */ if (pd[port].data_role == PD_ROLE_DFP && - (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) { + (pd[port].flags & PD_FLAGS_CHECK_IDENTITY)) { pd_send_vdm(port, USB_SID_PD, CMD_DISCOVER_IDENT, NULL, 0); pd[port].flags &= ~PD_FLAGS_CHECK_IDENTITY; @@ -4368,27 +4376,28 @@ void pd_task(void *u) } /* Sent all messages, don't need to wake very often */ - timeout = 200*MSEC; + timeout = 200 * MSEC; break; case PD_STATE_SNK_SWAP_INIT: if (pd[port].last_state != pd[port].task_state) { res = send_control(port, PD_CTRL_PR_SWAP); if (res < 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * If failed to get goodCRC, send * soft reset, otherwise ignore * failure. */ - set_state(port, res == -1 ? - PD_STATE_SOFT_RESET : - PD_STATE_SNK_READY); + set_state(port, + res == -1 ? + PD_STATE_SOFT_RESET : + PD_STATE_SNK_READY); break; } /* Wait for accept or reject */ set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, PD_STATE_SNK_READY); } break; @@ -4397,19 +4406,18 @@ void pd_task(void *u) pd_set_input_current_limit(port, 0, 0); #ifdef CONFIG_CHARGE_MANAGER typec_set_input_current_limit(port, 0, 0); - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE); #endif set_state(port, PD_STATE_SNK_SWAP_SRC_DISABLE); - timeout = 10*MSEC; + timeout = 10 * MSEC; break; case PD_STATE_SNK_SWAP_SRC_DISABLE: /* Wait for PS_RDY */ if (pd[port].last_state != pd[port].task_state) set_state_timeout(port, get_time().val + - PD_T_PS_SOURCE_OFF, + PD_T_PS_SOURCE_OFF, PD_STATE_HARD_RESET_SEND); break; case PD_STATE_SNK_SWAP_STANDBY: @@ -4419,7 +4427,7 @@ void pd_task(void *u) if (pd_set_power_supply_ready(port)) { /* Restore Rd */ tcpm_set_cc(port, TYPEC_CC_RD); - timeout = 10*MSEC; + timeout = 10 * MSEC; set_state(port, PD_STATE_SNK_DISCONNECTED); break; @@ -4428,7 +4436,7 @@ void pd_task(void *u) set_state_timeout( port, get_time().val + - PD_POWER_SUPPLY_TURN_ON_DELAY, + PD_POWER_SUPPLY_TURN_ON_DELAY, PD_STATE_SNK_SWAP_COMPLETE); } break; @@ -4445,34 +4453,36 @@ void pd_task(void *u) } /* Don't send GET_SINK_CAP on swap */ - snk_cap_count = PD_SNK_CAP_RETRIES+1; + snk_cap_count = PD_SNK_CAP_RETRIES + 1; caps_count = 0; pd[port].msg_id = 0; pd_set_power_role(port, PD_ROLE_SOURCE); pd_update_roles(port); set_state(port, PD_STATE_SRC_DISCOVERY); - timeout = 10*MSEC; + timeout = 10 * MSEC; break; #ifdef CONFIG_USBC_VCONN_SWAP case PD_STATE_VCONN_SWAP_SEND: if (pd[port].last_state != pd[port].task_state) { res = send_control(port, PD_CTRL_VCONN_SWAP); if (res < 0) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * If failed to get goodCRC, send * soft reset, otherwise ignore * failure. */ - set_state(port, res == -1 ? - PD_STATE_SOFT_RESET : - READY_RETURN_STATE(port)); + set_state(port, + res == -1 ? + PD_STATE_SOFT_RESET : + READY_RETURN_STATE( + port)); break; } /* Wait for accept or reject */ set_state_timeout(port, get_time().val + - PD_T_SENDER_RESPONSE, + PD_T_SENDER_RESPONSE, READY_RETURN_STATE(port)); } break; @@ -4481,12 +4491,14 @@ void pd_task(void *u) if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) { /* Turn VCONN on and wait for it */ set_vconn(port, 1); - set_state_timeout(port, + set_state_timeout( + port, get_time().val + - CONFIG_USBC_VCONN_SWAP_DELAY_US, + CONFIG_USBC_VCONN_SWAP_DELAY_US, PD_STATE_VCONN_SWAP_READY); } else { - set_state_timeout(port, + set_state_timeout( + port, get_time().val + PD_T_VCONN_SOURCE_ON, READY_RETURN_STATE(port)); @@ -4498,29 +4510,30 @@ void pd_task(void *u) if (!(pd[port].flags & PD_FLAGS_VCONN_ON)) { /* VCONN is now on, send PS_RDY */ pd_set_vconn_role(port, - PD_ROLE_VCONN_ON); + PD_ROLE_VCONN_ON); res = send_control(port, - PD_CTRL_PS_RDY); + PD_CTRL_PS_RDY); if (res == -1) { - timeout = 10*MSEC; + timeout = 10 * MSEC; /* * If failed to get goodCRC, * send soft reset */ set_state(port, - PD_STATE_SOFT_RESET); + PD_STATE_SOFT_RESET); break; } set_state(port, - READY_RETURN_STATE(port)); + READY_RETURN_STATE(port)); } else { /* Turn VCONN off and wait for it */ set_vconn(port, 0); pd_set_vconn_role(port, - PD_ROLE_VCONN_OFF); - set_state_timeout(port, + PD_ROLE_VCONN_OFF); + set_state_timeout( + port, get_time().val + - CONFIG_USBC_VCONN_SWAP_DELAY_US, + CONFIG_USBC_VCONN_SWAP_DELAY_US, READY_RETURN_STATE(port)); } } @@ -4538,14 +4551,14 @@ void pd_task(void *u) if (res < 0) { set_state(port, PD_STATE_HARD_RESET_SEND); - timeout = 5*MSEC; + timeout = 5 * MSEC; break; } - set_state_timeout( - port, - get_time().val + PD_T_SENDER_RESPONSE, - PD_STATE_HARD_RESET_SEND); + set_state_timeout(port, + get_time().val + + PD_T_SENDER_RESPONSE, + PD_STATE_HARD_RESET_SEND); } break; case PD_STATE_HARD_RESET_SEND: @@ -4577,7 +4590,7 @@ void pd_task(void *u) break; if (pd_transmit(port, TCPCI_MSG_TX_HARD_RESET, 0, NULL, - AMS_START) < 0) { + AMS_START) < 0) { /* * likely a non-idle channel * TCPCI r2.0 v1.0 4.4.15: @@ -4614,7 +4627,8 @@ void pd_task(void *u) */ if (pd[port].power_role == PD_ROLE_SOURCE) { set_state_timeout(port, - get_time().val + PD_T_PS_HARD_RESET, + get_time().val + + PD_T_PS_HARD_RESET, PD_STATE_HARD_RESET_EXECUTE); } else { set_state(port, PD_STATE_HARD_RESET_EXECUTE); @@ -4633,32 +4647,31 @@ void pd_task(void *u) /* reset our own state machine */ pd_execute_hard_reset(port); - timeout = 10*MSEC; + timeout = 10 * MSEC; break; #ifdef CONFIG_COMMON_RUNTIME case PD_STATE_BIST_RX: send_bist_cmd(port); /* Delay at least enough for partner to finish BIST */ - timeout = PD_T_BIST_RECEIVE + 20*MSEC; + timeout = PD_T_BIST_RECEIVE + 20 * MSEC; /* Set to appropriate port disconnected state */ - set_state(port, DUAL_ROLE_IF_ELSE(port, - PD_STATE_SNK_DISCONNECTED, + set_state(port, DUAL_ROLE_IF_ELSE( + port, PD_STATE_SNK_DISCONNECTED, PD_STATE_SRC_DISCONNECTED)); break; case PD_STATE_BIST_TX: pd_transmit(port, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL, AMS_START); /* Delay at least enough to finish sending BIST */ - timeout = PD_T_BIST_TRANSMIT + 20*MSEC; + timeout = PD_T_BIST_TRANSMIT + 20 * MSEC; /* Set to appropriate port disconnected state */ - set_state(port, DUAL_ROLE_IF_ELSE(port, - PD_STATE_SNK_DISCONNECTED, + set_state(port, DUAL_ROLE_IF_ELSE( + port, PD_STATE_SNK_DISCONNECTED, PD_STATE_SRC_DISCONNECTED)); break; #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - case PD_STATE_DRP_AUTO_TOGGLE: - { + case PD_STATE_DRP_AUTO_TOGGLE: { enum pd_drp_next_states next_state; assert(auto_toggle_supported); @@ -4701,10 +4714,8 @@ void pd_task(void *u) tcpm_get_cc(port, &cc1, &cc2); next_state = drp_auto_toggle_next_state( - &pd[port].drp_sink_time, - pd[port].power_role, - drp_state[port], - cc1, cc2, false); + &pd[port].drp_sink_time, pd[port].power_role, + drp_state[port], cc1, cc2, false); #ifdef CONFIG_USB_PD_TCPC_LOW_POWER /* @@ -4718,7 +4729,7 @@ void pd_task(void *u) #endif if (next_state == DRP_TC_DEFAULT) { if (PD_DEFAULT_STATE(port) == - PD_STATE_SNK_DISCONNECTED) + PD_STATE_SNK_DISCONNECTED) next_state = DRP_TC_UNATTACHED_SNK; else next_state = DRP_TC_UNATTACHED_SRC; @@ -4737,7 +4748,7 @@ void pd_task(void *u) tcpm_set_cc(port, TYPEC_CC_RD); pd_set_power_role(port, PD_ROLE_SINK); - timeout = 2*MSEC; + timeout = 2 * MSEC; set_state(port, PD_STATE_SNK_DISCONNECTED); } else if (next_state == DRP_TC_UNATTACHED_SRC) { /* @@ -4752,7 +4763,7 @@ void pd_task(void *u) tcpm_set_cc(port, TYPEC_CC_RP); pd_set_power_role(port, PD_ROLE_SOURCE); - timeout = 2*MSEC; + timeout = 2 * MSEC; set_state(port, PD_STATE_SRC_DISCONNECTED); } else { /* @@ -4770,8 +4781,9 @@ void pd_task(void *u) case PD_STATE_ENTER_USB: if (pd[port].last_state != pd[port].task_state) { set_state_timeout(port, - get_time().val + PD_T_SENDER_RESPONSE, - READY_RETURN_STATE(port)); + get_time().val + + PD_T_SENDER_RESPONSE, + READY_RETURN_STATE(port)); } break; default: @@ -4789,7 +4801,8 @@ void pd_task(void *u) if (now.val >= pd[port].timeout) { set_state(port, pd[port].timeout_state); /* On a state timeout, run next state soon */ - timeout = timeout < 10*MSEC ? timeout : 10*MSEC; + timeout = timeout < 10 * MSEC ? timeout : + 10 * MSEC; } else if (pd[port].timeout - now.val < timeout) { timeout = pd[port].timeout - now.val; } @@ -4836,7 +4849,7 @@ void pd_task(void *u) if (cc1 == TYPEC_CC_VOLT_OPEN) { set_state(port, PD_STATE_SRC_DISCONNECTED); /* Debouncing */ - timeout = 10*MSEC; + timeout = 10 * MSEC; #ifdef CONFIG_USB_PD_DUAL_ROLE /* * If Try.SRC is configured, then ATTACHED_SRC @@ -4848,8 +4861,8 @@ void pd_task(void *u) pd_set_power_role(port, PD_ROLE_SINK); tcpm_set_cc(port, TYPEC_CC_RD); /* Set timer for TryWait.SNK state */ - pd[port].try_src_marker = get_time().val - + PD_T_DEBOUNCE; + pd[port].try_src_marker = + get_time().val + PD_T_DEBOUNCE; /* Advance to TryWait.SNK state */ set_state(port, PD_STATE_SNK_DISCONNECTED); @@ -4874,7 +4887,7 @@ void pd_task(void *u) /* Sink: detect disconnect by monitoring VBUS */ set_state(port, PD_STATE_SNK_DISCONNECTED); /* set timeout small to reconnect fast */ - timeout = 5*MSEC; + timeout = 5 * MSEC; } #endif /* CONFIG_USB_PD_DUAL_ROLE */ } @@ -5013,16 +5026,16 @@ void pd_send_hpd(int port, enum hpd_event hpd) if (!opos) return; - data[0] = VDO_DP_STATUS((hpd == hpd_irq), /* IRQ_HPD */ - (hpd != hpd_low), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ - 1, /* enabled */ - 0, /* power low */ + data[0] = VDO_DP_STATUS((hpd == hpd_irq), /* IRQ_HPD */ + (hpd != hpd_low), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + 1, /* enabled */ + 0, /* power low */ 0x2); - pd_send_vdm(port, USB_SID_DISPLAYPORT, - VDO_OPOS(opos) | CMD_ATTENTION, data, 1); + pd_send_vdm(port, USB_SID_DISPLAYPORT, VDO_OPOS(opos) | CMD_ATTENTION, + data, 1); /* Wait until VDM is done. */ while (pd[0].vdm_state > 0) task_wait_event(USB_PD_RX_TMOUT_US * @@ -5037,15 +5050,15 @@ int pd_fetch_acc_log_entry(int port) /* Cannot send a VDM now, the host should retry */ if (pd[port].vdm_state > 0) return pd[port].vdm_state == VDM_STATE_BUSY ? - EC_RES_BUSY : EC_RES_UNAVAILABLE; + EC_RES_BUSY : + EC_RES_UNAVAILABLE; pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_GET_LOG, NULL, 0); - timeout.val = get_time().val + 75*MSEC; + timeout.val = get_time().val + 75 * MSEC; /* Wait until VDM is done */ - while ((pd[port].vdm_state > 0) && - (get_time().val < timeout.val)) - task_wait_event(10*MSEC); + while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val)) + task_wait_event(10 * MSEC); if (pd[port].vdm_state > 0) return EC_RES_TIMEOUT; @@ -5119,7 +5132,6 @@ static int command_pd(int argc, char **argv) return EC_SUCCESS; } - #ifdef CONFIG_CMD_PD #ifdef CONFIG_CMD_PD_DEV_DUMP_INFO else if (!strncasecmp(argv[1], "rwhashtable", 3)) { @@ -5234,8 +5246,8 @@ static int command_pd(int argc, char **argv) } ccprintf("Pings %s\n", - (pd[port].flags & PD_FLAGS_PING_ENABLED) ? - "on" : "off"); + (pd[port].flags & PD_FLAGS_PING_ENABLED) ? "on" : + "off"); } else if (!strncasecmp(argv[2], "vdm", 3)) { if (argc < 4) return EC_ERROR_PARAM_COUNT; @@ -5250,11 +5262,11 @@ static int command_pd(int argc, char **argv) pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_PING_ENABLE, &enable, 1); } else if (!strncasecmp(argv[3], "curr", 4)) { - pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT, - NULL, 0); + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_CURRENT, NULL, + 0); } else if (!strncasecmp(argv[3], "vers", 4)) { - pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION, - NULL, 0); + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_VERSION, NULL, + 0); } else { return EC_ERROR_PARAM_COUNT; } @@ -5293,8 +5305,7 @@ static int command_pd(int argc, char **argv) else if (!strcasecmp(argv[3], "sink")) pd_set_dual_role(port, PD_DRP_FORCE_SINK); else if (!strcasecmp(argv[3], "source")) - pd_set_dual_role(port, - PD_DRP_FORCE_SOURCE); + pd_set_dual_role(port, PD_DRP_FORCE_SOURCE); else return EC_ERROR_PARAM4; } @@ -5302,17 +5313,17 @@ static int command_pd(int argc, char **argv) #endif } else #endif - if (!strncasecmp(argv[2], "state", 5)) { + if (!strncasecmp(argv[2], "state", 5)) { ccprintf("Port C%d CC%d, %s - Role: %s-%s%s " "State: %d(%s), Flags: 0x%04x\n", - port, pd[port].polarity + 1, - pd_comm_is_enabled(port) ? "Ena" : "Dis", - pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK", - pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP", - (pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "", - pd[port].task_state, - debug_level > 0 ? pd_get_task_state_name(port) : "", - pd[port].flags); + port, pd[port].polarity + 1, + pd_comm_is_enabled(port) ? "Ena" : "Dis", + pd[port].power_role == PD_ROLE_SOURCE ? "SRC" : "SNK", + pd[port].data_role == PD_ROLE_DFP ? "DFP" : "UFP", + (pd[port].flags & PD_FLAGS_VCONN_ON) ? "-VC" : "", + pd[port].task_state, + debug_level > 0 ? pd_get_task_state_name(port) : "", + pd[port].flags); } else { return EC_ERROR_PARAM1; } @@ -5360,9 +5371,8 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) if (p->size + sizeof(*p) > args->params_size) return EC_RES_INVALID_PARAM; -#if defined(CONFIG_BATTERY) && \ - (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ - defined(CONFIG_BATTERY_PRESENT_GPIO)) +#if defined(CONFIG_BATTERY) && (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ + defined(CONFIG_BATTERY_PRESENT_GPIO)) /* * Do not allow PD firmware update if no battery and this port * is sinking power, because we will lose power. @@ -5400,7 +5410,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) case USB_PD_FW_ERASE_SIG: pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_ERASE_SIG, NULL, 0); - timeout.val = get_time().val + 500*MSEC; + timeout.val = get_time().val + 500 * MSEC; break; case USB_PD_FW_FLASH_WRITE: @@ -5412,12 +5422,12 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) for (i = 0; i < size; i += VDO_MAX_SIZE - 1) { pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE, data + i, MIN(size - i, VDO_MAX_SIZE - 1)); - timeout.val = get_time().val + 500*MSEC; + timeout.val = get_time().val + 500 * MSEC; /* Wait until VDM is done */ while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val)) - task_wait_event(10*MSEC); + task_wait_event(10 * MSEC); if (pd[port].vdm_state > 0) return EC_RES_TIMEOUT; @@ -5431,7 +5441,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) /* Wait until VDM is done or timeout */ while ((pd[port].vdm_state > 0) && (get_time().val < timeout.val)) - task_wait_event(50*MSEC); + task_wait_event(50 * MSEC); if ((pd[port].vdm_state > 0) || (pd[port].vdm_state == VDM_STATE_ERR_TMOUT)) @@ -5441,12 +5451,9 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) return rv; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, - hc_remote_flash, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, hc_remote_flash, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_FLASHPD */ #endif /* HAS_TASK_HOSTCMD */ - #endif /* CONFIG_COMMON_RUNTIME */ -- cgit v1.2.1 From 5a96a73f94b6961d63f85d429c84fdbcad200976 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:11 -0600 Subject: util/ectool.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I814fed1a24f1b2c035417e1bf770e20d97e4b07e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730618 Reviewed-by: Jeremy Bettis --- util/ectool.c | 2495 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 1223 insertions(+), 1272 deletions(-) diff --git a/util/ectool.c b/util/ectool.c index 589923d574..6e4bd1ff35 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -42,8 +42,8 @@ */ #define HELLO_RESP(in_data) ((in_data) + 0x01020304) -#define USB_VID_GOOGLE 0x18d1 -#define USB_PID_HAMMER 0x5022 +#define USB_VID_GOOGLE 0x18d1 +#define USB_PID_HAMMER 0x5022 /* Command line options */ enum { @@ -55,17 +55,15 @@ enum { OPT_DEVICE, }; -static struct option long_opts[] = { - {"dev", 1, 0, OPT_DEV}, - {"interface", 1, 0, OPT_INTERFACE}, - {"name", 1, 0, OPT_NAME}, - {"ascii", 0, 0, OPT_ASCII}, - {"i2c_bus", 1, 0, OPT_I2C_BUS}, - {"device", 1, 0, OPT_DEVICE}, - {NULL, 0, 0, 0} -}; +static struct option long_opts[] = { { "dev", 1, 0, OPT_DEV }, + { "interface", 1, 0, OPT_INTERFACE }, + { "name", 1, 0, OPT_NAME }, + { "ascii", 0, 0, OPT_ASCII }, + { "i2c_bus", 1, 0, OPT_I2C_BUS }, + { "device", 1, 0, OPT_DEVICE }, + { NULL, 0, 0, 0 } }; -#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */ +#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */ const char help_str[] = "Commands:\n" @@ -275,7 +273,7 @@ const char help_str[] = " readtest \n" " Reads a pattern from the EC via LPC\n" " reboot_ec " - " [at-shutdown|switch-slot]\n" + " [at-shutdown|switch-slot]\n" " Reboot EC to RO or RW\n" " reboot_ap_on_g3 []\n" " Requests that the EC will automatically reboot the AP after a\n" @@ -344,17 +342,17 @@ const char help_str[] = " usbmux \n" " Set USB mux switch state\n" " usbpd \n" + "[toggle|toggle-off|sink|source] [none|usb|dp|dock] " + "[dr_swap|pr_swap|vconn_swap]>\n" " Control USB PD/type-C [deprecated]\n" " usbpddps [enable | disable]\n" " Enable or disable dynamic pdo selection\n" " usbpdmuxinfo [tsv]\n" " Get USB-C SS mux info.\n" " tsv: Output as tab separated values. Columns are defined " - "as:\n" + "as:\n" " Port, USB enabled, DP enabled, Polarity, HPD IRQ, " - "HPD LVL\n" + "HPD LVL\n" " usbpdpower [port]\n" " Get USB PD power information\n" " version\n" @@ -366,17 +364,18 @@ const char help_str[] = ""; /* Note: depends on enum ec_image */ -static const char * const image_names[] = {"unknown", "RO", "RW"}; +static const char *const image_names[] = { "unknown", "RO", "RW" }; /* Note: depends on enum ec_led_colors */ -static const char * const led_color_names[] = { - "red", "green", "blue", "yellow", "white", "amber"}; +static const char *const led_color_names[] = { "red", "green", "blue", + "yellow", "white", "amber" }; BUILD_ASSERT(ARRAY_SIZE(led_color_names) == EC_LED_COLOR_COUNT); /* Note: depends on enum ec_led_id */ -static const char * const led_names[] = { - "battery", "power", "adapter", "left", "right", "recovery_hwreinit", - "sysrq debug" }; +static const char *const led_names[] = { "battery", "power", + "adapter", "left", + "right", "recovery_hwreinit", + "sysrq debug" }; BUILD_ASSERT(ARRAY_SIZE(led_names) == EC_LED_ID_COUNT); /* ASCII mode for printing, default off */ @@ -395,7 +394,7 @@ int parse_bool(const char *s, int *dest) *dest = 0; return 1; } else if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) || - tolower(*s) == 't' || tolower(*s) == 'y') { + tolower(*s) == 't' || tolower(*s) == 'y') { *dest = 1; return 1; } else { @@ -546,11 +545,11 @@ int cmd_add_entropy(int argc, char *argv[]) } /* Abort if EC returns an error other than EC_RES_BUSY. */ - if (rv <= -EECRESULT && rv != -EECRESULT-EC_RES_BUSY) + if (rv <= -EECRESULT && rv != -EECRESULT - EC_RES_BUSY) goto out; } - rv = -EECRESULT-EC_RES_TIMEOUT; + rv = -EECRESULT - EC_RES_TIMEOUT; out: fprintf(stderr, "Failed to add entropy: %d\n", rv); return rv; @@ -595,8 +594,8 @@ int cmd_hibdelay(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_HIBERNATION_DELAY, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) { fprintf(stderr, "err: rv=%d\n", rv); return -1; @@ -611,18 +610,18 @@ int cmd_hibdelay(int argc, char *argv[]) static void cmd_hostevent_help(char *cmd) { fprintf(stderr, - " Usage: %s get \n" - " Usage: %s set \n" - " is one of:\n" - " 1: EC_HOST_EVENT_B\n" - " 2: EC_HOST_EVENT_SCI_MASK\n" - " 3: EC_HOST_EVENT_SMI_MASK\n" - " 4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n" - " 5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n" - " 6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n" - " 7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n" - " 8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n" - , cmd, cmd); + " Usage: %s get \n" + " Usage: %s set \n" + " is one of:\n" + " 1: EC_HOST_EVENT_B\n" + " 2: EC_HOST_EVENT_SCI_MASK\n" + " 3: EC_HOST_EVENT_SMI_MASK\n" + " 4: EC_HOST_EVENT_ALWAYS_REPORT_MASK\n" + " 5: EC_HOST_EVENT_ACTIVE_WAKE_MASK\n" + " 6: EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX\n" + " 7: EC_HOST_EVENT_LAZY_WAKE_MASK_S3\n" + " 8: EC_HOST_EVENT_LAZY_WAKE_MASK_S5\n", + cmd, cmd); } static int cmd_hostevent(int argc, char *argv[]) @@ -693,12 +692,12 @@ static int get_latest_cmd_version(uint8_t cmd, int *version) *version = 0; /* Figure out the latest version of the given command the EC supports */ p.cmd = cmd; - rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) { if (rv == -EC_RES_INVALID_PARAM) printf("Command 0x%02x not supported by EC.\n", - EC_CMD_GET_CMD_VERSIONS); + EC_CMD_GET_CMD_VERSIONS); return rv; } @@ -721,7 +720,8 @@ int cmd_hostsleepstate(int argc, char *argv[]) uint32_t timeout, transitions; if (argc < 2) { - fprintf(stderr, "Usage: %s " + fprintf(stderr, + "Usage: %s " "[suspend|wsuspend|resume|freeze|thaw] [timeout]\n", argv[0]); return -1; @@ -751,8 +751,7 @@ int cmd_hostsleepstate(int argc, char *argv[]) if ((*afterscan != '\0') || (afterscan == argv[2])) { - fprintf(stderr, - "Invalid value: %s\n", + fprintf(stderr, "Invalid value: %s\n", argv[2]); return -1; @@ -789,8 +788,7 @@ int cmd_hostsleepstate(int argc, char *argv[]) EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK; printf("%s%d sleep line transitions.\n", - timeout ? "Timeout: " : "", - transitions); + timeout ? "Timeout: " : "", transitions); } return 0; @@ -799,7 +797,7 @@ int cmd_hostsleepstate(int argc, char *argv[]) int cmd_test(int argc, char *argv[]) { struct ec_params_test_protocol p = { - .buf = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + .buf = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 } }; @@ -808,8 +806,7 @@ int cmd_test(int argc, char *argv[]) char *e; if (argc < 3) { - fprintf(stderr, "Usage: %s result length [version]\n", - argv[0]); + fprintf(stderr, "Usage: %s result length [version]\n", argv[0]); return -1; } @@ -832,8 +829,8 @@ int cmd_test(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_TEST_PROTOCOL, version, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_TEST_PROTOCOL, version, &p, sizeof(p), &r, + sizeof(r)); printf("rv = %d\n", rv); return rv; @@ -856,15 +853,15 @@ int cmd_s5(int argc, char *argv[]) p.value = param; } - rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_GSV_PAUSE_IN_S5, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv > 0) printf("%s\n", r.value ? "on" : "off"); return rv < 0; } -static const char * const ec_feature_names[] = { +static const char *const ec_feature_names[] = { [EC_FEATURE_LIMITED] = "Limited image, load RW for more", [EC_FEATURE_FLASH] = "Flash", [EC_FEATURE_PWM_FAN] = "Direct Fan power management", @@ -934,15 +931,14 @@ int cmd_inventory(int argc, char *argv[]) strlen(ec_feature_names[idx]) == 0) printf("%-4d: Unknown feature\n", idx); else - printf("%-4d: %s support\n", - idx, ec_feature_names[idx]); + printf("%-4d: %s support\n", idx, + ec_feature_names[idx]); } } } return 0; } - int cmd_cmdversions(int argc, char *argv[]) { struct ec_params_get_cmd_versions p; @@ -962,8 +958,8 @@ int cmd_cmdversions(int argc, char *argv[]) } p.cmd = cmd; - rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_GET_CMD_VERSIONS, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) { if (rv == -EC_RES_INVALID_PARAM) printf("Command 0x%02x not supported by EC.\n", cmd); @@ -971,8 +967,8 @@ int cmd_cmdversions(int argc, char *argv[]) return rv; } - printf("Command 0x%02x supports version mask 0x%08x\n", - cmd, r.version_mask); + printf("Command 0x%02x supports version mask 0x%08x\n", cmd, + r.version_mask); return 0; } @@ -983,7 +979,7 @@ int cmd_cmdversions(int argc, char *argv[]) */ static const char *reset_cause_to_str(uint16_t cause) { - static const char * const reset_causes[] = { + static const char *const reset_causes[] = { "(reset unknown)", "reset: board custom", "reset: ap hang detected", @@ -998,7 +994,7 @@ static const char *reset_cause_to_str(uint16_t cause) }; BUILD_ASSERT(ARRAY_SIZE(reset_causes) == CHIPSET_RESET_COUNT); - static const char * const shutdown_causes[] = { + static const char *const shutdown_causes[] = { "shutdown: power failure", "shutdown: during EC initialization", "shutdown: board custom", @@ -1032,8 +1028,8 @@ int cmd_uptimeinfo(int argc, char *argv[]) int i; int flag_count; uint32_t flag; - static const char * const reset_flag_descs[] = { - #include "reset_flag_desc.inc" + static const char *const reset_flag_descs[] = { +#include "reset_flag_desc.inc" }; if (argc != 1) { @@ -1048,9 +1044,8 @@ int cmd_uptimeinfo(int argc, char *argv[]) return rv; } - printf("EC uptime: %d.%03d seconds\n", - r.time_since_ec_boot_ms / 1000, - r.time_since_ec_boot_ms % 1000); + printf("EC uptime: %d.%03d seconds\n", r.time_since_ec_boot_ms / 1000, + r.time_since_ec_boot_ms % 1000); printf("AP resets since EC boot: %d\n", r.ap_resets_since_ec_boot); @@ -1060,9 +1055,9 @@ int cmd_uptimeinfo(int argc, char *argv[]) continue; printf("\t%d.%03d: %s\n", - r.recent_ap_reset[i].reset_time_ms / 1000, - r.recent_ap_reset[i].reset_time_ms % 1000, - reset_cause_to_str(r.recent_ap_reset[i].reset_cause)); + r.recent_ap_reset[i].reset_time_ms / 1000, + r.recent_ap_reset[i].reset_time_ms % 1000, + reset_cause_to_str(r.recent_ap_reset[i].reset_cause)); } printf("EC reset flags at last EC boot: "); @@ -1113,11 +1108,11 @@ int cmd_version(int argc, char *argv[]) goto exit; } - rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, - NULL, 0, ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) { fprintf(stderr, "ERROR: EC_CMD_GET_BUILD_INFO failed: %d\n", - rv); + rv); goto exit; } @@ -1138,7 +1133,8 @@ int cmd_version(int argc, char *argv[]) printf("RW cros fwid: %s\n", r.cros_fwid_rw); printf("Firmware copy: %s\n", (r.current_image < ARRAY_SIZE(image_names) ? - image_names[r.current_image] : "?")); + image_names[r.current_image] : + "?")); printf("Build info: %s\n", build_string); exit: printf("Tool version: %s %s %s\n", CROS_ECTOOL_VERSION, DATE, BUILDER); @@ -1146,7 +1142,6 @@ exit: return rv; } - int cmd_read_test(int argc, char *argv[]) { struct ec_params_read_test p; @@ -1181,8 +1176,8 @@ int cmd_read_test(int argc, char *argv[]) for (i = 0; i < size; i += sizeof(r.data)) { p.offset = offset + i / sizeof(uint32_t); p.size = MIN(size - i, sizeof(r.data)); - rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_READ_TEST, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) { fprintf(stderr, "Read error at offset %d\n", i); free(buf); @@ -1211,7 +1206,6 @@ int cmd_read_test(int argc, char *argv[]) return 0; } - int cmd_reboot_ec(int argc, char *argv[]) { struct ec_params_reboot_ec p; @@ -1294,22 +1288,22 @@ int cmd_reboot_ap_on_g3(int argc, char *argv[]) static void cmd_rgbkbd_help(char *cmd) { fprintf(stderr, - " Usage1: %s [ ...]\n" - " Set the color of to . Multiple colors for\n" - " adjacent keys can be set at once.\n" - "\n" - " Usage2: %s clear \n" - " Set the color of all keys to .\n" - "\n" - " Usage3: %s demo \n" - " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" - "\n" - " Usage4: %s scale \n" - " Set the scale parameter of key_ to .\n" - " is a 24-bit integer where scale values are encoded\n" - " as R=23:16, G=15:8, B=7:0.\n" - "\n", - cmd, cmd, cmd, cmd); + " Usage1: %s [ ...]\n" + " Set the color of to . Multiple colors for\n" + " adjacent keys can be set at once.\n" + "\n" + " Usage2: %s clear \n" + " Set the color of all keys to .\n" + "\n" + " Usage3: %s demo \n" + " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" + "\n" + " Usage4: %s scale \n" + " Set the scale parameter of key_ to .\n" + " is a 24-bit integer where scale values are encoded\n" + " as R=23:16, G=15:8, B=7:0.\n" + "\n", + cmd, cmd, cmd, cmd); } static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color) @@ -1373,7 +1367,8 @@ static int cmd_rgbkbd(int argc, char *argv[]) { int val; char *e; - int rv = -1;; + int rv = -1; + ; if (argc < 3) { cmd_rgbkbd_help(argv[0]); @@ -1502,8 +1497,8 @@ int cmd_flash_info(int argc, char *argv[]) if (cmdver >= 1) { /* Fields added in ver.1 available */ - printf("WriteIdealSize %d\nFlags 0x%x\n", - r.write_ideal_size, r.flags); + printf("WriteIdealSize %d\nFlags 0x%x\n", r.write_ideal_size, + r.flags); } return 0; @@ -1591,8 +1586,8 @@ int cmd_flash_read(int argc, char *argv[]) uint8_t *buf; if (argc < 4) { - fprintf(stderr, - "Usage: %s \n", argv[0]); + fprintf(stderr, "Usage: %s \n", + argv[0]); return -1; } offset = strtol(argv[1], &e, 0); @@ -1655,8 +1650,7 @@ int cmd_flash_write(int argc, char *argv[]) printf("Writing to offset %d...\n", offset); /* Write data in chunks */ - rv = ec_flash_write((const uint8_t *)(buf), offset, - size); + rv = ec_flash_write((const uint8_t *)(buf), offset, size); free(buf); @@ -1706,7 +1700,6 @@ int cmd_flash_erase(int argc, char *argv[]) return 0; } - static void print_flash_protect_flags(const char *desc, uint32_t flags) { printf("%s 0x%08x", desc, flags); @@ -1737,7 +1730,6 @@ static void print_flash_protect_flags(const char *desc, uint32_t flags) printf("\n"); } - int cmd_flash_protect(int argc, char *argv[]) { struct ec_params_flash_protect p; @@ -1760,8 +1752,8 @@ int cmd_flash_protect(int argc, char *argv[]) p.mask |= EC_FLASH_PROTECT_RO_AT_BOOT; } - rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_FLASH_PROTECT, EC_VER_FLASH_PROTECT, &p, + sizeof(p), &r, sizeof(r)); if (rv < 0) return rv; if (rv < sizeof(r)) { @@ -1776,12 +1768,15 @@ int cmd_flash_protect(int argc, char *argv[]) /* Check if we got all the flags we asked for */ if ((r.flags & p.mask) != (p.flags & p.mask)) { - fprintf(stderr, "Unable to set requested flags " + fprintf(stderr, + "Unable to set requested flags " "(wanted mask 0x%08x flags 0x%08x)\n", p.mask, p.flags); if (p.mask & ~r.writable_flags) - fprintf(stderr, "Which is expected, because writable " - "mask is 0x%08x.\n", r.writable_flags); + fprintf(stderr, + "Which is expected, because writable " + "mask is 0x%08x.\n", + r.writable_flags); return -1; } @@ -1817,10 +1812,10 @@ int cmd_rw_hash_pd(int argc, char *argv[]) fprintf(stderr, "Bad RW hash\n"); return -1; } - rwp[0] = (uint8_t) (val >> 0) & 0xff; - rwp[1] = (uint8_t) (val >> 8) & 0xff; - rwp[2] = (uint8_t) (val >> 16) & 0xff; - rwp[3] = (uint8_t) (val >> 24) & 0xff; + rwp[0] = (uint8_t)(val >> 0) & 0xff; + rwp[1] = (uint8_t)(val >> 8) & 0xff; + rwp[2] = (uint8_t)(val >> 16) & 0xff; + rwp[3] = (uint8_t)(val >> 24) & 0xff; rwp += 4; } rv = ec_command(EC_CMD_USB_PD_RW_HASH_ENTRY, 0, p, sizeof(*p), NULL, 0); @@ -1833,8 +1828,8 @@ int cmd_rwsig_status(int argc, char *argv[]) int rv; struct ec_response_rwsig_check_status resp; - rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0, - &resp, sizeof(resp)); + rv = ec_command(EC_CMD_RWSIG_CHECK_STATUS, 0, NULL, 0, &resp, + sizeof(resp)); if (rv < 0) return rv; @@ -1884,9 +1879,10 @@ enum rwsig_info_fields { RWSIG_INFO_FIELD_HASH_ALG = BIT(2), RWSIG_INFO_FIELD_KEY_IS_VALID = BIT(3), RWSIG_INFO_FIELD_KEY_ID = BIT(4), - RWSIG_INFO_FIELD_ALL = RWSIG_INFO_FIELD_SIG_ALG | - RWSIG_INFO_FIELD_KEY_VERSION | RWSIG_INFO_FIELD_HASH_ALG | - RWSIG_INFO_FIELD_KEY_IS_VALID | RWSIG_INFO_FIELD_KEY_ID + RWSIG_INFO_FIELD_ALL = + RWSIG_INFO_FIELD_SIG_ALG | RWSIG_INFO_FIELD_KEY_VERSION | + RWSIG_INFO_FIELD_HASH_ALG | RWSIG_INFO_FIELD_KEY_IS_VALID | + RWSIG_INFO_FIELD_KEY_ID }; static int rwsig_info(enum rwsig_info_fields fields) @@ -2071,7 +2067,6 @@ int cmd_sysinfo(int argc, char **argv) if (print_prefix) printf("Flags: "); printf("0x%08x\n", r.flags); - } if (fields & SYSINFO_FIELD_CURRENT_IMAGE) { @@ -2083,8 +2078,9 @@ int cmd_sysinfo(int argc, char **argv) return 0; sysinfo_error_usage: - fprintf(stderr, "Usage: %s " - "[flags|reset_flags|firmware_copy]\n", + fprintf(stderr, + "Usage: %s " + "[flags|reset_flags|firmware_copy]\n", argv[0]); return -1; } @@ -2139,8 +2135,8 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index) void *buffer; uint8_t *ptr; int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0; - int rsize = cmdver == 1 ? sizeof(*info) - : sizeof(struct ec_response_fp_info_v0); + int rsize = cmdver == 1 ? sizeof(*info) : + sizeof(struct ec_response_fp_info_v0); const int max_attempts = 3; int num_attempts; @@ -2153,7 +2149,7 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index) return NULL; if (index == FP_FRAME_INDEX_SIMPLE_IMAGE) { - size = (size_t)info->width * info->bpp/8 * info->height; + size = (size_t)info->width * info->bpp / 8 * info->height; index = FP_FRAME_INDEX_RAW_IMAGE; } else if (index == FP_FRAME_INDEX_RAW_IMAGE) { size = info->frame_size; @@ -2175,8 +2171,8 @@ static void *fp_download_frame(struct ec_response_fp_info *info, int index) num_attempts = 0; while (num_attempts < max_attempts) { num_attempts++; - rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p), - ptr, stride); + rv = ec_command(EC_CMD_FP_FRAME, 0, &p, sizeof(p), ptr, + stride); if (rv >= 0) break; if (rv == -EECRESULT - EC_RES_ACCESS_DENIED) @@ -2254,7 +2250,7 @@ int cmd_fp_mode(int argc, char *argv[]) printf("finger-up "); if (r.mode & FP_MODE_ENROLL_SESSION) printf("enroll%s ", - r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : ""); + r.mode & FP_MODE_ENROLL_IMAGE ? "+image" : ""); if (r.mode & FP_MODE_MATCH) printf("match "); if (r.mode & FP_MODE_CAPTURE) @@ -2308,7 +2304,7 @@ int cmd_fp_stats(int argc, char *argv[]) printf("Invalid\n"); else printf("%d us (finger: %d)\n", r.matching_time_us, - r.template_matched); + r.template_matched); printf("Last overall time: "); if (r.timestamps_invalid) @@ -2324,8 +2320,8 @@ int cmd_fp_info(int argc, char *argv[]) struct ec_response_fp_info r; int rv; int cmdver = ec_cmd_version_supported(EC_CMD_FP_INFO, 1) ? 1 : 0; - int rsize = cmdver == 1 ? sizeof(r) - : sizeof(struct ec_response_fp_info_v0); + int rsize = cmdver == 1 ? sizeof(r) : + sizeof(struct ec_response_fp_info_v0); uint16_t dead; rv = ec_command(EC_CMD_FP_INFO, cmdver, NULL, 0, &r, rsize); @@ -2333,7 +2329,7 @@ int cmd_fp_info(int argc, char *argv[]) return rv; printf("Fingerprint sensor: vendor %x product %x model %x version %x\n", - r.vendor_id, r.product_id, r.model_id, r.version); + r.vendor_id, r.product_id, r.model_id, r.version); printf("Image: size %dx%d %d bpp\n", r.width, r.height, r.bpp); printf("Error flags: %s%s%s%s\n", r.errors & FP_ERROR_NO_IRQ ? "NO_IRQ " : "", @@ -2438,7 +2434,8 @@ int cmd_fp_frame(int argc, char *argv[]) { struct ec_response_fp_info r; int idx = (argc == 2 && !strcasecmp(argv[1], "raw")) ? - FP_FRAME_INDEX_RAW_IMAGE : FP_FRAME_INDEX_SIMPLE_IMAGE; + FP_FRAME_INDEX_RAW_IMAGE : + FP_FRAME_INDEX_SIMPLE_IMAGE; uint8_t *buffer = (uint8_t *)(fp_download_frame(&r, idx)); uint8_t *ptr = buffer; int x, y; @@ -2473,8 +2470,8 @@ int cmd_fp_template(int argc, char *argv[]) struct ec_params_fp_template *p = (struct ec_params_fp_template *)(ec_outbuf); /* TODO(b/78544921): removing 32 bits is a workaround for the MCU bug */ - int max_chunk = ec_max_outsize - - offsetof(struct ec_params_fp_template, data) - 4; + int max_chunk = ec_max_outsize - + offsetof(struct ec_params_fp_template, data) - 4; int idx = -1; char *e; int size; @@ -2514,8 +2511,9 @@ int cmd_fp_template(int argc, char *argv[]) if (!size) p->size |= FP_TEMPLATE_COMMIT; memcpy(p->data, buffer + offset, tlen); - rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p, tlen + - offsetof(struct ec_params_fp_template, data), + rv = ec_command(EC_CMD_FP_TEMPLATE, 0, p, + tlen + offsetof(struct ec_params_fp_template, + data), NULL, 0); if (rv < 0) break; @@ -2548,8 +2546,8 @@ static int in_gfu_mode(int *opos, int port) p->port = port; p->svid_idx = 0; do { - ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), - ec_inbuf, ec_max_insize); + ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf, + ec_max_insize); if (!r->svid || (r->svid == USB_VID_GOOGLE)) break; p->svid_idx++; @@ -2599,8 +2597,7 @@ static int enter_gfu_mode(int port) p->opos = opos; p->cmd = PD_ENTER_MODE; - ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), - NULL, 0); + ec_command(EC_CMD_USB_PD_SET_AMODE, 0, p, sizeof(*p), NULL, 0); usleep(500000); /* sleep to allow time for set mode */ gfu_mode = in_gfu_mode(&opos, port); } @@ -2630,8 +2627,8 @@ int cmd_pd_device_info(int argc, char *argv[]) p->port = port; r1 = (struct ec_params_usb_pd_discovery_entry *)ec_inbuf; - rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_DISCOVERY, 0, p, sizeof(*p), ec_inbuf, + ec_max_insize); if (rv < 0) return rv; @@ -2648,8 +2645,8 @@ int cmd_pd_device_info(int argc, char *argv[]) } p->port = port; - rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_DEV_INFO, 0, p, sizeof(*p), ec_inbuf, + ec_max_insize); if (rv < 0) return rv; @@ -2714,8 +2711,8 @@ int cmd_flash_pd(int argc, char *argv[]) p->port = port; p->cmd = USB_PD_FW_ERASE_SIG; p->size = 0; - rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, - p, p->size + sizeof(*p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p), + NULL, 0); if (rv < 0) goto pd_flash_error; @@ -2726,8 +2723,8 @@ int cmd_flash_pd(int argc, char *argv[]) p->port = port; p->cmd = USB_PD_FW_REBOOT; p->size = 0; - rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, - p, p->size + sizeof(*p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p), + NULL, 0); if (rv < 0) goto pd_flash_error; @@ -2746,8 +2743,8 @@ int cmd_flash_pd(int argc, char *argv[]) p->port = port; p->cmd = USB_PD_FW_FLASH_ERASE; p->size = 0; - rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, - p, p->size + sizeof(*p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p), + NULL, 0); /* 3 secs should allow ample time for 2KB page erases at 40ms */ usleep(3000000); @@ -2765,8 +2762,8 @@ int cmd_flash_pd(int argc, char *argv[]) for (i = 0; i < fsize; i += step) { p->size = MIN(fsize - i, step); memcpy(data, buf + i, p->size); - rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, - p, p->size + sizeof(*p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, + p->size + sizeof(*p), NULL, 0); if (rv < 0) goto pd_flash_error; @@ -2784,8 +2781,8 @@ int cmd_flash_pd(int argc, char *argv[]) fprintf(stderr, "Rebooting PD into new RW\n"); p->cmd = USB_PD_FW_REBOOT; p->size = 0; - rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, - p, p->size + sizeof(*p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_FW_UPDATE, 0, p, p->size + sizeof(*p), + NULL, 0); if (rv < 0) goto pd_flash_error; @@ -2860,15 +2857,15 @@ int cmd_pd_get_amode(int argc, char *argv[]) p->svid_idx = 0; do { - ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), - ec_inbuf, ec_max_insize); + ec_command(EC_CMD_USB_PD_GET_AMODE, 0, p, sizeof(*p), ec_inbuf, + ec_max_insize); if (!r->svid) break; - printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ', - r->svid); + printf("%cSVID:0x%04x ", (r->opos) ? '*' : ' ', r->svid); for (i = 0; i < PDO_MODES; i++) { - printf("%c0x%08x ", (r->opos && (r->opos == i + 1)) ? - '*' : ' ', r->vdo[i]); + printf("%c0x%08x ", + (r->opos && (r->opos == i + 1)) ? '*' : ' ', + r->vdo[i]); } printf("\n"); p->svid_idx++; @@ -2899,7 +2896,6 @@ int cmd_serial_test(int argc, char *argv[]) return 0; } - int cmd_port_80_flood(int argc, char *argv[]) { int i; @@ -2971,8 +2967,8 @@ int cmd_smart_discharge(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p), - r, ec_max_insize); + rv = ec_command(EC_CMD_SMART_DISCHARGE, 0, p, sizeof(*p), r, + ec_max_insize); if (rv < 0) { perror("ERROR: EC_CMD_SMART_DISCHARGE failed"); return rv; @@ -2985,10 +2981,10 @@ int cmd_smart_discharge(int argc, char *argv[]) } printf("%-27s %5d h\n", "Hours to zero capacity:", r->hours_to_zero); - printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:", - r->dzone.stayup, cap > 0 ? r->dzone.stayup * 100 / cap : -1); - printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:", - r->dzone.cutoff, cap > 0 ? r->dzone.cutoff * 100 / cap : -1); + printf("%-27s %5d mAh (%d %%)\n", "Stay-up threshold:", r->dzone.stayup, + cap > 0 ? r->dzone.stayup * 100 / cap : -1); + printf("%-27s %5d mAh (%d %%)\n", "Cutoff threshold:", r->dzone.cutoff, + cap > 0 ? r->dzone.cutoff * 100 / cap : -1); printf("%-27s %5d uA\n", "Hibernate discharge rate:", r->drate.hibern); printf("%-27s %5d uA\n", "Cutoff discharge rate:", r->drate.cutoff); @@ -3042,8 +3038,8 @@ int cmd_stress_test(int argc, char *argv[]) } } - printf("Stress test tool version: %s %s %s\n", - CROS_ECTOOL_VERSION, DATE, BUILDER); + printf("Stress test tool version: %s %s %s\n", CROS_ECTOOL_VERSION, + DATE, BUILDER); start_time = time(NULL); last_update_time = start_time; @@ -3068,16 +3064,16 @@ int cmd_stress_test(int argc, char *argv[]) struct ec_response_hello hello_r; /* Request EC Version Strings */ - rv = ec_command(EC_CMD_GET_VERSION, 0, - NULL, 0, &ver_r, sizeof(ver_r)); + rv = ec_command(EC_CMD_GET_VERSION, 0, NULL, 0, &ver_r, + sizeof(ver_r)); if (rv < 0) { failures++; perror("ERROR: EC_CMD_GET_VERSION failed"); } - ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1] - = '\0'; - ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1] - = '\0'; + ver_r.version_string_ro[sizeof(ver_r.version_string_ro) - 1] = + '\0'; + ver_r.version_string_rw[sizeof(ver_r.version_string_rw) - 1] = + '\0'; if (strlen(ver_r.version_string_ro) == 0) { failures++; fprintf(stderr, "RO version string is empty\n"); @@ -3090,8 +3086,8 @@ int cmd_stress_test(int argc, char *argv[]) usleep(rand_r(&rand_seed) % max_sleep_usec); /* Request EC Build String */ - rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, - NULL, 0, ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_GET_BUILD_INFO, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) { failures++; perror("ERROR: EC_CMD_GET_BUILD_INFO failed"); @@ -3134,8 +3130,7 @@ int cmd_stress_test(int argc, char *argv[]) now = time(NULL); printf("Update: attempt %" PRIu64 " round %" PRIu64 " | took %.f seconds\n", - attempt, round, - difftime(now, last_update_time)); + attempt, round, difftime(now, last_update_time)); last_update_time = now; } @@ -3147,7 +3142,7 @@ int cmd_stress_test(int argc, char *argv[]) now = time(NULL); printf("End time: %s\n", ctime(&now)); printf("Total runtime: %.f seconds\n", - difftime(time(NULL), start_time)); + difftime(time(NULL), start_time)); printf("Total failures: %" PRIu64 "\n", failures); return 0; } @@ -3165,8 +3160,8 @@ int read_mapped_temperature(int id) } else if (id < EC_TEMP_SENSOR_ENTRIES) rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR + id); else if (read_mapped_mem8(EC_MEMMAP_THERMAL_VERSION) >= 2) - rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B + - id - EC_TEMP_SENSOR_ENTRIES); + rv = read_mapped_mem8(EC_MEMMAP_TEMP_SENSOR_B + id - + EC_TEMP_SENSOR_ENTRIES); else { /* Sensor in second bank, but second bank isn't supported */ rv = EC_TEMP_SENSOR_NOT_PRESENT; @@ -3181,8 +3176,8 @@ static int get_thermal_fan_percent(int temp, int sensor_id) int rv = 0; p.sensor_num = sensor_id; - rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r, + sizeof(r)); if (rv <= 0 || r.temp_fan_max == r.temp_fan_off) return -1; @@ -3191,7 +3186,7 @@ static int get_thermal_fan_percent(int temp, int sensor_id) if (temp > r.temp_fan_max) return 100; return 100 * (temp - r.temp_fan_off) / - (r.temp_fan_max - r.temp_fan_off); + (r.temp_fan_max - r.temp_fan_off); } static int cmd_temperature_print(int id, int mtemp) @@ -3202,8 +3197,8 @@ static int cmd_temperature_print(int id, int mtemp) int temp = mtemp + EC_TEMP_SENSOR_OFFSET; p.id = id; - rc = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), - &r, sizeof(r)); + rc = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), &r, + sizeof(r)); if (rc < 0) return rc; printf("%-20s %d K (= %d C) %11d%%\n", r.sensor_name, temp, @@ -3255,8 +3250,7 @@ int cmd_temperature(int argc, char *argv[]) return -1; } - if (id < 0 || - id >= EC_MAX_TEMP_SENSOR_ENTRIES) { + if (id < 0 || id >= EC_MAX_TEMP_SENSOR_ENTRIES) { printf("Sensor ID invalid.\n"); return -1; } @@ -3284,7 +3278,6 @@ int cmd_temperature(int argc, char *argv[]) } } - int cmd_temp_sensor_info(int argc, char *argv[]) { struct ec_params_temp_sensor_get_info p; @@ -3302,8 +3295,8 @@ int cmd_temp_sensor_info(int argc, char *argv[]) if (read_mapped_temperature(p.id) == EC_TEMP_SENSOR_NOT_PRESENT) continue; - rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, + sizeof(p), &r, sizeof(r)); if (rv < 0) continue; printf("%d: %d %s\n", p.id, r.sensor_type, @@ -3318,8 +3311,8 @@ int cmd_temp_sensor_info(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; @@ -3329,7 +3322,6 @@ int cmd_temp_sensor_info(int argc, char *argv[]) return 0; } - int cmd_thermal_get_threshold_v0(int argc, char *argv[]) { struct ec_params_thermal_get_threshold p; @@ -3338,8 +3330,8 @@ int cmd_thermal_get_threshold_v0(int argc, char *argv[]) int rv; if (argc != 3) { - fprintf(stderr, - "Usage: %s \n", argv[0]); + fprintf(stderr, "Usage: %s \n", + argv[0]); return -1; } @@ -3355,18 +3347,17 @@ int cmd_thermal_get_threshold_v0(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; - printf("Threshold %d for sensor type %d is %d K.\n", - p.threshold_id, p.sensor_type, r.value); + printf("Threshold %d for sensor type %d is %d K.\n", p.threshold_id, + p.sensor_type, r.value); return 0; } - int cmd_thermal_set_threshold_v0(int argc, char *argv[]) { struct ec_params_thermal_set_threshold p; @@ -3398,18 +3389,17 @@ int cmd_thermal_set_threshold_v0(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; - printf("Threshold %d for sensor type %d set to %d.\n", - p.threshold_id, p.sensor_type, p.value); + printf("Threshold %d for sensor type %d set to %d.\n", p.threshold_id, + p.sensor_type, p.value); return 0; } - int cmd_thermal_get_threshold_v1(int argc, char *argv[]) { struct ec_params_thermal_get_threshold_v1 p; @@ -3421,31 +3411,27 @@ int cmd_thermal_get_threshold_v1(int argc, char *argv[]) printf("sensor warn high halt fan_off fan_max name\n"); for (i = 0; i < EC_MAX_TEMP_SENSOR_ENTRIES; i++) { - - if (read_mapped_temperature(i) == - EC_TEMP_SENSOR_NOT_PRESENT) + if (read_mapped_temperature(i) == EC_TEMP_SENSOR_NOT_PRESENT) continue; /* ask for one */ p.sensor_num = i; - rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, - &p, sizeof(p), &r, sizeof(r)); - if (rv <= 0) /* stop on first failure */ + rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), + &r, sizeof(r)); + if (rv <= 0) /* stop on first failure */ break; /* ask for its name, too */ pi.id = i; - rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, - &pi, sizeof(pi), &ri, sizeof(ri)); + rv = ec_command(EC_CMD_TEMP_SENSOR_GET_INFO, 0, &pi, sizeof(pi), + &ri, sizeof(ri)); /* print what we know */ - printf(" %2d %3d %3d %3d %3d %3d %s\n", - i, + printf(" %2d %3d %3d %3d %3d %3d %s\n", i, r.temp_host[EC_TEMP_THRESH_WARN], r.temp_host[EC_TEMP_THRESH_HIGH], - r.temp_host[EC_TEMP_THRESH_HALT], - r.temp_fan_off, r.temp_fan_max, - rv > 0 ? ri.sensor_name : "?"); + r.temp_host[EC_TEMP_THRESH_HALT], r.temp_fan_off, + r.temp_fan_max, rv > 0 ? ri.sensor_name : "?"); } if (i) printf("(all temps in degrees Kelvin)\n"); @@ -3475,8 +3461,8 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[]) } p.sensor_num = n; - rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_THERMAL_GET_THRESHOLD, 1, &p, sizeof(p), &r, + sizeof(r)); if (rv <= 0) return rv; @@ -3496,7 +3482,7 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[]) case 2: case 3: case 4: - s.cfg.temp_host[i-2] = val; + s.cfg.temp_host[i - 2] = val; break; case 5: s.cfg.temp_fan_off = val; @@ -3507,8 +3493,8 @@ int cmd_thermal_set_threshold_v1(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1, - &s, sizeof(s), NULL, 0); + rv = ec_command(EC_CMD_THERMAL_SET_THRESHOLD, 1, &s, sizeof(s), NULL, + 0); return rv; } @@ -3535,7 +3521,6 @@ int cmd_thermal_set_threshold(int argc, char *argv[]) return -1; } - static int get_num_fans(void) { int idx, rv; @@ -3565,13 +3550,13 @@ int cmd_thermal_auto_fan_ctrl(int argc, char *argv[]) char *e; int cmdver = 1; - if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver) - || (argc == 1)) { + if (!ec_cmd_version_supported(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver) || + (argc == 1)) { /* If no argument is provided then enable auto fan ctrl */ /* for all fans by using version 0 of the host command */ - rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0, - NULL, 0, NULL, 0); + rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, 0, NULL, 0, NULL, + 0); if (rv < 0) return rv; @@ -3591,8 +3576,8 @@ int cmd_thermal_auto_fan_ctrl(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver, - &p_v1, sizeof(p_v1), NULL, 0); + rv = ec_command(EC_CMD_THERMAL_AUTO_FAN_CTRL, cmdver, &p_v1, + sizeof(p_v1), NULL, 0); if (rv < 0) return rv; @@ -3655,7 +3640,6 @@ int cmd_pwm_get_fan_rpm(int argc, char *argv[]) return 0; } - int cmd_pwm_set_fan_rpm(int argc, char *argv[]) { struct ec_params_pwm_set_fan_target_rpm_v1 p_v1; @@ -3670,8 +3654,7 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[]) cmdver = 0; if (argc != 2) { - fprintf(stderr, - "Usage: %s \n", argv[0]); + fprintf(stderr, "Usage: %s \n", argv[0]); return -1; } p_v0.rpm = strtol(argv[1], &e, 0); @@ -3680,8 +3663,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, - &p_v0, sizeof(p_v0), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0, + sizeof(p_v0), NULL, 0); if (rv < 0) return rv; @@ -3711,8 +3694,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[]) cmdver = 0; p_v0.rpm = p_v1.rpm; - rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, - &p_v0, sizeof(p_v0), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v0, + sizeof(p_v0), NULL, 0); if (rv < 0) return rv; @@ -3724,8 +3707,8 @@ int cmd_pwm_set_fan_rpm(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, - &p_v1, sizeof(p_v1), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_TARGET_RPM, cmdver, &p_v1, + sizeof(p_v1), NULL, 0); if (rv < 0) return rv; @@ -3740,8 +3723,8 @@ int cmd_pwm_get_keyboard_backlight(int argc, char *argv[]) struct ec_response_pwm_get_keyboard_backlight r; int rv; - rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, 0, NULL, 0, &r, + sizeof(r)); if (rv < 0) return rv; @@ -3753,7 +3736,6 @@ int cmd_pwm_get_keyboard_backlight(int argc, char *argv[]) return 0; } - int cmd_pwm_set_keyboard_backlight(int argc, char *argv[]) { struct ec_params_pwm_set_keyboard_backlight p; @@ -3770,8 +3752,8 @@ int cmd_pwm_set_keyboard_backlight(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, 0, &p, sizeof(p), + NULL, 0); if (rv < 0) return rv; @@ -3814,7 +3796,6 @@ int cmd_pwm_get_duty(int argc, char *argv[]) return 0; } - int cmd_pwm_set_duty(int argc, char *argv[]) { struct ec_params_pwm_set_duty p; @@ -3848,8 +3829,7 @@ int cmd_pwm_set_duty(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_DUTY, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_DUTY, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -3868,8 +3848,7 @@ int cmd_fanduty(int argc, char *argv[]) struct ec_params_pwm_set_fan_duty_v0 p_v0; if (argc != 2) { - fprintf(stderr, - "Usage: %s \n", argv[0]); + fprintf(stderr, "Usage: %s \n", argv[0]); return -1; } p_v0.percent = strtol(argv[1], &e, 0); @@ -3878,8 +3857,8 @@ int cmd_fanduty(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0, - &p_v0, sizeof(p_v0), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, 0, &p_v0, sizeof(p_v0), + NULL, 0); if (rv < 0) return rv; @@ -3890,9 +3869,9 @@ int cmd_fanduty(int argc, char *argv[]) if (argc > 3 || (argc == 2 && !strcmp(argv[1], "help")) || argc == 1) { printf("Usage: %s [idx] \n", argv[0]); printf("'%s 0 50' - Set fan 0 duty cycle to 50 percent\n", - argv[0]); + argv[0]); printf("'%s 30' - Set all fans duty cycle to 30 percent\n", - argv[0]); + argv[0]); return -1; } @@ -3911,8 +3890,8 @@ int cmd_fanduty(int argc, char *argv[]) cmdver = 0; p_v0.percent = p_v1.percent; - rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, - &p_v0, sizeof(p_v0), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v0, + sizeof(p_v0), NULL, 0); if (rv < 0) return rv; @@ -3924,8 +3903,8 @@ int cmd_fanduty(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, - &p_v1, sizeof(p_v1), NULL, 0); + rv = ec_command(EC_CMD_PWM_SET_FAN_DUTY, cmdver, &p_v1, + sizeof(p_v1), NULL, 0); if (rv < 0) return rv; @@ -3937,9 +3916,7 @@ int cmd_fanduty(int argc, char *argv[]) #define LBMSG(state) #state #include "lightbar_msg_list.h" -static const char * const lightbar_cmds[] = { - LIGHTBAR_MSG_LIST -}; +static const char *const lightbar_cmds[] = { LIGHTBAR_MSG_LIST }; #undef LBMSG /* Size of field in structure */ @@ -3958,36 +3935,36 @@ static const struct { { ST_CMD_SIZE, 0 }, { ST_CMD_SIZE, 0 }, { ST_CMD_SIZE, 0 }, - { ST_PRM_SIZE(set_brightness), 0}, - { ST_PRM_SIZE(seq), 0}, - { ST_PRM_SIZE(reg), 0}, - { ST_PRM_SIZE(set_rgb), 0}, + { ST_PRM_SIZE(set_brightness), 0 }, + { ST_PRM_SIZE(seq), 0 }, + { ST_PRM_SIZE(reg), 0 }, + { ST_PRM_SIZE(set_rgb), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_seq) }, - { ST_PRM_SIZE(demo), 0}, + { ST_PRM_SIZE(demo), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v0) }, - { ST_PRM_SIZE(set_params_v0), 0}, + { ST_PRM_SIZE(set_params_v0), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(version) }, { ST_CMD_SIZE, ST_RSP_SIZE(get_brightness) }, { ST_PRM_SIZE(get_rgb), ST_RSP_SIZE(get_rgb) }, { ST_CMD_SIZE, ST_RSP_SIZE(get_demo) }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v1) }, - { ST_PRM_SIZE(set_params_v1), 0}, - { ST_PRM_SIZE(set_program), 0}, - { ST_PRM_SIZE(manual_suspend_ctrl), 0}, + { ST_PRM_SIZE(set_params_v1), 0 }, + { ST_PRM_SIZE(set_program), 0 }, + { ST_PRM_SIZE(manual_suspend_ctrl), 0 }, { ST_CMD_SIZE, 0 }, { ST_CMD_SIZE, 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_timing) }, - { ST_PRM_SIZE(set_v2par_timing), 0}, + { ST_PRM_SIZE(set_v2par_timing), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_tap) }, - { ST_PRM_SIZE(set_v2par_tap), 0}, + { ST_PRM_SIZE(set_v2par_tap), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_osc) }, - { ST_PRM_SIZE(set_v2par_osc), 0}, + { ST_PRM_SIZE(set_v2par_osc), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_bright) }, - { ST_PRM_SIZE(set_v2par_bright), 0}, + { ST_PRM_SIZE(set_v2par_bright), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_thlds) }, - { ST_PRM_SIZE(set_v2par_thlds), 0}, + { ST_PRM_SIZE(set_v2par_thlds), 0 }, { ST_CMD_SIZE, ST_RSP_SIZE(get_params_v2_colors) }, - { ST_PRM_SIZE(set_v2par_colors), 0}, + { ST_PRM_SIZE(set_v2par_colors), 0 }, }; BUILD_ASSERT(ARRAY_SIZE(lb_command_paramcount) == LIGHTBAR_NUM_CMDS); @@ -4004,16 +3981,20 @@ static int lb_help(const char *cmd) printf(" %s init - load default vals\n", cmd); printf(" %s brightness [NUM] - get/set intensity(0-ff)\n", cmd); printf(" %s seq [NUM|SEQUENCE] - run given pattern" - " (no arg for list)\n", cmd); + " (no arg for list)\n", + cmd); printf(" %s CTRL REG VAL - set LED controller regs\n", cmd); printf(" %s LED RED GREEN BLUE - set color manually" - " (LED=4 for all)\n", cmd); + " (LED=4 for all)\n", + cmd); printf(" %s LED - get current LED color\n", cmd); printf(" %s demo [0|1] - turn demo mode on & off\n", cmd); printf(" %s params [setfile] - get params" - " (or set from file)\n", cmd); + " (or set from file)\n", + cmd); printf(" %s params2 group [setfile] - get params by group\n" - " (or set from file)\n", cmd); + " (or set from file)\n", + cmd); printf(" %s program file - load program from file\n", cmd); return 0; } @@ -4028,15 +4009,14 @@ static uint8_t lb_find_msg_by_name(const char *str) return LIGHTBAR_NUM_SEQUENCES; } -static int lb_do_cmd(enum lightbar_command cmd, - struct ec_params_lightbar *in, +static int lb_do_cmd(enum lightbar_command cmd, struct ec_params_lightbar *in, struct ec_response_lightbar *out) { int rv; in->cmd = cmd; - rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0, - in, lb_command_paramcount[cmd].insize, - out, lb_command_paramcount[cmd].outsize); + rv = ec_command(EC_CMD_LIGHTBAR_CMD, 0, in, + lb_command_paramcount[cmd].insize, out, + lb_command_paramcount[cmd].outsize); return (rv < 0 ? rv : 0); } @@ -4073,38 +4053,50 @@ static int lb_read_params_v0_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) - /* Do it */ - READ(1); p->google_ramp_up = val[0]; - READ(1); p->google_ramp_down = val[0]; - READ(1); p->s3s0_ramp_up = val[0]; - READ(1); p->s0_tick_delay[0] = val[0]; - READ(1); p->s0_tick_delay[1] = val[0]; - READ(1); p->s0a_tick_delay[0] = val[0]; - READ(1); p->s0a_tick_delay[1] = val[0]; - READ(1); p->s0s3_ramp_down = val[0]; - READ(1); p->s3_sleep_for = val[0]; - READ(1); p->s3_ramp_up = val[0]; - READ(1); p->s3_ramp_down = val[0]; - READ(1); p->new_s0 = val[0]; + READ(1); + p->google_ramp_up = val[0]; + READ(1); + p->google_ramp_down = val[0]; + READ(1); + p->s3s0_ramp_up = val[0]; + READ(1); + p->s0_tick_delay[0] = val[0]; + READ(1); + p->s0_tick_delay[1] = val[0]; + READ(1); + p->s0a_tick_delay[0] = val[0]; + READ(1); + p->s0a_tick_delay[1] = val[0]; + READ(1); + p->s0s3_ramp_down = val[0]; + READ(1); + p->s3_sleep_for = val[0]; + READ(1); + p->s3_ramp_up = val[0]; + READ(1); + p->s3_ramp_down = val[0]; + READ(1); + p->new_s0 = val[0]; READ(2); p->osc_min[0] = val[0]; @@ -4192,39 +4184,30 @@ static void lb_show_params_v0(const struct lightbar_params_v0 *p) printf("%d\t\t# .s3_ramp_up\n", p->s3_ramp_up); printf("%d\t\t# .s3_ramp_down\n", p->s3_ramp_down); printf("%d\t\t# .new_s0\n", p->new_s0); - printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", - p->osc_min[0], p->osc_min[1]); - printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", - p->osc_max[0], p->osc_max[1]); - printf("%d %d\t\t# .w_ofs (battery, AC)\n", - p->w_ofs[0], p->w_ofs[1]); + printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0], + p->osc_min[1]); + printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0], + p->osc_max[1]); + printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]); printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n", p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]); printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n", p->bright_bl_on_min[0], p->bright_bl_on_min[1]); printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n", p->bright_bl_on_max[0], p->bright_bl_on_max[1]); - printf("%d %d %d\t\t# .battery_threshold\n", - p->battery_threshold[0], - p->battery_threshold[1], - p->battery_threshold[2]); - printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", - p->s0_idx[0][0], p->s0_idx[0][1], - p->s0_idx[0][2], p->s0_idx[0][3]); - printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", - p->s0_idx[1][0], p->s0_idx[1][1], - p->s0_idx[1][2], p->s0_idx[1][3]); - printf("%d %d %d %d\t# .s3_idx[] (battery)\n", - p->s3_idx[0][0], p->s3_idx[0][1], - p->s3_idx[0][2], p->s3_idx[0][3]); - printf("%d %d %d %d\t# .s3_idx[] (AC)\n", - p->s3_idx[1][0], p->s3_idx[1][1], - p->s3_idx[1][2], p->s3_idx[1][3]); + printf("%d %d %d\t\t# .battery_threshold\n", p->battery_threshold[0], + p->battery_threshold[1], p->battery_threshold[2]); + printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0], + p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]); + printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0], + p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]); + printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0], + p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]); + printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0], + p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]); for (i = 0; i < ARRAY_SIZE(p->color); i++) - printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", - p->color[i].r, - p->color[i].g, - p->color[i].b, i); + printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r, + p->color[i].g, p->color[i].b, i); } static int lb_read_params_v1_from_file(const char *filename, @@ -4240,46 +4223,65 @@ static int lb_read_params_v1_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) - /* Do it */ - READ(1); p->google_ramp_up = val[0]; - READ(1); p->google_ramp_down = val[0]; - READ(1); p->s3s0_ramp_up = val[0]; - READ(1); p->s0_tick_delay[0] = val[0]; - READ(1); p->s0_tick_delay[1] = val[0]; - READ(1); p->s0a_tick_delay[0] = val[0]; - READ(1); p->s0a_tick_delay[1] = val[0]; - READ(1); p->s0s3_ramp_down = val[0]; - READ(1); p->s3_sleep_for = val[0]; - READ(1); p->s3_ramp_up = val[0]; - READ(1); p->s3_ramp_down = val[0]; - READ(1); p->tap_tick_delay = val[0]; - READ(1); p->tap_gate_delay = val[0]; - READ(1); p->tap_display_time = val[0]; - - READ(1); p->tap_pct_red = val[0]; - READ(1); p->tap_pct_green = val[0]; - READ(1); p->tap_seg_min_on = val[0]; - READ(1); p->tap_seg_max_on = val[0]; - READ(1); p->tap_seg_osc = val[0]; + READ(1); + p->google_ramp_up = val[0]; + READ(1); + p->google_ramp_down = val[0]; + READ(1); + p->s3s0_ramp_up = val[0]; + READ(1); + p->s0_tick_delay[0] = val[0]; + READ(1); + p->s0_tick_delay[1] = val[0]; + READ(1); + p->s0a_tick_delay[0] = val[0]; + READ(1); + p->s0a_tick_delay[1] = val[0]; + READ(1); + p->s0s3_ramp_down = val[0]; + READ(1); + p->s3_sleep_for = val[0]; + READ(1); + p->s3_ramp_up = val[0]; + READ(1); + p->s3_ramp_down = val[0]; + READ(1); + p->tap_tick_delay = val[0]; + READ(1); + p->tap_gate_delay = val[0]; + READ(1); + p->tap_display_time = val[0]; + + READ(1); + p->tap_pct_red = val[0]; + READ(1); + p->tap_pct_green = val[0]; + READ(1); + p->tap_seg_min_on = val[0]; + READ(1); + p->tap_seg_max_on = val[0]; + READ(1); + p->tap_seg_osc = val[0]; READ(3); p->tap_idx[0] = val[0]; p->tap_idx[1] = val[1]; @@ -4378,41 +4380,32 @@ static void lb_show_params_v1(const struct lightbar_params_v1 *p) printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on); printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on); printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc); - printf("%d %d %d\t\t# .tap_idx\n", - p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]); - printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", - p->osc_min[0], p->osc_min[1]); - printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", - p->osc_max[0], p->osc_max[1]); - printf("%d %d\t\t# .w_ofs (battery, AC)\n", - p->w_ofs[0], p->w_ofs[1]); + printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1], + p->tap_idx[2]); + printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0], + p->osc_min[1]); + printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0], + p->osc_max[1]); + printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]); printf("0x%02x 0x%02x\t# .bright_bl_off_fixed (battery, AC)\n", p->bright_bl_off_fixed[0], p->bright_bl_off_fixed[1]); printf("0x%02x 0x%02x\t# .bright_bl_on_min (battery, AC)\n", p->bright_bl_on_min[0], p->bright_bl_on_min[1]); printf("0x%02x 0x%02x\t# .bright_bl_on_max (battery, AC)\n", p->bright_bl_on_max[0], p->bright_bl_on_max[1]); - printf("%d %d %d\t# .battery_threshold\n", - p->battery_threshold[0], - p->battery_threshold[1], - p->battery_threshold[2]); - printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", - p->s0_idx[0][0], p->s0_idx[0][1], - p->s0_idx[0][2], p->s0_idx[0][3]); - printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", - p->s0_idx[1][0], p->s0_idx[1][1], - p->s0_idx[1][2], p->s0_idx[1][3]); - printf("%d %d %d %d\t# .s3_idx[] (battery)\n", - p->s3_idx[0][0], p->s3_idx[0][1], - p->s3_idx[0][2], p->s3_idx[0][3]); - printf("%d %d %d %d\t# .s3_idx[] (AC)\n", - p->s3_idx[1][0], p->s3_idx[1][1], - p->s3_idx[1][2], p->s3_idx[1][3]); + printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0], + p->battery_threshold[1], p->battery_threshold[2]); + printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0], + p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]); + printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0], + p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]); + printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0], + p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]); + printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0], + p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]); for (i = 0; i < ARRAY_SIZE(p->color); i++) - printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", - p->color[i].r, - p->color[i].g, - p->color[i].b, i); + printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r, + p->color[i].g, p->color[i].b, i); } static int lb_rd_timing_v2par_from_file(const char *filename, @@ -4427,38 +4420,53 @@ static int lb_rd_timing_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) - READ(1); p->google_ramp_up = val[0]; - READ(1); p->google_ramp_down = val[0]; - READ(1); p->s3s0_ramp_up = val[0]; - READ(1); p->s0_tick_delay[0] = val[0]; - READ(1); p->s0_tick_delay[1] = val[0]; - READ(1); p->s0a_tick_delay[0] = val[0]; - READ(1); p->s0a_tick_delay[1] = val[0]; - READ(1); p->s0s3_ramp_down = val[0]; - READ(1); p->s3_sleep_for = val[0]; - READ(1); p->s3_ramp_up = val[0]; - READ(1); p->s3_ramp_down = val[0]; - READ(1); p->tap_tick_delay = val[0]; - READ(1); p->tap_gate_delay = val[0]; - READ(1); p->tap_display_time = val[0]; + READ(1); + p->google_ramp_up = val[0]; + READ(1); + p->google_ramp_down = val[0]; + READ(1); + p->s3s0_ramp_up = val[0]; + READ(1); + p->s0_tick_delay[0] = val[0]; + READ(1); + p->s0_tick_delay[1] = val[0]; + READ(1); + p->s0a_tick_delay[0] = val[0]; + READ(1); + p->s0a_tick_delay[1] = val[0]; + READ(1); + p->s0s3_ramp_down = val[0]; + READ(1); + p->s3_sleep_for = val[0]; + READ(1); + p->s3_ramp_up = val[0]; + READ(1); + p->s3_ramp_down = val[0]; + READ(1); + p->tap_tick_delay = val[0]; + READ(1); + p->tap_gate_delay = val[0]; + READ(1); + p->tap_display_time = val[0]; #undef READ /* Yay */ @@ -4483,29 +4491,35 @@ static int lb_rd_tap_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) - READ(1); p->tap_pct_red = val[0]; - READ(1); p->tap_pct_green = val[0]; - READ(1); p->tap_seg_min_on = val[0]; - READ(1); p->tap_seg_max_on = val[0]; - READ(1); p->tap_seg_osc = val[0]; + READ(1); + p->tap_pct_red = val[0]; + READ(1); + p->tap_pct_green = val[0]; + READ(1); + p->tap_seg_min_on = val[0]; + READ(1); + p->tap_seg_max_on = val[0]; + READ(1); + p->tap_seg_osc = val[0]; READ(3); p->tap_idx[0] = val[0]; p->tap_idx[1] = val[1]; @@ -4534,22 +4548,23 @@ static int lb_rd_osc_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) READ(2); @@ -4585,22 +4600,23 @@ static int lb_rd_bright_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) READ(2); @@ -4638,22 +4654,23 @@ static int lb_rd_thlds_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) READ(3); @@ -4685,22 +4702,23 @@ static int lb_rd_colors_v2par_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) READ(4); @@ -4770,18 +4788,17 @@ static void lb_show_v2par_tap(const struct lightbar_params_v2_tap *p) printf("%d\t\t# .tap_seg_min_on\n", p->tap_seg_min_on); printf("%d\t\t# .tap_seg_max_on\n", p->tap_seg_max_on); printf("%d\t\t# .tap_seg_osc\n", p->tap_seg_osc); - printf("%d %d %d\t\t# .tap_idx\n", - p->tap_idx[0], p->tap_idx[1], p->tap_idx[2]); + printf("%d %d %d\t\t# .tap_idx\n", p->tap_idx[0], p->tap_idx[1], + p->tap_idx[2]); } static void lb_show_v2par_osc(const struct lightbar_params_v2_oscillation *p) { - printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", - p->osc_min[0], p->osc_min[1]); - printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", - p->osc_max[0], p->osc_max[1]); - printf("%d %d\t\t# .w_ofs (battery, AC)\n", - p->w_ofs[0], p->w_ofs[1]); + printf("0x%02x 0x%02x\t# .osc_min (battery, AC)\n", p->osc_min[0], + p->osc_min[1]); + printf("0x%02x 0x%02x\t# .osc_max (battery, AC)\n", p->osc_max[0], + p->osc_max[1]); + printf("%d %d\t\t# .w_ofs (battery, AC)\n", p->w_ofs[0], p->w_ofs[1]); } static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p) @@ -4796,34 +4813,26 @@ static void lb_show_v2par_bright(const struct lightbar_params_v2_brightness *p) static void lb_show_v2par_thlds(const struct lightbar_params_v2_thresholds *p) { - printf("%d %d %d\t# .battery_threshold\n", - p->battery_threshold[0], - p->battery_threshold[1], - p->battery_threshold[2]); + printf("%d %d %d\t# .battery_threshold\n", p->battery_threshold[0], + p->battery_threshold[1], p->battery_threshold[2]); } static void lb_show_v2par_colors(const struct lightbar_params_v2_colors *p) { int i; - printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", - p->s0_idx[0][0], p->s0_idx[0][1], - p->s0_idx[0][2], p->s0_idx[0][3]); - printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", - p->s0_idx[1][0], p->s0_idx[1][1], - p->s0_idx[1][2], p->s0_idx[1][3]); - printf("%d %d %d %d\t# .s3_idx[] (battery)\n", - p->s3_idx[0][0], p->s3_idx[0][1], - p->s3_idx[0][2], p->s3_idx[0][3]); - printf("%d %d %d %d\t# .s3_idx[] (AC)\n", - p->s3_idx[1][0], p->s3_idx[1][1], - p->s3_idx[1][2], p->s3_idx[1][3]); + printf("%d %d %d %d\t\t# .s0_idx[] (battery)\n", p->s0_idx[0][0], + p->s0_idx[0][1], p->s0_idx[0][2], p->s0_idx[0][3]); + printf("%d %d %d %d\t\t# .s0_idx[] (AC)\n", p->s0_idx[1][0], + p->s0_idx[1][1], p->s0_idx[1][2], p->s0_idx[1][3]); + printf("%d %d %d %d\t# .s3_idx[] (battery)\n", p->s3_idx[0][0], + p->s3_idx[0][1], p->s3_idx[0][2], p->s3_idx[0][3]); + printf("%d %d %d %d\t# .s3_idx[] (AC)\n", p->s3_idx[1][0], + p->s3_idx[1][1], p->s3_idx[1][2], p->s3_idx[1][3]); for (i = 0; i < ARRAY_SIZE(p->color); i++) - printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", - p->color[i].r, - p->color[i].g, - p->color[i].b, i); + printf("0x%02x 0x%02x 0x%02x\t# color[%d]\n", p->color[i].r, + p->color[i].g, p->color[i].b, i); } static int lb_load_program(const char *filename, struct lightbar_program *prog) @@ -4834,19 +4843,18 @@ static int lb_load_program(const char *filename, struct lightbar_program *prog) fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } rc = fseek(fp, 0, SEEK_END); if (rc) { - fprintf(stderr, "Couldn't find end of file %s", - filename); + fprintf(stderr, "Couldn't find end of file %s", filename); fclose(fp); return 1; } - rc = (int) ftell(fp); + rc = (int)ftell(fp); if (rc > EC_LB_PROG_LEN) { fprintf(stderr, "File %s is too long, aborting\n", filename); fclose(fp); @@ -4870,12 +4878,10 @@ static int cmd_lightbar_params_v0(int argc, char **argv) int r; if (argc > 2) { - r = lb_read_params_v0_from_file(argv[2], - ¶m.set_params_v0); + r = lb_read_params_v0_from_file(argv[2], ¶m.set_params_v0); if (r) return r; - return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0, - ¶m, &resp); + return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V0, ¶m, &resp); } r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V0, ¶m, &resp); if (!r) @@ -4890,12 +4896,10 @@ static int cmd_lightbar_params_v1(int argc, char **argv) int r; if (argc > 2) { - r = lb_read_params_v1_from_file(argv[2], - ¶m.set_params_v1); + r = lb_read_params_v1_from_file(argv[2], ¶m.set_params_v1); if (r) return r; - return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1, - ¶m, &resp); + return lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V1, ¶m, &resp); } r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V1, ¶m, &resp); if (!r) @@ -4944,8 +4948,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv) &p.set_v2par_timing); if (r) return r; - r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING, - &p, &resp); + r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TIMING, &p, + &resp); if (r) return r; } @@ -4959,8 +4963,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv) &p.set_v2par_tap); if (r) return r; - r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP, - &p, &resp); + r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_TAP, &p, + &resp); if (r) return r; } @@ -4990,13 +4994,12 @@ static int cmd_lightbar_params_v2(int argc, char **argv) &p.set_v2par_bright); if (r) return r; - r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS, - &p, &resp); + r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS, &p, + &resp); if (r) return r; } - r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p, - &resp); + r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS, &p, &resp); if (r) return r; lb_show_v2par_bright(&resp.get_params_v2_bright); @@ -5006,13 +5009,12 @@ static int cmd_lightbar_params_v2(int argc, char **argv) &p.set_v2par_thlds); if (r) return r; - r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS, - &p, &resp); + r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS, &p, + &resp); if (r) return r; } - r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p, - &resp); + r = lb_do_cmd(LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS, &p, &resp); if (r) return r; lb_show_v2par_thlds(&resp.get_params_v2_thlds); @@ -5022,8 +5024,8 @@ static int cmd_lightbar_params_v2(int argc, char **argv) &p.set_v2par_colors); if (r) return r; - r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS, - &p, &resp); + r = lb_do_cmd(LIGHTBAR_CMD_SET_PARAMS_V2_COLORS, &p, + &resp); if (r) return r; } @@ -5044,14 +5046,13 @@ static int cmd_lightbar(int argc, char **argv) struct ec_params_lightbar param; struct ec_response_lightbar resp; - if (1 == argc) { /* no args = dump 'em all */ + if (1 == argc) { /* no args = dump 'em all */ r = lb_do_cmd(LIGHTBAR_CMD_DUMP, ¶m, &resp); if (r) return r; for (i = 0; i < ARRAY_SIZE(resp.dump.vals); i++) { printf(" %02x %02x %02x\n", - resp.dump.vals[i].reg, - resp.dump.vals[i].ic0, + resp.dump.vals[i].reg, resp.dump.vals[i].ic0, resp.dump.vals[i].ic1); } return 0; @@ -5087,8 +5088,8 @@ static int cmd_lightbar(int argc, char **argv) if (!strcasecmp(argv[1], "version")) { r = lb_do_cmd(LIGHTBAR_CMD_VERSION, ¶m, &resp); if (!r) - printf("version %d flags 0x%x\n", - resp.version.num, resp.version.flags); + printf("version %d flags 0x%x\n", resp.version.num, + resp.version.flags); return r; } @@ -5097,12 +5098,11 @@ static int cmd_lightbar(int argc, char **argv) int rv; if (argc > 2) { param.set_brightness.num = 0xff & - strtoull(argv[2], &e, 16); - return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS, - ¶m, &resp); + strtoull(argv[2], &e, 16); + return lb_do_cmd(LIGHTBAR_CMD_SET_BRIGHTNESS, ¶m, + &resp); } - rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS, - ¶m, &resp); + rv = lb_do_cmd(LIGHTBAR_CMD_GET_BRIGHTNESS, ¶m, &resp); if (rv) return rv; printf("%02x\n", resp.get_brightness.num); @@ -5177,10 +5177,8 @@ static int cmd_lightbar(int argc, char **argv) r = lb_do_cmd(LIGHTBAR_CMD_GET_RGB, ¶m, &resp); if (r) return r; - printf("%02x %02x %02x\n", - resp.get_rgb.red, - resp.get_rgb.green, - resp.get_rgb.blue); + printf("%02x %02x %02x\n", resp.get_rgb.red, + resp.get_rgb.green, resp.get_rgb.blue); return 0; } } @@ -5193,7 +5191,10 @@ static int cmd_lightbar(int argc, char **argv) #define ST_PRM_SIZE(SUBCMD) \ (ST_CMD_SIZE + ST_FLD_SIZE(ec_params_motion_sense, SUBCMD)) #define ST_RSP_SIZE(SUBCMD) ST_FLD_SIZE(ec_response_motion_sense, SUBCMD) -#define ST_BOTH_SIZES(SUBCMD) { ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) } +#define ST_BOTH_SIZES(SUBCMD) \ + { \ + ST_PRM_SIZE(SUBCMD), ST_RSP_SIZE(SUBCMD) \ + } /* * For ectool only, assume no more than 16 sensors. More advanced @@ -5206,22 +5207,17 @@ static const struct { uint8_t outsize; uint8_t insize; } ms_command_sizes[] = { - { - ST_PRM_SIZE(dump), - ST_RSP_SIZE(dump) + - sizeof(struct ec_response_motion_sensor_data) * - ECTOOL_MAX_SENSOR - }, + { ST_PRM_SIZE(dump), + ST_RSP_SIZE(dump) + sizeof(struct ec_response_motion_sensor_data) * + ECTOOL_MAX_SENSOR }, ST_BOTH_SIZES(info_4), ST_BOTH_SIZES(ec_rate), ST_BOTH_SIZES(sensor_odr), ST_BOTH_SIZES(sensor_range), ST_BOTH_SIZES(kb_wake_angle), ST_BOTH_SIZES(data), - { - ST_CMD_SIZE, - ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR - }, + { ST_CMD_SIZE, + ST_RSP_SIZE(fifo_info) + sizeof(uint16_t) * ECTOOL_MAX_SENSOR }, ST_BOTH_SIZES(fifo_flush), ST_BOTH_SIZES(fifo_read), ST_BOTH_SIZES(perform_calib), @@ -5247,40 +5243,43 @@ static int ms_help(const char *cmd) { printf("Usage:\n"); printf(" %s - dump all motion data\n", - cmd); + cmd); printf(" %s active - print active flag\n", cmd); printf(" %s info NUM - print sensor info\n", cmd); printf(" %s ec_rate NUM [RATE_MS] - set/get sample rate\n", - cmd); - printf(" %s odr NUM [ODR [ROUNDUP]] - set/get sensor ODR\n", - cmd); + cmd); + printf(" %s odr NUM [ODR [ROUNDUP]] - set/get sensor ODR\n", cmd); printf(" %s range NUM [RANGE [ROUNDUP]] - set/get sensor range\n", - cmd); + cmd); printf(" %s offset NUM [-- X Y Z [TEMP]] - set/get sensor offset\n", - cmd); + cmd); printf(" %s kb_wake NUM - set/get KB wake ang\n", - cmd); + cmd); printf(" %s fifo_info - print fifo info\n", cmd); printf(" %s fifo_int_enable [0/1] - enable/disable/get fifo " - "interrupt status\n", cmd); + "interrupt status\n", + cmd); printf(" %s fifo_read MAX_DATA - read fifo data\n", cmd); printf(" %s fifo_flush NUM - trigger fifo interrupt\n", - cmd); + cmd); printf(" %s list_activities - list supported " - "activities\n", cmd); + "activities\n", + cmd); printf(" %s set_activity ACT EN - enable/disable activity\n", - cmd); + cmd); printf(" %s get_activity ACT - get activity status\n", - cmd); + cmd); printf(" %s lid_angle - print lid angle\n", cmd); printf(" %s spoof -- NUM [0/1] [X Y Z] - enable/disable spoofing\n", - cmd); + cmd); printf(" %s spoof -- NUM activity ACT [0/1] [STATE] - enable/disable " - "activity spoofing\n", cmd); + "activity spoofing\n", + cmd); printf(" %s tablet_mode_angle ANG HYS - set/get tablet mode " - "angle\n", cmd); + "angle\n", + cmd); printf(" %s calibrate NUM - run sensor calibration\n", - cmd); + cmd); return 0; } @@ -5291,11 +5290,9 @@ static void motionsense_display_activities(uint32_t activities) printf("%d: Significant motion\n", MOTIONSENSE_ACTIVITY_SIG_MOTION); if (activities & BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP)) - printf("%d: Double tap\n", - MOTIONSENSE_ACTIVITY_DOUBLE_TAP); + printf("%d: Double tap\n", MOTIONSENSE_ACTIVITY_DOUBLE_TAP); if (activities & BIT(MOTIONSENSE_ACTIVITY_ORIENTATION)) - printf("%d: Orientation\n", - MOTIONSENSE_ACTIVITY_ORIENTATION); + printf("%d: Orientation\n", MOTIONSENSE_ACTIVITY_ORIENTATION); if (activities & BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION)) printf("%d: Body Detection\n", MOTIONSENSE_ACTIVITY_BODY_DETECTION); @@ -5316,32 +5313,30 @@ static int cmd_motionsense(int argc, char **argv) * for kernel_CrosECSysfsAccel. */ const char *motion_status_string[2][2] = { - { "Motion sensing inactive", "0"}, - { "Motion sensing active", "1"}, + { "Motion sensing inactive", "0" }, + { "Motion sensing active", "1" }, }; /* No motionsense command has more than 7 args. */ if (argc > 7) return ms_help(argv[0]); - if ((argc == 1) || - (argc == 2 && !strcasecmp(argv[1], "active"))) { + if ((argc == 1) || (argc == 2 && !strcasecmp(argv[1], "active"))) { param.cmd = MOTIONSENSE_CMD_DUMP; param.dump.max_sensor_count = ECTOOL_MAX_SENSOR; - rv = ec_command( - EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv > 0) { - printf("%s\n", motion_status_string[ - !!(resp->dump.module_flags & - MOTIONSENSE_MODULE_FLAG_ACTIVE)][ - status_only]); + printf("%s\n", motion_status_string[!!( + resp->dump.module_flags & + MOTIONSENSE_MODULE_FLAG_ACTIVE)] + [status_only]); if (status_only) return 0; if (resp->dump.sensor_count > ECTOOL_MAX_SENSOR) { printf("Too many sensors to handle: %d", - resp->dump.sensor_count); + resp->dump.sensor_count); return -1; } for (i = 0; i < resp->dump.sensor_count; i++) { @@ -5353,11 +5348,11 @@ static int cmd_motionsense(int argc, char **argv) */ printf("Sensor %d: ", i); if (resp->dump.sensor[i].flags & - MOTIONSENSE_SENSOR_FLAG_PRESENT) + MOTIONSENSE_SENSOR_FLAG_PRESENT) printf("%d\t%d\t%d\n", - resp->dump.sensor[i].data[0], - resp->dump.sensor[i].data[1], - resp->dump.sensor[i].data[2]); + resp->dump.sensor[i].data[0], + resp->dump.sensor[i].data[1], + resp->dump.sensor[i].data[2]); else printf("None\n"); } @@ -5381,9 +5376,9 @@ static int cmd_motionsense(int argc, char **argv) return -1; } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, version, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5530,11 +5525,11 @@ static int cmd_motionsense(int argc, char **argv) if (version >= 3) { printf("Min Frequency: %d mHz\n", - resp->info_3.min_frequency); + resp->info_3.min_frequency); printf("Max Frequency: %d mHz\n", - resp->info_3.max_frequency); + resp->info_3.max_frequency); printf("FIFO Max Event Count: %d\n", - resp->info_3.fifo_max_event_count); + resp->info_3.fifo_max_event_count); } if (version >= 4) { printf("Flags: %d\n", @@ -5559,9 +5554,9 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5597,9 +5592,9 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5635,9 +5630,9 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5658,9 +5653,9 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5681,16 +5676,16 @@ static int cmd_motionsense(int argc, char **argv) EC_MOTION_SENSE_NO_VALUE; if (argc == 4) { - param.tablet_mode_threshold.lid_angle = strtol(argv[2], - &e, 0); + param.tablet_mode_threshold.lid_angle = + strtol(argv[2], &e, 0); if (e && *e) { fprintf(stderr, "Bad %s arg.\n", argv[2]); return -1; } - param.tablet_mode_threshold.hys_degree = strtol(argv[3], - &e, 0); + param.tablet_mode_threshold.hys_degree = + strtol(argv[3], &e, 0); if (e && *e) { fprintf(stderr, "Bad %s arg.\n", argv[3]); return -1; @@ -5699,9 +5694,9 @@ static int cmd_motionsense(int argc, char **argv) return ms_help(argv[0]); } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5718,17 +5713,17 @@ static int cmd_motionsense(int argc, char **argv) param.cmd = MOTIONSENSE_CMD_DUMP; param.dump.max_sensor_count = 0; - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; sensor_count = resp->dump.sensor_count; param.cmd = MOTIONSENSE_CMD_FIFO_INFO; - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5750,9 +5745,9 @@ static int cmd_motionsense(int argc, char **argv) param.fifo_int_enable.enable = strtol(argv[2], &e, 0); else param.fifo_int_enable.enable = EC_MOTION_SENSE_NO_VALUE; - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5768,7 +5763,7 @@ static int cmd_motionsense(int argc, char **argv) } fifo_read_buffer = { .number_data = UINT32_MAX, }; - int print_data = 0, max_data = strtol(argv[2], &e, 0); + int print_data = 0, max_data = strtol(argv[2], &e, 0); if (e && *e) { fprintf(stderr, "Bad %s arg.\n", argv[2]); @@ -5782,8 +5777,7 @@ static int cmd_motionsense(int argc, char **argv) MIN(ARRAY_SIZE(fifo_read_buffer.data), max_data - print_data); - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, ms_command_sizes[param.cmd].outsize, &fifo_read_buffer, ec_max_insize); if (rv < 0) @@ -5793,24 +5787,21 @@ static int cmd_motionsense(int argc, char **argv) for (i = 0; i < fifo_read_buffer.number_data; i++) { vector = &fifo_read_buffer.data[i]; if (vector->flags & - (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP | - MOTIONSENSE_SENSOR_FLAG_FLUSH)) { - + (MOTIONSENSE_SENSOR_FLAG_TIMESTAMP | + MOTIONSENSE_SENSOR_FLAG_FLUSH)) { printf("Timestamp:%" PRIx32 "%s\n", - vector->timestamp, - (vector->flags & - MOTIONSENSE_SENSOR_FLAG_FLUSH ? - " - Flush" : "")); + vector->timestamp, + (vector->flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ? + " - Flush" : + "")); } else { printf("Sensor %d: %d\t%d\t%d " "(as uint16: %u\t%u\t%u)\n", - vector->sensor_num, - vector->data[0], - vector->data[1], - vector->data[2], - vector->data[0], - vector->data[1], - vector->data[2]); + vector->sensor_num, + vector->data[0], vector->data[1], + vector->data[2], vector->data[0], + vector->data[1], + vector->data[2]); } } } @@ -5825,9 +5816,9 @@ static int cmd_motionsense(int argc, char **argv) return -1; } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); return rv < 0 ? rv : 0; } @@ -5841,18 +5832,18 @@ static int cmd_motionsense(int argc, char **argv) return -1; } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; printf("--- Calibrated well ---\n"); printf("New offset vector: X:%d, Y:%d, Z:%d\n", - resp->perform_calib.offset[0], - resp->perform_calib.offset[1], - resp->perform_calib.offset[2]); + resp->perform_calib.offset[0], + resp->perform_calib.offset[1], + resp->perform_calib.offset[2]); if ((uint16_t)resp->perform_calib.temp == EC_MOTION_SENSE_INVALID_CALIB_TEMP) printf("Temperature at calibration unknown\n"); @@ -5878,19 +5869,24 @@ static int cmd_motionsense(int argc, char **argv) /* Regarded as a command to set offset */ if (argc >= 6 && argc < 8) { /* Set offset : X, Y, Z */ - param.sensor_offset.flags = MOTION_SENSE_SET_OFFSET; + param.sensor_offset.flags = + MOTION_SENSE_SET_OFFSET; for (i = 0; i < 3; i++) { - param.sensor_offset.offset[i] = strtol(argv[3+i], &e, 0); + param.sensor_offset.offset[i] = + strtol(argv[3 + i], &e, 0); if (e && *e) { - fprintf(stderr, "Bad %s arg.\n", argv[3+i]); + fprintf(stderr, "Bad %s arg.\n", + argv[3 + i]); return -1; } } if (argc == 7) { /* Set offset : Temperature */ - param.sensor_offset.temp = strtol(argv[6], &e, 0); + param.sensor_offset.temp = + strtol(argv[6], &e, 0); if (e && *e) { - fprintf(stderr, "Bad %s arg.\n", argv[6]); + fprintf(stderr, "Bad %s arg.\n", + argv[6]); return -1; } } @@ -5899,17 +5895,17 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 1, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; printf("Offset vector: X:%d, Y:%d, Z:%d\n", - resp->sensor_offset.offset[0], - resp->sensor_offset.offset[1], - resp->sensor_offset.offset[2]); + resp->sensor_offset.offset[0], + resp->sensor_offset.offset[1], + resp->sensor_offset.offset[2]); if ((uint16_t)resp->sensor_offset.temp == EC_MOTION_SENSE_INVALID_CALIB_TEMP) printf("temperature at calibration unknown\n"); @@ -5922,9 +5918,9 @@ static int cmd_motionsense(int argc, char **argv) if (argc == 2 && !strcasecmp(argv[1], "list_activities")) { param.cmd = MOTIONSENSE_CMD_LIST_ACTIVITIES; - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -5939,9 +5935,9 @@ static int cmd_motionsense(int argc, char **argv) param.set_activity.activity = strtol(argv[2], &e, 0); param.set_activity.enable = strtol(argv[3], &e, 0); - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; return 0; @@ -5950,9 +5946,9 @@ static int cmd_motionsense(int argc, char **argv) param.cmd = MOTIONSENSE_CMD_GET_ACTIVITY; param.get_activity.activity = strtol(argv[2], &e, 0); - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; printf("State: %d\n", resp->get_activity.state); @@ -5960,9 +5956,9 @@ static int cmd_motionsense(int argc, char **argv) } if (argc == 2 && !strcasecmp(argv[1], "lid_angle")) { param.cmd = MOTIONSENSE_CMD_LID_ANGLE; - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -6023,7 +6019,7 @@ static int cmd_motionsense(int argc, char **argv) } else if (argc != 5) { return ms_help(argv[0]); } - /* spoof accel data */ + /* spoof accel data */ } else if (argc >= 4) { int enable, i; int16_t val; @@ -6049,10 +6045,10 @@ static int cmd_motionsense(int argc, char **argv) param.spoof.spoof_enable = MOTIONSENSE_SPOOF_MODE_CUSTOM; for (i = 0; i < 3; i++) { - val = strtol(argv[4+i], &e, 0); + val = strtol(argv[4 + i], &e, 0); if (e && *e) { fprintf(stderr, "Bad %s arg.\n", - argv[4+i]); + argv[4 + i]); return -1; } param.spoof.components[i] = val; @@ -6065,9 +6061,9 @@ static int cmd_motionsense(int argc, char **argv) } } - rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, - ¶m, ms_command_sizes[param.cmd].outsize, - resp, ms_command_sizes[param.cmd].insize); + rv = ec_command(EC_CMD_MOTION_SENSE_CMD, 2, ¶m, + ms_command_sizes[param.cmd].outsize, resp, + ms_command_sizes[param.cmd].insize); if (rv < 0) return rv; @@ -6092,8 +6088,8 @@ int cmd_next_event(int argc, char *argv[]) int rv; int i; - rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0, - NULL, 0, rdata, ec_max_insize); + rv = ec_command(EC_CMD_GET_NEXT_EVENT, 0, NULL, 0, rdata, + ec_max_insize); if (rv < 0) return rv; @@ -6146,7 +6142,8 @@ int cmd_led(int argc, char *argv[]) if (argc < 3) { fprintf(stderr, "Usage: %s | =...>\n", argv[0]); + "off | | =...>\n", + argv[0]); return -1; } @@ -6162,16 +6159,15 @@ int cmd_led(int argc, char *argv[]) if (!strcasecmp(argv[2], "query")) { p.flags = EC_LED_FLAGS_QUERY; - rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_LED_CONTROL, 1, &p, sizeof(p), &r, + sizeof(r)); printf("Brightness range for LED %d:\n", p.led_id); if (rv < 0) { fprintf(stderr, "Error: Unsupported LED.\n"); return rv; } for (i = 0; i < EC_LED_COLOR_COUNT; ++i) - printf("\t%s\t: 0x%x\n", - led_color_names[i], + printf("\t%s\t: 0x%x\n", led_color_names[i], r.brightness_range[i]); return 0; } @@ -6212,7 +6208,6 @@ int cmd_led(int argc, char *argv[]) return (rv < 0 ? rv : 0); } - int cmd_usb_charge_set_mode(int argc, char *argv[]) { struct ec_params_usb_charge_set_mode p; @@ -6238,18 +6233,17 @@ int cmd_usb_charge_set_mode(int argc, char *argv[]) p.inhibit_charge = 0; if (argc == 4) { p.inhibit_charge = strtol(argv[3], &e, 0); - if ((e && *e) || (p.inhibit_charge != 0 && - p.inhibit_charge != 1)) { + if ((e && *e) || + (p.inhibit_charge != 0 && p.inhibit_charge != 1)) { fprintf(stderr, "Bad value\n"); return -1; } } printf("Setting port %d to mode %d inhibit_charge %d...\n", - p.usb_port_id, p.mode, p.inhibit_charge); + p.usb_port_id, p.mode, p.inhibit_charge); - rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_USB_CHARGE_SET_MODE, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -6257,7 +6251,6 @@ int cmd_usb_charge_set_mode(int argc, char *argv[]) return 0; } - int cmd_usb_mux(int argc, char *argv[]) { struct ec_params_usb_mux p; @@ -6275,8 +6268,7 @@ int cmd_usb_mux(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_USB_MUX, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_USB_MUX, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -6285,13 +6277,12 @@ int cmd_usb_mux(int argc, char *argv[]) return 0; } - int cmd_usb_pd(int argc, char *argv[]) { - const char *role_str[] = {"", "toggle", "toggle-off", "sink", "source", - "freeze"}; - const char *mux_str[] = {"", "none", "usb", "dp", "dock", "auto"}; - const char *swap_str[] = {"", "dr_swap", "pr_swap", "vconn_swap"}; + const char *role_str[] = { "", "toggle", "toggle-off", + "sink", "source", "freeze" }; + const char *mux_str[] = { "", "none", "usb", "dp", "dock", "auto" }; + const char *swap_str[] = { "", "dr_swap", "pr_swap", "vconn_swap" }; struct ec_params_usb_pd_control p; struct ec_response_usb_pd_control_v2 *r_v2 = (struct ec_response_usb_pd_control_v2 *)ec_inbuf; @@ -6378,7 +6369,6 @@ int cmd_usb_pd(int argc, char *argv[]) } } - if (!option_ok) { fprintf(stderr, "Unknown option: %s\n", argv[i]); return -1; @@ -6392,8 +6382,8 @@ int cmd_usb_pd(int argc, char *argv[]) else cmdver = 0; - rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_CONTROL, cmdver, &p, sizeof(p), ec_inbuf, + ec_max_insize); if (rv < 0 || argc != 2) return (rv < 0) ? rv : 0; @@ -6408,9 +6398,11 @@ int cmd_usb_pd(int argc, char *argv[]) "Role:%s %s%s, Polarity:CC%d\n", p.port, (r_v1->enabled & PD_CTRL_RESP_ENABLED_COMMS) ? - "enabled" : "disabled", + "enabled" : + "disabled", (r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) ? - "connected" : "disconnected", + "connected" : + "disconnected", r_v1->state, (r_v1->role & PD_CTRL_RESP_ROLE_POWER) ? "SRC" : "SNK", @@ -6456,21 +6448,26 @@ int cmd_usb_pd(int argc, char *argv[]) } printf("Cable type:%s\n", - r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ? - "Active" : "Passive"); + r_v2->control_flags & USB_PD_CTRL_ACTIVE_CABLE ? + "Active" : + "Passive"); printf("TBT Adapter type:%s\n", - r_v2->control_flags & - USB_PD_CTRL_TBT_LEGACY_ADAPTER ? - "Legacy" : "Gen3"); + r_v2->control_flags & + USB_PD_CTRL_TBT_LEGACY_ADAPTER ? + "Legacy" : + "Gen3"); printf("Optical Cable:%s\n", - r_v2->control_flags & - USB_PD_CTRL_OPTICAL_CABLE ? "True" : "False"); + r_v2->control_flags & USB_PD_CTRL_OPTICAL_CABLE ? + "True" : + "False"); printf("Link LSRX Communication:%s-directional\n", - r_v2->control_flags & - USB_PD_CTRL_ACTIVE_LINK_UNIDIR ? "Uni" : "Bi"); + r_v2->control_flags & + USB_PD_CTRL_ACTIVE_LINK_UNIDIR ? + "Uni" : + "Bi"); printf("TBT Cable Speed:"); switch (r_v2->cable_speed) { @@ -6489,20 +6486,24 @@ int cmd_usb_pd(int argc, char *argv[]) printf("\n"); printf("Rounded support: 3rd Gen %srounded support\n", - r_v2->cable_gen ? "and 4th Gen " : ""); + r_v2->cable_gen ? "and 4th Gen " : ""); } /* If connected to a PD device, then print port partner info */ if ((r_v1->enabled & PD_CTRL_RESP_ENABLED_CONNECTED) && (r_v1->enabled & PD_CTRL_RESP_ENABLED_PD_CAPABLE)) printf("PD Partner Capabilities:\n%s%s%s%s", - (r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ? - " DR power\n" : "", - (r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ? - " DR data\n" : "", - (r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ? - " USB capable\n" : "", - (r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ? - " Unconstrained power\n" : ""); + (r_v1->role & PD_CTRL_RESP_ROLE_DR_POWER) ? + " DR power\n" : + "", + (r_v1->role & PD_CTRL_RESP_ROLE_DR_DATA) ? + " DR data\n" : + "", + (r_v1->role & PD_CTRL_RESP_ROLE_USB_COMM) ? + " USB capable\n" : + "", + (r_v1->role & PD_CTRL_RESP_ROLE_UNCONSTRAINED) ? + " Unconstrained power\n" : + ""); } return 0; } @@ -6530,8 +6531,7 @@ int cmd_usb_pd_dps(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_USB_PD_DPS_CONTROL, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_USB_PD_DPS_CONTROL, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -6557,8 +6557,7 @@ static void print_pd_power_info(struct ec_response_usb_pd_power_info *r) printf("Unknown"); } - if ((r->role == USB_PD_PORT_POWER_SOURCE) && - (r->meas.current_max)) + if ((r->role == USB_PD_PORT_POWER_SOURCE) && (r->meas.current_max)) printf(" %dmA", r->meas.current_max); if ((r->role == USB_PD_PORT_POWER_DISCONNECTED) || @@ -6597,9 +6596,8 @@ static void print_pd_power_info(struct ec_response_usb_pd_power_info *r) printf(" Unknown"); break; } - printf(" %dmV / %dmA, max %dmV / %dmA", - r->meas.voltage_now, r->meas.current_lim, r->meas.voltage_max, - r->meas.current_max); + printf(" %dmV / %dmA, max %dmV / %dmA", r->meas.voltage_now, + r->meas.current_lim, r->meas.voltage_max, r->meas.current_max); if (r->max_power) printf(" / %dmW", r->max_power / 1000); printf("\n"); @@ -6619,17 +6617,16 @@ int cmd_usb_pd_mux_info(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) return rv; num_ports = ((struct ec_response_usb_pd_ports *)ec_inbuf)->num_ports; for (i = 0; i < num_ports; i++) { p.port = i; - rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0, - &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_USB_PD_MUX_INFO, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; @@ -6643,29 +6640,27 @@ int cmd_usb_pd_mux_info(int argc, char *argv[]) printf("%d\t", i); printf("%d\t", !!(r.flags & USB_PD_MUX_USB_ENABLED)); printf("%d\t", !!(r.flags & USB_PD_MUX_DP_ENABLED)); - printf("%s\t", - r.flags & USB_PD_MUX_POLARITY_INVERTED ? - "INVERTED" : "NORMAL"); + printf("%s\t", r.flags & USB_PD_MUX_POLARITY_INVERTED ? + "INVERTED" : + "NORMAL"); printf("%d\t", !!(r.flags & USB_PD_MUX_HPD_IRQ)); printf("%d\n", !!(r.flags & USB_PD_MUX_HPD_LVL)); } else { /* Human-readable mux info. */ printf("Port %d: ", i); - printf("USB=%d ", - !!(r.flags & USB_PD_MUX_USB_ENABLED)); + printf("USB=%d ", !!(r.flags & USB_PD_MUX_USB_ENABLED)); printf("DP=%d ", !!(r.flags & USB_PD_MUX_DP_ENABLED)); printf("POLARITY=%s ", - r.flags & USB_PD_MUX_POLARITY_INVERTED ? - "INVERTED" : "NORMAL"); - printf("HPD_IRQ=%d ", - !!(r.flags & USB_PD_MUX_HPD_IRQ)); - printf("HPD_LVL=%d ", - !!(r.flags & USB_PD_MUX_HPD_LVL)); + r.flags & USB_PD_MUX_POLARITY_INVERTED ? + "INVERTED" : + "NORMAL"); + printf("HPD_IRQ=%d ", !!(r.flags & USB_PD_MUX_HPD_IRQ)); + printf("HPD_LVL=%d ", !!(r.flags & USB_PD_MUX_HPD_LVL)); printf("SAFE=%d ", !!(r.flags & USB_PD_MUX_SAFE_MODE)); printf("TBT=%d ", - !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED)); + !!(r.flags & USB_PD_MUX_TBT_COMPAT_ENABLED)); printf("USB4=%d ", - !!(r.flags & USB_PD_MUX_USB4_ENABLED)); + !!(r.flags & USB_PD_MUX_USB4_ENABLED)); printf("\n"); } } @@ -6681,8 +6676,8 @@ int cmd_usb_pd_power(int argc, char *argv[]) int num_ports, i, rv; char *e; - rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_PORTS, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) return rv; num_ports = ((struct ec_response_usb_pd_ports *)r)->num_ports; @@ -6690,9 +6685,8 @@ int cmd_usb_pd_power(int argc, char *argv[]) if (argc < 2) { for (i = 0; i < num_ports; i++) { p.port = i; - rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, - &p, sizeof(p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p, + sizeof(p), ec_inbuf, ec_max_insize); if (rv < 0) return rv; @@ -6705,8 +6699,7 @@ int cmd_usb_pd_power(int argc, char *argv[]) fprintf(stderr, "Bad port.\n"); return -1; } - rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, - &p, sizeof(p), + rv = ec_command(EC_CMD_USB_PD_POWER_INFO, 0, &p, sizeof(p), ec_inbuf, ec_max_insize); if (rv < 0) return rv; @@ -6725,8 +6718,7 @@ int cmd_kbpress(int argc, char *argv[]) int rv; if (argc != 4) { - fprintf(stderr, - "Usage: %s <0|1>\n", argv[0]); + fprintf(stderr, "Usage: %s <0|1>\n", argv[0]); return -1; } p.row = strtol(argv[1], &e, 0); @@ -6746,11 +6738,9 @@ int cmd_kbpress(int argc, char *argv[]) } printf("%s row %d col %d.\n", p.pressed ? "Pressing" : "Releasing", - p.row, - p.col); + p.row, p.col); - rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_MKBP_SIMULATE_KEY, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; printf("Done.\n"); @@ -6762,14 +6752,14 @@ int cmd_keyboard_factory_test(int argc, char *argv[]) struct ec_response_keyboard_factory_test r; int rv; - rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_KEYBOARD_FACTORY_TEST, 0, NULL, 0, &r, + sizeof(r)); if (rv < 0) return rv; if (r.shorted != 0) printf("Keyboard %d and %d pin are shorted.\n", - r.shorted & 0x00ff, r.shorted >> 8); + r.shorted & 0x00ff, r.shorted >> 8); else printf("Keyboard factory test passed.\n"); @@ -6780,8 +6770,8 @@ int cmd_panic_info(int argc, char *argv[]) { int rv; - rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0, - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_GET_PANIC_INFO, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) return rv; @@ -6793,7 +6783,6 @@ int cmd_panic_info(int argc, char *argv[]) return parse_panic_info((char *)(ec_inbuf), rv); } - int cmd_power_info(int argc, char *argv[]) { struct ec_response_power_info_v1 r; @@ -6833,7 +6822,6 @@ int cmd_power_info(int argc, char *argv[]) return 0; } - int cmd_pse(int argc, char *argv[]) { struct ec_params_pse p; @@ -6896,7 +6884,6 @@ int cmd_pse(int argc, char *argv[]) return 0; } - int cmd_pstore_info(int argc, char *argv[]) { struct ec_response_pstore_info r; @@ -6910,7 +6897,6 @@ int cmd_pstore_info(int argc, char *argv[]) return 0; } - int cmd_pstore_read(int argc, char *argv[]) { struct ec_params_pstore_read p; @@ -6922,8 +6908,8 @@ int cmd_pstore_read(int argc, char *argv[]) char *buf; if (argc < 4) { - fprintf(stderr, - "Usage: %s \n", argv[0]); + fprintf(stderr, "Usage: %s \n", + argv[0]); return -1; } offset = strtol(argv[1], &e, 0); @@ -6948,8 +6934,8 @@ int cmd_pstore_read(int argc, char *argv[]) for (i = 0; i < size; i += EC_PSTORE_SIZE_MAX) { p.offset = offset + i; p.size = MIN(size - i, EC_PSTORE_SIZE_MAX); - rv = ec_command(EC_CMD_PSTORE_READ, 0, - &p, sizeof(p), rdata, sizeof(rdata)); + rv = ec_command(EC_CMD_PSTORE_READ, 0, &p, sizeof(p), rdata, + sizeof(rdata)); if (rv < 0) { fprintf(stderr, "Read error at offset %d\n", i); free(buf); @@ -6967,7 +6953,6 @@ int cmd_pstore_read(int argc, char *argv[]) return 0; } - int cmd_pstore_write(int argc, char *argv[]) { struct ec_params_pstore_write p; @@ -6999,8 +6984,7 @@ int cmd_pstore_write(int argc, char *argv[]) p.offset = offset + i; p.size = MIN(size - i, EC_PSTORE_SIZE_MAX); memcpy(p.data, buf + i, p.size); - rv = ec_command(EC_CMD_PSTORE_WRITE, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_PSTORE_WRITE, 0, &p, sizeof(p), NULL, 0); if (rv < 0) { fprintf(stderr, "Write error at offset %d\n", i); free(buf); @@ -7013,7 +6997,6 @@ int cmd_pstore_write(int argc, char *argv[]) return 0; } - int cmd_host_event_get_raw(int argc, char *argv[]) { uint32_t events = read_mapped_mem32(EC_MEMMAP_HOST_EVENTS); @@ -7027,14 +7010,12 @@ int cmd_host_event_get_raw(int argc, char *argv[]) return 0; } - int cmd_host_event_get_b(int argc, char *argv[]) { struct ec_response_host_event_mask r; int rv; - rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_HOST_EVENT_GET_B, 0, NULL, 0, &r, sizeof(r)); if (rv < 0) return rv; if (rv < sizeof(r)) { @@ -7051,14 +7032,13 @@ int cmd_host_event_get_b(int argc, char *argv[]) return 0; } - int cmd_host_event_get_smi_mask(int argc, char *argv[]) { struct ec_response_host_event_mask r; int rv; - rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_HOST_EVENT_GET_SMI_MASK, 0, NULL, 0, &r, + sizeof(r)); if (rv < 0) return rv; @@ -7066,14 +7046,13 @@ int cmd_host_event_get_smi_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_get_sci_mask(int argc, char *argv[]) { struct ec_response_host_event_mask r; int rv; - rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_HOST_EVENT_GET_SCI_MASK, 0, NULL, 0, &r, + sizeof(r)); if (rv < 0) return rv; @@ -7081,14 +7060,13 @@ int cmd_host_event_get_sci_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_get_wake_mask(int argc, char *argv[]) { struct ec_response_host_event_mask r; int rv; - rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_HOST_EVENT_GET_WAKE_MASK, 0, NULL, 0, &r, + sizeof(r)); if (rv < 0) return rv; @@ -7096,7 +7074,6 @@ int cmd_host_event_get_wake_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_set_smi_mask(int argc, char *argv[]) { struct ec_params_host_event_mask p; @@ -7113,8 +7090,8 @@ int cmd_host_event_set_smi_mask(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_HOST_EVENT_SET_SMI_MASK, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; @@ -7122,7 +7099,6 @@ int cmd_host_event_set_smi_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_set_sci_mask(int argc, char *argv[]) { struct ec_params_host_event_mask p; @@ -7139,8 +7115,8 @@ int cmd_host_event_set_sci_mask(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_HOST_EVENT_SET_SCI_MASK, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; @@ -7148,7 +7124,6 @@ int cmd_host_event_set_sci_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_set_wake_mask(int argc, char *argv[]) { struct ec_params_host_event_mask p; @@ -7165,8 +7140,8 @@ int cmd_host_event_set_wake_mask(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_HOST_EVENT_SET_WAKE_MASK, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; @@ -7174,7 +7149,6 @@ int cmd_host_event_set_wake_mask(int argc, char *argv[]) return 0; } - int cmd_host_event_clear(int argc, char *argv[]) { struct ec_params_host_event_mask p; @@ -7191,8 +7165,7 @@ int cmd_host_event_clear(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_HOST_EVENT_CLEAR, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -7200,7 +7173,6 @@ int cmd_host_event_clear(int argc, char *argv[]) return 0; } - int cmd_host_event_clear_b(int argc, char *argv[]) { struct ec_params_host_event_mask p; @@ -7217,8 +7189,7 @@ int cmd_host_event_clear_b(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_HOST_EVENT_CLEAR_B, 0, &p, sizeof(p), NULL, 0); if (rv < 0) return rv; @@ -7226,7 +7197,6 @@ int cmd_host_event_clear_b(int argc, char *argv[]) return 0; } - int cmd_switches(int argc, char *argv[]) { uint8_t s = read_mapped_mem8(EC_MEMMAP_SWITCHES); @@ -7243,7 +7213,6 @@ int cmd_switches(int argc, char *argv[]) return 0; } - int cmd_wireless(int argc, char *argv[]) { char *e; @@ -7272,8 +7241,8 @@ int cmd_wireless(int argc, char *argv[]) struct ec_params_switch_enable_wireless_v0 p; p.enabled = now_flags; - rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, 0, &p, sizeof(p), + NULL, 0); if (rv < 0) return rv; @@ -7308,19 +7277,18 @@ int cmd_wireless(int argc, char *argv[]) } rv = ec_command(EC_CMD_SWITCH_ENABLE_WIRELESS, - EC_VER_SWITCH_ENABLE_WIRELESS, - &p, sizeof(p), &r, sizeof(r)); + EC_VER_SWITCH_ENABLE_WIRELESS, &p, sizeof(p), + &r, sizeof(r)); if (rv < 0) return rv; - printf("Now=0x%x, suspend=0x%x\n", - r.now_flags, r.suspend_flags); + printf("Now=0x%x, suspend=0x%x\n", r.now_flags, + r.suspend_flags); } return 0; } - static void cmd_locate_chip_help(const char *const cmd) { fprintf(stderr, @@ -7332,15 +7300,12 @@ static void cmd_locate_chip_help(const char *const cmd) cmd); } -static const char *bus_type[] = { - "I2C", - "EMBEDDED" -}; +static const char *bus_type[] = { "I2C", "EMBEDDED" }; int cmd_locate_chip(int argc, char *argv[]) { struct ec_params_locate_chip p; - struct ec_response_locate_chip r = {0}; + struct ec_response_locate_chip r = { 0 }; char *e; int rv; @@ -7383,8 +7348,8 @@ int cmd_locate_chip(int argc, char *argv[]) if (rv < 0) return rv; - if (r.bus_type >= EC_BUS_TYPE_COUNT - || r.bus_type >= ARRAY_SIZE(bus_type)) { + if (r.bus_type >= EC_BUS_TYPE_COUNT || + r.bus_type >= ARRAY_SIZE(bus_type)) { fprintf(stderr, "Unknown bus type (%d)\n", r.bus_type); return -1; } @@ -7416,8 +7381,8 @@ int cmd_lcd_backlight(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_SWITCH_ENABLE_BKLIGHT, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; @@ -7427,8 +7392,7 @@ int cmd_lcd_backlight(int argc, char *argv[]) static void cmd_basestate_help(void) { - fprintf(stderr, - "Usage: ectool basestate [attach | detach | reset]\n"); + fprintf(stderr, "Usage: ectool basestate [attach | detach | reset]\n"); } int cmd_basestate(int argc, char *argv[]) @@ -7451,8 +7415,7 @@ int cmd_basestate(int argc, char *argv[]) return -1; } - return ec_command(EC_CMD_SET_BASE_STATE, 0, - &p, sizeof(p), NULL, 0); + return ec_command(EC_CMD_SET_BASE_STATE, 0, &p, sizeof(p), NULL, 0); } int cmd_ext_power_limit(int argc, char *argv[]) @@ -7462,8 +7425,7 @@ int cmd_ext_power_limit(int argc, char *argv[]) char *e; if (argc != 3) { - fprintf(stderr, - "Usage: %s \n", + fprintf(stderr, "Usage: %s \n", argv[0]); return -1; } @@ -7481,11 +7443,10 @@ int cmd_ext_power_limit(int argc, char *argv[]) } /* Send version 1 of command */ - return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p), - NULL, 0); + return ec_command(EC_CMD_EXTERNAL_POWER_LIMIT, 1, &p, sizeof(p), NULL, + 0); } - int cmd_charge_current_limit(int argc, char *argv[]) { struct ec_params_current_limit p; @@ -7503,8 +7464,7 @@ int cmd_charge_current_limit(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p), - NULL, 0); + rv = ec_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &p, sizeof(p), NULL, 0); return rv; } @@ -7514,16 +7474,16 @@ static void cmd_charge_control_help(const char *cmd, const char *msg) fprintf(stderr, "ERROR: %s\n", msg); fprintf(stderr, - "\n" - " Usage: %s\n" - " Get current settings.\n" - " Usage: %s normal|idle|discharge\n" - " Set charge mode (and disable battery sustainer).\n" - " Usage: %s normal \n" - " Enable battery sustainer. and are battery SoC\n" - " between which EC tries to keep the battery level.\n" - "\n", - cmd, cmd, cmd); + "\n" + " Usage: %s\n" + " Get current settings.\n" + " Usage: %s normal|idle|discharge\n" + " Set charge mode (and disable battery sustainer).\n" + " Usage: %s normal \n" + " Enable battery sustainer. and are battery SoC\n" + " between which EC tries to keep the battery level.\n" + "\n", + cmd, cmd, cmd); } int cmd_charge_control(int argc, char *argv[]) @@ -7531,7 +7491,7 @@ int cmd_charge_control(int argc, char *argv[]) struct ec_params_charge_control p; struct ec_response_charge_control r; int version = 2; - const char * const charge_mode_text[] = EC_CHARGE_MODE_TEXT; + const char *const charge_mode_text[] = EC_CHARGE_MODE_TEXT; char *e; int rv; @@ -7545,19 +7505,22 @@ int cmd_charge_control(int argc, char *argv[]) return -1; } p.cmd = EC_CHARGE_CONTROL_CMD_GET; - rv = ec_command(EC_CMD_CHARGE_CONTROL, version, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_CHARGE_CONTROL, version, &p, sizeof(p), + &r, sizeof(r)); if (rv < 0) { fprintf(stderr, "Command failed.\n"); return rv; } printf("Charge mode = %s (%d)\n", - r.mode < ARRAY_SIZE(charge_mode_text) - ? charge_mode_text[r.mode] : "UNDEFINED", + r.mode < ARRAY_SIZE(charge_mode_text) ? + charge_mode_text[r.mode] : + "UNDEFINED", r.mode); printf("Battery sustainer = %s (%d%% ~ %d%%)\n", - (r.sustain_soc.lower != -1 && r.sustain_soc.upper != -1) - ? "on" : "off", + (r.sustain_soc.lower != -1 && + r.sustain_soc.upper != -1) ? + "on" : + "off", r.sustain_soc.lower, r.sustain_soc.upper); return 0; } @@ -7570,20 +7533,21 @@ int cmd_charge_control(int argc, char *argv[]) p.sustain_soc.upper = -1; } else if (argc == 4) { if (version < 2) { - cmd_charge_control_help(argv[0], + cmd_charge_control_help( + argv[0], "Old EC doesn't support sustainer."); return -1; } p.sustain_soc.lower = strtol(argv[2], &e, 0); if (e && *e) { - cmd_charge_control_help(argv[0], - "Bad character in "); + cmd_charge_control_help( + argv[0], "Bad character in "); return -1; } p.sustain_soc.upper = strtol(argv[3], &e, 0); if (e && *e) { - cmd_charge_control_help(argv[0], - "Bad character in "); + cmd_charge_control_help( + argv[0], "Bad character in "); return -1; } } else { @@ -7616,8 +7580,10 @@ int cmd_charge_control(int argc, char *argv[]) switch (p.mode) { case CHARGE_CONTROL_NORMAL: printf("Charge state machine is in normal mode%s.\n", - (p.sustain_soc.lower == -1 || p.sustain_soc.upper == -1) - ? "" : " with sustainer enabled"); + (p.sustain_soc.lower == -1 || + p.sustain_soc.upper == -1) ? + "" : + " with sustainer enabled"); break; case CHARGE_CONTROL_IDLE: printf("Charge state machine force idle.\n"); @@ -7631,7 +7597,6 @@ int cmd_charge_control(int argc, char *argv[]) return 0; } - static void print_bool(const char *name, bool value) { printf("%s = %s\n", name, value ? "true" : "false"); @@ -7678,7 +7643,6 @@ usage: return -1; } - #define ST_CMD_SIZE ST_FLD_SIZE(ec_params_charge_state, cmd) #define ST_PRM_SIZE(SUBCMD) \ (ST_CMD_SIZE + ST_FLD_SIZE(ec_params_charge_state, SUBCMD)) @@ -7692,7 +7656,7 @@ static const struct { /* Order must match enum charge_state_command */ { ST_CMD_SIZE, ST_RSP_SIZE(get_state) }, { ST_PRM_SIZE(get_param), ST_RSP_SIZE(get_param) }, - { ST_PRM_SIZE(set_param), 0}, + { ST_PRM_SIZE(set_param), 0 }, }; BUILD_ASSERT(ARRAY_SIZE(cs_paramcount) == CHARGE_STATE_NUM_CMDS); @@ -7706,20 +7670,16 @@ static int cs_do_cmd(struct ec_params_charge_state *to_ec, int rv; int cmd = to_ec->cmd; - rv = ec_command(EC_CMD_CHARGE_STATE, 0, - to_ec, cs_paramcount[cmd].to_ec_size, - from_ec, cs_paramcount[cmd].from_ec_size); + rv = ec_command(EC_CMD_CHARGE_STATE, 0, to_ec, + cs_paramcount[cmd].to_ec_size, from_ec, + cs_paramcount[cmd].from_ec_size); return (rv < 0 ? 1 : 0); } -static const char * const base_params[] = { - "chg_voltage", - "chg_current", - "chg_input_current", - "chg_status", - "chg_option", - "limit_power", +static const char *const base_params[] = { + "chg_voltage", "chg_current", "chg_input_current", + "chg_status", "chg_option", "limit_power", }; BUILD_ASSERT(ARRAY_SIZE(base_params) == CS_NUM_BASE_PARAMS); @@ -7826,8 +7786,8 @@ int cmd_gpio_get(int argc, char *argv[]) } strcpy(p.name, argv[1]); - rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p, - sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; @@ -7861,21 +7821,21 @@ int cmd_gpio_get(int argc, char *argv[]) } strcpy(p_v1.get_value_by_name.name, argv[1]); - rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, - sizeof(p_v1), &r_v1, sizeof(r_v1)); + rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1), + &r_v1, sizeof(r_v1)); if (rv < 0) return rv; printf("GPIO %s = %d\n", p_v1.get_value_by_name.name, - r_v1.get_value_by_name.val); + r_v1.get_value_by_name.val); return 0; } /* Need GPIO count for EC_GPIO_GET_COUNT or EC_GPIO_GET_INFO */ p_v1.subcmd = EC_GPIO_GET_COUNT; - rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, - sizeof(p_v1), &r_v1, sizeof(r_v1)); + rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1), &r_v1, + sizeof(r_v1)); if (rv < 0) return rv; @@ -7891,19 +7851,18 @@ int cmd_gpio_get(int argc, char *argv[]) for (i = 0; i < num_gpios; i++) { p_v1.get_info.index = i; - rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, - sizeof(p_v1), &r_v1, sizeof(r_v1)); + rv = ec_command(EC_CMD_GPIO_GET, cmdver, &p_v1, sizeof(p_v1), + &r_v1, sizeof(r_v1)); if (rv < 0) return rv; printf("%2d %-32s 0x%04X\n", r_v1.get_info.val, - r_v1.get_info.name, r_v1.get_info.flags); + r_v1.get_info.name, r_v1.get_info.flags); } return 0; } - int cmd_gpio_set(int argc, char *argv[]) { struct ec_params_gpio_set p; @@ -7962,16 +7921,14 @@ int get_battery_command(int index) printf("Battery %d info:\n", index); static_p.index = index; - rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1, - &static_p, sizeof(static_p), - &static_r, sizeof(static_r)); + rv = ec_command(EC_CMD_BATTERY_GET_STATIC, 1, &static_p, + sizeof(static_p), &static_r, sizeof(static_r)); if (rv < 0) return -1; dynamic_p.index = index; - rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0, - &dynamic_p, sizeof(dynamic_p), - &dynamic_r, sizeof(dynamic_r)); + rv = ec_command(EC_CMD_BATTERY_GET_DYNAMIC, 0, &dynamic_p, + sizeof(dynamic_p), &dynamic_r, sizeof(dynamic_r)); if (rv < 0) return -1; @@ -8022,7 +7979,7 @@ int get_battery_command(int index) if (!is_battery_range(dynamic_r.remaining_capacity)) goto cmd_error; printf(" Remaining capacity %u mAh\n", - dynamic_r.remaining_capacity); + dynamic_r.remaining_capacity); if (!is_battery_range(dynamic_r.desired_voltage)) goto cmd_error; @@ -8063,8 +8020,7 @@ int cmd_battery(int argc, char *argv[]) * Read non-primary batteries through hostcmd, and all batteries * if longer strings are supported for static info. */ - if (index > 0 || - ec_cmd_version_supported(EC_CMD_BATTERY_GET_STATIC, 1)) + if (index > 0 || ec_cmd_version_supported(EC_CMD_BATTERY_GET_STATIC, 1)) return get_battery_command(index); val = read_mapped_mem8(EC_MEMMAP_BATTERY_VERSION); @@ -8078,25 +8034,25 @@ int cmd_battery(int argc, char *argv[]) printf("Battery info:\n"); rv = read_mapped_string(EC_MEMMAP_BATT_MFGR, batt_text, - sizeof(batt_text)); + sizeof(batt_text)); if (rv < 0 || !is_string_printable(batt_text)) goto cmd_error; printf(" OEM name: %s\n", batt_text); rv = read_mapped_string(EC_MEMMAP_BATT_MODEL, batt_text, - sizeof(batt_text)); + sizeof(batt_text)); if (rv < 0 || !is_string_printable(batt_text)) goto cmd_error; printf(" Model number: %s\n", batt_text); rv = read_mapped_string(EC_MEMMAP_BATT_TYPE, batt_text, - sizeof(batt_text)); + sizeof(batt_text)); if (rv < 0 || !is_string_printable(batt_text)) goto cmd_error; printf(" Chemistry : %s\n", batt_text); rv = read_mapped_string(EC_MEMMAP_BATT_SERIAL, batt_text, - sizeof(batt_text)); + sizeof(batt_text)); printf(" Serial number: %s\n", batt_text); val = read_mapped_mem32(EC_MEMMAP_BATT_DCAP); @@ -8180,10 +8136,11 @@ int cmd_battery_cut_off(int argc, char *argv[]) if (rv < 0) { fprintf(stderr, "Failed to cut off battery, rv=%d\n", rv); - fprintf(stderr, "It is expected if the rv is -%d " - "(EC_RES_INVALID_COMMAND) if the battery " - "doesn't support cut-off function.\n", - EC_RES_INVALID_COMMAND); + fprintf(stderr, + "It is expected if the rv is -%d " + "(EC_RES_INVALID_COMMAND) if the battery " + "doesn't support cut-off function.\n", + EC_RES_INVALID_COMMAND); } else { printf("\n"); printf("SUCCESS. The battery has arranged a cut-off.\n"); @@ -8235,8 +8192,8 @@ int cmd_battery_vendor_param(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p), - &r, sizeof(r)); + rv = ec_command(EC_CMD_BATTERY_VENDOR_PARAM, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; @@ -8270,28 +8227,29 @@ int cmd_board_version(int argc, char *argv[]) static void cmd_cbi_help(char *cmd) { fprintf(stderr, - " Usage: %s get [get_flag]\n" - " Usage: %s set [set_flag]\n" - " Usage: %s remove [set_flag]\n" - " is one of:\n" - " 0: BOARD_VERSION\n" - " 1: OEM_ID\n" - " 2: SKU_ID\n" - " 3: DRAM_PART_NUM (string)\n" - " 4: OEM_NAME (string)\n" - " 5: MODEL_ID\n" - " 6: FW_CONFIG\n" - " 7: PCB_VENDOR\n" - " 8: SSFC\n" - " 9: REWORK_ID\n" - " is the size of the data in byte. It should be zero for\n" - " string types.\n" - " is an integer or a string to be set\n" - " [get_flag] is combination of:\n" - " 01b: Invalidate cache and reload data from EEPROM\n" - " [set_flag] is combination of:\n" - " 01b: Skip write to EEPROM. Use for back-to-back writes\n" - " 10b: Set all fields to defaults first\n", cmd, cmd, cmd); + " Usage: %s get [get_flag]\n" + " Usage: %s set [set_flag]\n" + " Usage: %s remove [set_flag]\n" + " is one of:\n" + " 0: BOARD_VERSION\n" + " 1: OEM_ID\n" + " 2: SKU_ID\n" + " 3: DRAM_PART_NUM (string)\n" + " 4: OEM_NAME (string)\n" + " 5: MODEL_ID\n" + " 6: FW_CONFIG\n" + " 7: PCB_VENDOR\n" + " 8: SSFC\n" + " 9: REWORK_ID\n" + " is the size of the data in byte. It should be zero for\n" + " string types.\n" + " is an integer or a string to be set\n" + " [get_flag] is combination of:\n" + " 01b: Invalidate cache and reload data from EEPROM\n" + " [set_flag] is combination of:\n" + " 01b: Skip write to EEPROM. Use for back-to-back writes\n" + " 10b: Set all fields to defaults first\n", + cmd, cmd, cmd); } static int cmd_cbi_is_string_field(enum cbi_data_tag tag) @@ -8348,15 +8306,15 @@ static int cmd_cbi(int argc, char *argv[]) if (cmd_cbi_is_string_field(tag)) { printf("%.*s", rv, (const char *)ec_inbuf); } else { - const uint8_t * const buffer = + const uint8_t *const buffer = (const uint8_t *const)(ec_inbuf); uint64_t int_value = 0; - for(i = 0; i < rv; i++) + for (i = 0; i < rv; i++) int_value |= (uint64_t)buffer[i] << (i * 8); - printf("As uint: %llu (0x%llx)\n", - (unsigned long long)int_value, - (unsigned long long)int_value); + printf("As uint: %llu (0x%llx)\n", + (unsigned long long)int_value, + (unsigned long long)int_value); printf("As binary:"); for (i = 0; i < rv; i++) { if (i % 32 == 31) @@ -8368,7 +8326,7 @@ static int cmd_cbi(int argc, char *argv[]) return 0; } else if (!strcasecmp(argv[1], "set")) { struct ec_params_set_cbi *p = - (struct ec_params_set_cbi *)ec_outbuf; + (struct ec_params_set_cbi *)ec_outbuf; void *val_ptr; uint64_t val = 0; uint8_t size; @@ -8398,11 +8356,11 @@ static int cmd_cbi(int argc, char *argv[]) size = strtol(argv[4], &e, 0); if (tag == CBI_TAG_REWORK_ID) { if ((e && *e) || size < 1 || size > 8 || - (size < 8 && val >= (1ull << size*8))) + (size < 8 && val >= (1ull << size * 8))) bad_size = 1; } else { if ((e && *e) || size < 1 || 4 < size || - val >= (1ull << size*8)) + val >= (1ull << size * 8)) bad_size = 1; } if (bad_size == 1) { @@ -8428,11 +8386,12 @@ static int cmd_cbi(int argc, char *argv[]) return -1; } } - rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, - p, sizeof(*p) + size, NULL, 0); + rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, p, + sizeof(*p) + size, NULL, 0); if (rv < 0) { if (rv == -EC_RES_ACCESS_DENIED - EECRESULT) - fprintf(stderr, "Write-protect is enabled or " + fprintf(stderr, + "Write-protect is enabled or " "EC explicitly refused to change the " "requested field.\n"); else @@ -8452,11 +8411,12 @@ static int cmd_cbi(int argc, char *argv[]) return -1; } } - rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, - &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_SET_CROS_BOARD_INFO, 0, &p, sizeof(p), + NULL, 0); if (rv < 0) { if (rv == -EC_RES_ACCESS_DENIED - EECRESULT) - fprintf(stderr, "Write-protect is enabled or " + fprintf(stderr, + "Write-protect is enabled or " "EC explicitly refused to change the " "requested field.\n"); else @@ -8497,8 +8457,8 @@ int cmd_proto_info(int argc, char *argv[]) printf("Protocol info:\n"); - rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, - &info, sizeof(info)); + rv = ec_command(EC_CMD_GET_PROTOCOL_INFO, 0, NULL, 0, &info, + sizeof(info)); if (rv < 0) { fprintf(stderr, "Protocol info unavailable. EC probably only " "supports protocol version 2.\n"); @@ -8534,7 +8494,6 @@ static int ec_hash_help(const char *cmd) return 0; } - static int ec_hash_print(const struct ec_response_vboot_hash *r) { int i; @@ -8566,7 +8525,6 @@ static int ec_hash_print(const struct ec_response_vboot_hash *r) return 0; } - int cmd_ec_hash(int argc, char *argv[]) { struct ec_params_vboot_hash p; @@ -8578,8 +8536,8 @@ int cmd_ec_hash(int argc, char *argv[]) if (argc < 2) { /* Get hash status */ p.cmd = EC_VBOOT_HASH_GET; - rv = ec_command(EC_CMD_VBOOT_HASH, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r, + sizeof(r)); if (rv < 0) return rv; @@ -8589,8 +8547,8 @@ int cmd_ec_hash(int argc, char *argv[]) if (argc == 2 && !strcasecmp(argv[1], "abort")) { /* Abort hash calculation */ p.cmd = EC_VBOOT_HASH_ABORT; - rv = ec_command(EC_CMD_VBOOT_HASH, 0, - &p, sizeof(p), &r, sizeof(r)); + rv = ec_command(EC_CMD_VBOOT_HASH, 0, &p, sizeof(p), &r, + sizeof(r)); return (rv < 0 ? rv : 0); } @@ -8661,7 +8619,6 @@ int cmd_ec_hash(int argc, char *argv[]) return ec_hash_print(&r); } - int cmd_rtc_get(int argc, char *argv[]) { struct ec_response_rtc r; @@ -8675,7 +8632,6 @@ int cmd_rtc_get(int argc, char *argv[]) return 0; } - int cmd_rtc_set(int argc, char *argv[]) { struct ec_params_rtc p; @@ -8755,8 +8711,8 @@ int cmd_console(int argc, char *argv[]) /* Loop and read from the snapshot until it's done */ while (1) { - rv = ec_command(EC_CMD_CONSOLE_READ, 0, - NULL, 0, ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_CONSOLE_READ, 0, NULL, 0, ec_inbuf, + ec_max_insize); if (rv < 0) return rv; @@ -8772,17 +8728,16 @@ int cmd_console(int argc, char *argv[]) return 0; } struct param_info { - const char *name; /* name of this parameter */ - const char *help; /* help message */ - int size; /* size in bytes */ - int offset; /* offset within structure */ + const char *name; /* name of this parameter */ + const char *help; /* help message */ + int size; /* size in bytes */ + int offset; /* offset within structure */ }; -#define FIELD(fname, field, help_str) \ - { \ - .name = fname, \ - .help = help_str, \ - .size = sizeof(((struct ec_mkbp_config *)NULL)->field), \ +#define FIELD(fname, field, help_str) \ + { \ + .name = fname, .help = help_str, \ + .size = sizeof(((struct ec_mkbp_config *)NULL)->field), \ .offset = __builtin_offsetof(struct ec_mkbp_config, field), \ } @@ -8803,7 +8758,8 @@ static const struct param_info keyconfig_params[] = { }; static const struct param_info *find_field(const struct param_info *params, - int count, const char *name, unsigned int *nump) + int count, const char *name, + unsigned int *nump) { const struct param_info *param; int i; @@ -8847,7 +8803,7 @@ static int show_fields(struct ec_mkbp_config *config, int argc, char *argv[]) int i; if (!argc) { - mask = -1U; /* show all fields */ + mask = -1U; /* show all fields */ } else { mask = 0; while (argc > 0) { @@ -8939,7 +8895,8 @@ static int cmd_keyconfig(int argc, char *argv[]) const struct param_info *param; int i; - fprintf(stderr, "Usage: %s get [] - print params\n" + fprintf(stderr, + "Usage: %s get [] - print params\n" "\t%s set [> ]\n" " Available params are: (all time values are in us)", argv[0], argv[0]); @@ -8975,14 +8932,14 @@ static int cmd_keyconfig(int argc, char *argv[]) return 0; } -static const char * const mkbp_button_strings[] = { +static const char *const mkbp_button_strings[] = { [EC_MKBP_POWER_BUTTON] = "Power", [EC_MKBP_VOL_UP] = "Volume up", [EC_MKBP_VOL_DOWN] = "Volume down", [EC_MKBP_RECOVERY] = "Recovery", }; -static const char * const mkbp_switch_strings[] = { +static const char *const mkbp_switch_strings[] = { [EC_MKBP_LID_OPEN] = "Lid open", [EC_MKBP_TABLET_MODE] = "Tablet mode", [EC_MKBP_BASE_ATTACHED] = "Base attached", @@ -9011,8 +8968,7 @@ static int cmd_mkbp_get(int argc, char *argv[]) } p.info_type = EC_MKBP_INFO_SUPPORTED; - rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, - sizeof(r)); + rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r)); if (rv < 0) return rv; if (p.event_type == EC_MKBP_EVENT_BUTTON) @@ -9023,8 +8979,7 @@ static int cmd_mkbp_get(int argc, char *argv[]) return -1; p.info_type = EC_MKBP_INFO_CURRENT; - rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, - sizeof(r)); + rv = ec_command(EC_CMD_MKBP_INFO, 0, &p, sizeof(p), &r, sizeof(r)); if (rv < 0) return rv; @@ -9064,9 +9019,10 @@ static int cmd_mkbp_wake_mask(int argc, char *argv[]) int rv; if (argc < 3) { - fprintf(stderr, "Usage: %s get \n" - "\t%s set \n", argv[0], - argv[0]); + fprintf(stderr, + "Usage: %s get \n" + "\t%s set \n", + argv[0], argv[0]); return -1; } @@ -9105,15 +9061,16 @@ static int cmd_mkbp_wake_mask(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r, - sizeof(r)); + rv = ec_command(EC_CMD_MKBP_WAKE_MASK, 0, &p, sizeof(p), &r, sizeof(r)); if (rv < 0) { - if (rv == -EECRESULT-EC_RES_INVALID_PARAM) { - fprintf(stderr, "Unknown mask, or mask is not in use. " + if (rv == -EECRESULT - EC_RES_INVALID_PARAM) { + fprintf(stderr, + "Unknown mask, or mask is not in use. " "You may need to enable the " - "CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n" - , p.mask_type == EC_MKBP_EVENT_WAKE_MASK ? - "EVENT" : "HOSTEVENT"); + "CONFIG_MKBP_%s_WAKEUP_MASK option in the EC.\n", + p.mask_type == EC_MKBP_EVENT_WAKE_MASK ? + "EVENT" : + "HOSTEVENT"); } return rv; } @@ -9138,8 +9095,8 @@ static int cmd_tmp006cal_v0(int idx, int argc, char *argv[]) /* Get current values */ pg.index = idx; - rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0, - &pg, sizeof(pg), &rg, sizeof(rg)); + rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 0, &pg, sizeof(pg), &rg, + sizeof(rg)); if (rv < 0) return rv; @@ -9188,8 +9145,8 @@ static int cmd_tmp006cal_v0(int idx, int argc, char *argv[]) } /* Set 'em */ - return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0, - &ps, sizeof(ps), NULL, 0); + return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 0, &ps, sizeof(ps), + NULL, 0); } /* Index is already checked. argv[0] is first param value */ @@ -9205,15 +9162,15 @@ static int cmd_tmp006cal_v1(int idx, int argc, char *argv[]) int i, rv, cmdsize; /* Algorithm 1 parameter names */ - static const char * const alg1_pname[] = { - "s0", "a1", "a2", "b0", "b1", "b2", "c2", - "d0", "d1", "ds", "e0", "e1", + static const char *const alg1_pname[] = { + "s0", "a1", "a2", "b0", "b1", "b2", + "c2", "d0", "d1", "ds", "e0", "e1", }; /* Get current values */ pg.index = idx; - rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1, - &pg, sizeof(pg), rg, ec_max_insize); + rv = ec_command(EC_CMD_TMP006_GET_CALIBRATION, 1, &pg, sizeof(pg), rg, + ec_max_insize); if (rv < 0) return rv; @@ -9255,8 +9212,8 @@ static int cmd_tmp006cal_v1(int idx, int argc, char *argv[]) /* Set 'em */ cmdsize = sizeof(*ps) + ps->num_params * sizeof(ps->val[0]); - return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1, - ps, cmdsize, NULL, 0); + return ec_command(EC_CMD_TMP006_SET_CALIBRATION, 1, ps, cmdsize, NULL, + 0); } int cmd_tmp006cal(int argc, char *argv[]) @@ -9373,8 +9330,8 @@ static int cmd_hang_detect(int argc, char *argv[]) } enum port_80_event { - PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ - PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ + PORT_80_EVENT_RESUME = 0x1001, /* S3->S0 transition */ + PORT_80_EVENT_RESET = 0x1002, /* RESET transition */ }; int cmd_port80_read(int argc, char *argv[]) @@ -9390,18 +9347,17 @@ int cmd_port80_read(int argc, char *argv[]) if (!ec_cmd_version_supported(EC_CMD_PORT80_READ, cmdver)) { /* fall back to last boot */ struct ec_response_port80_last_boot r; - rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0, - NULL, 0, &r, sizeof(r)); + rv = ec_command(EC_CMD_PORT80_LAST_BOOT, 0, NULL, 0, &r, + sizeof(r)); fprintf(stderr, "Last boot %2x\n", r.code); printf("done.\n"); return 0; } - /* read writes and history_size */ p.subcmd = EC_PORT80_GET_INFO; - rv = ec_command(EC_CMD_PORT80_READ, cmdver, - &p, sizeof(p), &rsp, sizeof(rsp)); + rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp, + sizeof(rsp)); if (rv < 0) { fprintf(stderr, "Read error at writes\n"); return rv; @@ -9409,8 +9365,7 @@ int cmd_port80_read(int argc, char *argv[]) writes = rsp.get_info.writes; history_size = rsp.get_info.history_size; - history = (uint16_t *)( - malloc(history_size * sizeof(uint16_t))); + history = (uint16_t *)(malloc(history_size * sizeof(uint16_t))); if (!history) { fprintf(stderr, "Unable to allocate buffer.\n"); return -1; @@ -9428,15 +9383,15 @@ int cmd_port80_read(int argc, char *argv[]) for (i = 0; i < history_size; i += EC_PORT80_SIZE_MAX) { p.read_buffer.offset = i; p.read_buffer.num_entries = EC_PORT80_SIZE_MAX; - rv = ec_command(EC_CMD_PORT80_READ, cmdver, - &p, sizeof(p), &rsp, sizeof(rsp)); + rv = ec_command(EC_CMD_PORT80_READ, cmdver, &p, sizeof(p), &rsp, + sizeof(rsp)); if (rv < 0) { fprintf(stderr, "Read error at offset %d\n", i); free(history); return rv; } memcpy((void *)(history + i), rsp.data.codes, - EC_PORT80_SIZE_MAX*sizeof(uint16_t)); + EC_PORT80_SIZE_MAX * sizeof(uint16_t)); } head = writes; @@ -9517,8 +9472,8 @@ int cmd_charge_port_override(int argc, char *argv[]) } } - rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p), - NULL, 0); + rv = ec_command(EC_CMD_PD_CHARGE_PORT_OVERRIDE, 0, &p, sizeof(p), NULL, + 0); if (rv < 0) return rv; @@ -9529,28 +9484,30 @@ int cmd_charge_port_override(int argc, char *argv[]) static void cmd_pchg_help(char *cmd) { fprintf(stderr, - " Usage1: %s\n" - " Print the number of ports.\n" - "\n" - " Usage2: %s \n" - " Print the status of .\n" - "\n" - " Usage3: %s reset\n" - " Reset .\n" - "\n" - " Usage4: %s update ...\n" - " Update firmware of .\n", - cmd, cmd, cmd, cmd); + " Usage1: %s\n" + " Print the number of ports.\n" + "\n" + " Usage2: %s \n" + " Print the status of .\n" + "\n" + " Usage3: %s reset\n" + " Reset .\n" + "\n" + " Usage4: %s update ...\n" + " Update firmware of .\n", + cmd, cmd, cmd, cmd); } static int cmd_pchg_info(const struct ec_response_pchg *res) { - static const char * const pchg_state_text[] = EC_PCHG_STATE_TEXT; + static const char *const pchg_state_text[] = EC_PCHG_STATE_TEXT; BUILD_ASSERT(ARRAY_SIZE(pchg_state_text) == PCHG_STATE_COUNT); - printf("State: %s (%d)\n", res->state < PCHG_STATE_COUNT - ? pchg_state_text[res->state] : "UNDEF", res->state); + printf("State: %s (%d)\n", + res->state < PCHG_STATE_COUNT ? pchg_state_text[res->state] : + "UNDEF", + res->state); printf("Battery: %u%%\n", res->battery_percentage); printf("Errors: 0x%x\n", res->error); printf("FW Version: 0x%x\n", res->fw_version); @@ -9578,8 +9535,8 @@ static int cmd_pchg_wait_event(int port, uint32_t expected) return 0; } - fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n", - expected, *e); + fprintf(stderr, "\nExpected event=0x%x but received 0x%x\n", expected, + *e); return -1; } @@ -9618,8 +9575,8 @@ static int cmd_pchg_update_open(int port, uint32_t version, rv = ec_command(EC_CMD_PCHG, 2, &p, sizeof(p), &rv2, sizeof(rv2)); if (rv == -EC_RES_INVALID_VERSION - EECRESULT) /* We can use v2 because it's a superset of v1. */ - rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), - &rv2, sizeof(struct ec_response_pchg)); + rv = ec_command(EC_CMD_PCHG, 1, &p, sizeof(p), &rv2, + sizeof(struct ec_response_pchg)); if (rv < 0) { fprintf(stderr, "EC_CMD_PCHG failed: %d\n", rv); return rv; @@ -9633,8 +9590,8 @@ static int cmd_pchg_update_open(int port, uint32_t version, if (rv) return rv; - printf("Opened update session (port=%d ver=0x%x bsize=%d):\n", - port, version, r->block_size); + printf("Opened update session (port=%d ver=0x%x bsize=%d):\n", port, + version, r->block_size); *block_size = r->block_size; crc32_ctx_init(crc); @@ -9655,8 +9612,8 @@ static int cmd_pchg_update_write(int port, uint32_t address, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "\nCan't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "\nCan't open %s: %s\n", filename, + strerror(errno)); return -1; } @@ -9676,8 +9633,8 @@ static int cmd_pchg_update_write(int port, uint32_t address, crc32_ctx_hash(crc, p->data, len); p->size = len; - rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, - sizeof(*p) + len, NULL, 0); + rv = ec_command(EC_CMD_PCHG_UPDATE, 0, p, sizeof(*p) + len, + NULL, 0); if (rv < 0) { fprintf(stderr, "\nFailed to write FW: %d\n", rv); fclose(fp); @@ -9776,8 +9733,8 @@ static int cmd_pchg(int argc, char *argv[]) u->cmd = EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL; rv = ec_command(EC_CMD_PCHG_UPDATE, 0, u, sizeof(*u), NULL, 0); if (rv < 0) { - fprintf(stderr, "\nFailed to reset port %d: %d\n", - port, rv); + fprintf(stderr, "\nFailed to reset port %d: %d\n", port, + rv); cmd_pchg_help(argv[0]); return rv; } @@ -9825,12 +9782,12 @@ static int cmd_pchg(int argc, char *argv[]) cmd_pchg_help(argv[0]); return -1; } - rv = cmd_pchg_update_write(port, address, argv[i+1], + rv = cmd_pchg_update_write(port, address, argv[i + 1], block_size, &crc); if (rv < 0) { fprintf(stderr, "\nFailed to write file '%s': %d", - argv[i+i], rv); + argv[i + i], rv); return -1; } } @@ -9868,8 +9825,8 @@ int cmd_pd_log(int argc, char *argv[]) while (1) { now = time(NULL); - rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0, - NULL, 0, &u, sizeof(u)); + rv = ec_command(EC_CMD_PD_GET_LOG_ENTRY, 0, NULL, 0, &u, + sizeof(u)); if (rv < 0) return rv; @@ -9879,8 +9836,9 @@ int cmd_pd_log(int argc, char *argv[]) } /* the timestamp is in 1024th of seconds */ - milliseconds = ((uint64_t)u.r.timestamp << - PD_LOG_TIMESTAMP_SHIFT) / 1000; + milliseconds = + ((uint64_t)u.r.timestamp << PD_LOG_TIMESTAMP_SHIFT) / + 1000; /* the timestamp is the number of milliseconds in the past */ seconds = (milliseconds + 999) / 1000; milliseconds -= seconds * 1000; @@ -9888,18 +9846,18 @@ int cmd_pd_log(int argc, char *argv[]) localtime_r(&now, <ime); strftime(time_str, sizeof(time_str), "%F %T", <ime); printf("%s.%03lld P%d ", time_str, -milliseconds, - PD_LOG_PORT(u.r.size_port)); + PD_LOG_PORT(u.r.size_port)); if (u.r.type == PD_EVENT_MCU_CHARGE) { if (u.r.data & CHARGE_FLAGS_OVERRIDE) printf("override "); if (u.r.data & CHARGE_FLAGS_DELAYED_OVERRIDE) printf("pending_override "); memcpy(&pinfo.meas, u.r.payload, - sizeof(struct usb_chg_measures)); + sizeof(struct usb_chg_measures)); pinfo.dualrole = !!(u.r.data & CHARGE_FLAGS_DUAL_ROLE); pinfo.role = u.r.data & CHARGE_FLAGS_ROLE_MASK; - pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK) - >> CHARGE_FLAGS_TYPE_SHIFT; + pinfo.type = (u.r.data & CHARGE_FLAGS_TYPE_MASK) >> + CHARGE_FLAGS_TYPE_SHIFT; pinfo.max_power = 0; print_pd_power_info(&pinfo); } else if (u.r.type == PD_EVENT_MCU_CONNECT) { @@ -9909,25 +9867,24 @@ int cmd_pd_log(int argc, char *argv[]) } else if (u.r.type == PD_EVENT_ACC_RW_FAIL) { printf("RW signature check failed\n"); } else if (u.r.type == PD_EVENT_PS_FAULT) { - static const char * const fault_names[] = { + static const char *const fault_names[] = { "---", "OCP", "fast OCP", "OVP", "Discharge" }; const char *fault = u.r.data < ARRAY_SIZE(fault_names) ? - fault_names[u.r.data] : "???"; + fault_names[u.r.data] : + "???"; printf("Power supply fault: %s\n", fault); } else if (u.r.type == PD_EVENT_VIDEO_DP_MODE) { - printf("DP mode %sabled\n", (u.r.data == 1) ? - "en" : "dis"); + printf("DP mode %sabled\n", + (u.r.data == 1) ? "en" : "dis"); } else if (u.r.type == PD_EVENT_VIDEO_CODEC) { - memcpy(&minfo, u.r.payload, - sizeof(struct mcdp_info)); + memcpy(&minfo, u.r.payload, sizeof(struct mcdp_info)); printf("HDMI info: family:%04x chipid:%04x " "irom:%d.%d.%d fw:%d.%d.%d\n", MCDP_FAMILY(minfo.family), - MCDP_CHIPID(minfo.chipid), - minfo.irom.major, minfo.irom.minor, - minfo.irom.build, minfo.fw.major, - minfo.fw.minor, minfo.fw.build); + MCDP_CHIPID(minfo.chipid), minfo.irom.major, + minfo.irom.minor, minfo.irom.build, + minfo.fw.major, minfo.fw.minor, minfo.fw.build); } else { /* Unknown type */ int i; printf("Event %02x (%04x) [", u.r.type, u.r.data); @@ -9990,7 +9947,8 @@ int cmd_pd_chip_info(int argc, char *argv[]) int cmdver = 1; if (argc < 2 || 3 < argc) { - fprintf(stderr, "Usage: %s []\n" + fprintf(stderr, + "Usage: %s []\n" "live parameter can take values 0 or 1\n" "0 -> Return hard-coded value for VID/PID and\n" " cached value for Firmware Version\n" @@ -10046,8 +10004,7 @@ int cmd_pd_write_log(int argc, char *argv[]) char *e; if (argc < 3) { - fprintf(stderr, "Usage: %s \n", - argv[0]); + fprintf(stderr, "Usage: %s \n", argv[0]); return -1; } @@ -10130,7 +10087,7 @@ int cmd_typec_control(int argc, char *argv[]) conversion_result = strtol(argv[3], &endptr, 0); if ((endptr && *endptr) || conversion_result > UINT8_MAX || - conversion_result < 0) { + conversion_result < 0) { fprintf(stderr, "Bad mode\n"); return -1; } @@ -10144,7 +10101,7 @@ int cmd_typec_control(int argc, char *argv[]) conversion_result = strtol(argv[3], &endptr, 0); if ((endptr && *endptr) || conversion_result > UINT8_MAX || - conversion_result < 0) { + conversion_result < 0) { fprintf(stderr, "Bad reply\n"); return -1; } @@ -10158,7 +10115,7 @@ int cmd_typec_control(int argc, char *argv[]) conversion_result = strtol(argv[3], &endptr, 0); if ((endptr && *endptr) || conversion_result > UINT8_MAX || - conversion_result < 0) { + conversion_result < 0) { fprintf(stderr, "Bad index\n"); return -1; } @@ -10184,8 +10141,8 @@ int cmd_typec_control(int argc, char *argv[]) break; } - rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_TYPEC_CONTROL, 0, &p, sizeof(p), ec_inbuf, + ec_max_insize); if (rv < 0) return -1; @@ -10196,7 +10153,7 @@ int cmd_typec_discovery(int argc, char *argv[]) { struct ec_params_typec_discovery p; struct ec_response_typec_discovery *r = - (struct ec_response_typec_discovery *)ec_inbuf; + (struct ec_response_typec_discovery *)ec_inbuf; char *e; int rv, i, j; @@ -10206,7 +10163,8 @@ int cmd_typec_discovery(int argc, char *argv[]) " is the type-c port to query\n" " is one of:\n" " 0: SOP\n" - " 1: SOP prime\n", argv[0]); + " 1: SOP prime\n", + argv[0]); return -1; } @@ -10222,8 +10180,8 @@ int cmd_typec_discovery(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_TYPEC_DISCOVERY, 0, &p, sizeof(p), ec_inbuf, + ec_max_insize); if (rv < 0) return -1; @@ -10253,10 +10211,8 @@ int cmd_typec_discovery(int argc, char *argv[]) /* Print shared fields of sink and source cap PDOs */ static inline void print_pdo_fixed(uint32_t pdo) { - printf(" Fixed: %dmV %dmA %s%s%s%s", - PDO_FIXED_VOLTAGE(pdo), - PDO_FIXED_CURRENT(pdo), - pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "", + printf(" Fixed: %dmV %dmA %s%s%s%s", PDO_FIXED_VOLTAGE(pdo), + PDO_FIXED_CURRENT(pdo), pdo & PDO_FIXED_DUAL_ROLE ? "DRP " : "", pdo & PDO_FIXED_UNCONSTRAINED ? "UP " : "", pdo & PDO_FIXED_COMM_CAP ? "USB " : "", pdo & PDO_FIXED_DATA_SWAP ? "DRD" : ""); @@ -10265,24 +10221,21 @@ static inline void print_pdo_fixed(uint32_t pdo) static inline void print_pdo_battery(uint32_t pdo) { printf(" Battery: max %dmV min %dmV max %dmW\n", - PDO_BATT_MAX_VOLTAGE(pdo), - PDO_BATT_MIN_VOLTAGE(pdo), + PDO_BATT_MAX_VOLTAGE(pdo), PDO_BATT_MIN_VOLTAGE(pdo), PDO_BATT_MAX_POWER(pdo)); } static inline void print_pdo_variable(uint32_t pdo) { printf(" Variable: max %dmV min %dmV max %dmA\n", - PDO_VAR_MAX_VOLTAGE(pdo), - PDO_VAR_MIN_VOLTAGE(pdo), + PDO_VAR_MAX_VOLTAGE(pdo), PDO_VAR_MIN_VOLTAGE(pdo), PDO_VAR_MAX_CURRENT(pdo)); } static inline void print_pdo_augmented(uint32_t pdo) { printf(" Augmented: max %dmV min %dmV max %dmA\n", - PDO_AUG_MAX_VOLTAGE(pdo), - PDO_AUG_MIN_VOLTAGE(pdo), + PDO_AUG_MAX_VOLTAGE(pdo), PDO_AUG_MIN_VOLTAGE(pdo), PDO_AUG_MAX_CURRENT(pdo)); } @@ -10290,7 +10243,7 @@ int cmd_typec_status(int argc, char *argv[]) { struct ec_params_typec_status p; struct ec_response_typec_status *r = - (struct ec_response_typec_status *)ec_inbuf; + (struct ec_response_typec_status *)ec_inbuf; char *endptr; int rv, i; const char *desc; @@ -10298,7 +10251,8 @@ int cmd_typec_status(int argc, char *argv[]) if (argc != 2) { fprintf(stderr, "Usage: %s \n" - " is the type-c port to query\n", argv[0]); + " is the type-c port to query\n", + argv[0]); return -1; } @@ -10308,8 +10262,8 @@ int cmd_typec_status(int argc, char *argv[]) return -1; } - rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p), - ec_inbuf, ec_max_insize); + rv = ec_command(EC_CMD_TYPEC_STATUS, 0, &p, sizeof(p), ec_inbuf, + ec_max_insize); if (rv == -EC_RES_INVALID_COMMAND - EECRESULT) /* Fall back to PD_CONTROL to support older ECs */ return cmd_usb_pd(argc, argv); @@ -10318,15 +10272,14 @@ int cmd_typec_status(int argc, char *argv[]) printf("Port C%d: %s, %s State:%s\n" "Role:%s %s%s, Polarity:CC%d\n", - p.port, - r->pd_enabled ? "enabled" : "disabled", - r->dev_connected ? "connected" : "disconnected", - r->tc_state, - (r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK", - (r->data_role == PD_ROLE_DFP) ? "DFP" : - (r->data_role == PD_ROLE_UFP) ? "UFP" : "", - (r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "", - (r->polarity % 2 + 1)); + p.port, r->pd_enabled ? "enabled" : "disabled", + r->dev_connected ? "connected" : "disconnected", r->tc_state, + (r->power_role == PD_ROLE_SOURCE) ? "SRC" : "SNK", + (r->data_role == PD_ROLE_DFP) ? "DFP" : + (r->data_role == PD_ROLE_UFP) ? "UFP" : + "", + (r->vconn_role == PD_ROLE_VCONN_SRC) ? " VCONN" : "", + (r->polarity % 2 + 1)); switch (r->cc_state) { case PD_CC_NONE: @@ -10385,8 +10338,9 @@ int cmd_typec_status(int argc, char *argv[]) " SAFE=%d TBT=%d USB4=%d\n", !!(r->mux_state & USB_PD_MUX_USB_ENABLED), !!(r->mux_state & USB_PD_MUX_DP_ENABLED), - (r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ? - "INVERTED" : "NORMAL", + (r->mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + "INVERTED" : + "NORMAL", !!(r->mux_state & USB_PD_MUX_HPD_IRQ), !!(r->mux_state & USB_PD_MUX_HPD_LVL), !!(r->mux_state & USB_PD_MUX_SAFE_MODE), @@ -10445,8 +10399,8 @@ int cmd_typec_status(int argc, char *argv[]) if (pdo_type == PDO_TYPE_FIXED) { print_pdo_fixed(pdo); /* Note: FRS bits are reserved in PD 2.0 spec */ - printf("%s\n", pdo & PDO_FIXED_FRS_CURR_MASK ? - "FRS" : ""); + printf("%s\n", + pdo & PDO_FIXED_FRS_CURR_MASK ? "FRS" : ""); } else if (pdo_type == PDO_TYPE_BATTERY) { print_pdo_battery(pdo); } else if (pdo_type == PDO_TYPE_VARIABLE) { @@ -10459,7 +10413,7 @@ int cmd_typec_status(int argc, char *argv[]) return 0; } -int cmd_tp_self_test(int argc, char* argv[]) +int cmd_tp_self_test(int argc, char *argv[]) { int rv; @@ -10473,13 +10427,13 @@ int cmd_tp_self_test(int argc, char* argv[]) return rv; } -int cmd_tp_frame_get(int argc, char* argv[]) +int cmd_tp_frame_get(int argc, char *argv[]) { int i, j; uint32_t remaining = 0, offset = 0; int rv = EC_SUCCESS; uint8_t *data; - struct ec_response_tp_frame_info* r; + struct ec_response_tp_frame_info *r; struct ec_params_tp_frame_get p; data = (uint8_t *)(malloc(ec_max_insize)); @@ -10513,11 +10467,13 @@ int cmd_tp_frame_get(int argc, char* argv[]) p.offset = offset; p.size = MIN(remaining, ec_max_insize); - rv = ec_command(EC_CMD_TP_FRAME_GET, 0, - &p, sizeof(p), data, p.size); + rv = ec_command(EC_CMD_TP_FRAME_GET, 0, &p, sizeof(p), + data, p.size); if (rv < 0) { - fprintf(stderr, "Failed to get frame data " - "at offset 0x%x\n", offset); + fprintf(stderr, + "Failed to get frame data " + "at offset 0x%x\n", + offset); goto err; } @@ -10551,8 +10507,7 @@ int cmd_wait_event(int argc, char *argv[]) } if (argc < 2) { - fprintf(stderr, "Usage: %s []\n", - argv[0]); + fprintf(stderr, "Usage: %s []\n", argv[0]); return -1; } @@ -10596,7 +10551,6 @@ static void cmd_cec_help(const char *cmd) " enable: Enable or disable CEC\n" " is 1 to enable, 0 to disable\n", cmd, cmd, cmd, cmd); - } static int cmd_cec_write(int argc, char *argv[]) @@ -10669,8 +10623,8 @@ static int cmd_cec_read(int argc, char *argv[]) } } - rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer, - sizeof(buffer), timeout); + rv = wait_event(EC_MKBP_EVENT_CEC_MESSAGE, &buffer, sizeof(buffer), + timeout); if (rv < 0) return rv; @@ -10718,18 +10672,15 @@ static int cmd_cec_set(int argc, char *argv[]) p.cmd = cmd; p.val = val; - return ec_command(EC_CMD_CEC_SET, - 0, &p, sizeof(p), NULL, 0); + return ec_command(EC_CMD_CEC_SET, 0, &p, sizeof(p), NULL, 0); } - static int cmd_cec_get(int argc, char *argv[]) { int rv, cmd; struct ec_params_cec_get p; struct ec_response_cec_get r; - if (argc != 3) { fprintf(stderr, "Invalid number of params\n"); cmd_cec_help(argv[0]); @@ -10743,7 +10694,6 @@ static int cmd_cec_get(int argc, char *argv[]) } p.cmd = cmd; - rv = ec_command(EC_CMD_CEC_GET, 0, &p, sizeof(p), &r, sizeof(r)); if (rv < 0) return rv; @@ -10777,150 +10727,150 @@ int cmd_cec(int argc, char *argv[]) /* NULL-terminated list of commands */ const struct command commands[] = { - {"adcread", cmd_adc_read}, - {"addentropy", cmd_add_entropy}, - {"apreset", cmd_apreset}, - {"autofanctrl", cmd_thermal_auto_fan_ctrl}, - {"backlight", cmd_lcd_backlight}, - {"basestate", cmd_basestate}, - {"battery", cmd_battery}, - {"batterycutoff", cmd_battery_cut_off}, - {"batteryparam", cmd_battery_vendor_param}, - {"boardversion", cmd_board_version}, - {"button", cmd_button}, - {"cbi", cmd_cbi}, - {"chargecurrentlimit", cmd_charge_current_limit}, - {"chargecontrol", cmd_charge_control}, - {"chargeoverride", cmd_charge_port_override}, - {"chargesplash", cmd_chargesplash}, - {"chargestate", cmd_charge_state}, - {"chipinfo", cmd_chipinfo}, - {"cmdversions", cmd_cmdversions}, - {"console", cmd_console}, - {"cec", cmd_cec}, - {"echash", cmd_ec_hash}, - {"eventclear", cmd_host_event_clear}, - {"eventclearb", cmd_host_event_clear_b}, - {"eventget", cmd_host_event_get_raw}, - {"eventgetb", cmd_host_event_get_b}, - {"eventgetscimask", cmd_host_event_get_sci_mask}, - {"eventgetsmimask", cmd_host_event_get_smi_mask}, - {"eventgetwakemask", cmd_host_event_get_wake_mask}, - {"eventsetscimask", cmd_host_event_set_sci_mask}, - {"eventsetsmimask", cmd_host_event_set_smi_mask}, - {"eventsetwakemask", cmd_host_event_set_wake_mask}, - {"extpwrlimit", cmd_ext_power_limit}, - {"fanduty", cmd_fanduty}, - {"flasherase", cmd_flash_erase}, - {"flasheraseasync", cmd_flash_erase}, - {"flashprotect", cmd_flash_protect}, - {"flashread", cmd_flash_read}, - {"flashwrite", cmd_flash_write}, - {"flashinfo", cmd_flash_info}, - {"flashspiinfo", cmd_flash_spi_info}, - {"flashpd", cmd_flash_pd}, - {"forcelidopen", cmd_force_lid_open}, - {"fpcontext", cmd_fp_context}, - {"fpencstatus", cmd_fp_enc_status}, - {"fpframe", cmd_fp_frame}, - {"fpinfo", cmd_fp_info}, - {"fpmode", cmd_fp_mode}, - {"fpseed", cmd_fp_seed}, - {"fpstats", cmd_fp_stats}, - {"fptemplate", cmd_fp_template}, - {"gpioget", cmd_gpio_get}, - {"gpioset", cmd_gpio_set}, - {"hangdetect", cmd_hang_detect}, - {"hello", cmd_hello}, - {"hibdelay", cmd_hibdelay}, - {"hostevent", cmd_hostevent}, - {"hostsleepstate", cmd_hostsleepstate}, - {"locatechip", cmd_locate_chip}, - {"i2cprotect", cmd_i2c_protect}, - {"i2cread", cmd_i2c_read}, - {"i2cspeed", cmd_i2c_speed}, - {"i2cwrite", cmd_i2c_write}, - {"i2cxfer", cmd_i2c_xfer}, - {"infopddev", cmd_pd_device_info}, - {"inventory", cmd_inventory}, - {"led", cmd_led}, - {"lightbar", cmd_lightbar}, - {"kbfactorytest", cmd_keyboard_factory_test}, - {"kbid", cmd_kbid}, - {"kbinfo", cmd_kbinfo}, - {"kbpress", cmd_kbpress}, - {"keyconfig", cmd_keyconfig}, - {"keyscan", cmd_keyscan}, - {"mkbpget", cmd_mkbp_get}, - {"mkbpwakemask", cmd_mkbp_wake_mask}, - {"motionsense", cmd_motionsense}, - {"nextevent", cmd_next_event}, - {"panicinfo", cmd_panic_info}, - {"pause_in_s5", cmd_s5}, - {"pchg", cmd_pchg}, - {"pdgetmode", cmd_pd_get_amode}, - {"pdsetmode", cmd_pd_set_amode}, - {"port80read", cmd_port80_read}, - {"pdlog", cmd_pd_log}, - {"pdcontrol", cmd_pd_control}, - {"pdchipinfo", cmd_pd_chip_info}, - {"pdwritelog", cmd_pd_write_log}, - {"powerinfo", cmd_power_info}, - {"protoinfo", cmd_proto_info}, - {"pse", cmd_pse}, - {"pstoreinfo", cmd_pstore_info}, - {"pstoreread", cmd_pstore_read}, - {"pstorewrite", cmd_pstore_write}, - {"pwmgetfanrpm", cmd_pwm_get_fan_rpm}, - {"pwmgetkblight", cmd_pwm_get_keyboard_backlight}, - {"pwmgetnumfans", cmd_pwm_get_num_fans}, - {"pwmgetduty", cmd_pwm_get_duty}, - {"pwmsetfanrpm", cmd_pwm_set_fan_rpm}, - {"pwmsetkblight", cmd_pwm_set_keyboard_backlight}, - {"pwmsetduty", cmd_pwm_set_duty}, - {"rand", cmd_rand}, - {"readtest", cmd_read_test}, - {"reboot_ec", cmd_reboot_ec}, - {"rgbkbd", cmd_rgbkbd}, - {"rollbackinfo", cmd_rollback_info}, - {"rtcget", cmd_rtc_get}, - {"rtcgetalarm", cmd_rtc_get_alarm}, - {"rtcset", cmd_rtc_set}, - {"rtcsetalarm", cmd_rtc_set_alarm}, - {"rwhashpd", cmd_rw_hash_pd}, - {"rwsig", cmd_rwsig}, - {"rwsigaction", cmd_rwsig_action_legacy}, - {"rwsigstatus", cmd_rwsig_status}, - {"sertest", cmd_serial_test}, - {"smartdischarge", cmd_smart_discharge}, - {"stress", cmd_stress_test}, - {"sysinfo", cmd_sysinfo}, - {"port80flood", cmd_port_80_flood}, - {"switches", cmd_switches}, - {"temps", cmd_temperature}, - {"tempsinfo", cmd_temp_sensor_info}, - {"test", cmd_test}, - {"thermalget", cmd_thermal_get_threshold}, - {"thermalset", cmd_thermal_set_threshold}, - {"tpselftest", cmd_tp_self_test}, - {"tpframeget", cmd_tp_frame_get}, - {"tmp006cal", cmd_tmp006cal}, - {"tmp006raw", cmd_tmp006raw}, - {"typeccontrol", cmd_typec_control}, - {"typecdiscovery", cmd_typec_discovery}, - {"typecstatus", cmd_typec_status}, - {"uptimeinfo", cmd_uptimeinfo}, - {"usbchargemode", cmd_usb_charge_set_mode}, - {"usbmux", cmd_usb_mux}, - {"usbpd", cmd_usb_pd}, - {"usbpddps", cmd_usb_pd_dps}, - {"usbpdmuxinfo", cmd_usb_pd_mux_info}, - {"usbpdpower", cmd_usb_pd_power}, - {"version", cmd_version}, - {"waitevent", cmd_wait_event}, - {"wireless", cmd_wireless}, - {"reboot_ap_on_g3", cmd_reboot_ap_on_g3}, - {NULL, NULL} + { "adcread", cmd_adc_read }, + { "addentropy", cmd_add_entropy }, + { "apreset", cmd_apreset }, + { "autofanctrl", cmd_thermal_auto_fan_ctrl }, + { "backlight", cmd_lcd_backlight }, + { "basestate", cmd_basestate }, + { "battery", cmd_battery }, + { "batterycutoff", cmd_battery_cut_off }, + { "batteryparam", cmd_battery_vendor_param }, + { "boardversion", cmd_board_version }, + { "button", cmd_button }, + { "cbi", cmd_cbi }, + { "chargecurrentlimit", cmd_charge_current_limit }, + { "chargecontrol", cmd_charge_control }, + { "chargeoverride", cmd_charge_port_override }, + { "chargesplash", cmd_chargesplash }, + { "chargestate", cmd_charge_state }, + { "chipinfo", cmd_chipinfo }, + { "cmdversions", cmd_cmdversions }, + { "console", cmd_console }, + { "cec", cmd_cec }, + { "echash", cmd_ec_hash }, + { "eventclear", cmd_host_event_clear }, + { "eventclearb", cmd_host_event_clear_b }, + { "eventget", cmd_host_event_get_raw }, + { "eventgetb", cmd_host_event_get_b }, + { "eventgetscimask", cmd_host_event_get_sci_mask }, + { "eventgetsmimask", cmd_host_event_get_smi_mask }, + { "eventgetwakemask", cmd_host_event_get_wake_mask }, + { "eventsetscimask", cmd_host_event_set_sci_mask }, + { "eventsetsmimask", cmd_host_event_set_smi_mask }, + { "eventsetwakemask", cmd_host_event_set_wake_mask }, + { "extpwrlimit", cmd_ext_power_limit }, + { "fanduty", cmd_fanduty }, + { "flasherase", cmd_flash_erase }, + { "flasheraseasync", cmd_flash_erase }, + { "flashprotect", cmd_flash_protect }, + { "flashread", cmd_flash_read }, + { "flashwrite", cmd_flash_write }, + { "flashinfo", cmd_flash_info }, + { "flashspiinfo", cmd_flash_spi_info }, + { "flashpd", cmd_flash_pd }, + { "forcelidopen", cmd_force_lid_open }, + { "fpcontext", cmd_fp_context }, + { "fpencstatus", cmd_fp_enc_status }, + { "fpframe", cmd_fp_frame }, + { "fpinfo", cmd_fp_info }, + { "fpmode", cmd_fp_mode }, + { "fpseed", cmd_fp_seed }, + { "fpstats", cmd_fp_stats }, + { "fptemplate", cmd_fp_template }, + { "gpioget", cmd_gpio_get }, + { "gpioset", cmd_gpio_set }, + { "hangdetect", cmd_hang_detect }, + { "hello", cmd_hello }, + { "hibdelay", cmd_hibdelay }, + { "hostevent", cmd_hostevent }, + { "hostsleepstate", cmd_hostsleepstate }, + { "locatechip", cmd_locate_chip }, + { "i2cprotect", cmd_i2c_protect }, + { "i2cread", cmd_i2c_read }, + { "i2cspeed", cmd_i2c_speed }, + { "i2cwrite", cmd_i2c_write }, + { "i2cxfer", cmd_i2c_xfer }, + { "infopddev", cmd_pd_device_info }, + { "inventory", cmd_inventory }, + { "led", cmd_led }, + { "lightbar", cmd_lightbar }, + { "kbfactorytest", cmd_keyboard_factory_test }, + { "kbid", cmd_kbid }, + { "kbinfo", cmd_kbinfo }, + { "kbpress", cmd_kbpress }, + { "keyconfig", cmd_keyconfig }, + { "keyscan", cmd_keyscan }, + { "mkbpget", cmd_mkbp_get }, + { "mkbpwakemask", cmd_mkbp_wake_mask }, + { "motionsense", cmd_motionsense }, + { "nextevent", cmd_next_event }, + { "panicinfo", cmd_panic_info }, + { "pause_in_s5", cmd_s5 }, + { "pchg", cmd_pchg }, + { "pdgetmode", cmd_pd_get_amode }, + { "pdsetmode", cmd_pd_set_amode }, + { "port80read", cmd_port80_read }, + { "pdlog", cmd_pd_log }, + { "pdcontrol", cmd_pd_control }, + { "pdchipinfo", cmd_pd_chip_info }, + { "pdwritelog", cmd_pd_write_log }, + { "powerinfo", cmd_power_info }, + { "protoinfo", cmd_proto_info }, + { "pse", cmd_pse }, + { "pstoreinfo", cmd_pstore_info }, + { "pstoreread", cmd_pstore_read }, + { "pstorewrite", cmd_pstore_write }, + { "pwmgetfanrpm", cmd_pwm_get_fan_rpm }, + { "pwmgetkblight", cmd_pwm_get_keyboard_backlight }, + { "pwmgetnumfans", cmd_pwm_get_num_fans }, + { "pwmgetduty", cmd_pwm_get_duty }, + { "pwmsetfanrpm", cmd_pwm_set_fan_rpm }, + { "pwmsetkblight", cmd_pwm_set_keyboard_backlight }, + { "pwmsetduty", cmd_pwm_set_duty }, + { "rand", cmd_rand }, + { "readtest", cmd_read_test }, + { "reboot_ec", cmd_reboot_ec }, + { "rgbkbd", cmd_rgbkbd }, + { "rollbackinfo", cmd_rollback_info }, + { "rtcget", cmd_rtc_get }, + { "rtcgetalarm", cmd_rtc_get_alarm }, + { "rtcset", cmd_rtc_set }, + { "rtcsetalarm", cmd_rtc_set_alarm }, + { "rwhashpd", cmd_rw_hash_pd }, + { "rwsig", cmd_rwsig }, + { "rwsigaction", cmd_rwsig_action_legacy }, + { "rwsigstatus", cmd_rwsig_status }, + { "sertest", cmd_serial_test }, + { "smartdischarge", cmd_smart_discharge }, + { "stress", cmd_stress_test }, + { "sysinfo", cmd_sysinfo }, + { "port80flood", cmd_port_80_flood }, + { "switches", cmd_switches }, + { "temps", cmd_temperature }, + { "tempsinfo", cmd_temp_sensor_info }, + { "test", cmd_test }, + { "thermalget", cmd_thermal_get_threshold }, + { "thermalset", cmd_thermal_set_threshold }, + { "tpselftest", cmd_tp_self_test }, + { "tpframeget", cmd_tp_frame_get }, + { "tmp006cal", cmd_tmp006cal }, + { "tmp006raw", cmd_tmp006raw }, + { "typeccontrol", cmd_typec_control }, + { "typecdiscovery", cmd_typec_discovery }, + { "typecstatus", cmd_typec_status }, + { "uptimeinfo", cmd_uptimeinfo }, + { "usbchargemode", cmd_usb_charge_set_mode }, + { "usbmux", cmd_usb_mux }, + { "usbpd", cmd_usb_pd }, + { "usbpddps", cmd_usb_pd_dps }, + { "usbpdmuxinfo", cmd_usb_pd_mux_info }, + { "usbpdpower", cmd_usb_pd_power }, + { "version", cmd_version }, + { "waitevent", cmd_wait_event }, + { "wireless", cmd_wireless }, + { "reboot_ap_on_g3", cmd_reboot_ap_on_g3 }, + { NULL, NULL } }; int main(int argc, char *argv[]) @@ -10981,8 +10931,8 @@ int main(int argc, char *argv[]) break; case OPT_I2C_BUS: i2c_bus = strtoull(optarg, &e, 0); - if (*optarg == '\0' || (e && *e != '\0') - || i2c_bus < 0) { + if (*optarg == '\0' || (e && *e != '\0') || + i2c_bus < 0) { fprintf(stderr, "Invalid --i2c_bus\n"); parse_error = 1; } @@ -10993,9 +10943,10 @@ int main(int argc, char *argv[]) } } - if (i2c_bus != -1) { + if (i2c_bus != -1) { if (!(interfaces & COMM_I2C)) { - fprintf(stderr, "--i2c_bus is specified, but --interface is set to something other than I2C\n"); + fprintf(stderr, + "--i2c_bus is specified, but --interface is set to something other than I2C\n"); parse_error = 1; } else { interfaces = COMM_I2C; @@ -11034,7 +10985,7 @@ int main(int argc, char *argv[]) /* Lock is not needed for COMM_USB */ if (!(interfaces & COMM_USB) && - acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) { + acquire_gec_lock(GEC_LOCK_TIMEOUT_SECS) < 0) { fprintf(stderr, "Could not acquire GEC lock.\n"); exit(1); } -- cgit v1.2.1 From c596d0c965946f6bd90716cf0d80df5ac927646a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:02 -0600 Subject: test/usb_pd_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I31cda5899b36d87bd5d4ab25052cda6ce9efb654 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730550 Reviewed-by: Jeremy Bettis --- test/usb_pd_console.c | 57 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 29 deletions(-) diff --git a/test/usb_pd_console.c b/test/usb_pd_console.c index 0c8ad63542..8587edfe94 100644 --- a/test/usb_pd_console.c +++ b/test/usb_pd_console.c @@ -140,7 +140,7 @@ uint8_t board_get_usb_pd_port_count(void) } void pe_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data, - int count) + int count) { int i; @@ -249,7 +249,7 @@ enum pd_cc_states pd_get_task_cc_state(int port) static int test_command_pd_dump(void) { int argc = 3; - char *argv[] = {"pd", "dump", "", 0, 0, 0}; + char *argv[] = { "pd", "dump", "", 0, 0, 0 }; char test[2]; sprintf(test, "e"); @@ -277,7 +277,7 @@ static int test_command_pd_dump(void) static int test_command_pd_try_src(void) { int argc = 3; - char *argv[] = {"pd", "trysrc", "2", 0, 0}; + char *argv[] = { "pd", "trysrc", "2", 0, 0 }; try_src_override = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -297,7 +297,7 @@ static int test_command_pd_try_src(void) static int test_command_pd_version(void) { int argc = 2; - char *argv[] = {"pd", "version", 0, 0, 0}; + char *argv[] = { "pd", "version", 0, 0, 0 }; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -307,7 +307,7 @@ static int test_command_pd_version(void) static int test_command_pd_arg_count(void) { int argc; - char *argv[] = {"pd", "", 0, 0, 0}; + char *argv[] = { "pd", "", 0, 0, 0 }; for (argc = 0; argc < 3; argc++) TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT); @@ -318,7 +318,7 @@ static int test_command_pd_arg_count(void) static int test_command_pd_port_num(void) { int argc = 3; - char *argv[10] = {"pd", "0", 0, 0, 0}; + char *argv[10] = { "pd", "0", 0, 0, 0 }; char test[2]; sprintf(test, "%d", CONFIG_USB_PD_PORT_MAX_COUNT); @@ -331,7 +331,7 @@ static int test_command_pd_port_num(void) static int test_command_pd_tx(void) { int argc = 3; - char *argv[] = {"pd", "0", "tx", 0, 0}; + char *argv[] = { "pd", "0", "tx", 0, 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -344,7 +344,7 @@ static int test_command_pd_tx(void) static int test_command_pd_charger(void) { int argc = 3; - char *argv[] = {"pd", "1", "charger", 0, 0}; + char *argv[] = { "pd", "1", "charger", 0, 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -357,7 +357,7 @@ static int test_command_pd_charger(void) static int test_command_pd_dev1(void) { int argc = 4; - char *argv[] = {"pd", "0", "dev", "20", 0}; + char *argv[] = { "pd", "0", "dev", "20", 0 }; request = 0; max_volt = 0; @@ -372,7 +372,7 @@ static int test_command_pd_dev1(void) static int test_command_pd_dev2(void) { int argc = 3; - char *argv[] = {"pd", "1", "dev", 0, 0}; + char *argv[] = { "pd", "1", "dev", 0, 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -386,7 +386,7 @@ static int test_command_pd_dev2(void) static int test_command_pd_disable(void) { int argc = 3; - char *argv[] = {"pd", "0", "disable", 0, 0}; + char *argv[] = { "pd", "0", "disable", 0, 0 }; comm_enable = 1; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -399,7 +399,7 @@ static int test_command_pd_disable(void) static int test_command_pd_enable(void) { int argc = 3; - char *argv[] = {"pd", "1", "enable", 0, 0}; + char *argv[] = { "pd", "1", "enable", 0, 0 }; comm_enable = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -412,7 +412,7 @@ static int test_command_pd_enable(void) static int test_command_pd_hard(void) { int argc = 3; - char *argv[] = {"pd", "0", "hard", 0, 0}; + char *argv[] = { "pd", "0", "hard", 0, 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -425,7 +425,7 @@ static int test_command_pd_hard(void) static int test_command_pd_soft(void) { int argc = 3; - char *argv[] = {"pd", "0", "soft", 0, 0}; + char *argv[] = { "pd", "0", "soft", 0, 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -438,7 +438,7 @@ static int test_command_pd_soft(void) static int test_command_pd_swap1(void) { int argc = 3; - char *argv[] = {"pd", "0", "swap", 0, 0}; + char *argv[] = { "pd", "0", "swap", 0, 0 }; TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM_COUNT); @@ -448,7 +448,7 @@ static int test_command_pd_swap1(void) static int test_command_pd_swap2(void) { int argc = 4; - char *argv[] = {"pd", "0", "swap", "power", 0}; + char *argv[] = { "pd", "0", "swap", "power", 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -461,7 +461,7 @@ static int test_command_pd_swap2(void) static int test_command_pd_swap3(void) { int argc = 4; - char *argv[] = {"pd", "1", "swap", "data", 0}; + char *argv[] = { "pd", "1", "swap", "data", 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -474,7 +474,7 @@ static int test_command_pd_swap3(void) static int test_command_pd_swap4(void) { int argc = 4; - char *argv[] = {"pd", "0", "swap", "vconn", 0}; + char *argv[] = { "pd", "0", "swap", "vconn", 0 }; request = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -487,7 +487,7 @@ static int test_command_pd_swap4(void) static int test_command_pd_swap5(void) { int argc = 4; - char *argv[] = {"pd", "0", "swap", "xyz", 0}; + char *argv[] = { "pd", "0", "swap", "xyz", 0 }; TEST_ASSERT(command_pd(argc, argv) == EC_ERROR_PARAM3); @@ -497,7 +497,7 @@ static int test_command_pd_swap5(void) static int test_command_pd_dualrole0(void) { int argc = 3; - char *argv[] = {"pd", "0", "dualrole", 0, 0}; + char *argv[] = { "pd", "0", "dualrole", 0, 0 }; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -507,7 +507,7 @@ static int test_command_pd_dualrole0(void) static int test_command_pd_dualrole1(void) { int argc = 4; - char *argv[] = {"pd", "0", "dualrole", "on", 0}; + char *argv[] = { "pd", "0", "dualrole", "on", 0 }; dr_state = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -520,7 +520,7 @@ static int test_command_pd_dualrole1(void) static int test_command_pd_dualrole2(void) { int argc = 4; - char *argv[] = {"pd", "0", "dualrole", "off", 0}; + char *argv[] = { "pd", "0", "dualrole", "off", 0 }; dr_state = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -533,7 +533,7 @@ static int test_command_pd_dualrole2(void) static int test_command_pd_dualrole3(void) { int argc = 4; - char *argv[] = {"pd", "0", "dualrole", "freeze", 0}; + char *argv[] = { "pd", "0", "dualrole", "freeze", 0 }; dr_state = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -546,7 +546,7 @@ static int test_command_pd_dualrole3(void) static int test_command_pd_dualrole4(void) { int argc = 4; - char *argv[] = {"pd", "0", "dualrole", "sink", 0}; + char *argv[] = { "pd", "0", "dualrole", "sink", 0 }; dr_state = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -559,7 +559,7 @@ static int test_command_pd_dualrole4(void) static int test_command_pd_dualrole5(void) { int argc = 4; - char *argv[] = {"pd", "0", "dualrole", "source", 0}; + char *argv[] = { "pd", "0", "dualrole", "source", 0 }; dr_state = 0; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -572,7 +572,7 @@ static int test_command_pd_dualrole5(void) static int test_command_pd_state(void) { int argc = 3; - char *argv[] = {"pd", "0", "state", 0, 0}; + char *argv[] = { "pd", "0", "state", 0, 0 }; pd_get_polarity_called = false; pd_comm_is_enabled_called = false; @@ -601,7 +601,7 @@ static int test_command_pd_state(void) static int test_command_pd_srccaps(void) { int argc = 3; - char *argv[] = {"pd", "0", "srccaps", 0, 0}; + char *argv[] = { "pd", "0", "srccaps", 0, 0 }; pd_srccaps_dump_called = false; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -613,7 +613,7 @@ static int test_command_pd_srccaps(void) static int test_command_pd_timer(void) { int argc = 3; - char *argv[] = {"pd", "0", "timer", 0, 0}; + char *argv[] = { "pd", "0", "timer", 0, 0 }; pd_timer_dump_called = false; TEST_ASSERT(command_pd(argc, argv) == EC_SUCCESS); @@ -622,7 +622,6 @@ static int test_command_pd_timer(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 7ca48102ea908d4f7dd2abc750d3954d4e58c82a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:12 -0600 Subject: common/mock/usb_tc_sm_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If87e96c88aab70e062a507271490fcdd932c9fca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729694 Reviewed-by: Jeremy Bettis --- common/mock/usb_tc_sm_mock.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/common/mock/usb_tc_sm_mock.c b/common/mock/usb_tc_sm_mock.c index d55def12e2..20802db127 100644 --- a/common/mock/usb_tc_sm_mock.c +++ b/common/mock/usb_tc_sm_mock.c @@ -26,7 +26,7 @@ void mock_tc_port_reset(void) { int port; - for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) { + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) { mock_tc_port[port].rev = PD_REV30; mock_tc_port[port].pd_enable = 0; mock_tc_port[port].msg_tx_id = 0; @@ -93,7 +93,8 @@ int tc_check_vconn_swap(int port) } void tc_ctvpd_detected(int port) -{} +{ +} int tc_is_vconn_src(int port) { @@ -106,31 +107,40 @@ void tc_hard_reset_request(int port) } void tc_partner_dr_data(int port, int en) -{} +{ +} void tc_partner_dr_power(int port, int en) -{} +{ +} void tc_partner_unconstrainedpower(int port, int en) -{} +{ +} void tc_partner_usb_comm(int port, int en) -{} +{ +} void tc_pd_connection(int port, int en) -{} +{ +} void tc_pr_swap_complete(int port, bool success) -{} +{ +} void tc_src_power_off(int port) -{} +{ +} void tc_start_error_recovery(int port) -{} +{ +} void tc_snk_power_off(int port) -{} +{ +} void tc_request_power_swap(int port) { @@ -200,13 +210,16 @@ enum tcpc_cc_polarity pd_get_polarity(int port) } void pd_request_data_swap(int port) -{} +{ +} void pd_request_vconn_swap_off(int port) -{} +{ +} void pd_request_vconn_swap_on(int port) -{} +{ +} bool pd_alt_mode_capable(int port) { -- cgit v1.2.1 From f2d424ec27c77b816f8d16ea57e1396d34f593ef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:15 -0600 Subject: baseboard/mtscp-rv32i/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2938f5483f7f0aae317ac1970afda02caa06cb24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727926 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/baseboard.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h index 3af9fe1af9..8776645d8f 100644 --- a/baseboard/mtscp-rv32i/baseboard.h +++ b/baseboard/mtscp-rv32i/baseboard.h @@ -21,8 +21,8 @@ /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 -#define CONFIG_IPC_SHARED_OBJ_ADDR \ - (SCP_FW_END - \ +#define CONFIG_IPC_SHARED_OBJ_ADDR \ + (SCP_FW_END - \ (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) #define CONFIG_IPI #define CONFIG_RPMSG_NAME_SERVICE @@ -62,7 +62,8 @@ #define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */ #ifdef CHIP_VARIANT_MT8195 -#define CONFIG_PANIC_DATA_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) +#define CONFIG_PANIC_DATA_BASE \ + (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) #endif /* MPU settings */ -- cgit v1.2.1 From 2684c3e5879d145ca6afe704a421045815ee9b72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:52 -0600 Subject: include/config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I69b033fd16f138d78ad024093968bd2236ea4f8d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730232 Reviewed-by: Jeremy Bettis --- include/config.h | 496 +++++++++++++++++++++++++------------------------------ 1 file changed, 227 insertions(+), 269 deletions(-) diff --git a/include/config.h b/include/config.h index 931ea405d7..87c4582642 100644 --- a/include/config.h +++ b/include/config.h @@ -623,7 +623,7 @@ * are supplied and charging will be disabled after * CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT seconds. */ -#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30*60*SECOND) +#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (30 * 60 * SECOND) /* * Specify the battery percentage at which the host is told it is full. @@ -695,7 +695,7 @@ * - If system fails to shutdown for some reason and battery further discharges * to 2%, EC will trigger shutdown. */ -#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */ +#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 4 /* shutdown if soc <= 4% */ /* * Powerd's full_factor. The value comes from: @@ -703,7 +703,7 @@ * * This value is used by the host to calculate the ETA for full charge. */ -#define CONFIG_BATT_HOST_FULL_FACTOR 97 +#define CONFIG_BATT_HOST_FULL_FACTOR 97 /* * Smart battery pass-through host commands. @@ -943,7 +943,6 @@ #undef CONFIG_CHARGER_SM5803 #undef CONFIG_CHARGER_SY21612 - /* Allow run-time completion of the charger driver structure */ #undef CONFIG_CHARGER_RUNTIME_CONFIG @@ -1120,7 +1119,6 @@ */ #undef CONFIG_CHARGER_BQ25710_CMP_POL_EXTERNAL - /* Enable if CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG should be applied */ #undef CONFIG_CHARGER_BQ25710_PKPWR_TOVLD_DEG_CUSTOM @@ -1234,8 +1232,8 @@ * analog signaling. If the AP requires greater than 15W to boot, then see * CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW. */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */ -#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2 /* Don't boot if soc < 2% */ +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC 1 /* Default: 15000 */ #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON /* Default: Disabled */ @@ -1395,38 +1393,38 @@ /* Chipset config */ /* AP chipset support; pick at most one */ -#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */ -#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) - * with power sequencer - * chip - */ -#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ -#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ -#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ -#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), - * discrete EC control - */ -#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */ -#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/ -#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ -#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ -#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */ -#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */ -#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ -#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ -#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */ -#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */ -#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ -#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ -#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ -#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */ -#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */ -#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ -#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ -#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ +#undef CONFIG_CHIPSET_ALDERLAKE /* Intel Alderlake (x86) */ +#undef CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 /* Intel Alderlake (x86) \ + * with power sequencer \ + * chip \ + */ +#undef CONFIG_CHIPSET_APOLLOLAKE /* Intel Apollolake (x86) */ +#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */ +#undef CONFIG_CHIPSET_COMETLAKE /* Intel Cometlake (x86) */ +#undef CONFIG_CHIPSET_COMETLAKE_DISCRETE /* Intel Cometlake (x86), \ + * discrete EC control \ + */ +#undef CONFIG_CHIPSET_ECDRIVEN /* Mock power module */ +#undef CONFIG_CHIPSET_FALCONLITE /* Falcon-lite*/ +#undef CONFIG_CHIPSET_GEMINILAKE /* Intel Geminilake (x86) */ +#undef CONFIG_CHIPSET_ICELAKE /* Intel Icelake (x86) */ +#undef CONFIG_CHIPSET_JASPERLAKE /* Intel Jasperlake (x86) */ +#undef CONFIG_CHIPSET_METEORLAKE /* Intel Meteorlake (x86) */ +#undef CONFIG_CHIPSET_MT817X /* MediaTek MT817x */ +#undef CONFIG_CHIPSET_MT8183 /* MediaTek MT8183 */ +#undef CONFIG_CHIPSET_MT8192 /* MediaTek MT8192 */ +#undef CONFIG_CHIPSET_CEZANNE /* AMD Cezanne (x86) */ +#undef CONFIG_CHIPSET_RK3288 /* Rockchip rk3288 */ +#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */ +#undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */ +#undef CONFIG_CHIPSET_SC7180 /* Qualcomm SC7180 */ +#undef CONFIG_CHIPSET_SC7280 /* Qualcomm SC7280 */ +#undef CONFIG_CHIPSET_SDM845 /* Qualcomm SDM845 */ +#undef CONFIG_CHIPSET_STONEY /* AMD Stoney (x86)*/ +#undef CONFIG_CHIPSET_TIGERLAKE /* Intel Tigerlake (x86) */ /* Shared chipset support; automatically gets defined below. */ -#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ +#undef CONFIG_CHIPSET_APL_GLK /* Apollolake & Geminilake */ /* Support chipset throttling */ #undef CONFIG_CHIPSET_CAN_THROTTLE @@ -1538,8 +1536,8 @@ * Required Configuration: * - CONFIG_BLINK_LEDS --> List of LEDs (gpio enum names) to use as bits */ -#undef CONFIG_BLINK -#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */ +#undef CONFIG_BLINK +#undef CONFIG_BLINK_LEDS /* Ex: GPIO_LED1, GPIO_LED2 */ /*****************************************************************************/ /* @@ -1549,20 +1547,20 @@ * console. */ -#undef CONFIG_CMD_ACCELS -#undef CONFIG_CMD_ACCEL_FIFO -#undef CONFIG_CMD_ACCEL_INFO +#undef CONFIG_CMD_ACCELS +#undef CONFIG_CMD_ACCEL_FIFO +#undef CONFIG_CMD_ACCEL_INFO #define CONFIG_CMD_ACCELSPOOF #define CONFIG_CMD_ADC -#undef CONFIG_CMD_ALS +#undef CONFIG_CMD_ALS #define CONFIG_CMD_APTHROTTLE -#undef CONFIG_CMD_BATDEBUG +#undef CONFIG_CMD_BATDEBUG #define CONFIG_CMD_BATTFAKE -#undef CONFIG_CMD_BATT_MFG_ACCESS -#undef CONFIG_CMD_BUTTON +#undef CONFIG_CMD_BATT_MFG_ACCESS +#undef CONFIG_CMD_BUTTON #define CONFIG_CMD_CBI -#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE -#undef CONFIG_CMD_VBUS +#undef CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE +#undef CONFIG_CMD_VBUS /* * HAS_TASK_CHIPSET implies the GSC presence. @@ -1575,97 +1573,97 @@ #undef CONFIG_CMD_CHARGEN #endif #define CONFIG_CMD_CHARGER -#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON -#undef CONFIG_CMD_CHARGER_DUMP -#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE -#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST +#undef CONFIG_CMD_CHARGER_ADC_AMON_BMON +#undef CONFIG_CMD_CHARGER_DUMP +#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE +#undef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST #define CONFIG_CMD_CHARGE_SUPPLIER_INFO -#undef CONFIG_CMD_CHGRAMP -#undef CONFIG_CMD_CLOCKGATES -#undef CONFIG_CMD_COMXTEST +#undef CONFIG_CMD_CHGRAMP +#undef CONFIG_CMD_CLOCKGATES +#undef CONFIG_CMD_COMXTEST #define CONFIG_CMD_CRASH #define CONFIG_CMD_DEVICE_EVENT -#undef CONFIG_CMD_DLOG -#undef CONFIG_CMD_ECTEMP +#undef CONFIG_CMD_DLOG +#undef CONFIG_CMD_ECTEMP #define CONFIG_CMD_FASTCHARGE -#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FLASH #define CONFIG_CMD_FLASHINFO -#undef CONFIG_CMD_FLASH_TRISTATE -#undef CONFIG_CMD_FORCETIME -#undef CONFIG_CMD_FPSENSOR_DEBUG +#undef CONFIG_CMD_FLASH_TRISTATE +#undef CONFIG_CMD_FORCETIME +#undef CONFIG_CMD_FPSENSOR_DEBUG #define CONFIG_CMD_GETTIME -#undef CONFIG_CMD_GL3590 -#undef CONFIG_CMD_GPIO_EXTENDED -#undef CONFIG_CMD_GT7288 +#undef CONFIG_CMD_GL3590 +#undef CONFIG_CMD_GPIO_EXTENDED +#undef CONFIG_CMD_GT7288 #define CONFIG_CMD_HASH #define CONFIG_CMD_HCDEBUG -#undef CONFIG_CMD_HOSTCMD -#undef CONFIG_CMD_I2CWEDGE -#undef CONFIG_CMD_I2C_PROTECT +#undef CONFIG_CMD_HOSTCMD +#undef CONFIG_CMD_I2CWEDGE +#undef CONFIG_CMD_I2C_PROTECT #define CONFIG_CMD_I2C_SCAN -#undef CONFIG_CMD_I2C_SPEED -#undef CONFIG_CMD_I2C_STRESS_TEST -#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL -#undef CONFIG_CMD_I2C_STRESS_TEST_ALS -#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY -#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER -#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC +#undef CONFIG_CMD_I2C_SPEED +#undef CONFIG_CMD_I2C_STRESS_TEST +#undef CONFIG_CMD_I2C_STRESS_TEST_ACCEL +#undef CONFIG_CMD_I2C_STRESS_TEST_ALS +#undef CONFIG_CMD_I2C_STRESS_TEST_BATTERY +#undef CONFIG_CMD_I2C_STRESS_TEST_CHARGER +#undef CONFIG_CMD_I2C_STRESS_TEST_TCPC #define CONFIG_CMD_I2C_XFER -#undef CONFIG_CMD_I2C_XFER_RAW +#undef CONFIG_CMD_I2C_XFER_RAW #define CONFIG_CMD_IDLE_STATS #define CONFIG_CMD_INA -#undef CONFIG_CMD_JUMPTAGS +#undef CONFIG_CMD_JUMPTAGS #define CONFIG_CMD_KEYBOARD -#undef CONFIG_CMD_LEDTEST -#undef CONFIG_CMD_MCDP +#undef CONFIG_CMD_LEDTEST +#undef CONFIG_CMD_MCDP #define CONFIG_CMD_MD #define CONFIG_CMD_MEM #define CONFIG_CMD_MFALLOW #define CONFIG_CMD_MMAPINFO #define CONFIG_CMD_PD -#undef CONFIG_CMD_PD_DEV_DUMP_INFO -#undef CONFIG_CMD_PD_FLASH -#undef CONFIG_CMD_PD_TIMER +#undef CONFIG_CMD_PD_DEV_DUMP_INFO +#undef CONFIG_CMD_PD_FLASH +#undef CONFIG_CMD_PD_TIMER #define CONFIG_CMD_PECI -#undef CONFIG_CMD_PLL +#undef CONFIG_CMD_PLL #define CONFIG_CMD_POWERINDEBUG -#undef CONFIG_CMD_POWERLED +#undef CONFIG_CMD_POWERLED #define CONFIG_CMD_PWR_AVG #define CONFIG_CMD_POWER_AP -#undef CONFIG_CMD_PPC_DUMP -#undef CONFIG_CMD_PS2 -#undef CONFIG_CMD_RAND +#undef CONFIG_CMD_PPC_DUMP +#undef CONFIG_CMD_PS2 +#undef CONFIG_CMD_RAND #define CONFIG_CMD_REGULATOR -#undef CONFIG_CMD_RESET_FLAGS +#undef CONFIG_CMD_RESET_FLAGS #define CONFIG_CMD_RETIMER -#undef CONFIG_CMD_RTC -#undef CONFIG_CMD_RTC_ALARM +#undef CONFIG_CMD_RTC +#undef CONFIG_CMD_RTC_ALARM #define CONFIG_CMD_RW -#undef CONFIG_CMD_S5_TIMEOUT -#undef CONFIG_CMD_SCRATCHPAD -#undef CONFIG_CMD_SEVEN_SEG_DISPLAY +#undef CONFIG_CMD_S5_TIMEOUT +#undef CONFIG_CMD_SCRATCHPAD +#undef CONFIG_CMD_SEVEN_SEG_DISPLAY #define CONFIG_CMD_SHMEM -#undef CONFIG_CMD_SLEEP +#undef CONFIG_CMD_SLEEP #define CONFIG_CMD_SLEEPMASK #define CONFIG_CMD_SLEEPMASK_SET -#undef CONFIG_CMD_SPI_FLASH -#undef CONFIG_CMD_SPI_NOR -#undef CONFIG_CMD_SPI_XFER -#undef CONFIG_CMD_STACKOVERFLOW +#undef CONFIG_CMD_SPI_FLASH +#undef CONFIG_CMD_SPI_NOR +#undef CONFIG_CMD_SPI_XFER +#undef CONFIG_CMD_STACKOVERFLOW #define CONFIG_CMD_SYSINFO #define CONFIG_CMD_SYSJUMP #define CONFIG_CMD_SYSLOCK -#undef CONFIG_CMD_TASK_RESET -#undef CONFIG_CMD_TASKREADY -#undef CONFIG_CMD_TCPC_DUMP +#undef CONFIG_CMD_TASK_RESET +#undef CONFIG_CMD_TASKREADY +#undef CONFIG_CMD_TCPC_DUMP #define CONFIG_CMD_TEMP_SENSOR #define CONFIG_CMD_TIMERINFO #define CONFIG_CMD_TYPEC -#undef CONFIG_CMD_USART_INFO -#undef CONFIG_CMD_USB_PD_CABLE -#undef CONFIG_CMD_USB_PD_PE +#undef CONFIG_CMD_USART_INFO +#undef CONFIG_CMD_USB_PD_CABLE +#undef CONFIG_CMD_USB_PD_PE #define CONFIG_CMD_WAITMS -#undef CONFIG_CMD_AP_RESET_LOG +#undef CONFIG_CMD_AP_RESET_LOG /*****************************************************************************/ @@ -2239,7 +2237,6 @@ /* If defined, protect rollback region readback using MPU. */ #undef CONFIG_ROLLBACK_MPU_PROTECT - /* * If defined, inject some locally generated entropy when secret is updated, * using board_get_entropy function. @@ -2437,7 +2434,7 @@ #ifdef HAS_TASK_HOSTCMD #define CONFIG_HOSTCMD_EVENTS #else -#undef CONFIG_HOSTCMD_EVENTS +#undef CONFIG_HOSTCMD_EVENTS #endif /* @@ -2467,9 +2464,9 @@ * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be * enforced. */ -#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC) -#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC) -#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC) +#define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC) /* PD MCU supports host commands */ #undef CONFIG_HOSTCMD_PD @@ -2529,11 +2526,11 @@ * List of host commands whose debug output will be suppressed * By default remove periodic commands and commands called often (SENSE). */ -#define CONFIG_SUPPRESSED_HOST_COMMANDS \ +#define CONFIG_SUPPRESSED_HOST_COMMANDS \ EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_USB_PD_DISCOVERY, \ - EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \ - EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT, EC_CMD_GET_UPTIME_INFO - + EC_CMD_USB_PD_POWER_INFO, EC_CMD_PD_GET_LOG_ENTRY, \ + EC_CMD_MOTION_SENSE_CMD, EC_CMD_GET_NEXT_EVENT, \ + EC_CMD_GET_UPTIME_INFO /*****************************************************************************/ @@ -2775,7 +2772,6 @@ #undef CONFIG_INA231 #undef CONFIG_INA3221 - /*****************************************************************************/ /* Inductive charging */ @@ -3152,16 +3148,16 @@ #undef CONFIG_LED_POWER_ACTIVE_LOW /* Support for LED driver chip(s) */ -#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */ -#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */ +#undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */ +#undef CONFIG_LED_DRIVER_LM3509 /* LM3509, on I2C interface */ #undef CONFIG_LED_DRIVER_LM3630A /* LM3630A, on I2C interface */ -#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */ -#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */ -#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */ +#undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */ +#undef CONFIG_LED_DRIVER_MP3385 /* MPS MP3385, on I2C */ +#undef CONFIG_LED_DRIVER_OZ554 /* O2Micro OZ554, on I2C */ #undef CONFIG_LED_DRIVER_IS31FL3733B /* Lumissil IS31FL3733B on I2C */ #undef CONFIG_LED_DRIVER_IS31FL3743B /* Lumissil IS31FL3743B on SPI */ -#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ -#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ +#undef CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ +#undef CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ /* Enable late init for is31fl3743b. Work around b:232443638. */ #undef CONFIG_IS31FL3743B_LATE_INIT @@ -3576,7 +3572,7 @@ #undef CONFIG_POWER_BUTTON_INIT_IDLE /* Timeout before power button task gives up starting system */ -#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1 +#define CONFIG_POWER_BUTTON_INIT_TIMEOUT 1 /* * Enable delay between DSW_PWROK and PWRBTN assertion. @@ -4146,28 +4142,28 @@ #undef CONFIG_TEMP_SENSOR /* Support particular temperature sensor chips */ -#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */ -#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek F75303 sensor, on I2C bus */ -#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_ADT7481 /* ADT 7481 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_EC_ADC /* Thermistors on EC's own ADC */ +#undef CONFIG_TEMP_SENSOR_G753 /* G753 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_G782 /* G782 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_OTI502 /* OTI502 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_PCT2075 /* PCT2075 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_SB_TSI /* SB_TSI sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP112 /* TI TMP112 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP411 /* TI TMP411 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_TMP468 /* TI TMP468 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_F75303 /* Fintek F75303 sensor, on I2C bus */ +#undef CONFIG_TEMP_SENSOR_AMD_R19ME4070 /* AMD_R19ME4070 sensor, on I2C bus */ /* Compile common code for thermistor support */ #undef CONFIG_THERMISTOR /* Support particular thermistors */ -#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */ +#undef CONFIG_THERMISTOR_NCP15WB /* NCP15WB thermistor */ /* * If defined, image includes lookup tables and helper functions that convert @@ -4679,7 +4675,7 @@ * Some TCPCs need additional time following a VBUS change to internally * debounce the CC line status and updating the CC_STATUS register. */ -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (25 * MSEC) /* Define EC and TCPC modules are in one integrated chip */ #undef CONFIG_USB_PD_TCPC_ON_CHIP @@ -5140,7 +5136,6 @@ /* The delay in ms from power off to power on for MAX14637 */ #define CONFIG_BC12_MAX14637_DELAY_FROM_OFF_TO_ON_MS 1 - /* Enable USB serial console module. */ #undef CONFIG_USB_CONSOLE @@ -5415,7 +5410,6 @@ */ #undef CONFIG_STREAM_SIGNATURE - /*****************************************************************************/ /* @@ -5663,7 +5657,7 @@ * Used to include files for unit and other builds tests. */ - /* Define to enable Policy Engine State Machine. */ +/* Define to enable Policy Engine State Machine. */ #undef CONFIG_TEST_USB_PE_SM /* Define to enable USB State Machine framework. */ @@ -5690,13 +5684,13 @@ /* * The USB port used for CCD. Defaults to 0/C0. */ -#define CONFIG_CCD_USBC_PORT_NUMBER 0 +#define CONFIG_CCD_USBC_PORT_NUMBER 0 /* * The historical default SCI pulse width to the host is 65 microseconds, but * some chipsets may require different widths. */ -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 65 +#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 65 /*****************************************************************************/ /* @@ -5722,7 +5716,7 @@ * Define CONFIG_HOST_ESPI_VW_POWER_SIGNAL if any power signals from the host * are configured as virtual wires. */ -#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \ +#if defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S3) || \ defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S4) || \ defined(CONFIG_HOSTCMD_ESPI_VW_SLP_S5) #define CONFIG_HOST_ESPI_VW_POWER_SIGNAL @@ -5745,7 +5739,7 @@ * without using eSPI for host commands. */ #if (!defined(CONFIG_ZEPHYR) && defined(CONFIG_HOST_ESPI_VW_POWER_SIGNAL) && \ - !defined(CONFIG_HOST_INTERFACE_ESPI)) + !defined(CONFIG_HOST_INTERFACE_ESPI)) #error Must enable eSPI to enable virtual wires. #endif @@ -5776,7 +5770,7 @@ #if !defined(CONFIG_USBC_SS_MUX) #error CONFIG_USBC_SS_MUX must be enabled for USB4 mode support #endif -# if !defined(CONFIG_USB_PD_ALT_MODE_DFP) +#if !defined(CONFIG_USB_PD_ALT_MODE_DFP) #error CONFIG_USB_PD_ALT_MODE_DFP must be enabled for USB4 mode support #endif #endif @@ -5823,9 +5817,9 @@ * Ensure that CONFIG_USB_PD_TCPMV2 is being used with exactly one device type */ #ifdef CONFIG_USB_PD_TCPMV2 -#if defined(CONFIG_USB_VPD) + \ - defined(CONFIG_USB_CTVPD) + \ - defined(CONFIG_USB_DRP_ACC_TRYSRC) != 1 +#if defined(CONFIG_USB_VPD) + defined(CONFIG_USB_CTVPD) + \ + defined(CONFIG_USB_DRP_ACC_TRYSRC) != \ + 1 #error Must define exactly one CONFIG_USB_ device type. #endif #endif @@ -5846,7 +5840,7 @@ #error Define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT is limited to TCPMv1 #endif #ifndef CONFIG_USB_PD_3A_PORTS -#define CONFIG_USB_PD_3A_PORTS 1 +#define CONFIG_USB_PD_3A_PORTS 1 #endif /* USB4 support requires at least one port providing 3.0 A */ #if defined(CONFIG_USB_PD_USB4) && CONFIG_USB_PD_3A_PORTS == 0 @@ -5854,14 +5848,13 @@ #endif #endif - /******************************************************************************/ /* * Ensure CONFIG_USB_PD_TCPMV2 and CONFIG_USBC_SS_MUX both are defined. USBC * retimer firmware update feature requires both. */ #if (defined(CONFIG_USBC_RETIMER_FW_UPDATE) && \ - (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX)))) + (!(defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USBC_SS_MUX)))) #error Retimer firmware update requires TCPMv2 and USBC_SS_MUX #endif @@ -5878,8 +5871,7 @@ #error Must select only one type of host communication bus. #endif -#if defined(CONFIG_HOSTCMD_X86) && \ - !defined(CONFIG_HOST_INTERFACE_LPC) && \ +#if defined(CONFIG_HOSTCMD_X86) && !defined(CONFIG_HOST_INTERFACE_LPC) && \ !defined(CONFIG_HOST_INTERFACE_ESPI) #error Must select one type of host communication bus. #endif @@ -5903,11 +5895,11 @@ /* Automatic configuration of RAM banks **************************************/ /* Assume one RAM bank if not specified, auto-compute number of banks */ #ifndef CONFIG_RAM_BANK_SIZE -#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE +#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE #endif #ifndef CONFIG_RAM_BANKS -#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) +#define CONFIG_RAM_BANKS (CONFIG_RAM_SIZE / CONFIG_RAM_BANK_SIZE) #endif /******************************************************************************/ @@ -5918,13 +5910,12 @@ * the beginning of RAM. */ #ifndef CONFIG_PANIC_DATA_SIZE -#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data) +#define CONFIG_PANIC_DATA_SIZE sizeof(struct panic_data) #endif #ifndef CONFIG_PANIC_DATA_BASE -#define CONFIG_PANIC_DATA_BASE (CONFIG_RAM_BASE \ - + CONFIG_RAM_SIZE \ - - CONFIG_PANIC_DATA_SIZE) +#define CONFIG_PANIC_DATA_BASE \ + (CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE) #endif /******************************************************************************/ @@ -5956,7 +5947,6 @@ #endif #endif /* !CONFIG_SHAREDMEM_MINIMUM_SIZE */ - /******************************************************************************/ /* * Disable the built-in console history if using the experimental console. @@ -5969,7 +5959,6 @@ #define CONFIG_CRC8 #endif /* defined(CONFIG_EXPERIMENTAL_CONSOLE) */ - /******************************************************************************/ /* * Thermal throttling AP must have temperature sensor enabled to get @@ -5988,7 +5977,6 @@ #define CONFIG_TEMP_SENSOR #endif - /******************************************************************************/ /* The Matrix Keyboard Protocol depends on MKBP input devices and events. */ #ifdef CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -6002,18 +5990,18 @@ /******************************************************************************/ /* MKBP events delivery methods. */ #ifdef CONFIG_MKBP_EVENT -#if !defined(CONFIG_MKBP_USE_CUSTOM) && \ - !defined(CONFIG_MKBP_USE_HOST_EVENT) && \ - !defined(CONFIG_MKBP_USE_GPIO) && \ +#if !defined(CONFIG_MKBP_USE_CUSTOM) && \ + !defined(CONFIG_MKBP_USE_HOST_EVENT) && \ + !defined(CONFIG_MKBP_USE_GPIO) && \ !defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) && \ !defined(CONFIG_MKBP_USE_HECI) #error Please define one of CONFIG_MKBP_USE_* macro. #endif -#if defined(CONFIG_MKBP_USE_CUSTOM) + \ - defined(CONFIG_MKBP_USE_GPIO) + \ - defined(CONFIG_MKBP_USE_HOST_EVENT) + \ - defined(CONFIG_MKBP_USE_HOST_HECI) > 1 +#if defined(CONFIG_MKBP_USE_CUSTOM) + defined(CONFIG_MKBP_USE_GPIO) + \ + defined(CONFIG_MKBP_USE_HOST_EVENT) + \ + defined(CONFIG_MKBP_USE_HOST_HECI) > \ + 1 #error Must select only one type of MKBP event delivery method. #endif #endif /* CONFIG_MKBP_EVENT */ @@ -6030,27 +6018,22 @@ /*****************************************************************************/ /* Define CONFIG_BATTERY if board has a battery. */ -#if defined(CONFIG_BATTERY_BQ20Z453) || \ - defined(CONFIG_BATTERY_BQ27541) || \ - defined(CONFIG_BATTERY_BQ27621) || \ - defined(CONFIG_BATTERY_BQ4050) || \ - defined(CONFIG_BATTERY_MAX17055) || \ - defined(CONFIG_BATTERY_MM8013) || \ +#if defined(CONFIG_BATTERY_BQ20Z453) || defined(CONFIG_BATTERY_BQ27541) || \ + defined(CONFIG_BATTERY_BQ27621) || defined(CONFIG_BATTERY_BQ4050) || \ + defined(CONFIG_BATTERY_MAX17055) || defined(CONFIG_BATTERY_MM8013) || \ defined(CONFIG_BATTERY_SMART) #define CONFIG_BATTERY #endif /*****************************************************************************/ /* Define CONFIG_USBC_PPC if board has a USB Type-C Power Path Controller. */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_NX20P3483) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3483) || \ defined(CONFIG_USBC_PPC_SN5S330) #define CONFIG_USBC_PPC #endif /* "has a PPC" */ /* Following chips use Power Path Control information from TCPC chip */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_NX20P3481) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_NX20P3481) || \ defined(CONFIG_USBC_PPC_NX20P3483) #define CONFIG_USB_PD_PPC #endif @@ -6062,7 +6045,6 @@ #define CONFIG_USBC_PPC_VCONN #endif - /*****************************************************************************/ /* PPC SYV682C is a subset of SYV682X. */ #if defined(CONFIG_USBC_PPC_SYV682C) @@ -6099,13 +6081,11 @@ /*****************************************************************************/ /* Define CONFIG_USBC_OCP if a component can detect overcurrent */ -#if defined(CONFIG_USBC_PPC_AOZ1380) || \ - defined(CONFIG_USBC_PPC_KTU1125) || \ - defined(CONFIG_USBC_PPC_NX20P3481) || \ - defined(CONFIG_USBC_PPC_NX20P3483) || \ - defined(CONFIG_USBC_PPC_SN5S330) || \ - defined(CONFIG_USBC_PPC_SYV682X) || \ - defined(CONFIG_CHARGER_SM5803) || \ +#if defined(CONFIG_USBC_PPC_AOZ1380) || defined(CONFIG_USBC_PPC_KTU1125) || \ + defined(CONFIG_USBC_PPC_NX20P3481) || \ + defined(CONFIG_USBC_PPC_NX20P3483) || \ + defined(CONFIG_USBC_PPC_SN5S330) || \ + defined(CONFIG_USBC_PPC_SYV682X) || defined(CONFIG_CHARGER_SM5803) || \ defined(CONFIG_USB_PD_TCPM_TCPCI) #define CONFIG_USBC_OCP #endif @@ -6115,14 +6095,10 @@ * Define CONFIG_USB_PD_VBUS_MEASURE_CHARGER if the charger on the board * supports VBUS measurement. */ -#if defined(CONFIG_CHARGER_BD9995X) || \ - defined(CONFIG_CHARGER_RT9466) || \ - defined(CONFIG_CHARGER_RT9467) || \ - defined(CONFIG_CHARGER_RT9490) || \ - defined(CONFIG_CHARGER_MT6370) || \ - defined(CONFIG_CHARGER_BQ25710) || \ - defined(CONFIG_CHARGER_BQ25720) || \ - defined(CONFIG_CHARGER_ISL9241) +#if defined(CONFIG_CHARGER_BD9995X) || defined(CONFIG_CHARGER_RT9466) || \ + defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_RT9490) || \ + defined(CONFIG_CHARGER_MT6370) || defined(CONFIG_CHARGER_BQ25710) || \ + defined(CONFIG_CHARGER_BQ25720) || defined(CONFIG_CHARGER_ISL9241) #define CONFIG_USB_PD_VBUS_MEASURE_CHARGER #ifdef CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT @@ -6161,7 +6137,7 @@ * Define CONFIG_CHARGER_NARROW_VDC for chargers that use a Narrow VDC power * architecture. */ -#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \ +#if defined(CONFIG_CHARGER_ISL9237) || defined(CONFIG_CHARGER_ISL9238) || \ defined(CONFIG_CHARGER_ISL9238C) || defined(CONFIG_CHARGER_ISL9241) || \ defined(CONFIG_CHARGER_RAA489000) || defined(CONFIG_CHARGER_SM5803) || \ defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_BQ25720) @@ -6177,7 +6153,6 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON) */ - #ifdef CONFIG_LED_PWM_COUNT #define CONFIG_LED_PWM #endif /* defined(CONFIG_LED_PWM_COUNT) */ @@ -6212,7 +6187,7 @@ /*****************************************************************************/ /* Define derived USB PD Discharge common path */ -#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ +#if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) || \ defined(CONFIG_USB_PD_DISCHARGE_PPC) #define CONFIG_USB_PD_DISCHARGE @@ -6284,7 +6259,7 @@ #ifndef CONFIG_AP_POWER_CONTROL #ifdef HAS_TASK_CHIPSET #define CONFIG_AP_POWER_CONTROL -#endif /* HAS_TASK_CHIPSET */ +#endif /* HAS_TASK_CHIPSET */ #endif /* CONFIG_AP_POWER_CONTROL */ /* @@ -6305,12 +6280,11 @@ #endif /* !defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) */ #endif /* defined(HAS_TASK_CHIPSET) */ - #ifdef CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW -# ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT -# define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \ +#ifndef CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT \ (CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) -# endif +#endif #endif #ifndef CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON @@ -6379,13 +6353,11 @@ /*****************************************************************************/ /* Define derived Chipset configs */ -#if defined(CONFIG_CHIPSET_APOLLOLAKE) || \ - defined(CONFIG_CHIPSET_GEMINILAKE) +#if defined(CONFIG_CHIPSET_APOLLOLAKE) || defined(CONFIG_CHIPSET_GEMINILAKE) #define CONFIG_CHIPSET_APL_GLK #endif -#if defined(CONFIG_CHIPSET_JASPERLAKE) || \ - defined(CONFIG_CHIPSET_TIGERLAKE) || \ +#if defined(CONFIG_CHIPSET_JASPERLAKE) || defined(CONFIG_CHIPSET_TIGERLAKE) || \ defined(CONFIG_CHIPSET_ALDERLAKE) #define CONFIG_CHIPSET_ICELAKE #endif @@ -6395,23 +6367,21 @@ #define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 #endif -#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ - defined(CONFIG_CHIPSET_APOLLOLAKE) || \ - defined(CONFIG_CHIPSET_CANNONLAKE) || \ - defined(CONFIG_CHIPSET_COMETLAKE) || \ +#if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ + defined(CONFIG_CHIPSET_APOLLOLAKE) || \ + defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_COMETLAKE) || \ defined(CONFIG_CHIPSET_COMETLAKE_DISCRETE) || \ - defined(CONFIG_CHIPSET_GEMINILAKE) || \ - defined(CONFIG_CHIPSET_ICELAKE) || \ - defined(CONFIG_CHIPSET_METEORLAKE) || \ - defined(CONFIG_CHIPSET_SKYLAKE) + defined(CONFIG_CHIPSET_GEMINILAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE) #define CONFIG_POWER_COMMON #endif #if defined(CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) || \ - defined(CONFIG_CHIPSET_CANNONLAKE) || \ - defined(CONFIG_CHIPSET_ICELAKE) || \ - defined(CONFIG_CHIPSET_METEORLAKE) || \ - defined(CONFIG_CHIPSET_SKYLAKE) + defined(CONFIG_CHIPSET_CANNONLAKE) || \ + defined(CONFIG_CHIPSET_ICELAKE) || \ + defined(CONFIG_CHIPSET_METEORLAKE) || defined(CONFIG_CHIPSET_SKYLAKE) #define CONFIG_CHIPSET_X86_RSMRST_DELAY #endif @@ -6440,8 +6410,7 @@ /* * Automatically define CONFIG_ACCEL_LIS2D_COMMON if a child option is defined. */ -#if defined(CONFIG_ACCEL_LIS2DH) || \ - defined(CONFIG_ACCEL_LIS2DE) || \ +#if defined(CONFIG_ACCEL_LIS2DH) || defined(CONFIG_ACCEL_LIS2DE) || \ defined(CONFIG_ACCEL_LNG2DM) #define CONFIG_ACCEL_LIS2D_COMMON #endif @@ -6449,8 +6418,7 @@ /* * Automatically define CONFIG_ACCEL_LIS2DW_COMMON if a child option is defined. */ -#if defined(CONFIG_ACCEL_LIS2DW12) || \ - defined(CONFIG_ACCEL_LIS2DWL) +#if defined(CONFIG_ACCEL_LIS2DW12) || defined(CONFIG_ACCEL_LIS2DWL) #define CONFIG_ACCEL_LIS2DW_COMMON #endif @@ -6458,8 +6426,7 @@ * CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL can't be defined at the same * time. */ -#if defined(CONFIG_ACCEL_LIS2DW12) && \ - defined(CONFIG_ACCEL_LIS2DWL) +#if defined(CONFIG_ACCEL_LIS2DW12) && defined(CONFIG_ACCEL_LIS2DWL) #error "Define only one of CONFIG_ACCEL_LIS2DW12 and CONFIG_ACCEL_LIS2DWL" #endif @@ -6497,7 +6464,6 @@ #error CONFIG_CHIP_INIT_ROM_REGION requires CONFIG_RW_ROM_RESIDENT_SIZE #endif - #if (CONFIG_RO_ROM_RESIDENT_SIZE == 0) #error CONFIG_RO_ROM_RESIDENT_SIZE is 0 with CONFIG_CHIP_INIT_ROM_REGION defined #endif @@ -6543,7 +6509,7 @@ * period. */ #ifdef CONFIG_WATCHDOG -#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2) +#if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS)*2) #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS" #endif #endif @@ -6562,20 +6528,17 @@ #endif /* Enable BMI secondary port if needed. */ -#if defined(CONFIG_MAG_BMI_BMM150) || \ - defined(CONFIG_MAG_BMI_LIS2MDL) +#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_BMI_LIS2MDL) #define CONFIG_BMI_SEC_I2C #endif /* Enable LSM2MDL secondary port if needed. */ -#if defined(CONFIG_MAG_LSM6DSM_BMM150) || \ - defined(CONFIG_MAG_LSM6DSM_LIS2MDL) +#if defined(CONFIG_MAG_LSM6DSM_BMM150) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL) #define CONFIG_LSM6DSM_SEC_I2C #endif /* Load LIS2MDL driver if needed */ -#if defined(CONFIG_MAG_BMI_LIS2MDL) || \ - defined(CONFIG_MAG_LSM6DSM_LIS2MDL) +#if defined(CONFIG_MAG_BMI_LIS2MDL) || defined(CONFIG_MAG_LSM6DSM_LIS2MDL) #define CONFIG_MAG_LIS2MDL #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS #error "The i2c address of the magnetometer is not set." @@ -6583,8 +6546,7 @@ #endif /* Load BMM150 driver if needed */ -#if defined(CONFIG_MAG_BMI_BMM150) || \ - defined(CONFIG_MAG_LSM6DSM_BMM150) +#if defined(CONFIG_MAG_BMI_BMM150) || defined(CONFIG_MAG_LSM6DSM_BMM150) #define CONFIG_MAG_BMM150 #ifndef CONFIG_ACCELGYRO_SEC_ADDR_FLAGS #error "The i2c address of the magnetometer is not set." @@ -6617,7 +6579,7 @@ #endif #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ -#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \ +#if defined(CONFIG_USB_PD_TCPM_ANX3429) || \ defined(CONFIG_USB_PD_TCPM_ANX740X) || \ defined(CONFIG_USB_PD_TCPM_ANX7471) /* Note: ANX7447 is handled by its own driver, not ANX74XX. */ @@ -6643,10 +6605,8 @@ /*****************************************************************************/ /* ISH power management related definitions */ -#if defined(CONFIG_ISH_PM_D0I2) || \ - defined(CONFIG_ISH_PM_D0I3) || \ - defined(CONFIG_ISH_PM_D3) || \ - defined(CONFIG_ISH_PM_RESET_PREP) +#if defined(CONFIG_ISH_PM_D0I2) || defined(CONFIG_ISH_PM_D0I3) || \ + defined(CONFIG_ISH_PM_D3) || defined(CONFIG_ISH_PM_RESET_PREP) #ifndef CONFIG_LOW_POWER_IDLE #error "Must define CONFIG_LOW_POWER_IDLE if enable ISH low power states" @@ -6679,7 +6639,6 @@ #endif /* CONFIG_ACCEL_FIFO */ - /* * If USB PD Discharge is enabled, verify that CONFIG_USB_PD_DISCHARGE_GPIO * and CONFIG_USB_PD_PORT_MAX_COUNT, CONFIG_USB_PD_DISCHARGE_TCPC, or @@ -6750,21 +6709,21 @@ #endif #if defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX) -#if defined(CONFIG_USB_PD_TCPM_PS8705) + \ - defined(CONFIG_USB_PD_TCPM_PS8751) + \ - defined(CONFIG_USB_PD_TCPM_PS8755) + \ - defined(CONFIG_USB_PD_TCPM_PS8805) + \ - defined(CONFIG_USB_PD_TCPM_PS8815) < 2 +#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \ + defined(CONFIG_USB_PD_TCPM_PS8755) + \ + defined(CONFIG_USB_PD_TCPM_PS8805) + \ + defined(CONFIG_USB_PD_TCPM_PS8815) < \ + 2 #error "Must select 2 CONFIG_USB_PD_TCPM_PS8* or above if " \ "CONFIG_USB_PD_TCPM_MULTI_PS8XXX is defined." #endif #endif /* CONFIG_USB_PD_TCPM_MULTI_PS8XXX */ -#if defined(CONFIG_USB_PD_TCPM_PS8705) + \ - defined(CONFIG_USB_PD_TCPM_PS8751) + \ - defined(CONFIG_USB_PD_TCPM_PS8755) + \ - defined(CONFIG_USB_PD_TCPM_PS8805) + \ - defined(CONFIG_USB_PD_TCPM_PS8815) > 1 +#if defined(CONFIG_USB_PD_TCPM_PS8705) + defined(CONFIG_USB_PD_TCPM_PS8751) + \ + defined(CONFIG_USB_PD_TCPM_PS8755) + \ + defined(CONFIG_USB_PD_TCPM_PS8805) + \ + defined(CONFIG_USB_PD_TCPM_PS8815) > \ + 1 #if !defined(CONFIG_USB_PD_TCPM_MULTI_PS8XXX) #error "CONFIG_USB_PD_TCPM_MULTI_PS8XXX MUST be defined if more than one " \ "CONFIG_USB_PD_TCPM_PS8* are intended to support in a board." @@ -6779,25 +6738,25 @@ #endif /* ifndef(CONFIG_BODY_DETECTION_SENSOR) */ #ifndef CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE -#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */ +#define CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE 250 /* max sensor odr (Hz) */ #endif #ifndef CONFIG_BODY_DETECTION_VAR_THRESHOLD -#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */ +#define CONFIG_BODY_DETECTION_VAR_THRESHOLD 550 /* (mm/s^2)^2 */ #endif #ifndef CONFIG_BODY_DETECTION_CONFIDENCE_DELTA -#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */ +#define CONFIG_BODY_DETECTION_CONFIDENCE_DELTA 525 /* (mm/s^2)^2 */ #endif #ifndef CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR -#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */ +#define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 120 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_ON_BODY_CON -#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */ +#define CONFIG_BODY_DETECTION_ON_BODY_CON 50 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_OFF_BODY_CON -#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */ +#define CONFIG_BODY_DETECTION_OFF_BODY_CON 10 /* % */ #endif #ifndef CONFIG_BODY_DETECTION_STATIONARY_DURATION -#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */ +#define CONFIG_BODY_DETECTION_STATIONARY_DURATION 15 /* second */ #endif #else /* CONFIG_BODY_DETECTION */ @@ -6841,7 +6800,6 @@ #define ALS_COUNT 0 #endif /* CONFIG_ALS */ - /* * If the EC has exclusive control over CBI EEPROM WP, don't consult the main * flash WP. @@ -6876,9 +6834,9 @@ #else #define CONFIG_ACCELGYRO_ICM_COMM_SPI #endif -#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && - * !CONFIG_ACCELGYRO_ICM_COMM_I2C - */ +#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_ICM_COMM_SPI && \ + * !CONFIG_ACCELGYRO_ICM_COMM_I2C \ + */ #if !defined(CONFIG_ZEPHYR) && !defined(CONFIG_ACCELGYRO_BMI_COMM_SPI) && \ !defined(CONFIG_ACCELGYRO_BMI_COMM_I2C) @@ -6887,9 +6845,9 @@ #else #define CONFIG_ACCELGYRO_BMI_COMM_SPI #endif -#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \ - * !CONFIG_ACCELGYRO_BMI_I2C - */ +#endif /* !CONFIG_ZEPHYR && !CONFIG_ACCELGYRO_BMI_SPI && \ + * !CONFIG_ACCELGYRO_BMI_I2C \ + */ /* AMD STT requires AMD SB-RMI to be enabled */ #if defined(CONFIG_AMD_STT) && !defined(CONFIG_AMD_SB_RMI) @@ -6904,4 +6862,4 @@ #define CONFIG_S5_EXIT_WAIT 4 #endif -#endif /* __CROS_EC_CONFIG_H */ +#endif /* __CROS_EC_CONFIG_H */ -- cgit v1.2.1 From cbd230492664ee6ede009a3f68d9fc07c00e8be7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:40 -0600 Subject: zephyr/emul/emul_bb_retimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iae67763355c679bbfde7ee79cf99b2fbad7f9e29 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730684 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_bb_retimer.c | 67 +++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/zephyr/emul/emul_bb_retimer.c b/zephyr/emul/emul_bb_retimer.c index 9a3e0a7b6e..8a9d8b5633 100644 --- a/zephyr/emul/emul_bb_retimer.c +++ b/zephyr/emul/emul_bb_retimer.c @@ -19,7 +19,7 @@ LOG_MODULE_REGISTER(emul_bb_retimer); #include "driver/retimer/bb_retimer.h" -#define BB_DATA_FROM_I2C_EMUL(_emul) \ +#define BB_DATA_FROM_I2C_EMUL(_emul) \ CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ struct bb_emul_data, common) @@ -90,14 +90,14 @@ void bb_emul_set_err_on_rsvd_write(struct i2c_emul *emul, bool set) /** Mask reserved bits in each register of BB retimer */ static const uint32_t bb_emul_rsvd_mask[] = { - [BB_RETIMER_REG_VENDOR_ID] = 0x00000000, - [BB_RETIMER_REG_DEVICE_ID] = 0x00000000, - [0x02] = 0xffffffff, /* Reserved */ - [0x03] = 0xffffffff, /* Reserved */ - [BB_RETIMER_REG_CONNECTION_STATE] = 0xc0201000, - [BB_RETIMER_REG_TBT_CONTROL] = 0xffffdfff, - [0x06] = 0xffffffff, /* Reserved */ - [BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x08007f00, + [BB_RETIMER_REG_VENDOR_ID] = 0x00000000, + [BB_RETIMER_REG_DEVICE_ID] = 0x00000000, + [0x02] = 0xffffffff, /* Reserved */ + [0x03] = 0xffffffff, /* Reserved */ + [BB_RETIMER_REG_CONNECTION_STATE] = 0xc0201000, + [BB_RETIMER_REG_TBT_CONTROL] = 0xffffdfff, + [0x06] = 0xffffffff, /* Reserved */ + [BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x08007f00, }; /** @@ -111,14 +111,14 @@ static void bb_emul_reset(struct i2c_emul *emul) data = BB_DATA_FROM_I2C_EMUL(emul); - data->reg[BB_RETIMER_REG_VENDOR_ID] = data->vendor_id; - data->reg[BB_RETIMER_REG_DEVICE_ID] = BB_RETIMER_DEVICE_ID; - data->reg[0x02] = 0x00; /* Reserved */ - data->reg[0x03] = 0x00; /* Reserved */ - data->reg[BB_RETIMER_REG_CONNECTION_STATE] = 0x00; - data->reg[BB_RETIMER_REG_TBT_CONTROL] = 0x00; - data->reg[0x06] = 0x00; /* Reserved */ - data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x00; + data->reg[BB_RETIMER_REG_VENDOR_ID] = data->vendor_id; + data->reg[BB_RETIMER_REG_DEVICE_ID] = BB_RETIMER_DEVICE_ID; + data->reg[0x02] = 0x00; /* Reserved */ + data->reg[0x03] = 0x00; /* Reserved */ + data->reg[BB_RETIMER_REG_CONNECTION_STATE] = 0x00; + data->reg[BB_RETIMER_REG_TBT_CONTROL] = 0x00; + data->reg[0x06] = 0x00; /* Reserved */ + data->reg[BB_RETIMER_REG_EXT_CONNECTION_MODE] = 0x00; } /** @@ -155,8 +155,7 @@ static int bb_emul_handle_write(struct i2c_emul *emul, int reg, int msg_len) LOG_WRN("Got %d bytes of WR data, expected 4", msg_len - 2); } - if (reg <= BB_RETIMER_REG_DEVICE_ID || - reg >= BB_RETIMER_REG_COUNT || + if (reg <= BB_RETIMER_REG_DEVICE_ID || reg >= BB_RETIMER_REG_COUNT || reg == BB_RETIMER_REG_TBT_CONTROL) { if (data->error_on_ro_write) { LOG_ERR("Writing to reg 0x%x which is RO", reg); @@ -298,8 +297,7 @@ static int bb_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, * * @return 0 indicating success (always) */ -static int bb_emul_init(const struct emul *emul, - const struct device *parent) +static int bb_emul_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = cfg->data; @@ -318,7 +316,7 @@ static int bb_emul_init(const struct emul *emul, return ret; } -#define BB_RETIMER_EMUL(n) \ +#define BB_RETIMER_EMUL(n) \ static struct bb_emul_data bb_emul_data_##n = { \ .vendor_id = DT_STRING_TOKEN(DT_DRV_INST(n), vendor), \ .error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\ @@ -333,27 +331,28 @@ static int bb_emul_init(const struct emul *emul, .finish_read = NULL, \ .access_reg = bb_emul_access_reg, \ }, \ - }; \ - \ - static const struct i2c_common_emul_cfg bb_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .data = &bb_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(bb_emul_init, DT_DRV_INST(n), &bb_emul_cfg_##n, \ + }; \ + \ + static const struct i2c_common_emul_cfg bb_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .data = &bb_emul_data_##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(bb_emul_init, DT_DRV_INST(n), &bb_emul_cfg_##n, \ &bb_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL) -#define BB_RETIMER_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &bb_emul_data_##n.common.emul; +#define BB_RETIMER_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &bb_emul_data_##n.common.emul; /** Check description in emul_bb_emulator.h */ struct i2c_emul *bb_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(BB_RETIMER_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From 23b923fb53ec483a55dcb5df36daaebc7961b512 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:44 -0600 Subject: board/chronicler/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ff9ecae2f6f584405b02763e24abdc5233b5477 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728125 Reviewed-by: Jeremy Bettis --- board/chronicler/usbc_config.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/chronicler/usbc_config.h b/board/chronicler/usbc_config.h index 55dfce7621..a13944250a 100644 --- a/board/chronicler/usbc_config.h +++ b/board/chronicler/usbc_config.h @@ -8,11 +8,7 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /* Configure the USB3 daughterboard type */ void config_usb3_db_type(void); -- cgit v1.2.1 From 902f29c795ad5d50f989daffadbbd36363717492 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:49 -0600 Subject: board/goroh/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I26ae5cff5824a452545c76391daf126bde0976df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728428 Reviewed-by: Jeremy Bettis --- board/goroh/board.h | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/board/goroh/board.h b/board/goroh/board.h index c5b1758aa4..70a23447a5 100644 --- a/board/goroh/board.h +++ b/board/goroh/board.h @@ -46,7 +46,7 @@ #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_STACKOVERFLOW -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 /* Sensor */ #define CONFIG_GMR_TABLET_MODE @@ -99,20 +99,16 @@ enum sensor_id { }; enum adc_channel { - ADC_BOARD_ID, /* ADC 1 */ - ADC_TEMP_SENSOR_CPU, /* ADC 2 */ - ADC_TEMP_SENSOR_GPU, /* ADC 3 */ + ADC_BOARD_ID, /* ADC 1 */ + ADC_TEMP_SENSOR_CPU, /* ADC 2 */ + ADC_TEMP_SENSOR_GPU, /* ADC 3 */ ADC_TEMP_SENSOR_CHARGER, /* ADC 5 */ /* Number of ADC channels */ ADC_CH_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; enum pwm_channel { PWM_CH_LED_GREEN, @@ -122,10 +118,7 @@ enum pwm_channel { PWM_CH_COUNT, }; -enum fan_channel { - FAN_CH_0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0, FAN_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_CPU, -- cgit v1.2.1 From c7b6f74a6543e32ae78f888dd21ef76bad723764 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 1 Jun 2022 14:57:45 +0800 Subject: anx7447: support FRS Support Fast-Role Swap function on ANX7447 driver. BUG=b:223087277 TEST=kingler FRS work BRANCH=none Change-Id: I474dd3522d755b40d61dc3683478c364f02662cc Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3682984 Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen --- driver/tcpm/anx7447.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ driver/tcpm/anx7447.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index 8bd0be36f4..8e19f6ee90 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -370,6 +370,11 @@ static int anx7447_init(int port) if (rv) return rv; + if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) + /* Unmask FRSWAP signal detect */ + tcpc_write(port, ANX7447_REG_VD_ALERT_MASK, + ANX7447_FRSWAP_SIGNAL_DETECTED); + #ifdef CONFIG_USB_PD_TCPM_MUX /* * Run mux_set() here for considering CCD(Case-Closed Debugging) case @@ -460,12 +465,55 @@ int anx7447_board_charging_enable(int port, int enable) return tcpc_write(port, TCPC_REG_COMMAND, enable ? 0x55 : 0x44); } +static void anx7447_vendor_defined_alert(int port) +{ + int alert; + + tcpc_read(port, ANX7447_REG_VD_ALERT, &alert); + + /* write to clear alerts */ + tcpc_write(port, ANX7447_REG_VD_ALERT, alert); + + if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC) && + alert & ANX7447_FRSWAP_SIGNAL_DETECTED) + pd_got_frs_signal(port); +} + static void anx7447_tcpc_alert(int port) { + int alert; + + tcpc_read16(port, TCPC_REG_ALERT, &alert); + if (alert & TCPC_REG_ALERT_VENDOR_DEF) + anx7447_vendor_defined_alert(port); + /* process and clear alert status */ tcpci_tcpc_alert(port); } +#ifdef CONFIG_USB_PD_FRS_TCPC +static int anx7447_set_frs_enable(int port, int enable) +{ + int val; + + RETURN_ERROR(tcpc_update8(port, ANX7447_REG_FRSWAP_CTRL, + ANX7447_FRSWAP_DETECT_ENABLE, + enable ? MASK_SET : MASK_CLR)); + + RETURN_ERROR( + anx7447_reg_read(port, ANX7447_REG_ADDR_GPIO_CTRL_1, &val)); + + if (enable) + val |= ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; + else + val &= ~ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; + + RETURN_ERROR( + anx7447_reg_write(port, ANX7447_REG_ADDR_GPIO_CTRL_1, val)); + return EC_SUCCESS; +} +#endif /* CONFIG_USB_PD_FRS_TCPC */ + /* * timestamp of the next possible toggle to ensure the 2-ms spacing * between IRQ_HPD. @@ -933,6 +981,9 @@ const struct tcpm_drv anx7447_tcpm_drv = { .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER .enter_low_power_mode = &tcpci_enter_low_power_mode, +#endif +#ifdef CONFIG_USB_PD_FRS_TCPC + .set_frs_enable = &anx7447_set_frs_enable, #endif .set_bist_test_mode = &anx7447_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h index 623a80b9c7..e2752142d8 100644 --- a/driver/tcpm/anx7447.h +++ b/driver/tcpm/anx7447.h @@ -42,6 +42,8 @@ #define ANX7447_REG_INTP_MASK_0 0x86 +#define ANX7447_REG_ADDR_GPIO_CTRL_1 0x89 + #define ANX7447_REG_TCPC_CTRL_1 0x9D #define CC_DEBOUNCE_MS BIT(3) #define CC_DEBOUNCE_TIME_HI_BIT BIT(0) @@ -58,6 +60,13 @@ #define ANX7447_REG_ANALOG_CTRL_10 0xAA #define ANX7447_REG_CABLE_DET_DIG 0x40 +#define ANX7447_REG_FRSWAP_CTRL 0xAB + +#define ANX7447_REG_T_CHK_VBUS_TIMER 0xBB + +#define ANX7447_REG_VD_ALERT_MASK 0xC7 +#define ANX7447_REG_VD_ALERT 0xC8 + #define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_MASK 0x38 #define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_19US 0x00 #define ANX7447_REG_R_VCONN_PWR_PRT_INRUSH_TIME_38US 0x08 @@ -72,6 +81,28 @@ #define ANX7447_REG_SAFE_MODE 0x80 #define ANX7447_REG_R_AUX_RES_PULL_SRC 0x20 +/* FRSWAP_CTRL bit definitions */ +#define ANX7447_FR_SWAP BIT(7) +#define ANX7447_FR_SWAP_EN BIT(6) +#define ANX7447_R_FRSWAP_CONTROL_SELECT BIT(3) +#define ANX7447_R_SIGNAL_FRSWAP BIT(2) +#define ANX7447_TRANSMIT_FRSWAP_SIGNAL BIT(1) +#define ANX7447_FRSWAP_DETECT_ENABLE BIT(0) + +/* ADDR_GPIO_CTRL_1 bit definitions */ +#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA BIT(3) +#define ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_OEN BIT(2) + +/* VD_ALERT and VD_ALERT_MASK bit definitions */ +#define ANX7447_TIMER_1_DONE BIT(7) +#define ANX7447_TIMER_0_DONE BIT(6) +#define ANX7447_SOFT_INTP BIT(5) +#define ANX7447_VCONN_VOLTAGE_ALARM_LO BIT(4) +#define ANX7447_VCONN_VOLTAGE_ALARM_HI BIT(3) +#define ANX7447_VCONN_OCP_OCCURRED BIT(2) +#define ANX7447_VBUS_OCP_OCCURRED BIT(1) +#define ANX7447_FRSWAP_SIGNAL_DETECTED BIT(0) + /* * This section of defines are only required to support the config option * CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND. -- cgit v1.2.1 From 8e548d618e4caf5f591d9daa1693bd578dd152bf Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Tue, 7 Jun 2022 14:02:49 +0800 Subject: anx7447: delay FRS_DATA deassertion to PPC This CL delay the dassertion of FRS_EN output to the PPC. Some PPCs need the FRS_EN pin to stay asserted until the VBUS dropped to a threshold under 5V to successfully source. However, on some hubs with a larger cap, the VBUS might take more than 10 ms. This workaround is to delay the FRS_EN deassertion to PPC for 30 ms, which should be enough for most cases. BUG=b:223087277 TEST=tested on a hub with large cap under 5V cases BRANCH=none Change-Id: I23faca31c9922762164c028b7269ca41a93bf6ca Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3692646 Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- driver/tcpm/anx7447.c | 44 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index 8e19f6ee90..ae21b6e263 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -36,6 +36,11 @@ static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state, static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT]; static struct anx_usb_mux mux[CONFIG_USB_PD_PORT_MAX_COUNT]; +#ifdef CONFIG_USB_PD_FRS_TCPC +/* an array to indicate which port is waiting for FRS disablement. */ +static bool anx_frs_dis[CONFIG_USB_PD_PORT_MAX_COUNT]; +#endif /* CONFIG_USB_PD_FRS_TCPC */ + /* * ANX7447 has two co-existence I2C addresses, TCPC address and * SPI address. The registers of TCPC address are partly compliant @@ -492,6 +497,22 @@ static void anx7447_tcpc_alert(int port) } #ifdef CONFIG_USB_PD_FRS_TCPC +static void anx7447_disable_frs_deferred(void) +{ + int i, val; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (!anx_frs_dis[i]) + continue; + + anx_frs_dis[i] = false; + anx7447_reg_read(i, ANX7447_REG_ADDR_GPIO_CTRL_1, &val); + val &= ~ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; + anx7447_reg_write(i, ANX7447_REG_ADDR_GPIO_CTRL_1, val); + } +} +DECLARE_DEFERRED(anx7447_disable_frs_deferred); + static int anx7447_set_frs_enable(int port, int enable) { int val; @@ -500,14 +521,25 @@ static int anx7447_set_frs_enable(int port, int enable) ANX7447_FRSWAP_DETECT_ENABLE, enable ? MASK_SET : MASK_CLR)); + if (!enable) { + /* + * b/223087277#comment52: delay to disable FRS output to the + * PPC. Some PPCs need the FRS_EN pin to stay asserted until the + * VBUS dropped to a threshold under 5V to successfully source. + * However, on some hubs with a larger cap, the VBUS might take + * more than 10 ms. This workaround is to delay the FRS_EN + * deassertion to PPC for 30 ms, which should be enough for + * most cases. + */ + anx_frs_dis[port] = true; + hook_call_deferred(&anx7447_disable_frs_deferred_data, + 30 * MSEC); + return EC_SUCCESS; + } + RETURN_ERROR( anx7447_reg_read(port, ANX7447_REG_ADDR_GPIO_CTRL_1, &val)); - - if (enable) - val |= ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; - else - val &= ~ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; - + val |= ANX7447_ADDR_GPIO_CTRL_1_FRS_EN_DATA; RETURN_ERROR( anx7447_reg_write(port, ANX7447_REG_ADDR_GPIO_CTRL_1, val)); return EC_SUCCESS; -- cgit v1.2.1 From b19aa3b01c47165403409b5e9fb0304361b800e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:33 -0600 Subject: zephyr/test/drivers/src/ppc_sn5s330.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20a78b5021993c1b8212f9bad51586ab5c57a844 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730958 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/ppc_sn5s330.c | 46 +++++++++++++++++------------------ 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/zephyr/test/drivers/src/ppc_sn5s330.c b/zephyr/test/drivers/src/ppc_sn5s330.c index bd38f874f7..bc81ed3c5b 100644 --- a/zephyr/test/drivers/src/ppc_sn5s330.c +++ b/zephyr/test/drivers/src/ppc_sn5s330.c @@ -194,9 +194,8 @@ ZTEST(ppc_sn5s330, test_vbus_source_sink_enable) } /* This test depends on EC GIPO initialization happening before I2C */ -BUILD_ASSERT( - CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY < CONFIG_I2C_INIT_PRIORITY, - "GPIO initialization must happen before I2C"); +BUILD_ASSERT(CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY < CONFIG_I2C_INIT_PRIORITY, + "GPIO initialization must happen before I2C"); ZTEST(ppc_sn5s330, test_vbus_discharge) { const struct emul *emul = EMUL; @@ -438,25 +437,24 @@ enum i2c_operation { I2C_READ, }; -#define INIT_I2C_FAIL_HELPER(EMUL, RW, REG) \ - do { \ - if ((RW) == I2C_READ) { \ - i2c_common_emul_set_read_fail_reg((EMUL), (REG)); \ - i2c_common_emul_set_write_fail_reg( \ - (EMUL), I2C_COMMON_EMUL_NO_FAIL_REG); \ - } else if ((RW) == I2C_WRITE) { \ - i2c_common_emul_set_read_fail_reg( \ - (EMUL), I2C_COMMON_EMUL_NO_FAIL_REG); \ - i2c_common_emul_set_write_fail_reg((EMUL), (REG)); \ - } else { \ - zassert_true(false, "Invalid I2C operation"); \ - } \ - zassert_equal( \ - EC_ERROR_INVAL, sn5s330_drv.init(SN5S330_PORT), \ - "Did not get EC_ERROR_INVAL when reg %s (0x%02x)" \ - "could not be %s", \ - #REG, (REG), \ - ((RW) == I2C_READ) ? "read" : "written"); \ +#define INIT_I2C_FAIL_HELPER(EMUL, RW, REG) \ + do { \ + if ((RW) == I2C_READ) { \ + i2c_common_emul_set_read_fail_reg((EMUL), (REG)); \ + i2c_common_emul_set_write_fail_reg( \ + (EMUL), I2C_COMMON_EMUL_NO_FAIL_REG); \ + } else if ((RW) == I2C_WRITE) { \ + i2c_common_emul_set_read_fail_reg( \ + (EMUL), I2C_COMMON_EMUL_NO_FAIL_REG); \ + i2c_common_emul_set_write_fail_reg((EMUL), (REG)); \ + } else { \ + zassert_true(false, "Invalid I2C operation"); \ + } \ + zassert_equal( \ + EC_ERROR_INVAL, sn5s330_drv.init(SN5S330_PORT), \ + "Did not get EC_ERROR_INVAL when reg %s (0x%02x)" \ + "could not be %s", \ + #REG, (REG), ((RW) == I2C_READ) ? "read" : "written"); \ } while (0) ZTEST(ppc_sn5s330, test_init_reg_fails) @@ -665,9 +663,9 @@ static inline void reset_sn5s330_state(void) i2c_common_emul_set_write_func(i2c_emul, NULL, NULL); i2c_common_emul_set_read_func(i2c_emul, NULL, NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, - I2C_COMMON_EMUL_NO_FAIL_REG); + I2C_COMMON_EMUL_NO_FAIL_REG); i2c_common_emul_set_read_fail_reg(i2c_emul, - I2C_COMMON_EMUL_NO_FAIL_REG); + I2C_COMMON_EMUL_NO_FAIL_REG); sn5s330_emul_reset(EMUL); RESET_FAKE(sn5s330_emul_interrupt_set_stub); } -- cgit v1.2.1 From 8e34bc5a72458b0a3a806de473cf7d79202da75a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:01 -0600 Subject: chip/stm32/usb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f78ce2c0315f0247158aaa39973608f54f71df1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729426 Reviewed-by: Jeremy Bettis --- chip/stm32/usb.c | 124 ++++++++++++++++++++++++++----------------------------- 1 file changed, 58 insertions(+), 66 deletions(-) diff --git a/chip/stm32/usb.c b/chip/stm32/usb.c index a1f60e8906..37f34aac13 100644 --- a/chip/stm32/usb.c +++ b/chip/stm32/usb.c @@ -21,7 +21,7 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #ifdef CONFIG_USB_BOS /* v2.10 (vs 2.00) BOS Descriptor provided */ @@ -73,11 +73,11 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = { .bConfigurationValue = 1, .iConfiguration = USB_STR_VERSION, .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 +#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ + | 0x40 #endif #ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 + | 0x20 #endif , .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), @@ -85,8 +85,7 @@ const struct usb_config_descriptor USB_CONF_DESC(conf) = { const uint8_t usb_string_desc[] = { 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ + USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */ }; #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR @@ -95,7 +94,8 @@ const uint8_t usb_string_desc[] = { * descriptor is used by Windows OS to know to request a Windows Compatible ID * OS Descriptor so that Windows will load the proper WINUSB driver. */ -const void *const usb_ms_os_string_descriptor = {USB_MS_STRING_DESC("MSFT100")}; +const void *const usb_ms_os_string_descriptor = { USB_MS_STRING_DESC( + "MSFT100") }; /* * Extended Compat ID OS Feature descriptor. This descriptor is used by Windows @@ -125,7 +125,7 @@ struct stm32_endpoint btable_ep[USB_EP_COUNT] __aligned(8) __usb_btable; static usb_uint ep0_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; static usb_uint ep0_buf_rx[USB_MAX_PACKET_SIZE / 2] __usb_ram; -#define EP0_BUF_TX_SRAM_ADDR ((void *) usb_sram_addr(ep0_buf_tx)) +#define EP0_BUF_TX_SRAM_ADDR ((void *)usb_sram_addr(ep0_buf_tx)) static int set_addr; /* remaining size of descriptor data to transfer */ @@ -142,10 +142,10 @@ static int remote_wakeup_enabled; void usb_read_setup_packet(usb_uint *buffer, struct usb_setup_packet *packet) { packet->bmRequestType = buffer[0] & 0xff; - packet->bRequest = buffer[0] >> 8; - packet->wValue = buffer[1]; - packet->wIndex = buffer[2]; - packet->wLength = buffer[3]; + packet->bRequest = buffer[0] >> 8; + packet->wValue = buffer[1]; + packet->wIndex = buffer[2]; + packet->wLength = buffer[3]; } struct usb_descriptor_patch { @@ -155,8 +155,8 @@ struct usb_descriptor_patch { static struct usb_descriptor_patch desc_patches[USB_DESC_PATCH_COUNT]; -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data) +void set_descriptor_patch(enum usb_desc_patch_type type, const void *address, + uint16_t data) { desc_patches[type].address = address; desc_patches[type].data = data; @@ -176,7 +176,8 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n) continue; memcpy_to_usbram((void *)(usb_sram_addr(ep0_buf_tx) + offset), - &desc_patches[i].data, sizeof(desc_patches[i].data)); + &desc_patches[i].data, + sizeof(desc_patches[i].data)); } return ret; @@ -246,7 +247,7 @@ static void ep0_rx(void) #ifdef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR if (b_req == USB_MS_STRING_DESC_VENDOR_CODE && - w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) { + w_index == USB_MS_EXT_COMPATIBLE_ID_INDEX) { ep0_send_descriptor((uint8_t *)&winusb_desc, winusb_desc.dwLength, 0); return; @@ -310,8 +311,9 @@ static void ep0_rx(void) default: /* unhandled descriptor */ goto unknown_req; } - ep0_send_descriptor(desc, len, type == USB_DT_CONFIGURATION ? - USB_DESC_SIZE : 0); + ep0_send_descriptor( + desc, len, + type == USB_DT_CONFIGURATION ? USB_DESC_SIZE : 0); } else if (req == (USB_DIR_IN | (USB_REQ_GET_STATUS << 8))) { uint16_t data = 0; /* Get status */ @@ -325,14 +327,14 @@ static void ep0_rx(void) memcpy_to_usbram(EP0_BUF_TX_SRAM_ADDR, (void *)&data, 2); btable_ep[0].tx_count = 2; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, - EP_STATUS_OUT /*null OUT transaction */); + EP_STATUS_OUT /*null OUT transaction */); } else if ((req & 0xff) == USB_DIR_OUT) { switch (req >> 8) { case USB_REQ_SET_FEATURE: case USB_REQ_CLEAR_FEATURE: #ifdef CONFIG_USB_REMOTE_WAKEUP if (ep0_buf_rx[1] == - USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { + USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP) { remote_wakeup_enabled = ((req >> 8) == USB_REQ_SET_FEATURE); btable_ep[0].tx_count = 0; @@ -407,13 +409,12 @@ static void ep0_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - STM32_USB_EP(0) = BIT(9) /* control EP */ | - (2 << 4) /* TX NAK */ | + STM32_USB_EP(0) = BIT(9) /* control EP */ | (2 << 4) /* TX NAK */ | (3 << 12) /* RX VALID */; btable_ep[0].tx_addr = usb_sram_addr(ep0_buf_tx); btable_ep[0].rx_addr = usb_sram_addr(ep0_buf_rx); - btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE/32-1) << 10); + btable_ep[0].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); btable_ep[0].tx_count = 0; } USB_DECLARE_EP(0, ep0_tx, ep0_rx, ep0_event); @@ -473,8 +474,8 @@ static volatile int sof_received; static void usb_resume_deferred(void) { - uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + uint32_t state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; CPRINTF("RSMd %d %04x %d\n", state, STM32_USB_CNTR, sof_received); if (sof_received == 0 && (state == 2 || state == 3)) @@ -496,8 +497,8 @@ static void usb_resume(void) /* USB is in use again */ disable_sleep(SLEEP_MASK_USB_DEVICE); - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; CPRINTF("RSM %d %04x\n", state, STM32_USB_CNTR); @@ -534,8 +535,7 @@ static volatile int usb_wake_done = 1; */ static volatile int esof_count; -__attribute__((weak)) -void board_usb_wake(void) +__attribute__((weak)) void board_usb_wake(void) { /* Side-band USB wake, do nothing by default. */ } @@ -598,8 +598,8 @@ void usb_wake(void) /* STM32_USB_CNTR can also be updated from interrupt context. */ interrupt_disable(); - STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | - STM32_USB_CNTR_ESOFM | STM32_USB_CNTR_SOFM; + STM32_USB_CNTR |= STM32_USB_CNTR_RESUME | STM32_USB_CNTR_ESOFM | + STM32_USB_CNTR_SOFM; interrupt_enable(); /* Try side-band wake as well. */ @@ -654,8 +654,8 @@ static void usb_interrupt_handle_wake(uint16_t status) STM32_USB_CNTR &= ~STM32_USB_CNTR_RESUME; /* Then count down until state is resumed. */ - state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) - >> STM32_USB_FNR_RXDP_RXDM_SHIFT; + state = (STM32_USB_FNR & STM32_USB_FNR_RXDP_RXDM_MASK) >> + STM32_USB_FNR_RXDP_RXDM_SHIFT; /* * state 2, or receiving an SOF, means resume @@ -670,13 +670,13 @@ static void usb_interrupt_handle_wake(uint16_t status) STM32_USB_CNTR &= ~STM32_USB_CNTR_ESOFM; usb_wake_done = 1; if (!good) { - CPRINTF("wake error: cnt=%d state=%d\n", - esof_count, state); + CPRINTF("wake error: cnt=%d state=%d\n", esof_count, + state); usb_suspend(); return; } - CPRINTF("RSMOK%d %d\n", -esof_count, state); + CPRINTF("RSMOK%d %d\n", -esof_count, state); for (ep = 1; ep < USB_EP_COUNT; ep++) usb_ep_event[ep](USB_EVENT_DEVICE_RESUME); @@ -703,7 +703,7 @@ static void usb_interrupt(void) #ifdef CONFIG_USB_REMOTE_WAKEUP if (status & (STM32_USB_ISTR_ESOF | STM32_USB_ISTR_SOF) && - !usb_wake_done) + !usb_wake_done) usb_interrupt_handle_wake(status); #endif @@ -759,12 +759,10 @@ void usb_init(void) /* Enable interrupt handlers */ task_enable_irq(STM32_IRQ_USB_LP); /* set interrupts mask : reset/correct transfer/errors */ - STM32_USB_CNTR = STM32_USB_CNTR_CTRM | - STM32_USB_CNTR_PMAOVRM | + STM32_USB_CNTR = STM32_USB_CNTR_CTRM | STM32_USB_CNTR_PMAOVRM | STM32_USB_CNTR_ERRM | #ifdef CONFIG_USB_SUSPEND - STM32_USB_CNTR_WKUPM | - STM32_USB_CNTR_SUSPM | + STM32_USB_CNTR_WKUPM | STM32_USB_CNTR_SUSPM | #endif STM32_USB_CNTR_RESETM; @@ -809,10 +807,10 @@ int usb_is_enabled(void) void *memcpy_to_usbram(void *dest, const void *src, size_t n) { - int unaligned = (((uintptr_t) dest) & 1); - usb_uint *d = &__usb_ram_start[((uintptr_t) dest) / 2]; - uint8_t *s = (uint8_t *) src; - int i; + int unaligned = (((uintptr_t)dest) & 1); + usb_uint *d = &__usb_ram_start[((uintptr_t)dest) / 2]; + uint8_t *s = (uint8_t *)src; + int i; /* * Handle unaligned leading byte via read/modify/write. @@ -839,10 +837,10 @@ void *memcpy_to_usbram(void *dest, const void *src, size_t n) void *memcpy_from_usbram(void *dest, const void *src, size_t n) { - int unaligned = (((uintptr_t) src) & 1); - usb_uint const *s = &__usb_ram_start[((uintptr_t) src) / 2]; - uint8_t *d = (uint8_t *) dest; - int i; + int unaligned = (((uintptr_t)src) & 1); + usb_uint const *s = &__usb_ram_start[((uintptr_t)src) / 2]; + uint8_t *d = (uint8_t *)dest; + int i; if (unaligned && n) { *d = *s >> 8; @@ -931,12 +929,10 @@ static int command_serialno(int argc, char **argv) int i; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving serial number\n"); rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading serial number\n"); rv = usb_load_serial(); } else @@ -949,11 +945,10 @@ static int command_serialno(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); +DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]", + "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ +#endif /* CONFIG_USB_SERIALNO */ #ifdef CONFIG_MAC_ADDR @@ -982,16 +977,14 @@ static int usb_save_mac_addr(const char *mac_addr) static int command_macaddr(int argc, char **argv) { - const char* buf; + const char *buf; int rv = EC_SUCCESS; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving MAC address\n"); rv = usb_save_mac_addr(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading MAC address\n"); } else { return EC_ERROR_INVAL; @@ -1006,8 +999,7 @@ static int command_macaddr(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, - "load/set [value]", - "Read and write MAC address"); +DECLARE_CONSOLE_COMMAND(macaddr, command_macaddr, "load/set [value]", + "Read and write MAC address"); -#endif /* CONFIG_MAC_ADDR */ +#endif /* CONFIG_MAC_ADDR */ -- cgit v1.2.1 From 9c04f8b61d4c2499a701a1ef5807a2cc1c2e0145 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:44 -0600 Subject: board/bellis/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f5383d1164e024725dfad572dd99a97a2262067 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728052 Reviewed-by: Jeremy Bettis --- board/bellis/led.c | 53 +++++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/board/bellis/led.c b/board/bellis/led.c index a6a926a958..24725c4274 100644 --- a/board/bellis/led.c +++ b/board/bellis/led.c @@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor -led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From e72a546f9ac04f633c75b063b7cea49c17acb71b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:33 -0600 Subject: chip/npcx/hwtimer_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19b0b446cb633d8275b5362562cd801e94e5d2ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729399 Reviewed-by: Jeremy Bettis --- chip/npcx/hwtimer_chip.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h index 987f3b52bd..379d999973 100644 --- a/chip/npcx/hwtimer_chip.h +++ b/chip/npcx/hwtimer_chip.h @@ -9,14 +9,14 @@ #define __CROS_EC_HWTIMER_CHIP_H /* Use ITIM32 as main hardware timer */ -#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF +#define TICK_ITIM32_MAX_CNT 0xFFFFFFFF /* Maximum deadline of event */ -#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT +#define EVT_MAX_EXPIRED_US TICK_ITIM32_MAX_CNT /* Clock source for ITIM16 */ enum ITIM_SOURCE_CLOCK_T { ITIM_SOURCE_CLOCK_APB2 = 0, - ITIM_SOURCE_CLOCK_32K = 1, + ITIM_SOURCE_CLOCK_32K = 1, }; /** -- cgit v1.2.1 From b1b06014fe5fb12935852d33a94e78f3312bc0fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:37 -0600 Subject: driver/temp_sensor/tmp432.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id47344d28f473961550fa1c551ae8a07342dd6e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729883 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp432.c | 50 +++++++++++++++++++-------------------------- 1 file changed, 21 insertions(+), 29 deletions(-) diff --git a/driver/temp_sensor/tmp432.c b/driver/temp_sensor/tmp432.c index 8db6a99e19..b05e986ade 100644 --- a/driver/temp_sensor/tmp432.c +++ b/driver/temp_sensor/tmp432.c @@ -19,7 +19,7 @@ static int temp_val_remote2; #ifndef CONFIG_TEMP_SENSOR_POWER static uint8_t is_sensor_shutdown; #endif -static int fake_temp[TMP432_IDX_COUNT] = {-1, -1, -1}; +static int fake_temp[TMP432_IDX_COUNT] = { -1, -1, -1 }; /** * Determine whether the sensor is powered. @@ -37,14 +37,14 @@ static int has_power(void) static int raw_read8(const int offset, int *data_ptr) { - return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset, + data_ptr); } static int raw_write8(const int offset, int data) { - return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, - offset, data); + return i2c_write8(I2C_PORT_THERMAL, TMP432_I2C_ADDR_FLAGS, offset, + data); } static int get_temp(const int offset, int *temp_ptr) @@ -150,7 +150,7 @@ int tmp432_set_therm_limit(int channel, int limit_c, int hysteresis) return EC_ERROR_INVAL; if (hysteresis > TMP432_HYSTERESIS_HIGH_LIMIT || - hysteresis < TMP432_HYSTERESIS_LOW_LIMIT) + hysteresis < TMP432_HYSTERESIS_LOW_LIMIT) return EC_ERROR_INVAL; /* hysteresis must be less than high limit */ @@ -228,12 +228,10 @@ static int tmp432_set_fake_temp(int index, int degree_c) return EC_SUCCESS; } -static void print_temps( - const char *name, - const int tmp432_temp_reg, - const int tmp432_therm_limit_reg, - const int tmp432_high_limit_reg, - const int tmp432_low_limit_reg) +static void print_temps(const char *name, const int tmp432_temp_reg, + const int tmp432_therm_limit_reg, + const int tmp432_high_limit_reg, + const int tmp432_low_limit_reg) { int value; @@ -261,20 +259,14 @@ static int print_status(void) { int value, i; - print_temps("Local", TMP432_LOCAL, - TMP432_LOCAL_THERM_LIMIT, - TMP432_LOCAL_HIGH_LIMIT_R, - TMP432_LOCAL_LOW_LIMIT_R); + print_temps("Local", TMP432_LOCAL, TMP432_LOCAL_THERM_LIMIT, + TMP432_LOCAL_HIGH_LIMIT_R, TMP432_LOCAL_LOW_LIMIT_R); - print_temps("Remote1", TMP432_REMOTE1, - TMP432_REMOTE1_THERM_LIMIT, - TMP432_REMOTE1_HIGH_LIMIT_R, - TMP432_REMOTE1_LOW_LIMIT_R); + print_temps("Remote1", TMP432_REMOTE1, TMP432_REMOTE1_THERM_LIMIT, + TMP432_REMOTE1_HIGH_LIMIT_R, TMP432_REMOTE1_LOW_LIMIT_R); - print_temps("Remote2", TMP432_REMOTE2, - TMP432_REMOTE2_THERM_LIMIT, - TMP432_REMOTE2_HIGH_LIMIT_R, - TMP432_REMOTE2_LOW_LIMIT_R); + print_temps("Remote2", TMP432_REMOTE2, TMP432_REMOTE2_THERM_LIMIT, + TMP432_REMOTE2_HIGH_LIMIT_R, TMP432_REMOTE2_LOW_LIMIT_R); ccprintf("\n"); @@ -321,8 +313,7 @@ static int command_tmp432(int argc, char **argv) rv = tmp432_set_power(TMP432_POWER_ON); if (!rv) print_status(); - } - else if (!strncasecmp(power, "off", sizeof("off"))) + } else if (!strncasecmp(power, "off", sizeof("off"))) rv = tmp432_set_power(TMP432_POWER_OFF); else return EC_ERROR_PARAM2; @@ -351,8 +342,8 @@ static int command_tmp432(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", - offset, BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is %pb\n", offset, + BINARY_VALUE(data, 8)); return rv; } @@ -379,7 +370,8 @@ static int command_tmp432(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(tmp432, command_tmp432, +DECLARE_CONSOLE_COMMAND( + tmp432, command_tmp432, "[settemp|setbyte ] or [getbyte ] or" "[fake ] or [power ]. " "Temps in Celsius.", -- cgit v1.2.1 From 029982ec8fc82fbe4fa1d7fa6273d61e714506be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:35 -0600 Subject: test/stillness_detector.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f01bc7a954c89b4fd19da2feb69f1ede7a6eb0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730523 Reviewed-by: Jeremy Bettis --- test/stillness_detector.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/test/stillness_detector.c b/test/stillness_detector.c index 57057e217e..ce28c76eb1 100644 --- a/test/stillness_detector.c +++ b/test/stillness_detector.c @@ -35,8 +35,8 @@ static int test_not_still_short_window(void) int i; for (i = 0; i < 6; ++i) - TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, - 0.0f, 0.0f, 0.0f)); + TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, 0.0f, 0.0f, + 0.0f)); return EC_SUCCESS; } @@ -47,8 +47,8 @@ static int test_not_still_long_window(void) int i; for (i = 0; i < 5; ++i) - TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC, - 0.0f, 0.0f, 0.0f)); + TEST_ASSERT(!still_det_update(&det, i * 300 * MSEC, 0.0f, 0.0f, + 0.0f)); return EC_SUCCESS; } @@ -59,8 +59,8 @@ static int test_not_still_not_enough_samples(void) int i; for (i = 0; i < 4; ++i) - TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC, - 0.0f, 0.0f, 0.0f)); + TEST_ASSERT(!still_det_update(&det, i * 200 * MSEC, 0.0f, 0.0f, + 0.0f)); return EC_SUCCESS; } @@ -71,9 +71,8 @@ static int test_is_still_all_axes(void) int i; for (i = 0; i < 9; ++i) { - int result = still_det_update(&det, i * 100 * MSEC, - i * 0.001f, i * 0.001f, - i * 0.001f); + int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f, + i * 0.001f, i * 0.001f); TEST_EQ(result, i == 8 ? 1 : 0, "%d"); } @@ -90,9 +89,8 @@ static int test_not_still_one_axis(void) int i; for (i = 0; i < 9; ++i) { - TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, - i * 0.001f, i * 0.001f, - i * 0.01f)); + TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f, + i * 0.001f, i * 0.01f)); } return EC_SUCCESS; @@ -104,15 +102,13 @@ static int test_resets(void) int i; for (i = 0; i < 9; ++i) { - TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, - i * 0.001f, i * 0.001f, - i * 0.01f)); + TEST_ASSERT(!still_det_update(&det, i * 100 * MSEC, i * 0.001f, + i * 0.001f, i * 0.01f)); } for (i = 0; i < 9; ++i) { - int result = still_det_update(&det, i * 100 * MSEC, - i * 0.001f, i * 0.001f, - i * 0.001f); + int result = still_det_update(&det, i * 100 * MSEC, i * 0.001f, + i * 0.001f, i * 0.001f); TEST_EQ(result, i == 8 ? 1 : 0, "%d"); } -- cgit v1.2.1 From ef0da78dd65d981adb3871165a765d2d2ee20f29 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:59 -0600 Subject: board/cerise/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7352dd2119bec52115b02803b34ffe6b8587371c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728142 Reviewed-by: Jeremy Bettis --- board/cerise/led.c | 43 +++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/board/cerise/led.c b/board/cerise/led.c index 53bec5bf05..cbde98e94a 100644 --- a/board/cerise/led.c +++ b/board/cerise/led.c @@ -19,25 +19,32 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From 6ea0ecfc75f84879b0bfabc271b13d81cdcfa36d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:43 -0600 Subject: common/ioexpander.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee0ebda0a5387d804dc95a8e24cf84f170837b16 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729639 Reviewed-by: Jeremy Bettis --- common/ioexpander.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/common/ioexpander.c b/common/ioexpander.c index 2bed1039f4..f81f996c6b 100644 --- a/common/ioexpander.c +++ b/common/ioexpander.c @@ -11,8 +11,8 @@ #include "system.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) int signal_is_ioex(int signal) { @@ -68,7 +68,7 @@ int ioex_enable_interrupt(enum ioex_signal signal) rv = ioex_is_valid_interrupt_signal(signal); if (rv != EC_SUCCESS) - return rv; + return rv; drv = ioex_config[g->ioex].drv; return drv->enable_interrupt(g->ioex, g->port, g->mask, 1); @@ -82,7 +82,7 @@ int ioex_disable_interrupt(enum ioex_signal signal) rv = ioex_is_valid_interrupt_signal(signal); if (rv != EC_SUCCESS) - return rv; + return rv; drv = ioex_config[g->ioex].drv; return drv->enable_interrupt(g->ioex, g->port, g->mask, 0); @@ -107,8 +107,8 @@ int ioex_get_flags(enum ioex_signal signal, int *flags) if (g == NULL) return EC_ERROR_BUSY; - return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex, - g->port, g->mask, flags); + return ioex_config[g->ioex].drv->get_flags_by_mask(g->ioex, g->port, + g->mask, flags); } int ioex_set_flags(enum ioex_signal signal, int flags) @@ -118,8 +118,8 @@ int ioex_set_flags(enum ioex_signal signal, int flags) if (g == NULL) return EC_ERROR_BUSY; - return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex, - g->port, g->mask, flags); + return ioex_config[g->ioex].drv->set_flags_by_mask(g->ioex, g->port, + g->mask, flags); } int ioex_get_level(enum ioex_signal signal, int *val) @@ -129,8 +129,8 @@ int ioex_get_level(enum ioex_signal signal, int *val) if (g == NULL) return EC_ERROR_BUSY; - return ioex_config[g->ioex].drv->get_level(g->ioex, g->port, - g->mask, val); + return ioex_config[g->ioex].drv->get_level(g->ioex, g->port, g->mask, + val); } int ioex_set_level(enum ioex_signal signal, int value) @@ -140,8 +140,8 @@ int ioex_set_level(enum ioex_signal signal, int value) if (g == NULL) return EC_ERROR_BUSY; - return ioex_config[g->ioex].drv->set_level(g->ioex, g->port, - g->mask, value); + return ioex_config[g->ioex].drv->set_level(g->ioex, g->port, g->mask, + value); } #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT @@ -198,7 +198,7 @@ int ioex_restore_gpio_state(int ioex, const int *state, int state_len) } rv = drv->set_flags_by_mask(g->ioex, g->port, g->mask, - state[state_offset++]); + state[state_offset++]); if (rv) { CPRINTS("%s failed to set flags rv=%d", __func__, rv); return rv; @@ -233,8 +233,8 @@ int ioex_init(int ioex) if (system_jumped_late()) flags &= ~(GPIO_LOW | GPIO_HIGH); - drv->set_flags_by_mask(g->ioex, g->port, - g->mask, flags); + drv->set_flags_by_mask(g->ioex, g->port, g->mask, + flags); } } @@ -253,8 +253,8 @@ static void ioex_init_default(void) * If the IO Expander has been initialized or if the default * initialization is disabled, skip initializing. */ - if (ioex_config[i].flags & (IOEX_FLAGS_INITIALIZED | - IOEX_FLAGS_DEFAULT_INIT_DISABLED)) + if (ioex_config[i].flags & + (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED)) continue; ioex_init(i); -- cgit v1.2.1 From a66a0660625af621ef706e759b2f3b3b3be4b690 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:12 -0600 Subject: chip/it83xx/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f6d3e75a46c96e08b7607bdf31be3259df9c850 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729199 Reviewed-by: Jeremy Bettis --- chip/it83xx/i2c.c | 164 ++++++++++++++++++++++++++---------------------------- 1 file changed, 78 insertions(+), 86 deletions(-) diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c index 836ee7a82f..7dc41a7eb4 100644 --- a/chip/it83xx/i2c.c +++ b/chip/it83xx/i2c.c @@ -16,7 +16,7 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* Default maximum time we allow for an I2C transfer */ #define I2C_TIMEOUT_DEFAULT_US (100 * MSEC) @@ -28,13 +28,13 @@ #endif /* It is allowed to configure the size up to 2K bytes. */ -#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128 +#define I2C_CQ_MODE_MAX_PAYLOAD_SIZE 128 /* reserved 5 bytes for ID and CMD_x */ -#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5) +#define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5) uint8_t i2c_cq_mode_tx_dlm[I2C_ENHANCED_PORT_COUNT] - [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); + [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT] - [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); + [I2C_CQ_MODE_MAX_PAYLOAD_SIZE] __aligned(4); /* Repeat Start */ #define I2C_CQ_CMD_L_RS BIT(7) @@ -44,9 +44,9 @@ uint8_t i2c_cq_mode_rx_dlm[I2C_ENHANCED_PORT_COUNT] */ #define I2C_CQ_CMD_L_RW BIT(6) /* P (STOP) is the I2C STOP condition */ -#define I2C_CQ_CMD_L_P BIT(5) +#define I2C_CQ_CMD_L_P BIT(5) /* E (End) is this device end flag */ -#define I2C_CQ_CMD_L_E BIT(4) +#define I2C_CQ_CMD_L_E BIT(4) /* LA (Last ACK) is Last ACK in master receiver */ #define I2C_CQ_CMD_L_LA BIT(3) /* bit[2:0] are number of transfer out or receive data which depends on R/W. */ @@ -86,8 +86,8 @@ enum i2c_host_status { /* Byte done status */ HOSTA_BDS = 0x80, /* Error bit is set */ - HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | - HOSTA_FAIL | HOSTA_NACK | HOSTA_TMOE), + HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL | HOSTA_NACK | + HOSTA_TMOE), /* W/C for next byte */ HOSTA_NEXT_BYTE = HOSTA_BDS, /* W/C host status register */ @@ -155,10 +155,10 @@ struct i2c_ch_freq { }; static const struct i2c_ch_freq i2c_freq_select[] = { - { 50, 1}, - { 100, 2}, - { 400, 3}, - { 1000, 4}, + { 50, 1 }, + { 100, 2 }, + { 400, 3 }, + { 1000, 4 }, }; struct i2c_pin { @@ -173,37 +173,30 @@ struct i2c_pin { }; static const struct i2c_pin i2c_pin_regs[] = { - { &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4, - &IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDRB, - &IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB, - 0x08, 0x10}, - { &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2, - &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRC, - &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC, - 0x02, 0x04}, + { &IT83XX_GPIO_GPCRB3, &IT83XX_GPIO_GPCRB4, &IT83XX_GPIO_GPDRB, + &IT83XX_GPIO_GPDRB, &IT83XX_GPIO_GPDMRB, &IT83XX_GPIO_GPDMRB, 0x08, + 0x10 }, + { &IT83XX_GPIO_GPCRC1, &IT83XX_GPIO_GPCRC2, &IT83XX_GPIO_GPDRC, + &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRC, 0x02, + 0x04 }, #ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7 - { &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7, - &IT83XX_GPIO_GPDRC, &IT83XX_GPIO_GPDRF, - &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF, - 0x80, 0x80}, + { &IT83XX_GPIO_GPCRC7, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRC, + &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRC, &IT83XX_GPIO_GPDMRF, 0x80, + 0x80 }, #else - { &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7, - &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDRF, - &IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF, - 0x40, 0x80}, + { &IT83XX_GPIO_GPCRF6, &IT83XX_GPIO_GPCRF7, &IT83XX_GPIO_GPDRF, + &IT83XX_GPIO_GPDRF, &IT83XX_GPIO_GPDMRF, &IT83XX_GPIO_GPDMRF, 0x40, + 0x80 }, #endif - { &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, - &IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDRH, - &IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH, - 0x02, 0x04}, - { &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7, - &IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDRE, - &IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE, - 0x01, 0x80}, - { &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5, - &IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDRA, - &IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA, - 0x10, 0x20}, + { &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, &IT83XX_GPIO_GPDRH, + &IT83XX_GPIO_GPDRH, &IT83XX_GPIO_GPDMRH, &IT83XX_GPIO_GPDMRH, 0x02, + 0x04 }, + { &IT83XX_GPIO_GPCRE0, &IT83XX_GPIO_GPCRE7, &IT83XX_GPIO_GPDRE, + &IT83XX_GPIO_GPDRE, &IT83XX_GPIO_GPDMRE, &IT83XX_GPIO_GPDMRE, 0x01, + 0x80 }, + { &IT83XX_GPIO_GPCRA4, &IT83XX_GPIO_GPCRA5, &IT83XX_GPIO_GPDRA, + &IT83XX_GPIO_GPDRA, &IT83XX_GPIO_GPDMRA, &IT83XX_GPIO_GPDMRA, 0x10, + 0x20 }, }; struct i2c_ctrl_t { @@ -213,12 +206,12 @@ struct i2c_ctrl_t { }; const struct i2c_ctrl_t i2c_ctrl_regs[] = { - {IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1}, - {IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1}, - {IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1}, - {IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3}, - {IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0}, - {IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1}, + { IT83XX_IRQ_SMB_A, CGC_OFFSET_SMBA, -1 }, + { IT83XX_IRQ_SMB_B, CGC_OFFSET_SMBB, -1 }, + { IT83XX_IRQ_SMB_C, CGC_OFFSET_SMBC, -1 }, + { IT83XX_IRQ_SMB_D, CGC_OFFSET_SMBD, 3 }, + { IT83XX_IRQ_SMB_E, CGC_OFFSET_SMBE, 0 }, + { IT83XX_IRQ_SMB_F, CGC_OFFSET_SMBF, 1 }, }; enum i2c_ch_status { @@ -230,17 +223,17 @@ enum i2c_ch_status { /* I2C port state data */ struct i2c_port_data { - const uint8_t *out; /* Output data pointer */ - int out_size; /* Output data to transfer, in bytes */ - uint8_t *in; /* Input data pointer */ - int in_size; /* Input data to transfer, in bytes */ - int flags; /* Flags (I2C_XFER_*) */ - int widx; /* Index into output data */ - int ridx; /* Index into input data */ - int err; /* Error code, if any */ - uint8_t addr_8bit; /* address of device */ + const uint8_t *out; /* Output data pointer */ + int out_size; /* Output data to transfer, in bytes */ + uint8_t *in; /* Input data pointer */ + int in_size; /* Input data to transfer, in bytes */ + int flags; /* Flags (I2C_XFER_*) */ + int widx; /* Index into output data */ + int ridx; /* Index into input data */ + int err; /* Error code, if any */ + uint8_t addr_8bit; /* address of device */ uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - uint8_t freq; /* Frequency setting */ + uint8_t freq; /* Frequency setting */ enum i2c_ch_status i2ccs; /* Task waiting on port, or TASK_ID_INVALID if none. */ @@ -329,8 +322,8 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct, if (first_byte) { /* First byte must be peripheral address. */ - IT83XX_I2C_DTR(p_ch) = - data | (direct == RX_DIRECT ? BIT(0) : 0); + IT83XX_I2C_DTR(p_ch) = data | + (direct == RX_DIRECT ? BIT(0) : 0); /* start or repeat start signal. */ IT83XX_I2C_CTR(p_ch) = E_START_ID; } else { @@ -343,12 +336,12 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct, * Last byte should be NACK in the end of read cycle */ if (((pd->ridx + 1) == pd->in_size) && - (pd->flags & I2C_XFER_STOP)) + (pd->flags & I2C_XFER_STOP)) nack = 1; } /* Set hardware reset to start next transmission */ - IT83XX_I2C_CTR(p_ch) = - E_INT_EN | E_MODE_SEL | E_HW_RST | (nack ? 0 : E_ACK); + IT83XX_I2C_CTR(p_ch) = E_INT_EN | E_MODE_SEL | E_HW_RST | + (nack ? 0 : E_ACK); } } @@ -439,7 +432,7 @@ static int i2c_tran_read(int p) IT83XX_SMB_HOCTL(p) = 0x5D; } else { if ((pd->i2ccs == I2C_CH_REPEAT_START) || - (pd->i2ccs == I2C_CH_WAIT_READ)) { + (pd->i2ccs == I2C_CH_WAIT_READ)) { if (pd->i2ccs == I2C_CH_REPEAT_START) { /* write to read */ i2c_w2r_change_direction(p); @@ -532,8 +525,8 @@ static int enhanced_i2c_tran_write(int p) /* Write to read protocol */ pd->i2ccs = I2C_CH_REPEAT_START; /* Repeat Start */ - i2c_pio_trans_data(p, RX_DIRECT, - pd->addr_8bit, 1); + i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit, + 1); } else { if (pd->flags & I2C_XFER_STOP) { IT83XX_I2C_CTR(p_ch) = E_FINISH; @@ -582,8 +575,8 @@ static int enhanced_i2c_tran_read(int p) /* Write to read */ pd->i2ccs = I2C_CH_WAIT_READ; /* Send ID */ - i2c_pio_trans_data(p, RX_DIRECT, - pd->addr_8bit, 1); + i2c_pio_trans_data(p, RX_DIRECT, pd->addr_8bit, + 1); task_enable_irq(i2c_ctrl_regs[p].irq); } } else { @@ -622,7 +615,7 @@ static int enhanced_i2c_error(int p) if (i2c_str & E_HOSTA_ANY_ERROR) { pd->err = i2c_str & E_HOSTA_ANY_ERROR; - /* device does not respond ACK */ + /* device does not respond ACK */ } else if ((i2c_str & E_HOSTA_BDS_AND_ACK) == E_HOSTA_BDS) { if (IT83XX_I2C_CTR(p_ch) & E_ACK) pd->err = E_HOSTA_ACK; @@ -672,8 +665,8 @@ static int command_i2c_idle_mask(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask, - NULL, "Display i2c idle mask"); +DECLARE_SAFE_CONSOLE_COMMAND(i2cidlemask, command_i2c_idle_mask, NULL, + "Display i2c idle mask"); static void enhanced_i2c_cq_write(int p) { @@ -703,8 +696,8 @@ static void enhanced_i2c_cq_read(int p) i2c_cq_pckt = (struct i2c_cq_packet *)&i2c_cq_mode_tx_dlm[dlm_index]; /* Set commands in RAM. */ i2c_cq_pckt->id = pd->addr_8bit; - i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | - I2C_CQ_CMD_L_E | num_bit_2_0; + i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | + num_bit_2_0; i2c_cq_pckt->cmd_h = num_bit_10_3; } @@ -728,7 +721,7 @@ static void enhanced_i2c_cq_write_to_read(int p) num_bit_2_0 = (pd->in_size - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; num_bit_10_3 = ((pd->in_size - 1) >> 3) & 0xff; i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW | - I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0; + I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0; i2c_cq_pckt->wdata[i] = num_bit_10_3; } @@ -751,7 +744,7 @@ static int enhanced_i2c_cmd_queue_trans(int p) pd->err = E_HOSTA_ACK; else pd->err = IT83XX_I2C_STR(p_ch) & - E_HOSTA_ANY_ERROR; + E_HOSTA_ANY_ERROR; } /* reset bus */ IT83XX_I2C_CTR(p_ch) = E_STS_AND_HW_RST; @@ -761,7 +754,7 @@ static int enhanced_i2c_cmd_queue_trans(int p) } if ((pd->out_size > I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE) || - (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) { + (pd->in_size > I2C_CQ_MODE_MAX_PAYLOAD_SIZE)) { pd->err = EC_ERROR_INVAL; return 0; } @@ -868,9 +861,8 @@ int i2c_is_busy(int port) return (IT83XX_I2C_STR(p_ch) & E_HOSTA_BB); } -int chip_i2c_xfer(int port, uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { struct i2c_port_data *pd = pdata + port; uint32_t events = 0; @@ -900,9 +892,9 @@ int chip_i2c_xfer(int port, uint16_t addr_flags, pd->addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; /* Make sure we're in a good state to start */ - if ((flags & I2C_XFER_START) && (i2c_is_busy(port) - || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { - + if ((flags & I2C_XFER_START) && + (i2c_is_busy(port) || + (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { /* Attempt to unwedge the port. */ pd->err = i2c_unwedge(port); @@ -953,7 +945,7 @@ int i2c_raw_get_scl(int port) if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) return !!(*i2c_pin_regs[port].mirror_clk & - i2c_pin_regs[port].clk_mask); + i2c_pin_regs[port].clk_mask); /* If no SCL pin defined for this port, then return 1 to appear idle */ return 1; @@ -965,7 +957,7 @@ int i2c_raw_get_sda(int port) if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) return !!(*i2c_pin_regs[port].mirror_data & - i2c_pin_regs[port].data_mask); + i2c_pin_regs[port].data_mask); /* If no SDA pin defined for this port, then return 1 to appear idle */ return 1; @@ -1041,7 +1033,7 @@ static void i2c_standard_port_set_frequency(int port, int freq_khz) for (int f = ARRAY_SIZE(i2c_freq_select) - 1; f >= 0; f--) { if (freq_khz >= i2c_freq_select[f].kbps) { IT83XX_SMB_SCLKTS(port) = - i2c_freq_select[f].freq_set; + i2c_freq_select[f].freq_set; break; } } @@ -1143,10 +1135,10 @@ void i2c_init(void) p_ch = i2c_ch_reg_shift(p); switch (p) { case IT83XX_I2C_CH_D: - #ifndef CONFIG_UART_HOST +#ifndef CONFIG_UART_HOST /* Enable SMBus D channel */ IT83XX_GPIO_GRC2 |= 0x20; - #endif +#endif break; case IT83XX_I2C_CH_E: /* Enable SMBus E channel */ -- cgit v1.2.1 From fcfb2c1d51bd65a8bad710d1d71a26933f5ba845 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:22 -0600 Subject: board/bobba/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I21a4bcbf1b7d607b2d73ca8fff0ec2b8b9fc6d39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728061 Reviewed-by: Jeremy Bettis --- board/bobba/board.h | 35 ++++++++++++----------------------- 1 file changed, 12 insertions(+), 23 deletions(-) diff --git a/board/bobba/board.h b/board/bobba/board.h index a1fc900084..e63a26b002 100644 --- a/board/bobba/board.h +++ b/board/bobba/board.h @@ -16,7 +16,7 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* I2C bus configuraiton */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* EC console commands */ #define CONFIG_CMD_ACCEL_INFO @@ -40,10 +40,10 @@ #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2 /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel main source*/ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ -#define CONFIG_SYNC /* Camera VSYNC */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel main source*/ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_SYNC /* Camera VSYNC */ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Sensors without hardware FIFO are in forced mode */ @@ -55,9 +55,7 @@ #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) - -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -97,10 +95,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -111,19 +109,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - VSYNC, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 49a47c5cabc4fb23961fa8494ab2d450b51ae728 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:25 -0600 Subject: board/servo_v4/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I297cc1bf39ed3954ee0410a84d517d917e5b87dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728906 Reviewed-by: Jeremy Bettis --- board/servo_v4/usb_pd_config.h | 51 +++++++++++++++++++++++++----------------- 1 file changed, 30 insertions(+), 21 deletions(-) diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h index af9d84922c..4b42bd6c29 100644 --- a/board/servo_v4/usb_pd_config.h +++ b/board/servo_v4/usb_pd_config.h @@ -56,22 +56,22 @@ #define CONFIG_HW_CRC /* Servo v4 CC configuration */ -#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ -#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ -#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ -#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ -#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ -#define CC_POLARITY BIT(5) /* CC polarity */ +#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ +#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ +#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ +#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ +#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ +#define CC_POLARITY BIT(5) /* CC polarity */ /* Servo v4 DP alt-mode configuration */ -#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ -#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ -#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ -#define ALT_DP_PIN_E BIT(3) /* Pin assignment E supported */ -#define ALT_DP_MF_PREF BIT(4) /* Multi-Function preferred */ -#define ALT_DP_PLUG BIT(5) /* Plug or receptacle */ -#define ALT_DP_OVERRIDE_HPD BIT(6) /* Override the HPD signal */ -#define ALT_DP_HPD_LVL BIT(7) /* HPD level if overridden */ +#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ +#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ +#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ +#define ALT_DP_PIN_E BIT(3) /* Pin assignment E supported */ +#define ALT_DP_MF_PREF BIT(4) /* Multi-Function preferred */ +#define ALT_DP_PLUG BIT(5) /* Plug or receptacle */ +#define ALT_DP_OVERRIDE_HPD BIT(6) /* Override the HPD signal */ +#define ALT_DP_HPD_LVL BIT(7) /* HPD level if overridden */ /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */ #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) @@ -94,14 +94,14 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG) #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG) -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 /* * EXTI line 21 is connected to the CMP1 output, * EXTI line 22 is connected to the CMP2 output, * CHG uses CMP2, and DUT uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22)) +#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -193,13 +193,23 @@ static inline void pd_select_polarity(int port, int polarity) if (port == 0) { /* CHG use the right comparator inverted input for COMP2 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | - (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ - : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ + (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: + C0_CC2 + */ + : + STM32_COMP_CMP2INSEL_INM6); /* PA2: + C0_CC1 + */ } else { /* DUT use the right comparator inverted input for COMP1 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ - : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ + (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: + C1_CC2 + */ + : + STM32_COMP_CMP1INSEL_INM6); /* PA0: + C1_CC1 + */ } } @@ -279,7 +289,6 @@ static inline void pd_config_init(int port, uint8_t power_role) /* Initialize TX pins and put them in Hi-Z */ pd_tx_init(); - } int pd_adc_read(int port, int cc); -- cgit v1.2.1 From 4459ee23d7664053e953b14c3b718dee8bbab3c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:45 -0600 Subject: common/ioexpander_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0cb8d07641de75f3e2abb4626bf131b4864e9262 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729657 Reviewed-by: Jeremy Bettis --- common/ioexpander_commands.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/common/ioexpander_commands.c b/common/ioexpander_commands.c index a09337ea88..13d7ba0690 100644 --- a/common/ioexpander_commands.c +++ b/common/ioexpander_commands.c @@ -69,14 +69,13 @@ static void print_ioex_info(enum ioex_signal signal) changed = last_val_changed(signal, val); - ccprintf(" %d%c %s%s%s%s%s%s\n", val, - (changed ? '*' : ' '), + ccprintf(" %d%c %s%s%s%s%s%s\n", val, (changed ? '*' : ' '), (flags & GPIO_INPUT ? "I " : ""), (flags & GPIO_OUTPUT ? "O " : ""), (flags & GPIO_LOW ? "L " : ""), (flags & GPIO_HIGH ? "H " : ""), (flags & GPIO_OPEN_DRAIN ? "ODR " : ""), - ioex_get_name(signal)); + ioex_get_name(signal)); /* Flush console to avoid truncating output */ cflush(); @@ -116,8 +115,7 @@ static int command_ioex_set(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set, - "name <0 | 1>", +DECLARE_CONSOLE_COMMAND(ioexset, command_ioex_set, "name <0 | 1>", "Set level of a IO expander pin"); static int command_ioex_get(int argc, char **argv) @@ -140,6 +138,5 @@ static int command_ioex_get(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get, - "[name]", +DECLARE_SAFE_CONSOLE_COMMAND(ioexget, command_ioex_get, "[name]", "Read level of IO expander pin(s)"); -- cgit v1.2.1 From b2bcb414e2078828f1160a2146d25fdb485cad0e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:34 -0600 Subject: board/kingoftown/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia7a35d1a262c845c70ecb57c7e98e645c2d769b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728548 Reviewed-by: Jeremy Bettis --- board/kingoftown/board.c | 125 ++++++++++++++++++----------------------------- 1 file changed, 47 insertions(+), 78 deletions(-) diff --git a/board/kingoftown/board.c b/board/kingoftown/board.c index e3d91575e1..54e0e495a5 100644 --- a/board/kingoftown/board.c +++ b/board/kingoftown/board.c @@ -26,8 +26,8 @@ #include "usbc_config.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -39,10 +39,8 @@ __override struct keyboard_scan_config keyscan_config = { * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key); * as it still uses the legacy location (KSO_01/KSI_00). */ - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -57,52 +55,42 @@ __override struct keyboard_scan_config keyscan_config = { * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -110,37 +98,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -192,17 +165,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 1e75702d05042ae7f0e3109334195d61de82353f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:55 -0600 Subject: test/powerdemo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iab6cf319cdf1a3d2fbd5ee696735fa154893db06 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730530 Reviewed-by: Jeremy Bettis --- test/powerdemo.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/test/powerdemo.c b/test/powerdemo.c index e695bb8e5e..a3aa052e8f 100644 --- a/test/powerdemo.c +++ b/test/powerdemo.c @@ -13,17 +13,16 @@ #include "registers.h" static volatile enum { - POWER_STATE_IDLE = 0, /* Idle */ - POWER_STATE_DOWN1, /* Assert output for 1ms */ - POWER_STATE_UP1, /* Deassert output for 1ms */ - POWER_STATE_DOWN10, /* Assert output for 10ms */ - POWER_STATE_UP5, /* Deassert output for 5ms */ - POWER_STATE_DOWN15, /* Assert output for 15ms */ - POWER_STATE_WAIT, /* Wait for button to be released */ - POWER_STATE_DOWN2 /* Assert output for 2ms */ + POWER_STATE_IDLE = 0, /* Idle */ + POWER_STATE_DOWN1, /* Assert output for 1ms */ + POWER_STATE_UP1, /* Deassert output for 1ms */ + POWER_STATE_DOWN10, /* Assert output for 10ms */ + POWER_STATE_UP5, /* Deassert output for 5ms */ + POWER_STATE_DOWN15, /* Assert output for 15ms */ + POWER_STATE_WAIT, /* Wait for button to be released */ + POWER_STATE_DOWN2 /* Assert output for 2ms */ } state = POWER_STATE_IDLE; - /* Stops the timer. */ static void __stop_timer(void) { @@ -33,7 +32,6 @@ static void __stop_timer(void) LM4_TIMER_ICR(7) = LM4_TIMER_RIS(7); } - /* Starts the timer with the specified delay. If the timer is already * started, resets it. */ static void __start_timer(int usec) @@ -46,7 +44,6 @@ static void __start_timer(int usec) LM4_TIMER_CTL(7) |= 0x01; } - static void __set_state(int new_state, int pin_value, int timeout) { LM4_GPIO_DATA(LM4_GPIO_D, 0x08) = (pin_value ? 0x08 : 0); @@ -57,7 +54,6 @@ static void __set_state(int new_state, int pin_value, int timeout) state = new_state; } - int power_demo_init(void) { volatile uint32_t scratch __attribute__((unused)); @@ -102,7 +98,6 @@ int power_demo_init(void) return EC_SUCCESS; } - /* GPIO interrupt handler */ static void __gpio_d_interrupt(void) { @@ -125,7 +120,6 @@ static void __gpio_d_interrupt(void) DECLARE_IRQ(LM4_IRQ_GPIOD, __gpio_d_interrupt, 1); - /* Timer interrupt handler */ static void __timer_w1_interrupt(void) { -- cgit v1.2.1 From 63ce8d752ead55a5b50f62d743d99af9abddf8d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:06 -0600 Subject: zephyr/projects/herobrine/src/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0732a58901cd234c753c5fd826f5daf0e0c3e79a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730770 Reviewed-by: Jeremy Bettis --- zephyr/projects/herobrine/src/usb_pd_policy.c | 37 ++++++++++++--------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/zephyr/projects/herobrine/src/usb_pd_policy.c b/zephyr/projects/herobrine/src/usb_pd_policy.c index a2e353d7d4..23eeb7034d 100644 --- a/zephyr/projects/herobrine/src/usb_pd_policy.c +++ b/zephyr/projects/herobrine/src/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -94,11 +94,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -176,8 +176,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -189,13 +188,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -222,8 +219,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv IRQ. HPD->1", port); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; @@ -231,8 +228,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl); gpio_pin_set_dt(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -248,10 +245,10 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); CPRINTS("C%d: DP exit. HPD->0", port); - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r), 0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det_r), + 0); } } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ -- cgit v1.2.1 From 7d6712a673ef874bf9acade456f99cb5a2cba0b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:23 -0600 Subject: test/motion_angle.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I77d8dc7f45a7608e2a242c6924c162430429fc1c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730512 Reviewed-by: Jeremy Bettis --- test/motion_angle.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/test/motion_angle.c b/test/motion_angle.c index 30f663de14..06a896fbdd 100644 --- a/test/motion_angle.c +++ b/test/motion_angle.c @@ -32,10 +32,10 @@ int filler(const struct motion_sensor_t *s, const float v) static int test_lid_angle_less180(void) { int index = 0, lid_angle; - struct motion_sensor_t *lid = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_LID]; - struct motion_sensor_t *base = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_BASE]; + struct motion_sensor_t *lid = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID]; + struct motion_sensor_t *base = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE]; /* We don't have TASK_CHIP so simulate init ourselves */ hook_notify(HOOK_CHIPSET_SHUTDOWN); @@ -56,41 +56,38 @@ static int test_lid_angle_less180(void) cprints(CC_ACCEL, "start loop"); /* Check we will never enter tablet mode. */ while (index < kAccelerometerLaptopModeTestDataLength) { - feed_accel_data(kAccelerometerLaptopModeTestData, - &index, filler); + feed_accel_data(kAccelerometerLaptopModeTestData, &index, + filler); wait_for_valid_sample(); lid_angle = motion_lid_get_angle(); cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d", - index / TEST_LID_SAMPLE_SIZE, - lid->xyz[X], lid->xyz[Y], lid->xyz[Z], - base->xyz[X], base->xyz[Y], base->xyz[Z], - lid_angle); + index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y], + lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z], + lid_angle); /* We need few sample to debounce and enter laptop mode. */ TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE * - (TABLET_MODE_DEBOUNCE_COUNT + 2) || + (TABLET_MODE_DEBOUNCE_COUNT + 2) || !tablet_get_mode()); } /* Check we will never exit tablet mode. */ index = 0; while (index < kAccelerometerFullyOpenTestDataLength) { - feed_accel_data(kAccelerometerFullyOpenTestData, - &index, filler); + feed_accel_data(kAccelerometerFullyOpenTestData, &index, + filler); wait_for_valid_sample(); lid_angle = motion_lid_get_angle(); cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d", - index / TEST_LID_SAMPLE_SIZE, - lid->xyz[X], lid->xyz[Y], lid->xyz[Z], - base->xyz[X], base->xyz[Y], base->xyz[Z], - lid_angle); + index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y], + lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z], + lid_angle); TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE * - (TABLET_MODE_DEBOUNCE_COUNT + 2) || + (TABLET_MODE_DEBOUNCE_COUNT + 2) || tablet_get_mode()); } return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 1024b67b80c572a7328fc57987da9f4dc5216672 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:19 -0600 Subject: chip/npcx/apm_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4283396dc19fd89be19e10be01de121a89685986 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729374 Reviewed-by: Jeremy Bettis --- chip/npcx/apm_chip.h | 53 +++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/chip/npcx/apm_chip.h b/chip/npcx/apm_chip.h index ad62538374..6de3a330b7 100644 --- a/chip/npcx/apm_chip.h +++ b/chip/npcx/apm_chip.h @@ -9,31 +9,27 @@ #include "common.h" /* MIX indirect registers. */ -#define APM_INDIRECT_MIX_2_REG 0x02 +#define APM_INDIRECT_MIX_2_REG 0x02 /* ADC_AGC indirect registers. */ -#define APM_INDIRECT_ADC_AGC_0_REG 0x00 -#define APM_INDIRECT_ADC_AGC_1_REG 0x01 -#define APM_INDIRECT_ADC_AGC_2_REG 0x02 -#define APM_INDIRECT_ADC_AGC_3_REG 0x03 -#define APM_INDIRECT_ADC_AGC_4_REG 0x04 +#define APM_INDIRECT_ADC_AGC_0_REG 0x00 +#define APM_INDIRECT_ADC_AGC_1_REG 0x01 +#define APM_INDIRECT_ADC_AGC_2_REG 0x02 +#define APM_INDIRECT_ADC_AGC_3_REG 0x03 +#define APM_INDIRECT_ADC_AGC_4_REG 0x04 /* APM_VAD_REG indirect registers. */ -#define APM_INDIRECT_VAD_0_REG 0x00 -#define APM_INDIRECT_VAD_1_REG 0x01 +#define APM_INDIRECT_VAD_0_REG 0x00 +#define APM_INDIRECT_VAD_1_REG 0x01 /* APM macros. */ -#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND) +#define APM_IS_IRQ_PENDING IS_BIT_SET(NPCX_APM_SR, NPCX_APM_SR_IRQ_PEND) #define APM_IS_VOICE_ACTIVITY_DETECTED \ IS_BIT_SET(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) -#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) +#define APM_CLEAR_VAD_INTERRUPT SET_BIT(NPCX_APM_IFR, NPCX_APM_IFR_VAD_DTC) /* Indirect registers. */ -enum apm_indirect_reg_offset { - APM_MIX_REG = 0, - APM_ADC_AGC_REG, - APM_VAD_REG -}; +enum apm_indirect_reg_offset { APM_MIX_REG = 0, APM_ADC_AGC_REG, APM_VAD_REG }; /* ADC wind noise filter modes. */ enum apm_adc_wind_noise_filter_mode { @@ -60,22 +56,22 @@ enum apm_adc_frequency { /* DMIC source. */ enum apm_dmic_src { APM_CURRENT_DMIC_CHANNEL = 0x01, /* Current channel, left or rigth. */ - APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right. */ + APM_AVERAGE_DMIC_CHANNEL = 0x02 /* Average between left & right. */ }; /* ADC digital microphone rate. */ enum apm_dmic_rate { /* 3.0, 2.4 & 1.0 must be 0, 1 & 2 respectively */ - APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */ - APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz. */ - APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz. */ - APM_DMIC_RATE_1_2, /* 1.2 MHz. */ - APM_DMIC_RATE_0_75 /* 750 KHz. */ + APM_DMIC_RATE_3_0 = 0, /* 3.0 -3.25 MHz (default). */ + APM_DMIC_RATE_2_4, /* 2.4 -2.6 MHz. */ + APM_DMIC_RATE_1_0, /* 1.0 -1.08 MHz. */ + APM_DMIC_RATE_1_2, /* 1.2 MHz. */ + APM_DMIC_RATE_0_75 /* 750 KHz. */ }; /* Digitla mixer output. */ enum apm_dig_mix { - APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */ + APM_OUT_MIX_NORMAL_INPUT = 0, /* Default. */ APM_OUT_MIX_CROSS_INPUT, APM_OUT_MIX_MIXED_INPUT, APM_OUT_MIX_NO_INPUT @@ -341,8 +337,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq); * @return None */ void apm_adc_config(int hpf_enable, - enum apm_adc_wind_noise_filter_mode filter_mode, - enum apm_adc_frequency adc_freq); + enum apm_adc_wind_noise_filter_mode filter_mode, + enum apm_adc_frequency adc_freq); /** * Enables/Disables Digital Microphone. @@ -360,7 +356,7 @@ void apm_dmic_enable(int enable); * @return None */ void apm_digital_mixer_config(enum apm_dig_mix mix_left, - enum apm_dig_mix mix_right); + enum apm_dig_mix mix_right); /** * Enables/Disables the VAD functionality. @@ -422,7 +418,8 @@ void apm_vad_restart(void); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling, - uint8_t left_chan_gain, uint8_t right_chan_gain); + uint8_t left_chan_gain, + uint8_t right_chan_gain); /** * Enables/Disables the automatic gain. @@ -438,8 +435,8 @@ void apm_auto_gain_cntrl_enable(int enable); * @param gain_cfg - struct of apm auto gain config * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list apm_adc_auto_gain_config( - struct apm_auto_gain_config *gain_cfg); +enum ec_error_list +apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg); /** * Sets APM mode (enables & disables APN sub modules accordingly -- cgit v1.2.1 From 61a1c226054cbf74488b329a8a237b95fb550752 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:31 -0600 Subject: zephyr/test/drivers/src/power_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie770871de678973d37bc375c39608461f93c5685 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730992 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/power_common.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/zephyr/test/drivers/src/power_common.c b/zephyr/test/drivers/src/power_common.c index 03832b6c0c..2d61ecf333 100644 --- a/zephyr/test/drivers/src/power_common.c +++ b/zephyr/test/drivers/src/power_common.c @@ -500,7 +500,7 @@ ZTEST(power_common_hibernation, test_power_hc_hibernation_delay) zassert_ok(shell_execute_cmd(get_ec_shell(), "lidclose"), NULL); zassert_equal(power_get_state(), POWER_G3, - "Power state is %d, expected G3", power_get_state()); + "Power state is %d, expected G3", power_get_state()); /* This is a no-op, but it will reset the last_shutdown_time. */ power_set_state(POWER_G3); @@ -612,28 +612,23 @@ ZTEST(power_common_hibernation, test_power_cmd_hibernation_delay) int sleep_time; zassert_equal(power_get_state(), POWER_G3, - "Power state is %d, expected G3", power_get_state()); + "Power state is %d, expected G3", power_get_state()); /* This is a no-op, but it will reset the last_shutdown_time. */ power_set_state(POWER_G3); /* Test success on call without argument */ - zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "hibdelay"), + zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "hibdelay"), NULL); /* Test error on hibernation delay argument that is not a number */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "hibdelay test1"), + shell_execute_cmd(get_ec_shell(), "hibdelay test1"), NULL); /* Set hibernate delay */ h_delay = 3; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "hibdelay 3"), - NULL); + shell_execute_cmd(get_ec_shell(), "hibdelay 3"), NULL); /* Kick chipset task to process new hibernation delay */ task_wake(TASK_ID_CHIPSET); -- cgit v1.2.1 From 7b9b87e0f3663958869c220694e8f3b0b817c555 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:46 -0600 Subject: driver/temp_sensor/tmp468.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44ce2aa8158aa538625ca1ad0a6b7d959c6a9092 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729886 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp468.h | 135 ++++++++++++++++++++++---------------------- 1 file changed, 67 insertions(+), 68 deletions(-) diff --git a/driver/temp_sensor/tmp468.h b/driver/temp_sensor/tmp468.h index 59fbd20477..fd8a271ec3 100644 --- a/driver/temp_sensor/tmp468.h +++ b/driver/temp_sensor/tmp468.h @@ -11,73 +11,73 @@ #define TMP468_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN) #define TMP468_SHIFT1 7 -#define TMP468_LOCAL 0x00 -#define TMP468_REMOTE1 0x01 -#define TMP468_REMOTE2 0x02 -#define TMP468_REMOTE3 0x03 -#define TMP468_REMOTE4 0x04 -#define TMP468_REMOTE5 0x05 -#define TMP468_REMOTE6 0x06 -#define TMP468_REMOTE7 0x07 -#define TMP468_REMOTE8 0x08 - -#define TMP468_SRST 0x20 -#define TMP468_THERM 0x21 -#define TMP468_THERM2 0x22 -#define TMP468_ROPEN 0x23 - -#define TMP468_CONFIGURATION 0x30 -#define TMP468_THERM_HYST 0x38 - -#define TMP468_LOCAL_LOW_LIMIT 0x39 -#define TMP468_LOCAL_HIGH_LIMT 0x3a - -#define TMP468_REMOTE1_OFFSET 0x40 -#define TMP468_REMOTE1_NFACTOR 0x41 -#define TMP468_REMOTE1_LOW_LIMIT 0x41 -#define TMP468_REMOTE1_HIGH_LIMIT 0x42 - -#define TMP468_REMOTE2_OFFSET 0x48 -#define TMP468_REMOTE2_NFACTOR 0x49 -#define TMP468_REMOTE2_LOW_LIMIT 0x4a -#define TMP468_REMOTE2_HIGH_LIMIT 0x4b - -#define TMP468_REMOTE3_OFFSET 0x50 -#define TMP468_REMOTE3_NFACTOR 0x51 -#define TMP468_REMOTE3_LOW_LIMIT 0x52 -#define TMP468_REMOTE3_HIGH_LIMIT 0x53 - -#define TMP468_REMOTE4_OFFSET 0x58 -#define TMP468_REMOTE4_NFACTOR 0x59 -#define TMP468_REMOTE4_LOW_LIMIT 0x59 -#define TMP468_REMOTE4_HIGH_LIMIT 0x5a - -#define TMP468_REMOTE5_OFFSET 0x60 -#define TMP468_REMOTE5_NFACTOR 0x61 -#define TMP468_REMOTE5_LOW_LIMIT 0x62 -#define TMP468_REMOTE5_HIGH_LIMIT 0x63 - -#define TMP468_REMOTE6_OFFSET 0x68 -#define TMP468_REMOTE6_NFACTOR 0x69 -#define TMP468_REMOTE6_LOW_LIMIT 0x6a -#define TMP468_REMOTE6_HIGH_LIMIT 0x6b - -#define TMP468_REMOTE7_OFFSET 0x70 -#define TMP468_REMOTE7_NFACTOR 0x71 -#define TMP468_REMOTE7_LOW_LIMIT 0x72 -#define TMP468_REMOTE7_HIGH_LIMIT 0x73 - -#define TMP468_REMOTE8_OFFSET 0x78 -#define TMP468_REMOTE8_NFACTOR 0x79 -#define TMP468_REMOTE8_LOW_LIMIT 0x7a -#define TMP468_REMOTE8_HIGH_LIMIT 0x7b - -#define TMP468_LOCK 0xc4 - -#define TMP468_DEVICE_ID 0xfd -#define TMP468_MANUFACTURER_ID 0xfe - -#define TMP468_SHUTDOWN BIT(5) +#define TMP468_LOCAL 0x00 +#define TMP468_REMOTE1 0x01 +#define TMP468_REMOTE2 0x02 +#define TMP468_REMOTE3 0x03 +#define TMP468_REMOTE4 0x04 +#define TMP468_REMOTE5 0x05 +#define TMP468_REMOTE6 0x06 +#define TMP468_REMOTE7 0x07 +#define TMP468_REMOTE8 0x08 + +#define TMP468_SRST 0x20 +#define TMP468_THERM 0x21 +#define TMP468_THERM2 0x22 +#define TMP468_ROPEN 0x23 + +#define TMP468_CONFIGURATION 0x30 +#define TMP468_THERM_HYST 0x38 + +#define TMP468_LOCAL_LOW_LIMIT 0x39 +#define TMP468_LOCAL_HIGH_LIMT 0x3a + +#define TMP468_REMOTE1_OFFSET 0x40 +#define TMP468_REMOTE1_NFACTOR 0x41 +#define TMP468_REMOTE1_LOW_LIMIT 0x41 +#define TMP468_REMOTE1_HIGH_LIMIT 0x42 + +#define TMP468_REMOTE2_OFFSET 0x48 +#define TMP468_REMOTE2_NFACTOR 0x49 +#define TMP468_REMOTE2_LOW_LIMIT 0x4a +#define TMP468_REMOTE2_HIGH_LIMIT 0x4b + +#define TMP468_REMOTE3_OFFSET 0x50 +#define TMP468_REMOTE3_NFACTOR 0x51 +#define TMP468_REMOTE3_LOW_LIMIT 0x52 +#define TMP468_REMOTE3_HIGH_LIMIT 0x53 + +#define TMP468_REMOTE4_OFFSET 0x58 +#define TMP468_REMOTE4_NFACTOR 0x59 +#define TMP468_REMOTE4_LOW_LIMIT 0x59 +#define TMP468_REMOTE4_HIGH_LIMIT 0x5a + +#define TMP468_REMOTE5_OFFSET 0x60 +#define TMP468_REMOTE5_NFACTOR 0x61 +#define TMP468_REMOTE5_LOW_LIMIT 0x62 +#define TMP468_REMOTE5_HIGH_LIMIT 0x63 + +#define TMP468_REMOTE6_OFFSET 0x68 +#define TMP468_REMOTE6_NFACTOR 0x69 +#define TMP468_REMOTE6_LOW_LIMIT 0x6a +#define TMP468_REMOTE6_HIGH_LIMIT 0x6b + +#define TMP468_REMOTE7_OFFSET 0x70 +#define TMP468_REMOTE7_NFACTOR 0x71 +#define TMP468_REMOTE7_LOW_LIMIT 0x72 +#define TMP468_REMOTE7_HIGH_LIMIT 0x73 + +#define TMP468_REMOTE8_OFFSET 0x78 +#define TMP468_REMOTE8_NFACTOR 0x79 +#define TMP468_REMOTE8_LOW_LIMIT 0x7a +#define TMP468_REMOTE8_HIGH_LIMIT 0x7b + +#define TMP468_LOCK 0xc4 + +#define TMP468_DEVICE_ID 0xfd +#define TMP468_MANUFACTURER_ID 0xfe + +#define TMP468_SHUTDOWN BIT(5) enum tmp468_channel_id { TMP468_CHANNEL_LOCAL, @@ -101,7 +101,6 @@ enum tmp468_power_state { TMP468_POWER_COUNT }; - /** * Get the last polled value of a sensor. * -- cgit v1.2.1 From fdae0464ce93fc1b9badc118ad7ae55ec37de48e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:21 -0600 Subject: board/gimble/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8b83555bf894369cf00dfdfd4a393556d52a87f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728417 Reviewed-by: Jeremy Bettis --- board/gimble/sensors.c | 79 ++++++++++++++++++++------------------------------ 1 file changed, 32 insertions(+), 47 deletions(-) diff --git a/board/gimble/sensors.c b/board/gimble/sensors.c index f39b9f2de2..7701056808 100644 --- a/board/gimble/sensors.c +++ b/board/gimble/sensors.c @@ -69,30 +69,22 @@ static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; static struct accelgyro_saved_data_t g_bma422_data; /* TODO(b/192477578): calibrate the orientation matrix on later board stage */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref_id_1 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TODO(b/192477578): calibrate the orientation matrix on later board stage */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref_id_1 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref_id_1 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -287,24 +279,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_FAN] = { - .name = "Fan", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_FAN - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_FAN] = { .name = "Fan", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_FAN }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -318,8 +304,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -346,8 +332,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -359,8 +345,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; __maybe_unused static const struct ec_thermal_config thermal_inductor = THERMAL_INDUCTOR; -#define THERMAL_FAN_MISSING \ - { \ +#define THERMAL_FAN_MISSING \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -388,9 +374,8 @@ static void config_thermal_params(void) { int rv, val; - rv = tcpc_addr_read16_no_lpm_exit(USBC_PORT_C1, - PS8XXX_I2C_ADDR1_FLAGS, TCPC_REG_VENDOR_ID, - &val); + rv = tcpc_addr_read16_no_lpm_exit(USBC_PORT_C1, PS8XXX_I2C_ADDR1_FLAGS, + TCPC_REG_VENDOR_ID, &val); if (rv != 0) { thermal_params[TEMP_SENSOR_2_FAN] = -- cgit v1.2.1 From 802f09031a16d88e178fdda11e275c60174310dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:06 -0600 Subject: test/kb_scan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If203b74abb7ce19e8645fe5746ff59ac2f39cc52 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730510 Reviewed-by: Jeremy Bettis --- test/kb_scan.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/test/kb_scan.c b/test/kb_scan.c index a43808c0c1..b36f868b8e 100644 --- a/test/kb_scan.c +++ b/test/kb_scan.c @@ -20,15 +20,15 @@ #include "timer.h" #include "util.h" -#define KEYDOWN_DELAY_MS 10 -#define KEYDOWN_RETRY 10 -#define NO_KEYDOWN_DELAY_MS 100 +#define KEYDOWN_DELAY_MS 10 +#define KEYDOWN_RETRY 10 +#define NO_KEYDOWN_DELAY_MS 100 -#define CHECK_KEY_COUNT(old, expected) \ - do { \ +#define CHECK_KEY_COUNT(old, expected) \ + do { \ if (verify_key_presses(old, expected) != EC_SUCCESS) \ - return EC_ERROR_UNKNOWN; \ - old = fifo_add_count; \ + return EC_ERROR_UNKNOWN; \ + old = fifo_add_count; \ } while (0) /* Emulated physical key state */ @@ -121,13 +121,10 @@ void chipset_reset(void) } #endif -#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_ ## k, \ - KEYBOARD_COL_ ## k, \ - p) +#define mock_defined_key(k, p) mock_key(KEYBOARD_ROW_##k, KEYBOARD_COL_##k, p) -#define mock_default_key(k, p) mock_key(KEYBOARD_DEFAULT_ROW_ ## k, \ - KEYBOARD_DEFAULT_COL_ ## k, \ - p) +#define mock_default_key(k, p) \ + mock_key(KEYBOARD_DEFAULT_ROW_##k, KEYBOARD_DEFAULT_COL_##k, p) static void mock_key(int r, int c, int keydown) { @@ -403,7 +400,7 @@ static int debounce_test(void) * Push down each subsequent key, until all 8 are pressed, each * time bouncing the former one once. */ - for (i = 1 ; i < 8; i++) { + for (i = 1; i < 8; i++) { mock_key(i, 1, 1); task_wake(TASK_ID_KEYSCAN); msleep(3); @@ -587,7 +584,7 @@ static void run_test_step1(void) else RUN_TEST(debounce_test); - if (0) /* crbug.com/976974 */ + if (0) /* crbug.com/976974 */ RUN_TEST(simulate_key_test); #ifdef EMU_BUILD RUN_TEST(runtime_key_test); -- cgit v1.2.1 From 375484eccfada0ed81d066aa2f47e805955a814e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:17 -0600 Subject: util/ectool_keyscan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If57628ee4f7d2ecbd6ce65815baea370e82ffddc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730620 Reviewed-by: Jeremy Bettis --- util/ectool_keyscan.c | 114 ++++++++++++++++++++++++++------------------------ 1 file changed, 59 insertions(+), 55 deletions(-) diff --git a/util/ectool_keyscan.c b/util/ectool_keyscan.c index 4f5393157d..4975493615 100644 --- a/util/ectool_keyscan.c +++ b/util/ectool_keyscan.c @@ -18,39 +18,39 @@ enum { /* Alloc this many more scans when needed */ - KEYSCAN_ALLOC_STEP = 64, - KEYSCAN_MAX_TESTS = 10, /* Maximum number of tests supported */ - KEYSCAN_MAX_INPUT_LEN = 20, /* Maximum characters we can receive */ + KEYSCAN_ALLOC_STEP = 64, + KEYSCAN_MAX_TESTS = 10, /* Maximum number of tests supported */ + KEYSCAN_MAX_INPUT_LEN = 20, /* Maximum characters we can receive */ }; /* A single entry of the key matrix */ struct matrix_entry { - int row; /* key matrix row */ - int col; /* key matrix column */ - int keycode; /* corresponding linux key code */ + int row; /* key matrix row */ + int col; /* key matrix column */ + int keycode; /* corresponding linux key code */ }; struct keyscan_test_item { - uint32_t beat; /* Beat number */ - uint8_t scan[KEYBOARD_COLS_MAX]; /* Scan data */ + uint32_t beat; /* Beat number */ + uint8_t scan[KEYBOARD_COLS_MAX]; /* Scan data */ }; /* A single test, consisting of a list of key scans and expected ascii input */ struct keyscan_test { - char *name; /* name of test */ - char *expect; /* resulting input we expect to see */ - int item_count; /* number of items in data */ - int item_alloced; /* number of items alloced in data */ - struct keyscan_test_item *items; /* key data for EC */ + char *name; /* name of test */ + char *expect; /* resulting input we expect to see */ + int item_count; /* number of items in data */ + int item_alloced; /* number of items alloced in data */ + struct keyscan_test_item *items; /* key data for EC */ }; /* A list of tests that we can run */ struct keyscan_info { - unsigned int beat_us; /* length of each beat in microseconds */ - struct keyscan_test tests[KEYSCAN_MAX_TESTS]; /* the tests */ - int test_count; /* number of tests */ - struct matrix_entry *matrix; /* the key matrix info */ - int matrix_count; /* number of keys in matrix */ + unsigned int beat_us; /* length of each beat in microseconds */ + struct keyscan_test tests[KEYSCAN_MAX_TESTS]; /* the tests */ + int test_count; /* number of tests */ + struct matrix_entry *matrix; /* the key matrix info */ + int matrix_count; /* number of keys in matrix */ }; /** @@ -125,18 +125,18 @@ static int keyscan_read_fdt_matrix(struct keyscan_info *keyscan, * when we see a space in a key sequence file. */ static const unsigned char kbd_plain_xlate[] = { - 0xff, 0x1b, '1', '2', '3', '4', '5', '6', - '7', '8', '9', '0', '-', '=', '\b', '\t', /* 0x00 - 0x0f */ - 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', - 'o', 'p', '[', ']', '\r', 0xff, 'a', 's', /* 0x10 - 0x1f */ - 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', - '\'', '`', 0xff, '\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ - 'b', 'n', 'm', ',' , '.', '/', 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', - '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ - '2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */ + 0xff, 0x1b, '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\b', '\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', + 'o', 'p', '[', ']', '\r', 0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', + '\'', '`', 0xff, '\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',', '.', '/', 0xff, 0xff, + 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 - 0x3f */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '7', + '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.', 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x50 - 0x5F */ '\r', 0xff, 0xff, '\0' }; @@ -216,7 +216,7 @@ static int keyscan_add_to_scan(struct keyscan_info *keyscan, char **keysp, /* Look up keycode in matrix */ for (i = 0, matrix = keyscan->matrix; i < keyscan->matrix_count; - i++, matrix++) { + i++, matrix++) { if (matrix->keycode == keycode) { #ifdef DEBUG printf("%d: %d,%d\n", matrix->keycode, matrix->row, @@ -289,15 +289,15 @@ static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum, keys++; while (*keys) { if (keyscan_add_to_scan(keyscan, &keys, item->scan)) { - fprintf(stderr, "Line %d: Cannot parse" - " key input '%s'\n", linenum, - keys); + fprintf(stderr, + "Line %d: Cannot parse" + " key input '%s'\n", + linenum, keys); return -1; } } } else if (*keys) { - fprintf(stderr, "Line %d: Need space after beat\n", - linenum); + fprintf(stderr, "Line %d: Need space after beat\n", linenum); return -1; } test->item_count++; @@ -307,10 +307,10 @@ static int keyscan_process_keys(struct keyscan_info *keyscan, int linenum, /* These are the commands we understand in a key sequence file */ enum keyscan_cmd { - KEYSCAN_CMD_TEST, /* start a new test */ - KEYSCAN_CMD_ENDTEST, /* end a test */ - KEYSCAN_CMD_SEQ, /* add a keyscan to a test sequence */ - KEYSCAN_CMD_EXPECT, /* indicate what input is expected */ + KEYSCAN_CMD_TEST, /* start a new test */ + KEYSCAN_CMD_ENDTEST, /* end a test */ + KEYSCAN_CMD_SEQ, /* add a keyscan to a test sequence */ + KEYSCAN_CMD_EXPECT, /* indicate what input is expected */ KEYSCAN_CMD_COUNT }; @@ -388,7 +388,7 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan) /* Start a new test */ if (keyscan->test_count == KEYSCAN_MAX_TESTS) { fprintf(stderr, "KEYSCAN_MAX_TESTS " - "exceeded\n"); + "exceeded\n"); return -1; } cur_test = &keyscan->tests[keyscan->test_count]; @@ -401,8 +401,10 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan) case KEYSCAN_CMD_EXPECT: /* Get expect string */ if (!cur_test) { - fprintf(stderr, "Line %d: expect should be " - "inside test\n", linenum); + fprintf(stderr, + "Line %d: expect should be " + "inside test\n", + linenum); return -1; } cur_test->expect = strdup(args); @@ -418,9 +420,11 @@ static int keyscan_process_file(FILE *f, struct keyscan_info *keyscan) break; case KEYSCAN_CMD_SEQ: if (keyscan_process_keys(keyscan, linenum, cur_test, - args)) { - fprintf(stderr, "Line %d: Cannot parse key " - "input '%s'\n", linenum, args); + args)) { + fprintf(stderr, + "Line %d: Cannot parse key " + "input '%s'\n", + linenum, args); return -1; } break; @@ -519,8 +523,8 @@ static int keyscan_send_sequence(struct keyscan_info *keyscan, fprintf(stderr, "Out of memory for message\n"); return -1; } - for (upto = rv = 0, item = test->items; rv >= 0 && - upto < test->item_count; upto++, item++) { + for (upto = rv = 0, item = test->items; + rv >= 0 && upto < test->item_count; upto++, item++) { req->cmd = EC_KEYSCAN_SEQ_ADD; req->add.time_us = item->beat * keyscan->beat_us; memcpy(req->add.scan, item->scan, sizeof(item->scan)); @@ -553,8 +557,8 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test) /* First clear the sequence */ ctrl.cmd = EC_KEYSCAN_SEQ_CLEAR; - rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), - NULL, 0); + rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL, + 0); if (rv < 0) return rv; @@ -565,13 +569,13 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test) /* Start it */ set_to_raw(fd, 1); ctrl.cmd = EC_KEYSCAN_SEQ_START; - rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), - NULL, 0); + rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), NULL, + 0); if (rv < 0) return rv; /* Work out how long we need to wait */ - wait_us = 100 * 1000; /* Wait 100ms to at least */ + wait_us = 100 * 1000; /* Wait 100ms to at least */ if (test->item_count) { struct keyscan_test_item *ksi; @@ -593,8 +597,8 @@ static int run_test(struct keyscan_info *keyscan, struct keyscan_test *test) ctrl.cmd = EC_KEYSCAN_SEQ_COLLECT; ctrl.collect.start_item = 0; ctrl.collect.num_items = test->item_count; - rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), - resp, size); + rv = ec_command(EC_CMD_KEYSCAN_SEQ_CTRL, 0, &ctrl, sizeof(ctrl), resp, + size); if (rv < 0) return rv; -- cgit v1.2.1 From 664713ef1b6ac5e4195c42b29891119512f53b0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:44 -0600 Subject: board/primus/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95f841a65ba81c81300853f300684dfd104fcd87 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728844 Reviewed-by: Jeremy Bettis --- board/primus/sensors.c | 62 +++++++++++++++++++++----------------------------- 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/board/primus/sensors.c b/board/primus/sensors.c index 60cfa1428f..91878cebae 100644 --- a/board/primus/sensors.c +++ b/board/primus/sensors.c @@ -59,36 +59,26 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_SSD] = { - .name = "SSD", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_SSD - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, - [TEMP_SENSOR_4_MEMORY] = { - .name = "MEMORY", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_MEMORY - }, - [TEMP_SENSOR_5_USBC] = { - .name = "USBC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_5_USBC - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_SSD] = { .name = "SSD", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_SSD }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, + [TEMP_SENSOR_4_MEMORY] = { .name = "MEMORY", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_MEMORY }, + [TEMP_SENSOR_5_USBC] = { .name = "USBC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_5_USBC }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -102,8 +92,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -119,8 +109,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_SSD \ - { \ +#define THERMAL_SSD \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(92), \ @@ -149,8 +139,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ssd = THERMAL_SSD; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ -- cgit v1.2.1 From 3681bcd4903aa3464c42a825644f7e68a13a1822 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:01 -0600 Subject: driver/usb_mux/amd_fp5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a05460d0d1bf976c1555ffe1beca4710805a79c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730152 Reviewed-by: Jeremy Bettis --- driver/usb_mux/amd_fp5.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/usb_mux/amd_fp5.h b/driver/usb_mux/amd_fp5.h index 7534ea0d8a..8fc6506447 100644 --- a/driver/usb_mux/amd_fp5.h +++ b/driver/usb_mux/amd_fp5.h @@ -8,14 +8,14 @@ #ifndef __CROS_EC_USB_MUX_AMD_FP5_H #define __CROS_EC_USB_MUX_AMD_FP5_H -#define AMD_FP5_MUX_I2C_ADDR_FLAGS 0x5C +#define AMD_FP5_MUX_I2C_ADDR_FLAGS 0x5C -#define AMD_FP5_MUX_SAFE 0x00 -#define AMD_FP5_MUX_USB 0x02 -#define AMD_FP5_MUX_USB_INVERTED 0x11 -#define AMD_FP5_MUX_DOCK 0x06 -#define AMD_FP5_MUX_DOCK_INVERTED 0x19 -#define AMD_FP5_MUX_DP 0x0C -#define AMD_FP5_MUX_DP_INVERTED 0x1C +#define AMD_FP5_MUX_SAFE 0x00 +#define AMD_FP5_MUX_USB 0x02 +#define AMD_FP5_MUX_USB_INVERTED 0x11 +#define AMD_FP5_MUX_DOCK 0x06 +#define AMD_FP5_MUX_DOCK_INVERTED 0x19 +#define AMD_FP5_MUX_DP 0x0C +#define AMD_FP5_MUX_DP_INVERTED 0x1C #endif /* __CROS_EC_USB_MUX_AMD_FP5_H */ -- cgit v1.2.1 From c437d2d0c8564ddc97a59a6b181d375e18def4d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:50 -0600 Subject: driver/charger/isl923x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50ee85a6dd237186d5ea5c94e668ac965e36e145 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729938 Reviewed-by: Jeremy Bettis --- driver/charger/isl923x.c | 182 ++++++++++++++++++++++------------------------- 1 file changed, 87 insertions(+), 95 deletions(-) diff --git a/driver/charger/isl923x.c b/driver/charger/isl923x.c index c90fe5224e..1fc218dbc8 100644 --- a/driver/charger/isl923x.c +++ b/driver/charger/isl923x.c @@ -32,62 +32,61 @@ #endif #ifdef CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 - #undef CONFIG_CHARGER_SENSE_RESISTOR_AC - #define CONFIG_CHARGER_SENSE_RESISTOR_AC \ - CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 +#undef CONFIG_CHARGER_SENSE_RESISTOR_AC +#define CONFIG_CHARGER_SENSE_RESISTOR_AC \ + CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 #endif - #define DEFAULT_R_AC 20 #define DEFAULT_R_SNS 10 #define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR -#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS) -#define CURRENT_TO_REG(CUR) ((CUR) * R_SNS / DEFAULT_R_SNS) -#define AC_REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_AC / R_AC) -#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC) +#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS) +#define CURRENT_TO_REG(CUR) ((CUR)*R_SNS / DEFAULT_R_SNS) +#define AC_REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_AC / R_AC) +#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC) #if defined(CONFIG_CHARGER_ISL9237) -#define CHARGER_NAME "isl9237" -#define CHARGE_V_MAX ISL9237_SYS_VOLTAGE_REG_MAX -#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN +#define CHARGER_NAME "isl9237" +#define CHARGE_V_MAX ISL9237_SYS_VOLTAGE_REG_MAX +#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN #define CHARGE_V_STEP 8 #elif defined(CONFIG_CHARGER_ISL9238) -#define CHARGER_NAME "isl9238" -#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX -#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN +#define CHARGER_NAME "isl9238" +#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX +#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN #define CHARGE_V_STEP 8 #elif defined(CONFIG_CHARGER_ISL9238C) -#define CHARGER_NAME "isl9238c" -#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX -#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN +#define CHARGER_NAME "isl9238c" +#define CHARGE_V_MAX ISL9238_SYS_VOLTAGE_REG_MAX +#define CHARGE_V_MIN ISL923X_SYS_VOLTAGE_REG_MIN #define CHARGE_V_STEP 8 #elif defined(CONFIG_CHARGER_RAA489000) -#define CHARGER_NAME "raa489000" -#define CHARGE_V_MAX RAA489000_SYS_VOLTAGE_REG_MAX -#define CHARGE_V_MIN RAA489000_SYS_VOLTAGE_REG_MIN +#define CHARGER_NAME "raa489000" +#define CHARGE_V_MAX RAA489000_SYS_VOLTAGE_REG_MAX +#define CHARGE_V_MIN RAA489000_SYS_VOLTAGE_REG_MIN #define CHARGE_V_STEP 8 #endif #ifdef CONFIG_CHARGER_RAA489000 -#define CHARGE_I_MAX RAA489000_CURRENT_REG_MAX +#define CHARGE_I_MAX RAA489000_CURRENT_REG_MAX #else -#define CHARGE_I_MAX ISL923X_CURRENT_REG_MAX +#define CHARGE_I_MAX ISL923X_CURRENT_REG_MAX #endif /* CONFIG_CHARGER_RAA489000 */ -#define CHARGE_I_MIN 4 -#define CHARGE_I_OFF 0 +#define CHARGE_I_MIN 4 +#define CHARGE_I_OFF 0 #define CHARGE_I_STEP 4 #ifdef CONFIG_CHARGER_RAA489000 -#define INPUT_I_MAX RAA489000_CURRENT_REG_MAX +#define INPUT_I_MAX RAA489000_CURRENT_REG_MAX #else -#define INPUT_I_MAX ISL923X_CURRENT_REG_MAX +#define INPUT_I_MAX ISL923X_CURRENT_REG_MAX #endif /* CONFIG_CHARGER_RAA489000 */ -#define INPUT_I_MIN 4 -#define INPUT_I_STEP 4 +#define INPUT_I_MIN 4 +#define INPUT_I_STEP 4 /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) enum isl923x_amon_bmon { AMON, BMON }; enum isl923x_mon_dir { MON_CHARGE = 0, MON_DISCHARGE = 1 }; @@ -102,38 +101,36 @@ static enum ec_error_list isl923x_discharge_on_ac_weak_disable(int chgnum); /* Charger parameters */ static const struct charger_info isl9237_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = REG_TO_CURRENT(CHARGE_I_MAX), - .current_min = REG_TO_CURRENT(CHARGE_I_MIN), + .current_max = REG_TO_CURRENT(CHARGE_I_MAX), + .current_min = REG_TO_CURRENT(CHARGE_I_MIN), .current_step = REG_TO_CURRENT(CHARGE_I_STEP), - .input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX), - .input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN), + .input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX), + .input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN), .input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP), }; static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value) { return i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list raw_write16(int chgnum, int offset, int value) { return i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list raw_update16(int chgnum, int offset, int mask, enum mask_update_action action) { return i2c_update16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, mask, action); + chg_chips[chgnum].i2c_addr_flags, offset, mask, + action); } static enum ec_error_list isl9237_set_current(int chgnum, uint16_t current) @@ -236,7 +233,7 @@ static enum ec_error_list isl923x_get_input_current_limit(int chgnum, #ifdef CONFIG_CHARGER_RAA489000 static enum ec_error_list raa489000_get_input_current(int chgnum, - int *input_current) + int *input_current) { int rv; int regval; @@ -305,13 +302,13 @@ static enum ec_error_list isl923x_set_otg_current_voltage(int chgnum, { int rv; uint16_t volt_reg = (output_voltage / ISL9238_OTG_VOLTAGE_STEP) - << ISL9238_OTG_VOLTAGE_SHIFT; + << ISL9238_OTG_VOLTAGE_SHIFT; uint16_t current_reg = DIV_ROUND_UP(output_current, ISL923X_OTG_CURRENT_STEP) - << ISL923X_OTG_CURRENT_SHIFT; + << ISL923X_OTG_CURRENT_SHIFT; if (output_current < 0 || output_current > ISL923X_OTG_CURRENT_MAX || - output_voltage > ISL9238_OTG_VOLTAGE_MAX) + output_voltage > ISL9238_OTG_VOLTAGE_MAX) return EC_ERROR_INVAL; /* Set voltage. */ @@ -554,8 +551,8 @@ int isl923x_set_comparator_inversion(int chgnum, int invert) int regval; rv = i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - ISL923X_REG_CONTROL2, ®val); + chg_chips[chgnum].i2c_addr_flags, ISL923X_REG_CONTROL2, + ®val); if (invert) regval |= ISL923X_C2_INVERT_CMOUT; else @@ -577,8 +574,8 @@ static void isl923x_init(int chgnum) { int reg; const struct battery_info *bi = battery_get_info(); - int precharge_voltage = bi->precharge_voltage ? - bi->precharge_voltage : bi->voltage_min; + int precharge_voltage = bi->precharge_voltage ? bi->precharge_voltage : + bi->voltage_min; if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) { if (CONFIG_CHARGER_SENSE_RESISTOR == @@ -590,9 +587,9 @@ static void isl923x_init(int chgnum) if (raw_read16(chgnum, ISL9238_REG_CONTROL4, ®)) goto init_fail; - if (raw_write16(chgnum, ISL9238_REG_CONTROL4, - reg | - RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1)) + if (raw_write16( + chgnum, ISL9238_REG_CONTROL4, + reg | RAA489000_C4_PSYS_RSNS_RATIO_1_TO_1)) goto init_fail; } @@ -603,8 +600,7 @@ static void isl923x_init(int chgnum) goto init_fail; if (raw_write16(chgnum, ISL9238_REG_CONTROL3, - reg | - RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE)) + reg | RAA489000_C3_DCM_CCM_HYSTERESIS_ENABLE)) goto init_fail; /* Set switching frequency to 600KHz to help with ripple. */ @@ -614,8 +610,7 @@ static void isl923x_init(int chgnum) reg &= ~ISL923X_C1_SWITCH_FREQ_MASK; if (raw_write16(chgnum, ISL923X_REG_CONTROL1, - reg | - ISL9237_C1_SWITCH_FREQ_599K)) + reg | ISL9237_C1_SWITCH_FREQ_599K)) goto init_fail; } @@ -650,8 +645,7 @@ static void isl923x_init(int chgnum) reg |= ISL923X_C2_PROCHOT_DEBOUNCE_1000; if (raw_write16(chgnum, ISL923X_REG_CONTROL2, - reg | - ISL923X_C2_ADAPTER_DEBOUNCE_150)) + reg | ISL923X_C2_ADAPTER_DEBOUNCE_150)) goto init_fail; /* @@ -687,10 +681,10 @@ static void isl923x_init(int chgnum) */ if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) reg = (4437 / RAA489000_INPUT_VOLTAGE_REF_STEP) - << RAA489000_INPUT_VOLTAGE_REF_SHIFT; + << RAA489000_INPUT_VOLTAGE_REF_SHIFT; else reg = (4439 / ISL9238_INPUT_VOLTAGE_REF_STEP) - << ISL9238_INPUT_VOLTAGE_REF_SHIFT; + << ISL9238_INPUT_VOLTAGE_REF_SHIFT; if (raw_write16(chgnum, ISL9238_REG_INPUT_VOLTAGE, reg)) goto init_fail; @@ -762,7 +756,7 @@ static void isl923x_init(int chgnum) * Initialize the input current limit to the board's default. */ if (isl923x_set_input_current_limit( - chgnum, CONFIG_CHARGER_INPUT_CURRENT)) + chgnum, CONFIG_CHARGER_INPUT_CURRENT)) goto init_fail; } @@ -975,16 +969,15 @@ enum ec_error_list isl9238c_hibernate(int chgnum) { /* Disable PSYS */ RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1, - ISL923X_C1_ENABLE_PSYS, MASK_CLR)); + ISL923X_C1_ENABLE_PSYS, MASK_CLR)); /* Disable GP comparator */ RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2, - ISL923X_C2_COMPARATOR, MASK_SET)); + ISL923X_C2_COMPARATOR, MASK_SET)); /* Force BGATE off */ RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3, - ISL9238_C3_BGATE_OFF, MASK_SET)); - + ISL9238_C3_BGATE_OFF, MASK_SET)); return EC_SUCCESS; } @@ -993,18 +986,17 @@ enum ec_error_list isl9238c_resume(int chgnum) { /* Revert everything in isl9238c_hibernate() */ RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL1, - ISL923X_C1_ENABLE_PSYS, MASK_SET)); + ISL923X_C1_ENABLE_PSYS, MASK_SET)); RETURN_ERROR(raw_update16(chgnum, ISL923X_REG_CONTROL2, - ISL923X_C2_COMPARATOR, MASK_CLR)); + ISL923X_C2_COMPARATOR, MASK_CLR)); RETURN_ERROR(raw_update16(chgnum, ISL9238_REG_CONTROL3, - ISL9238_C3_BGATE_OFF, MASK_CLR)); + ISL9238_C3_BGATE_OFF, MASK_CLR)); return EC_SUCCESS; } - /*****************************************************************************/ /* Hardware current ramping */ @@ -1038,7 +1030,6 @@ static int isl923x_ramp_get_current_limit(int chgnum) } #endif /* CONFIG_CHARGE_RAMP_HW */ - #ifdef CONFIG_CHARGER_PSYS static int psys_enabled; /* @@ -1120,8 +1111,7 @@ static int console_command_psys(int argc, char **argv) ccprintf("PSYS = %d uW\n", charger_get_system_power()); return 0; } -DECLARE_CONSOLE_COMMAND(psys, console_command_psys, - NULL, +DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL, "Get the system power in mW"); #endif /* CONFIG_CHARGER_PSYS_READ */ #endif /* CONFIG_CHARGER_PSYS */ @@ -1138,7 +1128,7 @@ static int print_amon_bmon(int chgnum, enum isl923x_amon_bmon amon, curr = adc / resistor; ccprintf("%cMON(%sharging): %d uV, %d mA\n", amon == AMON ? 'A' : 'B', - direction == MON_DISCHARGE ? "Disc" : "C", adc, curr); + direction == MON_DISCHARGE ? "Disc" : "C", adc, curr); return ret; } @@ -1172,24 +1162,27 @@ static int console_command_amon_bmon(int argc, char **argv) if (print_ac) { if (print_charge) - ret |= print_amon_bmon(chgnum, AMON, MON_CHARGE, - CONFIG_CHARGER_SENSE_RESISTOR_AC); + ret |= print_amon_bmon( + chgnum, AMON, MON_CHARGE, + CONFIG_CHARGER_SENSE_RESISTOR_AC); if (IS_ENABLED(CHARGER_ISL9238X) && print_discharge) - ret |= print_amon_bmon(chgnum, AMON, MON_DISCHARGE, - CONFIG_CHARGER_SENSE_RESISTOR_AC); + ret |= print_amon_bmon( + chgnum, AMON, MON_DISCHARGE, + CONFIG_CHARGER_SENSE_RESISTOR_AC); } if (print_battery) { if (IS_ENABLED(CHARGER_ISL9238X) && print_charge) - ret |= print_amon_bmon(chgnum, BMON, MON_CHARGE, - /* - * charging current monitor has - * 2x amplification factor - */ - 2 * CONFIG_CHARGER_SENSE_RESISTOR); + ret |= print_amon_bmon( + chgnum, BMON, MON_CHARGE, + /* + * charging current monitor has + * 2x amplification factor + */ + 2 * CONFIG_CHARGER_SENSE_RESISTOR); if (print_discharge) ret |= print_amon_bmon(chgnum, BMON, MON_DISCHARGE, - CONFIG_CHARGER_SENSE_RESISTOR); + CONFIG_CHARGER_SENSE_RESISTOR); } return ret; @@ -1213,8 +1206,7 @@ static void dump_reg_range(int chgnum, int low, int high) for (reg = low; reg <= high; reg++) { CPRINTF("[%Xh] = ", reg); rv = i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - reg, ®val); + chg_chips[chgnum].i2c_addr_flags, reg, ®val); if (!rv) CPRINTF("0x%04x\n", regval); else @@ -1275,15 +1267,14 @@ static enum ec_error_list raa489000_enable_linear_charge(int chgnum, /* Disable charge current loop for the aux charger. */ rv |= raw_update16(act_chg, RAA489000_REG_CONTROL10, - RAA489000_C10_DISABLE_DVC_CC_LOOP, - MASK_SET); + RAA489000_C10_DISABLE_DVC_CC_LOOP, MASK_SET); /* * Set primary charger charge current to the desired precharge * current. */ rv |= isl9237_set_current(CHARGER_PRIMARY, - batt_info->precharge_current); + batt_info->precharge_current); /* * Set primary charger max VSYS to the max of the battery. @@ -1307,10 +1298,11 @@ static enum ec_error_list raa489000_enable_linear_charge(int chgnum, regval); /* Enable DVC trickle charge and DVC charge mode. */ - rv |= raw_update16(CHARGER_PRIMARY, RAA489000_REG_CONTROL10, - RAA489000_C10_ENABLE_DVC_MODE | - RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE, - MASK_SET); + rv |= raw_update16( + CHARGER_PRIMARY, RAA489000_REG_CONTROL10, + RAA489000_C10_ENABLE_DVC_MODE | + RAA489000_C10_ENABLE_DVC_TRICKLE_CHARGE, + MASK_SET); if (rv) return EC_ERROR_UNKNOWN; -- cgit v1.2.1 From 9edf64f19cb510f7505751586bef08c46969a6c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:15 -0600 Subject: builtin/stdbool.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic40cf953745bb9064bf2f0b9b49374aab60462e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729145 Reviewed-by: Jeremy Bettis --- builtin/stdbool.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/builtin/stdbool.h b/builtin/stdbool.h index 6e0f92dfc0..fa6c896acb 100644 --- a/builtin/stdbool.h +++ b/builtin/stdbool.h @@ -6,8 +6,8 @@ #ifndef __CROS_EC_STDBOOL_H__ #define __CROS_EC_STDBOOL_H__ -#define bool _Bool -#define true 1 -#define false 0 +#define bool _Bool +#define true 1 +#define false 0 #endif /* __CROS_EC_STDBOOL_H__ */ -- cgit v1.2.1 From b4e3d8bf00238ebab828ea563e94f4c6e7966662 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:30 -0600 Subject: board/corori2/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia7d0efe110a93cd43c6dda779966c89779988c61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728165 Reviewed-by: Jeremy Bettis --- board/corori2/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/corori2/led.c b/board/corori2/led.c index 3c27bf0f8e..1df2e00a5b 100644 --- a/board/corori2/led.c +++ b/board/corori2/led.c @@ -20,13 +20,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, White */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 100 }, - [EC_LED_COLOR_AMBER] = { 100, 0 }, + /* Amber, White */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 }, }; /* One logical LED with amber and white channels. */ -- cgit v1.2.1 From 43a0ac545ce76541b532b0920a7a3afafd3c31de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:25 -0600 Subject: driver/bc12/pi3usb9281.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I132c7568376906607d031b62a0b7e1291311182f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729955 Reviewed-by: Jeremy Bettis --- driver/bc12/pi3usb9281.h | 78 ++++++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/driver/bc12/pi3usb9281.h b/driver/bc12/pi3usb9281.h index ca1828f49c..95d09a0c58 100644 --- a/driver/bc12/pi3usb9281.h +++ b/driver/bc12/pi3usb9281.h @@ -8,55 +8,55 @@ #ifndef __CROS_EC_PI3USB9281_H #define __CROS_EC_PI3USB9281_H -#define PI3USB9281_REG_DEV_ID 0x01 -#define PI3USB9281_REG_CONTROL 0x02 -#define PI3USB9281_REG_INT 0x03 -#define PI3USB9281_REG_INT_MASK 0x05 -#define PI3USB9281_REG_DEV_TYPE 0x0a -#define PI3USB9281_REG_CHG_STATUS 0x0e -#define PI3USB9281_REG_MANUAL 0x13 -#define PI3USB9281_REG_RESET 0x1b -#define PI3USB9281_REG_VBUS 0x1d +#define PI3USB9281_REG_DEV_ID 0x01 +#define PI3USB9281_REG_CONTROL 0x02 +#define PI3USB9281_REG_INT 0x03 +#define PI3USB9281_REG_INT_MASK 0x05 +#define PI3USB9281_REG_DEV_TYPE 0x0a +#define PI3USB9281_REG_CHG_STATUS 0x0e +#define PI3USB9281_REG_MANUAL 0x13 +#define PI3USB9281_REG_RESET 0x1b +#define PI3USB9281_REG_VBUS 0x1d -#define PI3USB9281_DEV_ID 0x10 -#define PI3USB9281_DEV_ID_A 0x18 +#define PI3USB9281_DEV_ID 0x10 +#define PI3USB9281_DEV_ID_A 0x18 -#define PI3USB9281_CTRL_INT_DIS BIT(0) -#define PI3USB9281_CTRL_AUTO BIT(2) +#define PI3USB9281_CTRL_INT_DIS BIT(0) +#define PI3USB9281_CTRL_AUTO BIT(2) #define PI3USB9281_CTRL_SWITCH_AUTO BIT(4) /* Bits 5 thru 7 are read X, write 0 */ -#define PI3USB9281_CTRL_MASK 0x1f +#define PI3USB9281_CTRL_MASK 0x1f /* Bits 1 and 3 are read 1, write 1 */ -#define PI3USB9281_CTRL_RSVD_1 0x0a +#define PI3USB9281_CTRL_RSVD_1 0x0a -#define PI3USB9281_PIN_MANUAL_VBUS (3 << 0) -#define PI3USB9281_PIN_MANUAL_DP BIT(2) -#define PI3USB9281_PIN_MANUAL_DM BIT(5) +#define PI3USB9281_PIN_MANUAL_VBUS (3 << 0) +#define PI3USB9281_PIN_MANUAL_DP BIT(2) +#define PI3USB9281_PIN_MANUAL_DM BIT(5) -#define PI3USB9281_INT_ATTACH BIT(0) -#define PI3USB9281_INT_DETACH BIT(1) -#define PI3USB9281_INT_OVP BIT(5) -#define PI3USB9281_INT_OCP BIT(6) -#define PI3USB9281_INT_OVP_OC BIT(7) -#define PI3USB9281_INT_ATTACH_DETACH (PI3USB9281_INT_ATTACH | \ - PI3USB9281_INT_DETACH) +#define PI3USB9281_INT_ATTACH BIT(0) +#define PI3USB9281_INT_DETACH BIT(1) +#define PI3USB9281_INT_OVP BIT(5) +#define PI3USB9281_INT_OCP BIT(6) +#define PI3USB9281_INT_OVP_OC BIT(7) +#define PI3USB9281_INT_ATTACH_DETACH \ + (PI3USB9281_INT_ATTACH | PI3USB9281_INT_DETACH) -#define PI3USB9281_TYPE_NONE 0 -#define PI3USB9281_TYPE_MHL BIT(0) -#define PI3USB9281_TYPE_OTG BIT(1) -#define PI3USB9281_TYPE_SDP BIT(2) -#define PI3USB9281_TYPE_CAR BIT(4) -#define PI3USB9281_TYPE_CDP BIT(5) -#define PI3USB9281_TYPE_DCP BIT(6) +#define PI3USB9281_TYPE_NONE 0 +#define PI3USB9281_TYPE_MHL BIT(0) +#define PI3USB9281_TYPE_OTG BIT(1) +#define PI3USB9281_TYPE_SDP BIT(2) +#define PI3USB9281_TYPE_CAR BIT(4) +#define PI3USB9281_TYPE_CDP BIT(5) +#define PI3USB9281_TYPE_DCP BIT(6) -#define PI3USB9281_CHG_NONE 0 -#define PI3USB9281_CHG_CAR_TYPE1 BIT(1) -#define PI3USB9281_CHG_CAR_TYPE2 (3 << 0) -#define PI3USB9281_CHG_APPLE_1A BIT(2) -#define PI3USB9281_CHG_APPLE_2A BIT(3) -#define PI3USB9281_CHG_APPLE_2_4A BIT(4) +#define PI3USB9281_CHG_NONE 0 +#define PI3USB9281_CHG_CAR_TYPE1 BIT(1) +#define PI3USB9281_CHG_CAR_TYPE2 (3 << 0) +#define PI3USB9281_CHG_APPLE_1A BIT(2) +#define PI3USB9281_CHG_APPLE_2A BIT(3) +#define PI3USB9281_CHG_APPLE_2_4A BIT(4) /* Check if charge status has any connection */ -#define PI3USB9281_CHG_STATUS_ANY(x) (((x) & 0x1f) > 1) +#define PI3USB9281_CHG_STATUS_ANY(x) (((x)&0x1f) > 1) /* Define configuration of one pi3usb9281 part */ struct pi3usb9281_config { -- cgit v1.2.1 From d20926d1727120b645ee7496152d5e8dbcf8cd49 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:21 -0600 Subject: chip/stm32/usb_dwc_hw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20e2d448f5416e790791ab7dbeb9720a6ed95e1d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729551 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_hw.h | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/chip/stm32/usb_dwc_hw.h b/chip/stm32/usb_dwc_hw.h index d1fe07cb87..14dcda608e 100644 --- a/chip/stm32/usb_dwc_hw.h +++ b/chip/stm32/usb_dwc_hw.h @@ -18,29 +18,27 @@ #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler +#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ + void _EP_TX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(tx_handler)))); \ + void _EP_RX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(rx_handler)))); \ + void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ + __attribute__((alias(STRINGIFY(evt_handler)))); \ + static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \ + tx_handler; \ + static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \ + rx_handler; \ + static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))( \ + enum usb_ep_event evt) = evt_handler /* Endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); +extern void (*usb_ep_tx[])(void); +extern void (*usb_ep_rx[])(void); +extern void (*usb_ep_event[])(enum usb_ep_event evt); struct usb_setup_packet; /* EP0 Interface handler callbacks */ -extern int (*usb_iface_request[]) (struct usb_setup_packet *req); - +extern int (*usb_iface_request[])(struct usb_setup_packet *req); /* True if the HW Rx/OUT FIFO is currently listening. */ int rx_ep_is_active(uint32_t ep_num); @@ -99,8 +97,8 @@ void epN_reset(uint32_t ep_num); * (and thus indicate error to the host). */ #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(struct usb_setup_packet *req) \ - __attribute__ ((alias(STRINGIFY(handler)))) +#define USB_DECLARE_IFACE(num, handler) \ + int _IFACE_HANDLER(num)(struct usb_setup_packet * req) \ + __attribute__((alias(STRINGIFY(handler)))) -#endif /* __CROS_EC_USB_DWC_HW_H */ +#endif /* __CROS_EC_USB_DWC_HW_H */ -- cgit v1.2.1 From 37124c5c1c24be671ffcf1684b8e2e6d832c45ae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:31 -0600 Subject: board/nautilus/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic941c0668e2098680ac91da6abf6a118ca636ebf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728724 Reviewed-by: Jeremy Bettis --- board/nautilus/led.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/board/nautilus/led.c b/board/nautilus/led.c index 86567701f0..93cabbd4c9 100644 --- a/board/nautilus/led.c +++ b/board/nautilus/led.c @@ -23,9 +23,8 @@ #define LED_TOTAL_TICKS 16 #define LED_ON_TICKS 8 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -67,7 +66,6 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) return EC_SUCCESS; } - static void nautilus_led_set_power_battery(void) { static unsigned int power_ticks; @@ -82,9 +80,10 @@ static void nautilus_led_set_power_battery(void) /* Flash red on critical battery, which usually inhibits AP power-on. */ if (battery_is_present() != BP_YES || - charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { - set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ? - LED_RED : LED_OFF); + charge_percent < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { + set_color(((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ? + LED_RED : + LED_OFF); return; } @@ -92,7 +91,7 @@ static void nautilus_led_set_power_battery(void) switch (chg_state) { case PWR_STATE_DISCHARGE: if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) && - charge_percent >= BATTERY_LEVEL_NEAR_FULL) + charge_percent >= BATTERY_LEVEL_NEAR_FULL) cur_led_color = LED_GREEN; else cur_led_color = LED_OFF; @@ -101,12 +100,14 @@ static void nautilus_led_set_power_battery(void) cur_led_color = LED_RED; break; case PWR_STATE_ERROR: - cur_led_color = ((power_ticks++ % LED_TOTAL_TICKS) - < LED_ON_TICKS) ? LED_RED : LED_GREEN; + cur_led_color = + ((power_ticks++ % LED_TOTAL_TICKS) < LED_ON_TICKS) ? + LED_RED : + LED_GREEN; break; case PWR_STATE_CHARGE_NEAR_FULL: case PWR_STATE_IDLE: - if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) + if (charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) cur_led_color = LED_GREEN; else cur_led_color = LED_OFF; @@ -128,8 +129,8 @@ static void nautilus_led_set_power_battery(void) static void led_tick(void) { if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED) && - led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { - nautilus_led_set_power_battery(); + led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + nautilus_led_set_power_battery(); } } -- cgit v1.2.1 From 25711b614bf8d780b19d06047b3f544a0cb799e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:10 -0600 Subject: chip/max32660/gcr_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f9df736f7a45d092ce820528308f363aafa98eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729220 Reviewed-by: Jeremy Bettis --- chip/max32660/gcr_regs.h | 2003 +++++++++++++++++++++++++--------------------- 1 file changed, 1110 insertions(+), 893 deletions(-) diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h index c9de13812c..560029961d 100644 --- a/chip/max32660/gcr_regs.h +++ b/chip/max32660/gcr_regs.h @@ -39,118 +39,121 @@ * Structure type to access the GCR Registers. */ typedef struct { - __IO uint32_t scon; /**< \b 0x00:<\tt> GCR SCON Register */ + __IO uint32_t scon; /**< \b 0x00:<\tt> GCR SCON Register */ __IO uint32_t rstr0; /**< \b 0x04:<\tt> GCR RSTR0 Register */ __IO uint32_t clkcn; /**< \b 0x08:<\tt> GCR CLKCN Register */ - __IO uint32_t pm; /**< \b 0x0C:<\tt> GCR PM Register */ + __IO uint32_t pm; /**< \b 0x0C:<\tt> GCR PM Register */ __R uint32_t rsv_0x10_0x17[2]; __IO uint32_t pckdiv; /**< \b 0x18:<\tt> GCR PCKDIV Register */ __R uint32_t rsv_0x1c_0x23[2]; __IO uint32_t perckcn0; /**< \b 0x24:<\tt> GCR PERCKCN0 Register */ - __IO uint32_t memckcn; /**< \b 0x28:<\tt> GCR MEMCKCN Register */ - __IO uint32_t memzcn; /**< \b 0x2C:<\tt> GCR MEMZCN Register */ + __IO uint32_t memckcn; /**< \b 0x28:<\tt> GCR MEMCKCN Register */ + __IO uint32_t memzcn; /**< \b 0x2C:<\tt> GCR MEMZCN Register */ __R uint32_t rsv_0x30; - __IO uint32_t scck; /**< \b 0x34:<\tt> GCR SCCK Register */ - __IO uint32_t mpri0; /**< \b 0x38:<\tt> GCR MPRI0 Register */ - __IO uint32_t mpri1; /**< \b 0x3C:<\tt> GCR MPRI1 Register */ - __IO uint32_t sysst; /**< \b 0x40:<\tt> GCR SYSST Register */ - __IO uint32_t rstr1; /**< \b 0x44:<\tt> GCR RSTR1 Register */ + __IO uint32_t scck; /**< \b 0x34:<\tt> GCR SCCK Register */ + __IO uint32_t mpri0; /**< \b 0x38:<\tt> GCR MPRI0 Register */ + __IO uint32_t mpri1; /**< \b 0x3C:<\tt> GCR MPRI1 Register */ + __IO uint32_t sysst; /**< \b 0x40:<\tt> GCR SYSST Register */ + __IO uint32_t rstr1; /**< \b 0x44:<\tt> GCR RSTR1 Register */ __IO uint32_t perckcn1; /**< \b 0x48:<\tt> GCR PERCKCN1 Register */ - __IO uint32_t evten; /**< \b 0x4C:<\tt> GCR EVTEN Register */ - __I uint32_t revision; /**< \b 0x50:<\tt> GCR REVISION Register */ - __IO uint32_t syssie; /**< \b 0x54:<\tt> GCR SYSSIE Register */ + __IO uint32_t evten; /**< \b 0x4C:<\tt> GCR EVTEN Register */ + __I uint32_t revision; /**< \b 0x50:<\tt> GCR REVISION Register */ + __IO uint32_t syssie; /**< \b 0x54:<\tt> GCR SYSSIE Register */ } mxc_gcr_regs_t; /** * GCR Peripheral Register Offsets from the GCR Base Peripheral * Address. */ -#define MXC_R_GCR_SCON \ - ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_SCON \ + ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: \ 0x0x000 */ -#define MXC_R_GCR_RSTR0 \ - ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_RSTR0 \ + ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: \ 0x0x004 */ -#define MXC_R_GCR_CLKCN \ - ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_CLKCN \ + ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: \ 0x0x008 */ -#define MXC_R_GCR_PM \ - ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_PM \ + ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: \ 0x0x00C */ -#define MXC_R_GCR_PCKDIV \ - ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_PCKDIV \ + ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: \ 0x0x018 */ -#define MXC_R_GCR_PERCKCN0 \ - ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_PERCKCN0 \ + ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: \ 0x0x024 */ -#define MXC_R_GCR_MEMCKCN \ - ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_MEMCKCN \ + ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: \ 0x0x028 */ -#define MXC_R_GCR_MEMZCN \ - ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_MEMZCN \ + ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: \ 0x0x02C */ -#define MXC_R_GCR_SCCK \ - ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_SCCK \ + ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: \ 0x0x034 */ -#define MXC_R_GCR_MPRI0 \ - ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_MPRI0 \ + ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: \ 0x0x038 */ -#define MXC_R_GCR_MPRI1 \ - ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_MPRI1 \ + ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: \ 0x0x03C */ -#define MXC_R_GCR_SYSST \ - ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_SYSST \ + ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: \ 0x0x040 */ -#define MXC_R_GCR_RSTR1 \ - ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_RSTR1 \ + ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: \ 0x0x044 */ -#define MXC_R_GCR_PERCKCN1 \ - ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_PERCKCN1 \ + ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: \ 0x0x048 */ -#define MXC_R_GCR_EVTEN \ - ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_EVTEN \ + ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: \ 0x0x04C */ -#define MXC_R_GCR_REVISION \ - ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_REVISION \ + ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: \ 0x0x050 */ -#define MXC_R_GCR_SYSSIE \ - ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: \ +#define MXC_R_GCR_SYSSIE \ + ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: \ 0x0x054 */ /** * System Control. */ #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ -#define MXC_F_GCR_SCON_SBUSARB \ - ((uint32_t)(0x3UL \ - << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ -#define MXC_V_GCR_SCON_SBUSARB_FIX \ +#define MXC_F_GCR_SCON_SBUSARB \ + ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB \ + Mask */ +#define MXC_V_GCR_SCON_SBUSARB_FIX \ ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ -#define MXC_S_GCR_SCON_SBUSARB_FIX \ - (MXC_V_GCR_SCON_SBUSARB_FIX \ - << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ -#define MXC_V_GCR_SCON_SBUSARB_ROUND \ +#define MXC_S_GCR_SCON_SBUSARB_FIX \ + (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ + SCON_SBUSARB_FIX \ + Setting \ + */ +#define MXC_V_GCR_SCON_SBUSARB_ROUND \ ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ -#define MXC_S_GCR_SCON_SBUSARB_ROUND \ - (MXC_V_GCR_SCON_SBUSARB_ROUND \ - << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ +#define MXC_S_GCR_SCON_SBUSARB_ROUND \ + (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ + SCON_SBUSARB_ROUND \ + Setting \ + */ -#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \ +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \ 4 /**< SCON_FLASH_PAGE_FLIP Position */ -#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< \ - SCON_FLASH_PAGE_FLIP \ - Mask */ -#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ +#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< \ + SCON_FLASH_PAGE_FLIP \ + Mask */ +#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL \ << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< \ SCON_FLASH_PAGE_FLIP_NORMAL \ Setting */ -#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ +#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED \ @@ -159,1053 +162,1246 @@ typedef struct { Setting */ #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ -#define MXC_F_GCR_SCON_FPU_DIS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ -#define MXC_V_GCR_SCON_FPU_DIS_ENABLE \ +#define MXC_F_GCR_SCON_FPU_DIS \ + ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS \ + Mask */ +#define MXC_V_GCR_SCON_FPU_DIS_ENABLE \ ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_ENABLE \ - (MXC_V_GCR_SCON_FPU_DIS_ENABLE \ - << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */ -#define MXC_V_GCR_SCON_FPU_DIS_DISABLE \ +#define MXC_S_GCR_SCON_FPU_DIS_ENABLE \ + (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ + SCON_FPU_DIS_ENABLE \ + Setting \ + */ +#define MXC_V_GCR_SCON_FPU_DIS_DISABLE \ ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_DISABLE \ - (MXC_V_GCR_SCON_FPU_DIS_DISABLE \ - << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */ +#define MXC_S_GCR_SCON_FPU_DIS_DISABLE \ + (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ + SCON_FPU_DIS_DISABLE \ + Setting \ + */ #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ -#define MXC_F_GCR_SCON_CCACHE_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH \ - Mask */ -#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ +#define MXC_F_GCR_SCON_CCACHE_FLUSH \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< \ + SCON_CCACHE_FLUSH \ + Mask */ +#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ -#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL \ - (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL \ +#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL \ + (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL \ + << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL \ Setting */ -#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ +#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ -#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH \ - (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ - << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH \ +#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH \ + (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH \ + << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH \ Setting */ #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ -#define MXC_F_GCR_SCON_SWD_DIS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ -#define MXC_V_GCR_SCON_SWD_DIS_ENABLE \ +#define MXC_F_GCR_SCON_SWD_DIS \ + ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS \ + Mask */ +#define MXC_V_GCR_SCON_SWD_DIS_ENABLE \ ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_ENABLE \ - (MXC_V_GCR_SCON_SWD_DIS_ENABLE \ - << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */ -#define MXC_V_GCR_SCON_SWD_DIS_DISABLE \ +#define MXC_S_GCR_SCON_SWD_DIS_ENABLE \ + (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ + SCON_SWD_DIS_ENABLE \ + Setting \ + */ +#define MXC_V_GCR_SCON_SWD_DIS_DISABLE \ ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_DISABLE \ - (MXC_V_GCR_SCON_SWD_DIS_DISABLE \ - << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */ +#define MXC_S_GCR_SCON_SWD_DIS_DISABLE \ + (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ + SCON_SWD_DIS_DISABLE \ + Setting \ + */ /** * Reset Register 0. */ #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ -#define MXC_F_GCR_RSTR0_DMA \ +#define MXC_F_GCR_RSTR0_DMA \ ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ #define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */ -#define MXC_S_GCR_RSTR0_DMA_RFU \ - (MXC_V_GCR_RSTR0_DMA_RFU \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */ -#define MXC_V_GCR_RSTR0_DMA_RESET \ +#define MXC_S_GCR_RSTR0_DMA_RFU \ + (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_DMA_RESET \ ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET \ - (MXC_V_GCR_RSTR0_DMA_RESET \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */ -#define MXC_V_GCR_RSTR0_DMA_RESET_DONE \ +#define MXC_S_GCR_RSTR0_DMA_RESET \ + (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_DMA_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ - (MXC_V_GCR_RSTR0_DMA_RESET_DONE \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_DMA_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \ +#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ + (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_DMA_BUSY \ + ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_DMA_BUSY \ - (MXC_V_GCR_RSTR0_DMA_BUSY \ - << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */ +#define MXC_S_GCR_RSTR0_DMA_BUSY \ + (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ -#define MXC_F_GCR_RSTR0_WDT \ +#define MXC_F_GCR_RSTR0_WDT \ ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */ #define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */ -#define MXC_S_GCR_RSTR0_WDT_RFU \ - (MXC_V_GCR_RSTR0_WDT_RFU \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */ -#define MXC_V_GCR_RSTR0_WDT_RESET \ +#define MXC_S_GCR_RSTR0_WDT_RFU \ + (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_WDT_RESET \ ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET \ - (MXC_V_GCR_RSTR0_WDT_RESET \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */ -#define MXC_V_GCR_RSTR0_WDT_RESET_DONE \ +#define MXC_S_GCR_RSTR0_WDT_RESET \ + (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_WDT_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET_DONE \ - (MXC_V_GCR_RSTR0_WDT_RESET_DONE \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_WDT_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \ +#define MXC_S_GCR_RSTR0_WDT_RESET_DONE \ + (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_WDT_BUSY \ + ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_WDT_BUSY \ - (MXC_V_GCR_RSTR0_WDT_BUSY \ - << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */ +#define MXC_S_GCR_RSTR0_WDT_BUSY \ + (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ #define MXC_F_GCR_RSTR0_GPIO0 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ -#define MXC_V_GCR_RSTR0_GPIO0_RFU \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask \ + */ +#define MXC_V_GCR_RSTR0_GPIO0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RFU \ - (MXC_V_GCR_RSTR0_GPIO0_RFU \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_RESET \ +#define MXC_S_GCR_RSTR0_GPIO0_RFU \ + (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_GPIO0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET \ - (MXC_V_GCR_RSTR0_GPIO0_RESET \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ +#define MXC_S_GCR_RSTR0_GPIO0_RESET \ + (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE \ - (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_GPIO0_BUSY \ +#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE \ + (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_GPIO0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */ -#define MXC_S_GCR_RSTR0_GPIO0_BUSY \ - (MXC_V_GCR_RSTR0_GPIO0_BUSY \ - << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */ +#define MXC_S_GCR_RSTR0_GPIO0_BUSY \ + (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ -#define MXC_F_GCR_RSTR0_TIMER0 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ -#define MXC_V_GCR_RSTR0_TIMER0_RFU \ +#define MXC_F_GCR_RSTR0_TIMER0 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 \ + Mask */ +#define MXC_V_GCR_RSTR0_TIMER0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RFU \ - (MXC_V_GCR_RSTR0_TIMER0_RFU \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER0_RESET \ +#define MXC_S_GCR_RSTR0_TIMER0_RFU \ + (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_RFU \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RESET \ - (MXC_V_GCR_RSTR0_TIMER0_RESET \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ +#define MXC_S_GCR_RSTR0_TIMER0_RESET \ + (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting \ +#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE \ + (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ + << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting \ */ -#define MXC_V_GCR_RSTR0_TIMER0_BUSY \ +#define MXC_V_GCR_RSTR0_TIMER0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER0_BUSY \ - (MXC_V_GCR_RSTR0_TIMER0_BUSY \ - << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */ +#define MXC_S_GCR_RSTR0_TIMER0_BUSY \ + (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ -#define MXC_F_GCR_RSTR0_TIMER1 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ -#define MXC_V_GCR_RSTR0_TIMER1_RFU \ +#define MXC_F_GCR_RSTR0_TIMER1 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 \ + Mask */ +#define MXC_V_GCR_RSTR0_TIMER1_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RFU \ - (MXC_V_GCR_RSTR0_TIMER1_RFU \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER1_RESET \ +#define MXC_S_GCR_RSTR0_TIMER1_RFU \ + (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_RFU \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RESET \ - (MXC_V_GCR_RSTR0_TIMER1_RESET \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ +#define MXC_S_GCR_RSTR0_TIMER1_RESET \ + (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting \ +#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE \ + (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ + << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting \ */ -#define MXC_V_GCR_RSTR0_TIMER1_BUSY \ +#define MXC_V_GCR_RSTR0_TIMER1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER1_BUSY \ - (MXC_V_GCR_RSTR0_TIMER1_BUSY \ - << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */ +#define MXC_S_GCR_RSTR0_TIMER1_BUSY \ + (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ -#define MXC_F_GCR_RSTR0_TIMER2 \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ -#define MXC_V_GCR_RSTR0_TIMER2_RFU \ +#define MXC_F_GCR_RSTR0_TIMER2 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 \ + Mask */ +#define MXC_V_GCR_RSTR0_TIMER2_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RFU \ - (MXC_V_GCR_RSTR0_TIMER2_RFU \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */ -#define MXC_V_GCR_RSTR0_TIMER2_RESET \ +#define MXC_S_GCR_RSTR0_TIMER2_RFU \ + (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_RFU \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER2_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RESET \ - (MXC_V_GCR_RSTR0_TIMER2_RESET \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */ -#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ +#define MXC_S_GCR_RSTR0_TIMER2_RESET \ + (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE \ - (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting \ +#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE \ + (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ + << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting \ */ -#define MXC_V_GCR_RSTR0_TIMER2_BUSY \ +#define MXC_V_GCR_RSTR0_TIMER2_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER2_BUSY \ - (MXC_V_GCR_RSTR0_TIMER2_BUSY \ - << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */ +#define MXC_S_GCR_RSTR0_TIMER2_BUSY \ + (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ #define MXC_F_GCR_RSTR0_UART0 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ -#define MXC_V_GCR_RSTR0_UART0_RFU \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask \ + */ +#define MXC_V_GCR_RSTR0_UART0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */ -#define MXC_S_GCR_RSTR0_UART0_RFU \ - (MXC_V_GCR_RSTR0_UART0_RFU \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */ -#define MXC_V_GCR_RSTR0_UART0_RESET \ +#define MXC_S_GCR_RSTR0_UART0_RFU \ + (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_UART0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET \ - (MXC_V_GCR_RSTR0_UART0_RESET \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */ -#define MXC_V_GCR_RSTR0_UART0_RESET_DONE \ +#define MXC_S_GCR_RSTR0_UART0_RESET \ + (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_UART0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART0_RESET_DONE \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_UART0_BUSY \ +#define MXC_S_GCR_RSTR0_UART0_RESET_DONE \ + (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_UART0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART0_BUSY \ - (MXC_V_GCR_RSTR0_UART0_BUSY \ - << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */ +#define MXC_S_GCR_RSTR0_UART0_BUSY \ + (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ #define MXC_F_GCR_RSTR0_UART1 \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */ -#define MXC_V_GCR_RSTR0_UART1_RFU \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask \ + */ +#define MXC_V_GCR_RSTR0_UART1_RFU \ ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */ -#define MXC_S_GCR_RSTR0_UART1_RFU \ - (MXC_V_GCR_RSTR0_UART1_RFU \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */ -#define MXC_V_GCR_RSTR0_UART1_RESET \ +#define MXC_S_GCR_RSTR0_UART1_RFU \ + (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_UART1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET \ - (MXC_V_GCR_RSTR0_UART1_RESET \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */ -#define MXC_V_GCR_RSTR0_UART1_RESET_DONE \ +#define MXC_S_GCR_RSTR0_UART1_RESET \ + (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_UART1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART1_RESET_DONE \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_UART1_BUSY \ +#define MXC_S_GCR_RSTR0_UART1_RESET_DONE \ + (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_UART1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART1_BUSY \ - (MXC_V_GCR_RSTR0_UART1_BUSY \ - << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */ +#define MXC_S_GCR_RSTR0_UART1_BUSY \ + (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ -#define MXC_F_GCR_RSTR0_SPI0 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask \ +#define MXC_F_GCR_RSTR0_SPI0 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask \ */ -#define MXC_V_GCR_RSTR0_SPI0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \ +#define MXC_V_GCR_RSTR0_SPI0_RFU \ + ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SPI0_RFU \ - (MXC_V_GCR_RSTR0_SPI0_RFU \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */ -#define MXC_V_GCR_RSTR0_SPI0_RESET \ +#define MXC_S_GCR_RSTR0_SPI0_RFU \ + (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_SPI0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET \ - (MXC_V_GCR_RSTR0_SPI0_RESET \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */ -#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ +#define MXC_S_GCR_RSTR0_SPI0_RESET \ + (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SPI0_BUSY \ +#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE \ + (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_SPI0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI0_BUSY \ - (MXC_V_GCR_RSTR0_SPI0_BUSY \ - << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */ +#define MXC_S_GCR_RSTR0_SPI0_BUSY \ + (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ -#define MXC_F_GCR_RSTR0_SPI1 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask \ +#define MXC_F_GCR_RSTR0_SPI1 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask \ */ -#define MXC_V_GCR_RSTR0_SPI1_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \ +#define MXC_V_GCR_RSTR0_SPI1_RFU \ + ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SPI1_RFU \ - (MXC_V_GCR_RSTR0_SPI1_RFU \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */ -#define MXC_V_GCR_RSTR0_SPI1_RESET \ +#define MXC_S_GCR_RSTR0_SPI1_RFU \ + (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_SPI1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET \ - (MXC_V_GCR_RSTR0_SPI1_RESET \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */ -#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ +#define MXC_S_GCR_RSTR0_SPI1_RESET \ + (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SPI1_BUSY \ +#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE \ + (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_SPI1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI1_BUSY \ - (MXC_V_GCR_RSTR0_SPI1_BUSY \ - << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */ +#define MXC_S_GCR_RSTR0_SPI1_BUSY \ + (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ -#define MXC_F_GCR_RSTR0_I2C0 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask \ +#define MXC_F_GCR_RSTR0_I2C0 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask \ */ -#define MXC_V_GCR_RSTR0_I2C0_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \ +#define MXC_V_GCR_RSTR0_I2C0_RFU \ + ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \ */ -#define MXC_S_GCR_RSTR0_I2C0_RFU \ - (MXC_V_GCR_RSTR0_I2C0_RFU \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */ -#define MXC_V_GCR_RSTR0_I2C0_RESET \ +#define MXC_S_GCR_RSTR0_I2C0_RFU \ + (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_I2C0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET \ - (MXC_V_GCR_RSTR0_I2C0_RESET \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */ -#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ +#define MXC_S_GCR_RSTR0_I2C0_RESET \ + (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE \ - (MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_I2C0_BUSY \ +#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE \ + (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_I2C0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */ -#define MXC_S_GCR_RSTR0_I2C0_BUSY \ - (MXC_V_GCR_RSTR0_I2C0_BUSY \ - << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */ +#define MXC_S_GCR_RSTR0_I2C0_BUSY \ + (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ -#define MXC_F_GCR_RSTR0_RTC \ +#define MXC_F_GCR_RSTR0_RTC \ ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */ #define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */ -#define MXC_S_GCR_RSTR0_RTC_RFU \ - (MXC_V_GCR_RSTR0_RTC_RFU \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */ -#define MXC_V_GCR_RSTR0_RTC_RESET \ +#define MXC_S_GCR_RSTR0_RTC_RFU \ + (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_RTC_RESET \ ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET \ - (MXC_V_GCR_RSTR0_RTC_RESET \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */ -#define MXC_V_GCR_RSTR0_RTC_RESET_DONE \ +#define MXC_S_GCR_RSTR0_RTC_RESET \ + (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_RTC_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET_DONE \ - (MXC_V_GCR_RSTR0_RTC_RESET_DONE \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_RTC_BUSY \ - ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \ +#define MXC_S_GCR_RSTR0_RTC_RESET_DONE \ + (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_RTC_BUSY \ + ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_RTC_BUSY \ - (MXC_V_GCR_RSTR0_RTC_BUSY \ - << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */ +#define MXC_S_GCR_RSTR0_RTC_BUSY \ + (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ -#define MXC_F_GCR_RSTR0_SRST \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask \ +#define MXC_F_GCR_RSTR0_SRST \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask \ */ -#define MXC_V_GCR_RSTR0_SRST_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \ +#define MXC_V_GCR_RSTR0_SRST_RFU \ + ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SRST_RFU \ - (MXC_V_GCR_RSTR0_SRST_RFU \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */ -#define MXC_V_GCR_RSTR0_SRST_RESET \ +#define MXC_S_GCR_RSTR0_SRST_RFU \ + (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_SRST_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET \ - (MXC_V_GCR_RSTR0_SRST_RESET \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */ -#define MXC_V_GCR_RSTR0_SRST_RESET_DONE \ +#define MXC_S_GCR_RSTR0_SRST_RESET \ + (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_SRST_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_SRST_RESET_DONE \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_SRST_BUSY \ +#define MXC_S_GCR_RSTR0_SRST_RESET_DONE \ + (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_SRST_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_SRST_BUSY \ - (MXC_V_GCR_RSTR0_SRST_BUSY \ - << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */ +#define MXC_S_GCR_RSTR0_SRST_BUSY \ + (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ -#define MXC_F_GCR_RSTR0_PRST \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask \ +#define MXC_F_GCR_RSTR0_PRST \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask \ */ -#define MXC_V_GCR_RSTR0_PRST_RFU \ - ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \ +#define MXC_V_GCR_RSTR0_PRST_RFU \ + ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \ */ -#define MXC_S_GCR_RSTR0_PRST_RFU \ - (MXC_V_GCR_RSTR0_PRST_RFU \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */ -#define MXC_V_GCR_RSTR0_PRST_RESET \ +#define MXC_S_GCR_RSTR0_PRST_RFU \ + (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RFU \ + Setting */ +#define MXC_V_GCR_RSTR0_PRST_RESET \ ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET \ - (MXC_V_GCR_RSTR0_PRST_RESET \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */ -#define MXC_V_GCR_RSTR0_PRST_RESET_DONE \ +#define MXC_S_GCR_RSTR0_PRST_RESET \ + (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RESET \ + Setting */ +#define MXC_V_GCR_RSTR0_PRST_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_PRST_RESET_DONE \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR0_PRST_BUSY \ +#define MXC_S_GCR_RSTR0_PRST_RESET_DONE \ + (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_PRST_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_PRST_BUSY \ - (MXC_V_GCR_RSTR0_PRST_BUSY \ - << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */ +#define MXC_S_GCR_RSTR0_PRST_BUSY \ + (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ -#define MXC_F_GCR_RSTR0_SYSTEM \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ -#define MXC_V_GCR_RSTR0_SYSTEM_RFU \ +#define MXC_F_GCR_RSTR0_SYSTEM \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM \ + Mask */ +#define MXC_V_GCR_RSTR0_SYSTEM_RFU \ ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RFU \ - (MXC_V_GCR_RSTR0_SYSTEM_RFU \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */ -#define MXC_V_GCR_RSTR0_SYSTEM_RESET \ +#define MXC_S_GCR_RSTR0_SYSTEM_RFU \ + (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_RFU \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_SYSTEM_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RESET \ - (MXC_V_GCR_RSTR0_SYSTEM_RESET \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */ -#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ +#define MXC_S_GCR_RSTR0_SYSTEM_RESET \ + (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_RESET \ + Setting \ + */ +#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE \ - (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting \ +#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE \ + (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ + << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting \ */ -#define MXC_V_GCR_RSTR0_SYSTEM_BUSY \ +#define MXC_V_GCR_RSTR0_SYSTEM_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_BUSY \ - (MXC_V_GCR_RSTR0_SYSTEM_BUSY \ - << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */ +#define MXC_S_GCR_RSTR0_SYSTEM_BUSY \ + (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_BUSY \ + Setting \ + */ /** * Clock Control. */ #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ -#define MXC_F_GCR_CLKCN_PSC \ +#define MXC_F_GCR_CLKCN_PSC \ ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ -#define MXC_V_GCR_CLKCN_PSC_DIV1 \ - ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \ +#define MXC_V_GCR_CLKCN_PSC_DIV1 \ + ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV1 \ - (MXC_V_GCR_CLKCN_PSC_DIV1 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV2 \ - ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \ +#define MXC_S_GCR_CLKCN_PSC_DIV1 \ + (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV1 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV2 \ + ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV2 \ - (MXC_V_GCR_CLKCN_PSC_DIV2 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV4 \ - ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \ +#define MXC_S_GCR_CLKCN_PSC_DIV2 \ + (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV2 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV4 \ + ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV4 \ - (MXC_V_GCR_CLKCN_PSC_DIV4 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV8 \ - ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \ +#define MXC_S_GCR_CLKCN_PSC_DIV4 \ + (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV4 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV8 \ + ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV8 \ - (MXC_V_GCR_CLKCN_PSC_DIV8 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV16 \ +#define MXC_S_GCR_CLKCN_PSC_DIV8 \ + (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV8 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV16 \ ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV16 \ - (MXC_V_GCR_CLKCN_PSC_DIV16 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV32 \ +#define MXC_S_GCR_CLKCN_PSC_DIV16 \ + (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV16 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV32 \ ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV32 \ - (MXC_V_GCR_CLKCN_PSC_DIV32 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV64 \ +#define MXC_S_GCR_CLKCN_PSC_DIV32 \ + (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV32 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV64 \ ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV64 \ - (MXC_V_GCR_CLKCN_PSC_DIV64 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */ -#define MXC_V_GCR_CLKCN_PSC_DIV128 \ +#define MXC_S_GCR_CLKCN_PSC_DIV64 \ + (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV64 \ + Setting */ +#define MXC_V_GCR_CLKCN_PSC_DIV128 \ ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV128 \ - (MXC_V_GCR_CLKCN_PSC_DIV128 \ - << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV128 \ + (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV128 \ + Setting */ #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ -#define MXC_F_GCR_CLKCN_CLKSEL \ - ((uint32_t)(0x7UL \ - << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ -#define MXC_V_GCR_CLKCN_CLKSEL_HIRC \ +#define MXC_F_GCR_CLKCN_CLKSEL \ + ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL \ + Mask */ +#define MXC_V_GCR_CLKCN_CLKSEL_HIRC \ ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ - (MXC_V_GCR_CLKCN_CLKSEL_HIRC \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ -#define MXC_V_GCR_CLKCN_CLKSEL_NANORING \ +#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ + (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_HIRC \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_CLKSEL_NANORING \ ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_NANORING \ - (MXC_V_GCR_CLKCN_CLKSEL_NANORING \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */ -#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ +#define MXC_S_GCR_CLKCN_CLKSEL_NANORING \ + (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_NANORING \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN \ - (MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ - << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */ +#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN \ + (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_HFXIN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ #define MXC_F_GCR_CLKCN_CKRDY \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ -#define MXC_V_GCR_CLKCN_CKRDY_BUSY \ + ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask \ + */ +#define MXC_V_GCR_CLKCN_CKRDY_BUSY \ ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ - (MXC_V_GCR_CLKCN_CKRDY_BUSY \ - << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */ -#define MXC_V_GCR_CLKCN_CKRDY_READY \ +#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ + (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ + CLKCN_CKRDY_BUSY \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_CKRDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_READY \ - (MXC_V_GCR_CLKCN_CKRDY_READY \ - << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */ +#define MXC_S_GCR_CLKCN_CKRDY_READY \ + (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ + CLKCN_CKRDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ -#define MXC_F_GCR_CLKCN_X32K_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */ -#define MXC_V_GCR_CLKCN_X32K_EN_DIS \ +#define MXC_F_GCR_CLKCN_X32K_EN \ + ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN \ + Mask */ +#define MXC_V_GCR_CLKCN_X32K_EN_DIS \ ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_DIS \ - (MXC_V_GCR_CLKCN_X32K_EN_DIS \ - << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */ -#define MXC_V_GCR_CLKCN_X32K_EN_EN \ +#define MXC_S_GCR_CLKCN_X32K_EN_DIS \ + (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ + CLKCN_X32K_EN_DIS \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_X32K_EN_EN \ ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_EN \ - (MXC_V_GCR_CLKCN_X32K_EN_EN \ - << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */ +#define MXC_S_GCR_CLKCN_X32K_EN_EN \ + (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ + CLKCN_X32K_EN_EN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ -#define MXC_F_GCR_CLKCN_HIRC_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ -#define MXC_V_GCR_CLKCN_HIRC_EN_DIS \ +#define MXC_F_GCR_CLKCN_HIRC_EN \ + ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN \ + Mask */ +#define MXC_V_GCR_CLKCN_HIRC_EN_DIS \ ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ - (MXC_V_GCR_CLKCN_HIRC_EN_DIS \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */ -#define MXC_V_GCR_CLKCN_HIRC_EN_EN \ +#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ + (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ + CLKCN_HIRC_EN_DIS \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_HIRC_EN_EN \ ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ - (MXC_V_GCR_CLKCN_HIRC_EN_EN \ - << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */ +#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ + (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ + CLKCN_HIRC_EN_EN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ -#define MXC_F_GCR_CLKCN_X32K_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */ -#define MXC_V_GCR_CLKCN_X32K_RDY_NOT \ +#define MXC_F_GCR_CLKCN_X32K_RDY \ + ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< \ + CLKCN_X32K_RDY \ + Mask */ +#define MXC_V_GCR_CLKCN_X32K_RDY_NOT \ ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_NOT \ - (MXC_V_GCR_CLKCN_X32K_RDY_NOT \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */ -#define MXC_V_GCR_CLKCN_X32K_RDY_READY \ +#define MXC_S_GCR_CLKCN_X32K_RDY_NOT \ + (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ + CLKCN_X32K_RDY_NOT \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_X32K_RDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_READY \ - (MXC_V_GCR_CLKCN_X32K_RDY_READY \ - << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */ +#define MXC_S_GCR_CLKCN_X32K_RDY_READY \ + (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ + CLKCN_X32K_RDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ -#define MXC_F_GCR_CLKCN_HIRC_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ -#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ +#define MXC_F_GCR_CLKCN_HIRC_RDY \ + ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< \ + CLKCN_HIRC_RDY \ + Mask */ +#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ - (MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */ -#define MXC_V_GCR_CLKCN_HIRC_RDY_READY \ +#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ + (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ + CLKCN_HIRC_RDY_NOT \ + Setting \ + */ +#define MXC_V_GCR_CLKCN_HIRC_RDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ - (MXC_V_GCR_CLKCN_HIRC_RDY_READY \ - << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */ +#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ + (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ + CLKCN_HIRC_RDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ -#define MXC_F_GCR_CLKCN_LIRC8K_RDY \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY \ +#define MXC_F_GCR_CLKCN_LIRC8K_RDY \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY \ Mask */ -#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ +#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT \ - (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting \ +#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT \ + (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT \ + << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting \ */ -#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ +#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY \ - (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ - << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY \ +#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY \ + (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY \ + << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY \ Setting */ /** * Power Management. */ #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ -#define MXC_F_GCR_PM_MODE \ +#define MXC_F_GCR_PM_MODE \ ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ -#define MXC_V_GCR_PM_MODE_ACTIVE \ - ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value \ +#define MXC_V_GCR_PM_MODE_ACTIVE \ + ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value \ */ -#define MXC_S_GCR_PM_MODE_ACTIVE \ - (MXC_V_GCR_PM_MODE_ACTIVE \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ -#define MXC_V_GCR_PM_MODE_SHUTDOWN \ +#define MXC_S_GCR_PM_MODE_ACTIVE \ + (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< \ + PM_MODE_ACTIVE \ + Setting */ +#define MXC_V_GCR_PM_MODE_SHUTDOWN \ ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ -#define MXC_S_GCR_PM_MODE_SHUTDOWN \ - (MXC_V_GCR_PM_MODE_SHUTDOWN \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ -#define MXC_V_GCR_PM_MODE_BACKUP \ - ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \ +#define MXC_S_GCR_PM_MODE_SHUTDOWN \ + (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< \ + PM_MODE_SHUTDOWN \ + Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP \ + ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \ */ -#define MXC_S_GCR_PM_MODE_BACKUP \ - (MXC_V_GCR_PM_MODE_BACKUP \ - << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ +#define MXC_S_GCR_PM_MODE_BACKUP \ + (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< \ + PM_MODE_BACKUP \ + Setting */ #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ #define MXC_F_GCR_PM_GPIOWKEN \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ -#define MXC_V_GCR_PM_GPIOWKEN_DIS \ + ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask \ + */ +#define MXC_V_GCR_PM_GPIOWKEN_DIS \ ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ -#define MXC_S_GCR_PM_GPIOWKEN_DIS \ - (MXC_V_GCR_PM_GPIOWKEN_DIS \ - << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */ -#define MXC_V_GCR_PM_GPIOWKEN_EN \ - ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \ +#define MXC_S_GCR_PM_GPIOWKEN_DIS \ + (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ + PM_GPIOWKEN_DIS \ + Setting */ +#define MXC_V_GCR_PM_GPIOWKEN_EN \ + ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \ */ -#define MXC_S_GCR_PM_GPIOWKEN_EN \ - (MXC_V_GCR_PM_GPIOWKEN_EN \ - << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */ +#define MXC_S_GCR_PM_GPIOWKEN_EN \ + (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ + PM_GPIOWKEN_EN \ + Setting */ #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ -#define MXC_F_GCR_PM_RTCWKEN \ - ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask \ +#define MXC_F_GCR_PM_RTCWKEN \ + ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask \ */ -#define MXC_V_GCR_PM_RTCWKEN_DIS \ - ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \ +#define MXC_V_GCR_PM_RTCWKEN_DIS \ + ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \ */ -#define MXC_S_GCR_PM_RTCWKEN_DIS \ - (MXC_V_GCR_PM_RTCWKEN_DIS \ - << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */ +#define MXC_S_GCR_PM_RTCWKEN_DIS \ + (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< \ + PM_RTCWKEN_DIS \ + Setting */ #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */ #define MXC_S_GCR_PM_RTCWKEN_EN \ - (MXC_V_GCR_PM_RTCWKEN_EN \ - << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */ + (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< \ + PM_RTCWKEN_EN \ + Setting */ #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ -#define MXC_F_GCR_PM_HIRCPD \ +#define MXC_F_GCR_PM_HIRCPD \ ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ -#define MXC_V_GCR_PM_HIRCPD_ACTIVE \ +#define MXC_V_GCR_PM_HIRCPD_ACTIVE \ ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ -#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ - (MXC_V_GCR_PM_HIRCPD_ACTIVE \ - << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */ -#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ +#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ + (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< \ + PM_HIRCPD_ACTIVE \ + Setting */ +#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ -#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ - (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ - << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */ +#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ + (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< \ + PM_HIRCPD_DEEPSLEEP \ + Setting \ + */ /** * Peripheral Clock Divider. */ #define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */ -#define MXC_F_GCR_PCKDIV_AONCD \ - ((uint32_t)(0x3UL \ - << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ +#define MXC_F_GCR_PCKDIV_AONCD \ + ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD \ + Mask */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_4 \ + Setting \ + */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_8 \ + Setting \ + */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ -#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_16 \ + Setting \ + */ +#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ - << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_32 \ + Setting \ + */ /** * Peripheral Clock Disable. */ #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ -#define MXC_F_GCR_PERCKCN0_GPIO0D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_GPIO0D_EN \ +#define MXC_F_GCR_PERCKCN0_GPIO0D \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_GPIO0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ - (MXC_V_GCR_PERCKCN0_GPIO0D_EN \ - << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ +#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ + (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ + PERCKCN0_GPIO0D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ - (MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ - << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ + (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ + PERCKCN0_GPIO0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ -#define MXC_F_GCR_PERCKCN0_DMAD \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ -#define MXC_V_GCR_PERCKCN0_DMAD_EN \ +#define MXC_F_GCR_PERCKCN0_DMAD \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD \ + Mask */ +#define MXC_V_GCR_PERCKCN0_DMAD_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_EN \ - (MXC_V_GCR_PERCKCN0_DMAD_EN \ - << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */ -#define MXC_V_GCR_PERCKCN0_DMAD_DIS \ +#define MXC_S_GCR_PERCKCN0_DMAD_EN \ + (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ + PERCKCN0_DMAD_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_DMAD_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_DIS \ - (MXC_V_GCR_PERCKCN0_DMAD_DIS \ - << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_DMAD_DIS \ + (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ + PERCKCN0_DMAD_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ -#define MXC_F_GCR_PERCKCN0_SPI0D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */ -#define MXC_V_GCR_PERCKCN0_SPI0D_EN \ +#define MXC_F_GCR_PERCKCN0_SPI0D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< \ + PERCKCN0_SPI0D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_SPI0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_EN \ - (MXC_V_GCR_PERCKCN0_SPI0D_EN \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_SPI0D_DIS \ +#define MXC_S_GCR_PERCKCN0_SPI0D_EN \ + (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ + PERCKCN0_SPI0D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_SPI0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI0D_DIS \ - << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_SPI0D_DIS \ + (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ + PERCKCN0_SPI0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ -#define MXC_F_GCR_PERCKCN0_SPI1D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ -#define MXC_V_GCR_PERCKCN0_SPI1D_EN \ +#define MXC_F_GCR_PERCKCN0_SPI1D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< \ + PERCKCN0_SPI1D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_SPI1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_EN \ - (MXC_V_GCR_PERCKCN0_SPI1D_EN \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_SPI1D_DIS \ +#define MXC_S_GCR_PERCKCN0_SPI1D_EN \ + (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ + PERCKCN0_SPI1D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_SPI1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI1D_DIS \ - << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_SPI1D_DIS \ + (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ + PERCKCN0_SPI1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ -#define MXC_F_GCR_PERCKCN0_UART0D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_UART0D_EN \ +#define MXC_F_GCR_PERCKCN0_UART0D \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_UART0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_EN \ - (MXC_V_GCR_PERCKCN0_UART0D_EN \ - << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_UART0D_DIS \ +#define MXC_S_GCR_PERCKCN0_UART0D_EN \ + (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ + PERCKCN0_UART0D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_UART0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_DIS \ - (MXC_V_GCR_PERCKCN0_UART0D_DIS \ - << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_UART0D_DIS \ + (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ + PERCKCN0_UART0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ -#define MXC_F_GCR_PERCKCN0_UART1D \ - ((uint32_t)( \ - 0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D \ - Mask */ -#define MXC_V_GCR_PERCKCN0_UART1D_EN \ +#define MXC_F_GCR_PERCKCN0_UART1D \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_UART1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_EN \ - (MXC_V_GCR_PERCKCN0_UART1D_EN \ - << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_UART1D_DIS \ +#define MXC_S_GCR_PERCKCN0_UART1D_EN \ + (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ + PERCKCN0_UART1D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_UART1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_DIS \ - (MXC_V_GCR_PERCKCN0_UART1D_DIS \ - << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_UART1D_DIS \ + (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ + PERCKCN0_UART1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ -#define MXC_F_GCR_PERCKCN0_I2C0D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ -#define MXC_V_GCR_PERCKCN0_I2C0D_EN \ +#define MXC_F_GCR_PERCKCN0_I2C0D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< \ + PERCKCN0_I2C0D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_I2C0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_EN \ - (MXC_V_GCR_PERCKCN0_I2C0D_EN \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_I2C0D_DIS \ +#define MXC_S_GCR_PERCKCN0_I2C0D_EN \ + (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ + PERCKCN0_I2C0D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_I2C0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C0D_DIS \ - << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_I2C0D_DIS \ + (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ + PERCKCN0_I2C0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ -#define MXC_F_GCR_PERCKCN0_T0D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */ -#define MXC_V_GCR_PERCKCN0_T0D_EN \ +#define MXC_F_GCR_PERCKCN0_T0D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_T0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T0D_EN \ - (MXC_V_GCR_PERCKCN0_T0D_EN \ - << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T0D_DIS \ +#define MXC_S_GCR_PERCKCN0_T0D_EN \ + (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ + PERCKCN0_T0D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_T0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T0D_DIS \ - (MXC_V_GCR_PERCKCN0_T0D_DIS \ - << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_T0D_DIS \ + (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ + PERCKCN0_T0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ -#define MXC_F_GCR_PERCKCN0_T1D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */ -#define MXC_V_GCR_PERCKCN0_T1D_EN \ +#define MXC_F_GCR_PERCKCN0_T1D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_T1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T1D_EN \ - (MXC_V_GCR_PERCKCN0_T1D_EN \ - << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T1D_DIS \ +#define MXC_S_GCR_PERCKCN0_T1D_EN \ + (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ + PERCKCN0_T1D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_T1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T1D_DIS \ - (MXC_V_GCR_PERCKCN0_T1D_DIS \ - << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_T1D_DIS \ + (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ + PERCKCN0_T1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ -#define MXC_F_GCR_PERCKCN0_T2D \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */ -#define MXC_V_GCR_PERCKCN0_T2D_EN \ +#define MXC_F_GCR_PERCKCN0_T2D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_T2D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T2D_EN \ - (MXC_V_GCR_PERCKCN0_T2D_EN \ - << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_T2D_DIS \ +#define MXC_S_GCR_PERCKCN0_T2D_EN \ + (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ + PERCKCN0_T2D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_T2D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T2D_DIS \ - (MXC_V_GCR_PERCKCN0_T2D_DIS \ - << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_T2D_DIS \ + (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ + PERCKCN0_T2D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ -#define MXC_F_GCR_PERCKCN0_I2C1D \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */ -#define MXC_V_GCR_PERCKCN0_I2C1D_EN \ +#define MXC_F_GCR_PERCKCN0_I2C1D \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< \ + PERCKCN0_I2C1D \ + Mask */ +#define MXC_V_GCR_PERCKCN0_I2C1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_EN \ - (MXC_V_GCR_PERCKCN0_I2C1D_EN \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */ -#define MXC_V_GCR_PERCKCN0_I2C1D_DIS \ +#define MXC_S_GCR_PERCKCN0_I2C1D_EN \ + (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ + PERCKCN0_I2C1D_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN0_I2C1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C1D_DIS \ - << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */ +#define MXC_S_GCR_PERCKCN0_I2C1D_DIS \ + (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ + PERCKCN0_I2C1D_DIS \ + Setting \ + */ /** * Memory Clock Control Register. */ #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ #define MXC_F_GCR_MEMCKCN_FWS \ - ((uint32_t)( \ - 0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ + ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask \ + */ #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM0LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ +#define MXC_F_GCR_MEMCKCN_SYSRAM0LS \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< \ + MEMCKCN_SYSRAM0LS \ + Mask */ +#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE \ +#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE \ + << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE \ Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ +#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< \ - MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ +#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< \ + MEMCKCN_SYSRAM0LS_LIGHT_SLEEP \ Setting */ #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM1LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ +#define MXC_F_GCR_MEMCKCN_SYSRAM1LS \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< \ + MEMCKCN_SYSRAM1LS \ + Mask */ +#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE \ +#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE \ + << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE \ Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ +#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< \ - MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ +#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< \ + MEMCKCN_SYSRAM1LS_LIGHT_SLEEP \ Setting */ #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM2LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ +#define MXC_F_GCR_MEMCKCN_SYSRAM2LS \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< \ + MEMCKCN_SYSRAM2LS \ + Mask */ +#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE \ +#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE \ + << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE \ Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ +#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< \ - MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ +#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< \ + MEMCKCN_SYSRAM2LS_LIGHT_SLEEP \ Setting */ #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */ -#define MXC_F_GCR_MEMCKCN_SYSRAM3LS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS \ - Mask */ -#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ +#define MXC_F_GCR_MEMCKCN_SYSRAM3LS \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< \ + MEMCKCN_SYSRAM3LS \ + Mask */ +#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE \ +#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE \ + << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE \ Setting */ -#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ +#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< \ - MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ +#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< \ + MEMCKCN_SYSRAM3LS_LIGHT_SLEEP \ Setting */ #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */ -#define MXC_F_GCR_MEMCKCN_ICACHELS \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS \ +#define MXC_F_GCR_MEMCKCN_ICACHELS \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS \ Mask */ -#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ +#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */ -#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE \ - (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE \ +#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE \ + (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE \ + << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE \ Setting */ -#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ +#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */ -#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ - (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ - << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP \ +#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ + (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP \ + << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP \ Setting */ /** * Memory Zeroize Control. */ #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ -#define MXC_F_GCR_MEMZCN_SRAM0Z \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ -#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ +#define MXC_F_GCR_MEMZCN_SRAM0Z \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z \ + Mask */ +#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ - (MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */ -#define MXC_V_GCR_MEMZCN_SRAM0Z_START \ +#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ + (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ + MEMZCN_SRAM0Z_NOP \ + Setting \ + */ +#define MXC_V_GCR_MEMZCN_SRAM0Z_START \ ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ - (MXC_V_GCR_MEMZCN_SRAM0Z_START \ - << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */ +#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ + (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ + MEMZCN_SRAM0Z_START \ + Setting \ + */ #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */ -#define MXC_F_GCR_MEMZCN_ICACHEZ \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ -#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ +#define MXC_F_GCR_MEMZCN_ICACHEZ \ + ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< \ + MEMZCN_ICACHEZ \ + Mask */ +#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP \ - (MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */ -#define MXC_V_GCR_MEMZCN_ICACHEZ_START \ +#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP \ + (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ + MEMZCN_ICACHEZ_NOP \ + Setting \ + */ +#define MXC_V_GCR_MEMZCN_ICACHEZ_START \ ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_START \ - (MXC_V_GCR_MEMZCN_ICACHEZ_START \ - << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */ +#define MXC_S_GCR_MEMZCN_ICACHEZ_START \ + (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ + MEMZCN_ICACHEZ_START \ + Setting \ + */ /** * System Status Register. */ #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */ -#define MXC_F_GCR_SYSST_ICECLOCK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */ -#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \ +#define MXC_F_GCR_SYSST_ICECLOCK \ + ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< \ + SYSST_ICECLOCK \ + Mask */ +#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \ ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */ #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED \ (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED \ << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting \ */ -#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ +#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */ -#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED \ - (MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ - << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting \ +#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED \ + (MXC_V_GCR_SYSST_ICECLOCK_LOCKED \ + << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting \ */ #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ -#define MXC_F_GCR_SYSST_CODEINTERR \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR \ +#define MXC_F_GCR_SYSST_CODEINTERR \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR \ Mask */ -#define MXC_V_GCR_SYSST_CODEINTERR_NORM \ +#define MXC_V_GCR_SYSST_CODEINTERR_NORM \ ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */ #define MXC_S_GCR_SYSST_CODEINTERR_NORM \ (MXC_V_GCR_SYSST_CODEINTERR_NORM \ << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting \ */ -#define MXC_V_GCR_SYSST_CODEINTERR_CODE \ +#define MXC_V_GCR_SYSST_CODEINTERR_CODE \ ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */ #define MXC_S_GCR_SYSST_CODEINTERR_CODE \ (MXC_V_GCR_SYSST_CODEINTERR_CODE \ @@ -1213,153 +1409,174 @@ typedef struct { */ #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ -#define MXC_F_GCR_SYSST_SCMEMF \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ -#define MXC_V_GCR_SYSST_SCMEMF_NORM \ +#define MXC_F_GCR_SYSST_SCMEMF \ + ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF \ + Mask */ +#define MXC_V_GCR_SYSST_SCMEMF_NORM \ ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */ -#define MXC_S_GCR_SYSST_SCMEMF_NORM \ - (MXC_V_GCR_SYSST_SCMEMF_NORM \ - << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */ -#define MXC_V_GCR_SYSST_SCMEMF_MEMORY \ +#define MXC_S_GCR_SYSST_SCMEMF_NORM \ + (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ + SYSST_SCMEMF_NORM \ + Setting \ + */ +#define MXC_V_GCR_SYSST_SCMEMF_MEMORY \ ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */ -#define MXC_S_GCR_SYSST_SCMEMF_MEMORY \ - (MXC_V_GCR_SYSST_SCMEMF_MEMORY \ - << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */ +#define MXC_S_GCR_SYSST_SCMEMF_MEMORY \ + (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ + SYSST_SCMEMF_MEMORY \ + Setting \ + */ /** * Reset Register. */ #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */ -#define MXC_F_GCR_RSTR1_I2C1 \ - ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask \ +#define MXC_F_GCR_RSTR1_I2C1 \ + ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask \ */ -#define MXC_V_GCR_RSTR1_I2C1_RESET \ +#define MXC_V_GCR_RSTR1_I2C1_RESET \ ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET \ - (MXC_V_GCR_RSTR1_I2C1_RESET \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */ -#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ +#define MXC_S_GCR_RSTR1_I2C1_RESET \ + (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_RESET \ + Setting */ +#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE \ - (MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */ -#define MXC_V_GCR_RSTR1_I2C1_BUSY \ +#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE \ + (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_RESET_DONE \ + Setting \ + */ +#define MXC_V_GCR_RSTR1_I2C1_BUSY \ ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */ -#define MXC_S_GCR_RSTR1_I2C1_BUSY \ - (MXC_V_GCR_RSTR1_I2C1_BUSY \ - << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */ +#define MXC_S_GCR_RSTR1_I2C1_BUSY \ + (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_BUSY \ + Setting */ /** * Peripheral Clock Disable. */ #define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */ -#define MXC_F_GCR_PERCKCN1_FLCD \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */ -#define MXC_V_GCR_PERCKCN1_FLCD_EN \ +#define MXC_F_GCR_PERCKCN1_FLCD \ + ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD \ + Mask */ +#define MXC_V_GCR_PERCKCN1_FLCD_EN \ ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_EN \ - (MXC_V_GCR_PERCKCN1_FLCD_EN \ - << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */ -#define MXC_V_GCR_PERCKCN1_FLCD_DIS \ +#define MXC_S_GCR_PERCKCN1_FLCD_EN \ + (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ + PERCKCN1_FLCD_EN \ + Setting \ + */ +#define MXC_V_GCR_PERCKCN1_FLCD_DIS \ ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_DIS \ - (MXC_V_GCR_PERCKCN1_FLCD_DIS \ - << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */ +#define MXC_S_GCR_PERCKCN1_FLCD_DIS \ + (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ + PERCKCN1_FLCD_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ -#define MXC_F_GCR_PERCKCN1_ICACHED \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED \ +#define MXC_F_GCR_PERCKCN1_ICACHED \ + ((uint32_t)(0x1UL \ + << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED \ Mask */ -#define MXC_V_GCR_PERCKCN1_ICACHED_EN \ +#define MXC_V_GCR_PERCKCN1_ICACHED_EN \ ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */ -#define MXC_S_GCR_PERCKCN1_ICACHED_EN \ - (MXC_V_GCR_PERCKCN1_ICACHED_EN \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting \ +#define MXC_S_GCR_PERCKCN1_ICACHED_EN \ + (MXC_V_GCR_PERCKCN1_ICACHED_EN \ + << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting \ */ -#define MXC_V_GCR_PERCKCN1_ICACHED_DIS \ +#define MXC_V_GCR_PERCKCN1_ICACHED_DIS \ ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */ -#define MXC_S_GCR_PERCKCN1_ICACHED_DIS \ - (MXC_V_GCR_PERCKCN1_ICACHED_DIS \ - << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting \ +#define MXC_S_GCR_PERCKCN1_ICACHED_DIS \ + (MXC_V_GCR_PERCKCN1_ICACHED_DIS \ + << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting \ */ /** * Event Enable Register. */ #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ -#define MXC_F_GCR_EVTEN_DMAEVENT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ +#define MXC_F_GCR_EVTEN_DMAEVENT \ + ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< \ + EVTEN_DMAEVENT \ + Mask */ #define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */ -#define MXC_F_GCR_EVTEN_RXEVENT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */ +#define MXC_F_GCR_EVTEN_RXEVENT \ + ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT \ + Mask */ /** * Revision Register. */ #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ -#define MXC_F_GCR_REVISION_REVISION \ - ((uint32_t)( \ - 0xFFFFUL \ - << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION \ - Mask */ +#define MXC_F_GCR_REVISION_REVISION \ + ((uint32_t)(0xFFFFUL \ + << MXC_F_GCR_REVISION_REVISION_POS)) /**< \ + REVISION_REVISION \ + Mask */ /** * System Status Interrupt Enable Register. */ #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ -#define MXC_F_GCR_SYSSIE_ICEULIE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ -#define MXC_V_GCR_SYSSIE_ICEULIE_DIS \ +#define MXC_F_GCR_SYSSIE_ICEULIE \ + ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< \ + SYSSIE_ICEULIE \ + Mask */ +#define MXC_V_GCR_SYSSIE_ICEULIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ - (MXC_V_GCR_SYSSIE_ICEULIE_DIS \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_ICEULIE_EN \ +#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ + (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ + SYSSIE_ICEULIE_DIS \ + Setting \ + */ +#define MXC_V_GCR_SYSSIE_ICEULIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ - (MXC_V_GCR_SYSSIE_ICEULIE_EN \ - << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */ +#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ + (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ + SYSSIE_ICEULIE_EN \ + Setting \ + */ #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ -#define MXC_F_GCR_SYSSIE_CIEIE \ - ((uint32_t)(0x1UL \ - << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */ -#define MXC_V_GCR_SYSSIE_CIEIE_DIS \ +#define MXC_F_GCR_SYSSIE_CIEIE \ + ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE \ + Mask */ +#define MXC_V_GCR_SYSSIE_CIEIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_DIS \ - (MXC_V_GCR_SYSSIE_CIEIE_DIS \ - << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_CIEIE_EN \ +#define MXC_S_GCR_SYSSIE_CIEIE_DIS \ + (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ + SYSSIE_CIEIE_DIS \ + Setting \ + */ +#define MXC_V_GCR_SYSSIE_CIEIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_EN \ - (MXC_V_GCR_SYSSIE_CIEIE_EN \ - << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */ +#define MXC_S_GCR_SYSSIE_CIEIE_EN \ + (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ + SYSSIE_CIEIE_EN \ + Setting \ + */ #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ -#define MXC_F_GCR_SYSSIE_SCMFIE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */ -#define MXC_V_GCR_SYSSIE_SCMFIE_DIS \ +#define MXC_F_GCR_SYSSIE_SCMFIE \ + ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE \ + Mask */ +#define MXC_V_GCR_SYSSIE_SCMFIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_DIS \ - (MXC_V_GCR_SYSSIE_SCMFIE_DIS \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */ -#define MXC_V_GCR_SYSSIE_SCMFIE_EN \ +#define MXC_S_GCR_SYSSIE_SCMFIE_DIS \ + (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ + SYSSIE_SCMFIE_DIS \ + Setting \ + */ +#define MXC_V_GCR_SYSSIE_SCMFIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_EN \ - (MXC_V_GCR_SYSSIE_SCMFIE_EN \ - << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */ +#define MXC_S_GCR_SYSSIE_SCMFIE_EN \ + (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ + SYSSIE_SCMFIE_EN \ + Setting \ + */ #endif /* _GCR_REGS_H_ */ -- cgit v1.2.1 From fa6bd7bbca547a1fcd7d936aeb3a6b25ecc5f19d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:10 -0600 Subject: chip/mchp/config_flash_layout.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie90e8d4632102973a234e1d3e938be776386b3a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729287 Reviewed-by: Jeremy Bettis --- chip/mchp/config_flash_layout.h | 60 +++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 32 deletions(-) diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h index caa1e204e0..cd0d115473 100644 --- a/chip/mchp/config_flash_layout.h +++ b/chip/mchp/config_flash_layout.h @@ -16,8 +16,8 @@ /* Non-memmory mapped, external SPI */ #define CONFIG_EXTERNAL_STORAGE -#undef CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE +#undef CONFIG_MAPPED_STORAGE +#undef CONFIG_FLASH_PSTATE #define CONFIG_SPI_FLASH /* @@ -33,32 +33,30 @@ * EC_RO and EC_RW padded sizes from the build are 188KB each. * Storage size is 1/2 flash size. */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 /* Lower 256KB of flash is protected region */ #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 /* Writable storage for EC_RW starts at 256KB */ #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 /* Writeable storage is 256KB */ -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 - +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 /* Loader resides at the beginning of program memory */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0x1000 +#define CONFIG_LOADER_MEM_OFF 0 +#define CONFIG_LOADER_SIZE 0x1000 /* Write protect Loader and RO Image */ -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF /* * Write protect LFW + EC_RO */ -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * RO / RW images follow the loader in program memory. Either RO or RW * image will be loaded -- both cannot be loaded at the same time. */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) +#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE) /* * Total SRAM and the amount allocated for data are specified * by CONFIG_MEC_SRAM_SIZE and CONFIG_RAM_SIZE in config_chip.h @@ -69,20 +67,20 @@ * and must be located on a erase block boundary. !!! */ #if (CONFIG_MEC_SRAM_SIZE > CONFIG_EC_PROTECTED_STORAGE_SIZE) -#define CONFIG_RO_SIZE (CONFIG_EC_PROTECTED_STORAGE_SIZE - \ - CONFIG_LOADER_SIZE - 0x2000) +#define CONFIG_RO_SIZE \ + (CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_LOADER_SIZE - 0x2000) #else -#define CONFIG_RO_SIZE (CONFIG_MEC_SRAM_SIZE - \ - CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE) +#define CONFIG_RO_SIZE \ + (CONFIG_MEC_SRAM_SIZE - CONFIG_RAM_SIZE - CONFIG_LOADER_SIZE) #endif -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF /* * NOTE: CONFIG_RW_SIZE is passed to the SPI image generation script by * chip build.mk * LFW requires CONFIG_RW_SIZE is equal to CONFIG_RO_SIZE !!! */ -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_SIZE CONFIG_RO_SIZE /* * WP region consists of first half of SPI containing TAGs at beginning @@ -104,7 +102,7 @@ * greater aligned boundaries. */ -#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0 #if defined(CHIP_FAMILY_MEC172X) /* * Changed to 0x140 original 0xc0 which is incorrect @@ -123,33 +121,31 @@ * 0x40000 - 0x7ffff = EC_RW padded with 0xFF * To EC the "header" is one 4KB chunk at offset 0 */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x1000 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x1000 #elif defined(CHIP_FAMILY_MEC152X) -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140 #elif defined(CHIP_FAMILY_MEC170X) -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 #else #error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid" #endif -#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0 +#define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0 /* Loader / lfw image immediately follows the boot header on SPI */ -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) +#define CONFIG_LOADER_STORAGE_OFF \ + (CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE) /* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) +#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE) /* * RW image starts at offset 0 of second half of SPI. * RW Header not needed. */ -#define CONFIG_RW_STORAGE_OFF (CONFIG_RW_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_RW_BOOT_HEADER_STORAGE_SIZE) - +#define CONFIG_RW_STORAGE_OFF \ + (CONFIG_RW_BOOT_HEADER_STORAGE_OFF + CONFIG_RW_BOOT_HEADER_STORAGE_SIZE) #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ -- cgit v1.2.1 From 5fffd06a2eefbf1a457e02da985f31de76cfdf4a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:46 -0600 Subject: zephyr/app/ec/ec_app_main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic61005fe4bbfbe613ea88c8d8b0940dc137fc30f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730667 Reviewed-by: Jeremy Bettis --- zephyr/app/ec/ec_app_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/app/ec/ec_app_main.c b/zephyr/app/ec/ec_app_main.c index 17c6eeb697..414ed65e9c 100644 --- a/zephyr/app/ec/ec_app_main.c +++ b/zephyr/app/ec/ec_app_main.c @@ -39,7 +39,7 @@ void ec_app_main(void) system_print_banner(); if (IS_ENABLED(CONFIG_PLATFORM_EC_WATCHDOG) && - !IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) { + !IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) { watchdog_init(); } -- cgit v1.2.1 From 08883e9b4175b726e037d9814497abd65f6dc894 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:58 -0600 Subject: baseboard/intelrvp/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d5e4f914425999573167b430787347b4184ab8d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727895 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/baseboard.h | 45 ++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 9b497568e7..035d7150ec 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -12,13 +12,13 @@ #include "stdbool.h" #ifdef VARIANT_INTELRVP_EC_IT8320 - #include "ite_ec.h" +#include "ite_ec.h" #elif defined(VARIANT_INTELRVP_EC_MCHP) - #include "mchp_ec.h" +#include "mchp_ec.h" #elif defined(VARIANT_INTELRVP_EC_NPCX) - #include "npcx_ec.h" +#include "npcx_ec.h" #else - #error "Define EC chip variant" +#error "Define EC chip variant" #endif /* @@ -27,7 +27,7 @@ */ #define CONFIG_SYSTEM_UNLOCKED -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE /* @@ -51,7 +51,7 @@ #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 /* Battery */ #define CONFIG_BATTERY_CUT_OFF @@ -66,7 +66,7 @@ #define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CHARGER_SENSE_RESISTOR 5 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_TRICKLE_CHARGING @@ -75,8 +75,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Keyboard */ @@ -109,7 +109,7 @@ /* USB MUX */ #ifdef CONFIG_USB_MUX_VIRTUAL - #define CONFIG_HOSTCMD_LOCATE_CHIP +#define CONFIG_HOSTCMD_LOCATE_CHIP #endif #define CONFIG_USBC_SS_MUX @@ -152,13 +152,13 @@ /* Temperature sensor */ #ifdef CONFIG_TEMP_SENSOR - #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B - #define CONFIG_TEMP_SENSOR_POWER - #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A - #define CONFIG_THERMISTOR - #define CONFIG_THROTTLE_AP +#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B +#define CONFIG_TEMP_SENSOR_POWER +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define CONFIG_THERMISTOR +#define CONFIG_THROTTLE_AP #ifdef CONFIG_PECI - #define CONFIG_PECI_COMMON +#define CONFIG_PECI_COMMON #endif /* CONFIG_PECI */ #endif /* CONFIG_TEMP_SENSOR */ @@ -177,10 +177,7 @@ FORWARD_DECLARE_ENUM(tcpc_rp_value); /* PWM channels */ -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT }; /* FAN channels */ enum fan_channel { @@ -211,13 +208,13 @@ enum temp_sensor_id { }; /* TODO(b:132652892): Verify the below numbers. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* Define typical operating power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000) #define DC_JACK_MAX_VOLTAGE_MV 19000 /* TCPC gpios */ -- cgit v1.2.1 From eaa3c122d07c50fe4d961d7a231fffb50591eac1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:31 -0600 Subject: board/morphius/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I448f527fcc29bcae624d7da84b4e96d51f2a6106 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728701 Reviewed-by: Jeremy Bettis --- board/morphius/board.h | 80 +++++++++++++++++++++----------------------------- 1 file changed, 33 insertions(+), 47 deletions(-) diff --git a/board/morphius/board.h b/board/morphius/board.h index 180b1df9d0..6454d4a1a5 100644 --- a/board/morphius/board.h +++ b/board/morphius/board.h @@ -52,36 +52,35 @@ #define RPM_DEVIATION 1 /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PWR_A -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PWR_A +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE /* I2C mapping from board specific function*/ -#define I2C_PORT_THERMAL I2C_PORT_AP_HDMI +#define I2C_PORT_THERMAL I2C_PORT_AP_HDMI #ifndef __ASSEMBLER__ - void ps2_pwr_en_interrupt(enum gpio_signal signal); enum adc_channel { @@ -118,11 +117,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -172,40 +167,32 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBC1_RETIMER_PS8802 \ - (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB)) +#define HAS_USBC1_RETIMER_PS8802 (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB)) static inline bool ec_config_has_usbc1_retimer_ps8802(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8802); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802); } -#define HAS_USBC1_RETIMER_PS8818 \ - (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI)) +#define HAS_USBC1_RETIMER_PS8818 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI)) static inline bool ec_config_has_usbc1_retimer_ps8818(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8818); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(MORPHIUS_DB_T_OPT1_USBC_HDMI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } -#define HAS_MST_HUB_RTD2141B \ - (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB)) +#define HAS_MST_HUB_RTD2141B (BIT(MORPHIUS_DB_T_OPT3_USBC_HDMI_MSTHUB)) static inline bool ec_config_has_mst_hub_rtd2141b(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_MST_HUB_RTD2141B); + return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B); } void motion_interrupt(enum gpio_signal signal); @@ -226,5 +213,4 @@ extern struct usb_mux usbc1_amd_fp5_usb_mux; #endif /* !__ASSEMBLER__ */ - #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 4fc99a8c9666f6041ef9fd926516d04b6db1d516 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:08 -0600 Subject: board/herobrine/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ca3db16c084c7c1d2c4856d1fb49af563c74ee1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728303 Reviewed-by: Jeremy Bettis --- board/herobrine/board.h | 31 +++++++++++-------------------- 1 file changed, 11 insertions(+), 20 deletions(-) diff --git a/board/herobrine/board.h b/board/herobrine/board.h index 15cbcf305a..a208eea156 100644 --- a/board/herobrine/board.h +++ b/board/herobrine/board.h @@ -25,7 +25,7 @@ #define CONFIG_PWM_KBLIGHT /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE @@ -62,26 +62,21 @@ #define CONFIG_GMR_TABLET_MODE /* GPIO alias */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_SWITCHCAP_PG GPIO_SRC_VPH_PWR_PG -#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_S5 -#define GPIO_POWER_GOOD GPIO_MB_POWER_GOOD -#define GPIO_EC_INT_L GPIO_AP_EC_INT_L -#define GPIO_DP_HOT_PLUG_DET GPIO_DP_HOT_PLUG_DET_R +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_SWITCHCAP_PG GPIO_SRC_VPH_PWR_PG +#define GPIO_ACOK_OD GPIO_CHG_ACOK_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_S5 +#define GPIO_POWER_GOOD GPIO_MB_POWER_GOOD +#define GPIO_EC_INT_L GPIO_AP_EC_INT_L +#define GPIO_DP_HOT_PLUG_DET GPIO_DP_HOT_PLUG_DET_R #ifndef __ASSEMBLER__ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -91,11 +86,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 491385a3b9cdbad48cef80bad0333959eb6e9067 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:37 -0600 Subject: board/anahera/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc481a90ccacd930fb32bbf7fdc01f7c29d3d3da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727106 Reviewed-by: Jeremy Bettis --- board/anahera/keyboard.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/anahera/keyboard.c b/board/anahera/keyboard.c index 782ba0d0db..43164df58c 100644 --- a/board/anahera/keyboard.c +++ b/board/anahera/keyboard.c @@ -154,13 +154,13 @@ board_vivaldi_keybd_config(void) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 780cf51a57d4c3512bae26b63f445122094a596b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:09 -0600 Subject: board/kappa/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I48f07fa68e9c783f8c226eac43a49830afc98a9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728525 Reviewed-by: Jeremy Bettis --- board/kappa/board.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/kappa/board.h b/board/kappa/board.h index 7cc7f68406..e8136377d7 100644 --- a/board/kappa/board.h +++ b/board/kappa/board.h @@ -50,16 +50,16 @@ #undef CONFIG_TABLET_MODE_SWITCH /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 2 -#define I2C_PORT_CHARGER 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 2 +#define I2C_PORT_CHARGER 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 7b4020f72963c16ac1d8fa20a779eef8ae79588b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:44 -0600 Subject: test/usb_test/device_configuration.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I295716f7233e7afad720a4567ea7cfd9aa4b67aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730579 Reviewed-by: Jeremy Bettis --- test/usb_test/device_configuration.c | 59 +++++++++++++++++------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/test/usb_test/device_configuration.c b/test/usb_test/device_configuration.c index 69f889c2d3..2edb124b9f 100644 --- a/test/usb_test/device_configuration.c +++ b/test/usb_test/device_configuration.c @@ -13,8 +13,8 @@ #include /* Options */ -static uint16_t vid = 0x18d1; /* Google */ -static uint16_t pid = 0x5014; /* Cr50 */ +static uint16_t vid = 0x18d1; /* Google */ +static uint16_t pid = 0x5014; /* Cr50 */ static char *progname; @@ -25,7 +25,8 @@ static void usage(int errs) "Set/Get the USB Device Configuration value\n" "\n" "The default vid:pid is %04x:%04x\n" - "\n", progname, vid, pid); + "\n", + progname, vid, pid); exit(!!errs); } @@ -49,14 +50,13 @@ static void stupid_usb(const char *format, ...) exit(1); } - int main(int argc, char *argv[]) { int r = 1; int errorcnt = 0; int do_set = 0; uint16_t setval = 0; - uint8_t buf[80]; /* Arbitrary size */ + uint8_t buf[80]; /* Arbitrary size */ int i; progname = strrchr(argv[0], '/'); @@ -65,13 +65,13 @@ int main(int argc, char *argv[]) else progname = argv[0]; - opterr = 0; /* quiet, you */ + opterr = 0; /* quiet, you */ while ((i = getopt(argc, argv, "")) != -1) { switch (i) { case 'h': usage(errorcnt); break; - case 0: /* auto-handled option */ + case 0: /* auto-handled option */ break; case '?': if (optopt) @@ -111,8 +111,8 @@ int main(int argc, char *argv[]) r = libusb_init(NULL); if (r) { - printf("libusb_init() returned 0x%x: %s\n", - r, libusb_error_name(r)); + printf("libusb_init() returned 0x%x: %s\n", r, + libusb_error_name(r)); return 1; } @@ -122,41 +122,36 @@ int main(int argc, char *argv[]) stupid_usb("Can't open device %04x:%04x\n", vid, pid); } - /* Set config*/ if (do_set) { printf("SetCfg %d\n", setval); - r = libusb_control_transfer( - devh, - 0x00, /* bmRequestType */ - 0x09, /* bRequest */ - setval, /* wValue */ - 0x0000, /* wIndex */ - NULL, /* data */ - 0x0000, /* wLength */ - 1000); /* timeout (ms) */ + r = libusb_control_transfer(devh, 0x00, /* bmRequestType */ + 0x09, /* bRequest */ + setval, /* wValue */ + 0x0000, /* wIndex */ + NULL, /* data */ + 0x0000, /* wLength */ + 1000); /* timeout (ms) */ if (r < 0) - printf("transfer returned 0x%x %s\n", - r, libusb_error_name(r)); + printf("transfer returned 0x%x %s\n", r, + libusb_error_name(r)); } /* Get config */ memset(buf, 0, sizeof(buf)); - r = libusb_control_transfer( - devh, - 0x80, /* bmRequestType */ - 0x08, /* bRequest */ - 0x0000, /* wValue */ - 0x0000, /* wIndex */ - buf, /* data */ - 0x0001, /* wLength */ - 1000); /* timeout (ms) */ + r = libusb_control_transfer(devh, 0x80, /* bmRequestType */ + 0x08, /* bRequest */ + 0x0000, /* wValue */ + 0x0000, /* wIndex */ + buf, /* data */ + 0x0001, /* wLength */ + 1000); /* timeout (ms) */ if (r <= 0) - stupid_usb("GetCfg transfer() returned 0x%x %s\n", - r, libusb_error_name(r)); + stupid_usb("GetCfg transfer() returned 0x%x %s\n", r, + libusb_error_name(r)); printf("GetCfg returned %d bytes:", r); for (i = 0; i < r; i++) -- cgit v1.2.1 From 5ffac5a13924cce002afb0f734c05d5700581910 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:26 -0600 Subject: board/nautilus/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I421df9ea9af867d281105bf368dc99230a89f775 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728722 Reviewed-by: Jeremy Bettis --- board/nautilus/board.c | 153 ++++++++++++++++++++++--------------------------- 1 file changed, 70 insertions(+), 83 deletions(-) diff --git a/board/nautilus/board.c b/board/nautilus/board.c index 73a40b8433..7e0cc17930 100644 --- a/board/nautilus/board.c +++ b/board/nautilus/board.c @@ -52,8 +52,8 @@ #include "util.h" #include "espi.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -75,9 +75,9 @@ static void vbus_discharge_handler(void) { if (system_get_board_version() >= 2) { pd_set_vbus_discharge(0, - gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); + gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); pd_set_vbus_discharge(1, - gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); + gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); } } DECLARE_DEFERRED(vbus_discharge_handler); @@ -122,56 +122,47 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Base detection */ - [ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0, - ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, /* Vbus sensing (10x voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18, - ADC_READ_MAX+1, 0}, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "tcpc1", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "charger", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "pmic", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "accelgyro", - .port = NPCX_I2C_PORT3, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "tcpc1", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "charger", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "pmic", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "accelgyro", + .port = NPCX_I2C_PORT3, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -222,7 +213,7 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) == CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT); const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { - GPIO_USB1_ENABLE, + GPIO_USB1_ENABLE, }; const struct charger_config_t chg_chips[] = { @@ -260,9 +251,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { @@ -282,13 +273,13 @@ uint16_t tcpc_get_alert_status(void) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* These BD99992GW temp sensors are only readable in S0 */ - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -304,8 +295,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) != + EC_SUCCESS) return; if (!(vrfault & BIT(4))) @@ -414,8 +405,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void) i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a); } -__override void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__override void power_board_handle_host_sleep_event(enum host_sleep_event state) { if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) board_pmic_enable_slp_s0_vr_decay(); @@ -463,13 +453,13 @@ static void board_init(void) gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L); /* Level of sensor's I2C and interrupt are 3.3V on proto board */ - if(system_get_board_version() < 2) { + if (system_get_board_version() < 2) { /* ACCELGYRO3_INT_L */ gpio_set_flags(GPIO_ACCELGYRO3_INT_L, GPIO_INT_FALLING); /* I2C3_SCL / I2C3_SDA */ gpio_set_flags(GPIO_I2C3_SCL, GPIO_INPUT); gpio_set_flags(GPIO_I2C3_SDA, GPIO_INPUT); - } + } /* Enable Gyro interrupts */ gpio_enable_interrupt(GPIO_ACCELGYRO3_INT_L); @@ -519,10 +509,12 @@ int board_set_active_charge_port(int charge_port) } else { /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L : - GPIO_USB_C1_CHARGE_L, 1); + GPIO_USB_C1_CHARGE_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 0); + GPIO_USB_C0_CHARGE_L, + 0); } return EC_SUCCESS; @@ -536,16 +528,16 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - /* - * Limit the input current to 96% negotiated limit, - * to account for the charger chip margin. - */ + /* + * Limit the input current to 96% negotiated limit, + * to account for the charger chip margin. + */ charge_ma = charge_ma * 96 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -571,7 +563,7 @@ void board_hibernate(void) CPRINTS("Triggering PMIC shutdown."); uart_flush_output(); - /* Trigger PMIC shutdown. */ + /* Trigger PMIC shutdown. */ if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) { /* * If we can't tell the PMIC to shutdown, instead reset @@ -625,17 +617,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(1), 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(1), 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -779,13 +767,12 @@ int board_has_working_reset_flags(void) * I2C callbacks to ensure bus free time for battery I2C transactions is at * least 5ms. */ -#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC) +#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC) static timestamp_t battery_last_i2c_time; static int is_battery_i2c(const int port, const uint16_t addr_flags) { - return (port == I2C_PORT_BATTERY) - && (addr_flags == BATTERY_ADDR_FLAGS); + return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS); } void i2c_start_xfer_notify(const int port, const uint16_t addr_flags) -- cgit v1.2.1 From 2a554e239fc3280f9ebd0eeb6f7f96712c0994a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:12 -0600 Subject: test/usb_tcpmv2_td_pd_snk3_e12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iced61d412b61b9705d8e993ca5236b367c6a193c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730574 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_snk3_e12.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_snk3_e12.c b/test/usb_tcpmv2_td_pd_snk3_e12.c index 0195d39dba..28f157456d 100644 --- a/test/usb_tcpmv2_td_pd_snk3_e12.c +++ b/test/usb_tcpmv2_td_pd_snk3_e12.c @@ -46,8 +46,8 @@ int test_td_pd_snk3_e12(void) * d) The Tester verifies that a Soft_Reset message is sent by the UUT * within tReceive max + tSoftReset max */ - TEST_EQ(verify_tcpci_tx_timeout( - TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 16 * MSEC), + TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, + 16 * MSEC), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); -- cgit v1.2.1 From 2cbf6fbf715012a8330908bf5eb3eae8fc6636a6 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 27 Jun 2022 09:59:09 +0800 Subject: ec_commands: Drop VBNV read/write support All devices using EC to store VBNV (Vboot nvdata) have reached their AUE. Remove all VBNV-related code. BUG=b:178689388 TEST=make build_cros_ec_commands BRANCH=none Cq-Depend: chromium:3725376 Change-Id: I85851b1404e3b6279ed4588e19db21738ad2f07c Signed-off-by: Yu-Ping Wu Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724971 Reviewed-by: Ting Shen --- extra/ftdi_hostcmd/test_cmds.c | 1 - include/ec_commands.h | 28 ---------------------------- 2 files changed, 29 deletions(-) diff --git a/extra/ftdi_hostcmd/test_cmds.c b/extra/ftdi_hostcmd/test_cmds.c index 4552476d0f..edacfbb93c 100644 --- a/extra/ftdi_hostcmd/test_cmds.c +++ b/extra/ftdi_hostcmd/test_cmds.c @@ -414,7 +414,6 @@ static struct lookup cmd_table[] = { {0x13, "EC_CMD_FLASH_ERASE"}, {0x15, "EC_CMD_FLASH_PROTECT"}, {0x16, "EC_CMD_FLASH_REGION_INFO"}, - {0x17, "EC_CMD_VBNV_CONTEXT"}, {0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM"}, {0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM"}, {0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT"}, diff --git a/include/ec_commands.h b/include/ec_commands.h index 6e8a3e40c9..62da3c4b94 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -1869,34 +1869,6 @@ struct ec_response_flash_region_info { uint32_t size; } __ec_align4; -/* - * Read/write VbNvContext - * - * Deprecated as of February 2021. No current devices use VBNV in EC - * BBRAM anymore, so this is guaranteed to fail. - * - * TODO(b/178689388): remove from this header once no external - * dependencies reference these constants. - */ -#define EC_CMD_VBNV_CONTEXT 0x0017 -#define EC_VER_VBNV_CONTEXT 1 -#define EC_VBNV_BLOCK_SIZE 16 - -enum ec_vbnvcontext_op { - EC_VBNV_CONTEXT_OP_READ, - EC_VBNV_CONTEXT_OP_WRITE, -}; - -struct ec_params_vbnvcontext { - uint32_t op; - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - -struct ec_response_vbnvcontext { - uint8_t block[EC_VBNV_BLOCK_SIZE]; -} __ec_align4; - - /* Get SPI flash information */ #define EC_CMD_FLASH_SPI_INFO 0x0018 -- cgit v1.2.1 From ccf09958a1ef33b054d10e9c58d31803d492b800 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:51 -0600 Subject: board/vell/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I025e9d10c37b8d495d8d462a020c42bbff9fcc0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729046 Reviewed-by: Jeremy Bettis --- board/vell/fw_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/vell/fw_config.h b/board/vell/fw_config.h index 6e4eb3ef58..7f9b472d83 100644 --- a/board/vell/fw_config.h +++ b/board/vell/fw_config.h @@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type { union brya_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; - uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From aa708e57f7dbe55630ab22a4bb2808c13906572d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:07 -0600 Subject: core/minute-ia/interrupts.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I77124a15e6edd17c7ea487a4833fda3ee434f498 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729853 Reviewed-by: Jeremy Bettis --- core/minute-ia/interrupts.h | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/core/minute-ia/interrupts.h b/core/minute-ia/interrupts.h index 3a951a5ddb..ed8d406333 100644 --- a/core/minute-ia/interrupts.h +++ b/core/minute-ia/interrupts.h @@ -11,7 +11,7 @@ #ifndef __ASSEMBLER__ #include -#define USHRT_MAX 0xFFFF +#define USHRT_MAX 0xFFFF typedef struct { unsigned irq; unsigned trigger; @@ -19,13 +19,11 @@ typedef struct { unsigned vector; } irq_desc_t; -#define INTR_DESC(__irq,__vector,__trig) \ - { \ - .irq = __irq, \ - .trigger = __trig, \ - .polarity = IOAPIC_REDTBL_INTPOL_HIGH, \ - .vector = __vector \ - } +#define INTR_DESC(__irq, __vector, __trig) \ + { \ + .irq = __irq, .trigger = __trig, \ + .polarity = IOAPIC_REDTBL_INTPOL_HIGH, .vector = __vector \ + } #define LEVEL_INTR(__irq, __vector) \ INTR_DESC(__irq, __vector, IOAPIC_REDTBL_TRIGGER_LEVEL) @@ -34,18 +32,18 @@ typedef struct { #endif /* ISH has a single core processor */ -#define DEST_APIC_ID 0 -#define NUM_VECTORS 256 +#define DEST_APIC_ID 0 +#define NUM_VECTORS 256 /* APIC bit definitions. */ -#define APIC_DIV_16 0x03 -#define APIC_ENABLE_BIT (1UL << 8UL) -#define APIC_SPURIOUS_INT REG32(ISH_LAPIC_BASE + 0xF0UL ) -#define APIC_LVT_ERROR REG32(ISH_LAPIC_BASE + 0x370UL) +#define APIC_DIV_16 0x03 +#define APIC_ENABLE_BIT (1UL << 8UL) +#define APIC_SPURIOUS_INT REG32(ISH_LAPIC_BASE + 0xF0UL) +#define APIC_LVT_ERROR REG32(ISH_LAPIC_BASE + 0x370UL) #ifndef __ASSEMBLER__ -typedef void (*isr_handler_t) (void); +typedef void (*isr_handler_t)(void); void init_interrupts(void); void mask_interrupt(unsigned int irq); @@ -66,4 +64,4 @@ void restore_interrupts(uint64_t irq_map); uint32_t get_current_interrupt_vector(void); #endif -#endif /* __CROS_EC_IA32_INTERRUPTS_H */ +#endif /* __CROS_EC_IA32_INTERRUPTS_H */ -- cgit v1.2.1 From a46c9205b802f862426615985313ab137f9bf2c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:56 -0600 Subject: baseboard/goroh/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I955d449fa728b5806eb4ea6238e82c69ed6a25ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727513 Reviewed-by: Jeremy Bettis --- baseboard/goroh/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/goroh/usb_pd_policy.c b/baseboard/goroh/usb_pd_policy.c index 5030489ec8..0ec79d4956 100644 --- a/baseboard/goroh/usb_pd_policy.c +++ b/baseboard/goroh/usb_pd_policy.c @@ -15,8 +15,8 @@ #error Goroh reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) void svdm_set_hpd_gpio(int port, int en) { -- cgit v1.2.1 From 2b52ba76a89bb0e56d360f0f40a090a09d87771a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:40 -0600 Subject: driver/tcpm/fusb307.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40c7bb4e29679bf8ffc76df206c5e71b016bf1d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730078 Reviewed-by: Jeremy Bettis --- driver/tcpm/fusb307.c | 58 +++++++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/driver/tcpm/fusb307.c b/driver/tcpm/fusb307.c index 3569032805..6a865af69c 100644 --- a/driver/tcpm/fusb307.c +++ b/driver/tcpm/fusb307.c @@ -14,8 +14,8 @@ #include "timer.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int fusb307_power_supply_reset(int port) { @@ -44,25 +44,29 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) tcpm_get_cc(port, &cc1, &cc2); if (cc1) { if (pd_get_power_role(port) == PD_ROLE_SINK) { - int role = TCPC_REG_ROLE_CTRL_SET(0, - tcpci_get_cached_rp(port), TYPEC_CC_RD, TYPEC_CC_OPEN); + int role = TCPC_REG_ROLE_CTRL_SET( + 0, tcpci_get_cached_rp(port), TYPEC_CC_RD, + TYPEC_CC_OPEN); tcpc_write(port, TCPC_REG_ROLE_CTRL, role); } else { - int role = TCPC_REG_ROLE_CTRL_SET(0, - tcpci_get_cached_rp(port), TYPEC_CC_RP, TYPEC_CC_OPEN); + int role = TCPC_REG_ROLE_CTRL_SET( + 0, tcpci_get_cached_rp(port), TYPEC_CC_RP, + TYPEC_CC_OPEN); tcpc_write(port, TCPC_REG_ROLE_CTRL, role); } } else if (cc2) { if (pd_get_power_role(port) == PD_ROLE_SINK) { - int role = TCPC_REG_ROLE_CTRL_SET(0, - tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RD); + int role = TCPC_REG_ROLE_CTRL_SET( + 0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN, + TYPEC_CC_RD); tcpc_write(port, TCPC_REG_ROLE_CTRL, role); } else { - int role = TCPC_REG_ROLE_CTRL_SET(0, - tcpci_get_cached_rp(port), TYPEC_CC_OPEN, TYPEC_CC_RP); + int role = TCPC_REG_ROLE_CTRL_SET( + 0, tcpci_get_cached_rp(port), TYPEC_CC_OPEN, + TYPEC_CC_RP); tcpc_write(port, TCPC_REG_ROLE_CTRL, role); } @@ -77,26 +81,26 @@ int fusb307_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) } const struct tcpm_drv fusb307_tcpm_drv = { - .init = &fusb307_tcpm_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &fusb307_tcpm_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &fusb307_tcpm_set_polarity, - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tcpci_tcpc_alert, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &fusb307_tcpm_set_polarity, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, .tcpc_enable_auto_discharge_disconnect = - &tcpci_tcpc_enable_auto_discharge_disconnect, - .get_chip_info = &tcpci_get_chip_info, + &tcpci_tcpc_enable_auto_discharge_disconnect, + .get_chip_info = &tcpci_get_chip_info, #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; -- cgit v1.2.1 From 35355115d86ee32818d97c18b9a097ae47efe189 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:45 -0600 Subject: chip/stm32/usart_rx_interrupt.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f70b2b1fcc97ed3606dc9ef2738bb65ac2c2324 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729423 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_interrupt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/usart_rx_interrupt.c b/chip/stm32/usart_rx_interrupt.c index 49d4e83894..4d5060a26e 100644 --- a/chip/stm32/usart_rx_interrupt.c +++ b/chip/stm32/usart_rx_interrupt.c @@ -23,8 +23,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); if (status & STM32_USART_SR_RXNE) { uint8_t byte = STM32_USART_RDR(base); -- cgit v1.2.1 From fd908da85f67fb363555090e1ec014b6af553d15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:36 -0600 Subject: chip/max32660/pwrseq_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id88cd8c66b200e7d1c06599c061ebc295040a0c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729235 Reviewed-by: Jeremy Bettis --- chip/max32660/pwrseq_regs.h | 486 ++++++++++++++++++++++---------------------- 1 file changed, 247 insertions(+), 239 deletions(-) diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h index 1ac0686aa6..e84c814ef4 100644 --- a/chip/max32660/pwrseq_regs.h +++ b/chip/max32660/pwrseq_regs.h @@ -53,8 +53,8 @@ extern "C" { */ typedef struct { __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ - __IO uint32_t - lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ + __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL + Register */ __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ __R uint32_t rsv_0xc_0x3f[13]; __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ @@ -64,234 +64,240 @@ typedef struct { * Register offsets for module PWRSEQ * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base */ -#define MXC_R_PWRSEQ_LP_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: \ \ +#define MXC_R_PWRSEQ_LP_CTRL \ + ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: \ \ \ \ \ 0x0000 */ -#define MXC_R_PWRSEQ_LP_WAKEFL \ - ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: \ \ +#define MXC_R_PWRSEQ_LP_WAKEFL \ + ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: \ \ \ \ \ 0x0004 */ -#define MXC_R_PWRSEQ_LPWK_EN \ - ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: \ \ +#define MXC_R_PWRSEQ_LPWK_EN \ + ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: \ \ \ \ \ 0x0008 */ -#define MXC_R_PWRSEQ_LPMEMSD \ - ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: \ \ +#define MXC_R_PWRSEQ_LPMEMSD \ + ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: \ \ \ \ \ 0x0040 */ /** * pwrseq_registers * Low Power Control Register. */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \ 0 /**< LP_CTRL_RAMRET_SEL0 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL0 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL0 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \ 1 /**< LP_CTRL_RAMRET_SEL1 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL1 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL1 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \ 2 /**< LP_CTRL_RAMRET_SEL2 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL2 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL2 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \ 3 /**< LP_CTRL_RAMRET_SEL3 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL3 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL3 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \ \ \ \ \ Setting */ #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ -#define MXC_F_PWRSEQ_LP_CTRL_OVR \ - ((uint32_t)(0x3UL \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ +#define MXC_F_PWRSEQ_LP_CTRL_OVR \ + ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR \ + Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_0_9V \ + Setting \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_0V \ + Setting \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_1V \ + Setting \ + */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_DET_BYPASS \ - \ \ - \ \ \ \ \ - Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ + \ \ \ \ \ + LP_CTRL_VCORE_DET_BYPASS \ + \ \ + \ \ \ \ \ + Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_DET_BYPASS_ENABLED \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_DET_BYPASS_DISABLE \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \ - 8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \ + 8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< \ + LP_CTRL_RETREG_EN \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \ +#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \ 10 /**< LP_CTRL_FAST_WK_EN Position */ -#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \ - LP_CTRL_FAST_WK_EN \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \ + LP_CTRL_FAST_WK_EN \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ - (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ - << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \ +#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ + (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ + << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \ \ \ \ Setting */ #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ -#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \ - ((uint32_t)( \ - 0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ +#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */ -#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \ - (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ +#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \ + (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ +#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */ #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF \ (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \ * \ \ - * \ \ \ - * \ \ \ \ + * \ \ \ + * \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \ 12 /**< LP_CTRL_VCORE_POR_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_POR_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VCORE_POR_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_POR_DIS_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_POR_DIS_EN \ \ \ \ \ Setting */ @@ -300,70 +306,70 @@ typedef struct { ((uint32_t)(0x1UL \ << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \ \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \ - (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \ - * \ \ - * \ \ \ - * \ \ \ \ - * \ \ \ \ \ +#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \ + (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ + << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \ + * \ \ + * \ \ \ + * \ \ \ \ + * \ \ \ \ \ */ -#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \ * \ \ - * \ \ \ - * \ \ \ \ - * \ \ \ \ \ + * \ \ \ + * \ \ \ \ + * \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \ 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_SVM_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VCORE_SVM_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_SVM_DIS_EN \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_SVM_DIS_DIS \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \ 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VDDIO_POR_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VDDIO_POR_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VDDIO_POR_DIS_EN \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VDDIO_POR_DIS_DIS \ \ \ \ \ Setting */ @@ -372,11 +378,12 @@ typedef struct { * Low Power Mode Wakeup Flags for GPIO0 */ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ -#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ - ((uint32_t)( \ - 0x3FFFUL \ - << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \ - \ \ \ Mask */ +#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ + ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ + LP_WAKEFL_WAKEST \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers @@ -384,104 +391,105 @@ typedef struct { * power wakeup functionality for GPIO0. */ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ -#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ - ((uint32_t)(0x3FFFUL \ - << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \ - \ \ \ Mask */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ + ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ + LPWK_EN_WAKEEN \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers * Low Power Memory Shutdown Control. */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \ - 0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \ + 0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< \ + LPMEMSD_SRAM0_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM0_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM0_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \ - 1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \ + 1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< \ + LPMEMSD_SRAM1_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM1_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM1_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \ - 2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \ + 2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< \ + LPMEMSD_SRAM2_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM2_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM2_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \ - 3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \ + 3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< \ + LPMEMSD_SRAM3_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM3_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM3_OFF_SHUTDOWN \ \ \ \ \ Setting */ - #ifdef __cplusplus } #endif -- cgit v1.2.1 From 1731f9f0822db4c2770a2bdc0a4be2ce04513324 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:38 -0600 Subject: power/common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfe4c4bcf82b514d3838bace118c8a6050ca951a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727058 Reviewed-by: Jeremy Bettis --- power/common.c | 179 +++++++++++++++++++++++++-------------------------------- 1 file changed, 79 insertions(+), 100 deletions(-) diff --git a/power/common.c b/power/common.c index 04d416ee5f..8b807f8364 100644 --- a/power/common.c +++ b/power/common.c @@ -27,8 +27,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /* * Default timeout in us; if we've been waiting this long for an input @@ -43,37 +43,24 @@ static int s5_inactivity_timeout = 10; static const int s5_inactivity_timeout = 10; #endif -static const char * const state_names[] = { - "G3", - "S5", - "S4", - "S3", - "S0", +static const char *const state_names[] = { + "G3", "S5", "S4", "S3", "S0", #ifdef CONFIG_POWER_S0IX "S0ix", #endif - "G3->S5", - "S5->S3", - "S3->S0", - "S0->S3", - "S3->S5", - "S5->G3", - "S3->S4", - "S4->S3", - "S4->S5", - "S5->S4", + "G3->S5", "S5->S3", "S3->S0", "S0->S3", "S3->S5", + "S5->G3", "S3->S4", "S4->S3", "S4->S5", "S5->S4", #ifdef CONFIG_POWER_S0IX - "S0ix->S0", - "S0->S0ix", + "S0ix->S0", "S0->S0ix", #endif }; -static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */ -static uint32_t in_want; /* Input signal state we're waiting for */ -static uint32_t in_debug; /* Signal values which print debug output */ +static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */ +static uint32_t in_want; /* Input signal state we're waiting for */ +static uint32_t in_debug; /* Signal values which print debug output */ -static enum power_state state = POWER_G3; /* Current state */ -static int want_g3_exit; /* Should we exit the G3 state? */ +static enum power_state state = POWER_G3; /* Current state */ +static int want_g3_exit; /* Should we exit the G3 state? */ static uint64_t last_shutdown_time; /* When did we enter G3? */ #ifdef CONFIG_HIBERNATE @@ -86,7 +73,7 @@ static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC; static int pause_in_s5; #endif -static bool want_reboot_ap_at_g3;/* Want to reboot AP from G3? */ +static bool want_reboot_ap_at_g3; /* Want to reboot AP from G3? */ /* Want to reboot AP from G3 with delay? */ static uint64_t reboot_ap_at_g3_delay; @@ -111,8 +98,7 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, - host_command_reboot_ap_on_g3, +DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3, EC_VER_MASK(0) | EC_VER_MASK(1)); __overridable int power_signal_get_level(enum gpio_signal signal) @@ -150,7 +136,7 @@ int power_signal_enable_interrupt(enum gpio_signal signal) int power_signal_is_asserted(const struct power_signal_info *s) { return power_signal_get_level(s->gpio) == - !!(s->flags & POWER_SIGNAL_ACTIVE_STATE); + !!(s->flags & POWER_SIGNAL_ACTIVE_STATE); } #ifdef CONFIG_BRINGUP @@ -196,8 +182,8 @@ int power_has_signals(uint32_t want) if ((in_signals & want) == want) return 1; - CPRINTS("power lost input; wanted 0x%04x, got 0x%04x", - want, in_signals & want); + CPRINTS("power lost input; wanted 0x%04x, got 0x%04x", want, + in_signals & want); return 0; } @@ -267,18 +253,19 @@ enum power_state power_get_state(void) #ifdef CONFIG_HOSTCMD_X86 /* If host doesn't program s0ix lazy wake mask, use default s0ix mask */ -#define DEFAULT_WAKE_MASK_S0IX (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - - /* - * Set the wake mask according to the current power state: - * 1. On transition to S0, wake mask is reset. - * 2. In non-S0 states, active mask set by host gets a higher preference. - * 3. If host has not set any active mask, then check if a lazy mask exists - * for the current power state. - * 4. If state is S0ix and no lazy or active wake mask is set, then use default - * S0ix mask to be compatible with older BIOS versions. - */ +#define DEFAULT_WAKE_MASK_S0IX \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* + * Set the wake mask according to the current power state: + * 1. On transition to S0, wake mask is reset. + * 2. In non-S0 states, active mask set by host gets a higher preference. + * 3. If host has not set any active mask, then check if a lazy mask exists + * for the current power state. + * 4. If state is S0ix and no lazy or active wake mask is set, then use default + * S0ix mask to be compatible with older BIOS versions. + */ void power_update_wake_mask(void) { @@ -300,11 +287,11 @@ void power_update_wake_mask(void) lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, wake_mask); } - /* - * Set wake mask after power state has stabilized, 5ms after power state - * change. The reason for making this a deferred call is to avoid race - * conditions occurring from S0ix periodic wakes on the SoC. - */ +/* + * Set wake mask after power state has stabilized, 5ms after power state + * change. The reason for making this a deferred call is to avoid race + * conditions occurring from S0ix periodic wakes on the SoC. + */ static void power_update_wake_mask_deferred(void); DECLARE_DEFERRED(power_update_wake_mask_deferred); @@ -329,12 +316,13 @@ static void power_set_active_wake_mask(void) * that it takes ~2msec for the periodic wake cycle to complete on the * host for KBL. */ - hook_call_deferred(&power_update_wake_mask_deferred_data, - 5 * MSEC); + hook_call_deferred(&power_update_wake_mask_deferred_data, 5 * MSEC); } #else -static void power_set_active_wake_mask(void) { } +static void power_set_active_wake_mask(void) +{ +} #endif #ifdef CONFIG_HIBERNATE @@ -378,15 +366,15 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args) else if (p->drate.cutoff > 0 && p->drate.hibern > 0) drate = p->drate; else if (p->drate.cutoff == 0 && p->drate.hibern == 0) - ; /* no-op. use the current drate. */ + ; /* no-op. use the current drate. */ else return EC_RES_INVALID_PARAM; /* Commit */ hours_to_zero = p->hours_to_zero; sdzone.stayup = MIN(hours_to_zero * drate.hibern / 1000, cap); - sdzone.cutoff = MIN(hours_to_zero * drate.cutoff / 1000, - sdzone.stayup); + sdzone.cutoff = + MIN(hours_to_zero * drate.cutoff / 1000, sdzone.stayup); } /* Return the effective values. */ @@ -397,12 +385,12 @@ static enum ec_status hc_smart_discharge(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, - hc_smart_discharge, +DECLARE_HOST_COMMAND(EC_CMD_SMART_DISCHARGE, hc_smart_discharge, EC_VER_MASK(0)); -__overridable enum critical_shutdown board_system_is_idle( - uint64_t last_shutdown_time, uint64_t *target, uint64_t now) +__overridable enum critical_shutdown +board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target, + uint64_t now) { int remain; @@ -427,14 +415,15 @@ __overridable enum critical_shutdown board_system_is_idle( } #else /* Default implementation for battery-less systems */ -__overridable enum critical_shutdown board_system_is_idle( - uint64_t last_shutdown_time, uint64_t *target, uint64_t now) +__overridable enum critical_shutdown +board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target, + uint64_t now) { - return now > *target ? - CRITICAL_SHUTDOWN_HIBERNATE : CRITICAL_SHUTDOWN_IGNORE; + return now > *target ? CRITICAL_SHUTDOWN_HIBERNATE : + CRITICAL_SHUTDOWN_IGNORE; } -#endif /* CONFIG_BATTERY */ -#endif /* CONFIG_HIBERNATE */ +#endif /* CONFIG_BATTERY */ +#endif /* CONFIG_HIBERNATE */ /** * Common handler for steady states @@ -475,7 +464,7 @@ static enum power_state power_common_state(enum power_state state) now = get_time().val; target = last_shutdown_time + - (uint64_t)hibernate_delay * SECOND; + (uint64_t)hibernate_delay * SECOND; switch (board_system_is_idle(last_shutdown_time, &target, now)) { case CRITICAL_SHUTDOWN_HIBERNATE: @@ -708,8 +697,8 @@ void chipset_task(void *u) */ this_in_signals = in_signals; if (this_in_signals != last_in_signals || state != last_state) { - CPRINTS("power state %d = %s, in 0x%04x", - state, state_names[state], this_in_signals); + CPRINTS("power state %d = %s, in 0x%04x", state, + state_names[state], this_in_signals); if (IS_ENABLED(CONFIG_SEVEN_SEG_DISPLAY)) display_7seg_write(SEVEN_SEG_EC_DISPLAY, state); last_in_signals = this_in_signals; @@ -809,7 +798,7 @@ static struct { static void siglog_deferred(void) { unsigned int i; - timestamp_t tdiff = {.val = 0}; + timestamp_t tdiff = { .val = 0 }; /* Disable interrupts for input signals while we print stuff.*/ for (i = 0; i < POWER_SIGNAL_COUNT; i++) @@ -818,10 +807,9 @@ static void siglog_deferred(void) CPRINTF("%d signal changes:\n", siglog_entries); for (i = 0; i < siglog_entries; i++) { if (i) - tdiff.val = siglog[i].time.val - siglog[i-1].time.val; - CPRINTF(" %.6lld +%.6lld %s => %d\n", - siglog[i].time.val, tdiff.val, - power_signal_get_name(siglog[i].signal), + tdiff.val = siglog[i].time.val - siglog[i - 1].time.val; + CPRINTF(" %.6lld +%.6lld %s => %d\n", siglog[i].time.val, + tdiff.val, power_signal_get_name(siglog[i].signal), siglog[i].level); } if (siglog_truncated) @@ -853,7 +841,7 @@ static void siglog_add(enum gpio_signal signal) #else #define SIGLOG(S) -#endif /* CONFIG_BRINGUP */ +#endif /* CONFIG_BRINGUP */ #ifdef CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD /* @@ -870,8 +858,7 @@ static void reset_power_signal_interrupt_count(void) for (i = 0; i < POWER_SIGNAL_COUNT; ++i) power_signal_interrupt_count[i] = 0; } -DECLARE_HOOK(HOOK_SECOND, - reset_power_signal_interrupt_count, +DECLARE_HOOK(HOOK_SECOND, reset_power_signal_interrupt_count, HOOK_PRIO_DEFAULT); #endif @@ -884,7 +871,7 @@ void power_signal_interrupt(enum gpio_signal signal) for (i = 0; i < POWER_SIGNAL_COUNT; ++i) { if (power_signal_list[i].gpio == signal) { if (power_signal_interrupt_count[i]++ == - CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD) + CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD) CPRINTS("Interrupt storm! Signal %d", i); break; } @@ -921,13 +908,12 @@ static int command_powerinfo(int argc, char **argv) * Print power state in same format as state machine. This is * used by FAFT tests, so must match exactly. */ - ccprintf("power state %d = %s, in 0x%04x\n", - state, state_names[state], in_signals); + ccprintf("power state %d = %s, in 0x%04x\n", state, state_names[state], + in_signals); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo, - NULL, +DECLARE_CONSOLE_COMMAND(powerinfo, command_powerinfo, NULL, "Show current power state"); #ifdef CONFIG_CMD_POWERINDEBUG @@ -955,14 +941,13 @@ static int command_powerindebug(int argc, char **argv) ccprintf("bit meanings:\n"); for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) { int mask = 1 << i; - ccprintf(" 0x%04x %d %s\n", - mask, in_signals & mask ? 1 : 0, s->name); + ccprintf(" 0x%04x %d %s\n", mask, in_signals & mask ? 1 : 0, + s->name); } return EC_SUCCESS; }; -DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug, - "[mask]", +DECLARE_CONSOLE_COMMAND(powerindebug, command_powerindebug, "[mask]", "Get/set power input debug mask"); #endif @@ -985,8 +970,7 @@ static int command_s5_timeout(int argc, char **argv) ccprintf("S5 inactivity timeout: %d s\n", s5_inactivity_timeout); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout, - "[sec]", +DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout, "[sec]", "Set the timeout from S5 to G3 transition, " "-1 to indicate no transition"); #endif @@ -995,8 +979,8 @@ DECLARE_CONSOLE_COMMAND(s5_timeout, command_s5_timeout, static int command_hibernation_delay(int argc, char **argv) { char *e; - uint32_t time_g3 = ((uint32_t)(get_time().val - last_shutdown_time)) - / SECOND; + uint32_t time_g3 = + ((uint32_t)(get_time().val - last_shutdown_time)) / SECOND; if (argc >= 2) { uint32_t s = strtoi(argv[1], &e, 0); @@ -1014,8 +998,7 @@ static int command_hibernation_delay(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay, - "[sec]", +DECLARE_CONSOLE_COMMAND(hibdelay, command_hibernation_delay, "[sec]", "Set the delay before going into hibernation"); static enum ec_status @@ -1048,8 +1031,7 @@ host_command_hibernation_delay(struct host_cmd_handler_args *args) args->response_size = sizeof(struct ec_response_hibernation_delay); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY, - host_command_hibernation_delay, +DECLARE_HOST_COMMAND(EC_CMD_HIBERNATION_DELAY, host_command_hibernation_delay, EC_VER_MASK(0)); #endif /* CONFIG_HIBERNATE */ @@ -1068,8 +1050,7 @@ host_command_pause_in_s5(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5, - host_command_pause_in_s5, +DECLARE_HOST_COMMAND(EC_CMD_GSV_PAUSE_IN_S5, host_command_pause_in_s5, EC_VER_MASK(0)); static int command_pause_in_s5(int argc, char **argv) @@ -1081,8 +1062,7 @@ static int command_pause_in_s5(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5, - "[on|off]", +DECLARE_CONSOLE_COMMAND(pause_in_s5, command_pause_in_s5, "[on|off]", "Should the AP pause in S5 during shutdown?"); #endif /* CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 */ @@ -1116,14 +1096,13 @@ void power_5v_enable(task_id_t tid, int enable) mutex_unlock(&pwr_5v_ctl_mtx); } -#define P5_SYSJUMP_TAG 0x5005 /* "P5" */ +#define P5_SYSJUMP_TAG 0x5005 /* "P5" */ static void restore_enable_5v_state(void) { const uint32_t *state; int size; - state = (const uint32_t *) system_get_jump_tag(P5_SYSJUMP_TAG, 0, - &size); + state = (const uint32_t *)system_get_jump_tag(P5_SYSJUMP_TAG, 0, &size); if (state && size == sizeof(pwr_5v_en_req)) { mutex_lock(&pwr_5v_ctl_mtx); pwr_5v_en_req |= *state; @@ -1136,7 +1115,7 @@ static void preserve_enable_5v_state(void) { mutex_lock(&pwr_5v_ctl_mtx); system_add_jump_tag(P5_SYSJUMP_TAG, 0, sizeof(pwr_5v_en_req), - &pwr_5v_en_req); + &pwr_5v_en_req); mutex_unlock(&pwr_5v_ctl_mtx); } DECLARE_HOOK(HOOK_SYSJUMP, preserve_enable_5v_state, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From a67313ab07c03b428ea7817aa21359bf312efdac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:47 -0600 Subject: board/drawcia_riscv/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e5446350d83918a41d0a2a47d3cef4adbd8e782 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728241 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/drawcia_riscv/cbi_ssfc.c b/board/drawcia_riscv/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/drawcia_riscv/cbi_ssfc.c +++ b/board/drawcia_riscv/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 22bf9f3c2f8283f942bc1c3e69b1abd7eddcb728 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:48 -0600 Subject: board/kukui/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd72ddc81a42ac8ba5b8ec4ea2154a30950a612c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728592 Reviewed-by: Jeremy Bettis --- board/kukui/led.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/board/kukui/led.c b/board/kukui/led.c index 59f7681754..9c4afcc0da 100644 --- a/board/kukui/led.c +++ b/board/kukui/led.c @@ -17,15 +17,15 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); static enum charge_state prv_chstate = PWR_STATE_INIT; -#define LED_OFF MT6370_LED_ID_OFF -#define LED_RED MT6370_LED_ID1 -#define LED_GREEN MT6370_LED_ID2 -#define LED_BLUE MT6370_LED_ID3 +#define LED_OFF MT6370_LED_ID_OFF +#define LED_RED MT6370_LED_ID1 +#define LED_GREEN MT6370_LED_ID2 +#define LED_BLUE MT6370_LED_ID3 -#define LED_MASK_OFF 0 -#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN -#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN -#define LED_MASK_BLUE MT6370_MASK_RGB_ISNK3DIM_EN +#define LED_MASK_OFF 0 +#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN +#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN +#define LED_MASK_BLUE MT6370_MASK_RGB_ISNK3DIM_EN static void kukui_led_set_battery(void) { @@ -35,8 +35,7 @@ static void kukui_led_set_battery(void) chstate = charge_get_state(); - if (prv_chstate == chstate && - chstate != PWR_STATE_DISCHARGE) + if (prv_chstate == chstate && chstate != PWR_STATE_DISCHARGE) return; prv_chstate = chstate; @@ -62,8 +61,7 @@ static void kukui_led_set_battery(void) return; } - if (prv_r == br[EC_LED_COLOR_RED] && - prv_g == br[EC_LED_COLOR_GREEN] && + if (prv_r == br[EC_LED_COLOR_RED] && prv_g == br[EC_LED_COLOR_GREEN] && prv_b == br[EC_LED_COLOR_BLUE]) return; -- cgit v1.2.1 From 0db4eaba3aba07a3921f45cb0983523a34b1c0f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:03 -0600 Subject: common/queue.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5130a9b5e9597325217f39bf5ec7125a0a59f7bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729703 Reviewed-by: Jeremy Bettis --- common/queue.c | 82 +++++++++++++++++++++------------------------------------- 1 file changed, 30 insertions(+), 52 deletions(-) diff --git a/common/queue.c b/common/queue.c index 7b083233ad..8ad08c8438 100644 --- a/common/queue.c +++ b/common/queue.c @@ -8,14 +8,14 @@ #include "queue.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) static void queue_action_null(struct queue_policy const *policy, size_t count) { } struct queue_policy const queue_policy_null = { - .add = queue_action_null, + .add = queue_action_null, .remove = queue_action_null, }; @@ -74,17 +74,17 @@ struct queue_chunk queue_get_write_chunk(struct queue const *q, size_t offset) { size_t head = q->state->head & q->buffer_units_mask; size_t tail = (q->state->tail + offset) & q->buffer_units_mask; - size_t last = (tail < head) ? head : /* Wrapped */ - q->buffer_units; /* Normal | Empty */ + size_t last = (tail < head) ? head : /* Wrapped */ + q->buffer_units; /* Normal | Empty */ /* Make sure that the offset doesn't exceed free space. */ if (queue_space(q) <= offset) - return ((struct queue_chunk) { + return ((struct queue_chunk){ .count = 0, .buffer = NULL, }); - return ((struct queue_chunk) { + return ((struct queue_chunk){ .count = last - tail, .buffer = q->buffer + (tail * q->unit_bytes), }); @@ -95,10 +95,10 @@ struct queue_chunk queue_get_read_chunk(struct queue const *q) size_t head = q->state->head & q->buffer_units_mask; size_t tail = q->state->tail & q->buffer_units_mask; size_t last = (queue_is_empty(q) ? head : /* Empty */ - ((head < tail) ? tail : /* Normal */ - q->buffer_units)); /* Wrapped | Full */ + ((head < tail) ? tail : /* Normal */ + q->buffer_units)); /* Wrapped | Full */ - return ((struct queue_chunk) { + return ((struct queue_chunk){ .count = (last - head), .buffer = q->buffer + (head * q->unit_bytes), }); @@ -134,7 +134,7 @@ size_t queue_add_unit(struct queue const *q, const void *src) return 0; if (q->unit_bytes == 1) - q->buffer[tail] = *((uint8_t *) src); + q->buffer[tail] = *((uint8_t *)src); else memcpy(q->buffer + tail * q->unit_bytes, src, q->unit_bytes); @@ -146,46 +146,33 @@ size_t queue_add_units(struct queue const *q, const void *src, size_t count) return queue_add_memcpy(q, src, count, memcpy); } -size_t queue_add_memcpy(struct queue const *q, - const void *src, - size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)) +size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)) { size_t transfer = MIN(count, queue_space(q)); - size_t tail = q->state->tail & q->buffer_units_mask; - size_t first = MIN(transfer, q->buffer_units - tail); + size_t tail = q->state->tail & q->buffer_units_mask; + size_t first = MIN(transfer, q->buffer_units - tail); - memcpy(q->buffer + tail * q->unit_bytes, - src, - first * q->unit_bytes); + memcpy(q->buffer + tail * q->unit_bytes, src, first * q->unit_bytes); if (first < transfer) memcpy(q->buffer, - ((uint8_t const *) src) + first * q->unit_bytes, + ((uint8_t const *)src) + first * q->unit_bytes, (transfer - first) * q->unit_bytes); return queue_advance_tail(q, transfer); } -static void queue_read_safe(struct queue const *q, - void *dest, - size_t head, - size_t transfer, - void *(*memcpy)(void *dest, - const void *src, - size_t n)) +static void +queue_read_safe(struct queue const *q, void *dest, size_t head, size_t transfer, + void *(*memcpy)(void *dest, const void *src, size_t n)) { size_t first = MIN(transfer, q->buffer_units - head); - memcpy(dest, - q->buffer + head * q->unit_bytes, - first * q->unit_bytes); + memcpy(dest, q->buffer + head * q->unit_bytes, first * q->unit_bytes); if (first < transfer) - memcpy(((uint8_t *) dest) + first * q->unit_bytes, - q->buffer, + memcpy(((uint8_t *)dest) + first * q->unit_bytes, q->buffer, (transfer - first) * q->unit_bytes); } @@ -197,7 +184,7 @@ size_t queue_remove_unit(struct queue const *q, void *dest) return 0; if (q->unit_bytes == 1) - *((uint8_t *) dest) = q->buffer[head]; + *((uint8_t *)dest) = q->buffer[head]; else memcpy(dest, q->buffer + head * q->unit_bytes, q->unit_bytes); @@ -209,39 +196,30 @@ size_t queue_remove_units(struct queue const *q, void *dest, size_t count) return queue_remove_memcpy(q, dest, count, memcpy); } -size_t queue_remove_memcpy(struct queue const *q, - void *dest, - size_t count, - void *(*memcpy)(void *dest, - const void *src, +size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)) { size_t transfer = MIN(count, queue_count(q)); - size_t head = q->state->head & q->buffer_units_mask; + size_t head = q->state->head & q->buffer_units_mask; queue_read_safe(q, dest, head, transfer, memcpy); return queue_advance_head(q, transfer); } -size_t queue_peek_units(struct queue const *q, - void *dest, - size_t i, +size_t queue_peek_units(struct queue const *q, void *dest, size_t i, size_t count) { return queue_peek_memcpy(q, dest, i, count, memcpy); } -size_t queue_peek_memcpy(struct queue const *q, - void *dest, - size_t i, +size_t queue_peek_memcpy(struct queue const *q, void *dest, size_t i, size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)) + void *(*memcpy)(void *dest, const void *src, size_t n)) { size_t available = queue_count(q); - size_t transfer = MIN(count, available - i); + size_t transfer = MIN(count, available - i); if (i < available) { size_t head = (q->state->head + i) & q->buffer_units_mask; @@ -258,7 +236,7 @@ void queue_begin(struct queue const *q, struct queue_iterator *it) it->ptr = NULL; else it->ptr = q->buffer + (q->state->head & q->buffer_units_mask) * - q->unit_bytes; + q->unit_bytes; it->_state.offset = 0; it->_state.head = q->state->head; it->_state.tail = q->state->tail; -- cgit v1.2.1 From 40c1d382ef52737582d2ab038d437c7c9b4cc613 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:18 -0600 Subject: board/bobba/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fc39bf3bbcdd601a0b559634e090a7b07343ef9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728037 Reviewed-by: Jeremy Bettis --- board/bobba/board.c | 152 +++++++++++++++++++++++++--------------------------- 1 file changed, 72 insertions(+), 80 deletions(-) diff --git a/board/bobba/board.c b/board/bobba/board.c index 1ab1dad660..44101476ea 100644 --- a/board/bobba/board.c +++ b/board/bobba/board.c @@ -48,11 +48,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -62,17 +62,16 @@ static uint8_t sku_id; * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* Check PPC ID Pin and Board ver to decide which one ppc is used. */ static bool support_syv_ppc(void) @@ -115,31 +114,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -149,17 +148,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* * Sparky360 SKU ID 26 has AR Cam, and move base accel/gryo to AR Cam board. @@ -174,9 +169,9 @@ const mat33_fp_t base_icm_ref = { * |0 0.27564 0.96126| */ const mat33_fp_t base_ar_cam_ref = { - { 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564)}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126)} + { 0, FLOAT_TO_FP(-0.96126), FLOAT_TO_FP(0.27564) }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(0.27564), FLOAT_TO_FP(0.96126) } }; /* sensor private data */ @@ -301,20 +296,20 @@ struct motion_sensor_t icm426xx_base_accel = { }; struct motion_sensor_t icm426xx_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm426xx_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &base_icm_ref, - .min_frequency = ICM426XX_GYRO_MIN_FREQ, - .max_frequency = ICM426XX_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM426XX, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm426xx_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm426xx_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &base_icm_ref, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; static int board_is_convertible(void) @@ -323,9 +318,8 @@ static int board_is_convertible(void) * SKU ID of Bobba360, Sparky360, & unprovisioned: 9, 10, 11, 12, * 25, 26, 27, 255 */ - return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12 - || sku_id == 25 || sku_id == 26 || sku_id == 27 - || sku_id == 255; + return sku_id == 9 || sku_id == 10 || sku_id == 11 || sku_id == 12 || + sku_id == 25 || sku_id == 26 || sku_id == 27 || sku_id == 255; } static int board_with_ar_cam(void) @@ -407,8 +401,9 @@ static void board_usb_charge_mode_init(void) int i; /* - * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough because - * USB_SYSJUMP_TAG preserves the settings to RW. And we should honor to it. + * Only overriding the USB_DISALLOW_SUSPEND_CHARGE in RO is enough + * because USB_SYSJUMP_TAG preserves the settings to RW. And we should + * honor to it. */ if (system_jumped_late()) return; @@ -425,7 +420,7 @@ static void board_usb_charge_mode_init(void) */ for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++) usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE, - USB_DISALLOW_SUSPEND_CHARGE); + USB_DISALLOW_SUSPEND_CHARGE); } /* * usb_charge_init() is hooked in HOOK_PRIO_DEFAULT and set inhibit_charge to @@ -462,15 +457,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) } static const struct ppc_config_t ppc_syv682x_port0 = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static const struct ppc_config_t ppc_syv682x_port1 = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static void board_setup_ppc(void) @@ -478,11 +473,9 @@ static void board_setup_ppc(void) if (!support_syv_ppc()) return; - memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], - &ppc_syv682x_port0, + memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0, sizeof(struct ppc_config_t)); - memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], - &ppc_syv682x_port1, + memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1, sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH); @@ -490,14 +483,14 @@ static void board_setup_ppc(void) } DECLARE_HOOK(HOOK_INIT, board_setup_ppc, HOOK_PRIO_INIT_I2C + 2); -void board_hibernate_late(void) { - +void board_hibernate_late(void) +{ int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) @@ -528,7 +521,6 @@ void board_overcurrent_event(int port, int is_overcurrented) gpio_set_level(GPIO_USB_C_OC, !is_overcurrented); } - int ppc_get_alert_status(int port) { if (port == 0) -- cgit v1.2.1 From 0c3d16e854197800a4df35c98e9a780ac79b6677 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:29 -0600 Subject: board/beetley/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I78b5760757095b965fe5d039e942f123392d7630 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728049 Reviewed-by: Jeremy Bettis --- board/beetley/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/beetley/cbi_ssfc.c b/board/beetley/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/beetley/cbi_ssfc.c +++ b/board/beetley/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From a6b92b8e7a1e5cdc50317a9e2d5f689923ab51a5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:54 -0600 Subject: chip/stm32/clock-f.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff7547d671184915bbc0bea22fc8ec64eea6abd8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729459 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-f.c | 52 +++++++++++++++++++++------------------------------- 1 file changed, 21 insertions(+), 31 deletions(-) diff --git a/chip/stm32/clock-f.c b/chip/stm32/clock-f.c index 0ae4440d78..3fdc3bcc43 100644 --- a/chip/stm32/clock-f.c +++ b/chip/stm32/clock-f.c @@ -23,7 +23,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* Convert decimal to BCD */ static uint8_t u8_to_bcd(uint8_t val) @@ -41,8 +41,8 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) uint32_t sec; /* convert the hours field */ - sec = (((rtc_tr & 0x300000) >> 20) * 10 + - ((rtc_tr & 0xf0000) >> 16)) * 3600; + sec = (((rtc_tr & 0x300000) >> 20) * 10 + ((rtc_tr & 0xf0000) >> 16)) * + 3600; /* convert the minutes field */ sec += (((rtc_tr & 0x7000) >> 12) * 10 + ((rtc_tr & 0xf00) >> 8)) * 60; /* convert the seconds field */ @@ -122,10 +122,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) struct calendar_date time; uint32_t sec; - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); + time.year = + (((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16)); + time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8)); time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); sec = date_to_sec(time); @@ -258,8 +257,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, * If the caller doesn't specify subsecond delay (e.g. host command), * just align the alarm time to second. */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; + STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) : + 0; #ifdef CONFIG_HOSTCMD_RTC /* @@ -321,8 +320,7 @@ static void set_rtc_host_event(void) DECLARE_DEFERRED(set_rtc_host_event); #endif -test_mockable -void rtc_alarm_irq(void) +test_mockable void rtc_alarm_irq(void) { struct rtc_time_reg rtc; reset_rtc_alarm(&rtc); @@ -342,8 +340,7 @@ static void __rtc_alarm_irq(void) } DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); -__attribute__((weak)) -int clock_get_timer_freq(void) +__attribute__((weak)) int clock_get_timer_freq(void) { return clock_get_freq(); } @@ -416,9 +413,8 @@ static int command_system_rtc(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set ]", - "Get/set real-time clock"); +DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set ]", + "Get/set real-time clock"); #ifdef CONFIG_CMD_RTC_ALARM static int command_rtc_alarm_test(int argc, char **argv) @@ -433,7 +429,6 @@ static int command_rtc_alarm_test(int argc, char **argv) s = strtoi(argv[1], &e, 10); if (*e) return EC_ERROR_PARAM1; - } if (argc > 2) { us = strtoi(argv[2], &e, 10); @@ -445,8 +440,7 @@ static int command_rtc_alarm_test(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); + "[seconds [microseconds]]", "Test alarm"); #endif /* CONFIG_CMD_RTC_ALARM */ #endif /* CONFIG_CMD_RTC */ @@ -465,9 +459,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) { @@ -476,9 +469,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) rtc_set(p->time); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) { @@ -492,9 +484,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) set_rtc_alarm(p->time, 0, &rtc, 1); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm, + EC_VER_MASK(0)); static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) { @@ -505,8 +496,7 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm, + EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_RTC */ -- cgit v1.2.1 From ed44112c8e161a724eebd1b3c934a4af3f5ce11f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:23 -0600 Subject: power/alderlake_slg4bd44540.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ce0327ee2bb3085c4f4cabe06cbf2beb566c2ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730460 Reviewed-by: Jeremy Bettis --- power/alderlake_slg4bd44540.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/power/alderlake_slg4bd44540.c b/power/alderlake_slg4bd44540.c index 0f7b5cb3e4..0f2bd18d60 100644 --- a/power/alderlake_slg4bd44540.c +++ b/power/alderlake_slg4bd44540.c @@ -24,30 +24,29 @@ */ /* PG_EC_ALL_SYS_PWRGD high to VCCST_PWRGD high delay */ -#define VCCST_PWRGD_DELAY_MS 2 +#define VCCST_PWRGD_DELAY_MS 2 /* IMVP9_VRRDY high to PCH_PWROK high delay */ -#define PCH_PWROK_DELAY_MS 2 +#define PCH_PWROK_DELAY_MS 2 /* PG_EC_ALL_SYS_PWRGD high to EC_PCH_SYS_PWROK high delay */ -#define SYS_PWROK_DELAY_MS 45 +#define SYS_PWROK_DELAY_MS 45 /* IMVP9_VRRDY high timeout */ -#define VRRDY_TIMEOUT_MS 50 +#define VRRDY_TIMEOUT_MS 50 /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(signal, value) \ gpio_set_level_verbose(CC_CHIPSET, signal, value) #else -#define GPIO_SET_LEVEL(signal, value) \ - gpio_set_level(signal, value) +#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value) #endif /* The wait time is ~150 msec, allow for safety margin. */ -#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) +#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) /* Power signals list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -250,7 +249,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_G3S5: GPIO_SET_LEVEL(GPIO_EN_S5_RAILS, 1); @@ -262,7 +260,8 @@ enum power_state power_handle_state(enum power_state state) * signal doesn't go high within 250 msec then go back to G3. */ if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED, - IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) { + IN_PCH_SLP_SUS_WAIT_TIME_USEC) != + EC_SUCCESS) { CPRINTS("SLP_SUS_L didn't go high! Going back to G3."); return POWER_S5G3; } -- cgit v1.2.1 From 19cc2d0bc80391568807918c48336babfccf98e1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:34 -0600 Subject: zephyr/shim/src/cbi/cros_cbi_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3fc5c8ae3c506b6265958b3cf4957bcf1dc2fd30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730888 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/cbi/cros_cbi_fw_config.c | 38 ++++++++++++++------------------ 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/zephyr/shim/src/cbi/cros_cbi_fw_config.c b/zephyr/shim/src/cbi/cros_cbi_fw_config.c index e94c950a0f..71d68f6864 100644 --- a/zephyr/shim/src/cbi/cros_cbi_fw_config.c +++ b/zephyr/shim/src/cbi/cros_cbi_fw_config.c @@ -20,15 +20,15 @@ LOG_MODULE_REGISTER(cros_cbi_fw_config, LOG_LEVEL_ERR); * Statically count the number of bits set in a 32 bit constant expression. */ #define BIT_SET(v, b) ((v >> b) & 1) -#define BIT_COUNT(v) \ +#define BIT_COUNT(v) \ (BIT_SET(v, 31) + BIT_SET(v, 30) + BIT_SET(v, 29) + BIT_SET(v, 28) + \ BIT_SET(v, 27) + BIT_SET(v, 26) + BIT_SET(v, 25) + BIT_SET(v, 24) + \ BIT_SET(v, 23) + BIT_SET(v, 22) + BIT_SET(v, 21) + BIT_SET(v, 20) + \ BIT_SET(v, 19) + BIT_SET(v, 18) + BIT_SET(v, 17) + BIT_SET(v, 16) + \ BIT_SET(v, 15) + BIT_SET(v, 14) + BIT_SET(v, 13) + BIT_SET(v, 12) + \ - BIT_SET(v, 11) + BIT_SET(v, 10) + BIT_SET(v, 9) + BIT_SET(v, 8) + \ - BIT_SET(v, 7) + BIT_SET(v, 6) + BIT_SET(v, 5) + BIT_SET(v, 4) + \ - BIT_SET(v, 3) + BIT_SET(v, 2) + BIT_SET(v, 1) + BIT_SET(v, 0)) + BIT_SET(v, 11) + BIT_SET(v, 10) + BIT_SET(v, 9) + BIT_SET(v, 8) + \ + BIT_SET(v, 7) + BIT_SET(v, 6) + BIT_SET(v, 5) + BIT_SET(v, 4) + \ + BIT_SET(v, 3) + BIT_SET(v, 2) + BIT_SET(v, 1) + BIT_SET(v, 0)) /* * Shorthand macros to access properties on the field node. @@ -64,7 +64,7 @@ LOG_MODULE_REGISTER(cros_cbi_fw_config, LOG_LEVEL_ERR); * fw_config nodes, and another for the child field nodes in each * of the fw_config nodes. */ -#define PLUS_FIELD_SIZE(inst) + DT_PROP(inst, size) +#define PLUS_FIELD_SIZE(inst) +DT_PROP(inst, size) #define FIELDS_ALL_SIZE(inst) \ DT_FOREACH_CHILD_STATUS_OKAY(inst, PLUS_FIELD_SIZE) @@ -83,23 +83,21 @@ BUILD_ASSERT(TOTAL_FW_CONFIG_NODES_SIZE <= 32, * total of the sizes. They should match. */ #define OR_FIELD_SHIFT_MASK(id) | FW_SHIFT_MASK(id) -#define FIELDS_ALL_BITS_SET(inst) \ +#define FIELDS_ALL_BITS_SET(inst) \ DT_FOREACH_CHILD_STATUS_OKAY(inst, OR_FIELD_SHIFT_MASK) #define TOTAL_BITS_SET \ - (0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, \ - FIELDS_ALL_BITS_SET)) + (0 DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, FIELDS_ALL_BITS_SET)) BUILD_ASSERT(BIT_COUNT(TOTAL_BITS_SET) == TOTAL_FW_CONFIG_NODES_SIZE, - "CBI FW Config has overlapping fields"); + "CBI FW Config has overlapping fields"); /* * Validation for each assigned field values. * The value must fit within the parent's defined size. */ -#define FW_VALUE_BUILD_ASSERT(inst) \ - BUILD_ASSERT(DT_PROP(inst, value) < \ - (1 << FW_PARENT_SIZE(inst)), \ +#define FW_VALUE_BUILD_ASSERT(inst) \ + BUILD_ASSERT(DT_PROP(inst, value) < (1 << FW_PARENT_SIZE(inst)), \ "CBI FW Config value too big"); DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, FW_VALUE_BUILD_ASSERT) @@ -144,9 +142,9 @@ DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, FW_VALUE_BUILD_ASSERT) * The per-field case statement. * Extract the field value using the start and size. */ -#define FW_FIELD_CASE(id, cached, value) \ - case CBI_FW_CONFIG_ENUM(id): \ - *value = (cached >> FW_START(id)) & FW_MASK(id); \ +#define FW_FIELD_CASE(id, cached, value) \ + case CBI_FW_CONFIG_ENUM(id): \ + *value = (cached >> FW_START(id)) & FW_MASK(id); \ break; /* @@ -173,10 +171,9 @@ void cros_cbi_fw_config_init(void) LOG_INF("Read CBI FW Config : 0x%08X\n", cached_fw_config); } -static int cros_cbi_fw_config_get_field( - uint32_t cached_fw_config, - enum cbi_fw_config_field_id field_id, - uint32_t *value) +static int cros_cbi_fw_config_get_field(uint32_t cached_fw_config, + enum cbi_fw_config_field_id field_id, + uint32_t *value) { switch (field_id) { /* @@ -184,8 +181,7 @@ static int cros_cbi_fw_config_get_field( * and create cases for all of their child nodes. */ DT_FOREACH_STATUS_OKAY_VARGS(CBI_FW_CONFIG_COMPAT, - FW_FIELD_NODES, - cached_fw_config, + FW_FIELD_NODES, cached_fw_config, value) default: return -EINVAL; -- cgit v1.2.1 From 4476bb3b77793bdd452b33e4bc5646910c90eeea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:56 -0600 Subject: board/reef_mchp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idbc93346a5a2f3cc0ea4457743af5c3866db3a2d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728892 Reviewed-by: Jeremy Bettis --- board/reef_mchp/board.h | 61 ++++++++++++++++++++++++------------------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/board/reef_mchp/board.h b/board/reef_mchp/board.h index ad98fac829..cb6c105052 100644 --- a/board/reef_mchp/board.h +++ b/board/reef_mchp/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -24,14 +24,14 @@ #define CONFIG_CMD_ACCEL_INFO #define CONFIG_CMD_BATT_MFG_ACCESS #define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define BD9995X_IOUT_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V + BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V #define CONFIG_CHARGER_PSYS_READ #define BD9995X_PSYS_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW + BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW #define CONFIG_CMD_I2C_STRESS_TEST #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL @@ -41,7 +41,7 @@ #define CONFIG_CMD_I2C_STRESS_TEST_TCPC /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_SMART @@ -62,7 +62,7 @@ #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON -#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES +#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT @@ -89,7 +89,7 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ +#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ #define CONFIG_USB_PD_TCPM_ANX3429 /* Silicon on Reef is ANX3429 */ #define CONFIG_USB_PD_TCPM_PS8751 #define CONFIG_USB_PD_TCPM_TCPCI @@ -117,8 +117,8 @@ /* EC */ #define CONFIG_ADC #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_FPU #define CONFIG_HOSTCMD_FLASH_SPI_INFO #define CONFIG_I2C @@ -145,7 +145,7 @@ #define CONFIG_WIRELESS #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER #define CONFIG_WLAN_POWER_ACTIVE_LOW -#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER +#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER #define CONFIG_PWR_STATE_DISCHARGE_FULL /* @@ -171,7 +171,7 @@ #define CONFIG_FLASH_SIZE_BYTES 524288 #define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ +#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ /* * Enable 1 slot of secure temporary storage to support @@ -186,17 +186,17 @@ #define CONFIG_BOARD_PRE_INIT /* I2C ports */ -#define I2C_CONTROLLER_COUNT 4 -#define I2C_PORT_COUNT 5 - -#define I2C_PORT_GYRO MCHP_I2C_PORT6 -#define I2C_PORT_LID_ACCEL MCHP_I2C_PORT7 -#define I2C_PORT_ALS MCHP_I2C_PORT7 -#define I2C_PORT_BARO MCHP_I2C_PORT7 -#define I2C_PORT_BATTERY MCHP_I2C_PORT3 -#define I2C_PORT_CHARGER MCHP_I2C_PORT3 +#define I2C_CONTROLLER_COUNT 4 +#define I2C_PORT_COUNT 5 + +#define I2C_PORT_GYRO MCHP_I2C_PORT6 +#define I2C_PORT_LID_ACCEL MCHP_I2C_PORT7 +#define I2C_PORT_ALS MCHP_I2C_PORT7 +#define I2C_PORT_BARO MCHP_I2C_PORT7 +#define I2C_PORT_BATTERY MCHP_I2C_PORT3 +#define I2C_PORT_CHARGER MCHP_I2C_PORT3 /* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_ACCEL I2C_PORT_GYRO /* Sensors */ #define CONFIG_MKBP_EVENT @@ -222,7 +222,6 @@ /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -230,9 +229,9 @@ /* ADC signal */ enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ - ADC_TEMP_SENSOR_AMB, /* ADC1 */ - ADC_BOARD_ID, /* ADC2 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ + ADC_TEMP_SENSOR_AMB, /* ADC1 */ + ADC_BOARD_ID, /* ADC2 */ ADC_CH_COUNT }; @@ -271,7 +270,7 @@ enum sensor_id { BASE_GYRO, BASE_MAG, BASE_BARO, - LID_ALS, /* firmware-reef-9042.B doesn't have this */ + LID_ALS, /* firmware-reef-9042.B doesn't have this */ SENSOR_COUNT, }; @@ -294,16 +293,16 @@ enum reef_board_version { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Reset PD MCU */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From a74f50a59b900d3b7e386c1f971d2c365d9cf4be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:10 -0600 Subject: board/fluffy/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id523fa7fcdc2eea7175d24de3e54f49e73907791 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728374 Reviewed-by: Jeremy Bettis --- board/fluffy/board.c | 68 +++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/board/fluffy/board.c b/board/fluffy/board.c index 874195404b..3935411af8 100644 --- a/board/fluffy/board.c +++ b/board/fluffy/board.c @@ -19,20 +19,20 @@ #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Fluffy"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Fluffy"), /* This gets filled in at runtime. */ - [USB_STR_SERIALNO] = USB_STRING_DESC(""), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_SERIALNO] = USB_STRING_DESC(""), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Fluffy Shell"), }; @@ -106,20 +106,19 @@ static int command_cc_flip(int argc, char *argv[]) print_port_status(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip, - "", +DECLARE_CONSOLE_COMMAND(ccflip, command_cc_flip, "", "enable or disable flipping CC orientation"); /* * Support tca6416 I2C ioexpander. */ -#define GPIOX_I2C_ADDR_FLAGS 0x20 -#define GPIOX_IN_PORT_A 0x0 -#define GPIOX_IN_PORT_B 0x1 -#define GPIOX_OUT_PORT_A 0x2 -#define GPIOX_OUT_PORT_B 0x3 -#define GPIOX_DIR_PORT_A 0x6 -#define GPIOX_DIR_PORT_B 0x7 -#define I2C_PORT_MASTER 1 +#define GPIOX_I2C_ADDR_FLAGS 0x20 +#define GPIOX_IN_PORT_A 0x0 +#define GPIOX_IN_PORT_B 0x1 +#define GPIOX_OUT_PORT_A 0x2 +#define GPIOX_OUT_PORT_B 0x3 +#define GPIOX_DIR_PORT_A 0x6 +#define GPIOX_DIR_PORT_B 0x7 +#define I2C_PORT_MASTER 1 static void i2c_expander_init(void) { @@ -128,12 +127,12 @@ static void i2c_expander_init(void) /* * Setup P00, P02, P04, P10, and P12 on the I/O expander as an output. */ - i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, - GPIOX_DIR_PORT_A, 0xea); - i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, - GPIOX_DIR_PORT_B, 0xfa); + i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_A, + 0xea); + i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, GPIOX_DIR_PORT_B, + 0xfa); } -DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, i2c_expander_init, HOOK_PRIO_INIT_I2C + 1); /* Write to a GPIO register on the tca6416 I2C ioexpander. */ static void write_ioexpander(int bank, int gpio, int reg, int val) @@ -141,15 +140,13 @@ static void write_ioexpander(int bank, int gpio, int reg, int val) int tmp; /* Read output port register */ - i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, - reg + bank, &tmp); + i2c_read8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, &tmp); if (val) tmp |= BIT(gpio); else tmp &= ~BIT(gpio); /* Write back modified output port register */ - i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, - reg + bank, tmp); + i2c_write8(I2C_PORT_MASTER, GPIOX_I2C_ADDR_FLAGS, reg + bank, tmp); } enum led_ch { @@ -227,7 +224,6 @@ static void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - enum usb_mux { USB_MUX0 = 0, USB_MUX1, @@ -293,7 +289,7 @@ static int command_portctl(int argc, char **argv) gpio_set_level(enabled_port, 0); if (enabled_port != GPIO_EN_C0 + port) - CPRINTS("Port %d: disabled", enabled_port-GPIO_EN_C0); + CPRINTS("Port %d: disabled", enabled_port - GPIO_EN_C0); /* Allow time for an "unplug" to allow VBUS and CC to fall. */ usleep(1 * SECOND); @@ -309,17 +305,17 @@ static int command_portctl(int argc, char **argv) gpio_set_level(enabled_port, 1); if (port < 8) { - set_mux(USB_MUX0, 7-port); + set_mux(USB_MUX0, 7 - port); set_mux(USB_MUX2, 3); } else if (port < 16) { if (port < 14) - set_mux(USB_MUX1, 5-(port-8)); + set_mux(USB_MUX1, 5 - (port - 8)); else - set_mux(USB_MUX1, 7-(port-14)); + set_mux(USB_MUX1, 7 - (port - 14)); set_mux(USB_MUX2, 1); } else { - set_mux(USB_MUX2, 7-(port-16)); + set_mux(USB_MUX2, 7 - (port - 16)); } gpio_set_level(GPIO_EN_USB_MUX2, 1); @@ -341,7 +337,7 @@ static int command_status(int argc, char **argv) { int vbus_mv = adc_read_channel(ADC_PPVAR_VBUS_DUT); - CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv*7692/1000, + CPRINTS("PPVAR_VBUS_DUT: %dmV (raw: %d)", vbus_mv * 7692 / 1000, vbus_mv); print_port_status(); @@ -388,7 +384,8 @@ void show_output_voltage_on_leds(void) set_led(i, i < max_on_exclusive); act = (vbus_mv * 76667) / 10000; - if ((vbus_mv > prev_vbus_mv+2) || (vbus_mv < prev_vbus_mv-2)) { + if ((vbus_mv > prev_vbus_mv + 2) || + (vbus_mv < prev_vbus_mv - 2)) { CPRINTS("PPVAR_VBUS_DUT: %d mV (raw: %d)", act, vbus_mv); prev_vbus_mv = vbus_mv; @@ -400,6 +397,5 @@ void show_output_voltage_on_leds(void) * a hook with a HOOK_TICK period is to allow the LED sweep sequence * when the board boots up. */ - hook_call_deferred(&show_output_voltage_on_leds_data, - 500 * MSEC); + hook_call_deferred(&show_output_voltage_on_leds_data, 500 * MSEC); } -- cgit v1.2.1 From db3cf1e61a6293955acd41d3646eaab5847da5be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:18 -0600 Subject: chip/stm32/crc_hw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I209f153dd09eb4f65a9b53c5f179d5a2dbb91179 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729487 Reviewed-by: Jeremy Bettis --- chip/stm32/crc_hw.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/crc_hw.h b/chip/stm32/crc_hw.h index 2a50d5760e..7c58a7a00e 100644 --- a/chip/stm32/crc_hw.h +++ b/chip/stm32/crc_hw.h @@ -17,8 +17,8 @@ static inline void crc32_init(void) /* Delay 1 AHB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_AHB, 1); /* reset CRC state */ - STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT - | STM32_CRC_CR_REV_IN_WORD; + STM32_CRC_CR = STM32_CRC_CR_RESET | STM32_CRC_CR_REV_OUT | + STM32_CRC_CR_REV_IN_WORD; while (STM32_CRC_CR & 1) ; } -- cgit v1.2.1 From b5a984d28da9102b17223a50a3d6b56f3a734af8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:56 -0600 Subject: board/lalala/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I60b2682eb6bc0a2028f4673bdd2be3da46d701f9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728605 Reviewed-by: Jeremy Bettis --- board/lalala/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lalala/cbi_ssfc.c b/board/lalala/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/lalala/cbi_ssfc.c +++ b/board/lalala/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 28a9515b30792edd9fffb786802311057261c4db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:26 -0600 Subject: driver/temp_sensor/tmp006.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f69d0a7245f52ff76fce309cc60d19fe13ca6c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729879 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp006.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/driver/temp_sensor/tmp006.h b/driver/temp_sensor/tmp006.h index 594dbc711a..6d1b13def3 100644 --- a/driver/temp_sensor/tmp006.h +++ b/driver/temp_sensor/tmp006.h @@ -9,11 +9,11 @@ #define __CROS_EC_TMP006_H /* Registers within the TMP006 chip */ -#define TMP006_REG_VOBJ 0x00 -#define TMP006_REG_TDIE 0x01 -#define TMP006_REG_CONFIG 0x02 +#define TMP006_REG_VOBJ 0x00 +#define TMP006_REG_TDIE 0x01 +#define TMP006_REG_CONFIG 0x02 #define TMP006_REG_MANUFACTURER_ID 0xfe -#define TMP006_REG_DEVICE_ID 0xff +#define TMP006_REG_DEVICE_ID 0xff /* I2C address components */ #define TMP006_ADDR(PORT, REG) ((PORT << 16) + REG) @@ -22,7 +22,7 @@ struct tmp006_t { const char *name; - int addr_flags; /* I2C address formed by TMP006_ADDR macro. */ + int addr_flags; /* I2C address formed by TMP006_ADDR macro. */ }; /* Names and addresses of the sensors we have */ @@ -40,4 +40,4 @@ extern const struct tmp006_t tmp006_sensors[]; */ int tmp006_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_TMP006_H */ +#endif /* __CROS_EC_TMP006_H */ -- cgit v1.2.1 From 8fc6e3d0ff7bb1e6e7c25a9d08a498d07642a910 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:07 -0600 Subject: board/blipper/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3fac0040cf3a00e30e292974f95992cba80770fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728035 Reviewed-by: Jeremy Bettis --- board/blipper/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/blipper/usb_pd_policy.c b/board/blipper/usb_pd_policy.c index b7c0ca21df..814287a417 100644 --- a/board/blipper/usb_pd_policy.c +++ b/board/blipper/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From a64484a564530621607bf627d7d8219553dcc98b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:04 -0600 Subject: board/kukui_scp/isp_p2_srv.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I221ee9c264a774b80bc21ced3a18b1f99f93fe29 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728596 Reviewed-by: Jeremy Bettis --- board/kukui_scp/isp_p2_srv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kukui_scp/isp_p2_srv.h b/board/kukui_scp/isp_p2_srv.h index 70fb0673de..63db5791e3 100644 --- a/board/kukui_scp/isp_p2_srv.h +++ b/board/kukui_scp/isp_p2_srv.h @@ -13,7 +13,8 @@ struct dip_msg_service { unsigned char msg[288]; }; -BUILD_ASSERT(member_size(struct dip_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE); +BUILD_ASSERT(member_size(struct dip_msg_service, msg) <= + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void dip_msg_handler(void *data); -- cgit v1.2.1 From 784138d527359de9b5380cfdf88691ae971bdb44 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:57 -0600 Subject: driver/charger/isl9241.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2207fde747134c9f0c48813788e27708f886ade Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729965 Reviewed-by: Jeremy Bettis --- driver/charger/isl9241.h | 148 +++++++++++++++++++++++------------------------ 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h index f6f7844ef5..769ee9c921 100644 --- a/driver/charger/isl9241.h +++ b/driver/charger/isl9241.h @@ -10,21 +10,21 @@ #include "driver/charger/isl9241_public.h" -#define CHARGER_NAME "ISL9241" -#define CHARGE_V_MAX 18304 -#define CHARGE_V_MIN 64 -#define CHARGE_V_STEP 8 +#define CHARGER_NAME "ISL9241" +#define CHARGE_V_MAX 18304 +#define CHARGE_V_MIN 64 +#define CHARGE_V_STEP 8 /* * When the default sense resistor value is used, register values * represent mA. For other sense resistors values, register * values must be scaled accordingly to convert to mA. */ -#define CHARGE_I_MAX 6140 -#define CHARGE_I_MIN 4 -#define CHARGE_I_STEP 4 -#define INPUT_I_MAX 6140 -#define INPUT_I_MIN 4 -#define INPUT_I_STEP 4 +#define CHARGE_I_MAX 6140 +#define CHARGE_I_MIN 4 +#define CHARGE_I_STEP 4 +#define INPUT_I_MAX 6140 +#define INPUT_I_MIN 4 +#define INPUT_I_STEP 4 /* Registers */ @@ -32,30 +32,30 @@ * ChargeCurrentLimit [12:2] 11-bit (0x0000h = disables fast charging, * trickle charging is allowed) */ -#define ISL9241_REG_CHG_CURRENT_LIMIT 0x14 +#define ISL9241_REG_CHG_CURRENT_LIMIT 0x14 /* MaxSystemVoltage [14:3] 12-bit, (0x0000h = disables switching) */ -#define ISL9241_REG_MAX_SYSTEM_VOLTAGE 0x15 +#define ISL9241_REG_MAX_SYSTEM_VOLTAGE 0x15 -#define ISL9241_REG_CONTROL7 0x38 +#define ISL9241_REG_CONTROL7 0x38 /* Configures various charger options */ -#define ISL9241_REG_CONTROL0 0x39 +#define ISL9241_REG_CONTROL0 0x39 /* 2: Input Voltage Regulation (0 = Enable (default), 1 = Disable) */ -#define ISL9241_CONTROL0_INPUT_VTG_REGULATION BIT(2) -#define ISL9241_CONTROL0_EN_VIN_VOUT_COMP BIT(5) -#define ISL9241_CONTROL0_EN_CHARGE_PUMPS BIT(6) -#define ISL9241_CONTROL0_EN_BYPASS_GATE BIT(11) -#define ISL9241_CONTROL0_NGATE_OFF BIT(12) +#define ISL9241_CONTROL0_INPUT_VTG_REGULATION BIT(2) +#define ISL9241_CONTROL0_EN_VIN_VOUT_COMP BIT(5) +#define ISL9241_CONTROL0_EN_CHARGE_PUMPS BIT(6) +#define ISL9241_CONTROL0_EN_BYPASS_GATE BIT(11) +#define ISL9241_CONTROL0_NGATE_OFF BIT(12) -#define ISL9241_REG_INFORMATION1 0x3A -#define ISL9241_REG_ADAPTER_CUR_LIMIT2 0x3B +#define ISL9241_REG_INFORMATION1 0x3A +#define ISL9241_REG_ADAPTER_CUR_LIMIT2 0x3B /* Configures various charger options */ -#define ISL9241_REG_CONTROL1 0x3C -#define ISL9241_CONTROL1_PSYS BIT(3) -#define ISL9241_CONTROL1_BGATE_OFF BIT(6) -#define ISL9241_CONTROL1_LEARN_MODE BIT(12) +#define ISL9241_REG_CONTROL1 0x3C +#define ISL9241_CONTROL1_PSYS BIT(3) +#define ISL9241_CONTROL1_BGATE_OFF BIT(6) +#define ISL9241_CONTROL1_LEARN_MODE BIT(12) /* * 9:7 - Switching Frequency */ @@ -63,14 +63,14 @@ #define ISL9241_CONTROL1_SWITCHING_FREQ_1420KHZ 0 #define ISL9241_CONTROL1_SWITCHING_FREQ_1180KHZ 1 #define ISL9241_CONTROL1_SWITCHING_FREQ_1020KHZ 2 -#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ 3 -#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ 4 -#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ 5 -#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ 6 -#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ 7 +#define ISL9241_CONTROL1_SWITCHING_FREQ_890KHZ 3 +#define ISL9241_CONTROL1_SWITCHING_FREQ_808KHZ 4 +#define ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ 5 +#define ISL9241_CONTROL1_SWITCHING_FREQ_656KHZ 6 +#define ISL9241_CONTROL1_SWITCHING_FREQ_600KHZ 7 /* Configures various charger options */ -#define ISL9241_REG_CONTROL2 0x3D +#define ISL9241_REG_CONTROL2 0x3D /* * 15:13 - Trickle Charging Current * <000> 32mA (do not use) @@ -82,79 +82,79 @@ * <110> 224mA * <111> 256mA */ -#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr) ((((curr) >> 5) - 1) << 13) +#define ISL9241_CONTROL2_TRICKLE_CHG_CURR(curr) ((((curr) >> 5) - 1) << 13) /* 12 - Two-Level Adapter Current Limit */ -#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR BIT(12) +#define ISL9241_CONTROL2_TWO_LEVEL_ADP_CURR BIT(12) /* 10:9 PROCHOT# debounce time in uS */ -#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK GENMASK(10, 9) -#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500 (2 << 9) -#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000 (3 << 9) +#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK GENMASK(10, 9) +#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_500 (2 << 9) +#define ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000 (3 << 9) /* MinSystemVoltage [13:6] 8-bit (0x0000h = disables all battery charging) */ -#define ISL9241_REG_MIN_SYSTEM_VOLTAGE 0x3E +#define ISL9241_REG_MIN_SYSTEM_VOLTAGE 0x3E -#define ISL9241_REG_ADAPTER_CUR_LIMIT1 0x3F -#define ISL9241_REG_ACOK_REFERENCE 0x40 -#define ISL9241_REG_CONTROL6 0x43 -#define ISL9241_REG_AC_PROCHOT 0x47 -#define ISL9241_REG_DC_PROCHOT 0x48 -#define ISL9241_REG_OTG_VOLTAGE 0x49 -#define ISL9241_REG_OTG_CURRENT 0x4A +#define ISL9241_REG_ADAPTER_CUR_LIMIT1 0x3F +#define ISL9241_REG_ACOK_REFERENCE 0x40 +#define ISL9241_REG_CONTROL6 0x43 +#define ISL9241_REG_AC_PROCHOT 0x47 +#define ISL9241_REG_DC_PROCHOT 0x48 +#define ISL9241_REG_OTG_VOLTAGE 0x49 +#define ISL9241_REG_OTG_CURRENT 0x4A -#define ISL9241_MV_TO_ACOK_REFERENCE(mv) (((mv) / 96) << 6) +#define ISL9241_MV_TO_ACOK_REFERENCE(mv) (((mv) / 96) << 6) /* VIN Voltage (ADP Min Voltage) (default 4.096V) */ -#define ISL9241_REG_VIN_VOLTAGE 0x4B +#define ISL9241_REG_VIN_VOLTAGE 0x4B /* Configures various charger options */ -#define ISL9241_REG_CONTROL3 0x4C +#define ISL9241_REG_CONTROL3 0x4C /* 14: ACLIM Reload (0 - reload, 1 - Do not reload */ -#define ISL9241_CONTROL3_ACLIM_RELOAD BIT(14) +#define ISL9241_CONTROL3_ACLIM_RELOAD BIT(14) /* 5: Input Current Limit Loop (0 - Enable, 1 - Disable */ -#define ISL9241_CONTROL3_INPUT_CURRENT_LIMIT BIT(5) +#define ISL9241_CONTROL3_INPUT_CURRENT_LIMIT BIT(5) /* 2: Digital Reset (0 - Idle, 1 - Reset */ -#define ISL9241_CONTROL3_DIGITAL_RESET BIT(2) +#define ISL9241_CONTROL3_DIGITAL_RESET BIT(2) /* 0: Enable ADC (0 - Active when charging, 1 - Active always) */ -#define ISL9241_CONTROL3_ENABLE_ADC BIT(0) +#define ISL9241_CONTROL3_ENABLE_ADC BIT(0) /* Indicates various charger status */ -#define ISL9241_REG_INFORMATION2 0x4D +#define ISL9241_REG_INFORMATION2 0x4D /* 12: BATGONE pin status (0 = Battery is present, 1 = No battery) */ -#define ISL9241_INFORMATION2_BATGONE_PIN BIT(12) +#define ISL9241_INFORMATION2_BATGONE_PIN BIT(12) /* 14: ACOK pin status (0 = No adapter, 1 = Adapter is present) */ -#define ISL9241_INFORMATION2_ACOK_PIN BIT(14) +#define ISL9241_INFORMATION2_ACOK_PIN BIT(14) -#define ISL9241_REG_CONTROL4 0x4E -#define ISL9241_CONTROL4_FORCE_BUCK_MODE BIT(10) +#define ISL9241_REG_CONTROL4 0x4E +#define ISL9241_CONTROL4_FORCE_BUCK_MODE BIT(10) /* 11: Rsense (Rs1:Rs2) ratio for PSYS (0 - 2:1, 1 - 1:1) */ -#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO BIT(11) +#define ISL9241_CONTROL4_PSYS_RSENSE_RATIO BIT(11) /* 13: Enable VSYS slew rate control (0 - disable, 1 - enable) */ -#define ISL9241_CONTROL4_SLEW_RATE_CTRL BIT(13) +#define ISL9241_CONTROL4_SLEW_RATE_CTRL BIT(13) -#define ISL9241_REG_CONTROL5 0x4F -#define ISL9241_REG_NTC_ADC_RESULTS 0x80 -#define ISL9241_REG_VBAT_ADC_RESULTS 0x81 -#define ISL9241_REG_TJ_ADC_RESULTS 0x82 +#define ISL9241_REG_CONTROL5 0x4F +#define ISL9241_REG_NTC_ADC_RESULTS 0x80 +#define ISL9241_REG_VBAT_ADC_RESULTS 0x81 +#define ISL9241_REG_TJ_ADC_RESULTS 0x82 /* ADC result for adapter current measurements, LSB = 22.2mA */ -#define ISL9241_REG_IADP_ADC_RESULTS 0x83 +#define ISL9241_REG_IADP_ADC_RESULTS 0x83 -#define ISL9241_REG_DC_ADC_RESULTS 0x84 -#define ISL9241_REG_CC_ADC_RESULTS 0x85 -#define ISL9241_REG_VSYS_ADC_RESULTS 0x86 -#define ISL9241_REG_VIN_ADC_RESULTS 0x87 -#define ISL9241_REG_INFORMATION3 0x90 -#define ISL9241_REG_INFORMATION4 0x91 -#define ISL9241_REG_MANUFACTURER_ID 0xFE -#define ISL9241_REG_DEVICE_ID 0xFF +#define ISL9241_REG_DC_ADC_RESULTS 0x84 +#define ISL9241_REG_CC_ADC_RESULTS 0x85 +#define ISL9241_REG_VSYS_ADC_RESULTS 0x86 +#define ISL9241_REG_VIN_ADC_RESULTS 0x87 +#define ISL9241_REG_INFORMATION3 0x90 +#define ISL9241_REG_INFORMATION4 0x91 +#define ISL9241_REG_MANUFACTURER_ID 0xFE +#define ISL9241_REG_DEVICE_ID 0xFF -#define ISL9241_VIN_ADC_BIT_OFFSET 6 -#define ISL9241_VIN_ADC_STEP_MV 96 +#define ISL9241_VIN_ADC_BIT_OFFSET 6 +#define ISL9241_VIN_ADC_STEP_MV 96 /* * Used to reset ACOKref register to normal value to detect low voltage (5V or * 9V) adapter during next plug in event */ -#define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV 3600 +#define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV 3600 #endif /* __CROS_EC_ISL9241_H */ -- cgit v1.2.1 From 9fdc9a5e9c9dd3133be5b591c2bc0c40b645c5fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:33 -0600 Subject: include/keyboard_scan.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09fc86b91b515ad82135273003bd0622e0adc03f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730309 Reviewed-by: Jeremy Bettis --- include/keyboard_scan.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h index 1e164bca37..77c7ef9c27 100644 --- a/include/keyboard_scan.h +++ b/include/keyboard_scan.h @@ -89,10 +89,10 @@ const uint8_t *keyboard_scan_get_state(void); enum kb_scan_disable_masks { /* Reasons why keyboard scanning should be disabled */ - KB_SCAN_DISABLE_LID_CLOSED = (1<<0), - KB_SCAN_DISABLE_POWER_BUTTON = (1<<1), - KB_SCAN_DISABLE_LID_ANGLE = (1<<2), - KB_SCAN_DISABLE_USB_SUSPENDED = (1<<3), + KB_SCAN_DISABLE_LID_CLOSED = (1 << 0), + KB_SCAN_DISABLE_POWER_BUTTON = (1 << 1), + KB_SCAN_DISABLE_LID_ANGLE = (1 << 2), + KB_SCAN_DISABLE_USB_SUSPENDED = (1 << 3), }; #ifdef HAS_TASK_KEYSCAN @@ -111,7 +111,9 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask); void clear_typematic_key(void); #else static inline void keyboard_scan_enable(int enable, - enum kb_scan_disable_masks mask) { } + enum kb_scan_disable_masks mask) +{ +} #endif #ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE @@ -136,7 +138,9 @@ int keyboard_get_keyboard_id(void); #ifdef CONFIG_KEYBOARD_RUNTIME_KEYS void set_vol_up_key(uint8_t row, uint8_t col); #else -static inline void set_vol_up_key(uint8_t row, uint8_t col) {} +static inline void set_vol_up_key(uint8_t row, uint8_t col) +{ +} #endif #ifdef CONFIG_KEYBOARD_FACTORY_TEST @@ -148,5 +152,4 @@ extern const int keyboard_factory_scan_pins[][2]; extern const int keyboard_factory_scan_pins_used; #endif - -#endif /* __CROS_EC_KEYBOARD_SCAN_H */ +#endif /* __CROS_EC_KEYBOARD_SCAN_H */ -- cgit v1.2.1 From a7cb9e83d2b7bce928c6af2bbb09753be9d43916 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:19 -0600 Subject: include/charge_state.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3c4df26feb745c64c9890858de232088b61f1e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730222 Reviewed-by: Jeremy Bettis --- include/charge_state.h | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/include/charge_state.h b/include/charge_state.h index ed777c1a64..9cb24381ed 100644 --- a/include/charge_state.h +++ b/include/charge_state.h @@ -14,14 +14,14 @@ #define PRECHARGE_TIMEOUT CONFIG_BATTERY_PRECHARGE_TIMEOUT /* Power state task polling periods in usec */ -#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE -#define CHARGE_POLL_PERIOD_LONG (MSEC * 500) -#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250) -#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100) -#define CHARGE_MIN_SLEEP_USEC (MSEC * 50) +#define CHARGE_POLL_PERIOD_VERY_LONG MINUTE +#define CHARGE_POLL_PERIOD_LONG (MSEC * 500) +#define CHARGE_POLL_PERIOD_CHARGE (MSEC * 250) +#define CHARGE_POLL_PERIOD_SHORT (MSEC * 100) +#define CHARGE_MIN_SLEEP_USEC (MSEC * 50) /* If a board hasn't provided a max sleep, use 1 minute as default */ #ifndef CHARGE_MAX_SLEEP_USEC -#define CHARGE_MAX_SLEEP_USEC MINUTE +#define CHARGE_MAX_SLEEP_USEC MINUTE #endif /* Power states */ @@ -61,20 +61,13 @@ enum charge_state { /* Debugging constants, in the same order as enum charge_state. This string * table was moved here to sync with enum above. */ -#define CHARGE_STATE_NAME_TABLE { \ - "unchange", \ - "init", \ - "reinit", \ - "idle0", \ - "idle", \ - "discharge", \ - "discharge_full", \ - "charge", \ - "charge_near_full", \ - "error" \ +#define CHARGE_STATE_NAME_TABLE \ + { \ + "unchange", "init", "reinit", "idle0", "idle", "discharge", \ + "discharge_full", "charge", "charge_near_full", \ + "error" \ } - /* End of CHARGE_STATE_NAME_TABLE macro */ - +/* End of CHARGE_STATE_NAME_TABLE macro */ /** * Return current charge state. @@ -159,8 +152,7 @@ int charge_get_battery_temp(int idx, int *temp_ptr); */ const struct batt_params *charger_current_battery_params(void); - /* Config Charger */ #include "charge_state_v2.h" -#endif /* __CROS_EC_CHARGE_STATE_H */ +#endif /* __CROS_EC_CHARGE_STATE_H */ -- cgit v1.2.1 From 2d6f5008595a3fc938bbd33ec059a6ba6e713121 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:49 -0600 Subject: include/compiler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba7a1de4d7136406d090cb1f8740403cfcdfd21f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730231 Reviewed-by: Jeremy Bettis --- include/compiler.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/compiler.h b/include/compiler.h index b3d99e26af..904073263c 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -21,7 +21,7 @@ * macro. */ #ifndef typeof -#define typeof(x) __typeof__(x) +#define typeof(x) __typeof__(x) #endif /** -- cgit v1.2.1 From c74910cd378bbb01fbacf0a6a82b5416c29b584a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:06 -0600 Subject: zephyr/projects/nissa/src/nivviks/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie09b34c68dad27eecdc1659c1548cca13302d8e6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730791 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nivviks/fan.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/zephyr/projects/nissa/src/nivviks/fan.c b/zephyr/projects/nissa/src/nivviks/fan.c index b177c6eab1..95f3a32935 100644 --- a/zephyr/projects/nissa/src/nivviks/fan.c +++ b/zephyr/projects/nissa/src/nivviks/fan.c @@ -28,8 +28,7 @@ static void fan_init(void) */ ret = cros_cbi_get_fw_config(FW_FAN, &val); if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", - FW_FAN); + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); return; } if (val != FW_FAN_PRESENT) { @@ -37,9 +36,8 @@ static void fan_init(void) fan_set_count(0); } else { /* Configure the fan enable GPIO */ - gpio_pin_configure_dt( - GPIO_DT_FROM_NODELABEL(gpio_fan_enable), - GPIO_OUTPUT); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); } } DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); -- cgit v1.2.1 From 9f7fb8479b370a1d4dc6e4a5a7ae2c7ff7134d93 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:24 -0600 Subject: board/terrador/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2345fb48630f5c709f44b8d1636130dd3da8b11a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729017 Reviewed-by: Jeremy Bettis --- board/terrador/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/terrador/led.c b/board/terrador/led.c index 640312bd64..18bbb8c170 100644 --- a/board/terrador/led.c +++ b/board/terrador/led.c @@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = { const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map[] = { - /* Green, Red, Blue */ - [EC_LED_COLOR_GREEN] = { 100, 0, 0 }, - [EC_LED_COLOR_RED] = { 0, 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + /* Green, Red, Blue */ + [EC_LED_COLOR_GREEN] = { 100, 0, 0 }, + [EC_LED_COLOR_RED] = { 0, 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, /* The green LED seems to be brighter than the others, so turn down * green from its natural level for these secondary colors. */ - [EC_LED_COLOR_YELLOW] = { 70, 100, 0 }, - [EC_LED_COLOR_WHITE] = { 70, 100, 100 }, - [EC_LED_COLOR_AMBER] = { 20, 100, 0 }, + [EC_LED_COLOR_YELLOW] = { 70, 100, 0 }, + [EC_LED_COLOR_WHITE] = { 70, 100, 100 }, + [EC_LED_COLOR_AMBER] = { 20, 100, 0 }, }; struct pwm_led pwm_leds[] = { -- cgit v1.2.1 From 32b77db41d0806e83b9f5404911b5e977ccacd26 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:25 -0600 Subject: board/jinlon/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib42dfab52680deaf4ce200bc3db5433e40b63261 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728476 Reviewed-by: Jeremy Bettis --- board/jinlon/led.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/board/jinlon/led.c b/board/jinlon/led.c index 4cef6dc3ae..88652dd797 100644 --- a/board/jinlon/led.c +++ b/board/jinlon/led.c @@ -25,11 +25,9 @@ #define LED_ON_TICKS 5 #define POWER_LED_ON_TICKS 2 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -37,7 +35,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color_battery(int port, enum led_color color) @@ -159,9 +157,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(0, (battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_battery( + 0, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(0, LED_OFF); } @@ -170,17 +171,19 @@ static void led_set_battery(void) led_set_color_battery(1, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; @@ -200,9 +203,10 @@ static void led_set_power(void) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY)) - led_set_color_power((power_tick % - LED_TICKS_PER_CYCLE < POWER_LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_power((power_tick % LED_TICKS_PER_CYCLE < + POWER_LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 7461cb01de461dd86571733b9b3fff239f9ed55e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:52 -0600 Subject: chip/npcx/lct_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f259f85b7851a4404705fccfe97db2f45462f4d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729402 Reviewed-by: Jeremy Bettis --- chip/npcx/lct_chip.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/chip/npcx/lct_chip.h b/chip/npcx/lct_chip.h index 197c189f43..8915bdf047 100644 --- a/chip/npcx/lct_chip.h +++ b/chip/npcx/lct_chip.h @@ -10,10 +10,7 @@ #define NPCX_LCT_MAX (16 * SECS_PER_WEEK - 1) -enum NPCX_LCT_PWR_SRC { - NPCX_LCT_PWR_SRC_VCC1, - NPCX_LCT_PWR_SRC_VSBY -}; +enum NPCX_LCT_PWR_SRC { NPCX_LCT_PWR_SRC_VCC1, NPCX_LCT_PWR_SRC_VSBY }; void npcx_lct_config(int seconds, int psl_ena, int int_ena); void npcx_lct_enable(uint8_t enable); @@ -25,4 +22,4 @@ int npcx_lct_is_event_set(void); /* return the current time of LCT in second */ uint32_t npcx_lct_get_time(void); -#endif /* __CROS_EC_LCT_CHIP_H */ +#endif /* __CROS_EC_LCT_CHIP_H */ -- cgit v1.2.1 From b82b45af00ff3483af7d7acc777205071e876ffb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:03 -0600 Subject: baseboard/trogdor/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3bae4aa76ded0cd582a65559b68f84ae087d0443 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727943 Reviewed-by: Jeremy Bettis --- baseboard/trogdor/baseboard.h | 88 +++++++++++++++++++++---------------------- 1 file changed, 43 insertions(+), 45 deletions(-) diff --git a/baseboard/trogdor/baseboard.h b/baseboard/trogdor/baseboard.h index d65fb2dc1e..1511e4cdf6 100644 --- a/baseboard/trogdor/baseboard.h +++ b/baseboard/trogdor/baseboard.h @@ -13,12 +13,12 @@ * The sensor stack is generating a lot of activity. * They can be enabled through the console command 'chan'. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_SPI_FLASH_REGS @@ -142,13 +142,13 @@ #define CONFIG_CMD_ACCEL_INFO /* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Chipset */ #define CONFIG_CHIPSET_SC7180 @@ -166,56 +166,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* I2C Ports */ #define I2C_PORT_BATTERY I2C_PORT_POWER #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* UART */ #define CONFIG_CMD_CHARGEN /* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) /* And the MKBP events */ #ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #else #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) + (BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #endif #endif /* __CROS_EC_BASEBOARD_H */ -- cgit v1.2.1 From ca0075fcddc16586d2b8646c686cb72030544efd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:46 -0600 Subject: core/cortex-m/llsr.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I561629bff28f8024968b05dac0c6fef69e161973 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729822 Reviewed-by: Jeremy Bettis --- core/cortex-m/llsr.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/core/cortex-m/llsr.c b/core/cortex-m/llsr.c index 616b8653db..85f4f7d804 100644 --- a/core/cortex-m/llsr.c +++ b/core/cortex-m/llsr.c @@ -38,13 +38,11 @@ static int command_llsr(int argc, char **argv) const struct { uint32_t shift_by; uint64_t result; - } cases[] = { - {0, start}, - {16, 0x123456789ABCull}, - {32, 0x12345678u}, - {48, 0x1234u}, - {64, 0u} - }; + } cases[] = { { 0, start }, + { 16, 0x123456789ABCull }, + { 32, 0x12345678u }, + { 48, 0x1234u }, + { 64, 0u } }; for (x = 0; x < ARRAY_SIZE(cases); ++x) { if ((start >> cases[x].shift_by) != cases[x].result) { @@ -58,8 +56,7 @@ static int command_llsr(int argc, char **argv) } DECLARE_CONSOLE_COMMAND( - llsrtest, command_llsr, - "", - "Run tests against the LLSR ABI. Prints SUCCESS or FAILURE."); + llsrtest, command_llsr, "", + "Run tests against the LLSR ABI. Prints SUCCESS or FAILURE."); -#endif /* CONFIG_LLSR_TEST */ +#endif /* CONFIG_LLSR_TEST */ -- cgit v1.2.1 From f53ef40aaba8fcaf6b510fe27611d728e14360a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:54 -0600 Subject: board/dewatt/board_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia0126a44862ac9b348c2411cf4311fd36bf06128 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728199 Reviewed-by: Jeremy Bettis --- board/dewatt/board_fw_config.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/dewatt/board_fw_config.c b/board/dewatt/board_fw_config.c index e6dbcadb92..40e19aaca8 100644 --- a/board/dewatt/board_fw_config.c +++ b/board/dewatt/board_fw_config.c @@ -14,7 +14,8 @@ bool board_is_convertible(void) bool board_has_kblight(void) { return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET, - FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES); + FW_CONFIG_KBLIGHT_WIDTH) == + FW_CONFIG_KBLIGHT_YES); } enum board_usb_c1_mux board_get_usb_c1_mux(void) -- cgit v1.2.1 From b315a91aac2ce3e48627225b3b928343ded7e000 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:58 -0600 Subject: board/reef_mchp/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibef5cfc34482af73ea5a5ac0d9f6dd87ecd4c9c0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728893 Reviewed-by: Jeremy Bettis --- board/reef_mchp/led.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/board/reef_mchp/led.c b/board/reef_mchp/led.c index ca49fe4ed5..f80d792a23 100644 --- a/board/reef_mchp/led.c +++ b/board/reef_mchp/led.c @@ -27,8 +27,7 @@ #define LED_ON_1SEC_TICKS 1 #define LED_ON_2SECS_TICKS 2 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -36,7 +35,7 @@ enum led_color { LED_OFF = 0, LED_BLUE, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -113,16 +112,19 @@ static void led_set_battery(void) } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Blink once every four seconds. */ led_set_color_battery( - (suspend_ticks % LED_TOTAL_4SECS_TICKS) - < LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF); + (suspend_ticks % LED_TOTAL_4SECS_TICKS) < + LED_ON_1SEC_TICKS ? + LED_AMBER : + LED_OFF); } else { led_set_color_battery(LED_OFF); } break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % LED_TOTAL_2SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS < + LED_ON_1SEC_TICKS) ? + LED_AMBER : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_BLUE); @@ -131,7 +133,9 @@ static void led_set_battery(void) if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) led_set_color_battery( (battery_ticks % LED_TOTAL_4SECS_TICKS < - LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE); + LED_ON_2SECS_TICKS) ? + LED_AMBER : + LED_BLUE); else led_set_color_battery(LED_BLUE); break; -- cgit v1.2.1 From eb00213ae063012a2222b75d0ba29fbd71677382 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:14 -0600 Subject: board/herobrine/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a5e6111d40bc6e7d07d085a5eea4dac6f45b750 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728305 Reviewed-by: Jeremy Bettis --- board/herobrine/usbc_config.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/board/herobrine/usbc_config.c b/board/herobrine/usbc_config.c index 93ec401171..2bf0133eaf 100644 --- a/board/herobrine/usbc_config.c +++ b/board/herobrine/usbc_config.c @@ -23,8 +23,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO Interrupt Handlers */ void tcpc_alert_event(enum gpio_signal signal) @@ -84,16 +84,12 @@ void ppc_interrupt(enum gpio_signal signal) /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -186,7 +182,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -232,8 +228,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -261,7 +256,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -285,23 +279,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From 95d20a21e1539c9c6f8698738234097e91f17687 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:55 -0600 Subject: board/arcada_ish/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0e26940105c98299bcf19dc5f4885b93ff8e80f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727992 Reviewed-by: Jeremy Bettis --- board/arcada_ish/board.h | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/board/arcada_ish/board.h b/board/arcada_ish/board.h index bf05a48697..7275714aab 100644 --- a/board/arcada_ish/board.h +++ b/board/arcada_ish/board.h @@ -16,7 +16,7 @@ #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* ISH specific*/ -#undef CONFIG_DEBUG_ASSERT +#undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL /* EC */ #define CONFIG_FLASH_SIZE_BYTES 0x80000 @@ -24,13 +24,13 @@ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define CONFIG_ACCEL_LNG2DM /* Base sensor: LNG2DM - * (uses LIS2DH driver) - */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Lid sensor: LSM6DS3 - * (uses LSM6DSM driver) - */ -#define CONFIG_MAG_LIS2MDL /* Lid sensor: LIS2DML */ +#define CONFIG_ACCEL_LNG2DM /* Base sensor: LNG2DM \ + * (uses LIS2DH driver) \ + */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Lid sensor: LSM6DS3 \ + * (uses LSM6DSM driver) \ + */ +#define CONFIG_MAG_LIS2MDL /* Lid sensor: LIS2DML */ #define CONFIG_MAG_CALIBRATE /* Enable sensor fifo, must also define the _SIZE and _THRES */ @@ -40,7 +40,7 @@ /* Depends on how fast the AP boots and typical ODRs. */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(BASE_ACCEL) | BIT(LID_MAG)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(BASE_ACCEL) | BIT(LID_MAG)) #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) @@ -99,8 +99,8 @@ #define CONFIG_ISH_PM_D3 #define CONFIG_ISH_PM_RESET_PREP -#define CONFIG_ISH_D0I2_MIN_USEC (15*MSEC) /* need final tune */ -#define CONFIG_ISH_D0I3_MIN_USEC (100*MSEC) /* need final tune */ +#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC) /* need final tune */ +#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC) /* need final tune */ #ifndef __ASSEMBLER__ @@ -112,13 +112,7 @@ * Note: Since we aren't using LPC memory map to transmit sensor data, the * order of this enum does not need to be accel, accel, gyro */ -enum sensor_id { - LID_ACCEL, - LID_GYRO, - BASE_ACCEL, - LID_MAG, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 0f9368b13ba2d06553bfaae9d9bbbc9464595401 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:17 -0600 Subject: board/gimble/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fb5fd292a9bef2bab7e500257ab92b91cdb419a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728416 Reviewed-by: Jeremy Bettis --- board/gimble/led.c | 54 +++++++++++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/board/gimble/led.c b/board/gimble/led.c index 3176e1a35d..f0476599ab 100644 --- a/board/gimble/led.c +++ b/board/gimble/led.c @@ -28,34 +28,34 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = { - {EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} - }, - [STATE_FACTORY_TEST] = { - {EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} - }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = { - {LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -108,7 +108,7 @@ __override void led_set_color_battery(enum ec_led_colors color) default: /* Unknown charging port */ break; } - } else { + } else { switch (color) { case EC_LED_COLOR_AMBER: led1_duty = BAT_LED_ON_LVL; -- cgit v1.2.1 From d1a2c8cbce4ecb3779d1f5bdb9171edd5ae50f8b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:11 -0600 Subject: include/i8042_protocol.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib22e53c9e8b6f28c377bc0c56f0972a303953b66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730308 Reviewed-by: Jeremy Bettis --- include/i8042_protocol.h | 132 +++++++++++++++++++++++------------------------ 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h index 7e554fc03e..f56da0956c 100644 --- a/include/i8042_protocol.h +++ b/include/i8042_protocol.h @@ -11,82 +11,82 @@ /* Some commands appear more than once. Why? */ /* port 0x60 */ -#define I8042_CMD_MOUSE_1_1 0xe6 -#define I8042_CMD_MOUSE_2_1 0xe7 -#define I8042_CMD_MOUSE_RES 0xe8 -#define I8042_CMD_OK_GETID 0xe8 -#define I8042_CMD_GET_MOUSE 0xe9 -#define I8042_CMD_EX_ENABLE 0xea -#define I8042_CMD_EX_SETLEDS 0xeb -#define I8042_CMD_SETLEDS 0xed -#define I8042_CMD_DIAG_ECHO 0xee -#define I8042_CMD_GSCANSET 0xf0 -#define I8042_CMD_SSCANSET 0xf0 -#define I8042_CMD_GETID 0xf2 -#define I8042_CMD_SETREP 0xf3 -#define I8042_CMD_ENABLE 0xf4 -#define I8042_CMD_RESET_DIS 0xf5 -#define I8042_CMD_RESET_DEF 0xf6 -#define I8042_CMD_ALL_TYPEM 0xf7 -#define I8042_CMD_SETALL_MB 0xf8 -#define I8042_CMD_SETALL_MBR 0xfa -#define I8042_CMD_SET_A_KEY_T 0xfb -#define I8042_CMD_SET_A_KEY_MR 0xfc -#define I8042_CMD_SET_A_KEY_M 0xfd -#define I8042_CMD_RESET 0xff -#define I8042_CMD_RESEND 0xfe +#define I8042_CMD_MOUSE_1_1 0xe6 +#define I8042_CMD_MOUSE_2_1 0xe7 +#define I8042_CMD_MOUSE_RES 0xe8 +#define I8042_CMD_OK_GETID 0xe8 +#define I8042_CMD_GET_MOUSE 0xe9 +#define I8042_CMD_EX_ENABLE 0xea +#define I8042_CMD_EX_SETLEDS 0xeb +#define I8042_CMD_SETLEDS 0xed +#define I8042_CMD_DIAG_ECHO 0xee +#define I8042_CMD_GSCANSET 0xf0 +#define I8042_CMD_SSCANSET 0xf0 +#define I8042_CMD_GETID 0xf2 +#define I8042_CMD_SETREP 0xf3 +#define I8042_CMD_ENABLE 0xf4 +#define I8042_CMD_RESET_DIS 0xf5 +#define I8042_CMD_RESET_DEF 0xf6 +#define I8042_CMD_ALL_TYPEM 0xf7 +#define I8042_CMD_SETALL_MB 0xf8 +#define I8042_CMD_SETALL_MBR 0xfa +#define I8042_CMD_SET_A_KEY_T 0xfb +#define I8042_CMD_SET_A_KEY_MR 0xfc +#define I8042_CMD_SET_A_KEY_M 0xfd +#define I8042_CMD_RESET 0xff +#define I8042_CMD_RESEND 0xfe /* port 0x64 */ -#define I8042_READ_CMD_BYTE 0x20 -#define I8042_READ_CTL_RAM 0x21 -#define I8042_READ_CTL_RAM_END 0x3f -#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */ -#define I8042_WRITE_CTL_RAM 0x61 +#define I8042_READ_CMD_BYTE 0x20 +#define I8042_READ_CTL_RAM 0x21 +#define I8042_READ_CTL_RAM_END 0x3f +#define I8042_WRITE_CMD_BYTE 0x60 /* expect a byte on port 0x60 */ +#define I8042_WRITE_CTL_RAM 0x61 #define I8042_WRITE_CTL_RAM_END 0x7f -#define I8042_ROUTE_AUX0 0x90 -#define I8042_ROUTE_AUX1 0x91 -#define I8042_ROUTE_AUX2 0x92 -#define I8042_ROUTE_AUX3 0x93 -#define I8042_ENA_PASSWORD 0xa6 -#define I8042_DIS_MOUSE 0xa7 -#define I8042_ENA_MOUSE 0xa8 -#define I8042_TEST_MOUSE 0xa9 -#define I8042_RESET_SELF_TEST 0xaa -#define I8042_TEST_KB_PORT 0xab -#define I8042_DIS_KB 0xad -#define I8042_ENA_KB 0xae -#define I8042_READ_OUTPUT_PORT 0xd0 +#define I8042_ROUTE_AUX0 0x90 +#define I8042_ROUTE_AUX1 0x91 +#define I8042_ROUTE_AUX2 0x92 +#define I8042_ROUTE_AUX3 0x93 +#define I8042_ENA_PASSWORD 0xa6 +#define I8042_DIS_MOUSE 0xa7 +#define I8042_ENA_MOUSE 0xa8 +#define I8042_TEST_MOUSE 0xa9 +#define I8042_RESET_SELF_TEST 0xaa +#define I8042_TEST_KB_PORT 0xab +#define I8042_DIS_KB 0xad +#define I8042_ENA_KB 0xae +#define I8042_READ_OUTPUT_PORT 0xd0 #define I8042_WRITE_OUTPUT_PORT 0xd1 -#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */ -#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */ -#define I8042_DISABLE_A20 0xdd -#define I8042_ENABLE_A20 0xdf -#define I8042_PULSE_START 0xf0 -#define I8042_SYSTEM_RESET 0xfe -#define I8042_PULSE_END 0xff +#define I8042_ECHO_MOUSE 0xd3 /* expect a byte on port 0x60 */ +#define I8042_SEND_TO_MOUSE 0xd4 /* expect a byte on port 0x60 */ +#define I8042_DISABLE_A20 0xdd +#define I8042_ENABLE_A20 0xdf +#define I8042_PULSE_START 0xf0 +#define I8042_SYSTEM_RESET 0xfe +#define I8042_PULSE_END 0xff /* port 0x60 return value */ -#define I8042_RET_EMUL0 0xe0 -#define I8042_RET_EMUL1 0xe1 -#define I8042_RET_ECHO 0xee -#define I8042_RET_RELEASE 0xf0 -#define I8042_RET_HANJA 0xf1 -#define I8042_RET_HANGEUL 0xf2 -#define I8042_RET_ACK 0xfa -#define I8042_RET_TEST_FAIL 0xfc +#define I8042_RET_EMUL0 0xe0 +#define I8042_RET_EMUL1 0xe1 +#define I8042_RET_ECHO 0xee +#define I8042_RET_RELEASE 0xf0 +#define I8042_RET_HANJA 0xf1 +#define I8042_RET_HANGEUL 0xf2 +#define I8042_RET_ACK 0xfa +#define I8042_RET_TEST_FAIL 0xfc #define I8042_RET_INTERNAL_FAIL 0xfd -#define I8042_RET_NAK 0xfe -#define I8042_RET_ERR 0xff +#define I8042_RET_NAK 0xfe +#define I8042_RET_ERR 0xff /* port 64 - command byte bits */ -#define I8042_XLATE BIT(6) -#define I8042_AUX_DIS BIT(5) -#define I8042_KBD_DIS BIT(4) -#define I8042_SYS_FLAG BIT(2) -#define I8042_ENIRQ12 BIT(1) -#define I8042_ENIRQ1 BIT(0) +#define I8042_XLATE BIT(6) +#define I8042_AUX_DIS BIT(5) +#define I8042_KBD_DIS BIT(4) +#define I8042_SYS_FLAG BIT(2) +#define I8042_ENIRQ12 BIT(1) +#define I8042_ENIRQ1 BIT(0) /* Status Flags */ -#define I8042_AUX_DATA BIT(5) +#define I8042_AUX_DATA BIT(5) #endif /* __CROS_EC_I8042_PROTOCOL_H */ -- cgit v1.2.1 From 4fbdd5fcecb4e10886ffd3a6967f2be5e8c67794 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:18 -0600 Subject: chip/mec1322/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia75f08d5d67f7949c761269836f36eef23147220 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729322 Reviewed-by: Jeremy Bettis --- chip/mec1322/registers.h | 637 +++++++++++++++++++++++------------------------ 1 file changed, 310 insertions(+), 327 deletions(-) diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 7bbd9fb068..055eb74fff 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -11,105 +11,102 @@ #include "common.h" /* Helper function for RAM address aliasing */ -#define MEC1322_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) +#define MEC1322_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x)) /* EC Chip Configuration */ -#define MEC1322_CHIP_BASE 0x400fff00 -#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20) -#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21) - +#define MEC1322_CHIP_BASE 0x400fff00 +#define MEC1322_CHIP_DEV_ID REG8(MEC1322_CHIP_BASE + 0x20) +#define MEC1322_CHIP_DEV_REV REG8(MEC1322_CHIP_BASE + 0x21) /* Power/Clocks/Resets */ -#define MEC1322_PCR_BASE 0x40080100 -#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0) +#define MEC1322_PCR_BASE 0x40080100 +#define MEC1322_PCR_CHIP_SLP_EN REG32(MEC1322_PCR_BASE + 0x0) #define MEC1322_PCR_CHIP_CLK_REQ REG32(MEC1322_PCR_BASE + 0x4) -#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8) +#define MEC1322_PCR_EC_SLP_EN REG32(MEC1322_PCR_BASE + 0x8) /* Command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 -#define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) +#define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 +#define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) +#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) +#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) +#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) +#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) /* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) -#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) -#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10) +#define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) +#define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) +#define MEC1322_PCR_HOST_SLP_EN REG32(MEC1322_PCR_BASE + 0x10) /* Command all blocks to sleep */ -#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003 +#define MEC1322_PCR_HOST_SLP_EN_SLEEP 0x5f003 /* Allow all blocks to request clocks */ -#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003) +#define MEC1322_PCR_HOST_SLP_EN_WAKE (~0x5f003) #define MEC1322_PCR_HOST_CLK_REQ REG32(MEC1322_PCR_BASE + 0x14) -#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18) +#define MEC1322_PCR_SYS_SLP_CTL REG32(MEC1322_PCR_BASE + 0x18) #define MEC1322_PCR_PROC_CLK_CTL REG32(MEC1322_PCR_BASE + 0x20) -#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24) +#define MEC1322_PCR_EC_SLP_EN2 REG32(MEC1322_PCR_BASE + 0x24) /* Mask to command all blocks to sleep */ -#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8 +#define MEC1322_PCR_EC_SLP_EN2_SLEEP 0x1ffffff8 /* Allow all blocks to request clocks */ -#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8) -#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28) +#define MEC1322_PCR_EC_SLP_EN2_WAKE (~0x03fffff8) +#define MEC1322_PCR_EC_CLK_REQ2 REG32(MEC1322_PCR_BASE + 0x28) #define MEC1322_PCR_SLOW_CLK_CTL REG32(MEC1322_PCR_BASE + 0x2c) -#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30) +#define MEC1322_PCR_CHIP_OSC_ID REG32(MEC1322_PCR_BASE + 0x30) #define MEC1322_PCR_CHIP_PWR_RST REG32(MEC1322_PCR_BASE + 0x34) -#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38) -#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c) -#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40) -#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) -#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) +#define MEC1322_PCR_CHIP_RST_EN REG32(MEC1322_PCR_BASE + 0x38) +#define MEC1322_PCR_HOST_RST_EN REG32(MEC1322_PCR_BASE + 0x3c) +#define MEC1322_PCR_EC_RST_EN REG32(MEC1322_PCR_BASE + 0x40) +#define MEC1322_PCR_EC_RST_EN2 REG32(MEC1322_PCR_BASE + 0x44) +#define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) /* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ #define MEC1322_PWR_RST_STS_VCC1 BIT(6) #define MEC1322_PWR_RST_STS_VBAT BIT(5) /* EC Subsystem */ -#define MEC1322_EC_BASE 0x4000fc00 -#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18) -#define MEC1322_EC_TRACE_EN REG32(MEC1322_EC_BASE + 0x1c) -#define MEC1322_EC_JTAG_EN REG32(MEC1322_EC_BASE + 0x20) -#define MEC1322_EC_WDT_CNT REG32(MEC1322_EC_BASE + 0x28) +#define MEC1322_EC_BASE 0x4000fc00 +#define MEC1322_EC_INT_CTRL REG32(MEC1322_EC_BASE + 0x18) +#define MEC1322_EC_TRACE_EN REG32(MEC1322_EC_BASE + 0x1c) +#define MEC1322_EC_JTAG_EN REG32(MEC1322_EC_BASE + 0x20) +#define MEC1322_EC_WDT_CNT REG32(MEC1322_EC_BASE + 0x28) #define MEC1322_EC_ADC_VREF_PD REG32(MEC1322_EC_BASE + 0x38) /* Interrupt aggregator */ -#define MEC1322_INT_BASE 0x4000c000 -#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x) - 8) * 0x14) -#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0) -#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4) -#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8) +#define MEC1322_INT_BASE 0x4000c000 +#define MEC1322_INTx_BASE(x) (MEC1322_INT_BASE + ((x)-8) * 0x14) +#define MEC1322_INT_SOURCE(x) REG32(MEC1322_INTx_BASE(x) + 0x0) +#define MEC1322_INT_ENABLE(x) REG32(MEC1322_INTx_BASE(x) + 0x4) +#define MEC1322_INT_RESULT(x) REG32(MEC1322_INTx_BASE(x) + 0x8) #define MEC1322_INT_DISABLE(x) REG32(MEC1322_INTx_BASE(x) + 0xc) -#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200) -#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204) -#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208) - +#define MEC1322_INT_BLK_EN REG32(MEC1322_INT_BASE + 0x200) +#define MEC1322_INT_BLK_DIS REG32(MEC1322_INT_BASE + 0x204) +#define MEC1322_INT_BLK_IRQ REG32(MEC1322_INT_BASE + 0x208) /* UART */ -#define MEC1322_UART_CONFIG_BASE 0x400f1f00 +#define MEC1322_UART_CONFIG_BASE 0x400f1f00 #define MEC1322_UART_RUNTIME_BASE 0x400f1c00 -#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30) -#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0) +#define MEC1322_UART_ACT REG8(MEC1322_UART_CONFIG_BASE + 0x30) +#define MEC1322_UART_CFG REG8(MEC1322_UART_CONFIG_BASE + 0xf0) /* DLAB=0 */ -#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1) +#define MEC1322_UART_RB /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) +#define MEC1322_UART_TB /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x0) +#define MEC1322_UART_IER REG8(MEC1322_UART_RUNTIME_BASE + 0x1) /* DLAB=1 */ -#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0) -#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1) +#define MEC1322_UART_PBRG0 REG8(MEC1322_UART_RUNTIME_BASE + 0x0) +#define MEC1322_UART_PBRG1 REG8(MEC1322_UART_RUNTIME_BASE + 0x1) #define MEC1322_UART_FCR /*W*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) #define MEC1322_UART_IIR /*R*/ REG8(MEC1322_UART_RUNTIME_BASE + 0x2) -#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3) -#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4) -#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5) -#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6) -#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) +#define MEC1322_UART_LCR REG8(MEC1322_UART_RUNTIME_BASE + 0x3) +#define MEC1322_UART_MCR REG8(MEC1322_UART_RUNTIME_BASE + 0x4) +#define MEC1322_UART_LSR REG8(MEC1322_UART_RUNTIME_BASE + 0x5) +#define MEC1322_UART_MSR REG8(MEC1322_UART_RUNTIME_BASE + 0x6) +#define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) /* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY BIT(5) +#define MEC1322_LSR_TX_EMPTY BIT(5) /* GPIO */ -#define MEC1322_GPIO_BASE 0x40081000 +#define MEC1322_GPIO_BASE 0x40081000 static inline uintptr_t gpio_port_base(int port_id) { @@ -120,243 +117,230 @@ static inline uintptr_t gpio_port_base(int port_id) #define UNIMPLEMENTED_GPIO_BANK 0 - /* Timer */ -#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x) * 0x20) -#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x) * 0x20) - -#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0) -#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4) -#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8) -#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc) -#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10) -#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0) -#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4) -#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8) -#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc) -#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10) - +#define MEC1322_TMR16_BASE(x) (0x40000c00 + (x)*0x20) +#define MEC1322_TMR32_BASE(x) (0x40000c80 + (x)*0x20) + +#define MEC1322_TMR16_CNT(x) REG32(MEC1322_TMR16_BASE(x) + 0x0) +#define MEC1322_TMR16_PRE(x) REG32(MEC1322_TMR16_BASE(x) + 0x4) +#define MEC1322_TMR16_STS(x) REG32(MEC1322_TMR16_BASE(x) + 0x8) +#define MEC1322_TMR16_IEN(x) REG32(MEC1322_TMR16_BASE(x) + 0xc) +#define MEC1322_TMR16_CTL(x) REG32(MEC1322_TMR16_BASE(x) + 0x10) +#define MEC1322_TMR32_CNT(x) REG32(MEC1322_TMR32_BASE(x) + 0x0) +#define MEC1322_TMR32_PRE(x) REG32(MEC1322_TMR32_BASE(x) + 0x4) +#define MEC1322_TMR32_STS(x) REG32(MEC1322_TMR32_BASE(x) + 0x8) +#define MEC1322_TMR32_IEN(x) REG32(MEC1322_TMR32_BASE(x) + 0xc) +#define MEC1322_TMR32_CTL(x) REG32(MEC1322_TMR32_BASE(x) + 0x10) /* Watchdog */ -#define MEC1322_WDG_BASE 0x40000400 -#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0) -#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4) -#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8) -#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc) - +#define MEC1322_WDG_BASE 0x40000400 +#define MEC1322_WDG_LOAD REG16(MEC1322_WDG_BASE + 0x0) +#define MEC1322_WDG_CTL REG8(MEC1322_WDG_BASE + 0x4) +#define MEC1322_WDG_KICK REG8(MEC1322_WDG_BASE + 0x8) +#define MEC1322_WDG_CNT REG16(MEC1322_WDG_BASE + 0xc) /* VBAT */ -#define MEC1322_VBAT_BASE 0x4000a400 -#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0) -#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8) -#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) +#define MEC1322_VBAT_BASE 0x4000a400 +#define MEC1322_VBAT_STS REG32(MEC1322_VBAT_BASE + 0x0) +#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8) +#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) /* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT BIT(5) +#define MEC1322_VBAT_STS_WDT BIT(5) /* Miscellaneous firmware control fields * scratch pad index cannot be more than 16 as * mec has 64 bytes = 16 indexes of scratchpad RAM */ -#define MEC1322_IMAGETYPE_IDX 15 +#define MEC1322_IMAGETYPE_IDX 15 /* LPC */ -#define MEC1322_LPC_CFG_BASE 0x400f3300 -#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30) -#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x)) -#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60) -#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64) -#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68) -#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78) +#define MEC1322_LPC_CFG_BASE 0x400f3300 +#define MEC1322_LPC_ACT REG8(MEC1322_LPC_CFG_BASE + 0x30) +#define MEC1322_LPC_SIRQ(x) REG8(MEC1322_LPC_CFG_BASE + 0x40 + (x)) +#define MEC1322_LPC_CFG_BAR REG32(MEC1322_LPC_CFG_BASE + 0x60) +#define MEC1322_LPC_EMI_BAR REG32(MEC1322_LPC_CFG_BASE + 0x64) +#define MEC1322_LPC_UART_BAR REG32(MEC1322_LPC_CFG_BASE + 0x68) +#define MEC1322_LPC_8042_BAR REG32(MEC1322_LPC_CFG_BASE + 0x78) #define MEC1322_LPC_ACPI_EC0_BAR REG32(MEC1322_LPC_CFG_BASE + 0x88) #define MEC1322_LPC_ACPI_EC1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x8c) #define MEC1322_LPC_ACPI_PM1_BAR REG32(MEC1322_LPC_CFG_BASE + 0x90) -#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94) -#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98) -#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c) -#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0) -#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4) - -#define MEC1322_LPC_RT_BASE 0x400f3100 -#define MEC1322_LPC_BUS_MONITOR REG32(MEC1322_LPC_RT_BASE + 0x4) -#define MEC1322_LPC_CLK_CTRL REG32(MEC1322_LPC_RT_BASE + 0x10) +#define MEC1322_LPC_PORT92_BAR REG32(MEC1322_LPC_CFG_BASE + 0x94) +#define MEC1322_LPC_MAILBOX_BAR REG32(MEC1322_LPC_CFG_BASE + 0x98) +#define MEC1322_LPC_RTC_BAR REG32(MEC1322_LPC_CFG_BASE + 0x9c) +#define MEC1322_LPC_MEM_BAR REG32(MEC1322_LPC_CFG_BASE + 0xa0) +#define MEC1322_LPC_MEM_BAR_CFG REG32(MEC1322_LPC_CFG_BASE + 0xa4) + +#define MEC1322_LPC_RT_BASE 0x400f3100 +#define MEC1322_LPC_BUS_MONITOR REG32(MEC1322_LPC_RT_BASE + 0x4) +#define MEC1322_LPC_CLK_CTRL REG32(MEC1322_LPC_RT_BASE + 0x10) #define MEC1322_LPC_MEM_HOST_CFG REG32(MEC1322_LPC_RT_BASE + 0xfc) - /* EMI */ -#define MEC1322_EMI_BASE 0x400f0100 -#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0) -#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1) -#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4) -#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8) -#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa) -#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc) -#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10) -#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12) -#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14) -#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16) - -#define MEC1322_EMI_RT_BASE 0x400f0000 -#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8) -#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9) -#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa) -#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb) - +#define MEC1322_EMI_BASE 0x400f0100 +#define MEC1322_EMI_H2E_MBX REG8(MEC1322_EMI_BASE + 0x0) +#define MEC1322_EMI_E2H_MBX REG8(MEC1322_EMI_BASE + 0x1) +#define MEC1322_EMI_MBA0 REG32(MEC1322_EMI_BASE + 0x4) +#define MEC1322_EMI_MRL0 REG16(MEC1322_EMI_BASE + 0x8) +#define MEC1322_EMI_MWL0 REG16(MEC1322_EMI_BASE + 0xa) +#define MEC1322_EMI_MBA1 REG32(MEC1322_EMI_BASE + 0xc) +#define MEC1322_EMI_MRL1 REG16(MEC1322_EMI_BASE + 0x10) +#define MEC1322_EMI_MWL1 REG16(MEC1322_EMI_BASE + 0x12) +#define MEC1322_EMI_ISR REG16(MEC1322_EMI_BASE + 0x14) +#define MEC1322_EMI_HCE REG16(MEC1322_EMI_BASE + 0x16) + +#define MEC1322_EMI_RT_BASE 0x400f0000 +#define MEC1322_EMI_ISR_B0 REG8(MEC1322_EMI_RT_BASE + 0x8) +#define MEC1322_EMI_ISR_B1 REG8(MEC1322_EMI_RT_BASE + 0x9) +#define MEC1322_EMI_IMR_B0 REG8(MEC1322_EMI_RT_BASE + 0xa) +#define MEC1322_EMI_IMR_B1 REG8(MEC1322_EMI_RT_BASE + 0xb) /* Mailbox */ -#define MEC1322_MBX_RT_BASE 0x400f2400 -#define MEC1322_MBX_INDEX REG8(MEC1322_MBX_RT_BASE + 0x0) -#define MEC1322_MBX_DATA REG8(MEC1322_MBX_RT_BASE + 0x1) - -#define MEC1322_MBX_BASE 0x400f2500 -#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0) -#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4) -#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8) -#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) -#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) +#define MEC1322_MBX_RT_BASE 0x400f2400 +#define MEC1322_MBX_INDEX REG8(MEC1322_MBX_RT_BASE + 0x0) +#define MEC1322_MBX_DATA REG8(MEC1322_MBX_RT_BASE + 0x1) +#define MEC1322_MBX_BASE 0x400f2500 +#define MEC1322_MBX_H2E_MBX REG8(MEC1322_MBX_BASE + 0x0) +#define MEC1322_MBX_E2H_MBX REG8(MEC1322_MBX_BASE + 0x4) +#define MEC1322_MBX_ISR REG8(MEC1322_MBX_BASE + 0x8) +#define MEC1322_MBX_IMR REG8(MEC1322_MBX_BASE + 0xc) +#define MEC1322_MBX_REG(x) REG8(MEC1322_MBX_BASE + 0x10 + (x)) /* PWM */ -#define MEC1322_PWM_BASE(x) (0x40005800 + (x) * 0x10) -#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00) -#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04) -#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08) - +#define MEC1322_PWM_BASE(x) (0x40005800 + (x)*0x10) +#define MEC1322_PWM_ON(x) REG32(MEC1322_PWM_BASE(x) + 0x00) +#define MEC1322_PWM_OFF(x) REG32(MEC1322_PWM_BASE(x) + 0x04) +#define MEC1322_PWM_CFG(x) REG32(MEC1322_PWM_BASE(x) + 0x08) /* ACPI */ -#define MEC1322_ACPI_EC_BASE(x) (0x400f0c00 + (x) * 0x400) +#define MEC1322_ACPI_EC_BASE(x) (0x400f0c00 + (x)*0x400) #define MEC1322_ACPI_EC_EC2OS(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x100 + (y)) -#define MEC1322_ACPI_EC_STATUS(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x104) +#define MEC1322_ACPI_EC_STATUS(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x104) #define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105) #define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y)) -#define MEC1322_ACPI_PM_RT_BASE 0x400f1400 -#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0) -#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1) -#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2) -#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3) -#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4) -#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5) -#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6) -#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7) -#define MEC1322_ACPI_PM_EC_BASE 0x400f1500 -#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10) - +#define MEC1322_ACPI_PM_RT_BASE 0x400f1400 +#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0) +#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1) +#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2) +#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3) +#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4) +#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5) +#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6) +#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7) +#define MEC1322_ACPI_PM_EC_BASE 0x400f1500 +#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10) /* 8042 */ -#define MEC1322_8042_BASE 0x400f0400 -#define MEC1322_8042_OBF_CLR REG8(MEC1322_8042_BASE + 0x0) -#define MEC1322_8042_H2E REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_E2H REG8(MEC1322_8042_BASE + 0x100) -#define MEC1322_8042_STS REG8(MEC1322_8042_BASE + 0x104) -#define MEC1322_8042_KB_CTRL REG8(MEC1322_8042_BASE + 0x108) -#define MEC1322_8042_PCOBF REG8(MEC1322_8042_BASE + 0x114) -#define MEC1322_8042_ACT REG8(MEC1322_8042_BASE + 0x330) - +#define MEC1322_8042_BASE 0x400f0400 +#define MEC1322_8042_OBF_CLR REG8(MEC1322_8042_BASE + 0x0) +#define MEC1322_8042_H2E REG8(MEC1322_8042_BASE + 0x100) +#define MEC1322_8042_E2H REG8(MEC1322_8042_BASE + 0x100) +#define MEC1322_8042_STS REG8(MEC1322_8042_BASE + 0x104) +#define MEC1322_8042_KB_CTRL REG8(MEC1322_8042_BASE + 0x108) +#define MEC1322_8042_PCOBF REG8(MEC1322_8042_BASE + 0x114) +#define MEC1322_8042_ACT REG8(MEC1322_8042_BASE + 0x330) /* FAN */ -#define MEC1322_FAN_BASE 0x4000a000 -#define MEC1322_FAN_SETTING REG8(MEC1322_FAN_BASE + 0x0) +#define MEC1322_FAN_BASE 0x4000a000 +#define MEC1322_FAN_SETTING REG8(MEC1322_FAN_BASE + 0x0) #define MEC1322_FAN_PWM_DIVIDE REG8(MEC1322_FAN_BASE + 0x1) -#define MEC1322_FAN_CFG1 REG8(MEC1322_FAN_BASE + 0x2) -#define MEC1322_FAN_CFG2 REG8(MEC1322_FAN_BASE + 0x3) -#define MEC1322_FAN_GAIN REG8(MEC1322_FAN_BASE + 0x5) -#define MEC1322_FAN_SPIN_UP REG8(MEC1322_FAN_BASE + 0x6) -#define MEC1322_FAN_STEP REG8(MEC1322_FAN_BASE + 0x7) -#define MEC1322_FAN_MIN_DRV REG8(MEC1322_FAN_BASE + 0x8) -#define MEC1322_FAN_VALID_CNT REG8(MEC1322_FAN_BASE + 0x9) -#define MEC1322_FAN_DRV_FAIL REG16(MEC1322_FAN_BASE + 0xa) -#define MEC1322_FAN_TARGET REG16(MEC1322_FAN_BASE + 0xc) -#define MEC1322_FAN_READING REG16(MEC1322_FAN_BASE + 0xe) -#define MEC1322_FAN_BASE_FREQ REG8(MEC1322_FAN_BASE + 0x10) -#define MEC1322_FAN_STATUS REG8(MEC1322_FAN_BASE + 0x11) - +#define MEC1322_FAN_CFG1 REG8(MEC1322_FAN_BASE + 0x2) +#define MEC1322_FAN_CFG2 REG8(MEC1322_FAN_BASE + 0x3) +#define MEC1322_FAN_GAIN REG8(MEC1322_FAN_BASE + 0x5) +#define MEC1322_FAN_SPIN_UP REG8(MEC1322_FAN_BASE + 0x6) +#define MEC1322_FAN_STEP REG8(MEC1322_FAN_BASE + 0x7) +#define MEC1322_FAN_MIN_DRV REG8(MEC1322_FAN_BASE + 0x8) +#define MEC1322_FAN_VALID_CNT REG8(MEC1322_FAN_BASE + 0x9) +#define MEC1322_FAN_DRV_FAIL REG16(MEC1322_FAN_BASE + 0xa) +#define MEC1322_FAN_TARGET REG16(MEC1322_FAN_BASE + 0xc) +#define MEC1322_FAN_READING REG16(MEC1322_FAN_BASE + 0xe) +#define MEC1322_FAN_BASE_FREQ REG8(MEC1322_FAN_BASE + 0x10) +#define MEC1322_FAN_STATUS REG8(MEC1322_FAN_BASE + 0x11) /* I2C */ -#define MEC1322_I2C0_BASE 0x40001800 -#define MEC1322_I2C1_BASE 0x4000ac00 -#define MEC1322_I2C2_BASE 0x4000b000 -#define MEC1322_I2C3_BASE 0x4000b400 -#define MEC1322_I2C_BASESEP 0x00000400 +#define MEC1322_I2C0_BASE 0x40001800 +#define MEC1322_I2C1_BASE 0x4000ac00 +#define MEC1322_I2C2_BASE 0x4000b000 +#define MEC1322_I2C3_BASE 0x4000b400 +#define MEC1322_I2C_BASESEP 0x00000400 #define MEC1322_I2C_ADDR(controller, offset) \ - (offset + (controller == 0 ? MEC1322_I2C0_BASE : \ - MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1))) + (offset + \ + (controller == 0 ? \ + MEC1322_I2C0_BASE : \ + MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1))) /* * MEC1322 has five ports distributed among four controllers. Locking must * occur by-controller (not by-port). */ enum mec1322_i2c_port { - MEC1322_I2C0_0 = 0, /* Controller 0, port 0 */ - MEC1322_I2C0_1 = 1, /* Controller 0, port 1 */ - MEC1322_I2C1 = 2, /* Controller 1 */ - MEC1322_I2C2 = 3, /* Controller 2 */ - MEC1322_I2C3 = 4, /* Controller 3 */ + MEC1322_I2C0_0 = 0, /* Controller 0, port 0 */ + MEC1322_I2C0_1 = 1, /* Controller 0, port 1 */ + MEC1322_I2C1 = 2, /* Controller 1 */ + MEC1322_I2C2 = 3, /* Controller 2 */ + MEC1322_I2C3 = 4, /* Controller 3 */ MEC1322_I2C_PORT_COUNT, }; -#define MEC1322_I2C_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_STATUS(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) -#define MEC1322_I2C_OWN_ADDR(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x4)) -#define MEC1322_I2C_DATA(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x8)) -#define MEC1322_I2C_MASTER_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0xc)) -#define MEC1322_I2C_SLAVE_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x10)) -#define MEC1322_I2C_PEC(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x14)) -#define MEC1322_I2C_DATA_TIM_2(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x18)) -#define MEC1322_I2C_COMPLETE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x20)) -#define MEC1322_I2C_IDLE_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x24)) -#define MEC1322_I2C_CONFIG(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x28)) -#define MEC1322_I2C_BUS_CLK(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x2c)) -#define MEC1322_I2C_BLK_ID(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x30)) -#define MEC1322_I2C_REV(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x34)) -#define MEC1322_I2C_BB_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x38)) -#define MEC1322_I2C_DATA_TIM(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x40)) -#define MEC1322_I2C_TOUT_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x44)) -#define MEC1322_I2C_SLAVE_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x48)) -#define MEC1322_I2C_SLAVE_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x4c)) +#define MEC1322_I2C_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) +#define MEC1322_I2C_STATUS(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x0)) +#define MEC1322_I2C_OWN_ADDR(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x4)) +#define MEC1322_I2C_DATA(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x8)) +#define MEC1322_I2C_MASTER_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0xc)) +#define MEC1322_I2C_SLAVE_CMD(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x10)) +#define MEC1322_I2C_PEC(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x14)) +#define MEC1322_I2C_DATA_TIM_2(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x18)) +#define MEC1322_I2C_COMPLETE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x20)) +#define MEC1322_I2C_IDLE_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x24)) +#define MEC1322_I2C_CONFIG(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x28)) +#define MEC1322_I2C_BUS_CLK(ctrl) REG16(MEC1322_I2C_ADDR(ctrl, 0x2c)) +#define MEC1322_I2C_BLK_ID(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x30)) +#define MEC1322_I2C_REV(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x34)) +#define MEC1322_I2C_BB_CTRL(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x38)) +#define MEC1322_I2C_DATA_TIM(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x40)) +#define MEC1322_I2C_TOUT_SCALE(ctrl) REG32(MEC1322_I2C_ADDR(ctrl, 0x44)) +#define MEC1322_I2C_SLAVE_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x48)) +#define MEC1322_I2C_SLAVE_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x4c)) #define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50)) #define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54)) - /* Keyboard scan matrix */ -#define MEC1322_KS_BASE 0x40009c00 -#define MEC1322_KS_KSO_SEL REG32(MEC1322_KS_BASE + 0x4) -#define MEC1322_KS_KSI_INPUT REG32(MEC1322_KS_BASE + 0x8) -#define MEC1322_KS_KSI_STATUS REG32(MEC1322_KS_BASE + 0xc) -#define MEC1322_KS_KSI_INT_EN REG32(MEC1322_KS_BASE + 0x10) -#define MEC1322_KS_EXT_CTRL REG32(MEC1322_KS_BASE + 0x14) - +#define MEC1322_KS_BASE 0x40009c00 +#define MEC1322_KS_KSO_SEL REG32(MEC1322_KS_BASE + 0x4) +#define MEC1322_KS_KSI_INPUT REG32(MEC1322_KS_BASE + 0x8) +#define MEC1322_KS_KSI_STATUS REG32(MEC1322_KS_BASE + 0xc) +#define MEC1322_KS_KSI_INT_EN REG32(MEC1322_KS_BASE + 0x10) +#define MEC1322_KS_EXT_CTRL REG32(MEC1322_KS_BASE + 0x14) /* ADC */ -#define MEC1322_ADC_BASE 0x40007c00 -#define MEC1322_ADC_CTRL REG32(MEC1322_ADC_BASE + 0x0) -#define MEC1322_ADC_DELAY REG32(MEC1322_ADC_BASE + 0x4) -#define MEC1322_ADC_STS REG32(MEC1322_ADC_BASE + 0x8) -#define MEC1322_ADC_SINGLE REG32(MEC1322_ADC_BASE + 0xc) -#define MEC1322_ADC_REPEAT REG32(MEC1322_ADC_BASE + 0x10) -#define MEC1322_ADC_READ(x) REG32(MEC1322_ADC_BASE + 0x14 + (x) * 0x4) - +#define MEC1322_ADC_BASE 0x40007c00 +#define MEC1322_ADC_CTRL REG32(MEC1322_ADC_BASE + 0x0) +#define MEC1322_ADC_DELAY REG32(MEC1322_ADC_BASE + 0x4) +#define MEC1322_ADC_STS REG32(MEC1322_ADC_BASE + 0x8) +#define MEC1322_ADC_SINGLE REG32(MEC1322_ADC_BASE + 0xc) +#define MEC1322_ADC_REPEAT REG32(MEC1322_ADC_BASE + 0x10) +#define MEC1322_ADC_READ(x) REG32(MEC1322_ADC_BASE + 0x14 + (x)*0x4) /* Hibernation timer */ -#define MEC1322_HTIMER_BASE 0x40009800 +#define MEC1322_HTIMER_BASE 0x40009800 #define MEC1322_HTIMER_PRELOAD REG16(MEC1322_HTIMER_BASE + 0x0) #define MEC1322_HTIMER_CONTROL REG16(MEC1322_HTIMER_BASE + 0x4) -#define MEC1322_HTIMER_COUNT REG16(MEC1322_HTIMER_BASE + 0x8) - +#define MEC1322_HTIMER_COUNT REG16(MEC1322_HTIMER_BASE + 0x8) /* SPI */ #define MEC1322_SPI_BASE(port) (0x40009400 + 0x80 * (port)) -#define MEC1322_SPI_AR(port) REG8(MEC1322_SPI_BASE(port) + 0x00) -#define MEC1322_SPI_CR(port) REG8(MEC1322_SPI_BASE(port) + 0x04) -#define MEC1322_SPI_SR(port) REG8(MEC1322_SPI_BASE(port) + 0x08) -#define MEC1322_SPI_TD(port) REG8(MEC1322_SPI_BASE(port) + 0x0c) -#define MEC1322_SPI_RD(port) REG8(MEC1322_SPI_BASE(port) + 0x10) -#define MEC1322_SPI_CC(port) REG8(MEC1322_SPI_BASE(port) + 0x14) -#define MEC1322_SPI_CG(port) REG8(MEC1322_SPI_BASE(port) + 0x18) - +#define MEC1322_SPI_AR(port) REG8(MEC1322_SPI_BASE(port) + 0x00) +#define MEC1322_SPI_CR(port) REG8(MEC1322_SPI_BASE(port) + 0x04) +#define MEC1322_SPI_SR(port) REG8(MEC1322_SPI_BASE(port) + 0x08) +#define MEC1322_SPI_TD(port) REG8(MEC1322_SPI_BASE(port) + 0x0c) +#define MEC1322_SPI_RD(port) REG8(MEC1322_SPI_BASE(port) + 0x10) +#define MEC1322_SPI_CC(port) REG8(MEC1322_SPI_BASE(port) + 0x14) +#define MEC1322_SPI_CG(port) REG8(MEC1322_SPI_BASE(port) + 0x18) /* DMA */ -#define MEC1322_DMA_BASE 0x40002400 +#define MEC1322_DMA_BASE 0x40002400 /* * Available DMA channels. @@ -367,31 +351,31 @@ enum mec1322_i2c_port { */ enum dma_channel { /* Channel numbers */ - MEC1322_DMAC_I2C0_SLAVE = 0, + MEC1322_DMAC_I2C0_SLAVE = 0, MEC1322_DMAC_I2C0_MASTER = 1, - MEC1322_DMAC_I2C1_SLAVE = 2, + MEC1322_DMAC_I2C1_SLAVE = 2, MEC1322_DMAC_I2C1_MASTER = 3, - MEC1322_DMAC_I2C2_SLAVE = 4, + MEC1322_DMAC_I2C2_SLAVE = 4, MEC1322_DMAC_I2C2_MASTER = 5, - MEC1322_DMAC_I2C3_SLAVE = 6, + MEC1322_DMAC_I2C3_SLAVE = 6, MEC1322_DMAC_I2C3_MASTER = 7, - MEC1322_DMAC_SPI0_TX = 8, - MEC1322_DMAC_SPI0_RX = 9, - MEC1322_DMAC_SPI1_TX = 10, - MEC1322_DMAC_SPI1_RX = 11, + MEC1322_DMAC_SPI0_TX = 8, + MEC1322_DMAC_SPI0_RX = 9, + MEC1322_DMAC_SPI1_TX = 10, + MEC1322_DMAC_SPI1_RX = 11, /* Channel count */ - MEC1322_DMAC_COUNT = 12, + MEC1322_DMAC_COUNT = 12, }; /* Registers for a single channel of the DMA controller */ struct mec1322_dma_chan { - uint32_t act; /* Activate */ - uint32_t mem_start; /* Memory start address */ - uint32_t mem_end; /* Memory end address */ - uint32_t dev; /* Device address */ - uint32_t ctrl; /* Control */ - uint32_t int_status; /* Interrupt status */ + uint32_t act; /* Activate */ + uint32_t mem_start; /* Memory start address */ + uint32_t mem_end; /* Memory end address */ + uint32_t dev; /* Device address */ + uint32_t ctrl; /* Control */ + uint32_t int_status; /* Interrupt status */ uint32_t int_enabled; /* Interrupt enabled */ uint32_t pad; }; @@ -416,87 +400,86 @@ typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; #define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) /* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN BIT(0) -#define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV BIT(17) -#define MEC1322_DMA_INC_MEM BIT(16) -#define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV BIT(8) -#define MEC1322_DMA_DONE BIT(2) -#define MEC1322_DMA_RUN BIT(0) - +#define MEC1322_DMA_ACT_EN BIT(0) +#define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) +#define MEC1322_DMA_INC_DEV BIT(17) +#define MEC1322_DMA_INC_MEM BIT(16) +#define MEC1322_DMA_DEV(x) ((x) << 9) +#define MEC1322_DMA_TO_DEV BIT(8) +#define MEC1322_DMA_DONE BIT(2) +#define MEC1322_DMA_RUN BIT(0) /* IRQ Numbers */ -#define MEC1322_IRQ_I2C_0 0 -#define MEC1322_IRQ_I2C_1 1 -#define MEC1322_IRQ_I2C_2 2 -#define MEC1322_IRQ_I2C_3 3 -#define MEC1322_IRQ_DMA_0 4 -#define MEC1322_IRQ_DMA_1 5 -#define MEC1322_IRQ_DMA_2 6 -#define MEC1322_IRQ_DMA_3 7 -#define MEC1322_IRQ_DMA_4 8 -#define MEC1322_IRQ_DMA_5 9 -#define MEC1322_IRQ_DMA_6 10 -#define MEC1322_IRQ_DMA_7 11 -#define MEC1322_IRQ_LPC 12 -#define MEC1322_IRQ_UART 13 -#define MEC1322_IRQ_EMI 14 -#define MEC1322_IRQ_ACPIEC0_IBF 15 -#define MEC1322_IRQ_ACPIEC0_OBF 16 -#define MEC1322_IRQ_ACPIEC1_IBF 17 -#define MEC1322_IRQ_ACPIEC1_OBF 18 -#define MEC1322_IRQ_ACPIPM1_CTL 19 -#define MEC1322_IRQ_ACPIPM1_EN 20 -#define MEC1322_IRQ_ACPIPM1_STS 21 -#define MEC1322_IRQ_8042EM_OBF 22 -#define MEC1322_IRQ_8042EM_IBF 23 -#define MEC1322_IRQ_MAILBOX 24 -#define MEC1322_IRQ_PECI_HOST 25 -#define MEC1322_IRQ_TACH_0 26 -#define MEC1322_IRQ_TACH_1 27 -#define MEC1322_IRQ_ADC_SNGL 28 -#define MEC1322_IRQ_ADC_RPT 29 -#define MEC1322_IRQ_PS2_0 32 -#define MEC1322_IRQ_PS2_1 33 -#define MEC1322_IRQ_PS2_2 34 -#define MEC1322_IRQ_PS2_3 35 -#define MEC1322_IRQ_SPI0_TX 36 -#define MEC1322_IRQ_SPI0_RX 37 -#define MEC1322_IRQ_HTIMER 38 -#define MEC1322_IRQ_KSC_INT 39 +#define MEC1322_IRQ_I2C_0 0 +#define MEC1322_IRQ_I2C_1 1 +#define MEC1322_IRQ_I2C_2 2 +#define MEC1322_IRQ_I2C_3 3 +#define MEC1322_IRQ_DMA_0 4 +#define MEC1322_IRQ_DMA_1 5 +#define MEC1322_IRQ_DMA_2 6 +#define MEC1322_IRQ_DMA_3 7 +#define MEC1322_IRQ_DMA_4 8 +#define MEC1322_IRQ_DMA_5 9 +#define MEC1322_IRQ_DMA_6 10 +#define MEC1322_IRQ_DMA_7 11 +#define MEC1322_IRQ_LPC 12 +#define MEC1322_IRQ_UART 13 +#define MEC1322_IRQ_EMI 14 +#define MEC1322_IRQ_ACPIEC0_IBF 15 +#define MEC1322_IRQ_ACPIEC0_OBF 16 +#define MEC1322_IRQ_ACPIEC1_IBF 17 +#define MEC1322_IRQ_ACPIEC1_OBF 18 +#define MEC1322_IRQ_ACPIPM1_CTL 19 +#define MEC1322_IRQ_ACPIPM1_EN 20 +#define MEC1322_IRQ_ACPIPM1_STS 21 +#define MEC1322_IRQ_8042EM_OBF 22 +#define MEC1322_IRQ_8042EM_IBF 23 +#define MEC1322_IRQ_MAILBOX 24 +#define MEC1322_IRQ_PECI_HOST 25 +#define MEC1322_IRQ_TACH_0 26 +#define MEC1322_IRQ_TACH_1 27 +#define MEC1322_IRQ_ADC_SNGL 28 +#define MEC1322_IRQ_ADC_RPT 29 +#define MEC1322_IRQ_PS2_0 32 +#define MEC1322_IRQ_PS2_1 33 +#define MEC1322_IRQ_PS2_2 34 +#define MEC1322_IRQ_PS2_3 35 +#define MEC1322_IRQ_SPI0_TX 36 +#define MEC1322_IRQ_SPI0_RX 37 +#define MEC1322_IRQ_HTIMER 38 +#define MEC1322_IRQ_KSC_INT 39 #define MEC1322_IRQ_MAILBOX_DATA 40 -#define MEC1322_IRQ_TIMER16_0 49 -#define MEC1322_IRQ_TIMER16_1 50 -#define MEC1322_IRQ_TIMER16_2 51 -#define MEC1322_IRQ_TIMER16_3 52 -#define MEC1322_IRQ_TIMER32_0 53 -#define MEC1322_IRQ_TIMER32_1 54 -#define MEC1322_IRQ_SPI1_TX 55 -#define MEC1322_IRQ_SPI1_RX 56 -#define MEC1322_IRQ_GIRQ8 57 -#define MEC1322_IRQ_GIRQ9 58 -#define MEC1322_IRQ_GIRQ10 59 -#define MEC1322_IRQ_GIRQ11 60 -#define MEC1322_IRQ_GIRQ12 61 -#define MEC1322_IRQ_GIRQ13 62 -#define MEC1322_IRQ_GIRQ14 63 -#define MEC1322_IRQ_GIRQ15 64 -#define MEC1322_IRQ_GIRQ16 65 -#define MEC1322_IRQ_GIRQ17 66 -#define MEC1322_IRQ_GIRQ18 67 -#define MEC1322_IRQ_GIRQ19 68 -#define MEC1322_IRQ_GIRQ20 69 -#define MEC1322_IRQ_GIRQ21 70 -#define MEC1322_IRQ_GIRQ22 71 -#define MEC1322_IRQ_GIRQ23 72 -#define MEC1322_IRQ_DMA_8 81 -#define MEC1322_IRQ_DMA_9 82 -#define MEC1322_IRQ_DMA_10 83 -#define MEC1322_IRQ_DMA_11 84 -#define MEC1322_IRQ_PWM_WDT3 85 -#define MEC1322_IRQ_RTC 91 -#define MEC1322_IRQ_RTC_ALARM 92 +#define MEC1322_IRQ_TIMER16_0 49 +#define MEC1322_IRQ_TIMER16_1 50 +#define MEC1322_IRQ_TIMER16_2 51 +#define MEC1322_IRQ_TIMER16_3 52 +#define MEC1322_IRQ_TIMER32_0 53 +#define MEC1322_IRQ_TIMER32_1 54 +#define MEC1322_IRQ_SPI1_TX 55 +#define MEC1322_IRQ_SPI1_RX 56 +#define MEC1322_IRQ_GIRQ8 57 +#define MEC1322_IRQ_GIRQ9 58 +#define MEC1322_IRQ_GIRQ10 59 +#define MEC1322_IRQ_GIRQ11 60 +#define MEC1322_IRQ_GIRQ12 61 +#define MEC1322_IRQ_GIRQ13 62 +#define MEC1322_IRQ_GIRQ14 63 +#define MEC1322_IRQ_GIRQ15 64 +#define MEC1322_IRQ_GIRQ16 65 +#define MEC1322_IRQ_GIRQ17 66 +#define MEC1322_IRQ_GIRQ18 67 +#define MEC1322_IRQ_GIRQ19 68 +#define MEC1322_IRQ_GIRQ20 69 +#define MEC1322_IRQ_GIRQ21 70 +#define MEC1322_IRQ_GIRQ22 71 +#define MEC1322_IRQ_GIRQ23 72 +#define MEC1322_IRQ_DMA_8 81 +#define MEC1322_IRQ_DMA_9 82 +#define MEC1322_IRQ_DMA_10 83 +#define MEC1322_IRQ_DMA_11 84 +#define MEC1322_IRQ_PWM_WDT3 85 +#define MEC1322_IRQ_RTC 91 +#define MEC1322_IRQ_RTC_ALARM 92 /* Wake pin definitions, defined at board-level */ #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC -- cgit v1.2.1 From b92fbe0b0e1188a5b905f40271abd60cd37d8a40 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:27 -0600 Subject: zephyr/projects/intelrvp/src/intel_rvp_board_id.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie35f8b6f2e436f6d48289c7401ede7eee819240f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730778 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/src/intel_rvp_board_id.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c index d4172a468e..ea8e98da3a 100644 --- a/zephyr/projects/intelrvp/src/intel_rvp_board_id.c +++ b/zephyr/projects/intelrvp/src/intel_rvp_board_id.c @@ -9,25 +9,22 @@ #define DT_DRV_COMPAT intel_rvp_board_id BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, - "Unsupported RVP Board ID instance"); + "Unsupported RVP Board ID instance"); #define RVP_ID_GPIO_DT_SPEC_GET(idx, node_id, prop) \ GPIO_DT_SPEC_GET_BY_IDX(node_id, prop, idx), -#define RVP_ID_CONFIG_LIST(node_id, prop) \ - LISTIFY(DT_PROP_LEN(node_id, prop), \ - RVP_ID_GPIO_DT_SPEC_GET, (), node_id, prop) +#define RVP_ID_CONFIG_LIST(node_id, prop) \ + LISTIFY(DT_PROP_LEN(node_id, prop), RVP_ID_GPIO_DT_SPEC_GET, (), \ + node_id, prop) #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) -const struct gpio_dt_spec bom_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), bom_gpios) -}; +const struct gpio_dt_spec bom_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + bom_gpios) }; -const struct gpio_dt_spec fab_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), fab_gpios) -}; +const struct gpio_dt_spec fab_id_config[] = { RVP_ID_CONFIG_LIST(DT_DRV_INST(0), + fab_gpios) }; -const struct gpio_dt_spec board_id_config[] = { - RVP_ID_CONFIG_LIST(DT_DRV_INST(0), board_gpios) -}; +const struct gpio_dt_spec board_id_config[] = { RVP_ID_CONFIG_LIST( + DT_DRV_INST(0), board_gpios) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 688e4c08f8fff0ea45aada5fc84f3ffda409b4e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:03 -0600 Subject: board/blipper/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I001e77b88723332765d909135fe514e939c0ad1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728034 Reviewed-by: Jeremy Bettis --- board/blipper/led.c | 58 ++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/board/blipper/led.c b/board/blipper/led.c index c28b39f6af..43afc9873f 100644 --- a/board/blipper/led.c +++ b/board/blipper/led.c @@ -11,42 +11,46 @@ #include "gpio.h" #include "pwm.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From 3703b77aea2a3b91361e723dc0476cbb98941fa5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:07 -0600 Subject: board/guybrush/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5df87ef5468c43b86b3172767210b11f468f441e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728436 Reviewed-by: Jeremy Bettis --- board/guybrush/board.c | 90 ++++++++++++++++++++++---------------------------- 1 file changed, 39 insertions(+), 51 deletions(-) diff --git a/board/guybrush/board.c b/board/guybrush/board.c index 6ba8de04c9..e2f799e064 100644 --- a/board/guybrush/board.c +++ b/board/guybrush/board.c @@ -45,17 +45,13 @@ static struct bmi_drv_data_t g_bmi_data; static struct accelgyro_saved_data_t g_bma422_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* * We have total 30 pins for keyboard connecter {-1, -1} mean @@ -63,16 +59,15 @@ const mat33_fp_t lid_standard_ref = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -222,51 +217,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me) } __override int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - PS8818_RX_INPUT_TERM_112_OHM); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + PS8818_RX_INPUT_TERM_112_OHM); if (rv) return rv; } @@ -274,11 +264,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -356,8 +345,7 @@ static void board_chipset_startup(void) if (get_board_version() > 1) tmp112_init(); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); int board_get_soc_temp_k(int idx, int *temp_k) { -- cgit v1.2.1 From 5579ac78578c708323e3851c8d35d43dfb2e7632 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:44 -0600 Subject: board/pdeval-stm32f072/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I33bfe0f8192b38f007afc67f07fdbc6dd39f9033 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728817 Reviewed-by: Jeremy Bettis --- board/pdeval-stm32f072/board.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/pdeval-stm32f072/board.c b/board/pdeval-stm32f072/board.c index 525f14a4af..e089a34cef 100644 --- a/board/pdeval-stm32f072/board.c +++ b/board/pdeval-stm32f072/board.c @@ -30,10 +30,10 @@ void alert_event(enum gpio_signal signal) #include "gpio_list.h" const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("PDeval-stm32f072"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("PDeval-stm32f072"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"), }; @@ -52,15 +52,11 @@ void board_reset_pd_mcu(void) } /* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = I2C_PORT_TCPC, - .kbps = 400 /* kHz */, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - } -}; +const struct i2c_port_t i2c_ports[] = { { .name = "tcpc", + .port = I2C_PORT_TCPC, + .kbps = 400 /* kHz */, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA } }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { -- cgit v1.2.1 From 191c94438770ab2567c74aee6531d8f74d05e0f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:54 -0600 Subject: board/trembyle/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia0a878903eb90814b8410217ac68becca3166d8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729023 Reviewed-by: Jeremy Bettis --- board/trembyle/board.h | 104 +++++++++++++++++++------------------------------ 1 file changed, 41 insertions(+), 63 deletions(-) diff --git a/board/trembyle/board.h b/board/trembyle/board.h index 6d3382af08..38b1739c5f 100644 --- a/board/trembyle/board.h +++ b/board/trembyle/board.h @@ -29,36 +29,32 @@ #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_AP18F4M, @@ -71,11 +67,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -84,11 +76,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -153,57 +141,47 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBC1_RETIMER_PS8802 \ - (BIT(TREMBYLE_DB_T_OPT2_USBAC) | \ - BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_USBC1_RETIMER_PS8802 \ + (BIT(TREMBYLE_DB_T_OPT2_USBAC) | \ + BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_usbc1_retimer_ps8802(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8802); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802); } -#define HAS_USBC1_RETIMER_PS8818 \ - (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) +#define HAS_USBC1_RETIMER_PS8818 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_usbc1_retimer_ps8818(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8818); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } -#define HAS_MST_HUB_RTD2141B \ - (BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_MST_HUB_RTD2141B (BIT(TREMBYLE_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_mst_hub_rtd2141b(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_MST_HUB_RTD2141B); + return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B); } -#define HAS_HDMI_CONN_HPD \ - (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) +#define HAS_HDMI_CONN_HPD (BIT(TREMBYLE_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_hdmi_conn_hpd(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_CONN_HPD); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD); } -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB_C0_HPD \ - : (ec_config_has_usbc1_retimer_ps8802()) \ - ? GPIO_DP1_HPD \ - : GPIO_DP2_HPD) +#define PORT_TO_HPD(port) \ + ((port == 0) ? GPIO_USB_C0_HPD : \ + (ec_config_has_usbc1_retimer_ps8802()) ? GPIO_DP1_HPD : \ + GPIO_DP2_HPD) extern const struct usb_mux usbc0_pi3dpx1207_usb_retimer; extern const struct usb_mux usbc1_ps8802; -- cgit v1.2.1 From d1727309a4b35a93d7ba6f89d40e1952c679a8f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:36 -0600 Subject: baseboard/herobrine/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6749807740df6fcc8f471c8070fd110a114bae1d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727887 Reviewed-by: Jeremy Bettis --- baseboard/herobrine/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/herobrine/usbc_config.c b/baseboard/herobrine/usbc_config.c index f5ee9c157d..f1a5d63411 100644 --- a/baseboard/herobrine/usbc_config.c +++ b/baseboard/herobrine/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From ca2cd9c481261c5727bc6ff3d93be3d9c2a097b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:57 -0600 Subject: zephyr/shim/src/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I823bc06fbbcb4f05b13cc44faf00466398005156 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730901 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/system.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/src/system.c b/zephyr/shim/src/system.c index 807bbd50b0..89356edf60 100644 --- a/zephyr/shim/src/system.c +++ b/zephyr/shim/src/system.c @@ -14,10 +14,10 @@ #include "system.h" #include "watchdog.h" -#define BBRAM_REGION_PD0 DT_PATH(named_bbram_regions, pd0) -#define BBRAM_REGION_PD1 DT_PATH(named_bbram_regions, pd1) -#define BBRAM_REGION_PD2 DT_PATH(named_bbram_regions, pd2) -#define BBRAM_REGION_TRY_SLOT DT_PATH(named_bbram_regions, try_slot) +#define BBRAM_REGION_PD0 DT_PATH(named_bbram_regions, pd0) +#define BBRAM_REGION_PD1 DT_PATH(named_bbram_regions, pd1) +#define BBRAM_REGION_PD2 DT_PATH(named_bbram_regions, pd2) +#define BBRAM_REGION_TRY_SLOT DT_PATH(named_bbram_regions, try_slot) #define GET_BBRAM_OFFSET(node) \ DT_PROP(DT_PATH(named_bbram_regions, node), offset) @@ -172,9 +172,8 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Total time on: %.6llds\n", ts.val); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", + "Print last idle stats"); #endif const char *system_get_chip_vendor(void) -- cgit v1.2.1 From d355cdd91e9a2343c2236d88fee79b6a364b8bfe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:19 -0600 Subject: zephyr/test/drivers/src/isl923x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0a90ef1f04748f4cafe22f2971294ce90d52125 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730974 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/isl923x.c | 49 ++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/zephyr/test/drivers/src/isl923x.c b/zephyr/test/drivers/src/isl923x.c index 203a2ed979..321845ea04 100644 --- a/zephyr/test/drivers/src/isl923x.c +++ b/zephyr/test/drivers/src/isl923x.c @@ -131,19 +131,18 @@ ZTEST(isl923x, test_isl923x_set_input_current_limit) { const struct emul *isl923x_emul = ISL923X_EMUL; struct i2c_emul *i2c_emul = isl923x_emul_get_i2c_emul(isl923x_emul); - int expected_current_milli_amps[] = { - EXPECTED_INPUT_CURRENT_MA(0), - EXPECTED_INPUT_CURRENT_MA(4), - EXPECTED_INPUT_CURRENT_MA(8), - EXPECTED_INPUT_CURRENT_MA(16), - EXPECTED_INPUT_CURRENT_MA(32), - EXPECTED_INPUT_CURRENT_MA(64), - EXPECTED_INPUT_CURRENT_MA(128), - EXPECTED_INPUT_CURRENT_MA(256), - EXPECTED_INPUT_CURRENT_MA(512), - EXPECTED_INPUT_CURRENT_MA(1024), - EXPECTED_INPUT_CURRENT_MA(2048), - EXPECTED_INPUT_CURRENT_MA(4096) }; + int expected_current_milli_amps[] = { EXPECTED_INPUT_CURRENT_MA(0), + EXPECTED_INPUT_CURRENT_MA(4), + EXPECTED_INPUT_CURRENT_MA(8), + EXPECTED_INPUT_CURRENT_MA(16), + EXPECTED_INPUT_CURRENT_MA(32), + EXPECTED_INPUT_CURRENT_MA(64), + EXPECTED_INPUT_CURRENT_MA(128), + EXPECTED_INPUT_CURRENT_MA(256), + EXPECTED_INPUT_CURRENT_MA(512), + EXPECTED_INPUT_CURRENT_MA(1024), + EXPECTED_INPUT_CURRENT_MA(2048), + EXPECTED_INPUT_CURRENT_MA(4096) }; int current_milli_amps; /* Test failing to write to current limit 1 reg */ @@ -230,10 +229,9 @@ ZTEST(isl923x, test_device_id) zassert_equal(0x5678, id, NULL); /* Test read error */ - i2c_common_emul_set_read_fail_reg(i2c_emul, - ISL923X_REG_DEVICE_ID); - zassert_equal(EC_ERROR_INVAL, - isl923x_drv.device_id(CHARGER_NUM, &id), NULL); + i2c_common_emul_set_read_fail_reg(i2c_emul, ISL923X_REG_DEVICE_ID); + zassert_equal(EC_ERROR_INVAL, isl923x_drv.device_id(CHARGER_NUM, &id), + NULL); /* Reset fail register */ i2c_common_emul_set_read_fail_reg(i2c_emul, @@ -576,8 +574,8 @@ ZTEST(isl923x, test_get_vbus_voltage) * VBUS. */ zassert_within(expected_voltage_mv, voltage, 100, - "Expected %dmV but got %dmV", expected_voltage_mv, - voltage); + "Expected %dmV but got %dmV", + expected_voltage_mv, voltage); } } @@ -622,8 +620,7 @@ ZTEST(isl923x, test_init) NULL); zassert_equal(0, input_current, - "Expected input current 0mA but got %dmA", - input_current); + "Expected input current 0mA but got %dmA", input_current); /* Test failed CTRL 0 write */ isl923x_emul_reset_registers(isl923x_emul); @@ -636,8 +633,7 @@ ZTEST(isl923x, test_init) NULL); zassert_equal(0, input_current, - "Expected input current 0mA but got %dmA", - input_current); + "Expected input current 0mA but got %dmA", input_current); /* Test failed CTRL 3 read */ isl923x_emul_reset_registers(isl923x_emul); @@ -832,8 +828,9 @@ ZTEST(isl923x_hibernate, test_isl923x_hibernate__happy_path) /* Check ISL923X_REG_CONTROL1 */ actual = isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1); - zassert_false(actual & RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE, - "RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE should not be set"); + zassert_false( + actual & RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE, + "RAA489000_C1_ENABLE_SUPP_SUPPORT_MODE should not be set"); zassert_false(actual & ISL923X_C1_ENABLE_PSYS, "ISL923X_C1_ENABLE_PSYS should not be set"); zassert_true(actual & RAA489000_C1_BGATE_FORCE_OFF, @@ -1004,7 +1001,7 @@ ZTEST(isl923x_hibernate, test_isl9238c_hibernate) /* Part 1: Happy path */ control1_expected = (isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL1) & - ~ISL923X_C1_ENABLE_PSYS) | + ~ISL923X_C1_ENABLE_PSYS) | ISL923X_C1_DISABLE_MON; control2_expected = isl923x_emul_peek_reg(i2c_emul, ISL923X_REG_CONTROL2) | -- cgit v1.2.1 From b1c05494b975daebc42b171d41711d67e60c7a30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:57 -0600 Subject: board/kano/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2d4db4ecd932f7f9e00badc81312184624407917 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728484 Reviewed-by: Jeremy Bettis --- board/kano/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/kano/led.c b/board/kano/led.c index 23c9fca50c..ec1febf29b 100644 --- a/board/kano/led.c +++ b/board/kano/led.c @@ -18,23 +18,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From a1436e1b19eceeb19308a7bdaff00f8848568591 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:19 -0600 Subject: driver/led/lm3630a.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfce9d69a1ad2a0126c0e2d6816aafd83fd46734 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730015 Reviewed-by: Jeremy Bettis --- driver/led/lm3630a.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/driver/led/lm3630a.c b/driver/led/lm3630a.c index e927c677a4..005912724b 100644 --- a/driver/led/lm3630a.c +++ b/driver/led/lm3630a.c @@ -10,14 +10,12 @@ #include "lm3630a.h" #include "timer.h" - /* I2C address */ #define LM3630A_I2C_ADDR_FLAGS 0x36 static inline int lm3630a_write(uint8_t reg, uint8_t val) { - return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS, - reg, val); + return i2c_write8(I2C_PORT_KBLIGHT, LM3630A_I2C_ADDR_FLAGS, reg, val); } static void deferred_lm3630a_poweron(void) @@ -46,23 +44,22 @@ int lm3630a_poweron(void) /* Enable feedback and PWM for banks A. */ ret |= lm3630a_write(LM3630A_REG_CONFIG, - LM3630A_CFG_BIT_FB_EN_A | - LM3630A_CFG_BIT_PWM_EN_A); + LM3630A_CFG_BIT_FB_EN_A | + LM3630A_CFG_BIT_PWM_EN_A); /* 24V, 800mA overcurrent protection, 500kHz boost frequency. */ ret |= lm3630a_write(LM3630A_REG_BOOST_CONTROL, - LM3630A_BOOST_OVP_24V | - LM3630A_BOOST_OCP_800MA | - LM3630A_FMODE_500KHZ); + LM3630A_BOOST_OVP_24V | LM3630A_BOOST_OCP_800MA | + LM3630A_FMODE_500KHZ); /* Limit current to 24.5mA */ ret |= lm3630a_write(LM3630A_REG_A_CURRENT, 0x1a); /* Enable bank A, put in linear mode, and connect LED2 to bank A. */ ret |= lm3630a_write(LM3630A_REG_CONTROL, - LM3630A_CTRL_BIT_LINEAR_A | - LM3630A_CTRL_BIT_LED_EN_A | - LM3630A_CTRL_BIT_LED2_ON_A); + LM3630A_CTRL_BIT_LINEAR_A | + LM3630A_CTRL_BIT_LED_EN_A | + LM3630A_CTRL_BIT_LED2_ON_A); /* * Only set the brightness after ~100 ms. Without this, LED may blink -- cgit v1.2.1 From 60a45bc49851306fc8e7051861f9d945b891c0ac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:51 -0600 Subject: chip/mt_scp/mt818x/ipi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifa32d6bbc75c3b3d17d35115ee63667c75b75957 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729348 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/ipi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/mt_scp/mt818x/ipi.c b/chip/mt_scp/mt818x/ipi.c index 8b695d57e0..7fc1039b90 100644 --- a/chip/mt_scp/mt818x/ipi.c +++ b/chip/mt_scp/mt818x/ipi.c @@ -196,7 +196,6 @@ int ipi_send(int32_t id, const void *buf, uint32_t len, int wait) return EC_ERROR_BUSY; } - scp_send_obj->id = id; scp_send_obj->len = len; memcpy(scp_send_obj->buffer, buf, len); -- cgit v1.2.1 From c31bbaeac2b16f855df2f300c27cbe26ffd1d1c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:38 -0600 Subject: driver/tcpm/tusb422.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I116183a2b2fc0cf5085f4f5b90cfd34693408cf2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730101 Reviewed-by: Jeremy Bettis --- driver/tcpm/tusb422.c | 52 +++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/driver/tcpm/tusb422.c b/driver/tcpm/tusb422.c index 6e07bce5e1..b2ca8ef83f 100644 --- a/driver/tcpm/tusb422.c +++ b/driver/tcpm/tusb422.c @@ -36,7 +36,7 @@ enum tusb422_reg_addr { enum vbus_and_vconn_control_mask { INT_VCONNDIS_DISABLE = BIT(1), - INT_VBUSDIS_DISABLE = BIT(2), + INT_VBUSDIS_DISABLE = BIT(2), }; /* The TUSB422 cannot drive an FRS GPIO, but can detect FRS */ @@ -86,7 +86,7 @@ static int tusb422_tcpci_tcpm_init(int port) * Mode. */ tcpc_write(port, TUSB422_REG_VBUS_AND_VCONN_CONTROL, - INT_VBUSDIS_DISABLE); + INT_VBUSDIS_DISABLE); } if (IS_ENABLED(CONFIG_USB_PD_FRS_TCPC)) { /* Disable FRS detection, and enable the FRS detection alert */ @@ -103,7 +103,7 @@ static int tusb422_tcpci_tcpm_init(int port) */ /* Enable VBUS detection */ return tcpc_write16(port, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_ENABLE_VBUS_DETECT); + TCPC_REG_COMMAND_ENABLE_VBUS_DETECT); } static int tusb422_tcpm_set_cc(int port, int pull) @@ -154,40 +154,40 @@ static void tusb422_tcpci_tcpc_alert(int port) } const struct tcpm_drv tusb422_tcpm_drv = { - .init = &tusb422_tcpci_tcpm_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &tusb422_tcpci_tcpm_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tusb422_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tusb422_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tusb422_tcpci_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tusb422_tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif .tcpc_enable_auto_discharge_disconnect = - &tcpci_tcpc_enable_auto_discharge_disconnect, + &tcpci_tcpc_enable_auto_discharge_disconnect, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tusb422_tcpc_drp_toggle, + .drp_toggle = &tusb422_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, - .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &tcpci_get_chip_info, + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &tcpci_enter_low_power_mode, + .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_USB_PD_FRS_TCPC - .set_frs_enable = &tusb422_set_frs_enable, + .set_frs_enable = &tusb422_set_frs_enable, #endif }; -- cgit v1.2.1 From 596255f515af59b7ca78864b70849d1bc0ca99e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:54 -0600 Subject: power/meteorlake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55993b8007f621b6a78398b863199fb90b1832a7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727062 Reviewed-by: Jeremy Bettis --- power/meteorlake.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/power/meteorlake.c b/power/meteorlake.c index 80785c2345..9a92768ad3 100644 --- a/power/meteorlake.c +++ b/power/meteorlake.c @@ -20,14 +20,13 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(signal, value) \ gpio_set_level_verbose(CC_CHIPSET, signal, value) #else -#define GPIO_SET_LEVEL(signal, value) \ - gpio_set_level(signal, value) +#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value) #endif /* Power signals list. Must match order of enum power_signal. */ @@ -117,7 +116,6 @@ static void enable_pp5000_rail(void) power_5v_enable(task_get_current(), 1); else GPIO_SET_LEVEL(GPIO_EN_PP5000, 1); - } /* @@ -126,7 +124,7 @@ static void enable_pp5000_rail(void) * ¶m level 0 deasserts the signal, other values assert the signal */ static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal, - int level) + int level) { GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level); } @@ -167,8 +165,9 @@ static void all_sys_pwrgd_pass_thru(void) } /* PCH_PWROK is combination of ALL_SYS_PWRGD and SLP_S3 */ - gpio_set_level(GPIO_PCH_PWROK, all_sys_pwrgd_in && - power_signal_get_level(SLP_S3_SIGNAL_L)); + gpio_set_level(GPIO_PCH_PWROK, + all_sys_pwrgd_in && + power_signal_get_level(SLP_S3_SIGNAL_L)); } enum power_state power_handle_state(enum power_state state) @@ -178,7 +177,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_G3S5: if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) { /* -- cgit v1.2.1 From b4246fb6c728b28bd9d59470347a75b9140b2916 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:55 -0600 Subject: board/pompom/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0bd7993ed3ba8e41e54ea35d2f036f9b036fbba5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728840 Reviewed-by: Jeremy Bettis --- board/pompom/led.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/pompom/led.c b/board/pompom/led.c index db571a067c..bfe7be7ded 100644 --- a/board/pompom/led.c +++ b/board/pompom/led.c @@ -31,21 +31,21 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color_battery(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL); + (color == LED_AMBER) ? LED_ON_LVL : LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_W_C0, - (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL); + (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL); } void led_set_color_power(enum led_color color) { gpio_set_level(GPIO_EC_PWR_LED_W, - (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL); + (color == LED_WHITE) ? LED_ON_LVL : LED_OFF_LVL); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From 5f1af845c34bbea308a193d70ae6d7058f12559d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:25 -0600 Subject: chip/npcx/rom_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e294bef1946cbed9297e255142717aa09bde947 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729429 Reviewed-by: Jeremy Bettis --- chip/npcx/rom_chip.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h index bb66f95e88..fe6678971f 100644 --- a/chip/npcx/rom_chip.h +++ b/chip/npcx/rom_chip.h @@ -42,25 +42,23 @@ enum API_RETURN_STATUS_T { /* * Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) +#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40) #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) + status) \ + (((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)( \ + src_offset, dest_addr, size, sign, exe_addr, status)) /******************************************************************************/ /* * Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( +typedef void (*download_from_flash_ptr)( uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ + uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ + uint32_t size, /* Number of bytes to download */ enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ uint32_t exe_addr, /* jump to this address after download if not zero */ enum API_RETURN_STATUS_T *status /* Status fo download */ ); - - #endif /* __CROS_EC_ROM_CHIP_H_ */ -- cgit v1.2.1 From 7481a1240caa09820f7f21d7da01dc61c25c20ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:38 -0600 Subject: chip/mchp/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I975b1c3baa6b0474cecbebd2c5f04dffd81d4fbb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729244 Reviewed-by: Jeremy Bettis --- chip/mchp/i2c.c | 147 +++++++++++++++++++++++++++++--------------------------- 1 file changed, 75 insertions(+), 72 deletions(-) diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c index 2aaef83dfe..edb01a49de 100644 --- a/chip/mchp/i2c.c +++ b/chip/mchp/i2c.c @@ -24,77 +24,77 @@ /* * MCHP I2C BAUD clock source is 16 MHz. */ -#define I2C_CLOCK 16000000UL -#define MCHP_I2C_SUPPORTED_BUS_CLOCKS 6 +#define I2C_CLOCK 16000000UL +#define MCHP_I2C_SUPPORTED_BUS_CLOCKS 6 /* SMBus Timing values for 1MHz Speed */ -#define SPEED_1MHZ_BUS_CLOCK 0x0509ul -#define SPEED_1MHZ_DATA_TIMING 0x06060601ul -#define SPEED_1MHZ_DATA_TIMING_2 0x06ul -#define SPEED_1MHZ_IDLE_SCALING 0x01000050ul -#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7ul +#define SPEED_1MHZ_BUS_CLOCK 0x0509ul +#define SPEED_1MHZ_DATA_TIMING 0x06060601ul +#define SPEED_1MHZ_DATA_TIMING_2 0x06ul +#define SPEED_1MHZ_IDLE_SCALING 0x01000050ul +#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7ul /* SMBus Timing values for 400kHz speed */ -#define SPEED_400KHZ_BUS_CLOCK 0x0F17ul -#define SPEED_400KHZ_DATA_TIMING 0x040A0F01ul -#define SPEED_400KHZ_DATA_TIMING_2 0x0Aul -#define SPEED_400KHZ_IDLE_SCALING 0x01000050ul -#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7ul +#define SPEED_400KHZ_BUS_CLOCK 0x0F17ul +#define SPEED_400KHZ_DATA_TIMING 0x040A0F01ul +#define SPEED_400KHZ_DATA_TIMING_2 0x0Aul +#define SPEED_400KHZ_IDLE_SCALING 0x01000050ul +#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7ul /* SMBus Timing values for 100kHz speed */ -#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful -#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul -#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul -#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul -#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul +#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful +#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul +#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul +#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul +#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul /* Bus clock dividers for 333, 80, and 40 kHz */ -#define SPEED_333KHZ_BUS_CLOCK 0x0F1Ful -#define SPEED_80KHZ_BUS_CLOCK 0x6363ul -#define SPEED_40KHZ_BUS_CLOCK 0xC7C7ul +#define SPEED_333KHZ_BUS_CLOCK 0x0F1Ful +#define SPEED_80KHZ_BUS_CLOCK 0x6363ul +#define SPEED_40KHZ_BUS_CLOCK 0xC7C7ul /* Status */ -#define STS_NBB BIT(0) /* Bus busy */ -#define STS_LAB BIT(1) /* Arbitration lost */ -#define STS_LRB BIT(3) /* Last received bit */ -#define STS_BER BIT(4) /* Bus error */ -#define STS_PIN BIT(7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK BIT(0) /* Acknowledge */ -#define CTRL_STO BIT(1) /* STOP */ -#define CTRL_STA BIT(2) /* START */ -#define CTRL_ENI BIT(3) /* Enable interrupt */ -#define CTRL_ESO BIT(6) /* Enable serial output */ -#define CTRL_PIN BIT(7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_DTEN BIT(2) /* enable device timeouts */ -#define COMP_MCEN BIT(3) /* enable ctrl. cumulative timeouts */ -#define COMP_SCEN BIT(4) /* enable periph. cumulative timeouts */ -#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */ -#define COMP_IDLE BIT(29) /* i2c bus is idle */ -#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ +#define COMP_DTEN BIT(2) /* enable device timeouts */ +#define COMP_MCEN BIT(3) /* enable ctrl. cumulative timeouts */ +#define COMP_SCEN BIT(4) /* enable periph. cumulative timeouts */ +#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ +#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Configuration */ -#define CFG_PORT_MASK (0x0F) /* port selection field */ -#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */ -#define CFG_FEN BIT(8) /* enable input filtering */ -#define CFG_RESET BIT(9) /* reset controller */ -#define CFG_ENABLE BIT(10) /* enable controller */ -#define CFG_GC_DIS BIT(14) /* disable general call address */ -#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */ +#define CFG_PORT_MASK (0x0F) /* port selection field */ +#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */ +#define CFG_FEN BIT(8) /* enable input filtering */ +#define CFG_RESET BIT(9) /* reset controller */ +#define CFG_ENABLE BIT(10) /* enable controller */ +#define CFG_GC_DIS BIT(14) /* disable general call address */ +#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */ /* Enable network layer controller done interrupt */ -#define CFG_ENMI BIT(30) +#define CFG_ENMI BIT(30) /* Enable network layer peripheral done interrupt */ -#define CFG_ENSI BIT(31) +#define CFG_ENSI BIT(31) /* Controller Command */ -#define MCMD_MRUN BIT(0) -#define MCMD_MPROCEED BIT(1) -#define MCMD_START0 BIT(8) -#define MCMD_STARTN BIT(9) -#define MCMD_STOP BIT(10) -#define MCMD_READM BIT(12) -#define MCMD_WCNT_BITPOS (16) -#define MCMD_WCNT_MASK0 (0xFF) -#define MCMD_WCNT_MASK (0xFF << 16) -#define MCMD_RCNT_BITPOS (24) -#define MCMD_RCNT_MASK0 (0xFF) -#define MCMD_RCNT_MASK (0xFF << 24) +#define MCMD_MRUN BIT(0) +#define MCMD_MPROCEED BIT(1) +#define MCMD_START0 BIT(8) +#define MCMD_STARTN BIT(9) +#define MCMD_STOP BIT(10) +#define MCMD_READM BIT(12) +#define MCMD_WCNT_BITPOS (16) +#define MCMD_WCNT_MASK0 (0xFF) +#define MCMD_WCNT_MASK (0xFF << 16) +#define MCMD_RCNT_BITPOS (24) +#define MCMD_RCNT_MASK0 (0xFF) +#define MCMD_RCNT_MASK (0xFF << 24) /* Maximum transfer of a SMBUS block transfer */ #define SMBUS_MAX_BLOCK_SIZE 32 @@ -146,34 +146,37 @@ static struct { uint8_t lines; } cdata[I2C_CONTROLLER_COUNT]; -static const uint16_t i2c_ctrl_nvic_id[] = { - MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3, +static const uint16_t i2c_ctrl_nvic_id[] = { MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, + MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3, #if defined(CHIP_FAMILY_MEC172X) - MCHP_IRQ_I2C_4 + MCHP_IRQ_I2C_4 #elif defined(CHIP_FAMILY_MEC152X) - MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7 + MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, + MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7 #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX); -static const uint16_t i2c_controller_pcr[] = { - MCHP_PCR_I2C0, MCHP_PCR_I2C1, MCHP_PCR_I2C2, MCHP_PCR_I2C3, +static const uint16_t i2c_controller_pcr[] = { MCHP_PCR_I2C0, MCHP_PCR_I2C1, + MCHP_PCR_I2C2, MCHP_PCR_I2C3, #if defined(CHIP_FAMILY_MEC172X) - MCHP_PCR_I2C4 + MCHP_PCR_I2C4 #elif defined(CHIP_FAMILY_MEC152X) MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7, #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX); -static uintptr_t i2c_ctrl_base_addr[] = { - MCHP_I2C0_BASE, MCHP_I2C1_BASE, MCHP_I2C2_BASE, MCHP_I2C3_BASE, +static uintptr_t i2c_ctrl_base_addr[] = { MCHP_I2C0_BASE, MCHP_I2C1_BASE, + MCHP_I2C2_BASE, MCHP_I2C3_BASE, #if defined(CHIP_FAMILY_MEC172X) - MCHP_I2C4_BASE + MCHP_I2C4_BASE #elif defined(CHIP_FAMILY_MEC152X) - MCHP_I2C4_BASE, - /* NOTE: 5-7 do not implement network layer hardware */ - MCHP_I2C5_BASE, MCHP_I2C6_BASE, MCHP_I2C7_BASE + MCHP_I2C4_BASE, + /* NOTE: 5-7 do not implement network + layer hardware */ + MCHP_I2C5_BASE, MCHP_I2C6_BASE, + MCHP_I2C7_BASE #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX); @@ -230,7 +233,7 @@ struct i2c_bus_clk { }; const struct i2c_bus_clk i2c_freq_tbl[] = { - { 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK }, + { 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK }, { 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK }, { 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK }, }; -- cgit v1.2.1 From 8b1bff1a484acba7f0c323ef4952cdf7f9a6ec8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:01 -0600 Subject: driver/ppc/syv682x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie2cf834a8b0fab95ed570e7fb7e475fd4f243792 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730052 Reviewed-by: Jeremy Bettis --- driver/ppc/syv682x.h | 142 +++++++++++++++++++++++++-------------------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h index d9416f47f1..9bb3e24556 100644 --- a/driver/ppc/syv682x.h +++ b/driver/ppc/syv682x.h @@ -12,91 +12,91 @@ #include "driver/ppc/syv682x_public.h" /* Source OC deglitch implemented in HW for SYV682B */ -#define SYV682X_HW_OC_DEGLITCH_MS 10 +#define SYV682X_HW_OC_DEGLITCH_MS 10 /* SYV682x register addresses */ -#define SYV682X_STATUS_REG 0x00 -#define SYV682X_CONTROL_1_REG 0x01 -#define SYV682X_CONTROL_2_REG 0x02 -#define SYV682X_CONTROL_3_REG 0x03 -#define SYV682X_CONTROL_4_REG 0x04 +#define SYV682X_STATUS_REG 0x00 +#define SYV682X_CONTROL_1_REG 0x01 +#define SYV682X_CONTROL_2_REG 0x02 +#define SYV682X_CONTROL_3_REG 0x03 +#define SYV682X_CONTROL_4_REG 0x04 /* Status Register */ -#define SYV682X_STATUS_OC_HV BIT(7) -#define SYV682X_STATUS_RVS BIT(6) -#define SYV682X_STATUS_OC_5V BIT(5) -#define SYV682X_STATUS_OVP BIT(4) -#define SYV682X_STATUS_FRS BIT(3) -#define SYV682X_STATUS_TSD BIT(2) -#define SYV682X_STATUS_VSAFE_5V BIT(1) -#define SYV682X_STATUS_VSAFE_0V BIT(0) -#define SYV682X_STATUS_INT_MASK 0xfc +#define SYV682X_STATUS_OC_HV BIT(7) +#define SYV682X_STATUS_RVS BIT(6) +#define SYV682X_STATUS_OC_5V BIT(5) +#define SYV682X_STATUS_OVP BIT(4) +#define SYV682X_STATUS_FRS BIT(3) +#define SYV682X_STATUS_TSD BIT(2) +#define SYV682X_STATUS_VSAFE_5V BIT(1) +#define SYV682X_STATUS_VSAFE_0V BIT(0) +#define SYV682X_STATUS_INT_MASK 0xfc /* Control Register 1 */ -#define SYV682X_CONTROL_1_CH_SEL BIT(1) -#define SYV682X_CONTROL_1_HV_DR BIT(2) -#define SYV682X_CONTROL_1_PWR_ENB BIT(7) +#define SYV682X_CONTROL_1_CH_SEL BIT(1) +#define SYV682X_CONTROL_1_HV_DR BIT(2) +#define SYV682X_CONTROL_1_PWR_ENB BIT(7) -#define SYV682X_5V_ILIM_MASK 0x18 -#define SYV682X_5V_ILIM_BIT_SHIFT 3 -#define SYV682X_5V_ILIM_1_25 0 -#define SYV682X_5V_ILIM_1_75 1 -#define SYV682X_5V_ILIM_2_25 2 -#define SYV682X_5V_ILIM_3_30 3 +#define SYV682X_5V_ILIM_MASK 0x18 +#define SYV682X_5V_ILIM_BIT_SHIFT 3 +#define SYV682X_5V_ILIM_1_25 0 +#define SYV682X_5V_ILIM_1_75 1 +#define SYV682X_5V_ILIM_2_25 2 +#define SYV682X_5V_ILIM_3_30 3 -#define SYV682X_HV_ILIM_MASK 0x60 -#define SYV682X_HV_ILIM_BIT_SHIFT 5 -#define SYV682X_HV_ILIM_1_25 0 -#define SYV682X_HV_ILIM_1_75 1 -#define SYV682X_HV_ILIM_3_30 2 -#define SYV682X_HV_ILIM_5_50 3 +#define SYV682X_HV_ILIM_MASK 0x60 +#define SYV682X_HV_ILIM_BIT_SHIFT 5 +#define SYV682X_HV_ILIM_1_25 0 +#define SYV682X_HV_ILIM_1_75 1 +#define SYV682X_HV_ILIM_3_30 2 +#define SYV682X_HV_ILIM_5_50 3 /* Control Register 2 */ -#define SYV682X_OC_DELAY_MASK GENMASK(7, 6) -#define SYV682X_OC_DELAY_SHIFT 6 -#define SYV682X_OC_DELAY_1MS 0 -#define SYV682X_OC_DELAY_10MS 1 -#define SYV682X_OC_DELAY_50MS 2 -#define SYV682X_OC_DELAY_100MS 3 -#define SYV682X_DSG_TIME_MASK GENMASK(5, 4) -#define SYV682X_DSG_TIME_SHIFT 4 -#define SYV682X_DSG_TIME_50MS 0 -#define SYV682X_DSG_TIME_100MS 1 -#define SYV682X_DSG_TIME_200MS 2 -#define SYV682X_DSG_TIME_400MS 3 -#define SYV682X_DSG_RON_MASK GENMASK(3, 2) -#define SYV682X_DSG_RON_SHIFT 2 -#define SYV682X_DSG_RON_200_OHM 0 -#define SYV682X_DSG_RON_400_OHM 1 -#define SYV682X_DSG_RON_800_OHM 2 -#define SYV682X_DSG_RON_1600_OHM 3 -#define SYV682X_CONTROL_2_SDSG BIT(1) -#define SYV682X_CONTROL_2_FDSG BIT(0) +#define SYV682X_OC_DELAY_MASK GENMASK(7, 6) +#define SYV682X_OC_DELAY_SHIFT 6 +#define SYV682X_OC_DELAY_1MS 0 +#define SYV682X_OC_DELAY_10MS 1 +#define SYV682X_OC_DELAY_50MS 2 +#define SYV682X_OC_DELAY_100MS 3 +#define SYV682X_DSG_TIME_MASK GENMASK(5, 4) +#define SYV682X_DSG_TIME_SHIFT 4 +#define SYV682X_DSG_TIME_50MS 0 +#define SYV682X_DSG_TIME_100MS 1 +#define SYV682X_DSG_TIME_200MS 2 +#define SYV682X_DSG_TIME_400MS 3 +#define SYV682X_DSG_RON_MASK GENMASK(3, 2) +#define SYV682X_DSG_RON_SHIFT 2 +#define SYV682X_DSG_RON_200_OHM 0 +#define SYV682X_DSG_RON_400_OHM 1 +#define SYV682X_DSG_RON_800_OHM 2 +#define SYV682X_DSG_RON_1600_OHM 3 +#define SYV682X_CONTROL_2_SDSG BIT(1) +#define SYV682X_CONTROL_2_FDSG BIT(0) /* Control Register 3 */ -#define SYV682X_BUSY BIT(7) -#define SYV682X_RVS_MASK BIT(3) -#define SYV682X_RST_REG BIT(0) -#define SYV682X_OVP_MASK 0x70 -#define SYV682X_OVP_BIT_SHIFT 4 -#define SYV682X_OVP_06_0 0 -#define SYV682X_OVP_08_0 1 -#define SYV682X_OVP_11_1 2 -#define SYV682X_OVP_12_1 3 -#define SYV682X_OVP_14_2 4 -#define SYV682X_OVP_17_9 5 -#define SYV682X_OVP_21_6 6 -#define SYV682X_OVP_23_7 7 +#define SYV682X_BUSY BIT(7) +#define SYV682X_RVS_MASK BIT(3) +#define SYV682X_RST_REG BIT(0) +#define SYV682X_OVP_MASK 0x70 +#define SYV682X_OVP_BIT_SHIFT 4 +#define SYV682X_OVP_06_0 0 +#define SYV682X_OVP_08_0 1 +#define SYV682X_OVP_11_1 2 +#define SYV682X_OVP_12_1 3 +#define SYV682X_OVP_14_2 4 +#define SYV682X_OVP_17_9 5 +#define SYV682X_OVP_21_6 6 +#define SYV682X_OVP_23_7 7 /* Control Register 4 */ -#define SYV682X_CONTROL_4_CC1_BPS BIT(7) -#define SYV682X_CONTROL_4_CC2_BPS BIT(6) -#define SYV682X_CONTROL_4_VCONN1 BIT(5) -#define SYV682X_CONTROL_4_VCONN2 BIT(4) -#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) -#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) -#define SYV682X_CONTROL_4_CC_FRS BIT(1) -#define SYV682X_CONTROL_4_INT_MASK 0x0c +#define SYV682X_CONTROL_4_CC1_BPS BIT(7) +#define SYV682X_CONTROL_4_CC2_BPS BIT(6) +#define SYV682X_CONTROL_4_VCONN1 BIT(5) +#define SYV682X_CONTROL_4_VCONN2 BIT(4) +#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) +#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) +#define SYV682X_CONTROL_4_CC_FRS BIT(1) +#define SYV682X_CONTROL_4_INT_MASK 0x0c /* * syv682x_board_is_syv682c -- cgit v1.2.1 From 58385e65363a04d996a68cf3228b7f3e409bd502 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:54 -0600 Subject: board/adlrvpp_ite/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f203e86a3e3754eaf271cfc9297e4b96f981c8a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727963 Reviewed-by: Jeremy Bettis --- board/adlrvpp_ite/board.h | 80 +++++++++++++++++++++++------------------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h index 55b56854ea..4059cf05dd 100644 --- a/board/adlrvpp_ite/board.h +++ b/board/adlrvpp_ite/board.h @@ -19,56 +19,56 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC -#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC -#define GPIO_LID_OPEN GPIO_SMC_LID -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC -#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N -#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC -#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L -#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP -#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R -#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT -#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R -#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC -#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC -#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC -#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC -#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC -#define GPIO_EN_PP3300_A GPIO_EC_DS3 -#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION +#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC +#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC +#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L +#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT +#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R +#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC +#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC +#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC +#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC +#define GPIO_EN_PP3300_A GPIO_EC_DS3 +#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION /* I2C ports & Configs */ #define CONFIG_IT83XX_SMCLK2_ON_GPC7 -#define I2C_PORT_CHARGER IT83XX_I2C_CH_B +#define I2C_PORT_CHARGER IT83XX_I2C_CH_B /* Battery */ -#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B /* Board ID */ -#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B +#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B /* Port 80 */ -#define I2C_PORT_PORT80 IT83XX_I2C_CH_B +#define I2C_PORT_PORT80 IT83XX_I2C_CH_B /* USB-C I2C */ -#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C -#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F +#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C +#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F #if defined(HAS_TASK_PD_C2) -#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E -#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D +#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E +#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D #endif /* TCPC */ @@ -76,12 +76,12 @@ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 /* Config Fan */ -#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N -#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC +#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N +#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC /* Increase EC speed */ #undef PLL_CLOCK -#define PLL_CLOCK 96000000 +#define PLL_CLOCK 96000000 #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 3d833637973b1504517fcf260618691867427212 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:09 -0600 Subject: board/pirika/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d8bf2dfd2fc9da6b932bc2737bbd18984d6e829 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728826 Reviewed-by: Jeremy Bettis --- board/pirika/board.c | 134 ++++++++++++++++++++++----------------------------- 1 file changed, 57 insertions(+), 77 deletions(-) diff --git a/board/pirika/board.c b/board/pirika/board.c index 7a21d632d2..19b7d31e71 100644 --- a/board/pirika/board.c +++ b/board/pirika/board.c @@ -41,8 +41,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -104,8 +104,8 @@ static const struct ec_response_keybd_config pasara_kb = { }, .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT) return &pirika_kb; @@ -188,34 +188,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -275,40 +267,31 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; /* USB Retimer */ -enum tusb544_conf { - USB_DP = 0, - USB_DP_INV, - USB, - USB_INV, - DP, - DP_INV -}; +enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV }; -static int board_tusb544_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state) { - int rv = EC_SUCCESS; + int rv = EC_SUCCESS; enum tusb544_conf usb_mode = 0; /* USB */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_DP_INV - : USB_DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_DP_INV : + USB_DP; } /* USB without DP */ else { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_INV - : USB; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_INV : + USB; } } /* DP without USB */ else if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? DP_INV - : DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV : + DP; } /* Nothing enabled */ else @@ -521,8 +504,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -584,12 +566,10 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(0); return EC_SUCCESS; - } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -622,7 +602,7 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Sensor Data */ -static struct kionix_accel_data g_kx022_data; +static struct kionix_accel_data g_kx022_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Drivers */ @@ -702,26 +682,26 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Vcore", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Vcore", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(68), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -735,8 +715,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_VCORE \ - { \ +#define THERMAL_VCORE \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -750,8 +730,8 @@ __maybe_unused static const struct ec_thermal_config thermal_vcore = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_AMBIENT \ - { \ +#define THERMAL_AMBIENT \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From ccda17229482dd6bc6dc1cb80810b2033520594d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:00 -0600 Subject: board/dewatt/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I134836db3efab83d9dbe80632c35c8d6788a94d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728200 Reviewed-by: Jeremy Bettis --- board/dewatt/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/dewatt/led.c b/board/dewatt/led.c index 7cbb9133bf..4d5ab312e0 100644 --- a/board/dewatt/led.c +++ b/board/dewatt/led.c @@ -14,10 +14,10 @@ #include "pwm.h" /* Note PWM LEDs are active low */ -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) __override const int led_charge_lvl_1 = 5; @@ -45,20 +45,29 @@ static void led_pwm_ch_init(void) DECLARE_HOOK(HOOK_INIT, led_pwm_ch_init, HOOK_PRIO_INIT_PWM - 1); __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_S5] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 3ec19be3e53198356f1536bb2126539a91652ce7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:52 -0600 Subject: include/hwtimer.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If5f05b54b25fc8805798a2197303eb9a46efa38d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730282 Reviewed-by: Jeremy Bettis --- include/hwtimer.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/hwtimer.h b/include/hwtimer.h index 3c0e9aaf8a..f93537f935 100644 --- a/include/hwtimer.h +++ b/include/hwtimer.h @@ -34,7 +34,8 @@ void __hw_clock_event_clear(void); #ifdef CONFIG_HWTIMER_64BIT __override_proto #endif -uint32_t __hw_clock_source_read(void); + uint32_t + __hw_clock_source_read(void); /** * Override the lower 32-bits of the hardware counter @@ -115,4 +116,4 @@ void hwtimer_setup_watchdog(void); /* Reset the watchdog timer, to avoid the watchdog warning */ void hwtimer_reset_watchdog(void); -#endif /* __CROS_EC_HWTIMER_H */ +#endif /* __CROS_EC_HWTIMER_H */ -- cgit v1.2.1 From 57a743293fb1404bacdaa63dbe6aea2de7d118d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:05 -0600 Subject: board/trogdor/hibernate.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b485b3db17a5b78081e9b37799df2680221b96c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729026 Reviewed-by: Jeremy Bettis --- board/trogdor/hibernate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/trogdor/hibernate.c b/board/trogdor/hibernate.c index 504a295463..e32f56db83 100644 --- a/board/trogdor/hibernate.c +++ b/board/trogdor/hibernate.c @@ -11,8 +11,6 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_LID_ACCEL_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } -- cgit v1.2.1 From ae2ee606391d8984b87bfb19bcb41221926f2e6e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:50 -0600 Subject: chip/stm32/usart_tx_dma.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idaa7ebd88c9ba8dbb92649b4b50d2a39b23f1571 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729425 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_tx_dma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/usart_tx_dma.h b/chip/stm32/usart_tx_dma.h index c17164e04a..136df1584d 100644 --- a/chip/stm32/usart_tx_dma.h +++ b/chip/stm32/usart_tx_dma.h @@ -29,7 +29,7 @@ * required because the queue isn't notified that it has been read from until * after the DMA transfer completes. */ -#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ +#define USART_TX_DMA(CHANNEL, MAX_BYTES) \ ((struct usart_tx_dma const) { \ .usart_tx = { \ .consumer_ops = { \ -- cgit v1.2.1 From ff651438fe7356e88eb6613f70b4b1eb6d08cf41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:35 -0600 Subject: driver/tcpm/fusb302.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I81cbb9e27e9e2b6c747fd807726010b07be1d820 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730090 Reviewed-by: Jeremy Bettis --- driver/tcpm/fusb302.c | 107 +++++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 57 deletions(-) diff --git a/driver/tcpm/fusb302.c b/driver/tcpm/fusb302.c index 8357359012..4c4a035469 100644 --- a/driver/tcpm/fusb302.c +++ b/driver/tcpm/fusb302.c @@ -25,8 +25,8 @@ #error "Unsupported config options of fusb302 PD driver" #endif -#define PACKET_IS_GOOD_CRC(head) (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && \ - PD_HEADER_CNT(head) == 0) +#define PACKET_IS_GOOD_CRC(head) \ + (PD_HEADER_TYPE(head) == PD_CTRL_GOOD_CRC && PD_HEADER_CNT(head) == 0) static struct fusb302_chip_state { int cc_polarity; @@ -77,7 +77,7 @@ static void fusb302_auto_goodcrc_enable(int port, int enable) { int reg; - tcpc_read(port, TCPC_REG_SWITCHES1, ®); + tcpc_read(port, TCPC_REG_SWITCHES1, ®); if (enable) reg |= TCPC_REG_SWITCHES1_AUTO_GCRC; @@ -158,8 +158,8 @@ static int measure_cc_pin_source(int port, int cc_measure) /* Read status register */ tcpc_read(port, TCPC_REG_STATUS0, ®); - cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD - : TYPEC_CC_VOLT_RA; + cc_lvl = (reg & TCPC_REG_STATUS0_COMP) ? TYPEC_CC_VOLT_RD : + TYPEC_CC_VOLT_RA; } /* Restore SWITCHES0 register to its value prior */ @@ -172,8 +172,8 @@ static int measure_cc_pin_source(int port, int cc_measure) /* Determine cc pin state for source when in manual detect mode */ static void detect_cc_pin_source_manual(int port, - enum tcpc_cc_voltage_status *cc1_lvl, - enum tcpc_cc_voltage_status *cc2_lvl) + enum tcpc_cc_voltage_status *cc1_lvl, + enum tcpc_cc_voltage_status *cc2_lvl) { int cc1_measure = TCPC_REG_SWITCHES0_MEAS_CC1; int cc2_measure = TCPC_REG_SWITCHES0_MEAS_CC2; @@ -189,12 +189,11 @@ static void detect_cc_pin_source_manual(int port, *cc1_lvl = measure_cc_pin_source(port, cc1_measure); *cc2_lvl = measure_cc_pin_source(port, cc2_measure); } - } /* Determine cc pin state for sink */ static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int reg; int orig_meas_cc1; @@ -220,7 +219,6 @@ static void detect_cc_pin_sink(int port, enum tcpc_cc_voltage_status *cc1, else orig_meas_cc2 = 0; - /* Disable CC2 measurement switch, enable CC1 measurement switch */ reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2; reg |= TCPC_REG_SWITCHES0_MEAS_CC1; @@ -296,7 +294,7 @@ static int get_num_bytes(uint16_t header) } static int fusb302_send_message(int port, uint16_t header, const uint32_t *data, - uint8_t *buf, int buf_pos) + uint8_t *buf, int buf_pos) { int rv; int reg; @@ -472,7 +470,7 @@ static int fusb302_tcpm_release(int port) } static int fusb302_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { if (state[port].pulling_up) { /* Source mode? */ @@ -504,12 +502,12 @@ static int fusb302_tcpm_set_cc(int port, int pull) TCPC_REG_SWITCHES0_VCONN_CC2); reg |= TCPC_REG_SWITCHES0_CC1_PU_EN | - TCPC_REG_SWITCHES0_CC2_PU_EN; + TCPC_REG_SWITCHES0_CC2_PU_EN; if (state[port].vconn_enabled) reg |= state[port].cc_polarity ? - TCPC_REG_SWITCHES0_VCONN_CC1 : - TCPC_REG_SWITCHES0_VCONN_CC2; + TCPC_REG_SWITCHES0_VCONN_CC1 : + TCPC_REG_SWITCHES0_VCONN_CC2; tcpc_write(port, TCPC_REG_SWITCHES0, reg); @@ -609,7 +607,7 @@ static int fusb302_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) } __maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port, - bool enable) + bool enable) { int reg; @@ -617,11 +615,9 @@ __maybe_unused static int fusb302_tcpm_decode_sop_prime_enable(int port, return EC_ERROR_UNKNOWN; if (enable) - reg |= (TCPC_REG_CONTROL1_ENSOP1 | - TCPC_REG_CONTROL1_ENSOP2); + reg |= (TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2); else - reg &= ~(TCPC_REG_CONTROL1_ENSOP1 | - TCPC_REG_CONTROL1_ENSOP2); + reg &= ~(TCPC_REG_CONTROL1_ENSOP1 | TCPC_REG_CONTROL1_ENSOP2); return tcpc_write(port, TCPC_REG_CONTROL1, reg); } @@ -648,12 +644,11 @@ static int fusb302_tcpm_set_vconn(int port, int enable) if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) { if (state[port].rx_enable) { if (fusb302_tcpm_decode_sop_prime_enable(port, - true)) + true)) return EC_ERROR_UNKNOWN; } } } else { - tcpc_read(port, TCPC_REG_SWITCHES0, ®); /* clear VCONN switch bits */ @@ -665,7 +660,7 @@ static int fusb302_tcpm_set_vconn(int port, int enable) if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) { if (state[port].rx_enable) { if (fusb302_tcpm_decode_sop_prime_enable(port, - false)) + false)) return EC_ERROR_UNKNOWN; } } @@ -731,7 +726,6 @@ static int fusb302_tcpm_set_rx_enable(int port, int enable) /* flush rx fifo in case messages have been coming our way */ fusb302_flush_rx_fifo(port); - } else { tcpc_write(port, TCPC_REG_SWITCHES0, reg); @@ -814,7 +808,8 @@ static int fusb302_tcpm_get_message_raw(int port, uint32_t *payload, int *head) * No START, but do issue a STOP at the end. * add 4 to len to read CRC out */ - rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len+4, I2C_XFER_STOP); + rv |= tcpc_xfer_unlocked(port, 0, 0, buf, len + 4, + I2C_XFER_STOP); tcpc_lock(port, 0); } while (!rv && PACKET_IS_GOOD_CRC(*head) && @@ -988,9 +983,8 @@ void fusb302_tcpc_alert(int port) if (interrupt & TCPC_REG_INTERRUPT_VBUSOK) { /* VBUS crossed threshold */ #ifdef CONFIG_USB_CHARGER - usb_charger_vbus_change(port, - fusb302_tcpm_check_vbus_level(port, - VBUS_PRESENT)); + usb_charger_vbus_change(port, fusb302_tcpm_check_vbus_level( + port, VBUS_PRESENT)); #else if (!fusb302_tcpm_check_vbus_level(port, VBUS_PRESENT)) pd_vbus_low(port); @@ -1040,7 +1034,6 @@ void fusb302_tcpc_alert(int port) fusb302_flush_rx_fifo(port); } } - } /* For BIST receiving */ @@ -1064,16 +1057,16 @@ static int fusb302_set_toggle_mode(int port, int mode) int reg, rv; rv = i2c_read8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_CONTROL2, ®); + tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2, + ®); if (rv) return rv; reg &= ~TCPC_REG_CONTROL2_MODE_MASK; reg |= mode << TCPC_REG_CONTROL2_MODE_POS; return i2c_write8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_CONTROL2, reg); + tcpc_config[port].i2c_info.addr_flags, + TCPC_REG_CONTROL2, reg); } static int fusb302_tcpm_enter_low_power_mode(int port) @@ -1087,8 +1080,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port) * - start toggling */ rv = i2c_write8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_POWER, TCPC_REG_POWER_PWR_LOW); + tcpc_config[port].i2c_info.addr_flags, TCPC_REG_POWER, + TCPC_REG_POWER_PWR_LOW); if (rv) return rv; @@ -1101,8 +1094,8 @@ static int fusb302_tcpm_enter_low_power_mode(int port) break; case PD_DRP_FREEZE: mode = pd_get_power_role(port) == PD_ROLE_SINK ? - TCPC_REG_CONTROL2_MODE_UFP : - TCPC_REG_CONTROL2_MODE_DFP; + TCPC_REG_CONTROL2_MODE_UFP : + TCPC_REG_CONTROL2_MODE_DFP; break; case PD_DRP_FORCE_SINK: mode = TCPC_REG_CONTROL2_MODE_UFP; @@ -1118,14 +1111,14 @@ static int fusb302_tcpm_enter_low_power_mode(int port) usleep(250); rv = i2c_read8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_CONTROL2, ®); + tcpc_config[port].i2c_info.addr_flags, TCPC_REG_CONTROL2, + ®); if (rv) return rv; reg |= TCPC_REG_CONTROL2_TOGGLE; return i2c_write8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_CONTROL2, reg); + tcpc_config[port].i2c_info.addr_flags, + TCPC_REG_CONTROL2, reg); } #endif @@ -1143,7 +1136,7 @@ static int fusb302_compare_mdac(int port, int mdac) tcpc_read(port, TCPC_REG_MEASURE, &orig_reg); /* set reg_measure bit 0~5 to mdac, and bit6 to 1(measure vbus) */ tcpc_write(port, TCPC_REG_MEASURE, - (mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS); + (mdac & TCPC_REG_MEASURE_MDAC_MASK) | TCPC_REG_MEASURE_VBUS); /* Wait on measurement */ usleep(350); @@ -1181,25 +1174,25 @@ int tcpc_get_vbus_voltage(int port) } const struct tcpm_drv fusb302_tcpm_drv = { - .init = &fusb302_tcpm_init, - .release = &fusb302_tcpm_release, - .get_cc = &fusb302_tcpm_get_cc, + .init = &fusb302_tcpm_init, + .release = &fusb302_tcpm_release, + .get_cc = &fusb302_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &fusb302_tcpm_check_vbus_level, + .check_vbus_level = &fusb302_tcpm_check_vbus_level, #endif - .select_rp_value = &fusb302_tcpm_select_rp_value, - .set_cc = &fusb302_tcpm_set_cc, - .set_polarity = &fusb302_tcpm_set_polarity, + .select_rp_value = &fusb302_tcpm_select_rp_value, + .set_cc = &fusb302_tcpm_set_cc, + .set_polarity = &fusb302_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &fusb302_tcpm_decode_sop_prime_enable, + .sop_prime_enable = &fusb302_tcpm_decode_sop_prime_enable, #endif - .set_vconn = &fusb302_tcpm_set_vconn, - .set_msg_header = &fusb302_tcpm_set_msg_header, - .set_rx_enable = &fusb302_tcpm_set_rx_enable, - .get_message_raw = &fusb302_tcpm_get_message_raw, - .transmit = &fusb302_tcpm_transmit, - .tcpc_alert = &fusb302_tcpc_alert, + .set_vconn = &fusb302_tcpm_set_vconn, + .set_msg_header = &fusb302_tcpm_set_msg_header, + .set_rx_enable = &fusb302_tcpm_set_rx_enable, + .get_message_raw = &fusb302_tcpm_get_message_raw, + .transmit = &fusb302_tcpm_transmit, + .tcpc_alert = &fusb302_tcpc_alert, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &fusb302_tcpm_enter_low_power_mode, + .enter_low_power_mode = &fusb302_tcpm_enter_low_power_mode, #endif }; -- cgit v1.2.1 From 8dd71cf33dc4090ca1f1ef78366f4abd51c36a6a Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 14:20:14 +0800 Subject: zephyr: battery: add BYD L22B3PG0 Add BYD L22B3PG0 battery BUG=b:235434904 TEST=zmake testall BRANCH=none Change-Id: Ie3f009a81cb7c97f80e182c6f3e95df041772a1e Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697272 Reviewed-by: Mike Lee Reviewed-by: Eric Yilun Lin --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/byd,l22b3pg0.yaml | 54 ++++++++++++++++++++++++++ zephyr/dts/bindings/vendor-prefixes.txt | 1 + 3 files changed, 56 insertions(+) create mode 100644 zephyr/dts/bindings/battery/byd,l22b3pg0.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index c2c6d28175..fcaf1aa0e3 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -13,6 +13,7 @@ properties: enum: - "aec,5477109" - "as3gwrc3ka,c235-41" + - "byd,l22b3pg0" - "ganfeng,7c01" - "getac,bq40z50-R3-S3" - "getac,bq40z50-R3-S2" diff --git a/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml new file mode 100644 index 0000000000..2b827dcbf7 --- /dev/null +++ b/zephyr/dts/bindings/battery/byd,l22b3pg0.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "BYD L22B3PG0" +compatible: "byd,l22b3pg0" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "byd,l22b3pg0" + + # Fuel gauge + manuf_name: + default: "BYD" + device_name: + default: "L22B3PG0" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x34 + fet_reg_mask: + default: 0x0100 + fet_disconnect_val: + default: 0x0100 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11310 + voltage_min: + default: 9000 + precharge_current: + default: 416 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 70 + diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt index 403b0ba1ea..efe9db3e96 100644 --- a/zephyr/dts/bindings/vendor-prefixes.txt +++ b/zephyr/dts/bindings/vendor-prefixes.txt @@ -15,3 +15,4 @@ aec Battery vendor powertech Battery vendor getac Battery vendor ganfeng Battery vendor +byd Battery vendor -- cgit v1.2.1 From 96e07fc781c2d9d1214b5befd9b1dfcb8a64efe7 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 15:00:05 +0800 Subject: zephyr: battery: add Celxpert L22C3PG0 Add Celxpert L22C3PG0 battery BUG=b:235332195 TEST=zmake testall BRANCH=none Change-Id: Iba7c59e7d8bf753932dbac598b74a8087a079187 Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697273 Reviewed-by: Sung-Chi Li Reviewed-by: Mike Lee --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml | 54 ++++++++++++++++++++++ zephyr/dts/bindings/vendor-prefixes.txt | 1 + 3 files changed, 56 insertions(+) create mode 100644 zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index fcaf1aa0e3..fc44b8465b 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -14,6 +14,7 @@ properties: - "aec,5477109" - "as3gwrc3ka,c235-41" - "byd,l22b3pg0" + - "celxpert,l22c3pg0" - "ganfeng,7c01" - "getac,bq40z50-R3-S3" - "getac,bq40z50-R3-S2" diff --git a/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml new file mode 100644 index 0000000000..64ac926990 --- /dev/null +++ b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "CELXPERT L22C3PG0" +compatible: "celxpert,l22c3pg0" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "celxpert,l22c3pg0" + + # Fuel gauge + manuf_name: + default: "Celxpert" + device_name: + default: "L22C3PG0" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x34 + fet_reg_mask: + default: 0x0100 + fet_disconnect_val: + default: 0x0100 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11310 + voltage_min: + default: 9000 + precharge_current: + default: 416 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 70 + diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt index efe9db3e96..0aa061c6d8 100644 --- a/zephyr/dts/bindings/vendor-prefixes.txt +++ b/zephyr/dts/bindings/vendor-prefixes.txt @@ -16,3 +16,4 @@ powertech Battery vendor getac Battery vendor ganfeng Battery vendor byd Battery vendor +celxpert Battery vendor -- cgit v1.2.1 From d3affe7123a9f7b8ff504c5e56faf41d8bcea104 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 15:44:35 +0800 Subject: zephyr: battery: add Sunwoda L22D3PG0 Add Sunwoda L22D3PG0 battery BUG=b:235456598 TEST=zmake testall BRANCH=none Change-Id: Ic12db06f0875fade3a06a6915b7a00a575e38a9d Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697274 Reviewed-by: Mike Lee Reviewed-by: Sung-Chi Li --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml | 54 +++++++++++++++++++++++ zephyr/dts/bindings/vendor-prefixes.txt | 1 + 3 files changed, 56 insertions(+) create mode 100644 zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index fc44b8465b..b509a44ba3 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -31,3 +31,4 @@ properties: - "smp,l20m3pg0" - "smp,l20m3pg1" - "smp,l20m3pg2" + - "sunwoda,l22d3pg0" diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml new file mode 100644 index 0000000000..9d4da91747 --- /dev/null +++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "SUNWODA L22D3PG0" +compatible: "sunwoda,l22d3pg0" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "sunwoda,l22d3pg0" + + # Fuel gauge + manuf_name: + default: "Sunwoda" + device_name: + default: "L22D3PG0" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x34 + fet_reg_mask: + default: 0x0100 + fet_disconnect_val: + default: 0x0100 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11310 + voltage_min: + default: 9000 + precharge_current: + default: 209 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 63 + discharging_min_c: + default: -20 + discharging_max_c: + default: 63 + diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt index 0aa061c6d8..fb01231208 100644 --- a/zephyr/dts/bindings/vendor-prefixes.txt +++ b/zephyr/dts/bindings/vendor-prefixes.txt @@ -17,3 +17,4 @@ getac Battery vendor ganfeng Battery vendor byd Battery vendor celxpert Battery vendor +sunwoda Battery vendor -- cgit v1.2.1 From eeaecf0fa7415004302fd570d7865eaee5707a85 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 16:03:42 +0800 Subject: zephyr: battery: add SMP L22M3PG0 Add SMP L22M3PG0 battery BUG=b:235459059 TEST=zmake testall BRANCH=none Change-Id: Ie8377e9f668dd91fed2b2c0060091d31367850fe Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697275 Reviewed-by: Eric Yilun Lin Reviewed-by: Mike Lee --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/smp,l22m3pg0.yaml | 54 ++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 zephyr/dts/bindings/battery/smp,l22m3pg0.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index b509a44ba3..37c4fe9485 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -31,4 +31,5 @@ properties: - "smp,l20m3pg0" - "smp,l20m3pg1" - "smp,l20m3pg2" + - "smp,l22m3pg0" - "sunwoda,l22d3pg0" diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml new file mode 100644 index 0000000000..e0b9722675 --- /dev/null +++ b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "SMP L22M3PG0" +compatible: "smp,l22m3pg0" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "smp,l22m3pg0" + + # Fuel gauge + manuf_name: + default: "SMP" + device_name: + default: "L22M3PG0" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x34 + fet_reg_mask: + default: 0x0100 + fet_disconnect_val: + default: 0x0100 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11310 + voltage_min: + default: 9000 + precharge_current: + default: 208 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 60 + -- cgit v1.2.1 From ad82204d2a910e4be2542b0dd198278e6a707346 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 16:43:10 +0800 Subject: zephyr: battery: add COSMX L22X3PG0 Add COSMX L22X3PG0 battery BUG=b:235460488 TEST=zmake testall BRANCH=none Change-Id: I42fd8e59378a604e77307d9fec6cb84a5c8615f2 Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3698176 Reviewed-by: Eric Yilun Lin Reviewed-by: Mike Lee --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml | 54 +++++++++++++++++++++++++ zephyr/dts/bindings/vendor-prefixes.txt | 1 + 3 files changed, 56 insertions(+) create mode 100644 zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index 37c4fe9485..edcb239703 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -15,6 +15,7 @@ properties: - "as3gwrc3ka,c235-41" - "byd,l22b3pg0" - "celxpert,l22c3pg0" + - "cosmx,l22x3pg0" - "ganfeng,7c01" - "getac,bq40z50-R3-S3" - "getac,bq40z50-R3-S2" diff --git a/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml new file mode 100644 index 0000000000..ddcc67c3a0 --- /dev/null +++ b/zephyr/dts/bindings/battery/cosmx,l22x3pg0.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "COSMX L22X3PG0" +compatible: "cosmx,l22x3pg0" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "cosmx,l22x3pg0" + + # Fuel gauge + manuf_name: + default: "COSMX" + device_name: + default: "L22X3PG0" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x34 + fet_reg_mask: + default: 0x0100 + fet_disconnect_val: + default: 0x0100 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11310 + voltage_min: + default: 9000 + precharge_current: + default: 207 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 70 + diff --git a/zephyr/dts/bindings/vendor-prefixes.txt b/zephyr/dts/bindings/vendor-prefixes.txt index fb01231208..c9b56f8c65 100644 --- a/zephyr/dts/bindings/vendor-prefixes.txt +++ b/zephyr/dts/bindings/vendor-prefixes.txt @@ -18,3 +18,4 @@ ganfeng Battery vendor byd Battery vendor celxpert Battery vendor sunwoda Battery vendor +cosmx Battery vendor -- cgit v1.2.1 From edf0de91bac5eb7e0b51424b117c31ff90e09db2 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Thu, 9 Jun 2022 17:05:37 +0800 Subject: steelix: add supported batteries Add five supported batteries for Steelix. The supported batteries are as follows: 1. byd_l22b3pg0 2. celxpert_l22c3pg0 3. cosmx_l22x3pg0 4. smp_l22m3pg0 5. sunwoda_l22d3pg0 BUG=b:232050545 TEST=1)Battery is detected at EC bootup 2)Battery cutoff is working as expected BRANCH=none Change-Id: I53c313d0cad395e3af794dd42267b09e29cb2379 Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3698177 Reviewed-by: Eric Yilun Lin Reviewed-by: Mike Lee --- zephyr/projects/corsola/battery_steelix.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/corsola/battery_steelix.dts b/zephyr/projects/corsola/battery_steelix.dts index 63d3b7ea21..aad956ba71 100644 --- a/zephyr/projects/corsola/battery_steelix.dts +++ b/zephyr/projects/corsola/battery_steelix.dts @@ -5,11 +5,20 @@ / { batteries { - default_battery: smp_l20m3pg2 { - compatible = "smp,l20m3pg2", "battery-smart"; + default_battery: byd_l22b3pg0 { + compatible = "byd,l22b3pg0", "battery-smart"; }; - lgc_l20l3pg2 { - compatible = "lgc,l20l3pg2", "battery-smart"; + celxpert_l22c3pg0 { + compatible = "celxpert,l22c3pg0", "battery-smart"; + }; + cosmx_l22x3pg0 { + compatible = "cosmx,l22x3pg0", "battery-smart"; + }; + smp_l22m3pg0 { + compatible = "smp,l22m3pg0", "battery-smart"; + }; + sunwoda_l22d3pg0 { + compatible = "sunwoda,l22d3pg0", "battery-smart"; }; }; }; -- cgit v1.2.1 From bdaf468174fa0ee7e9bebc36367667f8d28d721e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:04 -0600 Subject: chip/mec1322/lfw/ec_lfw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11a070eb69adc5a849d20b855bbfd9f2df41bf64 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729332 Reviewed-by: Jeremy Bettis --- chip/mec1322/lfw/ec_lfw.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/mec1322/lfw/ec_lfw.h b/chip/mec1322/lfw/ec_lfw.h index dd26fbd323..861057d1a9 100644 --- a/chip/mec1322/lfw/ec_lfw.h +++ b/chip/mec1322/lfw/ec_lfw.h @@ -8,16 +8,16 @@ #include -noreturn void lfw_main(void) __attribute__ ((naked)); +noreturn void lfw_main(void) __attribute__((naked)); void fault_handler(void) __attribute__((naked)); struct int_vector_t { - void *stack_ptr; - void *reset_vector; - void *nmi; - void *hard_fault; - void *bus_fault; - void *usage_fault; + void *stack_ptr; + void *reset_vector; + void *nmi; + void *hard_fault; + void *bus_fault; + void *usage_fault; }; -#define SPI_CHUNK_SIZE 1024 +#define SPI_CHUNK_SIZE 1024 -- cgit v1.2.1 From ce885602829b07db13087506c7ddf41600797c3a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:23 -0600 Subject: board/katsu/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2643344892f9c883ae2b84bf38de5805fbc04372 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728530 Reviewed-by: Jeremy Bettis --- board/katsu/led.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/katsu/led.c b/board/katsu/led.c index c72f5e4cdb..f94a474b0c 100644 --- a/board/katsu/led.c +++ b/board/katsu/led.c @@ -16,13 +16,13 @@ const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -#define LED_OFF MT6370_LED_ID_OFF -#define LED_AMBER MT6370_LED_ID1 -#define LED_WHITE MT6370_LED_ID2 +#define LED_OFF MT6370_LED_ID_OFF +#define LED_AMBER MT6370_LED_ID1 +#define LED_WHITE MT6370_LED_ID2 -#define LED_MASK_OFF 0 -#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN -#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN +#define LED_MASK_OFF 0 +#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN +#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN static void katsu_led_set_battery(void) { -- cgit v1.2.1 From fe448b3286f26da9d294f92d6be16f0048b14190 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:09 -0600 Subject: driver/retimer/anx7483.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifeacf0b43875e56b1fa00d1c762ff7e7ce75ec0e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730039 Reviewed-by: Jeremy Bettis --- driver/retimer/anx7483.h | 108 +++++++++++++++++++++++------------------------ 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/driver/retimer/anx7483.h b/driver/retimer/anx7483.h index d5f6723818..2346df571d 100644 --- a/driver/retimer/anx7483.h +++ b/driver/retimer/anx7483.h @@ -20,12 +20,12 @@ * 1 DP_EN (0: disable DP mode; 1: Enable DP mode.) * 0 USB_EN (1: disable USB mode; 1: enable USB mode.) */ -#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07 -#define ANX7483_CTRL_REG_BYPASS_EN BIT(5) -#define ANX7483_CTRL_REG_EN BIT(4) -#define ANX7483_CTRL_FLIP_EN BIT(2) -#define ANX7483_CTRL_DP_EN BIT(1) -#define ANX7483_CTRL_USB_EN BIT(0) +#define ANX7483_ANALOG_STATUS_CTRL_REG 0x07 +#define ANX7483_CTRL_REG_BYPASS_EN BIT(5) +#define ANX7483_CTRL_REG_EN BIT(4) +#define ANX7483_CTRL_FLIP_EN BIT(2) +#define ANX7483_CTRL_DP_EN BIT(1) +#define ANX7483_CTRL_USB_EN BIT(0) /* * Register_EQ/FG/SW_EN register @@ -34,8 +34,8 @@ * 7:1 Reserved * 0 Reg_EQ/FG/SW_EN (0: from pin control; 1: from register control) */ -#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15 -#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0) +#define ANX7483_ENABLE_EQ_FLAT_SWING_REG 0x15 +#define ANX7483_ENABLE_EQ_FLAT_SWING_EN BIT(0) /* * EQ Settings Registers @@ -43,20 +43,20 @@ * 7:4 Equilation settings when pin is input * 3:0 Fine tuning EQ step */ -#define ANX7483_UTX1_PORT_CFG0_REG 0x52 -#define ANX7483_UTX2_PORT_CFG0_REG 0x16 -#define ANX7483_URX1_PORT_CFG0_REG 0x3E -#define ANX7483_URX2_PORT_CFG0_REG 0x2A -#define ANX7483_DRX1_PORT_CFG0_REG 0x5C -#define ANX7483_DRX2_PORT_CFG0_REG 0x20 +#define ANX7483_UTX1_PORT_CFG0_REG 0x52 +#define ANX7483_UTX2_PORT_CFG0_REG 0x16 +#define ANX7483_URX1_PORT_CFG0_REG 0x3E +#define ANX7483_URX2_PORT_CFG0_REG 0x2A +#define ANX7483_DRX1_PORT_CFG0_REG 0x5C +#define ANX7483_DRX2_PORT_CFG0_REG 0x20 -#define ANX7483_CFG0_EQ_SHIFT 4 -#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) +#define ANX7483_CFG0_EQ_SHIFT 4 +#define ANX7483_CFG0_EQ_MASK GENMASK(7, 4) /* * Default CFG0 value to apply: 9.2 dB with optimized tuning step */ -#define ANX7483_CFG0_DEF 0x53 +#define ANX7483_CFG0_DEF 0x53 /* * Flat Gain Settings Registers @@ -65,17 +65,17 @@ * 5:4 Flat gain settings when pin is input * 3:0 Fine tuning EQ */ -#define ANX7483_UTX1_PORT_CFG2_REG 0x54 -#define ANX7483_UTX2_PORT_CFG2_REG 0x18 -#define ANX7483_URX1_PORT_CFG2_REG 0x40 -#define ANX7483_URX2_PORT_CFG2_REG 0x2C -#define ANX7483_DRX1_PORT_CFG2_REG 0x5E -#define ANX7483_DRX2_PORT_CFG2_REG 0x22 +#define ANX7483_UTX1_PORT_CFG2_REG 0x54 +#define ANX7483_UTX2_PORT_CFG2_REG 0x18 +#define ANX7483_URX1_PORT_CFG2_REG 0x40 +#define ANX7483_URX2_PORT_CFG2_REG 0x2C +#define ANX7483_DRX1_PORT_CFG2_REG 0x5E +#define ANX7483_DRX2_PORT_CFG2_REG 0x22 /* * Default CFG2 value to apply: 0.3 dB with optimized fine tuning */ -#define ANX7483_CFG2_DEF 0xEE +#define ANX7483_CFG2_DEF 0xEE /* * Swing and 60K Input Termination Registers @@ -85,20 +85,20 @@ * 3:2 Vendor internal use * 1:0 Swing setting when configured as input port */ -#define ANX7483_UTX1_PORT_CFG4_REG 0x56 -#define ANX7483_UTX2_PORT_CFG4_REG 0x1A -#define ANX7483_URX1_PORT_CFG4_REG 0x42 -#define ANX7483_URX2_PORT_CFG4_REG 0x2E -#define ANX7483_DRX1_PORT_CFG4_REG 0x60 -#define ANX7483_DRX2_PORT_CFG4_REG 0x24 -#define ANX7483_DTX1_PORT_CFG4_REG 0x4C -#define ANX7483_DTX2_PORT_CFG4_REG 0x38 +#define ANX7483_UTX1_PORT_CFG4_REG 0x56 +#define ANX7483_UTX2_PORT_CFG4_REG 0x1A +#define ANX7483_URX1_PORT_CFG4_REG 0x42 +#define ANX7483_URX2_PORT_CFG4_REG 0x2E +#define ANX7483_DRX1_PORT_CFG4_REG 0x60 +#define ANX7483_DRX2_PORT_CFG4_REG 0x24 +#define ANX7483_DTX1_PORT_CFG4_REG 0x4C +#define ANX7483_DTX2_PORT_CFG4_REG 0x38 /* * Default values: 1300 mV gain with 60k termination either enabled or disabled */ -#define ANX7483_CFG4_TERM_DISABLE 0x63 -#define ANX7483_CFG4_TERM_ENABLE 0x73 +#define ANX7483_CFG4_TERM_DISABLE 0x63 +#define ANX7483_CFG4_TERM_ENABLE 0x73 /* * Termination Resistance Registers @@ -108,21 +108,21 @@ * 1 Enable termination res for UTX2 path. (0:disable 1: enable.) * 0 Tune Flat Gain. */ -#define ANX7483_UTX1_PORT_CFG3_REG 0x55 -#define ANX7483_UTX2_PORT_CFG3_REG 0x19 -#define ANX7483_URX1_PORT_CFG3_REG 0x41 -#define ANX7483_URX2_PORT_CFG3_REG 0x2D -#define ANX7483_DTX1_PORT_CFG3_REG 0x4B -#define ANX7483_DTX2_PORT_CFG3_REG 0x37 -#define ANX7483_DRX1_PORT_CFG3_REG 0x5F -#define ANX7483_DRX2_PORT_CFG3_REG 0x23 +#define ANX7483_UTX1_PORT_CFG3_REG 0x55 +#define ANX7483_UTX2_PORT_CFG3_REG 0x19 +#define ANX7483_URX1_PORT_CFG3_REG 0x41 +#define ANX7483_URX2_PORT_CFG3_REG 0x2D +#define ANX7483_DTX1_PORT_CFG3_REG 0x4B +#define ANX7483_DTX2_PORT_CFG3_REG 0x37 +#define ANX7483_DRX1_PORT_CFG3_REG 0x5F +#define ANX7483_DRX2_PORT_CFG3_REG 0x23 /* * Default values: Either 100Ohm or 90Ohm, input or output */ -#define ANX7483_CFG3_100Ohm_IN 0x3A -#define ANX7483_CFG3_90Ohm_IN 0x7A -#define ANX7483_CFG3_90Ohm_OUT 0x7E +#define ANX7483_CFG3_100Ohm_IN 0x3A +#define ANX7483_CFG3_90Ohm_IN 0x7A +#define ANX7483_CFG3_90Ohm_OUT 0x7E /* * AUX_Snooping_CTRL register @@ -131,13 +131,13 @@ * 2:1 AUX_VTH (00:60mVppd, 01:90mVppd, 10:120mVppd, 11:140mVppd) * 0 AUX_Snooping_EN (0: disable; 1: enable.) */ -#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13 +#define ANX7483_AUX_SNOOPING_CTRL_REG 0x13 /* * Default value: Enable snooping with 90mVppd * (register ignored outside DP mode and does not need to be cleared) */ -#define ANX7483_AUX_SNOOPING_DEF 0x13 +#define ANX7483_AUX_SNOOPING_DEF 0x13 /* * Middle Frequency Compensation @@ -146,17 +146,17 @@ * 5:3 UTX1_EQ_MFR CTLE middle-freq resistance when input * 2:0 UTX1_EQ_MFC CTLE middle-freq Capacitance */ -#define ANX7483_UTX1_PORT_CFG1_REG 0x53 -#define ANX7483_UTX2_PORT_CFG1_REG 0x17 -#define ANX7483_URX1_PORT_CFG1_REG 0x3F -#define ANX7483_URX2_PORT_CFG1_REG 0x2B -#define ANX7483_DRX1_PORT_CFG1_REG 0x5D -#define ANX7483_DRX2_PORT_CFG1_REG 0x21 +#define ANX7483_UTX1_PORT_CFG1_REG 0x53 +#define ANX7483_UTX2_PORT_CFG1_REG 0x17 +#define ANX7483_URX1_PORT_CFG1_REG 0x3F +#define ANX7483_URX2_PORT_CFG1_REG 0x2B +#define ANX7483_DRX1_PORT_CFG1_REG 0x5D +#define ANX7483_DRX2_PORT_CFG1_REG 0x21 /* * Default CFG1 setting: current bias max, Middle frequency resistance of 0x5, * Middle frequency capacitance of 0x6 */ -#define ANX7483_CFG1_DEF 0xEE +#define ANX7483_CFG1_DEF 0xEE #endif /* __CROS_EC_USB_RETIMER_ANX7483_H */ -- cgit v1.2.1 From b2ef15d463f8cabe9f6b6db1782600ac72871a37 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:43 -0600 Subject: driver/accel_bma4xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id19cae0b32bc7acb22084b5c550978e51feeeb39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729766 Reviewed-by: Jeremy Bettis --- driver/accel_bma4xx.c | 43 ++++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/driver/accel_bma4xx.c b/driver/accel_bma4xx.c index 9b383edf80..0ed15dc2ab 100644 --- a/driver/accel_bma4xx.c +++ b/driver/accel_bma4xx.c @@ -20,7 +20,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /** * Read 8bit register from accelerometer. @@ -97,20 +97,19 @@ static int set_foc_config(struct motion_sensor_t *s) BMA4_NV_ACCEL_OFFSET_MSK)); /* Set accelerometer configurations to 50Hz,CIC, continuous mode */ - RETURN_ERROR(bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR, - BMA4_FOC_ACC_CONF_VAL)); - + RETURN_ERROR( + bma4_write8(s, BMA4_ACCEL_CONFIG_ADDR, BMA4_FOC_ACC_CONF_VAL)); /* Set accelerometer to normal mode by enabling it */ RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CTRL_ADDR, - (BMA4_ENABLE << BMA4_ACCEL_ENABLE_POS), + (BMA4_ENABLE << BMA4_ACCEL_ENABLE_POS), BMA4_ACCEL_ENABLE_MSK)); /* Disable advance power save mode */ - RETURN_ERROR(bma4_set_reg8(s, BMA4_POWER_CONF_ADDR, - (BMA4_DISABLE - << BMA4_ADVANCE_POWER_SAVE_POS), - BMA4_ADVANCE_POWER_SAVE_MSK)); + RETURN_ERROR( + bma4_set_reg8(s, BMA4_POWER_CONF_ADDR, + (BMA4_DISABLE << BMA4_ADVANCE_POWER_SAVE_POS), + BMA4_ADVANCE_POWER_SAVE_MSK)); return EC_SUCCESS; } @@ -120,7 +119,7 @@ static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v) int i; /* Retry 5 times */ - uint8_t reg_data[6] = {0}, try_cnt = 5; + uint8_t reg_data[6] = { 0 }, try_cnt = 5; /* Check if data is ready */ while (try_cnt && (!(reg_data[0] & BMA4_STAT_DATA_RDY_ACCEL_MSK))) { @@ -142,8 +141,8 @@ static int wait_and_read_data(struct motion_sensor_t *s, intv3_t v) BMA4_DATA_8_ADDR, reg_data, 6)); for (i = X; i <= Z; i++) { - v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8) - | (reg_data[i * 2] & 0xf0); + v[i] = (((int8_t)reg_data[i * 2 + 1]) << 8) | + (reg_data[i * 2] & 0xf0); /* Since the resolution is only 12 bits*/ v[i] = (v[i] / 0x10); @@ -160,7 +159,7 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target, intv3_t accel_data, offset; /* Structure to store accelerometer data temporarily */ - int32_t delta_value[3] = {0, 0, 0}; + int32_t delta_value[3] = { 0, 0, 0 }; /* Variable to define count */ uint8_t i, loop, sample_count = 0; @@ -181,8 +180,10 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target, * (unit of offset:mg) */ for (i = X; i <= Z; ++i) { - offset[i] = ((((delta_value[i] * 1000 * sens_range) - / sample_count) / 2048) * -1); + offset[i] = ((((delta_value[i] * 1000 * sens_range) / + sample_count) / + 2048) * + -1); } RETURN_ERROR(write_accel_offset(s, offset)); @@ -199,7 +200,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) { uint8_t config[2]; int pwr_ctrl, pwr_conf; - intv3_t target = {0, 0, 0}; + intv3_t target = { 0, 0, 0 }; int sens_range = s->current_range; if (!enable) @@ -207,7 +208,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) /* Read accelerometer configurations */ RETURN_ERROR(i2c_read_block(s->port, s->i2c_spi_addr_flags, - BMA4_ACCEL_CONFIG_ADDR, config, 2)); + BMA4_ACCEL_CONFIG_ADDR, config, 2)); /* Get accelerometer enable status to be saved */ RETURN_ERROR(bma4_read8(s, BMA4_POWER_CTRL_ADDR, &pwr_ctrl)); @@ -225,7 +226,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) /* Set the saved sensor configuration */ RETURN_ERROR(i2c_write_block(s->port, s->i2c_spi_addr_flags, - BMA4_ACCEL_CONFIG_ADDR, config, 2)); + BMA4_ACCEL_CONFIG_ADDR, config, 2)); RETURN_ERROR(bma4_write8(s, BMA4_POWER_CTRL_ADDR, pwr_ctrl)); @@ -236,7 +237,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) static int set_range(struct motion_sensor_t *s, int range, int round) { - int ret, range_reg_val; + int ret, range_reg_val; range_reg_val = BMA4_RANGE_TO_REG(range); @@ -366,8 +367,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v) mutex_lock(s->mutex); /* Read 6 bytes starting at X_AXIS_LSB. */ - ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, - BMA4_DATA_8_ADDR, acc, 6); + ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, BMA4_DATA_8_ADDR, + acc, 6); mutex_unlock(s->mutex); -- cgit v1.2.1 From e00ceccda67139b3e1473ec799ee14d4dad100b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:03 -0600 Subject: zephyr/shim/src/gpio_int.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie56fe73f180bc472872a283b382009878cc1a440 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730894 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/gpio_int.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/src/gpio_int.c b/zephyr/shim/src/gpio_int.c index 6f13976acc..e79fcdc7fd 100644 --- a/zephyr/shim/src/gpio_int.c +++ b/zephyr/shim/src/gpio_int.c @@ -174,7 +174,7 @@ int gpio_enable_dt_interrupt(const struct gpio_int_config *conf) } const struct gpio_int_config * - gpio_interrupt_get_config(enum gpio_interrupts intr) +gpio_interrupt_get_config(enum gpio_interrupts intr) { return &gpio_int_data[intr]; } -- cgit v1.2.1 From 1eb973efe763dda5e76ab0574b31319e368ed20c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:26 -0600 Subject: baseboard/cherry/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I41bb3ea958013fa4f4405b57f200b2d490e64f3e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727867 Reviewed-by: Jeremy Bettis --- baseboard/cherry/baseboard.c | 114 +++++++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 59 deletions(-) diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c index 83c169c636..223358d377 100644 --- a/baseboard/cherry/baseboard.c +++ b/baseboard/cherry/baseboard.c @@ -52,8 +52,8 @@ static void xhci_init_done_interrupt(enum gpio_signal signal); #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Wake-up pins for hibernate */ enum gpio_signal hibernate_wake_pins[] = { @@ -76,10 +76,10 @@ static void baseboard_charger_init(void) { /* b/198707662#comment9 */ int reg = (4096 / ISL9238_INPUT_VOLTAGE_REF_STEP) - << ISL9238_INPUT_VOLTAGE_REF_SHIFT; + << ISL9238_INPUT_VOLTAGE_REF_SHIFT; i2c_write16(I2C_PORT_CHARGER, ISL923X_ADDR_FLAGS, - ISL9238_REG_INPUT_VOLTAGE, reg); + ISL9238_REG_INPUT_VOLTAGE, reg); } DECLARE_HOOK(HOOK_INIT, baseboard_charger_init, HOOK_PRIO_DEFAULT + 2); @@ -113,14 +113,14 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal) /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0}, - {"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1}, - {"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2}, + { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 }, + { "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, + { "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, /* AMON/BMON gain = 17.97 */ - {"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH3}, - {"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6}, - {"TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7}, + { "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH3 }, + { "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 }, + { "TEMP_SENSOR_CHG", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH7 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -210,7 +210,8 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal) { enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; for (int i = 0; i < USB_PORT_COUNT; i++) usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); @@ -246,34 +247,26 @@ __maybe_unused void xhci_init_done_interrupt(enum gpio_signal signal) /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 1000, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 1000, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -315,26 +308,30 @@ __override int board_rt1718s_init(int port) /* gpio 1/2 output high when receiving frx signal */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL, - RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); + RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, - RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); + RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); /* Turn on SBU switch */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | - RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | - RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, - 0xFF)); + RETURN_ERROR( + rt1718s_update_bits8(port, RT1718S_RT2_SBU_CTRL_01, + RT1718S_RT2_SBU_CTRL_01_SBU_VIEN | + RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN | + RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN, + 0xFF)); /* Trigger GPIO 1/2 change when FRS signal received */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_FRS_CTRL3, + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1)); /* Set FRS signal detect time to 46.875us */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1, - RT1718S_FRS_CTRL1_FRSWAPRX_MASK, - 0xFF)); + RT1718S_FRS_CTRL1_FRSWAPRX_MASK, + 0xFF)); return EC_SUCCESS; } @@ -371,8 +368,8 @@ void board_reset_pd_mcu(void) /* C1: Add code if TCPC chips need a reset */ } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); @@ -452,13 +449,12 @@ int ppc_get_alert_status(int port) return 0; } /* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) +int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages, + uint16_t *voltages_mv) { enum mt6360_regulator_id id = index; - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); + return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv); } int board_regulator_enable(uint32_t index, uint8_t enable) @@ -508,7 +504,7 @@ __override int board_rt1718s_set_frs_enable(int port, int enable) * FRS path. */ rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS, - enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); + enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); return EC_SUCCESS; } -- cgit v1.2.1 From cc533989a8e24dddc67268ebaa01ecfd097697c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:12 -0600 Subject: test/fake_usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I393b5d1c576c1aa7344ea3581c673008a051fce8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730499 Reviewed-by: Jeremy Bettis --- test/fake_usbc.c | 68 ++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 42 insertions(+), 26 deletions(-) diff --git a/test/fake_usbc.c b/test/fake_usbc.c index 2cabb2dee0..1e98e78426 100644 --- a/test/fake_usbc.c +++ b/test/fake_usbc.c @@ -15,17 +15,20 @@ __overridable int pd_is_vbus_present(int port) } __overridable void pd_request_data_swap(int port) -{} +{ +} __overridable void pd_request_power_swap(int port) -{} +{ +} void pd_request_vconn_swap_off(int port) -{} +{ +} void pd_request_vconn_swap_on(int port) -{} - +{ +} static enum pd_data_role data_role; __overridable enum pd_data_role pd_get_data_role(int port) @@ -68,10 +71,12 @@ int tc_check_vconn_swap(int port) } void tc_ctvpd_detected(int port) -{} +{ +} void tc_disc_ident_complete(int port) -{} +{ +} static int attached_snk; int tc_is_attached_snk(int port) @@ -91,28 +96,36 @@ int tc_is_vconn_src(int port) } void tc_hard_reset_request(int port) -{} +{ +} void tc_hard_reset_complete(int port) -{} +{ +} void tc_partner_dr_data(int port, int en) -{} +{ +} void tc_partner_dr_power(int port, int en) -{} +{ +} void tc_partner_unconstrainedpower(int port, int en) -{} +{ +} void tc_partner_usb_comm(int port, int en) -{} +{ +} void tc_pd_connection(int port, int en) -{} +{ +} void tc_pr_swap_complete(int port, bool success) -{} +{ +} void tc_prs_snk_src_assert_rp(int port) { @@ -127,16 +140,20 @@ void tc_prs_src_snk_assert_rd(int port) } void tc_src_power_off(int port) -{} +{ +} void tc_set_timeout(int port, uint64_t timeout) -{} +{ +} __overridable void tc_start_error_recovery(int port) -{} +{ +} __overridable void tc_snk_power_off(int port) -{} +{ +} __overridable void pe_invalidate_explicit_contract(int port) { @@ -148,7 +165,7 @@ __overridable enum pd_dual_role_states pd_get_dual_role(int port) } __overridable void pd_dev_get_rw_hash(int port, uint16_t *dev_id, - uint8_t *rw_hash, uint32_t *current_image) + uint8_t *rw_hash, uint32_t *current_image) { } @@ -185,7 +202,7 @@ enum idh_ptype get_usb_pd_mux_cable_type(int port) return IDH_PTYPE_UNDEF; } -const uint32_t * const pd_get_src_caps(int port) +const uint32_t *const pd_get_src_caps(int port) { return NULL; } @@ -200,8 +217,7 @@ uint8_t pd_get_src_cap_cnt(int port) } #endif -#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && \ - !defined(CONFIG_USB_CTVPD) +#if !defined(CONFIG_USB_DRP_ACC_TRYSRC) && !defined(CONFIG_USB_CTVPD) int pd_is_connected(int port) { return true; @@ -271,12 +287,12 @@ void dpm_mode_exit_complete(int port) } void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { } void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, - uint8_t vdm_cmd) + uint8_t vdm_cmd) { } @@ -325,7 +341,7 @@ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len) static enum tcpc_rp_value lcl_rp; __overridable void typec_select_src_current_limit_rp(int port, - enum tcpc_rp_value rp) + enum tcpc_rp_value rp) { lcl_rp = rp; } -- cgit v1.2.1 From 98ba4365a28607a1e5eb55497bcfe67d7f6c1729 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:54 -0600 Subject: board/prism/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I472ad18218378e6f4d3832b15448eea462ea6367 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727765 Reviewed-by: Jeremy Bettis --- board/prism/board.c | 297 +++++++++++++++++++++++++--------------------------- 1 file changed, 145 insertions(+), 152 deletions(-) diff --git a/board/prism/board.c b/board/prism/board.c index dc5c042db1..752b614fc2 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -37,20 +37,20 @@ #define CROS_EC_SECTION "RO" #endif -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Prism"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), - [USB_STR_HOSTCMD_NAME] = USB_STRING_DESC("Host command"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Prism"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_HOSTCMD_NAME] = USB_STRING_DESC("Host command"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -61,10 +61,9 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); #ifdef SECTION_IS_RW const struct spi_device_t spi_devices[] = { - [SPI_RGB0_DEVICE_ID] = { - CONFIG_SPI_RGB_PORT, - 2, /* 2: Fpclk/8 = 48Mhz/8 = 6Mhz */ - GPIO_SPI1_CS1_L }, + [SPI_RGB0_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, /* 2: Fpclk/8 = 48Mhz/8 + = 6Mhz */ + GPIO_SPI1_CS1_L }, [SPI_RGB1_DEVICE_ID] = { CONFIG_SPI_RGB_PORT, 2, GPIO_SPI1_CS2_L }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); @@ -103,143 +102,138 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, /* 0: (null) */ - LED( 0, 1), DELM, /* 1: ~ ` */ - LED( 1, 1), LED( 1, 2), DELM, /* 2: ! 1 */ - LED( 2, 1), LED( 2, 2), DELM, /* 3: @ 2 */ - LED( 3, 1), LED( 3, 2), DELM, /* 4: # 3 */ - LED( 4, 1), LED( 4, 2), DELM, /* 5: $ 4 */ - LED( 5, 1), LED( 5, 2), DELM, /* 6: % 5 */ - LED( 6, 1), LED( 6, 2), DELM, /* 7: ^ 6 */ - LED( 7, 1), LED( 7, 2), DELM, /* 8: & 7 */ - LED( 8, 1), LED( 8, 2), DELM, /* 9: * 8 */ - LED( 9, 1), LED( 9, 2), DELM, /* 10: ( 9 */ - LED(10, 1), LED(10, 2), DELM, /* 11: ) 0 */ - LED(11, 1), LED(11, 2), DELM, /* 12: _ - */ - LED(12, 1), LED(12, 2), DELM, /* 13: + = */ - DELM, /* 14: (null) */ - LED(13, 1), LED(13, 2), DELM, /* 15: backspace */ - LED( 0, 3), DELM, /* 16: tab */ - LED( 1, 3), DELM, /* 17: q */ - LED( 2, 3), DELM, /* 18: w */ - LED( 3, 3), DELM, /* 19: e */ - LED( 4, 3), DELM, /* 20: r */ - LED( 5, 3), DELM, /* 21: t */ - LED( 6, 3), DELM, /* 22: y */ - LED( 7, 3), DELM, /* 23: u */ - LED( 8, 3), DELM, /* 24: i */ - LED( 9, 3), DELM, /* 25: o */ - LED(10, 3), DELM, /* 26: p */ - LED(11, 3), LED(12, 3), DELM, /* 27: [ { */ - LED(13, 3), LED(14, 3), DELM, /* 28: ] } */ - LED(15, 3), LED(16, 3), DELM, /* 29: \ | */ - LED( 0, 4), LED( 1, 4), DELM, /* 30: caps lock */ - LED( 2, 4), DELM, /* 31: a */ - LED( 3, 4), DELM, /* 32: s */ - LED( 4, 4), DELM, /* 33: d */ - LED( 5, 4), DELM, /* 34: f */ - LED( 6, 4), DELM, /* 35: g */ - LED( 7, 4), DELM, /* 36: h */ - LED( 8, 4), DELM, /* 37: j */ - LED( 9, 4), DELM, /* 38: k */ - LED(10, 4), DELM, /* 39: l */ - LED(11, 4), LED(12, 4), DELM, /* 40: ; : */ - LED(13, 4), LED(14, 4), DELM, /* 41: " ' */ - DELM, /* 42: (null) */ - LED(15, 4), LED(16, 4), DELM, /* 43: enter */ - LED( 0, 5), LED( 1, 5), - LED( 2, 5), DELM, /* 44: L-shift */ - DELM, /* 45: (null) */ - LED( 3, 5), DELM, /* 46: z */ - LED( 4, 5), DELM, /* 47: x */ - LED( 5, 5), DELM, /* 48: c */ - LED( 6, 5), DELM, /* 49: v */ - LED( 7, 5), DELM, /* 50: b */ - LED( 8, 5), DELM, /* 51: n */ - LED( 9, 5), DELM, /* 52: m */ - LED(10, 5), LED(11, 5), DELM, /* 53: , < */ - LED(12, 5), LED(13, 5), DELM, /* 54: . > */ - LED(14, 5), LED(15, 5), DELM, /* 55: / ? */ - DELM, /* 56: (null) */ - LED(16, 5), LED(17, 5), - LED(18, 5), DELM, /* 57: R-shift */ - LED(17, 4), LED(18, 4), - LED(19, 4), DELM, /* 58: L-ctrl */ - LED(15, 0), DELM, /* 59: power */ - LED(17, 2), LED(18, 2), - LED(19, 2), DELM, /* 60: L-alt */ - LED(17, 3), LED(18, 3), - LED(19, 3), LED(20, 3), - LED(21, 3), DELM, /* 61: space */ - LED(20, 2), DELM, /* 62: R-alt */ - DELM, /* 63: (null) */ - LED(21, 2), DELM, /* 64: R-ctrl */ - DELM, /* 65: (null) */ - DELM, /* 66: (null) */ - DELM, /* 67: (null) */ - DELM, /* 68: (null) */ - DELM, /* 69: (null) */ - DELM, /* 70: (null) */ - DELM, /* 71: (null) */ - DELM, /* 72: (null) */ - DELM, /* 73: (null) */ - DELM, /* 74: (null) */ - DELM, /* 75: (null) */ - DELM, /* 76: (null) */ - DELM, /* 77: (null) */ - DELM, /* 78: (null) */ - LED(19, 5), DELM, /* 79: left */ - DELM, /* 80: (null) */ - DELM, /* 81: (null) */ - DELM, /* 82: (null) */ - LED(20, 4), DELM, /* 83: up */ - LED(20, 5), DELM, /* 84: down */ - DELM, /* 85: (null) */ - DELM, /* 86: (null) */ - DELM, /* 87: (null) */ - DELM, /* 88: (null) */ - LED(21, 5), DELM, /* 89: right */ - DELM, /* 90: (null) */ - DELM, /* 91: (null) */ - DELM, /* 92: (null) */ - DELM, /* 93: (null) */ - DELM, /* 94: (null) */ - DELM, /* 95: (null) */ - DELM, /* 96: (null) */ - DELM, /* 97: (null) */ - DELM, /* 98: (null) */ - DELM, /* 99: (null) */ - DELM, /* 100: (null) */ - DELM, /* 101: (null) */ - DELM, /* 102: (null) */ - DELM, /* 103: (null) */ - DELM, /* 104: (null) */ - DELM, /* 105: (null) */ - DELM, /* 106: (null) */ - DELM, /* 107: (null) */ - DELM, /* 108: (null) */ - DELM, /* 109: (null) */ - LED( 0, 0), DELM, /* 110: esc */ - LED( 1, 0), DELM, /* T1: previous page */ - LED( 2, 0), DELM, /* T2: refresh */ - LED( 3, 0), DELM, /* T3: full screen */ - LED( 4, 0), DELM, /* T4: windows */ - LED( 5, 0), DELM, /* T5: screenshot */ - LED( 6, 0), DELM, /* T6: brightness down */ - LED( 7, 0), DELM, /* T7: brightness up */ - LED( 8, 0), DELM, /* T8: KB backlight off */ - LED( 9, 0), DELM, /* T9: play/pause */ - LED(10, 0), DELM, /* T10: mute microphone */ - LED(11, 0), DELM, /* T11: mute speakers */ - LED(12, 0), DELM, /* T12: volume down */ - LED(13, 0), DELM, /* T13: volume up */ - DELM, /* T14: (null) */ - DELM, /* T15: (null) */ - DELM, /* 126: (null) */ - DELM, /* 127: (null) */ + DELM, /* 0: (null) */ + LED(0, 1), DELM, /* 1: ~ ` */ + LED(1, 1), LED(1, 2), DELM, /* 2: ! 1 */ + LED(2, 1), LED(2, 2), DELM, /* 3: @ 2 */ + LED(3, 1), LED(3, 2), DELM, /* 4: # 3 */ + LED(4, 1), LED(4, 2), DELM, /* 5: $ 4 */ + LED(5, 1), LED(5, 2), DELM, /* 6: % 5 */ + LED(6, 1), LED(6, 2), DELM, /* 7: ^ 6 */ + LED(7, 1), LED(7, 2), DELM, /* 8: & 7 */ + LED(8, 1), LED(8, 2), DELM, /* 9: * 8 */ + LED(9, 1), LED(9, 2), DELM, /* 10: ( 9 */ + LED(10, 1), LED(10, 2), DELM, /* 11: ) 0 */ + LED(11, 1), LED(11, 2), DELM, /* 12: _ - */ + LED(12, 1), LED(12, 2), DELM, /* 13: + = */ + DELM, /* 14: (null) */ + LED(13, 1), LED(13, 2), DELM, /* 15: backspace */ + LED(0, 3), DELM, /* 16: tab */ + LED(1, 3), DELM, /* 17: q */ + LED(2, 3), DELM, /* 18: w */ + LED(3, 3), DELM, /* 19: e */ + LED(4, 3), DELM, /* 20: r */ + LED(5, 3), DELM, /* 21: t */ + LED(6, 3), DELM, /* 22: y */ + LED(7, 3), DELM, /* 23: u */ + LED(8, 3), DELM, /* 24: i */ + LED(9, 3), DELM, /* 25: o */ + LED(10, 3), DELM, /* 26: p */ + LED(11, 3), LED(12, 3), DELM, /* 27: [ { */ + LED(13, 3), LED(14, 3), DELM, /* 28: ] } */ + LED(15, 3), LED(16, 3), DELM, /* 29: \ | */ + LED(0, 4), LED(1, 4), DELM, /* 30: caps lock */ + LED(2, 4), DELM, /* 31: a */ + LED(3, 4), DELM, /* 32: s */ + LED(4, 4), DELM, /* 33: d */ + LED(5, 4), DELM, /* 34: f */ + LED(6, 4), DELM, /* 35: g */ + LED(7, 4), DELM, /* 36: h */ + LED(8, 4), DELM, /* 37: j */ + LED(9, 4), DELM, /* 38: k */ + LED(10, 4), DELM, /* 39: l */ + LED(11, 4), LED(12, 4), DELM, /* 40: ; : */ + LED(13, 4), LED(14, 4), DELM, /* 41: " ' */ + DELM, /* 42: (null) */ + LED(15, 4), LED(16, 4), DELM, /* 43: enter */ + LED(0, 5), LED(1, 5), LED(2, 5), DELM, /* 44: L-shift */ + DELM, /* 45: (null) */ + LED(3, 5), DELM, /* 46: z */ + LED(4, 5), DELM, /* 47: x */ + LED(5, 5), DELM, /* 48: c */ + LED(6, 5), DELM, /* 49: v */ + LED(7, 5), DELM, /* 50: b */ + LED(8, 5), DELM, /* 51: n */ + LED(9, 5), DELM, /* 52: m */ + LED(10, 5), LED(11, 5), DELM, /* 53: , < */ + LED(12, 5), LED(13, 5), DELM, /* 54: . > */ + LED(14, 5), LED(15, 5), DELM, /* 55: / ? */ + DELM, /* 56: (null) */ + LED(16, 5), LED(17, 5), LED(18, 5), DELM, /* 57: R-shift */ + LED(17, 4), LED(18, 4), LED(19, 4), DELM, /* 58: L-ctrl */ + LED(15, 0), DELM, /* 59: power */ + LED(17, 2), LED(18, 2), LED(19, 2), DELM, /* 60: L-alt */ + LED(17, 3), LED(18, 3), LED(19, 3), LED(20, 3), + LED(21, 3), DELM, /* 61: space */ + LED(20, 2), DELM, /* 62: R-alt */ + DELM, /* 63: (null) */ + LED(21, 2), DELM, /* 64: R-ctrl */ + DELM, /* 65: (null) */ + DELM, /* 66: (null) */ + DELM, /* 67: (null) */ + DELM, /* 68: (null) */ + DELM, /* 69: (null) */ + DELM, /* 70: (null) */ + DELM, /* 71: (null) */ + DELM, /* 72: (null) */ + DELM, /* 73: (null) */ + DELM, /* 74: (null) */ + DELM, /* 75: (null) */ + DELM, /* 76: (null) */ + DELM, /* 77: (null) */ + DELM, /* 78: (null) */ + LED(19, 5), DELM, /* 79: left */ + DELM, /* 80: (null) */ + DELM, /* 81: (null) */ + DELM, /* 82: (null) */ + LED(20, 4), DELM, /* 83: up */ + LED(20, 5), DELM, /* 84: down */ + DELM, /* 85: (null) */ + DELM, /* 86: (null) */ + DELM, /* 87: (null) */ + DELM, /* 88: (null) */ + LED(21, 5), DELM, /* 89: right */ + DELM, /* 90: (null) */ + DELM, /* 91: (null) */ + DELM, /* 92: (null) */ + DELM, /* 93: (null) */ + DELM, /* 94: (null) */ + DELM, /* 95: (null) */ + DELM, /* 96: (null) */ + DELM, /* 97: (null) */ + DELM, /* 98: (null) */ + DELM, /* 99: (null) */ + DELM, /* 100: (null) */ + DELM, /* 101: (null) */ + DELM, /* 102: (null) */ + DELM, /* 103: (null) */ + DELM, /* 104: (null) */ + DELM, /* 105: (null) */ + DELM, /* 106: (null) */ + DELM, /* 107: (null) */ + DELM, /* 108: (null) */ + DELM, /* 109: (null) */ + LED(0, 0), DELM, /* 110: esc */ + LED(1, 0), DELM, /* T1: previous page */ + LED(2, 0), DELM, /* T2: refresh */ + LED(3, 0), DELM, /* T3: full screen */ + LED(4, 0), DELM, /* T4: windows */ + LED(5, 0), DELM, /* T5: screenshot */ + LED(6, 0), DELM, /* T6: brightness down */ + LED(7, 0), DELM, /* T7: brightness up */ + LED(8, 0), DELM, /* T8: KB backlight off */ + LED(9, 0), DELM, /* T9: play/pause */ + LED(10, 0), DELM, /* T10: mute microphone */ + LED(11, 0), DELM, /* T11: mute speakers */ + LED(12, 0), DELM, /* T12: volume down */ + LED(13, 0), DELM, /* T13: volume up */ + DELM, /* T14: (null) */ + DELM, /* T15: (null) */ + DELM, /* 126: (null) */ + DELM, /* 127: (null) */ }; #undef LED #undef DELM @@ -322,7 +316,7 @@ int board_get_entropy(void *buffer, int len) uint8_t *data = buffer; uint32_t start; /* We expect one SOF per ms, so wait at most 2ms. */ - const uint32_t timeout = 2*MSEC; + const uint32_t timeout = 2 * MSEC; for (i = 0; i < len; i++) { STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC; @@ -353,8 +347,7 @@ __override const char *board_read_serial(void) int i; for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) { - snprintf(&str[pos], sizeof(str)-pos, - "%02x", id[i]); + snprintf(&str[pos], sizeof(str) - pos, "%02x", id[i]); } } -- cgit v1.2.1 From 6a9bb2a6ca1c125dd177dfcf2b4c4cbd5830df96 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:38 -0600 Subject: common/i2c_trace.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie311c38df6e602bd2a3003f1edc5869e8c9084ff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729638 Reviewed-by: Jeremy Bettis --- common/i2c_trace.c | 64 +++++++++++++++++++++--------------------------------- 1 file changed, 25 insertions(+), 39 deletions(-) diff --git a/common/i2c_trace.c b/common/i2c_trace.c index af65d85210..b39f0f5266 100644 --- a/common/i2c_trace.c +++ b/common/i2c_trace.c @@ -11,8 +11,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) struct i2c_trace_range { bool enabled; @@ -23,18 +23,17 @@ struct i2c_trace_range { static struct i2c_trace_range trace_entries[8]; -void i2c_trace_notify(int port, uint16_t addr_flags, - const uint8_t *out_data, size_t out_size, - const uint8_t *in_data, size_t in_size, int ret) +void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data, + size_t out_size, const uint8_t *in_data, size_t in_size, + int ret) { size_t i; uint16_t addr = I2C_STRIP_FLAGS(addr_flags); for (i = 0; i < ARRAY_SIZE(trace_entries); i++) - if (trace_entries[i].enabled - && trace_entries[i].port == port - && trace_entries[i].addr_lo <= addr - && trace_entries[i].addr_hi >= addr) + if (trace_entries[i].enabled && trace_entries[i].port == port && + trace_entries[i].addr_lo <= addr && + trace_entries[i].addr_hi >= addr) goto trace_enabled; return; @@ -66,19 +65,16 @@ static int command_i2ctrace_list(void) for (i = 0; i < ARRAY_SIZE(trace_entries); i++) { if (trace_entries[i].enabled) { i2c_port = get_i2c_port(trace_entries[i].port); - ccprintf("%-2zd %d %-8s 0x%X", - i, - trace_entries[i].port, + ccprintf("%-2zd %d %-8s 0x%X", i, trace_entries[i].port, #ifndef CONFIG_ZEPHYR i2c_port->name, #else "", #endif /* CONFIG_ZEPHYR */ trace_entries[i].addr_lo); - if (trace_entries[i].addr_hi - != trace_entries[i].addr_lo) - ccprintf(" to 0x%X", - trace_entries[i].addr_hi); + if (trace_entries[i].addr_hi != + trace_entries[i].addr_lo) + ccprintf(" to 0x%X", trace_entries[i].addr_hi); ccprintf("\n"); } } @@ -95,8 +91,7 @@ static int command_i2ctrace_disable(size_t id) return EC_SUCCESS; } -static int command_i2ctrace_enable(int port, int addr_lo, - int addr_hi) +static int command_i2ctrace_enable(int port, int addr_lo, int addr_hi) { struct i2c_trace_range *t; struct i2c_trace_range *new_entry = NULL; @@ -111,41 +106,34 @@ static int command_i2ctrace_enable(int port, int addr_lo, * Scan thru existing entries to see if there is one we can * extend instead of making a new entry */ - for (t = trace_entries; - t < trace_entries + ARRAY_SIZE(trace_entries); + for (t = trace_entries; t < trace_entries + ARRAY_SIZE(trace_entries); t++) { if (t->enabled && t->port == port) { /* Subset of existing range, do nothing */ - if (t->addr_lo <= addr_lo && - t->addr_hi >= addr_hi) + if (t->addr_lo <= addr_lo && t->addr_hi >= addr_hi) return EC_SUCCESS; /* Extends exising range on both directions, replace */ - if (t->addr_lo >= addr_lo && - t->addr_hi <= addr_hi) { + if (t->addr_lo >= addr_lo && t->addr_hi <= addr_hi) { t->enabled = 0; - return command_i2ctrace_enable( - port, addr_lo, addr_hi); + return command_i2ctrace_enable(port, addr_lo, + addr_hi); } /* Extends existing range below */ if (t->addr_lo - 1 <= addr_hi && t->addr_hi >= addr_hi) { t->enabled = 0; - return command_i2ctrace_enable( - port, - addr_lo, - t->addr_hi); + return command_i2ctrace_enable(port, addr_lo, + t->addr_hi); } /* Extends existing range above */ if (t->addr_lo <= addr_lo && t->addr_hi + 1 >= addr_lo) { t->enabled = 0; - return command_i2ctrace_enable( - port, - t->addr_lo, - addr_hi); + return command_i2ctrace_enable(port, t->addr_lo, + addr_hi); } } else if (!t->enabled && !new_entry) { new_entry = t; @@ -165,7 +153,6 @@ static int command_i2ctrace_enable(int port, int addr_lo, return EC_ERROR_MEMORY_ALLOCATION; } - static int command_i2ctrace(int argc, char **argv) { int id_or_port; @@ -204,14 +191,13 @@ static int command_i2ctrace(int argc, char **argv) return EC_ERROR_PARAM_COUNT; } - return command_i2ctrace_enable( - id_or_port, address_low, address_high); + return command_i2ctrace_enable(id_or_port, address_low, + address_high); } return EC_ERROR_PARAM1; } -DECLARE_CONSOLE_COMMAND(i2ctrace, - command_i2ctrace, +DECLARE_CONSOLE_COMMAND(i2ctrace, command_i2ctrace, "[list | disable | enable
| " "enable ]", "Trace I2C transactions"); -- cgit v1.2.1 From cf75f03cbb0c42a01e2c2e1ad2b3073b9bed7a91 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:40 -0600 Subject: extra/usb_console/usb_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idfbb6dea2a0516fd93b74a7b4bc038dfe84561ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730187 Reviewed-by: Jeremy Bettis --- extra/usb_console/usb_console.c | 55 +++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/extra/usb_console/usb_console.c b/extra/usb_console/usb_console.c index e4f8ea504f..d0136bf8a1 100644 --- a/extra/usb_console/usb_console.c +++ b/extra/usb_console/usb_console.c @@ -18,12 +18,12 @@ #include /* Options */ -static uint16_t vid = 0x18d1; /* Google */ -static uint16_t pid = 0x500f; /* discovery-stm32f072 */ -static uint8_t ep_num = 4; /* console endpoint */ +static uint16_t vid = 0x18d1; /* Google */ +static uint16_t pid = 0x500f; /* discovery-stm32f072 */ +static uint8_t ep_num = 4; /* console endpoint */ -static unsigned char rx_buf[1024]; /* much too big */ -static unsigned char tx_buf[1024]; /* much too big */ +static unsigned char rx_buf[1024]; /* much too big */ +static unsigned char tx_buf[1024]; /* much too big */ static const struct libusb_pollfd **usb_fds; static struct libusb_device_handle *devh; static struct libusb_transfer *rx_transfer; @@ -40,9 +40,8 @@ static void request_exit(const char *format, ...) do_exit++; } -#define BOO(msg, r) \ - request_exit("%s: line %d, %s\n", msg, __LINE__, \ - libusb_error_name(r)) +#define BOO(msg, r) \ + request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r)) static void sighandler(int signum) { @@ -105,8 +104,8 @@ static void send_tx(int len) { int r; - libusb_fill_bulk_transfer(tx_transfer, devh, - ep_num, tx_buf, len, cb_tx, NULL, 0); + libusb_fill_bulk_transfer(tx_transfer, devh, ep_num, tx_buf, len, cb_tx, + NULL, 0); r = libusb_submit_transfer(tx_transfer); if (r < 0) @@ -185,7 +184,7 @@ static int wait_for_stuff_to_happen(void) return -1; } - if (r == 0) /* timed out */ + if (r == 0) /* timed out */ return 0; /* Ignore stdin until we've finished sending the current line */ @@ -235,11 +234,9 @@ static char *progname; static char *short_opts = ":v:p:e:h"; static const struct option long_opts[] = { /* name hasarg *flag val */ - {"vid", 1, NULL, 'v'}, - {"pid", 1, NULL, 'p'}, - {"ep", 1, NULL, 'e'}, - {"help", 0, NULL, 'h'}, - {NULL, 0, NULL, 0}, + { "vid", 1, NULL, 'v' }, { "pid", 1, NULL, 'p' }, + { "ep", 1, NULL, 'e' }, { "help", 0, NULL, 'h' }, + { NULL, 0, NULL, 0 }, }; static void usage(int errs) @@ -254,7 +251,8 @@ static void usage(int errs) " -p,--pid HEXVAL Product ID (default %04x)\n" " -e,--ep NUM Endpoint (default %d)\n" " -h,--help Show this message\n" - "\n", progname, vid, pid, ep_num); + "\n", + progname, vid, pid, ep_num); exit(!!errs); } @@ -275,25 +273,25 @@ int main(int argc, char *argv[]) else progname = argv[0]; - opterr = 0; /* quiet, you */ + opterr = 0; /* quiet, you */ while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) { switch (i) { case 'p': - pid = (uint16_t) strtoull(optarg, &e, 16); + pid = (uint16_t)strtoull(optarg, &e, 16); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; } break; case 'v': - vid = (uint16_t) strtoull(optarg, &e, 16); + vid = (uint16_t)strtoull(optarg, &e, 16); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; } break; case 'e': - ep_num = (uint8_t) strtoull(optarg, &e, 0); + ep_num = (uint8_t)strtoull(optarg, &e, 0); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; @@ -302,7 +300,7 @@ int main(int argc, char *argv[]) case 'h': usage(errorcnt); break; - case 0: /* auto-handled option */ + case 0: /* auto-handled option */ break; case '?': if (optopt) @@ -368,9 +366,8 @@ int main(int argc, char *argv[]) printf("can't alloc rx_transfer"); goto out; } - libusb_fill_bulk_transfer(rx_transfer, devh, - 0x80 | ep_num, - rx_buf, sizeof(rx_buf), cb_rx, NULL, 0); + libusb_fill_bulk_transfer(rx_transfer, devh, 0x80 | ep_num, rx_buf, + sizeof(rx_buf), cb_rx, NULL, 0); tx_transfer = libusb_alloc_transfer(0); if (!tx_transfer) { @@ -396,14 +393,14 @@ int main(int argc, char *argv[]) while (!do_exit) { r = wait_for_stuff_to_happen(); switch (r) { - case 0: /* timed out */ + case 0: /* timed out */ /* printf("."); */ /* fflush(stdout); */ break; - case 1: /* stdin ready */ + case 1: /* stdin ready */ handle_stdin(); break; - case 2: /* libusb ready */ + case 2: /* libusb ready */ handle_libusb(); break; } @@ -440,7 +437,7 @@ int main(int argc, char *argv[]) printf("bye\n"); r = 0; - out: +out: if (tx_transfer) libusb_free_transfer(tx_transfer); if (rx_transfer) -- cgit v1.2.1 From f25011ada88086b793e8d3ca5eab2c6f30b1f4be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:07 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci_partner_src.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I18077580589955c4debe797bd70801df7d5fbabb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730731 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci_partner_src.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h index 00f592ae2f..15c6a22141 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_src.h @@ -95,10 +95,10 @@ enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data); * * @return Pointer to USB-C source extension */ -struct tcpci_partner_extension *tcpci_src_emul_init( - struct tcpci_src_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext); +struct tcpci_partner_extension * +tcpci_src_emul_init(struct tcpci_src_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext); /** * @brief Send capability message constructed from source device emulator PDOs @@ -134,9 +134,7 @@ int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data, */ int tcpci_src_emul_send_capability_msg_with_timer( struct tcpci_src_emul_data *data, - struct tcpci_partner_data *common_data, - uint64_t delay); - + struct tcpci_partner_data *common_data, uint64_t delay); /** * @brief Clear the alert received flag. -- cgit v1.2.1 From eeccc2c6501d444903d635f84673abe7bfabca67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:19 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e32.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2231b48c05f089360599bb8d8cf35dd63b2076be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730558 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e32.c | 43 ++++++++++++++-------------------------- 1 file changed, 15 insertions(+), 28 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e32.c b/test/usb_tcpmv2_td_pd_src3_e32.c index 9ade7b83c8..d80c17dd9b 100644 --- a/test/usb_tcpmv2_td_pd_src3_e32.c +++ b/test/usb_tcpmv2_td_pd_src3_e32.c @@ -10,18 +10,17 @@ #include "timer.h" #include "usb_tcpmv2_compliance.h" -#define PD_T_CHUNK_RECEIVER_REQUEST_MAX (15 * MSEC) -#define PD_T_CHUNK_SENDER_RSP_MAX (30 * MSEC) -#define PD_T_CHUNKING_NOT_SUPPORTED_MIN (40 * MSEC) -#define PD_T_CHUNKING_NOT_SUPPORTED_MAX (50 * MSEC) +#define PD_T_CHUNK_RECEIVER_REQUEST_MAX (15 * MSEC) +#define PD_T_CHUNK_SENDER_RSP_MAX (30 * MSEC) +#define PD_T_CHUNKING_NOT_SUPPORTED_MIN (40 * MSEC) +#define PD_T_CHUNKING_NOT_SUPPORTED_MAX (50 * MSEC) static void setup_chunk_msg(int chunk, char *data) { int i; int base_msg_byte = chunk * PD_MAX_EXTENDED_MSG_CHUNK_LEN; - *(uint16_t *)data = PD_EXT_HEADER(chunk, 0, - PD_MAX_EXTENDED_MSG_LEN); + *(uint16_t *)data = PD_EXT_HEADER(chunk, 0, PD_MAX_EXTENDED_MSG_LEN); for (i = 0; i < PD_MAX_EXTENDED_MSG_CHUNK_LEN; ++i) { int val = (i + base_msg_byte) % 256; @@ -85,12 +84,8 @@ int test_td_pd_src3_e32(void) possible[1].ctrl_msg = 0; possible[1].data_msg = 0x1F; - TEST_EQ(verify_tcpci_possible_tx(possible, - 2, - &found_index, - data, - sizeof(data), - &msg_len, + TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data, + sizeof(data), &msg_len, PD_T_CHUNKING_NOT_SUPPORTED_MAX), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); @@ -112,7 +107,7 @@ int test_td_pd_src3_e32(void) * tChunkReceiverRequest max (15ms), the test fails. */ TEST_ASSERT((get_time().val - start_time) <= - PD_T_CHUNK_RECEIVER_REQUEST_MAX); + PD_T_CHUNK_RECEIVER_REQUEST_MAX); while (chunk < 4) { int next_chunk; @@ -130,12 +125,9 @@ int test_td_pd_src3_e32(void) setup_chunk_msg(chunk, data); partner_send_msg(TCPCI_MSG_SOP, 0x1F, 7, 1, (uint32_t *)data); - TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, - 0x1F, - data, - sizeof(data), - &msg_len, - PD_T_CHUNK_RECEIVER_REQUEST_MAX), + TEST_EQ(verify_tcpci_tx_with_data( + TCPCI_MSG_SOP, 0x1F, data, sizeof(data), + &msg_len, PD_T_CHUNK_RECEIVER_REQUEST_MAX), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); @@ -159,12 +151,9 @@ int test_td_pd_src3_e32(void) * i) If a message is not received within tChunkReceiverRequest max, * the test fails. */ - TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, - 0x1F, - data, - sizeof(data), - &msg_len, - PD_T_CHUNK_RECEIVER_REQUEST_MAX), + TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, 0x1F, data, + sizeof(data), &msg_len, + PD_T_CHUNK_RECEIVER_REQUEST_MAX), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); @@ -207,9 +196,7 @@ int test_td_pd_src3_e32(void) * Number of Data Objects field */ header = *(uint32_t *)&data[1]; - TEST_EQ(msg_len - 3, - PD_HEADER_CNT(header) * 4, - "%d"); + TEST_EQ(msg_len - 3, PD_HEADER_CNT(header) * 4, "%d"); /* * 4. The last 2 bytes of the Data Object are 0 -- cgit v1.2.1 From 346e1ff9416fea0167ee94c8fe77134932c8c933 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:22 -0600 Subject: common/sha256.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I742c0ab00f1f4cea26345d8ee89e169eb501f343 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729748 Reviewed-by: Jeremy Bettis --- common/sha256.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 295 insertions(+), 1 deletion(-) mode change 120000 => 100644 common/sha256.c diff --git a/common/sha256.c b/common/sha256.c deleted file mode 120000 index 8c0778c3e6..0000000000 --- a/common/sha256.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/sha2//sha256.c \ No newline at end of file diff --git a/common/sha256.c b/common/sha256.c new file mode 100644 index 0000000000..33ed38c5ec --- /dev/null +++ b/common/sha256.c @@ -0,0 +1,295 @@ +/* SHA-256 and SHA-512 implementation based on code by Oliver Gay + * under a BSD-style license. See below. + */ + +/* + * FIPS 180-2 SHA-224/256/384/512 implementation + * Last update: 02/02/2007 + * Issue date: 04/30/2005 + * + * Copyright (C) 2005, 2007 Olivier Gay + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the project nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "sha256.h" +#include "util.h" + +#define SHFR(x, n) (x >> n) +#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n))) +#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) +#define CH(x, y, z) ((x & y) ^ (~x & z)) +#define MAJ(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +#define SHA256_F1(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22)) +#define SHA256_F2(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25)) +#define SHA256_F3(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHFR(x, 3)) +#define SHA256_F4(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHFR(x, 10)) + +#define UNPACK32(x, str) \ + { \ + *((str) + 3) = (uint8_t)((x)); \ + *((str) + 2) = (uint8_t)((x) >> 8); \ + *((str) + 1) = (uint8_t)((x) >> 16); \ + *((str) + 0) = (uint8_t)((x) >> 24); \ + } + +#define PACK32(str, x) \ + { \ + *(x) = ((uint32_t) * ((str) + 3)) | \ + ((uint32_t) * ((str) + 2) << 8) | \ + ((uint32_t) * ((str) + 1) << 16) | \ + ((uint32_t) * ((str) + 0) << 24); \ + } + +/* Macros used for loops unrolling */ + +#define SHA256_SCR(i) \ + { \ + w[i] = SHA256_F4(w[i - 2]) + w[i - 7] + SHA256_F3(w[i - 15]) + \ + w[i - 16]; \ + } + +#define SHA256_EXP(a, b, c, d, e, f, g, h, j) \ + { \ + t1 = wv[h] + SHA256_F2(wv[e]) + CH(wv[e], wv[f], wv[g]) + \ + sha256_k[j] + w[j]; \ + t2 = SHA256_F1(wv[a]) + MAJ(wv[a], wv[b], wv[c]); \ + wv[d] += t1; \ + wv[h] = t1 + t2; \ + } + +static const uint32_t sha256_h0[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372, + 0xa54ff53a, 0x510e527f, 0x9b05688c, + 0x1f83d9ab, 0x5be0cd19 }; + +static const uint32_t sha256_k[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, + 0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786, + 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, + 0x06ca6351, 0x14292967, 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, 0xa2bfe8a1, 0xa81a664b, + 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, + 0x5b9cca4f, 0x682e6ff3, 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +}; + +void SHA256_init(struct sha256_ctx *ctx) +{ + int i; + + for (i = 0; i < 8; i++) + ctx->h[i] = sha256_h0[i]; + + ctx->len = 0; + ctx->tot_len = 0; +} + +static void SHA256_transform(struct sha256_ctx *ctx, const uint8_t *message, + unsigned int block_nb) +{ + /* Note: this function requires a considerable amount of stack */ + uint32_t w[64]; + uint32_t wv[8]; + uint32_t t1, t2; + const unsigned char *sub_block; + int i, j; + + for (i = 0; i < (int)block_nb; i++) { + sub_block = message + (i << 6); + + for (j = 0; j < 16; j++) + PACK32(&sub_block[j << 2], &w[j]); + +#ifdef CONFIG_SHA256_UNROLLED + for (j = 16; j < 64; j += 8) { + SHA256_SCR(j); + SHA256_SCR(j + 1); + SHA256_SCR(j + 2); + SHA256_SCR(j + 3); + SHA256_SCR(j + 4); + SHA256_SCR(j + 5); + SHA256_SCR(j + 6); + SHA256_SCR(j + 7); + } +#else + for (j = 16; j < 64; j++) + SHA256_SCR(j); +#endif + + for (j = 0; j < 8; j++) + wv[j] = ctx->h[j]; + +#ifdef CONFIG_SHA256_UNROLLED + for (j = 0; j < 64; j += 8) { + SHA256_EXP(0, 1, 2, 3, 4, 5, 6, 7, j); + SHA256_EXP(7, 0, 1, 2, 3, 4, 5, 6, j + 1); + SHA256_EXP(6, 7, 0, 1, 2, 3, 4, 5, j + 2); + SHA256_EXP(5, 6, 7, 0, 1, 2, 3, 4, j + 3); + SHA256_EXP(4, 5, 6, 7, 0, 1, 2, 3, j + 4); + SHA256_EXP(3, 4, 5, 6, 7, 0, 1, 2, j + 5); + SHA256_EXP(2, 3, 4, 5, 6, 7, 0, 1, j + 6); + SHA256_EXP(1, 2, 3, 4, 5, 6, 7, 0, j + 7); + } +#else + for (j = 0; j < 64; j++) { + t1 = wv[7] + SHA256_F2(wv[4]) + + CH(wv[4], wv[5], wv[6]) + sha256_k[j] + w[j]; + t2 = SHA256_F1(wv[0]) + MAJ(wv[0], wv[1], wv[2]); + wv[7] = wv[6]; + wv[6] = wv[5]; + wv[5] = wv[4]; + wv[4] = wv[3] + t1; + wv[3] = wv[2]; + wv[2] = wv[1]; + wv[1] = wv[0]; + wv[0] = t1 + t2; + } +#endif + + for (j = 0; j < 8; j++) + ctx->h[j] += wv[j]; + } +} + +void SHA256_update(struct sha256_ctx *ctx, const uint8_t *data, uint32_t len) +{ + unsigned int block_nb; + unsigned int new_len, rem_len, tmp_len; + const uint8_t *shifted_data; + + tmp_len = SHA256_BLOCK_SIZE - ctx->len; + rem_len = len < tmp_len ? len : tmp_len; + + memcpy(&ctx->block[ctx->len], data, rem_len); + + if (ctx->len + len < SHA256_BLOCK_SIZE) { + ctx->len += len; + return; + } + + new_len = len - rem_len; + block_nb = new_len / SHA256_BLOCK_SIZE; + + shifted_data = data + rem_len; + + SHA256_transform(ctx, ctx->block, 1); + SHA256_transform(ctx, shifted_data, block_nb); + + rem_len = new_len % SHA256_BLOCK_SIZE; + + memcpy(ctx->block, &shifted_data[block_nb << 6], rem_len); + + ctx->len = rem_len; + ctx->tot_len += (block_nb + 1) << 6; +} + +/* + * Specialized SHA256_init + SHA256_update that takes the first data block of + * size SHA256_BLOCK_SIZE as input. + */ +static void SHA256_init_1b(struct sha256_ctx *ctx, const uint8_t *data) +{ + int i; + + for (i = 0; i < 8; i++) + ctx->h[i] = sha256_h0[i]; + + SHA256_transform(ctx, data, 1); + + ctx->len = 0; + ctx->tot_len = SHA256_BLOCK_SIZE; +} + +uint8_t *SHA256_final(struct sha256_ctx *ctx) +{ + unsigned int block_nb; + unsigned int pm_len; + unsigned int len_b; + int i; + + block_nb = (1 + + ((SHA256_BLOCK_SIZE - 9) < (ctx->len % SHA256_BLOCK_SIZE))); + + len_b = (ctx->tot_len + ctx->len) << 3; + pm_len = block_nb << 6; + + memset(ctx->block + ctx->len, 0, pm_len - ctx->len); + ctx->block[ctx->len] = 0x80; + UNPACK32(len_b, ctx->block + pm_len - 4); + + SHA256_transform(ctx, ctx->block, block_nb); + + for (i = 0; i < 8; i++) + UNPACK32(ctx->h[i], &ctx->buf[i << 2]); + + return ctx->buf; +} + +static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key, + const int key_len, const uint8_t *data, + const int data_len) +{ + struct sha256_ctx ctx; + uint8_t *key_pad = ctx.block; + uint8_t *tmp; + int i; + + /* key_pad = key (zero-padded) ^ mask */ + memset(key_pad, mask, SHA256_BLOCK_SIZE); + for (i = 0; i < key_len; i++) + key_pad[i] ^= key[i]; + + /* tmp = hash(key_pad || message) */ + SHA256_init_1b(&ctx, key_pad); + SHA256_update(&ctx, data, data_len); + tmp = SHA256_final(&ctx); + memcpy(output, tmp, SHA256_DIGEST_SIZE); +} + +void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, + const uint8_t *message, const int message_len) +{ + /* This code does not support key_len > block_size. */ + ASSERT(key_len <= SHA256_BLOCK_SIZE); + + /* + * i_key_pad = key (zero-padded) ^ 0x36 + * output = hash(i_key_pad || message) + * (Use output as temporary buffer) + */ + hmac_SHA256_step(output, 0x36, key, key_len, message, message_len); + + /* + * o_key_pad = key (zero-padded) ^ 0x5c + * output = hash(o_key_pad || output) + */ + hmac_SHA256_step(output, 0x5c, key, key_len, output, + SHA256_DIGEST_SIZE); +} -- cgit v1.2.1 From 68526df5ca365ba271bcc029bba44f6bc440347d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:01 -0600 Subject: board/servo_v4p1/ioexpanders.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I505c0d381404680d8561d14d0e5ad3f83706a0df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728932 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/ioexpanders.c | 47 +++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/board/servo_v4p1/ioexpanders.c b/board/servo_v4p1/ioexpanders.c index 46dcbcc167..3c871f45e5 100644 --- a/board/servo_v4p1/ioexpanders.c +++ b/board/servo_v4p1/ioexpanders.c @@ -9,22 +9,22 @@ #include "ioexpander.h" #include "ioexpanders.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /****************************************************************************** * Initialize IOExpanders. */ -#define PCAL6524HE_PORT TCA6424A_PORT -#define PCAL6524HE_ADDR TCA6424A_ADDR -#define PCAL6524HE_DEVICE_ID_ADDR 0x7c -#define PCAL6524HE_DEVICE_ID_REG 0x46 -#define PCAL6524HE_DEVICE_ID0 0 -#define PCAL6524HE_DEVICE_ID1 0x08 -#define PCAL6524HE_DEVICE_ID2 0x30 -#define PCAL6524HE_INT_MASK_REG_PORT1 0x55 -#define PCAL6524HE_INT_MASK_REG_PORT2 0x56 +#define PCAL6524HE_PORT TCA6424A_PORT +#define PCAL6524HE_ADDR TCA6424A_ADDR +#define PCAL6524HE_DEVICE_ID_ADDR 0x7c +#define PCAL6524HE_DEVICE_ID_REG 0x46 +#define PCAL6524HE_DEVICE_ID0 0 +#define PCAL6524HE_DEVICE_ID1 0x08 +#define PCAL6524HE_DEVICE_ID2 0x30 +#define PCAL6524HE_INT_MASK_REG_PORT1 0x55 +#define PCAL6524HE_INT_MASK_REG_PORT2 0x56 static enum servo_board_id board_id_val = BOARD_ID_UNSET; @@ -51,16 +51,16 @@ int init_ioexpanders(void) /* Attempt to read the device id register of the PCAL6524HE device */ i2c_read_block(PCAL6524HE_PORT, PCAL6524HE_DEVICE_ID_ADDR, - PCAL6524HE_DEVICE_ID_REG, dat, 3); + PCAL6524HE_DEVICE_ID_REG, dat, 3); if (dat[2] == PCAL6524HE_DEVICE_ID2 && - dat[1] == PCAL6524HE_DEVICE_ID1 && - dat[0] == PCAL6524HE_DEVICE_ID0) { + dat[1] == PCAL6524HE_DEVICE_ID1 && + dat[0] == PCAL6524HE_DEVICE_ID0) { ccprintf("Detected PCAL6524HE\n"); i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR, - PCAL6524HE_INT_MASK_REG_PORT1, 0); + PCAL6524HE_INT_MASK_REG_PORT1, 0); i2c_write8(PCAL6524HE_PORT, PCAL6524HE_ADDR, - PCAL6524HE_INT_MASK_REG_PORT2, 0xbe); + PCAL6524HE_INT_MASK_REG_PORT2, 0xbe); } else { ccprintf("Detected TCA6424A\n"); } @@ -74,7 +74,7 @@ int init_ioexpanders(void) } if ((!!(irqs & HOST_CHRG_DET) != bc12_charger) && - (board_id_det() <= BOARD_ID_REV1)) { + (board_id_det() <= BOARD_ID_REV1)) { CPRINTF("BC1.2 charger %s\n", (irqs & HOST_CHRG_DET) ? "plugged" : "unplugged"); bc12_charger = !!(irqs & HOST_CHRG_DET); @@ -220,8 +220,7 @@ inline int board_id_det(void) /* Cache board ID at init */ if (ioex_get_port(IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->ioex, - IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, - &id)) + IOEX_GET_INFO(IOEX_BOARD_ID_DET0)->port, &id)) return id; /* Board ID consists of bits 5, 4, and 3 */ @@ -296,8 +295,7 @@ inline int read_faults(void) int val; ioex_get_port(IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->ioex, - IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, - &val); + IOEX_GET_INFO(IOEX_USERVO_FAULT_L)->port, &val); return val; } @@ -307,8 +305,7 @@ inline int read_irqs(void) int val; ioex_get_port(IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->ioex, - IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, - &val); + IOEX_GET_INFO(IOEX_SYS_PWR_IRQ_ODL)->port, &val); return val; } @@ -343,9 +340,7 @@ inline int board_id_det(void) int res; /* Cache board ID at init */ - res = i2c_read8(TCA6416A_PORT, - TCA6416A_ADDR, - BOARD_ID_DET_PORT, + res = i2c_read8(TCA6416A_PORT, TCA6416A_ADDR, BOARD_ID_DET_PORT, &id); if (res != EC_SUCCESS) return res; -- cgit v1.2.1 From d4532d134aefa1aeed4a9dc2775a871bf70f6579 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:41 -0600 Subject: chip/mt_scp/mt818x/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib06bbdf38d9f8cc7cd63493787fdc3a5b216f7ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729338 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/config_chip.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/mt_scp/mt818x/config_chip.h b/chip/mt_scp/mt818x/config_chip.h index e0d7158728..87103a3069 100644 --- a/chip/mt_scp/mt818x/config_chip.h +++ b/chip/mt_scp/mt818x/config_chip.h @@ -10,7 +10,7 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* Default to UART 2 (AP UART) for EC console */ #define CONFIG_UART_CONSOLE 2 @@ -26,7 +26,7 @@ #define MAX_EINT_PORT (MAX_NUM_EINT / 32) /* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_FW_INCLUDE_RO #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE 0 #define CONFIG_RW_MEM_OFF 0 -- cgit v1.2.1 From 56d1de31daab5120b8a75a1871ca28416bfb4e65 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:59 -0600 Subject: board/helios/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I75b80f2d4ca5155e19fb9547929b64cc4960ccc4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728300 Reviewed-by: Jeremy Bettis --- board/helios/board.c | 99 +++++++++++++++++++++++++--------------------------- 1 file changed, 47 insertions(+), 52 deletions(-) diff --git a/board/helios/board.c b/board/helios/board.c index b4d2fb1ef8..0f2a460848 100644 --- a/board/helios/board.c +++ b/board/helios/board.c @@ -44,8 +44,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void ppc_interrupt(enum gpio_signal signal) { @@ -134,16 +134,16 @@ static void board_gmr_tablet_switch_isr(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -215,22 +215,18 @@ enum base_accelgyro_type { static enum base_accelgyro_type base_accelgyro_config; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static const mat33_fp_t base_standard_ref_icm = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)}, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; struct motion_sensor_t icm426xx_base_accel = { @@ -379,8 +375,7 @@ static void board_detect_motionsense(void) ccprints("Base Accelgyro: BMI160"); } } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1); /******************************************************************************/ @@ -388,7 +383,7 @@ DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_INIT_I2C + 1); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -407,40 +402,40 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_4] = { - "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Temp3", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "Temp4", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Temp3", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "Temp4", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -448,8 +443,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ @@ -500,8 +495,8 @@ int board_tcpc_post_init(int port) /* Set MUX_DP_EQ to 3.6dB (0x98) */ rv = tcpc_write(port, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98); else if (port == USB_PD_PORT_TCPC_1) - rv = tcpc_write(port, - PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD, 0x80); + rv = tcpc_write(port, PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD, + 0x80); return rv; } -- cgit v1.2.1 From a31ed85673322d163b3b243fe3a112cb5c7c6921 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:19 -0600 Subject: core/cortex-m0/vecttable.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iacc813c593c019b5f7bf24038dfc43fcb4a61d2d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729835 Reviewed-by: Jeremy Bettis --- core/cortex-m0/vecttable.c | 81 ++++++++++++---------------------------------- 1 file changed, 20 insertions(+), 61 deletions(-) diff --git a/core/cortex-m0/vecttable.c b/core/cortex-m0/vecttable.c index 5c69f6d6c8..a0c3c1afa9 100644 --- a/core/cortex-m0/vecttable.c +++ b/core/cortex-m0/vecttable.c @@ -13,7 +13,7 @@ #include "config.h" #include "panic-internal.h" #include "task.h" -#endif /* __INIT */ +#endif /* __INIT */ typedef void (*func)(void); @@ -30,7 +30,7 @@ void __attribute__((naked)) default_handler(void) * restricting the relative placement of default_handler and * exception_panic. */ - asm volatile("bx %0\n" : : "r" (exception_panic)); + asm volatile("bx %0\n" : : "r"(exception_panic)); } #define table(x) x @@ -38,8 +38,8 @@ void __attribute__((naked)) default_handler(void) /* Note: the alias target must be defined in this translation unit */ #define weak_with_default __attribute__((used, weak, alias("default_handler"))) -#define vec(name) extern void weak_with_default name ## _handler(void); -#define irq(num) vec(irq_ ## num) +#define vec(name) extern void weak_with_default name##_handler(void); +#define irq(num) vec(irq_##num) #define item(name) extern void name(void); #define null @@ -77,69 +77,28 @@ extern void reset(void); #pragma clang diagnostic ignored "-Winitializer-overrides" #endif /* __clang__ */ -#define table(x) \ - const func vectors[] __attribute__((section(".text.vecttable"))) = { \ - x \ - [IRQ_UNUSED_OFFSET] = null \ - } +#define table(x) \ + const func vectors[] __attribute__(( \ + section(".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null } -#define vec(name) name ## _handler, -#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num) +#define vec(name) name##_handler, +#define irq(num) \ + [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \ + vec(irq_##num) #define item(name) name, #define null (void *)0, #endif /* PASS 2 */ -table( - item(stack_end) - item(reset) - vec(nmi) - vec(hard_fault) - vec(mpu_fault) - vec(bus_fault) - vec(usage_fault) - null - null - null - null - vec(svc) - vec(debug) - null - vec(pendsv) - vec(sys_tick) - irq(0) - irq(1) - irq(2) - irq(3) - irq(4) - irq(5) - irq(6) - irq(7) - irq(8) - irq(9) - irq(10) - irq(11) - irq(12) - irq(13) - irq(14) - irq(15) - irq(16) - irq(17) - irq(18) - irq(19) - irq(20) - irq(21) - irq(22) - irq(23) - irq(24) - irq(25) - irq(26) - irq(27) - irq(28) - irq(29) - irq(30) - irq(31) -); +table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec( + bus_fault) vec(usage_fault) null null null null vec(svc) vec(debug) + null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) + irq(5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) + irq(13) irq(14) irq(15) irq(16) irq(17) irq(18) + irq(19) irq(20) irq(21) irq(22) irq(23) + irq(24) irq(25) irq(26) irq(27) + irq(28) irq(29) irq(30) + irq(31)); #if PASS == 2 #ifdef __clang__ -- cgit v1.2.1 From cc7871598dbad7970c8b07a2fdee6dd065b24b87 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:34 -0600 Subject: board/copano/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c81488142b8bec2c6b3a2090c5bcca371e727b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728155 Reviewed-by: Jeremy Bettis --- board/copano/board.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/board/copano/board.c b/board/copano/board.c index efcde2c177..ce442cdaaa 100644 --- a/board/copano/board.c +++ b/board/copano/board.c @@ -42,7 +42,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -77,8 +77,8 @@ static const struct ec_response_keybd_config copano_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &copano_kb; } @@ -93,7 +93,6 @@ union volteer_cbi_fw_config fw_config_defaults = { static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -180,8 +179,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -208,8 +207,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -277,7 +276,6 @@ __override void board_cbi_init(void) /* Reassign USB_C0_RT_RST_ODL */ bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN; bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL; - } /******************************************************************************/ -- cgit v1.2.1 From 3fcd1f0f2884089ea46ff5bfd5a6fadf4c3e8786 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:29 -0600 Subject: board/waddledoo2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ffa89f678f4407698c9df3873a5e32d2df804a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729112 Reviewed-by: Jeremy Bettis --- board/waddledoo2/board.h | 52 ++++++++++++++++++++---------------------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/board/waddledoo2/board.h b/board/waddledoo2/board.h index e55539bc3e..e9627704de 100644 --- a/board/waddledoo2/board.h +++ b/board/waddledoo2/board.h @@ -24,9 +24,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -44,7 +45,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -81,16 +82,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -99,15 +100,15 @@ #define CONFIG_CMD_ACCEL_INFO #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -143,25 +144,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From afaaca49970252a00b9fc8ce5c5378d0ca9de009 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:02 -0600 Subject: board/madoo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f83af6881c652811e9f92414a30336ef2cddba1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728647 Reviewed-by: Jeremy Bettis --- board/madoo/board.c | 56 ++++++++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 33 deletions(-) diff --git a/board/madoo/board.c b/board/madoo/board.c index 2f465a81f0..359f1cca10 100644 --- a/board/madoo/board.c +++ b/board/madoo/board.c @@ -46,8 +46,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -87,7 +87,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -122,7 +121,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -237,8 +235,7 @@ __override void board_power_5v_enable(int enable) set_5v_gpio(!!enable); if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", enable ? "en" : "dis"); } int board_is_sourcing_vbus(int port) @@ -247,13 +244,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -317,8 +312,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -344,17 +339,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct accelgyro_saved_data_t g_bma253_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; @@ -434,20 +425,19 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -557,7 +547,7 @@ static void reconfigure_usbmux(void) usb_muxes[0].next_mux = &usbc0_retimer; } } -DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_usbmux, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { -- cgit v1.2.1 From 5259f5b1870946e9ad5e9ed2f0d18ba00ff7bf2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:46 -0600 Subject: zephyr/emul/tcpc/emul_tcpci_partner_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I05b0accc3116f5b08c0fcfdd54c5d88c455fbbe5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730704 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 115 +++++++++++++-------------- 1 file changed, 54 insertions(+), 61 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 5ef5d12729..21725f11f0 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -18,9 +18,9 @@ LOG_MODULE_REGISTER(tcpci_partner, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include "util.h" /** Length of PDO, RDO and BIST request object in SOP message in bytes */ -#define TCPCI_MSG_DO_LEN 4 +#define TCPCI_MSG_DO_LEN 4 /** Length of header in SOP message in bytes */ -#define TCPCI_MSG_HEADER_LEN 2 +#define TCPCI_MSG_HEADER_LEN 2 /** Length of extended header in bytes */ #define TCPCI_MSG_EXT_HEADER_LEN 2 @@ -136,10 +136,8 @@ tcpci_partner_alloc_extended_msg(size_t payload_size) * @return Pointer to message status */ static enum tcpci_emul_tx_status *tcpci_partner_log_msg( - struct tcpci_partner_data *data, - const struct tcpci_emul_msg *msg, - enum tcpci_partner_msg_sender sender, - enum tcpci_emul_tx_status status) + struct tcpci_partner_data *data, const struct tcpci_emul_msg *msg, + enum tcpci_partner_msg_sender sender, enum tcpci_emul_tx_status status) { struct tcpci_partner_log_msg *log_msg; int cnt; @@ -348,8 +346,8 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data, return ret; } - prev_msg = SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, prev_msg, - node); + prev_msg = + SYS_SLIST_PEEK_HEAD_CONTAINER(&data->to_send, prev_msg, node); /* Current message should be sent first */ if (prev_msg == NULL || prev_msg->time > msg->time) { sys_slist_prepend(&data->to_send, &msg->node); @@ -359,7 +357,8 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data, } SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->to_send, prev_msg, next_msg, - node) { + node) + { /* * If we reach tail or next message should be sent after new * message, insert new message to the list. @@ -378,8 +377,7 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data, } int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, - enum pd_ctrl_msg_type type, - uint64_t delay) + enum pd_ctrl_msg_type type, uint64_t delay) { struct tcpci_partner_msg *msg; @@ -401,9 +399,8 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, } int tcpci_partner_send_data_msg(struct tcpci_partner_data *data, - enum pd_data_msg_type type, - uint32_t *data_obj, int data_obj_num, - uint64_t delay) + enum pd_data_msg_type type, uint32_t *data_obj, + int data_obj_num, uint64_t delay) { struct tcpci_partner_msg *msg; int addr; @@ -566,9 +563,8 @@ void tcpci_partner_common_send_get_battery_capabilities( static void tcpci_partner_sender_response_timeout(struct k_work *work) { struct k_work_delayable *dwork = k_work_delayable_from_work(work); - struct tcpci_partner_data *data = - CONTAINER_OF(dwork, struct tcpci_partner_data, - sender_response_timeout); + struct tcpci_partner_data *data = CONTAINER_OF( + dwork, struct tcpci_partner_data, sender_response_timeout); if (k_mutex_lock(&data->transmit_mutex, K_NO_WAIT) != 0) { /* @@ -842,9 +838,9 @@ tcpi_partner_common_handle_accept(struct tcpci_partner_data *data) * @param TCPCI_PARTNER_COMMON_MSG_HARD_RESET Message was handled by sending * hard reset */ -static enum tcpci_partner_handler_res tcpci_partner_common_sop_msg_handler( - struct tcpci_partner_data *data, - const struct tcpci_emul_msg *tx_msg) +static enum tcpci_partner_handler_res +tcpci_partner_common_sop_msg_handler(struct tcpci_partner_data *data, + const struct tcpci_emul_msg *tx_msg) { struct tcpci_partner_extension *ext; uint16_t header; @@ -1045,8 +1041,10 @@ static char *tcpci_partner_sender_names[] = { * * @return Number of written bytes */ -static __printf_like(4, 5) int tcpci_partner_print_to_buf( - char *buf, const int buf_len, int start, const char *fmt, ...) +static __printf_like(4, 5) int tcpci_partner_print_to_buf(char *buf, + const int buf_len, + int start, + const char *fmt, ...) { va_list ap; int ret; @@ -1082,7 +1080,8 @@ void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data) chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in, "===PD messages log:\n"); - SYS_SLIST_FOR_EACH_CONTAINER(&data->msg_log, msg, node) { + SYS_SLIST_FOR_EACH_CONTAINER(&data->msg_log, msg, node) + { /* * If there is too many messages to keep them in local buffer, * accept possibility of lines interleaving on console and print @@ -1092,27 +1091,27 @@ void tcpci_partner_common_print_logged_msgs(struct tcpci_partner_data *data) LOG_PRINTK("%s", buf); chars_in = 0; } - chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in, - "\tAt %lld Msg SOP %d from %s (status 0x%x):\n", - msg->time, msg->sop, - tcpci_partner_sender_names[msg->sender], - msg->status); + chars_in += tcpci_partner_print_to_buf( + buf, buf_len, chars_in, + "\tAt %lld Msg SOP %d from %s (status 0x%x):\n", + msg->time, msg->sop, + tcpci_partner_sender_names[msg->sender], msg->status); header = sys_get_le16(msg->buf); + chars_in += tcpci_partner_print_to_buf( + buf, buf_len, chars_in, + "\t\text=%d;cnt=%d;id=%d;pr=%d;dr=%d;rev=%d;type=%d\n", + PD_HEADER_EXT(header), PD_HEADER_CNT(header), + PD_HEADER_ID(header), PD_HEADER_PROLE(header), + PD_HEADER_DROLE(header), PD_HEADER_REV(header), + PD_HEADER_TYPE(header)); chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in, - "\t\text=%d;cnt=%d;id=%d;pr=%d;dr=%d;rev=%d;type=%d\n", - PD_HEADER_EXT(header), PD_HEADER_CNT(header), - PD_HEADER_ID(header), PD_HEADER_PROLE(header), - PD_HEADER_DROLE(header), PD_HEADER_REV(header), - PD_HEADER_TYPE(header)); - chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in, - "\t\t"); + "\t\t"); for (i = 0; i < msg->cnt; i++) { chars_in += tcpci_partner_print_to_buf( - buf, buf_len, chars_in, - "%02x ", msg->buf[i]); + buf, buf_len, chars_in, "%02x ", msg->buf[i]); } chars_in += tcpci_partner_print_to_buf(buf, buf_len, chars_in, - "\n"); + "\n"); } LOG_PRINTK("%s===\n", buf); @@ -1149,11 +1148,10 @@ void tcpci_partner_common_set_ams_ctrl_msg(struct tcpci_partner_data *data, enum pd_ctrl_msg_type msg_type) { /* Make sure we handle one CTRL request at a time */ - zassert_equal( - data->cur_ams_ctrl_req, PD_CTRL_INVALID, - "More than one CTRL msg handled in parallel" - " cur_ams_ctrl_req=%d, msg_type=%d", - data->cur_ams_ctrl_req, msg_type); + zassert_equal(data->cur_ams_ctrl_req, PD_CTRL_INVALID, + "More than one CTRL msg handled in parallel" + " cur_ams_ctrl_req=%d, msg_type=%d", + data->cur_ams_ctrl_req, msg_type); data->cur_ams_ctrl_req = msg_type; } @@ -1184,7 +1182,6 @@ void tcpci_partner_received_msg_status(struct tcpci_partner_data *data, LOG_WRN("Changing status of received message more than once"); } *data->received_msg_status = status; - } /** @@ -1200,8 +1197,7 @@ void tcpci_partner_received_msg_status(struct tcpci_partner_data *data, static void tcpci_partner_transmit_op(const struct emul *emul, const struct tcpci_emul_partner_ops *ops, const struct tcpci_emul_msg *tx_msg, - enum tcpci_msg_type type, - int retry) + enum tcpci_msg_type type, int retry) { struct tcpci_partner_data *data = CONTAINER_OF(ops, struct tcpci_partner_data, ops); @@ -1209,9 +1205,8 @@ static void tcpci_partner_transmit_op(const struct emul *emul, struct tcpci_partner_extension *ext; int ret; - data->received_msg_status = - tcpci_partner_log_msg(data, tx_msg, TCPCI_PARTNER_SENDER_TCPM, - TCPCI_EMUL_TX_UNKNOWN); + data->received_msg_status = tcpci_partner_log_msg( + data, tx_msg, TCPCI_PARTNER_SENDER_TCPM, TCPCI_EMUL_TX_UNKNOWN); ret = k_mutex_lock(&data->transmit_mutex, K_FOREVER); if (ret) { @@ -1265,8 +1260,7 @@ static void tcpci_partner_transmit_op(const struct emul *emul, } /* Send reject for not handled messages (PD rev 2.0) */ - tcpci_partner_send_control_msg(data, - PD_CTRL_REJECT, 0); + tcpci_partner_send_control_msg(data, PD_CTRL_REJECT, 0); message_handled: k_mutex_unlock(&data->transmit_mutex); @@ -1280,14 +1274,13 @@ message_handled: * @param ops Pointer to partner operations structure * @param rx_msg Message that was consumed by TCPM */ -static void tcpci_partner_rx_consumed_op( - const struct emul *emul, - const struct tcpci_emul_partner_ops *ops, - const struct tcpci_emul_msg *rx_msg) +static void +tcpci_partner_rx_consumed_op(const struct emul *emul, + const struct tcpci_emul_partner_ops *ops, + const struct tcpci_emul_msg *rx_msg) { - struct tcpci_partner_msg *msg = CONTAINER_OF(rx_msg, - struct tcpci_partner_msg, - msg); + struct tcpci_partner_msg *msg = + CONTAINER_OF(rx_msg, struct tcpci_partner_msg, msg); tcpci_partner_free_msg(msg); } @@ -1298,9 +1291,9 @@ static void tcpci_partner_rx_consumed_op( * @param emul Pointer to TCPCI emulator * @param ops Pointer to partner operations structure */ -static void tcpci_partner_disconnect_op( - const struct emul *emul, - const struct tcpci_emul_partner_ops *ops) +static void +tcpci_partner_disconnect_op(const struct emul *emul, + const struct tcpci_emul_partner_ops *ops) { struct tcpci_partner_data *data = CONTAINER_OF(ops, struct tcpci_partner_data, ops); -- cgit v1.2.1 From e61da4fb542e0ec3711260c6cdfabe61a2e05edc Mon Sep 17 00:00:00 2001 From: Dino Li Date: Thu, 16 Jun 2022 17:57:27 +0800 Subject: iteflash: don't reset EC during flashing The reset is redundant after dbgr_disable_protect_path () routine is introduced. Remove it to avoid i2c transaction failure after erasing. BRANCH=none BUG=none TEST=Flashing Nereid successfully via C2D2. x10 Signed-off-by: Dino Li Change-Id: Iddd1bf873474d57fda59b89aabd296d8eaadbfd3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726596 Reviewed-by: Eric Yilun Lin --- util/iteflash.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/util/iteflash.c b/util/iteflash.c index a4a166d3d8..8cf388069e 100644 --- a/util/iteflash.c +++ b/util/iteflash.c @@ -672,28 +672,6 @@ static int check_chipid(struct common_hnd *chnd) return 0; } -/* DBGR Reset */ -static int dbgr_reset(struct common_hnd *chnd, unsigned char val) -{ - int ret = 0; - - /* Reset CPU only, and we keep power state until flashing is done. */ - if (chnd->dbgr_addr_3bytes) - ret |= i2c_write_byte(chnd, 0x80, 0xf0); - - ret |= i2c_write_byte(chnd, 0x2f, 0x20); - ret |= i2c_write_byte(chnd, 0x2e, 0x06); - - /* Enable the Reset Status by val */ - ret |= i2c_write_byte(chnd, 0x30, val); - - ret |= i2c_write_byte(chnd, 0x27, 0x80); - if (ret < 0) - fprintf(stderr, "DBGR RESET FAILED\n"); - - return 0; -} - /* Exit DBGR mode */ static int exit_dbgr_mode(struct common_hnd *chnd) { @@ -2386,8 +2364,6 @@ int main(int argc, char **argv) command_erase2(&chnd, chnd.flash_size, 0, 0); else command_erase(&chnd, chnd.flash_size, 0); - /* Call DBGR Rest to clear the EC lock status after erasing */ - dbgr_reset(&chnd, RSTS_VCCDO_PW_ON|RSTS_HGRST|RSTS_GRST); } if (chnd.conf.output_filename) { -- cgit v1.2.1 From 965d85d46abd486abe1f0173c7a7902c00f3f1f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:40 -0600 Subject: driver/usb_mux/ps8740.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1474d4ad563f63f9e396870ff28db5dbde3ae8bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730166 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8740.h | 70 ++++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 35 deletions(-) diff --git a/driver/usb_mux/ps8740.h b/driver/usb_mux/ps8740.h index 3a669b5ad9..ad4a271cd5 100644 --- a/driver/usb_mux/ps8740.h +++ b/driver/usb_mux/ps8740.h @@ -11,67 +11,67 @@ #include "usb_mux.h" -#define PS8740_I2C_ADDR0_FLAG 0x10 -#define PS8740_I2C_ADDR1_FLAG 0x11 -#define PS8740_I2C_ADDR2_FLAG 0x19 -#define PS8740_I2C_ADDR3_FLAG 0x1a +#define PS8740_I2C_ADDR0_FLAG 0x10 +#define PS8740_I2C_ADDR1_FLAG 0x11 +#define PS8740_I2C_ADDR2_FLAG 0x19 +#define PS8740_I2C_ADDR3_FLAG 0x1a /* Mode register for setting mux */ #define PS8740_REG_MODE 0x00 #define PS8740_MODE_POLARITY_INVERTED BIT(4) -#define PS8740_MODE_USB_ENABLED BIT(5) -#define PS8740_MODE_DP_ENABLED BIT(6) +#define PS8740_MODE_USB_ENABLED BIT(5) +#define PS8740_MODE_DP_ENABLED BIT(6) #ifdef CONFIG_USB_MUX_PS8740 - #define PS8740_MODE_POWER_DOWN BIT(7) +#define PS8740_MODE_POWER_DOWN BIT(7) #elif defined(CONFIG_USB_MUX_PS8742) - #define PS8740_MODE_CE_DP_ENABLED BIT(7) - /* To reset the state machine to default */ - #define PS8740_MODE_POWER_DOWN 0 +#define PS8740_MODE_CE_DP_ENABLED BIT(7) +/* To reset the state machine to default */ +#define PS8740_MODE_POWER_DOWN 0 #endif /* Status register for checking mux state */ #define PS8740_REG_STATUS 0x09 #define PS8740_STATUS_POLARITY_INVERTED BIT(2) -#define PS8740_STATUS_USB_ENABLED BIT(3) -#define PS8740_STATUS_DP_ENABLED BIT(4) -#define PS8740_STATUS_HPD_ASSERTED BIT(7) +#define PS8740_STATUS_USB_ENABLED BIT(3) +#define PS8740_STATUS_DP_ENABLED BIT(4) +#define PS8740_STATUS_HPD_ASSERTED BIT(7) /* Chip ID / revision registers and expected fused values */ #define PS8740_REG_REVISION_ID1 0xf0 #define PS8740_REG_REVISION_ID2 0xf1 -#define PS8740_REG_CHIP_ID1 0xf2 -#define PS8740_REG_CHIP_ID2 0xf3 +#define PS8740_REG_CHIP_ID1 0xf2 +#define PS8740_REG_CHIP_ID2 0xf3 #ifdef CONFIG_USB_MUX_PS8740 - #define PS8740_REVISION_ID1 0x00 - #define PS8740_REVISION_ID2_0 0x0a - #define PS8740_REVISION_ID2_1 0x0b - #define PS8740_CHIP_ID1 0x40 +#define PS8740_REVISION_ID1 0x00 +#define PS8740_REVISION_ID2_0 0x0a +#define PS8740_REVISION_ID2_1 0x0b +#define PS8740_CHIP_ID1 0x40 #elif defined(CONFIG_USB_MUX_PS8742) - #define PS8740_REVISION_ID1 0x01 - #define PS8740_REVISION_ID2_0 0x0a - #define PS8740_REVISION_ID2_1 0x0a - #define PS8740_CHIP_ID1 0x42 +#define PS8740_REVISION_ID1 0x01 +#define PS8740_REVISION_ID2_0 0x0a +#define PS8740_REVISION_ID2_1 0x0a +#define PS8740_CHIP_ID1 0x42 #endif -#define PS8740_CHIP_ID2 0x87 +#define PS8740_CHIP_ID2 0x87 /* USB equalization settings for Host to Mux */ -#define PS8740_REG_USB_EQ_TX 0x32 +#define PS8740_REG_USB_EQ_TX 0x32 #define PS8740_USB_EQ_TX_10_1_DB 0x00 #define PS8740_USB_EQ_TX_14_3_DB 0x20 -#define PS8740_USB_EQ_TX_8_5_DB 0x40 -#define PS8740_USB_EQ_TX_6_5_DB 0x60 +#define PS8740_USB_EQ_TX_8_5_DB 0x40 +#define PS8740_USB_EQ_TX_6_5_DB 0x60 #define PS8740_USB_EQ_TX_11_5_DB 0x80 -#define PS8740_USB_EQ_TX_9_5_DB 0xc0 -#define PS8740_USB_EQ_TX_7_5_DB 0xe0 +#define PS8740_USB_EQ_TX_9_5_DB 0xc0 +#define PS8740_USB_EQ_TX_7_5_DB 0xe0 #define PS8740_USB_EQ_TERM_100_OHM (0 << 2) -#define PS8740_USB_EQ_TERM_85_OHM BIT(2) +#define PS8740_USB_EQ_TERM_85_OHM BIT(2) /* USB equalization settings for Connector to Mux */ -#define PS8740_REG_USB_EQ_RX 0x3b -#define PS8740_USB_EQ_RX_4_4_DB 0x00 -#define PS8740_USB_EQ_RX_7_0_DB 0x10 -#define PS8740_USB_EQ_RX_8_2_DB 0x20 -#define PS8740_USB_EQ_RX_9_4_DB 0x30 +#define PS8740_REG_USB_EQ_RX 0x3b +#define PS8740_USB_EQ_RX_4_4_DB 0x00 +#define PS8740_USB_EQ_RX_7_0_DB 0x10 +#define PS8740_USB_EQ_RX_8_2_DB 0x20 +#define PS8740_USB_EQ_RX_9_4_DB 0x30 #define PS8740_USB_EQ_RX_10_2_DB 0x40 #define PS8740_USB_EQ_RX_11_4_DB 0x50 #define PS8740_USB_EQ_RX_14_3_DB 0x60 -- cgit v1.2.1 From 396d4d7f5bf60193b8e3eea8c742d8bffc7c704e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:36 -0600 Subject: board/drawcia/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0430ed3b68ed206c3bb6e8d812a475184c25ef4f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728238 Reviewed-by: Jeremy Bettis --- board/drawcia/led.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/drawcia/led.c b/board/drawcia/led.c index ed22fc29ba..3d743265f4 100644 --- a/board/drawcia/led.c +++ b/board/drawcia/led.c @@ -18,10 +18,8 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -29,7 +27,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -127,9 +125,9 @@ static void led_set_battery(void) */ if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } } @@ -158,8 +156,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); @@ -186,8 +184,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 042852befeb64e6d5d900c1d825f9bc2c1627693 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:54 -0600 Subject: chip/max32660/wdt_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I371d2b077cab499f7254f2dac7e0dc50e60fe6c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729239 Reviewed-by: Jeremy Bettis --- chip/max32660/wdt_regs.h | 430 ++++++++++++++++++++++++----------------------- 1 file changed, 221 insertions(+), 209 deletions(-) diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h index 32d6fe0925..fc2015696e 100644 --- a/chip/max32660/wdt_regs.h +++ b/chip/max32660/wdt_regs.h @@ -31,325 +31,337 @@ */ typedef struct { __IO uint32_t ctrl; /**< \b 0x00:<\tt> WDT CTRL Register */ - __O uint32_t rst; /**< \b 0x04:<\tt> WDT RST Register */ + __O uint32_t rst; /**< \b 0x04:<\tt> WDT RST Register */ } mxc_wdt_regs_t; /** * WDT Peripheral Register Offsets from the WDT Base Peripheral * Address. */ -#define MXC_R_WDT_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: \ +#define MXC_R_WDT_CTRL \ + ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: \ 0x0x000 */ -#define MXC_R_WDT_RST \ - ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: \ +#define MXC_R_WDT_RST \ + ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: \ 0x0x004 */ /** * Watchdog Timer Control Register. */ #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ -#define MXC_F_WDT_CTRL_INT_PERIOD \ - ((uint32_t)( \ - 0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD \ - Mask */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ +#define MXC_F_WDT_CTRL_INT_PERIOD \ + ((uint32_t)(0xFUL \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD \ + Mask */ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 \ Setting */ -#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ +#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ -#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 \ - (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ - << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 \ +#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 \ + (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 \ + << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 \ Setting */ #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ -#define MXC_F_WDT_CTRL_RST_PERIOD \ - ((uint32_t)( \ - 0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD \ - Mask */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ +#define MXC_F_WDT_CTRL_RST_PERIOD \ + ((uint32_t)(0xFUL \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD \ + Mask */ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 \ Setting */ -#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ +#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ -#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 \ - (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ - << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 \ +#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 \ + (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 \ + << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 \ Setting */ #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ #define MXC_F_WDT_CTRL_WDT_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ -#define MXC_V_WDT_CTRL_WDT_EN_DIS \ + ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask \ + */ +#define MXC_V_WDT_CTRL_WDT_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_WDT_EN_DIS \ - (MXC_V_WDT_CTRL_WDT_EN_DIS \ - << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_WDT_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \ +#define MXC_S_WDT_CTRL_WDT_EN_DIS \ + (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ + CTRL_WDT_EN_DIS \ + Setting */ +#define MXC_V_WDT_CTRL_WDT_EN_EN \ + ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_WDT_EN_EN \ - (MXC_V_WDT_CTRL_WDT_EN_EN \ - << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */ +#define MXC_S_WDT_CTRL_WDT_EN_EN \ + (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ + CTRL_WDT_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ -#define MXC_F_WDT_CTRL_INT_FLAG \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ -#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ +#define MXC_F_WDT_CTRL_INT_FLAG \ + ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG \ + Mask */ +#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */ -#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE \ - (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ - << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting \ +#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE \ + (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE \ + << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting \ */ -#define MXC_V_WDT_CTRL_INT_FLAG_PENDING \ +#define MXC_V_WDT_CTRL_INT_FLAG_PENDING \ ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */ -#define MXC_S_WDT_CTRL_INT_FLAG_PENDING \ - (MXC_V_WDT_CTRL_INT_FLAG_PENDING \ - << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */ +#define MXC_S_WDT_CTRL_INT_FLAG_PENDING \ + (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< \ + CTRL_INT_FLAG_PENDING \ + Setting \ + */ #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ #define MXC_F_WDT_CTRL_INT_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ -#define MXC_V_WDT_CTRL_INT_EN_DIS \ + ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask \ + */ +#define MXC_V_WDT_CTRL_INT_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_INT_EN_DIS \ - (MXC_V_WDT_CTRL_INT_EN_DIS \ - << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_INT_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \ +#define MXC_S_WDT_CTRL_INT_EN_DIS \ + (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ + CTRL_INT_EN_DIS \ + Setting */ +#define MXC_V_WDT_CTRL_INT_EN_EN \ + ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_INT_EN_EN \ - (MXC_V_WDT_CTRL_INT_EN_EN \ - << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */ +#define MXC_S_WDT_CTRL_INT_EN_EN \ + (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ + CTRL_INT_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ #define MXC_F_WDT_CTRL_RST_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ -#define MXC_V_WDT_CTRL_RST_EN_DIS \ + ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask \ + */ +#define MXC_V_WDT_CTRL_RST_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */ -#define MXC_S_WDT_CTRL_RST_EN_DIS \ - (MXC_V_WDT_CTRL_RST_EN_DIS \ - << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */ -#define MXC_V_WDT_CTRL_RST_EN_EN \ - ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \ +#define MXC_S_WDT_CTRL_RST_EN_DIS \ + (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ + CTRL_RST_EN_DIS \ + Setting */ +#define MXC_V_WDT_CTRL_RST_EN_EN \ + ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_RST_EN_EN \ - (MXC_V_WDT_CTRL_RST_EN_EN \ - << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */ +#define MXC_S_WDT_CTRL_RST_EN_EN \ + (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ + CTRL_RST_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ -#define MXC_F_WDT_CTRL_RST_FLAG \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ -#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ +#define MXC_F_WDT_CTRL_RST_FLAG \ + ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG \ + Mask */ +#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */ -#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT \ - (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ - << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */ -#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ +#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT \ + (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< \ + CTRL_RST_FLAG_NOEVENT \ + Setting \ + */ +#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */ -#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED \ - (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ - << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting \ +#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED \ + (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ + << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting \ */ /** * Watchdog Timer Reset Register. */ #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ -#define MXC_F_WDT_RST_WDT_RST \ - ((uint32_t)( \ - 0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ -#define MXC_V_WDT_RST_WDT_RST_SEQ0 \ +#define MXC_F_WDT_RST_WDT_RST \ + ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST \ + Mask */ +#define MXC_V_WDT_RST_WDT_RST_SEQ0 \ ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ0 \ - (MXC_V_WDT_RST_WDT_RST_SEQ0 \ - << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ -#define MXC_V_WDT_RST_WDT_RST_SEQ1 \ +#define MXC_S_WDT_RST_WDT_RST_SEQ0 \ + (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< \ + RST_WDT_RST_SEQ0 \ + Setting \ + */ +#define MXC_V_WDT_RST_WDT_RST_SEQ1 \ ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ1 \ - (MXC_V_WDT_RST_WDT_RST_SEQ1 \ - << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ +#define MXC_S_WDT_RST_WDT_RST_SEQ1 \ + (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< \ + RST_WDT_RST_SEQ1 \ + Setting \ + */ #endif /* _WDT_REGS_H_ */ -- cgit v1.2.1 From 2e871da534ec0a413294119e54773f0719372d0d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:59 -0600 Subject: chip/stm32/clock-l4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia0dc06f5e8aba338b8ac229b19287a7e2da396b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729461 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-l4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/clock-l4.h b/chip/stm32/clock-l4.h index d237b84580..25416e3c7c 100644 --- a/chip/stm32/clock-l4.h +++ b/chip/stm32/clock-l4.h @@ -107,4 +107,4 @@ void restore_host_wake_alarm(void); void low_power_init(void); #endif -#endif /* __CROS_EC_CLOCK_L4_H */ +#endif /* __CROS_EC_CLOCK_L4_H */ -- cgit v1.2.1 From e726c3f7c7fe3b7507d0c991bb81ac8530d6cac1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:18 -0600 Subject: board/gelarshie/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49350fd83bbbb3e14bdc2459c7f915b5bf8c8a48 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728395 Reviewed-by: Jeremy Bettis --- board/gelarshie/led.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/gelarshie/led.c b/board/gelarshie/led.c index 0a6c85be6d..aae9fa44cb 100644 --- a/board/gelarshie/led.c +++ b/board/gelarshie/led.c @@ -35,15 +35,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_W_C0, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -84,16 +84,15 @@ static void board_led_set_battery(void) period = (1 + 1) * LED_ONE_SEC; battery_ticks = battery_ticks % period; if (battery_ticks < 1 * LED_ONE_SEC) { - if (charge_get_percent() < 10) - { - /* Blink amber light (1 sec on, 1 sec off) */ + if (charge_get_percent() < 10) { + /* Blink amber light (1 sec on, 1 sec + * off) */ color = LED_AMBER; - } - else - { - /* Blink white light (1 sec on, 1 sec off) */ + } else { + /* Blink white light (1 sec on, 1 sec + * off) */ color = LED_BLUE; - } + } } else { color = LED_OFF; } -- cgit v1.2.1 From bd7a9c455b14dfd634eea8253159817b94e84cbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:52 -0600 Subject: board/hatch/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id53dde1d418c5dfb71a42ee82b93495dcaed39c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728319 Reviewed-by: Jeremy Bettis --- board/hatch/board.h | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/board/hatch/board.h b/board/hatch/board.h index 78c97372ec..7e61d2cdad 100644 --- a/board/hatch/board.h +++ b/board/hatch/board.h @@ -43,7 +43,7 @@ #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) -#define I2C_PORT_ALS I2C_PORT_SENSOR +#define I2C_PORT_ALS I2C_PORT_SENSOR /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_COMM_LOCKED @@ -107,16 +107,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -128,8 +128,8 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ ADC_CH_COUNT }; @@ -142,11 +142,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, @@ -160,11 +156,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 3be373f376c4e911e655e3452d1f6eaf788966d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:53 -0600 Subject: board/crota/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d22eb3a56a12b47b121df4ba7855e341f53a372 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728189 Reviewed-by: Jeremy Bettis --- board/crota/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/crota/board.c b/board/crota/board.c index 855eeabb81..d74bdc29b6 100644 --- a/board/crota/board.c +++ b/board/crota/board.c @@ -31,8 +31,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) __override void board_cbi_init(void) { @@ -75,4 +75,4 @@ static void usba_power(void) } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usba_power, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_AC_CHANGE, usba_power, HOOK_PRIO_DEFAULT); -#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */ +#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */ -- cgit v1.2.1 From 253b571724f11e538a8b89343c1597f9f59fbca2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:44 -0600 Subject: include/led_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a8d85b08af8604ada0f39c4bb8a4ade8b169a9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730312 Reviewed-by: Jeremy Bettis --- include/led_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/led_common.h b/include/led_common.h index 8e9f1441f3..87cd10f766 100644 --- a/include/led_common.h +++ b/include/led_common.h @@ -79,8 +79,8 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness); void led_enable(int enable); enum ec_led_state { - LED_STATE_OFF = 0, - LED_STATE_ON = 1, + LED_STATE_OFF = 0, + LED_STATE_ON = 1, LED_STATE_RESET = 2, }; -- cgit v1.2.1 From 7c59200c3960b16b66180bad9d2d48b857da4c28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:29 -0600 Subject: driver/tcpm/ccgxxf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If95f79e1655b05bc102a54e28684e1b919bbeb98 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730076 Reviewed-by: Jeremy Bettis --- driver/tcpm/ccgxxf.c | 54 ++++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c index ee1754ce08..b206da44c2 100644 --- a/driver/tcpm/ccgxxf.c +++ b/driver/tcpm/ccgxxf.c @@ -25,55 +25,55 @@ static void ccgxxf_dump_registers(int port) /* Get the F/W version and build ID */ if (!tcpc_read16(port, CCGXXF_REG_FW_VERSION, &fw_ver) && - !tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) { + !tcpc_read16(port, CCGXXF_REG_FW_VERSION_BUILD, &fw_build)) { ccprintf(" FW_VERSION(build.major.minor) = %d.%d.%d\n", - fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); + fw_build & 0xFF, (fw_ver >> 8) & 0xFF, fw_ver & 0xFF); } } #endif const struct tcpm_drv ccgxxf_tcpm_drv = { - .init = &tcpci_tcpm_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &tcpci_tcpm_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tcpci_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif .tcpc_enable_auto_discharge_disconnect = &tcpci_tcpc_enable_auto_discharge_disconnect, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, + .get_chip_info = &tcpci_get_chip_info, #ifdef CONFIG_USB_PD_PPC - .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, - .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, - .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #endif #ifdef CONFIG_USB_PD_TCPM_SBU - .set_sbu = &ccgxxf_tcpc_set_sbu, + .set_sbu = &ccgxxf_tcpc_set_sbu, #endif #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &tcpci_enter_low_power_mode, + .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP - .dump_registers = &ccgxxf_dump_registers, + .dump_registers = &ccgxxf_dump_registers, #endif }; -- cgit v1.2.1 From 8e7ecdb70f4b591593bafb2a3e0f90bc3e37b98f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:20 -0600 Subject: board/taeko/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ddaec07b05de02fadb7cc4568ddccd9e6f7acaf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728982 Reviewed-by: Jeremy Bettis --- board/taeko/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/taeko/fw_config.c b/board/taeko/fw_config.c index 02480a6205..0d3c6fc493 100644 --- a/board/taeko/fw_config.c +++ b/board/taeko/fw_config.c @@ -10,7 +10,7 @@ #include "fw_config.h" #include "gpio.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union taeko_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 26b2f375a3108b92d22850aa452f1dda99bc8e9e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:12 -0600 Subject: common/vec3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibcbfa142d701322c99bd413d72f33095b2cddb9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729810 Reviewed-by: Jeremy Bettis --- common/vec3.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/common/vec3.c b/common/vec3.c index dadf7715ff..1679e8a7f5 100644 --- a/common/vec3.c +++ b/common/vec3.c @@ -9,9 +9,8 @@ #include "vec3.h" #include "util.h" -static fpv3_t zero_initialized_vector = { - FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f) -}; +static fpv3_t zero_initialized_vector = { FLOAT_TO_FP(0.0f), FLOAT_TO_FP(0.0f), + FLOAT_TO_FP(0.0f) }; void fpv3_zero(fpv3_t v) { -- cgit v1.2.1 From 6c78ed6ac183f9a8e386d8f6b110f6fcc04fcec5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:12 -0600 Subject: zephyr/test/hooks/hooks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9fcee8dcf57e0b53dd3662794d5559a6e218a1f2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730961 Reviewed-by: Jeremy Bettis --- zephyr/test/hooks/hooks.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/zephyr/test/hooks/hooks.c b/zephyr/test/hooks/hooks.c index 0070f2e6b4..c9ff456084 100644 --- a/zephyr/test/hooks/hooks.c +++ b/zephyr/test/hooks/hooks.c @@ -179,7 +179,7 @@ static void test_hook_ap_power_events(void) cb.count = 0; ap_power_ev_init_callback(&cb.cb, ev_handler, - AP_POWER_SUSPEND|AP_POWER_RESUME); + AP_POWER_SUSPEND | AP_POWER_RESUME); ap_power_ev_add_callback(&cb.cb); hook_notify(HOOK_CHIPSET_SUSPEND); zassert_equal(1, cb.count, "Callbacks not called"); @@ -201,15 +201,13 @@ static void test_hook_ap_power_events(void) void test_main(void) { - ztest_test_suite( - hooks_tests, - ztest_unit_test(test_hook_list_multiple), - ztest_unit_test(test_hook_list_single), - ztest_unit_test(test_hook_list_empty), - ztest_unit_test(test_deferred_func), - ztest_unit_test(test_deferred_func_push_out), - ztest_unit_test(test_deferred_func_cancel), - ztest_unit_test(test_hook_ap_power_events)); + ztest_test_suite(hooks_tests, ztest_unit_test(test_hook_list_multiple), + ztest_unit_test(test_hook_list_single), + ztest_unit_test(test_hook_list_empty), + ztest_unit_test(test_deferred_func), + ztest_unit_test(test_deferred_func_push_out), + ztest_unit_test(test_deferred_func_cancel), + ztest_unit_test(test_hook_ap_power_events)); ztest_run_test_suite(hooks_tests); } -- cgit v1.2.1 From 5d3b91abbab18aa5333a02679937e42a733c8e5d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:48 -0600 Subject: baseboard/goroh/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I539e8b095d83561d5bd4ee42877791be98684cb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727510 Reviewed-by: Jeremy Bettis --- baseboard/goroh/baseboard.c | 85 +++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 46 deletions(-) diff --git a/baseboard/goroh/baseboard.c b/baseboard/goroh/baseboard.c index d51b881753..94649d2670 100644 --- a/baseboard/goroh/baseboard.c +++ b/baseboard/goroh/baseboard.c @@ -48,8 +48,8 @@ #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Wake-up pins for hibernate */ enum gpio_signal hibernate_wake_pins[] = { @@ -68,11 +68,9 @@ const struct charger_config_t chg_chips[] = { }; /* BC12 skeleton to make build happy. */ -struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { -}; +struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = {}; -const int usb_port_enable[USB_PORT_COUNT] = { -}; +const int usb_port_enable[USB_PORT_COUNT] = {}; /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) @@ -109,34 +107,26 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -145,7 +135,6 @@ int board_allow_i2c_passthru(const struct i2c_cmd_desc_t *cmd_desc) return (cmd_desc->port == I2C_PORT_VIRTUAL_BATTERY); } - void board_overcurrent_event(int port, int is_overcurrented) { /* TODO: check correct operation for GOROH */ @@ -155,21 +144,25 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -- cgit v1.2.1 From 2174fff2cf52e0f91597687ae1a22653c348a008 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:22 -0600 Subject: chip/max32660/hwtimer_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If12f7393fdc74052652e80863474a7227281d8b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729232 Reviewed-by: Jeremy Bettis --- chip/max32660/hwtimer_chip.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/chip/max32660/hwtimer_chip.c b/chip/max32660/hwtimer_chip.c index 5417e161b2..a8e21627cd 100644 --- a/chip/max32660/hwtimer_chip.c +++ b/chip/max32660/hwtimer_chip.c @@ -41,36 +41,36 @@ static uint32_t last_deadline; /* brief Timer prescaler values */ enum tmr_pres { - TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1, /// Divide input clock by 1 - TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2, /// Divide input clock by 2 - TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4, /// Divide input clock by 4 - TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8, /// Divide input clock by 8 - TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16, /// Divide input clock by 16 - TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32, /// Divide input clock by 32 - TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64, /// Divide input clock by 64 + TMR_PRES_1 = MXC_V_TMR_CN_PRES_DIV1, /// Divide input clock by 1 + TMR_PRES_2 = MXC_V_TMR_CN_PRES_DIV2, /// Divide input clock by 2 + TMR_PRES_4 = MXC_V_TMR_CN_PRES_DIV4, /// Divide input clock by 4 + TMR_PRES_8 = MXC_V_TMR_CN_PRES_DIV8, /// Divide input clock by 8 + TMR_PRES_16 = MXC_V_TMR_CN_PRES_DIV16, /// Divide input clock by 16 + TMR_PRES_32 = MXC_V_TMR_CN_PRES_DIV32, /// Divide input clock by 32 + TMR_PRES_64 = MXC_V_TMR_CN_PRES_DIV64, /// Divide input clock by 64 TMR_PRES_128 = MXC_V_TMR_CN_PRES_DIV128, /// Divide input clock by 128 - TMR_PRES_256 = - (0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 256 - TMR_PRES_512 = - (0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 512 - TMR_PRES_1024 = - (0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 1024 - TMR_PRES_2048 = - (0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 2048 - TMR_PRES_4096 = - (0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock by 4096 + TMR_PRES_256 = (0x20 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock + /// by 256 + TMR_PRES_512 = (0x21 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock + /// by 512 + TMR_PRES_1024 = (0x22 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock + /// by 1024 + TMR_PRES_2048 = (0x23 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock + /// by 2048 + TMR_PRES_4096 = (0x24 << MXC_F_TMR_CN_PRES_POS), /// Divide input clock + /// by 4096 }; /* Timer modes */ enum tmr_mode { TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT - TMR_MODE_CONTINUOUS = - MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode CONTINUOUS + TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode + /// CONTINUOUS TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER - TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM + TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE - TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED + TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED TMR_MODE_CAPTURE_COMPARE = MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE }; -- cgit v1.2.1 From 24639527bac79e732ece453627c711626414fc58 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:05 -0600 Subject: driver/usb_mux/usb_mux.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iadbcd75b18c11f20ab5236500d307de7728b97b6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730173 Reviewed-by: Jeremy Bettis --- driver/usb_mux/usb_mux.c | 148 ++++++++++++++++++++++------------------------- 1 file changed, 68 insertions(+), 80 deletions(-) diff --git a/driver/usb_mux/usb_mux.c b/driver/usb_mux/usb_mux.c index 1dea4b8d29..19898c4505 100644 --- a/driver/usb_mux/usb_mux.c +++ b/driver/usb_mux/usb_mux.c @@ -19,8 +19,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -35,17 +35,18 @@ static int enable_debug_prints; static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; /* Device is in low power mode. */ -#define USB_MUX_FLAG_IN_LPM BIT(0) +#define USB_MUX_FLAG_IN_LPM BIT(0) /* Device initialized at least once */ -#define USB_MUX_FLAG_INIT BIT(1) +#define USB_MUX_FLAG_INIT BIT(1) /* Coordinate mux accesses by-port among the tasks */ static mutex_t mux_lock[CONFIG_USB_PD_PORT_MAX_COUNT]; /* Coordinate which task requires an ACK event */ static task_id_t ack_task[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID }; + [0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = TASK_ID_INVALID +}; static void perform_mux_set(int port, int index, mux_state_t mux_mode, enum usb_switch usb_mode, int polarity); @@ -79,7 +80,7 @@ enum mux_config_type { * Depth must be a power of 2, which is normally enforced by the queue init * code, but must be manually enforced here. */ -#define MUX_QUEUE_DEPTH 4 +#define MUX_QUEUE_DEPTH 4 BUILD_ASSERT(POWER_OF_TWO(MUX_QUEUE_DEPTH)); /* Define in order to enable debug info about how long the queue takes */ @@ -87,10 +88,10 @@ BUILD_ASSERT(POWER_OF_TWO(MUX_QUEUE_DEPTH)); struct mux_queue_entry { enum mux_config_type type; - int index; /* Index to set, or USB_MUX_ALL_CHIPS */ - mux_state_t mux_mode; /* For both HPD and mux set */ - enum usb_switch usb_config; /* Set only */ - int polarity; /* Set only */ + int index; /* Index to set, or USB_MUX_ALL_CHIPS */ + mux_state_t mux_mode; /* For both HPD and mux set */ + enum usb_switch usb_config; /* Set only */ + int polarity; /* Set only */ #ifdef DEBUG_MUX_QUEUE_TIME timestamp_t enqueued_time; #endif @@ -108,10 +109,9 @@ struct mux_queue_entry { */ static struct queue mux_queue[CONFIG_USB_PD_PORT_MAX_COUNT]; __maybe_unused static struct queue_state - queue_states[CONFIG_USB_PD_PORT_MAX_COUNT]; + queue_states[CONFIG_USB_PD_PORT_MAX_COUNT]; __maybe_unused static struct mux_queue_entry - queue_buffers[CONFIG_USB_PD_PORT_MAX_COUNT] - [MUX_QUEUE_DEPTH]; + queue_buffers[CONFIG_USB_PD_PORT_MAX_COUNT][MUX_QUEUE_DEPTH]; static mutex_t queue_lock[CONFIG_USB_PD_PORT_MAX_COUNT]; #else extern struct queue const mux_queue[]; @@ -136,11 +136,9 @@ static int init_mux_mutex(const struct device *dev) SYS_INIT(init_mux_mutex, POST_KERNEL, 50); #endif /* CONFIG_ZEPHYR */ -__maybe_unused static void mux_task_enqueue(int port, int index, - enum mux_config_type type, - mux_state_t mux_mode, - enum usb_switch usb_config, - int polarity) +__maybe_unused static void +mux_task_enqueue(int port, int index, enum mux_config_type type, + mux_state_t mux_mode, enum usb_switch usb_config, int polarity) { struct mux_queue_entry new_entry; @@ -177,7 +175,7 @@ static void init_queue_structs(void) mux_queue[i].buffer_units = MUX_QUEUE_DEPTH; mux_queue[i].buffer_units_mask = MUX_QUEUE_DEPTH - 1; mux_queue[i].unit_bytes = sizeof(struct mux_queue_entry); - mux_queue[i].buffer = (uint8_t *) &queue_buffers[i][0]; + mux_queue[i].buffer = (uint8_t *)&queue_buffers[i][0]; } } DECLARE_HOOK(HOOK_INIT, init_queue_structs, HOOK_PRIO_FIRST); @@ -227,7 +225,8 @@ __maybe_unused void usb_mux_task(void *u) next.mux_mode); else CPRINTS("Error: Unknown mux task type:" - "%d", next.type); + "%d", + next.type); #ifdef DEBUG_MUX_QUEUE_TIME CPRINTS("C%d: Completed mux set queued %d " @@ -254,16 +253,14 @@ __maybe_unused void usb_mux_task(void *u) } /* Configure the MUX */ -static int configure_mux(int port, int index, - enum mux_config_type config, +static int configure_mux(int port, int index, enum mux_config_type config, mux_state_t *mux_state) { int rv = EC_SUCCESS; const struct usb_mux *mux_ptr; int chip = 0; - if (config == USB_MUX_SET_MODE || - config == USB_MUX_GET_MODE) { + if (config == USB_MUX_SET_MODE || config == USB_MUX_GET_MODE) { if (mux_state == NULL) return EC_ERROR_INVAL; @@ -276,8 +273,7 @@ static int configure_mux(int port, int index, * MUXes. So when we change one, we traverse the whole list * to make sure they are all updated appropriately. */ - for (mux_ptr = &usb_muxes[port]; - rv == EC_SUCCESS && mux_ptr != NULL; + for (mux_ptr = &usb_muxes[port]; rv == EC_SUCCESS && mux_ptr != NULL; mux_ptr = mux_ptr->next_mux, chip++) { mux_state_t lcl_state; const struct usb_mux_driver *drv = mux_ptr->driver; @@ -335,10 +331,12 @@ static int configure_mux(int port, int index, /* Inform the AP its selected mux is set */ if (IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL)) { if (chip == 0) - pd_notify_event(port, + pd_notify_event( + port, PD_STATUS_EVENT_MUX_0_SET_DONE); else if (chip == 1) - pd_notify_event(port, + pd_notify_event( + port, PD_STATUS_EVENT_MUX_1_SET_DONE); } @@ -363,7 +361,6 @@ static int configure_mux(int port, int index, if (mux_ptr->hpd_update) mux_ptr->hpd_update(mux_ptr, *mux_state, &ack_required); - } /* Unlock before any host command waits */ @@ -380,10 +377,10 @@ static int configure_mux(int port, int index, assert(task_get_current() == TASK_ID_USB_MUX); } else { #if defined(CONFIG_ZEPHYR) && defined(TEST_BUILD) - assert(port == - TASK_ID_TO_PD_PORT(task_get_current()) || + assert(port == TASK_ID_TO_PD_PORT( + task_get_current()) || task_get_current() == - TASK_ID_TEST_RUNNER); + TASK_ID_TEST_RUNNER); #else assert(port == TASK_ID_TO_PD_PORT(task_get_current())); @@ -397,7 +394,7 @@ static int configure_mux(int port, int index, * mux, but could be made configurable for other * purposes. */ - task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100*MSEC); + task_wait_event_mask(PD_EVENT_AP_MUX_DONE, 100 * MSEC); ack_task[port] = TASK_ID_INVALID; usleep(12.5 * MSEC); @@ -405,8 +402,7 @@ static int configure_mux(int port, int index, } if (rv) - CPRINTS("mux config:%d, port:%d, rv:%d", - config, port, rv); + CPRINTS("mux config:%d, port:%d, rv:%d", config, port, rv); return rv; } @@ -474,7 +470,7 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode, mux_state_t mux_state; const int should_enter_low_power_mode = (mux_mode == USB_PD_MUX_NONE && - usb_mode == USB_SWITCH_DISCONNECT); + usb_mode == USB_SWITCH_DISCONNECT); /* Perform initialization if not initialized yet */ if (!(flags[port] & USB_MUX_FLAG_INIT)) @@ -496,17 +492,16 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode, return; /* Configure superspeed lanes */ - mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity) - ? mux_mode | USB_PD_MUX_POLARITY_INVERTED - : mux_mode; + mux_state = ((mux_mode != USB_PD_MUX_NONE) && polarity) ? + mux_mode | USB_PD_MUX_POLARITY_INVERTED : + mux_mode; if (configure_mux(port, index, USB_MUX_SET_MODE, &mux_state)) return; if (enable_debug_prints) - CPRINTS( - "usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)", - port, mux_mode, usb_mode, polarity); + CPRINTS("usb/dp mux: port(%d) typec_mux(%d) usb2(%d) polarity(%d)", + port, mux_mode, usb_mode, polarity); /* * If we are completely disconnecting the mux, then we should put it in @@ -516,20 +511,19 @@ static void perform_mux_set(int port, int index, mux_state_t mux_mode, enter_low_power_mode(port); } -void usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_mode, int polarity) +void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_mode, + int polarity) { if (port >= board_get_usb_pd_port_count()) return; /* Block if we have no mux task, but otherwise queue it up and return */ if (IS_ENABLED(HAS_TASK_USB_MUX)) - mux_task_enqueue(port, USB_MUX_ALL_CHIPS, - USB_MUX_SET_MODE, mux_mode, - usb_mode, polarity); + mux_task_enqueue(port, USB_MUX_ALL_CHIPS, USB_MUX_SET_MODE, + mux_mode, usb_mode, polarity); else - perform_mux_set(port, USB_MUX_ALL_CHIPS, - mux_mode, usb_mode, polarity); + perform_mux_set(port, USB_MUX_ALL_CHIPS, mux_mode, usb_mode, + polarity); } void usb_mux_set_single(int port, int index, mux_state_t mux_mode, @@ -540,12 +534,10 @@ void usb_mux_set_single(int port, int index, mux_state_t mux_mode, /* Block if we have no mux task, but otherwise queue it up and return */ if (IS_ENABLED(HAS_TASK_USB_MUX)) - mux_task_enqueue(port, index, - USB_MUX_SET_MODE, mux_mode, + mux_task_enqueue(port, index, USB_MUX_SET_MODE, mux_mode, usb_mode, polarity); else - perform_mux_set(port, index, - mux_mode, usb_mode, polarity); + perform_mux_set(port, index, mux_mode, usb_mode, polarity); } bool usb_mux_set_completed(int port) @@ -561,9 +553,9 @@ bool usb_mux_set_completed(int port) mutex_lock(&queue_lock[port]); for (queue_begin(&mux_queue[port], &it); it.ptr != NULL; - queue_next(&mux_queue[port], &it)) { + queue_next(&mux_queue[port], &it)) { const struct mux_queue_entry *check = - (struct mux_queue_entry *) it.ptr; + (struct mux_queue_entry *)it.ptr; if (check->type == USB_MUX_SET_MODE) { sets_pending = true; @@ -666,8 +658,8 @@ int usb_mux_retimer_fw_update_port_info(void) mux_ptr = &usb_muxes[i]; while (mux_ptr) { if (mux_ptr->driver && - mux_ptr->driver->is_retimer_fw_update_capable && - mux_ptr->driver->is_retimer_fw_update_capable()) + mux_ptr->driver->is_retimer_fw_update_capable && + mux_ptr->driver->is_retimer_fw_update_capable()) port_info |= BIT(i); mux_ptr = mux_ptr->next_mux; } @@ -701,7 +693,7 @@ static void usb_mux_reset_in_g3(void) if (mux_ptr->flags & USB_MUX_FLAG_RESETS_IN_G3) { atomic_clear_bits(&flags[port], USB_MUX_FLAG_INIT | - USB_MUX_FLAG_IN_LPM); + USB_MUX_FLAG_IN_LPM); } mux_ptr = mux_ptr->next_mux; } @@ -712,7 +704,7 @@ DECLARE_HOOK(HOOK_CHIPSET_HARD_OFF, usb_mux_reset_in_g3, HOOK_PRIO_DEFAULT); #ifdef CONFIG_CMD_TYPEC static int command_typec(int argc, char **argv) { - const char * const mux_name[] = {"none", "usb", "dp", "dock"}; + const char *const mux_name[] = { "none", "usb", "dp", "dock" }; char *e; int port; mux_state_t mux = USB_PD_MUX_NONE; @@ -735,16 +727,16 @@ static int command_typec(int argc, char **argv) mux_state = usb_mux_get(port); ccprintf("Port %d: USB=%d DP=%d POLARITY=%s HPD_IRQ=%d " - "HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n", port, - !!(mux_state & USB_PD_MUX_USB_ENABLED), - !!(mux_state & USB_PD_MUX_DP_ENABLED), - mux_state & USB_PD_MUX_POLARITY_INVERTED ? - "INVERTED" : "NORMAL", - !!(mux_state & USB_PD_MUX_HPD_IRQ), - !!(mux_state & USB_PD_MUX_HPD_LVL), - !!(mux_state & USB_PD_MUX_SAFE_MODE), - !!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED), - !!(mux_state & USB_PD_MUX_USB4_ENABLED)); + "HPD_LVL=%d SAFE=%d TBT=%d USB4=%d\n", + port, !!(mux_state & USB_PD_MUX_USB_ENABLED), + !!(mux_state & USB_PD_MUX_DP_ENABLED), + mux_state & USB_PD_MUX_POLARITY_INVERTED ? "INVERTED" : + "NORMAL", + !!(mux_state & USB_PD_MUX_HPD_IRQ), + !!(mux_state & USB_PD_MUX_HPD_LVL), + !!(mux_state & USB_PD_MUX_SAFE_MODE), + !!(mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED), + !!(mux_state & USB_PD_MUX_USB4_ENABLED)); return EC_SUCCESS; } @@ -752,14 +744,13 @@ static int command_typec(int argc, char **argv) for (i = 0; i < ARRAY_SIZE(mux_name); i++) if (!strcasecmp(argv[2], mux_name[i])) mux = i; - usb_mux_set(port, mux, mux == USB_PD_MUX_NONE ? - USB_SWITCH_DISCONNECT : - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + usb_mux_set(port, mux, + mux == USB_PD_MUX_NONE ? USB_SWITCH_DISCONNECT : + USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(typec, command_typec, - "[port|debug] [none|usb|dp|dock]", +DECLARE_CONSOLE_COMMAND(typec, command_typec, "[port|debug] [none|usb|dp|dock]", "Control type-C connector muxing"); #endif @@ -786,8 +777,7 @@ static enum ec_status hc_usb_pd_mux_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO, - hc_usb_pd_mux_info, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_INFO, hc_usb_pd_mux_info, EC_VER_MASK(0)); static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args) @@ -802,6 +792,4 @@ static enum ec_status hc_usb_pd_mux_ack(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK, - hc_usb_pd_mux_ack, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_MUX_ACK, hc_usb_pd_mux_ack, EC_VER_MASK(0)); -- cgit v1.2.1 From 819f9e138bcc1efd58de0f07203e90fc53237699 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:00 -0600 Subject: common/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70ddb6a28ae1bb4907b896caa9ace0c25636e55f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729728 Reviewed-by: Jeremy Bettis --- common/pwm.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/common/pwm.c b/common/pwm.c index a4edfdd5a5..df869673b8 100644 --- a/common/pwm.c +++ b/common/pwm.c @@ -13,9 +13,8 @@ #ifdef CONFIG_PWM -#define PWM_RAW_TO_PERCENT(v) \ - DIV_ROUND_NEAREST((uint32_t)(v) * 100, UINT16_MAX) -#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v) * UINT16_MAX / 100) +#define PWM_RAW_TO_PERCENT(v) DIV_ROUND_NEAREST((uint32_t)(v)*100, UINT16_MAX) +#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v)*UINT16_MAX / 100) /* * Get target channel based on type / index host command parameters. @@ -71,8 +70,7 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); static enum ec_status @@ -92,8 +90,7 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); /** @@ -153,7 +150,7 @@ static int cc_pwm_duty(int argc, char **argv) ccprintf("Setting channel %d to %d\n", ch, value); pwm_enable(ch, 1); (max_duty == 100) ? pwm_set_duty(ch, value) : - pwm_set_raw_duty(ch, value); + pwm_set_raw_duty(ch, value); } } -- cgit v1.2.1 From fdb4f4fe85dfb20a614c24728453a8b79d35cc4c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:37 -0600 Subject: test/motion_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I436a96f98aaa44baef67fda36d8dbc1cb1f6822a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730513 Reviewed-by: Jeremy Bettis --- test/motion_common.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/test/motion_common.c b/test/motion_common.c index c7c3395fc4..a63683ce29 100644 --- a/test/motion_common.c +++ b/test/motion_common.c @@ -43,9 +43,8 @@ static int accel_get_resolution(const struct motion_sensor_t *s) int test_data_rate[2] = { 0 }; -static int accel_set_data_rate(const struct motion_sensor_t *s, - const int rate, - const int rnd) +static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate, + const int rnd) { test_data_rate[s - motion_sensors] = rate | (rnd ? ROUND_UP_FLAG : 0); return EC_SUCCESS; @@ -62,8 +61,8 @@ static int accel_get_rms_noise(const struct motion_sensor_t *s) /* Assume we are using BMI160 */ fp_t rate = INT_TO_FP(accel_get_data_rate(s) / 1000); fp_t noise_100hz = INT_TO_FP(BMI160_ACCEL_RMS_NOISE_100HZ); - fp_t sqrt_rate_ratio = fp_sqrtf(fp_div(rate, - INT_TO_FP(BMI_ACCEL_100HZ))); + fp_t sqrt_rate_ratio = + fp_sqrtf(fp_div(rate, INT_TO_FP(BMI_ACCEL_100HZ))); return FP_TO_INT(fp_mul(noise_100hz, sqrt_rate_ratio)); } #endif @@ -118,7 +117,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Read 6 samples from array to sensor vectors, convert units if necessary. */ void feed_accel_data(const float *array, int *idx, - int (filler)(const struct motion_sensor_t*, const float)) + int(filler)(const struct motion_sensor_t *, const float)) { int i, j; -- cgit v1.2.1 From d3be0c14579fa8b172c4485c8cf8968ee71dfb23 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:34 -0600 Subject: driver/accelgyro_bmi_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff4fe44c21e0385746ddbede46b70a39327f2b21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729892 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi_common.c | 95 +++++++++++++++++++++---------------------- 1 file changed, 46 insertions(+), 49 deletions(-) diff --git a/driver/accelgyro_bmi_common.c b/driver/accelgyro_bmi_common.c index 210cfd37ce..7ab202d515 100644 --- a/driver/accelgyro_bmi_common.c +++ b/driver/accelgyro_bmi_common.c @@ -8,7 +8,6 @@ * 3D digital accelerometer & 3D digital gyroscope */ - #include "accelgyro.h" #include "console.h" #include "accelgyro_bmi_common.h" @@ -20,29 +19,29 @@ #include "spi.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) -#if !defined(CONFIG_ACCELGYRO_BMI160) && \ - !defined(CONFIG_ACCELGYRO_BMI220) && \ - !defined(CONFIG_ACCELGYRO_BMI260) && \ - !defined(CONFIG_ACCELGYRO_BMI3XX) +#if !defined(CONFIG_ACCELGYRO_BMI160) && !defined(CONFIG_ACCELGYRO_BMI220) && \ + !defined(CONFIG_ACCELGYRO_BMI260) && !defined(CONFIG_ACCELGYRO_BMI3XX) #error "Must use following sensors BMI160 BMI220 BMI260 BMI3XX" #endif #if (defined(CONFIG_ACCELGYRO_BMI260) || defined(CONFIG_ACCELGYRO_BMI220)) && \ - !defined(CONFIG_ACCELGYRO_BMI160) + !defined(CONFIG_ACCELGYRO_BMI160) #define V(s_) 1 -#elif defined(CONFIG_ACCELGYRO_BMI160) && \ - !(defined(CONFIG_ACCELGYRO_BMI260) || defined(CONFIG_ACCELGYRO_BMI220)) +#elif defined(CONFIG_ACCELGYRO_BMI160) && \ + !(defined(CONFIG_ACCELGYRO_BMI260) || \ + defined(CONFIG_ACCELGYRO_BMI220)) #define V(s_) 0 #else -#define V(s_) ((s_)->chip == MOTIONSENSE_CHIP_BMI260 || \ - (s_)->chip == MOTIONSENSE_CHIP_BMI220) +#define V(s_) \ + ((s_)->chip == MOTIONSENSE_CHIP_BMI260 || \ + (s_)->chip == MOTIONSENSE_CHIP_BMI220) #endif /* Index for which table to use. */ #if defined(CONFIG_ACCELGYRO_BMI160) && \ - (defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)) + (defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260)) #define T(s_) V(s_) #else #define T(s_) 0 @@ -51,16 +50,16 @@ /* List of range values in +/-G's and their associated register values. */ const struct bmi_accel_param_pair g_ranges[][4] = { #ifdef CONFIG_ACCELGYRO_BMI160 - { {2, BMI160_GSEL_2G}, - {4, BMI160_GSEL_4G}, - {8, BMI160_GSEL_8G}, - {16, BMI160_GSEL_16G} }, + { { 2, BMI160_GSEL_2G }, + { 4, BMI160_GSEL_4G }, + { 8, BMI160_GSEL_8G }, + { 16, BMI160_GSEL_16G } }, #endif #if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260) - { {2, BMI260_GSEL_2G}, - {4, BMI260_GSEL_4G}, - {8, BMI260_GSEL_8G}, - {16, BMI260_GSEL_16G} }, + { { 2, BMI260_GSEL_2G }, + { 4, BMI260_GSEL_4G }, + { 8, BMI260_GSEL_8G }, + { 16, BMI260_GSEL_16G } }, #endif }; @@ -70,18 +69,18 @@ const struct bmi_accel_param_pair g_ranges[][4] = { */ const struct bmi_accel_param_pair dps_ranges[][5] = { #ifdef CONFIG_ACCELGYRO_BMI160 - { {125, BMI160_DPS_SEL_125}, - {250, BMI160_DPS_SEL_250}, - {500, BMI160_DPS_SEL_500}, - {1000, BMI160_DPS_SEL_1000}, - {2000, BMI160_DPS_SEL_2000} }, + { { 125, BMI160_DPS_SEL_125 }, + { 250, BMI160_DPS_SEL_250 }, + { 500, BMI160_DPS_SEL_500 }, + { 1000, BMI160_DPS_SEL_1000 }, + { 2000, BMI160_DPS_SEL_2000 } }, #endif #if defined(CONFIG_ACCELGYRO_BMI220) || defined(CONFIG_ACCELGYRO_BMI260) - { {125, BMI260_DPS_SEL_125}, - {250, BMI260_DPS_SEL_250}, - {500, BMI260_DPS_SEL_500}, - {1000, BMI260_DPS_SEL_1000}, - {2000, BMI260_DPS_SEL_2000} }, + { { 125, BMI260_DPS_SEL_125 }, + { 250, BMI260_DPS_SEL_250 }, + { 500, BMI260_DPS_SEL_500 }, + { 1000, BMI260_DPS_SEL_1000 }, + { 2000, BMI260_DPS_SEL_2000 } }, #endif }; @@ -99,8 +98,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s) } } -const struct bmi_accel_param_pair *bmi_get_range_table( - const struct motion_sensor_t *s, int *psize) +const struct bmi_accel_param_pair * +bmi_get_range_table(const struct motion_sensor_t *s, int *psize) { if (s->type == MOTIONSENSE_TYPE_ACCEL) { if (psize) @@ -119,8 +118,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table( * outside the range of values, it returns the closest valid reg value. */ int bmi_get_reg_val(const int eng_val, const int round_up, - const struct bmi_accel_param_pair *pairs, - const int size) + const struct bmi_accel_param_pair *pairs, const int size) { int i; @@ -128,7 +126,7 @@ int bmi_get_reg_val(const int eng_val, const int round_up, if (eng_val <= pairs[i].val) break; - if (eng_val < pairs[i+1].val) { + if (eng_val < pairs[i + 1].val) { if (round_up) i += 1; break; @@ -154,8 +152,8 @@ int bmi_get_engineering_val(const int reg_val, } #ifdef CONFIG_ACCELGYRO_BMI_COMM_SPI -static int bmi_spi_raw_read(const int addr, const uint8_t reg, - uint8_t *data, const int len) +static int bmi_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data, + const int len) { uint8_t cmd = 0x80 | reg; @@ -166,8 +164,8 @@ static int bmi_spi_raw_read(const int addr, const uint8_t reg, /** * Read 8bit register from accelerometer. */ -int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int *data_ptr) +int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int *data_ptr) { int rv; @@ -189,8 +187,8 @@ int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, /** * Write 8bit register from accelerometer. */ -int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int data) +int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int data) { int rv; @@ -381,16 +379,16 @@ int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr, s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE) v = s->spoof_xyz; if (IS_ENABLED(CONFIG_ACCEL_FIFO)) { - struct ec_response_motion_sensor_data vector; + struct ec_response_motion_sensor_data + vector; vector.flags = 0; vector.data[X] = v[X]; vector.data[Y] = v[Y]; vector.data[Z] = v[Z]; vector.sensor_num = s - motion_sensors; - motion_sense_fifo_stage_data(&vector, s, - 3, - last_ts); + motion_sense_fifo_stage_data( + &vector, s, 3, last_ts); } else { motion_sense_push_raw_xyz(s); } @@ -859,7 +857,7 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v) } int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v, - int *val98_ptr) + int *val98_ptr) { int i, val, ret; @@ -903,8 +901,7 @@ void motion_orientation_update(const struct motion_sensor_t *s) } #endif -int bmi_list_activities(const struct motion_sensor_t *s, - uint32_t *enabled, +int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled, uint32_t *disabled) { struct bmi_drv_data_t *data = BMI_GET_DATA(s); -- cgit v1.2.1 From c2bb62f4a895b296ca6dcb0a48b0e1d312357248 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:08 -0600 Subject: board/puff/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea65e69bbb6aa50db3614afb97ae2c57fbc8d054 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728849 Reviewed-by: Jeremy Bettis --- board/puff/usb_pd_policy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/puff/usb_pd_policy.c b/board/puff/usb_pd_policy.c index 9b0a372400..a7d6e63243 100644 --- a/board/puff/usb_pd_policy.c +++ b/board/puff/usb_pd_policy.c @@ -19,9 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 8f772e6212ab28160d28b4003d50679daf509b11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:34 -0600 Subject: board/mithrax/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id671dda4e88a492c5280449cb07a5befd606013e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728460 Reviewed-by: Jeremy Bettis --- board/mithrax/fw_config.h | 40 ++++++++++++++-------------------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/board/mithrax/fw_config.h b/board/mithrax/fw_config.h index 4e9ba7f3c6..2883e68cc4 100644 --- a/board/mithrax/fw_config.h +++ b/board/mithrax/fw_config.h @@ -14,43 +14,31 @@ * Source of truth is the project/brya/mithrax/config.star configuration file. */ -enum ec_cfg_usb_db_type { - DB_USB3_PS8815 = 1, - DB_USB4_NCT3807 = 2 -}; +enum ec_cfg_usb_db_type { DB_USB3_PS8815 = 1, DB_USB4_NCT3807 = 2 }; enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_usb_mb_type { - MB_USB4_TBT = 0, - MB_USB3_NON_TBT = 1 -}; +enum ec_cfg_usb_mb_type { MB_USB4_TBT = 0, MB_USB3_NON_TBT = 1 }; -enum ec_cfg_stylus_type { - STYLUS_ABSENT = 0, - STYLUS_PRSENT = 1 -}; +enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 }; -enum ec_cfg_kb_backlight_type { - SOLID_COLOR = 0, - RGB = 1 -}; +enum ec_cfg_kb_backlight_type { SOLID_COLOR = 0, RGB = 1 }; union mithrax_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 3; - uint32_t wifi : 1; - enum ec_cfg_kb_backlight_type rgb : 1; - enum ec_cfg_stylus_type stylus : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t thermal : 2; - uint32_t table_mode : 1; - enum ec_cfg_usb_mb_type usb_mb : 3; - uint32_t reserved_1 : 16; + enum ec_cfg_usb_db_type usb_db : 3; + uint32_t wifi : 1; + enum ec_cfg_kb_backlight_type rgb : 1; + enum ec_cfg_stylus_type stylus : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t thermal : 2; + uint32_t table_mode : 1; + enum ec_cfg_usb_mb_type usb_mb : 3; + uint32_t reserved_1 : 16; }; uint32_t raw_value; }; -- cgit v1.2.1 From e7741b935eb2cb1cb592f14662f73a5a9db48db3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:13 -0600 Subject: chip/mec1322/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic55775e89a06bc82a33e25d882e54edcb59c8bb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729333 Reviewed-by: Jeremy Bettis --- chip/mec1322/pwm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c index ce94e50e7e..1eea58d2a3 100644 --- a/chip/mec1322/pwm.c +++ b/chip/mec1322/pwm.c @@ -24,8 +24,7 @@ void pwm_enable(enum pwm_channel ch, int enabled) if (enabled) { MEC1322_PWM_CFG(id) |= 0x1; if (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) - pwm_keep_awake_mask |= - MEC1322_PCR_EC_SLP_EN_PWM(id); + pwm_keep_awake_mask |= MEC1322_PCR_EC_SLP_EN_PWM(id); } else { MEC1322_PWM_CFG(id) &= ~0x1; pwm_keep_awake_mask &= ~MEC1322_PCR_EC_SLP_EN_PWM(id); @@ -66,9 +65,9 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=0 selects the 48MHz Ring Oscillator source * clock_low=1 selects the 100kHz_Clk source */ - MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ + MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ (active_low ? BIT(2) : 0) | - (clock_low ? BIT(1) : 0); + (clock_low ? BIT(1) : 0); } static void pwm_init(void) -- cgit v1.2.1 From 06ba0ecfa632ef1882618a942af31fc48924738f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:06 -0600 Subject: zephyr/shim/include/shimmed_task_id.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8780ecb3f9f17b18bec28d36b35eea73f060c6bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730848 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/shimmed_task_id.h | 244 ++++++++++++++++++---------------- 1 file changed, 131 insertions(+), 113 deletions(-) diff --git a/zephyr/shim/include/shimmed_task_id.h b/zephyr/shim/include/shimmed_task_id.h index 31df4daece..c03e3d6d3e 100644 --- a/zephyr/shim/include/shimmed_task_id.h +++ b/zephyr/shim/include/shimmed_task_id.h @@ -14,14 +14,13 @@ typedef uint8_t task_id_t; /* * Bitmask of port enable bits, expanding to a value like `BIT(0) | BIT(2) | 0`. */ -#define PD_INT_SHARED_PORT_MASK ( \ - FOR_EACH_NONEMPTY_TERM(BIT, (|), \ - IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED, (0)), \ - IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED, (1)), \ - IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED, (2)), \ - IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED, (3)), \ - ) 0 \ -) +#define PD_INT_SHARED_PORT_MASK \ + (FOR_EACH_NONEMPTY_TERM( \ + BIT, (|), \ + IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED, (0)), \ + IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED, (1)), \ + IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_2_SHARED, (2)), \ + IF_ENABLED(CONFIG_PLATFORM_EC_USB_PD_PORT_3_SHARED, (3)), ) 0) /* Highest priority on bottom -- same as in platform/ec. */ enum { @@ -64,104 +63,126 @@ enum { * CONFIG_HAS_TEST_TASKS and not CONFIG_SHIMMED_TASKS. */ #ifdef CONFIG_SHIMMED_TASKS -#define CROS_EC_TASK_LIST \ - COND_CODE_1(HAS_TASK_CHG_RAMP, \ - (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0, \ - CONFIG_TASK_CHG_RAMP_STACK_SIZE, \ - EC_TASK_CHG_RAMP_PRIO)), ()) \ - COND_CODE_1(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK, \ - (CROS_EC_TASK(USB_CHG, usb_charger_task_shared, 0, \ - CONFIG_TASK_USB_CHG_STACK_SIZE, \ - EC_TASK_USB_CHG_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_USB_CHG_P0, \ - (CROS_EC_TASK(USB_CHG_P0, usb_charger_task, 0, \ - CONFIG_TASK_USB_CHG_STACK_SIZE, \ - EC_TASK_USB_CHG_P0_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_USB_CHG_P1, \ - (CROS_EC_TASK(USB_CHG_P1, usb_charger_task, 0, \ - CONFIG_TASK_USB_CHG_STACK_SIZE, \ - EC_TASK_USB_CHG_P1_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_USB_CHG_P2, \ - (CROS_EC_TASK(USB_CHG_P2, usb_charger_task, 0, \ - CONFIG_TASK_USB_CHG_STACK_SIZE, \ - EC_TASK_USB_CHG_P2_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_USB_CHG_P3, \ - (CROS_EC_TASK(USB_CHG_P3, usb_charger_task, 0, \ - CONFIG_TASK_USB_CHG_STACK_SIZE, \ - EC_TASK_USB_CHG_P3_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_DPS, \ - (CROS_EC_TASK(DPS, dps_task, 0, \ - CONFIG_TASK_DPS_STACK_SIZE, \ - EC_TASK_DPS_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_CHARGER, \ - (CROS_EC_TASK(CHARGER, charger_task, 0, \ - CONFIG_TASK_CHARGER_STACK_SIZE, \ - EC_TASK_CHARGER_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_CHIPSET, \ - (CROS_EC_TASK(CHIPSET, chipset_task, 0, \ - CONFIG_TASK_CHIPSET_STACK_SIZE, \ - EC_TASK_CHIPSET_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_MOTIONSENSE, \ - (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0, \ - CONFIG_TASK_MOTIONSENSE_STACK_SIZE, \ - EC_TASK_MOTIONSENSE_PRIO)), ()) \ - IF_ENABLED(HAS_TASK_USB_MUX, \ - (CROS_EC_TASK(USB_MUX, usb_mux_task, 0, \ - CONFIG_TASK_USB_MUX_STACK_SIZE, \ - EC_TASK_USB_MUX_PRIO))) \ - COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_DEDICATED, \ - (CROS_EC_TASK(HOSTCMD, host_command_task, 0, \ - CONFIG_TASK_HOSTCMD_STACK_SIZE, \ - EC_TASK_HOSTCMD_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_KEYPROTO, \ - (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0, \ - CONFIG_TASK_KEYPROTO_STACK_SIZE, \ - EC_TASK_KEYPROTO_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_POWERBTN, \ - (CROS_EC_TASK(POWERBTN, power_button_task, 0, \ - CONFIG_TASK_POWERBTN_STACK_SIZE, \ - EC_TASK_POWERBTN_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_KEYSCAN, \ - (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0, \ - CONFIG_TASK_KEYSCAN_STACK_SIZE, \ - EC_TASK_KEYSCAN_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_C0, \ - (CROS_EC_TASK(PD_C0, pd_task, 0, \ - CONFIG_TASK_PD_STACK_SIZE, \ - EC_TASK_PD_C0_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_C1, \ - (CROS_EC_TASK(PD_C1, pd_task, 0, \ - CONFIG_TASK_PD_STACK_SIZE, \ - EC_TASK_PD_C1_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_C2, \ - (CROS_EC_TASK(PD_C2, pd_task, 0, \ - CONFIG_TASK_PD_STACK_SIZE, \ - EC_TASK_PD_C2_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_C3, \ - (CROS_EC_TASK(PD_C3, pd_task, 0, \ - CONFIG_TASK_PD_STACK_SIZE, \ - EC_TASK_PD_C3_PRIO)), ()) \ - IF_ENABLED(CONFIG_HAS_TASK_PD_INT_SHARED, \ - (CROS_EC_TASK(PD_INT_SHARED, pd_shared_alert_task, \ - PD_INT_SHARED_PORT_MASK, \ - CONFIG_TASK_PD_INT_STACK_SIZE, \ - EC_TASK_PD_INT_SHARED_PRIO))) \ - COND_CODE_1(HAS_TASK_PD_INT_C0, \ - (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \ - CONFIG_TASK_PD_INT_STACK_SIZE, \ - EC_TASK_PD_INT_C0_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_INT_C1, \ - (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \ - CONFIG_TASK_PD_INT_STACK_SIZE, \ - EC_TASK_PD_INT_C1_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_INT_C2, \ - (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \ - CONFIG_TASK_PD_INT_STACK_SIZE, \ - EC_TASK_PD_INT_C2_PRIO)), ()) \ - COND_CODE_1(HAS_TASK_PD_INT_C3, \ - (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \ - CONFIG_TASK_PD_INT_STACK_SIZE, \ - EC_TASK_PD_INT_C3_PRIO)), ()) +#define CROS_EC_TASK_LIST \ + COND_CODE_1(HAS_TASK_CHG_RAMP, \ + (CROS_EC_TASK(CHG_RAMP, chg_ramp_task, 0, \ + CONFIG_TASK_CHG_RAMP_STACK_SIZE, \ + EC_TASK_CHG_RAMP_PRIO)), \ + ()) \ + COND_CODE_1(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK, \ + (CROS_EC_TASK(USB_CHG, usb_charger_task_shared, 0, \ + CONFIG_TASK_USB_CHG_STACK_SIZE, \ + EC_TASK_USB_CHG_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_USB_CHG_P0, \ + (CROS_EC_TASK(USB_CHG_P0, usb_charger_task, 0, \ + CONFIG_TASK_USB_CHG_STACK_SIZE, \ + EC_TASK_USB_CHG_P0_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_USB_CHG_P1, \ + (CROS_EC_TASK(USB_CHG_P1, usb_charger_task, 0, \ + CONFIG_TASK_USB_CHG_STACK_SIZE, \ + EC_TASK_USB_CHG_P1_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_USB_CHG_P2, \ + (CROS_EC_TASK(USB_CHG_P2, usb_charger_task, 0, \ + CONFIG_TASK_USB_CHG_STACK_SIZE, \ + EC_TASK_USB_CHG_P2_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_USB_CHG_P3, \ + (CROS_EC_TASK(USB_CHG_P3, usb_charger_task, 0, \ + CONFIG_TASK_USB_CHG_STACK_SIZE, \ + EC_TASK_USB_CHG_P3_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_DPS, \ + (CROS_EC_TASK(DPS, dps_task, 0, \ + CONFIG_TASK_DPS_STACK_SIZE, \ + EC_TASK_DPS_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_CHARGER, \ + (CROS_EC_TASK(CHARGER, charger_task, 0, \ + CONFIG_TASK_CHARGER_STACK_SIZE, \ + EC_TASK_CHARGER_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_CHIPSET, \ + (CROS_EC_TASK(CHIPSET, chipset_task, 0, \ + CONFIG_TASK_CHIPSET_STACK_SIZE, \ + EC_TASK_CHIPSET_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_MOTIONSENSE, \ + (CROS_EC_TASK(MOTIONSENSE, motion_sense_task, 0, \ + CONFIG_TASK_MOTIONSENSE_STACK_SIZE, \ + EC_TASK_MOTIONSENSE_PRIO)), \ + ()) \ + IF_ENABLED(HAS_TASK_USB_MUX, \ + (CROS_EC_TASK(USB_MUX, usb_mux_task, 0, \ + CONFIG_TASK_USB_MUX_STACK_SIZE, \ + EC_TASK_USB_MUX_PRIO))) \ + COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_DEDICATED, \ + (CROS_EC_TASK(HOSTCMD, host_command_task, 0, \ + CONFIG_TASK_HOSTCMD_STACK_SIZE, \ + EC_TASK_HOSTCMD_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_KEYPROTO, \ + (CROS_EC_TASK(KEYPROTO, keyboard_protocol_task, 0, \ + CONFIG_TASK_KEYPROTO_STACK_SIZE, \ + EC_TASK_KEYPROTO_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_POWERBTN, \ + (CROS_EC_TASK(POWERBTN, power_button_task, 0, \ + CONFIG_TASK_POWERBTN_STACK_SIZE, \ + EC_TASK_POWERBTN_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_KEYSCAN, \ + (CROS_EC_TASK(KEYSCAN, keyboard_scan_task, 0, \ + CONFIG_TASK_KEYSCAN_STACK_SIZE, \ + EC_TASK_KEYSCAN_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_C0, \ + (CROS_EC_TASK(PD_C0, pd_task, 0, \ + CONFIG_TASK_PD_STACK_SIZE, \ + EC_TASK_PD_C0_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_C1, \ + (CROS_EC_TASK(PD_C1, pd_task, 0, \ + CONFIG_TASK_PD_STACK_SIZE, \ + EC_TASK_PD_C1_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_C2, \ + (CROS_EC_TASK(PD_C2, pd_task, 0, \ + CONFIG_TASK_PD_STACK_SIZE, \ + EC_TASK_PD_C2_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_C3, \ + (CROS_EC_TASK(PD_C3, pd_task, 0, \ + CONFIG_TASK_PD_STACK_SIZE, \ + EC_TASK_PD_C3_PRIO)), \ + ()) \ + IF_ENABLED(CONFIG_HAS_TASK_PD_INT_SHARED, \ + (CROS_EC_TASK(PD_INT_SHARED, pd_shared_alert_task, \ + PD_INT_SHARED_PORT_MASK, \ + CONFIG_TASK_PD_INT_STACK_SIZE, \ + EC_TASK_PD_INT_SHARED_PRIO))) \ + COND_CODE_1(HAS_TASK_PD_INT_C0, \ + (CROS_EC_TASK(PD_INT_C0, pd_interrupt_handler_task, 0, \ + CONFIG_TASK_PD_INT_STACK_SIZE, \ + EC_TASK_PD_INT_C0_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_INT_C1, \ + (CROS_EC_TASK(PD_INT_C1, pd_interrupt_handler_task, 1, \ + CONFIG_TASK_PD_INT_STACK_SIZE, \ + EC_TASK_PD_INT_C1_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_INT_C2, \ + (CROS_EC_TASK(PD_INT_C2, pd_interrupt_handler_task, 2, \ + CONFIG_TASK_PD_INT_STACK_SIZE, \ + EC_TASK_PD_INT_C2_PRIO)), \ + ()) \ + COND_CODE_1(HAS_TASK_PD_INT_C3, \ + (CROS_EC_TASK(PD_INT_C3, pd_interrupt_handler_task, 3, \ + CONFIG_TASK_PD_INT_STACK_SIZE, \ + EC_TASK_PD_INT_C3_PRIO)), \ + ()) #elif defined(CONFIG_HAS_TEST_TASKS) #include "shimmed_test_tasks.h" /* @@ -191,7 +212,7 @@ enum { TASK_ID_IDLE = -1, /* We don't shim the idle task */ CROS_EC_TASK_LIST #ifdef TEST_BUILD - TASK_ID_TEST_RUNNER, + TASK_ID_TEST_RUNNER, #endif TASK_ID_COUNT, TASK_ID_INVALID = 0xff, /* Unable to find the task */ @@ -203,20 +224,17 @@ enum { * Additional task IDs for features that runs on non shimmed threads, * task_get_current() needs to be updated to identify these ones. */ -#define CROS_EC_EXTRA_TASKS(fn) \ +#define CROS_EC_EXTRA_TASKS(fn) \ COND_CODE_1(CONFIG_TASK_HOSTCMD_THREAD_MAIN, (fn(HOSTCMD)), ()) \ fn(SYSWORKQ) #define EXTRA_TASK_INTERNAL_ID(name) EXTRA_TASK_##name, enum { - CROS_EC_EXTRA_TASKS(EXTRA_TASK_INTERNAL_ID) - EXTRA_TASK_COUNT, + CROS_EC_EXTRA_TASKS(EXTRA_TASK_INTERNAL_ID) EXTRA_TASK_COUNT, }; #define EXTRA_TASK_ID(name) \ TASK_ID_##name = (TASK_ID_COUNT + EXTRA_TASK_##name), -enum { - CROS_EC_EXTRA_TASKS(EXTRA_TASK_ID) -}; +enum { CROS_EC_EXTRA_TASKS(EXTRA_TASK_ID) }; #endif /* __CROS_EC_SHIMMED_TASK_ID_H */ -- cgit v1.2.1 From 0d25ee0c10b7de65f6cf351a6ebe36876aea1cbe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:52 -0600 Subject: test/online_calibration.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iceeab0d9294d27707635d01ea04a51216224e9cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730516 Reviewed-by: Jeremy Bettis --- test/online_calibration.c | 58 ++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/test/online_calibration.c b/test/online_calibration.c index 1b3abf51bc..8a9215caa3 100644 --- a/test/online_calibration.c +++ b/test/online_calibration.c @@ -48,17 +48,14 @@ static struct accelgyro_drv mock_sensor_driver = { .read_temp = mock_read_temp, }; -static struct accel_cal_algo base_accel_cal_algos[] = { - { - .newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), - FLOAT_TO_FP(0.25f), - FLOAT_TO_FP(1.0e-8f), 100), - } -}; +static struct accel_cal_algo base_accel_cal_algos[] = { { + .newton_fit = NEWTON_FIT(4, 15, FLOAT_TO_FP(0.01f), FLOAT_TO_FP(0.25f), + FLOAT_TO_FP(1.0e-8f), 100), +} }; static struct accel_cal base_accel_cal_data = { - .still_det = STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, - 5), + .still_det = + STILL_DET(FLOAT_TO_FP(0.00025f), 800 * MSEC, 1200 * MSEC, 5), .algos = base_accel_cal_algos, .num_temp_windows = ARRAY_SIZE(base_accel_cal_algos), }; @@ -68,9 +65,8 @@ static struct mag_cal_t lid_mag_cal_data; static bool next_accel_cal_accumulate_result; static fpv3_t next_accel_cal_bias; -bool accel_cal_accumulate( - struct accel_cal *cal, uint32_t sample_time, fp_t x, fp_t y, fp_t z, - fp_t temp) +bool accel_cal_accumulate(struct accel_cal *cal, uint32_t sample_time, fp_t x, + fp_t y, fp_t z, fp_t temp) { if (next_accel_cal_accumulate_result) { cal->bias[X] = next_accel_cal_bias[X]; @@ -110,8 +106,8 @@ static int test_read_temp_on_stage(void) mock_read_temp_results = &expected; data.sensor_num = BASE; - rc = online_calibration_process_data( - &data, &motion_sensors[0], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[0], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(expected.used_count, 1, "%d"); @@ -128,12 +124,12 @@ static int test_read_temp_from_cache_on_stage(void) mock_read_temp_results = &expected; data.sensor_num = BASE; - rc = online_calibration_process_data( - &data, &motion_sensors[0], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[0], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); - rc = online_calibration_process_data( - &data, &motion_sensors[0], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[0], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(expected.used_count, 1, "%d"); @@ -150,13 +146,13 @@ static int test_read_temp_twice_after_cache_stale(void) mock_read_temp_results = &expected; data.sensor_num = BASE; - rc = online_calibration_process_data( - &data, &motion_sensors[0], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[0], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); sleep(2); - rc = online_calibration_process_data( - &data, &motion_sensors[0], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[0], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(expected.used_count, 2, "%d"); @@ -176,17 +172,17 @@ static int test_new_calibration_value(void) next_accel_cal_accumulate_result = false; data.sensor_num = BASE; - rc = online_calibration_process_data( - &data, &motion_sensors[BASE], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[BASE], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(online_calibration_has_new_values(), false, "%d"); next_accel_cal_accumulate_result = true; - next_accel_cal_bias[X] = 0.01f; /* expect: 81 */ - next_accel_cal_bias[Y] = -0.02f; /* expect: -163 */ - next_accel_cal_bias[Z] = 0; /* expect: 0 */ - rc = online_calibration_process_data( - &data, &motion_sensors[BASE], __hw_clock_source_read()); + next_accel_cal_bias[X] = 0.01f; /* expect: 81 */ + next_accel_cal_bias[Y] = -0.02f; /* expect: -163 */ + next_accel_cal_bias[Z] = 0; /* expect: 0 */ + rc = online_calibration_process_data(&data, &motion_sensors[BASE], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(online_calibration_has_new_values(), true, "%d"); @@ -216,8 +212,8 @@ int test_mag_reading_updated_cal(void) init_mag_cal(&expected_results); mag_cal_update(&expected_results, test_values); - rc = online_calibration_process_data( - &data, &motion_sensors[LID], __hw_clock_source_read()); + rc = online_calibration_process_data(&data, &motion_sensors[LID], + __hw_clock_source_read()); TEST_EQ(rc, EC_SUCCESS, "%d"); TEST_EQ(expected_results.kasa_fit.nsamples, lid_mag_cal_data.kasa_fit.nsamples, "%d"); -- cgit v1.2.1 From c869dc67089091789c89df5b8e905195a12c71eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:40 -0600 Subject: zephyr/emul/tcpc/emul_ps8xxx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I899ae064dc8fc60c754d9a0c80df69ff8bb63eda Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730702 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_ps8xxx.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c index 2fc372c9a7..9a509e6afc 100644 --- a/zephyr/emul/tcpc/emul_ps8xxx.c +++ b/zephyr/emul/tcpc/emul_ps8xxx.c @@ -21,7 +21,7 @@ LOG_MODULE_REGISTER(ps8xxx_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include "driver/tcpm/ps8xxx.h" -#define PS8XXX_REG_MUX_IN_HPD_ASSERTION MUX_IN_HPD_ASSERTION_REG +#define PS8XXX_REG_MUX_IN_HPD_ASSERTION MUX_IN_HPD_ASSERTION_REG /** Run-time data used by the emulator */ struct ps8xxx_emul_data { @@ -164,10 +164,10 @@ struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul, * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ -static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_read_byte( - const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, uint8_t *val, int bytes) +static enum tcpci_emul_ops_resp +ps8xxx_emul_tcpci_read_byte(const struct emul *emul, + const struct tcpci_emul_dev_ops *ops, int reg, + uint8_t *val, int bytes) { uint16_t reg_val; @@ -206,10 +206,10 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_read_byte( * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ -static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_write_byte( - const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, uint8_t val, int bytes) +static enum tcpci_emul_ops_resp +ps8xxx_emul_tcpci_write_byte(const struct emul *emul, + const struct tcpci_emul_dev_ops *ops, int reg, + uint8_t val, int bytes) { uint16_t prod_id; @@ -252,10 +252,10 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_write_byte( * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ -static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_handle_write( - const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, int msg_len) +static enum tcpci_emul_ops_resp +ps8xxx_emul_tcpci_handle_write(const struct emul *emul, + const struct tcpci_emul_dev_ops *ops, int reg, + int msg_len) { uint16_t prod_id; @@ -286,7 +286,7 @@ static enum tcpci_emul_ops_resp ps8xxx_emul_tcpci_handle_write( * @param ops Pointer to device operations structure */ static void ps8xxx_emul_tcpci_reset(const struct emul *emul, - struct tcpci_emul_dev_ops *ops) + struct tcpci_emul_dev_ops *ops) { tcpci_emul_set_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31); tcpci_emul_set_reg(emul, PS8XXX_REG_MUX_IN_HPD_ASSERTION, 0x00); @@ -535,7 +535,7 @@ static int ps8xxx_emul_init(const struct emul *emul, return ret; } -#define PS8XXX_EMUL(n) \ +#define PS8XXX_EMUL(n) \ static struct ps8xxx_emul_data ps8xxx_emul_data_##n = { \ .prod_id = PS8805_PRODUCT_ID, \ .p0_data = { \ @@ -550,8 +550,8 @@ static int ps8xxx_emul_init(const struct emul *emul, .write_byte = ps8xxx_emul_write_byte, \ .read_byte = ps8xxx_emul_read_byte, \ }, \ - }; \ - \ + }; \ + \ static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = { \ .tcpci_emul = DT_LABEL(DT_INST_PHANDLE(n, tcpci_i2c)), \ .p0_cfg = { \ @@ -572,9 +572,9 @@ static int ps8xxx_emul_init(const struct emul *emul, .data = &ps8xxx_emul_data_##n.gpio_data, \ .addr = DT_INST_PROP(n, gpio_i2c_addr), \ }, \ - }; \ - EMUL_DEFINE(ps8xxx_emul_init, DT_DRV_INST(n), \ - &ps8xxx_emul_cfg_##n, &ps8xxx_emul_data_##n) + }; \ + EMUL_DEFINE(ps8xxx_emul_init, DT_DRV_INST(n), &ps8xxx_emul_cfg_##n, \ + &ps8xxx_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL) -- cgit v1.2.1 From 7fedd77fd98accb8a89f66535ea801fd7740225f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:59 -0600 Subject: common/battery_v1.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2fa05110eadc3f916710aeca642310494bc218e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729590 Reviewed-by: Jeremy Bettis --- common/battery_v1.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/common/battery_v1.c b/common/battery_v1.c index d6fc42affb..d0920d30b4 100644 --- a/common/battery_v1.c +++ b/common/battery_v1.c @@ -15,8 +15,8 @@ #include "printf.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Returns zero if every item was updated. */ int update_static_battery_info(void) @@ -136,7 +136,8 @@ void update_dynamic_battery_info(void) * Don't report zero charge, as that has special meaning * to Chrome OS powerd. */ - if (curr->batt.remaining_capacity == 0 && !curr->batt_is_charging) + if (curr->batt.remaining_capacity == 0 && + !curr->batt_is_charging) *memmap_cap = 1; else *memmap_cap = curr->batt.remaining_capacity; @@ -156,7 +157,7 @@ void update_dynamic_battery_info(void) tmp |= EC_BATT_FLAG_LEVEL_CRITICAL; tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING : - EC_BATT_FLAG_DISCHARGING; + EC_BATT_FLAG_DISCHARGING; /* Tell the AP to re-read battery status if charge state changes */ if (*memmap_flags != tmp) -- cgit v1.2.1 From 5e2a265bfc888e0b50ee1ecd774cda5e3ff89fbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:12 -0600 Subject: driver/sync.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I74ff4f3d0ec443bb95119287d02aa7c4c1fa3d78 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730066 Reviewed-by: Jeremy Bettis --- driver/sync.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/driver/sync.c b/driver/sync.c index 3dc9c98ece..bedacbe5fc 100644 --- a/driver/sync.c +++ b/driver/sync.c @@ -17,8 +17,8 @@ #include "task.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args) #ifndef CONFIG_ACCEL_FIFO #error This driver needs CONFIG_ACCEL_FIFO @@ -35,7 +35,7 @@ static struct queue const sync_event_queue = struct sync_event_t next_event; struct ec_response_motion_sensor_data vector = { .flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO, - .data = {0, 0, 0} + .data = { 0, 0, 0 } }; int sync_enabled; @@ -51,8 +51,8 @@ static int sync_read(const struct motion_sensor_t *s, intv3_t v) * still depends on being able to set this to 0 to disable it, we'll just use * non 0 rate values as an enable boolean. */ -static int sync_set_data_rate(const struct motion_sensor_t *s, - int rate, int roundup) +static int sync_set_data_rate(const struct motion_sensor_t *s, int rate, + int roundup) { sync_enabled = !!rate; CPRINTF("sync event driver enabling=%d\n", sync_enabled); @@ -88,8 +88,8 @@ static int motion_irq_handler(struct motion_sensor_t *s, uint32_t *event) while (queue_remove_unit(&sync_event_queue, &sync_event)) { vector.data[X] = sync_event.counter; - motion_sense_fifo_stage_data( - &vector, s, 1, sync_event.timestamp); + motion_sense_fifo_stage_data(&vector, s, 1, + sync_event.timestamp); } motion_sense_fifo_commit_data(); @@ -118,9 +118,7 @@ static int command_sync(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(sync, command_sync, - "[count]", - "Simulates sync events"); +DECLARE_CONSOLE_COMMAND(sync, command_sync, "[count]", "Simulates sync events"); #endif const struct accelgyro_drv sync_drv = { -- cgit v1.2.1 From cf66b36b1804545b0b05d957f6ba05d91037426a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:09 -0600 Subject: test/rgb_keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I83ced4caafcd75bf9d5f49372a82a021903562cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730518 Reviewed-by: Jeremy Bettis --- test/rgb_keyboard.c | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/test/rgb_keyboard.c b/test/rgb_keyboard.c index a8da437f7c..8419b84ab4 100644 --- a/test/rgb_keyboard.c +++ b/test/rgb_keyboard.c @@ -52,11 +52,8 @@ const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; const uint8_t rgbkbd_map[] = { - RGBKBD_DELM, - RGBKBD_COORD(1, 2), RGBKBD_DELM, - RGBKBD_COORD(3, 4), RGBKBD_COORD(5, 6), RGBKBD_DELM, - RGBKBD_DELM, - RGBKBD_DELM, + RGBKBD_DELM, RGBKBD_COORD(1, 2), RGBKBD_DELM, RGBKBD_COORD(3, 4), + RGBKBD_COORD(5, 6), RGBKBD_DELM, RGBKBD_DELM, RGBKBD_DELM, }; const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map); @@ -72,9 +69,13 @@ static struct rgbkbd_mock { uint32_t gcc_level; } mock_state; -__override void board_kblight_init(void) {} +__override void board_kblight_init(void) +{ +} -__override void board_kblight_shutdown(void) {} +__override void board_kblight_shutdown(void) +{ +} void before_test(void) { @@ -106,7 +107,6 @@ static int test_drv_set_color(struct rgbkbd *ctx, uint8_t offset, return EC_SUCCESS; } - static int test_drv_set_scale(struct rgbkbd *ctx, uint8_t offset, struct rgb_s scale, uint8_t len) { @@ -130,8 +130,8 @@ static int test_rgbkbd_map(void) rgbkbd_init_lookup_table(); led.u8 = rgbkbd_map[rgbkbd_table[0]]; - zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), - RGBKBD_DELM, "key[0] -> None"); + zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM, + "key[0] -> None"); led.u8 = rgbkbd_map[rgbkbd_table[1]]; zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), @@ -145,12 +145,12 @@ static int test_rgbkbd_map(void) RGBKBD_COORD(5, 6), "key[2] -> LED(5,6)"); led.u8 = rgbkbd_map[rgbkbd_table[3]]; - zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), - RGBKBD_DELM, "key[3] -> None"); + zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM, + "key[3] -> None"); led.u8 = rgbkbd_map[rgbkbd_table[4]]; - zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), - RGBKBD_DELM, "key[4] -> None"); + zassert_equal(RGBKBD_COORD(led.coord.x, led.coord.y), RGBKBD_DELM, + "key[4] -> None"); return EC_SUCCESS; } @@ -220,10 +220,10 @@ static int test_rgbkbd_console_command(void) char buf[8]; int i, x, y, r, c; uint8_t offset; - char *argv_demo[] = {"rgbk", "demo", "0"}; - char *argv_gcc[] = {"rgbk", "100"}; - char *argv_color[] = {"rgbk", buf, "0x010203"}; - char *argv_all[] = {"rgbk", "all", "0x010203"}; + char *argv_demo[] = { "rgbk", "demo", "0" }; + char *argv_gcc[] = { "rgbk", "100" }; + char *argv_color[] = { "rgbk", buf, "0x010203" }; + char *argv_all[] = { "rgbk", "all", "0x010203" }; /* Test 'rgbk demo 0'. */ before_test(); @@ -248,8 +248,8 @@ static int test_rgbkbd_console_command(void) offset = rgbkbd_vsize * x + y; sprintf(buf, "%d,%d", x, y); argc = ARRAY_SIZE(argv_color); - zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, - "rgbk %s 0x010203", buf); + zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 0x010203", + buf); zassert_equal(ctx->buf[offset].r, 1, "R = 1"); zassert_equal(ctx->buf[offset].g, 2, "G = 2"); zassert_equal(ctx->buf[offset].b, 3, "B = 3"); @@ -261,8 +261,8 @@ static int test_rgbkbd_console_command(void) y = -1; sprintf(buf, "%d,%d", x, y); argc = ARRAY_SIZE(argv_color); - zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, - "rgbk %s 1 2 3", buf); + zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3", + buf); for (r = 0; r < rgbkbd_vsize; r++) { offset = rgbkbd_vsize * x + r; zassert_equal(ctx->buf[offset].r, 1, "R = 1"); @@ -276,8 +276,8 @@ static int test_rgbkbd_console_command(void) y = 1; sprintf(buf, "%d,%d", x, y); argc = ARRAY_SIZE(argv_color); - zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, - "rgbk %s 1 2 3", buf); + zassert_equal(cc_rgb(argc, argv_color), EC_SUCCESS, "rgbk %s 1 2 3", + buf); for (c = 0; c < rgbkbd_hsize; c++) { ctx = &rgbkbds[c / rgbkbds[0].cfg->col_len]; offset = rgbkbd_vsize * (c % ctx->cfg->col_len) + y; @@ -340,7 +340,7 @@ static int test_rgbkbd_rotate_color(void) static int test_rgbkbd_demo_flow(void) { struct rgb_s copy[ARRAY_SIZE(rgbkbds)][RGB_GRID0_COL * RGB_GRID0_ROW]; - char *argv_demo[] = {"rgbk", "demo", "1"}; + char *argv_demo[] = { "rgbk", "demo", "1" }; struct rgb_s *p; int argc; struct rgbkbd *ctx; -- cgit v1.2.1 From 13e3ad21e0003042c662f46fffb8aa6cca2cc0c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:06 -0600 Subject: board/garg/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b0a2ec6794b0eb0937c0fe1d31e861925a3b7ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728391 Reviewed-by: Jeremy Bettis --- board/garg/led.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/board/garg/led.c b/board/garg/led.c index bc77efe9b9..d232101513 100644 --- a/board/garg/led.c +++ b/board/garg/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100; /* Garg: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From d493acf537b2a88f7090e7d269242ea8d9e037d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:09 -0600 Subject: driver/stm_mems_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I601b6d77a7bb0783689a23c2e46cc9e7e6208442 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730065 Reviewed-by: Jeremy Bettis --- driver/stm_mems_common.h | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/driver/stm_mems_common.h b/driver/stm_mems_common.h index 1c0afbc9f4..75377cabbf 100644 --- a/driver/stm_mems_common.h +++ b/driver/stm_mems_common.h @@ -15,25 +15,25 @@ #include "i2c.h" /* X, Y, Z axis data len */ -#define OUT_XYZ_SIZE 6 +#define OUT_XYZ_SIZE 6 -#define ST_NORMALIZE_RATE(_fs) (1 << __fls(_fs)) +#define ST_NORMALIZE_RATE(_fs) (1 << __fls(_fs)) -#define FIFO_BUFFER_NUM_PATTERN 8 +#define FIFO_BUFFER_NUM_PATTERN 8 /* Define number of data to be read from FIFO each time * It must be a multiple of OUT_XYZ_SIZE. * In case of LSM6DSM FIFO contains pattern depending ODR * of Acc/gyro, be sure that FIFO can contains almost * FIFO_BUFFER_NUM_PATTERNpattern */ -#define FIFO_READ_LEN (FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE) +#define FIFO_READ_LEN (FIFO_BUFFER_NUM_PATTERN * OUT_XYZ_SIZE) /** * Read single register */ static inline int st_raw_read8(const int port, - const uint16_t i2c_spi_addr_flags, - const int reg, int *data_ptr) + const uint16_t i2c_spi_addr_flags, const int reg, + int *data_ptr) { /* TODO: Implement SPI interface support */ return i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr); @@ -53,18 +53,16 @@ static inline int st_raw_write8(const int port, /** * st_raw_read_n - Read n bytes for read */ -int st_raw_read_n(const int port, - const uint16_t i2c_spi_addr_flags, +int st_raw_read_n(const int port, const uint16_t i2c_spi_addr_flags, const uint8_t reg, uint8_t *data_ptr, const int len); /** * st_raw_read_n_noinc - Read n bytes for read (no auto inc address) */ -int st_raw_read_n_noinc(const int port, - const uint16_t i2c_spi_addr_flags, +int st_raw_read_n_noinc(const int port, const uint16_t i2c_spi_addr_flags, const uint8_t reg, uint8_t *data_ptr, const int len); - /** +/** * st_write_data_with_mask - Write register with mask * @s: Motion sensor pointer * @reg: Device register @@ -72,9 +70,9 @@ int st_raw_read_n_noinc(const int port, * @data: Data pointer */ int st_write_data_with_mask(const struct motion_sensor_t *s, int reg, - uint8_t mask, uint8_t data); + uint8_t mask, uint8_t data); - /** +/** * st_get_resolution - Get bit resolution * @s: Motion sensor pointer */ @@ -86,8 +84,8 @@ int st_get_resolution(const struct motion_sensor_t *s); * @offset: offset vector * @temp: Temp */ -int st_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, int16_t temp); +int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp); /** * st_get_offset - Get data offset @@ -95,8 +93,8 @@ int st_set_offset(const struct motion_sensor_t *s, * @offset: offset vector * @temp: Temp */ -int st_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp); +int st_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); /** * st_get_data_rate - Get data rate (ODR) @@ -115,8 +113,8 @@ void st_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data); /* Internal data structure for sensors */ struct stprivate_data { struct accelgyro_saved_data_t base; - uint8_t enabled_activities; - uint8_t disabled_activities; + uint8_t enabled_activities; + uint8_t disabled_activities; int16_t offset[3]; uint8_t resol; }; -- cgit v1.2.1 From f834fc993c4a2b0df7bc32991aed72b7f4395ba3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:39 -0600 Subject: include/lb_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic699fc2c12d3ac33a800b12de3399a84bdeb95ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730311 Reviewed-by: Jeremy Bettis --- include/lb_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/lb_common.h b/include/lb_common.h index 327c810cad..1cf6caa35a 100644 --- a/include/lb_common.h +++ b/include/lb_common.h @@ -38,4 +38,4 @@ void lb_hc_cmd_reg(const struct ec_params_lightbar *in); */ int lb_power(int enabled); -#endif /* __CROS_EC_LB_COMMON_H */ +#endif /* __CROS_EC_LB_COMMON_H */ -- cgit v1.2.1 From 75c2d40d68094a223e6bd40b74e95d9f4cb330b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:50 -0600 Subject: test/test_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2fcae6523dc95785c881f73376d1967293142f43 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730547 Reviewed-by: Jeremy Bettis --- test/test_config.h | 83 +++++++++++++++++++++++++----------------------------- 1 file changed, 38 insertions(+), 45 deletions(-) diff --git a/test/test_config.h b/test/test_config.h index afd72ce1d2..67615182b3 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -169,17 +169,13 @@ #define CONFIG_MKBP_USE_GPIO #endif -#if defined(CONFIG_ONLINE_CALIB) && \ - !defined(CONFIG_TEMP_CACHE_STALE_THRES) +#if defined(CONFIG_ONLINE_CALIB) && !defined(CONFIG_TEMP_CACHE_STALE_THRES) #define CONFIG_TEMP_CACHE_STALE_THRES (1 * SECOND) #endif /* CONFIG_ONLINE_CALIB && !CONFIG_TEMP_CACHE_STALE_THRES */ -#if defined(CONFIG_ONLINE_CALIB) || \ - defined(TEST_BODY_DETECTION) || \ - defined(TEST_MOTION_ANGLE) || \ - defined(TEST_MOTION_ANGLE_TABLET) || \ - defined(TEST_MOTION_LID) || \ - defined(TEST_MOTION_SENSE_FIFO) +#if defined(CONFIG_ONLINE_CALIB) || defined(TEST_BODY_DETECTION) || \ + defined(TEST_MOTION_ANGLE) || defined(TEST_MOTION_ANGLE_TABLET) || \ + defined(TEST_MOTION_LID) || defined(TEST_MOTION_SENSE_FIFO) enum sensor_id { BASE, LID, @@ -195,15 +191,14 @@ enum sensor_id { #endif #if defined(TEST_MOTION_ANGLE) -#define CONFIG_ACCEL_FORCE_MODE_MASK \ +#define CONFIG_ACCEL_FORCE_MODE_MASK \ ((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \ (1 << CONFIG_LID_ANGLE_SENSOR_LID)) #define CONFIG_ACCEL_STD_REF_FRAME_OLD #endif -#if defined(TEST_MOTION_ANGLE_TABLET) || \ - defined(TEST_MOTION_LID) -#define CONFIG_ACCEL_FORCE_MODE_MASK \ +#if defined(TEST_MOTION_ANGLE_TABLET) || defined(TEST_MOTION_LID) +#define CONFIG_ACCEL_FORCE_MODE_MASK \ ((1 << CONFIG_LID_ANGLE_SENSOR_BASE) | \ (1 << CONFIG_LID_ANGLE_SENSOR_LID)) #endif @@ -216,19 +211,21 @@ enum sensor_id { #ifdef TEST_RMA_AUTH /* Test server public and private keys */ -#define RMA_KEY_BLOB { \ - 0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, \ - 0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd, \ - 0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5, \ - 0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f, \ - 0x10 \ +#define RMA_KEY_BLOB \ + { \ + 0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3, \ + 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, \ + 0xa8, 0xeb, 0x7e, 0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, \ + 0x8a, 0x0f, 0x28, 0x3f, 0x10 \ } -#define RMA_TEST_SERVER_PRIVATE_KEY { \ - 0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, \ - 0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07, \ - 0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3, \ - 0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad} +#define RMA_TEST_SERVER_PRIVATE_KEY \ + { \ + 0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd, \ + 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, \ + 0x7b, 0x52, 0x8c, 0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, \ + 0x65, 0xb4, 0x31, 0xad \ + } #define RMA_TEST_SERVER_KEY_ID 0x10 #define CONFIG_BASE32 @@ -290,8 +287,8 @@ int board_discharge_on_ac(int enabled); #define I2C_PORT_BATTERY 0 #define I2C_PORT_CHARGER 0 #define CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION -#undef CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT -#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (2*SECOND) +#undef CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT +#define CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT (2 * SECOND) #endif #ifdef TEST_THERMAL @@ -361,10 +358,8 @@ int ncp15wb_calculate_temp(uint16_t adc); #define CONFIG_USB_PD_ONLY_FIXED_PDOS #endif -#if defined(TEST_USB_SM_FRAMEWORK_H3) || \ - defined(TEST_USB_SM_FRAMEWORK_H2) || \ - defined(TEST_USB_SM_FRAMEWORK_H1) || \ - defined(TEST_USB_SM_FRAMEWORK_H0) +#if defined(TEST_USB_SM_FRAMEWORK_H3) || defined(TEST_USB_SM_FRAMEWORK_H2) || \ + defined(TEST_USB_SM_FRAMEWORK_H1) || defined(TEST_USB_SM_FRAMEWORK_H0) #define CONFIG_TEST_SM #endif @@ -457,8 +452,7 @@ int ncp15wb_calculate_temp(uint16_t adc); #endif /* TEST_USB_PE_DRP || TEST_USB_PE_DRP_NOEXTENDED */ /* Common TypeC tests defines */ -#if defined(TEST_USB_TYPEC_VPD) || \ - defined(TEST_USB_TYPEC_CTVPD) +#if defined(TEST_USB_TYPEC_VPD) || defined(TEST_USB_TYPEC_CTVPD) #define CONFIG_USB_PID 0x5036 #define VPD_HW_VERSION 0x0001 #define VPD_FW_VERSION 0x0001 @@ -629,18 +623,17 @@ int ncp15wb_calculate_temp(uint16_t adc); #define CONFIG_RSA #define CONFIG_RWSIG_TYPE_RWSIG #define CONFIG_RW_B -#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF -#undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) -#undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE) -#define CONFIG_RW_A_SIGN_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define CONFIG_RW_B_SIGN_STORAGE_OFF (CONFIG_RW_B_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#undef CONFIG_RW_SIZE +#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF +#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE) +#define CONFIG_RW_A_SIGN_STORAGE_OFF \ + (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_SIGN_STORAGE_OFF \ + (CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) #endif #ifdef TEST_X25519 @@ -654,5 +647,5 @@ int ncp15wb_calculate_temp(uint16_t adc); #define I2C_BITBANG_PORT_COUNT 1 #endif -#endif /* TEST_BUILD */ -#endif /* __TEST_TEST_CONFIG_H */ +#endif /* TEST_BUILD */ +#endif /* __TEST_TEST_CONFIG_H */ -- cgit v1.2.1 From 3b9240964ffea6d1e73fc003cf492f81d523cf79 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:22 -0600 Subject: util/comm-host.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I159a0f62e51871e2c15ea7465ef970a449af6c9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730324 Reviewed-by: Jeremy Bettis --- util/comm-host.h | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/util/comm-host.h b/util/comm-host.h index bd22655e57..17dd28d077 100644 --- a/util/comm-host.h +++ b/util/comm-host.h @@ -63,9 +63,11 @@ int comm_init_buffer(void); * Send a command to the EC. Returns the length of output data returned (0 if * none), or negative on error. */ -int ec_command(int command, int version, - const void *outdata, int outsize, /* to the EC */ - void *indata, int insize); /* from the EC */ +int ec_command(int command, int version, const void *outdata, int outsize, /* to + the + EC + */ + void *indata, int insize); /* from the EC */ /** * Set the offset to be applied to the command number when ec_command() calls @@ -79,9 +81,9 @@ void set_command_offset(int offset); * by the protocol-specific driver. DO NOT call this version directly from * anywhere but ec_command(), or the --device option will not work. */ -extern int (*ec_command_proto)(int command, int version, - const void *outdata, int outsize, /* to EC */ - void *indata, int insize); /* from EC */ +extern int (*ec_command_proto)(int command, int version, const void *outdata, + int outsize, /* to EC */ + void *indata, int insize); /* from EC */ /** * Return the content of the EC information area mapped as "memory". -- cgit v1.2.1 From 55db56e0bb5eaf5c253a931b3ca29adf23083f1b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:00 -0600 Subject: baseboard/kukui/battery_smart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib5a1b535f359bd620fa2fd6788791a5d4b080c0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727920 Reviewed-by: Jeremy Bettis --- baseboard/kukui/battery_smart.c | 35 +++++++++++++---------------------- 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/baseboard/kukui/battery_smart.c b/baseboard/kukui/battery_smart.c index ba2af17443..960177a560 100644 --- a/baseboard/kukui/battery_smart.c +++ b/baseboard/kukui/battery_smart.c @@ -98,39 +98,30 @@ __override void board_battery_compensate_params(struct batt_params *batt) /* return cached values for at most CACHE_INVALIDATION_TIME_US */ fix_single_param(batt->flags & BATT_FLAG_BAD_STATE_OF_CHARGE, - &batt_cache.state_of_charge, - &batt->state_of_charge); + &batt_cache.state_of_charge, &batt->state_of_charge); fix_single_param(batt->flags & BATT_FLAG_BAD_VOLTAGE, - &batt_cache.voltage, - &batt->voltage); + &batt_cache.voltage, &batt->voltage); fix_single_param(batt->flags & BATT_FLAG_BAD_CURRENT, - &batt_cache.current, - &batt->current); + &batt_cache.current, &batt->current); fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_VOLTAGE, - &batt_cache.desired_voltage, - &batt->desired_voltage); + &batt_cache.desired_voltage, &batt->desired_voltage); fix_single_param(batt->flags & BATT_FLAG_BAD_DESIRED_CURRENT, - &batt_cache.desired_current, - &batt->desired_current); + &batt_cache.desired_current, &batt->desired_current); fix_single_param(batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY, - &batt_cache.remaining_capacity, - &batt->remaining_capacity); + &batt_cache.remaining_capacity, + &batt->remaining_capacity); fix_single_param(batt->flags & BATT_FLAG_BAD_FULL_CAPACITY, - &batt_cache.full_capacity, - &batt->full_capacity); - fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, - &batt_cache.status, - &batt->status); + &batt_cache.full_capacity, &batt->full_capacity); + fix_single_param(batt->flags & BATT_FLAG_BAD_STATUS, &batt_cache.status, + &batt->status); fix_single_param(batt->flags & BATT_FLAG_BAD_TEMPERATURE, - &batt_cache.temperature, - &batt->temperature); + &batt_cache.temperature, &batt->temperature); /* * If battery_compensate_params() didn't calculate display_charge * for us, also update it with last good value. */ - fix_single_param(batt->display_charge == 0, - &batt_cache.display_charge, - &batt->display_charge); + fix_single_param(batt->display_charge == 0, &batt_cache.display_charge, + &batt->display_charge); /* remove bad flags after applying cached values */ batt->flags &= ~BATT_FLAG_BAD_ANY; -- cgit v1.2.1 From e6fbaf1a563e0874bffb3f6350d5037e7fbd2035 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:22 -0600 Subject: chip/stm32/config-stm32f03x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1abed5f20dfa5500b37a9fe75fdeb40853f8b11f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729469 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f03x.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h index 3c51086c26..3e833101a8 100644 --- a/chip/stm32/config-stm32f03x.h +++ b/chip/stm32/config-stm32f03x.h @@ -5,21 +5,21 @@ #ifdef CHIP_VARIANT_STM32F03X8 #define CONFIG_FLASH_SIZE_BYTES 0x00010000 -#define CONFIG_RAM_SIZE 0x00002000 +#define CONFIG_RAM_SIZE 0x00002000 #else #define CONFIG_FLASH_SIZE_BYTES 0x00008000 -#define CONFIG_RAM_SIZE 0x00001000 +#define CONFIG_RAM_SIZE 0x00001000 #endif /* Memory mapping */ -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_BASE 0x20000000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 -- cgit v1.2.1 From f9cb29841c4bfe07d9e14e0be20b571ca341551e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:44 -0600 Subject: board/ezkinil/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0cbc43e91f95d253cc76cbb318c62332f1bea0c1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728349 Reviewed-by: Jeremy Bettis --- board/ezkinil/board.c | 114 +++++++++++++++++++++----------------------------- 1 file changed, 48 insertions(+), 66 deletions(-) diff --git a/board/ezkinil/board.c b/board/ezkinil/board.c index 46757d22f3..47089c85da 100644 --- a/board/ezkinil/board.c +++ b/board/ezkinil/board.c @@ -50,17 +50,16 @@ static int board_ver; * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* Motion sensors */ static struct mutex g_lid_mutex; @@ -72,21 +71,15 @@ static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -const mat33_fp_t base_standard_ref_1 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ struct motion_sensor_t motion_sensors[] = { @@ -211,7 +204,6 @@ struct motion_sensor_t icm426xx_base_gyro = { .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; - struct motion_sensor_t icm42607_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -411,8 +403,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the PS8818 as the secondary MUX */ usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818; @@ -424,8 +415,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the TUSB544 as the secondary MUX */ usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544; @@ -437,8 +427,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the PS8743 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_ps8743, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_ps8743, sizeof(struct usb_mux)); /* Set the AMD FP5 as the secondary MUX */ usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux; @@ -462,7 +451,7 @@ struct usb_mux usb_muxes[] = { BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); static int board_tusb544_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Enable IN_HPD on the DB */ @@ -474,8 +463,7 @@ static int board_tusb544_mux_set(const struct usb_mux *me, return EC_SUCCESS; } -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { if (mux_state & USB_PD_MUX_DP_ENABLED) /* Enable IN_HPD on the DB */ @@ -543,15 +531,15 @@ __override void ppc_interrupt(enum gpio_signal signal) } } -__override int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +__override int +board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; /* Use the TCPC to set the current limit */ - rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN - : IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); + rv = ioex_set_level(port ? IOEX_USB_C1_PPC_ILIM_3A_EN : + IOEX_USB_C0_PPC_ILIM_3A_EN, + (rp == TYPEC_RP_3A0) ? 1 : 0); return rv; } @@ -621,10 +609,9 @@ static void hdmi_hpd_handler(void) gpio_set_level(GPIO_DP1_HPD, hpd); ccprints("HDMI HPD %d", hpd); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && hpd); + pi3hdx1204_enable( + I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd); } DECLARE_DEFERRED(hdmi_hpd_handler); @@ -652,8 +639,7 @@ static void board_chipset_resume(void) if (ec_config_has_hdmi_retimer_pi3hdx1204()) { ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, check_hdmi_hpd_status()); } } @@ -664,9 +650,7 @@ static void board_chipset_suspend(void) ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0); } @@ -681,7 +665,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -772,8 +756,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_THERMISTOR \ - { \ +#define THERMAL_THERMISTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(95), \ @@ -790,8 +774,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_SOC \ - { \ +#define THERMAL_SOC \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -814,14 +798,14 @@ struct fan_step { /* Note: Do not make the fan on/off point equal to 0 or 100 */ static const struct fan_step fan_table0[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 9, .off = 1, .rpm = 3200}, - {.on = 21, .off = 7, .rpm = 3500}, - {.on = 28, .off = 16, .rpm = 3900}, - {.on = 37, .off = 26, .rpm = 4200}, - {.on = 47, .off = 35, .rpm = 4600}, - {.on = 56, .off = 44, .rpm = 5100}, - {.on = 72, .off = 60, .rpm = 5500}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 9, .off = 1, .rpm = 3200 }, + { .on = 21, .off = 7, .rpm = 3500 }, + { .on = 28, .off = 16, .rpm = 3900 }, + { .on = 37, .off = 26, .rpm = 4200 }, + { .on = 47, .off = 35, .rpm = 4600 }, + { .on = 56, .off = 44, .rpm = 5100 }, + { .on = 72, .off = 60, .rpm = 5500 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) @@ -867,8 +851,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) { + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) { cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); board_print_temps(); @@ -878,7 +861,7 @@ int fan_percent_to_rpm(int fan, int pct) } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Limit the input current to 95% negotiated limit, @@ -886,7 +869,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From a33562f9cc6f94a89e9e12a986729398a06223c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:57 -0600 Subject: baseboard/octopus/variant_usbc_ec_tcpcs.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I31d3b3ab64a71a1e15794b3bd5a57d9f30a81004 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727941 Reviewed-by: Jeremy Bettis --- baseboard/octopus/variant_usbc_ec_tcpcs.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c index 00640168cf..6b3d2e2315 100644 --- a/baseboard/octopus/variant_usbc_ec_tcpcs.c +++ b/baseboard/octopus/variant_usbc_ec_tcpcs.c @@ -22,8 +22,8 @@ #include "usbc_ppc.h" #include "util.h" -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 +#define USB_PD_PORT_ITE_0 0 +#define USB_PD_PORT_ITE_1 1 /******************************************************************************/ /* USB-C TPCP Configuration */ @@ -49,13 +49,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* TODO(crbug.com/826441): Consolidate this logic with other impls */ static void board_it83xx_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required) + mux_state_t mux_state, bool *ack_required) { int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0; - enum gpio_signal gpio = me->usb_port ? - GPIO_USB_C1_HPD_1V8_ODL : GPIO_USB_C0_HPD_1V8_ODL; + enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1V8_ODL : + GPIO_USB_C0_HPD_1V8_ODL; /* This driver does not use host command ACKs */ *ack_required = false; @@ -94,16 +93,12 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_ITE_0] = { - .i2c_port = I2C_PORT_USBC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_ITE_1] = { - .i2c_port = I2C_PORT_USBC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_ITE_0] = { .i2c_port = I2C_PORT_USBC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_ITE_1] = { .i2c_port = I2C_PORT_USBC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -158,6 +153,6 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) * correctly in the PPC driver via the pd state machine. */ if (ppc_set_vconn(port, enabled) != EC_SUCCESS) - cprints(CC_USBPD, "C%d: Failed %sabling vconn", - port, enabled ? "en" : "dis"); + cprints(CC_USBPD, "C%d: Failed %sabling vconn", port, + enabled ? "en" : "dis"); } -- cgit v1.2.1 From 0a6d948e5a3ee4bda2ecc13326d7ba3baf65e454 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:28 -0600 Subject: power/apollolake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id28f2073ff46b34cb1641c902943a3cee58cabdd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727056 Reviewed-by: Jeremy Bettis --- power/apollolake.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/power/apollolake.c b/power/apollolake.c index 3bc03af626..d6a9f75e89 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -13,7 +13,7 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* * force_shutdown is used to maintain chipset shutdown request. This request @@ -145,7 +145,6 @@ enum power_state power_handle_state(enum power_state state) new_state = POWER_S5G3; goto rsmrst_handle; - } /* If force shutdown is requested, perform that. */ -- cgit v1.2.1 From cf1043d05fa92baa9ca74e7101a8d393bd8e4b53 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:23 -0600 Subject: board/brya/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50e40aea0c56408111a5abd08bbb8635625c3b4d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728099 Reviewed-by: Jeremy Bettis --- board/brya/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brya/fans.c b/board/brya/fans.c index 021f0de8e2..c65680bb62 100644 --- a/board/brya/fans.c +++ b/board/brya/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 61c61d3d98511099d8affcf6db6dd4c56203a18a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:33 -0600 Subject: board/kakadu/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea23222eb413e05d49d54c826775ee7bee81b6e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728521 Reviewed-by: Jeremy Bettis --- board/kakadu/board.h | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/board/kakadu/board.h b/board/kakadu/board.h index 09ff6d10be..89a8881fc7 100644 --- a/board/kakadu/board.h +++ b/board/kakadu/board.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_BOARD_H #define __CROS_EC_BOARD_H -#define BQ27541_ADDR 0x55 +#define BQ27541_ADDR 0x55 #define VARIANT_KUKUI_BATTERY_BQ27541 #define VARIANT_KUKUI_POGO_KEYBOARD @@ -27,35 +27,33 @@ #define CONFIG_USB_MUX_RUNTIME_CONFIG /* Battery */ -#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ +#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ #define CONFIG_CHARGER_MT6370_BACKLIGHT - /* Motion Sensors */ #ifdef SECTION_IS_RW #define CONFIG_ACCELGYRO_BMI160 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) -#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) /* Camera VSYNC */ #define CONFIG_SYNC #define CONFIG_SYNC_COMMAND -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #endif /* SECTION_IS_RW */ /* I2C ports */ -#define I2C_PORT_CHARGER 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 1 +#define I2C_PORT_CHARGER 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 1 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_ACCEL 1 -#define I2C_PORT_BC12 1 +#define I2C_PORT_ACCEL 1 +#define I2C_PORT_BC12 1 /* Route sbs host requests to virtual battery driver */ #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B -- cgit v1.2.1 From d4991718175d51c0947dd2f9ac2959f1599d446f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:27 -0600 Subject: chip/npcx/wov_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a524f965e6e07c3e5e3abf5c520e50ef686eda5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729449 Reviewed-by: Jeremy Bettis --- chip/npcx/wov_chip.h | 80 +++++++++++++++++++++------------------------------- 1 file changed, 32 insertions(+), 48 deletions(-) diff --git a/chip/npcx/wov_chip.h b/chip/npcx/wov_chip.h index dce534c501..0add348d95 100644 --- a/chip/npcx/wov_chip.h +++ b/chip/npcx/wov_chip.h @@ -34,10 +34,7 @@ enum wov_mic_source { }; /* Clock source for APM. */ -enum wov_clk_src_sel { - WOV_FMUL2_CLK_SRC = 0, - WOV_PLL_CLK_SRC = 1 -}; +enum wov_clk_src_sel { WOV_FMUL2_CLK_SRC = 0, WOV_PLL_CLK_SRC = 1 }; /* FMUL clock division factore. */ enum wov_fmul_div { @@ -48,10 +45,7 @@ enum wov_fmul_div { }; /* Lock state. */ -enum wov_lock_state { - WOV_UNLOCK = 0, - WOV_LOCK = 1 -}; +enum wov_lock_state { WOV_UNLOCK = 0, WOV_LOCK = 1 }; /* Reference clock source select. */ enum wov_ref_clk_src_sel { @@ -60,10 +54,7 @@ enum wov_ref_clk_src_sel { }; /* PLL external divider select. */ -enum wov_ext_div_sel { - WOV_EXT_DIV_BINARY_CNT = 0, - WOV_EXT_DIV_LFSR_DIV = 1 -}; +enum wov_ext_div_sel { WOV_EXT_DIV_BINARY_CNT = 0, WOV_EXT_DIV_LFSR_DIV = 1 }; /* FMUL output frequency. */ enum wov_fmul_out_freq { @@ -117,10 +108,7 @@ enum wov_interrupt_index { }; /* FIFO DMA request selection. */ -enum wov_dma_req_sel { - WOV_DFLT_ESPI_DMA_REQ = 0, - WOV_FROM_FIFO_DMA_REQUEST -}; +enum wov_dma_req_sel { WOV_DFLT_ESPI_DMA_REQ = 0, WOV_FROM_FIFO_DMA_REQUEST }; /* Core FIFO input select. */ enum wov_core_fifo_in_sel { @@ -131,10 +119,7 @@ enum wov_core_fifo_in_sel { }; /* PLL external divider selector. */ -enum wov_pll_ext_div_sel { - WOV_PLL_EXT_DIV_BIN_CNT = 0, - WOV_PLL_EXT_DIV_LFSR -}; +enum wov_pll_ext_div_sel { WOV_PLL_EXT_DIV_BIN_CNT = 0, WOV_PLL_EXT_DIV_LFSR }; /* Code for events for call back function. */ enum wov_events { @@ -144,7 +129,7 @@ enum wov_events { * need to call to wov_set_buffer to update the buffer * pointer */ WOV_EVENT_DATA_READY = 1, - WOV_EVENT_VAD, /* Voice activity detected */ + WOV_EVENT_VAD, /* Voice activity detected */ WOV_EVENT_ERROR_FIRST = 128, WOV_EVENT_ERROR_CORE_FIFO_OVERRUN = 128, @@ -158,8 +143,8 @@ enum wov_events { enum wov_fifo_errors { WOV_FIFO_NO_ERROR = 0, WOV_CORE_FIFO_OVERRUN = 1, /* 2 : I2S FIFO is underrun. */ - WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun. */ - WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */ + WOV_I2S_FIFO_OVERRUN = 2, /* 3 : I2S FIFO is overrun. */ + WOV_I2S_FIFO_UNDERRUN = 3 /* 4 : I2S FIFO is underrun. */ }; @@ -191,12 +176,12 @@ enum wov_modes { /* DAI format. */ enum wov_dai_format { - WOV_DAI_FMT_I2S, /* I2S mode */ + WOV_DAI_FMT_I2S, /* I2S mode */ WOV_DAI_FMT_RIGHT_J, /* Right Justified mode */ - WOV_DAI_FMT_LEFT_J, /* Left Justified mode */ - WOV_DAI_FMT_PCM_A, /* PCM A Audio */ - WOV_DAI_FMT_PCM_B, /* PCM B Audio */ - WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing */ + WOV_DAI_FMT_LEFT_J, /* Left Justified mode */ + WOV_DAI_FMT_PCM_A, /* PCM A Audio */ + WOV_DAI_FMT_PCM_B, /* PCM B Audio */ + WOV_DAI_FMT_PCM_TDM /* Time Division Multiplexing */ }; struct wov_config { @@ -375,10 +360,10 @@ void wov_enable_agc(int enable); * @param min_applied_gain - Minimum Gain Value to apply to the ADC path. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_set_agc_config(int stereo, float target, - int noise_gate_threshold, uint8_t hold_time, - uint16_t attack_time, uint16_t decay_time, - float max_applied_gain, float min_applied_gain); +enum ec_error_list +wov_set_agc_config(int stereo, float target, int noise_gate_threshold, + uint8_t hold_time, uint16_t attack_time, uint16_t decay_time, + float max_applied_gain, float min_applied_gain); /** * Sets VAD sensitivity. @@ -438,7 +423,7 @@ void wov_set_i2s_bclk(uint32_t i2s_clock); * @return EC error code. */ enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay, - uint32_t flags); + uint32_t flags); /** * Configure FMUL2 clock tunning. @@ -477,8 +462,9 @@ extern void wov_set_clk_selection(enum wov_clk_src_sel clk_src); * PLL External Divider Load Values table. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_pll_clk_ext_div_config( - enum wov_pll_ext_div_sel ext_div_sel, uint32_t div_factor); +enum ec_error_list +wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel, + uint32_t div_factor); /** * PLL power down. @@ -498,9 +484,9 @@ void wov_pll_enable(int enable); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1, - uint32_t out_div_2, - uint32_t feedback_div, - uint32_t in_div); + uint32_t out_div_2, + uint32_t feedback_div, + uint32_t in_div); /** * Enables/Disables WoV interrupt. @@ -521,7 +507,7 @@ void wov_interrupt_enable(enum wov_interrupt_index int_index, int enable); * @return None */ void wov_cfifo_config(enum wov_core_fifo_in_sel in_sel, - enum wov_fifo_threshold threshold); + enum wov_fifo_threshold threshold); /** * Start the actual capturing of the Voice data to the RAM. @@ -632,13 +618,10 @@ void wov_handle_event(enum wov_events event); * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_global_config( - enum wov_floating_mode i2s_hiz_data, - enum wov_floating_mode i2s_hiz, - enum wov_clk_inverted_mode clk_invert, - int out_pull_en, enum wov_pull_upd_down_sel out_pull_mode, - int in_pull_en, - enum wov_pull_upd_down_sel in_pull_mode, - enum wov_test_mode test_mode); + enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz, + enum wov_clk_inverted_mode clk_invert, int out_pull_en, + enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en, + enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode); /** * I2S channel configuration @@ -652,7 +635,8 @@ enum ec_error_list wov_i2s_global_config( * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, - uint32_t bit_count, enum wov_i2s_chan_trigger trigger, - int32_t start_delay); + uint32_t bit_count, + enum wov_i2s_chan_trigger trigger, + int32_t start_delay); #endif /* __CROS_EC_WOV_CHIP_H */ -- cgit v1.2.1 From ec0bf546df904e4405ebb35e4426919af7362d28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:30 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e9.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia13f9d0812a8a0479fabd69d596c094fbb4470c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730576 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e9.c | 49 +++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e9.c b/test/usb_tcpmv2_td_pd_src3_e9.c index 49b8209669..e328b3a4b7 100644 --- a/test/usb_tcpmv2_td_pd_src3_e9.c +++ b/test/usb_tcpmv2_td_pd_src3_e9.c @@ -23,8 +23,8 @@ #define SCEDB_NUM_BATTERY_OFFSET 22 #define SCEDB_NUM_BYTES 24 -#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1) -#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF) +#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1) +#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF) static int number_of_fixed_batteries(void) { @@ -84,33 +84,26 @@ int test_td_pd_src3_e9(void) possible[1].ctrl_msg = 0; possible[1].data_msg = PD_DATA_SOURCE_CAP; - TEST_EQ(verify_tcpci_possible_tx(possible, - 2, - &found_index, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data, + sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); if (found_index == 1) { mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); task_wait_event(10 * MSEC); - TEST_EQ(msg_len, HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BYTES, + TEST_EQ(msg_len, + HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES, "%d"); num_fixed_batteries = - data[HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BATTERY_OFFSET] & - 0x0F; + data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + + SCEDB_NUM_BATTERY_OFFSET] & + 0x0F; num_swappable_battery_slots = - (data[HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BATTERY_OFFSET] >> 4) & - 0x0F; + (data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + + SCEDB_NUM_BATTERY_OFFSET] >> + 4) & + 0x0F; } /* * If a Not_Supported message is received, the Tester reads the @@ -133,8 +126,7 @@ int test_td_pd_src3_e9(void) * to 8, to the UUT. */ ref = 8; - ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | - (ref << 16); + ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16); partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1, &ext_msg); @@ -153,13 +145,8 @@ int test_td_pd_src3_e9(void) possible[1].ctrl_msg = 0; possible[1].data_msg = PD_DATA_BATTERY_STATUS; - TEST_EQ(verify_tcpci_possible_tx(possible, - 2, - &found_index, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data, + sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); if (found_index == 0) { mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); @@ -210,8 +197,8 @@ int test_td_pd_src3_e9(void) * 6. Invalid Battery Reference field (Bit 0) of the * Battery Info field in the BSDO is 1 */ - bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES); + bsdo = UINT32_FROM_BYTE_ARRAY_LE( + data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES); TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d"); /* -- cgit v1.2.1 From 1a6d752fc781ff306b1a1896984f15e7d7497cd9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:32 -0600 Subject: chip/host/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If91faa2981d5412bf72e6c48b1ee324fc132fbe6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729149 Reviewed-by: Jeremy Bettis --- chip/host/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/host/gpio.c b/chip/host/gpio.c index 3c15205ad5..5d1bd78e79 100644 --- a/chip/host/gpio.c +++ b/chip/host/gpio.c @@ -19,8 +19,8 @@ static int gpio_interrupt_enabled[GPIO_COUNT]; /* Create a dictionary of names for debug console print */ #define GPIO_INT(name, pin, flags, signal) #name, #define GPIO(name, pin, flags) #name, -const char * gpio_names[GPIO_COUNT] = { - #include "gpio.wrap" +const char *gpio_names[GPIO_COUNT] = { +#include "gpio.wrap" }; #undef GPIO #undef GPIO_INT @@ -92,7 +92,7 @@ test_mockable void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, } test_mockable void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* Nothing */ } -- cgit v1.2.1 From cef4c1b6c3ce3824c6aed86b1a3648df24cbf0ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:06 -0600 Subject: board/moli/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id876aad366c35ecd51e0bac6387fb9ff3e971e26 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728692 Reviewed-by: Jeremy Bettis --- board/moli/pwm.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/board/moli/pwm.c b/board/moli/pwm.c index ad3d45f34c..bba4f8cac9 100644 --- a/board/moli/pwm.c +++ b/board/moli/pwm.c @@ -11,21 +11,17 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_AMBER] = { - .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, - [PWM_CH_LED_BLUE] = { - .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, + [PWM_CH_LED_AMBER] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_BLUE] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From 6f02e2cdffac2a9215a36f4f02cc7cb0e3c2954a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:31 -0600 Subject: include/rsa.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68794bd1f2c258907e1c165c4326e04453325c34 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730399 Reviewed-by: Jeremy Bettis --- include/rsa.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/include/rsa.h b/include/rsa.h index 60d56711ca..3c5a534578 100644 --- a/include/rsa.h +++ b/include/rsa.h @@ -45,23 +45,21 @@ /* RSA public key definition, VBoot2 packing */ struct rsa_public_key { uint32_t size; - uint32_t n0inv; /* -1 / n[0] mod 2^32 */ - uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */ }; #else /* RSA public key definition */ struct rsa_public_key { - uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ + uint32_t n[RSANUMWORDS]; /* modulus as little endian array */ uint32_t rr[RSANUMWORDS]; /* R^2 as little endian array */ - uint32_t n0inv; /* -1 / n[0] mod 2^32 */ + uint32_t n0inv; /* -1 / n[0] mod 2^32 */ }; #endif -int rsa_verify(const struct rsa_public_key *key, - const uint8_t *signature, - const uint8_t *sha, - uint32_t *workbuf32); +int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature, + const uint8_t *sha, uint32_t *workbuf32); #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 97b81e0fdd655f70747948ebe65aca19291c00bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:05 -0600 Subject: common/vboot/vb21_lib.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib9cd3606106bcf0fe4875927fbd3305009c321aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729807 Reviewed-by: Jeremy Bettis --- common/vboot/vb21_lib.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/common/vboot/vb21_lib.c b/common/vboot/vb21_lib.c index 4e215c14e5..107f2d9ac1 100644 --- a/common/vboot/vb21_lib.c +++ b/common/vboot/vb21_lib.c @@ -52,7 +52,6 @@ const struct vb21_packed_key *vb21_get_packed_key(void) static void read_rwsig_info(struct ec_response_rwsig_info *r) { - const struct vb21_packed_key *vb21_key; int rv; @@ -61,10 +60,14 @@ static void read_rwsig_info(struct ec_response_rwsig_info *r) r->sig_alg = vb21_key->sig_alg; r->hash_alg = vb21_key->hash_alg; r->key_version = vb21_key->key_version; - { BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id), - "key ID sizes must match"); } - { BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw), - "key ID sizes must match"); } + { + BUILD_ASSERT(sizeof(r->key_id) == sizeof(vb21_key->id), + "key ID sizes must match"); + } + { + BUILD_ASSERT(sizeof(vb21_key->id) == sizeof(vb21_key->id.raw), + "key ID sizes must match"); + } memcpy(r->key_id, vb21_key->id.raw, sizeof(r->key_id)); rv = vb21_is_packed_key_valid(vb21_key); -- cgit v1.2.1 From bb335408395e704c8791da0eb60df6251d616cf9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:06 -0600 Subject: board/scout/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I575bdd5f61fcd4706a64e2541d286d93a0e6e67e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728919 Reviewed-by: Jeremy Bettis --- board/scout/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/scout/led.c b/board/scout/led.c index 3066c182d1..716b95114f 100644 --- a/board/scout/led.c +++ b/board/scout/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From c36b09e5e99a109e357fc61c7692458c4b8b7590 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:01 -0600 Subject: board/nocturne/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I42ad60444b11546a569372e07a7511c35b0d000b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728756 Reviewed-by: Jeremy Bettis --- board/nocturne/base_detect.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/board/nocturne/base_detect.c b/board/nocturne/base_detect.c index 48c7b1f9dd..d84fcc45e3 100644 --- a/board/nocturne/base_detect.c +++ b/board/nocturne/base_detect.c @@ -26,8 +26,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define DEFAULT_POLL_TIMEOUT_US (250 * MSEC) #define DEBOUNCE_TIMEOUT_US (20 * MSEC) @@ -62,7 +62,6 @@ */ #define WINDOW_SIZE 5 - enum base_detect_state { BASE_DETACHED = 0, BASE_ATTACHED_DEBOUNCE, @@ -82,7 +81,7 @@ static timestamp_t detached_decision_deadline; static void enable_base_interrupts(int enable) { int (*fn)(enum gpio_signal) = enable ? gpio_enable_interrupt : - gpio_disable_interrupt; + gpio_disable_interrupt; /* This pin is present on boards newer than rev 0. */ if (board_get_version() > 0) @@ -141,28 +140,26 @@ static void base_detect_changed(void) static int base_seems_attached(int attach_pin_mv, int detach_pin_mv) { /* We can't tell if we don't have good readings. */ - if (attach_pin_mv == ADC_READ_ERROR || - detach_pin_mv == ADC_READ_ERROR) + if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR) return 0; if (gpio_get_level(GPIO_BASE_PWR_EN)) return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) && - (detach_pin_mv >= DETACH_MIN_MV); + (detach_pin_mv >= DETACH_MIN_MV); else return (attach_pin_mv <= ATTACH_MAX_MV) && - (attach_pin_mv >= ATTACH_MIN_MV) && - (detach_pin_mv <= DETACH_MIN_MV); + (attach_pin_mv >= ATTACH_MIN_MV) && + (detach_pin_mv <= DETACH_MIN_MV); } static int base_seems_detached(int attach_pin_mv, int detach_pin_mv) { /* We can't tell if we don't have good readings. */ - if (attach_pin_mv == ADC_READ_ERROR || - detach_pin_mv == ADC_READ_ERROR) + if (attach_pin_mv == ADC_READ_ERROR || detach_pin_mv == ADC_READ_ERROR) return 0; return (attach_pin_mv >= PWREN_ATTACH_MIN_MV) && - (detach_pin_mv <= DETACH_MIN_MV); + (detach_pin_mv <= DETACH_MIN_MV); } static void set_state(enum base_detect_state new_state) @@ -194,9 +191,9 @@ static void base_detect_deferred(void) if (forced_state != BASE_NO_FORCED_STATE) { if (state != forced_state) { - CPRINTS("BD forced %s", - forced_state == BASE_ATTACHED ? - "attached" : "detached"); + CPRINTS("BD forced %s", forced_state == BASE_ATTACHED ? + "attached" : + "detached"); set_state(forced_state); base_detect_changed(); } @@ -212,8 +209,7 @@ static void base_detect_deferred(void) if (debug) { int i; - CPRINTS("BD st%d: att: %dmV det: %dmV", state, - attach_reading, + CPRINTS("BD st%d: att: %dmV det: %dmV", state, attach_reading, detach_reading); CPRINTF("det readings = ["); for (i = 0; i < WINDOW_SIZE; i++) @@ -341,7 +337,6 @@ static void check_and_reapply_base_power_deferred(void) hook_call_deferred(&clear_base_power_on_attempts_deferred_data, SECOND); } - } DECLARE_DEFERRED(check_and_reapply_base_power_deferred); @@ -371,15 +366,14 @@ static int command_basedetectdebug(int argc, char **argv) if ((argc > 1) && !parse_bool(argv[1], &debug)) return EC_ERROR_PARAM1; - CPRINTS("BD: %sst%d", forced_state != BASE_NO_FORCED_STATE ? - "forced " : "", state); + CPRINTS("BD: %sst%d", + forced_state != BASE_NO_FORCED_STATE ? "forced " : "", state); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(basedebug, command_basedetectdebug, "[ena|dis]", "En/Disable base detection debug"); - void base_force_state(enum ec_set_base_state_cmd state) { if (state == EC_SET_BASE_STATE_ATTACH) -- cgit v1.2.1 From 10356a2f249ad9e50e0b3234c8aea60ad2221f56 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:45 -0600 Subject: board/cret/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia30868aec28a9995a780ad0bbf2a6c9caa643549 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728208 Reviewed-by: Jeremy Bettis --- board/cret/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/cret/cbi_ssfc.h b/board/cret/cbi_ssfc.h index 058290de8d..34c2be182c 100644 --- a/board/cret/cbi_ssfc.h +++ b/board/cret/cbi_ssfc.h @@ -61,5 +61,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From ed4bdf25750498d5aa8bf834c6773f4f4acc6c3b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:14 -0600 Subject: chip/ish/config_flash_layout.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f63794e25368d80519953b991ce5b2276fd04b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729175 Reviewed-by: Jeremy Bettis --- chip/ish/config_flash_layout.h | 43 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h index 9a6cc4f28b..100d009d8e 100644 --- a/chip/ish/config_flash_layout.h +++ b/chip/ish/config_flash_layout.h @@ -8,14 +8,14 @@ /* Mem-mapped, No external SPI for ISH */ #undef CONFIG_EXTERNAL_STORAGE -#define CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE +#define CONFIG_MAPPED_STORAGE +#undef CONFIG_FLASH_PSTATE #undef CONFIG_SPI_FLASH #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_ISH_BOOT_START 0xFF200000 +#define CONFIG_ISH_BOOT_START 0xFF200000 #else -#define CONFIG_ISH_BOOT_START 0xFF000000 +#define CONFIG_ISH_BOOT_START 0xFF000000 #endif /*****************************************************************************/ @@ -24,40 +24,37 @@ * turn off SPI and flash, making these unnecessary. */ -#define CONFIG_MAPPED_STORAGE_BASE 0x0 +#define CONFIG_MAPPED_STORAGE_BASE 0x0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Unused for ISH - loader is external to ISH FW */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 - +#define CONFIG_LOADER_MEM_OFF 0 +#define CONFIG_LOADER_SIZE 0xC00 /* RO/RW images - not relevant for ISH */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE) +#define CONFIG_RO_SIZE (97 * 1024) +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE /*****************************************************************************/ /* Not relevant for ISH */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) +#define CONFIG_LOADER_STORAGE_OFF \ + (CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE) /* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) +#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE) /* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ -- cgit v1.2.1 From 79f481874bad1b51bf67bf854caf199858d394f9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:08 -0600 Subject: driver/als_al3010.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I45c1a563b1ceec76d4edcb524965cca49287a209 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729923 Reviewed-by: Jeremy Bettis --- driver/als_al3010.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/driver/als_al3010.c b/driver/als_al3010.c index b129dc2f57..fb3311df8b 100644 --- a/driver/als_al3010.c +++ b/driver/als_al3010.c @@ -15,13 +15,13 @@ int al3010_init(void) { int ret; - ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, - AL3010_REG_CONFIG, AL3010_GAIN << 4); + ret = i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_CONFIG, + AL3010_GAIN << 4); if (ret) return ret; - return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, - AL3010_REG_SYSTEM, AL3010_ENABLE); + return i2c_write8(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_SYSTEM, + AL3010_ENABLE); } /** @@ -33,8 +33,8 @@ int al3010_read_lux(int *lux, int af) int val; long long val64; - ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR, - AL3010_REG_DATA_LOW, &val); + ret = i2c_read16(I2C_PORT_ALS, AL3010_I2C_ADDR, AL3010_REG_DATA_LOW, + &val); if (ret) return ret; -- cgit v1.2.1 From f92bb148f8cd34140dfdea10fecc152aafb1996a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:59 -0600 Subject: driver/ppc/syv682x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59d3658b11f3db9b8483f0856d4919b627fb7f63 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730036 Reviewed-by: Jeremy Bettis --- driver/ppc/syv682x.c | 76 +++++++++++++++++++++++++--------------------------- 1 file changed, 36 insertions(+), 40 deletions(-) diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c index 22ff51f3d2..d7539d7a81 100644 --- a/driver/ppc/syv682x.c +++ b/driver/ppc/syv682x.c @@ -21,16 +21,16 @@ #include "usb_pd.h" #include "util.h" -#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0) -#define SYV682X_FLAGS_SINK_ENABLED BIT(1) +#define SYV682X_FLAGS_SOURCE_ENABLED BIT(0) +#define SYV682X_FLAGS_SINK_ENABLED BIT(1) /* 0 -> CC1, 1 -> CC2 */ -#define SYV682X_FLAGS_CC_POLARITY BIT(2) -#define SYV682X_FLAGS_VBUS_PRESENT BIT(3) -#define SYV682X_FLAGS_TSD BIT(4) -#define SYV682X_FLAGS_OVP BIT(5) -#define SYV682X_FLAGS_5V_OC BIT(6) -#define SYV682X_FLAGS_FRS BIT(7) -#define SYV682X_FLAGS_VCONN_OCP BIT(8) +#define SYV682X_FLAGS_CC_POLARITY BIT(2) +#define SYV682X_FLAGS_VBUS_PRESENT BIT(3) +#define SYV682X_FLAGS_TSD BIT(4) +#define SYV682X_FLAGS_OVP BIT(5) +#define SYV682X_FLAGS_5V_OC BIT(6) +#define SYV682X_FLAGS_FRS BIT(7) +#define SYV682X_FLAGS_VCONN_OCP BIT(8) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -39,7 +39,7 @@ static atomic_t sink_ocp_count[CONFIG_USB_PD_PORT_MAX_COUNT]; static timestamp_t vbus_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT]; static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT]; -#define SYV682X_VBUS_DET_THRESH_MV 4000 +#define SYV682X_VBUS_DET_THRESH_MV 4000 /* Longest time that can be programmed in DSG_TIME field */ #define SYV682X_MAX_VBUS_DISCHARGE_TIME_MS 400 /* @@ -68,9 +68,10 @@ static timestamp_t vconn_oc_timer[CONFIG_USB_PD_PORT_MAX_COUNT]; "instead of the TCPC" #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -static int syv682x_vbus_sink_enable(int port, int enable); + static int + syv682x_vbus_sink_enable(int port, int enable); static int syv682x_init(int port); @@ -79,9 +80,7 @@ static void syv682x_interrupt_delayed(int port, int delay); static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } #ifdef CONFIG_USBC_PPC_SYV682C @@ -107,8 +106,8 @@ static int syv682x_wait_for_ready(int port, int reg) return EC_SUCCESS; #endif - deadline.val = get_time().val - + (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC); + deadline.val = + get_time().val + (SYV682X_MAX_VBUS_DISCHARGE_TIME_MS * MSEC); do { rv = read_reg(port, SYV682X_CONTROL_3_REG, ®val); @@ -138,9 +137,7 @@ static int write_reg(uint8_t port, int reg, int regval) return rv; return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int syv682x_is_sourcing_vbus(int port) @@ -186,8 +183,8 @@ static int syv682x_vbus_source_enable(int port, int enable) if (enable) { /* Select 5V path and turn on channel */ - regval &= ~(SYV682X_CONTROL_1_CH_SEL | - SYV682X_CONTROL_1_PWR_ENB); + regval &= + ~(SYV682X_CONTROL_1_CH_SEL | SYV682X_CONTROL_1_PWR_ENB); /* Disable HV Sink path */ regval |= SYV682X_CONTROL_1_HV_DR; } else if (flags[port] & SYV682X_FLAGS_SOURCE_ENABLED) { @@ -416,8 +413,8 @@ static int syv682x_vbus_sink_enable(int port, int enable) /* Select high voltage path */ regval |= SYV682X_CONTROL_1_CH_SEL; /* Select Sink mode and turn on the channel */ - regval &= ~(SYV682X_CONTROL_1_HV_DR | - SYV682X_CONTROL_1_PWR_ENB); + regval &= + ~(SYV682X_CONTROL_1_HV_DR | SYV682X_CONTROL_1_PWR_ENB); /* Set sink current limit to the configured value */ regval |= CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT; atomic_clear_bits(&flags[port], SYV682X_FLAGS_SOURCE_ENABLED); @@ -567,8 +564,8 @@ static int syv682x_dump(int port) ccprintf("ppc_syv682[p%d]: Failed to read reg 0x%02x\n", port, reg_addr); else - ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n", - port, reg_addr, data); + ccprintf("ppc_syv682[p%d]: reg 0x%02x = 0x%02x\n", port, + reg_addr, data); } cflush(); @@ -652,10 +649,10 @@ static int syv682x_set_frs_enable(int port, int enable) * should be set. */ regval &= ~(SYV682X_CONTROL_4_CC1_BPS | - SYV682X_CONTROL_4_CC2_BPS); + SYV682X_CONTROL_4_CC2_BPS); regval |= flags[port] & SYV682X_FLAGS_CC_POLARITY ? - SYV682X_CONTROL_4_CC2_BPS : - SYV682X_CONTROL_4_CC1_BPS; + SYV682X_CONTROL_4_CC2_BPS : + SYV682X_CONTROL_4_CC1_BPS; /* set GPIO after configuring */ write_reg(port, SYV682X_CONTROL_4_REG, regval); gpio_or_ioex_set_level(ppc_chips[port].frs_en, 1); @@ -705,9 +702,9 @@ static bool syv682x_is_sink(uint8_t control_1) * * The SYV682 is only a sink when !HV_DR && CH_SEL */ - if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB) - && !(control_1 & SYV682X_CONTROL_1_HV_DR) - && (control_1 & SYV682X_CONTROL_1_CH_SEL)) + if (!(control_1 & SYV682X_CONTROL_1_PWR_ENB) && + !(control_1 & SYV682X_CONTROL_1_HV_DR) && + (control_1 & SYV682X_CONTROL_1_CH_SEL)) return true; return false; @@ -735,8 +732,7 @@ static int syv682x_init(int port) if (IS_ENABLED(CONFIG_USB_PD_FRS_PPC)) gpio_or_ioex_set_level(ppc_chips[port].frs_en, 0); - if (!syv682x_is_sink(control_1) - || (status & SYV682X_STATUS_VSAFE_0V)) { + if (!syv682x_is_sink(control_1) || (status & SYV682X_STATUS_VSAFE_0V)) { /* * Disable both power paths, * set HV_ILIM to 3.3A, @@ -745,9 +741,9 @@ static int syv682x_init(int port) * select HV channel. */ regval = SYV682X_CONTROL_1_PWR_ENB | - (CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) | - /* !SYV682X_CONTROL_1_HV_DR */ - SYV682X_CONTROL_1_CH_SEL; + (CONFIG_SYV682X_HV_ILIM << SYV682X_HV_ILIM_BIT_SHIFT) | + /* !SYV682X_CONTROL_1_HV_DR */ + SYV682X_CONTROL_1_CH_SEL; rv = write_reg(port, SYV682X_CONTROL_1_REG, regval); if (rv) return rv; @@ -775,9 +771,9 @@ static int syv682x_init(int port) * tVconnOff (35ms) timeout. * On SYV682C, we are allowed to access CONTROL4 while the i2c busy. */ - regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) - | (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT) - | (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT); + regval = (SYV682X_OC_DELAY_10MS << SYV682X_OC_DELAY_SHIFT) | + (SYV682X_DSG_RON_200_OHM << SYV682X_DSG_RON_SHIFT) | + (SYV682X_DSG_TIME_50MS << SYV682X_DSG_TIME_SHIFT); if (IS_ENABLED(CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE)) regval |= SYV682X_CONTROL_2_SDSG; -- cgit v1.2.1 From 96fdb6acedba536a267ae7086a27c73bd128223b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:54 -0600 Subject: board/coral/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iad733c7b8d94b2a341fc1da48ced809a47de3b8f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728159 Reviewed-by: Jeremy Bettis --- board/coral/led.c | 78 +++++++++++++++++++++++++++---------------------------- 1 file changed, 38 insertions(+), 40 deletions(-) diff --git a/board/coral/led.c b/board/coral/led.c index 2a1e39946c..0743c5e691 100644 --- a/board/coral/led.c +++ b/board/coral/led.c @@ -28,8 +28,7 @@ #define LED_POWER_ON_TICKS (LED_POWER_BLINK_ON_MSEC / HOOK_TICK_INTERVAL_MS) #define LED_POWER_OFF_TICKS (LED_POWER_BLINK_OFF_MSEC / HOOK_TICK_INTERVAL_MS) -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -37,18 +36,14 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); #define GPIO_LED_COLOR_2 GPIO_BAT_LED_BLUE #define GPIO_LED_COLOR_3 GPIO_POW_LED -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; enum led_color { LED_OFF, LED_COLOR_1, LED_COLOR_2, LED_COLOR_BOTH, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; enum led_states { @@ -85,37 +80,37 @@ struct led_info { /* COLOR_1 = Amber, COLOR_2 = Blue */ static const struct led_descriptor led_default_state_table[][LED_NUM_PHASES] = { - { {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_1, 1 * LED_ONE_SEC }, {LED_OFF, 3 * LED_ONE_SEC} }, - { {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} }, - { {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} }, + { { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 3 * LED_ONE_SEC } }, + { { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } }, + { { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } }, }; /* COLOR_1 = Green, COLOR_2 = Red */ static const struct led_descriptor led_robo_state_table[][LED_NUM_PHASES] = { - { {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_BOTH, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} }, - { {LED_COLOR_2, 2 * LED_ONE_SEC}, {LED_COLOR_1, 2 * LED_ONE_SEC} }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_BOTH, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } }, + { { LED_COLOR_2, 2 * LED_ONE_SEC }, { LED_COLOR_1, 2 * LED_ONE_SEC } }, }; static const struct led_descriptor led_nasher_state_table[][LED_NUM_PHASES] = { - { {LED_COLOR_1, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_COLOR_1, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_2, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} }, - { {LED_OFF, LED_INDEFINITE}, {LED_OFF, LED_INDEFINITE} }, - { {LED_COLOR_1, 1 * LED_ONE_SEC}, {LED_OFF, 1 * LED_ONE_SEC} }, - { {LED_COLOR_1, 2 * LED_ONE_SEC}, {LED_COLOR_2, 2 * LED_ONE_SEC} }, + { { LED_COLOR_1, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_COLOR_1, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_2, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } }, + { { LED_OFF, LED_INDEFINITE }, { LED_OFF, LED_INDEFINITE } }, + { { LED_COLOR_1, 1 * LED_ONE_SEC }, { LED_OFF, 1 * LED_ONE_SEC } }, + { { LED_COLOR_1, 2 * LED_ONE_SEC }, { LED_COLOR_2, 2 * LED_ONE_SEC } }, }; static struct led_info led; @@ -176,7 +171,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) static enum led_states led_get_state(void) { - int charge_lvl; + int charge_lvl; enum led_states new_state = LED_NUM_STATES; switch (charge_get_state()) { @@ -185,7 +180,8 @@ static enum led_states led_get_state(void) charge_lvl = charge_get_percent(); /* Determine which charge state to use */ new_state = charge_lvl <= led.charge_lvl_1 ? - STATE_CHARGING_LVL_1 : STATE_CHARGING_LVL_2; + STATE_CHARGING_LVL_1 : + STATE_CHARGING_LVL_2; break; case PWR_STATE_DISCHARGE_FULL: if (extpower_is_present()) { @@ -248,11 +244,13 @@ static void led_update_battery(void) int period; period = led.state_table[led.state][LED_PHASE_0].time + - led.state_table[led.state][LED_PHASE_1].time; + led.state_table[led.state][LED_PHASE_1].time; if (period) - phase = ticks % period < - led.state_table[led.state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks % period < led.state_table[led.state] + [LED_PHASE_0] + .time ? + 0 : + 1; } /* Set the color for the given state and phase */ @@ -278,8 +276,8 @@ static void led_robo_update_power(void) * power LED is off for 600 msec, on for 3 seconds. */ period = LED_POWER_ON_TICKS + LED_POWER_OFF_TICKS; - level = ticks % period < LED_POWER_OFF_TICKS ? - LED_OFF_LVL : LED_ON_LVL; + level = ticks % period < LED_POWER_OFF_TICKS ? LED_OFF_LVL : + LED_ON_LVL; ticks++; } else { level = LED_OFF_LVL; -- cgit v1.2.1 From da04dcf99291b0822537519432563ff2668fa9cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:26 -0600 Subject: board/cappy2/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1bacb0070a8b7720ffe1f031e40297f399f55311 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728135 Reviewed-by: Jeremy Bettis --- board/cappy2/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/cappy2/cbi_ssfc.h b/board/cappy2/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/cappy2/cbi_ssfc.h +++ b/board/cappy2/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 6cd92bda4ff6f1fbaaf2a6f84121c99f4b184fa6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:09 -0600 Subject: include/accelgyro.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide097f3aaed14fd3d393ccaf0624443afb59ceac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730198 Reviewed-by: Jeremy Bettis --- include/accelgyro.h | 50 +++++++++++++++++++------------------------------- 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/include/accelgyro.h b/include/accelgyro.h index be6b8061c3..3ea250ac58 100644 --- a/include/accelgyro.h +++ b/include/accelgyro.h @@ -60,9 +60,7 @@ struct accelgyro_drv { * * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_range)(struct motion_sensor_t *s, - int range, - int rnd); + int (*set_range)(struct motion_sensor_t *s, int range, int rnd); /** * Setter and getter methods for the sensor resolution. @@ -72,9 +70,8 @@ struct accelgyro_drv { * value. Otherwise, it rounds down. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_resolution)(const struct motion_sensor_t *s, - int res, - int rnd); + int (*set_resolution)(const struct motion_sensor_t *s, int res, + int rnd); int (*get_resolution)(const struct motion_sensor_t *s); /** @@ -86,12 +83,10 @@ struct accelgyro_drv { * value. Otherwise, it rounds down. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_data_rate)(const struct motion_sensor_t *s, - int rate, - int rnd); + int (*set_data_rate)(const struct motion_sensor_t *s, int rate, + int rnd); int (*get_data_rate)(const struct motion_sensor_t *s); - /** * Setter and getter methods for the sensor offset. * @s Pointer to sensor data. @@ -100,11 +95,9 @@ struct accelgyro_drv { * @return EC_SUCCESS if successful, non-zero if error. */ int (*set_offset)(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp); - int (*get_offset)(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp); + const int16_t *offset, int16_t temp); + int (*get_offset)(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); /** * Setter and getter methods for the sensor scale. * @s Pointer to sensor data. @@ -112,19 +105,16 @@ struct accelgyro_drv { * @temp: temperature when calibration was done. * @return EC_SUCCESS if successful, non-zero if error. */ - int (*set_scale)(const struct motion_sensor_t *s, - const uint16_t *scale, - int16_t temp); - int (*get_scale)(const struct motion_sensor_t *s, - uint16_t *scale, - int16_t *temp); + int (*set_scale)(const struct motion_sensor_t *s, const uint16_t *scale, + int16_t temp); + int (*get_scale)(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp); /** * Request performing/entering calibration. * Either a one shot mode (enable is not used), * or enter/exit a calibration state. */ - int (*perform_calib)(struct motion_sensor_t *s, - int enable); + int (*perform_calib)(struct motion_sensor_t *s, int enable); /** * Function that probes if supported chip is present. @@ -161,8 +151,7 @@ struct accelgyro_drv { * @data additional data if needed, activity dependent. */ int (*manage_activity)(const struct motion_sensor_t *s, - enum motionsensor_activity activity, - int enable, + enum motionsensor_activity activity, int enable, const struct ec_motion_sense_activity *data); /** * List activities managed by the sensors. @@ -171,8 +160,7 @@ struct accelgyro_drv { * @disabled bit mask of activities currently disabled. */ int (*list_activities)(const struct motion_sensor_t *s, - uint32_t *enabled, - uint32_t *disabled); + uint32_t *enabled, uint32_t *disabled); /** * Get the root mean square of current noise (ug/mdps) in the sensor. @@ -248,9 +236,9 @@ struct rgb_calibration_t { /* als driver data */ struct als_drv_data_t { - int rate; /* holds current sensor rate */ - int last_value; /* holds last als clear channel value */ - struct als_calibration_t als_cal; /* calibration data */ + int rate; /* holds current sensor rate */ + int last_value; /* holds last als clear channel value */ + struct als_calibration_t als_cal; /* calibration data */ }; #define SENSOR_APPLY_DIV_SCALE(_input, _scale) \ @@ -260,6 +248,6 @@ struct als_drv_data_t { (((_input) * (uint64_t)(_scale)) / MOTION_SENSE_DEFAULT_SCALE) /* Individual channel scale value between 0 and 2 represented in 16 bits */ -#define ALS_CHANNEL_SCALE(_x) ((_x) * MOTION_SENSE_DEFAULT_SCALE) +#define ALS_CHANNEL_SCALE(_x) ((_x)*MOTION_SENSE_DEFAULT_SCALE) #endif /* __CROS_EC_ACCELGYRO_H */ -- cgit v1.2.1 From cbf84e495d45c4e77b58fb0b62d55edad235cf67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:16 -0600 Subject: include/charge_ramp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I244dbdd3f31622f4bab56aee211dd5cba0752571 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730221 Reviewed-by: Jeremy Bettis --- include/charge_ramp.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/include/charge_ramp.h b/include/charge_ramp.h index 0745f5ef98..8dbe9823d2 100644 --- a/include/charge_ramp.h +++ b/include/charge_ramp.h @@ -11,10 +11,7 @@ #include "timer.h" /* Charge ramp state used for checking VBUS */ -enum chg_ramp_vbus_state { - CHG_RAMP_VBUS_RAMPING, - CHG_RAMP_VBUS_STABLE -}; +enum chg_ramp_vbus_state { CHG_RAMP_VBUS_RAMPING, CHG_RAMP_VBUS_STABLE }; /** * Check if VBUS is too low @@ -81,11 +78,15 @@ int chg_ramp_is_detected(void); * @voltage Negotiated charge voltage. */ void chg_ramp_charge_supplier_change(int port, int supplier, int current, - timestamp_t registration_time, int voltage); + timestamp_t registration_time, + int voltage); #else -static inline void chg_ramp_charge_supplier_change( - int port, int supplier, timestamp_t registration_time) { } +static inline void +chg_ramp_charge_supplier_change(int port, int supplier, + timestamp_t registration_time) +{ +} #endif #endif /* __CROS_EC_CHARGE_RAMP_H */ -- cgit v1.2.1 From 4ac55329893845e97fa9da1139bdf937d270e4d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:34 -0600 Subject: board/makomo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I503fc4906874b19c625a19d78f6569b9913a5bb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728644 Reviewed-by: Jeremy Bettis --- board/makomo/board.h | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/board/makomo/board.h b/board/makomo/board.h index 9919557553..465fcf0bb3 100644 --- a/board/makomo/board.h +++ b/board/makomo/board.h @@ -53,14 +53,13 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ALS #define CONFIG_CMD_ACCEL_INFO - #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL @@ -76,20 +75,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_BATTERY 2 +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BATTERY 2 /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 9b4fdfed37d4c1fdb4632d595bb4e746984289d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:45 -0600 Subject: common/charge_state_v2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32c867a8cd66b75ba3c2609702c7b39958d392e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729598 Reviewed-by: Jeremy Bettis --- common/charge_state_v2.c | 462 +++++++++++++++++++++++------------------------ 1 file changed, 223 insertions(+), 239 deletions(-) diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index f3dc811eef..396e841d07 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -35,8 +35,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHARGER, outstr) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) /* Extra debugging prints when allocating power between lid and base. */ #undef CHARGE_ALLOCATE_EXTRA_DEBUG @@ -87,8 +87,8 @@ static int prev_ac, prev_charge, prev_full, prev_disp_charge; static enum battery_present prev_bp; static int is_full; /* battery not accepting current */ static enum ec_charge_control_mode chg_ctl_mode; -static int manual_voltage; /* Manual voltage override (-1 = no override) */ -static int manual_current; /* Manual current override (-1 = no override) */ +static int manual_voltage; /* Manual voltage override (-1 = no override) */ +static int manual_current; /* Manual current override (-1 = no override) */ static unsigned int user_current_limit = -1U; test_export_static timestamp_t shutdown_target_time; static bool is_charging_progress_displayed; @@ -155,18 +155,10 @@ static int battery_was_removed; static int problems_exist; static int debugging; - -static const char * const prob_text[] = { - "static update", - "set voltage", - "set current", - "set mode", - "set input current", - "post init", - "chg params", - "batt params", - "custom profile", - "cfg secondary chg" +static const char *const prob_text[] = { + "static update", "set voltage", "set current", "set mode", + "set input current", "post init", "chg params", "batt params", + "custom profile", "cfg secondary chg" }; BUILD_ASSERT(ARRAY_SIZE(prob_text) == NUM_PROBLEM_TYPES); @@ -184,7 +176,7 @@ void charge_problem(enum problem_type p, int v) t_now = get_time(); t_diff.val = t_now.val - last_prob_time[p].val; CPRINTS("charge problem: %s, 0x%x -> 0x%x after %.6" PRId64 "s", - prob_text[p], last_prob_val[p], v, t_diff.val); + prob_text[p], last_prob_val[p], v, t_diff.val); last_prob_val[p] = v; last_prob_time[p] = t_now; } @@ -304,11 +296,12 @@ static const struct dual_battery_policy db_policy = { }; /* Add at most "value" to power_var, subtracting from total_power budget. */ -#define CHG_ALLOCATE(power_var, total_power, value) do { \ - int val_capped = MIN(value, total_power); \ - (power_var) += val_capped; \ - (total_power) -= val_capped; \ -} while (0) +#define CHG_ALLOCATE(power_var, total_power, value) \ + do { \ + int val_capped = MIN(value, total_power); \ + (power_var) += val_capped; \ + (total_power) -= val_capped; \ + } while (0) /* Update base battery information */ static void update_base_battery_info(void) @@ -346,9 +339,9 @@ static void update_base_battery_info(void) /* Newly connected battery, or change in capacity. */ if (old_flags & EC_BATT_FLAG_INVALID_DATA || - ((old_flags & EC_BATT_FLAG_BATT_PRESENT) != - (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) || - old_full_capacity != bd->full_capacity) + ((old_flags & EC_BATT_FLAG_BATT_PRESENT) != + (bd->flags & EC_BATT_FLAG_BATT_PRESENT)) || + old_full_capacity != bd->full_capacity) host_set_single_event(EC_HOST_EVENT_BATTERY); if (flags_changed) @@ -359,8 +352,8 @@ static void update_base_battery_info(void) BATT_FLAG_BAD_REMAINING_CAPACITY)) charge_base = -1; else if (bd->full_capacity > 0) - charge_base = 100 * bd->remaining_capacity - / bd->full_capacity; + charge_base = 100 * bd->remaining_capacity / + bd->full_capacity; else charge_base = 0; } @@ -380,8 +373,8 @@ static int set_base_current(int current_base, int allow_charge_base) const int otg_voltage = db_policy.otg_voltage; int ret; - ret = ec_ec_client_base_charge_control(current_base, - otg_voltage, allow_charge_base); + ret = ec_ec_client_base_charge_control(current_base, otg_voltage, + allow_charge_base); if (ret) { /* Ignore errors until the base is responsive. */ if (base_responsive) @@ -418,9 +411,9 @@ static void set_base_lid_current(int current_base, int allow_charge_base, if (prev_current_base != current_base || prev_allow_charge_base != allow_charge_base || prev_current_lid != current_lid) { - CPRINTS("Base/Lid: %d%s/%d%s mA", - current_base, allow_charge_base ? "+" : "", - current_lid, allow_charge_lid ? "+" : ""); + CPRINTS("Base/Lid: %d%s/%d%s mA", current_base, + allow_charge_base ? "+" : "", current_lid, + allow_charge_lid ? "+" : ""); } /* @@ -452,12 +445,12 @@ static void set_base_lid_current(int current_base, int allow_charge_base, return; if (allow_charge_lid) ret = charge_request(curr.requested_voltage, - curr.requested_current); + curr.requested_current); else ret = charge_request(0, 0); } else { - ret = charge_set_output_current_limit(CHARGER_SOLO, - -current_lid, otg_voltage); + ret = charge_set_output_current_limit( + CHARGER_SOLO, -current_lid, otg_voltage); } if (ret) @@ -536,7 +529,6 @@ static void charge_allocate_input_current_limit(void) const struct ec_response_battery_dynamic_info *const base_bd = &battery_dynamic[BATT_IDX_BASE]; - if (!base_connected) { set_base_lid_current(0, 0, curr.desired_input_current, 1); prev_base_battery_power = -1; @@ -553,7 +545,8 @@ static void charge_allocate_input_current_limit(void) * but the value is currently wrong, especially during transitions. */ if (total_power <= 0) { - int base_critical = charge_base >= 0 && + int base_critical = + charge_base >= 0 && charge_base < db_policy.max_charge_base_batt_to_batt; /* Discharging */ @@ -567,14 +560,14 @@ static void charge_allocate_input_current_limit(void) if (manual_noac_current_base > 0) { base_current = -manual_noac_current_base; - lid_current = - add_margin(manual_noac_current_base, - db_policy.margin_otg_current); + lid_current = add_margin( + manual_noac_current_base, + db_policy.margin_otg_current); } else { lid_current = manual_noac_current_base; - base_current = - add_margin(-manual_noac_current_base, - db_policy.margin_otg_current); + base_current = add_margin( + -manual_noac_current_base, + db_policy.margin_otg_current); } set_base_lid_current(base_current, 0, lid_current, 0); @@ -605,18 +598,20 @@ static void charge_allocate_input_current_limit(void) * touchpad events. */ if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - !base_critical) { + !base_critical) { set_base_lid_current(0, 0, 0, 0); return; } if (charge_base > db_policy.min_charge_base_otg) { int lid_current = db_policy.max_base_to_lid_current; - int base_current = add_margin(lid_current, - db_policy.margin_otg_current); + int base_current = add_margin( + lid_current, db_policy.margin_otg_current); /* Draw current from base to lid */ - set_base_lid_current(-base_current, 0, lid_current, - charge_lid < db_policy.max_charge_lid_batt_to_batt); + set_base_lid_current( + -base_current, 0, lid_current, + charge_lid < + db_policy.max_charge_lid_batt_to_batt); } else { /* * Base battery is too low, apply power to it, and allow @@ -635,8 +630,8 @@ static void charge_allocate_input_current_limit(void) int base_current = (db_policy.min_base_system_power * 1000) / db_policy.otg_voltage; - int lid_current = add_margin(base_current, - db_policy.margin_otg_current); + int lid_current = add_margin( + base_current, db_policy.margin_otg_current); set_base_lid_current(base_current, base_critical, -lid_current, 0); @@ -664,8 +659,8 @@ static void charge_allocate_input_current_limit(void) lid_system_power = charger_get_system_power() / 1000; /* Smooth system power, as it is very spiky */ - lid_system_power = smooth_value(prev_lid_system_power, - lid_system_power, db_policy.lid_system_power_smooth); + lid_system_power = smooth_value(prev_lid_system_power, lid_system_power, + db_policy.lid_system_power_smooth); prev_lid_system_power = lid_system_power; /* @@ -677,15 +672,15 @@ static void charge_allocate_input_current_limit(void) */ /* Estimate lid battery power. */ if (!(curr.batt.flags & - (BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT))) - lid_battery_power = curr.batt.current * - curr.batt.voltage / 1000; + (BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT))) + lid_battery_power = + curr.batt.current * curr.batt.voltage / 1000; if (lid_battery_power < prev_lid_battery_power) - lid_battery_power = smooth_value(prev_lid_battery_power, - lid_battery_power, db_policy.battery_power_smooth); + lid_battery_power = + smooth_value(prev_lid_battery_power, lid_battery_power, + db_policy.battery_power_smooth); if (!(curr.batt.flags & - (BATT_FLAG_BAD_DESIRED_VOLTAGE | - BATT_FLAG_BAD_DESIRED_CURRENT))) + (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT))) lid_battery_power_max = curr.batt.desired_current * curr.batt.desired_voltage / 1000; @@ -699,19 +694,20 @@ static void charge_allocate_input_current_limit(void) base_bd->desired_voltage / 1000; } if (base_battery_power < prev_base_battery_power) - base_battery_power = smooth_value(prev_base_battery_power, - base_battery_power, db_policy.battery_power_smooth); + base_battery_power = smooth_value( + prev_base_battery_power, base_battery_power, + db_policy.battery_power_smooth); base_battery_power = MIN(base_battery_power, base_battery_power_max); if (debugging) { CPRINTF("%s:\n", __func__); CPRINTF("total power: %d\n", total_power); - CPRINTF("base battery power: %d (%d)\n", - base_battery_power, base_battery_power_max); + CPRINTF("base battery power: %d (%d)\n", base_battery_power, + base_battery_power_max); CPRINTF("lid system power: %d\n", lid_system_power); CPRINTF("lid battery power: %d\n", lid_battery_power); - CPRINTF("percent base/lid: %d%% %d%%\n", - charge_base, charge_lid); + CPRINTF("percent base/lid: %d%% %d%%\n", charge_base, + charge_lid); } prev_lid_battery_power = lid_battery_power; @@ -720,30 +716,31 @@ static void charge_allocate_input_current_limit(void) if (total_power > 0) { /* Charging */ /* Allocate system power */ CHG_ALLOCATE(power_base, total_power, - db_policy.min_base_system_power); + db_policy.min_base_system_power); CHG_ALLOCATE(power_lid, total_power, lid_system_power); /* Allocate lid, then base battery power */ - lid_battery_power = add_margin(lid_battery_power, - db_policy.margin_lid_battery_power); + lid_battery_power = add_margin( + lid_battery_power, db_policy.margin_lid_battery_power); CHG_ALLOCATE(power_lid, total_power, lid_battery_power); - base_battery_power = add_margin(base_battery_power, - db_policy.margin_base_battery_power); + base_battery_power = + add_margin(base_battery_power, + db_policy.margin_base_battery_power); CHG_ALLOCATE(power_base, total_power, base_battery_power); /* Give everything else to the lid. */ CHG_ALLOCATE(power_lid, total_power, total_power); if (debugging) - CPRINTF("power: base %d mW / lid %d mW\n", - power_base, power_lid); + CPRINTF("power: base %d mW / lid %d mW\n", power_base, + power_lid); current_base = 1000 * power_base / curr.input_voltage; current_lid = 1000 * power_lid / curr.input_voltage; if (current_base > db_policy.max_lid_to_base_current) { - current_lid += (current_base - - db_policy.max_lid_to_base_current); + current_lid += (current_base - + db_policy.max_lid_to_base_current); current_base = db_policy.max_lid_to_base_current; } @@ -760,12 +757,13 @@ static void charge_allocate_input_current_limit(void) } #endif /* CONFIG_EC_EC_COMM_BATTERY_CLIENT */ -static const char * const state_list[] = { - "idle", "discharge", "charge", "precharge" -}; +static const char *const state_list[] = { "idle", "discharge", "charge", + "precharge" }; BUILD_ASSERT(ARRAY_SIZE(state_list) == NUM_STATES_V2); -static const char * const batt_pres[] = { - "NO", "YES", "NOT_SURE", +static const char *const batt_pres[] = { + "NO", + "YES", + "NOT_SURE", }; const char *mode_text[] = EC_CHARGE_MODE_TEXT; @@ -774,9 +772,9 @@ BUILD_ASSERT(ARRAY_SIZE(mode_text) == CHARGE_CONTROL_COUNT); static void dump_charge_state(void) { #define DUMP(FLD, FMT) ccprintf(#FLD " = " FMT "\n", curr.FLD) -#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg. FLD) -#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt. FLD) -#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc. FLD) +#define DUMP_CHG(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.chg.FLD) +#define DUMP_BATT(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.batt.FLD) +#define DUMP_OCPC(FLD, FMT) ccprintf("\t" #FLD " = " FMT "\n", curr.ocpc.FLD) enum ec_charge_control_mode cmode = get_chg_ctrl_mode(); @@ -846,8 +844,8 @@ static void dump_charge_state(void) ccprintf("battery_was_removed = %d\n", battery_was_removed); ccprintf("debug output = %s\n", debugging ? "on" : "off"); ccprintf("Battery sustainer = %s (%d%% ~ %d%%)\n", - battery_sustainer_enabled() ? "on" : "off", - sustain_soc.lower, sustain_soc.upper); + battery_sustainer_enabled() ? "on" : "off", sustain_soc.lower, + sustain_soc.upper); #undef DUMP } @@ -901,14 +899,13 @@ static void show_charging_progress(void) dsoc = charge_get_display_charge(); if (rv) CPRINTS("Battery %d%% (Display %d.%d %%) / ??h:?? %s%s", - curr.batt.state_of_charge, - dsoc / 10, dsoc % 10, + curr.batt.state_of_charge, dsoc / 10, dsoc % 10, to_full ? "to full" : "to empty", is_full ? ", not accepting current" : ""); else CPRINTS("Battery %d%% (Display %d.%d %%) / %dh:%d %s%s", - curr.batt.state_of_charge, - dsoc / 10, dsoc % 10, minutes / 60, minutes % 60, + curr.batt.state_of_charge, dsoc / 10, dsoc % 10, + minutes / 60, minutes % 60, to_full ? "to full" : "to empty", is_full ? ", not accepting current" : ""); @@ -1019,9 +1016,9 @@ static int charge_request(int voltage, int current) */ if (curr.ocpc.active_chg_chip == CHARGER_SECONDARY) { if ((current >= 0) || (voltage >= 0)) - r3 = ocpc_config_secondary_charger(&curr.desired_input_current, - &curr.ocpc, - voltage, current); + r3 = ocpc_config_secondary_charger( + &curr.desired_input_current, &curr.ocpc, + voltage, current); if (r3 != EC_SUCCESS) charge_problem(PR_CFG_SEC_CHG, r3); } @@ -1140,9 +1137,8 @@ static inline int battery_too_low(void) curr.batt.voltage <= batt_info->voltage_min)); } -__attribute__((weak)) -enum critical_shutdown board_critical_shutdown_check( - struct charge_state_data *curr) +__attribute__((weak)) enum critical_shutdown +board_critical_shutdown_check(struct charge_state_data *curr) { #ifdef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF return CRITICAL_SHUTDOWN_CUTOFF; @@ -1173,21 +1169,21 @@ static int is_battery_critical(void) } if (battery_too_low() && !curr.batt_is_charging) { - CPRINTS("Low battery: %d%%, %dmV", - curr.batt.state_of_charge, curr.batt.voltage); + CPRINTS("Low battery: %d%%, %dmV", curr.batt.state_of_charge, + curr.batt.voltage); return 1; } return 0; } - /* - * If the battery is at extremely low charge (and discharging) or extremely - * high temperature, the EC will notify the AP and start a timer. If the - * critical condition is not corrected before the timeout expires, the EC - * will shut down the AP (if the AP is not already off) and then optionally - * hibernate or cut off battery. - */ +/* + * If the battery is at extremely low charge (and discharging) or extremely + * high temperature, the EC will notify the AP and start a timer. If the + * critical condition is not corrected before the timeout expires, the EC + * will shut down the AP (if the AP is not already off) and then optionally + * hibernate or cut off battery. + */ static int shutdown_on_critical_battery(void) { if (!is_battery_critical()) { @@ -1199,8 +1195,8 @@ static int shutdown_on_critical_battery(void) if (!shutdown_target_time.val) { /* Start count down timer */ CPRINTS("Start shutdown due to critical battery"); - shutdown_target_time.val = get_time().val - + CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US; + shutdown_target_time.val = + get_time().val + CRITICAL_BATTERY_SHUTDOWN_TIMEOUT_US; #ifdef CONFIG_HOSTCMD_EVENTS if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) host_set_single_event(EC_HOST_EVENT_BATTERY_SHUTDOWN); @@ -1245,8 +1241,7 @@ static int shutdown_on_critical_battery(void) } } else { /* Timeout waiting for AP to shut down, so kill it */ - CPRINTS( - "charge force shutdown due to critical battery"); + CPRINTS("charge force shutdown due to critical battery"); chipset_force_shutdown(CHIPSET_SHUTDOWN_BATTERY_CRIT); } @@ -1295,16 +1290,16 @@ static void notify_host_of_low_battery_voltage(void) THROTTLE_SRC_BAT_VOLTAGE); uvp_throttle_start_time = get_time(); } else if (uvp_throttle_start_time.val && - (curr.batt.voltage < BAT_LOW_VOLTAGE_THRESH + - BAT_UVP_HYSTERESIS)) { + (curr.batt.voltage < + BAT_LOW_VOLTAGE_THRESH + BAT_UVP_HYSTERESIS)) { /* * Reset the timer when we are not sure if VBAT can stay * above BAT_LOW_VOLTAGE_THRESH after we stop throttling. */ uvp_throttle_start_time = get_time(); } else if (uvp_throttle_start_time.val && - (get_time().val > uvp_throttle_start_time.val + - BAT_UVP_TIMEOUT_US)) { + (get_time().val > + uvp_throttle_start_time.val + BAT_UVP_TIMEOUT_US)) { throttle_ap(THROTTLE_OFF, THROTTLE_SOFT, THROTTLE_SRC_BAT_VOLTAGE); uvp_throttle_start_time.val = 0; @@ -1328,8 +1323,8 @@ static void notify_host_of_over_current(struct batt_params *batt) throttle_ap(THROTTLE_ON, THROTTLE_SOFT, THROTTLE_SRC_BAT_DISCHG_CURRENT); } else if (ocp_throttle_start_time.val && - (get_time().val > ocp_throttle_start_time.val + - BAT_OCP_TIMEOUT_US)) { + (get_time().val > + ocp_throttle_start_time.val + BAT_OCP_TIMEOUT_US)) { /* * Clear the timer and notify AP to stop throttling if * we haven't seen over current for BAT_OCP_TIMEOUT_US. @@ -1361,8 +1356,8 @@ static int battery_outside_charging_temperature(void) if (curr.batt.flags & BATT_FLAG_BAD_TEMPERATURE) return 0; - if((curr.batt.desired_voltage == 0) && - (curr.batt.desired_current == 0)){ + if ((curr.batt.desired_voltage == 0) && + (curr.batt.desired_current == 0)) { max_c = batt_info->start_charging_max_c; min_c = batt_info->start_charging_min_c; } else { @@ -1370,9 +1365,7 @@ static int battery_outside_charging_temperature(void) min_c = batt_info->charging_min_c; } - - if ((batt_temp_c >= max_c) || - (batt_temp_c <= min_c)) { + if ((batt_temp_c >= max_c) || (batt_temp_c <= min_c)) { return 1; } return 0; @@ -1385,8 +1378,8 @@ static void sustain_battery_soc(void) int rv; /* If either AC or battery is not present, nothing to do. */ - if (!curr.ac || curr.batt.is_present != BP_YES - || !battery_sustainer_enabled()) + if (!curr.ac || curr.batt.is_present != BP_YES || + !battery_sustainer_enabled()) return; soc = charge_get_display_charge() / 10; @@ -1402,7 +1395,8 @@ static void sustain_battery_soc(void) /* Going up */ if (sustain_soc.upper < soc) mode = sustain_soc.upper == sustain_soc.lower ? - CHARGE_CONTROL_IDLE : CHARGE_CONTROL_DISCHARGE; + CHARGE_CONTROL_IDLE : + CHARGE_CONTROL_DISCHARGE; break; case CHARGE_CONTROL_IDLE: /* Discharging naturally */ @@ -1422,8 +1416,8 @@ static void sustain_battery_soc(void) return; rv = set_chg_ctrl_mode(mode); - CPRINTS("%s: %s control mode to %s", - __func__, rv == EC_SUCCESS ? "Switched" : "Failed to switch", + CPRINTS("%s: %s control mode to %s", __func__, + rv == EC_SUCCESS ? "Switched" : "Failed to switch", mode_text[mode]); } @@ -1465,20 +1459,19 @@ static void bat_low_voltage_throttle_reset(void) { uvp_throttle_start_time.val = 0; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - bat_low_voltage_throttle_reset, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, bat_low_voltage_throttle_reset, HOOK_PRIO_DEFAULT); #endif static int get_desired_input_current(enum battery_present batt_present, - const struct charger_info * const info) + const struct charger_info *const info) { if (batt_present == BP_YES || system_is_locked() || base_connected) { #ifdef CONFIG_CHARGE_MANAGER int ilim = charge_manager_get_charger_current(); return ilim == CHARGE_CURRENT_UNINITIALIZED ? - CHARGE_CURRENT_UNINITIALIZED : - MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim); + CHARGE_CURRENT_UNINITIALIZED : + MAX(CONFIG_CHARGER_INPUT_CURRENT, ilim); #else return CONFIG_CHARGER_INPUT_CURRENT; #endif @@ -1498,9 +1491,9 @@ static void wakeup_battery(int *need_static) set_charge_state(ST_IDLE); curr.requested_voltage = 0; curr.requested_current = 0; - } else if (curr.state == ST_PRECHARGE - && (get_time().val > precharge_start_time.val + - PRECHARGE_TIMEOUT_US)) { + } else if (curr.state == ST_PRECHARGE && + (get_time().val > + precharge_start_time.val + PRECHARGE_TIMEOUT_US)) { /* We've tried long enough, give up */ CPRINTS("battery seems to be dead"); battery_seems_dead = 1; @@ -1531,9 +1524,10 @@ static void deep_charge_battery(int *need_static) /* Deep charge time out , do nothing */ curr.requested_voltage = 0; curr.requested_current = 0; - } else if (curr.state == ST_PRECHARGE - && (get_time().val > precharge_start_time.val + - CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT)) { + } else if (curr.state == ST_PRECHARGE && + (get_time().val > + precharge_start_time.val + + CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT)) { /* We've tried long enough, give up */ CPRINTS("Precharge for low voltage timed out"); set_charge_state(ST_IDLE); @@ -1552,13 +1546,11 @@ static void deep_charge_battery(int *need_static) } } - static void revive_battery(int *need_static) { - if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD) - && curr.requested_voltage == 0 - && curr.requested_current == 0 - && curr.batt.state_of_charge == 0) { + if (IS_ENABLED(CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD) && + curr.requested_voltage == 0 && curr.requested_current == 0 && + curr.batt.state_of_charge == 0) { /* * Battery is dead, give precharge current * TODO (crosbug.com/p/29467): remove this workaround @@ -1566,10 +1558,9 @@ static void revive_battery(int *need_static) */ curr.requested_voltage = batt_info->voltage_max; curr.requested_current = batt_info->precharge_current; - } else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT) - && curr.requested_voltage == 0 - && curr.requested_current == 0 - && battery_seems_disconnected) { + } else if (IS_ENABLED(CONFIG_BATTERY_REVIVE_DISCONNECT) && + curr.requested_voltage == 0 && curr.requested_current == 0 && + battery_seems_disconnected) { /* * Battery is in disconnect state. Apply a * current to kick it out of this state. @@ -1577,8 +1568,8 @@ static void revive_battery(int *need_static) CPRINTS("found battery in disconnect state"); curr.requested_voltage = batt_info->voltage_max; curr.requested_current = batt_info->precharge_current; - } else if (curr.state == ST_PRECHARGE - || battery_seems_dead || battery_was_removed) { + } else if (curr.state == ST_PRECHARGE || battery_seems_dead || + battery_was_removed) { CPRINTS("battery woke up"); /* Update the battery-specific values */ batt_info = battery_get_info(); @@ -1594,7 +1585,7 @@ void charger_task(void *u) int sleep_usec; int battery_critical; int need_static = 1; - const struct charger_info * const info = charger_get_info(); + const struct charger_info *const info = charger_get_info(); int prev_plt_and_desired_mw; int chgnum = 0; @@ -1622,8 +1613,8 @@ void charger_task(void *u) * as needed. */ prev_bp = BP_NOT_INIT; - curr.desired_input_current = get_desired_input_current( - curr.batt.is_present, info); + curr.desired_input_current = + get_desired_input_current(curr.batt.is_present, info); if (IS_ENABLED(CONFIG_USB_PD_PREFER_MV)) { /* init battery desired power */ @@ -1640,7 +1631,6 @@ void charger_task(void *u) battery_level_shutdown = board_set_battery_level_shutdown(); while (1) { - /* Let's see what's going on... */ curr.ts = get_time(); sleep_usec = 0; @@ -1657,8 +1647,8 @@ void charger_task(void *u) curr.ac = 0; /* System is off: if AC gets connected, reset the base. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && - !prev_ac && curr.ac) + if (chipset_in_state(CHIPSET_STATE_ANY_OFF) && !prev_ac && + curr.ac) board_base_reset(); #endif if (curr.ac != prev_ac) { @@ -1679,7 +1669,7 @@ void charger_task(void *u) if (rv != EC_SUCCESS) { charge_problem(PR_POST_INIT, rv); } else if (curr.desired_input_current != - CHARGE_CURRENT_UNINITIALIZED) { + CHARGE_CURRENT_UNINITIALIZED) { rv = charger_set_input_current_limit( chgnum, curr.desired_input_current); @@ -1727,8 +1717,8 @@ void charger_task(void *u) get_desired_input_current(prev_bp, info); if (curr.desired_input_current != CHARGE_CURRENT_UNINITIALIZED) - charger_set_input_current_limit(chgnum, - curr.desired_input_current); + charger_set_input_current_limit( + chgnum, curr.desired_input_current); hook_notify(HOOK_BATTERY_SOC_CHANGE); } @@ -1749,7 +1739,7 @@ void charger_task(void *u) * applying power to a battery we can't talk to. */ if (curr.batt.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE | - BATT_FLAG_BAD_DESIRED_CURRENT)) { + BATT_FLAG_BAD_DESIRED_CURRENT)) { curr.requested_voltage = 0; curr.requested_current = 0; } else { @@ -1805,9 +1795,9 @@ void charger_task(void *u) goto wait_for_it; } - if (IS_ENABLED(CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION) - && !(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) - && (curr.batt.voltage <= batt_info->voltage_min)) { + if (IS_ENABLED(CONFIG_BATTERY_LOW_VOLTAGE_PROTECTION) && + !(curr.batt.flags & BATT_FLAG_BAD_VOLTAGE) && + (curr.batt.voltage <= batt_info->voltage_min)) { deep_charge_battery(&need_static); goto wait_for_it; } @@ -1819,23 +1809,23 @@ void charger_task(void *u) * the battery disconnect state is one of the items used * to decide whether or not to leave safe mode. */ - battery_seems_disconnected = - battery_get_disconnect_state() == BATTERY_DISCONNECTED; + battery_seems_disconnected = battery_get_disconnect_state() == + BATTERY_DISCONNECTED; revive_battery(&need_static); set_charge_state(ST_CHARGE); -wait_for_it: - if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) - && get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) { + wait_for_it: + if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) && + get_chg_ctrl_mode() == CHARGE_CONTROL_NORMAL) { sleep_usec = charger_profile_override(&curr); if (sleep_usec < 0) charge_problem(PR_CUSTOM, sleep_usec); } - if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS) - && battery_outside_charging_temperature()) { + if (IS_ENABLED(CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS) && + battery_outside_charging_temperature()) { curr.requested_current = 0; curr.requested_voltage = 0; curr.batt.flags &= ~BATT_FLAG_WANT_CHARGE; @@ -1845,7 +1835,7 @@ wait_for_it: #ifdef CONFIG_CHARGE_MANAGER if (curr.batt.state_of_charge >= - CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT && + CONFIG_CHARGE_MANAGER_BAT_PCT_SAFE_MODE_EXIT && !battery_seems_disconnected) { /* * Sometimes the fuel gauge will report that it has @@ -1882,12 +1872,11 @@ wait_for_it: sustain_battery_soc(); if ((!(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) && - curr.batt.state_of_charge != prev_charge) || + curr.batt.state_of_charge != prev_charge) || #ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT (charge_base != prev_charge_base) || #endif - (is_full != prev_full) || - (curr.state != prev_state) || + (is_full != prev_full) || (curr.state != prev_state) || (charge_get_display_charge() != prev_disp_charge)) { show_charging_progress(); prev_charge = curr.batt.state_of_charge; @@ -1968,9 +1957,8 @@ wait_for_it: sleep_usec = CHARGE_POLL_PERIOD_SHORT; else if (sleep_usec <= 0) { /* default values depend on the state */ - if (!curr.ac && - (curr.state == ST_IDLE || - curr.state == ST_DISCHARGE)) { + if (!curr.ac && (curr.state == ST_IDLE || + curr.state == ST_DISCHARGE)) { #ifdef CONFIG_CHARGER_OTG int output_current = curr.output_current; #else @@ -1980,9 +1968,10 @@ wait_for_it: * If AP is off and we do not provide power, we * can sleep a long time. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_ANY_SUSPEND) - && output_current == 0) + if (chipset_in_state( + CHIPSET_STATE_ANY_OFF | + CHIPSET_STATE_ANY_SUSPEND) && + output_current == 0) sleep_usec = CHARGE_POLL_PERIOD_VERY_LONG; else @@ -2062,15 +2051,14 @@ wait_for_it: } } - /*****************************************************************************/ /* Exported functions */ int charge_want_shutdown(void) { return (curr.state == ST_DISCHARGE) && - !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) && - (curr.batt.state_of_charge < battery_level_shutdown); + !(curr.batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) && + (curr.batt.state_of_charge < battery_level_shutdown); } int charge_prevent_power_on(int power_button_pressed) @@ -2103,14 +2091,14 @@ int charge_prevent_power_on(int power_button_pressed) if (current_batt_params->is_present != BP_YES || #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE (current_batt_params->flags & BATT_FLAG_IMBALANCED_CELL && - current_batt_params->state_of_charge < - CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) || + current_batt_params->state_of_charge < + CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON) || #endif #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED || #endif current_batt_params->state_of_charge < - CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) + CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) prevent_power_on = 1; #if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON) && \ @@ -2123,13 +2111,14 @@ int charge_prevent_power_on(int power_button_pressed) #if defined(CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT) && \ defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC) else if (charge_manager_get_power_limit_uw() >= - CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT * 1000 + CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT * + 1000 #ifdef CONFIG_BATTERY_REVIVE_DISCONNECT - && battery_get_disconnect_state() == - BATTERY_NOT_DISCONNECTED + && battery_get_disconnect_state() == + BATTERY_NOT_DISCONNECTED #endif - && (current_batt_params->state_of_charge >= - CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)) + && (current_batt_params->state_of_charge >= + CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC)) prevent_power_on = 0; #endif } @@ -2140,18 +2129,18 @@ int charge_prevent_power_on(int power_button_pressed) * except when auto-power-on at EC startup and the battery * is physically present. */ - prevent_power_on &= (system_is_locked() || (automatic_power_on + prevent_power_on &= + (system_is_locked() || (automatic_power_on #ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM - && battery_hw_present() == BP_YES + && battery_hw_present() == BP_YES #endif - )); + )); #endif /* CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON */ #ifdef CONFIG_CHARGE_MANAGER /* Always prevent power on until charge current is initialized */ - if (extpower_is_present() && - (charge_manager_get_charger_current() == - CHARGE_CURRENT_UNINITIALIZED)) + if (extpower_is_present() && (charge_manager_get_charger_current() == + CHARGE_CURRENT_UNINITIALIZED)) prevent_power_on = 1; #ifdef CONFIG_BATTERY_HW_PRESENT_CUSTOM /* @@ -2161,19 +2150,19 @@ int charge_prevent_power_on(int power_button_pressed) if (extpower_is_present() && battery_hw_present() == BP_NO #ifdef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON && charge_manager_get_power_limit_uw() < - CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000 + CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000 #endif /* CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON */ - ) + ) prevent_power_on = 1; #endif /* CONFIG_BATTERY_HW_PRESENT_CUSTOM */ #endif /* CONFIG_CHARGE_MANAGER */ - /* - * Prevent power on if there is no battery nor ac power. This - * happens when the servo is powering the EC to flash it. Only include - * this logic for boards in initial bring up phase since this won't - * happen for released boards. - */ + /* + * Prevent power on if there is no battery nor ac power. This + * happens when the servo is powering the EC to flash it. Only + * include this logic for boards in initial bring up phase since + * this won't happen for released boards. + */ #ifdef CONFIG_SYSTEM_UNLOCKED if (!current_batt_params->is_present && !curr.ac) prevent_power_on = 1; @@ -2317,8 +2306,7 @@ int charge_set_input_current_limit(int ma, int mv) * browning out due to insufficient input current. */ if (curr.batt.is_present != BP_YES && !system_is_locked() && - !base_connected) { - + !base_connected) { int prev_input = 0; charger_get_input_current_limit(chgnum, &prev_input); @@ -2333,8 +2321,8 @@ int charge_set_input_current_limit(int ma, int mv) * input system power. */ - if (mv > 0 && mv * curr.desired_input_current > - PD_MAX_POWER_MW * 1000) + if (mv > 0 && + mv * curr.desired_input_current > PD_MAX_POWER_MW * 1000) ma = (PD_MAX_POWER_MW * 1000) / mv; /* * If the active charger has already been initialized to at @@ -2346,11 +2334,11 @@ int charge_set_input_current_limit(int ma, int mv) if (prev_input >= ma) return EC_SUCCESS; #endif - /* - * If the current needs lowered due to PD max power - * considerations, or needs raised for the selected active - * charger chip, fall through to set. - */ + /* + * If the current needs lowered due to PD max power + * considerations, or needs raised for the selected + * active charger chip, fall through to set. + */ #endif /* CONFIG_USB_POWER_DELIVERY */ } @@ -2468,8 +2456,8 @@ charge_command_charge_control(struct host_cmd_handler_args *args) if (p->cmd == EC_CHARGE_CONTROL_CMD_SET) { if (p->mode == CHARGE_CONTROL_NORMAL) { rv = battery_sustainer_set( - p->sustain_soc.lower, - p->sustain_soc.upper); + p->sustain_soc.lower, + p->sustain_soc.upper); if (rv == EC_RES_UNAVAILABLE) return EC_RES_UNAVAILABLE; if (rv) @@ -2565,7 +2553,6 @@ charge_command_charge_state(struct host_cmd_handler_args *args) chgnum = in->chgnum; switch (in->cmd) { - case CHARGE_STATE_CMD_GET_STATE: out->get_state.ac = curr.ac; out->get_state.chg_voltage = curr.chg.voltage; @@ -2577,18 +2564,18 @@ charge_command_charge_state(struct host_cmd_handler_args *args) case CHARGE_STATE_CMD_GET_PARAM: val = 0; - if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) - && in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN - && in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) { + if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) && + in->get_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN && + in->get_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) { /* custom profile params */ - rv = charger_profile_override_get_param( + rv = charger_profile_override_get_param( in->get_param.param, &val); - } else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG) - && in->get_param.param >= CS_PARAM_DEBUG_MIN - && in->get_param.param <= CS_PARAM_DEBUG_MAX) { + } else if (IS_ENABLED(CONFIG_CHARGE_STATE_DEBUG) && + in->get_param.param >= CS_PARAM_DEBUG_MIN && + in->get_param.param <= CS_PARAM_DEBUG_MAX) { /* debug params */ - rv = charge_get_charge_state_debug( - in->get_param.param, &val); + rv = charge_get_charge_state_debug(in->get_param.param, + &val); } else { /* standard params */ switch (in->get_param.param) { @@ -2615,10 +2602,11 @@ charge_command_charge_state(struct host_cmd_handler_args *args) */ if ((curr.batt.is_present != BP_YES || curr.batt.state_of_charge < - CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT) - && charge_manager_get_power_limit_uw() < - CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW - * 1000 && system_is_locked()) + CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT) && + charge_manager_get_power_limit_uw() < + CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW * + 1000 && + system_is_locked()) val = 1; else #endif @@ -2639,11 +2627,11 @@ charge_command_charge_state(struct host_cmd_handler_args *args) return EC_RES_ACCESS_DENIED; val = in->set_param.value; - if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) - && in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN - && in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) { + if (IS_ENABLED(CONFIG_CHARGER_PROFILE_OVERRIDE) && + in->set_param.param >= CS_PARAM_CUSTOM_PROFILE_MIN && + in->set_param.param <= CS_PARAM_CUSTOM_PROFILE_MAX) { /* custom profile params */ - rv = charger_profile_override_set_param( + rv = charger_profile_override_set_param( in->set_param.param, val); } else { switch (in->set_param.param) { @@ -2669,7 +2657,6 @@ charge_command_charge_state(struct host_cmd_handler_args *args) break; default: rv = EC_RES_INVALID_PARAM; - } } break; @@ -2705,13 +2692,11 @@ static int command_pwr_avg(int argc, char **argv) avg_ma = battery_get_avg_current(); avg_mw = avg_mv * avg_ma / 1000; - ccprintf("mv = %d\nma = %d\nmw = %d\n", - avg_mv, avg_ma, avg_mw); + ccprintf("mv = %d\nma = %d\nmw = %d\n", avg_mv, avg_ma, avg_mw); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg, - NULL, +DECLARE_CONSOLE_COMMAND(pwr_avg, command_pwr_avg, NULL, "Get 1 min power average"); #endif /* CONFIG_CMD_PWR_AVG */ @@ -2729,7 +2714,7 @@ static int command_chgstate(int argc, char **argv) if (!parse_bool(argv[2], &val)) return EC_ERROR_PARAM2; rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_IDLE : - CHARGE_CONTROL_NORMAL); + CHARGE_CONTROL_NORMAL); if (rv) return rv; } else if (!strcasecmp(argv[1], "discharge")) { @@ -2738,7 +2723,7 @@ static int command_chgstate(int argc, char **argv) if (!parse_bool(argv[2], &val)) return EC_ERROR_PARAM2; rv = set_chg_ctrl_mode(val ? CHARGE_CONTROL_DISCHARGE : - CHARGE_CONTROL_NORMAL); + CHARGE_CONTROL_NORMAL); if (rv) return rv; } else if (!strcasecmp(argv[1], "debug")) { @@ -2812,9 +2797,8 @@ static int command_chgdualdebug(int argc, char **argv) return EC_ERROR_PARAM1; } } else { - ccprintf("Base/Lid: %d%s/%d mA\n", - prev_current_base, prev_allow_charge_base ? "+" : "", - prev_current_lid); + ccprintf("Base/Lid: %d%s/%d mA\n", prev_current_base, + prev_allow_charge_base ? "+" : "", prev_current_lid); } return EC_SUCCESS; -- cgit v1.2.1 From 9ea95719243c390abc8cb36d92fd503e4df8ce7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:48 -0600 Subject: board/ezkinil/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic331e3ff9a46bf002a23bf02a57743afad04b640 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728350 Reviewed-by: Jeremy Bettis --- board/ezkinil/board.h | 105 ++++++++++++++++++++------------------------------ 1 file changed, 41 insertions(+), 64 deletions(-) diff --git a/board/ezkinil/board.h b/board/ezkinil/board.h index 72ccbc78d2..9c784e3397 100644 --- a/board/ezkinil/board.h +++ b/board/ezkinil/board.h @@ -40,38 +40,34 @@ #define TUSB544_I2C_ADDR_FLAGS1 0x0F /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_DP1_HPD GPIO_EC_DP1_HPD -#define IOEX_HDMI_CONN_HPD_3V3_DB IOEX_USB_C1_PPC_ILIM_3A_EN +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_DP1_HPD GPIO_EC_DP1_HPD +#define IOEX_HDMI_CONN_HPD_3V3_DB IOEX_USB_C1_PPC_ILIM_3A_EN #ifndef __ASSEMBLER__ -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_AP19B8M, @@ -85,11 +81,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -98,11 +90,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -153,57 +141,46 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBA1_RETIMER_TUSB522 \ - (BIT(EZKINIL_DB_T_OPT2_USBAC)) +#define HAS_USBA1_RETIMER_TUSB522 (BIT(EZKINIL_DB_T_OPT2_USBAC)) static inline bool ec_config_has_usba1_retimer_tusb522(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBA1_RETIMER_TUSB522); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBA1_RETIMER_TUSB522); } -#define HAS_USBC1_RETIMER_PS8743 \ - (BIT(EZKINIL_DB_T_OPT2_USBAC)) +#define HAS_USBC1_RETIMER_PS8743 (BIT(EZKINIL_DB_T_OPT2_USBAC)) static inline bool ec_config_has_usbc1_retimer_ps8743(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8743); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743); } -#define HAS_USBC1_RETIMER_TUSB544 \ - (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) +#define HAS_USBC1_RETIMER_TUSB544 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) static inline bool ec_config_has_usbc1_retimer_tusb544(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_TUSB544); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } -#define HAS_HDMI_CONN_HPD \ - (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) +#define HAS_HDMI_CONN_HPD (BIT(EZKINIL_DB_T_OPT1_USBC_HDMI)) static inline bool ec_config_has_hdmi_conn_hpd(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_CONN_HPD); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD); } /* TODO: Fill in with GPIO values */ -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB_C0_HPD \ - : (ec_config_has_usbc1_retimer_ps8743()) \ - ? GPIO_DP1_HPD \ - : GPIO_DP2_HPD) +#define PORT_TO_HPD(port) \ + ((port == 0) ? GPIO_USB_C0_HPD : \ + (ec_config_has_usbc1_retimer_ps8743()) ? GPIO_DP1_HPD : \ + GPIO_DP2_HPD) extern const struct usb_mux usbc1_tusb544; extern const struct usb_mux usbc1_ps8818; -- cgit v1.2.1 From fad2362b4286f44d0589d71f1954d7b2b16720a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:02 -0600 Subject: board/moli/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1434a18ef779db0014c97b241b6a689dfac3164 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728691 Reviewed-by: Jeremy Bettis --- board/moli/led.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/board/moli/led.c b/board/moli/led.c index 4f04ecdf43..8e30f20c5e 100644 --- a/board/moli/led.c +++ b/board/moli/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* * When pulsing is enabled, brightness is incremented by every @@ -231,8 +231,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|blue|amber|off|alert|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|blue|amber|off|alert|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -251,8 +250,8 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness) return set_color(id, LED_OFF, 0); } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = -- cgit v1.2.1 From ef6a1acbdba6a586a5a38bbf54d1be7a4cc48897 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:11 -0600 Subject: board/guybrush/board_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I994369af065796b5ff4b7914dc29029c8e5bfdb6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728438 Reviewed-by: Jeremy Bettis --- board/guybrush/board_fw_config.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/guybrush/board_fw_config.c b/board/guybrush/board_fw_config.c index c919d82851..7c29112f2d 100644 --- a/board/guybrush/board_fw_config.c +++ b/board/guybrush/board_fw_config.c @@ -9,14 +9,15 @@ bool board_is_convertible(void) { return (get_fw_config_field(FW_CONFIG_FORM_FACTOR_OFFSET, - FW_CONFIG_FORM_FACTOR_WIDTH) - == FW_CONFIG_FORM_FACTOR_CONVERTIBLE); + FW_CONFIG_FORM_FACTOR_WIDTH) == + FW_CONFIG_FORM_FACTOR_CONVERTIBLE); } bool board_has_kblight(void) { return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET, - FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES); + FW_CONFIG_KBLIGHT_WIDTH) == + FW_CONFIG_KBLIGHT_YES); } enum board_usb_c1_mux board_get_usb_c1_mux(void) -- cgit v1.2.1 From 36fb7d386dd1890b3966d3e8b118bf2c4f9c1fa0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:02 -0600 Subject: chip/npcx/system-npcx9.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e178e0e07b1af5427398c897583852c130529fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729441 Reviewed-by: Jeremy Bettis --- chip/npcx/system-npcx9.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 230 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/npcx/system-npcx9.c diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c deleted file mode 120000 index 48088614a0..0000000000 --- a/chip/npcx/system-npcx9.c +++ /dev/null @@ -1 +0,0 @@ -system-npcx7.c \ No newline at end of file diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c new file mode 100644 index 0000000000..b3a8aec6fd --- /dev/null +++ b/chip/npcx/system-npcx9.c @@ -0,0 +1,230 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +/* System module driver depends on chip series for Chrome EC */ +#include "common.h" +#include "console.h" +#include "cpu.h" +#include "ec_commands.h" +#include "hooks.h" +#include "lct_chip.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "util.h" +#include "gpio.h" +#include "hwtimer_chip.h" +#include "system_chip.h" +#include "rom_chip.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) + +/* Macros for last 32K ram block */ +#define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) +/* Higher bits are reserved and need to be masked */ +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) + +/*****************************************************************************/ +/* IC specific low-level driver depends on chip series */ + +void system_mpu_config(void) +{ +} + +#ifdef CONFIG_HIBERNATE_PSL +#ifndef NPCX_PSL_MODE_SUPPORT +#error "Do not enable CONFIG_HIBERNATE_PSL if npcx ec doesn't support PSL mode!" +#endif + +static enum psl_pin_t system_gpio_to_psl(enum gpio_signal signal) +{ + enum psl_pin_t psl_no; + const struct gpio_info *g = gpio_list + signal; + + if (g->port == GPIO_PORT_D && g->mask == MASK_PIN2) /* GPIOD2 */ + psl_no = PSL_IN1; + else if (g->port == GPIO_PORT_0 && (g->mask & 0x07)) /* GPIO00/01/02 */ + psl_no = GPIO_MASK_TO_NUM(g->mask) + 1; + else + psl_no = PSL_NONE; + + return psl_no; +} + +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 +void system_set_psl_gpo(int level) +{ + if (level) + SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL); + else + CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL); +} +#endif + +void system_enter_psl_mode(void) +{ + /* Configure pins from GPIOs to PSL which rely on VSBY power rail. */ + gpio_config_module(MODULE_PMU, 1); + + /* + * In npcx7, only physical PSL_IN pins can pull PSL_OUT to high and + * reboot ec. + * In npcx9, LCT timeout event can also pull PSL_OUT. + * We won't decide the wake cause now but only mark we are entering + * hibernation via PSL. + * The actual wakeup cause will be checked by the PSL input event bits + * when ec reboots. + */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL; + +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + /* + * If pulse mode is enabled, the VCC power is turned off by the + * external component (Ex: PMIC) but PSL_OUT. So we can just return + * here. + */ + if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN)) + return; +#endif + + /* + * Pull PSL_OUT (GPIO85) to low to cut off ec's VCC power rail by + * setting bit 5 of PDOUT(8). + */ + SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5); +} + +/* Hibernate function implemented by PSL (Power Switch Logic) mode. */ +noreturn void __keep __enter_hibernate_in_psl(void) +{ + system_enter_psl_mode(); + /* Spin and wait for PSL cuts power; should never return */ + while (1) + ; +} + +static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags) +{ + /* Set PSL input events' type as level or edge trigger */ + if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) + CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); + else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING)) + SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); + + /* + * Set PSL input events' polarity is low (high-to-low) active or + * high (low-to-high) active + */ + if (flags & GPIO_HIB_WAKE_HIGH) + SET_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin); + else + CLEAR_BIT(NPCX_DEVALT(ALT_GROUP_D), 2 * psl_pin); +} + +int system_config_psl_mode(enum gpio_signal signal) +{ + enum psl_pin_t psl_no; + const struct gpio_info *g = gpio_list + signal; + + psl_no = system_gpio_to_psl(signal); + if (psl_no == PSL_NONE) + return 0; + + system_psl_type_sel(psl_no, g->flags); + return 1; +} + +#else +/** + * Hibernate function in last 32K ram block for npcx7 series. + * Do not use global variable since we also turn off data ram. + */ +noreturn void __keep __attribute__((section(".after_init"))) +__enter_hibernate_in_last_block(void) +{ + /* + * The hibernate utility is located in the last block of RAM. The size + * of each RAM block is 32KB. We turn off all blocks except last one + * for better power consumption. + */ + NPCX_RAM_PD(0) = RAM_PD_MASK & 0xFF; +#if defined(CHIP_FAMILY_NPCX7) + NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x0F; +#elif defined(CHIP_FAMILY_NPCX9) + NPCX_RAM_PD(1) = (RAM_PD_MASK >> 8) & 0x7F; +#endif + + /* Set deep idle mode */ + NPCX_PMCSR = 0x6; + + /* Enter deep idle, wake-up by GPIOs or RTC */ + asm volatile("wfi"); + + /* RTC wake-up */ + if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) + /* + * Mark wake-up reason for hibernate + * Do not call bbram_data_write directly cause of + * no stack. + */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_MTC; +#ifdef NPCX_LCT_SUPPORT + else if (IS_BIT_SET(NPCX_LCTSTAT, NPCX_LCTSTAT_EVST)) { + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_LCT; + /* Clear LCT event */ + NPCX_LCTSTAT = BIT(NPCX_LCTSTAT_EVST); + } +#endif + else + /* Otherwise, we treat it as GPIOs wake-up */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN; + + /* Start a watchdog reset */ + NPCX_WDCNT = 0x01; + /* Reload and restart Timer 0 */ + SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST); + /* Wait for timer is loaded and restart */ + while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST)) + ; + + /* Spin and wait for reboot; should never return */ + while (1) + ; +} +#endif + +/** + * Hibernate function for different Nuvoton chip series. + */ +void __hibernate_npcx_series(void) +{ +#ifdef CONFIG_HIBERNATE_PSL + __enter_hibernate_in_psl(); +#else + /* Make sure this is located in the last 32K code RAM block */ + ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE < + (32 * 1024)); + + /* Execute hibernate func in last 32K block */ + __enter_hibernate_in_last_block(); +#endif +} + +#if defined(CONFIG_HIBERNATE_PSL) +static void report_psl_wake_source(void) +{ + if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE)) + return; + + CPRINTS("PSL_CTS: 0x%x", NPCX_GLUE_PSL_CTS & 0xf); +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + CPRINTS("PSL_MCTL1 event: 0x%x", NPCX_GLUE_PSL_MCTL1 & 0x18); +#endif +} +DECLARE_HOOK(HOOK_INIT, report_psl_wake_source, HOOK_PRIO_DEFAULT); +#endif -- cgit v1.2.1 From 212399eca7b769ce289b527566ad38faba67f00a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:23 -0600 Subject: zephyr/include/dt-bindings/motionsense/utils.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08123c65a43f38b7cf30a494eabef12ece82d14f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730715 Reviewed-by: Jeremy Bettis --- zephyr/include/dt-bindings/motionsense/utils.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/include/dt-bindings/motionsense/utils.h b/zephyr/include/dt-bindings/motionsense/utils.h index 7f0e5f5fc8..f7a3a31927 100644 --- a/zephyr/include/dt-bindings/motionsense/utils.h +++ b/zephyr/include/dt-bindings/motionsense/utils.h @@ -7,8 +7,8 @@ #ifndef DT_BINDINGS_UTILS_H #define DT_BINDINGS_UTILS_H -#define BIT(x) (1U << (x)) -#define ROUND_UP_FLAG BIT(31) -#define USEC_PER_MSEC 1000 +#define BIT(x) (1U << (x)) +#define ROUND_UP_FLAG BIT(31) +#define USEC_PER_MSEC 1000 #endif /* DT_BINDINGS_UTILS_H */ -- cgit v1.2.1 From de9bf3c1cd447ade004c85fd0bd084c4df8a68ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:23 -0600 Subject: chip/it83xx/keyboard_raw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a6953af672cfe2bb7a3f9db801385560edd6d1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729202 Reviewed-by: Jeremy Bettis --- chip/it83xx/keyboard_raw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c index 6c7a10c463..a06856fd82 100644 --- a/chip/it83xx/keyboard_raw.c +++ b/chip/it83xx/keyboard_raw.c @@ -111,7 +111,7 @@ test_mockable void keyboard_raw_drive_column(int col) * we are using). */ IT83XX_KBS_KSOH1 = (IT83XX_KBS_KSOH1 & ~KSOH_PIN_MASK) | - ((mask >> 8) & KSOH_PIN_MASK); + ((mask >> 8) & KSOH_PIN_MASK); /* restore interrupts */ set_int_mask(int_mask); } -- cgit v1.2.1 From 2bbd3d3cf952e7b97029a193c47933cc7571a768 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:21 -0600 Subject: chip/stm32/gpio-stm32l5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibff48ffc1984b528c6490782df8e10154b3291ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729508 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-stm32l5.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/stm32/gpio-stm32l5.c b/chip/stm32/gpio-stm32l5.c index 9943edd55b..b1ab904dfc 100644 --- a/chip/stm32/gpio-stm32l5.c +++ b/chip/stm32/gpio-stm32l5.c @@ -45,7 +45,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI13); task_enable_irq(STM32_IRQ_EXTI14); task_enable_irq(STM32_IRQ_EXTI15); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 2aaaa3f347b498f0658f54c3bc9507bdb781f65c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:18 -0600 Subject: board/redrix/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I044c6fd6f666b8aed9d941241ff57621df95316b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728862 Reviewed-by: Jeremy Bettis --- board/redrix/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/redrix/usbc_config.c b/board/redrix/usbc_config.c index e463c15da1..3f47a06f1c 100644 --- a/board/redrix/usbc_config.c +++ b/board/redrix/usbc_config.c @@ -31,8 +31,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From dacb1c060cda7f4735e7c72eb3935d57b95ff41b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:40 -0600 Subject: zephyr/subsys/ap_pwrseq/include/signal_vw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08f6ae3fbe0c8c98a3df90425278898fe74c7ea5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730906 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/signal_vw.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/signal_vw.h b/zephyr/subsys/ap_pwrseq/include/signal_vw.h index d005daaa40..dba81a353f 100644 --- a/zephyr/subsys/ap_pwrseq/include/signal_vw.h +++ b/zephyr/subsys/ap_pwrseq/include/signal_vw.h @@ -6,7 +6,7 @@ #ifndef __AP_PWRSEQ_SIGNAL_VW_H__ #define __AP_PWRSEQ_SIGNAL_VW_H__ -#define PWR_SIG_TAG_VW PWR_VW_ +#define PWR_SIG_TAG_VW PWR_VW_ /* * Generate enums for the virtual wire signals. @@ -21,13 +21,13 @@ enum pwr_sig_vw { #if HAS_VW_SIGNALS -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_VW_ENUM) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_VW_ENUM) #endif - PWR_SIG_VW_COUNT + PWR_SIG_VW_COUNT }; -#undef PWR_VW_ENUM -#undef TAG_VW +#undef PWR_VW_ENUM +#undef TAG_VW /** * @brief Get the value of the virtual wire signal. -- cgit v1.2.1 From 6b013653aeab341966f2b6a7743c4f07192537d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:16 -0600 Subject: zephyr/projects/intelrvp/include/gpio_map.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19bba32ce2bd8be4fbb554bc855cb0c1b82f315a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730774 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/include/gpio_map.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h index 3263007880..01110dbe7d 100644 --- a/zephyr/projects/intelrvp/include/gpio_map.h +++ b/zephyr/projects/intelrvp/include/gpio_map.h @@ -6,12 +6,12 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#define GPIO_EN_PP5000 GPIO_UNIMPLEMENTED -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define GPIO_EN_PP5000 GPIO_UNIMPLEMENTED +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A /* TODO: Implement GPIO_ENTERING_RW in IOEX */ #ifdef CONFIG_BOARD_MTLRVP_NPCX -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #endif /* CONFIG_BOARD_MTLRVP_NPCK */ #endif /* __ZEPHYR_GPIO_MAP_H */ -- cgit v1.2.1 From efaa2547379a1e65f73117fa07a56799c931d6da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:32 -0600 Subject: chip/stm32/usb_dwc_stream.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec0867464e884da16e7fb0eb0502ecf4b2028a36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729574 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_stream.h | 192 ++++++++++++++++++++------------------------ 1 file changed, 85 insertions(+), 107 deletions(-) diff --git a/chip/stm32/usb_dwc_stream.h b/chip/stm32/usb_dwc_stream.h index e46e7a929c..979f0a7e72 100644 --- a/chip/stm32/usb_dwc_stream.h +++ b/chip/stm32/usb_dwc_stream.h @@ -54,7 +54,6 @@ struct usb_stream_config { extern struct consumer_ops const usb_stream_consumer_ops; extern struct producer_ops const usb_stream_producer_ops; - /* * Convenience macro for defining USB streams and their associated state and * buffers. @@ -92,26 +91,19 @@ extern struct producer_ops const usb_stream_producer_ops; * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ - static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ - static int CONCAT2(NAME, _is_reset_); \ - static int CONCAT2(NAME, _overflow_); \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ +#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE, \ + RX_QUEUE, TX_QUEUE) \ + \ + static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE]; \ + static uint8_t CONCAT2(NAME, _buf_tx_)[TX_SIZE]; \ + static int CONCAT2(NAME, _is_reset_); \ + static int CONCAT2(NAME, _overflow_); \ + static void CONCAT2(NAME, _deferred_tx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ + static void CONCAT2(NAME, _deferred_rx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ struct usb_stream_config const NAME = { \ .endpoint = ENDPOINT, \ .is_reset = &CONCAT2(NAME, _is_reset_), \ @@ -130,94 +122,80 @@ extern struct producer_ops const usb_stream_producer_ops; .queue = &RX_QUEUE, \ .ops = &usb_stream_producer_ops, \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { tx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { rx_stream_handler(&NAME); } \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_epN_tx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_epN_rx(ENDPOINT); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_expected = 0, \ - .out_data = 0, \ - .out_databuffer = CONCAT2(NAME, _buf_rx_), \ - .out_databuffer_max = RX_SIZE, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = CONCAT2(NAME, _buf_tx_), \ - .in_databuffer_max = TX_SIZE, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = RX_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _deferred_tx_)(void) \ + { \ + tx_stream_handler(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_rx_)(void) \ + { \ + rx_stream_handler(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_epN_tx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_epN_rx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_stream_event(&NAME, evt); \ + } \ + struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ + .max_packet = USB_MAX_PACKET_SIZE, \ + .tx_fifo = ENDPOINT, \ + .out_pending = 0, \ + .out_expected = 0, \ + .out_data = 0, \ + .out_databuffer = CONCAT2(NAME, _buf_rx_), \ + .out_databuffer_max = RX_SIZE, \ + .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ + .in_packets = 0, \ + .in_pending = 0, \ + .in_data = 0, \ + .in_databuffer = CONCAT2(NAME, _buf_tx_), \ + .in_databuffer_max = TX_SIZE, \ + .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ + }; \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ CONCAT2(NAME, _ep_event)); /* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) +#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \ + TX_SIZE, RX_QUEUE, TX_QUEUE) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE) /* * Handle USB and Queue request in a deferred callback. @@ -232,6 +210,6 @@ int tx_stream_handler(struct usb_stream_config const *config); void usb_stream_tx(struct usb_stream_config const *config); void usb_stream_rx(struct usb_stream_config const *config); void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt); + enum usb_ep_event evt); #endif /* __CROS_EC_USB_STREAM_H */ -- cgit v1.2.1 From 13d7af2a7630f5469e4c554f5817da7e828ecc62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:26 -0600 Subject: board/primus/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73b635decfd8b5b50aa3735a57cbb6321d047a2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727758 Reviewed-by: Jeremy Bettis --- board/primus/charger.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/primus/charger.c diff --git a/board/primus/charger.c b/board/primus/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/primus/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/primus/charger.c b/board/primus/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/primus/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From 9570afd9412494df9fbe6c4edbaf7567e44bc906 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:00 -0600 Subject: power/mt8183.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib68b0300db2adbbf3064b78db8c15460d1e61b8e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727063 Reviewed-by: Jeremy Bettis --- power/mt8183.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/power/mt8183.c b/power/mt8183.c index f62ddafb51..d083edc958 100644 --- a/power/mt8183.c +++ b/power/mt8183.c @@ -30,29 +30,29 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Input state flags */ -#define IN_PGOOD_PMIC POWER_SIGNAL_MASK(PMIC_PWR_GOOD) -#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3_L) +#define IN_PGOOD_PMIC POWER_SIGNAL_MASK(PMIC_PWR_GOOD) +#define IN_SUSPEND_ASSERTED POWER_SIGNAL_MASK(AP_IN_S3_L) /* Rails required for S3 and S0 */ -#define IN_PGOOD_S0 (IN_PGOOD_PMIC) -#define IN_PGOOD_S3 (IN_PGOOD_PMIC) +#define IN_PGOOD_S0 (IN_PGOOD_PMIC) +#define IN_PGOOD_S3 (IN_PGOOD_PMIC) /* All inputs in the right state for S0 */ -#define IN_ALL_S0 (IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED) +#define IN_ALL_S0 (IN_PGOOD_S0 & ~IN_SUSPEND_ASSERTED) /* Long power key press to force shutdown in S0. go/crosdebug */ #ifdef VARIANT_KUKUI_JACUZZI -#define FORCED_SHUTDOWN_DELAY (8 * SECOND) +#define FORCED_SHUTDOWN_DELAY (8 * SECOND) #else -#define FORCED_SHUTDOWN_DELAY (10 * SECOND) +#define FORCED_SHUTDOWN_DELAY (10 * SECOND) #endif /* Long power key press to boot from S5/G3 state. */ #ifndef POWERBTN_BOOT_DELAY -#define POWERBTN_BOOT_DELAY (1 * SECOND) +#define POWERBTN_BOOT_DELAY (1 * SECOND) #endif #define CHARGER_INITIALIZED_DELAY_MS 100 @@ -96,12 +96,10 @@ static const struct power_seq_op s5s3_power_seq[] = { }; /* The power sequence for POWER_S3S0 */ -static const struct power_seq_op s3s0_power_seq[] = { -}; +static const struct power_seq_op s3s0_power_seq[] = {}; /* The power sequence for POWER_S0S3 */ -static const struct power_seq_op s0s3_power_seq[] = { -}; +static const struct power_seq_op s0s3_power_seq[] = {}; /* The power sequence for POWER_S3S5 */ static const struct power_seq_op s3s5_power_seq[] = { @@ -261,8 +259,7 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops, int i; for (i = 0; i < op_count; i++) { - gpio_set_level(power_seq_ops[i].signal, - power_seq_ops[i].level); + gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level); if (!power_seq_ops[i].delay) continue; msleep(power_seq_ops[i].delay); @@ -351,8 +348,7 @@ enum power_state power_handle_state(enum power_state state) break; case POWER_S0: - if (!power_has_signals(IN_PGOOD_S0) || - forcing_shutdown || + if (!power_has_signals(IN_PGOOD_S0) || forcing_shutdown || power_get_signals() & IN_SUSPEND_ASSERTED) return POWER_S0S3; @@ -525,7 +521,7 @@ enum power_state power_handle_state(enum power_state state) if (power_button_is_pressed()) { forcing_shutdown = 1; hook_call_deferred(&chipset_force_shutdown_button_data, - -1); + -1); } return POWER_S3; @@ -564,7 +560,7 @@ enum power_state power_handle_state(enum power_state state) gpio_set_level(GPIO_PMIC_FORCE_RESET_ODL, 0); msleep(5); hook_call_deferred(&release_pmic_force_reset_data, - PMIC_FORCE_RESET_TIME); + PMIC_FORCE_RESET_TIME); return POWER_S5G3; } @@ -581,16 +577,15 @@ enum power_state power_handle_state(enum power_state state) } #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__override void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { CPRINTS("Warning: Detected sleep hang! Waking host up!"); host_set_single_event(EC_HOST_EVENT_HANG_DETECT); } -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { CPRINTS("Handle sleep: %d", state); @@ -611,7 +606,6 @@ __override void power_chipset_handle_host_sleep_event( sleep_set_notify(SLEEP_NOTIFY_RESUME); task_wake(TASK_ID_CHIPSET); sleep_complete_resume(ctx); - } } #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */ -- cgit v1.2.1 From 60d7e609afc8d89bf1e6d07fe6eb78dde41f64f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:35 -0600 Subject: zephyr/include/emul/emul_bmi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia15b31d327a19132e4c91762a561d1804631ad67 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730719 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_bmi.h | 52 ++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/zephyr/include/emul/emul_bmi.h b/zephyr/include/emul/emul_bmi.h index b04278bd5e..ad9cbb770d 100644 --- a/zephyr/include/emul/emul_bmi.h +++ b/zephyr/include/emul/emul_bmi.h @@ -60,49 +60,49 @@ enum bmi_emul_axis { }; /** BMI emulator models */ -#define BMI_EMUL_160 1 -#define BMI_EMUL_260 2 +#define BMI_EMUL_160 1 +#define BMI_EMUL_260 2 /** Last register supported by emulator */ -#define BMI_EMUL_MAX_REG 0x80 +#define BMI_EMUL_MAX_REG 0x80 /** Maximum number of registers that can be backed in NVM */ -#define BMI_EMUL_MAX_NVM_REGS 10 +#define BMI_EMUL_MAX_NVM_REGS 10 /** Headers used in FIFO frames */ -#define BMI_EMUL_FIFO_HEAD_SKIP 0x40 -#define BMI_EMUL_FIFO_HEAD_TIME 0x44 -#define BMI_EMUL_FIFO_HEAD_CONFIG 0x48 -#define BMI_EMUL_FIFO_HEAD_EMPTY 0x80 -#define BMI_EMUL_FIFO_HEAD_DATA 0x80 -#define BMI_EMUL_FIFO_HEAD_DATA_MAG BIT(4) -#define BMI_EMUL_FIFO_HEAD_DATA_GYR BIT(3) -#define BMI_EMUL_FIFO_HEAD_DATA_ACC BIT(2) -#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK 0x03 +#define BMI_EMUL_FIFO_HEAD_SKIP 0x40 +#define BMI_EMUL_FIFO_HEAD_TIME 0x44 +#define BMI_EMUL_FIFO_HEAD_CONFIG 0x48 +#define BMI_EMUL_FIFO_HEAD_EMPTY 0x80 +#define BMI_EMUL_FIFO_HEAD_DATA 0x80 +#define BMI_EMUL_FIFO_HEAD_DATA_MAG BIT(4) +#define BMI_EMUL_FIFO_HEAD_DATA_GYR BIT(3) +#define BMI_EMUL_FIFO_HEAD_DATA_ACC BIT(2) +#define BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK 0x03 /** * Acceleration 1g in internal emulator units. It is helpful for using * functions @ref bmi_emul_set_value @ref bmi_emul_get_value * @ref bmi_emul_set_off and @ref bmi_emul_get_off */ -#define BMI_EMUL_1G BIT(14) +#define BMI_EMUL_1G BIT(14) /** * Gyroscope 125°/s in internal emulator units. It is helpful for using * functions @ref bmi_emul_set_value @ref bmi_emul_get_value * @ref bmi_emul_set_off and @ref bmi_emul_get_off */ -#define BMI_EMUL_125_DEG_S BIT(15) +#define BMI_EMUL_125_DEG_S BIT(15) /** Type of frames that can be added to the emulator frames list */ -#define BMI_EMUL_FRAME_CONFIG BIT(0) -#define BMI_EMUL_FRAME_ACC BIT(1) -#define BMI_EMUL_FRAME_MAG BIT(2) -#define BMI_EMUL_FRAME_GYR BIT(3) +#define BMI_EMUL_FRAME_CONFIG BIT(0) +#define BMI_EMUL_FRAME_ACC BIT(1) +#define BMI_EMUL_FRAME_MAG BIT(2) +#define BMI_EMUL_FRAME_GYR BIT(3) /** * Code returned by model specific handle_read and handle_write functions, when * RO register is accessed on write or WO register is accessed on read */ -#define BMI_EMUL_ACCESS_E 1 +#define BMI_EMUL_ACCESS_E 1 /** Structure used to describe single FIFO frame */ struct bmi_emul_frame { @@ -400,9 +400,8 @@ uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header); * * @return FIFO data byte */ -uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte, - bool tag_time, bool header, int acc_shift, - int gyr_shift); +uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte, bool tag_time, + bool header, int acc_shift, int gyr_shift); /** * @brief Saves current internal state of sensors to emulator's registers. @@ -419,10 +418,9 @@ uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte, * @param gyr_off_en Indicate if gyroscope offset should be included to * sensor data value */ -void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift, - int gyr_shift, int acc_reg, int gyr_reg, - int sensortime_reg, bool acc_off_en, - bool gyr_off_en); +void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift, int gyr_shift, + int acc_reg, int gyr_reg, int sensortime_reg, + bool acc_off_en, bool gyr_off_en); /** * @} -- cgit v1.2.1 From 8a59fce97bb56320c38e1fd40bba560081cb3b35 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:12 -0600 Subject: chip/stm32/gpio-stm32g4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ae9232ba3af1343a66cba2b37852f383fb79be0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729505 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-stm32g4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/stm32/gpio-stm32g4.c b/chip/stm32/gpio-stm32g4.c index e77adc0ba6..ce4baf4313 100644 --- a/chip/stm32/gpio-stm32g4.c +++ b/chip/stm32/gpio-stm32g4.c @@ -17,12 +17,12 @@ int gpio_required_clocks(void) { const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" +#define GPIO(name, pin, flags) pin +#define GPIO_INT(name, pin, flags, signal) pin +#define ALTERNATE(pinmask, function, module, flagz) pinmask +#define PIN(port, index) | STM32_RCC_AHB2ENR_GPIO_PORT##port +#define PIN_MASK(port, mask) PIN(port, 0) +#include "gpio.wrap" ); /* -- cgit v1.2.1 From eb73bb073f90c960f128403a9eae5370069f0f02 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:16 -0600 Subject: common/version.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5fb90ad360b1d25142f2f94502590e92b4faf2df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729811 Reviewed-by: Jeremy Bettis --- common/version.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common/version.c b/common/version.c index 3978e796b5..781840d55e 100644 --- a/common/version.c +++ b/common/version.c @@ -17,8 +17,7 @@ BUILD_ASSERT(CONFIG_ROLLBACK_VERSION >= 0); BUILD_ASSERT(CONFIG_ROLLBACK_VERSION <= INT32_MAX); -const struct image_data __keep current_image_data - FIXED_SECTION("ver") = { +const struct image_data __keep current_image_data FIXED_SECTION("ver") = { .cookie1 = CROS_EC_IMAGE_DATA_COOKIE1, .version = CROS_EC_VERSION32, #ifndef TEST_BUILD @@ -69,7 +68,6 @@ static int get_num_commits(const struct image_data *data) } return (i == sizeof(data->version) ? 0 : ret); - } /* LCOV_EXCL_STOP */ -- cgit v1.2.1 From bcb440621a7072d0c2aa27c9ef5481fa62054251 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:35 -0600 Subject: test/usb_sm_checks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3a4beb0524361e3bbf7147bc32a2d1d5d3fcf271 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730569 Reviewed-by: Jeremy Bettis --- test/usb_sm_checks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/usb_sm_checks.c b/test/usb_sm_checks.c index 49b2dbae28..d9b62148d5 100644 --- a/test/usb_sm_checks.c +++ b/test/usb_sm_checks.c @@ -39,7 +39,7 @@ const struct test_sm_data test_pe_sm_data[] = {}; const int test_pe_sm_data_size; #endif -test_static int test_no_parent_cycles(const struct test_sm_data * const sm_data) +test_static int test_no_parent_cycles(const struct test_sm_data *const sm_data) { int i; -- cgit v1.2.1 From e629ddc5e66cbfd96aeda8eb7688659662a8bea6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:20 -0600 Subject: include/onewire.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7285c484a2106f26efddba1590f2865751e3f30a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730372 Reviewed-by: Jeremy Bettis --- include/onewire.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/onewire.h b/include/onewire.h index 58899360a4..67537b167b 100644 --- a/include/onewire.h +++ b/include/onewire.h @@ -40,4 +40,4 @@ int onewire_read(void); */ void onewire_write(int data); -#endif /* __CROS_EC_ONEWIRE_H */ +#endif /* __CROS_EC_ONEWIRE_H */ -- cgit v1.2.1 From 7708df38ede19dfc21c1c835b9ed8f0f20bfca94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:42 -0600 Subject: common/audio_codec_wov.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7521ea7204881b625eb759cf06d7f0b9b14f1fd2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729587 Reviewed-by: Jeremy Bettis --- common/audio_codec_wov.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/common/audio_codec_wov.c b/common/audio_codec_wov.c index f84e45f342..fc45d5682c 100644 --- a/common/audio_codec_wov.c +++ b/common/audio_codec_wov.c @@ -13,7 +13,7 @@ #include "task.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) /* * To shorten the variable names, or the following code is likely to greater @@ -99,7 +99,7 @@ static enum ec_status wov_set_lang_shm(struct host_cmd_handler_args *args) { const struct ec_param_ec_codec_wov *p = args->params; const struct ec_param_ec_codec_wov_set_lang_shm *pp = - &p->set_lang_shm_param; + &p->set_lang_shm_param; if (pp->total_len > LANG_BUF_LEN) return EC_RES_INVALID_PARAM; @@ -135,11 +135,11 @@ static enum ec_status wov_set_lang(struct host_cmd_handler_args *args) return EC_RES_BUSY; if (!pp->offset) - memset((uint8_t *)audio_codec_wov_lang_buf_addr, - 0, LANG_BUF_LEN); + memset((uint8_t *)audio_codec_wov_lang_buf_addr, 0, + LANG_BUF_LEN); - memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset, - pp->buf, pp->len); + memcpy((uint8_t *)audio_codec_wov_lang_buf_addr + pp->offset, pp->buf, + pp->len); if (pp->offset + pp->len == pp->total_len) { if (check_lang_buf((uint8_t *)audio_codec_wov_lang_buf_addr, @@ -176,7 +176,7 @@ static enum ec_status wov_enable(struct host_cmd_handler_args *args) if (!speech_lib_loaded) { if (!GoogleHotwordDspInit( - (void *)audio_codec_wov_lang_buf_addr)) + (void *)audio_codec_wov_lang_buf_addr)) return EC_RES_ERROR; speech_lib_loaded = 1; } else { @@ -359,7 +359,6 @@ void audio_codec_wov_task(void *arg) continue; } - /* Clear the buffer if full. */ if (is_buf_full()) { audio_buf_wp = audio_buf_rp; @@ -415,7 +414,7 @@ void audio_codec_wov_task(void *arg) * case, sample is S16_LE. Thus, n / 2. */ if (!hotword_detected && - GoogleHotwordDspProcess(p, n / 2, &r)) { + GoogleHotwordDspProcess(p, n / 2, &r)) { CPRINTS("hotword detected"); mutex_lock(&lock); -- cgit v1.2.1 From 8646a313001065ba630752ee5207f270bc9faae4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:17 -0600 Subject: chip/it83xx/intc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6107ebe18c117bfeebb491908b65e4842cea6bab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729201 Reviewed-by: Jeremy Bettis --- chip/it83xx/intc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h index 50d31999f9..843f64e2cb 100644 --- a/chip/it83xx/intc.h +++ b/chip/it83xx/intc.h @@ -15,7 +15,7 @@ static inline void data_serialization_barrier(void) { if (IS_ENABLED(CHIP_CORE_NDS32)) - asm volatile ("dsb"); + asm volatile("dsb"); } int intc_get_ec_int(void); -- cgit v1.2.1 From 341ea5cbde577273d44c14b40f5719bd013267d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:33 -0600 Subject: board/plankton/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7f4454c1214717008b23f5e6086f95daa7ad3649 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728835 Reviewed-by: Jeremy Bettis --- board/plankton/usb_pd_pdo.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/plankton/usb_pd_pdo.c b/board/plankton/usb_pd_pdo.c index f51a40abdc..67fe6b65b2 100644 --- a/board/plankton/usb_pd_pdo.c +++ b/board/plankton/usb_pd_pdo.c @@ -7,28 +7,28 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DATA_SWAP | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP) /* Source PDOs */ const uint32_t pd_src_pdo[] = { - PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), - PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), - PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS), }; /* Fake PDOs : we just want our pre-defined voltages */ const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), - PDO_FIXED(12000, 500, PDO_FIXED_FLAGS), - PDO_FIXED(20000, 500, PDO_FIXED_FLAGS), + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_FIXED(12000, 500, PDO_FIXED_FLAGS), + PDO_FIXED(20000, 500, PDO_FIXED_FLAGS), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); static const int pd_src_pdo_cnts[] = { - [SRC_CAP_5V] = 1, - [SRC_CAP_12V] = 2, - [SRC_CAP_20V] = 3, + [SRC_CAP_5V] = 1, + [SRC_CAP_12V] = 2, + [SRC_CAP_20V] = 3, }; static int pd_src_pdo_idx; -- cgit v1.2.1 From c1b1de57218ea4c9e828cd6eac560f931fe1fe43 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:24 -0600 Subject: include/driver/ln9310.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f4d3b951e5b7cf16a05674db72ceca9ad2af010 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730275 Reviewed-by: Jeremy Bettis --- include/driver/ln9310.h | 356 ++++++++++++++++++++++++------------------------ 1 file changed, 178 insertions(+), 178 deletions(-) diff --git a/include/driver/ln9310.h b/include/driver/ln9310.h index a5d3cf8922..6e79f20e05 100644 --- a/include/driver/ln9310.h +++ b/include/driver/ln9310.h @@ -12,192 +12,192 @@ #include "gpio_signal.h" /* I2C address */ -#define LN9310_I2C_ADDR_0_FLAGS 0x72 -#define LN9310_I2C_ADDR_1_FLAGS 0x73 -#define LN9310_I2C_ADDR_2_FLAGS 0x53 -#define LN9310_I2C_ADDR_3_FLAGS 0x54 +#define LN9310_I2C_ADDR_0_FLAGS 0x72 +#define LN9310_I2C_ADDR_1_FLAGS 0x73 +#define LN9310_I2C_ADDR_2_FLAGS 0x53 +#define LN9310_I2C_ADDR_3_FLAGS 0x54 /* Registers */ -#define LN9310_REG_CHIP_ID 0x00 -#define LN9310_CHIP_ID 0x44 -#define LN9310_REG_INT1 0x01 -#define LN9310_REG_INT1_MSK 0x02 -#define LN9310_INT1_TIMER BIT(0) -#define LN9310_INT1_INFET BIT(1) -#define LN9310_INT1_TEMP BIT(2) -#define LN9310_INT1_REV_CURR BIT(3) -#define LN9310_INT1_MODE BIT(4) -#define LN9310_INT1_ALARM BIT(5) -#define LN9310_INT1_OK BIT(6) -#define LN9310_INT1_FAULT BIT(7) - -#define LN9310_REG_SYSGPIO_MSK 0x03 - -#define LN9310_REG_SYS_STS 0x04 -#define LN9310_SYS_STANDBY BIT(0) -#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) -#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) -#define LN9310_SYS_BYPASS_ACTIVE BIT(3) -#define LN9310_SYS_INFET_OK BIT(4) -#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) -#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) - -#define LN9310_REG_SAFETY_STS 0x05 -#define LN9310_REG_FAULT1_STS 0x06 -#define LN9310_REG_FAULT2_STS 0x07 - -#define LN9310_REG_PWR_CTRL 0x1d -#define LN9310_PWR_OP_MODE0 BIT(0) -#define LN9310_PWR_OP_MODE1 BIT(1) -#define LN9310_PWR_INFET_EN BIT(2) -#define LN9310_PWR_INFET_AUTO_MODE BIT(3) -#define LN9310_PWR_REVERSE_MODE BIT(4) -#define LN9310_PWR_VIN_OV_IGNORE BIT(5) -#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) -#define LN9310_PWR_FORCE_INSNS_EN BIT(7) -#define LN9310_PWR_OP_MODE_MASK 0x03 -#define LN9310_PWR_OP_MODE_DISABLED 0x00 -#define LN9310_PWR_OP_MODE_BYPASS 0x01 -#define LN9310_PWR_OP_MODE_SWITCH21 0x02 -#define LN9310_PWR_OP_MODE_SWITCH31 0x03 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 -#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 -#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 -#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 - -#define LN9310_REG_SYS_CTRL 0x1e - -#define LN9310_REG_STARTUP_CTRL 0x1f -#define LN9310_STARTUP_STANDBY_EN BIT(0) -#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) - -#define LN9310_REG_IIN_CTRL 0x20 -#define LN9310_REG_VIN_CTRL 0x21 - -#define LN9310_REG_TRACK_CTRL 0x22 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 -#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 - -#define LN9310_REG_OCP_CTRL 0x23 - -#define LN9310_REG_TIMER_CTRL 0x24 -#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) -#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 -#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 - -#define LN9310_REG_RECOVERY_CTRL 0x25 - -#define LN9310_REG_LB_CTRL 0x26 -#define LN9310_LB_MIN_FREQ_EN BIT(2) -#define LN9310_LB_DELTA_MASK 0x38 -#define LN9310_LB_DELTA_2S 0x20 -#define LN9310_LB_DELTA_3S 0x20 - -#define LN9310_REG_SC_OUT_OV_CTRL 0x29 -#define LN9310_REG_STS_CTRL 0x2d - -#define LN9310_REG_MODE_CHANGE_CFG 0x2e -#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) -#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) -#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) -#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) -#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) -#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) -#define LN9310_MODE_FORCE_MODE_CFG BIT(7) -#define LN9310_MODE_TM_TRACK_MASK 0x60 -#define LN9310_MODE_TM_TRACK_BYPASS 0x00 -#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 -#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 -#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 -#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 -#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 -#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 -#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ -#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ - -#define LN9310_REG_SPARE_0 0x2A -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 -#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 -#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 - -#define LN9310_REG_SC_DITHER_CTRL 0x2f - -#define LN9310_REG_LION_CTRL 0x30 -#define LN9310_LION_CTRL_MASK 0xFF -#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA -#define LN9310_LION_CTRL_UNLOCK 0x5B +#define LN9310_REG_CHIP_ID 0x00 +#define LN9310_CHIP_ID 0x44 +#define LN9310_REG_INT1 0x01 +#define LN9310_REG_INT1_MSK 0x02 +#define LN9310_INT1_TIMER BIT(0) +#define LN9310_INT1_INFET BIT(1) +#define LN9310_INT1_TEMP BIT(2) +#define LN9310_INT1_REV_CURR BIT(3) +#define LN9310_INT1_MODE BIT(4) +#define LN9310_INT1_ALARM BIT(5) +#define LN9310_INT1_OK BIT(6) +#define LN9310_INT1_FAULT BIT(7) + +#define LN9310_REG_SYSGPIO_MSK 0x03 + +#define LN9310_REG_SYS_STS 0x04 +#define LN9310_SYS_STANDBY BIT(0) +#define LN9310_SYS_SWITCHING21_ACTIVE BIT(1) +#define LN9310_SYS_SWITCHING31_ACTIVE BIT(2) +#define LN9310_SYS_BYPASS_ACTIVE BIT(3) +#define LN9310_SYS_INFET_OK BIT(4) +#define LN9310_SYS_SC_OUT_SWITCH_OK BIT(5) +#define LN9310_SYS_INFET_OUT_SWITCH_OK BIT(6) + +#define LN9310_REG_SAFETY_STS 0x05 +#define LN9310_REG_FAULT1_STS 0x06 +#define LN9310_REG_FAULT2_STS 0x07 + +#define LN9310_REG_PWR_CTRL 0x1d +#define LN9310_PWR_OP_MODE0 BIT(0) +#define LN9310_PWR_OP_MODE1 BIT(1) +#define LN9310_PWR_INFET_EN BIT(2) +#define LN9310_PWR_INFET_AUTO_MODE BIT(3) +#define LN9310_PWR_REVERSE_MODE BIT(4) +#define LN9310_PWR_VIN_OV_IGNORE BIT(5) +#define LN9310_PWR_OP_MANUAL_UPDATE BIT(6) +#define LN9310_PWR_FORCE_INSNS_EN BIT(7) +#define LN9310_PWR_OP_MODE_MASK 0x03 +#define LN9310_PWR_OP_MODE_DISABLED 0x00 +#define LN9310_PWR_OP_MODE_BYPASS 0x01 +#define LN9310_PWR_OP_MODE_SWITCH21 0x02 +#define LN9310_PWR_OP_MODE_SWITCH31 0x03 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK 0x40 +#define LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF 0x00 +#define LN9310_PWR_INFET_AUTO_MODE_MASK 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_ON 0x08 +#define LN9310_PWR_INFET_AUTO_MODE_OFF 0x00 + +#define LN9310_REG_SYS_CTRL 0x1e + +#define LN9310_REG_STARTUP_CTRL 0x1f +#define LN9310_STARTUP_STANDBY_EN BIT(0) +#define LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR BIT(3) + +#define LN9310_REG_IIN_CTRL 0x20 +#define LN9310_REG_VIN_CTRL 0x21 + +#define LN9310_REG_TRACK_CTRL 0x22 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN BIT(7) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG2 BIT(6) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG1 BIT(5) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG0 BIT(4) +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON 0x80 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF 0x00 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK 0x70 +#define LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V 0x10 + +#define LN9310_REG_OCP_CTRL 0x23 + +#define LN9310_REG_TIMER_CTRL 0x24 +#define LN9310_TIMER_OP_SELF_SYNC_EN BIT(3) +#define LN9310_TIMER_OP_SELF_SYNC_EN_MASK 0x08 +#define LN9310_TIMER_OP_SELF_SYNC_EN_ON 0x08 + +#define LN9310_REG_RECOVERY_CTRL 0x25 + +#define LN9310_REG_LB_CTRL 0x26 +#define LN9310_LB_MIN_FREQ_EN BIT(2) +#define LN9310_LB_DELTA_MASK 0x38 +#define LN9310_LB_DELTA_2S 0x20 +#define LN9310_LB_DELTA_3S 0x20 + +#define LN9310_REG_SC_OUT_OV_CTRL 0x29 +#define LN9310_REG_STS_CTRL 0x2d + +#define LN9310_REG_MODE_CHANGE_CFG 0x2e +#define LN9310_MODE_TM_VIN_OV_CFG0 BIT(0) +#define LN9310_MODE_TM_VIN_OV_CFG1 BIT(1) +#define LN9310_MODE_TM_VIN_OV_CFG2 BIT(2) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG0 BIT(3) +#define LN9310_MODE_TM_SC_OUT_PRECHG_CFG1 BIT(4) +#define LN9310_MODE_TM_TRACK_CFG0 BIT(5) +#define LN9310_MODE_TM_TRACK_CFG1 BIT(6) +#define LN9310_MODE_FORCE_MODE_CFG BIT(7) +#define LN9310_MODE_TM_TRACK_MASK 0x60 +#define LN9310_MODE_TM_TRACK_BYPASS 0x00 +#define LN9310_MODE_TM_TRACK_SWITCH21 0x20 +#define LN9310_MODE_TM_TRACK_SWITCH31 0x60 +#define LN9310_MODE_TM_SC_OUT_PRECHG_MASK 0x18 +#define LN9310_MODE_TM_SC_OUT_PRECHG_BYPASS 0x0 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH21 0x08 +#define LN9310_MODE_TM_SC_OUT_PRECHG_SWITCH31 0x18 +#define LN9310_MODE_TM_VIN_OV_CFG_MASK 0x07 +#define LN9310_MODE_TM_VIN_OV_CFG_2S 0x0 /* 14V */ +#define LN9310_MODE_TM_VIN_OV_CFG_3S 0x2 /* 20V */ + +#define LN9310_REG_SPARE_0 0x2A +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_MASK 0x40 +#define LN9310_SPARE_0_SW4_BEFORE_BSTH_BSTL_EN_CFG_ON 0x40 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK 0x10 +#define LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON 0x10 + +#define LN9310_REG_SC_DITHER_CTRL 0x2f + +#define LN9310_REG_LION_CTRL 0x30 +#define LN9310_LION_CTRL_MASK 0xFF +#define LN9310_LION_CTRL_UNLOCK_AND_EN_TM 0xAA +#define LN9310_LION_CTRL_UNLOCK 0x5B /* * value changed to 0x22 to distinguish from reset value of 0x00 * 0x22 and 0x00 are functionally equivalent within LN9310 */ -#define LN9310_LION_CTRL_LOCK 0x22 - -#define LN9310_REG_CFG_0 0x3C -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 -#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 - -#define LN9310_REG_CFG_4 0x40 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 -#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 -#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 -#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 - -#define LN9310_REG_CFG_5 0x41 -#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 -#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 -#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 - -#define LN9310_REG_TEST_MODE_CTRL 0x46 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 -#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 - -#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 -#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 - -#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 -#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 - -#define LN9310_REG_SWAP_CTRL_0 0x58 -#define LN9310_REG_SWAP_CTRL_1 0x59 -#define LN9310_REG_SWAP_CTRL_2 0x5A -#define LN9310_REG_SWAP_CTRL_3 0x5B - -#define LN9310_REG_BC_STS_B 0x51 -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) -#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 - -#define LN9310_REG_BC_STS_C 0x52 -#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 -#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 +#define LN9310_LION_CTRL_LOCK 0x22 + +#define LN9310_REG_CFG_0 0x3C +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK 0x20 +#define LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON 0x20 + +#define LN9310_REG_CFG_4 0x40 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG BIT(2) +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK BIT(3) +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_MASK 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_MASK 0x08 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_MASK 0xC0 +#define LN9310_CFG_4_SC_OUT_PRECHARGE_EN_TIME_CFG_ON 0x04 +#define LN9310_CFG_4_SW1_VGS_SHORT_EN_MSK_OFF 0x00 +#define LN9310_CFG_4_BSTH_BSTL_HIGH_ROUT_CFG_LOWEST 0x00 + +#define LN9310_REG_CFG_5 0x41 +#define LN9310_CFG_5_INGATE_PD_EN_MASK 0xC0 +#define LN9310_CFG_5_INGATE_PD_EN_OFF 0x00 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK 0x30 +#define LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST 0x00 + +#define LN9310_REG_TEST_MODE_CTRL 0x46 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON 0x40 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF 0x00 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON 0x20 +#define LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF 0x00 + +#define LN9310_REG_FORCE_SC21_CTRL_1 0x49 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK 0xFF +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON 0x59 +#define LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF 0x40 + +#define LN9310_REG_FORCE_SC21_CTRL_2 0x4A +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON 0x80 +#define LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF 0x00 + +#define LN9310_REG_SWAP_CTRL_0 0x58 +#define LN9310_REG_SWAP_CTRL_1 0x59 +#define LN9310_REG_SWAP_CTRL_2 0x5A +#define LN9310_REG_SWAP_CTRL_3 0x5B + +#define LN9310_REG_BC_STS_B 0x51 +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK BIT(5) +#define LN9310_BC_STS_B_INFET_OUT_SWITCH_OK_MASK 0x20 + +#define LN9310_REG_BC_STS_C 0x52 +#define LN9310_BC_STS_C_CHIP_REV_MASK 0xF0 +#define LN9310_BC_STS_C_CHIP_REV_FIXED 0x40 /* LN9310 Timing definition */ -#define LN9310_CDC_DELAY 120 /* 120us */ -#define LN9310_CFLY_PRECHARGE_DELAY (12*MSEC) -#define LN9310_CFLY_PRECHARGE_TIMEOUT (100*MSEC) +#define LN9310_CDC_DELAY 120 /* 120us */ +#define LN9310_CFLY_PRECHARGE_DELAY (12 * MSEC) +#define LN9310_CFLY_PRECHARGE_TIMEOUT (100 * MSEC) /* LN9310 Driver Configuration */ #define LN9310_INIT_RETRY_COUNT 3 -- cgit v1.2.1 From 6c8da81e17c5020501ea190dd827e8872d80f195 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:31 -0600 Subject: common/ec_ec_comm_server.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20a77934d4011279d507afe1f7591a9edab2d8e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729606 Reviewed-by: Jeremy Bettis --- common/ec_ec_comm_server.c | 68 +++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 37 deletions(-) diff --git a/common/ec_ec_comm_server.c b/common/ec_ec_comm_server.c index 23b5fee139..3a2a884317 100644 --- a/common/ec_ec_comm_server.c +++ b/common/ec_ec_comm_server.c @@ -21,8 +21,8 @@ #include "task.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Print extra debugging information */ #undef EXTRA_DEBUG @@ -37,11 +37,10 @@ static int charging_allowed; #define LARGEST_PARAMS_SIZE 8 BUILD_ASSERT(LARGEST_PARAMS_SIZE >= - sizeof(struct ec_params_battery_static_info)); + sizeof(struct ec_params_battery_static_info)); BUILD_ASSERT(LARGEST_PARAMS_SIZE >= - sizeof(struct ec_params_battery_dynamic_info)); -BUILD_ASSERT(LARGEST_PARAMS_SIZE >= - sizeof(struct ec_params_charger_control)); + sizeof(struct ec_params_battery_dynamic_info)); +BUILD_ASSERT(LARGEST_PARAMS_SIZE >= sizeof(struct ec_params_charger_control)); #define COMMAND_BUFFER_PARAMS_SIZE (LARGEST_PARAMS_SIZE + 1) @@ -51,7 +50,6 @@ BUILD_ASSERT(LARGEST_PARAMS_SIZE >= */ #define COMMAND_TIMEOUT_US (5 * MSEC) - void ec_ec_comm_server_written(struct consumer const *consumer, size_t count) { task_wake(TASK_ID_ECCOMM); @@ -67,7 +65,7 @@ static void discard_queue(void) { do { queue_advance_head(&ec_ec_comm_server_input, - queue_count(&ec_ec_comm_server_input)); + queue_count(&ec_ec_comm_server_input)); usleep(1 * MSEC); } while (queue_count(&ec_ec_comm_server_input) > 0); } @@ -78,19 +76,17 @@ static void write_response(uint16_t res, int seq, const void *data, int len) struct ec_host_response4 header; uint8_t crc; - header.fields0 = - 4 | /* version */ - EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */ - (seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */ + header.fields0 = 4 | /* version */ + EC_PACKET4_0_IS_RESPONSE_MASK | /* is_response */ + (seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */ /* Set data_crc_present if there is data */ header.fields1 = (len > 0) ? EC_PACKET4_1_DATA_CRC_PRESENT_MASK : 0; header.result = res; header.data_len = len; header.reserved = 0; - header.header_crc = - cros_crc8((uint8_t *)&header, sizeof(header)-1); - QUEUE_ADD_UNITS(&ec_ec_comm_server_output, - (uint8_t *)&header, sizeof(header)); + header.header_crc = cros_crc8((uint8_t *)&header, sizeof(header) - 1); + QUEUE_ADD_UNITS(&ec_ec_comm_server_output, (uint8_t *)&header, + sizeof(header)); if (len > 0) { QUEUE_ADD_UNITS(&ec_ec_comm_server_output, data, len); @@ -123,9 +119,8 @@ static int read_data(void *buffer, size_t len, uint32_t start) return EC_SUCCESS; } -static void handle_cmd_reboot_ec( - const struct ec_params_reboot_ec *params, - int data_len, int seq) +static void handle_cmd_reboot_ec(const struct ec_params_reboot_ec *params, + int data_len, int seq) { int ret = EC_RES_SUCCESS; @@ -150,9 +145,9 @@ out: } #ifdef CONFIG_EC_EC_COMM_BATTERY -static void handle_cmd_charger_control( - const struct ec_params_charger_control *params, - int data_len, int seq) +static void +handle_cmd_charger_control(const struct ec_params_charger_control *params, + int data_len, int seq) { int ret = EC_RES_SUCCESS; int prev_charging_allowed = charging_allowed; @@ -169,7 +164,7 @@ static void handle_cmd_charger_control( charging_allowed = params->allow_charging; } else { if (-params->max_current > MAX_OTG_CURRENT_MA || - params->otg_voltage > MAX_OTG_VOLTAGE_MV) { + params->otg_voltage > MAX_OTG_VOLTAGE_MV) { ret = EC_RES_INVALID_PARAM; goto out; } @@ -233,8 +228,8 @@ void ec_ec_comm_server_task(void *u) #ifdef EXTRA_DEBUG CPRINTS("%s f0=%02x f1=%02x cmd=%02x, length=%d", __func__, - header.fields0, header.fields1, - header.command, header.data_len); + header.fields0, header.fields1, header.command, + header.data_len); #endif /* Ignore response (we wrote that ourselves) */ @@ -266,7 +261,7 @@ void ec_ec_comm_server_task(void *u) } seq = (header.fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >> - EC_PACKET4_0_SEQ_NUM_SHIFT; + EC_PACKET4_0_SEQ_NUM_SHIFT; cmdver = header.fields1 & EC_PACKET4_1_COMMAND_VERSION_MASK; @@ -277,7 +272,7 @@ void ec_ec_comm_server_task(void *u) } /* Check data CRC */ - if (hascrc && params[len-1] != cros_crc8(params, len-1)) { + if (hascrc && params[len - 1] != cros_crc8(params, len - 1)) { CPRINTS("%s data crc error", __func__); write_response(EC_RES_INVALID_CHECKSUM, seq, NULL, 0); goto discard; @@ -295,31 +290,30 @@ void ec_ec_comm_server_task(void *u) case EC_CMD_BATTERY_GET_STATIC: /* Note that we ignore the battery index parameter. */ write_response(EC_RES_SUCCESS, seq, - &battery_static[BATT_IDX_MAIN], - sizeof(battery_static[BATT_IDX_MAIN])); + &battery_static[BATT_IDX_MAIN], + sizeof(battery_static[BATT_IDX_MAIN])); break; case EC_CMD_BATTERY_GET_DYNAMIC: /* Note that we ignore the battery index parameter. */ write_response(EC_RES_SUCCESS, seq, - &battery_dynamic[BATT_IDX_MAIN], - sizeof(battery_dynamic[BATT_IDX_MAIN])); + &battery_dynamic[BATT_IDX_MAIN], + sizeof(battery_dynamic[BATT_IDX_MAIN])); break; case EC_CMD_CHARGER_CONTROL: handle_cmd_charger_control((void *)params, - header.data_len, seq); + header.data_len, seq); break; #endif case EC_CMD_REBOOT_EC: - handle_cmd_reboot_ec((void *)params, - header.data_len, seq); + handle_cmd_reboot_ec((void *)params, header.data_len, + seq); break; default: - write_response(EC_RES_INVALID_COMMAND, seq, - NULL, 0); + write_response(EC_RES_INVALID_COMMAND, seq, NULL, 0); } continue; -discard: + discard: /* * Some error occurred: discard all data in the queue. */ -- cgit v1.2.1 From 7d2fe4f315a8ed153486a16db87d12033f890a6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:42 -0600 Subject: board/volet/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I032fefa034313253ecc013bef112482b3dd1ed3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729063 Reviewed-by: Jeremy Bettis --- board/volet/sensors.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/board/volet/sensors.c b/board/volet/sensors.c index fb093729d3..06ea238618 100644 --- a/board/volet/sensors.c +++ b/board/volet/sensors.c @@ -24,7 +24,7 @@ #include "tablet_mode.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) /******************************************************************************/ /* Sensors */ static struct mutex g_lid_accel_mutex; @@ -39,23 +39,17 @@ static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t kx022_lid_accel = { .name = "Lid Accel", @@ -228,8 +222,7 @@ static void board_sensors_init(void) motion_sensor_count = 0; gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ - gpio_set_flags(GPIO_EC_IMU_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } } DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 66d4774b24220b6d947280f3dd0ebfd6f548d899 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:31 -0600 Subject: common/usbc/usb_tc_ctvpd_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea137774934fa5c97d394e9e3d1a92e14f87a893 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729795 Reviewed-by: Jeremy Bettis --- common/usbc/usb_tc_ctvpd_sm.c | 65 ++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/common/usbc/usb_tc_ctvpd_sm.c b/common/usbc/usb_tc_ctvpd_sm.c index 46550978ed..cfe5a22c3a 100644 --- a/common/usbc/usb_tc_ctvpd_sm.c +++ b/common/usbc/usb_tc_ctvpd_sm.c @@ -16,18 +16,18 @@ /* USB Type-C CTVPD module */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) #endif /* Type-C Layer Flags */ -#define TC_FLAGS_VCONN_ON BIT(0) +#define TC_FLAGS_VCONN_ON BIT(0) -#define SUPPORT_TIMER_RESET_INIT 0 -#define SUPPORT_TIMER_RESET_REQUEST 1 +#define SUPPORT_TIMER_RESET_INIT 0 +#define SUPPORT_TIMER_RESET_REQUEST 1 #define SUPPORT_TIMER_RESET_COMPLETE 2 /** @@ -105,9 +105,8 @@ enum usb_tc_state { /* Forward declare the full list of states. This is indexed by usb_tc_state */ static const struct usb_state tc_states[]; - /* List of human readable state names for console debugging */ -__maybe_unused const char * const tc_state_names[] = { +__maybe_unused const char *const tc_state_names[] = { #ifdef CONFIG_COMMON_RUNTIME [TC_DISABLED] = "Disabled", [TC_UNATTACHED_SNK] = "Unattached.SNK", @@ -257,9 +256,9 @@ test_mockable_static void print_current_state(const int port) int pd_is_connected(int port) { return (get_state_tc(port) == TC_ATTACHED_SNK) || - (get_state_tc(port) == TC_ATTACHED_SRC) || - (get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) || - (get_state_tc(port) == TC_CT_ATTACHED_VPD); + (get_state_tc(port) == TC_ATTACHED_SRC) || + (get_state_tc(port) == TC_CT_ATTACHED_UNSUPPORTED) || + (get_state_tc(port) == TC_CT_ATTACHED_VPD); } bool pd_is_disconnected(int port) @@ -398,7 +397,7 @@ static void tc_unattached_snk_run(const int port) * 2) VBUS is detected */ if (vpd_is_ct_vbus_present() && - tc[port].cc_state == PD_CC_DFP_ATTACHED) { + tc[port].cc_state == PD_CC_DFP_ATTACHED) { set_state_tc(port, TC_UNATTACHED_SRC); return; } @@ -436,11 +435,11 @@ static void tc_attach_wait_snk_run(const int port) if (tc[port].host_cc_state != host_new_cc_state) { tc[port].host_cc_state = host_new_cc_state; if (host_new_cc_state == PD_CC_DFP_ATTACHED) - tc[port].host_cc_debounce = get_time().val + - PD_T_CC_DEBOUNCE; + tc[port].host_cc_debounce = + get_time().val + PD_T_CC_DEBOUNCE; else - tc[port].host_cc_debounce = get_time().val + - PD_T_PD_DEBOUNCE; + tc[port].host_cc_debounce = + get_time().val + PD_T_PD_DEBOUNCE; return; } @@ -458,7 +457,7 @@ static void tc_attach_wait_snk_run(const int port) * CC2 pins is SNK.Open for at least tPDDebounce. */ if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED && - (vpd_is_vconn_present() || vpd_is_host_vbus_present())) + (vpd_is_vconn_present() || vpd_is_host_vbus_present())) set_state_tc(port, TC_ATTACHED_SNK); else if (tc[port].host_cc_state == PD_CC_NONE) set_state_tc(port, TC_UNATTACHED_SNK); @@ -551,7 +550,7 @@ static void tc_attached_snk_run(const int port) /* Check the Support Timer */ if (get_time().val > tc[port].support_timer && - !tc[port].billboard_presented) { + !tc[port].billboard_presented) { /* * Present USB Billboard Device Class interface * indicating that Charge-Through is not supported @@ -654,7 +653,7 @@ static void tc_unattached_src_run(const int port) * if Charge-Through VBUS is removed. */ if (!vpd_is_ct_vbus_present() || - get_time().val > tc[port].next_role_swap) { + get_time().val > tc[port].next_role_swap) { set_state_tc(port, TC_UNATTACHED_SNK); return; } @@ -719,7 +718,7 @@ static void tc_attach_wait_src_run(const int port) * state is on the Host-side port’s CC pin for at least tCCDebounce. */ if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED && - !vpd_is_host_vbus_present()) { + !vpd_is_host_vbus_present()) { set_state_tc(port, TC_TRY_SNK); return; } @@ -847,7 +846,7 @@ static void tc_try_snk_run(const int port) * for tTryCCDebounce. */ if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED && - (vpd_is_host_vbus_present() || vpd_is_vconn_present())) + (vpd_is_host_vbus_present() || vpd_is_vconn_present())) set_state_tc(port, TC_ATTACHED_SNK); else if (tc[port].host_cc_state == PD_CC_NONE) set_state_tc(port, TC_TRY_WAIT_SRC); @@ -887,7 +886,7 @@ static void tc_try_wait_src_run(const int port) if (tc[port].host_cc_state != host_new_cc_state) { tc[port].host_cc_state = host_new_cc_state; tc[port].host_cc_debounce = - get_time().val + PD_T_TRY_CC_DEBOUNCE; + get_time().val + PD_T_TRY_CC_DEBOUNCE; return; } @@ -899,7 +898,7 @@ static void tc_try_wait_src_run(const int port) * at least tTryCCDebounce. */ if (tc[port].host_cc_state == PD_CC_UFP_ATTACHED && - !vpd_is_host_vbus_present()) { + !vpd_is_host_vbus_present()) { set_state_tc(port, TC_ATTACHED_SRC); return; } @@ -988,7 +987,7 @@ static void tc_ct_try_snk_run(const int port) * Charge-Through port. */ if (tc[port].cc_state == PD_CC_DFP_ATTACHED && - vpd_is_ct_vbus_present()) { + vpd_is_ct_vbus_present()) { set_state_tc(port, TC_CT_ATTACHED_VPD); return; } @@ -1001,8 +1000,7 @@ static void tc_ct_try_snk_run(const int port) * for tDRPTryWait. */ if (tc[port].cc_state == PD_CC_NONE) { - set_state_tc(port, - TC_CT_ATTACHED_UNSUPPORTED); + set_state_tc(port, TC_CT_ATTACHED_UNSUPPORTED); return; } } @@ -1181,8 +1179,7 @@ static void tc_ct_unattached_unsupported_run(const int port) * on both the CC1 and CC2 pins. */ if (cc_is_at_least_one_rd(cc1, cc2) || cc_is_audio_acc(cc1, cc2)) { - set_state_tc(port, - TC_CT_ATTACH_WAIT_UNSUPPORTED); + set_state_tc(port, TC_CT_ATTACH_WAIT_UNSUPPORTED); return; } @@ -1343,7 +1340,7 @@ static void tc_ct_attached_vpd_entry(const int port) * pins is connected through the cable */ vpd_ct_get_cc(&cc1, &cc2); - tc[port].ct_cc = cc_is_rp(cc2) ? CT_CC2 : CT_CC1; + tc[port].ct_cc = cc_is_rp(cc2) ? CT_CC2 : CT_CC1; /* * 1. Remove or reduce any additional capacitance on the @@ -1468,10 +1465,8 @@ static void tc_ct_attach_wait_vpd_run(const int port) /* Debounce the cc state */ if (new_cc_state != tc[port].cc_state) { tc[port].cc_state = new_cc_state; - tc[port].cc_debounce = get_time().val + - PD_T_CC_DEBOUNCE; - tc[port].pd_debounce = get_time().val + - PD_T_PD_DEBOUNCE; + tc[port].cc_debounce = get_time().val + PD_T_CC_DEBOUNCE; + tc[port].pd_debounce = get_time().val + PD_T_PD_DEBOUNCE; return; } @@ -1482,7 +1477,7 @@ static void tc_ct_attach_wait_vpd_run(const int port) * port’s CC1 and CC2 pins are SNK.Open for at least * tPDDebounce. */ - if (tc[port].cc_state == PD_CC_NONE) { + if (tc[port].cc_state == PD_CC_NONE) { set_state_tc(port, TC_CT_UNATTACHED_VPD); return; } @@ -1496,8 +1491,8 @@ static void tc_ct_attach_wait_vpd_run(const int port) * least tCCDebounce and VBUS on the Charge-Through port is * detected. */ - if (tc[port].cc_state == PD_CC_DFP_ATTACHED && - vpd_is_ct_vbus_present()) { + if (tc[port].cc_state == PD_CC_DFP_ATTACHED && + vpd_is_ct_vbus_present()) { set_state_tc(port, TC_CT_ATTACHED_VPD); return; } -- cgit v1.2.1 From 16d48f1613795237c897bd19cb0ab72aef32af04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:37 -0600 Subject: chip/stm32/adc-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia48549fadef2322d67e75807985b0dc482795bb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729453 Reviewed-by: Jeremy Bettis --- chip/stm32/adc-stm32l.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/chip/stm32/adc-stm32l.c b/chip/stm32/adc-stm32l.c index c1f1cfae4a..6d8a70d90c 100644 --- a/chip/stm32/adc-stm32l.c +++ b/chip/stm32/adc-stm32l.c @@ -91,7 +91,7 @@ static void adc_init(void) if (!adc_powered()) /* Power on ADC module */ - STM32_ADC_CR2 |= BIT(0); /* ADON */ + STM32_ADC_CR2 |= BIT(0); /* ADON */ /* Set right alignment */ STM32_ADC_CR2 &= ~BIT(11); @@ -165,6 +165,7 @@ int adc_read_channel(enum adc_channel ch) adc_release(); mutex_unlock(&adc_lock); - return (value == ADC_READ_ERROR) ? ADC_READ_ERROR : - value * adc->factor_mul / adc->factor_div + adc->shift; + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; } -- cgit v1.2.1 From dd5756ab106505c73f99e50cdf333df2984a548e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:41 -0600 Subject: include/typec_control.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1398d1225ad44b06cf571c182e39e85b00851d39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730424 Reviewed-by: Jeremy Bettis --- include/typec_control.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/typec_control.h b/include/typec_control.h index b162467663..7705b75214 100644 --- a/include/typec_control.h +++ b/include/typec_control.h @@ -33,7 +33,7 @@ void typec_set_sbu(int port, bool enable); * @param rp Pull-up values to be aplied as a SRC to advertise current limits */ __override_proto void typec_set_source_current_limit(int port, - enum tcpc_rp_value rp); + enum tcpc_rp_value rp); /** * Turn on/off the VCONN FET -- cgit v1.2.1 From 0a70ab605603a5cf5b1990c814b9d5664e9b65f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:44 -0600 Subject: baseboard/asurada/board_id.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I57667c955ae24083fa7ff77a8fb9c284cbfee3a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727850 Reviewed-by: Jeremy Bettis --- baseboard/asurada/board_id.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/baseboard/asurada/board_id.c b/baseboard/asurada/board_id.c index 642785034c..ba83e4e272 100644 --- a/baseboard/asurada/board_id.c +++ b/baseboard/asurada/board_id.c @@ -34,21 +34,8 @@ * 14 | 47 | 680 | 3086.7 */ const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, + 136, 388, 584, 785, 993, 1220, 1432, 1650, + 1875, 2084, 2273, 2461, 2672, 2888, 3086, }; const int threshold_mv = 100; -- cgit v1.2.1 From f5974a4ee00511119ea97faab51bbf9f8e90b7ae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:24 -0600 Subject: builtin/stdnoreturn.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4fc89c0e89c67a5dfd49a218fa583ba10a16da3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729146 Reviewed-by: Jeremy Bettis --- builtin/stdnoreturn.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/builtin/stdnoreturn.h b/builtin/stdnoreturn.h index 659d3c540f..a6fb13d3f4 100644 --- a/builtin/stdnoreturn.h +++ b/builtin/stdnoreturn.h @@ -9,7 +9,8 @@ /* * Only defined for C: https://en.cppreference.com/w/c/language/_Noreturn * - * C++ uses [[noreturn]]: https://en.cppreference.com/w/cpp/language/attributes/noreturn + * C++ uses [[noreturn]]: + * https://en.cppreference.com/w/cpp/language/attributes/noreturn */ #ifndef __cplusplus #ifndef noreturn -- cgit v1.2.1 From 5c2bcc3d5acccfe41fab53986c4baecd7af36f1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:34 -0600 Subject: board/rainier/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaac1ac5e5b9a310a119cd09b65eeaffbf83cd712 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728852 Reviewed-by: Jeremy Bettis --- board/rainier/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/rainier/usb_pd_policy.c b/board/rainier/usb_pd_policy.c index 6de1dc9271..3c13d516ef 100644 --- a/board/rainier/usb_pd_policy.c +++ b/board/rainier/usb_pd_policy.c @@ -18,8 +18,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en; -- cgit v1.2.1 From f2081e76a154430bd48a489b6343c92fc83dff30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:24 -0600 Subject: driver/pmic_bd99992gw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I017e05fa3752ec0ad2cdb25e8423e788b706c36f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730022 Reviewed-by: Jeremy Bettis --- driver/pmic_bd99992gw.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h index e00ea1d252..205e15fa13 100644 --- a/driver/pmic_bd99992gw.h +++ b/driver/pmic_bd99992gw.h @@ -10,22 +10,22 @@ #include "temp_sensor/bd99992gw.h" -#define BD99992GW_REG_PWRSRCINT 0x04 -#define BD99992GW_REG_RESETIRQ1 0x08 -#define BD99992GW_REG_PBCONFIG 0x14 -#define BD99992GW_REG_PWRSTAT1 0x16 -#define BD99992GW_REG_PWRSTAT2 0x17 -#define BD99992GW_REG_VCCIOCNT 0x30 -#define BD99992GW_REG_V5ADS3CNT 0x31 -#define BD99992GW_REG_V18ACNT 0x34 -#define BD99992GW_REG_V100ACNT 0x37 -#define BD99992GW_REG_V085ACNT 0x38 -#define BD99992GW_REG_VRMODECTRL 0x3b -#define BD99992GW_REG_DISCHGCNT1 0x3c -#define BD99992GW_REG_DISCHGCNT2 0x3d -#define BD99992GW_REG_DISCHGCNT3 0x3e -#define BD99992GW_REG_DISCHGCNT4 0x3f -#define BD99992GW_REG_SDWNCTRL 0x49 -#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */ +#define BD99992GW_REG_PWRSRCINT 0x04 +#define BD99992GW_REG_RESETIRQ1 0x08 +#define BD99992GW_REG_PBCONFIG 0x14 +#define BD99992GW_REG_PWRSTAT1 0x16 +#define BD99992GW_REG_PWRSTAT2 0x17 +#define BD99992GW_REG_VCCIOCNT 0x30 +#define BD99992GW_REG_V5ADS3CNT 0x31 +#define BD99992GW_REG_V18ACNT 0x34 +#define BD99992GW_REG_V100ACNT 0x37 +#define BD99992GW_REG_V085ACNT 0x38 +#define BD99992GW_REG_VRMODECTRL 0x3b +#define BD99992GW_REG_DISCHGCNT1 0x3c +#define BD99992GW_REG_DISCHGCNT2 0x3d +#define BD99992GW_REG_DISCHGCNT3 0x3e +#define BD99992GW_REG_DISCHGCNT4 0x3f +#define BD99992GW_REG_SDWNCTRL 0x49 +#define BD99992GW_SDWNCTRL_SWDN BIT(0) /* SWDN mask */ -#endif /* __CROS_EC_PMIC_BD99992GW_H */ +#endif /* __CROS_EC_PMIC_BD99992GW_H */ -- cgit v1.2.1 From 0b49c2b132e5f18168927b53f791c1aaaefe417b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:04 -0600 Subject: board/elm/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic33c85a40d611b1edb1706ba2f544144afb7a078 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728310 Reviewed-by: Jeremy Bettis --- board/elm/board.c | 98 ++++++++++++++++++++++++------------------------------- 1 file changed, 43 insertions(+), 55 deletions(-) diff --git a/board/elm/board.c b/board/elm/board.c index 1c7cc4b320..dcaca1b004 100644 --- a/board/elm/board.c +++ b/board/elm/board.c @@ -49,8 +49,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Dispaly port hardware can connect to port 0, 1 or neither. */ #define PD_PORT_NONE -1 @@ -73,8 +73,8 @@ void usb_evt(enum gpio_signal signal) /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"}, - {GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"}, + { GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" }, + { GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -84,11 +84,11 @@ const struct adc_t adc_channels[] = { * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm * output in mW */ - [ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)}, + [ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) }, /* AMON_BMON(PC0): ADC_IN10, output in uV */ - [ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)}, + [ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) }, /* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */ - [ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)}, + [ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -107,23 +107,18 @@ int anx7688_passthru_allowed(const struct i2c_port_t *port, } /* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "pd", - .port = I2C_PORT_PD_MCU, - .kbps = 1000, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA, - .passthru_allowed = anx7688_passthru_allowed - } -}; +const struct i2c_port_t i2c_ports[] = { { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "pd", + .port = I2C_PORT_PD_MCU, + .kbps = 1000, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA, + .passthru_allowed = + anx7688_passthru_allowed } }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -162,22 +157,21 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) == */ const struct temp_sensor_t temp_sensors[] = { #ifdef CONFIG_TEMP_SENSOR_TMP432 - {"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, - {"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE2}, + { "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, + { "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE2 }, #endif - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, - 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { .usb_port = 0, - .driver = &anx7688_usb_mux_driver, + .driver = &anx7688_usb_mux_driver, }, }; @@ -207,7 +201,7 @@ void deferred_reset_pd_mcu(void) * and wait for 1ms. */ gpio_set_level(GPIO_USB_C0_PWR_EN_L, 1); - hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC); + hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC); break; case 1: /* @@ -215,7 +209,7 @@ void deferred_reset_pd_mcu(void) * pull PD reset pin and wait for another 1ms */ gpio_set_level(GPIO_USB_C0_RST, 1); - hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC); + hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC); /* on PD reset, trigger PD task to reset state */ task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET); break; @@ -225,7 +219,7 @@ void deferred_reset_pd_mcu(void) * enable power and wait for 10ms then pull RESET_N */ gpio_set_level(GPIO_USB_C0_PWR_EN_L, 0); - hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC); + hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC); break; case 2: /* @@ -244,7 +238,7 @@ static void board_power_on_pd_mcu(void) return; gpio_set_level(GPIO_USB_C0_EXTPWR_EN, 1); - hook_call_deferred(&deferred_reset_pd_mcu_data, 1*MSEC); + hook_call_deferred(&deferred_reset_pd_mcu_data, 1 * MSEC); } void board_reset_pd_mcu(void) @@ -253,7 +247,7 @@ void board_reset_pd_mcu(void) anx7688_enable_cable_detection(0); /* wait for 10ms, then start port controller's reset sequence */ - hook_call_deferred(&deferred_reset_pd_mcu_data, 10*MSEC); + hook_call_deferred(&deferred_reset_pd_mcu_data, 10 * MSEC); } static int command_pd_reset(int argc, char **argv) @@ -261,9 +255,7 @@ static int command_pd_reset(int argc, char **argv) board_reset_pd_mcu(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset, - "", - "Reset PD IC"); +DECLARE_CONSOLE_COMMAND(resetpd, command_pd_reset, "", "Reset PD IC"); /** * There is a level shift for AC_OK & LID_OPEN signal between AP & EC, @@ -342,13 +334,13 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Limit input current 95% ratio on elm board for safety */ charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); pd_send_host_event(PD_EVENT_POWER_CHANGE); } @@ -464,17 +456,13 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); static struct mutex g_kx022_mutex[2]; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* KX022 private data */ struct kionix_accel_data g_kx022_data[2]; -- cgit v1.2.1 From bb7c307e1044b645500426f60ee556f3dae5ca5f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:15 -0600 Subject: board/brya/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9901b2a44edffc45b0abc6fb1d30ef7c6416fbdf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728097 Reviewed-by: Jeremy Bettis --- board/brya/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/brya/board.c b/board/brya/board.c index 32c3aaed3e..b73f7b2d8b 100644 --- a/board/brya/board.c +++ b/board/brya/board.c @@ -28,8 +28,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) __override void board_cbi_init(void) { -- cgit v1.2.1 From 5bea2e04d18f66e15caadc1746214e34c582b92e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:20 -0600 Subject: include/queue_policies.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I96af0acdd23eacfc1a969ad01a9e668801ce1010 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730395 Reviewed-by: Jeremy Bettis --- include/queue_policies.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/queue_policies.h b/include/queue_policies.h index b9d698072f..4e01cfc23a 100644 --- a/include/queue_policies.h +++ b/include/queue_policies.h @@ -27,7 +27,7 @@ struct queue_policy_direct { void queue_add_direct(struct queue_policy const *policy, size_t count); void queue_remove_direct(struct queue_policy const *policy, size_t count); -#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \ +#define QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER) \ ((struct queue_policy_direct const) { \ .policy = { \ .add = queue_add_direct, \ @@ -37,7 +37,7 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count); .consumer = &CONSUMER, \ }) -#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \ +#define QUEUE_DIRECT(SIZE, TYPE, PRODUCER, CONSUMER) \ QUEUE(SIZE, TYPE, QUEUE_POLICY_DIRECT(PRODUCER, CONSUMER).policy) /* -- cgit v1.2.1 From b67936e1c6b1f90728e7ea61a151b62d5bb99200 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:28 -0600 Subject: driver/led/max695x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idcc654f513f682fcfa77ed3dbfc85d0d833717e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729999 Reviewed-by: Jeremy Bettis --- driver/led/max695x.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/driver/led/max695x.c b/driver/led/max695x.c index c6155f1499..e48ae4482a 100644 --- a/driver/led/max695x.c +++ b/driver/led/max695x.c @@ -13,12 +13,11 @@ #include "max695x.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static inline int max695x_i2c_write8(uint8_t offset, uint8_t data) { - return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR, - offset, (int)data); + return i2c_write8(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, (int)data); } static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len) @@ -27,8 +26,8 @@ static inline int max695x_i2c_write(uint8_t offset, uint8_t *data, int len) * The address pointer stored in the MAX695x increments after * each data byte is written unless the address equals 01111111 */ - return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR, - offset, data, len); + return i2c_write_block(I2C_PORT_PORT80, PORT80_I2C_ADDR, offset, data, + len); } int display_7seg_write(enum seven_seg_module_display module, uint16_t data) @@ -84,12 +83,10 @@ int display_7seg_write(enum seven_seg_module_display module, uint16_t data) */ static void max695x_init(void) { - uint8_t buf[4] = { - [0] = MAX695X_DECODE_MODE_HEX_DECODE, - [1] = MAX695X_INTENSITY_MEDIUM, - [2] = MAX695X_SCAN_LIMIT_4, - [3] = MAX695X_CONFIG_OPR_NORMAL - }; + uint8_t buf[4] = { [0] = MAX695X_DECODE_MODE_HEX_DECODE, + [1] = MAX695X_INTENSITY_MEDIUM, + [2] = MAX695X_SCAN_LIMIT_4, + [3] = MAX695X_CONFIG_OPR_NORMAL }; max695x_i2c_write(MAX695X_REG_DECODE_MODE, buf, ARRAY_SIZE(buf)); } DECLARE_HOOK(HOOK_INIT, max695x_init, HOOK_PRIO_DEFAULT); @@ -97,8 +94,7 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, max695x_init, HOOK_PRIO_DEFAULT); static void max695x_shutdown(void) { - max695x_i2c_write8(MAX695X_REG_CONFIG, - MAX695X_CONFIG_OPR_SHUTDOWN); + max695x_i2c_write8(MAX695X_REG_CONFIG, MAX695X_CONFIG_OPR_SHUTDOWN); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, max695x_shutdown, HOOK_PRIO_DEFAULT); @@ -118,7 +114,6 @@ static int console_command_max695x_write(int argc, char **argv) return display_7seg_write(SEVEN_SEG_CONSOLE_DISPLAY, val); } -DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write, - "", +DECLARE_CONSOLE_COMMAND(seg, console_command_max695x_write, "", "Write to 7 segment display in hex"); #endif -- cgit v1.2.1 From 2de466d3a871560121b1177846e6267a1658cbe7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:26 -0600 Subject: zephyr/emul/emul_sn5s330.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32f7d6ad7a91552ea4b4bfa6ac39bdb9d1f8aa1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730697 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_sn5s330.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/zephyr/emul/emul_sn5s330.c b/zephyr/emul/emul_sn5s330.c index 8f8c3cd852..1b58e8e9ad 100644 --- a/zephyr/emul/emul_sn5s330.c +++ b/zephyr/emul/emul_sn5s330.c @@ -346,10 +346,9 @@ static int emul_sn5s330_init(const struct emul *emul, #define SN5S330_GET_GPIO_INT_PORT(n) \ DEVICE_DT_GET(DT_GPIO_CTLR(DT_INST_PROP(n, int_pin), gpios)) -#define SN5S330_GET_GPIO_INT_PIN(n) \ - DT_GPIO_PIN(DT_INST_PROP(n, int_pin), gpios) +#define SN5S330_GET_GPIO_INT_PIN(n) DT_GPIO_PIN(DT_INST_PROP(n, int_pin), gpios) -#define INIT_SN5S330(n) \ +#define INIT_SN5S330(n) \ static struct sn5s330_emul_data sn5s330_emul_data_##n = { \ .common = { \ .write_byte = sn5s330_emul_write_byte, \ @@ -357,15 +356,15 @@ static int emul_sn5s330_init(const struct emul *emul, }, \ .gpio_int_port = SN5S330_GET_GPIO_INT_PORT(n), \ .gpio_int_pin = SN5S330_GET_GPIO_INT_PIN(n), \ - }; \ + }; \ static struct sn5s330_emul_cfg sn5s330_emul_cfg_##n = { \ .common = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ - }; \ - EMUL_DEFINE(emul_sn5s330_init, DT_DRV_INST(n), &sn5s330_emul_cfg_##n, \ + }; \ + EMUL_DEFINE(emul_sn5s330_init, DT_DRV_INST(n), &sn5s330_emul_cfg_##n, \ &sn5s330_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(INIT_SN5S330) -- cgit v1.2.1 From 40169b6a36b5b898e8a4d4d7dcd316d2e2f6c4a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:34 -0600 Subject: common/spi_nor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie478105912bcc8ea50bf3f1012e11d59a7b352ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729733 Reviewed-by: Jeremy Bettis --- common/spi_nor.c | 239 ++++++++++++++++++++++++++----------------------------- 1 file changed, 111 insertions(+), 128 deletions(-) diff --git a/common/spi_nor.c b/common/spi_nor.c index 0a719d63b3..e8ef49d061 100644 --- a/common/spi_nor.c +++ b/common/spi_nor.c @@ -18,7 +18,7 @@ #ifdef CONFIG_SPI_NOR_DEBUG #define CPRINTS(dev, string, args...) \ - cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ## args) + cprints(CC_SPI, "SPI NOR %s: " string, (dev)->name, ##args) #else #define CPRINTS(dev, string, args...) #endif @@ -74,8 +74,8 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device) int rv = EC_SUCCESS; /* Set the write enable latch. */ - rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], - &cmd, 1, NULL, 0); + rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd, + 1, NULL, 0); if (rv) return rv; @@ -84,7 +84,7 @@ static int spi_nor_write_enable(const struct spi_nor_device_t *spi_nor_device) if (rv) return rv; if ((status_register_value & SPI_NOR_STATUS_REGISTER_WEL) == 0) - return EC_ERROR_UNKNOWN; /* WEL not set but should be. */ + return EC_ERROR_UNKNOWN; /* WEL not set but should be. */ return rv; } @@ -101,7 +101,7 @@ static int spi_nor_read_ear(const struct spi_nor_device_t *spi_nor_device, uint8_t command = SPI_NOR_OPCODE_RDEAR; return spi_transaction(&spi_devices[spi_nor_device->spi_controller], - &command, sizeof(command), value, 1); + &command, sizeof(command), value, 1); } int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, @@ -122,8 +122,8 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, buf[0] = SPI_NOR_OPCODE_WREAR; buf[1] = value; - rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], - buf, sizeof(buf), NULL, 0); + rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], buf, + sizeof(buf), NULL, 0); if (rv) { CPRINTS(spi_nor_device, "Failed to write EAR, rv=%d", rv); goto err_free; @@ -134,9 +134,9 @@ int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, goto err_free; if (ear != value) { - CPRINTS(spi_nor_device, - "Write EAR error: write=%d, read=%d", value, ear); - rv = EC_ERROR_UNKNOWN; /* WEL not set but should be. */ + CPRINTS(spi_nor_device, "Write EAR error: write=%d, read=%d", + value, ear); + rv = EC_ERROR_UNKNOWN; /* WEL not set but should be. */ goto err_free; } @@ -157,8 +157,7 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device) rv = spi_nor_read_status(spi_nor_device, &status_register_value); if (rv) return rv; - timeout.val = - get_time().val + spi_nor_device->timeout_usec; + timeout.val = get_time().val + spi_nor_device->timeout_usec; while (status_register_value & SPI_NOR_STATUS_REGISTER_WIP) { /* Reload the watchdog before sleeping. */ watchdog_reload(); @@ -181,10 +180,9 @@ static int spi_nor_wait(const struct spi_nor_device_t *spi_nor_device) /** * Read the Manufacturer bank and ID out of the JEDEC ID. */ -static int spi_nor_read_jedec_mfn_id( - const struct spi_nor_device_t *spi_nor_device, - uint8_t *out_mfn_bank, - uint8_t *out_mfn_id) +static int +spi_nor_read_jedec_mfn_id(const struct spi_nor_device_t *spi_nor_device, + uint8_t *out_mfn_bank, uint8_t *out_mfn_id) { int rv = EC_SUCCESS; uint8_t jedec_id[SPI_NOR_JEDEC_ID_BANKS]; @@ -192,8 +190,8 @@ static int spi_nor_read_jedec_mfn_id( uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID; /* Read the standardized part of the JEDEC ID. */ - rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], - &cmd, 1, jedec_id, SPI_NOR_JEDEC_ID_BANKS); + rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd, + 1, jedec_id, SPI_NOR_JEDEC_ID_BANKS); if (rv) return rv; @@ -214,11 +212,11 @@ static int spi_nor_read_jedec_mfn_id( /** * Read a doubleword out of a SFDP table (DWs are 1-based like the SFDP spec). */ -static int spi_nor_read_sfdp_dword( - const struct spi_nor_device_t *spi_nor_device, - uint32_t table_offset, - uint8_t table_double_word, - uint32_t *out_dw) { +static int +spi_nor_read_sfdp_dword(const struct spi_nor_device_t *spi_nor_device, + uint32_t table_offset, uint8_t table_double_word, + uint32_t *out_dw) +{ uint8_t sfdp_cmd[5]; /* Calculate the byte offset based on the double word. */ uint32_t sfdp_offset = table_offset + ((table_double_word - 1) * 4); @@ -228,7 +226,7 @@ static int spi_nor_read_sfdp_dword( sfdp_cmd[1] = (sfdp_offset & 0xFF0000) >> 16; sfdp_cmd[2] = (sfdp_offset & 0xFF00) >> 8; sfdp_cmd[3] = (sfdp_offset & 0xFF); - sfdp_cmd[4] = 0; /* Required extra cycle. */ + sfdp_cmd[4] = 0; /* Required extra cycle. */ return spi_transaction(&spi_devices[spi_nor_device->spi_controller], sfdp_cmd, 5, (uint8_t *)out_dw, 4); } @@ -248,10 +246,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev, BASIC_FLASH_PARAMETER_TABLE_1_0_ID); } else if (sfdp_major_rev == 1 && sfdp_minor_rev >= 5) { return ((SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, - parameter_header_dw1) == + parameter_header_dw1) == BASIC_FLASH_PARAMETER_TABLE_1_5_ID_LSB) && (SFDP_GET_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, - parameter_header_dw2) == + parameter_header_dw2) == BASIC_FLASH_PARAMETER_TABLE_1_5_ID_MSB)); } @@ -262,13 +260,10 @@ static int is_basic_flash_parameter_table(uint8_t sfdp_major_rev, * Helper function to locate the SFDP Basic SPI Flash NOR Parameter Table. */ static int locate_sfdp_basic_parameter_table( - const struct spi_nor_device_t *spi_nor_device, - uint8_t *out_sfdp_major_rev, - uint8_t *out_sfdp_minor_rev, - uint8_t *out_table_major_rev, - uint8_t *out_table_minor_rev, - uint32_t *out_table_offset, - size_t *out_table_size) + const struct spi_nor_device_t *spi_nor_device, + uint8_t *out_sfdp_major_rev, uint8_t *out_sfdp_minor_rev, + uint8_t *out_table_major_rev, uint8_t *out_table_minor_rev, + uint32_t *out_table_offset, size_t *out_table_size) { int rv = EC_SUCCESS; uint8_t number_parameter_headers; @@ -296,8 +291,8 @@ static int locate_sfdp_basic_parameter_table( SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, dw2); *out_sfdp_minor_rev = SFDP_GET_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, dw2); - CPRINTS(spi_nor_device, "SFDP v%d.%d discovered", - *out_sfdp_major_rev, *out_sfdp_minor_rev); + CPRINTS(spi_nor_device, "SFDP v%d.%d discovered", *out_sfdp_major_rev, + *out_sfdp_minor_rev); /* NPH is 0-based, so add 1. */ number_parameter_headers = @@ -315,17 +310,16 @@ static int locate_sfdp_basic_parameter_table( number_parameter_headers--; /* Read this parameter header's two dwords. */ - rv = spi_nor_read_sfdp_dword( - spi_nor_device, table_offset, 1, &dw1); - rv |= spi_nor_read_sfdp_dword( - spi_nor_device, table_offset, 2, &dw2); + rv = spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 1, + &dw1); + rv |= spi_nor_read_sfdp_dword(spi_nor_device, table_offset, 2, + &dw2); if (rv) return rv; /* Ensure it's the basic flash parameter table. */ - if (!is_basic_flash_parameter_table(*out_sfdp_major_rev, - *out_sfdp_minor_rev, - dw1, dw2)) + if (!is_basic_flash_parameter_table( + *out_sfdp_major_rev, *out_sfdp_minor_rev, dw1, dw2)) continue; /* The parameter header major and minor versioning is still the @@ -352,8 +346,10 @@ static int locate_sfdp_basic_parameter_table( *out_table_offset = SFDP_GET_BITFIELD( SFDP_1_0_PARAMETER_HEADER_DW2_PTP, dw2); /* Convert the size from DW to Bytes. */ - *out_table_size = SFDP_GET_BITFIELD( - SFDP_1_0_PARAMETER_HEADER_DW1_PTL, dw1) * 4; + *out_table_size = + SFDP_GET_BITFIELD(SFDP_1_0_PARAMETER_HEADER_DW1_PTL, + dw1) * + 4; } if (!table_found) { @@ -376,8 +372,7 @@ static int spi_nor_device_discover_sfdp_page_size( struct spi_nor_device_t *spi_nor_device, uint8_t basic_parameter_table_major_version, uint8_t basic_parameter_table_minor_version, - uint32_t basic_parameter_table_offset, - size_t *page_size) + uint32_t basic_parameter_table_offset, size_t *page_size) { int rv = EC_SUCCESS; uint32_t dw; @@ -397,12 +392,12 @@ static int spi_nor_device_discover_sfdp_page_size( } else if (basic_parameter_table_major_version == 1 && basic_parameter_table_minor_version >= 5) { /* Use the Basic Flash Parameter v1.5 page size reporting. */ - rv = spi_nor_read_sfdp_dword(spi_nor_device, - basic_parameter_table_offset, 11, &dw); + rv = spi_nor_read_sfdp_dword( + spi_nor_device, basic_parameter_table_offset, 11, &dw); if (rv) return rv; - *page_size = - 1 << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw); + *page_size = 1 + << SFDP_GET_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, dw); } return EC_SUCCESS; @@ -413,11 +408,10 @@ static int spi_nor_device_discover_sfdp_page_size( * NOR Parameter Table. */ static int spi_nor_device_discover_sfdp_capacity( - struct spi_nor_device_t *spi_nor_device, - uint8_t basic_parameter_table_major_version, - uint8_t basic_parameter_table_minor_version, - uint32_t basic_parameter_table_offset, - uint32_t *capacity) + struct spi_nor_device_t *spi_nor_device, + uint8_t basic_parameter_table_major_version, + uint8_t basic_parameter_table_minor_version, + uint32_t basic_parameter_table_offset, uint32_t *capacity) { int rv = EC_SUCCESS; uint32_t dw; @@ -425,15 +419,16 @@ static int spi_nor_device_discover_sfdp_capacity( /* First attempt to discover the device's capacity. */ if (basic_parameter_table_major_version == 1) { /* Use the Basic Flash Parameter v1.0 capacity reporting. */ - rv = spi_nor_read_sfdp_dword(spi_nor_device, - basic_parameter_table_offset, 2, &dw); + rv = spi_nor_read_sfdp_dword( + spi_nor_device, basic_parameter_table_offset, 2, &dw); if (rv) return rv; if (SFDP_GET_BITFIELD(BFPT_1_0_DW2_GT_2_GIBIBITS, dw)) { /* Ensure the capacity is less than 4GiB. */ - uint64_t tmp_capacity = 1 << - (SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3); + uint64_t tmp_capacity = + 1 + << (SFDP_GET_BITFIELD(BFPT_1_0_DW2_N, dw) - 3); if (tmp_capacity > UINT32_MAX) return EC_ERROR_OVERFLOW; *capacity = tmp_capacity; @@ -456,8 +451,7 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device, * is larger than the maximum read size. */ while (size > 0) { - size_t read_size = - MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE); + size_t read_size = MIN(size, CONFIG_SPI_NOR_MAX_READ_SIZE); size_t read_command_size; /* Set up the read command in the TX buffer. */ @@ -468,7 +462,7 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device, buf[3] = (offset & 0xFF00) >> 8; buf[4] = (offset & 0xFF); read_command_size = 5; - } else { /* in 3 byte addressing mode */ + } else { /* in 3 byte addressing mode */ buf[1] = (offset & 0xFF0000) >> 16; buf[2] = (offset & 0xFF00) >> 8; buf[3] = (offset & 0xFF); @@ -476,8 +470,8 @@ static int spi_nor_read_internal(const struct spi_nor_device_t *spi_nor_device, } rv = spi_transaction( - &spi_devices[spi_nor_device->spi_controller], - buf, read_command_size, data, read_size); + &spi_devices[spi_nor_device->spi_controller], buf, + read_command_size, data, read_size); if (rv) return rv; @@ -513,16 +507,12 @@ int spi_nor_init(void) uint8_t table_major_rev, table_minor_rev; uint32_t table_offset; size_t table_size; - struct spi_nor_device_t *spi_nor_device = - &spi_nor_devices[i]; + struct spi_nor_device_t *spi_nor_device = &spi_nor_devices[i]; - rv |= locate_sfdp_basic_parameter_table(spi_nor_device, - &sfdp_major_rev, - &sfdp_minor_rev, - &table_major_rev, - &table_minor_rev, - &table_offset, - &table_size); + rv |= locate_sfdp_basic_parameter_table( + spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev, + &table_major_rev, &table_minor_rev, &table_offset, + &table_size); /* If we failed to find a compatible SFDP Basic Flash Parameter * table, use the default capacity, page size, and addressing @@ -532,13 +522,11 @@ int spi_nor_init(void) uint32_t capacity = 0; rv |= spi_nor_device_discover_sfdp_page_size( - spi_nor_device, - table_major_rev, table_minor_rev, table_offset, - &page_size); + spi_nor_device, table_major_rev, + table_minor_rev, table_offset, &page_size); rv |= spi_nor_device_discover_sfdp_capacity( - spi_nor_device, - table_major_rev, table_minor_rev, table_offset, - &capacity); + spi_nor_device, table_major_rev, + table_minor_rev, table_offset, &capacity); if (rv == EC_SUCCESS) { mutex_lock(&driver_mutex); spi_nor_device->capacity = capacity; @@ -595,8 +583,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device, /* Claim the driver mutex to modify the device state. */ mutex_lock(&driver_mutex); - rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], - &cmd, 1, NULL, 0); + rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd, + 1, NULL, 0); if (rv == EC_SUCCESS) { spi_nor_device->in_4b_addressing_mode = enter_4b_addressing_mode; @@ -619,7 +607,8 @@ int spi_nor_set_4b_mode(struct spi_nor_device_t *spi_nor_device, * @return ec_error_list (non-zero on error and timeout). */ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, - size_t size, uint8_t *data) { + size_t size, uint8_t *data) +{ int rv; uint8_t cmd = SPI_NOR_OPCODE_JEDEC_ID; @@ -628,8 +617,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, /* Claim the driver mutex. */ mutex_lock(&driver_mutex); /* Read the JEDEC ID. */ - rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], - &cmd, 1, data, size); + rv = spi_transaction(&spi_devices[spi_nor_device->spi_controller], &cmd, + 1, data, size); /* Release the driver mutex. */ mutex_unlock(&driver_mutex); @@ -645,8 +634,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, * @param data Destination buffer for data. * @return ec_error_list (non-zero on error and timeout). */ -int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, - uint32_t offset, size_t size, uint8_t *data) +int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset, + size_t size, uint8_t *data) { int rv; @@ -708,8 +697,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device, read_offset = offset; read_left = erase_size; while (read_left) { - read_size = MIN(read_left, - CONFIG_SPI_NOR_MAX_READ_SIZE); + read_size = + MIN(read_left, CONFIG_SPI_NOR_MAX_READ_SIZE); /* Since CONFIG_SPI_NOR_MAX_READ_SIZE & erase_size are * both guaranteed to be multiples of 4. */ @@ -731,8 +720,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device, */ verify_offset = 0; while (verify_offset <= read_size - 4) { - if (*(uint32_t *)(buffer + verify_offset) - != 0xffffffff) { + if (*(uint32_t *)(buffer + verify_offset) != + 0xffffffff) { break; } verify_offset += 4; @@ -767,7 +756,7 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device, buf[3] = (offset & 0xFF00) >> 8; buf[4] = (offset & 0xFF); erase_command_size = 5; - } else { /* in 3 byte addressing mode */ + } else { /* in 3 byte addressing mode */ buf[1] = (offset & 0xFF0000) >> 16; buf[2] = (offset & 0xFF00) >> 8; buf[3] = (offset & 0xFF); @@ -775,8 +764,8 @@ int spi_nor_erase(const struct spi_nor_device_t *spi_nor_device, } rv = spi_transaction( - &spi_devices[spi_nor_device->spi_controller], - buf, erase_command_size, NULL, 0); + &spi_devices[spi_nor_device->spi_controller], buf, + erase_command_size, NULL, 0); if (rv) goto err_free; @@ -814,8 +803,8 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, /* Ensure the device's page size fits in the driver's buffer, if not * emulate a smaller page size based on the buffer size. */ - effective_page_size = MIN(spi_nor_device->page_size, - CONFIG_SPI_NOR_MAX_WRITE_SIZE); + effective_page_size = + MIN(spi_nor_device->page_size, CONFIG_SPI_NOR_MAX_WRITE_SIZE); /* Split the write into multiple writes if the size is too large. */ while (size > 0) { @@ -843,7 +832,7 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, buf[3] = (offset & 0xFF00) >> 8; buf[4] = (offset & 0xFF); prefix_size = 5; - } else { /* in 3 byte addressing mode */ + } else { /* in 3 byte addressing mode */ buf[1] = (offset & 0xFF0000) >> 16; buf[2] = (offset & 0xFF00) >> 8; buf[3] = (offset & 0xFF); @@ -853,8 +842,8 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, memmove(buf + prefix_size, data, write_size); rv = spi_transaction( - &spi_devices[spi_nor_device->spi_controller], - buf, prefix_size + write_size, NULL, 0); + &spi_devices[spi_nor_device->spi_controller], buf, + prefix_size + write_size, NULL, 0); if (rv) goto err_free; @@ -908,14 +897,13 @@ static int command_spi_nor_info(int argc, char **argv) ccprintf("\tName: %s\n", spi_nor_device->name); ccprintf("\tSPI controller index: %d\n", spi_nor_device->spi_controller); - ccprintf("\tTimeout: %d uSec\n", - spi_nor_device->timeout_usec); + ccprintf("\tTimeout: %d uSec\n", spi_nor_device->timeout_usec); ccprintf("\tCapacity: %d KiB\n", spi_nor_device->capacity >> 10), - ccprintf("\tAddressing: %s addressing mode\n", - spi_nor_device->in_4b_addressing_mode ? "4B" : "3B"); - ccprintf("\tPage Size: %d Bytes\n", - spi_nor_device->page_size); + ccprintf("\tAddressing: %s addressing mode\n", + spi_nor_device->in_4b_addressing_mode ? "4B" : + "3B"); + ccprintf("\tPage Size: %d Bytes\n", spi_nor_device->page_size); /* Get JEDEC ID info. */ rv = spi_nor_read_jedec_mfn_id(spi_nor_device, &mfn_bank, @@ -927,24 +915,23 @@ static int command_spi_nor_info(int argc, char **argv) /* Get SFDP info. */ if (locate_sfdp_basic_parameter_table( - spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev, - &table_major_rev, &table_minor_rev, &table_offset, - &table_size) != EC_SUCCESS) { + spi_nor_device, &sfdp_major_rev, &sfdp_minor_rev, + &table_major_rev, &table_minor_rev, &table_offset, + &table_size) != EC_SUCCESS) { ccputs("\tNo JEDEC SFDP support detected\n"); - continue; /* Go on to the next device. */ + continue; /* Go on to the next device. */ } ccprintf("\tSFDP v%d.%d\n", sfdp_major_rev, sfdp_minor_rev); ccprintf("\tFlash Parameter Table v%d.%d (%dB @ 0x%x)\n", - table_major_rev, table_minor_rev, - table_size, table_offset); + table_major_rev, table_minor_rev, table_size, + table_offset); } return rv; } -DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info, - "[device]", +DECLARE_CONSOLE_COMMAND(spinorinfo, command_spi_nor_info, "[device]", "Report Serial NOR Flash device information"); -#endif /* CONFIG_CMD_SPI_NOR */ +#endif /* CONFIG_CMD_SPI_NOR */ #ifdef CONFIG_CMD_SPI_NOR static int command_spi_nor_erase(int argc, char **argv) @@ -967,14 +954,13 @@ static int command_spi_nor_erase(int argc, char **argv) if (rv) return rv; - ccprintf("Erasing %d bytes at 0x%x on %s...\n", - size, offset, spi_nor_device->name); + ccprintf("Erasing %d bytes at 0x%x on %s...\n", size, offset, + spi_nor_device->name); return spi_nor_erase(spi_nor_device, offset, size); } DECLARE_CONSOLE_COMMAND(spinorerase, command_spi_nor_erase, - "device [offset] [size]", - "Erase flash"); -#endif /* CONFIG_CMD_SPI_NOR */ + "device [offset] [size]", "Erase flash"); +#endif /* CONFIG_CMD_SPI_NOR */ #ifdef CONFIG_CMD_SPI_NOR static int command_spi_nor_write(int argc, char **argv) @@ -1013,8 +999,8 @@ static int command_spi_nor_write(int argc, char **argv) for (i = 0; i < size; i++) data[i] = i; - ccprintf("Writing %d bytes to 0x%x on %s...\n", - size, offset, spi_nor_device->name); + ccprintf("Writing %d bytes to 0x%x on %s...\n", size, offset, + spi_nor_device->name); rv = spi_nor_write(spi_nor_device, offset, size, data); /* Free the buffer */ @@ -1023,9 +1009,8 @@ static int command_spi_nor_write(int argc, char **argv) return rv; } DECLARE_CONSOLE_COMMAND(spinorwrite, command_spi_nor_write, - "device [offset] [size]", - "Write pattern to flash"); -#endif /* CONFIG_CMD_SPI_NOR */ + "device [offset] [size]", "Write pattern to flash"); +#endif /* CONFIG_CMD_SPI_NOR */ #ifdef CONFIG_CMD_SPI_NOR static int command_spi_nor_read(int argc, char **argv) @@ -1061,8 +1046,7 @@ static int command_spi_nor_read(int argc, char **argv) } /* Read the data */ - ccprintf("Reading %d bytes from %s...", - size, spi_nor_device->name); + ccprintf("Reading %d bytes from %s...", size, spi_nor_device->name); if (spi_nor_read(spi_nor_device, offset, size, data)) { rv = EC_ERROR_INVAL; goto err_free; @@ -1086,6 +1070,5 @@ err_free: return rv; } DECLARE_CONSOLE_COMMAND(spinorread, command_spi_nor_read, - "device [offset] [size]", - "Read flash"); -#endif /* CONFIG_CMD_SPI_NOR */ + "device [offset] [size]", "Read flash"); +#endif /* CONFIG_CMD_SPI_NOR */ -- cgit v1.2.1 From a26f85a54413ba7720e20823c32360cf89bc0971 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:47 -0600 Subject: board/wheelie/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97daeb8eb1431312cf181e83c970d288bda111dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729127 Reviewed-by: Jeremy Bettis --- board/wheelie/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/wheelie/cbi_ssfc.c b/board/wheelie/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/wheelie/cbi_ssfc.c +++ b/board/wheelie/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From a61728b0d8de8624aeb817dff3f03dd5992252c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:40 -0600 Subject: board/brya/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifee1e0c65d13baa15a25333acaed5370a3ce8070 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728046 Reviewed-by: Jeremy Bettis --- board/brya/usbc_config.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c index 90d113ae51..7d0947ed19 100644 --- a/board/brya/usbc_config.c +++ b/board/brya/usbc_config.c @@ -36,8 +36,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #ifdef CONFIG_ZEPHYR enum ioex_port { @@ -84,7 +84,7 @@ const struct tcpc_config_t tcpc_config[] = { }; BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); -#endif /* !CONFIG_ZEPHYR */ +#endif /* !CONFIG_ZEPHYR */ /******************************************************************************/ /* USB-A charging control */ @@ -241,8 +241,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -354,11 +354,11 @@ static void board_tcpc_init(void) if (!system_jumped_late()) board_reset_pd_mcu(); - /* - * These IO expander pins are implemented using the - * C0/C2 TCPC, so they must be set up after the TCPC has - * been taken out of reset. - */ + /* + * These IO expander pins are implemented using the + * C0/C2 TCPC, so they must be set up after the TCPC has + * been taken out of reset. + */ #ifndef CONFIG_ZEPHYR ioex_init(IOEX_C0_NCT38XX); ioex_init(IOEX_C2_NCT38XX); -- cgit v1.2.1 From 5b339dbbc38ddf81c523a4b2243d41321bae24ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:24 -0600 Subject: board/lazor/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d1ae13d5d04f5ea4d46969e5fe863790e2f83bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728619 Reviewed-by: Jeremy Bettis --- board/lazor/board.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/board/lazor/board.h b/board/lazor/board.h index f4f722c6a2..bdc16d7594 100644 --- a/board/lazor/board.h +++ b/board/lazor/board.h @@ -11,7 +11,7 @@ #include "baseboard.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Reduce flash usage */ #define CONFIG_USB_PD_DEBUG_LEVEL 2 @@ -25,7 +25,7 @@ #define CONFIG_PWM_KBLIGHT /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE @@ -91,12 +91,7 @@ #include "registers.h" #include "sku.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -106,11 +101,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From fd928db70b52b56ec94279756822a4101a39d78a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:18 -0600 Subject: zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia416d7cb3df7a62d2982e43ecd6e15579752b533 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730677 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c | 78 +++++++++++++------------ 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c index 661268ee9b..2880801d72 100644 --- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c +++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.c @@ -43,8 +43,8 @@ enum timer_type { * type == RTC_TIMER: Reads time registers SECONDS, MINUTES, HOURS, DAYS, and * MONTHS, YEARS */ -static int idt1337ag_read_time_regs(const struct device *dev, - uint8_t *time_reg, enum timer_type type) +static int idt1337ag_read_time_regs(const struct device *dev, uint8_t *time_reg, + enum timer_type type) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; uint8_t start_reg; @@ -58,12 +58,12 @@ static int idt1337ag_read_time_regs(const struct device *dev, num_reg = NUM_TIMER_REGS; } - return i2c_burst_read(config->bus, - config->i2c_addr_flags, start_reg, time_reg, num_reg); + return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg, + time_reg, num_reg); } -static int idt1337ag_read_reg(const struct device *dev, - uint8_t reg, uint8_t *val) +static int idt1337ag_read_reg(const struct device *dev, uint8_t reg, + uint8_t *val) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; @@ -97,12 +97,12 @@ static int idt1337ag_write_time_regs(const struct device *dev, num_reg = NUM_TIMER_REGS; } - return i2c_burst_write(config->bus, - config->i2c_addr_flags, start_reg, time_reg, num_reg); + return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg, + time_reg, num_reg); } -static int idt1337ag_write_reg(const struct device *dev, - uint8_t reg, uint8_t val) +static int idt1337ag_write_reg(const struct device *dev, uint8_t reg, + uint8_t val) { const struct renesas_rtc_idt1337ag_config *const config = dev->config; uint8_t tx_buf[2]; @@ -110,8 +110,8 @@ static int idt1337ag_write_reg(const struct device *dev, tx_buf[0] = reg; tx_buf[1] = val; - return i2c_write(config->bus, - tx_buf, sizeof(tx_buf), config->i2c_addr_flags); + return i2c_write(config->bus, tx_buf, sizeof(tx_buf), + config->i2c_addr_flags); } /* @@ -139,7 +139,8 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask) } static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, - uint32_t *value, enum timer_type type) + uint32_t *value, + enum timer_type type) { uint8_t time_reg[NUM_TIMER_REGS]; struct calendar_date time; @@ -152,12 +153,12 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, } if (type == ALARM_TIMER) { - *value = (bcd_to_dec(time_reg[DAYS], DAYS_MASK) * - SECS_PER_DAY) + + *value = + (bcd_to_dec(time_reg[DAYS], DAYS_MASK) * SECS_PER_DAY) + (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + + SECS_PER_HOUR) + (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + + SECS_PER_MINUTE) + bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); } else { time.year = bcd_to_dec(time_reg[YEARS], YEARS_MASK); @@ -165,18 +166,19 @@ static int renesas_rtc_idt1337ag_read_seconds(const struct device *dev, time.day = bcd_to_dec(time_reg[DAYS], DAYS_MASK); *value = date_to_sec(time) - SECS_TILL_YEAR_2K + - (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); + (bcd_to_dec(time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(time_reg[SECONDS], SECONDS_MASK); } return ret; } static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev, - uint32_t value, enum timer_type type) + uint32_t value, + enum timer_type type) { uint8_t time_reg[NUM_TIMER_REGS]; struct calendar_date time; @@ -206,7 +208,7 @@ static int renesas_rtc_idt1337ag_write_seconds(const struct device *dev, } static int renesas_rtc_idt1337ag_configure(const struct device *dev, - cros_rtc_alarm_callback_t callback) + cros_rtc_alarm_callback_t callback) { struct renesas_rtc_idt1337ag_data *data = dev->data; @@ -232,7 +234,8 @@ static int renesas_rtc_idt1337ag_set_value(const struct device *dev, } static int renesas_rtc_idt1337ag_get_alarm(const struct device *dev, - uint32_t *seconds, uint32_t *microseconds) + uint32_t *seconds, + uint32_t *microseconds) { *microseconds = 0; return renesas_rtc_idt1337ag_read_seconds(dev, seconds, ALARM_TIMER); @@ -283,7 +286,8 @@ static int renesas_rtc_idt1337ag_reset_alarm(const struct device *dev) } static int renesas_rtc_idt1337ag_set_alarm(const struct device *dev, - uint32_t seconds, uint32_t microseconds) + uint32_t seconds, + uint32_t microseconds) { int ret; uint8_t val; @@ -429,8 +433,8 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) return ret; } - gpio_init_callback(&data->gpio_cb, - renesas_rtc_idt1337ag_isr, BIT(config->gpio_alert.pin)); + gpio_init_callback(&data->gpio_cb, renesas_rtc_idt1337ag_isr, + BIT(config->gpio_alert.pin)); ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb); @@ -445,8 +449,7 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) GPIO_INT_EDGE_FALLING); } -#define IDT1337AG_INT_PIN \ - DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin) +#define IDT1337AG_INT_PIN DT_PHANDLE(DT_NODELABEL(idt1337ag), int_pin) /* * dt_flags is a uint8_t type. However, for platform/ec @@ -455,12 +458,11 @@ static int renesas_rtc_idt1337ag_init(const struct device *dev) * Cast back to a gpio_dt_flags to compile, discarding the bits * that are not supported by the Zephyr GPIO API. */ -#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ - { \ - .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ - .pin = DT_GPIO_PIN(node_id, prop), \ - .dt_flags = \ - (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ +#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ + { \ + .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ + .pin = DT_GPIO_PIN(node_id, prop), \ + .dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ } static const struct renesas_rtc_idt1337ag_config renesas_rtc_idt1337ag_cfg_0 = { @@ -473,6 +475,6 @@ static struct renesas_rtc_idt1337ag_data renesas_rtc_idt1337ag_data_0; DEVICE_DT_INST_DEFINE(0, renesas_rtc_idt1337ag_init, /* pm_control_fn= */ NULL, &renesas_rtc_idt1337ag_data_0, - &renesas_rtc_idt1337ag_cfg_0, - POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, + &renesas_rtc_idt1337ag_cfg_0, POST_KERNEL, + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &renesas_rtc_idt1337ag_driver_api); -- cgit v1.2.1 From a954df1364f078f26982ff82ece06e6da1a675f2 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Mon, 30 May 2022 07:46:25 +0200 Subject: zephyr: improve tcpc emulator creation Rework the TCPC emulators architecture. A separate general TCPCI emualtor is now not needed for a scific chip emulator. Only one DTS node should be created per the TCPC emulator and the TCPCI_EMUL_DEFINE macro should be used. BUG=b:233645785 TEST=zmake testall BRANCH=main Signed-off-by: Dawid Niedzwiecki Change-Id: I5eba9eeb9bcff5d587f843094e530a13c140cc22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3705480 Commit-Queue: Dawid Niedzwiecki Reviewed-by: Yuval Peress Reviewed-by: Tomasz Michalec --- zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml | 8 +- zephyr/dts/bindings/emul/cros,tcpci-emul.yaml | 16 - .../dts/bindings/emul/cros,tcpci-generic-emul.yaml | 9 + zephyr/dts/bindings/emul/tcpci.yaml | 14 + zephyr/emul/tcpc/CMakeLists.txt | 1 + zephyr/emul/tcpc/Kconfig | 5 +- zephyr/emul/tcpc/emul_ps8xxx.c | 223 +++--- zephyr/emul/tcpc/emul_tcpci.c | 808 ++++++++------------- zephyr/emul/tcpc/emul_tcpci_generic.c | 172 +++++ zephyr/include/emul/tcpc/emul_tcpci.h | 181 ++++- zephyr/test/drivers/overlay.dts | 15 +- zephyr/test/drivers/prj.conf | 1 + .../test/drivers/src/console_cmd/charge_manager.c | 1 + zephyr/test/drivers/src/integration/usbc/usb.c | 2 +- .../src/integration/usbc/usb_attach_src_snk.c | 2 +- zephyr/test/drivers/src/ps8xxx.c | 172 ++--- zephyr/test/drivers/src/stubs.c | 3 +- 17 files changed, 872 insertions(+), 761 deletions(-) delete mode 100644 zephyr/dts/bindings/emul/cros,tcpci-emul.yaml create mode 100644 zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml create mode 100644 zephyr/dts/bindings/emul/tcpci.yaml create mode 100644 zephyr/emul/tcpc/emul_tcpci_generic.c diff --git a/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml index e2d45ca52f..85828b6e37 100644 --- a/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml +++ b/zephyr/dts/bindings/emul/cros,ps8xxx-emul.yaml @@ -6,15 +6,9 @@ description: Zephyr PS8xxx emulator compatible: "cros,ps8xxx-emul" -include: base.yaml +include: tcpci.yaml properties: - tcpci-i2c: - type: phandle - required: true - description: - Base TCPCI emulator. Has to be sibling of PS8xxx emulator. - p0-i2c-addr: type: int required: true diff --git a/zephyr/dts/bindings/emul/cros,tcpci-emul.yaml b/zephyr/dts/bindings/emul/cros,tcpci-emul.yaml deleted file mode 100644 index 3b218acd62..0000000000 --- a/zephyr/dts/bindings/emul/cros,tcpci-emul.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -description: Zephyr TCPCI Emulator - -compatible: "cros,tcpci-emul" - -include: base.yaml - -properties: - alert_gpio: - type: phandle - required: false - description: - Reference to Alert# GPIO. diff --git a/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml new file mode 100644 index 0000000000..8e09020a98 --- /dev/null +++ b/zephyr/dts/bindings/emul/cros,tcpci-generic-emul.yaml @@ -0,0 +1,9 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: Zephyr TCPCI Generic Emulator + +compatible: "cros,tcpci-generic-emul" + +include: tcpci.yaml diff --git a/zephyr/dts/bindings/emul/tcpci.yaml b/zephyr/dts/bindings/emul/tcpci.yaml new file mode 100644 index 0000000000..8d62989fe7 --- /dev/null +++ b/zephyr/dts/bindings/emul/tcpci.yaml @@ -0,0 +1,14 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: Common TCPCI properties + +include: base.yaml + +properties: + alert_gpio: + type: phandle + required: false + description: + Reference to Alert# GPIO. diff --git a/zephyr/emul/tcpc/CMakeLists.txt b/zephyr/emul/tcpc/CMakeLists.txt index c6200bbfc3..00cddd1894 100644 --- a/zephyr/emul/tcpc/CMakeLists.txt +++ b/zephyr/emul/tcpc/CMakeLists.txt @@ -4,6 +4,7 @@ zephyr_library_sources_ifdef(CONFIG_EMUL_PS8XXX emul_ps8xxx.c) zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI emul_tcpci.c) +zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI emul_tcpci_generic.c) zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_COMMON emul_tcpci_partner_common.c) zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_DRP emul_tcpci_partner_drp.c) zephyr_library_sources_ifdef(CONFIG_EMUL_TCPCI_PARTNER_SNK emul_tcpci_partner_snk.c) diff --git a/zephyr/emul/tcpc/Kconfig b/zephyr/emul/tcpc/Kconfig index 127b12e00f..e9ca442532 100644 --- a/zephyr/emul/tcpc/Kconfig +++ b/zephyr/emul/tcpc/Kconfig @@ -2,11 +2,8 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -DT_COMPAT_TCPCI_EMUL := cros,tcpci-emul - menuconfig EMUL_TCPCI - bool "TCPCI emulator" - default $(dt_compat_enabled,$(DT_COMPAT_TCPCI_EMUL)) + bool "TCPCI common functionality" depends on I2C_EMUL help Enable the TCPCI emulator. This driver uses the emulated I2C bus. diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c index 9a509e6afc..5fe8828e31 100644 --- a/zephyr/emul/tcpc/emul_ps8xxx.c +++ b/zephyr/emul/tcpc/emul_ps8xxx.c @@ -12,6 +12,7 @@ LOG_MODULE_REGISTER(ps8xxx_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include #include #include +#include #include "tcpm/tcpci.h" @@ -32,8 +33,6 @@ struct ps8xxx_emul_data { /** Product ID of emulated device */ int prod_id; - /** Pointer to TCPCI emulator that is base for this emulator */ - const struct emul *tcpci_emul; /** Chip revision used by PS8805 */ uint8_t chip_rev; @@ -47,9 +46,6 @@ struct ps8xxx_emul_data { /** Constant configuration of the emulator */ struct ps8xxx_emul_cfg { - /** Phandle (name) of TCPCI emulator that is base for this emulator */ - const char *tcpci_emul; - /** Common I2C configuration used by "hidden" ports */ const struct i2c_common_emul_cfg p0_cfg; const struct i2c_common_emul_cfg p1_cfg; @@ -59,7 +55,8 @@ struct ps8xxx_emul_cfg { /** Check description in emul_ps8xxx.h */ void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; data->chip_rev = chip_rev; } @@ -67,7 +64,8 @@ void ps8xxx_emul_set_chip_rev(const struct emul *emul, uint8_t chip_rev) /** Check description in emul_ps8xxx.h */ void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; data->hw_rev = hw_rev; } @@ -75,7 +73,8 @@ void ps8xxx_emul_set_hw_rev(const struct emul *emul, uint16_t hw_rev) /** Check description in emul_ps8xxx.h */ void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; data->gpio_ctrl = gpio_ctrl; } @@ -83,7 +82,8 @@ void ps8xxx_emul_set_gpio_ctrl(const struct emul *emul, uint8_t gpio_ctrl) /** Check description in emul_ps8xxx.h */ uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; return data->gpio_ctrl; } @@ -91,7 +91,8 @@ uint8_t ps8xxx_emul_get_gpio_ctrl(const struct emul *emul) /** Check description in emul_ps8xxx.h */ uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; return data->dci_cfg; } @@ -99,7 +100,8 @@ uint8_t ps8xxx_emul_get_dci_cfg(const struct emul *emul) /** Check description in emul_ps8xxx.h */ int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; if (product_id != PS8805_PRODUCT_ID && product_id != PS8815_PRODUCT_ID) { @@ -108,7 +110,7 @@ int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id) } data->prod_id = product_id; - tcpci_emul_set_reg(data->tcpci_emul, TCPC_REG_PRODUCT_ID, product_id); + tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, product_id); return 0; } @@ -116,24 +118,19 @@ int ps8xxx_emul_set_product_id(const struct emul *emul, uint16_t product_id) /** Check description in emul_ps8xxx.h */ uint16_t ps8xxx_emul_get_product_id(const struct emul *emul) { - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; return data->prod_id; } -const struct emul *ps8xxx_emul_get_tcpci(const struct emul *emul) -{ - struct ps8xxx_emul_data *data = emul->data; - - return data->tcpci_emul; -} - /** Check description in emul_ps8xxx.h */ struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul, enum ps8xxx_emul_port port) { const struct ps8xxx_emul_cfg *cfg = emul->cfg; - struct ps8xxx_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; switch (port) { case PS8XXX_EMUL_PORT_0: @@ -152,24 +149,25 @@ struct i2c_emul *ps8xxx_emul_get_i2c_emul(const struct emul *emul, } /** - * @brief Function called for each byte of read message + * @brief Function called for each byte of read message from TCPC chip * - * @param emul Pointer to TCPCI emulator - * @param ops Pointer to device operations structure + * @param i2c_emul Pointer to PS8xxx emulator * @param reg First byte of last write message * @param val Pointer where byte to read should be stored - * @param bytes Number of bytes already readded + * @param bytes Number of bytes already read * - * @return TCPCI_EMUL_CONTINUE to continue with default handler - * @return TCPCI_EMUL_DONE to immedietly return success - * @return TCPCI_EMUL_ERROR to immedietly return error + * @return 0 on success + * @return -EIO on invalid read request */ -static enum tcpci_emul_ops_resp -ps8xxx_emul_tcpci_read_byte(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, int reg, - uint8_t *val, int bytes) +static int ps8xxx_emul_tcpc_read_byte(struct i2c_emul *i2c_emul, int reg, + uint8_t *val, int bytes) { uint16_t reg_val; + const struct emul *emul; + + LOG_DBG("PS8XXX TCPC 0x%x: read reg 0x%x", i2c_emul->addr, reg); + + emul = i2c_emul->parent; switch (reg) { case PS8XXX_REG_FW_REV: @@ -182,36 +180,39 @@ ps8xxx_emul_tcpci_read_byte(const struct emul *emul, if (bytes != 0) { LOG_ERR("Reading byte %d from 1 byte register 0x%x", bytes, reg); - return TCPCI_EMUL_ERROR; + return -EIO; } tcpci_emul_get_reg(emul, reg, ®_val); *val = reg_val & 0xff; - return TCPCI_EMUL_DONE; + return 0; default: - return TCPCI_EMUL_CONTINUE; + break; } + + return tcpci_emul_read_byte(emul, reg, val, bytes); } /** - * @brief Function called for each byte of write message + * @brief Function called for each byte of write message to TCPC chip * - * @param emul Pointer to TCPCI emulator - * @param ops Pointer to device operations structure + * @param i2c_emul Pointer to PS8xxx emulator * @param reg First byte of write message * @param val Received byte of write message * @param bytes Number of bytes already received * - * @return TCPCI_EMUL_CONTINUE to continue with default handler - * @return TCPCI_EMUL_DONE to immedietly return success - * @return TCPCI_EMUL_ERROR to immedietly return error + * @return 0 on success + * @return -EIO on invalid write request */ -static enum tcpci_emul_ops_resp -ps8xxx_emul_tcpci_write_byte(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, int reg, - uint8_t val, int bytes) +static int ps8xxx_emul_tcpc_write_byte(struct i2c_emul *i2c_emul, int reg, + uint8_t val, int bytes) { uint16_t prod_id; + const struct emul *emul; + + LOG_DBG("PS8XXX TCPC 0x%x: write reg 0x%x", i2c_emul->addr, reg); + + emul = i2c_emul->parent; tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id); @@ -219,7 +220,7 @@ ps8xxx_emul_tcpci_write_byte(const struct emul *emul, case PS8XXX_REG_RP_DETECT_CONTROL: /* This register is present only on PS8815 */ if (prod_id != PS8815_PRODUCT_ID) { - return TCPCI_EMUL_CONTINUE; + break; } case PS8XXX_REG_I2C_DEBUGGING_ENABLE: case PS8XXX_REG_MUX_IN_HPD_ASSERTION: @@ -230,34 +231,37 @@ ps8xxx_emul_tcpci_write_byte(const struct emul *emul, if (bytes != 1) { LOG_ERR("Writing byte %d to 1 byte register 0x%x", bytes, reg); - return TCPCI_EMUL_ERROR; + return -EIO; } tcpci_emul_set_reg(emul, reg, val); - return TCPCI_EMUL_DONE; + return 0; default: - return TCPCI_EMUL_CONTINUE; + break; } + + return tcpci_emul_write_byte(emul, reg, val, bytes); } /** - * @brief Function called on the end of write message + * @brief Function called on the end of write message to TCPC chip * - * @param emul Pointer to TCPCI emulator - * @param ops Pointer to device operations structure + * @param i2c_emul Pointer to PS8xxx emulator * @param reg Register which is written * @param msg_len Length of handled I2C message * - * @return TCPCI_EMUL_CONTINUE to continue with default handler - * @return TCPCI_EMUL_DONE to immedietly return success - * @return TCPCI_EMUL_ERROR to immedietly return error + * @return 0 on success + * @return -EIO on error */ -static enum tcpci_emul_ops_resp -ps8xxx_emul_tcpci_handle_write(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, int reg, - int msg_len) +static int ps8xxx_emul_tcpc_finish_write(struct i2c_emul *i2c_emul, int reg, + int msg_len) { uint16_t prod_id; + const struct emul *emul; + + LOG_DBG("PS8XXX TCPC 0x%x: finish write reg 0x%x", i2c_emul->addr, reg); + + emul = i2c_emul->parent; tcpci_emul_get_reg(emul, TCPC_REG_PRODUCT_ID, &prod_id); @@ -265,7 +269,7 @@ ps8xxx_emul_tcpci_handle_write(const struct emul *emul, case PS8XXX_REG_RP_DETECT_CONTROL: /* This register is present only on PS8815 */ if (prod_id != PS8815_PRODUCT_ID) { - return TCPCI_EMUL_CONTINUE; + break; } case PS8XXX_REG_I2C_DEBUGGING_ENABLE: case PS8XXX_REG_MUX_IN_HPD_ASSERTION: @@ -273,20 +277,37 @@ ps8xxx_emul_tcpci_handle_write(const struct emul *emul, case PS8XXX_REG_BIST_CONT_MODE_BYTE1: case PS8XXX_REG_BIST_CONT_MODE_BYTE2: case PS8XXX_REG_BIST_CONT_MODE_CTR: - return TCPCI_EMUL_DONE; + return 0; default: - return TCPCI_EMUL_CONTINUE; + break; } + + return tcpci_emul_handle_write(emul, reg, msg_len); +} + +/** + * @brief Get currently accessed register, which always equals to selected + * register from TCPC chip. + * + * @param i2c_emul Pointer to TCPCI emulator + * @param reg First byte of last write message + * @param bytes Number of bytes already handled from current message + * @param read If currently handled is read message + * + * @return Currently accessed register + */ +static int ps8xxx_emul_tcpc_access_reg(struct i2c_emul *i2c_emul, int reg, + int bytes, bool read) +{ + return reg; } /** * @brief Function called on reset * - * @param emul Pointer to TCPCI emulator - * @param ops Pointer to device operations structure + * @param emul Pointer to PS8xxx emulator */ -static void ps8xxx_emul_tcpci_reset(const struct emul *emul, - struct tcpci_emul_dev_ops *ops) +static int ps8xxx_emul_tcpc_reset(const struct emul *emul) { tcpci_emul_set_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, 0x31); tcpci_emul_set_reg(emul, PS8XXX_REG_MUX_IN_HPD_ASSERTION, 0x00); @@ -294,15 +315,9 @@ static void ps8xxx_emul_tcpci_reset(const struct emul *emul, tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE1, 0x0f); tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_BYTE2, 0x00); tcpci_emul_set_reg(emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0x00); -} -/** TCPCI PS8xxx operations */ -static struct tcpci_emul_dev_ops ps8xxx_emul_ops = { - .read_byte = ps8xxx_emul_tcpci_read_byte, - .write_byte = ps8xxx_emul_tcpci_write_byte, - .handle_write = ps8xxx_emul_tcpci_handle_write, - .reset = ps8xxx_emul_tcpci_reset, -}; + return tcpci_emul_reset(emul); +} /** * @brief Get port associated with given "hidden" I2C device @@ -340,7 +355,7 @@ static enum ps8xxx_emul_port ps8xxx_emul_get_port(struct i2c_emul *i2c_emul) * @param i2c_emul Pointer to PS8xxx emulator * @param reg First byte of last write message * @param val Pointer where byte to read should be stored - * @param bytes Number of bytes already readded + * @param bytes Number of bytes already read * * @return 0 on success * @return -EIO on invalid read request @@ -348,16 +363,19 @@ static enum ps8xxx_emul_port ps8xxx_emul_get_port(struct i2c_emul *i2c_emul) static int ps8xxx_emul_read_byte(struct i2c_emul *i2c_emul, int reg, uint8_t *val, int bytes) { + struct tcpc_emul_data *tcpc_data; struct ps8xxx_emul_data *data; enum ps8xxx_emul_port port; const struct emul *emul; uint16_t i2c_dbg_reg; + LOG_DBG("PS8XXX 0x%x: read reg 0x%x", i2c_emul->addr, reg); + emul = i2c_emul->parent; - data = emul->data; + tcpc_data = emul->data; + data = tcpc_data->chip_data; - tcpci_emul_get_reg(data->tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, - &i2c_dbg_reg); + tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg); /* There is no need to enable I2C debug on PS8815 */ if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) { LOG_ERR("Accessing hidden i2c address without enabling debug"); @@ -427,15 +445,18 @@ static int ps8xxx_emul_write_byte(struct i2c_emul *i2c_emul, int reg, uint8_t val, int bytes) { struct ps8xxx_emul_data *data; + struct tcpc_emul_data *tcpc_data; enum ps8xxx_emul_port port; const struct emul *emul; uint16_t i2c_dbg_reg; + LOG_DBG("PS8XXX 0x%x: write reg 0x%x", i2c_emul->addr, reg); + emul = i2c_emul->parent; - data = emul->data; + tcpc_data = emul->data; + data = tcpc_data->chip_data; - tcpci_emul_get_reg(data->tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, - &i2c_dbg_reg); + tcpci_emul_get_reg(emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, &i2c_dbg_reg); /* There is no need to enable I2C debug on PS8815 */ if (data->prod_id != PS8815_PRODUCT_ID && i2c_dbg_reg & 0x1) { LOG_ERR("Accessing hidden i2c address without enabling debug"); @@ -488,14 +509,22 @@ static int ps8xxx_emul_write_byte(struct i2c_emul *i2c_emul, int reg, static int ps8xxx_emul_init(const struct emul *emul, const struct device *parent) { + struct tcpc_emul_data *tcpc_data = emul->data; + struct ps8xxx_emul_data *data = tcpc_data->chip_data; + struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx; const struct ps8xxx_emul_cfg *cfg = emul->cfg; - struct ps8xxx_emul_data *data = emul->data; const struct device *i2c_dev; int ret; - data->tcpci_emul = emul_get_binding(cfg->tcpci_emul); i2c_dev = parent; + tcpci_ctx->common.write_byte = ps8xxx_emul_tcpc_write_byte; + tcpci_ctx->common.finish_write = ps8xxx_emul_tcpc_finish_write; + tcpci_ctx->common.read_byte = ps8xxx_emul_tcpc_read_byte; + tcpci_ctx->common.access_reg = ps8xxx_emul_tcpc_access_reg; + + tcpci_emul_i2c_init(emul, i2c_dev); + data->p0_data.emul.api = &i2c_common_emul_api; data->p0_data.emul.addr = cfg->p0_cfg.addr; data->p0_data.emul.parent = emul; @@ -510,7 +539,9 @@ static int ps8xxx_emul_init(const struct emul *emul, data->p1_data.cfg = &cfg->p1_cfg; i2c_common_emul_init(&data->p1_data); - ret = i2c_emul_register(i2c_dev, emul->dev_label, &data->p0_data.emul); + ret = i2c_emul_register(i2c_dev, emul->dev_label, + &tcpci_ctx->common.emul); + ret |= i2c_emul_register(i2c_dev, emul->dev_label, &data->p0_data.emul); ret |= i2c_emul_register(i2c_dev, emul->dev_label, &data->p1_data.emul); if (cfg->gpio_cfg.addr != 0) { @@ -524,18 +555,16 @@ static int ps8xxx_emul_init(const struct emul *emul, &data->gpio_data.emul); } - tcpci_emul_set_dev_ops(data->tcpci_emul, &ps8xxx_emul_ops); - ps8xxx_emul_tcpci_reset(data->tcpci_emul, &ps8xxx_emul_ops); + ret |= ps8xxx_emul_tcpc_reset(emul); - tcpci_emul_set_reg(data->tcpci_emul, TCPC_REG_PRODUCT_ID, - data->prod_id); + tcpci_emul_set_reg(emul, TCPC_REG_PRODUCT_ID, data->prod_id); /* FW rev is never 0 in a working device. Set arbitrary FW rev. */ - tcpci_emul_set_reg(data->tcpci_emul, PS8XXX_REG_FW_REV, 0x31); + tcpci_emul_set_reg(emul, PS8XXX_REG_FW_REV, 0x31); return ret; } -#define PS8XXX_EMUL(n) \ +#define PS8XXX_EMUL(n) \ static struct ps8xxx_emul_data ps8xxx_emul_data_##n = { \ .prod_id = PS8805_PRODUCT_ID, \ .p0_data = { \ @@ -553,7 +582,6 @@ static int ps8xxx_emul_init(const struct emul *emul, }; \ \ static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = { \ - .tcpci_emul = DT_LABEL(DT_INST_PHANDLE(n, tcpci_i2c)), \ .p0_cfg = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ @@ -573,15 +601,14 @@ static int ps8xxx_emul_init(const struct emul *emul, .addr = DT_INST_PROP(n, gpio_i2c_addr), \ }, \ }; \ - EMUL_DEFINE(ps8xxx_emul_init, DT_DRV_INST(n), &ps8xxx_emul_cfg_##n, \ - &ps8xxx_emul_data_##n) + TCPCI_EMUL_DEFINE(n, ps8xxx_emul_init, &ps8xxx_emul_cfg_##n, \ + &ps8xxx_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL) -#ifdef CONFIG_ZMAKE_NEW_API - +#ifdef CONFIG_ZTEST_NEW_API #define PS8XXX_EMUL_RESET_RULE_BEFORE(n) \ - ps8xxx_emul_tcpci_reset(&ps8xxx_emul_data_##n, &ps8xxx_emul_ops); + ps8xxx_emul_tcpc_reset(&EMUL_REG_NAME(DT_DRV_INST(n))); static void ps8xxx_emul_reset_rule_before(const struct ztest_unit_test *test, void *data) { @@ -589,5 +616,5 @@ static void ps8xxx_emul_reset_rule_before(const struct ztest_unit_test *test, ARG_UNUSED(data); DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL_RESET_RULE_BEFORE); } -ZTEST_RULE(ps8xxx_emul_reset, ps8xxx_emul_reset_rule_before, NULL); -#endif /* CONFIG_ZMAKE_NEW_API */ +ZTEST_RULE(PS8XXX_emul_reset, ps8xxx_emul_reset_rule_before, NULL); +#endif /* CONFIG_ZTEST_NEW_API */ diff --git a/zephyr/emul/tcpc/emul_tcpci.c b/zephyr/emul/tcpc/emul_tcpci.c index ac547be3c3..5f1ac5e502 100644 --- a/zephyr/emul/tcpc/emul_tcpci.c +++ b/zephyr/emul/tcpc/emul_tcpci.c @@ -3,8 +3,6 @@ * found in the LICENSE file. */ -#define DT_DRV_COMPAT cros_tcpci_emul - #include LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); @@ -13,6 +11,7 @@ LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include #include #include +#include #include #include "tcpm/tcpci.h" @@ -20,52 +19,6 @@ LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include "emul/emul_common_i2c.h" #include "emul/tcpc/emul_tcpci.h" -#define TCPCI_DATA_FROM_I2C_EMUL(_emul) \ - CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ - struct tcpci_emul_data, common) - -/** - * Number of emulated register. This include vendor registers defined in TCPCI - * specification - */ -#define TCPCI_EMUL_REG_COUNT 0x100 - - -/** Run-time data used by the emulator */ -struct tcpci_emul_data { - /** Common I2C data */ - struct i2c_common_emul_data common; - - /** Current state of all emulated TCPCI registers */ - uint8_t reg[TCPCI_EMUL_REG_COUNT]; - - /** Structures representing TX and RX buffers */ - struct tcpci_emul_msg *rx_msg; - struct tcpci_emul_msg *tx_msg; - - /** Data that should be written to register (except TX_BUFFER) */ - uint16_t write_data; - - /** Return error when trying to write to RO register */ - bool error_on_ro_write; - /** Return error when trying to write 1 to reserved bit */ - bool error_on_rsvd_write; - - /** User function called when alert line could change */ - tcpci_emul_alert_state_func alert_callback; - /** Data passed to alert_callback */ - void *alert_callback_data; - - /** Callbacks for specific TCPCI device emulator */ - struct tcpci_emul_dev_ops *dev_ops; - /** Callbacks for TCPCI partner */ - const struct tcpci_emul_partner_ops *partner; - - /** Reference to Alert# GPIO emulator. */ - const struct device *alert_gpio_port; - gpio_pin_t alert_gpio_pin; -}; - /** * @brief Returns number of bytes in specific register * @@ -101,10 +54,58 @@ static int tcpci_emul_reg_bytes(int reg) return 1; } +/** + * @brief Get value of given register of TCPCI + * + * @param ctx Pointer to TCPCI context + * @param reg Register address + * @param val Pointer where value should be stored + * + * @return 0 on success + * @return -EINVAL when register is out of range defined in TCPCI specification + * or val is NULL + */ +static int get_reg(const struct tcpci_ctx *ctx, int reg, uint16_t *val) +{ + int byte; + + if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT || val == NULL) { + return -EINVAL; + } + + *val = 0; + + byte = tcpci_emul_reg_bytes(reg); + if (byte == 2) { + *val = sys_get_le16(&ctx->reg[reg]); + } else { + *val = ctx->reg[reg]; + } + + return 0; +} + /** Check description in emul_tcpci.h */ -int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val) +int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val) +{ + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; + + return get_reg(ctx, reg, val); +} + +/** + * @brief Set value of given register of TCPCI + * + * @param ctx Pointer to TCPCI context + * @param reg Register address which value will be changed + * @param val New value of the register + * + * @return 0 on success + * @return -EINVAL when register is out of range defined in TCPCI specification + */ +static int set_reg(struct tcpci_ctx *ctx, int reg, uint16_t val) { - struct tcpci_emul_data *data = emul->data; uint16_t update_alert = 0; uint16_t alert; int byte; @@ -130,82 +131,70 @@ int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val) } if (update_alert != 0) { - tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert); - tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert | update_alert); + get_reg(ctx, TCPC_REG_ALERT, &alert); + set_reg(ctx, TCPC_REG_ALERT, alert | update_alert); } - for (byte = tcpci_emul_reg_bytes(reg); byte > 0; byte--) { - data->reg[reg] = val & 0xff; - val >>= 8; - reg++; + byte = tcpci_emul_reg_bytes(reg); + if (byte == 2) { + sys_put_le16(val, &ctx->reg[reg]); + } else { + ctx->reg[reg] = val; } return 0; } /** Check description in emul_tcpci.h */ -int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val) +int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val) { - struct tcpci_emul_data *data = emul->data; - int byte; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - if (reg < 0 || reg > TCPCI_EMUL_REG_COUNT || val == NULL) { - return -EINVAL; - } - - *val = 0; - - byte = tcpci_emul_reg_bytes(reg); - for (byte -= 1; byte >= 0; byte--) { - *val <<= 8; - *val |= data->reg[reg + byte]; - } - - return 0; + return set_reg(ctx, reg, val); } /** * @brief Check if alert line should be active based on alert registers and * masks * - * @param emul Pointer to TCPCI emulator + * @param ctx Pointer to TCPCI context * * @return State of alert line */ -static bool tcpci_emul_check_int(const struct emul *emul) +static bool tcpci_emul_check_int(const struct tcpci_ctx *ctx) { - struct tcpci_emul_data *data = emul->data; uint16_t alert_mask; uint16_t alert; - tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert); - tcpci_emul_get_reg(emul, TCPC_REG_ALERT_MASK, &alert_mask); + get_reg(ctx, TCPC_REG_ALERT, &alert); + get_reg(ctx, TCPC_REG_ALERT_MASK, &alert_mask); /* * For nested interrupts alert group bit and alert register bit has to * be unmasked */ if (alert & alert_mask & TCPC_REG_ALERT_ALERT_EXT && - data->reg[TCPC_REG_ALERT_EXT] & - data->reg[TCPC_REG_ALERT_EXTENDED_MASK]) { + ctx->reg[TCPC_REG_ALERT_EXT] & + ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK]) { return true; } if (alert & alert_mask & TCPC_REG_ALERT_EXT_STATUS && - data->reg[TCPC_REG_EXT_STATUS] & - data->reg[TCPC_REG_EXT_STATUS_MASK]) { + ctx->reg[TCPC_REG_EXT_STATUS] & + ctx->reg[TCPC_REG_EXT_STATUS_MASK]) { return true; } if (alert & alert_mask & TCPC_REG_ALERT_FAULT && - data->reg[TCPC_REG_FAULT_STATUS] & - data->reg[TCPC_REG_FAULT_STATUS_MASK]) { + ctx->reg[TCPC_REG_FAULT_STATUS] & + ctx->reg[TCPC_REG_FAULT_STATUS_MASK]) { return true; } if (alert & alert_mask & TCPC_REG_ALERT_POWER_STATUS && - data->reg[TCPC_REG_POWER_STATUS] & - data->reg[TCPC_REG_POWER_STATUS_MASK]) { + ctx->reg[TCPC_REG_POWER_STATUS] & + ctx->reg[TCPC_REG_POWER_STATUS_MASK]) { return true; } @@ -222,34 +211,34 @@ static bool tcpci_emul_check_int(const struct emul *emul) /** * @brief If alert callback is provided, call it with current alert line state * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return 0 for success, or non-0 for errors. */ static int tcpci_emul_alert_changed(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; int rc; - bool alert_is_active = tcpci_emul_check_int(emul); + bool alert_is_active = tcpci_emul_check_int(ctx); /** Trigger GPIO. */ - if (data->alert_gpio_port != NULL) { + if (ctx->alert_gpio_port != NULL) { /* Triggers on edge falling, so set to 0 when there is an alert. */ - rc = gpio_emul_input_set(data->alert_gpio_port, - data->alert_gpio_pin, + rc = gpio_emul_input_set(ctx->alert_gpio_port, + ctx->alert_gpio_pin, alert_is_active ? 0 : 1); if (rc != 0) return rc; } /* Nothing to do */ - if (data->alert_callback == NULL) { + if (ctx->alert_callback == NULL) { return 0; } - data->alert_callback(emul, alert_is_active, - data->alert_callback_data); + ctx->alert_callback(emul, alert_is_active, ctx->alert_callback_data); return 0; } @@ -257,31 +246,32 @@ static int tcpci_emul_alert_changed(const struct emul *emul) * @brief Load next rx message and inform partner which message was consumed * by TCPC * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return 0 when there is no new message to load * @return 1 when new rx message is loaded */ static int tcpci_emul_get_next_rx_msg(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; struct tcpci_emul_msg *consumed_msg; - if (data->rx_msg == NULL) { + if (ctx->rx_msg == NULL) { return 0; } - consumed_msg = data->rx_msg; - data->rx_msg = consumed_msg->next; + consumed_msg = ctx->rx_msg; + ctx->rx_msg = consumed_msg->next; /* Inform partner */ - if (data->partner && data->partner->rx_consumed) { - data->partner->rx_consumed(emul, data->partner, consumed_msg); + if (ctx->partner && ctx->partner->rx_consumed) { + ctx->partner->rx_consumed(emul, ctx->partner, consumed_msg); } /* Prepare new loaded message */ - if (data->rx_msg) { - data->rx_msg->idx = 0; + if (ctx->rx_msg) { + ctx->rx_msg->idx = 0; return 1; } @@ -293,17 +283,15 @@ static int tcpci_emul_get_next_rx_msg(const struct emul *emul) * @brief Reset mask registers that are reset upon receiving or transmitting * Hard Reset message. * - * @param emul Pointer to TCPCI emulator + * @param ctx Pointer to TCPCI context */ -static void tcpci_emul_reset_mask_regs(const struct emul *emul) +static void tcpci_emul_reset_mask_regs(struct tcpci_ctx *ctx) { - struct tcpci_emul_data *data = emul->data; - - data->reg[TCPC_REG_ALERT_MASK] = 0xff; - data->reg[TCPC_REG_ALERT_MASK + 1] = 0x7f; - data->reg[TCPC_REG_POWER_STATUS_MASK] = 0xff; - data->reg[TCPC_REG_EXT_STATUS_MASK] = 0x01; - data->reg[TCPC_REG_ALERT_EXTENDED_MASK] = 0x07; + ctx->reg[TCPC_REG_ALERT_MASK] = 0xff; + ctx->reg[TCPC_REG_ALERT_MASK + 1] = 0x7f; + ctx->reg[TCPC_REG_POWER_STATUS_MASK] = 0xff; + ctx->reg[TCPC_REG_EXT_STATUS_MASK] = 0x01; + ctx->reg[TCPC_REG_ALERT_EXTENDED_MASK] = 0x07; } /** @@ -311,11 +299,14 @@ static void tcpci_emul_reset_mask_regs(const struct emul *emul) * delivery (clear RECEIVE_DETECT register and clear already received * messages in buffer) * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator */ static void tcpci_emul_disable_pd_msg_delivery(const struct emul *emul) { - tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT, 0); + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; + + set_reg(ctx, TCPC_REG_RX_DETECT, 0); /* Clear received messages */ while (tcpci_emul_get_next_rx_msg(emul)) ; @@ -325,7 +316,8 @@ static void tcpci_emul_disable_pd_msg_delivery(const struct emul *emul) int tcpci_emul_add_rx_msg(const struct emul *emul, struct tcpci_emul_msg *rx_msg, bool alert) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t rx_detect_mask; uint16_t rx_detect; uint16_t dev_cap_2; @@ -333,7 +325,7 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, int rc; /* Acquire lock to prevent race conditions with TCPM accessing I2C */ - rc = i2c_common_emul_lock_data(&data->common.emul, K_FOREVER); + rc = i2c_common_emul_lock_data(&ctx->common.emul, K_FOREVER); if (rc != 0) { LOG_ERR("Failed to acquire TCPCI lock"); return rc; @@ -362,32 +354,32 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, rx_detect_mask = TCPC_REG_RX_DETECT_CABLE_RST; break; default: - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return -EINVAL; } - tcpci_emul_get_reg(emul, TCPC_REG_RX_DETECT, &rx_detect); + get_reg(ctx, TCPC_REG_RX_DETECT, &rx_detect); if (!(rx_detect & rx_detect_mask)) { /* * TCPCI will not respond with GoodCRC, so from partner emulator * point of view it failed to send message */ - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return TCPCI_EMUL_TX_FAILED; } - tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert_reg); + get_reg(ctx, TCPC_REG_ALERT, &alert_reg); /* Handle HardReset */ if (rx_msg->type == TCPCI_MSG_TX_HARD_RESET) { tcpci_emul_disable_pd_msg_delivery(emul); - tcpci_emul_reset_mask_regs(emul); + tcpci_emul_reset_mask_regs(ctx); alert_reg |= TCPC_REG_ALERT_RX_HARD_RST; - tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert_reg); + set_reg(ctx, TCPC_REG_ALERT, alert_reg); rc = tcpci_emul_alert_changed(emul); - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return rc; } @@ -397,30 +389,30 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, /* Rest of CableReset handling is the same as SOP* message */ } - if (data->rx_msg == NULL) { - tcpci_emul_get_reg(emul, TCPC_REG_DEV_CAP_2, &dev_cap_2); + if (ctx->rx_msg == NULL) { + get_reg(ctx, TCPC_REG_DEV_CAP_2, &dev_cap_2); if ((!(dev_cap_2 & TCPC_REG_DEV_CAP_2_LONG_MSG) && rx_msg->cnt > 31) || rx_msg->cnt > 265) { LOG_ERR("Too long first message (%d)", rx_msg->cnt); - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return -EINVAL; } - data->rx_msg = rx_msg; - } else if (data->rx_msg->next == NULL) { + ctx->rx_msg = rx_msg; + } else if (ctx->rx_msg->next == NULL) { if (rx_msg->cnt > 31) { LOG_ERR("Too long second message (%d)", rx_msg->cnt); - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return -EINVAL; } - data->rx_msg->next = rx_msg; + ctx->rx_msg->next = rx_msg; if (alert) { alert_reg |= TCPC_REG_ALERT_RX_BUF_OVF; } } else { LOG_ERR("Cannot setup third message"); - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return -EINVAL; } @@ -430,11 +422,11 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, } alert_reg |= TCPC_REG_ALERT_RX_STATUS; - tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert_reg); + set_reg(ctx, TCPC_REG_ALERT, alert_reg); rc = tcpci_emul_alert_changed(emul); if (rc != 0) { - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return rc; } } @@ -442,16 +434,17 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, rx_msg->next = NULL; rx_msg->idx = 0; - i2c_common_emul_unlock_data(&data->common.emul); + i2c_common_emul_unlock_data(&ctx->common.emul); return TCPCI_EMUL_TX_SUCCESS; } /** Check description in emul_tcpci.h */ struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - return data->tx_msg; + return ctx->tx_msg; } /** Check description in emul_tcpci.h */ @@ -471,33 +464,26 @@ void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev) } } -/** Check description in emul_tcpci.h */ -void tcpci_emul_set_dev_ops(const struct emul *emul, - struct tcpci_emul_dev_ops *dev_ops) -{ - struct tcpci_emul_data *data = emul->data; - - data->dev_ops = dev_ops; -} - /** Check description in emul_tcpci.h */ void tcpci_emul_set_alert_callback(const struct emul *emul, tcpci_emul_alert_state_func alert_callback, void *alert_callback_data) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - data->alert_callback = alert_callback; - data->alert_callback_data = alert_callback_data; + ctx->alert_callback = alert_callback; + ctx->alert_callback_data = alert_callback_data; } /** Check description in emul_tcpci.h */ void tcpci_emul_set_partner_ops(const struct emul *emul, const struct tcpci_emul_partner_ops *partner) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - data->partner = partner; + ctx->partner = partner; } /** @@ -545,6 +531,8 @@ int tcpci_emul_connect_partner(const struct emul *emul, enum tcpc_cc_voltage_status partner_cc2, enum tcpc_cc_polarity polarity) { + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t cc_status, alert, role_ctrl, power_status; enum tcpc_cc_voltage_status cc1_v, cc2_v; enum tcpc_cc_pull cc1_r, cc2_r; @@ -557,7 +545,7 @@ int tcpci_emul_connect_partner(const struct emul *emul, cc2_v = partner_cc1; } - tcpci_emul_get_reg(emul, TCPC_REG_CC_STATUS, &cc_status); + get_reg(ctx, TCPC_REG_CC_STATUS, &cc_status); if (TCPC_REG_CC_STATUS_LOOK4CONNECTION(cc_status)) { /* Change resistors values in case of DRP toggling */ if (partner_power_role == PD_ROLE_SOURCE) { @@ -571,7 +559,7 @@ int tcpci_emul_connect_partner(const struct emul *emul, } } else { /* Use role control resistors values otherwise */ - tcpci_emul_get_reg(emul, TCPC_REG_ROLE_CTRL, &role_ctrl); + get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl); cc1_r = TCPC_REG_ROLE_CTRL_CC1(role_ctrl); cc2_r = TCPC_REG_ROLE_CTRL_CC2(role_ctrl); } @@ -583,21 +571,19 @@ int tcpci_emul_connect_partner(const struct emul *emul, cc_status = TCPC_REG_CC_STATUS_SET( partner_power_role == PD_ROLE_SOURCE ? 1 : 0, cc2_v, cc1_v); - tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, cc_status); - tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert); - tcpci_emul_set_reg(emul, TCPC_REG_ALERT, - alert | TCPC_REG_ALERT_CC_STATUS); + set_reg(ctx, TCPC_REG_CC_STATUS, cc_status); + get_reg(ctx, TCPC_REG_ALERT, &alert); + set_reg(ctx, TCPC_REG_ALERT, alert | TCPC_REG_ALERT_CC_STATUS); if (partner_power_role == PD_ROLE_SOURCE) { - tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS, &power_status); + get_reg(ctx, TCPC_REG_POWER_STATUS, &power_status); if (power_status & TCPC_REG_POWER_STATUS_VBUS_DET) { /* * Set TCPCI emulator VBUS to present (connected, * above 4V) only if VBUS detection is enabled */ - tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, - TCPC_REG_POWER_STATUS_VBUS_PRES | - power_status); + set_reg(ctx, TCPC_REG_POWER_STATUS, + TCPC_REG_POWER_STATUS_VBUS_PRES | power_status); } } @@ -609,32 +595,33 @@ int tcpci_emul_connect_partner(const struct emul *emul, /** Check description in emul_tcpci.h */ int tcpci_emul_disconnect_partner(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t power_status; uint16_t val; uint16_t term; int rc; tcpci_emul_disable_pd_msg_delivery(emul); - if (data->partner && data->partner->disconnect) { - data->partner->disconnect(emul, data->partner); + if (ctx->partner && ctx->partner->disconnect) { + ctx->partner->disconnect(emul, ctx->partner); } - data->partner = NULL; + ctx->partner = NULL; /* Set both CC lines to open to indicate disconnect. */ - rc = tcpci_emul_get_reg(emul, TCPC_REG_CC_STATUS, &val); + rc = get_reg(ctx, TCPC_REG_CC_STATUS, &val); if (rc != 0) return rc; term = TCPC_REG_CC_STATUS_TERM(val); - rc = tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, - TCPC_REG_CC_STATUS_SET(term, TYPEC_CC_VOLT_OPEN, - TYPEC_CC_VOLT_OPEN)); + rc = set_reg(ctx, TCPC_REG_CC_STATUS, + TCPC_REG_CC_STATUS_SET(term, TYPEC_CC_VOLT_OPEN, + TYPEC_CC_VOLT_OPEN)); if (rc != 0) return rc; - data->reg[TCPC_REG_ALERT] |= TCPC_REG_ALERT_CC_STATUS; + ctx->reg[TCPC_REG_ALERT] |= TCPC_REG_ALERT_CC_STATUS; rc = tcpci_emul_alert_changed(emul); if (rc != 0) return rc; @@ -644,10 +631,10 @@ int tcpci_emul_disconnect_partner(const struct emul *emul) */ /* Clear VBUS present in case if source partner is disconnected */ - tcpci_emul_get_reg(emul, TCPC_REG_POWER_STATUS, &power_status); + get_reg(ctx, TCPC_REG_POWER_STATUS, &power_status); if (power_status & TCPC_REG_POWER_STATUS_VBUS_PRES) { power_status &= ~TCPC_REG_POWER_STATUS_VBUS_PRES; - tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, power_status); + set_reg(ctx, TCPC_REG_POWER_STATUS, power_status); } return 0; @@ -657,6 +644,8 @@ int tcpci_emul_disconnect_partner(const struct emul *emul) void tcpci_emul_partner_msg_status(const struct emul *emul, enum tcpci_emul_tx_status status) { + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t alert; uint16_t tx_status_alert; @@ -679,8 +668,8 @@ void tcpci_emul_partner_msg_status(const struct emul *emul, return; } - tcpci_emul_get_reg(emul, TCPC_REG_ALERT, &alert); - tcpci_emul_set_reg(emul, TCPC_REG_ALERT, alert | tx_status_alert); + get_reg(ctx, TCPC_REG_ALERT, &alert); + set_reg(ctx, TCPC_REG_ALERT, alert | tx_status_alert); tcpci_emul_alert_changed(emul); } @@ -749,40 +738,38 @@ static const uint8_t tcpci_emul_rsvd_mask[] = { [0x80 ... TCPCI_EMUL_REG_COUNT - 1] = 0x00, }; - /** * @brief Reset role control and header info registers to default values. * - * @param emul Pointer to TCPCI emulator + * @param ctx Pointer to TCPCI context */ -static void tcpci_emul_reset_role_ctrl(const struct emul *emul) +static void tcpci_emul_reset_role_ctrl(struct tcpci_ctx *ctx) { - struct tcpci_emul_data *data = emul->data; uint16_t dev_cap_1; - tcpci_emul_get_reg(emul, TCPC_REG_DEV_CAP_1, &dev_cap_1); + get_reg(ctx, TCPC_REG_DEV_CAP_1, &dev_cap_1); switch (dev_cap_1 & TCPC_REG_DEV_CAP_1_PWRROLE_MASK) { case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK: case TCPC_REG_DEV_CAP_1_PWRROLE_SNK: case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC: - data->reg[TCPC_REG_ROLE_CTRL] = 0x0a; - data->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; + ctx->reg[TCPC_REG_ROLE_CTRL] = 0x0a; + ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; break; case TCPC_REG_DEV_CAP_1_PWRROLE_SRC: /* Dead batter */ - data->reg[TCPC_REG_ROLE_CTRL] = 0x05; - data->reg[TCPC_REG_MSG_HDR_INFO] = 0x0d; + ctx->reg[TCPC_REG_ROLE_CTRL] = 0x05; + ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x0d; break; case TCPC_REG_DEV_CAP_1_PWRROLE_DRP: /* Dead batter and dbg acc ind */ - data->reg[TCPC_REG_ROLE_CTRL] = 0x4a; - data->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; + ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a; + ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; break; case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL: case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP: /* Dead batter and dbg acc ind */ - data->reg[TCPC_REG_ROLE_CTRL] = 0x4a; - data->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; + ctx->reg[TCPC_REG_ROLE_CTRL] = 0x4a; + ctx->reg[TCPC_REG_MSG_HDR_INFO] = 0x04; break; } } @@ -794,46 +781,43 @@ static void tcpci_emul_reset_role_ctrl(const struct emul *emul) * @param emul Pointer to TCPCI emulator * @return 0 if successful */ -static int tcpci_emul_reset(const struct emul *emul) +int tcpci_emul_reset(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; - - data->reg[TCPC_REG_ALERT] = 0x00; - data->reg[TCPC_REG_ALERT + 1] = 0x00; - data->reg[TCPC_REG_FAULT_STATUS_MASK] = 0xff; - data->reg[TCPC_REG_CONFIG_STD_OUTPUT] = 0x60; - data->reg[TCPC_REG_TCPC_CTRL] = 0x00; - data->reg[TCPC_REG_FAULT_CTRL] = 0x00; - data->reg[TCPC_REG_POWER_CTRL] = 0x60; - data->reg[TCPC_REG_CC_STATUS] = 0x00; - data->reg[TCPC_REG_POWER_STATUS] = 0x08; - data->reg[TCPC_REG_FAULT_STATUS] = 0x80; - data->reg[TCPC_REG_EXT_STATUS] = 0x00; - data->reg[TCPC_REG_ALERT_EXT] = 0x00; - data->reg[TCPC_REG_COMMAND] = 0x00; - data->reg[TCPC_REG_CONFIG_EXT_1] = 0x00; - data->reg[TCPC_REG_GENERIC_TIMER] = 0x00; - data->reg[TCPC_REG_GENERIC_TIMER + 1] = 0x00; - data->reg[TCPC_REG_RX_DETECT] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00; - data->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x8c; - data->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0x00; - data->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x20; - data->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00; - data->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0x00; - data->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00; - data->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00; - - tcpci_emul_reset_mask_regs(emul); - tcpci_emul_reset_role_ctrl(emul); - - if (data->dev_ops && data->dev_ops->reset) { - data->dev_ops->reset(emul, data->dev_ops); - } + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; + + ctx->reg[TCPC_REG_ALERT] = 0x00; + ctx->reg[TCPC_REG_ALERT + 1] = 0x00; + ctx->reg[TCPC_REG_FAULT_STATUS_MASK] = 0xff; + ctx->reg[TCPC_REG_CONFIG_STD_OUTPUT] = 0x60; + ctx->reg[TCPC_REG_TCPC_CTRL] = 0x00; + ctx->reg[TCPC_REG_FAULT_CTRL] = 0x00; + ctx->reg[TCPC_REG_POWER_CTRL] = 0x60; + ctx->reg[TCPC_REG_CC_STATUS] = 0x00; + ctx->reg[TCPC_REG_POWER_STATUS] = 0x08; + ctx->reg[TCPC_REG_FAULT_STATUS] = 0x80; + ctx->reg[TCPC_REG_EXT_STATUS] = 0x00; + ctx->reg[TCPC_REG_ALERT_EXT] = 0x00; + ctx->reg[TCPC_REG_COMMAND] = 0x00; + ctx->reg[TCPC_REG_CONFIG_EXT_1] = 0x00; + ctx->reg[TCPC_REG_GENERIC_TIMER] = 0x00; + ctx->reg[TCPC_REG_GENERIC_TIMER + 1] = 0x00; + ctx->reg[TCPC_REG_RX_DETECT] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE + 1] = 0x00; + ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x8c; + ctx->reg[TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0x00; + ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x20; + ctx->reg[TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00; + ctx->reg[TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0x00; + ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00; + ctx->reg[TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00; + + tcpci_emul_reset_mask_regs(ctx); + tcpci_emul_reset_role_ctrl(ctx); return tcpci_emul_alert_changed(emul); } @@ -841,16 +825,18 @@ static int tcpci_emul_reset(const struct emul *emul) /** * @brief Set alert and fault registers to indicate i2c interface fault * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @return 0 if successful */ static int tcpci_emul_set_i2c_interface_err(const struct emul *emul) { + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t fault_status; - tcpci_emul_get_reg(emul, TCPC_REG_FAULT_STATUS, &fault_status); + get_reg(ctx, TCPC_REG_FAULT_STATUS, &fault_status); fault_status |= TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR; - tcpci_emul_set_reg(emul, TCPC_REG_FAULT_STATUS, fault_status); + set_reg(ctx, TCPC_REG_FAULT_STATUS, fault_status); return tcpci_emul_alert_changed(emul); } @@ -858,7 +844,7 @@ static int tcpci_emul_set_i2c_interface_err(const struct emul *emul) /** * @brief Handle read from RX buffer registers for TCPCI rev 1.0 and rev 2.0 * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param reg First byte of last i2c write message * @param val Pointer where byte to read should be stored * @param bytes Number of bytes already readded @@ -869,10 +855,11 @@ static int tcpci_emul_set_i2c_interface_err(const struct emul *emul) static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, uint8_t *val, int bytes) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; int is_rev1; - is_rev1 = data->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0; + is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0; if (!is_rev1 && reg != TCPC_REG_RX_BUFFER) { LOG_ERR("Register 0x%x defined only for revision 1.0", reg); @@ -882,7 +869,7 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, switch (reg) { case TCPC_REG_RX_BUFFER: - if (data->rx_msg == NULL) { + if (ctx->rx_msg == NULL) { if (bytes < 2) { *val = 0; } else { @@ -894,16 +881,16 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, } if (bytes == 0) { /* TCPCI message size count include type byte */ - *val = data->rx_msg->cnt + 1; + *val = ctx->rx_msg->cnt + 1; } else if (is_rev1) { LOG_ERR("Revision 1.0 has only byte count at 0x30"); tcpci_emul_set_i2c_interface_err(emul); return -EIO; } else if (bytes == 1) { - *val = data->rx_msg->type; - } else if (data->rx_msg->idx < data->rx_msg->cnt) { - *val = data->rx_msg->buf[data->rx_msg->idx]; - data->rx_msg->idx++; + *val = ctx->rx_msg->type; + } else if (ctx->rx_msg->idx < ctx->rx_msg->cnt) { + *val = ctx->rx_msg->buf[ctx->rx_msg->idx]; + ctx->rx_msg->idx++; } else { LOG_ERR("Reading past RX buffer"); tcpci_emul_set_i2c_interface_err(emul); @@ -918,10 +905,10 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - if (data->rx_msg == NULL) { + if (ctx->rx_msg == NULL) { *val = 0; } else { - *val = data->rx_msg->type; + *val = ctx->rx_msg->type; } break; @@ -932,24 +919,24 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - if (data->rx_msg == NULL) { + if (ctx->rx_msg == NULL) { LOG_ERR("Accessing RX buffer with no msg"); tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - *val = data->rx_msg->buf[bytes]; + *val = ctx->rx_msg->buf[bytes]; break; case TCPC_REG_RX_DATA: - if (data->rx_msg == NULL) { + if (ctx->rx_msg == NULL) { LOG_ERR("Accessing RX buffer with no msg"); tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - if (bytes < data->rx_msg->cnt - 2) { + if (bytes < ctx->rx_msg->cnt - 2) { /* rx_msg cnt include two bytes of header */ - *val = data->rx_msg->buf[bytes + 2]; - data->rx_msg->idx++; + *val = ctx->rx_msg->buf[bytes + 2]; + ctx->rx_msg->idx++; } else { LOG_ERR("Reading past RX buffer"); tcpci_emul_set_i2c_interface_err(emul); @@ -961,39 +948,12 @@ static int tcpci_emul_handle_rx_buf(const struct emul *emul, int reg, return 0; } -/** - * @brief Function called for each byte of read message - * - * @param i2c_emul Pointer to TCPCI emulator - * @param reg First byte of last write message - * @param val Pointer where byte to read should be stored - * @param bytes Number of bytes already readded - * - * @return 0 on success - */ -static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg, - uint8_t *val, int bytes) +/** Check description in emul_tcpci.h */ +int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val, + int bytes) { - struct tcpci_emul_data *data; - const struct emul *emul; - - emul = i2c_emul->parent; - data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul); - - LOG_DBG("TCPCI 0x%x: read reg 0x%x", i2c_emul->addr, reg); - - if (data->dev_ops && data->dev_ops->read_byte) { - switch (data->dev_ops->read_byte(emul, data->dev_ops, reg, val, - bytes)) { - case TCPCI_EMUL_CONTINUE: - break; - case TCPCI_EMUL_DONE: - return 0; - case TCPCI_EMUL_ERROR: - default: - return -EIO; - } - } + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; switch (reg) { /* 16 bits values */ @@ -1019,7 +979,7 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - *val = data->reg[reg + bytes]; + *val = ctx->reg[reg + bytes]; break; /* 8 bits values */ @@ -1048,7 +1008,7 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - *val = data->reg[reg]; + *val = ctx->reg[reg]; break; case TCPC_REG_RX_BUFFER: @@ -1066,43 +1026,15 @@ static int tcpci_emul_read_byte(struct i2c_emul *i2c_emul, int reg, return 0; } -/** - * @brief Function called for each byte of write message. Data are stored - * in write_data field of tcpci_emul_data or in tx_msg in case of - * writing to TX buffer. - * - * @param i2c_emul Pointer to TCPCI emulator - * @param reg First byte of write message - * @param val Received byte of write message - * @param bytes Number of bytes already received - * - * @return 0 on success - * @return -EIO on invalid write to TX buffer - */ -static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg, - uint8_t val, int bytes) +/** Check description in emul_tcpci.h */ +int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val, + int bytes) { - struct tcpci_emul_data *data; - const struct emul *emul; int is_rev1; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - emul = i2c_emul->parent; - data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul); - - if (data->dev_ops && data->dev_ops->write_byte) { - switch (data->dev_ops->write_byte(emul, data->dev_ops, reg, val, - bytes)) { - case TCPCI_EMUL_CONTINUE: - break; - case TCPCI_EMUL_DONE: - return 0; - case TCPCI_EMUL_ERROR: - default: - return -EIO; - } - } - - is_rev1 = data->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0; + is_rev1 = ctx->reg[TCPC_REG_PD_INT_REV] == TCPC_REG_PD_INT_REV_REV_1_0; switch (reg) { case TCPC_REG_TX_BUFFER: if (is_rev1) { @@ -1111,16 +1043,16 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - data->tx_msg->idx = val; + ctx->tx_msg->idx = val; } if (bytes == 1) { - data->tx_msg->cnt = val; + ctx->tx_msg->cnt = val; } else { - if (data->tx_msg->cnt > 0) { - data->tx_msg->cnt--; - data->tx_msg->buf[data->tx_msg->idx] = val; - data->tx_msg->idx++; + if (ctx->tx_msg->cnt > 0) { + ctx->tx_msg->cnt--; + ctx->tx_msg->buf[ctx->tx_msg->idx] = val; + ctx->tx_msg->idx++; } else { LOG_ERR("Writing past TX buffer"); tcpci_emul_set_i2c_interface_err(emul); @@ -1146,7 +1078,7 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - data->tx_msg->buf[bytes] = val; + ctx->tx_msg->buf[bytes] = val; return 0; case TCPC_REG_TX_HDR: @@ -1166,14 +1098,14 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg, tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - data->tx_msg->buf[bytes] = val; + ctx->tx_msg->buf[bytes] = val; return 0; } if (bytes == 1) { - data->write_data = val; + ctx->write_data = val; } else if (bytes == 2) { - data->write_data |= (uint16_t)val << 8; + ctx->write_data |= (uint16_t)val << 8; } return 0; @@ -1182,29 +1114,30 @@ static int tcpci_emul_write_byte(struct i2c_emul *i2c_emul, int reg, /** * @brief Handle writes to command register * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return 0 on success * @return -EIO on unknown command value */ static int tcpci_emul_handle_command(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t role_ctrl; uint16_t pwr_ctrl; - switch (data->write_data & 0xff) { + switch (ctx->write_data & 0xff) { case TCPC_REG_COMMAND_RESET_TRANSMIT_BUF: - data->tx_msg->idx = 0; + ctx->tx_msg->idx = 0; break; case TCPC_REG_COMMAND_RESET_RECEIVE_BUF: - if (data->rx_msg) { - data->rx_msg->idx = 0; + if (ctx->rx_msg) { + ctx->rx_msg->idx = 0; } break; case TCPC_REG_COMMAND_LOOK4CONNECTION: - tcpci_emul_get_reg(emul, TCPC_REG_ROLE_CTRL, &role_ctrl); - tcpci_emul_get_reg(emul, TCPC_REG_POWER_CTRL, &pwr_ctrl); + get_reg(ctx, TCPC_REG_ROLE_CTRL, &role_ctrl); + get_reg(ctx, TCPC_REG_POWER_CTRL, &pwr_ctrl); /* * Start DRP toggling only if auto discharge is disabled, @@ -1217,8 +1150,7 @@ static int tcpci_emul_handle_command(const struct emul *emul) (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RP || TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RD)) { /* Set Look4Connection and clear CC1/2 state */ - tcpci_emul_set_reg( - emul, TCPC_REG_CC_STATUS, + set_reg(ctx, TCPC_REG_CC_STATUS, TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK); } break; @@ -1238,45 +1170,47 @@ static int tcpci_emul_handle_command(const struct emul *emul) * Set command register to allow easier inspection of last * command sent */ - tcpci_emul_set_reg(emul, TCPC_REG_COMMAND, data->write_data & 0xff); + set_reg(ctx, TCPC_REG_COMMAND, ctx->write_data & 0xff); return 0; } /** * @brief Handle write to transmit register * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return 0 on success * @return -EIO when sending SOP message with less than 2 bytes in TX buffer */ static int tcpci_emul_handle_transmit(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; enum tcpci_msg_type type; - data->tx_msg->cnt = data->tx_msg->idx; - data->tx_msg->type = TCPC_REG_TRANSMIT_TYPE(data->write_data); - data->tx_msg->idx = 0; + ctx->tx_msg->cnt = ctx->tx_msg->idx; + ctx->tx_msg->type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data); + ctx->tx_msg->idx = 0; - type = TCPC_REG_TRANSMIT_TYPE(data->write_data); + type = TCPC_REG_TRANSMIT_TYPE(ctx->write_data); - if (type < NUM_SOP_STAR_TYPES && data->tx_msg->cnt < 2) { + if (type < NUM_SOP_STAR_TYPES && ctx->tx_msg->cnt < 2) { LOG_ERR("Transmitting too short message (%d)", - data->tx_msg->cnt); + ctx->tx_msg->cnt); tcpci_emul_set_i2c_interface_err(emul); return -EIO; } - if (data->partner && data->partner->transmit) { - data->partner->transmit(emul, data->partner, data->tx_msg, type, - TCPC_REG_TRANSMIT_RETRY(data->write_data)); + if (ctx->partner && ctx->partner->transmit) { + ctx->partner->transmit( + emul, ctx->partner, ctx->tx_msg, type, + TCPC_REG_TRANSMIT_RETRY(ctx->write_data)); } switch (type) { case TCPCI_MSG_TX_HARD_RESET: tcpci_emul_disable_pd_msg_delivery(emul); - tcpci_emul_reset_mask_regs(emul); + tcpci_emul_reset_mask_regs(ctx); /* fallthrough */ case TCPCI_MSG_CABLE_RESET: /* @@ -1293,22 +1227,11 @@ static int tcpci_emul_handle_transmit(const struct emul *emul) return 0; } -/** - * @brief Handle I2C write message. It is checked if accessed register isn't RO - * and reserved bits are set to 0. - * - * @param i2c_emul Pointer to TCPCI emulator - * @param reg Register which is written - * @param msg_len Length of handled I2C message - * - * @return 0 on success - * @return -EIO on error - */ -static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, - int msg_len) +/** Check description in emul_tcpci.h */ +int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len) { - struct tcpci_emul_data *data; - const struct emul *emul; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; uint16_t rsvd_mask = 0; uint16_t alert_val; bool inform_partner = false; @@ -1324,43 +1247,24 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, /* Exclude register address byte from message length */ msg_len--; - emul = i2c_emul->parent; - data = TCPCI_DATA_FROM_I2C_EMUL(i2c_emul); - - LOG_DBG("TCPCI 0x%x: write reg 0x%x val 0x%x", i2c_emul->addr, reg, - data->write_data); - - if (data->dev_ops && data->dev_ops->handle_write) { - switch (data->dev_ops->handle_write(emul, data->dev_ops, reg, - msg_len)) { - case TCPCI_EMUL_CONTINUE: - break; - case TCPCI_EMUL_DONE: - return 0; - case TCPCI_EMUL_ERROR: - default: - return -EIO; - } - } - switch (reg) { /* Alert registers */ case TCPC_REG_ALERT: /* Overflow is cleared by Receive SOP message status */ - data->write_data &= ~TCPC_REG_ALERT_RX_BUF_OVF; - if (data->write_data & TCPC_REG_ALERT_RX_STATUS) { - data->write_data |= TCPC_REG_ALERT_RX_BUF_OVF; + ctx->write_data &= ~TCPC_REG_ALERT_RX_BUF_OVF; + if (ctx->write_data & TCPC_REG_ALERT_RX_STATUS) { + ctx->write_data |= TCPC_REG_ALERT_RX_BUF_OVF; /* Do not clear RX status if there is new message */ if (tcpci_emul_get_next_rx_msg(emul)) { - data->write_data &= ~TCPC_REG_ALERT_RX_STATUS; + ctx->write_data &= ~TCPC_REG_ALERT_RX_STATUS; } } /* fallthrough */ case TCPC_REG_FAULT_STATUS: case TCPC_REG_ALERT_EXT: /* Clear bits where TCPM set 1 */ - tcpci_emul_get_reg(emul, reg, &alert_val); - data->write_data = alert_val & (~data->write_data); + get_reg(ctx, reg, &alert_val); + ctx->write_data = alert_val & (~ctx->write_data); /* fallthrough */ case TCPC_REG_ALERT_MASK: case TCPC_REG_POWER_STATUS_MASK: @@ -1390,11 +1294,11 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, break; case TCPC_REG_CONFIG_EXT_1: - if (data->write_data & TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR && - ((data->reg[TCPC_REG_STD_INPUT_CAP] & + if (ctx->write_data & TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR && + ((ctx->reg[TCPC_REG_STD_INPUT_CAP] & TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP) == BIT(4)) && - data->reg[TCPC_REG_STD_OUTPUT_CAP] & - TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET) { + ctx->reg[TCPC_REG_STD_OUTPUT_CAP] & + TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET) { tcpci_emul_set_i2c_interface_err(emul); return 0; } @@ -1447,10 +1351,10 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, } /* Check reserved bits */ - if (data->error_on_rsvd_write && rsvd_mask & data->write_data) { + if (ctx->error_on_rsvd_write && rsvd_mask & ctx->write_data) { tcpci_emul_set_i2c_interface_err(emul); LOG_ERR("Writing 0x%x to reg 0x%x with rsvd bits mask 0x%x", - data->write_data, reg, rsvd_mask); + ctx->write_data, reg, rsvd_mask); return -EIO; } @@ -1463,7 +1367,7 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, } /* Set new value of register */ - tcpci_emul_set_reg(emul, reg, data->write_data); + set_reg(ctx, reg, ctx->write_data); if (alert_changed) { rc = tcpci_emul_alert_changed(emul); @@ -1471,119 +1375,33 @@ static int tcpci_emul_handle_write(struct i2c_emul *i2c_emul, int reg, return rc; } - if (inform_partner && data->partner && data->partner->control_change) { - data->partner->control_change(emul, data->partner); + if (inform_partner && ctx->partner && ctx->partner->control_change) { + ctx->partner->control_change(emul, ctx->partner); } return 0; } -/** - * @brief Get currently accessed register, which always equals to selected - * register. - * - * @param i2c_emul Pointer to TCPCI emulator - * @param reg First byte of last write message - * @param bytes Number of bytes already handled from current message - * @param read If currently handled is read message - * - * @return Currently accessed register - */ -static int tcpci_emul_access_reg(struct i2c_emul *i2c_emul, int reg, int bytes, - bool read) -{ - return reg; -} - -/* Device instantiation */ - /** Check description in emul_tcpci.h */ struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul) { - struct tcpci_emul_data *data = emul->data; + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; - return &data->common.emul; + return &ctx->common.emul; } -/** - * @brief Set up a new TCPCI emulator - * - * This should be called for each TCPCI device that needs to be - * emulated. It registers it with the I2C emulation controller. - * - * @param emul Emulation information - * @param parent Device to emulate - * - * @return 0 indicating success (always) - */ -static int tcpci_emul_init(const struct emul *emul, const struct device *parent) +/** Check description in emul_tcpci.h */ +void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev) { - const struct i2c_common_emul_cfg *cfg = emul->cfg; - struct tcpci_emul_data *data = emul->data; - int ret; - - data->common.emul.api = &i2c_common_emul_api; - data->common.emul.addr = cfg->addr; - data->common.emul.parent = emul; - data->common.i2c = parent; - data->common.cfg = cfg; - i2c_common_emul_init(&data->common); - - ret = i2c_emul_register(parent, emul->dev_label, &data->common.emul); - if (ret != 0) - return ret; - - return tcpci_emul_reset(emul); -} + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *ctx = tcpc_data->tcpci_ctx; -#define TCPCI_EMUL(n) \ - uint8_t tcpci_emul_tx_buf_##n[128]; \ - static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = { \ - .buf = tcpci_emul_tx_buf_##n, \ - }; \ - \ - static struct tcpci_emul_data tcpci_emul_data_##n = { \ - .tx_msg = &tcpci_emul_tx_msg_##n, \ - .error_on_ro_write = true, \ - .error_on_rsvd_write = true, \ - .common = { \ - .write_byte = tcpci_emul_write_byte, \ - .finish_write = tcpci_emul_handle_write, \ - .read_byte = tcpci_emul_read_byte, \ - .access_reg = tcpci_emul_access_reg, \ - }, \ - .alert_gpio_port = COND_CODE_1( \ - DT_INST_NODE_HAS_PROP(n, alert_gpio), \ - (DEVICE_DT_GET(DT_GPIO_CTLR( \ - DT_INST_PROP(n, alert_gpio), gpios))), \ - (NULL)), \ - .alert_gpio_pin = COND_CODE_1( \ - DT_INST_NODE_HAS_PROP(n, alert_gpio), \ - (DT_GPIO_PIN(DT_INST_PROP(n, alert_gpio), \ - gpios)), \ - (0)), \ - }; \ - \ - static const struct i2c_common_emul_cfg tcpci_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .data = &tcpci_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(tcpci_emul_init, DT_DRV_INST(n), \ - &tcpci_emul_cfg_##n, &tcpci_emul_data_##n) - -DT_INST_FOREACH_STATUS_OKAY(TCPCI_EMUL) - -#ifdef CONFIG_ZTEST_NEW_API -#define TCPCI_EMUL_RESET_RULE_BEFORE(n) \ - tcpci_emul_reset(&EMUL_REG_NAME(DT_DRV_INST(n))); -static void tcpci_emul_reset_rule_before(const struct ztest_unit_test *test, - void *data) -{ - ARG_UNUSED(test); - ARG_UNUSED(data); - DT_INST_FOREACH_STATUS_OKAY(TCPCI_EMUL_RESET_RULE_BEFORE); + ctx->common.emul.api = &i2c_common_emul_api; + ctx->common.emul.addr = tcpc_data->i2c_cfg.addr; + ctx->common.emul.parent = emul; + ctx->common.i2c = i2c_dev; + ctx->common.cfg = &tcpc_data->i2c_cfg; + + i2c_common_emul_init(&ctx->common); } -ZTEST_RULE(tcpci_emul_reset, tcpci_emul_reset_rule_before, NULL); -#endif /* CONFIG_ZTEST_NEW_API */ diff --git a/zephyr/emul/tcpc/emul_tcpci_generic.c b/zephyr/emul/tcpc/emul_tcpci_generic.c new file mode 100644 index 0000000000..4ff05d1f40 --- /dev/null +++ b/zephyr/emul/tcpc/emul_tcpci_generic.c @@ -0,0 +1,172 @@ +/* Copyright 2022 The ChromiumOS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#define DT_DRV_COMPAT cros_tcpci_generic_emul + +#include +LOG_MODULE_REGISTER(tcpci_generic_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); + +#include +#include +#include +#include +#include + +#include "tcpm/tcpci.h" + +#include "emul/emul_common_i2c.h" +#include "emul/tcpc/emul_tcpci.h" + +/** + * @brief Function called for each byte of read message from TCPCI emulator + * + * @param i2c_emul Pointer to I2C TCPCI emulator + * @param reg First byte of last write message + * @param val Pointer where byte to read should be stored + * @param bytes Number of bytes already read + * + * @return 0 on success + * @return -EIO on invalid read request + */ +static int tcpci_generic_emul_read_byte(struct i2c_emul *i2c_emul, int reg, + uint8_t *val, int bytes) +{ + const struct emul *emul; + + LOG_DBG("TCPCI Generic 0x%x: read reg 0x%x", i2c_emul->addr, reg); + + emul = i2c_emul->parent; + + return tcpci_emul_read_byte(emul, reg, val, bytes); +} + +/** + * @brief Function called for each byte of write message to TCPCI emulator + * + * @param i2c_emul Pointer to I2C TCPCI emulator + * @param reg First byte of write message + * @param val Received byte of write message + * @param bytes Number of bytes already received + * + * @return 0 on success + * @return -EIO on invalid write request + */ +static int tcpci_generic_emul_write_byte(struct i2c_emul *i2c_emul, int reg, + uint8_t val, int bytes) +{ + const struct emul *emul; + + LOG_DBG("TCPCI Generic 0x%x: write reg 0x%x", i2c_emul->addr, reg); + + emul = i2c_emul->parent; + + return tcpci_emul_write_byte(emul, reg, val, bytes); +} + +/** + * @brief Function called on the end of write message to TCPCI emulator + * + * @param i2c_emul Pointer to I2C TCPCI emulator + * @param reg Register which is written + * @param msg_len Length of handled I2C message + * + * @return 0 on success + * @return -EIO on error + */ +static int tcpci_generic_emul_finish_write(struct i2c_emul *i2c_emul, int reg, + int msg_len) +{ + const struct emul *emul; + + LOG_DBG("TCPCI Generic 0x%x: finish write reg 0x%x", i2c_emul->addr, + reg); + + emul = i2c_emul->parent; + + return tcpci_emul_handle_write(emul, reg, msg_len); +} + +/** + * @brief Get currently accessed register, which always equals to selected + * register from TCPCI emulator. + * + * @param i2c_emul Pointer to I2C TCPCI emulator + * @param reg First byte of last write message + * @param bytes Number of bytes already handled from current message + * @param read If currently handled is read message + * + * @return Currently accessed register + */ +static int tcpci_generic_emul_access_reg(struct i2c_emul *i2c_emul, int reg, + int bytes, bool read) +{ + return reg; +} + +/** + * @brief Function called on reset + * + * @param emul Pointer to TCPC emulator + */ +static void tcpci_generic_emul_reset(const struct emul *emul) +{ + tcpci_emul_reset(emul); +} + +/** + * @brief Set up a new TCPCI generic emulator + * + * This should be called for each TCPCI Generic device that needs to be + * emulated. + * + * @param emul Emulation information + * @param parent Device to emulate + * + * @return 0 indicating success (always) + */ +static int tcpci_generic_emul_init(const struct emul *emul, + const struct device *parent) +{ + struct tcpc_emul_data *tcpc_data = emul->data; + struct tcpci_ctx *tcpci_ctx = tcpc_data->tcpci_ctx; + const struct device *i2c_dev; + int ret; + + i2c_dev = parent; + + tcpci_ctx->common.write_byte = tcpci_generic_emul_write_byte; + tcpci_ctx->common.finish_write = tcpci_generic_emul_finish_write; + tcpci_ctx->common.read_byte = tcpci_generic_emul_read_byte; + tcpci_ctx->common.access_reg = tcpci_generic_emul_access_reg; + + tcpci_emul_i2c_init(emul, i2c_dev); + + ret = i2c_emul_register(i2c_dev, emul->dev_label, + &tcpci_ctx->common.emul); + + tcpci_generic_emul_reset(emul); + + return ret; +} + +#define TCPCI_GENERIC_EMUL(n) \ + TCPCI_EMUL_DEFINE(n, tcpci_generic_emul_init, NULL, NULL) + +DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL) + +#ifdef CONFIG_ZTEST_NEW_API +#define TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE(n) \ + tcpci_generic_emul_reset(&EMUL_REG_NAME(DT_DRV_INST(n))); +static void +tcpci_generic_emul_reset_rule_before(const struct ztest_unit_test *test, + void *data) +{ + ARG_UNUSED(test); + ARG_UNUSED(data); + DT_INST_FOREACH_STATUS_OKAY(TCPCI_GENERIC_EMUL_RESET_RULE_BEFORE); +} +ZTEST_RULE(tcpci_generic_emul_reset, tcpci_generic_emul_reset_rule_before, + NULL); +#endif /* CONFIG_ZTEST_NEW_API */ diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h index dd225c5f6e..81fea3edeb 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci.h +++ b/zephyr/include/emul/tcpc/emul_tcpci.h @@ -17,27 +17,13 @@ #include #include +#include "emul/emul_common_i2c.h" + /** - * @brief TCPCI emulator backend API - * @defgroup tcpci_emul TCPCI emulator - * @{ - * - * TCPCI emulator supports access to its registers using I2C messages. - * It follows Type-C Port Controller Interface Specification. It is possible - * to use this emulator as base for implementation of specific TCPC emulator - * which follows TCPCI specification. Emulator allows to set callbacks - * on change of CC status or transmitting message to implement partner emulator. - * There is also callback used to inform about alert line state change. - * Application may alter emulator state: - * - * - call @ref tcpci_emul_set_reg and @ref tcpci_emul_get_reg to set and get - * value of TCPCI registers - * - call functions from emul_common_i2c.h to setup custom handlers for I2C - * messages - * - call @ref tcpci_emul_add_rx_msg to setup received SOP messages - * - call @ref tcpci_emul_get_tx_msg to examine sended message - * - call @ref tcpci_emul_set_rev to set revision of emulated TCPCI + * Number of emulated register. This include vendor registers defined in TCPCI + * specification */ +#define TCPCI_EMUL_REG_COUNT 0x100 /** SOP message structure */ struct tcpci_emul_msg { @@ -64,6 +50,81 @@ struct tcpci_emul_msg { typedef void (*tcpci_emul_alert_state_func)(const struct emul *emul, bool alert, void *data); +/** Run-time data used by the emulator */ +struct tcpci_ctx { + /** Common I2C data for TCPC */ + struct i2c_common_emul_data common; + + /** Current state of all emulated TCPCI registers */ + uint8_t reg[TCPCI_EMUL_REG_COUNT]; + + /** Structures representing TX and RX buffers */ + struct tcpci_emul_msg *rx_msg; + struct tcpci_emul_msg *tx_msg; + + /** Data that should be written to register (except TX_BUFFER) */ + uint16_t write_data; + + /** Return error when trying to write to RO register */ + bool error_on_ro_write; + /** Return error when trying to write 1 to reserved bit */ + bool error_on_rsvd_write; + + /** User function called when alert line could change */ + tcpci_emul_alert_state_func alert_callback; + /** Data passed to alert_callback */ + void *alert_callback_data; + + /** Callbacks for TCPCI partner */ + const struct tcpci_emul_partner_ops *partner; + + /** Reference to Alert# GPIO emulator. */ + const struct device *alert_gpio_port; + gpio_pin_t alert_gpio_pin; +}; + +/** Run-time data used by the emulator */ +struct tcpc_emul_data { + /** Pointer to the common TCPCI emulator context */ + struct tcpci_ctx *tcpci_ctx; + + /** Pointer to chip specific data */ + void *chip_data; + + const struct i2c_common_emul_cfg i2c_cfg; +}; + +#define TCPCI_EMUL_DEFINE(n, init, cfg_ptr, chip_data_ptr) \ + static uint8_t tcpci_emul_tx_buf_##n[128]; \ + static struct tcpci_emul_msg tcpci_emul_tx_msg_##n = { \ + .buf = tcpci_emul_tx_buf_##n, \ + }; \ + static struct tcpci_ctx tcpci_ctx##n = { \ + .tx_msg = &tcpci_emul_tx_msg_##n, \ + .error_on_ro_write = true, \ + .error_on_rsvd_write = true, \ + .alert_gpio_port = COND_CODE_1( \ + DT_INST_NODE_HAS_PROP(n, alert_gpio), \ + (DEVICE_DT_GET(DT_GPIO_CTLR( \ + DT_INST_PROP(n, alert_gpio), gpios))), \ + (NULL)), \ + .alert_gpio_pin = COND_CODE_1( \ + DT_INST_NODE_HAS_PROP(n, alert_gpio), \ + (DT_GPIO_PIN(DT_INST_PROP(n, alert_gpio), gpios)), \ + (0)), \ + }; \ + static struct tcpc_emul_data tcpc_emul_data_##n = { \ + .tcpci_ctx = &tcpci_ctx##n, \ + .chip_data = chip_data_ptr, \ + .i2c_cfg = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .data = &tcpci_ctx##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }, \ + }; \ + EMUL_DEFINE(init, DT_DRV_INST(n), cfg_ptr, &tcpc_emul_data_##n) + /** Response from TCPCI specific device operations */ enum tcpci_emul_ops_resp { TCPCI_EMUL_CONTINUE = 0, @@ -203,7 +264,7 @@ struct tcpci_emul_partner_ops { /** * @brief Get i2c_emul for TCPCI emulator * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return Pointer to I2C TCPCI emulator */ @@ -212,7 +273,7 @@ struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul); /** * @brief Set value of given register of TCPCI * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param reg Register address which value will be changed * @param val New value of the register * @@ -221,6 +282,68 @@ struct i2c_emul *tcpci_emul_get_i2c_emul(const struct emul *emul); */ int tcpci_emul_set_reg(const struct emul *emul, int reg, uint16_t val); +/** + * @brief Function called for each byte of read message from TCPCI + * + * @param emul Pointer to TCPC emulator + * @param reg First byte of last write message + * @param val Pointer where byte to read should be stored + * @param bytes Number of bytes already readded + * + * @return 0 on success + */ +int tcpci_emul_read_byte(const struct emul *emul, int reg, uint8_t *val, + int bytes); + +/** + * @brief Function called for each byte of write message from TCPCI. + * Data are stored in write_data field of tcpci_emul_data or in tx_msg + * in case of writing to TX buffer. + * + * @param emul Pointer to TCPC emulator + * @param reg First byte of write message + * @param val Received byte of write message + * @param bytes Number of bytes already received + * + * @return 0 on success + * @return -EIO on invalid write to TX buffer + */ +int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val, + int bytes); + +/** + * @brief Handle I2C write message. It is checked if accessed register isn't RO + * and reserved bits are set to 0. + * + * @param emul Pointer to TCPC emulator + * @param reg Register which is written + * @param msg_len Length of handled I2C message + * + * @return 0 on success + * @return -EIO on error + */ +int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len); + +/** + * @brief Set up a new TCPCI emulator + * + * This should be called for each TCPC device that needs to be + * registered on the I2C bus. + * + * @param emul Pointer to TCPC emulator + * @param parent Pointer to emulated I2C bus + */ +void tcpci_emul_i2c_init(const struct emul *emul, const struct device *i2c_dev); + +/** + * @brief Reset registers to default values. Vendor and reserved registers + * are not changed. + * + * @param emul Pointer to TCPC emulator + * @return 0 if successful + */ +int tcpci_emul_reset(const struct emul *emul); + /** * @brief Get value of given register of TCPCI * @@ -237,7 +360,7 @@ int tcpci_emul_get_reg(const struct emul *emul, int reg, uint16_t *val); /** * @brief Add up to two SOP RX messages * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param rx_msg Pointer to message that is added * @param alert Select if alert register should be updated * @@ -255,7 +378,7 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, /** * @brief Get SOP TX message to examine what was sended by TCPM * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return Pointer to TX message */ @@ -264,7 +387,7 @@ struct tcpci_emul_msg *tcpci_emul_get_tx_msg(const struct emul *emul); /** * @brief Set TCPCI revision in PD_INT_REV register * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param rev Requested revision */ void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev); @@ -281,7 +404,7 @@ void tcpci_emul_set_dev_ops(const struct emul *emul, /** * @brief Set callback which is called when alert register is changed * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param alert_callback Pointer to callback * @param alert_callback_data Pointer to data passed to callback as an argument */ @@ -292,7 +415,7 @@ void tcpci_emul_set_alert_callback(const struct emul *emul, /** * @brief Set callbacks for port partner device emulator * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param partner Pointer to callbacks */ void tcpci_emul_set_partner_ops(const struct emul *emul, @@ -301,7 +424,7 @@ void tcpci_emul_set_partner_ops(const struct emul *emul, /** * @brief Emulate connection of specific device to emulated TCPCI * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param partner_power_role Power role of connected partner (sink or source) * @param partner_cc1 Voltage on partner CC1 line (usually Rd or Rp) * @param partner_cc2 Voltage on partner CC2 line (usually open or Ra if active @@ -321,7 +444,7 @@ int tcpci_emul_connect_partner(const struct emul *emul, /** @brief Emulate the disconnection of the partner device to emulated TCPCI * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * * @return 0 on success */ @@ -330,7 +453,7 @@ int tcpci_emul_disconnect_partner(const struct emul *emul); /** * @brief Allows port partner to select if message was received correctly * - * @param emul Pointer to TCPCI emulator + * @param emul Pointer to TCPC emulator * @param status Status of sended message */ void tcpci_emul_partner_msg_status(const struct emul *emul, diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index e7002ba4a2..1944fd32fa 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -704,18 +704,10 @@ reg = <0x400 4>; label = "I2C_1"; - tcpci_ps8xxx_emul: tcpci_ps8xxx_emul@b { - compatible = "cros,tcpci-emul"; - status = "okay"; + ps8xxx_emul: ps8xxx_emul@b { + compatible = "cros,ps8xxx-emul"; reg = <0xb>; - label = "TCPCI_PS8XXX_EMUL"; alert_gpio = <&usb_c1_tcpc_int_odl>; - }; - - ps8xxx_emul: ps8xxx_emul@b1 { - compatible = "cros,ps8xxx-emul"; - reg = <0xb1>; - tcpci-i2c = <&tcpci_ps8xxx_emul>; p0-i2c-addr = <0x8>; p1-i2c-addr = <0x9>; gpio-i2c-addr = <0x1a>; @@ -883,12 +875,13 @@ }; tcpci_emul: tcpci_emul@82 { - compatible = "cros,tcpci-emul"; + compatible = "cros,tcpci-generic-emul"; status = "okay"; reg = <0x82>; label = "TCPCI_EMUL"; alert_gpio = <&usb_c0_tcpc_int_odl>; }; + }; /* Enable all thermistors for testing */ diff --git a/zephyr/test/drivers/prj.conf b/zephyr/test/drivers/prj.conf index aadf8e44eb..f006bc0117 100644 --- a/zephyr/test/drivers/prj.conf +++ b/zephyr/test/drivers/prj.conf @@ -59,6 +59,7 @@ CONFIG_EMUL_BMA255=y CONFIG_EMUL_BMI=y CONFIG_EMUL_TCS3400=y CONFIG_EMUL_BB_RETIMER=y +CONFIG_EMUL_TCPCI=y CONFIG_EMUL_PS8XXX=y CONFIG_EMUL_TCPCI_PARTNER_DRP=y CONFIG_EMUL_TCPCI_PARTNER_FAULTY_SNK=y diff --git a/zephyr/test/drivers/src/console_cmd/charge_manager.c b/zephyr/test/drivers/src/console_cmd/charge_manager.c index e9a3a8ca29..64716b1ced 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_manager.c +++ b/zephyr/test/drivers/src/console_cmd/charge_manager.c @@ -9,6 +9,7 @@ #include "charge_manager.h" #include "console.h" #include "emul/emul_isl923x.h" +#include "emul/tcpc/emul_tcpci.h" #include "emul/tcpc/emul_tcpci_partner_snk.h" #include "tcpm/tcpci.h" #include "test/drivers/test_state.h" diff --git a/zephyr/test/drivers/src/integration/usbc/usb.c b/zephyr/test/drivers/src/integration/usbc/usb.c index 0a6443ded9..2344ca5935 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb.c +++ b/zephyr/test/drivers/src/integration/usbc/usb.c @@ -26,7 +26,7 @@ #include "test/drivers/test_state.h" #define TCPCI_EMUL_LABEL DT_NODELABEL(tcpci_emul) -#define TCPCI_EMUL_LABEL2 DT_NODELABEL(tcpci_ps8xxx_emul) +#define TCPCI_EMUL_LABEL2 DT_NODELABEL(ps8xxx_emul) #define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c index e88aedd6e3..90409b2a83 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c @@ -26,7 +26,7 @@ #define SRC_PORT USBC_PORT_C1 #define TCPCI_EMUL_LABEL DT_NODELABEL(tcpci_emul) -#define TCPCI_PS8XXX_EMUL_LABEL DT_NODELABEL(tcpci_ps8xxx_emul) +#define TCPCI_PS8XXX_EMUL_LABEL DT_NODELABEL(ps8xxx_emul) #define DEFAULT_VBUS_MV 5000 diff --git a/zephyr/test/drivers/src/ps8xxx.c b/zephyr/test/drivers/src/ps8xxx.c index dc1695d793..303be071ea 100644 --- a/zephyr/test/drivers/src/ps8xxx.c +++ b/zephyr/test/drivers/src/ps8xxx.c @@ -26,26 +26,25 @@ static void test_ps8xxx_init_fail(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *ps8xxx_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); /* Test fail on FW reg read */ - i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV); + i2c_common_emul_set_read_fail_reg(ps8xxx_i2c_emul, PS8XXX_REG_FW_REV); zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); - i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, + i2c_common_emul_set_read_fail_reg(ps8xxx_i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test fail on FW reg set to 0 */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x0); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x0); zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); /* Set arbitrary FW reg value != 0 for rest of the test */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); /* Test fail on TCPCI init */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, TCPC_REG_POWER_STATUS_UNINIT); zassert_equal(EC_ERROR_TIMEOUT, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); @@ -68,15 +67,14 @@ ZTEST(ps8815, test_init_fail) ZTEST(ps8805, test_ps8805_init) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); struct i2c_emul *p1_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); /* Set arbitrary FW reg value != 0 for this test */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); /* Set correct power status for this test */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0); /* Test fail on read I2C debug reg */ i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, @@ -96,7 +94,7 @@ ZTEST(ps8805, test_ps8805_init) /* Test successful init */ zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); - check_tcpci_reg(tcpci_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, + check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE, PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON); zassert_equal(PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF, ps8xxx_emul_get_dci_cfg(ps8xxx_emul) & @@ -107,14 +105,13 @@ ZTEST(ps8805, test_ps8805_init) ZTEST(ps8815, test_ps8815_init) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); struct i2c_emul *p1_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1); /* Set arbitrary FW reg value != 0 for this test */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); /* Set correct power status for rest of the test */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0); /* Test fail on reading HW revision register */ i2c_common_emul_set_read_fail_reg(p1_i2c_emul, @@ -132,8 +129,7 @@ ZTEST(ps8815, test_ps8815_init) static void test_ps8xxx_release(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); uint64_t start_ms; /* Test successful release with correct FW reg read */ @@ -170,11 +166,10 @@ static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc, uint16_t rp_detect_ctrl, const char *test_case) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); uint16_t reg_val, exp_role_ctrl; /* Clear RP detect register to see if it is set after test */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_RP_DETECT_CONTROL, 0); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL, 0); exp_role_ctrl = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, rp, cc, cc); @@ -184,12 +179,13 @@ static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc, zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.set_cc(USBC_PORT_C1, cc), "Failed to set CC for case: %s", test_case); - zassert_ok(tcpci_emul_get_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, ®_val), + zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, + ®_val), "Failed tcpci_emul_get_reg() for case: %s", test_case); zassert_equal(exp_role_ctrl, reg_val, "0x%x != (role_ctrl = 0x%x) for case: %s", exp_role_ctrl, reg_val, test_case); - zassert_ok(tcpci_emul_get_reg(tcpci_emul, PS8XXX_REG_RP_DETECT_CONTROL, + zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_RP_DETECT_CONTROL, ®_val), "Failed tcpci_emul_get_reg() for case: %s", test_case); zassert_equal(rp_detect_ctrl, reg_val, @@ -201,12 +197,11 @@ static void check_ps8815_set_cc(enum tcpc_rp_value rp, enum tcpc_cc_pull cc, ZTEST(ps8815, test_ps8815_set_cc) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); int64_t start_time; int64_t delay; /* Set firmware version <= 0x10 to set "disable rp detect" workaround */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x8); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x8); zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, RP_DETECT_DISABLE, @@ -226,7 +221,7 @@ ZTEST(ps8815, test_ps8815_set_cc) * Set firmware version <= 0x10 to set "disable rp detect" workaround * again */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0xa); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0xa); zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); /* CC RD shouldn't trigger "disable rp detect" workaround */ @@ -237,7 +232,7 @@ ZTEST(ps8815, test_ps8815_set_cc) * Set firmware version > 0x10 to unset "disable rp detect" * workaround */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x12); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x12); zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); /* Firmware > 0x10 shouldn't trigger "disable rp detect" workaround */ @@ -320,13 +315,12 @@ ZTEST(ps8815, test_set_vconn) static void test_ps8xxx_transmit(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); struct tcpci_emul_msg *msg; uint64_t exp_cnt, cnt; uint16_t reg_val; - msg = tcpci_emul_get_tx_msg(tcpci_emul); + msg = tcpci_emul_get_tx_msg(ps8xxx_emul); /* Test fail on transmitting BIST MODE 2 message */ i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, TCPC_REG_TRANSMIT); @@ -343,23 +337,26 @@ static void test_ps8xxx_transmit(void) ps8xxx_tcpm_drv.transmit(USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL), NULL); - check_tcpci_reg(tcpci_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0); + check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0); zassert_equal(TCPCI_MSG_TX_BIST_MODE_2, msg->type, NULL); /* Check BIST counter value */ - zassert_ok(tcpci_emul_get_reg(tcpci_emul, + zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_BYTE2, - ®_val), NULL); + ®_val), + NULL); cnt = reg_val; cnt <<= 8; - zassert_ok(tcpci_emul_get_reg(tcpci_emul, + zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_BYTE1, - ®_val), NULL); + ®_val), + NULL); cnt |= reg_val; cnt <<= 8; - zassert_ok(tcpci_emul_get_reg(tcpci_emul, + zassert_ok(tcpci_emul_get_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_BYTE0, - ®_val), NULL); + ®_val), + NULL); cnt |= reg_val; zassert_equal(exp_cnt, cnt, "0x%llx != 0x%llx", exp_cnt, cnt); } @@ -378,8 +375,7 @@ ZTEST(ps8815, test_transmit) static void test_ps88x5_drp_toggle(bool delay_expected) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); uint16_t exp_role_ctrl; int64_t start_time; int64_t delay; @@ -404,7 +400,7 @@ static void test_ps88x5_drp_toggle(bool delay_expected) I2C_COMMON_EMUL_NO_FAIL_REG); /* Set CC status as snk, CC lines set arbitrary */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_CC_STATUS, + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS, TCPC_REG_CC_STATUS_SET(1, TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA)); @@ -424,12 +420,12 @@ static void test_ps88x5_drp_toggle(bool delay_expected) } else { zassert_true(delay == 0, "unexpected delay (%lld ms)", delay); } - check_tcpci_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl); - check_tcpci_reg(tcpci_emul, TCPC_REG_COMMAND, + check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl); + check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_LOOK4CONNECTION); /* Set CC status as src, CC lines set arbitrary */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_CC_STATUS, + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_CC_STATUS, TCPC_REG_CC_STATUS_SET(0, TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA)); @@ -445,8 +441,8 @@ static void test_ps88x5_drp_toggle(bool delay_expected) } else { zassert_true(delay == 0, "unexpected delay (%lld ms)", delay); } - check_tcpci_reg(tcpci_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl); - check_tcpci_reg(tcpci_emul, TCPC_REG_COMMAND, + check_tcpci_reg(ps8xxx_emul, TCPC_REG_ROLE_CTRL, exp_role_ctrl); + check_tcpci_reg(ps8xxx_emul, TCPC_REG_COMMAND, TCPC_REG_COMMAND_LOOK4CONNECTION); } @@ -482,8 +478,7 @@ ZTEST(ps8805, test_drp_toggle) static void test_ps8xxx_get_chip_info(uint16_t current_product_id) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); struct ec_response_pd_chip_info_v1 info; uint16_t vendor, product, device_id, fw_rev; @@ -495,10 +490,10 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id) device_id = 0x2; /* Arbitrary revision */ fw_rev = 0x32; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product); - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id); - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev); /* Test fail on reading FW revision */ i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV); @@ -519,18 +514,18 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id) /* Test fail on wrong vendor id */ vendor = 0x0; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); zassert_equal(EC_ERROR_UNKNOWN, ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info), NULL); /* Set correct vendor id */ vendor = PS8XXX_VENDOR_ID; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); /* Set firmware revision to 0 */ fw_rev = 0x0; - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev); /* * Test fail on firmware revision equals to 0 when getting chip info @@ -554,7 +549,7 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id) /* Set wrong vendor id */ vendor = 0; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); /* Test fail on vendor id mismatch on live device */ zassert_equal(EC_ERROR_UNKNOWN, @@ -572,11 +567,11 @@ static void test_ps8xxx_get_chip_info(uint16_t current_product_id) /* Set correct vendor id */ vendor = PS8XXX_VENDOR_ID; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); /* Set wrong product id */ product = 0; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product); /* Test fail on product id mismatch on live device */ zassert_equal(EC_ERROR_UNKNOWN, @@ -610,7 +605,6 @@ ZTEST(ps8815, test_ps8815_get_chip_info) ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); struct i2c_emul *p0_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_0); struct ec_response_pd_chip_info_v1 info; @@ -638,18 +632,18 @@ ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id) product = PS8805_PRODUCT_ID; /* Arbitrary revision */ fw_rev = 0x32; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product); - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev); /* Set correct power status for this test */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0); /* Init to allow access to "hidden" I2C ports */ zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); /* Set device id which requires fixing */ device_id = 0x1; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id); /* Test error on fixing device id because of fail chip revision read */ i2c_common_emul_set_read_fail_reg(p0_i2c_emul, @@ -702,7 +696,6 @@ ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id) ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); struct i2c_emul *p1_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_1); struct ec_response_pd_chip_info_v1 info; @@ -735,13 +728,13 @@ ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id) product = PS8815_PRODUCT_ID; /* Arbitrary revision */ fw_rev = 0x32; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_VENDOR_ID, vendor); - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_PRODUCT_ID, product); - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, fw_rev); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_VENDOR_ID, vendor); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_PRODUCT_ID, product); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, fw_rev); /* Set device id which requires fixing */ device_id = 0x1; - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_BCD_DEV, device_id); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_BCD_DEV, device_id); /* Test error on fixing device id because of fail hw revision read */ i2c_common_emul_set_read_fail_reg(p1_i2c_emul, @@ -793,7 +786,6 @@ ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id) ZTEST(ps8805, test_ps8805_gpio) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); struct i2c_emul *gpio_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_GPIO); uint8_t exp_ctrl, gpio_ctrl; @@ -851,9 +843,9 @@ ZTEST(ps8805, test_ps8805_gpio) }; /* Set arbitrary FW reg value != 0 for this test */ - tcpci_emul_set_reg(tcpci_emul, PS8XXX_REG_FW_REV, 0x31); + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); /* Set correct power status for this test */ - tcpci_emul_set_reg(tcpci_emul, TCPC_REG_POWER_STATUS, 0x0); + tcpci_emul_set_reg(ps8xxx_emul, TCPC_REG_POWER_STATUS, 0x0); /* Init to allow access to "hidden" I2C ports */ zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); @@ -929,9 +921,8 @@ ZTEST(ps8805, test_ps8805_gpio) static void test_ps8xxx_tcpci_init(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_init(tcpci_emul, USBC_PORT_C1); + test_tcpci_init(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_init) @@ -948,9 +939,8 @@ ZTEST(ps8815, test_tcpci_init) static void test_ps8xxx_tcpci_release(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_release(tcpci_emul, USBC_PORT_C1); + test_tcpci_release(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_release) @@ -967,9 +957,8 @@ ZTEST(ps8815, test_tcpci_release) static void test_ps8xxx_tcpci_get_cc(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_get_cc(tcpci_emul, USBC_PORT_C1); + test_tcpci_get_cc(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_get_cc) @@ -986,9 +975,8 @@ ZTEST(ps8815, test_tcpci_get_cc) static void test_ps8xxx_tcpci_set_cc(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_set_cc(tcpci_emul, USBC_PORT_C1); + test_tcpci_set_cc(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_set_cc) @@ -1005,9 +993,8 @@ ZTEST(ps8815, test_tcpci_set_cc) static void test_ps8xxx_tcpci_set_polarity(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_set_polarity(tcpci_emul, USBC_PORT_C1); + test_tcpci_set_polarity(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_set_polarity) @@ -1024,9 +1011,8 @@ ZTEST(ps8815, test_tcpci_set_polarity) static void test_ps8xxx_tcpci_set_vconn(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_set_vconn(tcpci_emul, USBC_PORT_C1); + test_tcpci_set_vconn(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_set_vconn) @@ -1043,9 +1029,8 @@ ZTEST(ps8815, test_tcpci_set_vconn) static void test_ps8xxx_tcpci_set_msg_header(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_set_msg_header(tcpci_emul, USBC_PORT_C1); + test_tcpci_set_msg_header(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_set_msg_header) @@ -1062,9 +1047,8 @@ ZTEST(ps8815, test_tcpci_set_msg_header) static void test_ps8xxx_tcpci_get_rx_message_raw(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_get_rx_message_raw(tcpci_emul, USBC_PORT_C1); + test_tcpci_get_rx_message_raw(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_get_rx_message_raw) @@ -1081,9 +1065,8 @@ ZTEST(ps8815, test_tcpci_get_rx_message_raw) static void test_ps8xxx_tcpci_transmit(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_transmit(tcpci_emul, USBC_PORT_C1); + test_tcpci_transmit(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_transmit) @@ -1100,9 +1083,8 @@ ZTEST(ps8815, test_tcpci_transmit) static void test_ps8xxx_tcpci_alert(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_alert(tcpci_emul, USBC_PORT_C1); + test_tcpci_alert(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_alert) @@ -1119,9 +1101,8 @@ ZTEST(ps8815, test_tcpci_alert) static void test_ps8xxx_tcpci_alert_rx_message(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_alert_rx_message(tcpci_emul, USBC_PORT_C1); + test_tcpci_alert_rx_message(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_alert_rx_message) @@ -1138,7 +1119,6 @@ ZTEST(ps8815, test_tcpci_alert_rx_message) static void test_ps8xxx_tcpci_low_power_mode(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); /* * PS8751/PS8815 has the auto sleep function that enters * low power mode on its own in ~2 seconds. Other chips @@ -1147,7 +1127,7 @@ static void test_ps8xxx_tcpci_low_power_mode(void) if (board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8751_PRODUCT_ID || board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID) return; - test_tcpci_low_power_mode(tcpci_emul, USBC_PORT_C1); + test_tcpci_low_power_mode(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_low_power_mode) @@ -1164,9 +1144,8 @@ ZTEST(ps8815, test_tcpci_low_power_mode) static void test_ps8xxx_tcpci_set_bist_mode(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - test_tcpci_set_bist_mode(tcpci_emul, USBC_PORT_C1); + test_tcpci_set_bist_mode(ps8xxx_emul, USBC_PORT_C1); } ZTEST(ps8805, test_tcpci_set_bist_mode) @@ -1183,8 +1162,7 @@ ZTEST(ps8815, test_tcpci_set_bist_mode) static void setup_no_fail_all(void) { const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); - const struct emul *tcpci_emul = ps8xxx_emul_get_tcpci(ps8xxx_emul); - struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(tcpci_emul); + struct i2c_emul *tcpci_i2c_emul = tcpci_emul_get_i2c_emul(ps8xxx_emul); struct i2c_emul *p0_i2c_emul = ps8xxx_emul_get_i2c_emul(ps8xxx_emul, PS8XXX_EMUL_PORT_0); struct i2c_emul *p1_i2c_emul = diff --git a/zephyr/test/drivers/src/stubs.c b/zephyr/test/drivers/src/stubs.c index 84ae387fb4..a547198217 100644 --- a/zephyr/test/drivers/src/stubs.c +++ b/zephyr/test/drivers/src/stubs.c @@ -133,8 +133,7 @@ struct tcpc_config_t tcpc_config[] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { .port = I2C_PORT_USB_C1, - .addr_flags = DT_REG_ADDR(DT_NODELABEL( - tcpci_ps8xxx_emul)), + .addr_flags = DT_REG_ADDR(DT_NODELABEL(ps8xxx_emul)), }, .drv = &ps8xxx_tcpm_drv, }, -- cgit v1.2.1 From 8ece0af813b46212a4458628cef944d521a6bd0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:00 -0600 Subject: chip/it83xx/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91260967c971ae1b3442e2d065c8a6b98cb05864 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729210 Reviewed-by: Jeremy Bettis --- chip/it83xx/fan.c | 53 +++++++++++++++++++++++++---------------------------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/chip/it83xx/fan.c b/chip/it83xx/fan.c index adb3985025..02acfbaf88 100644 --- a/chip/it83xx/fan.c +++ b/chip/it83xx/fan.c @@ -18,12 +18,12 @@ #include "task.h" #include "util.h" -#define TACH_EC_FREQ 8000000 -#define FAN_CTRL_BASED_MS 10 -#define FAN_CTRL_INTERVAL_MAX_MS 60 +#define TACH_EC_FREQ 8000000 +#define FAN_CTRL_BASED_MS 10 +#define FAN_CTRL_INTERVAL_MAX_MS 60 /* The sampling rate (fs) is FreqEC / 128 */ -#define TACH_DATA_VALID_TIMEOUT_MS (0xFFFF * 128 / (TACH_EC_FREQ / 1000)) +#define TACH_DATA_VALID_TIMEOUT_MS (0xFFFF * 128 / (TACH_EC_FREQ / 1000)) /* * Fan Speed (RPM) = 60 / (1/fs sec * {FnTMRR, FnTLRR} * P) @@ -37,25 +37,25 @@ #define TACH1_TO_RPM(pulse, raw) (raw * 120 / (pulse * 2)) enum fan_output_s { - FAN_DUTY_I = 0x01, - FAN_DUTY_R = 0x02, + FAN_DUTY_I = 0x01, + FAN_DUTY_R = 0x02, FAN_DUTY_OV = 0x03, FAN_DUTY_DONE = 0x04, }; struct fan_info { - unsigned int flags; - int fan_mode; - int fan_p; - int rpm_target; - int rpm_actual; - int tach_valid_ms; - int rpm_re; - int fan_ms; - int fan_ms_idx; - int startup_duty; + unsigned int flags; + int fan_mode; + int fan_p; + int rpm_target; + int rpm_actual; + int tach_valid_ms; + int rpm_re; + int fan_ms; + int fan_ms_idx; + int startup_duty; enum fan_status fan_sts; - int enabled; + int enabled; }; static struct fan_info fan_info_data[TACH_CH_COUNT]; @@ -72,7 +72,8 @@ static void fan_set_interval(int ch) tach_ch = tach_bind(ch); diff = ABS(fan_info_data[tach_ch].rpm_target - - fan_info_data[tach_ch].rpm_actual) / 100; + fan_info_data[tach_ch].rpm_actual) / + 100; fan_ms = FAN_CTRL_INTERVAL_MAX_MS; @@ -122,7 +123,7 @@ void fan_set_enabled(int ch, int enabled) disable_sleep(SLEEP_MASK_FAN); /* enable timer interrupt for fan control */ ext_timer_start(FAN_CTRL_EXT_TIMER, 1); - /* disable */ + /* disable */ } else { fan_set_duty(ch, 0); @@ -245,9 +246,8 @@ enum fan_status fan_get_status(int ch) int fan_is_stalled(int ch) { /* Must be enabled with non-zero target to stall */ - if (!fan_get_enabled(ch) || - fan_get_rpm_target(ch) == 0 || - !fan_get_duty(ch)) + if (!fan_get_enabled(ch) || fan_get_rpm_target(ch) == 0 || + !fan_get_duty(ch)) return 0; /* Check for stall condition */ @@ -273,8 +273,7 @@ static void fan_ctrl(int ch) tach_ch = tach_bind(ch); fan_info_data[tach_ch].fan_ms_idx += FAN_CTRL_BASED_MS; - if (fan_info_data[tach_ch].fan_ms_idx > - fan_info_data[tach_ch].fan_ms) { + if (fan_info_data[tach_ch].fan_ms_idx > fan_info_data[tach_ch].fan_ms) { fan_info_data[tach_ch].fan_ms_idx = 0x00; adjust = 1; } @@ -411,7 +410,7 @@ static void proc_tach(int ch) } else { fan_info_data[tach_ch].tach_valid_ms += FAN_CTRL_BASED_MS; if (fan_info_data[tach_ch].tach_valid_ms > - TACH_DATA_VALID_TIMEOUT_MS) + TACH_DATA_VALID_TIMEOUT_MS) fan_info_data[tach_ch].rpm_actual = 0; } } @@ -436,14 +435,12 @@ static void fan_init(void) enum tach_ch_sel tach_ch; for (ch = 0; ch < fan_get_count(); ch++) { - rpm_re = fan_tach[pwm_channels[FAN_CH(ch)].channel].rpm_re; fan_p = fan_tach[pwm_channels[FAN_CH(ch)].channel].fan_p; s_duty = fan_tach[pwm_channels[FAN_CH(ch)].channel].s_duty; tach_ch = tach_bind(FAN_CH(ch)); if (tach_ch < TACH_CH_COUNT) { - if (tach_ch == TACH_CH_TACH0B) { /* GPJ2 will select TACH0B as its alt. */ IT83XX_GPIO_GRC5 |= 0x01; @@ -473,6 +470,6 @@ static void fan_init(void) /* init external timer for fan control */ ext_timer_ms(FAN_CTRL_EXT_TIMER, EXT_PSR_32P768K_HZ, 0, 0, - FAN_CTRL_BASED_MS, 1, 0); + FAN_CTRL_BASED_MS, 1, 0); } DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_INIT_FAN); -- cgit v1.2.1 From ef59bc8f0f4702413fa77c0c50f198637d2c0044 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:03 -0600 Subject: board/fleex/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe0aaef75f77ecd99161d368cb74730c3d0e24d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728372 Reviewed-by: Jeremy Bettis --- board/fleex/board.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/board/fleex/board.h b/board/fleex/board.h index b097685449..a579924af7 100644 --- a/board/fleex/board.h +++ b/board/fleex/board.h @@ -33,8 +33,8 @@ #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2 /* Sensors */ -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT @@ -80,10 +80,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -94,18 +94,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From e122d0365ff690e3fde8cd151a930a86539fc9d5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:57 -0600 Subject: include/mock/timer_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If4e351d7270ae5abbf95c400e902be2bb7195299 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730364 Reviewed-by: Jeremy Bettis --- include/mock/timer_mock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mock/timer_mock.h b/include/mock/timer_mock.h index 04dc01e9ab..74644f6544 100644 --- a/include/mock/timer_mock.h +++ b/include/mock/timer_mock.h @@ -12,4 +12,4 @@ void set_time(timestamp_t now_); timestamp_t get_time(void); -#endif /* __MOCK_TIMER_MOCK_H */ +#endif /* __MOCK_TIMER_MOCK_H */ -- cgit v1.2.1 From 024a7710a30ba4c571e244f9d30ffea7cc185155 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:06 -0600 Subject: chip/max32660/flc_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d90dda7a57c06344fa1d143c45a29f1e6bf5ae5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729219 Reviewed-by: Jeremy Bettis --- chip/max32660/flc_regs.h | 253 +++++++++++++++++++++++++---------------------- 1 file changed, 134 insertions(+), 119 deletions(-) diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h index a484763c0b..54ce7ff0bd 100644 --- a/chip/max32660/flc_regs.h +++ b/chip/max32660/flc_regs.h @@ -43,14 +43,14 @@ extern "C" { * Structure type to access the FLC Registers. */ typedef struct { - __IO uint32_t addr; /**< \b 0x00:<\tt> FLC ADDR Register */ + __IO uint32_t addr; /**< \b 0x00:<\tt> FLC ADDR Register */ __IO uint32_t clkdiv; /**< \b 0x04:<\tt> FLC CLKDIV Register */ - __IO uint32_t cn; /**< \b 0x08:<\tt> FLC CN Register */ + __IO uint32_t cn; /**< \b 0x08:<\tt> FLC CN Register */ __R uint32_t rsv_0xc_0x23[6]; __IO uint32_t intr; /**< \b 0x024:<\tt> FLC INTR Register */ __R uint32_t rsv_0x28_0x2f[2]; __IO uint32_t data[4]; /**< \b 0x30:<\tt> FLC DATA Register */ - __O uint32_t acntl; /**< \b 0x40:<\tt> FLC ACNTL Register */ + __O uint32_t acntl; /**< \b 0x40:<\tt> FLC ACNTL Register */ } mxc_flc_regs_t; /* Register offsets for module FLC */ @@ -58,32 +58,32 @@ typedef struct { * FLC Peripheral Register Offsets from the FLC Base Peripheral * Address. */ -#define MXC_R_FLC_ADDR \ - ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_ADDR \ + ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: \ 0x0x000 */ -#define MXC_R_FLC_CLKDIV \ - ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_CLKDIV \ + ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: \ 0x0x004 */ -#define MXC_R_FLC_CN \ - ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_CN \ + ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: \ 0x0x008 */ -#define MXC_R_FLC_INTR \ - ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_INTR \ + ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: \ 0x0x024 */ -#define MXC_R_FLC_DATA \ - ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_DATA \ + ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: \ 0x0x030 */ -#define MXC_R_FLC_ACNTL \ - ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: \ +#define MXC_R_FLC_ACNTL \ + ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: \ 0x0x040 */ /** * Flash Write Address. */ #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ -#define MXC_F_FLC_ADDR_ADDR \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ +#define MXC_F_FLC_ADDR_ADDR \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR \ + Mask */ /** * Flash Clock Divide. The clock (PLL0) is divided by this value to @@ -91,177 +91,191 @@ typedef struct { */ #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ #define MXC_F_FLC_CLKDIV_CLKDIV \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV \ + Mask */ /** * Flash Control Register. */ #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ -#define MXC_F_FLC_CN_WR \ +#define MXC_F_FLC_CN_WR \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ -#define MXC_V_FLC_CN_WR_COMPLETE \ - ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value \ +#define MXC_V_FLC_CN_WR_COMPLETE \ + ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value \ */ -#define MXC_S_FLC_CN_WR_COMPLETE \ - (MXC_V_FLC_CN_WR_COMPLETE \ - << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */ +#define MXC_S_FLC_CN_WR_COMPLETE \ + (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE \ + Setting */ #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */ -#define MXC_S_FLC_CN_WR_START \ - (MXC_V_FLC_CN_WR_START \ - << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */ +#define MXC_S_FLC_CN_WR_START \ + (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START \ + Setting */ #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ -#define MXC_F_FLC_CN_ME \ +#define MXC_F_FLC_CN_ME \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ -#define MXC_F_FLC_CN_PGE \ +#define MXC_F_FLC_CN_PGE \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */ -#define MXC_F_FLC_CN_WDTH \ +#define MXC_F_FLC_CN_WDTH \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ -#define MXC_V_FLC_CN_WDTH_SIZE128 \ +#define MXC_V_FLC_CN_WDTH_SIZE128 \ ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ -#define MXC_S_FLC_CN_WDTH_SIZE128 \ - (MXC_V_FLC_CN_WDTH_SIZE128 \ - << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */ -#define MXC_V_FLC_CN_WDTH_SIZE32 \ - ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \ +#define MXC_S_FLC_CN_WDTH_SIZE128 \ + (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< \ + CN_WDTH_SIZE128 \ + Setting */ +#define MXC_V_FLC_CN_WDTH_SIZE32 \ + ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \ */ -#define MXC_S_FLC_CN_WDTH_SIZE32 \ - (MXC_V_FLC_CN_WDTH_SIZE32 \ - << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */ +#define MXC_S_FLC_CN_WDTH_SIZE32 \ + (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< \ + CN_WDTH_SIZE32 \ + Setting */ #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ #define MXC_F_FLC_CN_ERASE_CODE \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ -#define MXC_V_FLC_CN_ERASE_CODE_NOP \ + ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE \ + Mask */ +#define MXC_V_FLC_CN_ERASE_CODE_NOP \ ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ -#define MXC_S_FLC_CN_ERASE_CODE_NOP \ - (MXC_V_FLC_CN_ERASE_CODE_NOP \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ -#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ +#define MXC_S_FLC_CN_ERASE_CODE_NOP \ + (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< \ + CN_ERASE_CODE_NOP \ + Setting \ + */ +#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ -#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \ - (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting \ +#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \ + (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ + << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting \ */ -#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ +#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ -#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL \ - (MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ - << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting \ +#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL \ + (MXC_V_FLC_CN_ERASE_CODE_ERASEALL \ + << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting \ */ #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ -#define MXC_F_FLC_CN_PEND \ +#define MXC_F_FLC_CN_PEND \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ -#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ -#define MXC_S_FLC_CN_PEND_IDLE \ - (MXC_V_FLC_CN_PEND_IDLE \ - << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */ +#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ +#define MXC_S_FLC_CN_PEND_IDLE \ + (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE \ + Setting */ #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */ -#define MXC_S_FLC_CN_PEND_BUSY \ - (MXC_V_FLC_CN_PEND_BUSY \ - << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */ +#define MXC_S_FLC_CN_PEND_BUSY \ + (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY \ + Setting */ #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */ -#define MXC_F_FLC_CN_LVE \ +#define MXC_F_FLC_CN_LVE \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */ -#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ +#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ #define MXC_S_FLC_CN_LVE_DIS \ - (MXC_V_FLC_CN_LVE_DIS \ - << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */ + (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting \ + */ #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */ -#define MXC_S_FLC_CN_LVE_EN \ - (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting \ +#define MXC_S_FLC_CN_LVE_EN \ + (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting \ */ #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */ -#define MXC_F_FLC_CN_BRST \ +#define MXC_F_FLC_CN_BRST \ ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ -#define MXC_V_FLC_CN_BRST_DISABLE \ +#define MXC_V_FLC_CN_BRST_DISABLE \ ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ -#define MXC_S_FLC_CN_BRST_DISABLE \ - (MXC_V_FLC_CN_BRST_DISABLE \ - << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */ -#define MXC_V_FLC_CN_BRST_ENABLE \ - ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \ +#define MXC_S_FLC_CN_BRST_DISABLE \ + (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< \ + CN_BRST_DISABLE \ + Setting */ +#define MXC_V_FLC_CN_BRST_ENABLE \ + ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \ */ -#define MXC_S_FLC_CN_BRST_ENABLE \ - (MXC_V_FLC_CN_BRST_ENABLE \ - << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */ +#define MXC_S_FLC_CN_BRST_ENABLE \ + (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< \ + CN_BRST_ENABLE \ + Setting */ #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ -#define MXC_F_FLC_CN_UNLOCK \ +#define MXC_F_FLC_CN_UNLOCK \ ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ -#define MXC_V_FLC_CN_UNLOCK_UNLOCKED \ +#define MXC_V_FLC_CN_UNLOCK_UNLOCKED \ ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ -#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ - (MXC_V_FLC_CN_UNLOCK_UNLOCKED \ - << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ +#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ + (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< \ + CN_UNLOCK_UNLOCKED \ + Setting \ + */ /** * Flash Interrupt Register. */ #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ -#define MXC_F_FLC_INTR_DONE \ +#define MXC_F_FLC_INTR_DONE \ ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ -#define MXC_V_FLC_INTR_DONE_INACTIVE \ +#define MXC_V_FLC_INTR_DONE_INACTIVE \ ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ -#define MXC_S_FLC_INTR_DONE_INACTIVE \ - (MXC_V_FLC_INTR_DONE_INACTIVE \ - << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ -#define MXC_V_FLC_INTR_DONE_PENDING \ +#define MXC_S_FLC_INTR_DONE_INACTIVE \ + (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< \ + INTR_DONE_INACTIVE \ + Setting \ + */ +#define MXC_V_FLC_INTR_DONE_PENDING \ ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ -#define MXC_S_FLC_INTR_DONE_PENDING \ - (MXC_V_FLC_INTR_DONE_PENDING \ - << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ +#define MXC_S_FLC_INTR_DONE_PENDING \ + (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< \ + INTR_DONE_PENDING \ + Setting */ #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ -#define MXC_F_FLC_INTR_AF \ +#define MXC_F_FLC_INTR_AF \ ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ -#define MXC_V_FLC_INTR_AF_NOERROR \ +#define MXC_V_FLC_INTR_AF_NOERROR \ ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ -#define MXC_S_FLC_INTR_AF_NOERROR \ - (MXC_V_FLC_INTR_AF_NOERROR \ - << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */ +#define MXC_S_FLC_INTR_AF_NOERROR \ + (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< \ + INTR_AF_NOERROR \ + Setting */ #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ -#define MXC_S_FLC_INTR_AF_ERROR \ - (MXC_V_FLC_INTR_AF_ERROR \ - << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */ +#define MXC_S_FLC_INTR_AF_ERROR \ + (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR \ + Setting */ #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ #define MXC_F_FLC_INTR_DONEIE \ - ((uint32_t)( \ - 0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ -#define MXC_V_FLC_INTR_DONEIE_DISABLE \ + ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask \ + */ +#define MXC_V_FLC_INTR_DONEIE_DISABLE \ ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_DISABLE \ - (MXC_V_FLC_INTR_DONEIE_DISABLE \ - << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */ -#define MXC_V_FLC_INTR_DONEIE_ENABLE \ +#define MXC_S_FLC_INTR_DONEIE_DISABLE \ + (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< \ + INTR_DONEIE_DISABLE \ + Setting \ + */ +#define MXC_V_FLC_INTR_DONEIE_ENABLE \ ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_ENABLE \ - (MXC_V_FLC_INTR_DONEIE_ENABLE \ - << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */ +#define MXC_S_FLC_INTR_DONEIE_ENABLE \ + (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< \ + INTR_DONEIE_ENABLE \ + Setting \ + */ #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ -#define MXC_F_FLC_INTR_AFIE \ +#define MXC_F_FLC_INTR_AFIE \ ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ /** * Flash Write Data. */ #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ -#define MXC_F_FLC_DATA_DATA \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ +#define MXC_F_FLC_DATA_DATA \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA \ + Mask */ /** * Access Control Register. Writing the ACNTL register with the @@ -273,8 +287,9 @@ typedef struct { */ #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */ #define MXC_F_FLC_ACNTL_ACNTL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< \ + ACNTL_ACNTL \ + Mask */ #ifdef __cplusplus } -- cgit v1.2.1 From 36dbb3ebd0a9443e9536899e08fca5c64fcccbfb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:22 -0600 Subject: driver/charger/sy21612.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iceca83a9549db0e54ac1b44ffac40068d99b0f8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729943 Reviewed-by: Jeremy Bettis --- driver/charger/sy21612.h | 152 +++++++++++++++++++++++------------------------ 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/driver/charger/sy21612.h b/driver/charger/sy21612.h index befb8e6a35..d3a3b8a1c3 100644 --- a/driver/charger/sy21612.h +++ b/driver/charger/sy21612.h @@ -11,7 +11,7 @@ #include "gpio.h" #ifndef SY21612_ADDR_FLAGS -#define SY21612_ADDR_FLAGS 0x71 +#define SY21612_ADDR_FLAGS 0x71 #endif enum sy21612_switching_freq { @@ -40,94 +40,94 @@ enum sy21612_vbus_adj { SY21612_VBUS_5, }; -#define SY21612_CTRL1 0x00 -#define SY21612_CTRL1_REG_EN BIT(7) -#define SY21612_CTRL1_LOW_BAT_MASK (7 << 4) -#define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4) -#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4) -#define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4) -#define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4) -#define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4) -#define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4) -#define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4) -#define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4) -#define SY21612_CTRL1_ADC_EN BIT(3) -#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2) -#define SY21612_CTRL1_VBUS_NDISCHG BIT(1) - -#define SY21612_CTRL2 0x01 -#define SY21612_CTRL2_FREQ_MASK (3 << 6) -#define SY21612_CTRL2_FREQ_SHIFT 6 -#define SY21612_CTRL2_FREQ_250K (0 << 6) -#define SY21612_CTRL2_FREQ_500K BIT(6) -#define SY21612_CTRL2_FREQ_750K (2 << 6) -#define SY21612_CTRL2_FREQ_1M (3 << 6) -#define SY21612_CTRL2_VBUS_MASK (7 << 3) -#define SY21612_CTRL2_VBUS_SHIFT 3 -#define SY21612_CTRL2_VBUS_5V (2 << 3) -#define SY21612_CTRL2_VBUS_7V (3 << 3) -#define SY21612_CTRL2_VBUS_9V (4 << 3) -#define SY21612_CTRL2_VBUS_12V (5 << 3) -#define SY21612_CTRL2_VBUS_15V (6 << 3) -#define SY21612_CTRL2_VBUS_20V (7 << 3) -#define SY21612_CTRL2_VBUS_ADJ_MASK 7 +#define SY21612_CTRL1 0x00 +#define SY21612_CTRL1_REG_EN BIT(7) +#define SY21612_CTRL1_LOW_BAT_MASK (7 << 4) +#define SY21612_CTRL1_LOW_BAT_10_2V (0 << 4) +#define SY21612_CTRL1_LOW_BAT_10_7V BIT(4) +#define SY21612_CTRL1_LOW_BAT_11_2V (2 << 4) +#define SY21612_CTRL1_LOW_BAT_11_7V (3 << 4) +#define SY21612_CTRL1_LOW_BAT_22_0V (4 << 4) +#define SY21612_CTRL1_LOW_BAT_22_5V (5 << 4) +#define SY21612_CTRL1_LOW_BAT_23_0V (6 << 4) +#define SY21612_CTRL1_LOW_BAT_23_5V (7 << 4) +#define SY21612_CTRL1_ADC_EN BIT(3) +#define SY21612_CTRL1_ADC_AUTO_MODE BIT(2) +#define SY21612_CTRL1_VBUS_NDISCHG BIT(1) + +#define SY21612_CTRL2 0x01 +#define SY21612_CTRL2_FREQ_MASK (3 << 6) +#define SY21612_CTRL2_FREQ_SHIFT 6 +#define SY21612_CTRL2_FREQ_250K (0 << 6) +#define SY21612_CTRL2_FREQ_500K BIT(6) +#define SY21612_CTRL2_FREQ_750K (2 << 6) +#define SY21612_CTRL2_FREQ_1M (3 << 6) +#define SY21612_CTRL2_VBUS_MASK (7 << 3) +#define SY21612_CTRL2_VBUS_SHIFT 3 +#define SY21612_CTRL2_VBUS_5V (2 << 3) +#define SY21612_CTRL2_VBUS_7V (3 << 3) +#define SY21612_CTRL2_VBUS_9V (4 << 3) +#define SY21612_CTRL2_VBUS_12V (5 << 3) +#define SY21612_CTRL2_VBUS_15V (6 << 3) +#define SY21612_CTRL2_VBUS_20V (7 << 3) +#define SY21612_CTRL2_VBUS_ADJ_MASK 7 #define SY21612_CTRL2_VBUS_ADJ_SHIFT 0 -#define SY21612_CTRL2_VBUS_ADJ_M2_5 0 +#define SY21612_CTRL2_VBUS_ADJ_M2_5 0 #define SY21612_CTRL2_VBUS_ADJ_M1_25 1 -#define SY21612_CTRL2_VBUS_ADJ_0 2 -#define SY21612_CTRL2_VBUS_ADJ_1_25 3 -#define SY21612_CTRL2_VBUS_ADJ_2_5 4 -#define SY21612_CTRL2_VBUS_ADJ_3_75 5 -#define SY21612_CTRL2_VBUS_ADJ_5 6 - -#define SY21612_PROT1 0x02 -#define SY21612_PROT1_I_THRESH_MASK (7 << 5) -#define SY21612_PROT1_I_THRESH_18MV (0 << 5) -#define SY21612_PROT1_I_THRESH_22MV BIT(5) -#define SY21612_PROT1_I_THRESH_27MV (2 << 5) -#define SY21612_PROT1_I_THRESH_31MV (3 << 5) -#define SY21612_PROT1_I_THRESH_36MV (4 << 5) -#define SY21612_PROT1_I_THRESH_45MV (5 << 5) -#define SY21612_PROT1_I_THRESH_54MV (6 << 5) -#define SY21612_PROT1_I_THRESH_64MV (7 << 5) +#define SY21612_CTRL2_VBUS_ADJ_0 2 +#define SY21612_CTRL2_VBUS_ADJ_1_25 3 +#define SY21612_CTRL2_VBUS_ADJ_2_5 4 +#define SY21612_CTRL2_VBUS_ADJ_3_75 5 +#define SY21612_CTRL2_VBUS_ADJ_5 6 + +#define SY21612_PROT1 0x02 +#define SY21612_PROT1_I_THRESH_MASK (7 << 5) +#define SY21612_PROT1_I_THRESH_18MV (0 << 5) +#define SY21612_PROT1_I_THRESH_22MV BIT(5) +#define SY21612_PROT1_I_THRESH_27MV (2 << 5) +#define SY21612_PROT1_I_THRESH_31MV (3 << 5) +#define SY21612_PROT1_I_THRESH_36MV (4 << 5) +#define SY21612_PROT1_I_THRESH_45MV (5 << 5) +#define SY21612_PROT1_I_THRESH_54MV (6 << 5) +#define SY21612_PROT1_I_THRESH_64MV (7 << 5) #define SY21612_PROT1_OVP_THRESH_MASK (3 << 3) -#define SY21612_PROT1_OVP_THRESH_110 (0 << 3) -#define SY21612_PROT1_OVP_THRESH_115 BIT(3) -#define SY21612_PROT1_OVP_THRESH_120 (2 << 3) -#define SY21612_PROT1_OVP_THRESH_125 (3 << 3) +#define SY21612_PROT1_OVP_THRESH_110 (0 << 3) +#define SY21612_PROT1_OVP_THRESH_115 BIT(3) +#define SY21612_PROT1_OVP_THRESH_120 (2 << 3) +#define SY21612_PROT1_OVP_THRESH_125 (3 << 3) #define SY21612_PROT1_UVP_THRESH_MASK (3 << 1) -#define SY21612_PROT1_UVP_THRESH_50 (0 << 1) -#define SY21612_PROT1_UVP_THRESH_60 BIT(1) -#define SY21612_PROT1_UVP_THRESH_70 (2 << 1) -#define SY21612_PROT1_UVP_THRESH_80 (3 << 1) - -#define SY21612_PROT2 0x03 -#define SY21612_PROT2_I_LIMIT_MASK (3 << 6) -#define SY21612_PROT2_I_LIMIT_6A (0 << 6) -#define SY21612_PROT2_I_LIMIT_8A (2 << 6) -#define SY21612_PROT2_I_LIMIT_10A (3 << 6) +#define SY21612_PROT1_UVP_THRESH_50 (0 << 1) +#define SY21612_PROT1_UVP_THRESH_60 BIT(1) +#define SY21612_PROT1_UVP_THRESH_70 (2 << 1) +#define SY21612_PROT1_UVP_THRESH_80 (3 << 1) + +#define SY21612_PROT2 0x03 +#define SY21612_PROT2_I_LIMIT_MASK (3 << 6) +#define SY21612_PROT2_I_LIMIT_6A (0 << 6) +#define SY21612_PROT2_I_LIMIT_8A (2 << 6) +#define SY21612_PROT2_I_LIMIT_10A (3 << 6) #define SY21612_PROT2_OCP_AUTORECOVER BIT(5) #define SY21612_PROT2_UVP_AUTORECOVER BIT(4) #define SY21612_PROT2_OTP_AUTORECOVER BIT(3) -#define SY21612_PROT2_SINK_MODE BIT(2) +#define SY21612_PROT2_SINK_MODE BIT(2) -#define SY21612_STATE 0x04 -#define SY21612_STATE_POWER_GOOD BIT(7) -#define SY21612_STATE_VBAT_LT_VBUS BIT(6) -#define SY21612_STATE_VBAT_LOW BIT(5) +#define SY21612_STATE 0x04 +#define SY21612_STATE_POWER_GOOD BIT(7) +#define SY21612_STATE_VBAT_LT_VBUS BIT(6) +#define SY21612_STATE_VBAT_LOW BIT(5) -#define SY21612_INT 0x05 -#define SY21612_INT_ADC_READY BIT(7) -#define SY21612_INT_VBUS_OCP BIT(6) -#define SY21612_INT_INDUCTOR_OCP BIT(5) -#define SY21612_INT_UVP BIT(4) -#define SY21612_INT_OTP BIT(3) +#define SY21612_INT 0x05 +#define SY21612_INT_ADC_READY BIT(7) +#define SY21612_INT_VBUS_OCP BIT(6) +#define SY21612_INT_INDUCTOR_OCP BIT(5) +#define SY21612_INT_UVP BIT(4) +#define SY21612_INT_OTP BIT(3) /* Battery voltage range: 0 ~ 25V */ -#define SY21612_VBAT_VOLT 0x06 +#define SY21612_VBAT_VOLT 0x06 /* VBUS voltage range: 0 ~ 25V */ -#define SY21612_VBUS_VOLT 0x07 +#define SY21612_VBUS_VOLT 0x07 /* Output current sense voltage range 0 ~ 67mV */ #define SY21612_VBUS_CURRENT 0x08 -- cgit v1.2.1 From 5ffc1d9e8bf15b454069df3dbbad62d6bdfbc149 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:55 -0600 Subject: util/ec_parse_panicinfo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7e8e15ef61c3548f6362e1bd86b0528735e47fa7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730613 Reviewed-by: Jeremy Bettis --- util/ec_parse_panicinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/ec_parse_panicinfo.c b/util/ec_parse_panicinfo.c index 3a2da4590a..1865757b79 100644 --- a/util/ec_parse_panicinfo.c +++ b/util/ec_parse_panicinfo.c @@ -20,7 +20,7 @@ int main(int argc, char *argv[]) size_t size = 0; size_t read; - BUILD_ASSERT(sizeof(pdata) > sizeof(struct panic_data)*2); + BUILD_ASSERT(sizeof(pdata) > sizeof(struct panic_data) * 2); /* * Provide a minimal help message. @@ -36,7 +36,7 @@ int main(int argc, char *argv[]) } while (1) { - read = fread(&pdata[size], 1, sizeof(pdata)-size, stdin); + read = fread(&pdata[size], 1, sizeof(pdata) - size, stdin); if (read < 0) { fprintf(stderr, "Cannot read panicinfo from stdin.\n"); return 1; -- cgit v1.2.1 From da2bfb64867b94b78e9b57bb226fb7ba95e613cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:00 -0600 Subject: chip/mt_scp/rv32i_common/memmap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c20ba6644990b266af43fe0893aceca45ce61a6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729371 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/memmap.c | 71 ++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 38 deletions(-) diff --git a/chip/mt_scp/rv32i_common/memmap.c b/chip/mt_scp/rv32i_common/memmap.c index a666bb23d7..1905431b88 100644 --- a/chip/mt_scp/rv32i_common/memmap.c +++ b/chip/mt_scp/rv32i_common/memmap.c @@ -33,53 +33,48 @@ * 0xf000_0000 0x6000_0000 */ -#define REMAP_ADDR_SHIFT 28 -#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1) -#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT) +#define REMAP_ADDR_SHIFT 28 +#define REMAP_ADDR_LSB_MASK (BIT(REMAP_ADDR_SHIFT) - 1) +#define REMAP_ADDR_MSB_MASK ((~0) << REMAP_ADDR_SHIFT) #define MAP_INVALID 0xff static const uint8_t addr_map[16] = { - MAP_INVALID, /* SRAM */ - 0x5, /* ext_addr_0x1 */ - 0x7, /* ext_addr_0x2 */ - MAP_INVALID, /* no ext_addr_0x3 */ - - MAP_INVALID, /* no ext_addr_0x4 */ - 0x0, /* ext_addr_0x5 */ - 0x1, /* ext_addr_0x6 */ - 0xa, /* ext_addr_0x7 */ - - MAP_INVALID, /* no ext_addr_0x8 */ - 0x8, /* ext_addr_0x9 */ - 0x9, /* ext_addr_0xa */ - MAP_INVALID, /* no ext_addr_0xb */ - - 0x8, /* ext_addr_0xc */ - 0x2, /* ext_addr_0xd */ - 0x3, /* ext_addr_0xe */ - 0x6, /* ext_addr_0xf */ + MAP_INVALID, /* SRAM */ + 0x5, /* ext_addr_0x1 */ + 0x7, /* ext_addr_0x2 */ + MAP_INVALID, /* no ext_addr_0x3 */ + + MAP_INVALID, /* no ext_addr_0x4 */ + 0x0, /* ext_addr_0x5 */ + 0x1, /* ext_addr_0x6 */ + 0xa, /* ext_addr_0x7 */ + + MAP_INVALID, /* no ext_addr_0x8 */ + 0x8, /* ext_addr_0x9 */ + 0x9, /* ext_addr_0xa */ + MAP_INVALID, /* no ext_addr_0xb */ + + 0x8, /* ext_addr_0xc */ + 0x2, /* ext_addr_0xd */ + 0x3, /* ext_addr_0xe */ + 0x6, /* ext_addr_0xf */ }; void memmap_init(void) { - SCP_R_REMAP_0X0123 = - (uint32_t)addr_map[0x1] << 8 | - (uint32_t)addr_map[0x2] << 16; + SCP_R_REMAP_0X0123 = (uint32_t)addr_map[0x1] << 8 | + (uint32_t)addr_map[0x2] << 16; - SCP_R_REMAP_0X4567 = - (uint32_t)addr_map[0x5] << 8 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x7] << 24; + SCP_R_REMAP_0X4567 = (uint32_t)addr_map[0x5] << 8 | + (uint32_t)addr_map[0x6] << 16 | + (uint32_t)addr_map[0x7] << 24; - SCP_R_REMAP_0X89AB = - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0xa] << 16; + SCP_R_REMAP_0X89AB = (uint32_t)addr_map[0x9] << 8 | + (uint32_t)addr_map[0xa] << 16; SCP_R_REMAP_0XCDEF = - (uint32_t)addr_map[0xc] | - (uint32_t)addr_map[0xd] << 8 | - (uint32_t)addr_map[0xe] << 16 | - (uint32_t)addr_map[0xf] << 24; + (uint32_t)addr_map[0xc] | (uint32_t)addr_map[0xd] << 8 | + (uint32_t)addr_map[0xe] << 16 | (uint32_t)addr_map[0xf] << 24; cache_init(); } @@ -94,7 +89,7 @@ int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) continue; *scp_addr = (ap_addr & REMAP_ADDR_LSB_MASK) | - (i << REMAP_ADDR_SHIFT); + (i << REMAP_ADDR_SHIFT); return EC_SUCCESS; } @@ -109,6 +104,6 @@ int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) return EC_ERROR_INVAL; *ap_addr = (scp_addr & REMAP_ADDR_LSB_MASK) | - (addr_map[i] << REMAP_ADDR_SHIFT); + (addr_map[i] << REMAP_ADDR_SHIFT); return EC_SUCCESS; } -- cgit v1.2.1 From 3163d8ca9aa7a0a5cbecf359190a849f33bd4cef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:53 -0600 Subject: chip/mt_scp/mt818x/ipi_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3bedcfdaaabfc228372a00bd5f0b4c0875ad4a08 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729339 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/ipi_chip.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/mt_scp/mt818x/ipi_chip.h b/chip/mt_scp/mt818x/ipi_chip.h index 03b5572497..46f2d842a6 100644 --- a/chip/mt_scp/mt818x/ipi_chip.h +++ b/chip/mt_scp/mt818x/ipi_chip.h @@ -97,15 +97,15 @@ extern int *ipi_wakeup_table[]; * handler: The IPI handler function * is_wakeup_src: Declare IPI ID as a wake-up source or not */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int tmp1[_id < IPI_COUNT ? 1 : -1]; \ +#define DECLARE_IPI(_id, handler, is_wakeup_src) \ + struct ipi_num_check##_id { \ + int tmp1[_id < IPI_COUNT ? 1 : -1]; \ int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ + }; \ + void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ + { \ + handler(id, buf, len); \ + } \ const int __keep IPI_WAKEUP(_id) = is_wakeup_src #endif /* __CROS_EC_IPI_CHIP_H */ -- cgit v1.2.1 From f1e7b095784650509cc0d8444d3d4582e56ce4c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:15 -0600 Subject: driver/usb_mux/anx7440.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ica418f1c77a848db0996e674e3b86b23d12a9855 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730157 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx7440.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/driver/usb_mux/anx7440.c b/driver/usb_mux/anx7440.c index 89e593217d..2915d4bd3c 100644 --- a/driver/usb_mux/anx7440.c +++ b/driver/usb_mux/anx7440.c @@ -13,17 +13,16 @@ #include "usb_mux.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -static inline int anx7440_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7440_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7440_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7440_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } -- cgit v1.2.1 From 723d875fd093f4392e73009cac3afaa54f85e0a3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:47 -0600 Subject: common/base32.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ecfcd0b4a83b5feb010e80af70231807716899f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729607 Reviewed-by: Jeremy Bettis --- common/base32.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/common/base32.c b/common/base32.c index a6be8409b1..aaadad14ce 100644 --- a/common/base32.c +++ b/common/base32.c @@ -9,15 +9,13 @@ #include "base32.h" #include "util.h" -static const unsigned char crc5_table1[] = { - 0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F, 0x0D, 0x03, - 0x0B, 0x05, 0x17, 0x19, 0x1A, 0x14, 0x06, 0x08 -}; +static const unsigned char crc5_table1[] = { 0x00, 0x0E, 0x1C, 0x12, 0x11, 0x1F, + 0x0D, 0x03, 0x0B, 0x05, 0x17, 0x19, + 0x1A, 0x14, 0x06, 0x08 }; -static const unsigned char crc5_table0[] = { - 0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C, 0x0F, 0x19, - 0x14, 0x02, 0x11, 0x07, 0x1E, 0x08, 0x1B, 0x0D -}; +static const unsigned char crc5_table0[] = { 0x00, 0x16, 0x05, 0x13, 0x0A, 0x1C, + 0x0F, 0x19, 0x14, 0x02, 0x11, 0x07, + 0x1E, 0x08, 0x1B, 0x0D }; uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc) { @@ -46,9 +44,8 @@ static int decode_sym(int sym) return -1; } -int base32_encode(char *dest, int destlen_chars, - const void *srcbits, int srclen_bits, - int add_crc_every) +int base32_encode(char *dest, int destlen_chars, const void *srcbits, + int srclen_bits, int add_crc_every) { const uint8_t *src = srcbits; int destlen_needed; @@ -59,14 +56,14 @@ int base32_encode(char *dest, int destlen_chars, *dest = 0; /* Make sure destination is big enough */ - destlen_needed = (srclen_bits + 4) / 5; /* Symbols before adding CRC */ + destlen_needed = (srclen_bits + 4) / 5; /* Symbols before adding CRC */ if (add_crc_every) { /* Must be an exact number of groups to add CRC */ if (destlen_needed % add_crc_every) return EC_ERROR_INVAL; destlen_needed += destlen_needed / add_crc_every; } - destlen_needed++; /* For terminating null */ + destlen_needed++; /* For terminating null */ if (destlen_chars < destlen_needed) return EC_ERROR_INVAL; @@ -124,7 +121,7 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src, sym = decode_sym(*src); if (sym < 0) - return -1; /* Bad input symbol */ + return -1; /* Bad input symbol */ /* Check CRC if needed */ if (crc_after_every) { @@ -155,7 +152,7 @@ int base32_decode(uint8_t *dest, int destlen_bits, const char *src, dbits = 8 - (out_bits & 7); b = MIN(dbits, sbits); if (dbits == 8) - dest[out_bits / 8] = 0; /* Starting a new byte */ + dest[out_bits / 8] = 0; /* Starting a new byte */ dest[out_bits / 8] |= (sym << (dbits - b)) >> (sbits - b); out_bits += b; sbits -= b; -- cgit v1.2.1 From ec4c53d121e335bac31caf4c3a39056ab9fdb54c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:27 -0600 Subject: board/panqueque/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16aeb82ad93f43f13fe0a5b6174fc269f24d4741 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728811 Reviewed-by: Jeremy Bettis --- board/panqueque/board.c | 82 ++++++++++++++++++++++--------------------------- 1 file changed, 37 insertions(+), 45 deletions(-) diff --git a/board/panqueque/board.c b/board/panqueque/board.c index cea834c75e..c134105b1b 100644 --- a/board/panqueque/board.c +++ b/board/panqueque/board.c @@ -28,8 +28,8 @@ #include "usb_tc_sm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define QUICHE_PD_DEBUG_LVL 1 @@ -84,25 +84,25 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal) * signals is driven by USB/MST hub power sequencing requirements. */ const struct power_seq board_power_seq[] = { - {GPIO_EN_AC_JACK, 1, 20}, - {GPIO_EC_DFU_MUX_CTRL, 0, 0}, - {GPIO_EN_PP5000_A, 1, 31}, - {GPIO_MST_LP_CTL_L, 1, 0}, - {GPIO_EN_PP3300_B, 1, 1}, - {GPIO_EN_PP1100_A, 1, 100+30}, - {GPIO_EN_BB, 1, 30}, - {GPIO_EN_PP1050_A, 1, 30}, - {GPIO_EN_PP1200_A, 1, 20}, - {GPIO_EN_PP5000_C, 1, 20}, - {GPIO_EN_PP5000_HSPORT, 1, 31}, - {GPIO_EN_DP_SINK, 1, 80}, - {GPIO_MST_RST_L, 1, 61}, - {GPIO_EC_HUB2_RESET_L, 1, 41}, - {GPIO_EC_HUB3_RESET_L, 1, 33}, - {GPIO_DP_SINK_RESET, 1, 100}, - {GPIO_USBC_UF_RESET_L, 1, 33}, - {GPIO_DEMUX_DP_HDMI_PD_N, 1, 10}, - {GPIO_DEMUX_DP_HDMI_MODE, 1, 5}, + { GPIO_EN_AC_JACK, 1, 20 }, + { GPIO_EC_DFU_MUX_CTRL, 0, 0 }, + { GPIO_EN_PP5000_A, 1, 31 }, + { GPIO_MST_LP_CTL_L, 1, 0 }, + { GPIO_EN_PP3300_B, 1, 1 }, + { GPIO_EN_PP1100_A, 1, 100 + 30 }, + { GPIO_EN_BB, 1, 30 }, + { GPIO_EN_PP1050_A, 1, 30 }, + { GPIO_EN_PP1200_A, 1, 20 }, + { GPIO_EN_PP5000_C, 1, 20 }, + { GPIO_EN_PP5000_HSPORT, 1, 31 }, + { GPIO_EN_DP_SINK, 1, 80 }, + { GPIO_MST_RST_L, 1, 61 }, + { GPIO_EC_HUB2_RESET_L, 1, 41 }, + { GPIO_EC_HUB3_RESET_L, 1, 33 }, + { GPIO_DP_SINK_RESET, 1, 100 }, + { GPIO_USBC_UF_RESET_L, 1, 33 }, + { GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 }, + { GPIO_DEMUX_DP_HDMI_MODE, 1, 5 }, }; const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); @@ -110,13 +110,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Plugable"), - [USB_STR_PRODUCT] = USB_STRING_DESC("UC-MSTHDC"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Plugable"), + [USB_STR_PRODUCT] = USB_STRING_DESC("UC-MSTHDC"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -135,8 +135,7 @@ struct ppc_config_t ppc_chips[] = { * PS8802 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8822_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; @@ -167,16 +166,12 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_HOST] = { - .i2c_port = I2C_PORT_I2C1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_USB3] = { - .i2c_port = I2C_PORT_I2C3, - .i2c_addr_flags = SN5S330_ADDR1_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3, + .i2c_addr_flags = SN5S330_ADDR1_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -284,14 +279,13 @@ static void board_usb_tc_disconnect(void) if (port == USB_PD_PORT_HOST) gpio_set_level(GPIO_UFP_PLUG_DET, 1); } -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect,\ +DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, HOOK_PRIO_DEFAULT); #endif /* SECTION_IS_RW */ static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -356,6 +350,4 @@ static int command_dplane(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dplane, command_dplane, - "<2 | 4>", - "MST lane control."); +DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control."); -- cgit v1.2.1 From 3f4de60e52598d85ed83b063707edd8bfacae243 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:31 -0600 Subject: driver/usb_mux/pi3usb3x532.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide7166ab9f691d899ed2847ce350f0e2c02a06b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730163 Reviewed-by: Jeremy Bettis --- driver/usb_mux/pi3usb3x532.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/driver/usb_mux/pi3usb3x532.c b/driver/usb_mux/pi3usb3x532.c index 2435157967..c67e0b0ed4 100644 --- a/driver/usb_mux/pi3usb3x532.c +++ b/driver/usb_mux/pi3usb3x532.c @@ -11,8 +11,7 @@ #include "usb_mux.h" #include "util.h" -static int pi3usb3x532_read(const struct usb_mux *me, - uint8_t reg, uint8_t *val) +static int pi3usb3x532_read(const struct usb_mux *me, uint8_t reg, uint8_t *val) { int read, res; @@ -33,8 +32,7 @@ static int pi3usb3x532_read(const struct usb_mux *me, return EC_SUCCESS; } -static int pi3usb3x532_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static int pi3usb3x532_write(const struct usb_mux *me, uint8_t reg, uint8_t val) { if (reg != PI3USB3X532_REG_CONTROL) return EC_ERROR_UNKNOWN; @@ -58,11 +56,10 @@ int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val) static int pi3usb3x532_reset(const struct usb_mux *me) { - return pi3usb3x532_write( - me, - PI3USB3X532_REG_CONTROL, - (PI3USB3X532_MODE_POWERDOWN & PI3USB3X532_CTRL_MASK) | - PI3USB3X532_CTRL_RSVD); + return pi3usb3x532_write(me, PI3USB3X532_REG_CONTROL, + (PI3USB3X532_MODE_POWERDOWN & + PI3USB3X532_CTRL_MASK) | + PI3USB3X532_CTRL_RSVD); } static int pi3usb3x532_init(const struct usb_mux *me) @@ -83,8 +80,7 @@ static int pi3usb3x532_init(const struct usb_mux *me) } /* Writes control register to set switch mode */ -static int pi3usb3x532_set_mux(const struct usb_mux *me, - mux_state_t mux_state, +static int pi3usb3x532_set_mux(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { uint8_t reg = 0; @@ -104,8 +100,7 @@ static int pi3usb3x532_set_mux(const struct usb_mux *me, } /* Reads control register and updates mux_state accordingly */ -static int pi3usb3x532_get_mux(const struct usb_mux *me, - mux_state_t *mux_state) +static int pi3usb3x532_get_mux(const struct usb_mux *me, mux_state_t *mux_state) { uint8_t reg = 0; uint8_t res; -- cgit v1.2.1 From ed442b0c38fbd3ae2694814ab055b33ab89eaf5d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:27 -0600 Subject: common/ec_ec_comm_client.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0e3766260168022a0e3223934cc54e3e719a029 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729623 Reviewed-by: Jeremy Bettis --- common/ec_ec_comm_client.c | 72 ++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 38 deletions(-) diff --git a/common/ec_ec_comm_client.c b/common/ec_ec_comm_client.c index b2f2387976..8f59c5b65e 100644 --- a/common/ec_ec_comm_client.c +++ b/common/ec_ec_comm_client.c @@ -16,7 +16,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) /* * TODO(b:65697962): The packed structures below do not play well if we force EC @@ -97,9 +97,8 @@ struct { * - EC_ERROR_INVAL when the received header is invalid. * - EC_ERROR_UNKNOWN on other error. */ -static int write_command(uint16_t command, - uint8_t *data, int req_len, int resp_len, - int timeout_us) +static int write_command(uint16_t command, uint8_t *data, int req_len, + int resp_len, int timeout_us) { /* Sequence number. */ static uint8_t cur_seq; @@ -111,11 +110,10 @@ static int write_command(uint16_t command, int tx_length = sizeof(*request_header) + ((req_len > 0) ? (req_len + 1) : 0); - struct ec_host_response4 *response_header = - (void *)&data[tx_length]; + struct ec_host_response4 *response_header = (void *)&data[tx_length]; /* RX length is TX length + response from server. */ - int rx_length = tx_length + - sizeof(*request_header) + ((resp_len > 0) ? (resp_len + 1) : 0); + int rx_length = tx_length + sizeof(*request_header) + + ((resp_len > 0) ? (resp_len + 1) : 0); /* * Make sure there is a gap between each command, so that the server @@ -124,7 +122,7 @@ static int write_command(uint16_t command, * TODO(b:65697962): We can be much smarter than this, and record the * last transaction time instead of just sleeping blindly. */ - usleep(10*MSEC); + usleep(10 * MSEC); #ifdef DEBUG_EC_COMM_STATS if ((comm_stats.total % 128) == 0) { @@ -136,26 +134,26 @@ static int write_command(uint16_t command, #endif cur_seq = (cur_seq + 1) & - (EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT); + (EC_PACKET4_0_SEQ_NUM_MASK >> EC_PACKET4_0_SEQ_NUM_SHIFT); memset(request_header, 0, sizeof(*request_header)); /* fields0: leave seq_dup and is_response as 0. */ - request_header->fields0 = - EC_EC_HOSTCMD_VERSION | /* version */ - (cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num */ + request_header->fields0 = EC_EC_HOSTCMD_VERSION | /* version */ + (cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num + */ /* fields1: leave command_version as 0. */ if (req_len > 0) request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK; request_header->command = command; request_header->data_len = req_len; - request_header->header_crc = - cros_crc8((uint8_t *)request_header, sizeof(*request_header)-1); + request_header->header_crc = cros_crc8((uint8_t *)request_header, + sizeof(*request_header) - 1); if (req_len > 0) data[sizeof(*request_header) + req_len] = cros_crc8(&data[sizeof(*request_header)], req_len); - ret = uart_alt_pad_write_read((void *)data, tx_length, - (void *)data, rx_length, timeout_us); + ret = uart_alt_pad_write_read((void *)data, tx_length, (void *)data, + rx_length, timeout_us); INCR_COMM_STATS(total); @@ -187,20 +185,19 @@ static int write_command(uint16_t command, hascrc = response_header->fields1 & EC_PACKET4_1_DATA_CRC_PRESENT_MASK; response_seq = (response_header->fields0 & EC_PACKET4_0_SEQ_NUM_MASK) >> - EC_PACKET4_0_SEQ_NUM_SHIFT; + EC_PACKET4_0_SEQ_NUM_SHIFT; /* * Validate received header. * Note that we _require_ data crc to be present if there is data to be * read back, else we would not know how many bytes to read exactly. */ - if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) - != EC_EC_HOSTCMD_VERSION || - !(response_header->fields0 & - EC_PACKET4_0_IS_RESPONSE_MASK) || - response_seq != cur_seq || - (response_header->data_len > 0 && !hascrc) || - response_header->data_len != resp_len) { + if ((response_header->fields0 & EC_PACKET4_0_STRUCT_VERSION_MASK) != + EC_EC_HOSTCMD_VERSION || + !(response_header->fields0 & EC_PACKET4_0_IS_RESPONSE_MASK) || + response_seq != cur_seq || + (response_header->data_len > 0 && !hascrc) || + response_header->data_len != resp_len) { INCR_COMM_STATS(errinval); return EC_ERROR_INVAL; } @@ -259,9 +256,9 @@ int ec_ec_client_base_get_dynamic_info(void) data.req.param.index = 0; - ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC, - (void *)&data, sizeof(data.req.param), - sizeof(data.resp.info), 15 * MSEC); + ret = write_command(EC_CMD_BATTERY_GET_DYNAMIC, (void *)&data, + sizeof(data.req.param), sizeof(data.resp.info), + 15 * MSEC); ret = handle_error(__func__, ret, data.resp.head.result); if (ret != EC_RES_SUCCESS) return ret; @@ -277,7 +274,7 @@ int ec_ec_client_base_get_dynamic_info(void) #endif memcpy(&battery_dynamic[BATT_IDX_BASE], &data.resp.info, - sizeof(battery_dynamic[BATT_IDX_BASE])); + sizeof(battery_dynamic[BATT_IDX_BASE])); return EC_RES_SUCCESS; } @@ -301,9 +298,9 @@ int ec_ec_client_base_get_static_info(void) data.req.param.index = 0; - ret = write_command(EC_CMD_BATTERY_GET_STATIC, - (void *)&data, sizeof(data.req.param), - sizeof(data.resp.info), 15 * MSEC); + ret = write_command(EC_CMD_BATTERY_GET_STATIC, (void *)&data, + sizeof(data.req.param), sizeof(data.resp.info), + 15 * MSEC); ret = handle_error(__func__, ret, data.resp.head.result); if (ret != EC_RES_SUCCESS) return ret; @@ -330,8 +327,7 @@ int ec_ec_client_base_get_static_info(void) return EC_RES_SUCCESS; } -int ec_ec_client_base_charge_control(int max_current, - int otg_voltage, +int ec_ec_client_base_charge_control(int max_current, int otg_voltage, int allow_charging) { int ret; @@ -350,8 +346,8 @@ int ec_ec_client_base_charge_control(int max_current, data.req.ctrl.max_current = max_current; data.req.ctrl.otg_voltage = otg_voltage; - ret = write_command(EC_CMD_CHARGER_CONTROL, - (void *)&data, sizeof(data.req.ctrl), 0, 30 * MSEC); + ret = write_command(EC_CMD_CHARGER_CONTROL, (void *)&data, + sizeof(data.req.ctrl), 0, 30 * MSEC); return handle_error(__func__, ret, data.resp.head.result); } @@ -372,8 +368,8 @@ int ec_ec_client_hibernate(void) data.req.param.cmd = EC_REBOOT_HIBERNATE; data.req.param.flags = 0; - ret = write_command(EC_CMD_REBOOT_EC, - (void *)&data, sizeof(data.req.param), 0, 30 * MSEC); + ret = write_command(EC_CMD_REBOOT_EC, (void *)&data, + sizeof(data.req.param), 0, 30 * MSEC); return handle_error(__func__, ret, data.resp.head.result); } -- cgit v1.2.1 From c8b6cdb0951ed9f05f96a0b65b810f37306cbd1b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:06 -0600 Subject: board/herobrine/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieef8cb8d11537c2cbad01055ec074faa2c367221 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728320 Reviewed-by: Jeremy Bettis --- board/herobrine/board.c | 125 ++++++++++++++++++------------------------------ 1 file changed, 46 insertions(+), 79 deletions(-) diff --git a/board/herobrine/board.c b/board/herobrine/board.c index fea8bf3a88..a3d2a120b6 100644 --- a/board/herobrine/board.c +++ b/board/herobrine/board.c @@ -26,8 +26,8 @@ #include "usbc_config.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -50,10 +50,8 @@ __override struct keyboard_scan_config keyscan_config = { * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key); * as it still uses the legacy location (KSO_01/KSI_00). */ - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -64,48 +62,36 @@ __override struct keyboard_scan_config keyscan_config = { /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "rtc", - .port = I2C_PORT_RTC, - .kbps = 400, - .scl = GPIO_EC_I2C_RTC_SCL, - .sda = GPIO_EC_I2C_RTC_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "rtc", + .port = I2C_PORT_RTC, + .kbps = 400, + .scl = GPIO_EC_I2C_RTC_SCL, + .sda = GPIO_EC_I2C_RTC_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -113,37 +99,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -214,17 +185,13 @@ static struct bmi_drv_data_t g_bmi260_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 9aff229f3a32b4bcb9ffa67b3b0aa778facbf3ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:43 -0600 Subject: chip/mt_scp/mt818x/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7036365a6afa99998259eeacf81abed26e588044 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729326 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/gpio.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/chip/mt_scp/mt818x/gpio.c b/chip/mt_scp/mt818x/gpio.c index 2bd4bfbb02..e7e1f046b2 100644 --- a/chip/mt_scp/mt818x/gpio.c +++ b/chip/mt_scp/mt818x/gpio.c @@ -13,7 +13,7 @@ #include "util.h" void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { int bit, mode_reg_index, shift; uint32_t mode_bits, mode_mask; @@ -37,18 +37,16 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, shift = (bit & 7) << 2; mode_bits = func << shift; mode_mask = ~(0xf << shift); - AP_GPIO_MODE(mode_reg_index) = (AP_GPIO_MODE(mode_reg_index) & - mode_mask) | mode_bits; + AP_GPIO_MODE(mode_reg_index) = + (AP_GPIO_MODE(mode_reg_index) & mode_mask) | mode_bits; } } test_mockable int gpio_get_level(enum gpio_signal signal) { - return !!(AP_GPIO_DIN(gpio_list[signal].port) & - gpio_list[signal].mask); + return !!(AP_GPIO_DIN(gpio_list[signal].port) & gpio_list[signal].mask); } - void gpio_set_level(enum gpio_signal signal, int value) { if (value) -- cgit v1.2.1 From c8b3833ad7b7688b64a22c1bb3382d27309d7aa8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:23 -0600 Subject: chip/mchp/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9edf4bc61891a82b5073db54b08258916d1d1d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729291 Reviewed-by: Jeremy Bettis --- chip/mchp/flash.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/chip/mchp/flash.c b/chip/mchp/flash.c index 1679cf92cb..fff94cc9ec 100644 --- a/chip/mchp/flash.c +++ b/chip/mchp/flash.c @@ -55,7 +55,7 @@ int crec_flash_physical_read(int offset, int size, char *data) int crec_flash_physical_write(int offset, int size, const char *data) { int ret = EC_SUCCESS; - int i, write_size; + int i, write_size; trace13(0, FLASH, 0, "flash_phys_write: offset=0x%08X size=0x%08X dataptr=0x%08X", @@ -70,8 +70,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) for (i = 0; i < size; i += write_size) { write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE); - ret = spi_flash_write(offset + i, - write_size, + ret = spi_flash_write(offset + i, write_size, (uint8_t *)data + i); if (ret != EC_SUCCESS) break; @@ -94,8 +93,7 @@ int crec_flash_physical_erase(int offset, int size) if (entire_flash_locked) return EC_ERROR_ACCESS_DENIED; - trace12(0, FLASH, 0, - "flash_phys_erase: offset=0x%08X size=0x%08X", + trace12(0, FLASH, 0, "flash_phys_erase: offset=0x%08X size=0x%08X", offset, size); ret = spi_flash_erase(offset, size); return ret; @@ -110,7 +108,7 @@ int crec_flash_physical_erase(int offset, int size) int crec_flash_physical_get_protect(int bank) { return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE, - CONFIG_FLASH_BANK_SIZE); + CONFIG_FLASH_BANK_SIZE); } /** @@ -164,8 +162,7 @@ uint32_t crec_flash_physical_get_protect_flags(void) */ uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -182,8 +179,9 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) wp_status = spi_flash_check_wp(); - if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE && - !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) + if (wp_status == SPI_WP_NONE || + (wp_status == SPI_WP_HARDWARE && + !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; if (!entire_flash_locked) @@ -253,7 +251,7 @@ int crec_flash_physical_restore_state(void) */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) entire_flash_locked = prev->entire_flash_locked; -- cgit v1.2.1 From a876377ba6699d293caeb75c4250a9e8d3438c45 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:55 -0600 Subject: common/printf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53093c6f4fdaa728b30637072147aa8db1fdc38e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729727 Reviewed-by: Jeremy Bettis --- common/printf.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/common/printf.c b/common/printf.c index e302708a9b..9fbac19e20 100644 --- a/common/printf.c +++ b/common/printf.c @@ -12,7 +12,7 @@ static const char error_str[] = "ERROR"; -#define MAX_FORMAT 1024 /* Maximum chars in a single format field */ +#define MAX_FORMAT 1024 /* Maximum chars in a single format field */ #ifndef CONFIG_DEBUG_PRINTF static inline int divmod(uint64_t *n, int d) @@ -47,27 +47,26 @@ static int hexdigit(int c) } /* Flags for vfnprintf() flags */ -#define PF_LEFT BIT(0) /* Left-justify */ -#define PF_PADZERO BIT(1) /* Pad with 0's not spaces */ -#define PF_SIGN BIT(2) /* Add sign (+) for a positive number */ +#define PF_LEFT BIT(0) /* Left-justify */ +#define PF_PADZERO BIT(1) /* Pad with 0's not spaces */ +#define PF_SIGN BIT(2) /* Add sign (+) for a positive number */ /* Deactivate the PF_64BIT flag is 64-bit support is disabled. */ #ifdef NO_UINT64_SUPPORT -#define PF_64BIT 0 +#define PF_64BIT 0 #else -#define PF_64BIT BIT(3) /* Number is 64-bit */ +#define PF_64BIT BIT(3) /* Number is 64-bit */ #endif /* * Print the buffer as a string of bytes in hex. * Returns 0 on success or an error on failure. */ -static int print_hex_buffer(int (*addchar)(void *context, int c), - void *context, const char *vstr, int precision, - int pad_width, int flags) +static int print_hex_buffer(int (*addchar)(void *context, int c), void *context, + const char *vstr, int precision, int pad_width, + int flags) { - /* * Divide pad_width instead of multiplying precision to avoid overflow * error in the condition. The "/2" and "2*" can be optimized by @@ -270,8 +269,8 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, * Avoid null pointer dereference for %ph and * %pb. %pT and %pP can accept null. */ - if (ptrval == NULL - && ptrspec != 'T' && ptrspec != 'P') + if (ptrval == NULL && ptrspec != 'T' && + ptrspec != 'P') continue; /* %pT - print a timestamp. */ if (ptrspec == 'T' && @@ -285,7 +284,7 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, v = *(uint64_t *)ptrval; if (IS_ENABLED( - CONFIG_CONSOLE_VERBOSE)) { + CONFIG_CONSOLE_VERBOSE)) { precision = 6; } else { precision = 3; @@ -298,11 +297,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, ptrval; int rc; - rc = print_hex_buffer(addchar, - context, + rc = print_hex_buffer(addchar, context, hexbuf->buffer, - hexbuf->size, - 0, + hexbuf->size, 0, 0); if (rc != EC_SUCCESS) @@ -443,7 +440,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, vlen = strnlen(vstr, precision); } - while (vlen < pad_width && !(flags & PF_LEFT)) { if (addchar(context, flags & PF_PADZERO ? '0' : ' ')) return EC_ERROR_OVERFLOW; @@ -509,7 +505,7 @@ int crec_vsnprintf(char *str, size_t size, const char *format, va_list args) return -EC_ERROR_INVAL; ctx.str = str; - ctx.size = size - 1; /* Reserve space for terminating '\0' */ + ctx.size = size - 1; /* Reserve space for terminating '\0' */ rv = vfnprintf(snprintf_addchar, &ctx, format, args); -- cgit v1.2.1 From be05805572cf8c121629a0f94866a2a28e283ed7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:24 -0600 Subject: util/uut/com_port.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a53655d8fc3d725a4b3460a07f84da2d8c56c30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730660 Reviewed-by: Jeremy Bettis --- util/uut/com_port.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/uut/com_port.h b/util/uut/com_port.h index 36331f2fb6..9f2ec41f2c 100644 --- a/util/uut/com_port.h +++ b/util/uut/com_port.h @@ -35,10 +35,10 @@ extern "C" { #define COMP_PORT_PREFIX_3 "pts" struct comport_fields { - uint32_t baudrate; /* Baudrate at which running */ - tcflag_t byte_size; /* Number of bits/byte, 4-8 */ - tcflag_t parity; /* 0-4=None,Odd,Even,Mark,Space */ - uint8_t stop_bits; /* 0,1,2 = 1, 1.5, 2 */ + uint32_t baudrate; /* Baudrate at which running */ + tcflag_t byte_size; /* Number of bits/byte, 4-8 */ + tcflag_t parity; /* 0-4=None,Odd,Even,Mark,Space */ + uint8_t stop_bits; /* 0,1,2 = 1, 1.5, 2 */ uint8_t flow_control; /* 0-none, 1-SwFlowControl,2-HwFlowControl */ }; @@ -60,7 +60,7 @@ struct comport_fields { *--------------------------------------------------------------------------- */ int com_port_open(const char *com_port_dev_name, - struct comport_fields com_port_fields); + struct comport_fields com_port_fields); /*--------------------------------------------------------------------------- * Function: int com_config_uart() @@ -110,7 +110,7 @@ bool com_port_close(int device_id); *--------------------------------------------------------------------------- */ bool com_port_write_bin(int device_id, const uint8_t *buffer, - uint32_t buf_size); + uint32_t buf_size); /*--------------------------------------------------------------------------- * Function: uint32_t com_port_read_bin() -- cgit v1.2.1 From 803d2f16658ea7a70f4eb9d80d2bd774a4348afd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:58 -0600 Subject: board/pompom/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0a2288907cc19f98782cb6ec18e0860e575cbfda Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727750 Reviewed-by: Jeremy Bettis --- board/pompom/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/pompom/usbc_config.c b/board/pompom/usbc_config.c index aac136415d..73666d087c 100644 --- a/board/pompom/usbc_config.c +++ b/board/pompom/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From f4d8cfcd1cee4de025c555561a856fd64cc850a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:58 -0600 Subject: driver/usb_mux/amd_fp5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I069a0e995841c8df24b7363ffa789d8b8ec57567 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730151 Reviewed-by: Jeremy Bettis --- driver/usb_mux/amd_fp5.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/driver/usb_mux/amd_fp5.c b/driver/usb_mux/amd_fp5.c index c32e6992c2..53f81aaf7c 100644 --- a/driver/usb_mux/amd_fp5.c +++ b/driver/usb_mux/amd_fp5.c @@ -22,8 +22,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val) uint8_t buf[3] = { 0 }; int rv; - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - NULL, 0, buf, 3); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0, buf, 3); if (rv) return rv; @@ -34,8 +33,7 @@ static inline int amd_fp5_mux_read(const struct usb_mux *me, uint8_t *val) static inline int amd_fp5_mux_write(const struct usb_mux *me, uint8_t val) { - return i2c_write8(me->i2c_port, me->i2c_addr_flags, - me->usb_port, val); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, me->usb_port, val); } static int amd_fp5_init(const struct usb_mux *me) @@ -60,20 +58,22 @@ static int amd_fp5_set_mux(const struct usb_mux *me, mux_state_t mux_state, * it because a powered down MUX is off. */ if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) - ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; if ((mux_state & USB_PD_MUX_USB_ENABLED) && - (mux_state & USB_PD_MUX_DP_ENABLED)) - val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? AMD_FP5_MUX_DOCK_INVERTED : AMD_FP5_MUX_DOCK; + (mux_state & USB_PD_MUX_DP_ENABLED)) + val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + AMD_FP5_MUX_DOCK_INVERTED : + AMD_FP5_MUX_DOCK; else if (mux_state & USB_PD_MUX_USB_ENABLED) - val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? AMD_FP5_MUX_USB_INVERTED : AMD_FP5_MUX_USB; + val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + AMD_FP5_MUX_USB_INVERTED : + AMD_FP5_MUX_USB; else if (mux_state & USB_PD_MUX_DP_ENABLED) - val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? AMD_FP5_MUX_DP_INVERTED : AMD_FP5_MUX_DP; + val = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + AMD_FP5_MUX_DP_INVERTED : + AMD_FP5_MUX_DP; return amd_fp5_mux_write(me, val); } @@ -101,21 +101,21 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state) break; case AMD_FP5_MUX_USB_INVERTED: *mux_state = USB_PD_MUX_USB_ENABLED | - USB_PD_MUX_POLARITY_INVERTED; + USB_PD_MUX_POLARITY_INVERTED; break; case AMD_FP5_MUX_DOCK: *mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED; break; case AMD_FP5_MUX_DOCK_INVERTED: - *mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED - | USB_PD_MUX_POLARITY_INVERTED; + *mux_state = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | + USB_PD_MUX_POLARITY_INVERTED; break; case AMD_FP5_MUX_DP: *mux_state = USB_PD_MUX_DP_ENABLED; break; case AMD_FP5_MUX_DP_INVERTED: *mux_state = USB_PD_MUX_DP_ENABLED | - USB_PD_MUX_POLARITY_INVERTED; + USB_PD_MUX_POLARITY_INVERTED; break; case AMD_FP5_MUX_SAFE: default: @@ -126,8 +126,8 @@ static int amd_fp5_get_mux(const struct usb_mux *me, mux_state_t *mux_state) return EC_SUCCESS; } -static struct queue const chipset_reset_queue - = QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *); +static struct queue const chipset_reset_queue = + QUEUE_NULL(CONFIG_USB_PD_PORT_MAX_COUNT, struct usb_mux *); static void amd_fp5_chipset_reset_delay(void) { -- cgit v1.2.1 From 1283184e82ce1ef3483d568ca2336bc7b85c3334 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:01 -0600 Subject: board/elm/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida73dfe47f803ff51b570820efbe07343e8e16bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728290 Reviewed-by: Jeremy Bettis --- board/elm/battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/elm/battery.c b/board/elm/battery.c index de9685a89d..787f654439 100644 --- a/board/elm/battery.c +++ b/board/elm/battery.c @@ -10,8 +10,8 @@ #include "util.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHIP_MODE_REG 0x3a -#define SB_SHUTDOWN_DATA 0xC574 +#define SB_SHIP_MODE_REG 0x3a +#define SB_SHUTDOWN_DATA 0xC574 static const struct battery_info info = { .voltage_max = 13200, -- cgit v1.2.1 From 741a1ab023117f9dac2e0093bf3ad753d7c4570c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:45 -0600 Subject: driver/accel_bma4xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I112de09964553713cbcf55ac4734e8040575f4d2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729887 Reviewed-by: Jeremy Bettis --- driver/accel_bma4xx.h | 262 +++++++++++++++++++++++++------------------------- 1 file changed, 131 insertions(+), 131 deletions(-) diff --git a/driver/accel_bma4xx.h b/driver/accel_bma4xx.h index 13c9da4a92..49c6d1a8d0 100644 --- a/driver/accel_bma4xx.h +++ b/driver/accel_bma4xx.h @@ -8,158 +8,158 @@ #ifndef __CROS_EC_ACCEL_BMA4XX_H #define __CROS_EC_ACCEL_BMA4XX_H -#define BMA4_I2C_ADDR_PRIMARY 0x18 -#define BMA4_I2C_ADDR_SECONDARY 0x19 -#define BMA4_I2C_BMM150_ADDR 0x10 +#define BMA4_I2C_ADDR_PRIMARY 0x18 +#define BMA4_I2C_ADDR_SECONDARY 0x19 +#define BMA4_I2C_BMM150_ADDR 0x10 /* Chip-specific registers */ -#define BMA4_CHIP_ID_ADDR 0x00 -#define BMA4_CHIP_ID_MIN 0x10 -#define BMA4_CHIP_ID_MAX 0x15 - -#define BMA4_ERROR_ADDR 0x02 -#define BMA4_FATAL_ERR_MSK 0x01 -#define BMA4_CMD_ERR_POS 1 -#define BMA4_CMD_ERR_MSK 0x02 -#define BMA4_ERR_CODE_POS 2 -#define BMA4_ERR_CODE_MSK 0x1C -#define BMA4_FIFO_ERR_POS 6 -#define BMA4_FIFO_ERR_MSK 0x40 -#define BMA4_AUX_ERR_POS 7 -#define BMA4_AUX_ERR_MSK 0x80 - -#define BMA4_STATUS_ADDR 0x03 -#define BMA4_STAT_DATA_RDY_ACCEL_POS 7 -#define BMA4_STAT_DATA_RDY_ACCEL_MSK 0x80 - -#define BMA4_DATA_0_ADDR 0x0A -#define BMA4_DATA_8_ADDR 0x12 - -#define BMA4_SENSORTIME_0_ADDR 0x18 -#define BMA4_INT_STAT_0_ADDR 0x1C -#define BMA4_INT_STAT_1_ADDR 0x1D -#define BMA4_STEP_CNT_OUT_0_ADDR 0x1E -#define BMA4_HIGH_G_OUT_ADDR 0x1F -#define BMA4_TEMPERATURE_ADDR 0x22 - -#define BMA4_FIFO_LENGTH_0_ADDR 0x24 -#define BMA4_FIFO_DATA_ADDR 0x26 -#define BMA4_ACTIVITY_OUT_ADDR 0x27 -#define BMA4_ORIENTATION_OUT_ADDR 0x28 - -#define BMA4_INTERNAL_STAT 0x2A -#define BMA4_ASIC_INITIALIZED 0x01 - -#define BMA4_ACCEL_CONFIG_ADDR 0x40 -#define BMA4_ACCEL_ODR_POS 0 -#define BMA4_ACCEL_ODR_MSK 0x0F -#define BMA4_ACCEL_BW_POS 4 -#define BMA4_ACCEL_BW_MSK 0x70 -#define BMA4_ACCEL_PERFMODE_POS 7 -#define BMA4_ACCEL_PERFMODE_MSK 0x80 -#define BMA4_OUTPUT_DATA_RATE_0_78HZ 0x01 -#define BMA4_OUTPUT_DATA_RATE_1_56HZ 0x02 -#define BMA4_OUTPUT_DATA_RATE_3_12HZ 0x03 -#define BMA4_OUTPUT_DATA_RATE_6_25HZ 0x04 -#define BMA4_OUTPUT_DATA_RATE_12_5HZ 0x05 -#define BMA4_OUTPUT_DATA_RATE_25HZ 0x06 -#define BMA4_OUTPUT_DATA_RATE_50HZ 0x07 -#define BMA4_OUTPUT_DATA_RATE_100HZ 0x08 -#define BMA4_OUTPUT_DATA_RATE_200HZ 0x09 -#define BMA4_OUTPUT_DATA_RATE_400HZ 0x0A -#define BMA4_OUTPUT_DATA_RATE_800HZ 0x0B -#define BMA4_OUTPUT_DATA_RATE_1600HZ 0x0C -#define BMA4_ACCEL_OSR4_AVG1 0 -#define BMA4_ACCEL_OSR2_AVG2 1 -#define BMA4_ACCEL_NORMAL_AVG4 2 -#define BMA4_ACCEL_CIC_AVG8 3 -#define BMA4_ACCEL_RES_AVG16 4 -#define BMA4_ACCEL_RES_AVG32 5 -#define BMA4_ACCEL_RES_AVG64 6 -#define BMA4_ACCEL_RES_AVG128 7 -#define BMA4_CIC_AVG_MODE 0 -#define BMA4_CONTINUOUS_MODE 1 - -#define BMA4_ACCEL_RANGE_ADDR 0x41 -#define BMA4_ACCEL_RANGE_POS 0 -#define BMA4_ACCEL_RANGE_MSK 0x03 -#define BMA4_ACCEL_RANGE_2G 0 -#define BMA4_ACCEL_RANGE_4G 1 -#define BMA4_ACCEL_RANGE_8G 2 -#define BMA4_ACCEL_RANGE_16G 3 - -#define BMA4_RESERVED_REG_5B_ADDR 0x5B -#define BMA4_RESERVED_REG_5C_ADDR 0x5C -#define BMA4_FEATURE_CONFIG_ADDR 0x5E -#define BMA4_INTERNAL_ERROR 0x5F -#define BMA4_IF_CONFIG_ADDR 0x6B -#define BMA4_FOC_ACC_CONF_VAL 0xB7 - -#define BMA4_NV_CONFIG_ADDR 0x70 -#define BMA4_NV_ACCEL_OFFSET_POS 3 -#define BMA4_NV_ACCEL_OFFSET_MSK 0x08 - -#define BMA4_OFFSET_0_ADDR 0x71 -#define BMA4_OFFSET_1_ADDR 0x72 -#define BMA4_OFFSET_2_ADDR 0x73 - -#define BMA4_POWER_CONF_ADDR 0x7C -#define BMA4_ADVANCE_POWER_SAVE_POS 0 -#define BMA4_ADVANCE_POWER_SAVE_MSK 0x01 - -#define BMA4_POWER_CTRL_ADDR 0x7D -#define BMA4_ACCEL_ENABLE_POS 2 -#define BMA4_ACCEL_ENABLE_MSK 0x04 -#define BMA4_ENABLE 0x01 -#define BMA4_DISABLE 0x00 - -#define BMA4_CMD_ADDR 0x7E -#define BMA4_NVM_PROG 0xA0 -#define BMA4_FIFO_FLUSH 0xB0 -#define BMA4_SOFT_RESET 0xB6 +#define BMA4_CHIP_ID_ADDR 0x00 +#define BMA4_CHIP_ID_MIN 0x10 +#define BMA4_CHIP_ID_MAX 0x15 + +#define BMA4_ERROR_ADDR 0x02 +#define BMA4_FATAL_ERR_MSK 0x01 +#define BMA4_CMD_ERR_POS 1 +#define BMA4_CMD_ERR_MSK 0x02 +#define BMA4_ERR_CODE_POS 2 +#define BMA4_ERR_CODE_MSK 0x1C +#define BMA4_FIFO_ERR_POS 6 +#define BMA4_FIFO_ERR_MSK 0x40 +#define BMA4_AUX_ERR_POS 7 +#define BMA4_AUX_ERR_MSK 0x80 + +#define BMA4_STATUS_ADDR 0x03 +#define BMA4_STAT_DATA_RDY_ACCEL_POS 7 +#define BMA4_STAT_DATA_RDY_ACCEL_MSK 0x80 + +#define BMA4_DATA_0_ADDR 0x0A +#define BMA4_DATA_8_ADDR 0x12 + +#define BMA4_SENSORTIME_0_ADDR 0x18 +#define BMA4_INT_STAT_0_ADDR 0x1C +#define BMA4_INT_STAT_1_ADDR 0x1D +#define BMA4_STEP_CNT_OUT_0_ADDR 0x1E +#define BMA4_HIGH_G_OUT_ADDR 0x1F +#define BMA4_TEMPERATURE_ADDR 0x22 + +#define BMA4_FIFO_LENGTH_0_ADDR 0x24 +#define BMA4_FIFO_DATA_ADDR 0x26 +#define BMA4_ACTIVITY_OUT_ADDR 0x27 +#define BMA4_ORIENTATION_OUT_ADDR 0x28 + +#define BMA4_INTERNAL_STAT 0x2A +#define BMA4_ASIC_INITIALIZED 0x01 + +#define BMA4_ACCEL_CONFIG_ADDR 0x40 +#define BMA4_ACCEL_ODR_POS 0 +#define BMA4_ACCEL_ODR_MSK 0x0F +#define BMA4_ACCEL_BW_POS 4 +#define BMA4_ACCEL_BW_MSK 0x70 +#define BMA4_ACCEL_PERFMODE_POS 7 +#define BMA4_ACCEL_PERFMODE_MSK 0x80 +#define BMA4_OUTPUT_DATA_RATE_0_78HZ 0x01 +#define BMA4_OUTPUT_DATA_RATE_1_56HZ 0x02 +#define BMA4_OUTPUT_DATA_RATE_3_12HZ 0x03 +#define BMA4_OUTPUT_DATA_RATE_6_25HZ 0x04 +#define BMA4_OUTPUT_DATA_RATE_12_5HZ 0x05 +#define BMA4_OUTPUT_DATA_RATE_25HZ 0x06 +#define BMA4_OUTPUT_DATA_RATE_50HZ 0x07 +#define BMA4_OUTPUT_DATA_RATE_100HZ 0x08 +#define BMA4_OUTPUT_DATA_RATE_200HZ 0x09 +#define BMA4_OUTPUT_DATA_RATE_400HZ 0x0A +#define BMA4_OUTPUT_DATA_RATE_800HZ 0x0B +#define BMA4_OUTPUT_DATA_RATE_1600HZ 0x0C +#define BMA4_ACCEL_OSR4_AVG1 0 +#define BMA4_ACCEL_OSR2_AVG2 1 +#define BMA4_ACCEL_NORMAL_AVG4 2 +#define BMA4_ACCEL_CIC_AVG8 3 +#define BMA4_ACCEL_RES_AVG16 4 +#define BMA4_ACCEL_RES_AVG32 5 +#define BMA4_ACCEL_RES_AVG64 6 +#define BMA4_ACCEL_RES_AVG128 7 +#define BMA4_CIC_AVG_MODE 0 +#define BMA4_CONTINUOUS_MODE 1 + +#define BMA4_ACCEL_RANGE_ADDR 0x41 +#define BMA4_ACCEL_RANGE_POS 0 +#define BMA4_ACCEL_RANGE_MSK 0x03 +#define BMA4_ACCEL_RANGE_2G 0 +#define BMA4_ACCEL_RANGE_4G 1 +#define BMA4_ACCEL_RANGE_8G 2 +#define BMA4_ACCEL_RANGE_16G 3 + +#define BMA4_RESERVED_REG_5B_ADDR 0x5B +#define BMA4_RESERVED_REG_5C_ADDR 0x5C +#define BMA4_FEATURE_CONFIG_ADDR 0x5E +#define BMA4_INTERNAL_ERROR 0x5F +#define BMA4_IF_CONFIG_ADDR 0x6B +#define BMA4_FOC_ACC_CONF_VAL 0xB7 + +#define BMA4_NV_CONFIG_ADDR 0x70 +#define BMA4_NV_ACCEL_OFFSET_POS 3 +#define BMA4_NV_ACCEL_OFFSET_MSK 0x08 + +#define BMA4_OFFSET_0_ADDR 0x71 +#define BMA4_OFFSET_1_ADDR 0x72 +#define BMA4_OFFSET_2_ADDR 0x73 + +#define BMA4_POWER_CONF_ADDR 0x7C +#define BMA4_ADVANCE_POWER_SAVE_POS 0 +#define BMA4_ADVANCE_POWER_SAVE_MSK 0x01 + +#define BMA4_POWER_CTRL_ADDR 0x7D +#define BMA4_ACCEL_ENABLE_POS 2 +#define BMA4_ACCEL_ENABLE_MSK 0x04 +#define BMA4_ENABLE 0x01 +#define BMA4_DISABLE 0x00 + +#define BMA4_CMD_ADDR 0x7E +#define BMA4_NVM_PROG 0xA0 +#define BMA4_FIFO_FLUSH 0xB0 +#define BMA4_SOFT_RESET 0xB6 /* Other definitions */ -#define BMA4_X_AXIS 0 -#define BMA4_Y_AXIS 1 -#define BMA4_Z_AXIS 2 +#define BMA4_X_AXIS 0 +#define BMA4_Y_AXIS 1 +#define BMA4_Z_AXIS 2 -#define BMA4_12_BIT_RESOLUTION 12 -#define BMA4_14_BIT_RESOLUTION 14 -#define BMA4_16_BIT_RESOLUTION 16 +#define BMA4_12_BIT_RESOLUTION 12 +#define BMA4_14_BIT_RESOLUTION 14 +#define BMA4_16_BIT_RESOLUTION 16 /* * The max positive value of accel data is 0x07FF, equal to range(g) * So, in order to get +1g, divide the 0x07FF by range */ -#define BMA4_ACC_DATA_PLUS_1G(range) (0x07FF / (range)) +#define BMA4_ACC_DATA_PLUS_1G(range) (0x07FF / (range)) /* For offset registers 1LSB - 3.9mg */ -#define BMA4_OFFSET_ACC_MULTI_MG (3900 * 1000) -#define BMA4_OFFSET_ACC_DIV_MG 1000000 +#define BMA4_OFFSET_ACC_MULTI_MG (3900 * 1000) +#define BMA4_OFFSET_ACC_DIV_MG 1000000 -#define BMA4_FOC_SAMPLE_LIMIT 32 +#define BMA4_FOC_SAMPLE_LIMIT 32 /* Min and Max sampling frequency in mHz */ -#define BMA4_ACCEL_MIN_FREQ 12500 -#define BMA4_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) +#define BMA4_ACCEL_MIN_FREQ 12500 +#define BMA4_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) -#define BMA4_RANGE_TO_REG(_range) \ +#define BMA4_RANGE_TO_REG(_range) \ ((_range) < 8 ? BMA4_ACCEL_RANGE_2G + ((_range) / 4) : \ BMA4_ACCEL_RANGE_8G + ((_range) / 16)) -#define BMA4_REG_TO_RANGE(_reg) \ - ((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg) * 2 : \ - 8 + ((_reg) - BMA4_ACCEL_RANGE_8G) * 8) +#define BMA4_REG_TO_RANGE(_reg) \ + ((_reg) < BMA4_ACCEL_RANGE_8G ? 2 + (_reg)*2 : \ + 8 + ((_reg)-BMA4_ACCEL_RANGE_8G) * 8) -#define BMA4_ODR_TO_REG(_odr) \ - ((_odr) < 125000 ? \ - BMA4_OUTPUT_DATA_RATE_0_78HZ + __fls(((_odr) * 10) / 7800) : \ - BMA4_OUTPUT_DATA_RATE_25HZ + __fls((_odr) / 25000)) +#define BMA4_ODR_TO_REG(_odr) \ + ((_odr) < 125000 ? \ + BMA4_OUTPUT_DATA_RATE_0_78HZ + __fls(((_odr)*10) / 7800) : \ + BMA4_OUTPUT_DATA_RATE_25HZ + __fls((_odr) / 25000)) -#define BMA4_REG_TO_ODR(_reg) \ - ((_reg) < BMA4_OUTPUT_DATA_RATE_25HZ ? \ - (7800 << ((_reg) - BMA4_OUTPUT_DATA_RATE_0_78HZ)) / 10 : \ - 25000 << ((_reg) - BMA4_OUTPUT_DATA_RATE_25HZ)) +#define BMA4_REG_TO_ODR(_reg) \ + ((_reg) < BMA4_OUTPUT_DATA_RATE_25HZ ? \ + (7800 << ((_reg)-BMA4_OUTPUT_DATA_RATE_0_78HZ)) / 10 : \ + 25000 << ((_reg)-BMA4_OUTPUT_DATA_RATE_25HZ)) extern const struct accelgyro_drv bma4_accel_drv; -- cgit v1.2.1 From 5420cbb935d9bb4e20b2ce7a3e76067f64c3c380 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:21 -0600 Subject: board/dratini/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b6bd2f5424bd5cc2c711e2c1d89532e8167dcdb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728235 Reviewed-by: Jeremy Bettis --- board/dratini/board.h | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/board/dratini/board.h b/board/dratini/board.h index 82c09494f5..7fb4998d81 100644 --- a/board/dratini/board.h +++ b/board/dratini/board.h @@ -30,10 +30,10 @@ * Dratini's battery takes several seconds to come back out of its disconnect * state (~4 seconds, but give it 6 for margin). */ -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6 -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 /* Sensors */ /* BMI160 Base accel/gyro */ @@ -112,16 +112,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -129,9 +129,9 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC2 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC2 */ ADC_CH_COUNT }; @@ -142,11 +142,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From c5c52be52e32acc56c7248eca1d9f640af90ad50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:53 -0600 Subject: test/charge_ramp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I313f64d0863f3c952aa739537051d5ec94229a05 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730474 Reviewed-by: Jeremy Bettis --- test/charge_ramp.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/test/charge_ramp.c b/test/charge_ramp.c index 84cac57b8e..6356b44c57 100644 --- a/test/charge_ramp.c +++ b/test/charge_ramp.c @@ -19,7 +19,7 @@ #define TASK_EVENT_OVERCURRENT (1 << 0) -#define RAMP_STABLE_DELAY (120*SECOND) +#define RAMP_STABLE_DELAY (120 * SECOND) /* * Time to delay for detecting the charger type. This value follows @@ -27,7 +27,7 @@ * CHARGE_DETECT_DELAY so we guarantee we wake up before the ramp * has started. */ -#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100*MSEC) +#define CHARGE_DETECT_DELAY_TEST (CHARGE_DETECT_DELAY - 100 * MSEC) static int system_load_current_ma; static int vbus_low_current_ma = 500; @@ -73,8 +73,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) vbus_low_current_ma; } -void board_set_charge_limit(int port, int supplier, int limit_ma, - int max_ma, int max_mv) +void board_set_charge_limit(int port, int supplier, int limit_ma, int max_ma, + int max_mv) { charge_limit_ma = limit_ma; if (charge_limit_ma > overcurrent_current_ma) @@ -96,9 +96,8 @@ static void plug_charger_with_ts(int supplier_type, int port, int min_current, static void plug_charger(int supplier_type, int port, int min_current, int vbus_low_current, int overcurrent_current) { - plug_charger_with_ts(supplier_type, port, min_current, - vbus_low_current, overcurrent_current, - get_time()); + plug_charger_with_ts(supplier_type, port, min_current, vbus_low_current, + overcurrent_current, get_time()); } static void unplug_charger(void) @@ -137,7 +136,7 @@ static int test_no_ramp(void) * the charge limit. This just needs at least transition to the * CHG_RAMP_OVERCURRENT_DETECT state. */ - usleep(CHARGE_DETECT_DELAY_TEST + 200*MSEC); + usleep(CHARGE_DETECT_DELAY_TEST + 200 * MSEC); /* That's right. Start at 500 mA */ TEST_ASSERT(charge_limit_ma == 500); TEST_ASSERT(wait_stable_no_overcurrent()); @@ -442,14 +441,14 @@ static int test_equal_priority_overcurrent(void) * switches to the other one. */ while (1) { - plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, - 2000, oc_time); + plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 0, 500, 3000, 2000, + oc_time); oc_time = get_time(); oc_time.val += 600 * MSEC; if (wait_stable_no_overcurrent()) break; - plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000, - 2000, oc_time); + plug_charger_with_ts(CHARGE_SUPPLIER_TEST4, 1, 500, 3000, 2000, + oc_time); oc_time = get_time(); oc_time.val += 600 * MSEC; if (wait_stable_no_overcurrent()) -- cgit v1.2.1 From 416d05c91dce12845b5281354e28940b0a76ba38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:48 -0600 Subject: baseboard/zork/variant_trembyle.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b0c3ec817bfe73a039711306a59cbf593169926 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727961 Reviewed-by: Jeremy Bettis --- baseboard/zork/variant_trembyle.c | 94 ++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 55 deletions(-) diff --git a/baseboard/zork/variant_trembyle.c b/baseboard/zork/variant_trembyle.c index f9173df05a..871f3b351d 100644 --- a/baseboard/zork/variant_trembyle.c +++ b/baseboard/zork/variant_trembyle.c @@ -28,8 +28,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct i2c_port_t i2c_ports[] = { { @@ -160,8 +160,7 @@ __overridable void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -182,7 +181,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -284,7 +282,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -333,18 +330,15 @@ void tcpc_alert_event(enum gpio_signal signal) schedule_deferred_pd_interrupt(port); } - int board_pd_set_frs_enable(int port, int enable) { int rv = EC_SUCCESS; /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -393,8 +387,7 @@ BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT); * PS8802 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8802_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8802_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; @@ -406,11 +399,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2, + PS8802_REG2_USB_SSEQ_LEVEL, + PS8802_USBEQ_LEVEL_UP_MASK, + PS8802_USBEQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -418,11 +410,10 @@ static int board_ps8802_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE2, + PS8802_REG2_DPEQ_LEVEL, + PS8802_DPEQ_LEVEL_UP_MASK, + PS8802_DPEQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -434,52 +425,46 @@ static int board_ps8802_mux_set(const struct usb_mux *me, * PS8818 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - ZORK_PS8818_RX_INPUT_TERM); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + ZORK_PS8818_RX_INPUT_TERM); if (rv) return rv; } @@ -487,11 +472,10 @@ static int board_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; -- cgit v1.2.1 From f8ac2a6f2bb5e2993177e7df889a842bd8236d03 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:10 -0600 Subject: common/rgb_keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15b9661d7febd66673ddc8f25dab0135daf511d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729730 Reviewed-by: Jeremy Bettis --- common/rgb_keyboard.c | 47 ++++++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c index 815e4a3435..95ed7a062b 100644 --- a/common/rgb_keyboard.c +++ b/common/rgb_keyboard.c @@ -24,7 +24,7 @@ #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args) test_export_static enum ec_rgbkbd_demo demo = -#if defined(CONFIG_RGBKBD_DEMO_FLOW) +#if defined(CONFIG_RGBKBD_DEMO_FLOW) EC_RGBKBD_DEMO_FLOW; #elif defined(CONFIG_RGBKBD_DEMO_DOT) EC_RGBKBD_DEMO_DOT; @@ -35,15 +35,14 @@ test_export_static enum ec_rgbkbd_demo demo = const int default_demo_interval_ms = 250; test_export_static int demo_interval_ms = -1; -test_export_static -uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT]; +test_export_static uint8_t rgbkbd_table[EC_RGBKBD_MAX_KEY_COUNT]; static enum rgbkbd_state rgbkbd_state; const struct rgbkbd_init rgbkbd_init_default = { .gcc = RGBKBD_MAX_GCC_LEVEL / 2, .scale = { RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE, RGBKBD_MAX_SCALE }, - .color = { .r = 0xff, .g = 0xff, .b = 0xff }, /* white */ + .color = { .r = 0xff, .g = 0xff, .b = 0xff }, /* white */ }; const struct rgbkbd_init *rgbkbd_init_setting = &rgbkbd_init_default; @@ -88,8 +87,8 @@ static int set_color_single(struct rgb_s color, int x, int y) rv = ctx->cfg->drv->set_color(ctx, offset, &ctx->buf[offset], 1); CPRINTS("%set (%d,%d) to color=(%d,%d,%d) grid=%u offset=%u (%d)", - rv ? "Failed to s" : "S", - x, y, color.r, color.g, color.b, grid, offset, rv); + rv ? "Failed to s" : "S", x, y, color.r, color.g, color.b, grid, + offset, rv); return rv; } @@ -214,14 +213,13 @@ static void rgbkbd_demo_run(enum ec_rgbkbd_demo id) } } -test_export_static -void rgbkbd_init_lookup_table(void) +test_export_static void rgbkbd_init_lookup_table(void) { bool add = true; int i, k = 0; if (rgbkbd_map[0] != RGBKBD_DELM || - rgbkbd_map[rgbkbd_map_size - 1] != RGBKBD_DELM) { + rgbkbd_map[rgbkbd_map_size - 1] != RGBKBD_DELM) { CPRINTS("Invalid Key-LED map"); return; } @@ -267,8 +265,8 @@ static int rgbkbd_set_global_brightness(uint8_t gcc) e = ctx->cfg->drv->set_gcc(ctx, gcc); if (e) { - CPRINTS("Failed to set GCC to %u for grid=%d (%d)", - gcc, grid, e); + CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc, + grid, e); rv = e; continue; } @@ -356,8 +354,8 @@ static int rgbkbd_init(void) e = ctx->cfg->drv->set_gcc(ctx, gcc); if (e) { - CPRINTS("Failed to set GCC to %u for grid=%d (%d)", - gcc, i, e); + CPRINTS("Failed to set GCC to %u for grid=%d (%d)", gcc, + i, e); rv = e; continue; } @@ -423,8 +421,8 @@ static int rgbkbd_enable(int enable) } if (rv == EC_SUCCESS) { - rgbkbd_state = enable ? - RGBKBD_STATE_ENABLED : RGBKBD_STATE_DISABLED; + rgbkbd_state = enable ? RGBKBD_STATE_ENABLED : + RGBKBD_STATE_DISABLED; } /* Return EC_SUCCESS or the last error. */ @@ -518,8 +516,8 @@ static enum ec_status hc_rgbkbd_set_color(struct host_cmd_handler_args *args) if (led.u8 == RGBKBD_DELM) /* Reached end of the group. */ break; - if (set_color_single(p->color[i], - led.coord.x, led.coord.y)) + if (set_color_single(p->color[i], led.coord.x, + led.coord.y)) return EC_RES_ERROR; } while (led.u8 != RGBKBD_DELM); } @@ -606,19 +604,19 @@ test_export_static int cc_rgb(int argc, char **argv) if (y < 0) { /* Set all LEDs on column x. */ - ccprintf("Set column %d to 0x%02x%02x%02x\n", - x, rgb.r, rgb.g, rgb.b); + ccprintf("Set column %d to 0x%02x%02x%02x\n", x, rgb.r, + rgb.g, rgb.b); for (i = 0; i < rgbkbd_vsize; i++) rv = set_color_single(rgb, x, i); } else if (x < 0) { /* Set all LEDs on row y. */ - ccprintf("Set row %d to 0x%02x%02x%02x\n", - y, rgb.r, rgb.g, rgb.b); + ccprintf("Set row %d to 0x%02x%02x%02x\n", y, rgb.r, + rgb.g, rgb.b); for (i = 0; i < rgbkbd_hsize; i++) rv = set_color_single(rgb, i, y); } else { - ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", - x, y, rgb.r, rgb.g, rgb.b); + ccprintf("Set (%d,%d) to 0x%02x%02x%02x\n", x, y, rgb.r, + rgb.g, rgb.b); rv = set_color_single(rgb, x, y); } } else if (!strcasecmp(argv[1], "all")) { @@ -680,6 +678,5 @@ DECLARE_CONSOLE_COMMAND(rgb, cc_rgb, "4. rgb demo \n" "5. rgb reset/enable/disable/red\n" "6. rgb scale <24-bit RGB scale>\n", - "Control RGB keyboard" - ); + "Control RGB keyboard"); #endif -- cgit v1.2.1 From 0a65f8af965b6394bf9327d6b5e2d97c9bda2592 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:09 -0600 Subject: board/madoo/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie96dc6fb1b09f0bb63722c845c6429ff5870fb7e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728648 Reviewed-by: Jeremy Bettis --- board/madoo/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/madoo/cbi_ssfc.h b/board/madoo/cbi_ssfc.h index 873b90f993..501d629703 100644 --- a/board/madoo/cbi_ssfc.h +++ b/board/madoo/cbi_ssfc.h @@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 2f251eb2831ea6cb2bf9dd5465902c7ee2372dd7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:33 -0600 Subject: board/boldar/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id40ddea9bfbb081b550405a5fdc44034d31043ce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728066 Reviewed-by: Jeremy Bettis --- board/boldar/sensors.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/boldar/sensors.c b/board/boldar/sensors.c index 534065cde3..1d9cb27558 100644 --- a/board/boldar/sensors.c +++ b/board/boldar/sensors.c @@ -85,17 +85,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 48a7b61dfdd626d498372b4efca68cf669cbe585 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:24 -0600 Subject: zephyr/shim/include/gpio/gpio_int.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia59a93d0ff59af98f12038d4e47b41e1edf87b72 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730828 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/gpio/gpio_int.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/gpio/gpio_int.h b/zephyr/shim/include/gpio/gpio_int.h index 5cbddf76ca..af5c9c4ace 100644 --- a/zephyr/shim/include/gpio/gpio_int.h +++ b/zephyr/shim/include/gpio/gpio_int.h @@ -23,8 +23,7 @@ /* * Maps nodelabel of interrupt node to internal configuration block. */ -#define GPIO_INT_FROM_NODELABEL(lbl) \ - (GPIO_INT_FROM_NODE(DT_NODELABEL(lbl))) +#define GPIO_INT_FROM_NODELABEL(lbl) (GPIO_INT_FROM_NODE(DT_NODELABEL(lbl))) /* * Unique enum name for the interrupt. @@ -38,7 +37,7 @@ enum gpio_interrupts { #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts) DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts), - GPIO_INT_ENUM_WITH_COMMA) + GPIO_INT_ENUM_WITH_COMMA) #endif GPIO_INT_COUNT }; @@ -60,24 +59,24 @@ struct gpio_int_config; * ... // set up device * gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(my_interrupt_node)); */ -int gpio_enable_dt_interrupt(const struct gpio_int_config * const ic); +int gpio_enable_dt_interrupt(const struct gpio_int_config *const ic); /* * Disable the interrupt. */ -int gpio_disable_dt_interrupt(const struct gpio_int_config * const ic); +int gpio_disable_dt_interrupt(const struct gpio_int_config *const ic); /* * Get the interrupt config for this interrupt. */ const struct gpio_int_config * - gpio_interrupt_get_config(enum gpio_interrupts intr); +gpio_interrupt_get_config(enum gpio_interrupts intr); /* * Declare interrupt configuration data structures. */ -#define GPIO_INT_DECLARE(id) \ - extern const struct gpio_int_config * const GPIO_INT_FROM_NODE(id); +#define GPIO_INT_DECLARE(id) \ + extern const struct gpio_int_config *const GPIO_INT_FROM_NODE(id); #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_gpio_interrupts) DT_FOREACH_CHILD(DT_COMPAT_GET_ANY_STATUS_OKAY(cros_ec_gpio_interrupts), -- cgit v1.2.1 From c4d874233483c5c700869ca51a84eea1cd31010c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:10 -0600 Subject: builtin/endian.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I694fb45a5eebb5049d0c7709d84615d1627e0bf0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729144 Reviewed-by: Jeremy Bettis --- builtin/endian.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/builtin/endian.h b/builtin/endian.h index 65c064bb78..88fd39d558 100644 --- a/builtin/endian.h +++ b/builtin/endian.h @@ -17,7 +17,7 @@ extern "C" { * host byte order. Note that the code currently does not require functions * for converting little endian integers. */ -#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) +#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) static inline uint16_t be16toh(uint16_t in) { @@ -40,10 +40,10 @@ static inline uint64_t be64toh(uint64_t in) #define htole32(x) (uint32_t)(x) #define htole64(x) (uint64_t)(x) -#endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ +#endif /* __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ */ #ifdef __cplusplus } #endif -#endif /* __EC_BUILTIN_ENDIAN_H */ +#endif /* __EC_BUILTIN_ENDIAN_H */ -- cgit v1.2.1 From b1cb4339a742bd12f17ae0a8d4dc7fa6dc0a557b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:23 -0600 Subject: board/pirika/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f2d8f2ddaffa5ed6afc3ce0dd691e470cd93724 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728831 Reviewed-by: Jeremy Bettis --- board/pirika/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/pirika/usb_pd_policy.c b/board/pirika/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/pirika/usb_pd_policy.c +++ b/board/pirika/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From bd988c16ac75146ac714a761f05c493075c2a09b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:05 -0600 Subject: zephyr/shim/chip/it8xxx2/include/flash_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7869ed9263213158802a8118fb47df4b7b9bb775 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730813 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/it8xxx2/include/flash_chip.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h index 692eaa9db0..ce8cc326ff 100644 --- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h +++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h @@ -9,25 +9,25 @@ * One page program instruction allows maximum 256 bytes (a page) of data * to be programmed. */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - write_block_size) +#define CONFIG_FLASH_WRITE_SIZE \ + DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) /* Erase bank size */ -#define CONFIG_FLASH_ERASE_SIZE DT_PROP(DT_INST(0, soc_nv_flash), \ - erase_block_size) +#define CONFIG_FLASH_ERASE_SIZE \ + DT_PROP(DT_INST(0, soc_nv_flash), erase_block_size) /* Protect bank size */ -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE -#define CONFIG_RO_STORAGE_OFF 0x0 -#define CONFIG_RW_STORAGE_OFF 0x0 +#define CONFIG_RO_STORAGE_OFF 0x0 +#define CONFIG_RW_STORAGE_OFF 0x0 /* * The EC uses the one bank of flash to emulate a SPI-like write protect * register with persistent state. */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_FLASH_SIZE_BYTES / 2 - \ - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF \ + (CONFIG_FLASH_SIZE_BYTES / 2 - CONFIG_FW_PSTATE_SIZE) #endif /* __CROS_EC_FLASH_CHIP_H */ -- cgit v1.2.1 From 40cf2026fd19d2ed863064f44ebe8f006e1e0352 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:10 -0600 Subject: common/body_detection.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2c14c714b5814d0fb6fceb5f910b86daa8a7d60 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729593 Reviewed-by: Jeremy Bettis --- common/body_detection.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/common/body_detection.c b/common/body_detection.c index 4fbc88e852..ebb1db59dc 100644 --- a/common/body_detection.c +++ b/common/body_detection.c @@ -14,8 +14,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) static struct motion_sensor_t *body_sensor = &motion_sensors[CONFIG_BODY_DETECTION_SENSOR]; @@ -31,10 +31,9 @@ static bool history_initialized; static bool body_detect_enable; STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) bool spoof_enable; -static struct body_detect_motion_data -{ +static struct body_detect_motion_data { int history[CONFIG_BODY_DETECTION_MAX_WINDOW_SIZE]; /* acceleration */ - int sum; /* sum(history) */ + int sum; /* sum(history) */ uint64_t n2_variance; /* n^2 * var(history) */ } data[2]; /* motion data for X-axis and Y-axis */ @@ -59,8 +58,8 @@ static void update_motion_data(struct body_detect_motion_data *x, int x_n) const int sum_diff = x_n - x_0; const int new_sum = x->sum + sum_diff; - x->n2_variance += sum_diff * - ((int64_t)n * (x_n + x_0) - new_sum - x->sum); + x->n2_variance += + sum_diff * ((int64_t)n * (x_n + x_0) - new_sum - x->sum); x->sum = new_sum; x->history[history_idx] = x_n; } @@ -76,8 +75,8 @@ static void update_motion_variance(void) /* return Var(X) + Var(Y) */ static uint64_t get_motion_variance(void) { - return (data[X].n2_variance + data[Y].n2_variance) - / window_size / window_size; + return (data[X].n2_variance + data[Y].n2_variance) / window_size / + window_size; } static int calculate_motion_confidence(uint64_t var) @@ -87,7 +86,7 @@ static int calculate_motion_confidence(uint64_t var) if (var > var_threshold_scaled + confidence_delta_scaled) return 100; return 100 * (var - var_threshold_scaled + confidence_delta_scaled) / - (2 * confidence_delta_scaled); + (2 * confidence_delta_scaled); } /* Change the motion state and commit the change to AP. */ @@ -105,7 +104,7 @@ void body_detect_change_state(enum body_detect_states state, bool spoof) .sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID, }; motion_sense_fifo_stage_data(&vector, NULL, 0, - __hw_clock_source_read()); + __hw_clock_source_read()); motion_sense_fifo_commit_data(); } /* change the motion state */ @@ -160,15 +159,15 @@ static void determine_threshold_scale(int range, int resolution, int rms_noise) * CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR / 100. */ const int var_noise = POW2((uint64_t)rms_noise) * - CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR * POW2(98) - / 100 / POW2(10000); + CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR * + POW2(98) / 100 / POW2(10000); - var_threshold_scaled = (uint64_t) - (CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) * - multiplier / divisor; - confidence_delta_scaled = (uint64_t) - CONFIG_BODY_DETECTION_CONFIDENCE_DELTA * + var_threshold_scaled = + (uint64_t)(CONFIG_BODY_DETECTION_VAR_THRESHOLD + var_noise) * multiplier / divisor; + confidence_delta_scaled = + (uint64_t)CONFIG_BODY_DETECTION_CONFIDENCE_DELTA * multiplier / + divisor; } void body_detect_reset(void) @@ -185,8 +184,8 @@ void body_detect_reset(void) if (odr == 0) return; determine_window_size(odr); - determine_threshold_scale(body_sensor->current_range, - resolution, rms_noise); + determine_threshold_scale(body_sensor->current_range, resolution, + rms_noise); /* initialize motion data and state */ memset(data, 0, sizeof(data)); history_idx = 0; -- cgit v1.2.1 From c4f541c7276cebc74fe678e413453b0cf2e1dc42 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:38 -0600 Subject: chip/stm32/usart_rx_interrupt-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a5c31e60c02dcfc6b16049d93a7cb1a423f9a4d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729420 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_interrupt-stm32f3.c | 50 ++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/usart_rx_interrupt-stm32f3.c diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c \ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32f3.c b/chip/stm32/usart_rx_interrupt-stm32f3.c new file mode 100644 index 0000000000..4d5060a26e --- /dev/null +++ b/chip/stm32/usart_rx_interrupt-stm32f3.c @@ -0,0 +1,49 @@ +/* Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ + +#include "usart.h" + +#include "atomic.h" +#include "common.h" +#include "queue.h" +#include "registers.h" + +static void usart_rx_init(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + + STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; + STM32_USART_CR1(base) |= STM32_USART_CR1_RE; + STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; +} + +static void usart_rx_interrupt_handler(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); + + if (status & STM32_USART_SR_RXNE) { + uint8_t byte = STM32_USART_RDR(base); + + if (!queue_add_unit(config->producer.queue, &byte)) + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); + } +} + +struct usart_rx const usart_rx_interrupt = { + .producer_ops = { + /* + * Nothing to do here, we either had enough space in the queue + * when a character came in or we dropped it already. + */ + .read = NULL, + }, + + .init = usart_rx_init, + .interrupt = usart_rx_interrupt_handler, + .info = NULL, +}; -- cgit v1.2.1 From 97f45573bc6a06c779021ec9260a7a08cade73bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:59 -0600 Subject: board/dood/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b7ccb79e24a1c5c7e5f638a5c3712cd4e140bb0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726415 Reviewed-by: Jeremy Bettis --- board/dood/led.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/board/dood/led.c b/board/dood/led.c index 3f6958b1bc..649444007d 100644 --- a/board/dood/led.c +++ b/board/dood/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -19,18 +19,25 @@ __override const int led_charge_lvl_2 = 100; /* Dood: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From a5a9c690e07cc2a91cbfd94ce22243d75e1d7492 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:15 -0600 Subject: board/stern/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic2a556b5bb9508909389502222fcae6c2b14240c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728954 Reviewed-by: Jeremy Bettis --- board/stern/led.c | 51 ++++++++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/board/stern/led.c b/board/stern/led.c index ac4813c8c0..7ae753c1ab 100644 --- a/board/stern/led.c +++ b/board/stern/led.c @@ -18,32 +18,37 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From aea41c8497ed8a1ff8369111b9f462c546d8bbb6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:18 -0600 Subject: driver/als_cm32183.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cae1fd08c11e318094b4adb6672d3cc771b0464 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729924 Reviewed-by: Jeremy Bettis --- driver/als_cm32183.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/als_cm32183.c b/driver/als_cm32183.c index 13ea942dd1..de6398491b 100644 --- a/driver/als_cm32183.c +++ b/driver/als_cm32183.c @@ -20,7 +20,7 @@ struct cm32183_drv_data { int16_t offset; }; -#define CM32183_GET_DATA(_s) ((struct cm32183_drv_data *)(_s)->drv_data) +#define CM32183_GET_DATA(_s) ((struct cm32183_drv_data *)(_s)->drv_data) /* * Read CM32183 light sensor data. @@ -31,7 +31,7 @@ static int cm32183_read_lux(int *lux) int data; ret = i2c_read16(I2C_PORT_SENSOR, CM32183_I2C_ADDR, - CM32183_REG_ALS_RESULT, &data); + CM32183_REG_ALS_RESULT, &data); if (ret) return ret; @@ -39,7 +39,7 @@ static int cm32183_read_lux(int *lux) /* * lux = data * 0.016 */ - *lux = (data * 16)/1000; + *lux = (data * 16) / 1000; return EC_SUCCESS; } @@ -60,7 +60,7 @@ static int cm32183_read(const struct motion_sensor_t *s, intv3_t v) lux_data += drv_data->offset; lux_data = lux_data * drv_data->scale + - lux_data * drv_data->uscale / 10000; + lux_data * drv_data->uscale / 10000; v[0] = lux_data; v[1] = 0; @@ -77,14 +77,13 @@ static int cm32183_read(const struct motion_sensor_t *s, intv3_t v) return EC_SUCCESS; } -static int cm32183_set_range(struct motion_sensor_t *s, int range, - int rnd) +static int cm32183_set_range(struct motion_sensor_t *s, int range, int rnd) { return EC_SUCCESS; } -static int cm32183_set_data_rate(const struct motion_sensor_t *s, - int rate, int roundup) +static int cm32183_set_data_rate(const struct motion_sensor_t *s, int rate, + int roundup) { CM32183_GET_DATA(s)->rate = rate; return EC_SUCCESS; @@ -96,14 +95,14 @@ static int cm32183_get_data_rate(const struct motion_sensor_t *s) } static int cm32183_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, int16_t temp) + const int16_t *offset, int16_t temp) { /* TODO: check calibration method */ return EC_SUCCESS; } -static int cm32183_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp) +static int cm32183_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { *offset = CM32183_GET_DATA(s)->offset; return EC_SUCCESS; @@ -117,14 +116,14 @@ static int cm32183_init(struct motion_sensor_t *s) int ret; int data; - ret = i2c_write16(s->port, s->i2c_spi_addr_flags, - CM32183_REG_CONFIGURE, CM32183_REG_CONFIGURE_CH_EN); + ret = i2c_write16(s->port, s->i2c_spi_addr_flags, CM32183_REG_CONFIGURE, + CM32183_REG_CONFIGURE_CH_EN); if (ret) return ret; - ret = i2c_read16(s->port, s->i2c_spi_addr_flags, - CM32183_REG_ALS_RESULT, &data); + ret = i2c_read16(s->port, s->i2c_spi_addr_flags, CM32183_REG_ALS_RESULT, + &data); if (ret) return ret; -- cgit v1.2.1 From 94af57e81d2f628f52f26f53acd005a19f6c99aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:01 -0600 Subject: baseboard/brask/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1189b928f6afe833b1902981d97396401b5b8f44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727857 Reviewed-by: Jeremy Bettis --- baseboard/brask/baseboard.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h index 15a451473d..7deece4b89 100644 --- a/baseboard/brask/baseboard.h +++ b/baseboard/brask/baseboard.h @@ -11,16 +11,16 @@ /* * By default, enable all console messages excepted HC */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) /* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* * This defines which pads (GPIO10/11 or GPIO64/65) are connected to * the "UART1" (NPCX_UART_PORT0) controller when used for * CONSOLE_UART. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ /* CrOS Board Info */ #define CONFIG_CBI_EEPROM @@ -59,7 +59,7 @@ /* Support Barrel Jack */ #undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 45000 /* Chipset config */ #define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 @@ -87,7 +87,7 @@ /* ADL has new low-power features that requires extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ #undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 /* Buttons */ #define CONFIG_DEDICATED_RECOVERY_BUTTON @@ -137,7 +137,7 @@ #define CONFIG_USB_PD_TCPM_NCT38XX #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -145,7 +145,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD -- cgit v1.2.1 From 46f23b636a30ccc5bddc7b68fa7b9c07751a291e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:24 -0600 Subject: board/chocodile_vpdmcu/vpd_api.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If67628b80d8ff036ef3ad70855977c222b3b198a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728145 Reviewed-by: Jeremy Bettis --- board/chocodile_vpdmcu/vpd_api.h | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/board/chocodile_vpdmcu/vpd_api.h b/board/chocodile_vpdmcu/vpd_api.h index df50f92006..e77a868214 100644 --- a/board/chocodile_vpdmcu/vpd_api.h +++ b/board/chocodile_vpdmcu/vpd_api.h @@ -12,34 +12,18 @@ #include "gpio.h" #include "usb_pd.h" -enum vpd_pin { - PIN_ADC, - PIN_CMP, - PIN_GPO -}; +enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO }; -enum vpd_gpo { - GPO_HZ, - GPO_HIGH, - GPO_LOW -}; +enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW }; enum vpd_pwr { PWR_VCONN, PWR_VBUS, }; -enum vpd_cc { - CT_OPEN, - CT_CC1, - CT_CC2 -}; +enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 }; -enum vpd_billboard { - BB_NONE, - BB_SRC, - BB_SNK -}; +enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK }; /** * Set Charge-Through Rp or Rd on CC lines -- cgit v1.2.1 From 910d511be39cb14f98fe551cb9c3c19d86d842fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:55 -0600 Subject: zephyr/projects/corsola/src/regulator.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10bd0932cd73fb32fae0559acfccfadc567f83c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730746 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/regulator.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/corsola/src/regulator.c b/zephyr/projects/corsola/src/regulator.c index 35670bda82..dae6ba13ea 100644 --- a/zephyr/projects/corsola/src/regulator.c +++ b/zephyr/projects/corsola/src/regulator.c @@ -7,13 +7,12 @@ #include "bc12/mt6360_public.h" /* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) +int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages, + uint16_t *voltages_mv) { enum mt6360_regulator_id id = index; - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); + return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv); } int board_regulator_enable(uint32_t index, uint8_t enable) -- cgit v1.2.1 From cae948244557c2f21d5857ae14edf41b7595c47d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:20 -0600 Subject: baseboard/volteer/cbi_ec_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f5b3ec0fb56528e589f138f149c3680aa3a12d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727950 Reviewed-by: Jeremy Bettis --- baseboard/volteer/cbi_ec_fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/volteer/cbi_ec_fw_config.c b/baseboard/volteer/cbi_ec_fw_config.c index e602691aeb..323b7b4703 100644 --- a/baseboard/volteer/cbi_ec_fw_config.c +++ b/baseboard/volteer/cbi_ec_fw_config.c @@ -8,7 +8,7 @@ #include "cbi_ec_fw_config.h" #include "cros_board_info.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union volteer_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 4b8eb912501ff0073e26b26c2fe7ba96045586a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:17 -0600 Subject: core/minute-ia/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie7be207aee02324b2f9f93ee1555741e8cf379c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729857 Reviewed-by: Jeremy Bettis --- core/minute-ia/task.c | 117 ++++++++++++++++++++++---------------------------- 1 file changed, 51 insertions(+), 66 deletions(-) diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c index 4eb33e295a..052df663bb 100644 --- a/core/minute-ia/task.c +++ b/core/minute-ia/task.c @@ -26,8 +26,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* Value to store in unused stack */ #define STACK_UNUSED_VALUE 0xdeadd00d @@ -43,11 +43,9 @@ CONFIG_TEST_TASK_LIST extern volatile uint32_t __in_isr; /* Task names for easier debugging */ -#define TASK(n, r, d, s, f) #n, -static const char * const task_names[] = { - "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST +#define TASK(n, r, d, s, f) #n, +static const char *const task_names[] = { + "<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK @@ -57,12 +55,12 @@ static uint64_t task_start_time; /* Time task scheduling started */ * We only keep 32-bit values for exception start/end time, to avoid * accounting errors when we service interrupt when the timer wraps around. */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static atomic_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static atomic_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif void __schedule(int desched, int resched); @@ -97,22 +95,20 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s, f) { \ - .r0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ - .flags = f, \ -}, +#define TASK(n, r, d, s, f) \ + { \ + .r0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + .flags = f, \ + }, static const struct { uint32_t r0; uint32_t pc; uint16_t stack_size; uint32_t flags; -} tasks_init[] = { - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -}; +} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK @@ -122,18 +118,13 @@ static task_ tasks[TASK_ID_COUNT]; BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8); BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); - /* Stacks for all tasks */ -#define TASK(n, r, d, s, f) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s, f) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE, 0) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8); #undef TASK - task_ *current_task, *next_task; /* @@ -151,7 +142,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -static int start_called; /* Has task swapping started */ +static int start_called; /* Has task swapping started */ static inline task_ *__task_id_to_ptr(task_id_t id) { @@ -160,7 +151,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id) void interrupt_disable(void) { - __asm__ __volatile__ ("cli"); + __asm__ __volatile__("cli"); } void interrupt_enable(void) @@ -170,16 +161,16 @@ void interrupt_enable(void) */ ASSERT(task_start_called() != 1); - __asm__ __volatile__ ("sti"); + __asm__ __volatile__("sti"); } inline bool is_interrupt_enabled(void) { uint32_t eflags = 0; - __asm__ __volatile__ ("pushfl\n" - "popl %0\n" - : "=r"(eflags)); + __asm__ __volatile__("pushfl\n" + "popl %0\n" + : "=r"(eflags)); /* Check Interrupt Enable flag */ return eflags & 0x200; @@ -251,8 +242,7 @@ uint32_t switch_handler(int desched, task_id_t resched) next = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled)); /* Only the first ISR on the (nested IRQ) stack calculates time */ - if (IS_ENABLED(CONFIG_TASK_PROFILING) && - __in_isr == 1) { + if (IS_ENABLED(CONFIG_TASK_PROFILING) && __in_isr == 1) { /* Track time in interrupts */ uint32_t t = get_time().le.lo; @@ -465,11 +455,10 @@ void mutex_lock(struct mutex *mtx) do { old_val = 0; - __asm__ __volatile__( - ASM_LOCK_PREFIX "cmpxchg %1, %2\n" - : "=a" (old_val) - : "r" (value), "m" (mtx->lock), "a" (old_val) - : "memory"); + __asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n" + : "=a"(old_val) + : "r"(value), "m"(mtx->lock), "a"(old_val) + : "memory"); if (old_val != 0) { /* Contention on the mutex */ @@ -486,11 +475,10 @@ void mutex_unlock(struct mutex *mtx) uint32_t old_val = 1, val = 0; task_ *tsk = current_task; - __asm__ __volatile__( - ASM_LOCK_PREFIX "cmpxchg %1, %2\n" - : "=a" (old_val) - : "r" (val), "m" (mtx->lock), "a" (old_val) - : "memory"); + __asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchg %1, %2\n" + : "=a"(old_val) + : "r"(val), "m"(mtx->lock), "a"(old_val) + : "memory"); if (old_val == 1) waiters = mtx->waiters; /* else? Does unlock fail - what to do then ? */ @@ -532,13 +520,13 @@ void task_print_list(void) if (IS_ENABLED(CONFIG_FPU)) { char use_fpu = tasks[i].use_fpu ? 'Y' : 'N'; - ccprintf("%4d %c %-16s %08x %11.6lld %3d/%3d %c\n", - i, is_ready, task_get_name(i), + ccprintf("%4d %c %-16s %08x %11.6lld %3d/%3d %c\n", i, + is_ready, task_get_name(i), (int)tasks[i].events, tasks[i].runtime, stackused, tasks_init[i].stack_size, use_fpu); } else { - ccprintf("%4d %c %-16s %08x %11.6lld %3d/%3d\n", - i, is_ready, task_get_name(i), + ccprintf("%4d %c %-16s %08x %11.6lld %3d/%3d\n", i, + is_ready, task_get_name(i), (int)tasks[i].events, tasks[i].runtime, stackused, tasks_init[i].stack_size); } @@ -577,12 +565,9 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, - "Print task info"); +DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); -__maybe_unused -static int command_task_ready(int argc, char **argv) +__maybe_unused static int command_task_ready(int argc, char **argv) { if (argc < 2) { ccprintf("tasks_ready: 0x%08x\n", (int)tasks_ready); @@ -596,8 +581,7 @@ static int command_task_ready(int argc, char **argv) } #ifdef CONFIG_CMD_TASKREADY -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); #endif @@ -606,7 +590,7 @@ void task_pre_init(void) int i, cs; uint32_t *stack_next = (uint32_t *)task_stacks; - __asm__ __volatile__ ("movl %%cs, %0":"=r" (cs)); + __asm__ __volatile__("movl %%cs, %0" : "=r"(cs)); /* Fill the task memory with initial values */ for (i = 0; i < TASK_ID_COUNT; i++) { @@ -638,12 +622,12 @@ void task_pre_init(void) sp[7] = 0xea; /* EAX */ #endif /* For IRET */ - sp[8] = tasks_init[i].pc; /* pc */ + sp[8] = tasks_init[i].pc; /* pc */ sp[9] = cs; sp[10] = INITIAL_EFLAGS; - sp[11] = (uint32_t) task_exit_trap; - sp[12] = tasks_init[i].r0; /* task argument */ + sp[11] = (uint32_t)task_exit_trap; + sp[12] = tasks_init[i].r0; /* task argument */ sp[13] = 0x00; sp[14] = 0x00; sp[15] = 0x00; @@ -656,7 +640,8 @@ void task_pre_init(void) 0x00, 0x00, /* Status[0-15] */ 0xff, 0xff, /* unused */ 0xff, 0xff, /* Tag[0-15] */ - 0xff, 0xff};/* unused */ + 0xff, 0xff + }; /* unused */ /* Copy default x86 FPU state for each task */ memcpy(tasks[i].fp_ctx, default_fp_ctx, -- cgit v1.2.1 From 22b958eff1b23d6711a67766bcc1505e2020f299 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:27 -0600 Subject: common/wireless.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I292179d2a26096d10e8afe0df51bae90d2844fdf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729814 Reviewed-by: Jeremy Bettis --- common/wireless.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/common/wireless.c b/common/wireless.c index d1f5cad645..fffe66cb55 100644 --- a/common/wireless.c +++ b/common/wireless.c @@ -34,13 +34,11 @@ static int suspend_flags = CONFIG_WIRELESS_SUSPEND; static void wireless_enable(int flags) { #ifdef WIRELESS_GPIO_WLAN - gpio_set_level(WIRELESS_GPIO_WLAN, - flags & EC_WIRELESS_SWITCH_WLAN); + gpio_set_level(WIRELESS_GPIO_WLAN, flags & EC_WIRELESS_SWITCH_WLAN); #endif #ifdef WIRELESS_GPIO_WWAN - gpio_set_level(WIRELESS_GPIO_WWAN, - flags & EC_WIRELESS_SWITCH_WWAN); + gpio_set_level(WIRELESS_GPIO_WWAN, flags & EC_WIRELESS_SWITCH_WWAN); #endif #ifdef WIRELESS_GPIO_BLUETOOTH @@ -57,7 +55,6 @@ static void wireless_enable(int flags) !(flags & EC_WIRELESS_SWITCH_WLAN_POWER)); #endif /* CONFIG_WLAN_POWER_ACTIVE_LOW */ #endif - } static int wireless_get(void) @@ -126,7 +123,7 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args) (p->now_flags & p->now_mask)); suspend_flags = (suspend_flags & ~p->suspend_mask) | - (p->suspend_flags & p->suspend_mask); + (p->suspend_flags & p->suspend_mask); /* And return the current flags */ r->now_flags = wireless_get(); @@ -134,8 +131,7 @@ static enum ec_status wireless_enable_cmd(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS, - wireless_enable_cmd, +DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_WIRELESS, wireless_enable_cmd, EC_VER_MASK(0) | EC_VER_MASK(1)); static int command_wireless(int argc, char **argv) @@ -164,6 +160,5 @@ static int command_wireless(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(wireless, command_wireless, - "[now [suspend]]", +DECLARE_CONSOLE_COMMAND(wireless, command_wireless, "[now [suspend]]", "Get/set wireless flags"); -- cgit v1.2.1 From 9e454d41e19b72aad96802ee71fdd439f1cae514 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:02 -0600 Subject: driver/led/aw20198.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c209550976809ffb578e59288c244d229045996 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730013 Reviewed-by: Jeremy Bettis --- driver/led/aw20198.h | 64 ++++++++++++++++++++++++++-------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/driver/led/aw20198.h b/driver/led/aw20198.h index bbb284cc3a..84aacfc7db 100644 --- a/driver/led/aw20198.h +++ b/driver/led/aw20198.h @@ -7,38 +7,38 @@ #define __CROS_EC_DRIVER_LED_AW20198_H /* This depends on AD0 and AD1. (GRD, GRD) = 0x20. */ -#define AW20198_I2C_ADDR_FLAG 0x20 - -#define AW20198_ROW_SIZE 6 -#define AW20198_COL_SIZE 11 -#define AW20198_GRID_SIZE (AW20198_COL_SIZE * AW20198_ROW_SIZE) - -#define AW20198_PAGE_FUNC 0xC0 -#define AW20198_PAGE_PWM 0xC1 -#define AW20198_PAGE_SCALE 0xC2 - -#define AW20198_REG_GCR 0x00 -#define AW20198_REG_GCR_SWSEL_MASK 0xF0 -#define AW20198_REG_GCR_SWSEL_SHIFT 4 -#define AW20198_REG_GCR_SW1_ACTIVE 0 -#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE 1 -#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE 2 -#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE 3 -#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE 4 -#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE 5 -#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE 6 -#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE 7 -#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE 8 -#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE 9 -#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE 10 - -#define AW20198_REG_GCC 0x01 -#define AW20198_REG_RSTN 0x2F -#define AW20198_REG_MIXCR 0x46 -#define AW20198_REG_PAGE 0xF0 - -#define AW20198_RESET_MAGIC 0xAE +#define AW20198_I2C_ADDR_FLAG 0x20 + +#define AW20198_ROW_SIZE 6 +#define AW20198_COL_SIZE 11 +#define AW20198_GRID_SIZE (AW20198_COL_SIZE * AW20198_ROW_SIZE) + +#define AW20198_PAGE_FUNC 0xC0 +#define AW20198_PAGE_PWM 0xC1 +#define AW20198_PAGE_SCALE 0xC2 + +#define AW20198_REG_GCR 0x00 +#define AW20198_REG_GCR_SWSEL_MASK 0xF0 +#define AW20198_REG_GCR_SWSEL_SHIFT 4 +#define AW20198_REG_GCR_SW1_ACTIVE 0 +#define AW20198_REG_GCR_SW1_TO_SW2_ACTIVE 1 +#define AW20198_REG_GCR_SW1_TO_SW3_ACTIVE 2 +#define AW20198_REG_GCR_SW1_TO_SW4_ACTIVE 3 +#define AW20198_REG_GCR_SW1_TO_SW5_ACTIVE 4 +#define AW20198_REG_GCR_SW1_TO_SW6_ACTIVE 5 +#define AW20198_REG_GCR_SW1_TO_SW7_ACTIVE 6 +#define AW20198_REG_GCR_SW1_TO_SW8_ACTIVE 7 +#define AW20198_REG_GCR_SW1_TO_SW9_ACTIVE 8 +#define AW20198_REG_GCR_SW1_TO_SW10_ACTIVE 9 +#define AW20198_REG_GCR_SW1_TO_SW11_ACTIVE 10 + +#define AW20198_REG_GCC 0x01 +#define AW20198_REG_RSTN 0x2F +#define AW20198_REG_MIXCR 0x46 +#define AW20198_REG_PAGE 0xF0 + +#define AW20198_RESET_MAGIC 0xAE extern const struct rgbkbd_drv aw20198_drv; -#endif /* __CROS_EC_DRIVER_LED_AW20198_H */ +#endif /* __CROS_EC_DRIVER_LED_AW20198_H */ -- cgit v1.2.1 From b4495826a2bd4b1e272f6f20867d423d5b3ad125 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:52 -0600 Subject: board/arcada_ish/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5ce746396ff17aa291f68fde4a1f259874114928 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728009 Reviewed-by: Jeremy Bettis --- board/arcada_ish/board.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/arcada_ish/board.c b/board/arcada_ish/board.c index b23784cd38..9fcb250b14 100644 --- a/board/arcada_ish/board.c +++ b/board/arcada_ish/board.c @@ -42,11 +42,9 @@ static struct stprivate_data g_lis2dh_data; static struct lis2mdl_private_data lis2mdl_a_data; /* Matrix to rotate lid sensor into standard reference frame */ -const mat33_fp_t lid_rot_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -155,8 +153,7 @@ int board_sensor_at_360(void) * closed at 0 degrees. Ignore the hall sensor when the lid close is * also active. */ - return lid_is_open() && - !gpio_get_level(GPIO_TABLET_MODE_L); + return lid_is_open() && !gpio_get_level(GPIO_TABLET_MODE_L); } /* Initialize board. */ -- cgit v1.2.1 From e983c174fb1a841d1c512b19cead6fb7f39a8446 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:27 -0600 Subject: chip/ish/hbm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb1e01bb02c2bb9955135221a51f189c81543eef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729176 Reviewed-by: Jeremy Bettis --- chip/ish/hbm.h | 101 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 50 insertions(+), 51 deletions(-) diff --git a/chip/ish/hbm.h b/chip/ish/hbm.h index edfb587d21..bce3c37c36 100644 --- a/chip/ish/hbm.h +++ b/chip/ish/hbm.h @@ -11,65 +11,64 @@ #include "heci_client.h" -#define HBM_MAJOR_VERSION 1 +#define HBM_MAJOR_VERSION 1 #ifdef HECI_ENABLE_DMA -#define HBM_MINOR_VERSION 2 +#define HBM_MINOR_VERSION 2 #else -#define HBM_MINOR_VERSION 0 +#define HBM_MINOR_VERSION 0 #endif #define __packed __attribute__((packed)) -#define HECI_MSG_REPONSE_FLAG 0x80 +#define HECI_MSG_REPONSE_FLAG 0x80 enum HECI_BUS_MSG { /* requests */ - HECI_BUS_MSG_VERSION_REQ = 1, - HECI_BUS_MSG_HOST_STOP_REQ = 2, - HECI_BUS_MSG_ME_STOP_REQ = 3, - HECI_BUS_MSG_HOST_ENUM_REQ = 4, - HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5, - HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6, - HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7, - HECI_BUS_MSG_FLOW_CONTROL = 8, - HECI_BUS_MSG_RESET_REQ = 9, - HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A, - HECI_BUS_MSG_DMA_REQ = 0x10, - HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11, - HECI_BUS_MSG_DMA_XFER_REQ = 0x12, + HECI_BUS_MSG_VERSION_REQ = 1, + HECI_BUS_MSG_HOST_STOP_REQ = 2, + HECI_BUS_MSG_ME_STOP_REQ = 3, + HECI_BUS_MSG_HOST_ENUM_REQ = 4, + HECI_BUS_MSG_HOST_CLIENT_PROP_REQ = 5, + HECI_BUS_MSG_CLIENT_CONNECT_REQ = 6, + HECI_BUS_MSG_CLIENT_DISCONNECT_REQ = 7, + HECI_BUS_MSG_FLOW_CONTROL = 8, + HECI_BUS_MSG_RESET_REQ = 9, + HECI_BUS_MSG_ADD_CLIENT_REQ = 0x0A, + HECI_BUS_MSG_DMA_REQ = 0x10, + HECI_BUS_MSG_DMA_ALLOC_NOTIFY = 0x11, + HECI_BUS_MSG_DMA_XFER_REQ = 0x12, /* responses */ - HECI_BUS_MSG_VERSION_RESP = + HECI_BUS_MSG_VERSION_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_VERSION_REQ), - HECI_BUS_MSG_HOST_STOP_RESP = + HECI_BUS_MSG_HOST_STOP_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_STOP_REQ), - HECI_BUS_MSG_HOST_ENUM_RESP = + HECI_BUS_MSG_HOST_ENUM_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_ENUM_REQ), - HECI_BUS_MSG_HOST_CLIENT_PROP_RESP = + HECI_BUS_MSG_HOST_CLIENT_PROP_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_HOST_CLIENT_PROP_REQ), - HECI_BUS_MSG_CLIENT_CONNECT_RESP = + HECI_BUS_MSG_CLIENT_CONNECT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_CONNECT_REQ), - HECI_BUS_MSG_CLIENT_DISCONNECT_RESP = + HECI_BUS_MSG_CLIENT_DISCONNECT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_CLIENT_DISCONNECT_REQ), - HECI_BUS_MSG_RESET_RESP = + HECI_BUS_MSG_RESET_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_RESET_REQ), - HECI_BUS_MSG_ADD_CLIENT_RESP = + HECI_BUS_MSG_ADD_CLIENT_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_ADD_CLIENT_REQ), - HECI_BUS_MSG_DMA_RESP = - (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ), - HECI_BUS_MSG_DMA_ALLOC_RESP = + HECI_BUS_MSG_DMA_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_REQ), + HECI_BUS_MSG_DMA_ALLOC_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_ALLOC_NOTIFY), - HECI_BUS_MSG_DMA_XFER_RESP = + HECI_BUS_MSG_DMA_XFER_RESP = (HECI_MSG_REPONSE_FLAG | HECI_BUS_MSG_DMA_XFER_REQ) }; enum { - HECI_CONNECT_STATUS_SUCCESS = 0, - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1, - HECI_CONNECT_STATUS_ALREADY_EXISTS = 2, - HECI_CONNECT_STATUS_REJECTED = 3, + HECI_CONNECT_STATUS_SUCCESS = 0, + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND = 1, + HECI_CONNECT_STATUS_ALREADY_EXISTS = 2, + HECI_CONNECT_STATUS_REJECTED = 3, HECI_CONNECT_STATUS_INVALID_PARAMETER = 4, - HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5, + HECI_CONNECT_STATUS_INACTIVE_CLIENT = 5, }; struct hbm_version { @@ -101,14 +100,14 @@ struct hbm_client_prop_req { uint8_t reserved[2]; } __packed; -#define CLIENT_DMA_ENABLE 0x80 +#define CLIENT_DMA_ENABLE 0x80 struct hbm_client_properties { struct heci_guid protocol_name; /* heci client protocol ID */ - uint8_t protocol_version; /* protocol version */ + uint8_t protocol_version; /* protocol version */ /* max connection from host to client. currently only 1 is allowed */ uint8_t max_number_of_connections; - uint8_t fixed_address; /* not yet supported */ + uint8_t fixed_address; /* not yet supported */ uint8_t single_recv_buf; /* not yet supported */ uint32_t max_msg_length; /* max payload size */ /* not yet supported. [7] enable/disable, [6:0] dma length */ @@ -168,13 +167,13 @@ struct hbm_host_stop_res { struct hbm_h2i { uint8_t cmd; union { - struct hbm_version_req ver_req; - struct hbm_enum_req enum_req; - struct hbm_client_prop_req client_prop_req; - struct hbm_client_connect_req client_connect_req; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_req client_disconnect_req; - struct hbm_host_stop_req host_stop_req; + struct hbm_version_req ver_req; + struct hbm_enum_req enum_req; + struct hbm_client_prop_req client_prop_req; + struct hbm_client_connect_req client_connect_req; + struct hbm_flow_control flow_ctrl; + struct hbm_client_disconnect_req client_disconnect_req; + struct hbm_host_stop_req host_stop_req; } data; } __packed; @@ -182,13 +181,13 @@ struct hbm_h2i { struct hbm_i2h { uint8_t cmd; union { - struct hbm_version_res ver_res; - struct hbm_enum_res enum_res; - struct hbm_client_prop_res client_prop_res; - struct hbm_client_connect_res client_connect_res; - struct hbm_flow_control flow_ctrl; - struct hbm_client_disconnect_res client_disconnect_res; - struct hbm_host_stop_res host_stop_res; + struct hbm_version_res ver_res; + struct hbm_enum_res enum_res; + struct hbm_client_prop_res client_prop_res; + struct hbm_client_connect_res client_connect_res; + struct hbm_flow_control flow_ctrl; + struct hbm_client_disconnect_res client_disconnect_res; + struct hbm_host_stop_res host_stop_res; } data; } __packed; -- cgit v1.2.1 From 08e2b594bfb3861b7f9ce1729e8960e237a751fb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:47 -0600 Subject: common/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a377f918fca365fa3717c3d3c222bf98486c623 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729647 Reviewed-by: Jeremy Bettis --- common/flash.c | 192 +++++++++++++++++++++++++-------------------------------- 1 file changed, 84 insertions(+), 108 deletions(-) diff --git a/common/flash.c b/common/flash.c index 055064d029..9dd4a1c0d2 100644 --- a/common/flash.c +++ b/common/flash.c @@ -42,14 +42,14 @@ /* Persistent protection state - emulates a SPI status register for flashrom */ /* NOTE: It's not expected that RO and RW will support * differing PSTATE versions. */ -#define PERSIST_STATE_VERSION 3 /* Expected persist_state.version */ +#define PERSIST_STATE_VERSION 3 /* Expected persist_state.version */ /* Flags for persist_state.flags */ /* Protect persist state and RO firmware at boot */ #define PERSIST_FLAG_PROTECT_RO 0x02 -#define PSTATE_VALID_FLAGS BIT(0) -#define PSTATE_VALID_SERIALNO BIT(1) -#define PSTATE_VALID_MAC_ADDR BIT(2) +#define PSTATE_VALID_FLAGS BIT(0) +#define PSTATE_VALID_SERIALNO BIT(1) +#define PSTATE_VALID_MAC_ADDR BIT(2) /* * Error correction code operates on blocks equal to CONFIG_FLASH_WRITE_SIZE @@ -59,10 +59,10 @@ * size of the structure to ensure that it is also a multiple of the alignment. */ struct persist_state { - uint8_t version; /* Version of this struct */ - uint8_t flags; /* Lock flags (PERSIST_FLAG_*) */ - uint8_t valid_fields; /* Flags for valid data. */ - uint8_t reserved; /* Reserved; set 0 */ + uint8_t version; /* Version of this struct */ + uint8_t flags; /* Lock flags (PERSIST_FLAG_*) */ + uint8_t valid_fields; /* Flags for valid data. */ + uint8_t reserved; /* Reserved; set 0 */ #ifdef CONFIG_SERIALNO_LEN uint8_t serialno[CONFIG_SERIALNO_LEN]; /* Serial number. */ #endif /* CONFIG_SERIALNO_LEN */ @@ -91,11 +91,11 @@ BUILD_ASSERT(sizeof(struct persist_state) <= CONFIG_FW_PSTATE_SIZE); * lock the flash at boot. */ #if (CONFIG_FLASH_ERASED_VALUE32 == -1U) -#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */ -#define PSTATE_MAGIC_LOCKED 0x00000000 /* "" */ +#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */ +#define PSTATE_MAGIC_LOCKED 0x00000000 /* "" */ #elif (CONFIG_FLASH_ERASED_VALUE32 == 0) -#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */ -#define PSTATE_MAGIC_LOCKED 0x5f5f5057 /* "WP__" */ +#define PSTATE_MAGIC_UNLOCKED 0x4f4e5057 /* "WPNO" */ +#define PSTATE_MAGIC_LOCKED 0x5f5f5057 /* "WP__" */ #else /* What kind of wacky flash doesn't erase all bits to 1 or 0? */ #error "PSTATE needs magic values for this flash architecture." @@ -171,8 +171,8 @@ int crec_flash_bank_index(int offset) return bank_offset; for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) { - int all_sector_size = flash_bank_array[i].count << - flash_bank_array[i].size_exp; + int all_sector_size = flash_bank_array[i].count + << flash_bank_array[i].size_exp; if (offset >= all_sector_size) { offset -= all_sector_size; bank_offset += flash_bank_array[i].count; @@ -217,16 +217,15 @@ int crec_flash_bank_start_offset(int bank) return offset; } -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ static int flash_range_ok(int offset, int size_req, int align) { - if (offset < 0 || size_req < 0 || - offset > CONFIG_FLASH_SIZE_BYTES || + if (offset < 0 || size_req < 0 || offset > CONFIG_FLASH_SIZE_BYTES || size_req > CONFIG_FLASH_SIZE_BYTES || offset + size_req > CONFIG_FLASH_SIZE_BYTES || (offset | size_req) & (align - 1)) - return 0; /* Invalid range */ + return 0; /* Invalid range */ return 1; } @@ -251,7 +250,7 @@ static const char *flash_physical_dataptr(int offset) int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp) { if (!flash_range_ok(offset, size_req, align)) - return -1; /* Invalid range */ + return -1; /* Invalid range */ if (ptrp) *ptrp = flash_physical_dataptr(offset); @@ -268,8 +267,8 @@ int crec_flash_dataptr(int offset, int size_req, int align, const char **ptrp) static uint32_t flash_read_pstate(void) { const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); if ((pstate->version == PERSIST_STATE_VERSION) && (pstate->valid_fields & PSTATE_VALID_FLAGS) && @@ -314,8 +313,6 @@ static int flash_write_pstate_data(struct persist_state *newpstate) (const char *)newpstate); } - - /** * Validate and Init persistent state datastructure. * @@ -342,8 +339,8 @@ static int flash_write_pstate(uint32_t flags) { struct persist_state newpstate; const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); /* Only check the flags we write to pstate */ flags &= EC_FLASH_PROTECT_RO_AT_BOOT; @@ -372,8 +369,8 @@ static int flash_write_pstate(uint32_t flags) const char *crec_flash_read_pstate_serial(void) { const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); if ((pstate->version == PERSIST_STATE_VERSION) && (pstate->valid_fields & PSTATE_VALID_SERIALNO)) { @@ -394,8 +391,8 @@ int crec_flash_write_pstate_serial(const char *serialno) int length; struct persist_state newpstate; const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); /* Check that this is OK */ if (!serialno) @@ -432,8 +429,8 @@ int crec_flash_write_pstate_serial(const char *serialno) const char *crec_flash_read_pstate_mac_addr(void) { const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); if ((pstate->version == PERSIST_STATE_VERSION) && (pstate->valid_fields & PSTATE_VALID_MAC_ADDR)) { @@ -454,8 +451,8 @@ int crec_flash_write_pstate_mac_addr(const char *mac_addr) int length; struct persist_state newpstate; const struct persist_state *pstate = - (const struct persist_state *) - flash_physical_dataptr(CONFIG_FW_PSTATE_OFF); + (const struct persist_state *)flash_physical_dataptr( + CONFIG_FW_PSTATE_OFF); /* Check that this is OK, data is valid and fits in the region. */ if (!mac_addr) { @@ -559,10 +556,9 @@ static int flash_write_pstate(uint32_t flags) * Write a new pstate. We can overwrite the existing value, because * we're only moving bits from the erased state to the unerased state. */ - return crec_flash_physical_write(get_pstate_addr() - - CONFIG_PROGRAM_MEMORY_BASE, - sizeof(new_pstate), - (const char *)&new_pstate); + return crec_flash_physical_write( + get_pstate_addr() - CONFIG_PROGRAM_MEMORY_BASE, + sizeof(new_pstate), (const char *)&new_pstate); } #endif /* !CONFIG_FLASH_PSTATE_BANK */ @@ -575,7 +571,7 @@ int crec_flash_is_erased(uint32_t offset, int size) #ifdef CONFIG_MAPPED_STORAGE /* Use pointer directly to flash */ if (crec_flash_dataptr(offset, size, sizeof(uint32_t), - (const char **)&ptr) < 0) + (const char **)&ptr) < 0) return 0; crec_flash_lock_mapped_storage(1); @@ -583,7 +579,7 @@ int crec_flash_is_erased(uint32_t offset, int size) if (*ptr != CONFIG_FLASH_ERASED_VALUE32) { crec_flash_lock_mapped_storage(0); return 0; - } + } crec_flash_lock_mapped_storage(0); #else @@ -604,7 +600,6 @@ int crec_flash_is_erased(uint32_t offset, int size) for (bsize /= sizeof(uint32_t); bsize > 0; bsize--, ptr++) if (*ptr != CONFIG_FLASH_ERASED_VALUE32) return 0; - } #endif @@ -657,11 +652,11 @@ static void flash_abort_or_invalidate_hash(int offset, int size) * jump to RW after the timeout. */ if ((offset >= CONFIG_RW_MEM_OFF && - offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) || + offset < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) || ((offset + size) > CONFIG_RW_MEM_OFF && - (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) || + (offset + size) <= (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)) || (offset < CONFIG_RW_MEM_OFF && - (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE))) + (offset + size) > (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE))) rwsig_abort(); #endif } @@ -669,7 +664,7 @@ static void flash_abort_or_invalidate_hash(int offset, int size) int crec_flash_write(int offset, int size, const char *data) { if (!flash_range_ok(offset, size, CONFIG_FLASH_WRITE_SIZE)) - return EC_ERROR_INVAL; /* Invalid range */ + return EC_ERROR_INVAL; /* Invalid range */ flash_abort_or_invalidate_hash(offset, size); @@ -680,7 +675,7 @@ int crec_flash_erase(int offset, int size) { #ifndef CONFIG_FLASH_MULTIPLE_REGION if (!flash_range_ok(offset, size, CONFIG_FLASH_ERASE_SIZE)) - return EC_ERROR_INVAL; /* Invalid range */ + return EC_ERROR_INVAL; /* Invalid range */ #endif flash_abort_or_invalidate_hash(offset, size); @@ -736,7 +731,7 @@ uint32_t crec_flash_get_protect(void) uint32_t flags = 0; int i; /* Region protection status */ - int not_protected[FLASH_REGION_COUNT] = {0}; + int not_protected[FLASH_REGION_COUNT] = { 0 }; #ifdef CONFIG_ROLLBACK /* Flags that must be set to set ALL_NOW flag. */ const uint32_t all_flags = EC_FLASH_PROTECT_RO_NOW | @@ -759,11 +754,11 @@ uint32_t crec_flash_get_protect(void) /* Scan flash protection */ for (i = 0; i < PHYSICAL_BANKS; i++) { int is_ro = (i >= WP_BANK_OFFSET && - i < WP_BANK_OFFSET + WP_BANK_COUNT); + i < WP_BANK_OFFSET + WP_BANK_COUNT); enum flash_region region = is_ro ? FLASH_REGION_RO : - FLASH_REGION_RW; + FLASH_REGION_RW; int bank_flag = is_ro ? EC_FLASH_PROTECT_RO_NOW : - EC_FLASH_PROTECT_RW_NOW; + EC_FLASH_PROTECT_RW_NOW; #ifdef CONFIG_ROLLBACK if (i >= ROLLBACK_BANK_OFFSET && @@ -824,10 +819,11 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags) { int retval = EC_SUCCESS; int rv; - int old_flags_at_boot = crec_flash_get_protect() & + int old_flags_at_boot = + crec_flash_get_protect() & (EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | - EC_FLASH_PROTECT_ALL_AT_BOOT); + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | + EC_FLASH_PROTECT_ALL_AT_BOOT); int new_flags_at_boot = old_flags_at_boot; /* Sanitize input flags */ @@ -908,8 +904,8 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags) * All subsequent flags only work if write protect is enabled (that is, * hardware WP flag) *and* RO is protected at boot (software WP flag). */ - if ((~crec_flash_get_protect()) & (EC_FLASH_PROTECT_GPIO_ASSERTED | - EC_FLASH_PROTECT_RO_AT_BOOT)) + if ((~crec_flash_get_protect()) & + (EC_FLASH_PROTECT_GPIO_ASSERTED | EC_FLASH_PROTECT_RO_AT_BOOT)) return retval; /* @@ -948,8 +944,7 @@ int crec_flash_set_protect(uint32_t mask, uint32_t flags) * we're now protecting the RO region with SW WP. */ if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) && - (EC_FLASH_PROTECT_GPIO_ASSERTED & - crec_flash_get_protect())) + (EC_FLASH_PROTECT_GPIO_ASSERTED & crec_flash_get_protect())) cbi_latch_eeprom_wp(); } @@ -992,8 +987,7 @@ static int command_flash_info(int argc, char **argv) #ifdef CONFIG_FLASH_MULTIPLE_REGION ccprintf("Regions:\n"); for (i = 0; i < ARRAY_SIZE(flash_bank_array); i++) { - ccprintf(" %d region%s:\n", - flash_bank_array[i].count, + ccprintf(" %d region%s:\n", flash_bank_array[i].count, (flash_bank_array[i].count == 1 ? "" : "s")); ccprintf(" Erase: %4d B (to %d-bits)\n", 1 << flash_bank_array[i].erase_size_exp, @@ -1049,8 +1043,7 @@ static int command_flash_info(int argc, char **argv) ccputs("\n"); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(flashinfo, command_flash_info, NULL, "Print flash info"); #endif /* CONFIG_CMD_FLASHINFO */ @@ -1071,8 +1064,7 @@ static int command_flash_erase(int argc, char **argv) ccprintf("Erasing %d bytes at 0x%x...\n", size, offset); return crec_flash_erase(offset, size); } -DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase, - "offset size", +DECLARE_CONSOLE_COMMAND(flasherase, command_flash_erase, "offset size", "Erase flash"); static int command_flash_write(int argc, char **argv) @@ -1112,8 +1104,7 @@ static int command_flash_write(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write, - "offset size", +DECLARE_CONSOLE_COMMAND(flashwrite, command_flash_write, "offset size", "Write pattern to flash"); static int command_flash_read(int argc, char **argv) @@ -1160,8 +1151,7 @@ static int command_flash_read(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(flashread, command_flash_read, - "offset [size]", +DECLARE_CONSOLE_COMMAND(flashread, command_flash_read, "offset [size]", "Read flash"); #endif @@ -1203,7 +1193,7 @@ static int command_flash_wp(int argc, char **argv) /* Do this last, since anything starting with 'n' means "no" */ if (parse_bool(argv[1], &val)) return crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT, - val ? -1 : 0); + val ? -1 : 0); return EC_ERROR_PARAM1; } @@ -1215,7 +1205,8 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp, #ifdef CONFIG_ROLLBACK " | rb | norb" #endif - , "Modify flash write protect"); + , + "Modify flash write protect"); #endif /* CONFIG_CMD_FLASH_WP */ /*****************************************************************************/ @@ -1231,8 +1222,8 @@ DECLARE_CONSOLE_COMMAND(flashwp, command_flash_wp, * region belonging to the EC. TODO(crbug.com/529365): Handle fmap_base * correctly in flashrom, dump_fmap, etc. and remove EC_FLASH_REGION_START. */ -#define EC_FLASH_REGION_START MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define EC_FLASH_REGION_START \ + MIN(CONFIG_EC_PROTECTED_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_OFF) static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) { @@ -1263,8 +1254,8 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) * Compute the ideal amount of data for the host to send us, * based on the maximum response size and the ideal write size. */ - ideal_size = (args->response_max - - sizeof(struct ec_params_flash_write)) & + ideal_size = + (args->response_max - sizeof(struct ec_params_flash_write)) & ~(CONFIG_FLASH_WRITE_IDEAL_SIZE - 1); /* * If we can't get at least one ideal block, then just want @@ -1272,9 +1263,8 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) */ if (!ideal_size) ideal_size = (args->response_max - - sizeof(struct ec_params_flash_write)) & - ~(CONFIG_FLASH_WRITE_SIZE - 1); - + sizeof(struct ec_params_flash_write)) & + ~(CONFIG_FLASH_WRITE_SIZE - 1); if (args->version >= 2) { args->response_size = sizeof(struct ec_response_flash_info_2); @@ -1319,16 +1309,14 @@ static enum ec_status flash_command_get_info(struct host_cmd_handler_args *args) #endif } return EC_RES_SUCCESS; -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ } #ifdef CONFIG_FLASH_MULTIPLE_REGION #define FLASH_INFO_VER EC_VER_MASK(2) #else #define FLASH_INFO_VER (EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2)) #endif -DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO, - flash_command_get_info, FLASH_INFO_VER); - +DECLARE_HOST_COMMAND(EC_CMD_FLASH_INFO, flash_command_get_info, FLASH_INFO_VER); static enum ec_status flash_command_read(struct host_cmd_handler_args *args) { @@ -1345,9 +1333,7 @@ static enum ec_status flash_command_read(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ, - flash_command_read, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_FLASH_READ, flash_command_read, EC_VER_MASK(0)); /** * Flash write command @@ -1376,8 +1362,7 @@ static enum ec_status flash_command_write(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE, - flash_command_write, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_WRITE, flash_command_write, EC_VER_MASK(0) | EC_VER_MASK(EC_VER_FLASH_WRITE)); #ifndef CONFIG_FLASH_MULTIPLE_REGION @@ -1453,13 +1438,12 @@ static enum ec_status flash_command_erase(struct host_cmd_handler_args *args) return rc; } - DECLARE_HOST_COMMAND(EC_CMD_FLASH_ERASE, flash_command_erase, - EC_VER_MASK(0) + EC_VER_MASK(0) #ifdef CONFIG_FLASH_DEFERRED_ERASE - | EC_VER_MASK(1) + | EC_VER_MASK(1) #endif - ); +); static enum ec_status flash_command_protect(struct host_cmd_handler_args *args) { @@ -1484,12 +1468,11 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args) r->flags = crec_flash_get_protect(); /* Indicate which flags are valid on this platform */ - r->valid_flags = - EC_FLASH_PROTECT_GPIO_ASSERTED | - EC_FLASH_PROTECT_ERROR_STUCK | - EC_FLASH_PROTECT_ERROR_INCONSISTENT | - EC_FLASH_PROTECT_ERROR_UNKNOWN | - crec_flash_physical_get_valid_flags(); + r->valid_flags = EC_FLASH_PROTECT_GPIO_ASSERTED | + EC_FLASH_PROTECT_ERROR_STUCK | + EC_FLASH_PROTECT_ERROR_INCONSISTENT | + EC_FLASH_PROTECT_ERROR_UNKNOWN | + crec_flash_physical_get_valid_flags(); r->writable_flags = crec_flash_physical_get_writable_flags(r->flags); args->response_size = sizeof(*r); @@ -1502,8 +1485,7 @@ static enum ec_status flash_command_protect(struct host_cmd_handler_args *args) * temporary workaround for a problem in the cros_ec driver. Drop * EC_VER_MASK(0) once cros_ec driver can send the correct version. */ -DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT, - flash_command_protect, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_PROTECT, flash_command_protect, EC_VER_MASK(0) | EC_VER_MASK(1)); static enum ec_status @@ -1515,23 +1497,21 @@ flash_command_region_info(struct host_cmd_handler_args *args) switch (p->region) { case EC_FLASH_REGION_RO: r->offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF - - EC_FLASH_REGION_START; + CONFIG_RO_STORAGE_OFF - EC_FLASH_REGION_START; r->size = EC_FLASH_REGION_RO_SIZE; break; case EC_FLASH_REGION_ACTIVE: r->offset = flash_get_rw_offset(system_get_active_copy()) - - EC_FLASH_REGION_START; + EC_FLASH_REGION_START; r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE; break; case EC_FLASH_REGION_WP_RO: - r->offset = CONFIG_WP_STORAGE_OFF - - EC_FLASH_REGION_START; + r->offset = CONFIG_WP_STORAGE_OFF - EC_FLASH_REGION_START; r->size = CONFIG_WP_STORAGE_SIZE; break; case EC_FLASH_REGION_UPDATE: r->offset = flash_get_rw_offset(system_get_update_copy()) - - EC_FLASH_REGION_START; + EC_FLASH_REGION_START; r->size = CONFIG_EC_WRITABLE_STORAGE_SIZE; break; default: @@ -1541,11 +1521,9 @@ flash_command_region_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO, - flash_command_region_info, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_REGION_INFO, flash_command_region_info, EC_VER_MASK(EC_VER_FLASH_REGION_INFO)); - #ifdef CONFIG_FLASH_SELECT_REQUIRED static enum ec_status flash_command_select(struct host_cmd_handler_args *args) @@ -1554,8 +1532,6 @@ static enum ec_status flash_command_select(struct host_cmd_handler_args *args) return crec_board_flash_select(p->select); } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT, - flash_command_select, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_FLASH_SELECT, flash_command_select, EC_VER_MASK(0)); #endif /* CONFIG_FLASH_SELECT_REQUIRED */ -- cgit v1.2.1 From db2c8d2ee26278a94def563417e1855b9688dd02 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:13 -0600 Subject: include/usb_hid_touchpad.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1018c156bfdc1cc231f434463409cfaa0da56505 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730435 Reviewed-by: Jeremy Bettis --- include/usb_hid_touchpad.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/include/usb_hid_touchpad.h b/include/usb_hid_touchpad.h index 1e6d4cf832..67922cc8ff 100644 --- a/include/usb_hid_touchpad.h +++ b/include/usb_hid_touchpad.h @@ -10,27 +10,27 @@ #define USB_HID_TOUCHPAD_TIMESTAMP_UNIT 100 /* usec */ -#define REPORT_ID_TOUCHPAD 0x01 -#define REPORT_ID_DEVICE_CAPS 0x0A -#define REPORT_ID_DEVICE_CERT 0x0B +#define REPORT_ID_TOUCHPAD 0x01 +#define REPORT_ID_DEVICE_CAPS 0x0A +#define REPORT_ID_DEVICE_CERT 0x0B -#define MAX_FINGERS 5 +#define MAX_FINGERS 5 struct usb_hid_touchpad_report { uint8_t id; /* 0x01 */ struct { - uint16_t confidence:1; - uint16_t tip:1; - uint16_t inrange:1; - uint16_t id:4; - uint16_t pressure:9; - uint16_t width:12; - uint16_t height:12; - uint16_t x:12; - uint16_t y:12; + uint16_t confidence : 1; + uint16_t tip : 1; + uint16_t inrange : 1; + uint16_t id : 4; + uint16_t pressure : 9; + uint16_t width : 12; + uint16_t height : 12; + uint16_t x : 12; + uint16_t y : 12; } __packed finger[MAX_FINGERS]; - uint8_t count:7; - uint8_t button:1; + uint8_t count : 7; + uint8_t button : 1; uint16_t timestamp; } __packed; -- cgit v1.2.1 From ee8bf704ebed953d6f6538dba930f3322211d76f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:36 -0600 Subject: include/peripheral_charger.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8b7673ffc9f1b74ed294fcd1defae87fe79e3a5b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730378 Reviewed-by: Jeremy Bettis --- include/peripheral_charger.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/peripheral_charger.h b/include/peripheral_charger.h index 0479b5e7bd..e06ae96e57 100644 --- a/include/peripheral_charger.h +++ b/include/peripheral_charger.h @@ -87,7 +87,7 @@ */ /* Size of event queue. Use it to initialize struct pchg.events. */ -#define PCHG_EVENT_QUEUE_SIZE 8 +#define PCHG_EVENT_QUEUE_SIZE 8 enum pchg_event { /* No event */ @@ -143,7 +143,7 @@ enum pchg_error { PCHG_ERROR_OTHER, }; -#define PCHG_ERROR_MASK(e) BIT(e) +#define PCHG_ERROR_MASK(e) BIT(e) enum pchg_mode { PCHG_MODE_NORMAL = 0, @@ -189,7 +189,7 @@ struct pchg_update { */ struct pchg { /* Static configuration */ - const struct pchg_config * const cfg; + const struct pchg_config *const cfg; /* Current state of the port */ enum pchg_state state; /* Event queue */ @@ -246,7 +246,7 @@ extern struct pchg pchgs[]; extern const int pchg_count; /* Utility macro converting port config to port number. */ -#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0]) +#define PCHG_CTX_TO_PORT(ctx) ((ctx) - &pchgs[0]) /** * Interrupt handler for a peripheral charger. -- cgit v1.2.1 From 64a11d66fdcea24b5661ee0b6b5d5fbde591e8c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:42 -0600 Subject: board/yorp/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6f469bf0d62aeb81bbff1129d567552b7148d72d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729138 Reviewed-by: Jeremy Bettis --- board/yorp/led.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/board/yorp/led.c b/board/yorp/led.c index 37ce7446b0..b9cfc674ee 100644 --- a/board/yorp/led.c +++ b/board/yorp/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -19,19 +19,28 @@ __override const int led_charge_lvl_2 = 100; /* Yorp: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 9a98c88d097004ff6177af71087703b5c7fb8e99 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:31 -0600 Subject: chip/mec1322/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f1e3853fb7090c211e0818d3ca2e9e522435601 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729335 Reviewed-by: Jeremy Bettis --- chip/mec1322/watchdog.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c index ad93fb1240..16b2d38a2a 100644 --- a/chip/mec1322/watchdog.c +++ b/chip/mec1322/watchdog.c @@ -96,7 +96,8 @@ void IRQ_HANDLER(MEC1322_IRQ_TIMER16_0)(void) "b task_resched_if_needed\n"); } const struct irq_priority __keep IRQ_PRIORITY(MEC1322_IRQ_TIMER16_0) - __attribute__((section(".rodata.irqprio"))) - = {MEC1322_IRQ_TIMER16_0, 0}; /* put the watchdog at the - highest priority */ + __attribute__((section(".rodata.irqprio"))) = { MEC1322_IRQ_TIMER16_0, + 0 }; /* put the watchdog + at the highest + priority */ #endif -- cgit v1.2.1 From 3055f7ac5458662c83c3f2e505b9b87e53f312d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:08 -0600 Subject: board/trogdor/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e5ba1e707ce296a5b934a422df2ce263b813ff4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729047 Reviewed-by: Jeremy Bettis --- board/trogdor/led.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/board/trogdor/led.c b/board/trogdor/led.c index 3af5776e12..07b28e8461 100644 --- a/board/trogdor/led.c +++ b/board/trogdor/led.c @@ -31,15 +31,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void side_led_set_color(int port, enum led_color color) { gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -102,8 +102,9 @@ static void board_led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() <= 10) - side_led_set_color(0, - (battery_ticks & 0x4) ? LED_WHITE : LED_OFF); + side_led_set_color(0, (battery_ticks & 0x4) ? + LED_WHITE : + LED_OFF); else side_led_set_color(0, LED_OFF); } @@ -112,16 +113,16 @@ static void board_led_set_battery(void) side_led_set_color(1, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks & 0x4) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks & 0x4) ? LED_AMBER : LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From f29415e9816e777fb4ec57247aafe51eebf7fcf0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:27 -0600 Subject: test/fpsensor_crypto.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ice9a3acf31d07ee58d5ae2aab872c2956afbc376 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730502 Reviewed-by: Jeremy Bettis --- test/fpsensor_crypto.c | 188 ++++++++++++++++++++++--------------------------- 1 file changed, 85 insertions(+), 103 deletions(-) diff --git a/test/fpsensor_crypto.c b/test/fpsensor_crypto.c index d0fd92cf7c..85dfa97f8c 100644 --- a/test/fpsensor_crypto.c +++ b/test/fpsensor_crypto.c @@ -21,10 +21,9 @@ static const uint8_t fake_positive_match_salt[] = { }; static const uint8_t fake_user_id[] = { - 0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88, - 0xce, 0xc5, 0xd1, 0xfe, 0x1d, 0x58, 0x5b, 0x94, - 0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea, 0xb1, 0xea, - 0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64, + 0x28, 0xb5, 0x5a, 0x55, 0x57, 0x1b, 0x26, 0x88, 0xce, 0xc5, 0xd1, + 0xfe, 0x1d, 0x58, 0x5b, 0x94, 0x51, 0xa2, 0x60, 0x49, 0x9f, 0xea, + 0xb1, 0xea, 0xf7, 0x04, 0x2f, 0x0b, 0x20, 0xa5, 0x93, 0x64, }; /* @@ -83,10 +82,9 @@ static const uint8_t fake_user_id[] = { * go run util/all_tests.go */ static const uint8_t expected_positive_match_secret_for_empty_user_id[] = { - 0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72, - 0xd6, 0xdd, 0xa1, 0x4c, 0xb8, 0xa1, 0x76, 0x2b, - 0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, 0x74, 0x51, - 0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68, + 0x8d, 0xc4, 0x5b, 0xdf, 0x55, 0x1e, 0xa8, 0x72, 0xd6, 0xdd, 0xa1, + 0x4c, 0xb8, 0xa1, 0x76, 0x2b, 0xde, 0x38, 0xd5, 0x03, 0xce, 0xe4, + 0x74, 0x51, 0x63, 0x6c, 0x6a, 0x26, 0xa9, 0xb7, 0xfa, 0x68, }; /* @@ -94,10 +92,9 @@ static const uint8_t expected_positive_match_secret_for_empty_user_id[] = { * |fake_user_id| instead of all-zero user_id. */ static const uint8_t expected_positive_match_secret_for_fake_user_id[] = { - 0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66, - 0x2f, 0x71, 0xf6, 0xc6, 0xca, 0x8a, 0x41, 0x69, - 0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a, 0x5f, 0x4d, - 0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30, + 0x0d, 0xf5, 0xac, 0x7c, 0xad, 0x37, 0x0a, 0x66, 0x2f, 0x71, 0xf6, + 0xc6, 0xca, 0x8a, 0x41, 0x69, 0x8a, 0xd3, 0xcf, 0x0b, 0xc4, 0x5a, + 0x5f, 0x4d, 0x54, 0xeb, 0x7b, 0xad, 0x5d, 0x1b, 0xbe, 0x30, }; static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size, @@ -106,8 +103,8 @@ static int test_hkdf_expand_raw(const uint8_t *prk, size_t prk_size, { uint8_t actual_okm[okm_size]; - TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size, - info, info_size) == EC_SUCCESS); + TEST_ASSERT(hkdf_expand(actual_okm, okm_size, prk, prk_size, info, + info_size) == EC_SUCCESS); TEST_ASSERT_ARRAY_EQ(expected_okm, actual_okm, okm_size); return EC_SUCCESS; } @@ -122,16 +119,14 @@ test_static int test_hkdf_expand(void) 0x22, 0xec, 0x84, 0x4a, 0xd7, 0xc2, 0xb3, 0xe5, }; static const uint8_t info1[] = { - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, }; static const uint8_t expected_okm1[] = { - 0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, - 0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, - 0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, - 0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf, - 0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18, - 0x58, 0x65, + 0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, 0x90, + 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, 0x2d, 0x2d, + 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, 0x5d, 0xb0, 0x2d, + 0x56, 0xec, 0xc4, 0xc5, 0xbf, 0x34, 0x00, 0x72, 0x08, + 0xd5, 0xb8, 0x87, 0x18, 0x58, 0x65, }; static const uint8_t prk2[] = { 0x06, 0xa6, 0xb8, 0x8c, 0x58, 0x53, 0x36, 0x1a, @@ -140,28 +135,24 @@ test_static int test_hkdf_expand(void) 0x4a, 0x19, 0x3f, 0x40, 0xc1, 0x5f, 0xc2, 0x44, }; static const uint8_t info2[] = { - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, - 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, - 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, - 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, - 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, + 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0, 0xc1, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, + 0xce, 0xcf, 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 0xe0, 0xe1, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, + 0xec, 0xed, 0xee, 0xef, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, + 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; static const uint8_t expected_okm2[] = { - 0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1, - 0xc8, 0xe7, 0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34, - 0x4f, 0x01, 0x2e, 0xda, 0x2d, 0x4e, 0xfa, 0xd8, - 0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf, 0xa9, 0x7c, - 0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72, - 0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09, - 0xda, 0x32, 0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8, - 0x36, 0x77, 0x93, 0xa9, 0xac, 0xa3, 0xdb, 0x71, - 0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec, 0x3e, 0x87, - 0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f, + 0xb1, 0x1e, 0x39, 0x8d, 0xc8, 0x03, 0x27, 0xa1, 0xc8, 0xe7, + 0xf7, 0x8c, 0x59, 0x6a, 0x49, 0x34, 0x4f, 0x01, 0x2e, 0xda, + 0x2d, 0x4e, 0xfa, 0xd8, 0xa0, 0x50, 0xcc, 0x4c, 0x19, 0xaf, + 0xa9, 0x7c, 0x59, 0x04, 0x5a, 0x99, 0xca, 0xc7, 0x82, 0x72, + 0x71, 0xcb, 0x41, 0xc6, 0x5e, 0x59, 0x0e, 0x09, 0xda, 0x32, + 0x75, 0x60, 0x0c, 0x2f, 0x09, 0xb8, 0x36, 0x77, 0x93, 0xa9, + 0xac, 0xa3, 0xdb, 0x71, 0xcc, 0x30, 0xc5, 0x81, 0x79, 0xec, + 0x3e, 0x87, 0xc1, 0x4c, 0x01, 0xd5, 0xc1, 0xf3, 0x43, 0x4f, 0x1d, 0x87, }; static const uint8_t prk3[] = { @@ -171,52 +162,48 @@ test_static int test_hkdf_expand(void) 0xac, 0x43, 0x4c, 0x1c, 0x29, 0x3c, 0xcb, 0x04, }; static const uint8_t expected_okm3[] = { - 0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, - 0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, - 0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, - 0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d, - 0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a, - 0x96, 0xc8, + 0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, 0x71, + 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, 0xb8, 0xa1, + 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, 0xc3, 0x45, 0x4e, + 0x5f, 0x3c, 0x73, 0x8d, 0x2d, 0x9d, 0x20, 0x13, 0x95, + 0xfa, 0xa4, 0xb6, 0x1a, 0x96, 0xc8, }; static uint8_t unused_output[SHA256_DIGEST_SIZE] = { 0 }; TEST_ASSERT(test_hkdf_expand_raw(prk1, sizeof(prk1), info1, sizeof(info1), expected_okm1, - sizeof(expected_okm1)) - == EC_SUCCESS); + sizeof(expected_okm1)) == EC_SUCCESS); TEST_ASSERT(test_hkdf_expand_raw(prk2, sizeof(prk2), info2, sizeof(info2), expected_okm2, - sizeof(expected_okm2)) - == EC_SUCCESS); + sizeof(expected_okm2)) == EC_SUCCESS); TEST_ASSERT(test_hkdf_expand_raw(prk3, sizeof(prk3), NULL, 0, - expected_okm3, sizeof(expected_okm3)) - == EC_SUCCESS); - - TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1, - sizeof(prk1), info1, sizeof(info1)) - == EC_ERROR_INVAL); - TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), - NULL, sizeof(prk1), info1, sizeof(info1)) - == EC_ERROR_INVAL); - TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), - prk1, sizeof(prk1), NULL, sizeof(info1)) - == EC_ERROR_INVAL); + expected_okm3, + sizeof(expected_okm3)) == EC_SUCCESS); + + TEST_ASSERT(hkdf_expand(NULL, sizeof(unused_output), prk1, sizeof(prk1), + info1, sizeof(info1)) == EC_ERROR_INVAL); + TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), NULL, + sizeof(prk1), info1, + sizeof(info1)) == EC_ERROR_INVAL); + TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1, + sizeof(prk1), NULL, + sizeof(info1)) == EC_ERROR_INVAL); /* Info size too long. */ - TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), - prk1, sizeof(prk1), info1, 1024) - == EC_ERROR_INVAL); + TEST_ASSERT(hkdf_expand(unused_output, sizeof(unused_output), prk1, + sizeof(prk1), info1, 1024) == EC_ERROR_INVAL); /* OKM size too big. */ - TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE, - prk1, sizeof(prk1), info1, sizeof(info1)) - == EC_ERROR_INVAL); + TEST_ASSERT(hkdf_expand(unused_output, 256 * SHA256_DIGEST_SIZE, prk1, + sizeof(prk1), info1, + sizeof(info1)) == EC_ERROR_INVAL); return EC_SUCCESS; } test_static int test_derive_encryption_key_failure_seed_not_set(void) { static uint8_t unused_key[SBP_ENC_KEY_LEN]; - static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] - = { 0 }; + static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { + 0 + }; /* GIVEN that the TPM seed is not set. */ if (fp_tpm_seed_is_set()) { @@ -314,8 +301,9 @@ test_static int test_derive_encryption_key(void) test_static int test_derive_encryption_key_failure_rollback_fail(void) { static uint8_t unused_key[SBP_ENC_KEY_LEN]; - static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] - = { 0 }; + static const uint8_t unused_salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { + 0 + }; /* GIVEN that reading the rollback secret will fail. */ mock_ctrl_rollback.get_secret_fail = true; @@ -346,11 +334,10 @@ test_static int test_derive_positive_match_secret_fail_seed_not_set(void) /* Deriving positive match secret will fail. */ TEST_ASSERT(derive_positive_match_secret(output, - fake_positive_match_salt) - == EC_ERROR_ACCESS_DENIED); + fake_positive_match_salt) == + EC_ERROR_ACCESS_DENIED); return EC_SUCCESS; - } test_static int test_derive_new_pos_match_secret(void) @@ -367,30 +354,26 @@ test_static int test_derive_new_pos_match_secret(void) * GIVEN that the TPM seed is set, and reading the rollback secret will * succeed. */ - TEST_ASSERT( - fp_tpm_seed_is_set() && !mock_ctrl_rollback.get_secret_fail); + TEST_ASSERT(fp_tpm_seed_is_set() && + !mock_ctrl_rollback.get_secret_fail); /* GIVEN that the salt is not trivial. */ TEST_ASSERT(!bytes_are_trivial(fake_positive_match_salt, sizeof(fake_positive_match_salt))); /* THEN the derivation will succeed. */ - TEST_ASSERT(derive_positive_match_secret(output, - fake_positive_match_salt) - == EC_SUCCESS); + TEST_ASSERT(derive_positive_match_secret( + output, fake_positive_match_salt) == EC_SUCCESS); TEST_ASSERT_ARRAY_EQ( - output, - expected_positive_match_secret_for_empty_user_id, + output, expected_positive_match_secret_for_empty_user_id, sizeof(expected_positive_match_secret_for_empty_user_id)); /* Now change the user_id to be non-trivial. */ memcpy(user_id, fake_user_id, sizeof(fake_user_id)); - TEST_ASSERT(derive_positive_match_secret(output, - fake_positive_match_salt) - == EC_SUCCESS); + TEST_ASSERT(derive_positive_match_secret( + output, fake_positive_match_salt) == EC_SUCCESS); TEST_ASSERT_ARRAY_EQ( - output, - expected_positive_match_secret_for_fake_user_id, + output, expected_positive_match_secret_for_fake_user_id, sizeof(expected_positive_match_secret_for_fake_user_id)); memset(user_id, 0, sizeof(user_id)); @@ -409,8 +392,8 @@ test_static int test_derive_positive_match_secret_fail_rollback_fail(void) /* Deriving positive match secret will fail. */ TEST_ASSERT(derive_positive_match_secret(output, - fake_positive_match_salt) - == EC_ERROR_HW_INTERNAL); + fake_positive_match_salt) == + EC_ERROR_HW_INTERNAL); mock_ctrl_rollback.get_secret_fail = false; return EC_SUCCESS; @@ -424,8 +407,8 @@ test_static int test_derive_positive_match_secret_fail_salt_trivial(void) static const uint8_t salt[FP_CONTEXT_ENCRYPTION_SALT_BYTES] = { 0 }; /* THEN deriving positive match secret will fail. */ - TEST_ASSERT(derive_positive_match_secret(output, salt) - == EC_ERROR_INVAL); + TEST_ASSERT(derive_positive_match_secret(output, salt) == + EC_ERROR_INVAL); return EC_SUCCESS; } @@ -435,8 +418,8 @@ static int test_enable_positive_match_secret_once( const int8_t kIndexToEnable = 0; timestamp_t now = get_time(); - TEST_ASSERT(fp_enable_positive_match_secret( - kIndexToEnable, dumb_state) == EC_SUCCESS); + TEST_ASSERT(fp_enable_positive_match_secret(kIndexToEnable, + dumb_state) == EC_SUCCESS); TEST_ASSERT(dumb_state->template_matched == kIndexToEnable); TEST_ASSERT(dumb_state->readable); TEST_ASSERT(dumb_state->deadline.val == now.val + (5 * SECOND)); @@ -452,12 +435,12 @@ test_static int test_enable_positive_match_secret(void) .deadline.val = 0, }; - TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) - == EC_SUCCESS); + TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) == + EC_SUCCESS); /* Trying to enable again before reading secret should fail. */ TEST_ASSERT(fp_enable_positive_match_secret(0, &dumb_state) == - EC_ERROR_UNKNOWN); + EC_ERROR_UNKNOWN); TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE); TEST_ASSERT(!dumb_state.readable); TEST_ASSERT(dumb_state.deadline.val == 0); @@ -473,8 +456,8 @@ test_static int test_disable_positive_match_secret(void) .deadline.val = 0, }; - TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) - == EC_SUCCESS); + TEST_ASSERT(test_enable_positive_match_secret_once(&dumb_state) == + EC_SUCCESS); fp_disable_positive_match_secret(&dumb_state); TEST_ASSERT(dumb_state.template_matched == FP_NO_SUCH_TEMPLATE); @@ -601,8 +584,7 @@ test_static int test_command_read_match_secret_unreadable(void) positive_match_secret_state.readable = false; /* EVEN IF the finger is just matched. */ - TEST_ASSERT(positive_match_secret_state.template_matched - == params.fgr); + TEST_ASSERT(positive_match_secret_state.template_matched == params.fgr); /* EVEN IF encryption salt is non-trivial. */ memcpy(fp_positive_match_salt[0], fake_positive_match_salt, @@ -625,7 +607,7 @@ void run_test(int argc, char **argv) * cleared. */ ASSERT(fpsensor_state_mock_set_tpm_seed(default_fake_tpm_seed) == - EC_SUCCESS); + EC_SUCCESS); /* The following test requires TPM seed to be already set. */ RUN_TEST(test_derive_encryption_key); -- cgit v1.2.1 From eaa105ddff3e049c6f3c0d9417964981b3d65c62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:15 -0600 Subject: driver/temp_sensor/g78x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I379000081d79239716210388ed2b6ed092d593fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730119 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/g78x.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/driver/temp_sensor/g78x.c b/driver/temp_sensor/g78x.c index c4fd0ff243..84bddfe719 100644 --- a/driver/temp_sensor/g78x.c +++ b/driver/temp_sensor/g78x.c @@ -35,15 +35,14 @@ static int has_power(void) static int raw_read8(const int offset, int *data_ptr) { - return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset, + data_ptr); } #ifdef CONFIG_CMD_TEMP_SENSOR static int raw_write8(const int offset, int data) { - return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, - offset, data); + return i2c_write8(I2C_PORT_THERMAL, G78X_I2C_ADDR_FLAGS, offset, data); } #endif @@ -113,10 +112,8 @@ static void temp_sensor_poll(void) DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR); #ifdef CONFIG_CMD_TEMP_SENSOR -static void print_temps(const char *name, - const int temp_reg, - const int therm_limit_reg, - const int high_limit_reg, +static void print_temps(const char *name, const int temp_reg, + const int therm_limit_reg, const int high_limit_reg, const int low_limit_reg) { int value; @@ -145,19 +142,15 @@ static int print_status(void) return EC_ERROR_NOT_POWERED; } - print_temps("Local", G78X_TEMP_LOCAL, - G78X_LOCAL_TEMP_THERM_LIMIT, - G78X_LOCAL_TEMP_HIGH_LIMIT_R, - G78X_LOCAL_TEMP_LOW_LIMIT_R); + print_temps("Local", G78X_TEMP_LOCAL, G78X_LOCAL_TEMP_THERM_LIMIT, + G78X_LOCAL_TEMP_HIGH_LIMIT_R, G78X_LOCAL_TEMP_LOW_LIMIT_R); - print_temps("Remote1", G78X_TEMP_REMOTE1, - G78X_REMOTE1_TEMP_THERM_LIMIT, + print_temps("Remote1", G78X_TEMP_REMOTE1, G78X_REMOTE1_TEMP_THERM_LIMIT, G78X_REMOTE1_TEMP_HIGH_LIMIT_R, G78X_REMOTE1_TEMP_LOW_LIMIT_R); #ifdef CONFIG_TEMP_SENSOR_G782 - print_temps("Remote2", G78X_TEMP_REMOTE1, - G78X_REMOTE2_TEMP_THERM_LIMIT, + print_temps("Remote2", G78X_TEMP_REMOTE1, G78X_REMOTE2_TEMP_THERM_LIMIT, G78X_REMOTE2_TEMP_HIGH_LIMIT_R, G78X_REMOTE2_TEMP_LOW_LIMIT_R); #endif @@ -207,8 +200,8 @@ static int command_g78x(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", - offset, BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is %pb\n", offset, + BINARY_VALUE(data, 8)); return rv; } @@ -231,7 +224,8 @@ static int command_g78x(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(g78x, command_g78x, +DECLARE_CONSOLE_COMMAND( + g78x, command_g78x, "[settemp|setbyte ] or [getbyte ]. " "Temps in Celsius.", "Print g781/g782 temp sensor status or set parameters."); -- cgit v1.2.1 From aa738ddd0b17a7601c53fa617eec10f3bace708d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:38 -0600 Subject: include/base32.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I806cb48c3a4d6c2a660a456d42d8dad268f3f6b6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730208 Reviewed-by: Jeremy Bettis --- include/base32.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/base32.h b/include/base32.h index ac04ce9c70..efe52a587b 100644 --- a/include/base32.h +++ b/include/base32.h @@ -41,9 +41,8 @@ uint8_t crc5_sym(uint8_t sym, uint8_t previous_crc); * must be a multiple of add_crc_every. * @return EC_SUCCESS, or non-zero error code. */ -int base32_encode(char *dest, int destlen_chars, - const void *srcbits, int srclen_bits, - int add_crc_every); +int base32_encode(char *dest, int destlen_chars, const void *srcbits, + int srclen_bits, int add_crc_every); /** * base32-decode data from a null-terminated string -- cgit v1.2.1 From 510ffd5a9f1150fa38369c7c6b4d3515d89b9172 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:44 -0600 Subject: board/voxel/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icff8cde5d185c413276f1f7d7a748d459a04134a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729084 Reviewed-by: Jeremy Bettis --- board/voxel/board.h | 119 ++++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 64 deletions(-) diff --git a/board/voxel/board.h b/board/voxel/board.h index 7d7109330c..8c8adeabec 100644 --- a/board/voxel/board.h +++ b/board/voxel/board.h @@ -13,7 +13,7 @@ /* Optional features */ #undef NPCX7_PWM1_SEL -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* * The RAM and flash size combination on the the NPCX797FC does not leave @@ -47,8 +47,8 @@ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* BMI160 Base accel/gyro */ #define CONFIG_ACCELGYRO_BMI160 -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ -#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ @@ -60,27 +60,27 @@ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) /* BMA253 Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_ACCEL_BMA255 #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY #ifdef BOARD_VOXEL_ECMODEENTRY @@ -92,16 +92,16 @@ /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41 #define CONFIG_USB_PD_DATA_RESET_MSG /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ #define CONFIG_USB_PD_FRS_PPC /* BC 1.2 */ @@ -114,8 +114,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -123,46 +123,45 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -175,11 +174,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -188,11 +183,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From d473753c1b0a88e1371c1185a17f9552be82a64c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:27 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e8.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I275008147b1f48a44a9a81d23707e4bb7b061e58 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730559 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e8.c | 77 ++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 48 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e8.c b/test/usb_tcpmv2_td_pd_src3_e8.c index b884156d43..92fe80375c 100644 --- a/test/usb_tcpmv2_td_pd_src3_e8.c +++ b/test/usb_tcpmv2_td_pd_src3_e8.c @@ -24,10 +24,10 @@ #define SCEDB_NUM_BYTES 24 #define BSDO_NUM_BYTES 4 -#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1) -#define BSDO_BATTERY_PRESENT(bsdo) (((bsdo) >> 9) & 1) -#define BSDO_BATTERY_CHRG_STS(bsdo) (((bsdo) >> 10) & 3) -#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF) +#define BSDO_INV_BATTERY_REF(bsdo) (((bsdo) >> 8) & 1) +#define BSDO_BATTERY_PRESENT(bsdo) (((bsdo) >> 9) & 1) +#define BSDO_BATTERY_CHRG_STS(bsdo) (((bsdo) >> 10) & 3) +#define BSDO_BATTERY_INFO(bsdo) (((bsdo) >> 8) & 0xFF) static int number_of_fixed_batteries(void) { @@ -88,33 +88,26 @@ int test_td_pd_src3_e8(void) possible[1].ctrl_msg = 0; possible[1].data_msg = PD_DATA_SOURCE_CAP; - TEST_EQ(verify_tcpci_possible_tx(possible, - 2, - &found_index, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data, + sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); if (found_index == 1) { mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); task_wait_event(10 * MSEC); - TEST_EQ(msg_len, HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BYTES, + TEST_EQ(msg_len, + HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + SCEDB_NUM_BYTES, "%d"); num_fixed_batteries = - data[HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BATTERY_OFFSET] & - 0x0F; + data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + + SCEDB_NUM_BATTERY_OFFSET] & + 0x0F; num_swappable_battery_slots = - (data[HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - SCEDB_NUM_BATTERY_OFFSET] >> 4) & - 0x0F; + (data[HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + + SCEDB_NUM_BATTERY_OFFSET] >> + 4) & + 0x0F; } /* * If a Not_Supported message is received, the Tester reads the @@ -141,8 +134,7 @@ int test_td_pd_src3_e8(void) uint16_t header; uint32_t bsdo; - ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | - (ref << 16); + ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | (ref << 16); partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1, &ext_msg); @@ -151,17 +143,13 @@ int test_td_pd_src3_e8(void) * verifies: */ TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, - PD_DATA_BATTERY_STATUS, - data, - sizeof(data), - &msg_len, - 0), + PD_DATA_BATTERY_STATUS, data, + sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); task_wait_event(10 * MSEC); - TEST_EQ(msg_len, HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES + - BSDO_NUM_BYTES, + TEST_EQ(msg_len, + HEADER_BYTE_OFFSET + HEADER_NUM_BYTES + BSDO_NUM_BYTES, "%d"); /* @@ -200,33 +188,26 @@ int test_td_pd_src3_e8(void) * 8. If Invalid Battery Reference field is 1, Battery is * present field shall be 0 */ - bsdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET + - HEADER_NUM_BYTES); + bsdo = UINT32_FROM_BYTE_ARRAY_LE( + data, HEADER_BYTE_OFFSET + HEADER_NUM_BYTES); /* FIXED BATTERY */ if (ref < 4) { if (ref < num_fixed_batteries) { - TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), - 0, "%d"); - TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), - 1, "%d"); + TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d"); + TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 1, "%d"); } else { - TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), - 1, "%d"); - TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), - 0, "%d"); + TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d"); + TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d"); } } /* BATTERY SLOT */ else { if ((ref - 4) < num_swappable_battery_slots) { - TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), - 0, "%d"); + TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 0, "%d"); } else { - TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), - 1, "%d"); - TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), - 0, "%d"); + TEST_EQ(BSDO_INV_BATTERY_REF(bsdo), 1, "%d"); + TEST_EQ(BSDO_BATTERY_PRESENT(bsdo), 0, "%d"); } } -- cgit v1.2.1 From 65bfc1b6949e775092df522ff8fac42ece71052d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:46 -0600 Subject: board/dojo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d71a7a6b5660b6568faa98e084e0dd732746790 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728230 Reviewed-by: Jeremy Bettis --- board/dojo/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/dojo/board.h b/board/dojo/board.h index 15de045652..5c018fccda 100644 --- a/board/dojo/board.h +++ b/board/dojo/board.h @@ -37,14 +37,15 @@ #define CONFIG_CHARGER_PROFILE_OVERRIDE /* PD / USB-C / PPC */ -#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console */ +#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \ + */ /* Optional console commands */ #define CONFIG_CMD_FLASH #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_STACKOVERFLOW -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 /* Keyboard */ #define CONFIG_KEYBOARD_REFRESH_ROW3 -- cgit v1.2.1 From c7c9684c791908c1eb3f5ba5ef2d0eda75a992f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:44 -0600 Subject: chip/it83xx/config_chip_it8320.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8224cdfdfac66fa0dbbed331909ce2fc19271a0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729207 Reviewed-by: Jeremy Bettis --- chip/it83xx/config_chip_it8320.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h index 53f4a1cbd3..5dfcbce1a6 100644 --- a/chip/it83xx/config_chip_it8320.h +++ b/chip/it83xx/config_chip_it8320.h @@ -12,19 +12,19 @@ /* N8 core */ #define CHIP_CORE_NDS32 /* The base address of EC interrupt controller registers. */ -#define CHIP_EC_INTC_BASE 0x00F01100 +#define CHIP_EC_INTC_BASE 0x00F01100 /****************************************************************************/ /* Memory mapping */ -#define CHIP_H2RAM_BASE 0x0008D000 /* 0x0008D000~0x0008DFFF */ -#define CHIP_RAMCODE_BASE 0x0008E000 /* 0x0008E000~0x0008EFFF */ -#define CHIP_EXTRA_STACK_SPACE 0 +#define CHIP_H2RAM_BASE 0x0008D000 /* 0x0008D000~0x0008DFFF */ +#define CHIP_RAMCODE_BASE 0x0008E000 /* 0x0008E000~0x0008EFFF */ +#define CHIP_EXTRA_STACK_SPACE 0 -#define CONFIG_RAM_BASE 0x00080000 -#define CONFIG_RAM_SIZE 0x0000C000 +#define CONFIG_RAM_BASE 0x00080000 +#define CONFIG_RAM_SIZE 0x0000C000 -#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 /****************************************************************************/ /* Chip IT8320 is used with IT83XX TCPM driver */ @@ -36,7 +36,7 @@ * doesn't support a write-protect pin, and if we make the write-protection * permanent, it can't be undone easily enough to support RMA. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* For IT8320BX, we have to reload cc parameters after ec softreset. */ #define IT83XX_USBPD_CC_PARAMETER_RELOAD /* @@ -45,7 +45,7 @@ */ #define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT /* Chip IT8320BX actually has TCPC physical port count */ -#define IT83XX_USBPD_PHY_PORT_COUNT 2 +#define IT83XX_USBPD_PHY_PORT_COUNT 2 /* For IT8320BX, we have to write 0xff to clear pending bit.*/ #define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR /* For IT8320BX, we have to read observation register of external timer two @@ -53,7 +53,7 @@ */ #define IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES #elif defined(CHIP_VARIANT_IT8320DX) -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * Disable eSPI pad, then PLL change @@ -96,9 +96,9 @@ /* Chip Dx transmit status bit of PD register is different from Bx. */ #define IT83XX_PD_TX_ERROR_STATUS_BIT5 /* Chip IT8320DX actually has TCPC physical port count */ -#define IT83XX_USBPD_PHY_PORT_COUNT 2 +#define IT83XX_USBPD_PHY_PORT_COUNT 2 #else #error "Unsupported chip variant!" #endif -#endif /* __CROS_EC_CONFIG_CHIP_IT8320_H */ +#endif /* __CROS_EC_CONFIG_CHIP_IT8320_H */ -- cgit v1.2.1 From 17fe3aba0b99bcbbad460784ecc98dcdc192cd98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:08 -0600 Subject: chip/mt_scp/rv32i_common/uart_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6977fe98cecbb3caa5eb643fa25d8d8ccf24ba5e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729373 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/uart_regs.h | 90 ++++++++++++++++++------------------ 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/chip/mt_scp/rv32i_common/uart_regs.h b/chip/mt_scp/rv32i_common/uart_regs.h index c88b9c758b..44ad192f55 100644 --- a/chip/mt_scp/rv32i_common/uart_regs.h +++ b/chip/mt_scp/rv32i_common/uart_regs.h @@ -16,65 +16,65 @@ void uart_init_pinmux(void); /* DLAB (Divisor Latch Access Bit) == 0 */ /* (Read) receiver buffer register */ -#define UART_RBR(n) UART_REG(n, 0) +#define UART_RBR(n) UART_REG(n, 0) /* (Write) transmitter holding register */ -#define UART_THR(n) UART_REG(n, 0) +#define UART_THR(n) UART_REG(n, 0) /* (Write) interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* received data */ -#define UART_IER_THRI BIT(1) /* THR empty */ -#define UART_IER_RLSI BIT(2) /* receiver LSR change */ -#define UART_IER_MSI BIT(3) /* MSR change */ +#define UART_IER(n) UART_REG(n, 1) +#define UART_IER_RDI BIT(0) /* received data */ +#define UART_IER_THRI BIT(1) /* THR empty */ +#define UART_IER_RLSI BIT(2) /* receiver LSR change */ +#define UART_IER_MSI BIT(3) /* MSR change */ /* (Read) interrupt identification register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_ID_MASK 0x0e -#define UART_IIR_MSI 0x00 /* modem status change */ -#define UART_IIR_NO_INT 0x01 /* no int pending */ -#define UART_IIR_THRI 0x02 /* THR empty */ -#define UART_IIR_RDI 0x04 /* received data available */ -#define UART_IIR_RLSI 0x06 /* line status change */ +#define UART_IIR(n) UART_REG(n, 2) +#define UART_IIR_ID_MASK 0x0e +#define UART_IIR_MSI 0x00 /* modem status change */ +#define UART_IIR_NO_INT 0x01 /* no int pending */ +#define UART_IIR_THRI 0x02 /* THR empty */ +#define UART_IIR_RDI 0x04 /* received data available */ +#define UART_IIR_RLSI 0x06 /* line status change */ /* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */ +#define UART_FCR(n) UART_REG(n, 2) +#define UART_FCR_ENABLE_FIFO BIT(0) /* enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* clear receive FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* clear transmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* select DMA mode */ /* (Write) line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* parity enable */ -#define UART_LCR_EPAR BIT(4) /* even parity */ -#define UART_LCR_SPAR BIT(5) /* stick parity */ -#define UART_LCR_SBC BIT(6) /* set break control */ -#define UART_LCR_DLAB BIT(7) /* divisor latch access */ +#define UART_LCR(n) UART_REG(n, 3) +#define UART_LCR_WLEN5 0 /* word length 5 bits */ +#define UART_LCR_WLEN6 1 +#define UART_LCR_WLEN7 2 +#define UART_LCR_WLEN8 3 +#define UART_LCR_STOP BIT(2) /* stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* parity enable */ +#define UART_LCR_EPAR BIT(4) /* even parity */ +#define UART_LCR_SPAR BIT(5) /* stick parity */ +#define UART_LCR_SBC BIT(6) /* set break control */ +#define UART_LCR_DLAB BIT(7) /* divisor latch access */ /* (Write) modem control register */ -#define UART_MCR(n) UART_REG(n, 4) +#define UART_MCR(n) UART_REG(n, 4) /* (Read) line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* data ready */ -#define UART_LSR_OE BIT(1) /* overrun error */ -#define UART_LSR_PE BIT(2) /* parity error */ -#define UART_LSR_FE BIT(3) /* frame error */ -#define UART_LSR_BI BIT(4) /* break interrupt */ -#define UART_LSR_THRE BIT(5) /* THR empty */ -#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ +#define UART_LSR(n) UART_REG(n, 5) +#define UART_LSR_DR BIT(0) /* data ready */ +#define UART_LSR_OE BIT(1) /* overrun error */ +#define UART_LSR_PE BIT(2) /* parity error */ +#define UART_LSR_FE BIT(3) /* frame error */ +#define UART_LSR_BI BIT(4) /* break interrupt */ +#define UART_LSR_THRE BIT(5) /* THR empty */ +#define UART_LSR_TEMT BIT(6) /* THR empty, line idle */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* (Read) modem status register */ -#define UART_MSR(n) UART_REG(n, 6) +#define UART_MSR(n) UART_REG(n, 6) /* (Read/Write) scratch register */ -#define UART_SCR(n) UART_REG(n, 7) +#define UART_SCR(n) UART_REG(n, 7) /* DLAB == 1 */ /* (Write) divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) -#define UART_DLH(n) UART_REG(n, 1) +#define UART_DLL(n) UART_REG(n, 0) +#define UART_DLH(n) UART_REG(n, 1) /* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) +#define UART_HIGHSPEED(n) UART_REG(n, 9) #endif /* __CROS_EC_UART_REGS_H */ -- cgit v1.2.1 From e97139b3b115146ef6c31ce55a566b9ec595656e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:27 -0600 Subject: board/quiche/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f89590c9ccb889df27666469043577536e70e70 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728872 Reviewed-by: Jeremy Bettis --- board/quiche/board.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/quiche/board.h b/board/quiche/board.h index 98feab31f6..cd109cc8f5 100644 --- a/board/quiche/board.h +++ b/board/quiche/board.h @@ -20,11 +20,10 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ #undef CONFIG_FLASH_PSTATE_LOCKED - /* USB Type C and USB PD defines */ -#define USB_PD_PORT_HOST 0 -#define USB_PD_PORT_DP 1 -#define USB_PD_PORT_USB3 2 +#define USB_PD_PORT_HOST 0 +#define USB_PD_PORT_DP 1 +#define USB_PD_PORT_USB3 2 /* * The host (C0) and display (C1) usbc ports are usb-pd capable. There is @@ -41,9 +40,9 @@ #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 /* I2C port names */ -#define I2C_PORT_I2C1 0 -#define I2C_PORT_I2C2 1 -#define I2C_PORT_I2C3 2 +#define I2C_PORT_I2C1 0 +#define I2C_PORT_I2C2 1 +#define I2C_PORT_I2C3 2 /* Required symbolic I2C port names */ #define I2C_PORT_MP4245 I2C_PORT_I2C3 @@ -71,7 +70,7 @@ #define GPIO_TRIGGER_1 GPIO_EC_STATUS_LED1 #define GPIO_TRIGGER_2 GPIO_EC_STATUS_LED2 -enum debug_gpio { +enum debug_gpio { TRIGGER_1 = 0, TRIGGER_2, }; -- cgit v1.2.1 From 20f7b156d481e5ba89f26e7739fee02435fa9441 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:07 -0600 Subject: board/burnet/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3d4d90e365e544a4f68a4cc6911127f8fb03ef4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728112 Reviewed-by: Jeremy Bettis --- board/burnet/led.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/board/burnet/led.c b/board/burnet/led.c index 06ae68609e..c705ebd42e 100644 --- a/board/burnet/led.c +++ b/board/burnet/led.c @@ -17,10 +17,8 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -28,7 +26,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -111,8 +109,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } @@ -132,10 +129,10 @@ static void led_set_battery(void) */ if (!board_is_convertible()) { if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && - charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + CHIPSET_STATE_STANDBY) && + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } } @@ -164,8 +161,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); -- cgit v1.2.1 From 7153a515b67f7a659b2d5fcade5775b21477e544 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:08 -0600 Subject: zephyr/shim/chip/it8xxx2/power_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4242471820661897e90a5af879db4e894180cc2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730814 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/it8xxx2/power_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/chip/it8xxx2/power_policy.c b/zephyr/shim/chip/it8xxx2/power_policy.c index 7c2e02e258..978f620060 100644 --- a/zephyr/shim/chip/it8xxx2/power_policy.c +++ b/zephyr/shim/chip/it8xxx2/power_policy.c @@ -29,8 +29,8 @@ const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks) * To check if given power state is enabled and * could be used. */ - if (pm_policy_state_lock_is_active( - pm_states[i].state, PM_ALL_SUBSTATES)) { + if (pm_policy_state_lock_is_active(pm_states[i].state, + PM_ALL_SUBSTATES)) { continue; } -- cgit v1.2.1 From bc60d84b694636580046462f71a24e0734085349 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:41 -0600 Subject: board/voxel/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91408b6e0960c1306dd3f759705c390935451aed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729094 Reviewed-by: Jeremy Bettis --- board/voxel/board.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/board/voxel/board.c b/board/voxel/board.c index c57d03b9d3..ab83384eaa 100644 --- a/board/voxel/board.c +++ b/board/voxel/board.c @@ -44,7 +44,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static const struct ec_response_keybd_config zbu_new_kb = { .num_top_row_keys = 10, @@ -80,8 +80,8 @@ static const struct ec_response_keybd_config zbu_old_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_board_id() > 2) return &zbu_new_kb; @@ -111,16 +111,15 @@ __override struct keyboard_scan_config keyscan_config = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); __override uint32_t board_override_feature_flags0(uint32_t flags0) { @@ -146,7 +145,7 @@ union volteer_cbi_fw_config fw_config_defaults = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -183,8 +182,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -314,12 +313,12 @@ static void setup_board_tcpc(void) if (board_id == 0) { /* config typec C0 prot TUSB422 TCPC */ - tcpc_config[USBC_PORT_C0].i2c_info.addr_flags - = TUSB422_I2C_ADDR_FLAGS; + tcpc_config[USBC_PORT_C0].i2c_info.addr_flags = + TUSB422_I2C_ADDR_FLAGS; tcpc_config[USBC_PORT_C0].drv = &tusb422_tcpm_drv; /* config typec C1 prot TUSB422 TCPC */ - tcpc_config[USBC_PORT_C1].i2c_info.addr_flags - = TUSB422_I2C_ADDR_FLAGS; + tcpc_config[USBC_PORT_C1].i2c_info.addr_flags = + TUSB422_I2C_ADDR_FLAGS; tcpc_config[USBC_PORT_C1].drv = &tusb422_tcpm_drv; } } -- cgit v1.2.1 From 50b6ea7ae56f8d8bee7f76e2eb2847e27a26b0e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:22 -0600 Subject: zephyr/shim/src/led_driver/led_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6c84c1886161d9f02a26250b9a732c00bb3fd94 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730912 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/led_driver/led_gpio.c | 46 +++++++++++++++-------------------- 1 file changed, 19 insertions(+), 27 deletions(-) diff --git a/zephyr/shim/src/led_driver/led_gpio.c b/zephyr/shim/src/led_driver/led_gpio.c index 5a4735a162..fa70cab2d4 100644 --- a/zephyr/shim/src/led_driver/led_gpio.c +++ b/zephyr/shim/src/led_driver/led_gpio.c @@ -17,46 +17,38 @@ LOG_MODULE_REGISTER(gpio_led, LOG_LEVEL_ERR); -#define SET_PIN(node_id, prop, i) \ -{ \ - .signal = GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, i)), \ - .val = DT_PHA_BY_IDX(node_id, prop, i, value) \ -}, +#define SET_PIN(node_id, prop, i) \ + { .signal = GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, i)), \ + .val = DT_PHA_BY_IDX(node_id, prop, i, value) }, -#define SET_GPIO_PIN(node_id) \ -{ \ - DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) \ -}; +#define SET_GPIO_PIN(node_id) \ + { DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) }; -#define GEN_PINS_ARRAY(id) \ -struct gpio_pin_t PINS_ARRAY(id)[] = SET_GPIO_PIN(id) +#define GEN_PINS_ARRAY(id) struct gpio_pin_t PINS_ARRAY(id)[] = SET_GPIO_PIN(id) DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, GEN_PINS_ARRAY) -#define SET_PIN_NODE(node_id) \ -{ \ - .led_color = GET_PROP(node_id, led_color), \ - .led_id = GET_PROP(node_id, led_id), \ - .br_color = GET_PROP_NVE(node_id, br_color), \ - .gpio_pins = PINS_ARRAY(node_id), \ - .pins_count = DT_PROP_LEN(node_id, led_pins) \ -}; +#define SET_PIN_NODE(node_id) \ + { .led_color = GET_PROP(node_id, led_color), \ + .led_id = GET_PROP(node_id, led_id), \ + .br_color = GET_PROP_NVE(node_id, br_color), \ + .gpio_pins = PINS_ARRAY(node_id), \ + .pins_count = DT_PROP_LEN(node_id, led_pins) }; /* * Initialize led_pins_node_t struct for each pin node defined */ -#define GEN_PINS_NODES(id) \ -const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id) +#define GEN_PINS_NODES(id) \ + const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id) DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, GEN_PINS_NODES) /* * Array of pointers to each pin node */ -#define PINS_NODE_PTR(id) &PINS_NODE(id), -const struct led_pins_node_t *pins_node[] = { - DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, PINS_NODE_PTR) -}; +#define PINS_NODE_PTR(id) &PINS_NODE(id), +const struct led_pins_node_t *pins_node[] = { DT_FOREACH_CHILD( + GPIO_LED_PINS_NODE, PINS_NODE_PTR) }; /* * Set all the GPIO pins defined in the node to the defined value, @@ -65,8 +57,8 @@ const struct led_pins_node_t *pins_node[] = { void led_set_color_with_node(const struct led_pins_node_t *pins_node) { for (int j = 0; j < pins_node->pins_count; j++) { - gpio_pin_set_dt(gpio_get_dt_spec( - pins_node->gpio_pins[j].signal), + gpio_pin_set_dt( + gpio_get_dt_spec(pins_node->gpio_pins[j].signal), pins_node->gpio_pins[j].val); } } -- cgit v1.2.1 From 634094113c8bc58983278cc46155ecc77ba4b13e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:25 -0600 Subject: board/taeko/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf803e3003d0ed03741ba897a4e76a7e0a4c1f1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728962 Reviewed-by: Jeremy Bettis --- board/taeko/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/taeko/keyboard.c b/board/taeko/keyboard.c index 5ad9a6cdf3..194e90053b 100644 --- a/board/taeko/keyboard.c +++ b/board/taeko/keyboard.c @@ -63,8 +63,8 @@ static const struct ec_response_keybd_config tarlo_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (ec_cfg_has_keyboard_number_pad()) return &tarlo_kb; -- cgit v1.2.1 From 3c466d43805a88c1964aee6dd9861b0f179d11bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:33 -0600 Subject: chip/stm32/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b3c6b90b737b915ef13d6047a9e94196eb7c285 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729512 Reviewed-by: Jeremy Bettis --- chip/stm32/hwtimer.c | 112 ++++++++++++++++++++++++++------------------------- 1 file changed, 57 insertions(+), 55 deletions(-) diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 8748b7f870..46c47f3c1e 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -33,20 +33,20 @@ * -------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_17 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_1 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_15 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_15_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_16 2 #define STM32_TIM_TS_SECONDARY_15_PRIMARY_17 3 #elif defined(CHIP_FAMILY_STM32F3) @@ -61,28 +61,28 @@ * --------------------- * ts = 0 1 2 3 */ -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 -#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 -#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_15 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_5 2 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_14 3 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_19 0 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_4 2 +#define STM32_TIM_TS_SECONDARY_5_PRIMARY_15 3 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_4 0 +#define STM32_TIM_TS_SECONDARY_12_PRIMARY_5 1 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_13 2 #define STM32_TIM_TS_SECONDARY_12_PRIMARY_14 3 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_19_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_15 2 #define STM32_TIM_TS_SECONDARY_19_PRIMARY_16 3 #else /* !CHIP_FAMILY_STM32F0 && !CHIP_FAMILY_STM32F3 */ @@ -97,23 +97,23 @@ * ts = 0 1 2 3 */ #define STM32_TIM_TS_SECONDARY_1_PRIMARY_15 0 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_1_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_9 0 #define STM32_TIM_TS_SECONDARY_2_PRIMARY_10 1 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_2_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_9 0 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_2 1 #define STM32_TIM_TS_SECONDARY_3_PRIMARY_11 2 -#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 +#define STM32_TIM_TS_SECONDARY_3_PRIMARY_4 3 #define STM32_TIM_TS_SECONDARY_4_PRIMARY_10 0 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 -#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 -#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_2 1 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_3 2 +#define STM32_TIM_TS_SECONDARY_4_PRIMARY_9 3 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_2 0 +#define STM32_TIM_TS_SECONDARY_9_PRIMARY_3 1 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_10 2 #define STM32_TIM_TS_SECONDARY_9_PRIMARY_11 3 #endif /* !CHIP_FAMILY_STM32F0 */ @@ -126,7 +126,7 @@ */ #define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB) #define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB) -#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) +#define IRQ_WD IRQ_TIM(TIM_WATCHDOG) /* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */ #if defined TIM_WATCHDOG && (TIM_WATCHDOG == 1) @@ -360,8 +360,8 @@ int __hw_clock_source_init(uint32_t start_t) STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000; STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020; - STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | - (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); + STM32_TIM_SMCR(TIM_CLOCK_MSB) = + 0x0007 | (TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4); STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000; /* Auto-reload value : 16-bit free-running counters */ @@ -419,9 +419,11 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ + __attribute__((section(".rodata.irqprio"))) = { IRQ_WD, + 0 }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { @@ -474,4 +476,4 @@ void hwtimer_reset_watchdog(void) timer->cnt = timer->arr; } -#endif /* defined(CONFIG_WATCHDOG_HELP) */ +#endif /* defined(CONFIG_WATCHDOG_HELP) */ -- cgit v1.2.1 From 20bbcaf2cceaf7ae8a7644571d4c92fabfd16a9b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:38 -0600 Subject: include/sfdp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f913a806a35319521d576966009d7e3d565250f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730402 Reviewed-by: Jeremy Bettis --- include/sfdp.h | 182 +++++++++++++++++++++++++-------------------------------- 1 file changed, 81 insertions(+), 101 deletions(-) diff --git a/include/sfdp.h b/include/sfdp.h index 087708d799..643e4e42a1 100644 --- a/include/sfdp.h +++ b/include/sfdp.h @@ -12,22 +12,20 @@ * Helper macros to declare and access SFDP defined bitfields at a JEDEC SFDP * defined double word (32b) granularity. */ -#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \ - static const uint32_t name = (((1ULL << ((hi) - (lo) + 1)) - 1UL) \ - << (lo)); -#define SFDP_DEFINE_SHIFT_32(name, hi, lo) \ - static const size_t name = (lo); -#define SFDP_DEFINE_BITFIELD(name, hi, lo) \ - SFDP_DEFINE_BITMASK_32(name ## _MASK, hi, lo) \ - SFDP_DEFINE_SHIFT_32(name ## _SHIFT, hi, lo) -#define SFDP_GET_BITFIELD(name, dw) \ - (((dw) & name ## _MASK) >> name ## _SHIFT) +#define SFDP_DEFINE_BITMASK_32(name, hi, lo) \ + static const uint32_t name = \ + (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo)); +#define SFDP_DEFINE_SHIFT_32(name, hi, lo) static const size_t name = (lo); +#define SFDP_DEFINE_BITFIELD(name, hi, lo) \ + SFDP_DEFINE_BITMASK_32(name##_MASK, hi, lo) \ + SFDP_DEFINE_SHIFT_32(name##_SHIFT, hi, lo) +#define SFDP_GET_BITFIELD(name, dw) (((dw)&name##_MASK) >> name##_SHIFT) /** * Helper macros to construct SFDP defined double words (32b). Note reserved or * unused fields must always be set to all 1's. */ -#define SFDP_BITFIELD(name, value) (((value) << name ## _SHIFT) & name ## _MASK) +#define SFDP_BITFIELD(name, value) (((value) << name##_SHIFT) & name##_MASK) #define SFDP_UNUSED(hi, lo) (((1ULL << ((hi) - (lo) + 1)) - 1UL) << (lo)) /******************************************************************************/ @@ -85,10 +83,9 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW1_S, 7, 0); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_NPH, 23, 16); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, 15, 8); SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0); -#define SFDP_HEADER_DWORD_2(nph, major, minor) \ - (SFDP_UNUSED(31, 24) | \ - SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \ - SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \ +#define SFDP_HEADER_DWORD_2(nph, major, minor) \ + (SFDP_UNUSED(31, 24) | SFDP_BITFIELD(SFDP_HEADER_DW2_NPH, nph) | \ + SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MAJOR, major) | \ SFDP_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, minor)) /******************************************************************************/ @@ -98,7 +95,7 @@ SFDP_DEFINE_BITFIELD(SFDP_HEADER_DW2_SFDP_MINOR, 7, 0); /* In SFDP v1.0, the only reserved ID was the Basic Flash Parameter Table ID of * 0x00. Otherwise this field must be set to the vendor's manufacturer ID. Note, * the spec does not call out how to report the manufacturer bank number. */ - #define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00 +#define BASIC_FLASH_PARAMETER_TABLE_1_0_ID 0x00 /* * SFDP v1.0: Parameter Header 1st DWORD @@ -178,8 +175,8 @@ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW1_ID_LSB, 7, 0); */ SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, 31, 24); SFDP_DEFINE_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, 23, 0); -#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp) \ - (SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \ +#define SFDP_1_5_PARAMETER_HEADER_DWORD_2(idmsb, ptp) \ + (SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_ID_MSB, idmsb) | \ SFDP_BITFIELD(SFDP_1_5_PARAMETER_HEADER_DW2_PTP, ptp)) /******************************************************************************/ @@ -226,20 +223,20 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, 4, 4); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WREN_REQ, 3, 3); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, 2, 2); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, 1, 0); -#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, \ - rm4kb, wrenop, wrenrq, wrgr, ergr) \ - (SFDP_UNUSED(31, 23) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) | \ - SFDP_UNUSED(7, 5) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) | \ - SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) | \ +#define BFPT_1_0_DWORD_1(fr114, fr144, fr122, dtr, addr, fr112, rm4kb, wrenop, \ + wrenrq, wrgr, ergr) \ + (SFDP_UNUSED(31, 23) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_1_4_SUPPORTED, fr114) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_4_4_SUPPORTED, fr144) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_2_2_SUPPORTED, fr122) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_DTR_SUPPORTED, dtr) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_ADDR_BYTES, addr) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_1_1_2_SUPPORTED, fr112) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_ERASE_OPCODE, rm4kb) | \ + SFDP_UNUSED(7, 5) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WREN_OPCODE_SELECT, wrenop) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WREN_REQ, wrenrq) | \ + SFDP_BITFIELD(BFPT_1_0_DW1_WRITE_GRANULARITY, wrgr) | \ SFDP_BITFIELD(BFPT_1_0_DW1_4KIB_AVAILABILITY, ergr)) /* Basic Flash Parameter Table v1.0 2nd DWORD @@ -270,13 +267,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, 7, 5); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, 4, 0); -#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, \ - fr144op, fr144mb, fr144dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) | \ - SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) | \ +#define BFPT_1_0_DWORD_3(fr114op, fr114mb, fr114dc, fr144op, fr144mb, fr144dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_OPCODE, fr114op) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_MODE_BITS, fr114mb) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_1_4_WAIT_STATE_CLOCKS, fr114dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_OPCODE, fr144op) | \ + SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_MODE_BITS, fr144mb) | \ SFDP_BITFIELD(BFPT_1_0_DW3_1_4_4_WAIT_STATE_CLOCKS, fr144dc)) /* Basic Flash Parameter Table v1.0 4th DWORD @@ -294,13 +290,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, 15, 8); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, 7, 5); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, 4, 0); -#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, \ - fr112op, fr112mb, fr112dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) | \ - SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) | \ +#define BFPT_1_0_DWORD_4(fr122op, fr122mb, fr122dc, fr112op, fr112mb, fr112dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_OPCODE, fr122op) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_MODE_BITS, fr122mb) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_2_2_WAIT_STATE_CLOCKS, fr122dc) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_OPCODE, fr112op) | \ + SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_MODE_BITS, fr112mb) | \ SFDP_BITFIELD(BFPT_1_0_DW4_1_1_2_WAIT_STATE_CLOCKS, fr112dc)) /* Basic Flash Parameter Table v1.0 5th DWORD @@ -328,9 +323,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW5_2_2_2_SUPPORTED, 0, 0); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, 23, 21); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16); -#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) | \ - SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) | \ +#define BFPT_1_0_DWORD_6(fr222op, fr222mb, fr222dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_OPCODE, fr222op) | \ + SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_MODE_BITS, fr222mb) | \ SFDP_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, fr222dc) | \ SFDP_UNUSED(15, 0)) @@ -344,9 +339,9 @@ SFDP_DEFINE_BITFIELD(BFPT_1_0_DW6_2_2_2_WAIT_STATE_CLOCKS, 20, 16); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, 31, 24); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, 23, 21); SFDP_DEFINE_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, 20, 16); -#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc) \ - (SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) | \ - SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) | \ +#define BFPT_1_0_DWORD_7(fr444op, fr444mb, fr444dc) \ + (SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_OPCODE, fr444op) | \ + SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_MODE_BITS, fr444mb) | \ SFDP_BITFIELD(BFPT_1_0_DW7_4_4_4_WAIT_STATE_CLOCKS, fr444dc) | \ SFDP_UNUSED(15, 0)) @@ -419,17 +414,16 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, 15, 11); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, 10, 9); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, 8, 4); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, 3, 0); -#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, \ - rm3count, rm2unit, rm2count, \ - rm1unit, rm1count, maxmult) \ - (SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) | \ - SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) | \ +#define BFPT_1_5_DWORD_10(rm4unit, rm4count, rm3unit, rm3count, rm2unit, \ + rm2count, rm1unit, rm1count, maxmult) \ + (SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_UNIT, rm4unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_4_TIME_CNT, rm4count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_UNIT, rm3unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_3_TIME_CNT, rm3count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_UNIT, rm2unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_2_TIME_CNT, rm2count) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_UNIT, rm1unit) | \ + SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_1_TIME_CNT, rm1count) | \ SFDP_BITFIELD(BFPT_1_5_DW10_ERASE_TIME_MAX_MULT, maxmult)) /* Basic Flash Parameter Table v1.5 11th DWORD @@ -464,18 +458,12 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW11_WR_TIME_MAX_MULT, 3, 0); #define BFPT_1_5_DWORD_11(crmunit, crmcount, mrbunit, mrbcount, initunit, \ initcount, pgwrunit, pgwrcount, pagesz, maxmult) \ (SFDP_UNUSED(31, 31) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, \ - crmunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, \ - crmcount) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, \ - mrbunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, \ - mrbcount) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, \ - initunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, \ - initcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_UNIT, crmunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_CHIP_ERASE_TIME_CNT, crmcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_UNIT, mrbunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_MORE_BYTE_WR_TIME_CNT, mrbcount) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_UNIT, initunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW11_INIT_BYTE_WR_TIME_CNT, initcount) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_UNIT, pgwrunit) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_WR_TIME_CNT, pgwrcount) | \ SFDP_BITFIELD(BFPT_1_5_DW11_PAGE_SIZE, pagesz) | \ @@ -532,26 +520,21 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, 17, 13); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, 12, 9); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, 7, 4); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, 3, 0); -#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \ - suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt, \ - prohibopsrmsusp, prohibopswrsusp) \ - (SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, \ - susprmlatun) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, \ - susprmlatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT, \ - rmressusplatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, \ - suspwrmaxlatunit) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, \ - suspwrmaxlatcnt) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, \ - wrressuspcnt) | \ - SFDP_UNUSED(8, 8) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, \ - prohibopsrmsusp) | \ - SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, \ +#define BFPT_1_5_DWORD_12(unsup, susprmlatun, susprmlatcnt, rmressusplatcnt, \ + suspwrmaxlatunit, suspwrmaxlatcnt, wrressuspcnt, \ + prohibopsrmsusp, prohibopswrsusp) \ + (SFDP_BITFIELD(BFPT_1_5_DW12_SUSPEND_UNSUPPORTED, unsup) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_UNIT, susprmlatun) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_RM_MAX_LAT_CNT, susprmlatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_RM_RES_TO_SUSP_LAT_CNT, \ + rmressusplatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_UNIT, suspwrmaxlatunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_SUSP_WR_MAX_LAT_CNT, suspwrmaxlatcnt) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_WR_RES_TO_SUSP_LAT_CNT, wrressuspcnt) | \ + SFDP_UNUSED(8, 8) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_RM_SUSP, \ + prohibopsrmsusp) | \ + SFDP_BITFIELD(BFPT_1_5_DW12_PROHIB_OPS_DURING_WR_SUSP, \ prohibopswrsusp)) /* Basic Flash Parameter Table v1.5 13th DWORD @@ -600,12 +583,10 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, 12, 8); SFDP_DEFINE_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, 7, 2); #define BFPT_1_5_DWORD_14(pwrdwnunsup, pwrdwnop, pwrupop, pwrupunit, pwrupcnt, \ busypollflags) \ - (SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, \ - pwrdwnunsup) | \ + (SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_UNSUPPORTED, pwrdwnunsup) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_DOWN_OPCODE, pwrdwnop) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_OPCODE, pwrupop) | \ - SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, \ - pwrupunit) | \ + SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_UNIT, pwrupunit) | \ SFDP_BITFIELD(BFPT_1_5_DW14_POWER_UP_TIME_CNT, pwrupcnt) | \ SFDP_BITFIELD(BFPT_1_5_DW14_BUSY_FLAGS, busypollflags) | \ SFDP_UNUSED(1, 0)) @@ -702,7 +683,6 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, 3, 0); SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_ENTRY, fr444entry) | \ SFDP_BITFIELD(BFPT_1_5_DW15_4_4_4_EXIT, fr444exit)) - /* Basic Flash Parameter Table v1.5 16th DWORD * ------------------------------------------- * <31:24> : Enter 4-Byte Addressing, where @@ -804,4 +784,4 @@ SFDP_DEFINE_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, 6, 0); SFDP_UNUSED(7, 7) | \ SFDP_BITFIELD(BFPT_1_5_DW16_STATUS_REG_1, statusreg1)) -#endif /* __CROS_EC_SFDP_H */ +#endif /* __CROS_EC_SFDP_H */ -- cgit v1.2.1 From fad95a80cdc17026f8d2466274ad83b0ecc9e99c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:12 -0600 Subject: board/beadrix/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9afaf348615edd7b928a2b69644a4a3cd00c954d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728006 Reviewed-by: Jeremy Bettis --- board/beadrix/board.h | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/board/beadrix/board.h b/board/beadrix/board.h index 6e7975fd14..215bc6fff1 100644 --- a/board/beadrix/board.h +++ b/board/beadrix/board.h @@ -30,9 +30,10 @@ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGE_RAMP_HW -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ /* * GPIO for C1 interrupts, for baseboard use @@ -45,7 +46,7 @@ #define CONFIG_PWM /* TCPC */ -#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: MUX only*/ +#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: MUX only*/ #define CONFIG_USB_PD_TCPM_MUX #define CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD @@ -57,7 +58,7 @@ /* USB */ #define CONFIG_BC12_DETECT_PI3USB9201 #define CONFIG_USB_MUX_RUNTIME_CONFIG -#define CONFIG_USB_MUX_IT5205 /* C0: ITE MUX */ +#define CONFIG_USB_MUX_IT5205 /* C0: ITE MUX */ /* USB PD */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 @@ -67,7 +68,7 @@ /* USB Mux and Retimer */ #define CONFIG_USB_MUX_RUNTIME_CONFIG -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ #define CONFIG_USBC_RETIMER_NB7V904M /* USB defines specific to external TCPCs */ @@ -82,8 +83,8 @@ #undef PD_POWER_SUPPLY_TURN_ON_DELAY #undef PD_POWER_SUPPLY_TURN_OFF_DELAY /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #ifndef __ASSEMBLER__ @@ -103,18 +104,14 @@ enum pwm_channel { /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From aec9f669d6098aa713fb1b491d4ce57ca02d6f99 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:33 -0600 Subject: include/peci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1503c64c6f339635f67045016f758cf7d4a3f792 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730377 Reviewed-by: Jeremy Bettis --- include/peci.h | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/include/peci.h b/include/peci.h index 993e7d637d..dccf32100a 100644 --- a/include/peci.h +++ b/include/peci.h @@ -10,37 +10,37 @@ #include "common.h" -#define PECI_TARGET_ADDRESS 0x30 -#define PECI_WRITE_DATA_FIFO_SIZE 15 -#define PECI_READ_DATA_FIFO_SIZE 16 +#define PECI_TARGET_ADDRESS 0x30 +#define PECI_WRITE_DATA_FIFO_SIZE 15 +#define PECI_READ_DATA_FIFO_SIZE 16 -#define PECI_GET_TEMP_READ_LENGTH 2 -#define PECI_GET_TEMP_WRITE_LENGTH 0 -#define PECI_GET_TEMP_TIMEOUT_US 200 +#define PECI_GET_TEMP_READ_LENGTH 2 +#define PECI_GET_TEMP_WRITE_LENGTH 0 +#define PECI_GET_TEMP_TIMEOUT_US 200 /* PECI Command Code */ enum peci_command_code { - PECI_CMD_PING = 0x00, - PECI_CMD_GET_DIB = 0xF7, - PECI_CMD_GET_TEMP = 0x01, - PECI_CMD_RD_PKG_CFG = 0xA1, - PECI_CMD_WR_PKG_CFG = 0xA5, - PECI_CMD_RD_IAMSR = 0xB1, - PECI_CMD_WR_IAMSR = 0xB5, - PECI_CMD_RD_PCI_CFG = 0x61, - PECI_CMD_WR_PCI_CFG = 0x65, + PECI_CMD_PING = 0x00, + PECI_CMD_GET_DIB = 0xF7, + PECI_CMD_GET_TEMP = 0x01, + PECI_CMD_RD_PKG_CFG = 0xA1, + PECI_CMD_WR_PKG_CFG = 0xA5, + PECI_CMD_RD_IAMSR = 0xB1, + PECI_CMD_WR_IAMSR = 0xB5, + PECI_CMD_RD_PCI_CFG = 0x61, + PECI_CMD_WR_PCI_CFG = 0x65, PECI_CMD_RD_PCI_CFG_LOCAL = 0xE1, PECI_CMD_WR_PCI_CFG_LOCAL = 0xE5, }; struct peci_data { enum peci_command_code cmd_code; /* command code */ - uint8_t addr; /* client address */ - uint8_t w_len; /* write length */ - uint8_t r_len; /* read length */ - uint8_t *w_buf; /* buffer pointer of write data */ - uint8_t *r_buf; /* buffer pointer of read data */ - int timeout_us; /* transaction timeout unit:us */ + uint8_t addr; /* client address */ + uint8_t w_len; /* write length */ + uint8_t r_len; /* read length */ + uint8_t *w_buf; /* buffer pointer of write data */ + uint8_t *r_buf; /* buffer pointer of read data */ + int timeout_us; /* transaction timeout unit:us */ }; /** @@ -62,4 +62,4 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr); */ int peci_transaction(struct peci_data *peci); -#endif /* __CROS_EC_PECI_H */ +#endif /* __CROS_EC_PECI_H */ -- cgit v1.2.1 From 5a4758946742e44c707a60e1e05e2aa8ea037f2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:56 -0600 Subject: board/galtic/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2a7b81ffd9fb0ecf0331c726eb540f3af117cf0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728388 Reviewed-by: Jeremy Bettis --- board/galtic/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/galtic/usb_pd_policy.c b/board/galtic/usb_pd_policy.c index 3190595596..9edc5a181d 100644 --- a/board/galtic/usb_pd_policy.c +++ b/board/galtic/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From db0b1d0cac3cd3da888a172c33a3becfbfcac691 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:37 -0600 Subject: board/liara/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8026aba90c03728ebf17d1f9a44ea12926e3ff7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728633 Reviewed-by: Jeremy Bettis --- board/liara/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/liara/board.h b/board/liara/board.h index ae4494115b..dbd31d8483 100644 --- a/board/liara/board.h +++ b/board/liara/board.h @@ -17,13 +17,13 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF #define CONFIG_MKBP_USE_HOST_EVENT -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 /* Power and battery LEDs */ #define CONFIG_LED_COMMON -- cgit v1.2.1 From 61897d41f2fe47d7b4d8dfb6ec95692b56ce2a0f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:41 -0600 Subject: board/copano/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c4567387e5a339b95c25eb8126b021e758e75ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728156 Reviewed-by: Jeremy Bettis --- board/copano/sensors.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/copano/sensors.c b/board/copano/sensors.c index 8aa9f5888b..8b0da8b67a 100644 --- a/board/copano/sensors.c +++ b/board/copano/sensors.c @@ -36,22 +36,18 @@ static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; const mat33_fp_t base_standard_ref_icm = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)}, + { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; struct motion_sensor_t icm426xx_base_accel = { -- cgit v1.2.1 From b7acc5348fc8ca257d64f05bdac716e43be27944 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:38 -0600 Subject: zephyr/shim/include/usbc/tcpc_fusb302.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia32ce5247fb76073b97a8cccfa2d972d7aee8480 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730838 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_fusb302.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h index fefb54af7d..74532767d0 100644 --- a/zephyr/shim/include/usbc/tcpc_fusb302.h +++ b/zephyr/shim/include/usbc/tcpc_fusb302.h @@ -8,7 +8,7 @@ #define FUSB302_TCPC_COMPAT fairchild_fusb302 -#define TCPC_CONFIG_FUSB302(id) \ +#define TCPC_CONFIG_FUSB302(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ -- cgit v1.2.1 From 16acbcd202364f1a0e840da732b3d9bfb6caf5ac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:17 -0600 Subject: board/moonbuggy/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide017b1dad6d1dfb84931c2105f72112b882ddb6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728696 Reviewed-by: Jeremy Bettis --- board/moonbuggy/board.c | 136 +++++++++++++++++++++--------------------------- 1 file changed, 60 insertions(+), 76 deletions(-) diff --git a/board/moonbuggy/board.c b/board/moonbuggy/board.c index b5f51efc32..6ee831abd5 100644 --- a/board/moonbuggy/board.c +++ b/board/moonbuggy/board.c @@ -36,8 +36,8 @@ #include "usb_common.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -49,14 +49,14 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1500) -#define PWR_FRONT_LOW (5*900) -#define PWR_REAR (5*1500) -#define PWR_HDMI (5*562) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1500) +#define PWR_FRONT_LOW (5 * 900) +#define PWR_REAR (5 * 1500) +#define PWR_HDMI (5 * 562) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -147,64 +147,52 @@ void ads_12v_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_WHITE] = { .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_WHITE] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "pse", - .port = I2C_PORT_PSE, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "pse", + .port = I2C_PORT_PSE, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -260,15 +248,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -287,7 +274,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -296,8 +283,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ @@ -386,14 +373,12 @@ static void board_init(void) /* ADS GPIO interrupt enable*/ gpio_enable_interrupt(GPIO_ADS_5VS_V2_ADP_PRESENT_L); gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_L); - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /******************************************************************************/ /* USB-A port control */ -const int usb_port_enable[USB_PORT_COUNT] = { -}; +const int usb_port_enable[USB_PORT_COUNT] = {}; int64_t get_time_dsw_pwrok(void) { @@ -454,23 +439,23 @@ void board_enable_s0_rails(int enable) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -483,8 +468,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ -- cgit v1.2.1 From 7fe50bf514da729f32acf21c5b6c30682f3092d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:14 -0600 Subject: board/lantis/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia706ad3587449c8f809af362b852ce4e923c472a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728615 Reviewed-by: Jeremy Bettis --- board/lantis/cbi_ssfc.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/lantis/cbi_ssfc.h b/board/lantis/cbi_ssfc.h index 448fa5a163..b2cd930d8b 100644 --- a/board/lantis/cbi_ssfc.h +++ b/board/lantis/cbi_ssfc.h @@ -36,18 +36,18 @@ enum ec_ssfc_lid_sensor { * Audio Codec Source(Bit 8-10) */ enum ec_ssfc_audio_codec_source { - SSFC_AUDIO_CODEC_DEFAULT = 0, - SSFC_AUDIO_CODEC_VD = 1, - SSFC_ADUIO_CODEC_VS = 2, + SSFC_AUDIO_CODEC_DEFAULT = 0, + SSFC_AUDIO_CODEC_VD = 1, + SSFC_ADUIO_CODEC_VS = 2, }; /* * Touchscreen Driver Source(Bit 11-13) */ enum ec_ssfc_ts_driver_source { - SSFC_TS_DRIVER_DEFAULT = 0, - SSFC_TS_DRIVER_GENERIC = 1, - SSFC_TS_DRIVER_HID = 2, + SSFC_TS_DRIVER_DEFAULT = 0, + SSFC_TS_DRIVER_GENERIC = 1, + SSFC_TS_DRIVER_HID = 2, }; union dedede_cbi_ssfc { @@ -56,7 +56,7 @@ union dedede_cbi_ssfc { uint32_t lid_sensor : 3; uint32_t reserved : 2; uint32_t audio_codec_source : 3; - uint32_t ts_driver_source: 3; + uint32_t ts_driver_source : 3; uint32_t reserved_2 : 18; }; uint32_t raw_value; @@ -76,5 +76,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From cb2d2cf3a6b2c47fc8b63e951d1efa5fcac7d079 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:41 -0600 Subject: board/mithrax/keyboard_customization.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94ebaa310442b74d8940728596db0eeefe61fa97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728463 Reviewed-by: Jeremy Bettis --- board/mithrax/keyboard_customization.h | 74 +++++++++++++++++----------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/board/mithrax/keyboard_customization.h b/board/mithrax/keyboard_customization.h index b177a11eb4..e319330365 100644 --- a/board/mithrax/keyboard_customization.h +++ b/board/mithrax/keyboard_customization.h @@ -25,47 +25,47 @@ extern uint8_t keyboard_cols; #define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) /* Columns and masks for keys we particularly care about */ -#define KEYBOARD_COL_DOWN 11 -#define KEYBOARD_ROW_DOWN 5 -#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) -#define KEYBOARD_COL_ESC 1 -#define KEYBOARD_ROW_ESC 1 -#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) -#define KEYBOARD_COL_KEY_H 6 -#define KEYBOARD_ROW_KEY_H 1 -#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) -#define KEYBOARD_COL_KEY_R 3 -#define KEYBOARD_ROW_KEY_R 7 -#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) -#define KEYBOARD_COL_LEFT_ALT 10 -#define KEYBOARD_ROW_LEFT_ALT 6 -#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) -#define KEYBOARD_COL_REFRESH 2 -#define KEYBOARD_ROW_REFRESH 3 -#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) -#define KEYBOARD_COL_RIGHT_ALT 10 -#define KEYBOARD_ROW_RIGHT_ALT 0 -#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) -#define KEYBOARD_DEFAULT_COL_VOL_UP 4 -#define KEYBOARD_DEFAULT_ROW_VOL_UP 1 -#define KEYBOARD_COL_LEFT_CTRL 0 -#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 5 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 +#define KEYBOARD_ROW_REFRESH 3 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 1 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) #define KEYBOARD_COL_RIGHT_CTRL 0 #define KEYBOARD_ROW_RIGHT_CTRL 4 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) -#define KEYBOARD_COL_SEARCH 0 -#define KEYBOARD_ROW_SEARCH 3 -#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) -#define KEYBOARD_COL_KEY_0 9 -#define KEYBOARD_ROW_KEY_0 0 -#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) -#define KEYBOARD_COL_KEY_1 1 -#define KEYBOARD_ROW_KEY_1 7 -#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) -#define KEYBOARD_COL_KEY_2 4 -#define KEYBOARD_ROW_KEY_2 6 -#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_SEARCH 0 +#define KEYBOARD_ROW_SEARCH 3 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 9 +#define KEYBOARD_ROW_KEY_0 0 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 7 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) #define KEYBOARD_COL_LEFT_SHIFT 7 #define KEYBOARD_ROW_LEFT_SHIFT 1 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) -- cgit v1.2.1 From 57b8c526f4805905f6e0cf261eaaac0df049a2aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:26 -0600 Subject: board/corori2/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1eb412e07b54cfe9dd009fb3d2c1641c98829e1c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728163 Reviewed-by: Jeremy Bettis --- board/corori2/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/corori2/cbi_ssfc.c b/board/corori2/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/corori2/cbi_ssfc.c +++ b/board/corori2/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From e21df13e80e88cc62b01c8f709644ed0130645a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:10 -0600 Subject: chip/stm32/usb_dfu_runtime.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief63bbc0cd87ac197db6528ccc5573e9c39929dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729569 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dfu_runtime.h | 55 ++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/chip/stm32/usb_dfu_runtime.h b/chip/stm32/usb_dfu_runtime.h index 08781d77b0..9185dc9bbc 100644 --- a/chip/stm32/usb_dfu_runtime.h +++ b/chip/stm32/usb_dfu_runtime.h @@ -12,47 +12,46 @@ * https://www.usb.org/sites/default/files/DFU_1.1.pdf */ -#define USB_DFU_RUNTIME_SUBCLASS 0x01 -#define USB_DFU_RUNTIME_PROTOCOL 0x01 +#define USB_DFU_RUNTIME_SUBCLASS 0x01 +#define USB_DFU_RUNTIME_PROTOCOL 0x01 -#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0) -#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1) -#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2) -#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3) +#define USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD BIT(0) +#define USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD BIT(1) +#define USB_DFU_RUNTIME_DESC_ATTR_MANIFEST_TOLERANT BIT(2) +#define USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH BIT(3) -#define USB_DFU_RUNTIME_DESC_ATTRS \ +#define USB_DFU_RUNTIME_DESC_ATTRS \ (USB_DFU_RUNTIME_DESC_ATTR_CAN_DOWNLOAD | \ - USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD | \ - USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH) + USB_DFU_RUNTIME_DESC_ATTR_CAN_UPLOAD | \ + USB_DFU_RUNTIME_DESC_ATTR_WILL_DETACH) -#define USB_DFU_RUNTIME_DESC_SIZE 9 -#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21 -#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff -#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64 -#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022 +#define USB_DFU_RUNTIME_DESC_SIZE 9 +#define USB_DFU_RUNTIME_DESC_FUNCTIONAL 0x21 +#define USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT 0xffff +#define USB_DFU_RUNTIME_DESC_TRANSFER_SIZE 64 +#define USB_DFU_RUNTIME_DESC_DFU_VERSION 0x0022 /* DFU states */ -#define USB_DFU_RUNTIME_STATE_APP_IDLE 0 -#define USB_DFU_RUNTIME_STATE_APP_DETACH 1 +#define USB_DFU_RUNTIME_STATE_APP_IDLE 0 +#define USB_DFU_RUNTIME_STATE_APP_DETACH 1 /* DFU status */ -#define USB_DFU_RUNTIME_STATUS_OK 0 +#define USB_DFU_RUNTIME_STATUS_OK 0 /* DFU Request types */ -#define USB_DFU_RUNTIME_REQ_DETACH 0 -#define USB_DFU_RUNTIME_REQ_DNLOAD 1 -#define USB_DFU_RUNTIME_REQ_UPLOAD 2 -#define USB_DFU_RUNTIME_REQ_GET_STATUS 3 -#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4 -#define USB_DFU_RUNTIME_REQ_GET_STATE 5 -#define USB_DFU_RUNTIME_REQ_ABORT 6 - +#define USB_DFU_RUNTIME_REQ_DETACH 0 +#define USB_DFU_RUNTIME_REQ_DNLOAD 1 +#define USB_DFU_RUNTIME_REQ_UPLOAD 2 +#define USB_DFU_RUNTIME_REQ_GET_STATUS 3 +#define USB_DFU_RUNTIME_REQ_CLR_STATUS 4 +#define USB_DFU_RUNTIME_REQ_GET_STATE 5 +#define USB_DFU_RUNTIME_REQ_ABORT 6 /* DFU Functional Descriptor */ struct usb_runtime_dfu_functional_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bmAttributes; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; uint16_t wDetachTimeOut; uint16_t wTransferSize; uint16_t bcdDFUVersion; -- cgit v1.2.1 From f6bfcf833d9708e2bc2d703f53ab22ad877aaa6f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:00 -0600 Subject: zephyr/projects/trogdor/lazor/src/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7080545cc4d51e91d86538031cff7b6c8c8177d2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730811 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/usbc_config.c | 32 +++++++++++-------------- 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/zephyr/projects/trogdor/lazor/src/usbc_config.c b/zephyr/projects/trogdor/lazor/src/usbc_config.c index 59dbeb6fc6..fdcd6678b0 100644 --- a/zephyr/projects/trogdor/lazor/src/usbc_config.c +++ b/zephyr/projects/trogdor/lazor/src/usbc_config.c @@ -27,8 +27,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int charger_profile_override(struct charge_state_data *curr) { @@ -71,9 +71,9 @@ enum ec_status charger_profile_override_set_param(uint32_t param, static void usba_oc_deferred(void) { /* Use next number after all USB-C ports to indicate the USB-A port */ - board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT, - !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_usb_a0_oc_odl))); + board_overcurrent_event( + CONFIG_USB_PD_PORT_MAX_COUNT, + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl))); } DECLARE_DEFERRED(usba_oc_deferred); @@ -199,7 +199,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); @@ -244,8 +244,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -273,7 +272,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -297,23 +295,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) @@ -322,11 +318,11 @@ uint16_t tcpc_get_alert_status(void) if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) status |= PD_STATUS_TCPC_ALERT_0; if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) status |= PD_STATUS_TCPC_ALERT_1; return status; -- cgit v1.2.1 From 9c7bbc240fb4c175320191c452c8d40f2e77f01b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:10 -0600 Subject: chip/stm32/gpio-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If70fe4379a3035cc2e6cf2b2266e481ba1055716 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729504 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-stm32f4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/stm32/gpio-stm32f4.c b/chip/stm32/gpio-stm32f4.c index 1ccdadd472..9726bd277f 100644 --- a/chip/stm32/gpio-stm32f4.c +++ b/chip/stm32/gpio-stm32f4.c @@ -17,12 +17,12 @@ int gpio_required_clocks(void) { const int gpio_ports_used = (0 -# define GPIO(name, pin, flags) pin -# define GPIO_INT(name, pin, flags, signal) pin -# define ALTERNATE(pinmask, function, module, flagz) pinmask -# define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT ## port -# define PIN_MASK(port, mask) PIN(port, 0) -# include "gpio.wrap" +#define GPIO(name, pin, flags) pin +#define GPIO_INT(name, pin, flags, signal) pin +#define ALTERNATE(pinmask, function, module, flagz) pinmask +#define PIN(port, index) | STM32_RCC_AHB1ENR_GPIO_PORT##port +#define PIN_MASK(port, mask) PIN(port, 0) +#include "gpio.wrap" ); /* -- cgit v1.2.1 From eea31aea599c02259bcd28a2e5f1017b05d2eec7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:18 -0600 Subject: board/katsu/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8ebca997686422af16bab3501bb8d6177272ee2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728529 Reviewed-by: Jeremy Bettis --- board/katsu/board.c | 75 ++++++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 44 deletions(-) diff --git a/board/katsu/board.c b/board/katsu/board.c index a91f2c4afa..e68d3b2fa0 100644 --- a/board/katsu/board.c +++ b/board/katsu/board.c @@ -42,8 +42,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -60,45 +60,40 @@ static void gauge_interrupt(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, - [ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, + [ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0, + STM32_AIN(6) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ @@ -118,8 +113,7 @@ struct mt6370_thermal_bound thermal_bound = { .err = 4, }; -static void board_hpd_update(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -244,9 +238,8 @@ int extpower_is_present(void) if (board_vbus_source_enabled(CHARGE_PORT_USB_C)) usb_c_extpower_present = 0; else - usb_c_extpower_present = tcpm_check_vbus_level( - CHARGE_PORT_USB_C, - VBUS_PRESENT); + usb_c_extpower_present = + tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT); if (prev_usb_c_extpower_present != usb_c_extpower_present) { if (usb_c_extpower_present) @@ -332,11 +325,9 @@ static struct mutex g_lid_mutex; static struct icm_drv_data_t g_icm426xx_data; /* Matrix to rotate accelerometer into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -436,9 +427,8 @@ __override int board_charge_port_is_connected(int port) return gpio_get_level(GPIO_POGO_VBUS_PRESENT); } -__override -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r) +__override void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r) { r->meas.voltage_now = 3300; r->meas.voltage_max = 3300; @@ -451,13 +441,10 @@ void board_fill_source_power_info(int port, static void mt6370_reg_fix(void) { i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT946X_REG_CHGCTRL1, + chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1, BIT(3) | BIT(5), MASK_CLR); i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT946X_REG_CHGCTRL2, - BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), - MASK_CLR); + chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2, + BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR); } DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From ba318393162d2d629d87c1ca5c2e7eae52d3cf6c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:04 -0600 Subject: include/mock_filter.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief028260b4daad1a3672389dff782dfa1d3bc1b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730366 Reviewed-by: Jeremy Bettis --- include/mock_filter.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/mock_filter.h b/include/mock_filter.h index 113c227a3b..c86f7fd61d 100644 --- a/include/mock_filter.h +++ b/include/mock_filter.h @@ -18,5 +18,4 @@ CONFIG_TEST_MOCK_LIST #endif - #endif /* __CROS_EC_MOCK_FILTER_H */ -- cgit v1.2.1 From 5334b0aff3bc7a63d6275240ffe1798e40dcb41b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:28 -0600 Subject: common/i2c_bitbang.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73bd99ffa5835401b3fb62780e96b832f204bd79 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729655 Reviewed-by: Jeremy Bettis --- common/i2c_bitbang.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/common/i2c_bitbang.c b/common/i2c_bitbang.c index 99868b2dc6..ab1dcfd968 100644 --- a/common/i2c_bitbang.c +++ b/common/i2c_bitbang.c @@ -11,7 +11,7 @@ #include "util.h" #define CPUTS(str) cputs(CC_I2C, str) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) static int started; @@ -22,8 +22,8 @@ static void i2c_delay(void) } /* Number of attempts to unwedge each pin. */ -#define UNWEDGE_SCL_ATTEMPTS 10 -#define UNWEDGE_SDA_ATTEMPTS 3 +#define UNWEDGE_SCL_ATTEMPTS 10 +#define UNWEDGE_SDA_ATTEMPTS 3 static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port) { @@ -84,7 +84,7 @@ static void i2c_bitbang_unwedge(const struct i2c_port_t *i2c_port) /* Check if the bus is unwedged. */ if (gpio_get_level(i2c_port->sda) && - gpio_get_level(i2c_port->scl)) + gpio_get_level(i2c_port->scl)) break; } @@ -263,7 +263,7 @@ static int i2c_write_byte(const struct i2c_port_t *i2c_port, uint8_t byte) } static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte, - int nack) + int nack) { int i; @@ -281,9 +281,8 @@ static int i2c_read_byte(const struct i2c_port_t *i2c_port, uint8_t *byte, } static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) + const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { uint16_t addr_8bit = addr_flags << 1, err = EC_SUCCESS; int i = 0; @@ -320,7 +319,8 @@ static int i2c_bitbang_xfer(const struct i2c_port_t *i2c_port, for (i = 0; i < in_size; i++) { err = i2c_read_byte(i2c_port, &in[i], - (flags & I2C_XFER_STOP) && (i == in_size - 1)); + (flags & I2C_XFER_STOP) && + (i == in_size - 1)); if (err) goto exit; } @@ -353,9 +353,7 @@ __overridable void board_pre_task_i2c_peripheral_init(void) { } -const struct i2c_drv bitbang_drv = { - .xfer = &i2c_bitbang_xfer -}; +const struct i2c_drv bitbang_drv = { .xfer = &i2c_bitbang_xfer }; #ifdef TEST_BUILD int bitbang_start_cond(const struct i2c_port_t *i2c_port) -- cgit v1.2.1 From b0c18ccb74eb659284d812134e2bcab13e399b3f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:55 -0600 Subject: driver/charger/isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id603dcf90d4156a975f8faefadafb9aa5ace4871 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729964 Reviewed-by: Jeremy Bettis --- driver/charger/isl9241.c | 124 ++++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 66 deletions(-) diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c index bd84d30755..586f0db8cf 100644 --- a/driver/charger/isl9241.c +++ b/driver/charger/isl9241.c @@ -29,20 +29,20 @@ #endif /* Sense resistor default values in milli Ohm */ -#define ISL9241_DEFAULT_RS1 20 /* Input current sense resistor */ -#define ISL9241_DEFAULT_RS2 10 /* Battery charge current sense resistor */ +#define ISL9241_DEFAULT_RS1 20 /* Input current sense resistor */ +#define ISL9241_DEFAULT_RS2 10 /* Battery charge current sense resistor */ #define BOARD_RS1 CONFIG_CHARGER_SENSE_RESISTOR_AC #define BOARD_RS2 CONFIG_CHARGER_SENSE_RESISTOR -#define BC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS2) / BOARD_RS2) -#define BC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS2) / ISL9241_DEFAULT_RS2) +#define BC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS2) / BOARD_RS2) +#define BC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS2) / ISL9241_DEFAULT_RS2) -#define AC_REG_TO_CURRENT(REG) (((REG) * ISL9241_DEFAULT_RS1) / BOARD_RS1) -#define AC_CURRENT_TO_REG(CUR) (((CUR) * BOARD_RS1) / ISL9241_DEFAULT_RS1) +#define AC_REG_TO_CURRENT(REG) (((REG)*ISL9241_DEFAULT_RS1) / BOARD_RS1) +#define AC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS1) / ISL9241_DEFAULT_RS1) /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static int learn_mode; @@ -51,29 +51,28 @@ K_MUTEX_DEFINE(control1_mutex_isl9241); /* Charger parameters */ static const struct charger_info isl9241_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = BC_REG_TO_CURRENT(CHARGE_I_MAX), - .current_min = BC_REG_TO_CURRENT(CHARGE_I_MIN), + .current_max = BC_REG_TO_CURRENT(CHARGE_I_MAX), + .current_min = BC_REG_TO_CURRENT(CHARGE_I_MIN), .current_step = BC_REG_TO_CURRENT(CHARGE_I_STEP), - .input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX), - .input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN), + .input_current_max = AC_REG_TO_CURRENT(INPUT_I_MAX), + .input_current_min = AC_REG_TO_CURRENT(INPUT_I_MIN), .input_current_step = AC_REG_TO_CURRENT(INPUT_I_STEP), }; static enum ec_error_list isl9241_discharge_on_ac(int chgnum, int enable); static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum, - int enable); + int enable); static enum ec_error_list isl9241_discharge_on_ac_weak_disable(int chgnum); static inline enum ec_error_list isl9241_read(int chgnum, int offset, int *value) { int rv = i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); if (rv) CPRINTS("%s failed (%d)", __func__, rv); @@ -84,8 +83,7 @@ static inline enum ec_error_list isl9241_write(int chgnum, int offset, int value) { int rv = i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); if (rv) CPRINTS("%s failed (%d)", __func__, rv); @@ -97,8 +95,8 @@ static inline enum ec_error_list isl9241_update(int chgnum, int offset, enum mask_update_action action) { int rv = i2c_update16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, mask, action); + chg_chips[chgnum].i2c_addr_flags, offset, mask, + action); if (rv) CPRINTS("%s failed (%d)", __func__, rv); @@ -227,15 +225,16 @@ static enum ec_error_list isl9241_set_mode(int chgnum, int mode) * MinSystemVoltage 0x00h = disables all battery charging */ rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, - mode & CHARGE_FLAG_INHIBIT_CHARGE ? - 0 : battery_get_info()->voltage_min); + mode & CHARGE_FLAG_INHIBIT_CHARGE ? + 0 : + battery_get_info()->voltage_min); if (rv) return rv; /* POR reset */ if (mode & CHARGE_FLAG_POR_RESET) { rv = isl9241_write(chgnum, ISL9241_REG_CONTROL3, - ISL9241_CONTROL3_DIGITAL_RESET); + ISL9241_CONTROL3_DIGITAL_RESET); } return rv; @@ -256,7 +255,7 @@ static enum ec_error_list isl9241_get_current(int chgnum, int *current) static enum ec_error_list isl9241_set_current(int chgnum, int current) { return isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, - BC_CURRENT_TO_REG(current)); + BC_CURRENT_TO_REG(current)); } static enum ec_error_list isl9241_get_voltage(int chgnum, int *voltage) @@ -326,12 +325,11 @@ static enum ec_error_list isl9241_post_init(int chgnum) * Writes to ISL9241_REG_CONTROL1, unsafe as it does not lock * control1_mutex_isl9241. */ -static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum, - int enable) +static enum ec_error_list isl9241_discharge_on_ac_unsafe(int chgnum, int enable) { int rv = isl9241_update(chgnum, ISL9241_REG_CONTROL1, - ISL9241_CONTROL1_LEARN_MODE, - (enable) ? MASK_SET : MASK_CLR); + ISL9241_CONTROL1_LEARN_MODE, + (enable) ? MASK_SET : MASK_CLR); if (!rv) learn_mode = enable; @@ -417,7 +415,7 @@ static bool isl9241_is_ac_present(int chgnum) if (rv == EC_SUCCESS) ac_is_present = !!(reg & ISL9241_INFORMATION2_ACOK_PIN); - return ac_is_present; + return ac_is_present; } /* @@ -462,12 +460,12 @@ static enum ec_error_list isl9241_bypass_to_bat(int chgnum) isl9241_update(chgnum, ISL9241_REG_CONTROL3, ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR); /* 5: Set BGATE to normal operation. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL1, - ISL9241_CONTROL1_BGATE_OFF, MASK_CLR); + isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, + MASK_CLR); /* 6: Set ACOK reference to normal value. TODO: Revisit. */ isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE( - ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV)); + ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV)); return EC_SUCCESS; } @@ -493,8 +491,8 @@ static enum ec_error_list isl9241_bypass_chrg_to_bat(int chgnum) isl9241_update(chgnum, ISL9241_REG_CONTROL3, ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR); /* 6: Set BGATE to normal operation. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL1, - ISL9241_CONTROL1_BGATE_OFF, MASK_CLR); + isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, + MASK_CLR); /* 7: Set ACOK reference to normal value. TODO: Revisit. */ isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE(3600)); @@ -533,8 +531,8 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) int voltage; /* 1: Set adapter current limit. */ - isl9241_set_input_current_limit( - chgnum, charge_manager_get_charger_current()); + isl9241_set_input_current_limit(chgnum, + charge_manager_get_charger_current()); /* 2: Set charge pumps to 100%. */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_EN_CHARGE_PUMPS, MASK_SET); @@ -551,8 +549,8 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) */ /* 6*: Reduce system load below ACLIM. */ /* 7: Turn off BGATE */ - isl9241_update(chgnum, ISL9241_REG_CONTROL1, - ISL9241_CONTROL1_BGATE_OFF, MASK_SET); + isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, + MASK_SET); /* 8*: Set MaxSysVoltage to VADP. */ isl9241_get_vbus_voltage(chgnum, 0, &voltage); isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage - 256); @@ -563,13 +561,13 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) /* 11: Wait 1 ms. */ msleep(1); /* 12*: Turn off NGATE. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL0, - ISL9241_CONTROL0_NGATE_OFF, MASK_SET); + isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF, + MASK_SET); /* 14*: Stop switching. */ isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0); /* 15: Set BGATE to normal operation. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL1, - ISL9241_CONTROL1_BGATE_OFF, MASK_CLR); + isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, + MASK_CLR); /* * Suggestion-1: If ACOK goes low before step A16, stop here * then execute the steps for Bypass to BAT to abort. @@ -626,8 +624,8 @@ static enum ec_error_list isl9241_bypass_to_nvdc(int chgnum) /* 7*: Wait until VSYS == MaxSysVoltage. */ msleep(1); /* 8*: Turn on NGATE. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL0, - ISL9241_CONTROL0_NGATE_OFF, MASK_CLR); + isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF, + MASK_CLR); /* 10*: Turn off Bypass gate */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR); @@ -714,11 +712,11 @@ static void isl9241_init(int chgnum) * [15:13]: Trickle Charging Current (battery pre-charge current) * [10:9] : Prochot# Debounce time (1000us) */ - if (isl9241_update(chgnum, ISL9241_REG_CONTROL2, - (ISL9241_CONTROL2_TRICKLE_CHG_CURR( - bi->precharge_current) | - ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000), - MASK_SET)) + if (isl9241_update( + chgnum, ISL9241_REG_CONTROL2, + (ISL9241_CONTROL2_TRICKLE_CHG_CURR(bi->precharge_current) | + ISL9241_CONTROL2_PROCHOT_DEBOUNCE_1000), + MASK_SET)) goto init_fail; /* @@ -726,8 +724,7 @@ static void isl9241_init(int chgnum) * [14]: ACLIM Reload (Do not reload) */ if (isl9241_update(chgnum, ISL9241_REG_CONTROL3, - ISL9241_CONTROL3_ACLIM_RELOAD, - MASK_SET)) + ISL9241_CONTROL3_ACLIM_RELOAD, MASK_SET)) goto init_fail; /* @@ -735,14 +732,12 @@ static void isl9241_init(int chgnum) * [13]: Slew rate control enable (sets VSYS ramp to 8mV/us) */ if (isl9241_update(chgnum, ISL9241_REG_CONTROL4, - ISL9241_CONTROL4_SLEW_RATE_CTRL, - MASK_SET)) + ISL9241_CONTROL4_SLEW_RATE_CTRL, MASK_SET)) goto init_fail; #ifndef CONFIG_CHARGE_RAMP_HW if (isl9241_update(chgnum, ISL9241_REG_CONTROL0, - ISL9241_CONTROL0_INPUT_VTG_REGULATION, - MASK_SET)) + ISL9241_CONTROL0_INPUT_VTG_REGULATION, MASK_SET)) goto init_fail; #endif @@ -751,7 +746,7 @@ static void isl9241_init(int chgnum) goto init_fail; ctl_val &= ~ISL9241_CONTROL1_SWITCHING_FREQ_MASK; ctl_val |= ((CONFIG_ISL9241_SWITCHING_FREQ << 7) & - ISL9241_CONTROL1_SWITCHING_FREQ_MASK); + ISL9241_CONTROL1_SWITCHING_FREQ_MASK); if (isl9241_write(chgnum, ISL9241_REG_CONTROL1, ctl_val)) goto init_fail; #endif @@ -823,22 +818,19 @@ static int isl9241_ramp_get_current_limit(int chgnum) */ static void isl9241_restart_charge_voltage_when_full(void) { - if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL - && battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) { + if (!chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && + charge_get_state() == PWR_STATE_CHARGE_NEAR_FULL && + battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) { charger_discharge_on_ac(1); msleep(50); charger_discharge_on_ac(0); } } -DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, - isl9241_restart_charge_voltage_when_full, +DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, isl9241_restart_charge_voltage_when_full, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, - isl9241_restart_charge_voltage_when_full, +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, isl9241_restart_charge_voltage_when_full, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - isl9241_restart_charge_voltage_when_full, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, isl9241_restart_charge_voltage_when_full, HOOK_PRIO_DEFAULT); /*****************************************************************************/ -- cgit v1.2.1 From 7734ce5632f4b5ea23fca064f0f84d4941e54086 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:52 -0600 Subject: driver/retimer/tdp142.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1c1a4ef7c335e4a758947d024345ed1a7886142 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730060 Reviewed-by: Jeremy Bettis --- driver/retimer/tdp142.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/driver/retimer/tdp142.c b/driver/retimer/tdp142.c index e1632150d0..5368c70b59 100644 --- a/driver/retimer/tdp142.c +++ b/driver/retimer/tdp142.c @@ -12,18 +12,12 @@ static enum ec_error_list tdp142_write(int offset, int data) { - return i2c_write8(TDP142_I2C_PORT, - TDP142_I2C_ADDR, - offset, data); - + return i2c_write8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, data); } static enum ec_error_list tdp142_read(int offset, int *regval) { - return i2c_read8(TDP142_I2C_PORT, - TDP142_I2C_ADDR, - offset, regval); - + return i2c_read8(TDP142_I2C_PORT, TDP142_I2C_ADDR, offset, regval); } enum ec_error_list tdp142_set_ctlsel(enum tdp142_ctlsel selection) -- cgit v1.2.1 From cb928caf5d68ae5954459ed315e8eb020175c028 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:28 -0600 Subject: zephyr/shim/src/bc12_pi3usb9201.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e2e822e03f4e737f1249a3ed01db6cf77d29a68 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730862 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/bc12_pi3usb9201.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/src/bc12_pi3usb9201.c b/zephyr/shim/src/bc12_pi3usb9201.c index 3322e0770c..137441ba52 100644 --- a/zephyr/shim/src/bc12_pi3usb9201.c +++ b/zephyr/shim/src/bc12_pi3usb9201.c @@ -14,28 +14,25 @@ #include "usb_pd.h" #include "usbc/utils.h" - #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0, - "No compatible BC1.2 instance found"); + "No compatible BC1.2 instance found"); -#define USBC_PORT_BC12(inst) \ - { \ - .i2c_port = I2C_PORT(DT_PHANDLE(DT_DRV_INST(inst), port)), \ - .i2c_addr_flags = DT_STRING_UPPER_TOKEN( \ - DT_DRV_INST(inst), i2c_addr_flags), \ +#define USBC_PORT_BC12(inst) \ + { \ + .i2c_port = I2C_PORT(DT_PHANDLE(DT_DRV_INST(inst), port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(DT_DRV_INST(inst), \ + i2c_addr_flags), \ }, const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { DT_INST_FOREACH_STATUS_OKAY(USBC_PORT_BC12) }; -static void bc12_enable_irqs(void) -{ +static void bc12_enable_irqs(void){ DT_INST_FOREACH_STATUS_OKAY(BC12_GPIO_ENABLE_INTERRUPT) -} -DECLARE_HOOK(HOOK_INIT, bc12_enable_irqs, HOOK_PRIO_DEFAULT); +} DECLARE_HOOK(HOOK_INIT, bc12_enable_irqs, HOOK_PRIO_DEFAULT); #if DT_INST_NODE_HAS_PROP(0, irq) void usb0_evt(enum gpio_signal signal) -- cgit v1.2.1 From 18aebab708567f5853d77cb9732d4cc8825aa160 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:50 -0600 Subject: zephyr/projects/nissa/src/craask/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibff8f72a9f4aeba8580176833b8bb7865ca14adf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730785 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/craask/usbc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/nissa/src/craask/usbc.c b/zephyr/projects/nissa/src/craask/usbc.c index 32a390e502..dcf613bd4b 100644 --- a/zephyr/projects/nissa/src/craask/usbc.c +++ b/zephyr/projects/nissa/src/craask/usbc.c @@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port) usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); } -static inline void poll_usb_gpio(int port, - const struct gpio_dt_spec *gpio, +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, const struct deferred_data *ud) { if (!gpio_pin_get_dt(gpio)) { @@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port, } } -static void poll_c0_int (void) +static void poll_c0_int(void) { - poll_usb_gpio(0, - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), &poll_c0_int_data); } -static void poll_c1_int (void) +static void poll_c1_int(void) { - poll_usb_gpio(1, - GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), &poll_c1_int_data); } -- cgit v1.2.1 From 99a25096a0b6ce673fe1541de088c6e0e39fe7c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:49 -0600 Subject: driver/retimer/ps8818.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If63b05db72d20f407137e86b4e56707a1708b1a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730059 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8818.h | 123 +++++++++++++++++++++++------------------------- 1 file changed, 60 insertions(+), 63 deletions(-) diff --git a/driver/retimer/ps8818.h b/driver/retimer/ps8818.h index b56df4b411..ee1713f3ec 100644 --- a/driver/retimer/ps8818.h +++ b/driver/retimer/ps8818.h @@ -9,91 +9,88 @@ #ifndef __CROS_EC_USB_RETIMER_PS8818_H #define __CROS_EC_USB_RETIMER_PS8818_H -#define PS8818_I2C_ADDR_FLAGS 0x28 +#define PS8818_I2C_ADDR_FLAGS 0x28 /* * PAGE 0 Register Definitions */ -#define PS8818_REG_PAGE0 0x00 +#define PS8818_REG_PAGE0 0x00 -#define PS8818_REG0_FLIP 0x00 -#define PS8818_FLIP_CONFIG BIT(7) -#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 +#define PS8818_REG0_FLIP 0x00 +#define PS8818_FLIP_CONFIG BIT(7) +#define PS8818_FLIP_NON_RESERVED_MASK 0xE0 -#define PS8818_REG0_MODE 0x01 -#define PS8818_MODE_DP_ENABLE BIT(7) -#define PS8818_MODE_USB_ENABLE BIT(6) -#define PS8818_MODE_NON_RESERVED_MASK 0xC0 +#define PS8818_REG0_MODE 0x01 +#define PS8818_MODE_DP_ENABLE BIT(7) +#define PS8818_MODE_USB_ENABLE BIT(6) +#define PS8818_MODE_NON_RESERVED_MASK 0xC0 -#define PS8818_REG0_DPHPD_CONFIG 0x02 -#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) -#define PS8818_DPHPD_PLUGGED BIT(6) -#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC +#define PS8818_REG0_DPHPD_CONFIG 0x02 +#define PS8818_DPHPD_CONFIG_INHPD_DISABLE BIT(7) +#define PS8818_DPHPD_PLUGGED BIT(6) +#define PS8818_DPHPD_NON_RESERVED_MASK 0xFC /* * PAGE 1 Register Definitions */ -#define PS8818_REG_PAGE1 0x01 +#define PS8818_REG_PAGE1 0x01 -#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 -#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 -#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 -#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A -#define PS8818_REG1_APRX1_DE_LEVEL 0x0C -#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 -#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 -#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 -#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A -#define PS8818_EQ_LEVEL_UP_9DB (0) -#define PS8818_EQ_LEVEL_UP_10DB (1) -#define PS8818_EQ_LEVEL_UP_12DB (2) -#define PS8818_EQ_LEVEL_UP_13DB (3) -#define PS8818_EQ_LEVEL_UP_16DB (4) -#define PS8818_EQ_LEVEL_UP_17DB (5) -#define PS8818_EQ_LEVEL_UP_18DB (6) -#define PS8818_EQ_LEVEL_UP_19DB (7) -#define PS8818_EQ_LEVEL_UP_20DB (8) -#define PS8818_EQ_LEVEL_UP_21DB (9) -#define PS8818_EQ_LEVEL_UP_MASK (0x0F) +#define PS8818_REG1_APTX1EQ_10G_LEVEL 0x00 +#define PS8818_REG1_APTX2EQ_10G_LEVEL 0x02 +#define PS8818_REG1_CRX1EQ_10G_LEVEL 0x08 +#define PS8818_REG1_CRX2EQ_10G_LEVEL 0x0A +#define PS8818_REG1_APRX1_DE_LEVEL 0x0C +#define PS8818_REG1_APTX1EQ_5G_LEVEL 0x70 +#define PS8818_REG1_APTX2EQ_5G_LEVEL 0x72 +#define PS8818_REG1_CRX1EQ_5G_LEVEL 0x78 +#define PS8818_REG1_CRX2EQ_5G_LEVEL 0x7A +#define PS8818_EQ_LEVEL_UP_9DB (0) +#define PS8818_EQ_LEVEL_UP_10DB (1) +#define PS8818_EQ_LEVEL_UP_12DB (2) +#define PS8818_EQ_LEVEL_UP_13DB (3) +#define PS8818_EQ_LEVEL_UP_16DB (4) +#define PS8818_EQ_LEVEL_UP_17DB (5) +#define PS8818_EQ_LEVEL_UP_18DB (6) +#define PS8818_EQ_LEVEL_UP_19DB (7) +#define PS8818_EQ_LEVEL_UP_20DB (8) +#define PS8818_EQ_LEVEL_UP_21DB (9) +#define PS8818_EQ_LEVEL_UP_MASK (0x0F) -#define PS8818_REG1_RX_PHY 0x6D -#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) -#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) -#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) -#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) -#define PS8818_RX_INPUT_TERM_MASK (3 << 6) +#define PS8818_REG1_RX_PHY 0x6D +#define PS8818_RX_INPUT_TERM_112_OHM (0 << 6) +#define PS8818_RX_INPUT_TERM_104_OHM (1 << 6) +#define PS8818_RX_INPUT_TERM_96_OHM (2 << 6) +#define PS8818_RX_INPUT_TERM_85_OHM (3 << 6) +#define PS8818_RX_INPUT_TERM_MASK (3 << 6) -#define PS8818_REG1_DPEQ_LEVEL 0xB6 -#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) -#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) -#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) -#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) -#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) -#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) -#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) -#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) -#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) -#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) -#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) +#define PS8818_REG1_DPEQ_LEVEL 0xB6 +#define PS8818_DPEQ_LEVEL_UP_9DB (0 << 3) +#define PS8818_DPEQ_LEVEL_UP_10DB (1 << 3) +#define PS8818_DPEQ_LEVEL_UP_12DB (2 << 3) +#define PS8818_DPEQ_LEVEL_UP_13DB (3 << 3) +#define PS8818_DPEQ_LEVEL_UP_16DB (4 << 3) +#define PS8818_DPEQ_LEVEL_UP_17DB (5 << 3) +#define PS8818_DPEQ_LEVEL_UP_18DB (6 << 3) +#define PS8818_DPEQ_LEVEL_UP_19DB (7 << 3) +#define PS8818_DPEQ_LEVEL_UP_20DB (8 << 3) +#define PS8818_DPEQ_LEVEL_UP_21DB (9 << 3) +#define PS8818_DPEQ_LEVEL_UP_MASK (0x0F << 3) /* * PAGE 2 Register Definitions */ -#define PS8818_REG_PAGE2 0x02 +#define PS8818_REG_PAGE2 0x02 -#define PS8818_REG2_TX_STATUS 0x42 -#define PS8818_REG2_RX_STATUS 0x46 -#define PS8818_STATUS_NORMAL_OPERATION BIT(7) -#define PS8818_STATUS_10_GBPS BIT(5) +#define PS8818_REG2_TX_STATUS 0x42 +#define PS8818_REG2_RX_STATUS 0x46 +#define PS8818_STATUS_NORMAL_OPERATION BIT(7) +#define PS8818_STATUS_10_GBPS BIT(5) extern const struct usb_mux_driver ps8818_usb_retimer_driver; -int ps8818_i2c_read(const struct usb_mux *me, - int page, int offset, int *data); -int ps8818_i2c_write(const struct usb_mux *me, - int page, int offset, int data); -int ps8818_i2c_field_update8(const struct usb_mux *me, - int page, int offset, +int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data); +int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data); +int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, uint8_t field_mask, uint8_t set_value); #endif /* __CROS_EC_USB_RETIMER_PS8818_H */ -- cgit v1.2.1 From d61cd357988ea49bdf29d68d53f496dbdefcb8f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:46 -0600 Subject: chip/stm32/bkpdata.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I880bdc51daed603c63ece38707322d4344045e4b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729456 Reviewed-by: Jeremy Bettis --- chip/stm32/bkpdata.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c index ded77401d6..5a51128fc3 100644 --- a/chip/stm32/bkpdata.c +++ b/chip/stm32/bkpdata.c @@ -76,8 +76,7 @@ uint32_t bkpdata_read_reset_flags() return flags; } -__overridable -void bkpdata_write_reset_flags(uint32_t save_flags) +__overridable void bkpdata_write_reset_flags(uint32_t save_flags) { bkpdata_write(BKPDATA_INDEX_SAVED_RESET_FLAGS, save_flags & 0xffff); #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS -- cgit v1.2.1 From ffce9f6134555416e9af3236850fa01af1be6e04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:11 -0600 Subject: board/c2d2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fb6d3d56d6b0caf8cb0874dff2ab2f8dfcc7681 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728113 Reviewed-by: Jeremy Bettis --- board/c2d2/board.h | 49 ++++++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/board/c2d2/board.h b/board/c2d2/board.h index ada5b01ab6..607138f3e8 100644 --- a/board/c2d2/board.h +++ b/board/c2d2/board.h @@ -21,9 +21,9 @@ /* Enable USART */ #define CONFIG_STREAM_USART -#define CONFIG_STREAM_USART1 /* EC USART */ -#define CONFIG_STREAM_USART3 /* AP USART - not connected by default */ -#define CONFIG_STREAM_USART4 /* H1 USART */ +#define CONFIG_STREAM_USART1 /* EC USART */ +#define CONFIG_STREAM_USART3 /* AP USART - not connected by default */ +#define CONFIG_STREAM_USART4 /* H1 USART */ #define CONFIG_STREAM_USB #define CONFIG_CMD_USART_INFO @@ -45,35 +45,34 @@ #define DEFAULT_SERIALNO "Uninitialized" #define CONFIG_USB_UPDATE - /* USB interface indexes (use define rather than enum to expand them) * * Note these values are used in servo_interface.py for the 'interface' value */ -#define USB_IFACE_USART4_STREAM 0 /* H1 */ -#define USB_IFACE_UPDATE 1 -#define USB_IFACE_SPI 2 -#define USB_IFACE_CONSOLE 3 -#define USB_IFACE_I2C 4 -#define USB_IFACE_USART3_STREAM 5 /* AP (not connected by default) */ -#define USB_IFACE_USART1_STREAM 6 /* EC */ -#define USB_IFACE_COUNT 7 +#define USB_IFACE_USART4_STREAM 0 /* H1 */ +#define USB_IFACE_UPDATE 1 +#define USB_IFACE_SPI 2 +#define USB_IFACE_CONSOLE 3 +#define USB_IFACE_I2C 4 +#define USB_IFACE_USART3_STREAM 5 /* AP (not connected by default) */ +#define USB_IFACE_USART1_STREAM 6 /* EC */ +#define USB_IFACE_COUNT 7 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_USART4_STREAM 1 -#define USB_EP_UPDATE 2 -#define USB_EP_SPI 3 -#define USB_EP_CONSOLE 4 -#define USB_EP_I2C 5 -#define USB_EP_USART3_STREAM 6 -#define USB_EP_USART1_STREAM 7 -#define USB_EP_COUNT 8 +#define USB_EP_CONTROL 0 +#define USB_EP_USART4_STREAM 1 +#define USB_EP_UPDATE 2 +#define USB_EP_SPI 3 +#define USB_EP_CONSOLE 4 +#define USB_EP_I2C 5 +#define USB_EP_USART3_STREAM 6 +#define USB_EP_USART1_STREAM 7 +#define USB_EP_COUNT 8 /* Enable control of SPI over USB */ #define CONFIG_USB_SPI #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FLASH_PORT 0 /* SPI2 is 0th in stm's SPI_REGS var */ +#define CONFIG_SPI_FLASH_PORT 0 /* SPI2 is 0th in stm's SPI_REGS var */ /* Enable control of I2C over USB */ #define CONFIG_USB_I2C @@ -87,8 +86,8 @@ #define CONFIG_I2C_XFER_LARGE_TRANSFER #undef CONFIG_USB_I2C_MAX_WRITE_COUNT #undef CONFIG_USB_I2C_MAX_READ_COUNT -#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4) -#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6) +#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4) +#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6) /* * Set all ADC samples to take 239.5 clock cycles. This allows us to measure @@ -114,7 +113,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" -- cgit v1.2.1 From b5a5432ecc56c9ea669bf89a1ed55468037a066a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:25 -0600 Subject: driver/usb_mux/it5205.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97e1ff90b1503c5dfaa88736d9492836afae94d8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730161 Reviewed-by: Jeremy Bettis --- driver/usb_mux/it5205.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/driver/usb_mux/it5205.c b/driver/usb_mux/it5205.c index 0cfecdeda0..26073268c3 100644 --- a/driver/usb_mux/it5205.c +++ b/driver/usb_mux/it5205.c @@ -25,15 +25,15 @@ static int it5205_write(const struct usb_mux *me, uint8_t reg, uint8_t val) static int it5205h_sbu_update(const struct usb_mux *me, uint8_t reg, uint8_t mask, enum mask_update_action action) { - return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, - reg, mask, action); + return i2c_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg, mask, + action); } static int it5205h_sbu_field_update(const struct usb_mux *me, uint8_t reg, uint8_t field_mask, uint8_t set_value) { - return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, - reg, field_mask, set_value); + return i2c_field_update8(me->i2c_port, IT5205H_SBU_I2C_ADDR_FLAGS, reg, + field_mask, set_value); } struct mux_chip_id_t { @@ -42,10 +42,10 @@ struct mux_chip_id_t { }; static const struct mux_chip_id_t mux_chip_id_verify[] = { - { '5', IT5205_REG_CHIP_ID3}, - { '2', IT5205_REG_CHIP_ID2}, - { '0', IT5205_REG_CHIP_ID1}, - { '5', IT5205_REG_CHIP_ID0}, + { '5', IT5205_REG_CHIP_ID3 }, + { '2', IT5205_REG_CHIP_ID2 }, + { '0', IT5205_REG_CHIP_ID1 }, + { '5', IT5205_REG_CHIP_ID0 }, }; static int it5205_init(const struct usb_mux *me) @@ -67,16 +67,16 @@ static int it5205_init(const struct usb_mux *me) } if (IS_ENABLED(CONFIG_USB_MUX_IT5205H_SBU_OVP)) { - RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_VSR, - IT5205H_VREF_SELECT_MASK, - IT5205H_VREF_SELECT_3_3V)); + RETURN_ERROR(it5205h_sbu_field_update( + me, IT5205H_REG_VSR, IT5205H_VREF_SELECT_MASK, + IT5205H_VREF_SELECT_3_3V)); RETURN_ERROR(it5205h_sbu_field_update(me, IT5205H_REG_CSBUOVPSR, - IT5205H_OVP_SELECT_MASK, - IT5205H_OVP_3_68V)); + IT5205H_OVP_SELECT_MASK, + IT5205H_OVP_3_68V)); - RETURN_ERROR(it5205h_sbu_update(me, IT5205H_REG_ISR, - IT5205H_ISR_CSBU_MASK, MASK_CLR)); + RETURN_ERROR(it5205h_sbu_update( + me, IT5205H_REG_ISR, IT5205H_ISR_CSBU_MASK, MASK_CLR)); RETURN_ERROR(it5205h_enable_csbu_switch(me, true)); } @@ -86,8 +86,8 @@ static int it5205_init(const struct usb_mux *me) enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me, bool en) { - return it5205h_sbu_update(me, IT5205H_REG_CSBUSR, - IT5205H_CSBUSR_SWITCH, en ? MASK_SET : MASK_CLR); + return it5205h_sbu_update(me, IT5205H_REG_CSBUSR, IT5205H_CSBUSR_SWITCH, + en ? MASK_SET : MASK_CLR); } /* Writes control register to set switch mode */ -- cgit v1.2.1 From ee69e4f1c77e1818bb98189098d11800730c6be3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:15 -0600 Subject: zephyr/shim/include/zephyr_host_command.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I80a0caae8f22b1e4de6abea974c0d0cb0f1df38c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730859 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_host_command.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/include/zephyr_host_command.h b/zephyr/shim/include/zephyr_host_command.h index cc67049614..614d73b10d 100644 --- a/zephyr/shim/include/zephyr_host_command.h +++ b/zephyr/shim/include/zephyr_host_command.h @@ -27,11 +27,11 @@ bool in_host_command_main(void); /** * See include/host_command.h for documentation. */ -#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask) \ - STRUCT_SECTION_ITERABLE(host_command, _cros_hcmd_##_command) = { \ - .command = _command, \ - .handler = _routine, \ - .version_mask = _version_mask, \ +#define DECLARE_HOST_COMMAND(_command, _routine, _version_mask) \ + STRUCT_SECTION_ITERABLE(host_command, _cros_hcmd_##_command) = { \ + .command = _command, \ + .handler = _routine, \ + .version_mask = _version_mask, \ } #else /* !CONFIG_PLATFORM_EC_HOSTCMD */ @@ -39,12 +39,12 @@ bool in_host_command_main(void); * Create a fake routine to call the function. The linker should * garbage-collect it since it is behind 'if (0)' */ -#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ - int __remove_ ## command(void) \ - { \ - if (0) \ - routine(NULL); \ - return 0; \ +#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ + int __remove_##command(void) \ + { \ + if (0) \ + routine(NULL); \ + return 0; \ } #endif /* CONFIG_PLATFORM_EC_HOSTCMD */ -- cgit v1.2.1 From 6f2041d10cae417194903629c3cb997532db68cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:38 -0600 Subject: chip/stm32/i2c-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0751e3447791c37554f8b5e1b259bb139dafcb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729514 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32f0.c | 77 ++++++++++++++++++++++++------------------------ 1 file changed, 39 insertions(+), 38 deletions(-) diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c index f78a450a4e..7120144c4a 100644 --- a/chip/stm32/i2c-stm32f0.c +++ b/chip/stm32/i2c-stm32f0.c @@ -23,10 +23,10 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS #if (I2C_PORT_EC == STM32_I2C1_PORT) @@ -36,11 +36,10 @@ #endif #endif - /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -52,8 +51,8 @@ void i2c_set_timeout(int port, uint32_t timeout) /* timingr register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /** @@ -72,7 +71,7 @@ static int wait_isr(int port, int mask) /* Check for errors */ if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) + STM32_I2C_ISR_NACK)) return EC_ERROR_UNKNOWN; /* Check for desired mask */ @@ -118,8 +117,7 @@ int chip_i2c_set_freq(int port, enum i2c_freq freq) enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) if (port == STM32_I2C1_PORT) { /* * Use HSI (8MHz) for i2c clock. This allows smooth wakeup @@ -165,8 +163,7 @@ static int i2c_init_port(const struct i2c_port_t *p) if (port == STM32_I2C1_PORT) { #if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ - defined(CONFIG_LOW_POWER_IDLE) && \ - (I2C_PORT_EC == STM32_I2C1_PORT) + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) /* * Use HSI (8MHz) for i2c clock. This allows smooth wakeup * from STOP mode since HSI is only clock running immediately @@ -218,7 +215,7 @@ static int i2c_init_port(const struct i2c_port_t *p) */ static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; +static uint8_t *const host_buffer = host_buffer_padded + 2; static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); static int host_i2c_resp_port; static int tx_pending; @@ -330,7 +327,7 @@ static void i2c_event_handler(int port) /* Clear error status bits */ STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | - STM32_I2C_ICR_ARLOCF; + STM32_I2C_ICR_ARLOCF; } /* Transfer matched our peripheral address */ @@ -439,16 +436,18 @@ static void i2c_event_handler(int port) } } } -static void i2c2_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } +static void i2c2_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2); #endif /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -495,13 +494,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -524,11 +523,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -614,7 +613,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } void i2c_init(void) @@ -626,9 +625,10 @@ void i2c_init(void) i2c_init_port(p); #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; #if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) /* * If using low power idle and EC port is I2C1, then set I2C1 to wake @@ -637,15 +637,16 @@ void i2c_init(void) */ STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; #endif - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); #ifdef TCPCI_I2C_PERIPHERAL /* * Configure TCPC address with OA2[1] masked so that we respond * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. */ - STM32_I2C_OAR2(I2C_PORT_EC) = 0x8100 - | (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); + STM32_I2C_OAR2(I2C_PORT_EC) = + 0x8100 | + (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); #endif task_enable_irq(IRQ_PERIPHERAL); #endif -- cgit v1.2.1 From 6fc8bdbf3c8cae0fbb0e89b6bd251770d41328bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:26 -0600 Subject: board/beetley/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id6efb540c72ba27076994dd060067e6723248be2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728048 Reviewed-by: Jeremy Bettis --- board/beetley/board.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/board/beetley/board.h b/board/beetley/board.h index 15eac0d3f8..e80240278c 100644 --- a/board/beetley/board.h +++ b/board/beetley/board.h @@ -42,13 +42,13 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ @@ -112,12 +112,7 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { -- cgit v1.2.1 From e5685cc5e858dc4460320b04a00df11d9e986f41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:29 -0600 Subject: board/drawcia/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If1686339566fa82edbc8db8b3aa1feae1bef1b81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728252 Reviewed-by: Jeremy Bettis --- board/drawcia/board.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/board/drawcia/board.h b/board/drawcia/board.h index 9cff277255..7f00767a10 100644 --- a/board/drawcia/board.h +++ b/board/drawcia/board.h @@ -23,21 +23,22 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -70,8 +71,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -82,8 +83,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -106,21 +107,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 37af0878bd4652b766cc523f5bd648fb3b5e1011 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:04 -0600 Subject: driver/tcpm/nct38xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0f9d3abb49e6a2aa81e83733fd94387d5e9c29a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730081 Reviewed-by: Jeremy Bettis --- driver/tcpm/nct38xx.h | 97 ++++++++++++++++++++++++++------------------------- 1 file changed, 49 insertions(+), 48 deletions(-) diff --git a/driver/tcpm/nct38xx.h b/driver/tcpm/nct38xx.h index a63a9f0808..531ab3252c 100644 --- a/driver/tcpm/nct38xx.h +++ b/driver/tcpm/nct38xx.h @@ -10,71 +10,72 @@ #define __CROS_EC_USB_PD_TCPM_NCT38XX_H /* Chip variant ID (Part number) */ -#define NCT38XX_VARIANT_MASK 0x1C -#define NCT38XX_VARIANT_3807 0x0 -#define NCT38XX_VARIANT_3808 0x2 +#define NCT38XX_VARIANT_MASK 0x1C +#define NCT38XX_VARIANT_3807 0x0 +#define NCT38XX_VARIANT_3808 0x2 /* There are two IO ports in NCT3807 */ -#define NCT38XX_NCT3807_MAX_IO_PORT 2 +#define NCT38XX_NCT3807_MAX_IO_PORT 2 /* There is only one IO port in NCT3808 */ -#define NCT38XX_NCT3808_MAX_IO_PORT 1 +#define NCT38XX_NCT3808_MAX_IO_PORT 1 -#define NCT38XX_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \ - GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_F_RISING | \ - GPIO_INT_F_FALLING | GPIO_INT_F_HIGH | GPIO_INT_F_LOW) +#define NCT38XX_SUPPORT_GPIO_FLAGS \ + (GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \ + GPIO_INT_F_RISING | GPIO_INT_F_FALLING | GPIO_INT_F_HIGH | \ + GPIO_INT_F_LOW) /* I2C interface */ -#define NCT38XX_I2C_ADDR1_1_FLAGS 0x70 -#define NCT38XX_I2C_ADDR1_2_FLAGS 0x71 -#define NCT38XX_I2C_ADDR1_3_FLAGS 0x72 -#define NCT38XX_I2C_ADDR1_4_FLAGS 0x73 +#define NCT38XX_I2C_ADDR1_1_FLAGS 0x70 +#define NCT38XX_I2C_ADDR1_2_FLAGS 0x71 +#define NCT38XX_I2C_ADDR1_3_FLAGS 0x72 +#define NCT38XX_I2C_ADDR1_4_FLAGS 0x73 -#define NCT38XX_I2C_ADDR2_1_FLAGS 0x74 -#define NCT38XX_I2C_ADDR2_2_FLAGS 0x75 -#define NCT38XX_I2C_ADDR2_3_FLAGS 0x76 -#define NCT38XX_I2C_ADDR2_4_FLAGS 0x77 +#define NCT38XX_I2C_ADDR2_1_FLAGS 0x74 +#define NCT38XX_I2C_ADDR2_2_FLAGS 0x75 +#define NCT38XX_I2C_ADDR2_3_FLAGS 0x76 +#define NCT38XX_I2C_ADDR2_4_FLAGS 0x77 -#define NCT38XX_REG_VENDOR_ID_L 0x00 -#define NCT38XX_REG_VENDOR_ID_H 0x01 -#define NCT38XX_VENDOR_ID 0x0416 +#define NCT38XX_REG_VENDOR_ID_L 0x00 +#define NCT38XX_REG_VENDOR_ID_H 0x01 +#define NCT38XX_VENDOR_ID 0x0416 -#define NCT38XX_PRODUCT_ID 0xC301 +#define NCT38XX_PRODUCT_ID 0xC301 /* * Default value from the ROLE_CTRL register on first boot will depend on * whether we're coming from a dead battery state. */ -#define NCT38XX_ROLE_CTRL_DEAD_BATTERY 0x0A -#define NCT39XX_ROLE_CTRL_GOOD_BATTERY 0x4A - -#define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8)) -#define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8)) -#define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8)) -#define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8)) -#define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8)) -#define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8)) -#define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8)) -#define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8)) -#define NCT38XX_REG_MUX_CONTROL 0xD0 -#define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n)) +#define NCT38XX_ROLE_CTRL_DEAD_BATTERY 0x0A +#define NCT39XX_ROLE_CTRL_GOOD_BATTERY 0x4A + +#define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n)*8)) +#define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n)*8)) +#define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n)*8)) +#define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n)*8)) +#define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n)*8)) +#define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n)*8)) +#define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n)*8)) +#define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n)*8)) +#define NCT38XX_REG_MUX_CONTROL 0xD0 +#define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n)) /* NCT3808 only supports GPIO 2/3/4/6/7 */ -#define NCT38XXX_3808_VALID_GPIO_MASK 0xDC +#define NCT38XXX_3808_VALID_GPIO_MASK 0xDC -#define NCT38XX_REG_CTRL_OUT_EN 0xD2 -#define NCT38XX_REG_CTRL_OUT_EN_SRCEN (1 << 0) -#define NCT38XX_REG_CTRL_OUT_EN_FASTEN (1 << 1) -#define NCT38XX_REG_CTRL_OUT_EN_SNKEN (1 << 2) -#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN (1 << 6) +#define NCT38XX_REG_CTRL_OUT_EN 0xD2 +#define NCT38XX_REG_CTRL_OUT_EN_SRCEN (1 << 0) +#define NCT38XX_REG_CTRL_OUT_EN_FASTEN (1 << 1) +#define NCT38XX_REG_CTRL_OUT_EN_SNKEN (1 << 2) +#define NCT38XX_REG_CTRL_OUT_EN_CONNDIREN (1 << 6) -#define NCT38XX_REG_VBC_FAULT_CTL 0xD7 -#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN (1 << 0) -#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN (1 << 1) -#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF (1 << 3) -#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF (1 << 4) -#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF (1 << 5) +#define NCT38XX_REG_VBC_FAULT_CTL 0xD7 +#define NCT38XX_REG_VBC_FAULT_CTL_VC_OCP_EN (1 << 0) +#define NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN (1 << 1) +#define NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF (1 << 3) +#define NCT38XX_REG_VBC_FAULT_CTL_VB_OCP_OFF (1 << 4) +#define NCT38XX_REG_VBC_FAULT_CTL_VC_OVP_OFF (1 << 5) -#define NCT38XX_RESET_HOLD_DELAY_MS 1 +#define NCT38XX_RESET_HOLD_DELAY_MS 1 /* * From the datasheet (section 4.4.2 Reset Timing) as following: @@ -85,8 +86,8 @@ * NCT3808 (dual port) | x | 3ms | * ----------------------+-------+-------+ */ -#define NCT3807_RESET_POST_DELAY_MS 2 -#define NCT3808_RESET_POST_DELAY_MS 3 +#define NCT3807_RESET_POST_DELAY_MS 2 +#define NCT3808_RESET_POST_DELAY_MS 3 extern const struct tcpm_drv nct38xx_tcpm_drv; -- cgit v1.2.1 From 25ebe2597a0aa9876352fd83874cd44eb0890e4c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:06 -0600 Subject: board/kinox/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib81f194e11ffc207c164279f1560853b5c2b50a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728536 Reviewed-by: Jeremy Bettis --- board/kinox/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kinox/usbc_config.c b/board/kinox/usbc_config.c index a5c171bede..a2b8fdca3e 100644 --- a/board/kinox/usbc_config.c +++ b/board/kinox/usbc_config.c @@ -28,8 +28,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From b3e80af86fbf4f61a02799cb73b3244316131b0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:55 -0600 Subject: include/spi_flash.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I058552f2ed90b06b57fc041e7d7fee5263d74568 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730408 Reviewed-by: Jeremy Bettis --- include/spi_flash.h | 52 ++++++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/include/spi_flash.h b/include/spi_flash.h index ca3e796fd3..59f0f418b4 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -12,40 +12,40 @@ #define SPI_FLASH_SIZE(x) (1 << (x)) /* SPI flash instructions */ -#define SPI_FLASH_WRITE_ENABLE 0x06 -#define SPI_FLASH_WRITE_DISABLE 0x04 -#define SPI_FLASH_READ_SR1 0x05 -#define SPI_FLASH_READ_SR2 0x35 -#define SPI_FLASH_WRITE_SR 0x01 -#define SPI_FLASH_ERASE_4KB 0x20 -#define SPI_FLASH_ERASE_32KB 0x52 -#define SPI_FLASH_ERASE_64KB 0xD8 -#define SPI_FLASH_ERASE_CHIP 0xC7 -#define SPI_FLASH_READ 0x03 -#define SPI_FLASH_PAGE_PRGRM 0x02 -#define SPI_FLASH_REL_PWRDWN 0xAB -#define SPI_FLASH_MFR_DEV_ID 0x90 -#define SPI_FLASH_JEDEC_ID 0x9F -#define SPI_FLASH_UNIQUE_ID 0x4B -#define SPI_FLASH_SFDP 0x44 -#define SPI_FLASH_ERASE_SEC_REG 0x44 -#define SPI_FLASH_PRGRM_SEC_REG 0x42 -#define SPI_FLASH_READ_SEC_REG 0x48 -#define SPI_FLASH_ENABLE_RESET 0x66 -#define SPI_FLASH_RESET 0x99 +#define SPI_FLASH_WRITE_ENABLE 0x06 +#define SPI_FLASH_WRITE_DISABLE 0x04 +#define SPI_FLASH_READ_SR1 0x05 +#define SPI_FLASH_READ_SR2 0x35 +#define SPI_FLASH_WRITE_SR 0x01 +#define SPI_FLASH_ERASE_4KB 0x20 +#define SPI_FLASH_ERASE_32KB 0x52 +#define SPI_FLASH_ERASE_64KB 0xD8 +#define SPI_FLASH_ERASE_CHIP 0xC7 +#define SPI_FLASH_READ 0x03 +#define SPI_FLASH_PAGE_PRGRM 0x02 +#define SPI_FLASH_REL_PWRDWN 0xAB +#define SPI_FLASH_MFR_DEV_ID 0x90 +#define SPI_FLASH_JEDEC_ID 0x9F +#define SPI_FLASH_UNIQUE_ID 0x4B +#define SPI_FLASH_SFDP 0x44 +#define SPI_FLASH_ERASE_SEC_REG 0x44 +#define SPI_FLASH_PRGRM_SEC_REG 0x42 +#define SPI_FLASH_READ_SEC_REG 0x48 +#define SPI_FLASH_ENABLE_RESET 0x66 +#define SPI_FLASH_RESET 0x99 /* Maximum single write size (in bytes) for the W25Q64FV SPI flash */ -#define SPI_FLASH_MAX_WRITE_SIZE 256 +#define SPI_FLASH_MAX_WRITE_SIZE 256 /* * Maximum message size (in bytes) for the W25Q64FV SPI flash * Instruction (1) + Address (3) + Data (256) = 260 * Limited by chip maximum input length of write instruction */ -#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4) +#define SPI_FLASH_MAX_MESSAGE_SIZE (SPI_FLASH_MAX_WRITE_SIZE + 4) /* Maximum single read size in bytes. Limited by size of the message buffer */ -#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4) +#define SPI_FLASH_MAX_READ_SIZE (SPI_FLASH_MAX_MESSAGE_SIZE - 4) /* Status register write protect structure */ enum spi_flash_wp { @@ -120,7 +120,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes); * @return EC_SUCCESS, or non-zero if any error. */ int spi_flash_write(unsigned int offset, unsigned int bytes, - const uint8_t *data); + const uint8_t *data); /** * Gets the SPI flash JEDEC ID (manufacturer ID, memory type, and capacity) @@ -185,4 +185,4 @@ int spi_flash_check_protect(unsigned int offset, unsigned int bytes); */ int spi_flash_set_protect(unsigned int offset, unsigned int bytes); -#endif /* __CROS_EC_SPI_FLASH_H */ +#endif /* __CROS_EC_SPI_FLASH_H */ -- cgit v1.2.1 From 72770fd69f772f5e6a44f4a8be99f3a3abdf548d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:41 -0600 Subject: board/storo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief58ab37a9d5cd479c6aaf45bd2db76578ff3eaf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728960 Reviewed-by: Jeremy Bettis --- board/storo/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/storo/led.c b/board/storo/led.c index d5094f1f30..f5480489aa 100644 --- a/board/storo/led.c +++ b/board/storo/led.c @@ -10,28 +10,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From fd19963537a4dda44ac4363a215ad30b3f3f9f7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:01 -0600 Subject: common/usbc/usb_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I652cada425489a8b03ea95cd568ed2dc1ff337b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729783 Reviewed-by: Jeremy Bettis --- common/usbc/usb_mode.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/common/usbc/usb_mode.c b/common/usbc/usb_mode.c index e7c385c59c..b087de9613 100644 --- a/common/usbc/usb_mode.c +++ b/common/usbc/usb_mode.c @@ -26,8 +26,8 @@ #include "usbc_ppc.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -117,7 +117,7 @@ static void usb4_debug_prints(int port, enum usb4_mode_status usb4_status) bool enter_usb_entry_is_done(int port) { return usb4_state[port] == USB4_ACTIVE || - usb4_state[port] == USB4_INACTIVE; + usb4_state[port] == USB4_INACTIVE; } void usb4_exit_mode_request(int port) @@ -153,7 +153,7 @@ static bool enter_usb_response_valid(int port, enum tcpci_msg_type type) * Check for an unexpected response. */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE && - type != TCPCI_MSG_SOP) { + type != TCPCI_MSG_SOP) { enter_usb_failed(port); return false; } @@ -163,7 +163,7 @@ static bool enter_usb_response_valid(int port, enum tcpci_msg_type type) bool enter_usb_port_partner_is_capable(int port) { const struct pd_discovery *disc = - pd_get_am_discovery(port, TCPCI_MSG_SOP); + pd_get_am_discovery(port, TCPCI_MSG_SOP); if (usb4_state[port] == USB4_INACTIVE) return false; @@ -185,7 +185,7 @@ bool enter_usb_cable_is_capable(int port) if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) >= VDM_VER20 && disc_sop_prime->identity.product_t1.a_rev30.vdo_ver >= - VDO_VERSION_1_3) { + VDO_VERSION_1_3) { union active_cable_vdo2_rev30 a2_rev30 = disc_sop_prime->identity.product_t2.a2_rev30; /* @@ -195,25 +195,25 @@ bool enter_usb_cable_is_capable(int port) */ if (a2_rev30.usb_40_support == USB4_NOT_SUPPORTED) return false; - /* - * For VDM version < 2.0 or VDO version < 1.3, do not enter USB4 - * mode if the cable - - * doesn't support modal operation or - * doesn't support Intel SVID or - * doesn't have rounded support. - */ + /* + * For VDM version < 2.0 or VDO version < 1.3, do not + * enter USB4 mode if the cable - doesn't support modal + * operation or doesn't support Intel SVID or doesn't + * have rounded support. + */ } else { const struct pd_discovery *disc = pd_get_am_discovery(port, TCPCI_MSG_SOP); union tbt_mode_resp_cable cable_mode_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, - TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo( + port, TCPCI_MSG_SOP_PRIME) + }; if (!disc->identity.idh.modal_support || - !pd_is_mode_discovered_for_svid(port, - TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) || + !pd_is_mode_discovered_for_svid( + port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL) || cable_mode_resp.tbt_rounded != - TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED) + TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED) return false; } } else { @@ -288,7 +288,7 @@ uint32_t enter_usb_setup_next_msg(int port, enum tcpci_msg_type *type) if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 || disc_sop_prime->identity.product_t1.a_rev30.vdo_ver < - VDO_VERSION_1_3 || + VDO_VERSION_1_3 || get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) { usb4_state[port] = USB4_ENTER_SOP; } else { -- cgit v1.2.1 From 5f22b9a5e638d139e8d63b0892d4ff93c4aa882e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:25 -0600 Subject: include/keyboard_mkbp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4542f4975f62f7d48e98e8c1ebbf17402cc6e3fa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730297 Reviewed-by: Jeremy Bettis --- include/keyboard_mkbp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/keyboard_mkbp.h b/include/keyboard_mkbp.h index 03e84550a7..b80e84c327 100644 --- a/include/keyboard_mkbp.h +++ b/include/keyboard_mkbp.h @@ -18,4 +18,4 @@ */ int mkbp_keyboard_add(const uint8_t *buffp); -#endif /* __CROS_EC_KEYBOARD_MKBP_H */ +#endif /* __CROS_EC_KEYBOARD_MKBP_H */ -- cgit v1.2.1 From adc0ec88606509337c01174f307fef75b65fa748 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:28 -0600 Subject: include/device_event.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6549aab717f79faf0aa4cffa61b9a26e103f0079 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730239 Reviewed-by: Jeremy Bettis --- include/device_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/device_event.h b/include/device_event.h index 7a6403e51d..6b688f80e6 100644 --- a/include/device_event.h +++ b/include/device_event.h @@ -50,4 +50,4 @@ static inline void device_set_single_event(int event) */ void device_enable_event(enum ec_device_event event); -#endif /* __CROS_EC_DEVICE_EVENT_H */ +#endif /* __CROS_EC_DEVICE_EVENT_H */ -- cgit v1.2.1 From b58a3852501da2d3147d20e14897267fcb9cae8a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:13 -0600 Subject: board/gimble/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id51ea67600d1ab35f904a39a98cc11072c529677 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728414 Reviewed-by: Jeremy Bettis --- board/gimble/fw_config.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/board/gimble/fw_config.h b/board/gimble/fw_config.h index 32631f7b77..a621d3ac53 100644 --- a/board/gimble/fw_config.h +++ b/board/gimble/fw_config.h @@ -25,22 +25,19 @@ enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_keyboard_layout { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1 -}; +enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 }; union brya_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; - uint32_t reserved_0 : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t cellular_db : 2; - uint32_t wifi_sar_id : 1; - enum ec_cfg_keyboard_layout kb_layout : 2; - uint32_t reserved_1 : 16; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t reserved_0 : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t cellular_db : 2; + uint32_t wifi_sar_id : 1; + enum ec_cfg_keyboard_layout kb_layout : 2; + uint32_t reserved_1 : 16; }; uint32_t raw_value; }; -- cgit v1.2.1 From ce75b430ae56f941a0ed3ce2296ef1d7fdc11812 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:24 -0600 Subject: zephyr/projects/corsola/include/gpio_map.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40dbd9fd4982eab401b3093417e26057ef63ae06 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730736 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/include/gpio_map.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/zephyr/projects/corsola/include/gpio_map.h b/zephyr/projects/corsola/include/gpio_map.h index 562671b685..1bed290896 100644 --- a/zephyr/projects/corsola/include/gpio_map.h +++ b/zephyr/projects/corsola/include/gpio_map.h @@ -6,16 +6,15 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H - #include #include -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S -#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1 -#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2 -#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 +#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1 +#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2 +#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 #endif #endif /* __ZEPHYR_GPIO_MAP_H */ -- cgit v1.2.1 From b641a12713c575099e638a48a2ed9fd111ecc1a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:36 -0600 Subject: board/ghost/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf19b0059bc474035e74feab58d1d24e5113c0e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728401 Reviewed-by: Jeremy Bettis --- board/ghost/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ghost/board.c b/board/ghost/board.c index d156a78975..dafa99c586 100644 --- a/board/ghost/board.c +++ b/board/ghost/board.c @@ -14,8 +14,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) -- cgit v1.2.1 From 67b3b2595f6aaffbbd6ed0868eef1a24ecb9af05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:49 -0600 Subject: board/primus/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a94cf9ca9701700f8130ef8030de63052741acf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728846 Reviewed-by: Jeremy Bettis --- board/primus/usbc_config.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/primus/usbc_config.c b/board/primus/usbc_config.c index ecaac56b2d..a3a92f6d9f 100644 --- a/board/primus/usbc_config.c +++ b/board/primus/usbc_config.c @@ -3,7 +3,6 @@ * found in the LICENSE file. */ - #include #include @@ -32,8 +31,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -178,7 +177,6 @@ void board_reset_pd_mcu(void) static void board_tcpc_init(void) { - /* Don't reset TCPCs after initial reset */ if (!system_jumped_late()) { board_reset_pd_mcu(); @@ -195,7 +193,6 @@ static void board_tcpc_init(void) /* Enable BC1.2 interrupts. */ gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); - } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); -- cgit v1.2.1 From e3b41f566a4f212d9b1ff1edfe0c7f4c9f03a653 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:11 -0600 Subject: board/brask/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1abfc3719f23a38c6b4050c99e4c4279e1b8d85c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728096 Reviewed-by: Jeremy Bettis --- board/brask/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/brask/usbc_config.c b/board/brask/usbc_config.c index caae5437a9..d320b4f77a 100644 --- a/board/brask/usbc_config.c +++ b/board/brask/usbc_config.c @@ -32,8 +32,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From 708c684cac831bdebe85ebd493fdc16f0ca4bce3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:10 -0600 Subject: baseboard/guybrush/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09842b5fd16eae710f5d9e5a5f4837727b04b9c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727518 Reviewed-by: Jeremy Bettis --- baseboard/guybrush/baseboard.c | 59 +++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c index 6a390b0a43..d4440a1fe1 100644 --- a/baseboard/guybrush/baseboard.c +++ b/baseboard/guybrush/baseboard.c @@ -40,10 +40,10 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format ## args) +#define CPRINTSCHIP(format, args...) cprints(CC_CHIPSET, format##args) static void reset_nct38xx_port(int port); @@ -53,7 +53,7 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* Power Signal Input List */ const struct power_signal_info power_signal_list[] = { @@ -145,8 +145,6 @@ const struct i2c_port_t i2c_ports[] = { }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - - const struct charger_config_t chg_chips[] = { { .i2c_port = I2C_PORT_CHARGER, @@ -235,7 +233,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); -static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t); +static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t); __overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) @@ -389,8 +387,7 @@ DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; @@ -404,7 +401,7 @@ int board_set_active_charge_port(int port) * ahead and reset it so EN_SNK responds properly. */ if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } @@ -453,7 +450,7 @@ int board_set_active_charge_port(int port) * change because we'll brown out. */ if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } else { @@ -505,7 +502,9 @@ int board_is_i2c_port_powered(int port) case I2C_PORT_THERMAL_AP: /* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */ return chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1; + CHIPSET_STATE_ANY_SUSPEND) ? + 0 : + 1; default: return 1; } @@ -516,8 +515,7 @@ int board_is_i2c_port_powered(int port) * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; @@ -528,12 +526,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port, return rv; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void sbu_fault_interrupt(enum ioex_signal signal) @@ -571,10 +568,10 @@ void tcpc_alert_event(enum gpio_signal signal) static void reset_nct38xx_port(int port) { int rv; - int saved_state[IOEX_COUNT] = {0}; + int saved_state[IOEX_COUNT] = { 0 }; enum gpio_signal reset_gpio_l = (port == USBC_PORT_C0) ? - GPIO_USB_C0_TCPC_RST_L : - GPIO_USB_C1_TCPC_RST_L; + GPIO_USB_C0_TCPC_RST_L : + GPIO_USB_C1_TCPC_RST_L; if (port < 0 || port > USBC_PORT_COUNT) { CPRINTSUSB("%s invalid port %d", __func__, port); @@ -877,9 +874,9 @@ static void baseboard_set_en_pwr_pcore(void) * EN_PWR_S0_R. */ gpio_set_level(GPIO_EN_PWR_PCORE_S0_R, - gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) && - gpio_get_level(GPIO_PG_GROUPC_S0_OD) && - gpio_get_level(GPIO_EN_PWR_S0_R)); + gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) && + gpio_get_level(GPIO_PG_GROUPC_S0_OD) && + gpio_get_level(GPIO_EN_PWR_S0_R)); } void baseboard_en_pwr_pcore_signal(enum gpio_signal signal) @@ -891,19 +888,17 @@ static void baseboard_check_groupc_low(void) { /* Warn if we see unexpected sequencing here */ if (!gpio_get_level(GPIO_EN_PWR_S0_R) && - gpio_get_level(GPIO_PG_GROUPC_S0_OD)) + gpio_get_level(GPIO_PG_GROUPC_S0_OD)) CPRINTSCHIP("WARN: PG_GROUPC_S0_OD high while EN_PWR_S0_R low"); - } DECLARE_DEFERRED(baseboard_check_groupc_low); void baseboard_en_pwr_s0(enum gpio_signal signal) { - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ gpio_set_level(GPIO_EN_PWR_S0_R, - gpio_get_level(GPIO_SLP_S3_L) && - gpio_get_level(GPIO_PG_PWR_S5)); + gpio_get_level(GPIO_SLP_S3_L) && + gpio_get_level(GPIO_PG_PWR_S5)); /* * If we set EN_PWR_S0_R low, then check PG_GROUPC_S0_OD went low as @@ -973,7 +968,7 @@ __override void power_board_handle_sleep_hang(enum sleep_hang_type hang_type) ccprints("Consecutive(%d) hard sleep hangs detected!", hard_sleep_hang_count); ccprints("AP will be force shutdown in %dms if hang persists", - HARD_SLEEP_HANG_TIMEOUT); + HARD_SLEEP_HANG_TIMEOUT); } hook_call_deferred(&board_handle_hard_sleep_hang_data, @@ -999,7 +994,7 @@ static void board_handle_hard_sleep_hang(void) /* If AP reset does not break hang, force a shutdown */ shutdown_on_hard_hang = true; ccprints("AP will be shutdown in %dms if hang persists", - HARD_SLEEP_HANG_TIMEOUT); + HARD_SLEEP_HANG_TIMEOUT); hook_call_deferred(&board_handle_hard_sleep_hang_data, HARD_SLEEP_HANG_TIMEOUT * MSEC); chipset_reset(CHIPSET_RESET_HANG_REBOOT); -- cgit v1.2.1 From 4ee224442e5de25885891e008e37084a518d54aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:48 -0600 Subject: board/kano/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic57aeafd11728d1ed9794a4ed5e2c394ce661739 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728482 Reviewed-by: Jeremy Bettis --- board/kano/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kano/fw_config.c b/board/kano/fw_config.c index e6e5ba28bb..8127e78b2f 100644 --- a/board/kano/fw_config.c +++ b/board/kano/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union kano_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 67f8b9952e250e1fc93ed679ff3235151ce34033 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:10 -0600 Subject: baseboard/intelrvp/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If125604449235c8c8354275bdd0da599f9aea8a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727900 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/led.c | 58 ++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/baseboard/intelrvp/led.c b/baseboard/intelrvp/led.c index add2ebbe43..7cb5fad368 100644 --- a/baseboard/intelrvp/led.c +++ b/baseboard/intelrvp/led.c @@ -19,30 +19,30 @@ const int led_charge_lvl_1 = 5; const int led_charge_lvl_2 = 97; struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC } }, }; const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -51,15 +51,15 @@ void led_set_color_power(enum ec_led_colors color) if (color == EC_LED_COLOR_WHITE) #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_ON_LVL); + LED_ON_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ else - /* LED_OFF and unsupported colors */ + /* LED_OFF and unsupported colors */ #ifdef CONFIG_ZEPHYR gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_white_l), - LED_OFF_LVL); + LED_OFF_LVL); #else gpio_set_level(GPIO_PWR_LED_WHITE_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ @@ -70,32 +70,28 @@ void led_set_color_battery(enum ec_led_colors color) switch (color) { case EC_LED_COLOR_RED: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_AMBER: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_ON_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_ON_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_ON_LVL); #endif /* CONFIG_ZEPHYR */ break; case EC_LED_COLOR_GREEN: #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ break; default: /* LED_OFF and other unsupported colors */ #ifdef CONFIG_ZEPHYR - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), - LED_OFF_LVL); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(led_red_l), LED_OFF_LVL); #else gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); #endif /* CONFIG_ZEPHYR */ -- cgit v1.2.1 From f115c04b2c2d6111f3a466e729037095ed4ed2b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:17 -0600 Subject: baseboard/intelrvp/mchp_ec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I401206629dc41703622a63d84673d709b1e5b3e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727903 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/mchp_ec.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/baseboard/intelrvp/mchp_ec.h b/baseboard/intelrvp/mchp_ec.h index 227ccaef6d..594c5fa784 100644 --- a/baseboard/intelrvp/mchp_ec.h +++ b/baseboard/intelrvp/mchp_ec.h @@ -9,10 +9,10 @@ #define __CROS_EC_MCHP_EC_H /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH7 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH3 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 /* * ADC maximum voltage is a board level configuration. -- cgit v1.2.1 From 9b77021c520cffcbf7b4dd44a3bda73882b99b3f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:34 -0600 Subject: chip/mt_scp/mt818x/audio_codec_wov.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I48e4056133c4dabceb83726575f371cd039ab390 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729336 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/audio_codec_wov.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/mt_scp/mt818x/audio_codec_wov.c b/chip/mt_scp/mt818x/audio_codec_wov.c index 0a4684f909..f0da97a1c0 100644 --- a/chip/mt_scp/mt818x/audio_codec_wov.c +++ b/chip/mt_scp/mt818x/audio_codec_wov.c @@ -79,7 +79,7 @@ int32_t audio_codec_wov_read(void *buf, uint32_t count) while (count-- && wov_fifo_level()) { if (IS_ENABLED(CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN)) *out++ = audio_codec_s16_scale_and_clip( - SCP_VIF_FIFO_DATA, gain); + SCP_VIF_FIFO_DATA, gain); else *out++ = SCP_VIF_FIFO_DATA; } -- cgit v1.2.1 From 4251601ad90acdc9b7d12390bfc7d44fb0cefcd6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:11 -0600 Subject: driver/wpc/p9221.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I30d5255d8ce95252eaefc605f0ccbbfc0b1b6ff9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730176 Reviewed-by: Jeremy Bettis --- driver/wpc/p9221.c | 119 +++++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 64 deletions(-) diff --git a/driver/wpc/p9221.c b/driver/wpc/p9221.c index 973d991240..951b7b0f38 100644 --- a/driver/wpc/p9221.c +++ b/driver/wpc/p9221.c @@ -23,19 +23,19 @@ #include #include "printf.h" -#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ##args) -#define P9221_TX_TIMEOUT_MS (20 * 1000*1000) -#define P9221_DCIN_TIMEOUT_MS (2 * 1000*1000) -#define P9221_VRECT_TIMEOUT_MS (2 * 1000*1000) -#define P9221_NOTIFIER_DELAY_MS (80*1000) -#define P9221R7_ILIM_MAX_UA (1600 * 1000) -#define P9221R7_OVER_CHECK_NUM 3 +#define P9221_TX_TIMEOUT_MS (20 * 1000 * 1000) +#define P9221_DCIN_TIMEOUT_MS (2 * 1000 * 1000) +#define P9221_VRECT_TIMEOUT_MS (2 * 1000 * 1000) +#define P9221_NOTIFIER_DELAY_MS (80 * 1000) +#define P9221R7_ILIM_MAX_UA (1600 * 1000) +#define P9221R7_OVER_CHECK_NUM 3 -#define OVC_LIMIT 1 -#define OVC_THRESHOLD 1400000 -#define OVC_BACKOFF_LIMIT 900000 -#define OVC_BACKOFF_AMOUNT 100000 +#define OVC_LIMIT 1 +#define OVC_THRESHOLD 1400000 +#define OVC_BACKOFF_LIMIT 900000 +#define OVC_BACKOFF_AMOUNT 100000 /* P9221 parameters */ static struct wpc_charger_info p9221_charger_info = { @@ -48,10 +48,9 @@ static struct wpc_charger_info *wpc = &p9221_charger_info; static void p9221_set_offline(void); -static const uint32_t p9221_ov_set_lut[] = { - 17000000, 20000000, 15000000, 13000000, - 11000000, 11000000, 11000000, 11000000 -}; +static const uint32_t p9221_ov_set_lut[] = { 17000000, 20000000, 15000000, + 13000000, 11000000, 11000000, + 11000000, 11000000 }; static int p9221_reg_is_8_bit(uint16_t reg) { @@ -98,38 +97,38 @@ static int p9221_reg_is_8_bit(uint16_t reg) static int p9221_read8(uint16_t reg, int *val) { - return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, val, 1); + return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, + 1); } static int p9221_write8(uint16_t reg, int val) { - return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, val, 1); + return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, + 1); } static int p9221_read16(uint16_t reg, int *val) { - return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, val, 2); + return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, + 2); } static int p9221_write16(uint16_t reg, int val) { - return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, val, 2); + return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, + 2); } static int p9221_block_read(uint16_t reg, uint8_t *data, int len) { - return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, data, len); + return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, + data, len); } static int p9221_block_write(uint16_t reg, uint8_t *data, int len) { - return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, - reg, data, len); + return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, + data, len); } static int p9221_set_cmd_reg(uint8_t cmd) @@ -161,30 +160,30 @@ static int p9221_set_cmd_reg(uint8_t cmd) static int p9221_convert_reg_r7(uint16_t reg, uint16_t raw_data, uint32_t *val) { switch (reg) { - case P9221R7_ALIGN_X_ADC_REG: /* raw */ - case P9221R7_ALIGN_Y_ADC_REG: /* raw */ + case P9221R7_ALIGN_X_ADC_REG: /* raw */ + case P9221R7_ALIGN_Y_ADC_REG: /* raw */ *val = raw_data; break; - case P9221R7_VOUT_ADC_REG: /* 12-bit ADC raw */ - case P9221R7_IOUT_ADC_REG: /* 12-bit ADC raw */ - case P9221R7_DIE_TEMP_ADC_REG: /* 12-bit ADC raw */ + case P9221R7_VOUT_ADC_REG: /* 12-bit ADC raw */ + case P9221R7_IOUT_ADC_REG: /* 12-bit ADC raw */ + case P9221R7_DIE_TEMP_ADC_REG: /* 12-bit ADC raw */ case P9221R7_EXT_TEMP_REG: *val = raw_data & 0xFFF; break; - case P9221R7_VOUT_SET_REG: /* 0.1V -> uV */ + case P9221R7_VOUT_SET_REG: /* 0.1V -> uV */ *val = raw_data * 100 * 1000; break; - case P9221R7_IOUT_REG: /* mA -> uA */ - case P9221R7_VRECT_REG: /* mV -> uV */ - case P9221R7_VOUT_REG: /* mV -> uV */ - case P9221R7_OP_FREQ_REG: /* kHz -> Hz */ - case P9221R7_TX_PINGFREQ_REG: /* kHz -> Hz */ + case P9221R7_IOUT_REG: /* mA -> uA */ + case P9221R7_VRECT_REG: /* mV -> uV */ + case P9221R7_VOUT_REG: /* mV -> uV */ + case P9221R7_OP_FREQ_REG: /* kHz -> Hz */ + case P9221R7_TX_PINGFREQ_REG: /* kHz -> Hz */ *val = raw_data * 1000; break; - case P9221R7_ILIM_SET_REG: /* 100mA -> uA, 200mA offset */ + case P9221R7_ILIM_SET_REG: /* 100mA -> uA, 200mA offset */ *val = ((raw_data * 100) + 200) * 1000; break; - case P9221R7_OVSET_REG: /* uV */ + case P9221R7_OVSET_REG: /* uV */ raw_data &= P9221R7_OVSET_MASK; *val = p9221_ov_set_lut[raw_data]; break; @@ -215,8 +214,8 @@ static int p9221_is_online(void) { int chip_id; - if (p9221_read16(P9221_CHIP_ID_REG, &chip_id) - || chip_id != P9221_CHIP_ID) + if (p9221_read16(P9221_CHIP_ID_REG, &chip_id) || + chip_id != P9221_CHIP_ID) return false; else return true; @@ -227,7 +226,6 @@ int wpc_chip_is_online(void) return p9221_is_online(); } - void p9221_interrupt(enum gpio_signal signal) { task_wake(TASK_ID_WPC); @@ -261,8 +259,8 @@ static int p9221_enable_interrupts_r7(void) CPRINTS("Enable interrupts"); - mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK - | P9221_STAT_VRECT; + mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK | + P9221_STAT_VRECT; p9221r7_clear_interrupts(mask); @@ -307,13 +305,12 @@ static void print_current_samples(uint32_t *iout_val, int count) int i; char temp[P9221R7_OVER_CHECK_NUM * 9 + 1] = { 0 }; - for (i = 0; i < count ; i++) - snprintf(temp + i * 9, sizeof(temp) - i * 9, - "%08x ", iout_val[i]); + for (i = 0; i < count; i++) + snprintf(temp + i * 9, sizeof(temp) - i * 9, "%08x ", + iout_val[i]); CPRINTS("OVER IOUT_SAMPLES: %s", temp); } - /* * Number of times to poll the status to see if the current limit condition * was transient or not. @@ -344,8 +341,8 @@ static void p9221_limit_handler_r7(uint16_t orign_irq_src) reason = P9221_EOP_OVER_CURRENT; for (i = 0; i < P9221R7_OVER_CHECK_NUM; i++) { - ret = p9221r7_clear_interrupts( - irq_src & P9221R7_STAT_LIMIT_MASK); + ret = p9221r7_clear_interrupts(irq_src & + P9221R7_STAT_LIMIT_MASK); msleep(50); if (ret) continue; @@ -434,8 +431,8 @@ static void p9221r7_irq_handler(uint16_t irq_src) /* Proprietary packet */ if (irq_src & P9221R7_STAT_PPRCVD) { - res = p9221_block_read(P9221R7_DATA_RECV_BUF_START, - wpc->pp_buf, sizeof(wpc->pp_buf)); + res = p9221_block_read(P9221R7_DATA_RECV_BUF_START, wpc->pp_buf, + sizeof(wpc->pp_buf)); if (res) { CPRINTS("Failed to read PP: %d", res); wpc->pp_buf_valid = false; @@ -477,7 +474,6 @@ static int p9221_is_epp(void) static void p9221_config_fod(void) { - int epp; uint8_t *fod; int fod_len; @@ -496,8 +492,8 @@ static void p9221_config_fod(void) while (retries) { uint8_t fod_read[fod_len]; - CPRINTS("Writing %s FOD (n=%d try=%d)", - epp ? "EPP" : "BPP", fod_len, retries); + CPRINTS("Writing %s FOD (n=%d try=%d)", epp ? "EPP" : "BPP", + fod_len, retries); ret = p9221_block_write(P9221R7_FOD_REG, fod, fod_len); if (ret) @@ -547,7 +543,6 @@ static void p9221_vbus_check_timeout(void) CPRINTS("Timeout VBUS, online=%d", wpc->online); if (wpc->online) p9221_set_offline(); - } DECLARE_DEFERRED(p9221_vbus_check_timeout); @@ -601,7 +596,7 @@ static int p9221_get_charge_supplier(void) return ret; ret = p9221_block_read(P9221R7_PROP_TX_ID_REG, - (uint8_t *) &tx_id, + (uint8_t *)&tx_id, P9221R7_PROP_TX_ID_SIZE); if (ret) return ret; @@ -609,8 +604,8 @@ static int p9221_get_charge_supplier(void) if (tx_id & P9221R7_PROP_TX_ID_GPP_MASK) wpc->charge_supplier = CHARGE_SUPPLIER_WPC_GPP; - CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d", - txmf_id, tx_id, wpc->charge_supplier); + CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d", txmf_id, + tx_id, wpc->charge_supplier); } else { wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP; CPRINTS("supplier=%d", wpc->charge_supplier); @@ -703,7 +698,6 @@ static int p9221_set_dc_icl(void) return EC_SUCCESS; } - static void p9221_notifier_check_vbus(void) { struct charge_port_info chg; @@ -749,12 +743,10 @@ static void p9221_notifier_check_vbus(void) CPRINTS("check_vbus changed on:%d vbus:%d", wpc->online, wpc->vbus_status); - } static void p9221_detect_work(void) { - CPRINTS("%s online:%d check_vbus:%d check_det:%d vbus:%d", __func__, wpc->online, wpc->p9221_check_vbus, wpc->p9221_check_det, wpc->vbus_status); @@ -766,7 +758,6 @@ static void p9221_detect_work(void) /* Step 2 */ if (wpc->p9221_check_vbus) p9221_notifier_check_vbus(); - } DECLARE_DEFERRED(p9221_detect_work); -- cgit v1.2.1 From bc8124d1c04224eb548f3e8cb1bfca6ac8730fd2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:12 -0600 Subject: board/stern/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a3a48af9bc46fa2f989cd12e079d18971a101a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728968 Reviewed-by: Jeremy Bettis --- board/stern/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/stern/board.h b/board/stern/board.h index f113969d3d..8b1b8b19d8 100644 --- a/board/stern/board.h +++ b/board/stern/board.h @@ -55,7 +55,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -71,20 +71,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 2 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 2 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 833ef54b55af2757bd82ab0ac316e152fda2e0e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:31 -0600 Subject: board/fusb307bgevb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9686c010699fcf3d3861e32e5ff0093c00dd9cff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728380 Reviewed-by: Jeremy Bettis --- board/fusb307bgevb/board.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h index 3495f7125f..c678238e6b 100644 --- a/board/fusb307bgevb/board.h +++ b/board/fusb307bgevb/board.h @@ -8,7 +8,6 @@ #ifndef __CROS_EC_BOARD_H #define __CROS_EC_BOARD_H - /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 @@ -56,11 +55,11 @@ #define PD_OPERATING_POWER_MW 15000 #define PD_MAX_VOLTAGE_MV 20000 #define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) /* Degine board specific type-C power constants */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ /* I2C master port connected to the TCPC */ #define I2C_PORT_TCPC 1 @@ -69,19 +68,19 @@ #define LCD_SLAVE_ADDR 0x27 /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_STREAM 0 -#define USB_IFACE_GPIO 1 -#define USB_IFACE_SPI 2 +#define USB_IFACE_STREAM 0 +#define USB_IFACE_GPIO 1 +#define USB_IFACE_SPI 2 #define USB_IFACE_CONSOLE 3 -#define USB_IFACE_COUNT 4 +#define USB_IFACE_COUNT 4 /* USB endpoint indexes (use define rather than enum to expand them) */ #define USB_EP_CONTROL 0 -#define USB_EP_STREAM 1 -#define USB_EP_GPIO 2 -#define USB_EP_SPI 3 +#define USB_EP_STREAM 1 +#define USB_EP_GPIO 2 +#define USB_EP_SPI 3 #define USB_EP_CONSOLE 4 -#define USB_EP_COUNT 5 +#define USB_EP_COUNT 5 /* Enable control of GPIOs over USB */ #define CONFIG_USB_GPIO -- cgit v1.2.1 From 52eb55ea7b8d9195f867915211951d870dc10d0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:55 -0600 Subject: chip/stm32/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c7f70bae124ab9107a3c2fe05ed2cd3f094b979 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729537 Reviewed-by: Jeremy Bettis --- chip/stm32/uart.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 6be0790c63..121a5fce96 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -18,7 +18,7 @@ #include "stm32-dma.h" /* Console USART index */ -#define UARTN CONFIG_UART_CONSOLE +#define UARTN CONFIG_UART_CONSOLE #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) #ifdef CONFIG_UART_TX_DMA @@ -33,7 +33,7 @@ static const struct dma_option dma_tx_option = { CONFIG_UART_TX_DMA_CH, (void *)&STM32_USART_TDR(UARTN_BASE), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(CONFIG_UART_TX_REQ_CH) #endif }; @@ -51,16 +51,16 @@ static const struct dma_option dma_rx_option = { CONFIG_UART_RX_DMA_CH, (void *)&STM32_USART_RDR(UARTN_BASE), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | #ifdef CHIP_FAMILY_STM32F4 - STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | + STM32_DMA_CCR_CHANNEL(CONFIG_UART_RX_REQ_CH) | #endif - STM32_DMA_CCR_CIRC + STM32_DMA_CCR_CIRC }; -static int dma_rx_len; /* Size of receive DMA circular buffer */ +static int dma_rx_len; /* Size of receive DMA circular buffer */ #endif -static int init_done; /* Initialization done? */ -static int should_stop; /* Last TX control action */ +static int init_done; /* Initialization done? */ +static int should_stop; /* Last TX control action */ int uart_init_done(void) { @@ -249,13 +249,13 @@ static void uart_freq_change(void) freq = clock_get_freq(); #endif -#if (UARTN == 9) /* LPUART */ +#if (UARTN == 9) /* LPUART */ div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE) * 256; #else div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE); #endif -#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ +#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) || \ defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32G4) if (div / 16 > 0) { @@ -277,7 +277,6 @@ static void uart_freq_change(void) /* STM32F only supports x16 oversampling */ STM32_USART_BRR(UARTN_BASE) = div; #endif - } DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT); @@ -286,7 +285,7 @@ void uart_init(void) /* Select clock source */ #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) #if (UARTN == 1) - STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ + STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ #elif (UARTN == 2) STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ #endif /* UARTN */ @@ -339,8 +338,8 @@ void uart_init(void) /* Configure GPIOs */ gpio_config_module(MODULE_UART, 1); -#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) \ -|| defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4) +#if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ + defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32L4) /* * Wake up on start bit detection. WUS can only be written when UE=0, * so clear UE first. @@ -352,7 +351,7 @@ void uart_init(void) * and we don't want to clear an extra flag in the interrupt */ STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_WUS_START_BIT | - STM32_USART_CR3_OVRDIS; + STM32_USART_CR3_OVRDIS; #endif /* @@ -360,11 +359,10 @@ void uart_init(void) * TX and RX enabled. */ #ifdef CHIP_FAMILY_STM32L4 - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_TE | STM32_USART_CR1_RE; #else - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE | + STM32_USART_CR1_RE; #endif /* 1 stop bit, no fancy stuff */ -- cgit v1.2.1 From af9b84688f7cb52d1e48ad2b838828b7a2c4429b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:43 -0600 Subject: test/host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9efd5ac3130e2141b351386f55acb9179f778f75 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730478 Reviewed-by: Jeremy Bettis --- test/host_command.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/test/host_command.c b/test/host_command.c index ba1d4dcd96..5c13e2b4cf 100644 --- a/test/host_command.c +++ b/test/host_command.c @@ -202,15 +202,15 @@ static int test_hostcmd_reuse_response_buffer(void) h->checksum = calculate_checksum(resp_buf, pkt.request_size); ccprintf("\nBuffer contents before process 0x%ph\n", - HEX_BUF(resp_buf, BUFFER_SIZE)); + HEX_BUF(resp_buf, BUFFER_SIZE)); host_packet_receive(&pkt); task_wait_event(-1); ccprintf("\nBuffer contents after process 0x%ph\n", - HEX_BUF(resp_buf, BUFFER_SIZE)); + HEX_BUF(resp_buf, BUFFER_SIZE)); - TEST_EQ(calculate_checksum(resp_buf, - sizeof(*resp) + resp->data_len), 0, "%d"); + TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0, + "%d"); TEST_EQ(resp->result, EC_RES_SUCCESS, "%d"); TEST_EQ(r->out_data, 0x12243648, "0x%x"); @@ -246,11 +246,10 @@ static int test_hostcmd_clears_unused_data(void) hostcmd_send(); - ccprintf("\nBuffer contents 0x%ph\n", - HEX_BUF(resp_buf, BUFFER_SIZE)); + ccprintf("\nBuffer contents 0x%ph\n", HEX_BUF(resp_buf, BUFFER_SIZE)); - TEST_EQ(calculate_checksum(resp_buf, - sizeof(*resp) + resp->data_len), 0, "%d"); + TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0, + "%d"); TEST_EQ(resp->result, EC_RES_SUCCESS, "%d"); /* Ensure partial strings have 0s after the NULL byte */ -- cgit v1.2.1 From 79caa1963f607f71345844ce42835bea62ba094b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:33 -0600 Subject: baseboard/asurada/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I096cdad54c8d0e8e30c9877fa59b209b93916727 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727847 Reviewed-by: Jeremy Bettis --- baseboard/asurada/baseboard.c | 70 ++++++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 37 deletions(-) diff --git a/baseboard/asurada/baseboard.c b/baseboard/asurada/baseboard.c index 1a86950281..3ec15ae80c 100644 --- a/baseboard/asurada/baseboard.c +++ b/baseboard/asurada/baseboard.c @@ -71,34 +71,26 @@ int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "bat_chg", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "usb0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "usb1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C_E_SCL, - .sda = GPIO_I2C_E_SDA - }, + { .name = "bat_chg", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "usb0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "usb1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C_E_SCL, + .sda = GPIO_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -111,15 +103,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } -- cgit v1.2.1 From e9c458623e387b9222bc3018c865f675594a434a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:29 -0600 Subject: driver/tcpm/stm32gx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I057ca353f20a6d660394d298f4bcac8430a69aec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730108 Reviewed-by: Jeremy Bettis --- driver/tcpm/stm32gx.c | 53 ++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/driver/tcpm/stm32gx.c b/driver/tcpm/stm32gx.c index 359c7c1108..8f53fbd0ab 100644 --- a/driver/tcpm/stm32gx.c +++ b/driver/tcpm/stm32gx.c @@ -30,8 +30,8 @@ #error "Unsupported config options of Stm32gx PD driver" #endif -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Wait time for vconn power switch to turn off. */ #ifndef PD_STM32GX_VCONN_TURN_OFF_DELAY_US @@ -40,7 +40,6 @@ static int cached_rp[CONFIG_USB_PD_PORT_MAX_COUNT]; - static int stm32gx_tcpm_get_message_raw(int port, uint32_t *buf, int *head) { return stm32gx_ucpd_get_message_raw(port, buf, head); @@ -57,7 +56,7 @@ static int stm32gx_tcpm_release(int port) } static int stm32gx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { /* Get cc_state value for each CC line */ stm32gx_ucpd_get_cc(port, cc1, cc2); @@ -102,10 +101,8 @@ static int stm32gx_tcpm_set_rx_enable(int port, int enable) return stm32gx_ucpd_set_rx_enable(port, enable); } -static int stm32gx_tcpm_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data) +static int stm32gx_tcpm_transmit(int port, enum tcpci_msg_type type, + uint16_t header, const uint32_t *data) { return stm32gx_ucpd_transmit(port, type, header, data); } @@ -115,9 +112,9 @@ static int stm32gx_tcpm_sop_prime_enable(int port, bool enable) return stm32gx_ucpd_sop_prime_enable(port, enable); } - -static int stm32gx_tcpm_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) +static int +stm32gx_tcpm_get_chip_info(int port, int live, + struct ec_response_pd_chip_info_v1 *chip_info) { return stm32gx_ucpd_get_chip_info(port, live, chip_info); } @@ -147,7 +144,7 @@ static int stm32gx_tcpm_reset_bist_type_2(int port) } enum ec_error_list stm32gx_tcpm_set_bist_test_mode(const int port, - const bool enable) + const bool enable) { return stm32gx_ucpd_set_bist_test_mode(port, enable); } @@ -165,22 +162,22 @@ bool stm32gx_tcpm_check_vbus_level(int port, enum vbus_level level) } const struct tcpm_drv stm32gx_tcpm_drv = { - .init = &stm32gx_tcpm_init, - .release = &stm32gx_tcpm_release, - .get_cc = &stm32gx_tcpm_get_cc, - .check_vbus_level = &stm32gx_tcpm_check_vbus_level, - .select_rp_value = &stm32gx_tcpm_select_rp_value, - .set_cc = &stm32gx_tcpm_set_cc, - .set_polarity = &stm32gx_tcpm_set_polarity, + .init = &stm32gx_tcpm_init, + .release = &stm32gx_tcpm_release, + .get_cc = &stm32gx_tcpm_get_cc, + .check_vbus_level = &stm32gx_tcpm_check_vbus_level, + .select_rp_value = &stm32gx_tcpm_select_rp_value, + .set_cc = &stm32gx_tcpm_set_cc, + .set_polarity = &stm32gx_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &stm32gx_tcpm_sop_prime_enable, + .sop_prime_enable = &stm32gx_tcpm_sop_prime_enable, #endif - .set_vconn = &stm32gx_tcpm_set_vconn, - .set_msg_header = &stm32gx_tcpm_set_msg_header, - .set_rx_enable = &stm32gx_tcpm_set_rx_enable, - .get_message_raw = &stm32gx_tcpm_get_message_raw, - .transmit = &stm32gx_tcpm_transmit, - .get_chip_info = &stm32gx_tcpm_get_chip_info, - .reset_bist_type_2 = &stm32gx_tcpm_reset_bist_type_2, - .set_bist_test_mode = &stm32gx_tcpm_set_bist_test_mode, + .set_vconn = &stm32gx_tcpm_set_vconn, + .set_msg_header = &stm32gx_tcpm_set_msg_header, + .set_rx_enable = &stm32gx_tcpm_set_rx_enable, + .get_message_raw = &stm32gx_tcpm_get_message_raw, + .transmit = &stm32gx_tcpm_transmit, + .get_chip_info = &stm32gx_tcpm_get_chip_info, + .reset_bist_type_2 = &stm32gx_tcpm_reset_bist_type_2, + .set_bist_test_mode = &stm32gx_tcpm_set_bist_test_mode, }; -- cgit v1.2.1 From 844bbe2c84fd921b0a11c336c00d4a73087b1077 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:18 -0600 Subject: board/kukui_scp/venc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8871c1b48ac65607295feefe32cf4a69dd7d39c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728543 Reviewed-by: Jeremy Bettis --- board/kukui_scp/venc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/board/kukui_scp/venc.c b/board/kukui_scp/venc.c index c7e19d120c..cd6ae7550b 100644 --- a/board/kukui_scp/venc.c +++ b/board/kukui_scp/venc.c @@ -20,11 +20,11 @@ static struct consumer const event_venc_consumer; static void event_venc_written(struct consumer const *consumer, size_t count); -static struct queue const event_venc_queue = QUEUE_DIRECT(8, - struct venc_msg, null_producer, event_venc_consumer); +static struct queue const event_venc_queue = + QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer); static struct consumer const event_venc_consumer = { .queue = &event_venc_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_venc_written, }), }; @@ -33,7 +33,9 @@ static venc_msg_handler mtk_venc_msg_handle[VENC_MAX]; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT8183 -void venc_h264_msg_handler(void *data) {} +void venc_h264_msg_handler(void *data) +{ +} #endif static void event_venc_written(struct consumer const *consumer, size_t count) -- cgit v1.2.1 From 9419d4db436b1ed662f028281d94b720e2251c89 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:00 -0600 Subject: driver/accelgyro_lsm6dsm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d675c8c07b6bc3e170b213b15f7c6527dc58bc0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729896 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6dsm.h | 276 ++++++++++++++++++++++----------------------- 1 file changed, 136 insertions(+), 140 deletions(-) diff --git a/driver/accelgyro_lsm6dsm.h b/driver/accelgyro_lsm6dsm.h index 907429257a..35ec27380b 100644 --- a/driver/accelgyro_lsm6dsm.h +++ b/driver/accelgyro_lsm6dsm.h @@ -17,165 +17,163 @@ * 7-bit address is 110101xb. Where 'x' is determined * by the voltage on the ADDR pin */ -#define LSM6DSM_ADDR0_FLAGS 0x6a -#define LSM6DSM_ADDR1_FLAGS 0x6b +#define LSM6DSM_ADDR0_FLAGS 0x6a +#define LSM6DSM_ADDR1_FLAGS 0x6b /* COMMON DEFINE FOR ACCEL-GYRO SENSORS */ -#define LSM6DSM_EN_BIT 0x01 -#define LSM6DSM_DIS_BIT 0x00 +#define LSM6DSM_EN_BIT 0x01 +#define LSM6DSM_DIS_BIT 0x00 /* Access to embedded sensor hub register bank */ -#define LSM6DSM_FUNC_CFG_ACC_ADDR 0x01 -#define LSM6DSM_FUNC_CFG_EN 0x80 -#define LSM6DSM_FUNC_CFG_EN_B 0x20 +#define LSM6DSM_FUNC_CFG_ACC_ADDR 0x01 +#define LSM6DSM_FUNC_CFG_EN 0x80 +#define LSM6DSM_FUNC_CFG_EN_B 0x20 /* FIFO decimator registers and bitmask */ -#define LSM6DSM_FIFO_CTRL1_ADDR 0x06 +#define LSM6DSM_FIFO_CTRL1_ADDR 0x06 /* Output data rate registers and masks */ -#define LSM6DSM_ODR_REG(_sensor) \ - (LSM6DSM_CTRL1_ADDR + _sensor) -#define LSM6DSM_ODR_MASK 0xf0 +#define LSM6DSM_ODR_REG(_sensor) (LSM6DSM_CTRL1_ADDR + _sensor) +#define LSM6DSM_ODR_MASK 0xf0 -#define LSM6DSM_FIFO_CTRL2_ADDR 0x07 +#define LSM6DSM_FIFO_CTRL2_ADDR 0x07 -#define LSM6DSM_FIFO_CTRL3_ADDR 0x08 -#define LSM6DSM_FIFO_DEC_XL_OFF 0 -#define LSM6DSM_FIFO_DEC_G_OFF 3 +#define LSM6DSM_FIFO_CTRL3_ADDR 0x08 +#define LSM6DSM_FIFO_DEC_XL_OFF 0 +#define LSM6DSM_FIFO_DEC_G_OFF 3 -#define LSM6DSM_FIFO_CTRL4_ADDR 0x09 +#define LSM6DSM_FIFO_CTRL4_ADDR 0x09 #define LSM6DSM_FIFO_DECIMATOR(_dec) \ (_dec < 8 ? _dec : (2 + __builtin_ctz(_dec))) /* Hardware FIFO size in byte */ -#define LSM6DSM_MAX_FIFO_SIZE 4096 -#define LSM6DSM_MAX_FIFO_LENGTH (LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE) +#define LSM6DSM_MAX_FIFO_SIZE 4096 +#define LSM6DSM_MAX_FIFO_LENGTH (LSM6DSM_MAX_FIFO_SIZE / OUT_XYZ_SIZE) -#define LSM6DSM_FIFO_CTRL5_ADDR 0x0a -#define LSM6DSM_FIFO_CTRL5_ODR_OFF 3 -#define LSM6DSM_FIFO_CTRL5_ODR_MASK \ - (0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF) -#define LSM6DSM_FIFO_CTRL5_MODE_MASK 0x07 +#define LSM6DSM_FIFO_CTRL5_ADDR 0x0a +#define LSM6DSM_FIFO_CTRL5_ODR_OFF 3 +#define LSM6DSM_FIFO_CTRL5_ODR_MASK (0xf << LSM6DSM_FIFO_CTRL5_ODR_OFF) +#define LSM6DSM_FIFO_CTRL5_MODE_MASK 0x07 -#define LSM6DSM_INT1_CTRL 0x0d -#define LSM6DSM_INT_FIFO_TH 0x08 -#define LSM6DSM_INT_FIFO_OVR 0x10 -#define LSM6DSM_INT_FIFO_FULL 0x20 -#define LSM6DSM_INT_SIGMO 0x40 +#define LSM6DSM_INT1_CTRL 0x0d +#define LSM6DSM_INT_FIFO_TH 0x08 +#define LSM6DSM_INT_FIFO_OVR 0x10 +#define LSM6DSM_INT_FIFO_FULL 0x20 +#define LSM6DSM_INT_SIGMO 0x40 /* Who Am I */ -#define LSM6DSM_WHO_AM_I_REG 0x0f +#define LSM6DSM_WHO_AM_I_REG 0x0f /* LSM6DSM/LSM6DSL/LSM6DS3TR-C */ -#define LSM6DSM_WHO_AM_I 0x6a +#define LSM6DSM_WHO_AM_I 0x6a /* LSM6DS3 */ -#define LSM6DS3_WHO_AM_I 0x69 +#define LSM6DS3_WHO_AM_I 0x69 -#define LSM6DSM_CTRL1_ADDR 0x10 -#define LSM6DSM_XL_ODR_MASK 0xf0 +#define LSM6DSM_CTRL1_ADDR 0x10 +#define LSM6DSM_XL_ODR_MASK 0xf0 -#define LSM6DSM_CTRL2_ADDR 0x11 -#define LSM6DSM_CTRL3_ADDR 0x12 -#define LSM6DSM_SW_RESET 0x01 -#define LSM6DSM_IF_INC 0x04 -#define LSM6DSM_PP_OD 0x10 -#define LSM6DSM_H_L_ACTIVE 0x20 -#define LSM6DSM_BDU 0x40 -#define LSM6DSM_BOOT 0x80 +#define LSM6DSM_CTRL2_ADDR 0x11 +#define LSM6DSM_CTRL3_ADDR 0x12 +#define LSM6DSM_SW_RESET 0x01 +#define LSM6DSM_IF_INC 0x04 +#define LSM6DSM_PP_OD 0x10 +#define LSM6DSM_H_L_ACTIVE 0x20 +#define LSM6DSM_BDU 0x40 +#define LSM6DSM_BOOT 0x80 -#define LSM6DSM_CTRL4_ADDR 0x13 -#define LSM6DSM_INT2_ON_INT1_MASK 0x20 +#define LSM6DSM_CTRL4_ADDR 0x13 +#define LSM6DSM_INT2_ON_INT1_MASK 0x20 -#define LSM6DSM_CTRL6_ADDR 0x15 -#define LSM6DSM_CTRL7_ADDR 0x16 +#define LSM6DSM_CTRL6_ADDR 0x15 +#define LSM6DSM_CTRL7_ADDR 0x16 -#define LSM6DSM_CTRL10_ADDR 0x19 -#define LSM6DSM_FUNC_EN_MASK 0x04 -#define LSM6DSM_SIG_MOT_MASK 0x01 -#define LSM6DSM_EMBED_FUNC_EN 0x04 -#define LSM6DSM_SIG_MOT_EN 0x01 +#define LSM6DSM_CTRL10_ADDR 0x19 +#define LSM6DSM_FUNC_EN_MASK 0x04 +#define LSM6DSM_SIG_MOT_MASK 0x01 +#define LSM6DSM_EMBED_FUNC_EN 0x04 +#define LSM6DSM_SIG_MOT_EN 0x01 /* Controller mode configuration register */ -#define LSM6DSM_CONTROLLER_CFG_ADDR 0x1a -#define LSM6DSM_PASSTROUGH_MASK 0x1f -#define LSM6DSM_EXT_TRIGGER_EN 0x10 -#define LSM6DSM_PULLUP_EN 0x08 -#define LSM6DSM_I2C_PASS_THRU_MODE 0x04 -#define LSM6DSM_I2C_CONTROLLER_ON 0x01 +#define LSM6DSM_CONTROLLER_CFG_ADDR 0x1a +#define LSM6DSM_PASSTROUGH_MASK 0x1f +#define LSM6DSM_EXT_TRIGGER_EN 0x10 +#define LSM6DSM_PULLUP_EN 0x08 +#define LSM6DSM_I2C_PASS_THRU_MODE 0x04 +#define LSM6DSM_I2C_CONTROLLER_ON 0x01 -#define LSM6DSM_TAP_SRC_ADDR 0x1c -#define LSM6DSM_STAP_DETECT 0x20 -#define LSM6DSM_DTAP_DETECT 0x10 +#define LSM6DSM_TAP_SRC_ADDR 0x1c +#define LSM6DSM_STAP_DETECT 0x20 +#define LSM6DSM_DTAP_DETECT 0x10 -#define LSM6DSM_STATUS_REG 0x1e +#define LSM6DSM_STATUS_REG 0x1e -#define LSM6DSM_OUT_TEMP_L_ADDR 0x20 +#define LSM6DSM_OUT_TEMP_L_ADDR 0x20 -#define LSM6DSM_GYRO_OUT_X_L_ADDR 0x22 -#define LSM6DSM_ACCEL_OUT_X_L_ADDR 0x28 +#define LSM6DSM_GYRO_OUT_X_L_ADDR 0x22 +#define LSM6DSM_ACCEL_OUT_X_L_ADDR 0x28 -#define LSM6DSM_SENSORHUB1_REG 0x2e +#define LSM6DSM_SENSORHUB1_REG 0x2e -#define LSM6DSM_FIFO_STS1_ADDR 0x3a -#define LSM6DSM_FIFO_STS2_ADDR 0x3b -#define LSM6DSM_FIFO_DIFF_MASK 0x0fff -#define LSM6DSM_FIFO_EMPTY 0x1000 -#define LSM6DSM_FIFO_FULL 0x2000 -#define LSM6DSM_FIFO_DATA_OVR 0x4000 -#define LSM6DSM_FIFO_WATERMARK 0x8000 -#define LSM6DSM_FIFO_NODECIM 0x01 +#define LSM6DSM_FIFO_STS1_ADDR 0x3a +#define LSM6DSM_FIFO_STS2_ADDR 0x3b +#define LSM6DSM_FIFO_DIFF_MASK 0x0fff +#define LSM6DSM_FIFO_EMPTY 0x1000 +#define LSM6DSM_FIFO_FULL 0x2000 +#define LSM6DSM_FIFO_DATA_OVR 0x4000 +#define LSM6DSM_FIFO_WATERMARK 0x8000 +#define LSM6DSM_FIFO_NODECIM 0x01 /* Out data register */ -#define LSM6DSM_FIFO_DATA_ADDR 0x3e +#define LSM6DSM_FIFO_DATA_ADDR 0x3e /* Registers value for supported FIFO mode */ -#define LSM6DSM_FIFO_MODE_BYPASS_VAL 0x00 -#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL 0x06 +#define LSM6DSM_FIFO_MODE_BYPASS_VAL 0x00 +#define LSM6DSM_FIFO_MODE_CONTINUOUS_VAL 0x06 -#define LSM6DSM_FUNC_SRC1_ADDR 0x53 -#define LSM6DSM_SENSORHUB_END_OP 0x01 -#define LSM6DSM_SIGN_MOTION_IA 0x40 +#define LSM6DSM_FUNC_SRC1_ADDR 0x53 +#define LSM6DSM_SENSORHUB_END_OP 0x01 +#define LSM6DSM_SIGN_MOTION_IA 0x40 -#define LSM6DSM_LIR_ADDR 0x58 -#define LSM6DSM_LIR_MASK 0x01 -#define LSM6DSM_EN_INT 0x80 -#define LSM6DSM_EN_TAP 0x0e -#define LSM6DSM_TAP_MASK 0x8e +#define LSM6DSM_LIR_ADDR 0x58 +#define LSM6DSM_LIR_MASK 0x01 +#define LSM6DSM_EN_INT 0x80 +#define LSM6DSM_EN_TAP 0x0e +#define LSM6DSM_TAP_MASK 0x8e -#define LSM6DSM_TAP_THS_6D 0x59 -#define LSM6DSM_D4D_EN_MASK 0x80 -#define LSM6DSM_TAP_TH_MASK 0x1f +#define LSM6DSM_TAP_THS_6D 0x59 +#define LSM6DSM_D4D_EN_MASK 0x80 +#define LSM6DSM_TAP_TH_MASK 0x1f -#define LSM6DSM_INT_DUR2_ADDR 0x5a -#define LSM6DSM_TAP_DUR_MASK 0xf0 -#define LSM6DSM_TAP_QUIET_MASK 0x0c +#define LSM6DSM_INT_DUR2_ADDR 0x5a +#define LSM6DSM_TAP_DUR_MASK 0xf0 +#define LSM6DSM_TAP_QUIET_MASK 0x0c -#define LSM6DSM_WUP_THS_ADDR 0x5b -#define LSM6DSM_S_D_TAP_MASK 0x80 -#define LSM6DSM_STAP_EN 0 -#define LSM6DSM_DTAP_EN 1 +#define LSM6DSM_WUP_THS_ADDR 0x5b +#define LSM6DSM_S_D_TAP_MASK 0x80 +#define LSM6DSM_STAP_EN 0 +#define LSM6DSM_DTAP_EN 1 -#define LSM6DSM_MD1_CFG_ADDR 0x5e -#define LSM6DSM_INT1_STAP 0x40 -#define LSM6DSM_INT1_DTAP 0x08 +#define LSM6DSM_MD1_CFG_ADDR 0x5e +#define LSM6DSM_INT1_STAP 0x40 +#define LSM6DSM_INT1_DTAP 0x08 /* Register values for Sensor Hub Slave 0 / Bank A */ -#define LSM6DSM_SLV0_ADD_ADDR 0x02 -#define LSM6DSM_SLV0_ADDR_SHFT 1 -#define LSM6DSM_SLV0_ADDR_MASK 0xfe -#define LSM6DSM_SLV0_RD_BIT 0x01 +#define LSM6DSM_SLV0_ADD_ADDR 0x02 +#define LSM6DSM_SLV0_ADDR_SHFT 1 +#define LSM6DSM_SLV0_ADDR_MASK 0xfe +#define LSM6DSM_SLV0_RD_BIT 0x01 -#define LSM6DSM_SLV0_SUBADD_ADDR 0x03 +#define LSM6DSM_SLV0_SUBADD_ADDR 0x03 -#define LSM6DSM_SLV0_CONFIG_ADDR 0x04 -#define LSM6DSM_SLV0_SLV_RATE_SHFT 6 -#define LSM6DSM_SLV0_SLV_RATE_MASK 0xc0 -#define LSM6DSM_SLV0_AUX_SENS_SHFT 4 -#define LSM6DSM_SLV0_AUX_SENS_MASK 0x30 -#define LSM6DSM_SLV0_NUM_OPS_MASK 0x07 +#define LSM6DSM_SLV0_CONFIG_ADDR 0x04 +#define LSM6DSM_SLV0_SLV_RATE_SHFT 6 +#define LSM6DSM_SLV0_SLV_RATE_MASK 0xc0 +#define LSM6DSM_SLV0_AUX_SENS_SHFT 4 +#define LSM6DSM_SLV0_AUX_SENS_MASK 0x30 +#define LSM6DSM_SLV0_NUM_OPS_MASK 0x07 -#define LSM6DSM_SLV1_CONFIG_ADDR 0x07 -#define LSM6DSM_SLV0_WR_ONCE_MASK 0x20 +#define LSM6DSM_SLV1_CONFIG_ADDR 0x07 +#define LSM6DSM_SLV0_WR_ONCE_MASK 0x20 #define LSM6DSM_DATA_WRITE_SUB_SLV0_ADDR 0x0e @@ -188,9 +186,9 @@ enum dev_fifo { }; #ifdef CONFIG_LSM6DSM_SEC_I2C -#define FIFO_DEV_NUM (FIFO_DEV_MAG + 1) +#define FIFO_DEV_NUM (FIFO_DEV_MAG + 1) #else -#define FIFO_DEV_NUM (FIFO_DEV_ACCEL + 1) +#define FIFO_DEV_NUM (FIFO_DEV_ACCEL + 1) #endif struct fstatus { @@ -199,7 +197,7 @@ struct fstatus { }; /* Absolute maximum rate for acc and gyro sensors */ -#define LSM6DSM_ODR_MIN_VAL 13000 +#define LSM6DSM_ODR_MIN_VAL 13000 #define LSM6DSM_ODR_MAX_VAL \ MOTION_MAX_SENSOR_FREQUENCY(416000, LSM6DSM_ODR_MIN_VAL) @@ -210,31 +208,30 @@ struct fstatus { #define LSM6DSM_REG_TO_ODR(_reg) (LSM6DSM_ODR_MIN_VAL << (_reg - 1)) /* Full Scale range value and gain for Acc */ -#define LSM6DSM_FS_LIST_NUM 4 +#define LSM6DSM_FS_LIST_NUM 4 -#define LSM6DSM_ACCEL_FS_ADDR 0x10 -#define LSM6DSM_ACCEL_FS_MASK 0x0c +#define LSM6DSM_ACCEL_FS_ADDR 0x10 +#define LSM6DSM_ACCEL_FS_MASK 0x0c -#define LSM6DSM_ACCEL_FS_2G_VAL 0x00 -#define LSM6DSM_ACCEL_FS_4G_VAL 0x02 -#define LSM6DSM_ACCEL_FS_8G_VAL 0x03 -#define LSM6DSM_ACCEL_FS_16G_VAL 0x01 +#define LSM6DSM_ACCEL_FS_2G_VAL 0x00 +#define LSM6DSM_ACCEL_FS_4G_VAL 0x02 +#define LSM6DSM_ACCEL_FS_8G_VAL 0x03 +#define LSM6DSM_ACCEL_FS_16G_VAL 0x01 -#define LSM6DSM_ACCEL_FS_MAX_VAL 16 +#define LSM6DSM_ACCEL_FS_MAX_VAL 16 /* Accel Reg value from Full Scale */ -#define LSM6DSM_ACCEL_FS_REG(_fs) \ - (_fs == 2 ? LSM6DSM_ACCEL_FS_2G_VAL : \ - _fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \ - __fls(_fs)) +#define LSM6DSM_ACCEL_FS_REG(_fs) \ + (_fs == 2 ? LSM6DSM_ACCEL_FS_2G_VAL : \ + _fs == 16 ? LSM6DSM_ACCEL_FS_16G_VAL : \ + __fls(_fs)) /* Accel normalized FS value from Full Scale */ #define LSM6DSM_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs)) /* Full Scale range value and gain for Gyro */ -#define LSM6DSM_GYRO_FS_ADDR 0x11 -#define LSM6DSM_GYRO_FS_MASK 0x0c - +#define LSM6DSM_GYRO_FS_ADDR 0x11 +#define LSM6DSM_GYRO_FS_MASK 0x0c /* Supported gyroscope ranges: * name(dps) | register | gain(udps/LSB) | actual value(dps) @@ -255,8 +252,8 @@ struct fstatus { ((LSM6DSM_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000) /* FS register address/mask for Acc/Gyro sensors */ -#define LSM6DSM_RANGE_REG(_sensor) (LSM6DSM_ACCEL_FS_ADDR + (_sensor)) -#define LSM6DSM_RANGE_MASK 0x0c +#define LSM6DSM_RANGE_REG(_sensor) (LSM6DSM_ACCEL_FS_ADDR + (_sensor)) +#define LSM6DSM_RANGE_MASK 0x0c /* Status register bitmask for Acc/Gyro data ready */ enum lsm6dsm_status { @@ -265,11 +262,11 @@ enum lsm6dsm_status { LSM6DSM_STS_GDA_UP = 0x02 }; -#define LSM6DSM_STS_XLDA_MASK 0x01 -#define LSM6DSM_STS_GDA_MASK 0x02 +#define LSM6DSM_STS_XLDA_MASK 0x01 +#define LSM6DSM_STS_GDA_MASK 0x02 /* Sensor resolution in number of bits: fixed 16 bit */ -#define LSM6DSM_RESOLUTION 16 +#define LSM6DSM_RESOLUTION 16 extern const struct accelgyro_drv lsm6dsm_drv; @@ -347,24 +344,24 @@ struct lsm6dsm_data { #if defined(CONFIG_LSM6DSM_SEC_I2C) && defined(CONFIG_MAG_CALIBRATE) union { #ifdef CONFIG_MAG_LSM6DSM_BMM150 - struct bmm150_private_data compass; + struct bmm150_private_data compass; #endif #ifdef CONFIG_MAG_LSM6DSM_LIS2MDL - struct lis2mdl_private_data compass; + struct lis2mdl_private_data compass; #endif - struct mag_cal_t cal; + struct mag_cal_t cal; }; -#endif /* CONFIG_MAG_CALIBRATE */ +#endif /* CONFIG_MAG_CALIBRATE */ }; #ifdef CONFIG_ACCEL_FIFO -#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state) {})) +#define LSM6DSM_ACCEL_FIFO_STATE (&((struct lsm6dsm_accel_fifo_state){})) #else #define LSM6DSM_ACCEL_FIFO_STATE NULL #endif -#define LSM6DSM_DATA \ - ((struct lsm6dsm_data) { \ +#define LSM6DSM_DATA \ + ((struct lsm6dsm_data){ \ .accel_fifo_state = LSM6DSM_ACCEL_FIFO_STATE, \ }) @@ -389,5 +386,4 @@ struct lsm6dsm_data { int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd); - #endif /* __CROS_EC_ACCELGYRO_LSM6DSM_H */ -- cgit v1.2.1 From e8db08d2d7f09ca4e1d1013b7721b91035886caa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:04 -0600 Subject: util/misc_util.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01c5013d8be986c69ec065c62626b577c7bec0b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730653 Reviewed-by: Jeremy Bettis --- util/misc_util.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/util/misc_util.h b/util/misc_util.h index 240d735556..52c5842105 100644 --- a/util/misc_util.h +++ b/util/misc_util.h @@ -7,8 +7,14 @@ #define __UTIL_MISC_UTIL_H /* Don't use a macro where an inline will do... */ -static inline int MIN(int a, int b) { return a < b ? a : b; } -static inline int MAX(int a, int b) { return a > b ? a : b; } +static inline int MIN(int a, int b) +{ + return a < b ? a : b; +} +static inline int MAX(int a, int b) +{ + return a > b ? a : b; +} /** * Write a buffer to the file. -- cgit v1.2.1 From 7f4ab49140aeeda5adf20dac2d80a626dccbd6b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:26 -0600 Subject: board/mithrax/charger_isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95b2e48d3b834b176696949e56c1e42813eb16e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728457 Reviewed-by: Jeremy Bettis --- board/mithrax/charger_isl9241.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/mithrax/charger_isl9241.c b/board/mithrax/charger_isl9241.c index 10bc45b333..4168bad2fd 100644 --- a/board/mithrax/charger_isl9241.c +++ b/board/mithrax/charger_isl9241.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -85,7 +84,6 @@ __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { charge_ma = (charge_ma * 90) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 6768d08a6964b710cc8d05eba20ba1b3cacbc528 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:32 -0600 Subject: driver/tcpm/ccgxxf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14b6ee1c63e6db64b38190911e7c432f90b084cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730089 Reviewed-by: Jeremy Bettis --- driver/tcpm/ccgxxf.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h index 246a231d04..c20a6b18a6 100644 --- a/driver/tcpm/ccgxxf.h +++ b/driver/tcpm/ccgxxf.h @@ -10,15 +10,15 @@ #ifndef __CROS_EC_DRIVER_TCPM_CCGXXF_H #define __CROS_EC_DRIVER_TCPM_CCGXXF_H -#define CCGXXF_I2C_ADDR1_FLAGS 0x0B -#define CCGXXF_I2C_ADDR2_FLAGS 0x1B +#define CCGXXF_I2C_ADDR1_FLAGS 0x0B +#define CCGXXF_I2C_ADDR2_FLAGS 0x1B /* SBU FET control register */ -#define CCGXXF_REG_SBU_MUX_CTL 0xBB +#define CCGXXF_REG_SBU_MUX_CTL 0xBB /* F/W info register */ -#define CCGXXF_REG_FW_VERSION 0x94 -#define CCGXXF_REG_FW_VERSION_BUILD 0x96 +#define CCGXXF_REG_FW_VERSION 0x94 +#define CCGXXF_REG_FW_VERSION_BUILD 0x96 extern const struct tcpm_drv ccgxxf_tcpm_drv; @@ -45,13 +45,13 @@ enum ccgxxf_io_pins { CCGXXF_IO_7 }; -#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80) -#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84) +#define CCGXXF_REG_GPIO_CONTROL(port) ((port) + 0x80) +#define CCGXXF_REG_GPIO_STATUS(port) ((port) + 0x84) -#define CCGXXF_REG_GPIO_MODE 0x88 -#define CCGXXF_GPIO_PIN_MASK_SHIFT 8 -#define CCGXXF_GPIO_PIN_MODE_SHIFT 2 -#define CCGXXF_GPIO_1P8V_SEL BIT(7) +#define CCGXXF_REG_GPIO_MODE 0x88 +#define CCGXXF_GPIO_PIN_MASK_SHIFT 8 +#define CCGXXF_GPIO_PIN_MODE_SHIFT 2 +#define CCGXXF_GPIO_1P8V_SEL BIT(7) enum ccgxxf_gpio_mode { CCGXXF_GPIO_MODE_HIZ_ANALOG, -- cgit v1.2.1 From f3db35cfa7870be3b437001e3940ba1aa848cbb7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:24 -0600 Subject: board/foob/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iabfdf2dcec5983265338644eaddfb3d86339300d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728378 Reviewed-by: Jeremy Bettis --- board/foob/led.c | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/board/foob/led.c b/board/foob/led.c index bb7764dadd..fa5287a7aa 100644 --- a/board/foob/led.c +++ b/board/foob/led.c @@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From e08250c862c28ce1afb639f1421c442ec34690aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:42 -0600 Subject: board/fizz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f3d998557f4c73e9dd73f8d79a179fcab7541f3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728366 Reviewed-by: Jeremy Bettis --- board/fizz/board.c | 218 +++++++++++++++++++++++++---------------------------- 1 file changed, 102 insertions(+), 116 deletions(-) diff --git a/board/fizz/board.c b/board/fizz/board.c index a397ca27e4..446afe0d84 100644 --- a/board/fizz/board.c +++ b/board/fizz/board.c @@ -50,8 +50,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint16_t board_version; static uint8_t oem; @@ -62,7 +62,7 @@ static void tcpc_alert_event(enum gpio_signal signal) schedule_deferred_pd_interrupt(0 /* port */); } -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* * ADP_IN pin state. It's initialized to 1 (=unplugged) because the IRQ won't * be triggered if BJ is the power source. @@ -125,7 +125,8 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -133,7 +134,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_FAN_PWR_EN, }; @@ -158,47 +159,37 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "eeprom", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "charger", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "pmic", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = NPCX_I2C_PORT3, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "eeprom", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "charger", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "pmic", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = NPCX_I2C_PORT3, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -221,21 +212,16 @@ static int ps8751_tune_mux(const struct usb_mux *me) return EC_SUCCESS; } -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .usb_port = 0, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, - .board_init = &ps8751_tune_mux, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .usb_port = 0, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .board_init = &ps8751_tune_mux, +} }; const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_USB1_ENABLE, - GPIO_USB2_ENABLE, - GPIO_USB3_ENABLE, - GPIO_USB4_ENABLE, - GPIO_USB5_ENABLE, + GPIO_USB1_ENABLE, GPIO_USB2_ENABLE, GPIO_USB3_ENABLE, + GPIO_USB4_ENABLE, GPIO_USB5_ENABLE, }; void board_reset_pd_mcu(void) @@ -270,9 +256,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { @@ -294,10 +280,10 @@ uint16_t tcpc_get_alert_status(void) * src/mainboard/google/${board}/acpi/dptf.asl */ const struct temp_sensor_t temp_sensors[] = { - {"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, + { "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -310,9 +296,11 @@ struct ec_thermal_config thermal_params[] = { * {Twarn, Thigh, X }, * fan_off, fan_max */ - {{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0}, - C_TO_K(4), C_TO_K(76)}, /* TMP431_Internal */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* TMP431_Sensor_1 */ + { { 0, C_TO_K(80), C_TO_K(81) }, + { 0, C_TO_K(78), 0 }, + C_TO_K(4), + C_TO_K(76) }, /* TMP431_Internal */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); @@ -521,8 +509,8 @@ static void set_charge_limit(int charge_ma) } } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int p87w = 0, p65w = 0, p60w = 0; @@ -533,7 +521,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, * is called. */ led_alert(charge_ma * charge_mv < - CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000); + CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000); /* * In terms of timing, this should always work because @@ -580,11 +568,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, } else { /* * TODO:http://crosbug.com/p/65013352. - * The current monitoring system doesn't support lower - * current. These currents are most likely not enough to - * power the system. However, if they're needed, EC can - * monitor PMON_PSYS and trigger H_PROCHOT by itself. - */ + * The current monitoring system doesn't support lower + * current. These currents are most likely not enough to + * power the system. However, if they're needed, EC can + * monitor PMON_PSYS and trigger H_PROCHOT by itself. + */ p60w = 1; CPRINTS("Current %dmA not supported", charge_ma); } @@ -602,9 +590,9 @@ int64_t get_time_dsw_pwrok(void) } const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_GREEN] = { 5, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -618,44 +606,44 @@ static const struct fan_step *fan_table; /* Note: Do not make the fan on/off point equal to 0 or 100 */ static const struct fan_step fan_table0[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 36, .off = 1, .rpm = 2800}, - {.on = 58, .off = 58, .rpm = 3200}, - {.on = 66, .off = 61, .rpm = 3400}, - {.on = 75, .off = 69, .rpm = 4200}, - {.on = 81, .off = 76, .rpm = 4800}, - {.on = 88, .off = 83, .rpm = 5200}, - {.on = 98, .off = 91, .rpm = 5600}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 36, .off = 1, .rpm = 2800 }, + { .on = 58, .off = 58, .rpm = 3200 }, + { .on = 66, .off = 61, .rpm = 3400 }, + { .on = 75, .off = 69, .rpm = 4200 }, + { .on = 81, .off = 76, .rpm = 4800 }, + { .on = 88, .off = 83, .rpm = 5200 }, + { .on = 98, .off = 91, .rpm = 5600 }, }; static const struct fan_step fan_table1[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 36, .off = 1, .rpm = 2800}, - {.on = 62, .off = 58, .rpm = 3200}, - {.on = 68, .off = 63, .rpm = 3400}, - {.on = 75, .off = 69, .rpm = 4200}, - {.on = 81, .off = 76, .rpm = 4800}, - {.on = 88, .off = 83, .rpm = 5200}, - {.on = 98, .off = 91, .rpm = 5600}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 36, .off = 1, .rpm = 2800 }, + { .on = 62, .off = 58, .rpm = 3200 }, + { .on = 68, .off = 63, .rpm = 3400 }, + { .on = 75, .off = 69, .rpm = 4200 }, + { .on = 81, .off = 76, .rpm = 4800 }, + { .on = 88, .off = 83, .rpm = 5200 }, + { .on = 98, .off = 91, .rpm = 5600 }, }; static const struct fan_step fan_table2[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 36, .off = 1, .rpm = 2200}, - {.on = 63, .off = 56, .rpm = 2900}, - {.on = 69, .off = 65, .rpm = 3000}, - {.on = 75, .off = 70, .rpm = 3300}, - {.on = 80, .off = 76, .rpm = 3600}, - {.on = 87, .off = 81, .rpm = 3900}, - {.on = 98, .off = 91, .rpm = 5000}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 36, .off = 1, .rpm = 2200 }, + { .on = 63, .off = 56, .rpm = 2900 }, + { .on = 69, .off = 65, .rpm = 3000 }, + { .on = 75, .off = 70, .rpm = 3300 }, + { .on = 80, .off = 76, .rpm = 3600 }, + { .on = 87, .off = 81, .rpm = 3900 }, + { .on = 98, .off = 91, .rpm = 5000 }, }; static const struct fan_step fan_table3[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 36, .off = 22, .rpm = 2500}, - {.on = 54, .off = 49, .rpm = 3200}, - {.on = 61, .off = 56, .rpm = 3500}, - {.on = 68, .off = 63, .rpm = 3900}, - {.on = 75, .off = 69, .rpm = 4500}, - {.on = 82, .off = 76, .rpm = 5100}, - {.on = 92, .off = 85, .rpm = 5400}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 36, .off = 22, .rpm = 2500 }, + { .on = 54, .off = 49, .rpm = 3200 }, + { .on = 61, .off = 56, .rpm = 3500 }, + { .on = 68, .off = 63, .rpm = 3900 }, + { .on = 75, .off = 69, .rpm = 4500 }, + { .on = 82, .off = 76, .rpm = 5100 }, + { .on = 92, .off = 85, .rpm = 5400 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) @@ -748,8 +736,8 @@ static void setup_bj(void) switch (oem) { case OEM_KENCH: - bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? - BJ_90W_19P5V : BJ_65W_19P5V; + bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V : + BJ_65W_19P5V; break; case OEM_TEEMO: case OEM_BLEEMO: @@ -758,15 +746,14 @@ static void setup_bj(void) case OEM_WUKONG_A: case OEM_WUKONG_M: case OEM_EXCELSIOR: - bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? - BJ_90W_19V : BJ_65W_19V; + bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19V : BJ_65W_19V; break; case OEM_JAX: bj = BJ_65W_19V; break; default: - bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? - BJ_90W_19P5V : BJ_65W_19P5V; + bj = (BJ_ADAPTER_90W_MASK & BIT(sku)) ? BJ_90W_19P5V : + BJ_65W_19P5V; break; } @@ -795,8 +782,8 @@ static void board_charge_manager_init(void) charge_manager_update_charge(j, i, NULL); } - port = gpio_get_level(GPIO_ADP_IN_L) ? - CHARGE_PORT_TYPEC0 : CHARGE_PORT_BARRELJACK; + port = gpio_get_level(GPIO_ADP_IN_L) ? CHARGE_PORT_TYPEC0 : + CHARGE_PORT_BARRELJACK; CPRINTS("Power source is p%d (%s)", port, port == CHARGE_PORT_TYPEC0 ? "USB-C" : "BJ"); @@ -855,8 +842,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); -- cgit v1.2.1 From 79d62d35c7fd381184697099d88e86ae843b957e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:46 -0600 Subject: board/kinox/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6afb493a7d72404c2d6f892678f0b36cc75af0c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728552 Reviewed-by: Jeremy Bettis --- board/kinox/board.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/kinox/board.c b/board/kinox/board.c index 0dae3b0f5e..59aaee817b 100644 --- a/board/kinox/board.c +++ b/board/kinox/board.c @@ -24,8 +24,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -99,8 +99,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { } -- cgit v1.2.1 From 2fcfdaa58325ee17ece6b2c0adfb1bce234d04c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:17 -0600 Subject: board/endeavour/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ca11944722ffcc6404b10109a155f5587fc5ca3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728292 Reviewed-by: Jeremy Bettis --- board/endeavour/board.c | 101 ++++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 54 deletions(-) diff --git a/board/endeavour/board.c b/board/endeavour/board.c index 98d805f60a..973126c569 100644 --- a/board/endeavour/board.c +++ b/board/endeavour/board.c @@ -38,8 +38,8 @@ #include "uart.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint8_t board_version; static uint32_t oem; @@ -56,14 +56,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* TODO: Verify fan control and mft */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_FAN_PWR_EN, }; @@ -80,39 +81,31 @@ const struct fan_t fans[] = { BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "pse", - .port = I2C_PORT_PSE, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "pmic", - .port = I2C_PORT_PMIC, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "pse", + .port = I2C_PORT_PSE, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "pmic", + .port = I2C_PORT_PMIC, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -131,10 +124,10 @@ const int usb_port_enable[USB_PORT_COUNT] = { * src/mainboard/google/${board}/acpi/dptf.asl */ const struct temp_sensor_t temp_sensors[] = { - {"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, + { "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -147,9 +140,11 @@ struct ec_thermal_config thermal_params[] = { * {Twarn, Thigh, X }, * fan_off, fan_max */ - {{0, C_TO_K(81), C_TO_K(82)}, {0, C_TO_K(77), 0}, - C_TO_K(19), C_TO_K(74)}, /* TMP431_Internal */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* TMP431_Sensor_1 */ + { { 0, C_TO_K(81), C_TO_K(82) }, + { 0, C_TO_K(77), 0 }, + C_TO_K(19), + C_TO_K(74) }, /* TMP431_Internal */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); @@ -318,9 +313,9 @@ int64_t get_time_dsw_pwrok(void) } const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_WHITE] = { 5, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -332,21 +327,20 @@ struct fan_step { /* Note: Do not make the fan on/off point equal to 0 or 100 */ static const struct fan_step fan_table0[] = { - {.on = 0, .off = 2, .rpm = 0}, - {.on = 11, .off = 2, .rpm = 2500}, - {.on = 38, .off = 29, .rpm = 3200}, - {.on = 65, .off = 36, .rpm = 3500}, - {.on = 76, .off = 64, .rpm = 3900}, - {.on = 84, .off = 75, .rpm = 4500}, - {.on = 91, .off = 82, .rpm = 5100}, - {.on = 98, .off = 89, .rpm = 5400}, + { .on = 0, .off = 2, .rpm = 0 }, + { .on = 11, .off = 2, .rpm = 2500 }, + { .on = 38, .off = 29, .rpm = 3200 }, + { .on = 65, .off = 36, .rpm = 3500 }, + { .on = 76, .off = 64, .rpm = 3900 }, + { .on = 84, .off = 75, .rpm = 4500 }, + { .on = 91, .off = 82, .rpm = 5100 }, + { .on = 98, .off = 89, .rpm = 5400 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) static const struct fan_step *fan_table = fan_table0; - static void cbi_init(void) { uint32_t val; @@ -403,8 +397,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); -- cgit v1.2.1 From 27925d7cfb218392407eaaad8f9eaa9ead9074e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:55 -0600 Subject: baseboard/asurada/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia60d1d948fc00e9989e2f40613db30565656486d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727855 Reviewed-by: Jeremy Bettis --- baseboard/asurada/usbc_config.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/baseboard/asurada/usbc_config.c b/baseboard/asurada/usbc_config.c index 89cb24ff12..08858489ab 100644 --- a/baseboard/asurada/usbc_config.c +++ b/baseboard/asurada/usbc_config.c @@ -37,9 +37,9 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -56,7 +56,7 @@ static void baseboard_init(void) gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); gpio_enable_interrupt(GPIO_AP_XHCI_INIT_DONE); } -DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT-1); +DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT - 1); /* Sub-board */ @@ -193,14 +193,14 @@ BUILD_ASSERT(ARRAY_SIZE(usb_port_enable) == USB_PORT_COUNT); void usb_a0_interrupt(enum gpio_signal signal) { enum usb_charge_mode mode = gpio_get_level(signal) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; for (int i = 0; i < USB_PORT_COUNT; i++) usb_charge_set_mode(i, mode, USB_ALLOW_SUSPEND_CHARGE); } -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; int reg = 0; @@ -297,8 +297,8 @@ void board_reset_pd_mcu(void) */ } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); @@ -422,9 +422,9 @@ int ppc_get_alert_status(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) - return ADC_VBUS_C0; + return ADC_VBUS_C0; if (port == 1) - return ADC_VBUS_C1; + return ADC_VBUS_C1; CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; } -- cgit v1.2.1 From 16b8c5bb1653770049003e3e78426995c63d0285 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:14 -0600 Subject: include/adc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I54a106722e86f16cfa40f005b014ee214020b01c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730200 Reviewed-by: Jeremy Bettis --- include/adc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/adc.h b/include/adc.h index 890b6662d4..a2e7ccc882 100644 --- a/include/adc.h +++ b/include/adc.h @@ -11,7 +11,7 @@ #include "adc_chip.h" #include "common.h" -#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */ +#define ADC_READ_ERROR -1 /* Value returned by adc_read_channel() on error */ #ifdef CONFIG_ZEPHYR #include @@ -80,4 +80,4 @@ int adc_disable_watchdog(void); */ int adc_set_watchdog_delay(int delay_ms); -#endif /* __CROS_EC_ADC_H */ +#endif /* __CROS_EC_ADC_H */ -- cgit v1.2.1 From fb70591fbe4c6dd7f6c2069ad8a85e018c067cff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:43 -0600 Subject: baseboard/octopus/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8bdacbf31fdddf8bd9576beb9a8765670951e65b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727935 Reviewed-by: Jeremy Bettis --- baseboard/octopus/baseboard.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/baseboard/octopus/baseboard.c b/baseboard/octopus/baseboard.c index 4f338ab131..3c8e981bfc 100644 --- a/baseboard/octopus/baseboard.c +++ b/baseboard/octopus/baseboard.c @@ -27,8 +27,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* Keyboard scan setting */ @@ -218,9 +218,9 @@ int board_is_i2c_port_powered(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) - return ADC_VBUS_C0; + return ADC_VBUS_C0; if (port == 1) - return ADC_VBUS_C1; + return ADC_VBUS_C1; CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; } @@ -238,27 +238,26 @@ void baseboard_tcpc_init(void) */ for (int port = 0; port < board_get_usb_pd_port_count(); ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } /* Called after the cbi_init (via +2) */ DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 2); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; if (!is_valid_port && port != CHARGE_PORT_NONE) return EC_ERROR_INVAL; - if (port == CHARGE_PORT_NONE) { CPRINTSUSB("Disabling all charger ports"); /* Disable all ports. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { + for (i = 0; + (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); + i++) { /* * Do not return early if one fails otherwise we can * get into a boot loop assertion failure. @@ -282,8 +281,7 @@ int board_set_active_charge_port(int port) * Turn off the other ports' sink path FETs, before enabling the * requested charge port. */ - for (i = 0; (i < ppc_cnt) && - (i < board_get_usb_pd_port_count()); i++) { + for (i = 0; (i < ppc_cnt) && (i < board_get_usb_pd_port_count()); i++) { if (i == port) continue; @@ -300,8 +298,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Empirically, the charger seems to draw a little more current that @@ -310,9 +308,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, #if defined(CONFIG_CHARGER_BQ25710) || defined(CONFIG_CHARGER_ISL9238) charge_ma = (charge_ma * 95) / 100; #endif - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_hibernate(void) -- cgit v1.2.1 From fc2aa6d157568a3b6687585f0378e6bd3cbc30fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:15 -0600 Subject: chip/stm32/gpio-stm32h7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc076cfff7e83626c38b687aaa77cfd1e74bbcb5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729506 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-stm32h7.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/stm32/gpio-stm32h7.c b/chip/stm32/gpio-stm32h7.c index 2cb723f076..6c8378a4f0 100644 --- a/chip/stm32/gpio-stm32h7.c +++ b/chip/stm32/gpio-stm32h7.c @@ -33,7 +33,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI4); task_enable_irq(STM32_IRQ_EXTI9_5); task_enable_irq(STM32_IRQ_EXTI15_10); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From ebd0165e8f4165d4c1c6e9773ac418acdcd66f02 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:26 -0600 Subject: include/math_util.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If72343f342826d714c5df1bc2d5ecdc1e1473150 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730351 Reviewed-by: Jeremy Bettis --- include/math_util.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/include/math_util.h b/include/math_util.h index 9ee075839e..7f8c8f217e 100644 --- a/include/math_util.h +++ b/include/math_util.h @@ -40,9 +40,9 @@ typedef int64_t fp_inter_t; #define INT_TO_FP(x) ((fp_t)(x) << FP_BITS) #define FP_TO_INT(x) ((int32_t)((x) >> FP_BITS)) /* Float to fixed-point, only for compile-time constants and unit tests */ -#define FLOAT_TO_FP(x) ((fp_t)((x) * (float)(1< Date: Mon, 27 Jun 2022 15:36:09 -0600 Subject: zephyr/shim/include/temp_sensor/temp_sensor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0470240ee124a98768edc111d18cf2f8f5a15300 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730849 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/temp_sensor/temp_sensor.h | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/zephyr/shim/include/temp_sensor/temp_sensor.h b/zephyr/shim/include/temp_sensor/temp_sensor.h index 2c6eabe485..6f06ae5a44 100644 --- a/zephyr/shim/include/temp_sensor/temp_sensor.h +++ b/zephyr/shim/include/temp_sensor/temp_sensor.h @@ -15,23 +15,21 @@ #define TEMP_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_TEMP_SENSOR_ID(node_id), #define HAS_POWER_GOOD_PIN(node_id) DT_NODE_HAS_PROP(node_id, power_good_pin) || -#define ANY_INST_HAS_POWER_GOOD_PIN \ - (DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, HAS_POWER_GOOD_PIN) \ - 0) +#define ANY_INST_HAS_POWER_GOOD_PIN \ + (DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, HAS_POWER_GOOD_PIN) 0) enum temp_sensor_id { #if DT_NODE_EXISTS(DT_PATH(named_temp_sensors)) - DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), - TEMP_SENSOR_ID_WITH_COMMA) + DT_FOREACH_CHILD(DT_PATH(named_temp_sensors), TEMP_SENSOR_ID_WITH_COMMA) #endif /* named_temp_sensors */ - TEMP_SENSOR_COUNT + TEMP_SENSOR_COUNT }; #undef TEMP_SENSOR_ID_WITH_COMMA /* PCT2075 access array */ -#define ZSHIM_PCT2075_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, \ - pct2075_name) +#define ZSHIM_PCT2075_SENSOR_ID(node_id) \ + DT_STRING_UPPER_TOKEN(node_id, pct2075_name) #define PCT2075_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_PCT2075_SENSOR_ID(node_id), enum pct2075_sensor { @@ -39,14 +37,14 @@ enum pct2075_sensor { DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075, PCT2075_SENSOR_ID_WITH_COMMA) #endif - PCT2075_COUNT, + PCT2075_COUNT, }; #undef PCT2075_SENSOR_ID_WITH_COMMA /* TMP112 access array */ -#define ZSHIM_TMP112_SENSOR_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, \ - tmp112_name) +#define ZSHIM_TMP112_SENSOR_ID(node_id) \ + DT_STRING_UPPER_TOKEN(node_id, tmp112_name) #define TMP112_SENSOR_ID_WITH_COMMA(node_id) ZSHIM_TMP112_SENSOR_ID(node_id), enum tmp112_sensor { @@ -54,7 +52,7 @@ enum tmp112_sensor { DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_tmp112, TMP112_SENSOR_ID_WITH_COMMA) #endif - TMP112_COUNT, + TMP112_COUNT, }; #undef TMP112_SENSOR_ID_WITH_COMMA -- cgit v1.2.1 From 05c7e8365835b51b1a3e4a977c9b4ab2ae9e919f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:43 -0600 Subject: driver/ioexpander/pca9555.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4763a4e4c151b7576aba307c69722e3bbcd1e735 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729991 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pca9555.h | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/driver/ioexpander/pca9555.h b/driver/ioexpander/pca9555.h index 273f898821..061a6c6d81 100644 --- a/driver/ioexpander/pca9555.h +++ b/driver/ioexpander/pca9555.h @@ -10,33 +10,31 @@ #include "i2c.h" -#define PCA9555_CMD_INPUT_PORT_0 0 -#define PCA9555_CMD_INPUT_PORT_1 1 -#define PCA9555_CMD_OUTPUT_PORT_0 2 -#define PCA9555_CMD_OUTPUT_PORT_1 3 -#define PCA9555_CMD_POLARITY_INVERSION_PORT_0 4 -#define PCA9555_CMD_POLARITY_INVERSION_PORT_1 5 -#define PCA9555_CMD_CONFIGURATION_PORT_0 6 -#define PCA9555_CMD_CONFIGURATION_PORT_1 7 +#define PCA9555_CMD_INPUT_PORT_0 0 +#define PCA9555_CMD_INPUT_PORT_1 1 +#define PCA9555_CMD_OUTPUT_PORT_0 2 +#define PCA9555_CMD_OUTPUT_PORT_1 3 +#define PCA9555_CMD_POLARITY_INVERSION_PORT_0 4 +#define PCA9555_CMD_POLARITY_INVERSION_PORT_1 5 +#define PCA9555_CMD_CONFIGURATION_PORT_0 6 +#define PCA9555_CMD_CONFIGURATION_PORT_1 7 -#define PCA9555_IO_0 BIT(0) -#define PCA9555_IO_1 BIT(1) -#define PCA9555_IO_2 BIT(2) -#define PCA9555_IO_3 BIT(3) -#define PCA9555_IO_4 BIT(4) -#define PCA9555_IO_5 BIT(5) -#define PCA9555_IO_6 BIT(6) -#define PCA9555_IO_7 BIT(7) +#define PCA9555_IO_0 BIT(0) +#define PCA9555_IO_1 BIT(1) +#define PCA9555_IO_2 BIT(2) +#define PCA9555_IO_3 BIT(3) +#define PCA9555_IO_4 BIT(4) +#define PCA9555_IO_5 BIT(5) +#define PCA9555_IO_6 BIT(6) +#define PCA9555_IO_7 BIT(7) -static inline int pca9555_read(const int port, - const uint16_t i2c_addr_flags, +static inline int pca9555_read(const int port, const uint16_t i2c_addr_flags, int reg, int *data_ptr) { return i2c_read8(port, i2c_addr_flags, reg, data_ptr); } -static inline int pca9555_write(const int port, - const uint16_t i2c_addr_flags, +static inline int pca9555_write(const int port, const uint16_t i2c_addr_flags, int reg, int data) { return i2c_write8(port, i2c_addr_flags, reg, data); -- cgit v1.2.1 From 2f25689465a2f06c17fa017db25a7966ab27878b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:53 -0600 Subject: driver/charger/isl923x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01a0201d93446761c9daa816bf42a333ba0ac7b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729963 Reviewed-by: Jeremy Bettis --- driver/charger/isl923x.h | 142 +++++++++++++++++++++++------------------------ 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/driver/charger/isl923x.h b/driver/charger/isl923x.h index 0de2a32ae5..1bb1135a4b 100644 --- a/driver/charger/isl923x.h +++ b/driver/charger/isl923x.h @@ -12,29 +12,29 @@ #include "driver/charger/isl923x_public.h" /* Registers */ -#define ISL923X_REG_CHG_CURRENT 0x14 +#define ISL923X_REG_CHG_CURRENT 0x14 #define ISL923X_REG_ADAPTER_CURRENT_LIMIT1 0x3f #define ISL923X_REG_ADAPTER_CURRENT_LIMIT2 0x3b -#define ISL923X_REG_SYS_VOLTAGE_MAX 0x15 -#define ISL923X_REG_SYS_VOLTAGE_MIN 0x3e -#define ISL923X_REG_PROCHOT_AC 0x47 -#define ISL923X_REG_PROCHOT_DC 0x48 -#define ISL923X_REG_T1_T2 0x38 -#define ISL923X_REG_CONTROL0 0x39 -#define ISL923X_REG_CONTROL1 0x3c -#define ISL923X_REG_CONTROL2 0x3d -#define ISL9238_REG_CONTROL3 0x4c -#define ISL9238_REG_CONTROL4 0x4e -#define ISL9238C_REG_CONTROL6 0x37 -#define ISL923X_REG_INFO 0x3a -#define ISL9238_REG_INFO2 0x4d -#define ISL923X_REG_OTG_VOLTAGE 0x49 -#define ISL923X_REG_OTG_CURRENT 0x4a -#define ISL9238_REG_INPUT_VOLTAGE 0x4b -#define ISL923X_REG_MANUFACTURER_ID 0xfe -#define ISL923X_REG_DEVICE_ID 0xff -#define RAA489000_REG_CONTROL8 0x37 -#define RAA489000_REG_CONTROL10 0x35 +#define ISL923X_REG_SYS_VOLTAGE_MAX 0x15 +#define ISL923X_REG_SYS_VOLTAGE_MIN 0x3e +#define ISL923X_REG_PROCHOT_AC 0x47 +#define ISL923X_REG_PROCHOT_DC 0x48 +#define ISL923X_REG_T1_T2 0x38 +#define ISL923X_REG_CONTROL0 0x39 +#define ISL923X_REG_CONTROL1 0x3c +#define ISL923X_REG_CONTROL2 0x3d +#define ISL9238_REG_CONTROL3 0x4c +#define ISL9238_REG_CONTROL4 0x4e +#define ISL9238C_REG_CONTROL6 0x37 +#define ISL923X_REG_INFO 0x3a +#define ISL9238_REG_INFO2 0x4d +#define ISL923X_REG_OTG_VOLTAGE 0x49 +#define ISL923X_REG_OTG_CURRENT 0x4a +#define ISL9238_REG_INPUT_VOLTAGE 0x4b +#define ISL923X_REG_MANUFACTURER_ID 0xfe +#define ISL923X_REG_DEVICE_ID 0xff +#define RAA489000_REG_CONTROL8 0x37 +#define RAA489000_REG_CONTROL10 0x35 /* Sense resistor default values in mOhm */ #define ISL923X_DEFAULT_SENSE_RESISTOR_AC 20 @@ -48,18 +48,18 @@ #define ISL923X_T1_10000 0x00 #define ISL923X_T1_20000 0x01 #define ISL923X_T1_15000 0x02 -#define ISL923X_T1_5000 0x03 -#define ISL923X_T1_1000 0x04 -#define ISL923X_T1_500 0x05 -#define ISL923X_T1_100 0x06 -#define ISL923X_T1_0 0x07 -#define ISL923X_T2_10 (0x00 << 8) -#define ISL923X_T2_100 (0x01 << 8) -#define ISL923X_T2_500 (0x02 << 8) -#define ISL923X_T2_1000 (0x03 << 8) -#define ISL923X_T2_300 (0x04 << 8) -#define ISL923X_T2_750 (0x05 << 8) -#define ISL923X_T2_2000 (0x06 << 8) +#define ISL923X_T1_5000 0x03 +#define ISL923X_T1_1000 0x04 +#define ISL923X_T1_500 0x05 +#define ISL923X_T1_100 0x06 +#define ISL923X_T1_0 0x07 +#define ISL923X_T2_10 (0x00 << 8) +#define ISL923X_T2_100 (0x01 << 8) +#define ISL923X_T2_500 (0x02 << 8) +#define ISL923X_T2_1000 (0x03 << 8) +#define ISL923X_T2_300 (0x04 << 8) +#define ISL923X_T2_750 (0x05 << 8) +#define ISL923X_T2_2000 (0x06 << 8) #define ISL923X_T2_10000 (0x07 << 8) #define ISL9237_SYS_VOLTAGE_REG_MAX 13824 @@ -69,19 +69,19 @@ #define RAA489000_SYS_VOLTAGE_REG_MIN 64 /* PROCHOT# debounce time and duration time in micro seconds */ -#define ISL923X_PROCHOT_DURATION_10000 (0 << 6) -#define ISL923X_PROCHOT_DURATION_20000 BIT(6) -#define ISL923X_PROCHOT_DURATION_15000 (2 << 6) -#define ISL923X_PROCHOT_DURATION_5000 (3 << 6) -#define ISL923X_PROCHOT_DURATION_1000 (4 << 6) -#define ISL923X_PROCHOT_DURATION_500 (5 << 6) +#define ISL923X_PROCHOT_DURATION_10000 (0 << 6) +#define ISL923X_PROCHOT_DURATION_20000 BIT(6) +#define ISL923X_PROCHOT_DURATION_15000 (2 << 6) +#define ISL923X_PROCHOT_DURATION_5000 (3 << 6) +#define ISL923X_PROCHOT_DURATION_1000 (4 << 6) +#define ISL923X_PROCHOT_DURATION_500 (5 << 6) #define ISL923X_PROCHOT_DURATION_100000 (6 << 6) -#define ISL923X_PROCHOT_DURATION_0 (7 << 6) -#define ISL923X_PROCHOT_DURATION_MASK (7 << 6) +#define ISL923X_PROCHOT_DURATION_0 (7 << 6) +#define ISL923X_PROCHOT_DURATION_MASK (7 << 6) -#define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9) -#define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9) +#define ISL923X_PROCHOT_DEBOUNCE_10 (0 << 9) +#define ISL923X_PROCHOT_DEBOUNCE_100 BIT(9) +#define ISL923X_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_PROCHOT_DEBOUNCE_MASK (3 << 9) @@ -100,10 +100,10 @@ #define ISL923X_C0_DISABLE_VREG BIT(2) /* Control0: battery DCHOT reference for RS2 == 20mOhm */ -#define ISL923X_C0_DCHOT_6A (0 << 3) -#define ISL923X_C0_DCHOT_5A BIT(3) -#define ISL923X_C0_DCHOT_4A (2 << 3) -#define ISL923X_C0_DCHOT_3A (3 << 3) +#define ISL923X_C0_DCHOT_6A (0 << 3) +#define ISL923X_C0_DCHOT_5A BIT(3) +#define ISL923X_C0_DCHOT_4A (2 << 3) +#define ISL923X_C0_DCHOT_3A (3 << 3) #define ISL923X_C0_DCHOT_MASK (3 << 3) /* Control0: BGATE force on */ @@ -111,15 +111,15 @@ #define RAA489000_C0_EN_CHG_PUMPS_TO_100PCT BIT(6) /* Control1: general purpose comparator debounce time in micro second */ -#define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14) -#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14) -#define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14) +#define ISL923X_C1_GP_DEBOUNCE_2 (0 << 14) +#define ISL923X_C1_GP_DEBOUNCE_12 BIT(14) +#define ISL923X_C1_GP_DEBOUNCE_2000 (2 << 14) #define ISL923X_C1_GP_DEBOUNCE_5000000 (3 << 14) -#define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14) +#define ISL923X_C1_GP_DEBOUNCE_MASK (3 << 14) /* Control1: learn mode */ #define ISL923X_C1_LEARN_MODE_AUTOEXIT BIT(13) -#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12) +#define ISL923X_C1_LEARN_MODE_ENABLE BIT(12) /* Control1: OTG enable */ #define ISL923X_C1_OTG BIT(11) @@ -161,15 +161,15 @@ #define RAA489000_C1_BGATE_FORCE_OFF BIT(6) /* Control2: trickle charging current in mA */ -#define ISL923X_C2_TRICKLE_256 (0 << 14) -#define ISL923X_C2_TRICKLE_128 BIT(14) -#define ISL923X_C2_TRICKLE_64 (2 << 14) -#define ISL923X_C2_TRICKLE_512 (3 << 14) +#define ISL923X_C2_TRICKLE_256 (0 << 14) +#define ISL923X_C2_TRICKLE_128 BIT(14) +#define ISL923X_C2_TRICKLE_64 (2 << 14) +#define ISL923X_C2_TRICKLE_512 (3 << 14) #define ISL923X_C2_TRICKLE_MASK (3 << 14) /* Control2: OTGEN debounce time in ms */ #define ISL923X_C2_OTG_DEBOUNCE_1300 (0 << 13) -#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13) +#define ISL923X_C2_OTG_DEBOUNCE_150 BIT(13) #define ISL923X_C2_OTG_DEBOUNCE_MASK BIT(13) /* Control2: 2-level adapter over current */ @@ -177,14 +177,14 @@ /* Control2: adapter insertion debounce time in ms */ #define ISL923X_C2_ADAPTER_DEBOUNCE_1300 (0 << 11) -#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11) +#define ISL923X_C2_ADAPTER_DEBOUNCE_150 BIT(11) #define ISL923X_C2_ADAPTER_DEBOUNCE_MASK BIT(11) /* Control2: PROCHOT debounce time in uS */ -#define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9) -#define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9) -#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9) -#define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9) +#define ISL9238_C2_PROCHOT_DEBOUNCE_7 (0 << 9) +#define ISL9237_C2_PROCHOT_DEBOUNCE_10 (0 << 9) +#define ISL923X_C2_PROCHOT_DEBOUNCE_100 BIT(9) +#define ISL923X_C2_PROCHOT_DEBOUNCE_500 (2 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_1000 (3 << 9) #define ISL923X_C2_PROCHOT_DEBOUNCE_MASK (3 << 9) @@ -192,12 +192,12 @@ #define ISL923X_C2_PROCHOT_DURATION_10000 (0 << 6) #define ISL923X_C2_PROCHOT_DURATION_20000 BIT(6) #define ISL923X_C2_PROCHOT_DURATION_15000 (2 << 6) -#define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6) -#define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6) -#define ISL923X_C2_PROCHOT_DURATION_500 (5 << 6) -#define ISL923X_C2_PROCHOT_DURATION_100 (6 << 6) -#define ISL923X_C2_PROCHOT_DURATION_0 (7 << 6) -#define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6) +#define ISL923X_C2_PROCHOT_DURATION_5000 (3 << 6) +#define ISL923X_C2_PROCHOT_DURATION_1000 (4 << 6) +#define ISL923X_C2_PROCHOT_DURATION_500 (5 << 6) +#define ISL923X_C2_PROCHOT_DURATION_100 (6 << 6) +#define ISL923X_C2_PROCHOT_DURATION_0 (7 << 6) +#define ISL923X_C2_PROCHOT_DURATION_MASK (7 << 6) /* Control2: turn off ASGATE in OTG mode */ #define ISL923X_C2_ASGATE_OFF BIT(5) @@ -346,7 +346,7 @@ enum isl9237_fsm_state { #define I2C_ADDR_CHARGER_FLAGS ISL923X_ADDR_FLAGS -#define ISL923X_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ -#define ISL923X_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ +#define ISL923X_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ +#define ISL923X_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ #endif /* __CROS_EC_ISL923X_H */ -- cgit v1.2.1 From 602f4d939f37058f26f20d688c5ab5811e16495c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:55 -0600 Subject: common/mock/rollback_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ef563f3230e27158ca7b3c3298ebe1dc1d8e20b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729675 Reviewed-by: Jeremy Bettis --- common/mock/rollback_mock.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/mock/rollback_mock.c b/common/mock/rollback_mock.c index 2b26d9d8d7..cf38f5f985 100644 --- a/common/mock/rollback_mock.c +++ b/common/mock/rollback_mock.c @@ -23,10 +23,9 @@ struct mock_ctrl_rollback mock_ctrl_rollback = MOCK_CTRL_DEFAULT_ROLLBACK; static const uint8_t fake_rollback_secret[] = { - 0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, - 0x0d, 0xb6, 0x02, 0xa9, 0x68, 0xba, 0x2a, 0x61, - 0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09, 0x54, 0x8a, - 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14, + 0xcf, 0xe3, 0x23, 0x76, 0x35, 0x04, 0xc2, 0x0f, 0x0d, 0xb6, 0x02, + 0xa9, 0x68, 0xba, 0x2a, 0x61, 0x86, 0x2a, 0x85, 0xd1, 0xca, 0x09, + 0x54, 0x8a, 0x6b, 0xe2, 0xe3, 0x38, 0xde, 0x5d, 0x59, 0x14, }; BUILD_ASSERT(sizeof(fake_rollback_secret) == CONFIG_ROLLBACK_SECRET_SIZE); -- cgit v1.2.1 From 59fc4017960634d5c12feb5c86ede424e4401704 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:14 -0600 Subject: chip/stm32/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I07c219b436e10365018dfb7b6e0c4cdfb6fed8ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729560 Reviewed-by: Jeremy Bettis --- chip/stm32/watchdog.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/chip/stm32/watchdog.c b/chip/stm32/watchdog.c index 40dfc72059..0c7d017382 100644 --- a/chip/stm32/watchdog.c +++ b/chip/stm32/watchdog.c @@ -67,8 +67,9 @@ int watchdog_init(void) STM32_IWDG_PR = IWDG_PRESCALER & 7; /* Set the reload value of the watchdog counter */ - STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, CONFIG_WATCHDOG_PERIOD_MS * - (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); + STM32_IWDG_RLR = MIN(STM32_IWDG_RLR_MAX, + CONFIG_WATCHDOG_PERIOD_MS * + (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000); #ifdef CHIP_FAMILY_STM32L4 tickstart = get_time(); /* Wait for SR */ -- cgit v1.2.1 From c04ae0f9dd493df200666e15a8840d139c24bfe3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:30 -0600 Subject: zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4884dc211cbc8ca2c910574882ef8fcc62d082b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730913 Reviewed-by: Jeremy Bettis --- .../src/motionsense_driver/drvdata-accelgyro.h | 60 +++++++++++----------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h index 069587f90f..fd8f9d8ded 100644 --- a/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h +++ b/zephyr/shim/src/motionsense_driver/drvdata-accelgyro.h @@ -23,28 +23,27 @@ * cover-scale = <1>; * }; */ -#define ACCELGYRO_ALS_CHANNEL_SCALE(id) \ - { \ - .k_channel_scale = \ - ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)),\ - .cover_scale = \ - ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)), \ +#define ACCELGYRO_ALS_CHANNEL_SCALE(id) \ + { \ + .k_channel_scale = \ + ALS_CHANNEL_SCALE(DT_PROP(id, k_channel_scale)), \ + .cover_scale = ALS_CHANNEL_SCALE(DT_PROP(id, cover_scale)), \ } -#define ALS_CALIBRATION_CHANNEL_SCALE(id) \ +#define ALS_CALIBRATION_CHANNEL_SCALE(id) \ .als_cal.channel_scale = ACCELGYRO_ALS_CHANNEL_SCALE(id), -#define ALS_CALIBRATION_SET(id) \ - .als_cal.scale = DT_PROP(id, scale), \ - .als_cal.uscale = DT_PROP(id, uscale), \ - .als_cal.offset = DT_PROP(id, offset), \ +#define ALS_CALIBRATION_SET(id) \ + .als_cal.scale = DT_PROP(id, scale), \ + .als_cal.uscale = DT_PROP(id, uscale), \ + .als_cal.offset = DT_PROP(id, offset), \ ALS_CALIBRATION_CHANNEL_SCALE(DT_CHILD(id, als_channel_scale)) /* * compatible = "cros-ec,accelgyro-als-drv-data" * als_drv_data_t in accelgyro.h * - * e.g) The following is the example in DT for als_drv_data_t + * e.g) The following is the example in DT for als_drv_data_t * als-drv-data { * compatible = "cros-ec,accelgyro-als-drv-data"; * als-cal { @@ -59,22 +58,21 @@ * }; * }; */ -#define ACCELGYRO_ALS_DRV_DATA(id) \ - { \ - ALS_CALIBRATION_SET(DT_CHILD(id, als_cal)) \ +#define ACCELGYRO_ALS_DRV_DATA(id) \ + { \ + ALS_CALIBRATION_SET(DT_CHILD(id, als_cal)) \ } -#define RGB_CAL_RGB_SET_SCALE(id) \ - .scale = ACCELGYRO_ALS_CHANNEL_SCALE(id), +#define RGB_CAL_RGB_SET_SCALE(id) .scale = ACCELGYRO_ALS_CHANNEL_SCALE(id), -#define RGB_CAL_RGB_SET_ONE(id, suffix) \ - .rgb_cal[suffix] = { \ - .offset = DT_PROP(id, offset), \ - .coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)), \ - .coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)), \ - .coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)), \ - .coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)), \ - RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale)) \ +#define RGB_CAL_RGB_SET_ONE(id, suffix) \ + .rgb_cal[suffix] = { \ + .offset = DT_PROP(id, offset), \ + .coeff[0] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 0)), \ + .coeff[1] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 1)), \ + .coeff[2] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 2)), \ + .coeff[3] = FLOAT_TO_FP(DT_PROP_BY_IDX(id, coeff, 3)), \ + RGB_CAL_RGB_SET_SCALE(DT_CHILD(id, als_channel_scale)) \ }, /* @@ -116,12 +114,12 @@ * }; * }; */ -#define ACCELGYRO_RGB_CALIBRATION(id) \ - { \ - RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X) \ - RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y) \ - RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z) \ - .irt = INT_TO_FP(DT_PROP(id, irt)), \ +#define ACCELGYRO_RGB_CALIBRATION(id) \ + { \ + RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_x), X) \ + RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_y), Y) \ + RGB_CAL_RGB_SET_ONE(DT_CHILD(id, rgb_cal_z), Z).irt = \ + INT_TO_FP(DT_PROP(id, irt)), \ } #endif /* __ZEPHYR_SHIM_SRC_MOTIONSENSE_DRIVER_DRVDATA_ACCELGYRO_H */ -- cgit v1.2.1 From 13888e395e6ef44d2201a6f7ffbe705a7a124d82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:53 -0600 Subject: board/zinger/hardware.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23220835766cb332292284bfcf2e93f7b27fd26c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729141 Reviewed-by: Jeremy Bettis --- board/zinger/hardware.c | 54 ++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index 7e6e1f8f4c..c5542750e8 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -39,16 +39,16 @@ static void power_init(void) /* enable TIM2, TIM3, TIM14, PWR */ STM32_RCC_APB1ENR = 0x10000103; /* enable DMA, SRAM, CRC, GPA, GPB, GPF */ - STM32_RCC_AHBENR = 0x460045; + STM32_RCC_AHBENR = 0x460045; } /* GPIO setting helpers */ -#define OUT(n) (1 << ((n) * 2)) -#define AF(n) (2 << ((n) * 2)) -#define ANALOG(n) (3 << ((n) * 2)) +#define OUT(n) (1 << ((n)*2)) +#define AF(n) (2 << ((n)*2)) +#define ANALOG(n) (3 << ((n)*2)) #define HIGH(n) (1 << (n)) #define ODR(n) (1 << (n)) -#define HISPEED(n) (3 << ((n) * 2)) +#define HISPEED(n) (3 << ((n)*2)) #define AFx(n, x) (x << (((n) % 8) * 4)) static void pins_init(void) @@ -83,9 +83,9 @@ static void pins_init(void) STM32_GPIO_AFRH(GPIO_A) = AFx(9, 1) | AFx(10, 1); STM32_GPIO_OTYPER(GPIO_A) = ODR(4); STM32_GPIO_OSPEEDR(GPIO_A) = HISPEED(5) | HISPEED(6) | HISPEED(7); - STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3) - | OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9) - | AF(10) | OUT(13) | OUT(14); + STM32_GPIO_MODER(GPIO_A) = OUT(0) | ANALOG(1) | ANALOG(2) | ANALOG(3) | + OUT(4) | AF(5) /*| AF(6)*/ | AF(7) | AF(9) | + AF(10) | OUT(13) | OUT(14); /* set PF0 / PF1 as output */ STM32_GPIO_ODR(GPIO_F) = 0; STM32_GPIO_MODER(GPIO_F) = OUT(0) | OUT(1); @@ -107,7 +107,8 @@ static void adc_init(void) ; } /* Single conversion, right aligned, 12-bit */ - STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */; + STM32_ADC_CFGR1 = BIT(12); /* BIT(15) => AUTOOFF */ + ; /* clock is ADCCLK (ADEN must be off when writing this reg) */ STM32_ADC_CFGR2 = 0; /* Sampling time : 71.5 ADC clock cycles, about 5us */ @@ -132,8 +133,8 @@ static void uart_init(void) STM32_USART_BRR(UARTN_BASE) = DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE); /* UART enabled, 8 Data bits, oversampling x16, no parity */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE | + STM32_USART_CR1_RE; /* 1 stop bit, no fancy stuff */ STM32_USART_CR2(UARTN_BASE) = 0x0000; /* DMA disabled, special modes disabled, error interrupt disabled */ @@ -200,7 +201,7 @@ static int watchdog_ain_id, watchdog_ain_high, watchdog_ain_low; static int adc_enable_last_watchdog(void) { return adc_enable_watchdog(watchdog_ain_id, watchdog_ain_high, - watchdog_ain_low); + watchdog_ain_low); } static inline int adc_watchdog_enabled(void) @@ -248,8 +249,7 @@ int adc_enable_watchdog(int ch, int high, int low) /* Clear flags */ STM32_ADC_ISR = 0x8e; /* Set Watchdog enable bit on a single channel / continuous mode */ - STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) - | BIT(13) | BIT(12); + STM32_ADC_CFGR1 = (ch << 26) | BIT(23) | BIT(22) | BIT(13) | BIT(12); /* Enable watchdog interrupt */ STM32_ADC_IER = BIT(7); /* Start continuous conversion */ @@ -289,17 +289,17 @@ int adc_disable_watchdog(void) (FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP) /* Flash unlocking keys */ -#define KEY1 0x45670123 -#define KEY2 0xCDEF89AB +#define KEY1 0x45670123 +#define KEY2 0xCDEF89AB /* Lock bits for FLASH_CR register */ -#define PG BIT(0) -#define PER BIT(1) -#define OPTPG BIT(4) -#define OPTER BIT(5) -#define STRT BIT(6) -#define CR_LOCK BIT(7) -#define OPTWRE BIT(9) +#define PG BIT(0) +#define PER BIT(1) +#define OPTPG BIT(4) +#define OPTER BIT(5) +#define STRT BIT(6) +#define CR_LOCK BIT(7) +#define OPTWRE BIT(9) int crec_flash_physical_write(int offset, int size, const char *data) { @@ -369,14 +369,13 @@ int crec_flash_physical_erase(int offset, int size) STM32_FLASH_CR |= PER; for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - offset += CONFIG_FLASH_ERASE_SIZE) { + offset += CONFIG_FLASH_ERASE_SIZE) { int i; /* select page to erase */ STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; /* set STRT bit : start erase */ STM32_FLASH_CR |= STRT; - /* Wait for erase to complete */ for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP); i++) @@ -434,7 +433,6 @@ static void unlock_erase_optb(void) STM32_FLASH_CR = OPTWRE; } - static void write_optb(int byte, uint8_t value) { volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte); @@ -475,6 +473,6 @@ int flash_physical_is_permanently_protected(void) { /* if RDP is still at level 0, the flash protection is not in place */ return (STM32_FLASH_OBR & STM32_FLASH_OBR_RDP_MASK) && - /* the low 16KB (RO partition) are write-protected */ - !(STM32_FLASH_WRPR & 0xF); + /* the low 16KB (RO partition) are write-protected */ + !(STM32_FLASH_WRPR & 0xF); } -- cgit v1.2.1 From fc6b1da8bf485f435689ceace395ac0cb2762eb5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:58 -0600 Subject: include/spi_flash_reg.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieca7f0ee9dd8b4a443c177539ec656846d9e536c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730409 Reviewed-by: Jeremy Bettis --- include/spi_flash_reg.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/include/spi_flash_reg.h b/include/spi_flash_reg.h index a0ffefc721..46e8ee20d6 100644 --- a/include/spi_flash_reg.h +++ b/include/spi_flash_reg.h @@ -15,21 +15,21 @@ * Common register bits for SPI flash. All registers / bits may not be valid * for all parts. */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* SR2 register existence based upon chip */ #ifdef CONFIG_SPI_FLASH_W25X40 @@ -70,4 +70,4 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start, int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, uint8_t *sr2); -#endif /* __CROS_EC_SPI_FLASH_REG_H */ +#endif /* __CROS_EC_SPI_FLASH_REG_H */ -- cgit v1.2.1 From 42847f58cce656ad71437c29ac0836bf4a9c0425 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:56 -0600 Subject: zephyr/emul/emul_common_i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8bb05162f4856f08555b4ac62cac01d971b57940 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730689 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_common_i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/emul/emul_common_i2c.c b/zephyr/emul/emul_common_i2c.c index ae603f924a..01353310a2 100644 --- a/zephyr/emul/emul_common_i2c.c +++ b/zephyr/emul/emul_common_i2c.c @@ -357,8 +357,8 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs, } } - data->msg_state = read ? I2C_COMMON_EMUL_IN_READ - : I2C_COMMON_EMUL_IN_WRITE; + data->msg_state = read ? I2C_COMMON_EMUL_IN_READ : + I2C_COMMON_EMUL_IN_WRITE; if (stop) { data->msg_state = I2C_COMMON_EMUL_NONE_MSG; @@ -395,8 +395,8 @@ int i2c_common_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs, } else { /* Dispatch read command */ for (i = 0; i < msgs->len; i++, data->msg_byte++) { - ret = i2c_common_emul_read_byte(emul, data, - &(msgs->buf[i])); + ret = i2c_common_emul_read_byte( + emul, data, &(msgs->buf[i])); if (ret) { return ret; } -- cgit v1.2.1 From 1f6d89ef48e4bf78983535c6041bb3143a1fed82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:10 -0600 Subject: chip/stm32/clock-stm32g4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If45ac6561e63e564b694bd3d4f18f27833b9f696 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729465 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32g4.c | 54 +++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c index b0bf56d85f..a46946e22b 100644 --- a/chip/stm32/clock-stm32g4.c +++ b/chip/stm32/clock-stm32g4.c @@ -21,14 +21,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) -#define MHZ(x) ((x) * 1000000) -#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) +#define MHZ(x) ((x)*1000000) +#define WAIT_STATE_FREQ_STEP_HZ MHZ(20) /* PLL configuration constants */ -#define STM32G4_SYSCLK_MAX_HZ MHZ(170) -#define STM32G4_HSI_CLK_HZ MHZ(16) -#define STM32G4_PLL_IN_FREQ_HZ MHZ(4) +#define STM32G4_SYSCLK_MAX_HZ MHZ(170) +#define STM32G4_HSI_CLK_HZ MHZ(16) +#define STM32G4_PLL_IN_FREQ_HZ MHZ(4) #define STM32G4_PLL_R 2 #define STM32G4_AHB_PRE 1 #define STM32G4_APB1_PRE 1 @@ -42,7 +42,7 @@ enum rcc_clksrc { }; static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, - uint32_t pll_clk_in_hz) + uint32_t pll_clk_in_hz) { /* * The pll output frequency (Fhclkc) is determined by: @@ -81,20 +81,16 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, ASSERT(pll_m && (pll_m <= 16)); ASSERT((pll_n >= 8) && (pll_n <= 127)); - hclk_freq = pll_clk_in_hz * pll_n / (pll_m * - STM32G4_PLL_R * STM32G4_AHB_PRE); + hclk_freq = pll_clk_in_hz * pll_n / + (pll_m * STM32G4_PLL_R * STM32G4_AHB_PRE); /* Ensure that there aren't any integer rounding errors */ ASSERT(hclk_freq == hclk_hz); /* Program PLL config register */ - STM32_RCC_PLLCFGR = PLLCFGR_PLLP(0) | - PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) | - PLLCFGR_PLLR_EN | - PLLCFGR_PLLQ(0) | - PLLCFGR_PLLQ_EN | - PLLCFGR_PLLN(pll_n) | - PLLCFGR_PLLM(pll_m - 1) | - pll_src; + STM32_RCC_PLLCFGR = + PLLCFGR_PLLP(0) | PLLCFGR_PLLR(STM32G4_PLL_R / 2 - 1) | + PLLCFGR_PLLR_EN | PLLCFGR_PLLQ(0) | PLLCFGR_PLLQ_EN | + PLLCFGR_PLLN(pll_n) | PLLCFGR_PLLM(pll_m - 1) | pll_src; /* Wait until PLL is locked */ wait_for_ready(&(STM32_RCC_CR), STM32_RCC_CR_PLLON, @@ -116,8 +112,8 @@ static void stm32g4_config_pll(uint32_t hclk_hz, uint32_t pll_src, static void stm32g4_config_low_speed_clock(void) { /* Ensure that LSI is ON */ - wait_for_ready(&(STM32_RCC_CSR), - STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY); + wait_for_ready(&(STM32_RCC_CSR), STM32_RCC_CSR_LSION, + STM32_RCC_CSR_LSIRDY); /* Setup RTC Clock input */ STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; @@ -163,10 +159,10 @@ void stm32g4_set_flash_ws(uint32_t freq_hz) * found in Table 9 of RM0440 - STM32G4 technical reference manual. A * table lookup is not required though as WS = HCLK (MHz) / 20 */ - ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; + ws = freq_hz / WAIT_STATE_FREQ_STEP_HZ; /* Enable data and instruction cache */ STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN | - STM32_FLASH_ACR_PRFTEN | ws; + STM32_FLASH_ACR_PRFTEN | ws; } void clock_init(void) @@ -255,16 +251,14 @@ void clock_enable_module(enum module_id module, int enable) } else if (module == MODULE_I2C) { if (enable) { /* Enable clocks to I2C modules if necessary */ - STM32_RCC_APB1ENR1 |= - STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN; + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_I2C1EN | + STM32_RCC_APB1ENR1_I2C2EN | + STM32_RCC_APB1ENR1_I2C3EN; STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_I2C4EN; } else { - STM32_RCC_APB1ENR1 &= - ~(STM32_RCC_APB1ENR1_I2C1EN | - STM32_RCC_APB1ENR1_I2C2EN | - STM32_RCC_APB1ENR1_I2C3EN); + STM32_RCC_APB1ENR1 &= ~(STM32_RCC_APB1ENR1_I2C1EN | + STM32_RCC_APB1ENR1_I2C2EN | + STM32_RCC_APB1ENR1_I2C3EN); STM32_RCC_APB1ENR2 &= ~STM32_RCC_APB1ENR2_I2C4EN; } } else if (module == MODULE_ADC) { @@ -274,7 +268,7 @@ void clock_enable_module(enum module_id module, int enable) STM32_RCC_APB2ENR_ADC345EN); else STM32_RCC_AHB2ENR &= ~(STM32_RCC_AHB2ENR_ADC12EN | - STM32_RCC_APB2ENR_ADC345EN); + STM32_RCC_APB2ENR_ADC345EN); } else { CPRINTS("stm32g4: enable clock module %d not supported", module); -- cgit v1.2.1 From a83bad821356636eb65b8c1416fcd7873c15fcc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:16 -0600 Subject: board/lantis/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I703107392de6dfdce6241758b5ea86f04ad1e682 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728616 Reviewed-by: Jeremy Bettis --- board/lantis/led.c | 54 ++++++++++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/board/lantis/led.c b/board/lantis/led.c index 632f91e118..f593197d72 100644 --- a/board/lantis/led.c +++ b/board/lantis/led.c @@ -19,11 +19,9 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -31,22 +29,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LEFT_PORT = 0, - RIGHT_PORT -}; +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; static int led_set_color_battery(int port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_BAT_LED_AMBER_C1 : - GPIO_BAT_LED_AMBER_C0); + GPIO_BAT_LED_AMBER_C0); white_led = (port == RIGHT_PORT ? GPIO_BAT_LED_WHITE_C1 : - GPIO_BAT_LED_WHITE_C0); + GPIO_BAT_LED_WHITE_C0); switch (color) { case LED_OFF: @@ -144,7 +139,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) static bool is_led_old_policy(void) { if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_ABSENT && - get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) + get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) return 1; else return 0; @@ -160,10 +155,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -181,14 +176,15 @@ static void led_set_battery(void) */ if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; led_set_color_battery(RIGHT_PORT, power_ticks & 0x2 ? - LED_WHITE : LED_OFF); + LED_WHITE : + LED_OFF); led_set_color_battery(LEFT_PORT, power_ticks & 0x2 ? - LED_WHITE : LED_OFF); + LED_WHITE : + LED_OFF); return; } } @@ -212,22 +208,25 @@ static void led_set_battery(void) */ if (charge_get_percent() < 10) { if (is_led_old_policy()) { - led_set_color_battery( - RIGHT_PORT, (battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + led_set_color_battery(RIGHT_PORT, + (battery_ticks & 0x2) ? + LED_WHITE : + LED_OFF); } else { if (led_auto_control_is_enabled( - EC_LED_ID_RIGHT_LED)) + EC_LED_ID_RIGHT_LED)) led_set_color_battery( RIGHT_PORT, (battery_ticks & 0x2) ? - LED_AMBER : LED_OFF); + LED_AMBER : + LED_OFF); if (led_auto_control_is_enabled( - EC_LED_ID_LEFT_LED)) + EC_LED_ID_LEFT_LED)) led_set_color_battery( LEFT_PORT, (battery_ticks & 0x2) ? - LED_AMBER : LED_OFF); + LED_AMBER : + LED_OFF); } } else { set_active_port_color(LED_OFF); @@ -266,8 +265,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 7889857cfa90de65f54c53451dd7f7bf3d666f59 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:35 -0600 Subject: core/cortex-m/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3007abd5c6bec9caadd8e09fd9bde60d73b8d54e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729817 Reviewed-by: Jeremy Bettis --- core/cortex-m/cpu.h | 131 ++++++++++++++++++++++++++-------------------------- 1 file changed, 65 insertions(+), 66 deletions(-) diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index e3137cd864..c7645ac20d 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -12,66 +12,66 @@ #include "compile_time_macros.h" /* Macro to access 32-bit registers */ -#define CPUREG(addr) (*(volatile uint32_t*)(addr)) +#define CPUREG(addr) (*(volatile uint32_t *)(addr)) -#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) -#define ST_ENABLE BIT(0) -#define ST_TICKINT BIT(1) -#define ST_CLKSOURCE BIT(2) -#define ST_COUNTFLAG BIT(16) +#define CPU_NVIC_ST_CTRL CPUREG(0xE000E010) +#define ST_ENABLE BIT(0) +#define ST_TICKINT BIT(1) +#define ST_CLKSOURCE BIT(2) +#define ST_COUNTFLAG BIT(16) /* Nested Vectored Interrupt Controller */ -#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) -#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) -#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +#define CPU_NVIC_EN(x) CPUREG(0xe000e100 + 4 * (x)) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180 + 4 * (x)) +#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280 + 4 * (x)) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* SCB AIRCR : Application interrupt and reset control register */ -#define CPU_NVIC_APINT CPUREG(0xe000ed0c) -#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ -#define CPU_NVIC_APINT_PRIOGRP (BIT(8)|BIT(9)|BIT(10)) -#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ -#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) -#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_PRIOGRP (BIT(8) | BIT(9) | BIT(10)) +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0xFA05U << 16) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* NVIC STIR : Software Trigger Interrupt Register */ -#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) +#define CPU_NVIC_SWTRIG CPUREG(0xe000ef00) /* SCB SCR : System Control Register */ -#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) -#define CPU_NVIC_CCR CPUREG(0xe000ed14) -#define CPU_NVIC_SHCSR CPUREG(0xe000ed24) -#define CPU_NVIC_CFSR CPUREG(0xe000ed28) -#define CPU_NVIC_HFSR CPUREG(0xe000ed2c) -#define CPU_NVIC_DFSR CPUREG(0xe000ed30) -#define CPU_NVIC_MFAR CPUREG(0xe000ed34) -#define CPU_NVIC_BFAR CPUREG(0xe000ed38) +#define CPU_NVIC_CCR CPUREG(0xe000ed14) +#define CPU_NVIC_SHCSR CPUREG(0xe000ed24) +#define CPU_NVIC_CFSR CPUREG(0xe000ed28) +#define CPU_NVIC_HFSR CPUREG(0xe000ed2c) +#define CPU_NVIC_DFSR CPUREG(0xe000ed30) +#define CPU_NVIC_MFAR CPUREG(0xe000ed34) +#define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_CFSR_BFARVALID = BIT(15), - CPU_NVIC_CFSR_MFARVALID = BIT(7), + CPU_NVIC_CFSR_BFARVALID = BIT(15), + CPU_NVIC_CFSR_MFARVALID = BIT(7), - CPU_NVIC_CCR_ICACHE = BIT(17), - CPU_NVIC_CCR_DCACHE = BIT(16), - CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), - CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), + CPU_NVIC_CCR_ICACHE = BIT(17), + CPU_NVIC_CCR_DCACHE = BIT(16), + CPU_NVIC_CCR_DIV_0_TRAP = BIT(4), + CPU_NVIC_CCR_UNALIGN_TRAP = BIT(3), - CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, - CPU_NVIC_HFSR_FORCED = BIT(30), - CPU_NVIC_HFSR_VECTTBL = BIT(1), + CPU_NVIC_HFSR_DEBUGEVT = 1UL << 31, + CPU_NVIC_HFSR_FORCED = BIT(30), + CPU_NVIC_HFSR_VECTTBL = BIT(1), - CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), - CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), - CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), + CPU_NVIC_SHCSR_MEMFAULTENA = BIT(16), + CPU_NVIC_SHCSR_BUSFAULTENA = BIT(17), + CPU_NVIC_SHCSR_USGFAULTENA = BIT(18), }; /* System Control Block: cache registers */ -#define CPU_SCB_CCSIDR CPUREG(0xe000ed80) -#define CPU_SCB_CCSELR CPUREG(0xe000ed84) -#define CPU_SCB_ICIALLU CPUREG(0xe000ef50) -#define CPU_SCB_DCISW CPUREG(0xe000ef60) -#define CPU_SCB_DCCISW CPUREG(0xe000ef74) +#define CPU_SCB_CCSIDR CPUREG(0xe000ed80) +#define CPU_SCB_CCSELR CPUREG(0xe000ed84) +#define CPU_SCB_ICIALLU CPUREG(0xe000ef50) +#define CPU_SCB_DCISW CPUREG(0xe000ef60) +#define CPU_SCB_DCCISW CPUREG(0xe000ef74) /* Floating Point Context Address Register */ -#define CPU_FPU_FPCAR CPUREG(0xe000ef38) +#define CPU_FPU_FPCAR CPUREG(0xe000ef38) /* * As defined by Armv7-M Reference Manual B1.5.7 "Context state stacking on @@ -85,28 +85,29 @@ enum { #define FPU_FPSCR_UFC BIT(3) /* Underflow */ #define FPU_FPSCR_IXC BIT(4) /* Inexact */ #define FPU_FPSCR_IDC BIT(7) /* Input denormal */ -#define FPU_FPSCR_EXC_FLAGS (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | \ - FPU_FPSCR_UFC | FPU_FPSCR_IXC | FPU_FPSCR_IDC) +#define FPU_FPSCR_EXC_FLAGS \ + (FPU_FPSCR_IOC | FPU_FPSCR_DZC | FPU_FPSCR_OFC | FPU_FPSCR_UFC | \ + FPU_FPSCR_IXC | FPU_FPSCR_IDC) /* Bitfield values for EXC_RETURN. */ -#define EXC_RETURN_ES_MASK BIT(0) +#define EXC_RETURN_ES_MASK BIT(0) #define EXC_RETURN_ES_NON_SECURE 0 -#define EXC_RETURN_ES_SECURE BIT(0) -#define EXC_RETURN_SPSEL_MASK BIT(2) -#define EXC_RETURN_SPSEL_MSP 0 -#define EXC_RETURN_SPSEL_PSP BIT(2) -#define EXC_RETURN_MODE_MASK BIT(3) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD BIT(3) -#define EXC_RETURN_FTYPE_MASK BIT(4) -#define EXC_RETURN_FTYPE_ON 0 -#define EXC_RETURN_FTYPE_OFF BIT(4) -#define EXC_RETURN_DCRS_MASK BIT(5) -#define EXC_RETURN_DCRS_OFF 0 -#define EXC_RETURN_DCRS_ON BIT(5) -#define EXC_RETURN_S_MASK BIT(6) -#define EXC_RETURN_S_NON_SECURE 0 -#define EXC_RETURN_S_SECURE BIT(6) +#define EXC_RETURN_ES_SECURE BIT(0) +#define EXC_RETURN_SPSEL_MASK BIT(2) +#define EXC_RETURN_SPSEL_MSP 0 +#define EXC_RETURN_SPSEL_PSP BIT(2) +#define EXC_RETURN_MODE_MASK BIT(3) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD BIT(3) +#define EXC_RETURN_FTYPE_MASK BIT(4) +#define EXC_RETURN_FTYPE_ON 0 +#define EXC_RETURN_FTYPE_OFF BIT(4) +#define EXC_RETURN_DCRS_MASK BIT(5) +#define EXC_RETURN_DCRS_OFF 0 +#define EXC_RETURN_DCRS_ON BIT(5) +#define EXC_RETURN_S_MASK BIT(6) +#define EXC_RETURN_S_NON_SECURE 0 +#define EXC_RETURN_S_SECURE BIT(6) /* Set up the cpu to detect faults */ void cpu_init(void); @@ -132,10 +133,8 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) if (priority > 7) priority = 7; - CPU_NVIC_PRI(irq / 4) = - (CPU_NVIC_PRI(irq / 4) & - ~(7 << prio_shift)) | - (priority << prio_shift); + CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(7 << prio_shift)) | + (priority << prio_shift); } #endif /* __CROS_EC_CPU_H */ -- cgit v1.2.1 From 07355c337201fb108ff8e103e0b4a6f5bcdb8e64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:29 -0600 Subject: chip/stm32/dfu_bootmanager_shared.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d038575ef7bb9c1144caaae5af2afede06310bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729491 Reviewed-by: Jeremy Bettis --- chip/stm32/dfu_bootmanager_shared.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/stm32/dfu_bootmanager_shared.h b/chip/stm32/dfu_bootmanager_shared.h index 4003583ee2..de35ac1ab1 100644 --- a/chip/stm32/dfu_bootmanager_shared.h +++ b/chip/stm32/dfu_bootmanager_shared.h @@ -15,12 +15,12 @@ #include "common.h" /* Registers to validate the backup memory region. */ -#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF -#define DFU_BOOTMANAGER_VALID_MASK 0xFF00 -#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00 +#define DFU_BOOTMANAGER_VALUE_MASK 0x00FF +#define DFU_BOOTMANAGER_VALID_MASK 0xFF00 +#define DFU_BOOTMANAGER_VALID_CHECK 0xAA00 -#define DFU_BOOTMANAGER_VALUE_CLEAR 0 -#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX +#define DFU_BOOTMANAGER_VALUE_CLEAR 0 +#define DFU_BOOTMANAGER_VALUE_DFU UINT8_MAX /* * Reset and enter the DFU mode. -- cgit v1.2.1 From ac73b842b0f563577791d0c3ad15cb8cd2017cbe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:46:04 -0600 Subject: board/meep/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3e450c09c9bd7fff33d59f8d28d6287e274371a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728658 Reviewed-by: Jeremy Bettis --- board/meep/board.c | 110 +++++++++++++++++++++++++---------------------------- 1 file changed, 52 insertions(+), 58 deletions(-) diff --git a/board/meep/board.c b/board/meep/board.c index 3771c72072..e20ca0987a 100644 --- a/board/meep/board.c +++ b/board/meep/board.c @@ -42,13 +42,13 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 #ifdef CONFIG_KEYBOARD_KEYPAD #error "KSO_14 was repurposed to PPC_ID pin so CONFIG_KEYBOARD_KEYPAD \ @@ -86,32 +86,32 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */ - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -121,17 +121,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t lid_standrd_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standrd_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct kionix_accel_data kx022_data; @@ -228,9 +224,9 @@ int board_is_convertible(void) * Vortininja: 49, 50, 51, 52 * Unprovisioned: 255 */ - return sku_id == 1 || sku_id == 2 || sku_id == 3 || - sku_id == 4 || sku_id == 49 || sku_id == 50 || - sku_id == 51 || sku_id == 52 || sku_id == 255; + return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 || + sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 || + sku_id == 255; } static void board_update_sensor_config_from_sku(void) @@ -306,8 +302,8 @@ void board_hibernate_late(void) const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) @@ -336,15 +332,15 @@ __override void lid_angle_peripheral_enable(int enable) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif void board_overcurrent_event(int port, int is_overcurrented) @@ -389,31 +385,29 @@ __override uint16_t board_get_ps8xxx_product_id(int port) } static const struct ppc_config_t ppc_syv682x_port0 = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static const struct ppc_config_t ppc_syv682x_port1 = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static void board_setup_ppc(void) { if (c0_port_ppc == PPC_SYV682X) { - memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], - &ppc_syv682x_port0, - sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0, + sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH); } if (c1_port_ppc == PPC_SYV682X) { - memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], - &ppc_syv682x_port1, - sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1, + sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH); } -- cgit v1.2.1 From 765da0b8984e0290bfa79705cdfc6962e72c70b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:00 -0600 Subject: zephyr/test/drivers/src/uart_hostcmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieda76a3e912cc5600d116cc64b25f4308cd403b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730980 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/uart_hostcmd.c | 48 +++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/zephyr/test/drivers/src/uart_hostcmd.c b/zephyr/test/drivers/src/uart_hostcmd.c index 0e68c440ce..d599e76985 100644 --- a/zephyr/test/drivers/src/uart_hostcmd.c +++ b/zephyr/test/drivers/src/uart_hostcmd.c @@ -86,8 +86,8 @@ static void test_uart_hc_read_next(int ver) */ msg1_start = response + read_args.response_size - 1 - MSG_LEN(msg1); zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1), - "expected \"%s\", got \"%.*s\"", - msg1, MSG_LEN(msg1), msg1_start); + "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1), + msg1_start); /* Set new snapshot which should include message 2 */ zassert_equal(EC_RES_SUCCESS, host_command_process(&snap_args), NULL); @@ -106,11 +106,11 @@ static void test_uart_hc_read_next(int ver) msg2_start = response + read_args.response_size - 1 - MSG_LEN(msg2); msg1_start = msg2_start - MSG_LEN(msg1); zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2), - "expected \"%s\", got \"%.*s\"", - msg2, MSG_LEN(msg2), msg2_start); + "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2), + msg2_start); zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1), - "expected \"%s\", got \"%.*s\"", - msg1, MSG_LEN(msg1), msg1_start); + "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1), + msg1_start); /* Append third message */ cputs(CC_COMMAND, msg3); @@ -135,14 +135,14 @@ static void test_uart_hc_read_next(int ver) msg2_start = msg3_start - MSG_LEN(msg2); msg1_start = msg2_start - MSG_LEN(msg1); zassert_mem_equal(msg3, msg3_start, MSG_LEN(msg3), - "expected \"%s\", got \"%.*s\"", - msg3, MSG_LEN(msg3), msg3_start); + "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3), + msg3_start); zassert_mem_equal(msg2, msg2_start, MSG_LEN(msg2), - "expected \"%s\", got \"%.*s\"", - msg2, MSG_LEN(msg2), msg2_start); + "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2), + msg2_start); zassert_mem_equal(msg1, msg1_start, MSG_LEN(msg1), - "expected \"%s\", got \"%.*s\"", - msg1, MSG_LEN(msg1), msg1_start); + "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1), + msg1_start); } ZTEST_USER(uart_hostcmd, test_uart_hc_read_next_v0) @@ -176,11 +176,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1) response[read_args.response_size]); /* Account additional NULL char at the end */ zassert_equal(MSG_LEN(msg1) + 1, read_args.response_size, - "expected message length %d, got %d", - MSG_LEN(msg1) + 1, read_args.response_size); + "expected message length %d, got %d", MSG_LEN(msg1) + 1, + read_args.response_size); zassert_mem_equal(msg1, response, MSG_LEN(msg1), - "expected \"%s\", got \"%.*s\"", - msg1, MSG_LEN(msg1), response); + "expected \"%s\", got \"%.*s\"", msg1, MSG_LEN(msg1), + response); /* Set new snapshot after second message */ zassert_equal(EC_RES_SUCCESS, host_command_process(&snap_args), NULL); @@ -193,11 +193,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1) response[read_args.response_size]); /* Account additional NULL char at the end */ zassert_equal(MSG_LEN(msg2) + 1, read_args.response_size, - "expected message length %d, got %d", - MSG_LEN(msg2) + 1, read_args.response_size); + "expected message length %d, got %d", MSG_LEN(msg2) + 1, + read_args.response_size); zassert_mem_equal(msg2, response, MSG_LEN(msg2), - "expected \"%s\", got \"%.*s\"", - msg2, MSG_LEN(msg2), response); + "expected \"%s\", got \"%.*s\"", msg2, MSG_LEN(msg2), + response); /* Append third message */ cputs(CC_COMMAND, msg3); @@ -220,11 +220,11 @@ ZTEST_USER(uart_hostcmd, test_uart_hc_read_recent_v1) response[read_args.response_size]); /* Account additional NULL char at the end */ zassert_equal(MSG_LEN(msg3) + 1, read_args.response_size, - "expected message length %d, got %d", - MSG_LEN(msg3) + 1, read_args.response_size); + "expected message length %d, got %d", MSG_LEN(msg3) + 1, + read_args.response_size); zassert_mem_equal(msg3, response, MSG_LEN(msg3), - "expected \"%s\", got \"%.*s\"", - msg3, MSG_LEN(msg3), response); + "expected \"%s\", got \"%.*s\"", msg3, MSG_LEN(msg3), + response); } ZTEST_SUITE(uart_hostcmd, drivers_predicate_post_main, NULL, -- cgit v1.2.1 From bd7fccdcabf38eb300c2b7a2e229bb8a7d8d7e89 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:43 -0600 Subject: board/osiris/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0cd9d4146d646712aba1208cb96fd12deadc7bbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728794 Reviewed-by: Jeremy Bettis --- board/osiris/board.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/osiris/board.c b/board/osiris/board.c index 8d20de1550..1439a96714 100644 --- a/board/osiris/board.c +++ b/board/osiris/board.c @@ -27,8 +27,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) @@ -66,15 +66,14 @@ __override void board_kblight_init(void) * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 1c4281e7c53bf1c99d390732159d4025251a97ef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:54 -0600 Subject: board/drawcia_riscv/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4ed6f7fcbffbf7e8dec01a14452d6ec68f7a5726 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728243 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/drawcia_riscv/usb_pd_policy.c b/board/drawcia_riscv/usb_pd_policy.c index 3ff7152541..6c3370ca2f 100644 --- a/board/drawcia_riscv/usb_pd_policy.c +++ b/board/drawcia_riscv/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 9d22d62bcef92617a8e0b26b0d97eaa20189de0a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:36 -0600 Subject: common/i2c_peripheral.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf5f68b993e69badab20014eb11847a350cec0fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729637 Reviewed-by: Jeremy Bettis --- common/i2c_peripheral.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/i2c_peripheral.c b/common/i2c_peripheral.c index ebc7167f8d..545ad5b53c 100644 --- a/common/i2c_peripheral.c +++ b/common/i2c_peripheral.c @@ -29,6 +29,5 @@ static enum ec_status i2c_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - i2c_get_protocol_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, i2c_get_protocol_info, EC_VER_MASK(0)); -- cgit v1.2.1 From 56225a6758af61c814f45d89ec96911873aa164a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:01 -0600 Subject: board/reef_mchp/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ceee1579ee6d8ba44bc2d1e059969bdac6fa51c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728894 Reviewed-by: Jeremy Bettis --- board/reef_mchp/usb_pd_policy.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/board/reef_mchp/usb_pd_policy.c b/board/reef_mchp/usb_pd_policy.c index 90f44f8580..efe97c9bd7 100644 --- a/board/reef_mchp/usb_pd_policy.c +++ b/board/reef_mchp/usb_pd_policy.c @@ -25,12 +25,12 @@ #include "tfdp_chip.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -41,7 +41,8 @@ static void board_vbus_update_source_current(int port) { enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); /* * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance -- cgit v1.2.1 From 53c71261806f06b8368b0d6dfdfce4d1582f9340 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:39 -0600 Subject: board/kingoftown/hibernate.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib17700c69f907b7237bb7d39b2a1f94945f3b9e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728550 Reviewed-by: Jeremy Bettis --- board/kingoftown/hibernate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/board/kingoftown/hibernate.c b/board/kingoftown/hibernate.c index 504a295463..e32f56db83 100644 --- a/board/kingoftown/hibernate.c +++ b/board/kingoftown/hibernate.c @@ -11,8 +11,6 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_LID_ACCEL_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } -- cgit v1.2.1 From 5c0ce2129cb05e89c5897ff2b4489ab15740fd69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:32 -0600 Subject: util/gen_touchpad_hash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife30fe948c27fc9c4ee51914077a145761cce74f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730624 Reviewed-by: Jeremy Bettis --- util/gen_touchpad_hash.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/util/gen_touchpad_hash.c b/util/gen_touchpad_hash.c index e03c4638f3..3b2eb4cb07 100644 --- a/util/gen_touchpad_hash.c +++ b/util/gen_touchpad_hash.c @@ -35,7 +35,7 @@ static int hash_fw_blank(FILE *hashes) CONFIG_TOUCHPAD_VIRTUAL_SIZE / CONFIG_UPDATE_PDU_SIZE, SHA256_DIGEST_LENGTH); for (len = 0; len < CONFIG_TOUCHPAD_VIRTUAL_SIZE; - len += CONFIG_UPDATE_PDU_SIZE) { + len += CONFIG_UPDATE_PDU_SIZE) { print_hex(hashes, digest, sizeof(digest), 0); } fputs("};\n", hashes); @@ -93,7 +93,7 @@ static int hash_fw(FILE *tp_fw, FILE *hashes) if (len != CONFIG_TOUCHPAD_VIRTUAL_SIZE) { warnx("Incorrect TP FW size (%d vs %d)", len, - CONFIG_TOUCHPAD_VIRTUAL_SIZE); + CONFIG_TOUCHPAD_VIRTUAL_SIZE); return 1; } @@ -109,16 +109,14 @@ int main(int argc, char **argv) FILE *tp_fw = NULL; FILE *hashes; const char short_opt[] = "f:ho:"; - const struct option long_opts[] = { - { "firmware", 1, NULL, 'f' }, - { "help", 0, NULL, 'h' }, - { "out", 1, NULL, 'o' }, - { NULL } - }; + const struct option long_opts[] = { { "firmware", 1, NULL, 'f' }, + { "help", 0, NULL, 'h' }, + { "out", 1, NULL, 'o' }, + { NULL } }; const char usage[] = "USAGE: %s -f -o \n"; - while ((nopt = getopt_long(argc, argv, short_opt, - long_opts, NULL)) != -1) { + while ((nopt = getopt_long(argc, argv, short_opt, long_opts, NULL)) != + -1) { switch (nopt) { case 'f': /* -f or --firmware */ tp_fw_name = optarg; -- cgit v1.2.1 From a1be4f86a2340f9996e3ff302660282809a27f88 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:20 -0600 Subject: board/anahera/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3d78e06f47fc276205aeec3fb1ddbce67caf6384 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727103 Reviewed-by: Jeremy Bettis --- board/anahera/board.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/anahera/board.c b/board/anahera/board.c index b7110951ce..f1da042cc7 100644 --- a/board/anahera/board.c +++ b/board/anahera/board.c @@ -28,8 +28,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -66,14 +66,13 @@ enum battery_present battery_hw_present(void) } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Limit the input current to 95% negotiated limit, * to account for the charger chip margin. */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 284d38b662d6f1c7ed32e209e9a0999e3b8df307 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:19 -0600 Subject: chip/mchp/spi_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I74ce59cd89bff9e65d7fa2562711aeb4fd479ee4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729301 Reviewed-by: Jeremy Bettis --- chip/mchp/spi_chip.h | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/chip/mchp/spi_chip.h b/chip/mchp/spi_chip.h index 167a9cdf4a..24ac524478 100644 --- a/chip/mchp/spi_chip.h +++ b/chip/mchp/spi_chip.h @@ -19,28 +19,27 @@ /* struct spi_device_t */ #include "spi.h" -#define SPI_DMA_OPTION_RD 0 -#define SPI_DMA_OPTION_WR 1 +#define SPI_DMA_OPTION_RD 0 +#define SPI_DMA_OPTION_WR 1 /* * bits[3:0] = controller instance * bits[7:4] = controller family * 0 = QMSPI, 1 = GPSPI */ -#define QMSPI0_PORT 0x00 -#define GPSPI0_PORT 0x10 -#define GPSPI1_PORT 0x11 +#define QMSPI0_PORT 0x00 +#define GPSPI0_PORT 0x10 +#define GPSPI1_PORT 0x11 +#define QMSPI_CLASS0 0 +#define GPSPI_CLASS0 1 -#define QMSPI_CLASS0 0 -#define GPSPI_CLASS0 1 +#define QMSPI_CLASS (0 << 4) +#define GPSPI_CLASS BIT(4) -#define QMSPI_CLASS (0 << 4) -#define GPSPI_CLASS BIT(4) - -#define QMSPI_CTRL0 0 -#define GPSPI_CTRL0 0 -#define GPSPI_CTRL1 1 +#define QMSPI_CTRL0 0 +#define GPSPI_CTRL0 0 +#define GPSPI_CTRL1 1 /* * Encode zero based controller class and instance values @@ -51,8 +50,7 @@ /* * helper to return pointer to QMSPI or GPSPI struct dma_option */ -const void *spi_dma_option(const struct spi_device_t *spi_device, - int is_tx); +const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx); #endif /* #ifndef _QMSPI_CHIP_H */ /** @} -- cgit v1.2.1 From cac8bae7fd202aa692fc5f348f875968a5215d2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:47 -0600 Subject: driver/retimer/ps8818.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92cad74dd9981b55b83ce6f468c676e6f5a54bf1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730058 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8818.c | 94 ++++++++++++++++++------------------------------- 1 file changed, 34 insertions(+), 60 deletions(-) diff --git a/driver/retimer/ps8818.c b/driver/retimer/ps8818.c index 2f8e353099..26945a3874 100644 --- a/driver/retimer/ps8818.c +++ b/driver/retimer/ps8818.c @@ -20,15 +20,12 @@ int ps8818_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8818_DEBUG) ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, *data); + me->usb_port, me->i2c_addr_flags + page, offset, + *data); return rv; } @@ -39,26 +36,19 @@ int ps8818_i2c_write(const struct usb_mux *me, int page, int offset, int data) int pre_val, post_val; if (PS8818_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8818_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) " - "0x%02X=>0x%02X\n", - __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + "0x%02X=>0x%02X\n", + __func__, me->usb_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; @@ -71,28 +61,20 @@ int ps8818_i2c_field_update8(const struct usb_mux *me, int page, int offset, int pre_val, post_val; if (PS8818_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8818_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) " "0x%02X=>0x%02X\n", - __func__, - me->usb_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->usb_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; @@ -108,16 +90,16 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, *ack_required = false; if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; if (PS8818_DEBUG) - ccprintf("%s(%d, 0x%02X) %s %s %s\n", - __func__, me->usb_port, mux_state, - (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", - (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", - (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? "FLIP" : ""); + ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port, + mux_state, + (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", + (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", + (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" : + ""); /* Set the mode */ if (mux_state & USB_PD_MUX_USB_ENABLED) @@ -125,11 +107,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) val |= PS8818_MODE_DP_ENABLE; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_MODE, - PS8818_MODE_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_MODE, + PS8818_MODE_NON_RESERVED_MASK, val); if (rv) return rv; @@ -138,11 +117,8 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_POLARITY_INVERTED) val |= PS8818_FLIP_CONFIG; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_FLIP, - PS8818_FLIP_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, PS8818_REG0_FLIP, + PS8818_FLIP_NON_RESERVED_MASK, val); if (rv) return rv; @@ -151,11 +127,9 @@ static int ps8818_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) val |= PS8818_DPHPD_PLUGGED; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE0, - PS8818_REG0_DPHPD_CONFIG, - PS8818_DPHPD_NON_RESERVED_MASK, - val); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE0, + PS8818_REG0_DPHPD_CONFIG, + PS8818_DPHPD_NON_RESERVED_MASK, val); return rv; } -- cgit v1.2.1 From 65b78f9d91c738771d21a3992d6c9ea81e68da7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:02 -0600 Subject: driver/accel_kxcj9.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46f4e213a90583cfb28b33a42834f8f8fbc43898 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729907 Reviewed-by: Jeremy Bettis --- driver/accel_kxcj9.h | 178 +++++++++++++++++++++++++-------------------------- 1 file changed, 89 insertions(+), 89 deletions(-) diff --git a/driver/accel_kxcj9.h b/driver/accel_kxcj9.h index f7488317f0..9a3479ef32 100644 --- a/driver/accel_kxcj9.h +++ b/driver/accel_kxcj9.h @@ -14,98 +14,98 @@ * 7-bit address is 000111Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define KXCJ9_ADDR0_FLAGS 0x0E -#define KXCJ9_ADDR1_FLAGS 0x0D -#define KXCJ9_WHO_AM_I_VAL 0x0A +#define KXCJ9_ADDR0_FLAGS 0x0E +#define KXCJ9_ADDR1_FLAGS 0x0D +#define KXCJ9_WHO_AM_I_VAL 0x0A /* Chip-specific registers */ -#define KXCJ9_XOUT_L 0x06 -#define KXCJ9_XOUT_H 0x07 -#define KXCJ9_YOUT_L 0x08 -#define KXCJ9_YOUT_H 0x09 -#define KXCJ9_ZOUT_L 0x0a -#define KXCJ9_ZOUT_H 0x0b -#define KXCJ9_DCST_RESP 0x0c -#define KXCJ9_WHOAMI 0x0f -#define KXCJ9_INT_SRC1 0x16 -#define KXCJ9_INT_SRC2 0x17 -#define KXCJ9_STATUS 0x18 -#define KXCJ9_INT_REL 0x1a -#define KXCJ9_CTRL1 0x1b -#define KXCJ9_CTRL2 0x1d -#define KXCJ9_INT_CTRL1 0x1e -#define KXCJ9_INT_CTRL2 0x1f -#define KXCJ9_DATA_CTRL 0x21 -#define KXCJ9_WAKEUP_TIMER 0x29 -#define KXCJ9_SELF_TEST 0x3a -#define KXCJ9_WAKEUP_THRESHOLD 0x6a - -#define KXCJ9_INT_SRC1_WUFS BIT(1) -#define KXCJ9_INT_SRC1_DRDY BIT(4) - -#define KXCJ9_INT_SRC2_ZPWU BIT(0) -#define KXCJ9_INT_SRC2_ZNWU BIT(1) -#define KXCJ9_INT_SRC2_YPWU BIT(2) -#define KXCJ9_INT_SRC2_YNWU BIT(3) -#define KXCJ9_INT_SRC2_XPWU BIT(4) -#define KXCJ9_INT_SRC2_XNWU BIT(5) - -#define KXCJ9_STATUS_INT BIT(4) - -#define KXCJ9_CTRL1_WUFE BIT(1) -#define KXCJ9_CTRL1_DRDYE BIT(5) -#define KXCJ9_CTRL1_PC1 BIT(7) - -#define KXCJ9_GSEL_2G (0 << 3) -#define KXCJ9_GSEL_4G BIT(3) -#define KXCJ9_GSEL_8G (2 << 3) -#define KXCJ9_GSEL_8G_14BIT (3 << 3) -#define KXCJ9_GSEL_ALL (3 << 3) - -#define KXCJ9_RES_8BIT (0 << 6) -#define KXCJ9_RES_12BIT BIT(6) - -#define KXCJ9_CTRL2_OWUF (7 << 0) -#define KXCJ9_CTRL2_DCST BIT(4) -#define KXCJ9_CTRL2_SRST BIT(7) - -#define KXCJ9_OWUF_0_781HZ 0 -#define KXCJ9_OWUF_1_563HZ 1 -#define KXCJ9_OWUF_3_125HZ 2 -#define KXCJ9_OWUF_6_250HZ 3 -#define KXCJ9_OWUF_12_50HZ 4 -#define KXCJ9_OWUF_25_00HZ 5 -#define KXCJ9_OWUF_50_00HZ 6 -#define KXCJ9_OWUF_100_0HZ 7 - -#define KXCJ9_INT_CTRL1_IEL BIT(3) -#define KXCJ9_INT_CTRL1_IEA BIT(4) -#define KXCJ9_INT_CTRL1_IEN BIT(5) - -#define KXCJ9_INT_CTRL2_ZPWUE BIT(0) -#define KXCJ9_INT_CTRL2_ZNWUE BIT(1) -#define KXCJ9_INT_CTRL2_YPWUE BIT(2) -#define KXCJ9_INT_CTRL2_YNWUE BIT(3) -#define KXCJ9_INT_CTRL2_XPWUE BIT(4) -#define KXCJ9_INT_CTRL2_XNWUE BIT(5) - -#define KXCJ9_OSA_0_000HZ 0 -#define KXCJ9_OSA_0_781HZ 8 -#define KXCJ9_OSA_1_563HZ 9 -#define KXCJ9_OSA_3_125HZ 0xa -#define KXCJ9_OSA_6_250HZ 0xb -#define KXCJ9_OSA_12_50HZ 0 -#define KXCJ9_OSA_25_00HZ 1 -#define KXCJ9_OSA_50_00HZ 2 -#define KXCJ9_OSA_100_0HZ 3 -#define KXCJ9_OSA_200_0HZ 4 -#define KXCJ9_OSA_400_0HZ 5 -#define KXCJ9_OSA_800_0HZ 6 -#define KXCJ9_OSA_1600_HZ 7 -#define KXCJ9_OSA_FIELD 0xf +#define KXCJ9_XOUT_L 0x06 +#define KXCJ9_XOUT_H 0x07 +#define KXCJ9_YOUT_L 0x08 +#define KXCJ9_YOUT_H 0x09 +#define KXCJ9_ZOUT_L 0x0a +#define KXCJ9_ZOUT_H 0x0b +#define KXCJ9_DCST_RESP 0x0c +#define KXCJ9_WHOAMI 0x0f +#define KXCJ9_INT_SRC1 0x16 +#define KXCJ9_INT_SRC2 0x17 +#define KXCJ9_STATUS 0x18 +#define KXCJ9_INT_REL 0x1a +#define KXCJ9_CTRL1 0x1b +#define KXCJ9_CTRL2 0x1d +#define KXCJ9_INT_CTRL1 0x1e +#define KXCJ9_INT_CTRL2 0x1f +#define KXCJ9_DATA_CTRL 0x21 +#define KXCJ9_WAKEUP_TIMER 0x29 +#define KXCJ9_SELF_TEST 0x3a +#define KXCJ9_WAKEUP_THRESHOLD 0x6a + +#define KXCJ9_INT_SRC1_WUFS BIT(1) +#define KXCJ9_INT_SRC1_DRDY BIT(4) + +#define KXCJ9_INT_SRC2_ZPWU BIT(0) +#define KXCJ9_INT_SRC2_ZNWU BIT(1) +#define KXCJ9_INT_SRC2_YPWU BIT(2) +#define KXCJ9_INT_SRC2_YNWU BIT(3) +#define KXCJ9_INT_SRC2_XPWU BIT(4) +#define KXCJ9_INT_SRC2_XNWU BIT(5) + +#define KXCJ9_STATUS_INT BIT(4) + +#define KXCJ9_CTRL1_WUFE BIT(1) +#define KXCJ9_CTRL1_DRDYE BIT(5) +#define KXCJ9_CTRL1_PC1 BIT(7) + +#define KXCJ9_GSEL_2G (0 << 3) +#define KXCJ9_GSEL_4G BIT(3) +#define KXCJ9_GSEL_8G (2 << 3) +#define KXCJ9_GSEL_8G_14BIT (3 << 3) +#define KXCJ9_GSEL_ALL (3 << 3) + +#define KXCJ9_RES_8BIT (0 << 6) +#define KXCJ9_RES_12BIT BIT(6) + +#define KXCJ9_CTRL2_OWUF (7 << 0) +#define KXCJ9_CTRL2_DCST BIT(4) +#define KXCJ9_CTRL2_SRST BIT(7) + +#define KXCJ9_OWUF_0_781HZ 0 +#define KXCJ9_OWUF_1_563HZ 1 +#define KXCJ9_OWUF_3_125HZ 2 +#define KXCJ9_OWUF_6_250HZ 3 +#define KXCJ9_OWUF_12_50HZ 4 +#define KXCJ9_OWUF_25_00HZ 5 +#define KXCJ9_OWUF_50_00HZ 6 +#define KXCJ9_OWUF_100_0HZ 7 + +#define KXCJ9_INT_CTRL1_IEL BIT(3) +#define KXCJ9_INT_CTRL1_IEA BIT(4) +#define KXCJ9_INT_CTRL1_IEN BIT(5) + +#define KXCJ9_INT_CTRL2_ZPWUE BIT(0) +#define KXCJ9_INT_CTRL2_ZNWUE BIT(1) +#define KXCJ9_INT_CTRL2_YPWUE BIT(2) +#define KXCJ9_INT_CTRL2_YNWUE BIT(3) +#define KXCJ9_INT_CTRL2_XPWUE BIT(4) +#define KXCJ9_INT_CTRL2_XNWUE BIT(5) + +#define KXCJ9_OSA_0_000HZ 0 +#define KXCJ9_OSA_0_781HZ 8 +#define KXCJ9_OSA_1_563HZ 9 +#define KXCJ9_OSA_3_125HZ 0xa +#define KXCJ9_OSA_6_250HZ 0xb +#define KXCJ9_OSA_12_50HZ 0 +#define KXCJ9_OSA_25_00HZ 1 +#define KXCJ9_OSA_50_00HZ 2 +#define KXCJ9_OSA_100_0HZ 3 +#define KXCJ9_OSA_200_0HZ 4 +#define KXCJ9_OSA_400_0HZ 5 +#define KXCJ9_OSA_800_0HZ 6 +#define KXCJ9_OSA_1600_HZ 7 +#define KXCJ9_OSA_FIELD 0xf /* Min and Max sampling frequency in mHz */ -#define KXCJ9_ACCEL_MIN_FREQ 12500 -#define KXCJ9_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) +#define KXCJ9_ACCEL_MIN_FREQ 12500 +#define KXCJ9_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 6250) #endif /* __CROS_EC_ACCEL_KXCJ9_H */ -- cgit v1.2.1 From b6fdc95af22290302b76a3c475b1d4bd92e0526e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:18 -0600 Subject: board/twinkie/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib5e0a0f27f05f3cf192e720a9cafb744af9dedef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729038 Reviewed-by: Jeremy Bettis --- board/twinkie/board.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/board/twinkie/board.h b/board/twinkie/board.h index 3d601ee979..4410c4c57f 100644 --- a/board/twinkie/board.h +++ b/board/twinkie/board.h @@ -54,7 +54,7 @@ /* USB configuration */ #define CONFIG_USB_PID 0x500A /* By default, enable all console messages excepted USB */ -#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USB)) +#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USB)) /* * Allow dangerous commands all the time, since we don't have a write protect @@ -79,9 +79,9 @@ void trace_packets(void); void set_trace_mode(int mode); /* Timer selection */ -#define TIM_CLOCK_MSB 3 +#define TIM_CLOCK_MSB 3 #define TIM_CLOCK_LSB 15 -#define TIM_ADC 16 +#define TIM_ADC 16 #include "gpio_signal.h" @@ -106,28 +106,28 @@ enum usb_strings { }; /* Standard-current Rp */ -#define PD_SRC_VNC PD_SRC_DEF_VNC_MV -#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV +#define PD_SRC_VNC PD_SRC_DEF_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV /* delay necessary for the voltage transition on the power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #endif /* !__ASSEMBLER__ */ /* USB interface indexes (use define rather than enum to expand them) */ #define USB_IFACE_CONSOLE 0 -#define USB_IFACE_VENDOR 1 +#define USB_IFACE_VENDOR 1 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 /* * Endpoint 2 is missing because the console used to use two bidirectional @@ -137,13 +137,13 @@ enum usb_strings { */ #ifdef HAS_TASK_SNIFFER -#define USB_EP_SNIFFER 3 -#define USB_EP_COUNT 4 -#define USB_IFACE_COUNT 2 +#define USB_EP_SNIFFER 3 +#define USB_EP_COUNT 4 +#define USB_IFACE_COUNT 2 #else -#define USB_EP_COUNT 2 +#define USB_EP_COUNT 2 /* No IFACE_VENDOR for the sniffer */ -#define USB_IFACE_COUNT 1 +#define USB_IFACE_COUNT 1 #endif #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 4fdef302c2660c018ef7ede8e58da7b65ece9c00 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:21 -0600 Subject: board/wormdingler/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3642b69bf7b13ae21600a8a64fc1ec5f74feae3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729118 Reviewed-by: Jeremy Bettis --- board/wormdingler/base_detect.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/wormdingler/base_detect.c b/board/wormdingler/base_detect.c index 87d6ab8046..5982cdde1f 100644 --- a/board/wormdingler/base_detect.c +++ b/board/wormdingler/base_detect.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Make sure POGO VBUS starts later then PP3300_HUB when power on */ #define BASE_DETECT_EN_LATER_US (600 * MSEC) @@ -95,8 +95,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -187,8 +187,7 @@ static void base_enable(void) { /* Enable base detection interrupt. */ base_detect_debounce_time = get_time().val; - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_EN_LATER_US); + hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US); gpio_enable_interrupt(GPIO_BASE_DET_L); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT); @@ -214,7 +213,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From acc11035555c1a4929e2430d96d9d3e7288f918c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:28 -0600 Subject: util/gen_ipi_table.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief6620dc5074e73f304588ad738e0f0478b9e958 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730623 Reviewed-by: Jeremy Bettis --- util/gen_ipi_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/gen_ipi_table.c b/util/gen_ipi_table.c index 07a3a39be0..07a616a290 100644 --- a/util/gen_ipi_table.c +++ b/util/gen_ipi_table.c @@ -12,7 +12,7 @@ #include "board.h" -#define FPRINTF(format, args...) fprintf(fout, format, ## args) +#define FPRINTF(format, args...) fprintf(fout, format, ##args) int main(int argc, char **argv) { -- cgit v1.2.1 From 4f3f24d7d0cb4e20aeb70ba65dc2315145394928 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:22 -0600 Subject: common/usbc/usb_pe_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49144b9f38e37bd0f592c354c90dfad3dffcf4ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729791 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pe_private.h | 82 ++++++++++++++++++++++++-------------------- 1 file changed, 45 insertions(+), 37 deletions(-) diff --git a/common/usbc/usb_pe_private.h b/common/usbc/usb_pe_private.h index e68c4c2fcd..ca2e3ab32c 100644 --- a/common/usbc/usb_pe_private.h +++ b/common/usbc/usb_pe_private.h @@ -13,76 +13,84 @@ */ enum { -/* At least one successful PD communication packet received from port partner */ + /* At least one successful PD communication packet received from port + partner */ PE_FLAGS_PD_CONNECTION_FN = 0, -/* Accept message received from port partner */ + /* Accept message received from port partner */ PE_FLAGS_ACCEPT_FN, -/* Power Supply Ready message received from port partner */ + /* Power Supply Ready message received from port partner */ PE_FLAGS_PS_READY_FN, -/* Protocol Error was determined based on error recovery current state */ + /* Protocol Error was determined based on error recovery current state + */ PE_FLAGS_PROTOCOL_ERROR_FN, -/* Set if we are in Modal Operation */ + /* Set if we are in Modal Operation */ PE_FLAGS_MODAL_OPERATION_FN, -/* A message we requested to be sent has been transmitted */ + /* A message we requested to be sent has been transmitted */ PE_FLAGS_TX_COMPLETE_FN, -/* A message sent by a port partner has been received */ + /* A message sent by a port partner has been received */ PE_FLAGS_MSG_RECEIVED_FN, -/* A hard reset has been requested but has not been sent, not currently used */ + /* A hard reset has been requested but has not been sent, not currently + used */ PE_FLAGS_HARD_RESET_PENDING_FN, -/* Port partner sent a Wait message. Wait before we resend our message */ + /* Port partner sent a Wait message. Wait before we resend our message + */ PE_FLAGS_WAIT_FN, -/* An explicit contract is in place with our port partner */ + /* An explicit contract is in place with our port partner */ PE_FLAGS_EXPLICIT_CONTRACT_FN, -/* Waiting for Sink Capabailities timed out. Used for retry error handling */ + /* Waiting for Sink Capabailities timed out. Used for retry error + handling */ PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN, -/* Power Supply voltage/current transition timed out */ + /* Power Supply voltage/current transition timed out */ PE_FLAGS_PS_TRANSITION_TIMEOUT_FN, -/* Flag to note current Atomic Message Sequence is interruptible */ + /* Flag to note current Atomic Message Sequence is interruptible */ PE_FLAGS_INTERRUPTIBLE_AMS_FN, -/* Flag to note Power Supply reset has completed */ + /* Flag to note Power Supply reset has completed */ PE_FLAGS_PS_RESET_COMPLETE_FN, -/* VCONN swap operation has completed */ + /* VCONN swap operation has completed */ PE_FLAGS_VCONN_SWAP_COMPLETE_FN, -/* Flag to note no more setup VDMs (discovery, etc.) should be sent */ + /* Flag to note no more setup VDMs (discovery, etc.) should be sent */ PE_FLAGS_VDM_SETUP_DONE_FN, -/* Flag to note PR Swap just completed for Startup entry */ + /* Flag to note PR Swap just completed for Startup entry */ PE_FLAGS_PR_SWAP_COMPLETE_FN, -/* Flag to note Port Discovery port partner replied with BUSY */ + /* Flag to note Port Discovery port partner replied with BUSY */ PE_FLAGS_VDM_REQUEST_BUSY_FN, -/* Flag to note Port Discovery port partner replied with NAK */ + /* Flag to note Port Discovery port partner replied with NAK */ PE_FLAGS_VDM_REQUEST_NAKED_FN, -/* Flag to note FRS/PRS context in shared state machine path */ + /* Flag to note FRS/PRS context in shared state machine path */ PE_FLAGS_FAST_ROLE_SWAP_PATH_FN, -/* Flag to note if FRS listening is enabled */ + /* Flag to note if FRS listening is enabled */ PE_FLAGS_FAST_ROLE_SWAP_ENABLED_FN, -/* Flag to note TCPC passed on FRS signal from port partner */ + /* Flag to note TCPC passed on FRS signal from port partner */ PE_FLAGS_FAST_ROLE_SWAP_SIGNALED_FN, -/* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */ + /* TODO: POLICY decision: Triggers a DR SWAP attempt from UFP to DFP */ PE_FLAGS_DR_SWAP_TO_DFP_FN, -/* - * TODO: POLICY decision - * Flag to trigger a message resend after receiving a WAIT from port partner - */ + /* + * TODO: POLICY decision + * Flag to trigger a message resend after receiving a WAIT from port + * partner + */ PE_FLAGS_WAITING_PR_SWAP_FN, -/* FLAG is set when an AMS is initiated locally. ie. AP requested a PR_SWAP */ + /* FLAG is set when an AMS is initiated locally. ie. AP requested a + PR_SWAP */ PE_FLAGS_LOCALLY_INITIATED_AMS_FN, -/* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY */ + /* Flag to note the first message sent in PE_SRC_READY and PE_SNK_READY + */ PE_FLAGS_FIRST_MSG_FN, -/* Flag to continue a VDM request if it was interrupted */ + /* Flag to continue a VDM request if it was interrupted */ PE_FLAGS_VDM_REQUEST_CONTINUE_FN, -/* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */ + /* TODO: POLICY decision: Triggers a Vconn SWAP attempt to on */ PE_FLAGS_VCONN_SWAP_TO_ON_FN, -/* FLAG to track that VDM request to port partner timed out */ + /* FLAG to track that VDM request to port partner timed out */ PE_FLAGS_VDM_REQUEST_TIMEOUT_FN, -/* FLAG to note message was discarded due to incoming message */ + /* FLAG to note message was discarded due to incoming message */ PE_FLAGS_MSG_DISCARDED_FN, -/* FLAG to note that hard reset can't be performed due to battery low */ + /* FLAG to note that hard reset can't be performed due to battery low */ PE_FLAGS_SNK_WAITING_BATT_FN, -/* FLAG to note that a data reset is complete */ + /* FLAG to note that a data reset is complete */ PE_FLAGS_DATA_RESET_COMPLETE_FN, -/* Waiting for SRC to SNK settle time */ + /* Waiting for SRC to SNK settle time */ PE_FLAGS_SRC_SNK_SETTLE_FN, -/* Last element */ + /* Last element */ PE_FLAGS_COUNT }; -- cgit v1.2.1 From 9edd2798f61a1ad439fef9646ab0e9e9ffd87626 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:42 -0600 Subject: driver/usb_mux/ps8743.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08363d23b3ba3ca08ace89496ab0647b9d010325 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730167 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8743.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/driver/usb_mux/ps8743.c b/driver/usb_mux/ps8743.c index 28ad5e9546..3673a10b9d 100644 --- a/driver/usb_mux/ps8743.c +++ b/driver/usb_mux/ps8743.c @@ -25,24 +25,21 @@ static enum usb_conn_status saved_usb_conn_status[CONFIG_USB_PD_PORT_MAX_COUNT]; int ps8743_read(const struct usb_mux *me, uint8_t reg, int *val) { - return i2c_read8(me->i2c_port, me->i2c_addr_flags, - reg, val); + return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } int ps8743_write(const struct usb_mux *me, uint8_t reg, uint8_t val) { - return i2c_write8(me->i2c_port, me->i2c_addr_flags, - reg, val); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } int ps8743_field_update(const struct usb_mux *me, uint8_t reg, uint8_t mask, uint8_t val) { - return i2c_field_update8(me->i2c_port, me->i2c_addr_flags, - reg, mask, val); + return i2c_field_update8(me->i2c_port, me->i2c_addr_flags, reg, mask, + val); } - int ps8743_check_chip_id(const struct usb_mux *me, int *val) { int id1; @@ -56,7 +53,7 @@ int ps8743_check_chip_id(const struct usb_mux *me, int *val) if (res) return res; - res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2); + res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2); if (res) return res; @@ -83,7 +80,7 @@ static int ps8743_init(const struct usb_mux *me) if (res) return res; - res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2); + res = ps8743_read(me, PS8743_REG_CHIP_ID2, &id2); if (res) return res; @@ -121,10 +118,9 @@ static int ps8743_set_mux(const struct usb_mux *me, mux_state_t mux_state, * For CE_DP, CE_USB, and FLIP, disable pin control and enable I2C * control. */ - uint8_t reg = (PS8743_MODE_IN_HPD_CONTROL | - PS8743_MODE_DP_REG_CONTROL | - PS8743_MODE_USB_REG_CONTROL | - PS8743_MODE_FLIP_REG_CONTROL); + uint8_t reg = + (PS8743_MODE_IN_HPD_CONTROL | PS8743_MODE_DP_REG_CONTROL | + PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_FLIP_REG_CONTROL); /* This driver does not use host command ACKs */ *ack_required = false; -- cgit v1.2.1 From 1d89375c39bdeafb4a49104f78df657aaf9bbf28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:48 -0600 Subject: driver/usb_mux/ps8822.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idea7065b73c5d44860a9566ec591fb0895e9f247 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730169 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8822.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/driver/usb_mux/ps8822.c b/driver/usb_mux/ps8822.c index 7f25db37f4..a2b433848a 100644 --- a/driver/usb_mux/ps8822.c +++ b/driver/usb_mux/ps8822.c @@ -15,15 +15,13 @@ static int ps8822_read(const struct usb_mux *me, int page, uint8_t reg, int *val) { - return i2c_read8(me->i2c_port, me->i2c_addr_flags + page, - reg, val); + return i2c_read8(me->i2c_port, me->i2c_addr_flags + page, reg, val); } static int ps8822_write(const struct usb_mux *me, int page, uint8_t reg, int val) { - return i2c_write8(me->i2c_port, me->i2c_addr_flags + page, - reg, val); + return i2c_write8(me->i2c_port, me->i2c_addr_flags + page, reg, val); } int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db) @@ -32,8 +30,7 @@ int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db) int rv; /* Read DP EQ register */ - rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, - &dpeq_reg); + rv = ps8822_read(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, &dpeq_reg); if (rv) return rv; @@ -44,13 +41,11 @@ int ps8822_set_dp_rx_eq(const struct usb_mux *me, int db) dpeq_reg &= ~PS8822_DP_EQ_AUTO_EN; /* Set gain to the requested value */ - dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK << - PS8822_REG_DP_EQ_SHIFT); + dpeq_reg &= ~(PS8822_DPEQ_LEVEL_UP_MASK << PS8822_REG_DP_EQ_SHIFT); dpeq_reg |= (db << PS8822_REG_DP_EQ_SHIFT); /* Apply new EQ setting */ - return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, - dpeq_reg); + return ps8822_write(me, PS8822_REG_PAGE1, PS8822_REG_DP_EQ, dpeq_reg); } static int ps8822_init(const struct usb_mux *me) @@ -126,7 +121,6 @@ static int ps8822_get_mux(const struct usb_mux *me, mux_state_t *mux_state) return EC_SUCCESS; } - const struct usb_mux_driver ps8822_usb_mux_driver = { .init = ps8822_init, .set = ps8822_set_mux, -- cgit v1.2.1 From a150f58e1399fc9719a5761b5b20c89baa2b3b4a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:55 -0600 Subject: test/timer_calib.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I618d0897f0036578fd95ac8356dddca568313e3f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730548 Reviewed-by: Jeremy Bettis --- test/timer_calib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/timer_calib.c b/test/timer_calib.c index 68603762fe..fe2d26761d 100644 --- a/test/timer_calib.c +++ b/test/timer_calib.c @@ -13,7 +13,7 @@ uint32_t difftime(timestamp_t t0, timestamp_t t1) { - return (uint32_t)(t1.val-t0.val); + return (uint32_t)(t1.val - t0.val); } int timer_calib_task(void *data) -- cgit v1.2.1 From 8618b554ca3f73e23cd413d275989863386ff9c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:13 -0600 Subject: board/brask/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If1a25a3ed5f027d7da9b3ea11f2d7caa4d4918c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728043 Reviewed-by: Jeremy Bettis --- board/brask/usbc_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brask/usbc_config.h b/board/brask/usbc_config.h index 7319bcb5e2..a57b3c486e 100644 --- a/board/brask/usbc_config.h +++ b/board/brask/usbc_config.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 3 +#define CONFIG_USB_PD_PORT_MAX_COUNT 3 enum usbc_port { USBC_PORT_C0 = 0, -- cgit v1.2.1 From a6f2bdb124eab5d457efd47fa8cee23feb09c0dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:05 -0600 Subject: board/brask/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I145f67147f3802c09dc5258dc74c0063a44da88d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728042 Reviewed-by: Jeremy Bettis --- board/brask/pwm.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/board/brask/pwm.c b/board/brask/pwm.c index 5ad905f861..a2ae9988f5 100644 --- a/board/brask/pwm.c +++ b/board/brask/pwm.c @@ -11,21 +11,16 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_GREEN] = { - .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, - .freq = 1000 - }, - [PWM_CH_LED_RED] = { - .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, + [PWM_CH_LED_GREEN] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, + .freq = 1000 }, + [PWM_CH_LED_RED] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From b49aae3d4b6f27a3cb8603fca702a8f1ccf6d645 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:05 -0600 Subject: chip/stm32/usb_power.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib4e88969854434172b4b17a56e1b0932d749ee10 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729579 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_power.h | 257 +++++++++++++++++++++++++------------------------ 1 file changed, 129 insertions(+), 128 deletions(-) diff --git a/chip/stm32/usb_power.h b/chip/stm32/usb_power.h index 51220691b6..2802148552 100644 --- a/chip/stm32/usb_power.h +++ b/chip/stm32/usb_power.h @@ -38,7 +38,8 @@ * * addina: 0x0002 * +--------+--------------------------+-------------+--------------+-----------+--------+ - * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: extra | 4B: Rs | + * | 0x0002 | 1B: 4b: extender 4b: bus | 1B:INA type | 1B: INA addr | 1B: + *extra | 4B: Rs | * +--------+--------------------------+-------------+--------------+-----------+--------+ * * start: 0x0003 @@ -90,40 +91,40 @@ /* 8b status field. */ enum usb_power_error { - USB_POWER_SUCCESS = 0x00, - USB_POWER_ERROR_I2C = 0x01, - USB_POWER_ERROR_OVERFLOW = 0x02, - USB_POWER_ERROR_NOT_SETUP = 0x03, - USB_POWER_ERROR_NOT_CAPTURING = 0x04, - USB_POWER_ERROR_TIMEOUT = 0x05, - USB_POWER_ERROR_BUSY = 0x06, - USB_POWER_ERROR_READ_SIZE = 0x07, - USB_POWER_ERROR_FULL = 0x08, - USB_POWER_ERROR_INVAL = 0x09, - USB_POWER_ERROR_UNKNOWN = 0x80, + USB_POWER_SUCCESS = 0x00, + USB_POWER_ERROR_I2C = 0x01, + USB_POWER_ERROR_OVERFLOW = 0x02, + USB_POWER_ERROR_NOT_SETUP = 0x03, + USB_POWER_ERROR_NOT_CAPTURING = 0x04, + USB_POWER_ERROR_TIMEOUT = 0x05, + USB_POWER_ERROR_BUSY = 0x06, + USB_POWER_ERROR_READ_SIZE = 0x07, + USB_POWER_ERROR_FULL = 0x08, + USB_POWER_ERROR_INVAL = 0x09, + USB_POWER_ERROR_UNKNOWN = 0x80, }; /* 16b command field. */ enum usb_power_command { - USB_POWER_CMD_RESET = 0x0000, - USB_POWER_CMD_STOP = 0x0001, - USB_POWER_CMD_ADDINA = 0x0002, - USB_POWER_CMD_START = 0x0003, - USB_POWER_CMD_NEXT = 0x0004, - USB_POWER_CMD_SETTIME = 0x0005, + USB_POWER_CMD_RESET = 0x0000, + USB_POWER_CMD_STOP = 0x0001, + USB_POWER_CMD_ADDINA = 0x0002, + USB_POWER_CMD_START = 0x0003, + USB_POWER_CMD_NEXT = 0x0004, + USB_POWER_CMD_SETTIME = 0x0005, }; /* Addina "INA Type" field. */ enum usb_power_ina_type { - USBP_INA231_POWER = 0x01, - USBP_INA231_BUSV = 0x02, - USBP_INA231_CURRENT = 0x03, - USBP_INA231_SHUNTV = 0x04, + USBP_INA231_POWER = 0x01, + USBP_INA231_BUSV = 0x02, + USBP_INA231_CURRENT = 0x03, + USBP_INA231_SHUNTV = 0x04, }; /* Internal state machine values */ enum usb_power_states { - USB_POWER_STATE_OFF = 0, + USB_POWER_STATE_OFF = 0, USB_POWER_STATE_SETUP, USB_POWER_STATE_CAPTURING, }; @@ -154,8 +155,7 @@ struct usb_power_ina_cfg { int shared; }; - -struct __attribute__ ((__packed__)) usb_power_report { +struct __attribute__((__packed__)) usb_power_report { uint8_t status; uint8_t size; uint64_t timestamp; @@ -163,17 +163,19 @@ struct __attribute__ ((__packed__)) usb_power_report { }; /* Must be 4 byte aligned */ -#define USB_POWER_RECORD_SIZE(ina_count) \ - ((((sizeof(struct usb_power_report) \ - - (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) \ - + (sizeof(uint16_t) * (ina_count))) + 3) / 4) * 4) - -#define USB_POWER_DATA_SIZE \ +#define USB_POWER_RECORD_SIZE(ina_count) \ + ((((sizeof(struct usb_power_report) - \ + (sizeof(uint16_t) * USB_POWER_MAX_READ_COUNT) + \ + (sizeof(uint16_t) * (ina_count))) + \ + 3) / \ + 4) * \ + 4) + +#define USB_POWER_DATA_SIZE \ (sizeof(struct usb_power_report) * (USB_POWER_MIN_CACHED + 1)) -#define USB_POWER_MAX_CACHED(ina_count) \ +#define USB_POWER_MAX_CACHED(ina_count) \ (USB_POWER_DATA_SIZE / USB_POWER_RECORD_SIZE(ina_count)) - struct usb_power_state { /* * The power data acquisition must be setup, then started, in order to @@ -212,7 +214,6 @@ struct usb_power_state { uint8_t tx_buf[USB_MAX_PACKET_SIZE * 4]; }; - /* * Compile time Per-USB gpio configuration stored in flash. Instances of this * structure are provided by the user of the USB gpio. This structure binds @@ -234,12 +235,12 @@ struct usb_power_config { const struct deferred_data *deferred_cap; }; -struct __attribute__ ((__packed__)) usb_power_command_start { +struct __attribute__((__packed__)) usb_power_command_start { uint16_t command; uint32_t integration_us; }; -struct __attribute__ ((__packed__)) usb_power_command_addina { +struct __attribute__((__packed__)) usb_power_command_addina { uint16_t command; uint8_t port; uint8_t type; @@ -248,7 +249,7 @@ struct __attribute__ ((__packed__)) usb_power_command_addina { uint32_t rs; }; -struct __attribute__ ((__packed__)) usb_power_command_settime { +struct __attribute__((__packed__)) usb_power_command_settime { uint16_t command; uint64_t time; }; @@ -260,7 +261,6 @@ union usb_power_command_data { struct usb_power_command_settime settime; }; - /* * Convenience macro for defining a USB INA Power driver. * @@ -273,92 +273,96 @@ union usb_power_command_data { * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_POWER_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT) \ - static void CONCAT2(NAME, _deferred_tx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ - static void CONCAT2(NAME, _deferred_rx_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ - static void CONCAT2(NAME, _deferred_cap_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ - struct usb_power_state CONCAT2(NAME, _state_) = { \ - .state = USB_POWER_STATE_OFF, \ - .ina_count = 0, \ - .integration_us = 0, \ - .reports_head = 0, \ - .reports_tail = 0, \ - .wall_offset = 0, \ - }; \ - static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ - .max_packet = USB_MAX_PACKET_SIZE, \ - .tx_fifo = ENDPOINT, \ - .out_pending = 0, \ - .out_data = 0, \ - .out_databuffer = 0, \ - .out_databuffer_max = 0, \ - .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ - .in_packets = 0, \ - .in_pending = 0, \ - .in_data = 0, \ - .in_databuffer = 0, \ - .in_databuffer_max = 0, \ - .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ - }; \ - struct usb_power_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .ep = &CONCAT2(NAME, _ep_ctl), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 1, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_epN_tx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_epN_rx(ENDPOINT); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_power_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static void CONCAT2(NAME, _deferred_tx_)(void) \ - { usb_power_deferred_tx(&NAME); } \ - static void CONCAT2(NAME, _deferred_rx_)(void) \ - { usb_power_deferred_rx(&NAME); } \ - static void CONCAT2(NAME, _deferred_cap_)(void) \ - { usb_power_deferred_cap(&NAME); } - +#define USB_POWER_CONFIG(NAME, INTERFACE, ENDPOINT) \ + static void CONCAT2(NAME, _deferred_tx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_tx_)); \ + static void CONCAT2(NAME, _deferred_rx_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_)); \ + static void CONCAT2(NAME, _deferred_cap_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_cap_)); \ + struct usb_power_state CONCAT2(NAME, _state_) = { \ + .state = USB_POWER_STATE_OFF, \ + .ina_count = 0, \ + .integration_us = 0, \ + .reports_head = 0, \ + .reports_tail = 0, \ + .wall_offset = 0, \ + }; \ + static struct dwc_usb_ep CONCAT2(NAME, _ep_ctl) = { \ + .max_packet = USB_MAX_PACKET_SIZE, \ + .tx_fifo = ENDPOINT, \ + .out_pending = 0, \ + .out_data = 0, \ + .out_databuffer = 0, \ + .out_databuffer_max = 0, \ + .rx_deferred = &CONCAT2(NAME, _deferred_rx__data), \ + .in_packets = 0, \ + .in_pending = 0, \ + .in_data = 0, \ + .in_databuffer = 0, \ + .in_databuffer_max = 0, \ + .tx_deferred = &CONCAT2(NAME, _deferred_tx__data), \ + }; \ + struct usb_power_config const NAME = { \ + .state = &CONCAT2(NAME, _state_), \ + .ep = &CONCAT2(NAME, _ep_ctl), \ + .interface = INTERFACE, \ + .endpoint = ENDPOINT, \ + .deferred_cap = &CONCAT2(NAME, _deferred_cap__data), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_POWER, \ + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_POWER, \ + .iInterface = 0, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 1, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx_)(void) \ + { \ + usb_epN_tx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_rx_)(void) \ + { \ + usb_epN_rx(ENDPOINT); \ + } \ + static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ + { \ + usb_power_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_), \ + CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_)); \ + static void CONCAT2(NAME, _deferred_tx_)(void) \ + { \ + usb_power_deferred_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_rx_)(void) \ + { \ + usb_power_deferred_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _deferred_cap_)(void) \ + { \ + usb_power_deferred_cap(&NAME); \ + } /* * Handle power request in a deferred callback. @@ -374,9 +378,6 @@ void usb_power_deferred_cap(struct usb_power_config const *config); void usb_power_tx(struct usb_power_config const *config); void usb_power_rx(struct usb_power_config const *config); void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt); - - - + enum usb_ep_event evt); #endif /* __CROS_EC_USB_DWC_POWER_H */ -- cgit v1.2.1 From 5317a903132c1314a9b97ff68034a902d84ede29 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:40 -0600 Subject: common/i2c_wedge.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f1f187ab0ac7cfadc73aef32b134a1281be92e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729656 Reviewed-by: Jeremy Bettis --- common/i2c_wedge.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/common/i2c_wedge.c b/common/i2c_wedge.c index fc0a5132b7..9caa880052 100644 --- a/common/i2c_wedge.c +++ b/common/i2c_wedge.c @@ -199,8 +199,7 @@ static void i2c_bang_xfer(int addr, int reg) ccprintf(" read byte: %d\n", byte); } -static void i2c_bang_wedge_write(int addr, int byte, int bit_count, - int reboot) +static void i2c_bang_wedge_write(int addr, int byte, int bit_count, int reboot) { int i; @@ -219,8 +218,7 @@ static void i2c_bang_wedge_write(int addr, int byte, int bit_count, system_reset(0); } -static void i2c_bang_wedge_read(int addr, int reg, int bit_count, - int reboot) +static void i2c_bang_wedge_read(int addr, int reg, int bit_count, int reboot) { int i; @@ -244,9 +242,9 @@ static void i2c_bang_wedge_read(int addr, int reg, int bit_count, system_reset(0); } -#define WEDGE_WRITE 1 -#define WEDGE_READ 2 -#define WEDGE_REBOOT 4 +#define WEDGE_WRITE 1 +#define WEDGE_READ 2 +#define WEDGE_REBOOT 4 static int command_i2c_wedge(int argc, char **argv) { @@ -256,17 +254,17 @@ static int command_i2c_wedge(int argc, char **argv) /* Verify that the I2C_PORT_HOST has SDA and SCL pins defined. */ if (get_sda_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS || - get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) { + get_scl_from_i2c_port(I2C_PORT_HOST, &tmp) != EC_SUCCESS) { ccprintf("Cannot wedge bus because no SCL and SDA pins are" - "defined for this port. Check i2c_ports[].\n"); + "defined for this port. Check i2c_ports[].\n"); return EC_SUCCESS; } if (argc < 3) { ccputs("Usage: i2cwedge addr out_byte " - "[wedge_flag [wedge_bit_count]]\n"); + "[wedge_flag [wedge_bit_count]]\n"); ccputs(" wedge_flag - (1: wedge out; 2: wedge in;" - " 5: wedge out+reboot; 6: wedge in+reboot)]\n"); + " 5: wedge out+reboot; 6: wedge in+reboot)]\n"); ccputs(" wedge_bit_count - 0 to 8\n"); return EC_ERROR_UNKNOWN; } @@ -302,12 +300,12 @@ static int command_i2c_wedge(int argc, char **argv) if (wedge_bit_count < 0) wedge_bit_count = 8; i2c_bang_wedge_write(addr, reg, wedge_bit_count, - (wedge_flag & WEDGE_REBOOT)); + (wedge_flag & WEDGE_REBOOT)); } else if (wedge_flag & WEDGE_READ) { if (wedge_bit_count < 0) wedge_bit_count = 2; i2c_bang_wedge_read(addr, reg, wedge_bit_count, - (wedge_flag & WEDGE_REBOOT)); + (wedge_flag & WEDGE_REBOOT)); } else { i2c_bang_xfer(addr, reg); } @@ -326,7 +324,7 @@ static int command_i2c_wedge(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(i2cwedge, command_i2c_wedge, "i2cwedge addr out_byte " - "[wedge_flag [wedge_bit_count]]", + "[wedge_flag [wedge_bit_count]]", "Wedge host I2C bus"); static int command_i2c_unwedge(int argc, char **argv) @@ -335,6 +333,5 @@ static int command_i2c_unwedge(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge, - "", - "Unwedge host I2C bus"); +DECLARE_CONSOLE_COMMAND(i2cunwedge, command_i2c_unwedge, "", + "Unwedge host I2C bus"); -- cgit v1.2.1 From e149581ddab1a7c8fa42d3c79577560694f83833 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:26 -0600 Subject: zephyr/shim/chip/mchp/system_external_storage.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2b79aef92da1d3bc9432b35aab91894513405532 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730820 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/system_external_storage.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/chip/mchp/system_external_storage.c b/zephyr/shim/chip/mchp/system_external_storage.c index c326a07328..983cebd64e 100644 --- a/zephyr/shim/chip/mchp/system_external_storage.c +++ b/zephyr/shim/chip/mchp/system_external_storage.c @@ -13,12 +13,11 @@ #include "system_chip.h" #include "config_chip.h" -#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */ -#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */ -#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr) +#define MCHP_ECRO_WORD 0x4F524345u /* ASCII ECRO */ +#define MCHP_ECRW_WORD 0x57524345u /* ASCII ECRW */ +#define MCHP_PCR_NODE DT_INST(0, microchip_xec_pcr) -#define GET_BBRAM_OFS(node) \ - DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset) #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) static const struct device *const bbram_dev = @@ -49,8 +48,8 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_CROS_EC_RW_SIZE; break; case EC_IMAGE_RO: -- cgit v1.2.1 From a59d0e8d995ddf229f917a121997fd280ad63c78 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:45 -0600 Subject: common/mock/battery_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I60da12d72cd8d86d34b1a9b74cfe7c1a34934514 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729687 Reviewed-by: Jeremy Bettis --- common/mock/battery_mock.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/common/mock/battery_mock.c b/common/mock/battery_mock.c index 63e94c660b..45bd944fbd 100644 --- a/common/mock/battery_mock.c +++ b/common/mock/battery_mock.c @@ -141,7 +141,7 @@ void set_battery_time_to_full(int new_value) } #define MAX_DEVICE_NAME_LENGTH 40 -static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH+1] = "?"; +static char battery_device_name_value[MAX_DEVICE_NAME_LENGTH + 1] = "?"; int battery_device_name(char *dest, int size) { int i; @@ -159,12 +159,13 @@ void set_battery_device_name(char *new_value) for (i = 0; i < size && i < MAX_DEVICE_NAME_LENGTH; ++i) battery_device_name_value[i] = new_value[i]; - for (; i < MAX_DEVICE_NAME_LENGTH+1; ++i) + for (; i < MAX_DEVICE_NAME_LENGTH + 1; ++i) battery_device_name_value[i] = '\0'; } #define MAX_DEVICE_CHEMISTRY_LENGTH 40 -static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH+1] = "?"; +static char battery_device_chemistry_value[MAX_DEVICE_CHEMISTRY_LENGTH + 1] = + "?"; int battery_device_chemistry(char *dest, int size) { int i; @@ -182,7 +183,7 @@ void set_battery_device_chemistry(char *new_value) for (i = 0; i < size && i < MAX_DEVICE_CHEMISTRY_LENGTH; ++i) battery_device_chemistry_value[i] = new_value[i]; - for (; i < MAX_DEVICE_CHEMISTRY_LENGTH+1; ++i) + for (; i < MAX_DEVICE_CHEMISTRY_LENGTH + 1; ++i) battery_device_chemistry_value[i] = '\0'; } @@ -194,7 +195,7 @@ static int battery_temperature_value = 20; static int battery_voltage_value = 5000; void battery_get_params(struct batt_params *batt) { - struct batt_params batt_new = {0}; + struct batt_params batt_new = { 0 }; batt_new.temperature = battery_temperature_value; batt_new.state_of_charge = battery_soc_value; -- cgit v1.2.1 From b8bde36fb3797b563ff2ba0d374ce51e09909867 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:37 -0600 Subject: extra/touchpad_updater/touchpad_updater.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie427e3ee7843883b0b4c9337980ad1074da2a630 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730186 Reviewed-by: Jeremy Bettis --- extra/touchpad_updater/touchpad_updater.c | 164 ++++++++++++++---------------- 1 file changed, 77 insertions(+), 87 deletions(-) diff --git a/extra/touchpad_updater/touchpad_updater.c b/extra/touchpad_updater/touchpad_updater.c index 716ded00f5..561e4252b2 100644 --- a/extra/touchpad_updater/touchpad_updater.c +++ b/extra/touchpad_updater/touchpad_updater.c @@ -18,16 +18,16 @@ #include /* Command line options */ -static uint16_t vid = 0x18d1; /* Google */ -static uint16_t pid = 0x5022; /* Hammer */ -static uint8_t ep_num = 4; /* console endpoint */ -static uint8_t extended_i2c_exercise; /* non-zero to exercise */ -static char *firmware_binary = "144.0_2.0.bin"; /* firmware blob */ +static uint16_t vid = 0x18d1; /* Google */ +static uint16_t pid = 0x5022; /* Hammer */ +static uint8_t ep_num = 4; /* console endpoint */ +static uint8_t extended_i2c_exercise; /* non-zero to exercise */ +static char *firmware_binary = "144.0_2.0.bin"; /* firmware blob */ /* Firmware binary blob related */ -#define MAX_FW_PAGE_SIZE 512 -#define MAX_FW_PAGE_COUNT 1024 -#define MAX_FW_SIZE (128 * 1024) +#define MAX_FW_PAGE_SIZE 512 +#define MAX_FW_PAGE_COUNT 1024 +#define MAX_FW_SIZE (128 * 1024) static uint8_t fw_data[MAX_FW_SIZE]; int fw_page_count; @@ -47,13 +47,10 @@ static char *progname; static char *short_opts = ":f:v:p:e:hd"; static const struct option long_opts[] = { /* name hasarg *flag val */ - {"file", 1, NULL, 'f'}, - {"vid", 1, NULL, 'v'}, - {"pid", 1, NULL, 'p'}, - {"ep", 1, NULL, 'e'}, - {"help", 0, NULL, 'h'}, - {"debug", 0, NULL, 'd'}, - {NULL, 0, NULL, 0}, + { "file", 1, NULL, 'f' }, { "vid", 1, NULL, 'v' }, + { "pid", 1, NULL, 'p' }, { "ep", 1, NULL, 'e' }, + { "help", 0, NULL, 'h' }, { "debug", 0, NULL, 'd' }, + { NULL, 0, NULL, 0 }, }; static void usage(int errs) @@ -71,7 +68,8 @@ static void usage(int errs) " -d,--debug Exercise extended read I2C over USB\n" " and print verbose debug messages.\n" " -h,--help Show this message\n" - "\n", progname, firmware_binary, vid, pid, ep_num); + "\n", + progname, firmware_binary, vid, pid, ep_num); exit(!!errs); } @@ -87,28 +85,28 @@ static void parse_cmdline(int argc, char *argv[]) else progname = argv[0]; - opterr = 0; /* quiet, you */ + opterr = 0; /* quiet, you */ while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) { switch (i) { case 'f': firmware_binary = optarg; break; case 'p': - pid = (uint16_t) strtoull(optarg, &e, 16); + pid = (uint16_t)strtoull(optarg, &e, 16); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; } break; case 'v': - vid = (uint16_t) strtoull(optarg, &e, 16); + vid = (uint16_t)strtoull(optarg, &e, 16); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; } break; case 'e': - ep_num = (uint8_t) strtoull(optarg, &e, 0); + ep_num = (uint8_t)strtoull(optarg, &e, 0); if (!*optarg || (e && *e)) { printf("Invalid argument: \"%s\"\n", optarg); errorcnt++; @@ -120,7 +118,7 @@ static void parse_cmdline(int argc, char *argv[]) case 'h': usage(errorcnt); break; - case 0: /* auto-handled option */ + case 0: /* auto-handled option */ break; case '?': if (optopt) @@ -142,7 +140,6 @@ static void parse_cmdline(int argc, char *argv[]) if (errorcnt) usage(errorcnt); - } /* USB transfer related */ @@ -163,7 +160,7 @@ static void request_exit(const char *format, ...) va_start(ap, format); vfprintf(stderr, format, ap); va_end(ap); - do_exit++; /* Why need this ? */ + do_exit++; /* Why need this ? */ if (tx_transfer) libusb_free_transfer(tx_transfer); @@ -178,9 +175,8 @@ static void request_exit(const char *format, ...) exit(1); } -#define DIE(msg, r) \ - request_exit("%s: line %d, %s\n", msg, __LINE__, \ - libusb_error_name(r)) +#define DIE(msg, r) \ + request_exit("%s: line %d, %s\n", msg, __LINE__, libusb_error_name(r)) static void sighandler(int signum) { @@ -259,8 +255,8 @@ static void register_sigaction(void) } /* Transfer over libusb */ -#define I2C_PORT_ON_HAMMER 0x00 -#define I2C_ADDRESS_ON_HAMMER 0x15 +#define I2C_PORT_ON_HAMMER 0x00 +#define I2C_ADDRESS_ON_HAMMER 0x15 static int check_read_status(int r, int expected, int actual) { @@ -291,12 +287,12 @@ static int check_read_status(int r, int expected, int actual) return r; } -#define MAX_USB_PACKET_SIZE 64 -#define PRIMITIVE_READING_SIZE 60 +#define MAX_USB_PACKET_SIZE 64 +#define PRIMITIVE_READING_SIZE 60 -static int libusb_single_write_and_read( - const uint8_t *to_write, uint16_t write_length, - uint8_t *to_read, uint16_t read_length) +static int libusb_single_write_and_read(const uint8_t *to_write, + uint16_t write_length, uint8_t *to_read, + uint16_t read_length) { int r; int tx_ready; @@ -315,10 +311,10 @@ static int libusb_single_write_and_read( tx_buf[4] = read_length >> 7; if (extended_i2c_exercise) { printf("Triggering extended reading." - "rc:%0x, rc1:%0x\n", - tx_buf[3], tx_buf[4]); + "rc:%0x, rc1:%0x\n", + tx_buf[3], tx_buf[4]); printf("Expecting %d Bytes.\n", - (tx_buf[3] & 0x7f) | (tx_buf[4] << 7)); + (tx_buf[3] & 0x7f) | (tx_buf[4] << 7)); } } else { tx_buf[3] = read_length; @@ -331,19 +327,18 @@ static int libusb_single_write_and_read( while (sent_bytes < (offset + write_length)) { tx_ready = remains = (offset + write_length) - sent_bytes; - r = libusb_bulk_transfer(devh, - (ep_num | LIBUSB_ENDPOINT_OUT), - tx_buf + sent_bytes, tx_ready, - &actual_length, 5000); + r = libusb_bulk_transfer(devh, (ep_num | LIBUSB_ENDPOINT_OUT), + tx_buf + sent_bytes, tx_ready, + &actual_length, 5000); if (r == 0 && actual_length == tx_ready) { r = libusb_bulk_transfer(devh, - (ep_num | LIBUSB_ENDPOINT_IN), - rx_buf, sizeof(rx_buf), - &actual_length, 5000); + (ep_num | LIBUSB_ENDPOINT_IN), + rx_buf, sizeof(rx_buf), + &actual_length, 5000); } - r = check_read_status( - r, (remains == tx_ready) ? read_length : 0, - actual_length); + r = check_read_status(r, + (remains == tx_ready) ? read_length : 0, + actual_length); if (r) break; sent_bytes += tx_ready; @@ -352,21 +347,19 @@ static int libusb_single_write_and_read( } /* Control Elan trackpad I2C over USB */ -#define ETP_I2C_INF_LENGTH 2 +#define ETP_I2C_INF_LENGTH 2 -static int elan_write_and_read( - int reg, uint8_t *buf, int read_length, - int with_cmd, int cmd) +static int elan_write_and_read(int reg, uint8_t *buf, int read_length, + int with_cmd, int cmd) { - tx_buf[0] = (reg >> 0) & 0xff; tx_buf[1] = (reg >> 8) & 0xff; if (with_cmd) { tx_buf[2] = (cmd >> 0) & 0xff; tx_buf[3] = (cmd >> 8) & 0xff; } - return libusb_single_write_and_read( - tx_buf, with_cmd ? 4 : 2, rx_buf, read_length); + return libusb_single_write_and_read(tx_buf, with_cmd ? 4 : 2, rx_buf, + read_length); } static int elan_read_block(int reg, uint8_t *buf, int read_length) @@ -385,16 +378,16 @@ static int elan_write_cmd(int reg, int cmd) } /* Elan trackpad firmware information related */ -#define ETP_I2C_IAP_VERSION_CMD 0x0110 -#define ETP_I2C_FW_VERSION_CMD 0x0102 -#define ETP_I2C_IAP_CHECKSUM_CMD 0x0315 -#define ETP_I2C_FW_CHECKSUM_CMD 0x030F -#define ETP_I2C_OSM_VERSION_CMD 0x0103 +#define ETP_I2C_IAP_VERSION_CMD 0x0110 +#define ETP_I2C_FW_VERSION_CMD 0x0102 +#define ETP_I2C_IAP_CHECKSUM_CMD 0x0315 +#define ETP_I2C_FW_CHECKSUM_CMD 0x030F +#define ETP_I2C_OSM_VERSION_CMD 0x0103 static int elan_get_version(int is_iap) { - elan_read_cmd( - is_iap ? ETP_I2C_IAP_VERSION_CMD : ETP_I2C_FW_VERSION_CMD); + elan_read_cmd(is_iap ? ETP_I2C_IAP_VERSION_CMD : + ETP_I2C_FW_VERSION_CMD); return le_bytes_to_int(rx_buf + 4); } @@ -435,8 +428,8 @@ static void elan_get_ic_page_count(void) static int elan_get_checksum(int is_iap) { - elan_read_cmd( - is_iap ? ETP_I2C_IAP_CHECKSUM_CMD : ETP_I2C_FW_CHECKSUM_CMD); + elan_read_cmd(is_iap ? ETP_I2C_IAP_CHECKSUM_CMD : + ETP_I2C_FW_CHECKSUM_CMD); return le_bytes_to_int(rx_buf + 4); } @@ -451,21 +444,21 @@ static uint16_t elan_get_fw_info(void) iap_checksum = elan_get_checksum(1); fw_version = elan_get_version(0); iap_version = elan_get_version(1); - printf("IAP version: %4x, FW version: %4x\n", - iap_version, fw_version); - printf("IAP checksum: %4x, FW checksum: %4x\n", - iap_checksum, fw_checksum); + printf("IAP version: %4x, FW version: %4x\n", iap_version, + fw_version); + printf("IAP checksum: %4x, FW checksum: %4x\n", iap_checksum, + fw_checksum); return fw_checksum; } /* Update preparation */ -#define ETP_I2C_IAP_RESET_CMD 0x0314 -#define ETP_I2C_IAP_RESET 0xF0F0 -#define ETP_I2C_IAP_CTRL_CMD 0x0310 -#define ETP_I2C_MAIN_MODE_ON (1 << 9) -#define ETP_I2C_IAP_CMD 0x0311 -#define ETP_I2C_IAP_PASSWORD 0x1EA5 -#define ETP_I2C_IAP_TYPE_CMD 0x0304 +#define ETP_I2C_IAP_RESET_CMD 0x0314 +#define ETP_I2C_IAP_RESET 0xF0F0 +#define ETP_I2C_IAP_CTRL_CMD 0x0310 +#define ETP_I2C_MAIN_MODE_ON (1 << 9) +#define ETP_I2C_IAP_CMD 0x0311 +#define ETP_I2C_IAP_PASSWORD 0x1EA5 +#define ETP_I2C_IAP_TYPE_CMD 0x0304 static int elan_in_main_mode(void) { @@ -478,8 +471,7 @@ static int elan_read_write_iap_type(void) for (int retry = 0; retry < 3; ++retry) { uint16_t val; - if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD, - fw_page_size / 2)) + if (elan_write_cmd(ETP_I2C_IAP_TYPE_CMD, fw_page_size / 2)) return -1; if (elan_read_cmd(ETP_I2C_IAP_TYPE_CMD)) @@ -490,7 +482,6 @@ static int elan_read_write_iap_type(void) printf("%s: OK\n", __func__); return 0; } - } return -1; } @@ -528,17 +519,17 @@ static void elan_prepare_for_update(void) request_exit("cannot read iap password.\n"); if (le_bytes_to_int(rx_buf + 4) != ETP_I2C_IAP_PASSWORD) request_exit("Got an unexpected IAP password %4x\n", - le_bytes_to_int(rx_buf + 4)); + le_bytes_to_int(rx_buf + 4)); } /* Firmware block update */ -#define ETP_IAP_START_ADDR 0x0083 +#define ETP_IAP_START_ADDR 0x0083 static uint16_t elan_calc_checksum(uint8_t *data, int length) { uint16_t checksum = 0; for (int i = 0; i < length; i += 2) - checksum += ((uint16_t)(data[i+1]) << 8) | (data[i]); + checksum += ((uint16_t)(data[i + 1]) << 8) | (data[i]); return checksum; } @@ -547,11 +538,11 @@ static int elan_get_iap_addr(void) return le_bytes_to_int(fw_data + ETP_IAP_START_ADDR * 2) * 2; } -#define ETP_I2C_IAP_REG_L 0x01 -#define ETP_I2C_IAP_REG_H 0x06 +#define ETP_I2C_IAP_REG_L 0x01 +#define ETP_I2C_IAP_REG_H 0x06 -#define ETP_FW_IAP_PAGE_ERR (1 << 5) -#define ETP_FW_IAP_INTF_ERR (1 << 4) +#define ETP_FW_IAP_PAGE_ERR (1 << 5) +#define ETP_FW_IAP_INTF_ERR (1 << 4) static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum) { @@ -564,8 +555,8 @@ static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum) page_store[fw_page_size + 2 + 0] = (checksum >> 0) & 0xff; page_store[fw_page_size + 2 + 1] = (checksum >> 8) & 0xff; - rv = libusb_single_write_and_read( - page_store, fw_page_size + 4, rx_buf, 0); + rv = libusb_single_write_and_read(page_store, fw_page_size + 4, rx_buf, + 0); if (rv) return rv; usleep((fw_page_size >= 512 ? 50 : 35) * 1000); @@ -578,7 +569,6 @@ static int elan_write_fw_block(uint8_t *raw_data, uint16_t checksum) return 0; } - static uint16_t elan_update_firmware(void) { uint16_t checksum = 0, block_checksum; @@ -661,7 +651,7 @@ int main(int argc, char *argv[]) remote_checksum = elan_get_checksum(1); if (remote_checksum != local_checksum) printf("checksum diff local=[%04X], remote=[%04X]\n", - local_checksum, remote_checksum); + local_checksum, remote_checksum); /* Print the updated firmware information */ elan_get_fw_info(); -- cgit v1.2.1 From f267b3973ff935a57a12fa49aa45bb6b7c465caf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:22 -0600 Subject: driver/retimer/nb7v904m.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d622690943ce3c80008d6fe68f365c9c99d0d6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730042 Reviewed-by: Jeremy Bettis --- driver/retimer/nb7v904m.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/driver/retimer/nb7v904m.c b/driver/retimer/nb7v904m.c index 94e96230b2..4e73c5d3ee 100644 --- a/driver/retimer/nb7v904m.c +++ b/driver/retimer/nb7v904m.c @@ -12,8 +12,8 @@ #include "nb7v904m.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #ifdef CONFIG_NB7V904M_LPM_OVERRIDE int nb7v904m_lpm_disable = 0; @@ -21,18 +21,12 @@ int nb7v904m_lpm_disable = 0; static int nb7v904m_write(const struct usb_mux *me, int offset, int data) { - return i2c_write8(me->i2c_port, - me->i2c_addr_flags, - offset, data); - + return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data); } static int nb7v904m_read(const struct usb_mux *me, int offset, int *regval) { - return i2c_read8(me->i2c_port, - me->i2c_addr_flags, - offset, regval); - + return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, regval); } static int set_low_power_mode(const struct usb_mux *me, bool enable) @@ -68,7 +62,7 @@ static int nb7v904m_enter_low_power_mode(const struct usb_mux *me) /* Tune USB Eq All: This must be called on board_init context */ int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, - uint8_t eq_b, uint8_t eq_c, uint8_t eq_d) + uint8_t eq_b, uint8_t eq_c, uint8_t eq_d) { int rv = EC_SUCCESS; @@ -89,7 +83,7 @@ int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, /* Tune USB Flat Gain: This must be called on board_init context */ int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, - uint8_t gain_b, uint8_t gain_c, uint8_t gain_d) + uint8_t gain_b, uint8_t gain_c, uint8_t gain_d) { int rv = EC_SUCCESS; @@ -110,7 +104,8 @@ int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, /* Set Loss Profile Matching : This must be called on board_init context */ int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a, - uint8_t loss_b, uint8_t loss_c, uint8_t loss_d) + uint8_t loss_b, uint8_t loss_c, + uint8_t loss_d) { int rv = EC_SUCCESS; @@ -168,8 +163,8 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* Clear operation mode field */ rv = nb7v904m_read(me, NB7V904M_REG_GEN_DEV_SETTINGS, ®val); if (rv) { - CPRINTS("C%d %s: Failed to obtain dev settings!", - me->usb_port, __func__); + CPRINTS("C%d %s: Failed to obtain dev settings!", me->usb_port, + __func__); return rv; } regval &= ~NB7V904M_OP_MODE_MASK; @@ -193,9 +188,9 @@ static int nb7v904m_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Connect AUX */ - rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, flipped ? - NB7V904M_AUX_CH_FLIPPED : - NB7V904M_AUX_CH_NORMAL); + rv = nb7v904m_write(me, NB7V904M_REG_AUX_CH_CTRL, + flipped ? NB7V904M_AUX_CH_FLIPPED : + NB7V904M_AUX_CH_NORMAL); /* Enable all channels for DP */ regval |= NB7V904M_CH_EN_MASK; } else { -- cgit v1.2.1 From ee5a74b8ae6974049324962ad1ca852108ef71bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:00 -0600 Subject: util/ec_sb_firmware_update.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0613967c206c0ebf84033c7ccba81535ad2fda5b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730615 Reviewed-by: Jeremy Bettis --- util/ec_sb_firmware_update.h | 54 ++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/util/ec_sb_firmware_update.h b/util/ec_sb_firmware_update.h index 5bddebaf4a..720968ef10 100644 --- a/util/ec_sb_firmware_update.h +++ b/util/ec_sb_firmware_update.h @@ -55,7 +55,7 @@ struct sb_fw_header { uint16_t data_table_version; /* E F */ uint32_t fw_binary_offset; /*0x10 0x11 0x12 0x13 */ uint32_t fw_binary_size; /* 0x14 0x15 0x16 0x17 */ - uint8_t checksum; /* 0x18 */ + uint8_t checksum; /* 0x18 */ }; /** @@ -63,25 +63,25 @@ struct sb_fw_header { * Firmware Update Status */ struct sb_fw_update_status { - uint16_t v_fail_maker_id:1; /* b0 */ - uint16_t v_fail_hw_id:1; /* b1 */ - uint16_t v_fail_fw_version:1; /* b2 */ - uint16_t v_fail_permanent:1; /* b3 */ + uint16_t v_fail_maker_id : 1; /* b0 */ + uint16_t v_fail_hw_id : 1; /* b1 */ + uint16_t v_fail_fw_version : 1; /* b2 */ + uint16_t v_fail_permanent : 1; /* b3 */ - uint16_t rsvd5:1; /* b4 */ - uint16_t permanent_failure:1; /* b5 */ - uint16_t abnormal_condition:1; /* b6 */ - uint16_t fw_update_supported:1; /* b7 */ + uint16_t rsvd5 : 1; /* b4 */ + uint16_t permanent_failure : 1; /* b5 */ + uint16_t abnormal_condition : 1; /* b6 */ + uint16_t fw_update_supported : 1; /* b7 */ - uint16_t fw_update_mode:1; /* b8 */ - uint16_t fw_corrupted:1; /* b9 */ - uint16_t cmd_reject:1; /* b10 */ - uint16_t invalid_data:1; /* b11 */ + uint16_t fw_update_mode : 1; /* b8 */ + uint16_t fw_corrupted : 1; /* b9 */ + uint16_t cmd_reject : 1; /* b10 */ + uint16_t invalid_data : 1; /* b11 */ - uint16_t fw_fatal_error:1; /* b12 */ - uint16_t fec_error:1; /* b13 */ - uint16_t busy:1; /* b14 */ - uint16_t rsvd15:1; /* b15 */ + uint16_t fw_fatal_error : 1; /* b12 */ + uint16_t fec_error : 1; /* b13 */ + uint16_t busy : 1; /* b14 */ + uint16_t rsvd15 : 1; /* b15 */ } __packed; /** @@ -90,22 +90,22 @@ struct sb_fw_update_status { * sequence:=b1,b0,b3,b2,b5,b5,b7,b6 */ struct sb_fw_update_info { - uint16_t maker_id; /* b0, b1 */ + uint16_t maker_id; /* b0, b1 */ uint16_t hardware_id; /* b2, b3 */ - uint16_t fw_version; /* b4, b5 */ - uint16_t data_version;/* b6, b7 */ + uint16_t fw_version; /* b4, b5 */ + uint16_t data_version; /* b6, b7 */ } __packed; /** * smart.battery.maker.id */ enum sb_maker_id { - sb_maker_id_lgc = 0x0001, /* b0=0; b1=1 */ + sb_maker_id_lgc = 0x0001, /* b0=0; b1=1 */ sb_maker_id_panasonic = 0x0002, - sb_maker_id_sanyo = 0x0003, - sb_maker_id_sony = 0x0004, - sb_maker_id_simplo = 0x0005, - sb_maker_id_celxpert = 0x0006, + sb_maker_id_sanyo = 0x0003, + sb_maker_id_sony = 0x0004, + sb_maker_id_simplo = 0x0005, + sb_maker_id_celxpert = 0x0006, }; /* @@ -119,8 +119,8 @@ enum sb_maker_id { * case 5. If battery interface is busy, retry < 10 times. * Delay 1 second between retries. */ -#define SB_FW_UPDATE_ERROR_RETRY_CNT 2 -#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT 2 +#define SB_FW_UPDATE_ERROR_RETRY_CNT 2 +#define SB_FW_UPDATE_FEC_ERROR_RETRY_CNT 2 #define SB_FW_UPDATE_BUSY_ERROR_RETRY_CNT 4 #endif -- cgit v1.2.1 From d577813629a2c9223872bd8c47f65cea7d84ad80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:06 -0600 Subject: board/mushu/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f91aa4a44050620e8540a2497ea33e408ebe084 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728714 Reviewed-by: Jeremy Bettis --- board/mushu/led.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/board/mushu/led.c b/board/mushu/led.c index a5d81fabd4..4763babb89 100644 --- a/board/mushu/led.c +++ b/board/mushu/led.c @@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 2759549bbd22c2ac8209268c53c44318d06f5ce0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:50 -0600 Subject: include/power/cannonlake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida78f8ac97660606ac5aafbfd15f3c2904b4972f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730384 Reviewed-by: Jeremy Bettis --- include/power/cannonlake.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/include/power/cannonlake.h b/include/power/cannonlake.h index a056a96ec8..20f282f398 100644 --- a/include/power/cannonlake.h +++ b/include/power/cannonlake.h @@ -9,18 +9,19 @@ #define __CROS_EC_CANNONLAKE_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK) -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) +#define IN_ALL_S0 \ + (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ + PP5000_PGOOD_POWER_SIGNAL_MASK) #define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED -- cgit v1.2.1 From 95e1b456f5df37fae764ca17002a8cbd2cfad31b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:03 -0600 Subject: test/kb_mkbp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iab1500d84b8863195526937760df55f7a215ba66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730481 Reviewed-by: Jeremy Bettis --- test/kb_mkbp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/kb_mkbp.c b/test/kb_mkbp.c index 3b191a47ac..7d73479382 100644 --- a/test/kb_mkbp.c +++ b/test/kb_mkbp.c @@ -19,7 +19,7 @@ static uint8_t state[KEYBOARD_COLS_MAX]; static int ec_int_level; -static const char *action[2] = {"release", "press"}; +static const char *action[2] = { "release", "press" }; /*****************************************************************************/ /* Mock functions */ @@ -43,7 +43,7 @@ int lid_is_open(void) /*****************************************************************************/ /* Test utilities */ -#define FIFO_EMPTY() (ec_int_level == 1) +#define FIFO_EMPTY() (ec_int_level == 1) #define FIFO_NOT_EMPTY() (ec_int_level == 0) void clear_state(void) @@ -71,7 +71,7 @@ int press_key(int c, int r, int pressed) int verify_key(int c, int r, int pressed) { struct host_cmd_handler_args args; - struct ec_response_get_next_event event; + struct ec_response_get_next_event event; int i; args.version = 0; @@ -104,7 +104,7 @@ int verify_key(int c, int r, int pressed) int verify_key_v2(int c, int r, int pressed, int expect_more) { struct host_cmd_handler_args args; - struct ec_response_get_next_event_v1 event; + struct ec_response_get_next_event_v1 event; int i; args.version = 2; -- cgit v1.2.1 From fb79964db3568eaa8285816f93fd3b9228654e17 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:06 -0600 Subject: board/osiris/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fe420d8eb4f5f249db112b60bc3d97989a83027 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728803 Reviewed-by: Jeremy Bettis --- board/osiris/sensors.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/osiris/sensors.c b/board/osiris/sensors.c index e02bee6a20..8c50a9514c 100644 --- a/board/osiris/sensors.c +++ b/board/osiris/sensors.c @@ -70,8 +70,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -84,9 +84,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; - -#define THERMAL_UNUSED \ - { \ +#define THERMAL_UNUSED \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = 0, \ [EC_TEMP_THRESH_HALT] = 0, \ -- cgit v1.2.1 From 09348e29a688ce005c69bed27e2159af90d36581 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:13 -0600 Subject: include/charge_manager.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8c102aac348d4bab2e4385d8b4add49f9ddbba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730220 Reviewed-by: Jeremy Bettis --- include/charge_manager.h | 47 +++++++++++++++++++++-------------------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/include/charge_manager.h b/include/charge_manager.h index e8e09798bf..a579674bb0 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -19,7 +19,7 @@ /* Only track BC1.2 charge current if we support BC1.2 charging */ #if defined(HAS_TASK_USB_CHG) || defined(HAS_TASK_USB_CHG_P0) || \ - defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) || \ + defined(CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK) || \ defined(TEST_BUILD) #define CHARGE_MANAGER_BC12 #endif @@ -28,7 +28,7 @@ * Time to delay for detecting the charger type (must be long enough for BC1.2 * driver to get supplier information and notify charge manager). */ -#define CHARGE_DETECT_DELAY (2*SECOND) +#define CHARGE_DETECT_DELAY (2 * SECOND) /* * Commonly-used charge suppliers listed in no particular order. @@ -60,14 +60,13 @@ enum charge_supplier { }; #ifdef CHARGE_MANAGER_BC12 -#define CHARGE_SUPPLIER_NAME_BC12 \ - [CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP", \ - [CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP", \ - [CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP", \ - [CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP", \ +#define CHARGE_SUPPLIER_NAME_BC12 \ + [CHARGE_SUPPLIER_BC12_DCP] = "BC12_DCP", \ + [CHARGE_SUPPLIER_BC12_CDP] = "BC12_CDP", \ + [CHARGE_SUPPLIER_BC12_SDP] = "BC12_SDP", \ + [CHARGE_SUPPLIER_PROPRIETARY] = "BC12_PROP", \ [CHARGE_SUPPLIER_TYPEC_UNDER_1_5A] = "USBC_U1_5A", \ - [CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", \ - [CHARGE_SUPPLIER_VBUS] = "VBUS", + [CHARGE_SUPPLIER_OTHER] = "BC12_OTHER", [CHARGE_SUPPLIER_VBUS] = "VBUS", #else #define CHARGE_SUPPLIER_NAME_BC12 #endif @@ -78,7 +77,7 @@ enum charge_supplier { #define CHARGE_SUPPLIER_NAME_DEDICATED #endif #ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 -#define CHARGE_SUPPLIER_NAME_QI \ +#define CHARGE_SUPPLIER_NAME_QI \ [CHARGE_SUPPLIER_WPC_BPP] = "QI_BPP", \ [CHARGE_SUPPLIER_WPC_EPP] = "QI_EPP", \ [CHARGE_SUPPLIER_WPC_GPP] = "QI_GPP", @@ -86,13 +85,11 @@ enum charge_supplier { #define CHARGE_SUPPLIER_NAME_QI #endif -#define CHARGE_SUPPLIER_NAME \ - [CHARGE_SUPPLIER_PD] = "PD", \ - [CHARGE_SUPPLIER_TYPEC] = "USBC", \ - [CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS", \ - CHARGE_SUPPLIER_NAME_BC12 \ - CHARGE_SUPPLIER_NAME_DEDICATED \ - CHARGE_SUPPLIER_NAME_QI +#define CHARGE_SUPPLIER_NAME \ + [CHARGE_SUPPLIER_PD] = "PD", [CHARGE_SUPPLIER_TYPEC] = "USBC", \ + [CHARGE_SUPPLIER_TYPEC_DTS] = "USBC_DTS", \ + CHARGE_SUPPLIER_NAME_BC12 CHARGE_SUPPLIER_NAME_DEDICATED \ + CHARGE_SUPPLIER_NAME_QI /* * Charge supplier priority: lower number indicates higher priority. @@ -114,8 +111,7 @@ struct charge_port_info { * @param charge Charge port current / voltage. If NULL, current = 0 * voltage = 0 will be used. */ -void charge_manager_update_charge(int supplier, - int port, +void charge_manager_update_charge(int supplier, int port, const struct charge_port_info *charge); /* Partner port dualrole capabilities */ @@ -152,8 +148,8 @@ enum ceil_requestor { CEIL_REQUESTOR_COUNT, }; -#define CHARGE_PORT_COUNT (CONFIG_USB_PD_PORT_MAX_COUNT + \ - CONFIG_DEDICATED_CHARGE_PORT_COUNT) +#define CHARGE_PORT_COUNT \ + (CONFIG_USB_PD_PORT_MAX_COUNT + CONFIG_DEDICATED_CHARGE_PORT_COUNT) #if (CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0) /** @@ -322,8 +318,8 @@ int board_set_active_charge_port(int charge_port); * @param max_ma Maximum charge current limit, >= charge_ma. * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv); +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv); /** * Get whether the port is sourcing power on VBUS. @@ -367,9 +363,8 @@ __override_proto int board_charge_port_is_connected(int port); * @param port Dedicated charge port. * @param r USB PD power info to be updated. */ -__override_proto -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r); +__override_proto void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r); /** * Board specific callback to get vbus voltage. -- cgit v1.2.1 From da32c377100a8fc585d7b6e73fac42a590b42d4b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:53 -0600 Subject: zephyr/shim/include/usbc/tcpci_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icdb71dc2d42379c9d5091869fc64854ff15fdb1b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730843 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpci_usb_mux.h | 49 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/zephyr/shim/include/usbc/tcpci_usb_mux.h b/zephyr/shim/include/usbc/tcpci_usb_mux.h index 9fa29c7c85..74a2fe8ffc 100644 --- a/zephyr/shim/include/usbc/tcpci_usb_mux.h +++ b/zephyr/shim/include/usbc/tcpci_usb_mux.h @@ -10,41 +10,40 @@ #include "tcpm/ps8xxx_public.h" #include "tcpm/tcpci.h" -#define TCPCI_TCPM_USB_MUX_COMPAT cros_ec_usbc_mux_tcpci -#define PS8XXX_USB_MUX_COMPAT parade_usbc_mux_ps8xxx +#define TCPCI_TCPM_USB_MUX_COMPAT cros_ec_usbc_mux_tcpci +#define PS8XXX_USB_MUX_COMPAT parade_usbc_mux_ps8xxx /** * Add I2C configuration and USB_MUX_FLAG_NOT_TCPC to enforce it when * mux_read()/mux_write() functions are used. */ -#define USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, \ - USB_MUX_FLAG_NOT_TCPC, \ - USB_MUX_FLAG_NOT_TCPC),\ - .driver = &tcpci_tcpm_usb_mux_driver, \ - .hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id, \ - hpd_update), \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, \ + USB_MUX_FLAG_NOT_TCPC, \ + USB_MUX_FLAG_NOT_TCPC), \ + .driver = &tcpci_tcpm_usb_mux_driver, \ + .hpd_update = \ + USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update), \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags), \ } /** Use I2C configuration from TCPC */ -#define USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &tcpci_tcpm_usb_mux_driver, \ - .hpd_update = USB_MUX_CALLBACK_OR_NULL(mux_id, \ - hpd_update), \ +#define USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &tcpci_tcpm_usb_mux_driver, \ + .hpd_update = \ + USB_MUX_CALLBACK_OR_NULL(mux_id, hpd_update), \ } /** This macro will fail if only port or i2c_addr_flags property is present */ -#define USB_MUX_CONFIG_TCPCI_TCPM(mux_id, port_id, idx) \ - COND_CODE_1(UTIL_OR(DT_NODE_HAS_PROP(mux_id, port), \ - DT_NODE_HAS_PROP(mux_id, i2c_addr_flags)), \ - (USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id,\ - idx)), \ - (USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id, \ - idx))) +#define USB_MUX_CONFIG_TCPCI_TCPM(mux_id, port_id, idx) \ + COND_CODE_1( \ + UTIL_OR(DT_NODE_HAS_PROP(mux_id, port), \ + DT_NODE_HAS_PROP(mux_id, i2c_addr_flags)), \ + (USB_MUX_CONFIG_TCPCI_TCPM_WITH_I2C(mux_id, port_id, idx)), \ + (USB_MUX_CONFIG_TCPCI_TCPM_WO_I2C(mux_id, port_id, idx))) #endif /* __ZEPHYR_SHIM_TCPCI_USB_MUX_H */ -- cgit v1.2.1 From 2f282bc3484775003c3706e8fae84a4979cbcb79 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:12 -0600 Subject: chip/mchp/dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4fa586d708d480813bafa46240fa9a0c3bf67d07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729288 Reviewed-by: Jeremy Bettis --- chip/mchp/dma.c | 74 +++++++++++++++++++++++---------------------------------- 1 file changed, 30 insertions(+), 44 deletions(-) diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c index 982dfa8122..2a99be3b41 100644 --- a/chip/mchp/dma.c +++ b/chip/mchp/dma.c @@ -15,7 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) +#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args) dma_chan_t *dma_get_channel(enum dma_channel channel) { @@ -23,7 +23,7 @@ dma_chan_t *dma_get_channel(enum dma_channel channel) if (channel < MCHP_DMAC_COUNT) { pd = (dma_chan_t *)(MCHP_DMA_BASE + MCHP_DMA_CH_OFS + - (channel << MCHP_DMA_CH_OFS_BITPOS)); + (channel << MCHP_DMA_CH_OFS_BITPOS)); } return pd; @@ -35,7 +35,7 @@ void dma_disable(enum dma_channel channel) if (MCHP_DMA_CH_CTRL(channel) & MCHP_DMA_RUN) MCHP_DMA_CH_CTRL(channel) &= ~(MCHP_DMA_RUN); - if (MCHP_DMA_CH_ACT(channel) & MCHP_DMA_ACT_EN) + if (MCHP_DMA_CH_ACT(channel) & MCHP_DMA_ACT_EN) MCHP_DMA_CH_ACT(channel) = 0; } } @@ -74,10 +74,9 @@ void dma_disable_all(void) * is the number of bytes to transfer memory start - memory end = count. */ static void prepare_channel(enum dma_channel ch, unsigned int count, - void *periph, void *memory, unsigned int flags) + void *periph, void *memory, unsigned int flags) { if (ch < MCHP_DMAC_COUNT) { - MCHP_DMA_CH_CTRL(ch) = 0; MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory; MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count; @@ -115,16 +114,14 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count, * Cast away const for memory pointer; this is ok because * we know we're preparing the channel for transmit. */ - prepare_channel(option->channel, count, option->periph, - (void *)memory, - MCHP_DMA_INC_MEM | - MCHP_DMA_TO_DEV | - MCHP_DMA_DEV(option->channel) | - option->flags); + prepare_channel( + option->channel, count, option->periph, (void *)memory, + MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV | + MCHP_DMA_DEV(option->channel) | option->flags); } void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count, - const void *memory, uint32_t dma_xfr_units) + const void *memory, uint32_t dma_xfr_units) { uint32_t nflags; @@ -136,23 +133,19 @@ void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count, * we know we're preparing the channel for transmit. */ prepare_channel(option->channel, count, option->periph, - (void *)memory, - MCHP_DMA_INC_MEM | - MCHP_DMA_TO_DEV | - MCHP_DMA_DEV(option->channel) | - nflags); + (void *)memory, + MCHP_DMA_INC_MEM | MCHP_DMA_TO_DEV | + MCHP_DMA_DEV(option->channel) | nflags); } } -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) +void dma_start_rx(const struct dma_option *option, unsigned count, void *memory) { if (option != NULL) { - prepare_channel(option->channel, count, option->periph, - memory, + prepare_channel(option->channel, count, option->periph, memory, MCHP_DMA_INC_MEM | - MCHP_DMA_DEV(option->channel) | - option->flags); + MCHP_DMA_DEV(option->channel) | + option->flags); dma_go_chan(option->channel); } } @@ -161,26 +154,21 @@ void dma_start_rx(const struct dma_option *option, unsigned count, * Configure and start DMA channel for read from device and write to * memory. Allow caller to override DMA transfer unit length. */ -void dma_xfr_start_rx(const struct dma_option *option, - uint32_t dma_xfr_ulen, - uint32_t count, void *memory) +void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen, + uint32_t count, void *memory) { uint32_t ch, ctrl; if (option != NULL) { ch = option->channel; if (ch < MCHP_DMAC_COUNT) { - MCHP_DMA_CH_CTRL(ch) = 0; MCHP_DMA_CH_MEM_START(ch) = (uint32_t)memory; - MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + - count; + MCHP_DMA_CH_MEM_END(ch) = (uint32_t)memory + count; - MCHP_DMA_CH_DEV_ADDR(ch) = - (uint32_t)option->periph; + MCHP_DMA_CH_DEV_ADDR(ch) = (uint32_t)option->periph; - ctrl = option->flags & - ~(MCHP_DMA_XFER_SIZE_MASK); + ctrl = option->flags & ~(MCHP_DMA_XFER_SIZE_MASK); ctrl |= MCHP_DMA_INC_MEM; ctrl |= MCHP_DMA_XFER_SIZE(dma_xfr_ulen); ctrl |= MCHP_DMA_DEV(option->channel); @@ -228,8 +216,8 @@ int dma_bytes_done_chan(enum dma_channel ch, uint32_t orig_count) if (ch < MCHP_DMAC_COUNT) if (MCHP_DMA_CH_CTRL(ch) & MCHP_DMA_RUN) cnt = (uint32_t)orig_count - - (MCHP_DMA_CH_MEM_END(ch) - - MCHP_DMA_CH_MEM_START(ch)); + (MCHP_DMA_CH_MEM_END(ch) - + MCHP_DMA_CH_MEM_START(ch)); return (int)cnt; } @@ -259,9 +247,7 @@ int dma_wait(enum dma_channel channel) deadline.val = get_time().val + DMA_TRANSFER_TIMEOUT_US; - while (!(MCHP_DMA_CH_ISTS(channel) & - MCHP_DMA_STS_DONE)) { - + while (!(MCHP_DMA_CH_ISTS(channel) & MCHP_DMA_STS_DONE)) { if (deadline.val <= get_time().val) return EC_ERROR_TIMEOUT; @@ -282,8 +268,8 @@ void dma_clear_isr(enum dma_channel channel) MCHP_DMA_CH_ISTS(channel) = 0x0f; } -void dma_cfg_buffers(enum dma_channel ch, const void *membuf, - uint32_t nb, const void *pdev) +void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb, + const void *pdev) { if (ch < MCHP_DMAC_COUNT) { MCHP_DMA_CH_MEM_START(ch) = (uint32_t)membuf; @@ -301,8 +287,8 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf, * b[2] = 1 increment device address * b[3] = disable HW flow control */ -void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, - uint8_t dev_id, uint8_t flags) +void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id, + uint8_t flags) { uint32_t ctrl; @@ -378,7 +364,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien) MCHP_DMA_CH_IEN(0) = 0; MCHP_DMA_CH_ISTS(0) = 0xff; MCHP_DMA_CH0_CRC32_EN = 1; - MCHP_DMA_CH0_CRC32_DATA = 0xfffffffful; + MCHP_DMA_CH0_CRC32_DATA = 0xfffffffful; /* program device address to point to read-only register */ MCHP_DMA_CH_DEV_ADDR(0) = (uint32_t)(MCHP_DMA_CH_BASE + 0x1c); MCHP_DMA_CH_MEM_START(0) = (uint32_t)mstart; @@ -387,7 +373,7 @@ int dma_crc32_start(const uint8_t *mstart, const uint32_t nbytes, int ien) MCHP_DMA_CH_IEN(0) = 0x07; MCHP_DMA_CH_ACT(0) = 1; MCHP_DMA_CH_CTRL(0) = MCHP_DMA_TO_DEV + MCHP_DMA_INC_MEM + - MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4); + MCHP_DMA_DIS_HW_FLOW + MCHP_DMA_XFER_SIZE(4); MCHP_DMA_CH_CTRL(0) |= MCHP_DMA_SW_GO; return EC_SUCCESS; } -- cgit v1.2.1 From eaab6467c060de80adf3bdb31d3a9528c898693a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:07 -0600 Subject: board/crota/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c296efbeeae209106369f16d7a934a35a2e51dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728193 Reviewed-by: Jeremy Bettis --- board/crota/fw_config.h | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/board/crota/fw_config.h b/board/crota/fw_config.h index f441650ec6..3f39fc0d97 100644 --- a/board/crota/fw_config.h +++ b/board/crota/fw_config.h @@ -14,10 +14,7 @@ * Source of truth is the project/brya/brya/config.star configuration file. */ -enum ec_cfg_usb_db_type { - DB_USB_ABSENT = 0, - DB_USB_ABSENT2 = 15 -}; +enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB_ABSENT2 = 15 }; enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, @@ -26,12 +23,12 @@ enum ec_cfg_keyboard_backlight_type { union brya_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; - uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From 423f800fd83798128fef8136ae46cb948c4e1501 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:33 -0600 Subject: common/i2c_hid_touchpad.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I74dc1b97fcf8478bf130c00470d3327df04d4ba7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729636 Reviewed-by: Jeremy Bettis --- common/i2c_hid_touchpad.c | 522 ++++++++++++++++++++++------------------------ 1 file changed, 250 insertions(+), 272 deletions(-) diff --git a/common/i2c_hid_touchpad.c b/common/i2c_hid_touchpad.c index 29122f83d6..1c467cd6f6 100644 --- a/common/i2c_hid_touchpad.c +++ b/common/i2c_hid_touchpad.c @@ -10,23 +10,23 @@ #include "util.h" /* 2 bytes for length + 1 byte for report ID */ -#define I2C_HID_HEADER_SIZE 3 +#define I2C_HID_HEADER_SIZE 3 /* Report ID */ -#define REPORT_ID_TOUCH 0x01 -#define REPORT_ID_MOUSE 0x02 -#define REPORT_ID_DEVICE_CAPS 0x0A -#define REPORT_ID_DEVICE_CERT 0x0B -#define REPORT_ID_INPUT_MODE 0x0C -#define REPORT_ID_REPORTING 0x0D +#define REPORT_ID_TOUCH 0x01 +#define REPORT_ID_MOUSE 0x02 +#define REPORT_ID_DEVICE_CAPS 0x0A +#define REPORT_ID_DEVICE_CERT 0x0B +#define REPORT_ID_INPUT_MODE 0x0C +#define REPORT_ID_REPORTING 0x0D -#define INPUT_MODE_MOUSE 0x00 -#define INPUT_MODE_TOUCH 0x03 +#define INPUT_MODE_MOUSE 0x00 +#define INPUT_MODE_TOUCH 0x03 /* VID/PID/FW version */ -#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) || \ - !defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \ - !defined(I2C_HID_TOUCHPAD_FW_VERSION) +#if !defined(I2C_HID_TOUCHPAD_VENDOR_ID) || \ + !defined(I2C_HID_TOUCHPAD_PRODUCT_ID) || \ + !defined(I2C_HID_TOUCHPAD_FW_VERSION) #error "Must define touchpad VID/PID/FW version" #endif /* @@ -34,10 +34,9 @@ * * Physical dimensions are in the unit of mms. */ -#if !defined(I2C_HID_TOUCHPAD_MAX_X) || \ - !defined(I2C_HID_TOUCHPAD_MAX_Y) || \ - !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) || \ - !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y) +#if !defined(I2C_HID_TOUCHPAD_MAX_X) || !defined(I2C_HID_TOUCHPAD_MAX_Y) || \ + !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_X) || \ + !defined(I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y) #error "Must define finger maximum X/Y and physical dimensions" #endif /* @@ -49,9 +48,9 @@ * different data ranges. It is therefore recommended for the user to check the * device's spec and set these values manually. */ -#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) || \ - !defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \ - !defined(I2C_HID_TOUCHPAD_MAX_PRESSURE) +#if !defined(I2C_HID_TOUCHPAD_MAX_WIDTH) || \ + !defined(I2C_HID_TOUCHPAD_MAX_HEIGHT) || \ + !defined(I2C_HID_TOUCHPAD_MAX_PRESSURE) #error "Must define finger maximum width/height/pressure" #endif /* @@ -67,42 +66,37 @@ * This is a bit similar to the mouse CPI and is used by mouse reports only. */ #if !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_X) || \ - !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y) + !defined(I2C_HID_TOUCHPAD_MOUSE_SCALE_Y) #error "Must define mouse horizontal/vertical scaling factors" #endif /* Helper bit-op macros */ -#define N_BITS(n) \ -( \ - (n) < (1 << 1) ? 1 : \ - (n) < (1 << 2) ? 2 : \ - (n) < (1 << 3) ? 3 : \ - (n) < (1 << 4) ? 4 : \ - (n) < (1 << 5) ? 5 : \ - (n) < (1 << 6) ? 6 : \ - (n) < (1 << 7) ? 7 : \ - (n) < (1 << 8) ? 8 : \ - (n) < (1 << 9) ? 9 : \ - (n) < (1 << 10) ? 10 : \ - (n) < (1 << 11) ? 11 : \ - (n) < (1 << 12) ? 12 : \ - (n) < (1 << 13) ? 13 : \ - (n) < (1 << 14) ? 14 : \ - (n) < (1 << 15) ? 15 : \ - 16 \ -) +#define N_BITS(n) \ + ((n) < (1 << 1) ? 1 : \ + (n) < (1 << 2) ? 2 : \ + (n) < (1 << 3) ? 3 : \ + (n) < (1 << 4) ? 4 : \ + (n) < (1 << 5) ? 5 : \ + (n) < (1 << 6) ? 6 : \ + (n) < (1 << 7) ? 7 : \ + (n) < (1 << 8) ? 8 : \ + (n) < (1 << 9) ? 9 : \ + (n) < (1 << 10) ? 10 : \ + (n) < (1 << 11) ? 11 : \ + (n) < (1 << 12) ? 12 : \ + (n) < (1 << 13) ? 13 : \ + (n) < (1 << 14) ? 14 : \ + (n) < (1 << 15) ? 15 : \ + 16) /* We would need to pad some bits at the end of each finger struct to match * the allocation unit's boundary so the array indexing may work correctly. */ -#define N_VAR_BITS \ -( \ - N_BITS(I2C_HID_TOUCHPAD_MAX_X) + \ - N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \ - N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) + \ - N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) + \ - N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) + \ - N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) \ -) +#define N_VAR_BITS \ + (N_BITS(I2C_HID_TOUCHPAD_MAX_X) + N_BITS(I2C_HID_TOUCHPAD_MAX_Y) + \ + N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH) + \ + N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT) + \ + N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE) + \ + N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION)) #define N_PADDING_BITS ((DIV_ROUND_UP(N_VAR_BITS, 8) * 8) - N_VAR_BITS) #define N_BITS_ORIENTATION \ (N_BITS(I2C_HID_TOUCHPAD_MAX_ORIENTATION) + N_PADDING_BITS) @@ -121,45 +115,45 @@ struct finger { * identify unintended contacts or palms but is up to the OS * explanation. */ - uint8_t confidence:1; + uint8_t confidence : 1; /* * Whether a finger is touching the surface (leaving/left finger gets * 0). */ - uint8_t tip:1; + uint8_t tip : 1; /* * Whether a finger is within the sensor range. For example, hovering * fingers would have tip=0 and inrange=1. */ - uint8_t inrange:1; + uint8_t inrange : 1; /* * Contact id. This is like slot numbers in Linux MT-B. */ - uint8_t id:5; - uint16_t x:N_BITS(I2C_HID_TOUCHPAD_MAX_X); - uint16_t y:N_BITS(I2C_HID_TOUCHPAD_MAX_Y); - uint16_t width:N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH); - uint16_t height:N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT); - uint16_t pressure:N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE); - uint16_t orientation:N_BITS_ORIENTATION; + uint8_t id : 5; + uint16_t x : N_BITS(I2C_HID_TOUCHPAD_MAX_X); + uint16_t y : N_BITS(I2C_HID_TOUCHPAD_MAX_Y); + uint16_t width : N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH); + uint16_t height : N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT); + uint16_t pressure : N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE); + uint16_t orientation : N_BITS_ORIENTATION; } __packed; struct touch_report { - uint8_t button:1; - uint8_t count:7; + uint8_t button : 1; + uint8_t count : 7; uint16_t timestamp; struct finger finger[I2C_HID_TOUCHPAD_MAX_FINGERS]; } __packed; struct mouse_report { - uint8_t button1:1; + uint8_t button1 : 1; /* Windows expects at least two button usages in a mouse report. Many * touchpads on the Chromebook are a single clickable surface, so * button2 isn't used. That said, we may later report a button2 event if * necessary. */ - uint8_t button2:1; - uint8_t unused:6; + uint8_t button2 : 1; + uint8_t unused : 6; int8_t x; int8_t y; } __packed; @@ -173,231 +167,215 @@ struct mouse_report { */ static const uint8_t report_desc[] = { /* Mouse Collection */ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ - 0x09, 0x02, /* Usage (Mouse) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_MOUSE, /* Report ID (Mouse) */ - 0x09, 0x01, /* Usage (Pointer) */ - 0xA1, 0x00, /* Collection (Physical) */ - 0x05, 0x09, /* Usage Page (Button) */ - 0x19, 0x01, /* Usage Minimum (Button 1) */ - 0x29, 0x02, /* Usage Maximum (Button 2) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x02, /* Report Count (2) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - 0x95, 0x06, /* Report Count (6) */ - 0x81, 0x03, /* Input (Cnst,Var,Abs) */ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ - 0x09, 0x30, /* Usage (X) */ - 0x09, 0x31, /* Usage (Y) */ - 0x15, 0x81, /* Logical Minimum (-127) */ - 0x25, 0x7F, /* Logical Maximum (127) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0x81, 0x06, /* Input (Data,Var,Rel) */ - 0xC0, /* End Collection */ - 0xC0, /* End Collection */ + 0x05, 0x01, /* Usage Page (Generic Desktop) */ + 0x09, 0x02, /* Usage (Mouse) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x85, REPORT_ID_MOUSE, /* Report ID (Mouse) */ + 0x09, 0x01, /* Usage (Pointer) */ + 0xA1, 0x00, /* Collection (Physical) */ + 0x05, 0x09, /* Usage Page (Button) */ + 0x19, 0x01, /* Usage Minimum (Button 1) */ + 0x29, 0x02, /* Usage Maximum (Button 2) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x02, /* Report Count (2) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x95, 0x06, /* Report Count (6) */ + 0x81, 0x03, /* Input (Cnst,Var,Abs) */ + 0x05, 0x01, /* Usage Page (Generic Desktop) */ + 0x09, 0x30, /* Usage (X) */ + 0x09, 0x31, /* Usage (Y) */ + 0x15, 0x81, /* Logical Minimum (-127) */ + 0x25, 0x7F, /* Logical Maximum (127) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x02, /* Report Count (2) */ + 0x81, 0x06, /* Input (Data,Var,Rel) */ + 0xC0, /* End Collection */ + 0xC0, /* End Collection */ /* Touchpad Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x05, /* Usage (Touch Pad) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_TOUCH, /* Report ID (Touch) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x05, /* Usage (Touch Pad) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x85, REPORT_ID_TOUCH, /* Report ID (Touch) */ /* Button */ - 0x05, 0x09, /* Usage Page (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x01, /* Usage Maximum (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x09, /* Usage Page (Button) */ + 0x19, 0x01, /* Usage Minimum (0x01) */ + 0x29, 0x01, /* Usage Maximum (0x01) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Contact count */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x54, /* Usage (Contact count) */ - 0x25, I2C_HID_TOUCHPAD_MAX_FINGERS, /* Logical Max. (MAX_FINGERS) */ - 0x75, 0x07, /* Report Size (7) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x54, /* Usage (Contact count) */ + 0x25, I2C_HID_TOUCHPAD_MAX_FINGERS, /* Logical Max. (MAX_FINGERS) */ + 0x75, 0x07, /* Report Size (7) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Scan time */ - 0x55, 0x0C, /* Unit Exponent (-4) */ - 0x66, 0x01, 0x10, /* Unit (Seconds) */ - 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ - 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ - 0x75, 0x10, /* Report Size (16) */ - 0x95, 0x01, /* Report Count (1) */ - 0x05, 0x0D, /* Usage Page (Digitizers) */ - 0x09, 0x56, /* Usage (Scan Time) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - -#define FINGER(FINGER_NUMBER) \ - /* Finger FINGER_NUMBER */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x22, /* Usage (Finger) */ \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x09, 0x47, /* Usage (Confidence) */ \ - 0x09, 0x42, /* Usage (Tip Switch) */ \ - 0x09, 0x32, /* Usage (In Range) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x03, /* Report Count (3) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x51, /* Usage (Contact identifier) */ \ - 0x25, 0x1F, /* Logical Maximum (31) */ \ - 0x75, 0x05, /* Report Size (5) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ - 0x09, 0x30, /* Usage (X) */ \ - 0x55, 0x0E, /* Unit Exponent (-2) */ \ - 0x65, 0x11, /* Unit (SI Linear, Length: cm) */ \ - 0x35, 0x00, /* Physical Minimum (0) */ \ - 0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X&0xff, \ - I2C_HID_TOUCHPAD_MAX_PHYSICAL_X>>8, \ - /* Physical Maximum */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_X&0xff, I2C_HID_TOUCHPAD_MAX_X>>8, \ - /* Logical Maximum */ \ - 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X), \ - /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x31, /* Usage (Y) */ \ - 0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y&0xff, \ - I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y>>8, \ - /* Physical Maximum */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_Y&0xff, I2C_HID_TOUCHPAD_MAX_Y>>8, \ - /* Logical Maximum */ \ - 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y), \ - /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x48, /* Usage (Width) */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_WIDTH&0xff, I2C_HID_TOUCHPAD_MAX_WIDTH>>8, \ - /* Logical Maximum */ \ - 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH), \ - /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x49, /* Usage (Height) */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT&0xff, I2C_HID_TOUCHPAD_MAX_HEIGHT>>8,\ - /* Logical Maximum */ \ - 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT), \ - /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x30, /* Usage (Tip pressure) */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE&0xff, \ - I2C_HID_TOUCHPAD_MAX_PRESSURE>>8, \ - /* Logical Maximum */ \ - 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE), \ - /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x3f, /* Usage (Azimuth Orientation) */ \ - 0x16, 0x00, 0x00, /* Logical Minimum (0) */ \ - 0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION&0xff, \ - I2C_HID_TOUCHPAD_MAX_ORIENTATION>>8, \ - /* Logical Maximum */ \ - 0x75, N_BITS_ORIENTATION, /* Report Size */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0xC0, /* End Collection */ - - FINGER(1) - FINGER(2) - FINGER(3) - FINGER(4) - FINGER(5) + 0x55, 0x0C, /* Unit Exponent (-4) */ + 0x66, 0x01, 0x10, /* Unit (Seconds) */ + 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ + 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ + 0x75, 0x10, /* Report Size (16) */ + 0x95, 0x01, /* Report Count (1) */ + 0x05, 0x0D, /* Usage Page (Digitizers) */ + 0x09, 0x56, /* Usage (Scan Time) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ + +#define FINGER(FINGER_NUMBER) \ + /* Finger FINGER_NUMBER */ \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ \ + 0x09, 0x22, /* Usage (Finger) */ \ + 0xA1, 0x02, /* Collection (Logical) */ \ + 0x09, 0x47, /* Usage (Confidence) */ \ + 0x09, 0x42, /* Usage (Tip Switch) */ \ + 0x09, 0x32, /* Usage (In Range) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x03, /* Report Count (3) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x51, /* Usage (Contact identifier) */ \ + 0x25, 0x1F, /* Logical Maximum (31) */ \ + 0x75, 0x05, /* Report Size (5) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ + 0x09, 0x30, /* Usage (X) */ \ + 0x55, 0x0E, /* Unit Exponent (-2) */ \ + 0x65, 0x11, /* Unit (SI Linear, Length: cm) */ \ + 0x35, 0x00, /* Physical Minimum (0) */ \ + 0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_X & 0xff, \ + I2C_HID_TOUCHPAD_MAX_PHYSICAL_X >> 8, /* Physical Maximum \ + */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_X & 0xff, \ + I2C_HID_TOUCHPAD_MAX_X >> 8, /* Logical Maximum */ \ + 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_X), /* Report Size */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x31, /* Usage (Y) */ \ + 0x46, I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y & 0xff, \ + I2C_HID_TOUCHPAD_MAX_PHYSICAL_Y >> 8, /* Physical Maximum \ + */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_Y & 0xff, \ + I2C_HID_TOUCHPAD_MAX_Y >> 8, /* Logical Maximum */ \ + 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_Y), /* Report Size */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ \ + 0x09, 0x48, /* Usage (Width) */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_WIDTH & 0xff, \ + I2C_HID_TOUCHPAD_MAX_WIDTH >> 8, /* Logical Maximum */ \ + 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_WIDTH), /* Report Size \ + */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x49, /* Usage (Height) */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_HEIGHT & 0xff, \ + I2C_HID_TOUCHPAD_MAX_HEIGHT >> 8, /* Logical Maximum */ \ + 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_HEIGHT), /* Report Size \ + */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x30, /* Usage (Tip pressure) */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_PRESSURE & 0xff, \ + I2C_HID_TOUCHPAD_MAX_PRESSURE >> 8, /* Logical Maximum */ \ + 0x75, N_BITS(I2C_HID_TOUCHPAD_MAX_PRESSURE), /* Report \ + Size */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x3f, /* Usage (Azimuth Orientation) */ \ + 0x16, 0x00, 0x00, /* Logical Minimum (0) */ \ + 0x26, I2C_HID_TOUCHPAD_MAX_ORIENTATION & 0xff, \ + I2C_HID_TOUCHPAD_MAX_ORIENTATION >> 8, /* Logical Maximum \ + */ \ + 0x75, N_BITS_ORIENTATION, /* Report Size */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0xC0, /* End Collection */ + + FINGER(1) FINGER(2) FINGER(3) FINGER(4) FINGER(5) #undef FINGER - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ - 0x09, 0x55, /* Usage (Contact Count Maximum) */ - 0x09, 0x59, /* Usage (Pad Type) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ - 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ - 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ - 0x75, 0x08, /* Report Size (8) */ - 0x96, 0x00, 0x01, /* Report Count (256) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - 0xC0, /* End Collection */ + 0x05, + 0x0D, /* Usage Page (Digitizer) */ + 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ + 0x09, 0x55, /* Usage (Contact Count Maximum) */ + 0x09, 0x59, /* Usage (Pad Type) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x02, /* Report Count (2) */ + 0x25, 0x0F, /* Logical Maximum (15) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ + 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ + 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ + 0x75, 0x08, /* Report Size (8) */ + 0x96, 0x00, 0x01, /* Report Count (256) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0xC0, /* End Collection */ /* Configuration Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x0E, /* Usage (Configuration) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_INPUT_MODE, /* Report ID (Input Mode) */ - 0x09, 0x22, /* Usage (Finger) */ - 0xA1, 0x02, /* Collection (Logical) */ - 0x09, 0x52, /* Usage (Input Mode) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x01, /* Report Count (1) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - 0xC0, /* End Collection */ - 0x09, 0x22, /* Usage (Finger) */ - 0xA1, 0x00, /* Collection (Physical) */ - 0x85, REPORT_ID_REPORTING, /* Report ID (Selective Reporting)*/ - 0x09, 0x57, /* Usage (Surface Switch) */ - 0x09, 0x58, /* Usage (Button Switch) */ - 0x75, 0x04, /* Report Size (4) */ - 0x95, 0x02, /* Report Count (2) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - 0xC0, /* End Collection */ - 0xC0, /* End Collection */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x0E, /* Usage (Configuration) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x85, REPORT_ID_INPUT_MODE, /* Report ID (Input Mode) */ + 0x09, 0x22, /* Usage (Finger) */ + 0xA1, 0x02, /* Collection (Logical) */ + 0x09, 0x52, /* Usage (Input Mode) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x0F, /* Logical Maximum (15) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x01, /* Report Count (1) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0xC0, /* End Collection */ + 0x09, 0x22, /* Usage (Finger) */ + 0xA1, 0x00, /* Collection (Physical) */ + 0x85, REPORT_ID_REPORTING, /* Report ID (Selective Reporting)*/ + 0x09, 0x57, /* Usage (Surface Switch) */ + 0x09, 0x58, /* Usage (Button Switch) */ + 0x75, 0x04, /* Report Size (4) */ + 0x95, 0x02, /* Report Count (2) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0xC0, /* End Collection */ + 0xC0, /* End Collection */ }; static const uint8_t device_caps[] = { - I2C_HID_TOUCHPAD_MAX_FINGERS, /* Contact Count Maximum */ - 0x00, /* Pad Type: Depressible click-pad */ + I2C_HID_TOUCHPAD_MAX_FINGERS, /* Contact Count Maximum */ + 0x00, /* Pad Type: Depressible click-pad */ }; /* A 256-byte default blob for the 'device certification status' feature report * expected by Windows. */ static const uint8_t device_cert[] = { - 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, - 0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88, - 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, - 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, - 0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43, - 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, - 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, - 0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71, - 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, - 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, - 0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9, - 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, - 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, - 0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B, - 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, - 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, - 0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1, - 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, - 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, - 0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35, - 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, - 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, - 0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF, - 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, - 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, - 0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13, - 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, - 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, - 0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89, - 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, - 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, - 0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2, + 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, 0x0D, 0xBE, 0x57, 0x3C, + 0xB6, 0x70, 0x09, 0x88, 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, + 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, 0x2E, 0x84, 0x1B, 0xE8, + 0xB4, 0x51, 0x78, 0x43, 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, + 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, 0xF3, 0x47, 0x18, 0x53, + 0x1A, 0xA2, 0xA1, 0x71, 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, + 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, 0x3E, 0xB3, 0xAF, 0x75, + 0x81, 0x9D, 0x53, 0xB9, 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, + 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, 0x9C, 0x65, 0x3B, 0x85, + 0x68, 0x89, 0xD7, 0x3B, 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, + 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, 0xC0, 0x8F, 0x33, 0x13, + 0x03, 0xF1, 0xD3, 0xC1, 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, + 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, 0xE8, 0x8A, 0x56, 0xF0, + 0x8C, 0xAA, 0xFA, 0x35, 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, + 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, 0x02, 0x38, 0x7C, 0x73, + 0xB6, 0x41, 0xE7, 0xFF, 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, + 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, 0x80, 0xE3, 0x0F, 0xBD, + 0x65, 0x20, 0x08, 0x13, 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, + 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, 0x1F, 0xFB, 0xDA, 0xAF, + 0xA2, 0xA8, 0x6A, 0x89, 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, + 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, 0x24, 0x8B, 0xC4, 0x43, + 0xA5, 0xE5, 0x24, 0xC2, }; #define MAX_SIZEOF(a, b) (sizeof(a) > sizeof(b) ? sizeof(a) : sizeof(b)) @@ -431,7 +409,7 @@ static bool pending_probe; static bool pending_reset; /* Reports (double buffered) */ -#define MAX_REPORT_CNT 2 +#define MAX_REPORT_CNT 2 static struct touch_report touch_reports[MAX_REPORT_CNT]; static struct mouse_report mouse_reports[MAX_REPORT_CNT]; @@ -448,8 +426,8 @@ static uint8_t input_mode; * |reporting.button_switch|, respectively. */ struct selective_reporting { - uint8_t surface_switch:4; - uint8_t button_switch:4; + uint8_t surface_switch : 4; + uint8_t button_switch : 4; } __packed; static struct selective_reporting reporting; @@ -568,7 +546,7 @@ int i2c_hid_touchpad_process(unsigned int len, uint8_t *buffer, break; case I2C_HID_COMMAND_REGISTER: *cmd = i2c_hid_touchpad_command_process(len, buffer, - send_response, data); + send_response, data); break; default: /* Unknown register has been received. */ @@ -697,9 +675,9 @@ void i2c_hid_compile_report(struct touchpad_event *event) touch->finger[i].pressure = event->finger[i].pressure; if (event->finger[i].is_palm) touch->finger[i].pressure = - I2C_HID_TOUCHPAD_MAX_PRESSURE; + I2C_HID_TOUCHPAD_MAX_PRESSURE; touch->finger[i].orientation = - event->finger[i].orientation; + event->finger[i].orientation; contact_num++; } else if (touch_old->finger[i].tip) { /* -- cgit v1.2.1 From 1365328b26c4b8766f1028100f6d58faa308278d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:24 -0600 Subject: zephyr/test/drivers/src/lis2dw12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4b56fa177d8811e3cea3849acfce13bc600a8b63 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730991 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/lis2dw12.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/zephyr/test/drivers/src/lis2dw12.c b/zephyr/test/drivers/src/lis2dw12.c index 56f71cc406..5def699088 100644 --- a/zephyr/test/drivers/src/lis2dw12.c +++ b/zephyr/test/drivers/src/lis2dw12.c @@ -109,8 +109,8 @@ ZTEST(lis2dw12, test_lis2dw12_init__timeout_read_soft_reset) } static int lis2dw12_test_mock_write_fail_set_bdu(struct i2c_emul *emul, int reg, - uint8_t val, int bytes, - void *data) + uint8_t val, int bytes, + void *data) { if (reg == LIS2DW12_BDU_ADDR && bytes == 1 && (val & LIS2DW12_BDU_MASK) != 0) { @@ -126,13 +126,13 @@ ZTEST(lis2dw12, test_lis2dw12_init__fail_set_bdu) int rv; i2c_common_emul_set_write_func(lis2dw12_emul_to_i2c_emul(emul), - lis2dw12_test_mock_write_fail_set_bdu, - NULL); + lis2dw12_test_mock_write_fail_set_bdu, + NULL); rv = ms->drv->init(ms); zassert_equal(EC_ERROR_INVAL, rv, "init returned %d but expected %d", rv, EC_ERROR_INVAL); zassert_true(lis2dw12_emul_get_soft_reset_count(emul) > 0, - "expected at least one soft reset"); + "expected at least one soft reset"); } ZTEST(lis2dw12, test_lis2dw12_init__fail_set_lir) @@ -425,8 +425,8 @@ ZTEST(lis2dw12, test_lis2dw12_read) * output */ - expected_sample[i] = fake_sample[i] * - (1 << (16 - LIS2DW12_RESOLUTION)); + expected_sample[i] = + fake_sample[i] * (1 << (16 - LIS2DW12_RESOLUTION)); } i2c_common_emul_set_read_fail_reg(i2c_emul, -- cgit v1.2.1 From b47dae1d98a0688691ba9d64f2310a0a7555b364 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:50 -0600 Subject: board/bugzzy/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c6652e21e1475ab43aef2a2c6f6bca4df39b457 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728110 Reviewed-by: Jeremy Bettis --- board/bugzzy/board.h | 85 +++++++++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 45 deletions(-) diff --git a/board/bugzzy/board.h b/board/bugzzy/board.h index 722375b34b..129e8baade 100644 --- a/board/bugzzy/board.h +++ b/board/bugzzy/board.h @@ -34,10 +34,11 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #define CONFIG_CHARGE_RAMP_HW -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) #define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS @@ -60,9 +61,8 @@ #define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL - /* PWM */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Thermistors */ #define CONFIG_TEMP_SENSOR @@ -97,23 +97,23 @@ #undef PD_POWER_SUPPLY_TURN_OFF_DELAY #undef CONFIG_USBC_VCONN_SWAP_DELAY_US /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 -#define I2C_PORT_LCD NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_LCD NPCX_I2C_PORT3_0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ #define I2C_ADDR_ISL98607_FLAGS 0x29 @@ -121,30 +121,30 @@ /* ISL98607 registers and value */ /* Enable VP / VN / VBST */ -#define ISL98607_REG_ENABLE 0x05 -#define ISL98607_VP_VN_VBST_EN 0x07 -#define ISL97607_VP_VN_VBST_DIS 0x00 +#define ISL98607_REG_ENABLE 0x05 +#define ISL98607_VP_VN_VBST_EN 0x07 +#define ISL97607_VP_VN_VBST_DIS 0x00 /* VBST Voltage Adjustment */ -#define ISL98607_REG_VBST_OUT 0x06 -#define ISL98607_VBST_OUT_5P65 0x0a +#define ISL98607_REG_VBST_OUT 0x06 +#define ISL98607_VBST_OUT_5P65 0x0a /* VN Voltage Adjustment */ -#define ISL98607_REG_VN_OUT 0x08 -#define ISL98607_VN_OUT_5P5 0x0a +#define ISL98607_REG_VN_OUT 0x08 +#define ISL98607_VN_OUT_5P5 0x0a /* VP Voltage Adjustment */ -#define ISL98607_REG_VP_OUT 0x09 -#define ISL98607_VP_OUT_5P5 0x0a +#define ISL98607_REG_VP_OUT 0x09 +#define ISL98607_VP_OUT_5P5 0x0a /* MP3372 registers and value */ /* ISET & CHEN */ -#define MP3372_REG_ISET_CHEN 0x00 -#define MP3372_ISET_21P8_CHEN_ALL 0x70ff -#define MP3372_ISET_19P4_CHEN_ALL 0x63ff -#define MP3372_ISET_18P0_CHEN_ALL 0x5cff -#define MP3372_ISET_15P8_CHEN_ALL 0x50ff -#define MP3372_ISET_15P3_CHEN_ALL 0x4eff +#define MP3372_REG_ISET_CHEN 0x00 +#define MP3372_ISET_21P8_CHEN_ALL 0x70ff +#define MP3372_ISET_19P4_CHEN_ALL 0x63ff +#define MP3372_ISET_18P0_CHEN_ALL 0x5cff +#define MP3372_ISET_15P8_CHEN_ALL 0x50ff +#define MP3372_ISET_15P3_CHEN_ALL 0x4eff /* * I2C pin names for baseboard * @@ -158,18 +158,18 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ /* Lid operates in forced mode, base in interrupt mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -204,21 +204,16 @@ enum temp_sensor_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC5 */ - ADC_TEMP_SENSOR_4, /* ADC6 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC5 */ + ADC_TEMP_SENSOR_4, /* ADC6 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 7a46aed15240d83409ff9435f23a2d5ef10831fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:00 -0600 Subject: test/usb_tcpmv2_td_pd_ll_e3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I51d1d412e90f8f82ec7baa288cf09d1c0a4a3e92 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730553 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_ll_e3.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_ll_e3.c b/test/usb_tcpmv2_td_pd_ll_e3.c index 46fbee393f..893a12cb71 100644 --- a/test/usb_tcpmv2_td_pd_ll_e3.c +++ b/test/usb_tcpmv2_td_pd_ll_e3.c @@ -29,8 +29,8 @@ static int td_pd_ll_e3(enum pd_data_role data_role) /* * a) Run PROC.PD.E1 Bring-up according to the UUT role. */ - TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), - EC_SUCCESS, "%d"); + TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS, + "%d"); /* * Make sure we are idle. Reject everything that is pending @@ -42,13 +42,11 @@ static int td_pd_ll_e3(enum pd_data_role data_role) * and do not send GoodCrc for nRetryCount + 1 times * (nRetryCount equals 3 since PD 2.1). */ - partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_GET_SINK_CAP, - 0, 0, NULL); + partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL); retries = (partner_get_pd_rev() == PD_REV30) ? 2 : 3; TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP, - retries), + retries), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_FAILED); -- cgit v1.2.1 From faf14bd705ede6db44e6886733757facff315df0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:44 -0600 Subject: common/backlight_lid.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I63feefb6ab735cb46788a89aeb3e57cfda74cc1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729566 Reviewed-by: Jeremy Bettis --- common/backlight_lid.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/common/backlight_lid.c b/common/backlight_lid.c index f0dd3b2e24..82bffaf383 100644 --- a/common/backlight_lid.c +++ b/common/backlight_lid.c @@ -11,7 +11,6 @@ #include "host_command.h" #include "lid_switch.h" - /** * Activate/Deactivate the backlight GPIO pin considering active high or low. */ @@ -32,7 +31,7 @@ static void update_backlight(void) #ifdef CONFIG_BACKLIGHT_REQ_GPIO /* Enable the backlight if lid is open AND requested by AP */ enable_backlight(lid_is_open() && - gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO)); + gpio_get_level(CONFIG_BACKLIGHT_REQ_GPIO)); #else /* * Enable backlight if lid is open; this is AND'd with the request from @@ -79,5 +78,4 @@ switch_command_enable_backlight(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT, - switch_command_enable_backlight, - EC_VER_MASK(0)); + switch_command_enable_backlight, EC_VER_MASK(0)); -- cgit v1.2.1 From 663e049241cfb0d67da72f2b70dbca76c9493e69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:04 -0600 Subject: board/helios/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I519ea23e2cf3dda4310aa828f66e97407b5438a5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728302 Reviewed-by: Jeremy Bettis --- board/helios/led.c | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/board/helios/led.c b/board/helios/led.c index 7a63c4401c..b95b745e5d 100644 --- a/board/helios/led.c +++ b/board/helios/led.c @@ -19,29 +19,37 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From ac1d8b5c7f0cafa6a355c7f57cc59f2586c7fb65 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:24 -0600 Subject: board/palkia/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib78d4da1ce226ab7b2ad277409e1710ead9d4afa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728810 Reviewed-by: Jeremy Bettis --- board/palkia/led.c | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/board/palkia/led.c b/board/palkia/led.c index df74a38d52..13059eee95 100644 --- a/board/palkia/led.c +++ b/board/palkia/led.c @@ -19,29 +19,37 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 62b99224a6b3887de71f2dbcc5665754e912f188 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:25 -0600 Subject: chip/stm32/config-stm32f05x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2e6b85d2271468945418250a462996136e470a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729470 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f05x.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/stm32/config-stm32f05x.h b/chip/stm32/config-stm32f05x.h index 00bf45fde5..918ae0f022 100644 --- a/chip/stm32/config-stm32f05x.h +++ b/chip/stm32/config-stm32f05x.h @@ -5,15 +5,15 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES (64 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00002000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 -- cgit v1.2.1 From 76cd4b94d76c529fe03ba8ddbcbaa783c14410d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:45 -0600 Subject: driver/ppc/rt1718s.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6d586013cc8c1ab0dea66a0e8bd31542265d239 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730034 Reviewed-by: Jeremy Bettis --- driver/ppc/rt1718s.c | 44 ++++++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c index a7a378d934..3bcb161e25 100644 --- a/driver/ppc/rt1718s.c +++ b/driver/ppc/rt1718s.c @@ -14,40 +14,33 @@ #include "usbc_ppc.h" #include "util.h" - #define RT1718S_FLAGS_SOURCE_ENABLED BIT(0) static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static int read_reg(uint8_t port, int reg, int *val) { if (reg > 0xFF) { - return i2c_read_offset16( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val, 1); + return i2c_read_offset16(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, + val, 1); } else { - return i2c_read8( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val); + return i2c_read8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, val); } } static int write_reg(uint8_t port, int reg, int val) { if (reg > 0xFF) { - return i2c_write_offset16( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val, 1); + return i2c_write_offset16(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, + val, 1); } else { - return i2c_write8( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val); + return i2c_write8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, val); } } @@ -75,11 +68,11 @@ static int rt1718s_vbus_source_enable(int port, int enable) atomic_t prev_flag; if (enable) - prev_flag = atomic_or(&flags[port], - RT1718S_FLAGS_SOURCE_ENABLED); + prev_flag = + atomic_or(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED); else prev_flag = atomic_clear_bits(&flags[port], - RT1718S_FLAGS_SOURCE_ENABLED); + RT1718S_FLAGS_SOURCE_ENABLED); /* Return if status doesn't change */ if (!!(prev_flag & RT1718S_FLAGS_SOURCE_ENABLED) == !!enable) @@ -105,10 +98,9 @@ static int rt1718s_vbus_sink_enable(int port, int enable) static int rt1718s_discharge_vbus(int port, int enable) { - return update_bits(port, - TCPC_REG_POWER_CTRL, - TCPC_REG_POWER_CTRL_FORCE_DISCHARGE, - enable ? 0xFF : 0x00); + return update_bits(port, TCPC_REG_POWER_CTRL, + TCPC_REG_POWER_CTRL_FORCE_DISCHARGE, + enable ? 0xFF : 0x00); } #ifdef CONFIG_CMD_PPC_DUMP -- cgit v1.2.1 From 8f472ada095afbdd83223a85350f980296cea716 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:48 -0600 Subject: board/stryke/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I51737c82e90b9d199ad04c6d2ebef6444189dd0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728961 Reviewed-by: Jeremy Bettis --- board/stryke/board.c | 64 ++++++++++++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 35 deletions(-) diff --git a/board/stryke/board.c b/board/stryke/board.c index 783f73a666..46a4176b46 100644 --- a/board/stryke/board.c +++ b/board/stryke/board.c @@ -41,8 +41,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO to enable/disable the USB Type-A port. */ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { @@ -108,16 +108,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -181,22 +181,18 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation * matrix can't be tested properly. This needs to be revisited after EVT to make * sure the rotaiton matrix for the lid sensor is correct. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -277,7 +273,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -296,32 +292,31 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Stryke Temperature sensors */ /* * TODO(b/124316213): These setting need to be reviewed and set appropriately @@ -331,8 +326,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -387,7 +382,6 @@ static void board_gpio_set_pp5000(void) } else if (board_id >= 1) { reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW); } - } static void board_init(void) -- cgit v1.2.1 From 16a62428d22bbaeccd4d0af0a57e64949b194b7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:36 -0600 Subject: core/host/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I495368f303e0cf44cab0ca27e97d1e4756c21830 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729842 Reviewed-by: Jeremy Bettis --- core/host/panic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/host/panic.c b/core/host/panic.c index 7b0829989d..e62e49c05e 100644 --- a/core/host/panic.c +++ b/core/host/panic.c @@ -11,8 +11,8 @@ void panic_assert_fail(const char *msg, const char *func, const char *fname, int linenum) { - fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n", - fname, linenum, func, msg); + fprintf(stderr, "ASSERTION FAIL: %s:%d:%s - %s\n", fname, linenum, func, + msg); task_dump_trace(); puts("Fail!"); /* Inform test runner */ -- cgit v1.2.1 From b9b09be371b6f05d1487c63a5f83c8235878f278 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:34 -0600 Subject: board/discovery-stm32f072/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If498e964fbc6a0f9975caf76280289308ddf12cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728247 Reviewed-by: Jeremy Bettis --- board/discovery-stm32f072/board.c | 81 +++++++++++++-------------------------- 1 file changed, 27 insertions(+), 54 deletions(-) diff --git a/board/discovery-stm32f072/board.c b/board/discovery-stm32f072/board.c index 086e5260a2..5932e9611d 100644 --- a/board/discovery-stm32f072/board.c +++ b/board/discovery-stm32f072/board.c @@ -28,31 +28,22 @@ void button_event(enum gpio_signal signal); #include "gpio_list.h" static enum gpio_signal const usb_gpio_list[] = { - GPIO_USER_BUTTON, - GPIO_LED_U, - GPIO_LED_D, - GPIO_LED_L, - GPIO_LED_R, + GPIO_USER_BUTTON, GPIO_LED_U, GPIO_LED_D, GPIO_LED_L, GPIO_LED_R, }; /* * This instantiates struct usb_gpio_config const usb_gpio, plus several other * variables, all named something beginning with usb_gpio_ */ -USB_GPIO_CONFIG(usb_gpio, - usb_gpio_list, - USB_IFACE_GPIO, - USB_EP_GPIO); +USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO); /****************************************************************************** * Setup USART1 as a loopback device, it just echo's back anything sent to it. */ static struct usart_config const loopback_usart; -static struct queue const loopback_queue = - QUEUE_DIRECT(64, uint8_t, - loopback_usart.producer, - loopback_usart.consumer); +static struct queue const loopback_queue = QUEUE_DIRECT( + 64, uint8_t, loopback_usart.producer, loopback_usart.consumer); static struct usart_rx_dma const loopback_rx_dma = USART_RX_DMA(STM32_DMAC_CH3, 8); @@ -60,14 +51,9 @@ static struct usart_rx_dma const loopback_rx_dma = static struct usart_tx_dma const loopback_tx_dma = USART_TX_DMA(STM32_DMAC_CH2, 16); -static struct usart_config const loopback_usart = - USART_CONFIG(usart1_hw, - loopback_rx_dma.usart_rx, - loopback_tx_dma.usart_tx, - 115200, - 0, - loopback_queue, - loopback_queue); +static struct usart_config const loopback_usart = USART_CONFIG( + usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200, + 0, loopback_queue, loopback_queue); /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -75,36 +61,24 @@ static struct usart_config const loopback_usart = static struct usart_config const forward_usart; struct usb_stream_config const forward_usb; -static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t, - forward_usart.producer, - forward_usb.consumer); -static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t, - forward_usb.producer, - forward_usart.consumer); +static struct queue const usart_to_usb = + QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer); +static struct queue const usb_to_usart = + QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer); static struct usart_tx_dma const forward_tx_dma = USART_TX_DMA(STM32_DMAC_CH7, 16); static struct usart_config const forward_usart = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - forward_tx_dma.usart_tx, - 115200, - 0, - usart_to_usb, - usb_to_usart); - -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 - -USB_STREAM_CONFIG(forward_usb, - USB_IFACE_STREAM, - USB_STR_STREAM_NAME, - USB_EP_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart, - usart_to_usb) + USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx, + 115200, 0, usart_to_usb, usb_to_usart); + +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 + +USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME, + USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart, usart_to_usb) /****************************************************************************** * Handle button presses by cycling the LEDs on the board. Also run a tick @@ -135,18 +109,17 @@ DECLARE_HOOK(HOOK_TICK, usb_gpio_tick, HOOK_PRIO_DEFAULT); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("discovery-stm32f072"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("discovery-stm32f072"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); - /****************************************************************************** * Support SPI bridging over USB, this requires usb_spi_board_enable and * usb_spi_board_disable to be defined to enable and disable the SPI bridge. @@ -154,7 +127,7 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); /* SPI devices */ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS}, + { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -- cgit v1.2.1 From 38325b5989b2f78621d6f8c938a1f8fffb20539f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:07 -0600 Subject: board/madoo/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd982e1a38b1447e4d66c0fe25adea1cb3990daf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728639 Reviewed-by: Jeremy Bettis --- board/madoo/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/madoo/cbi_ssfc.c b/board/madoo/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/madoo/cbi_ssfc.c +++ b/board/madoo/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 78e4df3faf712905af2b840a06f906dedcbb6079 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:00 -0600 Subject: zephyr/shim/include/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb245152b0305caceadb8f968737761f7751dcad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730563 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/atomic.h b/zephyr/shim/include/atomic.h index 6b44bf02a5..9b3d118910 100644 --- a/zephyr/shim/include/atomic.h +++ b/zephyr/shim/include/atomic.h @@ -13,4 +13,4 @@ static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits) return atomic_and(addr, ~bits); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 049dc7f6e09cc5f966e59fc9fc74b4c4ab3b6d70 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:24 -0600 Subject: board/magolor/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2f407ce7f5580300b10aaa55ab54b15cdb8f3f5f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728652 Reviewed-by: Jeremy Bettis --- board/magolor/cbi_ssfc.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/magolor/cbi_ssfc.h b/board/magolor/cbi_ssfc.h index f59d165071..2cb70172f6 100644 --- a/board/magolor/cbi_ssfc.h +++ b/board/magolor/cbi_ssfc.h @@ -45,12 +45,12 @@ union dedede_cbi_ssfc { struct { uint32_t base_sensor : 3; uint32_t lid_sensor : 3; - uint32_t cam_wfc: 3; - uint32_t cam_ufc: 2; - uint32_t cam_vcm: 2; - uint32_t TS_Source: 4; - uint32_t AUDIO_CODEC_SOURCE: 3; - uint32_t usb_mux: 2; + uint32_t cam_wfc : 3; + uint32_t cam_ufc : 2; + uint32_t cam_vcm : 2; + uint32_t TS_Source : 4; + uint32_t AUDIO_CODEC_SOURCE : 3; + uint32_t usb_mux : 2; uint32_t reserved_2 : 10; }; uint32_t raw_value; -- cgit v1.2.1 From cb23aff558411be6acd858cbdc85c16c8c08928c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:55 -0600 Subject: common/keyboard_mkbp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa947f79b6f39e510ccc5c6f550ff604a237aad5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729642 Reviewed-by: Jeremy Bettis --- common/keyboard_mkbp.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/common/keyboard_mkbp.c b/common/keyboard_mkbp.c index 51c17a5cee..f35e0ea7b9 100644 --- a/common/keyboard_mkbp.c +++ b/common/keyboard_mkbp.c @@ -21,7 +21,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) /* Changes to col,row here need to also be reflected in kernel. * drivers/input/mkbp.c ... see KEY_BATTERY. @@ -36,9 +36,9 @@ /* Config for mkbp protocol; does not include fields from scan config */ struct ec_mkbp_protocol_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; @@ -46,9 +46,10 @@ struct ec_mkbp_protocol_config { static struct ec_mkbp_protocol_config config = { .valid_mask = EC_MKBP_VALID_SCAN_PERIOD | EC_MKBP_VALID_POLL_TIMEOUT | - EC_MKBP_VALID_MIN_POST_SCAN_DELAY | - EC_MKBP_VALID_OUTPUT_SETTLE | EC_MKBP_VALID_DEBOUNCE_DOWN | - EC_MKBP_VALID_DEBOUNCE_UP | EC_MKBP_VALID_FIFO_MAX_DEPTH, + EC_MKBP_VALID_MIN_POST_SCAN_DELAY | + EC_MKBP_VALID_OUTPUT_SETTLE | + EC_MKBP_VALID_DEBOUNCE_DOWN | EC_MKBP_VALID_DEBOUNCE_UP | + EC_MKBP_VALID_FIFO_MAX_DEPTH, .valid_flags = EC_MKBP_FLAGS_ENABLE, .flags = EC_MKBP_FLAGS_ENABLE, .fifo_max_depth = FIFO_DEPTH, @@ -81,7 +82,8 @@ static int keyboard_get_next_event(uint8_t *out) DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_KEY_MATRIX, keyboard_get_next_event); void clear_typematic_key(void) -{ } +{ +} static void set_keyscan_config(const struct ec_mkbp_config *src, struct ec_mkbp_protocol_config *dst, @@ -119,7 +121,7 @@ static void set_keyscan_config(const struct ec_mkbp_config *src, * fall out of the task_wait_event() in keyboard_scan_task(). */ if ((new_flags & EC_MKBP_FLAGS_ENABLE) && - !(dst->flags & EC_MKBP_FLAGS_ENABLE)) + !(dst->flags & EC_MKBP_FLAGS_ENABLE)) task_wake(TASK_ID_KEYSCAN); } @@ -151,15 +153,14 @@ static void get_keyscan_config(struct ec_mkbp_config *dst) * over to dst->flags */ static void keyscan_copy_config(const struct ec_mkbp_config *src, - struct ec_mkbp_protocol_config *dst, - uint32_t valid_mask, uint8_t valid_flags) + struct ec_mkbp_protocol_config *dst, + uint32_t valid_mask, uint8_t valid_flags) { uint8_t new_flags; if (valid_mask & EC_MKBP_VALID_FIFO_MAX_DEPTH) { /* Validity check for fifo depth */ - dst->fifo_max_depth = MIN(src->fifo_max_depth, - FIFO_DEPTH); + dst->fifo_max_depth = MIN(src->fifo_max_depth, FIFO_DEPTH); } new_flags = dst->flags & ~valid_flags; @@ -182,8 +183,7 @@ host_command_mkbp_set_config(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG, - host_command_mkbp_set_config, +DECLARE_HOST_COMMAND(EC_CMD_MKBP_SET_CONFIG, host_command_mkbp_set_config, EC_VER_MASK(0)); static enum ec_status @@ -206,6 +206,5 @@ host_command_mkbp_get_config(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG, - host_command_mkbp_get_config, +DECLARE_HOST_COMMAND(EC_CMD_MKBP_GET_CONFIG, host_command_mkbp_get_config, EC_VER_MASK(0)); -- cgit v1.2.1 From 14178b862fdb35f14bb92301b24a2cc7e2e7e34b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:10 -0600 Subject: chip/it83xx/hwtimer_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I148fc2b4a4e53181070ebd65c79d100d70f939cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729198 Reviewed-by: Jeremy Bettis --- chip/it83xx/hwtimer_chip.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/chip/it83xx/hwtimer_chip.h b/chip/it83xx/hwtimer_chip.h index 2ccdce1d96..cced9a1490 100644 --- a/chip/it83xx/hwtimer_chip.h +++ b/chip/it83xx/hwtimer_chip.h @@ -8,17 +8,17 @@ #ifndef __CROS_EC_HWTIMER_CHIP_H #define __CROS_EC_HWTIMER_CHIP_H -#define TIMER_COUNT_1US_SHIFT 3 +#define TIMER_COUNT_1US_SHIFT 3 /* Microseconds to event timer counter setting register */ -#define EVENT_TIMER_US_TO_COUNT(us) ((us) << TIMER_COUNT_1US_SHIFT) +#define EVENT_TIMER_US_TO_COUNT(us) ((us) << TIMER_COUNT_1US_SHIFT) /* Event timer counter observation value to microseconds */ #define EVENT_TIMER_COUNT_TO_US(cnt) ((cnt) >> TIMER_COUNT_1US_SHIFT) -#define FREE_EXT_TIMER_L EXT_TIMER_3 -#define FREE_EXT_TIMER_H EXT_TIMER_4 -#define FAN_CTRL_EXT_TIMER EXT_TIMER_5 -#define EVENT_EXT_TIMER EXT_TIMER_6 +#define FREE_EXT_TIMER_L EXT_TIMER_3 +#define FREE_EXT_TIMER_H EXT_TIMER_4 +#define FAN_CTRL_EXT_TIMER EXT_TIMER_5 +#define EVENT_EXT_TIMER EXT_TIMER_6 /* * The low power timer is used to continue system time when EC goes into low * power in idle task. Timer 7 is 24bit timer and configured at 32.768khz. @@ -30,15 +30,15 @@ * mask of observation register in clock_sleep_mode_wakeup_isr() or EC will get * wrong system time after resume. */ -#define LOW_POWER_EXT_TIMER EXT_TIMER_7 +#define LOW_POWER_EXT_TIMER EXT_TIMER_7 #define LOW_POWER_TIMER_MASK (BIT(24) - 1) -#define WDT_EXT_TIMER EXT_TIMER_8 +#define WDT_EXT_TIMER EXT_TIMER_8 enum ext_timer_clock_source { EXT_PSR_32P768K_HZ = 0, - EXT_PSR_1P024K_HZ = 1, - EXT_PSR_32_HZ = 2, - EXT_PSR_8M_HZ = 3 + EXT_PSR_1P024K_HZ = 1, + EXT_PSR_32_HZ = 2, + EXT_PSR_8M_HZ = 3 }; /* @@ -83,11 +83,7 @@ void update_exc_start_time(void); * @param raw (!=0) timer count equal to param "ms" no conversion. */ int ext_timer_ms(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int et_int, - int32_t ms, - int first_time_enable, - int raw); + enum ext_timer_clock_source ext_timer_clock, int start, + int et_int, int32_t ms, int first_time_enable, int raw); #endif /* __CROS_EC_HWTIMER_CHIP_H */ -- cgit v1.2.1 From 5738e12ef4fa699c0b45a4bc310f934f35a3b5f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:05 -0600 Subject: include/stack_trace.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1cb296e34f00921c7e6539542891e51a7fde919f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730411 Reviewed-by: Jeremy Bettis --- include/stack_trace.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/include/stack_trace.h b/include/stack_trace.h index 52ebe3619f..5364fc7249 100644 --- a/include/stack_trace.h +++ b/include/stack_trace.h @@ -18,8 +18,12 @@ void task_register_tracedump(void); /* Dump current stack trace */ void task_dump_trace(void); #else -static inline void task_register_tracedump(void) { } -static inline void task_dump_trace(void) { } +static inline void task_register_tracedump(void) +{ +} +static inline void task_dump_trace(void) +{ +} #endif -#endif /* __CROS_EC_STACK_TRACE_H */ +#endif /* __CROS_EC_STACK_TRACE_H */ -- cgit v1.2.1 From 32653d57c955dd495bcf9f7cb1f359ecd85a9c82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:44 -0600 Subject: board/akemi/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia015a627f4984283fa5102bcc4e393019e47c431 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727977 Reviewed-by: Jeremy Bettis --- board/akemi/board.c | 87 +++++++++++++++++++++++++---------------------------- 1 file changed, 41 insertions(+), 46 deletions(-) diff --git a/board/akemi/board.c b/board/akemi/board.c index de5438344e..31fcf74828 100644 --- a/board/akemi/board.c +++ b/board/akemi/board.c @@ -43,8 +43,8 @@ #include "util.h" #include "battery_smart.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO to enable/disable the USB Type-A port. */ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { @@ -105,16 +105,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -177,17 +177,13 @@ static struct stprivate_data g_lis2dwl_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -267,13 +263,12 @@ struct motion_sensor_t motion_sensors[] = { }; unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); - /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -292,36 +287,35 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Temp3", - .type = TEMP_SENSOR_TYPE_CPU, - .read = g753_get_val, - .idx = 0}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Temp3", + .type = TEMP_SENSOR_TYPE_CPU, + .read = g753_get_val, + .idx = 0 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Hatch Temperature sensors */ /* * TODO(b/124316213): These setting need to be reviewed and set appropriately @@ -331,8 +325,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -391,12 +385,12 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) } /* Battery functions */ -#define SB_OPTIONALMFG_FUNCTION2 0x26 -#define QUICK_CHARGE_SUPPORT 0x01 -#define QUICK_CHARGE_ENABLE 0x02 +#define SB_OPTIONALMFG_FUNCTION2 0x26 +#define QUICK_CHARGE_SUPPORT 0x01 +#define QUICK_CHARGE_ENABLE 0x02 -#define SB_QUICK_CHARGE_ENABLE 1 -#define SB_QUICK_CHARGE_DISABLE 0 +#define SB_QUICK_CHARGE_ENABLE 1 +#define SB_QUICK_CHARGE_DISABLE 0 static void sb_quick_charge_mode(int enable) { @@ -422,7 +416,8 @@ static void board_chipset_startup(void) /* Normal charge current */ sb_quick_charge_mode(SB_QUICK_CHARGE_DISABLE); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, + HOOK_PRIO_INIT_I2C + 1); /* Called on AP S0 -> S5 transition */ static void board_chipset_shutdown(void) @@ -437,5 +432,5 @@ bool board_is_convertible(void) const uint8_t sku = get_board_sku(); return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 3) || - (sku == 4); + (sku == 4); } -- cgit v1.2.1 From 93142bec62db2159b55b68a3b123c9e48f2a3234 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:30 -0600 Subject: chip/stm32/usart_rx_dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I858a5a5eec5bdd3f89bf6e77e333f5206250707e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729545 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_dma.c | 45 +++++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/chip/stm32/usart_rx_dma.c b/chip/stm32/usart_rx_dma.c index c75ebdde41..043372f1a9 100644 --- a/chip/stm32/usart_rx_dma.c +++ b/chip/stm32/usart_rx_dma.c @@ -14,7 +14,7 @@ #include "util.h" typedef size_t (*add_data_t)(struct usart_config const *config, - const uint8_t *src, size_t count); + const uint8_t *src, size_t count); void usart_rx_dma_init(struct usart_config const *config) { @@ -25,10 +25,9 @@ void usart_rx_dma_init(struct usart_config const *config) struct dma_option options = { .channel = dma_config->channel, - .periph = (void *)&STM32_USART_RDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC), + .periph = (void *)&STM32_USART_RDR(base), + .flags = (STM32_DMA_CCR_MSIZE_8_BIT | + STM32_DMA_CCR_PSIZE_8_BIT | STM32_DMA_CCR_CIRC), }; if (IS_ENABLED(CHIP_FAMILY_STM32F4)) @@ -38,31 +37,29 @@ void usart_rx_dma_init(struct usart_config const *config) STM32_USART_CR1(base) |= STM32_USART_CR1_RE; STM32_USART_CR3(base) |= STM32_USART_CR3_DMAR; - dma_config->state->index = 0; + dma_config->state->index = 0; dma_config->state->max_bytes = 0; dma_start_rx(&options, dma_config->fifo_size, dma_config->fifo_buffer); } -static void usart_rx_dma_interrupt_common( - struct usart_config const *config, - add_data_t add_data) +static void usart_rx_dma_interrupt_common(struct usart_config const *config, + add_data_t add_data) { struct usart_rx_dma const *dma_config = DOWNCAST(config->rx, struct usart_rx_dma const, usart_rx); - dma_chan_t *channel = dma_get_channel(dma_config->channel); - size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); - size_t old_index = dma_config->state->index; - size_t new_bytes = 0; - size_t added = 0; + dma_chan_t *channel = dma_get_channel(dma_config->channel); + size_t new_index = dma_bytes_done(channel, dma_config->fifo_size); + size_t old_index = dma_config->state->index; + size_t new_bytes = 0; + size_t added = 0; if (new_index > old_index) { new_bytes = new_index - old_index; - added = add_data(config, - dma_config->fifo_buffer + old_index, - new_bytes); + added = add_data(config, dma_config->fifo_buffer + old_index, + new_bytes); } else if (new_index < old_index) { /* * Handle the case where the received bytes are not contiguous @@ -71,12 +68,9 @@ static void usart_rx_dma_interrupt_common( */ new_bytes = dma_config->fifo_size - (old_index - new_index); - added = add_data(config, - dma_config->fifo_buffer + old_index, - dma_config->fifo_size - old_index) + - add_data(config, - dma_config->fifo_buffer, - new_index); + added = add_data(config, dma_config->fifo_buffer + old_index, + dma_config->fifo_size - old_index) + + add_data(config, dma_config->fifo_buffer, new_index); } else { /* (new_index == old_index): nothing to add to the queue. */ } @@ -89,8 +83,8 @@ static void usart_rx_dma_interrupt_common( dma_config->state->index = new_index; } -static size_t queue_add(struct usart_config const *config, - const uint8_t *src, size_t count) +static size_t queue_add(struct usart_config const *config, const uint8_t *src, + size_t count) { return queue_add_units(config->producer.queue, (void *)src, count); } @@ -100,7 +94,6 @@ void usart_rx_dma_interrupt(struct usart_config const *config) usart_rx_dma_interrupt_common(config, &queue_add); } - #if defined(CONFIG_USART_HOST_COMMAND) void usart_host_command_rx_dma_interrupt(struct usart_config const *config) { -- cgit v1.2.1 From 76c403d69d4ebacd1943388f06645bc0d8c03b10 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:12 -0600 Subject: driver/led/lm3509.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee61ec091a98ab145b7fb73412dfe52b16c3070d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730014 Reviewed-by: Jeremy Bettis --- driver/led/lm3509.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/driver/led/lm3509.c b/driver/led/lm3509.c index fbd783a42e..46b520184d 100644 --- a/driver/led/lm3509.c +++ b/driver/led/lm3509.c @@ -12,22 +12,19 @@ static inline int lm3509_write(uint8_t reg, uint8_t val) { - return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, - reg, val); + return i2c_write8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val); } static inline int lm3509_read(uint8_t reg, int *val) { - return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, - reg, val); + return i2c_read8(I2C_PORT_KBLIGHT, LM3509_I2C_ADDR_FLAGS, reg, val); } /* Brightness level (0.0 to 100.0%) to brightness register conversion table */ static const uint16_t lm3509_brightness[32] = { - 0, 1, 6, 10, 11, 13, 16, 20, - 24, 28, 31, 37, 43, 52, 62, 75, - 87, 100, 125, 150, 168, 187, 225, 262, - 312, 375, 437, 525, 612, 700, 875, 1000 + 0, 1, 6, 10, 11, 13, 16, 20, 24, 28, 31, + 37, 43, 52, 62, 75, 87, 100, 125, 150, 168, 187, + 225, 262, 312, 375, 437, 525, 612, 700, 875, 1000 }; static int brightness_to_bmain(int percent) -- cgit v1.2.1 From 1f7cb1155b8045b58b23b47ce31504c63296b5e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:32 -0600 Subject: board/collis/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8bb3c710a41e7233d83a72c193e89fd0775b94b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728154 Reviewed-by: Jeremy Bettis --- board/collis/sensors.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/collis/sensors.c b/board/collis/sensors.c index cdf6db971e..91ead904a2 100644 --- a/board/collis/sensors.c +++ b/board/collis/sensors.c @@ -36,22 +36,18 @@ static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; const mat33_fp_t base_standard_ref_icm = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)}, + { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; struct motion_sensor_t icm426xx_base_accel = { -- cgit v1.2.1 From eaeb046284265ac37153a01865dcfc67ccb98f44 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:39 -0600 Subject: include/usb_pd_tcpm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12f359fbc1ee16f07a36536a2279ae171c6c6eec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730444 Reviewed-by: Jeremy Bettis --- include/usb_pd_tcpm.h | 82 +++++++++++++++++++++++++-------------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/include/usb_pd_tcpm.h b/include/usb_pd_tcpm.h index e34329eb18..29f27c655c 100644 --- a/include/usb_pd_tcpm.h +++ b/include/usb_pd_tcpm.h @@ -15,7 +15,7 @@ #include "i2c.h" /* Time to wait for TCPC to complete transmit */ -#define PD_T_TCPC_TX_TIMEOUT (100*MSEC) +#define PD_T_TCPC_TX_TIMEOUT (100 * MSEC) enum usbpd_cc_pin { USBPD_CC_PIN_1, @@ -25,8 +25,8 @@ enum usbpd_cc_pin { /* Detected resistor values of port partner */ enum tcpc_cc_voltage_status { TYPEC_CC_VOLT_OPEN = 0, - TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */ - TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */ + TYPEC_CC_VOLT_RA = 1, /* Port partner is applying Ra */ + TYPEC_CC_VOLT_RD = 2, /* Port partner is applying Rd */ TYPEC_CC_VOLT_RP_DEF = 5, /* Port partner is applying Rp (0.5A) */ TYPEC_CC_VOLT_RP_1_5 = 6, /* Port partner is applying Rp (1.5A) */ TYPEC_CC_VOLT_RP_3_0 = 7, /* Port partner is applying Rp (3.0A) */ @@ -42,7 +42,7 @@ enum tcpc_cc_pull { }; /* Pull-up values we apply as a SRC to advertise different current limits */ -FORWARD_DECLARE_ENUM(tcpc_rp_value) { +FORWARD_DECLARE_ENUM(tcpc_rp_value){ TYPEC_RP_USB = 0, TYPEC_RP_1A5 = 1, TYPEC_RP_3A0 = 2, @@ -58,8 +58,8 @@ enum tcpc_drp { /** * Returns whether the polarity without the DTS extension */ -static inline enum tcpc_cc_polarity polarity_rm_dts( - enum tcpc_cc_polarity polarity) +static inline enum tcpc_cc_polarity +polarity_rm_dts(enum tcpc_cc_polarity polarity) { BUILD_ASSERT(POLARITY_COUNT == 4); return (enum tcpc_cc_polarity)(polarity & BIT(0)); @@ -91,9 +91,9 @@ enum tcpci_msg_type { enum tcpc_transmit_complete { TCPC_TX_UNSET = -1, TCPC_TX_WAIT = 0, - TCPC_TX_COMPLETE_SUCCESS = 1, + TCPC_TX_COMPLETE_SUCCESS = 1, TCPC_TX_COMPLETE_DISCARDED = 2, - TCPC_TX_COMPLETE_FAILED = 3, + TCPC_TX_COMPLETE_FAILED = 3, }; /* @@ -102,9 +102,9 @@ enum tcpc_transmit_complete { * Return true on Vbus check if Vbus is... */ enum vbus_level { - VBUS_SAFE0V, /* less than vSafe0V max */ - VBUS_PRESENT, /* at least vSafe5V min */ - VBUS_REMOVED, /* less than vSinkDisconnect max */ + VBUS_SAFE0V, /* less than vSafe0V max */ + VBUS_PRESENT, /* at least vSafe5V min */ + VBUS_REMOVED, /* less than vSinkDisconnect max */ }; /** @@ -120,7 +120,7 @@ static inline int cc_is_rp(enum tcpc_cc_voltage_status cc) * Returns true if both CC lines are completely open. */ static inline int cc_is_open(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_OPEN && cc2 == TYPEC_CC_VOLT_OPEN; } @@ -129,7 +129,7 @@ static inline int cc_is_open(enum tcpc_cc_voltage_status cc1, * Returns true if we detect the port partner is a snk debug accessory. */ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD; } @@ -138,7 +138,7 @@ static inline int cc_is_snk_dbg_acc(enum tcpc_cc_voltage_status cc1, * Returns true if we detect the port partner is a src debug accessory. */ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc_is_rp(cc1) && cc_is_rp(cc2); } @@ -147,7 +147,7 @@ static inline int cc_is_src_dbg_acc(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is an audio accessory. */ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA; } @@ -156,7 +156,7 @@ static inline int cc_is_audio_acc(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is presenting at least one Rd */ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD; } @@ -165,7 +165,7 @@ static inline int cc_is_at_least_one_rd(enum tcpc_cc_voltage_status cc1, * Returns true if the port partner is presenting Rd on only one CC line. */ static inline int cc_is_only_one_rd(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return cc_is_at_least_one_rd(cc1, cc2) && cc1 != cc2; } @@ -200,7 +200,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*get_cc)(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level @@ -233,7 +233,8 @@ struct tcpm_drv { int (*select_rp_value)(int port, int rp); /** - * Set the CC pull resistor. This sets our role as either source or sink. + * Set the CC pull resistor. This sets our role as either source or + * sink. * * @param port Type-C port number * @param pull One of enum tcpc_cc_pull @@ -321,7 +322,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*transmit)(int port, enum tcpci_msg_type type, uint16_t header, - const uint32_t *data); + const uint32_t *data); /** * TCPC is asserting alert @@ -344,8 +345,7 @@ struct tcpm_drv { * @param port Type-C port number * @param enable Auto Discharge enable or disable */ - void (*tcpc_enable_auto_discharge_disconnect)(int port, - int enable); + void (*tcpc_enable_auto_discharge_disconnect)(int port, int enable); /** * Manual control of TCPC DebugAccessory enable @@ -384,7 +384,7 @@ struct tcpm_drv { * @return EC_SUCCESS or error */ int (*get_chip_info)(int port, int live, - struct ec_response_pd_chip_info_v1 *info); + struct ec_response_pd_chip_info_v1 *info); /** * Request current sinking state of the TCPC @@ -478,7 +478,7 @@ struct tcpm_drv { * * @return EC_SUCCESS or error */ - int (*set_frs_enable)(int port, int enable); + int (*set_frs_enable)(int port, int enable); #endif /** @@ -489,7 +489,7 @@ struct tcpm_drv { * * @return EC_SUCCESS or error */ - int (*handle_fault)(int port, int fault); + int (*handle_fault)(int port, int fault); /** * Controls BIST Test Mode (or analogous functionality) in the TCPC and @@ -500,7 +500,7 @@ struct tcpm_drv { * @param enable true to enter BIST Test Mode; false to exit * @return EC_SUCCESS or error code */ - enum ec_error_list (*set_bist_test_mode)(int port, bool enable); + enum ec_error_list (*set_bist_test_mode)(int port, bool enable); #ifdef CONFIG_CMD_TCPC_DUMP /** @@ -508,7 +508,7 @@ struct tcpm_drv { * * @param port Type-C port number */ - void (*dump_registers)(int port); + void (*dump_registers)(int port); #endif /* defined(CONFIG_CMD_TCPC_DUMP) */ int (*reset_bist_type_2)(int port); @@ -534,20 +534,20 @@ struct tcpm_drv { * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off) * Bit 8 --> TCPC enable VBUS monitoring */ -#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) -#define TCPC_FLAGS_ALERT_OD BIT(1) -#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) -#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) -#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) -#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) -#define TCPC_FLAGS_CONTROL_VCONN BIT(6) -#define TCPC_FLAGS_CONTROL_FRS BIT(7) -#define TCPC_FLAGS_VBUS_MONITOR BIT(8) +#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) +#define TCPC_FLAGS_ALERT_OD BIT(1) +#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) +#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) +#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) +#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) +#define TCPC_FLAGS_CONTROL_VCONN BIT(6) +#define TCPC_FLAGS_CONTROL_FRS BIT(7) +#define TCPC_FLAGS_VBUS_MONITOR BIT(8) #endif /* !CONFIG_ZEPHYR */ struct tcpc_config_t { - enum ec_bus_type bus_type; /* enum ec_bus_type */ + enum ec_bus_type bus_type; /* enum ec_bus_type */ union { struct i2c_info_t i2c_info; }; @@ -632,9 +632,9 @@ int tcpc_get_vbus_voltage(int port); #ifdef CONFIG_CMD_TCPC_DUMP struct tcpc_reg_dump_map { - uint8_t addr; - uint8_t size; - const char *name; + uint8_t addr; + uint8_t size; + const char *name; }; /** @@ -654,6 +654,6 @@ void tcpc_dump_std_registers(int port); * */ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg, - int count); + int count); #endif #endif /* __CROS_EC_USB_PD_TCPM_H */ -- cgit v1.2.1 From 933d0ffd5f3f8412eb43fb83210318b4effdddeb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:06 -0600 Subject: zephyr/shim/src/hooks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I07259ed91e6218ec9c6266eb04df30991a276bd0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730895 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/hooks.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/src/hooks.c b/zephyr/shim/src/hooks.c index 07bf27f3b0..392f046c85 100644 --- a/zephyr/shim/src/hooks.c +++ b/zephyr/shim/src/hooks.c @@ -23,21 +23,20 @@ * this code must manually generate references to the symbols generated by * STRUCT_SECTION_ITERABLE_ALTERNATE in zephyr_hooks_shim.h. */ -#define HOOK_LIST_EXTERNS(type) \ - extern const struct zephyr_shim_hook_info \ +#define HOOK_LIST_EXTERNS(type) \ + extern const struct zephyr_shim_hook_info \ _zephyr_shim_hook_##type##_list_start[]; \ - extern const struct zephyr_shim_hook_info \ + extern const struct zephyr_shim_hook_info \ _zephyr_shim_hook_##type##_list_end[]; FOR_EACH(HOOK_LIST_EXTERNS, (), HOOK_TYPES_LIST) -#define HOOK_LIST_ENTRY(type) \ - [type] = { \ +#define HOOK_LIST_ENTRY(type) \ + [type] = { \ .start = _zephyr_shim_hook_##type##_list_start, \ .end = _zephyr_shim_hook_##type##_list_end, \ } -static const struct zephyr_shim_hook_list hook_registry[] = { - FOR_EACH(HOOK_LIST_ENTRY, (,), HOOK_TYPES_LIST) -}; +static const struct zephyr_shim_hook_list hook_registry[] = { FOR_EACH( + HOOK_LIST_ENTRY, (, ), HOOK_TYPES_LIST) }; BUILD_ASSERT(ARRAY_SIZE(hook_registry) == HOOK_TYPE_COUNT, "All defined hook types must be represented in hook_registry"); BUILD_ASSERT(NUM_VA_ARGS_LESS_1(HOOK_TYPES_LIST) + 1 == HOOK_TYPE_COUNT, -- cgit v1.2.1 From ad6fa9658ca0c027e24ef1f6a0d6dc76fece711b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:07 -0600 Subject: include/lightbar_opcode_list.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib5d61199137fb32b6642269acd5909ec99b7c8b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730305 Reviewed-by: Jeremy Bettis --- include/lightbar_opcode_list.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/include/lightbar_opcode_list.h b/include/lightbar_opcode_list.h index 5d75feb459..340b740b3f 100644 --- a/include/lightbar_opcode_list.h +++ b/include/lightbar_opcode_list.h @@ -6,21 +6,21 @@ */ /* NAME OPERAND BYTES MNEMONIC*/ -#define LIGHTBAR_OPCODE_TABLE \ - OP(ON, 0, "on" )\ - OP(OFF, 0, "off" )\ - OP(JUMP, 1, "jump" )\ - OP(JUMP_BATTERY, 2, "jbat" )\ - OP(JUMP_IF_CHARGING, 1, "jcharge" )\ - OP(SET_WAIT_DELAY, 4, "delay.w" )\ - OP(SET_RAMP_DELAY, 4, "delay.r" )\ - OP(WAIT, 0, "wait" )\ - OP(SET_BRIGHTNESS, 1, "bright" )\ - OP(SET_COLOR_SINGLE, 2, "set.1" )\ - OP(SET_COLOR_RGB, 4, "set.rgb" )\ - OP(GET_COLORS, 0, "get" )\ - OP(SWAP_COLORS, 0, "swap" )\ - OP(RAMP_ONCE, 0, "ramp.1" )\ - OP(CYCLE_ONCE, 0, "cycle.1" )\ - OP(CYCLE, 0, "cycle" )\ - OP(HALT, 0, "halt" ) +#define LIGHTBAR_OPCODE_TABLE \ + OP(ON, 0, "on") \ + OP(OFF, 0, "off") \ + OP(JUMP, 1, "jump") \ + OP(JUMP_BATTERY, 2, "jbat") \ + OP(JUMP_IF_CHARGING, 1, "jcharge") \ + OP(SET_WAIT_DELAY, 4, "delay.w") \ + OP(SET_RAMP_DELAY, 4, "delay.r") \ + OP(WAIT, 0, "wait") \ + OP(SET_BRIGHTNESS, 1, "bright") \ + OP(SET_COLOR_SINGLE, 2, "set.1") \ + OP(SET_COLOR_RGB, 4, "set.rgb") \ + OP(GET_COLORS, 0, "get") \ + OP(SWAP_COLORS, 0, "swap") \ + OP(RAMP_ONCE, 0, "ramp.1") \ + OP(CYCLE_ONCE, 0, "cycle.1") \ + OP(CYCLE, 0, "cycle") \ + OP(HALT, 0, "halt") -- cgit v1.2.1 From 443f0dfcca04e5c870a55094ad5a387b7563e1ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:01 -0600 Subject: board/adlrvpp_mchp1521/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7bf7d0939d66f0443aa4d93d61c591759754a45c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727965 Reviewed-by: Jeremy Bettis --- board/adlrvpp_mchp1521/board.h | 99 +++++++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 50 deletions(-) diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h index a76fbd87df..3867cab1a1 100644 --- a/board/adlrvpp_mchp1521/board.h +++ b/board/adlrvpp_mchp1521/board.h @@ -24,77 +24,76 @@ * which purpose. */ /* Power sequencing */ -#define GPIO_EC_SPI_OE_N GPIO_EC_PCH_SPI_OE_N -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC_N -#define GPIO_PCH_SLP_S0_L GPIO_PM_SLP_S0_R_N -#define GPIO_PG_EC_DSW_PWROK GPIO_EC_TRACE_DATA_2 -#define GPIO_VCCST_PWRGD GPIO_EC_TRACE_DATA_3 -#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_N -#define GPIO_SYS_RESET_L GPIO_DG2_PRESENT -#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_R -#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_R -#define GPIO_EN_PP3300_A GPIO_EC_DS3_R -#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK_EC_R -#define GPIO_PCH_DSW_PWROK GPIO_EC_TRACE_DATA_1 +#define GPIO_EC_SPI_OE_N GPIO_EC_PCH_SPI_OE_N +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC_N +#define GPIO_PCH_SLP_S0_L GPIO_PM_SLP_S0_R_N +#define GPIO_PG_EC_DSW_PWROK GPIO_EC_TRACE_DATA_2 +#define GPIO_VCCST_PWRGD GPIO_EC_TRACE_DATA_3 +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_N +#define GPIO_SYS_RESET_L GPIO_DG2_PRESENT +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_R +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_R +#define GPIO_EN_PP3300_A GPIO_EC_DS3_R +#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK_EC_R +#define GPIO_PCH_DSW_PWROK GPIO_EC_TRACE_DATA_1 /* Buttons */ -#define GPIO_LID_OPEN GPIO_SMC_LID -#define GPIO_VOLUME_UP_L GPIO_VOL_UP_EC -#define GPIO_VOLUME_DOWN_L GPIO_VOL_DOWN_EC -#define GPIO_POWER_BUTTON_L GPIO_PWRBTN_EC_IN_N +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_VOLUME_UP_L GPIO_VOL_UP_EC +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DOWN_EC +#define GPIO_POWER_BUTTON_L GPIO_PWRBTN_EC_IN_N /* Sensors */ -#define GPIO_TABLET_MODE_L GPIO_EC_SLATEMODE_HALLOUT_SNSR_R -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_R +#define GPIO_TABLET_MODE_L GPIO_EC_SLATEMODE_HALLOUT_SNSR_R +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_R /* AC & Battery */ -#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT_EC -#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC_IN -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_ID_R +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT_EC +#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC_IN +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_ID_R /* eSPI/Host communication */ -#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_EC_R_N -#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N -#define GPIO_EC_INT_L GPIO_EC_TRACE_DATA_0 +#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_EC_R_N +#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N +#define GPIO_EC_INT_L GPIO_EC_TRACE_DATA_0 /* H1 */ -#define GPIO_WP_L GPIO_EC_WAKE_CLK_R -#define GPIO_PACKET_MODE_EN GPIO_EC_TRACE_CLK -#define GPIO_ENTERING_RW GPIO_DNX_FORCE_RELOAD_EC_R +#define GPIO_WP_L GPIO_EC_WAKE_CLK_R +#define GPIO_PACKET_MODE_EN GPIO_EC_TRACE_CLK +#define GPIO_ENTERING_RW GPIO_DNX_FORCE_RELOAD_EC_R /* FAN */ -#define GPIO_FAN_POWER_EN GPIO_FAN_PWR_DISABLE +#define GPIO_FAN_POWER_EN GPIO_FAN_PWR_DISABLE /* LEDs */ -#define GPIO_BAT_LED_RED_L GPIO_PM_BAT_STATUS_LED2 -#define GPIO_PWR_LED_WHITE_L GPIO_PM_PWRBTN_LED +#define GPIO_BAT_LED_RED_L GPIO_PM_BAT_STATUS_LED2 +#define GPIO_PWR_LED_WHITE_L GPIO_PM_PWRBTN_LED /* Uart */ -#define GPIO_UART2_RX GPIO_EC_UART_RX +#define GPIO_UART2_RX GPIO_EC_UART_RX /* Case Closed Debug Mode interrupt */ -#define GPIO_CCD_MODE_ODL GPIO_KBC_NUMLOCK +#define GPIO_CCD_MODE_ODL GPIO_KBC_NUMLOCK /* USB-C interrupts */ -#define GPIO_USBC_TCPC_ALRT_P0 GPIO_TYPEC_EC_SMBUS_ALERT_0_R -#define GPIO_USBC_TCPC_ALRT_P1 GPIO_TYPEC_EC_SMBUS_ALERT_1_R -#define GPIO_USBC_TCPC_PPC_ALRT_P0 GPIO_KBC_SCANOUT_15 -#define GPIO_USBC_TCPC_PPC_ALRT_P1 GPIO_KBC_CAPSLOCK - +#define GPIO_USBC_TCPC_ALRT_P0 GPIO_TYPEC_EC_SMBUS_ALERT_0_R +#define GPIO_USBC_TCPC_ALRT_P1 GPIO_TYPEC_EC_SMBUS_ALERT_1_R +#define GPIO_USBC_TCPC_PPC_ALRT_P0 GPIO_KBC_SCANOUT_15 +#define GPIO_USBC_TCPC_PPC_ALRT_P1 GPIO_KBC_CAPSLOCK /* I2C ports & Configs */ /* Charger */ -#define I2C_PORT_CHARGER MCHP_I2C_PORT0 +#define I2C_PORT_CHARGER MCHP_I2C_PORT0 /* Port 80 */ -#define I2C_PORT_PORT80 MCHP_I2C_PORT0 +#define I2C_PORT_PORT80 MCHP_I2C_PORT0 /* Board ID */ -#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0 +#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0 /* Battery */ -#define I2C_PORT_BATTERY MCHP_I2C_PORT0 +#define I2C_PORT_BATTERY MCHP_I2C_PORT0 /* USB-C I2C */ -#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT1 -#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT5 +#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT1 +#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT5 /* * MEC1521H loads firmware using QMSPI controller @@ -109,8 +108,8 @@ * is of size 512KB. This bin is then later appended with 0xFF to become 32MB * binary for flashing purpose. */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) -#define CONFIG_SPI_FLASH_W25X40 /* TODO: change to W25R256 */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_SPI_FLASH_W25X40 /* TODO: change to W25R256 */ /* ADC channels */ /* @@ -122,10 +121,10 @@ #undef ADC_TEMP_SNS_DDR_CHANNEL #undef ADC_TEMP_SNS_SKIN_CHANNEL -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH5 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH6 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH7 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH4 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH5 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH6 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH7 /* To do: Remove once fan register details are added in mchp/fan.c */ #undef CONFIG_FANS -- cgit v1.2.1 From 06e4f16aadac6b65fa63563c0f7a749adbcfee0f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:45 -0600 Subject: board/vell/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4240d2a735ad17ce417103a18608270a877fa172 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729044 Reviewed-by: Jeremy Bettis --- board/vell/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/vell/fans.c b/board/vell/fans.c index fb2b29f502..c1a778627d 100644 --- a/board/vell/fans.c +++ b/board/vell/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From eddc05fcaeebc2a2fdafd4bf8f922c6d5313092a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:45 -0600 Subject: board/boten/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6150a630c1f95faf34342b5c7eec024878cbe3bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728089 Reviewed-by: Jeremy Bettis --- board/boten/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/boten/cbi_ssfc.h b/board/boten/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/boten/cbi_ssfc.h +++ b/board/boten/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 32ba2e038074e48b58a8947d69da68c223bb0384 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:32 -0600 Subject: board/waddledoo2/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2c0a818b8c8a94f019ee861e7219dcd561fbad5e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729103 Reviewed-by: Jeremy Bettis --- board/waddledoo2/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledoo2/cbi_ssfc.c b/board/waddledoo2/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/waddledoo2/cbi_ssfc.c +++ b/board/waddledoo2/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 621d08aac954b783a754c1b2232eb4ff24198fca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:50 -0600 Subject: zephyr/test/drivers/src/tcs3400.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaeb138fa1a9f5c4962a7fd5e960e53bdefd2bbbf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730978 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/tcs3400.c | 115 ++++++++++++++++++-------------------- 1 file changed, 53 insertions(+), 62 deletions(-) diff --git a/zephyr/test/drivers/src/tcs3400.c b/zephyr/test/drivers/src/tcs3400.c index 66955481f7..33c476c4d1 100644 --- a/zephyr/test/drivers/src/tcs3400.c +++ b/zephyr/test/drivers/src/tcs3400.c @@ -16,14 +16,14 @@ #include "driver/als_tcs3400.h" #include "test/drivers/test_state.h" -#define TCS_ORD DT_DEP_ORD(DT_NODELABEL(tcs_emul)) -#define TCS_CLR_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_clear)) -#define TCS_RGB_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_rgb)) -#define TCS_INT_EVENT \ +#define TCS_ORD DT_DEP_ORD(DT_NODELABEL(tcs_emul)) +#define TCS_CLR_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_clear)) +#define TCS_RGB_SENSOR_ID SENSOR_ID(DT_NODELABEL(tcs3400_rgb)) +#define TCS_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int))) /** How accurate comparision of rgb sensors should be */ -#define V_EPS 8 +#define V_EPS 8 /** Test initialization of light sensor driver and device */ ZTEST_USER(tcs3400, test_tcs_init) @@ -52,8 +52,8 @@ ZTEST_USER(tcs3400, test_tcs_init) /* Test successful init. ATIME and AGAIN should be changed on init */ zassert_equal(EC_SUCCESS, ms->drv->init(ms), NULL); - zassert_equal(TCS_DEFAULT_ATIME, - tcs_emul_get_reg(emul, TCS_I2C_ATIME), NULL); + zassert_equal(TCS_DEFAULT_ATIME, tcs_emul_get_reg(emul, TCS_I2C_ATIME), + NULL); zassert_equal(TCS_DEFAULT_AGAIN, tcs_emul_get_reg(emul, TCS_I2C_CONTROL), NULL); } @@ -132,8 +132,7 @@ static void check_fifo_empty_f(struct motion_sensor_t *ms, } } } -#define check_fifo_empty(ms, ms_rgb) \ - check_fifo_empty_f(ms, ms_rgb, __LINE__) +#define check_fifo_empty(ms, ms_rgb) check_fifo_empty_f(ms, ms_rgb, __LINE__) /** * Test different conditions where irq handler fail or commit no data @@ -179,12 +178,12 @@ ZTEST_USER(tcs3400, test_tcs_irq_handler_fail) * expected value. */ static void check_fifo_f(struct motion_sensor_t *ms, - struct motion_sensor_t *ms_rgb, - int *exp_v, int eps, int line) + struct motion_sensor_t *ms_rgb, int *exp_v, int eps, + int line) { struct ec_response_motion_sensor_data vector; uint16_t size; - int ret_v[4] = {-1, -1, -1, -1}; + int ret_v[4] = { -1, -1, -1, -1 }; int i; /* Read all data committed to FIFO */ @@ -217,13 +216,14 @@ static void check_fifo_f(struct motion_sensor_t *ms, /* Compare with last committed data */ for (i = 0; i < 4; i++) { - zassert_within(exp_v[i], ret_v[i], eps, + zassert_within( + exp_v[i], ret_v[i], eps, "Expected [%d; %d; %d; %d], got [%d; %d; %d; %d]; line: %d", - exp_v[0], exp_v[1], exp_v[2], exp_v[3], - ret_v[0], ret_v[1], ret_v[2], ret_v[3], line); + exp_v[0], exp_v[1], exp_v[2], exp_v[3], ret_v[0], + ret_v[1], ret_v[2], ret_v[3], line); } } -#define check_fifo(ms, ms_rgb, exp_v, eps) \ +#define check_fifo(ms, ms_rgb, exp_v, eps) \ check_fifo_f(ms, ms_rgb, exp_v, eps, __LINE__) /** Test calibration mode reading of light sensor values */ @@ -346,23 +346,17 @@ ZTEST_USER(tcs3400, test_tcs_read_xyz) uint32_t event = TCS_INT_EVENT; /* Expected data to test: IR, R, G, B */ int exp_v[][4] = { - {200, 1110, 870, 850}, - {300, 1110, 10000, 8500}, - {600, 50000, 40000, 30000}, - {1000, 3000, 40000, 2000}, - {1000, 65000, 65000, 65000}, - {100, 214, 541, 516}, - {143, 2141, 5414, 5163}, - {100, 50000, 40000, 30000}, - {1430, 2141, 5414, 5163}, - {10000, 50000, 40000, 30000}, - {10000, 214, 541, 516}, - {15000, 50000, 40000, 30000}, - }; - uint16_t scale[4] = { - MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE + { 200, 1110, 870, 850 }, { 300, 1110, 10000, 8500 }, + { 600, 50000, 40000, 30000 }, { 1000, 3000, 40000, 2000 }, + { 1000, 65000, 65000, 65000 }, { 100, 214, 541, 516 }, + { 143, 2141, 5414, 5163 }, { 100, 50000, 40000, 30000 }, + { 1430, 2141, 5414, 5163 }, { 10000, 50000, 40000, 30000 }, + { 10000, 214, 541, 516 }, { 15000, 50000, 40000, 30000 }, }; + uint16_t scale[4] = { MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE }; int i, test; intv3_t v; @@ -424,34 +418,32 @@ ZTEST_USER(tcs3400, test_tcs_scale) uint32_t event = TCS_INT_EVENT; /* Expected data to test: IR, R, G, B */ int exp_v[][4] = { - {200, 1110, 870, 850}, - {300, 1110, 10000, 8500}, - {600, 5000, 4000, 3000}, - {100, 3000, 4000, 2000}, - {100, 1000, 1000, 1000}, + { 200, 1110, 870, 850 }, { 300, 1110, 10000, 8500 }, + { 600, 5000, 4000, 3000 }, { 100, 3000, 4000, 2000 }, + { 100, 1000, 1000, 1000 }, }; /* Scale for each test */ uint16_t exp_scale[][4] = { - {MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE}, - {MOTION_SENSE_DEFAULT_SCALE + 300, - MOTION_SENSE_DEFAULT_SCALE + 300, - MOTION_SENSE_DEFAULT_SCALE + 300, - MOTION_SENSE_DEFAULT_SCALE + 300}, - {MOTION_SENSE_DEFAULT_SCALE - 300, - MOTION_SENSE_DEFAULT_SCALE - 300, - MOTION_SENSE_DEFAULT_SCALE - 300, - MOTION_SENSE_DEFAULT_SCALE - 300}, - {MOTION_SENSE_DEFAULT_SCALE + 345, - MOTION_SENSE_DEFAULT_SCALE - 5423, - MOTION_SENSE_DEFAULT_SCALE - 30, - MOTION_SENSE_DEFAULT_SCALE + 400}, - {MOTION_SENSE_DEFAULT_SCALE - 345, - MOTION_SENSE_DEFAULT_SCALE + 5423, - MOTION_SENSE_DEFAULT_SCALE + 30, - MOTION_SENSE_DEFAULT_SCALE - 400}, - {MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE} + { MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE }, + { MOTION_SENSE_DEFAULT_SCALE + 300, + MOTION_SENSE_DEFAULT_SCALE + 300, + MOTION_SENSE_DEFAULT_SCALE + 300, + MOTION_SENSE_DEFAULT_SCALE + 300 }, + { MOTION_SENSE_DEFAULT_SCALE - 300, + MOTION_SENSE_DEFAULT_SCALE - 300, + MOTION_SENSE_DEFAULT_SCALE - 300, + MOTION_SENSE_DEFAULT_SCALE - 300 }, + { MOTION_SENSE_DEFAULT_SCALE + 345, + MOTION_SENSE_DEFAULT_SCALE - 5423, + MOTION_SENSE_DEFAULT_SCALE - 30, + MOTION_SENSE_DEFAULT_SCALE + 400 }, + { MOTION_SENSE_DEFAULT_SCALE - 345, + MOTION_SENSE_DEFAULT_SCALE + 5423, + MOTION_SENSE_DEFAULT_SCALE + 30, + MOTION_SENSE_DEFAULT_SCALE - 400 }, + { MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, MOTION_SENSE_DEFAULT_SCALE } }; uint16_t scale[3]; int16_t temp; @@ -476,16 +468,16 @@ ZTEST_USER(tcs3400, test_tcs_scale) zassert_equal(EC_SUCCESS, ms->drv->set_scale(ms, exp_scale[test], 0), "test %d", test); - zassert_equal(EC_SUCCESS, - ms->drv->get_scale(ms, scale, &temp), + zassert_equal(EC_SUCCESS, ms->drv->get_scale(ms, scale, &temp), "test %d", test); zassert_equal((int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, temp, "test %d, %d", test, temp); zassert_equal(exp_scale[test][0], scale[0], "test %d", test); /* Set and test RGB sensor scale */ - zassert_equal(EC_SUCCESS, ms_rgb->drv->set_scale(ms_rgb, - &(exp_scale[test][1]), 0), + zassert_equal(EC_SUCCESS, + ms_rgb->drv->set_scale(ms_rgb, + &(exp_scale[test][1]), 0), "test %d", test); zassert_equal(EC_SUCCESS, ms_rgb->drv->get_scale(ms_rgb, scale, &temp), @@ -560,7 +552,6 @@ ZTEST_USER(tcs3400, test_tcs_data_rate) zassert_equal(0, ms->drv->get_data_rate(ms), NULL); zassert_equal(0, ms_rgb->drv->get_data_rate(ms_rgb), NULL); - /* Test setting non-zero rate enables device */ zassert_equal(EC_SUCCESS, ms->drv->set_data_rate(ms, 100, 0), NULL); enable = tcs_emul_get_reg(emul, TCS_I2C_ENABLE); -- cgit v1.2.1 From 5f041c9b261d361734866cf21e8f568fdf254d61 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:46 -0600 Subject: board/goroh/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I05eead0650a1bc28275fe3164472f578d7309008 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728427 Reviewed-by: Jeremy Bettis --- board/goroh/board.c | 58 ++++++++++++++++++++++++----------------------------- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/board/goroh/board.c b/board/goroh/board.c index c99b0deff6..116b579f95 100644 --- a/board/goroh/board.c +++ b/board/goroh/board.c @@ -41,9 +41,9 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Initialize board. */ static void board_init(void) @@ -55,41 +55,35 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, - { "TEMP_CPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, - { "TEMP_GPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3 }, + { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, + { "TEMP_CPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, + { "TEMP_GPU", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH3 }, { "TEMP_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* PWM channels. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_GREEN] = { - .channel = PWM_HW_CH_DCR0, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN | - PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, - [PWM_CH_LED_RED] = { - .channel = PWM_HW_CH_DCR1, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN | - PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, - [PWM_CH_FAN] = { - .channel = PWM_HW_CH_DCR2, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq_hz = 25000, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, - [PWM_CH_KBLIGHT] = { - .channel = PWM_HW_CH_DCR3, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 25000, - .pcfsr_sel = PWM_PRESCALER_C4 - }, + [PWM_CH_LED_GREEN] = { .channel = PWM_HW_CH_DCR0, + .flags = PWM_CONFIG_DSLEEP | + PWM_CONFIG_OPEN_DRAIN | + PWM_CONFIG_ACTIVE_LOW, + .freq_hz = 324, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, + [PWM_CH_LED_RED] = { .channel = PWM_HW_CH_DCR1, + .flags = PWM_CONFIG_DSLEEP | + PWM_CONFIG_OPEN_DRAIN | + PWM_CONFIG_ACTIVE_LOW, + .freq_hz = 324, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, + [PWM_CH_FAN] = { .channel = PWM_HW_CH_DCR2, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq_hz = 25000, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, + [PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR3, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 25000, + .pcfsr_sel = PWM_PRESCALER_C4 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From e5a22bea324645b008eb07a8b42f8b60d54fd2e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:09 -0600 Subject: driver/charger/rt9490.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15e0d52c3bb057a9ad0485864805fac04f921292 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729940 Reviewed-by: Jeremy Bettis --- driver/charger/rt9490.h | 320 ++++++++++++++++++++++++------------------------ 1 file changed, 160 insertions(+), 160 deletions(-) diff --git a/driver/charger/rt9490.h b/driver/charger/rt9490.h index 2fd0edbac2..80afb65274 100644 --- a/driver/charger/rt9490.h +++ b/driver/charger/rt9490.h @@ -9,71 +9,71 @@ #ifndef __CROS_EC_RT9490_H #define __CROS_EC_RT9490_H -#define RT9490_ADDR_FLAGS 0x53 +#define RT9490_ADDR_FLAGS 0x53 /* Registers */ -#define RT9490_REG_SYS_MIN_REGU 0x00 -#define RT9490_REG_VCHG_CTRL 0x01 -#define RT9490_REG_ICHG_CTRL 0x03 -#define RT9490_REG_MIVR_CTRL 0x05 -#define RT9490_REG_AICR_CTRL 0x06 -#define RT9490_REG_PRE_CHG 0x08 -#define RT9490_REG_EOC_CTRL 0x09 -#define RT9490_REG_RECHG 0x0A -#define RT9490_REG_VOTG_REGU 0x0B -#define RT9490_REG_IOTG_REGU 0x0D -#define RT9490_REG_SAFETY_TMR_CTRL 0x0E -#define RT9490_REG_CHG_CTRL0 0x0F -#define RT9490_REG_CHG_CTRL1 0x10 -#define RT9490_REG_CHG_CTRL2 0x11 -#define RT9490_REG_CHG_CTRL3 0x12 -#define RT9490_REG_CHG_CTRL4 0x13 -#define RT9490_REG_CHG_CTRL5 0x14 -#define RT9490_REG_THREG_CTRL 0x16 -#define RT9490_REG_JEITA_CTRL0 0x17 -#define RT9490_REG_JEITA_CTRL1 0x18 -#define RT9490_REG_AICC_CTRL 0x19 -#define RT9490_REG_CHG_STATUS0 0x1B -#define RT9490_REG_CHG_STATUS1 0x1C -#define RT9490_REG_CHG_STATUS2 0x1D -#define RT9490_REG_CHG_STATUS3 0x1E -#define RT9490_REG_CHG_STATUS4 0x1F -#define RT9490_REG_FAULT_STATUS0 0x20 -#define RT9490_REG_FAULT_STATUS1 0x21 -#define RT9490_REG_CHG_IRQ_FLAG0 0x22 -#define RT9490_REG_CHG_IRQ_FLAG1 0x23 -#define RT9490_REG_CHG_IRQ_FLAG2 0x24 -#define RT9490_REG_CHG_IRQ_FLAG3 0x25 -#define RT9490_REG_CHG_IRQ_FLAG4 0x26 -#define RT9490_REG_CHG_IRQ_FLAG5 0x27 -#define RT9490_REG_CHG_IRQ_MASK0 0x28 -#define RT9490_REG_CHG_IRQ_MASK1 0x29 -#define RT9490_REG_CHG_IRQ_MASK2 0x2A -#define RT9490_REG_CHG_IRQ_MASK3 0x2B -#define RT9490_REG_CHG_IRQ_MASK4 0x2C -#define RT9490_REG_CHG_IRQ_MASK5 0x2D -#define RT9490_REG_ADC_CTRL 0x2E -#define RT9490_REG_ADC_CHANNEL0 0x2F -#define RT9490_REG_ADC_CHANNEL1 0x30 -#define RT9490_REG_IBUS_ADC 0x31 -#define RT9490_REG_IBAT_ADC 0x33 -#define RT9490_REG_VBUS_ADC 0x35 -#define RT9490_REG_VAC1_ADC 0x37 -#define RT9490_REG_VAC2_ADC 0x39 -#define RT9490_REG_VBAT_ADC 0x3B -#define RT9490_REG_VSYS_ADC 0x3D -#define RT9490_REG_TS_ADC 0x3F -#define RT9490_REG_TDIE_ADC 0x41 -#define RT9490_REG_DP_ADC 0x43 -#define RT9490_REG_DM_ADC 0x45 -#define RT9490_REG_DPDM_MANU_CTRL 0x47 -#define RT9490_REG_DEVICE_INFO 0x48 -#define RT9490_REG_PUMP_EXP 0x49 -#define RT9490_REG_ADD_CTRL0 0x4A -#define RT9490_REG_ADD_CTRL1 0x4B -#define RT9490_REG_ADD_CTRL2 0x4C -#define RT9490_REG_ADD_IRQ_FLAG 0x4D -#define RT9490_REG_ADD_IRQ_MASK6 0x4E +#define RT9490_REG_SYS_MIN_REGU 0x00 +#define RT9490_REG_VCHG_CTRL 0x01 +#define RT9490_REG_ICHG_CTRL 0x03 +#define RT9490_REG_MIVR_CTRL 0x05 +#define RT9490_REG_AICR_CTRL 0x06 +#define RT9490_REG_PRE_CHG 0x08 +#define RT9490_REG_EOC_CTRL 0x09 +#define RT9490_REG_RECHG 0x0A +#define RT9490_REG_VOTG_REGU 0x0B +#define RT9490_REG_IOTG_REGU 0x0D +#define RT9490_REG_SAFETY_TMR_CTRL 0x0E +#define RT9490_REG_CHG_CTRL0 0x0F +#define RT9490_REG_CHG_CTRL1 0x10 +#define RT9490_REG_CHG_CTRL2 0x11 +#define RT9490_REG_CHG_CTRL3 0x12 +#define RT9490_REG_CHG_CTRL4 0x13 +#define RT9490_REG_CHG_CTRL5 0x14 +#define RT9490_REG_THREG_CTRL 0x16 +#define RT9490_REG_JEITA_CTRL0 0x17 +#define RT9490_REG_JEITA_CTRL1 0x18 +#define RT9490_REG_AICC_CTRL 0x19 +#define RT9490_REG_CHG_STATUS0 0x1B +#define RT9490_REG_CHG_STATUS1 0x1C +#define RT9490_REG_CHG_STATUS2 0x1D +#define RT9490_REG_CHG_STATUS3 0x1E +#define RT9490_REG_CHG_STATUS4 0x1F +#define RT9490_REG_FAULT_STATUS0 0x20 +#define RT9490_REG_FAULT_STATUS1 0x21 +#define RT9490_REG_CHG_IRQ_FLAG0 0x22 +#define RT9490_REG_CHG_IRQ_FLAG1 0x23 +#define RT9490_REG_CHG_IRQ_FLAG2 0x24 +#define RT9490_REG_CHG_IRQ_FLAG3 0x25 +#define RT9490_REG_CHG_IRQ_FLAG4 0x26 +#define RT9490_REG_CHG_IRQ_FLAG5 0x27 +#define RT9490_REG_CHG_IRQ_MASK0 0x28 +#define RT9490_REG_CHG_IRQ_MASK1 0x29 +#define RT9490_REG_CHG_IRQ_MASK2 0x2A +#define RT9490_REG_CHG_IRQ_MASK3 0x2B +#define RT9490_REG_CHG_IRQ_MASK4 0x2C +#define RT9490_REG_CHG_IRQ_MASK5 0x2D +#define RT9490_REG_ADC_CTRL 0x2E +#define RT9490_REG_ADC_CHANNEL0 0x2F +#define RT9490_REG_ADC_CHANNEL1 0x30 +#define RT9490_REG_IBUS_ADC 0x31 +#define RT9490_REG_IBAT_ADC 0x33 +#define RT9490_REG_VBUS_ADC 0x35 +#define RT9490_REG_VAC1_ADC 0x37 +#define RT9490_REG_VAC2_ADC 0x39 +#define RT9490_REG_VBAT_ADC 0x3B +#define RT9490_REG_VSYS_ADC 0x3D +#define RT9490_REG_TS_ADC 0x3F +#define RT9490_REG_TDIE_ADC 0x41 +#define RT9490_REG_DP_ADC 0x43 +#define RT9490_REG_DM_ADC 0x45 +#define RT9490_REG_DPDM_MANU_CTRL 0x47 +#define RT9490_REG_DEVICE_INFO 0x48 +#define RT9490_REG_PUMP_EXP 0x49 +#define RT9490_REG_ADD_CTRL0 0x4A +#define RT9490_REG_ADD_CTRL1 0x4B +#define RT9490_REG_ADD_CTRL2 0x4C +#define RT9490_REG_ADD_IRQ_FLAG 0x4D +#define RT9490_REG_ADD_IRQ_MASK6 0x4E struct rt9490_init_setting { int eoc_current; @@ -83,164 +83,164 @@ struct rt9490_init_setting { }; /* CV */ -#define RT9490_CV_MASK 0x7FF -#define RT9490_CV_MIN 3000 -#define RT9490_CV_MAX 18800 -#define RT9490_CV_STEP 10 +#define RT9490_CV_MASK 0x7FF +#define RT9490_CV_MIN 3000 +#define RT9490_CV_MAX 18800 +#define RT9490_CV_STEP 10 /* ICGH */ -#define RT9490_ICHG_MASK 0x1FF -#define RT9490_ICHG_SHIFT 0 -#define RT9490_ICHG_MIN 50 -#define RT9490_ICHG_MAX 5000 -#define RT9490_ICHG_STEP 10 -#define RT9490_ICHG_MIN_REG_VAL 0x0005 +#define RT9490_ICHG_MASK 0x1FF +#define RT9490_ICHG_SHIFT 0 +#define RT9490_ICHG_MIN 50 +#define RT9490_ICHG_MAX 5000 +#define RT9490_ICHG_STEP 10 +#define RT9490_ICHG_MIN_REG_VAL 0x0005 /* PRE CHG */ -#define RT9490_IPRE_CHG_MASK 0x1F -#define RT9490_IPRE_CHG_MIN 40 -#define RT9490_IPRE_CHG_MAX 2000 -#define RT9490_IPRE_CHG_STEP 40 -#define RT9490_IPREC_SHIFT 0 +#define RT9490_IPRE_CHG_MASK 0x1F +#define RT9490_IPRE_CHG_MIN 40 +#define RT9490_IPRE_CHG_MAX 2000 +#define RT9490_IPRE_CHG_STEP 40 +#define RT9490_IPREC_SHIFT 0 /* MIVR */ -#define RT9490_MIVR_MIN 3600 -#define RT9490_MIVR_MAX 22000 -#define RT9490_MIVR_STEP 100 -#define RT9490_MIVR_MIN_REG_VAL 0x24 +#define RT9490_MIVR_MIN 3600 +#define RT9490_MIVR_MAX 22000 +#define RT9490_MIVR_STEP 100 +#define RT9490_MIVR_MIN_REG_VAL 0x24 /* AICR */ -#define RT9490_AICR_MASK 0x1FF -#define RT9490_AICR_SHIFT 0 -#define RT9490_AICR_MIN 100 -#define RT9490_AICR_MAX 3300 -#define RT9490_AICR_STEP 10 -#define RT9490_AICR_MIN_REG_VAL 0x000A +#define RT9490_AICR_MASK 0x1FF +#define RT9490_AICR_SHIFT 0 +#define RT9490_AICR_MIN 100 +#define RT9490_AICR_MAX 3300 +#define RT9490_AICR_STEP 10 +#define RT9490_AICR_MIN_REG_VAL 0x000A /* EOC */ -#define RT9490_IEOC_MIN 40 -#define RT9490_IEOC_MAX 1000 -#define RT9490_IEOC_STEP 40 -#define RT9490_IEOC_MIN_REG_VAL 0x01 -#define RT9490_IEOC_SHIFT 0 -#define RT9490_IEOC_MASK 0x1F +#define RT9490_IEOC_MIN 40 +#define RT9490_IEOC_MAX 1000 +#define RT9490_IEOC_STEP 40 +#define RT9490_IEOC_MIN_REG_VAL 0x01 +#define RT9490_IEOC_SHIFT 0 +#define RT9490_IEOC_MASK 0x1F /* DEVICE INFO */ -#define RT9490_DEVICE_ID 0x60 -#define RT9490_DEVICE_INFO_MASK 0x78 +#define RT9490_DEVICE_ID 0x60 +#define RT9490_DEVICE_INFO_MASK 0x78 /* EOC_CTRL */ -#define RT9490_RST_ALL_MASK BIT(7) +#define RT9490_RST_ALL_MASK BIT(7) /* CHG_CTRL0 */ -#define RT9490_EN_CHG BIT(5) -#define RT9490_EN_AICC BIT(4) -#define RT9490_FORCE_AICC BIT(3) -#define RT9490_EN_HZ BIT(2) +#define RT9490_EN_CHG BIT(5) +#define RT9490_EN_AICC BIT(4) +#define RT9490_FORCE_AICC BIT(3) +#define RT9490_EN_HZ BIT(2) /* CHG_CTRL1 */ -#define RT9490_VAC_OVP_SHIFT 4 -#define RT9490_VAC_OVP_MASK (3 << RT9490_VAC_OVP_SHIFT) -#define RT9490_VAC_OVP_26V 0 -#define RT9490_VAC_OVP_22V 1 -#define RT9490_VAC_OVP_12V 2 -#define RT9490_VAC_OVP_7V 3 - -#define RT9490_WATCHDOG_MASK 0x07 -#define RT9490_WATCHDOG_DISABLE 0 -#define RT9490_WATCHDOG_0_5_SEC 1 /* 0.5 sec */ -#define RT9490_WATCHDOG_1_SEC 2 -#define RT9490_WATCHDOG_2_SEC 3 -#define RT9490_WATCHDOG_20_SEC 4 -#define RT9490_WATCHDOG_40_SEC 5 -#define RT9490_WATCHDOG_80_SEC 6 -#define RT9490_WATCHDOG_160_SEC 7 +#define RT9490_VAC_OVP_SHIFT 4 +#define RT9490_VAC_OVP_MASK (3 << RT9490_VAC_OVP_SHIFT) +#define RT9490_VAC_OVP_26V 0 +#define RT9490_VAC_OVP_22V 1 +#define RT9490_VAC_OVP_12V 2 +#define RT9490_VAC_OVP_7V 3 + +#define RT9490_WATCHDOG_MASK 0x07 +#define RT9490_WATCHDOG_DISABLE 0 +#define RT9490_WATCHDOG_0_5_SEC 1 /* 0.5 sec */ +#define RT9490_WATCHDOG_1_SEC 2 +#define RT9490_WATCHDOG_2_SEC 3 +#define RT9490_WATCHDOG_20_SEC 4 +#define RT9490_WATCHDOG_40_SEC 5 +#define RT9490_WATCHDOG_80_SEC 6 +#define RT9490_WATCHDOG_160_SEC 7 /* CHG_CTRL2 */ -#define RT9490_BC12_EN BIT(6) +#define RT9490_BC12_EN BIT(6) /* CHG_CTRL3 */ -#define RT9490_EN_OTG BIT(6) +#define RT9490_EN_OTG BIT(6) /* CHG_CTRL5 */ -#define RT9490_ILIM_HZ_EN BIT(1) +#define RT9490_ILIM_HZ_EN BIT(1) /* CHG_STATUS4 */ -#define RT9490_JEITA_COLD_MASK BIT(3) -#define RT9490_JEITA_COOL_MASK BIT(2) -#define RT9490_JEITA_WARM_MASK BIT(1) -#define RT9490_JEITA_HOT_MASK BIT(0) +#define RT9490_JEITA_COLD_MASK BIT(3) +#define RT9490_JEITA_COOL_MASK BIT(2) +#define RT9490_JEITA_WARM_MASK BIT(1) +#define RT9490_JEITA_HOT_MASK BIT(0) /* CHG_IRQ_FLAG1 */ -#define RT9490_BC12_DONE_FLAG BIT(0) +#define RT9490_BC12_DONE_FLAG BIT(0) /* CHG_IRQ_MASK0 */ -#define RT9490_CHG_IRQ_MASK0_ALL 0xFF +#define RT9490_CHG_IRQ_MASK0_ALL 0xFF /* CHG_IRQ_MASK1 */ -#define RT9490_BC12_DONE_MASK BIT(0) -#define RT9490_CHG_IRQ_MASK1_ALL 0xD7 +#define RT9490_BC12_DONE_MASK BIT(0) +#define RT9490_CHG_IRQ_MASK1_ALL 0xD7 /* CHG_IRQ_MASK2 */ -#define RT9490_CHG_IRQ_MASK2_ALL 0x7F +#define RT9490_CHG_IRQ_MASK2_ALL 0x7F /* CHG_IRQ_MASK3 */ -#define RT9490_CHG_IRQ_MASK3_ALL 0x1F +#define RT9490_CHG_IRQ_MASK3_ALL 0x1F /* CHG_IRQ_MASK4 */ -#define RT9490_CHG_IRQ_MASK4_ALL 0xFF +#define RT9490_CHG_IRQ_MASK4_ALL 0xFF /* CHG_IRQ_MASK5 */ -#define RT9490_CHG_IRQ_MASK5_ALL 0xF4 +#define RT9490_CHG_IRQ_MASK5_ALL 0xF4 /* SAFETY TMR CTRL */ -#define RT9490_EN_TRICHG_TMR BIT(5) -#define RT9490_EN_PRECHG_TMR BIT(4) -#define RT9490_EN_FASTCHG_TMR BIT(3) +#define RT9490_EN_TRICHG_TMR BIT(5) +#define RT9490_EN_PRECHG_TMR BIT(4) +#define RT9490_EN_FASTCHG_TMR BIT(3) /* VOTG REGU */ -#define RT9490_VOTG_MASK 0x7FF -#define RT9490_VOTG_MIN 2800 -#define RT9490_VOTG_MAX 22000 -#define RT9490_VOTG_STEP 10 +#define RT9490_VOTG_MASK 0x7FF +#define RT9490_VOTG_MIN 2800 +#define RT9490_VOTG_MAX 22000 +#define RT9490_VOTG_STEP 10 /* IOTG REGU */ -#define RT9490_IOTG_MASK 0x7F -#define RT9490_IOTG_MIN 120 -#define RT9490_IOTG_MAX 3320 -#define RT9490_IOTG_STEP 40 +#define RT9490_IOTG_MASK 0x7F +#define RT9490_IOTG_MIN 120 +#define RT9490_IOTG_MAX 3320 +#define RT9490_IOTG_STEP 40 /* JEITA_CTRL1 */ -#define RT9490_JEITA_DIS BIT(0) +#define RT9490_JEITA_DIS BIT(0) /* CHG_STATUS1 */ -#define RT9490_CHG_STAT_MASK 0xE0 -#define RT9490_CHG_STAT_SHIFT 5 -#define RT9490_VBUS_STAT_MASK 0x1E -#define RT9490_VBUS_STAT_SHIFT 1 -#define RT9490_BC12_DONE_STAT BIT(0) +#define RT9490_CHG_STAT_MASK 0xE0 +#define RT9490_CHG_STAT_SHIFT 5 +#define RT9490_VBUS_STAT_MASK 0x1E +#define RT9490_VBUS_STAT_SHIFT 1 +#define RT9490_BC12_DONE_STAT BIT(0) -#define RT9490_SDP 0x1 -#define RT9490_CDP 0x2 -#define RT9490_DCP 0x3 +#define RT9490_SDP 0x1 +#define RT9490_CDP 0x2 +#define RT9490_DCP 0x3 /* FAULT STATUS0 */ -#define RT9490_VBAT_OVP_STAT BIT(5) +#define RT9490_VBAT_OVP_STAT BIT(5) /* ADC CTRL */ -#define RT9490_ADC_EN BIT(7) +#define RT9490_ADC_EN BIT(7) /* ADC CHANNEL0 */ -#define RT9490_VSYS_ADC_DIS BIT(3) +#define RT9490_VSYS_ADC_DIS BIT(3) /* ADD CTRL0 */ -#define RT9490_AUTO_AICR BIT(5) -#define RT9490_TD_EOC BIT(4) -#define RT9490_AUTO_MIVR BIT(2) -#define RT9490_JEITA_COLD_HOT BIT(0) +#define RT9490_AUTO_AICR BIT(5) +#define RT9490_TD_EOC BIT(4) +#define RT9490_AUTO_MIVR BIT(2) +#define RT9490_JEITA_COLD_HOT BIT(0) /* ADD CTRL1 */ -#define RT9490_PWM_1MHZ_EN BIT(4) +#define RT9490_PWM_1MHZ_EN BIT(4) extern const struct charger_drv rt9490_drv; extern const struct bc12_drv rt9490_bc12_drv; -- cgit v1.2.1 From 6f8a9de957e01baf96e70563a3411715a05d0c86 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:03 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a0dd5c583e6d416cfe1d82fb885d6fe7c38d597 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730730 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h index 5e23a770da..3956637300 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_snk.h @@ -53,10 +53,10 @@ struct tcpci_snk_emul_data { * * @return Pointer to USB-C sink extension */ -struct tcpci_partner_extension *tcpci_snk_emul_init( - struct tcpci_snk_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext); +struct tcpci_partner_extension * +tcpci_snk_emul_init(struct tcpci_snk_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext); /** * @brief Clear the ping received flag. -- cgit v1.2.1 From 11e5f9cae86c66037c7a2c515b464eb4260ebc38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:28 -0600 Subject: driver/als_opt3001.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic2299ea6eb380539b6bb23bf7e9e29236388c14c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729902 Reviewed-by: Jeremy Bettis --- driver/als_opt3001.c | 53 ++++++++++++++++++++++------------------------------ 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/driver/als_opt3001.c b/driver/als_opt3001.c index 53f2b7df89..0e75fbfb4a 100644 --- a/driver/als_opt3001.c +++ b/driver/als_opt3001.c @@ -17,11 +17,10 @@ static int opt3001_i2c_read(const int reg, int *data_ptr) { int ret; - ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, - reg, data_ptr); + ret = i2c_read16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data_ptr); if (!ret) *data_ptr = ((*data_ptr << 8) & 0xFF00) | - ((*data_ptr >> 8) & 0x00FF); + ((*data_ptr >> 8) & 0x00FF); return ret; } @@ -32,8 +31,7 @@ static int opt3001_i2c_read(const int reg, int *data_ptr) static int opt3001_i2c_write(const int reg, int data) { data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF); - return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, - reg, data); + return i2c_write16(I2C_PORT_ALS, OPT3001_I2C_ADDR_FLAGS, reg, data); } /** @@ -102,25 +100,23 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = { .i2c_read_dev = &opt3001_i2c_read, .i2c_write_dev = &opt3001_i2c_write, }; -#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */ -#else /* HAS_TASK_ALS */ +#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */ +#else /* HAS_TASK_ALS */ #include "accelgyro.h" #include "math_util.h" /** * Read register from OPT3001 light sensor. */ -static int opt3001_i2c_read(const int port, - const uint16_t i2c_addr_flags, +static int opt3001_i2c_read(const int port, const uint16_t i2c_addr_flags, const int reg, int *data_ptr) { int ret; - ret = i2c_read16(port, i2c_addr_flags, - reg, data_ptr); + ret = i2c_read16(port, i2c_addr_flags, reg, data_ptr); if (!ret) *data_ptr = ((*data_ptr << 8) & 0xFF00) | - ((*data_ptr >> 8) & 0x00FF); + ((*data_ptr >> 8) & 0x00FF); return ret; } @@ -128,8 +124,7 @@ static int opt3001_i2c_read(const int port, /** * Write register to OPT3001 light sensor. */ -static int opt3001_i2c_write(const int port, - const uint16_t i2c_addr_flags, +static int opt3001_i2c_write(const int port, const uint16_t i2c_addr_flags, const int reg, int data) { data = ((data << 8) & 0xFF00) | ((data >> 8) & 0x00FF); @@ -177,8 +172,7 @@ int opt3001_read_lux(const struct motion_sensor_t *s, intv3_t v) } } -static int opt3001_set_range(struct motion_sensor_t *s, int range, - int rnd) +static int opt3001_set_range(struct motion_sensor_t *s, int range, int rnd) { struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s); @@ -188,8 +182,8 @@ static int opt3001_set_range(struct motion_sensor_t *s, int range, return EC_SUCCESS; } -static int opt3001_set_data_rate(const struct motion_sensor_t *s, - int rate, int roundup) +static int opt3001_set_data_rate(const struct motion_sensor_t *s, int rate, + int roundup) { struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s); int rv; @@ -216,10 +210,9 @@ static int opt3001_set_data_rate(const struct motion_sensor_t *s, if (rv) return rv; - rv = opt3001_i2c_write(s->port, s->i2c_spi_addr_flags, - OPT3001_REG_CONFIGURE, - (reg & OPT3001_MODE_MASK) | - (mode << OPT3001_MODE_OFFSET)); + rv = opt3001_i2c_write( + s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE, + (reg & OPT3001_MODE_MASK) | (mode << OPT3001_MODE_OFFSET)); if (rv) return rv; @@ -235,8 +228,7 @@ static int opt3001_get_data_rate(const struct motion_sensor_t *s) } static int opt3001_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) + const int16_t *offset, int16_t temp) { struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s); @@ -244,9 +236,8 @@ static int opt3001_set_offset(const struct motion_sensor_t *s, return EC_SUCCESS; } -static int opt3001_get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) +static int opt3001_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct opt3001_drv_data_t *drv_data = OPT3001_GET_DATA(s); @@ -283,8 +274,8 @@ static int opt3001_init(struct motion_sensor_t *s) * [11] : 1b Conversion time 800ms * [4] : 1b Latched window-style comparison operation */ - opt3001_i2c_write(s->port, s->i2c_spi_addr_flags, - OPT3001_REG_CONFIGURE, 0xC810); + opt3001_i2c_write(s->port, s->i2c_spi_addr_flags, OPT3001_REG_CONFIGURE, + 0xC810); opt3001_set_range(s, s->default_range, 0); @@ -311,5 +302,5 @@ struct i2c_stress_test_dev opt3001_i2c_stress_test_dev = { .i2c_read = &opt3001_i2c_read, .i2c_write = &opt3001_i2c_write, }; -#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */ -#endif /* HAS_TASK_ALS */ +#endif /* CONFIG_CMD_I2C_STRESS_TEST_ALS */ +#endif /* HAS_TASK_ALS */ -- cgit v1.2.1 From b695a6d4780ced462ade6665c609e0023b12017f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:39 -0600 Subject: driver/accelgyro_icm42607.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0056164771a17759fc9c7015001b989c651c5c8d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729917 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm42607.h | 336 ++++++++++++++++++++++---------------------- 1 file changed, 165 insertions(+), 171 deletions(-) diff --git a/driver/accelgyro_icm42607.h b/driver/accelgyro_icm42607.h index e2d2b3469a..aaba155474 100644 --- a/driver/accelgyro_icm42607.h +++ b/driver/accelgyro_icm42607.h @@ -15,59 +15,55 @@ * 7-bit address is 110100Xb. Where 'X' is determined * by the logic level on pin AP_AD0. */ -#define ICM42607_ADDR0_FLAGS 0x68 -#define ICM42607_ADDR1_FLAGS 0x69 +#define ICM42607_ADDR0_FLAGS 0x68 +#define ICM42607_ADDR1_FLAGS 0x69 /* Min and Max sampling frequency in mHz */ -#define ICM42607_ACCEL_MIN_FREQ 1562 -#define ICM42607_ACCEL_MAX_FREQ \ - MOTION_MAX_SENSOR_FREQUENCY(400000, 100000) -#define ICM42607_GYRO_MIN_FREQ 12500 -#define ICM42607_GYRO_MAX_FREQ \ - MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) +#define ICM42607_ACCEL_MIN_FREQ 1562 +#define ICM42607_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(400000, 100000) +#define ICM42607_GYRO_MIN_FREQ 12500 +#define ICM42607_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) /* Min and Max Accel FS in g */ -#define ICM42607_ACCEL_FS_MIN_VAL 2 -#define ICM42607_ACCEL_FS_MAX_VAL 16 +#define ICM42607_ACCEL_FS_MIN_VAL 2 +#define ICM42607_ACCEL_FS_MAX_VAL 16 /* Min and Max Gyro FS in dps */ -#define ICM42607_GYRO_FS_MIN_VAL 250 -#define ICM42607_GYRO_FS_MAX_VAL 2000 +#define ICM42607_GYRO_FS_MIN_VAL 250 +#define ICM42607_GYRO_FS_MAX_VAL 2000 /* accel stabilization time in us */ -#define ICM42607_ACCEL_START_TIME 20000 -#define ICM42607_ACCEL_STOP_TIME 0 +#define ICM42607_ACCEL_START_TIME 20000 +#define ICM42607_ACCEL_STOP_TIME 0 /* gyro stabilization time in us */ -#define ICM42607_GYRO_START_TIME 40000 -#define ICM42607_GYRO_STOP_TIME 20000 +#define ICM42607_GYRO_START_TIME 40000 +#define ICM42607_GYRO_STOP_TIME 20000 /* Reg value from Accel FS in G */ -#define ICM42607_ACCEL_FS_TO_REG(_fs) ((_fs) <= 2 ? 3 : \ - (_fs) >= 16 ? 0 : \ - 3 - __fls((_fs) / 2)) +#define ICM42607_ACCEL_FS_TO_REG(_fs) \ + ((_fs) <= 2 ? 3 : (_fs) >= 16 ? 0 : 3 - __fls((_fs) / 2)) /* Accel FSR in G from Reg value */ -#define ICM42607_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2) +#define ICM42607_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2) /* Reg value from Gyro FS in dps */ -#define ICM42607_GYRO_FS_TO_REG(_fs) ((_fs) <= 250 ? 3 : \ - (_fs) >= 2000 ? 0 : \ - 3 - __fls((_fs) / 250)) +#define ICM42607_GYRO_FS_TO_REG(_fs) \ + ((_fs) <= 250 ? 3 : (_fs) >= 2000 ? 0 : 3 - __fls((_fs) / 250)) /* Gyro FSR in dps from Reg value */ -#define ICM42607_GYRO_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 250) +#define ICM42607_GYRO_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 250) /* Reg value from ODR in mHz */ -#define ICM42607_ODR_TO_REG(_odr) ((_odr) == 0 ? 0 : \ - (__fls(1600000 / (_odr)) + 5)) +#define ICM42607_ODR_TO_REG(_odr) \ + ((_odr) == 0 ? 0 : (__fls(1600000 / (_odr)) + 5)) /* ODR in mHz from Reg value */ -#define ICM42607_REG_TO_ODR(_reg) ((_reg) <= 5 ? 1600000 : \ - (1600000 / (1 << ((_reg) - 5)))) +#define ICM42607_REG_TO_ODR(_reg) \ + ((_reg) <= 5 ? 1600000 : (1600000 / (1 << ((_reg)-5)))) /* Reg value for the next higher ODR */ -#define ICM42607_ODR_REG_UP(_reg) ((_reg) - 1) +#define ICM42607_ODR_REG_UP(_reg) ((_reg)-1) /* * Filter bandwidth values from ODR reg @@ -77,10 +73,8 @@ * 50Hz (10) -> 25Hz (6) * <= 25Hz (11) -> 16Hz (7) */ -#define ICM42607_ODR_TO_FILT_BW(_odr) ((_odr) <= 7 ? 1 : \ - (_odr) <= 9 ? (_odr) - 5 : \ - (_odr) == 10 ? 6 : \ - 7) +#define ICM42607_ODR_TO_FILT_BW(_odr) \ + ((_odr) <= 7 ? 1 : (_odr) <= 9 ? (_odr)-5 : (_odr) == 10 ? 6 : 7) /* * Register addresses are virtual address on 16 bits. @@ -88,53 +82,53 @@ * and LSB real register address. * ex: MREG2 (block 0x28) register 03 => 0x2803 */ -#define ICM42607_REG_MCLK_RDY 0x0000 -#define ICM42607_MCLK_RDY BIT(3) +#define ICM42607_REG_MCLK_RDY 0x0000 +#define ICM42607_MCLK_RDY BIT(3) -#define ICM42607_REG_DEVICE_CONFIG 0x0001 -#define ICM42607_SPI_MODE_1_2 BIT(0) -#define ICM42607_SPI_AP_4WIRE BIT(2) +#define ICM42607_REG_DEVICE_CONFIG 0x0001 +#define ICM42607_SPI_MODE_1_2 BIT(0) +#define ICM42607_SPI_AP_4WIRE BIT(2) -#define ICM42607_REG_SIGNAL_PATH_RESET 0x0002 -#define ICM42607_SOFT_RESET_DEV_CONFIG BIT(4) -#define ICM42607_FIFO_FLUSH BIT(2) +#define ICM42607_REG_SIGNAL_PATH_RESET 0x0002 +#define ICM42607_SOFT_RESET_DEV_CONFIG BIT(4) +#define ICM42607_FIFO_FLUSH BIT(2) -#define ICM42607_REG_DRIVE_CONFIG1 0x0003 +#define ICM42607_REG_DRIVE_CONFIG1 0x0003 -#define ICM42607_REG_DRIVE_CONFIG2 0x0004 +#define ICM42607_REG_DRIVE_CONFIG2 0x0004 -#define ICM42607_REG_DRIVE_CONFIG3 0x0005 +#define ICM42607_REG_DRIVE_CONFIG3 0x0005 /* default int configuration is pulsed mode, open drain, and active low */ -#define ICM42607_REG_INT_CONFIG 0x0006 -#define ICM42607_INT2_MASK GENMASK(5, 3) -#define ICM42607_INT2_LATCHED BIT(5) -#define ICM42607_INT2_PUSH_PULL BIT(4) -#define ICM42607_INT2_ACTIVE_HIGH BIT(3) -#define ICM42607_INT1_MASK GENMASK(2, 0) -#define ICM42607_INT1_LATCHED BIT(2) -#define ICM42607_INT1_PUSH_PULL BIT(1) -#define ICM42607_INT1_ACTIVE_HIGH BIT(0) +#define ICM42607_REG_INT_CONFIG 0x0006 +#define ICM42607_INT2_MASK GENMASK(5, 3) +#define ICM42607_INT2_LATCHED BIT(5) +#define ICM42607_INT2_PUSH_PULL BIT(4) +#define ICM42607_INT2_ACTIVE_HIGH BIT(3) +#define ICM42607_INT1_MASK GENMASK(2, 0) +#define ICM42607_INT1_LATCHED BIT(2) +#define ICM42607_INT1_PUSH_PULL BIT(1) +#define ICM42607_INT1_ACTIVE_HIGH BIT(0) /* data are 16 bits */ -#define ICM42607_REG_TEMP_DATA 0x0009 +#define ICM42607_REG_TEMP_DATA 0x0009 /* X + Y + Z: 3 * 16 bits */ -#define ICM42607_REG_ACCEL_DATA_XYZ 0x000B -#define ICM42607_REG_GYRO_DATA_XYZ 0x0011 +#define ICM42607_REG_ACCEL_DATA_XYZ 0x000B +#define ICM42607_REG_GYRO_DATA_XYZ 0x0011 -#define ICM42607_INVALID_DATA -32768 +#define ICM42607_INVALID_DATA -32768 /* data are 16 bits */ -#define ICM42607_REG_TMST_FSYNCH 0x0017 +#define ICM42607_REG_TMST_FSYNCH 0x0017 -#define ICM42607_REG_PWR_MGMT0 0x001F -#define ICM42607_ACCEL_LP_CLK_SEL BIT(7) -#define ICM42607_IDLE BIT(4) -#define ICM42607_GYRO_MODE_MASK GENMASK(3, 2) -#define ICM42607_GYRO_MODE(_m) (((_m) & 0x03) << 2) -#define ICM42607_ACCEL_MODE_MASK GENMASK(1, 0) -#define ICM42607_ACCEL_MODE(_m) ((_m) & 0x03) +#define ICM42607_REG_PWR_MGMT0 0x001F +#define ICM42607_ACCEL_LP_CLK_SEL BIT(7) +#define ICM42607_IDLE BIT(4) +#define ICM42607_GYRO_MODE_MASK GENMASK(3, 2) +#define ICM42607_GYRO_MODE(_m) (((_m)&0x03) << 2) +#define ICM42607_ACCEL_MODE_MASK GENMASK(1, 0) +#define ICM42607_ACCEL_MODE(_m) ((_m)&0x03) enum icm42607_sensor_mode { ICM42607_MODE_OFF, @@ -143,14 +137,14 @@ enum icm42607_sensor_mode { ICM42607_MODE_LOW_NOISE, }; -#define ICM42607_REG_GYRO_CONFIG0 0x0020 -#define ICM42607_REG_ACCEL_CONFIG0 0x0021 -#define ICM42607_FS_MASK GENMASK(6, 5) -#define ICM42607_FS_SEL(_fs) (((_fs) & 0x03) << 5) -#define ICM42607_ODR_MASK GENMASK(3, 0) -#define ICM42607_ODR(_odr) ((_odr) & 0x0F) +#define ICM42607_REG_GYRO_CONFIG0 0x0020 +#define ICM42607_REG_ACCEL_CONFIG0 0x0021 +#define ICM42607_FS_MASK GENMASK(6, 5) +#define ICM42607_FS_SEL(_fs) (((_fs)&0x03) << 5) +#define ICM42607_ODR_MASK GENMASK(3, 0) +#define ICM42607_ODR(_odr) ((_odr)&0x0F) -#define ICM42607_REG_TEMP_CONFIG0 0x0022 +#define ICM42607_REG_TEMP_CONFIG0 0x0022 enum icm42607_ui_avg { ICM42607_UI_AVG_2X, @@ -172,122 +166,122 @@ enum icm42607_ui_filt_bw { ICM42607_UI_FILT_BW_16HZ, }; -#define ICM42607_REG_GYRO_CONFIG1 0x0023 -#define ICM42607_REG_ACCEL_CONFIG1 0x0024 -#define ICM42607_UI_AVG_MASK GENMASK(6, 4) -#define ICM42607_UI_AVG_SET(_avg) (((_avg) & 0x07) << 4) -#define ICM42607_UI_FILT_BW_MASK GENMASK(2, 0) -#define ICM42607_UI_FILT_BW_SET(_filt) ((_filt) & 0x07) +#define ICM42607_REG_GYRO_CONFIG1 0x0023 +#define ICM42607_REG_ACCEL_CONFIG1 0x0024 +#define ICM42607_UI_AVG_MASK GENMASK(6, 4) +#define ICM42607_UI_AVG_SET(_avg) (((_avg)&0x07) << 4) +#define ICM42607_UI_FILT_BW_MASK GENMASK(2, 0) +#define ICM42607_UI_FILT_BW_SET(_filt) ((_filt)&0x07) -#define ICM42607_REG_FIFO_CONFIG1 0x0028 -#define ICM42607_REG_FIFO_CONFIG2 0x0029 -#define ICM42607_REG_FIFO_CONFIG3 0x002A -#define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1) -#define ICM42607_FIFO_BYPASS BIT(0) -#define ICM42607_FIFO_MODE_STREAM 0x00 +#define ICM42607_REG_FIFO_CONFIG1 0x0028 +#define ICM42607_REG_FIFO_CONFIG2 0x0029 +#define ICM42607_REG_FIFO_CONFIG3 0x002A +#define ICM42607_FIFO_STOP_ON_FULL_MODE BIT(1) +#define ICM42607_FIFO_BYPASS BIT(0) +#define ICM42607_FIFO_MODE_STREAM 0x00 /* FIFO watermark value is 16 bits little endian */ -#define ICM42607_REG_FIFO_WM 0x0029 - -#define ICM42607_REG_INT_SOURCE0 0x002B -#define ICM42607_ST_INT1_EN BIT(7) -#define ICM42607_FSYNC_INT1_EN BIT(6) -#define ICM42607_PLL_RDY_INT1_EN BIT(5) -#define ICM42607_RESET_DONE_INT1_EN BIT(4) -#define ICM42607_DRDY_INT1_EN BIT(3) -#define ICM42607_FIFO_THS_INT1_EN BIT(2) -#define ICM42607_FIFO_FULL_INT1_EN BIT(1) -#define ICM42607_UI_AGC_RDY_INT1_EN BIT(0) - -#define ICM42607_REG_INTF_CONFIG0 0x0035 -#define ICM42607_FIFO_COUNT_FORMAT BIT(6) -#define ICM42607_FIFO_COUNT_ENDIAN BIT(5) -#define ICM42607_SENSOR_DATA_ENDIAN BIT(4) - -#define ICM42607_REG_INTF_CONFIG1 0x0036 -#define ICM42607_I3C_SDR_EN BIT(3) -#define ICM42607_I3C_DDR_EN BIT(2) -#define ICM42607_CLKSEL_MASK GENMASK(1, 0) -#define ICM42607_CLKSEL_PLL_ENABLE 0x01 - -#define ICM42607_REG_INT_STATUS_DRDY 0x0039 -#define ICM42607_DATA_RDY_INT BIT(0) - -#define ICM42607_REG_INT_STATUS 0x003A -#define ICM42607_ST_INT BIT(7) -#define ICM42607_FSYNC_INT BIT(6) -#define ICM42607_PLL_RDY_INT BIT(5) -#define ICM42607_RESET_DONE_INT BIT(4) -#define ICM42607_FIFO_THS_INT BIT(2) -#define ICM42607_FIFO_FULL_INT BIT(1) -#define ICM42607_AGC_RDY_INT BIT(0) +#define ICM42607_REG_FIFO_WM 0x0029 + +#define ICM42607_REG_INT_SOURCE0 0x002B +#define ICM42607_ST_INT1_EN BIT(7) +#define ICM42607_FSYNC_INT1_EN BIT(6) +#define ICM42607_PLL_RDY_INT1_EN BIT(5) +#define ICM42607_RESET_DONE_INT1_EN BIT(4) +#define ICM42607_DRDY_INT1_EN BIT(3) +#define ICM42607_FIFO_THS_INT1_EN BIT(2) +#define ICM42607_FIFO_FULL_INT1_EN BIT(1) +#define ICM42607_UI_AGC_RDY_INT1_EN BIT(0) + +#define ICM42607_REG_INTF_CONFIG0 0x0035 +#define ICM42607_FIFO_COUNT_FORMAT BIT(6) +#define ICM42607_FIFO_COUNT_ENDIAN BIT(5) +#define ICM42607_SENSOR_DATA_ENDIAN BIT(4) + +#define ICM42607_REG_INTF_CONFIG1 0x0036 +#define ICM42607_I3C_SDR_EN BIT(3) +#define ICM42607_I3C_DDR_EN BIT(2) +#define ICM42607_CLKSEL_MASK GENMASK(1, 0) +#define ICM42607_CLKSEL_PLL_ENABLE 0x01 + +#define ICM42607_REG_INT_STATUS_DRDY 0x0039 +#define ICM42607_DATA_RDY_INT BIT(0) + +#define ICM42607_REG_INT_STATUS 0x003A +#define ICM42607_ST_INT BIT(7) +#define ICM42607_FSYNC_INT BIT(6) +#define ICM42607_PLL_RDY_INT BIT(5) +#define ICM42607_RESET_DONE_INT BIT(4) +#define ICM42607_FIFO_THS_INT BIT(2) +#define ICM42607_FIFO_FULL_INT BIT(1) +#define ICM42607_AGC_RDY_INT BIT(0) /* FIFO count is 16 bits */ -#define ICM42607_REG_FIFO_COUNT 0x003D +#define ICM42607_REG_FIFO_COUNT 0x003D -#define ICM42607_REG_FIFO_DATA 0x003F +#define ICM42607_REG_FIFO_DATA 0x003F -#define ICM42607_REG_APEX_CONFIG0 0x0025 -#define ICM42607_DMP_SRAM_RESET_APEX BIT(0) +#define ICM42607_REG_APEX_CONFIG0 0x0025 +#define ICM42607_DMP_SRAM_RESET_APEX BIT(0) -#define ICM42607_REG_APEX_CONFIG1 0x0026 -#define ICM42607_DMP_ODR_50HZ BIT(1) +#define ICM42607_REG_APEX_CONFIG1 0x0026 +#define ICM42607_DMP_ODR_50HZ BIT(1) -#define ICM42607_REG_WHO_AM_I 0x0075 -#define ICM42607_CHIP_ICM42607P 0x60 +#define ICM42607_REG_WHO_AM_I 0x0075 +#define ICM42607_CHIP_ICM42607P 0x60 /* MREG read access registers */ -#define ICM42607_REG_BLK_SEL_W 0x0079 -#define ICM42607_REG_MADDR_W 0x007A -#define ICM42607_REG_M_W 0x007B +#define ICM42607_REG_BLK_SEL_W 0x0079 +#define ICM42607_REG_MADDR_W 0x007A +#define ICM42607_REG_M_W 0x007B /* MREG write access registers */ -#define ICM42607_REG_BLK_SEL_R 0x007C -#define ICM42607_REG_MADDR_R 0x007D -#define ICM42607_REG_M_R 0x007E +#define ICM42607_REG_BLK_SEL_R 0x007C +#define ICM42607_REG_MADDR_R 0x007D +#define ICM42607_REG_M_R 0x007E /* USER BANK MREG1 */ -#define ICM42607_MREG_FIFO_CONFIG5 0x0001 -#define ICM42607_FIFO_WM_GT_TH BIT(5) -#define ICM42607_FIFO_RESUME_PARTIAL_RD BIT(4) -#define ICM42607_FIFO_HIRES_EN BIT(3) -#define ICM42607_FIFO_TMST_FSYNC_EN BIT(2) -#define ICM42607_FIFO_GYRO_EN BIT(1) -#define ICM42607_FIFO_ACCEL_EN BIT(0) - -#define ICM42607_MREG_OTP_CONFIG 0x002B -#define ICM42607_OTP_COPY_MODE_MASK GENMASK(3, 2) -#define ICM42607_OTP_COPY_TRIM (0x01 << 2) -#define ICM42607_OTP_COPY_ST_DATA (0x03 << 2) - -#define ICM42607_MREG_INT_SOURCE7 0x0030 -#define ICM42607_MREG_INT_SOURCE8 0x0031 -#define ICM42607_MREG_INT_SOURCE9 0x0032 -#define ICM42607_MREG_INT_SOURCE10 0x0033 - -#define ICM42607_MREG_APEX_CONFIG2 0x0044 -#define ICM42607_MREG_APEX_CONFIG3 0x0045 -#define ICM42607_MREG_APEX_CONFIG4 0x0046 -#define ICM42607_MREG_APEX_CONFIG5 0x0047 -#define ICM42607_MREG_APEX_CONFIG9 0x0048 -#define ICM42607_MREG_APEX_CONFIG10 0x0049 -#define ICM42607_MREG_APEX_CONFIG11 0x004A -#define ICM42607_MREG_APEX_CONFIG12 0x0067 - -#define ICM42607_MREG_OFFSET_USER0 0x004E -#define ICM42607_MREG_OFFSET_USER1 0x004F -#define ICM42607_MREG_OFFSET_USER2 0x0050 -#define ICM42607_MREG_OFFSET_USER3 0x0051 -#define ICM42607_MREG_OFFSET_USER4 0x0052 -#define ICM42607_MREG_OFFSET_USER5 0x0053 -#define ICM42607_MREG_OFFSET_USER6 0x0054 -#define ICM42607_MREG_OFFSET_USER7 0x0055 -#define ICM42607_MREG_OFFSET_USER8 0x0056 +#define ICM42607_MREG_FIFO_CONFIG5 0x0001 +#define ICM42607_FIFO_WM_GT_TH BIT(5) +#define ICM42607_FIFO_RESUME_PARTIAL_RD BIT(4) +#define ICM42607_FIFO_HIRES_EN BIT(3) +#define ICM42607_FIFO_TMST_FSYNC_EN BIT(2) +#define ICM42607_FIFO_GYRO_EN BIT(1) +#define ICM42607_FIFO_ACCEL_EN BIT(0) + +#define ICM42607_MREG_OTP_CONFIG 0x002B +#define ICM42607_OTP_COPY_MODE_MASK GENMASK(3, 2) +#define ICM42607_OTP_COPY_TRIM (0x01 << 2) +#define ICM42607_OTP_COPY_ST_DATA (0x03 << 2) + +#define ICM42607_MREG_INT_SOURCE7 0x0030 +#define ICM42607_MREG_INT_SOURCE8 0x0031 +#define ICM42607_MREG_INT_SOURCE9 0x0032 +#define ICM42607_MREG_INT_SOURCE10 0x0033 + +#define ICM42607_MREG_APEX_CONFIG2 0x0044 +#define ICM42607_MREG_APEX_CONFIG3 0x0045 +#define ICM42607_MREG_APEX_CONFIG4 0x0046 +#define ICM42607_MREG_APEX_CONFIG5 0x0047 +#define ICM42607_MREG_APEX_CONFIG9 0x0048 +#define ICM42607_MREG_APEX_CONFIG10 0x0049 +#define ICM42607_MREG_APEX_CONFIG11 0x004A +#define ICM42607_MREG_APEX_CONFIG12 0x0067 + +#define ICM42607_MREG_OFFSET_USER0 0x004E +#define ICM42607_MREG_OFFSET_USER1 0x004F +#define ICM42607_MREG_OFFSET_USER2 0x0050 +#define ICM42607_MREG_OFFSET_USER3 0x0051 +#define ICM42607_MREG_OFFSET_USER4 0x0052 +#define ICM42607_MREG_OFFSET_USER5 0x0053 +#define ICM42607_MREG_OFFSET_USER6 0x0054 +#define ICM42607_MREG_OFFSET_USER7 0x0055 +#define ICM42607_MREG_OFFSET_USER8 0x0056 /* USER BANK MREG2 */ -#define ICM42607_MREG_OTP_CTRL7 0x2806 -#define ICM42607_OTP_RELOAD BIT(3) -#define ICM42607_OTP_PWR_DOWN BIT(1) +#define ICM42607_MREG_OTP_CTRL7 0x2806 +#define ICM42607_OTP_RELOAD BIT(3) +#define ICM42607_OTP_PWR_DOWN BIT(1) extern const struct accelgyro_drv icm42607_drv; -- cgit v1.2.1 From 7c9517e80d7a1c5227459cde77ec82c7de3c68ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:16 -0600 Subject: core/cortex-m0/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff41a3b4441379065a00dec73db374a70b9dfc82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729834 Reviewed-by: Jeremy Bettis --- core/cortex-m0/task.c | 88 ++++++++++++++++++++++----------------------------- 1 file changed, 38 insertions(+), 50 deletions(-) diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index 52a6921ae6..5eb67c7346 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -21,10 +21,10 @@ typedef union { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ }; } task_; @@ -40,12 +40,10 @@ CONFIG_CTS_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -55,12 +53,12 @@ static uint64_t task_start_time; /* Time task scheduling started */ * We only keep 32-bit values for exception start/end time, to avoid * accounting errors when we service interrupt when the timer wraps around. */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern int __task_start(int *task_stack_ready); @@ -89,20 +87,19 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .r0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .r0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t r0; uint32_t pc; uint16_t stack_size; } tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -112,15 +109,11 @@ static task_ tasks[TASK_ID_COUNT]; BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8); BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); - /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST + CONFIG_CTS_TASK_LIST] __aligned(8); #undef TASK @@ -144,7 +137,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -static int start_called; /* Has task swapping started */ +static int start_called; /* Has task swapping started */ static inline task_ *__task_id_to_ptr(task_id_t id) { @@ -166,7 +159,7 @@ inline bool is_interrupt_enabled(void) int primask; /* Interrupts are enabled when PRIMASK bit is 0 */ - asm("mrs %0, primask":"=r"(primask)); + asm("mrs %0, primask" : "=r"(primask)); return !(primask & 0x1); } @@ -184,7 +177,7 @@ static inline int get_interrupt_context(void) { int ret; asm("mrs %0, ipsr\n" : "=r"(ret)); /* read exception number */ - return ret & 0x1ff; /* exception bits are the 9 LSB */ + return ret & 0x1ff; /* exception bits are the 9 LSB */ } #endif @@ -211,7 +204,7 @@ int task_start_called(void) /** * Scheduling system call */ -task_ __attribute__((noinline)) *__svc_handler(int desched, task_id_t resched) +task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched) { task_ *current, *next; #ifdef CONFIG_TASK_PROFILING @@ -304,9 +297,8 @@ void task_start_irq_handler(void *excep_return) * Continue iff the tasks are ready and we are not called from another * exception (as the time accouting is done in the outer irq). */ - if (!start_called - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; exc_start_time = t; @@ -324,9 +316,8 @@ void task_end_irq_handler(void *excep_return) * Continue iff the tasks are ready and we are not called from another * exception (as the time accouting is done in the outer irq). */ - if (!start_called - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!start_called || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; /* Track time in interrupts */ @@ -613,9 +604,7 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, - "Print task info"); +DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); #ifdef CONFIG_CMD_TASKREADY static int command_task_ready(int argc, char **argv) @@ -630,8 +619,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); #endif @@ -657,10 +645,10 @@ void task_pre_init(void) tasks[i].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[8] = tasks_init[i].r0; /* r0 */ - sp[13] = (uint32_t)task_exit_trap; /* lr */ - sp[14] = tasks_init[i].pc; /* pc */ - sp[15] = 0x01000000; /* psr */ + sp[8] = tasks_init[i].r0; /* r0 */ + sp[13] = (uint32_t)task_exit_trap; /* lr */ + sp[14] = tasks_init[i].pc; /* pc */ + sp[15] = 0x01000000; /* psr */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++) -- cgit v1.2.1 From 2d40061f2c4eb18b03e12f721d779f88386d62c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:10 -0600 Subject: board/metaknight/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9073f45504b107137adff1deb9eeb197b9cfaaf8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728451 Reviewed-by: Jeremy Bettis --- board/metaknight/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/metaknight/cbi_ssfc.c b/board/metaknight/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/metaknight/cbi_ssfc.c +++ b/board/metaknight/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 69cffae8ff5f37111643b41d12845438e7afef7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:56 -0600 Subject: driver/temp_sensor/bd99992gw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9dd4318e5c052392731b9575a0a41e47a70da1e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730114 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/bd99992gw.h | 102 ++++++++++++++++++++--------------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/driver/temp_sensor/bd99992gw.h b/driver/temp_sensor/bd99992gw.h index c461012c45..7bd3f547df 100644 --- a/driver/temp_sensor/bd99992gw.h +++ b/driver/temp_sensor/bd99992gw.h @@ -8,74 +8,74 @@ #ifndef __CROS_EC_TEMP_SENSOR_BD99992GW_H #define __CROS_EC_TEMP_SENSOR_BD99992GW_H -#define BD99992GW_I2C_ADDR_FLAGS 0x30 +#define BD99992GW_I2C_ADDR_FLAGS 0x30 /* ADC channels */ enum bd99992gw_adc_channel { - BD99992GW_ADC_CHANNEL_NONE = -1, - BD99992GW_ADC_CHANNEL_BATTERY = 0, - BD99992GW_ADC_CHANNEL_AC = 1, + BD99992GW_ADC_CHANNEL_NONE = -1, + BD99992GW_ADC_CHANNEL_BATTERY = 0, + BD99992GW_ADC_CHANNEL_AC = 1, BD99992GW_ADC_CHANNEL_SYSTHERM0 = 2, BD99992GW_ADC_CHANNEL_SYSTHERM1 = 3, BD99992GW_ADC_CHANNEL_SYSTHERM2 = 4, BD99992GW_ADC_CHANNEL_SYSTHERM3 = 5, - BD99992GW_ADC_CHANNEL_DIE_TEMP = 6, - BD99992GW_ADC_CHANNEL_VDC = 7, - BD99992GW_ADC_CHANNEL_COUNT = 8, + BD99992GW_ADC_CHANNEL_DIE_TEMP = 6, + BD99992GW_ADC_CHANNEL_VDC = 7, + BD99992GW_ADC_CHANNEL_COUNT = 8, }; /* Registers */ -#define BD99992GW_REG_IRQLVL1 0x02 -#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */ +#define BD99992GW_REG_IRQLVL1 0x02 +#define BD99992GW_IRQLVL1_ADC BIT(1) /* ADC IRQ asserted */ -#define BD99992GW_REG_ADC1INT 0x03 -#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */ +#define BD99992GW_REG_ADC1INT 0x03 +#define BD99992GW_ADC1INT_RND BIT(0) /* RR cycle completed */ -#define BD99992GW_REG_MADC1INT 0x0a -#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */ +#define BD99992GW_REG_MADC1INT 0x0a +#define BD99992GW_MADC1INT_RND BIT(0) /* RR cycle mask */ -#define BD99992GW_REG_IRQLVL1MSK 0x13 -#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */ +#define BD99992GW_REG_IRQLVL1MSK 0x13 +#define BD99992GW_IRQLVL1MSK_MADC BIT(1) /* ADC IRQ mask */ -#define BD99992GW_REG_ADC1CNTL1 0x80 -#define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */ -#define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */ -#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */ -#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */ -#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */ +#define BD99992GW_REG_ADC1CNTL1 0x80 +#define BD99992GW_ADC1CNTL1_SLP27MS (0x6 << 3) /* 27ms between pass */ +#define BD99992GW_ADC1CNTL1_NOLOOP (0x7 << 3) /* Single loop pass only */ +#define BD99992GW_ADC1CNTL1_ADPAUSE BIT(2) /* ADC pause */ +#define BD99992GW_ADC1CNTL1_ADSTRT BIT(1) /* ADC start */ +#define BD99992GW_ADC1CNTL1_ADEN BIT(0) /* ADC enable */ -#define BD99992GW_REG_ADC1CNTL2 0x81 -#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */ +#define BD99992GW_REG_ADC1CNTL2 0x81 +#define BD99992GW_ADC1CNTL2_ADCTHERM BIT(0) /* Enable ADC sequencing */ - /* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */ -#define BD99992GW_ADC_POINTER_REG_COUNT 8 -#define BD99992GW_REG_ADC1ADDR0 0x82 -#define BD99992GW_REG_ADC1ADDR1 0x83 -#define BD99992GW_REG_ADC1ADDR2 0x84 -#define BD99992GW_REG_ADC1ADDR3 0x85 -#define BD99992GW_REG_ADC1ADDR4 0x86 -#define BD99992GW_REG_ADC1ADDR5 0x87 -#define BD99992GW_REG_ADC1ADDR6 0x88 -#define BD99992GW_REG_ADC1ADDR7 0x89 -#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */ +/* ADC1 Pointer file regs - assign to proper bd99992gw_adc_channel */ +#define BD99992GW_ADC_POINTER_REG_COUNT 8 +#define BD99992GW_REG_ADC1ADDR0 0x82 +#define BD99992GW_REG_ADC1ADDR1 0x83 +#define BD99992GW_REG_ADC1ADDR2 0x84 +#define BD99992GW_REG_ADC1ADDR3 0x85 +#define BD99992GW_REG_ADC1ADDR4 0x86 +#define BD99992GW_REG_ADC1ADDR5 0x87 +#define BD99992GW_REG_ADC1ADDR6 0x88 +#define BD99992GW_REG_ADC1ADDR7 0x89 +#define BD99992GW_ADC1ADDR_STOP BIT(3) /* Last conversion channel */ /* Result registers */ -#define BD99992GW_REG_ADC1DATA0L 0x95 -#define BD99992GW_REG_ADC1DATA0H 0x96 -#define BD99992GW_REG_ADC1DATA1L 0x97 -#define BD99992GW_REG_ADC1DATA1H 0x98 -#define BD99992GW_REG_ADC1DATA2L 0x99 -#define BD99992GW_REG_ADC1DATA2H 0x9a -#define BD99992GW_REG_ADC1DATA3L 0x9b -#define BD99992GW_REG_ADC1DATA3H 0x9c -#define BD99992GW_REG_ADC1DATA4L 0x9d -#define BD99992GW_REG_ADC1DATA4H 0x9e -#define BD99992GW_REG_ADC1DATA5L 0x9f -#define BD99992GW_REG_ADC1DATA5H 0xa0 -#define BD99992GW_REG_ADC1DATA6L 0xa1 -#define BD99992GW_REG_ADC1DATA6H 0xa2 -#define BD99992GW_REG_ADC1DATA7L 0xa3 -#define BD99992GW_REG_ADC1DATA7H 0xa4 +#define BD99992GW_REG_ADC1DATA0L 0x95 +#define BD99992GW_REG_ADC1DATA0H 0x96 +#define BD99992GW_REG_ADC1DATA1L 0x97 +#define BD99992GW_REG_ADC1DATA1H 0x98 +#define BD99992GW_REG_ADC1DATA2L 0x99 +#define BD99992GW_REG_ADC1DATA2H 0x9a +#define BD99992GW_REG_ADC1DATA3L 0x9b +#define BD99992GW_REG_ADC1DATA3H 0x9c +#define BD99992GW_REG_ADC1DATA4L 0x9d +#define BD99992GW_REG_ADC1DATA4H 0x9e +#define BD99992GW_REG_ADC1DATA5L 0x9f +#define BD99992GW_REG_ADC1DATA5H 0xa0 +#define BD99992GW_REG_ADC1DATA6L 0xa1 +#define BD99992GW_REG_ADC1DATA6H 0xa2 +#define BD99992GW_REG_ADC1DATA7L 0xa3 +#define BD99992GW_REG_ADC1DATA7H 0xa4 /** * Get the latest value from the sensor. @@ -87,4 +87,4 @@ enum bd99992gw_adc_channel { */ int bd99992gw_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */ +#endif /* __CROS_EC_TEMP_SENSOR_BD99992GW_H */ -- cgit v1.2.1 From c075390f0c2e1358627c35debaddec94b8142e9e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:08 -0600 Subject: power/qcom.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b9884e6f87f4179392c27032bb717c8f5159f84 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727066 Reviewed-by: Jeremy Bettis --- power/qcom.c | 81 ++++++++++++++++++++++++++++-------------------------------- 1 file changed, 38 insertions(+), 43 deletions(-) diff --git a/power/qcom.c b/power/qcom.c index 107bdcb04d..5fcdeda98e 100644 --- a/power/qcom.c +++ b/power/qcom.c @@ -35,7 +35,7 @@ #include "task.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -75,13 +75,12 @@ const struct power_signal_info power_signal_list[] = { BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /* Masks for power signals */ -#define IN_POWER_GOOD POWER_SIGNAL_MASK(SC7X80_POWER_GOOD) -#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED) -#define IN_SUSPEND POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND) - +#define IN_POWER_GOOD POWER_SIGNAL_MASK(SC7X80_POWER_GOOD) +#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SC7X80_AP_RST_ASSERTED) +#define IN_SUSPEND POWER_SIGNAL_MASK(SC7X80_AP_SUSPEND) /* Long power key press to force shutdown */ -#define DELAY_FORCE_SHUTDOWN (8 * SECOND) +#define DELAY_FORCE_SHUTDOWN (8 * SECOND) /* * If the power button is pressed to turn on, then held for this long, we @@ -91,37 +90,37 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); * into the inner loop, waiting for next event to occur (power button * press or POWER_GOOD == 0). */ -#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) +#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) /* * After trigger PMIC power sequence, how long it triggers AP to turn on * or off. Observed that the worst case is ~150ms. Pick a safe vale. */ -#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC) +#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC) /* * After force off the switch cap, how long the PMIC/AP totally off. * Observed that the worst case is 2s. Pick a safe vale. */ -#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND) +#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND) /* Wait for polling the AP on signal */ -#define PMIC_POWER_AP_WAIT (1 * MSEC) +#define PMIC_POWER_AP_WAIT (1 * MSEC) /* The length of an issued low pulse to the PMIC_RESIN_L signal */ -#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC) +#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC) /* The timeout of the check if the system can boot AP */ -#define CAN_BOOT_AP_CHECK_TIMEOUT (1500 * MSEC) +#define CAN_BOOT_AP_CHECK_TIMEOUT (1500 * MSEC) /* Wait for polling if the system can boot AP */ -#define CAN_BOOT_AP_CHECK_WAIT (200 * MSEC) +#define CAN_BOOT_AP_CHECK_WAIT (200 * MSEC) /* The timeout of the check if the switchcap outputs good voltage */ -#define SWITCHCAP_PG_CHECK_TIMEOUT (100 * MSEC) +#define SWITCHCAP_PG_CHECK_TIMEOUT (100 * MSEC) /* Wait for polling if the switchcap outputs good voltage */ -#define SWITCHCAP_PG_CHECK_WAIT (6 * MSEC) +#define SWITCHCAP_PG_CHECK_WAIT (6 * MSEC) /* * Delay between power-on the system and power-on the PMIC. @@ -131,7 +130,7 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); * Measured on Herobrine IOB + Trogdor MLB, the delay takes ~200ms. Set * it with margin. */ -#define SYSTEM_POWER_ON_DELAY (300 * MSEC) +#define SYSTEM_POWER_ON_DELAY (300 * MSEC) /* * Delay between the PMIC power drop and power-off the system. @@ -139,17 +138,17 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); * this delay to the same value as the above power-on sequence, which * has much safer margin. */ -#define PMIC_POWER_OFF_DELAY (150 * MSEC) +#define PMIC_POWER_OFF_DELAY (150 * MSEC) /* The AP_RST_L transition count of a normal AP warm reset */ -#define EXPECTED_AP_RST_TRANSITIONS 3 +#define EXPECTED_AP_RST_TRANSITIONS 3 /* * The timeout of waiting the next AP_RST_L transition. We measured * the interval between AP_RST_L transitions is 130ms ~ 150ms. Pick * a safer value. */ -#define AP_RST_TRANSITION_TIMEOUT (450 * MSEC) +#define AP_RST_TRANSITION_TIMEOUT (450 * MSEC) /* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */ /* 1 if the power button was pressed last time we checked */ @@ -282,9 +281,11 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal) */ ap_rst_overdriven = 1; gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | - GPIO_SEL_1P8V | GPIO_OUT_HIGH); + GPIO_SEL_1P8V | + GPIO_OUT_HIGH); gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | - GPIO_SEL_1P8V | GPIO_OUT_LOW); + GPIO_SEL_1P8V | + GPIO_OUT_LOW); } /* Ignore the else clause, the pull-up rail drops. */ } else { @@ -315,10 +316,8 @@ void chipset_power_good_interrupt(enum gpio_signal signal) * When POWER_GOOD drops, high-Z both AP_RST_L and PS_HOLD * to restore their states. */ - gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | - GPIO_SEL_1P8V); - gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | - GPIO_SEL_1P8V); + gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | GPIO_SEL_1P8V); + gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | GPIO_SEL_1P8V); ap_rst_overdriven = 0; } power_signal_interrupt(signal); @@ -590,7 +589,7 @@ enum power_state power_chipset_init(void) if (reset_flags & EC_RESET_FLAG_AP_OFF) auto_power_on = 0; else if (!(reset_flags & EC_RESET_FLAG_EFS) && - (reset_flags & EC_RESET_FLAG_SYSJUMP)) + (reset_flags & EC_RESET_FLAG_SYSJUMP)) auto_power_on = 0; if (battery_is_present() == BP_YES) { @@ -666,7 +665,7 @@ static int power_is_enough(void) * waste the time and exit the loop. */ while (!system_can_boot_ap() && !charge_want_shutdown() && - get_time().val < poll_deadline.val) { + get_time().val < poll_deadline.val) { usleep(CAN_BOOT_AP_CHECK_WAIT); } @@ -910,8 +909,8 @@ static int command_fake_suspend(int argc, char **argv) if (argc < 2) { ccprintf("fake_suspend: %s\n", - fake_suspend == -1 ? "reset" - : (fake_suspend ? "on" : "off")); + fake_suspend == -1 ? "reset" : + (fake_suspend ? "on" : "off")); return EC_SUCCESS; } @@ -926,8 +925,7 @@ static int command_fake_suspend(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend, - "on/off/reset", +DECLARE_CONSOLE_COMMAND(fakesuspend, command_fake_suspend, "on/off/reset", "Fake the AP_SUSPEND signal"); /* Get system sleep state through GPIOs */ @@ -939,8 +937,7 @@ static inline int chipset_get_sleep_signal(void) return fake_suspend; } -__override void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { CPRINTS("Warning: Detected sleep hang! Waking host up!"); host_set_single_event(EC_HOST_EVENT_HANG_DETECT); @@ -964,9 +961,9 @@ static void handle_chipset_reset(void) } DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST); -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { CPRINTS("Handle sleep: %d", state); @@ -1110,9 +1107,9 @@ enum power_state power_handle_state(enum power_state state) shutdown_from_on = check_for_power_off_event(); if (shutdown_from_on) { return POWER_S0S3; - } else if (power_get_host_sleep_state() - == HOST_SLEEP_EVENT_S3_SUSPEND && - chipset_get_sleep_signal()) { + } else if (power_get_host_sleep_state() == + HOST_SLEEP_EVENT_S3_SUSPEND && + chipset_get_sleep_signal()) { return POWER_S0S3; } /* When receive the host event, trigger the RESUME hook. */ @@ -1200,7 +1197,7 @@ enum power_state_t { PSTATE_COUNT, }; -static const char * const state_name[] = { +static const char *const state_name[] = { "unknown", "off", "on", @@ -1232,6 +1229,4 @@ static int command_power(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(power, command_power, - "on/off", - "Turn AP power on/off"); +DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off"); -- cgit v1.2.1 From 32077c3f78106c77e7fedce210deb21b44ae13a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:41 -0600 Subject: core/cortex-m/include/mpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I057fcaa6f6be1404855c0f3b864b7bb1e0273ff6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729820 Reviewed-by: Jeremy Bettis --- core/cortex-m/include/mpu.h | 64 ++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/core/cortex-m/include/mpu.h b/core/cortex-m/include/mpu.h index 610728b501..177c74c6bd 100644 --- a/core/cortex-m/include/mpu.h +++ b/core/cortex-m/include/mpu.h @@ -14,7 +14,7 @@ /* * ARMv7-M SRAM region */ -#define CORTEX_M_SRAM_BASE 0x20000000 +#define CORTEX_M_SRAM_BASE 0x20000000 /* * Region assignment. 7 as the highest, a higher index has a higher priority. @@ -26,64 +26,64 @@ * made mutually exclusive. */ enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ + REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ + REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ + REGION_ROLLBACK = 10, /* For rollback */ }; -#define MPU_TYPE REG32(0xe000ed90) -#define MPU_CTRL REG32(0xe000ed94) -#define MPU_NUMBER REG32(0xe000ed98) -#define MPU_BASE REG32(0xe000ed9c) -#define MPU_SIZE REG16(0xe000eda0) -#define MPU_ATTR REG16(0xe000eda2) +#define MPU_TYPE REG32(0xe000ed90) +#define MPU_CTRL REG32(0xe000ed94) +#define MPU_NUMBER REG32(0xe000ed98) +#define MPU_BASE REG32(0xe000ed9c) +#define MPU_SIZE REG16(0xe000eda0) +#define MPU_ATTR REG16(0xe000eda2) /* * See ARM v7-M Architecture Reference Manual * Section B3.5.5 MPU Type Register, MPU_TYPE */ -#define MPU_TYPE_UNIFIED_MASK 0x00FF0001 -#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF) +#define MPU_TYPE_UNIFIED_MASK 0x00FF0001 +#define MPU_TYPE_REG_COUNT(t) (((t) >> 8) & 0xFF) -#define MPU_CTRL_PRIVDEFEN BIT(2) -#define MPU_CTRL_HFNMIENA BIT(1) -#define MPU_CTRL_ENABLE BIT(0) +#define MPU_CTRL_PRIVDEFEN BIT(2) +#define MPU_CTRL_HFNMIENA BIT(1) +#define MPU_CTRL_ENABLE BIT(0) /* * Minimum region size is 32 bytes, 5 bits of address space */ -#define MPU_SIZE_BITS_MIN 5 +#define MPU_SIZE_BITS_MIN 5 /* * XN (execute never) bit. It's bit 12 if accessed by halfword. * 0: XN off * 1: XN on */ -#define MPU_ATTR_XN BIT(12) +#define MPU_ATTR_XN BIT(12) /* AP bit. See table 3-5 of Stellaris LM4F232H5QC datasheet for details */ -#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ -#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */ -#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */ -#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */ -#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */ +#define MPU_ATTR_NO_NO (0 << 8) /* previleged no access, unprev no access */ +#define MPU_ATTR_RW_NO (1 << 8) /* previleged ReadWrite, unprev no access */ +#define MPU_ATTR_RW_RO (2 << 8) /* previleged ReadWrite, unprev Read-only */ +#define MPU_ATTR_RW_RW (3 << 8) /* previleged ReadWrite, unprev ReadWrite */ +#define MPU_ATTR_RO_NO (5 << 8) /* previleged Read-only, unprev no access */ /* Suggested value for TEX S/C/B bit. See table 3-6 of Stellaris LM4F232H5QC * datasheet and table 38 of STM32F10xxx Cortex-M3 programming manual. */ #ifndef MPU_ATTR_INTERNAL_SRAM -#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */ +#define MPU_ATTR_INTERNAL_SRAM 6 /* for Internal SRAM */ #endif #ifndef MPU_ATTR_FLASH_MEMORY -#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */ +#define MPU_ATTR_FLASH_MEMORY 2 /* for flash memory */ #endif /* Represent RW with at most 2 MPU regions. */ -- cgit v1.2.1 From 374264b2ce35ac94b1545e9a8f6ab09595793f28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:05 -0600 Subject: common/mock/usb_pd_dpm_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibee6143dccd13b51e0f58e921cff7ccc78f28715 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729691 Reviewed-by: Jeremy Bettis --- common/mock/usb_pd_dpm_mock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/mock/usb_pd_dpm_mock.c b/common/mock/usb_pd_dpm_mock.c index 005e0090a6..e46815ff75 100644 --- a/common/mock/usb_pd_dpm_mock.c +++ b/common/mock/usb_pd_dpm_mock.c @@ -36,12 +36,12 @@ void dpm_mode_exit_complete(int port) } void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { } void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, - uint8_t vdm_cmd) + uint8_t vdm_cmd) { } -- cgit v1.2.1 From 48290bdff60c145592d4f0ecf0dc3e2b79964c3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:54 -0600 Subject: chip/mchp/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I977bd0c1337103d5489ecb64511c66f05c8e90c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729307 Reviewed-by: Jeremy Bettis --- chip/mchp/pwm.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/chip/mchp/pwm.c b/chip/mchp/pwm.c index ae22f13ca5..0aa8a4701e 100644 --- a/chip/mchp/pwm.c +++ b/chip/mchp/pwm.c @@ -16,22 +16,16 @@ #include "tfdp_chip.h" #define CPUTS(outstr) cputs(CC_PWM, outstr) -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) /* Bit map of PWM channels that must remain active during low power idle. */ static uint32_t pwm_keep_awake_mask; /* Table of PWM PCR sleep enable register index and bit position. */ static const uint16_t pwm_pcr[] = { - MCHP_PCR_PWM0, - MCHP_PCR_PWM1, - MCHP_PCR_PWM2, - MCHP_PCR_PWM3, - MCHP_PCR_PWM4, - MCHP_PCR_PWM5, - MCHP_PCR_PWM6, - MCHP_PCR_PWM7, - MCHP_PCR_PWM8, + MCHP_PCR_PWM0, MCHP_PCR_PWM1, MCHP_PCR_PWM2, + MCHP_PCR_PWM3, MCHP_PCR_PWM4, MCHP_PCR_PWM5, + MCHP_PCR_PWM6, MCHP_PCR_PWM7, MCHP_PCR_PWM8, }; BUILD_ASSERT(ARRAY_SIZE(pwm_pcr) == MCHP_PWM_ID_MAX); @@ -90,8 +84,8 @@ void pwm_keep_awake(void) static void pwm_configure(int ch, int active_low, int clock_low) { MCHP_PWM_CFG(ch) = (15 << 3) /* divider = 16 */ - | (active_low ? BIT(2) : 0) - | (clock_low ? BIT(1) : 0); + | (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static void pwm_slp_en(int pwm_id, int sleep_en) -- cgit v1.2.1 From da1d83bff3de756b7f26362eecae66fb94b1cb04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:09 -0600 Subject: board/guybrush/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3479525ff42761712a66ffec0ce00c171c2bb0e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728437 Reviewed-by: Jeremy Bettis --- board/guybrush/board.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/guybrush/board.h b/board/guybrush/board.h index a749802cfa..64e1058b07 100644 --- a/board/guybrush/board.h +++ b/board/guybrush/board.h @@ -25,7 +25,7 @@ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCEL_BMA4XX -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* EC console commands */ #define CONFIG_CMD_ACCELS @@ -36,11 +36,11 @@ #define CONFIG_USB_MUX_ANX7451 #define CONFIG_USBC_RETIMER_ANX7451 -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Max Power = 100 W */ -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) /* USB Type A Features */ -- cgit v1.2.1 From 4a87e67011f697cf7206b8bb7727fbc98819399f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:25 -0600 Subject: board/kuldax/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2244b3c1a8eae77db28bdc71d9201355a93c6def Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728600 Reviewed-by: Jeremy Bettis --- board/kuldax/board.h | 120 +++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 65 deletions(-) diff --git a/board/kuldax/board.h b/board/kuldax/board.h index e73d1d8d4b..bb339a080e 100644 --- a/board/kuldax/board.h +++ b/board/kuldax/board.h @@ -21,11 +21,11 @@ /* HDMI CEC */ #define CONFIG_CEC #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT -#define CEC_GPIO_IN GPIO_HDMI_CEC_IN +#define CEC_GPIO_IN GPIO_HDMI_CEC_IN #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP /* USB Type A Features */ -#define USB_PORT_COUNT 4 +#define USB_PORT_COUNT 4 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -33,7 +33,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_PPC #define CONFIG_USB_PD_TCPM_RT1715 @@ -46,18 +46,18 @@ #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* The design should support up to 100W. */ /* TODO(b/197702356): Set the max PD to 60W now and change it * to 100W after we verify it. */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -65,58 +65,58 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD -#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD +#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD /* I2C Bus Configuration */ -#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 +#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_QI NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_QI NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -140,7 +140,7 @@ * TODO(b/197478860): Enable the fan control. We need * to check the sensor value and adjust the fan speed. */ - #define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL @@ -153,7 +153,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -171,7 +171,7 @@ enum adc_channel { ADC_TEMP_SENSOR_3_WIFI, ADC_TEMP_SENSOR_4_DIMM, ADC_VBUS, - ADC_PPVAR_IMON, /* ADC3 */ + ADC_PPVAR_IMON, /* ADC3 */ ADC_CH_COUNT }; @@ -183,28 +183,18 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C2_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT }; enum pwm_channel { - PWM_CH_LED_GREEN, /* PWM0 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED_RED, /* PWM2 */ + PWM_CH_LED_GREEN, /* PWM0 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED_RED, /* PWM2 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; extern void adp_connect_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 9947ec380852bb7adac76022e8fd12d15864da94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:33 -0600 Subject: baseboard/cherry/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I562bea82b7465bb07817b1d496bba70927dfdaab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727869 Reviewed-by: Jeremy Bettis --- baseboard/cherry/usb_pd_policy.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c index 1e7664bab9..6aa3eb0909 100644 --- a/baseboard/cherry/usb_pd_policy.c +++ b/baseboard/cherry/usb_pd_policy.c @@ -19,8 +19,8 @@ #error Cherry reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) /* The port that the aux channel is on. */ static enum { @@ -90,8 +90,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) dp_status[port] = payload[1]; - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -164,7 +163,7 @@ __override void svdm_exit_dp_mode(int port) svdm_set_hpd_gpio(port, 0); #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) baseboard_mst_enable_control(port, 0); -- cgit v1.2.1 From 2f8c06c6d8de56c2a7786220e1d3e29e21d15ad5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:16 -0600 Subject: zephyr/shim/src/usba.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic701b8005784bafa220ab795d3acc25e6091d363 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727466 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/usba.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/src/usba.c b/zephyr/shim/src/usba.c index e8e1ca373a..2b7d17bfda 100644 --- a/zephyr/shim/src/usba.c +++ b/zephyr/shim/src/usba.c @@ -10,18 +10,18 @@ #if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) -#define PIN(node_id, prop, idx) GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx)), +#define PIN(node_id, prop, idx) \ + GPIO_SIGNAL(DT_PHANDLE_BY_IDX(node_id, prop, idx)), BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0, - "No compatible USBA Port Enable instance found"); + "No compatible USBA Port Enable instance found"); #define USBA_ENABLE_PINS(inst) DT_INST_FOREACH_PROP_ELEM(inst, enable_pins, PIN) #if !IS_ENABLED(CONFIG_PLATFORM_EC_USB_PORT_ENABLE_DYNAMIC) const #endif -int usb_port_enable[] = { - DT_INST_FOREACH_STATUS_OKAY(USBA_ENABLE_PINS) -}; + int usb_port_enable[] = { DT_INST_FOREACH_STATUS_OKAY( + USBA_ENABLE_PINS) }; #endif /* DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT) */ -- cgit v1.2.1 From 8461d8b13081b8632852c195c8ca018129e7dc3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:36 -0600 Subject: board/volet/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifebaa77faf53f26014806c801be520c4f58fd981 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729061 Reviewed-by: Jeremy Bettis --- board/volet/board.h | 105 ++++++++++++++++++++++++---------------------------- 1 file changed, 48 insertions(+), 57 deletions(-) diff --git a/board/volet/board.h b/board/volet/board.h index c75eeed31f..c76cca4e58 100644 --- a/board/volet/board.h +++ b/board/volet/board.h @@ -13,7 +13,7 @@ /* Optional features */ #undef NPCX7_PWM1_SEL -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* * The RAM and flash size combination on the the NPCX797FC does not leave @@ -47,7 +47,7 @@ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* BMI160 Base accel/gyro */ #define CONFIG_ACCELGYRO_BMI160 -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ @@ -57,27 +57,27 @@ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) /* BMA253 Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_ACCEL_BMA255 #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY #ifdef BOARD_VOXEL_ECMODEENTRY @@ -88,11 +88,11 @@ #define CONFIG_USB_PD_TBT_COMPAT_MODE /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ #define CONFIG_USB_PD_FRS_PPC #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #undef CONFIG_USB_PD_TCPM_TUSB422 @@ -105,8 +105,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -118,44 +118,43 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -168,11 +167,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -181,11 +176,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From 350232bc378439aff3e1bb3fae293db4f78de34f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:28 -0600 Subject: include/rollback.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I994fe74e356fe46c12205d5a573225127b606bbb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730398 Reviewed-by: Jeremy Bettis --- include/rollback.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/rollback.h b/include/rollback.h index 8e439eaac3..b5e4867ed9 100644 --- a/include/rollback.h +++ b/include/rollback.h @@ -71,4 +71,4 @@ int board_get_entropy(void *buffer, int len); #endif -#endif /* __CROS_EC_ROLLBACK_H */ +#endif /* __CROS_EC_ROLLBACK_H */ -- cgit v1.2.1 From 426716a009ed2810e510f4028d892991e6cdd5b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:41 -0600 Subject: test/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I055b2367f130b6b5d0edc66b76b30018ea73a7c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730491 Reviewed-by: Jeremy Bettis --- test/cbi.c | 50 +++++++++++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/test/cbi.c b/test/cbi.c index 0ef2129377..58c29c4276 100644 --- a/test/cbi.c +++ b/test/cbi.c @@ -129,7 +129,7 @@ DECLARE_EC_TEST(test_not_found) DECLARE_EC_TEST(test_too_large) { - uint8_t buf[CBI_IMAGE_SIZE-1]; + uint8_t buf[CBI_IMAGE_SIZE - 1]; const int tag = 0xff; /* Data too large */ @@ -162,12 +162,12 @@ DECLARE_EC_TEST(test_all_tags) zassert_equal(cbi_set_board_info(CBI_TAG_SKU_ID, &d8, sizeof(d8)), EC_SUCCESS, NULL); count++; - zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM, - string, sizeof(string)), + zassert_equal(cbi_set_board_info(CBI_TAG_DRAM_PART_NUM, string, + sizeof(string)), EC_SUCCESS, NULL); count++; - zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME, - string, sizeof(string)), + zassert_equal(cbi_set_board_info(CBI_TAG_OEM_NAME, string, + sizeof(string)), EC_SUCCESS, NULL); count++; zassert_equal(cbi_set_board_info(CBI_TAG_MODEL_ID, &d8, sizeof(d8)), @@ -176,8 +176,7 @@ DECLARE_EC_TEST(test_all_tags) zassert_equal(cbi_set_board_info(CBI_TAG_FW_CONFIG, &d8, sizeof(d8)), EC_SUCCESS, NULL); count++; - zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8, - sizeof(d8)), + zassert_equal(cbi_set_board_info(CBI_TAG_PCB_SUPPLIER, &d8, sizeof(d8)), EC_SUCCESS, NULL); count++; zassert_equal(cbi_set_board_info(CBI_TAG_SSFC, &d8, sizeof(d8)), @@ -250,7 +249,7 @@ DECLARE_EC_TEST(test_bad_crc) zassert_equal(cbi_set_board_info(tag, &d8, sizeof(d8)), EC_SUCCESS, NULL); i2c_read8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, - offsetof(struct cbi_header, crc), &crc); + offsetof(struct cbi_header, crc), &crc); i2c_write8(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, offsetof(struct cbi_header, crc), ++crc); cbi_invalidate_cache(); @@ -263,24 +262,21 @@ DECLARE_EC_TEST(test_bad_crc) TEST_SUITE(test_suite_cbi) { - ztest_test_suite(test_cbi, - ztest_unit_test_setup_teardown(test_uint8, test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_uint32, test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_string, test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_not_found, - test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_too_large, - test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_all_tags, - test_setup, - test_teardown), - ztest_unit_test_setup_teardown(test_bad_crc, - test_setup, - test_teardown)); + ztest_test_suite( + test_cbi, + ztest_unit_test_setup_teardown(test_uint8, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_uint32, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_string, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_not_found, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_too_large, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_all_tags, test_setup, + test_teardown), + ztest_unit_test_setup_teardown(test_bad_crc, test_setup, + test_teardown)); ztest_run_test_suite(test_cbi); } -- cgit v1.2.1 From ee5265d5aabb5deb784907f20cd6082abedbb30f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:00 -0600 Subject: board/poppy/base_detect_lux.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I72f12a7176d4188467e37f3aa9a4003c8715a45d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728841 Reviewed-by: Jeremy Bettis --- board/poppy/base_detect_lux.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/poppy/base_detect_lux.c b/board/poppy/base_detect_lux.c index c348eb681d..f1be68d42d 100644 --- a/board/poppy/base_detect_lux.c +++ b/board/poppy/base_detect_lux.c @@ -20,8 +20,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* Base detection and debouncing */ #define BASE_DETECT_DEBOUNCE_US (20 * MSEC) @@ -44,7 +44,7 @@ #define BASE_DISCONNECTED_CONNECT_MAX_MV 600 #define BASE_DISCONNECTED_MIN_MV 2800 -#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT+1) +#define BASE_DISCONNECTED_MAX_MV (ADC_MAX_VOLT + 1) /* * When base is connected, then gets disconnected: @@ -93,7 +93,7 @@ int board_is_base_connected(void) void board_enable_base_power(int enable) { gpio_set_level(GPIO_PPVAR_VAR_BASE, - enable && current_base_status == BASE_CONNECTED); + enable && current_base_status == BASE_CONNECTED); } /* @@ -181,8 +181,7 @@ static void base_detect_deferred(void) retry: print_base_detect_value("status unclear", v); /* Unclear base status, schedule again in a while. */ - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_RETRY_US); + hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_RETRY_US); } void base_detect_interrupt(enum gpio_signal signal) @@ -216,7 +215,7 @@ static void base_init(void) hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_DEBOUNCE_US); gpio_enable_interrupt(GPIO_BASE_DET_A); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { @@ -230,7 +229,7 @@ void base_force_state(enum ec_set_base_state_cmd state) CPRINTS("BD forced disconnected"); } else { hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_DEBOUNCE_US); + BASE_DETECT_DEBOUNCE_US); gpio_enable_interrupt(GPIO_BASE_DET_A); CPRINTS("BD forced reset"); } -- cgit v1.2.1 From 8ce79ce9352b2cd9fedb0047aaf3725dfc7d36c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:01 -0600 Subject: board/banshee/tune_mp2964.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f5edd79d7e070321bb8e378ddb5682313282c02 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728025 Reviewed-by: Jeremy Bettis --- board/banshee/tune_mp2964.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/banshee/tune_mp2964.c b/board/banshee/tune_mp2964.c index f67caa587e..ee4de6d3c4 100644 --- a/board/banshee/tune_mp2964.c +++ b/board/banshee/tune_mp2964.c @@ -12,10 +12,10 @@ #include "mp2964.h" const static struct mp2964_reg_val rail_a[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ + { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ }; const static struct mp2964_reg_val rail_b[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ + { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ }; static void mp2964_on_startup(void) @@ -33,11 +33,10 @@ static void mp2964_on_startup(void) ccprintf("%s: attempting to tune PMIC\n", __func__); - status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a), - rail_b, ARRAY_SIZE(rail_b)); + status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a), rail_b, + ARRAY_SIZE(rail_b)); if (status != EC_SUCCESS) ccprintf("%s: could not update all settings\n", __func__); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup, - HOOK_PRIO_FIRST); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup, HOOK_PRIO_FIRST); -- cgit v1.2.1 From bd464d4c9b0bd05107b0f47c38261928c3fa5e77 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:39 -0600 Subject: board/nightfury/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8452dcba782669ea0d5967bfc608d707847a59d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728747 Reviewed-by: Jeremy Bettis --- board/nightfury/board.c | 83 +++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 47 deletions(-) diff --git a/board/nightfury/board.c b/board/nightfury/board.c index faaea01042..d601265b68 100644 --- a/board/nightfury/board.c +++ b/board/nightfury/board.c @@ -44,8 +44,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void ppc_interrupt(enum gpio_signal signal) { @@ -101,23 +101,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 3, - .flags = 0, - .freq = 10000 - }, - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -186,22 +179,18 @@ static struct opt3001_drv_data_t g_opt3001_data = { static struct stprivate_data g_lis2ds_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation * matrix can't be tested properly. This needs to be revisited after EVT to make * sure the rotation matrix for the lid sensor is correct. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -341,49 +330,49 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /**********************************************************************/ /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_IA", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "IA", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "GT", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "IA", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "GT", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* Nightfury Temperature sensors */ /* * TODO(b/138578073): These setting need to be reviewed and set appropriately - * for Nightfury. They matter when the EC is controlling the fan as opposed to DPTF - * control. + * for Nightfury. They matter when the EC is controlling the fan as opposed to + * DPTF control. */ /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ -- cgit v1.2.1 From 10da1b7f043ace28c7147c976dd24c83a6b447a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:24 -0600 Subject: chip/stm32/usart_host_command.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8da5c862b0bd4b804df77d2ce462d2be7cbc0224 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729544 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_host_command.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/usart_host_command.h b/chip/stm32/usart_host_command.h index ee41d8a59b..d73930c902 100644 --- a/chip/stm32/usart_host_command.h +++ b/chip/stm32/usart_host_command.h @@ -6,7 +6,7 @@ #ifndef __CROS_EC_USART_HOST_COMMAND_H #define __CROS_EC_USART_HOST_COMMAND_H -#include /* For va_list */ +#include /* For va_list */ #include "common.h" #include "gpio.h" #include "host_command.h" -- cgit v1.2.1 From 3723ad28a1c10855d1daf1f7dc910b44855dffa2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:46 -0600 Subject: board/bugzzy/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie867b4674d6dfea70d175a2278a88c7755843fed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728108 Reviewed-by: Jeremy Bettis --- board/bugzzy/battery.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/bugzzy/battery.c b/board/bugzzy/battery.c index 23318890f3..47b88fb21e 100644 --- a/board/bugzzy/battery.c +++ b/board/bugzzy/battery.c @@ -85,7 +85,7 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_SDI; int charger_profile_override(struct charge_state_data *curr) { if ((chipset_in_state(CHIPSET_STATE_ON)) && - (curr->requested_current > CHARGING_CURRENT_45C)) + (curr->requested_current > CHARGING_CURRENT_45C)) curr->requested_current = CHARGING_CURRENT_45C; return 0; @@ -115,7 +115,7 @@ static void reduce_input_voltage_when_full(void) int port; if (charge_get_percent() == 100 && - chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { + chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { if (max_pd_voltage_mv != PD_VOLTAGE_WHEN_FULL) { saved_input_voltage = max_pd_voltage_mv; max_pd_voltage_mv = PD_VOLTAGE_WHEN_FULL; @@ -131,5 +131,4 @@ static void reduce_input_voltage_when_full(void) pd_set_external_voltage_limit(port, max_pd_voltage_mv); } } -DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_SECOND, reduce_input_voltage_when_full, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From b34ed18b70f230d3beed3f15bcb1dd721b1c41ef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:55 -0600 Subject: board/ghost/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2a99827fa793f97cd9b195a6d2f92be19c44cc8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728408 Reviewed-by: Jeremy Bettis --- board/ghost/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/ghost/usbc_config.h b/board/ghost/usbc_config.h index 047d094c6d..da347946be 100644 --- a/board/ghost/usbc_config.h +++ b/board/ghost/usbc_config.h @@ -11,13 +11,9 @@ #include "baseboard_usbc_config.h" #ifndef CONFIG_ZEPHYR -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 #endif -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; #endif /* __CROS_EC_USBC_CONFIG_H */ -- cgit v1.2.1 From ec5eacc909fc4696532f95a8fced2e8a308e7dd1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:12 -0600 Subject: board/corori/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0c11a32a07f8952fe34910351489fecee9a8eb9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728162 Reviewed-by: Jeremy Bettis --- board/corori/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/corori/cbi_ssfc.h b/board/corori/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/corori/cbi_ssfc.h +++ b/board/corori/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 99fbb2b502a28b0809400fb6d5364b77f283d4ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:32 -0600 Subject: board/volteer/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5147caa945e052cd1f6ff7c4653f7dcb25f4bd5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729093 Reviewed-by: Jeremy Bettis --- board/volteer/usbc_config.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/volteer/usbc_config.h b/board/volteer/usbc_config.h index 55dfce7621..a13944250a 100644 --- a/board/volteer/usbc_config.h +++ b/board/volteer/usbc_config.h @@ -8,11 +8,7 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /* Configure the USB3 daughterboard type */ void config_usb3_db_type(void); -- cgit v1.2.1 From c24f533c627da2c4ec1d926f552000824733a513 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:19 -0600 Subject: board/volteer/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d9434efaee471f17d7379c4c520af530e2f6520 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729090 Reviewed-by: Jeremy Bettis --- board/volteer/board.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/volteer/board.c b/board/volteer/board.c index 0e7a1d21e0..352f32d026 100644 --- a/board/volteer/board.c +++ b/board/volteer/board.c @@ -64,7 +64,7 @@ __override struct keyboard_scan_config keyscan_config = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -100,8 +100,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -128,8 +128,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From afec3ebc91b210b48160b5b1a3f2bca5e9714936 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:33 -0600 Subject: board/oak/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If799d66dab3c0fe46bc51f4bf453b6b9106e4818 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728792 Reviewed-by: Jeremy Bettis --- board/oak/led.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/board/oak/led.c b/board/oak/led.c index 877f115a12..686a7d68f8 100644 --- a/board/oak/led.c +++ b/board/oak/led.c @@ -14,9 +14,7 @@ #include "util.h" #include "system.h" -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -27,7 +25,7 @@ enum led_color { BAT_LED_AMBER, PWR_LED_GREEN, PWR_LED_ORANGE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int bat_led_set(enum led_color color, int on) @@ -113,7 +111,7 @@ static void oak_led_set_power(int board_version) power_second++; - switch(board_version) { + switch (board_version) { case OAK_REV3: case OAK_REV4: /* @@ -131,8 +129,7 @@ static void oak_led_set_power(int board_version) bat_led_set(PWR_LED_ORANGE, 0); } else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) { bat_led_set(PWR_LED_GREEN, 0); - bat_led_set(PWR_LED_ORANGE, - (power_second & 3) ? 0 : 1); + bat_led_set(PWR_LED_ORANGE, (power_second & 3) ? 0 : 1); } break; default: @@ -146,7 +143,7 @@ static void oak_led_set_battery(int board_version) battery_second++; - switch(board_version) { + switch (board_version) { case OAK_REV3: case OAK_REV4: /* @@ -169,10 +166,10 @@ static void oak_led_set_battery(int board_version) bat_led_set(BAT_LED_GREEN, 0); if (charge_get_percent() < 3) bat_led_set(BAT_LED_RED, - (battery_second & 1) ? 0 : 1); + (battery_second & 1) ? 0 : 1); else if (charge_get_percent() < 10) bat_led_set(BAT_LED_RED, - (battery_second & 3) ? 0 : 1); + (battery_second & 3) ? 0 : 1); else bat_led_set(BAT_LED_RED, 0); break; @@ -191,7 +188,8 @@ static void oak_led_set_battery(int board_version) default: /* * Put power control here since we are using the "battery" LED. - * This allows LED autocontrol to be turned off by cmd during factory test. + * This allows LED autocontrol to be turned off by cmd during + * factory test. * * PWR LED behavior: * Power on: Green @@ -205,8 +203,8 @@ static void oak_led_set_battery(int board_version) else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) { int cycle_time = 4; /* Oak rev5 with GlaDOS ID has a extremely power - * comsuming LED. Increase LED blink cycle time to reduce - * S3 power comsuption. */ + * comsuming LED. Increase LED blink cycle time to + * reduce S3 power comsuption. */ if (board_version >= OAK_REV5) cycle_time = 10; bat_led_set(BAT_LED_GREEN, @@ -231,10 +229,10 @@ static void oak_led_set_battery(int board_version) case PWR_STATE_DISCHARGE: if (charge_get_percent() < 3) bat_led_set(BAT_LED_ORANGE, - (battery_second & 1) ? 0 : 1); + (battery_second & 1) ? 0 : 1); else if (charge_get_percent() < 10) bat_led_set(BAT_LED_ORANGE, - (battery_second & 3) ? 0 : 1); + (battery_second & 3) ? 0 : 1); else bat_led_set(BAT_LED_ORANGE, 0); break; -- cgit v1.2.1 From e29a0f79e0861f7026032067e75b7088c0c3efa9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:24 -0600 Subject: common/shared_mem.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2fff46d9ec85aed42557472576f332cc0b48dd0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729749 Reviewed-by: Jeremy Bettis --- common/shared_mem.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/shared_mem.c b/common/shared_mem.c index e435408d3b..e1d87fdf84 100644 --- a/common/shared_mem.c +++ b/common/shared_mem.c @@ -69,7 +69,6 @@ static int command_shmem(int argc, char **argv) ccprintf("Max: %6d\n", max_used); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(shmem, command_shmem, NULL, "Print shared memory stats"); #endif -- cgit v1.2.1 From 64d3404d3e8835207868efa67fd98c49433aa11a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:07 -0600 Subject: common/mock/usb_pe_sm_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46765ab57d3155f1ba95543fc644114101477e1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729692 Reviewed-by: Jeremy Bettis --- common/mock/usb_pe_sm_mock.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/mock/usb_pe_sm_mock.c b/common/mock/usb_pe_sm_mock.c index 8d1a25324b..0488ff59b0 100644 --- a/common/mock/usb_pe_sm_mock.c +++ b/common/mock/usb_pe_sm_mock.c @@ -23,7 +23,6 @@ struct mock_pe_port_t mock_pe_port[CONFIG_USB_PD_PORT_MAX_COUNT]; - /** * Resets all mock PE ports to initial values */ @@ -31,7 +30,7 @@ void mock_pe_port_reset(void) { int port; - for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) { + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) { mock_pe_port[port].mock_pe_error = -1; /* These mock variable only get set to 1 by various functions, * so initialize them to 0. Tests can verify they are still 0 @@ -93,7 +92,7 @@ bool pe_in_local_ams(int port) return false; } -const uint32_t * const pd_get_src_caps(int port) +const uint32_t *const pd_get_src_caps(int port) { return NULL; } @@ -108,7 +107,8 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps) } void pd_request_power_swap(int port) -{} +{ +} int pd_get_rev(int port, enum tcpci_msg_type type) { -- cgit v1.2.1 From 64a831ac86c1b81b80c102a052b7212f426e414b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:07 -0600 Subject: common/led_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c5de1ccc4d9d7a340896889096604e08b5344d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729645 Reviewed-by: Jeremy Bettis --- common/led_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/led_common.c b/common/led_common.c index e890ad71bb..69fb120fe9 100644 --- a/common/led_common.c +++ b/common/led_common.c @@ -91,8 +91,8 @@ static enum ec_status led_command_control(struct host_cmd_handler_args *args) } DECLARE_HOST_COMMAND(EC_CMD_LED_CONTROL, led_command_control, EC_VER_MASK(1)); -__attribute__((weak)) -void led_control(enum ec_led_id led_id, enum ec_led_state state) +__attribute__((weak)) void led_control(enum ec_led_id led_id, + enum ec_led_state state) { /* * Default weak implementation that does not affect the state of -- cgit v1.2.1 From 0850ea967da4296eae8e663a0f6a9620e57267c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:00 -0600 Subject: baseboard/intelrvp/chg_usb_pd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44d391ea28a8e6e906b68c100150cab3664df365 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727896 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/chg_usb_pd.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/baseboard/intelrvp/chg_usb_pd.c b/baseboard/intelrvp/chg_usb_pd.c index 1eb82b6688..5c277720d2 100644 --- a/baseboard/intelrvp/chg_usb_pd.c +++ b/baseboard/intelrvp/chg_usb_pd.c @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) bool is_typec_port(int port) { @@ -43,8 +43,8 @@ static void board_dc_jack_handle(void) /* System is booted from DC Jack */ if (board_dc_jack_present()) { - charge_dc_jack.current = (PD_MAX_POWER_MW * 1000) / - DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; } else { charge_dc_jack.current = 0; @@ -52,7 +52,7 @@ static void board_dc_jack_handle(void) } charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, &charge_dc_jack); + DEDICATED_CHARGE_PORT, &charge_dc_jack); } #endif @@ -75,7 +75,7 @@ static void board_charge_init(void) for (port = 0; port < CHARGE_PORT_COUNT; port++) { for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; supplier++) charge_manager_update_charge(supplier, port, - &charge_init); + &charge_init); } #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 @@ -88,8 +88,7 @@ int board_set_active_charge_port(int port) { int i; /* charge port is a realy physical port */ - int is_real_port = (port >= 0 && - port < CHARGE_PORT_COUNT); + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); /* check if we are source vbus on that port */ int source = board_vbus_source_enabled(port); @@ -127,9 +126,9 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From d790fc2c9246f32d5e30fb46fd38f651d4e043a3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:23 -0600 Subject: board/jinlon/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1af66eef35d0967fa290e2cdc9d41ab0ccaa275d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728475 Reviewed-by: Jeremy Bettis --- board/jinlon/board.h | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/board/jinlon/board.h b/board/jinlon/board.h index d4ecf9bbd6..cbd8da5d62 100644 --- a/board/jinlon/board.h +++ b/board/jinlon/board.h @@ -32,10 +32,10 @@ * Jinlon's battery takes several seconds to come back out of its disconnect * state (~4 seconds, but give it 6 for margin). */ -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6 -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 /* Sensors */ /* BMI160 Base accel/gyro */ @@ -117,16 +117,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -134,9 +134,9 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC2 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC2 */ ADC_CH_COUNT }; @@ -147,12 +147,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_FAN2, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From f03e5183fbe8c3074c07c26e780055846a2e125e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:14 -0600 Subject: test/usb_pe_drp_noextended.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I90c0a0a2d38485b248db28754eeda08dfb5d7099 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730543 Reviewed-by: Jeremy Bettis --- test/usb_pe_drp_noextended.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/test/usb_pe_drp_noextended.c b/test/usb_pe_drp_noextended.c index 68da7426e2..2e5593fea3 100644 --- a/test/usb_pe_drp_noextended.c +++ b/test/usb_pe_drp_noextended.c @@ -24,11 +24,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .driver = &mock_usb_mux_driver, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .driver = &mock_usb_mux_driver, +} }; void before_test(void) { -- cgit v1.2.1 From 76e80a83deafed5f8458b1207f7a05a9ed85a7a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:37 -0600 Subject: zephyr/projects/corsola/src/kingler/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01c8a39740c74641081b1e036dd0d49be9584789 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730740 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/kingler/usbc_config.c | 61 +++++++++++------------ 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index 42aa0a31d6..4b48d9fd96 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -31,9 +31,8 @@ #endif #include "gpio.h" - -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { @@ -61,16 +60,12 @@ struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv - }, - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_USB_C1, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv - } + [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, + .drv = &nx20p348x_drv }, + [USBC_PORT_C1] = { .i2c_port = I2C_PORT_USB_C1, + .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, + .drv = &nx20p348x_drv } }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -79,9 +74,8 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* USB Mux C1 : board_init of PS8743 */ static int ps8743_tune_mux(const struct usb_mux *me) { - ps8743_tune_usb_eq(me, - PS8743_USB_EQ_TX_3_6_DB, - PS8743_USB_EQ_RX_16_0_DB); + ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, + PS8743_USB_EQ_RX_16_0_DB); return EC_SUCCESS; } @@ -90,10 +84,9 @@ void board_usb_mux_init(void) { if (corsola_get_db_type() == CORSOLA_DB_TYPEC) { /* Disable DCI function. This is not needed for ARM. */ - ps8743_field_update(&usb_muxes[1], - PS8743_REG_DCI_CONFIG_2, - PS8743_AUTO_DCI_MODE_MASK, - PS8743_AUTO_DCI_MODE_FORCE_USB); + ps8743_field_update(&usb_muxes[1], PS8743_REG_DCI_CONFIG_2, + PS8743_AUTO_DCI_MODE_MASK, + PS8743_AUTO_DCI_MODE_FORCE_USB); } } DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); @@ -169,7 +162,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) { usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); @@ -188,20 +181,23 @@ __override int board_rt1718s_init(int port) /* gpio1 low, gpio2 output high when receiving frs signal */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO1_VBUS_CTRL, - RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, 0)); + RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS, + 0)); RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_GPIO2_VBUS_CTRL, - RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, 0xFF)); + RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS, + 0xFF)); /* Trigger GPIO 1/2 change when FRS signal received */ - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL3, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_FRS_CTRL3, + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1, - RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | + RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 | RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1)); /* Set FRS signal detect time to 46.875us */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_FRS_CTRL1, - RT1718S_FRS_CTRL1_FRSWAPRX_MASK, - 0xFF)); + RT1718S_FRS_CTRL1_FRSWAPRX_MASK, + 0xFF)); return EC_SUCCESS; } @@ -215,13 +211,12 @@ __override int board_rt1718s_set_frs_enable(int port, int enable) * FRS path. */ rt1718s_gpio_set_flags(port, GPIO_EN_USB_C1_FRS, - enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); + enable ? GPIO_OUT_HIGH : GPIO_OUT_LOW); return EC_SUCCESS; } void board_reset_pd_mcu(void) { - CPRINTS("Resetting TCPCs..."); /* reset C0 ANX3447 */ /* Assert reset */ @@ -315,15 +310,15 @@ uint16_t tcpc_get_alert_status(void) uint16_t status = 0; if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst))) { + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst))) { status |= PD_STATUS_TCPC_ALERT_0; } } if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { return status |= PD_STATUS_TCPC_ALERT_1; } return status; -- cgit v1.2.1 From 08555f2711e95caa06d0f4fc482a853acaf0935e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:37 -0600 Subject: chip/it83xx/adc_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic681124be58f7025b7450a385c30a49ac01718b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729192 Reviewed-by: Jeremy Bettis --- chip/it83xx/adc_chip.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/it83xx/adc_chip.h b/chip/it83xx/adc_chip.h index 15a8e68e94..3656aec001 100644 --- a/chip/it83xx/adc_chip.h +++ b/chip/it83xx/adc_chip.h @@ -61,13 +61,13 @@ enum vcmp_scan_period { VCMP_SCAN_PERIOD_400US = 0x30, VCMP_SCAN_PERIOD_600US = 0x40, VCMP_SCAN_PERIOD_800US = 0x50, - VCMP_SCAN_PERIOD_1MS = 0x60, + VCMP_SCAN_PERIOD_1MS = 0x60, VCMP_SCAN_PERIOD_1_5MS = 0x70, - VCMP_SCAN_PERIOD_2MS = 0x80, + VCMP_SCAN_PERIOD_2MS = 0x80, VCMP_SCAN_PERIOD_2_5MS = 0x90, - VCMP_SCAN_PERIOD_3MS = 0xA0, - VCMP_SCAN_PERIOD_4MS = 0xB0, - VCMP_SCAN_PERIOD_5MS = 0xC0, + VCMP_SCAN_PERIOD_3MS = 0xA0, + VCMP_SCAN_PERIOD_4MS = 0xB0, + VCMP_SCAN_PERIOD_5MS = 0xC0, }; /* Data structure to define ADC channel control registers. */ @@ -95,8 +95,8 @@ struct vcmp_ctrl_t { }; /* supported flags (member "flag" in struct vcmp_t) for voltage comparator */ -#define GREATER_THRESHOLD BIT(0) -#define LESS_EQUAL_THRESHOLD BIT(1) +#define GREATER_THRESHOLD BIT(0) +#define LESS_EQUAL_THRESHOLD BIT(1) /* Data structure for board to define voltage comparator list. */ struct vcmp_t { -- cgit v1.2.1 From f89dc808e2ccc3b8e3586d67b2229e34e4df7d09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:00 -0600 Subject: board/trogdor/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icb9c4b2dd848d68670876212d353bbe74d2b96ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729035 Reviewed-by: Jeremy Bettis --- board/trogdor/board.c | 113 ++++++++++++++++++-------------------------------- 1 file changed, 41 insertions(+), 72 deletions(-) diff --git a/board/trogdor/board.c b/board/trogdor/board.c index 7036e57c4a..089442c5bc 100644 --- a/board/trogdor/board.c +++ b/board/trogdor/board.c @@ -26,8 +26,8 @@ #include "usbc_config.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -39,10 +39,8 @@ __override struct keyboard_scan_config keyscan_config = { * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key); * as it still uses the legacy location (KSO_01/KSI_00). */ - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -53,41 +51,31 @@ __override struct keyboard_scan_config keyscan_config = { /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -95,37 +83,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -177,17 +150,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 0562326b5cfad3eb49f66a3ce776620529335677 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:03 -0600 Subject: board/kano/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I439082690348610901b05534efa994576d7b88db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728524 Reviewed-by: Jeremy Bettis --- board/kano/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kano/usbc_config.c b/board/kano/usbc_config.c index 0167646790..14df81b696 100644 --- a/board/kano/usbc_config.c +++ b/board/kano/usbc_config.c @@ -31,8 +31,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From 01dd6460bcf17abcc3fea8a267870e23013fb1d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:51 -0600 Subject: include/bluetooth_le.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a39b73c570babda522f690bb263c76ae2a4bb64 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730212 Reviewed-by: Jeremy Bettis --- include/bluetooth_le.h | 242 ++++++++++++++++++++++++------------------------- 1 file changed, 119 insertions(+), 123 deletions(-) diff --git a/include/bluetooth_le.h b/include/bluetooth_le.h index 286653dda6..04d5be8bf6 100644 --- a/include/bluetooth_le.h +++ b/include/bluetooth_le.h @@ -23,69 +23,67 @@ #include "common.h" #include "util.h" -#define BLUETOOTH_ADDR_OCTETS 6 +#define BLUETOOTH_ADDR_OCTETS 6 /* * GAP assigned numbers * https://www.bluetooth.org/en-us/specification/ * assigned-numbers/generic-access-profile */ -#define GAP_FLAGS 0x01 -#define GAP_INCOMP_16_BIT_UUID 0x02 -#define GAP_COMP_16_BIT_UUID 0x03 -#define GAP_INCOMP_32_BIT_UUID 0x04 -#define GAP_COMP_32_BIT_UUID 0x05 -#define GAP_INCOMP_128_BIT_UUID 0x06 -#define GAP_COMP_128_BIT_UUID 0x07 -#define GAP_SHORT_NAME 0x08 -#define GAP_COMPLETE_NAME 0x09 -#define GAP_TX_POWER_LEVEL 0x0A -#define GAP_CLASS_OF_DEVICE 0x0D -#define GAP_SIMPLE_PAIRING_HASH 0x0E -#define GAP_SIMPLE_PAIRING_HASH_192 0x0E -#define GAP_SIMPLE_PAIRING_RAND 0x0F -#define GAP_SIMPLE_PAIRING_RAND_192 0x0F -#define GAP_DEVICE_ID 0x10 -#define GAP_SECURITY_MANAGER_TK 0x10 -#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11 -#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 -#define GAP_SERVICE_SOLICITATION_UUID_16 0x14 -#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F -#define GAP_SERVICE_SOLICITATION_UUID_128 0x15 -#define GAP_SERVICE_DATA 0x16 -#define GAP_SERVICE_DATA_UUID_16 0x16 -#define GAP_SERVICE_DATA_UUID_32 0x20 -#define GAP_SERVICE_DATA_UUID_128 0x21 -#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22 -#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23 -#define GAP_PUBLIC_TARGET_ADDRESS 0x17 -#define GAP_RANDOM_TARGET_ADDRESS 0x18 -#define GAP_APPEARANCE 0x19 -#define GAP_ADVERTISING_INTERVAL 0x1A -#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B -#define GAP_LE_ROLE 0x1C -#define GAP_SIMPLE_PAIRING_HASH_256 0x1D -#define GAP_SIMPLE_PAIRING_RAND_256 0x1E -#define GAP_3D_INFORMATION_DATA 0x3D -#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF - +#define GAP_FLAGS 0x01 +#define GAP_INCOMP_16_BIT_UUID 0x02 +#define GAP_COMP_16_BIT_UUID 0x03 +#define GAP_INCOMP_32_BIT_UUID 0x04 +#define GAP_COMP_32_BIT_UUID 0x05 +#define GAP_INCOMP_128_BIT_UUID 0x06 +#define GAP_COMP_128_BIT_UUID 0x07 +#define GAP_SHORT_NAME 0x08 +#define GAP_COMPLETE_NAME 0x09 +#define GAP_TX_POWER_LEVEL 0x0A +#define GAP_CLASS_OF_DEVICE 0x0D +#define GAP_SIMPLE_PAIRING_HASH 0x0E +#define GAP_SIMPLE_PAIRING_HASH_192 0x0E +#define GAP_SIMPLE_PAIRING_RAND 0x0F +#define GAP_SIMPLE_PAIRING_RAND_192 0x0F +#define GAP_DEVICE_ID 0x10 +#define GAP_SECURITY_MANAGER_TK 0x10 +#define GAP_SECURITY_MANAGER_OOB_FLAGS 0x11 +#define GAP_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 +#define GAP_SERVICE_SOLICITATION_UUID_16 0x14 +#define GAP_SERVICE_SOLICITATION_UUID_32 0x1F +#define GAP_SERVICE_SOLICITATION_UUID_128 0x15 +#define GAP_SERVICE_DATA 0x16 +#define GAP_SERVICE_DATA_UUID_16 0x16 +#define GAP_SERVICE_DATA_UUID_32 0x20 +#define GAP_SERVICE_DATA_UUID_128 0x21 +#define GAP_LE_SECURE_CONNECTIONS_CONFIRMATION 0x22 +#define GAP_LE_SECURE_CONNECTIONS_RAND 0x23 +#define GAP_PUBLIC_TARGET_ADDRESS 0x17 +#define GAP_RANDOM_TARGET_ADDRESS 0x18 +#define GAP_APPEARANCE 0x19 +#define GAP_ADVERTISING_INTERVAL 0x1A +#define GAP_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B +#define GAP_LE_ROLE 0x1C +#define GAP_SIMPLE_PAIRING_HASH_256 0x1D +#define GAP_SIMPLE_PAIRING_RAND_256 0x1E +#define GAP_3D_INFORMATION_DATA 0x3D +#define GAP_MANUFACTURER_SPECIFIC_DATA 0xFF /* org.bluetooth.characteristic.gap.appearance.xml */ -#define GAP_APPEARANCE_HID_KEYBOARD 961 +#define GAP_APPEARANCE_HID_KEYBOARD 961 /* org.bluetooth.service.human_interface_device.xml */ -#define GATT_SERVICE_HID_UUID 0x1812 +#define GATT_SERVICE_HID_UUID 0x1812 /* Bluetooth Core Supplement v5 */ /* Bluetooth Core Supplement v5 1.3 */ -#define GAP_FLAGS_LE_LIM_DISC 0x01 -#define GAP_FLAGS_LE_GEN_DISC 0x02 -#define GAP_FLAGS_LE_NO_BR_EDR 0x04 +#define GAP_FLAGS_LE_LIM_DISC 0x01 +#define GAP_FLAGS_LE_GEN_DISC 0x02 +#define GAP_FLAGS_LE_NO_BR_EDR 0x04 /* Bluetooth Core Supplement v5 1.3 */ - /* BLE 4.1 Vol 6 section 2.3 pg 38+ */ /* Advertising PDU Header @@ -103,49 +101,48 @@ struct ble_adv_header { uint8_t length; }; -#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0 -#define BLE_ADV_HEADER_TXADD_SHIFT 6 -#define BLE_ADV_HEADER_RXADD_SHIFT 7 -#define BLE_ADV_HEADER_LENGTH_SHIFT 8 +#define BLE_ADV_HEADER_PDU_TYPE_SHIFT 0 +#define BLE_ADV_HEADER_TXADD_SHIFT 6 +#define BLE_ADV_HEADER_RXADD_SHIFT 7 +#define BLE_ADV_HEADER_LENGTH_SHIFT 8 -#define BLE_ADV_HEADER(type, tx, rx, length) \ - ((uint16_t) \ - ((((length) & 0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \ - (((rx) & 0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \ - (((tx) & 0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \ - (((type) & 0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT))) +#define BLE_ADV_HEADER(type, tx, rx, length) \ + ((uint16_t)((((length)&0x3f) << BLE_ADV_HEADER_LENGTH_SHIFT) | \ + (((rx)&0x1) << BLE_ADV_HEADER_RXADD_SHIFT) | \ + (((tx)&0x1) << BLE_ADV_HEADER_TXADD_SHIFT) | \ + (((type)&0xf) << BLE_ADV_HEADER_PDU_TYPE_SHIFT))) -#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0 -#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_IND 0 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND 1 #define BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND 2 -#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3 -#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4 -#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5 -#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6 +#define BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ 3 +#define BLE_ADV_HEADER_PDU_TYPE_SCAN_RSP 4 +#define BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ 5 +#define BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND 6 -#define BLE_ADV_HEADER_PUBLIC_ADDR 0 -#define BLE_ADV_HEADER_RANDOM_ADDR 1 +#define BLE_ADV_HEADER_PUBLIC_ADDR 0 +#define BLE_ADV_HEADER_RANDOM_ADDR 1 /* BLE 4.1 Vol 3 Part C 10.8 */ -#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00 -#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40 -#define BLE_RANDOM_ADDR_MSBS_RFU 0x80 -#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0 +#define BLE_RANDOM_ADDR_MSBS_PRIVATE 0x00 +#define BLE_RANDOM_ADDR_MSBS_RESOLVABLE_PRIVATE 0x40 +#define BLE_RANDOM_ADDR_MSBS_RFU 0x80 +#define BLE_RANDOM_ADDR_MSBS_STATIC 0xC0 #define BLE_ADV_ACCESS_ADDRESS 0x8E89BED6 #define BLE_ADV_CRCINIT 0x555555 -#define BLE_MAX_ADV_PAYLOAD_OCTETS 37 +#define BLE_MAX_ADV_PAYLOAD_OCTETS 37 /* LL SCA Values. They are shifted left 5 bits for Hop values */ -#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5) -#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5) -#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5) -#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5) -#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5) -#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5) -#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5) -#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5) +#define BLE_LL_SCA_251_PPM_TO_500_PPM (0 << 5) +#define BLE_LL_SCA_151_PPM_TO_250_PPM BIT(5) +#define BLE_LL_SCA_101_PPM_TO_150_PPM (2 << 5) +#define BLE_LL_SCA_076_PPM_TO_100_PPM (3 << 5) +#define BLE_LL_SCA_051_PPM_TO_075_PPM (4 << 5) +#define BLE_LL_SCA_031_PPM_TO_050_PPM (5 << 5) +#define BLE_LL_SCA_021_PPM_TO_030_PPM (6 << 5) +#define BLE_LL_SCA_000_PPM_TO_020_PPM (7 << 5) /* BLE 4.1 Vol 6 section 2.4 pg 45 */ @@ -169,26 +166,25 @@ struct ble_data_header { uint8_t length; }; -#define BLE_DATA_HEADER_LLID_SHIFT 0 -#define BLE_DATA_HEADER_NESN_SHIFT 2 -#define BLE_DATA_HEADER_SN_SHIFT 3 -#define BLE_DATA_HEADER_MD_SHIFT 4 -#define BLE_DATA_HEADER_LENGTH_SHIFT 8 +#define BLE_DATA_HEADER_LLID_SHIFT 0 +#define BLE_DATA_HEADER_NESN_SHIFT 2 +#define BLE_DATA_HEADER_SN_SHIFT 3 +#define BLE_DATA_HEADER_MD_SHIFT 4 +#define BLE_DATA_HEADER_LENGTH_SHIFT 8 #define BLE_DATA_HEADER_LLID_DATANOSTART 1 -#define BLE_DATA_HEADER_LLID_DATASTART 2 -#define BLE_DATA_HEADER_LLID_CONTROL 3 +#define BLE_DATA_HEADER_LLID_DATASTART 2 +#define BLE_DATA_HEADER_LLID_CONTROL 3 -#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \ - ((uint16_t) \ - ((((length) & 0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \ - (((MD) & 0x1) << BLE_DATA_HEADER_MD_SHIFT) | \ - (((SN) & 0x1) << BLE_DATA_HEADER_SN_SHIFT) | \ - (((NESN) & 0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \ - (((llid) & 0x3) << BLE_DATA_HEADER_LLID_SHIFT))) +#define BLE_DATA_HEADER(llid, nesn, sn, md, length) \ + ((uint16_t)((((length)&0x1f) << BLE_DATA_HEADER_LENGTH_SHIFT) | \ + (((MD)&0x1) << BLE_DATA_HEADER_MD_SHIFT) | \ + (((SN)&0x1) << BLE_DATA_HEADER_SN_SHIFT) | \ + (((NESN)&0x1) << BLE_DATA_HEADER_NESN_SHIFT) | \ + (((llid)&0x3) << BLE_DATA_HEADER_LLID_SHIFT))) -#define BLE_MAX_DATA_PAYLOAD_OCTETS 31 -#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS +#define BLE_MAX_DATA_PAYLOAD_OCTETS 31 +#define BLE_MAX_PAYLOAD_OCTETS BLE_MAX_ADV_PAYLOAD_OCTETS union ble_header { struct ble_adv_header adv; @@ -210,34 +206,34 @@ struct ble_packet { }; /* LL Control PDU Opcodes BLE 4.1 Vol 6 2.4.2 */ -#define BLE_LL_CONNECTION_UPDATE_REQ 0x00 -#define BLE_LL_CHANNEL_MAP_REQ 0x01 -#define BLE_LL_TERMINATE_IND 0x02 -#define BLE_LL_ENC_REQ 0x03 -#define BLE_LL_ENC_RSP 0x04 -#define BLE_LL_START_ENC_REQ 0x05 -#define BLE_LL_START_ENC_RSP 0x06 -#define BLE_LL_UNKNOWN_RSP 0x07 -#define BLE_LL_FEATURE_REQ 0x08 -#define BLE_LL_FEATURE_RSP 0x09 -#define BLE_LL_PAUSE_ENC_REQ 0x0A -#define BLE_LL_PAUSE_ENC_RSP 0x0B -#define BLE_LL_VERSION_IND 0x0C -#define BLE_LL_REJECT_IND 0x0D -#define BLE_LL_SLAVE_FEATURE_REQ 0x0E -#define BLE_LL_CONNECTION_PARAM_REQ 0x0F -#define BLE_LL_CONNECTION_PARAM_RSP 0x10 -#define BLE_LL_REJECT_IND_EXT 0x11 -#define BLE_LL_PING_REQ 0x12 -#define BLE_LL_PING_RSP 0x13 -#define BLE_LL_RFU 0x14 +#define BLE_LL_CONNECTION_UPDATE_REQ 0x00 +#define BLE_LL_CHANNEL_MAP_REQ 0x01 +#define BLE_LL_TERMINATE_IND 0x02 +#define BLE_LL_ENC_REQ 0x03 +#define BLE_LL_ENC_RSP 0x04 +#define BLE_LL_START_ENC_REQ 0x05 +#define BLE_LL_START_ENC_RSP 0x06 +#define BLE_LL_UNKNOWN_RSP 0x07 +#define BLE_LL_FEATURE_REQ 0x08 +#define BLE_LL_FEATURE_RSP 0x09 +#define BLE_LL_PAUSE_ENC_REQ 0x0A +#define BLE_LL_PAUSE_ENC_RSP 0x0B +#define BLE_LL_VERSION_IND 0x0C +#define BLE_LL_REJECT_IND 0x0D +#define BLE_LL_SLAVE_FEATURE_REQ 0x0E +#define BLE_LL_CONNECTION_PARAM_REQ 0x0F +#define BLE_LL_CONNECTION_PARAM_RSP 0x10 +#define BLE_LL_REJECT_IND_EXT 0x11 +#define BLE_LL_PING_REQ 0x12 +#define BLE_LL_PING_RSP 0x13 +#define BLE_LL_RFU 0x14 /* BLE 4.1 Vol 6 4.6 Table 4.3 */ -#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00 -#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01 -#define BLE_LL_FEATURE_EXT_REJ_IND 0x02 -#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03 -#define BLE_LL_FEATURE_LE_PING 0x04 +#define BLE_LL_FEATURE_LE_ENCRYPTION 0x00 +#define BLE_LL_FEATURE_CONN_PARAMS_REQ 0x01 +#define BLE_LL_FEATURE_EXT_REJ_IND 0x02 +#define BLE_LL_FEATURE_SLAVE_FEAT_EXCHG 0x03 +#define BLE_LL_FEATURE_LE_PING 0x04 struct ble_ll_connection_update_req { uint8_t win_size; @@ -285,8 +281,8 @@ struct ble_ll_feature_rsp { /* ble_ll_pause_enc_rsp has no CtrData field */ -#define BLE_LL_VERS_NR_4_0 6 -#define BLE_LL_VERS_NR_4_1 7 +#define BLE_LL_VERS_NR_4_0 6 +#define BLE_LL_VERS_NR_4_1 7 struct ble_ll_version_ind { uint8_t vers_nr; /* Version Number */ @@ -348,7 +344,7 @@ int chan2freq(int channel); /* BLE 4.1 Vol 6 2.3.3.1 */ void fill_remapping_table(struct remapping_table *rt, uint8_t map[5], - int hop_increment); + int hop_increment); void ble_tx(struct ble_pdu *pdu); @@ -376,7 +372,7 @@ uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data); uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr); const uint8_t *unpack_adv(const uint8_t *src, int *length, int *type, - const uint8_t **data); + const uint8_t **data); void dump_ble_addr(uint8_t *mem, char *name); -- cgit v1.2.1 From e868219a86b2d66958f3cb009a38933f755c5627 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:54 -0600 Subject: driver/usb_mux/tusb1064.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24ed2f973382cf246f1ffe112da7f830220eea87 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730171 Reviewed-by: Jeremy Bettis --- driver/usb_mux/tusb1064.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/usb_mux/tusb1064.c b/driver/usb_mux/tusb1064.c index 0d48725d40..6b3c86397b 100644 --- a/driver/usb_mux/tusb1064.c +++ b/driver/usb_mux/tusb1064.c @@ -7,27 +7,27 @@ #include "tusb1064.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #if defined(CONFIG_USB_MUX_TUSB1044) + defined(CONFIG_USB_MUX_TUSB1064) + \ - defined(CONFIG_USB_MUX_TUSB546) != 1 + defined(CONFIG_USB_MUX_TUSB546) != \ + 1 #error "Must choose exactly one of CONFIG_USB_MUX_TUSB{546,1044,1064}" #endif static int tusb1064_read(const struct usb_mux *me, uint8_t reg, uint8_t *val) { int buffer = 0xee; - int res = i2c_read8(me->i2c_port, me->i2c_addr_flags, - (int)reg, &buffer); + int res = + i2c_read8(me->i2c_port, me->i2c_addr_flags, (int)reg, &buffer); *val = buffer; return res; } static int tusb1064_write(const struct usb_mux *me, uint8_t reg, uint8_t val) { - return i2c_write8(me->i2c_port, me->i2c_addr_flags, - (int)reg, (int)val); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, (int)reg, (int)val); } #if defined(CONFIG_USB_MUX_TUSB1044) @@ -102,7 +102,7 @@ static int tusb1064_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* Mask bits that may be set in this function */ mask = REG_GENERAL_CTLSEL_USB3 | REG_GENERAL_CTLSEL_ANYDP | - REG_GENERAL_FLIPSEL; + REG_GENERAL_FLIPSEL; #if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546) mask |= REG_GENERAL_HPDIN_OVERRIDE; #endif -- cgit v1.2.1 From 8b938ab978313e274feb2818ef2fe217dc27ec0f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:26 -0600 Subject: power/amd_x86.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4940ee24235ea413ad5d8a369187897e1ebb0557 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727055 Reviewed-by: Jeremy Bettis --- power/amd_x86.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/power/amd_x86.c b/power/amd_x86.c index 2a35849039..af426a567b 100644 --- a/power/amd_x86.c +++ b/power/amd_x86.c @@ -231,8 +231,7 @@ static void lpc_s0ix_resume_restore_masks(void) backup_sci_mask = backup_smi_mask = 0; } -__override void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { /* * Wake up the AP so they don't just chill in a non-suspended state and @@ -274,15 +273,15 @@ void power_reset_host_sleep_state(void) #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__overridable void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__overridable void +power_board_handle_host_sleep_event(enum host_sleep_event state) { /* Default weak implementation -- no action required. */ } -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { power_board_handle_host_sleep_event(state); @@ -438,9 +437,9 @@ enum power_state power_handle_state(enum power_state state) * Ignore the SLP_S0 assertions in idle scenario by checking * the host sleep state. */ - else if (power_get_host_sleep_state() - == HOST_SLEEP_EVENT_S0IX_SUSPEND && - gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) { + else if (power_get_host_sleep_state() == + HOST_SLEEP_EVENT_S0IX_SUSPEND && + gpio_get_level(GPIO_PCH_SLP_S0_L) == 0) { return POWER_S0S0ix; } #endif -- cgit v1.2.1 From db7a6a612aa9b871fb10e5a78ff693b8af623f9b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:13 -0600 Subject: chip/mt_scp/mt8192/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3d71a24ef89902e01432f425f962dd2f1a67b130 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729351 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8192/clock.c | 56 +++++++++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 21 deletions(-) diff --git a/chip/mt_scp/mt8192/clock.c b/chip/mt_scp/mt8192/clock.c index 43f570fc62..b1901bfe1a 100644 --- a/chip/mt_scp/mt8192/clock.c +++ b/chip/mt_scp/mt8192/clock.c @@ -36,19 +36,35 @@ static struct opp_ulposc_cfg { uint32_t target_mhz; } opp[] = { { - .osc = 1, .target_mhz = 196, .div = 20, .fband = 10, .mod = 3, + .osc = 1, + .target_mhz = 196, + .div = 20, + .fband = 10, + .mod = 3, .cali = 64, }, { - .osc = 0, .target_mhz = 260, .div = 14, .fband = 2, .mod = 0, + .osc = 0, + .target_mhz = 260, + .div = 14, + .fband = 2, + .mod = 0, .cali = 64, }, { - .osc = 1, .target_mhz = 280, .div = 20, .fband = 2, .mod = 0, + .osc = 1, + .target_mhz = 280, + .div = 20, + .fband = 2, + .mod = 0, .cali = 64, }, { - .osc = 1, .target_mhz = 360, .div = 20, .fband = 10, .mod = 0, + .osc = 1, + .target_mhz = 360, + .div = 20, + .fband = 10, + .mod = 0, .cali = 64, }, }; @@ -112,13 +128,12 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc) int cnt; /* before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; + AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK; /* select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); + AP_CLK_DBG_CFG = + (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | + (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2); /* set meter divisor to 1, bit[31:24] = b00000000 */ AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | @@ -152,7 +167,7 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc) return result; } -#define CAL_MIS_RATE 40 +#define CAL_MIS_RATE 40 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) { uint32_t curr, target; @@ -278,8 +293,8 @@ static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp) opp->cali = clock_ulposc_process_cali(opp); #ifdef DEBUG - CPRINTF("osc:%u, target=%uMHz, cal:%u\n", - opp->osc, opp->target_mhz, opp->cali); + CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz, + opp->cali); #endif } @@ -327,12 +342,12 @@ void clock_init(void) SCP_SYS_CTRL |= AUTO_DDREN; /* set settle time */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1); - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1); - SCP_SLEEP_CTRL = - (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1); + SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | + CLK_SYS_VAL_VAL(1); + SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | + CLK_HIGH_VAL_VAL(1); + SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | + VREQ_COUNT_VAL(1); /* turn off ULPOSC2 */ SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; @@ -349,7 +364,7 @@ void clock_init(void) /* enable default clock gate */ SCP_SET_CLK_CG |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK; + CG_I2C_MCLK | CG_MAD_MCLK | CG_AP2P_MCLK; } #ifdef DEBUG @@ -358,8 +373,7 @@ int command_ulposc(int argc, char *argv[]) int i; for (i = 0; i <= 1; ++i) - ccprintf("ULPOSC%u frequency: %u kHz\n", - i + 1, + ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1, clock_ulposc_measure_freq(i) * 26 * 1000 / 1024); return EC_SUCCESS; -- cgit v1.2.1 From 4796dbf4c9266766a667b920512ce9b4c30a3f70 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:58 -0600 Subject: board/grunt/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d6114bf76bfcab62ca8be863127cb840740f79a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728432 Reviewed-by: Jeremy Bettis --- board/grunt/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/grunt/led.c b/board/grunt/led.c index 824ec55f6c..41de9b6c66 100644 --- a/board/grunt/led.c +++ b/board/grunt/led.c @@ -19,13 +19,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, Blue */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 0 }, - [EC_LED_COLOR_AMBER] = { 100, 0 }, + /* Amber, Blue */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 100 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 0 }, [EC_LED_COLOR_AMBER] = { 100, 0 }, }; /* One logical LED with amber and blue channels. */ -- cgit v1.2.1 From f5d4722bf05d4a84217e1136caf68e4e74a12f85 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:15 -0600 Subject: board/pirika/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cf7d1e2c44b5bb23d58880dadb9512a32f2db6f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728828 Reviewed-by: Jeremy Bettis --- board/pirika/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/pirika/cbi_ssfc.c b/board/pirika/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/pirika/cbi_ssfc.c +++ b/board/pirika/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 96ae7389e95d941a9f901dbd37e9dea5b9677de6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:07 -0600 Subject: driver/battery/smart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d1c235dbf31e1382abd07235e66a198a1556cc4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729931 Reviewed-by: Jeremy Bettis --- driver/battery/smart.c | 84 ++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 47 deletions(-) diff --git a/driver/battery/smart.c b/driver/battery/smart.c index c87a1a6cdc..5d56f2602a 100644 --- a/driver/battery/smart.c +++ b/driver/battery/smart.c @@ -15,9 +15,9 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHARGER, outstr); -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -#define BATTERY_NO_RESPONSE_TIMEOUT (1000*MSEC) +#define BATTERY_NO_RESPONSE_TIMEOUT (1000 * MSEC) static int fake_state_of_charge = -1; static int fake_temperature = -1; @@ -92,8 +92,7 @@ int sb_read_string(int offset, uint8_t *data, int len) if (battery_supports_pec()) addr_flags |= I2C_FLAG_PEC; - return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data, - len); + return i2c_read_string(I2C_PORT_BATTERY, addr_flags, offset, data, len); } int sb_read_sized_block(int offset, uint8_t *data, int len) @@ -315,12 +314,12 @@ test_mockable int battery_manufacture_date(int *year, int *month, int *day) /* battery date format: * ymd = day + month * 32 + (year - 1980) * 512 */ - *year = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >> - MANUFACTURE_DATE_YEAR_SHIFT) + MANUFACTURE_DATE_YEAR_OFFSET; + *year = ((ymd & MANUFACTURE_DATE_YEAR_MASK) >> + MANUFACTURE_DATE_YEAR_SHIFT) + + MANUFACTURE_DATE_YEAR_OFFSET; *month = (ymd & MANUFACTURE_DATE_MONTH_MASK) >> MANUFACTURE_DATE_MONTH_SHIFT; - *day = (ymd & MANUFACTURE_DATE_DAY_MASK) >> - MANUFACTURE_DATE_DAY_SHIFT; + *day = (ymd & MANUFACTURE_DATE_DAY_MASK) >> MANUFACTURE_DATE_DAY_SHIFT; return EC_SUCCESS; } @@ -408,16 +407,16 @@ void battery_get_params(struct batt_params *batt) memcpy(&batt_new, batt, sizeof(*batt)); batt_new.flags = 0; - if (sb_read(SB_TEMPERATURE, &batt_new.temperature) - && fake_temperature < 0) + if (sb_read(SB_TEMPERATURE, &batt_new.temperature) && + fake_temperature < 0) batt_new.flags |= BATT_FLAG_BAD_TEMPERATURE; /* If temperature is faked, override with faked data */ if (fake_temperature >= 0) batt_new.temperature = fake_temperature; - if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge) - && fake_state_of_charge < 0) + if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_new.state_of_charge) && + fake_state_of_charge < 0) batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE; if (sb_read(SB_VOLTAGE, &batt_new.voltage)) @@ -455,7 +454,7 @@ void battery_get_params(struct batt_params *batt) batt_new.flags |= BATT_FLAG_IMBALANCED_CELL; #endif -#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ +#if defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ defined(CONFIG_BATTERY_PRESENT_GPIO) /* Hardware can tell us for certain */ batt_new.is_present = battery_is_present(); @@ -471,23 +470,20 @@ void battery_get_params(struct batt_params *batt) * Charging allowed if both desired voltage and current are nonzero * and battery isn't full (and we read them all correctly). */ - if (!(batt_new.flags & (BATT_FLAG_BAD_DESIRED_VOLTAGE | - BATT_FLAG_BAD_DESIRED_CURRENT | - BATT_FLAG_BAD_STATE_OF_CHARGE)) && + if (!(batt_new.flags & + (BATT_FLAG_BAD_DESIRED_VOLTAGE | BATT_FLAG_BAD_DESIRED_CURRENT | + BATT_FLAG_BAD_STATE_OF_CHARGE)) && #ifdef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD - /* - * TODO (crosbug.com/p/29467): remove this workaround - * for dead battery that requests no voltage/current - */ - ((batt_new.desired_voltage && - batt_new.desired_current && - batt_new.state_of_charge < BATTERY_LEVEL_FULL) || - (batt_new.desired_voltage == 0 && - batt_new.desired_current == 0 && - batt_new.state_of_charge == 0))) + /* + * TODO (crosbug.com/p/29467): remove this workaround + * for dead battery that requests no voltage/current + */ + ((batt_new.desired_voltage && batt_new.desired_current && + batt_new.state_of_charge < BATTERY_LEVEL_FULL) || + (batt_new.desired_voltage == 0 && batt_new.desired_current == 0 && + batt_new.state_of_charge == 0))) #else - batt_new.desired_voltage && - batt_new.desired_current && + batt_new.desired_voltage && batt_new.desired_current && batt_new.state_of_charge < BATTERY_LEVEL_FULL) #endif batt_new.flags |= BATT_FLAG_WANT_CHARGE; @@ -515,7 +511,7 @@ int battery_wait_for_stable(void) uint64_t wait_timeout = get_time().val + BATTERY_NO_RESPONSE_TIMEOUT; CPRINTS("Wait for battery stabilized during %d", - BATTERY_NO_RESPONSE_TIMEOUT); + BATTERY_NO_RESPONSE_TIMEOUT); while (get_time().val < wait_timeout) { /* Starting pinging battery */ if (battery_status(&status) == EC_SUCCESS) { @@ -571,9 +567,10 @@ static int command_batttempfake(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(batttempfake, command_batttempfake, - "temperature (-1 = use real temperature)", - "Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)"); +DECLARE_CONSOLE_COMMAND( + batttempfake, command_batttempfake, + "temperature (-1 = use real temperature)", + "Set fake battery temperature in deciKelvin (2731 = 273.1 K = 0 deg C)"); #endif #ifdef CONFIG_CMD_BATT_MFG_ACCESS @@ -643,8 +640,7 @@ host_command_sb_read_word(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD, - host_command_sb_read_word, +DECLARE_HOST_COMMAND(EC_CMD_SB_READ_WORD, host_command_sb_read_word, EC_VER_MASK(0)); static enum ec_status @@ -661,8 +657,7 @@ host_command_sb_write_word(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD, - host_command_sb_write_word, +DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_WORD, host_command_sb_write_word, EC_VER_MASK(0)); static enum ec_status @@ -672,10 +667,8 @@ host_command_sb_read_block(struct host_cmd_handler_args *args) const struct ec_params_sb_rd *p = args->params; struct ec_response_sb_rd_block *r = args->response; - if ((p->reg != SB_MANUFACTURER_NAME) && - (p->reg != SB_DEVICE_NAME) && - (p->reg != SB_DEVICE_CHEMISTRY) && - (p->reg != SB_MANUFACTURER_DATA)) + if ((p->reg != SB_MANUFACTURER_NAME) && (p->reg != SB_DEVICE_NAME) && + (p->reg != SB_DEVICE_CHEMISTRY) && (p->reg != SB_MANUFACTURER_DATA)) return EC_RES_INVALID_PARAM; rv = sb_read_string(p->reg, r->data, 32); if (rv) @@ -685,8 +678,7 @@ host_command_sb_read_block(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK, - host_command_sb_read_block, +DECLARE_HOST_COMMAND(EC_CMD_SB_READ_BLOCK, host_command_sb_read_block, EC_VER_MASK(0)); static enum ec_status @@ -695,8 +687,7 @@ host_command_sb_write_block(struct host_cmd_handler_args *args) /* Not implemented */ return EC_RES_INVALID_COMMAND; } -DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK, - host_command_sb_write_block, +DECLARE_HOST_COMMAND(EC_CMD_SB_WRITE_BLOCK, host_command_sb_write_block, EC_VER_MASK(0)); #endif @@ -707,8 +698,8 @@ test_mockable int sb_i2c_test_read(int cmd, int *param) int rv; if (cmd == SB_DEVICE_CHEMISTRY) { - rv = battery_device_chemistry(chemistry, - sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY)); + rv = battery_device_chemistry( + chemistry, sizeof(CONFIG_BATTERY_DEVICE_CHEMISTRY)); if (rv) return rv; if (strcasecmp(chemistry, CONFIG_BATTERY_DEVICE_CHEMISTRY)) @@ -718,7 +709,6 @@ test_mockable int sb_i2c_test_read(int cmd, int *param) return EC_SUCCESS; } - return sb_read(cmd, param); } -- cgit v1.2.1 From c645cef6d8282f00973f2c475a0e23ad1fbbf0eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:35 -0600 Subject: include/backlight.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1727a5ed088d38acd0afc59853b28f305a65d85 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730207 Reviewed-by: Jeremy Bettis --- include/backlight.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/backlight.h b/include/backlight.h index 1bfafbdd2c..3492da1984 100644 --- a/include/backlight.h +++ b/include/backlight.h @@ -19,7 +19,9 @@ #ifdef CONFIG_BACKLIGHT_REQ_GPIO void backlight_interrupt(enum gpio_signal signal); #else -static inline void backlight_interrupt(enum gpio_signal signal) { } +static inline void backlight_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_BACKLIGHT_REQ_GPIO */ /** @@ -27,4 +29,4 @@ static inline void backlight_interrupt(enum gpio_signal signal) { } */ void enable_backlight(int enabled); -#endif /* __CROS_EC_BACKLIGHT_H */ +#endif /* __CROS_EC_BACKLIGHT_H */ -- cgit v1.2.1 From ec09cba4a3e5fc9a3bc4f35c63abb32a1585400e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:30 -0600 Subject: include/audio_codec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a772d5b094b84eb420748a7aa5dc04dcf41f027 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730206 Reviewed-by: Jeremy Bettis --- include/audio_codec.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/audio_codec.h b/include/audio_codec.h index b80d1c0f57..44b9050bfa 100644 --- a/include/audio_codec.h +++ b/include/audio_codec.h @@ -41,8 +41,8 @@ int audio_codec_capable(uint8_t cap); * EC_ERROR_INVAL if invalid cap. * EC_ERROR_BUSY if the shm_id has been registered. */ -int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, - uintptr_t *addr, uint32_t len, uint8_t type); +int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr, + uint32_t len, uint8_t type); /* * Translates the physical address from AP to EC's memory space. Required if @@ -63,7 +63,6 @@ int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr); */ int16_t audio_codec_s16_scale_and_clip(int16_t orig, uint8_t scalar); - /* * DMIC abstract layer */ @@ -120,7 +119,6 @@ int audio_codec_dmic_set_gain_idx(uint8_t channel, uint8_t gain); */ int audio_codec_dmic_get_gain_idx(uint8_t channel, uint8_t *gain); - /* * I2S RX abstract layer */ @@ -181,7 +179,6 @@ int audio_codec_i2s_rx_set_daifmt(uint8_t daifmt); */ int audio_codec_i2s_rx_set_bclk(uint32_t bclk); - /* * WoV abstract layer */ -- cgit v1.2.1 From 76f525aad7c47d8db5180d5bb7608038485f031e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:48 -0600 Subject: common/port80.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f7228e81f3e97f61d5ed59d7abdee482e48c3e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729700 Reviewed-by: Jeremy Bettis --- common/port80.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/common/port80.c b/common/port80.c index 231181cad8..c7c9d714ff 100644 --- a/common/port80.c +++ b/common/port80.c @@ -15,7 +15,7 @@ #include "timer.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_PORT80, format, ##args) #ifdef CONFIG_PORT80_4_BYTE typedef uint32_t port80_code_t; @@ -23,7 +23,7 @@ typedef uint32_t port80_code_t; typedef uint16_t port80_code_t; #endif static port80_code_t history[CONFIG_PORT80_HISTORY_LEN]; -static int writes; /* Number of port 80 writes so far */ +static int writes; /* Number of port 80 writes so far */ static uint16_t last_boot; /* Last code from previous boot */ static int scroll; @@ -54,14 +54,15 @@ void port_80_write(int data) * developers to help debug BIOS progress by tracing port80 messages. */ if (print_in_int) - CPRINTF("%c[%pT Port 80: 0x%02x]", - scroll ? '\n' : '\r', PRINTF_TIMESTAMP_NOW, data); + CPRINTF("%c[%pT Port 80: 0x%02x]", scroll ? '\n' : '\r', + PRINTF_TIMESTAMP_NOW, data); hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND); /* Save current port80 code if system is resetting */ if (data == PORT_80_EVENT_RESET && writes) { - port80_code_t prev = history[(writes-1) % ARRAY_SIZE(history)]; + port80_code_t prev = + history[(writes - 1) % ARRAY_SIZE(history)]; /* * last_boot only reports 8-bit codes. @@ -154,8 +155,7 @@ static int command_port80(int argc, char **argv) port80_dump_buffer(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(port80, command_port80, - "[scroll | intprint | flush]", +DECLARE_CONSOLE_COMMAND(port80, command_port80, "[scroll | intprint | flush]", "Print port80 writes or toggle port80 scrolling"); enum ec_status port80_last_boot(struct host_cmd_handler_args *args) @@ -187,24 +187,23 @@ static enum ec_status port80_command_read(struct host_cmd_handler_args *args) } else if (p->subcmd == EC_PORT80_READ_BUFFER) { /* do not allow bad offset or size */ if (offset >= ARRAY_SIZE(history) || entries == 0 || - entries > args->response_max) + entries > args->response_max) return EC_RES_INVALID_PARAM; for (i = 0; i < entries; i++) { - uint16_t e = history[(i + offset) % - ARRAY_SIZE(history)]; + uint16_t e = + history[(i + offset) % ARRAY_SIZE(history)]; rsp->data.codes[i] = e; } - args->response_size = entries*sizeof(uint16_t); + args->response_size = entries * sizeof(uint16_t); return EC_RES_SUCCESS; } return EC_RES_INVALID_PARAM; } -DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ, - port80_command_read, - EC_VER_MASK(0) | EC_VER_MASK(1)); +DECLARE_HOST_COMMAND(EC_CMD_PORT80_READ, port80_command_read, + EC_VER_MASK(0) | EC_VER_MASK(1)); static void port80_log_resume(void) { -- cgit v1.2.1 From 1bc518c9119ade722a5b301c41d9bab453391bac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:10 -0600 Subject: board/quackingstick/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I759a36060feafd42a267ec0d3cfacecfdc0f0592 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728868 Reviewed-by: Jeremy Bettis --- board/quackingstick/base_detect.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/quackingstick/base_detect.c b/board/quackingstick/base_detect.c index d008226125..c24d016e7b 100644 --- a/board/quackingstick/base_detect.c +++ b/board/quackingstick/base_detect.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Base detection and debouncing */ #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC) @@ -93,8 +93,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -211,7 +211,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From eccb92c82fce4660d5cdc7c3818f8fb95b838ab4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:11 -0600 Subject: board/bloog/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff58eeb108a1430755d9d05130104e25cfbd9c9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728059 Reviewed-by: Jeremy Bettis --- board/bloog/board.c | 111 ++++++++++++++++++++++++---------------------------- 1 file changed, 52 insertions(+), 59 deletions(-) diff --git a/board/bloog/board.c b/board/bloog/board.c index 47802bf584..c44d4966c9 100644 --- a/board/bloog/board.c +++ b/board/bloog/board.c @@ -40,13 +40,13 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -71,32 +71,32 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* Vbus C1 sensing (10x voltage divider). PPVAR_USB_C1_VBUS */ - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -106,23 +106,17 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t lid_a_cover_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_a_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_b_cover_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_b_cover_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data kx022_data; @@ -220,10 +214,10 @@ int board_is_convertible(void) * Bipship: 53, 54, 55, 56 * Unprovisioned: 255 */ - return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 - || sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 - || sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56 - || sku_id == 255; + return sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || + sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52 || + sku_id == 53 || sku_id == 54 || sku_id == 55 || sku_id == 56 || + sku_id == 255; } static void board_update_sensor_config_from_sku(void) @@ -234,8 +228,8 @@ static void board_update_sensor_config_from_sku(void) gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L); /* Override sensor marix for Bipship. */ - if (sku_id == 53 || sku_id == 54 || sku_id == 55 - || sku_id == 56) + if (sku_id == 53 || sku_id == 54 || sku_id == 55 || + sku_id == 56) motion_sensors[LID_ACCEL].rot_standard_ref = &lid_b_cover_ref; } else { @@ -265,10 +259,10 @@ void board_hibernate_late(void) const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_LED_WHITE_C0_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LED_AMBER_C0_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LED_WHITE_C1_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LED_AMBER_C1_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) @@ -297,15 +291,15 @@ __override void lid_angle_peripheral_enable(int enable) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif void board_overcurrent_event(int port, int is_overcurrented) @@ -323,9 +317,8 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) /* * Remove keyboard backlight feature for devices that don't support it. */ - if (sku_id == 33 || sku_id == 36 || sku_id == 51 || - sku_id == 52 || sku_id == 53 || sku_id == 55 || - sku_id == 66 || sku_id == 68) + if (sku_id == 33 || sku_id == 36 || sku_id == 51 || sku_id == 52 || + sku_id == 53 || sku_id == 55 || sku_id == 66 || sku_id == 68) return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); else return flags0; -- cgit v1.2.1 From d781fda0b3f2aa92b30b46e4c8dee98057108a2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:40 -0600 Subject: chip/stm32/usb_gpio.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I210747d9807699eeaddcd4912d658a10039dcf0c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729554 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_gpio.h | 115 ++++++++++++++++++++++++-------------------------- 1 file changed, 54 insertions(+), 61 deletions(-) diff --git a/chip/stm32/usb_gpio.h b/chip/stm32/usb_gpio.h index b27c7f9485..f6fafeeb39 100644 --- a/chip/stm32/usb_gpio.h +++ b/chip/stm32/usb_gpio.h @@ -55,69 +55,62 @@ struct usb_gpio_config { * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_GPIO_CONFIG(NAME, \ - GPIO_LIST, \ - INTERFACE, \ - ENDPOINT) \ - BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ - struct usb_gpio_config const NAME = { \ - .state = &((struct usb_gpio_state){}), \ - .endpoint = ENDPOINT, \ - .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ - .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ - .gpios = GPIO_LIST, \ - .num_gpios = ARRAY_SIZE(GPIO_LIST), \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = 0, \ - .bInterfaceProtocol = 0, \ - .iInterface = 0, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_gpio_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_gpio_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_gpio_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ +#define USB_GPIO_CONFIG(NAME, GPIO_LIST, INTERFACE, ENDPOINT) \ + BUILD_ASSERT(ARRAY_SIZE(GPIO_LIST) <= 32); \ + static usb_uint CONCAT2( \ + NAME, _ep_rx_buffer)[USB_GPIO_RX_PACKET_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2( \ + NAME, _ep_tx_buffer)[USB_GPIO_TX_PACKET_SIZE / 2] __usb_ram; \ + struct usb_gpio_config const NAME = { \ + .state = &((struct usb_gpio_state){}), \ + .endpoint = ENDPOINT, \ + .rx_ram = CONCAT2(NAME, _ep_rx_buffer), \ + .tx_ram = CONCAT2(NAME, _ep_tx_buffer), \ + .gpios = GPIO_LIST, \ + .num_gpios = ARRAY_SIZE(GPIO_LIST), \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = 0, \ + .bInterfaceProtocol = 0, \ + .iInterface = 0, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_GPIO_TX_PACKET_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_GPIO_RX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_gpio_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_gpio_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_gpio_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ CONCAT2(NAME, _ep_event)) - /* * These functions are used by the trampoline functions defined above to * connect USB endpoint events with the generic USB GPIO driver. -- cgit v1.2.1 From 943da00b90864d150506903625add2b318aab37a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:36 -0600 Subject: baseboard/zork/cbi_ec_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f746472bd6c2097687212d29f28a2fbf5bb5561 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727956 Reviewed-by: Jeremy Bettis --- baseboard/zork/cbi_ec_fw_config.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/baseboard/zork/cbi_ec_fw_config.c b/baseboard/zork/cbi_ec_fw_config.c index 50a29d3634..b5f1909f9f 100644 --- a/baseboard/zork/cbi_ec_fw_config.c +++ b/baseboard/zork/cbi_ec_fw_config.c @@ -28,8 +28,7 @@ uint32_t get_cbi_fw_config(void) */ enum ec_cfg_usb_db_type ec_config_get_usb_db(void) { - return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) - >> EC_CFG_USB_DB_L); + return ((get_cbi_fw_config() & EC_CFG_USB_DB_MASK) >> EC_CFG_USB_DB_L); } /* @@ -37,8 +36,7 @@ enum ec_cfg_usb_db_type ec_config_get_usb_db(void) */ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void) { - return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) - >> EC_CFG_USB_MB_L); + return ((get_cbi_fw_config() & EC_CFG_USB_MB_MASK) >> EC_CFG_USB_MB_L); } /* @@ -46,8 +44,8 @@ enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void) */ enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void) { - return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) - >> EC_CFG_LID_ACCEL_SENSOR_L); + return ((get_cbi_fw_config() & EC_CFG_LID_ACCEL_SENSOR_MASK) >> + EC_CFG_LID_ACCEL_SENSOR_L); } /* @@ -55,28 +53,27 @@ enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void) */ enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void) { - return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) - >> EC_CFG_BASE_GYRO_SENSOR_L); + return ((get_cbi_fw_config() & EC_CFG_BASE_GYRO_SENSOR_MASK) >> + EC_CFG_BASE_GYRO_SENSOR_L); } /* * ec_config_has_pwm_keyboard_backlight() will return 1 is present or 0 */ -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void) +enum ec_cfg_pwm_keyboard_backlight_type +ec_config_has_pwm_keyboard_backlight(void) { - return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) - >> EC_CFG_PWM_KEYBOARD_BACKLIGHT_L); + return ((get_cbi_fw_config() & EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK) >> + EC_CFG_PWM_KEYBOARD_BACKLIGHT_L); } /* * ec_config_has_lid_angle_tablet_mode() will return 1 is present or 0 */ -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void) +enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode(void) { - return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) - >> EC_CFG_LID_ANGLE_TABLET_MODE_L); + return ((get_cbi_fw_config() & EC_CFG_LID_ANGLE_TABLET_MODE_MASK) >> + EC_CFG_LID_ANGLE_TABLET_MODE_L); } /* @@ -84,8 +81,8 @@ enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( */ enum ec_cfg_lte_present_type ec_config_lte_present(void) { - return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) - >> EC_CFG_LTE_PRESENT_L); + return ((get_cbi_fw_config() & EC_CFG_LTE_PRESENT_MASK) >> + EC_CFG_LTE_PRESENT_L); } /* @@ -93,6 +90,6 @@ enum ec_cfg_lte_present_type ec_config_lte_present(void) */ enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void) { - return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) - >> EC_CFG_KEYBOARD_LAYOUT_L); + return ((get_cbi_fw_config() & EC_CFG_KEYBOARD_LAYOUT_MASK) >> + EC_CFG_KEYBOARD_LAYOUT_L); } -- cgit v1.2.1 From 6ffcf0d66a190f74a6da7f2f8e513b3445342d64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:32 -0600 Subject: board/tglrvp_ish/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia01f98760f8e55e05a6713b500ff24778eded75e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729019 Reviewed-by: Jeremy Bettis --- board/tglrvp_ish/board.h | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/board/tglrvp_ish/board.h b/board/tglrvp_ish/board.h index 12f4b5992a..49582fb078 100644 --- a/board/tglrvp_ish/board.h +++ b/board/tglrvp_ish/board.h @@ -22,7 +22,7 @@ #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* ISH specific */ -#undef CONFIG_DEBUG_ASSERT +#undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL #define CONFIG_ISH_UART_0 /* EC */ @@ -31,7 +31,7 @@ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define CONFIG_ACCELGYRO_LSM6DSM /* For LSM6DS3 */ +#define CONFIG_ACCELGYRO_LSM6DSM /* For LSM6DS3 */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(BASE_ACCEL) /* Host command over HECI */ @@ -81,8 +81,8 @@ #define CONFIG_ISH_IPAPG -#define CONFIG_ISH_D0I2_MIN_USEC (15*MSEC) -#define CONFIG_ISH_D0I3_MIN_USEC (50*MSEC) +#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC) +#define CONFIG_ISH_D0I3_MIN_USEC (50 * MSEC) #define CONFIG_ISH_NEW_PM @@ -92,10 +92,7 @@ #include "registers.h" /* Motion sensors */ -enum sensor_id { - BASE_ACCEL, - SENSOR_COUNT -}; +enum sensor_id { BASE_ACCEL, SENSOR_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From f87f77932a2fc1bff4e10f895a9eff18340945f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:35 -0600 Subject: board/fennel/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd3abbc284c5dbdf23b965fc965677a3d8115039 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728364 Reviewed-by: Jeremy Bettis --- board/fennel/board.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/fennel/board.h b/board/fennel/board.h index f15e61da11..ffd67e9f77 100644 --- a/board/fennel/board.h +++ b/board/fennel/board.h @@ -52,11 +52,11 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM42607 /* Base accel second source*/ #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) #define CONFIG_ALS @@ -75,20 +75,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_BATTERY 2 +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BATTERY 2 /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 44613d6a79dcef7d31536e4f8cd236bb94c0c101 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Thu, 23 Jun 2022 15:28:46 -0600 Subject: dp_alt_mode: Fix indentation Indent comment correctly. BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: Ie87be889010f9e6f47cfa4c50985b51b49190b5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724158 Reviewed-by: Diana Z Commit-Queue: Diana Z --- common/usbc/dp_alt_mode.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c index 5cf3c03ba8..0b34d42cb1 100644 --- a/common/usbc/dp_alt_mode.c +++ b/common/usbc/dp_alt_mode.c @@ -120,11 +120,12 @@ static void dp_exit_to_usb_mode(int port) set_usb_mux_with_current_data_role(port); CPRINTS("C%d: Exited DP mode", port); - /* - * If the EC exits an alt mode autonomously, don't try to enter it again. If - * the AP commands the EC to exit DP mode, it might command the EC to enter - * again later, so leave the state machine ready for that possibility. - */ + /* + * If the EC exits an alt mode autonomously, don't try to enter it + * again. If the AP commands the EC to exit DP mode, it might command + * the EC to enter again later, so leave the state machine ready for + * that possibility. + */ dp_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? DP_START : DP_INACTIVE; } -- cgit v1.2.1 From c3a6e319bf6ce8516bdf0f950a6347427bb6427b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:48 -0600 Subject: chip/stm32/usart_tx_dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c92f52f7f48778870c8c9745baf8215535ca817 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729424 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_tx_dma.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/chip/stm32/usart_tx_dma.c b/chip/stm32/usart_tx_dma.c index 0c8e2c73d6..895c8c0930 100644 --- a/chip/stm32/usart_tx_dma.c +++ b/chip/stm32/usart_tx_dma.c @@ -36,13 +36,13 @@ static void usart_tx_dma_start(struct usart_config const *config, struct usart_tx_dma const *dma_config) { struct usart_tx_dma_state volatile *state = dma_config->state; - intptr_t base = config->hw->base; + intptr_t base = config->hw->base; struct dma_option options = { .channel = dma_config->channel, - .periph = (void *)&STM32_USART_TDR(base), - .flags = (STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT), + .periph = (void *)&STM32_USART_TDR(base), + .flags = + (STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT), }; /* -- cgit v1.2.1 From fbd408dbc8c632409a3da485f7346847d74bed42 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:33 -0600 Subject: board/twinkie/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0fe606f2b1c1c0d5e60cd0c61eb6d0dd8b2f221 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729049 Reviewed-by: Jeremy Bettis --- board/twinkie/usb_pd_pdo.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/twinkie/usb_pd_pdo.c b/board/twinkie/usb_pd_pdo.c index 120c13125b..ebb40aec84 100644 --- a/board/twinkie/usb_pd_pdo.c +++ b/board/twinkie/usb_pd_pdo.c @@ -10,15 +10,15 @@ #define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP) const uint32_t pd_src_pdo[] = { - PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), - PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), - PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS), }; const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), - PDO_BATT(4750, 21000, 15000), - PDO_VAR(4750, 21000, 3000), + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); -- cgit v1.2.1 From 182d71920668e0ea1626561593cfc28a57f958cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:01 -0600 Subject: zephyr/projects/corsola/src/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9aa1d22e63619ecca1ede4bd8e7b14ce1c851884 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730768 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/usbc_config.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/zephyr/projects/corsola/src/usbc_config.c b/zephyr/projects/corsola/src/usbc_config.c index 1f927dbc21..fdd731b2f3 100644 --- a/zephyr/projects/corsola/src/usbc_config.c +++ b/zephyr/projects/corsola/src/usbc_config.c @@ -36,8 +36,8 @@ #include "variant_db_detection.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* a flag for indicating the tasks are inited. */ static bool tasks_inited; @@ -67,9 +67,10 @@ __override uint8_t board_get_usb_pd_port_count(void) /* USB-A */ void usb_a0_interrupt(enum gpio_signal signal) { - enum usb_charge_mode mode = gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done)) ? - USB_CHARGE_MODE_ENABLED : USB_CHARGE_MODE_DISABLED; + enum usb_charge_mode mode = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ap_xhci_init_done)) ? + USB_CHARGE_MODE_ENABLED : + USB_CHARGE_MODE_DISABLED; const int xhci_stat = gpio_get_level(signal); @@ -96,16 +97,15 @@ void usb_a0_interrupt(enum gpio_signal signal) __override enum pd_dual_role_states pd_get_drp_state_in_s0(void) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ap_xhci_init_done))) { return PD_DRP_TOGGLE_ON; } else { return PD_DRP_FORCE_SINK; } } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); @@ -127,8 +127,8 @@ int debounced_hpd; static void ps185_hdmi_hpd_deferred(void) { - const int new_hpd = gpio_pin_get_dt( - GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); + const int new_hpd = + gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); /* HPD status not changed, probably a glitch, just return. */ if (debounced_hpd == new_hpd) { @@ -155,8 +155,7 @@ static void ps185_hdmi_hpd_deferred(void) 0, /* power low? ... no */ (!!DP_FLAGS_DP_ON)); /* update C1 virtual mux */ - usb_mux_set(USBC_PORT_C1, - USB_PD_MUX_DP_ENABLED, + usb_mux_set(USBC_PORT_C1, USB_PD_MUX_DP_ENABLED, USB_SWITCH_DISCONNECT, 0 /* polarity, don't care */); @@ -171,8 +170,8 @@ DECLARE_DEFERRED(ps185_hdmi_hpd_deferred); static void ps185_hdmi_hpd_disconnect_deferred(void) { - const int new_hpd = gpio_pin_get_dt( - GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); + const int new_hpd = + gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd)); if (debounced_hpd == new_hpd && !new_hpd) { dp_status[USBC_PORT_C1] = @@ -188,7 +187,6 @@ static void ps185_hdmi_hpd_disconnect_deferred(void) USB_SWITCH_DISCONNECT, 0 /* polarity, don't care */); } - } DECLARE_DEFERRED(ps185_hdmi_hpd_disconnect_deferred); -- cgit v1.2.1 From 4a90d17024eb354b73ea0c4ec779356b3fb81f26 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:34 -0600 Subject: board/volet/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a8635f3e302e383551698bd4b77fdba7f40cb89 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729073 Reviewed-by: Jeremy Bettis --- board/volet/board.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/board/volet/board.c b/board/volet/board.c index 94bfa447b4..e934d37675 100644 --- a/board/volet/board.c +++ b/board/volet/board.c @@ -44,7 +44,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static const struct ec_response_keybd_config volet_kb = { .num_top_row_keys = 10, @@ -80,8 +80,8 @@ static const struct ec_response_keybd_config volet_kb_num = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (!ec_cfg_has_numeric_pad()) return &volet_kb; @@ -112,16 +112,15 @@ __override struct keyboard_scan_config keyscan_config = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); __override uint32_t board_override_feature_flags0(uint32_t flags0) { @@ -147,7 +146,7 @@ union volteer_cbi_fw_config fw_config_defaults = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -184,8 +183,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -299,8 +298,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -311,16 +309,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -332,7 +330,7 @@ void board_reset_pd_mcu(void) */ ps8815_reset(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } /******************************************************************************/ -- cgit v1.2.1 From 86d1d502591f2ad0aab095274535a37dfa86658f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:04 -0600 Subject: board/lalala/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c49e0c9989fdb7dea358aa8b6a3980b3b5ae40d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728606 Reviewed-by: Jeremy Bettis --- board/lalala/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lalala/usb_pd_policy.c b/board/lalala/usb_pd_policy.c index fd9018a3f0..98b770be8f 100644 --- a/board/lalala/usb_pd_policy.c +++ b/board/lalala/usb_pd_policy.c @@ -10,8 +10,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From becf6e645624dab44dca3ff10210e97b33d131ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:01 -0600 Subject: include/i2c_hid_touchpad.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id3c040828f58dbbc74da22d94896f9e8e36f2bdf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730285 Reviewed-by: Jeremy Bettis --- include/i2c_hid_touchpad.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/i2c_hid_touchpad.h b/include/i2c_hid_touchpad.h index d5d728a488..b72c2cd588 100644 --- a/include/i2c_hid_touchpad.h +++ b/include/i2c_hid_touchpad.h @@ -13,7 +13,7 @@ #include "stdint.h" /* Max fingers to support */ -#define I2C_HID_TOUCHPAD_MAX_FINGERS 5 +#define I2C_HID_TOUCHPAD_MAX_FINGERS 5 /* * Struct holding a touchpad event -- cgit v1.2.1 From 020ca45bae022b9c4e14c4852b94a4069db71a4b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:03 -0600 Subject: include/lightbar_msg_list.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ccf0b973396a6524809df10e98fde2b82803e88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730304 Reviewed-by: Jeremy Bettis --- include/lightbar_msg_list.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/include/lightbar_msg_list.h b/include/lightbar_msg_list.h index 15c7d14bf6..5694e9d6b6 100644 --- a/include/lightbar_msg_list.h +++ b/include/lightbar_msg_list.h @@ -6,17 +6,17 @@ * we can automatically derive the correct constants, functions, and message * types. */ -#define LIGHTBAR_MSG_LIST \ - LBMSG(ERROR), /* 0 */ \ - LBMSG(S5), /* 1 */ \ - LBMSG(S3), /* 2 */ \ - LBMSG(S0), /* 3 */ \ - LBMSG(S5S3), /* 4 */ \ - LBMSG(S3S0), /* 5 */ \ - LBMSG(S0S3), /* 6 */ \ - LBMSG(S3S5), /* 7 */ \ - LBMSG(STOP), /* 8 */ \ - LBMSG(RUN), /* 9 */ \ - LBMSG(KONAMI), /* A */ \ - LBMSG(TAP), /* B */ \ - LBMSG(PROGRAM), /* C */ +#define LIGHTBAR_MSG_LIST \ + LBMSG(ERROR), /* 0 */ \ + LBMSG(S5), /* 1 */ \ + LBMSG(S3), /* 2 */ \ + LBMSG(S0), /* 3 */ \ + LBMSG(S5S3), /* 4 */ \ + LBMSG(S3S0), /* 5 */ \ + LBMSG(S0S3), /* 6 */ \ + LBMSG(S3S5), /* 7 */ \ + LBMSG(STOP), /* 8 */ \ + LBMSG(RUN), /* 9 */ \ + LBMSG(KONAMI), /* A */ \ + LBMSG(TAP), /* B */ \ + LBMSG(PROGRAM), /* C */ -- cgit v1.2.1 From cc22f5cced10f72d658b66f1ee2e232e85a2052c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:59 -0600 Subject: board/bugzzy/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9428cc784705af8ffe5ab5279b79a21f0c9b10b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728128 Reviewed-by: Jeremy Bettis --- board/bugzzy/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/bugzzy/usb_pd_policy.c b/board/bugzzy/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/bugzzy/usb_pd_policy.c +++ b/board/bugzzy/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From c4196f4e6023afec76c653e614d30f0bbd08bf34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:46 -0600 Subject: driver/baro_bmp280.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba9a82d86fc4490d0f6580dd4e5a1fc2a9add56c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729947 Reviewed-by: Jeremy Bettis --- driver/baro_bmp280.h | 203 +++++++++++++++++++++++++-------------------------- 1 file changed, 101 insertions(+), 102 deletions(-) diff --git a/driver/baro_bmp280.h b/driver/baro_bmp280.h index ee95bd886f..e727b3c297 100644 --- a/driver/baro_bmp280.h +++ b/driver/baro_bmp280.h @@ -3,60 +3,60 @@ * found in the LICENSE file. */ /** \mainpage -* -**************************************************************************** -* Copyright (C) 2012 - 2015 Bosch Sensortec GmbH -* -* File : bmp280.h -* -* Date : 2015/03/27 -* -* Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1) -* -* Usage: Sensor Driver for BMP280 sensor -* -**************************************************************************** -* -* \section License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of the copyright holder nor the names of the -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER -* OR CONTRIBUTORS BE LIABLE FOR ANY -* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -* OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, -* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE -* -* The information provided is believed to be accurate and reliable. -* The copyright holder assumes no responsibility -* for the consequences of use -* of such information nor for any infringement of patents or -* other rights of third parties which may result from its use. -* No license is granted by implication or otherwise under any patent or -* patent rights of the copyright holder. -**************************************************************************/ + * + **************************************************************************** + * Copyright (C) 2012 - 2015 Bosch Sensortec GmbH + * + * File : bmp280.h + * + * Date : 2015/03/27 + * + * Revision : 2.0.4(Pressure and Temperature compensation code revision is 1.1) + * + * Usage: Sensor Driver for BMP280 sensor + * + **************************************************************************** + * + * \section License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holder nor the names of the + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + * The information provided is believed to be accurate and reliable. + * The copyright holder assumes no responsibility + * for the consequences of use + * of such information nor for any infringement of patents or + * other rights of third parties which may result from its use. + * No license is granted by implication or otherwise under any patent or + * patent rights of the copyright holder. + **************************************************************************/ /* BMP280 pressure and temperature module for Chrome EC */ #ifndef __CROS_EC_BARO_BMP280_H @@ -74,80 +74,81 @@ * Bit 1 of 7-bit address: 0 - If SDO is connected to GND * Bit 1 of 7-bit address: 1 - If SDO is connected to Vddio */ -#define BMP280_I2C_ADDRESS1_FLAGS 0x76 -#define BMP280_I2C_ADDRESS2_FLAGS 0x77 +#define BMP280_I2C_ADDRESS1_FLAGS 0x76 +#define BMP280_I2C_ADDRESS2_FLAGS 0x77 /* * CHIP ID */ -#define BMP280_CHIP_ID 0x58 +#define BMP280_CHIP_ID 0x58 /************************************************/ /* CALIBRATION PARAMETERS DEFINITION */ /************************************************/ -#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG 0x88 +#define BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG 0x88 /************************************************/ /* REGISTER ADDRESS DEFINITION */ /************************************************/ -#define BMP280_CHIP_ID_REG 0xD0 -#define BMP280_RST_REG 0xE0 /*Softreset Register */ -#define BMP280_STAT_REG 0xF3 /*Status Register */ -#define BMP280_CTRL_MEAS_REG 0xF4 /*Ctrl Measure Register */ -#define BMP280_CONFIG_REG 0xF5 /*Configuration Register */ -#define BMP280_PRESSURE_MSB_REG 0xF7 /*Pressure MSB Register */ -#define BMP280_PRESSURE_LSB_REG 0xF8 /*Pressure LSB Register */ -#define BMP280_PRESSURE_XLSB_REG 0xF9 /*Pressure XLSB Register */ +#define BMP280_CHIP_ID_REG 0xD0 +#define BMP280_RST_REG 0xE0 /*Softreset Register */ +#define BMP280_STAT_REG 0xF3 /*Status Register */ +#define BMP280_CTRL_MEAS_REG 0xF4 /*Ctrl Measure Register */ +#define BMP280_CONFIG_REG 0xF5 /*Configuration Register */ +#define BMP280_PRESSURE_MSB_REG 0xF7 /*Pressure MSB Register */ +#define BMP280_PRESSURE_LSB_REG 0xF8 /*Pressure LSB Register */ +#define BMP280_PRESSURE_XLSB_REG 0xF9 /*Pressure XLSB Register */ /************************************************/ /* POWER MODE DEFINITION */ /************************************************/ /* Sensor Specific constants */ -#define BMP280_SLEEP_MODE 0x00 -#define BMP280_FORCED_MODE 0x01 -#define BMP280_NORMAL_MODE 0x03 -#define BMP280_SOFT_RESET_CODE 0xB6 +#define BMP280_SLEEP_MODE 0x00 +#define BMP280_FORCED_MODE 0x01 +#define BMP280_NORMAL_MODE 0x03 +#define BMP280_SOFT_RESET_CODE 0xB6 /************************************************/ /* STANDBY TIME DEFINITION */ /************************************************/ -#define BMP280_STANDBY_TIME_1_MS 0x00 -#define BMP280_STANDBY_TIME_63_MS 0x01 -#define BMP280_STANDBY_TIME_125_MS 0x02 -#define BMP280_STANDBY_TIME_250_MS 0x03 -#define BMP280_STANDBY_TIME_500_MS 0x04 -#define BMP280_STANDBY_TIME_1000_MS 0x05 -#define BMP280_STANDBY_TIME_2000_MS 0x06 -#define BMP280_STANDBY_TIME_4000_MS 0x07 +#define BMP280_STANDBY_TIME_1_MS 0x00 +#define BMP280_STANDBY_TIME_63_MS 0x01 +#define BMP280_STANDBY_TIME_125_MS 0x02 +#define BMP280_STANDBY_TIME_250_MS 0x03 +#define BMP280_STANDBY_TIME_500_MS 0x04 +#define BMP280_STANDBY_TIME_1000_MS 0x05 +#define BMP280_STANDBY_TIME_2000_MS 0x06 +#define BMP280_STANDBY_TIME_4000_MS 0x07 /************************************************/ /* OVERSAMPLING DEFINITION */ /************************************************/ -#define BMP280_OVERSAMP_SKIPPED 0x00 -#define BMP280_OVERSAMP_1X 0x01 -#define BMP280_OVERSAMP_2X 0x02 -#define BMP280_OVERSAMP_4X 0x03 -#define BMP280_OVERSAMP_8X 0x04 -#define BMP280_OVERSAMP_16X 0x05 +#define BMP280_OVERSAMP_SKIPPED 0x00 +#define BMP280_OVERSAMP_1X 0x01 +#define BMP280_OVERSAMP_2X 0x02 +#define BMP280_OVERSAMP_4X 0x03 +#define BMP280_OVERSAMP_8X 0x04 +#define BMP280_OVERSAMP_16X 0x05 /************************************************/ /* DEFINITIONS FOR ARRAY SIZE OF DATA */ /************************************************/ -#define BMP280_PRESSURE_DATA_SIZE 3 -#define BMP280_DATA_FRAME_SIZE 6 -#define BMP280_CALIB_DATA_SIZE 24 +#define BMP280_PRESSURE_DATA_SIZE 3 +#define BMP280_DATA_FRAME_SIZE 6 +#define BMP280_CALIB_DATA_SIZE 24 /*******************************************************/ /* SAMPLING PERIOD COMPUTATION CONSTANT */ /*******************************************************/ -#define BMP280_STANDBY_CNT 8 -#define T_INIT_MAX (20) /* (20/16 = 1.25ms) */ -#define T_MEASURE_PER_OSRS_MAX (37) /* (37/16 = 2.31ms) */ -#define T_SETUP_PRESSURE_MAX (10) /* (10/16 = 0.62ms) */ +#define BMP280_STANDBY_CNT 8 +#define T_INIT_MAX (20) /* (20/16 = 1.25ms) */ +#define T_MEASURE_PER_OSRS_MAX (37) /* (37/16 = 2.31ms) */ +#define T_SETUP_PRESSURE_MAX (10) /* (10/16 = 0.62ms) */ /* * This is the measurement time required for pressure and temp */ -#define BMP280_COMPUTE_TIME \ - ((T_INIT_MAX + T_MEASURE_PER_OSRS_MAX * \ - ((BIT(BMP280_OVERSAMP_TEMP) >> 1) + \ - (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \ - (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) / 16) +#define BMP280_COMPUTE_TIME \ + ((T_INIT_MAX + \ + T_MEASURE_PER_OSRS_MAX * ((BIT(BMP280_OVERSAMP_TEMP) >> 1) + \ + (BIT(BMP280_OVERSAMP_PRES) >> 1)) + \ + (BMP280_OVERSAMP_PRES ? T_SETUP_PRESSURE_MAX : 0) + 15) / \ + 16) /* * These values are selected as per Bosch recommendation for @@ -158,15 +159,14 @@ /*******************************************************/ /* GET DRIVER DATA */ /*******************************************************/ -#define BMP280_GET_DATA(_s) \ - ((struct bmp280_drv_data_t *)(_s)->drv_data) +#define BMP280_GET_DATA(_s) ((struct bmp280_drv_data_t *)(_s)->drv_data) /* Min and Max sampling frequency in mHz based on x4 oversampling used */ /* FIXME - verify how chip is setup to make sure MAX is correct, manual says * "Typical", not Max. */ -#define BMP280_BARO_MIN_FREQ 75000 -#define BMP280_BARO_MAX_FREQ 87000 +#define BMP280_BARO_MIN_FREQ 75000 +#define BMP280_BARO_MAX_FREQ 87000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= BMP280_BARO_MAX_FREQ) #error "EC too slow for accelerometer" #endif @@ -208,8 +208,7 @@ struct bmp280_calib_param_t { * @range: bit offset to fit data in 16 bit or less. */ struct bmp280_drv_data_t { - - struct bmp280_calib_param_t calib_param; + struct bmp280_calib_param_t calib_param; uint16_t rate; uint16_t range; }; -- cgit v1.2.1 From db27bc74e75292ea11fa8f177f7751f023463171 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:21 -0600 Subject: zephyr/test/tasks/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ce9398638dc02fd9d60d549dfb6b2b4e7912ddc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730996 Reviewed-by: Jeremy Bettis --- zephyr/test/tasks/main.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/zephyr/test/tasks/main.c b/zephyr/test/tasks/main.c index ebf271d9b7..7d7b0053ea 100644 --- a/zephyr/test/tasks/main.c +++ b/zephyr/test/tasks/main.c @@ -107,7 +107,6 @@ static void test_task_get_current(void) run_test(&task_get_current1, &task_get_current2); } - static void timeout1(void) { const uint32_t start_ms = k_uptime_get(); @@ -201,7 +200,6 @@ static void test_event_delivered(void) run_test(&event_delivered1, &event_delivered2); } - static void event_mask_not_delivered1(void) { task_set_event(TASK_ID_TASK_2, 0x007F); @@ -226,7 +224,6 @@ static void test_event_mask_not_delivered(void) run_test(&event_mask_not_delivered1, &event_mask_not_delivered2); } - static void event_mask_extra1(void) { k_sleep(K_SECONDS(1)); @@ -253,7 +250,6 @@ static void test_event_mask_extra(void) run_test(&event_mask_extra1, &event_mask_extra2); } - static void empty_set_mask1(void) { k_sleep(K_SECONDS(1)); @@ -281,7 +277,6 @@ static void test_empty_set_mask(void) run_test(&empty_set_mask1, &empty_set_mask2); } - void test_main(void) { /* Note that test_set_event_before_task_start calls start_ec_tasks */ -- cgit v1.2.1 From 289f1ac67ac9fc3d4d1acec66e1a31830444b479 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:02 -0600 Subject: board/coachz/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf75f5dfbdd58f84b758d2b65756c2adccb52c8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728169 Reviewed-by: Jeremy Bettis --- board/coachz/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/coachz/usbc_config.c b/board/coachz/usbc_config.c index d6930586dd..cb63a780c5 100644 --- a/board/coachz/usbc_config.c +++ b/board/coachz/usbc_config.c @@ -11,8 +11,8 @@ #include "gpio.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 28a4ebe9617f89e429fa54537ae2cba685fe041b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:48 -0600 Subject: board/dojo/cbi_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d0f8cff04906b9f6180884373cd6cd9e7cc4fa7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728250 Reviewed-by: Jeremy Bettis --- board/dojo/cbi_fw_config.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/dojo/cbi_fw_config.c b/board/dojo/cbi_fw_config.c index 9972e02249..7db743a8f9 100644 --- a/board/dojo/cbi_fw_config.c +++ b/board/dojo/cbi_fw_config.c @@ -30,12 +30,12 @@ DECLARE_HOOK(HOOK_INIT, cbi_fw_config_init, HOOK_PRIO_FIRST); enum fw_config_kblight_type get_cbi_fw_config_kblight(void) { - return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) - >> FW_CONFIG_KB_BL_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >> + FW_CONFIG_KB_BL_OFFSET); } enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void) { - return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) - >> FW_CONFIG_KB_LAYOUT_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >> + FW_CONFIG_KB_LAYOUT_OFFSET); } -- cgit v1.2.1 From 100197ef5f12f9b7c8ca8360c5d543abe4a222cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:19 -0600 Subject: board/kodama/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec255f5f9626f919900065431615b96e69b8fae2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728562 Reviewed-by: Jeremy Bettis --- board/kodama/led.c | 65 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/board/kodama/led.c b/board/kodama/led.c index d96b340d73..2abfd55353 100644 --- a/board/kodama/led.c +++ b/board/kodama/led.c @@ -11,45 +11,48 @@ #include "led_onoff_states.h" #include "ec_commands.h" -#define LED_RED MT6370_LED_ID1 -#define LED_GREEN MT6370_LED_ID2 -#define LED_WHITE MT6370_LED_ID3 +#define LED_RED MT6370_LED_ID1 +#define LED_GREEN MT6370_LED_ID2 +#define LED_WHITE MT6370_LED_ID3 -#define LED_MASK_OFF 0 -#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN -#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN -#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK3DIM_EN +#define LED_MASK_OFF 0 +#define LED_MASK_RED MT6370_MASK_RGB_ISNK1DIM_EN +#define LED_MASK_GREEN MT6370_MASK_RGB_ISNK2DIM_EN +#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK3DIM_EN __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, LED_ONE_SEC / 2} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, LED_ONE_SEC / 2 } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 0327231c427cbb4c53add50167c7a181e108b421 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:45 -0600 Subject: zephyr/projects/corsola/src/krabby/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d9228535f9d9354700a036a53008a65200d18b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730743 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/krabby/led.c | 58 +++++++++++++++++++------------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/led.c b/zephyr/projects/corsola/src/krabby/led.c index c001615402..0d45105ba0 100644 --- a/zephyr/projects/corsola/src/krabby/led.c +++ b/zephyr/projects/corsola/src/krabby/led.c @@ -30,30 +30,40 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -75,8 +85,8 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); - LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", - ch->dev->name, percent, pulse_ns); + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, + percent, pulse_ns); rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, ch->flags); -- cgit v1.2.1 From f71ee22c3ad5762131b72af23c917452b15b18f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:29 -0600 Subject: chip/stm32/usb_dwc_stream.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2af3aa3f7040444cb25cfa940149c9c61ec0f1ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729573 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_stream.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/stm32/usb_dwc_stream.c b/chip/stm32/usb_dwc_stream.c index 2f20d88dda..8d83069309 100644 --- a/chip/stm32/usb_dwc_stream.c +++ b/chip/stm32/usb_dwc_stream.c @@ -9,7 +9,7 @@ #include "util.h" #include "console.h" -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* * This function tries to shove new bytes from the USB host into the queue for @@ -24,9 +24,8 @@ int rx_stream_handler(struct usb_stream_config const *config) /* If we have some, try to shove them into the queue */ if (rx_count) { - size_t added = QUEUE_ADD_UNITS( - config->producer.queue, config->rx_ram, - rx_count); + size_t added = QUEUE_ADD_UNITS(config->producer.queue, + config->rx_ram, rx_count); if (added != rx_count) { CPRINTF("rx_stream_handler: failed ep%d " "queue %d bytes, accepted %d\n", @@ -60,7 +59,7 @@ int tx_stream_handler(struct usb_stream_config const *config) /* Reset stream */ void usb_stream_event(struct usb_stream_config const *config, - enum usb_ep_event evt) + enum usb_ep_event evt) { if (evt != USB_EVENT_RESET) return; -- cgit v1.2.1 From 47492263a547a37263c60b6fb60462e677521dda Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:41 -0600 Subject: board/anahera/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If934a27169fc5962bbaf7cc0f8212d151b9ed8e0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728007 Reviewed-by: Jeremy Bettis --- board/anahera/sensors.c | 56 +++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 32 deletions(-) diff --git a/board/anahera/sensors.c b/board/anahera/sensors.c index 851930d1d3..1b4e657843 100644 --- a/board/anahera/sensors.c +++ b/board/anahera/sensors.c @@ -44,38 +44,30 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_FAN] = { - .name = "Fan", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_FAN - }, - [TEMP_SENSOR_2_SOC] = { - .name = "SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_SOC - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, - [TEMP_SENSOR_4_REGULATOR] = { - .name = "Regulator", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_REGULATOR - }, + [TEMP_SENSOR_1_FAN] = { .name = "Fan", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_FAN }, + [TEMP_SENSOR_2_SOC] = { .name = "SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_SOC }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, + [TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_REGULATOR }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -94,8 +86,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -109,8 +101,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -125,8 +117,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_REGULATOR \ - { \ +#define THERMAL_REGULATOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(55), \ [EC_TEMP_THRESH_HALT] = C_TO_K(60), \ -- cgit v1.2.1 From 4fa2221c74e627f8f38a35751621151cb92c6266 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:18 -0600 Subject: board/nami/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e92a95acdfebb6af537e6ddd32f311cba657546 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728719 Reviewed-by: Jeremy Bettis --- board/nami/led.c | 122 ++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 80 insertions(+), 42 deletions(-) diff --git a/board/nami/led.c b/board/nami/led.c index 17af4d5f82..674421c43e 100644 --- a/board/nami/led.c +++ b/board/nami/led.c @@ -38,8 +38,8 @@ #include "timer.h" #include "util.h" -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -79,19 +79,19 @@ struct led_pattern { uint8_t pulse; }; -#define PULSE_NO 0 -#define PULSE(interval) (BIT(7) | (interval)) -#define BLINK(interval) (interval) -#define ALTERNATE(interval) (BIT(6) | (interval)) -#define IS_PULSING(pulse) ((pulse) & 0x80) -#define IS_ALTERNATE(pulse) ((pulse) & 0x40) -#define PULSE_INTERVAL(pulse) (((pulse) & 0x3f) * 100 * MSEC) +#define PULSE_NO 0 +#define PULSE(interval) (BIT(7) | (interval)) +#define BLINK(interval) (interval) +#define ALTERNATE(interval) (BIT(6) | (interval)) +#define IS_PULSING(pulse) ((pulse)&0x80) +#define IS_ALTERNATE(pulse) ((pulse)&0x40) +#define PULSE_INTERVAL(pulse) (((pulse)&0x3f) * 100 * MSEC) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT] - [LED_POWER_STATE_COUNT]; + [LED_POWER_STATE_COUNT]; /* * Nami/Vayne - One dual color LED: @@ -105,11 +105,17 @@ typedef struct led_pattern led_patterns[LED_CHARGE_STATE_COUNT] */ const static led_patterns battery_pattern_0 = { /* discharging: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE(10)}, {LED_OFF, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE(10) }, + { LED_OFF, PULSE_NO } }, /* charging: s0, s3, s5 */ - {{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}}, + { { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO } }, }; /* @@ -117,11 +123,15 @@ const static led_patterns battery_pattern_0 = { */ const static led_patterns battery_pattern_1 = { /* discharging: s0, s3, s5 */ - {{LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}}, + { { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } }, /* charging: s0, s3, s5 */ - {{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}}, + { { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO } }, }; /* @@ -132,11 +142,15 @@ const static led_patterns battery_pattern_1 = { */ const static led_patterns battery_pattern_2 = { /* discharging: s0, s3, s5 */ - {{LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}, {LED_OFF, PULSE_NO}}, + { { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO }, { LED_OFF, PULSE_NO } }, /* charging: s0, s3, s5 */ - {{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}}, + { { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO } }, }; /* @@ -144,11 +158,17 @@ const static led_patterns battery_pattern_2 = { */ const static led_patterns power_pattern_1 = { /* discharging: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, BLINK(10) }, + { LED_OFF, PULSE_NO } }, /* charging: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, BLINK(10) }, + { LED_OFF, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, BLINK(10) }, + { LED_OFF, PULSE_NO } }, }; /* @@ -159,11 +179,17 @@ const static led_patterns power_pattern_1 = { */ const static led_patterns power_pattern_2 = { /* discharging: s0, s3, s5 */ - {{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}}, + { { LED_WHITE, 0 }, + { LED_WHITE, ALTERNATE(BLINK(10)) }, + { LED_OFF, 0 } }, /* charging: s0, s3, s5 */ - {{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}}, + { { LED_WHITE, 0 }, + { LED_WHITE, ALTERNATE(BLINK(10)) }, + { LED_OFF, 0 } }, /* full: s0, s3, s5 */ - {{LED_WHITE, 0}, {LED_WHITE, ALTERNATE(BLINK(10))}, {LED_OFF, 0}}, + { { LED_WHITE, 0 }, + { LED_WHITE, ALTERNATE(BLINK(10)) }, + { LED_OFF, 0 } }, }; /* @@ -178,30 +204,42 @@ const static led_patterns power_pattern_2 = { */ const static led_patterns battery_pattern_3 = { /* discharging: s0, s3, s5 */ - {{LED_WHITE, 0}, {LED_AMBER, ALTERNATE(BLINK(10))}, {LED_OFF, 0}}, + { { LED_WHITE, 0 }, + { LED_AMBER, ALTERNATE(BLINK(10)) }, + { LED_OFF, 0 } }, /* charging: s0, s3, s5 */ - {{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}}, + { { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO } }, }; const static led_patterns battery_pattern_4 = { /* discharging: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, BLINK(10)}, {LED_OFF, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, BLINK(10) }, + { LED_OFF, PULSE_NO } }, /* charging: s0, s3, s5 */ - {{LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}, {LED_AMBER, PULSE_NO}}, + { { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO }, + { LED_AMBER, PULSE_NO } }, /* full: s0, s3, s5 */ - {{LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}, {LED_WHITE, PULSE_NO}}, + { { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO }, + { LED_WHITE, PULSE_NO } }, }; /* Patterns for battery LED and power LED. Initialized at run-time. */ static led_patterns const *patterns[2]; /* Pattern for battery error. Only blinking battery LED is supported. */ -static struct led_pattern battery_error = {LED_AMBER, BLINK(10)}; +static struct led_pattern battery_error = { LED_AMBER, BLINK(10) }; /* Pattern for low state of charge. Only battery LED is supported. */ -static struct led_pattern low_battery = {LED_WHITE, BLINK(10)}; +static struct led_pattern low_battery = { LED_WHITE, BLINK(10) }; /* Pattern for factory mode. Blinking 2-color battery LED. */ -static struct led_pattern battery_factory = {LED_FACTORY, BLINK(20)}; +static struct led_pattern battery_factory = { LED_FACTORY, BLINK(20) }; static int low_battery_soc; static void led_charge_hook(void); static enum led_power_state power_state; @@ -222,7 +260,7 @@ static void led_init(void) patterns[1] = &power_pattern_1; } battery_error.pulse = BLINK(5); - low_battery_soc = 100; /* 10.0% */ + low_battery_soc = 100; /* 10.0% */ break; case PROJECT_PANTHEON: patterns[0] = &battery_pattern_2; @@ -452,7 +490,7 @@ void config_led(enum ec_led_id id, enum led_charge_state charge) pattern = patterns[id]; if (!pattern) - return; /* This LED isn't present */ + return; /* This LED isn't present */ start_tick(id, &(*pattern)[charge][power_state]); } @@ -505,8 +543,7 @@ static void call_handler(void) if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) led_factory(1); break; - default: - ; + default:; } } @@ -587,9 +624,10 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]", - "Turn on/off LED."); +DECLARE_CONSOLE_COMMAND( + led, command_led, + "[debug|red|green|amber|off|alert|s0|s3|s5|conf|factory]", + "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { -- cgit v1.2.1 From 853a90461f7da6873373776cd631fedc90da1265 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:50 -0600 Subject: chip/mec1322/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic5492cd159876ff38b978a6e1a9b129be969e5d4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729317 Reviewed-by: Jeremy Bettis --- chip/mec1322/fan.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c index 1f54389fc7..f7ad369a7e 100644 --- a/chip/mec1322/fan.c +++ b/chip/mec1322/fan.c @@ -31,7 +31,6 @@ static int rpm_setting; static int duty_setting; static int in_rpm_mode = 1; - static void clear_status(void) { /* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */ -- cgit v1.2.1 From 78438ecbbcc6f7fb648218fbcb8a455b4628a009 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Tue, 28 Jun 2022 11:35:31 -0700 Subject: include/ec_commands.h: Format with clang-format Minor manual tweaking was added to add trailing commas where required, leaving the diff produced by clang-format much smaller. BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e9d0025d9f581e00160eeb98b1c1f12aed2d044 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730260 Reviewed-by: Jeremy Bettis --- include/ec_commands.h | 1709 +++++++++++++++++++++++++------------------------ 1 file changed, 858 insertions(+), 851 deletions(-) diff --git a/include/ec_commands.h b/include/ec_commands.h index 62da3c4b94..24f53e449b 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -32,7 +32,7 @@ #ifndef BUILD_ASSERT #define BUILD_ASSERT(_cond) #endif /* !BUILD_ASSERT */ -#endif /* CHROMIUM_EC */ +#endif /* CHROMIUM_EC */ #ifdef __KERNEL__ #include @@ -45,11 +45,11 @@ */ #ifndef BIT -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) #endif #ifndef BIT_ULL -#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) #endif /* @@ -67,7 +67,7 @@ #endif #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ #ifdef __cplusplus extern "C" { @@ -80,28 +80,28 @@ extern "C" { * determined in other ways. Remove this once the kernel code no longer * depends on it. */ -#define EC_PROTO_VERSION 0x00000002 +#define EC_PROTO_VERSION 0x00000002 /* Command version mask */ #define EC_VER_MASK(version) BIT(version) /* I/O addresses for ACPI commands */ -#define EC_LPC_ADDR_ACPI_DATA 0x62 -#define EC_LPC_ADDR_ACPI_CMD 0x66 +#define EC_LPC_ADDR_ACPI_DATA 0x62 +#define EC_LPC_ADDR_ACPI_CMD 0x66 /* I/O addresses for host command */ -#define EC_LPC_ADDR_HOST_DATA 0x200 -#define EC_LPC_ADDR_HOST_CMD 0x204 +#define EC_LPC_ADDR_HOST_DATA 0x200 +#define EC_LPC_ADDR_HOST_CMD 0x204 /* I/O addresses for host command args and params */ /* Protocol version 2 */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ -#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is - * EC_PROTO2_MAX_PARAM_SIZE - */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */ +/* For version 2 params; size is EC_PROTO2_MAX_PARAM_SIZE */ +#define EC_LPC_ADDR_HOST_PARAM 0x804 + /* Protocol version 3 */ -#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ +#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ +#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ /* * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff @@ -110,65 +110,65 @@ extern "C" { * Other BIOSes report only the I/O port region spanned by the Microchip * MEC series EC; an attempt to address a larger region may fail. */ -#define EC_HOST_CMD_REGION0 0x800 -#define EC_HOST_CMD_REGION1 0x880 -#define EC_HOST_CMD_REGION_SIZE 0x80 +#define EC_HOST_CMD_REGION0 0x800 +#define EC_HOST_CMD_REGION1 0x880 +#define EC_HOST_CMD_REGION_SIZE 0x80 #define EC_HOST_CMD_MEC_REGION_SIZE 0x8 /* EC command register bit functions */ -#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ -#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ -#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ -#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ -#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ -#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ -#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ - -#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ -#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ +#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */ +#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */ +#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */ +#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */ +#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */ +#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */ +#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */ + +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */ /* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ -#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ -#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ -#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */ +#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ +#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ -#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ -#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ +#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ +#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */ /* Unused 0x28 - 0x2f */ -#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ +#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */ /* Unused 0x31 - 0x33 */ -#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ +#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */ /* Battery values are all 32 bits, unless otherwise noted. */ -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ -#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ -#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */ +#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */ +#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */ /* Unused 0x4f */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ /* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ -#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */ /* Unused 0x84 - 0x8f */ -#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ +#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/ /* Unused 0x91 */ -#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ +#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */ /* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */ /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ -#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ +#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ /* Unused 0xa6 - 0xdf */ /* @@ -179,82 +179,82 @@ extern "C" { #define EC_MEMMAP_NO_ACPI 0xe0 /* Define the format of the accelerometer mapped memory status byte. */ -#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f -#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) -#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) +#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f +#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4) +#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7) /* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2. */ -#define EC_TEMP_SENSOR_B_ENTRIES 8 +#define EC_TEMP_SENSOR_B_ENTRIES 8 /* Max temp sensor entries for host commands */ -#define EC_MAX_TEMP_SENSOR_ENTRIES (EC_TEMP_SENSOR_ENTRIES + \ - EC_TEMP_SENSOR_B_ENTRIES) +#define EC_MAX_TEMP_SENSOR_ENTRIES \ + (EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) /* Special values for mapped temperature sensors */ -#define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe -#define EC_TEMP_SENSOR_NOT_POWERED 0xfd +#define EC_TEMP_SENSOR_NOT_PRESENT 0xff +#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_NOT_POWERED 0xfd #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc /* * The offset of temperature value stored in mapped memory. This allows * reporting a temperature range of 200K to 454K = -73C to 181C. */ -#define EC_TEMP_SENSOR_OFFSET 200 +#define EC_TEMP_SENSOR_OFFSET 200 /* * Number of ALS readings at EC_MEMMAP_ALS */ -#define EC_ALS_ENTRIES 2 +#define EC_ALS_ENTRIES 2 /* * The default value a temperature sensor will return when it is present but * has not been read this boot. This is a reasonable number to avoid * triggering alarms on the host. */ -#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) +#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET) -#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ -#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ +#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ /* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_AC_PRESENT 0x01 #define EC_BATT_FLAG_BATT_PRESENT 0x02 -#define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_DISCHARGING 0x04 +#define EC_BATT_FLAG_CHARGING 0x08 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10 /* Set if some of the static/dynamic data is invalid (or outdated). */ #define EC_BATT_FLAG_INVALID_DATA 0x20 /* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 /* Was recovery requested via keyboard; now unused. */ -#define EC_SWITCH_IGNORE1 0x08 +#define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 +#define EC_SWITCH_IGNORE0 0x20 /* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ -#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 +#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01 /* Host command interface supports version 3 protocol */ -#define EC_HOST_CMD_FLAG_VERSION_3 0x02 +#define EC_HOST_CMD_FLAG_VERSION_3 0x02 /* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ -#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ -#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ -#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ +#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */ +#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */ +#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */ +#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */ +#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */ /*****************************************************************************/ /* @@ -322,19 +322,19 @@ extern "C" { /* Valid addresses in ACPI memory space, for read/write commands */ /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 +#define EC_ACPI_MEM_VERSION 0x00 /* * Test location; writing value here updates test compliment byte to (0xff - * value). */ -#define EC_ACPI_MEM_TEST 0x01 +#define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ -#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 +#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 /* Keyboard backlight brightness percent (0 - 100) */ #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03 /* DPTF Target Fan Duty (0-100, 0xff for auto/none) */ -#define EC_ACPI_MEM_FAN_DUTY 0x04 +#define EC_ACPI_MEM_FAN_DUTY 0x04 /* * DPTF temp thresholds. Any of the EC's temp sensors can have up to two @@ -351,9 +351,9 @@ extern "C" { * have tripped". Setting or enabling the thresholds for a sensor will clear * the unread event count for that sensor. */ -#define EC_ACPI_MEM_TEMP_ID 0x05 -#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 -#define EC_ACPI_MEM_TEMP_COMMIT 0x07 +#define EC_ACPI_MEM_TEMP_ID 0x05 +#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06 +#define EC_ACPI_MEM_TEMP_COMMIT 0x07 /* * Here are the bits for the COMMIT register: * bit 0 selects the threshold index for the chosen sensor (0/1) @@ -378,12 +378,12 @@ extern "C" { */ /* DPTF battery charging current limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 +#define EC_ACPI_MEM_CHARGING_LIMIT 0x08 /* Charging limit is specified in 64 mA steps */ -#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 +#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64 /* Value to disable DPTF battery charging limit */ -#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff +#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff /* * Report device orientation @@ -396,10 +396,10 @@ extern "C" { * 0 Tablet Mode Device Indicator (TBMD) */ #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09 -#define EC_ACPI_MEM_TBMD_SHIFT 0 -#define EC_ACPI_MEM_TBMD_MASK 0x1 -#define EC_ACPI_MEM_DDPN_SHIFT 1 -#define EC_ACPI_MEM_DDPN_MASK 0x7 +#define EC_ACPI_MEM_TBMD_SHIFT 0 +#define EC_ACPI_MEM_TBMD_MASK 0x1 +#define EC_ACPI_MEM_DDPN_SHIFT 1 +#define EC_ACPI_MEM_DDPN_MASK 0x7 /* * Report device features. Uses the same format as the host command, except: @@ -422,7 +422,7 @@ extern "C" { #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11 -#define EC_ACPI_MEM_BATTERY_INDEX 0x12 +#define EC_ACPI_MEM_BATTERY_INDEX 0x12 /* * USB Port Power. Each bit indicates whether the corresponding USB ports' power @@ -461,40 +461,38 @@ extern "C" { #define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14 #define USB_RETIMER_FW_UPDATE_OP_SHIFT 4 -#define USB_RETIMER_FW_UPDATE_ERR 0xfe +#define USB_RETIMER_FW_UPDATE_ERR 0xfe #define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff /* Mask to clear unused MUX bits in retimer firmware update */ -#define USB_RETIMER_FW_UPDATE_MUX_MASK (USB_PD_MUX_USB_ENABLED | \ - USB_PD_MUX_DP_ENABLED | \ - USB_PD_MUX_SAFE_MODE | \ - USB_PD_MUX_TBT_COMPAT_ENABLED | \ - USB_PD_MUX_USB4_ENABLED) +#define USB_RETIMER_FW_UPDATE_MUX_MASK \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) /* Retimer firmware update operations */ #define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */ #define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */ -#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ -#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ -#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ -#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ -#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ +#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */ +#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */ +#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */ +#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */ +#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ -#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f) #define EC_ACPI_MEM_USB_RETIMER_OP(x) \ - (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + (((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data * is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2. */ -#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 -#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 +#define EC_ACPI_MEM_MAPPED_BEGIN 0x20 +#define EC_ACPI_MEM_MAPPED_SIZE 0xe0 /* Current version of ACPI memory address space */ #define EC_ACPI_MEM_VERSION_CURRENT 2 - /* * This header file is used in coreboot both in C and ACPI code. The ACPI code * is pre-processed to handle constants but the ASL compiler is unable to @@ -514,7 +512,7 @@ extern "C" { #ifndef __aligned #define __aligned(x) __attribute__((aligned(x))) #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ /* * Attributes for EC request and response packets. Just defining __packed @@ -581,7 +579,7 @@ extern "C" { #define __ec_todo_packed __packed #define __ec_todo_unpacked -#else /* !CONFIG_HOSTCMD_ALIGNED */ +#else /* !CONFIG_HOSTCMD_ALIGNED */ /* * Packed structures make no assumption about alignment, so they do inefficient @@ -596,25 +594,25 @@ extern "C" { #define __ec_todo_packed __packed #define __ec_todo_unpacked -#endif /* !CONFIG_HOSTCMD_ALIGNED */ +#endif /* !CONFIG_HOSTCMD_ALIGNED */ /* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 +#define EC_LPC_STATUS_TO_HOST 0x01 /* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 +#define EC_LPC_STATUS_FROM_HOST 0x02 /* EC is processing a command */ -#define EC_LPC_STATUS_PROCESSING 0x04 +#define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 +#define EC_LPC_STATUS_LAST_CMD 0x08 /* EC is in burst mode */ -#define EC_LPC_STATUS_BURST_MODE 0x10 +#define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ #define EC_LPC_STATUS_SCI_PENDING 0x20 /* SMI event is pending (requesting SMI query) */ #define EC_LPC_STATUS_SMI_PENDING 0x40 /* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 +#define EC_LPC_STATUS_RESERVED 0x80 /* * EC is busy. This covers both the EC processing a command, and the host has @@ -635,21 +633,21 @@ enum ec_status { EC_RES_INVALID_RESPONSE = 5, EC_RES_INVALID_VERSION = 6, EC_RES_INVALID_CHECKSUM = 7, - EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ - EC_RES_UNAVAILABLE = 9, /* No response available */ - EC_RES_TIMEOUT = 10, /* We got a timeout */ - EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ - EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ - EC_RES_BUS_ERROR = 15, /* Communications bus error */ - EC_RES_BUSY = 16, /* Up but too busy. Should retry */ - EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ - EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ - EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ - EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ - - EC_RES_MAX = UINT16_MAX /**< Force enum to be 16 bits */ + EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */ + EC_RES_UNAVAILABLE = 9, /* No response available */ + EC_RES_TIMEOUT = 10, /* We got a timeout */ + EC_RES_OVERFLOW = 11, /* Table / data overflow */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ + EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */ + EC_RES_BUS_ERROR = 15, /* Communications bus error */ + EC_RES_BUSY = 16, /* Up but too busy. Should retry */ + EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */ + EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */ + EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ + EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); @@ -741,10 +739,10 @@ enum host_event_code { * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is * not initialized on the EC, or improperly configured on the host. */ - EC_HOST_EVENT_INVALID = 32 + EC_HOST_EVENT_INVALID = 32, }; /* Host event mask */ -#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1) +#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1) /** * struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS @@ -779,7 +777,7 @@ struct ec_lpc_host_args { * response. Command version is 0 and response data from EC is at * EC_LPC_ADDR_OLD_PARAM with unknown length. */ -#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 +#define EC_HOST_ARGS_FLAG_TO_HOST 0x02 /*****************************************************************************/ /* @@ -821,12 +819,12 @@ struct ec_lpc_host_args { * request, the AP will clock in bytes until it sees the framing byte, then * clock in the response packet. */ -#define EC_SPI_FRAME_START 0xec +#define EC_SPI_FRAME_START 0xec /* * Padding bytes which are clocked out after the end of a response packet. */ -#define EC_SPI_PAST_END 0xed +#define EC_SPI_PAST_END 0xed /* * EC is ready to receive, and has ignored the byte sent by the AP. EC expects @@ -837,36 +835,36 @@ struct ec_lpc_host_args { * CS goes low. This macro has the Most Significant Bit set to zero, * so SDO will not be driven high when CS goes low. */ -#define EC_SPI_RX_READY 0x78 +#define EC_SPI_RX_READY 0x78 /* * EC has started receiving the request from the AP, but hasn't started * processing it yet. */ -#define EC_SPI_RECEIVING 0xf9 +#define EC_SPI_RECEIVING 0xf9 /* EC has received the entire request from the AP and is processing it. */ -#define EC_SPI_PROCESSING 0xfa +#define EC_SPI_PROCESSING 0xfa /* * EC received bad data from the AP, such as a packet header with an invalid * length. EC will ignore all data until chip select deasserts. */ -#define EC_SPI_RX_BAD_DATA 0xfb +#define EC_SPI_RX_BAD_DATA 0xfb /* * EC received data from the AP before it was ready. That is, the AP asserted * chip select and started clocking data before the EC was ready to receive it. * EC will ignore all data until chip select deasserts. */ -#define EC_SPI_NOT_READY 0xfc +#define EC_SPI_NOT_READY 0xfc /* * EC was ready to receive a request from the AP. EC has treated the byte sent * by the AP as part of a request packet, or (for old-style ECs) is processing * a fully received packet but is not ready to respond yet. */ -#define EC_SPI_OLD_READY 0xfd +#define EC_SPI_OLD_READY 0xfd /*****************************************************************************/ @@ -888,22 +886,22 @@ struct ec_lpc_host_args { */ #define EC_PROTO2_REQUEST_HEADER_BYTES 3 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1 -#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \ - EC_PROTO2_REQUEST_TRAILER_BYTES) +#define EC_PROTO2_REQUEST_OVERHEAD \ + (EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES) #define EC_PROTO2_RESPONSE_HEADER_BYTES 2 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1 -#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES) +#define EC_PROTO2_RESPONSE_OVERHEAD \ + (EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES) /* Parameter length was limited by the LPC interface */ #define EC_PROTO2_MAX_PARAM_SIZE 0xfc /* Maximum request and response packet sizes for protocol version 2 */ -#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) -#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \ - EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_REQUEST_SIZE \ + (EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) +#define EC_PROTO2_MAX_RESPONSE_SIZE \ + (EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE) /*****************************************************************************/ @@ -1075,15 +1073,15 @@ struct ec_host_response4 { } __ec_align4; /* Fields in fields0 byte */ -#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f -#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 -#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 -#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 -#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 +#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f +#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10 +#define EC_PACKET4_0_SEQ_NUM_SHIFT 5 +#define EC_PACKET4_0_SEQ_NUM_MASK 0x60 +#define EC_PACKET4_0_SEQ_DUP_MASK 0x80 /* Fields in fields1 byte */ -#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ -#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 +#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */ +#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80 /*****************************************************************************/ /* @@ -1157,7 +1155,7 @@ enum ec_image { EC_IMAGE_RW, EC_IMAGE_RW_A = EC_IMAGE_RW, EC_IMAGE_RO_B, - EC_IMAGE_RW_B + EC_IMAGE_RW_B, }; /** @@ -1170,7 +1168,7 @@ enum ec_image { struct ec_response_get_version { char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ + char reserved[32]; /* Changed to cros_fwid_ro in version 1 */ uint32_t current_image; } __ec_align4; @@ -1190,9 +1188,9 @@ struct ec_response_get_version { struct ec_response_get_version_v1 { char version_string_ro[32]; char version_string_rw[32]; - char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ + char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */ uint32_t current_image; - char cros_fwid_rw[32]; /* Added in version 1 */ + char cros_fwid_rw[32]; /* Added in version 1 */ } __ec_align4; /* Read test */ @@ -1305,11 +1303,11 @@ struct ec_response_get_cmd_versions { * lpc must read the status from the command register. Attempting this on * lpc will overwrite the args/parameter space and corrupt its data. */ -#define EC_CMD_GET_COMMS_STATUS 0x0009 +#define EC_CMD_GET_COMMS_STATUS 0x0009 /* Avoid using ec_status which is for return values */ enum ec_comms_status { - EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ + EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */ }; /** @@ -1318,11 +1316,11 @@ enum ec_comms_status { * @flags: Mask of enum ec_comms_status. */ struct ec_response_get_comms_status { - uint32_t flags; /* Mask of enum ec_comms_status */ + uint32_t flags; /* Mask of enum ec_comms_status */ } __ec_align4; /* Fake a variety of responses, purely for testing purposes. */ -#define EC_CMD_TEST_PROTOCOL 0x000A +#define EC_CMD_TEST_PROTOCOL 0x000A /* Tell the EC what to send back to us. */ struct ec_params_test_protocol { @@ -1337,7 +1335,7 @@ struct ec_response_test_protocol { } __ec_align4; /* Get protocol information */ -#define EC_CMD_GET_PROTOCOL_INFO 0x000B +#define EC_CMD_GET_PROTOCOL_INFO 0x000B /* Flags for ec_response_get_protocol_info.flags */ /* EC_RES_IN_PROGRESS may be returned if a command is slow */ @@ -1359,12 +1357,11 @@ struct ec_response_get_protocol_info { uint32_t flags; } __ec_align4; - /*****************************************************************************/ /* Get/Set miscellaneous values */ /* The upper byte of .flags tells what to do (nothing means "get") */ -#define EC_GSV_SET 0x80000000 +#define EC_GSV_SET 0x80000000 /* * The lower three bytes of .flags identifies the parameter, if that has @@ -1383,11 +1380,11 @@ struct ec_response_get_set_value { } __ec_align4; /* More than one command can use these structs to get/set parameters. */ -#define EC_CMD_GSV_PAUSE_IN_S5 0x000C +#define EC_CMD_GSV_PAUSE_IN_S5 0x000C /*****************************************************************************/ /* List the features supported by the firmware */ -#define EC_CMD_GET_FEATURES 0x000D +#define EC_CMD_GET_FEATURES 0x000D /* Supported features */ enum ec_feature_code { @@ -1726,9 +1723,9 @@ struct ec_params_flash_erase { * permitted while erasing. (For instance, STM32F4). */ enum ec_flash_erase_cmd { - FLASH_ERASE_SECTOR, /* Erase and wait for result */ - FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ - FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ + FLASH_ERASE_SECTOR, /* Erase and wait for result */ + FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */ + FLASH_ERASE_GET_RESULT, /* Ask for last erase result */ }; /** @@ -1739,8 +1736,8 @@ enum ec_flash_erase_cmd { * @params: Same as v0 parameters. */ struct ec_params_flash_erase_v1 { - uint8_t cmd; - uint8_t reserved; + uint8_t cmd; + uint8_t reserved; uint16_t flag; struct ec_params_flash_erase params; } __ec_align4; @@ -1756,22 +1753,22 @@ struct ec_params_flash_erase_v1 { * If mask=0, simply returns the current flags state. */ #define EC_CMD_FLASH_PROTECT 0x0015 -#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ +#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */ /* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) +#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW BIT(1) +#define EC_FLASH_PROTECT_RO_NOW BIT(1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW BIT(2) +#define EC_FLASH_PROTECT_ALL_NOW BIT(2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) +#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by @@ -1779,18 +1776,17 @@ struct ec_params_flash_erase_v1 { */ #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5) /* Entire flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6) /* RW flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) +#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7) /* RW flash code protected now. */ -#define EC_FLASH_PROTECT_RW_NOW BIT(8) +#define EC_FLASH_PROTECT_RW_NOW BIT(8) /* Rollback information flash region protected when the EC boots */ -#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) +#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9) /* Rollback information flash region protected now */ -#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) +#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10) /* Error - Unknown error */ -#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) - +#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11) /** * struct ec_params_flash_protect - Parameters for the flash protect command. @@ -1886,7 +1882,6 @@ struct ec_response_flash_spi_info { uint8_t sr1, sr2; } __ec_align1; - /* Select flash during flash operations */ #define EC_CMD_FLASH_SELECT 0x0019 @@ -1898,22 +1893,21 @@ struct ec_params_flash_select { uint8_t select; } __ec_align4; - /** * Request random numbers to be generated and returned. * Can be used to test the random number generator is truly random. * See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and * https://webhome.phy.duke.edu/~rgb/General/dieharder.php. */ -#define EC_CMD_RAND_NUM 0x001A +#define EC_CMD_RAND_NUM 0x001A #define EC_VER_RAND_NUM 0 struct ec_params_rand_num { - uint16_t num_rand_bytes; /**< num random bytes to generate */ + uint16_t num_rand_bytes; /**< num random bytes to generate */ } __ec_align4; struct ec_response_rand_num { - uint8_t rand[0]; /**< generated random numbers */ + uint8_t rand[0]; /**< generated random numbers */ } __ec_align4; BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0); @@ -1981,9 +1975,9 @@ enum sysinfo_flags { }; struct ec_response_sysinfo { - uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ - uint32_t current_image; /**< enum ec_current_image */ - uint32_t flags; /**< enum sysinfo_flags */ + uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */ + uint32_t current_image; /**< enum ec_current_image */ + uint32_t flags; /**< enum sysinfo_flags */ } __ec_align4; /*****************************************************************************/ @@ -2056,20 +2050,20 @@ enum ec_pwm_type { }; struct ec_params_pwm_set_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ } __ec_align4; #define EC_CMD_PWM_GET_DUTY 0x0026 struct ec_params_pwm_get_duty { - uint8_t pwm_type; /* ec_pwm_type */ - uint8_t index; /* Type-specific index, or 0 if unique */ + uint8_t pwm_type; /* ec_pwm_type */ + uint8_t index; /* Type-specific index, or 0 if unique */ } __ec_align1; struct ec_response_pwm_get_duty { - uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ + uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */ } __ec_align2; /*****************************************************************************/ @@ -2096,8 +2090,8 @@ struct lightbar_params_v0 { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2105,24 +2099,24 @@ struct lightbar_params_v0 { /* Oscillation */ uint8_t new_s0; - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; struct lightbar_params_v1 { @@ -2130,8 +2124,8 @@ struct lightbar_params_v1 { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2151,27 +2145,27 @@ struct lightbar_params_v1 { uint8_t tap_idx[3]; /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ /* Battery level thresholds */ uint8_t battery_threshold[LB_BATTERY_LEVELS - 1]; /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; /* Lightbar command params v2 @@ -2188,8 +2182,8 @@ struct lightbar_params_v2_timing { int32_t google_ramp_up; int32_t google_ramp_down; int32_t s3s0_ramp_up; - int32_t s0_tick_delay[2]; /* AC=0/1 */ - int32_t s0a_tick_delay[2]; /* AC=0/1 */ + int32_t s0_tick_delay[2]; /* AC=0/1 */ + int32_t s0a_tick_delay[2]; /* AC=0/1 */ int32_t s0s3_ramp_down; int32_t s3_sleep_for; int32_t s3_ramp_up; @@ -2213,16 +2207,16 @@ struct lightbar_params_v2_tap { struct lightbar_params_v2_oscillation { /* Oscillation */ - uint8_t osc_min[2]; /* AC=0/1 */ - uint8_t osc_max[2]; /* AC=0/1 */ - uint8_t w_ofs[2]; /* AC=0/1 */ + uint8_t osc_min[2]; /* AC=0/1 */ + uint8_t osc_max[2]; /* AC=0/1 */ + uint8_t w_ofs[2]; /* AC=0/1 */ } __ec_todo_packed; struct lightbar_params_v2_brightness { /* Brightness limits based on the backlight and AC. */ - uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ - uint8_t bright_bl_on_min[2]; /* AC=0/1 */ - uint8_t bright_bl_on_max[2]; /* AC=0/1 */ + uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */ + uint8_t bright_bl_on_min[2]; /* AC=0/1 */ + uint8_t bright_bl_on_max[2]; /* AC=0/1 */ } __ec_todo_packed; struct lightbar_params_v2_thresholds { @@ -2232,14 +2226,14 @@ struct lightbar_params_v2_thresholds { struct lightbar_params_v2_colors { /* Map [AC][battery_level] to color index */ - uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ - uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ + uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */ + uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */ /* s5: single color pulse on inhibited power-up */ uint8_t s5_idx; /* Color palette */ - struct rgb_s color[8]; /* 0-3 are Google colors */ + struct rgb_s color[8]; /* 0-3 are Google colors */ } __ec_todo_packed; /* Lightbar program. */ @@ -2250,7 +2244,7 @@ struct lightbar_program { } __ec_todo_unpacked; struct ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ + uint8_t cmd; /* Command (see enum lightbar_command) */ union { /* * The following commands have no args: @@ -2315,7 +2309,6 @@ struct ec_response_lightbar { struct lightbar_params_v0 get_params_v0; struct lightbar_params_v1 get_params_v1; - struct lightbar_params_v2_timing get_params_v2_timing; struct lightbar_params_v2_tap get_params_v2_tap; struct lightbar_params_v2_oscillation get_params_v2_osc; @@ -2380,7 +2373,7 @@ enum lightbar_command { LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31, LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32, LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33, - LIGHTBAR_NUM_CMDS + LIGHTBAR_NUM_CMDS, }; /*****************************************************************************/ @@ -2407,12 +2400,12 @@ enum ec_led_id { /* LED to indicate sysrq debug mode. */ EC_LED_ID_SYSRQ_DEBUG_LED, - EC_LED_ID_COUNT + EC_LED_ID_COUNT, }; /* LED control flags */ #define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */ -#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ +#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */ enum ec_led_colors { EC_LED_COLOR_RED = 0, @@ -2422,12 +2415,12 @@ enum ec_led_colors { EC_LED_COLOR_WHITE, EC_LED_COLOR_AMBER, - EC_LED_COLOR_COUNT + EC_LED_COLOR_COUNT, }; struct ec_params_led_control { - uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ + uint8_t led_id; /* Which LED to control */ + uint8_t flags; /* Control flags */ uint8_t brightness[EC_LED_COLOR_COUNT]; } __ec_align1; @@ -2455,30 +2448,30 @@ struct ec_response_led_control { #define EC_CMD_VBOOT_HASH 0x002A struct ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ - uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ + uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ } __ec_align4; struct ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ } __ec_align4; enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ - EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ - EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ - EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ + EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ + EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ }; enum ec_vboot_hash_type { @@ -2496,9 +2489,9 @@ enum ec_vboot_hash_status { * If one of these is specified, the EC will automatically update offset and * size to the correct values for the specified image (RO or RW). */ -#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe -#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd -#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc +#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe +#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd +#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc /* * 'RW' is vague if there are multiple RW images; we mean the active one, @@ -2647,7 +2640,7 @@ enum motionsense_command { MOTIONSENSE_CMD_GET_ACTIVITY = 20, /* Number of motionsense sub-commands. */ - MOTIONSENSE_NUM_CMDS + MOTIONSENSE_NUM_CMDS, }; /* List of motion sensor types. */ @@ -2729,16 +2722,16 @@ struct ec_response_motion_sensor_data { uint8_t sensor_num; /* Each sensor is up to 3-axis. */ union { - int16_t data[3]; + int16_t data[3]; /* for sensors using unsigned data */ - uint16_t udata[3]; + uint16_t udata[3]; struct __ec_todo_packed { - uint16_t reserved; - uint32_t timestamp; + uint16_t reserved; + uint32_t timestamp; }; struct __ec_todo_unpacked { struct ec_response_activity_data activity_data; - int16_t add_info[2]; + int16_t add_info[2]; }; }; } __ec_todo_packed; @@ -2782,7 +2775,7 @@ enum motionsensor_activity { struct ec_motion_sense_activity { uint8_t sensor_num; uint8_t activity; /* one of enum motionsensor_activity */ - uint8_t enable; /* 1: enable, 0: disable */ + uint8_t enable; /* 1: enable, 0: disable */ uint8_t reserved; uint16_t parameters[3]; /* activity dependent parameters */ } __ec_todo_unpacked; @@ -2950,7 +2943,6 @@ struct ec_params_motion_sense { uint16_t scale[3]; } sensor_scale; - /* Used for MOTIONSENSE_CMD_FIFO_INFO */ /* (no params) */ @@ -3034,7 +3026,7 @@ struct ec_params_motion_sense { */ struct __ec_todo_unpacked { uint8_t sensor_num; - uint8_t activity; /* enum motionsensor_activity */ + uint8_t activity; /* enum motionsensor_activity */ } get_activity; }; } __ec_todo_packed; @@ -3135,19 +3127,19 @@ struct ec_response_motion_sense { /* Current value of the parameter queried. */ int32_t ret; } ec_rate, sensor_odr, sensor_range, kb_wake_angle, - fifo_int_enable, spoof; + fifo_int_enable, spoof; /* * Used for MOTIONSENSE_CMD_SENSOR_OFFSET, * PERFORM_CALIB. */ - struct __ec_todo_unpacked { + struct __ec_todo_unpacked { int16_t temp; int16_t offset[3]; } sensor_offset, perform_calib; /* Used for MOTIONSENSE_CMD_SENSOR_SCALE */ - struct __ec_todo_unpacked { + struct __ec_todo_unpacked { int16_t temp; uint16_t scale[3]; } sensor_scale; @@ -3238,20 +3230,20 @@ enum usb_charge_mode { /* Set USB port to CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE. */ USB_CHARGE_MODE_DEFAULT, - USB_CHARGE_MODE_COUNT + USB_CHARGE_MODE_COUNT, }; enum usb_suspend_charge { /* Enable charging in suspend */ USB_ALLOW_SUSPEND_CHARGE, /* Disable charging in suspend */ - USB_DISALLOW_SUSPEND_CHARGE + USB_DISALLOW_SUSPEND_CHARGE, }; struct ec_params_usb_charge_set_mode { uint8_t usb_port_id; - uint8_t mode:7; /* enum usb_charge_mode */ - uint8_t inhibit_charge:1; /* enum usb_suspend_charge */ + uint8_t mode : 7; /* enum usb_charge_mode */ + uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */ } __ec_align1; /*****************************************************************************/ @@ -3278,16 +3270,16 @@ struct ec_response_pstore_info { #define EC_CMD_PSTORE_READ 0x0041 struct ec_params_pstore_read { - uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ } __ec_align4; /* Write persistent storage */ #define EC_CMD_PSTORE_WRITE 0x0042 struct ec_params_pstore_write { - uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ + uint32_t offset; /* Byte offset to write */ + uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; } __ec_align4; @@ -3430,14 +3422,13 @@ struct ec_response_thermal_get_threshold { uint16_t value; } __ec_align2; - /* The version 1 structs are visible. */ enum ec_temp_thresholds { EC_TEMP_THRESH_WARN = 0, EC_TEMP_THRESH_HIGH, EC_TEMP_THRESH_HALT, - EC_TEMP_THRESH_COUNT + EC_TEMP_THRESH_COUNT, }; /* @@ -3465,8 +3456,8 @@ enum ec_temp_thresholds { struct ec_thermal_config { uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */ uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */ - uint32_t temp_fan_off; /* no active cooling needed */ - uint32_t temp_fan_max; /* max active cooling needed */ + uint32_t temp_fan_off; /* no active cooling needed */ + uint32_t temp_fan_max; /* max active cooling needed */ } __ec_align4; /* Version 1 - get config for one sensor. */ @@ -3546,7 +3537,6 @@ struct ec_params_tmp006_set_calibration_v1 { float val[0]; } __ec_align4; - /* Read raw TMP006 data */ #define EC_CMD_TMP006_GET_RAW 0x0055 @@ -3555,8 +3545,8 @@ struct ec_params_tmp006_get_raw { } __ec_align1; struct ec_response_tmp006_get_raw { - int32_t t; /* In 1/100 K */ - int32_t v; /* In nV */ + int32_t t; /* In 1/100 K */ + int32_t v; /* In nV */ } __ec_align4; /*****************************************************************************/ @@ -3656,17 +3646,17 @@ enum keyboard_id { /* flags */ enum mkbp_config_flags { - EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ + EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */ }; enum mkbp_config_valid { - EC_MKBP_VALID_SCAN_PERIOD = BIT(0), - EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), - EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), - EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), - EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), - EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), - EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), + EC_MKBP_VALID_SCAN_PERIOD = BIT(0), + EC_MKBP_VALID_POLL_TIMEOUT = BIT(1), + EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3), + EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4), + EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5), + EC_MKBP_VALID_DEBOUNCE_UP = BIT(6), + EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7), }; /* @@ -3676,10 +3666,10 @@ enum mkbp_config_valid { * ec_{params/response}_mkbp_get_config. */ struct ec_mkbp_config { - uint32_t valid_mask; /* valid fields */ - uint8_t flags; /* some flags (enum mkbp_config_flags) */ - uint8_t valid_flags; /* which flags are valid */ - uint16_t scan_period_us; /* period between start of scans */ + uint32_t valid_mask; /* valid fields */ + uint8_t flags; /* some flags (enum mkbp_config_flags) */ + uint8_t valid_flags; /* which flags are valid */ + uint16_t scan_period_us; /* period between start of scans */ /* revert to interrupt mode after no activity for this long */ uint32_t poll_timeout_us; /* @@ -3690,8 +3680,8 @@ struct ec_mkbp_config { uint16_t min_post_scan_delay_us; /* delay between setting up output and waiting for it to settle */ uint16_t output_settle_us; - uint16_t debounce_down_us; /* time for debounce on key down */ - uint16_t debounce_up_us; /* time for debounce on key up */ + uint16_t debounce_down_us; /* time for debounce on key down */ + uint16_t debounce_up_us; /* time for debounce on key up */ /* maximum depth to allow for fifo (0 = no keyscan output) */ uint8_t fifo_max_depth; } __ec_align_size1; @@ -3708,11 +3698,11 @@ struct ec_response_mkbp_get_config { #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066 enum ec_keyscan_seq_cmd { - EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ - EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ - EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ - EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ - EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ + EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */ + EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */ + EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */ + EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */ + EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */ }; enum ec_collect_flags { @@ -3720,19 +3710,19 @@ enum ec_collect_flags { * Indicates this scan was processed by the EC. Due to timing, some * scans may be skipped. */ - EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), + EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0), }; struct ec_collect_item { - uint8_t flags; /* some flags (enum ec_collect_flags) */ + uint8_t flags; /* some flags (enum ec_collect_flags) */ } __ec_align1; struct ec_params_keyscan_seq_ctrl { - uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ + uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */ union { struct __ec_align1 { - uint8_t active; /* still active */ - uint8_t num_items; /* number of items */ + uint8_t active; /* still active */ + uint8_t num_items; /* number of items */ /* Current item being presented */ uint8_t cur_item; } status; @@ -3742,11 +3732,11 @@ struct ec_params_keyscan_seq_ctrl { * start of the sequence. */ uint32_t time_us; - uint8_t scan[0]; /* keyscan data */ + uint8_t scan[0]; /* keyscan data */ } add; struct __ec_align1 { - uint8_t start_item; /* First item to return */ - uint8_t num_items; /* Number of items to return */ + uint8_t start_item; /* First item to return */ + uint8_t num_items; /* Number of items to return */ } collect; }; } __ec_todo_packed; @@ -3754,7 +3744,7 @@ struct ec_params_keyscan_seq_ctrl { struct ec_result_keyscan_seq_ctrl { union { struct __ec_todo_unpacked { - uint8_t num_items; /* Number of items */ + uint8_t num_items; /* Number of items */ /* Data for each item */ struct ec_collect_item item[0]; } collect; @@ -3897,58 +3887,57 @@ struct ec_response_get_next_event_v1 { /* Bit indices for buttons and switches.*/ /* Buttons */ -#define EC_MKBP_POWER_BUTTON 0 -#define EC_MKBP_VOL_UP 1 -#define EC_MKBP_VOL_DOWN 2 -#define EC_MKBP_RECOVERY 3 +#define EC_MKBP_POWER_BUTTON 0 +#define EC_MKBP_VOL_UP 1 +#define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 /* Switches */ -#define EC_MKBP_LID_OPEN 0 -#define EC_MKBP_TABLET_MODE 1 -#define EC_MKBP_BASE_ATTACHED 2 -#define EC_MKBP_FRONT_PROXIMITY 3 +#define EC_MKBP_LID_OPEN 0 +#define EC_MKBP_TABLET_MODE 1 +#define EC_MKBP_BASE_ATTACHED 2 +#define EC_MKBP_FRONT_PROXIMITY 3 /* Run keyboard factory test scanning */ #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068 struct ec_response_keyboard_factory_test { - uint16_t shorted; /* Keyboard pins are shorted */ + uint16_t shorted; /* Keyboard pins are shorted */ } __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ -#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) -#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F) #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 -#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \ - >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) +#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ + (((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) #define EC_MKBP_FP_MATCH_IDX_OFFSET 12 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 -#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \ - >> EC_MKBP_FP_MATCH_IDX_OFFSET) -#define EC_MKBP_FP_ENROLL BIT(27) -#define EC_MKBP_FP_MATCH BIT(28) -#define EC_MKBP_FP_FINGER_DOWN BIT(29) -#define EC_MKBP_FP_FINGER_UP BIT(30) -#define EC_MKBP_FP_IMAGE_READY BIT(31) +#define EC_MKBP_FP_MATCH_IDX(fpe) \ + (((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) +#define EC_MKBP_FP_ENROLL BIT(27) +#define EC_MKBP_FP_MATCH BIT(28) +#define EC_MKBP_FP_FINGER_DOWN BIT(29) +#define EC_MKBP_FP_FINGER_UP BIT(30) +#define EC_MKBP_FP_IMAGE_READY BIT(31) /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */ -#define EC_MKBP_FP_ERR_ENROLL_OK 0 -#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 -#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 -#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 -#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 +#define EC_MKBP_FP_ERR_ENROLL_OK 0 +#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1 +#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2 +#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3 +#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5 /* Can be used to detect if image was usable for enrollment or not. */ -#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 +#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1 /* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */ -#define EC_MKBP_FP_ERR_MATCH_NO 0 -#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 -#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 -#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 -#define EC_MKBP_FP_ERR_MATCH_YES 1 -#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 +#define EC_MKBP_FP_ERR_MATCH_NO 0 +#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 +#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 +#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 +#define EC_MKBP_FP_ERR_MATCH_YES 1 +#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5 - #define EC_CMD_MKBP_WAKE_MASK 0x0069 enum ec_mkbp_event_mask_action { /* Retrieve the value of a wake mask. */ @@ -4026,7 +4015,6 @@ struct ec_response_temp_sensor_get_info { /*****************************************************************************/ /* Host event commands */ - /* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */ /* * Host event mask params and response structures, shared by all of the host @@ -4041,17 +4029,17 @@ struct ec_response_host_event_mask { } __ec_align4; /* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x0087 -#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 -#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 +#define EC_CMD_HOST_EVENT_GET_B 0x0087 +#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088 +#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D /* These all use ec_params_host_event_mask */ -#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A -#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B -#define EC_CMD_HOST_EVENT_CLEAR 0x008C +#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A +#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B +#define EC_CMD_HOST_EVENT_CLEAR 0x008C #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E -#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F +#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F /* * Unified host event programming interface - Should be used by newer versions @@ -4063,7 +4051,6 @@ struct ec_response_host_event_mask { */ struct ec_params_host_event { - /* Action requested by host - one of enum ec_host_event_action. */ uint8_t action; @@ -4086,7 +4073,6 @@ struct ec_params_host_event { */ struct ec_response_host_event { - /* Mask value in case of get operation */ uint64_t value; } __ec_align4; @@ -4135,7 +4121,7 @@ enum ec_host_event_mask_type { EC_HOST_EVENT_LAZY_WAKE_MASK_S5, }; -#define EC_CMD_HOST_EVENT 0x00A4 +#define EC_CMD_HOST_EVENT 0x00A4 /*****************************************************************************/ /* Switch commands */ @@ -4291,10 +4277,11 @@ enum ec_charge_control_mode { CHARGE_CONTROL_COUNT, }; -#define EC_CHARGE_MODE_TEXT { \ - [CHARGE_CONTROL_NORMAL] = "NORMAL", \ - [CHARGE_CONTROL_IDLE] = "IDLE", \ - [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ +#define EC_CHARGE_MODE_TEXT \ + { \ + [CHARGE_CONTROL_NORMAL] = "NORMAL", \ + [CHARGE_CONTROL_IDLE] = "IDLE", \ + [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \ } enum ec_charge_control_cmd { @@ -4303,10 +4290,10 @@ enum ec_charge_control_cmd { }; struct ec_params_charge_control { - uint32_t mode; /* enum charge_control_mode */ + uint32_t mode; /* enum charge_control_mode */ /* Below are the fields added in V2. */ - uint8_t cmd; /* enum ec_charge_control_cmd. */ + uint8_t cmd; /* enum ec_charge_control_cmd. */ uint8_t reserved; /* * Lower and upper thresholds for battery sustainer. This struct isn't @@ -4317,15 +4304,15 @@ struct ec_params_charge_control { * lower=-1, upper=-1. */ struct { - int8_t lower; /* Display SoC in percentage. */ - int8_t upper; /* Display SoC in percentage. */ + int8_t lower; /* Display SoC in percentage. */ + int8_t upper; /* Display SoC in percentage. */ } sustain_soc; } __ec_align4; /* Added in v2 */ struct ec_response_charge_control { - uint32_t mode; /* enum charge_control_mode */ - struct { /* Battery sustainer thresholds */ + uint32_t mode; /* enum charge_control_mode */ + struct { /* Battery sustainer thresholds */ int8_t lower; int8_t upper; } sustain_soc; @@ -4353,7 +4340,7 @@ struct ec_response_charge_control { enum ec_console_read_subcmd { CONSOLE_READ_NEXT = 0, - CONSOLE_READ_RECENT + CONSOLE_READ_RECENT, }; struct ec_params_console_read_v1 { @@ -4371,7 +4358,7 @@ struct ec_params_console_read_v1 { */ #define EC_CMD_BATTERY_CUT_OFF 0x0099 -#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) +#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0) struct ec_params_battery_cutoff { uint8_t flags; @@ -4393,8 +4380,8 @@ struct ec_params_usb_mux { /* LDOs / FETs control. */ enum ec_ldo_state { - EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ - EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ + EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */ + EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */ }; /* @@ -4495,33 +4482,33 @@ struct ec_response_power_info_v1 { #define EC_CMD_I2C_PASSTHRU 0x009E /* Read data; if not present, message is a write */ -#define EC_I2C_FLAG_READ BIT(15) +#define EC_I2C_FLAG_READ BIT(15) /* Mask for address */ -#define EC_I2C_ADDR_MASK 0x3ff +#define EC_I2C_ADDR_MASK 0x3ff -#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ -#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ +#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */ +#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */ /* Any error */ -#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) +#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT) struct ec_params_i2c_passthru_msg { - uint16_t addr_flags; /* I2C peripheral address and flags */ - uint16_t len; /* Number of bytes to read or write */ + uint16_t addr_flags; /* I2C peripheral address and flags */ + uint16_t len; /* Number of bytes to read or write */ } __ec_align2; struct ec_params_i2c_passthru { - uint8_t port; /* I2C port number */ - uint8_t num_msgs; /* Number of messages */ + uint8_t port; /* I2C port number */ + uint8_t num_msgs; /* Number of messages */ struct ec_params_i2c_passthru_msg msg[]; /* Data to write for all messages is concatenated here */ } __ec_align2; struct ec_response_i2c_passthru { - uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ - uint8_t num_msgs; /* Number of messages processed */ - uint8_t data[]; /* Data read by messages concatenated here */ + uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */ + uint8_t num_msgs; /* Number of messages processed */ + uint8_t data[]; /* Data read by messages concatenated here */ } __ec_align1; /*****************************************************************************/ @@ -4531,16 +4518,16 @@ struct ec_response_i2c_passthru { /* Reasons to start hang detection timer */ /* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS BIT(0) +#define EC_HANG_START_ON_POWER_PRESS BIT(0) /* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE BIT(1) +#define EC_HANG_START_ON_LID_CLOSE BIT(1) - /* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN BIT(2) +/* Lid opened */ +#define EC_HANG_START_ON_LID_OPEN BIT(2) /* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME BIT(3) +#define EC_HANG_START_ON_RESUME BIT(3) /* Reasons to cancel hang detection */ @@ -4548,10 +4535,10 @@ struct ec_response_i2c_passthru { #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) /* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) +#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) /* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND BIT(10) +#define EC_HANG_STOP_ON_SUSPEND BIT(10) /* * If this flag is set, all the other fields are ignored, and the hang detect @@ -4559,14 +4546,14 @@ struct ec_response_i2c_passthru { * without reconfiguring any of the other hang detect settings. Note that * you must previously have configured the timeouts. */ -#define EC_HANG_START_NOW BIT(30) +#define EC_HANG_START_NOW BIT(30) /* * If this flag is set, all the other fields are ignored (including * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer * without reconfiguring any of the other hang detect settings. */ -#define EC_HANG_STOP_NOW BIT(31) +#define EC_HANG_STOP_NOW BIT(31) struct ec_params_hang_detect { /* Flags; see EC_HANG_* */ @@ -4593,7 +4580,7 @@ enum charge_state_command { CHARGE_STATE_CMD_GET_STATE, CHARGE_STATE_CMD_GET_PARAM, CHARGE_STATE_CMD_SET_PARAM, - CHARGE_STATE_NUM_CMDS + CHARGE_STATE_NUM_CMDS, }; /* @@ -4601,16 +4588,27 @@ enum charge_state_command { * params, which are handled by the particular implementations. */ enum charge_state_params { - CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */ - CS_PARAM_CHG_CURRENT, /* charger current limit */ - CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */ - CS_PARAM_CHG_STATUS, /* charger-specific status */ - CS_PARAM_CHG_OPTION, /* charger-specific options */ - CS_PARAM_LIMIT_POWER, /* - * Check if power is limited due to - * low battery and / or a weak external - * charger. READ ONLY. - */ + /* charger voltage limit */ + CS_PARAM_CHG_VOLTAGE, + + /* charger current limit */ + CS_PARAM_CHG_CURRENT, + + /* charger input current limit */ + CS_PARAM_CHG_INPUT_CURRENT, + + /* charger-specific status */ + CS_PARAM_CHG_STATUS, + + /* charger-specific options */ + CS_PARAM_CHG_OPTION, + + /* + * Check if power is limited due to low battery and / or a + * weak external charger. READ ONLY. + */ + CS_PARAM_LIMIT_POWER, + /* How many so far? */ CS_NUM_BASE_PARAMS, @@ -4633,20 +4631,20 @@ enum charge_state_params { }; struct ec_params_charge_state { - uint8_t cmd; /* enum charge_state_command */ + uint8_t cmd; /* enum charge_state_command */ union { /* get_state has no args */ struct __ec_todo_unpacked { - uint32_t param; /* enum charge_state_param */ + uint32_t param; /* enum charge_state_param */ } get_param; struct __ec_todo_unpacked { - uint32_t param; /* param to set */ - uint32_t value; /* value to set */ + uint32_t param; /* param to set */ + uint32_t value; /* value to set */ } set_param; }; - uint8_t chgnum; /* Version 1 supports chgnum */ + uint8_t chgnum; /* Version 1 supports chgnum */ } __ec_todo_packed; struct ec_response_charge_state { @@ -4667,7 +4665,6 @@ struct ec_response_charge_state { }; } __ec_align4; - /* * Set maximum battery charging current. */ @@ -4771,10 +4768,10 @@ struct ec_response_hibernation_delay { #define EC_CMD_HOST_SLEEP_EVENT 0x00A9 enum host_sleep_event { - HOST_SLEEP_EVENT_S3_SUSPEND = 1, - HOST_SLEEP_EVENT_S3_RESUME = 2, + HOST_SLEEP_EVENT_S3_SUSPEND = 1, + HOST_SLEEP_EVENT_S3_RESUME = 2, HOST_SLEEP_EVENT_S0IX_SUSPEND = 3, - HOST_SLEEP_EVENT_S0IX_RESUME = 4, + HOST_SLEEP_EVENT_S0IX_RESUME = 4, /* S3 suspend with additional enabled wake sources */ HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5, }; @@ -4875,13 +4872,13 @@ struct ec_response_device_event { /* Smart battery pass-through */ /* Get / Set 16-bit smart battery registers */ -#define EC_CMD_SB_READ_WORD 0x00B0 -#define EC_CMD_SB_WRITE_WORD 0x00B1 +#define EC_CMD_SB_READ_WORD 0x00B0 +#define EC_CMD_SB_WRITE_WORD 0x00B1 /* Get / Set string smart battery parameters * formatted as SMBUS "block". */ -#define EC_CMD_SB_READ_BLOCK 0x00B2 +#define EC_CMD_SB_READ_BLOCK 0x00B2 #define EC_CMD_SB_WRITE_BLOCK 0x00B3 struct ec_params_sb_rd { @@ -4939,14 +4936,14 @@ struct ec_response_battery_vendor_param { #define EC_CMD_SB_FW_UPDATE 0x00B5 enum ec_sb_fw_update_subcmd { - EC_SB_FW_UPDATE_PREPARE = 0x0, - EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ - EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ - EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ - EC_SB_FW_UPDATE_END = 0x4, - EC_SB_FW_UPDATE_STATUS = 0x5, - EC_SB_FW_UPDATE_PROTECT = 0x6, - EC_SB_FW_UPDATE_MAX = 0x7, + EC_SB_FW_UPDATE_PREPARE = 0x0, + EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */ + EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */ + EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */ + EC_SB_FW_UPDATE_END = 0x4, + EC_SB_FW_UPDATE_STATUS = 0x5, + EC_SB_FW_UPDATE_PROTECT = 0x6, + EC_SB_FW_UPDATE_MAX = 0x7, }; #define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32 @@ -4954,8 +4951,8 @@ enum ec_sb_fw_update_subcmd { #define SB_FW_UPDATE_CMD_INFO_SIZE 8 struct ec_sb_fw_update_header { - uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ - uint16_t fw_id; /* firmware id */ + uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */ + uint16_t fw_id; /* firmware id */ } __ec_align4; struct ec_params_sb_fw_update { @@ -4971,7 +4968,7 @@ struct ec_params_sb_fw_update { /* EC_SB_FW_UPDATE_WRITE = 0x3 */ struct __ec_align4 { - uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; + uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE]; } write; }; } __ec_align4; @@ -5004,9 +5001,9 @@ struct ec_params_entering_mode { int vboot_mode; } __ec_align4; -#define VBOOT_MODE_NORMAL 0 +#define VBOOT_MODE_NORMAL 0 #define VBOOT_MODE_DEVELOPER 1 -#define VBOOT_MODE_RECOVERY 2 +#define VBOOT_MODE_RECOVERY 2 /*****************************************************************************/ /* @@ -5023,14 +5020,13 @@ enum ec_i2c_passthru_protect_subcmd { struct ec_params_i2c_passthru_protect { uint8_t subcmd; - uint8_t port; /* I2C port number */ + uint8_t port; /* I2C port number */ } __ec_align1; struct ec_response_i2c_passthru_protect { - uint8_t status; /* Status flags (0: unlocked, 1: locked) */ + uint8_t status; /* Status flags (0: unlocked, 1: locked) */ } __ec_align1; - /*****************************************************************************/ /* * HDMI CEC commands @@ -5100,9 +5096,9 @@ enum cec_command { /* Events from CEC to AP */ enum mkbp_cec_event { /* Outgoing message was acknowledged by a follower */ - EC_MKBP_CEC_SEND_OK = BIT(0), + EC_MKBP_CEC_SEND_OK = BIT(0), /* Outgoing message was not acknowledged */ - EC_MKBP_CEC_SEND_FAILED = BIT(1), + EC_MKBP_CEC_SEND_FAILED = BIT(1), }; /*****************************************************************************/ @@ -5151,10 +5147,8 @@ struct __ec_align4 ec_param_ec_codec { uint8_t reserved[3]; union { - struct ec_param_ec_codec_get_shm_addr - get_shm_addr_param; - struct ec_param_ec_codec_set_shm_addr - set_shm_addr_param; + struct ec_param_ec_codec_get_shm_addr get_shm_addr_param; + struct ec_param_ec_codec_set_shm_addr set_shm_addr_param; }; }; @@ -5209,10 +5203,8 @@ struct __ec_align4 ec_param_ec_codec_dmic { uint8_t reserved[3]; union { - struct ec_param_ec_codec_dmic_set_gain_idx - set_gain_idx_param; - struct ec_param_ec_codec_dmic_get_gain_idx - get_gain_idx_param; + struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param; + struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param; }; }; @@ -5279,11 +5271,9 @@ struct __ec_align4 ec_param_ec_codec_i2s_rx { union { struct ec_param_ec_codec_i2s_rx_set_sample_depth - set_sample_depth_param; - struct ec_param_ec_codec_i2s_rx_set_daifmt - set_daifmt_param; - struct ec_param_ec_codec_i2s_rx_set_bclk - set_bclk_param; + set_sample_depth_param; + struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param; + struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param; }; }; @@ -5328,10 +5318,8 @@ struct __ec_align4 ec_param_ec_codec_wov { uint8_t reserved[3]; union { - struct ec_param_ec_codec_wov_set_lang - set_lang_param; - struct ec_param_ec_codec_wov_set_lang_shm - set_lang_shm_param; + struct ec_param_ec_codec_wov_set_lang set_lang_param; + struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param; }; }; @@ -5362,8 +5350,8 @@ enum ec_pse_subcmd { }; struct __ec_align1 ec_params_pse { - uint8_t cmd; /* enum ec_pse_subcmd */ - uint8_t port; /* PSE port */ + uint8_t cmd; /* enum ec_pse_subcmd */ + uint8_t port; /* PSE port */ }; enum ec_pse_status { @@ -5373,7 +5361,7 @@ enum ec_pse_status { }; struct __ec_align1 ec_response_pse_status { - uint8_t status; /* enum ec_pse_status */ + uint8_t status; /* enum ec_pse_status */ }; /*****************************************************************************/ @@ -5387,25 +5375,25 @@ struct __ec_align1 ec_response_pse_status { /* Command */ enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */ /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ - EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ - EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ + EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */ EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */ - EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ + EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */ }; /* Flags for ec_params_reboot_ec.reboot_flags */ -#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ -#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ -#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ +#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */ +#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */ +#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */ struct ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ } __ec_align1; /* @@ -5433,7 +5421,7 @@ struct ec_params_reboot_ec { * * Use EC_CMD_REBOOT_EC to reboot the EC more politely. */ -#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ +#define EC_CMD_REBOOT 0x00D1 /* Think "die" */ /* * Resend last response (not supported on LPC). @@ -5468,50 +5456,66 @@ struct ec_params_reboot_ec { #define EC_VER_PD_EXCHANGE_STATUS 2 enum pd_charge_state { - PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */ - PD_CHARGE_NONE, /* No charging allowed */ - PD_CHARGE_5V, /* 5V charging only */ - PD_CHARGE_MAX /* Charge at max voltage */ + /* Don't change charge state */ + PD_CHARGE_NO_CHANGE = 0, + + /* No charging allowed */ + PD_CHARGE_NONE, + + /* 5V charging only */ + PD_CHARGE_5V, + + /* Charge at max voltage */ + PD_CHARGE_MAX, }; /* Status of EC being sent to PD */ -#define EC_STATUS_HIBERNATING BIT(0) +#define EC_STATUS_HIBERNATING BIT(0) struct ec_params_pd_status { - uint8_t status; /* EC status */ - int8_t batt_soc; /* battery state of charge */ - uint8_t charge_state; /* charging state (from enum pd_charge_state) */ + /* EC status */ + uint8_t status; + + /* battery state of charge */ + int8_t batt_soc; + + /* charging state (from enum pd_charge_state) */ + uint8_t charge_state; } __ec_align1; /* Status of PD being sent back to EC */ -#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ -#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ +#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */ +#define PD_STATUS_IN_RW BIT(1) /* Running RW image */ #define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */ -#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ -#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ -#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ -#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ -#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \ - PD_STATUS_TCPC_ALERT_1 | \ - PD_STATUS_HOST_EVENT) +#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */ +#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */ +#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */ +#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */ +#define PD_STATUS_EC_INT_ACTIVE \ + (PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT) struct ec_response_pd_status { - uint32_t curr_lim_ma; /* input current limit */ - uint16_t status; /* PD MCU status */ - int8_t active_charge_port; /* active charging port */ + /* input current limit */ + uint32_t curr_lim_ma; + + /* PD MCU status */ + uint16_t status; + + /* active charging port */ + int8_t active_charge_port; } __ec_align_size1; /* AP to PD MCU host event status command, cleared on read */ #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104 /* PD MCU host event status bits */ -#define PD_EVENT_UPDATE_DEVICE BIT(0) -#define PD_EVENT_POWER_CHANGE BIT(1) -#define PD_EVENT_IDENTITY_RECEIVED BIT(2) -#define PD_EVENT_DATA_SWAP BIT(3) -#define PD_EVENT_TYPEC BIT(4) +#define PD_EVENT_UPDATE_DEVICE BIT(0) +#define PD_EVENT_POWER_CHANGE BIT(1) +#define PD_EVENT_IDENTITY_RECEIVED BIT(2) +#define PD_EVENT_DATA_SWAP BIT(3) +#define PD_EVENT_TYPEC BIT(4) struct ec_response_host_event_status { - uint32_t status; /* PD MCU host event status */ + uint32_t status; /* PD MCU host event status */ } __ec_align4; /* @@ -5530,7 +5534,7 @@ enum usb_pd_control_role { USB_PD_CTRL_ROLE_FORCE_SINK = 3, USB_PD_CTRL_ROLE_FORCE_SOURCE = 4, USB_PD_CTRL_ROLE_FREEZE = 5, - USB_PD_CTRL_ROLE_COUNT + USB_PD_CTRL_ROLE_COUNT, }; enum usb_pd_control_mux { @@ -5540,7 +5544,7 @@ enum usb_pd_control_mux { USB_PD_CTRL_MUX_DP = 3, USB_PD_CTRL_MUX_DOCK = 4, USB_PD_CTRL_MUX_AUTO = 5, - USB_PD_CTRL_MUX_COUNT + USB_PD_CTRL_MUX_COUNT, }; enum usb_pd_control_swap { @@ -5548,7 +5552,7 @@ enum usb_pd_control_swap { USB_PD_CTRL_SWAP_DATA = 1, USB_PD_CTRL_SWAP_POWER = 2, USB_PD_CTRL_SWAP_VCONN = 3, - USB_PD_CTRL_SWAP_COUNT + USB_PD_CTRL_SWAP_COUNT, }; struct ec_params_usb_pd_control { @@ -5558,17 +5562,18 @@ struct ec_params_usb_pd_control { uint8_t swap; } __ec_align1; -#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ -#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ +#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */ +#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */ #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */ -#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ -#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ -#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ -#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ -#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ -#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ -#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */ +#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */ +#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */ +#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */ +#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */ +#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */ +/* Partner unconstrained power */ +#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) struct ec_response_usb_pd_control { uint8_t enabled; @@ -5586,39 +5591,39 @@ struct ec_response_usb_pd_control_v1 { /* Possible port partner connections based on CC line states */ enum pd_cc_states { - PD_CC_NONE = 0, /* No port partner attached */ + PD_CC_NONE = 0, /* No port partner attached */ /* From DFP perspective */ - PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ - PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ - PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ - PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ + PD_CC_UFP_NONE = 1, /* No UFP accessory connected */ + PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */ + PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */ + PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */ /* From UFP perspective */ - PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ - PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ + PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */ + PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */ }; /* Active/Passive Cable */ -#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0) /* Optical/Non-optical cable */ -#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1) /* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */ -#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2) /* Active Link Uni-Direction */ -#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; uint8_t polarity; char state[32]; - uint8_t cc_state; /* enum pd_cc_states representing cc state */ - uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ - uint8_t reserved; /* Reserved for future use */ - uint8_t control_flags; /* USB_PD_CTRL_*flags */ - uint8_t cable_speed; /* TBT_SS_* cable speed */ - uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ + uint8_t cc_state; /* enum pd_cc_states representing cc state */ + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */ + uint8_t reserved; /* Reserved for future use */ + uint8_t control_flags; /* USB_PD_CTRL_*flags */ + uint8_t cable_speed; /* TBT_SS_* cable speed */ + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */ } __ec_align1; #define EC_CMD_USB_PD_PORTS 0x0102 @@ -5673,7 +5678,6 @@ struct ec_response_usb_pd_power_info { uint32_t max_power; } __ec_align4; - /* * This command will return the number of USB PD charge port + the number * of dedicated port present. @@ -5707,7 +5711,10 @@ struct ec_params_usb_pd_fw_update { uint16_t dev_id; uint8_t cmd; uint8_t port; - uint32_t size; /* Size to write in bytes */ + + /* Size to write in bytes */ + uint32_t size; + /* Followed by data to write */ } __ec_align4; @@ -5718,12 +5725,16 @@ struct ec_params_usb_pd_fw_update { struct ec_params_usb_pd_rw_hash_entry { uint16_t dev_id; uint8_t dev_rw_hash[PD_RW_HASH_SIZE]; - uint8_t reserved; /* - * For alignment of current_image - * TODO(rspangler) but it's not aligned! - * Should have been reserved[2]. - */ - uint32_t current_image; /* One of ec_image */ + + /* + * Reserved for alignment of current_image + * TODO(rspangler) but it's not aligned! + * Should have been reserved[2]. + */ + uint8_t reserved; + + /* One of ec_image */ + uint32_t current_image; } __ec_align1; /* Read USB-PD Accessory info */ @@ -5736,8 +5747,8 @@ struct ec_params_usb_pd_info_request { /* Read USB-PD Device discovery info */ #define EC_CMD_USB_PD_DISCOVERY 0x0113 struct ec_params_usb_pd_discovery_entry { - uint16_t vid; /* USB-IF VID */ - uint16_t pid; /* USB-IF PID */ + uint16_t vid; /* USB-IF VID */ + uint16_t pid; /* USB-IF PID */ uint8_t ptype; /* product type (hub,periph,cable,ama) */ } __ec_align_size1; @@ -5764,43 +5775,43 @@ struct ec_params_charge_port_override { struct ec_response_pd_log { uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type : see PD_EVENT_xx below */ - uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ + uint8_t type; /* event type : see PD_EVENT_xx below */ + uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ } __ec_align4; /* The timestamp is the microsecond counter shifted to get about a ms. */ #define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ -#define PD_LOG_SIZE_MASK 0x1f -#define PD_LOG_PORT_MASK 0xe0 -#define PD_LOG_PORT_SHIFT 5 -#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \ - ((size) & PD_LOG_SIZE_MASK)) +#define PD_LOG_SIZE_MASK 0x1f +#define PD_LOG_PORT_MASK 0xe0 +#define PD_LOG_PORT_SHIFT 5 +#define PD_LOG_PORT_SIZE(port, size) \ + (((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK)) #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) +#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK) /* PD event log : entry types */ /* PD MCU events */ -#define PD_EVENT_MCU_BASE 0x00 -#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0) -#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1) +#define PD_EVENT_MCU_BASE 0x00 +#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0) +#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1) /* Reserved for custom board event */ -#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2) +#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2) /* PD generic accessory events */ -#define PD_EVENT_ACC_BASE 0x20 -#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0) -#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1) +#define PD_EVENT_ACC_BASE 0x20 +#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0) +#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1) /* PD power supply events */ -#define PD_EVENT_PS_BASE 0x40 -#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0) +#define PD_EVENT_PS_BASE 0x40 +#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0) /* PD video dongles events */ -#define PD_EVENT_VIDEO_BASE 0x60 -#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0) -#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1) +#define PD_EVENT_VIDEO_BASE 0x60 +#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0) +#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1) /* Returned in the "type" field, when there is no entry available */ -#define PD_EVENT_NO_ENTRY 0xff +#define PD_EVENT_NO_ENTRY 0xff /* * PD_EVENT_MCU_CHARGE event definition : @@ -5808,24 +5819,24 @@ struct ec_response_pd_log { * the data field contains the port state flags as defined below : */ /* Port partner is a dual role device */ -#define CHARGE_FLAGS_DUAL_ROLE BIT(15) +#define CHARGE_FLAGS_DUAL_ROLE BIT(15) /* Port is the pending override port */ -#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) +#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14) /* Port is the override port */ -#define CHARGE_FLAGS_OVERRIDE BIT(13) +#define CHARGE_FLAGS_OVERRIDE BIT(13) /* Charger type */ -#define CHARGE_FLAGS_TYPE_SHIFT 3 -#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) +#define CHARGE_FLAGS_TYPE_SHIFT 3 +#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT) /* Power delivery role */ -#define CHARGE_FLAGS_ROLE_MASK (7 << 0) +#define CHARGE_FLAGS_ROLE_MASK (7 << 0) /* * PD_EVENT_PS_FAULT data field flags definition : */ -#define PS_FAULT_OCP 1 -#define PS_FAULT_FAST_OCP 2 -#define PS_FAULT_OVP 3 -#define PS_FAULT_DISCH 4 +#define PS_FAULT_OCP 1 +#define PS_FAULT_FAST_OCP 2 +#define PS_FAULT_OVP 3 +#define PS_FAULT_DISCH 4 /* * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info". @@ -5851,12 +5862,12 @@ struct mcdp_info { #define EC_CMD_USB_PD_GET_AMODE 0x0116 struct ec_params_usb_pd_get_mode_request { uint16_t svid_idx; /* SVID index to get */ - uint8_t port; /* port */ + uint8_t port; /* port */ } __ec_align_size1; struct ec_params_usb_pd_get_mode_response { - uint16_t svid; /* SVID */ - uint16_t opos; /* Object Position */ + uint16_t svid; /* SVID */ + uint16_t opos; /* Object Position */ uint32_t vdo[6]; /* Mode VDOs */ } __ec_align4; @@ -5870,10 +5881,10 @@ enum pd_mode_cmd { }; struct ec_params_usb_pd_set_mode_request { - uint32_t cmd; /* enum pd_mode_cmd */ + uint32_t cmd; /* enum pd_mode_cmd */ uint16_t svid; /* SVID to set */ - uint8_t opos; /* Object Position */ - uint8_t port; /* port */ + uint8_t opos; /* Object Position */ + uint8_t port; /* port */ } __ec_align4; /* Ask the PD MCU to record a log of a requested type */ @@ -5884,20 +5895,19 @@ struct ec_params_pd_write_log_entry { uint8_t port; /* port#, or 0 for events unrelated to a given port */ } __ec_align1; - /* Control USB-PD chip */ #define EC_CMD_PD_CONTROL 0x0119 enum ec_pd_control_cmd { - PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ - PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ - PD_RESET, /* Force reset the PD chip */ - PD_CONTROL_DISABLE, /* Disable further calls to this command */ - PD_CHIP_ON, /* Power on the PD chip */ + PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */ + PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */ + PD_RESET, /* Force reset the PD chip */ + PD_CONTROL_DISABLE, /* Disable further calls to this command */ + PD_CHIP_ON, /* Power on the PD chip */ }; struct ec_params_pd_control { - uint8_t chip; /* chip id */ + uint8_t chip; /* chip id */ uint8_t subcmd; } __ec_align1; @@ -5909,29 +5919,29 @@ struct ec_params_usb_pd_mux_info { } __ec_align1; /* Flags representing mux state */ -#define USB_PD_MUX_NONE 0 /* Open switch */ -#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ -#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ -#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ -#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ -#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ -#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ -#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ -#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ +#define USB_PD_MUX_NONE 0 /* Open switch */ +#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */ +#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */ +#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */ +#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */ +#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */ +#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */ +#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */ +#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */ #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */ -#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ +#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */ /* USB-C Dock connected */ -#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) +#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ } __ec_align1; -#define EC_CMD_PD_CHIP_INFO 0x011B +#define EC_CMD_PD_CHIP_INFO 0x011B struct ec_params_pd_chip_info { - uint8_t port; /* USB-C port number */ + uint8_t port; /* USB-C port number */ /* * Fetch the live chip info or hard-coded + cached chip info * 0: hardcoded value for VID/PID, cached value for FW version @@ -5965,18 +5975,18 @@ struct ec_response_pd_chip_info_v1 { } __ec_align2; /* Run RW signature verification and get status */ -#define EC_CMD_RWSIG_CHECK_STATUS 0x011C +#define EC_CMD_RWSIG_CHECK_STATUS 0x011C struct ec_response_rwsig_check_status { uint32_t status; } __ec_align4; /* For controlling RWSIG task */ -#define EC_CMD_RWSIG_ACTION 0x011D +#define EC_CMD_RWSIG_ACTION 0x011D enum rwsig_action { - RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ - RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ + RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */ + RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */ }; struct ec_params_rwsig_action { @@ -5984,10 +5994,10 @@ struct ec_params_rwsig_action { } __ec_align4; /* Run verification on a slot */ -#define EC_CMD_EFS_VERIFY 0x011E +#define EC_CMD_EFS_VERIFY 0x011E struct ec_params_efs_verify { - uint8_t region; /* enum ec_flash_region */ + uint8_t region; /* enum ec_flash_region */ } __ec_align1; /* @@ -5995,25 +6005,25 @@ struct ec_params_efs_verify { * type. Integers return a uint32. Strings return a string, using the response * size to determine how big it is. */ -#define EC_CMD_GET_CROS_BOARD_INFO 0x011F +#define EC_CMD_GET_CROS_BOARD_INFO 0x011F /* * Write info into Cros Board Info on EEPROM. Write fails if the board has * hardware write-protect enabled. */ -#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 +#define EC_CMD_SET_CROS_BOARD_INFO 0x0120 enum cbi_data_tag { CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */ - CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ - CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ + CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */ + CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */ CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */ - CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ - CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ - CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ - CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ + CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */ + CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */ + CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */ + CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */ /* Second Source Factory Cache */ - CBI_TAG_SSFC = 8, /* uint32_t bit field */ - CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_SSFC = 8, /* uint32_t bit field */ + CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ CBI_TAG_COUNT, }; @@ -6023,11 +6033,11 @@ enum cbi_data_tag { * RELOAD: Invalidate cache and read data from EEPROM. Useful to verify * write was successful without reboot. */ -#define CBI_GET_RELOAD BIT(0) +#define CBI_GET_RELOAD BIT(0) struct ec_params_get_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_GET_* */ + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_GET_* */ } __ec_align4; /* @@ -6038,14 +6048,14 @@ struct ec_params_get_cbi { * INIT: Need to be set when creating a new CBI from scratch. All fields * will be initialized to zero first. */ -#define CBI_SET_NO_SYNC BIT(0) -#define CBI_SET_INIT BIT(1) +#define CBI_SET_NO_SYNC BIT(0) +#define CBI_SET_INIT BIT(1) struct ec_params_set_cbi { - uint32_t tag; /* enum cbi_data_tag */ - uint32_t flag; /* CBI_SET_* */ - uint32_t size; /* Data size */ - uint8_t data[]; /* For string and raw data */ + uint32_t tag; /* enum cbi_data_tag */ + uint32_t flag; /* CBI_SET_* */ + uint32_t size; /* Data size */ + uint8_t data[]; /* For string and raw data */ } __ec_align1; /* @@ -6054,33 +6064,32 @@ struct ec_params_set_cbi { #define EC_CMD_GET_UPTIME_INFO 0x0121 /* EC reset causes */ -#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ -#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ -#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ -#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ -#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ -#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ -#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ -#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ -#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ -#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ -#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ -#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ -#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ -#define EC_RESET_FLAG_PRESERVED BIT(13) /* Some reset flags preserved from - * previous boot - */ -#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ -#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ -#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ -#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ -#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */ -#define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This - * enables PD in RO for Chromebox. - */ -#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ -#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ -#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ +#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */ +#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */ +#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */ +#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */ +#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */ +#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */ +#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */ +#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */ +#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */ +#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */ +#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */ +#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */ +#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */ +/* Some reset flags preserved from previous boot */ +#define EC_RESET_FLAG_PRESERVED BIT(13) +#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */ +#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */ +#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */ +#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */ +/* AP experienced a watchdog reset */ +#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) +/* Do not select RW in EFS. This enables PD in RO for Chromebox. */ +#define EC_RESET_FLAG_STAY_IN_RO BIT(19) +#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */ +#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */ +#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */ /* * Reason codes used by the AP after a shutdown to figure out why it was reset @@ -6148,7 +6157,6 @@ enum chipset_shutdown_reason { CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */ }; - struct ec_response_uptime_info { /* * Number of milliseconds since the last EC boot. Sysjump resets @@ -6197,7 +6205,7 @@ struct ec_response_uptime_info { * Depending on the chip, the operation may take a long time (e.g. to erase * flash), so the commands are asynchronous. */ -#define EC_CMD_ADD_ENTROPY 0x0122 +#define EC_CMD_ADD_ENTROPY 0x0122 enum add_entropy_action { /* Add entropy to the current secret. */ @@ -6219,7 +6227,7 @@ struct ec_params_rollback_add_entropy { /* * Perform a single read of a given ADC channel. */ -#define EC_CMD_ADC_READ 0x0123 +#define EC_CMD_ADC_READ 0x0123 struct ec_params_adc_read { uint8_t adc_channel; @@ -6232,7 +6240,7 @@ struct ec_response_adc_read { /* * Read back rollback info */ -#define EC_CMD_ROLLBACK_INFO 0x0124 +#define EC_CMD_ROLLBACK_INFO 0x0124 struct ec_response_rollback_info { int32_t id; /* Incrementing number to indicate which region to use. */ @@ -6240,7 +6248,6 @@ struct ec_response_rollback_info { int32_t rw_rollback_version; } __ec_align4; - /* Issue AP reset */ #define EC_CMD_AP_RESET 0x0125 @@ -6269,23 +6276,22 @@ enum ec_bus_type { }; struct ec_i2c_info { - uint16_t port; /* Physical port for device */ - uint16_t addr_flags; /* 7-bit (or 10-bit) address */ + uint16_t port; /* Physical port for device */ + uint16_t addr_flags; /* 7-bit (or 10-bit) address */ }; struct ec_params_locate_chip { - uint8_t type; /* enum ec_chip_type */ - uint8_t index; /* Specifies one instance of chip type */ + uint8_t type; /* enum ec_chip_type */ + uint8_t index; /* Specifies one instance of chip type */ /* Used for type specific parameters in future */ union { uint16_t reserved; }; } __ec_align2; - struct ec_response_locate_chip { - uint8_t bus_type; /* enum ec_bus_type */ - uint8_t reserved; /* Aligning the following union to 2 bytes */ + uint8_t bus_type; /* enum ec_bus_type */ + uint8_t reserved; /* Aligning the following union to 2 bytes */ union { struct ec_i2c_info i2c_info; }; @@ -6356,27 +6362,27 @@ enum ec_pd_port_location { * left side, while BACK_LEFT means the leftmost port on the back of the * device. */ - EC_PD_PORT_LOCATION_LEFT = 1, - EC_PD_PORT_LOCATION_RIGHT = 2, - EC_PD_PORT_LOCATION_BACK = 3, - EC_PD_PORT_LOCATION_FRONT = 4, - EC_PD_PORT_LOCATION_LEFT_FRONT = 5, - EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, - EC_PD_PORT_LOCATION_RIGHT_BACK = 8, - EC_PD_PORT_LOCATION_BACK_LEFT = 9, - EC_PD_PORT_LOCATION_BACK_RIGHT = 10, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, }; struct ec_params_get_pd_port_caps { - uint8_t port; /* Which port to interrogate */ + uint8_t port; /* Which port to interrogate */ } __ec_align1; struct ec_response_get_pd_port_caps { - uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ - uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ - uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ - uint8_t pd_port_location; /* enum ec_pd_port_location */ + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ } __ec_align1; /*****************************************************************************/ @@ -6393,27 +6399,27 @@ struct ec_response_get_pd_port_caps { struct ec_params_button { /* Button mask aligned to enum keyboard_button_type */ - uint32_t btn_mask; + uint32_t btn_mask; /* Duration in milliseconds button needs to be pressed */ - uint32_t press_ms; + uint32_t press_ms; } __ec_align1; enum keyboard_button_type { - KEYBOARD_BUTTON_POWER = 0, + KEYBOARD_BUTTON_POWER = 0, KEYBOARD_BUTTON_VOLUME_DOWN = 1, - KEYBOARD_BUTTON_VOLUME_UP = 2, - KEYBOARD_BUTTON_RECOVERY = 3, - KEYBOARD_BUTTON_CAPSENSE_1 = 4, - KEYBOARD_BUTTON_CAPSENSE_2 = 5, - KEYBOARD_BUTTON_CAPSENSE_3 = 6, - KEYBOARD_BUTTON_CAPSENSE_4 = 7, - KEYBOARD_BUTTON_CAPSENSE_5 = 8, - KEYBOARD_BUTTON_CAPSENSE_6 = 9, - KEYBOARD_BUTTON_CAPSENSE_7 = 10, - KEYBOARD_BUTTON_CAPSENSE_8 = 11, + KEYBOARD_BUTTON_VOLUME_UP = 2, + KEYBOARD_BUTTON_RECOVERY = 3, + KEYBOARD_BUTTON_CAPSENSE_1 = 4, + KEYBOARD_BUTTON_CAPSENSE_2 = 5, + KEYBOARD_BUTTON_CAPSENSE_3 = 6, + KEYBOARD_BUTTON_CAPSENSE_4 = 7, + KEYBOARD_BUTTON_CAPSENSE_5 = 8, + KEYBOARD_BUTTON_CAPSENSE_6 = 9, + KEYBOARD_BUTTON_CAPSENSE_7 = 10, + KEYBOARD_BUTTON_CAPSENSE_8 = 11, - KEYBOARD_BUTTON_COUNT + KEYBOARD_BUTTON_COUNT, }; /*****************************************************************************/ @@ -6467,15 +6473,15 @@ enum action_key { * action keys. This is possible for e.g. if the keyboard has a * dedicated Fn key. */ -#define KEYBD_CAP_FUNCTION_KEYS BIT(0) +#define KEYBD_CAP_FUNCTION_KEYS BIT(0) /* * Whether the keyboard has a dedicated numeric keyboard. */ -#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) +#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1) /* * Whether the keyboard has a screenlock key. */ -#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) +#define KEYBD_CAP_SCRNLOCK_KEY BIT(2) struct ec_response_keybd_config { /* @@ -6502,12 +6508,12 @@ struct ec_response_keybd_config { */ #define EC_CMD_SMART_DISCHARGE 0x012B -#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) +#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0) /* Discharge rates when the system is in cutoff or hibernation. */ struct discharge_rate { - uint16_t cutoff; /* Discharge rate (uA) in cutoff */ - uint16_t hibern; /* Discharge rate (uA) in hibernation */ + uint16_t cutoff; /* Discharge rate (uA) in cutoff */ + uint16_t hibern; /* Discharge rate (uA) in hibernation */ }; struct smart_discharge_zone { @@ -6518,7 +6524,7 @@ struct smart_discharge_zone { }; struct ec_params_smart_discharge { - uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ + uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */ /* * Desired hours for the battery to survive before reaching 0%. Set to * zero to disable smart discharging. That is, the system hibernates as @@ -6643,13 +6649,13 @@ struct ec_params_typec_discovery { struct svid_mode_info { uint16_t svid; - uint16_t mode_count; /* Number of modes partner sent */ + uint16_t mode_count; /* Number of modes partner sent */ uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ }; struct ec_response_typec_discovery { - uint8_t identity_count; /* Number of identity VDOs partner sent */ - uint8_t svid_count; /* Number of SVIDs partner sent */ + uint8_t identity_count; /* Number of identity VDOs partner sent */ + uint8_t svid_count; /* Number of SVIDs partner sent */ uint16_t reserved; uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */ struct svid_mode_info svids[0]; @@ -6680,13 +6686,16 @@ enum typec_tbt_ufp_reply { }; struct typec_usb_mux_set { - uint8_t mux_index; /* Index of the mux to set in the chain */ - uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */ + /* Index of the mux to set in the chain */ + uint8_t mux_index; + + /* USB_PD_MUX_*-encoded USB mux state to set */ + uint8_t mux_flags; } __ec_align1; struct ec_params_typec_control { uint8_t port; - uint8_t command; /* enum typec_control_command */ + uint8_t command; /* enum typec_control_command */ uint16_t reserved; /* @@ -6728,7 +6737,7 @@ struct ec_params_typec_control { */ enum pd_power_role { PD_ROLE_SINK = 0, - PD_ROLE_SOURCE = 1 + PD_ROLE_SOURCE = 1, }; /* @@ -6775,23 +6784,23 @@ enum tcpc_cc_polarity { * that this will give a hint that other places need to be * adjusted. */ - POLARITY_COUNT + POLARITY_COUNT, }; -#define MODE_DP_PIN_A BIT(0) -#define MODE_DP_PIN_B BIT(1) -#define MODE_DP_PIN_C BIT(2) -#define MODE_DP_PIN_D BIT(3) -#define MODE_DP_PIN_E BIT(4) -#define MODE_DP_PIN_F BIT(5) -#define MODE_DP_PIN_ALL GENMASK(5, 0) +#define MODE_DP_PIN_A BIT(0) +#define MODE_DP_PIN_B BIT(1) +#define MODE_DP_PIN_C BIT(2) +#define MODE_DP_PIN_D BIT(3) +#define MODE_DP_PIN_E BIT(4) +#define MODE_DP_PIN_F BIT(5) +#define MODE_DP_PIN_ALL GENMASK(5, 0) -#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) -#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) -#define PD_STATUS_EVENT_HARD_RESET BIT(2) -#define PD_STATUS_EVENT_DISCONNECTED BIT(3) -#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) -#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) +#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) +#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +#define PD_STATUS_EVENT_HARD_RESET BIT(2) +#define PD_STATUS_EVENT_DISCONNECTED BIT(3) +#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4) +#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5) /* * Encode and decode for BCD revision response @@ -6800,9 +6809,9 @@ enum tcpc_cc_polarity { * Specification Revision from the PD header, which currently only maps to PD * 1.0-3.0 with the major revision being one greater than the binary value. */ -#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) -#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) -#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) +#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12) +#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF) +#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF) /* * Decode helpers for Source and Sink Capability PDOs @@ -6810,11 +6819,11 @@ enum tcpc_cc_polarity { * Note: The Power Delivery Specification should be considered the ultimate * source of truth on the decoding of these PDOs */ -#define PDO_TYPE_FIXED (0 << 30) -#define PDO_TYPE_BATTERY (1 << 30) -#define PDO_TYPE_VARIABLE (2 << 30) +#define PDO_TYPE_FIXED (0 << 30) +#define PDO_TYPE_BATTERY (1 << 30) +#define PDO_TYPE_VARIABLE (2 << 30) #define PDO_TYPE_AUGMENTED (3 << 30) -#define PDO_TYPE_MASK (3 << 30) +#define PDO_TYPE_MASK (3 << 30) /* * From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0 @@ -6829,13 +6838,13 @@ enum tcpc_cc_polarity { * <19:10> : Voltage in 50mV Units * <9:0> : Maximum Current in 10mA units */ -#define PDO_FIXED_DUAL_ROLE BIT(29) -#define PDO_FIXED_UNCONSTRAINED BIT(27) -#define PDO_FIXED_COMM_CAP BIT(26) -#define PDO_FIXED_DATA_SWAP BIT(25) +#define PDO_FIXED_DUAL_ROLE BIT(29) +#define PDO_FIXED_UNCONSTRAINED BIT(27) +#define PDO_FIXED_COMM_CAP BIT(26) +#define PDO_FIXED_DATA_SWAP BIT(25) #define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */ -#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) +#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10) /* * From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0 @@ -6845,9 +6854,9 @@ enum tcpc_cc_polarity { * <19:10> : Minimum Voltage in 50mV units * <9:0> : Maximum Allowable Power in 250mW units */ -#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) -#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) +#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250) /* * From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0 @@ -6857,9 +6866,9 @@ enum tcpc_cc_polarity { * <19:10> : Minimum Voltage in 50mV units * <9:0> : Operational Current in 10mA units */ -#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) -#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) -#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) +#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50) +#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50) +#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10) /* * From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0 @@ -6877,33 +6886,33 @@ enum tcpc_cc_polarity { * <7> : Reserved * <6:0> : Maximum Current in 50mA increments */ -#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) -#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) -#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) +#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100) +#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100) +#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50) struct ec_params_typec_status { uint8_t port; } __ec_align1; struct ec_response_typec_status { - uint8_t pd_enabled; /* PD communication enabled - bool */ - uint8_t dev_connected; /* Device connected - bool */ - uint8_t sop_connected; /* Device is SOP PD capable - bool */ - uint8_t source_cap_count; /* Number of Source Cap PDOs */ + uint8_t pd_enabled; /* PD communication enabled - bool */ + uint8_t dev_connected; /* Device connected - bool */ + uint8_t sop_connected; /* Device is SOP PD capable - bool */ + uint8_t source_cap_count; /* Number of Source Cap PDOs */ - uint8_t power_role; /* enum pd_power_role */ - uint8_t data_role; /* enum pd_data_role */ - uint8_t vconn_role; /* enum pd_vconn_role */ - uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ + uint8_t power_role; /* enum pd_power_role */ + uint8_t data_role; /* enum pd_data_role */ + uint8_t vconn_role; /* enum pd_vconn_role */ + uint8_t sink_cap_count; /* Number of Sink Cap PDOs */ - uint8_t polarity; /* enum tcpc_cc_polarity */ - uint8_t cc_state; /* enum pd_cc_states */ - uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ - uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ + uint8_t polarity; /* enum tcpc_cc_polarity */ + uint8_t cc_state; /* enum pd_cc_states */ + uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */ + uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */ - char tc_state[32]; /* TC state name */ + char tc_state[32]; /* TC state name */ - uint32_t events; /* PD_STATUS_EVENT bitmask */ + uint32_t events; /* PD_STATUS_EVENT bitmask */ /* * BCD PD revisions for partners @@ -6918,9 +6927,9 @@ struct ec_response_typec_status { uint16_t sop_revision; uint16_t sop_prime_revision; - uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */ - uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ + uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */ } __ec_align1; /** @@ -6944,8 +6953,8 @@ struct ec_params_pchg { } __ec_align1; struct ec_response_pchg { - uint32_t error; /* enum pchg_error */ - uint8_t state; /* enum pchg_state state */ + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ uint8_t battery_percentage; uint8_t unused0; uint8_t unused1; @@ -6955,8 +6964,8 @@ struct ec_response_pchg { } __ec_align4; struct ec_response_pchg_v2 { - uint32_t error; /* enum pchg_error */ - uint8_t state; /* enum pchg_state state */ + uint32_t error; /* enum pchg_error */ + uint8_t state; /* enum pchg_state state */ uint8_t battery_percentage; uint8_t unused0; uint8_t unused1; @@ -6990,17 +6999,20 @@ enum pchg_state { PCHG_STATE_COUNT, }; -#define EC_PCHG_STATE_TEXT { \ - [PCHG_STATE_RESET] = "RESET", \ - [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ - [PCHG_STATE_ENABLED] = "ENABLED", \ - [PCHG_STATE_DETECTED] = "DETECTED", \ - [PCHG_STATE_CHARGING] = "CHARGING", \ - [PCHG_STATE_FULL] = "FULL", \ - [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ - [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ - [PCHG_STATE_CONNECTED] = "CONNECTED", \ +/* clang-format off */ +#define EC_PCHG_STATE_TEXT \ + { \ + [PCHG_STATE_RESET] = "RESET", \ + [PCHG_STATE_INITIALIZED] = "INITIALIZED", \ + [PCHG_STATE_ENABLED] = "ENABLED", \ + [PCHG_STATE_DETECTED] = "DETECTED", \ + [PCHG_STATE_CHARGING] = "CHARGING", \ + [PCHG_STATE_FULL] = "FULL", \ + [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \ + [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \ + [PCHG_STATE_CONNECTED] = "CONNECTED", \ } +/* clang-format on */ /** * Update firmware of peripheral chip @@ -7008,19 +7020,18 @@ enum pchg_state { #define EC_CMD_PCHG_UPDATE 0x0136 /* Port number is encoded in bit[28:31]. */ -#define EC_MKBP_PCHG_PORT_SHIFT 28 +#define EC_MKBP_PCHG_PORT_SHIFT 28 /* Utility macros for converting MKBP event <-> port number. */ -#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) -#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) +#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) +#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) /* Utility macro for extracting event bits. */ -#define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \ - & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0)) +#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) -#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) -#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) -#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) -#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) -#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) +#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) +#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) +#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2) +#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3) +#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4) enum ec_pchg_update_cmd { /* Reset chip to normal mode. */ @@ -7055,28 +7066,29 @@ struct ec_params_pchg_update { uint8_t data[]; } __ec_align4; -BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT - < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8)); +BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT < + BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8)); struct ec_response_pchg_update { /* Block size */ uint32_t block_size; } __ec_align4; - #define EC_CMD_DISPLAY_SOC 0x0137 struct ec_response_display_soc { - int16_t display_soc; /* Display charge in 10ths of a % (1000=100.0%) */ - int16_t full_factor; /* Full factor in 10ths of a % (1000=100.0%) */ - int16_t shutdown_soc; /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + /* Display charge in 10ths of a % (1000=100.0%) */ + int16_t display_soc; + /* Full factor in 10ths of a % (1000=100.0%) */ + int16_t full_factor; + /* Shutdown SoC in 10ths of a % (1000=100.0%) */ + int16_t shutdown_soc; } __ec_align2; - #define EC_CMD_SET_BASE_STATE 0x0138 struct ec_params_set_base_state { - uint8_t cmd; /* enum ec_set_base_state_cmd */ + uint8_t cmd; /* enum ec_set_base_state_cmd */ } __ec_align1; enum ec_set_base_state_cmd { @@ -7097,8 +7109,8 @@ enum ec_i2c_control_command { #define EC_I2C_CONTROL_SPEED_UNKNOWN 0 struct ec_params_i2c_control { - uint8_t port; /* I2C port number */ - uint8_t cmd; /* enum ec_i2c_control_command */ + uint8_t port; /* I2C port number */ + uint8_t cmd; /* enum ec_i2c_control_command */ union { uint16_t speed_khz; } cmd_params; @@ -7110,12 +7122,12 @@ struct ec_response_i2c_control { } cmd_response; } __ec_align_size1; -#define EC_CMD_RGBKBD_SET_COLOR 0x013A -#define EC_CMD_RGBKBD 0x013B +#define EC_CMD_RGBKBD_SET_COLOR 0x013A +#define EC_CMD_RGBKBD 0x013B -#define EC_RGBKBD_MAX_KEY_COUNT 128 -#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF -#define EC_RGBKBD_MAX_SCALE 0xFF +#define EC_RGBKBD_MAX_KEY_COUNT 128 +#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF +#define EC_RGBKBD_MAX_SCALE 0xFF enum rgbkbd_state { /* RGB keyboard is reset and not initialized. */ @@ -7153,10 +7165,10 @@ struct ec_rgbkbd_set_scale { }; struct ec_params_rgbkbd { - uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ + uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */ union { - struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ - uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ + struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */ + uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */ struct ec_rgbkbd_set_scale set_scale; }; } __ec_align1; @@ -7189,49 +7201,44 @@ struct ec_params_rgbkbd_set_color { #define EC_FP_FLAG_NOT_COMPLETE 0x1 struct ec_params_fp_passthru { - uint16_t len; /* Number of bytes to write then read */ - uint16_t flags; /* EC_FP_FLAG_xxx */ - uint8_t data[]; /* Data to send */ + uint16_t len; /* Number of bytes to write then read */ + uint16_t flags; /* EC_FP_FLAG_xxx */ + uint8_t data[]; /* Data to send */ } __ec_align2; /* Configure the Fingerprint MCU behavior */ #define EC_CMD_FP_MODE 0x0402 /* Put the sensor in its lowest power mode */ -#define FP_MODE_DEEPSLEEP BIT(0) +#define FP_MODE_DEEPSLEEP BIT(0) /* Wait to see a finger on the sensor */ -#define FP_MODE_FINGER_DOWN BIT(1) +#define FP_MODE_FINGER_DOWN BIT(1) /* Poll until the finger has left the sensor */ -#define FP_MODE_FINGER_UP BIT(2) +#define FP_MODE_FINGER_UP BIT(2) /* Capture the current finger image */ -#define FP_MODE_CAPTURE BIT(3) +#define FP_MODE_CAPTURE BIT(3) /* Finger enrollment session on-going */ #define FP_MODE_ENROLL_SESSION BIT(4) /* Enroll the current finger image */ -#define FP_MODE_ENROLL_IMAGE BIT(5) +#define FP_MODE_ENROLL_IMAGE BIT(5) /* Try to match the current finger image */ -#define FP_MODE_MATCH BIT(6) +#define FP_MODE_MATCH BIT(6) /* Reset and re-initialize the sensor. */ -#define FP_MODE_RESET_SENSOR BIT(7) +#define FP_MODE_RESET_SENSOR BIT(7) /* Sensor maintenance for dead pixels. */ #define FP_MODE_SENSOR_MAINTENANCE BIT(8) /* special value: don't change anything just read back current mode */ -#define FP_MODE_DONT_CHANGE BIT(31) - -#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \ - FP_MODE_FINGER_DOWN | \ - FP_MODE_FINGER_UP | \ - FP_MODE_CAPTURE | \ - FP_MODE_ENROLL_SESSION | \ - FP_MODE_ENROLL_IMAGE | \ - FP_MODE_MATCH | \ - FP_MODE_RESET_SENSOR | \ - FP_MODE_SENSOR_MAINTENANCE | \ - FP_MODE_DONT_CHANGE) +#define FP_MODE_DONT_CHANGE BIT(31) + +#define FP_VALID_MODES \ + (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ + FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \ + FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \ + FP_MODE_DONT_CHANGE) /* Capture types defined in bits [30..28] */ #define FP_MODE_CAPTURE_TYPE_SHIFT 28 -#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) +#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT) /** * enum fp_capture_type - Specifies the "mode" when capturing images. * @@ -7258,8 +7265,8 @@ enum fp_capture_type { FP_CAPTURE_TYPE_MAX, }; /* Extracts the capture type from the sensor 'mode' word */ -#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \ - >> FP_MODE_CAPTURE_TYPE_SHIFT) +#define FP_CAPTURE_TYPE(mode) \ + (((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ @@ -7273,15 +7280,15 @@ struct ec_response_fp_mode { #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) +#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF) /* Unknown number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ -#define FP_ERROR_NO_IRQ BIT(12) +#define FP_ERROR_NO_IRQ BIT(12) /* SPI communication error */ -#define FP_ERROR_SPI_COMM BIT(13) +#define FP_ERROR_SPI_COMM BIT(13) /* Invalid sensor Hardware ID */ -#define FP_ERROR_BAD_HWID BIT(14) +#define FP_ERROR_BAD_HWID BIT(14) /* Sensor initialization failed */ #define FP_ERROR_INIT_FAIL BIT(15) @@ -7314,8 +7321,8 @@ struct ec_response_fp_info { uint16_t bpp; uint16_t errors; /* see FP_ERROR_ flags above */ /* Template/finger current information */ - uint32_t template_size; /* max template size in bytes */ - uint16_t template_max; /* maximum number of fingers/templates */ + uint32_t template_size; /* max template size in bytes */ + uint16_t template_max; /* maximum number of fingers/templates */ uint16_t template_valid; /* number of valid fingers/templates */ uint32_t template_dirty; /* bitmap of templates with MCU side changes */ uint32_t template_version; /* version of the template format */ @@ -7325,13 +7332,13 @@ struct ec_response_fp_info { #define EC_CMD_FP_FRAME 0x0404 /* constants defining the 'offset' field which also contains the frame index */ -#define FP_FRAME_INDEX_SHIFT 28 +#define FP_FRAME_INDEX_SHIFT 28 /* Frame buffer where the captured image is stored */ -#define FP_FRAME_INDEX_RAW_IMAGE 0 +#define FP_FRAME_INDEX_RAW_IMAGE 0 /* First frame buffer holding a template */ -#define FP_FRAME_INDEX_TEMPLATE 1 +#define FP_FRAME_INDEX_TEMPLATE 1 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT) -#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF +#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF /* Version of the format of the encrypted templates. */ #define FP_TEMPLATE_FORMAT_VERSION 4 @@ -7398,14 +7405,14 @@ enum fp_context_action { /* Version 1 of the command is "asynchronous". */ struct ec_params_fp_context_v1 { - uint8_t action; /**< enum fp_context_action */ - uint8_t reserved[3]; /**< padding for alignment */ + uint8_t action; /**< enum fp_context_action */ + uint8_t reserved[3]; /**< padding for alignment */ uint32_t userid[FP_CONTEXT_USERID_WORDS]; } __ec_align4; #define EC_CMD_FP_STATS 0x0407 -#define FPSTATS_CAPTURE_INV BIT(0) +#define FPSTATS_CAPTURE_INV BIT(0) #define FPSTATS_MATCHING_INV BIT(1) struct ec_response_fp_stats { @@ -7675,14 +7682,14 @@ struct ec_params_usb_pd_mux_ack { * switch to the new names soon, as the old names may not be carried forward * forever. */ -#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE -#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 -#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE +#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE +#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 +#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* !__ACPI__ */ +#endif /* !__ACPI__ */ #ifdef __cplusplus } #endif -#endif /* __CROS_EC_EC_COMMANDS_H */ +#endif /* __CROS_EC_EC_COMMANDS_H */ -- cgit v1.2.1 From 819eebcdd1c07bdbbf1de9e501304922d0fa86bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:15 -0600 Subject: chip/stm32/usart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44d4b91b0f65bc617a87bfcdf5f2cbea4ea59d45 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729541 Reviewed-by: Jeremy Bettis --- chip/stm32/usart.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 7f8c55aaa6..c4f3f9bf74 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -45,7 +45,7 @@ void usart_init(struct usart_config const *config) cr2 = 0x0000; cr3 = 0x0000; #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) + defined(CHIP_FAMILY_STM32L4) if (config->flags & USART_CONFIG_FLAG_RX_INV) cr2 |= BIT(16); if (config->flags & USART_CONFIG_FLAG_TX_INV) @@ -87,9 +87,9 @@ void usart_shutdown(struct usart_config const *config) } void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz) + int frequency_hz) { - int div = DIV_ROUND_NEAREST(frequency_hz, baud); + int div = DIV_ROUND_NEAREST(frequency_hz, baud); intptr_t base = config->hw->base; if (div / 16 > 0) { @@ -110,7 +110,7 @@ void usart_set_baud_f0_l(struct usart_config const *config, int baud, } void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz) + int frequency_hz) { int div = DIV_ROUND_NEAREST(frequency_hz, baud); -- cgit v1.2.1 From 985379d26a6d4f56f3186fba8893230ad68c5197 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:21 -0600 Subject: driver/als_cm32183.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I104a07a8915497ac69eb8b328442a1f1d39b8479 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729901 Reviewed-by: Jeremy Bettis --- driver/als_cm32183.h | 68 ++++++++++++++++++++++++++-------------------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/driver/als_cm32183.h b/driver/als_cm32183.h index 57802e9f96..9de6c15a79 100644 --- a/driver/als_cm32183.h +++ b/driver/als_cm32183.h @@ -9,27 +9,27 @@ #define __CROS_EC_ALS_CM32183_H /* I2C interface */ -#define CM32183_I2C_ADDR 0x29 +#define CM32183_I2C_ADDR 0x29 /* CM32183 registers */ -#define CM32183_REG_CONFIGURE 0x00 +#define CM32183_REG_CONFIGURE 0x00 -#define CM32183_REG_CONFIGURE_CH_EN 0x0004 +#define CM32183_REG_CONFIGURE_CH_EN 0x0004 /* ALS Sensitivity_mode (BIT 12:11) */ -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11) -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2 -#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_MASK GENMASK(12, 11) +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_SHIFT 11 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1 0 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_2 1 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_8 2 +#define CM32183_REG_CONFIGURE_ALS_SENSITIVITY_1_DIV_4 3 /* * Gain mode * 0 Gain*1 * 1 Gain*2 (bit 10) */ -#define CM32183_REG_CONFIGURE_GAIN BIT(10) +#define CM32183_REG_CONFIGURE_GAIN BIT(10) /* * ALS integration time setting which represents how long @@ -40,12 +40,12 @@ * 0010 400ms * 0011 800ms */ -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6) -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2 -#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_MASK GENMASK(9, 6) +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SHIFT 6 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET100MS 0 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET200MS 1 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET400MS 2 +#define CM32183_REG_CONFIGURE_ALS_INTEGRATION_SET800MS 3 /* * ALS interrupt persistence setting.The interrupt pin is @@ -57,47 +57,47 @@ * 10 4 * 11 8 */ -#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4) -#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2 -#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3 +#define CM32183_REG_CONFIGURE_MEASUREMENT_MASK GENMASK(5, 4) +#define CM32183_REG_CONFIGURE_MEASUREMENT_SHIFT 4 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_1 0 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_2 1 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_4 2 +#define CM32183_REG_CONFIGURE_MEASUREMENT_CYCLE_8 3 /* * channel selection of interrupt (BIT 3) * 0 ALS CH interrupt * 1 White CH interrupt */ -#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3) +#define CM32183_REG_CONFIGURE_CHANNEL_SELECTION BIT(3) /* * Channel enable (BIT 2) * 0 ALS CH enable only * 1 ALS & White CH enable */ -#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2) +#define CM32183_REG_CONFIGURE_CHANNEL_ENABLE BIT(2) /* enable/disable interrupt function (BIT 1) */ -#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1) +#define CM32183_REG_CONFIGURE_INTERRUPT_ENABLE BIT(1) /* * how to power on and shutdown sensor (BIT 0) * 0 power on * 1 shutdown */ -#define CM32183_REG_CONFIGURE_POWER BIT(0) +#define CM32183_REG_CONFIGURE_POWER BIT(0) -#define CM32183_REG_INT_HSB 0x01 -#define CM32183_REG_INT_LSB 0x02 -#define CM32183_REG_ALS_RESULT 0x04 -#define CM32183_REG_WHITE_RESULT 0x05 +#define CM32183_REG_INT_HSB 0x01 +#define CM32183_REG_INT_LSB 0x02 +#define CM32183_REG_ALS_RESULT 0x04 +#define CM32183_REG_WHITE_RESULT 0x05 -#define CM32183_REG_TRIGGER 0x06 +#define CM32183_REG_TRIGGER 0x06 -#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15) -#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14) +#define CM32183_REG_TRIGGER_LOW_THRESHOLD BIT(15) +#define CM32183_REG_TRIGGER_HIGH_THRESHOLD BIT(14) extern const struct accelgyro_drv cm32183_drv; -#endif /* __CROS_EC_ALS_CM32183_H */ +#endif /* __CROS_EC_ALS_CM32183_H */ -- cgit v1.2.1 From f7b7686dd27752b306c25fe55bc7521367bcbde9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:17 -0600 Subject: driver/retimer/kb800x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2124d2f878932d7b3b3c20e628c5486c088f42a2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730054 Reviewed-by: Jeremy Bettis --- driver/retimer/kb800x.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/driver/retimer/kb800x.c b/driver/retimer/kb800x.c index 44bd166c14..18eda4f66a 100644 --- a/driver/retimer/kb800x.c +++ b/driver/retimer/kb800x.c @@ -79,14 +79,15 @@ static const uint8_t usb_ss_lane_to_eb[] = { [KB800X_TX0] = KB800X_EB4, /* Assign a phy TX to an elastic buffer */ static int kb800x_assign_tx_to_eb(const struct usb_mux *me, - enum kb800x_phy_lane phy_lane, enum kb800x_eb eb) + enum kb800x_phy_lane phy_lane, + enum kb800x_eb eb) { uint8_t field_value = 0; uint8_t regval; int rv; field_value = KB800X_PHY_IS_AB(phy_lane) ? tx_eb_to_field_ab[eb] : - tx_eb_to_field_cd[eb]; + tx_eb_to_field_cd[eb]; /* For lane1 of each PHY, shift by 3 bits */ field_value <<= 3 * KB800X_LANE_NUMBER_FROM_PHY(phy_lane); @@ -95,20 +96,19 @@ static int kb800x_assign_tx_to_eb(const struct usb_mux *me, if (rv) return rv; return kb800x_write(me, KB800X_REG_TXSEL_FROM_PHY(phy_lane), - regval | field_value); + regval | field_value); } - /* Assign a phy RX to an elastic buffer */ static int kb800x_assign_rx_to_eb(const struct usb_mux *me, - enum kb800x_phy_lane phy_lane, enum kb800x_eb eb) + enum kb800x_phy_lane phy_lane, + enum kb800x_eb eb) { uint16_t address = 0; uint8_t field_value = 0; uint8_t regval = 0; int rv; - field_value = rx_phy_lane_to_field[phy_lane]; address = rx_eb_to_address[eb]; @@ -246,13 +246,11 @@ static int kb800x_xbar_override(const struct usb_mux *me) for (i = KB800X_A0; i < KB800X_PHY_LANE_COUNT; ++i) { rv = kb800x_assign_lane( - me, i, - kb800x_control[me->usb_port].ss_lanes[i]); + me, i, kb800x_control[me->usb_port].ss_lanes[i]); if (rv) return rv; } - return kb800x_write(me, KB800X_REG_XBAR_OVR, - KB800X_XBAR_OVR_EN); + return kb800x_write(me, KB800X_REG_XBAR_OVR, KB800X_XBAR_OVR_EN); } #endif /* CONFIG_KB800X_CUSTOM_XBAR */ @@ -314,8 +312,8 @@ static int kb800x_dp_init(const struct usb_mux *me, mux_state_t mux_state) me, KB800X_REG_ORIENTATION, KB800X_ORIENTATION_DP_DFP | ((mux_state & USB_PD_MUX_POLARITY_INVERTED) ? - KB800X_ORIENTATION_POLARITY : - 0x0)); + KB800X_ORIENTATION_POLARITY : + 0x0)); } static int kb800x_usb3_init(const struct usb_mux *me, mux_state_t mux_state) @@ -356,7 +354,7 @@ static int kb800x_cio_init(const struct usb_mux *me, mux_state_t mux_state) if (!(mux_state & USB_PD_MUX_USB4_ENABLED)) { /* Special configuration only for legacy mode */ if (cable_type == IDH_PTYPE_ACABLE || - cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) { + cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) { /* Active cable */ if (cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) { orientation |= @@ -391,7 +389,7 @@ static int kb800x_set_state(const struct usb_mux *me, mux_state_t mux_state, return rv; /* Release memory map reset */ rv = kb800x_write(me, KB800X_REG_RESET, - KB800X_RESET_MASK & ~KB800X_RESET_MM); + KB800X_RESET_MASK & ~KB800X_RESET_MM); if (rv) return rv; -- cgit v1.2.1 From 18ed31336b95a30a2af8485cd827027c89444779 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:54 -0600 Subject: board/wheelie/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I612c288c12f00364ebd75a8de5d1689c8b31f10f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729128 Reviewed-by: Jeremy Bettis --- board/wheelie/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/wheelie/led.c b/board/wheelie/led.c index 9524a68a84..7d73bea2d0 100644 --- a/board/wheelie/led.c +++ b/board/wheelie/led.c @@ -20,13 +20,13 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * Board has one physical LED with red, green, and blue */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 100, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 50, 50, 0 }, - [EC_LED_COLOR_WHITE] = { 50, 50, 50 }, - [EC_LED_COLOR_AMBER] = { 70, 30, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 100, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 50, 50, 0 }, + [EC_LED_COLOR_WHITE] = { 50, 50, 50 }, + [EC_LED_COLOR_AMBER] = { 70, 30, 0 }, }; /* One logical LED with red, green, and blue channels. */ -- cgit v1.2.1 From 557ddfa26601994c5bd7046f01256c2af8c0237d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:19 -0600 Subject: chip/mt_scp/mt8192/intc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8b679b9ca888e11d6f7965488d35bbc90115056b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729353 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8192/intc.h | 180 +++++++++++++++++++++++----------------------- 1 file changed, 90 insertions(+), 90 deletions(-) diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h index 63eb1243b3..c2b8698434 100644 --- a/chip/mt_scp/mt8192/intc.h +++ b/chip/mt_scp/mt8192/intc.h @@ -7,120 +7,120 @@ #define __CROS_EC_INTC_H /* INTC */ -#define SCP_INTC_IRQ_POL0 0xef001f20 -#define SCP_INTC_IRQ_POL1 0x0800001d -#define SCP_INTC_IRQ_POL2 0x00000020 -#define SCP_INTC_GRP_LEN 3 -#define SCP_INTC_IRQ_COUNT 96 +#define SCP_INTC_IRQ_POL0 0xef001f20 +#define SCP_INTC_IRQ_POL1 0x0800001d +#define SCP_INTC_IRQ_POL2 0x00000020 +#define SCP_INTC_GRP_LEN 3 +#define SCP_INTC_IRQ_COUNT 96 /* IRQ numbers */ -#define SCP_IRQ_GIPC_IN0 0 -#define SCP_IRQ_GIPC_IN1 1 -#define SCP_IRQ_GIPC_IN2 2 -#define SCP_IRQ_GIPC_IN3 3 +#define SCP_IRQ_GIPC_IN0 0 +#define SCP_IRQ_GIPC_IN1 1 +#define SCP_IRQ_GIPC_IN2 2 +#define SCP_IRQ_GIPC_IN3 3 /* 4 */ -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_AP_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 +#define SCP_IRQ_SPM 4 +#define SCP_IRQ_AP_CIRQ 5 +#define SCP_IRQ_EINT 6 +#define SCP_IRQ_PMIC 7 /* 8 */ -#define SCP_IRQ_UART0_TX 8 -#define SCP_IRQ_UART1_TX 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1_0 11 +#define SCP_IRQ_UART0_TX 8 +#define SCP_IRQ_UART1_TX 9 +#define SCP_IRQ_I2C0 10 +#define SCP_IRQ_I2C1_0 11 /* 12 */ -#define SCP_IRQ_BUS_DBG_TRACKER 12 -#define SCP_IRQ_CLK_CTRL 13 -#define SCP_IRQ_VOW 14 -#define SCP_IRQ_TIMER0 15 +#define SCP_IRQ_BUS_DBG_TRACKER 12 +#define SCP_IRQ_CLK_CTRL 13 +#define SCP_IRQ_VOW 14 +#define SCP_IRQ_TIMER0 15 /* 16 */ -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 +#define SCP_IRQ_TIMER1 16 +#define SCP_IRQ_TIMER2 17 +#define SCP_IRQ_TIMER3 18 +#define SCP_IRQ_TIMER4 19 /* 20 */ -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_OS_TIMER 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 +#define SCP_IRQ_TIMER5 20 +#define SCP_IRQ_OS_TIMER 21 +#define SCP_IRQ_UART0_RX 22 +#define SCP_IRQ_UART1_RX 23 /* 24 */ -#define SCP_IRQ_GDMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD_DSP 26 -#define SCP_IRQ_ADSP 27 +#define SCP_IRQ_GDMA 24 +#define SCP_IRQ_AUDIO 25 +#define SCP_IRQ_MD_DSP 26 +#define SCP_IRQ_ADSP 27 /* 28 */ -#define SCP_IRQ_CPU_TICK 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 +#define SCP_IRQ_CPU_TICK 28 +#define SCP_IRQ_SPI0 29 +#define SCP_IRQ_SPI1 30 +#define SCP_IRQ_SPI2 31 /* 32 */ -#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 -#define SCP_IRQ_DBG 33 -#define SCP_IRQ_CCIF0 34 -#define SCP_IRQ_CCIF1 35 +#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 +#define SCP_IRQ_DBG 33 +#define SCP_IRQ_CCIF0 34 +#define SCP_IRQ_CCIF1 35 /* 36 */ -#define SCP_IRQ_CCIF2 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_USB0 38 -#define SCP_IRQ_USB1 39 +#define SCP_IRQ_CCIF2 36 +#define SCP_IRQ_WDT 37 +#define SCP_IRQ_USB0 38 +#define SCP_IRQ_USB1 39 /* 40 */ -#define SCP_IRQ_DPMAIF 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_CLK_CTRL_CORE 42 -#define SCP_IRQ_CLK_CTRL2_CORE 43 +#define SCP_IRQ_DPMAIF 40 +#define SCP_IRQ_INFRA 41 +#define SCP_IRQ_CLK_CTRL_CORE 42 +#define SCP_IRQ_CLK_CTRL2_CORE 43 /* 44 */ -#define SCP_IRQ_CLK_CTRL2 44 -#define SCP_IRQ_GIPC_IN4 45 /* HALT */ -#define SCP_IRQ_PERIBUS_TIMEOUT 46 -#define SCP_IRQ_INFRABUS_TIMEOUT 47 +#define SCP_IRQ_CLK_CTRL2 44 +#define SCP_IRQ_GIPC_IN4 45 /* HALT */ +#define SCP_IRQ_PERIBUS_TIMEOUT 46 +#define SCP_IRQ_INFRABUS_TIMEOUT 47 /* 48 */ -#define SCP_IRQ_MET0 48 -#define SCP_IRQ_MET1 49 -#define SCP_IRQ_MET2 50 -#define SCP_IRQ_MET3 51 +#define SCP_IRQ_MET0 48 +#define SCP_IRQ_MET1 49 +#define SCP_IRQ_MET2 50 +#define SCP_IRQ_MET3 51 /* 52 */ -#define SCP_IRQ_AP_WDT 52 -#define SCP_IRQ_L2TCM_SEC_VIO 53 -#define SCP_IRQ_CPU_TICK1 54 -#define SCP_IRQ_MAD_DATAIN 55 +#define SCP_IRQ_AP_WDT 52 +#define SCP_IRQ_L2TCM_SEC_VIO 53 +#define SCP_IRQ_CPU_TICK1 54 +#define SCP_IRQ_MAD_DATAIN 55 /* 56 */ -#define SCP_IRQ_I3C0_IBI_WAKE 56 -#define SCP_IRQ_I3C1_IBI_WAKE 57 -#define SCP_IRQ_I3C2_IBI_WAKE 58 -#define SCP_IRQ_APU_ENGINE 59 +#define SCP_IRQ_I3C0_IBI_WAKE 56 +#define SCP_IRQ_I3C1_IBI_WAKE 57 +#define SCP_IRQ_I3C2_IBI_WAKE 58 +#define SCP_IRQ_APU_ENGINE 59 /* 60 */ -#define SCP_IRQ_MBOX0 60 -#define SCP_IRQ_MBOX1 61 -#define SCP_IRQ_MBOX2 62 -#define SCP_IRQ_MBOX3 63 +#define SCP_IRQ_MBOX0 60 +#define SCP_IRQ_MBOX1 61 +#define SCP_IRQ_MBOX2 62 +#define SCP_IRQ_MBOX3 63 /* 64 */ -#define SCP_IRQ_MBOX4 64 -#define SCP_IRQ_SYS_CLK_REQ 65 -#define SCP_IRQ_BUS_REQ 66 -#define SCP_IRQ_APSRC_REQ 67 +#define SCP_IRQ_MBOX4 64 +#define SCP_IRQ_SYS_CLK_REQ 65 +#define SCP_IRQ_BUS_REQ 66 +#define SCP_IRQ_APSRC_REQ 67 /* 68 */ -#define SCP_IRQ_APU_MBOX 68 -#define SCP_IRQ_DEVAPC_SECURE_VIO 69 +#define SCP_IRQ_APU_MBOX 68 +#define SCP_IRQ_DEVAPC_SECURE_VIO 69 /* 72 */ /* 76 */ -#define SCP_IRQ_I2C1_2 78 -#define SCP_IRQ_I2C2 79 +#define SCP_IRQ_I2C1_2 78 +#define SCP_IRQ_I2C2 79 /* 80 */ -#define SCP_IRQ_AUD2AUDIODSP 80 -#define SCP_IRQ_AUD2AUDIODSP_2 81 -#define SCP_IRQ_CONN2ADSP_A2DPOL 82 -#define SCP_IRQ_CONN2ADSP_BTCVSD 83 +#define SCP_IRQ_AUD2AUDIODSP 80 +#define SCP_IRQ_AUD2AUDIODSP_2 81 +#define SCP_IRQ_CONN2ADSP_A2DPOL 82 +#define SCP_IRQ_CONN2ADSP_BTCVSD 83 /* 84 */ -#define SCP_IRQ_CONN2ADSP_BLEISO 84 -#define SCP_IRQ_PCIE2ADSP 85 -#define SCP_IRQ_APU2ADSP_ENGINE 86 -#define SCP_IRQ_APU2ADSP_MBOX 87 +#define SCP_IRQ_CONN2ADSP_BLEISO 84 +#define SCP_IRQ_PCIE2ADSP 85 +#define SCP_IRQ_APU2ADSP_ENGINE 86 +#define SCP_IRQ_APU2ADSP_MBOX 87 /* 88 */ -#define SCP_IRQ_CCIF3 88 -#define SCP_IRQ_I2C_DMA0 89 -#define SCP_IRQ_I2C_DMA1 90 -#define SCP_IRQ_I2C_DMA2 91 +#define SCP_IRQ_CCIF3 88 +#define SCP_IRQ_I2C_DMA0 89 +#define SCP_IRQ_I2C_DMA1 90 +#define SCP_IRQ_I2C_DMA2 91 /* 92 */ -#define SCP_IRQ_I2C_DMA3 92 +#define SCP_IRQ_I2C_DMA3 92 #endif /* __CROS_EC_INTC_H */ -- cgit v1.2.1 From dbb1522e7c20ee217141cabeae77a24706c166e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:04 -0600 Subject: board/kinox/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I258e4968271141ca578c732fb70a003270356e93 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728558 Reviewed-by: Jeremy Bettis --- board/kinox/sensors.c | 44 ++++++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/board/kinox/sensors.c b/board/kinox/sensors.c index e444664e8f..ccd2855f3d 100644 --- a/board/kinox/sensors.c +++ b/board/kinox/sensors.c @@ -63,30 +63,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CPU] = { - .name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CPU - }, - [TEMP_SENSOR_2_CPU_VR] = { - .name = "CPU VR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_CPU_VR - }, - [TEMP_SENSOR_3_WIFI] = { - .name = "WIFI", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_WIFI - }, - [TEMP_SENSOR_4_DIMM] = { - .name = "DIMM", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_DIMM - }, + [TEMP_SENSOR_1_CPU] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_CPU }, + [TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_CPU_VR }, + [TEMP_SENSOR_3_WIFI] = { .name = "WIFI", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_WIFI }, + [TEMP_SENSOR_4_DIMM] = { .name = "DIMM", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_DIMM }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -100,8 +92,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(95), \ -- cgit v1.2.1 From d1bab01be56a034a155dc7ce794517a3f7571248 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:04 -0600 Subject: baseboard/grunt/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaabfe4b57055bd0c4b9c96a8b092cab63eb642a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727516 Reviewed-by: Jeremy Bettis --- baseboard/grunt/baseboard.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index 5a79c48c63..4b2cc05065 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -8,15 +8,15 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H -#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) \ - + defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1 +#if (defined(VARIANT_GRUNT_TCPC_0_ANX3429) + \ + defined(VARIANT_GRUNT_TCPC_0_ANX3447)) != 1 #error Must choose VARIANT_GRUNT_TCPC_0_ANX3429 or VARIANT_GRUNT_TCPC_0_ANX3447 #endif /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ /* Flash is 1MB but reserve half for future use. */ @@ -85,7 +85,7 @@ * ACOK from ISL9238 sometimes has a negative pulse after connecting * USB-C power. We want to ignore it. b/77455171 */ -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_POWER_COMMON @@ -101,7 +101,6 @@ */ #define CONFIG_BOARD_RESET_AFTER_POWER_ON - #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 @@ -139,13 +138,13 @@ #define CONFIG_USB_PORT_POWER_DUMB #define USB_PORT_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Require PD negotiation to be complete when we are in a low-battery condition @@ -158,15 +157,15 @@ #undef CONFIG_PORT80_HISTORY_LEN #define CONFIG_PORT80_HISTORY_LEN 256 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT3_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* Sensors */ #define CONFIG_MKBP_EVENT @@ -184,8 +183,8 @@ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #endif /* VARIANT_GRUNT_NO_SENSORS */ -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 #ifndef __ASSEMBLER__ -- cgit v1.2.1 From bc60e44b99904122c9151daa99c0fd7d5eaa028d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:21 -0600 Subject: board/terrador/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie3bdaa2a096ef9d7fabc3937b6c294272b353b09 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729030 Reviewed-by: Jeremy Bettis --- board/terrador/board.h | 112 +++++++++++++++++++++++-------------------------- 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/board/terrador/board.h b/board/terrador/board.h index 4572a544c8..617d8737b3 100644 --- a/board/terrador/board.h +++ b/board/terrador/board.h @@ -46,49 +46,48 @@ /* TCS3400 ALS */ #define CONFIG_ALS -#define ALS_COUNT 1 +#define ALS_COUNT 1 #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ /* BC 1.2 */ @@ -98,8 +97,8 @@ #undef CONFIG_FANS /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -107,47 +106,46 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -176,11 +174,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From 55cb4ddf679010ba2f69bed8457d93414085a13d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:19 -0600 Subject: core/minute-ia/task_defs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e89cc3d3c43f94288661136bca04e8a2c9e50b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729858 Reviewed-by: Jeremy Bettis --- core/minute-ia/task_defs.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/core/minute-ia/task_defs.h b/core/minute-ia/task_defs.h index 18458b1533..d0bb35bfef 100644 --- a/core/minute-ia/task_defs.h +++ b/core/minute-ia/task_defs.h @@ -7,9 +7,9 @@ #define __CROS_EC_TASK_DEFS_H #ifdef CONFIG_FPU -#define FPU_CTX_SZ 108 /* 28 bytes header + 80 bytes registers */ -#define USE_FPU_OFFSET 20 /* offsetof(task_, use_fpu */ -#define FPU_CTX_OFFSET 24 /* offsetof(task_, fp_ctx) */ +#define FPU_CTX_SZ 108 /* 28 bytes header + 80 bytes registers */ +#define USE_FPU_OFFSET 20 /* offsetof(task_, use_fpu */ +#define FPU_CTX_OFFSET 24 /* offsetof(task_, fp_ctx) */ /* * defines for inline asm @@ -18,11 +18,11 @@ #include "atomic.h" #include "common.h" -#define USE_FPU_OFFSET_STR STRINGIFY(USE_FPU_OFFSET) /* "20" */ -#define FPU_CTX_OFFSET_STR STRINGIFY(FPU_CTX_OFFSET) /* "24" */ +#define USE_FPU_OFFSET_STR STRINGIFY(USE_FPU_OFFSET) /* "20" */ +#define FPU_CTX_OFFSET_STR STRINGIFY(FPU_CTX_OFFSET) /* "24" */ -asm (".equ USE_FPU_OFFSET, "USE_FPU_OFFSET_STR); -asm (".equ FPU_CTX_OFFSET, "FPU_CTX_OFFSET_STR); +asm(".equ USE_FPU_OFFSET, " USE_FPU_OFFSET_STR); +asm(".equ FPU_CTX_OFFSET, " FPU_CTX_OFFSET_STR); #endif #endif /* CONFIG_FPU */ @@ -34,12 +34,12 @@ typedef union { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ #ifdef CONFIG_FPU - uint32_t use_fpu; /* set if task uses FPU */ + uint32_t use_fpu; /* set if task uses FPU */ uint8_t fp_ctx[FPU_CTX_SZ]; /* x87 FPU context */ #endif }; @@ -50,7 +50,7 @@ void __switchto(void); void sw_irq_handler(void); /* Only the IF bit is set so tasks start with interrupts enabled. */ -#define INITIAL_EFLAGS (0x200UL) +#define INITIAL_EFLAGS (0x200UL) /* LAPIC ICR bit fields * 7:0 - vector @@ -61,7 +61,7 @@ void sw_irq_handler(void); * 15 - Trigger mode (0 = edge) * 20:18 - Destination (1 = self) */ -#define LAPIC_ICR_BITS 0x44000 +#define LAPIC_ICR_BITS 0x44000 #endif /* __ASSEMBLER__ */ #endif /* __CROS_EC_TASK_DEFS_H */ -- cgit v1.2.1 From 3f2598c036a88fcc69ca74f1951d361c451ed5f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:33 -0600 Subject: zephyr/shim/include/usbc/ppc_syv682x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I29cd0232f0fcfb4647e34ac156e3f7ae190d1122 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730836 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/ppc_syv682x.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/usbc/ppc_syv682x.h b/zephyr/shim/include/usbc/ppc_syv682x.h index 1c2691f684..f177aebe8b 100644 --- a/zephyr/shim/include/usbc/ppc_syv682x.h +++ b/zephyr/shim/include/usbc/ppc_syv682x.h @@ -7,12 +7,12 @@ #define SYV682X_COMPAT silergy_syv682x -#define PPC_CHIP_SYV682X(id) \ - { \ - .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ - .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags),\ - .drv = &syv682x_drv, \ - .frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, frs_en_gpio), \ - (GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), \ - (0)), \ +#define PPC_CHIP_SYV682X(id) \ + { \ + .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ + .drv = &syv682x_drv, \ + .frs_en = COND_CODE_1( \ + DT_NODE_HAS_PROP(id, frs_en_gpio), \ + (GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)), \ }, -- cgit v1.2.1 From cea320431e3458b032755f44d3819c747ee73991 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:15 -0600 Subject: board/quackingstick/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87c00ff680703ee78aaad56c1ef4085e396b73fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728870 Reviewed-by: Jeremy Bettis --- board/quackingstick/board.h | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/board/quackingstick/board.h b/board/quackingstick/board.h index f537d6b472..3e1bacc85c 100644 --- a/board/quackingstick/board.h +++ b/board/quackingstick/board.h @@ -13,7 +13,7 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Save some flash space */ #define CONFIG_LTO @@ -26,7 +26,7 @@ #undef CONFIG_CMD_TASK_RESET /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -82,10 +82,7 @@ enum adc_channel { ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_SYS2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_SYS2, TEMP_SENSOR_COUNT }; /* Motion sensors */ enum sensor_id { @@ -94,10 +91,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From a71c4e734ae355c659bb55cf9f4e4e73991c4fe3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:18 -0600 Subject: zephyr/test/i2c_dts/src/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e9413bae5a35df5192db995b3816799ddfe6d42 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730995 Reviewed-by: Jeremy Bettis --- zephyr/test/i2c_dts/src/main.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/zephyr/test/i2c_dts/src/main.c b/zephyr/test/i2c_dts/src/main.c index 7cb1052798..aad05285a8 100644 --- a/zephyr/test/i2c_dts/src/main.c +++ b/zephyr/test/i2c_dts/src/main.c @@ -10,14 +10,13 @@ static void test_i2c_get_device(void) { const struct device *accel0 = DEVICE_DT_GET( - DT_PHANDLE(DT_PATH(named_i2c_ports, accel_0), - i2c_port)); - const struct device *bmi_i2c = DEVICE_DT_GET( - DT_NODELABEL(bmi_i2c)); + DT_PHANDLE(DT_PATH(named_i2c_ports, accel_0), i2c_port)); + const struct device *bmi_i2c = DEVICE_DT_GET(DT_NODELABEL(bmi_i2c)); zassert_not_null(accel0, "accel0 was NULL"); zassert_not_null(bmi_i2c, "bmi_i2c was NULL"); - zassert_equal(accel0, bmi_i2c, + zassert_equal( + accel0, bmi_i2c, "named_i2c_ports/accel0 and bmi_i2c should resolve to the same device"); } -- cgit v1.2.1 From a40ef72133847dfc6013a677b0ad531f9e3c55d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:31 -0600 Subject: board/dirinboz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8eacd32f668953fb19faf4bc085e1c0786c74717 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728227 Reviewed-by: Jeremy Bettis --- board/dirinboz/led.c | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/board/dirinboz/led.c b/board/dirinboz/led.c index b05ade3bcc..60526bee12 100644 --- a/board/dirinboz/led.c +++ b/board/dirinboz/led.c @@ -28,13 +28,10 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LEFT_PORT = 0, - RIGHT_PORT -}; +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; static void led_set_color_battery(int port, enum led_color color) { @@ -44,9 +41,9 @@ static void led_set_color_battery(int port, enum led_color color) cbi_get_board_version(&board_ver); amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L : - IOEX_C1_CHARGER_LED_AMBER_DB); + IOEX_C1_CHARGER_LED_AMBER_DB); white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L : - IOEX_C1_CHARGER_LED_WHITE_DB); + IOEX_C1_CHARGER_LED_WHITE_DB); if ((board_ver >= 3) && (port == RIGHT_PORT)) { led_batt_on_lvl = 1; @@ -126,10 +123,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -145,16 +142,14 @@ static void led_set_battery(void) * design, blinking both two side battery white LEDs to indicate * system suspend with non-charging state. */ - if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && - charge_get_state() != PWR_STATE_CHARGE) { - + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) && + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; - led_set_color_battery(RIGHT_PORT, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); - led_set_color_battery(LEFT_PORT, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery(RIGHT_PORT, + power_ticks & 0x4 ? LED_WHITE : LED_OFF); + led_set_color_battery(LEFT_PORT, + power_ticks & 0x4 ? LED_WHITE : LED_OFF); return; } @@ -168,9 +163,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } @@ -179,17 +177,19 @@ static void led_set_battery(void) led_set_color_battery(LEFT_PORT, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 4a3bfc15446b00e7b3f04ad336f55dfeea7ff8c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:54 -0600 Subject: util/lock/file_lock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6dfef33d9497794eeb52278fe1344081038a00c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730650 Reviewed-by: Jeremy Bettis --- util/lock/file_lock.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/util/lock/file_lock.c b/util/lock/file_lock.c index 36b420d287..a3244f5237 100644 --- a/util/lock/file_lock.c +++ b/util/lock/file_lock.c @@ -59,7 +59,7 @@ #include "ipc_lock.h" #include "locks.h" -#define SLEEP_INTERVAL_MS 50 +#define SLEEP_INTERVAL_MS 50 static void msecs_to_timespec(int msecs, struct timespec *tmspec) { @@ -100,8 +100,8 @@ static int file_lock_open_or_create(struct ipc_lock *lock) if (!tmpdir) return -1; - if (snprintf(path, sizeof(path), "%s/%s", - tmpdir, lock->filename) < 0) { + if (snprintf(path, sizeof(path), "%s/%s", tmpdir, + lock->filename) < 0) { return -1; } } else { @@ -115,10 +115,9 @@ static int file_lock_open_or_create(struct ipc_lock *lock) return -1; } - if (snprintf(path, sizeof(path), - "%s/%s", dir, lock->filename) < 0) + if (snprintf(path, sizeof(path), "%s/%s", dir, lock->filename) < + 0) return -1; - } lock->fd = open(path, O_RDWR | O_CREAT, 0600); @@ -180,9 +179,9 @@ static int file_lock_write_pid(struct ipc_lock *lock) { ssize_t len; /* - * PIDs are usually 5 digits, but we'll reserve enough room for + * PIDs are usually 5 digits, but we'll reserve enough room for * a value of 2^32 (10 digits) out of paranoia. - */ + */ char pid_str[11]; if (ftruncate(lock->fd, 0) < 0) { -- cgit v1.2.1 From 746672053d7096da276bab81ccdd304392f798c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:43 -0600 Subject: board/marzipan/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide7fbde53a9979a2c56d74e66bd5a6e0c85fb961 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728668 Reviewed-by: Jeremy Bettis --- board/marzipan/led.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/marzipan/led.c b/board/marzipan/led.c index e4b34576c8..996d06cdd5 100644 --- a/board/marzipan/led.c +++ b/board/marzipan/led.c @@ -32,15 +32,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C1, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_B_C1, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From 9a5d365803b563043d169d6c290f3b41586f6853 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:28 -0600 Subject: board/twinkie/sniffer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie2bd65ba5c3388e11315c6b396da4949906c93e3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729042 Reviewed-by: Jeremy Bettis --- board/twinkie/sniffer.c | 68 ++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 38 deletions(-) diff --git a/board/twinkie/sniffer.c b/board/twinkie/sniffer.c index 7d2d8d439f..6b07fc7d1d 100644 --- a/board/twinkie/sniffer.c +++ b/board/twinkie/sniffer.c @@ -105,8 +105,8 @@ static void ep_tx(void) btable_ep[USB_EP_SNIFFER].tx_addr = usb_sram_addr(ep_buf[b]); } /* re-enable data transmission if we have available data */ - btable_ep[USB_EP_SNIFFER].tx_count = (free_usb & (1<> 12) & 0x1) +#define get_channel(b) (((b) >> 12) & 0x1) void tim_rx1_handler(uint32_t stat) { @@ -171,8 +170,7 @@ void tim_rx1_handler(uint32_t stat) uint32_t next = idx ? 0x0001 : 0x0100; sample_tstamp[idx] = __hw_clock_source_read(); - sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | - (SNIFFER_CHANNEL_CC1<<12); + sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC1 << 12); if (filled_dma & next) { oflow++; sample_seq[idx] |= 0x8000; @@ -193,8 +191,7 @@ void tim_rx2_handler(uint32_t stat) idx += 2; sample_tstamp[idx] = __hw_clock_source_read(); - sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | - (SNIFFER_CHANNEL_CC2<<12); + sample_seq[idx] = ((seq++ << 3) & 0x0ff8) | (SNIFFER_CHANNEL_CC2 << 12); if (filled_dma & next) { oflow++; sample_seq[idx] |= 0x8000; @@ -209,10 +206,10 @@ void tim_rx2_handler(uint32_t stat) static void tim_dma_handler(void) { stm32_dma_regs_t *dma = STM32_DMA1_REGS; - uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1) - | STM32_DMA_ISR_TCIF(DMAC_TIM_RX1) - | STM32_DMA_ISR_HTIF(DMAC_TIM_RX2) - | STM32_DMA_ISR_TCIF(DMAC_TIM_RX2)); + uint32_t stat = dma->isr & (STM32_DMA_ISR_HTIF(DMAC_TIM_RX1) | + STM32_DMA_ISR_TCIF(DMAC_TIM_RX1) | + STM32_DMA_ISR_HTIF(DMAC_TIM_RX2) | + STM32_DMA_ISR_TCIF(DMAC_TIM_RX2)); if (stat & STM32_DMA_ISR_ALL(DMAC_TIM_RX2)) tim_rx2_handler(stat); else @@ -251,30 +248,26 @@ static void rx_timer_init(int tim_id, timer_ctlr_t *tim, int ch_idx, int up_idx) tim->sr = 0; } - - void sniffer_init(void) { /* remap TIM1 CH1/2/3 to DMA channel 6 */ STM32_SYSCFG_CFGR1 |= BIT(28); /* TIM1 CH1 for CC1 RX */ - rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1), - TIM_RX1_CCR_IDX, 2); + rx_timer_init(TIM_RX1, (void *)STM32_TIM_BASE(TIM_RX1), TIM_RX1_CCR_IDX, + 2); /* TIM3 CH4 for CC2 RX */ - rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2), - TIM_RX2_CCR_IDX, 2); + rx_timer_init(TIM_RX2, (void *)STM32_TIM_BASE(TIM_RX2), TIM_RX2_CCR_IDX, + 2); /* turn on COMP/SYSCFG */ STM32_RCC_APB2ENR |= BIT(0); - STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED | - STM32_COMP_CMP1INSEL_VREF12 | - STM32_COMP_CMP1OUTSEL_TIM1_IC1 | - STM32_COMP_CMP1HYST_HI | - STM32_COMP_CMP2EN | STM32_COMP_CMP2MODE_HSPEED | - STM32_COMP_CMP2INSEL_VREF12 | - STM32_COMP_CMP2OUTSEL_TIM2_IC4 | - STM32_COMP_CMP2HYST_HI; + STM32_COMP_CSR = + STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_HSPEED | + STM32_COMP_CMP1INSEL_VREF12 | STM32_COMP_CMP1OUTSEL_TIM1_IC1 | + STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2EN | + STM32_COMP_CMP2MODE_HSPEED | STM32_COMP_CMP2INSEL_VREF12 | + STM32_COMP_CMP2OUTSEL_TIM2_IC4 | STM32_COMP_CMP2HYST_HI; /* start sampling the edges on the CC lines using the RX timers */ dma_start_rx(&dma_tim_cc1, RX_COUNT, samples[0]); @@ -311,11 +304,11 @@ void sniffer_task(void) ep_buf[u][0] = sample_seq[d >> 3] | (d & 7); ep_buf[u][1] = sample_tstamp[d >> 3]; - memcpy_to_usbram( - ((void *)usb_sram_addr(ep_buf[u] - + (EP_PACKET_HEADER_SIZE>>1))), - samples[d >> 4]+off, - EP_PAYLOAD_SIZE); + memcpy_to_usbram(((void *)usb_sram_addr( + ep_buf[u] + + (EP_PACKET_HEADER_SIZE >> 1))), + samples[d >> 4] + off, + EP_PAYLOAD_SIZE); atomic_clear_bits((atomic_t *)&free_usb, 1 << u); u = !u; atomic_clear_bits((atomic_t *)&filled_dma, 1 << d); @@ -332,8 +325,8 @@ void sniffer_task(void) int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us) { - stm32_dma_chan_t *chan = dma_get_channel(pol ? DMAC_TIM_RX2 - : DMAC_TIM_RX1); + stm32_dma_chan_t *chan = + dma_get_channel(pol ? DMAC_TIM_RX2 : DMAC_TIM_RX1); uint32_t t0 = __hw_clock_source_read(); uint32_t c0 = chan->cndtr; uint32_t t_gap = t0; @@ -355,7 +348,7 @@ int wait_packet(int pol, uint32_t min_edges, uint32_t timeout_us) total_edges += nb; } else { if ((t - t_gap) > 20 && - (total_edges - (t - t0)/256) >= min_edges) + (total_edges - (t - t0) / 256) >= min_edges) /* real gap after the packet */ break; } @@ -398,5 +391,4 @@ static int command_sniffer(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer, - "[]", "Buffering status"); +DECLARE_CONSOLE_COMMAND(sniffer, command_sniffer, "[]", "Buffering status"); -- cgit v1.2.1 From 27d4a70b39cc4d11b02744c2aff3f1b81d6ff1ee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:15 -0600 Subject: driver/led/lm3509.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide41ed5419bfda44ac10a28d7eeef884c03bca5a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729997 Reviewed-by: Jeremy Bettis --- driver/led/lm3509.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/led/lm3509.h b/driver/led/lm3509.h index a7defe1fb7..d18d22aaed 100644 --- a/driver/led/lm3509.h +++ b/driver/led/lm3509.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_LM3509_H #define __CROS_EC_LM3509_H -#define LM3509_I2C_ADDR_FLAGS 0x36 +#define LM3509_I2C_ADDR_FLAGS 0x36 /* * General purpose register @@ -18,7 +18,7 @@ * [1]= enable secondary current sink. * [0]= enable main current sink. */ -#define LM3509_REG_GP 0x10 +#define LM3509_REG_GP 0x10 /* * Brightness register @@ -27,10 +27,10 @@ * 0x1F: 100% * Power-on-value: 0% (0xE0) */ -#define LM3509_REG_BMAIN 0xA0 -#define LM3509_REG_BSUB 0xB0 +#define LM3509_REG_BMAIN 0xA0 +#define LM3509_REG_BSUB 0xB0 -#define LM3509_BMAIN_MASK 0x1F +#define LM3509_BMAIN_MASK 0x1F extern const struct kblight_drv kblight_lm3509; -- cgit v1.2.1 From 3c67a5d914fd90b14fc4f9e6bb8c03bb5539ccda Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:25 -0600 Subject: zephyr/subsys/ap_pwrseq/ap_power_interface.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2a425e4b4d04e0816f76d6fe1afedd7052af9460 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730948 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/ap_power_interface.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/ap_power_interface.c b/zephyr/subsys/ap_pwrseq/ap_power_interface.c index c959f4b976..69b2ddab9e 100644 --- a/zephyr/subsys/ap_pwrseq/ap_power_interface.c +++ b/zephyr/subsys/ap_pwrseq/ap_power_interface.c @@ -6,8 +6,7 @@ #include #include -bool ap_power_in_state( - enum ap_power_state_mask state_mask) +bool ap_power_in_state(enum ap_power_state_mask state_mask) { int need_mask = 0; @@ -21,16 +20,14 @@ bool ap_power_in_state( * In between hard and soft off states. Match only if caller * will accept both. */ - need_mask = AP_POWER_STATE_HARD_OFF | - AP_POWER_STATE_SOFT_OFF; + need_mask = AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF; break; case SYS_POWER_STATE_S5: need_mask = AP_POWER_STATE_SOFT_OFF; break; case SYS_POWER_STATE_S5S4: case SYS_POWER_STATE_S4S5: - need_mask = AP_POWER_STATE_SOFT_OFF | - AP_POWER_STATE_SUSPEND; + need_mask = AP_POWER_STATE_SOFT_OFF | AP_POWER_STATE_SUSPEND; break; case SYS_POWER_STATE_S4: case SYS_POWER_STATE_S4S3: @@ -40,8 +37,7 @@ bool ap_power_in_state( break; case SYS_POWER_STATE_S3S0: case SYS_POWER_STATE_S0S3: - need_mask = AP_POWER_STATE_SUSPEND | - AP_POWER_STATE_ON; + need_mask = AP_POWER_STATE_SUSPEND | AP_POWER_STATE_ON; break; case SYS_POWER_STATE_S0: need_mask = AP_POWER_STATE_ON; @@ -60,8 +56,7 @@ bool ap_power_in_state( return (state_mask & need_mask) == need_mask; } -bool ap_power_in_or_transitioning_to_state( - enum ap_power_state_mask state_mask) +bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask state_mask) { switch (pwr_sm_get_state()) { case SYS_POWER_STATE_G3: -- cgit v1.2.1 From 632cb071b59a3919f86a76ea71247436109bb17e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:52 -0600 Subject: chip/it83xx/ec2i.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb4f6559617a71c16057b468242529da8eddfd69 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729196 Reviewed-by: Jeremy Bettis --- chip/it83xx/ec2i.c | 83 +++++++++++++++++++++++++++--------------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c index 5542d455a9..d56eefc165 100644 --- a/chip/it83xx/ec2i.c +++ b/chip/it83xx/ec2i.c @@ -16,10 +16,10 @@ static const struct ec2i_t keyboard_settings[] = { /* Select logical device 06h(keyboard) */ - {HOST_INDEX_LDN, LDN_KBC_KEYBOARD}, + { HOST_INDEX_LDN, LDN_KBC_KEYBOARD }, /* Set IRQ=01h for logical device */ - {HOST_INDEX_IRQNUMX, 0x01}, - /* Configure IRQTP for KBC. */ + { HOST_INDEX_IRQNUMX, 0x01 }, +/* Configure IRQTP for KBC. */ #ifdef CONFIG_HOST_INTERFACE_ESPI /* * Interrupt request type select (IRQTP) for KBC. @@ -39,55 +39,55 @@ static const struct ec2i_t keyboard_settings[] = { * Additionally, this interrupt is configured as edge-triggered on the * host side. So, match the trigger mode on the EC side as well. */ - {HOST_INDEX_IRQTP, 0x02}, + { HOST_INDEX_IRQTP, 0x02 }, #endif /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; #ifdef CONFIG_IT83XX_ENABLE_MOUSE_DEVICE static const struct ec2i_t mouse_settings[] = { /* Select logical device 05h(mouse) */ - {HOST_INDEX_LDN, LDN_KBC_MOUSE}, + { HOST_INDEX_LDN, LDN_KBC_MOUSE }, /* Set IRQ=0Ch for logical device */ - {HOST_INDEX_IRQNUMX, 0x0C}, + { HOST_INDEX_IRQNUMX, 0x0C }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; #endif static const struct ec2i_t pm1_settings[] = { /* Select logical device 11h(PM1 ACPI) */ - {HOST_INDEX_LDN, LDN_PMC1}, + { HOST_INDEX_LDN, LDN_PMC1 }, /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, + { HOST_INDEX_IRQNUMX, 0x00 }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; static const struct ec2i_t pm2_settings[] = { /* Select logical device 12h(PM2) */ - {HOST_INDEX_LDN, LDN_PMC2}, + { HOST_INDEX_LDN, LDN_PMC2 }, /* I/O Port Base Address 200h/204h */ - {HOST_INDEX_IOBAD0_MSB, 0x02}, - {HOST_INDEX_IOBAD0_LSB, 0x00}, - {HOST_INDEX_IOBAD1_MSB, 0x02}, - {HOST_INDEX_IOBAD1_LSB, 0x04}, + { HOST_INDEX_IOBAD0_MSB, 0x02 }, + { HOST_INDEX_IOBAD0_LSB, 0x00 }, + { HOST_INDEX_IOBAD1_MSB, 0x02 }, + { HOST_INDEX_IOBAD1_LSB, 0x04 }, /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, + { HOST_INDEX_IRQNUMX, 0x00 }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; static const struct ec2i_t smfi_settings[] = { /* Select logical device 0Fh(SMFI) */ - {HOST_INDEX_LDN, LDN_SMFI}, + { HOST_INDEX_LDN, LDN_SMFI }, /* H2RAM LPC I/O cycle Dxxx */ - {HOST_INDEX_DSLDC6, 0x00}, + { HOST_INDEX_DSLDC6, 0x00 }, /* Enable H2RAM LPC I/O cycle */ - {HOST_INDEX_DSLDC7, 0x01}, + { HOST_INDEX_DSLDC7, 0x01 }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; /* @@ -96,16 +96,16 @@ static const struct ec2i_t smfi_settings[] = { */ static const struct ec2i_t pm3_settings[] = { /* Select logical device 17h(PM3) */ - {HOST_INDEX_LDN, LDN_PMC3}, + { HOST_INDEX_LDN, LDN_PMC3 }, /* I/O Port Base Address 80h */ - {HOST_INDEX_IOBAD0_MSB, 0x00}, - {HOST_INDEX_IOBAD0_LSB, 0x80}, - {HOST_INDEX_IOBAD1_MSB, 0x00}, - {HOST_INDEX_IOBAD1_LSB, 0x00}, + { HOST_INDEX_IOBAD0_MSB, 0x00 }, + { HOST_INDEX_IOBAD0_LSB, 0x80 }, + { HOST_INDEX_IOBAD1_MSB, 0x00 }, + { HOST_INDEX_IOBAD1_LSB, 0x00 }, /* Set IRQ=00h for logical device */ - {HOST_INDEX_IRQNUMX, 0x00}, + { HOST_INDEX_IRQNUMX, 0x00 }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; /* @@ -115,28 +115,28 @@ static const struct ec2i_t pm3_settings[] = { */ static const struct ec2i_t rtct_settings[] = { /* Select logical device 10h(RTCT) */ - {HOST_INDEX_LDN, LDN_RTCT}, + { HOST_INDEX_LDN, LDN_RTCT }, /* P80L Begin Index */ - {HOST_INDEX_DSLDC4, P80L_P80LB}, + { HOST_INDEX_DSLDC4, P80L_P80LB }, /* P80L End Index */ - {HOST_INDEX_DSLDC5, P80L_P80LE}, + { HOST_INDEX_DSLDC5, P80L_P80LE }, /* P80L Current Index */ - {HOST_INDEX_DSLDC6, P80L_P80LC}, + { HOST_INDEX_DSLDC6, P80L_P80LC }, }; #ifdef CONFIG_UART_HOST static const struct ec2i_t uart2_settings[] = { /* Select logical device 2h(UART2) */ - {HOST_INDEX_LDN, LDN_UART2}, + { HOST_INDEX_LDN, LDN_UART2 }, /* * I/O port base address is 2F8h. * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2. * See specification 7.24.4 for more detial. */ - {HOST_INDEX_IOBAD0_MSB, 0x02}, - {HOST_INDEX_IOBAD0_LSB, 0xF8}, + { HOST_INDEX_IOBAD0_MSB, 0x02 }, + { HOST_INDEX_IOBAD0_LSB, 0xF8 }, /* IRQ number is 3 */ - {HOST_INDEX_IRQNUMX, 0x03}, + { HOST_INDEX_IRQNUMX, 0x03 }, /* * Interrupt Request Type Select * bit1, 0: IRQ request is buffered and applied to SERIRQ. @@ -144,9 +144,9 @@ static const struct ec2i_t uart2_settings[] = { * bit0, 0: Edge triggered mode. * 1: Level triggered mode. */ - {HOST_INDEX_IRQTP, 0x02}, + { HOST_INDEX_IRQTP, 0x02 }, /* Enable logical device */ - {HOST_INDEX_LDA, 0x01}, + { HOST_INDEX_LDA, 0x01 }, }; #endif @@ -163,7 +163,7 @@ enum ec2i_status_mask { EC2I_STATUS_CRIB = BIT(1), /* 1: EC write-access is still processing with IHD register. */ EC2I_STATUS_CWIB = BIT(2), - EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB), + EC2I_STATUS_ALL = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB), }; static int ec2i_wait_status_bit_cleared(enum ec2i_status_mask mask) @@ -288,8 +288,7 @@ static void pnpcfg_configure(const struct ec2i_t *settings, size_t entries) } } -#define PNPCFG(_s) \ - pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings)) +#define PNPCFG(_s) pnpcfg_configure(_s##_settings, ARRAY_SIZE(_s##_settings)) static void pnpcfg_init(void) { -- cgit v1.2.1 From 1a9a5d21665dcfe1781cbbff8f70bc40f0d5c51d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:53 -0600 Subject: board/kukui_scp/fd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I228464d1c4bb1695b256b9d8f7d582300dc823e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728594 Reviewed-by: Jeremy Bettis --- board/kukui_scp/fd.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/board/kukui_scp/fd.c b/board/kukui_scp/fd.c index 237f15ca94..09f4f64f27 100644 --- a/board/kukui_scp/fd.c +++ b/board/kukui_scp/fd.c @@ -20,12 +20,11 @@ static struct consumer const event_fd_consumer; static void event_fd_written(struct consumer const *consumer, size_t count); -static struct queue const fd_queue = QUEUE_DIRECT(4, struct fd_msg, - null_producer, - event_fd_consumer); +static struct queue const fd_queue = + QUEUE_DIRECT(4, struct fd_msg, null_producer, event_fd_consumer); static struct consumer const event_fd_consumer = { .queue = &fd_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_fd_written, }), }; @@ -33,7 +32,9 @@ static struct consumer const event_fd_consumer = { /* Stub functions only provided by private overlays. */ // Jerry TODO implement private part and remove this #ifndef HAVE_PRIVATE_MT8183 -void fd_ipi_msg_handler(void *data) {} +void fd_ipi_msg_handler(void *data) +{ +} #endif static void event_fd_written(struct consumer const *consumer, size_t count) -- cgit v1.2.1 From 17365a497c2b93d8fec14f71f6bcd72c1ee48a7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:39 -0600 Subject: board/mrbland/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iddbc105d8bb40df0c505657bec393172f68779e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728704 Reviewed-by: Jeremy Bettis --- board/mrbland/base_detect.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/mrbland/base_detect.c b/board/mrbland/base_detect.c index 70217868ea..4b4c8a17dc 100644 --- a/board/mrbland/base_detect.c +++ b/board/mrbland/base_detect.c @@ -20,8 +20,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Make sure POGO VBUS starts later then PP3300_HUB when power on */ #define BASE_DETECT_EN_LATER_US (600 * MSEC) @@ -85,7 +85,7 @@ static void base_detect_change(enum base_status status) { int connected = (status == BASE_CONNECTED); bool base_enable_allow = - !chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF); + !chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF); if ((current_base_status == status) && (current_base_enable_allow == base_enable_allow)) @@ -109,8 +109,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -202,8 +202,7 @@ static void base_enable(void) { /* Enable base detection interrupt. */ base_detect_debounce_time = get_time().val; - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_EN_LATER_US); + hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US); gpio_enable_interrupt(GPIO_BASE_DET_L); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT); @@ -228,7 +227,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From a88426045ce5addc8701381be29b911bc7ee0f5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:52 -0600 Subject: board/bugzzy/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1acccf2802323d55b01209984a7d68612f67d7e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728105 Reviewed-by: Jeremy Bettis --- board/bugzzy/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/bugzzy/cbi_ssfc.c b/board/bugzzy/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/bugzzy/cbi_ssfc.c +++ b/board/bugzzy/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From cbb3ada26aceafad7e90dc467a6cb6f4a98280a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:11 -0600 Subject: board/herobrine/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib19ffbca836756c67b5823509f8fe867be733ead Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728304 Reviewed-by: Jeremy Bettis --- board/herobrine/led.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/board/herobrine/led.c b/board/herobrine/led.c index 295c8effeb..31724dbfc9 100644 --- a/board/herobrine/led.c +++ b/board/herobrine/led.c @@ -31,15 +31,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void side_led_set_color(int port, enum led_color color) { gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -102,8 +102,9 @@ static void board_led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() <= 10) - side_led_set_color(0, - (battery_ticks & 0x4) ? LED_WHITE : LED_OFF); + side_led_set_color(0, (battery_ticks & 0x4) ? + LED_WHITE : + LED_OFF); else side_led_set_color(0, LED_OFF); } @@ -112,16 +113,16 @@ static void board_led_set_battery(void) side_led_set_color(1, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks & 0x4) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks & 0x4) ? LED_AMBER : LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 38e2dbce7c446f2bc4617e6d73d2c72c97796d9b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:55 -0600 Subject: zephyr/drivers/cros_flash/cros_flash_xec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I33d83aedf6d280c52d5a6039e0afd93ae6881ec2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730670 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_flash/cros_flash_xec.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/zephyr/drivers/cros_flash/cros_flash_xec.c b/zephyr/drivers/cros_flash/cros_flash_xec.c index 2424c2a499..53ab4c57a7 100644 --- a/zephyr/drivers/cros_flash/cros_flash_xec.c +++ b/zephyr/drivers/cros_flash/cros_flash_xec.c @@ -184,7 +184,7 @@ static int cros_flash_xec_set_status_reg(const struct device *dev, } static int cros_flash_xec_write_protection_set(const struct device *dev, - bool enable) + bool enable) { int ret = 0; @@ -303,8 +303,7 @@ static int flash_set_status_for_prot(const struct device *dev, int reg1) flash_set_status(dev, reg1); - spi_flash_reg_to_protect(reg1, 0, &addr_prot_start, - &addr_prot_length); + spi_flash_reg_to_protect(reg1, 0, &addr_prot_start, &addr_prot_length); return EC_SUCCESS; } @@ -392,7 +391,6 @@ static int cros_flash_xec_init(const struct device *dev) return 0; } - static int cros_flash_xec_write(const struct device *dev, int offset, int size, const char *src_data) { @@ -524,7 +522,7 @@ static int cros_flash_xec_protect_now(const struct device *dev, int all) } static int cros_flash_xec_get_jedec_id(const struct device *dev, - uint8_t *manufacturer, uint16_t *device) + uint8_t *manufacturer, uint16_t *device) { int ret; uint8_t jedec_id[3]; @@ -546,7 +544,7 @@ static int cros_flash_xec_get_jedec_id(const struct device *dev, } static int cros_flash_xec_get_status(const struct device *dev, uint8_t *sr1, - uint8_t *sr2) + uint8_t *sr2) { flash_get_status(dev, sr1); *sr2 = 0; -- cgit v1.2.1 From a83dee32432f3efd92c881e5a3f202e22fa28006 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:12 -0600 Subject: common/led_policy_std.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff803cbd243dcdd3df176cad19a55aaa46222b03 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729667 Reviewed-by: Jeremy Bettis --- common/led_policy_std.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/common/led_policy_std.c b/common/led_policy_std.c index 65bf8cedbd..0a5cd6460f 100644 --- a/common/led_policy_std.c +++ b/common/led_policy_std.c @@ -31,8 +31,8 @@ #define POWER_LED_OFF 0 #endif -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -42,7 +42,7 @@ enum led_color { LED_AMBER, LED_GREEN, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int bat_led_set_color(enum led_color color) @@ -108,15 +108,18 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) case EC_LED_ID_BATTERY_LED: gpio_set_level(GPIO_BAT_LED_RED, (brightness[EC_LED_COLOR_RED] != 0) ? - BAT_LED_ON : BAT_LED_OFF); + BAT_LED_ON : + BAT_LED_OFF); gpio_set_level(GPIO_BAT_LED_GREEN, (brightness[EC_LED_COLOR_GREEN] != 0) ? - BAT_LED_ON : BAT_LED_OFF); + BAT_LED_ON : + BAT_LED_OFF); break; case EC_LED_ID_POWER_LED: gpio_set_level(GPIO_POWER_LED, (brightness[EC_LED_COLOR_WHITE] != 0) ? - POWER_LED_ON : POWER_LED_OFF); + POWER_LED_ON : + POWER_LED_OFF); break; default: return EC_ERROR_UNKNOWN; @@ -163,11 +166,11 @@ static void std_led_set_battery(void) break; case PWR_STATE_DISCHARGE: if (charge_get_percent() < 3) - bat_led_set_color((battery_second & 1) - ? LED_OFF : LED_AMBER); + bat_led_set_color((battery_second & 1) ? LED_OFF : + LED_AMBER); else if (charge_get_percent() < 10) - bat_led_set_color((battery_second & 3) - ? LED_OFF : LED_AMBER); + bat_led_set_color((battery_second & 3) ? LED_OFF : + LED_AMBER); else bat_led_set_color(LED_OFF); break; @@ -179,8 +182,8 @@ static void std_led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE. */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - bat_led_set_color( - (battery_second & 0x2) ? LED_GREEN : LED_AMBER); + bat_led_set_color((battery_second & 0x2) ? LED_GREEN : + LED_AMBER); else bat_led_set_color(LED_GREEN); break; -- cgit v1.2.1 From 239934fed3814635c07a3a477431f8ab22cfb2a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:00 -0600 Subject: chip/stm32/usb_pd_phy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0daa38fc7f041da82c6a31ec6a13b8162d67328 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729559 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_pd_phy.c | 116 ++++++++++++++++++++++++------------------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c index 21484b1a88..62c18200a9 100644 --- a/chip/stm32/usb_pd_phy.c +++ b/chip/stm32/usb_pd_phy.c @@ -21,8 +21,8 @@ #include "usb_pd_config.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -38,7 +38,7 @@ */ #define PD_BIT_LEN 429 -#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2) +#define PD_MAX_RAW_SIZE (PD_BIT_LEN * 2) /* maximum number of consecutive similar bits with Biphase Mark Coding */ #define MAX_BITS 2 @@ -46,12 +46,12 @@ /* alternating bit sequence used for packet preamble : 00 10 11 01 00 .. */ #define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */ -#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE))) +#define TX_CLOCK_DIV ((clock_get_freq() / (2 * PD_DATARATE))) /* threshold for 1 300-khz period */ #define PERIOD 4 -#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD) -#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2) +#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD / 2)) & 0xFF) / PERIOD) +#define PERIOD_THRESHOLD ((PERIOD + 2 * PERIOD) / 2) static struct pd_physical { /* samples for the PD messages */ @@ -73,8 +73,8 @@ static struct pd_physical { } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT]; /* keep track of RX edge timing in order to trigger receive */ -static timestamp_t - rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT][PD_RX_TRANSITION_COUNT]; +static timestamp_t rx_edge_ts[CONFIG_USB_PD_PORT_MAX_COUNT] + [PD_RX_TRANSITION_COUNT]; static int rx_edge_ts_idx[CONFIG_USB_PD_PORT_MAX_COUNT]; /* keep track of transmit polarity for DMA interrupt */ @@ -95,8 +95,8 @@ static int wait_bits(int port, int nb) avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE); if (avail < nb) { /* no received yet ... */ - while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) - && !(pd_phy[port].tim_rx->sr & 4)) + while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) && + !(pd_phy[port].tim_rx->sr & 4)) ; /* optimized for latency, not CPU usage ... */ if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) { CPRINTS("PD TMOUT RX %d/%d", @@ -117,8 +117,8 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val) w = wait_bits(port, off + 2); if (w < 0) goto stream_err; - cnt = samples[off] - samples[off-1]; - if (!cnt || (cnt > 3*PERIOD)) + cnt = samples[off] - samples[off - 1]; + if (!cnt || (cnt > 3 * PERIOD)) goto stream_err; off++; if (cnt <= PERIOD_THRESHOLD) { @@ -127,20 +127,22 @@ int pd_dequeue_bits(int port, int off, int len, uint32_t *val) if (w < 0) goto stream_err; */ - cnt = samples[off] - samples[off-1]; - if (cnt > PERIOD_THRESHOLD) + cnt = samples[off] - samples[off - 1]; + if (cnt > PERIOD_THRESHOLD) goto stream_err; off++; } /* enqueue the bit of the last period */ - pd_phy[port].d_last = (pd_phy[port].d_last >> 1) - | (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); + pd_phy[port].d_last = + (pd_phy[port].d_last >> 1) | + (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0); pd_phy[port].d_lastlen++; } if (off < PD_MAX_RAW_SIZE) { - *val = (pd_phy[port].d_last << (pd_phy[port].d_lastlen - len)) - >> (32 - len); + *val = (pd_phy[port].d_last + << (pd_phy[port].d_lastlen - len)) >> + (32 - len); pd_phy[port].d_lastlen -= len; return off; } else { @@ -168,7 +170,7 @@ int pd_find_preamble(int port) /* wait if the bit is not received yet ... */ if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) { while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) && - !(pd_phy[port].tim_rx->sr & 4)) + !(pd_phy[port].tim_rx->sr & 4)) ; if (pd_phy[port].tim_rx->sr & 4) { CPRINTS("PD TMOUT RX %d/%d", @@ -176,7 +178,7 @@ int pd_find_preamble(int port) return -1; } } - cnt = vals[bit] - vals[bit-1]; + cnt = vals[bit] - vals[bit - 1]; all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? BIT(31) : 0); if (all == 0x36db6db6) return bit - 1; /* should be SYNC-1 */ @@ -198,7 +200,7 @@ int pd_write_preamble(int port) msg[2] = PD_PREAMBLE; msg[3] = PD_PREAMBLE; pd_phy[port].b_toggle = 0x3FF; /* preamble ends with 1 */ - return 2*64; + return 2 * 64; } int pd_write_sym(int port, int bit_off, uint32_t val10) @@ -214,10 +216,10 @@ int pd_write_sym(int port, int bit_off, uint32_t val10) msg[word_idx] |= val << bit_idx; } else { msg[word_idx] |= val << bit_idx; - msg[word_idx+1] = val >> (32 - bit_idx); + msg[word_idx + 1] = val >> (32 - bit_idx); /* side effect: clear the new word when starting it */ } - return bit_off + 5*2; + return bit_off + 5 * 2; } int pd_write_last_edge(int port, int bit_off) @@ -239,7 +241,7 @@ int pd_write_last_edge(int port, int bit_off) } } /* ensure that the trailer is 0 */ - msg[word_idx+1] = 0; + msg[word_idx + 1] = 0; return bit_off + 3; } @@ -252,15 +254,15 @@ void pd_dump_packet(int port, const char *msg) CPRINTF("ERR %s:\n000:- ", msg); /* Packet debug output */ - for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { - int cnt = NB_PERIOD(vals[bit-1], vals[bit]); + for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) { + int cnt = NB_PERIOD(vals[bit - 1], vals[bit]); if ((bit & 31) == 0) CPRINTF("\n%03d:", bit); CPRINTF("%1d ", cnt); } CPRINTF("><\n"); cflush(); - for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { + for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) { if ((bit & 31) == 0) CPRINTF("\n%03d:", bit); CPRINTF("%02x ", vals[bit]); @@ -280,9 +282,9 @@ void pd_tx_spi_init(int port) spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8); /* Enable the slave SPI: LSB first, force NSS, TX only, CPHA */ - spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST - | STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE - | STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; + spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST | + STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE | + STM32_SPI_CR1_BIDIOE | STM32_SPI_CR1_CPHA; } static void tx_dma_done(void *data) @@ -330,9 +332,8 @@ int pd_start_tx(int port, int polarity, int bit_len) pd_phy[port].tim_tx->cnt = TX_CLOCK_DIV - 1; /* update DMA configuration */ - dma_prepare_tx(&(pd_phy[port].dma_tx_option), - DIV_ROUND_UP(bit_len, 8), - pd_phy[port].raw_samples); + dma_prepare_tx(&(pd_phy[port].dma_tx_option), DIV_ROUND_UP(bit_len, 8), + pd_phy[port].raw_samples); /* Flush data in write buffer so that DMA can get the latest data */ asm volatile("dmb;"); @@ -343,8 +344,7 @@ int pd_start_tx(int port, int polarity, int bit_len) if (!(pd_phy[port].dma_tx_option.flags & STM32_DMA_CCR_CIRC)) { /* Only enable interrupt if not in circular mode */ dma_enable_tc_interrupt_callback(DMAC_SPI_TX(port), - &tx_dma_done, - (void *)port); + &tx_dma_done, (void *)port); } #endif dma_go(tx); @@ -401,9 +401,10 @@ void pd_rx_start(int port) { /* start sampling the edges on the CC line using the RX timer */ dma_start_rx(&(pd_phy[port].dma_tim_option), PD_MAX_RAW_SIZE, - pd_phy[port].raw_samples); + pd_phy[port].raw_samples); /* enable TIM2 DMA requests */ - pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */; + pd_phy[port].tim_rx->egr = 0x0001; /* reset counter / reload PSC */ + ; pd_phy[port].tim_rx->sr = 0; /* clear overflows */ pd_phy[port].tim_rx->cr1 |= 1; } @@ -441,8 +442,8 @@ void pd_rx_disable_monitoring(int port) uint64_t get_time_since_last_edge(int port) { int prev_idx = (rx_edge_ts_idx[port] == 0) ? - PD_RX_TRANSITION_COUNT - 1 : - rx_edge_ts_idx[port] - 1; + PD_RX_TRANSITION_COUNT - 1 : + rx_edge_ts_idx[port] - 1; return get_time().val - rx_edge_ts[port][prev_idx].val; } @@ -467,11 +468,12 @@ void pd_rx_handler(void) if (pending & EXTI_COMP_MASK(i)) { rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val; next_idx = (rx_edge_ts_idx[i] == - PD_RX_TRANSITION_COUNT - 1) ? - 0 : rx_edge_ts_idx[i] + 1; + PD_RX_TRANSITION_COUNT - 1) ? + 0 : + rx_edge_ts_idx[i] + 1; -#if defined(CONFIG_LOW_POWER_IDLE) && \ -defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) +#if defined(CONFIG_LOW_POWER_IDLE) && \ + defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) /* * Do not deep sleep while waiting for more edges. For * most boards, sleep is already disabled due to being @@ -487,8 +489,8 @@ defined(CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED) * time, then trigger RX start. */ if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val - - rx_edge_ts[i][next_idx].val) - < PD_RX_TRANSITION_WINDOW) { + rx_edge_ts[i][next_idx].val) < + PD_RX_TRANSITION_WINDOW) { /* start sampling */ pd_rx_start(i); /* @@ -535,7 +537,7 @@ void pd_hw_init_rx(int port) phy->dma_tim_option.channel = DMAC_TIM_RX(port); phy->dma_tim_option.periph = (void *)(TIM_RX_CCR_REG(port)); phy->dma_tim_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_16_BIT; + STM32_DMA_CCR_PSIZE_16_BIT; /* --- set counter for RX timing : 2.4Mhz rate, free-running --- */ __hw_timer_enable_clock(TIM_CLOCK_PD_RX(port), 1); @@ -561,7 +563,8 @@ void pd_hw_init_rx(int port) phy->tim_rx->ccer = 0xB << ((TIM_RX_CCR_IDX(port) - 1) * 4); /* configure DMA request on CCRx update */ - phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */; + phy->tim_rx->dier |= 1 << (8 + TIM_RX_CCR_IDX(port)); /* CCxDE */ + ; /* set prescaler to /26 (F=1.2Mhz, T=0.8us) */ phy->tim_rx->psc = (clock_get_freq() / 2400000) - 1; /* Reload the pre-scaler and reset the counter (clear CCRx) */ @@ -590,18 +593,15 @@ void pd_hw_init_rx(int port) clock_wait_bus_cycles(BUS_APB, 1); /* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */ STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED | - STM32_COMP_CMP1INSEL_INM6 | - CMP1OUTSEL | - STM32_COMP_CMP1HYST_HI | - STM32_COMP_CMP2MODE_LSPEED | - STM32_COMP_CMP2INSEL_INM6 | - CMP2OUTSEL | + STM32_COMP_CMP1INSEL_INM6 | CMP1OUTSEL | + STM32_COMP_CMP1HYST_HI | STM32_COMP_CMP2MODE_LSPEED | + STM32_COMP_CMP2INSEL_INM6 | CMP2OUTSEL | STM32_COMP_CMP2HYST_HI; #elif defined(CHIP_FAMILY_STM32L) STM32_RCC_APB1ENR |= BIT(31); /* turn on COMP */ - STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1 - | STM32_COMP_SPEED_FAST; + STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | + STM32_COMP_INSEL_DAC_OUT1 | STM32_COMP_SPEED_FAST; /* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */ STM32_RI_ASCR2 |= BIT(4); #else @@ -638,9 +638,9 @@ void pd_hw_init(int port, enum pd_power_role role) phy->dma_tx_option.channel = DMAC_SPI_TX(port); phy->dma_tx_option.periph = (void *)&SPI_REGS(port)->dr; phy->dma_tx_option.flags = STM32_DMA_CCR_MSIZE_8_BIT | - STM32_DMA_CCR_PSIZE_8_BIT; + STM32_DMA_CCR_PSIZE_8_BIT; dma_prepare_tx(&(phy->dma_tx_option), PD_MAX_RAW_SIZE, - phy->raw_samples); + phy->raw_samples); /* configure registers used for timers */ phy->tim_tx = (void *)TIM_REG_TX(port); @@ -680,5 +680,5 @@ void pd_hw_init(int port, enum pd_power_role role) void pd_set_clock(int port, int freq) { - pd_phy[port].tim_tx->arr = clock_get_freq() / (2*freq); + pd_phy[port].tim_tx->arr = clock_get_freq() / (2 * freq); } -- cgit v1.2.1 From 47384389b12056bcbce19a1dd1f31351e6a52fee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:25 -0600 Subject: driver/retimer/nb7v904m.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe113e456c3ffee97216e7d3c358fe75559e689e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730055 Reviewed-by: Jeremy Bettis --- driver/retimer/nb7v904m.h | 147 +++++++++++++++++++++++----------------------- 1 file changed, 74 insertions(+), 73 deletions(-) diff --git a/driver/retimer/nb7v904m.h b/driver/retimer/nb7v904m.h index d19602153c..ed7bcc36ce 100644 --- a/driver/retimer/nb7v904m.h +++ b/driver/retimer/nb7v904m.h @@ -16,99 +16,99 @@ #define NB7V904M_I2C_ADDR2 0x1C /* Registers */ -#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00 -#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01 -#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03 -#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05 -#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07 -#define NB7V904M_REG_AUX_CH_CTRL 0x09 -#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18 -#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19 -#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a -#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b -#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c -#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d -#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e -#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f +#define NB7V904M_REG_GEN_DEV_SETTINGS 0x00 +#define NB7V904M_REG_CH_A_EQ_SETTINGS 0x01 +#define NB7V904M_REG_CH_B_EQ_SETTINGS 0x03 +#define NB7V904M_REG_CH_C_EQ_SETTINGS 0x05 +#define NB7V904M_REG_CH_D_EQ_SETTINGS 0x07 +#define NB7V904M_REG_AUX_CH_CTRL 0x09 +#define NB7V904M_REG_CH_A_FLAT_GAIN 0x18 +#define NB7V904M_REG_CH_A_LOSS_CTRL 0x19 +#define NB7V904M_REG_CH_B_FLAT_GAIN 0x1a +#define NB7V904M_REG_CH_B_LOSS_CTRL 0x1b +#define NB7V904M_REG_CH_C_FLAT_GAIN 0x1c +#define NB7V904M_REG_CH_C_LOSS_CTRL 0x1d +#define NB7V904M_REG_CH_D_FLAT_GAIN 0x1e +#define NB7V904M_REG_CH_D_LOSS_CTRL 0x1f /* 0x00 - General Device Settings */ -#define NB7V904M_CHIP_EN BIT(0) -#define NB7V904M_USB_DP_NORMAL BIT(1) +#define NB7V904M_CHIP_EN BIT(0) +#define NB7V904M_USB_DP_NORMAL BIT(1) #define NB7V904M_USB_DP_FLIPPED 0 -#define NB7V904M_DP_ONLY BIT(2) -#define NB7V904M_USB_ONLY (BIT(3) | BIT(1)) -#define NB7V904M_OP_MODE_MASK GENMASK(3, 1) -#define NB7V904M_CH_A_EN BIT(4) -#define NB7V904M_CH_B_EN BIT(5) -#define NB7V904M_CH_C_EN BIT(6) -#define NB7V904M_CH_D_EN BIT(7) -#define NB7V904M_CH_EN_MASK GENMASK(7, 4) +#define NB7V904M_DP_ONLY BIT(2) +#define NB7V904M_USB_ONLY (BIT(3) | BIT(1)) +#define NB7V904M_OP_MODE_MASK GENMASK(3, 1) +#define NB7V904M_CH_A_EN BIT(4) +#define NB7V904M_CH_B_EN BIT(5) +#define NB7V904M_CH_C_EN BIT(6) +#define NB7V904M_CH_D_EN BIT(7) +#define NB7V904M_CH_EN_MASK GENMASK(7, 4) /* 0x01 - Channel A Equalization Settings */ -#define NB7V904M_CH_A_EQ_0_DB 0x0a -#define NB7V904M_CH_A_EQ_2_DB 0x08 -#define NB7V904M_CH_A_EQ_4_DB 0x0e -#define NB7V904M_CH_A_EQ_6_DB 0x0c -#define NB7V904M_CH_A_EQ_8_DB 0x02 -#define NB7V904M_CH_A_EQ_10_DB 0x00 +#define NB7V904M_CH_A_EQ_0_DB 0x0a +#define NB7V904M_CH_A_EQ_2_DB 0x08 +#define NB7V904M_CH_A_EQ_4_DB 0x0e +#define NB7V904M_CH_A_EQ_6_DB 0x0c +#define NB7V904M_CH_A_EQ_8_DB 0x02 +#define NB7V904M_CH_A_EQ_10_DB 0x00 /* 0x03 - Channel B Equalization Settings */ -#define NB7V904M_CH_B_EQ_0_DB 0x0e -#define NB7V904M_CH_B_EQ_2_DB 0x0c -#define NB7V904M_CH_B_EQ_4_DB 0x0a -#define NB7V904M_CH_B_EQ_6_DB 0x08 -#define NB7V904M_CH_B_EQ_8_DB 0x06 -#define NB7V904M_CH_B_EQ_10_DB 0x00 +#define NB7V904M_CH_B_EQ_0_DB 0x0e +#define NB7V904M_CH_B_EQ_2_DB 0x0c +#define NB7V904M_CH_B_EQ_4_DB 0x0a +#define NB7V904M_CH_B_EQ_6_DB 0x08 +#define NB7V904M_CH_B_EQ_8_DB 0x06 +#define NB7V904M_CH_B_EQ_10_DB 0x00 /* 0x05 - Channel C Equalization Settings */ -#define NB7V904M_CH_C_EQ_0_DB 0x0e -#define NB7V904M_CH_C_EQ_2_DB 0x0c -#define NB7V904M_CH_C_EQ_4_DB 0x0a -#define NB7V904M_CH_C_EQ_6_DB 0x08 -#define NB7V904M_CH_C_EQ_8_DB 0x06 -#define NB7V904M_CH_C_EQ_10_DB 0x00 +#define NB7V904M_CH_C_EQ_0_DB 0x0e +#define NB7V904M_CH_C_EQ_2_DB 0x0c +#define NB7V904M_CH_C_EQ_4_DB 0x0a +#define NB7V904M_CH_C_EQ_6_DB 0x08 +#define NB7V904M_CH_C_EQ_8_DB 0x06 +#define NB7V904M_CH_C_EQ_10_DB 0x00 /* 0x07 - Channel D Equalization Settings */ -#define NB7V904M_CH_D_EQ_0_DB 0x0a -#define NB7V904M_CH_D_EQ_2_DB 0x08 -#define NB7V904M_CH_D_EQ_4_DB 0x0e -#define NB7V904M_CH_D_EQ_6_DB 0x0c -#define NB7V904M_CH_D_EQ_8_DB 0x02 -#define NB7V904M_CH_D_EQ_10_DB 0x00 +#define NB7V904M_CH_D_EQ_0_DB 0x0a +#define NB7V904M_CH_D_EQ_2_DB 0x08 +#define NB7V904M_CH_D_EQ_4_DB 0x0e +#define NB7V904M_CH_D_EQ_6_DB 0x0c +#define NB7V904M_CH_D_EQ_8_DB 0x02 +#define NB7V904M_CH_D_EQ_10_DB 0x00 /* 0x09 - Auxiliary Channel Control */ -#define NB7V904M_AUX_CH_NORMAL 0 -#define NB7V904M_AUX_CH_FLIPPED BIT(0) -#define NB7V904M_AUX_CH_HI_Z BIT(1) +#define NB7V904M_AUX_CH_NORMAL 0 +#define NB7V904M_AUX_CH_FLIPPED BIT(0) +#define NB7V904M_AUX_CH_HI_Z BIT(1) /* 0x18 - Channel A Flag Gain */ -#define NB7V904M_CH_A_GAIN_0_DB 0x00 -#define NB7V904M_CH_A_GAIN_1P5_DB 0x02 -#define NB7V904M_CH_A_GAIN_3P5_DB 0x03 +#define NB7V904M_CH_A_GAIN_0_DB 0x00 +#define NB7V904M_CH_A_GAIN_1P5_DB 0x02 +#define NB7V904M_CH_A_GAIN_3P5_DB 0x03 /* 0x1a - Channel B Flag Gain */ -#define NB7V904M_CH_B_GAIN_0_DB 0x03 -#define NB7V904M_CH_B_GAIN_1P5_DB 0x01 -#define NB7V904M_CH_B_GAIN_3P5_DB 0x00 +#define NB7V904M_CH_B_GAIN_0_DB 0x03 +#define NB7V904M_CH_B_GAIN_1P5_DB 0x01 +#define NB7V904M_CH_B_GAIN_3P5_DB 0x00 /* 0x1c - Channel C Flag Gain */ -#define NB7V904M_CH_C_GAIN_0_DB 0x03 -#define NB7V904M_CH_C_GAIN_1P5_DB 0x01 -#define NB7V904M_CH_C_GAIN_3P5_DB 0x00 +#define NB7V904M_CH_C_GAIN_0_DB 0x03 +#define NB7V904M_CH_C_GAIN_1P5_DB 0x01 +#define NB7V904M_CH_C_GAIN_3P5_DB 0x00 /* 0x1e - Channel D Flag Gain */ -#define NB7V904M_CH_D_GAIN_0_DB 0x00 -#define NB7V904M_CH_D_GAIN_1P5_DB 0x02 -#define NB7V904M_CH_D_GAIN_3P5_DB 0x03 +#define NB7V904M_CH_D_GAIN_0_DB 0x00 +#define NB7V904M_CH_D_GAIN_1P5_DB 0x02 +#define NB7V904M_CH_D_GAIN_3P5_DB 0x03 /* 0x19 - Channel A Loss Profile Matching Control */ /* 0x1b - Channel B Loss Profile Matching Control */ /* 0x1d - Channel C Loss Profile Matching Control */ /* 0x1f - Channel D Loss Profile Matching Control */ -#define NB7V904M_LOSS_PROFILE_A 0x00 -#define NB7V904M_LOSS_PROFILE_B 0x01 -#define NB7V904M_LOSS_PROFILE_C 0x02 -#define NB7V904M_LOSS_PROFILE_D 0x03 +#define NB7V904M_LOSS_PROFILE_A 0x00 +#define NB7V904M_LOSS_PROFILE_B 0x01 +#define NB7V904M_LOSS_PROFILE_C 0x02 +#define NB7V904M_LOSS_PROFILE_D 0x03 extern const struct usb_mux_driver nb7v904m_usb_redriver_drv; #ifdef CONFIG_NB7V904M_LPM_OVERRIDE @@ -116,18 +116,19 @@ extern int nb7v904m_lpm_disable; #endif /* Use this value if tuning eq wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_EQ 0xff +#define NB7V904M_CH_ALL_SKIP_EQ 0xff int nb7v904m_tune_usb_set_eq(const struct usb_mux *me, uint8_t eq_a, - uint8_t eq_b, uint8_t eq_c, uint8_t eq_d); + uint8_t eq_b, uint8_t eq_c, uint8_t eq_d); /* Use this value if tuning gain wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_GAIN 0xff +#define NB7V904M_CH_ALL_SKIP_GAIN 0xff int nb7v904m_tune_usb_flat_gain(const struct usb_mux *me, uint8_t gain_a, - uint8_t gain_b, uint8_t gain_c, uint8_t gain_d); + uint8_t gain_b, uint8_t gain_c, uint8_t gain_d); /* Use this value if loss profile control wants to be skipped */ -#define NB7V904M_CH_ALL_SKIP_LOSS 0xff +#define NB7V904M_CH_ALL_SKIP_LOSS 0xff /* Control channel Loss Profile Matching */ int nb7v904m_set_loss_profile_match(const struct usb_mux *me, uint8_t loss_a, - uint8_t loss_b, uint8_t loss_c, uint8_t loss_d); + uint8_t loss_b, uint8_t loss_c, + uint8_t loss_d); /* Control mapping between AUX and SBU */ int nb7v904m_set_aux_ch_switch(const struct usb_mux *me, uint8_t aux_ch); #endif /* __CROS_EC_USB_REDRIVER_NB7V904M_H */ -- cgit v1.2.1 From d527a47bb3bc8696f3bc8d9834464ee71dc8b899 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:07 -0600 Subject: board/redrix/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1620cb5e4a1e7fb562f58fee97a157eb207668d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728879 Reviewed-by: Jeremy Bettis --- board/redrix/keyboard.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/redrix/keyboard.c b/board/redrix/keyboard.c index e1a5381a6c..d491633ed3 100644 --- a/board/redrix/keyboard.c +++ b/board/redrix/keyboard.c @@ -74,7 +74,6 @@ board_vivaldi_keybd_config(void) return &keybd2; } - #ifdef CONFIG_KEYBOARD_FACTORY_TEST /* * Map keyboard connector pins to EC GPIO pins for factory test. @@ -82,13 +81,13 @@ board_vivaldi_keybd_config(void) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 5c7b454753ecb436fbec229a20a1c4f50acb20dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:48 -0600 Subject: chip/npcx/spiflashfw/monitor_hdr.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc0d750af5b7185be0f06048a1a148cad4112d2c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729436 Reviewed-by: Jeremy Bettis --- chip/npcx/spiflashfw/monitor_hdr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c index 219a037d27..42d4720d97 100644 --- a/chip/npcx/spiflashfw/monitor_hdr.c +++ b/chip/npcx/spiflashfw/monitor_hdr.c @@ -20,7 +20,7 @@ const struct monitor_header_tag monitor_hdr = { * programed into the SPI flash. */ CONFIG_PROGRAM_MEMORY_BASE, - /* 0x0C:The Flash start address to be programmed*/ +/* 0x0C:The Flash start address to be programmed*/ #ifdef SECTION_IS_RO /* Default: RO image is programed from the start of SPI flash */ CONFIG_EC_PROTECTED_STORAGE_OFF, -- cgit v1.2.1 From c5e7b19e411857a035013d931cffbe69b5314ee4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:57 -0600 Subject: board/adlrvpp_mchp1521/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1562237b8b4db2fb95183f80233c0b2f4e4e71b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727964 Reviewed-by: Jeremy Bettis --- board/adlrvpp_mchp1521/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/adlrvpp_mchp1521/board.c b/board/adlrvpp_mchp1521/board.c index 7a51d0cbd9..4a2f20f27c 100644 --- a/board/adlrvpp_mchp1521/board.c +++ b/board/adlrvpp_mchp1521/board.c @@ -105,6 +105,6 @@ BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT); /* SPI devices */ const struct spi_device_t spi_devices[] = { - { QMSPI0_PORT, 4, GPIO_QMSPI_CS0}, + { QMSPI0_PORT, 4, GPIO_QMSPI_CS0 }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -- cgit v1.2.1 From 4b69cd310c94bd2b4cd2a961bccd2617aded0f97 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:50 -0600 Subject: board/elemi/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2a3f1f1a03dcb27fb22d5af6e8310ae1fe74fbd8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728309 Reviewed-by: Jeremy Bettis --- board/elemi/board.c | 49 ++++++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/board/elemi/board.c b/board/elemi/board.c index 1aaf5e1d95..e5a4012ec1 100644 --- a/board/elemi/board.c +++ b/board/elemi/board.c @@ -42,7 +42,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -72,7 +72,7 @@ union volteer_cbi_fw_config fw_config_defaults = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -101,8 +101,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(68), \ [EC_TEMP_THRESH_HALT] = C_TO_K(70), \ @@ -118,8 +118,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -136,8 +136,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_REGULATOR \ - { \ +#define THERMAL_REGULATOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(68), \ [EC_TEMP_THRESH_HALT] = C_TO_K(70), \ @@ -248,8 +248,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT); __override void board_ps8xxx_tcpc_init(int port) { /* b/189587527: Set Displayport EQ loss up to 10dB */ - tcpc_addr_write(port, PS8XXX_I2C_ADDR1_P1_FLAGS, - PS8815_REG_DP_EQ_SETTING, + tcpc_addr_write( + port, PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_DP_EQ_SETTING, PS8815_DPEQ_LOSS_UP_10DB << PS8815_REG_DP_EQ_COMP_SHIFT); } @@ -277,8 +277,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -289,16 +288,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -308,7 +307,7 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ ps8815_reset(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } __override void board_cbi_init(void) @@ -458,13 +457,13 @@ int ppc_get_alert_status(int port) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 2f1fbfe98ca4f80ccb763a9afe01fc173e085bc0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:35 -0600 Subject: board/tigertail/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I56690e0c7c81a03f765447a2f44ddd91d1df8954 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729020 Reviewed-by: Jeremy Bettis --- board/tigertail/board.c | 97 +++++++++++++++++++++---------------------------- 1 file changed, 41 insertions(+), 56 deletions(-) diff --git a/board/tigertail/board.c b/board/tigertail/board.c index e7679a125d..dd872726db 100644 --- a/board/tigertail/board.c +++ b/board/tigertail/board.c @@ -27,16 +27,14 @@ #include "gpio_list.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 /****************************************************************************** * Forward USART1 as a simple USB serial interface. @@ -44,43 +42,33 @@ static struct usart_config const usart1; struct usb_stream_config const usart1_usb; -static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t, - usart1.producer, usart1_usb.consumer); -static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t, - usart1_usb.producer, usart1.consumer); +static struct queue const usart1_to_usb = + QUEUE_DIRECT(64, uint8_t, usart1.producer, usart1_usb.consumer); +static struct queue const usb_to_usart1 = + QUEUE_DIRECT(64, uint8_t, usart1_usb.producer, usart1.consumer); static struct usart_config const usart1 = - USART_CONFIG(usart1_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart1_to_usb, - usb_to_usart1); - -USB_STREAM_CONFIG(usart1_usb, - USB_IFACE_USART1_STREAM, - USB_STR_USART1_STREAM_NAME, - USB_EP_USART1_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart1, - usart1_to_usb) + USART_CONFIG(usart1_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart1_to_usb, usb_to_usart1); +USB_STREAM_CONFIG(usart1_usb, USB_IFACE_USART1_STREAM, + USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart1, + usart1_to_usb) /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Tigertail"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("DUT UART"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Tigertail"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("DUT UART"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Tigertail Console"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -90,30 +78,29 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); */ /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_SBU1] = {"SBU1", 3300, 4096, 0, STM32_AIN(6)}, - [ADC_SBU2] = {"SBU2", 3300, 4096, 0, STM32_AIN(7)}, + [ADC_SBU1] = { "SBU1", 3300, 4096, 0, STM32_AIN(6) }, + [ADC_SBU2] = { "SBU2", 3300, 4096, 0, STM32_AIN(7) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - - /****************************************************************************** * Support I2C bridging over USB. */ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Console commands. @@ -138,7 +125,7 @@ static void set_uart_gpios(int state) { int uart = GPIO_INPUT; int dir = 0; - int voltage = 1; /* 1: 1.8v, 0: 3.3v */ + int voltage = 1; /* 1: 1.8v, 0: 3.3v */ int enabled = 0; gpio_set_level(GPIO_ST_UART_LVL_DIS, 1); @@ -287,7 +274,7 @@ void set_uart_state(int state) */ void uart_sbu_tick(void) { - static int debounce; /* = 0 */ + static int debounce; /* = 0 */ if (uart_detect != UART_DETECT_AUTO) return; @@ -349,15 +336,15 @@ static int command_uart(int argc, char **argv) uart_state_str = uart_state_names[uart_state]; if (uart_detect == UART_DETECT_AUTO) uart_detect_str = "auto"; - ccprintf("UART mux is: %s, setting: %s\n", - uart_state_str, uart_detect_str); + ccprintf("UART mux is: %s, setting: %s\n", uart_state_str, + uart_detect_str); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(uart, command_uart, - "[off|on18|on33|flip18|flip33|auto]", - "Set the sbu uart state\n" - "WARNING: 3.3v may damage 1.8v devices.\n"); + "[off|on18|on33|flip18|flip33|auto]", + "Set the sbu uart state\n" + "WARNING: 3.3v may damage 1.8v devices.\n"); static void set_led_a(int r, int g, int b) { @@ -422,7 +409,6 @@ void set_mux_state(int state) set_led_b(1, 0, 0); } - /* On button press, toggle between mux A, B, off. */ static int button_ready = 1; void button_interrupt_deferred(void) @@ -484,9 +470,8 @@ static int command_mux(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(mux, command_mux, - "[off|A|B]", - "Get/set the mux and enable state of the TYPE-C mux"); +DECLARE_CONSOLE_COMMAND(mux, command_mux, "[off|A|B]", + "Get/set the mux and enable state of the TYPE-C mux"); /****************************************************************************** * Initialize board. -- cgit v1.2.1 From b35cdfc21c7a3a84755c9fa2cf1298f4762cdf6f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:45 -0600 Subject: board/wheelie/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f2f215e387347ee4a5a76a240e0f925c910fc2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729114 Reviewed-by: Jeremy Bettis --- board/wheelie/board.h | 47 ++++++++++++++++++----------------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/board/wheelie/board.h b/board/wheelie/board.h index 194c49adb6..91bc9a21e6 100644 --- a/board/wheelie/board.h +++ b/board/wheelie/board.h @@ -22,12 +22,12 @@ #define CONFIG_BC12_DETECT_PI3USB9201 /* Charger */ -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ -#define CONFIG_FPU /* For charger calculations */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_FPU /* For charger calculations */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP /* LED */ #define CONFIG_LED_PWM @@ -37,9 +37,9 @@ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ -#define CONFIG_SYNC /* Camera VSYNC */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_SYNC /* Camera VSYNC */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ @@ -56,8 +56,7 @@ #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #define CONFIG_TABLET_MODE #define CONFIG_TABLET_MODE_SWITCH @@ -65,8 +64,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 /* Thermistors */ @@ -75,10 +74,10 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ -#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ #ifndef __ASSEMBLER__ @@ -100,28 +99,18 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - VSYNC, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 49af044679eb342ad12728ad96d7dc11c79cb62b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:06 -0600 Subject: zephyr/drivers/cros_kblight/pwm_kblight.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8c392951a620445dab6dcdada4d7585a02bf5f9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730673 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_kblight/pwm_kblight.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/drivers/cros_kblight/pwm_kblight.c b/zephyr/drivers/cros_kblight/pwm_kblight.c index b57adff26d..b6695bbecf 100644 --- a/zephyr/drivers/cros_kblight/pwm_kblight.c +++ b/zephyr/drivers/cros_kblight/pwm_kblight.c @@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define KBLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0) #define KBLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0) #define KBLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0) -#define KBLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency)) +#define KBLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC / DT_INST_PROP(0, frequency)) static bool kblight_enabled; static int kblight_percent; @@ -39,8 +39,8 @@ static void kblight_pwm_set_duty(int percent) pulse_ns = DIV_ROUND_NEAREST(KBLIGHT_PWM_PERIOD_NS * percent, 100); - LOG_DBG("kblight PWM %s set percent (%d), pulse %d", - pwm_dev->name, percent, pulse_ns); + LOG_DBG("kblight PWM %s set percent (%d), pulse %d", pwm_dev->name, + percent, pulse_ns); rv = pwm_set(pwm_dev, KBLIGHT_PWM_CHANNEL, KBLIGHT_PWM_PERIOD_NS, pulse_ns, KBLIGHT_PWM_FLAGS); -- cgit v1.2.1 From 8ae681f521f4cbe708535759ca803e6534b447ee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:13 -0600 Subject: board/nucleo-h743zi/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I48f3b06b1b12e20b95a938ec78720906e41b4245 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728784 Reviewed-by: Jeremy Bettis --- board/nucleo-h743zi/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/nucleo-h743zi/board.h b/board/nucleo-h743zi/board.h index 966f2a8c94..a3dd376c12 100644 --- a/board/nucleo-h743zi/board.h +++ b/board/nucleo-h743zi/board.h @@ -28,6 +28,6 @@ * Enable the blink example that exercises the LEDs. */ #define CONFIG_BLINK -#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3 +#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3 #endif /* __BOARD_H */ -- cgit v1.2.1 From 7bedbad8b1fd99b3e4f281d61705a7ce1cb4fc29 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:38 -0600 Subject: board/homestar/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94ad3760708757f4c123619fbbb926c3bf304509 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728470 Reviewed-by: Jeremy Bettis --- board/homestar/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/homestar/led.c b/board/homestar/led.c index 3950ce1ec0..f9eab763b3 100644 --- a/board/homestar/led.c +++ b/board/homestar/led.c @@ -36,15 +36,15 @@ enum led_color { LED_RED, LED_GREEN, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, - (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_G_C0, - (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); if (color == LED_AMBER) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON); gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON); @@ -86,13 +86,13 @@ static void board_led_set_battery(void) case PWR_STATE_CHARGE: case PWR_STATE_CHARGE_NEAR_FULL: if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND | - CHIPSET_STATE_ANY_OFF)) { + CHIPSET_STATE_ANY_SUSPEND | + CHIPSET_STATE_ANY_OFF)) { if (percent <= BATTERY_LEVEL_CRITICAL) { /* battery capa <= 5%, Red */ color = LED_RED; } else if (percent > BATTERY_LEVEL_CRITICAL && - percent < BATTERY_LEVEL_NEAR_FULL) { + percent < BATTERY_LEVEL_NEAR_FULL) { /* 5% < battery capa < 97%, Orange */ color = LED_AMBER; } else { @@ -147,7 +147,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state) enum led_color color; if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) && - (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) + (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) return; if (state == LED_STATE_RESET) { -- cgit v1.2.1 From 2a628b96ec200319cdc94e3359e809c592d461e5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:58 -0600 Subject: board/nipperkin/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc329b6d127d2f0087fa0b0140f67248bfa3e86f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728755 Reviewed-by: Jeremy Bettis --- board/nipperkin/thermal.c | 100 ++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 53 deletions(-) diff --git a/board/nipperkin/thermal.c b/board/nipperkin/thermal.c index eecf23a9e3..9574de4ca0 100644 --- a/board/nipperkin/thermal.c +++ b/board/nipperkin/thermal.c @@ -18,7 +18,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, @@ -59,52 +59,51 @@ struct fan_step { static const struct fan_step fan_step_table[] = { { /* level 0 */ - .on = {51, 0, 44, -1, -1, -1}, - .off = {99, 99, 99, -1, -1, -1}, - .rpm = {0}, + .on = { 51, 0, 44, -1, -1, -1 }, + .off = { 99, 99, 99, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {52, 0, 47, -1, -1, -1}, - .off = {50, 99, 43, -1, -1, -1}, - .rpm = {3000}, + .on = { 52, 0, 47, -1, -1, -1 }, + .off = { 50, 99, 43, -1, -1, -1 }, + .rpm = { 3000 }, }, { /* level 2 */ - .on = {53, 0, 49, -1, -1, -1}, - .off = {51, 99, 45, -1, -1, -1}, - .rpm = {3400}, + .on = { 53, 0, 49, -1, -1, -1 }, + .off = { 51, 99, 45, -1, -1, -1 }, + .rpm = { 3400 }, }, { /* level 3 */ - .on = {54, 0, 51, -1, -1, -1}, - .off = {52, 99, 47, -1, -1, -1}, - .rpm = {3800}, + .on = { 54, 0, 51, -1, -1, -1 }, + .off = { 52, 99, 47, -1, -1, -1 }, + .rpm = { 3800 }, }, { /* level 4 */ - .on = {56, 50, 53, -1, -1, -1}, - .off = {53, 47, 49, -1, -1, -1}, - .rpm = {4100}, + .on = { 56, 50, 53, -1, -1, -1 }, + .off = { 53, 47, 49, -1, -1, -1 }, + .rpm = { 4100 }, }, { /* level 5 */ - .on = {57, 52, 55, -1, -1, -1}, - .off = {55, 49, 51, -1, -1, -1}, - .rpm = {4400}, + .on = { 57, 52, 55, -1, -1, -1 }, + .off = { 55, 49, 51, -1, -1, -1 }, + .rpm = { 4400 }, }, { /* level 6 */ - .on = {100, 100, 100, -1, -1, -1}, - .off = {56, 51, 53, -1, -1, -1}, - .rpm = {4900}, + .on = { 100, 100, 100, -1, -1, -1 }, + .off = { 56, 51, 53, -1, -1, -1 }, + .rpm = { 4900 }, }, }; #define NUM_FAN_LEVELS ARRAY_SIZE(fan_step_table) -BUILD_ASSERT(ARRAY_SIZE(fan_step_table) == - ARRAY_SIZE(fan_step_table)); +BUILD_ASSERT(ARRAY_SIZE(fan_step_table) == ARRAY_SIZE(fan_step_table)); int fan_table_to_rpm(int fan, int *temp) { @@ -121,30 +120,29 @@ int fan_table_to_rpm(int fan, int *temp) * 3. invariant path. (return the current RPM) */ if (temp[TEMP_SENSOR_CHARGER] < prev_tmp[TEMP_SENSOR_CHARGER] || - temp[TEMP_SENSOR_MEMORY] < prev_tmp[TEMP_SENSOR_MEMORY] || - temp[TEMP_SENSOR_SOC] < prev_tmp[TEMP_SENSOR_SOC]) { + temp[TEMP_SENSOR_MEMORY] < prev_tmp[TEMP_SENSOR_MEMORY] || + temp[TEMP_SENSOR_SOC] < prev_tmp[TEMP_SENSOR_SOC]) { for (i = current_level; i > 0; i--) { if (temp[TEMP_SENSOR_CHARGER] < - fan_step_table[i].off[TEMP_SENSOR_CHARGER] && - temp[TEMP_SENSOR_MEMORY] < - fan_step_table[i].off[TEMP_SENSOR_MEMORY] && - temp[TEMP_SENSOR_SOC] < - fan_step_table[i].off[TEMP_SENSOR_SOC]) { + fan_step_table[i].off[TEMP_SENSOR_CHARGER] && + temp[TEMP_SENSOR_MEMORY] < + fan_step_table[i].off[TEMP_SENSOR_MEMORY] && + temp[TEMP_SENSOR_SOC] < + fan_step_table[i].off[TEMP_SENSOR_SOC]) { current_level = i - 1; } else break; } } else if (temp[TEMP_SENSOR_CHARGER] > prev_tmp[TEMP_SENSOR_CHARGER] || - temp[TEMP_SENSOR_MEMORY] - > prev_tmp[TEMP_SENSOR_MEMORY] || - temp[TEMP_SENSOR_SOC] > prev_tmp[TEMP_SENSOR_SOC]) { + temp[TEMP_SENSOR_MEMORY] > prev_tmp[TEMP_SENSOR_MEMORY] || + temp[TEMP_SENSOR_SOC] > prev_tmp[TEMP_SENSOR_SOC]) { for (i = current_level; i < NUM_FAN_LEVELS; i++) { if ((temp[TEMP_SENSOR_CHARGER] > - fan_step_table[i].on[TEMP_SENSOR_CHARGER] && - temp[TEMP_SENSOR_MEMORY] > - fan_step_table[i].on[TEMP_SENSOR_MEMORY]) || - temp[TEMP_SENSOR_SOC] > - fan_step_table[i].on[TEMP_SENSOR_SOC]) { + fan_step_table[i].on[TEMP_SENSOR_CHARGER] && + temp[TEMP_SENSOR_MEMORY] > + fan_step_table[i].on[TEMP_SENSOR_MEMORY]) || + temp[TEMP_SENSOR_SOC] > + fan_step_table[i].on[TEMP_SENSOR_SOC]) { current_level = i + 1; } else break; @@ -167,15 +165,12 @@ int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } - struct chg_curr_step { int on; int off; @@ -183,12 +178,11 @@ struct chg_curr_step { }; static const struct chg_curr_step chg_curr_table[] = { - {.on = 0, .off = 0, .curr_ma = 3566}, - {.on = 66, .off = 65, .curr_ma = 2500}, - {.on = 70, .off = 69, .curr_ma = 1500}, + { .on = 0, .off = 0, .curr_ma = 3566 }, + { .on = 66, .off = 65, .curr_ma = 2500 }, + { .on = 70, .off = 69, .curr_ma = 1500 }, }; - #define NUM_CHG_CURRENT_LEVELS ARRAY_SIZE(chg_curr_table) int charger_profile_override(struct charge_state_data *curr) @@ -200,7 +194,6 @@ int charger_profile_override(struct charge_state_data *curr) static int current_level; static int prev_tmp; - if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE)) return 0; @@ -214,12 +207,13 @@ int charger_profile_override(struct charge_state_data *curr) if (chipset_in_state(CHIPSET_STATE_ON)) { if (chg_temp_c < prev_tmp) { - if ((chg_temp_c <= chg_curr_table[current_level].off) - && (current_level > 0)) + if ((chg_temp_c <= chg_curr_table[current_level].off) && + (current_level > 0)) current_level -= 1; } else if (chg_temp_c > prev_tmp) { - if ((chg_temp_c >= chg_curr_table[current_level + 1].on) - && (current_level < NUM_CHG_CURRENT_LEVELS - 1)) + if ((chg_temp_c >= + chg_curr_table[current_level + 1].on) && + (current_level < NUM_CHG_CURRENT_LEVELS - 1)) current_level += 1; } -- cgit v1.2.1 From 9f1166415a4a369f8e838db6ecc9b219a3516f52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:41 -0600 Subject: chip/ish/host_command_heci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic96238d4f78bc6355d541c31db8666f9d268ba31 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729180 Reviewed-by: Jeremy Bettis --- chip/ish/host_command_heci.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/chip/ish/host_command_heci.c b/chip/ish/host_command_heci.c index de1485417b..cec72063b4 100644 --- a/chip/ish/host_command_heci.c +++ b/chip/ish/host_command_heci.c @@ -13,11 +13,16 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) - -#define HECI_CLIENT_CROS_EC_ISH_GUID { 0x7b7154d0, 0x56f4, 0x4bdc,\ - { 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 } } +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) + +#define HECI_CLIENT_CROS_EC_ISH_GUID \ + { \ + 0x7b7154d0, 0x56f4, 0x4bdc, \ + { \ + 0xb0, 0xd8, 0x9e, 0x7c, 0xda, 0xe0, 0xd6, 0xa0 \ + } \ + } /* Handle for all heci cros_ec interactions */ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE; @@ -33,7 +38,7 @@ static heci_handle_t heci_cros_ec_handle = HECI_INVALID_HANDLE; struct cros_ec_ishtp_msg_hdr { uint8_t channel; uint8_t status; - uint8_t id; /* Pairs up request and responses */ + uint8_t id; /* Pairs up request and responses */ uint8_t reserved; } __ec_align4; @@ -88,10 +93,11 @@ static void heci_send_hostcmd_response(struct host_packet *pkt) } static void cros_ec_ishtp_subsys_new_msg_received(const heci_handle_t handle, - uint8_t *msg, const size_t msg_size) + uint8_t *msg, + const size_t msg_size) { - struct cros_ec_ishtp_msg *in = (void *) msg; - struct cros_ec_ishtp_msg *out = (void *) response_buffer; + struct cros_ec_ishtp_msg *in = (void *)msg; + struct cros_ec_ishtp_msg *out = (void *)response_buffer; if (in->hdr.channel != CROS_EC_COMMAND) { CPRINTS("Unknown HECI packet 0x%02x", in->hdr.channel); @@ -140,7 +146,7 @@ static enum ec_status heci_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, heci_get_protocol_info, -EC_VER_MASK(0)); + EC_VER_MASK(0)); static int cros_ec_ishtp_subsys_initialize(const heci_handle_t heci_handle) { -- cgit v1.2.1 From ccfdb4774e9a375804e3b095e92c0ec12f4dfabe Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Tue, 21 Jun 2022 13:33:47 -0700 Subject: zephyr/shim: Create bb_controls if BB or HB retimer is present Meteorlake adds the Hayden Bridge Retimer which uses the same driver and control logic as Burnside Bridge retimer does, hence create the struct if either of the retimers are chosen. BUG=b:229073490 BRANCH=none TEST=zmake testall/zmake mtlrvpp_npcx and verify retimer function Signed-off-by: Brandon Breitenstein Change-Id: I0e155a1248d1978f599d191f77f246292255ac7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716789 Reviewed-by: Yuval Peress Reviewed-by: Vijay P Hiremath --- zephyr/shim/src/usb_muxes.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/src/usb_muxes.c b/zephyr/shim/src/usb_muxes.c index f96146258a..188499aa30 100644 --- a/zephyr/shim/src/usb_muxes.c +++ b/zephyr/shim/src/usb_muxes.c @@ -58,8 +58,9 @@ MAYBE_CONST struct usb_mux usb_muxes[] = { */ USB_MUX_FOREACH_USBC_PORT(USB_MUX_NO_FIRST, USB_MUX_DEFINE) -/* Create bb_controls only if BB retimer driver is enabled */ -#ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB +/* Create bb_controls only if BB or HB retimer driver is enabled */ +#if defined(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB) || \ + defined(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB) /** * @brief bb_controls array should be constant only if configuration cannot * change in runtime @@ -80,6 +81,6 @@ USB_MUX_FOREACH_USBC_PORT(USB_MUX_NO_FIRST, USB_MUX_DEFINE) BB_CONTROLS_CONST struct bb_usb_control bb_controls[] = { USB_MUX_FOREACH_USBC_PORT(USB_MUX_BB_RETIMERS, USB_MUX_ARRAY) }; -#endif /* CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB */ +#endif /* CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB/HB */ #endif /* #if USB_MUX_FOREACH_USBC_PORT(USB_MUX_PORT_HAS_MUX, _) */ -- cgit v1.2.1 From 53ba6961bab837344943efb9cbec5097aaa4b594 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:55 -0600 Subject: board/host/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc5ef3c19b74053ed00a281952179fca9b93a93f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728473 Reviewed-by: Jeremy Bettis --- board/host/usb_pd_pdo.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/host/usb_pd_pdo.c b/board/host/usb_pd_pdo.c index a84b03f75f..f820f6bec5 100644 --- a/board/host/usb_pd_pdo.c +++ b/board/host/usb_pd_pdo.c @@ -10,14 +10,14 @@ #define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP) const uint32_t pd_src_pdo[] = { - PDO_FIXED(5000, 900, PDO_FIXED_FLAGS), - PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), + PDO_FIXED(5000, 900, PDO_FIXED_FLAGS), + PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS), }; const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), - PDO_BATT(4750, 21000, 15000), - PDO_VAR(4750, 21000, 3000), + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); -- cgit v1.2.1 From cb8f08dc33ae1657346fd452aba71332ad2ca1a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:25 -0600 Subject: extra/lightbar/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c49fd1d51d8ea32d570ad51149116ad7e512d73 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730181 Reviewed-by: Jeremy Bettis --- extra/lightbar/main.c | 110 ++++++++++++++++++++++++++++---------------------- 1 file changed, 62 insertions(+), 48 deletions(-) diff --git a/extra/lightbar/main.c b/extra/lightbar/main.c index ef011d35f1..dc4c3d59d8 100644 --- a/extra/lightbar/main.c +++ b/extra/lightbar/main.c @@ -55,7 +55,7 @@ void *entry_lightbar(void *ptr) /* timespec uses nanoseconds */ #define TS_USEC 1000L #define TS_MSEC 1000000L -#define TS_SEC 1000000000L +#define TS_SEC 1000000000L static void timespec_incr(struct timespec *v, time_t secs, long nsecs) { @@ -66,7 +66,6 @@ static void timespec_incr(struct timespec *v, time_t secs, long nsecs) v->tv_nsec %= TS_SEC; } - static pthread_mutex_t task_mutex = PTHREAD_MUTEX_INITIALIZER; static pthread_cond_t task_cond = PTHREAD_COND_INITIALIZER; static uint32_t task_event; @@ -82,8 +81,8 @@ uint32_t task_wait_event(int timeout_us) clock_gettime(CLOCK_REALTIME, &t); timespec_incr(&t, timeout_us / SECOND, timeout_us * TS_USEC); - if (ETIMEDOUT == pthread_cond_timedwait(&task_cond, - &task_mutex, &t)) + if (ETIMEDOUT == + pthread_cond_timedwait(&task_cond, &task_mutex, &t)) task_event |= TASK_EVENT_TIMER; } else { pthread_cond_wait(&task_cond, &task_mutex); @@ -96,7 +95,7 @@ uint32_t task_wait_event(int timeout_us) } void task_set_event(task_id_t tskid, /* always LIGHTBAR */ - uint32_t event) + uint32_t event) { pthread_mutex_lock(&task_mutex); task_event = event; @@ -104,8 +103,6 @@ void task_set_event(task_id_t tskid, /* always LIGHTBAR */ pthread_mutex_unlock(&task_mutex); } - - /* Stubbed functions */ void cprintf(int zero, const char *fmt, ...) @@ -146,7 +143,7 @@ timestamp_t get_time(void) clock_gettime(CLOCK_REALTIME, &t_start); clock_gettime(CLOCK_REALTIME, &t); ret.val = (t.tv_sec - t_start.tv_sec) * SECOND + - (t.tv_nsec - t_start.tv_nsec) / TS_USEC; + (t.tv_nsec - t_start.tv_nsec) / TS_USEC; return ret; } @@ -162,8 +159,7 @@ uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size) } /* Copied from util/ectool.c */ -int lb_read_params_from_file(const char *filename, - struct lightbar_params_v1 *p) +int lb_read_params_from_file(const char *filename, struct lightbar_params_v1 *p) { FILE *fp; char buf[80]; @@ -175,46 +171,65 @@ int lb_read_params_from_file(const char *filename, fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } /* We must read the correct number of params from each line */ -#define READ(N) do { \ - line++; \ - want = (N); \ - got = -1; \ - if (!fgets(buf, sizeof(buf), fp)) \ - goto done; \ - got = sscanf(buf, "%i %i %i %i", \ - &val[0], &val[1], &val[2], &val[3]); \ - if (want != got) \ - goto done; \ +#define READ(N) \ + do { \ + line++; \ + want = (N); \ + got = -1; \ + if (!fgets(buf, sizeof(buf), fp)) \ + goto done; \ + got = sscanf(buf, "%i %i %i %i", &val[0], &val[1], &val[2], \ + &val[3]); \ + if (want != got) \ + goto done; \ } while (0) - /* Do it */ - READ(1); p->google_ramp_up = val[0]; - READ(1); p->google_ramp_down = val[0]; - READ(1); p->s3s0_ramp_up = val[0]; - READ(1); p->s0_tick_delay[0] = val[0]; - READ(1); p->s0_tick_delay[1] = val[0]; - READ(1); p->s0a_tick_delay[0] = val[0]; - READ(1); p->s0a_tick_delay[1] = val[0]; - READ(1); p->s0s3_ramp_down = val[0]; - READ(1); p->s3_sleep_for = val[0]; - READ(1); p->s3_ramp_up = val[0]; - READ(1); p->s3_ramp_down = val[0]; - READ(1); p->tap_tick_delay = val[0]; - READ(1); p->tap_gate_delay = val[0]; - READ(1); p->tap_display_time = val[0]; - - READ(1); p->tap_pct_red = val[0]; - READ(1); p->tap_pct_green = val[0]; - READ(1); p->tap_seg_min_on = val[0]; - READ(1); p->tap_seg_max_on = val[0]; - READ(1); p->tap_seg_osc = val[0]; + READ(1); + p->google_ramp_up = val[0]; + READ(1); + p->google_ramp_down = val[0]; + READ(1); + p->s3s0_ramp_up = val[0]; + READ(1); + p->s0_tick_delay[0] = val[0]; + READ(1); + p->s0_tick_delay[1] = val[0]; + READ(1); + p->s0a_tick_delay[0] = val[0]; + READ(1); + p->s0a_tick_delay[1] = val[0]; + READ(1); + p->s0s3_ramp_down = val[0]; + READ(1); + p->s3_sleep_for = val[0]; + READ(1); + p->s3_ramp_up = val[0]; + READ(1); + p->s3_ramp_down = val[0]; + READ(1); + p->tap_tick_delay = val[0]; + READ(1); + p->tap_gate_delay = val[0]; + READ(1); + p->tap_display_time = val[0]; + + READ(1); + p->tap_pct_red = val[0]; + READ(1); + p->tap_pct_green = val[0]; + READ(1); + p->tap_seg_min_on = val[0]; + READ(1); + p->tap_seg_max_on = val[0]; + READ(1); + p->tap_seg_osc = val[0]; READ(3); p->tap_idx[0] = val[0]; p->tap_idx[1] = val[1]; @@ -298,19 +313,18 @@ int lb_load_program(const char *filename, struct lightbar_program *prog) fp = fopen(filename, "rb"); if (!fp) { - fprintf(stderr, "Can't open %s: %s\n", - filename, strerror(errno)); + fprintf(stderr, "Can't open %s: %s\n", filename, + strerror(errno)); return 1; } rc = fseek(fp, 0, SEEK_END); if (rc) { - fprintf(stderr, "Couldn't find end of file %s", - filename); + fprintf(stderr, "Couldn't find end of file %s", filename); fclose(fp); return 1; } - rc = (int) ftell(fp); + rc = (int)ftell(fp); if (rc > EC_LB_PROG_LEN) { fprintf(stderr, "File %s is too long, aborting\n", filename); fclose(fp); -- cgit v1.2.1 From 75431f64f4871ba22f62ef8986a3dbdb2959c2cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:45 -0600 Subject: board/host/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d1cf833a04bfe30082e31e0c804ecb0675de005 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728507 Reviewed-by: Jeremy Bettis --- board/host/board.c | 71 +++++++++++++++++++++--------------------------------- 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/board/host/board.c b/board/host/board.c index e639b6bc99..c364fdf6e2 100644 --- a/board/host/board.c +++ b/board/host/board.c @@ -28,7 +28,7 @@ * GPIO ports. This maps back to 0, which is then ignored by the host GPIO mock * code. */ -#define GPIO_0 0 +#define GPIO_0 0 #include "gpio_list.h" @@ -48,10 +48,10 @@ test_mockable_static int mock_temp_get_val(int idx, int *temp_ptr) } const struct temp_sensor_t temp_sensors[] = { - {"CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0}, - {"Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1}, - {"Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2}, - {"Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3}, + { "CPU", TEMP_SENSOR_TYPE_CPU, mock_temp_get_val, 0 }, + { "Board", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 1 }, + { "Case", TEMP_SENSOR_TYPE_CASE, mock_temp_get_val, 2 }, + { "Battery", TEMP_SENSOR_TYPE_BOARD, mock_temp_get_val, 3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -67,45 +67,31 @@ test_mockable void fps_event(enum gpio_signal signal) /* I2C ports */ const struct i2c_port_t i2c_ports[] = { #ifdef I2C_PORT_BATTERY - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = 0, - .sda = 0 - }, + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = 0, + .sda = 0 }, #elif defined I2C_PORT_LIGHTBAR - { - .name = "lightbar", - .port = I2C_PORT_LIGHTBAR, - .kbps = 100, - .scl = 0, - .sda = 0 - }, + { .name = "lightbar", + .port = I2C_PORT_LIGHTBAR, + .kbps = 100, + .scl = 0, + .sda = 0 }, #elif defined I2C_PORT_HOST_TCPC - { - .name = "tcpc", - .port = I2C_PORT_HOST_TCPC, - .kbps = 100, - .scl = 0, - .sda = 0 - }, + { .name = "tcpc", + .port = I2C_PORT_HOST_TCPC, + .kbps = 100, + .scl = 0, + .sda = 0 }, #elif defined I2C_PORT_EEPROM - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 100, - .scl = 0, - .sda = 0 - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = 0, + .sda = 0 }, #elif defined I2C_PORT_WLC - { - .name = "wlc", - .port = I2C_PORT_WLC, - .kbps = 100, - .scl = 0, - .sda = 0 - }, + { .name = "wlc", .port = I2C_PORT_WLC, .kbps = 100, .scl = 0, .sda = 0 }, #endif }; @@ -141,9 +127,8 @@ int board_get_entropy(void *buffer, int len) static uint8_t eeprom[CBI_IMAGE_SIZE]; -int eeprom_i2c_xfer(int port, uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int eeprom_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { static int offset; -- cgit v1.2.1 From 1918a62a634a6fe4f5c66a48af701bdda3205a2d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:13 -0600 Subject: baseboard/mtscp-rv32i/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19c1abd1bfb704933e978c2da8aea002a820577d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727925 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/baseboard.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c index ac261c3aa8..9a81125c40 100644 --- a/baseboard/mtscp-rv32i/baseboard.c +++ b/baseboard/mtscp-rv32i/baseboard.c @@ -13,22 +13,24 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { /* SRAM (for most code, data) */ - {0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, + { 0, SCP_SRAM_END, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R }, /* SRAM (for IPI shared buffer) */ - {SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R}, - /* For AP domain */ + { SCP_SRAM_END, SCP_FW_END, MPU_ATTR_W | MPU_ATTR_R }, +/* For AP domain */ #ifdef CHIP_VARIANT_MT8195 - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P}, + { 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R | MPU_ATTR_P }, #else - {0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x60000000, 0x70000000, MPU_ATTR_W | MPU_ATTR_R }, #endif /* For SCP sys */ - {0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R }, #ifdef CHIP_VARIANT_MT8195 - {0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, - {CONFIG_PANIC_DRAM_BASE, CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, MPU_ATTR_W | MPU_ATTR_R}, + { 0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R }, + { CONFIG_PANIC_DRAM_BASE, + CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_DRAM_SIZE, + MPU_ATTR_W | MPU_ATTR_R }, #else - {0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R}, + { 0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R }, #endif }; @@ -37,7 +39,7 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { #ifdef CONFIG_PANIC_CONSOLE_OUTPUT static void report_previous_panic(void) { - struct panic_data * panic = panic_get_data(); + struct panic_data *panic = panic_get_data(); if (panic == NULL && SCP_CORE0_MON_PC_LATCH == 0) return; @@ -48,11 +50,8 @@ static void report_previous_panic(void) } else { ccprintf("No panic data\n"); } - ccprintf("Latch PC:%x LR:%x SP:%x\n", - SCP_CORE0_MON_PC_LATCH, - SCP_CORE0_MON_LR_LATCH, - SCP_CORE0_MON_SP_LATCH); - + ccprintf("Latch PC:%x LR:%x SP:%x\n", SCP_CORE0_MON_PC_LATCH, + SCP_CORE0_MON_LR_LATCH, SCP_CORE0_MON_SP_LATCH); } DECLARE_HOOK(HOOK_INIT, report_previous_panic, HOOK_PRIO_DEFAULT); #endif -- cgit v1.2.1 From 43bd4979a1eb12eac74143eb364882b248566dee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:13 -0600 Subject: board/atlas/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c57265d0ea060fe08d3d2d48abc11082e022e30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728014 Reviewed-by: Jeremy Bettis --- board/atlas/battery.c | 52 ++++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/board/atlas/battery.c b/board/atlas/battery.c index fb2fba18be..2d07d360ef 100644 --- a/board/atlas/battery.c +++ b/board/atlas/battery.c @@ -18,10 +18,10 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHUTDOWN_DATA 0x0010 enum battery_type { BATTERY_LG, @@ -52,16 +52,16 @@ static int battery_report_present = 1; * limits are given by discharging_min/max_c. */ static const struct battery_info batt_info_lg = { - .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ - .voltage_normal = 7700, - .voltage_min = 6100, /* Add 100mV for charger accuracy */ - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 46, - .charging_min_c = 10, - .charging_max_c = 50, - .discharging_min_c = 0, - .discharging_max_c = 60, + .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ + .voltage_normal = 7700, + .voltage_min = 6100, /* Add 100mV for charger accuracy */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 46, + .charging_min_c = 10, + .charging_max_c = 50, + .discharging_min_c = 0, + .discharging_max_c = 60, }; /* @@ -70,16 +70,16 @@ static const struct battery_info batt_info_lg = { * limits are given by discharging_min/max_c. */ static const struct battery_info batt_info_lishen = { - .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ - .voltage_normal = 7700, - .voltage_min = 6100, /* Add 100mV for charger accuracy */ - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 46, - .charging_min_c = 10, - .charging_max_c = 50, - .discharging_min_c = 0, - .discharging_max_c = 60, + .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ + .voltage_normal = 7700, + .voltage_min = 6100, /* Add 100mV for charger accuracy */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 46, + .charging_min_c = 10, + .charging_max_c = 50, + .discharging_min_c = 0, + .discharging_max_c = 60, }; static const struct board_batt_params info[] = { @@ -110,7 +110,7 @@ static int board_get_battery_type(void) if (!battery_manufacturer_name(name, sizeof(name))) { for (i = 0; i < BATTERY_TYPE_COUNT; i++) { if (!strncasecmp(name, info[i].manuf_name, - ARRAY_SIZE(name)-1)) { + ARRAY_SIZE(name) - 1)) { board_battery_type = i; break; } @@ -139,7 +139,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1); const struct battery_info *battery_get_info(void) { return info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type].batt_info; + DEFAULT_BATTERY_TYPE : + board_battery_type] + .batt_info; } int board_cut_off_battery(void) @@ -183,7 +185,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) */ if (!battery_is_cut_off() && !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; return 0; -- cgit v1.2.1 From f1e575670090dc9ef154b90a5ad92f1d3154c466 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:36 -0600 Subject: board/storo/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3656389a45ffda0d31d04e37a4ea5aa1e7c5a16e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728971 Reviewed-by: Jeremy Bettis --- board/storo/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/storo/cbi_ssfc.c b/board/storo/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/storo/cbi_ssfc.c +++ b/board/storo/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 69b3183ab91ebf99abf612efdd261e72421f044d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:27 -0600 Subject: board/boldar/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaec8cd2ca7ca72cb60099f4641f90502b5338f1c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728063 Reviewed-by: Jeremy Bettis --- board/boldar/board.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/boldar/board.c b/board/boldar/board.c index 69546a4ea2..d2bfda4bae 100644 --- a/board/boldar/board.c +++ b/board/boldar/board.c @@ -47,7 +47,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -86,7 +86,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -111,8 +111,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -133,8 +133,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -313,8 +313,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -325,16 +324,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -346,8 +345,9 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ if (usb_db == DB_USB3_ACTIVE) { ps8815_reset(); - usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(USBC_PORT_C1, + USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); } } -- cgit v1.2.1 From a4da10324fe7f4effa382bd52646b47b01dcfed5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:51 -0600 Subject: extra/usb_updater/usb_updater2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08be6faa208b3cf6c62feaf9b4342c2e360943eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730191 Reviewed-by: Jeremy Bettis --- extra/usb_updater/usb_updater2.c | 270 ++++++++++++++++++--------------------- 1 file changed, 125 insertions(+), 145 deletions(-) diff --git a/extra/usb_updater/usb_updater2.c b/extra/usb_updater/usb_updater2.c index 81cf48a680..e1407abe67 100644 --- a/extra/usb_updater/usb_updater2.c +++ b/extra/usb_updater/usb_updater2.c @@ -46,16 +46,16 @@ #define PROTOCOL USB_PROTOCOL_GOOGLE_UPDATE enum exit_values { - noop = 0, /* All up to date, no update needed. */ - all_updated = 1, /* Update completed, reboot required. */ - rw_updated = 2, /* RO was not updated, reboot required. */ - update_error = 3 /* Something went wrong. */ + noop = 0, /* All up to date, no update needed. */ + all_updated = 1, /* Update completed, reboot required. */ + rw_updated = 2, /* RO was not updated, reboot required. */ + update_error = 3 /* Something went wrong. */ }; struct usb_endpoint { struct libusb_device_handle *devh; uint8_t ep_num; - int chunk_len; + int chunk_len; }; struct transfer_descriptor { @@ -76,22 +76,22 @@ static char *progname; static char *short_opts = "bd:efg:hjlnp:rsS:tuw"; static const struct option long_opts[] = { /* name hasarg *flag val */ - {"binvers", 1, NULL, 'b'}, - {"device", 1, NULL, 'd'}, - {"entropy", 0, NULL, 'e'}, - {"fwver", 0, NULL, 'f'}, - {"tp_debug", 1, NULL, 'g'}, - {"help", 0, NULL, 'h'}, - {"jump_to_rw", 0, NULL, 'j'}, - {"follow_log", 0, NULL, 'l'}, - {"no_reset", 0, NULL, 'n'}, - {"tp_update", 1, NULL, 'p'}, - {"reboot", 0, NULL, 'r'}, - {"stay_in_ro", 0, NULL, 's'}, - {"serial", 1, NULL, 'S'}, - {"tp_info", 0, NULL, 't'}, - {"unlock_rollback", 0, NULL, 'u'}, - {"unlock_rw", 0, NULL, 'w'}, + { "binvers", 1, NULL, 'b' }, + { "device", 1, NULL, 'd' }, + { "entropy", 0, NULL, 'e' }, + { "fwver", 0, NULL, 'f' }, + { "tp_debug", 1, NULL, 'g' }, + { "help", 0, NULL, 'h' }, + { "jump_to_rw", 0, NULL, 'j' }, + { "follow_log", 0, NULL, 'l' }, + { "no_reset", 0, NULL, 'n' }, + { "tp_update", 1, NULL, 'p' }, + { "reboot", 0, NULL, 'r' }, + { "stay_in_ro", 0, NULL, 's' }, + { "serial", 1, NULL, 'S' }, + { "tp_info", 0, NULL, 't' }, + { "unlock_rollback", 0, NULL, 'u' }, + { "unlock_rw", 0, NULL, 'w' }, {}, }; @@ -113,7 +113,7 @@ static void usage(int errs) "Options:\n" "\n" " -b,--binvers Report versions of image's " - "RW and RO, do not update\n" + "RW and RO, do not update\n" " -d,--device VID:PID USB device (default %04x:%04x)\n" " -e,--entropy Add entropy to device secret\n" " -f,--fwver Report running firmware versions.\n" @@ -128,7 +128,8 @@ static void usage(int errs) " -t,--tp_info Get touchpad information\n" " -u,--unlock_rollback Tell EC to unlock the rollback region\n" " -w,--unlock_rw Tell EC to unlock the RW region\n" - "\n", progname, VID, PID); + "\n", + progname, VID, PID); exit(errs ? update_error : noop); } @@ -138,7 +139,7 @@ static void str2hex(const char *str, uint8_t *data, int *len) int i; int slen = strlen(str); - if (slen/2 > *len) { + if (slen / 2 > *len) { fprintf(stderr, "Hex string too long.\n"); exit(update_error); } @@ -153,7 +154,7 @@ static void str2hex(const char *str, uint8_t *data, int *len) char tmp[3]; tmp[0] = str[i]; - tmp[1] = str[i+1]; + tmp[1] = str[i + 1]; tmp[2] = 0; data[*len] = strtol(tmp, &end, 16); @@ -250,9 +251,9 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr) return data; } -#define USB_ERROR(m, r) \ - fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \ - m, r, libusb_strerror(r)) +#define USB_ERROR(m, r) \ + fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \ + r, libusb_strerror(r)) /* * Actual USB transfer function, the 'allow_less' flag indicates that the @@ -261,17 +262,14 @@ static uint8_t *get_file_or_die(const char *filename, size_t *len_ptr) * bytes were received. */ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen, - void *inbuf, int inlen, int allow_less, - size_t *rxed_count) + void *inbuf, int inlen, int allow_less, size_t *rxed_count) { - int r, actual; /* Send data out */ if (outbuf && outlen) { actual = 0; - r = libusb_bulk_transfer(uep->devh, uep->ep_num, - outbuf, outlen, + r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen, &actual, 2000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); @@ -286,11 +284,9 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen, /* Read reply back */ if (inbuf && inlen) { - actual = 0; - r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, - inbuf, inlen, - &actual, 5000); + r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf, + inlen, &actual, 5000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); exit(update_error); @@ -307,8 +303,8 @@ static void do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen, } } -static void xfer(struct usb_endpoint *uep, void *outbuf, - size_t outlen, void *inbuf, size_t inlen, int allow_less) +static void xfer(struct usb_endpoint *uep, void *outbuf, size_t outlen, + void *inbuf, size_t inlen, int allow_less) { do_xfer(uep, outbuf, outlen, inbuf, inlen, allow_less, NULL); } @@ -321,8 +317,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface, if (iface->bInterfaceClass == 255 && iface->bInterfaceSubClass == SUBCLASS && - iface->bInterfaceProtocol == PROTOCOL && - iface->bNumEndpoints) { + iface->bInterfaceProtocol == PROTOCOL && iface->bNumEndpoints) { ep = &iface->endpoint[0]; uep->ep_num = ep->bEndpointAddress & 0x7f; uep->chunk_len = ep->wMaxPacketSize; @@ -377,19 +372,19 @@ static int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr) return 0; *s++ = '\0'; - *vid_ptr = (uint16_t) strtoull(copy, &e, 16); + *vid_ptr = (uint16_t)strtoull(copy, &e, 16); if (!*optarg || (e && *e)) return 0; - *pid_ptr = (uint16_t) strtoull(s, &e, 16); + *pid_ptr = (uint16_t)strtoull(s, &e, 16); if (!*optarg || (e && *e)) return 0; return 1; } -static libusb_device_handle *check_device(libusb_device *dev, - uint16_t vid, uint16_t pid, char *serialno) +static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid, + uint16_t pid, char *serialno) { struct libusb_device_descriptor desc; libusb_device_handle *handle = NULL; @@ -409,7 +404,9 @@ static libusb_device_handle *check_device(libusb_device *dev, if (desc.iSerialNumber) { ret = libusb_get_string_descriptor_ascii(handle, - desc.iSerialNumber, (unsigned char *)sn, sizeof(sn)); + desc.iSerialNumber, + (unsigned char *)sn, + sizeof(sn)); if (ret > 0) snvalid = 1; } @@ -428,8 +425,8 @@ static libusb_device_handle *check_device(libusb_device *dev, return NULL; } -static void usb_findit(uint16_t vid, uint16_t pid, - char *serialno, struct usb_endpoint *uep) +static void usb_findit(uint16_t vid, uint16_t pid, char *serialno, + struct usb_endpoint *uep) { int iface_num, r, i; libusb_device **devs; @@ -475,8 +472,8 @@ static void usb_findit(uint16_t vid, uint16_t pid, shut_down(uep); } - printf("found interface %d endpoint %d, chunk_len %d\n", - iface_num, uep->ep_num, uep->chunk_len); + printf("found interface %d endpoint %d, chunk_len %d\n", iface_num, + uep->ep_num, uep->chunk_len); libusb_set_auto_detach_kernel_driver(uep->devh, 1); r = libusb_claim_interface(uep->devh, iface_num); @@ -511,9 +508,8 @@ static int transfer_block(struct usb_endpoint *uep, } /* Now get the reply. */ - r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, - (void *) &reply, sizeof(reply), - &actual, 5000); + r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, (void *)&reply, + sizeof(reply), &actual, 5000); if (r) { if (r == -7) { fprintf(stderr, "Timeout!\n"); @@ -541,10 +537,8 @@ static int transfer_block(struct usb_endpoint *uep, * data_len - section size * smart_update - non-zero to enable the smart trailing of 0xff. */ -static void transfer_section(struct transfer_descriptor *td, - uint8_t *data_ptr, - uint32_t section_addr, - size_t data_len, +static void transfer_section(struct transfer_descriptor *td, uint8_t *data_ptr, + uint32_t section_addr, size_t data_len, uint8_t smart_update) { /* @@ -571,17 +565,16 @@ static void transfer_section(struct transfer_descriptor *td, struct update_frame_header ufh; ufh.block_size = htobe32(payload_size + - sizeof(struct update_frame_header)); + sizeof(struct update_frame_header)); ufh.cmd.block_base = block_base; ufh.cmd.block_digest = 0; for (max_retries = 10; max_retries; max_retries--) - if (!transfer_block(&td->uep, &ufh, - data_ptr, payload_size)) + if (!transfer_block(&td->uep, &ufh, data_ptr, + payload_size)) break; if (!max_retries) { - fprintf(stderr, - "Failed to transfer block, %zd to go\n", + fprintf(stderr, "Failed to transfer block, %zd to go\n", data_len); exit(update_error); } @@ -596,30 +589,27 @@ static void transfer_section(struct transfer_descriptor *td, * states. */ enum upgrade_status { - not_needed = 0, /* Version below or equal that on the target. */ - not_possible, /* - * RO is newer, but can't be transferred due to - * target RW shortcomings. - */ - needed /* - * This section needs to be transferred to the - * target. - */ + not_needed = 0, /* Version below or equal that on the target. */ + not_possible, /* + * RO is newer, but can't be transferred due to + * target RW shortcomings. + */ + needed /* + * This section needs to be transferred to the + * target. + */ }; /* This array describes all sections of the new image. */ static struct { const char *name; - uint32_t offset; - uint32_t size; - enum upgrade_status ustatus; + uint32_t offset; + uint32_t size; + enum upgrade_status ustatus; char version[32]; int32_t rollback; uint32_t key_version; -} sections[] = { - {"RO"}, - {"RW"} -}; +} sections[] = { { "RO" }, { "RW" } }; static const struct fmap_area *fmap_find_area_or_die(const struct fmap *fmap, const char *name) @@ -650,7 +640,7 @@ static void fetch_header_versions(const uint8_t *image, size_t len) fprintf(stderr, "Cannot find FMAP in image\n"); exit(update_error); } - fmap = (const struct fmap *)(image+offset); + fmap = (const struct fmap *)(image + offset); /* FIXME: validate fmap struct more than this? */ if (fmap->size != len) { @@ -693,15 +683,15 @@ static void fetch_header_versions(const uint8_t *image, size_t len) fprintf(stderr, "Invalid fwid size\n"); exit(update_error); } - memcpy(sections[i].version, image+fmaparea->offset, - fmaparea->size); + memcpy(sections[i].version, image + fmaparea->offset, + fmaparea->size); sections[i].rollback = -1; if (fmap_rollback_name) { fmaparea = fmap_find_area(fmap, fmap_rollback_name); if (fmaparea) memcpy(§ions[i].rollback, - image+fmaparea->offset, + image + fmaparea->offset, sizeof(sections[i].rollback)); } @@ -710,7 +700,8 @@ static void fetch_header_versions(const uint8_t *image, size_t len) fmaparea = fmap_find_area(fmap, fmap_key_name); if (fmaparea) { const struct vb21_packed_key *key = - (const void *)(image+fmaparea->offset); + (const void *)(image + + fmaparea->offset); sections[i].key_version = key->key_version; } } @@ -723,9 +714,9 @@ static int show_headers_versions(const void *image) for (i = 0; i < ARRAY_SIZE(sections); i++) { printf("%s off=%08x/%08x v=%.32s rb=%d kv=%d\n", - sections[i].name, sections[i].offset, sections[i].size, - sections[i].version, sections[i].rollback, - sections[i].key_version); + sections[i].name, sections[i].offset, sections[i].size, + sections[i].version, sections[i].rollback, + sections[i].key_version); } return 0; } @@ -772,17 +763,16 @@ static void setup_connection(struct transfer_descriptor *td) int actual = 0; /* Flush all data from endpoint to recover in case of error. */ - while (!libusb_bulk_transfer(td->uep.devh, - td->uep.ep_num | 0x80, - (void *)&inbuf, td->uep.chunk_len, - &actual, 10)) { + while (!libusb_bulk_transfer(td->uep.devh, td->uep.ep_num | 0x80, + (void *)&inbuf, td->uep.chunk_len, &actual, + 10)) { printf("flush\n"); } memset(&ufh, 0, sizeof(ufh)); ufh.block_size = htobe32(sizeof(ufh)); - do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp, - sizeof(start_resp), 1, &rxed_size); + do_xfer(&td->uep, &ufh, sizeof(ufh), &start_resp, sizeof(start_resp), 1, + &rxed_size); /* We got something. Check for errors in response */ if (rxed_size < 8) { @@ -803,10 +793,9 @@ static void setup_connection(struct transfer_descriptor *td) header_type = be16toh(start_resp.rpdu.header_type); printf("target running protocol version %d (type %d)\n", - protocol_version, header_type); + protocol_version, header_type); if (header_type != UPDATE_HEADER_TYPE_COMMON) { - fprintf(stderr, "Unsupported header type %d\n", - header_type); + fprintf(stderr, "Unsupported header type %d\n", header_type); exit(update_error); } @@ -820,7 +809,7 @@ static void setup_connection(struct transfer_descriptor *td) td->offset = be32toh(start_resp.rpdu.common.offset); memcpy(targ.common.version, start_resp.rpdu.common.version, - sizeof(start_resp.rpdu.common.version)); + sizeof(start_resp.rpdu.common.version)); targ.common.maximum_pdu_size = be32toh(start_resp.rpdu.common.maximum_pdu_size); targ.common.flash_protection = @@ -845,21 +834,20 @@ static void setup_connection(struct transfer_descriptor *td) * if it is - of what maximum size. */ static int ext_cmd_over_usb(struct usb_endpoint *uep, uint16_t subcommand, - void *cmd_body, size_t body_size, - void *resp, size_t *resp_size, - int allow_less) + void *cmd_body, size_t body_size, void *resp, + size_t *resp_size, int allow_less) { struct update_frame_header *ufh; uint16_t *frame_ptr; size_t usb_msg_size; - usb_msg_size = sizeof(struct update_frame_header) + - sizeof(subcommand) + body_size; + usb_msg_size = sizeof(struct update_frame_header) + sizeof(subcommand) + + body_size; ufh = malloc(usb_msg_size); if (!ufh) { - printf("%s: failed to allocate %zd bytes\n", - __func__, usb_msg_size); + printf("%s: failed to allocate %zd bytes\n", __func__, + usb_msg_size); return -1; } @@ -895,30 +883,28 @@ static void send_done(struct usb_endpoint *uep) } static void send_subcommand(struct transfer_descriptor *td, uint16_t subcommand, - void *cmd_body, size_t body_size, - uint8_t *response, size_t response_size) + void *cmd_body, size_t body_size, uint8_t *response, + size_t response_size) { send_done(&td->uep); - ext_cmd_over_usb(&td->uep, subcommand, - cmd_body, body_size, - response, &response_size, 0); + ext_cmd_over_usb(&td->uep, subcommand, cmd_body, body_size, response, + &response_size, 0); printf("sent command %x, resp %x\n", subcommand, response[0]); } /* Returns number of successfully transmitted image sections. */ -static int transfer_image(struct transfer_descriptor *td, - uint8_t *data, size_t data_len) +static int transfer_image(struct transfer_descriptor *td, uint8_t *data, + size_t data_len) { size_t i; int num_txed_sections = 0; for (i = 0; i < ARRAY_SIZE(sections); i++) if (sections[i].ustatus == needed) { - transfer_section(td, - data + sections[i].offset, - sections[i].offset, - sections[i].size, 1); + transfer_section(td, data + sections[i].offset, + sections[i].offset, sections[i].size, + 1); num_txed_sections++; } @@ -968,9 +954,8 @@ static void generate_reset_request(struct transfer_descriptor *td) command_body_size = 0; response_size = 1; subcommand = UPDATE_EXTRA_CMD_IMMEDIATE_RESET; - ext_cmd_over_usb(&td->uep, subcommand, - command_body, command_body_size, - &response, &response_size, 0); + ext_cmd_over_usb(&td->uep, subcommand, command_body, command_body_size, + &response, &response_size, 0); printf("reboot not triggered\n"); } @@ -987,7 +972,7 @@ static void get_random(uint8_t *data, int len) } while (i < len) { - int ret = fread(data+i, len-i, 1, fp); + int ret = fread(data + i, len - i, 1, fp); if (ret < 0) { perror("fread"); @@ -1005,7 +990,8 @@ static void read_console(struct transfer_descriptor *td) uint8_t payload[] = { 0x1 }; uint8_t response[64]; size_t response_size = 64; - struct timespec sleep_duration = { /* 100 ms */ + struct timespec sleep_duration = { + /* 100 ms */ .tv_sec = 0, .tv_nsec = 100l * 1000l * 1000l, }; @@ -1015,17 +1001,15 @@ static void read_console(struct transfer_descriptor *td) printf("\n"); while (1) { response_size = 1; - ext_cmd_over_usb(&td->uep, - UPDATE_EXTRA_CMD_CONSOLE_READ_INIT, - NULL, 0, - response, &response_size, 0); + ext_cmd_over_usb(&td->uep, UPDATE_EXTRA_CMD_CONSOLE_READ_INIT, + NULL, 0, response, &response_size, 0); while (1) { response_size = 64; ext_cmd_over_usb(&td->uep, UPDATE_EXTRA_CMD_CONSOLE_READ_NEXT, - payload, sizeof(payload), - response, &response_size, 1); + payload, sizeof(payload), response, + &response_size, 1); if (response[0] == 0) break; /* make sure it's null-terminated. */ @@ -1067,7 +1051,7 @@ int main(int argc, char *argv[]) memset(&td, 0, sizeof(td)); errorcnt = 0; - opterr = 0; /* quiet, you */ + opterr = 0; /* quiet, you */ while ((i = getopt_long(argc, argv, short_opts, long_opts, 0)) != -1) { switch (i) { case 'b': @@ -1091,8 +1075,8 @@ int main(int argc, char *argv[]) extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG; /* Maximum length. */ extra_command_data_len = 50; - str2hex(optarg, - extra_command_data, &extra_command_data_len); + str2hex(optarg, extra_command_data, + &extra_command_data_len); hexdump(extra_command_data, extra_command_data_len); extra_command_answer_len = 64; break; @@ -1112,8 +1096,8 @@ int main(int argc, char *argv[]) touchpad_update = 1; data = get_file_or_die(optarg, &data_len); - printf("read %zd(%#zx) bytes from %s\n", - data_len, data_len, argv[optind - 1]); + printf("read %zd(%#zx) bytes from %s\n", data_len, + data_len, argv[optind - 1]); break; case 'r': @@ -1127,8 +1111,7 @@ int main(int argc, char *argv[]) break; case 't': extra_command = UPDATE_EXTRA_CMD_TOUCHPAD_INFO; - extra_command_answer_len = - sizeof(struct touchpad_info); + extra_command_answer_len = sizeof(struct touchpad_info); break; case 'u': extra_command = UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK; @@ -1136,7 +1119,7 @@ int main(int argc, char *argv[]) case 'w': extra_command = UPDATE_EXTRA_CMD_UNLOCK_RW; break; - case 0: /* auto-handled option */ + case 0: /* auto-handled option */ break; case '?': if (optopt) @@ -1167,8 +1150,8 @@ int main(int argc, char *argv[]) } data = get_file_or_die(argv[optind], &data_len); - printf("read %zd(%#zx) bytes from %s\n", - data_len, data_len, argv[optind]); + printf("read %zd(%#zx) bytes from %s\n", data_len, data_len, + argv[optind]); fetch_header_versions(data, data_len); @@ -1190,16 +1173,13 @@ int main(int argc, char *argv[]) if (data) { if (touchpad_update) { - transfer_section(&td, - data, - 0x80000000, - data_len, 0); + transfer_section(&td, data, 0x80000000, data_len, 0); free(data); send_done(&td.uep); } else { - transferred_sections = transfer_image(&td, - data, data_len); + transferred_sections = + transfer_image(&td, data, data_len); free(data); if (transferred_sections && !no_reset_request) @@ -1208,16 +1188,16 @@ int main(int argc, char *argv[]) } else if (extra_command == UPDATE_EXTRA_CMD_CONSOLE_READ_INIT) { read_console(&td); } else if (extra_command > -1) { - send_subcommand(&td, extra_command, - extra_command_data, extra_command_data_len, - extra_command_answer, extra_command_answer_len); + send_subcommand(&td, extra_command, extra_command_data, + extra_command_data_len, extra_command_answer, + extra_command_answer_len); switch (extra_command) { case UPDATE_EXTRA_CMD_TOUCHPAD_INFO: dump_touchpad_info(extra_command_answer, extra_command_answer_len); break; - case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: + case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: hexdump(extra_command_answer, extra_command_answer_len); break; } -- cgit v1.2.1 From 5dc847c4c0c2e85787c46b726abbc0344a21d3cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:18 -0600 Subject: common/lid_angle.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd72f3eccbb392cc5d3f34124951bd377fc1c0ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729661 Reviewed-by: Jeremy Bettis --- common/lid_angle.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/common/lid_angle.c b/common/lid_angle.c index 8a3775b959..6ad65976a3 100644 --- a/common/lid_angle.c +++ b/common/lid_angle.c @@ -19,7 +19,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LIDANGLE, outstr) -#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LIDANGLE, format, ##args) /* * Define the number of previous lid angle measurements to keep for determining @@ -50,7 +50,7 @@ static int wake_large_angle = 180; static const int wake_small_angle = 13; /* Define hysteresis value to add stability to the flags. */ -#define LID_ANGLE_HYSTERESIS_DEG 2 +#define LID_ANGLE_HYSTERESIS_DEG 2 /* Define max and min values for wake_large_angle. */ #define LID_ANGLE_MIN_LARGE_ANGLE 0 @@ -74,8 +74,8 @@ static int lid_in_range_to_enable_peripherals(int ang) else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE) return 1; - return (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) && - (ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG)); + return (ang >= (wake_small_angle + LID_ANGLE_HYSTERESIS_DEG)) && + (ang <= (wake_large_angle - LID_ANGLE_HYSTERESIS_DEG)); } /** @@ -96,11 +96,10 @@ static int lid_in_range_to_ignore_peripherals(int ang) else if (wake_large_angle == LID_ANGLE_MAX_LARGE_ANGLE) return 0; - return (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) || - (ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG)); + return (ang <= (wake_small_angle - LID_ANGLE_HYSTERESIS_DEG)) || + (ang >= (wake_large_angle + LID_ANGLE_HYSTERESIS_DEG)); } - int lid_angle_get_wake_angle(void) { return wake_large_angle; @@ -125,7 +124,7 @@ void lid_angle_update(int lid_ang) /* Record most recent lid angle in circular buffer. */ lidangle_buffer[index] = lid_ang; - index = (index == LID_ANGLE_BUFFER_SIZE-1) ? 0 : index+1; + index = (index == LID_ANGLE_BUFFER_SIZE - 1) ? 0 : index + 1; /* * Manage whether or not peripherals are enabled based on lid angle -- cgit v1.2.1 From c8c85deb6471185b32aa8f0c7399157b9220a476 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:41 -0600 Subject: chip/it83xx/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I82fb76f30c0edcce411d23c077d060b8b7bdf0ff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729166 Reviewed-by: Jeremy Bettis --- chip/it83xx/config_chip.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index 2f552c794a..4ed466f294 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -6,7 +6,7 @@ #ifndef __CROS_EC_CONFIG_CHIP_H #define __CROS_EC_CONFIG_CHIP_H -#if defined(CHIP_FAMILY_IT8320) /* N8 core */ +#if defined(CHIP_FAMILY_IT8320) /* N8 core */ #include "config_chip_it8320.h" #elif defined(CHIP_FAMILY_IT8XXX2) /* RISCV core */ #include "config_chip_it8xxx2.h" @@ -19,7 +19,7 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* Default PLL frequency. */ #define PLL_CLOCK 48000000 @@ -35,34 +35,34 @@ #define I2C_ENHANCED_PORT_COUNT 3 /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE) -#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) -#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE) -#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE) -#define ULTRA_TASK_STACK_SIZE (1056 + CHIP_EXTRA_STACK_SPACE) -#define TRENTA_TASK_STACK_SIZE (1184 + CHIP_EXTRA_STACK_SPACE) +#define SMALLER_TASK_STACK_SIZE (384 + CHIP_EXTRA_STACK_SPACE) +#define IDLE_TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) +#define LARGER_TASK_STACK_SIZE (768 + CHIP_EXTRA_STACK_SPACE) +#define VENTI_TASK_STACK_SIZE (896 + CHIP_EXTRA_STACK_SPACE) +#define ULTRA_TASK_STACK_SIZE (1056 + CHIP_EXTRA_STACK_SPACE) +#define TRENTA_TASK_STACK_SIZE (1184 + CHIP_EXTRA_STACK_SPACE) /* Default task stack size */ -#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) +#define TASK_STACK_SIZE (512 + CHIP_EXTRA_STACK_SPACE) #ifdef IT83XX_CHIP_FLASH_IS_KGD -#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* protect bank size */ +#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* erase bank size */ #else -#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */ -#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */ +#define CONFIG_FLASH_ERASE_SIZE 0x00000400 /* erase bank size */ #endif -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */ +#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */ /* * This is the block size of the ILM on the it83xx chip. * The ILM for static code cache, CPU fetch instruction from * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled. */ -#define IT83XX_ILM_BLOCK_SIZE 0x00001000 +#define IT83XX_ILM_BLOCK_SIZE 0x00001000 #ifdef IT83XX_CHIP_FLASH_IS_KGD /* @@ -101,9 +101,9 @@ * IT8xxx2 series support mapping LPC/eSPI I/O cycle 800h ~ 9FFh * to 0x80081800 ~ 0x800819FF of DLM1. */ -#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE) -#define CONFIG_H2RAM_SIZE 0x00001000 -#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800 +#define CONFIG_H2RAM_BASE (CHIP_H2RAM_BASE) +#define CONFIG_H2RAM_SIZE 0x00001000 +#define CONFIG_H2RAM_HOST_LPC_IO_BASE 0x800 /****************************************************************************/ /* Customize the build */ @@ -123,4 +123,4 @@ #define __RAM_CODE_SECTION_NAME ".ram_code" -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From eb2b38b9ba73b656c7ef1cf2f5e5b7e7074b4573 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:48 -0600 Subject: board/reef_it8320/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a4ebf6b4d24fab4a7e39703c183671851887caa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728890 Reviewed-by: Jeremy Bettis --- board/reef_it8320/usb_pd_policy.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/reef_it8320/usb_pd_policy.c b/board/reef_it8320/usb_pd_policy.c index 7fec6bc975..85787c96f9 100644 --- a/board/reef_it8320/usb_pd_policy.c +++ b/board/reef_it8320/usb_pd_policy.c @@ -23,12 +23,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -39,7 +39,7 @@ static void board_vbus_update_source_current(int port) { enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A : - GPIO_EN_USB_C0_3A; + GPIO_EN_USB_C0_3A; gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0); gpio_set_level(gpio, vbus_en[port]); -- cgit v1.2.1 From 609a0ddc8ca50efd82359475212a3c2c081c3ae8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:09 -0600 Subject: common/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iacd0d2892115c8fac0133c4feae1bc6112c42aff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729631 Reviewed-by: Jeremy Bettis --- common/gpio.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/common/gpio.c b/common/gpio.c index 9fa8512e27..0a7b758f21 100644 --- a/common/gpio.c +++ b/common/gpio.c @@ -34,9 +34,9 @@ struct gpio_alt_func { * Construct the gpio_alt_funcs array. This array is used by gpio_config_module * to enable and disable GPIO alternate functions on a module by module basis. */ -#define ALTERNATE(pinmask, function, module, flagz) \ - {GPIO_##pinmask, .func = (function), .module_id = (module), \ - .flags = (flagz)}, +#define ALTERNATE(pinmask, function, module, flagz) \ + { GPIO_##pinmask, .func = (function), .module_id = (module), \ + .flags = (flagz) }, static __const_data const struct gpio_alt_func gpio_alt_funcs[] = { #include "gpio.wrap" @@ -74,9 +74,9 @@ static int gpio_config_pins(enum module_id id, uint32_t port, uint32_t pin_mask, gpio_set_flags_by_mask( af->port, (af->mask & pin_mask), enable ? af->flags : GPIO_INPUT); - gpio_set_alternate_function(af->port, - (af->mask & pin_mask), - enable ? af->func : GPIO_ALT_FUNC_NONE); + gpio_set_alternate_function( + af->port, (af->mask & pin_mask), + enable ? af->func : GPIO_ALT_FUNC_NONE); rv = EC_SUCCESS; /* We're done here if we were just setting one port. */ if (port != GPIO_CONFIG_ALL_PORTS) @@ -222,8 +222,8 @@ int gpio_or_ioex_get_level(int signal, int *value) int signal_is_gpio(int signal) { - return ((signal >= GPIO_SIGNAL_START) - && (signal < GPIO_SIGNAL_START + GPIO_COUNT)); + return ((signal >= GPIO_SIGNAL_START) && + (signal < GPIO_SIGNAL_START + GPIO_COUNT)); } __attribute__((weak)) void gpio_set_wakepin(enum gpio_signal signal, -- cgit v1.2.1 From a2bc3f0f3f778b568599bff0e0ba2183aec143fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:45 -0600 Subject: zephyr/shim/src/pwm_hc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I556fa6be82d650b90f72a137014c3da016235982 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730898 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/pwm_hc.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/zephyr/shim/src/pwm_hc.c b/zephyr/shim/src/pwm_hc.c index 00c8ddf69b..15e924f0d0 100644 --- a/zephyr/shim/src/pwm_hc.c +++ b/zephyr/shim/src/pwm_hc.c @@ -19,17 +19,15 @@ LOG_MODULE_REGISTER(pwm_shim, LOG_LEVEL_ERR); -#define PWM_RAW_TO_PERCENT(v) \ - DIV_ROUND_NEAREST((uint32_t)(v) * 100, UINT16_MAX) -#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v) * UINT16_MAX / 100) +#define PWM_RAW_TO_PERCENT(v) DIV_ROUND_NEAREST((uint32_t)(v)*100, UINT16_MAX) +#define PWM_PERCENT_TO_RAW(v) ((uint32_t)(v)*UINT16_MAX / 100) -#define HAS_PWM_GENERIC_CHANNEL(compat) \ +#define HAS_PWM_GENERIC_CHANNEL(compat) \ DT_NODE_HAS_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), \ generic_pwm_channel) #define PWM_GENERIC_CHANNEL_ID(compat) \ - DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), \ - generic_pwm_channel) + DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(compat), generic_pwm_channel) #ifdef CONFIG_PWM_KBLIGHT static bool pwm_is_kblight(int type, int index) @@ -63,9 +61,8 @@ static bool pwm_is_displight(int type, int index) } #endif /* CONFIG_PLATFORM_EC_PWM_DISPLIGHT */ - -static enum ec_status host_command_pwm_set_duty( - struct host_cmd_handler_args *args) +static enum ec_status +host_command_pwm_set_duty(struct host_cmd_handler_args *args) { __maybe_unused const struct ec_params_pwm_set_duty *p = args->params; @@ -85,12 +82,11 @@ static enum ec_status host_command_pwm_set_duty( return EC_RES_INVALID_PARAM; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); -static enum ec_status host_command_pwm_get_duty( - struct host_cmd_handler_args *args) +static enum ec_status +host_command_pwm_get_duty(struct host_cmd_handler_args *args) { __maybe_unused const struct ec_params_pwm_get_duty *p = args->params; __maybe_unused struct ec_response_pwm_get_duty *r = args->response; @@ -112,6 +108,5 @@ static enum ec_status host_command_pwm_get_duty( return EC_RES_INVALID_PARAM; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); -- cgit v1.2.1 From 4bea24126a58c1e215ace18b75fd14ab2bbf4edd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:46 -0600 Subject: zephyr/include/emul/emul_syv682x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5228692a08138f58e76ecdb62b84501f5eefc36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730723 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_syv682x.h | 146 ++++++++++++++++++------------------- 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/zephyr/include/emul/emul_syv682x.h b/zephyr/include/emul/emul_syv682x.h index f08960ccac..72ce2a7e8a 100644 --- a/zephyr/include/emul/emul_syv682x.h +++ b/zephyr/include/emul/emul_syv682x.h @@ -17,91 +17,91 @@ /* Register info copied from syv682.h */ /* SYV682x register addresses */ -#define SYV682X_STATUS_REG 0x00 -#define SYV682X_CONTROL_1_REG 0x01 -#define SYV682X_CONTROL_2_REG 0x02 -#define SYV682X_CONTROL_3_REG 0x03 -#define SYV682X_CONTROL_4_REG 0x04 +#define SYV682X_STATUS_REG 0x00 +#define SYV682X_CONTROL_1_REG 0x01 +#define SYV682X_CONTROL_2_REG 0x02 +#define SYV682X_CONTROL_3_REG 0x03 +#define SYV682X_CONTROL_4_REG 0x04 /* Status Register */ -#define SYV682X_STATUS_OC_HV BIT(7) -#define SYV682X_STATUS_RVS BIT(6) -#define SYV682X_STATUS_OC_5V BIT(5) -#define SYV682X_STATUS_OVP BIT(4) -#define SYV682X_STATUS_FRS BIT(3) -#define SYV682X_STATUS_TSD BIT(2) +#define SYV682X_STATUS_OC_HV BIT(7) +#define SYV682X_STATUS_RVS BIT(6) +#define SYV682X_STATUS_OC_5V BIT(5) +#define SYV682X_STATUS_OVP BIT(4) +#define SYV682X_STATUS_FRS BIT(3) +#define SYV682X_STATUS_TSD BIT(2) #define SYV682X_STATUS_VSAFE_5V BIT(1) #define SYV682X_STATUS_VSAFE_0V BIT(0) #define SYV682X_STATUS_INT_MASK 0xfc -#define SYV682X_STATUS_NONE 0 +#define SYV682X_STATUS_NONE 0 /* Control Register 1 */ -#define SYV682X_CONTROL_1_CH_SEL BIT(1) -#define SYV682X_CONTROL_1_HV_DR BIT(2) -#define SYV682X_CONTROL_1_PWR_ENB BIT(7) - -#define SYV682X_5V_ILIM_MASK 0x18 -#define SYV682X_5V_ILIM_BIT_SHIFT 3 -#define SYV682X_5V_ILIM_1_25 0 -#define SYV682X_5V_ILIM_1_75 1 -#define SYV682X_5V_ILIM_2_25 2 -#define SYV682X_5V_ILIM_3_30 3 - -#define SYV682X_HV_ILIM_MASK 0x60 -#define SYV682X_HV_ILIM_BIT_SHIFT 5 -#define SYV682X_HV_ILIM_1_25 0 -#define SYV682X_HV_ILIM_1_75 1 -#define SYV682X_HV_ILIM_3_30 2 -#define SYV682X_HV_ILIM_5_50 3 +#define SYV682X_CONTROL_1_CH_SEL BIT(1) +#define SYV682X_CONTROL_1_HV_DR BIT(2) +#define SYV682X_CONTROL_1_PWR_ENB BIT(7) + +#define SYV682X_5V_ILIM_MASK 0x18 +#define SYV682X_5V_ILIM_BIT_SHIFT 3 +#define SYV682X_5V_ILIM_1_25 0 +#define SYV682X_5V_ILIM_1_75 1 +#define SYV682X_5V_ILIM_2_25 2 +#define SYV682X_5V_ILIM_3_30 3 + +#define SYV682X_HV_ILIM_MASK 0x60 +#define SYV682X_HV_ILIM_BIT_SHIFT 5 +#define SYV682X_HV_ILIM_1_25 0 +#define SYV682X_HV_ILIM_1_75 1 +#define SYV682X_HV_ILIM_3_30 2 +#define SYV682X_HV_ILIM_5_50 3 /* Control Register 2 */ -#define SYV682X_OC_DELAY_MASK GENMASK(7, 6) -#define SYV682X_OC_DELAY_SHIFT 6 -#define SYV682X_OC_DELAY_1MS 0 -#define SYV682X_OC_DELAY_10MS 1 -#define SYV682X_OC_DELAY_50MS 2 -#define SYV682X_OC_DELAY_100MS 3 -#define SYV682X_DSG_TIME_MASK GENMASK(5, 4) -#define SYV682X_DSG_TIME_SHIFT 4 -#define SYV682X_DSG_TIME_50MS 0 -#define SYV682X_DSG_TIME_100MS 1 -#define SYV682X_DSG_TIME_200MS 2 -#define SYV682X_DSG_TIME_400MS 3 -#define SYV682X_DSG_RON_MASK GENMASK(3, 2) -#define SYV682X_DSG_RON_SHIFT 2 -#define SYV682X_DSG_RON_200_OHM 0 -#define SYV682X_DSG_RON_400_OHM 1 -#define SYV682X_DSG_RON_800_OHM 2 -#define SYV682X_DSG_RON_1600_OHM 3 -#define SYV682X_CONTROL_2_SDSG BIT(1) -#define SYV682X_CONTROL_2_FDSG BIT(0) +#define SYV682X_OC_DELAY_MASK GENMASK(7, 6) +#define SYV682X_OC_DELAY_SHIFT 6 +#define SYV682X_OC_DELAY_1MS 0 +#define SYV682X_OC_DELAY_10MS 1 +#define SYV682X_OC_DELAY_50MS 2 +#define SYV682X_OC_DELAY_100MS 3 +#define SYV682X_DSG_TIME_MASK GENMASK(5, 4) +#define SYV682X_DSG_TIME_SHIFT 4 +#define SYV682X_DSG_TIME_50MS 0 +#define SYV682X_DSG_TIME_100MS 1 +#define SYV682X_DSG_TIME_200MS 2 +#define SYV682X_DSG_TIME_400MS 3 +#define SYV682X_DSG_RON_MASK GENMASK(3, 2) +#define SYV682X_DSG_RON_SHIFT 2 +#define SYV682X_DSG_RON_200_OHM 0 +#define SYV682X_DSG_RON_400_OHM 1 +#define SYV682X_DSG_RON_800_OHM 2 +#define SYV682X_DSG_RON_1600_OHM 3 +#define SYV682X_CONTROL_2_SDSG BIT(1) +#define SYV682X_CONTROL_2_FDSG BIT(0) /* Control Register 3 */ -#define SYV682X_BUSY BIT(7) -#define SYV682X_RVS_MASK BIT(3) -#define SYV682X_RST_REG BIT(0) -#define SYV682X_OVP_MASK 0x70 -#define SYV682X_OVP_BIT_SHIFT 4 -#define SYV682X_OVP_06_0 0 -#define SYV682X_OVP_08_0 1 -#define SYV682X_OVP_11_1 2 -#define SYV682X_OVP_12_1 3 -#define SYV682X_OVP_14_2 4 -#define SYV682X_OVP_17_9 5 -#define SYV682X_OVP_21_6 6 -#define SYV682X_OVP_23_7 7 -#define SYV682X_CONTROL_3_NONE 0 +#define SYV682X_BUSY BIT(7) +#define SYV682X_RVS_MASK BIT(3) +#define SYV682X_RST_REG BIT(0) +#define SYV682X_OVP_MASK 0x70 +#define SYV682X_OVP_BIT_SHIFT 4 +#define SYV682X_OVP_06_0 0 +#define SYV682X_OVP_08_0 1 +#define SYV682X_OVP_11_1 2 +#define SYV682X_OVP_12_1 3 +#define SYV682X_OVP_14_2 4 +#define SYV682X_OVP_17_9 5 +#define SYV682X_OVP_21_6 6 +#define SYV682X_OVP_23_7 7 +#define SYV682X_CONTROL_3_NONE 0 /* Control Register 4 */ -#define SYV682X_CONTROL_4_CC1_BPS BIT(7) -#define SYV682X_CONTROL_4_CC2_BPS BIT(6) -#define SYV682X_CONTROL_4_VCONN1 BIT(5) -#define SYV682X_CONTROL_4_VCONN2 BIT(4) -#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) -#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) -#define SYV682X_CONTROL_4_CC_FRS BIT(1) -#define SYV682X_CONTROL_4_INT_MASK 0x0c -#define SYV682X_CONTROL_4_NONE 0 +#define SYV682X_CONTROL_4_CC1_BPS BIT(7) +#define SYV682X_CONTROL_4_CC2_BPS BIT(6) +#define SYV682X_CONTROL_4_VCONN1 BIT(5) +#define SYV682X_CONTROL_4_VCONN2 BIT(4) +#define SYV682X_CONTROL_4_VBAT_OVP BIT(3) +#define SYV682X_CONTROL_4_VCONN_OCP BIT(2) +#define SYV682X_CONTROL_4_CC_FRS BIT(1) +#define SYV682X_CONTROL_4_INT_MASK 0x0c +#define SYV682X_CONTROL_4_NONE 0 /** * @brief Get pointer to SYV682x emulator using device tree order number. @@ -123,7 +123,7 @@ struct i2c_emul *syv682x_emul_get(int ord); * an effect. */ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status, - uint8_t control_4); + uint8_t control_4); /** * @brief Cause CONTROL_3[BUSY] to be set for a number of reads. This bit -- cgit v1.2.1 From 208b5f24ce0718c0dc1a6ac92c9249acfdf488a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:32 -0600 Subject: baseboard/ite_evb/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If03d561cbdf338e7d01e878b6dacb8d171ce2a8f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727908 Reviewed-by: Jeremy Bettis --- baseboard/ite_evb/usb_pd_policy.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/baseboard/ite_evb/usb_pd_policy.c b/baseboard/ite_evb/usb_pd_policy.c index b5462bd1e2..7def6871b9 100644 --- a/baseboard/ite_evb/usb_pd_policy.c +++ b/baseboard/ite_evb/usb_pd_policy.c @@ -20,8 +20,8 @@ #include "usb_mux.h" #include "usb_pd_pdo.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_is_max_request_allowed(void) { @@ -62,7 +62,6 @@ void pd_power_supply_reset(int port) board_pd_vbus_ctrl(port, 0); } - __override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap: we can be DFP or UFP for USB */ @@ -107,7 +106,7 @@ __override void svdm_exit_dp_mode(int port) } __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { /* Return length 0, means nothing needn't tx */ return 0; -- cgit v1.2.1 From 7091dcb3a19d6d79d3906907f35644f0b7246efc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:45 -0600 Subject: board/storo/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a6bbc20c18ddb0ce5e8a0df130c38503dc46722 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728972 Reviewed-by: Jeremy Bettis --- board/storo/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/storo/usb_pd_policy.c b/board/storo/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/storo/usb_pd_policy.c +++ b/board/storo/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From ce022209bb7fa84b6e0f63707458896e3b0d2ad6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:24 -0600 Subject: board/volteer/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I25eb20f0c141a2d9487cb611a1eb7acf5e097440 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729080 Reviewed-by: Jeremy Bettis --- board/volteer/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/volteer/led.c b/board/volteer/led.c index 52a6b9d890..a3a83ccf37 100644 --- a/board/volteer/led.c +++ b/board/volteer/led.c @@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = { const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 100, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 100, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, /* The green LED seems to be brighter than the others, so turn down * green from its natural level for these secondary colors. */ - [EC_LED_COLOR_YELLOW] = { 100, 70, 0 }, - [EC_LED_COLOR_WHITE] = { 100, 70, 100 }, - [EC_LED_COLOR_AMBER] = { 100, 20, 0 }, + [EC_LED_COLOR_YELLOW] = { 100, 70, 0 }, + [EC_LED_COLOR_WHITE] = { 100, 70, 100 }, + [EC_LED_COLOR_AMBER] = { 100, 20, 0 }, }; struct pwm_led pwm_leds[] = { -- cgit v1.2.1 From 10453f55e9daae077cbe7624cc2fd127da76cc39 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:12 -0600 Subject: include/printf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4357139064df7c646395414efa92a1a8b4024fcc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730392 Reviewed-by: Jeremy Bettis --- include/printf.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/include/printf.h b/include/printf.h index 37c0cc3949..8eed1618f8 100644 --- a/include/printf.h +++ b/include/printf.h @@ -8,8 +8,8 @@ #ifndef __CROS_EC_PRINTF_H #define __CROS_EC_PRINTF_H -#include /* For va_list */ -#include /* For size_t */ +#include /* For va_list */ +#include /* For size_t */ #include "common.h" /* The declaration of snprintf is changed to crec_snprintf for Zephyr, @@ -99,9 +99,8 @@ __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c), * @param format Format string * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated. */ -__attribute__((__format__(__printf__, 3, 4))) -__stdlib_compat int crec_snprintf(char *str, size_t size, const char *format, - ...); +__attribute__((__format__(__printf__, 3, 4))) __stdlib_compat int +crec_snprintf(char *str, size_t size, const char *format, ...); /** * Print formatted output to a string. @@ -118,6 +117,6 @@ __stdlib_compat int crec_snprintf(char *str, size_t size, const char *format, __stdlib_compat int crec_vsnprintf(char *str, size_t size, const char *format, va_list args); -#endif /* !HIDE_EC_STDLIB */ +#endif /* !HIDE_EC_STDLIB */ -#endif /* __CROS_EC_PRINTF_H */ +#endif /* __CROS_EC_PRINTF_H */ -- cgit v1.2.1 From 5b5724844d0c06aa7a1a010266747dcff8e85690 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:06 -0600 Subject: board/zinger/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib928c7218d3075852b1cdfbfa0a28f06bc469190 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729123 Reviewed-by: Jeremy Bettis --- board/zinger/usb_pd_policy.c | 103 +++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 57 deletions(-) diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c index 08314e7aa6..0bc884003b 100644 --- a/board/zinger/usb_pd_policy.c +++ b/board/zinger/usb_pd_policy.c @@ -20,15 +20,15 @@ /* ------------------------- Power supply control ------------------------ */ /* GPIO level setting helpers through BSRR register */ -#define GPIO_SET(n) (1 << (n)) +#define GPIO_SET(n) (1 << (n)) #define GPIO_RESET(n) (1 << ((n) + 16)) /* Output voltage selection */ enum volt { - VO_5V = GPIO_RESET(13) | GPIO_RESET(14), - VO_12V = GPIO_SET(13) | GPIO_RESET(14), + VO_5V = GPIO_RESET(13) | GPIO_RESET(14), + VO_12V = GPIO_SET(13) | GPIO_RESET(14), VO_13V = GPIO_RESET(13) | GPIO_SET(14), - VO_20V = GPIO_SET(13) | GPIO_SET(14), + VO_20V = GPIO_SET(13) | GPIO_SET(14), }; static inline void set_output_voltage(enum volt v) @@ -73,26 +73,27 @@ static timestamp_t fault_deadline; /* ADC in 12-bit mode */ #define ADC_SCALE BIT(12) /* ADC power supply : VDDA = 3.3V */ -#define VDDA_MV 3300 +#define VDDA_MV 3300 /* Current sense resistor : 5 milliOhm */ -#define R_SENSE 5 +#define R_SENSE 5 /* VBUS voltage is measured through 10k / 100k voltage divider = /11 */ -#define VOLT_DIV ((10+100)/10) +#define VOLT_DIV ((10 + 100) / 10) /* The current sensing op-amp has a x100 gain */ #define CURR_GAIN 100 /* convert VBUS voltage in raw ADC value */ -#define VBUS_MV(mv) ((mv)*ADC_SCALE/VOLT_DIV/VDDA_MV) +#define VBUS_MV(mv) ((mv)*ADC_SCALE / VOLT_DIV / VDDA_MV) /* convert VBUS current in raw ADC value */ -#define VBUS_MA(ma) ((ma)*ADC_SCALE*R_SENSE/1000*CURR_GAIN/VDDA_MV) +#define VBUS_MA(ma) ((ma)*ADC_SCALE * R_SENSE / 1000 * CURR_GAIN / VDDA_MV) /* convert raw ADC value to mA */ -#define ADC_TO_CURR_MA(vbus) ((vbus)*1000/(ADC_SCALE*R_SENSE)*VDDA_MV/CURR_GAIN) +#define ADC_TO_CURR_MA(vbus) \ + ((vbus)*1000 / (ADC_SCALE * R_SENSE) * VDDA_MV / CURR_GAIN) /* convert raw ADC value to mV */ -#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV*VDDA_MV/ADC_SCALE) +#define ADC_TO_VOLT_MV(vbus) ((vbus)*VOLT_DIV * VDDA_MV / ADC_SCALE) /* Max current : 20% over rated current */ -#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6/5) +#define MAX_CURRENT VBUS_MA(RATED_CURRENT * 6 / 5) /* Fast short circuit protection : 50% over rated current */ -#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3/2) +#define MAX_CURRENT_FAST VBUS_MA(RATED_CURRENT * 3 / 2) /* reset over-current after 1 second */ #define OCP_TIMEOUT SECOND @@ -100,19 +101,19 @@ static timestamp_t fault_deadline; #define SINK_IDLE_CURRENT VBUS_MA(500 /* mA */) /* Under-voltage limit is 0.8x Vnom */ -#define UVP_MV(mv) VBUS_MV((mv) * 8 / 10) +#define UVP_MV(mv) VBUS_MV((mv)*8 / 10) /* Over-voltage limit is 1.2x Vnom */ -#define OVP_MV(mv) VBUS_MV((mv) * 12 / 10) +#define OVP_MV(mv) VBUS_MV((mv)*12 / 10) /* Over-voltage recovery threshold is 1.1x Vnom */ -#define OVP_REC_MV(mv) VBUS_MV((mv) * 11 / 10) +#define OVP_REC_MV(mv) VBUS_MV((mv)*11 / 10) /* Maximum discharging delay */ -#define DISCHARGE_TIMEOUT (275*MSEC) +#define DISCHARGE_TIMEOUT (275 * MSEC) /* Voltage overshoot below the OVP threshold for discharging to avoid OVP */ #define DISCHARGE_OVERSHOOT_MV VBUS_MV(200) /* Time to wait after last RX edge interrupt before allowing deep sleep */ -#define PD_RX_SLEEP_TIMEOUT (100*MSEC) +#define PD_RX_SLEEP_TIMEOUT (100 * MSEC) /* ----- output voltage discharging ----- */ @@ -151,16 +152,15 @@ static void discharge_voltage(int target_volt) /* PDO voltages (should match the table above) */ static const struct { enum volt select; /* GPIO configuration to select the voltage */ - int uvp; /* under-voltage limit in mV */ - int ovp; /* over-voltage limit in mV */ - int ovp_rec;/* over-voltage recovery threshold in mV */ + int uvp; /* under-voltage limit in mV */ + int ovp; /* over-voltage limit in mV */ + int ovp_rec; /* over-voltage recovery threshold in mV */ } voltages[ARRAY_SIZE(pd_src_pdo)] = { - [PDO_IDX_5V] = {VO_5V, UVP_MV(5000), OVP_MV(5000), - OVP_REC_MV(5000)}, - [PDO_IDX_12V] = {VO_12V, UVP_MV(12000), OVP_MV(12000), - OVP_REC_MV(12000)}, - [PDO_IDX_20V] = {VO_20V, UVP_MV(20000), OVP_MV(20000), - OVP_REC_MV(20000)}, + [PDO_IDX_5V] = { VO_5V, UVP_MV(5000), OVP_MV(5000), OVP_REC_MV(5000) }, + [PDO_IDX_12V] = { VO_12V, UVP_MV(12000), OVP_MV(12000), + OVP_REC_MV(12000) }, + [PDO_IDX_20V] = { VO_20V, UVP_MV(20000), OVP_MV(20000), + OVP_REC_MV(20000) }, }; /* current and previous selected PDO entry */ @@ -199,8 +199,8 @@ void pd_transition_voltage(int idx) /* Make sure discharging is disabled */ discharge_disable(); /* Enable over-current monitoring */ - adc_enable_watchdog(ADC_CH_A_SENSE, - MAX_CURRENT_FAST, 0); + adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, + 0); } } set_output_voltage(voltages[volt_idx].select); @@ -241,28 +241,22 @@ void pd_power_supply_reset(int port) } } -int pd_check_data_swap(int port, - enum pd_data_role data_role) +int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Allow data swap if we are a DFP, otherwise don't allow */ return (data_role == PD_ROLE_DFP) ? 1 : 0; } -void pd_execute_data_swap(int port, - enum pd_data_role data_role) +void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Do nothing */ } -void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags) +void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { /* If DFP, try to switch to UFP */ if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP) @@ -289,7 +283,7 @@ int pd_board_checks(void) __enter_hibernate(0, 0); } } else { - hib_to.val = get_time().val + 60*SECOND; + hib_to.val = get_time().val + 60 * SECOND; hib_to_ready = 1; } #endif @@ -319,8 +313,8 @@ int pd_board_checks(void) /* trigger the slow OCP iff all 4 samples are above the max */ if (count == 3) { debug_printf("OCP %d mA\n", - vbus_amp * VDDA_MV / CURR_GAIN * 1000 - / R_SENSE / ADC_SCALE); + vbus_amp * VDDA_MV / CURR_GAIN * 1000 / + R_SENSE / ADC_SCALE); pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OCP, NULL); fault = FAULT_OCP; /* reset over-current after 1 second */ @@ -349,8 +343,7 @@ int pd_board_checks(void) if ((output_is_enabled() && (vbus_volt > voltages[ovp_idx].ovp)) || (fault && (vbus_volt > voltages[ovp_idx].ovp_rec))) { if (!fault) { - debug_printf("OVP %d mV\n", - ADC_TO_VOLT_MV(vbus_volt)); + debug_printf("OVP %d mV\n", ADC_TO_VOLT_MV(vbus_volt)); pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_OVP, NULL); } fault = FAULT_OVP; @@ -361,7 +354,7 @@ int pd_board_checks(void) /* the discharge did not work properly */ if (discharge_is_enabled() && - (get_time().val > discharge_deadline.val)) { + (get_time().val > discharge_deadline.val)) { /* ensure we always finish a 2-step discharge */ volt_idx = discharge_volt_idx; set_output_voltage(voltages[volt_idx].select); @@ -369,8 +362,7 @@ int pd_board_checks(void) discharge_disable(); /* enable over-current monitoring */ adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, 0); - debug_printf("Disch FAIL %d mV\n", - ADC_TO_VOLT_MV(vbus_volt)); + debug_printf("Disch FAIL %d mV\n", ADC_TO_VOLT_MV(vbus_volt)); pd_log_event(PD_EVENT_PS_FAULT, 0, PS_FAULT_DISCH, NULL); fault = FAULT_DISCHARGE; /* reset it after 1 second */ @@ -390,7 +382,6 @@ int pd_board_checks(void) } return EC_SUCCESS; - } static void pd_adc_interrupt(void) @@ -407,10 +398,10 @@ static void pd_adc_interrupt(void) } else { /* discharge complete */ discharge_disable(); /* enable over-current monitoring */ - adc_enable_watchdog(ADC_CH_A_SENSE, - MAX_CURRENT_FAST, 0); + adc_enable_watchdog(ADC_CH_A_SENSE, MAX_CURRENT_FAST, + 0); } - } else {/* Over-current detection */ + } else { /* Over-current detection */ /* cut the power output */ pd_power_supply_reset(0); /* record a special fault */ @@ -453,9 +444,7 @@ static int svdm_response_svids(int port, uint32_t *payload) #define MODE_CNT 1 #define OPOS 1 -const uint32_t vdo_dp_mode[MODE_CNT] = { - VDO_MODE_GOOGLE(MODE_GOOGLE_FU) -}; +const uint32_t vdo_dp_mode[MODE_CNT] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) }; static int svdm_response_modes(int port, uint32_t *payload) { @@ -499,7 +488,7 @@ const struct svdm_response svdm_rsp = { }; __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { int cmd = PD_VDO_CMD(payload[0]); int rsize; @@ -507,8 +496,8 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE || !gfu_mode) return 0; - debug_printf("%pT] VDM/%d [%d] %08x\n", - PRINTF_TIMESTAMP_NOW, cnt, cmd, payload[0]); + debug_printf("%pT] VDM/%d [%d] %08x\n", PRINTF_TIMESTAMP_NOW, cnt, cmd, + payload[0]); *rpayload = payload; rsize = pd_custom_flash_vdm(port, cnt, payload); -- cgit v1.2.1 From 1e8e85c9ba9cdb7061d11f47589b28c84693c5ca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:10 -0600 Subject: chip/npcx/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8da2e52e1f20828726b48651bc99ab0d3142e39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729363 Reviewed-by: Jeremy Bettis --- chip/npcx/adc.c | 85 +++++++++++++++++++++++++++------------------------------ 1 file changed, 40 insertions(+), 45 deletions(-) diff --git a/chip/npcx/adc.c b/chip/npcx/adc.c index a31a0376dd..35859898d8 100644 --- a/chip/npcx/adc.c +++ b/chip/npcx/adc.c @@ -19,11 +19,11 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Maximum time we allow for an ADC conversion */ -#define ADC_TIMEOUT_US SECOND +#define ADC_TIMEOUT_US SECOND /* * ADC basic clock is from APB1. * In npcx5, APB1 clock frequency is (15 MHz / 4). @@ -34,23 +34,23 @@ * 7.5 MHz. */ #if defined(CHIP_FAMILY_NPCX5) -#define ADC_CLK 2000000 -#define ADC_DLY 0x03 -#define ADC_ADCCNF2 0x8B07 -#define ADC_GENDLY 0x0100 -#define ADC_MEAST 0x0001 +#define ADC_CLK 2000000 +#define ADC_DLY 0x03 +#define ADC_ADCCNF2 0x8B07 +#define ADC_GENDLY 0x0100 +#define ADC_MEAST 0x0001 #else -#define ADC_CLK 7500000 -#define ADC_DLY 0x02 -#define ADC_ADCCNF2 0x8901 -#define ADC_GENDLY 0x0100 -#define ADC_MEAST 0x0405 +#define ADC_CLK 7500000 +#define ADC_DLY 0x02 +#define ADC_ADCCNF2 0x8901 +#define ADC_GENDLY 0x0100 +#define ADC_MEAST 0x0405 #endif /* ADC conversion mode */ enum npcx_adc_conversion_mode { - ADC_CHN_CONVERSION_MODE = 0, - ADC_SCAN_CONVERSION_MODE = 1 + ADC_CHN_CONVERSION_MODE = 0, + ADC_SCAN_CONVERSION_MODE = 1 }; /* Global variables */ @@ -69,7 +69,7 @@ static volatile bool adc_done; */ void adc_freq_changed(void) { - uint8_t prescaler_divider = 0; + uint8_t prescaler_divider = 0; /* Set clock prescaler divider to ADC module*/ prescaler_divider = (uint8_t)(clock_get_apb1_freq() / ADC_CLK); @@ -91,8 +91,8 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, adc_freq_changed, HOOK_PRIO_DEFAULT); * @return TRUE/FALSE success/fail * @notes set SW-triggered interrupt conversion and one-shot mode in npcx chip */ -static int start_single_and_wait(enum npcx_adc_input_channel input_ch - , int timeout) +static int start_single_and_wait(enum npcx_adc_input_channel input_ch, + int timeout) { int event; @@ -107,7 +107,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch /* Set ADC conversion code to SW conversion mode */ SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD, - ADC_CHN_CONVERSION_MODE); + ADC_CHN_CONVERSION_MODE); /* Set conversion type to one-shot type */ CLEAR_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC); @@ -124,13 +124,12 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch /* Start conversion */ SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_START); -/* - * If tasks have started, we can suspend to the task that called us. - * If not, we need to busy poll for adc to finish before proceeding - */ + /* + * If tasks have started, we can suspend to the task that called us. + * If not, we need to busy poll for adc to finish before proceeding + */ if (IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) { if (!task_start_called()) { - /* Wait for the ADC interrupt to set the flag */ do { usleep(10); @@ -142,7 +141,7 @@ static int start_single_and_wait(enum npcx_adc_input_channel input_ch } else { /* Wait for interrupt */ event = task_wait_event_mask(TASK_EVENT_ADC_DONE, - timeout); + timeout); task_waiting = TASK_ID_INVALID; } @@ -213,8 +212,9 @@ int adc_read_data(enum npcx_adc_input_channel input_ch) uint16_t chn_data; chn_data = NPCX_CHNDAT(adc->input_ch); - value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * - adc->factor_mul / adc->factor_div + adc->shift; + value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * adc->factor_mul / + adc->factor_div + + adc->shift; return value; } @@ -241,11 +241,11 @@ int adc_read_channel(enum adc_channel ch) if (start_single_and_wait(adc->input_ch, ADC_TIMEOUT_US)) { chn_data = NPCX_CHNDAT(adc->input_ch); if ((adc->input_ch == - GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) - && (IS_BIT_SET(chn_data, - NPCX_CHNDAT_NEW))) { + GET_FIELD(NPCX_ASCADD, NPCX_ASCADD_SADDR_FIELD)) && + (IS_BIT_SET(chn_data, NPCX_CHNDAT_NEW))) { value = GET_FIELD(chn_data, NPCX_CHNDAT_CHDAT_FIELD) * - adc->factor_mul / adc->factor_div + adc->shift; + adc->factor_mul / adc->factor_div + + adc->shift; } else { value = ADC_READ_ERROR; } @@ -261,7 +261,7 @@ int adc_read_channel(enum adc_channel ch) } else { /* Set ADC conversion code to SW conversion mode */ SET_FIELD(NPCX_ADCCNF, NPCX_ADCCNF_ADCMD_FIELD, - ADC_SCAN_CONVERSION_MODE); + ADC_SCAN_CONVERSION_MODE); /* Set conversion type to repetitive (runs continuously) */ SET_BIT(NPCX_ADCCNF, NPCX_ADCCNF_ADCRPTC); /* Start conversion */ @@ -283,8 +283,7 @@ void npcx_adc_thresh_int_enable(int threshold_idx, int enable) enable = !!enable; if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) { - CPRINTS("Invalid ADC thresh index! (%d)", - threshold_idx); + CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx); return; } threshold_idx--; /* convert to 0-based */ @@ -313,24 +312,21 @@ void npcx_adc_register_thresh_irq(int threshold_idx, int shift; if ((threshold_idx < 1) || (threshold_idx > NPCX_ADC_THRESH_CNT)) { - CPRINTS("Invalid ADC thresh index! (%d)", - threshold_idx); + CPRINTS("Invalid ADC thresh index! (%d)", threshold_idx); return; } npcx_adc_ch = adc_channels[thresh_cfg->adc_ch].input_ch; if (!thresh_cfg->adc_thresh_cb) { - CPRINTS("No callback for ADC Threshold %d!", - threshold_idx); + CPRINTS("No callback for ADC Threshold %d!", threshold_idx); return; } /* Fill in the table */ - adc_thresh_irqs[threshold_idx-1] = thresh_cfg->adc_thresh_cb; + adc_thresh_irqs[threshold_idx - 1] = thresh_cfg->adc_thresh_cb; /* Select the channel */ - SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, - npcx_adc_ch); + SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_CHNSEL, npcx_adc_ch); if (thresh_cfg->lower_or_higher) SET_BIT(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_L_H); @@ -345,8 +341,7 @@ void npcx_adc_register_thresh_irq(int threshold_idx, raw_val = (thresh_cfg->thresh_assert - shift) * div / mul; CPRINTS("ADC THR%d: Setting THRVAL = %d, L_H: %d", threshold_idx, raw_val, thresh_cfg->lower_or_higher); - SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, - raw_val); + SET_FIELD(NPCX_THRCTL(threshold_idx), NPCX_THRCTL_THRVAL, raw_val); #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7 /* Disable deassertion threshold function */ @@ -396,7 +391,7 @@ static void adc_interrupt(void) IS_BIT_SET(NPCX_THRCTS, i)) { /* avoid clearing other threshold status */ thrcts = NPCX_THRCTS & - ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0); + ~GENMASK(NPCX_ADC_THRESH_CNT - 1, 0); /* Clear threshold status */ SET_BIT(thrcts, i); NPCX_THRCTS = thrcts; @@ -430,7 +425,7 @@ void adc_init(void) /* Enable ADC clock (bit4 mask = 0x10) */ clock_enable_peripheral(CGC_OFFSET_ADC, CGC_ADC_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Set Core Clock Division Factor in order to obtain the ADC clock */ adc_freq_changed(); -- cgit v1.2.1 From 195d11b6a50e0d15709c10b0f2f4aeaa950b909a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:58 -0600 Subject: chip/stm32/flash-stm32h7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7295e280bb1711696781fbffb62eb1bba548369b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729500 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32h7.c | 66 +++++++++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index 087ddbf062..841d8bf62a 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -45,7 +45,7 @@ * not what is called 'bank' in the common code (ie Write-Protect sectors) * both have the same number of 128KB blocks. */ -#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define HWBANK_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) #define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) @@ -74,8 +74,8 @@ struct flash_wp_state { static inline int calculate_flash_timeout(void) { - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int unlock(int bank) @@ -94,8 +94,8 @@ static int unlock(int bank) ignore_bus_fault(0); } - return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return (STM32_FLASH_CR(bank) & FLASH_CR_LOCK) ? EC_ERROR_UNKNOWN : + EC_SUCCESS; } static void lock(int bank) @@ -123,15 +123,14 @@ static int unlock_optb(void) ignore_bus_fault(0); } - return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return flash_option_bytes_locked() ? EC_ERROR_UNKNOWN : EC_SUCCESS; } static int commit_optb(void) { /* might use this before timer_init, cannot use get_time/usleep */ - int timeout = (FLASH_OPT_PRG_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + int timeout = (FLASH_OPT_PRG_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); STM32_FLASH_OPTCR(0) |= FLASH_OPTCR_OPTSTART; @@ -149,12 +148,11 @@ static void protect_blocks(uint32_t blocks) if (unlock_optb()) return; STM32_FLASH_WPSN_PRG(0) &= ~(blocks & BLOCKS_HWBANK_MASK); - STM32_FLASH_WPSN_PRG(1) &= ~((blocks >> BLOCKS_PER_HWBANK) - & BLOCKS_HWBANK_MASK); + STM32_FLASH_WPSN_PRG(1) &= + ~((blocks >> BLOCKS_PER_HWBANK) & BLOCKS_HWBANK_MASK); commit_optb(); } - /* * Helper function definitions for consistency with F4 to enable flash * physical unitesting @@ -226,7 +224,7 @@ bool flash_option_bytes_locked(void) * Always use bank 0 flash controller as there is only one option bytes * set for both banks. See http://b/181130245 */ - return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK); + return !!(STM32_FLASH_OPTCR(0) & FLASH_OPTCR_OPTLOCK); } bool flash_control_register_locked(void) @@ -252,8 +250,8 @@ bool flash_control_register_locked(void) static int is_wp_enabled(void) { #ifdef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE - return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) - != FLASH_OPTSR_RDP_LEVEL_0; + return (STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RDP_MASK) != + FLASH_OPTSR_RDP_LEVEL_0; #else return !!(STM32_FLASH_OPTSR_CUR(0) & FLASH_OPTSR_RSS1); #endif @@ -311,8 +309,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; /* select write parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; + STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) | + DEFAULT_PSIZE; /* set PG bit */ STM32_FLASH_CR(bank) |= FLASH_CR_PG; @@ -326,18 +324,21 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* write a 256-bit flash word */ if (unaligned) { - for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++, - data += 4) - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); + for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; + i++, data += 4) + *address++ = (uint32_t)data[0] | + (data[1] << 8) | (data[2] << 16) | + (data[3] << 24); } else { for (i = 0; i < CONFIG_FLASH_WRITE_SIZE / 4; i++) *address++ = *data32++; } /* Wait for writes to complete */ - for (i = 0; (STM32_FLASH_SR(bank) & - (FLASH_SR_WBNE | FLASH_SR_QW)) && (i < timeout); i++) + for (i = 0; + (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) && + (i < timeout); + i++) ; if (STM32_FLASH_SR(bank) & (FLASH_SR_WBNE | FLASH_SR_QW)) { @@ -386,16 +387,16 @@ int crec_flash_physical_erase(int offset, int size) STM32_FLASH_CCR(bank) = FLASH_CCR_ERR_MASK; /* select erase parallelism */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) - | DEFAULT_PSIZE; + STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) & ~FLASH_CR_PSIZE_MASK) | + DEFAULT_PSIZE; for (sect = offset / CONFIG_FLASH_ERASE_SIZE; sect < last; sect++) { timestamp_t deadline; /* select page to erase and PER bit */ - STM32_FLASH_CR(bank) = (STM32_FLASH_CR(bank) - & ~FLASH_CR_SNB_MASK) - | FLASH_CR_SER | FLASH_CR_SNB(sect); + STM32_FLASH_CR(bank) = + (STM32_FLASH_CR(bank) & ~FLASH_CR_SNB_MASK) | + FLASH_CR_SER | FLASH_CR_SNB(sect); /* set STRT bit : start erase */ STM32_FLASH_CR(bank) |= FLASH_CR_STRT; @@ -516,8 +517,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -549,11 +549,11 @@ int crec_flash_physical_restore_state(void) /* * If we have already jumped between images, an earlier image could * have applied write protection. We simply need to represent these - * irreversible flags to other components. + * irreversible flags to other components. */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) { access_disabled = prev->access_disabled; @@ -571,7 +571,7 @@ int crec_flash_pre_init(void) uint32_t reset_flags = system_get_reset_flags(); uint32_t prot_flags = crec_flash_get_protect(); uint32_t unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; + EC_FLASH_PROTECT_ERROR_INCONSISTENT; if (crec_flash_physical_restore_state()) return EC_SUCCESS; -- cgit v1.2.1 From 9e06ec41e97b6d20e8efd573e0cb551c05b7043f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:13 -0600 Subject: chip/stm32/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4fb98d5b078338a95b91896c26f67449d8766724 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729486 Reviewed-by: Jeremy Bettis --- chip/stm32/config_chip.h | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 4d630909e1..7554c5c03e 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -10,19 +10,19 @@ /* CPU core BFD configuration */ #include "core/cortex-m0/config_core.h" /* IRQ priorities */ -#define STM32_IRQ_EXT0_1_PRIORITY 1 -#define STM32_IRQ_EXT2_3_PRIORITY 1 -#define STM32_IRQ_EXTI4_15_PRIORITY 1 +#define STM32_IRQ_EXT0_1_PRIORITY 1 +#define STM32_IRQ_EXT2_3_PRIORITY 1 +#define STM32_IRQ_EXTI4_15_PRIORITY 1 #else /* CPU core BFD configuration */ #include "core/cortex-m/config_core.h" -#define STM32_IRQ_EXTI0_PRIORITY 1 -#define STM32_IRQ_EXTI1_PRIORITY 1 -#define STM32_IRQ_EXTI2_PRIORITY 1 -#define STM32_IRQ_EXTI3_PRIORITY 1 -#define STM32_IRQ_EXTI4_PRIORITY 1 -#define STM32_IRQ_EXTI9_5_PRIORITY 1 -#define STM32_IRQ_EXTI15_10_PRIORITY 1 +#define STM32_IRQ_EXTI0_PRIORITY 1 +#define STM32_IRQ_EXTI1_PRIORITY 1 +#define STM32_IRQ_EXTI2_PRIORITY 1 +#define STM32_IRQ_EXTI3_PRIORITY 1 +#define STM32_IRQ_EXTI4_PRIORITY 1 +#define STM32_IRQ_EXTI9_5_PRIORITY 1 +#define STM32_IRQ_EXTI15_10_PRIORITY 1 #endif /* Default to UART 1 for EC console */ @@ -87,10 +87,8 @@ /* Program is run directly from storage */ #define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE -#if !defined(CHIP_FAMILY_STM32F4) && \ - !defined(CHIP_FAMILY_STM32F7) && \ - !defined(CHIP_FAMILY_STM32H7) && \ - !defined(CHIP_VARIANT_STM32F09X) && \ +#if !defined(CHIP_FAMILY_STM32F4) && !defined(CHIP_FAMILY_STM32F7) && \ + !defined(CHIP_FAMILY_STM32H7) && !defined(CHIP_VARIANT_STM32F09X) && \ !defined(CHIP_VARIANT_STM32L431X) /* Compute the rest of the flash params from these */ #include "config_std_internal_flash.h" @@ -132,7 +130,7 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* * Use a timer to print a watchdog warning event before the actual watchdog @@ -148,7 +146,7 @@ #define CONFIG_RTC /* Number of peripheral request signals per DMA channel */ -#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 +#define STM32_DMA_PERIPHERALS_PER_CHANNEL 4 /* * Use DMA for UART transmit for all platforms. DMA for UART receive is @@ -165,13 +163,13 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT -#define GPIO_NAME_BY_PIN(port, index) #port#index +#define GPIO_NAME_BY_PIN(port, index) #port #index #define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) /* Prescaler values for PLL. Currently used only by STM32L476 and STM32L431. */ -#define STM32_PLLM 1 -#define STM32_PLLN 1 -#define STM32_PLLR 1 +#define STM32_PLLM 1 +#define STM32_PLLN 1 +#define STM32_PLLR 1 #endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From b8ed31147eaa6e1b31dd8f7a0f6510c5f70b872d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:33 -0600 Subject: board/taeko/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib636c4cb66efd9f8ff41a901a5770ceb8000ee70 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728963 Reviewed-by: Jeremy Bettis --- board/taeko/sensors.c | 93 +++++++++++++++++++++------------------------------ 1 file changed, 38 insertions(+), 55 deletions(-) diff --git a/board/taeko/sensors.c b/board/taeko/sensors.c index 22a349d95f..2354468ed1 100644 --- a/board/taeko/sensors.c +++ b/board/taeko/sensors.c @@ -22,8 +22,8 @@ #include "tablet_mode.h" #if 0 -#define CPRINTS(format, args...) ccprints(format, ## args) -#define CPRINTF(format, args...) ccprintf(format, ## args) +#define CPRINTS(format, args...) ccprints(format, ##args) +#define CPRINTF(format, args...) ccprintf(format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -70,23 +70,17 @@ static struct lsm6dso_data lsm6dso_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* The matrix for new DB */ -static const mat33_fp_t lid_ref_for_new_DB = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_ref_for_new_DB = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Matrix to rotate lid and base sensor into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t bma422_lid_accel = { .name = "Lid Accel - BMA", @@ -243,7 +237,6 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); #endif - static void board_detect_motionsensor(void) { int ret; @@ -260,8 +253,8 @@ static void board_detect_motionsensor(void) return; /* Check lid accel chip */ - ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, - LIS2DW12_WHO_AM_I_REG, &val); + ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG, + &val); if (ret == 0 && val == LIS2DW12_WHO_AM_I) { CPRINTS("LID_ACCEL is LIS2DW12"); return; @@ -281,8 +274,7 @@ static void board_detect_motionsensor(void) */ if (get_board_id() >= 2) { /* Need to change matrix when board ID >= 2 */ - bma422_lid_accel.rot_standard_ref = - &lid_ref_for_new_DB; + bma422_lid_accel.rot_standard_ref = &lid_ref_for_new_DB; } return; } @@ -293,7 +285,7 @@ static void board_detect_motionsensor(void) CPRINTS("No LID_ACCEL are detected"); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void baseboard_sensors_init(void) { @@ -316,7 +308,7 @@ static void baseboard_sensors_init(void) if (get_board_id() >= 2) { /* Need to change matrix when board ID >= 2 */ motion_sensors[LID_ACCEL].rot_standard_ref = - &lid_ref_for_new_DB; + &lid_ref_for_new_DB; } /* Enable gpio interrupt for base accelgyro sensor */ @@ -327,41 +319,32 @@ static void baseboard_sensors_init(void) gmr_tablet_switch_disable(); gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_DOWN); /* Gyro is not present, don't allow line to float */ - gpio_set_flags(GPIO_EC_IMU_INT_R_L, GPIO_INPUT | - GPIO_PULL_DOWN); + gpio_set_flags(GPIO_EC_IMU_INT_R_L, + GPIO_INPUT | GPIO_PULL_DOWN); } } DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_FAN] = { - .name = "FAN", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_FAN - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "CHARGER", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, - [TEMP_SENSOR_4_CPUCHOKE] = { - .name = "CPU CHOKE", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_CPUCHOKE - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_FAN] = { .name = "FAN", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_FAN }, + [TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, + [TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_CPUCHOKE }, }; - BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* @@ -374,8 +357,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -404,8 +387,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ -- cgit v1.2.1 From c6aed16103e68b3cba6ab50a66d68aae0c7cfe45 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:19 -0600 Subject: board/jacuzzi/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a3f6e441a8f76c44d9ac11fc01dfcc70516a173 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728517 Reviewed-by: Jeremy Bettis --- board/jacuzzi/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/jacuzzi/led.c b/board/jacuzzi/led.c index e76b73bc9a..0c53bdf41c 100644 --- a/board/jacuzzi/led.c +++ b/board/jacuzzi/led.c @@ -15,22 +15,27 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From d0854c9e09aa640d9340f2367746a50171c6ab6f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:12 -0600 Subject: board/servo_micro/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62920308f2f67fa3d2764f1ddb0210cd172bf8bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728904 Reviewed-by: Jeremy Bettis --- board/servo_micro/board.h | 47 ++++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/board/servo_micro/board.h b/board/servo_micro/board.h index 1983ee13e3..26e3a56ba6 100644 --- a/board/servo_micro/board.h +++ b/board/servo_micro/board.h @@ -33,9 +33,10 @@ #define CONFIG_STM_HWTIMER32 #define CONFIG_HW_CRC #define CONFIG_PVD -/* See 'Programmable voltage detector characteristics' in the STM32F072x8 Datasheet. - PVD Threshold 1 corresponds to a falling voltage threshold of min:2.09V, max:2.27V. */ -#define PVD_THRESHOLD (1) +/* See 'Programmable voltage detector characteristics' in the STM32F072x8 + Datasheet. PVD Threshold 1 corresponds to a falling voltage threshold of + min:2.09V, max:2.27V. */ +#define PVD_THRESHOLD (1) /* USB Configuration */ #define CONFIG_USB @@ -50,25 +51,25 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_USART4_STREAM 0 -#define USB_IFACE_UPDATE 1 -#define USB_IFACE_SPI 2 -#define USB_IFACE_CONSOLE 3 -#define USB_IFACE_I2C 4 -#define USB_IFACE_USART3_STREAM 5 -#define USB_IFACE_USART2_STREAM 6 -#define USB_IFACE_COUNT 7 +#define USB_IFACE_USART4_STREAM 0 +#define USB_IFACE_UPDATE 1 +#define USB_IFACE_SPI 2 +#define USB_IFACE_CONSOLE 3 +#define USB_IFACE_I2C 4 +#define USB_IFACE_USART3_STREAM 5 +#define USB_IFACE_USART2_STREAM 6 +#define USB_IFACE_COUNT 7 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_USART4_STREAM 1 -#define USB_EP_UPDATE 2 -#define USB_EP_SPI 3 -#define USB_EP_CONSOLE 4 -#define USB_EP_I2C 5 -#define USB_EP_USART3_STREAM 6 -#define USB_EP_USART2_STREAM 7 -#define USB_EP_COUNT 8 +#define USB_EP_CONTROL 0 +#define USB_EP_USART4_STREAM 1 +#define USB_EP_UPDATE 2 +#define USB_EP_SPI 3 +#define USB_EP_CONSOLE 4 +#define USB_EP_I2C 5 +#define USB_EP_USART3_STREAM 6 +#define USB_EP_USART2_STREAM 7 +#define USB_EP_COUNT 8 /* Enable console recasting of GPIO type. */ #define CONFIG_CMD_GPIO_EXTENDED @@ -76,7 +77,7 @@ /* Enable control of SPI over USB */ #define CONFIG_USB_SPI #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */ +#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */ /* This is not actually an EC so disable some features. */ #undef CONFIG_WATCHDOG_HELP @@ -93,8 +94,8 @@ #define CONFIG_I2C_XFER_LARGE_TRANSFER #undef CONFIG_USB_I2C_MAX_WRITE_COUNT #undef CONFIG_USB_I2C_MAX_READ_COUNT -#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4) -#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6) +#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4) +#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6) /* * Allow dangerous commands all the time, since we don't have a write protect -- cgit v1.2.1 From b3164588e53812aed6bfa5740f76dfb5bdbdb962 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:06 -0600 Subject: baseboard/brask/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I154ae4b571a4ac3bc9f4378eff137391fbb84fde Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727859 Reviewed-by: Jeremy Bettis --- baseboard/brask/usb_pd_policy.c | 80 ++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 46 deletions(-) diff --git a/baseboard/brask/usb_pd_policy.c b/baseboard/brask/usb_pd_policy.c index ddff378ae2..d76af26397 100644 --- a/baseboard/brask/usb_pd_policy.c +++ b/baseboard/brask/usb_pd_policy.c @@ -24,8 +24,8 @@ #include "usb_pd_vdo.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -85,49 +85,38 @@ int board_vbus_source_enabled(int port) #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { @@ -166,8 +155,7 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) } } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -176,7 +164,7 @@ static int svdm_tbt_compat_response_enter_mode( return 0; /* NAK */ if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); @@ -186,7 +174,7 @@ static int svdm_tbt_compat_response_enter_mode( * Enter Mode Command response. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); CPRINTS("UFP Enter TBT mode"); -- cgit v1.2.1 From 325c67d09257847128e4f11bcf32291f1e675d1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:58 -0600 Subject: chip/ish/ish_fwst.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8556c8d4f6da0958ca34518ff9b0c86c92b42bc0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729160 Reviewed-by: Jeremy Bettis --- chip/ish/ish_fwst.h | 102 ++++++++++++++++++++++++++-------------------------- 1 file changed, 51 insertions(+), 51 deletions(-) diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h index c114db3241..2782ac3af1 100644 --- a/chip/ish/ish_fwst.h +++ b/chip/ish/ish_fwst.h @@ -17,84 +17,84 @@ * IPC link is up(ready) * IPC can be used by other protocols */ -#define IPC_ISH_FWSTS_ILUP_FIELD 0x01 -#define IPC_ISH_FWSTS_ILUP_SHIFT 0 -#define IPC_ISH_FWSTS_ILUP_MASK \ - (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT) +#define IPC_ISH_FWSTS_ILUP_FIELD 0x01 +#define IPC_ISH_FWSTS_ILUP_SHIFT 0 +#define IPC_ISH_FWSTS_ILUP_MASK \ + (IPC_ISH_FWSTS_ILUP_FIELD << IPC_ISH_FWSTS_ILUP_SHIFT) /* * HECI layer is up(ready) */ -#define IPC_ISH_FWSTS_HUP_FIELD 0x01 -#define IPC_ISH_FWSTS_HUP_SHIFT 1 +#define IPC_ISH_FWSTS_HUP_FIELD 0x01 +#define IPC_ISH_FWSTS_HUP_SHIFT 1 #define IPC_ISH_FWSTS_HUP_MASK \ - (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT) + (IPC_ISH_FWSTS_HUP_FIELD << IPC_ISH_FWSTS_HUP_SHIFT) /* * ISH FW reason reason */ -#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F -#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2 +#define IPC_ISH_FWSTS_FAIL_REASON_FIELD 0x0F +#define IPC_ISH_FWSTS_FAIL_REASON_SHIFT 2 #define IPC_ISH_FWSTS_FAIL_REASON_MASK \ - (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT) + (IPC_ISH_FWSTS_FAIL_REASON_FIELD << IPC_ISH_FWSTS_FAIL_REASON_SHIFT) /* * ISH FW reset ID */ -#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F -#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8 +#define IPC_ISH_FWSTS_RESET_ID_FIELD 0x0F +#define IPC_ISH_FWSTS_RESET_ID_SHIFT 8 #define IPC_ISH_FWSTS_RESET_ID_MASK \ - (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT) + (IPC_ISH_FWSTS_RESET_ID_FIELD << IPC_ISH_FWSTS_RESET_ID_SHIFT) /* * ISH FW status type */ enum { - FWSTS_AFTER_RESET = 0, - FWSTS_WAIT_FOR_HOST = 4, - FWSTS_START_KERNEL_DMA = 5, - FWSTS_FW_IS_RUNNING = 7, - FWSTS_SENSOR_APP_LOADED = 8, - FWSTS_SENSOR_APP_RUNNING = 15 + FWSTS_AFTER_RESET = 0, + FWSTS_WAIT_FOR_HOST = 4, + FWSTS_START_KERNEL_DMA = 5, + FWSTS_FW_IS_RUNNING = 7, + FWSTS_SENSOR_APP_LOADED = 8, + FWSTS_SENSOR_APP_RUNNING = 15 }; /* * General ISH FW status */ -#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F -#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12 +#define IPC_ISH_FWSTS_FW_STATUS_FIELD 0x0F +#define IPC_ISH_FWSTS_FW_STATUS_SHIFT 12 #define IPC_ISH_FWSTS_FW_STATUS_MASK \ - (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT) + (IPC_ISH_FWSTS_FW_STATUS_FIELD << IPC_ISH_FWSTS_FW_STATUS_SHIFT) -#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16 +#define IPC_ISH_FWSTS_DMA0_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT 16 #define IPC_ISH_FWSTS_DMA0_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA0_IN_USE_FIELD << IPC_ISH_FWSTS_DMA0_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17 +#define IPC_ISH_FWSTS_DMA1_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT 17 #define IPC_ISH_FWSTS_DMA1_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA1_IN_USE_FIELD << IPC_ISH_FWSTS_DMA1_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18 +#define IPC_ISH_FWSTS_DMA2_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT 18 #define IPC_ISH_FWSTS_DMA2_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA2_IN_USE_FIELD << IPC_ISH_FWSTS_DMA2_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01 -#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19 +#define IPC_ISH_FWSTS_DMA3_IN_USE_FIELD 0x01 +#define IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT 19 #define IPC_ISH_FWSTS_DMA3_IN_USE_MASK \ - (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT) + (IPC_ISH_FWSTS_DMA3_IN_USE_FIELD << IPC_ISH_FWSTS_DMA3_IN_USE_SHIFT) -#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F -#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20 +#define IPC_ISH_FWSTS_POWER_STATE_FIELD 0x0F +#define IPC_ISH_FWSTS_POWER_STATE_SHIFT 20 #define IPC_ISH_FWSTS_POWER_STATE_MASK \ - (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT) + (IPC_ISH_FWSTS_POWER_STATE_FIELD << IPC_ISH_FWSTS_POWER_STATE_SHIFT) -#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07 -#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24 +#define IPC_ISH_FWSTS_AON_CHECK_FIELD 0x07 +#define IPC_ISH_FWSTS_AON_CHECK_SHIFT 24 #define IPC_ISH_FWSTS_AON_CHECK_MASK \ - (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT) + (IPC_ISH_FWSTS_AON_CHECK_FIELD << IPC_ISH_FWSTS_AON_CHECK_SHIFT) /* get ISH FW status register */ static inline uint32_t ish_fwst_get(void) @@ -105,7 +105,7 @@ static inline uint32_t ish_fwst_get(void) /* set IPC link up */ static inline void ish_fwst_set_ilup(void) { - IPC_ISH_FWSTS |= (1<> IPC_ISH_FWSTS_FAIL_REASON_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FAIL_REASON_MASK) >> + IPC_ISH_FWSTS_FAIL_REASON_SHIFT; } /* set reset id */ @@ -160,14 +160,14 @@ static inline void ish_fwst_set_reset_id(uint32_t val) uint32_t fwst = IPC_ISH_FWSTS; IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) | - (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); + (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); } /* get reset id */ static inline uint32_t ish_fwst_get_reset_id(void) { - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) - >> IPC_ISH_FWSTS_RESET_ID_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) >> + IPC_ISH_FWSTS_RESET_ID_SHIFT; } /* set general fw status */ @@ -176,14 +176,14 @@ static inline void ish_fwst_set_fw_status(uint32_t val) uint32_t fwst = IPC_ISH_FWSTS; IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) | - (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); + (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); } /* get general fw status */ static inline uint32_t ish_fwst_get_fw_status(void) { - return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) - >> IPC_ISH_FWSTS_FW_STATUS_SHIFT; + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) >> + IPC_ISH_FWSTS_FW_STATUS_SHIFT; } #endif /* __ISH_FWST_H */ -- cgit v1.2.1 From e8ec8f0b05110713ec14f197b66ae4e3f561127c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:09 -0600 Subject: zephyr/projects/herobrine/src/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iae60d7255999ff41ca86b8dfa0a8f7acc87f622d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730771 Reviewed-by: Jeremy Bettis --- zephyr/projects/herobrine/src/usbc_config.c | 33 ++++++++++++----------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/zephyr/projects/herobrine/src/usbc_config.c b/zephyr/projects/herobrine/src/usbc_config.c index 41319a75e9..148c7b6eb5 100644 --- a/zephyr/projects/herobrine/src/usbc_config.c +++ b/zephyr/projects/herobrine/src/usbc_config.c @@ -28,9 +28,8 @@ #include "usbc_ppc.h" #include "usbc/ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO Interrupt Handlers */ void tcpc_alert_event(enum gpio_signal signal) @@ -54,9 +53,9 @@ void tcpc_alert_event(enum gpio_signal signal) static void usba_oc_deferred(void) { /* Use next number after all USB-C ports to indicate the USB-A port */ - board_overcurrent_event(CONFIG_USB_PD_PORT_MAX_COUNT, - !gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl))); + board_overcurrent_event( + CONFIG_USB_PD_PORT_MAX_COUNT, + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_a0_oc_odl))); } DECLARE_DEFERRED(usba_oc_deferred); @@ -148,7 +147,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_POST_I2C); @@ -194,8 +193,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -223,7 +221,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -247,23 +244,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) @@ -272,11 +267,11 @@ uint16_t tcpc_get_alert_status(void) if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_int_odl))) if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_pd_rst_l))) status |= PD_STATUS_TCPC_ALERT_0; if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_int_odl))) if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_pd_rst_l))) status |= PD_STATUS_TCPC_ALERT_1; return status; -- cgit v1.2.1 From c5e3e603bdf80fe7d4d4c06f721a014c9dc432dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:12 -0600 Subject: board/gelarshie/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50c96fd05b10417216cb1afd575b4f42690a4edf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728393 Reviewed-by: Jeremy Bettis --- board/gelarshie/board.c | 156 ++++++++++++++++++------------------------------ 1 file changed, 57 insertions(+), 99 deletions(-) diff --git a/board/gelarshie/board.c b/board/gelarshie/board.c index b16e2f823f..9cade37b9f 100644 --- a/board/gelarshie/board.c +++ b/board/gelarshie/board.c @@ -37,10 +37,10 @@ #include "task.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -149,8 +149,7 @@ static void ks_change_deferred(void) proximity_detected = !(ks_attached && ks_open); CPRINTS("ks %s %s -> proximity %s", ks_attached ? "attached" : "detached", - ks_open ? "open" : "close", - proximity_detected ? "on" : "off"); + ks_open ? "open" : "close", proximity_detected ? "on" : "off"); debounced_ks_attached = ks_attached; debounced_ks_open = ks_open; @@ -172,41 +171,31 @@ static void switchcap_interrupt(enum gpio_signal signal) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -214,45 +203,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, /* Base detection */ - [ADC_BASE_DET] = { - "BASE_DET", - NPCX_ADC_CH5, - ADC_MAX_VOLT, - ADC_READ_MAX + 1, - 0 - }, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -270,16 +239,12 @@ const struct ln9310_config_t ln9310_config = { /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -344,11 +309,9 @@ static struct bmi_drv_data_t g_bmi260_data; bool is_bmi260_present; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -451,8 +414,8 @@ static void board_detect_motionsensor(void) /* Check base accelgyro chip */ bmi_read8(motion_sensors[LID_ACCEL].port, - motion_sensors[LID_ACCEL].i2c_spi_addr_flags, - BMI260_CHIP_ID, &val); + motion_sensors[LID_ACCEL].i2c_spi_addr_flags, BMI260_CHIP_ID, + &val); if (val == BMI260_CHIP_ID_MAJOR) { motion_sensors[LID_ACCEL] = motion_sensors_260[LID_ACCEL]; motion_sensors[LID_GYRO] = motion_sensors_260[LID_GYRO]; @@ -553,9 +516,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); void board_hibernate(void) { @@ -565,8 +528,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -663,8 +625,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -692,7 +653,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -716,24 +676,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From b6d2cf710ca9c84fc666eac2266d42246628a5cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:10 -0600 Subject: board/kukui_scp/mdp_ipi_message.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If0cb81c2e91273eabb97cedab439a418093396fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728597 Reviewed-by: Jeremy Bettis --- board/kukui_scp/mdp_ipi_message.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kukui_scp/mdp_ipi_message.h b/board/kukui_scp/mdp_ipi_message.h index bcedb58504..173b9487ec 100644 --- a/board/kukui_scp/mdp_ipi_message.h +++ b/board/kukui_scp/mdp_ipi_message.h @@ -11,9 +11,10 @@ struct mdp_msg_service { unsigned char msg[20]; }; -BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE); +BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); void mdp_common_init(void); void mdp_ipi_task_handler(void *pvParameters); -#endif // _MDP_IPI_MESSAGE_H +#endif // _MDP_IPI_MESSAGE_H -- cgit v1.2.1 From 907c74a5b3e389015ee3b9ec46c0d58d7e3025d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:57 -0600 Subject: board/blipper/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc5ba240b7d46dbba82d6f693f1ec7c1442bfabb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728033 Reviewed-by: Jeremy Bettis --- board/blipper/board.h | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/board/blipper/board.h b/board/blipper/board.h index 2e7ad6c6b5..219b3ec7f0 100644 --- a/board/blipper/board.h +++ b/board/blipper/board.h @@ -36,20 +36,20 @@ #define CONFIG_LED_ONOFF_STATES /*SENSOR*/ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCELGYRO_ICM42607 #define CONFIG_ACCELGYRO_BMI220 /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_I2C_XFER_LARGE_TRANSFER @@ -125,19 +125,14 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ ADC_CH_COUNT }; -- cgit v1.2.1 From ee2a54f1ccf8331a538d3e81b6a8a2d7941abb12 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:44 -0600 Subject: common/tablet_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie58e29fdd045337e8afdedb00669aef8f8a37974 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729736 Reviewed-by: Jeremy Bettis --- common/tablet_mode.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/common/tablet_mode.c b/common/tablet_mode.c index d6780f34a2..e870d2256b 100644 --- a/common/tablet_mode.c +++ b/common/tablet_mode.c @@ -13,8 +13,8 @@ #include "tablet_mode.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args) /* * Other code modules assume that notebook mode (i.e. tablet_mode = 0) at @@ -58,7 +58,6 @@ static void notify_tablet_mode_change(void) */ if (IS_ENABLED(CONFIG_HOSTCMD_EVENTS)) host_set_single_event(EC_HOST_EVENT_MODE_CHANGE); - } void tablet_set_mode(int mode, uint32_t trigger) @@ -105,9 +104,9 @@ void tablet_disable(void) #endif static void gmr_tablet_switch_interrupt_debounce(void) { - gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM) - ? board_sensor_at_360() - : !gpio_get_level(GPIO_TABLET_MODE_L); + gmr_sensor_at_360 = IS_ENABLED(CONFIG_GMR_TABLET_MODE_CUSTOM) ? + board_sensor_at_360() : + !gpio_get_level(GPIO_TABLET_MODE_L); /* * DPTF table is updated only when the board enters/exits completely @@ -116,9 +115,9 @@ static void gmr_tablet_switch_interrupt_debounce(void) * calculation and update DPTF table when lid angle > 300 degrees. */ if (IS_ENABLED(CONFIG_HOSTCMD_X86) && IS_ENABLED(CONFIG_DPTF)) { - acpi_dptf_set_profile_num(gmr_sensor_at_360 ? - DPTF_PROFILE_FLIPPED_360_MODE : - DPTF_PROFILE_CLAMSHELL); + acpi_dptf_set_profile_num( + gmr_sensor_at_360 ? DPTF_PROFILE_FLIPPED_360_MODE : + DPTF_PROFILE_CLAMSHELL); } /* * 1. Peripherals are disabled only when lid reaches 360 position (It's @@ -142,7 +141,7 @@ static void gmr_tablet_switch_interrupt_debounce(void) DECLARE_DEFERRED(gmr_tablet_switch_interrupt_debounce); /* Debounce time for gmr sensor tablet mode interrupt */ -#define GMR_SENSOR_DEBOUNCE_US (30 * MSEC) +#define GMR_SENSOR_DEBOUNCE_US (30 * MSEC) void gmr_tablet_switch_isr(enum gpio_signal signal) { @@ -206,7 +205,6 @@ static int command_settabletmode(int argc, char **argv) notify_tablet_mode_change(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode, - "[on | off | reset]", - "Manually force tablet mode to on, off or reset."); +DECLARE_CONSOLE_COMMAND(tabletmode, command_settabletmode, "[on | off | reset]", + "Manually force tablet mode to on, off or reset."); #endif -- cgit v1.2.1 From 869b92520ad2ab0683277338f03bc1ee3dcb3f01 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:34 -0600 Subject: baseboard/kalista/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib5643ee1ae4bc0bf5804aa5eba0cf00f597c9cc8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727909 Reviewed-by: Jeremy Bettis --- baseboard/kalista/baseboard.c | 123 ++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 66 deletions(-) diff --git a/baseboard/kalista/baseboard.c b/baseboard/kalista/baseboard.c index b06547106a..ef020ed6e7 100644 --- a/baseboard/kalista/baseboard.c +++ b/baseboard/kalista/baseboard.c @@ -48,8 +48,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint8_t board_version; static uint32_t oem; @@ -99,14 +99,15 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* TODO: Verify fan control and mft */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_FAN_PWR_EN, }; @@ -123,46 +124,36 @@ const struct fan_t fans[] = { BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "backlight", - .port = I2C_PORT_BACKLIGHT, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "pmic", - .port = I2C_PORT_PMIC, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "backlight", + .port = I2C_PORT_BACKLIGHT, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "pmic", + .port = I2C_PORT_PMIC, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -234,14 +225,14 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL) && - gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) + gpio_get_level(GPIO_USB_C0_PD_RST_ODL)) return PD_STATUS_TCPC_ALERT_0; return 0; } @@ -254,10 +245,10 @@ uint16_t tcpc_get_alert_status(void) * src/mainboard/google/${board}/acpi/dptf.asl */ const struct temp_sensor_t temp_sensors[] = { - {"TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, + { "TMP431_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP431_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -270,9 +261,11 @@ struct ec_thermal_config thermal_params[] = { * {Twarn, Thigh, X }, * fan_off, fan_max */ - {{0, C_TO_K(80), C_TO_K(81)}, {0, C_TO_K(78), 0}, - C_TO_K(4), C_TO_K(76)}, /* TMP431_Internal */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* TMP431_Sensor_1 */ + { { 0, C_TO_K(80), C_TO_K(81) }, + { 0, C_TO_K(78), 0 }, + C_TO_K(4), + C_TO_K(76) }, /* TMP431_Internal */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* TMP431_Sensor_1 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); @@ -441,9 +434,9 @@ int64_t get_time_dsw_pwrok(void) } const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_BLUE] = { 5, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -455,21 +448,20 @@ struct fan_step { /* Note: Do not make the fan on/off point equal to 0 or 100 */ static const struct fan_step fan_table0[] = { - {.on = 0, .off = 5, .rpm = 0}, - {.on = 30, .off = 5, .rpm = 2180}, - {.on = 49, .off = 46, .rpm = 2680}, - {.on = 53, .off = 50, .rpm = 3300}, - {.on = 58, .off = 54, .rpm = 3760}, - {.on = 63, .off = 59, .rpm = 4220}, - {.on = 68, .off = 64, .rpm = 4660}, - {.on = 75, .off = 70, .rpm = 4900}, + { .on = 0, .off = 5, .rpm = 0 }, + { .on = 30, .off = 5, .rpm = 2180 }, + { .on = 49, .off = 46, .rpm = 2680 }, + { .on = 53, .off = 50, .rpm = 3300 }, + { .on = 58, .off = 54, .rpm = 3760 }, + { .on = 63, .off = 59, .rpm = 4220 }, + { .on = 68, .off = 64, .rpm = 4660 }, + { .on = 75, .off = 70, .rpm = 4900 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) static const struct fan_step *fan_table = fan_table0; - static void cbi_init(void) { uint32_t val; @@ -489,8 +481,8 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1); static void setup_bj(void) { - enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? - BJ_135W_19V : BJ_90W_19V; + enum bj_adapter bj = (BJ_ADAPTER_135W_MASK & (1 << sku)) ? BJ_135W_19V : + BJ_90W_19V; gpio_set_level(GPIO_U22_90W, bj == BJ_90W_19V); } @@ -537,8 +529,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); -- cgit v1.2.1 From 6173343e797c51020921a2e56c10b2d5bb553ca5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:31 -0600 Subject: common/cbi_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf123d95f9af2295ac1dde2f07997bca111add5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729597 Reviewed-by: Jeremy Bettis --- common/cbi_gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cbi_gpio.c b/common/cbi_gpio.c index 7b9fb25ebb..ea7e13c629 100644 --- a/common/cbi_gpio.c +++ b/common/cbi_gpio.c @@ -11,7 +11,7 @@ #include "system.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args) static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len) { @@ -39,8 +39,8 @@ static int cbi_gpio_read(uint8_t offset, uint8_t *data, int len) } sku_id = system_get_sku_id(); - rv = cbi_set_board_info(CBI_TAG_SKU_ID, - (uint8_t *)&sku_id, sizeof(int)); + rv = cbi_set_board_info(CBI_TAG_SKU_ID, (uint8_t *)&sku_id, + sizeof(int)); if (rv) { CPRINTS("Failed (%d) to set SKU_ID tag", rv); err++; -- cgit v1.2.1 From 928eee4b68b6db7b8b50b26bc451545907344b04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:44 -0600 Subject: zephyr/projects/skyrim/usbc_config_guybrush.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifff125cdc9e0e77d1d5ae3a74084d50a9747426c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730805 Reviewed-by: Jeremy Bettis --- zephyr/projects/skyrim/usbc_config_guybrush.c | 50 ++++++++++----------------- 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c index 1d7afcbbb4..ef9a47e52c 100644 --- a/zephyr/projects/skyrim/usbc_config_guybrush.c +++ b/zephyr/projects/skyrim/usbc_config_guybrush.c @@ -31,22 +31,14 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); static void reset_nct38xx_port(int port); @@ -90,7 +82,7 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); * not needed as well. usb_mux.c can handle the situation * properly. */ -static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *); +static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t, bool *); struct usb_mux_driver usbc0_sbu_mux_driver = { .set = fsusb42umx_set_mux, }; @@ -194,8 +186,7 @@ DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; @@ -209,7 +200,7 @@ int board_set_active_charge_port(int port) * ahead and reset it so EN_SNK responds properly. */ if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } @@ -258,7 +249,7 @@ int board_set_active_charge_port(int port) * change because we'll brown out. */ if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } else { @@ -305,8 +296,7 @@ int board_set_active_charge_port(int port) * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv = EC_SUCCESS; @@ -316,12 +306,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port, return rv; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /* TODO: sbu_fault_interrupt from io expander */ @@ -373,7 +362,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -392,16 +380,16 @@ uint16_t tcpc_get_alert_status(void) * its reset line active. */ if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c0_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_0; } if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c1_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_1; } -- cgit v1.2.1 From a40fac9ffd1bb4ff80c33badfbca9b75333dd4b2 Mon Sep 17 00:00:00 2001 From: Manoj Gupta Date: Tue, 28 Jun 2022 02:05:03 +0000 Subject: Makefile.toolchain: Add -no-pie to more places Add -no-pie link flag to disable position independent code in more places. This is needed since GCC will be configured to use position independent code by default. BUG=b:236984388 TEST=CQ BRANCH=none Signed-off-by: Manoj Gupta Change-Id: I41ab27779218e84c5891a286a43c7b51776eed0b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727781 Tested-by: Manoj Gupta Reviewed-by: Jack Rosenthal Reviewed-by: Jeremy Bettis Commit-Queue: Manoj Gupta --- Makefile.toolchain | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile.toolchain b/Makefile.toolchain index b9f7c2005a..6b82885522 100644 --- a/Makefile.toolchain +++ b/Makefile.toolchain @@ -173,7 +173,7 @@ HOST_CXXFLAGS=$(HOST_CFLAGS) ifneq (${SYSROOT},) LDFLAGS_EXTRA+=--sysroot=${SYSROOT} endif -LDFLAGS=-nostdlib -g -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \ +LDFLAGS=-nostdlib -g -no-pie -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \ $(LDFLAGS_EXTRA) $(CFLAGS_CPU) MEMSIZE_FLAGS= ifeq ($(cc-name),gcc) @@ -182,12 +182,12 @@ endif BUILD_LDFLAGS=$(LIBFTDIUSB_LDLIBS) HOST_LDFLAGS=$(LIBFTDIUSB_LDLIBS) HOST_TEST_LDFLAGS=-Wl,-T core/host/host_exe.lds -lrt -pthread -rdynamic -lm\ - -fuse-ld=bfd \ + -fuse-ld=bfd -no-pie \ $(if $(TEST_COVERAGE), --coverage,) \ $(if $(TEST_ASAN), -fsanitize=address) \ $(if $(TEST_MSAN), -fsanitize=memory) \ $(if $(TEST_UBSAN), ${UBSAN_FLAGS}) \ - $(if $(TEST_FUZZ), -fsanitize=fuzzer -no-pie) + $(if $(TEST_FUZZ), -fsanitize=fuzzer) # utility function to provide overridable defaults # $1: name of variable to set -- cgit v1.2.1 From 1068145fd3ad4a37aab2fbc2d89bb057d83e132d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:59 -0600 Subject: board/servo_v4p1/ina231s.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3c8404f9fca330570a31f837a6720bd20ebfea2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728926 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/ina231s.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/servo_v4p1/ina231s.c b/board/servo_v4p1/ina231s.c index 3382686f3f..92e60d8248 100644 --- a/board/servo_v4p1/ina231s.c +++ b/board/servo_v4p1/ina231s.c @@ -7,9 +7,9 @@ #include "ina2xx.h" #include "util.h" -#define PP_DUT_IDX 0 -#define PP_CHG_IDX 1 -#define SR_CHG_IDX 2 +#define PP_DUT_IDX 0 +#define PP_CHG_IDX 1 +#define SR_CHG_IDX 2 void init_ina231s(void) { -- cgit v1.2.1 From 0febde5ceaa6ec1016dfe84903a628b9c0cdd147 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:07 -0600 Subject: driver/retimer/anx7483.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If9c50ad2a3255b5fe2869fb54065029e23f064b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730038 Reviewed-by: Jeremy Bettis --- driver/retimer/anx7483.c | 291 +++++++++++++++++++++++------------------------ 1 file changed, 145 insertions(+), 146 deletions(-) diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index 6804fd3de8..beb1149715 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -19,11 +19,11 @@ * Programming guide specifies it may be as much as 30ms after chip power on * before it's ready for i2c */ -#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 +#define ANX7483_I2C_WAKE_TIMEOUT_MS 30 #define ANX7483_I2C_WAKE_RETRY_DELAY_US 5000 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Tuning defaults */ struct anx7483_tuning_set { @@ -32,163 +32,162 @@ struct anx7483_tuning_set { }; static struct anx7483_tuning_set anx7483_usb_enabled[] = { - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT}, - - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_OUT }, + + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dp_enabled[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_noflip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, }; static struct anx7483_tuning_set anx7483_dock_flip[] = { - {ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF}, - - {ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - {ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF}, - - {ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - {ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF}, - - {ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - {ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE}, - - {ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - {ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE}, - - {ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - {ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF}, - - {ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, - {ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN}, - {ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN}, + { ANX7483_AUX_SNOOPING_CTRL_REG, ANX7483_AUX_SNOOPING_DEF }, + + { ANX7483_URX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_DRX2_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_URX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + { ANX7483_UTX1_PORT_CFG2_REG, ANX7483_CFG2_DEF }, + + { ANX7483_URX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_DRX2_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_URX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + { ANX7483_UTX1_PORT_CFG0_REG, ANX7483_CFG0_DEF }, + + { ANX7483_URX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + { ANX7483_DRX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_ENABLE }, + + { ANX7483_URX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_UTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX2_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DTX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + { ANX7483_DRX1_PORT_CFG4_REG, ANX7483_CFG4_TERM_DISABLE }, + + { ANX7483_URX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_UTX1_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_URX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + { ANX7483_DRX2_PORT_CFG1_REG, ANX7483_CFG1_DEF }, + + { ANX7483_URX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_URX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_UTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_UTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DRX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DRX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, + { ANX7483_DTX1_PORT_CFG3_REG, ANX7483_CFG3_100Ohm_IN }, + { ANX7483_DTX2_PORT_CFG3_REG, ANX7483_CFG3_90Ohm_IN }, }; -static inline int anx7483_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7483_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7483_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7483_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } @@ -324,7 +323,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, if (pin == ANX7483_PIN_UTX1) reg = ANX7483_UTX1_PORT_CFG0_REG; - else if (pin == ANX7483_PIN_UTX2) + else if (pin == ANX7483_PIN_UTX2) reg = ANX7483_UTX2_PORT_CFG0_REG; else if (pin == ANX7483_PIN_URX1) reg = ANX7483_URX1_PORT_CFG0_REG; -- cgit v1.2.1 From 96af7e505bf1b78bbeb1d115d81420df9d585072 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:14 -0600 Subject: baseboard/volteer/battery_presence.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3a42b6446ce113b787c1beafa3a8e20258cf57c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727948 Reviewed-by: Jeremy Bettis --- baseboard/volteer/battery_presence.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/baseboard/volteer/battery_presence.c b/baseboard/volteer/battery_presence.c index 4953d7a49e..747f364088 100644 --- a/baseboard/volteer/battery_presence.c +++ b/baseboard/volteer/battery_presence.c @@ -24,8 +24,9 @@ static bool battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } __overridable bool board_battery_is_initialized(void) -- cgit v1.2.1 From 0211d98b16c846268fe37f8ae6ee3de08160ec10 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:39 -0600 Subject: board/agah/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I63175112282955acb059da9500b3385449cf8871 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727975 Reviewed-by: Jeremy Bettis --- board/agah/usbc_config.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/board/agah/usbc_config.c b/board/agah/usbc_config.c index 0902f2f799..aca14304dd 100644 --- a/board/agah/usbc_config.c +++ b/board/agah/usbc_config.c @@ -33,8 +33,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -116,18 +116,17 @@ const static struct ps8818_reg_val equalizer_default_table[] = { #define NUM_EQ_DEFAULT_ARRAY ARRAY_SIZE(equalizer_default_table) -int board_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +int board_ps8818_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; int i; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { - /* Boost the USB gain */ for (i = 0; i < NUM_EQ_DEFAULT_ARRAY; i++) - rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + rv |= ps8818_i2c_field_update8( + me, PS8818_REG_PAGE1, equalizer_default_table[i].reg, equalizer_default_table[i].mask, equalizer_default_table[i].val); @@ -136,11 +135,10 @@ int board_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv |= ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); } return rv; @@ -203,8 +201,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -215,7 +213,7 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) void board_reset_pd_mcu(void) { - /* There's no reset pin on TCPC */ + /* There's no reset pin on TCPC */ } static void board_tcpc_init(void) -- cgit v1.2.1 From 20e1775575b96bb5e583c715e8e641eff2675483 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:41 -0600 Subject: include/power.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic750ef8156603f04b4cb8e264d74415749225473 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730380 Reviewed-by: Jeremy Bettis --- include/power.h | 91 +++++++++++++++++++++++++++++---------------------------- 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/include/power.h b/include/power.h index 6200392b95..f826f178e4 100644 --- a/include/power.h +++ b/include/power.h @@ -14,33 +14,33 @@ #include "gpio_signal.h" #include "task_id.h" -FORWARD_DECLARE_ENUM(power_state) { +FORWARD_DECLARE_ENUM(power_state){ /* Steady states */ - POWER_G3 = 0, /* - * System is off (not technically all the way into G3, - * which means totally unpowered...) - */ - POWER_S5, /* System is soft-off */ - POWER_S4, /* System is suspended to disk */ - POWER_S3, /* Suspend; RAM on, processor is asleep */ - POWER_S0, /* System is on */ + POWER_G3 = 0, /* + * System is off (not technically all the way into G3, + * which means totally unpowered...) + */ + POWER_S5, /* System is soft-off */ + POWER_S4, /* System is suspended to disk */ + POWER_S3, /* Suspend; RAM on, processor is asleep */ + POWER_S0, /* System is on */ #ifdef CONFIG_POWER_S0IX POWER_S0ix, #endif /* Transitions */ - POWER_G3S5, /* G3 -> S5 (at system init time) */ - POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ - POWER_S3S0, /* S3 -> S0 */ - POWER_S0S3, /* S0 -> S3 */ - POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ - POWER_S5G3, /* S5 -> G3 */ - POWER_S3S4, /* S3 -> S4 */ - POWER_S4S3, /* S4 -> S3 */ - POWER_S4S5, /* S4 -> S5 */ - POWER_S5S4, /* S5 -> S4 */ + POWER_G3S5, /* G3 -> S5 (at system init time) */ + POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ + POWER_S3S0, /* S3 -> S0 */ + POWER_S0S3, /* S0 -> S3 */ + POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ + POWER_S5G3, /* S5 -> G3 */ + POWER_S3S4, /* S3 -> S4 */ + POWER_S4S3, /* S4 -> S3 */ + POWER_S4S5, /* S4 -> S5 */ + POWER_S5S4, /* S5 -> S4 */ #ifdef CONFIG_POWER_S0IX - POWER_S0ixS0, /* S0ix -> S0 */ - POWER_S0S0ix, /* S0 -> S0ix */ + POWER_S0ixS0, /* S0ix -> S0 */ + POWER_S0S0ix, /* S0 -> S0ix */ #endif }; @@ -58,18 +58,18 @@ FORWARD_DECLARE_ENUM(power_state) { * +-----------------+------------------------------------+ */ -#define POWER_SIGNAL_ACTIVE_STATE BIT(0) -#define POWER_SIGNAL_ACTIVE_LOW (0 << 0) -#define POWER_SIGNAL_ACTIVE_HIGH BIT(0) +#define POWER_SIGNAL_ACTIVE_STATE BIT(0) +#define POWER_SIGNAL_ACTIVE_LOW (0 << 0) +#define POWER_SIGNAL_ACTIVE_HIGH BIT(0) -#define POWER_SIGNAL_INTR_STATE BIT(1) -#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1) +#define POWER_SIGNAL_INTR_STATE BIT(1) +#define POWER_SIGNAL_DISABLE_AT_BOOT BIT(1) /* Information on an power signal */ struct power_signal_info { - enum gpio_signal gpio; /* GPIO for signal */ - uint32_t flags; /* See POWER_SIGNAL_* macros */ - const char *name; /* Name of signal */ + enum gpio_signal gpio; /* GPIO for signal */ + uint32_t flags; /* See POWER_SIGNAL_* macros */ + const char *name; /* Name of signal */ }; /* @@ -161,7 +161,6 @@ int power_wait_signals_timeout(uint32_t want, int timeout); */ int power_wait_mask_signals_timeout(uint32_t want, uint32_t mask, int timeout); - /** * Set the low-level power chipset state. * @@ -177,7 +176,8 @@ void power_set_state(enum power_state new_state); #ifdef CONFIG_AP_POWER_CONTROL enum power_state power_get_state(void); #else -static inline enum power_state power_get_state(void) { +static inline enum power_state power_get_state(void) +{ return POWER_G3; } #endif @@ -208,7 +208,9 @@ enum power_state power_handle_state(enum power_state state); #ifdef CONFIG_AP_POWER_CONTROL void power_signal_interrupt(enum gpio_signal signal); #else -static inline void power_signal_interrupt(enum gpio_signal signal) { } +static inline void power_signal_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_AP_POWER_CONTROL */ /** @@ -254,7 +256,7 @@ void power_set_host_sleep_state(enum host_sleep_event state); /* Context to pass to a host sleep command handler. */ struct host_sleep_event_context { uint32_t sleep_transitions; /* Number of sleep transitions observed */ - uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ + uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ }; /** @@ -264,9 +266,9 @@ struct host_sleep_event_context { * @param state Current host sleep state updated by the host. * @param ctx Possible sleep parameters and return values, depending on state. */ -__override_proto void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx); +__override_proto void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx); /** * Provide callback to allow board to take any action on host sleep event @@ -274,8 +276,8 @@ __override_proto void power_chipset_handle_host_sleep_event( * * @param state Current host sleep state updated by the host. */ -__override_proto void power_board_handle_host_sleep_event( - enum host_sleep_event state); +__override_proto void +power_board_handle_host_sleep_event(enum host_sleep_event state); /* * This is the default state of host sleep event. Calls to @@ -283,7 +285,7 @@ __override_proto void power_board_handle_host_sleep_event( * value. EC components listening to host sleep event updates can check for this * special value to know if the state was reset. */ -#define HOST_SLEEP_EVENT_DEFAULT_RESET 0 +#define HOST_SLEEP_EVENT_DEFAULT_RESET 0 enum sleep_notify_type { SLEEP_NOTIFY_NONE, @@ -337,8 +339,8 @@ enum sleep_hang_type { * * @param hang_type Host sleep hang type detected. */ -__override_proto void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type); +__override_proto void +power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type); /** * Provide callback to allow board to take action on host sleep hang @@ -349,8 +351,8 @@ __override_proto void power_chipset_handle_sleep_hang( * * @param hang_type Host sleep hang type detected. */ -__override_proto void power_board_handle_sleep_hang( - enum sleep_hang_type hang_type); +__override_proto void +power_board_handle_sleep_hang(enum sleep_hang_type hang_type); /** * Start the suspend process. @@ -422,7 +424,6 @@ void power_5v_enable(task_id_t tid, int enable); void test_power_common_state(void); #endif - #ifdef CONFIG_POWERSEQ_FAKE_CONTROL /** * Enable a fake S0 state @@ -442,4 +443,4 @@ void power_fake_s0(void); void power_fake_disable(void); #endif /* defined(CONFIG_POWER_FAKE_CONTROL) */ -#endif /* __CROS_EC_POWER_H */ +#endif /* __CROS_EC_POWER_H */ -- cgit v1.2.1 From 27e7bbc502d58aba5ead7816b318ae34d5521f67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:19 -0600 Subject: driver/nfc/ctn730.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I397db0b811d1269717526ae52787c785399e03a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730031 Reviewed-by: Jeremy Bettis --- driver/nfc/ctn730.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c index 775149e659..45598f76b9 100644 --- a/driver/nfc/ctn730.c +++ b/driver/nfc/ctn730.c @@ -31,10 +31,10 @@ static const int _wake_up_delay_ms = 10; static const int _detection_interval_ms = 500; /* Buffer size for i2c read & write */ -#define CTN730_MESSAGE_BUFFER_SIZE 0x20 +#define CTN730_MESSAGE_BUFFER_SIZE 0x20 /* This driver isn't compatible with big endian. */ -BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__); +BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__); #define CPRINTS(fmt, args...) cprints(CC_PCHG, "CTN730: " fmt, ##args) @@ -158,8 +158,7 @@ static int _i2c_read(int i2c_port, uint8_t *in, int in_len) static void _print_header(const struct ctn730_msg *msg) { - CPRINTS("%s_%s", - _text_instruction(msg->instruction), + CPRINTS("%s_%s", _text_instruction(msg->instruction), _text_message_type(msg->message_type)); } @@ -206,9 +205,9 @@ static int ctn730_init(struct pchg *ctx) cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND; cmd->instruction = WLC_HOST_CTRL_RESET; cmd->length = WLC_HOST_CTRL_RESET_CMD_SIZE; - cmd->payload[0] = ctx->mode == PCHG_MODE_NORMAL - ? WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL - : WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD; + cmd->payload[0] = ctx->mode == PCHG_MODE_NORMAL ? + WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL : + WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD; /* TODO: Run 1 sec timeout timer. */ rv = _send_command(ctx, cmd); @@ -510,8 +509,8 @@ static int ctn730_get_soc(struct pchg *ctx) static int ctn730_update_open(struct pchg *ctx) { - uint8_t buf[sizeof(struct ctn730_msg) - + WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE]; + uint8_t buf[sizeof(struct ctn730_msg) + + WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE]; struct ctn730_msg *cmd = (void *)buf; uint32_t version = ctx->update.version; int rv; @@ -531,16 +530,16 @@ static int ctn730_update_open(struct pchg *ctx) static int ctn730_update_write(struct pchg *ctx) { - uint8_t buf[sizeof(struct ctn730_msg) - + WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE]; + uint8_t buf[sizeof(struct ctn730_msg) + + WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE]; struct ctn730_msg *cmd = (void *)buf; uint32_t *a = (void *)cmd->payload; uint8_t *d = (void *)&cmd->payload[CTN730_FLASH_ADDR_SIZE]; int rv; /* Address is 3 bytes. FW size must be a multiple of 128 bytes. */ - if (ctx->update.addr & GENMASK(31, 24) - || ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE) + if (ctx->update.addr & GENMASK(31, 24) || + ctx->update.size != WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE) return EC_ERROR_INVAL; cmd->message_type = CTN730_MESSAGE_TYPE_COMMAND; @@ -563,8 +562,8 @@ static int ctn730_update_write(struct pchg *ctx) static int ctn730_update_close(struct pchg *ctx) { - uint8_t buf[sizeof(struct ctn730_msg) - + WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE]; + uint8_t buf[sizeof(struct ctn730_msg) + + WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE]; struct ctn730_msg *cmd = (void *)buf; uint32_t *crc32 = (void *)cmd->payload; int rv; -- cgit v1.2.1 From 3c8e30a84dd0489de5205ed7527b2b8dba4f3e63 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:08 -0600 Subject: board/osiris/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I058af98a401e9a43980ea85cd2eaa58f4347122b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728804 Reviewed-by: Jeremy Bettis --- board/osiris/usbc_config.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/osiris/usbc_config.c b/board/osiris/usbc_config.c index 9a165ecdcc..fc85e6783a 100644 --- a/board/osiris/usbc_config.c +++ b/board/osiris/usbc_config.c @@ -32,8 +32,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -94,7 +94,6 @@ BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - /* * USB3 MB/DB mux configuration - the top level mux still needs to be set * to the virtual_usb_mux_driver so the AP gets notified of mux changes @@ -144,7 +143,6 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); - #ifdef CONFIG_CHARGE_RAMP_SW /* @@ -169,8 +167,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -220,7 +218,6 @@ static void board_tcpc_init(void) /* Enable BC1.2 interrupts. */ gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); - } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); -- cgit v1.2.1 From ee50624bd46eb9278d7da2050c470d21c12aeb94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:56 -0600 Subject: board/munna/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87b65901e7124ce30b4456bd73a8cca6c4c2056e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728711 Reviewed-by: Jeremy Bettis --- board/munna/led.c | 53 +++++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/board/munna/led.c b/board/munna/led.c index fa4f46b6ab..903e5a8d76 100644 --- a/board/munna/led.c +++ b/board/munna/led.c @@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor -led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From 22790d7b9c5303f27b75bc1e5d51acd8263b9cbf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:25 -0600 Subject: board/hoho/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d430c4cf14213a5ee571b2498d5e64aede931be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728324 Reviewed-by: Jeremy Bettis --- board/hoho/usb_pd_pdo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/hoho/usb_pd_pdo.c b/board/hoho/usb_pd_pdo.c index 19b5d127a5..20ebd7d9fe 100644 --- a/board/hoho/usb_pd_pdo.c +++ b/board/hoho/usb_pd_pdo.c @@ -13,6 +13,6 @@ const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); /* Fake PDOs : we just want our pre-defined voltages */ const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP), + PDO_FIXED(5000, 500, PDO_FIXED_COMM_CAP), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); -- cgit v1.2.1 From e789538756b8a5943db359d44f8983630ed06f02 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:44 -0600 Subject: util/uut/opr.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic75fe5e4e0319de8f4a9f167cf3d96af5b24fd2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730666 Reviewed-by: Jeremy Bettis --- util/uut/opr.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/util/uut/opr.h b/util/uut/opr.h index 3b166f0c7e..a9c0336ed0 100644 --- a/util/uut/opr.h +++ b/util/uut/opr.h @@ -15,16 +15,16 @@ */ /* Baud rate scan steps: */ -#define BR_BIG_STEP 20 /* in percents from current baud rate */ -#define BR_MEDIUM_STEP 10 /* in percents from current baud rate */ -#define BR_SMALL_STEP 1 /* in percents from current baud rate */ -#define BR_MIN_STEP 5 /* in absolute baud rate units */ -#define BR_LOW_LIMIT 400 /* Automatic BR detection starts at this value */ +#define BR_BIG_STEP 20 /* in percents from current baud rate */ +#define BR_MEDIUM_STEP 10 /* in percents from current baud rate */ +#define BR_SMALL_STEP 1 /* in percents from current baud rate */ +#define BR_MIN_STEP 5 /* in absolute baud rate units */ +#define BR_LOW_LIMIT 400 /* Automatic BR detection starts at this value */ #define BR_HIGH_LIMIT 150000 /* Automatic BR detection ends at this value */ -#define OPR_WRITE_MEM "wr" /* Write To Memory/Flash */ -#define OPR_READ_MEM "rd" /* Read From Memory/Flash */ -#define OPR_EXECUTE_EXIT "go" /* Execute a non-return code */ +#define OPR_WRITE_MEM "wr" /* Write To Memory/Flash */ +#define OPR_READ_MEM "rd" /* Read From Memory/Flash */ +#define OPR_EXECUTE_EXIT "go" /* Execute a non-return code */ #define OPR_EXECUTE_CONT "call" /* Execute returnable code */ enum sync_result { -- cgit v1.2.1 From bf27fa10250410bc7a2019f669da092d47686e3b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:34 -0600 Subject: chip/stm32/usb_endpoints.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I813085a5b6c018496c7d7d13ae65947c02dab39c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729552 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_endpoints.c | 128 +++++++++++++++++---------------------------- 1 file changed, 47 insertions(+), 81 deletions(-) diff --git a/chip/stm32/usb_endpoints.c b/chip/stm32/usb_endpoints.c index 7cdff25a6a..e08a69f759 100644 --- a/chip/stm32/usb_endpoints.c +++ b/chip/stm32/usb_endpoints.c @@ -12,7 +12,7 @@ #include "usb_hw.h" typedef void (*xfer_func)(void); -typedef void (*evt_func) (enum usb_ep_event evt); +typedef void (*evt_func)(enum usb_ep_event evt); #if defined(CHIP_FAMILY_STM32F4) #define iface_arguments struct usb_setup_packet *req @@ -44,18 +44,18 @@ int iface_undefined(iface_arguments) #define table(type, name, x) x -#define endpoint_tx(number) \ +#define endpoint_tx(number) \ extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _tx(void); -#define endpoint_rx(number) \ + ep_##number##_tx(void); +#define endpoint_rx(number) \ extern void __attribute__((used, weak, alias("ep_undefined"))) \ - ep_ ## number ## _rx(void); -#define endpoint_evt(number) \ + ep_##number##_rx(void); +#define endpoint_evt(number) \ extern void __attribute__((used, weak, alias("ep_evt_undefined"))) \ - ep_ ## number ## _evt(enum usb_ep_event evt); -#define interface(number) \ + ep_##number##_evt(enum usb_ep_event evt); +#define interface(number) \ extern int __attribute__((used, weak, alias("iface_undefined"))) \ - iface_ ## number ## _request(iface_arguments); + iface_##number##_request(iface_arguments); #define null @@ -79,20 +79,23 @@ int iface_undefined(iface_arguments) #endif /* __clang__ */ /* align function pointers on a 32-bit boundary */ -#define table(type, name, x) type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name ",\"a\" @"))) = { x }; -#define null (void*)0 +#define table(type, name, x) \ + type name[] __attribute__((aligned(4), section(".rodata.usb_ep." #name \ + ",\"a\" @"))) = { x }; +#define null (void *)0 #define ep_(num, suf) CONCAT3(ep_, num, suf) #define ep(num, suf) ep_(num, suf) #define endpoint_tx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_tx, #define endpoint_rx(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_rx, #define endpoint_evt(number) \ - [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _evt, -#define interface(number) \ - [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request, + [number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_##number##_evt, +#define interface(number) \ + [number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = \ + iface_##number##_request, #endif /* PASS 2 */ /* @@ -102,73 +105,36 @@ int iface_undefined(iface_arguments) * It all sorts out nicely */ table(xfer_func, usb_ep_tx, - endpoint_tx(15) - endpoint_tx(14) - endpoint_tx(13) - endpoint_tx(12) - endpoint_tx(11) - endpoint_tx(10) - endpoint_tx(9) - endpoint_tx(8) - endpoint_tx(7) - endpoint_tx(6) - endpoint_tx(5) - endpoint_tx(4) - endpoint_tx(3) - endpoint_tx(2) - endpoint_tx(1) - endpoint_tx(0) -) - -table(xfer_func, usb_ep_rx, - endpoint_rx(15) - endpoint_rx(14) - endpoint_rx(13) - endpoint_rx(12) - endpoint_rx(11) - endpoint_rx(10) - endpoint_rx(9) - endpoint_rx(8) - endpoint_rx(7) - endpoint_rx(6) - endpoint_rx(5) - endpoint_rx(4) - endpoint_rx(3) - endpoint_rx(2) - endpoint_rx(1) - endpoint_rx(0) -) - -table(evt_func, usb_ep_event, - endpoint_evt(15) - endpoint_evt(14) - endpoint_evt(13) - endpoint_evt(12) - endpoint_evt(11) - endpoint_evt(10) - endpoint_evt(9) - endpoint_evt(8) - endpoint_evt(7) - endpoint_evt(6) - endpoint_evt(5) - endpoint_evt(4) - endpoint_evt(3) - endpoint_evt(2) - endpoint_evt(1) - endpoint_evt(0) -) + endpoint_tx(15) endpoint_tx(14) endpoint_tx(13) endpoint_tx(12) + endpoint_tx(11) endpoint_tx(10) endpoint_tx(9) endpoint_tx(8) + endpoint_tx(7) endpoint_tx(6) endpoint_tx(5) + endpoint_tx(4) endpoint_tx(3) endpoint_tx(2) + endpoint_tx(1) endpoint_tx(0)) + + table(xfer_func, usb_ep_rx, + endpoint_rx(15) endpoint_rx(14) endpoint_rx(13) endpoint_rx(12) + endpoint_rx(11) endpoint_rx(10) endpoint_rx(9) + endpoint_rx(8) endpoint_rx(7) endpoint_rx(6) + endpoint_rx(5) endpoint_rx(4) + endpoint_rx(3) endpoint_rx(2) + endpoint_rx(1) + endpoint_rx(0)) + + table(evt_func, usb_ep_event, + endpoint_evt(15) endpoint_evt(14) endpoint_evt( + 13) endpoint_evt(12) endpoint_evt(11) + endpoint_evt(10) endpoint_evt(9) endpoint_evt( + 8) endpoint_evt(7) endpoint_evt(6) + endpoint_evt(5) endpoint_evt(4) + endpoint_evt(3) endpoint_evt(2) + endpoint_evt(1) + endpoint_evt(0)) #if USB_IFACE_COUNT > 0 -table(iface_func, usb_iface_request, - interface(7) - interface(6) - interface(5) - interface(4) - interface(3) - interface(2) - interface(1) - interface(0) -) + table(iface_func, usb_iface_request, + interface(7) interface(6) interface(5) + interface(4) interface(3) interface(2) + interface(1) interface(0)) #endif #if PASS == 2 -- cgit v1.2.1 From 10904a389a7cb7761a5348820c13fd497bc96a1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:52 -0600 Subject: chip/stm32/trng.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I444b1db1de35b27ca9b48984c42bd9b33c522cbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729536 Reviewed-by: Jeremy Bettis --- chip/stm32/trng.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 48d5335c53..6927786c48 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -57,8 +57,8 @@ test_mockable void init_trng(void) ; /* Clock the TRNG using the HSI48 */ - STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) - | (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); + STM32_RCC_CCIPR = (STM32_RCC_CCIPR & ~STM32_RCC_CCIPR_CLK48SEL_MASK) | + (0 << STM32_RCC_CCIPR_CLK48SEL_SHIFT); #elif defined(CHIP_FAMILY_STM32H7) /* Enable the 48Mhz internal RC oscillator */ STM32_RCC_CR |= STM32_RCC_CR_HSI48ON; @@ -68,8 +68,8 @@ test_mockable void init_trng(void) /* Clock the TRNG using the HSI48 */ STM32_RCC_D2CCIP2R = - (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) - | STM32_RCC_D2CCIP2_RNGSEL_HSI48; + (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) | + STM32_RCC_D2CCIP2_RNGSEL_HSI48; #elif defined(CHIP_FAMILY_STM32F4) /* * The RNG clock is the same as the SDIO/USB OTG clock, already set at @@ -115,8 +115,8 @@ static int command_rand(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rand, command_rand, - NULL, "Output random bytes to console."); +DECLARE_CONSOLE_COMMAND(rand, command_rand, NULL, + "Output random bytes to console."); static enum ec_status host_command_rand(struct host_cmd_handler_args *args) { -- cgit v1.2.1 From 029e72a6612f9990990f70ac303d7be18dbdf588 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:19 -0600 Subject: board/felwinter/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I154d0e35b52da33039d7321e4c086f1910de10d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728359 Reviewed-by: Jeremy Bettis --- board/felwinter/led.c | 52 +++++++++++++++++++++++++++++---------------------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/board/felwinter/led.c b/board/felwinter/led.c index 3b7e649470..b7858f2ae7 100644 --- a/board/felwinter/led.c +++ b/board/felwinter/led.c @@ -11,35 +11,43 @@ #include "led_onoff_states.h" #include "system.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 94; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 02be5ff93e965129d3a85c46bd7e54b3a22a8a1d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:37 -0600 Subject: common/usb_pd_host_cmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I90bdcd91f4c0c2d4ebfb1b064f9b72bb5f733c5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729774 Reviewed-by: Jeremy Bettis --- common/usb_pd_host_cmd.c | 143 +++++++++++++++++++++++------------------------ 1 file changed, 70 insertions(+), 73 deletions(-) diff --git a/common/usb_pd_host_cmd.c b/common/usb_pd_host_cmd.c index 09a5697829..226b6639d3 100644 --- a/common/usb_pd_host_cmd.c +++ b/common/usb_pd_host_cmd.c @@ -20,8 +20,8 @@ #include "usb_pd_tcpm.h" #include "usb_pd.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -38,9 +38,7 @@ static enum ec_status hc_pd_ports(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS, - hc_pd_ports, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_PORTS, hc_pd_ports, EC_VER_MASK(0)); #ifdef CONFIG_HOSTCMD_RWHASHPD static enum ec_status @@ -71,8 +69,7 @@ hc_remote_rw_hash_entry(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY, - hc_remote_rw_hash_entry, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_RW_HASH_ENTRY, hc_remote_rw_hash_entry, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_RWHASHPD */ @@ -93,15 +90,14 @@ static enum ec_status hc_remote_pd_chip_info(struct host_cmd_handler_args *args) * same layout for v0 data. (v1 just appends data) */ args->response_size = - args->version ? sizeof(struct ec_response_pd_chip_info_v1) - : sizeof(struct ec_response_pd_chip_info); + args->version ? sizeof(struct ec_response_pd_chip_info_v1) : + sizeof(struct ec_response_pd_chip_info); memcpy(args->response, &info, args->response_size); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO, - hc_remote_pd_chip_info, +DECLARE_HOST_COMMAND(EC_CMD_PD_CHIP_INFO, hc_remote_pd_chip_info, EC_VER_MASK(0) | EC_VER_MASK(1)); #endif /* CONFIG_EC_CMD_PD_CHIP_INFO && !CONFIG_USB_PD_TCPC */ @@ -110,8 +106,8 @@ static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args) { const struct ec_params_usb_pd_set_mode_request *p = args->params; - if ((p->port >= board_get_usb_pd_port_count()) || - (!p->svid) || (!p->opos)) + if ((p->port >= board_get_usb_pd_port_count()) || (!p->svid) || + (!p->opos)) return EC_RES_INVALID_PARAM; switch (p->cmd) { @@ -126,16 +122,16 @@ static enum ec_status hc_remote_pd_set_amode(struct host_cmd_handler_args *args) break; case PD_ENTER_MODE: if (pd_dfp_enter_mode(p->port, TCPCI_MSG_SOP, p->svid, p->opos)) - pd_send_vdm(p->port, p->svid, CMD_ENTER_MODE | - VDO_OPOS(p->opos), NULL, 0); + pd_send_vdm(p->port, p->svid, + CMD_ENTER_MODE | VDO_OPOS(p->opos), NULL, + 0); break; default: return EC_RES_INVALID_PARAM; } return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE, - hc_remote_pd_set_amode, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_SET_AMODE, hc_remote_pd_set_amode, EC_VER_MASK(0)); static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args) @@ -156,8 +152,7 @@ static enum ec_status hc_remote_pd_discovery(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY, - hc_remote_pd_discovery, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DISCOVERY, hc_remote_pd_discovery, EC_VER_MASK(0)); static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args) @@ -180,7 +175,7 @@ static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args) r->svid = pd_get_svid(p->port, p->svid_idx, TCPCI_MSG_SOP); r->opos = 0; memcpy(r->vdo, pd_get_mode_vdo(p->port, p->svid_idx, TCPCI_MSG_SOP), - sizeof(uint32_t) * PDO_MODES); + sizeof(uint32_t) * PDO_MODES); modep = pd_get_amode_data(p->port, TCPCI_MSG_SOP, r->svid); if (modep) @@ -189,8 +184,7 @@ static enum ec_status hc_remote_pd_get_amode(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE, - hc_remote_pd_get_amode, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE, hc_remote_pd_get_amode, EC_VER_MASK(0)); #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ @@ -215,23 +209,22 @@ static enum ec_status hc_remote_pd_dev_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO, - hc_remote_pd_dev_info, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DEV_INFO, hc_remote_pd_dev_info, EC_VER_MASK(0)); static const enum pd_dual_role_states dual_role_map[USB_PD_CTRL_ROLE_COUNT] = { - [USB_PD_CTRL_ROLE_TOGGLE_ON] = PD_DRP_TOGGLE_ON, - [USB_PD_CTRL_ROLE_TOGGLE_OFF] = PD_DRP_TOGGLE_OFF, - [USB_PD_CTRL_ROLE_FORCE_SINK] = PD_DRP_FORCE_SINK, + [USB_PD_CTRL_ROLE_TOGGLE_ON] = PD_DRP_TOGGLE_ON, + [USB_PD_CTRL_ROLE_TOGGLE_OFF] = PD_DRP_TOGGLE_OFF, + [USB_PD_CTRL_ROLE_FORCE_SINK] = PD_DRP_FORCE_SINK, [USB_PD_CTRL_ROLE_FORCE_SOURCE] = PD_DRP_FORCE_SOURCE, - [USB_PD_CTRL_ROLE_FREEZE] = PD_DRP_FREEZE, + [USB_PD_CTRL_ROLE_FREEZE] = PD_DRP_FREEZE, }; static const mux_state_t typec_mux_map[USB_PD_CTRL_MUX_COUNT] = { [USB_PD_CTRL_MUX_NONE] = USB_PD_MUX_NONE, - [USB_PD_CTRL_MUX_USB] = USB_PD_MUX_USB_ENABLED, + [USB_PD_CTRL_MUX_USB] = USB_PD_MUX_USB_ENABLED, [USB_PD_CTRL_MUX_AUTO] = USB_PD_MUX_DP_ENABLED, - [USB_PD_CTRL_MUX_DP] = USB_PD_MUX_DP_ENABLED, + [USB_PD_CTRL_MUX_DP] = USB_PD_MUX_DP_ENABLED, [USB_PD_CTRL_MUX_DOCK] = USB_PD_MUX_DOCK, }; @@ -260,14 +253,18 @@ static uint8_t get_pd_control_flags(int port) * For Passive cables, Active Cable Plug link training is set to 0 */ control_flags |= (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE || - cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ? - USB_PD_CTRL_ACTIVE_CABLE : 0; + cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) ? + USB_PD_CTRL_ACTIVE_CABLE : + 0; control_flags |= cable_resp.tbt_cable == TBT_CABLE_OPTICAL ? - USB_PD_CTRL_OPTICAL_CABLE : 0; + USB_PD_CTRL_OPTICAL_CABLE : + 0; control_flags |= device_resp.tbt_adapter == TBT_ADAPTER_TBT2_LEGACY ? - USB_PD_CTRL_TBT_LEGACY_ADAPTER : 0; + USB_PD_CTRL_TBT_LEGACY_ADAPTER : + 0; control_flags |= cable_resp.lsrx_comm == UNIDIR_LSRX_COMM ? - USB_PD_CTRL_ACTIVE_LINK_UNIDIR : 0; + USB_PD_CTRL_ACTIVE_LINK_UNIDIR : + 0; return control_flags; } @@ -275,19 +272,23 @@ static uint8_t get_pd_control_flags(int port) static uint8_t pd_get_role_flags(int port) { return (pd_get_power_role(port) == PD_ROLE_SOURCE ? - PD_CTRL_RESP_ROLE_POWER : 0) | - (pd_get_data_role(port) == PD_ROLE_DFP ? - PD_CTRL_RESP_ROLE_DATA : 0) | - (pd_get_vconn_state(port) ? - PD_CTRL_RESP_ROLE_VCONN : 0) | - (pd_get_partner_dual_role_power(port) ? - PD_CTRL_RESP_ROLE_DR_POWER : 0) | - (pd_get_partner_data_swap_capable(port) ? - PD_CTRL_RESP_ROLE_DR_DATA : 0) | - (pd_get_partner_usb_comm_capable(port) ? - PD_CTRL_RESP_ROLE_USB_COMM : 0) | - (pd_get_partner_unconstr_power(port) ? - PD_CTRL_RESP_ROLE_UNCONSTRAINED : 0); + PD_CTRL_RESP_ROLE_POWER : + 0) | + (pd_get_data_role(port) == PD_ROLE_DFP ? PD_CTRL_RESP_ROLE_DATA : + 0) | + (pd_get_vconn_state(port) ? PD_CTRL_RESP_ROLE_VCONN : 0) | + (pd_get_partner_dual_role_power(port) ? + PD_CTRL_RESP_ROLE_DR_POWER : + 0) | + (pd_get_partner_data_swap_capable(port) ? + PD_CTRL_RESP_ROLE_DR_DATA : + 0) | + (pd_get_partner_usb_comm_capable(port) ? + PD_CTRL_RESP_ROLE_USB_COMM : + 0) | + (pd_get_partner_unconstr_power(port) ? + PD_CTRL_RESP_ROLE_UNCONSTRAINED : + 0); } static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args) @@ -313,11 +314,11 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args) } if (IS_ENABLED(CONFIG_USBC_SS_MUX) && - p->mux != USB_PD_CTRL_MUX_NO_CHANGE) + p->mux != USB_PD_CTRL_MUX_NO_CHANGE) usb_mux_set(p->port, typec_mux_map[p->mux], typec_mux_map[p->mux] == USB_PD_MUX_NONE ? - USB_SWITCH_DISCONNECT : - USB_SWITCH_CONNECT, + USB_SWITCH_DISCONNECT : + USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(p->port))); if (p->swap == USB_PD_CTRL_SWAP_DATA) { @@ -326,7 +327,7 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args) if (p->swap == USB_PD_CTRL_SWAP_POWER) pd_request_power_swap(p->port); else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) && - p->swap == USB_PD_CTRL_SWAP_VCONN) + p->swap == USB_PD_CTRL_SWAP_VCONN) pd_request_vconn_swap(p->port); } @@ -340,17 +341,19 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args) break; case 1: case 2: - r_v2->enabled = - (pd_comm_is_enabled(p->port) ? - PD_CTRL_RESP_ENABLED_COMMS : 0) | - (pd_is_connected(p->port) ? - PD_CTRL_RESP_ENABLED_CONNECTED : 0) | - (pd_capable(p->port) ? - PD_CTRL_RESP_ENABLED_PD_CAPABLE : 0); + r_v2->enabled = (pd_comm_is_enabled(p->port) ? + PD_CTRL_RESP_ENABLED_COMMS : + 0) | + (pd_is_connected(p->port) ? + PD_CTRL_RESP_ENABLED_CONNECTED : + 0) | + (pd_capable(p->port) ? + PD_CTRL_RESP_ENABLED_PD_CAPABLE : + 0); r_v2->role = pd_get_role_flags(p->port); r_v2->polarity = pd_get_polarity(p->port); - r_v2->cc_state = pd_get_task_cc_state(p->port); + r_v2->cc_state = pd_get_task_cc_state(p->port); task_state_name = pd_get_task_state_name(p->port); if (task_state_name) strzcpy(r_v2->state, task_state_name, @@ -376,8 +379,7 @@ static enum ec_status hc_usb_pd_control(struct host_cmd_handler_args *args) } return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL, - hc_usb_pd_control, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_CONTROL, hc_usb_pd_control, EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2)); #endif /* CONFIG_COMMON_RUNTIME */ @@ -397,14 +399,14 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; #if defined(CONFIG_CHARGE_MANAGER) && defined(CONFIG_BATTERY) && \ - (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ + (defined(CONFIG_BATTERY_PRESENT_CUSTOM) || \ defined(CONFIG_BATTERY_PRESENT_GPIO)) /* * Do not allow PD firmware update if no battery and this port * is sinking power, because we will lose power. */ if (battery_is_present() != BP_YES && - charge_manager_get_active_charge_port() == port) + charge_manager_get_active_charge_port() == port) return EC_RES_UNAVAILABLE; #endif @@ -437,7 +439,7 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) size = p->size / 4; for (i = 0; i < size; i += VDO_MAX_SIZE - 1) { pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_FLASH_WRITE, - data + i, MIN(size - i, VDO_MAX_SIZE - 1)); + data + i, MIN(size - i, VDO_MAX_SIZE - 1)); } return EC_RES_SUCCESS; @@ -447,12 +449,9 @@ static enum ec_status hc_remote_flash(struct host_cmd_handler_args *args) return rv; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, - hc_remote_flash, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_FW_UPDATE, hc_remote_flash, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_FLASHPD && CONFIG_USB_PD_TCPMV2 */ - __overridable enum ec_pd_port_location board_get_pd_port_location(int port) { (void)port; @@ -479,8 +478,7 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args) else r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_NONE; - if (IS_ENABLED(CONFIG_USB_VPD) || - IS_ENABLED(CONFIG_USB_CTVPD)) + if (IS_ENABLED(CONFIG_USB_VPD) || IS_ENABLED(CONFIG_USB_CTVPD)) r->pd_data_role_cap = EC_PD_DATA_ROLE_UFP; else r->pd_data_role_cap = EC_PD_DATA_ROLE_DUAL; @@ -492,8 +490,7 @@ static enum ec_status hc_get_pd_port_caps(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS, - hc_get_pd_port_caps, +DECLARE_HOST_COMMAND(EC_CMD_GET_PD_PORT_CAPS, hc_get_pd_port_caps, EC_VER_MASK(0)); #ifdef CONFIG_HOSTCMD_PD_CONTROL -- cgit v1.2.1 From 8ca104526b63c3f5c880ba34b913f52e602bd688 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:48 -0600 Subject: util/ec_flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7512e66ef1a850ae9108d34be9b8ac6961e29714 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730611 Reviewed-by: Jeremy Bettis --- util/ec_flash.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/util/ec_flash.c b/util/ec_flash.c index ffa4eca4b7..5025b79b9e 100644 --- a/util/ec_flash.c +++ b/util/ec_flash.c @@ -27,8 +27,8 @@ int ec_flash_read(uint8_t *buf, int offset, int size) for (i = 0; i < size; i += ec_max_insize) { p.offset = offset + i; p.size = MIN(size - i, ec_max_insize); - rv = ec_command(EC_CMD_FLASH_READ, 0, - &p, sizeof(p), ec_inbuf, p.size); + rv = ec_command(EC_CMD_FLASH_READ, 0, &p, sizeof(p), ec_inbuf, + p.size); if (rv < 0) { fprintf(stderr, "Read error at offset %d\n", i); return rv; @@ -58,7 +58,8 @@ int ec_flash_verify(const uint8_t *buf, int offset, int size) for (i = 0; i < size; i++) { if (buf[i] != rbuf[i]) { - fprintf(stderr, "Mismatch at offset 0x%x: " + fprintf(stderr, + "Mismatch at offset 0x%x: " "want 0x%02x, got 0x%02x\n", i, buf[i], rbuf[i]); free(rbuf); @@ -76,12 +77,15 @@ int ec_flash_verify(const uint8_t *buf, int offset, int size) */ static int get_flash_info_v2(struct ec_response_flash_info_2 *info_response) { - struct ec_params_flash_info_2 info_params = { - /* - * By setting this to zero we indicate that we don't care - * about getting the bank description in the response. - */ - .num_banks_desc = 0 + struct ec_params_flash_info_2 info_params = { /* + * By setting this to zero + * we indicate that we + * don't care about + * getting the bank + * description in the + * response. + */ + .num_banks_desc = 0 }; return ec_command(EC_CMD_FLASH_INFO, 2, &info_params, -- cgit v1.2.1 From bc39a32101adb7669a820b360decf163cf21fe67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:36 -0600 Subject: board/hammer/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0193b648d2830e3322e436efb850f83a08b43f66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728314 Reviewed-by: Jeremy Bettis --- board/hammer/battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/hammer/battery.c b/board/hammer/battery.c index 4025a08b14..08b9f560df 100644 --- a/board/hammer/battery.c +++ b/board/hammer/battery.c @@ -13,8 +13,8 @@ #include "util.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS +#define SB_SHUTDOWN_DATA 0x0010 static const struct battery_info info = { .voltage_max = 8800, -- cgit v1.2.1 From a27873bf1cdf288db01316583331dedf22f0f887 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:57 -0600 Subject: baseboard/kukui/battery_mm8013.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a2b704e7f03b1bfb3bcaf5825f25748dfb4719b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727919 Reviewed-by: Jeremy Bettis --- baseboard/kukui/battery_mm8013.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/baseboard/kukui/battery_mm8013.c b/baseboard/kukui/battery_mm8013.c index e7f422e561..418bd11d1a 100644 --- a/baseboard/kukui/battery_mm8013.c +++ b/baseboard/kukui/battery_mm8013.c @@ -22,12 +22,9 @@ #define BAT_LEVEL_PD_LIMIT 85 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_SCUD = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_SCUD = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_SCUD] = { @@ -100,7 +97,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } -- cgit v1.2.1 From 920d5e7b83d6941e651dbc0f49525b4b9a6b198c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:36 -0600 Subject: board/damu/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I738af514f508010cf614910d61e681103797cca5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728196 Reviewed-by: Jeremy Bettis --- board/damu/led.c | 67 +++++++++++++++++++++++++++++++------------------------- 1 file changed, 37 insertions(+), 30 deletions(-) diff --git a/board/damu/led.c b/board/damu/led.c index ee376b4b41..9bbea50150 100644 --- a/board/damu/led.c +++ b/board/damu/led.c @@ -18,33 +18,40 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) @@ -79,24 +86,24 @@ __override void led_set_color_power(enum ec_led_colors color) void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { - if(led_id == EC_LED_ID_BATTERY_LED) { + if (led_id == EC_LED_ID_BATTERY_LED) { brightness_range[EC_LED_COLOR_AMBER] = 1; brightness_range[EC_LED_COLOR_WHITE] = 1; - } else if(led_id == EC_LED_ID_POWER_LED) { + } else if (led_id == EC_LED_ID_POWER_LED) { brightness_range[EC_LED_COLOR_WHITE] = 1; } } int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { - if(led_id == EC_LED_ID_BATTERY_LED) { - if(brightness[EC_LED_COLOR_AMBER] != 0) + if (led_id == EC_LED_ID_BATTERY_LED) { + if (brightness[EC_LED_COLOR_AMBER] != 0) led_set_color_battery(EC_LED_COLOR_AMBER); - else if(brightness[EC_LED_COLOR_WHITE] != 0) + else if (brightness[EC_LED_COLOR_WHITE] != 0) led_set_color_battery(EC_LED_COLOR_WHITE); else led_set_color_battery(LED_OFF); - } else if(led_id == EC_LED_ID_POWER_LED) { + } else if (led_id == EC_LED_ID_POWER_LED) { if (brightness[EC_LED_COLOR_WHITE] != 0) led_set_color_power(EC_LED_COLOR_WHITE); else -- cgit v1.2.1 From 2c81d996ebc703fb450b21f15f4e2cf48905a04c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:52 -0600 Subject: zephyr/shim/src/switchcap_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia56c7830a12a8ee145a30878c8d9c90b4221c48f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730900 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/switchcap_gpio.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/zephyr/shim/src/switchcap_gpio.c b/zephyr/shim/src/switchcap_gpio.c index 18f8344943..30fdae788c 100644 --- a/zephyr/shim/src/switchcap_gpio.c +++ b/zephyr/shim/src/switchcap_gpio.c @@ -17,15 +17,12 @@ #define SC_PIN_ENABLE_PHANDLE \ DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_pin, 0) -#define SC_PIN_ENABLE \ - GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE) +#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE) #define SC_PIN_POWER_GOOD_PHANDLE \ DT_PHANDLE_BY_IDX(DT_PATH(switchcap), power_good_pin, 0) -#define SC_PIN_POWER_GOOD_EXISTS \ - DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE) -#define SC_PIN_POWER_GOOD \ - GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_PHANDLE) +#define SC_PIN_POWER_GOOD_EXISTS DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE) +#define SC_PIN_POWER_GOOD GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_PHANDLE) void board_set_switchcap_power(int enable) { -- cgit v1.2.1 From 42d313a034eb9c743bf64ffe8a533865a8f71297 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:44 -0600 Subject: chip/stm32/i2c-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03c8ea6e443cd5cf0a90395017fe9cf5c653ff72 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729516 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32f4.c | 179 +++++++++++++++++++++++------------------------ 1 file changed, 89 insertions(+), 90 deletions(-) diff --git a/chip/stm32/i2c-stm32f4.c b/chip/stm32/i2c-stm32f4.c index bce81b14c9..11b6cc2f76 100644 --- a/chip/stm32/i2c-stm32f4.c +++ b/chip/stm32/i2c-stm32f4.c @@ -20,12 +20,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS #if (I2C_PORT_EC == STM32_I2C1_PORT) @@ -43,36 +43,36 @@ * two sets of functions to handle this for stm32f4. In stm32f446, we * only have one FMP block so we'll hardcode its port number. */ -#define STM32F4_FMPI2C_PORT 3 +#define STM32F4_FMPI2C_PORT 3 static const __unused struct dma_option dma_tx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH)}, - {STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH)}, - {STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH)}, + { STM32_DMAC_I2C1_TX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C1_TX_REQ_CH) }, + { STM32_DMAC_I2C2_TX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C2_TX_REQ_CH) }, + { STM32_DMAC_I2C3_TX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C3_TX_REQ_CH) }, + { STM32_DMAC_FMPI2C4_TX, (void *)&STM32_FMPI2C_TXDR(STM32_FMPI2C4_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_TX_REQ_CH) }, }; static const struct dma_option dma_rx_option[I2C_PORT_COUNT] = { - {STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH)}, - {STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH)}, - {STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH)}, - {STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH)}, + { STM32_DMAC_I2C1_RX, (void *)&STM32_I2C_DR(STM32_I2C1_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C1_RX_REQ_CH) }, + { STM32_DMAC_I2C2_RX, (void *)&STM32_I2C_DR(STM32_I2C2_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C2_RX_REQ_CH) }, + { STM32_DMAC_I2C3_RX, (void *)&STM32_I2C_DR(STM32_I2C3_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_I2C3_RX_REQ_CH) }, + { STM32_DMAC_FMPI2C4_RX, (void *)&STM32_FMPI2C_RXDR(STM32_FMPI2C4_PORT), + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + STM32_DMA_CCR_CHANNEL(STM32_FMPI2C4_RX_REQ_CH) }, }; /* Callback for ISR to wake task on DMA complete. */ @@ -164,7 +164,6 @@ static int wait_sr1(int port, int mask) return wait_sr1_poll(port, mask, SET, 100); } - /** * Send a start condition and peripheral address on the specified port. * @@ -232,8 +231,8 @@ static int wait_fmpi2c_isr_poll(int port, int mask, int val, int poll) int isr = STM32_FMPI2C_ISR(port); /* Check for errors */ - if (isr & (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | - FMPI2C_ISR_NACKF)) { + if (isr & + (FMPI2C_ISR_ARLO | FMPI2C_ISR_BERR | FMPI2C_ISR_NACKF)) { return EC_ERROR_UNKNOWN; } @@ -265,19 +264,18 @@ static int wait_fmpi2c_isr(int port, int mask) * * @return Non-zero if error. */ -static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, - int size, int is_read) +static int send_fmpi2c_start(const int port, const uint16_t addr_8bit, int size, + int is_read) { uint32_t reg; /* Send start bit */ reg = STM32_FMPI2C_CR2(port); reg &= ~(FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK | - FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP); - reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | - addr_8bit | FMPI2C_CR2_SIZE(size) | - (is_read ? FMPI2C_CR2_RD_WRN : 0); + FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | + FMPI2C_CR2_START | FMPI2C_CR2_STOP); + reg |= FMPI2C_CR2_START | FMPI2C_CR2_AUTOEND | addr_8bit | + FMPI2C_CR2_SIZE(size) | (is_read ? FMPI2C_CR2_RD_WRN : 0); STM32_FMPI2C_CR2(port) = reg; return EC_SUCCESS; @@ -300,17 +298,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) /* FMP I2C clock set. */ STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_PE; - prescalar = (freq / (p->kbps * 1000 * - (0x12 + 1 + 0xe + 1 + 1))) - 1; + prescalar = + (freq / (p->kbps * 1000 * (0x12 + 1 + 0xe + 1 + 1))) - + 1; actual = freq / ((prescalar + 1) * (0x12 + 1 + 0xe + 1 + 1)); - reg = FMPI2C_TIMINGR_SCLL(0x12) | - FMPI2C_TIMINGR_SCLH(0xe) | - FMPI2C_TIMINGR_PRESC(prescalar); + reg = FMPI2C_TIMINGR_SCLL(0x12) | FMPI2C_TIMINGR_SCLH(0xe) | + FMPI2C_TIMINGR_PRESC(prescalar); STM32_FMPI2C_TIMINGR(port) = reg; - CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", - port, p->kbps, prescalar, actual, reg); + CPRINTS("port %d target %d, pre %d, act %d, reg 0x%08x", port, + p->kbps, prescalar, actual, reg); STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_PE; udelay(10); @@ -323,9 +321,9 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) if (p->kbps > 100) { STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); } else { - STM32_I2C_CCR(port) = STM32_I2C_CCR_FM - | STM32_I2C_CCR_DUTY - | (freq / (16 + 9 * MSEC * p->kbps)); + STM32_I2C_CCR(port) = + STM32_I2C_CCR_FM | STM32_I2C_CCR_DUTY | + (freq / (16 + 9 * MSEC * p->kbps)); } STM32_I2C_CR2(port) = freq / SECOND; STM32_I2C_TRISE(port) = freq / SECOND + 1; @@ -384,10 +382,10 @@ static void fmpi2c_clear_regs(int port) STM32_FMPI2C_ICR(port) = 0xffffffff; /* Clear start, stop, NACK, etc. bits to get us in a known state */ - STM32_FMPI2C_CR2(port) &= ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | - FMPI2C_CR2_RD_WRN | FMPI2C_CR2_NACK | - FMPI2C_CR2_AUTOEND | - FMPI2C_CR2_SADD_MASK | FMPI2C_CR2_SIZE_MASK); + STM32_FMPI2C_CR2(port) &= + ~(FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RD_WRN | + FMPI2C_CR2_NACK | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_SADD_MASK | + FMPI2C_CR2_SIZE_MASK); } /** @@ -404,8 +402,8 @@ static void fmpi2c_clear_regs(int port) * @return EC_SUCCESS on success. */ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) + const uint8_t *out, int out_bytes, uint8_t *in, + int in_bytes, int flags) { int started = (flags & I2C_XFER_START) ? 0 : 1; int rv = EC_SUCCESS; @@ -424,8 +422,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, /* No out bytes and no in bytes means just check for active */ if (out_bytes || !in_bytes) { - rv = send_fmpi2c_start( - port, addr_8bit, out_bytes, FMPI2C_WRITE); + rv = send_fmpi2c_start(port, addr_8bit, out_bytes, + FMPI2C_WRITE); if (rv) goto xfer_exit; @@ -450,8 +448,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, dma_start_rx(dma, in_bytes, in); i2c_dma_enable_tc_interrupt(dma->channel, port); - rv_start = send_fmpi2c_start( - port, addr_8bit, in_bytes, FMPI2C_READ); + rv_start = send_fmpi2c_start(port, addr_8bit, in_bytes, + FMPI2C_READ); if (rv_start) goto xfer_exit; @@ -460,9 +458,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, goto xfer_exit; STM32_FMPI2C_CR1(port) |= FMPI2C_CR1_RXDMAEN; - rv = task_wait_event_mask( - TASK_EVENT_I2C_COMPLETION(port), - DMA_TRANSFER_TIMEOUT_US); + rv = task_wait_event_mask(TASK_EVENT_I2C_COMPLETION(port), + DMA_TRANSFER_TIMEOUT_US); if (rv & TASK_EVENT_I2C_COMPLETION(port)) rv = EC_SUCCESS; else @@ -478,7 +475,7 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, STM32_FMPI2C_CR1(port) &= ~FMPI2C_CR1_RXDMAEN; } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -492,7 +489,8 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, const struct i2c_port_t *p; CPRINTS("chip_fmpi2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); p = find_port(port); i2c_unwedge(port); @@ -522,7 +520,6 @@ static int chip_fmpi2c_xfer(const int port, const uint16_t addr_8bit, return rv; } - /** * Clear status regs on the specified I2C port. * @@ -539,10 +536,8 @@ static void i2c_clear_regs(int port) STM32_I2C_SR1(port) = 0; /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); + STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP | + STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK); } /***************************************************************************** @@ -550,9 +545,8 @@ static void i2c_clear_regs(int port) */ /* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int started = (flags & I2C_XFER_START) ? 0 : 1; @@ -565,9 +559,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, ASSERT(!started); if (p->port == STM32F4_FMPI2C_PORT) { - return chip_fmpi2c_xfer(port, addr_8bit, - out, out_bytes, - in, in_bytes, flags); + return chip_fmpi2c_xfer(port, addr_8bit, out, out_bytes, in, + in_bytes, flags); } i2c_clear_regs(port); @@ -644,7 +637,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_DMAEN; } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -658,7 +651,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, const struct i2c_port_t *p; CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); p = find_port(port); i2c_unwedge(port); @@ -711,7 +705,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ @@ -766,7 +760,7 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, i2c_freq_change_hook, HOOK_PRIO_DEFAULT); */ static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); -static uint8_t * const host_buffer = host_buffer_padded + 2; +static uint8_t *const host_buffer = host_buffer_padded + 2; static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); static int host_i2c_resp_port; static int tx_pending; @@ -879,14 +873,16 @@ static void i2c_event_handler(int port) /* Disable buffer interrupt */ STM32_I2C_CR2(port) &= ~STM32_I2C_CR2_ITBUFEN; /* Clear error status bits */ - STM32_I2C_SR1(port) &= ~(STM32_I2C_SR1_ARLO | - STM32_I2C_SR1_BERR); + STM32_I2C_SR1(port) &= + ~(STM32_I2C_SR1_ARLO | STM32_I2C_SR1_BERR); } /* Transfer matched our peripheral address */ if (i2c_sr1 & STM32_I2C_SR1_ADDR) { addr_8bit = ((i2c_sr2 & STM32_I2C_SR2_DUALF) ? - STM32_I2C_OAR2(port) : STM32_I2C_OAR1(port)) & 0xfe; + STM32_I2C_OAR2(port) : + STM32_I2C_OAR1(port)) & + 0xfe; if (i2c_sr2 & STM32_I2C_SR2_TRA) { /* Transmitter peripheral */ i2c_sr1 |= STM32_I2C_SR1_TXE; @@ -957,7 +953,7 @@ static void i2c_event_handler(int port) #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS if (rx_pending && (addr_8b >> 1) == - I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS)) + I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS)) i2c_process_board_command(0, addr_8bit, buf_idx); #endif rx_pending = 0; @@ -977,12 +973,14 @@ static void i2c_event_handler(int port) if (!(i2c_cr1 & STM32_I2C_CR1_PE)) STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; } -static void i2c_event_interrupt(void) { i2c_event_handler(I2C_PORT_EC); } +static void i2c_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} DECLARE_IRQ(IRQ_PERIPHERAL_EV, i2c_event_interrupt, 2); DECLARE_IRQ(IRQ_PERIPHERAL_ER, i2c_event_interrupt, 2); #endif - /* Init all available i2c ports */ void i2c_init(void) { @@ -992,19 +990,20 @@ void i2c_init(void) for (i = 0; i < i2c_ports_used; i++, p++) i2c_init_port(p); - #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS /* Enable ACK */ STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_ACK; /* Enable interrupts */ - STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN - | STM32_I2C_CR2_ITERREN; + STM32_I2C_CR2(I2C_PORT_EC) |= STM32_I2C_CR2_ITEVTEN | + STM32_I2C_CR2_ITERREN; /* Setup host command peripheral */ - STM32_I2C_OAR1(I2C_PORT_EC) = STM32_I2C_OAR1_B14 - | (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR1(I2C_PORT_EC) = + STM32_I2C_OAR1_B14 | + (I2C_STRIP_ADDR(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS - STM32_I2C_OAR2(I2C_PORT_EC) = STM32_I2C_OAR2_ENDUAL - | (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_OAR2(I2C_PORT_EC) = + STM32_I2C_OAR2_ENDUAL | + (I2C_STRIP_FLAGS(CONFIG_BOARD_I2C_ADDR_FLAGS) << 1); #endif task_enable_irq(IRQ_PERIPHERAL_EV); task_enable_irq(IRQ_PERIPHERAL_ER); -- cgit v1.2.1 From 033e3f9745b70feb3f0c14aad1b3a8fe224fd998 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:20 -0600 Subject: chip/npcx/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieeb986efb37ca95ff152a5e8aec29993d869c933 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729447 Reviewed-by: Jeremy Bettis --- chip/npcx/watchdog.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c index 55b8df8c1c..87d1afda3c 100644 --- a/chip/npcx/watchdog.c +++ b/chip/npcx/watchdog.c @@ -108,18 +108,18 @@ void IRQ_HANDLER(ITIM_INT(ITIM_WDG_NO))(void) { /* Naked call so we can extract raw LR and SP */ asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveninently saves - * R0=LR so we can pass it to task_resched_if_needed. */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); + "mov r1, sp\n" + /* Must push registers in pairs to keep 64-bit aligned + * stack for ARM EABI. This also conveninently saves + * R0=LR so we can pass it to task_resched_if_needed. */ + "push {r0, lr}\n" + "bl watchdog_check\n" + "pop {r0, lr}\n" + "b task_resched_if_needed\n"); } const struct irq_priority __keep IRQ_PRIORITY(ITIM_INT(ITIM_WDG_NO)) -__attribute__((section(".rodata.irqprio"))) -= {ITIM_INT(ITIM_WDG_NO), 0}; + __attribute__((section(".rodata.irqprio"))) = { ITIM_INT(ITIM_WDG_NO), + 0 }; /* put the watchdog at the highest priority */ void watchdog_reload(void) -- cgit v1.2.1 From b8bbc5d0d5bcbef80e27526778ca71974896440b Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Tue, 28 Jun 2022 14:55:02 +0800 Subject: osiris: Update rgbkbd_map This patch allow RGBKBD_SET_COLOR to specify LEDs by ID for Osiris BUG=b:237350685 BRANCH=none TEST=ectool rgbkbd <1~12> <0xff0000|0x00ff00|0x0000ff> TEST=ectool rgbkbd clear <0xff0000|0x00ff00|0x0000ff> Signed-off-by: Yu-An Chen Change-Id: Ie22066067553ee197644cce02070b3b8272e06e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726605 Reviewed-by: Parth Malkan Tested-by: Dexter ( Chia Hang ) Yeh Reviewed-by: Paris Yeh Commit-Queue: Dexter ( Chia Hang ) Yeh --- board/osiris/keyboard.c | 144 +++++------------------------------------------- 1 file changed, 14 insertions(+), 130 deletions(-) diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c index cf74661173..2a6d25916c 100644 --- a/board/osiris/keyboard.c +++ b/board/osiris/keyboard.c @@ -81,139 +81,23 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -/* TODO(b/233323599): need to check and update */ #define LED(x, y) RGBKBD_COORD((x), (y)) #define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, /* 0: (null) */ - LED(0, 0), DELM, /* 1: ~ ` */ - LED(0, 0), DELM, /* 2: ! 1 */ - LED(1, 0), DELM, /* 3: @ 2 */ - LED(1, 0), DELM, /* 4: # 3 */ - LED(2, 0), DELM, /* 5: $ 4 */ - LED(3, 0), DELM, /* 6: % 5 */ - LED(5, 0), DELM, /* 7: ^ 6 */ - LED(6, 0), DELM, /* 8: & 7 */ - LED(6, 0), DELM, /* 9: * 8 */ - LED(7, 0), DELM, /* 10: ( 9 */ - LED(8, 0), DELM, /* 11: ) 0 */ - LED(9, 0), DELM, /* 12: _ - */ - LED(10, 0), DELM, /* 13: + = */ - DELM, /* 14: (null) */ - LED(11, 0), DELM, /* 15: backspace */ - LED(0, 0), DELM, /* 16: tab */ - LED(0, 0), DELM, /* 17: q */ - LED(1, 0), DELM, /* 18: w */ - LED(2, 0), DELM, /* 19: e */ - LED(3, 0), DELM, /* 20: r */ - LED(4, 0), DELM, /* 21: t */ - LED(5, 0), DELM, /* 22: y */ - LED(6, 0), DELM, /* 23: u */ - LED(7, 0), DELM, /* 24: i */ - LED(8, 0), DELM, /* 25: o */ - LED(9, 0), DELM, /* 26: p */ - LED(10, 0), DELM, /* 27: [ { */ - LED(11, 0), DELM, /* 28: ] } */ - LED(11, 0), DELM, /* 29: \ | */ - LED(0, 0), DELM, /* 30: caps lock */ - LED(1, 0), DELM, /* 31: a */ - LED(1, 0), DELM, /* 32: s */ - LED(2, 0), DELM, /* 33: d */ - LED(3, 0), DELM, /* 34: f */ - LED(4, 0), DELM, /* 35: g */ - LED(5, 0), DELM, /* 36: h */ - LED(6, 0), DELM, /* 37: j */ - LED(7, 0), DELM, /* 38: k */ - LED(8, 0), DELM, /* 39: l */ - LED(9, 0), DELM, /* 40: ; : */ - LED(10, 0), DELM, /* 41: " ' */ - DELM, /* 42: (null) */ - LED(11, 0), DELM, /* 43: enter */ - LED(0, 0), DELM, /* 44: L-shift */ - DELM, /* 45: (null) */ - LED(1, 0), DELM, /* 46: z */ - LED(2, 0), DELM, /* 47: x */ - LED(3, 0), DELM, /* 48: c */ - LED(3, 0), DELM, /* 49: v */ - LED(5, 0), DELM, /* 50: b */ - LED(6, 0), DELM, /* 51: n */ - LED(7, 0), DELM, /* 52: m */ - LED(8, 0), DELM, /* 53: , < */ - LED(9, 0), DELM, /* 54: . > */ - LED(10, 0), DELM, /* 55: / ? */ - DELM, /* 56: (null) */ - LED(11, 0), DELM, /* 57: R-shift */ - LED(0, 0), DELM, /* 58: L-ctrl */ - LED(11, 0), DELM, /* 59: power */ - LED(1, 0), LED(2, 0), DELM, /* 60: L-alt */ - LED(3, 0), LED(4, 0), - LED(5, 0), LED(6, 0), DELM, /* 61: space */ - LED(8, 0), DELM, /* 62: R-alt */ - DELM, /* 63: (null) */ - LED(9, 0), DELM, /* 64: R-ctrl */ - DELM, /* 65: (null) */ - DELM, /* 66: (null) */ - DELM, /* 67: (null) */ - DELM, /* 68: (null) */ - DELM, /* 69: (null) */ - DELM, /* 70: (null) */ - DELM, /* 71: (null) */ - DELM, /* 72: (null) */ - DELM, /* 73: (null) */ - DELM, /* 74: (null) */ - DELM, /* 75: (null) */ - DELM, /* 76: delete */ - DELM, /* 77: (null) */ - DELM, /* 78: (null) */ - LED(10, 0), DELM, /* 79: left */ - DELM, /* 80: home */ - DELM, /* 81: end */ - DELM, /* 82: (null) */ - LED(11, 0), DELM, /* 83: up */ - LED(11, 0), DELM, /* 84: down */ - DELM, /* 85: page up */ - DELM, /* 86: page down */ - DELM, /* 87: (null) */ - DELM, /* 88: (null) */ - LED(11, 0), DELM, /* 89: right */ - DELM, /* 90: (null) */ - DELM, /* 91: numpad 7 */ - DELM, /* 92: numpad 4 */ - DELM, /* 93: numpad 1 */ - DELM, /* 94: (null) */ - DELM, /* 95: numpad / */ - DELM, /* 96: numpad 8 */ - DELM, /* 97: numpad 5 */ - DELM, /* 98: numpad 2 */ - DELM, /* 99: numpad 0 */ - DELM, /* 100: numpad * */ - DELM, /* 101: numpad 9 */ - DELM, /* 102: numpad 6 */ - DELM, /* 103: numpad 3 */ - DELM, /* 104: numpad . */ - DELM, /* 105: numpad - */ - DELM, /* 106: numpad + */ - DELM, /* 107: (null) */ - DELM, /* 108: numpad enter */ - DELM, /* 109: (null) */ - LED(0, 0), DELM, /* 110: esc */ - LED(0, 0), DELM, /* T1: back */ - LED(1, 0), DELM, /* T2: refresh */ - LED(2, 0), DELM, /* T3: full screen */ - LED(3, 0), DELM, /* T4: overview */ - LED(5, 0), DELM, /* T5: snapshot */ - LED(6, 0), DELM, /* T6: brightness down */ - LED(7, 0), DELM, /* T7: brightness up */ - LED(8, 0), DELM, /* T8: mute */ - LED(9, 0), DELM, /* T9: volume down */ - LED(10, 0), DELM, /* T10: volume up */ - DELM, /* T11: (null) */ - DELM, /* T12: (null) */ - DELM, /* T13: (null) */ - DELM, /* T14: (null) */ - DELM, /* T15: (null) */ - DELM, /* 126: (null) */ - DELM, /* 127: (null) */ + DELM, + LED(0, 0), DELM, + LED(1, 0), DELM, + LED(2, 0), DELM, + LED(3, 0), DELM, + LED(4, 0), DELM, + LED(5, 0), DELM, + LED(6, 0), DELM, + LED(7, 0), DELM, + LED(8, 0), DELM, + LED(9, 0), DELM, + LED(10, 0), DELM, + LED(11, 0), DELM, + DELM, }; #undef LED #undef DELM -- cgit v1.2.1 From 9da6708683e2acd0cff0d289768c9261e5f9129c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:37 -0600 Subject: test/usb_tcpmv2_td_pd_src_e2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d21da50bc41ecb74eba6c0de60bc10d40e76ef9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730561 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src_e2.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src_e2.c b/test/usb_tcpmv2_td_pd_src_e2.c index f0e1b64c7e..653c82dea5 100644 --- a/test/usb_tcpmv2_td_pd_src_e2.c +++ b/test/usb_tcpmv2_td_pd_src_e2.c @@ -63,12 +63,8 @@ int test_td_pd_src_e2(void) * Provider, if the Specification Revision field is 10b * (Rev 3.0), the test passes and stops here, */ - TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, - PD_DATA_SOURCE_CAP, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, + data, sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); TEST_GE(msg_len, HEADER_BYTE_CNT, "%d"); @@ -95,7 +91,7 @@ int test_td_pd_src_e2(void) TEST_EQ(revision, REVISION_2, "%d"); TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d"); TEST_EQ(PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, "%d"); - TEST_EQ(header & (BIT(4)|BIT(15)), 0, "%d"); + TEST_EQ(header & (BIT(4) | BIT(15)), 0, "%d"); /* * c) For the first PDO, the Tester verifies: @@ -103,8 +99,8 @@ int test_td_pd_src_e2(void) * 2. Voltage field = 100 (5 V) * 3. Bits 24..22 = 000b (Reserved) */ - pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT); + pdo = UINT32_FROM_BYTE_ARRAY_LE(data, + HEADER_BYTE_OFFSET + HEADER_BYTE_CNT); type = pdo & PDO_TYPE_MASK; TEST_EQ(type, PDO_TYPE_FIXED, "%d"); @@ -132,8 +128,7 @@ int test_td_pd_src_e2(void) int offset; uint32_t voltage; - offset = HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT + + offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + (i * PDO_BYTE_CNT); pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset); -- cgit v1.2.1 From 482a011d7a5eb84b90d4ca0f457a0080f082f1b9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:44 -0600 Subject: include/uart.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie3afc81b2128a850f07ac5e7f1b9be5b93e4dc40 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730425 Reviewed-by: Jeremy Bettis --- include/uart.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/include/uart.h b/include/uart.h index 3789ce127c..786e551fc0 100644 --- a/include/uart.h +++ b/include/uart.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_UART_H #define __CROS_EC_UART_H -#include /* For va_list */ +#include /* For va_list */ #include "common.h" #include "gpio_signal.h" @@ -72,8 +72,8 @@ int uart_put_raw(const char *out, int len); * * @return EC_SUCCESS, or non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 1, 2))) -int uart_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) int +uart_printf(const char *format, ...); /** * Print formatted output to the UART, like vprintf(). @@ -258,7 +258,9 @@ void uart_exit_dsleep(void); */ void uart_deepsleep_interrupt(enum gpio_signal signal); #else -static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { } +static inline void uart_deepsleep_interrupt(enum gpio_signal signal) +{ +} #endif /* !CONFIG_LOW_POWER_IDLE */ #if defined(HAS_TASK_CONSOLE) && defined(CONFIG_FORCE_CONSOLE_RESUME) @@ -269,7 +271,9 @@ static inline void uart_deepsleep_interrupt(enum gpio_signal signal) { } */ void uart_enable_wakeup(int enable); #elif !defined(CHIP_FAMILY_NPCX5) -static inline void uart_enable_wakeup(int enable) {} +static inline void uart_enable_wakeup(int enable) +{ +} #endif #ifdef CONFIG_UART_INPUT_FILTER @@ -335,7 +339,7 @@ void uart_reset_default_pad_panic(void); * time specified in timeout_us. */ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len, - int timeout_us); + int timeout_us); /** * Interrupt handler for default UART RX pin transition when UART is switched @@ -372,9 +376,7 @@ enum ec_status uart_console_read_buffer_init(void); * * @return result status (EC_RES_*) */ -int uart_console_read_buffer(uint8_t type, - char *dest, - uint16_t dest_size, +int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size, uint16_t *write_count); /** @@ -382,4 +384,4 @@ int uart_console_read_buffer(uint8_t type, */ void uart_init_buffer(void); -#endif /* __CROS_EC_UART_H */ +#endif /* __CROS_EC_UART_H */ -- cgit v1.2.1 From d66395db5abb22b306217a655bcbd5d79cd2886b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:14 -0600 Subject: board/beadrix/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7544d6cd48e77a07186ec9c7a75f34e0310190ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728027 Reviewed-by: Jeremy Bettis --- board/beadrix/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/beadrix/cbi_ssfc.c b/board/beadrix/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/beadrix/cbi_ssfc.c +++ b/board/beadrix/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From ae9e1e01402caa508b6c25125465d726efae513b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:52 -0600 Subject: board/lindar/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d9829d0dc33448d42943de6d8c94d515ff045f9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728635 Reviewed-by: Jeremy Bettis --- board/lindar/board.h | 99 ++++++++++++++++++++++++---------------------------- 1 file changed, 46 insertions(+), 53 deletions(-) diff --git a/board/lindar/board.h b/board/lindar/board.h index bc49b8514d..5681295207 100644 --- a/board/lindar/board.h +++ b/board/lindar/board.h @@ -27,12 +27,11 @@ /* Sensors */ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - BIT(LID_ACCEL) +#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -43,31 +42,29 @@ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 - -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #undef CONFIG_USB_MUX_RUNTIME_CONFIG /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ /* BC 1.2 */ @@ -76,8 +73,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -92,42 +89,42 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_MUTE_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_MUTE_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_LIGHTBAR NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_LIGHTBAR NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER #ifndef __ASSEMBLER__ @@ -156,11 +153,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From 090a2d0a0624fd4c31c23e71dce359aef1ef5880 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:40 -0600 Subject: chip/npcx/i2c-npcx9.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27772155ed8fdff7b8013e83f296b26ce068420e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729386 Reviewed-by: Jeremy Bettis --- chip/npcx/i2c-npcx9.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/npcx/i2c-npcx9.c diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c deleted file mode 120000 index b1b16a3198..0000000000 --- a/chip/npcx/i2c-npcx9.c +++ /dev/null @@ -1 +0,0 @@ -i2c-npcx7.c \ No newline at end of file diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c new file mode 100644 index 0000000000..0193f124e8 --- /dev/null +++ b/chip/npcx/i2c-npcx9.c @@ -0,0 +1,70 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* I2C module driver depends on chip series for Chrome EC */ + +#include "common.h" +#include "i2c.h" +#include "i2c_chip.h" +#include "registers.h" +#include "util.h" + +/*****************************************************************************/ +/* IC specific low-level driver depends on chip series */ + +int i2c_port_to_controller(int port) +{ + if (port < 0 || port >= I2C_PORT_COUNT) + return -1; + + if (port <= NPCX_I2C_PORT3_0) + return port; +#ifndef NPCX_PSL_MODE_SUPPORT + else if (port == NPCX_I2C_PORT4_0) + return 4; +#endif + else /* If port >= NPCX_I2C_PORT4_1 */ + return 4 + ((port - NPCX_I2C_PORT4_1 + 1) / 2); +} + +void i2c_select_port(int port) +{ + /* Only I2C 4/5/6 have multiple ports in series npcx7 */ + if (port <= NPCX_I2C_PORT3_0 || port >= NPCX_I2C_PORT7_0) + return; + /* Select I2C ports for the same controller */ + else if (port <= NPCX_I2C_PORT4_1) { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL, + (port == NPCX_I2C_PORT4_1)); + } else if (port <= NPCX_I2C_PORT5_1) { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL, + (port == NPCX_I2C_PORT5_1)); + } else { + UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL, + (port == NPCX_I2C_PORT6_1)); + } +} + +int i2c_is_raw_mode(int port) +{ + int group, bit; + + if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 || + port == NPCX_I2C_PORT6_1) { + group = 6; + bit = 7 - (port - NPCX_I2C_PORT4_1) / 2; + } else { + group = 2; + if (port <= NPCX_I2C_PORT3_0) + bit = 2 * port; + else + bit = I2C_PORT_COUNT - port; + } + + if (IS_BIT_SET(NPCX_DEVALT(group), bit)) + return 0; + else + return 1; +} -- cgit v1.2.1 From 51d511bb5baf7f7b5f656d3a71ee19dd5595f0b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:21 -0600 Subject: board/crota/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2edd49f72766d44c25ba86242a793bbe3b0287d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728216 Reviewed-by: Jeremy Bettis --- board/crota/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/crota/usbc_config.h b/board/crota/usbc_config.h index 55134ce79e..76528b1b6a 100644 --- a/board/crota/usbc_config.h +++ b/board/crota/usbc_config.h @@ -9,14 +9,10 @@ #define __CROS_EC_USBC_CONFIG_H #ifndef CONFIG_ZEPHYR -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 #endif -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From e22e709e291f53920bef2f1ab27515a437254606 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:09 -0600 Subject: test/usb_pd_test_util.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8b959eccf85a46650a7d7e190dc240a13a172f5f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730541 Reviewed-by: Jeremy Bettis --- test/usb_pd_test_util.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/usb_pd_test_util.h b/test/usb_pd_test_util.h index 02fae22b41..bb4446cbe4 100644 --- a/test/usb_pd_test_util.h +++ b/test/usb_pd_test_util.h @@ -31,4 +31,4 @@ int pd_test_tx_msg_verify_short(int port, uint16_t val); int pd_test_tx_msg_verify_word(int port, uint32_t val); int pd_test_tx_msg_verify_crc(int port); -#endif /* __TEST_USB_PD_TEST_UTIL_H */ +#endif /* __TEST_USB_PD_TEST_UTIL_H */ -- cgit v1.2.1 From 2c3585d5dd35bc2d23998fd45d64ab09675faa18 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:09 -0600 Subject: board/sasuke/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0da550cb8a3991a0e2a27c78d5fd447dbe0746f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728896 Reviewed-by: Jeremy Bettis --- board/sasuke/board.h | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/board/sasuke/board.h b/board/sasuke/board.h index 4d70cda5ab..600c016c95 100644 --- a/board/sasuke/board.h +++ b/board/sasuke/board.h @@ -25,11 +25,12 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGE_RAMP_HW -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS @@ -50,9 +51,8 @@ #define GPIO_BAT_LED_GREEN_L GPIO_LED_G_ODL #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL - /* PWM */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Thermistors */ #define CONFIG_TEMP_SENSOR @@ -85,10 +85,10 @@ #undef PD_POWER_SUPPLY_TURN_OFF_DELAY #undef CONFIG_USBC_VCONN_SWAP_DELAY_US /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -101,16 +101,16 @@ #define GPIO_USB1_ILIM_SEL GPIO_EN_USB_A0_5V_SUB /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -142,17 +142,13 @@ enum chg_id { CHARGER_NUM, }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 49e43c640642078b1ccf767d78fe503e0042e0b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:36 -0600 Subject: zephyr/subsys/ap_pwrseq/include/signal_adc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4b1cff024042c552bae009a02d5ae9a6c4fb305c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730905 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/signal_adc.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/signal_adc.h b/zephyr/subsys/ap_pwrseq/include/signal_adc.h index e43e73e1a7..0ed00b64d9 100644 --- a/zephyr/subsys/ap_pwrseq/include/signal_adc.h +++ b/zephyr/subsys/ap_pwrseq/include/signal_adc.h @@ -6,7 +6,7 @@ #ifndef __AP_PWRSEQ_SIGNAL_ADC_H__ #define __AP_PWRSEQ_SIGNAL_ADC_H__ -#define PWR_SIG_TAG_ADC PWR_ADC_ +#define PWR_SIG_TAG_ADC PWR_ADC_ /* * Generate enums for the analogue converters. @@ -21,13 +21,13 @@ enum pwr_sig_adc { #if HAS_ADC_SIGNALS -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_ADC_ENUM) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_ADC_ENUM) #endif - PWR_SIG_ADC_COUNT + PWR_SIG_ADC_COUNT }; -#undef PWR_ADC_ENUM -#undef TAG_ADC +#undef PWR_ADC_ENUM +#undef TAG_ADC /** * @brief Get the value of the ADC power signal. -- cgit v1.2.1 From f9b8b04d95254f848cb7037dd58d9c96433e3057 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:57 -0600 Subject: fuzz/host_command_fuzz.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ec90481e49630d114f20efd0ccf1e73c03dd83c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730193 Reviewed-by: Jeremy Bettis --- fuzz/host_command_fuzz.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fuzz/host_command_fuzz.c b/fuzz/host_command_fuzz.c index 4e30a5e8c1..856310db2b 100644 --- a/fuzz/host_command_fuzz.c +++ b/fuzz/host_command_fuzz.c @@ -75,7 +75,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size) chunks[2].start = chunks[1].start + chunks[1].size + data_len_size; chunks[2].size = sizeof(req_buf) - chunks[2].start; #else - struct chunk chunks[1] = { {0, sizeof(req_buf)} }; + struct chunk chunks[1] = { { 0, sizeof(req_buf) } }; #endif /* @@ -89,7 +89,7 @@ static int hostcmd_fill(const uint8_t *data, size_t size) * over checksum and data_len. */ for (i = 0; i < ARRAY_SIZE(chunks) && ipos < size; i++) { - int cp_size = MIN(chunks[i].size, size-ipos); + int cp_size = MIN(chunks[i].size, size - ipos); memcpy(req_buf + chunks[i].start, data + ipos, cp_size); @@ -112,8 +112,8 @@ static int hostcmd_fill(const uint8_t *data, size_t size) * issues. */ if (first) { - ccprintf("Request: cmd=%04x data=%ph\n", - req->command, HEX_BUF(req_buf, req_size)); + ccprintf("Request: cmd=%04x data=%ph\n", req->command, + HEX_BUF(req_buf, req_size)); first = 0; } -- cgit v1.2.1 From 3fe60306a68672d945fe28bb59454b63bc919988 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:05 -0600 Subject: chip/mt_scp/mt818x/serial_reg.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20598c21f6464544d953ad8426eae67df0c821e3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729350 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/serial_reg.h | 108 ++++++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/chip/mt_scp/mt818x/serial_reg.h b/chip/mt_scp/mt818x/serial_reg.h index 5344566272..0c5e87546e 100644 --- a/chip/mt_scp/mt818x/serial_reg.h +++ b/chip/mt_scp/mt818x/serial_reg.h @@ -19,72 +19,72 @@ * (Read) Rcvr buffer register * (Write) Xmit holding register */ -#define UART_DATA(n) UART_REG(n, 0) +#define UART_DATA(n) UART_REG(n, 0) /* (Write) Interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* Recv data int */ -#define UART_IER_THRI BIT(1) /* Xmit holding register int */ -#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ -#define UART_IER_MSI BIT(3) /* Modem status int */ +#define UART_IER(n) UART_REG(n, 1) +#define UART_IER_RDI BIT(0) /* Recv data int */ +#define UART_IER_THRI BIT(1) /* Xmit holding register int */ +#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ +#define UART_IER_MSI BIT(3) /* Modem status int */ /* (Read) Interrupt ID register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT BIT(0) /* No int pending */ -#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ -#define UART_IIR_MSI 0x00 -#define UART_IIR_THRI 0x02 -#define UART_IIR_RDI 0x04 -#define UART_IIR_RLSI 0x06 -#define UART_IIR_BUSY 0x07 /* DW APB busy */ +#define UART_IIR(n) UART_REG(n, 2) +#define UART_IIR_NO_INT BIT(0) /* No int pending */ +#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ +#define UART_IIR_MSI 0x00 +#define UART_IIR_THRI 0x02 +#define UART_IIR_RDI 0x04 +#define UART_IIR_RLSI 0x06 +#define UART_IIR_BUSY 0x07 /* DW APB busy */ /* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) +#define UART_FCR(n) UART_REG(n, 2) +#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* FIFO trigger levels */ -#define UART_FCR_T_TRIG_00 0x00 -#define UART_FCR_T_TRIG_01 0x10 -#define UART_FCR_T_TRIG_10 0x20 -#define UART_FCR_T_TRIG_11 0x30 -#define UART_FCR_R_TRIG_00 0x00 -#define UART_FCR_R_TRIG_01 0x40 -#define UART_FCR_R_TRIG_10 0x80 -#define UART_FCR_R_TRIG_11 0x80 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0x80 /* (Write) Line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* Word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* Parity enable */ -#define UART_LCR_EPAR BIT(4) /* Even parity */ -#define UART_LCR_SPAR BIT(5) /* Stick parity */ -#define UART_LCR_SBC BIT(6) /* Set break control */ -#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ +#define UART_LCR(n) UART_REG(n, 3) +#define UART_LCR_WLEN5 0 /* Word length 5 bits */ +#define UART_LCR_WLEN6 1 +#define UART_LCR_WLEN7 2 +#define UART_LCR_WLEN8 3 +#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* Parity enable */ +#define UART_LCR_EPAR BIT(4) /* Even parity */ +#define UART_LCR_SPAR BIT(5) /* Stick parity */ +#define UART_LCR_SBC BIT(6) /* Set break control */ +#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ /* (Write) Modem control register */ -#define UART_MCR(n) UART_REG(n, 4) +#define UART_MCR(n) UART_REG(n, 4) /* (Read) Line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* Data ready */ -#define UART_LSR_OE BIT(1) /* Overrun error */ -#define UART_LSR_PE BIT(2) /* Parity error */ -#define UART_LSR_FE BIT(3) /* Frame error */ -#define UART_LSR_BI BIT(4) /* Break interrupt */ -#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT BIT(6) /* Xmit empty */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ +#define UART_LSR(n) UART_REG(n, 5) +#define UART_LSR_DR BIT(0) /* Data ready */ +#define UART_LSR_OE BIT(1) /* Overrun error */ +#define UART_LSR_PE BIT(2) /* Parity error */ +#define UART_LSR_FE BIT(3) /* Frame error */ +#define UART_LSR_BI BIT(4) /* Break interrupt */ +#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ +#define UART_LSR_TEMT BIT(6) /* Xmit empty */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* DLAB == 1 */ /* (Write) Divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) /* Low */ -#define UART_DLH(n) UART_REG(n, 1) /* High */ +#define UART_DLL(n) UART_REG(n, 0) /* Low */ +#define UART_DLH(n) UART_REG(n, 1) /* High */ /* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) -#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) -#define UART_SAMPLE_POINT(n) UART_REG(n, 11) -#define UART_RATE_FIX(n) UART_REG(n, 13) +#define UART_HIGHSPEED(n) UART_REG(n, 9) +#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) +#define UART_SAMPLE_POINT(n) UART_REG(n, 11) +#define UART_RATE_FIX(n) UART_REG(n, 13) #endif /* __CROS_EC_SERIAL_REG_H */ -- cgit v1.2.1 From cdcbbb38d8247ac265022d5002449fcdb9f8d7fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:39 -0600 Subject: driver/charger/bq24773.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7400b431c6b10dd68872277ca76d5f92f899afdb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729959 Reviewed-by: Jeremy Bettis --- driver/charger/bq24773.c | 53 ++++++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 29 deletions(-) diff --git a/driver/charger/bq24773.c b/driver/charger/bq24773.c index d242f105c6..6b76b3dba9 100644 --- a/driver/charger/bq24773.c +++ b/driver/charger/bq24773.c @@ -22,39 +22,39 @@ /* Sense resistor configurations and macros */ #define DEFAULT_SENSE_RESISTOR 10 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR -#define R_AC (CONFIG_CHARGER_SENSE_RESISTOR_AC) -#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS)) +#define R_AC (CONFIG_CHARGER_SENSE_RESISTOR_AC) +#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS)) #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR) -#define REG8_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS) * R8) +#define REG8_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS)*R8) #define CURRENT_TO_REG8(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR / R8) /* ChargeCurrent Register - 0x14 (mA) */ -#define CHARGE_I_OFF 0 -#define CHARGE_I_MIN 128 -#define CHARGE_I_MAX 8128 -#define CHARGE_I_STEP 64 +#define CHARGE_I_OFF 0 +#define CHARGE_I_MIN 128 +#define CHARGE_I_MAX 8128 +#define CHARGE_I_STEP 64 /* MaxChargeVoltage Register - 0x15 (mV) */ -#define CHARGE_V_MIN 1024 -#define CHARGE_V_MAX 19200 -#define CHARGE_V_STEP 16 +#define CHARGE_V_MIN 1024 +#define CHARGE_V_MAX 19200 +#define CHARGE_V_STEP 16 /* InputCurrent Register - 0x3f (mA) */ -#define INPUT_I_MIN 128 -#define INPUT_I_MAX 8128 -#define INPUT_I_STEP 64 +#define INPUT_I_MIN 128 +#define INPUT_I_MAX 8128 +#define INPUT_I_STEP 64 /* Charger parameters */ static const struct charger_info bq2477x_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS), - .current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS), + .current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS), + .current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS), .current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS), - .input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC), - .input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC), + .input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC), + .input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC), .input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC), }; @@ -62,33 +62,28 @@ static const struct charger_info bq2477x_charger_info = { static inline enum ec_error_list raw_read8(int chgnum, int offset, int *value) { return i2c_read8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list raw_write8(int chgnum, int offset, int value) { return i2c_write8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } #endif static inline enum ec_error_list raw_read16(int chgnum, int offset, int *value) { return i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list raw_write16(int chgnum, int offset, int value) { return i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } - /* chip specific interfaces */ static enum ec_error_list bq2477x_set_input_current_limit(int chgnum, -- cgit v1.2.1 From b5d6e60b5190630d08b653b8b5b79d85460e1f63 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:37 -0600 Subject: board/mithrax/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9bc28ac7e7312a667442e8c97a0600ff5bca77b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728461 Reviewed-by: Jeremy Bettis --- board/mithrax/keyboard.c | 295 +++++++++++++++++++++++------------------------ 1 file changed, 147 insertions(+), 148 deletions(-) diff --git a/board/mithrax/keyboard.c b/board/mithrax/keyboard.c index 6534c7bc63..6d6fd3a4a6 100644 --- a/board/mithrax/keyboard.c +++ b/board/mithrax/keyboard.c @@ -61,145 +61,144 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, /* 0: (null) */ - LED(0, 0), DELM, /* 1: ~ ` */ - LED(0, 0), DELM, /* 2: ! 1 */ - LED(0, 0), DELM, /* 3: @ 2 */ - LED(0, 0), DELM, /* 4: # 3 */ - LED(1, 0), DELM, /* 5: $ 4 */ - LED(1, 0), DELM, /* 6: % 5 */ - LED(1, 0), DELM, /* 7: ^ 6 */ - LED(2, 0), DELM, /* 8: & 7 */ - LED(2, 0), DELM, /* 9: * 8 */ - LED(2, 0), DELM, /* 10: ( 9 */ - LED(2, 0), DELM, /* 11: ) 0 */ - LED(2, 0), DELM, /* 12: _ - */ - LED(3, 0), DELM, /* 13: + = */ - DELM, /* 14: (null) */ - LED(3, 0), DELM, /* 15: backspace */ - LED(0, 0), DELM, /* 16: tab */ - LED(0, 0), DELM, /* 17: q */ - LED(0, 0), DELM, /* 18: w */ - LED(0, 0), DELM, /* 19: e */ - LED(1, 0), DELM, /* 20: r */ - LED(1, 0), DELM, /* 21: t */ - LED(1, 0), DELM, /* 22: y */ - LED(2, 0), DELM, /* 23: u */ - LED(2, 0), DELM, /* 24: i */ - LED(2, 0), DELM, /* 25: o */ - LED(2, 0), DELM, /* 26: p */ - LED(2, 0), DELM, /* 27: [ { */ - LED(3, 0), DELM, /* 28: ] } */ - LED(3, 0), DELM, /* 29: \ | */ - LED(0, 0), DELM, /* 30: caps lock */ - LED(0, 0), DELM, /* 31: a */ - LED(0, 0), DELM, /* 32: s */ - LED(0, 0), DELM, /* 33: d */ - LED(1, 0), DELM, /* 34: f */ - LED(1, 0), DELM, /* 35: g */ - LED(1, 0), DELM, /* 36: h */ - LED(2, 0), DELM, /* 37: j */ - LED(2, 0), DELM, /* 38: k */ - LED(2, 0), DELM, /* 39: l */ - LED(3, 0), DELM, /* 40: ; : */ - LED(3, 0), DELM, /* 41: " ' */ - DELM, /* 42: (null) */ - LED(3, 0), DELM, /* 43: enter */ - LED(0, 0), DELM, /* 44: L-shift */ - DELM, /* 45: (null) */ - LED(0, 0), DELM, /* 46: z */ - LED(0, 0), DELM, /* 47: x */ - LED(0, 0), DELM, /* 48: c */ - LED(1, 0), DELM, /* 49: v */ - LED(1, 0), DELM, /* 50: b */ - LED(1, 0), DELM, /* 51: n */ - LED(2, 0), DELM, /* 52: m */ - LED(2, 0), DELM, /* 53: , < */ - LED(2, 0), DELM, /* 54: . > */ - LED(3, 0), DELM, /* 55: / ? */ - DELM, /* 56: (null) */ - LED(3, 0), DELM, /* 57: R-shift */ - LED(0, 0), DELM, /* 58: L-ctrl */ - LED(3, 0), DELM, /* 59: power */ - LED(0, 0), DELM, /* 60: L-alt */ - LED(0, 0), LED(1, 0), - LED(2, 0), DELM, /* 61: space */ - LED(2, 0), DELM, /* 62: R-alt */ - DELM, /* 63: (null) */ - LED(2, 0), DELM, /* 64: R-ctrl */ - DELM, /* 65: (null) */ - DELM, /* 66: (null) */ - DELM, /* 67: (null) */ - DELM, /* 68: (null) */ - DELM, /* 69: (null) */ - DELM, /* 70: (null) */ - DELM, /* 71: (null) */ - DELM, /* 72: (null) */ - DELM, /* 73: (null) */ - DELM, /* 74: (null) */ - DELM, /* 75: (null) */ - DELM, /* 76: delete */ - DELM, /* 77: (null) */ - DELM, /* 78: (null) */ - LED(3, 0), DELM, /* 79: left */ - DELM, /* 80: home */ - DELM, /* 81: end */ - DELM, /* 82: (null) */ - LED(3, 0), DELM, /* 83: up */ - LED(3, 0), DELM, /* 84: down */ - DELM, /* 85: page up */ - DELM, /* 86: page down */ - DELM, /* 87: (null) */ - DELM, /* 88: (null) */ - LED(3, 0), DELM, /* 89: right */ - DELM, /* 90: (null) */ - DELM, /* 91: numpad 7 */ - DELM, /* 92: numpad 4 */ - DELM, /* 93: numpad 1 */ - DELM, /* 94: (null) */ - DELM, /* 95: numpad / */ - DELM, /* 96: numpad 8 */ - DELM, /* 97: numpad 5 */ - DELM, /* 98: numpad 2 */ - DELM, /* 99: numpad 0 */ - DELM, /* 100: numpad * */ - DELM, /* 101: numpad 9 */ - DELM, /* 102: numpad 6 */ - DELM, /* 103: numpad 3 */ - DELM, /* 104: numpad . */ - DELM, /* 105: numpad - */ - DELM, /* 106: numpad + */ - DELM, /* 107: (null) */ - DELM, /* 108: numpad enter */ - DELM, /* 109: (null) */ - LED(0, 0), DELM, /* 110: esc */ - LED(0, 0), DELM, /* T1: back */ - LED(0, 0), DELM, /* T2: refresh */ - LED(1, 0), DELM, /* T3: full screen */ - LED(1, 0), DELM, /* T4: overview */ - LED(1, 0), DELM, /* T5: snapshot */ - LED(2, 0), DELM, /* T6: brightness down */ - LED(2, 0), DELM, /* T7: brightness up */ - LED(2, 0), DELM, /* T8: mute */ - LED(2, 0), DELM, /* T9: volume down */ - LED(3, 0), DELM, /* T10: volume up */ - DELM, /* T11: (null) */ - DELM, /* T12: (null) */ - DELM, /* T13: (null) */ - DELM, /* T14: (null) */ - DELM, /* T15: (null) */ - DELM, /* 126: (null) */ - DELM, /* 127: (null) */ + DELM, /* 0: (null) */ + LED(0, 0), DELM, /* 1: ~ ` */ + LED(0, 0), DELM, /* 2: ! 1 */ + LED(0, 0), DELM, /* 3: @ 2 */ + LED(0, 0), DELM, /* 4: # 3 */ + LED(1, 0), DELM, /* 5: $ 4 */ + LED(1, 0), DELM, /* 6: % 5 */ + LED(1, 0), DELM, /* 7: ^ 6 */ + LED(2, 0), DELM, /* 8: & 7 */ + LED(2, 0), DELM, /* 9: * 8 */ + LED(2, 0), DELM, /* 10: ( 9 */ + LED(2, 0), DELM, /* 11: ) 0 */ + LED(2, 0), DELM, /* 12: _ - */ + LED(3, 0), DELM, /* 13: + = */ + DELM, /* 14: (null) */ + LED(3, 0), DELM, /* 15: backspace */ + LED(0, 0), DELM, /* 16: tab */ + LED(0, 0), DELM, /* 17: q */ + LED(0, 0), DELM, /* 18: w */ + LED(0, 0), DELM, /* 19: e */ + LED(1, 0), DELM, /* 20: r */ + LED(1, 0), DELM, /* 21: t */ + LED(1, 0), DELM, /* 22: y */ + LED(2, 0), DELM, /* 23: u */ + LED(2, 0), DELM, /* 24: i */ + LED(2, 0), DELM, /* 25: o */ + LED(2, 0), DELM, /* 26: p */ + LED(2, 0), DELM, /* 27: [ { */ + LED(3, 0), DELM, /* 28: ] } */ + LED(3, 0), DELM, /* 29: \ | */ + LED(0, 0), DELM, /* 30: caps lock */ + LED(0, 0), DELM, /* 31: a */ + LED(0, 0), DELM, /* 32: s */ + LED(0, 0), DELM, /* 33: d */ + LED(1, 0), DELM, /* 34: f */ + LED(1, 0), DELM, /* 35: g */ + LED(1, 0), DELM, /* 36: h */ + LED(2, 0), DELM, /* 37: j */ + LED(2, 0), DELM, /* 38: k */ + LED(2, 0), DELM, /* 39: l */ + LED(3, 0), DELM, /* 40: ; : */ + LED(3, 0), DELM, /* 41: " ' */ + DELM, /* 42: (null) */ + LED(3, 0), DELM, /* 43: enter */ + LED(0, 0), DELM, /* 44: L-shift */ + DELM, /* 45: (null) */ + LED(0, 0), DELM, /* 46: z */ + LED(0, 0), DELM, /* 47: x */ + LED(0, 0), DELM, /* 48: c */ + LED(1, 0), DELM, /* 49: v */ + LED(1, 0), DELM, /* 50: b */ + LED(1, 0), DELM, /* 51: n */ + LED(2, 0), DELM, /* 52: m */ + LED(2, 0), DELM, /* 53: , < */ + LED(2, 0), DELM, /* 54: . > */ + LED(3, 0), DELM, /* 55: / ? */ + DELM, /* 56: (null) */ + LED(3, 0), DELM, /* 57: R-shift */ + LED(0, 0), DELM, /* 58: L-ctrl */ + LED(3, 0), DELM, /* 59: power */ + LED(0, 0), DELM, /* 60: L-alt */ + LED(0, 0), LED(1, 0), LED(2, 0), DELM, /* 61: space */ + LED(2, 0), DELM, /* 62: R-alt */ + DELM, /* 63: (null) */ + LED(2, 0), DELM, /* 64: R-ctrl */ + DELM, /* 65: (null) */ + DELM, /* 66: (null) */ + DELM, /* 67: (null) */ + DELM, /* 68: (null) */ + DELM, /* 69: (null) */ + DELM, /* 70: (null) */ + DELM, /* 71: (null) */ + DELM, /* 72: (null) */ + DELM, /* 73: (null) */ + DELM, /* 74: (null) */ + DELM, /* 75: (null) */ + DELM, /* 76: delete */ + DELM, /* 77: (null) */ + DELM, /* 78: (null) */ + LED(3, 0), DELM, /* 79: left */ + DELM, /* 80: home */ + DELM, /* 81: end */ + DELM, /* 82: (null) */ + LED(3, 0), DELM, /* 83: up */ + LED(3, 0), DELM, /* 84: down */ + DELM, /* 85: page up */ + DELM, /* 86: page down */ + DELM, /* 87: (null) */ + DELM, /* 88: (null) */ + LED(3, 0), DELM, /* 89: right */ + DELM, /* 90: (null) */ + DELM, /* 91: numpad 7 */ + DELM, /* 92: numpad 4 */ + DELM, /* 93: numpad 1 */ + DELM, /* 94: (null) */ + DELM, /* 95: numpad / */ + DELM, /* 96: numpad 8 */ + DELM, /* 97: numpad 5 */ + DELM, /* 98: numpad 2 */ + DELM, /* 99: numpad 0 */ + DELM, /* 100: numpad * */ + DELM, /* 101: numpad 9 */ + DELM, /* 102: numpad 6 */ + DELM, /* 103: numpad 3 */ + DELM, /* 104: numpad . */ + DELM, /* 105: numpad - */ + DELM, /* 106: numpad + */ + DELM, /* 107: (null) */ + DELM, /* 108: numpad enter */ + DELM, /* 109: (null) */ + LED(0, 0), DELM, /* 110: esc */ + LED(0, 0), DELM, /* T1: back */ + LED(0, 0), DELM, /* T2: refresh */ + LED(1, 0), DELM, /* T3: full screen */ + LED(1, 0), DELM, /* T4: overview */ + LED(1, 0), DELM, /* T5: snapshot */ + LED(2, 0), DELM, /* T6: brightness down */ + LED(2, 0), DELM, /* T7: brightness up */ + LED(2, 0), DELM, /* T8: mute */ + LED(2, 0), DELM, /* T9: volume down */ + LED(3, 0), DELM, /* T10: volume up */ + DELM, /* T11: (null) */ + DELM, /* T12: (null) */ + DELM, /* T13: (null) */ + DELM, /* T14: (null) */ + DELM, /* T15: (null) */ + DELM, /* 126: (null) */ + DELM, /* 127: (null) */ }; #undef LED #undef DELM const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map); -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &mithrax_kb; } @@ -213,20 +212,20 @@ __override const struct key { uint8_t row; uint8_t col; } vivaldi_keys[] = { - {.row = 4, .col = 2}, /* T1 */ - {.row = 3, .col = 2}, /* T2 */ - {.row = 2, .col = 2}, /* T3 */ - {.row = 1, .col = 2}, /* T4 */ - {.row = 4, .col = 4}, /* T5 */ - {.row = 3, .col = 4}, /* T6 */ - {.row = 2, .col = 4}, /* T7 */ - {.row = 2, .col = 9}, /* T8 */ - {.row = 1, .col = 9}, /* T9 */ - {.row = 1, .col = 4}, /* T10 */ - {.row = 0, .col = 4}, /* T11 */ - {.row = 1, .col = 5}, /* T12 */ - {.row = 3, .col = 5}, /* T13 */ - {.row = 2, .col = 1}, /* T14 */ - {.row = 0, .col = 1}, /* T15 */ + { .row = 4, .col = 2 }, /* T1 */ + { .row = 3, .col = 2 }, /* T2 */ + { .row = 2, .col = 2 }, /* T3 */ + { .row = 1, .col = 2 }, /* T4 */ + { .row = 4, .col = 4 }, /* T5 */ + { .row = 3, .col = 4 }, /* T6 */ + { .row = 2, .col = 4 }, /* T7 */ + { .row = 2, .col = 9 }, /* T8 */ + { .row = 1, .col = 9 }, /* T9 */ + { .row = 1, .col = 4 }, /* T10 */ + { .row = 0, .col = 4 }, /* T11 */ + { .row = 1, .col = 5 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 2, .col = 1 }, /* T14 */ + { .row = 0, .col = 1 }, /* T15 */ }; BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); -- cgit v1.2.1 From 2d97bc7b9f3e0bba01db0616a1afe2976f9cd458 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:57 -0600 Subject: zephyr/test/drivers/src/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I924b3441751a64d30b12fb58d4ecc07b7188af1d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730989 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/gpio.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/zephyr/test/drivers/src/gpio.c b/zephyr/test/drivers/src/gpio.c index e49222f08f..8686eee9c1 100644 --- a/zephyr/test/drivers/src/gpio.c +++ b/zephyr/test/drivers/src/gpio.c @@ -116,8 +116,8 @@ ZTEST(gpio, test_convert_to_zephyr_flags) */ ZTEST(gpio, test_signal_is_gpio) { - zassert_true(signal_is_gpio( - GPIO_SIGNAL(DT_NODELABEL(gpio_test))), "Expected true"); + zassert_true(signal_is_gpio(GPIO_SIGNAL(DT_NODELABEL(gpio_test))), + "Expected true"); } /** @@ -301,7 +301,6 @@ ZTEST(gpio, test_gpio_get_default_flags) zassert_equal(flags, GPIO_OUTPUT, "Flags set 0x%x", flags); } - /** * @brief TestPurpose: Verify GPIO no-auto-init. * @@ -319,16 +318,13 @@ ZTEST(gpio, test_gpio_no_auto_init) gpio_flags_t flags; flags = gpio_helper_get_flags(signal); - zassert_equal(0, flags, - "Expected 0x%08x, returned 0x%08X", - 0, flags); + zassert_equal(0, flags, "Expected 0x%08x, returned 0x%08X", 0, flags); /* Configure pin. */ gpio_pin_configure_dt(gp, GPIO_INPUT | GPIO_OUTPUT); flags = gpio_helper_get_flags(signal); - zassert_equal(flags, - (GPIO_ACTIVE_LOW | GPIO_OUTPUT | GPIO_INPUT), - "Flags set 0x%x", flags); + zassert_equal(flags, (GPIO_ACTIVE_LOW | GPIO_OUTPUT | GPIO_INPUT), + "Flags set 0x%x", flags); } /** -- cgit v1.2.1 From ae8a7cb7e5020612b99612143cbc4f83fa067545 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:45 -0600 Subject: driver/tcpm/it83xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24ddfe40cb5681456b6cccd5c4c5bc82ecd2b590 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730092 Reviewed-by: Jeremy Bettis --- driver/tcpm/it83xx.c | 166 ++++++++++++++++++++++++++------------------------- 1 file changed, 85 insertions(+), 81 deletions(-) diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c index c809cce153..cc82f16e63 100644 --- a/driver/tcpm/it83xx.c +++ b/driver/tcpm/it83xx.c @@ -22,8 +22,8 @@ #ifdef CONFIG_USB_PD_TCPMV1 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \ - defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \ - defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ + defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \ + defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) #error "Unsupported config options of IT83xx PD driver" #endif @@ -38,11 +38,11 @@ int rx_en[IT83XX_USBPD_PHY_PORT_COUNT]; STATIC_IF(CONFIG_USB_PD_DECODE_SOP) - bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT]; +bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT]; const struct usbpd_ctrl_t usbpd_ctrl_regs[] = { - {&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0}, - {&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1}, + { &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 }, + { &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 }, }; BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == IT83XX_USBPD_PHY_PORT_COUNT); @@ -58,7 +58,7 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port) { /* This only apply to active PD port */ if (*usbpd_ctrl_regs[port].cc1 == IT83XX_USBPD_CC_PIN_CONFIG && - *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) { + *usbpd_ctrl_regs[port].cc2 == IT83XX_USBPD_CC_PIN_CONFIG) { /* Disable PD PHY */ IT83XX_USBPD_GCR(port) &= ~(BIT(0) | BIT(4)); /* @@ -81,9 +81,8 @@ void it83xx_Rd_5_1K_only_for_hibernate(int port) } } -static enum tcpc_cc_voltage_status it83xx_get_cc( - enum usbpd_port port, - enum usbpd_cc_pin cc_pin) +static enum tcpc_cc_voltage_status it83xx_get_cc(enum usbpd_port port, + enum usbpd_cc_pin cc_pin) { enum usbpd_ufp_volt_status ufp_volt; enum usbpd_dfp_volt_status dfp_volt; @@ -91,8 +90,8 @@ static enum tcpc_cc_voltage_status it83xx_get_cc( int pull; pull = (cc_pin == USBPD_CC_PIN_1) ? - USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) : - USBPD_GET_CC2_PULL_REGISTER_SELECTION(port); + USBPD_GET_CC1_PULL_REGISTER_SELECTION(port) : + USBPD_GET_CC2_PULL_REGISTER_SELECTION(port); /* select Rp */ if (pull) @@ -125,7 +124,7 @@ static enum tcpc_cc_voltage_status it83xx_get_cc( cc_state = TYPEC_CC_VOLT_OPEN; break; } - /* source */ + /* source */ } else { if (cc_pin == USBPD_CC_PIN_1) dfp_volt = IT83XX_USBPD_DFPVDR(port) & 0xf; @@ -177,11 +176,10 @@ static int it83xx_tcpm_get_message_raw(int port, uint32_t *buf, int *head) return EC_SUCCESS; } -static enum tcpc_transmit_complete it83xx_tx_data( - enum usbpd_port port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *buf) +static enum tcpc_transmit_complete it83xx_tx_data(enum usbpd_port port, + enum tcpci_msg_type type, + uint16_t header, + const uint32_t *buf) { int r; uint32_t evt; @@ -198,8 +196,8 @@ static enum tcpc_transmit_complete it83xx_tx_data( * on dx version: * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''. */ - IT83XX_USBPD_MTSR1(port) = - (IT83XX_USBPD_MTSR1(port) & ~0x70) | ((type & 0x7) << 4); + IT83XX_USBPD_MTSR1(port) = (IT83XX_USBPD_MTSR1(port) & ~0x70) | + ((type & 0x7) << 4); /* bit7: transmit message is send to cable or not */ if (type == TCPCI_MSG_SOP) IT83XX_USBPD_MTSR0(port) &= ~USBPD_REG_MASK_CABLE_ENABLE; @@ -223,7 +221,7 @@ static enum tcpc_transmit_complete it83xx_tx_data( /* Start TX */ USBPD_KICK_TX_START(port); evt = task_wait_event_mask(TASK_EVENT_PHY_TX_DONE, - PD_T_TCPC_TX_TIMEOUT); + PD_T_TCPC_TX_TIMEOUT); /* check TX status */ if (USBPD_IS_TX_ERR(port) || (evt & TASK_EVENT_TIMER)) { /* @@ -247,8 +245,8 @@ static enum tcpc_transmit_complete it83xx_tx_data( return TCPC_TX_COMPLETE_SUCCESS; } -static enum tcpc_transmit_complete it83xx_send_hw_reset(enum usbpd_port port, - enum tcpci_msg_type reset_type) +static enum tcpc_transmit_complete +it83xx_send_hw_reset(enum usbpd_port port, enum tcpci_msg_type reset_type) { if (reset_type == TCPCI_MSG_CABLE_RESET) IT83XX_USBPD_MTSR0(port) |= USBPD_REG_MASK_CABLE_ENABLE; @@ -288,21 +286,23 @@ static void it83xx_enable_vconn(enum usbpd_port port, int enabled) /* Disable unused CC to become VCONN */ if (cc_pin == USBPD_CC_PIN_1) { IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port); - IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port) - & ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) - | USBPD_REG_MASK_DISCONNECT_POWER_CC1; + IT83XX_USBPD_CCPSR(port) = + (IT83XX_USBPD_CCPSR(port) & + ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) | + USBPD_REG_MASK_DISCONNECT_POWER_CC1; } else { IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port); - IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port) - & ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) - | USBPD_REG_MASK_DISCONNECT_POWER_CC2; + IT83XX_USBPD_CCPSR(port) = + (IT83XX_USBPD_CCPSR(port) & + ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) | + USBPD_REG_MASK_DISCONNECT_POWER_CC2; } } else { /* Enable cc1 and cc2 */ IT83XX_USBPD_CCCSR(port) &= ~0xaa; IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC1 | - USBPD_REG_MASK_DISCONNECT_POWER_CC2); + USBPD_REG_MASK_DISCONNECT_POWER_CC2); } } @@ -359,8 +359,8 @@ static void it83xx_set_power_role(enum usbpd_port port, int power_role) static void it83xx_set_data_role(enum usbpd_port port, int pd_role) { /* 0: PD_ROLE_UFP 1: PD_ROLE_DFP */ - IT83XX_USBPD_PDMSR(port) = - (IT83XX_USBPD_PDMSR(port) & ~0xc) | ((pd_role & 0x1) << 2); + IT83XX_USBPD_PDMSR(port) = (IT83XX_USBPD_PDMSR(port) & ~0xc) | + ((pd_role & 0x1) << 2); } #ifdef CONFIG_USB_PD_FRS_TCPC @@ -378,15 +378,18 @@ static int it83xx_tcpm_set_frs_enable(int port, int enable) /* W/C status */ IT83XX_USBPD_PD30IR(port) = 0x3f; /* Enable FRS detection (cc to GND) interrupt */ - IT83XX_USBPD_MPD30IR(port) &= ~(USBPD_REG_MASK_PD30_ISR | - USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); + IT83XX_USBPD_MPD30IR(port) &= + ~(USBPD_REG_MASK_PD30_ISR | + USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); /* Enable FRS detection (cc to GND) */ - IT83XX_USBPD_PDQSCR(port) = (IT83XX_USBPD_PDQSCR(port) & ~mask) - | USBPD_REG_FAST_SWAP_DETECT_ENABLE; + IT83XX_USBPD_PDQSCR(port) = + (IT83XX_USBPD_PDQSCR(port) & ~mask) | + USBPD_REG_FAST_SWAP_DETECT_ENABLE; } else { /* Disable FRS detection (cc to GND) interrupt */ - IT83XX_USBPD_MPD30IR(port) |= (USBPD_REG_MASK_PD30_ISR | - USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); + IT83XX_USBPD_MPD30IR(port) |= + (USBPD_REG_MASK_PD30_ISR | + USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); /* Disable FRS detection and requestion */ IT83XX_USBPD_PDQSCR(port) &= ~mask; } @@ -409,7 +412,7 @@ static void it83xx_init(enum usbpd_port port, int role) * (= retry count + 1) */ IT83XX_USBPD_BMCSR(port) = (IT83XX_USBPD_BMCSR(port) & ~0x70) | - ((CONFIG_PD_RETRY_COUNT + 1) << 4); + ((CONFIG_PD_RETRY_COUNT + 1) << 4); /* Disable Rx decode */ it83xx_tcpm_set_rx_enable(port, 0); if (IS_ENABLED(CONFIG_USB_PD_TCPMV1)) { @@ -440,7 +443,7 @@ static void it83xx_init(enum usbpd_port port, int role) IT83XX_USBPD_IMR(port) = 0xff; /* enable tx done and reset detect interrupt */ IT83XX_USBPD_IMR(port) &= ~(USBPD_REG_MASK_MSG_TX_DONE | - USBPD_REG_MASK_HARD_RESET_DETECT); + USBPD_REG_MASK_HARD_RESET_DETECT); #ifdef IT83XX_INTC_PLUG_IN_OUT_SUPPORT /* * when tcpc detect type-c plug in (cc lines voltage change), it will @@ -473,7 +476,7 @@ static void it83xx_init(enum usbpd_port port, int role) } static void it83xx_select_polarity(enum usbpd_port port, - enum usbpd_cc_pin cc_pin) + enum usbpd_cc_pin cc_pin) { /* cc1/cc2 selection */ if (cc_pin == USBPD_CC_PIN_1) @@ -519,7 +522,7 @@ static int it83xx_tcpm_release(int port) } static int it83xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { *cc2 = it83xx_get_cc(port, USBPD_CC_PIN_2); *cc1 = it83xx_get_cc(port, USBPD_CC_PIN_1); @@ -567,7 +570,8 @@ static int it83xx_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) { enum usbpd_cc_pin cc_pin = (polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ? - USBPD_CC_PIN_1 : USBPD_CC_PIN_2; + USBPD_CC_PIN_1 : + USBPD_CC_PIN_2; it83xx_select_polarity(port, cc_pin); @@ -613,7 +617,8 @@ static int it83xx_tcpm_set_vconn(int port, int enable) /* Turn on Vconn power switch. */ board_pd_vconn_ctrl(port, USBPD_GET_PULL_CC_SELECTION(port) ? - USBPD_CC_PIN_2 : USBPD_CC_PIN_1, + USBPD_CC_PIN_2 : + USBPD_CC_PIN_1, enable); } else { /* @@ -685,10 +690,8 @@ static int it83xx_tcpm_set_rx_enable(int port, int enable) return EC_SUCCESS; } -static int it83xx_tcpm_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data) +static int it83xx_tcpm_transmit(int port, enum tcpci_msg_type type, + uint16_t header, const uint32_t *data) { int status = TCPC_TX_COMPLETE_FAILED; @@ -698,10 +701,7 @@ static int it83xx_tcpm_transmit(int port, case TCPCI_MSG_SOP_PRIME_PRIME: case TCPCI_MSG_SOP_DEBUG_PRIME: case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME: - status = it83xx_tx_data(port, - type, - header, - data); + status = it83xx_tx_data(port, type, header, data); break; case TCPCI_MSG_TX_BIST_MODE_2: it83xx_send_bist_mode2_pattern(port); @@ -720,12 +720,13 @@ static int it83xx_tcpm_transmit(int port, return EC_SUCCESS; } -static int it83xx_tcpm_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) +static int +it83xx_tcpm_get_chip_info(int port, int live, + struct ec_response_pd_chip_info_v1 *chip_info) { chip_info->vendor_id = USB_VID_ITE; - chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) | - IT83XX_GCTRL_CHIPID2); + chip_info->product_id = + ((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2); chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf; chip_info->fw_version_number = 0xEC; @@ -757,16 +758,18 @@ static void it83xx_tcpm_switch_plug_out_type(int port) if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) || (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA)) /* We're source, switch to detect audio/debug plug out. */ - IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) & - ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) | - USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT | - USBPD_REG_PLUG_OUT_SELECT; + IT83XX_USBPD_TCDCR(port) = + (IT83XX_USBPD_TCDCR(port) & + ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) | + USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT | + USBPD_REG_PLUG_OUT_SELECT; else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD) /* We're source, switch to detect sink plug out. */ - IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) & - ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE & - ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) | - USBPD_REG_PLUG_OUT_SELECT; + IT83XX_USBPD_TCDCR(port) = + (IT83XX_USBPD_TCDCR(port) & + ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE & + ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) | + USBPD_REG_PLUG_OUT_SELECT; else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF) /* * We're sink, disable detect interrupt, so messages on cc line @@ -891,8 +894,9 @@ static void it83xx_tcpm_hook_disconnect(void) * Switch to detect plug in and enable detect plug in interrupt, * since pd task has detected a type-c physical disconnected. */ - IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT | - USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE); + IT83XX_USBPD_TCDCR(port) &= + ~(USBPD_REG_PLUG_OUT_SELECT | + USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE); /* exit BIST test data mode */ USBPD_SW_RESET(port); @@ -916,28 +920,28 @@ DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it83xx_tcpm_hook_disconnect, HOOK_PRIO_DEFAULT); const struct tcpm_drv it83xx_tcpm_drv = { - .init = &it83xx_tcpm_init, - .release = &it83xx_tcpm_release, - .get_cc = &it83xx_tcpm_get_cc, - .select_rp_value = &it83xx_tcpm_select_rp_value, - .set_cc = &it83xx_tcpm_set_cc, - .set_polarity = &it83xx_tcpm_set_polarity, + .init = &it83xx_tcpm_init, + .release = &it83xx_tcpm_release, + .get_cc = &it83xx_tcpm_get_cc, + .select_rp_value = &it83xx_tcpm_select_rp_value, + .set_cc = &it83xx_tcpm_set_cc, + .set_polarity = &it83xx_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &it83xx_tcpm_decode_sop_prime_enable, + .sop_prime_enable = &it83xx_tcpm_decode_sop_prime_enable, #endif - .set_vconn = &it83xx_tcpm_set_vconn, - .set_msg_header = &it83xx_tcpm_set_msg_header, - .set_rx_enable = &it83xx_tcpm_set_rx_enable, - .get_message_raw = &it83xx_tcpm_get_message_raw, - .transmit = &it83xx_tcpm_transmit, + .set_vconn = &it83xx_tcpm_set_vconn, + .set_msg_header = &it83xx_tcpm_set_msg_header, + .set_rx_enable = &it83xx_tcpm_set_rx_enable, + .get_message_raw = &it83xx_tcpm_get_message_raw, + .transmit = &it83xx_tcpm_transmit, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = NULL, + .drp_toggle = NULL, #endif - .get_chip_info = &it83xx_tcpm_get_chip_info, + .get_chip_info = &it83xx_tcpm_get_chip_info, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &it83xx_tcpm_enter_low_power_mode, + .enter_low_power_mode = &it83xx_tcpm_enter_low_power_mode, #endif #ifdef CONFIG_USB_PD_FRS_TCPC - .set_frs_enable = &it83xx_tcpm_set_frs_enable, + .set_frs_enable = &it83xx_tcpm_set_frs_enable, #endif }; -- cgit v1.2.1 From 89511e12259054d0a42d8c883aad547a286fd321 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:06 -0600 Subject: include/motion_lid.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e6f66ffae43ff6427c7a02d246e4c2f4bf034b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730367 Reviewed-by: Jeremy Bettis --- include/motion_lid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/motion_lid.h b/include/motion_lid.h index 28ddcaec24..04ef687fc0 100644 --- a/include/motion_lid.h +++ b/include/motion_lid.h @@ -34,4 +34,4 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args); void motion_lid_calc(void); -#endif /* __CROS_EC_MOTION_LID_H */ +#endif /* __CROS_EC_MOTION_LID_H */ -- cgit v1.2.1 From 8dd777b2c26fa220f8418c4e98494a5f386177a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:44 -0600 Subject: chip/stm32/config-stm32g473xc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idb57429abdbffdc3c39feef2ec551a7264d64608 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729477 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32g473xc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h index 0317b69491..40658edd56 100644 --- a/chip/stm32/config-stm32g473xc.h +++ b/chip/stm32/config-stm32g473xc.h @@ -42,11 +42,11 @@ * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased * at 0x2001 8000 address to be accessed by all bus controllers. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00020000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00020000 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 12 @@ -56,13 +56,13 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 +#define CONFIG_IRQ_COUNT 101 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 -- cgit v1.2.1 From 3aab52fb718e5d6b3e3eddb151e6bf5d5a4b5420 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:19 -0600 Subject: include/flash_log.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a1e69a64dd09de43a5f4236e78eac7aa7485629 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730288 Reviewed-by: Jeremy Bettis --- include/flash_log.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/flash_log.h b/include/flash_log.h index e504df6ee7..41287f88c7 100644 --- a/include/flash_log.h +++ b/include/flash_log.h @@ -16,10 +16,10 @@ enum flash_event_type { FE_LOG_CORRUPTED = 1, FE_TPM_I2C_ERROR = 2, FE_LOG_OVERFLOWS = 3, /* A single byte, overflow counter. */ - FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */ - FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */ - FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */ - FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */ + FE_LOG_LOCKS = 4, /* A single byte, lock failures counter. */ + FE_LOG_NVMEM = 5, /* NVMEM failure, variable structure. */ + FE_LOG_TPM_WIPE_ERROR = 6, /* Failed to wipe the TPM */ + FE_LOG_TRNG_STALL = 7, /* Stall while retrieving a random number. */ FE_LOG_DCRYPTO_FAILURE = 8, /* Dcrypto had to be reset. */ /* @@ -92,9 +92,9 @@ struct nvmem_failure_payload { #define FLASH_LOG_PAYLOAD_SIZE(size) ((size)&FLASH_LOG_PAYLOAD_SIZE_MASK) /* Size of log entry for a specific payload size. */ -#define FLASH_LOG_ENTRY_SIZE(payload_sz) \ - ((FLASH_LOG_PAYLOAD_SIZE(payload_sz) + \ - sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \ +#define FLASH_LOG_ENTRY_SIZE(payload_sz) \ + ((FLASH_LOG_PAYLOAD_SIZE(payload_sz) + \ + sizeof(struct flash_log_entry) + CONFIG_FLASH_WRITE_SIZE - 1) & \ ~(CONFIG_FLASH_WRITE_SIZE - 1)) /* -- cgit v1.2.1 From 426799a19b873c1dc7020c4cf5ae857792500857 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:25 -0600 Subject: driver/led/lp5562.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie72c5d767dd9be0fef205dde765bfd1173d0e062 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730016 Reviewed-by: Jeremy Bettis --- driver/led/lp5562.h | 64 ++++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/driver/led/lp5562.h b/driver/led/lp5562.h index 75e820aab7..8dd4dc64d4 100644 --- a/driver/led/lp5562.h +++ b/driver/led/lp5562.h @@ -8,40 +8,40 @@ #ifndef __CROS_EC_LP5562_H #define __CROS_EC_LP5562_H -#define LP5562_REG_ENABLE 0x00 -#define LP5562_REG_OP_MODE 0x01 -#define LP5562_REG_B_PWM 0x02 -#define LP5562_REG_G_PWM 0x03 -#define LP5562_REG_R_PWM 0x04 -#define LP5562_REG_B_CURRENT 0x05 -#define LP5562_REG_G_CURRENT 0x06 -#define LP5562_REG_R_CURRENT 0x07 -#define LP5562_REG_CONFIG 0x08 -#define LP5562_REG_ENG1_PC 0x09 -#define LP5562_REG_ENG2_PC 0x0a -#define LP5562_REG_ENG3_PC 0x0b -#define LP5562_REG_STATUS 0x0c -#define LP5562_REG_RESET 0x0d -#define LP5562_REG_W_PWM 0x0e -#define LP5562_REG_W_CURRENT 0x0f -#define LP5562_REG_LED_MAP 0x70 - -#define LP5562_REG_ENG_PROG(n) (0x10 + ((n)-1) * 0x20) +#define LP5562_REG_ENABLE 0x00 +#define LP5562_REG_OP_MODE 0x01 +#define LP5562_REG_B_PWM 0x02 +#define LP5562_REG_G_PWM 0x03 +#define LP5562_REG_R_PWM 0x04 +#define LP5562_REG_B_CURRENT 0x05 +#define LP5562_REG_G_CURRENT 0x06 +#define LP5562_REG_R_CURRENT 0x07 +#define LP5562_REG_CONFIG 0x08 +#define LP5562_REG_ENG1_PC 0x09 +#define LP5562_REG_ENG2_PC 0x0a +#define LP5562_REG_ENG3_PC 0x0b +#define LP5562_REG_STATUS 0x0c +#define LP5562_REG_RESET 0x0d +#define LP5562_REG_W_PWM 0x0e +#define LP5562_REG_W_CURRENT 0x0f +#define LP5562_REG_LED_MAP 0x70 + +#define LP5562_REG_ENG_PROG(n) (0x10 + ((n)-1) * 0x20) /* Brightness range: 0x00 - 0xff */ -#define LP5562_COLOR_NONE 0x000000 -#define LP5562_COLOR_RED(b) (0x010000 * (b)) -#define LP5562_COLOR_GREEN(b) (0x000100 * (b)) -#define LP5562_COLOR_BLUE(b) (0x000001 * (b)) - -#define LP5562_ENG_SEL_NONE 0x0 -#define LP5562_ENG_SEL_1 0x1 -#define LP5562_ENG_SEL_2 0x2 -#define LP5562_ENG_SEL_3 0x3 - -#define LP5562_ENG_HOLD 0x0 -#define LP5562_ENG_STEP 0x1 -#define LP5562_ENG_RUN 0x2 +#define LP5562_COLOR_NONE 0x000000 +#define LP5562_COLOR_RED(b) (0x010000 * (b)) +#define LP5562_COLOR_GREEN(b) (0x000100 * (b)) +#define LP5562_COLOR_BLUE(b) (0x000001 * (b)) + +#define LP5562_ENG_SEL_NONE 0x0 +#define LP5562_ENG_SEL_1 0x1 +#define LP5562_ENG_SEL_2 0x2 +#define LP5562_ENG_SEL_3 0x3 + +#define LP5562_ENG_HOLD 0x0 +#define LP5562_ENG_STEP 0x1 +#define LP5562_ENG_RUN 0x2 /* Power on and initialize LP5562. */ int lp5562_poweron(void); -- cgit v1.2.1 From 3225d9e149359e40ca256cb3eb7d32f7e6ea3cd2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:56 -0600 Subject: zephyr/shim/include/motionsense_sensors_defs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifded8b0402649c32349a8132845b47018ccb4e93 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730585 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/motionsense_sensors_defs.h | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/zephyr/shim/include/motionsense_sensors_defs.h b/zephyr/shim/include/motionsense_sensors_defs.h index a9535d3b5d..8adae0b757 100644 --- a/zephyr/shim/include/motionsense_sensors_defs.h +++ b/zephyr/shim/include/motionsense_sensors_defs.h @@ -10,7 +10,7 @@ #include "common.h" -#define SENSOR_ID(id) DT_CAT(SENSOR_, id) +#define SENSOR_ID(id) DT_CAT(SENSOR_, id) /* Define the SENSOR_ID if: * DT_NODE_HAS_STATUS(id, okay) && !DT_NODE_HAS_PROP(id, alternate_for) @@ -24,7 +24,7 @@ enum sensor_id { #if DT_NODE_EXISTS(SENSOR_NODE) DT_FOREACH_CHILD(SENSOR_NODE, SENSOR_ID_WITH_COMMA) #endif - SENSOR_COUNT, + SENSOR_COUNT, }; #undef SENSOR_ID_WITH_COMMA @@ -39,7 +39,7 @@ enum sensor_alt_id { #if DT_NODE_EXISTS(SENSOR_ALT_NODE) DT_FOREACH_CHILD(SENSOR_ALT_NODE, SENSOR_ID_WITH_COMMA) #endif - SENSOR_ALT_COUNT, + SENSOR_ALT_COUNT, }; /* @@ -73,8 +73,8 @@ enum sensor_alt_id { * }; */ #ifdef CONFIG_LID_ANGLE -#define CONFIG_LID_ANGLE_SENSOR_LID SENSOR_ID(DT_NODELABEL(lid_accel)) -#define CONFIG_LID_ANGLE_SENSOR_BASE SENSOR_ID(DT_NODELABEL(base_accel)) +#define CONFIG_LID_ANGLE_SENSOR_LID SENSOR_ID(DT_NODELABEL(lid_accel)) +#define CONFIG_LID_ANGLE_SENSOR_BASE SENSOR_ID(DT_NODELABEL(base_accel)) #endif /* @@ -90,12 +90,11 @@ enum sensor_alt_id { * }; */ #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, accel_force_mode_sensors) -#define SENSOR_IN_FORCE_MODE(i, id) \ +#define SENSOR_IN_FORCE_MODE(i, id) \ | BIT(SENSOR_ID(DT_PHANDLE_BY_IDX(id, accel_force_mode_sensors, i))) -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (0 LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, \ - accel_force_mode_sensors), SENSOR_IN_FORCE_MODE, (), \ - SENSOR_INFO_NODE)) +#define CONFIG_ACCEL_FORCE_MODE_MASK \ + (0 LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, accel_force_mode_sensors), \ + SENSOR_IN_FORCE_MODE, (), SENSOR_INFO_NODE)) #endif #endif /* __CROS_EC_MOTIONSENSE_SENSORS_DEFS_H */ -- cgit v1.2.1 From 5e1af39c86f47eaebd558d5edec5cd51cf0ffe51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:40 -0600 Subject: board/cret/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If98a61f0ac09c82ed77147d290544c0adc2a6322 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728187 Reviewed-by: Jeremy Bettis --- board/cret/board.h | 49 +++++++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 30 deletions(-) diff --git a/board/cret/board.h b/board/cret/board.h index 69394fe218..4ad8539c4b 100644 --- a/board/cret/board.h +++ b/board/cret/board.h @@ -47,7 +47,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* USB */ #define CONFIG_BC12_DETECT_PI3USB9201 @@ -74,23 +74,22 @@ #undef PD_POWER_SUPPLY_TURN_OFF_DELAY #undef CONFIG_USBC_VCONN_SWAP_DELAY_US /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ - +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -98,18 +97,17 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT #define CONFIG_LID_ANGLE @@ -132,24 +130,15 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From 5b55113f4808f84b74d3af3a3c766319ef3abc80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:40 -0600 Subject: board/npcx_evb_arm/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If33cc13e21b468d501cd340bc1cb6764edc950f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728771 Reviewed-by: Jeremy Bettis --- board/npcx_evb_arm/board.c | 75 +++++++++++++++++++++------------------------- 1 file changed, 34 insertions(+), 41 deletions(-) diff --git a/board/npcx_evb_arm/board.c b/board/npcx_evb_arm/board.c index abb6e2279b..63024ced5a 100644 --- a/board/npcx_evb_arm/board.c +++ b/board/npcx_evb_arm/board.c @@ -35,16 +35,19 @@ /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 }, [PWM_CH_KBLIGHT] = { 1, 0, 10000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -53,7 +56,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = 0, /* Use MFT id to control fan */ + .ch = 0, /* Use MFT id to control fan */ .pgood_gpio = GPIO_PGOOD_FAN, .enable_gpio = -1, }; @@ -72,48 +75,38 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master0-0", - .port = NPCX_I2C_PORT0_0, - .kbps = 100, - .scl = GPIO_I2C0_SCL0, - .sda = GPIO_I2C0_SDA0 - }, - { - .name = "master0-1", - .port = NPCX_I2C_PORT0_1, - .kbps = 100, - .scl = GPIO_I2C0_SCL1, - .sda = GPIO_I2C0_SDA1 - }, - { - .name = "master1", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "master2", - .port = NPCX_I2C_PORT2, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "master3", - .port = NPCX_I2C_PORT3, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "master0-0", + .port = NPCX_I2C_PORT0_0, + .kbps = 100, + .scl = GPIO_I2C0_SCL0, + .sda = GPIO_I2C0_SDA0 }, + { .name = "master0-1", + .port = NPCX_I2C_PORT0_1, + .kbps = 100, + .scl = GPIO_I2C0_SCL1, + .sda = GPIO_I2C0_SDA1 }, + { .name = "master1", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "master2", + .port = NPCX_I2C_PORT2, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "master3", + .port = NPCX_I2C_PORT3, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From e0124ac686f552d8b604d423e343497743a1f81c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:02 -0600 Subject: baseboard/kukui/charger_mt6370.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4c30ff9b72d1f9c5d89057f55e7748d5630f63a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727921 Reviewed-by: Jeremy Bettis --- baseboard/kukui/charger_mt6370.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/baseboard/kukui/charger_mt6370.c b/baseboard/kukui/charger_mt6370.c index 99e51aead2..03077fdfa9 100644 --- a/baseboard/kukui/charger_mt6370.c +++ b/baseboard/kukui/charger_mt6370.c @@ -51,7 +51,7 @@ static void update_plt_resume(void) } DECLARE_HOOK(HOOK_CHIPSET_RESUME, update_plt_resume, HOOK_PRIO_DEFAULT); -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* wait time to evaluate charger thermal status */ static timestamp_t thermal_wait_until; @@ -304,8 +304,8 @@ void mt6370_charger_profile_override(struct charge_state_data *curr) * and TE function. */ hook_call_deferred( - &charge_enable_eoc_and_te_data, - (4.5 * SECOND)); + &charge_enable_eoc_and_te_data, + (4.5 * SECOND)); } } } @@ -339,7 +339,6 @@ void mt6370_charger_profile_override(struct charge_state_data *curr) curr->batt.state_of_charge = MAX(BATTERY_LEVEL_NEAR_FULL, curr->batt.state_of_charge); } - } #ifndef CONFIG_BATTERY_SMART @@ -352,13 +351,12 @@ static void board_charge_termination(void) te = 1; } } -DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, - board_charge_termination, +DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination, HOOK_PRIO_DEFAULT); #endif -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { prev_charge_limit = charge_ma; prev_charge_mv = charge_mv; -- cgit v1.2.1 From 7aad477904f73b71d3e256b13378863bb3a46b98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 22:06:37 -0600 Subject: test/utils_str.c: Split combined TEST_CHECKs For readability, split any combined TEST_CHECK statements into separate statements. BUG=b:236386294 BRANCH=none TEST=test passes Change-Id: I523232926dc2108f38a4767fef3f8c6b7c6d884d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731078 Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes --- test/utils_str.c | 50 +++++++++++++++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 19 deletions(-) diff --git a/test/utils_str.c b/test/utils_str.c index f184abffa6..a855af1886 100644 --- a/test/utils_str.c +++ b/test/utils_str.c @@ -15,16 +15,28 @@ static int test_isalpha(void) { - TEST_CHECK(isalpha('a') && isalpha('z') && isalpha('A') && - isalpha('Z') && !isalpha('0') && !isalpha('~') && - !isalpha(' ') && !isalpha('\0') && !isalpha('\n')); + TEST_CHECK(isalpha('a')); + TEST_CHECK(isalpha('z')); + TEST_CHECK(isalpha('A')); + TEST_CHECK(isalpha('Z')); + TEST_CHECK(!isalpha('0')); + TEST_CHECK(!isalpha('~')); + TEST_CHECK(!isalpha(' ')); + TEST_CHECK(!isalpha('\0')); + TEST_CHECK(!isalpha('\n')); } static int test_isprint(void) { - TEST_CHECK(isprint('a') && isprint('z') && isprint('A') && - isprint('Z') && isprint('0') && isprint('~') && - isprint(' ') && !isprint('\0') && !isprint('\n')); + TEST_CHECK(isprint('a')); + TEST_CHECK(isprint('z')); + TEST_CHECK(isprint('A')); + TEST_CHECK(isprint('Z')); + TEST_CHECK(isprint('0')); + TEST_CHECK(isprint('~')); + TEST_CHECK(isprint(' ')); + TEST_CHECK(!isprint('\0')); + TEST_CHECK(!isprint('\n')); } static int test_strstr(void) @@ -229,27 +241,27 @@ static int test_strnlen(void) static int test_strcasecmp(void) { - TEST_CHECK((strcasecmp("test string", "TEST strIng") == 0) && - (strcasecmp("test123!@#", "TesT123!@#") == 0) && - (strcasecmp("lower", "UPPER") != 0)); + TEST_CHECK(strcasecmp("test string", "TEST strIng") == 0); + TEST_CHECK(strcasecmp("test123!@#", "TesT123!@#") == 0); + TEST_CHECK(strcasecmp("lower", "UPPER") != 0); } static int test_strncasecmp(void) { - TEST_CHECK((strncasecmp("test string", "TEST str", 4) == 0) && - (strncasecmp("test string", "TEST str", 8) == 0) && - (strncasecmp("test123!@#", "TesT321!@#", 5) != 0) && - (strncasecmp("test123!@#", "TesT321!@#", 4) == 0) && - (strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0) && - (strncasecmp("1test123", "teststr", 0) == 0)); + TEST_CHECK(strncasecmp("test string", "TEST str", 4) == 0); + TEST_CHECK(strncasecmp("test string", "TEST str", 8) == 0); + TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 5) != 0); + TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 4) == 0); + TEST_CHECK(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0); + TEST_CHECK(strncasecmp("1test123", "teststr", 0) == 0); } static int test_atoi(void) { - TEST_CHECK((atoi(" 901") == 901) && - (atoi("-12c") == -12) && - (atoi(" 0 ") == 0) && - (atoi("\t111") == 111)); + TEST_CHECK(atoi(" 901") == 901); + TEST_CHECK(atoi("-12c") == -12); + TEST_CHECK(atoi(" 0 ") == 0); + TEST_CHECK(atoi("\t111") == 111); } static int test_snprintf(void) -- cgit v1.2.1 From c554e40e548027672857c51ffc365844fe9c3409 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:04 -0600 Subject: chip/stm32/config-stm32l442.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I705b34bd0e869b048760fa2c59af9c65f76bb9e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729483 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l442.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/stm32/config-stm32l442.h b/chip/stm32/config-stm32l442.h index 8a2a284d69..d310f6dea8 100644 --- a/chip/stm32/config-stm32l442.h +++ b/chip/stm32/config-stm32l442.h @@ -4,24 +4,24 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 -- cgit v1.2.1 From f92752acdc3c0bd42bb77bdd548ab413be8a094a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:50 -0600 Subject: driver/temp_sensor/amd_r19me4070.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I25b5e411b98165ef96953b2d30d5345b80f12b9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730112 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/amd_r19me4070.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/temp_sensor/amd_r19me4070.h b/driver/temp_sensor/amd_r19me4070.h index d3c7977ba5..0ced7ecaf9 100644 --- a/driver/temp_sensor/amd_r19me4070.h +++ b/driver/temp_sensor/amd_r19me4070.h @@ -9,7 +9,7 @@ #define __CROS_EC_R19ME4070_H /* GPU features */ -#define R19ME4070_LOCAL 0 +#define R19ME4070_LOCAL 0 /* * get GPU temperature value and move to *tem_ptr -- cgit v1.2.1 From f2f7be78461a7f9d7381f355f6f7a101275188dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:19 -0600 Subject: driver/ina3221.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52c73f3b45b9a8de7f6e98cf45fa556959a0c7e6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729989 Reviewed-by: Jeremy Bettis --- driver/ina3221.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/driver/ina3221.h b/driver/ina3221.h index 4d8c8211b4..7d978df6c8 100644 --- a/driver/ina3221.h +++ b/driver/ina3221.h @@ -8,8 +8,8 @@ #ifndef __CROS_EC_INA3221_H #define __CROS_EC_INA3221_H -#define INA3221_REG_CONFIG 0x00 -#define INA3221_REG_MASK 0x0F +#define INA3221_REG_CONFIG 0x00 +#define INA3221_REG_MASK 0x0F /* * Common bits are: @@ -18,12 +18,12 @@ * conversion time = 1.1 ms * mode = shunt and bus, continuous. */ -#define INA3221_CONFIG_BASE 0x8127 +#define INA3221_CONFIG_BASE 0x8127 /* Bus voltage: lower 3 bits clear, LSB = 8 mV */ #define INA3221_BUS_MV(reg) (reg) /* Shunt voltage: lower 3 bits clear, LSB = 40 uV */ -#define INA3221_SHUNT_UV(reg) ((reg) * (40/8)) +#define INA3221_SHUNT_UV(reg) ((reg) * (40 / 8)) enum ina3221_channel { INA3221_CHAN_1 = 0, @@ -43,9 +43,9 @@ enum ina3221_register { /* Configuration table - defined in board file. */ struct ina3221_t { - int port; /* I2C port index */ - uint8_t address; /* I2C address */ - const char *name[INA3221_CHAN_COUNT]; /* Channel names */ + int port; /* I2C port index */ + uint8_t address; /* I2C address */ + const char *name[INA3221_CHAN_COUNT]; /* Channel names */ }; /* External config in board file */ -- cgit v1.2.1 From dd960cfbaf3a0fe1efe5fb347751bf61d51b879a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:29 -0600 Subject: board/boldar/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I28a56a51dd8bb69b6586083ae4e06602e858954d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728064 Reviewed-by: Jeremy Bettis --- board/boldar/board.h | 110 ++++++++++++++++++++++++--------------------------- 1 file changed, 52 insertions(+), 58 deletions(-) diff --git a/board/boldar/board.h b/board/boldar/board.h index 12409a5435..44ca16ccc6 100644 --- a/board/boldar/board.h +++ b/board/boldar/board.h @@ -51,19 +51,18 @@ /* TCS3400 ALS/RGB */ #define CONFIG_ALS -#define ALS_COUNT 1 +#define ALS_COUNT 1 #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ /* @@ -73,36 +72,36 @@ */ #define CONFIG_USB_PID 0x503E -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x37 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x37 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ /* BC 1.2 */ @@ -111,8 +110,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -120,45 +119,44 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -189,11 +187,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From b7791d9b80577463ad86944710169f65bf1104fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:06 -0600 Subject: board/fleex/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24b9f0f22adfec2ead2b485926a11fb3c50f43e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728373 Reviewed-by: Jeremy Bettis --- board/fleex/led.c | 47 ++++++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/board/fleex/led.c b/board/fleex/led.c index bf3fd6ccec..dc67160013 100644 --- a/board/fleex/led.c +++ b/board/fleex/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 10; @@ -19,23 +19,32 @@ __override const int led_charge_lvl_2 = 100; /* Fleex: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 15e2f2d2fafd587909a2b71e1a5ddbed1813761c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:13 -0600 Subject: include/system.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15d5e90dedaa40be5e47f93ba9faed8e6e0192ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730414 Reviewed-by: Jeremy Bettis --- include/system.h | 64 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/include/system.h b/include/system.h index 0fc0206bb3..9356aa4e6f 100644 --- a/include/system.h +++ b/include/system.h @@ -328,17 +328,17 @@ const char *system_get_build_info(void); * Hard reset. Cuts power to the entire system. If not present, does a soft * reset which just resets the core and on-chip peripherals. */ -#define SYSTEM_RESET_HARD BIT(0) +#define SYSTEM_RESET_HARD BIT(0) /* * Preserve existing reset flags. Used by flash pre-init when it discovers it * needs to do a hard reset to clear write protect registers. */ -#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1) +#define SYSTEM_RESET_PRESERVE_FLAGS BIT(1) /* * Leave AP off on next reboot, instead of powering it on to do EC software * sync. */ -#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2) +#define SYSTEM_RESET_LEAVE_AP_OFF BIT(2) /* * Indicate that this was a manually triggered reset. */ @@ -346,20 +346,20 @@ const char *system_get_build_info(void); /* * Wait for reset pin to be driven, rather that resetting ourselves. */ -#define SYSTEM_RESET_WAIT_EXT BIT(4) +#define SYSTEM_RESET_WAIT_EXT BIT(4) /* * Indicate that this reset was triggered by an AP watchdog */ -#define SYSTEM_RESET_AP_WATCHDOG BIT(5) +#define SYSTEM_RESET_AP_WATCHDOG BIT(5) /* * Stay in RO next reboot, instead of potentially selecting RW during EFS. */ -#define SYSTEM_RESET_STAY_IN_RO BIT(6) +#define SYSTEM_RESET_STAY_IN_RO BIT(6) /* * Hibernate reset. Reset EC when wake up from hibernate mode * (the most power saving mode). */ -#define SYSTEM_RESET_HIBERNATE BIT(7) +#define SYSTEM_RESET_HIBERNATE BIT(7) /** * Reset the system. @@ -369,7 +369,8 @@ const char *system_get_build_info(void); #ifndef TEST_FUZZ noreturn #endif -void system_reset(int flags); + void + system_reset(int flags); /** * Set a scratchpad register to the specified value. @@ -440,7 +441,6 @@ __override_proto const char *board_read_serial(void); */ __override_proto int board_write_serial(const char *serial); - /** * Optional board-level callback functions to read a unique MAC address per * chip. Default implementation reads from flash. @@ -525,7 +525,9 @@ timestamp_t system_get_rtc(void); #ifdef CONFIG_RTC void print_system_rtc(enum console_channel channel); #else -static inline void print_system_rtc(enum console_channel channel) { } +static inline void print_system_rtc(enum console_channel channel) +{ +} #endif /* !defined(CONFIG_RTC) */ /** @@ -538,32 +540,31 @@ enum { /* * Sleep masks to prevent going in to deep sleep. */ - SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */ - SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ + SLEEP_MASK_AP_RUN = BIT(0), /* the main CPU is running */ + SLEEP_MASK_UART = BIT(1), /* UART communication ongoing */ SLEEP_MASK_I2C_CONTROLLER = BIT(2), /* I2C controller comms ongoing */ - SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ - SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ - SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ - SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ + SLEEP_MASK_CHARGING = BIT(3), /* Charging loop ongoing */ + SLEEP_MASK_USB_PWR = BIT(4), /* USB power loop ongoing */ + SLEEP_MASK_USB_PD = BIT(5), /* USB PD device connected */ + SLEEP_MASK_SPI = BIT(6), /* SPI communications ongoing */ SLEEP_MASK_I2C_PERIPHERAL = BIT(7), /* I2C peripheral comms ongoing */ - SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */ + SLEEP_MASK_FAN = BIT(8), /* Fan control loop ongoing */ SLEEP_MASK_USB_DEVICE = BIT(9), /* Generic USB device in use */ - SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */ - SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence - * detection ongoing */ - SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */ - SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */ - SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */ - SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */ - + SLEEP_MASK_PWM = BIT(10), /* PWM output is enabled */ + SLEEP_MASK_PHYSICAL_PRESENCE = BIT(11), /* Physical presence + * detection ongoing */ + SLEEP_MASK_PLL = BIT(12), /* High-speed PLL in-use */ + SLEEP_MASK_ADC = BIT(13), /* ADC conversion ongoing */ + SLEEP_MASK_EMMC = BIT(14), /* eMMC emulation ongoing */ + SLEEP_MASK_FORCE_NO_DSLEEP = BIT(15), /* Force disable. */ /* * Sleep masks to prevent using slow speed clock in deep sleep. */ - SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ - SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ + SLEEP_MASK_JTAG = BIT(16), /* JTAG is in use. */ + SLEEP_MASK_CONSOLE = BIT(17), /* Console is in use. */ - SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ + SLEEP_MASK_FORCE_NO_LOW_SPEED = BIT(31) /* Force disable. */ }; /* @@ -578,10 +579,9 @@ extern atomic_t sleep_mask; */ #ifndef CONFIG_LOW_POWER_S0 -#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff)) +#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff)) #else -#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & \ - (~SLEEP_MASK_AP_RUN))) +#define DEEP_SLEEP_ALLOWED (!(sleep_mask & 0x0000ffff & (~SLEEP_MASK_AP_RUN))) #endif #define LOW_SPEED_DEEP_SLEEP_ALLOWED (!(sleep_mask & 0xffff0000)) @@ -761,4 +761,4 @@ uint32_t flash_get_rw_offset(enum ec_image copy); */ void system_compensate_rtc(void); -#endif /* __CROS_EC_SYSTEM_H */ +#endif /* __CROS_EC_SYSTEM_H */ -- cgit v1.2.1 From b3ad1159bfa94366b6d5a60fa64101fe75341c8e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:35 -0600 Subject: board/kakadu/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c9fbcfe1c16d44fd7c13b0cfaec81a529e1582e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728477 Reviewed-by: Jeremy Bettis --- board/kakadu/led.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/kakadu/led.c b/board/kakadu/led.c index 504bdf0d2f..7d05b6fd0d 100644 --- a/board/kakadu/led.c +++ b/board/kakadu/led.c @@ -16,13 +16,13 @@ const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -#define LED_OFF MT6370_LED_ID_OFF -#define LED_AMBER MT6370_LED_ID1 -#define LED_WHITE MT6370_LED_ID2 +#define LED_OFF MT6370_LED_ID_OFF +#define LED_AMBER MT6370_LED_ID1 +#define LED_WHITE MT6370_LED_ID2 -#define LED_MASK_OFF 0 -#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN -#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN +#define LED_MASK_OFF 0 +#define LED_MASK_AMBER MT6370_MASK_RGB_ISNK1DIM_EN +#define LED_MASK_WHITE MT6370_MASK_RGB_ISNK2DIM_EN static void kakadu_led_set_battery(void) { -- cgit v1.2.1 From f50cd2fd3e0eb964da7c6d06a8e4c3ae8a5b49f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:17 -0600 Subject: driver/bc12/pi3usb9201.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic5e7e5423ab293e7e0bad5599474d26d3e5a02cd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729954 Reviewed-by: Jeremy Bettis --- driver/bc12/pi3usb9201.c | 47 ++++++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 25 deletions(-) diff --git a/driver/bc12/pi3usb9201.c b/driver/bc12/pi3usb9201.c index 9e60c9b4fd..9b71eeb23c 100644 --- a/driver/bc12/pi3usb9201.c +++ b/driver/bc12/pi3usb9201.c @@ -18,7 +18,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) enum pi3usb9201_client_sts { CHG_OTHER = 0, @@ -45,21 +45,21 @@ static enum charge_supplier bc12_supplier[CONFIG_USB_PD_PORT_MAX_COUNT]; * will continue to allow those. */ static const struct bc12_status bc12_chg_limits[] = { - [CHG_OTHER] = {CHARGE_SUPPLIER_OTHER, 500}, - [CHG_2_4A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA}, - [CHG_2_0A] = {CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA}, - [CHG_1_0A] = {CHARGE_SUPPLIER_PROPRIETARY, 1000}, - [CHG_RESERVED] = {CHARGE_SUPPLIER_NONE, 0}, - [CHG_CDP] = {CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA}, - [CHG_SDP] = {CHARGE_SUPPLIER_BC12_SDP, 500}, - [CHG_DCP] = {CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA}, + [CHG_OTHER] = { CHARGE_SUPPLIER_OTHER, 500 }, + [CHG_2_4A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA }, + [CHG_2_0A] = { CHARGE_SUPPLIER_PROPRIETARY, USB_CHARGER_MAX_CURR_MA }, + [CHG_1_0A] = { CHARGE_SUPPLIER_PROPRIETARY, 1000 }, + [CHG_RESERVED] = { CHARGE_SUPPLIER_NONE, 0 }, + [CHG_CDP] = { CHARGE_SUPPLIER_BC12_CDP, USB_CHARGER_MAX_CURR_MA }, + [CHG_SDP] = { CHARGE_SUPPLIER_BC12_SDP, 500 }, + [CHG_DCP] = { CHARGE_SUPPLIER_BC12_DCP, USB_CHARGER_MAX_CURR_MA }, }; static inline int raw_read8(int port, int offset, int *value) { return i2c_read8(pi3usb9201_bc12_chips[port].i2c_port, - pi3usb9201_bc12_chips[port].i2c_addr_flags, - offset, value); + pi3usb9201_bc12_chips[port].i2c_addr_flags, offset, + value); } static int pi3usb9201_raw(int port, int reg, int mask, int val) @@ -73,8 +73,7 @@ static int pi3usb9201_raw(int port, int reg, int mask, int val) static int pi3usb9201_interrupt_mask(int port, int enable) { return pi3usb9201_raw(port, PI3USB9201_REG_CTRL_1, - PI3USB9201_REG_CTRL_1_INT_MASK, - enable); + PI3USB9201_REG_CTRL_1_INT_MASK, enable); } static int pi3usb9201_bc12_detect_ctrl(int port, int enable) @@ -121,7 +120,7 @@ static int pi3usb9201_get_status(int port, int *client, int *host) } static void bc12_update_supplier(enum charge_supplier supplier, int port, - struct charge_port_info *new_chg) + struct charge_port_info *new_chg) { /* * If most recent supplier type is not CHARGE_SUPPLIER_NONE, then the @@ -155,8 +154,8 @@ static void bc12_update_charge_manager(int port, int client_status) new_chg.current = bc12_chg_limits[bit_pos].current_limit; supplier = bc12_chg_limits[bit_pos].supplier; - CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d", - port, client_status, new_chg.current, supplier); + CPRINTS("pi3usb9201[p%d]: sts = 0x%x, lim = %d mA, supplier = %d", port, + client_status, new_chg.current, supplier); /* bc1.2 is complete and start bit does not auto clear */ pi3usb9201_bc12_detect_ctrl(port, 0); /* Inform charge manager of new supplier type and current limit */ @@ -281,8 +280,7 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt) if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) && (evt & USB_CHG_EVENT_VBUS)) - CPRINTS("VBUS p%d %d", port, - pd_snk_is_vbus_provided(port)); + CPRINTS("VBUS p%d %d", port, pd_snk_is_vbus_provided(port)); if (evt & USB_CHG_EVENT_DR_UFP) { bc12_power_up(port); @@ -298,8 +296,8 @@ static void pi3usb9201_usb_charger_task_event(const int port, uint32_t evt) new_chg.voltage = USB_CHARGER_VOLTAGE_MV; new_chg.current = USB_CHARGER_MIN_CURR_MA; /* Save supplier type and notify chg manager */ - bc12_update_supplier(CHARGE_SUPPLIER_OTHER, - port, &new_chg); + bc12_update_supplier(CHARGE_SUPPLIER_OTHER, port, + &new_chg); CPRINTS("pi3usb9201[p%d]: bc1.2 failed use defaults", port); } @@ -383,9 +381,8 @@ const struct bc12_drv pi3usb9201_drv = { #ifdef CONFIG_BC12_SINGLE_DRIVER /* provide a default bc12_ports[] for backward compatibility */ -struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { - [0 ... (CHARGE_PORT_COUNT - 1)] = { - .drv = &pi3usb9201_drv, - } -}; +struct bc12_config + bc12_ports[CHARGE_PORT_COUNT] = { [0 ...(CHARGE_PORT_COUNT - 1)] = { + .drv = &pi3usb9201_drv, + } }; #endif /* CONFIG_BC12_SINGLE_DRIVER */ -- cgit v1.2.1 From bfc65d5c3ecdc3047e08661c5e5ac30bcd34e50e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:43 -0600 Subject: chip/host/reboot.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieaa8dc379756eebdb1916565d37db074138f647a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729168 Reviewed-by: Jeremy Bettis --- chip/host/reboot.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/chip/host/reboot.c b/chip/host/reboot.c index e932c5f11a..dcda65f455 100644 --- a/chip/host/reboot.c +++ b/chip/host/reboot.c @@ -20,10 +20,9 @@ void emulator_reboot(void) ccprints("Emulator would reboot here. Fuzzing: doing nothing."); } #else /* !TEST_FUZZ */ -noreturn -void emulator_reboot(void) +noreturn void emulator_reboot(void) { - char *argv[] = {strdup(__get_prog_name()), NULL}; + char *argv[] = { strdup(__get_prog_name()), NULL }; emulator_flush(); execv(__get_prog_name(), argv); while (1) -- cgit v1.2.1 From bd88bcbfc0674ad814788dd9db7ecfe2d7d3e919 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:29 -0600 Subject: chip/npcx/sha256_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id00c5c1c2da52a686334bfc9150e63765c533547 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729430 Reviewed-by: Jeremy Bettis --- chip/npcx/sha256_chip.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/chip/npcx/sha256_chip.c b/chip/npcx/sha256_chip.c index 6d2d938895..0462b752ed 100644 --- a/chip/npcx/sha256_chip.c +++ b/chip/npcx/sha256_chip.c @@ -31,7 +31,7 @@ enum ncl_sha_type { * The base address of the table that holds the function pointer for each * SHA256 API in ROM. */ -#define NCL_SHA_BASE_ADDR 0x00000100UL +#define NCL_SHA_BASE_ADDR 0x00000100UL struct ncl_sha { /* Get the SHA context size required by SHA APIs. */ uint32_t (*get_context_size)(void); @@ -57,7 +57,8 @@ struct ncl_sha { enum ncl_status (*finish)(void *ctx, uint8_t *hashDigest); /* Perform a complete SHA calculation */ enum ncl_status (*calc)(void *ctx, enum ncl_sha_type type, - const uint8_t *data, uint32_t Len, uint8_t *hashDigest); + const uint8_t *data, uint32_t Len, + uint8_t *hashDigest); /* Power on/off the SHA module. */ enum ncl_status (*power)(void *ctx, uint8_t enable); /* Reset the SHA hardware and terminate any in-progress operations. */ @@ -95,9 +96,9 @@ uint8_t *SHA256_final(struct sha256_ctx *ctx) return ctx->buf; } -static void hmac_SHA256_step(uint8_t *output, uint8_t mask, - const uint8_t *key, const int key_len, - const uint8_t *data, const int data_len) +static void hmac_SHA256_step(uint8_t *output, uint8_t mask, const uint8_t *key, + const int key_len, const uint8_t *data, + const int data_len) { struct sha256_ctx hmac_ctx; uint8_t *key_pad = hmac_ctx.buf; @@ -120,7 +121,7 @@ static void hmac_SHA256_step(uint8_t *output, uint8_t mask, * hmac_SHA256_step. */ void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, - const uint8_t *message, const int message_len) + const uint8_t *message, const int message_len) { /* This code does not support key_len > block_size. */ ASSERT(key_len <= SHA256_BLOCK_SIZE); @@ -137,5 +138,5 @@ void hmac_SHA256(uint8_t *output, const uint8_t *key, const int key_len, * output = hash(o_key_pad || output) */ hmac_SHA256_step(output, 0x5c, key, key_len, output, - SHA256_DIGEST_SIZE); + SHA256_DIGEST_SIZE); } -- cgit v1.2.1 From bd25591a4a9fb581a71b3bfa0059a87ee836933d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:10 -0600 Subject: board/dingdong/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6878d2c640065bca6db854b90e48388f18bd72e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728203 Reviewed-by: Jeremy Bettis --- board/dingdong/board.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/dingdong/board.h b/board/dingdong/board.h index 64947960ba..62898d195a 100644 --- a/board/dingdong/board.h +++ b/board/dingdong/board.h @@ -39,7 +39,7 @@ #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 #define CONFIG_USB_PD_VBUS_DETECT_NONE #define CONFIG_USB_PD_LOGGING -#undef CONFIG_EVENT_LOG_SIZE +#undef CONFIG_EVENT_LOG_SIZE #define CONFIG_EVENT_LOG_SIZE 256 #define CONFIG_USB_PD_PORT_MAX_COUNT 1 #define CONFIG_USB_PD_TCPC @@ -63,7 +63,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" @@ -86,14 +86,14 @@ enum usb_strings { }; /* we are never a source : don't care about power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 1000 -#define PD_MAX_POWER_MW 1500 -#define PD_MAX_CURRENT_MA 300 -#define PD_MAX_VOLTAGE_MV 5000 +#define PD_MAX_POWER_MW 1500 +#define PD_MAX_CURRENT_MA 300 +#define PD_MAX_VOLTAGE_MV 5000 #endif /* !__ASSEMBLER__ */ @@ -101,10 +101,10 @@ enum usb_strings { #define USB_DEV_CLASS USB_CLASS_BILLBOARD /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_COUNT 0 +#define USB_IFACE_COUNT 0 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_COUNT 1 +#define USB_EP_CONTROL 0 +#define USB_EP_COUNT 1 #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From be040beff07b219194f31c699040af24ba7dffa1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:58 -0600 Subject: driver/temp_sensor/ec_adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3efe12086d811ab87d47a8c748331266e94b6113 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730115 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/ec_adc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/temp_sensor/ec_adc.c b/driver/temp_sensor/ec_adc.c index 196d191e47..6561b1a007 100644 --- a/driver/temp_sensor/ec_adc.c +++ b/driver/temp_sensor/ec_adc.c @@ -23,15 +23,15 @@ static int get_temp(int idx, int *temp_ptr) if (temp_raw == ADC_READ_ERROR) return EC_ERROR_UNKNOWN; - /* TODO : Need modification here if the result is not 10-bit */ + /* TODO : Need modification here if the result is not 10-bit */ - /* If there is no thermistor calculation function. - * 1. Add adjusting function like thermistor_ncp15wb.c - * 2. Place function here with ifdef - * 3. define it on board.h - */ + /* If there is no thermistor calculation function. + * 1. Add adjusting function like thermistor_ncp15wb.c + * 2. Place function here with ifdef + * 3. define it on board.h + */ #ifdef CONFIG_THERMISTOR_NCP15WB - *temp_ptr = ncp15wb_calculate_temp((uint16_t) temp_raw); + *temp_ptr = ncp15wb_calculate_temp((uint16_t)temp_raw); #else #error "Unknown thermistor for ec_adc" return EC_ERROR_UNKNOWN; @@ -45,7 +45,7 @@ int ec_adc_get_val(int idx, int *temp_ptr) int ret; int temp_c; - if(idx < 0 || idx >= ADC_CH_COUNT) + if (idx < 0 || idx >= ADC_CH_COUNT) return EC_ERROR_INVAL; ret = get_temp(idx, &temp_c); -- cgit v1.2.1 From 17753ff91bd218aa791c283ab34bb2d0f588bb2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:20 -0600 Subject: driver/tcpm/rt1715.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2a7b68c9d58aae8921485044715953cae8c57273 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730086 Reviewed-by: Jeremy Bettis --- driver/tcpm/rt1715.h | 83 ++++++++++++++++++++++++++-------------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/driver/tcpm/rt1715.h b/driver/tcpm/rt1715.h index dcf2aa28d4..b2d7029b92 100644 --- a/driver/tcpm/rt1715.h +++ b/driver/tcpm/rt1715.h @@ -7,78 +7,77 @@ #define __CROS_EC_USB_PD_TCPM_RT1715_H /* I2C interface */ -#define RT1715_I2C_ADDR_FLAGS 0x4E +#define RT1715_I2C_ADDR_FLAGS 0x4E -#define RT1715_VENDOR_ID 0x29CF +#define RT1715_VENDOR_ID 0x29CF -#define RT1715_REG_VENDOR_7 0xA0 -#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0) +#define RT1715_REG_VENDOR_7 0xA0 +#define RT1715_REG_VENDOR_7_SOFT_RESET BIT(0) -#define RT1715_REG_PHY_CTRL1 0x80 +#define RT1715_REG_PHY_CTRL1 0x80 /* Wait for tReceive before retrying transmit in response to a bad GoodCRC */ -#define RT1715_REG_PHY_CTRL1_ENRETRY BIT(7) +#define RT1715_REG_PHY_CTRL1_ENRETRY BIT(7) /* * Bit 6:4 : Consider CC to be idle if there are 7 or fewer BMC * transients observed in <46.67us> */ -#define RT1715_REG_PHY_CTRL1_TRANSCNT_7 0x70 +#define RT1715_REG_PHY_CTRL1_TRANSCNT_7 0x70 /* * Bit 1:0 : RX filter to make sure the stable received PD message. * default value is 01b * The debounce time is (register value + 2) * 41.67ns */ -#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS 0x01 -#define RT1715_REG_PHY_CTRL2 0x81 +#define RT1715_REG_PHY_CTRL1_TRXFILTER_125NS 0x01 +#define RT1715_REG_PHY_CTRL2 0x81 /* * Decrease the time that the PHY will wait for a second transition to detect * a BMC-encoded 1 bit from 2.67 us to 2.25 us. * Timeout = register value * .04167 us. */ -#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US 54 -#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US 60 -#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US 62 +#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_25US 54 +#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_5US 60 +#define RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US 62 -#define RT1715_REG_PWR 0x90 -#define RT1715_REG_PWR_BMCIO_LPEN BIT(3) -#define RT1715_REG_PWR_VBUS_DETEN BIT(1) -#define RT1715_REG_PWR_BMCIO_OSCEN BIT(0) +#define RT1715_REG_PWR 0x90 +#define RT1715_REG_PWR_BMCIO_LPEN BIT(3) +#define RT1715_REG_PWR_VBUS_DETEN BIT(1) +#define RT1715_REG_PWR_BMCIO_OSCEN BIT(0) -#define RT1715_REG_BMCIO_RXDZSEL 0x93 -#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA BIT(7) -#define RT1715_REG_BMCIO_RXDZSEL_SEL BIT(0) +#define RT1715_REG_BMCIO_RXDZSEL 0x93 +#define RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA BIT(7) +#define RT1715_REG_BMCIO_RXDZSEL_SEL BIT(0) -#define RT1715_REG_RT_INT 0x98 -#define RT1715_REG_RT_INT_WAKEUP BIT(0) +#define RT1715_REG_RT_INT 0x98 +#define RT1715_REG_RT_INT_WAKEUP BIT(0) -#define RT1715_REG_RT_MASK 0x99 -#define RT1715_REG_RT_MASK_M_WAKEUP BIT(0) +#define RT1715_REG_RT_MASK 0x99 +#define RT1715_REG_RT_MASK_M_WAKEUP BIT(0) -#define RT1715_REG_VENDOR_5 0x9B -#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF BIT(5) -#define RT1715_REG_VENDOR_5_ENEXTMSG BIT(4) -#define RT1715_REG_VENDOR_5_AUTOIDLE_EN BIT(3) +#define RT1715_REG_VENDOR_5 0x9B +#define RT1715_REG_VENDOR_5_SHUTDOWN_OFF BIT(5) +#define RT1715_REG_VENDOR_5_ENEXTMSG BIT(4) +#define RT1715_REG_VENDOR_5_AUTOIDLE_EN BIT(3) -#define RT1715_REG_I2CRST_CTRL 0x9E +#define RT1715_REG_I2CRST_CTRL 0x9E /* I2C reset : (val + 1) * 12.5ms */ -#define RT1715_REG_I2CRST_CTRL_TOUT_200MS 0x0F -#define RT1715_REG_I2CRST_CTRL_TOUT_150MS 0x0B -#define RT1715_REG_I2CRST_CTRL_TOUT_100MS 0x07 -#define RT1715_REG_I2CRST_CTRL_EN BIT(7) +#define RT1715_REG_I2CRST_CTRL_TOUT_200MS 0x0F +#define RT1715_REG_I2CRST_CTRL_TOUT_150MS 0x0B +#define RT1715_REG_I2CRST_CTRL_TOUT_100MS 0x07 +#define RT1715_REG_I2CRST_CTRL_EN BIT(7) +#define RT1715_REG_TTCPC_FILTER 0xA1 +#define RT1715_REG_TTCPC_FILTER_400US 0x0F -#define RT1715_REG_TTCPC_FILTER 0xA1 -#define RT1715_REG_TTCPC_FILTER_400US 0x0F - -#define RT1715_REG_DRP_TOGGLE_CYCLE 0xA2 +#define RT1715_REG_DRP_TOGGLE_CYCLE 0xA2 /* DRP Duty : (51.2 + 6.4 * val) ms */ -#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS 0x04 +#define RT1715_REG_DRP_TOGGLE_CYCLE_76MS 0x04 -#define RT1715_REG_DRP_DUTY_CTRL 0xA3 -#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT 400 +#define RT1715_REG_DRP_DUTY_CTRL 0xA3 +#define RT1715_REG_DRP_DUTY_CTRL_40PERCENT 400 -#define RT1715_REG_BMCIO_RXDZEN 0xAF -#define RT1715_REG_BMCIO_RXDZEN_ENABLE 0x01 -#define RT1715_REG_BMCIO_RXDZEN_DISABLE 0x00 +#define RT1715_REG_BMCIO_RXDZEN 0xAF +#define RT1715_REG_BMCIO_RXDZEN_ENABLE 0x01 +#define RT1715_REG_BMCIO_RXDZEN_DISABLE 0x00 extern const struct tcpm_drv rt1715_tcpm_drv; -- cgit v1.2.1 From 0a8039c9174e603a580bfcace8630f1ab275c0cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:12 -0600 Subject: board/sasuke/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie7ae0a215053f710acb98e2a1f930e41a1d910fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728907 Reviewed-by: Jeremy Bettis --- board/sasuke/cbi_ssfc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sasuke/cbi_ssfc.c b/board/sasuke/cbi_ssfc.c index 61db1ef4f6..97812a1b1c 100644 --- a/board/sasuke/cbi_ssfc.c +++ b/board/sasuke/cbi_ssfc.c @@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } enum ec_ssfc_usb_ss_mux get_cbi_ssfc_usb_ss_mux(void) { - return (enum ec_ssfc_usb_ss_mux) cached_ssfc.usb_ss_mux; + return (enum ec_ssfc_usb_ss_mux)cached_ssfc.usb_ss_mux; } -- cgit v1.2.1 From 6507c9ca0ceb22dacecce8c75b77201058b1b231 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:22 -0600 Subject: driver/ioexpander/ccgxxf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I706207cb7fe5944e4106a0adf4c67f4d851ba9b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729990 Reviewed-by: Jeremy Bettis --- driver/ioexpander/ccgxxf.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/driver/ioexpander/ccgxxf.c b/driver/ioexpander/ccgxxf.c index 08dd17c863..d4dfbf4da3 100644 --- a/driver/ioexpander/ccgxxf.c +++ b/driver/ioexpander/ccgxxf.c @@ -12,25 +12,25 @@ /* Add after all include files */ #include "ccgxxf.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) static inline int ccgxxf_read8(int ioex, int reg, int *data) { return i2c_read8(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, data); + ioex_config[ioex].i2c_addr_flags, reg, data); } static inline int ccgxxf_update8(int ioex, int reg, uint8_t mask, - enum mask_update_action action) + enum mask_update_action action) { return i2c_update8(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, mask, action); + ioex_config[ioex].i2c_addr_flags, reg, mask, action); } static inline int ccgxxf_write16(int ioex, uint16_t reg, uint16_t data) { return i2c_write16(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, data); + ioex_config[ioex].i2c_addr_flags, reg, data); } static int ccgxxf_get_level(int ioex, int port, int mask, int *val) @@ -64,9 +64,9 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags) /* Push-pull output can't be configured for 1.8V level */ if ((flags & GPIO_OUTPUT) && (flags & GPIO_SEL_1P8V) && - !(flags & GPIO_OPEN_DRAIN)) { + !(flags & GPIO_OPEN_DRAIN)) { CPRINTS("Invalid flags: ioex=%d, port=%d, mask=%d, flags=0x%x", - ioex, port, mask, flags); + ioex, port, mask, flags); return EC_ERROR_INVAL; } @@ -99,7 +99,7 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags) } pin_mode = port | (pin_mode << CCGXXF_GPIO_PIN_MODE_SHIFT) | - (mask << CCGXXF_GPIO_PIN_MASK_SHIFT); + (mask << CCGXXF_GPIO_PIN_MASK_SHIFT); /* Note: once set the 1.8V level affect whole GPIO port */ if (flags & GPIO_SEL_1P8V) @@ -111,17 +111,17 @@ static int ccgxxf_set_flags_by_mask(int ioex, int port, int mask, int flags) */ if (flags & (GPIO_HIGH | GPIO_LOW)) { rv = ccgxxf_set_level(ioex, port, mask, - flags & GPIO_HIGH ? 1 : 0); + flags & GPIO_HIGH ? 1 : 0); if (rv) return rv; } - return ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode); + return ccgxxf_write16(ioex, CCGXXF_REG_GPIO_MODE, pin_mode); } static int ccgxxf_get_flags_by_mask(int ioex, int port, int mask, int *flags) { - /* TODO: Add it after implementing in the CCGXXF firmware. */ + /* TODO: Add it after implementing in the CCGXXF firmware. */ return EC_SUCCESS; } @@ -131,7 +131,6 @@ static int ccgxxf_enable_interrupt(int ioex, int port, int mask, int enable) return EC_ERROR_UNIMPLEMENTED; } - #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT static int ccgxxf_get_port(int ioex, int port, int *val) { @@ -146,13 +145,13 @@ int ccgxxf_init(int ioex) } const struct ioexpander_drv ccgxxf_ioexpander_drv = { - .init = &ccgxxf_init, - .get_level = &ccgxxf_get_level, - .set_level = &ccgxxf_set_level, - .get_flags_by_mask = &ccgxxf_get_flags_by_mask, - .set_flags_by_mask = &ccgxxf_set_flags_by_mask, - .enable_interrupt = &ccgxxf_enable_interrupt, + .init = &ccgxxf_init, + .get_level = &ccgxxf_get_level, + .set_level = &ccgxxf_set_level, + .get_flags_by_mask = &ccgxxf_get_flags_by_mask, + .set_flags_by_mask = &ccgxxf_set_flags_by_mask, + .enable_interrupt = &ccgxxf_enable_interrupt, #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT - .get_port = &ccgxxf_get_port, + .get_port = &ccgxxf_get_port, #endif }; -- cgit v1.2.1 From dc3e9008b8b1d84e85d90bed5e86366b6c46a245 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:56 -0600 Subject: board/hatch_fp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=util/compare_build.sh -b hatch_fp Change-Id: Ia889f5ae5b1c51c348905fb96807e6b29e2f7cf2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728299 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes --- board/hatch_fp/board.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h index 290e0f80e6..2702152576 100644 --- a/board/hatch_fp/board.h +++ b/board/hatch_fp/board.h @@ -59,28 +59,28 @@ #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (128 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */ -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * We want to prevent flash readout, and use it as indicator of protection @@ -189,7 +189,7 @@ /* SPI configuration for the fingerprint sensor */ #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */ +#define CONFIG_SPI_FP_PORT 0 /* SPI2: first master config */ #define CONFIG_FINGERPRINT_MCU #ifdef SECTION_IS_RW #define CONFIG_FP_SENSOR_FPC1025 -- cgit v1.2.1 From 5c3ae648a00e085b685e10f27feb3da2aef105f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:56 -0600 Subject: common/timer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I335a82435cd3001f24d5eef7e209baf97b3d5016 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729756 Reviewed-by: Jeremy Bettis --- common/timer.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/common/timer.c b/common/timer.c index a8d02e7ece..a33eb84be4 100644 --- a/common/timer.c +++ b/common/timer.c @@ -19,19 +19,19 @@ #ifdef CONFIG_ZEPHYR #include /* For k_usleep() */ #else -extern __error("k_usleep() should only be called from Zephyr code") -int32_t k_usleep(int32_t); +extern __error("k_usleep() should only be called from Zephyr code") int32_t + k_usleep(int32_t); #endif /* CONFIG_ZEPHYR */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) #endif -#define TIMER_SYSJUMP_TAG 0x4d54 /* "TM" */ +#define TIMER_SYSJUMP_TAG 0x4d54 /* "TM" */ /* High 32-bits of the 64-bit timestamp counter. */ STATIC_IF_NOT(CONFIG_HWTIMER_64BIT) volatile uint32_t clksrc_high; @@ -82,7 +82,6 @@ void process_timers(int overflow) /* read atomically the current state of timer running */ check_timer = running_t0 = timer_running; while (check_timer) { - int tskid = __fls(check_timer); /* timer has expired ? */ if (timer_deadline[tskid].val <= now.val) @@ -95,7 +94,7 @@ void process_timers(int overflow) check_timer &= ~BIT(tskid); } - /* if there is a new timer, let's retry */ + /* if there is a new timer, let's retry */ } while (timer_running & ~running_t0); if (next.le.hi == 0xffffffff) { @@ -203,7 +202,7 @@ void usleep(unsigned us) do { evt |= task_wait_event(us); } while (!(evt & TASK_EVENT_TIMER) && - ((__hw_clock_source_read() - t0) < us)); + ((__hw_clock_source_read() - t0) < us)); /* Re-queue other events which happened in the meanwhile */ if (evt) @@ -246,7 +245,7 @@ timestamp_t get_time(void) clock_t clock(void) { /* __hw_clock_source_read() returns a microsecond resolution timer.*/ - return (clock_t) __hw_clock_source_read() / 1000; + return (clock_t)__hw_clock_source_read() / 1000; } void force_time(timestamp_t ts) @@ -299,8 +298,7 @@ void __hw_clock_source_set(uint32_t ts) void timer_print_info(void) { timestamp_t t = get_time(); - uint64_t deadline = (uint64_t)t.le.hi << 32 | - __hw_clock_event_get(); + uint64_t deadline = (uint64_t)t.le.hi << 32 | __hw_clock_event_get(); int tskid; ccprintf("Time: 0x%016llx us, %11.6lld s\n" @@ -384,8 +382,7 @@ static int command_wait(int argc, char **argv) return EC_SUCCESS; } /* Typically a large delay (e.g. 3s) will cause a reset */ -DECLARE_CONSOLE_COMMAND(waitms, command_wait, - "msec", +DECLARE_CONSOLE_COMMAND(waitms, command_wait, "msec", "Busy-wait for msec (large delays will reset)"); #endif @@ -416,8 +413,7 @@ static int command_force_time(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(forcetime, command_force_time, - "hi lo", +DECLARE_CONSOLE_COMMAND(forcetime, command_force_time, "hi lo", "Force current time"); #endif @@ -429,8 +425,7 @@ static int command_get_time(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(gettime, command_get_time, NULL, "Print current time"); #endif @@ -441,7 +436,6 @@ static int command_timer_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(timerinfo, command_timer_info, NULL, "Print timer info"); #endif -- cgit v1.2.1 From 5f1dfff2985d15d201fb9dfdaa9055cda22f2715 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:26 -0600 Subject: zephyr/include/dt-bindings/usb_pd_tcpm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I816bcf418c8143b378eec8246d3e0f107e9143a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730716 Reviewed-by: Jeremy Bettis --- zephyr/include/dt-bindings/usb_pd_tcpm.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/zephyr/include/dt-bindings/usb_pd_tcpm.h b/zephyr/include/dt-bindings/usb_pd_tcpm.h index 2b0902d097..6a5d0beb89 100644 --- a/zephyr/include/dt-bindings/usb_pd_tcpm.h +++ b/zephyr/include/dt-bindings/usb_pd_tcpm.h @@ -24,14 +24,14 @@ * Bit 7 --> TCPC controls FRS (even when CONFIG_USB_PD_FRS_TCPC is off) * Bit 8 --> TCPC enable VBUS monitoring */ -#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) -#define TCPC_FLAGS_ALERT_OD BIT(1) -#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) -#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) -#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) -#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) -#define TCPC_FLAGS_CONTROL_VCONN BIT(6) -#define TCPC_FLAGS_CONTROL_FRS BIT(7) -#define TCPC_FLAGS_VBUS_MONITOR BIT(8) +#define TCPC_FLAGS_ALERT_ACTIVE_HIGH BIT(0) +#define TCPC_FLAGS_ALERT_OD BIT(1) +#define TCPC_FLAGS_RESET_ACTIVE_HIGH BIT(2) +#define TCPC_FLAGS_TCPCI_REV2_0 BIT(3) +#define TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V BIT(4) +#define TCPC_FLAGS_NO_DEBUG_ACC_CONTROL BIT(5) +#define TCPC_FLAGS_CONTROL_VCONN BIT(6) +#define TCPC_FLAGS_CONTROL_FRS BIT(7) +#define TCPC_FLAGS_VBUS_MONITOR BIT(8) #endif -- cgit v1.2.1 From 7eaf01e8ac47d7d6a6e490d3060022bedb693615 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:48 -0600 Subject: board/banshee/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1511050a869ac5f441acbe2c59af35bb403585bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728022 Reviewed-by: Jeremy Bettis --- board/banshee/keyboard.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/board/banshee/keyboard.c b/board/banshee/keyboard.c index 3891955b46..ce1fcacf4c 100644 --- a/board/banshee/keyboard.c +++ b/board/banshee/keyboard.c @@ -63,8 +63,8 @@ static const struct ec_response_keybd_config banshee_kb_id2 = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_board_id() <= 1) return &banshee_kb_id1; @@ -81,20 +81,20 @@ __override const struct key { uint8_t row; uint8_t col; } vivaldi_keys[] = { - {.row = 3, .col = 5}, /* T1 */ - {.row = 2, .col = 5}, /* T2 */ - {.row = 6, .col = 4}, /* T3 */ - {.row = 3, .col = 4}, /* T4 */ - {.row = 4, .col = 10}, /* T5 */ - {.row = 3, .col = 10}, /* T6 */ - {.row = 2, .col = 10}, /* T7 */ - {.row = 1, .col = 15}, /* T8 */ - {.row = 3, .col = 11}, /* T9 */ - {.row = 4, .col = 8}, /* T10 */ - {.row = 6, .col = 8}, /* T11 */ - {.row = 3, .col = 13}, /* T12 */ - {.row = 3, .col = 5}, /* T13 */ - {.row = 0, .col = 9}, /* T14 */ - {.row = 0, .col = 11}, /* T15 */ + { .row = 3, .col = 5 }, /* T1 */ + { .row = 2, .col = 5 }, /* T2 */ + { .row = 6, .col = 4 }, /* T3 */ + { .row = 3, .col = 4 }, /* T4 */ + { .row = 4, .col = 10 }, /* T5 */ + { .row = 3, .col = 10 }, /* T6 */ + { .row = 2, .col = 10 }, /* T7 */ + { .row = 1, .col = 15 }, /* T8 */ + { .row = 3, .col = 11 }, /* T9 */ + { .row = 4, .col = 8 }, /* T10 */ + { .row = 6, .col = 8 }, /* T11 */ + { .row = 3, .col = 13 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 0, .col = 9 }, /* T14 */ + { .row = 0, .col = 11 }, /* T15 */ }; BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); -- cgit v1.2.1 From 0a3c2174b0b6e0c2c5798546ee5137c20bcfacdc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:34 -0600 Subject: common/usbc/usb_tc_drp_acc_trysrc_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I48831bf74faac3917ad967071fbfa43605579a31 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729796 Reviewed-by: Jeremy Bettis --- common/usbc/usb_tc_drp_acc_trysrc_sm.c | 374 ++++++++++++++++----------------- 1 file changed, 185 insertions(+), 189 deletions(-) diff --git a/common/usbc/usb_tc_drp_acc_trysrc_sm.c b/common/usbc/usb_tc_drp_acc_trysrc_sm.c index 2da6b59f0a..8a6a666da0 100644 --- a/common/usbc/usb_tc_drp_acc_trysrc_sm.c +++ b/common/usbc/usb_tc_drp_acc_trysrc_sm.c @@ -32,30 +32,30 @@ * See Figure 4-16 in Release 1.4 of USB Type-C Spec. */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) #endif -#define CPRINTF_LX(x, format, args...) \ - do { \ - if (tc_debug_level >= x) \ - CPRINTF(format, ## args); \ +#define CPRINTF_LX(x, format, args...) \ + do { \ + if (tc_debug_level >= x) \ + CPRINTF(format, ##args); \ } while (0) -#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args) -#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args) -#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args) - -#define CPRINTS_LX(x, format, args...) \ - do { \ - if (tc_debug_level >= x) \ - CPRINTS(format, ## args); \ +#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args) +#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args) +#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args) + +#define CPRINTS_LX(x, format, args...) \ + do { \ + if (tc_debug_level >= x) \ + CPRINTS(format, ##args); \ } while (0) -#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args) -#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args) -#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args) +#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args) +#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args) +#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args) /* * Define DEBUG_PRINT_FLAG_AND_EVENT_NAMES to print flag names when set and @@ -83,57 +83,58 @@ void print_flag(int port, int set_or_clear, int flag); /* Type-C Layer Flags */ /* Flag to note we are sourcing VCONN */ -#define TC_FLAGS_VCONN_ON BIT(0) +#define TC_FLAGS_VCONN_ON BIT(0) /* Flag to note port partner has Rp/Rp or Rd/Rd */ -#define TC_FLAGS_TS_DTS_PARTNER BIT(1) +#define TC_FLAGS_TS_DTS_PARTNER BIT(1) /* Flag to note VBus input has never been low */ -#define TC_FLAGS_VBUS_NEVER_LOW BIT(2) +#define TC_FLAGS_VBUS_NEVER_LOW BIT(2) /* Flag to note Low Power Mode transition is currently happening */ -#define TC_FLAGS_LPM_TRANSITION BIT(3) +#define TC_FLAGS_LPM_TRANSITION BIT(3) /* Flag to note Low Power Mode is currently on */ -#define TC_FLAGS_LPM_ENGAGED BIT(4) +#define TC_FLAGS_LPM_ENGAGED BIT(4) /* Flag to note CVTPD has been detected */ -#define TC_FLAGS_CTVPD_DETECTED BIT(5) +#define TC_FLAGS_CTVPD_DETECTED BIT(5) /* Flag to note request to swap to VCONN on */ -#define TC_FLAGS_REQUEST_VC_SWAP_ON BIT(6) +#define TC_FLAGS_REQUEST_VC_SWAP_ON BIT(6) /* Flag to note request to swap to VCONN off */ -#define TC_FLAGS_REQUEST_VC_SWAP_OFF BIT(7) +#define TC_FLAGS_REQUEST_VC_SWAP_OFF BIT(7) /* Flag to note request to swap VCONN is being rejected */ -#define TC_FLAGS_REJECT_VCONN_SWAP BIT(8) +#define TC_FLAGS_REJECT_VCONN_SWAP BIT(8) /* Flag to note request to power role swap */ -#define TC_FLAGS_REQUEST_PR_SWAP BIT(9) +#define TC_FLAGS_REQUEST_PR_SWAP BIT(9) /* Flag to note request to data role swap */ -#define TC_FLAGS_REQUEST_DR_SWAP BIT(10) +#define TC_FLAGS_REQUEST_DR_SWAP BIT(10) /* Flag to note request to power off sink */ -#define TC_FLAGS_POWER_OFF_SNK BIT(11) +#define TC_FLAGS_POWER_OFF_SNK BIT(11) /* Flag to note port partner is Power Delivery capable */ -#define TC_FLAGS_PARTNER_PD_CAPABLE BIT(12) +#define TC_FLAGS_PARTNER_PD_CAPABLE BIT(12) /* Flag to note hard reset has been requested */ -#define TC_FLAGS_HARD_RESET_REQUESTED BIT(13) +#define TC_FLAGS_HARD_RESET_REQUESTED BIT(13) /* Flag to note we are currently performing PR Swap */ -#define TC_FLAGS_PR_SWAP_IN_PROGRESS BIT(14) +#define TC_FLAGS_PR_SWAP_IN_PROGRESS BIT(14) /* Flag to note we should check for connection */ -#define TC_FLAGS_CHECK_CONNECTION BIT(15) +#define TC_FLAGS_CHECK_CONNECTION BIT(15) /* Flag to note request from pd_set_suspend to enter TC_DISABLED state */ -#define TC_FLAGS_REQUEST_SUSPEND BIT(16) +#define TC_FLAGS_REQUEST_SUSPEND BIT(16) /* Flag to note we are in TC_DISABLED state */ -#define TC_FLAGS_SUSPENDED BIT(17) +#define TC_FLAGS_SUSPENDED BIT(17) /* Flag to indicate the port current limit has changed */ -#define TC_FLAGS_UPDATE_CURRENT BIT(18) +#define TC_FLAGS_UPDATE_CURRENT BIT(18) /* Flag to indicate USB mux should be updated */ -#define TC_FLAGS_UPDATE_USB_MUX BIT(19) +#define TC_FLAGS_UPDATE_USB_MUX BIT(19) /* Flag for retimer firmware update */ -#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN BIT(20) +#define TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN BIT(20) #define TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN BIT(21) /* Flag for asynchronous call to request Error Recovery */ -#define TC_FLAGS_REQUEST_ERROR_RECOVERY BIT(22) +#define TC_FLAGS_REQUEST_ERROR_RECOVERY BIT(22) /* For checking flag_bit_names[] array */ -#define TC_FLAGS_COUNT 23 +#define TC_FLAGS_COUNT 23 /* On disconnect, clear most of the flags. */ -#define CLR_FLAGS_ON_DISCONNECT(port) TC_CLR_FLAG(port, \ - ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | TC_FLAGS_SUSPENDED)) +#define CLR_FLAGS_ON_DISCONNECT(port) \ + TC_CLR_FLAG(port, ~(TC_FLAGS_LPM_ENGAGED | TC_FLAGS_REQUEST_SUSPEND | \ + TC_FLAGS_SUSPENDED)) /* * 10 ms is enough time for any TCPC transaction to complete @@ -166,14 +167,14 @@ void print_flag(int port, int set_or_clear, int flag); * The TypeC state machine uses this bit to disable/enable PD * This bit corresponds to bit-0 of pd_disabled_mask */ -#define PD_DISABLED_NO_CONNECTION BIT(0) +#define PD_DISABLED_NO_CONNECTION BIT(0) /* * Console and Host commands use this bit to override the * PD_DISABLED_NO_CONNECTION bit that was set by the TypeC * state machine. * This bit corresponds to bit-1 of pd_disabled_mask */ -#define PD_DISABLED_BY_POLICY BIT(1) +#define PD_DISABLED_BY_POLICY BIT(1) /* Unreachable time in future */ #define TIMER_DISABLED 0xffffffffffffffff @@ -250,9 +251,8 @@ extern int _GPIO_CCD_MODE_ODL; * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0 * then the DEBUG LABELS will be removed from the build. */ -#if defined(CONFIG_COMMON_RUNTIME) && \ - (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \ - (CONFIG_USB_PD_DEBUG_LEVEL > 0)) +#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \ + (CONFIG_USB_PD_DEBUG_LEVEL > 0)) #define USB_PD_DEBUG_LABELS #endif @@ -268,9 +268,8 @@ extern int _GPIO_CCD_MODE_ODL; */ #define IS_ATTACHED_SNK(port) (get_state_tc(port) == TC_ATTACHED_SNK) - /* List of human readable state names for console debugging */ -__maybe_unused static __const_data const char * const tc_state_names[] = { +__maybe_unused static __const_data const char *const tc_state_names[] = { #ifdef USB_PD_DEBUG_LABELS [TC_DISABLED] = "Disabled", [TC_ERROR_RECOVERY] = "ErrorRecovery", @@ -289,7 +288,7 @@ __maybe_unused static __const_data const char * const tc_state_names[] = { [TC_LOW_POWER_MODE] = "LowPowerMode", #endif #ifdef CONFIG_USB_PE_SM - [TC_CT_UNATTACHED_SNK] = "CTUnattached.SNK", + [TC_CT_UNATTACHED_SNK] = "CTUnattached.SNK", [TC_CT_ATTACHED_SNK] = "CTAttached.SNK", #endif /* Super States */ @@ -310,8 +309,8 @@ static enum debug_level tc_debug_level = DEBUG_LEVEL_1; #ifdef DEBUG_PRINT_FLAG_AND_EVENT_NAMES struct bit_name { - int value; - const char *name; + int value; + const char *name; }; static struct bit_name flag_bit_names[] = { @@ -335,11 +334,10 @@ static struct bit_name flag_bit_names[] = { { TC_FLAGS_SUSPENDED, "SUSPENDED" }, { TC_FLAGS_UPDATE_CURRENT, "UPDATE_CURRENT" }, { TC_FLAGS_UPDATE_USB_MUX, "UPDATE_USB_MUX" }, - { TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN, - "USB_RETIMER_FW_UPDATE_RUN" }, + { TC_FLAGS_USB_RETIMER_FW_UPDATE_RUN, "USB_RETIMER_FW_UPDATE_RUN" }, { TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN, - "USB_RETIMER_FW_UPDATE_LTD_RUN" }, - { TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY"}, + "USB_RETIMER_FW_UPDATE_LTD_RUN" }, + { TC_FLAGS_REQUEST_ERROR_RECOVERY, "REQUEST_ERROR_RECOCVERY" }, }; BUILD_ASSERT(ARRAY_SIZE(flag_bit_names) == TC_FLAGS_COUNT); @@ -394,8 +392,8 @@ void print_flag(int port, int set_or_clear, int flag) #ifndef CONFIG_USB_PD_TRY_SRC extern int TC_TRY_SRC_UNDEFINED; extern int TC_TRY_WAIT_SNK_UNDEFINED; -#define TC_TRY_SRC TC_TRY_SRC_UNDEFINED -#define TC_TRY_WAIT_SNK TC_TRY_WAIT_SNK_UNDEFINED +#define TC_TRY_SRC TC_TRY_SRC_UNDEFINED +#define TC_TRY_WAIT_SNK TC_TRY_WAIT_SNK_UNDEFINED #endif static struct type_c { @@ -444,10 +442,11 @@ static struct type_c { } tc[CONFIG_USB_PD_PORT_MAX_COUNT]; /* Port dual-role state */ -static volatile __maybe_unused -enum pd_dual_role_states drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [0 ... (CONFIG_USB_PD_PORT_MAX_COUNT - 1)] = - CONFIG_USB_PD_INITIAL_DRP_STATE}; +static volatile __maybe_unused enum pd_dual_role_states + drp_state[CONFIG_USB_PD_PORT_MAX_COUNT] = { + [0 ...(CONFIG_USB_PD_PORT_MAX_COUNT - 1)] = + CONFIG_USB_PD_INITIAL_DRP_STATE + }; static void set_vconn(int port, int enable); @@ -516,7 +515,7 @@ __overridable void pd_set_vbus_discharge(int port, int enable) /* * These pd_ functions are implemented in the PE layer */ -const uint32_t * const pd_get_src_caps(int port) +const uint32_t *const pd_get_src_caps(int port) { return NULL; } @@ -526,7 +525,7 @@ uint8_t pd_get_src_cap_cnt(int port) return 0; } -const uint32_t * const pd_get_snk_caps(int port) +const uint32_t *const pd_get_snk_caps(int port) { return NULL; } @@ -718,7 +717,7 @@ __maybe_unused static void tc_enable_try_src(int en) static void tc_set_modes_exit(int port) { if (IS_ENABLED(CONFIG_USB_PE_SM) && - IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) { + IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) { pd_dfp_exit_mode(port, TCPCI_MSG_SOP, 0, 0); pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, 0, 0); pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME_PRIME, 0, 0); @@ -738,12 +737,13 @@ static void tc_detached(int port) /* Clear any mux connection on detach */ if (IS_ENABLED(CONFIG_USBC_SS_MUX)) - usb_mux_set(port, USB_PD_MUX_NONE, - USB_SWITCH_DISCONNECT, tc[port].polarity); + usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, + tc[port].polarity); } static inline void pd_set_dual_role_and_event(int port, - enum pd_dual_role_states state, uint32_t event) + enum pd_dual_role_states state, + uint32_t event) { drp_state[port] = state; @@ -1072,8 +1072,8 @@ static void tc_set_partner_role(int port, enum ppc_device_role role, * to run. So build in 1ms delays, for up to 300ms, to wait for * the suspend to actually happen. */ -#define SUSPEND_SLEEP_DELAY 1 -#define SUSPEND_SLEEP_RETRIES 300 +#define SUSPEND_SLEEP_DELAY 1 +#define SUSPEND_SLEEP_RETRIES 300 void pd_set_suspend(int port, int suspend) { @@ -1098,8 +1098,8 @@ void pd_set_suspend(int port, int suspend) /* Sleep this task if we are not suspended */ while (pd_is_port_enabled(port)) { if (++wait > SUSPEND_SLEEP_RETRIES) { - CPRINTS("C%d: NOT SUSPENDED after %dms", - port, wait * SUSPEND_SLEEP_DELAY); + CPRINTS("C%d: NOT SUSPENDED after %dms", port, + wait * SUSPEND_SLEEP_DELAY); return; } msleep(SUSPEND_SLEEP_DELAY); @@ -1177,8 +1177,8 @@ int pd_is_connected(int port) { return (IS_ATTACHED_SRC(port) || (IS_ENABLED(CONFIG_USB_PE_SM) && - ((get_state_tc(port) == TC_CT_UNATTACHED_SNK) || - (get_state_tc(port) == TC_CT_ATTACHED_SNK))) || + ((get_state_tc(port) == TC_CT_UNATTACHED_SNK) || + (get_state_tc(port) == TC_CT_ATTACHED_SNK))) || IS_ATTACHED_SNK(port)); } @@ -1235,7 +1235,7 @@ bool pd_get_partner_unconstr_power(int port) } static void bc12_role_change_handler(int port, enum pd_data_role prev_data_role, - enum pd_data_role data_role) + enum pd_data_role data_role) { int event = 0; bool role_changed = (data_role != prev_data_role); @@ -1290,8 +1290,7 @@ void typec_select_src_collision_rp(int port, enum tcpc_rp_value rp) static enum tcpc_rp_value typec_get_active_select_rp(int port) { /* Explicit contract will use the collision Rp */ - if (IS_ENABLED(CONFIG_USB_PD_REV30) && - pe_is_explicit_contract(port)) + if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_is_explicit_contract(port)) return tc[port].select_collision_rp; return tc[port].select_current_limit_rp; } @@ -1412,7 +1411,7 @@ static bool tc_perform_snk_hard_reset(int port) tc[port].ps_reset_state = PS_STATE2; pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SRC_RECOVER_MAX + - PD_T_SRC_TURN_ON); + PD_T_SRC_TURN_ON); } if (pd_timer_is_expired(port, TC_TIMER_TIMEOUT)) { @@ -1423,7 +1422,7 @@ static bool tc_perform_snk_hard_reset(int port) tc[port].ps_reset_state = PS_STATE2; pd_timer_enable(port, TC_TIMER_TIMEOUT, PD_T_SRC_RECOVER_MAX + - PD_T_SRC_TURN_ON); + PD_T_SRC_TURN_ON); } return false; case PS_STATE2: @@ -1497,8 +1496,8 @@ static void restart_tc_sm(int port, enum usb_tc_state start_state) * Update the Rp Value. We don't need to update CC lines though as that * happens in below set_state transition. */ - typec_select_src_current_limit_rp(port, - typec_get_default_current_limit_rp(port)); + typec_select_src_current_limit_rp( + port, typec_get_default_current_limit_rp(port)); /* Disable if restart failed, otherwise start in default state. */ set_state_tc(port, res ? TC_DISABLED : start_state); @@ -1567,7 +1566,6 @@ void tc_state_init(int port) return; } - /* Allow system to set try src enable */ if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) tc_try_src_override(TRY_SRC_NO_OVERRIDE); @@ -1582,11 +1580,13 @@ void tc_state_init(int port) if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) pd_set_dual_role_and_event(port, PD_DRP_FORCE_SINK, 0); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(), 0); + pd_set_dual_role_and_event(port, pd_get_drp_state_in_suspend(), + 0); else /* CHIPSET_STATE_ON */ pd_set_dual_role_and_event(port, pd_get_drp_state_in_s0(), 0); #else - pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port), 0); + pd_set_dual_role_and_event(port, board_tc_get_initial_drp_mode(port), + 0); #endif /* @@ -1771,8 +1771,7 @@ void tc_event_check(int port, int evt) * Notify all ports of sysjump */ if (evt & PD_EVENT_SYSJUMP) { - for (i = 0; i < - CONFIG_USB_PD_PORT_MAX_COUNT; i++) + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) dpm_set_mode_exit_request(i); notify_sysjump_ready(); } @@ -1834,8 +1833,8 @@ static void sink_stop_drawing_current(int port) if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) { typec_set_input_current_limit(port, 0, 0); - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, CHARGE_CEIL_NONE); + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, + CHARGE_CEIL_NONE); } } @@ -1861,9 +1860,9 @@ static void set_vconn(int port, int enable) static void pd_update_dual_role_config(int port) { if (tc[port].power_role == PD_ROLE_SOURCE && - (drp_state[port] == PD_DRP_FORCE_SINK || - (drp_state[port] == PD_DRP_TOGGLE_OFF && - get_state_tc(port) == TC_UNATTACHED_SRC))) { + (drp_state[port] == PD_DRP_FORCE_SINK || + (drp_state[port] == PD_DRP_TOGGLE_OFF && + get_state_tc(port) == TC_UNATTACHED_SRC))) { /* * Change to sink if port is currently a source AND (new DRP * state is force sink OR new DRP state is toggle off and we are @@ -1871,7 +1870,7 @@ static void pd_update_dual_role_config(int port) */ set_state_tc(port, TC_UNATTACHED_SNK); } else if (tc[port].power_role == PD_ROLE_SINK && - drp_state[port] == PD_DRP_FORCE_SOURCE) { + drp_state[port] == PD_DRP_FORCE_SOURCE) { /* * Change to source if port is currently a sink and the * new DRP state is force source. @@ -1885,10 +1884,9 @@ __maybe_unused static void handle_new_power_state(int port) if (!IS_ENABLED(CONFIG_POWER_COMMON)) assert(0); - if (IS_ENABLED(CONFIG_POWER_COMMON) && - IS_ENABLED(CONFIG_USB_PE_SM)) { + if (IS_ENABLED(CONFIG_POWER_COMMON) && IS_ENABLED(CONFIG_USB_PE_SM)) { if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_ANY_OFF)) { + CHIPSET_STATE_ANY_OFF)) { /* * The SoC will negotiate alternate mode again when it * boots up @@ -1905,8 +1903,7 @@ __maybe_unused static void handle_new_power_state(int port) */ if (IS_ENABLED(CONFIG_USB_PE_SM)) { if (tc_is_vconn_src(port) && tc_is_attached_snk(port) && - !pd_check_vconn_swap(port) && - pd_is_battery_capable()) + !pd_check_vconn_swap(port) && pd_is_battery_capable()) pd_dpm_request(port, DPM_REQUEST_HARD_RESET_SEND); } @@ -1928,7 +1925,7 @@ __maybe_unused static void handle_new_power_state(int port) void pd_request_vconn_swap_off(int port) { if (get_state_tc(port) == TC_ATTACHED_SRC || - get_state_tc(port) == TC_ATTACHED_SNK) { + get_state_tc(port) == TC_ATTACHED_SNK) { TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF); task_wake(PD_PORT_TO_TASK_ID(port)); } @@ -1937,7 +1934,7 @@ void pd_request_vconn_swap_off(int port) void pd_request_vconn_swap_on(int port) { if (get_state_tc(port) == TC_ATTACHED_SRC || - get_state_tc(port) == TC_ATTACHED_SNK) { + get_state_tc(port) == TC_ATTACHED_SNK) { TC_SET_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_ON); task_wake(PD_PORT_TO_TASK_ID(port)); } @@ -2090,14 +2087,13 @@ static void sink_power_sub_states(int port) tc[port].typec_curr = usb_get_typec_current_limit( tc[port].polarity, cc1, cc2); - typec_set_input_current_limit(port, - tc[port].typec_curr, TYPE_C_VOLTAGE); + typec_set_input_current_limit(port, tc[port].typec_curr, + TYPE_C_VOLTAGE); charge_manager_update_dualrole(port, CAP_DEDICATED); } } } - /* * TYPE-C State Implementations */ @@ -2124,13 +2120,16 @@ static void tc_disabled_run(const int port) /* If pd_set_suspend clears the request, go to TC_UNATTACHED_SNK/SRC. */ if (!TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) { set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ? - TC_UNATTACHED_SRC : TC_UNATTACHED_SNK); + TC_UNATTACHED_SRC : + TC_UNATTACHED_SNK); } else { if (IS_ENABLED(CONFIG_USBC_RETIMER_FW_UPDATE)) { - if (TC_CHK_FLAG(port, - TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) { - TC_CLR_FLAG(port, - TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN); + if (TC_CHK_FLAG( + port, + TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN)) { + TC_CLR_FLAG( + port, + TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN); usb_retimer_fw_update_process_op_cb(port); } } @@ -2179,7 +2178,8 @@ static void tc_error_recovery_run(const int port) */ if (tc[port].ctx.previous == NULL) { set_state_tc(port, drp_state[port] == PD_DRP_FORCE_SOURCE ? - TC_UNATTACHED_SRC : TC_UNATTACHED_SNK); + TC_UNATTACHED_SRC : + TC_UNATTACHED_SNK); return; } @@ -2230,11 +2230,10 @@ static void tc_unattached_snk_entry(const int port) */ tcpm_debug_detach(port); typec_select_pull(port, TYPEC_CC_RD); - typec_select_src_current_limit_rp(port, - typec_get_default_current_limit_rp(port)); + typec_select_src_current_limit_rp( + port, typec_get_default_current_limit_rp(port)); typec_update_cc(port); - prev_data_role = tc[port].data_role; tc[port].data_role = PD_ROLE_DISCONNECTED; /* @@ -2383,9 +2382,9 @@ static void tc_attach_wait_snk_run(const int port) if (new_cc_state == PD_CC_NONE && pd_timer_is_expired(port, TC_TIMER_PD_DEBOUNCE)) { /* We are detached */ - if (drp_state[port] == PD_DRP_TOGGLE_OFF - || drp_state[port] == PD_DRP_FREEZE - || drp_state[port] == PD_DRP_FORCE_SINK) + if (drp_state[port] == PD_DRP_TOGGLE_OFF || + drp_state[port] == PD_DRP_FREEZE || + drp_state[port] == PD_DRP_FORCE_SINK) set_state_tc(port, TC_UNATTACHED_SNK); else set_state_tc(port, TC_UNATTACHED_SRC); @@ -2425,9 +2424,9 @@ static void tc_attach_wait_snk_run(const int port) } if (IS_ENABLED(CONFIG_USB_PE_SM) && - IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) { + IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) { hook_call_deferred(&pd_usb_billboard_deferred_data, - PD_T_AME); + PD_T_AME); } } } @@ -2471,7 +2470,7 @@ static void tc_attached_snk_entry(const int port) /* Change role to sink */ tc_set_power_role(port, PD_ROLE_SINK); tcpm_set_msg_header(port, tc[port].power_role, - tc[port].data_role); + tc[port].data_role); /* * Maintain VCONN supply state, whether ON or OFF, and its @@ -2490,11 +2489,10 @@ static void tc_attached_snk_entry(const int port) hook_notify(HOOK_USB_PD_CONNECT); if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) { - tc[port].typec_curr = - usb_get_typec_current_limit(tc[port].polarity, - cc1, cc2); - typec_set_input_current_limit(port, - tc[port].typec_curr, TYPE_C_VOLTAGE); + tc[port].typec_curr = usb_get_typec_current_limit( + tc[port].polarity, cc1, cc2); + typec_set_input_current_limit(port, tc[port].typec_curr, + TYPE_C_VOLTAGE); /* * Start new connections as dedicated until source caps * are received, at which point the PE will update the @@ -2550,8 +2548,8 @@ static bool tc_snk_check_vbus_removed(const int port) TC_TIMER_VBUS_DEBOUNCE)) { pd_timer_enable(port, TC_TIMER_VBUS_DEBOUNCE, PD_T_FRS_VBUS_DEBOUNCE); - } else if (pd_timer_is_expired(port, - TC_TIMER_VBUS_DEBOUNCE)) { + } else if (pd_timer_is_expired( + port, TC_TIMER_VBUS_DEBOUNCE)) { set_state_tc(port, TC_UNATTACHED_SNK); return true; } @@ -2658,8 +2656,9 @@ static void tc_attached_snk_run(const int port) /* Perform Data Role Swap */ tc_set_data_role(port, - tc[port].data_role == PD_ROLE_UFP ? - PD_ROLE_DFP : PD_ROLE_UFP); + tc[port].data_role == PD_ROLE_UFP ? + PD_ROLE_DFP : + PD_ROLE_UFP); } /* @@ -2787,8 +2786,8 @@ static void tc_unattached_src_entry(const int port) */ tcpm_debug_detach(port); typec_select_pull(port, TYPEC_CC_RP); - typec_select_src_current_limit_rp(port, - typec_get_default_current_limit_rp(port)); + typec_select_src_current_limit_rp( + port, typec_get_default_current_limit_rp(port)); typec_update_cc(port); prev_data_role = tc[port].data_role; @@ -2983,9 +2982,8 @@ static void tc_attached_src_entry(const int port) if (TC_CHK_FLAG(port, TC_FLAGS_PR_SWAP_IN_PROGRESS)) { /* Change role to source */ tc_set_power_role(port, PD_ROLE_SOURCE); - tcpm_set_msg_header(port, - tc[port].power_role, - tc[port].data_role); + tcpm_set_msg_header(port, tc[port].power_role, + tc[port].data_role); /* Enable VBUS */ tc_src_power_on(port); @@ -3040,10 +3038,9 @@ static void tc_attached_src_entry(const int port) set_vconn(port, 0); if (IS_ENABLED(CONFIG_USBC_SS_MUX)) - usb_mux_set(port, - USB_PD_MUX_NONE, - USB_SWITCH_DISCONNECT, - tc[port].polarity); + usb_mux_set(port, USB_PD_MUX_NONE, + USB_SWITCH_DISCONNECT, + tc[port].polarity); } tc_enable_pd(port, 0); @@ -3093,7 +3090,8 @@ static void tc_attached_src_entry(const int port) if (IS_ENABLED(CONFIG_USBC_SS_MUX)) usb_mux_set(port, USB_PD_MUX_NONE, - USB_SWITCH_DISCONNECT, tc[port].polarity); + USB_SWITCH_DISCONNECT, + tc[port].polarity); } } @@ -3161,13 +3159,13 @@ static void tc_attached_src_run(const int port) if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) tryWait = is_try_src_enabled(port) && - !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER); + !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER); if (drp_state[port] == PD_DRP_FORCE_SOURCE) new_tc_state = TC_UNATTACHED_SRC; - else if(IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) - new_tc_state = tryWait ? - TC_TRY_WAIT_SNK : TC_UNATTACHED_SNK; + else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC)) + new_tc_state = tryWait ? TC_TRY_WAIT_SNK : + TC_UNATTACHED_SNK; set_state_tc(port, new_tc_state); return; @@ -3221,8 +3219,9 @@ static void tc_attached_src_run(const int port) /* Perform Data Role Swap */ tc_set_data_role(port, - tc[port].data_role == PD_ROLE_DFP ? - PD_ROLE_UFP : PD_ROLE_DFP); + tc[port].data_role == PD_ROLE_DFP ? + PD_ROLE_UFP : + PD_ROLE_DFP); } /* @@ -3230,7 +3229,7 @@ static void tc_attached_src_run(const int port) * UnorientedDebugAccessory.SRC shall not drive Vconn */ if (IS_ENABLED(CONFIG_USBC_VCONN) && - !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) { + !TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER)) { /* * VCONN Swap Request */ @@ -3239,7 +3238,7 @@ static void tc_attached_src_run(const int port) set_vconn(port, 1); pe_vconn_swap_complete(port); } else if (TC_CHK_FLAG(port, - TC_FLAGS_REQUEST_VC_SWAP_OFF)) { + TC_FLAGS_REQUEST_VC_SWAP_OFF)) { TC_CLR_FLAG(port, TC_FLAGS_REQUEST_VC_SWAP_OFF); set_vconn(port, 0); pe_vconn_swap_complete(port); @@ -3265,8 +3264,7 @@ static void tc_attached_src_run(const int port) * applied. */ if (!TC_CHK_FLAG(port, TC_FLAGS_TS_DTS_PARTNER) && - TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) { - + TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) { set_state_tc(port, TC_CT_UNATTACHED_SNK); } } @@ -3274,13 +3272,13 @@ static void tc_attached_src_run(const int port) if (TC_CHK_FLAG(port, TC_FLAGS_UPDATE_CURRENT)) { TC_CLR_FLAG(port, TC_FLAGS_UPDATE_CURRENT); - typec_set_source_current_limit(port, - tc[port].select_current_limit_rp); + typec_set_source_current_limit( + port, tc[port].select_current_limit_rp); pd_update_contract(port); /* Update Rp if no contract is present */ if (!IS_ENABLED(CONFIG_USB_PE_SM) || - !pe_is_explicit_contract(port)) + !pe_is_explicit_contract(port)) typec_update_cc(port); } } @@ -3302,7 +3300,7 @@ static void tc_attached_src_exit(const int port) * a CTVPD was not detected */ if (TC_CHK_FLAG(port, TC_FLAGS_VCONN_ON) && - !TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) + !TC_CHK_FLAG(port, TC_FLAGS_CTVPD_DETECTED)) set_vconn(port, 0); } @@ -3332,14 +3330,14 @@ static __maybe_unused void check_drp_connection(const int port) tc[port].drp_sink_time = get_time().val; /* Get the next toggle state */ - next_state = drp_auto_toggle_next_state(&tc[port].drp_sink_time, - tc[port].power_role, drp_state[port], cc1, cc2, - tcpm_auto_toggle_supported(port)); + next_state = drp_auto_toggle_next_state( + &tc[port].drp_sink_time, tc[port].power_role, drp_state[port], + cc1, cc2, tcpm_auto_toggle_supported(port)); if (next_state == DRP_TC_DEFAULT) - next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) - ? DRP_TC_UNATTACHED_SRC - : DRP_TC_UNATTACHED_SNK; + next_state = (PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? + DRP_TC_UNATTACHED_SRC : + DRP_TC_UNATTACHED_SNK; switch (next_state) { case DRP_TC_UNATTACHED_SNK: @@ -3491,8 +3489,8 @@ static void tc_try_src_entry(const int port) */ typec_select_pull(port, TYPEC_CC_RP); - typec_select_src_current_limit_rp(port, - typec_get_default_current_limit_rp(port)); + typec_select_src_current_limit_rp( + port, typec_get_default_current_limit_rp(port)); /* Apply Rp */ typec_update_cc(port); @@ -3507,7 +3505,7 @@ static void tc_try_src_run(const int port) tcpm_get_cc(port, &cc1, &cc2); if ((cc1 == TYPEC_CC_VOLT_RD && cc2 != TYPEC_CC_VOLT_RD) || - (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD)) + (cc1 != TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD)) new_cc_state = PD_CC_UFP_ATTACHED; else new_cc_state = PD_CC_NONE; @@ -3801,7 +3799,6 @@ static void tc_cc_rd_entry(const int port) tcpm_set_msg_header(port, tc[port].power_role, tc[port].data_role); } - /** * Super State CC_RP */ @@ -3887,8 +3884,8 @@ void tc_run(const int port) * If pd_set_suspend set TC_FLAGS_REQUEST_SUSPEND, go directly to * TC_DISABLED. */ - if (get_state_tc(port) != TC_DISABLED - && TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) { + if (get_state_tc(port) != TC_DISABLED && + TC_CHK_FLAG(port, TC_FLAGS_REQUEST_SUSPEND)) { /* Invalidate a contract, if there is one */ if (IS_ENABLED(CONFIG_USB_PE_SM)) pe_invalidate_explicit_contract(port); @@ -3918,17 +3915,16 @@ static void pd_chipset_resume(void) int i; for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - if(IS_ENABLED(CONFIG_USB_PE_SM)) + if (IS_ENABLED(CONFIG_USB_PE_SM)) pd_resume_check_pr_swap_needed(i); - pd_set_dual_role_and_event(i, - pd_get_drp_state_in_s0(), - PD_EVENT_UPDATE_DUAL_ROLE - | PD_EVENT_POWER_STATE_CHANGE); + pd_set_dual_role_and_event(i, pd_get_drp_state_in_s0(), + PD_EVENT_UPDATE_DUAL_ROLE | + PD_EVENT_POWER_STATE_CHANGE); if (tc[i].data_role == PD_ROLE_DFP) { pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT | - ADO_POWER_STATE_CHANGE); + ADO_POWER_STATE_CHANGE); } } @@ -3941,14 +3937,13 @@ static void pd_chipset_suspend(void) int i; for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { - pd_set_dual_role_and_event(i, - pd_get_drp_state_in_suspend(), - PD_EVENT_UPDATE_DUAL_ROLE - | PD_EVENT_POWER_STATE_CHANGE); + pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(), + PD_EVENT_UPDATE_DUAL_ROLE | + PD_EVENT_POWER_STATE_CHANGE); if (tc[i].data_role == PD_ROLE_DFP) { pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT | - ADO_POWER_STATE_CHANGE); + ADO_POWER_STATE_CHANGE); } } @@ -3974,12 +3969,15 @@ static void pd_chipset_reset(void) * kernel knows to consume discovery information for them. */ for (tx = TCPCI_MSG_SOP; tx <= TCPCI_MSG_SOP_PRIME; tx++) { - if (pd_get_identity_discovery(i, tx) != PD_DISC_NEEDED - && pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED - && pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED) - pd_notify_event(i, tx == TCPCI_MSG_SOP ? - PD_STATUS_EVENT_SOP_DISC_DONE : - PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + if (pd_get_identity_discovery(i, tx) != + PD_DISC_NEEDED && + pd_get_svids_discovery(i, tx) != PD_DISC_NEEDED && + pd_get_modes_discovery(i, tx) != PD_DISC_NEEDED) + pd_notify_event( + i, + tx == TCPCI_MSG_SOP ? + PD_STATUS_EVENT_SOP_DISC_DONE : + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } /* Exit mode so AP can enter mode again after reset */ @@ -3995,10 +3993,9 @@ static void pd_chipset_startup(void) for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX); - pd_set_dual_role_and_event(i, - pd_get_drp_state_in_suspend(), - PD_EVENT_UPDATE_DUAL_ROLE - | PD_EVENT_POWER_STATE_CHANGE); + pd_set_dual_role_and_event(i, pd_get_drp_state_in_suspend(), + PD_EVENT_UPDATE_DUAL_ROLE | + PD_EVENT_POWER_STATE_CHANGE); /* * Request port discovery to restore any * alt modes. @@ -4010,7 +4007,7 @@ static void pd_chipset_startup(void) if (tc[i].data_role == PD_ROLE_DFP) { pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT | - ADO_POWER_STATE_CHANGE); + ADO_POWER_STATE_CHANGE); } } @@ -4024,14 +4021,13 @@ static void pd_chipset_shutdown(void) for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { TC_SET_FLAG(i, TC_FLAGS_UPDATE_USB_MUX); - pd_set_dual_role_and_event(i, - PD_DRP_FORCE_SINK, - PD_EVENT_UPDATE_DUAL_ROLE - | PD_EVENT_POWER_STATE_CHANGE); + pd_set_dual_role_and_event(i, PD_DRP_FORCE_SINK, + PD_EVENT_UPDATE_DUAL_ROLE | + PD_EVENT_POWER_STATE_CHANGE); if (tc[i].data_role == PD_ROLE_DFP) { pd_send_alert_msg(i, ADO_EXTENDED_ALERT_EVENT | - ADO_POWER_STATE_CHANGE); + ADO_POWER_STATE_CHANGE); } } -- cgit v1.2.1 From 7cd188b992d7a8ff85d12c0422c97c6d44a18068 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:46 -0600 Subject: baseboard/kukui/base_detect_kukui.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib7c2685a39a568a3d171464e8bcac412b4cacc92 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727914 Reviewed-by: Jeremy Bettis --- baseboard/kukui/base_detect_kukui.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/baseboard/kukui/base_detect_kukui.c b/baseboard/kukui/base_detect_kukui.c index 55da56f687..a41a676ef4 100644 --- a/baseboard/kukui/base_detect_kukui.c +++ b/baseboard/kukui/base_detect_kukui.c @@ -14,7 +14,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) /* Krane base detection code */ @@ -41,11 +41,11 @@ enum kukui_pogo_device_type { struct { int mv_low, mv_high; } static const pogo_detect_table[] = { - [DEVICE_TYPE_DETACHED] = {2700, 3500}, /* 10K, NC, around 3.3V */ + [DEVICE_TYPE_DETACHED] = { 2700, 3500 }, /* 10K, NC, around 3.3V */ #ifdef VARIANT_KUKUI_POGO_DOCK - [DEVICE_TYPE_DOCK] = {141, 173}, /* 10K, 0.5K ohm */ + [DEVICE_TYPE_DOCK] = { 141, 173 }, /* 10K, 0.5K ohm */ #endif - [DEVICE_TYPE_KEYBOARD] = {270, 400}, /* 10K, 1K ohm */ + [DEVICE_TYPE_KEYBOARD] = { 270, 400 }, /* 10K, 1K ohm */ }; BUILD_ASSERT(ARRAY_SIZE(pogo_detect_table) == DEVICE_TYPE_COUNT); @@ -71,7 +71,7 @@ static enum kukui_pogo_device_type get_device_type(int mv) for (i = 0; i < DEVICE_TYPE_COUNT; i++) { if (pogo_detect_table[i].mv_low <= mv && - mv <= pogo_detect_table[i].mv_high) + mv <= pogo_detect_table[i].mv_high) return i; } @@ -82,17 +82,17 @@ static void enable_charge(int enable) { #ifdef VARIANT_KUKUI_POGO_DOCK if (enable) { - struct charge_port_info info = { - .voltage = 5000, .current = 1500}; + struct charge_port_info info = { .voltage = 5000, + .current = 1500 }; /* * Set supplier type to PD to have same priority as type c * port. */ - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, &info); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + CHARGE_PORT_POGO, &info); } else { - charge_manager_update_charge( - CHARGE_SUPPLIER_DEDICATED, CHARGE_PORT_POGO, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + CHARGE_PORT_POGO, NULL); } pd_send_host_event(PD_EVENT_POWER_CHANGE); #endif @@ -112,7 +112,7 @@ static void base_set_device_type(enum kukui_pogo_device_type device_type) case DEVICE_TYPE_ERROR: case DEVICE_TYPE_UNKNOWN: hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_RETRY_US); + BASE_DETECT_RETRY_US); break; case DEVICE_TYPE_DETACHED: @@ -210,11 +210,11 @@ void base_force_state(enum ec_set_base_state_cmd state) gpio_disable_interrupt(GPIO_POGO_ADC_INT_L); pogo_type = (state == 1 ? DEVICE_TYPE_KEYBOARD : DEVICE_TYPE_DETACHED); - base_set_device_type(state == EC_SET_BASE_STATE_ATTACH - ? DEVICE_TYPE_KEYBOARD - : DEVICE_TYPE_DETACHED); - CPRINTS("BD forced %sconnected", state == EC_SET_BASE_STATE_ATTACH ? - "" : "dis"); + base_set_device_type(state == EC_SET_BASE_STATE_ATTACH ? + DEVICE_TYPE_KEYBOARD : + DEVICE_TYPE_DETACHED); + CPRINTS("BD forced %sconnected", + state == EC_SET_BASE_STATE_ATTACH ? "" : "dis"); } #ifdef VARIANT_KUKUI_POGO_DOCK -- cgit v1.2.1 From 56cc2f2ee6a0b8d392cc4bf5e3fda18f65ede653 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:37 -0600 Subject: baseboard/asurada/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac25249506cde8cf344c09ef1fac15ac1960b29d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727848 Reviewed-by: Jeremy Bettis --- baseboard/asurada/baseboard.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/baseboard/asurada/baseboard.h b/baseboard/asurada/baseboard.h index 21a29cf942..609721d243 100644 --- a/baseboard/asurada/baseboard.h +++ b/baseboard/asurada/baseboard.h @@ -83,10 +83,10 @@ #define CONFIG_I2C_VIRTUAL_BATTERY #define I2C_PORT_CHARGER IT83XX_I2C_CH_A #define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_POWER IT83XX_I2C_CH_A +#define I2C_PORT_POWER IT83XX_I2C_CH_A #define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY @@ -171,13 +171,12 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* And the MKBP events */ #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT)) + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT)) #include "baseboard_common.h" -- cgit v1.2.1 From 64448b1b4d0f03da0baf2371c11685dc5794566d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:15 -0600 Subject: board/corori/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If0040a13ca8fd551bf1df28b7f9cd829cfd67811 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728181 Reviewed-by: Jeremy Bettis --- board/corori/led.c | 64 +++++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/board/corori/led.c b/board/corori/led.c index 96a43caa76..8a8503a526 100644 --- a/board/corori/led.c +++ b/board/corori/led.c @@ -19,20 +19,16 @@ #define LED_ON_LVL 0 #define LED_OFF_LVL 1 -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT struct led_descriptor { enum ec_led_colors color; uint8_t time; }; -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; enum led_states { STATE_CHARGING, @@ -47,28 +43,32 @@ enum led_states { }; static const struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_BATTERY_S0_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_BATTERY_S3_BLINK] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_BATTERY_S5_OFF] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING] = { { EC_LED_COLOR_AMBER, LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_BATTERY_S0_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_BATTERY_S3_BLINK] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_BATTERY_S5_OFF] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - static int led_get_charge_percent(void) { return DIV_ROUND_NEAREST(charge_get_display_charge(), 10); @@ -131,7 +131,8 @@ static enum led_states led_get_state(void) case PWR_STATE_DISCHARGE /* and PWR_STATE_DISCHARGE_FULL */: if (chipset_in_state(CHIPSET_STATE_ON)) new_state = (led_get_charge_percent() < 10) ? - STATE_DISCHARGE_S0_BAT_LOW : STATE_DISCHARGE_S0; + STATE_DISCHARGE_S0_BAT_LOW : + STATE_DISCHARGE_S0; else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) new_state = STATE_BATTERY_S3_BLINK; else @@ -182,8 +183,7 @@ static void led_update_battery(void) ticks = 0; period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - + led_bat_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ @@ -196,8 +196,8 @@ static void led_update_battery(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ -- cgit v1.2.1 From b40a758bb9f928cefbc8405d11798af9279e7dac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:55 -0600 Subject: baseboard/kukui/battery_max17055.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39406aae25be91a1e47cbabb83698c592c975ba7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727918 Reviewed-by: Jeremy Bettis --- baseboard/kukui/battery_max17055.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/baseboard/kukui/battery_max17055.c b/baseboard/kukui/battery_max17055.c index 53e72766a7..8f196019b0 100644 --- a/baseboard/kukui/battery_max17055.c +++ b/baseboard/kukui/battery_max17055.c @@ -20,12 +20,9 @@ #define BATTERY_SIMPLO_CHARGE_MIN_TEMP 0 #define BATTERY_SIMPLO_CHARGE_MAX_TEMP 60 -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -enum battery_type { - BATTERY_SIMPLO = 0, - BATTERY_COUNT -}; +enum battery_type { BATTERY_SIMPLO = 0, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_SIMPLO] = { @@ -132,7 +129,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[BATT_ID][temp_zone].temp_max) + temp_zones[BATT_ID][temp_zone].temp_max) break; } } @@ -178,7 +175,7 @@ enum ec_status charger_profile_override_set_param(uint32_t param, int get_battery_manufacturer_name(char *dest, int size) { - static const char * const name[] = { + static const char *const name[] = { [BATTERY_SIMPLO] = "SIMPLO", }; ASSERT(dest); -- cgit v1.2.1 From dfe37ed6375e50d86eb10264840149977538fc3c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:52 -0600 Subject: include/power/cometlake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If1e6529656fbd6824bc2839fb27d9a841a590da4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730385 Reviewed-by: Jeremy Bettis --- include/power/cometlake.h | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/include/power/cometlake.h b/include/power/cometlake.h index 0f48346c9e..9c1a3a7a93 100644 --- a/include/power/cometlake.h +++ b/include/power/cometlake.h @@ -9,19 +9,21 @@ #define __CROS_EC_COMETLAKE_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ - PP5000_PGOOD_POWER_SIGNAL_MASK) +#define IN_ALL_S0 \ + (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \ + PP5000_PGOOD_POWER_SIGNAL_MASK) -#define CHIPSET_G3S5_POWERUP_SIGNAL (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ - POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)) +#define CHIPSET_G3S5_POWERUP_SIGNAL \ + (POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) | \ + POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD)) #define CHARGER_INITIALIZED_DELAY_MS 100 #define CHARGER_INITIALIZED_TRIES 40 -- cgit v1.2.1 From d90feaba3df75c54ebafb8fc7c4524ddccce653d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:22 -0600 Subject: test/accel_cal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie53e1b5ab4e2130c81a5ce2dda82f501c1536bca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730469 Reviewed-by: Jeremy Bettis --- test/accel_cal.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/test/accel_cal.c b/test/accel_cal.c index 34fd5678c2..5c18ff0a91 100644 --- a/test/accel_cal.c +++ b/test/accel_cal.c @@ -29,12 +29,12 @@ struct accel_cal cal = { static bool accumulate(float x, float y, float z, float temperature) { - return accel_cal_accumulate(&cal, 0, x, y, z, temperature) - || accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature) - || accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature) - || accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature) - || accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature) - || accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature); + return accel_cal_accumulate(&cal, 0, x, y, z, temperature) || + accel_cal_accumulate(&cal, 200 * MSEC, x, y, z, temperature) || + accel_cal_accumulate(&cal, 400 * MSEC, x, y, z, temperature) || + accel_cal_accumulate(&cal, 600 * MSEC, x, y, z, temperature) || + accel_cal_accumulate(&cal, 800 * MSEC, x, y, z, temperature) || + accel_cal_accumulate(&cal, 1000 * MSEC, x, y, z, temperature); } DECLARE_EC_TEST(test_calibrated_correctly_with_kasa) @@ -66,20 +66,16 @@ DECLARE_EC_TEST(test_calibrated_correctly_with_newton) float kasa_radius; int i; float data[] = { - 1.00290f, 0.09170f, 0.09649f, - 0.95183f, 0.23626f, 0.25853f, - 0.95023f, 0.15387f, 0.31865f, - 0.97374f, 0.01639f, 0.27675f, - 0.88521f, 0.30212f, 0.39558f, - 0.92787f, 0.35157f, 0.21209f, - 0.95162f, 0.33173f, 0.10924f, - 0.98397f, 0.22644f, 0.07737f, + 1.00290f, 0.09170f, 0.09649f, 0.95183f, 0.23626f, 0.25853f, + 0.95023f, 0.15387f, 0.31865f, 0.97374f, 0.01639f, 0.27675f, + 0.88521f, 0.30212f, 0.39558f, 0.92787f, 0.35157f, 0.21209f, + 0.95162f, 0.33173f, 0.10924f, 0.98397f, 0.22644f, 0.07737f, }; kasa_reset(&kasa); for (i = 0; i < ARRAY_SIZE(data); i += 3) { zassert_false(has_bias, NULL); - kasa_accumulate(&kasa, data[i], data[i + 1], data[i + 2]); + kasa_accumulate(&kasa, data[i], data[i + 1], data[i + 2]); has_bias = accumulate(data[i], data[i + 1], data[i + 2], 21.0f); } @@ -93,9 +89,9 @@ DECLARE_EC_TEST(test_calibrated_correctly_with_newton) zassert_true(sqrtf(powf(cal.bias[X] - 0.01f, 2.0f) + powf(cal.bias[Y] - 0.01f, 2.0f) + powf(cal.bias[Z] - 0.01f, 2.0f)) < - sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) + - powf(kasa_bias[Y] - 0.01f, 2.0f) + - powf(kasa_bias[Z] - 0.01f, 2.0f)), + sqrtf(powf(kasa_bias[X] - 0.01f, 2.0f) + + powf(kasa_bias[Y] - 0.01f, 2.0f) + + powf(kasa_bias[Z] - 0.01f, 2.0f)), NULL); return EC_SUCCESS; @@ -125,7 +121,9 @@ void before_test(void) accel_cal_reset(&cal); } -void after_test(void) {} +void after_test(void) +{ +} TEST_MAIN() { -- cgit v1.2.1 From 9ca6090abaa95dd93c3c00c329ea600aaf493192 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:55 -0600 Subject: common/util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92460a83a7ace84cc25d81ef3bbd53ab96921874 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729803 Reviewed-by: Jeremy Bettis --- common/util.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/common/util.c b/common/util.c index f85eae5ebf..d2521304b9 100644 --- a/common/util.c +++ b/common/util.c @@ -23,8 +23,8 @@ __stdlib_compat int strcasecmp(const char *s1, const char *s2) static int find_base(int base, int *c, const char **nptr) { - if ((base == 0 || base == 16) && *c == '0' - && (**nptr == 'x' || **nptr == 'X')) { + if ((base == 0 || base == 16) && *c == '0' && + (**nptr == 'x' || **nptr == 'X')) { *c = (*nptr)[1]; (*nptr) += 2; base = 16; @@ -131,7 +131,6 @@ int parse_bool(const char *s, int *dest) return 0; } - /* Constant-time memory comparison */ int safe_memcmp(const void *s1, const void *s2, size_t size) { @@ -253,7 +252,7 @@ bool is_aligned(uint32_t addr, uint32_t align) int alignment_log2(unsigned int x) { - ASSERT(x != 0); /* ctz(0) is undefined */ + ASSERT(x != 0); /* ctz(0) is undefined */ return __builtin_ctz(x); } @@ -261,9 +260,9 @@ int alignment_log2(unsigned int x) /* stateful conditional stuff */ enum cond_internal_bits { - COND_CURR_MASK = BIT(0), /* current value */ - COND_RISE_MASK = BIT(1), /* set if 0->1 */ - COND_FALL_MASK = BIT(2), /* set if 1->0 */ + COND_CURR_MASK = BIT(0), /* current value */ + COND_RISE_MASK = BIT(1), /* set if 0->1 */ + COND_FALL_MASK = BIT(2), /* set if 1->0 */ }; void cond_init(cond_t *c, int val) @@ -319,8 +318,7 @@ int cond_went(cond_t *c, int val) * *offset<0. If argc Date: Mon, 27 Jun 2022 13:57:05 -0600 Subject: board/nucleo-g431rb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia8eadd8318a6fe10b21d75f0e9bda9f15b6fc5be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728781 Reviewed-by: Jeremy Bettis --- board/nucleo-g431rb/board.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/nucleo-g431rb/board.c b/board/nucleo-g431rb/board.c index 2daf157e22..c25eee95b7 100644 --- a/board/nucleo-g431rb/board.c +++ b/board/nucleo-g431rb/board.c @@ -11,7 +11,6 @@ #include "gpio_list.h" /* Must come after other header files. */ - static void board_init(void) { /* -- cgit v1.2.1 From 7f1e4df5134820e9b38b720afd761156c79cd6b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:07 -0600 Subject: chip/npcx/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I124967cddefea1a5cf0f683e76c8ca61f686e798 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727024 Reviewed-by: Jeremy Bettis --- chip/npcx/pwm.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/chip/npcx/pwm.c b/chip/npcx/pwm.c index b2016906b3..de39da52a1 100644 --- a/chip/npcx/pwm.c +++ b/chip/npcx/pwm.c @@ -23,7 +23,7 @@ #if !(DEBUG_PWM) #define CPRINTS(...) #else -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #endif /* pwm resolution for each channel */ @@ -31,20 +31,20 @@ static uint32_t pwm_res[PWM_CH_COUNT]; /* PWM clock source */ enum npcx_pwm_source_clock { - NPCX_PWM_CLOCK_APB2_LFCLK = 0, - NPCX_PWM_CLOCK_FX = 1, - NPCX_PWM_CLOCK_FR = 2, - NPCX_PWM_CLOCK_RESERVED = 3, - NPCX_PWM_CLOCK_UNDEF = 0xFF + NPCX_PWM_CLOCK_APB2_LFCLK = 0, + NPCX_PWM_CLOCK_FX = 1, + NPCX_PWM_CLOCK_FR = 2, + NPCX_PWM_CLOCK_RESERVED = 3, + NPCX_PWM_CLOCK_UNDEF = 0xFF }; /* PWM heartbeat mode */ enum npcx_pwm_heartbeat_mode { - NPCX_PWM_HBM_NORMAL = 0, - NPCX_PWM_HBM_25 = 1, - NPCX_PWM_HBM_50 = 2, - NPCX_PWM_HBM_100 = 3, - NPCX_PWM_HBM_UNDEF = 0xFF + NPCX_PWM_HBM_NORMAL = 0, + NPCX_PWM_HBM_25 = 1, + NPCX_PWM_HBM_50 = 2, + NPCX_PWM_HBM_100 = 3, + NPCX_PWM_HBM_UNDEF = 0xFF }; /** @@ -146,7 +146,7 @@ void pwm_set_raw_duty(enum pwm_channel ch, uint16_t duty) /* Assume the fan control is active high and invert it ourselves */ UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP, - (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)); + (pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW)); CPRINTS("initial freq=0x%x", pwm_channels[ch].freq); CPRINTS("duty_cycle_cnt=%d", duty); @@ -189,7 +189,7 @@ uint16_t pwm_get_raw_duty(enum pwm_channel ch) * so scale to 0 - 0xffff */ return DIV_ROUND_NEAREST(NPCX_DCR(mdl) * EC_PWM_MAX_DUTY, - pwm_res[ch]); + pwm_res[ch]); } /** @@ -206,22 +206,22 @@ void pwm_config(enum pwm_channel ch) /* Set PWM heartbeat mode is no heartbeat */ SET_FIELD(NPCX_PWMCTL(mdl), NPCX_PWMCTL_HB_DC_CTL_FIELD, - NPCX_PWM_HBM_NORMAL); + NPCX_PWM_HBM_NORMAL); /* Select default CLK or LFCLK clock input to PWM module */ SET_FIELD(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_FCK_SEL_FIELD, - NPCX_PWM_CLOCK_APB2_LFCLK); + NPCX_PWM_CLOCK_APB2_LFCLK); /* Set PWM polarity normal first */ CLEAR_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_INVP); /* Select PWM clock source */ UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL, - (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)); + (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP)); /* Select PWM IO type */ UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT, - (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN)); + (pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN)); /* Set PWM operation frequency */ pwm_set_freq(ch, pwm_channels[ch].freq); -- cgit v1.2.1 From 60c551852ded297367e8a4562c5c7a6814cf2672 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:43 -0600 Subject: zephyr/shim/include/usbc/tcpc_nct38xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb941161cd9e51cec470055e2992a3cfdf84e68a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730840 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_nct38xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h index 87b222c794..cf71122589 100644 --- a/zephyr/shim/include/usbc/tcpc_nct38xx.h +++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h @@ -11,7 +11,7 @@ #define NCT38XX_TCPC_COMPAT nuvoton_nct38xx -#define TCPC_CONFIG_NCT38XX(id) \ +#define TCPC_CONFIG_NCT38XX(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ -- cgit v1.2.1 From 14743cf4b28e543b63380a3c20d77835a075c2a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:24 -0600 Subject: board/corori2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61a2427da08fe67de3c6338999b9daf1bc27f7e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728184 Reviewed-by: Jeremy Bettis --- board/corori2/board.h | 57 ++++++++++++++++++++++----------------------------- 1 file changed, 24 insertions(+), 33 deletions(-) diff --git a/board/corori2/board.h b/board/corori2/board.h index 1e24d5eb71..5ed39cf531 100644 --- a/board/corori2/board.h +++ b/board/corori2/board.h @@ -19,7 +19,7 @@ /* Save some flash space */ #define CONFIG_CHIP_INIT_ROM_REGION -#undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CONSOLE_CMDHELP #define CONFIG_DEBUG_ASSERT_BRIEF #define CONFIG_USB_PD_DEBUG_LEVEL 2 @@ -37,9 +37,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -68,7 +69,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -98,23 +99,22 @@ #undef PD_POWER_SUPPLY_TURN_OFF_DELAY #undef CONFIG_USBC_VCONN_SWAP_DELAY_US /* 20% margin added for these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 13080 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 16080 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ - +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 787 /* us */ /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -128,13 +128,13 @@ #define GPIO_EC_I2C_SUB_USB_C1_SDA GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -161,25 +161,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From 353ac0ac699f23fc3285a664d9309e884ad4740b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:06 -0600 Subject: board/metaknight/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa71c14cadb27cea98cc41c23a177d7620c67ab4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728450 Reviewed-by: Jeremy Bettis --- board/metaknight/board.h | 53 +++++++++++++++++++----------------------------- 1 file changed, 21 insertions(+), 32 deletions(-) diff --git a/board/metaknight/board.h b/board/metaknight/board.h index c331c76457..0c1e8d0d77 100644 --- a/board/metaknight/board.h +++ b/board/metaknight/board.h @@ -11,7 +11,6 @@ #define VARIANT_DEDEDE_EC_NPCX796FC #include "baseboard.h" - /* Battery */ #define CONFIG_BATTERY_FUEL_GAUGE @@ -19,7 +18,7 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -31,12 +30,11 @@ */ #define GPIO_USB_C1_INT_ODL GPIO_SUB_C1_INT_EN_RAILS_ODL - /* LED defines */ #define CONFIG_LED_ONOFF_STATES /* PWM */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -71,16 +69,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -97,16 +95,16 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel second source */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel second source */ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel second source */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel second source */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source */ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -154,25 +152,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_MEMORY, - TEMP_SENSOR_CPU, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_MEMORY, TEMP_SENSOR_CPU, TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_COUNT, -- cgit v1.2.1 From 14502cb1090f9a22ae47f89c83a4a2e5944a7c3c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:24 -0600 Subject: board/npcx7_evb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc3d94a4308c441f0a996b086e234a2c98f6a79a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728765 Reviewed-by: Jeremy Bettis --- board/npcx7_evb/board.c | 83 +++++++++++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 44 deletions(-) diff --git a/board/npcx7_evb/board.c b/board/npcx7_evb/board.c index 7909668d2c..1cd4108266 100644 --- a/board/npcx7_evb/board.c +++ b/board/npcx7_evb/board.c @@ -36,18 +36,23 @@ /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 }, [PWM_CH_KBLIGHT] = { 2, 0, 10000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -56,7 +61,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = 0, /* Use MFT id to control fan */ + .ch = 0, /* Use MFT id to control fan */ .pgood_gpio = GPIO_PGOOD_FAN, .enable_gpio = -1, }; @@ -75,55 +80,45 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master0-0", - .port = NPCX_I2C_PORT0_0, - .kbps = 100, - .scl = GPIO_I2C0_SCL0, - .sda = GPIO_I2C0_SDA0 - }, - { - .name = "master1-0", - .port = NPCX_I2C_PORT1_0, - .kbps = 100, - .scl = GPIO_I2C1_SCL0, - .sda = GPIO_I2C1_SDA0 - }, - { - .name = "master2-0", - .port = NPCX_I2C_PORT2_0, - .kbps = 100, - .scl = GPIO_I2C2_SCL0, - .sda = GPIO_I2C2_SDA0 - }, - { - .name = "master3-0", - .port = NPCX_I2C_PORT3_0, - .kbps = 100, - .scl = GPIO_I2C3_SCL0, - .sda = GPIO_I2C3_SDA0 - }, - { - .name = "master7-0", - .port = NPCX_I2C_PORT7_0, - .kbps = 100, - .scl = GPIO_I2C7_SCL0, - .sda = GPIO_I2C7_SDA0 - }, + { .name = "master0-0", + .port = NPCX_I2C_PORT0_0, + .kbps = 100, + .scl = GPIO_I2C0_SCL0, + .sda = GPIO_I2C0_SDA0 }, + { .name = "master1-0", + .port = NPCX_I2C_PORT1_0, + .kbps = 100, + .scl = GPIO_I2C1_SCL0, + .sda = GPIO_I2C1_SDA0 }, + { .name = "master2-0", + .port = NPCX_I2C_PORT2_0, + .kbps = 100, + .scl = GPIO_I2C2_SCL0, + .sda = GPIO_I2C2_SDA0 }, + { .name = "master3-0", + .port = NPCX_I2C_PORT3_0, + .kbps = 100, + .scl = GPIO_I2C3_SCL0, + .sda = GPIO_I2C3_SDA0 }, + { .name = "master7-0", + .port = NPCX_I2C_PORT7_0, + .kbps = 100, + .scl = GPIO_I2C7_SCL0, + .sda = GPIO_I2C7_SDA0 }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /******************************************************************************/ /* SPI devices */ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L}, + { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -- cgit v1.2.1 From d032fa3657bd2ec7773ea3033b1a56185fb0df8f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:15 -0600 Subject: board/nuwani/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I63c89fe62e879d6fb8bf68741da70668c4ebf713 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728785 Reviewed-by: Jeremy Bettis --- board/nuwani/board.c | 94 ++++++++++++++++++++++------------------------------ 1 file changed, 40 insertions(+), 54 deletions(-) diff --git a/board/nuwani/board.c b/board/nuwani/board.c index 567a26c8ef..c69ffff280 100644 --- a/board/nuwani/board.c +++ b/board/nuwani/board.c @@ -29,45 +29,35 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -80,19 +70,15 @@ static struct stprivate_data g_lis2dwl_data; /* Base accel private data */ static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA; - /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t lsm6dsm_base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, + FLOAT_TO_FP(1) } }; -static const mat33_fp_t treeya_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t lid_accel_1 = { .name = "Lid Accel", @@ -159,8 +145,7 @@ struct motion_sensor_t base_gyro_1 = { .location = MOTIONSENSE_LOC_BASE, .drv = &lsm6dsm_drv, .mutex = &g_base_mutex_1, - .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, - MOTIONSENSE_TYPE_GYRO), + .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO), .port = I2C_PORT_ACCEL, .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, .default_range = 1000 | ROUND_UP_FLAG, /* dps */ @@ -188,10 +173,12 @@ void board_update_sensor_config_from_sku(void) motion_sensors[LID_ACCEL] = lid_accel_1; motion_sensors[BASE_ACCEL] = base_accel_1; motion_sensors[BASE_GYRO] = base_gyro_1; - } else{ + } else { /*Need to change matrix for treeya*/ - motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref; - motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref; + motion_sensors[BASE_ACCEL].rot_standard_ref = + &treeya_standard_ref; + motion_sensors[BASE_GYRO].rot_standard_ref = + &treeya_standard_ref; } /* Enable Gyro interrupts */ @@ -201,8 +188,7 @@ void board_update_sensor_config_from_sku(void) /* Device is clamshell only */ tablet_set_mode(0, TABLET_TRIGGER_LID); /* Gyro is not present, don't allow line to float */ - gpio_set_flags(GPIO_6AXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } } -- cgit v1.2.1 From 7a63376e4e9a2133e9f24f99ddf6230889a5abf5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:44 -0600 Subject: baseboard/dedede/variant_ec_it8320.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70298f6d7d2037ca539e1779fbd032278ee2378f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727874 Reviewed-by: Jeremy Bettis --- baseboard/dedede/variant_ec_it8320.c | 64 +++++++++++++++--------------------- 1 file changed, 27 insertions(+), 37 deletions(-) diff --git a/baseboard/dedede/variant_ec_it8320.c b/baseboard/dedede/variant_ec_it8320.c index 29c7758c6a..642901dc57 100644 --- a/baseboard/dedede/variant_ec_it8320.c +++ b/baseboard/dedede/variant_ec_it8320.c @@ -16,7 +16,7 @@ #include "power.h" #include "registers.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) static void pp3300_a_pgood_low(void) { @@ -75,47 +75,37 @@ BUILD_ASSERT(ARRAY_SIZE(vcmp_list) == VCMP_COUNT); /* I2C Ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, #ifdef HAS_TASK_MOTIONSENSE - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, #endif #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From 5c0f1619c6e82436adbe874d852e14b7cdd2baf3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:33 -0600 Subject: board/haboki/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I193e4a81c3994db8155e9ae081c26aacac608d2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728447 Reviewed-by: Jeremy Bettis --- board/haboki/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/haboki/usb_pd_policy.c b/board/haboki/usb_pd_policy.c index 3ff7152541..6c3370ca2f 100644 --- a/board/haboki/usb_pd_policy.c +++ b/board/haboki/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From bc58f626a7f545845aacc23b68c7d6675b0a06f9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:35 -0600 Subject: zephyr/drivers/cros_system/cros_system_npcx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5aa31d74e91a3192590be7a0fb588e4a055563fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730682 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_system/cros_system_npcx.c | 40 +++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index 2952831cee..0767a2d230 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -82,7 +82,7 @@ struct cros_system_npcx_data { #define NPCX_RAM_BLOCK_PD_MASK (BIT(NPCX_RAM_PD_DEPTH) - 1) /* Get saved reset flag address in battery-backed ram */ -#define BBRAM_SAVED_RESET_FLAG_ADDR \ +#define BBRAM_SAVED_RESET_FLAG_ADDR \ (DT_REG_ADDR(DT_INST(0, nuvoton_npcx_bbram)) + \ DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset)) @@ -90,8 +90,8 @@ struct cros_system_npcx_data { static int system_npcx_watchdog_stop(void) { if (IS_ENABLED(CONFIG_WATCHDOG)) { - const struct device *wdt_dev = DEVICE_DT_GET( - DT_NODELABEL(twd0)); + const struct device *wdt_dev = + DEVICE_DT_GET(DT_NODELABEL(twd0)); if (!device_is_ready(wdt_dev)) { LOG_ERR("Error: device %s is not ready", wdt_dev->name); return -ENODEV; @@ -182,7 +182,7 @@ static void system_npcx_set_wakeup_gpios_before_hibernate(void) /* * Get the interrupt DTS node for this wakeup pin */ -#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx) +#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx) /* * Get the named-gpio node for this wakeup pin by reading the @@ -194,19 +194,19 @@ static void system_npcx_set_wakeup_gpios_before_hibernate(void) /* * Reset and re-enable interrupts on this wake pin. */ -#define WAKEUP_SETUP(id, prop, idx) \ -do { \ - gpio_pin_configure_dt(GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \ - GPIO_INPUT); \ - gpio_enable_dt_interrupt( \ - GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \ +#define WAKEUP_SETUP(id, prop, idx) \ + do { \ + gpio_pin_configure_dt( \ + GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \ + GPIO_INPUT); \ + gpio_enable_dt_interrupt( \ + GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \ } while (0); -/* - * For all the wake-pins, re-init the GPIO and re-enable the interrupt. - */ - DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, - wakeup_irqs, + /* + * For all the wake-pins, re-init the GPIO and re-enable the interrupt. + */ + DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs, WAKEUP_SETUP); #undef WAKEUP_INT @@ -460,8 +460,8 @@ static int cros_system_npcx_init(const struct device *dev) data->reset = UNKNOWN_RST; /* Use scratch bit to check power on reset or VCC1_RST reset. */ if (!IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH)) { - bool is_vcc1_rst = IS_BIT_SET(inst_scfg->RSTCTL, - NPCX_RSTCTL_VCC1_RST_STS); + bool is_vcc1_rst = + IS_BIT_SET(inst_scfg->RSTCTL, NPCX_RSTCTL_VCC1_RST_STS); data->reset = is_vcc1_rst ? VCC1_RST_PIN : POWERUP; } @@ -587,9 +587,9 @@ DEVICE_DEFINE(cros_system_npcx_0, "CROS_SYSTEM", cros_system_npcx_init, NULL, #define HAL_DBG_REG_BASE_ADDR \ ((struct dbg_reg *)DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_dbg))) -#define DBG_NODE DT_NODELABEL(dbg) -#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0) -#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f) +#define DBG_NODE DT_NODELABEL(dbg) +#define DBG_PINCTRL_PH DT_PHANDLE_BY_IDX(DBG_NODE, pinctrl_0, 0) +#define DBG_ALT_FILED(f) DT_PHA_BY_IDX(DBG_PINCTRL_PH, alts, 0, f) PINCTRL_DT_DEFINE(DBG_NODE); -- cgit v1.2.1 From 32b0a7963e3b79194a1c0caa8e0643d75a2e8aa8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:10 -0600 Subject: chip/stm32/usb_spi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If21f4468f81460b8e13925c25a1e0eda8b423c52 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729581 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_spi.h | 209 ++++++++++++++++++++++++++------------------------- 1 file changed, 106 insertions(+), 103 deletions(-) diff --git a/chip/stm32/usb_spi.h b/chip/stm32/usb_spi.h index fa86ba3651..12be68c2b1 100644 --- a/chip/stm32/usb_spi.h +++ b/chip/stm32/usb_spi.h @@ -268,48 +268,48 @@ * http://libusb.sourceforge.net/api-1.0/group__misc.html */ -#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX) +#define USB_SPI_FULL_DUPLEX_ENABLED (UINT16_MAX) -#define USB_SPI_PAYLOAD_SIZE_V2_START (58) +#define USB_SPI_PAYLOAD_SIZE_V2_START (58) -#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60) +#define USB_SPI_PAYLOAD_SIZE_V2_RESPONSE (60) -#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60) +#define USB_SPI_PAYLOAD_SIZE_V2_CONTINUE (60) -#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60) +#define USB_SPI_PAYLOAD_SIZE_V2_ERROR (60) -#define USB_SPI_MIN_PACKET_SIZE (2) +#define USB_SPI_MIN_PACKET_SIZE (2) enum packet_id_type { /* Request USB SPI configuration data from device. */ USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG = 0, /* USB SPI configuration data from device. */ - USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1, + USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG = 1, /* * Start a USB SPI transfer specifying number of bytes to write, * read and deliver first packet of data to write. */ - USB_SPI_PKT_ID_CMD_TRANSFER_START = 2, + USB_SPI_PKT_ID_CMD_TRANSFER_START = 2, /* Additional packets containing write payload. */ - USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3, + USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE = 3, /* * Request the device restart the response enabling us to recover * from packet loss without another SPI transfer. */ - USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4, + USB_SPI_PKT_ID_CMD_RESTART_RESPONSE = 4, /* * First packet of USB SPI response with the status code * and read payload if it was successful. */ - USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, + USB_SPI_PKT_ID_RSP_TRANSFER_START = 5, /* Additional packets containing read payload. */ - USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, + USB_SPI_PKT_ID_RSP_TRANSFER_CONTINUE = 6, /* * Request assertion or deassertion of chip select */ - USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7, + USB_SPI_PKT_ID_CMD_CHIP_SELECT = 7, /* Response to above request. */ - USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8, + USB_SPI_PKT_ID_RSP_CHIP_SELECT = 8, }; enum feature_bitmap { @@ -383,25 +383,25 @@ struct usb_spi_packet_ctx { }; enum usb_spi_error { - USB_SPI_SUCCESS = 0x0000, - USB_SPI_TIMEOUT = 0x0001, - USB_SPI_BUSY = 0x0002, - USB_SPI_WRITE_COUNT_INVALID = 0x0003, - USB_SPI_READ_COUNT_INVALID = 0x0004, - USB_SPI_DISABLED = 0x0005, + USB_SPI_SUCCESS = 0x0000, + USB_SPI_TIMEOUT = 0x0001, + USB_SPI_BUSY = 0x0002, + USB_SPI_WRITE_COUNT_INVALID = 0x0003, + USB_SPI_READ_COUNT_INVALID = 0x0004, + USB_SPI_DISABLED = 0x0005, /* The RX continue packet's data index is invalid. */ - USB_SPI_RX_BAD_DATA_INDEX = 0x0006, + USB_SPI_RX_BAD_DATA_INDEX = 0x0006, /* The RX endpoint has received more data than write count. */ - USB_SPI_RX_DATA_OVERFLOW = 0x0007, + USB_SPI_RX_DATA_OVERFLOW = 0x0007, /* An unexpected packet arrived on the device. */ - USB_SPI_RX_UNEXPECTED_PACKET = 0x0008, + USB_SPI_RX_UNEXPECTED_PACKET = 0x0008, /* The device does not support full duplex mode. */ USB_SPI_UNSUPPORTED_FULL_DUPLEX = 0x0009, - USB_SPI_UNKNOWN_ERROR = 0x8000, + USB_SPI_UNKNOWN_ERROR = 0x8000, }; enum usb_spi_request { - USB_SPI_REQ_ENABLE = 0x0000, + USB_SPI_REQ_ENABLE = 0x0000, USB_SPI_REQ_DISABLE = 0x0001, }; @@ -416,11 +416,11 @@ enum usb_spi_request { #ifdef CONFIG_USB_SPI_BUFFER_SIZE #define USB_SPI_BUFFER_SIZE CONFIG_USB_SPI_BUFFER_SIZE #else -#define USB_SPI_BUFFER_SIZE (USB_SPI_PAYLOAD_SIZE_V2_START + \ - (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) +#define USB_SPI_BUFFER_SIZE \ + (USB_SPI_PAYLOAD_SIZE_V2_START + (4 * USB_SPI_PAYLOAD_SIZE_V2_CONTINUE)) #endif -#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE -#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE +#define USB_SPI_MAX_WRITE_COUNT USB_SPI_BUFFER_SIZE +#define USB_SPI_MAX_READ_COUNT USB_SPI_BUFFER_SIZE /* Protocol uses two-byte length fields. Larger buffer makes no sense. */ BUILD_ASSERT(USB_SPI_BUFFER_SIZE <= 65536); @@ -541,78 +541,82 @@ struct usb_spi_config { * FLAGS encodes different run-time control parameters. See * USB_SPI_CONFIG_FLAGS_* for definitions. */ -#define USB_SPI_CONFIG(NAME, \ - INTERFACE, \ - ENDPOINT, \ - FLAGS) \ - static uint16_t CONCAT2(NAME, _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2];\ - static usb_uint CONCAT2(NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - struct usb_spi_state CONCAT2(NAME, _state_) = { \ - .enabled_host = 0, \ - .enabled_device = 0, \ - .enabled = 0, \ +#define USB_SPI_CONFIG(NAME, INTERFACE, ENDPOINT, FLAGS) \ + static uint16_t CONCAT2(NAME, \ + _buffer_)[(USB_SPI_BUFFER_SIZE + 1) / 2]; \ + static usb_uint CONCAT2( \ + NAME, _ep_rx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2( \ + NAME, _ep_tx_buffer_)[USB_MAX_PACKET_SIZE / 2] __usb_ram; \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ + struct usb_spi_state CONCAT2(NAME, _state_) = { \ + .enabled_host = 0, \ + .enabled_device = 0, \ + .enabled = 0, \ .spi_write_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - .spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ - }; \ - struct usb_spi_config const NAME = { \ - .state = &CONCAT2(NAME, _state_), \ - .interface = INTERFACE, \ - .endpoint = ENDPOINT, \ - .deferred = &CONCAT2(NAME, _deferred__data), \ - .ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ - .ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ - .flags = FLAGS, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ - .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ - .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ - .iInterface = USB_STR_SPI_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx_) (void) { usb_spi_tx (&NAME); } \ - static void CONCAT2(NAME, _ep_rx_) (void) { usb_spi_rx (&NAME); } \ - static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ - { \ - usb_spi_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx_), \ - CONCAT2(NAME, _ep_rx_), \ - CONCAT2(NAME, _ep_event_)); \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_spi_interface(&NAME, rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_spi_deferred(&NAME); } + .spi_read_ctx.buffer = (uint8_t *)CONCAT2(NAME, _buffer_), \ + }; \ + struct usb_spi_config const NAME = { \ + .state = &CONCAT2(NAME, _state_), \ + .interface = INTERFACE, \ + .endpoint = ENDPOINT, \ + .deferred = &CONCAT2(NAME, _deferred__data), \ + .ep_rx_ram = CONCAT2(NAME, _ep_rx_buffer_), \ + .ep_tx_ram = CONCAT2(NAME, _ep_tx_buffer_), \ + .flags = FLAGS, \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ + .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SPI, \ + .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SPI, \ + .iInterface = USB_STR_SPI_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = USB_MAX_PACKET_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx_)(void) \ + { \ + usb_spi_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx_)(void) \ + { \ + usb_spi_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event_)(enum usb_ep_event evt) \ + { \ + usb_spi_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx_), \ + CONCAT2(NAME, _ep_rx_), CONCAT2(NAME, _ep_event_)); \ + static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf, \ + usb_uint * tx_buf) \ + { \ + return usb_spi_interface(&NAME, rx_buf, tx_buf); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_)); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_spi_deferred(&NAME); \ + } /* * Handle SPI request in a deferred callback. @@ -636,9 +640,8 @@ void usb_spi_enable(struct usb_spi_config const *config, int enabled); void usb_spi_tx(struct usb_spi_config const *config); void usb_spi_rx(struct usb_spi_config const *config); void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt); -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, - usb_uint *tx_buf); +int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf, + usb_uint *tx_buf); /* * These functions should be implemented by the board to provide any board -- cgit v1.2.1 From 558afd4a1643ace6efa3ac3872f0f83d3b442902 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:10 -0600 Subject: board/taeko/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20a081a6074d31a7a444bd8b2062be00068b59f7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728979 Reviewed-by: Jeremy Bettis --- board/taeko/board.h | 146 +++++++++++++++++++++++----------------------------- 1 file changed, 64 insertions(+), 82 deletions(-) diff --git a/board/taeko/board.h b/board/taeko/board.h index 67cd95d648..e4b4de8bb9 100644 --- a/board/taeko/board.h +++ b/board/taeko/board.h @@ -30,18 +30,17 @@ #define CONFIG_LED_ONOFF_STATES /* Sensors */ -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Button */ #define CONFIG_BUTTONS_RUNTIME_CONFIG - /* Change Request (b/199529373) * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C * LSM6DSOETR3TR base accel/gyro if board id = 0 * LSM6DS3TR-C Base accel/gyro if board id > 0 */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_LSM6DSM @@ -56,14 +55,13 @@ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL)) /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_BMA4XX #define CONFIG_ACCEL_LIS2DWL @@ -72,7 +70,7 @@ #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -80,7 +78,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 1 +#define CONFIG_IO_EXPANDER_PORT_COUNT 1 #define CONFIG_USB_PD_FRS_PPC #define CONFIG_USB_PD_FRS @@ -96,17 +94,17 @@ #define CONFIG_HOSTCMD_I2C_CONTROL /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* The lower the input voltage, the higher the power efficiency. */ #define PD_PREFER_LOW_VOLTAGE @@ -119,55 +117,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT - /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 - -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define I2C_ADDR_MP2964_FLAGS 0x20 /* Thermal features */ #define CONFIG_THERMISTOR @@ -176,16 +173,16 @@ #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Fan */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM /* 37h BIT7:2 VSYS_TH2 6.0V */ -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* 30h BIT13:12 Enable PSYS 00b */ #define CONFIG_CHARGER_BQ25710_PSYS_SENSING /* 31h BIT3 = 1 Enable ACOC */ @@ -202,15 +199,14 @@ #define CONFIG_CHARGER_BQ25710_PP_COMP /* 36h UVP 5600mV */ #define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_UVP \ - BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 +#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 /* 3Eh BIT15:8 VSYS_MIN 6.1V */ #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -230,17 +226,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT }; enum battery_type { BATTERY_SMP_51W, @@ -251,20 +239,14 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 956388204e16538cd31c12b18d95bceeec93de19 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:48 -0600 Subject: zephyr/shim/src/console_buffer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I36f89d1e3b06afc7a3df4c71b6ee87623b712f3d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730890 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/console_buffer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/zephyr/shim/src/console_buffer.c b/zephyr/shim/src/console_buffer.c index aaeb6dae68..6f970629f1 100644 --- a/zephyr/shim/src/console_buffer.c +++ b/zephyr/shim/src/console_buffer.c @@ -47,11 +47,9 @@ void console_buf_notify_chars(const char *s, size_t len) if (new_tail == head_idx) head_idx = next_idx(head_idx); if (new_tail == previous_snapshot_idx) - previous_snapshot_idx = - next_idx(previous_snapshot_idx); + previous_snapshot_idx = next_idx(previous_snapshot_idx); if (new_tail == current_snapshot_idx) - current_snapshot_idx = - next_idx(current_snapshot_idx); + current_snapshot_idx = next_idx(current_snapshot_idx); if (new_tail == read_next_idx) read_next_idx = next_idx(read_next_idx); -- cgit v1.2.1 From 385bcd82a1f3d0334214cea98b0c8c50b57f0c30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:14 -0600 Subject: driver/accel_lis2ds.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife41874d42e095562794460e455d02687def9284 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729911 Reviewed-by: Jeremy Bettis --- driver/accel_lis2ds.h | 152 +++++++++++++++++++++++++------------------------- 1 file changed, 75 insertions(+), 77 deletions(-) diff --git a/driver/accel_lis2ds.h b/driver/accel_lis2ds.h index e25bc5954f..bc10a10849 100644 --- a/driver/accel_lis2ds.h +++ b/driver/accel_lis2ds.h @@ -14,95 +14,93 @@ * 7-bit address is 110101Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define LIS2DS_ADDR0_FLAGS 0x1a -#define LIS2DS_ADDR1_FLAGS 0x1e +#define LIS2DS_ADDR0_FLAGS 0x1a +#define LIS2DS_ADDR1_FLAGS 0x1e /* who am I */ -#define LIS2DS_WHO_AM_I_REG 0x0f -#define LIS2DS_WHO_AM_I 0x43 +#define LIS2DS_WHO_AM_I_REG 0x0f +#define LIS2DS_WHO_AM_I 0x43 /* X, Y, Z axis data len */ -#define LIS2DS_OUT_XYZ_SIZE 6 +#define LIS2DS_OUT_XYZ_SIZE 6 /* COMMON DEFINE FOR ACCEL SENSOR */ -#define LIS2DS_EN_BIT 0x01 -#define LIS2DS_DIS_BIT 0x00 - -#define LIS2DS_CTRL1_ADDR 0x20 -#define LIS2DS_CTRL2_ADDR 0x21 -#define LIS2DS_CTRL3_ADDR 0x22 -#define LIS2DS_TAP_X_EN 0x20 -#define LIS2DS_TAP_Y_EN 0x10 -#define LIS2DS_TAP_Z_EN 0x08 -#define LIS2DS_TAP_EN_MASK (LIS2DS_TAP_X_EN | \ - LIS2DS_TAP_Y_EN | \ - LIS2DS_TAP_Z_EN) -#define LIS2DS_TAP_EN_ALL 0x07 - -#define LIS2DS_CTRL4_ADDR 0x23 -#define LIS2DS_INT1_FTH 0x02 -#define LIS2DS_INT1_D_TAP 0x08 -#define LIS2DS_INT1_S_TAP 0x40 - -#define LIS2DS_CTRL5_ADDR 0x24 -#define LIS2DS_FIFO_CTRL_ADDR 0x25 -#define LIS2DS_FIFO_MODE_MASK 0xe0 -#define LIS2DS_FIFO_BYPASS_MODE 0 -#define LIS2DS_FIFO_MODE 1 -#define LIS2DS_FIFO_CONT_MODE 6 - -#define LIS2DS_STATUS_REG 0x27 -#define LIS2DS_STS_XLDA_UP 0x01 -#define LIS2DS_SINGLE_TAP_UP 0x08 -#define LIS2DS_DOUBLE_TAP_UP 0x10 -#define LIS2DS_FIFO_THS_UP 0x80 - -#define LIS2DS_OUT_X_L_ADDR 0x28 -#define LIS2DS_FIFO_THS_ADDR 0x2e - -#define LIS2DS_FIFO_SRC_ADDR 0x2f -#define LIS2DS_FIFO_DIFF_MASK 0xff -#define LIS2DS_FIFO_DIFF8_MASK 0x20 -#define LIS2DS_FIFO_OVR_MASK 0x40 -#define LIS2DS_FIFO_FTH_MASK 0x80 +#define LIS2DS_EN_BIT 0x01 +#define LIS2DS_DIS_BIT 0x00 + +#define LIS2DS_CTRL1_ADDR 0x20 +#define LIS2DS_CTRL2_ADDR 0x21 +#define LIS2DS_CTRL3_ADDR 0x22 +#define LIS2DS_TAP_X_EN 0x20 +#define LIS2DS_TAP_Y_EN 0x10 +#define LIS2DS_TAP_Z_EN 0x08 +#define LIS2DS_TAP_EN_MASK (LIS2DS_TAP_X_EN | LIS2DS_TAP_Y_EN | LIS2DS_TAP_Z_EN) +#define LIS2DS_TAP_EN_ALL 0x07 + +#define LIS2DS_CTRL4_ADDR 0x23 +#define LIS2DS_INT1_FTH 0x02 +#define LIS2DS_INT1_D_TAP 0x08 +#define LIS2DS_INT1_S_TAP 0x40 + +#define LIS2DS_CTRL5_ADDR 0x24 +#define LIS2DS_FIFO_CTRL_ADDR 0x25 +#define LIS2DS_FIFO_MODE_MASK 0xe0 +#define LIS2DS_FIFO_BYPASS_MODE 0 +#define LIS2DS_FIFO_MODE 1 +#define LIS2DS_FIFO_CONT_MODE 6 + +#define LIS2DS_STATUS_REG 0x27 +#define LIS2DS_STS_XLDA_UP 0x01 +#define LIS2DS_SINGLE_TAP_UP 0x08 +#define LIS2DS_DOUBLE_TAP_UP 0x10 +#define LIS2DS_FIFO_THS_UP 0x80 + +#define LIS2DS_OUT_X_L_ADDR 0x28 +#define LIS2DS_FIFO_THS_ADDR 0x2e + +#define LIS2DS_FIFO_SRC_ADDR 0x2f +#define LIS2DS_FIFO_DIFF_MASK 0xff +#define LIS2DS_FIFO_DIFF8_MASK 0x20 +#define LIS2DS_FIFO_OVR_MASK 0x40 +#define LIS2DS_FIFO_FTH_MASK 0x80 /* * Concatenated with DIFF8 bit in FIFO_SRC (2Fh) register, it represents the * number of unread samples stored in FIFO. (000000000 = FIFO empty; * 100000000 = FIFO full, 256 unread samples). */ -#define LIS2DS_FIFO_SAMPLES_ADDR 0x30 -#define LIS2DS_TAP_6D_THS_ADDR 0x31 -#define LIS2DS_INT_DUR_ADDR 0x32 -#define LIS2DS_WAKE_UP_THS_ADDR 0x33 +#define LIS2DS_FIFO_SAMPLES_ADDR 0x30 +#define LIS2DS_TAP_6D_THS_ADDR 0x31 +#define LIS2DS_INT_DUR_ADDR 0x32 +#define LIS2DS_WAKE_UP_THS_ADDR 0x33 -#define LIS2DS_TAP_SRC_ADDR 0x38 -#define LIS2DS_TAP_EVENT_DETECT 0x40 +#define LIS2DS_TAP_SRC_ADDR 0x38 +#define LIS2DS_TAP_EVENT_DETECT 0x40 /* Alias Register/Mask */ -#define LIS2DS_ACC_ODR_ADDR LIS2DS_CTRL1_ADDR -#define LIS2DS_ACC_ODR_MASK 0xf0 +#define LIS2DS_ACC_ODR_ADDR LIS2DS_CTRL1_ADDR +#define LIS2DS_ACC_ODR_MASK 0xf0 -#define LIS2DS_BDU_ADDR LIS2DS_CTRL1_ADDR -#define LIS2DS_BDU_MASK 0x01 +#define LIS2DS_BDU_ADDR LIS2DS_CTRL1_ADDR +#define LIS2DS_BDU_MASK 0x01 -#define LIS2DS_SOFT_RESET_ADDR LIS2DS_CTRL2_ADDR -#define LIS2DS_SOFT_RESET_MASK 0x40 +#define LIS2DS_SOFT_RESET_ADDR LIS2DS_CTRL2_ADDR +#define LIS2DS_SOFT_RESET_MASK 0x40 -#define LIS2DS_LIR_ADDR LIS2DS_CTRL3_ADDR -#define LIS2DS_LIR_MASK 0x04 +#define LIS2DS_LIR_ADDR LIS2DS_CTRL3_ADDR +#define LIS2DS_LIR_MASK 0x04 -#define LIS2DS_H_ACTIVE_ADDR LIS2DS_CTRL3_ADDR -#define LIS2DS_H_ACTIVE_MASK 0x02 +#define LIS2DS_H_ACTIVE_ADDR LIS2DS_CTRL3_ADDR +#define LIS2DS_H_ACTIVE_MASK 0x02 -#define LIS2DS_INT1_FTH_ADDR LIS2DS_CTRL4_ADDR -#define LIS2DS_INT1_FTH_MASK 0x02 +#define LIS2DS_INT1_FTH_ADDR LIS2DS_CTRL4_ADDR +#define LIS2DS_INT1_FTH_MASK 0x02 -#define LIS2DS_INT2_ON_INT1_ADDR LIS2DS_CTRL5_ADDR -#define LIS2DS_INT2_ON_INT1_MASK 0x20 +#define LIS2DS_INT2_ON_INT1_ADDR LIS2DS_CTRL5_ADDR +#define LIS2DS_INT2_ON_INT1_MASK 0x20 -#define LIS2DS_DRDY_PULSED_ADDR LIS2DS_CTRL5_ADDR -#define LIS2DS_DRDY_PULSED_MASK 0x80 +#define LIS2DS_DRDY_PULSED_ADDR LIS2DS_CTRL5_ADDR +#define LIS2DS_DRDY_PULSED_MASK 0x80 /* Acc data rate for HR mode */ enum lis2ds_odr { @@ -118,7 +116,7 @@ enum lis2ds_odr { }; /* Absolute Acc rate */ -#define LIS2DS_ODR_MIN_VAL 12500 +#define LIS2DS_ODR_MIN_VAL 12500 #define LIS2DS_ODR_MAX_VAL \ MOTION_MAX_SENSOR_FREQUENCY(800000, LIS2DS_ODR_MIN_VAL) @@ -130,8 +128,8 @@ enum lis2ds_odr { (LIS2DS_ODR_MIN_VAL << (_reg - LIS2DS_ODR_12HZ_VAL)) /* Full scale range registers */ -#define LIS2DS_FS_ADDR LIS2DS_CTRL1_ADDR -#define LIS2DS_FS_MASK 0x0c +#define LIS2DS_FS_ADDR LIS2DS_CTRL1_ADDR +#define LIS2DS_FS_MASK 0x0c /* Acc FS value */ enum lis2ds_fs { @@ -142,20 +140,20 @@ enum lis2ds_fs { LIS2DS_FS_LIST_NUM }; -#define LIS2DS_ACCEL_FS_MAX_VAL 16 -#define LIS2DS_ACCEL_FS_MIN_VAL 2 +#define LIS2DS_ACCEL_FS_MAX_VAL 16 +#define LIS2DS_ACCEL_FS_MIN_VAL 2 /* Reg value from Full Scale */ -#define LIS2DS_FS_REG(_fs) \ - (_fs == 2 ? LIS2DS_FS_2G_VAL : \ - _fs == 16 ? LIS2DS_FS_16G_VAL : \ - __fls(_fs)) +#define LIS2DS_FS_REG(_fs) \ + (_fs == 2 ? LIS2DS_FS_2G_VAL : \ + _fs == 16 ? LIS2DS_FS_16G_VAL : \ + __fls(_fs)) /* * Sensor resolution in number of bits. Sensor has two resolution: * 10 and 14 bit for LP and HR mode resp. */ -#define LIS2DS_RESOLUTION 16 +#define LIS2DS_RESOLUTION 16 extern const struct accelgyro_drv lis2ds_drv; -- cgit v1.2.1 From ab4488422d4958dcf3783ac9232f85ecabf70fed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:28 -0600 Subject: board/eve/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2cf9b0f7ae8404797899662217061858aecdac06 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728313 Reviewed-by: Jeremy Bettis --- board/eve/battery.c | 95 +++++++++++++++++++++++++++-------------------------- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git a/board/eve/battery.c b/board/eve/battery.c index 2a505b80ec..40b211440d 100644 --- a/board/eve/battery.c +++ b/board/eve/battery.c @@ -18,10 +18,10 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHUTDOWN_DATA 0x0010 /* Vendor CTO command parameter */ #define SB_VENDOR_PARAM_CTO_DISABLE 0 @@ -81,16 +81,16 @@ static int otd_recovery_temp_reg = -1; * limits are given by discharging_min/max_c. */ static const struct battery_info batt_info_lg = { - .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ - .voltage_normal = 7700, - .voltage_min = 6100, /* Add 100mV for charger accuracy */ - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 46, - .charging_min_c = 10, - .charging_max_c = 50, - .discharging_min_c = 0, - .discharging_max_c = 60, + .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ + .voltage_normal = 7700, + .voltage_min = 6100, /* Add 100mV for charger accuracy */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 46, + .charging_min_c = 10, + .charging_max_c = 50, + .discharging_min_c = 0, + .discharging_max_c = 60, }; /* @@ -99,16 +99,16 @@ static const struct battery_info batt_info_lg = { * limits are given by discharging_min/max_c. */ static const struct battery_info batt_info_lishen = { - .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ - .voltage_normal = 7700, - .voltage_min = 6100, /* Add 100mV for charger accuracy */ - .precharge_current = 256, /* mA */ - .start_charging_min_c = 0, - .start_charging_max_c = 46, - .charging_min_c = 10, - .charging_max_c = 50, - .discharging_min_c = 0, - .discharging_max_c = 60, + .voltage_max = TARGET_WITH_MARGIN(8800, 5), /* mV */ + .voltage_normal = 7700, + .voltage_min = 6100, /* Add 100mV for charger accuracy */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 46, + .charging_min_c = 10, + .charging_max_c = 50, + .discharging_min_c = 0, + .discharging_max_c = 60, }; static const struct board_batt_params info[] = { @@ -139,7 +139,7 @@ static int board_get_battery_type(void) if (!battery_manufacturer_name(name, sizeof(name))) { for (i = 0; i < BATTERY_TYPE_COUNT; i++) { if (!strncasecmp(name, info[i].manuf_name, - ARRAY_SIZE(name)-1)) { + ARRAY_SIZE(name) - 1)) { board_battery_type = i; break; } @@ -168,7 +168,9 @@ DECLARE_HOOK(HOOK_INIT, board_init_battery_type, HOOK_PRIO_INIT_I2C + 1); const struct battery_info *battery_get_info(void) { return info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type].batt_info; + DEFAULT_BATTERY_TYPE : + board_battery_type] + .batt_info; } int board_cut_off_battery(void) @@ -192,7 +194,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) /* Do not discharge on AC if the battery is still waking up */ if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - !(curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.status & STATUS_FULLY_CHARGED)) return 0; /* @@ -209,8 +211,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) * and suspend USB charging and DC/DC converter. */ if (!battery_is_cut_off() && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; /* @@ -275,8 +277,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* Allow booting now that the battery has woke up */ @@ -305,8 +308,8 @@ static int battery_check_disconnect(void) uint8_t data[6]; /* Check if battery discharging is disabled. */ - rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return BATTERY_DISCONNECT_ERROR; @@ -384,14 +387,13 @@ static int board_battery_sb_write(uint8_t access, int cmd) buf[1] = cmd & 0xff; buf[2] = (cmd >> 8) & 0xff; - rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - buf, 1 + sizeof(uint16_t), NULL, 0); + rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, + 1 + sizeof(uint16_t), NULL, 0); return rv; } -int board_battery_read_mfgacc(int offset, int access, - uint8_t *buf, int len) +int board_battery_read_mfgacc(int offset, int access, uint8_t *buf, int len) { int rv; uint8_t block_len, reg; @@ -408,7 +410,7 @@ int board_battery_read_mfgacc(int offset, int access, reg = access; rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, ®, 1, - &block_len, 1, I2C_XFER_START); + &block_len, 1, I2C_XFER_START); if (rv) { i2c_lock(I2C_PORT_BATTERY, 0); return rv; @@ -419,7 +421,7 @@ int board_battery_read_mfgacc(int offset, int access, block_len = len; rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, NULL, 0, - buf, block_len, I2C_XFER_STOP); + buf, block_len, I2C_XFER_STOP); i2c_lock(I2C_PORT_BATTERY, 0); return rv; @@ -432,7 +434,8 @@ static int board_battery_unseal(uint32_t param) /* Get Operation Status */ rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + SB_ALT_MANUFACTURER_ACCESS, data, + sizeof(data)); if (rv) return EC_ERROR_UNKNOWN; @@ -457,7 +460,8 @@ static int board_battery_unseal(uint32_t param) /* Verify that battery is unsealed */ rv = board_battery_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + SB_ALT_MANUFACTURER_ACCESS, data, + sizeof(data)); if (rv || ((data[3] & 0x3) != 0x2)) return EC_ERROR_UNKNOWN; } @@ -474,7 +478,7 @@ static int board_battery_seal(void) int rv; i2c_lock(I2C_PORT_BATTERY, 1); - rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS, 0x0030); + rv = board_battery_sb_write(SB_MANUFACTURER_ACCESS, 0x0030); i2c_lock(I2C_PORT_BATTERY, 0); if (rv != EC_SUCCESS) @@ -507,8 +511,7 @@ static int board_battery_write_flash(int addr, uint32_t data, int len) len += 4; i2c_lock(I2C_PORT_BATTERY, 1); - rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, - len, NULL, 0); + rv = i2c_xfer(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, len, NULL, 0); i2c_lock(I2C_PORT_BATTERY, 0); return rv; @@ -522,13 +525,13 @@ static int board_battery_read_flash(int block, int len, uint8_t *buf) if (len > 4) len = 4; - rv = board_battery_read_mfgacc(block, - SB_ALT_MANUFACTURER_ACCESS, data, len + 2); + rv = board_battery_read_mfgacc(block, SB_ALT_MANUFACTURER_ACCESS, data, + len + 2); if (rv) return EC_RES_ERROR; for (i = 0; i < len; i++) - buf[i] = data[i+2]; + buf[i] = data[i + 2]; return EC_SUCCESS; } @@ -594,7 +597,7 @@ static int board_battery_fix_otd_recovery_temp(uint32_t value) (uint8_t *)&otd_recovery_temp)) otd_recovery_temp_reg = otd_recovery_temp; } else { - otd_recovery_temp_reg = otd_recovery_temp; + otd_recovery_temp_reg = otd_recovery_temp; } if (board_battery_seal()) { -- cgit v1.2.1 From bae899ded2999846d5b514c24a7945b82cf5b677 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:07 -0600 Subject: zephyr/emul/emul_isl923x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieaa3e670176fae8dc6c2e25a64bcf42fb54618d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730691 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_isl923x.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/zephyr/emul/emul_isl923x.c b/zephyr/emul/emul_isl923x.c index 9896804f7f..cb6abd849e 100644 --- a/zephyr/emul/emul_isl923x.c +++ b/zephyr/emul/emul_isl923x.c @@ -71,7 +71,7 @@ LOG_MODULE_REGISTER(isl923x_emul, CONFIG_ISL923X_EMUL_LOG_LEVEL); #define DEFAULT_R_SNS 10 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR -#define REG_TO_CURRENT(REG) ((REG) * DEFAULT_R_SNS / R_SNS) +#define REG_TO_CURRENT(REG) ((REG)*DEFAULT_R_SNS / R_SNS) struct isl923x_emul_data { /** Common I2C data */ @@ -160,8 +160,7 @@ void isl923x_emul_set_manufacturer_id(const struct emul *emulator, data->manufacturer_id_reg = manufacturer_id; } -void isl923x_emul_set_device_id(const struct emul *emulator, - uint16_t device_id) +void isl923x_emul_set_device_id(const struct emul *emulator, uint16_t device_id) { struct isl923x_emul_data *data = emulator->data; @@ -366,7 +365,7 @@ static int isl923x_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val, break; case ISL9238_REG_INPUT_VOLTAGE: WRITE_REG_16(data->input_voltage_reg, bytes, val, - REG_INPUT_VOLTAGE_MASK); + REG_INPUT_VOLTAGE_MASK); break; default: __ASSERT(false, "Attempt to write unimplemented reg 0x%02x", @@ -421,7 +420,7 @@ static int emul_isl923x_init(const struct emul *emul, return i2c_emul_register(parent, emul->dev_label, &data->common.emul); } -#define INIT_ISL923X(n) \ +#define INIT_ISL923X(n) \ static struct isl923x_emul_data isl923x_emul_data_##n = { \ .common = { \ .write_byte = isl923x_emul_write_byte, \ @@ -432,15 +431,15 @@ static int emul_isl923x_init(const struct emul *emul, DT_INST_NODE_HAS_PROP(n, battery), \ (DT_DEP_ORD(DT_INST_PROP(n, battery))), \ (-1)), \ - }; \ + }; \ static struct isl923x_emul_cfg isl923x_emul_cfg_##n = { \ .common = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ - }; \ - EMUL_DEFINE(emul_isl923x_init, DT_DRV_INST(n), &isl923x_emul_cfg_##n, \ + }; \ + EMUL_DEFINE(emul_isl923x_init, DT_DRV_INST(n), &isl923x_emul_cfg_##n, \ &isl923x_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(INIT_ISL923X) -- cgit v1.2.1 From acdb5ae8345fd918fadfdc3052d4def65068e75d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:42 -0600 Subject: common/charge_ramp_sw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2242db5cce312bcbe2de97d960952bfe25b80a3b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729616 Reviewed-by: Jeremy Bettis --- common/charge_ramp_sw.c | 65 ++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/common/charge_ramp_sw.c b/common/charge_ramp_sw.c index bfd6db057b..7a84343205 100644 --- a/common/charge_ramp_sw.c +++ b/common/charge_ramp_sw.c @@ -16,30 +16,30 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) /* Number of times to ramp current searching for limit before stable charging */ -#define RAMP_COUNT 3 +#define RAMP_COUNT 3 /* Maximum allowable time charger can be unplugged to be considered an OCP */ #define OC_RECOVER_MAX_TIME (SECOND) /* Delay for running state machine when board is not consuming full current */ -#define CURRENT_DRAW_DELAY (5*SECOND) +#define CURRENT_DRAW_DELAY (5 * SECOND) /* Current ramp increment */ -#define RAMP_CURR_INCR_MA 64 -#define RAMP_CURR_DELAY (500*MSEC) -#define RAMP_CURR_START_MA 500 +#define RAMP_CURR_INCR_MA 64 +#define RAMP_CURR_DELAY (500 * MSEC) +#define RAMP_CURR_START_MA 500 /* How much to backoff the input current limit when limit has been found */ -#define RAMP_ICL_BACKOFF (2*RAMP_CURR_INCR_MA) +#define RAMP_ICL_BACKOFF (2 * RAMP_CURR_INCR_MA) /* Interval at which VBUS voltage is monitored in stable state */ #define STABLE_VBUS_MONITOR_INTERVAL (SECOND) /* Time to delay for stablizing the charging current */ -#define STABLIZE_DELAY (5*SECOND) +#define STABLIZE_DELAY (5 * SECOND) enum chg_ramp_state { CHG_RAMP_DISCONNECTED, @@ -78,14 +78,13 @@ static int max_icl; static int min_icl; void chg_ramp_charge_supplier_change(int port, int supplier, int current, - timestamp_t registration_time, int voltage) + timestamp_t registration_time, int voltage) { /* * If the last active port was a valid port and the port * has changed, then this may have been an over-current. */ - if (active_port != CHARGE_PORT_NONE && - port != active_port) { + if (active_port != CHARGE_PORT_NONE && port != active_port) { if (oc_info_idx[active_port] == RAMP_COUNT - 1) oc_info_idx[active_port] = 0; else @@ -111,7 +110,8 @@ void chg_ramp_charge_supplier_change(int port, int supplier, int current, reg_time = registration_time; if (ramp_st != CHG_RAMP_STABILIZE) { ramp_st = (active_port == CHARGE_PORT_NONE) ? - CHG_RAMP_DISCONNECTED : CHG_RAMP_CHARGE_DETECT_DELAY; + CHG_RAMP_DISCONNECTED : + CHG_RAMP_CHARGE_DETECT_DELAY; CPRINTS("Ramp reset: st%d", ramp_st); task_wake(TASK_ID_CHG_RAMP); } @@ -153,7 +153,7 @@ void chg_ramp_task(void *u) int last_active_port = CHARGE_PORT_NONE; enum chg_ramp_state ramp_st_prev = CHG_RAMP_DISCONNECTED, - ramp_st_new = CHG_RAMP_DISCONNECTED; + ramp_st_new = CHG_RAMP_DISCONNECTED; int active_icl_new; /* Clear last OCP supplier to guarantee we ramp on first connect */ @@ -190,15 +190,15 @@ void chg_ramp_task(void *u) last_active_port = active_port; if (reg_time.val < ACTIVE_OC_INFO.ts.val + - OC_RECOVER_MAX_TIME) { + OC_RECOVER_MAX_TIME) { ACTIVE_OC_INFO.oc_detected = 1; } else { for (i = 0; i < RAMP_COUNT; ++i) - oc_info[active_port][i]. - oc_detected = 0; + oc_info[active_port][i] + .oc_detected = 0; } - detect_end_time_us = get_time().val + - CHARGE_DETECT_DELAY; + detect_end_time_us = + get_time().val + CHARGE_DETECT_DELAY; task_wait_time = CHARGE_DETECT_DELAY; break; } @@ -246,8 +246,8 @@ void chg_ramp_task(void *u) if (i == RAMP_COUNT) { /* Found OC threshold! */ - active_icl_new = ACTIVE_OC_INFO.icl - - RAMP_ICL_BACKOFF; + active_icl_new = + ACTIVE_OC_INFO.icl - RAMP_ICL_BACKOFF; ramp_st_new = CHG_RAMP_STABLE; } else { /* @@ -272,8 +272,8 @@ void chg_ramp_task(void *u) if (board_is_vbus_too_low(active_port, CHG_RAMP_VBUS_RAMPING)) { CPRINTS("VBUS low"); - active_icl_new = MAX(min_icl, active_icl - - RAMP_ICL_BACKOFF); + active_icl_new = MAX( + min_icl, active_icl - RAMP_ICL_BACKOFF); ramp_st_new = CHG_RAMP_STABILIZE; task_wait_time = STABLIZE_DELAY; stablize_port = active_port; @@ -300,8 +300,8 @@ void chg_ramp_task(void *u) } ramp_st_new = active_port == CHARGE_PORT_NONE ? - CHG_RAMP_DISCONNECTED : - CHG_RAMP_CHARGE_DETECT_DELAY; + CHG_RAMP_DISCONNECTED : + CHG_RAMP_CHARGE_DETECT_DELAY; break; case CHG_RAMP_STABLE: /* Maintain input current limit */ @@ -320,7 +320,7 @@ void chg_ramp_task(void *u) CHG_RAMP_VBUS_STABLE)) { CPRINTS("VBUS low; Re-ramp"); max_icl = MAX(min_icl, - max_icl - RAMP_ICL_BACKOFF); + max_icl - RAMP_ICL_BACKOFF); active_icl_new = min_icl; ramp_st_new = CHG_RAMP_RAMP; } @@ -334,9 +334,9 @@ void chg_ramp_task(void *u) /* Skip setting limit if status is stable twice in a row */ if (ramp_st_prev != CHG_RAMP_STABLE || - ramp_st != CHG_RAMP_STABLE) { - CPRINTS("Ramp p%d st%d %dmA %dmA", - active_port, ramp_st, min_icl, active_icl); + ramp_st != CHG_RAMP_STABLE) { + CPRINTS("Ramp p%d st%d %dmA %dmA", active_port, ramp_st, + min_icl, active_icl); /* Set the input current limit */ lim = chg_ramp_get_current_limit(); board_set_charge_limit(active_port, active_sup, lim, @@ -361,8 +361,8 @@ static int command_chgramp(int argc, char **argv) int i; int port; - ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n", - ramp_st, min_icl, active_icl); + ccprintf("Chg Ramp:\nState: %d\nMin ICL: %d\nActive ICL: %d\n", ramp_st, + min_icl, active_icl); for (port = 0; port < board_get_usb_pd_port_count(); port++) { ccprintf("Port %d:\n", port); @@ -377,7 +377,6 @@ static int command_chgramp(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp, - "", - "Dump charge ramp state info"); +DECLARE_CONSOLE_COMMAND(chgramp, command_chgramp, "", + "Dump charge ramp state info"); #endif -- cgit v1.2.1 From a940880e73eee39c87ef29dd77c744db64b13f38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:54 -0600 Subject: driver/touchpad_st.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7af32e090137f19c4f9279a24f92cf38254fc873 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730149 Reviewed-by: Jeremy Bettis --- driver/touchpad_st.c | 264 +++++++++++++++++++++------------------------------ 1 file changed, 107 insertions(+), 157 deletions(-) diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c index 56633bad16..db45b951c6 100644 --- a/driver/touchpad_st.c +++ b/driver/touchpad_st.c @@ -28,11 +28,11 @@ /* Console output macros */ #define CC_TOUCHPAD CC_USB #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr) -#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args) -#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_TP_UPDATED TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0) +#define TASK_EVENT_TP_UPDATED TASK_EVENT_CUSTOM_BIT(1) #define SPI (&(spi_devices[SPI_ST_TP_DEVICE_ID])) @@ -55,26 +55,26 @@ static void touchpad_power_control(void); */ static int system_state; -#define SYSTEM_STATE_DEBUG_MODE BIT(0) -#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1) -#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2) -#define SYSTEM_STATE_ACTIVE_MODE BIT(3) -#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4) -#define SYSTEM_STATE_READY BIT(5) +#define SYSTEM_STATE_DEBUG_MODE BIT(0) +#define SYSTEM_STATE_ENABLE_HEAT_MAP BIT(1) +#define SYSTEM_STATE_ENABLE_DOME_SWITCH BIT(2) +#define SYSTEM_STATE_ACTIVE_MODE BIT(3) +#define SYSTEM_STATE_DOME_SWITCH_LEVEL BIT(4) +#define SYSTEM_STATE_READY BIT(5) /* * Pending action for touchpad. */ static int tp_control; -#define TP_CONTROL_SHALL_HALT BIT(0) -#define TP_CONTROL_SHALL_RESET BIT(1) -#define TP_CONTROL_SHALL_INIT BIT(2) -#define TP_CONTROL_SHALL_INIT_FULL BIT(3) -#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4) -#define TP_CONTROL_RESETTING BIT(5) -#define TP_CONTROL_INIT BIT(6) -#define TP_CONTROL_INIT_FULL BIT(7) +#define TP_CONTROL_SHALL_HALT BIT(0) +#define TP_CONTROL_SHALL_RESET BIT(1) +#define TP_CONTROL_SHALL_INIT BIT(2) +#define TP_CONTROL_SHALL_INIT_FULL BIT(3) +#define TP_CONTROL_SHALL_DUMP_ERROR BIT(4) +#define TP_CONTROL_RESETTING BIT(5) +#define TP_CONTROL_INIT BIT(6) +#define TP_CONTROL_INIT_FULL BIT(7) /* * Number of times we have reset the touchpad because of errors. @@ -115,7 +115,6 @@ static struct { } /* anonymous */; } __packed rx_buf; - #ifdef CONFIG_USB_ISOCHRONOUS #define USB_ISO_PACKET_SIZE 256 /* @@ -124,7 +123,7 @@ static struct { struct packet_header_t { uint8_t index; -#define HEADER_FLAGS_NEW_FRAME BIT(0) +#define HEADER_FLAGS_NEW_FRAME BIT(0) uint8_t flags; } __packed; BUILD_ASSERT(sizeof(struct packet_header_t) < USB_ISO_PACKET_SIZE); @@ -133,7 +132,7 @@ static struct packet_header_t packet_header; /* What will be sent to USB interface. */ struct st_tp_usb_packet_t { -#define USB_FRAME_FLAGS_BUTTON BIT(0) +#define USB_FRAME_FLAGS_BUTTON BIT(0) /* * This will be true if user clicked on touchpad. * TODO(b/70482333): add corresponding code for button signal. @@ -165,7 +164,6 @@ static void st_tp_interrupt_send(void); DECLARE_DEFERRED(st_tp_interrupt_send); #endif - /* Function implementations */ static void set_bits(int *lvalue, int rvalue, int mask) @@ -184,8 +182,7 @@ static void set_bits(int *lvalue, int rvalue, int mask) * @return array index of next finger (i.e. (i + 1) if a finger is added). */ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report, - struct st_tp_event_t *event, - int i) + struct st_tp_event_t *event, int i) { const int id = event->finger.touch_id; @@ -193,9 +190,9 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report, if (event->finger.touch_type == ST_TP_TOUCH_TYPE_INVALID) return i; - if (event->evt_id == ST_TP_EVENT_ID_ENTER_POINTER) + if (event->evt_id == ST_TP_EVENT_ID_ENTER_POINTER) touch_slot |= 1 << id; - else if (event->evt_id == ST_TP_EVENT_ID_LEAVE_POINTER) + else if (event->evt_id == ST_TP_EVENT_ID_LEAVE_POINTER) touch_slot &= ~BIT(id); /* We cannot report more fingers */ @@ -213,10 +210,10 @@ static int st_tp_parse_finger(struct usb_hid_touchpad_report *report, report->finger[i].inrange = 1; report->finger[i].id = id; report->finger[i].pressure = event->finger.z; - report->finger[i].width = (event->finger.minor | - (event->minor_high << 4)) << 5; - report->finger[i].height = (event->finger.major | - (event->major_high << 4)) << 5; + report->finger[i].width = + (event->finger.minor | (event->minor_high << 4)) << 5; + report->finger[i].height = + (event->finger.major | (event->major_high << 4)) << 5; report->finger[i].x = (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X - event->finger.x); @@ -253,8 +250,7 @@ static int st_tp_check_domeswitch_state(void) * Domeswitch level from device is inverted. * That is, 0 => pressed, 1 => released. */ - set_bits(&system_state, - ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL, + set_bits(&system_state, ret ? 0 : SYSTEM_STATE_DOME_SWITCH_LEVEL, SYSTEM_STATE_DOME_SWITCH_LEVEL); return 0; } @@ -295,7 +291,7 @@ static int st_tp_write_hid_report(void) } } - if (!num_finger && !domeswitch_changed) /* nothing changed */ + if (!num_finger && !domeswitch_changed) /* nothing changed */ return 0; /* Don't report 0 finger click. */ @@ -343,8 +339,8 @@ static int st_tp_read_host_buffer_header(void) const uint8_t tx_buf[] = { ST_TP_CMD_READ_SPI_HOST_BUFFER, 0x00, 0x00 }; int rx_len = ST_TP_EXTRA_BYTE + sizeof(rx_buf.buffer_header); - return spi_transaction(SPI, tx_buf, sizeof(tx_buf), - (uint8_t *)&rx_buf, rx_len); + return spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf, + rx_len); } static int st_tp_send_ack(void) @@ -368,11 +364,7 @@ static int st_tp_update_system_state(int new_state, int mask) mask = SYSTEM_STATE_ENABLE_HEAT_MAP | SYSTEM_STATE_ENABLE_DOME_SWITCH; if ((new_state & mask) != (system_state & mask)) { - uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_FEATURE_SELECT, - 0x05, - 0 - }; + uint8_t tx_buf[] = { ST_TP_CMD_WRITE_FEATURE_SELECT, 0x05, 0 }; if (new_state & SYSTEM_STATE_ENABLE_HEAT_MAP) { CPRINTS("Heatmap enabled"); tx_buf[2] |= BIT(0); @@ -423,8 +415,8 @@ static int st_tp_update_system_state(int new_state, int mask) static void st_tp_enable_interrupt(int enable) { - uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01, enable ? 1 : 0}; + uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x01, + enable ? 1 : 0 }; if (enable) gpio_enable_interrupt(GPIO_TOUCHPAD_INT); spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0); @@ -434,8 +426,8 @@ static void st_tp_enable_interrupt(int enable) static int st_tp_start_scan(void) { - int new_state = (SYSTEM_STATE_ACTIVE_MODE | - SYSTEM_STATE_ENABLE_DOME_SWITCH); + int new_state = + (SYSTEM_STATE_ACTIVE_MODE | SYSTEM_STATE_ENABLE_DOME_SWITCH); int mask = new_state; int ret; @@ -451,9 +443,8 @@ static int st_tp_start_scan(void) static int st_tp_read_host_data_memory(uint16_t addr, void *rx_buf, int len) { - uint8_t tx_buf[] = { - ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8, addr & 0xFF - }; + uint8_t tx_buf[] = { ST_TP_CMD_READ_HOST_DATA_MEMORY, addr >> 8, + addr & 0xFF }; return spi_transaction(SPI, tx_buf, sizeof(tx_buf), rx_buf, len); } @@ -473,9 +464,7 @@ static int st_tp_stop_scan(void) static int st_tp_load_host_data(uint8_t mem_id) { - uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id - }; + uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x06, mem_id }; int retry, ret; uint16_t count; struct st_tp_host_data_header_t *header = &rx_buf.data_header; @@ -559,24 +548,24 @@ static int st_tp_read_system_info(int reload) */ static void enable_deep_sleep(int enable) { - uint8_t cmd[] = {0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08}; + uint8_t cmd[] = { 0xFA, 0x20, 0x00, 0x00, 0x68, enable ? 0x0B : 0x08 }; spi_transaction(SPI, cmd, sizeof(cmd), NULL, 0); } static void dump_error(void) { - uint8_t tx_buf[] = {0xFB, 0x20, 0x01, 0xEF, 0x80}; + uint8_t tx_buf[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 }; int rx_len = sizeof(rx_buf.dump_info) + ST_TP_EXTRA_BYTE; int i; - spi_transaction(SPI, tx_buf, sizeof(tx_buf), - (uint8_t *)&rx_buf, rx_len); + spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)&rx_buf, + rx_len); for (i = 0; i < ARRAY_SIZE(rx_buf.dump_info); i += 4) - CPRINTS("%08x %08x %08x %08x", - rx_buf.dump_info[i + 0], rx_buf.dump_info[i + 1], - rx_buf.dump_info[i + 2], rx_buf.dump_info[i + 3]); + CPRINTS("%08x %08x %08x %08x", rx_buf.dump_info[i + 0], + rx_buf.dump_info[i + 1], rx_buf.dump_info[i + 2], + rx_buf.dump_info[i + 3]); msleep(8); } @@ -590,7 +579,7 @@ static void dump_memory(void) { uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE; uint32_t offset, i; - uint8_t cmd[] = {0xFB, 0x00, 0x10, 0x00, 0x00}; + uint8_t cmd[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 }; if (!dump_memory_on_error) return; @@ -598,8 +587,8 @@ static void dump_memory(void) for (offset = 0; offset < size; offset += 512) { cmd[3] = (offset >> 8) & 0xFF; cmd[4] = (offset >> 0) & 0xFF; - spi_transaction(SPI, cmd, sizeof(cmd), - (uint8_t *)&rx_buf, rx_len); + spi_transaction(SPI, cmd, sizeof(cmd), (uint8_t *)&rx_buf, + rx_len); for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) { CPRINTF("%ph %ph %ph %ph " @@ -629,11 +618,8 @@ static void st_tp_handle_error(uint8_t error_type) /* * Suggest action: memory dump and power cycle. */ - if (error_type <= 0x06 || - error_type == 0xF1 || - error_type == 0xF2 || - error_type == 0xF3 || - (error_type >= 0x47 && error_type <= 0x4E)) { + if (error_type <= 0x06 || error_type == 0xF1 || error_type == 0xF2 || + error_type == 0xF3 || (error_type >= 0x47 && error_type <= 0x4E)) { tp_control |= TP_CONTROL_SHALL_RESET; return; } @@ -641,8 +627,7 @@ static void st_tp_handle_error(uint8_t error_type) /* * Suggest action: FW shall halt, consult ST. */ - if ((error_type >= 0x20 && error_type <= 0x23) || - error_type == 0x25 || + if ((error_type >= 0x20 && error_type <= 0x23) || error_type == 0x25 || (error_type >= 0x2E && error_type <= 0x46)) { CPRINTS("tp shall halt"); tp_control |= TP_CONTROL_SHALL_HALT; @@ -697,15 +682,13 @@ static void st_tp_handle_error_report(struct st_tp_event_t *e) static void st_tp_handle_status_report(struct st_tp_event_t *e) { static uint32_t prev_idle_count; - uint32_t info = ((e->report.info[0] << 0) | - (e->report.info[1] << 8) | - (e->report.info[2] << 16) | - (e->report.info[3] << 24)); + uint32_t info = ((e->report.info[0] << 0) | (e->report.info[1] << 8) | + (e->report.info[2] << 16) | (e->report.info[3] << 24)); if (e->report.report_type == ST_TP_STATUS_FCAL || e->report.report_type == ST_TP_STATUS_FRAME_DROP) - CPRINTS("TP STATUS REPORT: %02x %08x", - e->report.report_type, info); + CPRINTS("TP STATUS REPORT: %02x %08x", e->report.report_type, + info); /* * Idle count might not change if ST FW is busy (for example, when the @@ -803,8 +786,8 @@ static int st_tp_reset(void) * suggest us to reset or halt. */ if (!(tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) && - (tp_control & (TP_CONTROL_SHALL_HALT | - TP_CONTROL_SHALL_RESET))) + (tp_control & + (TP_CONTROL_SHALL_HALT | TP_CONTROL_SHALL_RESET))) break; for (i = 0; i < num_events; i++) { @@ -883,14 +866,10 @@ int touchpad_get_info(struct touchpad_info *tp) static int write_hwreg_cmd32(uint32_t address, uint32_t data) { uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_HW_REG, - (address >> 24) & 0xFF, - (address >> 16) & 0xFF, - (address >> 8) & 0xFF, - (address >> 0) & 0xFF, - (data >> 24) & 0xFF, - (data >> 16) & 0xFF, - (data >> 8) & 0xFF, + ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF, + (address >> 16) & 0xFF, (address >> 8) & 0xFF, + (address >> 0) & 0xFF, (data >> 24) & 0xFF, + (data >> 16) & 0xFF, (data >> 8) & 0xFF, (data >> 0) & 0xFF, }; @@ -900,12 +879,9 @@ static int write_hwreg_cmd32(uint32_t address, uint32_t data) static int write_hwreg_cmd8(uint32_t address, uint8_t data) { uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_HW_REG, - (address >> 24) & 0xFF, - (address >> 16) & 0xFF, - (address >> 8) & 0xFF, - (address >> 0) & 0xFF, - data, + ST_TP_CMD_WRITE_HW_REG, (address >> 24) & 0xFF, + (address >> 16) & 0xFF, (address >> 8) & 0xFF, + (address >> 0) & 0xFF, data, }; return spi_transaction(SPI, tx_buf, sizeof(tx_buf), NULL, 0); @@ -914,8 +890,7 @@ static int write_hwreg_cmd8(uint32_t address, uint8_t data) static int wait_for_flash_ready(uint8_t type) { uint8_t tx_buf[] = { - ST_TP_CMD_READ_HW_REG, - 0x20, 0x00, 0x00, type, + ST_TP_CMD_READ_HW_REG, 0x20, 0x00, 0x00, type, }; int ret = EC_SUCCESS, retry = 200; @@ -973,8 +948,8 @@ static int st_tp_start_flash_dma(void) return ret; } -static int st_tp_write_one_chunk(const uint8_t *head, - uint32_t addr, uint32_t chunk_size) +static int st_tp_write_one_chunk(const uint8_t *head, uint32_t addr, + uint32_t chunk_size) { uint8_t tx_buf[ST_TP_DMA_CHUNK_SIZE + 5]; uint32_t index = 0; @@ -1000,13 +975,13 @@ static int st_tp_write_one_chunk(const uint8_t *head, */ static int st_tp_write_flash(int offset, int size, const uint8_t *data) { - uint8_t tx_buf[12] = {0}; + uint8_t tx_buf[12] = { 0 }; const uint8_t *head = data, *tail = data + size; uint32_t addr, index, chunk_size; uint32_t flash_buffer_size; int ret; - offset >>= 2; /* offset should be count in words */ + offset >>= 2; /* offset should be count in words */ /* * To write to flash, the data has to be separated into several chunks. * Each chunk will be no more than `ST_TP_DMA_CHUNK_SIZE` bytes. @@ -1039,7 +1014,7 @@ static int st_tp_write_flash(int offset, int size, const uint8_t *data) tx_buf[index++] = 0x20; tx_buf[index++] = 0x00; tx_buf[index++] = 0x00; - tx_buf[index++] = 0x72; /* flash DMA config */ + tx_buf[index++] = 0x72; /* flash DMA config */ tx_buf[index++] = 0x00; tx_buf[index++] = 0x00; @@ -1108,9 +1083,7 @@ static uint8_t get_cx_version(uint8_t tp_version) */ static int st_tp_panel_init(int full) { - uint8_t tx_buf[] = { - ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02 - }; + uint8_t tx_buf[] = { ST_TP_CMD_WRITE_SYSTEM_COMMAND, 0x00, 0x02 }; int ret, retry; if (tp_control & (TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) @@ -1149,8 +1122,8 @@ static int st_tp_panel_init(int full) return EC_SUCCESS; } else if (ret == EC_ERROR_BUSY) { CPRINTS("Panel initialization on going..."); - } else if (tp_control & ~(TP_CONTROL_INIT | - TP_CONTROL_INIT_FULL)) { + } else if (tp_control & + ~(TP_CONTROL_INIT | TP_CONTROL_INIT_FULL)) { /* there are other kind of errors. */ CPRINTS("Panel initialization failed, tp_control: %x", tp_control); @@ -1275,8 +1248,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, int i; for (i = 0; i < num_events; i++) { - CPRINTS("event[%d]: id=%d, type=%d", - i, rx_buf.events[i].evt_id, + CPRINTS("event[%d]: id=%d, type=%d", i, + rx_buf.events[i].evt_id, rx_buf.events[i].report.report_type); } } @@ -1336,9 +1309,7 @@ static void touchpad_read_idle_count(void) uint32_t count; int ret; int rx_len = 2 + ST_TP_EXTRA_BYTE; - uint8_t cmd_read_counter[] = { - 0xFB, 0x00, 0x10, 0xff, 0xff - }; + uint8_t cmd_read_counter[] = { 0xFB, 0x00, 0x10, 0xff, 0xff }; /* Find address of idle count. */ ret = st_tp_load_host_data(ST_TP_MEM_ID_SYSTEM_INFO); @@ -1373,13 +1344,9 @@ static void touchpad_read_idle_count(void) */ static void touchpad_collect_error(void) { - const uint8_t tx_dump_error[] = { - 0xFB, 0x20, 0x01, 0xEF, 0x80 - }; + const uint8_t tx_dump_error[] = { 0xFB, 0x20, 0x01, 0xEF, 0x80 }; uint32_t dump_info[2]; - const uint8_t tx_dump_memory[] = { - 0xFB, 0x00, 0x10, 0x00, 0x00 - }; + const uint8_t tx_dump_memory[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 }; uint32_t dump_memory[16]; int i; @@ -1398,14 +1365,10 @@ static void touchpad_collect_error(void) CPRINTS("check memory dump:"); for (i = 0; i < ARRAY_SIZE(dump_memory); i += 8) { CPRINTF("%08x %08x %08x %08x %08x %08x %08x %08x\n", - dump_memory[i + 0], - dump_memory[i + 1], - dump_memory[i + 2], - dump_memory[i + 3], - dump_memory[i + 4], - dump_memory[i + 5], - dump_memory[i + 6], - dump_memory[i + 7]); + dump_memory[i + 0], dump_memory[i + 1], + dump_memory[i + 2], dump_memory[i + 3], + dump_memory[i + 4], dump_memory[i + 5], + dump_memory[i + 6], dump_memory[i + 7]); } for (i = 0; i < 3; i++) @@ -1522,9 +1485,9 @@ DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, touchpad_power_change, HOOK_PRIO_DEFAULT); #ifdef CONFIG_USB_ISOCHRONOUS static void st_tp_enable_heat_map(void) { - int new_state = (SYSTEM_STATE_ENABLE_HEAT_MAP | - SYSTEM_STATE_ENABLE_DOME_SWITCH | - SYSTEM_STATE_ACTIVE_MODE); + int new_state = + (SYSTEM_STATE_ENABLE_HEAT_MAP | + SYSTEM_STATE_ENABLE_DOME_SWITCH | SYSTEM_STATE_ACTIVE_MODE); int mask = new_state; st_tp_update_system_state(new_state, mask); @@ -1619,8 +1582,8 @@ static int st_tp_read_frame(void) * valid, but the data should always be ready when interrupt pin is low. * Let's skip this check for now. */ - ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), - (uint8_t *)rx_buf, rx_len); + ret = spi_transaction(SPI, tx_buf, sizeof(tx_buf), (uint8_t *)rx_buf, + rx_len); if (ret == EC_SUCCESS) { int i; uint8_t *dest = usb_packet[spi_buffer_index & 1].frame; @@ -1649,16 +1612,12 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config); static void st_tp_usb_tx_callback(struct usb_isochronous_config const *config); /* USB descriptors */ -USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config, - USB_IFACE_ST_TOUCHPAD, - USB_CLASS_VENDOR_SPEC, - USB_SUBCLASS_GOOGLE_HEATMAP, +USB_ISOCHRONOUS_CONFIG_FULL(usb_st_tp_heatmap_config, USB_IFACE_ST_TOUCHPAD, + USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_HEATMAP, USB_PROTOCOL_GOOGLE_HEATMAP, - USB_STR_HEATMAP_NAME, /* interface name */ - USB_EP_ST_TOUCHPAD, - USB_ISO_PACKET_SIZE, - st_tp_usb_tx_callback, - st_tp_usb_set_interface, + USB_STR_HEATMAP_NAME, /* interface name */ + USB_EP_ST_TOUCHPAD, USB_ISO_PACKET_SIZE, + st_tp_usb_tx_callback, st_tp_usb_set_interface, 1 /* 1 extra EP for interrupts */) /* ***This function will be executed in interrupt context*** */ @@ -1703,13 +1662,10 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config) if (num_byte_available > 0) { if (transmit_report_offset == 0) packet_header.flags |= HEADER_FLAGS_NEW_FRAME; - ret = usb_isochronous_write_buffer( - config, - (uint8_t *)&packet_header, - sizeof(packet_header), - offset, - &buffer_id, - 0); + ret = usb_isochronous_write_buffer(config, + (uint8_t *)&packet_header, + sizeof(packet_header), + offset, &buffer_id, 0); /* * Since USB_ISO_PACKET_SIZE > sizeof(packet_header), this must * be true. @@ -1721,12 +1677,8 @@ static int heatmap_send_packet(struct usb_isochronous_config const *config) packet_header.index++; ret = usb_isochronous_write_buffer( - config, - (uint8_t *)packet + transmit_report_offset, - num_byte_available, - offset, - &buffer_id, - 1); + config, (uint8_t *)packet + transmit_report_offset, + num_byte_available, offset, &buffer_id, 1); if (ret < 0) { /* * TODO(b/70482333): handle this error, it might be: @@ -1766,7 +1718,7 @@ static int st_tp_usb_set_interface(usb_uint alternate_setting, } else if (alternate_setting == 0) { hook_call_deferred(&st_tp_disable_heat_map_data, 0); return 0; - } else /* we only have two settings. */ + } else /* we only have two settings. */ return -1; } @@ -1785,12 +1737,12 @@ static int get_heat_map_addr(void) } struct st_tp_interrupt_t { -#define ST_TP_INT_FRAME_AVAILABLE BIT(0) +#define ST_TP_INT_FRAME_AVAILABLE BIT(0) uint8_t flags; } __packed; -static usb_uint st_tp_usb_int_buffer[ - DIV_ROUND_UP(sizeof(struct st_tp_interrupt_t), 2)] __usb_ram; +static usb_uint st_tp_usb_int_buffer[DIV_ROUND_UP( + sizeof(struct st_tp_interrupt_t), 2)] __usb_ram; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_ST_TOUCHPAD, 81) = { .bLength = USB_DT_ENDPOINT_SIZE, @@ -1809,8 +1761,8 @@ static void st_tp_interrupt_send(void) if (usb_buffer_index < spi_buffer_index) report.flags |= ST_TP_INT_FRAME_AVAILABLE; - memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer), - &report, sizeof(report)); + memcpy_to_usbram((void *)usb_sram_addr(st_tp_usb_int_buffer), &report, + sizeof(report)); /* enable TX */ STM32_TOGGLE_EP(USB_EP_ST_TOUCHPAD_INT, EP_TX_MASK, EP_TX_VALID, 0); usb_wake(); @@ -1833,10 +1785,8 @@ static void st_tp_interrupt_event(enum usb_ep_event evt) btable_ep[ep].tx_addr = usb_sram_addr(st_tp_usb_int_buffer); btable_ep[ep].tx_count = sizeof(struct st_tp_interrupt_t); - STM32_USB_EP(ep) = ((ep << 0) | - EP_TX_VALID | - (3 << 9) /* interrupt EP */ | - EP_RX_DISAB); + STM32_USB_EP(ep) = ((ep << 0) | EP_TX_VALID | + (3 << 9) /* interrupt EP */ | EP_RX_DISAB); } } -- cgit v1.2.1 From 1690831a6723b2b83009db42f5af135d04ff7ce4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:35 -0600 Subject: board/twinkie/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia26f9c9cfcaf60d2d8ba8d4e7e45ad24095575a2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729050 Reviewed-by: Jeremy Bettis --- board/twinkie/usb_pd_policy.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/twinkie/usb_pd_policy.c b/board/twinkie/usb_pd_policy.c index a8f76b40e5..4d39992e50 100644 --- a/board/twinkie/usb_pd_policy.c +++ b/board/twinkie/usb_pd_policy.c @@ -15,8 +15,8 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) @@ -50,27 +50,23 @@ __override int pd_check_power_swap(int port) return 0; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap */ return 1; } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { } __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { return 0; } -- cgit v1.2.1 From aa8ce68a966aa13bd55fb1171f79b7ef813df273 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:20 -0600 Subject: power/skylake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85667e3ac75888d8e36090ded5e20d82dd5eaa68 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730468 Reviewed-by: Jeremy Bettis --- power/skylake.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/power/skylake.c b/power/skylake.c index 511ab8c32f..883b6d0012 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -17,9 +17,9 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) -static int forcing_shutdown; /* Forced shutdown in progress? */ +static int forcing_shutdown; /* Forced shutdown in progress? */ /* Power signals list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -58,7 +58,6 @@ const struct power_signal_info power_signal_list[] = { }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - void chipset_force_shutdown(enum chipset_shutdown_reason reason) { CPRINTS("%s()", __func__); @@ -110,7 +109,7 @@ void chipset_handle_espi_reset_assert(void) * power button. If yes, release power button. */ if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) && - forcing_shutdown) { + forcing_shutdown) { power_button_pch_release(); forcing_shutdown = 0; } @@ -157,9 +156,8 @@ void chipset_handle_reboot(void) * Do not make PMIC re-sequence the power rails if the following reset * conditions are not met. */ - if (!(flags & - (EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HARD))) + if (!(flags & (EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | + EC_RESET_FLAG_HARD))) return; /* Preserve AP off request. */ -- cgit v1.2.1 From f2ce2f09a2b124e15f987ff86b6b4ef878726a2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:21 -0600 Subject: board/waddledoo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70388b23e8f804d7fef74464efba3cf29e6a423d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729109 Reviewed-by: Jeremy Bettis --- board/waddledoo/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/waddledoo/led.c b/board/waddledoo/led.c index b9ff2e74e8..f8568a5c27 100644 --- a/board/waddledoo/led.c +++ b/board/waddledoo/led.c @@ -20,13 +20,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, White */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 100 }, - [EC_LED_COLOR_AMBER] = { 100, 0 }, + /* Amber, White */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 100 }, [EC_LED_COLOR_AMBER] = { 100, 0 }, }; /* One logical LED with amber and white channels. */ -- cgit v1.2.1 From b323cafb82375a9ee4fa2d939449964f1ae28681 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:18 -0600 Subject: board/quackingstick/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec0f5f988cacd8839d06109f79cbe85211ca2d44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728850 Reviewed-by: Jeremy Bettis --- board/quackingstick/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/quackingstick/led.c b/board/quackingstick/led.c index e282459476..235b25a6a2 100644 --- a/board/quackingstick/led.c +++ b/board/quackingstick/led.c @@ -35,15 +35,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_LED_ORANGE, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_LED_BLUE, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -80,7 +80,7 @@ static void board_led_set_battery(void) break; case PWR_STATE_DISCHARGE: if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_ANY_SUSPEND)) { + CHIPSET_STATE_ANY_SUSPEND)) { /* Discharging in S3: Amber 1 sec, off 3 sec */ period = (1 + 3) * LED_ONE_SEC; battery_ticks = battery_ticks % period; @@ -89,7 +89,7 @@ static void board_led_set_battery(void) else color = LED_OFF; } else if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_ANY_OFF)) { + CHIPSET_STATE_ANY_OFF)) { /* Discharging in S5: off */ color = LED_OFF; } else { -- cgit v1.2.1 From de4624952b25a975d864f3993edbf46c14d93398 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:47 -0600 Subject: include/power/apollolake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8ea4c14957e0ed6e4c19f0b4af03624fbe9e2d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730383 Reviewed-by: Jeremy Bettis --- include/power/apollolake.h | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/include/power/apollolake.h b/include/power/apollolake.h index cc864f26c3..42bf15c67c 100644 --- a/include/power/apollolake.h +++ b/include/power/apollolake.h @@ -12,16 +12,15 @@ * Input state flags. * TODO: Normalize the power signal masks from board defines to SoC headers. */ -#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N) -#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N) +#define IN_RSMRST_N POWER_SIGNAL_MASK(X86_RSMRST_N) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_SLP_S3_N POWER_SIGNAL_MASK(X86_SLP_S3_N) +#define IN_SLP_S4_N POWER_SIGNAL_MASK(X86_SLP_S4_N) #define IN_PCH_SLP_S4_DEASSERTED IN_SLP_S4_N -#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK) -#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N) +#define IN_SUSPWRDNACK POWER_SIGNAL_MASK(X86_SUSPWRDNACK) +#define IN_SUS_STAT_N POWER_SIGNAL_MASK(X86_SUS_STAT_N) -#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | \ - IN_SLP_S4_N) +#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_N | IN_SLP_S4_N) #define IN_PGOOD_ALL_CORE (IN_RSMRST_N) @@ -34,16 +33,16 @@ enum power_signal { #ifdef CONFIG_POWER_S0IX - X86_SLP_S0_N, /* PCH -> SLP_S0_L */ + X86_SLP_S0_N, /* PCH -> SLP_S0_L */ #endif - X86_SLP_S3_N, /* PCH -> SLP_S3_L */ - X86_SLP_S4_N, /* PCH -> SLP_S4_L */ - X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ - - X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ - X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ - X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ - X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ + X86_SLP_S3_N, /* PCH -> SLP_S3_L */ + X86_SLP_S4_N, /* PCH -> SLP_S4_L */ + X86_SUSPWRDNACK, /* PCH -> SUSPWRDNACK */ + + X86_ALL_SYS_PG, /* PMIC -> PMIC_EC_PWROK_OD */ + X86_RSMRST_N, /* PMIC -> PMIC_EC_RSMRST_ODL */ + X86_PGOOD_PP3300, /* PMIC -> PP3300_PG_OD */ + X86_PGOOD_PP5000, /* PMIC -> PP5000_PG_OD */ /* Number of X86 signals */ POWER_SIGNAL_COUNT -- cgit v1.2.1 From e1c03bca02dac60c399ccc7432cfb493e576d51f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:03 -0600 Subject: common/keyboard_vivaldi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ica7620cdb9cb28c2b4c08049c960a890c8096a83 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729644 Reviewed-by: Jeremy Bettis --- common/keyboard_vivaldi.c | 55 ++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/common/keyboard_vivaldi.c b/common/keyboard_vivaldi.c index 1cab203857..2cee4f0b9f 100644 --- a/common/keyboard_vivaldi.c +++ b/common/keyboard_vivaldi.c @@ -15,7 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) /* * Row Column info for Top row keys T1 - T15. This has been sourced from @@ -25,21 +25,21 @@ __overridable const struct key { uint8_t row; uint8_t col; } vivaldi_keys[] = { - {.row = 0, .col = 2}, /* T1 */ - {.row = 3, .col = 2}, /* T2 */ - {.row = 2, .col = 2}, /* T3 */ - {.row = 1, .col = 2}, /* T4 */ - {.row = 3, .col = 4}, /* T5 */ - {.row = 2, .col = 4}, /* T6 */ - {.row = 1, .col = 4}, /* T7 */ - {.row = 2, .col = 9}, /* T8 */ - {.row = 1, .col = 9}, /* T9 */ - {.row = 0, .col = 4}, /* T10 */ - {.row = 0, .col = 1}, /* T11 */ - {.row = 1, .col = 5}, /* T12 */ - {.row = 3, .col = 5}, /* T13 */ - {.row = 0, .col = 9}, /* T14 */ - {.row = 0, .col = 11}, /* T15 */ + { .row = 0, .col = 2 }, /* T1 */ + { .row = 3, .col = 2 }, /* T2 */ + { .row = 2, .col = 2 }, /* T3 */ + { .row = 1, .col = 2 }, /* T4 */ + { .row = 3, .col = 4 }, /* T5 */ + { .row = 2, .col = 4 }, /* T6 */ + { .row = 1, .col = 4 }, /* T7 */ + { .row = 2, .col = 9 }, /* T8 */ + { .row = 1, .col = 9 }, /* T9 */ + { .row = 0, .col = 4 }, /* T10 */ + { .row = 0, .col = 1 }, /* T11 */ + { .row = 1, .col = 5 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 0, .col = 9 }, /* T14 */ + { .row = 0, .col = 11 }, /* T15 */ }; BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); @@ -69,8 +69,8 @@ static const uint16_t action_scancodes[] = { static const struct ec_response_keybd_config *vivaldi_keybd; -static enum -ec_status get_vivaldi_keybd_config(struct host_cmd_handler_args *args) +static enum ec_status +get_vivaldi_keybd_config(struct host_cmd_handler_args *args) { struct ec_response_keybd_config *resp = args->response; @@ -90,8 +90,8 @@ DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBD_CONFIG, get_vivaldi_keybd_config, * Boards selecting CONFIG_KEYBOARD_CUSTOMIZATION are likely to not * want vivaldi code messing with their customized keyboards. */ -__overridable -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) +__overridable const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return NULL; } @@ -117,8 +117,8 @@ static const struct ec_response_keybd_config default_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__overridable -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) +__overridable const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &default_keybd; } @@ -149,7 +149,6 @@ static void vivaldi_init(void) } for (i = 0; i < ARRAY_SIZE(vivaldi_keys); i++) { - uint8_t row, col, *mask; enum action_key key; @@ -157,8 +156,8 @@ static void vivaldi_init(void) col = vivaldi_keys[i].col; if (col >= KEYBOARD_COLS_MAX || row >= KEYBOARD_ROWS) { - CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)", - i, row, col); + CPRINTS("VIVALDI: Bad (row,col) for T-%u: (%u,%u)", i, + row, col); ASSERT(false); } @@ -171,18 +170,16 @@ static void vivaldi_init(void) key = vivaldi_keybd->action_keys[i]; if (i < vivaldi_keybd->num_top_row_keys && key != TK_ABSENT) { - /* Enable the mask */ *mask |= BIT(row); /* Populate the scancode */ set_scancode_set2(row, col, action_scancodes[key]); - CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X", - i, row, col, action_scancodes[key]); + CPRINTS("VIVALDI key-%u (r-%u, c-%u) = scancode-%X", i, + row, col, action_scancodes[key]); if (key == TK_VOL_UP) set_vol_up_key(row, col); - } } } -- cgit v1.2.1 From 72f80620b4a5aa3bfb51d23a7e357a3dd384878a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:55 -0600 Subject: board/blipper/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I405912e36c5396a682b734fb42e8d43d8bb50234 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728056 Reviewed-by: Jeremy Bettis --- board/blipper/board.c | 182 ++++++++++++++++++++++---------------------------- 1 file changed, 80 insertions(+), 102 deletions(-) diff --git a/board/blipper/board.c b/board/blipper/board.c index c980e3ce0f..8b2da26be2 100644 --- a/board/blipper/board.c +++ b/board/blipper/board.c @@ -47,8 +47,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 __override struct keyboard_scan_config keyscan_config = { @@ -105,7 +105,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -119,34 +118,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -208,16 +199,14 @@ static const struct ec_response_keybd_config blipper_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { - return &blipper_keybd; + return &blipper_keybd; } /* USB-A charging control */ -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_EN_USB_A0_VBUS -}; +const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS }; static uint32_t board_id; @@ -226,11 +215,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_lis2dwl_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; @@ -310,11 +297,9 @@ struct motion_sensor_t motion_sensors[] = { }; static struct icm_drv_data_t g_icm42607_data; -const mat33_fp_t based_ref_icm42607 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -342,28 +327,26 @@ struct motion_sensor_t icm42607_base_accel = { }, }; struct motion_sensor_t icm42607_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm42607_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm42607_data, - .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &based_ref_icm42607, - .min_frequency = ICM42607_GYRO_MIN_FREQ, - .max_frequency = ICM42607_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM42607, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm42607_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm42607_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &based_ref_icm42607, + .min_frequency = ICM42607_GYRO_MIN_FREQ, + .max_frequency = ICM42607_GYRO_MAX_FREQ, }; static struct bmi_drv_data_t g_bmi220_data; -const mat33_fp_t based_ref_bmi220 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t bmi220_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -391,20 +374,20 @@ struct motion_sensor_t bmi220_base_accel = { }, }; struct motion_sensor_t bmi220_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI220, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi260_drv, - .mutex = &g_base_mutex, - .drv_data = &g_bmi220_data, - .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &based_ref_bmi220, - .min_frequency = BMI_GYRO_MIN_FREQ, - .max_frequency = BMI_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMI220, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &bmi260_drv, + .mutex = &g_base_mutex, + .drv_data = &g_bmi220_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &based_ref_bmi220, + .min_frequency = BMI_GYRO_MIN_FREQ, + .max_frequency = BMI_GYRO_MAX_FREQ, }; unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); @@ -448,15 +431,13 @@ void board_init(void) * line to float. */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); /* Disable Volume keys for blipper */ button_disable_gpio(BUTTON_VOLUME_UP); button_disable_gpio(BUTTON_VOLUME_DOWN); - gpio_set_flags(GPIO_VOLDN_BTN_ODL, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_VOLUP_BTN_ODL, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_VOLDN_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_INPUT | GPIO_PULL_DOWN); } else { if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) { motion_sensors[BASE_ACCEL] = icm42607_base_accel; @@ -579,7 +560,6 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) @@ -591,8 +571,7 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); raa489000_enable_asgate(0, false); return EC_SUCCESS; } @@ -605,8 +584,7 @@ int board_set_active_charge_port(int port) /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { CPRINTUSB("p%d: sink path enable failed.", port); return EC_ERROR_UNKNOWN; } @@ -638,18 +616,18 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charge", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "5V_Inductor", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charge", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "5V_Inductor", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 9ef2059d81ec5f97432ad0162a12c7de308fc579 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:40 -0600 Subject: board/kano/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibde91643738909bb40d305b1853685b75cbb0b2f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728479 Reviewed-by: Jeremy Bettis --- board/kano/board.h | 136 +++++++++++++++++++++++------------------------------ 1 file changed, 60 insertions(+), 76 deletions(-) diff --git a/board/kano/board.h b/board/kano/board.h index e3988aad3f..7b4f793db9 100644 --- a/board/kano/board.h +++ b/board/kano/board.h @@ -25,7 +25,7 @@ #define CONFIG_LED_ONOFF_STATES /* Sensors */ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */ #define CONFIG_ACCELGYRO_ICM_COMM_I2C #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -46,12 +46,11 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_KX022 #define CONFIG_ACCEL_BMA4XX - /* Sensor console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO @@ -61,9 +60,8 @@ #define CONFIG_KEYBOARD_REFRESH_ROW3 #define CONFIG_KEYBOARD_FACTORY_TEST - /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -77,17 +75,17 @@ #define CONFIG_USB_PD_TCPM_RT1715 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -95,70 +93,70 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_ACCEL NPCX_I2C_PORT0_0 +#define I2C_PORT_ACCEL NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x54 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x54 /* SOC facing Burnside Bridge retimer */ -#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x55 +#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x55 /* Type-C connector facing Burnside Bridge retimer */ -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -180,12 +178,12 @@ /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -203,33 +201,19 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum battery_type { - BATTERY_AP19B8M, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_AP19B8M, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 25f083cb4ab0c068cc96d4d11f97e7cce177291f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:54 -0600 Subject: driver/ioexpander/tca64xxa.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc3902ac695ce9824186e5cd257ebb990dcf99cd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730010 Reviewed-by: Jeremy Bettis --- driver/ioexpander/tca64xxa.c | 61 ++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/driver/ioexpander/tca64xxa.c b/driver/ioexpander/tca64xxa.c index b44dd7a686..57b964257f 100644 --- a/driver/ioexpander/tca64xxa.c +++ b/driver/ioexpander/tca64xxa.c @@ -19,32 +19,33 @@ * must multiply them by 4. Flags value contains information which version * of chip is used. */ -#define TCA64XXA_PORT_ID(port, reg, flags) \ - ((((flags) & TCA64XXA_FLAG_VER_MASK) \ - >> TCA64XXA_FLAG_VER_OFFSET) * (reg) + (port)) +#define TCA64XXA_PORT_ID(port, reg, flags) \ + ((((flags)&TCA64XXA_FLAG_VER_MASK) >> TCA64XXA_FLAG_VER_OFFSET) * \ + (reg) + \ + (port)) static int tca64xxa_write_byte(int ioex, int port, int reg, uint8_t val) { const struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - const int reg_addr = TCA64XXA_PORT_ID(port, reg, - (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2:4); + const int reg_addr = TCA64XXA_PORT_ID( + port, reg, + (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 : + 4); - return i2c_write8(ioex_p->i2c_host_port, - ioex_p->i2c_addr_flags, - reg_addr, - val); + return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, + reg_addr, val); } static int tca64xxa_read_byte(int ioex, int port, int reg, int *val) { const struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - const int reg_addr = TCA64XXA_PORT_ID(port, reg, - (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2:4); + const int reg_addr = TCA64XXA_PORT_ID( + port, reg, + (ioex_p->flags & IOEX_FLAGS_TCA64XXA_FLAG_VER_TCA6416A) ? 2 : + 4); - return i2c_read8(ioex_p->i2c_host_port, - ioex_p->i2c_addr_flags, - reg_addr, - val); + return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, + reg_addr, val); } /* Restore default values in registers */ @@ -59,23 +60,17 @@ static int tca64xxa_reset(int ioex, int portsCount) * This loop sets default values (from specification) to all registers. */ for (port = 0; port < portsCount; port++) { - ret = tca64xxa_write_byte(ioex, - port, - TCA64XXA_REG_OUTPUT, + ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_OUTPUT, TCA64XXA_DEFAULT_OUTPUT); if (ret) return ret; - ret = tca64xxa_write_byte(ioex, - port, - TCA64XXA_REG_POLARITY_INV, + ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_POLARITY_INV, TCA64XXA_DEFAULT_POLARITY_INV); if (ret) return ret; - ret = tca64xxa_write_byte(ioex, - port, - TCA64XXA_REG_CONF, + ret = tca64xxa_write_byte(ioex, port, TCA64XXA_REG_CONF, TCA64XXA_DEFAULT_CONF); if (ret) return ret; @@ -150,7 +145,7 @@ static int tca64xxa_get_flags_by_mask(int ioex, int port, int mask, int *flags) *flags |= GPIO_OUTPUT; ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_OUTPUT, &v); - if(ret) + if (ret) return ret; if (v & mask) @@ -188,7 +183,7 @@ static int tca64xxa_set_flags_by_mask(int ioex, int port, int mask, int flags) /* Configuration */ ret = tca64xxa_read_byte(ioex, port, TCA64XXA_REG_CONF, &v); - if(ret) + if (ret) return ret; if (flags & GPIO_INPUT) @@ -217,13 +212,13 @@ static int tca64xxa_get_port(int ioex, int port, int *val) /* Driver structure */ const struct ioexpander_drv tca64xxa_ioexpander_drv = { - .init = tca64xxa_init, - .get_level = tca64xxa_get_level, - .set_level = tca64xxa_set_level, - .get_flags_by_mask = tca64xxa_get_flags_by_mask, - .set_flags_by_mask = tca64xxa_set_flags_by_mask, - .enable_interrupt = NULL, + .init = tca64xxa_init, + .get_level = tca64xxa_get_level, + .set_level = tca64xxa_set_level, + .get_flags_by_mask = tca64xxa_get_flags_by_mask, + .set_flags_by_mask = tca64xxa_set_flags_by_mask, + .enable_interrupt = NULL, #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT - .get_port = tca64xxa_get_port, + .get_port = tca64xxa_get_port, #endif }; -- cgit v1.2.1 From 0921de0437e147b6c4494a24d844a69b7ac710a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:29 -0600 Subject: chip/npcx/clock_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9035314214ab357f4cdf5c7539acdb15a25dc4ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729375 Reviewed-by: Jeremy Bettis --- chip/npcx/clock_chip.h | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h index 702b55c52a..1f3193ef61 100644 --- a/chip/npcx/clock_chip.h +++ b/chip/npcx/clock_chip.h @@ -95,40 +95,40 @@ * OSC_CLK (Unit:Hz). */ #if (OSC_CLK > 80000000) -#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */ +#define HFCGN 0x82 /* Set XF_RANGE as 1 if OSC_CLK >= 80MHz */ #else -#define HFCGN 0x02 +#define HFCGN 0x02 #endif -#if (OSC_CLK == 100000000) -#define HFCGMH 0x0B -#define HFCGML 0xEC +#if (OSC_CLK == 100000000) +#define HFCGMH 0x0B +#define HFCGML 0xEC #elif (OSC_CLK == 90000000) -#define HFCGMH 0x0A -#define HFCGML 0xBA +#define HFCGMH 0x0A +#define HFCGML 0xBA #elif (OSC_CLK == 80000000) -#define HFCGMH 0x09 -#define HFCGML 0x89 +#define HFCGMH 0x09 +#define HFCGML 0x89 #elif (OSC_CLK == 66000000) -#define HFCGMH 0x0F -#define HFCGML 0xBC +#define HFCGMH 0x0F +#define HFCGML 0xBC #elif (OSC_CLK == 50000000) -#define HFCGMH 0x0B -#define HFCGML 0xEC +#define HFCGMH 0x0B +#define HFCGML 0xEC #elif (OSC_CLK == 48000000) -#define HFCGMH 0x0B -#define HFCGML 0x72 +#define HFCGMH 0x0B +#define HFCGML 0x72 #elif (OSC_CLK == 40000000) -#define HFCGMH 0x09 -#define HFCGML 0x89 +#define HFCGMH 0x09 +#define HFCGML 0x89 #elif (OSC_CLK == 33000000) -#define HFCGMH 0x07 -#define HFCGML 0xDE +#define HFCGMH 0x07 +#define HFCGML 0xDE #elif (OSC_CLK == 30000000) -#define HFCGMH 0x07 -#define HFCGML 0x27 +#define HFCGMH 0x07 +#define HFCGML 0x27 #elif (OSC_CLK == 26000000) -#define HFCGMH 0x06 -#define HFCGML 0x33 +#define HFCGMH 0x06 +#define HFCGML 0x33 #else #error "Unsupported OSC_CLK Frequency" #endif -- cgit v1.2.1 From 428e96ee62665d62a98dcc0ab8c8b6c5989d6e5b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:14 -0600 Subject: common/rsa.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3e16221da54c37cae96cd1eb76ea6a14732351a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729731 Reviewed-by: Jeremy Bettis --- common/rsa.c | 54 +++++++++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/common/rsa.c b/common/rsa.c index 10f0afa4b4..b88298fa77 100644 --- a/common/rsa.c +++ b/common/rsa.c @@ -39,16 +39,14 @@ static int ge_mod(const struct rsa_public_key *key, const uint32_t *a) if (a[i] > key->n[i]) return 1; } - return 1; /* equal */ + return 1; /* equal */ } /** * Montgomery c[] += a * b[] / R % mod */ -static void mont_mul_add(const struct rsa_public_key *key, - uint32_t *c, - const uint32_t a, - const uint32_t *b) +static void mont_mul_add(const struct rsa_public_key *key, uint32_t *c, + const uint32_t a, const uint32_t *b) { uint64_t A = mula32(a, b[0], c[0]); uint32_t d0 = (uint32_t)A * key->n0inv; @@ -73,9 +71,8 @@ static void mont_mul_add(const struct rsa_public_key *key, /** * Montgomery c[] += 0 * b[] / R % mod */ -static void mont_mul_add_0(const struct rsa_public_key *key, - uint32_t *c, - const uint32_t *b) +static void mont_mul_add_0(const struct rsa_public_key *key, uint32_t *c, + const uint32_t *b) { uint32_t d0 = c[0] * key->n0inv; uint64_t B = mula32(d0, key->n[0], c[0]); @@ -90,8 +87,7 @@ static void mont_mul_add_0(const struct rsa_public_key *key, } /* Montgomery c[] = a[] * 1 / R % key. */ -static void mont_mul_1(const struct rsa_public_key *key, - uint32_t *c, +static void mont_mul_1(const struct rsa_public_key *key, uint32_t *c, const uint32_t *a) { int i; @@ -108,10 +104,8 @@ static void mont_mul_1(const struct rsa_public_key *key, /** * Montgomery c[] = a[] * b[] / R % mod */ -static void mont_mul(const struct rsa_public_key *key, - uint32_t *c, - const uint32_t *a, - const uint32_t *b) +static void mont_mul(const struct rsa_public_key *key, uint32_t *c, + const uint32_t *a, const uint32_t *b) { uint32_t i; for (i = 0; i < RSANUMWORDS; ++i) @@ -136,21 +130,20 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout, uint32_t *a = workbuf32; uint32_t *a_r = a + RSANUMWORDS; uint32_t *aa_r = a_r + RSANUMWORDS; - uint32_t *aaa = aa_r; /* Re-use location. */ + uint32_t *aaa = aa_r; /* Re-use location. */ int i; /* Convert from big endian byte array to little endian word array. */ for (i = 0; i < RSANUMWORDS; ++i) { - uint32_t tmp = - (inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) | - (inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) | - (inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) | - (inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0); + uint32_t tmp = (inout[((RSANUMWORDS - 1 - i) * 4) + 0] << 24) | + (inout[((RSANUMWORDS - 1 - i) * 4) + 1] << 16) | + (inout[((RSANUMWORDS - 1 - i) * 4) + 2] << 8) | + (inout[((RSANUMWORDS - 1 - i) * 4) + 3] << 0); a[i] = tmp; } /* TODO(drinkcat): This operation could be precomputed to save time. */ - mont_mul(key, a_r, a, key->rr); /* a_r = a * RR / R mod M */ + mont_mul(key, a_r, a, key->rr); /* a_r = a * RR / R mod M */ #ifdef CONFIG_RSA_EXPONENT_3 mont_mul(key, aa_r, a_r, a_r); mont_mul(key, a, aa_r, a_r); @@ -159,9 +152,10 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout, /* Exponent 65537 */ for (i = 0; i < 16; i += 2) { mont_mul(key, aa_r, a_r, a_r); /* aa_r = a_r * a_r / R mod M */ - mont_mul(key, a_r, aa_r, aa_r);/* a_r = aa_r * aa_r / R mod M */ + mont_mul(key, a_r, aa_r, aa_r); /* a_r = aa_r * aa_r / R mod M + */ } - mont_mul(key, aaa, a_r, a); /* aaa = a_r * a / R mod M */ + mont_mul(key, aaa, a_r, a); /* aaa = a_r * a / R mod M */ #endif /* Make sure aaa < mod; aaa is at most 1x mod too large. */ @@ -173,8 +167,8 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout, uint32_t tmp = aaa[i]; *inout++ = (uint8_t)(tmp >> 24); *inout++ = (uint8_t)(tmp >> 16); - *inout++ = (uint8_t)(tmp >> 8); - *inout++ = (uint8_t)(tmp >> 0); + *inout++ = (uint8_t)(tmp >> 8); + *inout++ = (uint8_t)(tmp >> 0); } } @@ -192,11 +186,9 @@ static void mod_pow(const struct rsa_public_key *key, uint8_t *inout, * * PS: octet string consisting of {Length(RSA Key) - Length(T) - 3} 0xFF */ -static const uint8_t sha256_tail[] = { - 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, - 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, - 0x05, 0x00, 0x04, 0x20 -}; +static const uint8_t sha256_tail[] = { 0x00, 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, + 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, + 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 }; #define PKCS_PAD_SIZE (RSANUMBYTES - SHA256_DIGEST_SIZE) @@ -255,5 +247,5 @@ int rsa_verify(const struct rsa_public_key *key, const uint8_t *signature, if (memcmp(buf + PKCS_PAD_SIZE, sha, SHA256_DIGEST_SIZE) != 0) return 0; - return 1; /* All checked out OK. */ + return 1; /* All checked out OK. */ } -- cgit v1.2.1 From 14f71750f19ba9c73a35ad51bb83704e7450a3ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:16 -0600 Subject: board/metaknight/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I712b14250365775d388b64966e6172989ce0a706 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728453 Reviewed-by: Jeremy Bettis --- board/metaknight/led.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/board/metaknight/led.c b/board/metaknight/led.c index 466037695c..a93f7b8a2e 100644 --- a/board/metaknight/led.c +++ b/board/metaknight/led.c @@ -19,20 +19,27 @@ __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; - + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From b80c6bb6597a742b8445a5fdee308db7397db57d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:23 -0600 Subject: test/rsa2048-F4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a3e2df6f4aed3bac224cdebfd2a9d985dc2e3f2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730536 Reviewed-by: Jeremy Bettis --- test/rsa2048-F4.h | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/test/rsa2048-F4.h b/test/rsa2048-F4.h index afe66a198f..4e698500bf 100644 --- a/test/rsa2048-F4.h +++ b/test/rsa2048-F4.h @@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data)); /* SHA-256 sum to verify: * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg' */ -const uint8_t hash[] = { - 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a, - 0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52, - 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 -}; +const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, + 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb, + 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52, + 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 }; /* Incorrect hash to test the negative case */ -const uint8_t hash_wrong[] = { - 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f, - 0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad, - 0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 -}; +const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, + 0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4, + 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad, + 0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 }; /* Generate signature using futility: * # futility create key.pem -- cgit v1.2.1 From cc33cc9195bcbedf4d704d1c5c6c20c687192ecb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:19 -0600 Subject: board/guybrush/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I685dbe58210e002496e3380c471d001b75a068ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728441 Reviewed-by: Jeremy Bettis --- board/guybrush/thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/guybrush/thermal.c b/board/guybrush/thermal.c index 606d21cfdf..517e374c6a 100644 --- a/board/guybrush/thermal.c +++ b/board/guybrush/thermal.c @@ -12,7 +12,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, -- cgit v1.2.1 From 263a0add068cb3b309f56516c0d7d8225f9e278b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:22 -0600 Subject: board/kohaku/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9be84b6ef885ff4725161bc7fbd776525b1e1268 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728563 Reviewed-by: Jeremy Bettis --- board/kohaku/board.c | 69 +++++++++++++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/board/kohaku/board.c b/board/kohaku/board.c index bf22dd6d41..5c704b718e 100644 --- a/board/kohaku/board.c +++ b/board/kohaku/board.c @@ -41,8 +41,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void ppc_interrupt(enum gpio_signal signal) { @@ -98,14 +98,13 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -223,11 +222,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -383,34 +380,34 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); /**********************************************************************/ /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_4] = { - "TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_AMB", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_GT", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_4] = { "TEMP_IA", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "GT", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "IA", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "GT", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "IA", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -423,8 +420,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ -- cgit v1.2.1 From 6cb3ae977b81061f5f3507c4ebc21c114e69c6be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:54 -0600 Subject: board/taniks/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id121f32ef7ea4cd3e640af7af65b97b602e9789a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729011 Reviewed-by: Jeremy Bettis --- board/taniks/fw_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/taniks/fw_config.c b/board/taniks/fw_config.c index cf1e27ad83..ee544fbffd 100644 --- a/board/taniks/fw_config.c +++ b/board/taniks/fw_config.c @@ -10,7 +10,7 @@ #include "fw_config.h" #include "gpio.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union taniks_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); @@ -65,7 +65,7 @@ void board_init_fw_config(void) CPRINTS("CBI: Using board defaults for early board"); if (ec_cfg_has_tabletmode()) { fw_config = fw_config_defaults; - } + } } determine_storage(); -- cgit v1.2.1 From 1c2220b635297a20fb8ac974095805f391761c98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:05 -0600 Subject: board/puff/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9865cd94857b85db8f18195fd76bd9e6de0c50f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728848 Reviewed-by: Jeremy Bettis --- board/puff/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/puff/led.c b/board/puff/led.c index ba87f05460..ce21bd789a 100644 --- a/board/puff/led.c +++ b/board/puff/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From d23a6dc54953b7c6f177020be66cf400544d2b75 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:19 -0600 Subject: zephyr/shim/include/usbc/bc12_rt1739.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie5922199449d795b72b152590057a15de784e382 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730850 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/bc12_rt1739.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/bc12_rt1739.h b/zephyr/shim/include/usbc/bc12_rt1739.h index 3347d7d717..15df73857a 100644 --- a/zephyr/shim/include/usbc/bc12_rt1739.h +++ b/zephyr/shim/include/usbc/bc12_rt1739.h @@ -7,4 +7,7 @@ #define RT1739_BC12_COMPAT richtek_rt1739_bc12 -#define BC12_CHIP_RT1739(id) { .drv = &rt1739_bc12_drv, }, +#define BC12_CHIP_RT1739(id) \ + { \ + .drv = &rt1739_bc12_drv, \ + }, -- cgit v1.2.1 From 83a7c3bfbe28bb93d4a490799422932f980c63b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:03 -0600 Subject: test/printf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie10f826042f3fa01b6f59497e7c100fe924434fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730531 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/printf.c | 181 +++++++++++++++++++++++++++------------------------------- 1 file changed, 85 insertions(+), 96 deletions(-) diff --git a/test/printf.c b/test/printf.c index f7e9b9dd2d..83d03c210f 100644 --- a/test/printf.c +++ b/test/printf.c @@ -18,8 +18,7 @@ static const char err_str[] = "ERROR"; static char output[1024]; -int run(int expect_ret, const char *expect, - bool output_null, size_t size_limit, +int run(int expect_ret, const char *expect, bool output_null, size_t size_limit, const char *format, va_list args) { size_t expect_size = expect ? strlen(expect) + 1 : 0; @@ -34,10 +33,8 @@ int run(int expect_ret, const char *expect, TEST_ASSERT(expect_size <= size_limit); memset(output, INIT_VALUE, sizeof(output)); - rv = vsnprintf(output_null ? NULL : output, size_limit, - format, args); - ccprintf("received='%.*s' | ret =%d\n", - 30, output, rv); + rv = vsnprintf(output_null ? NULL : output, size_limit, format, args); + ccprintf("received='%.*s' | ret =%d\n", 30, output, rv); TEST_ASSERT_ARRAY_EQ(output, expect, expect_size); TEST_ASSERT_MEMSET(&output[expect_size], INIT_VALUE, @@ -59,41 +56,36 @@ int expect_success(const char *expect, const char *format, ...) int rv; va_start(args, format); - rv = run(EC_SUCCESS, expect, - false, sizeof(output), - format, args); + rv = run(EC_SUCCESS, expect, false, sizeof(output), format, args); va_end(args); return rv; } -int expect(int expect_ret, const char *expect, - bool output_null, size_t size_limit, - const char *format, ...) +int expect(int expect_ret, const char *expect, bool output_null, + size_t size_limit, const char *format, ...) { va_list args; int rv; va_start(args, format); - rv = run(expect_ret, expect, - output_null, size_limit, - format, args); + rv = run(expect_ret, expect, output_null, size_limit, format, args); va_end(args); return rv; } -#define T(n) \ - do { \ - int rv = (n); \ - if (rv != EC_SUCCESS) \ - return rv; \ +#define T(n) \ + do { \ + int rv = (n); \ + if (rv != EC_SUCCESS) \ + return rv; \ } while (0) test_static int test_vsnprintf_args(void) { - T(expect_success("", "")); - T(expect_success("a", "a")); + T(expect_success("", "")); + T(expect_success("a", "a")); T(expect(/* expect an invalid args error */ EC_ERROR_INVAL, NO_BYTES_TOUCHED, @@ -122,17 +114,17 @@ test_static int test_vsnprintf_args(void) test_static int test_vsnprintf_int(void) { - T(expect_success("123", "%d", 123)); - T(expect_success("-123", "%d", -123)); - T(expect_success("+123", "%+d", 123)); - T(expect_success("-123", "%+d", -123)); - T(expect_success("123", "%-d", 123)); - T(expect_success("-123", "%-d", -123)); - - T(expect_success(" 123", "%5d", 123)); - T(expect_success(" +123", "%+5d", 123)); - T(expect_success("00123", "%05d", 123)); - T(expect_success("00123", "%005d", 123)); + T(expect_success("123", "%d", 123)); + T(expect_success("-123", "%d", -123)); + T(expect_success("+123", "%+d", 123)); + T(expect_success("-123", "%+d", -123)); + T(expect_success("123", "%-d", 123)); + T(expect_success("-123", "%-d", -123)); + + T(expect_success(" 123", "%5d", 123)); + T(expect_success(" +123", "%+5d", 123)); + T(expect_success("00123", "%05d", 123)); + T(expect_success("00123", "%005d", 123)); /* * TODO(crbug.com/974084): This odd behavior should be fixed. * T(expect_success("+0123", "%+05d", 123)); @@ -141,56 +133,56 @@ test_static int test_vsnprintf_int(void) * Actual: "0+123" */ - T(expect_success(" 123", "%*d", 5, 123)); - T(expect_success(" +123", "%+*d", 5, 123)); - T(expect_success("00123", "%0*d", 5, 123)); + T(expect_success(" 123", "%*d", 5, 123)); + T(expect_success(" +123", "%+*d", 5, 123)); + T(expect_success("00123", "%0*d", 5, 123)); /* * TODO(crbug.com/974084): This odd behavior should be fixed. * T(expect_success("00123", "%00*d", 5, 123)); * Actual: "ERROR" */ - T(expect_success("0+123", "%+0*d", 5, 123)); + T(expect_success("0+123", "%+0*d", 5, 123)); /* * TODO(crbug.com/974084): This odd behavior should be fixed. * T(expect_success("0+123", "%+00*d", 5, 123)); * Actual: "ERROR" */ - T(expect_success("123 ", "%-5d", 123)); - T(expect_success("+123 ", "%-+5d", 123)); - T(expect_success(err_str, "%+-5d", 123)); - T(expect_success("123 ", "%-05d", 123)); - T(expect_success("123 ", "%-005d", 123)); - T(expect_success("+123 ", "%-+05d", 123)); - T(expect_success("+123 ", "%-+005d", 123)); - - T(expect_success("0.00123", "%.5d", 123)); - T(expect_success("+0.00123", "%+.5d", 123)); - T(expect_success("0.00123", "%7.5d", 123)); - T(expect_success(" 0.00123", "%9.5d", 123)); - T(expect_success(" +0.00123", "%+9.5d", 123)); - - T(expect_success("123", "%u", 123)); - T(expect_success("4294967295", "%u", -1)); + T(expect_success("123 ", "%-5d", 123)); + T(expect_success("+123 ", "%-+5d", 123)); + T(expect_success(err_str, "%+-5d", 123)); + T(expect_success("123 ", "%-05d", 123)); + T(expect_success("123 ", "%-005d", 123)); + T(expect_success("+123 ", "%-+05d", 123)); + T(expect_success("+123 ", "%-+005d", 123)); + + T(expect_success("0.00123", "%.5d", 123)); + T(expect_success("+0.00123", "%+.5d", 123)); + T(expect_success("0.00123", "%7.5d", 123)); + T(expect_success(" 0.00123", "%9.5d", 123)); + T(expect_success(" +0.00123", "%+9.5d", 123)); + + T(expect_success("123", "%u", 123)); + T(expect_success("4294967295", "%u", -1)); T(expect_success("18446744073709551615", "%llu", (uint64_t)-1)); - T(expect_success("0", "%x", 0)); - T(expect_success("0", "%X", 0)); - T(expect_success("5e", "%x", 0X5E)); - T(expect_success("5E", "%X", 0X5E)); + T(expect_success("0", "%x", 0)); + T(expect_success("0", "%X", 0)); + T(expect_success("5e", "%x", 0X5E)); + T(expect_success("5E", "%X", 0X5E)); /* * %l is deprecated on 32-bit systems (see crbug.com/984041), but is * is still functional on 64-bit systems. */ if (sizeof(long) == sizeof(uint32_t)) { - T(expect_success(err_str, "%lx", 0x7b)); - T(expect_success(err_str, "%08lu", 0x7b)); - T(expect_success("13ERROR", "%d%lu", 13, 14)); + T(expect_success(err_str, "%lx", 0x7b)); + T(expect_success(err_str, "%08lu", 0x7b)); + T(expect_success("13ERROR", "%d%lu", 13, 14)); } else { - T(expect_success("7b", "%lx", 0x7b)); - T(expect_success("00000123", "%08lu", 123)); - T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); + T(expect_success("7b", "%lx", 0x7b)); + T(expect_success("00000123", "%08lu", 123)); + T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); } return EC_SUCCESS; @@ -201,22 +193,19 @@ test_static int test_vsnprintf_pointers(void) void *ptr = (void *)0x55005E00; unsigned int val = 0; - T(expect_success("55005e00", "%pP", ptr)); - T(expect_success(err_str, "%P", ptr)); + T(expect_success("55005e00", "%pP", ptr)); + T(expect_success(err_str, "%P", ptr)); /* %p by itself is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, - false, 0, "%p")); + T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%p")); /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, - false, 0, "%p ")); + T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%p ")); /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, - false, 0, "%pQ")); + T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%pQ")); /* Test %pb, binary format */ - T(expect_success("0", "%pb", BINARY_VALUE(val, 0))); + T(expect_success("0", "%pb", BINARY_VALUE(val, 0))); val = 0x5E; - T(expect_success("1011110", "%pb", BINARY_VALUE(val, 0))); + T(expect_success("1011110", "%pb", BINARY_VALUE(val, 0))); T(expect_success("0000000001011110", "%pb", BINARY_VALUE(val, 16))); val = 0x12345678; T(expect_success("10010001101000101011001111000", "%pb", @@ -230,36 +219,36 @@ test_static int test_vsnprintf_pointers(void) test_static int test_vsnprintf_chars(void) { - T(expect_success("a", "%c", 'a')); - T(expect_success("*", "%c", '*')); + T(expect_success("a", "%c", 'a')); + T(expect_success("*", "%c", '*')); return EC_SUCCESS; } test_static int test_vsnprintf_strings(void) { - T(expect_success("abc", "%s", "abc")); - T(expect_success(" abc", "%5s", "abc")); - T(expect_success("abc", "%0s", "abc")); - T(expect_success("abc ", "%-5s", "abc")); - T(expect_success("abc", "%*s", 0, "abc")); - T(expect_success("a", "%.1s", "abc")); - T(expect_success("a", "%.*s", 1, "abc")); - T(expect_success("", "%.0s", "abc")); - T(expect_success("", "%.*s", 0, "abc")); + T(expect_success("abc", "%s", "abc")); + T(expect_success(" abc", "%5s", "abc")); + T(expect_success("abc", "%0s", "abc")); + T(expect_success("abc ", "%-5s", "abc")); + T(expect_success("abc", "%*s", 0, "abc")); + T(expect_success("a", "%.1s", "abc")); + T(expect_success("a", "%.*s", 1, "abc")); + T(expect_success("", "%.0s", "abc")); + T(expect_success("", "%.*s", 0, "abc")); /* * TODO(crbug.com/974084): * Ignoring the padding parameter is slightly * odd behavior and could use a review. */ - T(expect_success("ab", "%5.2s", "abc")); - T(expect_success("abc", "%.4s", "abc")); + T(expect_success("ab", "%5.2s", "abc")); + T(expect_success("abc", "%.4s", "abc")); /* * Given a malformed string (address 0x1 is a good example), * if we ask for zero precision, expect no bytes to be read * from the malformed address and a blank output string. */ - T(expect_success("", "%.0s", (char *)1)); + T(expect_success("", "%.0s", (char *)1)); return EC_SUCCESS; } @@ -268,28 +257,28 @@ test_static int test_vsnprintf_timestamps(void) { uint64_t ts = 0; - T(expect_success("0.000000", "%pT", &ts)); + T(expect_success("0.000000", "%pT", &ts)); ts = 123456; - T(expect_success("0.123456", "%pT", &ts)); + T(expect_success("0.123456", "%pT", &ts)); ts = 9999999000000; - T(expect_success("9999999.000000", "%pT", &ts)); + T(expect_success("9999999.000000", "%pT", &ts)); return EC_SUCCESS; } test_static int test_vsnprintf_hexdump(void) { - const char bytes[] = {0x00, 0x5E}; + const char bytes[] = { 0x00, 0x5E }; - T(expect_success("005e", "%ph", HEX_BUF(bytes, 2))); - T(expect_success("", "%ph", HEX_BUF(bytes, 0))); - T(expect_success("00", "%ph", HEX_BUF(bytes, 1))); + T(expect_success("005e", "%ph", HEX_BUF(bytes, 2))); + T(expect_success("", "%ph", HEX_BUF(bytes, 0))); + T(expect_success("00", "%ph", HEX_BUF(bytes, 1))); return EC_SUCCESS; } test_static int test_vsnprintf_combined(void) { - T(expect_success("abc", "%c%s", 'a', "bc")); - T(expect_success("12\tbc", "%d\t%s", 12, "bc")); + T(expect_success("abc", "%c%s", 'a', "bc")); + T(expect_success("12\tbc", "%d\t%s", 12, "bc")); return EC_SUCCESS; } -- cgit v1.2.1 From f338039e5060778f99332ec435c8ecb004cf9a1c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:14 -0600 Subject: test/rollback_entropy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I02b52e8d9b291c5196ab22ee96748b3f5b36da18 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730534 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/rollback_entropy.c | 46 +++++++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/test/rollback_entropy.c b/test/rollback_entropy.c index 788fab2572..ce846e80a5 100644 --- a/test/rollback_entropy.c +++ b/test/rollback_entropy.c @@ -12,9 +12,7 @@ static const uint32_t VALID_ROLLBACK_COOKIE = 0x0b112233; static const uint32_t UNINITIALIZED_ROLLBACK_COOKIE = 0xffffffff; -static const uint8_t FAKE_ENTROPY[] = { - 0xff, 0xff, 0xff, 0xff -}; +static const uint8_t FAKE_ENTROPY[] = { 0xff, 0xff, 0xff, 0xff }; /* * Generated by concatenating 32-bytes (256-bits) of zeros with the 4 bytes @@ -26,13 +24,12 @@ static const uint8_t FAKE_ENTROPY[] = { * * 890ed82cf09f22243bdc4252e4d79c8a9810c1391f455dce37a7b732eb0a0e4f */ -#define EXPECTED_SECRET \ - 0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42, \ - 0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, 0x45, \ - 0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, 0x4f -__maybe_unused static const uint8_t _EXPECTED_SECRET[] = { - EXPECTED_SECRET -}; +#define EXPECTED_SECRET \ + 0x89, 0x0e, 0xd8, 0x2c, 0xf0, 0x9f, 0x22, 0x24, 0x3b, 0xdc, 0x42, \ + 0x52, 0xe4, 0xd7, 0x9c, 0x8a, 0x98, 0x10, 0xc1, 0x39, 0x1f, \ + 0x45, 0x5d, 0xce, 0x37, 0xa7, 0xb7, 0x32, 0xeb, 0x0a, 0x0e, \ + 0x4f +__maybe_unused static const uint8_t _EXPECTED_SECRET[] = { EXPECTED_SECRET }; BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE); /* @@ -45,22 +42,20 @@ BUILD_ASSERT(sizeof(_EXPECTED_SECRET) == CONFIG_ROLLBACK_SECRET_SIZE); * * b5d2c08b1f9109ac5c67de15486f0ac267ef9501bd9f646f4ea80085cb08284c */ -#define EXPECTED_SECRET2 \ - 0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde, \ - 0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, 0x9f, \ - 0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, 0x4c -__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = { - EXPECTED_SECRET2 -}; +#define EXPECTED_SECRET2 \ + 0xb5, 0xd2, 0xc0, 0x8b, 0x1f, 0x91, 0x09, 0xac, 0x5c, 0x67, 0xde, \ + 0x15, 0x48, 0x6f, 0x0a, 0xc2, 0x67, 0xef, 0x95, 0x01, 0xbd, \ + 0x9f, 0x64, 0x6f, 0x4e, 0xa8, 0x00, 0x85, 0xcb, 0x08, 0x28, \ + 0x4c +__maybe_unused static const uint8_t _EXPECTED_SECRET2[] = { EXPECTED_SECRET2 }; BUILD_ASSERT(sizeof(_EXPECTED_SECRET2) == CONFIG_ROLLBACK_SECRET_SIZE); -#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET \ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -__maybe_unused static const uint8_t -_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = { +#define EXPECTED_UNINITIALIZED_ROLLBACK_SECRET \ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, \ + 0xff, +__maybe_unused static const uint8_t _EXPECTED_UNINITIALIZED_ROLLBACK_SECRET[] = { EXPECTED_UNINITIALIZED_ROLLBACK_SECRET }; BUILD_ASSERT(sizeof(_EXPECTED_UNINITIALIZED_ROLLBACK_SECRET) == @@ -143,7 +138,8 @@ test_static int test_add_entropy(void) /* Immediately after boot region 1 should not yet be initialized. */ rv = read_rollback(1, &rb_data); TEST_EQ(rv, EC_SUCCESS, "%d"); - TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS, "%d"); + TEST_EQ(check_equal(&rb_data, &expected_uninitialized), EC_SUCCESS, + "%d"); /* * Add entropy. The result should end up being written to the unused -- cgit v1.2.1 From b1383e15f97a31d5fc939c6e79208efb9ca9398d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:16 -0600 Subject: driver/charger/sm5803.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia09b2f37c60837c7cd6da3183bbafff7303bddd1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729941 Reviewed-by: Jeremy Bettis --- driver/charger/sm5803.h | 494 ++++++++++++++++++++++++------------------------ 1 file changed, 246 insertions(+), 248 deletions(-) diff --git a/driver/charger/sm5803.h b/driver/charger/sm5803.h index b7638411e4..5a03ce37d4 100644 --- a/driver/charger/sm5803.h +++ b/driver/charger/sm5803.h @@ -11,92 +11,92 @@ #include "common.h" /* Note: configure charger struct with CHARGER_FLAGS */ -#define SM5803_ADDR_MAIN_FLAGS 0x30 -#define SM5803_ADDR_MEAS_FLAGS 0x31 -#define SM5803_ADDR_CHARGER_FLAGS 0x32 -#define SM5803_ADDR_TEST_FLAGS 0x37 +#define SM5803_ADDR_MAIN_FLAGS 0x30 +#define SM5803_ADDR_MEAS_FLAGS 0x31 +#define SM5803_ADDR_CHARGER_FLAGS 0x32 +#define SM5803_ADDR_TEST_FLAGS 0x37 /* Main registers (address 0x30) */ -#define SM5803_REG_CHIP_ID 0x00 - -#define SM5803_REG_STATUS1 0x01 -#define SM5803_STATUS1_VSYS_OK BIT(0) -#define SM5803_STATUS1_VPWR_OK BIT(1) -#define SM5803_STATUS1_VBUS_UVL BIT(3) -#define SM5803_STATUS1_VBUS_SHORT BIT(4) -#define SM5803_STATUS1_VBUS_OVH BIT(5) -#define SM5803_STATUS1_CHG_DET BIT(6) -#define SM5803_STATUS1_BAT_DET BIT(7) - -#define SM5803_REG_STATUS2 0x02 -#define SM5803_STATUS2_BAT_DET_FG BIT(1) -#define SM5803_STATUS2_VBAT_SHORT BIT(0) - -#define SM5803_REG_INT1_REQ 0x05 -#define SM5803_REG_INT1_EN 0x0A -#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT BIT(0) -#define SM5803_INT1_CHG BIT(2) -#define SM5803_INT1_BAT BIT(3) -#define SM5803_INT1_CLS_OC BIT(4) -#define SM5803_INT1_SLV_DET BIT(5) -#define SM5803_INT1_SWL_DISCH BIT(6) -#define SM5803_INT1_PREREG BIT(7) - -#define SM5803_REG_INT2_REQ 0x06 -#define SM5803_REG_INT2_EN 0x0B -#define SM5803_INT2_VBATSNSP BIT(0) -#define SM5803_INT2_IBAT_DISCHG BIT(1) -#define SM5803_INT2_IBAT_CHG BIT(2) -#define SM5803_INT2_IBUS BIT(3) -#define SM5803_INT2_VBUS BIT(4) -#define SM5803_INT2_VCHGPWR BIT(5) -#define SM5803_INT2_VSYS BIT(6) -#define SM5803_INT2_TINT BIT(7) - -#define SM5803_REG_INT3_REQ 0x07 -#define SM5803_REG_INT3_EN 0x0C -#define SM5803_INT3_GPADC0 BIT(0) -#define SM5803_INT3_BFET_PWR_LIMIT BIT(1) -#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT BIT(2) -#define SM5803_INT3_SPARE BIT(3) -#define SM5803_INT3_VBUS_PWR_LIMIT BIT(4) -#define SM5803_INT3_IBAT BIT(5) - -#define SM5803_REG_INT4_REQ 0x08 -#define SM5803_REG_INT4_EN 0x0D -#define SM5803_INT4_CHG_FAIL BIT(0) -#define SM5803_INT4_CHG_DONE BIT(1) -#define SM5803_INT4_CHG_START BIT(2) -#define SM5803_INT4_SLP_EXIT BIT(3) -#define SM5803_INT4_OTG_FAIL BIT(4) -#define SM5803_INT4_CHG_ILIM BIT(5) -#define SM5803_INT4_IBAT_CC BIT(6) -#define SM5803_INT4_CC BIT(7) - -#define SM5803_REG_MISC_CONFIG 0x15 -#define SM5803_MISC_INV_INT BIT(0) -#define SM5803_INT_CLEAR_MODE BIT(1) -#define SM5803_INT_MASK_MODE BIT(2) - -#define SM5803_REG_PLATFORM 0x18 -#define SM5803_PLATFORM_ID GENMASK(4, 0) - -#define SM5803_REG_REFERENCE 0x20 -#define SM5803_REFERENCE_LDO3P3_PGOOD BIT(4) -#define SM5803_REFERENCE_LDO5_PGOOD BIT(5) - -#define SM5803_REG_CLOCK_SEL 0x2A -#define SM5803_CLOCK_SEL_LOW BIT(0) - -#define SM5803_REG_GPIO0_CTRL 0x30 -#define SM5803_GPIO0_VAL BIT(0) -#define SM5803_GPIO0_MODE_MASK GENMASK(2, 1) -#define SM5803_GPIO0_OPEN_DRAIN_EN BIT(6) -#define SM5803_CHG_DET_OPEN_DRAIN_EN BIT(7) - -#define SM5803_REG_VBATSNSP_MEAS_MSB 0x40 -#define SM5803_REG_VBATSNSP_MEAS_LSB 0x41 +#define SM5803_REG_CHIP_ID 0x00 + +#define SM5803_REG_STATUS1 0x01 +#define SM5803_STATUS1_VSYS_OK BIT(0) +#define SM5803_STATUS1_VPWR_OK BIT(1) +#define SM5803_STATUS1_VBUS_UVL BIT(3) +#define SM5803_STATUS1_VBUS_SHORT BIT(4) +#define SM5803_STATUS1_VBUS_OVH BIT(5) +#define SM5803_STATUS1_CHG_DET BIT(6) +#define SM5803_STATUS1_BAT_DET BIT(7) + +#define SM5803_REG_STATUS2 0x02 +#define SM5803_STATUS2_BAT_DET_FG BIT(1) +#define SM5803_STATUS2_VBAT_SHORT BIT(0) + +#define SM5803_REG_INT1_REQ 0x05 +#define SM5803_REG_INT1_EN 0x0A +#define SM5803_INT1_VBUS_PWR_HWSAFE_LIMIT BIT(0) +#define SM5803_INT1_CHG BIT(2) +#define SM5803_INT1_BAT BIT(3) +#define SM5803_INT1_CLS_OC BIT(4) +#define SM5803_INT1_SLV_DET BIT(5) +#define SM5803_INT1_SWL_DISCH BIT(6) +#define SM5803_INT1_PREREG BIT(7) + +#define SM5803_REG_INT2_REQ 0x06 +#define SM5803_REG_INT2_EN 0x0B +#define SM5803_INT2_VBATSNSP BIT(0) +#define SM5803_INT2_IBAT_DISCHG BIT(1) +#define SM5803_INT2_IBAT_CHG BIT(2) +#define SM5803_INT2_IBUS BIT(3) +#define SM5803_INT2_VBUS BIT(4) +#define SM5803_INT2_VCHGPWR BIT(5) +#define SM5803_INT2_VSYS BIT(6) +#define SM5803_INT2_TINT BIT(7) + +#define SM5803_REG_INT3_REQ 0x07 +#define SM5803_REG_INT3_EN 0x0C +#define SM5803_INT3_GPADC0 BIT(0) +#define SM5803_INT3_BFET_PWR_LIMIT BIT(1) +#define SM5803_INT3_BFET_PWR_HWSAFE_LIMIT BIT(2) +#define SM5803_INT3_SPARE BIT(3) +#define SM5803_INT3_VBUS_PWR_LIMIT BIT(4) +#define SM5803_INT3_IBAT BIT(5) + +#define SM5803_REG_INT4_REQ 0x08 +#define SM5803_REG_INT4_EN 0x0D +#define SM5803_INT4_CHG_FAIL BIT(0) +#define SM5803_INT4_CHG_DONE BIT(1) +#define SM5803_INT4_CHG_START BIT(2) +#define SM5803_INT4_SLP_EXIT BIT(3) +#define SM5803_INT4_OTG_FAIL BIT(4) +#define SM5803_INT4_CHG_ILIM BIT(5) +#define SM5803_INT4_IBAT_CC BIT(6) +#define SM5803_INT4_CC BIT(7) + +#define SM5803_REG_MISC_CONFIG 0x15 +#define SM5803_MISC_INV_INT BIT(0) +#define SM5803_INT_CLEAR_MODE BIT(1) +#define SM5803_INT_MASK_MODE BIT(2) + +#define SM5803_REG_PLATFORM 0x18 +#define SM5803_PLATFORM_ID GENMASK(4, 0) + +#define SM5803_REG_REFERENCE 0x20 +#define SM5803_REFERENCE_LDO3P3_PGOOD BIT(4) +#define SM5803_REFERENCE_LDO5_PGOOD BIT(5) + +#define SM5803_REG_CLOCK_SEL 0x2A +#define SM5803_CLOCK_SEL_LOW BIT(0) + +#define SM5803_REG_GPIO0_CTRL 0x30 +#define SM5803_GPIO0_VAL BIT(0) +#define SM5803_GPIO0_MODE_MASK GENMASK(2, 1) +#define SM5803_GPIO0_OPEN_DRAIN_EN BIT(6) +#define SM5803_CHG_DET_OPEN_DRAIN_EN BIT(7) + +#define SM5803_REG_VBATSNSP_MEAS_MSB 0x40 +#define SM5803_REG_VBATSNSP_MEAS_LSB 0x41 enum sm5803_gpio0_modes { GPIO0_MODE_PROCHOT, @@ -104,14 +104,14 @@ enum sm5803_gpio0_modes { GPIO0_MODE_INPUT }; -#define SM5803_REG_BFET_PWR_MAX_TH 0x35 -#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH 0x36 +#define SM5803_REG_BFET_PWR_MAX_TH 0x35 +#define SM5803_REG_BFET_PWR_HWSAFE_MAX_TH 0x36 -#define SM5803_REG_PORTS_CTRL 0x40 -#define SM5803_PORTS_VBUS_DISCH BIT(0) -#define SM5803_PORTS_VBUS_PULLDOWN BIT(1) -#define SM5803_PORTS_VBUS_SNS_DISCH BIT(2) -#define SM5803_PORTS_VBUS_SNS_PULLDOWN BIT(3) +#define SM5803_REG_PORTS_CTRL 0x40 +#define SM5803_PORTS_VBUS_DISCH BIT(0) +#define SM5803_PORTS_VBUS_PULLDOWN BIT(1) +#define SM5803_PORTS_VBUS_SNS_DISCH BIT(2) +#define SM5803_PORTS_VBUS_SNS_PULLDOWN BIT(3) /* ADC Registers (address 0x31) */ @@ -119,48 +119,46 @@ enum sm5803_gpio0_modes { * Note: Some register bits must be enabled for the DC-DC converter to properly * handle transitions. */ -#define SM5803_REG_GPADC_CONFIG1 0x01 -#define SM5803_GPADCC1_VBATSNSP_EN BIT(0) -#define SM5803_GPADCC1_IBAT_DIS_EN BIT(1) -#define SM5803_GPADCC1_IBAT_CHG_EN BIT(2) -#define SM5803_GPADCC1_IBUS_EN BIT(3) -#define SM5803_GPADCC1_VBUS_EN BIT(4) -#define SM5803_GPADCC1_VCHGPWR_EN BIT(5) /* NOTE: DO NOT CLEAR */ -#define SM5803_GPADCC1_VSYS_EN BIT(6) /* NOTE: DO NOT CLEAR */ -#define SM5803_GPADCC1_TINT_EN BIT(7) +#define SM5803_REG_GPADC_CONFIG1 0x01 +#define SM5803_GPADCC1_VBATSNSP_EN BIT(0) +#define SM5803_GPADCC1_IBAT_DIS_EN BIT(1) +#define SM5803_GPADCC1_IBAT_CHG_EN BIT(2) +#define SM5803_GPADCC1_IBUS_EN BIT(3) +#define SM5803_GPADCC1_VBUS_EN BIT(4) +#define SM5803_GPADCC1_VCHGPWR_EN BIT(5) /* NOTE: DO NOT CLEAR */ +#define SM5803_GPADCC1_VSYS_EN BIT(6) /* NOTE: DO NOT CLEAR */ +#define SM5803_GPADCC1_TINT_EN BIT(7) -#define SM5803_REG_GPADC_CONFIG2 0x02 +#define SM5803_REG_GPADC_CONFIG2 0x02 -#define SM5803_REG_PSYS1 0x04 -#define SM5803_PSYS1_DAC_EN BIT(0) +#define SM5803_REG_PSYS1 0x04 +#define SM5803_PSYS1_DAC_EN BIT(0) /* Note: Threshold registers all assume lower 2 bits are 0 */ -#define SM5803_REG_VBUS_LOW_TH 0x1A -#define SM5803_REG_VBATSNSP_MAX_TH 0x26 -#define SM5803_REG_VBUS_HIGH_TH 0x2A -#define SM5803_REG_VCHG_PWR_LOW_TH 0x1B -#define SM5803_REG_VCHG_PWR_HIGH_TH 0x2B -#define SM5803_REG_TINT_LOW_TH 0x1D -#define SM5803_REG_TINT_HIGH_TH 0x2D +#define SM5803_REG_VBUS_LOW_TH 0x1A +#define SM5803_REG_VBATSNSP_MAX_TH 0x26 +#define SM5803_REG_VBUS_HIGH_TH 0x2A +#define SM5803_REG_VCHG_PWR_LOW_TH 0x1B +#define SM5803_REG_VCHG_PWR_HIGH_TH 0x2B +#define SM5803_REG_TINT_LOW_TH 0x1D +#define SM5803_REG_TINT_HIGH_TH 0x2D /* * Vbus levels increment in 23.4 mV, set thresholds to below 3.5V and above 4.0V * to mirror what TCPCI uses for Vbus present indication */ -#define SM5803_VBUS_LOW_LEVEL 0x25 -#define SM5803_VBUS_HIGH_LEVEL 0x2C - - +#define SM5803_VBUS_LOW_LEVEL 0x25 +#define SM5803_VBUS_HIGH_LEVEL 0x2C /* * TINT thresholds. TINT steps are in 0.43 K with the upper threshold set to * 360 K and lower threshold to de-assert PROCHOT at 330 K. */ -#define SM5803_TINT_LOW_LEVEL 0xBF -#define SM5803_TINT_HIGH_LEVEL 0xD1 +#define SM5803_TINT_LOW_LEVEL 0xBF +#define SM5803_TINT_HIGH_LEVEL 0xD1 -#define SM5803_TINT_MAX_LEVEL 0xFF -#define SM5803_TINT_MIN_LEVEL 0x00 +#define SM5803_TINT_MAX_LEVEL 0xFF +#define SM5803_TINT_MIN_LEVEL 0x00 /* * Set minimum thresholds for VBUS_PWR_LOW_TH interrupt generation @@ -179,47 +177,47 @@ enum sm5803_gpio0_modes { #define SM5803_VBAT_SNSP_MAXTH_2S_LEVEL 0xDC /* IBAT levels - The IBAT levels increment in 7.32mA */ -#define SM5803_REG_IBAT_CHG_MEAS_MSB 0x44 -#define SM5803_REG_IBAT_CHG_MEAS_LSB 0x45 -#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB 0xC4 -#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB 0xC5 -#define SM5803_IBAT_CHG_MEAS_LSB GENMASK(1, 0) +#define SM5803_REG_IBAT_CHG_MEAS_MSB 0x44 +#define SM5803_REG_IBAT_CHG_MEAS_LSB 0x45 +#define SM5803_REG_IBAT_CHG_AVG_MEAS_MSB 0xC4 +#define SM5803_REG_IBAT_CHG_AVG_MEAS_LSB 0xC5 +#define SM5803_IBAT_CHG_MEAS_LSB GENMASK(1, 0) /* IBUS levels - The IBUS levels increment in 7.32mA */ -#define SM5803_REG_IBUS_CHG_MEAS_MSB 0x46 -#define SM5803_REG_IBUS_CHG_MEAS_LSB 0x47 -#define SM5803_IBUS_CHG_MEAS_LSB GENMASK(1, 0) - -#define SM5803_REG_VBUS_MEAS_MSB 0x48 -#define SM5803_REG_VBUS_MEAS_LSB 0x49 -#define SM5803_VBUS_MEAS_LSB GENMASK(1, 0) -#define SM5803_VBUS_MEAS_BAT_DET BIT(2) -#define SM5803_VBUS_MEAS_VBUS_SHORT BIT(4) -#define SM5803_VBUS_MEAS_OV_TEMP BIT(5) -#define SM5803_VBUS_MEAS_CHG_DET BIT(6) +#define SM5803_REG_IBUS_CHG_MEAS_MSB 0x46 +#define SM5803_REG_IBUS_CHG_MEAS_LSB 0x47 +#define SM5803_IBUS_CHG_MEAS_LSB GENMASK(1, 0) + +#define SM5803_REG_VBUS_MEAS_MSB 0x48 +#define SM5803_REG_VBUS_MEAS_LSB 0x49 +#define SM5803_VBUS_MEAS_LSB GENMASK(1, 0) +#define SM5803_VBUS_MEAS_BAT_DET BIT(2) +#define SM5803_VBUS_MEAS_VBUS_SHORT BIT(4) +#define SM5803_VBUS_MEAS_OV_TEMP BIT(5) +#define SM5803_VBUS_MEAS_CHG_DET BIT(6) /* VCHGPWR levels - The VCHGPWR levels increment in 23.4mV steps. */ -#define SM5803_REG_VCHG_PWR_MSB 0x4A +#define SM5803_REG_VCHG_PWR_MSB 0x4A -#define SM5803_REG_TINT_MEAS_MSB 0x4E +#define SM5803_REG_TINT_MEAS_MSB 0x4E /* VSYS levels - The VSYS levels increment in 23.4mV steps. */ -#define SM5803_REG_VSYS_MEAS_MSB 0x4C -#define SM5803_REG_VSYS_MEAS_LSB 0x4D -#define SM5803_REG_VSYS_AVG_MEAS_MSB 0xCC -#define SM5803_REG_VSYS_AVG_MEAS_LSB 0xCD -#define SM5803_VSYS_MEAS_LSB GENMASK(1, 0) +#define SM5803_REG_VSYS_MEAS_MSB 0x4C +#define SM5803_REG_VSYS_MEAS_LSB 0x4D +#define SM5803_REG_VSYS_AVG_MEAS_MSB 0xCC +#define SM5803_REG_VSYS_AVG_MEAS_LSB 0xCD +#define SM5803_VSYS_MEAS_LSB GENMASK(1, 0) /* Charger registers (address 0x32) */ -#define SM5803_REG_CC_CONFIG1 0x01 -#define SM5803_CC_CONFIG1_SD_PWRUP BIT(3) +#define SM5803_REG_CC_CONFIG1 0x01 +#define SM5803_CC_CONFIG1_SD_PWRUP BIT(3) -#define SM5803_REG_FLOW1 0x1C -#define SM5803_FLOW1_MODE GENMASK(1, 0) -#define SM5803_FLOW1_DIRECTCHG_SRC_EN BIT(2) -#define SM5803_FLOW1_LINEAR_CHARGE_EN BIT(3) -#define SM5803_FLOW1_USB_SUSP BIT(7) +#define SM5803_REG_FLOW1 0x1C +#define SM5803_FLOW1_MODE GENMASK(1, 0) +#define SM5803_FLOW1_DIRECTCHG_SRC_EN BIT(2) +#define SM5803_FLOW1_LINEAR_CHARGE_EN BIT(3) +#define SM5803_FLOW1_USB_SUSP BIT(7) enum sm5803_charger_modes { CHARGER_MODE_DISABLED, @@ -228,157 +226,157 @@ enum sm5803_charger_modes { CHARGER_MODE_SOURCE, }; -#define SM5803_REG_FLOW2 0x1D -#define SM5803_FLOW2_AUTO_TRKL_EN BIT(0) -#define SM5803_FLOW2_AUTO_PRECHG_EN BIT(1) -#define SM5803_FLOW2_AUTO_FASTCHG_EN BIT(2) -#define SM5803_FLOW2_AUTO_ENABLED GENMASK(2, 0) -#define SM5803_FLOW2_FW_TRKL_CMD BIT(3) -#define SM5803_FLOW2_FW_PRECHG_CMD BIT(4) -#define SM5803_FLOW2_FW_FASTCHG_CMD BIT(5) -#define SM5803_FLOW2_HOST_MODE_EN BIT(6) -#define SM5803_FLOW2_AUTO_CHGEN_SET BIT(7) - -#define SM5803_REG_FLOW3 0x1E -#define SM5803_FLOW3_SWITCH_BCK_BST BIT(0) -#define SM5803_FLOW3_FW_SWITCH_RESUME BIT(1) -#define SM5803_FLOW3_FW_SWITCH_PAUSE BIT(2) -#define SM5803_FLOW3_SOFT_DISABLE_EN BIT(3) - -#define SM5803_REG_SWITCHER_CONF 0x1F -#define SM5803_SW_BCK_BST_CONF_AUTO BIT(0) - -#define SM5803_REG_ANA_EN1 0x21 -#define SM5803_ANA_EN1_CLS_DISABLE BIT(7) +#define SM5803_REG_FLOW2 0x1D +#define SM5803_FLOW2_AUTO_TRKL_EN BIT(0) +#define SM5803_FLOW2_AUTO_PRECHG_EN BIT(1) +#define SM5803_FLOW2_AUTO_FASTCHG_EN BIT(2) +#define SM5803_FLOW2_AUTO_ENABLED GENMASK(2, 0) +#define SM5803_FLOW2_FW_TRKL_CMD BIT(3) +#define SM5803_FLOW2_FW_PRECHG_CMD BIT(4) +#define SM5803_FLOW2_FW_FASTCHG_CMD BIT(5) +#define SM5803_FLOW2_HOST_MODE_EN BIT(6) +#define SM5803_FLOW2_AUTO_CHGEN_SET BIT(7) + +#define SM5803_REG_FLOW3 0x1E +#define SM5803_FLOW3_SWITCH_BCK_BST BIT(0) +#define SM5803_FLOW3_FW_SWITCH_RESUME BIT(1) +#define SM5803_FLOW3_FW_SWITCH_PAUSE BIT(2) +#define SM5803_FLOW3_SOFT_DISABLE_EN BIT(3) + +#define SM5803_REG_SWITCHER_CONF 0x1F +#define SM5803_SW_BCK_BST_CONF_AUTO BIT(0) + +#define SM5803_REG_ANA_EN1 0x21 +#define SM5803_ANA_EN1_CLS_DISABLE BIT(7) /* * Input current limit is CHG_ILIM_RAW *100 mA */ -#define SM5803_REG_CHG_ILIM 0x24 -#define SM5803_CHG_ILIM_RAW GENMASK(4, 0) -#define SM5803_CURRENT_STEP 100 -#define SM5803_REG_TO_CURRENT(r) ((r) * SM5803_CURRENT_STEP) -#define SM5803_CURRENT_TO_REG(c) ((c) / SM5803_CURRENT_STEP) +#define SM5803_REG_CHG_ILIM 0x24 +#define SM5803_CHG_ILIM_RAW GENMASK(4, 0) +#define SM5803_CURRENT_STEP 100 +#define SM5803_REG_TO_CURRENT(r) ((r)*SM5803_CURRENT_STEP) +#define SM5803_CURRENT_TO_REG(c) ((c) / SM5803_CURRENT_STEP) /* * DPM Voltage loop regulation contains the 8 bits with MSB register * and the lower 3 bits with LSB register. * The regulation value is 2.72 V + DPM_VL_SET * 10mV */ -#define SM5803_REG_DPM_VL_SET_MSB 0x26 -#define SM5803_REG_DPM_VL_SET_LSB 0x27 +#define SM5803_REG_DPM_VL_SET_MSB 0x26 +#define SM5803_REG_DPM_VL_SET_LSB 0x27 /* * Output voltage uses the same equation as Vsys * Lower saturation value is 3 V, upper 20.5 V */ -#define SM5803_REG_VPWR_MSB 0x30 -#define SM5803_REG_DISCH_CONF2 0x31 -#define SM5803_DISCH_CONF5_VPWR_LSB GENMASK(2, 0) +#define SM5803_REG_VPWR_MSB 0x30 +#define SM5803_REG_DISCH_CONF2 0x31 +#define SM5803_DISCH_CONF5_VPWR_LSB GENMASK(2, 0) /* * Output current limit is CLS_LIMIT * 50 mA and saturates to 3.2 A */ -#define SM5803_REG_DISCH_CONF5 0x34 -#define SM5803_DISCH_CONF5_CLS_LIMIT GENMASK(6, 0) -#define SM5803_CLS_CURRENT_STEP 50 +#define SM5803_REG_DISCH_CONF5 0x34 +#define SM5803_DISCH_CONF5_CLS_LIMIT GENMASK(6, 0) +#define SM5803_CLS_CURRENT_STEP 50 -#define SM5803_REG_DISCH_CONF6 0x35 -#define SM5803_DISCH_CONF6_RAMPS_DIS BIT(0) -#define SM5803_DISCH_CONF6_SMOOTH_DIS BIT(1) +#define SM5803_REG_DISCH_CONF6 0x35 +#define SM5803_DISCH_CONF6_RAMPS_DIS BIT(0) +#define SM5803_DISCH_CONF6_SMOOTH_DIS BIT(1) /* * Vsys is 11 bits, with the lower 3 bits in the LSB register. * The pre-regulation value is 2.72 V + Vsys_prereg * 10 mV * Lower saturation value is 3V, upper is 20V */ -#define SM5803_REG_VSYS_PREREG_MSB 0x36 -#define SM5803_REG_VSYS_PREREG_LSB 0x37 -#define SM5803_VOLTAGE_STEP 10 -#define SM5803_VOLTAGE_SHIFT 2720 -#define SM5803_REG_TO_VOLTAGE(r) (SM5803_VOLTAGE_SHIFT + \ - (r) * SM5803_VOLTAGE_STEP) -#define SM5803_VOLTAGE_TO_REG(v) (((v) - SM5803_VOLTAGE_SHIFT) \ - / SM5803_VOLTAGE_STEP) +#define SM5803_REG_VSYS_PREREG_MSB 0x36 +#define SM5803_REG_VSYS_PREREG_LSB 0x37 +#define SM5803_VOLTAGE_STEP 10 +#define SM5803_VOLTAGE_SHIFT 2720 +#define SM5803_REG_TO_VOLTAGE(r) \ + (SM5803_VOLTAGE_SHIFT + (r)*SM5803_VOLTAGE_STEP) +#define SM5803_VOLTAGE_TO_REG(v) \ + (((v)-SM5803_VOLTAGE_SHIFT) / SM5803_VOLTAGE_STEP) /* * Precharge Termination threshold. */ -#define SM5803_REG_PRE_FAST_CONF_REG1 0x39 -#define SM5803_VBAT_PRE_TERM_MIN_DV 23 +#define SM5803_REG_PRE_FAST_CONF_REG1 0x39 +#define SM5803_VBAT_PRE_TERM_MIN_DV 23 /* 3.8V+ gets rounded to 4V */ -#define SM5803_VBAT_PRE_TERM_MAX_DV 38 -#define SM5803_VBAT_PRE_TERM GENMASK(7, 4) -#define SM5803_VBAT_PRE_TERM_SHIFT 4 +#define SM5803_VBAT_PRE_TERM_MAX_DV 38 +#define SM5803_VBAT_PRE_TERM GENMASK(7, 4) +#define SM5803_VBAT_PRE_TERM_SHIFT 4 /* * Vbat for fast charge uses the same equation as Vsys * Lower saturation value is 3V, upper is dependent on number of cells */ -#define SM5803_REG_VBAT_FAST_MSB 0x3A -#define SM5803_REG_VBAT_FAST_LSB 0x3B +#define SM5803_REG_VBAT_FAST_MSB 0x3A +#define SM5803_REG_VBAT_FAST_LSB 0x3B /* * Fast charge current limit is ICHG_FAST * 100 mA * Value read back may be adjusted if tempearture limits are exceeded */ -#define SM5803_REG_FAST_CONF4 0x3C -#define SM5803_CONF4_ICHG_FAST GENMASK(5, 0) +#define SM5803_REG_FAST_CONF4 0x3C +#define SM5803_CONF4_ICHG_FAST GENMASK(5, 0) /* Fast charge Termination */ -#define SM5803_REG_FAST_CONF5 0x3D -#define SM5803_CONF5_IBAT_EOC_TH GENMASK(3, 0) +#define SM5803_REG_FAST_CONF5 0x3D +#define SM5803_CONF5_IBAT_EOC_TH GENMASK(3, 0) /* IR drop compensation */ -#define SM5803_REG_IR_COMP1 0x3F -#define SM5803_IR_COMP_RES_SET_MSB GENMASK(7, 6) +#define SM5803_REG_IR_COMP1 0x3F +#define SM5803_IR_COMP_RES_SET_MSB GENMASK(7, 6) #define SM5803_IR_COMP_RES_SET_MSB_SHIFT 6 -#define SM5803_IR_COMP_EN BIT(5) +#define SM5803_IR_COMP_EN BIT(5) /* LSB is in 1.67mOhm steps. */ -#define SM5803_REG_IR_COMP2 0x40 +#define SM5803_REG_IR_COMP2 0x40 /* Precharge current limit is also intervals of 100 mA */ -#define SM5803_REG_PRECHG 0x41 -#define SM5803_PRECHG_ICHG_PRE_SET GENMASK(5, 0) - -#define SM5803_REG_LOG1 0x42 -#define SM5803_BATFET_ON BIT(2) - -#define SM5803_REG_LOG2 0x43 -#define SM5803_ISOLOOP_ON BIT(1) - -#define SM5803_REG_STATUS_CHG_REG 0x48 -#define SM5803_STATUS_CHG_BATT_REMOVAL BIT(0) -#define SM5803_STATUS_CHG_CHG_REMOVAL BIT(1) -#define SM5803_STATUS_CHG_BATTEMP_NOK BIT(2) -#define SM5803_STATUS_CHG_CHGWDG_EXP BIT(3) -#define SM5803_STATUS_CHG_VBUS_OC BIT(4) -#define SM5803_STATUS_CHG_OV_VBAT BIT(5) -#define SM5803_STATUS_CHG_TIMEOUT BIT(6) -#define SM5803_STATUS_CHG_OV_ITEMP BIT(7) - -#define SM5803_REG_STATUS_DISCHG 0x49 -#define SM5803_STATUS_DISCHG_BATT_REM BIT(0) -#define SM5803_STATUS_DISCHG_UV_VBAT BIT(1) -#define SM5803_STATUS_DISCHG_VBUS_OC BIT(2) -#define SM5803_STATUS_DISCHG_VBUS_PWR GENMASK(4, 3) -#define SM5803_STATUS_DISCHG_ISO_CURR BIT(5) -#define SM5803_STATUS_DISCHG_VBUS_SHORT BIT(6) -#define SM5803_STATUS_DISCHG_OV_ITEMP BIT(7) - -#define SM5803_REG_CHG_MON_REG 0x5C -#define SM5803_DPM_LOOP_EN BIT(0) - -#define SM5803_REG_PHOT1 0x72 -#define SM5803_PHOT1_IBAT_PHOT_COMP_EN BIT(0) -#define SM5803_PHOT1_IBUS_PHOT_COMP_EN BIT(1) -#define SM5803_PHOT1_VSYS_MON_EN BIT(2) -#define SM5803_PHOT1_VBUS_MON_EN BIT(3) -#define SM5803_PHOT1_COMPARATOR_EN GENMASK(3, 0) -#define SM5803_PHOT1_DURATION GENMASK(6, 4) -#define SM5803_PHOT1_DURATION_SHIFT 4 -#define SM5803_PHOT1_IRQ_MODE BIT(7) +#define SM5803_REG_PRECHG 0x41 +#define SM5803_PRECHG_ICHG_PRE_SET GENMASK(5, 0) + +#define SM5803_REG_LOG1 0x42 +#define SM5803_BATFET_ON BIT(2) + +#define SM5803_REG_LOG2 0x43 +#define SM5803_ISOLOOP_ON BIT(1) + +#define SM5803_REG_STATUS_CHG_REG 0x48 +#define SM5803_STATUS_CHG_BATT_REMOVAL BIT(0) +#define SM5803_STATUS_CHG_CHG_REMOVAL BIT(1) +#define SM5803_STATUS_CHG_BATTEMP_NOK BIT(2) +#define SM5803_STATUS_CHG_CHGWDG_EXP BIT(3) +#define SM5803_STATUS_CHG_VBUS_OC BIT(4) +#define SM5803_STATUS_CHG_OV_VBAT BIT(5) +#define SM5803_STATUS_CHG_TIMEOUT BIT(6) +#define SM5803_STATUS_CHG_OV_ITEMP BIT(7) + +#define SM5803_REG_STATUS_DISCHG 0x49 +#define SM5803_STATUS_DISCHG_BATT_REM BIT(0) +#define SM5803_STATUS_DISCHG_UV_VBAT BIT(1) +#define SM5803_STATUS_DISCHG_VBUS_OC BIT(2) +#define SM5803_STATUS_DISCHG_VBUS_PWR GENMASK(4, 3) +#define SM5803_STATUS_DISCHG_ISO_CURR BIT(5) +#define SM5803_STATUS_DISCHG_VBUS_SHORT BIT(6) +#define SM5803_STATUS_DISCHG_OV_ITEMP BIT(7) + +#define SM5803_REG_CHG_MON_REG 0x5C +#define SM5803_DPM_LOOP_EN BIT(0) + +#define SM5803_REG_PHOT1 0x72 +#define SM5803_PHOT1_IBAT_PHOT_COMP_EN BIT(0) +#define SM5803_PHOT1_IBUS_PHOT_COMP_EN BIT(1) +#define SM5803_PHOT1_VSYS_MON_EN BIT(2) +#define SM5803_PHOT1_VBUS_MON_EN BIT(3) +#define SM5803_PHOT1_COMPARATOR_EN GENMASK(3, 0) +#define SM5803_PHOT1_DURATION GENMASK(6, 4) +#define SM5803_PHOT1_DURATION_SHIFT 4 +#define SM5803_PHOT1_IRQ_MODE BIT(7) #define CHARGER_NAME "sm5803" -- cgit v1.2.1 From 76c295a16f028f12ec106f6bdb16750ba6e4d3cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:53 -0600 Subject: board/grunt/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I422a106ff2473a4fdfe16f8b705acd5335df20b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728430 Reviewed-by: Jeremy Bettis --- board/grunt/board.c | 74 ++++++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 43 deletions(-) diff --git a/board/grunt/board.c b/board/grunt/board.c index 0efa8b9696..1941932e6e 100644 --- a/board/grunt/board.c +++ b/board/grunt/board.c @@ -25,52 +25,40 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "kblight", - .port = I2C_PORT_KBLIGHT, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "kblight", + .port = I2C_PORT_KBLIGHT, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From f1abd4e24fef4e52d462bf3fa7a1b32383f55782 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:43 -0600 Subject: chip/npcx/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If1e73a68c756907dd3480abfe09ac79bddb4d8ce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729400 Reviewed-by: Jeremy Bettis --- chip/npcx/i2c.c | 308 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 167 insertions(+), 141 deletions(-) diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index a7c389f1b3..387a69b9d4 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -24,8 +24,8 @@ #define CPRINTF(...) #else #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) #endif /* Timeout for device should be available after reset (SMBus spec. unit:ms) */ @@ -41,54 +41,54 @@ * I2C module that supports FIFO mode has 32 bytes Tx FIFO and * 32 bytes Rx FIFO. */ -#define NPCX_I2C_FIFO_MAX_SIZE 32 +#define NPCX_I2C_FIFO_MAX_SIZE 32 /* Macro functions of I2C */ #define I2C_START(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_START) -#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) -#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) +#define I2C_STOP(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STOP) +#define I2C_NACK(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_ACK) /* I2C module automatically stall bus after sending peripheral address */ #define I2C_STALL(ctrl) SET_BIT(NPCX_SMBCTL1(ctrl), NPCX_SMBCTL1_STASTRE) #define I2C_WRITE_BYTE(ctrl, data) (NPCX_SMBSDA(ctrl) = data) -#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) +#define I2C_READ_BYTE(ctrl, data) (data = NPCX_SMBSDA(ctrl)) #define I2C_TX_FIFO_OCCUPIED(ctrl) (NPCX_SMBTXF_STS(ctrl) & 0x3F) #define I2C_TX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_TX_FIFO_OCCUPIED(ctrl)) #define I2C_RX_FIFO_OCCUPIED(ctrl) (NPCX_SMBRXF_STS(ctrl) & 0x3F) #define I2C_RX_FIFO_AVAILABLE(ctrl) \ - (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) + (NPCX_I2C_FIFO_MAX_SIZE - I2C_RX_FIFO_OCCUPIED(ctrl)) /* Drive the SCL signal to low */ -#define I2C_SCL_STALL(ctrl) \ - (NPCX_SMBCTL3(ctrl) = \ - (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_STALL(ctrl) \ + (NPCX_SMBCTL3(ctrl) = \ + (NPCX_SMBCTL3(ctrl) & ~BIT(NPCX_SMBCTL3_SCL_LVL)) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* * Release the SCL signal to be pulled up to high level. * Note: The SCL might be still driven low either by I2C module or external * devices connected to ths bus. */ -#define I2C_SCL_FREE(ctrl) \ - (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ - BIT(NPCX_SMBCTL3_SDA_LVL)) +#define I2C_SCL_FREE(ctrl) \ + (NPCX_SMBCTL3(ctrl) |= BIT(NPCX_SMBCTL3_SCL_LVL) | \ + BIT(NPCX_SMBCTL3_SDA_LVL)) /* Error values that functions can return */ enum smb_error { - SMB_OK = 0, /* No error */ - SMB_CH_OCCUPIED, /* Channel is already occupied */ - SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ - SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ - SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ - SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ - SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ - SMB_BUS_ERROR, /* Encounter bus error */ - SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ - /* (Controller Mode) */ - SMB_READ_DATA_ERROR, /* Read data for SDA error */ - SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ - SMB_TIMEOUT_ERROR, /* Timeout expired */ - SMB_MODULE_ISBUSY, /* Module is occupied by other device */ - SMB_BUS_BUSY, /* SMBus is occupied by other device */ + SMB_OK = 0, /* No error */ + SMB_CH_OCCUPIED, /* Channel is already occupied */ + SMB_MEM_POOL_INIT_ERROR, /* Memory pool initialization error */ + SMB_BUS_FREQ_ERROR, /* SMbus freq was not valid */ + SMB_INVLAID_REGVALUE, /* Invalid SMbus register value */ + SMB_UNEXIST_CH_ERROR, /* Channel does not exist */ + SMB_NO_SUPPORT_PTL, /* Not support SMBus Protocol */ + SMB_BUS_ERROR, /* Encounter bus error */ + SMB_NO_ADDRESS_MATCH, /* No peripheral address match */ + /* (Controller Mode) */ + SMB_READ_DATA_ERROR, /* Read data for SDA error */ + SMB_READ_OVERFLOW_ERROR, /* Read data over than we predict */ + SMB_TIMEOUT_ERROR, /* Timeout expired */ + SMB_MODULE_ISBUSY, /* Module is occupied by other device */ + SMB_BUS_BUSY, /* SMBus is occupied by other device */ }; /* @@ -108,18 +108,18 @@ enum smb_oper_state_t { /* I2C controller state data */ struct i2c_status { - int flags; /* Flags (I2C_XFER_*) */ - const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ - uint8_t *rx_buf; /* Entry pointer of receive buffer */ - uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ - uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ - uint16_t idx_buf; /* Current index of Tx/Rx buffer */ - uint16_t addr_flags;/* Target address */ - enum smb_oper_state_t oper_state;/* Smbus operation state */ - enum smb_error err_code; /* Error code */ - int task_waiting; /* Task waiting on controller */ - uint32_t timeout_us;/* Transaction timeout */ - uint16_t kbps; /* Speed */ + int flags; /* Flags (I2C_XFER_*) */ + const uint8_t *tx_buf; /* Entry pointer of transmit buffer */ + uint8_t *rx_buf; /* Entry pointer of receive buffer */ + uint16_t sz_txbuf; /* Size of Tx buffer in bytes */ + uint16_t sz_rxbuf; /* Size of rx buffer in bytes */ + uint16_t idx_buf; /* Current index of Tx/Rx buffer */ + uint16_t addr_flags; /* Target address */ + enum smb_oper_state_t oper_state; /* Smbus operation state */ + enum smb_error err_code; /* Error code */ + int task_waiting; /* Task waiting on controller */ + uint32_t timeout_us; /* Transaction timeout */ + uint16_t kbps; /* Speed */ }; /* I2C controller state data array */ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; @@ -127,27 +127,29 @@ static struct i2c_status i2c_stsobjs[I2C_CONTROLLER_COUNT]; /* I2C timing setting */ struct i2c_timing { uint8_t clock; /* I2C source clock. (Unit: MHz)*/ - uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ - uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ - uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ + uint8_t HLDT; /* I2C hold-time. (Unit: clocks) */ + uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */ + uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */ }; /* I2C timing setting array of 400K & 1M Hz */ static const struct i2c_timing i2c_400k_timings[] = { - {20, 7, 32, 22}, - {15, 7, 24, 18},}; + { 20, 7, 32, 22 }, + { 15, 7, 24, 18 }, +}; const unsigned int i2c_400k_timing_used = ARRAY_SIZE(i2c_400k_timings); static const struct i2c_timing i2c_1m_timings[] = { - {20, 7, 16, 10}, - {15, 7, 14, 10},}; + { 20, 7, 16, 10 }, + { 15, 7, 14, 10 }, +}; const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings); /* IRQ for each port */ const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = { - NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, + NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4, #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, + NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8, #endif }; BUILD_ASSERT(ARRAY_SIZE(i2c_irqs) == I2C_CONTROLLER_COUNT); @@ -198,8 +200,8 @@ static void i2c_abort_data(int controller) SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_NEGACK); /* Wait till STOP condition is generated */ - if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) - != EC_SUCCESS) { + if (i2c_wait_stop_completed(controller, I2C_MAX_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "Abort i2c %02x fail!\n", controller); /* Clear BB (BUS BUSY) bit */ SET_BIT(NPCX_SMBCST(controller), NPCX_SMBCST_BB); @@ -219,8 +221,9 @@ static int i2c_reset(int controller) while (--timeout) { /* WAIT FOR SCL & SDA IS HIGH */ - if (IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SCL_LVL) - && IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) + if (IS_BIT_SET(NPCX_SMBCTL3(controller), + NPCX_SMBCTL3_SCL_LVL) && + IS_BIT_SET(NPCX_SMBCTL3(controller), NPCX_SMBCTL3_SDA_LVL)) break; msleep(1); } @@ -306,9 +309,8 @@ static void i2c_fifo_write_data(int controller) } for (i = 0; i < len; i++) { I2C_WRITE_BYTE(controller, - p_status->tx_buf[p_status->idx_buf++]); - CPRINTF("%02x ", - p_status->tx_buf[p_status->idx_buf - 1]); + p_status->tx_buf[p_status->idx_buf++]); + CPRINTF("%02x ", p_status->tx_buf[p_status->idx_buf - 1]); } CPRINTF("\n"); } @@ -355,7 +357,7 @@ enum smb_error i2c_controller_transaction(int controller) * is set simultaneously. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP)) { + (p_status->flags & I2C_XFER_STOP)) { /* * Since SCL is released after reading last * byte from previous transaction, adding a @@ -375,30 +377,30 @@ enum smb_error i2c_controller_transaction(int controller) } } else cprintf(CC_I2C, "Unexpected i2c state machine! %d\n", - p_status->oper_state); + p_status->oper_state); if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { if (p_status->sz_rxbuf > 0) { if (p_status->sz_rxbuf > NPCX_I2C_FIFO_MAX_SIZE) { /* Set RX threshold = FIFO_MAX_SIZE */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { /* * set RX threshold = remaining data bytes * (it should be <= FIFO_MAX_SIZE) */ SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - p_status->sz_rxbuf); + NPCX_SMBRXF_CTL_RX_THR, + p_status->sz_rxbuf); /* * Set LAST bit generate the NACK at the * last byte of the data group in FIFO */ if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); } } @@ -412,7 +414,7 @@ enum smb_error i2c_controller_transaction(int controller) /* Generate a START condition */ if (p_status->oper_state == SMB_CONTROLLER_START || - p_status->oper_state == SMB_REPEAT_START) { + p_status->oper_state == SMB_REPEAT_START) { I2C_START(controller); CPUTS("ST"); } @@ -421,8 +423,8 @@ enum smb_error i2c_controller_transaction(int controller) task_enable_irq(i2c_irqs[controller]); /* Wait for transfer complete or timeout */ - events = task_wait_event_mask(TASK_EVENT_I2C_IDLE, - p_status->timeout_us); + events = + task_wait_event_mask(TASK_EVENT_I2C_IDLE, p_status->timeout_us); /* Disable event and error interrupts */ task_disable_irq(i2c_irqs[controller]); @@ -452,8 +454,9 @@ enum smb_error i2c_controller_transaction(int controller) i2c_recovery(controller, p_status); /* Wait till STOP condition is generated for normal transaction */ - if (p_status->err_code == SMB_OK && i2c_wait_stop_completed(controller, - I2C_MIN_TIMEOUT) != EC_SUCCESS) { + if (p_status->err_code == SMB_OK && + i2c_wait_stop_completed(controller, I2C_MIN_TIMEOUT) != + EC_SUCCESS) { cprintf(CC_I2C, "STOP fail! scl %02x is held by slave device!\n", controller); @@ -476,7 +479,7 @@ void i2c_done(int controller) /* Clear RXF_TXE bit (RX FIFO full/TX FIFO empty) */ if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) NPCX_SMBFIF_CTS(controller) = - BIT(NPCX_SMBFIF_CTS_RXF_TXE); + BIT(NPCX_SMBFIF_CTS_RXF_TXE); /* Clear SDAST by writing mock byte */ I2C_WRITE_BYTE(controller, 0xFF); @@ -485,8 +488,9 @@ void i2c_done(int controller) /* Set error code */ p_status->err_code = SMB_OK; /* Set SMB status if we need stall bus */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_WRITE_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_WRITE_SUSPEND; /* * Disable interrupt for i2c controller stall SCL * and forbid SDAST generate interrupt @@ -540,7 +544,7 @@ static void i2c_handle_receive(int controller) /* Read to buf. Skip last byte if meet SMB_FAKE_READ_OPER */ if (p_status->oper_state == SMB_FAKE_READ_OPER && - p_status->idx_buf == (p_status->sz_rxbuf - 1)) + p_status->idx_buf == (p_status->sz_rxbuf - 1)) p_status->idx_buf++; else p_status->rx_buf[p_status->idx_buf++] = data; @@ -548,8 +552,9 @@ static void i2c_handle_receive(int controller) /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ @@ -623,35 +628,33 @@ static void i2c_fifo_handle_receive(int controller) if (remaining_bytes > 0) { if (remaining_bytes > NPCX_I2C_FIFO_MAX_SIZE) { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - NPCX_I2C_FIFO_MAX_SIZE); + NPCX_SMBRXF_CTL_RX_THR, + NPCX_I2C_FIFO_MAX_SIZE); } else { SET_FIELD(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_RX_THR, - remaining_bytes); + NPCX_SMBRXF_CTL_RX_THR, + remaining_bytes); if (p_status->flags & I2C_XFER_STOP) { SET_BIT(NPCX_SMBRXF_CTL(controller), - NPCX_SMBRXF_CTL_LAST); + NPCX_SMBRXF_CTL_LAST); CPRINTS("-FGNA"); } } - } i2c_stall_bus(controller, 0); - } /* last byte is read - end of transaction */ if (p_status->idx_buf == p_status->sz_rxbuf) { /* Set current status */ - p_status->oper_state = (p_status->flags & I2C_XFER_STOP) - ? SMB_IDLE : SMB_READ_SUSPEND; + p_status->oper_state = (p_status->flags & I2C_XFER_STOP) ? + SMB_IDLE : + SMB_READ_SUSPEND; /* Set error code */ p_status->err_code = SMB_OK; /* Notify upper layer of missing data */ task_set_event(p_status->task_waiting, TASK_EVENT_I2C_IDLE); CPUTS("-END"); } - } static void i2c_handle_sda_irq(int controller) @@ -660,10 +663,10 @@ static void i2c_handle_sda_irq(int controller) uint8_t addr_8bit = I2C_STRIP_FLAGS(p_status->addr_flags) << 1; /* 1 Issue Start is successful ie. write address byte */ - if (p_status->oper_state == SMB_CONTROLLER_START - || p_status->oper_state == SMB_REPEAT_START) { + if (p_status->oper_state == SMB_CONTROLLER_START || + p_status->oper_state == SMB_REPEAT_START) { /* Prepare address byte */ - if (p_status->sz_txbuf == 0) {/* Receive mode */ + if (p_status->sz_txbuf == 0) { /* Receive mode */ p_status->oper_state = SMB_READ_OPER; /* * Receiving one or zero bytes - stall bus after @@ -676,7 +679,7 @@ static void i2c_handle_sda_irq(int controller) /* Write the address to the bus R bit*/ I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPRINTS("-ARR-0x%02x", addr_8bit); - } else {/* Transmit mode */ + } else { /* Transmit mode */ p_status->oper_state = SMB_WRITE_OPER; /* Write the address to the bus W bit*/ I2C_WRITE_BYTE(controller, addr_8bit); @@ -720,14 +723,13 @@ static void i2c_handle_sda_irq(int controller) * in the SMBnTXF_CTL register. */ if (p_status->sz_rxbuf == 1 && - (p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + (p_status->flags & I2C_XFER_STOP) && + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); CPUTS("-GNA"); } /* Write the address to the bus R bit*/ - I2C_WRITE_BYTE(controller, - (addr_8bit | 0x1)); + I2C_WRITE_BYTE(controller, (addr_8bit | 0x1)); CPUTS("-ARR"); } } @@ -749,7 +751,7 @@ static void i2c_handle_sda_irq(int controller) * operation) */ else if (p_status->oper_state == SMB_READ_OPER || - p_status->oper_state == SMB_FAKE_READ_OPER) { + p_status->oper_state == SMB_FAKE_READ_OPER) { if (IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) i2c_fifo_handle_receive(controller); else @@ -826,7 +828,7 @@ static void i2c_controller_int_handler(int controller) * register. */ else if ((p_status->flags & I2C_XFER_STOP) && - !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { + !IS_ENABLED(NPCX_I2C_FIFO_SUPPORT)) { I2C_NACK(controller); } @@ -840,9 +842,10 @@ static void i2c_controller_int_handler(int controller) #if DEBUG_I2C /* SDAST still issued with unexpected state machine */ if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_SDAST) && - p_status->oper_state != SMB_WRITE_SUSPEND) { + p_status->oper_state != SMB_WRITE_SUSPEND) { cprints(CC_I2C, "i2c %d unknown state %d, error %d\n", - controller, p_status->oper_state, p_status->err_code); + controller, p_status->oper_state, + p_status->err_code); } #endif } @@ -858,15 +861,39 @@ void handle_interrupt(int controller) i2c_controller_int_handler(controller); } -static void i2c0_interrupt(void) { handle_interrupt(0); } -static void i2c1_interrupt(void) { handle_interrupt(1); } -static void i2c2_interrupt(void) { handle_interrupt(2); } -static void i2c3_interrupt(void) { handle_interrupt(3); } +static void i2c0_interrupt(void) +{ + handle_interrupt(0); +} +static void i2c1_interrupt(void) +{ + handle_interrupt(1); +} +static void i2c2_interrupt(void) +{ + handle_interrupt(2); +} +static void i2c3_interrupt(void) +{ + handle_interrupt(3); +} #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 -static void i2c4_interrupt(void) { handle_interrupt(4); } -static void i2c5_interrupt(void) { handle_interrupt(5); } -static void i2c6_interrupt(void) { handle_interrupt(6); } -static void i2c7_interrupt(void) { handle_interrupt(7); } +static void i2c4_interrupt(void) +{ + handle_interrupt(4); +} +static void i2c5_interrupt(void) +{ + handle_interrupt(5); +} +static void i2c6_interrupt(void) +{ + handle_interrupt(6); +} +static void i2c7_interrupt(void) +{ + handle_interrupt(7); +} #endif DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4); @@ -892,14 +919,12 @@ void i2c_set_timeout(int port, uint32_t timeout) return; /* Param is port, but timeout is stored by-controller. */ - i2c_stsobjs[ctrl].timeout_us = - timeout ? timeout : I2C_TIMEOUT_DEFAULT_US; + i2c_stsobjs[ctrl].timeout_us = timeout ? timeout : + I2C_TIMEOUT_DEFAULT_US; } -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { volatile struct i2c_status *p_status; int ctrl = i2c_port_to_controller(port); @@ -921,23 +946,23 @@ int chip_i2c_xfer(const int port, i2c_select_port(port); /* Copy data to controller struct */ - p_status->flags = flags; - p_status->tx_buf = out; - p_status->sz_txbuf = out_size; - p_status->rx_buf = in; - p_status->sz_rxbuf = in_size; + p_status->flags = flags; + p_status->tx_buf = out; + p_status->sz_txbuf = out_size; + p_status->rx_buf = in; + p_status->sz_rxbuf = in_size; p_status->addr_flags = addr_flags; /* Reset index & error */ - p_status->idx_buf = 0; - p_status->err_code = SMB_OK; + p_status->idx_buf = 0; + p_status->err_code = SMB_OK; /* Make sure we're in a good state to start */ if ((flags & I2C_XFER_START) && - /* Ignore busy bus for repeated start */ - p_status->oper_state != SMB_WRITE_SUSPEND && - (i2c_bus_busy(ctrl) - || (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { + /* Ignore busy bus for repeated start */ + p_status->oper_state != SMB_WRITE_SUSPEND && + (i2c_bus_busy(ctrl) || + (i2c_get_line_levels(port) != I2C_LINE_IDLE))) { int ret; /* Attempt to unwedge the i2c port */ @@ -974,7 +999,7 @@ int chip_i2c_xfer(const int port, int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } int i2c_raw_get_scl(int port) @@ -989,8 +1014,9 @@ int i2c_raw_get_scl(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SCL_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SCL_LVL); } /* If no SCL pin defined for this port, then return 1 to appear idle */ @@ -1009,11 +1035,11 @@ int i2c_raw_get_sda(int port) if (i2c_is_raw_mode(port)) return gpio_get_level(g); else - return IS_BIT_SET(NPCX_SMBCTL3( - i2c_port_to_controller(port)), NPCX_SMBCTL3_SDA_LVL); + return IS_BIT_SET( + NPCX_SMBCTL3(i2c_port_to_controller(port)), + NPCX_SMBCTL3_SDA_LVL); } - /* If no SDA pin defined for this port, then return 1 to appear idle */ return 1; } @@ -1032,8 +1058,8 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * SMB0/1/4/5/6/7 use APB3 clock * SMB2/3 use APB2 clock */ - freq = (ctrl < 2 || ctrl > 3) ? - clock_get_apb3_freq() : clock_get_apb2_freq(); + freq = (ctrl < 2 || ctrl > 3) ? clock_get_apb3_freq() : + clock_get_apb2_freq(); #else /* CHIP_FAMILY_NPCX5 */ /* * SMB0/1 use core clock @@ -1051,7 +1077,7 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) * fSCL = fCLK / (4*SCLFRQ) * SCLFRQ = ceil(fCLK/(4*fSCL)) */ - scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps*4000); /* Unit in bps */ + scl_freq = DIV_ROUND_UP(freq, bus_freq_kbps * 4000); /* Unit in bps */ /* Normal mode if I2C freq is under 100kHz */ if (bus_freq_kbps <= 100) { @@ -1089,19 +1115,19 @@ static void i2c_port_set_freq(const int ctrl, const int bus_freq_kbps) } for (j = 0; j < i2c_timing_used; j++, pTiming++) { - if (pTiming->clock == (freq/SECOND)) { + if (pTiming->clock == (freq / SECOND)) { i2c_stsobjs[ctrl].kbps = bus_freq_kbps; /* Set SCLH(L)T and hold-time */ - NPCX_SMBSCLLT(ctrl) = pTiming->k1/2; - NPCX_SMBSCLHT(ctrl) = pTiming->k2/2; - SET_FIELD(NPCX_SMBCTL4(ctrl), - NPCX_SMBCTL4_HLDT_FIELD, pTiming->HLDT); + NPCX_SMBSCLLT(ctrl) = pTiming->k1 / 2; + NPCX_SMBSCLHT(ctrl) = pTiming->k2 / 2; + SET_FIELD(NPCX_SMBCTL4(ctrl), NPCX_SMBCTL4_HLDT_FIELD, + pTiming->HLDT); break; } } if (j == i2c_timing_used) - cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", - ctrl, freq / SECOND); + cprints(CC_I2C, "Error: I2C %d: src clk %d not supported", ctrl, + freq / SECOND); } /* Hooks */ @@ -1187,10 +1213,10 @@ void i2c_init(void) /* Enable clock for I2C peripheral */ clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); #endif /* Set I2C freq */ -- cgit v1.2.1 From b2d30399a8bdcc11a3e9bd0d6957fd4441dcfcaa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:29 -0600 Subject: common/spi_flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b17aaee096dba157184ddcd8a2900acb5024e20 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729732 Reviewed-by: Jeremy Bettis --- common/spi_flash.c | 86 +++++++++++++++++++++++++----------------------------- 1 file changed, 39 insertions(+), 47 deletions(-) diff --git a/common/spi_flash.c b/common/spi_flash.c index e202e1e17d..d7cf9fc49a 100644 --- a/common/spi_flash.c +++ b/common/spi_flash.c @@ -22,12 +22,12 @@ /* * Time to sleep when chip is busy */ -#define SPI_FLASH_SLEEP_USEC 100 +#define SPI_FLASH_SLEEP_USEC 100 /* * This is the max time for 32kb flash erase */ -#define SPI_FLASH_TIMEOUT_USEC (800*MSEC) +#define SPI_FLASH_TIMEOUT_USEC (800 * MSEC) /* Internal buffer used by SPI flash driver */ static uint8_t buf[SPI_FLASH_MAX_MESSAGE_SIZE]; @@ -109,13 +109,12 @@ uint8_t spi_flash_get_status2(void) */ int spi_flash_set_status(int reg1, int reg2) { - uint8_t cmd[3] = {SPI_FLASH_WRITE_SR, reg1, reg2}; + uint8_t cmd[3] = { SPI_FLASH_WRITE_SR, reg1, reg2 }; int rv = EC_SUCCESS; /* fail if both HW pin is asserted and SRP(s) is 1 */ if (spi_flash_check_wp() != SPI_WP_NONE && - (crec_flash_get_protect() & - EC_FLASH_PROTECT_GPIO_ASSERTED) != 0) + (crec_flash_get_protect() & EC_FLASH_PROTECT_GPIO_ASSERTED) != 0) return EC_ERROR_ACCESS_DENIED; /* Enable writing to SPI flash */ @@ -123,7 +122,7 @@ int spi_flash_set_status(int reg1, int reg2) if (rv) return rv; - /* Second status register not present */ + /* Second status register not present */ #ifndef CONFIG_SPI_FLASH_HAS_SR2 reg2 = -1; #endif @@ -163,11 +162,8 @@ int spi_flash_read(uint8_t *buf_usr, unsigned int offset, unsigned int bytes) cmd[2] = (spi_addr >> 8) & 0xFF; cmd[3] = spi_addr & 0xFF; read_size = MIN((bytes - i), SPI_FLASH_MAX_READ_SIZE); - ret = spi_transaction(SPI_FLASH_DEVICE, - cmd, - 4, - buf_usr + i, - read_size); + ret = spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr + i, + read_size); if (ret != EC_SUCCESS) break; msleep(CONFIG_SPI_FLASH_READ_WAIT_MS); @@ -276,7 +272,7 @@ int spi_flash_erase(unsigned int offset, unsigned int bytes) * @return EC_SUCCESS, or non-zero if any error. */ int spi_flash_write(unsigned int offset, unsigned int bytes, - const uint8_t *data) + const uint8_t *data) { int rv, write_size; @@ -288,8 +284,10 @@ int spi_flash_write(unsigned int offset, unsigned int bytes, while (bytes > 0) { watchdog_reload(); /* Write length can not go beyond the end of the flash page */ - write_size = MIN(bytes, SPI_FLASH_MAX_WRITE_SIZE - - (offset & (SPI_FLASH_MAX_WRITE_SIZE - 1))); + write_size = + MIN(bytes, + SPI_FLASH_MAX_WRITE_SIZE - + (offset & (SPI_FLASH_MAX_WRITE_SIZE - 1))); /* Wait for previous operation to complete */ rv = spi_flash_wait(); @@ -310,8 +308,8 @@ int spi_flash_write(unsigned int offset, unsigned int bytes, buf[2] = (offset) >> 8; buf[3] = offset; - rv = spi_transaction(SPI_FLASH_DEVICE, - buf, 4 + write_size, NULL, 0); + rv = spi_transaction(SPI_FLASH_DEVICE, buf, 4 + write_size, + NULL, 0); if (rv) return rv; @@ -345,7 +343,7 @@ int spi_flash_get_jedec_id(uint8_t *dest) */ int spi_flash_get_mfr_dev_id(uint8_t *dest) { - uint8_t cmd[4] = {SPI_FLASH_MFR_DEV_ID, 0, 0, 0}; + uint8_t cmd[4] = { SPI_FLASH_MFR_DEV_ID, 0, 0, 0 }; return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 2); } @@ -358,7 +356,7 @@ int spi_flash_get_mfr_dev_id(uint8_t *dest) */ int spi_flash_get_unique_id(uint8_t *dest) { - uint8_t cmd[5] = {SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0}; + uint8_t cmd[5] = { SPI_FLASH_UNIQUE_ID, 0, 0, 0, 0 }; return spi_transaction(SPI_FLASH_DEVICE, cmd, sizeof(cmd), dest, 8); } @@ -497,18 +495,17 @@ static int command_spi_flashinfo(int argc, char **argv) spi_flash_get_jedec_id(jedec); spi_flash_get_unique_id(unique); - ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n", - jedec[0], jedec[1], jedec[2]); + ccprintf("Manufacturer ID: %02x\nDevice ID: %02x %02x\n", jedec[0], + jedec[1], jedec[2]); ccprintf("Unique ID: %02x %02x %02x %02x %02x %02x %02x %02x\n", - unique[0], unique[1], unique[2], unique[3], - unique[4], unique[5], unique[6], unique[7]); + unique[0], unique[1], unique[2], unique[3], unique[4], + unique[5], unique[6], unique[7]); ccprintf("Capacity: %4d kB\n", SPI_FLASH_SIZE(jedec[2]) / 1024); return rv; } -DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo, - NULL, - "Print SPI flash info"); +DECLARE_CONSOLE_COMMAND(spi_flashinfo, command_spi_flashinfo, NULL, + "Print SPI flash info"); #ifdef CONFIG_HOSTCMD_FLASH_SPI_INFO static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args) @@ -524,10 +521,9 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, - flash_command_spi_info, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info, EC_VER_MASK(0)); -#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */ +#endif /* CONFIG_HOSTCMD_FLASH_SPI_INFO */ #ifdef CONFIG_CMD_SPI_FLASH static int command_spi_flasherase(int argc, char **argv) @@ -549,8 +545,7 @@ static int command_spi_flasherase(int argc, char **argv) return spi_flash_erase(offset, bytes); } DECLARE_CONSOLE_COMMAND(spi_flasherase, command_spi_flasherase, - "offset [bytes]", - "Erase flash"); + "offset [bytes]", "Erase flash"); static int command_spi_flashwrite(int argc, char **argv) { @@ -578,7 +573,8 @@ static int command_spi_flashwrite(int argc, char **argv) while (bytes > 0) { /* First write multiples of 256, then (bytes % 256) last */ write_len = ((bytes % SPI_FLASH_MAX_WRITE_SIZE) == bytes) ? - bytes : SPI_FLASH_MAX_WRITE_SIZE; + bytes : + SPI_FLASH_MAX_WRITE_SIZE; /* Perform write */ rv = spi_flash_write(offset, write_len, buf); @@ -594,8 +590,7 @@ static int command_spi_flashwrite(int argc, char **argv) return rv; } DECLARE_CONSOLE_COMMAND(spi_flashwrite, command_spi_flashwrite, - "offset [bytes]", - "Write pattern to flash"); + "offset [bytes]", "Write pattern to flash"); static int command_spi_flashread(int argc, char **argv) { @@ -627,8 +622,8 @@ static int command_spi_flashread(int argc, char **argv) /* First read (bytes % 256), then in multiples of 256 */ read_len = (bytes % SPI_FLASH_MAX_READ_SIZE) ? - (bytes % SPI_FLASH_MAX_READ_SIZE) : - SPI_FLASH_MAX_READ_SIZE; + (bytes % SPI_FLASH_MAX_READ_SIZE) : + SPI_FLASH_MAX_READ_SIZE; rv = spi_flash_read(buf, offset, read_len); if (rv) @@ -651,9 +646,8 @@ static int command_spi_flashread(int argc, char **argv) ASSERT(bytes == 0); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread, - "offset bytes", - "Read flash"); +DECLARE_CONSOLE_COMMAND(spi_flashread, command_spi_flashread, "offset bytes", + "Read flash"); static int command_spi_flashread_sr(int argc, char **argv) { @@ -664,9 +658,8 @@ static int command_spi_flashread_sr(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr, - NULL, - "Read status registers"); +DECLARE_CONSOLE_COMMAND(spi_flash_rsr, command_spi_flashread_sr, NULL, + "Read status registers"); static int command_spi_flashwrite_sr(int argc, char **argv) { @@ -684,8 +677,7 @@ static int command_spi_flashwrite_sr(int argc, char **argv) return spi_flash_set_status(val1, val2); } DECLARE_CONSOLE_COMMAND(spi_flash_wsr, command_spi_flashwrite_sr, - "value1 value2", - "Write to status registers"); + "value1 value2", "Write to status registers"); static int command_spi_flashprotect(int argc, char **argv) { @@ -698,10 +690,10 @@ static int command_spi_flashprotect(int argc, char **argv) spi_enable(SPI_FLASH_DEVICE, 1); - ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1, val1+val2); + ccprintf("Setting protection for 0x%06x to 0x%06x\n", val1, + val1 + val2); return spi_flash_set_protect(val1, val2); } -DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect, - "offset len", - "Set block protection"); +DECLARE_CONSOLE_COMMAND(spi_flash_prot, command_spi_flashprotect, "offset len", + "Set block protection"); #endif -- cgit v1.2.1 From f2c597af044e2889691349fb44d45146c6d5c9c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:30 -0600 Subject: test/sha256.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idad3280704d9a70e07befccb11b74a1bfe62718c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730521 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/sha256.c | 69 +++++++++++++++++++++++++++-------------------------------- 1 file changed, 32 insertions(+), 37 deletions(-) diff --git a/test/sha256.c b/test/sha256.c index 105ae8fec5..955167f53a 100644 --- a/test/sha256.c +++ b/test/sha256.c @@ -12,23 +12,20 @@ #include "util.h" /* Short Msg from NIST FIPS 180-4 (Len = 8) */ -static const uint8_t sha256_8_input[] = { - 0xd3 -}; +static const uint8_t sha256_8_input[] = { 0xd3 }; static const uint8_t sha256_8_output[SHA256_DIGEST_SIZE] = { - 0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad, 0x96, - 0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea, 0x5c, 0x23, - 0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1 + 0x28, 0x96, 0x9c, 0xdf, 0xa7, 0x4a, 0x12, 0xc8, 0x2f, 0x3b, 0xad, + 0x96, 0x0b, 0x0b, 0x00, 0x0a, 0xca, 0x2a, 0xc3, 0x29, 0xde, 0xea, + 0x5c, 0x23, 0x28, 0xeb, 0xc6, 0xf2, 0xba, 0x98, 0x02, 0xc1 }; /* Short Msg from NIST FIPS 180-4 (Len = 72) */ -static const uint8_t sha256_72_input[] = { - 0x33, 0x34, 0xc5, 0x80, 0x75, 0xd3, 0xf4, 0x13, 0x9e -}; +static const uint8_t sha256_72_input[] = { 0x33, 0x34, 0xc5, 0x80, 0x75, + 0xd3, 0xf4, 0x13, 0x9e }; static const uint8_t sha256_72_output[SHA256_DIGEST_SIZE] = { - 0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43, 0x3f, - 0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0, 0x8b, 0x4b, - 0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20 + 0x07, 0x8d, 0xa3, 0xd7, 0x7e, 0xd4, 0x3b, 0xd3, 0x03, 0x7a, 0x43, + 0x3f, 0xd0, 0x34, 0x18, 0x55, 0x02, 0x37, 0x93, 0xf9, 0xaf, 0xd0, + 0x8b, 0x4b, 0x08, 0xea, 0x1e, 0x55, 0x97, 0xce, 0xef, 0x20 }; /* Long Msg from NIST FIPS 180-4 (Len = 2888) */ @@ -66,9 +63,9 @@ static const uint8_t sha256_2888_input[] = { 0x93 }; static const uint8_t sha256_2888_output[SHA256_DIGEST_SIZE] = { - 0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0, 0x09, - 0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7, 0x8a, 0x2e, - 0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40 + 0x5f, 0x4e, 0x16, 0xa7, 0x2d, 0x6c, 0x98, 0x57, 0xda, 0x0b, 0xa0, + 0x09, 0xcc, 0xac, 0xd4, 0xf2, 0x6d, 0x7f, 0x6b, 0xf6, 0xc1, 0xb7, + 0x8a, 0x2e, 0xd3, 0x5e, 0x68, 0xfc, 0xb1, 0x5b, 0x8e, 0x40 }; /* HMAC short key (40 bytes) from NIST FIPS 198-1 (Count = 34) */ @@ -86,15 +83,15 @@ static const uint8_t hmac_short_msg[] = { 0x03, 0x2b, 0x31, 0xd2, 0x41, 0xad, 0x33, 0x71 }; static const uint8_t hmac_short_key[] = { - 0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9, 0xb5, 0x44, - 0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca, 0x16, 0xb9, 0x2e, 0xe1, - 0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad, 0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34, - 0x39, 0x31, 0x1e, 0x04 + 0x9d, 0xa0, 0xc1, 0x14, 0x68, 0x2f, 0x82, 0xc1, 0xd1, 0xe9, + 0xb5, 0x44, 0x30, 0x58, 0x0b, 0x9c, 0x56, 0x94, 0x89, 0xca, + 0x16, 0xb9, 0x2e, 0xe1, 0x04, 0x98, 0xd5, 0x5d, 0x7c, 0xad, + 0x5d, 0xb5, 0xe6, 0x52, 0x06, 0x34, 0x39, 0x31, 0x1e, 0x04 }; static const uint8_t hmac_short_output[] = { - 0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41, 0x75, - 0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e, 0x86, 0x7e, - 0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2 + 0xcd, 0xea, 0xcf, 0xce, 0xbf, 0x46, 0xcc, 0x9d, 0x7e, 0x4d, 0x41, + 0x75, 0xe5, 0xd8, 0xd2, 0x67, 0xc2, 0x3a, 0x64, 0xcd, 0xe8, 0x3e, + 0x86, 0x7e, 0x50, 0x01, 0xec, 0xf2, 0x6f, 0xbd, 0x30, 0xd2 }; /* HMAC medium key (64 bytes) from NIST FIPS 198-1 (Count = 120) */ @@ -112,17 +109,17 @@ static const uint8_t hmac_medium_msg[] = { 0x85, 0x46, 0x80, 0x4f, 0x9c, 0xf2, 0xec, 0xfe }; static const uint8_t hmac_medium_key[] = { - 0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc, 0xbd, - 0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8, 0x18, 0x64, - 0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb, 0x5b, 0x50, 0x17, - 0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9, 0x5c, 0x32, 0x10, 0xc3, - 0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d, 0x1b, 0x4f, 0x39, 0x18, 0x17, - 0xf4, 0xc3, 0x51, 0x24 + 0x99, 0x28, 0x68, 0x50, 0x4d, 0x25, 0x64, 0xc4, 0xfb, 0x47, 0xbc, + 0xbd, 0x4a, 0xe4, 0x82, 0xd8, 0xfb, 0x0e, 0x8e, 0x56, 0xd7, 0xb8, + 0x18, 0x64, 0xe6, 0x19, 0x86, 0xa0, 0xe2, 0x56, 0x82, 0xda, 0xeb, + 0x5b, 0x50, 0x17, 0x7c, 0x09, 0x5e, 0xdc, 0x9e, 0x97, 0x1d, 0xa9, + 0x5c, 0x32, 0x10, 0xc3, 0x76, 0xe7, 0x23, 0x36, 0x5a, 0xc3, 0x3d, + 0x1b, 0x4f, 0x39, 0x18, 0x17, 0xf4, 0xc3, 0x51, 0x24 }; static const uint8_t hmac_medium_output[] = { - 0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b, 0x13, - 0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39, 0xc1, 0x0d, - 0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf + 0x2f, 0x83, 0x21, 0xf4, 0x16, 0xb9, 0xbb, 0x24, 0x9f, 0x11, 0x3b, + 0x13, 0xfc, 0x12, 0xd7, 0x0e, 0x16, 0x68, 0xdc, 0x33, 0x28, 0x39, + 0xc1, 0x0d, 0xaa, 0x57, 0x17, 0x89, 0x6c, 0xb7, 0x0d, 0xdf }; static int test_sha256(const uint8_t *input, int input_len, @@ -156,9 +153,8 @@ static int test_sha256(const uint8_t *input, int input_len, return 1; } -static int test_hmac(const uint8_t *key, int key_len, - const uint8_t *input, int input_len, - const uint8_t *output) +static int test_hmac(const uint8_t *key, int key_len, const uint8_t *input, + int input_len, const uint8_t *output) { uint8_t tmp[SHA256_DIGEST_SIZE]; @@ -196,9 +192,8 @@ void run_test(int argc, char **argv) } ccprintf("HMAC: Testing short key\n"); - if (!test_hmac(hmac_short_key, sizeof(hmac_short_key), - hmac_short_msg, sizeof(hmac_short_msg), - hmac_short_output)) { + if (!test_hmac(hmac_short_key, sizeof(hmac_short_key), hmac_short_msg, + sizeof(hmac_short_msg), hmac_short_output)) { test_fail(); return; } -- cgit v1.2.1 From ab1e90f1ff6cc4e87ec2e597c2cd6991682192af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:32 -0600 Subject: driver/accelgyro_bmi3xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f91b3edcdba7480d7383aaadd5d1fc563a8cc8b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729891 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi3xx.h | 298 +++++++++++++++++++++++----------------------- 1 file changed, 146 insertions(+), 152 deletions(-) diff --git a/driver/accelgyro_bmi3xx.h b/driver/accelgyro_bmi3xx.h index 13037fbe51..32381aab24 100644 --- a/driver/accelgyro_bmi3xx.h +++ b/driver/accelgyro_bmi3xx.h @@ -9,199 +9,196 @@ #define __CROS_EC_ACCELGYRO_BMI3XX_H /* Sensor Specific macros */ -#define BMI3_ADDR_I2C_PRIM 0x68 -#define BMI3_ADDR_I2C_SEC 0x69 -#define BMI3_16_BIT_RESOLUTION 16 +#define BMI3_ADDR_I2C_PRIM 0x68 +#define BMI3_ADDR_I2C_SEC 0x69 +#define BMI3_16_BIT_RESOLUTION 16 /* Chip-specific registers */ -#define BMI3_REG_CHIP_ID 0x00 - -#define BMI3_REG_STATUS 0x02 -#define BMI3_STAT_DATA_RDY_ACCEL_POS 7 -#define BMI3_STAT_DATA_RDY_ACCEL_MSK 0x80 - -#define BMI3_REG_ACC_DATA_X 0x03 -#define BMI3_ACC_RANGE_2G 0x00 -#define BMI3_ACC_RANGE_4G 0x01 -#define BMI3_ACC_RANGE_8G 0x02 -#define BMI3_ACC_RANGE_16G 0x03 -#define BMI3_ACC_MODE_DISABLE 0x00 -#define BMI3_ACC_MODE_LOW_PWR 0x03 -#define BMI3_ACC_MODE_NORMAL 0X04 -#define BMI3_ACC_MODE_HIGH_PERF 0x07 - -#define BMI3_REG_GYR_DATA_X 0x06 -#define BMI3_GYR_RANGE_125DPS 0x00 -#define BMI3_GYR_RANGE_250DPS 0x01 -#define BMI3_GYR_RANGE_500DPS 0x02 -#define BMI3_GYR_RANGE_1000DPS 0x03 -#define BMI3_GYR_RANGE_2000DPS 0x04 -#define BMI3_GYR_MODE_DISABLE 0x00 -#define BMI3_GYR_MODE_SUSPEND 0X01 -#define BMI3_GYR_MODE_ULTRA_LOW_PWR 0X02 -#define BMI3_GYR_MODE_LOW_PWR 0x03 -#define BMI3_GYR_MODE_NORMAL 0X04 -#define BMI3_GYR_MODE_HIGH_PERF 0x07 - -#define BMI3_REG_INT_STATUS_INT1 0x0D -#define BMI3_REG_FIFO_FILL_LVL 0x15 -#define BMI3_REG_FIFO_DATA 0x16 -#define BMI3_REG_ACC_CONF 0x20 -#define BMI3_REG_GYR_CONF 0x21 -#define BMI3_REG_INT_MAP1 0x3A -#define BMI3_REG_FIFO_WATERMARK 0x35 -#define BMI3_REG_UGAIN_OFF_SEL 0x3F -#define BMI3_REG_FIFO_CONF 0x36 -#define BMI3_FIFO_STOP_ON_FULL 0x01 -#define BMI3_FIFO_TIME_EN 0x01 -#define BMI3_FIFO_ACC_EN 0x02 -#define BMI3_FIFO_GYR_EN 0x04 -#define BMI3_FIFO_TEMP_EN 0x08 -#define BMI3_FIFO_ALL_EN 0x0F - -#define BMI3_REG_FIFO_CTRL 0x37 -#define BMI3_REG_IO_INT_CTRL 0x38 -#define BMI3_INT1_LVL_MASK 0x01 -#define BMI3_INT1_OD_MASK 0x02 -#define BMI3_INT1_OD_POS 1 -#define BMI3_INT1_OUTPUT_EN_MASK 0x04 -#define BMI3_INT1_OUTPUT_EN_POS 2 -#define BMI3_INT_PUSH_PULL 0 -#define BMI3_INT_OPEN_DRAIN 1 -#define BMI3_INT_ACTIVE_LOW 0 -#define BMI3_INT_ACTIVE_HIGH 1 - -#define BMI3_REG_IO_INT_CONF 0x39 -#define BMI3_INT_LATCH_EN 1 -#define BMI3_INT_LATCH_DISABLE 0 - -#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL 0x40 - -#define BMI3_FEATURE_EVENT_EXT 0x47 -#define BMI3_PORTRAIT_LANDSCAPE_MASK 0x03 -#define BMI3_PORTRAIT 0 -#define BMI3_LANDSCAPE 1 -#define BMI3_PORTRAIT_INVERT 2 -#define BMI3_LANDSCAPE_INVERT 3 - -#define ACC_DP_OFF_X 0x60 -#define GYR_DP_OFF_X 0x66 - -#define BMI3_REG_CMD 0x7E -#define BMI3_CMD_SOFT_RESET 0xDEAF +#define BMI3_REG_CHIP_ID 0x00 + +#define BMI3_REG_STATUS 0x02 +#define BMI3_STAT_DATA_RDY_ACCEL_POS 7 +#define BMI3_STAT_DATA_RDY_ACCEL_MSK 0x80 + +#define BMI3_REG_ACC_DATA_X 0x03 +#define BMI3_ACC_RANGE_2G 0x00 +#define BMI3_ACC_RANGE_4G 0x01 +#define BMI3_ACC_RANGE_8G 0x02 +#define BMI3_ACC_RANGE_16G 0x03 +#define BMI3_ACC_MODE_DISABLE 0x00 +#define BMI3_ACC_MODE_LOW_PWR 0x03 +#define BMI3_ACC_MODE_NORMAL 0X04 +#define BMI3_ACC_MODE_HIGH_PERF 0x07 + +#define BMI3_REG_GYR_DATA_X 0x06 +#define BMI3_GYR_RANGE_125DPS 0x00 +#define BMI3_GYR_RANGE_250DPS 0x01 +#define BMI3_GYR_RANGE_500DPS 0x02 +#define BMI3_GYR_RANGE_1000DPS 0x03 +#define BMI3_GYR_RANGE_2000DPS 0x04 +#define BMI3_GYR_MODE_DISABLE 0x00 +#define BMI3_GYR_MODE_SUSPEND 0X01 +#define BMI3_GYR_MODE_ULTRA_LOW_PWR 0X02 +#define BMI3_GYR_MODE_LOW_PWR 0x03 +#define BMI3_GYR_MODE_NORMAL 0X04 +#define BMI3_GYR_MODE_HIGH_PERF 0x07 + +#define BMI3_REG_INT_STATUS_INT1 0x0D +#define BMI3_REG_FIFO_FILL_LVL 0x15 +#define BMI3_REG_FIFO_DATA 0x16 +#define BMI3_REG_ACC_CONF 0x20 +#define BMI3_REG_GYR_CONF 0x21 +#define BMI3_REG_INT_MAP1 0x3A +#define BMI3_REG_FIFO_WATERMARK 0x35 +#define BMI3_REG_UGAIN_OFF_SEL 0x3F +#define BMI3_REG_FIFO_CONF 0x36 +#define BMI3_FIFO_STOP_ON_FULL 0x01 +#define BMI3_FIFO_TIME_EN 0x01 +#define BMI3_FIFO_ACC_EN 0x02 +#define BMI3_FIFO_GYR_EN 0x04 +#define BMI3_FIFO_TEMP_EN 0x08 +#define BMI3_FIFO_ALL_EN 0x0F + +#define BMI3_REG_FIFO_CTRL 0x37 +#define BMI3_REG_IO_INT_CTRL 0x38 +#define BMI3_INT1_LVL_MASK 0x01 +#define BMI3_INT1_OD_MASK 0x02 +#define BMI3_INT1_OD_POS 1 +#define BMI3_INT1_OUTPUT_EN_MASK 0x04 +#define BMI3_INT1_OUTPUT_EN_POS 2 +#define BMI3_INT_PUSH_PULL 0 +#define BMI3_INT_OPEN_DRAIN 1 +#define BMI3_INT_ACTIVE_LOW 0 +#define BMI3_INT_ACTIVE_HIGH 1 + +#define BMI3_REG_IO_INT_CONF 0x39 +#define BMI3_INT_LATCH_EN 1 +#define BMI3_INT_LATCH_DISABLE 0 + +#define BMI3_REG_FEATURE_ENGINE_GLOB_CTRL 0x40 + +#define BMI3_FEATURE_EVENT_EXT 0x47 +#define BMI3_PORTRAIT_LANDSCAPE_MASK 0x03 +#define BMI3_PORTRAIT 0 +#define BMI3_LANDSCAPE 1 +#define BMI3_PORTRAIT_INVERT 2 +#define BMI3_LANDSCAPE_INVERT 3 + +#define ACC_DP_OFF_X 0x60 +#define GYR_DP_OFF_X 0x66 + +#define BMI3_REG_CMD 0x7E +#define BMI3_CMD_SOFT_RESET 0xDEAF /* BMI3 Interrupt Output Enable */ -#define BMI3_INT_OUTPUT_DISABLE 0 -#define BMI3_INT_OUTPUT_ENABLE 1 +#define BMI3_INT_OUTPUT_DISABLE 0 +#define BMI3_INT_OUTPUT_ENABLE 1 /* FIFO sensor data length (in word), Accel or Gyro */ -#define BMI3_FIFO_ENTRY 0x3 +#define BMI3_FIFO_ENTRY 0x3 /* Macro to define accelerometer configuration value for FOC */ -#define BMI3_FOC_ACC_CONF_VAL_LSB 0xB7 -#define BMI3_FOC_ACC_CONF_VAL_MSB 0x40 +#define BMI3_FOC_ACC_CONF_VAL_LSB 0xB7 +#define BMI3_FOC_ACC_CONF_VAL_MSB 0x40 /* Macro to define the accel FOC range */ -#define BMI3_ACC_FOC_2G_REF 16384 -#define BMI3_ACC_FOC_4G_REF 8192 -#define BMI3_ACC_FOC_8G_REF 4096 -#define BMI3_ACC_FOC_16G_REF 2048 -#define BMI3_FOC_SAMPLE_LIMIT 32 +#define BMI3_ACC_FOC_2G_REF 16384 +#define BMI3_ACC_FOC_4G_REF 8192 +#define BMI3_ACC_FOC_8G_REF 4096 +#define BMI3_ACC_FOC_16G_REF 2048 +#define BMI3_FOC_SAMPLE_LIMIT 32 -#define FOC_TRY_COUNT 5 +#define FOC_TRY_COUNT 5 /* 20ms delay for 50Hz ODR */ -#define FOC_DELAY 20 -#define OFFSET_UPDATE_DELAY 120 -#define BMI3_INT_STATUS_FWM 0x4000 -#define BMI3_INT_STATUS_FFULL 0x8000 -#define BMI3_INT_STATUS_ORIENTATION 0x0008 +#define FOC_DELAY 20 +#define OFFSET_UPDATE_DELAY 120 +#define BMI3_INT_STATUS_FWM 0x4000 +#define BMI3_INT_STATUS_FFULL 0x8000 +#define BMI3_INT_STATUS_ORIENTATION 0x0008 - -#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME 0x7f02 -#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME 0x7f01 +#define BMI3_FIFO_GYRO_I2C_SYNC_FRAME 0x7f02 +#define BMI3_FIFO_ACCEL_I2C_SYNC_FRAME 0x7f01 /* Gyro self calibration address */ -#define BMI3_BASE_ADDR_SC 0x26 -#define BMI3_CMD_SELF_CALIB 0x0101 +#define BMI3_BASE_ADDR_SC 0x26 +#define BMI3_CMD_SELF_CALIB 0x0101 /* Feature engine General purpose register 1. */ -#define BMI3_FEATURE_IO_0 0x10 -#define BMI3_ANY_MOTION_X_EN_MASK 0x08 +#define BMI3_FEATURE_IO_0 0x10 +#define BMI3_ANY_MOTION_X_EN_MASK 0x08 -#define BMI3_FEATURE_IO_1 0x11 -#define BMI3_FEATURE_IO_1_ERROR_MASK 0x0F -#define BMI3_FEATURE_IO_1_NO_ERROR 0x05 -#define BMI3_SC_ST_STATUS_MASK 0x10 -#define BMI3_SC_RESULT_MASK 0x20 -#define BMI3_UGAIN_OFFS_UPD_COMPLETE 0x01 +#define BMI3_FEATURE_IO_1 0x11 +#define BMI3_FEATURE_IO_1_ERROR_MASK 0x0F +#define BMI3_FEATURE_IO_1_NO_ERROR 0x05 +#define BMI3_SC_ST_STATUS_MASK 0x10 +#define BMI3_SC_RESULT_MASK 0x20 +#define BMI3_UGAIN_OFFS_UPD_COMPLETE 0x01 -#define BMI3_FEATURE_IO_STATUS 0x14 +#define BMI3_FEATURE_IO_STATUS 0x14 /* * The max positive value of accel data is 0x7FFF, equal to range(g) * So, in order to get +1g, divide the 0x7FFF by range */ -#define BMI3_ACC_DATA_PLUS_1G(range) (0x7FFF / (range)) +#define BMI3_ACC_DATA_PLUS_1G(range) (0x7FFF / (range)) #define BMI3_ACC_DATA_MINUS_1G(range) (-BMI3_ACC_DATA_PLUS_1G(range)) /* Offset DMA registers */ -#define BMI3_ACC_OFFSET_ADDR 0x40 -#define BMI3_GYRO_OFFSET_ADDR 0x46 +#define BMI3_ACC_OFFSET_ADDR 0x40 +#define BMI3_GYRO_OFFSET_ADDR 0x46 /* * Start address of the DMA transaction. Has to be written to initiate a * transaction. */ -#define BMI3_FEATURE_ENGINE_DMA_TX 0x41 +#define BMI3_FEATURE_ENGINE_DMA_TX 0x41 /* DMA read/write data. On read transaction expect first word to be zero. */ -#define BMI3_FEATURE_ENGINE_DMA_TX_DATA 0x42 +#define BMI3_FEATURE_ENGINE_DMA_TX_DATA 0x42 /* Command for offset update */ -#define BMI3_CMD_USR_GAIN_OFFS_UPDATE 0x301 +#define BMI3_CMD_USR_GAIN_OFFS_UPDATE 0x301 /* 1LSB - 31 Micro-G */ -#define BMI3_OFFSET_ACC_MULTI_MG (31 * 1000) +#define BMI3_OFFSET_ACC_MULTI_MG (31 * 1000) /* 1LSB = 61 milli-dps*/ -#define BMI3_OFFSET_GYR_MDPS (61 * 1000) +#define BMI3_OFFSET_GYR_MDPS (61 * 1000) -#define BMI3_FIFO_BUFFER 32 +#define BMI3_FIFO_BUFFER 32 /* General Macro Definitions */ /* LSB and MSB mask definitions */ -#define BMI3_SET_LOW_BYTE 0x00FF -#define BMI3_SET_HIGH_BYTE 0xFF00 +#define BMI3_SET_LOW_BYTE 0x00FF +#define BMI3_SET_HIGH_BYTE 0xFF00 /* For enable and disable */ -#define BMI3_ENABLE 0x1 -#define BMI3_DISABLE 0x0 +#define BMI3_ENABLE 0x1 +#define BMI3_DISABLE 0x0 /* Defines mode of operation for Accelerometer */ -#define BMI3_POWER_MODE_MASK 0x70 -#define BMI3_POWER_MODE_POS 4 +#define BMI3_POWER_MODE_MASK 0x70 +#define BMI3_POWER_MODE_POS 4 -#define BMI3_SENS_ODR_MASK 0x0F +#define BMI3_SENS_ODR_MASK 0x0F /* Full scale, Resolution */ -#define BMI3_SENS_RANGE_MASK 0x70 -#define BMI3_SENS_RANGE_POS 4 +#define BMI3_SENS_RANGE_MASK 0x70 +#define BMI3_SENS_RANGE_POS 4 -#define BMI3_CHIP_ID_MASK 0xFF +#define BMI3_CHIP_ID_MASK 0xFF /* Map FIFO water-mark interrupt to either INT1 or INT2 or IBI */ -#define BMI3_FWM_INT_MASK 0x30 -#define BMI3_FWM_INT_POS 4 +#define BMI3_FWM_INT_MASK 0x30 +#define BMI3_FWM_INT_POS 4 /* Map FIFO full interrupt to either INT1 or INT2 or IBI */ -#define BMI3_FFULL_INT_MASK 0xC0 -#define BMI3_FFULL_INT_POS 6 - -#define BMI3_ORIENT_INT_MASK 0xC0 -#define BMI3_ORIENT_INT_POS 6 - +#define BMI3_FFULL_INT_MASK 0xC0 +#define BMI3_FFULL_INT_POS 6 +#define BMI3_ORIENT_INT_MASK 0xC0 +#define BMI3_ORIENT_INT_POS 6 /* Mask definitions for interrupt pin configuration */ -#define BMI3_INT_LATCH_MASK 0x0001 +#define BMI3_INT_LATCH_MASK 0x0001 /** * Current fill level of FIFO buffer @@ -210,7 +207,7 @@ * fifo_flush. The word counter is updated each time a complete frame was read * or written. */ -#define BMI3_FIFO_FILL_LVL_MASK 0x07FF +#define BMI3_FIFO_FILL_LVL_MASK 0x07FF /* Enum to define interrupt lines */ enum bmi3_hw_int_pin { @@ -236,24 +233,21 @@ enum sensor_index_t { NUM_OF_PRIMARY_SENSOR, }; -#define BMI3_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI3_DRDY_MASK(_sensor) (1 << BMI3_DRDY_OFF(_sensor)) +#define BMI3_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI3_DRDY_MASK(_sensor) (1 << BMI3_DRDY_OFF(_sensor)) /* Utility macros */ -#define BMI3_SET_BITS(reg_data, bitname, data) \ - ((reg_data & ~(bitname##_MASK)) | \ - ((data << bitname##_POS) & bitname##_MASK)) +#define BMI3_SET_BITS(reg_data, bitname, data) \ + ((reg_data & ~(bitname##_MASK)) | \ + ((data << bitname##_POS) & bitname##_MASK)) -#define BMI3_GET_BITS(reg_data, bitname) \ - ((reg_data & (bitname##_MASK)) >> \ - (bitname##_POS)) +#define BMI3_GET_BITS(reg_data, bitname) \ + ((reg_data & (bitname##_MASK)) >> (bitname##_POS)) -#define BMI3_SET_BIT_POS0(reg_data, bitname, data) \ - ((reg_data & ~(bitname##_MASK)) | \ - (data & bitname##_MASK)) +#define BMI3_SET_BIT_POS0(reg_data, bitname, data) \ + ((reg_data & ~(bitname##_MASK)) | (data & bitname##_MASK)) -#define BMI3_GET_BIT_POS0(reg_data, bitname) \ - (reg_data & (bitname##_MASK)) +#define BMI3_GET_BIT_POS0(reg_data, bitname) (reg_data & (bitname##_MASK)) extern const struct accelgyro_drv bmi3xx_drv; @@ -274,9 +268,9 @@ void bmi3xx_interrupt(enum gpio_signal signal); * bmi3xx-int = &base_accel; * }; */ -#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \ +#define CONFIG_ACCELGYRO_BMI3XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi3xx_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI3XX_H */ -- cgit v1.2.1 From f564c9de4df2b41648dd7bb400972fd0e902cce9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:39 -0600 Subject: chip/mec1322/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0aa318eabe908729875a6d180670582957145be8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729315 Reviewed-by: Jeremy Bettis --- chip/mec1322/clock.c | 66 ++++++++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 38 deletions(-) diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index ce07284891..1fcf8fd199 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -24,13 +24,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) #ifdef CONFIG_LOW_POWER_IDLE /* Recovery time for HvySlp2 is 0 usec */ -#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 +#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 -#define SET_HTIMER_DELAY_USEC 200 +#define SET_HTIMER_DELAY_USEC 200 static int idle_sleep_cnt; static int idle_dsleep_cnt; @@ -40,7 +40,7 @@ static uint64_t total_idle_dsleep_time_us; * Fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the heavy sleep mode is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) static int console_in_use_timeout_sec = 60; static timestamp_t console_expire_time; #endif /*CONFIG_LOW_POWER_IDLE */ @@ -50,7 +50,8 @@ static int freq = 48000000; void clock_wait_cycles(uint32_t cycles) { asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); + " bne 1b\n" + : "+r"(cycles)); } int clock_get_freq(void) @@ -104,8 +105,8 @@ DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); static void htimer_init(void) { MEC1322_INT_BLK_EN |= BIT(17); - MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ - MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ + MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ + MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ task_enable_irq(MEC1322_IRQ_HTIMER); } @@ -120,7 +121,6 @@ static void htimer_init(void) static void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds) { if (seconds || microseconds) { - if (seconds > 2) { /* count from 2 sec to 2 hrs, mec1322 sec 18.10.2 */ ASSERT(seconds <= 0xffff / 8); @@ -154,19 +154,18 @@ static timestamp_t system_get_htimer(void) uint16_t count; timestamp_t time; - count = MEC1322_HTIMER_COUNT; - + count = MEC1322_HTIMER_COUNT; if (MEC1322_HTIMER_CONTROL == 1) /* if > 2 sec */ /* 0.125 sec per count */ time.le.lo = (uint32_t)(count * 125000); - else /* if < 2 sec */ + else /* if < 2 sec */ /* 30.5(=61/2)usec per count */ time.le.lo = (uint32_t)(count * 61 / 2); time.le.hi = 0; - return time; /* in uSec */ + return time; /* in uSec */ } /** @@ -220,7 +219,7 @@ static void prepare_for_deep_sleep(void) MEC1322_LPC_ACT = 0x0; #endif - MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ + MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ CPU_NVIC_ST_CTRL &= ~ST_TICKINT; /* SYS_TICK_INT_DISABLE */ } @@ -248,7 +247,7 @@ static void resume_from_deep_sleep(void) MEC1322_PCR_HOST_SLP_EN &= MEC1322_PCR_HOST_SLP_EN_WAKE; MEC1322_PCR_EC_SLP_EN2 &= MEC1322_PCR_EC_SLP_EN2_WAKE; - MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ + MEC1322_PCR_SYS_SLP_CTL = 0xF8; /* default */ #ifndef CONFIG_POWER_S0IX /* Enable LPC */ @@ -256,7 +255,6 @@ static void resume_from_deep_sleep(void) #endif } - void clock_refresh_console_in_use(void) { disable_sleep(SLEEP_MASK_CONSOLE); @@ -284,7 +282,6 @@ void __idle(void) disable_sleep(SLEEP_MASK_CONSOLE); console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; - /* * Print when the idle task starts. This is the lowest priority task, * so this only starts once all other tasks have gotten a chance to do @@ -296,7 +293,7 @@ void __idle(void) /* Disable interrupts */ interrupt_disable(); - t0 = get_time(); /* uSec */ + t0 = get_time(); /* uSec */ /* __hw_clock_event_get() is next programmed timer event */ next_delay = __hw_clock_event_get() - t0.le.lo; @@ -308,14 +305,12 @@ void __idle(void) /* check if there enough time for deep sleep */ if (DEEP_SLEEP_ALLOWED && time_for_dsleep) { - - /* * Check if the console use has expired and console * sleep is masked by GPIO(UART-RX) interrupt. */ if ((sleep_mask & SLEEP_MASK_CONSOLE) && - t0.val > console_expire_time.val) { + t0.val > console_expire_time.val) { /* allow console to sleep. */ enable_sleep(SLEEP_MASK_CONSOLE); @@ -330,11 +325,10 @@ void __idle(void) CPRINTS("Disable console in deepsleep"); } - /* UART is not being used */ - uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED - && !uart_tx_in_progress() - && uart_buffer_empty(); + uart_ready_for_deepsleep = + LOW_SPEED_DEEP_SLEEP_ALLOWED && + !uart_tx_in_progress() && uart_buffer_empty(); /* * Since MEC1322's heavysleep modes requires all block @@ -342,7 +336,6 @@ void __idle(void) * decision factor of heavysleep of EC. */ if (uart_ready_for_deepsleep) { - idle_dsleep_cnt++; /* @@ -372,7 +365,6 @@ void __idle(void) asm("wfi"); if (uart_ready_for_deepsleep) { - resume_from_deep_sleep(); /* @@ -390,8 +382,8 @@ void __idle(void) /* disable/clear htimer wakeup interrupt */ system_reset_htimer_alarm(); - t1.val = t0.val + - (uint64_t)(max_sleep_time - ht_t1.le.lo); + t1.val = t0.val + (uint64_t)(max_sleep_time - + ht_t1.le.lo); force_time(t1); @@ -400,7 +392,8 @@ void __idle(void) /* Record time spent in deep sleep. */ total_idle_dsleep_time_us += - (uint64_t)(max_sleep_time - ht_t1.le.lo); + (uint64_t)(max_sleep_time - + ht_t1.le.lo); } } else { /* CPU 'Sleep' mode */ @@ -408,7 +401,6 @@ void __idle(void) idle_sleep_cnt++; asm("wfi"); - } interrupt_enable(); @@ -427,12 +419,11 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n", - total_idle_dsleep_time_us); + total_idle_dsleep_time_us); ccprintf("Total time on: %.6llds\n\n", ts.val); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* defined(CONFIG_CMD_IDLE_STATS) */ @@ -449,9 +440,9 @@ static int command_dsleep(int argc, char **argv) * Force deep sleep not to use heavy sleep mode or * allow it to use the heavy sleep mode. */ - if (v) /* 'on' */ + if (v) /* 'on' */ disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); - else /* 'off' */ + else /* 'off' */ enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); } else { /* Set console in use timeout. */ @@ -469,12 +460,11 @@ static int command_dsleep(int argc, char **argv) ccprintf("Sleep mask: %08x\n", sleep_mask); ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); + console_in_use_timeout_sec); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | sec]", +DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | sec]", "Deep sleep clock settings:\nUse 'on' to force deep " "sleep NOT to enter heavysleep mode.\nUse 'off' to " "allow deep sleep to use heavysleep whenever conditions" -- cgit v1.2.1 From 212969bbc4ddfb1f198d299e5621b333518df05e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:30 -0600 Subject: extra/lightbar/windows.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0545f6f73077099ebe5d7a777561772ef3ccfddb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730183 Reviewed-by: Jeremy Bettis --- extra/lightbar/windows.c | 49 +++++++++++++++++++++--------------------------- 1 file changed, 21 insertions(+), 28 deletions(-) diff --git a/extra/lightbar/windows.c b/extra/lightbar/windows.c index 115074363c..cd12a8ffd0 100644 --- a/extra/lightbar/windows.c +++ b/extra/lightbar/windows.c @@ -42,8 +42,8 @@ void init_windows(void) /* Get a colormap */ colormap_id = xcb_generate_id(c); - xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE, - colormap_id, screen->root, screen->root_visual); + xcb_create_colormap(c, XCB_COLORMAP_ALLOC_NONE, colormap_id, + screen->root, screen->root_visual); /* Create foreground GC */ foreground = xcb_generate_id(c); @@ -57,16 +57,16 @@ void init_windows(void) mask = XCB_CW_BACK_PIXEL | XCB_CW_EVENT_MASK; values[0] = screen->black_pixel; values[1] = XCB_EVENT_MASK_EXPOSURE | XCB_EVENT_MASK_BUTTON_PRESS; - xcb_create_window(c, /* Connection */ - XCB_COPY_FROM_PARENT, /* depth */ - win, /* window Id */ - screen->root, /* parent window */ - 0, 0, /* x, y */ - win_w, win_h, /* width, height */ - 10, /* border_width */ + xcb_create_window(c, /* Connection */ + XCB_COPY_FROM_PARENT, /* depth */ + win, /* window Id */ + screen->root, /* parent window */ + 0, 0, /* x, y */ + win_w, win_h, /* width, height */ + 10, /* border_width */ XCB_WINDOW_CLASS_INPUT_OUTPUT, /* class */ - screen->root_visual, /* visual */ - mask, values); /* masks */ + screen->root_visual, /* visual */ + mask, values); /* masks */ /* Map the window on the screen */ xcb_map_window(c, win); @@ -88,10 +88,10 @@ void cleanup(void) /* xcb likes 16-bit colors */ uint16_t leds[NUM_LEDS][3] = { - {0xffff, 0x0000, 0x0000}, - {0x0000, 0xffff, 0x0000}, - {0x0000, 0x0000, 0xffff}, - {0xffff, 0xffff, 0x0000}, + { 0xffff, 0x0000, 0x0000 }, + { 0x0000, 0xffff, 0x0000 }, + { 0x0000, 0x0000, 0xffff }, + { 0xffff, 0xffff, 0x0000 }, }; pthread_mutex_t leds_mutex = PTHREAD_MUTEX_INITIALIZER; @@ -101,10 +101,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue) uint32_t values[2]; xcb_alloc_color_reply_t *reply; - reply = xcb_alloc_color_reply(c, - xcb_alloc_color(c, colormap_id, - red, green, blue), - NULL); + reply = xcb_alloc_color_reply( + c, xcb_alloc_color(c, colormap_id, red, green, blue), NULL); assert(reply); mask = XCB_GC_FOREGROUND; @@ -116,8 +114,8 @@ void change_gc_color(uint16_t red, uint16_t green, uint16_t blue) void update_window(void) { xcb_segment_t segments[] = { - {0, 0, win_w, win_h}, - {0, win_h, win_w, 0}, + { 0, 0, win_w, win_h }, + { 0, win_h, win_w, 0 }, }; xcb_rectangle_t rect; int w = win_w / NUM_LEDS; @@ -135,8 +133,7 @@ void update_window(void) rect.width = w; rect.height = win_h; - change_gc_color(copyleds[i][0], - copyleds[i][1], + change_gc_color(copyleds[i][0], copyleds[i][1], copyleds[i][2]); xcb_poly_fill_rectangle(c, win, foreground, 1, &rect); @@ -184,8 +181,6 @@ void setrgb(int led, int red, int green, int blue) /*****************************************************************************/ /* lb_common stubs */ - - /* Brightness serves no purpose here. It's automatic on the Chromebook. */ static int brightness = 0xc0; void lb_set_brightness(unsigned int newval) @@ -238,14 +233,13 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out) printf("lightbar is %s\n", fake_power ? "on" : "off"); memset(out, fake_power, sizeof(*out)); }; -void lb_hc_cmd_reg(const struct ec_params_lightbar *in) { }; +void lb_hc_cmd_reg(const struct ec_params_lightbar *in){}; int lb_power(int enabled) { return fake_power; } - /*****************************************************************************/ /* Event handling stuff */ @@ -257,7 +251,6 @@ void *entry_windows(void *ptr) int chg = 1; while ((e = xcb_wait_for_event(c))) { - switch (e->response_type & ~0x80) { case XCB_EXPOSE: ev = (xcb_expose_event_t *)e; -- cgit v1.2.1 From 352f5cde6114ba132e3e7f8f0d913b4fd36d1ff3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:55 -0600 Subject: test/utils.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ica9779144679a2180d85e754c94aae1508b75f2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730316 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/utils.c | 55 +++++++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/test/utils.c b/test/utils.c index 3fc70cdc75..88d79d2e55 100644 --- a/test/utils.c +++ b/test/utils.c @@ -32,16 +32,16 @@ static int test_memmove(void) t0 = get_time(); for (i = 0; i < iteration; ++i) - memmove(buf + 101, buf, len); /* unaligned */ + memmove(buf + 101, buf, len); /* unaligned */ t1 = get_time(); TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); t2 = get_time(); for (i = 0; i < iteration; ++i) - memmove(buf + 100, buf, len); /* aligned */ + memmove(buf + 100, buf, len); /* aligned */ t3 = get_time(); - ccprintf(" %" PRId64 " us) ", t3.val-t2.val); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len); if (!IS_ENABLED(EMU_BUILD)) @@ -77,16 +77,16 @@ static int test_memcpy(void) t0 = get_time(); for (i = 0; i < iteration; ++i) - memcpy(buf + dest_offset + 1, buf, len); /* unaligned */ + memcpy(buf + dest_offset + 1, buf, len); /* unaligned */ t1 = get_time(); TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); t2 = get_time(); for (i = 0; i < iteration; ++i) - memcpy(buf + dest_offset, buf, len); /* aligned */ + memcpy(buf + dest_offset, buf, len); /* aligned */ t3 = get_time(); - ccprintf(" %" PRId64 " us) ", t3.val-t2.val); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len); if (!IS_ENABLED(EMU_BUILD)) @@ -136,14 +136,14 @@ static int test_memset(void) dumb_memset(buf, 1, len); t1 = get_time(); TEST_ASSERT_MEMSET(buf, (char)1, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val-t0.val); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); t2 = get_time(); for (i = 0; i < iteration; ++i) memset(buf, 1, len); t3 = get_time(); TEST_ASSERT_MEMSET(buf, (char)1, len); - ccprintf(" %" PRId64 " us) ", t3.val-t2.val); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); if (!IS_ENABLED(EMU_BUILD)) TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); @@ -361,25 +361,24 @@ static int test_mula32(void) } t1 = get_time(); - ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n", - i, (uint32_t)(r >> 32), (uint32_t)r, - (uint32_t)(r2 >> 32), (uint32_t)r2, t1.le.lo-t0.le.lo); - TEST_ASSERT(r == 0x9df59b9fb0ab9d96L); + ccprintf("After %d iterations, r=%08x%08x, r2=%08x%08x (time: %d)\n", i, + (uint32_t)(r >> 32), (uint32_t)r, (uint32_t)(r2 >> 32), + (uint32_t)r2, t1.le.lo - t0.le.lo); + TEST_ASSERT(r == 0x9df59b9fb0ab9d96L); TEST_ASSERT(r2 == 0x9df59b9fb0beabd6L); /* well okay then */ return EC_SUCCESS; } -#define SWAP_TEST_HARNESS(t, x, y) \ - do { \ - t a = x, b = y; \ - swap(a, b); \ +#define SWAP_TEST_HARNESS(t, x, y) \ + do { \ + t a = x, b = y; \ + swap(a, b); \ TEST_ASSERT(a == y); \ TEST_ASSERT(b == x); \ } while (0) - static int test_swap(void) { SWAP_TEST_HARNESS(uint8_t, UINT8_MAX, 0); @@ -455,15 +454,15 @@ test_static int test_alignment_log2(void) test_static int test_binary_first_base3_from_bits(void) { - int n0[] = {0, 0, 0}; /* LSB first */ - int n7[] = {1, 1, 1}; - int n8[] = {2, 0, 0}; - int n9[] = {2, 1, 0}; - int n10[] = {0, 2, 0}; - int n11[] = {1, 2, 0}; - int n18[] = {0, 0, 2}; - int n26[] = {2, 2, 2}; - int n38[] = {1, 2, 0, 1}; + int n0[] = { 0, 0, 0 }; /* LSB first */ + int n7[] = { 1, 1, 1 }; + int n8[] = { 2, 0, 0 }; + int n9[] = { 2, 1, 0 }; + int n10[] = { 0, 2, 0 }; + int n11[] = { 1, 2, 0 }; + int n18[] = { 0, 0, 2 }; + int n26[] = { 2, 2, 2 }; + int n38[] = { 1, 2, 0, 1 }; TEST_EQ(binary_first_base3_from_bits(n0, ARRAY_SIZE(n0)), 0, "%d"); TEST_EQ(binary_first_base3_from_bits(n7, ARRAY_SIZE(n7)), 7, "%d"); -- cgit v1.2.1 From 1ceade6e65668d87ce26764333bbdd4353a906a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:37 -0600 Subject: driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1529ff75a7038fa96b37d3cf43767a60e06480a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729971 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/bep/fpc_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/fingerprint/fpc/bep/fpc_private.h b/driver/fingerprint/fpc/bep/fpc_private.h index 1c01d61207..48c9f5b092 100644 --- a/driver/fingerprint/fpc/bep/fpc_private.h +++ b/driver/fingerprint/fpc/bep/fpc_private.h @@ -46,4 +46,4 @@ int fp_sensor_maintenance(uint8_t *image_data, */ int fpc_get_hwid(uint16_t *id); -#endif /* __CROS_EC_FPC_PRIVATE_H */ +#endif /* __CROS_EC_FPC_PRIVATE_H */ -- cgit v1.2.1 From a2bd40ce35728eb0fae16d652c0782286e984785 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:10 -0600 Subject: board/elm/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e97239171000b32383de7b264cb698d736d6186 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728311 Reviewed-by: Jeremy Bettis --- board/elm/led.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/elm/led.c b/board/elm/led.c index d73cc05c1b..8d7d83ffaa 100644 --- a/board/elm/led.c +++ b/board/elm/led.c @@ -19,10 +19,8 @@ #define LOW_BATTERY_PERMILLAGE 137 #define FULL_BATTERY_PERMILLAGE 937 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -31,7 +29,7 @@ enum led_color { BAT_LED_ORANGE, PWR_LED_BLUE, PWR_LED_ORANGE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int bat_led_set(enum led_color color, int on) @@ -111,8 +109,7 @@ static void elm_led_set_power(void) bat_led_set(PWR_LED_ORANGE, 0); } else if (chipset_in_state(CHIPSET_STATE_SUSPEND)) { bat_led_set(PWR_LED_BLUE, 0); - bat_led_set(PWR_LED_ORANGE, - (blink_second & 3) ? 0 : 1); + bat_led_set(PWR_LED_ORANGE, (blink_second & 3) ? 0 : 1); } } @@ -135,8 +132,9 @@ static void elm_led_set_battery(void) /* Make the percentage approximate to UI shown */ remaining_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP); full_charge_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC); - permillage = !full_charge_capacity ? 0 : - (1000 * remaining_capacity) / full_charge_capacity; + permillage = !full_charge_capacity ? + 0 : + (1000 * remaining_capacity) / full_charge_capacity; switch (charge_get_state()) { case PWR_STATE_CHARGE: @@ -156,12 +154,10 @@ static void elm_led_set_battery(void) bat_led_set(BAT_LED_BLUE, 0); if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) && permillage <= CRITICAL_LOW_BATTERY_PERMILLAGE) - bat_led_set(BAT_LED_ORANGE, - (blink_second & 1) ? 0 : 1); + bat_led_set(BAT_LED_ORANGE, (blink_second & 1) ? 0 : 1); else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) && permillage <= LOW_BATTERY_PERMILLAGE) - bat_led_set(BAT_LED_ORANGE, - (blink_second & 3) ? 0 : 1); + bat_led_set(BAT_LED_ORANGE, (blink_second & 3) ? 0 : 1); else bat_led_set(BAT_LED_ORANGE, 0); break; -- cgit v1.2.1 From a201405544a02961b55dec91d1a97421c42abba9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:48 -0600 Subject: chip/ish/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08cdaa5a7a88948b7b8b0cd87b5daea50b148bfe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729182 Reviewed-by: Jeremy Bettis --- chip/ish/hwtimer.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c index 1259dae7f4..b4bb020d39 100644 --- a/chip/ish/hwtimer.c +++ b/chip/ish/hwtimer.c @@ -14,8 +14,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) static uint32_t last_deadline; @@ -37,7 +37,7 @@ static uint32_t last_deadline; /* Scaling helper methods for different ISH chip variants */ #ifdef CHIP_FAMILY_ISH3 #define CLOCK_FACTOR 12 -BUILD_ASSERT(CLOCK_FACTOR * SECOND == ISH_HPET_CLK_FREQ); +BUILD_ASSERT(CLOCK_FACTOR *SECOND == ISH_HPET_CLK_FREQ); static inline uint64_t scale_us2ticks(uint64_t us) { @@ -239,8 +239,7 @@ int __hw_clock_source_init64(uint64_t start_t) /* Timer 1 - IRQ routing */ timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK; - timer1_config |= (ISH_HPET_TIMER1_IRQ << - HPET_Tn_INT_ROUTE_CNF_SHIFT); + timer1_config |= (ISH_HPET_TIMER1_IRQ << HPET_Tn_INT_ROUTE_CNF_SHIFT); /* Level triggered interrupt */ timer1_config |= HPET_Tn_INT_TYPE_CNF; -- cgit v1.2.1 From 0f7b5cb509ed3e1cf9b30301af847600b2a4e22f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:01 -0600 Subject: common/fpsensor/fpsensor_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf4345eee5a8c6c1f19230ef2cfa8da4e5ab1954 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729649 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- common/fpsensor/fpsensor_private.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/fpsensor/fpsensor_private.h b/common/fpsensor/fpsensor_private.h index a42049dece..90ba358244 100644 --- a/common/fpsensor/fpsensor_private.h +++ b/common/fpsensor/fpsensor_private.h @@ -10,8 +10,8 @@ #include -#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args) -#define CPRINTS(format, args...) cprints(CC_FP, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args) +#define CPRINTS(format, args...) cprints(CC_FP, format, ##args) int validate_fp_buffer_offset(uint32_t buffer_size, uint32_t offset, uint32_t size); -- cgit v1.2.1 From 85f9c35c9c76d4d55243f54840c12f3efd1f6baf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:41 -0600 Subject: board/sasukette/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7f55b37d13da42748af61fc462d857bcb45c2f4a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728912 Reviewed-by: Jeremy Bettis --- board/sasukette/led.c | 67 +++++++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 32 deletions(-) diff --git a/board/sasukette/led.c b/board/sasukette/led.c index 28643a7b87..b8db6772d9 100644 --- a/board/sasukette/led.c +++ b/board/sasukette/led.c @@ -13,8 +13,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 1; @@ -22,33 +22,36 @@ __override const int led_charge_lvl_2 = 100; /* Sasukette : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -56,7 +59,7 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -74,7 +77,7 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -118,12 +121,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, - !brightness[EC_LED_COLOR_GREEN]); + !brightness[EC_LED_COLOR_GREEN]); gpio_set_level(GPIO_BAT_LED_RED_L, - !brightness[EC_LED_COLOR_RED]); + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, - !brightness[EC_LED_COLOR_BLUE]); + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 931fb097aa02e2a04dc5361fac50500fb7483c18 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:25 -0600 Subject: test/aes.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I21b3a1415746802606f535101c4622d25c714a9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730488 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/aes.c | 441 +++++++++++++++++++++++++------------------------------------ 1 file changed, 182 insertions(+), 259 deletions(-) diff --git a/test/aes.c b/test/aes.c index 1c71e2874e..c7517c064a 100644 --- a/test/aes.c +++ b/test/aes.c @@ -29,23 +29,18 @@ static uint8_t tmp[512]; /* * Do encryption, put result in |result|, and compare with |ciphertext|. */ -static int test_aes_gcm_encrypt(uint8_t *result, - const uint8_t *key, - int key_size, - const uint8_t *plaintext, - const uint8_t *ciphertext, - int plaintext_size, - const uint8_t *nonce, - int nonce_size, - const uint8_t *tag, - int tag_size) +static int test_aes_gcm_encrypt(uint8_t *result, const uint8_t *key, + int key_size, const uint8_t *plaintext, + const uint8_t *ciphertext, int plaintext_size, + const uint8_t *nonce, int nonce_size, + const uint8_t *tag, int tag_size) { static AES_KEY aes_key; static GCM128_CONTEXT ctx; TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0); - CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0); + CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0); CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size); TEST_ASSERT(CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, result, plaintext_size)); @@ -58,23 +53,18 @@ static int test_aes_gcm_encrypt(uint8_t *result, /* * Do decryption, put result in |result|, and compare with |plaintext|. */ -static int test_aes_gcm_decrypt(uint8_t *result, - const uint8_t *key, - int key_size, - const uint8_t *plaintext, - const uint8_t *ciphertext, - int plaintext_size, - const uint8_t *nonce, - int nonce_size, - const uint8_t *tag, - int tag_size) +static int test_aes_gcm_decrypt(uint8_t *result, const uint8_t *key, + int key_size, const uint8_t *plaintext, + const uint8_t *ciphertext, int plaintext_size, + const uint8_t *nonce, int nonce_size, + const uint8_t *tag, int tag_size) { static AES_KEY aes_key; static GCM128_CONTEXT ctx; TEST_ASSERT(AES_set_encrypt_key(key, 8 * key_size, &aes_key) == 0); - CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f) AES_encrypt, 0); + CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0); CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size); TEST_ASSERT(CRYPTO_gcm128_decrypt(&ctx, &aes_key, ciphertext, result, plaintext_size)); @@ -84,17 +74,13 @@ static int test_aes_gcm_decrypt(uint8_t *result, return EC_SUCCESS; } -static int test_aes_gcm_raw_inplace(const uint8_t *key, - int key_size, +static int test_aes_gcm_raw_inplace(const uint8_t *key, int key_size, const uint8_t *plaintext, const uint8_t *ciphertext, - int plaintext_size, - const uint8_t *nonce, - int nonce_size, - const uint8_t *tag, + int plaintext_size, const uint8_t *nonce, + int nonce_size, const uint8_t *tag, int tag_size) { - /* * Make copies that will be clobbered during in-place encryption or * decryption. @@ -105,95 +91,53 @@ static int test_aes_gcm_raw_inplace(const uint8_t *key, memcpy(plaintext_copy, plaintext, plaintext_size); memcpy(ciphertext_copy, ciphertext, plaintext_size); - TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy, - key, - key_size, - plaintext_copy, - ciphertext, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_encrypt(plaintext_copy, key, key_size, + plaintext_copy, ciphertext, + plaintext_size, nonce, nonce_size, tag, tag_size) == EC_SUCCESS); - TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy, - key, - key_size, - plaintext, - ciphertext_copy, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_decrypt(ciphertext_copy, key, key_size, + plaintext, ciphertext_copy, + plaintext_size, nonce, nonce_size, tag, tag_size) == EC_SUCCESS); return EC_SUCCESS; } -static int test_aes_gcm_raw_non_inplace(const uint8_t *key, - int key_size, +static int test_aes_gcm_raw_non_inplace(const uint8_t *key, int key_size, const uint8_t *plaintext, const uint8_t *ciphertext, int plaintext_size, - const uint8_t *nonce, - int nonce_size, - const uint8_t *tag, - int tag_size) + const uint8_t *nonce, int nonce_size, + const uint8_t *tag, int tag_size) { - TEST_ASSERT(test_aes_gcm_encrypt(tmp, - key, - key_size, - plaintext, - ciphertext, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_encrypt(tmp, key, key_size, plaintext, + ciphertext, plaintext_size, nonce, + nonce_size, tag, tag_size) == EC_SUCCESS); - TEST_ASSERT(test_aes_gcm_decrypt(tmp, - key, - key_size, - plaintext, - ciphertext, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_decrypt(tmp, key, key_size, plaintext, + ciphertext, plaintext_size, nonce, + nonce_size, tag, tag_size) == EC_SUCCESS); return EC_SUCCESS; } -static int test_aes_gcm_raw(const uint8_t *key, - int key_size, - const uint8_t *plaintext, - const uint8_t *ciphertext, - int plaintext_size, - const uint8_t *nonce, - int nonce_size, - const uint8_t *tag, - int tag_size) +static int test_aes_gcm_raw(const uint8_t *key, int key_size, + const uint8_t *plaintext, const uint8_t *ciphertext, + int plaintext_size, const uint8_t *nonce, + int nonce_size, const uint8_t *tag, int tag_size) { TEST_ASSERT(plaintext_size <= sizeof(tmp)); - TEST_ASSERT(test_aes_gcm_raw_non_inplace(key, - key_size, - plaintext, - ciphertext, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_raw_non_inplace(key, key_size, plaintext, + ciphertext, plaintext_size, + nonce, nonce_size, tag, tag_size) == EC_SUCCESS); - TEST_ASSERT(test_aes_gcm_raw_inplace(key, - key_size, - plaintext, - ciphertext, - plaintext_size, - nonce, - nonce_size, - tag, + TEST_ASSERT(test_aes_gcm_raw_inplace(key, key_size, plaintext, + ciphertext, plaintext_size, nonce, + nonce_size, tag, tag_size) == EC_SUCCESS); return EC_SUCCESS; @@ -214,8 +158,8 @@ static int test_aes_gcm(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t nonce1[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t cipher1[] = { 0x03, 0x88, 0xda, 0xce, 0x60, 0xb6, 0xa3, 0x92, @@ -231,28 +175,26 @@ static int test_aes_gcm(void) 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08, }; static const uint8_t plain2[] = { - 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, - 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, - 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, - 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, - 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, - 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, - 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, - 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55, + 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59, + 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53, + 0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, + 0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a, + 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39, + 0x1a, 0xaf, 0xd2, 0x55, }; static const uint8_t nonce2[] = { - 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, - 0xde, 0xca, 0xf8, 0x88, + 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, + 0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88, }; static const uint8_t cipher2[] = { - 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, - 0x4b, 0x72, 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, - 0xe3, 0xaa, 0x21, 0x2f, 0x2c, 0x02, 0xa4, 0xe0, - 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, 0xa1, 0x2e, - 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c, - 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, - 0x1b, 0xa3, 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, - 0x3d, 0x58, 0xe0, 0x91, 0x47, 0x3f, 0x59, 0x85, + 0x42, 0x83, 0x1e, 0xc2, 0x21, 0x77, 0x74, 0x24, 0x4b, 0x72, + 0x21, 0xb7, 0x84, 0xd0, 0xd4, 0x9c, 0xe3, 0xaa, 0x21, 0x2f, + 0x2c, 0x02, 0xa4, 0xe0, 0x35, 0xc1, 0x7e, 0x23, 0x29, 0xac, + 0xa1, 0x2e, 0x21, 0xd5, 0x14, 0xb2, 0x54, 0x66, 0x93, 0x1c, + 0x7d, 0x8f, 0x6a, 0x5a, 0xac, 0x84, 0xaa, 0x05, 0x1b, 0xa3, + 0x0b, 0x39, 0x6a, 0x0a, 0xac, 0x97, 0x3d, 0x58, 0xe0, 0x91, + 0x47, 0x3f, 0x59, 0x85, }; static const uint8_t tag2[] = { 0x4d, 0x5c, 0x2a, 0xf3, 0x27, 0xcd, 0x64, 0xa6, @@ -269,8 +211,8 @@ static int test_aes_gcm(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t nonce3[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t cipher3[] = { 0x98, 0xe7, 0x24, 0x7c, 0x07, 0xf0, 0xfe, 0x41, @@ -287,28 +229,26 @@ static int test_aes_gcm(void) 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, }; static const uint8_t plain4[] = { - 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, - 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, - 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, - 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, - 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, - 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, - 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, - 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55, + 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59, + 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53, + 0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, + 0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a, + 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39, + 0x1a, 0xaf, 0xd2, 0x55, }; static const uint8_t nonce4[] = { - 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, - 0xde, 0xca, 0xf8, 0x88, + 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, + 0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88, }; static const uint8_t cipher4[] = { - 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, - 0xeb, 0x06, 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, - 0x85, 0x9e, 0x1c, 0xea, 0xa6, 0xef, 0xd9, 0x84, - 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, 0xe1, 0x9c, - 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25, - 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, - 0x18, 0xe2, 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, - 0xcc, 0xda, 0x27, 0x10, 0xac, 0xad, 0xe2, 0x56, + 0x39, 0x80, 0xca, 0x0b, 0x3c, 0x00, 0xe8, 0x41, 0xeb, 0x06, + 0xfa, 0xc4, 0x87, 0x2a, 0x27, 0x57, 0x85, 0x9e, 0x1c, 0xea, + 0xa6, 0xef, 0xd9, 0x84, 0x62, 0x85, 0x93, 0xb4, 0x0c, 0xa1, + 0xe1, 0x9c, 0x7d, 0x77, 0x3d, 0x00, 0xc1, 0x44, 0xc5, 0x25, + 0xac, 0x61, 0x9d, 0x18, 0xc8, 0x4a, 0x3f, 0x47, 0x18, 0xe2, + 0x44, 0x8b, 0x2f, 0xe3, 0x24, 0xd9, 0xcc, 0xda, 0x27, 0x10, + 0xac, 0xad, 0xe2, 0x56, }; static const uint8_t tag4[] = { 0x99, 0x24, 0xa7, 0xc8, 0x58, 0x73, 0x36, 0xbf, @@ -326,8 +266,8 @@ static int test_aes_gcm(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t nonce5[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t cipher5[] = { 0xce, 0xa7, 0x40, 0x3d, 0x4d, 0x60, 0x6b, 0x6e, @@ -345,28 +285,26 @@ static int test_aes_gcm(void) 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08, }; static const uint8_t plain6[] = { - 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, - 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, - 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, - 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, - 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, - 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, - 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, - 0xba, 0x63, 0x7b, 0x39, 0x1a, 0xaf, 0xd2, 0x55, + 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, 0xa5, 0x59, + 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, 0x86, 0xa7, 0xa9, 0x53, + 0x15, 0x34, 0xf7, 0xda, 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, + 0x8a, 0x72, 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, 0xb1, 0x6a, + 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39, + 0x1a, 0xaf, 0xd2, 0x55, }; static const uint8_t nonce6[] = { - 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, - 0xde, 0xca, 0xf8, 0x88, + 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, + 0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88, }; static const uint8_t cipher6[] = { - 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, - 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, - 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9, - 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa, - 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, - 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, - 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, - 0xbc, 0xc9, 0xf6, 0x62, 0x89, 0x80, 0x15, 0xad, + 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, 0xf4, 0x7f, + 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, 0x64, 0x3a, 0x8c, 0xdc, + 0xbf, 0xe5, 0xc0, 0xc9, 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, + 0xd1, 0xaa, 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, + 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, 0xc5, 0xf6, + 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, 0xbc, 0xc9, 0xf6, 0x62, + 0x89, 0x80, 0x15, 0xad, }; static const uint8_t tag6[] = { 0xb0, 0x94, 0xda, 0xc5, 0xd9, 0x34, 0x71, 0xbd, @@ -378,90 +316,75 @@ static int test_aes_gcm(void) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t plain7[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; /* This nonce results in 0xfff in counter LSB. */ static const uint8_t nonce7[] = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, }; static const uint8_t cipher7[] = { - 0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a, - 0x2b, 0x64, 0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14, - 0x25, 0xf1, 0x0d, 0x47, 0xa7, 0x5a, 0x5f, 0xce, - 0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a, 0xf2, 0x4f, - 0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70, - 0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18, - 0xa9, 0xae, 0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf, - 0xc6, 0xa7, 0x83, 0x97, 0xb9, 0xa8, 0x5b, 0x49, - 0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67, 0xca, 0xab, - 0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c, - 0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c, - 0xb4, 0xf3, 0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29, - 0xc9, 0xe8, 0xc4, 0xdc, 0x0a, 0x2a, 0x5f, 0xf1, - 0x90, 0x3e, 0x50, 0x15, 0x11, 0x22, 0x13, 0x76, - 0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2, - 0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce, - 0xb0, 0xab, 0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f, - 0x8c, 0x90, 0xbe, 0x40, 0x2d, 0xdf, 0x6d, 0x86, - 0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1, 0x5b, 0xfb, - 0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18, - 0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65, - 0x3c, 0x71, 0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42, - 0x11, 0xf4, 0x2b, 0xae, 0x12, 0xaf, 0x46, 0x2b, - 0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e, 0x36, 0x06, - 0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24, - 0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c, - 0x4b, 0xcc, 0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4, - 0x20, 0xa2, 0xf8, 0xeb, 0x66, 0xdc, 0xf3, 0x64, - 0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69, 0x90, 0x03, - 0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6, - 0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90, - 0x27, 0x83, 0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74, - 0x18, 0x8a, 0x43, 0x9c, 0x7e, 0xbc, 0xc0, 0x67, - 0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2, 0x79, 0x46, - 0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78, + 0x56, 0xb3, 0x37, 0x3c, 0xa9, 0xef, 0x6e, 0x4a, 0x2b, 0x64, + 0xfe, 0x1e, 0x9a, 0x17, 0xb6, 0x14, 0x25, 0xf1, 0x0d, 0x47, + 0xa7, 0x5a, 0x5f, 0xce, 0x13, 0xef, 0xc6, 0xbc, 0x78, 0x4a, + 0xf2, 0x4f, 0x41, 0x41, 0xbd, 0xd4, 0x8c, 0xf7, 0xc7, 0x70, + 0x88, 0x7a, 0xfd, 0x57, 0x3c, 0xca, 0x54, 0x18, 0xa9, 0xae, + 0xff, 0xcd, 0x7c, 0x5c, 0xed, 0xdf, 0xc6, 0xa7, 0x83, 0x97, + 0xb9, 0xa8, 0x5b, 0x49, 0x9d, 0xa5, 0x58, 0x25, 0x72, 0x67, + 0xca, 0xab, 0x2a, 0xd0, 0xb2, 0x3c, 0xa4, 0x76, 0xa5, 0x3c, + 0xb1, 0x7f, 0xb4, 0x1c, 0x4b, 0x8b, 0x47, 0x5c, 0xb4, 0xf3, + 0xf7, 0x16, 0x50, 0x94, 0xc2, 0x29, 0xc9, 0xe8, 0xc4, 0xdc, + 0x0a, 0x2a, 0x5f, 0xf1, 0x90, 0x3e, 0x50, 0x15, 0x11, 0x22, + 0x13, 0x76, 0xa1, 0xcd, 0xb8, 0x36, 0x4c, 0x50, 0x61, 0xa2, + 0x0c, 0xae, 0x74, 0xbc, 0x4a, 0xcd, 0x76, 0xce, 0xb0, 0xab, + 0xc9, 0xfd, 0x32, 0x17, 0xef, 0x9f, 0x8c, 0x90, 0xbe, 0x40, + 0x2d, 0xdf, 0x6d, 0x86, 0x97, 0xf4, 0xf8, 0x80, 0xdf, 0xf1, + 0x5b, 0xfb, 0x7a, 0x6b, 0x28, 0x24, 0x1e, 0xc8, 0xfe, 0x18, + 0x3c, 0x2d, 0x59, 0xe3, 0xf9, 0xdf, 0xff, 0x65, 0x3c, 0x71, + 0x26, 0xf0, 0xac, 0xb9, 0xe6, 0x42, 0x11, 0xf4, 0x2b, 0xae, + 0x12, 0xaf, 0x46, 0x2b, 0x10, 0x70, 0xbe, 0xf1, 0xab, 0x5e, + 0x36, 0x06, 0x87, 0x2c, 0xa1, 0x0d, 0xee, 0x15, 0xb3, 0x24, + 0x9b, 0x1a, 0x1b, 0x95, 0x8f, 0x23, 0x13, 0x4c, 0x4b, 0xcc, + 0xb7, 0xd0, 0x32, 0x00, 0xbc, 0xe4, 0x20, 0xa2, 0xf8, 0xeb, + 0x66, 0xdc, 0xf3, 0x64, 0x4d, 0x14, 0x23, 0xc1, 0xb5, 0x69, + 0x90, 0x03, 0xc1, 0x3e, 0xce, 0xf4, 0xbf, 0x38, 0xa3, 0xb6, + 0x0e, 0xed, 0xc3, 0x40, 0x33, 0xba, 0xc1, 0x90, 0x27, 0x83, + 0xdc, 0x6d, 0x89, 0xe2, 0xe7, 0x74, 0x18, 0x8a, 0x43, 0x9c, + 0x7e, 0xbc, 0xc0, 0x67, 0x2d, 0xbd, 0xa4, 0xdd, 0xcf, 0xb2, + 0x79, 0x46, 0x13, 0xb0, 0xbe, 0x41, 0x31, 0x5e, 0xf7, 0x78, 0x70, 0x8a, 0x70, 0xee, 0x7d, 0x75, 0x16, 0x5c, }; static const uint8_t tag7[] = { @@ -469,27 +392,27 @@ static int test_aes_gcm(void) 0xb0, 0x26, 0xa9, 0xed, 0x3f, 0xe1, 0xe8, 0x5f, }; - TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1), - plain1, cipher1, sizeof(plain1), - nonce1, sizeof(nonce1), tag1, sizeof(tag1))); - TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2), - plain2, cipher2, sizeof(plain2), - nonce2, sizeof(nonce2), tag2, sizeof(tag2))); - TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3), - plain3, cipher3, sizeof(plain3), - nonce3, sizeof(nonce3), tag3, sizeof(tag3))); - TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4), - plain4, cipher4, sizeof(plain4), - nonce4, sizeof(nonce4), tag4, sizeof(tag4))); - TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5), - plain5, cipher5, sizeof(plain5), - nonce5, sizeof(nonce5), tag5, sizeof(tag5))); - TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6), - plain6, cipher6, sizeof(plain6), - nonce6, sizeof(nonce6), tag6, sizeof(tag6))); - TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7), - plain7, cipher7, sizeof(plain7), - nonce7, sizeof(nonce7), tag7, sizeof(tag7))); + TEST_ASSERT(!test_aes_gcm_raw(key1, sizeof(key1), plain1, cipher1, + sizeof(plain1), nonce1, sizeof(nonce1), + tag1, sizeof(tag1))); + TEST_ASSERT(!test_aes_gcm_raw(key2, sizeof(key2), plain2, cipher2, + sizeof(plain2), nonce2, sizeof(nonce2), + tag2, sizeof(tag2))); + TEST_ASSERT(!test_aes_gcm_raw(key3, sizeof(key3), plain3, cipher3, + sizeof(plain3), nonce3, sizeof(nonce3), + tag3, sizeof(tag3))); + TEST_ASSERT(!test_aes_gcm_raw(key4, sizeof(key4), plain4, cipher4, + sizeof(plain4), nonce4, sizeof(nonce4), + tag4, sizeof(tag4))); + TEST_ASSERT(!test_aes_gcm_raw(key5, sizeof(key5), plain5, cipher5, + sizeof(plain5), nonce5, sizeof(nonce5), + tag5, sizeof(tag5))); + TEST_ASSERT(!test_aes_gcm_raw(key6, sizeof(key6), plain6, cipher6, + sizeof(plain6), nonce6, sizeof(nonce6), + tag6, sizeof(tag6))); + TEST_ASSERT(!test_aes_gcm_raw(key7, sizeof(key7), plain7, cipher7, + sizeof(plain7), nonce7, sizeof(nonce7), + tag7, sizeof(tag7))); return EC_SUCCESS; } @@ -505,11 +428,11 @@ static void test_aes_gcm_speed(void) static const uint8_t plaintext[512] = { 0 }; const int plaintext_size = sizeof(plaintext); static const uint8_t nonce[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; const int nonce_size = sizeof(nonce); - uint8_t tag[16] = {0}; + uint8_t tag[16] = { 0 }; const int tag_size = sizeof(tag); uint8_t *out = tmp; @@ -525,7 +448,7 @@ static void test_aes_gcm_speed(void) CRYPTO_gcm128_init(&ctx, &aes_key, (block128_f)AES_encrypt, 0); CRYPTO_gcm128_setiv(&ctx, &aes_key, nonce, nonce_size); CRYPTO_gcm128_encrypt(&ctx, &aes_key, plaintext, out, - plaintext_size); + plaintext_size); CRYPTO_gcm128_tag(&ctx, tag, tag_size); } t1 = get_time(); -- cgit v1.2.1 From 699f1435e2cfb662ae6a0e4c1f81ef163dbd1d46 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:25 -0600 Subject: common/usb_i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia436012ee5c442105817990874af9316b305e67c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729769 Reviewed-by: Jeremy Bettis --- common/usb_i2c.c | 59 ++++++++++++++++++++++++-------------------------------- 1 file changed, 25 insertions(+), 34 deletions(-) diff --git a/common/usb_i2c.c b/common/usb_i2c.c index ace2e7139c..8bb8a227bd 100644 --- a/common/usb_i2c.c +++ b/common/usb_i2c.c @@ -20,27 +20,24 @@ #include "usb-stream.h" #include "usb_i2c.h" +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +USB_I2C_CONFIG(i2c, USB_IFACE_I2C, USB_STR_I2C_NAME, USB_EP_I2C) - -USB_I2C_CONFIG(i2c, - USB_IFACE_I2C, - USB_STR_I2C_NAME, - USB_EP_I2C) - -static int (*cros_cmd_handler)(void *data_in, - size_t in_size, - void *data_out, +static int (*cros_cmd_handler)(void *data_in, size_t in_size, void *data_out, size_t out_size); static int16_t usb_i2c_map_error(int error) { switch (error) { - case EC_SUCCESS: return USB_I2C_SUCCESS; - case EC_ERROR_TIMEOUT: return USB_I2C_TIMEOUT; - case EC_ERROR_BUSY: return USB_I2C_BUSY; - default: return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff); + case EC_SUCCESS: + return USB_I2C_SUCCESS; + case EC_ERROR_TIMEOUT: + return USB_I2C_TIMEOUT; + case EC_ERROR_BUSY: + return USB_I2C_BUSY; + default: + return USB_I2C_UNKNOWN_ERROR | (error & 0x7fff); } } @@ -52,7 +49,7 @@ static int16_t usb_i2c_map_error(int error) static uint32_t usb_i2c_read_packet(struct usb_i2c_config const *config) { return QUEUE_REMOVE_UNITS(config->consumer.queue, config->buffer, - queue_count(config->consumer.queue)); + queue_count(config->consumer.queue)); } static void usb_i2c_write_packet(struct usb_i2c_config const *config, @@ -72,9 +69,8 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config) * In order to support larger write payload, we need to peek * the queue to see if we need to wait for more data. */ - if (queue_peek_units(config->consumer.queue, - peek, 0, sizeof(peek)) - != sizeof(peek)) { + if (queue_peek_units(config->consumer.queue, peek, 0, + sizeof(peek)) != sizeof(peek)) { /* Not enough data to calculate expected_size. */ return 0; } @@ -92,7 +88,6 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config) expected_size += (((size_t)peek[0] & 0xf0) << 4) | peek[2]; } - if (queue_count(config->consumer.queue) >= expected_size) { expected_size = 0; return 1; @@ -104,20 +99,20 @@ static uint8_t usb_i2c_executable(struct usb_i2c_config const *config) static void usb_i2c_execute(struct usb_i2c_config const *config) { /* Payload is ready to execute. */ - uint32_t count = usb_i2c_read_packet(config); - int portindex = (config->buffer[0] >> 0) & 0xf; + uint32_t count = usb_i2c_read_packet(config); + int portindex = (config->buffer[0] >> 0) & 0xf; uint16_t addr_flags = (config->buffer[0] >> 8) & 0x7f; - int write_count = ((config->buffer[0] << 4) & 0xf00) | - ((config->buffer[1] >> 0) & 0xff); - int read_count = (config->buffer[1] >> 8) & 0xff; - int offset = 0; /* Offset for extended reading header. */ + int write_count = ((config->buffer[0] << 4) & 0xf00) | + ((config->buffer[1] >> 0) & 0xff); + int read_count = (config->buffer[1] >> 8) & 0xff; + int offset = 0; /* Offset for extended reading header. */ config->buffer[0] = 0; config->buffer[1] = 0; if (read_count & 0x80) { read_count = ((config->buffer[2] & 0xff) << 7) | - (read_count & 0x7f); + (read_count & 0x7f); offset = 2; } @@ -127,7 +122,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config) if (!usb_i2c_board_is_enabled()) { config->buffer[0] = USB_I2C_DISABLED; } else if (write_count > CONFIG_USB_I2C_MAX_WRITE_COUNT || - write_count != (count - 4 - offset)) { + write_count != (count - 4 - offset)) { config->buffer[0] = USB_I2C_WRITE_COUNT_INVALID; } else if (read_count > CONFIG_USB_I2C_MAX_READ_COUNT) { config->buffer[0] = USB_I2C_READ_COUNT_INVALID; @@ -156,8 +151,7 @@ static void usb_i2c_execute(struct usb_i2c_config const *config) */ ret = i2c_xfer(i2c_ports[portindex].port, addr_flags, (uint8_t *)(config->buffer + 2) + offset, - write_count, - (uint8_t *)(config->buffer + 2), + write_count, (uint8_t *)(config->buffer + 2), read_count); config->buffer[0] = usb_i2c_map_error(ret); } @@ -183,11 +177,8 @@ struct consumer_ops const usb_i2c_consumer_ops = { .written = usb_i2c_written, }; -int usb_i2c_register_cros_cmd_handler(int (*cmd_handler) - (void *data_in, - size_t in_size, - void *data_out, - size_t out_size)) +int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)( + void *data_in, size_t in_size, void *data_out, size_t out_size)) { if (cros_cmd_handler) return -1; -- cgit v1.2.1 From 70dc2299949b9f89b4adfd170e98359bccaf1bf9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:56 -0600 Subject: chip/stm32/flash-stm32g4-l4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1165c201ac2eeed7d423546d34df058961b7432b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729499 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32g4-l4.c | 95 ++++++++++++++++++++----------------------- 1 file changed, 45 insertions(+), 50 deletions(-) diff --git a/chip/stm32/flash-stm32g4-l4.c b/chip/stm32/flash-stm32g4-l4.c index f792da6e3c..5510a7875d 100644 --- a/chip/stm32/flash-stm32g4-l4.c +++ b/chip/stm32/flash-stm32g4-l4.c @@ -37,31 +37,31 @@ #define FLASH_PAGE_SIZE CONFIG_FLASH_BANK_SIZE #define FLASH_PAGE_MAX_COUNT (CONFIG_FLASH_SIZE_BYTES / FLASH_PAGE_SIZE) #define FLASH_RO_FIRST_PAGE_IDX WP_BANK_OFFSET -#define FLASH_RO_LAST_PAGE_IDX ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) \ - + FLASH_RO_FIRST_PAGE_IDX - 1) +#define FLASH_RO_LAST_PAGE_IDX \ + ((CONFIG_WP_STORAGE_SIZE / FLASH_PAGE_SIZE) + \ + FLASH_RO_FIRST_PAGE_IDX - 1) #define FLASH_RW_FIRST_PAGE_IDX (FLASH_RO_LAST_PAGE_IDX + 1) #define FLASH_RW_LAST_PAGE_IDX (FLASH_PAGE_MAX_COUNT - 1) - #define FLASH_PAGE_ROLLBACK_COUNT ROLLBACK_BANK_COUNT #define FLASH_PAGE_ROLLBACK_FIRST_IDX ROLLBACK_BANK_OFFSET -#define FLASH_PAGE_ROLLBACK_LAST_IDX (FLASH_PAGE_ROLLBACK_FIRST_IDX +\ - FLASH_PAGE_ROLLBACK_COUNT -1) +#define FLASH_PAGE_ROLLBACK_LAST_IDX \ + (FLASH_PAGE_ROLLBACK_FIRST_IDX + FLASH_PAGE_ROLLBACK_COUNT - 1) #ifdef STM32_FLASH_DBANK_MODE -#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1) +#define FLASH_WRP_MASK (FLASH_PAGE_MAX_COUNT - 1) #else #ifdef CHIP_FAMILY_STM32L4 -#define FLASH_WRP_MASK 0xFF +#define FLASH_WRP_MASK 0xFF #else -#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1) +#define FLASH_WRP_MASK ((FLASH_PAGE_MAX_COUNT) / 2 - 1) #endif #endif /* CONFIG_FLASH_DBANK_MODE */ -#define FLASH_WRP_START(val) ((val) & FLASH_WRP_MASK) -#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK) -#define FLASH_WRP_RANGE(start, end) (((start) & FLASH_WRP_MASK) | \ - (((end) & FLASH_WRP_MASK) << 16)) -#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00) +#define FLASH_WRP_START(val) ((val)&FLASH_WRP_MASK) +#define FLASH_WRP_END(val) (((val) >> 16) & FLASH_WRP_MASK) +#define FLASH_WRP_RANGE(start, end) \ + (((start)&FLASH_WRP_MASK) | (((end)&FLASH_WRP_MASK) << 16)) +#define FLASH_WRP_RANGE_DISABLED FLASH_WRP_RANGE(FLASH_WRP_MASK, 0x00) #define FLASH_WRP1X_MASK FLASH_WRP_RANGE(FLASH_WRP_MASK, FLASH_WRP_MASK) enum wrp_region { @@ -77,8 +77,8 @@ struct wrp_info { static inline int calculate_flash_timeout(void) { - return (FLASH_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int wait_while_busy(void) @@ -104,8 +104,7 @@ static int unlock(int locks) STM32_FLASH_KEYR = FLASH_KEYR_KEY2; } /* unlock option memory if required */ - if ((locks & FLASH_CR_OPTLOCK) && - (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { + if ((locks & FLASH_CR_OPTLOCK) && (STM32_FLASH_CR & FLASH_CR_OPTLOCK)) { STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; } @@ -113,8 +112,8 @@ static int unlock(int locks) /* Re-enable bus fault handler */ ignore_bus_fault(0); - return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN - : EC_SUCCESS; + return (STM32_FLASH_CR & (locks | FLASH_CR_LOCK)) ? EC_ERROR_UNKNOWN : + EC_SUCCESS; } static void lock(void) @@ -299,10 +298,10 @@ static void optb_set_wrp(enum wrp_region region, struct wrp_info *wrp) * value. Otherwise, can use end passed in directly. */ if (start <= FLASH_WRP_MASK) { - rw_end = end > FLASH_WRP_MASK ? - FLASH_WRP_MASK : end; - STM32_FLASH_WRP1BR = FLASH_WRP_RANGE(start, - rw_end); + rw_end = end > FLASH_WRP_MASK ? FLASH_WRP_MASK : + end; + STM32_FLASH_WRP1BR = + FLASH_WRP_RANGE(start, rw_end); } /* * If the last RW flash page is in the 2nd half of @@ -366,8 +365,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) * write protection in the option bytes. Based on new_flags either RO or * RW or both regions write protect may be set. */ - if (new_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_RO_AT_BOOT)) { + if (new_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_RO_AT_BOOT)) { wrp_ro.start = FLASH_RO_FIRST_PAGE_IDX; wrp_ro.end = FLASH_RO_LAST_PAGE_IDX; wrp_ro.enable = 1; @@ -434,9 +433,9 @@ static int registers_need_reset(void) /* The RO region is write-protected by the WRP1AR range. */ uint32_t wrp1ar = STM32_OPTB_WRP1AR; uint32_t ro_range = ro_at_boot ? - FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX, - FLASH_RO_LAST_PAGE_IDX) - : FLASH_WRP_RANGE_DISABLED; + FLASH_WRP_RANGE(FLASH_RO_FIRST_PAGE_IDX, + FLASH_RO_LAST_PAGE_IDX) : + FLASH_WRP_RANGE_DISABLED; return ro_range != (wrp1ar & FLASH_WRP1X_MASK); } @@ -484,10 +483,10 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* write the 2 words */ if (unaligned) { - *address++ = (uint32_t)data[0] | (data[1] << 8) - | (data[2] << 16) | (data[3] << 24); - *address++ = (uint32_t)data[4] | (data[5] << 8) - | (data[6] << 16) | (data[7] << 24); + *address++ = (uint32_t)data[0] | (data[1] << 8) | + (data[2] << 16) | (data[3] << 24); + *address++ = (uint32_t)data[4] | (data[5] << 8) | + (data[6] << 16) | (data[7] << 24); data += STM32_FLASH_MIN_WRITE_SIZE; } else { *address++ = *data32++; @@ -540,8 +539,8 @@ int crec_flash_physical_erase(int offset, int size) timestamp_t deadline; /* select page to erase and PER bit */ - STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) - | FLASH_CR_PER | FLASH_CR_PNB(pg); + STM32_FLASH_CR = (STM32_FLASH_CR & ~FLASH_CR_PNB_MASK) | + FLASH_CR_PER | FLASH_CR_PNB(pg); /* set STRT bit : start erase */ STM32_FLASH_CR |= FLASH_CR_STRT; @@ -591,7 +590,7 @@ int crec_flash_physical_get_protect(int block) optb_get_wrp(WRP_RW, &wrp_rw); return ((block >= wrp_ro.start) && (block <= wrp_ro.end)) || - ((block >= wrp_rw.start) && (block <= wrp_rw.end)); + ((block >= wrp_rw.start) && (block <= wrp_rw.end)); } /* @@ -613,7 +612,6 @@ uint32_t crec_flash_physical_get_protect_flags(void) flags |= EC_FLASH_PROTECT_RO_AT_BOOT; if (wrp_rw.enable) { - #ifdef CONFIG_ROLLBACK if (wrp_rw.start <= FLASH_PAGE_ROLLBACK_FIRST_IDX && wrp_rw.end >= FLASH_PAGE_ROLLBACK_LAST_IDX) @@ -639,18 +637,15 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | #ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | + EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW | #endif #ifdef CONFIG_ROLLBACK EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | EC_FLASH_PROTECT_ROLLBACK_NOW | #endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; + EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -665,13 +660,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * ALL/RW at-boot state can be set if WP GPIO is asserted and can always * be cleared. */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; #ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_RW_AT_BOOT; #endif @@ -735,8 +730,8 @@ int crec_flash_pre_init(void) * to the check above. One of them should be able to * go away. */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); + crec_flash_protect_at_boot(prot_flags & + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else { @@ -751,7 +746,7 @@ int crec_flash_pre_init(void) } if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && + EC_FLASH_PROTECT_ALL_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { /* @@ -767,7 +762,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_FLASH_PROTECT_RW if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && + EC_FLASH_PROTECT_RW_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { /* RW_AT_BOOT and RW_NOW do not match. */ -- cgit v1.2.1 From 44a2e9e0ed59932b87e96cb351be6afa10451998 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:45 -0600 Subject: baseboard/zork/variant_dalboz.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23a460ae17e89dc17c853fad4830990fc6de741f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727960 Reviewed-by: Jeremy Bettis --- baseboard/zork/variant_dalboz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/zork/variant_dalboz.c b/baseboard/zork/variant_dalboz.c index 10058bb8bc..c45bac0777 100644 --- a/baseboard/zork/variant_dalboz.c +++ b/baseboard/zork/variant_dalboz.c @@ -58,7 +58,7 @@ int board_get_temp(int idx, int *temp_k) /* adc power not ready when transition to S5 */ if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_SOFT_OFF)) + CHIPSET_STATE_SOFT_OFF)) return EC_ERROR_NOT_POWERED; channel = ADC_TEMP_SENSOR_SOC; -- cgit v1.2.1 From 7fb6114e47c3e666dc294f41f43a75c2db681ec5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:33 -0600 Subject: board/morphius/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac7a32ab90783da1e01dc419287e0d5177badbe4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728702 Reviewed-by: Jeremy Bettis --- board/morphius/led.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/board/morphius/led.c b/board/morphius/led.c index 5e72653fe3..1d5be7fe6e 100644 --- a/board/morphius/led.c +++ b/board/morphius/led.c @@ -17,8 +17,8 @@ #include "timer.h" #include "util.h" -#define LED_BAT_OFF_LVL 0 -#define LED_BAT_ON_LVL 1 +#define LED_BAT_OFF_LVL 0 +#define LED_BAT_ON_LVL 1 #define LED_BAT_S3_OFF_TIME_MS 3000 #define LED_BAT_S3_PWM_RESCALE 5 #define LED_BAT_S3_TICK_MS 50 @@ -34,10 +34,8 @@ static int ticks; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -45,13 +43,13 @@ enum led_color { LED_OFF = 0, LED_WHITE, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; /* PWM brightness vs. color, in the order of off, white */ static const uint8_t color_brightness[2] = { - [LED_OFF] = 0, - [LED_WHITE] = 100, + [LED_OFF] = 0, + [LED_WHITE] = 100, }; void led_set_color_power(enum led_color color) @@ -111,10 +109,10 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) } else if (led_id == EC_LED_ID_POWER_LED) { if (brightness[EC_LED_COLOR_WHITE] != 0) pwm_set_duty(PWM_CH_POWER_LED, - color_brightness[LED_WHITE]); + color_brightness[LED_WHITE]); else pwm_set_duty(PWM_CH_POWER_LED, - color_brightness[LED_OFF]); + color_brightness[LED_OFF]); } return EC_SUCCESS; @@ -133,8 +131,8 @@ static void suspend_led_update_deferred(void) if (ticks <= TICKS_STEP2_DIMMER) { pwm_set_duty(PWM_CH_POWER_LED, ticks * LED_BAT_S3_PWM_RESCALE); } else if (ticks <= TICKS_STEP3_OFF) { - pwm_set_duty(PWM_CH_POWER_LED, - (TICKS_STEP3_OFF - ticks) * LED_BAT_S3_PWM_RESCALE); + pwm_set_duty(PWM_CH_POWER_LED, (TICKS_STEP3_OFF - ticks) * + LED_BAT_S3_PWM_RESCALE); } else { ticks = TICKS_STEP1_BRIGHTER; delay = LED_BAT_S3_OFF_TIME_MS * MSEC; @@ -204,9 +202,10 @@ static void led_set_power(void) power_ticks = 0; while (blink_ticks < LED_PWR_TICKS_PER_CYCLE) { - led_set_color_power( - (power_ticks % LED_TOTAL_TICKS) < LED_ON_TICKS ? - LED_WHITE : LED_OFF); + led_set_color_power((power_ticks % LED_TOTAL_TICKS) < + LED_ON_TICKS ? + LED_WHITE : + LED_OFF); previous_state_suspend = 1; return; -- cgit v1.2.1 From 1501f6c849b15ef9bbe1867a3f3dc153a5bac959 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:47 -0600 Subject: zephyr/projects/nissa/src/craask/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic28e1664eb3e1884d28434db9ed99cb73e07b34a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730784 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/craask/led.c | 37 +++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/zephyr/projects/nissa/src/craask/led.c b/zephyr/projects/nissa/src/craask/led.c index a0c0447419..fbe5c88218 100644 --- a/zephyr/projects/nissa/src/craask/led.c +++ b/zephyr/projects/nissa/src/craask/led.c @@ -13,20 +13,29 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From 7a05f9f84eabe4d2a062e18d507c7a67937ca890 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:23 -0600 Subject: include/fpsensor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f61e8570805a62a965501cb7d65529c3a6e8937 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730289 Reviewed-by: Jeremy Bettis --- include/fpsensor.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/fpsensor.h b/include/fpsensor.h index 8efc4a7006..a8742b1f7f 100644 --- a/include/fpsensor.h +++ b/include/fpsensor.h @@ -17,8 +17,9 @@ #endif /* Four-character-code */ -#define FOURCC(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ - ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) +#define FOURCC(a, b, c, d) \ + ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | \ + ((uint32_t)(d) << 24)) /* 8-bit greyscale pixel format as defined by V4L2 headers */ #define V4L2_PIX_FMT_GREY FOURCC('G', 'R', 'E', 'Y') -- cgit v1.2.1 From 2ba119498f8000e10bfd6f3d2d763dfe03a0f931 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:50 -0600 Subject: common/mock/dp_alt_mode_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa51d4f6f210e641e455e9847270a16c164c2c7b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729688 Reviewed-by: Jeremy Bettis --- common/mock/dp_alt_mode_mock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/mock/dp_alt_mode_mock.c b/common/mock/dp_alt_mode_mock.c index 29f76bdb7a..e16de74675 100644 --- a/common/mock/dp_alt_mode_mock.c +++ b/common/mock/dp_alt_mode_mock.c @@ -18,8 +18,8 @@ #endif #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) -- cgit v1.2.1 From 763b2f3c7bc328a8d3cbc1d548cbf754d2a8a182 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:25 -0600 Subject: core/host/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9de1b8a9a84b4934bb25da92b57b422583bee9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729837 Reviewed-by: Jeremy Bettis --- core/host/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/core/host/cpu.h b/core/host/cpu.h index d990e06afa..95166aecb3 100644 --- a/core/host/cpu.h +++ b/core/host/cpu.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_CPU_H #define __CROS_EC_CPU_H -static inline void cpu_init(void) { } +static inline void cpu_init(void) +{ +} #endif /* __CROS_EC_CPU_H */ -- cgit v1.2.1 From a1a0b3080112f6bd24464b12c5da0bb7d037243f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:30 -0600 Subject: baseboard/herobrine/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e4650402acc70df2fd291dcb78bddae55f5c731 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727525 Reviewed-by: Jeremy Bettis --- baseboard/herobrine/baseboard.h | 88 ++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 45 deletions(-) diff --git a/baseboard/herobrine/baseboard.h b/baseboard/herobrine/baseboard.h index ae5b2a3d33..065437dd52 100644 --- a/baseboard/herobrine/baseboard.h +++ b/baseboard/herobrine/baseboard.h @@ -13,12 +13,12 @@ * The sensor stack is generating a lot of activity. * They can be enabled through the console command 'chan'. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Internal SPI flash on NPCX7 */ #define CONFIG_SPI_FLASH_REGS @@ -140,13 +140,13 @@ #define CONFIG_CMD_ACCEL_INFO /* PD */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ -#define PD_OPERATING_POWER_MW 10000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 10000 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Chipset */ #define CONFIG_CHIPSET_SC7280 @@ -163,56 +163,54 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_LID_OPEN GPIO_LID_OPEN_EC -#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L -#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 -#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 -#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_LID_OPEN GPIO_LID_OPEN_EC +#define GPIO_SHI_CS_L GPIO_AP_EC_SPI_CS_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_BATT_PRES_ODL GPIO_EC_BATT_PRES_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_BL_DISABLE_L +#define GPIO_BOARD_VERSION1 GPIO_BRD_ID0 +#define GPIO_BOARD_VERSION2 GPIO_BRD_ID1 +#define GPIO_BOARD_VERSION3 GPIO_BRD_ID2 +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* I2C Ports */ #define I2C_PORT_BATTERY I2C_PORT_POWER #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_WLC NPCX_I2C_PORT3_0 -#define I2C_PORT_RTC NPCX_I2C_PORT4_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_WLC NPCX_I2C_PORT3_0 +#define I2C_PORT_RTC NPCX_I2C_PORT4_1 +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 /* UART */ #define CONFIG_CMD_CHARGEN /* Define the host events which are allowed to wake AP up from S3 */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_DEVICE)) /* And the MKBP events */ #ifdef HAS_TASK_KEYSCAN -#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) +#define CONFIG_MKBP_EVENT_WAKEUP_MASK \ + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT) | \ + BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #else #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_HOST_EVENT) | \ - BIT(EC_MKBP_EVENT_SENSOR_FIFO)) + (BIT(EC_MKBP_EVENT_HOST_EVENT) | BIT(EC_MKBP_EVENT_SENSOR_FIFO)) #endif #endif /* __CROS_EC_BASEBOARD_H */ -- cgit v1.2.1 From 4b726816f8c90d4a2d5312e63e41d857fee28e36 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:07 -0600 Subject: include/switch.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4390027a7b9b3f2c7134acf1d0b85d31c53347d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730412 Reviewed-by: Jeremy Bettis --- include/switch.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/switch.h b/include/switch.h index e026408af9..243c1b9a57 100644 --- a/include/switch.h +++ b/include/switch.h @@ -19,7 +19,9 @@ */ void switch_interrupt(enum gpio_signal signal); #else -static inline void switch_interrupt(enum gpio_signal signal) { } -#endif /* !CONFIG_SWITCH */ +static inline void switch_interrupt(enum gpio_signal signal) +{ +} +#endif /* !CONFIG_SWITCH */ -#endif /* __CROS_EC_SWITCH_H */ +#endif /* __CROS_EC_SWITCH_H */ -- cgit v1.2.1 From a8f99edf161a8cac86af77cf08063e6a06e3e884 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:46 -0600 Subject: extra/usb_serial/raiden.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icb5b66f4000902a76ebd4209af3008b2c83ca53f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730189 Reviewed-by: Jeremy Bettis --- extra/usb_serial/raiden.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/extra/usb_serial/raiden.c b/extra/usb_serial/raiden.c index e4720b4357..5461f00bb5 100644 --- a/extra/usb_serial/raiden.c +++ b/extra/usb_serial/raiden.c @@ -19,28 +19,25 @@ MODULE_LICENSE("GPL"); -#define USB_VENDOR_ID_GOOGLE 0x18d1 -#define USB_SUBCLASS_GOOGLE_SERIAL 0x50 -#define USB_PROTOCOL_GOOGLE_SERIAL 0x01 +#define USB_VENDOR_ID_GOOGLE 0x18d1 +#define USB_SUBCLASS_GOOGLE_SERIAL 0x50 +#define USB_PROTOCOL_GOOGLE_SERIAL 0x01 static struct usb_device_id const ids[] = { - { USB_VENDOR_AND_INTERFACE_INFO(USB_VENDOR_ID_GOOGLE, - USB_CLASS_VENDOR_SPEC, - USB_SUBCLASS_GOOGLE_SERIAL, - USB_PROTOCOL_GOOGLE_SERIAL) }, - { 0 } + { USB_VENDOR_AND_INTERFACE_INFO( + USB_VENDOR_ID_GOOGLE, USB_CLASS_VENDOR_SPEC, + USB_SUBCLASS_GOOGLE_SERIAL, USB_PROTOCOL_GOOGLE_SERIAL) }, + { 0 } }; MODULE_DEVICE_TABLE(usb, ids); -static struct usb_serial_driver device = -{ - .driver = { .owner = THIS_MODULE, - .name = "Google" }, - .id_table = ids, +static struct usb_serial_driver device = { + .driver = { .owner = THIS_MODULE, .name = "Google" }, + .id_table = ids, .num_ports = 1, }; -static struct usb_serial_driver * const drivers[] = { &device, NULL }; +static struct usb_serial_driver *const drivers[] = { &device, NULL }; module_usb_serial_driver(drivers, ids); -- cgit v1.2.1 From 285bb4deedb631648796217a98c8bee058f4674a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:35 -0600 Subject: chip/ish/hid_device.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0e240ab4faae2c3660a437dc618985c91701bdb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729158 Reviewed-by: Jeremy Bettis --- chip/ish/hid_device.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/chip/ish/hid_device.h b/chip/ish/hid_device.h index 0a32e305af..76cd028eef 100644 --- a/chip/ish/hid_device.h +++ b/chip/ish/hid_device.h @@ -11,15 +11,15 @@ #include "hooks.h" -#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954 +#define HID_SUBSYS_MAX_PAYLOAD_SIZE 4954 enum HID_SUBSYS_ERR { - HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1, + HID_SUBSYS_ERR_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, + HID_SUBSYS_ERR_TOO_MANY_HID_DEVICES = EC_ERROR_INTERNAL_FIRST + 1, }; -typedef void * hid_handle_t; -#define HID_INVALID_HANDLE NULL +typedef void *hid_handle_t; +#define HID_INVALID_HANDLE NULL struct hid_callbacks { /* @@ -73,11 +73,11 @@ int hid_subsys_set_device_data(const hid_handle_t handle, void *data); /* retrieve HID device specific data */ void *hid_subsys_get_device_data(const hid_handle_t handle); -#define HID_DEVICE_ENTRY(hid_dev) \ - void _hid_dev_entry_##hid_dev(void) \ - { \ +#define HID_DEVICE_ENTRY(hid_dev) \ + void _hid_dev_entry_##hid_dev(void) \ + { \ hid_subsys_register_device(&(hid_dev)); \ - } \ + } \ DECLARE_HOOK(HOOK_INIT, _hid_dev_entry_##hid_dev, HOOK_PRIO_LAST - 2) #endif /* __HID_DEVICE_H */ -- cgit v1.2.1 From 8b2f91a11d74e51384b29258f5c6e8889528a222 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:38 -0600 Subject: driver/als_tcs3400.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I574d6bbc4d010b9891c5ca38c81c60f13b2ac870 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729905 Reviewed-by: Jeremy Bettis --- driver/als_tcs3400.c | 234 +++++++++++++++++++++++++-------------------------- 1 file changed, 113 insertions(+), 121 deletions(-) diff --git a/driver/als_tcs3400.c b/driver/als_tcs3400.c index 4e1fdb9d4f..363148dba8 100644 --- a/driver/als_tcs3400.c +++ b/driver/als_tcs3400.c @@ -20,7 +20,7 @@ #define ALS_TCS3400_INT_ENABLE #endif -#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s "fmt, __func__, ## args) +#define CPRINTS(fmt, args...) cprints(CC_ACCEL, "%s " fmt, __func__, ##args) volatile uint32_t last_interrupt_timestamp; @@ -32,32 +32,34 @@ volatile uint32_t last_interrupt_timestamp; * Values in array are TCS_ATIME_GAIN_FACTOR (100x) times actual value to allow * for fractions using integers. */ -static const uint16_t -range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN + 1][TCS_MAX_ATIME_RANGES] = { -{11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575, 2275, 2075}, -{11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577, 525}, -{250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0}, -{790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; +static const uint16_t range_atime[TCS_MAX_AGAIN - TCS_MIN_AGAIN + + 1][TCS_MAX_ATIME_RANGES] = { + { 11200, 5600, 5600, 7200, 5500, 4500, 3800, 3800, 3300, 2900, 2575, + 2275, 2075 }, + { 11200, 5100, 2700, 1840, 1400, 1133, 981, 963, 833, 728, 650, 577, + 525 }, + { 250, 1225, 643, 441, 337, 276, 253, 235, 203, 176, 150, 0, 0 }, + { 790, 261, 163, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } +}; -static void -decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux, int percent) +static void decrement_atime(struct tcs_saturation_t *sat_p, uint16_t cur_lux, + int percent) { int atime; uint16_t steps; int lux = MIN(cur_lux, TCS_GAIN_TABLE_MAX_LUX); steps = percent * range_atime[sat_p->again][lux / 1000] / - TCS_ATIME_GAIN_FACTOR; + TCS_ATIME_GAIN_FACTOR; atime = MAX(sat_p->atime - steps, TCS_MIN_ATIME); sat_p->atime = MIN(atime, TCS_MAX_ATIME); } #else -static void -decrement_atime(struct tcs_saturation_t *sat_p, - uint16_t __attribute__((unused)) cur_lux, - int __attribute__((unused)) percent) +static void decrement_atime(struct tcs_saturation_t *sat_p, + uint16_t __attribute__((unused)) cur_lux, + int __attribute__((unused)) percent) { sat_p->atime = MAX(sat_p->atime - TCS_ATIME_DEC_STEP, TCS_MIN_ATIME); } @@ -69,14 +71,14 @@ static void increment_atime(struct tcs_saturation_t *sat_p) sat_p->atime = MIN(sat_p->atime + TCS_ATIME_INC_STEP, TCS_MAX_ATIME); } -static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s, - int reg, int *data) +static inline int tcs3400_i2c_read8(const struct motion_sensor_t *s, int reg, + int *data) { return i2c_read8(s->port, s->i2c_spi_addr_flags, reg, data); } -static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s, - int reg, int data) +static inline int tcs3400_i2c_write8(const struct motion_sensor_t *s, int reg, + int data) { return i2c_write8(s->port, s->i2c_spi_addr_flags, reg, data); } @@ -107,12 +109,12 @@ static int tcs3400_read(const struct motion_sensor_t *s, intv3_t v) int ret; /* Chip may have been off, make sure to setup important registers */ - if (TCS3400_RGB_DRV_DATA(s+1)->calibration_mode) { + if (TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode) { atime = TCS_CALIBRATION_ATIME; again = TCS_CALIBRATION_AGAIN; } else { - atime = TCS3400_RGB_DRV_DATA(s+1)->saturation.atime; - again = TCS3400_RGB_DRV_DATA(s+1)->saturation.again; + atime = TCS3400_RGB_DRV_DATA(s + 1)->saturation.atime; + again = TCS3400_RGB_DRV_DATA(s + 1)->saturation.again; } ret = tcs3400_i2c_write8(s, TCS_I2C_ATIME, atime); if (ret) @@ -159,17 +161,16 @@ static int tcs3400_rgb_read(const struct motion_sensor_t *s, intv3_t v) * AGAIN if it is not already at its maximum, or if it is, decrease * ATIME if it is not at it's minimum already. */ -static int -tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, - uint16_t cur_lux, - uint16_t *crgb_data, - uint32_t status) +static int tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, + uint16_t cur_lux, + uint16_t *crgb_data, + uint32_t status) { struct tcs_saturation_t *sat_p = - &TCS3400_RGB_DRV_DATA(s+1)->saturation; + &TCS3400_RGB_DRV_DATA(s + 1)->saturation; const uint8_t save_again = sat_p->again; const uint8_t save_atime = sat_p->atime; - uint16_t max_val = 0; + uint16_t max_val = 0; int ret; int percent_left = 0; @@ -182,7 +183,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, /* Don't process if status isn't valid yet */ if ((status & TCS_I2C_STATUS_ALS_SATURATED) || - (max_val >= TCS_SATURATION_LEVEL)) { + (max_val >= TCS_SATURATION_LEVEL)) { /* Saturation occurred, decrease AGAIN if we can */ if (sat_p->again > TCS_MIN_AGAIN) sat_p->again--; @@ -199,14 +200,15 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, * increase accumulation time by decrementing * ATIME register */ - percent_left = TSC_SATURATION_LOW_BAND_PERCENT - + percent_left = + TSC_SATURATION_LOW_BAND_PERCENT - (max_val * 100 / TCS_SATURATION_LEVEL); decrement_atime(sat_p, cur_lux, percent_left); } } else if (sat_p->atime > TCS_MIN_ATIME) { /* calculate percentage between current and desired */ percent_left = TSC_SATURATION_LOW_BAND_PERCENT - - (max_val * 100 / TCS_SATURATION_LEVEL); + (max_val * 100 / TCS_SATURATION_LEVEL); /* increase accumulation time by decrementing ATIME */ decrement_atime(sat_p, cur_lux, percent_left); @@ -233,7 +235,7 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, /* If atime or gain setting changed, update atime and gain registers */ if (save_again != sat_p->again) { ret = tcs3400_i2c_write8(s, TCS_I2C_CONTROL, - (sat_p->again & TCS_I2C_CONTROL_MASK)); + (sat_p->again & TCS_I2C_CONTROL_MASK)); if (ret) return ret; } @@ -252,24 +254,25 @@ tcs3400_adjust_sensor_for_saturation(struct motion_sensor_t *s, * different atime and again settings from the sample. */ static uint32_t normalize_channel_data(struct motion_sensor_t *s, - uint32_t sample) + uint32_t sample) { struct tcs_saturation_t *sat_p = - &(TCS3400_RGB_DRV_DATA(s+1)->saturation); + &(TCS3400_RGB_DRV_DATA(s + 1)->saturation); const uint16_t cur_gain = (1 << (2 * sat_p->again)); const uint16_t cal_again = (1 << (2 * TCS_CALIBRATION_AGAIN)); - return DIV_ROUND_NEAREST(sample * (TCS_ATIME_GRANULARITY - - TCS_CALIBRATION_ATIME) * cal_again, - (TCS_ATIME_GRANULARITY - sat_p->atime) * - cur_gain); + return DIV_ROUND_NEAREST( + sample * (TCS_ATIME_GRANULARITY - TCS_CALIBRATION_ATIME) * + cal_again, + (TCS_ATIME_GRANULARITY - sat_p->atime) * cur_gain); } - __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s, - int32_t *crgb_data, int32_t *xyz_data) + int32_t *crgb_data, + int32_t *xyz_data) { - struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1); + struct tcs3400_rgb_drv_data_t *rgb_drv_data = + TCS3400_RGB_DRV_DATA(s + 1); int32_t crgb_prime[CRGB_COUNT]; int32_t ir; int i; @@ -280,8 +283,9 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s, /* IR removal */ ir = FP_TO_INT(fp_mul(INT_TO_FP(crgb_data[1] + crgb_data[2] + - crgb_data[3] - crgb_data[0]), - rgb_drv_data->calibration.irt) / 2); + crgb_data[3] - crgb_data[0]), + rgb_drv_data->calibration.irt) / + 2); for (i = 0; i < ARRAY_SIZE(crgb_prime); i++) { if (crgb_data[i] < ir) @@ -297,17 +301,17 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s, /* regression fit to XYZ space */ for (i = 0; i < 3; i++) { const struct rgb_channel_calibration_t *p = - &rgb_drv_data->calibration.rgb_cal[i]; - - xyz_data[i] = p->offset + FP_TO_INT( - (fp_inter_t)p->coeff[RED_CRGB_IDX] * - crgb_prime[RED_CRGB_IDX] + - (fp_inter_t)p->coeff[GREEN_CRGB_IDX] * - crgb_prime[GREEN_CRGB_IDX] + - (fp_inter_t)p->coeff[BLUE_CRGB_IDX] * - crgb_prime[BLUE_CRGB_IDX] + - (fp_inter_t)p->coeff[CLEAR_CRGB_IDX] * - crgb_prime[CLEAR_CRGB_IDX]); + &rgb_drv_data->calibration.rgb_cal[i]; + + xyz_data[i] = p->offset + + FP_TO_INT((fp_inter_t)p->coeff[RED_CRGB_IDX] * + crgb_prime[RED_CRGB_IDX] + + (fp_inter_t)p->coeff[GREEN_CRGB_IDX] * + crgb_prime[GREEN_CRGB_IDX] + + (fp_inter_t)p->coeff[BLUE_CRGB_IDX] * + crgb_prime[BLUE_CRGB_IDX] + + (fp_inter_t)p->coeff[CLEAR_CRGB_IDX] * + crgb_prime[CLEAR_CRGB_IDX]); if (xyz_data[i] < 0) xyz_data[i] = 0; @@ -315,14 +319,16 @@ __overridable void tcs3400_translate_to_xyz(struct motion_sensor_t *s, } static void tcs3400_process_raw_data(struct motion_sensor_t *s, - uint8_t *raw_data_buf, - uint16_t *raw_light_data, int32_t *xyz_data) + uint8_t *raw_data_buf, + uint16_t *raw_light_data, + int32_t *xyz_data) { struct als_drv_data_t *als_drv_data = TCS3400_DRV_DATA(s); - struct tcs3400_rgb_drv_data_t *rgb_drv_data = TCS3400_RGB_DRV_DATA(s+1); + struct tcs3400_rgb_drv_data_t *rgb_drv_data = + TCS3400_RGB_DRV_DATA(s + 1); const uint8_t calibration_mode = rgb_drv_data->calibration_mode; - uint16_t k_channel_scale = - als_drv_data->als_cal.channel_scale.k_channel_scale; + uint16_t k_channel_scale = + als_drv_data->als_cal.channel_scale.k_channel_scale; uint16_t cover_scale = als_drv_data->als_cal.channel_scale.cover_scale; int32_t crgb_data[CRGB_COUNT]; int i; @@ -333,7 +339,7 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s, /* assemble the light value for this channel */ crgb_data[i] = raw_light_data[i] = - ((raw_data_buf[index+1] << 8) | raw_data_buf[index]); + ((raw_data_buf[index + 1] << 8) | raw_data_buf[index]); /* in calibration mode, we only assemble the raw data */ if (calibration_mode) @@ -342,14 +348,14 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s, /* rgb data at index 1, 2, and 3 owned by rgb driver, not ALS */ if (i > 0) { struct als_channel_scale_t *csp = - &rgb_drv_data->calibration.rgb_cal[i-1].scale; + &rgb_drv_data->calibration.rgb_cal[i - 1].scale; k_channel_scale = csp->k_channel_scale; cover_scale = csp->cover_scale; } /* Step 1: divide by individual channel scale value */ - crgb_data[i] = SENSOR_APPLY_DIV_SCALE(crgb_data[i], - k_channel_scale); + crgb_data[i] = + SENSOR_APPLY_DIV_SCALE(crgb_data[i], k_channel_scale); /* compensate for the light cover */ crgb_data[i] = SENSOR_APPLY_SCALE(crgb_data[i], cover_scale); @@ -365,7 +371,7 @@ static void tcs3400_process_raw_data(struct motion_sensor_t *s, /* calibration mode returns raw data */ for (i = 0; i < 3; i++) - xyz_data[i] = crgb_data[i+1]; + xyz_data[i] = crgb_data[i + 1]; } } @@ -373,7 +379,7 @@ static int32_t get_lux_from_xyz(struct motion_sensor_t *s, int32_t *xyz_data) { int32_t lux = xyz_data[Y]; const int32_t offset = - TCS3400_RGB_DRV_DATA(s+1)->calibration.rgb_cal[Y].offset; + TCS3400_RGB_DRV_DATA(s + 1)->calibration.rgb_cal[Y].offset; /* * Do not include the offset when determining LUX from XYZ. @@ -389,8 +395,7 @@ static bool is_spoof(struct motion_sensor_t *s) (s->flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE); } -static int tcs3400_post_events(struct motion_sensor_t *s, - uint32_t last_ts, +static int tcs3400_post_events(struct motion_sensor_t *s, uint32_t last_ts, uint32_t status) { /* @@ -399,7 +404,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s, */ struct motion_sensor_t *rgb_s = s + 1; const uint8_t is_calibration = - TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode; + TCS3400_RGB_DRV_DATA(rgb_s)->calibration_mode; uint8_t buf[TCS_RGBC_DATA_SIZE]; /* holds raw data read from chip */ int32_t xyz_data[3] = { 0, 0, 0 }; uint16_t raw_data[CRGB_COUNT]; /* holds raw CRGB assembled from buf[] */ @@ -408,7 +413,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s, int ret; if (IS_ENABLED(CONFIG_ALS_TCS3400_EMULATED_IRQ_EVENT)) { - int i = 5; /* 100ms max */ + int i = 5; /* 100ms max */ while (i--) { /* Make sure data is valid */ @@ -431,8 +436,7 @@ static int tcs3400_post_events(struct motion_sensor_t *s, /* Read the light registers */ ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, - TCS_DATA_START_LOCATION, - buf, sizeof(buf)); + TCS_DATA_START_LOCATION, buf, sizeof(buf)); if (ret) return ret; @@ -450,7 +454,8 @@ static int tcs3400_post_events(struct motion_sensor_t *s, if (is_spoof(s)) last_v[X] = s->spoof_xyz[X]; else - last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] : lux; + last_v[X] = is_calibration ? raw_data[CLEAR_CRGB_IDX] : + lux; if (IS_ENABLED(CONFIG_ACCEL_FIFO)) { struct ec_response_motion_sensor_data vector = { @@ -475,12 +480,13 @@ static int tcs3400_post_events(struct motion_sensor_t *s, last_v = rgb_s->raw_xyz; if (is_calibration || (((last_v[X] != xyz_data[X]) || (last_v[Y] != xyz_data[Y]) || - (last_v[Z] != xyz_data[Z])) && + (last_v[Z] != xyz_data[Z])) && ((raw_data[RED_CRGB_IDX] != TCS_SATURATION_LEVEL) && (raw_data[BLUE_CRGB_IDX] != TCS_SATURATION_LEVEL) && (raw_data[GREEN_CRGB_IDX] != TCS_SATURATION_LEVEL)))) { if (is_spoof(rgb_s)) { - memcpy(last_v, rgb_s->spoof_xyz, sizeof(rgb_s->spoof_xyz)); + memcpy(last_v, rgb_s->spoof_xyz, + sizeof(rgb_s->spoof_xyz)); } else if (is_calibration) { last_v[0] = raw_data[RED_CRGB_IDX]; last_v[1] = raw_data[GREEN_CRGB_IDX]; @@ -498,7 +504,8 @@ static int tcs3400_post_events(struct motion_sensor_t *s, ec_motion_sensor_clamp_u16s(udata, last_v); vector.sensor_num = rgb_s - motion_sensors; - motion_sense_fifo_stage_data(&vector, rgb_s, 3, last_ts); + motion_sense_fifo_stage_data(&vector, rgb_s, 3, + last_ts); } else { motion_sense_push_raw_xyz(rgb_s); } @@ -558,11 +565,10 @@ static int tcs3400_irq_handler(struct motion_sensor_t *s, uint32_t *event) } static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s, - uint16_t *scale, - int16_t *temp) + uint16_t *scale, int16_t *temp) { struct rgb_channel_calibration_t *rgb_cal = - TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal; + TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal; scale[X] = rgb_cal[RED_RGB_IDX].scale.k_channel_scale; scale[Y] = rgb_cal[GREEN_RGB_IDX].scale.k_channel_scale; @@ -572,11 +578,10 @@ static int tcs3400_rgb_get_scale(const struct motion_sensor_t *s, } static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s, - const uint16_t *scale, - int16_t temp) + const uint16_t *scale, int16_t temp) { struct rgb_channel_calibration_t *rgb_cal = - TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal; + TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal; if (scale[X] == 0 || scale[Y] == 0 || scale[Z] == 0) return EC_ERROR_INVAL; @@ -587,8 +592,7 @@ static int tcs3400_rgb_set_scale(const struct motion_sensor_t *s, } static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) + int16_t *offset, int16_t *temp) { offset[X] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[X].offset; offset[Y] = TCS3400_RGB_DRV_DATA(s)->calibration.rgb_cal[Y].offset; @@ -598,15 +602,13 @@ static int tcs3400_rgb_get_offset(const struct motion_sensor_t *s, } static int tcs3400_rgb_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) + const int16_t *offset, int16_t temp) { /* do not allow offset to be changed, it's predetermined */ return EC_SUCCESS; } -static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s, - int rate, +static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { return EC_SUCCESS; @@ -615,20 +617,16 @@ static int tcs3400_rgb_set_data_rate(const struct motion_sensor_t *s, /* Enable/disable special factory calibration mode */ static int tcs3400_perform_calib(struct motion_sensor_t *s, int enable) { - TCS3400_RGB_DRV_DATA(s+1)->calibration_mode = enable; + TCS3400_RGB_DRV_DATA(s + 1)->calibration_mode = enable; return EC_SUCCESS; } -static int tcs3400_rgb_set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int tcs3400_rgb_set_range(struct motion_sensor_t *s, int range, int rnd) { return EC_SUCCESS; } -static int tcs3400_set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int tcs3400_set_range(struct motion_sensor_t *s, int range, int rnd) { TCS3400_DRV_DATA(s)->als_cal.scale = range >> 16; TCS3400_DRV_DATA(s)->als_cal.uscale = range & 0xffff; @@ -636,9 +634,8 @@ static int tcs3400_set_range(struct motion_sensor_t *s, return EC_SUCCESS; } -static int tcs3400_get_scale(const struct motion_sensor_t *s, - uint16_t *scale, - int16_t *temp) +static int tcs3400_get_scale(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp) { scale[X] = TCS3400_DRV_DATA(s)->als_cal.channel_scale.k_channel_scale; scale[Y] = 0; @@ -648,8 +645,7 @@ static int tcs3400_get_scale(const struct motion_sensor_t *s, } static int tcs3400_set_scale(const struct motion_sensor_t *s, - const uint16_t *scale, - int16_t temp) + const uint16_t *scale, int16_t temp) { if (scale[X] == 0) return EC_ERROR_INVAL; @@ -657,8 +653,7 @@ static int tcs3400_set_scale(const struct motion_sensor_t *s, return EC_SUCCESS; } -static int tcs3400_get_offset(const struct motion_sensor_t *s, - int16_t *offset, +static int tcs3400_get_offset(const struct motion_sensor_t *s, int16_t *offset, int16_t *temp) { offset[X] = TCS3400_DRV_DATA(s)->als_cal.offset; @@ -669,8 +664,7 @@ static int tcs3400_get_offset(const struct motion_sensor_t *s, } static int tcs3400_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) + const int16_t *offset, int16_t temp) { /* do not allow offset to be changed, it's predetermined */ return EC_SUCCESS; @@ -686,8 +680,7 @@ static int tcs3400_rgb_get_data_rate(const struct motion_sensor_t *s) return tcs3400_get_data_rate(s - 1); } -static int tcs3400_set_data_rate(const struct motion_sensor_t *s, - int rate, +static int tcs3400_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { enum tcs3400_mode mode; @@ -737,22 +730,21 @@ static int tcs3400_init(struct motion_sensor_t *s) const struct reg_data { uint8_t reg; uint8_t data; - } defaults[] = { - { TCS_I2C_ENABLE, 0 }, - { TCS_I2C_ATIME, TCS_DEFAULT_ATIME }, - { TCS_I2C_WTIME, 0xFF }, - { TCS_I2C_AILTL, 0 }, - { TCS_I2C_AILTH, 0 }, - { TCS_I2C_AIHTL, 0 }, - { TCS_I2C_AIHTH, 0 }, - { TCS_I2C_PERS, 0 }, - { TCS_I2C_CONFIG, 0x40 }, - { TCS_I2C_CONTROL, (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) }, - { TCS_I2C_AUX, 0 }, - { TCS_I2C_IR, 0 }, - { TCS_I2C_CICLEAR, 0 }, - { TCS_I2C_AICLEAR, 0 } - }; + } defaults[] = { { TCS_I2C_ENABLE, 0 }, + { TCS_I2C_ATIME, TCS_DEFAULT_ATIME }, + { TCS_I2C_WTIME, 0xFF }, + { TCS_I2C_AILTL, 0 }, + { TCS_I2C_AILTH, 0 }, + { TCS_I2C_AIHTL, 0 }, + { TCS_I2C_AIHTH, 0 }, + { TCS_I2C_PERS, 0 }, + { TCS_I2C_CONFIG, 0x40 }, + { TCS_I2C_CONTROL, + (TCS_DEFAULT_AGAIN & TCS_I2C_CONTROL_MASK) }, + { TCS_I2C_AUX, 0 }, + { TCS_I2C_IR, 0 }, + { TCS_I2C_CICLEAR, 0 }, + { TCS_I2C_AICLEAR, 0 } }; int data = 0; int ret; -- cgit v1.2.1 From 87d1d22991b5652d79b83219800746757804d721 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:13 -0600 Subject: driver/temp_sensor/g753.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic56222d78765ab1afba94587a15767c09697e121 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730104 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/g753.h | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/driver/temp_sensor/g753.h b/driver/temp_sensor/g753.h index 04c412bfbb..41a4b817cf 100644 --- a/driver/temp_sensor/g753.h +++ b/driver/temp_sensor/g753.h @@ -8,36 +8,35 @@ #ifndef __CROS_EC_G753_H #define __CROS_EC_G753_H +#define G753_I2C_ADDR_FLAGS 0x48 -#define G753_I2C_ADDR_FLAGS 0x48 - -#define G753_IDX_INTERNAL 0 +#define G753_IDX_INTERNAL 0 /* G753 register */ -#define G753_TEMP_LOCAL 0x00 -#define G753_STATUS 0x02 -#define G753_CONFIGURATION_R 0x03 -#define G753_CONVERSION_RATE_R 0x04 -#define G753_LOCAL_TEMP_HIGH_LIMIT_R 0x05 -#define G753_CONFIGURATION_W 0x09 -#define G753_CONVERSION_RATE_W 0x0A -#define G753_LOCAL_TEMP_HIGH_LIMIT_W 0x0B -#define G753_ONESHOT 0x0F -#define G753_Customer_Data_Log_Register_1 0x2D -#define G753_Customer_Data_Log_Register_2 0x2E -#define G753_Customer_Data_Log_Register_3 0x2F -#define G753_ALERT_MODE 0xBF -#define G753_CHIP_ID 0xFD -#define G753_VENDOR_ID 0xFE -#define G753_DEVICE_ID 0xFF +#define G753_TEMP_LOCAL 0x00 +#define G753_STATUS 0x02 +#define G753_CONFIGURATION_R 0x03 +#define G753_CONVERSION_RATE_R 0x04 +#define G753_LOCAL_TEMP_HIGH_LIMIT_R 0x05 +#define G753_CONFIGURATION_W 0x09 +#define G753_CONVERSION_RATE_W 0x0A +#define G753_LOCAL_TEMP_HIGH_LIMIT_W 0x0B +#define G753_ONESHOT 0x0F +#define G753_Customer_Data_Log_Register_1 0x2D +#define G753_Customer_Data_Log_Register_2 0x2E +#define G753_Customer_Data_Log_Register_3 0x2F +#define G753_ALERT_MODE 0xBF +#define G753_CHIP_ID 0xFD +#define G753_VENDOR_ID 0xFE +#define G753_DEVICE_ID 0xFF /* Config register bits */ -#define G753_CONFIGURATION_STANDBY BIT(6) -#define G753_CONFIGURATION_ALERT_MASK BIT(7) +#define G753_CONFIGURATION_STANDBY BIT(6) +#define G753_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) -#define G753_STATUS_BUSY BIT(7) +#define G753_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define G753_STATUS_BUSY BIT(7) /** * Get the last polled value of a sensor. @@ -50,4 +49,4 @@ */ int g753_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_G753_H */ +#endif /* __CROS_EC_G753_H */ -- cgit v1.2.1 From 3826ed4d071e8d8a7e8f44964954ff4f689731f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:24 -0600 Subject: zephyr/emul/emul_smart_battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c920218bc2f87236d7462a9d217d0eb8c7c0bfd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730696 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_smart_battery.c | 48 ++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c index a6abd94054..1300e7da0a 100644 --- a/zephyr/emul/emul_smart_battery.c +++ b/zephyr/emul/emul_smart_battery.c @@ -20,7 +20,7 @@ LOG_MODULE_REGISTER(smart_battery); #include "crc8.h" #include "battery_smart.h" -#define SBAT_DATA_FROM_I2C_EMUL(_emul) \ +#define SBAT_DATA_FROM_I2C_EMUL(_emul) \ CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ struct sbat_emul_data, common) @@ -53,13 +53,13 @@ struct sbat_emul_bat_data *sbat_emul_get_bat_data(struct i2c_emul *emul) uint16_t sbat_emul_date_to_word(unsigned int day, unsigned int month, unsigned int year) { - year -= MANUFACTURE_DATE_YEAR_OFFSET; - year <<= MANUFACTURE_DATE_YEAR_SHIFT; - year &= MANUFACTURE_DATE_YEAR_MASK; + year -= MANUFACTURE_DATE_YEAR_OFFSET; + year <<= MANUFACTURE_DATE_YEAR_SHIFT; + year &= MANUFACTURE_DATE_YEAR_MASK; month <<= MANUFACTURE_DATE_MONTH_SHIFT; - month &= MANUFACTURE_DATE_MONTH_MASK; - day <<= MANUFACTURE_DATE_DAY_SHIFT; - day &= MANUFACTURE_DATE_DAY_MASK; + month &= MANUFACTURE_DATE_MONTH_MASK; + day <<= MANUFACTURE_DATE_DAY_SHIFT; + day &= MANUFACTURE_DATE_DAY_MASK; return day | month | year; } @@ -105,7 +105,7 @@ static uint16_t sbat_emul_10mw_to_ma(int mw, int mv) /* Smart battery use 10mW units, convert to mW */ mw *= 10; /* Multiple by 1000 to get mA instead of A */ - return 1000 * mw/mv; + return 1000 * mw / mv; } /** @@ -659,8 +659,8 @@ static int sbat_emul_finalize_write_msg(struct i2c_emul *emul, int reg, pec = cros_crc8_arg(data->msg_buf, 3, pec); if (pec != data->msg_buf[3]) { data->bat.error_code = STATUS_CODE_UNKNOWN_ERROR; - LOG_ERR("Wrong PEC 0x%x != 0x%x", - pec, data->msg_buf[3]); + LOG_ERR("Wrong PEC 0x%x != 0x%x", pec, + data->msg_buf[3]); return -EIO; } @@ -785,8 +785,7 @@ static int sbat_emul_access_reg(struct i2c_emul *emul, int reg, int bytes, * * @return 0 indicating success (always) */ -static int sbat_emul_init(const struct emul *emul, - const struct device *parent) +static int sbat_emul_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = cfg->data; @@ -803,7 +802,7 @@ static int sbat_emul_init(const struct emul *emul, return ret; } -#define SMART_BATTERY_EMUL(n) \ +#define SMART_BATTERY_EMUL(n) \ static struct sbat_emul_data sbat_emul_data_##n = { \ .bat = { \ .mf_access = DT_INST_PROP(n, mf_access), \ @@ -869,27 +868,28 @@ static int sbat_emul_init(const struct emul *emul, .finish_read = NULL, \ .access_reg = sbat_emul_access_reg, \ }, \ - }; \ - \ - static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + }; \ + \ + static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ - .data = &sbat_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(sbat_emul_init, DT_DRV_INST(n), &sbat_emul_cfg_##n, \ + .data = &sbat_emul_data_##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(sbat_emul_init, DT_DRV_INST(n), &sbat_emul_cfg_##n, \ &sbat_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL) -#define SMART_BATTERY_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &sbat_emul_data_##n.common.emul; +#define SMART_BATTERY_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &sbat_emul_data_##n.common.emul; /** Check description in emul_smart_battery.h */ struct i2c_emul *sbat_emul_get_ptr(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(SMART_BATTERY_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From 0f067afb0d16361449392bf122c86ad29c1ea87b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:44 -0600 Subject: include/mock/mkbp_events_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I652ad9c2d7309cbe8138b4774a029ffaec7dbef0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730359 Reviewed-by: Jeremy Bettis --- include/mock/mkbp_events_mock.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/mock/mkbp_events_mock.h b/include/mock/mkbp_events_mock.h index 3d686e3618..d8eea40cdd 100644 --- a/include/mock/mkbp_events_mock.h +++ b/include/mock/mkbp_events_mock.h @@ -15,10 +15,11 @@ struct mock_ctrl_mkbp_events { int mkbp_send_event_return; }; -#define MOCK_CTRL_DEFAULT_MKBP_EVENTS \ -(struct mock_ctrl_mkbp_events) { \ - .mkbp_send_event_return = 1, \ -} +#define MOCK_CTRL_DEFAULT_MKBP_EVENTS \ + (struct mock_ctrl_mkbp_events) \ + { \ + .mkbp_send_event_return = 1, \ + } extern struct mock_ctrl_mkbp_events mock_ctrl_mkbp_events; -- cgit v1.2.1 From 3ea5df4c586d29c1e7f1a39a2c66120e17659d94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:54 -0600 Subject: board/redrix/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6f96a2a2ba7acf94bb46fc319d8295b2db5f02e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728878 Reviewed-by: Jeremy Bettis --- board/redrix/board.h | 155 +++++++++++++++++++++++---------------------------- 1 file changed, 69 insertions(+), 86 deletions(-) diff --git a/board/redrix/board.h b/board/redrix/board.h index 96b48bd6be..2e65e84d2d 100644 --- a/board/redrix/board.h +++ b/board/redrix/board.h @@ -23,15 +23,15 @@ #define CONFIG_CHIPSET_RESUME_INIT_HOOK /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* TCS3400 ALS */ #define CONFIG_ALS @@ -48,9 +48,7 @@ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) - +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) /* Sensor console commands */ #define CONFIG_CMD_ACCELS @@ -65,7 +63,7 @@ #endif /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -73,7 +71,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_FRS_PPC @@ -83,17 +81,17 @@ #define CONFIG_USBC_PPC_NX20P3483 /* TODO: b/193452481 - measure and check these values on redrix */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -101,67 +99,67 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL - -#define GPIO_WLC_NRST_CONN GPIO_PEN_RST_L +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL + +#define GPIO_WLC_NRST_CONN GPIO_PEN_RST_L /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_WLC NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_WLC NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -179,9 +177,9 @@ #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Fan features */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT #define CONFIG_CUSTOM_FAN_CONTROL -#define RPM_DEVIATION 1 +#define RPM_DEVIATION 1 /* Charger defines */ #define CONFIG_CHARGER_BQ25720 @@ -192,12 +190,12 @@ * discharge current limit and what was tested to prevent the AP * rebooting with low charge level batteries. */ -#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192 +#define CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA 8192 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_PROFILE_OVERRIDE /* Keyboard features */ @@ -207,7 +205,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -236,35 +234,20 @@ enum sensor_id { SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; -enum battery_type { - BATTERY_DYNAPACK_COS, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_DYNAPACK_COS, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_FAN2, /* PWM7 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_FAN2, /* PWM7 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_1, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_1, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT }; #ifdef CONFIG_KEYBOARD_FACTORY_TEST extern const int keyboard_factory_scan_pins[][2]; -- cgit v1.2.1 From cc2dd85000ded9ffc49f6ad0cb3e8cda27a739a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:19 -0600 Subject: common/host_command_controller.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I56018cecba73bd82f15a01589ae8cc23dcd5c403 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729634 Reviewed-by: Jeremy Bettis --- common/host_command_controller.c | 37 +++++++++++++++---------------------- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/common/host_command_controller.c b/common/host_command_controller.c index eb35622ab3..4df5b6e449 100644 --- a/common/host_command_controller.c +++ b/common/host_command_controller.c @@ -16,8 +16,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_HOSTCMD, outstr) -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args) /* Number of attempts for each PD host command */ #define PD_HOST_COMMAND_ATTEMPTS 3 @@ -81,8 +81,7 @@ static int pd_host_command_internal(int command, int version, */ i2c_lock(I2C_PORT_PD_MCU, 1); i2c_set_timeout(I2C_PORT_PD_MCU, PD_HOST_COMMAND_TIMEOUT_US); - ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, - CONFIG_USB_PD_I2C_ADDR_FLAGS, + ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS, &req_buf[0], outsize + sizeof(rq) + 1, &resp_buf[0], 2, I2C_XFER_START); i2c_set_timeout(I2C_PORT_PD_MCU, 0); @@ -96,20 +95,17 @@ static int pd_host_command_internal(int command, int version, if (resp_len > (insize + sizeof(rs))) { /* Do a read to generate stop condition */ - i2c_xfer_unlocked(I2C_PORT_PD_MCU, - CONFIG_USB_PD_I2C_ADDR_FLAGS, + i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS, 0, 0, &resp_buf[2], 1, I2C_XFER_STOP); i2c_lock(I2C_PORT_PD_MCU, 0); - CPRINTS("response size is too large %d > %d", - resp_len, insize + sizeof(rs)); + CPRINTS("response size is too large %d > %d", resp_len, + insize + sizeof(rs)); return -EC_RES_RESPONSE_TOO_BIG; } /* Receive remaining data */ - ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, - CONFIG_USB_PD_I2C_ADDR_FLAGS, - 0, 0, - &resp_buf[2], resp_len, I2C_XFER_STOP); + ret = i2c_xfer_unlocked(I2C_PORT_PD_MCU, CONFIG_USB_PD_I2C_ADDR_FLAGS, + 0, 0, &resp_buf[2], resp_len, I2C_XFER_STOP); i2c_lock(I2C_PORT_PD_MCU, 0); if (ret) { CPRINTS("i2c transaction 2 failed: %d", ret); @@ -152,10 +148,9 @@ static int pd_host_command_internal(int command, int version, sum += *d; } - if ((uint8_t)sum) { - CPRINTS("command 0x%04x bad checksum returned: %d", - command, sum); + CPRINTS("command 0x%04x bad checksum returned: %d", command, + sum); return -EC_RES_INVALID_CHECKSUM; } @@ -163,8 +158,7 @@ static int pd_host_command_internal(int command, int version, return resp_len; } -int pd_host_command(int command, int version, - const void *outdata, int outsize, +int pd_host_command(int command, int version, const void *outdata, int outsize, void *indata, int insize) { int rv; @@ -183,7 +177,7 @@ int pd_host_command(int command, int version, /* If host command error due to i2c bus error, try again. */ if (rv != -EC_RES_BUS_ERROR) break; - task_wait_event(50*MSEC); + task_wait_event(50 * MSEC); } return rv; @@ -212,11 +206,11 @@ static int command_pd_mcu(int argc, char **argv) tmp = strtoi(argv[i], &e, 0); if (*e) return EC_ERROR_PARAM3; - outbuf[i-3] = tmp; + outbuf[i - 3] = tmp; } ret = pd_host_command(command, version, &outbuf, argc - 3, &inbuf, - sizeof(inbuf)); + sizeof(inbuf)); ccprintf("Host command 0x%02x, returned %d\n", command, ret); for (i = 0; i < ret; i++) @@ -224,6 +218,5 @@ static int command_pd_mcu(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu, - "cmd ver [params]", +DECLARE_CONSOLE_COMMAND(pdcmd, command_pd_mcu, "cmd ver [params]", "Send PD host command"); -- cgit v1.2.1 From c3323cdc3f0435f47e58a3a3d89c7934fe20a490 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:06 -0600 Subject: include/2id.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6dcc54f4d89e2d321ce09c35dbeb138844ecf494 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730197 Reviewed-by: Jeremy Bettis --- include/2id.h | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/include/2id.h b/include/2id.h index 8daa4d27db..4f871b63cd 100644 --- a/include/2id.h +++ b/include/2id.h @@ -25,8 +25,23 @@ struct vb2_id { #define EXPECTED_ID_SIZE VB2_ID_NUM_BYTES /* IDs to use for "keys" with sig_alg==VB2_SIG_NONE */ -#define VB2_ID_NONE_SHA1 {{0x00, 0x01,}} -#define VB2_ID_NONE_SHA256 {{0x02, 0x56,}} -#define VB2_ID_NONE_SHA512 {{0x05, 0x12,}} +#define VB2_ID_NONE_SHA1 \ + { \ + { \ + 0x00, 0x01, \ + } \ + } +#define VB2_ID_NONE_SHA256 \ + { \ + { \ + 0x02, 0x56, \ + } \ + } +#define VB2_ID_NONE_SHA512 \ + { \ + { \ + 0x05, 0x12, \ + } \ + } -#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */ +#endif /* VBOOT_REFERENCE_VBOOT_2ID_H_ */ -- cgit v1.2.1 From d0a753cb655b1e8e01b7ad9b2e8422d004127750 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:14 -0600 Subject: zephyr/projects/intelrvp/adlrvp/src/adlrvp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia05d4dc992be2081bb6d7a9980927a98910718fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730773 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/adlrvp/src/adlrvp.c | 46 +++++++++++++--------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c index bcb9bba1a8..960e149a38 100644 --- a/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c +++ b/zephyr/projects/intelrvp/adlrvp/src/adlrvp.c @@ -29,9 +29,8 @@ #include "usbc_ppc.h" #include "util.h" - -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -124,8 +123,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -211,11 +210,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -224,8 +223,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -251,9 +249,8 @@ static void configure_retimer_usbmux(void) case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; + TUSB1064_I2C_ADDR14_FLAGS; + usb_muxes[TYPE_C_PORT_0].driver = &tusb1064_usb_mux_driver; usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) @@ -275,15 +272,15 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + usb_muxes[TYPE_C_PORT_0].next_mux = + &soc_side_bb_retimer0_usb_mux; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + usb_muxes[TYPE_C_PORT_1].next_mux = + &soc_side_bb_retimer1_usb_mux; #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; @@ -357,8 +354,7 @@ __override int board_get_version(void) * This loop retries to ensure rail is settled and read is successful */ for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { - - rv = gpio_pin_get_dt(&bom_id_config[0]); + rv = gpio_pin_get_dt(&bom_id_config[0]); if (rv >= 0) break; @@ -374,21 +370,21 @@ __override int board_get_version(void) * BOM ID [2] : IOEX[0] * BOM ID [1:0] : IOEX[15:14] */ - bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; + bom_id = gpio_pin_get_dt(&bom_id_config[0]) << 2; bom_id |= gpio_pin_get_dt(&bom_id_config[1]) << 1; bom_id |= gpio_pin_get_dt(&bom_id_config[2]); /* * FAB ID [1:0] : IOEX[2:1] + 1 */ - fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; + fab_id = gpio_pin_get_dt(&fab_id_config[0]) << 1; fab_id |= gpio_pin_get_dt(&fab_id_config[1]); fab_id += 1; /* * BOARD ID[5:0] : IOEX[13:8] */ - board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; + board_id = gpio_pin_get_dt(&board_id_config[0]) << 5; board_id |= gpio_pin_get_dt(&board_id_config[1]) << 4; board_id |= gpio_pin_get_dt(&board_id_config[2]) << 3; board_id |= gpio_pin_get_dt(&board_id_config[3]) << 2; @@ -450,4 +446,4 @@ static int board_pre_task_peripheral_init(const struct device *unused) return 0; } SYS_INIT(board_pre_task_peripheral_init, APPLICATION, - CONFIG_APPLICATION_INIT_PRIORITY); + CONFIG_APPLICATION_INIT_PRIORITY); -- cgit v1.2.1 From d2bf77e2cc061b5f4483cbe0fe4fab8cb08ecd7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:52 -0600 Subject: board/adlrvpm_ite/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf7838f58e6c6344c536955edc6ff8edc72cbee6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727962 Reviewed-by: Jeremy Bettis --- board/adlrvpm_ite/board.h | 103 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/adlrvpm_ite/board.h diff --git a/board/adlrvpm_ite/board.h b/board/adlrvpm_ite/board.h deleted file mode 120000 index 2c75a3883c..0000000000 --- a/board/adlrvpm_ite/board.h +++ /dev/null @@ -1 +0,0 @@ -../adlrvpp_ite/board.h \ No newline at end of file diff --git a/board/adlrvpm_ite/board.h b/board/adlrvpm_ite/board.h new file mode 100644 index 0000000000..4059cf05dd --- /dev/null +++ b/board/adlrvpm_ite/board.h @@ -0,0 +1,102 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel ADL-P-RVP-ITE board-specific configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* ITE EC variant */ +#define VARIANT_INTELRVP_EC_IT8320 + +#include "adlrvp.h" + +/* + * Macros for GPIO signals used in common code that don't match the + * schematic names. Signal names in gpio.inc match the schematic and are + * then redefined here to so it's more clear which signal is being used for + * which purpose. + */ +#define GPIO_AC_PRESENT GPIO_BC_ACOK_EC +#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL_EC +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW_EC +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE_EC +#define GPIO_PCH_WAKE_L GPIO_PCH_WAKE_N +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N_EC +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_EC +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_R_L +#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3_EC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL_EC +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC_R +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT +#define GPIO_ESPI_RESET_L GPIO_ESPI_RST_R +#define GPIO_UART1_RX GPIO_UART_SERVO_TX_EC_RX +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET_EC +#define GPIO_BAT_LED_RED_L GPIO_LED_1_L_EC +#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L_EC +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_EC +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC +#define GPIO_PCH_DSW_PWROK GPIO_DSW_PWROK_EC +#define GPIO_EN_PP3300_A GPIO_EC_DS3 +#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION + +/* I2C ports & Configs */ +#define CONFIG_IT83XX_SMCLK2_ON_GPC7 + +#define I2C_PORT_CHARGER IT83XX_I2C_CH_B + +/* Battery */ +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B + +/* Board ID */ +#define I2C_PORT_PCA9555_BOARD_ID_GPIO IT83XX_I2C_CH_B + +/* Port 80 */ +#define I2C_PORT_PORT80 IT83XX_I2C_CH_B + +/* USB-C I2C */ +#define I2C_PORT_TYPEC_0 IT83XX_I2C_CH_C +#define I2C_PORT_TYPEC_1 IT83XX_I2C_CH_F +#if defined(HAS_TASK_PD_C2) +#define I2C_PORT_TYPEC_2 IT83XX_I2C_CH_E +#define I2C_PORT_TYPEC_3 IT83XX_I2C_CH_D +#endif + +/* TCPC */ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 + +/* Config Fan */ +#define GPIO_FAN_POWER_EN GPIO_EC_THRM_SEN_PWRGATE_N +#define GPIO_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD_EC + +/* Increase EC speed */ +#undef PLL_CLOCK +#define PLL_CLOCK 96000000 + +#ifndef __ASSEMBLER__ + +enum adlrvp_i2c_channel { + I2C_CHAN_FLASH, + I2C_CHAN_BATT_CHG, + I2C_CHAN_TYPEC_0, + I2C_CHAN_TYPEC_1, +#if defined(HAS_TASK_PD_C2) + I2C_CHAN_TYPEC_2, + I2C_CHAN_TYPEC_3, +#endif + I2C_CHAN_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 9662f2854f73c12f05549aa3622716ab609bcc44 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:12 -0600 Subject: board/ampton/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1fd696d2d7f8106f8232886e91789b0f00b5ac54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727983 Reviewed-by: Jeremy Bettis --- board/ampton/board.c | 121 +++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 66 deletions(-) diff --git a/board/ampton/board.c b/board/ampton/board.c index 3e7bee1993..4ba0bbd60d 100644 --- a/board/ampton/board.c +++ b/board/ampton/board.c @@ -65,8 +65,8 @@ int ppc_get_alert_status(int port) /******************************************************************************/ /* USB-C MUX Configuration */ -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 +#define USB_PD_PORT_ITE_0 0 +#define USB_PD_PORT_ITE_1 1 static int tune_mux(const struct usb_mux *me); @@ -101,8 +101,8 @@ static int tune_mux(const struct usb_mux *me) /* Auto EQ disabled, compensate for channel lost up to 3.6dB */ RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_EQ_CONFIGURATION, 0x98)); /* DP output swing adjustment +15% */ - RETURN_ERROR(mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION, - 0xc0)); + RETURN_ERROR( + mux_write(me, PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION, 0xc0)); return EC_SUCCESS; } @@ -110,44 +110,44 @@ static int tune_mux(const struct usb_mux *me) /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus C0 sensing (10x voltage divider). PPVAR_USB_C0_VBUS */ - [ADC_VBUS_C0] = {.name = "VBUS_C0", - .factor_mul = 10 * ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13}, + [ADC_VBUS_C0] = { .name = "VBUS_C0", + .factor_mul = 10 * ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, /* Vbus C1 sensing (10x voltage divider). SUB_EC_ADC */ - [ADC_VBUS_C1] = {.name = "VBUS_C1", - .factor_mul = 10 * ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH14}, + [ADC_VBUS_C1] = { .name = "VBUS_C1", + .factor_mul = 10 * ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH14 }, /* Convert to raw mV for thermistor table lookup */ - [ADC_TEMP_SENSOR_AMB] = {.name = "TEMP_AMB", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3}, + [ADC_TEMP_SENSOR_AMB] = { .name = "TEMP_AMB", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, /* Convert to raw mV for thermistor table lookup */ - [ADC_TEMP_SENSOR_CHARGER] = {.name = "TEMP_CHARGER", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH5}, + [ADC_TEMP_SENSOR_CHARGER] = { .name = "TEMP_CHARGER", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH5 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -156,35 +156,25 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); static struct mutex g_lid_mutex; static struct mutex g_base_mutex; -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t gyro_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t gyro_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref_icm42607 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref_sku57 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standard_ref_sku57 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; static struct bmi_drv_data_t g_bmi160_data; @@ -355,9 +345,9 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); static int board_is_convertible(void) { /* SKU IDs of Ampton & unprovisioned: 1, 2, 3, 4, 255 */ - return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 - || sku_id == 57 || sku_id == 255; - } + return sku_id == 1 || sku_id == 2 || sku_id == 3 || sku_id == 4 || + sku_id == 57 || sku_id == 255; +} static int board_with_sensor_bma253(void) { @@ -389,13 +379,12 @@ static void board_update_sensor_config_from_sku(void) if (board_with_sensor_icm42607()) { motion_sensors[BASE_ACCEL] = motion_sensor_accel_icm42607; - motion_sensors[BASE_GYRO] = - motion_sensor_gyro_icm42607; + motion_sensors[BASE_GYRO] = motion_sensor_gyro_icm42607; ccprints("Gyro sensor: ICM-42607"); } if (sku_id == 57) motion_sensors[LID_ACCEL].rot_standard_ref = - &lid_standard_ref_sku57; + &lid_standard_ref_sku57; /* Enable Base Accel interrupt */ gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L); -- cgit v1.2.1 From 3003ad71e9910f122e04c0f2262998107be6b482 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:49 -0600 Subject: baseboard/kukui/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieac5352185712e9d0009ea51766b8048d19c9a4c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727915 Reviewed-by: Jeremy Bettis --- baseboard/kukui/baseboard.c | 79 ++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/baseboard/kukui/baseboard.c b/baseboard/kukui/baseboard.c index c9831ed300..5b34568840 100644 --- a/baseboard/kukui/baseboard.c +++ b/baseboard/kukui/baseboard.c @@ -14,8 +14,8 @@ #include "registers.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #ifndef CONFIG_CHARGER_RUNTIME_CONFIG #if defined(VARIANT_KUKUI_CHARGER_MT6370) @@ -54,11 +54,11 @@ void board_config_pre_init(void) * Ch4: USART1_TX / Ch5: USART1_RX (1000) * Ch6: SPI2_RX / Ch7: SPI2_TX (0011) */ - STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | - (3 << 20) | (3 << 24); + STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) | + (3 << 24); #elif defined(VARIANT_KUKUI_EC_STM32L431) -#ifdef CONFIG_DMA +#ifdef CONFIG_DMA dma_init(); #endif /* @@ -102,43 +102,43 @@ enum kukui_board_version { /* map from kukui_board_version to board id voltage in mv */ #ifdef VARIANT_KUKUI_EC_IT81202 const int16_t kukui_board_id_map[] = { - 136, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 388, /* 51.1k , 6.8K ohm */ - 584, /* 51.1K , 11K ohm */ - 785, /* 56K , 17.4K ohm */ - 993, /* 51.1K , 22K ohm */ - 1221, /* 51.1K , 30K ohm */ - 1433, /* 51.1K , 39.2K ohm */ - 1650, /* 56K , 56K ohm */ - 1876, /* 47K , 61.9K ohm */ - 2084, /* 47K , 80.6K ohm */ - 2273, /* 56K , 124K ohm */ - 2461, /* 51.1K , 150K ohm */ - 2672, /* 47K , 200K ohm */ - 2889, /* 47K , 330K ohm */ - 3086, /* 47K , 680K ohm */ - 3300, /* 56K , NC */ + 136, /* 51.1K , 2.2K(gru 3.3K) ohm */ + 388, /* 51.1k , 6.8K ohm */ + 584, /* 51.1K , 11K ohm */ + 785, /* 56K , 17.4K ohm */ + 993, /* 51.1K , 22K ohm */ + 1221, /* 51.1K , 30K ohm */ + 1433, /* 51.1K , 39.2K ohm */ + 1650, /* 56K , 56K ohm */ + 1876, /* 47K , 61.9K ohm */ + 2084, /* 47K , 80.6K ohm */ + 2273, /* 56K , 124K ohm */ + 2461, /* 51.1K , 150K ohm */ + 2672, /* 47K , 200K ohm */ + 2889, /* 47K , 330K ohm */ + 3086, /* 47K , 680K ohm */ + 3300, /* 56K , NC */ }; #define THRESHOLD_MV 103 /* Simply assume 3300/16/2 */ #else const int16_t kukui_board_id_map[] = { - 109, /* 51.1K , 2.2K(gru 3.3K) ohm */ - 211, /* 51.1k , 6.8K ohm */ - 319, /* 51.1K , 11K ohm */ - 427, /* 56K , 17.4K ohm */ - 542, /* 51.1K , 22K ohm */ - 666, /* 51.1K , 30K ohm */ - 781, /* 51.1K , 39.2K ohm */ - 900, /* 56K , 56K ohm */ - 1023, /* 47K , 61.9K ohm */ - 1137, /* 47K , 80.6K ohm */ - 1240, /* 56K , 124K ohm */ - 1343, /* 51.1K , 150K ohm */ - 1457, /* 47K , 200K ohm */ - 1576, /* 47K , 330K ohm */ - 1684, /* 47K , 680K ohm */ - 1800, /* 56K , NC */ + 109, /* 51.1K , 2.2K(gru 3.3K) ohm */ + 211, /* 51.1k , 6.8K ohm */ + 319, /* 51.1K , 11K ohm */ + 427, /* 56K , 17.4K ohm */ + 542, /* 51.1K , 22K ohm */ + 666, /* 51.1K , 30K ohm */ + 781, /* 51.1K , 39.2K ohm */ + 900, /* 56K , 56K ohm */ + 1023, /* 47K , 61.9K ohm */ + 1137, /* 47K , 80.6K ohm */ + 1240, /* 56K , 124K ohm */ + 1343, /* 51.1K , 150K ohm */ + 1457, /* 47K , 200K ohm */ + 1576, /* 47K , 330K ohm */ + 1684, /* 47K , 680K ohm */ + 1800, /* 56K , NC */ }; #define THRESHOLD_MV 56 /* Simply assume 1800/16/2 */ @@ -178,7 +178,7 @@ int board_get_version(void) * for this board. */ if (CONFIG_DEDICATED_CHARGE_PORT_COUNT == 0 && - version != BOARD_VERSION_UNKNOWN) + version != BOARD_VERSION_UNKNOWN) adc_disable(); #endif @@ -216,8 +216,7 @@ __override void lid_angle_peripheral_enable(int enable) * ignore input devices or not. */ if (!chipset_in_s0) - keyboard_scan_enable(0, - KB_SCAN_DISABLE_LID_ANGLE); + keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE); } } #endif -- cgit v1.2.1 From 86b8420fcae203139a26d8a09a6e7ef5994976ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:30 -0600 Subject: board/homestar/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I99b661817c5e040f9581939383564482d8957fb4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728467 Reviewed-by: Jeremy Bettis --- board/homestar/base_detect.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/homestar/base_detect.c b/board/homestar/base_detect.c index b08784357b..cf5866626c 100644 --- a/board/homestar/base_detect.c +++ b/board/homestar/base_detect.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Make sure POGO VBUS starts later then PP3300_HUB when power on */ #define BASE_DETECT_EN_LATER_US (600 * MSEC) @@ -96,8 +96,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -188,8 +188,7 @@ static void base_enable(void) { /* Enable base detection interrupt. */ base_detect_debounce_time = get_time().val; - hook_call_deferred(&base_detect_deferred_data, - BASE_DETECT_EN_LATER_US); + hook_call_deferred(&base_detect_deferred_data, BASE_DETECT_EN_LATER_US); gpio_enable_interrupt(GPIO_BASE_DET_L); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, base_enable, HOOK_PRIO_DEFAULT); @@ -215,7 +214,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From 02c56d326a2493e13fd99f85652fb02d9a342a2d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:54 -0600 Subject: common/charger_profile_override.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1a288e5a0285bdc1f414a8195f8fd30eeda15dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729600 Reviewed-by: Jeremy Bettis --- common/charger_profile_override.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/common/charger_profile_override.c b/common/charger_profile_override.c index 2b691b9a5a..62b7c19321 100644 --- a/common/charger_profile_override.c +++ b/common/charger_profile_override.c @@ -20,17 +20,17 @@ static int test_vtg_mV = -1; static int fast_charging_allowed = 1; -int charger_profile_override_common(struct charge_state_data *curr, - const struct fast_charge_params *fast_chg_params, - const struct fast_charge_profile **prev_chg_prof_info, - int batt_vtg_max) +int charger_profile_override_common( + struct charge_state_data *curr, + const struct fast_charge_params *fast_chg_params, + const struct fast_charge_profile **prev_chg_prof_info, int batt_vtg_max) { int i, voltage_range; /* temp in 0.1 deg C */ int temp_c = curr->batt.temperature - 2731; int temp_ranges = fast_chg_params->total_temp_ranges; const struct fast_charge_profile *chg_profile_info = - fast_chg_params->chg_profile_info; + fast_chg_params->chg_profile_info; #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST if (fast_charge_test_on && test_vtg_mV != -1) { @@ -78,9 +78,9 @@ int charger_profile_override_common(struct charge_state_data *curr, if (!(curr->batt.flags & BATT_FLAG_BAD_VOLTAGE)) { for (i = 0; i < CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES - 1; - i++) { + i++) { if (curr->batt.voltage < - fast_chg_params->voltage_mV[i]) { + fast_chg_params->voltage_mV[i]) { voltage_range = i; break; } @@ -98,13 +98,13 @@ int charger_profile_override_common(struct charge_state_data *curr, * Okay, impose our custom will: */ curr->requested_current = - (*prev_chg_prof_info)->current_mA[voltage_range]; + (*prev_chg_prof_info)->current_mA[voltage_range]; curr->requested_voltage = curr->requested_current ? batt_vtg_max : 0; #ifdef CONFIG_CMD_CHARGER_PROFILE_OVERRIDE_TEST if (fast_charge_test_on) ccprintf("Fast charge profile i=%dmA, v=%dmV\n", - curr->requested_current, curr->requested_voltage); + curr->requested_current, curr->requested_voltage); #endif return 0; @@ -143,8 +143,7 @@ static int command_fastcharge(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, - "[on|off]", +DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]", "Get or set fast charging profile"); #endif -- cgit v1.2.1 From 23c3f29c6cc85781591150ce2e23fe4c8eca5e45 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:49 -0600 Subject: chip/npcx/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If31ba44ca321ba8aecae347233a33776089ad593 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729380 Reviewed-by: Jeremy Bettis --- chip/npcx/flash.c | 67 +++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c index 768c2ced29..3067258bb2 100644 --- a/chip/npcx/flash.c +++ b/chip/npcx/flash.c @@ -68,7 +68,7 @@ static void flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -94,7 +94,7 @@ static int flash_wait_ready(void) flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; /* Busy bit is clear */ @@ -316,8 +316,8 @@ static int flash_set_status_for_prot(int reg1, int reg2) #endif flash_set_status(reg1, reg2); - spi_flash_reg_to_protect(reg1, reg2, - &addr_prot_start, &addr_prot_length); + spi_flash_reg_to_protect(reg1, reg2, &addr_prot_start, + &addr_prot_length); return EC_SUCCESS; } @@ -328,8 +328,8 @@ static int flash_check_prot_range(unsigned int offset, unsigned int bytes) if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; /* Check if ranges overlap */ - if (MAX(addr_prot_start, offset) < MIN(addr_prot_start + - addr_prot_length, offset + bytes)) + if (MAX(addr_prot_start, offset) < + MIN(addr_prot_start + addr_prot_length, offset + bytes)) return EC_ERROR_ACCESS_DENIED; return EC_SUCCESS; @@ -369,7 +369,6 @@ static int flash_check_prot_reg(unsigned int offset, unsigned int bytes) return EC_ERROR_ACCESS_DENIED; return EC_SUCCESS; - } static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, @@ -395,7 +394,7 @@ static int flash_write_prot_reg(unsigned int offset, unsigned int bytes, } static void flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down */ @@ -413,15 +412,17 @@ static void flash_burst_write(unsigned int dest_addr, unsigned int bytes, } static int flash_program_bytes(uint32_t offset, uint32_t bytes, - const uint8_t *data) + const uint8_t *data) { int write_size; int rv; while (bytes > 0) { /* Write length can not go beyond the end of the flash page */ - write_size = MIN(bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE - - (offset & (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1))); + write_size = MIN(bytes, + CONFIG_FLASH_WRITE_IDEAL_SIZE - + (offset & + (CONFIG_FLASH_WRITE_IDEAL_SIZE - 1))); /* Enable write */ rv = flash_write_enable(); @@ -436,9 +437,9 @@ static int flash_program_bytes(uint32_t offset, uint32_t bytes, if (rv) return rv; - data += write_size; + data += write_size; offset += write_size; - bytes -= write_size; + bytes -= write_size; } return rv; @@ -467,7 +468,7 @@ int crec_flash_physical_read(int offset, int size, char *data) /* Burst read transaction */ for (idx = 0; idx < size; idx++) { /* 1101 0101 - EXEC, RD, NO CMD, NO ADDR, 4 bytes */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; /* wait for UMA to complete */ while (IS_BIT_SET(NPCX_UMA_CTS, EXEC_DONE)) ; @@ -493,8 +494,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) int rv; /* Fail if offset, size, and data aren't at least word-aligned */ - if ((offset | size - | (uint32_t)(uintptr_t)data) & (CONFIG_FLASH_WRITE_SIZE - 1)) + if ((offset | size | (uint32_t)(uintptr_t)data) & + (CONFIG_FLASH_WRITE_SIZE - 1)) return EC_ERROR_INVAL; /* check protection */ @@ -510,7 +511,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) while (size > 0) { /* First write multiples of 256, then (size % 256) last */ write_len = ((size % CONFIG_FLASH_WRITE_IDEAL_SIZE) == size) ? - size : CONFIG_FLASH_WRITE_IDEAL_SIZE; + size : + CONFIG_FLASH_WRITE_IDEAL_SIZE; /* check protection */ if (flash_check_prot_range(dest_addr, write_len)) { @@ -522,9 +524,9 @@ int crec_flash_physical_write(int offset, int size, const char *data) if (rv) break; - data += write_len; + data += write_len; dest_addr += write_len; - size -= write_len; + size -= write_len; } /* Enable tri-state */ @@ -551,7 +553,7 @@ int crec_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - offset += CONFIG_FLASH_ERASE_SIZE) { + offset += CONFIG_FLASH_ERASE_SIZE) { /* check protection */ if (flash_check_prot_range(offset, CONFIG_FLASH_ERASE_SIZE)) { rv = EC_ERROR_ACCESS_DENIED; @@ -645,7 +647,6 @@ int crec_flash_physical_protect_now(int all) return EC_SUCCESS; } - int crec_flash_physical_protect_at_boot(uint32_t new_flags) { int ret; @@ -657,8 +658,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) } ret = flash_write_prot_reg(CONFIG_WP_STORAGE_OFF, - CONFIG_WP_STORAGE_SIZE, - 1); + CONFIG_WP_STORAGE_SIZE, 1); /* * Set UMA_LOCK bit for locking all UMA transaction. @@ -672,9 +672,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | - EC_FLASH_PROTECT_ALL_NOW; + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | + EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -690,7 +689,7 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * the WP GPIO is asserted. */ if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && - (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) + (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_NOW; return ret; @@ -759,8 +758,7 @@ static enum ec_status flash_command_spi_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, - flash_command_spi_info, +DECLARE_HOST_COMMAND(EC_CMD_FLASH_SPI_INFO, flash_command_spi_info, EC_VER_MASK(0)); #endif @@ -801,8 +799,7 @@ static int command_flash_spi_sel_lock(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(flash_spi_lock, command_flash_spi_sel_lock, - "[on | off]", - "Lock spi flash interface selection"); + "[on | off]", "Lock spi flash interface selection"); static int command_flash_tristate(int argc, char **argv) { @@ -817,8 +814,7 @@ static int command_flash_tristate(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, - "[on | off]", +DECLARE_CONSOLE_COMMAND(flash_tristate, command_flash_tristate, "[on | off]", "Tristate spi flash pins"); #endif /* CONFIG_CMD_FLASH_TRISTATE */ @@ -832,10 +828,9 @@ static int command_flash_chip(int argc, char **argv) flash_get_jedec_id(jedec_id); ccprintf("Manufacturer: 0x%02x, DID: 0x%02x%02x\n", jedec_id[0], - jedec_id[1], jedec_id[2]); + jedec_id[1], jedec_id[2]); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, - NULL, +DECLARE_CONSOLE_COMMAND(flashchip, command_flash_chip, NULL, "Print flash chip info"); -- cgit v1.2.1 From fa1706ea4c5e46360351ffade279b00ed2a1a79a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:18 -0600 Subject: board/pirika/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifbf5facb3f054ffac96210d22e925d02e0638ac1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728829 Reviewed-by: Jeremy Bettis --- board/pirika/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/pirika/cbi_ssfc.h b/board/pirika/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/pirika/cbi_ssfc.h +++ b/board/pirika/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 9b5482844be0b3df075609a1c1ee05e9b25d702e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:48 -0600 Subject: board/pompom/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I774c182604d23e7e01f56a0e9bbca1e8a9bb0061 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728838 Reviewed-by: Jeremy Bettis --- board/pompom/board.c | 139 +++++++++++++++++++-------------------------------- 1 file changed, 51 insertions(+), 88 deletions(-) diff --git a/board/pompom/board.c b/board/pompom/board.c index 56241083d3..e0b5c70588 100644 --- a/board/pompom/board.c +++ b/board/pompom/board.c @@ -34,8 +34,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -115,10 +115,8 @@ __override struct keyboard_scan_config keyscan_config = { * as it uses the new location (KSO_00/KSI_03). And T11 key, which maps * to KSO_01/KSI_00, is not there. */ - .actual_key_mask = { - 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -129,34 +127,26 @@ __override struct keyboard_scan_config keyscan_config = { /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -164,37 +154,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -207,11 +182,9 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -299,10 +272,8 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_LID_ACCEL_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 2+ has the hardware fix. Don't need the following @@ -351,9 +322,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); /* Called on AP S0 -> S3 transition */ static void board_chipset_suspend(void) @@ -431,8 +402,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -460,7 +430,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -484,24 +453,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) @@ -524,17 +491,13 @@ static struct accelgyro_saved_data_t g_bma255_data; static struct stprivate_data g_lis2dwl_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -647,8 +610,8 @@ static void board_detect_motionsensor(void) * BMA253 and LIS2DWL have same slave address, so we check the * LIS2DWL WHO AM I register to check the lid accel type */ - i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS, - LIS2DW12_WHO_AM_I_REG, &val); + i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS, LIS2DW12_WHO_AM_I_REG, + &val); if (val == LIS2DW12_WHO_AM_I) { motion_sensors[LID_ACCEL] = lis2dwl_lid_accel; -- cgit v1.2.1 From ea1f2efc581ca2bcac9a5bd0a88e93219e131abe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:44 -0600 Subject: core/host/timer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id888c0d9be8a929411ab24717028fbfc701a709f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729845 Reviewed-by: Jeremy Bettis --- core/host/timer.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/core/host/timer.c b/core/host/timer.c index 3c3695cad4..67271c5112 100644 --- a/core/host/timer.c +++ b/core/host/timer.c @@ -90,15 +90,12 @@ int timestamp_expired(timestamp_t deadline, const timestamp_t *now) void timer_init(void) { - if (!time_set) { /* * Start the timer just before the 64-bit rollover to try * and catch 32-bit rollover/truncation bugs. */ - timestamp_t ts = { - .val = 0xFFFFFFF0 - }; + timestamp_t ts = { .val = 0xFFFFFFF0 }; force_time(ts); } -- cgit v1.2.1 From e716b2338257128d9d107add387dc4630d668453 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:02 -0600 Subject: driver/battery/mm8013.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I223dfed381c2e3076fdaca380f63d1da0188448c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729951 Reviewed-by: Jeremy Bettis --- driver/battery/mm8013.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/driver/battery/mm8013.c b/driver/battery/mm8013.c index 04503da2f5..01cb04c540 100644 --- a/driver/battery/mm8013.c +++ b/driver/battery/mm8013.c @@ -34,8 +34,8 @@ static int mm8013_read_block(int offset, uint8_t *data, int len) { int rv; - rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS, - offset, data, len); + rv = i2c_read_block(I2C_PORT_BATTERY, MM8013_ADDR_FLAGS, offset, data, + len); usleep(I2C_WAIT_TIME); if (rv) return rv; @@ -52,8 +52,8 @@ static int battery_current(int *current) int16_t tmp; int rv; - rv = mm8013_read_block(REG_AVERAGE_CURRENT, - (uint8_t *)&tmp, sizeof(int16_t)); + rv = mm8013_read_block(REG_AVERAGE_CURRENT, (uint8_t *)&tmp, + sizeof(int16_t)); if (rv) return rv; *current = tmp; @@ -66,8 +66,8 @@ int battery_device_name(char *device_name, int buf_size) int rv; char out_buf[BATTERY_PACK_INFO_LENGTH + 1]; - rv = mm8013_read_block(REG_PRODUCT_INFORMATION, - (uint8_t *)out_buf, BATTERY_PACK_INFO_LENGTH); + rv = mm8013_read_block(REG_PRODUCT_INFORMATION, (uint8_t *)out_buf, + BATTERY_PACK_INFO_LENGTH); if (rv) return rv; @@ -181,7 +181,7 @@ enum battery_present battery_is_present(void) void battery_get_params(struct batt_params *batt) { - struct batt_params batt_new = {0}; + struct batt_params batt_new = { 0 }; int flag = 0; /* -- cgit v1.2.1 From bdb9ec6778ea45987378f29ad8db8a48dafd0e11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:28 -0600 Subject: include/fpsensor_state.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If342e40358ad1edb1d25906d0670cbd08652d987 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730291 Reviewed-by: Jeremy Bettis --- include/fpsensor_state.h | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/include/fpsensor_state.h b/include/fpsensor_state.h index 98d5b63783..9a5476a260 100644 --- a/include/fpsensor_state.h +++ b/include/fpsensor_state.h @@ -28,14 +28,13 @@ #endif #define SBP_ENC_KEY_LEN 16 -#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \ - (FP_ALGORITHM_TEMPLATE_SIZE + \ - FP_POSITIVE_MATCH_SALT_BYTES + \ - sizeof(struct ec_fp_template_encryption_metadata)) +#define FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE \ + (FP_ALGORITHM_TEMPLATE_SIZE + FP_POSITIVE_MATCH_SALT_BYTES + \ + sizeof(struct ec_fp_template_encryption_metadata)) /* Events for the FPSENSOR task */ -#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_SENSOR_IRQ TASK_EVENT_CUSTOM_BIT(0) +#define TASK_EVENT_UPDATE_CONFIG TASK_EVENT_CUSTOM_BIT(1) #define FP_NO_SUCH_TEMPLATE -1 @@ -53,8 +52,8 @@ extern uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE]; */ extern uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE]; /* Salt used in derivation of positive match secret. */ -extern uint8_t fp_positive_match_salt - [FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES]; +extern uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT] + [FP_POSITIVE_MATCH_SALT_BYTES]; /* Index of the last enrolled but not retrieved template. */ extern int8_t template_newly_enrolled; /* Number of used templates */ @@ -128,14 +127,13 @@ int fp_set_sensor_mode(uint32_t mode, uint32_t *mode_output); * @return EC_SUCCESS if the request is valid, error code otherwise. */ int fp_enable_positive_match_secret(uint32_t fgr, - struct positive_match_secret_state *state); + struct positive_match_secret_state *state); /** * Disallow positive match secret for any finger to be read. * * @param state the state of positive match secret, e.g. readable or not. */ -void fp_disable_positive_match_secret( - struct positive_match_secret_state *state); +void fp_disable_positive_match_secret(struct positive_match_secret_state *state); #endif /* __CROS_EC_FPSENSOR_STATE_H */ -- cgit v1.2.1 From 1fb01d6d9743a1e659f86e55b5bfea3bc1716007 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:04 -0600 Subject: core/minute-ia/interrupts.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8b9b6a6807fdcb59dfa74b1684e56694a17c8b1b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729852 Reviewed-by: Jeremy Bettis --- core/minute-ia/interrupts.c | 105 +++++++++++++++++++++----------------------- 1 file changed, 50 insertions(+), 55 deletions(-) diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index 2d55d3129e..cf16217062 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -20,8 +20,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* The IDT - initialized in init.S */ extern struct idt_entry __idt[NUM_VECTORS]; @@ -54,7 +54,7 @@ static void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val) * bitmap for current IRQ's mask status * ISH support max 64 IRQs, 64 bit bitmap value is ok */ -#define ISH_MAX_IOAPIC_IRQS (64) +#define ISH_MAX_IOAPIC_IRQS (64) uint64_t ioapic_irq_mask_bitmap; /** @@ -70,7 +70,7 @@ uint64_t disable_all_interrupts(void) uint64_t saved_map; int i; - saved_map = ioapic_irq_mask_bitmap; + saved_map = ioapic_irq_mask_bitmap; for (i = 0; i < ISH_MAX_IOAPIC_IRQS; i++) { if (((uint64_t)0x1 << i) & saved_map) @@ -179,27 +179,27 @@ static const irq_desc_t system_irqs[] = { * and go directly to the CPU core, so get_current_interrupt_vector * cannot be used. */ -#define DEFINE_EXN_HANDLER(vector) \ +#define DEFINE_EXN_HANDLER(vector) \ _DEFINE_EXN_HANDLER(vector, exception_panic_##vector) -#define _DEFINE_EXN_HANDLER(vector, name) \ - void __keep name(void); \ - noreturn void name(void) \ - { \ - __asm__ ("push $0\n" \ - "push $" #vector "\n" \ - "call exception_panic\n"); \ - __builtin_unreachable(); \ +#define _DEFINE_EXN_HANDLER(vector, name) \ + void __keep name(void); \ + noreturn void name(void) \ + { \ + __asm__("push $0\n" \ + "push $" #vector "\n" \ + "call exception_panic\n"); \ + __builtin_unreachable(); \ } -#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector) \ +#define DEFINE_EXN_HANDLER_W_ERRORCODE(vector) \ _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, exception_panic_##vector) -#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name) \ - void __keep name(void); \ - noreturn void name(void) \ - { \ - __asm__ ("push $" #vector "\n" \ - "call exception_panic\n"); \ - __builtin_unreachable(); \ +#define _DEFINE_EXN_HANDLER_W_ERRORCODE(vector, name) \ + void __keep name(void); \ + noreturn void name(void) \ + { \ + __asm__("push $" #vector "\n" \ + "call exception_panic\n"); \ + __builtin_unreachable(); \ } DEFINE_EXN_HANDLER(0); @@ -228,15 +228,10 @@ DEFINE_EXN_HANDLER(20); * watchdog timer expiration. However, this time, hardware does not * push errorcode, and we must account for that by pushing zero. */ -noreturn __keep -void exception_panic_wdt(uint32_t cs) +noreturn __keep void exception_panic_wdt(uint32_t cs) { - exception_panic( - CONFIG_MIA_WDT_VEC, - 0, - (uint32_t)__builtin_return_address(0), - cs, - 0); + exception_panic(CONFIG_MIA_WDT_VEC, 0, + (uint32_t)__builtin_return_address(0), cs, 0); } void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags) @@ -244,7 +239,7 @@ void set_interrupt_gate(uint8_t num, isr_handler_t func, uint8_t flags) uint16_t code_segment; /* When the flat model is used the CS will never change. */ - __asm volatile ("mov %%cs, %0":"=r" (code_segment)); + __asm volatile("mov %%cs, %0" : "=r"(code_segment)); __idt[num].dword_lo = GEN_IDT_DESC_LO(func, code_segment, flags); __idt[num].dword_up = GEN_IDT_DESC_UP(func, code_segment, flags); @@ -384,26 +379,27 @@ void handle_lapic_lvt_error(void) /* LAPIC LVT error is not an IRQ and can not use DECLARE_IRQ() to call. */ void _lapic_error_handler(void); -__asm__ ( - ".section .text._lapic_error_handler\n" +__asm__(".section .text._lapic_error_handler\n" "_lapic_error_handler:\n" - "pusha\n" - ASM_LOCK_PREFIX "addl $1, __in_isr\n" - "movl %esp, %eax\n" - "movl $stack_end, %esp\n" - "push %eax\n" + "pusha\n" ASM_LOCK_PREFIX "addl $1, __in_isr\n" + "movl %esp, %eax\n" + "movl $stack_end, %esp\n" + "push %eax\n" #ifdef CONFIG_TASK_PROFILING - "push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n" - "call task_start_irq_handler\n" - "addl $0x04, %esp\n" + "push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n" + "call task_start_irq_handler\n" + "addl $0x04, %esp\n" #endif - "call handle_lapic_lvt_error\n" - "pop %esp\n" - "movl $0x00, (0xFEE000B0)\n" /* Set EOI for LAPIC */ - ASM_LOCK_PREFIX "subl $1, __in_isr\n" - "popa\n" - "iret\n" - ); + "call handle_lapic_lvt_error\n" + "pop %esp\n" + "movl $0x00, (0xFEE000B0)\n" /* Set + EOI + for + LAPIC + */ + ASM_LOCK_PREFIX "subl $1, __in_isr\n" + "popa\n" + "iret\n"); /* Should only be called in interrupt context */ void unhandled_vector(void) @@ -411,7 +407,7 @@ void unhandled_vector(void) uint32_t vec = get_current_interrupt_vector(); CPRINTF("Ignoring vector 0x%0x!\n", vec); /* Put the vector number in eax so default_int_handler can use it */ - asm("" : : "a" (vec)); + asm("" : : "a"(vec)); } /** @@ -454,8 +450,7 @@ void init_interrupts(void) /* Setup gates for IRQs declared by drivers using DECLARE_IRQ */ for (p = __irq_data; p < __irq_data_end; p++) - set_interrupt_gate(IRQ_TO_VEC(p->irq), - p->handler, + set_interrupt_gate(IRQ_TO_VEC(p->irq), p->handler, IDT_DESC_FLAGS); /* Software generated IRQ */ @@ -474,11 +469,11 @@ void init_interrupts(void) for (entry = 0; entry < num_system_irqs; entry++) set_ioapic_redtbl_raw(system_irqs[entry].irq, system_irqs[entry].vector | - IOAPIC_REDTBL_DELMOD_FIXED | - IOAPIC_REDTBL_DESTMOD_PHYS | - IOAPIC_REDTBL_MASK | - system_irqs[entry].polarity | - system_irqs[entry].trigger); + IOAPIC_REDTBL_DELMOD_FIXED | + IOAPIC_REDTBL_DESTMOD_PHYS | + IOAPIC_REDTBL_MASK | + system_irqs[entry].polarity | + system_irqs[entry].trigger); set_interrupt_gate(ISH_TS_VECTOR, __switchto, IDT_DESC_FLAGS); -- cgit v1.2.1 From cf6e1dafa64680ae5d97df79d671602a82ad3b8b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:04 -0600 Subject: board/metaknight/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b2ff8101d38c42bd612a5ae233f8bc56f82e069 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728449 Reviewed-by: Jeremy Bettis --- board/metaknight/board.c | 167 ++++++++++++++++++++--------------------------- 1 file changed, 69 insertions(+), 98 deletions(-) diff --git a/board/metaknight/board.c b/board/metaknight/board.c index bfff864b89..5502d2667e 100644 --- a/board/metaknight/board.c +++ b/board/metaknight/board.c @@ -49,13 +49,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) static uint8_t new_adc_key_state; @@ -101,7 +101,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -119,7 +118,7 @@ static void sub_hdmi_hpd_interrupt(enum gpio_signal s) static void pen_input_deferred(void) { int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) && - !chipset_in_state(CHIPSET_STATE_ANY_OFF); + !chipset_in_state(CHIPSET_STATE_ANY_OFF); if (pen_charge_enable) gpio_set_level(GPIO_EN_PP3300_PEN, 1); @@ -181,26 +180,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_MEMORY] = { - .name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1 - }, - [TEMP_SENSOR_CPU] = { - .name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2 - }, + [TEMP_SENSOR_MEMORY] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_CPU] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_MEMORY \ - { \ +#define THERMAL_MEMORY \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -218,8 +213,8 @@ __maybe_unused static const struct ec_thermal_config thermal_memory = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -238,7 +233,7 @@ struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT]; static void setup_thermal(void) { thermal_params[TEMP_SENSOR_MEMORY] = thermal_memory; - thermal_params[TEMP_SENSOR_CPU] = thermal_cpu; + thermal_params[TEMP_SENSOR_CPU] = thermal_cpu; } void board_hibernate(void) @@ -274,7 +269,7 @@ static void reconfigure_5v_gpio(void) gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW); } } -DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1); #endif /* BOARD_WADDLEDOO */ static void set_5v_gpio(int level) @@ -312,7 +307,7 @@ __override void board_power_5v_enable(int enable) set_5v_gpio(!!enable); if (get_cbi_fw_config_db() == DB_1A_HDMI || - get_cbi_fw_config_db() == DB_LTE_HDMI) { + get_cbi_fw_config_db() == DB_LTE_HDMI) { gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } } @@ -333,13 +328,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -403,8 +396,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -429,29 +422,21 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_lsm6dsm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_lsm6dsm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; @@ -593,8 +578,7 @@ struct motion_sensor_t lsm6dsm_base_gyro = { .location = MOTIONSENSE_LOC_BASE, .drv = &lsm6dsm_drv, .mutex = &g_base_mutex, - .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, - MOTIONSENSE_TYPE_GYRO), + .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO), .port = I2C_PORT_SENSOR, .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, .default_range = 1000 | ROUND_UP_FLAG, /* dps */ @@ -603,7 +587,6 @@ struct motion_sensor_t lsm6dsm_base_gyro = { .max_frequency = LSM6DSM_ODR_MAX_VAL, }; - struct motion_sensor_t icm426xx_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -660,12 +643,12 @@ void board_init(void) check_c0_line(); if (get_cbi_fw_config_db() == DB_1A_HDMI || - get_cbi_fw_config_db() == DB_LTE_HDMI) { + get_cbi_fw_config_db() == DB_LTE_HDMI) { /* Disable i2c on HDMI pins */ gpio_config_pin(MODULE_I2C, GPIO_HDMI_HPD_SUB_ODL, 0); gpio_config_pin(MODULE_I2C, GPIO_GPIO92_NC, 0); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -674,8 +657,7 @@ void board_init(void) gpio_enable_interrupt(GPIO_HDMI_HPD_SUB_ODL); } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_HDMI_HPD_SUB_ODL, GPIO_INPUT); } /* Enable gpio interrupt for base accelgyro sensor */ gpio_enable_interrupt(GPIO_BASE_SIXAXIS_INT_L); @@ -693,11 +675,11 @@ void board_init(void) if (base_gyro_config == SSFC_SENSOR_LSM6DSM) { motion_sensors[BASE_ACCEL] = lsm6dsm_base_accel; - motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro; + motion_sensors[BASE_GYRO] = lsm6dsm_base_gyro; cprints(CC_SYSTEM, "SSFC: BASE GYRO is LSM6DSM"); } else if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM426XX) { motion_sensors[BASE_ACCEL] = icm426xx_base_accel; - motion_sensors[BASE_GYRO] = icm426xx_base_gyro; + motion_sensors[BASE_GYRO] = icm426xx_base_gyro; cprints(CC_SYSTEM, "SSFC: BASE GYRO is ICM426XX"); } else cprints(CC_SYSTEM, "SSFC: BASE GYRO is BMI160"); @@ -710,7 +692,6 @@ void board_init(void) /* Initial thermal */ setup_thermal(); - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -873,45 +854,35 @@ void motion_interrupt(enum gpio_signal signal) } const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, - - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, - - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, + + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, + + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif }; -- cgit v1.2.1 From afe2553c72df1b6f1eddfe381fe624dadfd0e2e8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:20 -0600 Subject: board/cappy2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9ce9ece1edc1ae7e5ce8881b026180085da783c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728133 Reviewed-by: Jeremy Bettis --- board/cappy2/board.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/cappy2/board.h b/board/cappy2/board.h index 5a2fa75bba..e0b8a80568 100644 --- a/board/cappy2/board.h +++ b/board/cappy2/board.h @@ -11,9 +11,9 @@ #define VARIANT_KEEBY_EC_NPCX797FC #include "baseboard.h" -#undef GPIO_VOLUME_UP_L -#undef GPIO_VOLUME_DOWN_L -#undef CONFIG_VOLUME_BUTTONS +#undef GPIO_VOLUME_UP_L +#undef GPIO_VOLUME_DOWN_L +#undef CONFIG_VOLUME_BUTTONS /* System unlocked in early development */ #define CONFIG_SYSTEM_UNLOCKED @@ -36,11 +36,11 @@ #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_CHARGER_PROFILE_OVERRIDE -#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE +#undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) /* Keyboard */ -#undef CONFIG_PWM_KBLIGHT +#undef CONFIG_PWM_KBLIGHT /* LED defines */ #define CONFIG_LED_COMMON @@ -50,7 +50,7 @@ #define GPIO_PWR_LED_BLUE_L GPIO_LED_B_ODL /* PWM */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is used as PWM1. */ /******************************************************************************/ @@ -81,11 +81,11 @@ #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -95,11 +95,11 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_TEMP_SENSOR_3, /* ADC6 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_TEMP_SENSOR_3, /* ADC6 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -- cgit v1.2.1 From c24ee648b91a18466e014d188f0eb27c2d3e5bb9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:56 -0600 Subject: board/waddledee/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaad41f32e2bd53ab50af3f21e27463828de6f912 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729097 Reviewed-by: Jeremy Bettis --- board/waddledee/board.h | 42 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/board/waddledee/board.h b/board/waddledee/board.h index 9cdfcc1e06..a7975e3f95 100644 --- a/board/waddledee/board.h +++ b/board/waddledee/board.h @@ -24,13 +24,14 @@ #define CONFIG_BC12_DETECT_PI3USB9201 /* Charger */ -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* * GPIO for C1 interrupts, for baseboard use @@ -47,8 +48,8 @@ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ @@ -71,8 +72,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_ANX7447 /* C1: ANX TCPC + Mux */ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 /* Thermistors */ @@ -81,10 +82,10 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ -#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ #ifndef __ASSEMBLER__ @@ -106,27 +107,18 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 392865a11032f19b3ea576ad1309de3b39225e3c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:14 -0600 Subject: include/fan.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12d50e306f264cd6e59295d8ad40190f09901fc7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730266 Reviewed-by: Jeremy Bettis --- include/fan.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/fan.h b/include/fan.h index 87c8f4b7a6..2a7791712f 100644 --- a/include/fan.h +++ b/include/fan.h @@ -17,7 +17,7 @@ enum fan_channel { #if DT_NODE_EXISTS(DT_INST(0, cros_ec_fans)) DT_FOREACH_CHILD(DT_INST(0, cros_ec_fans), NODE_ID_AND_COMMA) #endif /* cros_ec_fans */ - FAN_CH_COUNT + FAN_CH_COUNT }; BUILD_ASSERT(FAN_CH_COUNT == CONFIG_PLATFORM_EC_NUM_FANS); @@ -50,7 +50,7 @@ struct fan_t { /* Values for .flags field */ /* Enable automatic RPM control using tach input */ -#define FAN_USE_RPM_MODE BIT(0) +#define FAN_USE_RPM_MODE BIT(0) /* Require a higher duty cycle to start up than to keep running */ #define FAN_USE_FAST_START BIT(1) @@ -62,7 +62,7 @@ extern const struct fan_t fans[]; #endif /* For convenience */ -#define FAN_CH(fan) fans[fan].conf->ch +#define FAN_CH(fan) fans[fan].conf->ch /** * Set the amount of active cooling needed. The thermal control task will call @@ -84,7 +84,6 @@ void fan_set_percent_needed(int fan, int pct); */ int fan_percent_to_rpm(int fan, int pct); - /** * These functions require chip-specific implementations. */ @@ -143,4 +142,4 @@ void fan_set_count(int count); int is_thermal_control_enabled(int idx); -#endif /* __CROS_EC_FAN_H */ +#endif /* __CROS_EC_FAN_H */ -- cgit v1.2.1 From c2c39bd01cf6595ac915885bc7fa20948067f024 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:02 -0600 Subject: common/uart_buffering.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d849f3baa0dfffe1ac41477cd4d5bedff6a713d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729522 Reviewed-by: Jeremy Bettis --- common/uart_buffering.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/common/uart_buffering.c b/common/uart_buffering.c index d993eab345..7e942c7a39 100644 --- a/common/uart_buffering.c +++ b/common/uart_buffering.c @@ -22,7 +22,7 @@ /* Macros to advance in the circular buffers */ #define TX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_TX_BUF_SIZE - 1)) #define RX_BUF_NEXT(i) (((i) + 1) & (CONFIG_UART_RX_BUF_SIZE - 1)) -#define RX_BUF_PREV(i) (((i) - 1) & (CONFIG_UART_RX_BUF_SIZE - 1)) +#define RX_BUF_PREV(i) (((i)-1) & (CONFIG_UART_RX_BUF_SIZE - 1)) /* Macros to calculate difference of pointers in the circular buffers. */ #define TX_BUF_DIFF(i, j) (((i) - (j)) & (CONFIG_UART_TX_BUF_SIZE - 1)) @@ -37,12 +37,12 @@ BUILD_ASSERT((CONFIG_UART_RX_BUF_SIZE & (CONFIG_UART_RX_BUF_SIZE - 1)) == 0); * of input has been detected by the normal tick task. There will be * CONFIG_UART_RX_DMA_RECHECKS rechecks between this tick and the next tick. */ -#define RX_DMA_RECHECK_INTERVAL (HOOK_TICK_INTERVAL / \ - (CONFIG_UART_RX_DMA_RECHECKS + 1)) +#define RX_DMA_RECHECK_INTERVAL \ + (HOOK_TICK_INTERVAL / (CONFIG_UART_RX_DMA_RECHECKS + 1)) /* Transmit and receive buffers */ -static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE] - __uncached __preserved_logs(tx_buf); +static volatile char tx_buf[CONFIG_UART_TX_BUF_SIZE] __uncached + __preserved_logs(tx_buf); static volatile int tx_buf_head __preserved_logs(tx_buf_head); static volatile int tx_buf_tail __preserved_logs(tx_buf_tail); static volatile char rx_buf[CONFIG_UART_RX_BUF_SIZE] __uncached; @@ -59,7 +59,6 @@ static int uart_buffer_calc_checksum(void) return tx_buf_head ^ tx_buf_tail; } - void uart_init_buffer(void) { if (tx_checksum != uart_buffer_calc_checksum() || @@ -81,8 +80,8 @@ int uart_tx_char_raw(void *context, int c) int tx_buf_next, tx_buf_new_tail; #if defined CONFIG_POLLING_UART - (void) tx_buf_next; - (void) tx_buf_new_tail; + (void)tx_buf_next; + (void)tx_buf_new_tail; uart_write_char(c); #else @@ -137,7 +136,7 @@ void uart_process_output(void) /* If a previous DMA transfer completed, free up the buffer it used */ if (tx_dma_in_progress) { tx_buf_tail = (tx_buf_tail + tx_dma_in_progress) & - (CONFIG_UART_TX_BUF_SIZE - 1); + (CONFIG_UART_TX_BUF_SIZE - 1); tx_dma_in_progress = 0; if (IS_ENABLED(CONFIG_PRESERVE_LOGS)) @@ -154,8 +153,9 @@ void uart_process_output(void) * Get the largest contiguous block of output. If the transmit buffer * wraps, only use the part before the wrap. */ - tx_dma_in_progress = (head > tx_buf_tail ? head : - CONFIG_UART_TX_BUF_SIZE) - tx_buf_tail; + tx_dma_in_progress = + (head > tx_buf_tail ? head : CONFIG_UART_TX_BUF_SIZE) - + tx_buf_tail; uart_tx_dma_start((char *)(tx_buf + tx_buf_tail), tx_dma_in_progress); } @@ -181,7 +181,7 @@ void uart_process_output(void) #endif /* !CONFIG_UART_TX_DMA */ #ifdef CONFIG_UART_RX_DMA -#ifdef CONFIG_UART_INPUT_FILTER /* TODO(crosbug.com/p/36745): */ +#ifdef CONFIG_UART_INPUT_FILTER /* TODO(crosbug.com/p/36745): */ #error "Filtering the UART input with DMA enabled is NOT SUPPORTED!" #endif @@ -245,7 +245,7 @@ void uart_process_input(void) void uart_clear_input(void) { - int scratch __attribute__ ((unused)); + int scratch __attribute__((unused)); while (uart_rx_available()) scratch = uart_read_char(); rx_buf_head = rx_buf_tail = 0; @@ -347,9 +347,7 @@ enum ec_status uart_console_read_buffer_init(void) return EC_RES_SUCCESS; } -int uart_console_read_buffer(uint8_t type, - char *dest, - uint16_t dest_size, +int uart_console_read_buffer(uint8_t type, char *dest, uint16_t dest_size, uint16_t *write_count) { int *tail; @@ -371,7 +369,6 @@ int uart_console_read_buffer(uint8_t type, /* Copy data to response */ while (*tail != tx_snapshot_head && *write_count < dest_size - 1) { - /* * Copy only non-zero bytes, so that we don't copy unused * bytes if the buffer hasn't completely rolled at boot. -- cgit v1.2.1 From 5523d1c380ee99911171101189c9020feb5db479 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:39 -0600 Subject: chip/max32660/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icd503413047c6a3f6caba9df10136efbdc912a5b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729222 Reviewed-by: Jeremy Bettis --- chip/max32660/registers.h | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h index e444888fa0..6df9b47dd8 100644 --- a/chip/max32660/registers.h +++ b/chip/max32660/registers.h @@ -72,9 +72,8 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ #ifndef PeripheralClock -#define PeripheralClock \ - (SystemCoreClock / \ - 2) /*!< Peripheral Clock Frequency \ +#define PeripheralClock \ + (SystemCoreClock / 2) /*!< Peripheral Clock Frequency \ */ #endif @@ -173,14 +172,17 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2) -#define MXC_TMR_GET_IRQ(i) \ - (IRQn_Type)((i) == 0 ? \ - TMR0_IRQn : \ - (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0) +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + 0) #define MXC_TMR_GET_BASE(i) \ ((i) == 0 ? MXC_BASE_TMR0 : \ - (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0) + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + 0) #define MXC_TMR_GET_TMR(i) \ ((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0) -- cgit v1.2.1 From bd44490514f642cecf81c8cd5be10ffd4a70b411 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:56 -0600 Subject: chip/ish/ipc_heci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I127c82a76dfc95b08250093b3da53a4fad30eee5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729184 Reviewed-by: Jeremy Bettis --- chip/ish/ipc_heci.h | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/chip/ish/ipc_heci.h b/chip/ish/ipc_heci.h index 183e6a2c6b..23ca29f265 100644 --- a/chip/ish/ipc_heci.h +++ b/chip/ish/ipc_heci.h @@ -8,16 +8,16 @@ #define __IPC_HECI_H enum IPC_ERR { - IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, - IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1, - IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2, - IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3, - IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4, - IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5, + IPC_ERR_IPC_IS_NOT_READY = EC_ERROR_INTERNAL_FIRST + 0, + IPC_ERR_TOO_SMALL_BUFFER = EC_ERROR_INTERNAL_FIRST + 1, + IPC_ERR_TX_QUEUE_FULL = EC_ERROR_INTERNAL_FIRST + 2, + IPC_ERR_INVALID_TASK = EC_ERROR_INTERNAL_FIRST + 3, + IPC_ERR_MSG_NOT_AVAILABLE = EC_ERROR_INTERNAL_FIRST + 4, + IPC_ERR_INVALID_MSG = EC_ERROR_INTERNAL_FIRST + 5, }; enum ipc_peer_id { - IPC_PEER_ID_HOST = 0, /* x64 host */ + IPC_PEER_ID_HOST = 0, /* x64 host */ #if 0 /* other peers are not implemented yet */ IPC_PEER_ID_PMC = 1, /* Power Management Controller */ IPC_PEER_ID_CSME = 2, /* Converged Security Management Engine */ @@ -33,11 +33,11 @@ enum ipc_peer_id { BUILD_ASSERT(IPC_PEERS_COUNT <= 0x0F); enum ipc_protocol { - IPC_PROTOCOL_BOOT = 0, /* Not supported */ - IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */ - IPC_PROTOCOL_MCTP, /* not supported */ - IPC_PROTOCOL_MNG, /* Management protocol */ - IPC_PROTOCOL_ECP, /* EC Protocol. not supported */ + IPC_PROTOCOL_BOOT = 0, /* Not supported */ + IPC_PROTOCOL_HECI, /* Host Embedded Controller Interface */ + IPC_PROTOCOL_MCTP, /* not supported */ + IPC_PROTOCOL_MNG, /* Management protocol */ + IPC_PROTOCOL_ECP, /* EC Protocol. not supported */ IPC_PROTOCOL_COUNT }; /* @@ -46,10 +46,10 @@ enum ipc_protocol { */ BUILD_ASSERT(IPC_PROTOCOL_COUNT <= 0x0F); -typedef void * ipc_handle_t; +typedef void *ipc_handle_t; -#define IPC_MAX_PAYLOAD_SIZE 128 -#define IPC_INVALID_HANDLE NULL +#define IPC_MAX_PAYLOAD_SIZE 128 +#define IPC_INVALID_HANDLE NULL /* * Open ipc channel @@ -61,8 +61,7 @@ typedef void * ipc_handle_t; * @return ipc handle or IPC_INVALID_HANDLE if there's error */ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event); + const enum ipc_protocol protocol, const uint32_t event); void ipc_close(const ipc_handle_t handle); /* @@ -74,10 +73,10 @@ void ipc_close(const ipc_handle_t handle); * if > 0, wait for the specified microsecond duration time */ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, - int timeout_us); + int timeout_us); /* Write message to ipc channel. */ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, - const size_t buf_size, uint32_t *timestamp); + const size_t buf_size, uint32_t *timestamp); #endif /* __IPC_HECI_H */ -- cgit v1.2.1 From 1a1174f8bfce13f542b5e5aa0eb985e66dbbedac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:54 -0600 Subject: board/hatch/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic69580d27412d8b308d1576931cd43512419f49a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728298 Reviewed-by: Jeremy Bettis --- board/hatch/led.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/board/hatch/led.c b/board/hatch/led.c index d03aed0585..a355df8cf5 100644 --- a/board/hatch/led.c +++ b/board/hatch/led.c @@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 6eb970194af281f15a01d7d0e9267229a7918ec4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:58 -0600 Subject: zephyr/test/drivers/src/thermistor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I907d6056020b76ed9a0fbfe1e7040d7d856ec9bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730979 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/thermistor.c | 61 +++++++++++++++++------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/zephyr/test/drivers/src/thermistor.c b/zephyr/test/drivers/src/thermistor.c index e760e0cf33..5a29ac7e89 100644 --- a/zephyr/test/drivers/src/thermistor.c +++ b/zephyr/test/drivers/src/thermistor.c @@ -16,11 +16,10 @@ #include "temp_sensor/temp_sensor.h" #include "test/drivers/test_state.h" - #define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok) #define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios) -#define ADC_DEVICE_NODE DT_NODELABEL(adc0) +#define ADC_DEVICE_NODE DT_NODELABEL(adc0) /* TODO replace counting macros with DT macro when * https://github.com/zephyrproject-rtos/zephyr/issues/38715 lands @@ -33,7 +32,7 @@ DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor, _ACCUMULATOR) 0 /* Conversion of temperature doesn't need to be 100% accurate */ -#define TEMP_EPS 2 +#define TEMP_EPS 2 #define A_VALID_VOLTAGE 1000 /** @@ -57,9 +56,8 @@ ZTEST_USER(thermistor, test_thermistor_power_pin) sensor_idx++) { const struct temp_sensor_t *sensor = &temp_sensors[sensor_idx]; - zassert_ok(adc_emul_const_value_set(adc_dev, - sensor->idx, - A_VALID_VOLTAGE), + zassert_ok(adc_emul_const_value_set(adc_dev, sensor->idx, + A_VALID_VOLTAGE), "adc_emul_value_func_set() failed on %s", sensor->name); } @@ -135,26 +133,26 @@ static int resistance_47kohm_B4050(int t) /* Thermistor manufacturer resistance lookup table*/ int r_table[] = { 155700, 147900, 140600, 133700, 127200, /* 0*C - 4*C */ - 121000, 115100, 109600, 104300, 99310, /* 5*C - 9*C */ - 94600, 90130, 85890, 81870, 78070, /* 10*C - 14*C */ - 74450, 71020, 67770, 64680, 61750, /* 15*C - 19*C */ - 58970, 56320, 53810, 51430, 49160, /* 20*C - 24*C */ - 47000, 44950, 42990, 41130, 39360, /* 25*C - 29*C */ - 37680, 36070, 34540, 33080, 31690, /* 30*C - 34*C */ - 30360, 29100, 27900, 26750, 25650, /* 35*C - 39*C */ - 24610, 23610, 22660, 21750, 20880, /* 40*C - 44*C */ - 20050, 19260, 18500, 17780, 17090, /* 45*C - 49*C */ - 16430, 15800, 15200, 14620, 14070, /* 50*C - 54*C */ - 13540, 13030, 12550, 12090, 11640, /* 55*C - 59*C */ - 11210, 10800, 10410, 10040, 9676, /* 60*C - 64*C */ - 9331, 8999, 8680, 8374, 8081, /* 65*C - 69*C */ - 7799, 7528, 7268, 7018, 6777, /* 70*C - 74*C */ - 6546, 6324, 6111, 5906, 5708, /* 75*C - 79*C */ - 5518, 5335, 5160, 4990, 4827, /* 80*C - 84*C */ - 4671, 4519, 4374, 4233, 4098, /* 85*C - 89*C */ - 3968, 3842, 3721, 3605, 3492, /* 90*C - 94*C */ - 3384, 3279, 3179, 3082, 2988, /* 95*C - 99*C */ - 2898 /* 100*C */ + 121000, 115100, 109600, 104300, 99310, /* 5*C - 9*C */ + 94600, 90130, 85890, 81870, 78070, /* 10*C - 14*C */ + 74450, 71020, 67770, 64680, 61750, /* 15*C - 19*C */ + 58970, 56320, 53810, 51430, 49160, /* 20*C - 24*C */ + 47000, 44950, 42990, 41130, 39360, /* 25*C - 29*C */ + 37680, 36070, 34540, 33080, 31690, /* 30*C - 34*C */ + 30360, 29100, 27900, 26750, 25650, /* 35*C - 39*C */ + 24610, 23610, 22660, 21750, 20880, /* 40*C - 44*C */ + 20050, 19260, 18500, 17780, 17090, /* 45*C - 49*C */ + 16430, 15800, 15200, 14620, 14070, /* 50*C - 54*C */ + 13540, 13030, 12550, 12090, 11640, /* 55*C - 59*C */ + 11210, 10800, 10410, 10040, 9676, /* 60*C - 64*C */ + 9331, 8999, 8680, 8374, 8081, /* 65*C - 69*C */ + 7799, 7528, 7268, 7018, 6777, /* 70*C - 74*C */ + 6546, 6324, 6111, 5906, 5708, /* 75*C - 79*C */ + 5518, 5335, 5160, 4990, 4827, /* 80*C - 84*C */ + 4671, 4519, 4374, 4233, 4098, /* 85*C - 89*C */ + 3968, 3842, 3721, 3605, 3492, /* 90*C - 94*C */ + 3384, 3279, 3179, 3082, 2988, /* 95*C - 99*C */ + 2898 /* 100*C */ }; t -= 273; @@ -188,8 +186,7 @@ static int adc_temperature_func(const struct device *dev, unsigned int channel, { struct thermistor_state *s = (struct thermistor_state *)param; - *result = volt_divider(s->v, - s->r, + *result = volt_divider(s->v, s->r, resistance_47kohm_B4050(s->temp_expected)); return 0; @@ -211,8 +208,7 @@ static void do_thermistor_test(const struct temp_sensor_t *temp_sensor, zassert_not_null(adc_dev, "Cannot get ADC device"); /* Setup ADC channel */ - zassert_ok(adc_emul_value_func_set(adc_dev, - temp_sensor->idx, + zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensor->idx, adc_temperature_func, &state), "adc_emul_value_func_set() failed on %s", temp_sensor->name); @@ -225,8 +221,9 @@ static void do_thermistor_test(const struct temp_sensor_t *temp_sensor, for (temp_expected = 273; temp_expected <= 373; temp_expected++) { state.temp_expected = temp_expected; zassert_equal(EC_SUCCESS, - temp_sensor->zephyr_info->read(temp_sensor, &temp), - "failed on %s", temp_sensor->name); + temp_sensor->zephyr_info->read(temp_sensor, + &temp), + "failed on %s", temp_sensor->name); zassert_within(temp_expected, temp, TEMP_EPS, "Expected %d*K, got %d*K on %s", temp_expected, temp, temp_sensor->name); -- cgit v1.2.1 From 869a7ca28977d7a9ce43e19a741c5c11fdff9817 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:38 -0600 Subject: include/driver/tcpm/ps8xxx_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87b00943fff70418f99bf0e0c29cfdff8d164b33 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730252 Reviewed-by: Jeremy Bettis --- include/driver/tcpm/ps8xxx_public.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h index ad84f93ced..0c0e7951c5 100644 --- a/include/driver/tcpm/ps8xxx_public.h +++ b/include/driver/tcpm/ps8xxx_public.h @@ -15,12 +15,12 @@ struct usb_mux; /* I2C interface */ #define PS8XXX_I2C_ADDR1_P1_FLAGS 0x09 #define PS8XXX_I2C_ADDR1_P2_FLAGS 0x0A -#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ -#define PS8XXX_I2C_ADDR2_FLAGS 0x1B -#define PS8XXX_I2C_ADDR3_FLAGS 0x2B -#define PS8XXX_I2C_ADDR4_FLAGS 0x4B +#define PS8XXX_I2C_ADDR1_FLAGS 0x0B /* P3 */ +#define PS8XXX_I2C_ADDR2_FLAGS 0x1B +#define PS8XXX_I2C_ADDR3_FLAGS 0x2B +#define PS8XXX_I2C_ADDR4_FLAGS 0x4B -#define PS8XXX_VENDOR_ID 0x1DA0 +#define PS8XXX_VENDOR_ID 0x1DA0 /* Minimum Delay for reset assertion */ #define PS8XXX_RESET_DELAY_MS 1 @@ -75,12 +75,10 @@ extern const struct tcpm_drv ps8xxx_tcpm_drv; * * @param port TCPC port number. */ -__override_proto -uint16_t board_get_ps8xxx_product_id(int port); +__override_proto uint16_t board_get_ps8xxx_product_id(int port); void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC extern struct i2c_stress_test_dev ps8xxx_i2c_stress_test_dev; -- cgit v1.2.1 From 294cf086e05a036935df56f7dfd9dd0ac901ee16 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:47 -0600 Subject: board/anahera/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ebf70638f4758633e6bdc0bac2782a18e789b95 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727990 Reviewed-by: Jeremy Bettis --- board/anahera/usbc_config.c | 58 ++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/board/anahera/usbc_config.c b/board/anahera/usbc_config.c index 52b6b498f0..7248cda081 100644 --- a/board/anahera/usbc_config.c +++ b/board/anahera/usbc_config.c @@ -32,8 +32,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -321,33 +321,33 @@ const static struct ps8811_reg_val equalizer_wwan_table[] = { { /* Set channel A EQ setting */ .reg = PS8811_REG1_USB_AEQ_LEVEL, - .val = (PS8811_AEQ_I2C_LEVEL_UP_13DB << - PS8811_AEQ_I2C_LEVEL_UP_SHIFT) | - (PS8811_AEQ_PIN_LEVEL_UP_18DB << - PS8811_AEQ_PIN_LEVEL_UP_SHIFT), + .val = (PS8811_AEQ_I2C_LEVEL_UP_13DB + << PS8811_AEQ_I2C_LEVEL_UP_SHIFT) | + (PS8811_AEQ_PIN_LEVEL_UP_18DB + << PS8811_AEQ_PIN_LEVEL_UP_SHIFT), }, { /* Set ADE pin setting */ .reg = PS8811_REG1_USB_ADE_CONFIG, - .val = (PS8811_ADE_PIN_MID_LEVEL_3DB << - PS8811_ADE_PIN_MID_LEVEL_SHIFT) | - PS8811_AEQ_CONFIG_REG_ENABLE | - PS8811_AEQ_ADAPTIVE_REG_ENABLE, + .val = (PS8811_ADE_PIN_MID_LEVEL_3DB + << PS8811_ADE_PIN_MID_LEVEL_SHIFT) | + PS8811_AEQ_CONFIG_REG_ENABLE | + PS8811_AEQ_ADAPTIVE_REG_ENABLE, }, { /* Set channel B EQ setting */ .reg = PS8811_REG1_USB_BEQ_LEVEL, - .val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB << - PS8811_BEQ_I2C_LEVEL_UP_SHIFT) | - (PS8811_BEQ_PIN_LEVEL_UP_18DB << - PS8811_BEQ_PIN_LEVEL_UP_SHIFT), + .val = (PS8811_BEQ_I2C_LEVEL_UP_10P5DB + << PS8811_BEQ_I2C_LEVEL_UP_SHIFT) | + (PS8811_BEQ_PIN_LEVEL_UP_18DB + << PS8811_BEQ_PIN_LEVEL_UP_SHIFT), }, { /* Set BDE pin setting */ .reg = PS8811_REG1_USB_BDE_CONFIG, - .val = (PS8811_BDE_PIN_MID_LEVEL_3DB << - PS8811_BDE_PIN_MID_LEVEL_SHIFT) | - PS8811_BEQ_CONFIG_REG_ENABLE, + .val = (PS8811_BDE_PIN_MID_LEVEL_3DB + << PS8811_BDE_PIN_MID_LEVEL_SHIFT) | + PS8811_BEQ_CONFIG_REG_ENABLE, }, }; @@ -357,8 +357,8 @@ const static struct ps8811_reg_val equalizer_wlan_table[] = { { /* Set 50ohm adjust for B channel */ .reg = PS8811_REG1_50OHM_ADJUST_CHAN_B, - .val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT << - PS8811_50OHM_ADJUST_CHAN_B_SHIFT), + .val = (PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT + << PS8811_50OHM_ADJUST_CHAN_B_SHIFT), }, }; @@ -371,16 +371,16 @@ static int usba_retimer_init(int port) int i; const struct usb_mux *me = &usba_ps8811[port]; - rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); + rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL, + &val); switch (port) { case USBA_PORT_A0: /* Set channel A output swing */ - rv = ps8811_i2c_field_update( - me, PS8811_REG_PAGE1, PS8811_REG1_USB_CHAN_A_SWING, - PS8811_CHAN_A_SWING_MASK, - 0x2 << PS8811_CHAN_A_SWING_SHIFT); + rv = ps8811_i2c_field_update(me, PS8811_REG_PAGE1, + PS8811_REG1_USB_CHAN_A_SWING, + PS8811_CHAN_A_SWING_MASK, + 0x2 << PS8811_CHAN_A_SWING_SHIFT); break; case USBA_PORT_A1: if (ec_cfg_has_lte()) { @@ -403,9 +403,9 @@ static int usba_retimer_init(int port) PS8811_REG1_USB_CHAN_B_DE_PS_MSB, PS8811_CHAN_B_DE_PS_MSB_MASK, 0x16); - for (i = 0; i < NUM_EQ_WWAN_ARRAY; i++) - rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1, + rv |= ps8811_i2c_write( + me, PS8811_REG_PAGE1, equalizer_wwan_table[i].reg, equalizer_wwan_table[i].val); } else { @@ -416,9 +416,9 @@ static int usba_retimer_init(int port) PS8811_CHAN_A_SWING_MASK, 0x2 << PS8811_CHAN_A_SWING_SHIFT); - for (i = 0; i < NUM_EQ_WLAN_ARRAY; i++) - rv |= ps8811_i2c_write(me, PS8811_REG_PAGE1, + rv |= ps8811_i2c_write( + me, PS8811_REG_PAGE1, equalizer_wlan_table[i].reg, equalizer_wlan_table[i].val); } -- cgit v1.2.1 From cf1bfcd64660538c8d11f9f765fc109d744bcfe5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:42 -0600 Subject: zephyr/projects/corsola/src/krabby/hooks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I875634b122364be6ad3c57e945ac4cd0a897e29f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730742 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/krabby/hooks.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/hooks.c b/zephyr/projects/corsola/src/krabby/hooks.c index 9fae7c8bb5..6f0a192e85 100644 --- a/zephyr/projects/corsola/src/krabby/hooks.c +++ b/zephyr/projects/corsola/src/krabby/hooks.c @@ -15,15 +15,16 @@ static void board_i2c3_ctrl(bool enable) { - if (DEVICE_DT_GET(DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), - scl_gpios, 0)) == DEVICE_DT_GET(DT_NODELABEL(gpiof))) { + if (DEVICE_DT_GET( + DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) == + DEVICE_DT_GET(DT_NODELABEL(gpiof))) { /* * TODO(b/226296649): * Use pinctrl APIs to enable/disable an interface. */ struct gctrl_it8xxx2_regs *const gctrl_base = - (struct gctrl_it8xxx2_regs *) - DT_REG_ADDR(DT_NODELABEL(gctrl)); + (struct gctrl_it8xxx2_regs *)DT_REG_ADDR( + DT_NODELABEL(gctrl)); if (enable) { gctrl_base->GCTRL_PMER3 |= IT8XXX2_GCTRL_SMB3PSEL; -- cgit v1.2.1 From 726865bd036d235bbc35ad45872878c762d2b7cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:10 -0600 Subject: include/usb_hid.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92dd3e5666f0e951cb50a931a58fa3922eb07290 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730434 Reviewed-by: Jeremy Bettis --- include/usb_hid.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/include/usb_hid.h b/include/usb_hid.h index e7b1cfe74b..6432b8ba05 100644 --- a/include/usb_hid.h +++ b/include/usb_hid.h @@ -8,39 +8,39 @@ #ifndef __CROS_EC_USB_HID_H #define __CROS_EC_USB_HID_H -#define USB_HID_SUBCLASS_BOOT 1 +#define USB_HID_SUBCLASS_BOOT 1 #define USB_HID_PROTOCOL_KEYBOARD 1 -#define USB_HID_PROTOCOL_MOUSE 2 +#define USB_HID_PROTOCOL_MOUSE 2 /* USB HID Class requests */ -#define USB_HID_REQ_GET_REPORT 0x01 -#define USB_HID_REQ_GET_IDLE 0x02 -#define USB_HID_REQ_GET_PROTOCOL 0x03 -#define USB_HID_REQ_SET_REPORT 0x09 -#define USB_HID_REQ_SET_IDLE 0x0A -#define USB_HID_REQ_SET_PROTOCOL 0x0B +#define USB_HID_REQ_GET_REPORT 0x01 +#define USB_HID_REQ_GET_IDLE 0x02 +#define USB_HID_REQ_GET_PROTOCOL 0x03 +#define USB_HID_REQ_SET_REPORT 0x09 +#define USB_HID_REQ_SET_IDLE 0x0A +#define USB_HID_REQ_SET_PROTOCOL 0x0B /* USB HID class descriptor types */ -#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01) -#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02) -#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) +#define USB_HID_DT_HID (USB_TYPE_CLASS | 0x01) +#define USB_HID_DT_REPORT (USB_TYPE_CLASS | 0x02) +#define USB_HID_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) /* Pre-defined report types */ -#define REPORT_TYPE_INPUT 0x01 -#define REPORT_TYPE_OUTPUT 0x02 -#define REPORT_TYPE_FEATURE 0x03 +#define REPORT_TYPE_INPUT 0x01 +#define REPORT_TYPE_OUTPUT 0x02 +#define REPORT_TYPE_FEATURE 0x03 struct usb_hid_class_descriptor { - uint8_t bDescriptorType; + uint8_t bDescriptorType; uint16_t wDescriptorLength; } __packed; struct usb_hid_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t bcdHID; - uint8_t bCountryCode; - uint8_t bNumDescriptors; + uint8_t bCountryCode; + uint8_t bNumDescriptors; struct usb_hid_class_descriptor desc[1]; } __packed; -- cgit v1.2.1 From 0b7526c4a6d80b1cbd9861d546b64801aa649cb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:10 -0600 Subject: baseboard/kukui/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24377da23425dc6e6c85ca73e77159e4a45e0f0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727924 Reviewed-by: Jeremy Bettis --- baseboard/kukui/usb_pd_policy.c | 48 +++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/baseboard/kukui/usb_pd_policy.c b/baseboard/kukui/usb_pd_policy.c index 28ef005ee8..c0fe554366 100644 --- a/baseboard/kukui/usb_pd_policy.c +++ b/baseboard/kukui/usb_pd_policy.c @@ -16,8 +16,8 @@ #include "usb_pd_policy.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static int board_get_polarity(int port) { @@ -30,8 +30,8 @@ static int board_get_polarity(int port) static uint8_t vbus_en; -#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */ -#define VBUS_EN_HOOK_VERSION 1 +#define VBUS_EN_SYSJUMP_TAG 0x5645 /* VE */ +#define VBUS_EN_HOOK_VERSION 1 static void vbus_en_preserve_state(void) { @@ -45,11 +45,11 @@ static void vbus_en_restore_state(void) const uint8_t *prev_vbus_en; int size, version; - prev_vbus_en = (const uint8_t *)system_get_jump_tag( - VBUS_EN_SYSJUMP_TAG, &version, &size); + prev_vbus_en = (const uint8_t *)system_get_jump_tag(VBUS_EN_SYSJUMP_TAG, + &version, &size); if (prev_vbus_en && version == VBUS_EN_HOOK_VERSION && - size == sizeof(*prev_vbus_en)) { + size == sizeof(*prev_vbus_en)) { memcpy(&vbus_en, prev_vbus_en, sizeof(vbus_en)); } } @@ -89,7 +89,8 @@ int pd_set_power_supply_ready(int port) gpio_set_level(GPIO_EN_USBC_CHARGE_L, 1); gpio_set_level(GPIO_EN_PP5000_USBC, 1); - if (IS_ENABLED(CONFIG_CHARGER_OTG) && IS_ENABLED(CONFIG_CHARGER_ISL9238C)) + if (IS_ENABLED(CONFIG_CHARGER_OTG) && + IS_ENABLED(CONFIG_CHARGER_ISL9238C)) charger_set_current(CHARGER_SOLO, 0); /* notify host of power info change */ @@ -142,7 +143,7 @@ __overridable int board_has_virtual_mux(void) } static void board_usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_mode, int polarity) + enum usb_switch usb_mode, int polarity) { usb_mux_set(port, mux_mode, usb_mode, polarity); @@ -163,8 +164,9 @@ __override void svdm_safe_dp_mode(int port) __override int svdm_enter_dp_mode(int port, uint32_t mode_caps) { /* Kukui/Krane doesn't support superspeed lanes. */ - const uint32_t support_pin_mode = board_has_virtual_mux() ? - (MODE_DP_PIN_C | MODE_DP_PIN_E) : MODE_DP_PIN_ALL; + const uint32_t support_pin_mode = + board_has_virtual_mux() ? (MODE_DP_PIN_C | MODE_DP_PIN_E) : + MODE_DP_PIN_ALL; /** * Only enter mode if device is DFP_D (and PIN_C/E for Kukui/Krane) @@ -205,11 +207,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) port, mf_pref ? USB_PD_MUX_DOCK : USB_PD_MUX_DP_ENABLED, USB_SWITCH_CONNECT, board_get_polarity(port)); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -227,8 +229,8 @@ __override void svdm_dp_post_config(int port) /* set the minimum time delay (2ms) for the next HPD IRQ */ svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, + USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED); } __override int svdm_dp_attention(int port, uint32_t *payload) @@ -267,8 +269,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) #endif /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; /* nak */ @@ -278,8 +280,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) board_set_dp_mux_control(lvl, board_get_polarity(port)); #endif /* set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } /* ack */ @@ -293,6 +295,6 @@ __override void svdm_exit_dp_mode(int port) board_set_dp_mux_control(0, 0); #endif usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ -- cgit v1.2.1 From feaceec6dc6e26f74acbdd30bb891a14b31a0fef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:15 -0600 Subject: baseboard/guybrush/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fda3e219793a4a19f59925c9f2667a82bb7d7d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727520 Reviewed-by: Jeremy Bettis --- baseboard/guybrush/cbi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c index 6d66b826dc..3036fb71d3 100644 --- a/baseboard/guybrush/cbi.c +++ b/baseboard/guybrush/cbi.c @@ -50,10 +50,9 @@ uint32_t get_fw_config(void) return UNINITIALIZED_FW_CONFIG; fw_config = val; } - return fw_config; + return fw_config; } - int get_fw_config_field(uint8_t offset, uint8_t width) { uint32_t fw_config = get_fw_config(); @@ -64,7 +63,6 @@ int get_fw_config_field(uint8_t offset, uint8_t width) return (fw_config >> offset) & ((1 << width) - 1); } - __overridable void board_cbi_init(void) { } -- cgit v1.2.1 From b493e0bc6686ad2ad1b1a8cd28e0f7f27fa6fad6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:13 -0600 Subject: common/btle_hci_controller.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40fd17641549886e985a24f7a79dd70c009893f6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729610 Reviewed-by: Jeremy Bettis --- common/btle_hci_controller.c | 308 +++++++++++++++++++------------------------ 1 file changed, 136 insertions(+), 172 deletions(-) diff --git a/common/btle_hci_controller.c b/common/btle_hci_controller.c index cc5b872b19..806eb7a2fa 100644 --- a/common/btle_hci_controller.c +++ b/common/btle_hci_controller.c @@ -11,8 +11,8 @@ #ifdef CONFIG_BLUETOOTH_HCI_DEBUG #define CPUTS(outstr) cputs(CC_BLUETOOTH_HCI, outstr) -#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_HCI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_HCI, format, ##args) #else /* CONFIG_BLUETOOTH_HCI_DEBUG */ @@ -27,7 +27,7 @@ static uint64_t hci_le_event_mask; #define MAX_MESSAGE 24 -#define STATUS (return_params[0]) +#define STATUS (return_params[0]) #define RPARAMS (&(return_params[1])) void hci_cmd(uint8_t *hciCmdbuf) @@ -56,215 +56,184 @@ void hci_cmd(uint8_t *hciCmdbuf) } switch (hdr->opcode) { - case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, - HCI_CMD_Reset): + case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, HCI_CMD_Reset): STATUS = ll_reset(); - break; + break; case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, - HCI_CMD_Set_Event_Mask): + HCI_CMD_Set_Event_Mask): if (hdr->paramLen != sizeof(hci_event_mask)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = HCI_SUCCESS; memcpy(&hci_event_mask, params, sizeof(hci_event_mask)); - break; + break; case CMD_MAKE_OPCODE(HCI_OGF_Controller_and_Baseband, - HCI_CMD_Read_Transmit_Power_Level): - case CMD_MAKE_OPCODE(HCI_OGF_Informational, - HCI_CMD_Read_Local_Supported_Features): + HCI_CMD_Read_Transmit_Power_Level): case CMD_MAKE_OPCODE(HCI_OGF_Informational, - HCI_CMD_Read_Local_Supported_Commands): + HCI_CMD_Read_Local_Supported_Features): case CMD_MAKE_OPCODE(HCI_OGF_Informational, - HCI_CMD_Read_Local_Version_Information): + HCI_CMD_Read_Local_Supported_Commands): case CMD_MAKE_OPCODE(HCI_OGF_Informational, - HCI_CMD_Read_BD_ADDR): + HCI_CMD_Read_Local_Version_Information): + case CMD_MAKE_OPCODE(HCI_OGF_Informational, HCI_CMD_Read_BD_ADDR): case CMD_MAKE_OPCODE(HCI_OGF_Link_Control, - HCI_CMD_Read_Remote_Version_Information): - case CMD_MAKE_OPCODE(HCI_OGF_Status, - HCI_CMD_Read_RSSI): + HCI_CMD_Read_Remote_Version_Information): + case CMD_MAKE_OPCODE(HCI_OGF_Status, HCI_CMD_Read_RSSI): event = 0; - break; + break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Event_Mask): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Event_Mask): if (hdr->paramLen != sizeof(hci_le_event_mask)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = HCI_SUCCESS; memcpy(&hci_le_event_mask, params, sizeof(hci_le_event_mask)); - break; + break; /* LE Information */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Buffer_Size): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Buffer_Size): if (hdr->paramLen != 0) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_read_buffer_size(RPARAMS); rparam_count = sizeof(struct hciCmplLeReadBufferSize); - break; + break; case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Local_Supported_Features): + HCI_CMD_LE_Read_Local_Supported_Features): if (hdr->paramLen != 0) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_read_local_supported_features(RPARAMS); rparam_count = sizeof(struct hciCmplLeReadLocalSupportedFeatures); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Supported_States): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Supported_States): if (hdr->paramLen != 0) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_read_supported_states(RPARAMS); rparam_count = sizeof(struct hciCmplLeReadSupportedStates); - break; + break; case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Host_Channel_Classification): + HCI_CMD_LE_Set_Host_Channel_Classification): if (hdr->paramLen != sizeof(struct hciLeSetHostChannelClassification)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_set_host_channel_classification(params); - break; + break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Random_Address): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Random_Address): if (hdr->paramLen != sizeof(struct hciLeSetRandomAddress)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_set_random_address(params); - break; + break; /* Advertising */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Advertise_Enable): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable): STATUS = ll_set_advertising_enable(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Advertising_Data): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data): STATUS = ll_set_adv_data(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Adv_Params): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Adv_Params): if (hdr->paramLen != sizeof(struct hciLeSetAdvParams)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_set_advertising_params(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Adv_Channel_TX_Power): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Adv_Channel_TX_Power): STATUS = ll_read_tx_power(); rparam_count = sizeof(struct hciCmplLeReadAdvChannelTxPower); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Scan_Response_Data): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data): STATUS = ll_set_scan_response_data(params); - break; + break; /* Connections */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Remote_Used_Features): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Remote_Used_Features): if (hdr->paramLen != sizeof(struct hciLeReadRemoteUsedFeatures)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_read_remote_used_features(params); event = HCI_EVT_Command_Status; - break; - case CMD_MAKE_OPCODE(HCI_OGF_Link_Control, - HCI_CMD_Disconnect): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Connection_Update): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Create_Connection): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Create_Connection_Cancel): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Channel_Map): + break; + case CMD_MAKE_OPCODE(HCI_OGF_Link_Control, HCI_CMD_Disconnect): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Connection_Update): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Create_Connection_Cancel): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Channel_Map): event = 0; - break; + break; /* Encryption */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Encrypt): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_LTK_Request_Reply): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_LTK_Request_Negative_Reply): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Rand): - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Start_Encryption): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Encrypt): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Reply): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_LTK_Request_Negative_Reply): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Rand): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Start_Encryption): event = 0; - break; + break; /* Scanning */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Scan_Enable): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Enable): if (hdr->paramLen != sizeof(struct hciLeSetScanEnable)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_set_scan_enable(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Scan_Parameters): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Parameters): if (hdr->paramLen != sizeof(struct hciLeSetScanParams)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_set_scan_params(params); - break; + break; /* Allow List */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Clear_Allow_List): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Clear_Allow_List): if (hdr->paramLen != 0) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_clear_allow_list(); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Read_Allow_List_Size): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Read_Allow_List_Size): if (hdr->paramLen != 0) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_read_allow_list_size(RPARAMS); rparam_count = sizeof(struct hciCmplLeReadAllowListSize); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Add_Device_To_Allow_List): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Add_Device_To_Allow_List): if (hdr->paramLen != sizeof(struct hciLeAddDeviceToAllowList)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_add_device_to_allow_list(params); - break; + break; case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Remove_Device_From_Allow_List): + HCI_CMD_LE_Remove_Device_From_Allow_List): if (hdr->paramLen != - sizeof(struct hciLeRemoveDeviceFromAllowList)) + sizeof(struct hciLeRemoveDeviceFromAllowList)) STATUS = HCI_ERR_Invalid_HCI_Command_Parameters; else STATUS = ll_remove_device_from_allow_list(params); - break; + break; /* RFPHY Testing Support */ - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Receiver_Test): + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Receiver_Test): STATUS = ll_receiver_test(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Transmitter_Test): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Transmitter_Test): STATUS = ll_transmitter_test(params); - break; - case CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Test_End): + break; + case CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Test_End): STATUS = ll_test_end(RPARAMS); rparam_count = sizeof(struct hciCmplLeTestEnd); - break; + break; default: STATUS = HCI_ERR_Unknown_HCI_Command; - break; + break; } hci_event(event, rparam_count, return_params); @@ -275,12 +244,11 @@ void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len) int i; /* Enqueue hdr, len, len bytes of data */ - CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n", - len, hdr & ACL_HDR_MASK_CONN_ID, - hdr & ACL_HDR_MASK_PB); - for (i = 0; i < len; i++) - CPRINTF("0x%x, ", data[i]); - CPRINTF("\n"); + CPRINTF("Sending %d bytes of data from handle %d with PB=%x.\n", len, + hdr & ACL_HDR_MASK_CONN_ID, hdr & ACL_HDR_MASK_PB); + for (i = 0; i < len; i++) + CPRINTF("0x%x, ", data[i]); + CPRINTF("\n"); } void hci_acl_from_host(uint8_t *hciAclbuf) @@ -290,12 +258,11 @@ void hci_acl_from_host(uint8_t *hciAclbuf) int i; /* Send the data to the link layer */ - CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n", - hdr->len, hdr->hdr & ACL_HDR_MASK_CONN_ID, - hdr->hdr & ACL_HDR_MASK_PB); - for (i = 0; i < hdr->len; i++) - CPRINTF("0x%x, ", data[i]); - CPRINTF("\n"); + CPRINTF("Sending %d bytes of data to handle %d with PB=%x.\n", hdr->len, + hdr->hdr & ACL_HDR_MASK_CONN_ID, hdr->hdr & ACL_HDR_MASK_PB); + for (i = 0; i < hdr->len; i++) + CPRINTF("0x%x, ", data[i]); + CPRINTF("\n"); } /* @@ -335,52 +302,50 @@ void hci_event(uint8_t event_code, uint8_t len, uint8_t *params) * hcitool lcmd 0x2008 18 0x42410906 0x03454443 0x203c119 0x3030501 0x1812 * hcitool cmd 8 8 6 9 41 42 43 44 45 3 19 c1 3 2 1 5 3 3 12 18 */ -uint8_t adv0[19] = {0x07, 0x09, 'A', 'B', 'C', 'D', 'E', 'F', /* Name */ - 0x03, 0x19, 0xc1, 0x03, /* Keyboard */ - 0x02, 0x01, 0x05, /* Flags */ - 0x03, 0x03, 0x12, 0x18}; /* UUID */ +uint8_t adv0[19] = { 0x07, 0x09, 'A', 'B', 'C', 'D', 'E', 'F', /* Name */ + 0x03, 0x19, 0xc1, 0x03, /* Keyboard */ + 0x02, 0x01, 0x05, /* Flags */ + 0x03, 0x03, 0x12, 0x18 }; /* UUID */ -uint8_t adv1[18] = {0x06, 0x09, 'A', 'B', 'C', 'D', 'E', /* Name */ - 0x02, 0x01, 0x05, /* Flags */ - 0x03, 0x19, 0xc1, 0x03, /* Keyboard */ - 0x03, 0x03, 0x12, 0x18}; /* UUID */ +uint8_t adv1[18] = { 0x06, 0x09, 'A', 'B', 'C', 'D', 'E', /* Name */ + 0x02, 0x01, 0x05, /* Flags */ + 0x03, 0x19, 0xc1, 0x03, /* Keyboard */ + 0x03, 0x03, 0x12, 0x18 }; /* UUID */ -uint8_t *adverts[] = {adv0, adv1}; -uint8_t adv_lengths[] = {sizeof(adv0), sizeof(adv1)}; +uint8_t *adverts[] = { adv0, adv1 }; +uint8_t adv_lengths[] = { sizeof(adv0), sizeof(adv1) }; -uint8_t scan0[4] = {0x03, 0x08, 'A', 'B'}; /* Short Name */ +uint8_t scan0[4] = { 0x03, 0x08, 'A', 'B' }; /* Short Name */ -uint8_t scan1[] = {}; /* Empty */ +uint8_t scan1[] = {}; /* Empty */ -uint8_t *scans[] = {scan0, scan1}; -uint8_t scan_lengths[] = {sizeof(scan0), sizeof(scan1)}; +uint8_t *scans[] = { scan0, scan1 }; +uint8_t scan_lengths[] = { sizeof(scan0), sizeof(scan1) }; /* * LE_Set_Adv_Params * hcitool lcmd 0x2006 15 0x010000f0 0xb0010100 0xb4b3b2b1 0x0007c5 * hcitool cmd 8 6 f0 0 0 1 0 1 1 b0 b1 b2 b3 b4 c5 7 0 */ -uint8_t adv_param0[15] = { - 0xf0, 0x00, /* IntervalMin */ - 0x00, 0x01, /* IntervalMax */ - 0x00, /* Adv Type */ - 0x01, /* Use Random Addr */ - 0x01, /* Direct Random */ - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */ - 0x07, /* Channel Map */ - 0x00}; /* Filter Policy */ - -uint8_t adv_param1[15] = { - 0xf0, 0x00, /* IntervalMin */ - 0x00, 0x01, /* IntervalMax */ - 0x02, /* Adv Type */ - 0x01, /* Use Random Addr */ - 0x01, /* Direct Random */ - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */ - 0x07, /* Channel Map */ - 0x00}; /* Filter Policy */ - -uint8_t *adv_params[] = {adv_param0, adv_param1}; +uint8_t adv_param0[15] = { 0xf0, 0x00, /* IntervalMin */ + 0x00, 0x01, /* IntervalMax */ + 0x00, /* Adv Type */ + 0x01, /* Use Random Addr */ + 0x01, /* Direct Random */ + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */ + 0x07, /* Channel Map */ + 0x00 }; /* Filter Policy */ + +uint8_t adv_param1[15] = { 0xf0, 0x00, /* IntervalMin */ + 0x00, 0x01, /* IntervalMax */ + 0x02, /* Adv Type */ + 0x01, /* Use Random Addr */ + 0x01, /* Direct Random */ + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xc5, /* Direct Addr */ + 0x07, /* Channel Map */ + 0x00 }; /* Filter Policy */ + +uint8_t *adv_params[] = { adv_param0, adv_param1 }; /* * LE Information @@ -489,7 +454,7 @@ static int command_ble_hci_cmd(int argc, char **argv) } for (i = 3; i < argc; i++) { - param[i-3] = strtoi(argv[i], &e, 0); + param[i - 3] = strtoi(argv[i], &e, 0); if (*e) return EC_ERROR_PARAM3 + i; } @@ -498,8 +463,7 @@ static int command_ble_hci_cmd(int argc, char **argv) header.paramLen = length; memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); - memcpy(hci_buf + sizeof(struct hciCmdHdr), - param, length); + memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length); hci_cmd(hci_buf); @@ -521,7 +485,7 @@ static int command_hcitool(int argc, char **argv) return EC_ERROR_PARAM_COUNT; if (argv[1][0] == 'l') /* strcmp lcmd */ - return command_ble_hci_cmd(argc-1, &argv[1]); + return command_ble_hci_cmd(argc - 1, &argv[1]); ogf = strtoi(argv[2], &e, 16); if (*e) @@ -532,7 +496,7 @@ static int command_hcitool(int argc, char **argv) return EC_ERROR_PARAM3; header.opcode = CMD_MAKE_OPCODE(ogf, ocf); - header.paramLen = argc-4; + header.paramLen = argc - 4; memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); for (i = 4; i < argc; i++) { @@ -547,9 +511,10 @@ static int command_hcitool(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hcitool, command_hcitool, - "cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)", - "Send an hci command of length len"); +DECLARE_CONSOLE_COMMAND( + hcitool, command_hcitool, + "cmd ogf ocf b0 b1 b2 b3... or lcmd opcode len uint32.. (little endian)", + "Send an hci command of length len"); static int command_ble_hci_acl(int argc, char **argv) { @@ -574,7 +539,7 @@ static int command_ble_hci_acl(int argc, char **argv) } for (i = 3; i < argc; i++) { - param[i-3] = strtoi(argv[i], &e, 0); + param[i - 3] = strtoi(argv[i], &e, 0); if (*e) return EC_ERROR_PARAM3 + i; } @@ -583,8 +548,7 @@ static int command_ble_hci_acl(int argc, char **argv) header.len = length; memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); - memcpy(hci_buf + sizeof(struct hciCmdHdr), - param, length); + memcpy(hci_buf + sizeof(struct hciCmdHdr), param, length); hci_cmd(hci_buf); @@ -625,33 +589,33 @@ static int command_ble_hci_adv(int argc, char **argv) header.paramLen = sizeof(struct hciLeSetAdvParams); memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); - memcpy(hci_buf + sizeof(struct hciCmdHdr), - adv_params[p], header.paramLen); + memcpy(hci_buf + sizeof(struct hciCmdHdr), adv_params[p], + header.paramLen); hci_cmd(hci_buf); - header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Advertising_Data); + header.opcode = + CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertising_Data); header.paramLen = adv_lengths[adv]; memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); - memcpy(hci_buf + sizeof(struct hciCmdHdr), - adverts[adv], header.paramLen); + memcpy(hci_buf + sizeof(struct hciCmdHdr), adverts[adv], + header.paramLen); hci_cmd(hci_buf); - header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Scan_Response_Data); + header.opcode = + CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Scan_Response_Data); header.paramLen = scan_lengths[scan_rsp]; memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); - memcpy(hci_buf + sizeof(struct hciCmdHdr), - scans[scan_rsp], header.paramLen); + memcpy(hci_buf + sizeof(struct hciCmdHdr), scans[scan_rsp], + header.paramLen); hci_cmd(hci_buf); - header.opcode = CMD_MAKE_OPCODE(HCI_OGF_LE, - HCI_CMD_LE_Set_Advertise_Enable); + header.opcode = + CMD_MAKE_OPCODE(HCI_OGF_LE, HCI_CMD_LE_Set_Advertise_Enable); header.paramLen = sizeof(struct hciLeSetAdvEnable); memcpy(hci_buf, &header, sizeof(struct hciCmdHdr)); -- cgit v1.2.1 From 976caaa6edc5b4e1d0235e25739d89fea794caaf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:02 -0600 Subject: board/crota/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I06918e97808fde42c5ed78fc8694d99bbae8325b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728210 Reviewed-by: Jeremy Bettis --- board/crota/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/crota/fans.c b/board/crota/fans.c index 27f5bca929..443ccf13d3 100644 --- a/board/crota/fans.c +++ b/board/crota/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 8099f0cf1d08d1cd738b7f3a57d24801512f64e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:24 -0600 Subject: chip/mec1322/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I554467e2a010dcf34635567990fdc9e8c9a9d395 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729324 Reviewed-by: Jeremy Bettis --- chip/mec1322/system.c | 52 +++++++++++++++++++++++++-------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index b672f72d2d..acf47eb371 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -23,38 +23,37 @@ /* Indices for hibernate data registers (RAM backed by VBAT) */ enum hibdata_index { - HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ + HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ - HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ - HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ + HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ + HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ + HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ }; static void check_reset_cause(void) { uint32_t status = MEC1322_VBAT_STS; uint32_t flags = 0; - uint32_t rst_sts = MEC1322_PCR_CHIP_PWR_RST & - (MEC1322_PWR_RST_STS_VCC1 | - MEC1322_PWR_RST_STS_VBAT); + uint32_t rst_sts = + MEC1322_PCR_CHIP_PWR_RST & + (MEC1322_PWR_RST_STS_VCC1 | MEC1322_PWR_RST_STS_VBAT); /* Clear the reset causes now that we've read them */ MEC1322_VBAT_STS |= status; MEC1322_PCR_CHIP_PWR_RST |= rst_sts; /* - * BIT[6] determine VCC1 reset - */ + * BIT[6] determine VCC1 reset + */ if (rst_sts & MEC1322_PWR_RST_STS_VCC1) flags |= EC_RESET_FLAG_RESET_PIN; - flags |= MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS) = 0; - if ((status & MEC1322_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) + if ((status & MEC1322_VBAT_STS_WDT) && + !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD | + EC_RESET_FLAG_HIBERNATE))) flags |= EC_RESET_FLAG_WATCHDOG; system_set_reset_flags(flags); @@ -64,18 +63,18 @@ int system_is_reboot_warm(void) { uint32_t reset_flags; /* - * Check reset cause here, - * gpio_pre_init is executed faster than system_pre_init - */ + * Check reset cause here, + * gpio_pre_init is executed faster than system_pre_init + */ check_reset_cause(); reset_flags = system_get_reset_flags(); if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT) || - (reset_flags & EC_RESET_FLAG_HIBERNATE)) + (reset_flags & EC_RESET_FLAG_POWER_ON) || + (reset_flags & EC_RESET_FLAG_WATCHDOG) || + (reset_flags & EC_RESET_FLAG_HARD) || + (reset_flags & EC_RESET_FLAG_SOFT) || + (reset_flags & EC_RESET_FLAG_HIBERNATE)) return 0; else return 1; @@ -105,8 +104,7 @@ uint32_t chip_read_reset_flags(void) return MEC1322_VBAT_RAM(HIBDATA_INDEX_SAVED_RESET_FLAGS); } -noreturn -void _system_reset(int flags, int wake_from_hibernate) +noreturn void _system_reset(int flags, int wake_from_hibernate) { uint32_t save_flags = 0; @@ -381,14 +379,14 @@ enum ec_image system_get_shrspi_image_copy(void) uint32_t system_get_lfw_address(void) { - uint32_t * const lfw_vector = - (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE; + uint32_t *const lfw_vector = + (uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE; return *(lfw_vector + 1); } void system_set_image_copy(enum ec_image copy) { - MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ? - EC_IMAGE_RW : EC_IMAGE_RO; + MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) = + (copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO; } -- cgit v1.2.1 From a85db40a022df6348f1b51b54fd785051ffb12fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:24 -0600 Subject: board/primus/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic976d7630421f3548c1f9c83e889cd400407dc10 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727757 Reviewed-by: Jeremy Bettis --- board/primus/board.h | 126 ++++++++++++++++++++++++--------------------------- 1 file changed, 60 insertions(+), 66 deletions(-) diff --git a/board/primus/board.h b/board/primus/board.h index 0b118efb6d..ef992d129c 100644 --- a/board/primus/board.h +++ b/board/primus/board.h @@ -31,29 +31,29 @@ #undef CONFIG_VOLUME_BUTTONS /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY -#undef CONFIG_USB_PD_TCPM_NCT38XX +#undef CONFIG_USB_PD_TCPM_NCT38XX #define CONFIG_USB_PD_TCPM_RT1715 #define CONFIG_USBC_RETIMER_INTEL_BB #define CONFIG_USBC_PPC_SYV682X -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -61,33 +61,33 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL +#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT @@ -97,23 +97,23 @@ /* I2C Bus Configuration */ -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C1_PPC_BC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_C1_RT NPCX_I2C_PORT3_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C1_PPC_BC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_C1_RT NPCX_I2C_PORT3_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_USB_A0_A1_MIX NPCX_I2C_PORT6_1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -135,19 +135,19 @@ /* Fan features */ #define CONFIG_CUSTOM_FAN_CONTROL -#define CONFIG_FANS FAN_CH_COUNT -#define RPM_DEVIATION 1 +#define CONFIG_FANS FAN_CH_COUNT +#define RPM_DEVIATION 1 /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* PROCHOT defines */ -#define BATT_MAX_CONTINUE_DISCHARGE_WATT 66 +#define BATT_MAX_CONTINUE_DISCHARGE_WATT 66 /* Prochot assertion/deassertion ratios*/ #define PROCHOT_ADAPTER_WATT_RATIO 97 @@ -164,11 +164,11 @@ #define CONFIG_8042_AUX #define CONFIG_PS2 #define CONFIG_CMD_PS2 -#define PRIMUS_PS2_CH NPCX_PS2_CH1 +#define PRIMUS_PS2_CH NPCX_PS2_CH1 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -208,24 +208,18 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_LED2_WHITE = 0, /* PWM0 (white charger) */ - PWM_CH_TKP_A_LED_N, /* PWM1 (LOGO led on A cover) */ - PWM_CH_LED1_AMBER, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED4, /* PWM7 (power) */ + PWM_CH_LED2_WHITE = 0, /* PWM0 (white charger) */ + PWM_CH_TKP_A_LED_N, /* PWM1 (LOGO led on A cover) */ + PWM_CH_LED1_AMBER, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED4, /* PWM7 (power) */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 6109c26f04f50cab6d00ac66b7483f9c04de84f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:41 -0600 Subject: chip/stm32/i2c-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1010ef054e74a82f977d4f68b01f640b5a760c88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729515 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32f3.c | 654 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 653 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/i2c-stm32f3.c diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c deleted file mode 120000 index ce8523ea90..0000000000 --- a/chip/stm32/i2c-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -i2c-stm32f0.c \ No newline at end of file diff --git a/chip/stm32/i2c-stm32f3.c b/chip/stm32/i2c-stm32f3.c new file mode 100644 index 0000000000..7120144c4a --- /dev/null +++ b/chip/stm32/i2c-stm32f3.c @@ -0,0 +1,653 @@ +/* Copyright 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "chipset.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "hwtimer.h" +#include "i2c.h" +#include "i2c_private.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "usb_pd_tcpc.h" +#include "usb_pd_tcpm.h" +#include "util.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_I2C, outstr) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) + +/* Transmit timeout in microseconds */ +#define I2C_TX_TIMEOUT_CONTROLLER (10 * MSEC) + +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS +#if (I2C_PORT_EC == STM32_I2C1_PORT) +#define IRQ_PERIPHERAL STM32_IRQ_I2C1 +#else +#define IRQ_PERIPHERAL STM32_IRQ_I2C2 +#endif +#endif + +/* I2C port state data */ +struct i2c_port_data { + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ +}; +static struct i2c_port_data pdata[I2C_PORT_COUNT]; + +void i2c_set_timeout(int port, uint32_t timeout) +{ + pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_CONTROLLER; +} + +/* timingr register values for supported input clks / i2c clk rates */ +static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { + [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ +}; + +/** + * Wait for ISR register to contain the specified mask. + * + * Returns EC_SUCCESS, EC_ERROR_TIMEOUT if timed out waiting, or + * EC_ERROR_UNKNOWN if an error bit appeared in the status register. + */ +static int wait_isr(int port, int mask) +{ + uint32_t start = __hw_clock_source_read(); + uint32_t delta = 0; + + do { + int isr = STM32_I2C_ISR(port); + + /* Check for errors */ + if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | + STM32_I2C_ISR_NACK)) + return EC_ERROR_UNKNOWN; + + /* Check for desired mask */ + if ((isr & mask) == mask) + return EC_SUCCESS; + + delta = __hw_clock_source_read() - start; + + /** + * Depending on the bus speed, busy loop for a while before + * sleeping and letting other things run. + */ + if (delta >= busyloop_us[pdata[port].freq]) + usleep(100); + } while (delta < pdata[port].timeout_us); + + return EC_ERROR_TIMEOUT; +} + +/* Supported i2c input clocks */ +enum stm32_i2c_clk_src { + I2C_CLK_SRC_48MHZ = 0, + I2C_CLK_SRC_8MHZ = 1, + I2C_CLK_SRC_COUNT, +}; + +/* timingr register values for supported input clks / i2c clk rates */ +static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { + [I2C_CLK_SRC_48MHZ] = { + [I2C_FREQ_1000KHZ] = 0x50100103, + [I2C_FREQ_400KHZ] = 0x50330609, + [I2C_FREQ_100KHZ] = 0xB0421214, + }, + [I2C_CLK_SRC_8MHZ] = { + [I2C_FREQ_1000KHZ] = 0x00100306, + [I2C_FREQ_400KHZ] = 0x00310309, + [I2C_FREQ_100KHZ] = 0x10420f13, + }, +}; + +int chip_i2c_set_freq(int port, enum i2c_freq freq) +{ + enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ; + +#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + if (port == STM32_I2C1_PORT) { + /* + * Use HSI (8MHz) for i2c clock. This allows smooth wakeup + * from STOP mode since HSI is only clock running immediately + * upon exit from STOP mode. + */ + src = I2C_CLK_SRC_8MHZ; + } +#endif + + /* Disable port */ + STM32_I2C_CR1(port) = 0; + STM32_I2C_CR2(port) = 0; + /* Set clock frequency */ + STM32_I2C_TIMINGR(port) = timingr_regs[src][freq]; + /* Enable port */ + STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; + + pdata[port].freq = freq; + + return EC_SUCCESS; +} + +enum i2c_freq chip_i2c_get_freq(int port) +{ + return pdata[port].freq; +} + +/** + * Initialize on the specified I2C port. + * + * @param p the I2c port + */ +static int i2c_init_port(const struct i2c_port_t *p) +{ + int port = p->port; + int ret = EC_SUCCESS; + enum i2c_freq freq; + + /* Enable clocks to I2C modules if necessary */ + if (!(STM32_RCC_APB1ENR & (1 << (21 + port)))) + STM32_RCC_APB1ENR |= 1 << (21 + port); + + if (port == STM32_I2C1_PORT) { +#if defined(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) && \ + defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + /* + * Use HSI (8MHz) for i2c clock. This allows smooth wakeup + * from STOP mode since HSI is only clock running immediately + * upon exit from STOP mode. + */ + STM32_RCC_CFGR3 &= ~0x10; +#else + /* Use SYSCLK for i2c clock. */ + STM32_RCC_CFGR3 |= 0x10; +#endif + } + + /* Configure GPIOs */ + gpio_config_module(MODULE_I2C, 1); + + /* Set clock frequency */ + switch (p->kbps) { + case 1000: + freq = I2C_FREQ_1000KHZ; + break; + case 400: + freq = I2C_FREQ_400KHZ; + break; + case 100: + freq = I2C_FREQ_100KHZ; + break; + default: /* unknown speed, defaults to 100kBps */ + CPRINTS("I2C bad speed %d kBps", p->kbps); + freq = I2C_FREQ_100KHZ; + ret = EC_ERROR_INVAL; + } + + /* Set up initial bus frequencies */ + chip_i2c_set_freq(p->port, freq); + + /* Set up default timeout */ + i2c_set_timeout(port, 0); + + return ret; +} + +/*****************************************************************************/ +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS +/* Host command peripheral */ +/* + * Buffer for received host command packets (including prefix byte on request, + * and result/size on response). After any protocol-specific headers, the + * buffers must be 32-bit aligned. + */ +static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 + + CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4); +static uint8_t *const host_buffer = host_buffer_padded + 2; +static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4); +static int host_i2c_resp_port; +static int tx_pending; +static int tx_index, tx_end; +static struct host_packet i2c_packet; + +static void i2c_send_response_packet(struct host_packet *pkt) +{ + int size = pkt->response_size; + uint8_t *out = host_buffer; + + /* Ignore host command in-progress */ + if (pkt->driver_result == EC_RES_IN_PROGRESS) + return; + + /* Write result and size to first two bytes. */ + *out++ = pkt->driver_result; + *out++ = size; + + /* host_buffer data range */ + tx_index = 0; + tx_end = size + 2; + + /* + * Set the transmitter to be in 'not full' state to keep sending + * '0xec' in the event loop. Because of this, the controller i2c + * doesn't need to snoop the response stream to abort transaction. + */ + STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; +} + +/* Process the command in the i2c host buffer */ +static void i2c_process_command(void) +{ + char *buff = host_buffer; + + /* + * TODO(crosbug.com/p/29241): Combine this functionality with the + * i2c_process_command function in chip/stm32/i2c-stm32f.c to make one + * host command i2c process function which handles all protocol + * versions. + */ + i2c_packet.send_response = i2c_send_response_packet; + + i2c_packet.request = (const void *)(&buff[1]); + i2c_packet.request_temp = params_copy; + i2c_packet.request_max = sizeof(params_copy); + /* Don't know the request size so pass in the entire buffer */ + i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE; + + /* + * Stuff response at buff[2] to leave the first two bytes of + * buffer available for the result and size to send over i2c. Note + * that this 2-byte offset and the 2-byte offset from host_buffer + * add up to make the response buffer 32-bit aligned. + */ + i2c_packet.response = (void *)(&buff[2]); + i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE; + i2c_packet.response_size = 0; + + if (*buff >= EC_COMMAND_PROTOCOL_3) { + i2c_packet.driver_result = EC_RES_SUCCESS; + } else { + /* Only host command protocol 3 is supported. */ + i2c_packet.driver_result = EC_RES_INVALID_HEADER; + } + host_packet_receive(&i2c_packet); +} + +#ifdef TCPCI_I2C_PERIPHERAL +static void i2c_send_tcpc_response(int len) +{ + /* host_buffer data range, beyond this length, will return 0xec */ + tx_index = 0; + tx_end = len; + + /* enable transmit interrupt and use irq to send data back */ + STM32_I2C_CR1(host_i2c_resp_port) |= STM32_I2C_CR1_TXIE; +} + +static void i2c_process_tcpc_command(int read, int addr, int len) +{ + tcpc_i2c_process(read, TCPC_ADDR_TO_PORT(addr), len, &host_buffer[0], + i2c_send_tcpc_response); +} +#endif + +static void i2c_event_handler(int port) +{ + int i2c_isr; + static int rx_pending, buf_idx; +#ifdef TCPCI_I2C_PERIPHERAL + int addr; +#endif + + i2c_isr = STM32_I2C_ISR(port); + + /* + * Check for error conditions. Note, arbitration loss and bus error + * are the only two errors we can get as a peripheral allowing clock + * stretching and in non-SMBus mode. + */ + if (i2c_isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR)) { + rx_pending = 0; + tx_pending = 0; + + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + + /* Clear error status bits */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | + STM32_I2C_ICR_ARLOCF; + } + + /* Transfer matched our peripheral address */ + if (i2c_isr & STM32_I2C_ISR_ADDR) { + if (i2c_isr & STM32_I2C_ISR_DIR) { + /* Transmitter peripheral */ + /* Clear transmit buffer */ + STM32_I2C_ISR(port) |= STM32_I2C_ISR_TXE; + + /* Enable txis interrupt to start response */ + STM32_I2C_CR1(port) |= STM32_I2C_CR1_TXIE; + } else { + /* Receiver peripheral */ + buf_idx = 0; + rx_pending = 1; + } + + /* Clear ADDR bit by writing to ADDRCF bit */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_ADDRCF; + /* Inhibit sleep mode when addressed until STOPF flag is set */ + disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); + } + + /* Receiver full event */ + if (i2c_isr & STM32_I2C_ISR_RXNE) + host_buffer[buf_idx++] = STM32_I2C_RXDR(port); + + /* Stop condition on bus */ + if (i2c_isr & STM32_I2C_ISR_STOP) { +#ifdef TCPCI_I2C_PERIPHERAL + /* + * if tcpc is being addressed, and we received a stop + * while rx is pending, then this is a write only to + * the tcpc. + */ + addr = STM32_I2C_ISR_ADDCODE(STM32_I2C_ISR(port)); + if (rx_pending && ADDR_IS_TCPC(addr)) + i2c_process_tcpc_command(0, addr, buf_idx); +#endif + rx_pending = 0; + tx_pending = 0; + + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + + /* Clear STOPF bit by writing to STOPCF bit */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_STOPCF; + + /* No longer inhibit deep sleep after stop condition */ + enable_sleep(SLEEP_MASK_I2C_PERIPHERAL); + } + + /* Controller requested STOP or RESTART */ + if (i2c_isr & STM32_I2C_ISR_NACK) { + /* Make sure TXIS interrupt is disabled */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + /* Clear NACK */ + STM32_I2C_ICR(port) |= STM32_I2C_ICR_NACKCF; + /* Resend last byte on RESTART */ + if (port == I2C_PORT_EC && tx_index) + tx_index--; + } + + /* Transmitter empty event */ + if (i2c_isr & STM32_I2C_ISR_TXIS) { + if (port == I2C_PORT_EC) { /* host is waiting for PD response */ + if (tx_pending) { + if (tx_index < tx_end) { + STM32_I2C_TXDR(port) = + host_buffer[tx_index++]; + } else { + STM32_I2C_TXDR(port) = 0xec; + /* + * Set tx_index = 0 to prevent NACK + * handler resending last buffer byte. + */ + tx_index = 0; + tx_end = 0; + /* No pending data */ + tx_pending = 0; + } + } else if (rx_pending) { + host_i2c_resp_port = port; + /* + * Disable TXIS interrupt, transmission will + * be prepared by host command task. + */ + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; + +#ifdef TCPCI_I2C_PERIPHERAL + addr = STM32_I2C_ISR_ADDCODE( + STM32_I2C_ISR(port)); + if (ADDR_IS_TCPC(addr)) + i2c_process_tcpc_command(1, addr, + buf_idx); + else +#endif + i2c_process_command(); + + /* Reset host buffer after end of transfer */ + rx_pending = 0; + tx_pending = 1; + } else { + STM32_I2C_TXDR(port) = 0xec; + } + } + } +} +static void i2c2_event_interrupt(void) +{ + i2c_event_handler(I2C_PORT_EC); +} +DECLARE_IRQ(IRQ_PERIPHERAL, i2c2_event_interrupt, 2); +#endif + +/*****************************************************************************/ +/* Interface */ + +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) +{ + int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; + int rv = EC_SUCCESS; + int i; + int xfer_start = flags & I2C_XFER_START; + int xfer_stop = flags & I2C_XFER_STOP; + +#if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT) + if (port == CONFIG_I2C_SCL_GATE_PORT && + addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) + gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1); +#endif + + ASSERT(out || !out_bytes); + ASSERT(in || !in_bytes); + + /* Clear status */ + if (xfer_start) { + uint32_t cr2 = STM32_I2C_CR2(port); + + STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; + STM32_I2C_CR2(port) = 0; + if (cr2 & STM32_I2C_CR2_RELOAD) { + /* + * If I2C_XFER_START flag is on and we've set RELOAD=1 + * in previous chip_i2c_xfer() call. Then we are + * probably in the middle of an i2c transaction. + * + * In this case, we need to clear the RELOAD bit and + * wait for Transfer Complete (TC) flag, to make sure + * the chip is not expecting another NBYTES data, And + * send repeated-start correctly. + */ + rv = wait_isr(port, STM32_I2C_ISR_TC); + if (rv) + goto xfer_exit; + } + } + + if (out_bytes || !in_bytes) { + /* + * Configure the write transfer: if we are stopping then set + * AUTOEND bit to automatically set STOP bit after NBYTES. + * if we are not stopping, set RELOAD bit so that we can load + * NBYTES again. if we are starting, then set START bit. + */ + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); + + for (i = 0; i < out_bytes; i++) { + rv = wait_isr(port, STM32_I2C_ISR_TXIS); + if (rv) + goto xfer_exit; + /* Write next data byte */ + STM32_I2C_TXDR(port) = out[i]; + } + } + if (in_bytes) { + if (out_bytes) { /* wait for completion of the write */ + rv = wait_isr(port, STM32_I2C_ISR_TC); + if (rv) + goto xfer_exit; + } + /* + * Configure the read transfer: if we are stopping then set + * AUTOEND bit to automatically set STOP bit after NBYTES. + * if we are not stopping, set RELOAD bit so that we can load + * NBYTES again. if we were just transmitting, we need to + * set START bit to send (re)start and begin read transaction. + */ + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + + for (i = 0; i < in_bytes; i++) { + /* Wait for receive buffer not empty */ + rv = wait_isr(port, STM32_I2C_ISR_RXNE); + if (rv) + goto xfer_exit; + + in[i] = STM32_I2C_RXDR(port); + } + } + + /* + * If we are stopping, then we already set AUTOEND and we should + * wait for the stop bit to be transmitted. Otherwise, we set + * the RELOAD bit and we should wait for transfer complete + * reload (TCR). + */ + rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); + if (rv) + goto xfer_exit; + +xfer_exit: + /* clear status */ + if (xfer_stop) + STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; + + /* On error, queue a stop condition */ + if (rv) { + /* queue a STOP condition */ + STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; + /* wait for it to take effect */ + /* Wait up to 100 us for bus idle */ + for (i = 0; i < 10; i++) { + if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) + break; + udelay(10); + } + + /* + * Allow bus to idle for at least one 100KHz clock = 10 us. + * This allows peripherals on the bus to detect bus-idle before + * the next start condition. + */ + udelay(10); + /* re-initialize the controller */ + STM32_I2C_CR2(port) = 0; + STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; + udelay(10); + STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; + } + +#ifdef CONFIG_I2C_SCL_GATE_ADDR + if (port == CONFIG_I2C_SCL_GATE_PORT && + addr_flags == CONFIG_I2C_SCL_GATE_ADDR_FLAGS) + gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0); +#endif + + return rv; +} + +int i2c_raw_get_scl(int port) +{ + enum gpio_signal g; + + if (get_scl_from_i2c_port(port, &g) == EC_SUCCESS) + return gpio_get_level(g); + + /* If no SCL pin defined for this port, then return 1 to appear idle. */ + return 1; +} + +int i2c_raw_get_sda(int port) +{ + enum gpio_signal g; + + if (get_sda_from_i2c_port(port, &g) == EC_SUCCESS) + return gpio_get_level(g); + + /* If no SCL pin defined for this port, then return 1 to appear idle. */ + return 1; +} + +int i2c_get_line_levels(int port) +{ + return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); +} + +void i2c_init(void) +{ + const struct i2c_port_t *p = i2c_ports; + int i; + + for (i = 0; i < i2c_ports_used; i++, p++) + i2c_init_port(p); + +#ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; +#if defined(CONFIG_LOW_POWER_IDLE) && (I2C_PORT_EC == STM32_I2C1_PORT) + /* + * If using low power idle and EC port is I2C1, then set I2C1 to wake + * from STOP mode on address match. Note, this only works on I2C1 and + * only if the clock to I2C1 is HSI 8MHz. + */ + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_WUPEN; +#endif + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); +#ifdef TCPCI_I2C_PERIPHERAL + /* + * Configure TCPC address with OA2[1] masked so that we respond + * to CONFIG_TCPC_I2C_BASE_ADDR and CONFIG_TCPC_I2C_BASE_ADDR + 2. + */ + STM32_I2C_OAR2(I2C_PORT_EC) = + 0x8100 | + (I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS) << 1); +#endif + task_enable_irq(IRQ_PERIPHERAL); +#endif +} -- cgit v1.2.1 From 1db05af7faa0d0de5766d706f8675eb1f9d97a65 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:19 -0600 Subject: baseboard/hatch/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0312f39c155eb73792caa1f0f7bc32e1e24770cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727521 Reviewed-by: Jeremy Bettis --- baseboard/hatch/baseboard.c | 166 +++++++++++++++++++------------------------- 1 file changed, 70 insertions(+), 96 deletions(-) diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c index bdbeb36a3c..dd34de956c 100644 --- a/baseboard/hatch/baseboard.c +++ b/baseboard/hatch/baseboard.c @@ -31,11 +31,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* Wake up pins */ @@ -52,85 +52,65 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { #ifdef CONFIG_ACCEL_FIFO - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, #endif - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, #endif - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, #ifdef BOARD_AKEMI - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif #ifdef BOARD_JINLON - { - .name = "thermal", - .port = I2C_PORT_THERMAL, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "thermal", + .port = I2C_PORT_THERMAL, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif #ifdef BOARD_MUSHU - { - .name = "f75303_temp", - .port = I2C_PORT_THERMAL, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "gpu_temp", - .port = I2C_PORT_GPU, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "f75303_temp", + .port = I2C_PORT_THERMAL, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "gpu_temp", + .port = I2C_PORT_GPU, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #endif - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 100, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -202,17 +182,13 @@ void board_hibernate(void) /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - [USB_PD_PORT_TCPC_1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_1] = { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, #endif }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -270,8 +246,8 @@ uint16_t tcpc_get_alert_status(void) return status; } -static void reset_pd_port(int port, enum gpio_signal reset_gpio, - int hold_delay, int finish_delay) +static void reset_pd_port(int port, enum gpio_signal reset_gpio, int hold_delay, + int finish_delay) { int level = !!(tcpc_config[port].flags & TCPC_FLAGS_RESET_ACTIVE_HIGH); @@ -308,8 +284,7 @@ void board_reset_pd_mcu(void) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_valid_port && port != CHARGE_PORT_NONE) @@ -365,20 +340,19 @@ int ppc_get_alert_status(int port) if (port == USB_PD_PORT_TCPC_0) return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; return port == USB_PD_PORT_TCPC_0 ? - gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 : + gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0 : #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; + gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; #else - EC_SUCCESS; + EC_SUCCESS; #endif } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } #ifdef USB_PD_PORT_TCPC_MST -- cgit v1.2.1 From d44c8ffee365a4804f496807aff7aad21241f89b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:57 -0600 Subject: board/gimble/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I537f7c398fc38ad71eda52b6b87e291adc0b86ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728409 Reviewed-by: Jeremy Bettis --- board/gimble/board.c | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/board/gimble/board.c b/board/gimble/board.c index 2d0ebdeb80..85cb1bdb9e 100644 --- a/board/gimble/board.c +++ b/board/gimble/board.c @@ -35,8 +35,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -106,8 +106,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -141,53 +141,53 @@ __overridable void board_ps8xxx_tcpc_init(int port) { int val; - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_10G, &val)) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_APTX_EQ_AT_10G, &val)) CPRINTS("ps8815: fail to read reg 0x%02x", PS8815_REG_APTX_EQ_AT_10G); /* APTX2 EQ 23dB, APTX1 EQ 23dB */ - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_10G, 0x99)) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_APTX_EQ_AT_10G, 0x99)) CPRINTS("ps8815: fail to write reg 0x%02x", PS8815_REG_APTX_EQ_AT_10G); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_10G, &val)) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_RX_EQ_AT_10G, &val)) CPRINTS("ps8815: fail to read reg 0x%02x", PS8815_REG_RX_EQ_AT_10G); /* RX2 EQ 18dB, RX1 EQ 16dB */ - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_10G, 0x64)) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_RX_EQ_AT_10G, 0x64)) CPRINTS("ps8815: fail to write reg 0x%02x", PS8815_REG_RX_EQ_AT_10G); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_5G, &val)) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_APTX_EQ_AT_5G, &val)) CPRINTS("ps8815: fail to read reg 0x%02x", PS8815_REG_APTX_EQ_AT_5G); /* APTX2 EQ 16dB, APTX1 EQ 16dB */ - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_APTX_EQ_AT_5G, 0x44)) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_APTX_EQ_AT_5G, 0x44)) CPRINTS("ps8815: fail to write reg 0x%02x", PS8815_REG_APTX_EQ_AT_5G); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_5G, &val)) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_RX_EQ_AT_5G, &val)) CPRINTS("ps8815: fail to read reg 0x%02x", PS8815_REG_RX_EQ_AT_5G); /* RX2 EQ 16dB, RX1 EQ 16dB */ - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_P1_FLAGS, PS8815_REG_RX_EQ_AT_5G, 0x44)) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_P1_FLAGS, + PS8815_REG_RX_EQ_AT_5G, 0x44)) CPRINTS("ps8815: fail to write reg 0x%02x", PS8815_REG_RX_EQ_AT_5G); } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Follow OEM request to limit the input current to @@ -195,7 +195,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 90 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 376174ef72638a660a86c507d21a87888ec1a601 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:40 -0600 Subject: board/primus/ps2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie81c7c7a39639eb54446ba5915f1b646462eca99 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727763 Reviewed-by: Jeremy Bettis --- board/primus/ps2.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/primus/ps2.c b/board/primus/ps2.c index ba341f6be0..8cf1e641d8 100644 --- a/board/primus/ps2.c +++ b/board/primus/ps2.c @@ -15,7 +15,7 @@ #include "registers.h" #include "time.h" -#define PS2_TRANSMIT_DELAY_MS 10 +#define PS2_TRANSMIT_DELAY_MS 10 static uint8_t queue_data[3]; static int data_count; @@ -39,8 +39,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); */ static void enable_ps2(void) { - gpio_set_alternate_function(GPIO_PORT_6, - BIT(2) | BIT(3), GPIO_ALT_FUNC_DEFAULT); + gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3), + GPIO_ALT_FUNC_DEFAULT); } DECLARE_DEFERRED(enable_ps2); @@ -48,8 +48,8 @@ static void disable_ps2(void) { gpio_set_flags(GPIO_EC_PS2_SCL_TPAD, GPIO_ODR_LOW); gpio_set_flags(GPIO_EC_PS2_SDA_TPAD, GPIO_ODR_LOW); - gpio_set_alternate_function(GPIO_PORT_6, - BIT(2) | BIT(3), GPIO_ALT_FUNC_NONE); + gpio_set_alternate_function(GPIO_PORT_6, BIT(2) | BIT(3), + GPIO_ALT_FUNC_NONE); /* make sure PLTRST# goes high and re-enable PS2.*/ hook_call_deferred(&enable_ps2_data, 2 * SECOND); } @@ -96,7 +96,7 @@ uint8_t get_trackpoint_id(void) * Also make sure only return the trackpoint device ID. */ if (queue_data[1] == TP_VARIANT_ELAN || - queue_data[1] == TP_VARIANT_SYNAPTICS) + queue_data[1] == TP_VARIANT_SYNAPTICS) return queue_data[1]; else return 0; @@ -129,10 +129,10 @@ static void ps2_suspend(void) */ if (trackpoint_id == TP_VARIANT_ELAN) send_command_to_trackpoint(TP_TOGGLE_BURST, - TP_TOGGLE_ELAN_SLEEP); + TP_TOGGLE_ELAN_SLEEP); else if (trackpoint_id == TP_VARIANT_SYNAPTICS) send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG, - TP_TOGGLE_SNAPTICS_SLEEP); + TP_TOGGLE_SNAPTICS_SLEEP); /* Clear the data in queue and the counter */ memset(queue_data, 0, ARRAY_SIZE(queue_data)); @@ -154,7 +154,7 @@ static void ps2_resume(void) */ if (trackpoint_id == TP_VARIANT_SYNAPTICS) send_command_to_trackpoint(TP_TOGGLE_SOURCE_TAG, - TP_TOGGLE_SNAPTICS_SLEEP); + TP_TOGGLE_SNAPTICS_SLEEP); /* Clear the data in queue and the counter */ memset(queue_data, 0, ARRAY_SIZE(queue_data)); -- cgit v1.2.1 From aae8dbbdf88682c70d68e0f4dcd7d299c73df9b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:57 -0600 Subject: board/scarlet/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea985649e56d775b30a69263530ed7a18ff66376 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728917 Reviewed-by: Jeremy Bettis --- board/scarlet/usb_pd_policy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/scarlet/usb_pd_policy.c b/board/scarlet/usb_pd_policy.c index cba4540ecd..f2d784a8e9 100644 --- a/board/scarlet/usb_pd_policy.c +++ b/board/scarlet/usb_pd_policy.c @@ -21,8 +21,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en; @@ -33,7 +33,6 @@ int board_vbus_source_enabled(int port) int pd_set_power_supply_ready(int port) { - pd_set_vbus_discharge(port, 0); /* Provide VBUS */ vbus_en = 1; -- cgit v1.2.1 From 94b988ece617dcfe24f8bff4d3f02ac0bc8c3d43 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:23 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I159383a499d488242df92d07396f7715c2497f6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730575 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e7.c | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e7.c b/test/usb_tcpmv2_td_pd_src3_e7.c index fa2c68b64e..d15a848e51 100644 --- a/test/usb_tcpmv2_td_pd_src3_e7.c +++ b/test/usb_tcpmv2_td_pd_src3_e7.c @@ -22,7 +22,6 @@ #define EXT_MSG_DATA_SIZE_1 1 #define GBSDB_FIXED_BATTERY_0 (0 << 16) - static int number_of_fixed_batteries(void) { return CONFIG_NUM_FIXED_BATTERIES; @@ -78,13 +77,8 @@ int test_td_pd_src3_e7(void) possible[1].ctrl_msg = 0; possible[1].data_msg = PD_DATA_SOURCE_CAP; - TEST_EQ(verify_tcpci_possible_tx(possible, - 2, - &found_index, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_possible_tx(possible, 2, &found_index, data, + sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); if (found_index == 0) { mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); @@ -104,8 +98,7 @@ int test_td_pd_src3_e7(void) mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); task_wait_event(10 * MSEC); - if (data[HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT + + if (data[HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + SRC_CAP_EXT_NUM_BATTERY_OFFSET] == 0) return EC_SUCCESS; } @@ -114,11 +107,9 @@ int test_td_pd_src3_e7(void) * e) The Tester waits until it can start an AMS (Run PROC.PD.E3) and * sends a Get_Battery_Status message to the UUT */ - ext_msg = EXT_MSG_CHUNKED | - EXT_MSG_DATA_SIZE_1 | - GBSDB_FIXED_BATTERY_0; + ext_msg = EXT_MSG_CHUNKED | EXT_MSG_DATA_SIZE_1 | GBSDB_FIXED_BATTERY_0; partner_send_msg(TCPCI_MSG_SOP, PD_EXT_GET_BATTERY_STATUS, 1, 1, - &ext_msg); + &ext_msg); /* * f) If a Battery_Status message is not received within @@ -127,10 +118,8 @@ int test_td_pd_src3_e7(void) * been transmitted to the time the first bit of the Battery_Status * message preamble has been received. */ - TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, - 0, - PD_DATA_BATTERY_STATUS, - (15 * MSEC)), + TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0, + PD_DATA_BATTERY_STATUS, (15 * MSEC)), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); task_wait_event(10 * MSEC); -- cgit v1.2.1 From bb57622ac82e5218fc312ffa76d8732c1ecc0dc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:13 -0600 Subject: baseboard/intelrvp/led_states.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic490b9cb0912e2a3694d36665c8fbb537657b287 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727901 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/led_states.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/baseboard/intelrvp/led_states.c b/baseboard/intelrvp/led_states.c index 5f8768bdd9..18126b5314 100644 --- a/baseboard/intelrvp/led_states.c +++ b/baseboard/intelrvp/led_states.c @@ -15,11 +15,11 @@ #include "led_common.h" #include "led_states.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) static enum led_states led_get_state(void) { - int charge_lvl; + int charge_lvl; enum led_states new_state = LED_NUM_STATES; switch (charge_get_state()) { @@ -88,14 +88,14 @@ static void led_update_battery(void) ticks = 0; period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - + led_bat_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for battery state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_battery(LED_OFF); return; } @@ -104,8 +104,8 @@ static void led_update_battery(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ @@ -141,14 +141,14 @@ static void led_update_power(void) ticks = 0; period = led_pwr_state_table[led_state][LED_PHASE_0].time + - led_pwr_state_table[led_state][LED_PHASE_1].time; - + led_pwr_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for power state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_power(LED_OFF); return; } @@ -157,8 +157,8 @@ static void led_update_power(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ -- cgit v1.2.1 From f0dfc7745409660e10864236c0433052d6c78e51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:13 -0600 Subject: include/driver/als_tcs3400.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4866bb97388019a2f3f987b9dd350922d139c54c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730271 Reviewed-by: Jeremy Bettis --- include/driver/als_tcs3400.h | 123 +++++++++++++++++++++---------------------- 1 file changed, 61 insertions(+), 62 deletions(-) diff --git a/include/driver/als_tcs3400.h b/include/driver/als_tcs3400.h index 0748befa71..12608af279 100644 --- a/include/driver/als_tcs3400.h +++ b/include/driver/als_tcs3400.h @@ -11,70 +11,69 @@ #include "driver/als_tcs3400_public.h" /* ID for TCS34001 and TCS34005 */ -#define TCS340015_DEVICE_ID 0x90 +#define TCS340015_DEVICE_ID 0x90 /* ID for TCS34003 and TCS34007 */ -#define TCS340037_DEVICE_ID 0x93 +#define TCS340037_DEVICE_ID 0x93 /* Register Map */ -#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ -#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ -#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ -#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ -#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ -#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ -#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ -#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ -#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ -#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ -#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ -#define TCS_I2C_REVID 0x91 /* R Revision ID */ -#define TCS_I2C_ID 0x92 /* R Device ID */ -#define TCS_I2C_STATUS 0x93 /* R Device status */ -#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ -#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ -#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ -#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ -#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ -#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ -#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ -#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ -#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ -#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ -#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ -#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ - -#define TCS_I2C_ENABLE_POWER_ON BIT(0) -#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) -#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) -#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) -#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) -#define TCS_I2C_ENABLE_MASK (TCS_I2C_ENABLE_POWER_ON | \ - TCS_I2C_ENABLE_ADC_ENABLE | \ - TCS_I2C_ENABLE_WAIT_ENABLE | \ - TCS_I2C_ENABLE_INT_ENABLE | \ - TCS_I2C_ENABLE_SLEEP_AFTER_INT) +#define TCS_I2C_ENABLE 0x80 /* R/W Enables states and interrupts */ +#define TCS_I2C_ATIME 0x81 /* R/W RGBC integration time */ +#define TCS_I2C_WTIME 0x83 /* R/W Wait time */ +#define TCS_I2C_AILTL 0x84 /* R/W Clear irq low threshold low byte */ +#define TCS_I2C_AILTH 0x85 /* R/W Clear irq low threshold high byte */ +#define TCS_I2C_AIHTL 0x86 /* R/W Clear irq high threshold low byte */ +#define TCS_I2C_AIHTH 0x87 /* R/W Clear irq high threshold high byte */ +#define TCS_I2C_PERS 0x8C /* R/W Interrupt persistence filter */ +#define TCS_I2C_CONFIG 0x8D /* R/W Configuration */ +#define TCS_I2C_CONTROL 0x8F /* R/W Gain control register */ +#define TCS_I2C_AUX 0x90 /* R/W Auxiliary control register */ +#define TCS_I2C_REVID 0x91 /* R Revision ID */ +#define TCS_I2C_ID 0x92 /* R Device ID */ +#define TCS_I2C_STATUS 0x93 /* R Device status */ +#define TCS_I2C_CDATAL 0x94 /* R Clear / IR channel low data register */ +#define TCS_I2C_CDATAH 0x95 /* R Clear / IR channel high data register */ +#define TCS_I2C_RDATAL 0x96 /* R Red ADC low data register */ +#define TCS_I2C_RDATAH 0x97 /* R Red ADC high data register */ +#define TCS_I2C_GDATAL 0x98 /* R Green ADC low data register */ +#define TCS_I2C_GDATAH 0x99 /* R Green ADC high data register */ +#define TCS_I2C_BDATAL 0x9A /* R Blue ADC low data register */ +#define TCS_I2C_BDATAH 0x9B /* R Blue ADC high data register */ +#define TCS_I2C_IR 0xC0 /* R/W Access IR Channel */ +#define TCS_I2C_IFORCE 0xE4 /* W Force Interrupt */ +#define TCS_I2C_CICLEAR 0xE6 /* W Clear channel interrupt clear */ +#define TCS_I2C_AICLEAR 0xE7 /* W Clear all interrupts */ + +#define TCS_I2C_ENABLE_POWER_ON BIT(0) +#define TCS_I2C_ENABLE_ADC_ENABLE BIT(1) +#define TCS_I2C_ENABLE_WAIT_ENABLE BIT(3) +#define TCS_I2C_ENABLE_INT_ENABLE BIT(4) +#define TCS_I2C_ENABLE_SLEEP_AFTER_INT BIT(6) +#define TCS_I2C_ENABLE_MASK \ + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | \ + TCS_I2C_ENABLE_WAIT_ENABLE | TCS_I2C_ENABLE_INT_ENABLE | \ + TCS_I2C_ENABLE_SLEEP_AFTER_INT) enum tcs3400_mode { TCS3400_MODE_SUSPEND = 0, - TCS3400_MODE_IDLE = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE), - TCS3400_MODE_COLLECTING = (TCS_I2C_ENABLE_POWER_ON | - TCS_I2C_ENABLE_ADC_ENABLE | - TCS_I2C_ENABLE_INT_ENABLE), + TCS3400_MODE_IDLE = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE), + TCS3400_MODE_COLLECTING = + (TCS_I2C_ENABLE_POWER_ON | TCS_I2C_ENABLE_ADC_ENABLE | + TCS_I2C_ENABLE_INT_ENABLE), }; -#define TCS_I2C_CONTROL_MASK 0x03 -#define TCS_I2C_STATUS_RGBC_VALID BIT(0) -#define TCS_I2C_STATUS_ALS_IRQ BIT(4) -#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) +#define TCS_I2C_CONTROL_MASK 0x03 +#define TCS_I2C_STATUS_RGBC_VALID BIT(0) +#define TCS_I2C_STATUS_ALS_IRQ BIT(4) +#define TCS_I2C_STATUS_ALS_SATURATED BIT(7) -#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) +#define TCS_I2C_AUX_ASL_INT_ENABLE BIT(5) /* Light data resides at 0x94 thru 0x98 */ -#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL -#define TCS_CLEAR_DATA_SIZE 2 -#define TCS_RGBC_DATA_SIZE 8 +#define TCS_DATA_START_LOCATION TCS_I2C_CDATAL +#define TCS_CLEAR_DATA_SIZE 2 +#define TCS_RGBC_DATA_SIZE 8 #define TCS3400_DRV_DATA(_s) ((struct als_drv_data_t *)(_s)->drv_data) #define TCS3400_RGB_DRV_DATA(_s) \ @@ -96,20 +95,20 @@ enum tcs3400_mode { * To avoid this, we require value to be <= 20% of saturation level * (TCS_GAIN_SAT_LEVEL) before allowing gain to be increased. */ -#define TCS_GAIN_ADJUST_FACTOR 5 -#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) -#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ -#define TCS_UPSHIFT_FACTOR_D 10 -#define TCS_GAIN_UPSHIFT_LEVEL (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D \ - / TCS_UPSHIFT_FACTOR_N) +#define TCS_GAIN_ADJUST_FACTOR 5 +#define TCS_GAIN_SAT_LEVEL (TCS_SATURATION_LEVEL / TCS_GAIN_ADJUST_FACTOR) +#define TCS_UPSHIFT_FACTOR_N 25 /* upshift factor = 2.5 */ +#define TCS_UPSHIFT_FACTOR_D 10 +#define TCS_GAIN_UPSHIFT_LEVEL \ + (TCS_SATURATION_LEVEL * TCS_UPSHIFT_FACTOR_D / TCS_UPSHIFT_FACTOR_N) /* * Percentage of saturation level that the auto-adjusting anti-saturation * method will drive towards. */ #define TSC_SATURATION_LOW_BAND_PERCENT 90 -#define TSC_SATURATION_LOW_BAND_LEVEL (TCS_SATURATION_LEVEL * \ - TSC_SATURATION_LOW_BAND_PERCENT / 100) +#define TSC_SATURATION_LOW_BAND_LEVEL \ + (TCS_SATURATION_LEVEL * TSC_SATURATION_LOW_BAND_PERCENT / 100) enum crbg_index { CLEAR_CRGB_IDX = 0, @@ -134,9 +133,9 @@ enum crbg_index { * tcs3400-int = &als_clear; * }; */ -#define CONFIG_ALS_TCS3400_INT_EVENT \ +#define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(tcs3400_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ALS_TCS3400_H */ -- cgit v1.2.1 From af9fba02446b633b7ca1cc9b52beecdd2e99e912 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:58 -0600 Subject: board/coral/sku.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I96caa5f6ef57d854def4632e0f898762571a9df1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728160 Reviewed-by: Jeremy Bettis --- board/coral/sku.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/coral/sku.h b/board/coral/sku.h index 4588932377..98ff548ffd 100644 --- a/board/coral/sku.h +++ b/board/coral/sku.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_SKU_H #define __CROS_EC_SKU_H -#define SKU_CONVERTIBLE(id) (1 << ((id) & 0x7)) +#define SKU_CONVERTIBLE(id) (1 << ((id)&0x7)) /* * There are 256 possible SKUs for Coral. This table is used to map a given SKU @@ -22,7 +22,7 @@ static const uint8_t form_factor[32] = { SKU_CONVERTIBLE(4) | SKU_CONVERTIBLE(5), /* SKU 8 - 15 */ SKU_CONVERTIBLE(8) | SKU_CONVERTIBLE(9) | SKU_CONVERTIBLE(10) | - SKU_CONVERTIBLE(11), + SKU_CONVERTIBLE(11), /* SKU 16 - 23 */ 0x00, /* SKU 24 - 31 */ @@ -61,7 +61,7 @@ static const uint8_t form_factor[32] = { 0x00, /* SKU 160 - 167 */ SKU_CONVERTIBLE(163) | SKU_CONVERTIBLE(164) | SKU_CONVERTIBLE(165) | - SKU_CONVERTIBLE(166), + SKU_CONVERTIBLE(166), /* SKU 168 - 175 */ 0x00, /* SKU 176 - 183 */ @@ -86,6 +86,6 @@ static const uint8_t form_factor[32] = { 0x00, }; -#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id) & 0x7)) & 1) +#define SKU_IS_CONVERTIBLE(id) ((form_factor[(id) >> 3] >> ((id)&0x7)) & 1) #endif /* __CROS_EC_SKU_H */ -- cgit v1.2.1 From 2ba528b912e175ae911c0974e222187562a11542 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:06 -0600 Subject: board/corori/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id40c0b1b0c315468387716aeb167ab9cb00cf58a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728180 Reviewed-by: Jeremy Bettis --- board/corori/board.h | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/board/corori/board.h b/board/corori/board.h index 42d242abee..504b1cc67b 100644 --- a/board/corori/board.h +++ b/board/corori/board.h @@ -34,9 +34,8 @@ #define GPIO_BAT_LED_AMBER GPIO_LED_Y_ODL #define GPIO_PWR_LED_WHITE GPIO_LED_W_ODL - /* PWM */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -65,16 +64,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -89,17 +88,13 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; enum battery_type { BATTERY_C21N2018, -- cgit v1.2.1 From aedbc37fb7b942ffeebb5c1d74f3336259224c1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:52 -0600 Subject: board/phaser/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife84d64741be063951861382517f2e6a9c32385d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728820 Reviewed-by: Jeremy Bettis --- board/phaser/board.c | 90 +++++++++++++++++++++++++--------------------------- 1 file changed, 43 insertions(+), 47 deletions(-) diff --git a/board/phaser/board.c b/board/phaser/board.c index 6259ad3cd7..92c5f9f84b 100644 --- a/board/phaser/board.c +++ b/board/phaser/board.c @@ -34,11 +34,11 @@ #include "util.h" #include "battery_smart.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; static bool support_syv_ppc; @@ -85,31 +85,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -119,11 +119,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate lid and base sensor into standard reference frame */ -const mat33_fp_t standard_rot_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct stprivate_data g_lis2dh_data; @@ -212,8 +210,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); static int board_is_convertible(void) { - return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 || \ - sku_id == 255; + return sku_id == 2 || sku_id == 3 || sku_id == 4 || sku_id == 5 || + sku_id == 255; } static void board_update_sensor_config_from_sku(void) @@ -331,7 +329,7 @@ void board_hibernate_late(void) } /* Clear all pending IRQ otherwise wfi will have no affect */ - for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++) + for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++) task_clear_pending_irq(i); __enter_hibernate_in_psl(); @@ -358,11 +356,11 @@ int board_is_lid_angle_tablet_mode(void) } /* Battery functions */ -#define SB_OPTIONALMFG_FUNCTION2 0x3e +#define SB_OPTIONALMFG_FUNCTION2 0x3e /* Optional mfg function2 */ -#define SMART_QUICK_CHARGE (1<<12) +#define SMART_QUICK_CHARGE (1 << 12) /* Quick charge support */ -#define MODE_QUICK_CHARGE_SUPPORT (1<<4) +#define MODE_QUICK_CHARGE_SUPPORT (1 << 4) static void sb_quick_charge_mode(int enable) { @@ -411,15 +409,15 @@ void board_overcurrent_event(int port, int is_overcurrented) } static const struct ppc_config_t ppc_syv682x_port0 = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static const struct ppc_config_t ppc_syv682x_port1 = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static void board_setup_ppc(void) @@ -427,12 +425,10 @@ static void board_setup_ppc(void) if (!support_syv_ppc) return; - memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], - &ppc_syv682x_port0, - sizeof(struct ppc_config_t)); - memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], - &ppc_syv682x_port1, - sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0, + sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1, + sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH); gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH); -- cgit v1.2.1 From e02da337db52954766b49db78df86698652a558d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:57 -0600 Subject: zephyr/shim/src/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc5c4beb36b9e7fc5ba9dfc06873b99cdcfbd162 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730892 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/gpio.c | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/zephyr/shim/src/gpio.c b/zephyr/shim/src/gpio.c index eb395813c8..e0415a3961 100644 --- a/zephyr/shim/src/gpio.c +++ b/zephyr/shim/src/gpio.c @@ -41,19 +41,19 @@ struct gpio_config { * whereas the standard macros assume that only 8 bits of initial flags * will be needed. */ -#define OUR_DT_SPEC(id) \ - { \ - .port = DEVICE_DT_GET(DT_GPIO_CTLR(id, gpios)), \ - .pin = DT_GPIO_PIN(id, gpios), \ - .dt_flags = 0xFF & (DT_GPIO_FLAGS(id, gpios)), \ +#define OUR_DT_SPEC(id) \ + { \ + .port = DEVICE_DT_GET(DT_GPIO_CTLR(id, gpios)), \ + .pin = DT_GPIO_PIN(id, gpios), \ + .dt_flags = 0xFF & (DT_GPIO_FLAGS(id, gpios)), \ } -#define GPIO_CONFIG(id) \ - { \ - .spec = OUR_DT_SPEC(id), \ - .name = DT_NODE_FULL_NAME(id), \ - .init_flags = DT_GPIO_FLAGS(id, gpios), \ - .no_auto_init = DT_PROP(id, no_auto_init), \ +#define GPIO_CONFIG(id) \ + { \ + .spec = OUR_DT_SPEC(id), \ + .name = DT_NODE_FULL_NAME(id), \ + .init_flags = DT_GPIO_FLAGS(id, gpios), \ + .no_auto_init = DT_PROP(id, no_auto_init), \ }, static const struct gpio_config configs[] = { #if DT_NODE_EXISTS(DT_PATH(named_gpios)) @@ -73,9 +73,9 @@ static const struct gpio_config configs[] = { * point directly into the table by exposing the gpio_config struct. */ -#define GPIO_PTRS(id) const struct gpio_dt_spec * const \ - GPIO_DT_NAME(GPIO_SIGNAL(id)) = \ - &configs[GPIO_SIGNAL(id)].spec; +#define GPIO_PTRS(id) \ + const struct gpio_dt_spec *const GPIO_DT_NAME(GPIO_SIGNAL(id)) = \ + &configs[GPIO_SIGNAL(id)].spec; #if DT_NODE_EXISTS(DT_PATH(named_gpios)) DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_PTRS) @@ -137,8 +137,7 @@ void gpio_set_level(enum gpio_signal signal, int value) return; int rv = gpio_pin_set_raw(configs[signal].spec.port, - configs[signal].spec.pin, - value); + configs[signal].spec.pin, value); if (rv < 0) { LOG_ERR("Cannot write %s (%d)", configs[signal].name, rv); @@ -167,15 +166,15 @@ int gpio_or_ioex_get_level(int signal, int *value) #define GPIO_CONVERSION_SAME_BITS \ (GPIO_OPEN_DRAIN | GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_VOLTAGE_1P8 | \ GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | \ - GPIO_OUTPUT_INIT_HIGH) + GPIO_OUTPUT_INIT_HIGH) #define FLAGS_HANDLED_FROM_ZEPHYR \ (GPIO_CONVERSION_SAME_BITS | GPIO_INT_ENABLE | GPIO_INT_EDGE | \ - GPIO_INT_HIGH_1 | GPIO_INT_LOW_0) + GPIO_INT_HIGH_1 | GPIO_INT_LOW_0) #define FLAGS_HANDLED_TO_ZEPHYR \ (GPIO_CONVERSION_SAME_BITS | GPIO_INT_F_RISING | GPIO_INT_F_FALLING | \ - GPIO_INT_F_LOW | GPIO_INT_F_HIGH) + GPIO_INT_F_LOW | GPIO_INT_F_HIGH) int convert_from_zephyr_flags(const gpio_flags_t zephyr) { @@ -219,11 +218,11 @@ gpio_flags_t convert_to_zephyr_flags(int ec_flags) } if (ec_flags & GPIO_INT_F_RISING) - zephyr_flags |= GPIO_INT_ENABLE - | GPIO_INT_EDGE | GPIO_INT_HIGH_1; + zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE | + GPIO_INT_HIGH_1; if (ec_flags & GPIO_INT_F_FALLING) - zephyr_flags |= GPIO_INT_ENABLE - | GPIO_INT_EDGE | GPIO_INT_LOW_0; + zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_EDGE | + GPIO_INT_LOW_0; if (ec_flags & GPIO_INT_F_LOW) zephyr_flags |= GPIO_INT_ENABLE | GPIO_INT_LOW_0; if (ec_flags & GPIO_INT_F_HIGH) @@ -276,7 +275,7 @@ static int init_gpios(const struct device *unused) */ if (is_sys_jumped && (flags & GPIO_OUTPUT)) { flags &= - ~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH); + ~(GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH); } rv = gpio_pin_configure_dt(&configs[i].spec, flags); -- cgit v1.2.1 From 3592aafc222662f6411a7b217fe436f228e9ecb0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:09 -0600 Subject: test/legacy_nvmem_dump.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibbd4b220e80740c9faa381d3f25bab716852d6dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730511 Reviewed-by: Jeremy Bettis --- test/legacy_nvmem_dump.h | 88 ++++++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/test/legacy_nvmem_dump.h b/test/legacy_nvmem_dump.h index 6816673c23..25e69fe716 100644 --- a/test/legacy_nvmem_dump.h +++ b/test/legacy_nvmem_dump.h @@ -12,10 +12,10 @@ * This binary dump is placed in a separate file not to free up the test file * using it. */ - 0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f, - 0x36, 0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, +0x00, 0x65, 0x8e, 0x10, 0x80, 0xca, 0x52, 0x1e, 0x95, 0x81, 0x12, 0x4f, 0x36, + 0x78, 0x9a, 0x34, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xff, 0xff, 0x00, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -32,12 +32,12 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70, - 0x61, 0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00, - 0x03, 0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00, - 0x9b, 0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0d, 0x00, 0x63, 0x72, 0x6f, 0x73, 0x2d, 0x70, 0x61, + 0x73, 0x73, 0x77, 0x6f, 0x72, 0x64, 0x00, 0xe1, 0xac, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x37, 0x01, 0x00, 0x03, + 0x00, 0x00, 0x00, 0xbd, 0xfe, 0xff, 0xff, 0x85, 0xfc, 0x05, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xb0, 0xde, 0x01, 0x00, 0xb4, 0xde, 0x01, 0x00, 0x9b, + 0x0f, 0x06, 0x00, 0xbc, 0xde, 0x01, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -48,34 +48,33 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x5b, 0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3, - 0xdd, 0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67, - 0x5c, 0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca, - 0x7d, 0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec, - 0x1a, 0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20, - 0x88, 0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c, - 0xad, 0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09, - 0xd1, 0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1, - 0x66, 0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc, - 0x1b, 0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d, - 0x29, 0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32, - 0x35, 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x5b, + 0x15, 0xa1, 0x0a, 0x05, 0x12, 0x58, 0x84, 0xbf, 0xf6, 0xc9, 0xf3, 0xdd, + 0xb7, 0x26, 0xce, 0x56, 0x9e, 0x5f, 0x7a, 0xa8, 0xd4, 0x8a, 0x67, 0x5c, + 0x26, 0x35, 0x0e, 0xb2, 0x13, 0x2c, 0x79, 0x20, 0x00, 0x26, 0xca, 0x7d, + 0xb8, 0x1a, 0x1f, 0x0b, 0x5c, 0x0a, 0xf3, 0xb5, 0xe2, 0x6a, 0xec, 0x1a, + 0x0d, 0x90, 0x8b, 0x92, 0x3c, 0x07, 0xb0, 0x41, 0xb0, 0x27, 0x20, 0x88, + 0x33, 0xfe, 0x5c, 0xf2, 0x7b, 0x20, 0x00, 0x9e, 0xb7, 0xa2, 0x4c, 0xad, + 0x6c, 0xc0, 0x92, 0x92, 0xef, 0xbc, 0x56, 0x65, 0x47, 0xf9, 0x09, 0xd1, + 0xc4, 0xbc, 0x36, 0xe8, 0x3a, 0xc2, 0x8a, 0x11, 0x3a, 0xca, 0xe1, 0x66, + 0xd7, 0x85, 0x57, 0x20, 0x00, 0x0c, 0x6d, 0xc7, 0x61, 0x92, 0xfc, 0x1b, + 0x24, 0x02, 0xc1, 0x92, 0x0e, 0xf4, 0xa1, 0x75, 0xbe, 0xb1, 0x3d, 0x29, + 0xfe, 0x1e, 0xe2, 0x65, 0xf5, 0x25, 0xae, 0xaf, 0xfe, 0x73, 0x32, 0x35, + 0x75, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x52, 0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f, - 0xd3, 0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38, - 0xc3, 0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x52, + 0x01, 0x7b, 0x53, 0xc5, 0x95, 0xa0, 0x3a, 0x07, 0xd5, 0x62, 0x7f, 0xd3, + 0x9c, 0x85, 0xaa, 0xfc, 0x56, 0xa0, 0xfa, 0x3a, 0xe8, 0x17, 0x38, 0xc3, + 0x59, 0x65, 0xbe, 0x75, 0x1b, 0xdc, 0xdc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd, - 0x10, 0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7, - 0xfb, 0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16, - 0xd5, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x84, 0xe7, 0x7e, 0x46, 0xfe, 0xbd, 0x10, + 0xdd, 0x5b, 0x09, 0xb2, 0xe2, 0xb1, 0x3f, 0xbf, 0x9a, 0xf3, 0xd7, 0xfb, + 0xf7, 0x28, 0xbb, 0x24, 0x10, 0xa3, 0xf3, 0x18, 0xa4, 0xa2, 0x16, 0xd5, + 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -86,15 +85,16 @@ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00, - 0x03, 0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00, - 0x03, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, - 0x00, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x00, 0x00, 0x00, 0x04, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0b, 0x00, 0x03, + 0xff, 0xff, 0xff, 0x0c, 0x00, 0x03, 0xff, 0xff, 0xff, 0x0d, 0x00, 0x03, + 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x00, + 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x00, 0x00, 0x01, 0x00, + 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -113,7 +113,7 @@ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, /* Manually added nonempty pcr. Array 0, index 0 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x02, 0x03, 0x04, 0x05, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -- cgit v1.2.1 From dfbf23fb8c5cd9871da31171f4507809fe2fb8b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:29 -0600 Subject: chip/max32660/i2c_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c12289b81face6b5012ceda1013012bb4b5f198 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729233 Reviewed-by: Jeremy Bettis --- chip/max32660/i2c_regs.h | 76 ++++++++++++++++++++++++------------------------ 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h index f6d2a6c0db..e57f3b2fa3 100644 --- a/chip/max32660/i2c_regs.h +++ b/chip/max32660/i2c_regs.h @@ -34,50 +34,50 @@ * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers. */ typedef struct { - __IO uint32_t ctrl; /* 0x00: I2C CTRL Register */ - __IO uint32_t status; /* 0x04: I2C STATUS Register */ - __IO uint32_t int_fl0; /* 0x08: I2C INT_FL0 Register */ - __IO uint32_t int_en0; /* 0x0C: I2C INT_EN0 Register */ - __IO uint32_t int_fl1; /* 0x10: I2C INT_FL1 Register */ - __IO uint32_t int_en1; /* 0x14: I2C INT_EN1 Register */ - __IO uint32_t fifo_len; /* 0x18: I2C FIFO_LEN Register */ - __IO uint32_t rx_ctrl0; /* 0x1C: I2C RX_CTRL0 Register */ - __IO uint32_t rx_ctrl1; /* 0x20: I2C RX_CTRL1 Register */ - __IO uint32_t tx_ctrl0; /* 0x24: I2C TX_CTRL0 Register */ - __IO uint32_t tx_ctrl1; /* 0x28: I2C TX_CTRL1 Register */ - __IO uint32_t fifo; /* 0x2C: I2C FIFO Register */ - __IO uint32_t controller_ctrl; /* 0x30: I2C CONTROLLER_CTRL Register */ - __IO uint32_t clk_lo; /* 0x34: I2C CLK_LO Register */ - __IO uint32_t clk_hi; /* 0x38: I2C CLK_HI Register */ - __IO uint32_t hs_clk; /* 0x3C: I2C HS_CLK Register */ - __IO uint32_t timeout; /* 0x40: I2C TIMEOUT Register */ - __IO uint32_t target_addr; /* 0x44: I2C TARGET_ADDR Register */ - __IO uint32_t dma; /* 0x48: I2C DMA Register */ + __IO uint32_t ctrl; /* 0x00: I2C CTRL Register */ + __IO uint32_t status; /* 0x04: I2C STATUS Register */ + __IO uint32_t int_fl0; /* 0x08: I2C INT_FL0 Register */ + __IO uint32_t int_en0; /* 0x0C: I2C INT_EN0 Register */ + __IO uint32_t int_fl1; /* 0x10: I2C INT_FL1 Register */ + __IO uint32_t int_en1; /* 0x14: I2C INT_EN1 Register */ + __IO uint32_t fifo_len; /* 0x18: I2C FIFO_LEN Register */ + __IO uint32_t rx_ctrl0; /* 0x1C: I2C RX_CTRL0 Register */ + __IO uint32_t rx_ctrl1; /* 0x20: I2C RX_CTRL1 Register */ + __IO uint32_t tx_ctrl0; /* 0x24: I2C TX_CTRL0 Register */ + __IO uint32_t tx_ctrl1; /* 0x28: I2C TX_CTRL1 Register */ + __IO uint32_t fifo; /* 0x2C: I2C FIFO Register */ + __IO uint32_t controller_ctrl; /* 0x30: I2C CONTROLLER_CTRL Register */ + __IO uint32_t clk_lo; /* 0x34: I2C CLK_LO Register */ + __IO uint32_t clk_hi; /* 0x38: I2C CLK_HI Register */ + __IO uint32_t hs_clk; /* 0x3C: I2C HS_CLK Register */ + __IO uint32_t timeout; /* 0x40: I2C TIMEOUT Register */ + __IO uint32_t target_addr; /* 0x44: I2C TARGET_ADDR Register */ + __IO uint32_t dma; /* 0x48: I2C DMA Register */ } mxc_i2c_regs_t; /* Register offsets for module I2C */ /* * I2C Peripheral Register Offsets from the I2C Base Peripheral Address. */ -#define MXC_R_I2C_CTRL 0x00000000UL -#define MXC_R_I2C_STATUS 0x00000004UL -#define MXC_R_I2C_INT_FL0 0x00000008UL -#define MXC_R_I2C_INT_EN0 0x0000000CUL -#define MXC_R_I2C_INT_FL1 0x00000010UL -#define MXC_R_I2C_INT_EN1 0x00000014UL -#define MXC_R_I2C_FIFO_LEN 0x00000018UL -#define MXC_R_I2C_RX_CTRL0 0x0000001CUL -#define MXC_R_I2C_RX_CTRL1 0x00000020UL -#define MXC_R_I2C_TX_CTRL0 0x00000024UL -#define MXC_R_I2C_TX_CTRL1 0x00000028UL -#define MXC_R_I2C_FIFO 0x0000002CUL -#define MXC_R_I2C_CONTROLLER_CTRL 0x00000030UL -#define MXC_R_I2C_CLK_LO 0x00000034UL -#define MXC_R_I2C_CLK_HI 0x00000038UL -#define MXC_R_I2C_HS_CLK 0x0000003CUL -#define MXC_R_I2C_TIMEOUT 0x00000040UL -#define MXC_R_I2C_TARGET_ADDR 0x00000044UL -#define MXC_R_I2C_DMA 0x00000048UL +#define MXC_R_I2C_CTRL 0x00000000UL +#define MXC_R_I2C_STATUS 0x00000004UL +#define MXC_R_I2C_INT_FL0 0x00000008UL +#define MXC_R_I2C_INT_EN0 0x0000000CUL +#define MXC_R_I2C_INT_FL1 0x00000010UL +#define MXC_R_I2C_INT_EN1 0x00000014UL +#define MXC_R_I2C_FIFO_LEN 0x00000018UL +#define MXC_R_I2C_RX_CTRL0 0x0000001CUL +#define MXC_R_I2C_RX_CTRL1 0x00000020UL +#define MXC_R_I2C_TX_CTRL0 0x00000024UL +#define MXC_R_I2C_TX_CTRL1 0x00000028UL +#define MXC_R_I2C_FIFO 0x0000002CUL +#define MXC_R_I2C_CONTROLLER_CTRL 0x00000030UL +#define MXC_R_I2C_CLK_LO 0x00000034UL +#define MXC_R_I2C_CLK_HI 0x00000038UL +#define MXC_R_I2C_HS_CLK 0x0000003CUL +#define MXC_R_I2C_TIMEOUT 0x00000040UL +#define MXC_R_I2C_TARGET_ADDR 0x00000044UL +#define MXC_R_I2C_DMA 0x00000048UL /** * Control Register0. -- cgit v1.2.1 From 658b879da45718b13c7ba3fdfb017f319ad4a064 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:39 -0600 Subject: board/rammus/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c9bd3f02e754c3699b934def33ce4293b79a0ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728875 Reviewed-by: Jeremy Bettis --- board/rammus/board.c | 147 +++++++++++++++++++++++---------------------------- 1 file changed, 66 insertions(+), 81 deletions(-) diff --git a/board/rammus/board.c b/board/rammus/board.c index a27828694d..6fcae701db 100644 --- a/board/rammus/board.c +++ b/board/rammus/board.c @@ -59,11 +59,11 @@ #include "util.h" #include "espi.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) -#define USB_PD_PORT_PS8751 1 -#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 static void tcpc_alert_event(enum gpio_signal signal) { @@ -130,53 +130,44 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (10x voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18, - ADC_READ_MAX+1, 0}, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "i2c_0_0", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "i2c_0_1", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "i2c_1", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "i2c_2", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "i2c_3", - .port = NPCX_I2C_PORT3, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "i2c_0_0", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "i2c_0_1", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "i2c_1", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "i2c_2", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "i2c_3", + .port = NPCX_I2C_PORT3, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -262,7 +253,7 @@ static void ps8751_i2c_remap(void) uint32_t board_version; if (cbi_get_board_version(&board_version) != EC_SUCCESS || - board_version > 1) + board_version > 1) return; /* * Due to b/118063849, we separate the ps8751 and anx3447 to @@ -293,9 +284,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { @@ -315,17 +306,17 @@ uint16_t tcpc_get_alert_status(void) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* These BD99992GW temp sensors are only readable in S0 */ - {"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, - {"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM3}, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, + { "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -341,8 +332,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) != + EC_SUCCESS) return; if (!(vrfault & BIT(4))) @@ -433,8 +424,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void) i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a); } -__override void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__override void power_board_handle_host_sleep_event(enum host_sleep_event state) { if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) board_pmic_enable_slp_s0_vr_decay(); @@ -508,7 +498,7 @@ static void usb_charge_mode_init(void) * inhibit_charging_in_suspend. */ usb_charge_set_mode(0, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE, - USB_DISALLOW_SUSPEND_CHARGE); + USB_DISALLOW_SUSPEND_CHARGE); } DECLARE_HOOK(HOOK_INIT, usb_charge_mode_init, HOOK_PRIO_DEFAULT + 1); @@ -552,10 +542,12 @@ int board_set_active_charge_port(int charge_port) } else { /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_EC_L : - GPIO_EN_USB_C1_CHARGE_EC_L, 1); + GPIO_EN_USB_C1_CHARGE_EC_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_EC_L : - GPIO_EN_USB_C0_CHARGE_EC_L, 0); + GPIO_EN_USB_C0_CHARGE_EC_L, + 0); } return EC_SUCCESS; @@ -569,8 +561,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 96% negotiated limit, @@ -578,8 +570,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 96 / 100; charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_hibernate(void) @@ -625,23 +616,17 @@ static struct accelgyro_saved_data_t g_bma255_data; static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0 }, - { 0, FLOAT_TO_FP(-1), 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref_icm = { - { 0, FLOAT_TO_FP(1), 0 }, - { FLOAT_TO_FP(1), 0, 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t base_standard_ref_icm = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(1), 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t base_accel_icm = { .name = "Base Accel", -- cgit v1.2.1 From ddfe5c1e469327498d4593636d1dc5472dd0ed32 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:59 -0600 Subject: fuzz/pchg_fuzz.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf95eadbb1d8ed2b18166ef3be1a6f765c4bd4f9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730194 Reviewed-by: Jeremy Bettis --- fuzz/pchg_fuzz.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/fuzz/pchg_fuzz.c b/fuzz/pchg_fuzz.c index 97dbca74c4..eced90bb5e 100644 --- a/fuzz/pchg_fuzz.c +++ b/fuzz/pchg_fuzz.c @@ -40,15 +40,15 @@ static pthread_cond_t done_cond; static pthread_mutex_t lock; #define MAX_MESSAGES 8 -#define MAX_MESSAGE_SIZE (sizeof(struct ctn730_msg) \ - + member_size(struct ctn730_msg, length) * 256) +#define MAX_MESSAGE_SIZE \ + (sizeof(struct ctn730_msg) + \ + member_size(struct ctn730_msg, length) * 256) static uint8_t input[MAX_MESSAGE_SIZE * MAX_MESSAGES]; static uint8_t *head, *tail; static bool data_available; -int pchg_i2c_xfer(int port, uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int pchg_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { if (port != I2C_PORT_WLC || addr_flags != CTN730_I2C_ADDR) return EC_ERROR_INVAL; @@ -92,7 +92,6 @@ void irq_task(int argc, char **argv) pthread_cond_signal(&done_cond); pthread_mutex_unlock(&lock); } - } void run_test(int argc, char **argv) -- cgit v1.2.1 From a731efc9f7987ca467f30e3f3f7fee01390524c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:23 -0600 Subject: zephyr/test/tasks/shimmed_test_tasks.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I299e3673786c9dcc2e34f60bbca19d74f822f9eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730963 Reviewed-by: Jeremy Bettis --- zephyr/test/tasks/shimmed_test_tasks.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/test/tasks/shimmed_test_tasks.h b/zephyr/test/tasks/shimmed_test_tasks.h index c040ed1bad..f35e9dd312 100644 --- a/zephyr/test/tasks/shimmed_test_tasks.h +++ b/zephyr/test/tasks/shimmed_test_tasks.h @@ -14,7 +14,7 @@ #define HAS_TASK_TASK_3 1 /* Highest priority on bottom same as in platform/ec */ -#define CROS_EC_TASK_LIST \ +#define CROS_EC_TASK_LIST \ CROS_EC_TASK(TASK_1, task1_entry, 0, 512, 2) \ CROS_EC_TASK(TASK_2, task2_entry, 0, 512, 1) \ CROS_EC_TASK(TASK_3, task3_entry, 0, 512, 0) -- cgit v1.2.1 From 88ce47819e8504d0fbd7ea6222dcefde11384ed2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:14 -0600 Subject: util/ectool_i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I992a5c72b04daa0d9660fdef22c4de0aa22243f3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730619 Reviewed-by: Jeremy Bettis --- util/ectool_i2c.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/util/ectool_i2c.c b/util/ectool_i2c.c index 97e47e6e85..30c57047ba 100644 --- a/util/ectool_i2c.c +++ b/util/ectool_i2c.c @@ -20,8 +20,7 @@ int cmd_i2c_protect(int argc, char *argv[]) int rv; if (argc != 2 && (argc != 3 || strcmp(argv[2], "status"))) { - fprintf(stderr, "Usage: %s [status]\n", - argv[0]); + fprintf(stderr, "Usage: %s [status]\n", argv[0]); return -1; } @@ -56,9 +55,8 @@ int cmd_i2c_protect(int argc, char *argv[]) return 0; } -static int do_i2c_xfer(unsigned int port, unsigned int addr, - uint8_t *write_buf, int write_len, - uint8_t **read_buf, int read_len) +static int do_i2c_xfer(unsigned int port, unsigned int addr, uint8_t *write_buf, + int write_len, uint8_t **read_buf, int read_len) { struct ec_params_i2c_passthru *p = (struct ec_params_i2c_passthru *)ec_outbuf; @@ -96,8 +94,8 @@ static int do_i2c_xfer(unsigned int port, unsigned int addr, msg->len = read_len; } - rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, - r, sizeof(*r) + read_len); + rv = ec_command(EC_CMD_I2C_PASSTHRU, 0, p, size + write_len, r, + sizeof(*r) + read_len); if (rv < 0) return rv; @@ -132,9 +130,7 @@ static void cmd_i2c_help(void) " offset to read from or write to\n" " data to write\n" " number of bytes to read\n" - " [bytes ...] data to write\n" - ); - + " [bytes ...] data to write\n"); } int cmd_i2c_read(int argc, char *argv[]) @@ -184,8 +180,8 @@ int cmd_i2c_read(int argc, char *argv[]) if (rv < 0) return rv; - printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n", - port, addr8, write_buf[0], *(uint16_t *)read_buf); + printf("Read from I2C port %d at 0x%x offset 0x%x = 0x%x\n", port, + addr8, write_buf[0], *(uint16_t *)read_buf); return 0; } @@ -324,7 +320,7 @@ int cmd_i2c_xfer(int argc, char *argv[]) static int i2c_get(int port) { - struct ec_params_i2c_control p; + struct ec_params_i2c_control p; struct ec_response_i2c_control r; uint16_t speed_khz; int rv; @@ -348,7 +344,7 @@ static int i2c_get(int port) static int i2c_set(int port, int new_speed_khz) { - struct ec_params_i2c_control p; + struct ec_params_i2c_control p; struct ec_response_i2c_control r; uint16_t old_speed_khz; int rv; @@ -374,8 +370,7 @@ static int i2c_set(int port, int new_speed_khz) printf("Port %d speed set to %d kHz\n", port, new_speed_khz); } else { printf("Port %d speed changed from %u kHz to %d kHz\n", port, - old_speed_khz, - new_speed_khz); + old_speed_khz, new_speed_khz); } return 0; @@ -403,7 +398,7 @@ int cmd_i2c_speed(int argc, char *argv[]) speed = strtol(argv[2], &e, 0); if (e && *e) { fprintf(stderr, "Bad speed. " - "Typical speeds are one of {100,400,1000}.\n"); + "Typical speeds are one of {100,400,1000}.\n"); return -1; } -- cgit v1.2.1 From 4d0f5281badfe409dc31fdd868bcec15c1fa275c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:38 -0600 Subject: board/kuldax/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I75b0f3bf366893ee6e5aa5a1715db7691ac370ff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728607 Reviewed-by: Jeremy Bettis --- board/kuldax/led.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/kuldax/led.c b/board/kuldax/led.c index c5e74d29c2..ada7517d1c 100644 --- a/board/kuldax/led.c +++ b/board/kuldax/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* * When pulsing is enabled, brightness is incremented by every @@ -231,8 +231,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|green|off|alert|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -250,10 +249,10 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness) else return set_color(id, LED_OFF, 0); } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - /* Blink alert if insufficient power per system_can_boot_ap(). */ + /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = (charge_ma * charge_mv) < (CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000); -- cgit v1.2.1 From e9698fffb47586ada7984672068a3b27107708f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:07 -0600 Subject: zephyr/test/drivers/src/usb_pd_host_cmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia2f5ab1b900111bac1a1b99fa08b7de9ad1a585a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730981 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/usb_pd_host_cmd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/test/drivers/src/usb_pd_host_cmd.c b/zephyr/test/drivers/src/usb_pd_host_cmd.c index 5eb589043c..bd421e7537 100644 --- a/zephyr/test/drivers/src/usb_pd_host_cmd.c +++ b/zephyr/test/drivers/src/usb_pd_host_cmd.c @@ -14,8 +14,7 @@ ZTEST_USER(usb_pd_host_cmd, test_host_command_hc_pd_ports) { struct ec_response_usb_pd_ports response; struct host_cmd_handler_args args = - BUILD_HOST_COMMAND_RESPONSE(EC_CMD_USB_PD_PORTS, 0, - response); + BUILD_HOST_COMMAND_RESPONSE(EC_CMD_USB_PD_PORTS, 0, response); zassert_ok(host_command_process(&args), NULL); zassert_ok(args.result, NULL); -- cgit v1.2.1 From 6db90c153804e8096acfd8ba102afd1b53fdb410 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:12 -0600 Subject: board/madoo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib4691ec91a9a253bcf175d495be0fdf625db9d13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728640 Reviewed-by: Jeremy Bettis --- board/madoo/led.c | 74 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/board/madoo/led.c b/board/madoo/led.c index aef7b0e425..1811b996f2 100644 --- a/board/madoo/led.c +++ b/board/madoo/led.c @@ -14,8 +14,8 @@ #include "hooks.h" #include "system.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -23,34 +23,40 @@ __override const int led_charge_lvl_2 = 100; /* madoo: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - /* STATE_DISCHARGE_S3 will changed if sku is clamshells */ - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + /* STATE_DISCHARGE_S3 will changed if sku is clamshells */ + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -77,8 +83,8 @@ int battery_safety_check(void) return false; /* turn off LED due to a safety fault */ - rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return false; /* @@ -111,7 +117,7 @@ __override void led_set_color_battery(enum ec_led_colors color) gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL); } else if (charge_manager_get_active_charge_port() == 1 || - system_get_board_version() < 3) { + system_get_board_version() < 3) { gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_ON_LVL); gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL); } else if (charge_manager_get_active_charge_port() == 0) { @@ -125,11 +131,11 @@ __override void led_set_color_battery(enum ec_led_colors color) gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL); } else if (charge_get_state() == PWR_STATE_ERROR && - system_get_board_version() >= 3) { + system_get_board_version() >= 3) { gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL); } else if (charge_manager_get_active_charge_port() == 1 || - system_get_board_version() < 3) { + system_get_board_version() < 3) { gpio_set_level(GPIO_BAT_LED_WHITE_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_AMBER_L, LED_ON_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_OFF_LVL); @@ -137,7 +143,7 @@ __override void led_set_color_battery(enum ec_led_colors color) gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL); } else if (charge_get_percent() < - CONFIG_LED_ONOFF_STATES_BAT_LOW) { + CONFIG_LED_ONOFF_STATES_BAT_LOW) { gpio_set_level(GPIO_EC_CHG_LED_R_W, LED_OFF_LVL); gpio_set_level(GPIO_EC_CHG_LED_R_Y, LED_ON_LVL); } -- cgit v1.2.1 From 8c24952a2edb2b910072254c33e005331de441ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:57 -0600 Subject: board/asurada/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I364a152adb2ca23c4a024150385116c55d618d88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728010 Reviewed-by: Jeremy Bettis --- board/asurada/board.c | 70 ++++++++++++++++++++++----------------------------- 1 file changed, 30 insertions(+), 40 deletions(-) diff --git a/board/asurada/board.c b/board/asurada/board.c index 83c95722ef..60cd12e10b 100644 --- a/board/asurada/board.c +++ b/board/asurada/board.c @@ -66,17 +66,15 @@ static enum base_accelgyro_type base_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ /* for rev 0 */ static const mat33_fp_t base_standard_ref_rev0 = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1)}, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; static void update_rotation_matrix(void) { - motion_sensors[BASE_ACCEL].rot_standard_ref = - &base_standard_ref_rev0; - motion_sensors[BASE_GYRO].rot_standard_ref = - &base_standard_ref_rev0; + motion_sensors[BASE_ACCEL].rot_standard_ref = &base_standard_ref_rev0; + motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref_rev0; } DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2); @@ -138,9 +136,9 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { /* Matrix to rotate accelerometer into standard reference frame */ /* for Hayato */ static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0 , 0}, - {0, 0, FLOAT_TO_FP(1)}, + { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) }, }; static void update_rotation_matrix(void) @@ -151,8 +149,7 @@ static void update_rotation_matrix(void) if (board_get_version() >= 2) { motion_sensors[BASE_ACCEL].rot_standard_ref = &base_standard_ref; - motion_sensors[BASE_GYRO].rot_standard_ref = - &base_standard_ref; + motion_sensors[BASE_GYRO].rot_standard_ref = &base_standard_ref; } } DECLARE_HOOK(HOOK_INIT, update_rotation_matrix, HOOK_PRIO_INIT_ADC + 2); @@ -340,28 +337,27 @@ static void board_detect_motionsense(void) if (val == ICM426XX_CHIP_ICM40608) { motion_sensors[BASE_ACCEL] = icm426xx_base_accel; motion_sensors[BASE_GYRO] = icm426xx_base_gyro; - base_accelgyro_config = BASE_GYRO_ICM426XX; + base_accelgyro_config = BASE_GYRO_ICM426XX; ccprints("Base Accelgyro: ICM426XX"); } else { base_accelgyro_config = BASE_GYRO_BMI160; ccprints("Base Accelgyro: BMI160"); } } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsense, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_INIT, board_detect_motionsense, HOOK_PRIO_DEFAULT); /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0}, - {"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1}, - {"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2}, + { "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 }, + { "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, + { "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, /* AMON/BMON gain = 17.97 */ - {"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH3}, - {"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5}, - {"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6}, + { "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH3 }, + { "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 }, + { "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -374,24 +370,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); * number of pwm channel greater than three. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_LED1] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, - [PWM_CH_LED2] = { - .channel = 1, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, - [PWM_CH_LED3] = { - .channel = 2, - .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, - .freq_hz = 324, /* maximum supported frequency */ - .pcfsr_sel = PWM_PRESCALER_C4 - }, + [PWM_CH_LED1] = { .channel = 0, + .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, + .freq_hz = 324, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, + [PWM_CH_LED2] = { .channel = 1, + .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, + .freq_hz = 324, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, + [PWM_CH_LED3] = { .channel = 2, + .flags = PWM_CONFIG_DSLEEP | PWM_CONFIG_ACTIVE_LOW, + .freq_hz = 324, /* maximum supported frequency */ + .pcfsr_sel = PWM_PRESCALER_C4 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From e32148799db07ebe57e9506d08750eb4bf651b55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:35 -0600 Subject: include/mkbp_fifo.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59d095cff3f9da732511e629f86147d14989223b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730355 Reviewed-by: Jeremy Bettis --- include/mkbp_fifo.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/mkbp_fifo.h b/include/mkbp_fifo.h index 347f94e2a7..7afb016614 100644 --- a/include/mkbp_fifo.h +++ b/include/mkbp_fifo.h @@ -11,10 +11,8 @@ #include "common.h" #include "ec_commands.h" - #define FIFO_DEPTH 16 - /** * Update the "soft" FIFO depth (size). The new depth should be less or * equal FIFO_DEPTH -- cgit v1.2.1 From c7b8fb103be23a2134db7de1bcba1755e1f0906f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:09 -0600 Subject: baseboard/volteer/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I89140df915fb0b7ca10432f7a67e754fe05d6fae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727946 Reviewed-by: Jeremy Bettis --- baseboard/volteer/baseboard.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c index 6b3ad33a35..a7940b2603 100644 --- a/baseboard/volteer/baseboard.c +++ b/baseboard/volteer/baseboard.c @@ -23,8 +23,8 @@ #include "usbc_config.h" #endif -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /******************************************************************************/ /* ADC configuration */ @@ -73,21 +73,21 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CHARGER}, - [TEMP_SENSOR_2_PP3300_REGULATOR] = {.name = "PP3300 Regulator", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR}, - [TEMP_SENSOR_3_DDR_SOC] = {.name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_DDR_SOC}, - [TEMP_SENSOR_4_FAN] = {.name = "Fan", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_FAN}, + [TEMP_SENSOR_1_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_CHARGER }, + [TEMP_SENSOR_2_PP3300_REGULATOR] = { .name = "PP3300 Regulator", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_PP3300_REGULATOR }, + [TEMP_SENSOR_3_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_DDR_SOC }, + [TEMP_SENSOR_4_FAN] = { .name = "Fan", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 9a0aa1ee2078e871edd4e304bb33fc1919c7de80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:50 -0600 Subject: baseboard/intelrvp/adlrvp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I877ea67464318f16e0e3a65d9f1db2cdffcd24c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727892 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/adlrvp.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c index 4d97418d23..33b022b585 100644 --- a/baseboard/intelrvp/adlrvp.c +++ b/baseboard/intelrvp/adlrvp.c @@ -26,8 +26,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) /* TCPC AIC GPIO Configuration */ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { @@ -253,8 +253,8 @@ void board_overcurrent_event(int port, int is_overcurrented) { /* Port 0 & 1 and 2 & 3 share same line for over current indication */ #if defined(HAS_TASK_PD_C2) - enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? - IOEX_USB_C0_C1_OC : IOEX_USB_C2_C3_OC; + enum ioex_signal oc_signal = port < TYPE_C_PORT_2 ? IOEX_USB_C0_C1_OC : + IOEX_USB_C2_C3_OC; #else enum ioex_signal oc_signal = IOEX_USB_C0_C1_OC; #endif @@ -340,11 +340,11 @@ void set_charger_system_voltage(void) * on AC or AC+battery */ if (extpower_is_present() && battery_is_present()) { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_min); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_min); } else { - bq25710_set_min_system_voltage(CHARGER_SOLO, - battery_get_info()->voltage_max); + bq25710_set_min_system_voltage( + CHARGER_SOLO, battery_get_info()->voltage_max); } break; @@ -353,8 +353,7 @@ void set_charger_system_voltage(void) break; } } -DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_AC_CHANGE, set_charger_system_voltage, HOOK_PRIO_DEFAULT); static void configure_charger(void) { @@ -380,9 +379,8 @@ static void configure_retimer_usbmux(void) case ADLN_LP5_RVP_SKU_BOARD_ID: /* enable TUSB1044RNQR redriver on Port0 */ usb_muxes[TYPE_C_PORT_0].i2c_addr_flags = - TUSB1064_I2C_ADDR14_FLAGS; - usb_muxes[TYPE_C_PORT_0].driver = - &tusb1064_usb_mux_driver; + TUSB1064_I2C_ADDR14_FLAGS; + usb_muxes[TYPE_C_PORT_0].driver = &tusb1064_usb_mux_driver; usb_muxes[TYPE_C_PORT_0].hpd_update = tusb1044_hpd_update; #if defined(HAS_TASK_PD_C1) @@ -404,15 +402,15 @@ static void configure_retimer_usbmux(void) * Change the default usb mux config on runtime to support * dual retimer topology. */ - usb_muxes[TYPE_C_PORT_0].next_mux - = &soc_side_bb_retimer0_usb_mux; + usb_muxes[TYPE_C_PORT_0].next_mux = + &soc_side_bb_retimer0_usb_mux; #if defined(HAS_TASK_PD_C1) - usb_muxes[TYPE_C_PORT_1].next_mux - = &soc_side_bb_retimer1_usb_mux; + usb_muxes[TYPE_C_PORT_1].next_mux = + &soc_side_bb_retimer1_usb_mux; #endif break; - /* Add additional board SKUs */ + /* Add additional board SKUs */ default: break; -- cgit v1.2.1 From 1eac3f5d031349dcf4ee7a9f72e90f97135d05ac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:32 -0600 Subject: driver/retimer/pi3hdx1204.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I883f420d7c1e2a507a38860d3fdd71d047059e3c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730045 Reviewed-by: Jeremy Bettis --- driver/retimer/pi3hdx1204.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/driver/retimer/pi3hdx1204.c b/driver/retimer/pi3hdx1204.c index 0431610059..770b2f47f5 100644 --- a/driver/retimer/pi3hdx1204.c +++ b/driver/retimer/pi3hdx1204.c @@ -9,8 +9,7 @@ #include "i2c.h" #include "pi3hdx1204.h" -int pi3hdx1204_enable(const int i2c_port, - const uint16_t i2c_addr_flags, +int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags, const int enable) { const uint8_t buf[PI3HDX1204_DE_OFFSET + 1] = { @@ -27,8 +26,7 @@ int pi3hdx1204_enable(const int i2c_port, }; int rv; - rv = i2c_xfer(i2c_port, i2c_addr_flags, - buf, PI3HDX1204_DE_OFFSET + 1, + rv = i2c_xfer(i2c_port, i2c_addr_flags, buf, PI3HDX1204_DE_OFFSET + 1, NULL, 0); if (rv) -- cgit v1.2.1 From 73055eeb3fca5064e80596dfa2592e3f5f0a0e72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:35 -0600 Subject: driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I61f104d9ab50b806cfed06c2036fab3946491dc2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729970 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/bep/fpc_private.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/fingerprint/fpc/bep/fpc_private.c b/driver/fingerprint/fpc/bep/fpc_private.c index 03ea84b899..9b83abf309 100644 --- a/driver/fingerprint/fpc/bep/fpc_private.c +++ b/driver/fingerprint/fpc/bep/fpc_private.c @@ -16,10 +16,10 @@ #include "driver/fingerprint/fpc/fpc_sensor.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args) -#define CPRINTS(format, args...) cprints(CC_FP, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args) +#define CPRINTS(format, args...) cprints(CC_FP, format, ##args) -static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4) = {0}; +static uint8_t enroll_ctx[FP_ALGORITHM_ENROLLMENT_SIZE] __aligned(4) = { 0 }; /* Recorded error flags */ static uint16_t errors; @@ -91,8 +91,8 @@ const fpc_bio_info_t fpc_bio_info = { /* Sensor IC commands */ enum fpc_cmd { - FPC_CMD_DEEPSLEEP = 0x2C, - FPC_CMD_HW_ID = 0xFC, + FPC_CMD_DEEPSLEEP = 0x2C, + FPC_CMD_HW_ID = 0xFC, }; /* Maximum size of a sensor command SPI transfer */ -- cgit v1.2.1 From 67870ffbc4052e21a21a69cc48a65a7ec681a0d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:51 -0600 Subject: board/banshee/keyboard_customization.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I987eb98c820cc1656a436358bd9d13893aebcfbd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728001 Reviewed-by: Jeremy Bettis --- board/banshee/keyboard_customization.c | 89 +++++++++++++++------------------- 1 file changed, 40 insertions(+), 49 deletions(-) diff --git a/board/banshee/keyboard_customization.c b/board/banshee/keyboard_customization.c index cf6904cb37..89ffd9cfaa 100644 --- a/board/banshee/keyboard_customization.c +++ b/board/banshee/keyboard_customization.c @@ -15,25 +15,24 @@ enum gpio_signal signal; static int colinv; static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A}, - {0x002f, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077}, - {0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c}, - {0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0xe05a, 0x0029, 0x0024, 0xe01d, 0xe01f, 0x0026, 0xe020, 0xe07a}, - {0x0022, 0x001a, 0xe030, 0xe038, 0x001b, 0x001e, 0x001d, 0x0076}, - {0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b}, - {0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b}, - {0x0049, 0xe072, 0x005d, 0x0044, 0xe023, 0x0046, 0xe021, 0x004b}, - {0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0041, 0x007c, 0xe02c, 0xe02d, 0xe024, 0x003e, 0x0043, 0x0042}, - {0x0013, 0x0064, 0x0075, 0xe054, 0x0051, 0x0061, 0xe06b, 0xe02f}, - {0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x004a, 0xe075, 0x004e, 0xe032, 0x0045, 0x004d, 0x0054, 0x004c}, - {0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023}, - {0x006a, 0xe035, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074}, + { 0x0021, 0x007B, 0x0079, 0x0072, 0x007A, 0x0071, 0x0069, 0xe04A }, + { 0x002f, 0xe070, 0x007D, 0xe01f, 0x006c, 0xe06c, 0xe07d, 0x0077 }, + { 0x0015, 0x0070, 0x00ff, 0x000D, 0x000E, 0x0016, 0x0067, 0x001c }, + { 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0xe05a, 0x0029, 0x0024, 0xe01d, 0xe01f, 0x0026, 0xe020, 0xe07a }, + { 0x0022, 0x001a, 0xe030, 0xe038, 0x001b, 0x001e, 0x001d, 0x0076 }, + { 0x002A, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b }, + { 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b }, + { 0x0049, 0xe072, 0x005d, 0x0044, 0xe023, 0x0046, 0xe021, 0x004b }, + { 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x0041, 0x007c, 0xe02c, 0xe02d, 0xe024, 0x003e, 0x0043, 0x0042 }, + { 0x0013, 0x0064, 0x0075, 0xe054, 0x0051, 0x0061, 0xe06b, 0xe02f }, + { 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x004a, 0xe075, 0x004e, 0xe032, 0x0045, 0x004d, 0x0054, 0x004c }, + { 0x0052, 0x005a, 0xe03c, 0xe069, 0x0055, 0x0066, 0x005b, 0x0023 }, + { 0x006a, 0xe035, 0xe074, 0xe054, 0x0000, 0x006b, 0x0073, 0x0074 }, }; - uint16_t get_scancode_set2(uint8_t row, uint8_t col) { if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) @@ -85,38 +84,30 @@ void board_keyboard_drive_col(int col) #ifdef CONFIG_KEYBOARD_DEBUG static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', - '1', KLLI_UNKNO, 'a'}, - {KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, - KLLI_SEARC, '3', KLLI_F3, KLLI_UNKNO}, - {'x', 'z', KLLI_F2, KLLI_F1, - 's', '2', 'w', KLLI_ESC}, - {'v', 'b', 'g', 't', - '5', '4', 'r', 'f'}, - {'m', 'n', 'h', 'y', - '6', '7', 'u', 'j'}, - {'.', KLLI_DOWN, '\\', 'o', - KLLI_F10, '9', KLLI_UNKNO, 'l'}, - {KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {',', KLLI_UNKNO, KLLI_F7, KLLI_F6, - KLLI_F5, '8', 'i', 'k'}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, - KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT, KLLI_UNKNO}, - {KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'/', KLLI_UP, '-', KLLI_UNKNO, - '0', 'p', '[', ';'}, - {'\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, - '=', KLLI_B_SPC, ']', 'd'}, - {KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + { 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' }, + { KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3, + KLLI_UNKNO }, + { 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC }, + { 'v', 'b', 'g', 't', '5', '4', 'r', 'f' }, + { 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' }, + { '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' }, + { KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO, + KLLI_LEFT, KLLI_UNKNO }, + { KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' }, + { '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' }, + { KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, }; char get_keycap_label(uint8_t row, uint8_t col) -- cgit v1.2.1 From 6343c04bb80253cd51bd7973f0354bbee174d793 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:14 -0600 Subject: board/jacuzzi/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic540e55db65bd8c0348db601b7b15eb5806d56d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728515 Reviewed-by: Jeremy Bettis --- board/jacuzzi/board.c | 110 +++++++++++++++++++++----------------------------- 1 file changed, 47 insertions(+), 63 deletions(-) diff --git a/board/jacuzzi/board.c b/board/jacuzzi/board.c index 861c139fdf..64878e6aff 100644 --- a/board/jacuzzi/board.c +++ b/board/jacuzzi/board.c @@ -46,8 +46,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -59,50 +59,42 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, #ifdef BOARD_JACUZZI - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, #else /* Juniper */ - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -110,8 +102,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -167,8 +159,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -249,12 +240,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -311,8 +302,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -329,8 +319,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -368,14 +357,12 @@ static void board_init(void) #ifndef VARIANT_KUKUI_NO_SENSORS motion_sensor_count = 0; gpio_disable_interrupt(GPIO_ACCEL_INT_ODL); - gpio_set_flags(GPIO_ACCEL_INT_ODL, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN); #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* Disable tablet mode. */ tablet_set_mode(0, TABLET_TRIGGER_LID); gmr_tablet_switch_disable(); - gpio_set_flags(GPIO_TABLET_MODE_L, - GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP); } } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -387,17 +374,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_bmi160_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_icm426xx_ref = { - {0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_icm426xx_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -558,10 +541,11 @@ static void board_detect_motionsensor(void) motion_sensors[BASE_ACCEL] = icm426xx_base_accel; motion_sensors[BASE_GYRO] = icm426xx_base_gyro; } - base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) - ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160; - CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) - ? "ICM40608" : "BMI160"); + base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ? + BASE_GYRO_ICM426XX : + BASE_GYRO_BMI160; + CPRINTS("Base Accelgyro: %s", + (val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160"); } DECLARE_HOOK(HOOK_INIT, board_detect_motionsensor, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From c28e6d1b2da599fae57341793a09492d3e4b9a22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:13 -0600 Subject: board/quackingstick/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie1fb7965882515a474e8f4abd53bb00897c3d1b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728869 Reviewed-by: Jeremy Bettis --- board/quackingstick/board.c | 98 ++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 58 deletions(-) diff --git a/board/quackingstick/board.c b/board/quackingstick/board.c index 9756eb0651..0c51a27250 100644 --- a/board/quackingstick/board.c +++ b/board/quackingstick/board.c @@ -40,10 +40,10 @@ #include "thermal.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -102,34 +102,26 @@ static void board_connect_c0_sbu(enum gpio_signal s) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -204,11 +196,9 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -262,11 +252,9 @@ enum lid_accelgyro_type { static enum lid_accelgyro_type lid_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -365,8 +353,7 @@ static void board_detect_motionsensor(void) return; /* Check base accelgyro chip */ - icm_read8(&motion_sensors_icm[LID_ACCEL], ICM42607_REG_WHO_AM_I, - &val); + icm_read8(&motion_sensors_icm[LID_ACCEL], ICM42607_REG_WHO_AM_I, &val); if (val == ICM42607_CHIP_ICM42607P) { motion_sensors[LID_ACCEL] = motion_sensors_icm[LID_ACCEL]; motion_sensors[LID_GYRO] = motion_sensors_icm[LID_GYRO]; @@ -443,9 +430,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); void board_hibernate(void) { @@ -455,8 +442,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -550,8 +536,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -579,7 +564,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -603,24 +587,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -629,7 +611,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, static void pen_input_deferred(void) { bool pen_charge_enable = !gpio_get_level(GPIO_EC_PEN_PDCT_L) && - !chipset_in_state(CHIPSET_STATE_ANY_OFF); + !chipset_in_state(CHIPSET_STATE_ANY_OFF); gpio_set_level(GPIO_PEN_PWR_EN, pen_charge_enable); -- cgit v1.2.1 From 84e53a65da1b7a40c9eb4a05a1d801322b871635 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:16 -0600 Subject: board/nocturne_fp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Icf25646ace4f8d3989e6144aa63260792640b6e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728762 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- board/nocturne_fp/board.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h index 704c5a0565..5b12d05321 100644 --- a/board/nocturne_fp/board.h +++ b/board/nocturne_fp/board.h @@ -51,28 +51,28 @@ #undef CONFIG_WP_STORAGE_OFF #undef CONFIG_WP_STORAGE_SIZE -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (768*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (768 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE (CONFIG_FLASH_BANK_SIZE * 2) -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * We want to prevent flash readout, and use it as indicator of protection @@ -155,7 +155,7 @@ /* SPI configuration for the fingerprint sensor */ #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */ +#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */ #define CONFIG_FINGERPRINT_MCU #ifdef SECTION_IS_RW @@ -168,7 +168,7 @@ */ #define CONFIG_MALLOC /* Special memory regions to store large arrays */ -#define FP_FRAME_SECTION __SECTION(ahb4) +#define FP_FRAME_SECTION __SECTION(ahb4) #define FP_TEMPLATE_SECTION __SECTION(ahb) #else /* SECTION_IS_RO */ -- cgit v1.2.1 From c27c72cb8a971262b799cc739bfbf4f00a13b7a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:24 -0600 Subject: chip/mchp/tfdp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2548d77f7dd86ef29381d3d73997d32a5a4fd1a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729303 Reviewed-by: Jeremy Bettis --- chip/mchp/tfdp.c | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/chip/mchp/tfdp.c b/chip/mchp/tfdp.c index b4368b46a8..b8d84d8ed6 100644 --- a/chip/mchp/tfdp.c +++ b/chip/mchp/tfdp.c @@ -17,12 +17,11 @@ #ifdef CONFIG_MCHP_TFDP - static uint32_t get_disable_intr(void) { uint32_t m; - __asm__ __volatile__ ("mrs %0, primask;cpsid i" : "=r" (m)); + __asm__ __volatile__("mrs %0, primask;cpsid i" : "=r"(m)); return m; } @@ -30,10 +29,9 @@ static uint32_t get_disable_intr(void) static void restore_intr(uint32_t m) { if (!m) - __asm__ __volatile__ ("cpsie i" : : : "memory"); + __asm__ __volatile__("cpsie i" : : : "memory"); } - /** * tfdp_power - Gate clocks On/Off to TFDP block when idle * @@ -48,7 +46,6 @@ void tfdp_power(uint8_t pwr_on) MCHP_PCR_SLP_EN_DEV(MCHP_PCR_TFDP); } - /** * tfdp_enable - Init Trace FIFO Data Port * @param uint8_t non-zero=enable TFDP, false=disable TFDP @@ -57,8 +54,8 @@ void tfdp_power(uint8_t pwr_on) * Else GPIO170/171 set to GPIO input, internal pull-up enabled. * @note - */ -#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) -#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) +#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) +#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) void tfdp_enable(uint8_t en, uint8_t pin_cfg) { @@ -73,7 +70,6 @@ void tfdp_enable(uint8_t en, uint8_t pin_cfg) } } /* end tfdp_enable() */ - /** * TFDPTrace0 - TRACE0: transmit 16-bit trace number lsb first * over TFDP. @@ -106,7 +102,6 @@ void TFDPTrace0(uint16_t nbr) #endif } - /** * TRDPTrace1 - TRACE1: transmit 16-bit trace number lsb first * and 16-bit data lsb first over TFDP. @@ -144,7 +139,6 @@ void TFDPTrace1(uint16_t nbr, uint32_t p1) #endif } - /** * TFDPTrace2 - TRACE2: transmit 16-bit trace number lsb first * and two 16-bit data parameters lsb first over TFDP. @@ -187,7 +181,6 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2) #endif } - /** * TFDPTrace3 - TRACE3: transmit 16-bit trace number lsb first * and three 16-bit data parameters lsb first over TFDP. @@ -203,8 +196,7 @@ void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2) * interrupts for critical section. These may use * priviledged instructions. */ -void TFDPTrace3(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3) +void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3) { #ifdef MCHP_TRACE_MASK_IRQ uint32_t prim; @@ -236,7 +228,6 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1, #endif } - /** * TFDPTrace4 - TRACE3: transmit 16-bit trace number lsb first * and four 16-bit data parameters lsb first over TFDP. @@ -253,8 +244,8 @@ void TFDPTrace3(uint16_t nbr, uint32_t p1, * interrupts for critical section. These may use * priviledged instructions. */ -void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4) +void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3, + uint32_t p4) { #ifdef MCHP_TRACE_MASK_IRQ uint32_t prim; @@ -290,7 +281,6 @@ void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, #endif } - /** * TFDPTrace11 - Transmit one 32-bit data item over TFDP * @@ -327,7 +317,6 @@ void TFDPTrace11(uint16_t nbr, uint32_t p1) #endif } - /** * TFDPTrace12 - Transmit two 32-bit data items over TFDP * @@ -383,8 +372,7 @@ void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2) * @param uint32_t p3 32-bit data3 to be transmitted * */ -void TFDPTrace13(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3) +void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3) { #ifdef MCHP_TRACE_MASK_IRQ uint32_t prim; @@ -438,8 +426,8 @@ void TFDPTrace13(uint16_t nbr, uint32_t p1, * @param uint32_t p3 32-bit data3 to be transmitted * @param uint32_t p4 32-bit data4 to be transmitted */ -void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4) +void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3, + uint32_t p4) { #ifdef MCHP_TRACE_MASK_IRQ uint32_t prim; @@ -493,7 +481,6 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, #endif /* #ifdef CONFIG_MCHP_TFDP */ - /* end tfdp.c */ /** @} */ -- cgit v1.2.1 From 0700db2ffc35baad9b333f4d3a995a08cb4fbb9c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:39 -0600 Subject: chip/npcx/sib.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85f4b215697a135e68851dd1a0e7c3e7057c76fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729433 Reviewed-by: Jeremy Bettis --- chip/npcx/sib.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/npcx/sib.c b/chip/npcx/sib.c index 424048518e..a441a3db83 100644 --- a/chip/npcx/sib.c +++ b/chip/npcx/sib.c @@ -28,7 +28,7 @@ /* Console output macros */ #ifdef DEBUG_SIB #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) #else #define CPUTS(...) #define CPRINTS(...) @@ -110,8 +110,7 @@ uint8_t sib_read_kbc_reg(uint8_t io_offset) } /* Super-IO read/write function */ -void sib_write_reg(uint8_t io_offset, uint8_t index_value, - uint8_t io_data) +void sib_write_reg(uint8_t io_offset, uint8_t index_value, uint8_t io_data) { /* Disable interrupts */ interrupt_disable(); @@ -132,7 +131,7 @@ void sib_write_reg(uint8_t io_offset, uint8_t index_value, sib_wait_host_write_done(); /* Specify the io_offset A0 = 1. the data register is accessed */ - NPCX_IHIOA = io_offset+1; + NPCX_IHIOA = io_offset + 1; /* Write the data. This starts the write access to the host module */ NPCX_IHD = io_data; /* Wait while Core write operation is in progress */ @@ -170,7 +169,7 @@ uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value) sib_wait_host_write_done(); /* Specify the io_offset A0 = 1. the data register is accessed */ - NPCX_IHIOA = io_offset+1; + NPCX_IHIOA = io_offset + 1; /* Start a Core read from host module */ SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSRD); /* Wait while Core read operation is in progress */ -- cgit v1.2.1 From 67618563387e74a08010ebf23ba0ab05e0c7a903 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:30 -0600 Subject: core/nds32/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27b00f3f480f17dd854155c9e7246711677728af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729862 Reviewed-by: Jeremy Bettis --- core/nds32/include/fpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/nds32/include/fpu.h b/core/nds32/include/fpu.h index 4f3efc2e5a..72be8a8d9b 100644 --- a/core/nds32/include/fpu.h +++ b/core/nds32/include/fpu.h @@ -11,4 +11,4 @@ float sqrtf(float x); float fabsf(float x); -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ -- cgit v1.2.1 From ef6a50b2ed9ac646c1407cdd2cdd9b458dba4229 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:50 -0600 Subject: zephyr/shim/include/usbc/tcpci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a6f2ba2509c602514bfb27fe77d53a1336372ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730842 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h index 35f706d09b..f65b6b7717 100644 --- a/zephyr/shim/include/usbc/tcpci.h +++ b/zephyr/shim/include/usbc/tcpci.h @@ -9,7 +9,7 @@ #define TCPCI_COMPAT cros_ec_tcpci -#define TCPC_CONFIG_TCPCI(id) \ +#define TCPC_CONFIG_TCPCI(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ -- cgit v1.2.1 From a2d255d8af182aeecd91a9ec4de21646887fc92b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:54 -0600 Subject: common/fpsensor/fpsensor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: If2ffe77e9ba2016cc0017a817535c01fcb8df171 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729629 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- common/fpsensor/fpsensor.c | 100 ++++++++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 51 deletions(-) diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c index 12904c0b39..263a9d0888 100644 --- a/common/fpsensor/fpsensor.c +++ b/common/fpsensor/fpsensor.c @@ -42,14 +42,14 @@ static timestamp_t encryption_deadline; #define FP_SENSOR_IMAGE_OFFSET 0 #endif -#define FP_MODE_ANY_CAPTURE (FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | \ - FP_MODE_MATCH) -#define FP_MODE_ANY_DETECT_FINGER (FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \ - FP_MODE_ANY_CAPTURE) -#define FP_MODE_ANY_WAIT_IRQ (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE) +#define FP_MODE_ANY_CAPTURE \ + (FP_MODE_CAPTURE | FP_MODE_ENROLL_IMAGE | FP_MODE_MATCH) +#define FP_MODE_ANY_DETECT_FINGER \ + (FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | FP_MODE_ANY_CAPTURE) +#define FP_MODE_ANY_WAIT_IRQ (FP_MODE_FINGER_DOWN | FP_MODE_ANY_CAPTURE) /* Delay between 2 s of the sensor to detect finger removal */ -#define FINGER_POLLING_DELAY (100*MSEC) +#define FINGER_POLLING_DELAY (100 * MSEC) /* Timing statistics. */ static uint32_t capture_time_us; @@ -76,8 +76,8 @@ static inline int is_raw_capture(uint32_t mode) { int capture_type = FP_CAPTURE_TYPE(mode); - return (capture_type == FP_CAPTURE_VENDOR_FORMAT - || capture_type == FP_CAPTURE_QUALITY_TEST); + return (capture_type == FP_CAPTURE_VENDOR_FORMAT || + capture_type == FP_CAPTURE_QUALITY_TEST); } __maybe_unused static bool fp_match_success(int match_result) @@ -92,10 +92,10 @@ static inline int is_test_capture(uint32_t mode) { int capture_type = FP_CAPTURE_TYPE(mode); - return (mode & FP_MODE_CAPTURE) - && (capture_type == FP_CAPTURE_PATTERN0 - || capture_type == FP_CAPTURE_PATTERN1 - || capture_type == FP_CAPTURE_RESET_TEST); + return (mode & FP_MODE_CAPTURE) && + (capture_type == FP_CAPTURE_PATTERN0 || + capture_type == FP_CAPTURE_PATTERN1 || + capture_type == FP_CAPTURE_RESET_TEST); } /* @@ -119,8 +119,8 @@ static uint32_t fp_process_enroll(void) res = fp_finger_enroll(fp_buffer, &percent); CPRINTS("[%d]Enroll =>%d (%d%%)", templ_valid, res, percent); if (res < 0) - return EC_MKBP_FP_ENROLL - | EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL); + return EC_MKBP_FP_ENROLL | + EC_MKBP_FP_ERRCODE(EC_MKBP_FP_ERR_ENROLL_INTERNAL); templ_dirty |= BIT(templ_valid); if (percent == 100) { res = fp_enrollment_finish(fp_template[templ_valid]); @@ -128,15 +128,15 @@ static uint32_t fp_process_enroll(void) res = EC_MKBP_FP_ERR_ENROLL_INTERNAL; } else { template_newly_enrolled = templ_valid; - fp_enable_positive_match_secret(templ_valid, - &positive_match_secret_state); + fp_enable_positive_match_secret( + templ_valid, &positive_match_secret_state); templ_valid++; } sensor_mode &= ~FP_MODE_ENROLL_SESSION; enroll_session &= ~FP_MODE_ENROLL_SESSION; } - return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res) - | (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET); + return EC_MKBP_FP_ENROLL | EC_MKBP_FP_ERRCODE(res) | + (percent << EC_MKBP_FP_ENROLL_PROGRESS_OFFSET); } static uint32_t fp_process_match(void) @@ -161,8 +161,8 @@ static uint32_t fp_process_match(void) * with EC_MKBP_FP_ERR_MATCH_NO_INTERNAL. */ if (fgr >= 0 && fgr < FP_MAX_FINGER_COUNT) { - fp_enable_positive_match_secret(fgr, - &positive_match_secret_state); + fp_enable_positive_match_secret( + fgr, &positive_match_secret_state); } else { res = EC_MKBP_FP_ERR_MATCH_NO_INTERNAL; } @@ -187,8 +187,9 @@ static uint32_t fp_process_match(void) timestamps_invalid |= FPSTATS_MATCHING_INV; matching_time_us = time_since32(t0); - return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res) - | ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) & EC_MKBP_FP_MATCH_IDX_MASK); + return EC_MKBP_FP_MATCH | EC_MKBP_FP_ERRCODE(res) | + ((fgr << EC_MKBP_FP_MATCH_IDX_OFFSET) & + EC_MKBP_FP_MATCH_IDX_MASK); } static void fp_process_finger(void) @@ -260,12 +261,12 @@ void fp_task(void) } else { fp_enrollment_finish(NULL); } - enroll_session = - sensor_mode & FP_MODE_ENROLL_SESSION; + enroll_session = sensor_mode & + FP_MODE_ENROLL_SESSION; } if (is_test_capture(mode)) { - fp_sensor_acquire_image_with_mode(fp_buffer, - FP_CAPTURE_TYPE(mode)); + fp_sensor_acquire_image_with_mode( + fp_buffer, FP_CAPTURE_TYPE(mode)); sensor_mode &= ~FP_MODE_CAPTURE; send_mkbp_event(EC_MKBP_FP_IMAGE_READY); continue; @@ -343,13 +344,14 @@ static enum ec_status fp_command_passthru(struct host_cmd_handler_args *args) if (system_is_locked()) return EC_RES_ACCESS_DENIED; - if (params->len > args->params_size + - offsetof(struct ec_params_fp_passthru, data) || + if (params->len > + args->params_size + + offsetof(struct ec_params_fp_passthru, data) || params->len > args->response_max) return EC_RES_INVALID_PARAM; - rc = spi_transaction_async(&spi_devices[0], params->data, - params->len, out, SPI_READBACK_ALL); + rc = spi_transaction_async(&spi_devices[0], params->data, params->len, + out, SPI_READBACK_ALL); if (params->flags & EC_FP_FLAG_NOT_COMPLETE) rc |= spi_transaction_wait(&spi_devices[0]); else @@ -381,8 +383,9 @@ static enum ec_status fp_command_info(struct host_cmd_handler_args *args) r->template_version = FP_TEMPLATE_FORMAT_VERSION; /* V1 is identical to V0 with more information appended */ - args->response_size = args->version ? sizeof(*r) : - sizeof(struct ec_response_fp_info_v0); + args->response_size = args->version ? + sizeof(*r) : + sizeof(struct ec_response_fp_info_v0); return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_FP_INFO, fp_command_info, @@ -508,8 +511,7 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) /* Encrypt the secret blob in-place. */ ret = aes_gcm_encrypt(key, SBP_ENC_KEY_LEN, encrypted_template, - encrypted_template, - encrypted_blob_size, + encrypted_template, encrypted_blob_size, enc_info->nonce, FP_CONTEXT_NONCE_BYTES, enc_info->tag, FP_CONTEXT_TAG_BYTES); always_memset(key, 0, sizeof(key)); @@ -550,12 +552,11 @@ DECLARE_HOST_COMMAND(EC_CMD_FP_STATS, fp_command_stats, EC_VER_MASK(0)); static bool template_needs_validation_value( struct ec_fp_template_encryption_metadata *enc_info) { - return enc_info->struct_version == 3 - && FP_TEMPLATE_FORMAT_VERSION == 4; + return enc_info->struct_version == 3 && FP_TEMPLATE_FORMAT_VERSION == 4; } -static int validate_template_format( - struct ec_fp_template_encryption_metadata *enc_info) +static int +validate_template_format(struct ec_fp_template_encryption_metadata *enc_info) { if (template_needs_validation_value(enc_info)) /* The host requested migration to v4. */ @@ -619,9 +620,8 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args) if (enc_info->struct_version <= 3) { encrypted_blob_size = sizeof(fp_template[0]); } else { - encrypted_blob_size = - sizeof(fp_template[0]) + - sizeof(fp_positive_match_salt[0]); + encrypted_blob_size = sizeof(fp_template[0]) + + sizeof(fp_positive_match_salt[0]); } ret = derive_encryption_key(key, enc_info->encryption_salt); @@ -632,8 +632,7 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args) /* Decrypt the secret blob in-place. */ ret = aes_gcm_decrypt(key, SBP_ENC_KEY_LEN, encrypted_template, - encrypted_template, - encrypted_blob_size, + encrypted_template, encrypted_blob_size, enc_info->nonce, FP_CONTEXT_NONCE_BYTES, enc_info->tag, FP_CONTEXT_TAG_BYTES); always_memset(key, 0, sizeof(key)); @@ -703,7 +702,8 @@ DECLARE_HOST_COMMAND(EC_CMD_FP_TEMPLATE, fp_command_template, EC_VER_MASK(0)); * Add the following to your ${HOME}/.screenrc: * * zmodem catch - * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display /tmp/finger.pgm"' + * zmodem recvcmd '!!! bash -c "ascii-xfr -rdv /tmp/finger.pgm && display + * /tmp/finger.pgm"' * * From *outside the chroot*, use screen to connect to UART console: * @@ -781,8 +781,8 @@ static int command_fpcapture(int argc, char **argv) if (*e || capture_type < 0) return EC_ERROR_PARAM1; } - mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT) - & FP_MODE_CAPTURE_TYPE_MASK); + mode = FP_MODE_CAPTURE | ((capture_type << FP_MODE_CAPTURE_TYPE_SHIFT) & + FP_MODE_CAPTURE_TYPE_MASK); rc = fp_console_action(mode); if (rc == EC_SUCCESS) @@ -799,8 +799,8 @@ static int command_fpenroll(int argc, char **argv) enum ec_error_list rc; int percent = 0; uint32_t event; - static const char * const enroll_str[] = {"OK", "Low Quality", - "Immobile", "Low Coverage"}; + static const char *const enroll_str[] = { "OK", "Low Quality", + "Immobile", "Low Coverage" }; /* * TODO(b/142944002): Remove this redundant check for system_is_locked @@ -832,9 +832,7 @@ static int command_fpenroll(int argc, char **argv) return rc; } DECLARE_CONSOLE_COMMAND_FLAGS(fpenroll, command_fpenroll, NULL, - "Enroll a new fingerprint", - CMD_FLAG_RESTRICTED); - + "Enroll a new fingerprint", CMD_FLAG_RESTRICTED); static int command_fpmatch(int argc, char **argv) { -- cgit v1.2.1 From 2a13f19996094bca37b7b762708770701e40ec72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:20 -0600 Subject: board/foob/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2a112f3f3b65fd10e50456218d43570b5e44c14 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728377 Reviewed-by: Jeremy Bettis --- board/foob/board.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/board/foob/board.h b/board/foob/board.h index 07637c3373..e3e1ec602e 100644 --- a/board/foob/board.h +++ b/board/foob/board.h @@ -30,8 +30,8 @@ #define CONFIG_CMD_ACCEL_INFO /* Sensors */ -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -50,10 +50,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT, }; @@ -64,18 +64,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From f2ed2cfe38455b3f38e7d516d6d93566c40561ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:39 -0600 Subject: zephyr/test/drivers/src/bma2x2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie494fdbfde657271a263392773f077e0c37736db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730939 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bma2x2.c | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/zephyr/test/drivers/src/bma2x2.c b/zephyr/test/drivers/src/bma2x2.c index 1995adc571..e04e402af1 100644 --- a/zephyr/test/drivers/src/bma2x2.c +++ b/zephyr/test/drivers/src/bma2x2.c @@ -27,11 +27,9 @@ static mutex_t sensor_mutex; /** Rotation used in some tests */ -static const mat33_fp_t test_rotation = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /** Rotate given vector by test rotation */ void rotate_int3v_by_test_rotation(int16_t *v) @@ -99,7 +97,8 @@ static void compare_int3v_f(int16_t *exp_v, int16_t *v, int line) int i; for (i = 0; i < 3; i++) { - zassert_within(exp_v[i], v[i], V_EPS, + zassert_within( + exp_v[i], v[i], V_EPS, "Expected [%d; %d; %d], got [%d; %d; %d]; line: %d", exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line); } @@ -269,8 +268,8 @@ static void check_set_range_f(struct i2c_emul *emul, int range, int rnd, zassert_equal(EC_SUCCESS, ms.drv->set_range(&ms, range, rnd), "set_range failed; line: %d", line); zassert_equal(exp_range, ms.current_range, - "Expected range %d, got %d; line %d", - exp_range, ms.current_range, line); + "Expected range %d, got %d; line %d", exp_range, + ms.current_range, line); range_reg = bma_emul_get_reg(emul, BMA2x2_RANGE_SELECT_ADDR); range_reg &= BMA2x2_RANGE_SELECT_MSK; @@ -299,7 +298,7 @@ static void check_set_range_f(struct i2c_emul *emul, int range, int rnd, "Expected range reg 0x%x, got 0x%x; line %d", exp_range_reg, range_reg, line); } -#define check_set_range(emul, range, rnd, exp_range) \ +#define check_set_range(emul, range, rnd, exp_range) \ check_set_range_f(emul, range, rnd, exp_range, __LINE__) /** Test set range with and without I2C errors. */ @@ -500,10 +499,10 @@ static void check_set_rate_f(struct i2c_emul *emul, int rate, int rnd, } zassert_equal(exp_rate_reg, rate_reg, - "Expected rate reg 0x%x, got 0x%x; line %d", - exp_rate_reg, rate_reg, line); + "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg, + rate_reg, line); } -#define check_set_rate(emul, rate, rnd, exp_rate) \ +#define check_set_rate(emul, rate, rnd, exp_rate) \ check_set_rate_f(emul, rate, rnd, exp_rate, __LINE__) /** Test set and get rate with and without I2C errors. */ @@ -589,8 +588,8 @@ ZTEST_USER(bma2x2, test_bma_rate) zassert_equal(EC_ERROR_INVAL, ms.drv->set_data_rate(&ms, 15625, 1), NULL); zassert_equal(drv_rate, ms.drv->get_data_rate(&ms), NULL); - zassert_equal(reg_rate, - bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR), NULL); + zassert_equal(reg_rate, bma_emul_get_reg(emul, BMA2x2_BW_SELECT_ADDR), + NULL); /* Do not fail on read */ i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -765,11 +764,9 @@ ZTEST_USER(bma2x2, test_bma_perform_calib) int16_t ret_off[3]; int range; int rate; - mat33_fp_t rot = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} - }; + mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; emul = bma_emul_get(BMA_ORD); @@ -875,8 +872,8 @@ ZTEST_USER(bma2x2, test_bma_perform_calib) /* Enable rotation with negative value on Z axis */ ms.rot_standard_ref = &rot; /* Expected offset -1G - accelerometer[Z] */ - exp_off[2] = -((int)BMA_EMUL_1G) - bma_emul_get_acc(emul, - BMA_EMUL_AXIS_Z); + exp_off[2] = + -((int)BMA_EMUL_1G) - bma_emul_get_acc(emul, BMA_EMUL_AXIS_Z); /* Test successful offset compenastion with negative Z rotation */ zassert_equal(EC_SUCCESS, ms.drv->perform_calib(&ms, 1), NULL); -- cgit v1.2.1 From 3cefa7308644a1195fc257d54632fe5a66862f4b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:07 -0600 Subject: chip/stm32/gpio-f0-l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I898edd8790f612371925828ccb7fbf767210dda2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729503 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-f0-l.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/stm32/gpio-f0-l.c b/chip/stm32/gpio-f0-l.c index 55628cb6d4..51691ba3be 100644 --- a/chip/stm32/gpio-f0-l.c +++ b/chip/stm32/gpio-f0-l.c @@ -62,7 +62,6 @@ int gpio_get_flags_by_mask(uint32_t port, uint32_t mask) flags |= GPIO_LOW; } - if (STM32_EXTI_RTSR & mask) flags |= GPIO_INT_F_RISING; if (STM32_EXTI_RTSR & mask) @@ -80,9 +79,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up pullup / pulldown */ val = STM32_GPIO_PUPDR(port) & ~mask2; if (flags & GPIO_PULL_UP) - val |= 0x55555555 & mask2; /* Pull Up = 01 */ + val |= 0x55555555 & mask2; /* Pull Up = 01 */ else if (flags & GPIO_PULL_DOWN) - val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ + val |= 0xaaaaaaaa & mask2; /* Pull Down = 10 */ STM32_GPIO_PUPDR(port) = val; /* @@ -133,10 +132,10 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) } void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* Ensure that the func parameter isn't overflowed */ - BUILD_ASSERT((int) MODULE_COUNT <= (int) GPIO_ALT_FUNC_MAX); + BUILD_ASSERT((int)MODULE_COUNT <= (int)GPIO_ALT_FUNC_MAX); int bit; uint32_t half; -- cgit v1.2.1 From 620e6171a127ddcad922c3d93df115ca1af08c0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:51 -0600 Subject: board/aleena/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I88f84386c4e4cbe1fe6fc406cd2b2c8e7071aa01 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727099 Reviewed-by: Jeremy Bettis --- board/aleena/board.c | 142 +++++++++++++++++++++++---------------------------- 1 file changed, 64 insertions(+), 78 deletions(-) diff --git a/board/aleena/board.c b/board/aleena/board.c index 460c73fcdd..ebc47deb67 100644 --- a/board/aleena/board.c +++ b/board/aleena/board.c @@ -31,52 +31,40 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "kblight", - .port = I2C_PORT_KBLIGHT, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "kblight", + .port = I2C_PORT_KBLIGHT, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -101,11 +89,9 @@ enum base_accelgyro_type { BASE_GYRO_ICM426XX = 2, }; -const mat33_fp_t base_standard_ref_icm426xx = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm426xx_base_accel = { .name = "Base Accel", @@ -136,20 +122,20 @@ struct motion_sensor_t icm426xx_base_accel = { }; struct motion_sensor_t icm426xx_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, - .mutex = &icm426xx_mutex, - .drv_data = &g_icm426xx_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &base_standard_ref_icm426xx, - .min_frequency = ICM426XX_GYRO_MIN_FREQ, - .max_frequency = ICM426XX_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM426XX, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm426xx_drv, + .mutex = &icm426xx_mutex, + .drv_data = &g_icm426xx_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &base_standard_ref_icm426xx, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; static enum base_accelgyro_type base_accelgyro_config; @@ -179,18 +165,20 @@ static void board_detect_motionsensor(void) if (board_is_convertible()) { /* Check base accelgyro chip */ - ret = icm_read8(&icm426xx_base_accel, - ICM426XX_REG_WHO_AM_I, &val); + ret = icm_read8(&icm426xx_base_accel, ICM426XX_REG_WHO_AM_I, + &val); if (ret) ccprints("Get ICM fail."); if (val == ICM426XX_CHIP_ICM40608) { motion_sensors[BASE_ACCEL] = icm426xx_base_accel; motion_sensors[BASE_GYRO] = icm426xx_base_gyro; } - base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) - ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160; - ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) - ? "ICM40608" : "BMI160"); + base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ? + BASE_GYRO_ICM426XX : + BASE_GYRO_BMI160; + ccprints("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) ? + "ICM40608" : + "BMI160"); } } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, @@ -207,8 +195,7 @@ void board_update_sensor_config_from_sku(void) /* Device is clamshell only */ tablet_set_mode(0, TABLET_TRIGGER_LID); /* Gyro is not present, don't allow line to float */ - gpio_set_flags(GPIO_6AXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } } @@ -230,15 +217,14 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT); * The connector has 30 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 6ba50ed57f30c8d9ab19b4f1ae59538882c7e273 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:21 -0600 Subject: board/kukui_scp/venc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4146fa9510681d736537b897f89f2099dd51c5bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728544 Reviewed-by: Jeremy Bettis --- board/kukui_scp/venc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kukui_scp/venc.h b/board/kukui_scp/venc.h index 7046633046..b1337c194d 100644 --- a/board/kukui_scp/venc.h +++ b/board/kukui_scp/venc.h @@ -22,7 +22,8 @@ struct venc_msg { unsigned char msg[288]; }; -BUILD_ASSERT(member_size(struct venc_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE); +BUILD_ASSERT(member_size(struct venc_msg, msg) <= + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void venc_h264_msg_handler(void *data); -- cgit v1.2.1 From 98a20f937e075d250d4fac205beb737151b72542 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:04 -0600 Subject: common/fpsensor/fpsensor_state.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I7235b7700287eaec6357638356300fe730051995 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729650 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- common/fpsensor/fpsensor_state.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/common/fpsensor/fpsensor_state.c b/common/fpsensor/fpsensor_state.c index bd907e2c00..0686fb2fa9 100644 --- a/common/fpsensor/fpsensor_state.c +++ b/common/fpsensor/fpsensor_state.c @@ -19,19 +19,18 @@ /* Last acquired frame (aligned as it is used by arbitrary binary libraries) */ uint8_t fp_buffer[FP_SENSOR_IMAGE_SIZE] FP_FRAME_SECTION __aligned(4); /* Fingers templates for the current user */ -uint8_t fp_template[FP_MAX_FINGER_COUNT][FP_ALGORITHM_TEMPLATE_SIZE] - FP_TEMPLATE_SECTION; +uint8_t fp_template[FP_MAX_FINGER_COUNT] + [FP_ALGORITHM_TEMPLATE_SIZE] FP_TEMPLATE_SECTION; /* Encryption/decryption buffer */ /* TODO: On-the-fly encryption/decryption without a dedicated buffer */ /* * Store the encryption metadata at the beginning of the buffer containing the * ciphered data. */ -uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE] - FP_TEMPLATE_SECTION; +uint8_t fp_enc_buffer[FP_ALGORITHM_ENCRYPTED_TEMPLATE_SIZE] FP_TEMPLATE_SECTION; /* Salt used in derivation of positive match secret. */ -uint8_t fp_positive_match_salt - [FP_MAX_FINGER_COUNT][FP_POSITIVE_MATCH_SALT_BYTES]; +uint8_t fp_positive_match_salt[FP_MAX_FINGER_COUNT] + [FP_POSITIVE_MATCH_SALT_BYTES]; struct positive_match_secret_state positive_match_secret_state = { .template_matched = FP_NO_SUCH_TEMPLATE, @@ -262,23 +261,22 @@ int fp_enable_positive_match_secret(uint32_t fgr, return EC_SUCCESS; } -void fp_disable_positive_match_secret( - struct positive_match_secret_state *state) +void fp_disable_positive_match_secret(struct positive_match_secret_state *state) { state->template_matched = FP_NO_SUCH_TEMPLATE; state->readable = false; state->deadline.val = 0; } -static enum ec_status fp_command_read_match_secret( - struct host_cmd_handler_args *args) +static enum ec_status +fp_command_read_match_secret(struct host_cmd_handler_args *args) { const struct ec_params_fp_read_match_secret *params = args->params; struct ec_response_fp_read_match_secret *response = args->response; int8_t fgr = params->fgr; timestamp_t now = get_time(); - struct positive_match_secret_state state_copy - = positive_match_secret_state; + struct positive_match_secret_state state_copy = + positive_match_secret_state; fp_disable_positive_match_secret(&positive_match_secret_state); @@ -293,13 +291,14 @@ static enum ec_status fp_command_read_match_secret( } if (fgr != state_copy.template_matched || !state_copy.readable) { CPRINTS("Positive match secret for finger %d is not meant to " - "be read now.", fgr); + "be read now.", + fgr); return EC_RES_ACCESS_DENIED; } if (derive_positive_match_secret(response->positive_match_secret, - fp_positive_match_salt[fgr]) - != EC_SUCCESS) { + fp_positive_match_salt[fgr]) != + EC_SUCCESS) { CPRINTS("Failed to derive positive match secret for finger %d", fgr); /* Keep the template and encryption salt. */ -- cgit v1.2.1 From 21289d170c20452f5b6ccd280e76aaba43f8c5a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:25 -0600 Subject: driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I2c0c0df98d06dea91304a1c07118a588b17d1376 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729969 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- driver/fingerprint/fpc/bep/fpc1025_private.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/fingerprint/fpc/bep/fpc1025_private.h b/driver/fingerprint/fpc/bep/fpc1025_private.h index 2da127741f..a25d789e37 100644 --- a/driver/fingerprint/fpc/bep/fpc1025_private.h +++ b/driver/fingerprint/fpc/bep/fpc1025_private.h @@ -13,19 +13,19 @@ #define FP_SENSOR_NAME "FPC1025" /* Sensor pixel resolution */ -#define FP_SENSOR_RES_X (160) /**< Sensor width */ -#define FP_SENSOR_RES_Y (160) /**< Sensor height */ -#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel */ +#define FP_SENSOR_RES_X (160) /**< Sensor width */ +#define FP_SENSOR_RES_Y (160) /**< Sensor height */ +#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel */ /* * Sensor image size * * Value from fpc_bep_image_get_buffer_size(): (160*160)+660 */ -#define FP_SENSOR_IMAGE_SIZE (26260) -#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y) +#define FP_SENSOR_IMAGE_SIZE (26260) +#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y) /* Offset of image data in fp_buffer */ -#define FP_SENSOR_IMAGE_OFFSET (400) +#define FP_SENSOR_IMAGE_OFFSET (400) /* * Constant value for the enrollment data size @@ -41,9 +41,9 @@ * * Template size + alignment padding + size of template size variable */ -#define FP_ALGORITHM_TEMPLATE_SIZE (5088 + 0 + 4) +#define FP_ALGORITHM_TEMPLATE_SIZE (5088 + 0 + 4) /* Max number of templates stored / matched against */ -#define FP_MAX_FINGER_COUNT (5) +#define FP_MAX_FINGER_COUNT (5) #endif /* __CROS_EC_FPC1025_PRIVATE_H */ -- cgit v1.2.1 From 49945a6a88c130c8807b65a17b31ace6f2eec4e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:05 -0600 Subject: include/vboot.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I427a43cbfa7022c80b4cf4d4314f3048e00e2833 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730453 Reviewed-by: Jeremy Bettis --- include/vboot.h | 67 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/include/vboot.h b/include/vboot.h index 52ccae6e90..2df76b9e03 100644 --- a/include/vboot.h +++ b/include/vboot.h @@ -31,7 +31,6 @@ int vb21_is_packed_key_valid(const struct vb21_packed_key *key); int vb21_is_signature_valid(const struct vb21_signature *sig, const struct vb21_packed_key *key); - /** * Returns the public key in RO that was used to sign RW. * @@ -58,8 +57,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end); * @param sig Signature of * @return EC_SUCCESS or EC_ERROR_* */ -int vboot_verify(const uint8_t *data, int len, - const struct rsa_public_key *key, const uint8_t *sig); +int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key, + const uint8_t *sig); /** * Entry point of EC EFS @@ -100,19 +99,19 @@ __override_proto void board_enable_packet_mode(bool enable); void packet_mode_interrupt(enum gpio_signal signal); /* Maximum number of times EC retries packet transmission before giving up. */ -#define CR50_COMM_MAX_RETRY 5 +#define CR50_COMM_MAX_RETRY 5 /* EC's timeout for packet transmission to Cr50. */ -#define CR50_COMM_TIMEOUT (50 * MSEC) +#define CR50_COMM_TIMEOUT (50 * MSEC) /* Preamble character repeated before the packet header starts. */ -#define CR50_COMM_PREAMBLE 0xec +#define CR50_COMM_PREAMBLE 0xec /* Magic characters used to identify ec-cr50-comm packets */ -#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */ +#define CR50_PACKET_MAGIC 0x4345 /* 'EC' in little endian */ /* version of struct cr50_comm_request */ -#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */ +#define CR50_COMM_PACKET_VERSION (0 << 4 | 0 << 0) /* 0.0 */ /** * EC-Cr50 data frame looks like the following: @@ -125,11 +124,11 @@ void packet_mode_interrupt(enum gpio_signal signal); */ struct cr50_comm_request { /* Header */ - uint16_t magic; /* CR50_PACKET_MAGIC */ - uint8_t struct_version; /* version of this struct msb:lsb=major:minor */ - uint8_t crc; /* checksum computed from all bytes after crc */ - uint16_t type; /* CR50_CMD_* */ - uint8_t size; /* Payload size. Be easy on Cr50 buffer. */ + uint16_t magic; /* CR50_PACKET_MAGIC */ + uint8_t struct_version; /* version of this struct msb:lsb=major:minor */ + uint8_t crc; /* checksum computed from all bytes after crc */ + uint16_t type; /* CR50_CMD_* */ + uint8_t size; /* Payload size. Be easy on Cr50 buffer. */ /* Payload */ uint8_t data[]; } __packed; @@ -138,33 +137,33 @@ struct cr50_comm_response { uint16_t error; } __packed; -#define CR50_COMM_MAX_REQUEST_SIZE (sizeof(struct cr50_comm_request) \ - + UINT8_MAX) -#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */ +#define CR50_COMM_MAX_REQUEST_SIZE \ + (sizeof(struct cr50_comm_request) + UINT8_MAX) +#define CR50_UART_RX_BUFFER_SIZE 32 /* TODO: Get from Cr50 header */ /* commands */ enum cr50_comm_cmd { - CR50_COMM_CMD_HELLO = 0x0000, - CR50_COMM_CMD_SET_BOOT_MODE = 0x0001, - CR50_COMM_CMD_VERIFY_HASH = 0x0002, - CR50_COMM_CMD_LIMIT = 0xffff, + CR50_COMM_CMD_HELLO = 0x0000, + CR50_COMM_CMD_SET_BOOT_MODE = 0x0001, + CR50_COMM_CMD_VERIFY_HASH = 0x0002, + CR50_COMM_CMD_LIMIT = 0xffff, } __packed; BUILD_ASSERT(sizeof(enum cr50_comm_cmd) == sizeof(uint16_t)); -#define CR50_COMM_ERR_PREFIX 0xec +#define CR50_COMM_ERR_PREFIX 0xec /* return code */ enum cr50_comm_err { - CR50_COMM_SUCCESS = 0xec00, - CR50_COMM_ERR_UNKNOWN = 0xec01, - CR50_COMM_ERR_MAGIC = 0xec02, - CR50_COMM_ERR_CRC = 0xec03, - CR50_COMM_ERR_SIZE = 0xec04, - CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */ - CR50_COMM_ERR_UNDEFINED_CMD = 0xec06, - CR50_COMM_ERR_BAD_PAYLOAD = 0xec07, - CR50_COMM_ERR_STRUCT_VERSION = 0xec08, - CR50_COMM_ERR_NVMEM = 0xec09, + CR50_COMM_SUCCESS = 0xec00, + CR50_COMM_ERR_UNKNOWN = 0xec01, + CR50_COMM_ERR_MAGIC = 0xec02, + CR50_COMM_ERR_CRC = 0xec03, + CR50_COMM_ERR_SIZE = 0xec04, + CR50_COMM_ERR_TIMEOUT = 0xec05, /* Generated by EC */ + CR50_COMM_ERR_UNDEFINED_CMD = 0xec06, + CR50_COMM_ERR_BAD_PAYLOAD = 0xec07, + CR50_COMM_ERR_STRUCT_VERSION = 0xec08, + CR50_COMM_ERR_NVMEM = 0xec09, } __packed; BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t)); @@ -173,8 +172,8 @@ BUILD_ASSERT(sizeof(enum cr50_comm_err) == sizeof(uint16_t)); * BIT(0) : RECOVERY flag */ enum boot_mode { - BOOT_MODE_NORMAL = 0x00, - BOOT_MODE_NO_BOOT = 0x01, + BOOT_MODE_NORMAL = 0x00, + BOOT_MODE_NO_BOOT = 0x01, } __packed; BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t)); @@ -187,4 +186,4 @@ BUILD_ASSERT(sizeof(enum boot_mode) == sizeof(uint8_t)); */ __override_proto bool vboot_allow_usb_pd(void); -#endif /* __CROS_EC_INCLUDE_VBOOT_H */ +#endif /* __CROS_EC_INCLUDE_VBOOT_H */ -- cgit v1.2.1 From aa2de3dbad700e94831b5b45bdbc3f2523318eae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:38 -0600 Subject: board/fennel/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91cc78e39c15faedf3a75c0683d409b598a55327 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728365 Reviewed-by: Jeremy Bettis --- board/fennel/led.c | 53 +++++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/board/fennel/led.c b/board/fennel/led.c index 7d95c4807e..b6b906a070 100644 --- a/board/fennel/led.c +++ b/board/fennel/led.c @@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From b513d068632c3bfb81a7b7d12f735d1b4329160e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:49 -0600 Subject: test/mutex.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I893a8076615c9dcd21dcdb7f4394c0b677ea14fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730515 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/mutex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/mutex.c b/test/mutex.c index 4fbf7d5cae..bd0e033453 100644 --- a/test/mutex.c +++ b/test/mutex.c @@ -22,7 +22,7 @@ static struct mutex mtx; int mutex_random_task(void *unused) { - char letter = 'A'+(TASK_ID_MTX3A - task_get_current()); + char letter = 'A' + (TASK_ID_MTX3A - task_get_current()); /* wait to be activated */ while (1) { -- cgit v1.2.1 From 7905e556a01cb306fa8df9630e15ebc10e50e5b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:58 -0600 Subject: common/fpsensor/fpsensor_crypto.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Id287d6745fbc756a138cadcc5199ed01d5ef9d2f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729630 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- common/fpsensor/fpsensor_crypto.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/common/fpsensor/fpsensor_crypto.c b/common/fpsensor/fpsensor_crypto.c index 73d7aca681..c4e79e9495 100644 --- a/common/fpsensor/fpsensor_crypto.c +++ b/common/fpsensor/fpsensor_crypto.c @@ -55,8 +55,8 @@ static void hkdf_extract(uint8_t *prk, const uint8_t *salt, size_t salt_size, } static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size, - uint8_t *prk, size_t prk_size, - uint8_t *info, size_t info_size) + uint8_t *prk, size_t prk_size, uint8_t *info, + size_t info_size) { uint8_t key_buf[SHA256_DIGEST_SIZE]; uint8_t message_buf[SHA256_DIGEST_SIZE + 1]; @@ -83,8 +83,8 @@ static int hkdf_expand_one_step(uint8_t *out_key, size_t out_key_size, return EC_SUCCESS; } -int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk, - size_t prk_size, const uint8_t *info, size_t info_size) +int hkdf_expand(uint8_t *out_key, size_t L, const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size) { /* * "Expand" step of HKDF. @@ -216,11 +216,9 @@ int derive_encryption_key(uint8_t *out_key, const uint8_t *salt) return ret; } -int aes_gcm_encrypt(const uint8_t *key, int key_size, - const uint8_t *plaintext, - uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - uint8_t *tag, int tag_size) +int aes_gcm_encrypt(const uint8_t *key, int key_size, const uint8_t *plaintext, + uint8_t *ciphertext, int text_size, const uint8_t *nonce, + int nonce_size, uint8_t *tag, int tag_size) { int res; AES_KEY aes_key; @@ -251,8 +249,8 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size, int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext, const uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - const uint8_t *tag, int tag_size) + const uint8_t *nonce, int nonce_size, const uint8_t *tag, + int tag_size) { int res; AES_KEY aes_key; -- cgit v1.2.1 From fa35afbabc935ae27dabe06a9141438b742d5c0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:02 -0600 Subject: test/cortexm_fpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7de4478f6d85568aca197b0c4b8d357e350023b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730496 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/cortexm_fpu.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/test/cortexm_fpu.c b/test/cortexm_fpu.c index 8564e2a4ef..a5e944f9d0 100644 --- a/test/cortexm_fpu.c +++ b/test/cortexm_fpu.c @@ -33,11 +33,7 @@ static float divf(float a, float b) { float result; - asm volatile( - "fdivs %0, %1, %2" - : "=w"(result) - : "w"(a), "w"(b) - ); + asm volatile("fdivs %0, %1, %2" : "=w"(result) : "w"(a), "w"(b)); return result; } -- cgit v1.2.1 From 4d5c516b98022ecca57081e74473d6f262511bba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:35 -0600 Subject: chip/stm32/config-stm32f373.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd76e3d86c568d8696c59b94c0ec2b0540b7c6e0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729473 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f373.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h index 7694db4421..7f8f812774 100644 --- a/chip/stm32/config-stm32f373.h +++ b/chip/stm32/config-stm32f373.h @@ -5,24 +5,24 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x2000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x2000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 81 /* STM32F3 uses the older 4 byte aligned access mechanism */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1fffd800 +#define STM32_DFU_BASE 0x1fffd800 -- cgit v1.2.1 From 3710eb99e7c781cece8dcfec949be05fa20f9e22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:46 -0600 Subject: board/scarlet/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ba9bc5639cab0074ed06030d2ca1a1c6aab19cd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728914 Reviewed-by: Jeremy Bettis --- board/scarlet/battery.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/board/scarlet/battery.c b/board/scarlet/battery.c index 0be4cc93e2..96cc0e557e 100644 --- a/board/scarlet/battery.c +++ b/board/scarlet/battery.c @@ -32,11 +32,7 @@ static uint8_t batt_id = 0xff; /* Do not change the enum values. We directly use strap gpio level to index. */ -enum battery_type { - BATTERY_SIMPLO = 0, - BATTERY_AETECH, - BATTERY_COUNT -}; +enum battery_type { BATTERY_SIMPLO = 0, BATTERY_AETECH, BATTERY_COUNT }; static const struct battery_info info[] = { [BATTERY_SIMPLO] = { @@ -192,7 +188,7 @@ int charger_profile_override(struct charge_state_data *curr) else { for (temp_zone = 0; temp_zone < TEMP_ZONE_COUNT; temp_zone++) { if (bat_temp_c < - temp_zones[batt_id][temp_zone].temp_max) + temp_zones[batt_id][temp_zone].temp_max) break; } } @@ -233,9 +229,10 @@ int charger_profile_override(struct charge_state_data *curr) curr->requested_voltage = temp_zones[batt_id][temp_zone].desired_voltage; - curr->requested_current = (charge_phase) ? - CHARGE_PHASE_CHANGED_CURRENT_MA : - temp_zones[batt_id][temp_zone].desired_current; + curr->requested_current = + (charge_phase) ? + CHARGE_PHASE_CHANGED_CURRENT_MA : + temp_zones[batt_id][temp_zone].desired_current; break; case TEMP_OUT_OF_RANGE: curr->requested_current = curr->requested_voltage = 0; @@ -281,8 +278,7 @@ static void board_charge_termination(void) te = 1; } } -DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, - board_charge_termination, +DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, board_charge_termination, HOOK_PRIO_DEFAULT); /* Customs options controllable by host command. */ -- cgit v1.2.1 From 4d347b6e3c32a955d4b4f36db04ac9c4de51b685 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:02 -0600 Subject: board/vell/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If009fe5f07f3a65537ee10731d0867c5f9b186a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729068 Reviewed-by: Jeremy Bettis --- board/vell/thermal.c | 58 ++++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/board/vell/thermal.c b/board/vell/thermal.c index e72b86e3b1..45f3813d01 100644 --- a/board/vell/thermal.c +++ b/board/vell/thermal.c @@ -15,7 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -37,27 +37,27 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {48, 60, 48, 47, -1}, - .off = {99, 99, 99, 99, -1}, - .rpm = {0}, + .on = { 48, 60, 48, 47, -1 }, + .off = { 99, 99, 99, 99, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {50, 60, 50, 49, -1}, - .off = {47, 99, 47, 46, -1}, - .rpm = {3600}, + .on = { 50, 60, 50, 49, -1 }, + .off = { 47, 99, 47, 46, -1 }, + .rpm = { 3600 }, }, { /* level 2 */ - .on = {53, 60, 53, 52, -1}, - .off = {49, 99, 49, 48, -1}, - .rpm = {4100}, + .on = { 53, 60, 53, 52, -1 }, + .off = { 49, 99, 49, 48, -1 }, + .rpm = { 4100 }, }, { /* level 3 */ - .on = {100, 100, 100, 100, -1}, - .off = {51, 59, 51, 50, -1}, - .rpm = {5500}, + .on = { 100, 100, 100, 100, -1 }, + .off = { 51, 59, 51, 50, -1 }, + .rpm = { 5500 }, }, }; @@ -82,33 +82,31 @@ static int fan_table_to_rpm(int fan, int *temp) temp[TEMP_SENSOR_4_DDR] < prev_tmp[TEMP_SENSOR_4_DDR]) { for (i = current_level; i > 0; i--) { if (temp[TEMP_SENSOR_1_SOC] < - fan_table[i].off[TEMP_SENSOR_1_SOC] && + fan_table[i].off[TEMP_SENSOR_1_SOC] && temp[TEMP_SENSOR_2_CHARGER] < - fan_table[i].off[TEMP_SENSOR_2_CHARGER] && + fan_table[i].off[TEMP_SENSOR_2_CHARGER] && temp[TEMP_SENSOR_3_WWAN] < - fan_table[i].off[TEMP_SENSOR_3_WWAN] && + fan_table[i].off[TEMP_SENSOR_3_WWAN] && temp[TEMP_SENSOR_4_DDR] < - fan_table[i].off[TEMP_SENSOR_4_DDR]) + fan_table[i].off[TEMP_SENSOR_4_DDR]) current_level = i - 1; else break; } } else if (temp[TEMP_SENSOR_1_SOC] > prev_tmp[TEMP_SENSOR_1_SOC] || temp[TEMP_SENSOR_2_CHARGER] > - prev_tmp[TEMP_SENSOR_2_CHARGER] || - temp[TEMP_SENSOR_3_WWAN] > - prev_tmp[TEMP_SENSOR_3_WWAN] || - temp[TEMP_SENSOR_4_DDR] > - prev_tmp[TEMP_SENSOR_4_DDR]) { + prev_tmp[TEMP_SENSOR_2_CHARGER] || + temp[TEMP_SENSOR_3_WWAN] > prev_tmp[TEMP_SENSOR_3_WWAN] || + temp[TEMP_SENSOR_4_DDR] > prev_tmp[TEMP_SENSOR_4_DDR]) { for (i = current_level; i < NUM_FAN_LEVELS; i++) { if (temp[TEMP_SENSOR_1_SOC] > - fan_table[i].on[TEMP_SENSOR_1_SOC] || + fan_table[i].on[TEMP_SENSOR_1_SOC] || (temp[TEMP_SENSOR_2_CHARGER] > - fan_table[i].on[TEMP_SENSOR_2_CHARGER] && - temp[TEMP_SENSOR_3_WWAN] > - fan_table[i].on[TEMP_SENSOR_3_WWAN]) || + fan_table[i].on[TEMP_SENSOR_2_CHARGER] && + temp[TEMP_SENSOR_3_WWAN] > + fan_table[i].on[TEMP_SENSOR_3_WWAN]) || temp[TEMP_SENSOR_4_DDR] > - fan_table[i].on[TEMP_SENSOR_4_DDR]) + fan_table[i].on[TEMP_SENSOR_4_DDR]) current_level = i + 1; else break; @@ -129,10 +127,8 @@ static int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } -- cgit v1.2.1 From 9cc9704f80bed8a309b4ed2fad7fa6c2326be838 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:15 -0600 Subject: board/waddledoo/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie70891aefeae7839ae136dd05bbea7f16903f528 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729102 Reviewed-by: Jeremy Bettis --- board/waddledoo/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledoo/cbi_ssfc.c b/board/waddledoo/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/waddledoo/cbi_ssfc.c +++ b/board/waddledoo/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From b96563649646f858cc9a5ff1ff3657e32c1a1a28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:36 -0600 Subject: chip/stm32/hwtimer32.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50e2fae0bdbdb95233050a603b39439109637e63 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729513 Reviewed-by: Jeremy Bettis --- chip/stm32/hwtimer32.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index f64eab989a..d53021d6a9 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -115,7 +115,7 @@ void __hw_timer_enable_clock(int n, int enable) #endif #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ -defined(CHIP_FAMILY_STM32H7) + defined(CHIP_FAMILY_STM32H7) if (n == 14) { reg = &STM32_RCC_APB1ENR; mask = STM32_RCC_PB1_TIM14; @@ -157,7 +157,7 @@ defined(CHIP_FAMILY_STM32H7) reg = &STM32_RCC_APB2ENR; mask = (n == 1) ? STM32_RCC_APB2ENR_TIM1EN : (n == 15) ? STM32_RCC_APB2ENR_TIM15EN : - STM32_RCC_APB2ENR_TIM16EN; + STM32_RCC_APB2ENR_TIM16EN; } #else if (n >= 2 && n <= 7) { @@ -213,12 +213,12 @@ static void update_prescaler(void) #ifdef CONFIG_WATCHDOG_HELP /* Watchdog timer runs at 1KHz */ STM32_TIM_PSC(TIM_WATCHDOG) = - (clock_get_timer_freq() / SECOND * MSEC)- 1; -#endif /* CONFIG_WATCHDOG_HELP */ + (clock_get_timer_freq() / SECOND * MSEC) - 1; +#endif /* CONFIG_WATCHDOG_HELP */ } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); #endif /* CHIP_FAMILY_STM32L || CHIP_FAMILY_STM32L4 || */ - /* CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */ +/* CHIP_FAMILY_STM32F4 || CHIP_FAMILY_STM32H7 */ int __hw_clock_source_init(uint32_t start_t) { @@ -285,9 +285,11 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) - = {IRQ_WD, 0}; /* put the watchdog at the highest - priority */ + __attribute__((section(".rodata.irqprio"))) = { IRQ_WD, + 0 }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { @@ -320,8 +322,7 @@ void hwtimer_setup_watchdog(void) STM32_TIM_ARR(TIM_WATCHDOG) = CONFIG_AUX_TIMER_PERIOD_MS; /* Update prescaler: watchdog timer runs at 1KHz */ - STM32_TIM_PSC(TIM_WATCHDOG) = - (freq / SECOND * MSEC) - 1; + STM32_TIM_PSC(TIM_WATCHDOG) = (freq / SECOND * MSEC) - 1; } #ifdef CHIP_FAMILY_STM32L4 else { @@ -351,4 +352,4 @@ void hwtimer_reset_watchdog(void) STM32_TIM_CNT(TIM_WATCHDOG) = 0x0000; } -#endif /* CONFIG_WATCHDOG_HELP */ +#endif /* CONFIG_WATCHDOG_HELP */ -- cgit v1.2.1 From 0862dcec02d7e90f5cead2a57cee65501aca7b34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:59 -0600 Subject: zephyr/shim/src/tasks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I331c4780ccdc5ea9fe2666e6f88e8bac836592af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727465 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/tasks.c | 42 ++++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/zephyr/shim/src/tasks.c b/zephyr/shim/src/tasks.c index 248d5e9607..3225bdb196 100644 --- a/zephyr/shim/src/tasks.c +++ b/zephyr/shim/src/tasks.c @@ -15,9 +15,8 @@ /* Ensure that the idle task is at lower priority than lowest priority task. */ BUILD_ASSERT(EC_TASK_PRIORITY(EC_TASK_PRIO_LOWEST) < K_IDLE_PRIO, - "CONFIG_NUM_PREEMPT_PRIORITIES too small, some tasks would run at " - "idle priority"); - + "CONFIG_NUM_PREEMPT_PRIORITIES too small, some tasks would run at " + "idle priority"); /* Declare all task stacks here */ #define CROS_EC_TASK(name, e, p, size, pr) \ @@ -68,21 +67,19 @@ struct task_ctx_data { struct task_ctx_base_data base; }; -#define CROS_EC_TASK(_name, _entry, _parameter, _size, _prio) \ - { \ - .entry = _entry, \ - .parameter = _parameter, \ - .stack = _name##_STACK, \ - .stack_size = _size, \ - .priority = EC_TASK_PRIORITY(_prio), \ - COND_CODE_1(CONFIG_THREAD_NAME, (.name = #_name,), ()) \ - }, +#define CROS_EC_TASK(_name, _entry, _parameter, _size, _prio) \ + { .entry = _entry, \ + .parameter = _parameter, \ + .stack = _name##_STACK, \ + .stack_size = _size, \ + .priority = EC_TASK_PRIORITY(_prio), \ + COND_CODE_1(CONFIG_THREAD_NAME, (.name = #_name, ), ()) }, #define TASK_TEST(_name, _entry, _parameter, _size) \ CROS_EC_TASK(_name, _entry, _parameter, _size) const static struct task_ctx_cfg shimmed_tasks_cfg[TASK_ID_COUNT] = { CROS_EC_TASK_LIST #ifdef TEST_BUILD - [TASK_ID_TEST_RUNNER] = {}, + [TASK_ID_TEST_RUNNER] = {}, #endif }; @@ -238,8 +235,7 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us) return events & event_mask; } -static void task_entry(void *task_context_cfg, - void *task_context_data, +static void task_entry(void *task_context_cfg, void *task_context_data, void *unused1) { ARG_UNUSED(task_context_data); @@ -335,17 +331,11 @@ void start_ec_tasks(void) * comment in config.h for CONFIG_TASK_LIST for existing flags * implementation. */ - data->zephyr_tid = k_thread_create( - &data->zephyr_thread, - cfg->stack, - cfg->stack_size, - task_entry, - (void *)cfg, - data, - NULL, - cfg->priority, - 0, - K_NO_WAIT); + data->zephyr_tid = k_thread_create(&data->zephyr_thread, + cfg->stack, cfg->stack_size, + task_entry, (void *)cfg, + data, NULL, cfg->priority, 0, + K_NO_WAIT); #ifdef CONFIG_THREAD_NAME /* Name thread for debugging */ -- cgit v1.2.1 From 76906bbcee3aac4b5375ad8ad49aa451a4849a3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:46 -0600 Subject: common/usbc_intr_task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0d38605c8c9c73d1f6b787fa96a124967a0155c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729800 Reviewed-by: Jeremy Bettis --- common/usbc_intr_task.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/common/usbc_intr_task.c b/common/usbc_intr_task.c index 0532645a35..258c068b78 100644 --- a/common/usbc_intr_task.c +++ b/common/usbc_intr_task.c @@ -18,19 +18,19 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Events for pd_interrupt_handler_task */ -#define PD_PROCESS_INTERRUPT BIT(0) +#define PD_PROCESS_INTERRUPT BIT(0) /* * Theoretically, we may need to support up to 480 USB-PD packets per second for * intensive operations such as FW update over PD. This value has tested well * preventing watchdog resets with a single bad port partner plugged in. */ -#define ALERT_STORM_MAX_COUNT 480 -#define ALERT_STORM_INTERVAL SECOND +#define ALERT_STORM_MAX_COUNT 480 +#define ALERT_STORM_INTERVAL SECOND static uint8_t pd_int_task_id[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -57,8 +57,7 @@ static void service_one_port(int port) tcpc_alert(port); now = get_time(); - if (timestamp_expired(storm_tracker[port].time, - &now)) { + if (timestamp_expired(storm_tracker[port].time, &now)) { /* Reset timer into future */ storm_tracker[port].time.val = now.val + ALERT_STORM_INTERVAL; @@ -91,7 +90,7 @@ __overridable void board_process_pd_alert(int port) */ void pd_interrupt_handler_task(void *p) { - const int port = (int) ((intptr_t) p); + const int port = (int)((intptr_t)p); const int port_mask = (PD_STATUS_TCPC_ALERT_0 << port); ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); @@ -122,7 +121,6 @@ void pd_interrupt_handler_task(void *p) */ while ((tcpc_get_alert_status() & port_mask) && pd_is_port_enabled(port)) { - service_one_port(port); } @@ -147,7 +145,7 @@ BUILD_ASSERT(PD_STATUS_TCPC_ALERT_3 == (PD_STATUS_TCPC_ALERT_0 << 3)); void pd_shared_alert_task(void *p) { - const int sources_mask = (int) ((intptr_t) p); + const int sources_mask = (int)((intptr_t)p); int want_alerts = 0; int port; int port_mask; -- cgit v1.2.1 From 1ce24d558ad030ae66b995e1b5fce5f2d7134541 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:59 -0600 Subject: include/util.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4ef1e28625a1dbf3e14eb173155855b38a37d023 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730451 Reviewed-by: Jeremy Bettis --- include/util.h | 92 ++++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/include/util.h b/include/util.h index e39b81ccdf..04b44accb7 100644 --- a/include/util.h +++ b/include/util.h @@ -12,7 +12,7 @@ #include "compile_time_macros.h" #include "panic.h" -#include "builtin/assert.h" /* For ASSERT(). */ +#include "builtin/assert.h" /* For ASSERT(). */ #include #include #ifdef CONFIG_ZEPHYR @@ -27,21 +27,21 @@ extern "C" { #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y)) #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y)) #ifndef MAX -#define MAX(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MAX(temp_a, temp_b); \ +#define MAX(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MAX(temp_a, temp_b); \ }) #endif #ifndef MIN -#define MIN(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MIN(temp_a, temp_b); \ +#define MIN(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MIN(temp_a, temp_b); \ }) #endif #ifndef NULL @@ -69,11 +69,11 @@ extern "C" { * contains the base struct. This requires knowing where in the contained * struct the base struct resides, this is the member parameter to downcast. */ -#define DOWNCAST(pointer, type, member) \ - ((type *)(((uint8_t *) pointer) - offsetof(type, member))) +#define DOWNCAST(pointer, type, member) \ + ((type *)(((uint8_t *)pointer) - offsetof(type, member))) /* True of x is a power of two */ -#define POWER_OF_TWO(x) ((x) && !((x) & ((x) - 1))) +#define POWER_OF_TWO(x) ((x) && !((x) & ((x)-1))) /* Macro to check if the value is in range */ #ifndef CONFIG_ZEPHYR @@ -84,7 +84,7 @@ extern "C" { * macros for integer division with various rounding variants * default integer division rounds down. */ -#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y)) +#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y)) #define DIV_ROUND_NEAREST(x, y) (((x) + ((y) / 2)) / (y)) /* @@ -93,12 +93,12 @@ extern "C" { * Swapping composites (e.g. a+b, x++) doesn't make sense. So, and * can only be a variable (x) or a pointer reference (*x) without operator. */ -#define swap(a, b) \ - do { \ +#define swap(a, b) \ + do { \ typeof(a) __t__; \ - __t__ = a; \ - a = b; \ - b = __t__; \ + __t__ = a; \ + a = b; \ + b = __t__; \ } while (0) #ifndef HIDE_EC_STDLIB @@ -173,7 +173,7 @@ char *strzcpy(char *dest, const char *src, int len); * Other strings return 0 and leave *dest unchanged. */ int parse_bool(const char *s, int *dest); -#endif /* !HIDE_EC_STDLIB */ +#endif /* !HIDE_EC_STDLIB */ /** * Constant time implementation of memcmp to avoid timing side channels. @@ -234,7 +234,6 @@ int alignment_log2(unsigned int x); */ void reverse(void *dest, size_t len); - /****************************************************************************/ /* Conditional stuff. * @@ -261,25 +260,49 @@ typedef uint8_t cond_t; /* Initialize a conditional to a specific state. Do this first. */ void cond_init(cond_t *c, int boolean); -static inline void cond_init_false(cond_t *c) { cond_init(c, 0); } -static inline void cond_init_true(cond_t *c) { cond_init(c, 1); } +static inline void cond_init_false(cond_t *c) +{ + cond_init(c, 0); +} +static inline void cond_init_true(cond_t *c) +{ + cond_init(c, 1); +} /* Set the current state. Do this as often as you like. */ void cond_set(cond_t *c, int boolean); -static inline void cond_set_false(cond_t *c) { cond_set(c, 0); } -static inline void cond_set_true(cond_t *c) { cond_set(c, 1); } +static inline void cond_set_false(cond_t *c) +{ + cond_set(c, 0); +} +static inline void cond_set_true(cond_t *c) +{ + cond_set(c, 1); +} /* Get the current state. Do this as often as you like. */ int cond_is(cond_t *c, int boolean); -static inline int cond_is_false(cond_t *c) { return cond_is(c, 0); } -static inline int cond_is_true(cond_t *c) { return cond_is(c, 1); } +static inline int cond_is_false(cond_t *c) +{ + return cond_is(c, 0); +} +static inline int cond_is_true(cond_t *c) +{ + return cond_is(c, 1); +} /* See if the state has transitioned. If it has, the corresponding function * will return true ONCE only, until it's changed back. */ int cond_went(cond_t *c, int boolean); -static inline int cond_went_false(cond_t *c) { return cond_went(c, 0); } -static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); } +static inline int cond_went_false(cond_t *c) +{ + return cond_went(c, 0); +} +static inline int cond_went_true(cond_t *c) +{ + return cond_went(c, 1); +} /****************************************************************************/ /* Console command parsing */ @@ -287,8 +310,7 @@ static inline int cond_went_true(cond_t *c) { return cond_went(c, 1); } /* Parse command-line arguments given integer shift value to obtain * offset and size. */ -int parse_offset_size(int argc, char **argv, int shift, - int *offset, int *size); +int parse_offset_size(int argc, char **argv, int shift, int *offset, int *size); /** * Print binary in hex and ASCII @@ -396,4 +418,4 @@ int ternary_from_bits(int *bits, int nbits); } #endif -#endif /* __CROS_EC_UTIL_H */ +#endif /* __CROS_EC_UTIL_H */ -- cgit v1.2.1 From e1b66af275744f0fed23073d42a61e31433e9878 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:12 -0600 Subject: board/servo_v4p1/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11c2464503faa4b7314fc11c76736cb635ebbecc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728934 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_pd_config.h | 60 +++++++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h index 7e97d68a11..0b21f2b063 100644 --- a/board/servo_v4p1/usb_pd_config.h +++ b/board/servo_v4p1/usb_pd_config.h @@ -47,26 +47,27 @@ #define CONFIG_HW_CRC /* Servo v4 CC configuration */ -#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ -#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ -#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ -#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ -#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ -#define CC_POLARITY BIT(5) /* CC polarity */ -#define CC_EMCA_SERVO BIT(6) /* - * Emulate Electronically Marked Cable Assembly - * (EMCA) servo (or non-EMCA) - */ -#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */ +#define CC_DETACH BIT(0) /* Emulate detach: both CC open */ +#define CC_DISABLE_DTS BIT(1) /* Apply resistors to single or both CC? */ +#define CC_ALLOW_SRC BIT(2) /* Allow charge through by policy? */ +#define CC_ENABLE_DRP BIT(3) /* Enable dual-role port */ +#define CC_SNK_WITH_PD BIT(4) /* Force enabling PD comm for sink role */ +#define CC_POLARITY BIT(5) /* CC polarity */ +#define CC_EMCA_SERVO \ + BIT(6) /* \ + * Emulate Electronically Marked Cable Assembly \ + * (EMCA) servo (or non-EMCA) \ + */ +#define CC_FASTBOOT_DFP BIT(7) /* Allow mux uServo->Fastboot on DFP */ /* Servo v4 DP alt-mode configuration */ -#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ -#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ -#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ -#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */ -#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */ -#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */ -#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */ +#define ALT_DP_ENABLE BIT(0) /* Enable DP alt-mode or not */ +#define ALT_DP_PIN_C BIT(1) /* Pin assignment C supported */ +#define ALT_DP_PIN_D BIT(2) /* Pin assignment D supported */ +#define ALT_DP_MF_PREF BIT(3) /* Multi-Function preferred */ +#define ALT_DP_PLUG BIT(4) /* Plug or receptacle */ +#define ALT_DP_OVERRIDE_HPD BIT(5) /* Override the HPD signal */ +#define ALT_DP_HPD_LVL BIT(6) /* HPD level if overridden */ /* TX uses SPI1 on PB3-4 for CHG port, SPI2 on PB 13-14 for DUT port */ #define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS) @@ -89,14 +90,14 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_DUT : TIM_TX_CCR_CHG) #define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_DUT : TIM_RX_CCR_CHG) -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 /* * EXTI line 21 is connected to the CMP1 output, * EXTI line 22 is connected to the CMP2 output, * CHG uses CMP2, and DUT uses CMP1. */ -#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : BIT(22)) +#define EXTI_COMP_MASK(p) ((p) ? (1 << 21) : BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -188,13 +189,23 @@ static inline void pd_select_polarity(int port, int polarity) if (port == CHG) { /* CHG use the right comparator inverted input for COMP2 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | - (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */ - : STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */ + (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: + C0_CC2 + */ + : + STM32_COMP_CMP2INSEL_INM6); /* PA2: + C0_CC1 + */ } else { /* DUT use the right comparator inverted input for COMP1 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */ - : STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */ + (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: + C1_CC2 + */ + : + STM32_COMP_CMP1INSEL_INM6); /* PA0: + C1_CC1 + */ } } @@ -274,7 +285,6 @@ static inline void pd_config_init(int port, uint8_t power_role) /* Initialize TX pins and put them in Hi-Z */ pd_tx_init(); - } int pd_adc_read(int port, int cc); -- cgit v1.2.1 From b827b974e1158f8b4b30b418595e16f66248b432 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:38 -0600 Subject: zephyr/test/drivers/src/smart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6865db134b083429fc2c3cca7efec5dd30d68c8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730944 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/smart.c | 93 ++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 48 deletions(-) diff --git a/zephyr/test/drivers/src/smart.c b/zephyr/test/drivers/src/smart.c index 3628a68d3e..6de42efe9c 100644 --- a/zephyr/test/drivers/src/smart.c +++ b/zephyr/test/drivers/src/smart.c @@ -18,7 +18,7 @@ #include "battery_smart.h" #include "test/drivers/test_state.h" -#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) +#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) /** Test all simple getters */ ZTEST_USER(smart_battery, test_battery_getters) @@ -40,22 +40,22 @@ ZTEST_USER(smart_battery, test_battery_getters) zassert_equal(expected, word, "%d != %d", expected, word); zassert_equal(EC_SUCCESS, battery_cycle_count(&word), NULL); - zassert_equal(bat->cycle_count, word, "%d != %d", - bat->cycle_count, word); + zassert_equal(bat->cycle_count, word, "%d != %d", bat->cycle_count, + word); zassert_equal(EC_SUCCESS, battery_design_voltage(&word), NULL); zassert_equal(bat->design_mv, word, "%d != %d", bat->design_mv, word); zassert_equal(EC_SUCCESS, battery_serial_number(&word), NULL); zassert_equal(bat->sn, word, "%d != %d", bat->sn, word); zassert_equal(EC_SUCCESS, get_battery_manufacturer_name(block, 32), NULL); - zassert_mem_equal(block, bat->mf_name, bat->mf_name_len, - "%s != %s", block, bat->mf_name); + zassert_mem_equal(block, bat->mf_name, bat->mf_name_len, "%s != %s", + block, bat->mf_name); zassert_equal(EC_SUCCESS, battery_device_name(block, 32), NULL); - zassert_mem_equal(block, bat->dev_name, bat->dev_name_len, - "%s != %s", block, bat->dev_name); + zassert_mem_equal(block, bat->dev_name, bat->dev_name_len, "%s != %s", + block, bat->dev_name); zassert_equal(EC_SUCCESS, battery_device_chemistry(block, 32), NULL); - zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len, - "%s != %s", block, bat->dev_chem); + zassert_mem_equal(block, bat->dev_chem, bat->dev_chem_len, "%s != %s", + block, bat->dev_chem); word = battery_get_avg_current(); zassert_equal(bat->avg_cur, word, "%d != %d", bat->avg_cur, word); word = battery_get_avg_voltage(); @@ -114,7 +114,6 @@ ZTEST_USER(smart_battery, test_battery_get_capacity) zassert_false(bat->mode & MODE_CAPACITY, "mAh mode not forced"); } - /** Test battery status */ ZTEST_USER(smart_battery, test_battery_status) { @@ -369,7 +368,8 @@ ZTEST_USER(smart_battery, test_battery_mfacc) len = 2; zassert_equal(EC_ERROR_INVAL, sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf, - len), NULL); + len), + NULL); /* Set correct length for rest of the test */ len = 10; @@ -378,13 +378,15 @@ ZTEST_USER(smart_battery, test_battery_mfacc) i2c_common_emul_set_write_fail_reg(emul, SB_MANUFACTURER_ACCESS); zassert_equal(EC_ERROR_INVAL, sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf, - len), NULL); + len), + NULL); i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test fail on reading manufacturer data (custom handler is not set) */ zassert_equal(EC_ERROR_INVAL, sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf, - len), NULL); + len), + NULL); /* Set arbitrary manufacturer data */ for (int i = 1; i < len; i++) { @@ -402,7 +404,8 @@ ZTEST_USER(smart_battery, test_battery_mfacc) /* Test error when mf_data doesn't start with command */ zassert_equal(EC_ERROR_UNKNOWN, sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf, - len), NULL); + len), + NULL); /* Set beginning of the manufacturer data */ mf_data[1] = cmd & 0xff; @@ -411,7 +414,8 @@ ZTEST_USER(smart_battery, test_battery_mfacc) /* Test successful manufacturer data read */ zassert_equal(EC_SUCCESS, sb_read_mfgacc(cmd, SB_ALT_MANUFACTURER_ACCESS, recv_buf, - len), NULL); + len), + NULL); /* Compare received data ignoring length byte */ zassert_mem_equal(mf_data + 1, recv_buf, len - 1, NULL); @@ -434,30 +438,25 @@ ZTEST_USER(smart_battery, test_battery_fake_charge) bat = sbat_emul_get_bat_data(emul); /* Success on command with no argument */ - zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "battfake"), NULL); + zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "battfake"), + NULL); /* Fail on command with argument which is not a number */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "battfake test"), NULL); + shell_execute_cmd(get_ec_shell(), "battfake test"), NULL); /* Fail on command with charge level above 100% */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "battfake 123"), NULL); + shell_execute_cmd(get_ec_shell(), "battfake 123"), NULL); /* Fail on command with charge level below 0% */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "battfake -23"), NULL); + shell_execute_cmd(get_ec_shell(), "battfake -23"), NULL); /* Set fake charge level */ fake_charge = 65; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "battfake 65"), NULL); + shell_execute_cmd(get_ec_shell(), "battfake 65"), NULL); /* Test that fake charge level is applied */ flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE; @@ -484,18 +483,17 @@ ZTEST_USER(smart_battery, test_battery_fake_charge) /* Disable fake charge level */ zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "battfake -1"), NULL); + shell_execute_cmd(get_ec_shell(), "battfake -1"), NULL); /* Test that fake charge level is not applied */ flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE; battery_get_params(&batt); zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags); charge = 100 * bat->cap / bat->full_cap; - zassert_equal(charge, batt.state_of_charge, "%d%% != %d%%", - charge, batt.state_of_charge); - zassert_equal(bat->cap, batt.remaining_capacity, "%d != %d", - bat->cap, batt.remaining_capacity); + zassert_equal(charge, batt.state_of_charge, "%d%% != %d%%", charge, + batt.state_of_charge); + zassert_equal(bat->cap, batt.remaining_capacity, "%d != %d", bat->cap, + batt.remaining_capacity); } /** Test battery fake temperature set and read */ @@ -512,48 +510,47 @@ ZTEST_USER(smart_battery, test_battery_fake_temperature) /* Success on command with no argument */ zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "batttempfake"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake"), NULL); /* Fail on command with argument which is not a number */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "batttempfake test"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake test"), + NULL); /* Fail on command with too high temperature (above 500.0 K) */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "batttempfake 5001"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake 5001"), + NULL); /* Fail on command with too low temperature (below 0 K) */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "batttempfake -23"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake -23"), + NULL); /* Set fake temperature */ fake_temp = 2840; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "batttempfake 2840"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake 2840"), + NULL); /* Test that fake temperature is applied */ flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE; battery_get_params(&batt); zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags); - zassert_equal(fake_temp, batt.temperature, "%d != %d", - fake_temp, batt.temperature); + zassert_equal(fake_temp, batt.temperature, "%d != %d", fake_temp, + batt.temperature); /* Disable fake temperature */ zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "batttempfake -1"), NULL); + shell_execute_cmd(get_ec_shell(), "batttempfake -1"), + NULL); /* Test that fake temperature is not applied */ flags = BATT_FLAG_WANT_CHARGE | BATT_FLAG_RESPONSIVE; battery_get_params(&batt); zassert_equal(flags, batt.flags, "0x%x != 0x%x", flags, batt.flags); - zassert_equal(bat->temp, batt.temperature, "%d != %d", - bat->temp, batt.temperature); + zassert_equal(bat->temp, batt.temperature, "%d != %d", bat->temp, + batt.temperature); } ZTEST_SUITE(smart_battery, drivers_predicate_post_main, NULL, NULL, NULL, NULL); -- cgit v1.2.1 From 7d376c11ed9389813e8564e6bc81a6f20e7cd7da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:20 -0600 Subject: test/flash_physical.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I370b29c5c63cee6ac46f1865de2ae1f46eba6b16 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730476 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/flash_physical.c | 1 - 1 file changed, 1 deletion(-) diff --git a/test/flash_physical.c b/test/flash_physical.c index 06dd495254..9c8277de7c 100644 --- a/test/flash_physical.c +++ b/test/flash_physical.c @@ -30,7 +30,6 @@ struct flash_info flash_info = { #error "Flash info not defined for this chip. Please add it." #endif - test_static int test_lock_option_bytes(void) { TEST_EQ(flash_option_bytes_locked(), true, "%d"); -- cgit v1.2.1 From 7d13d5a91605bcea34063f82a1eba5717b7fe0d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:59 -0600 Subject: driver/led/aw20198.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id77ee1432b5ddbcb96248245282921dcce2194c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730012 Reviewed-by: Jeremy Bettis --- driver/led/aw20198.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/driver/led/aw20198.c b/driver/led/aw20198.c index 1322c08a09..56611bce17 100644 --- a/driver/led/aw20198.c +++ b/driver/led/aw20198.c @@ -16,12 +16,12 @@ #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "AW20198: " fmt, ##args) #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "AW20198: " fmt, ##args) -#define BUF_SIZE (SIZE_OF_RGB * AW20198_GRID_SIZE) +#define BUF_SIZE (SIZE_OF_RGB * AW20198_GRID_SIZE) static int aw20198_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value) { - return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, - &addr, sizeof(addr), value, sizeof(*value)); + return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, &addr, + sizeof(addr), value, sizeof(*value)); } static int aw20198_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) @@ -31,8 +31,8 @@ static int aw20198_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) [1] = value, }; - return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, - buf, sizeof(buf), NULL, 0); + return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, sizeof(buf), + NULL, 0); } static int aw20198_set_page(struct rgbkbd *ctx, uint8_t page) @@ -103,8 +103,8 @@ static int aw20198_set_color(struct rgbkbd *ctx, uint8_t offset, buf[i * SIZE_OF_RGB + 3] = color[i].b; } - return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, - buf, frame_len, NULL, 0); + return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len, + NULL, 0); } static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset, @@ -131,8 +131,8 @@ static int aw20198_set_scale(struct rgbkbd *ctx, uint8_t offset, buf[i * SIZE_OF_RGB + 3] = scale.b; } - return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, - buf, frame_len, NULL, 0); + return i2c_xfer(ctx->cfg->i2c, AW20198_I2C_ADDR_FLAG, buf, frame_len, + NULL, 0); } static int aw20198_set_gcc(struct rgbkbd *ctx, uint8_t level) @@ -159,7 +159,7 @@ static int aw20198_init(struct rgbkbd *ctx) rv = aw20198_get_config(ctx, AW20198_REG_GCR, &u8); if (rv) { return rv; - } + } u8 &= ~AW20198_REG_GCR_SWSEL_MASK; u8 |= ((ctx->cfg->col_len - 1) << AW20198_REG_GCR_SWSEL_SHIFT); rv = aw20198_write(ctx, AW20198_REG_GCR, u8); -- cgit v1.2.1 From 1ec38bcdacb770c73e6c64f8b7e3d0edc623cd3f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:53 -0600 Subject: zephyr/drivers/cros_flash/cros_flash_it8xxx2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I321806e64afe85a840644b8e8c5db4c4d1b09373 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730669 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_flash/cros_flash_it8xxx2.c | 30 +++++++++++++------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c index 7be6ef86fb..1b2dd723c7 100644 --- a/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c +++ b/zephyr/drivers/cros_flash/cros_flash_it8xxx2.c @@ -102,7 +102,7 @@ static int cros_flash_it8xxx2_init(const struct device *dev) reset_flags = system_get_reset_flags(); prot_flags = crec_flash_get_protect(); unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; + EC_FLASH_PROTECT_ERROR_INCONSISTENT; /* * If we have already jumped between images, an earlier image could @@ -113,12 +113,12 @@ static int cros_flash_it8xxx2_init(const struct device *dev) if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { /* Protect the entire flash of host interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_HOST); /* Protect the entire flash of DBGR interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_DBGR); /* * Write protect is asserted. If we want RO flash protected, @@ -126,8 +126,9 @@ static int cros_flash_it8xxx2_init(const struct device *dev) */ if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); + int rv = + crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, + EC_FLASH_PROTECT_RO_NOW); if (rv) return rv; @@ -206,13 +207,13 @@ static int cros_flash_it8xxx2_erase(const struct device *dev, int offset, * during erasing. */ if (IS_ENABLED(HAS_TASK_HOSTCMD) && - IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) { + IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) { irq_enable(DT_IRQN(DT_NODELABEL(shi))); } /* Always use sector erase command */ for (; size > 0; size -= CONFIG_FLASH_ERASE_SIZE) { ret = flash_erase(flash_controller, offset, - CONFIG_FLASH_ERASE_SIZE); + CONFIG_FLASH_ERASE_SIZE); if (ret) break; @@ -273,17 +274,16 @@ static int cros_flash_it8xxx2_protect_now(const struct device *dev, int all) if (all) { /* Protect the entire flash */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_EC); data->all_protected = 1; } else { /* Protect the read-only section and persistent state */ - flash_protect_banks(WP_BANK_OFFSET, - WP_BANK_COUNT, FLASH_WP_EC); + flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC); #ifdef PSTATE_BANK - flash_protect_banks(PSTATE_BANK, - PSTATE_BANK_COUNT, FLASH_WP_EC); + flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT, + FLASH_WP_EC); #endif } -- cgit v1.2.1 From d6f224f3d08bb126188fdbf5a91d6a800ad8ec73 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:46 -0600 Subject: include/led_onoff_states.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6165234994d3853aaae283b33c71b3faf602daa5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730313 Reviewed-by: Jeremy Bettis --- include/led_onoff_states.h | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/include/led_onoff_states.h b/include/led_onoff_states.h index 63955e590a..47756da106 100644 --- a/include/led_onoff_states.h +++ b/include/led_onoff_states.h @@ -10,19 +10,15 @@ #include "ec_commands.h" -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT /* * All LED states should have one phase defined, * and an additional phase can be defined for blinking */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; /* * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 -- cgit v1.2.1 From 6a6015e61fcdd9fc98f651f4716c15bda129cb4d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:33 -0600 Subject: test/body_detection.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20d9987ea7d492b3c37f8954e97886e05a0b583e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730490 Reviewed-by: Jeremy Bettis --- test/body_detection.c | 1 - 1 file changed, 1 deletion(-) diff --git a/test/body_detection.c b/test/body_detection.c index aa131f0a31..4a6e5a7c90 100644 --- a/test/body_detection.c +++ b/test/body_detection.c @@ -105,7 +105,6 @@ static int test_body_detect(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 2f9269bb03f251ab8880faeb09827f85a94fb817 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:30 -0600 Subject: board/eldrid/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14c8d07ac6eb9afa6a24d606519e5dd12dda5360 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728264 Reviewed-by: Jeremy Bettis --- board/eldrid/battery.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/eldrid/battery.c b/board/eldrid/battery.c index 3c9f2b0c21..e988373672 100644 --- a/board/eldrid/battery.c +++ b/board/eldrid/battery.c @@ -100,7 +100,9 @@ __override bool board_battery_is_initialized(void) bool batt_initialization_state; int batt_status; - batt_initialization_state = (battery_status(&batt_status) ? false : - !!(batt_status & STATUS_INITIALIZED)); + batt_initialization_state = + (battery_status(&batt_status) ? + false : + !!(batt_status & STATUS_INITIALIZED)); return batt_initialization_state; } -- cgit v1.2.1 From c2a527983748e9d6be815713b6a22e7ab8c63214 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:50 -0600 Subject: core/minute-ia/config_core.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie31667859739941625345d06e2892a1c6fb92f42 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729847 Reviewed-by: Jeremy Bettis --- core/minute-ia/config_core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/minute-ia/config_core.h b/core/minute-ia/config_core.h index 47121642a4..b4bff97e0c 100644 --- a/core/minute-ia/config_core.h +++ b/core/minute-ia/config_core.h @@ -29,6 +29,6 @@ /* * Flag indicates the task uses FPU H/W */ -#define MIA_TASK_FLAG_USE_FPU 0x00000001 +#define MIA_TASK_FLAG_USE_FPU 0x00000001 #endif /* __CROS_EC_CONFIG_CORE_H */ -- cgit v1.2.1 From 6a937f3b6c49c1b87036e9fee3f095080e9c1b1b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:37 -0600 Subject: zephyr/projects/skyrim/power_signals.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icd9a8378dca7346d8d6d134636c747ba31d1bf11 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730802 Reviewed-by: Jeremy Bettis --- zephyr/projects/skyrim/power_signals.c | 48 ++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index f23d6d01ea..3b226eb0f9 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -49,15 +49,15 @@ static void baseboard_suspend_change(struct ap_power_ev_callback *cb, case AP_POWER_SUSPEND: /* Disable display backlight and retimer */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 1); ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); break; case AP_POWER_RESUME: /* Enable retimer and display backlight */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), 0); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl), + 0); ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1); /* Any retimer tuning can be done after the retimer turns on */ break; @@ -101,7 +101,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_suspend, HOOK_PRIO_DEFAULT); * PCH_PWRBTN_L. This can be as long as ~65ms after cold boot. Then wait an * additional delay of T1a defined in the EDS before changing the power button. */ -#define RSMRST_WAIT_DELAY 70 +#define RSMRST_WAIT_DELAY 70 #define EDS_PWR_BTN_RSMRST_T1A_DELAY 16 void board_pwrbtn_to_pch(int level) { @@ -113,13 +113,13 @@ void board_pwrbtn_to_pch(int level) start = get_time(); do { usleep(500); - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ec_soc_rsmrst_l))) break; } while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC)); if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) ccprints("Error pwrbtn: RSMRST_L still low"); msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY); @@ -130,10 +130,13 @@ void board_pwrbtn_to_pch(int level) /* Note: signal parameter unused */ void baseboard_set_soc_pwr_pgood(enum gpio_signal unused) { - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good), + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s0_od)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); } void baseboard_s0_pgood(enum gpio_signal signal) @@ -151,10 +154,13 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused) * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and * EN_PWR_S0_R */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r))); /* Update EC_SOC_PWR_GOOD based on our results */ baseboard_set_soc_pwr_pgood(unused); @@ -163,9 +169,11 @@ void baseboard_set_en_pwr_pcore(enum gpio_signal unused) void baseboard_en_pwr_s0(enum gpio_signal signal) { /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); /* Change EN_PWR_PCORE_S0_R if needed*/ baseboard_set_en_pwr_pcore(signal); @@ -196,7 +204,7 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal) { /* EC must enable PWR_S3 when SLP_S5_L goes high, disable on low */ gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s3), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l))); + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s5_l))); /* Chain off the normal power signal interrupt handler */ power_signal_interrupt(signal); -- cgit v1.2.1 From e660f060d901c7fad5dce206e51a8612609e4159 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:17 -0600 Subject: common/host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I80e2783f14ccf1346e2fb10433b93ab74dea5e62 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729633 Reviewed-by: Jeremy Bettis --- common/host_command.c | 78 +++++++++++++++++++++------------------------------ 1 file changed, 32 insertions(+), 46 deletions(-) diff --git a/common/host_command.c b/common/host_command.c index e05475ce48..775632c3bf 100644 --- a/common/host_command.c +++ b/common/host_command.c @@ -20,8 +20,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_HOSTCMD, outstr) -#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args) #define TASK_EVENT_CMD_PENDING TASK_EVENT_CUSTOM_BIT(0) @@ -42,18 +42,19 @@ static uint8_t host_memmap[EC_MEMMAP_SIZE] __aligned(4); #endif static enum { - HCDEBUG_OFF, /* No host command debug output */ - HCDEBUG_NORMAL, /* Normal output mode; skips repeated commands */ - HCDEBUG_EVERY, /* Print every command */ - HCDEBUG_PARAMS, /* ... and print params for request/response */ + HCDEBUG_OFF, /* No host command debug output */ + HCDEBUG_NORMAL, /* Normal output mode; skips repeated commands */ + HCDEBUG_EVERY, /* Print every command */ + HCDEBUG_PARAMS, /* ... and print params for request/response */ /* Number of host command debug modes */ HCDEBUG_MODES } hcdebug = CONFIG_HOSTCMD_DEBUG_MODE; #ifdef CONFIG_CMD_HCDEBUG -static const char * const hcdebug_mode_names[HCDEBUG_MODES] = { - "off", "normal", "every", "params"}; +static const char *const hcdebug_mode_names[HCDEBUG_MODES] = { "off", "normal", + "every", + "params" }; #endif #ifdef CONFIG_HOST_COMMAND_STATUS @@ -343,8 +344,8 @@ void host_packet_receive(struct host_packet *pkt) args0.version = r->command_version; args0.params_size = r->data_len; args0.response = (struct ec_host_response *)(pkt->response) + 1; - args0.response_max = pkt->response_max - - sizeof(struct ec_host_response); + args0.response_max = + pkt->response_max - sizeof(struct ec_host_response); args0.response_size = 0; args0.result = EC_RES_SUCCESS; @@ -440,7 +441,7 @@ void host_command_task(void *u) /* Process it */ if ((evt & TASK_EVENT_CMD_PENDING) && pending_args) { pending_args->result = - host_command_process(pending_args); + host_command_process(pending_args); host_send_response(pending_args); } @@ -473,8 +474,7 @@ host_command_proto_version(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION, - host_command_proto_version, +DECLARE_HOST_COMMAND(EC_CMD_PROTO_VERSION, host_command_proto_version, EC_VER_MASK(0)); static enum ec_status host_command_hello(struct host_cmd_handler_args *args) @@ -488,9 +488,7 @@ static enum ec_status host_command_hello(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HELLO, - host_command_hello, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_HELLO, host_command_hello, EC_VER_MASK(0)); static enum ec_status host_command_read_test(struct host_cmd_handler_args *args) { @@ -511,9 +509,7 @@ static enum ec_status host_command_read_test(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_READ_TEST, - host_command_read_test, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_READ_TEST, host_command_read_test, EC_VER_MASK(0)); #ifndef CONFIG_HOSTCMD_X86 /* @@ -543,8 +539,7 @@ host_command_read_memmap(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP, - host_command_read_memmap, +DECLARE_HOST_COMMAND(EC_CMD_READ_MEMMAP, host_command_read_memmap, EC_VER_MASK(0)); #endif @@ -555,9 +550,9 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args) const struct ec_params_get_cmd_versions_v1 *p_v1 = args->params; struct ec_response_get_cmd_versions *r = args->response; - const struct host_command *cmd = - (args->version == 1) ? find_host_command(p_v1->cmd) : - find_host_command(p->cmd); + const struct host_command *cmd = (args->version == 1) ? + find_host_command(p_v1->cmd) : + find_host_command(p->cmd); if (!cmd) return EC_RES_INVALID_PARAM; @@ -568,8 +563,7 @@ host_command_get_cmd_versions(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS, - host_command_get_cmd_versions, +DECLARE_HOST_COMMAND(EC_CMD_GET_CMD_VERSIONS, host_command_get_cmd_versions, EC_VER_MASK(0) | EC_VER_MASK(1)); static int host_command_is_suppressed(uint16_t cmd) @@ -614,10 +608,9 @@ static void dump_host_command_suppressed_(void) { dump_host_command_suppressed(1); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - dump_host_command_suppressed_, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_SYSJUMP, - dump_host_command_suppressed_, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, dump_host_command_suppressed_, + HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_SYSJUMP, dump_host_command_suppressed_, HOOK_PRIO_DEFAULT); #else } #endif /* CONFIG_SUPPRESSED_HOST_COMMANDS */ @@ -660,8 +653,7 @@ static void host_command_debug_request(struct host_cmd_handler_args *args) } if (hcdebug >= HCDEBUG_PARAMS && args->params_size) - CPRINTS("HC 0x%04x.%d:%ph", args->command, - args->version, + CPRINTS("HC 0x%04x.%d:%ph", args->command, args->version, HEX_BUF(args->params, args->params_size)); else CPRINTS("HC 0x%04x", args->command); @@ -693,9 +685,9 @@ uint16_t host_command_process(struct host_cmd_handler_args *args) if (args->command >= EC_CMD_PASSTHRU_OFFSET(1) && args->command <= EC_CMD_PASSTHRU_MAX(1)) { rv = pd_host_command(args->command - EC_CMD_PASSTHRU_OFFSET(1), - args->version, - args->params, args->params_size, - args->response, args->response_max); + args->version, args->params, + args->params_size, args->response, + args->response_max); if (rv >= 0) { /* Success; store actual response size */ args->response_size = rv; @@ -739,8 +731,7 @@ host_command_get_comms_status(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS, - host_command_get_comms_status, +DECLARE_HOST_COMMAND(EC_CMD_GET_COMMS_STATUS, host_command_get_comms_status, EC_VER_MASK(0)); /* Resend the last saved response */ @@ -756,8 +747,7 @@ host_command_resend_response(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE, - host_command_resend_response, +DECLARE_HOST_COMMAND(EC_CMD_RESEND_RESPONSE, host_command_resend_response, EC_VER_MASK(0)); #endif /* CONFIG_HOST_COMMAND_STATUS */ @@ -775,8 +765,7 @@ host_command_test_protocol(struct host_cmd_handler_args *args) return p->ec_result; } -DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL, - host_command_test_protocol, +DECLARE_HOST_COMMAND(EC_CMD_TEST_PROTOCOL, host_command_test_protocol, EC_VER_MASK(0)); /* Returns supported features. */ @@ -791,11 +780,9 @@ host_command_get_features(struct host_cmd_handler_args *args) r->flags[1] = get_feature_flags1(); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES, - host_command_get_features, +DECLARE_HOST_COMMAND(EC_CMD_GET_FEATURES, host_command_get_features, EC_VER_MASK(0)); - /*****************************************************************************/ /* Console commands */ @@ -897,8 +884,7 @@ static int command_host_command(int argc, char **argv) shared_mem_release(cmd_params); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command, - "cmd ver param", +DECLARE_CONSOLE_COMMAND(hostcmd, command_host_command, "cmd ver param", "Fake host command"); #endif /* CONFIG_CMD_HOSTCMD */ -- cgit v1.2.1 From 2ec6a534e31d12675757be3dba6acf4eaa25e176 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:10 -0600 Subject: chip/npcx/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie13ce8afe62b40cee228bec4c8fedfbd7fbe086f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729444 Reviewed-by: Jeremy Bettis --- chip/npcx/uart.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index c158049e6a..3961c282bb 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -21,12 +21,12 @@ #include "uartn.h" #include "util.h" -#define CONSOLE_UART CONFIG_CONSOLE_UART +#define CONSOLE_UART CONFIG_CONSOLE_UART #if CONSOLE_UART -#define CONSOLE_UART_IRQ NPCX_IRQ_UART2 +#define CONSOLE_UART_IRQ NPCX_IRQ_UART2 #else -#define CONSOLE_UART_IRQ NPCX_IRQ_UART +#define CONSOLE_UART_IRQ NPCX_IRQ_UART #endif static int init_done; @@ -54,7 +54,7 @@ static int altpad_tx_len; */ static timestamp_t last_default_pad_rx_time; -static const uint32_t block_alt_timeout_us = 500*MSEC; +static const uint32_t block_alt_timeout_us = 500 * MSEC; #else @@ -209,7 +209,8 @@ static void uart_ec_interrupt(void) } if (uartn_tx_ready(NPCX_UART_PORT0)) { if (altpad_tx_pos < altpad_tx_len) - uartn_write_char(NPCX_UART_PORT0, + uartn_write_char( + NPCX_UART_PORT0, altpad_tx_buf[altpad_tx_pos++]); else uart_tx_stop(); @@ -319,8 +320,8 @@ int uart_alt_pad_write_read(uint8_t *tx, int tx_len, uint8_t *rx, int rx_len, uint32_t start = __hw_clock_source_read(); int ret = 0; - if ((get_time().val - last_default_pad_rx_time.val) - < block_alt_timeout_us) + if ((get_time().val - last_default_pad_rx_time.val) < + block_alt_timeout_us) return -EC_ERROR_BUSY; cflush(); @@ -381,7 +382,6 @@ out: #endif void uart_init(void) { - uartn_init(CONSOLE_UART); init_done = 1; } -- cgit v1.2.1 From a70eff2b682f6571829974c3f992e7e97702f864 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Tue, 28 Jun 2022 11:44:39 -0700 Subject: zephyr: MTL power sequencing MTL doesn't have DSW_PWROK signal. BUG=none BRANCH=none TEST=zmake build mtlrvpp_npcx --clobber; MTL RVP boots to S0. Signed-off-by: Li Feng Change-Id: Icf79a63072fcc793231c4f96ed68b7b20513a717 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3732793 Reviewed-by: Andrew McRae --- zephyr/subsys/ap_pwrseq/include/x86_power_signals.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h index b31117569d..1547dc0fc4 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h @@ -72,11 +72,9 @@ POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD)) #define MASK_VW_POWER \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK)) + POWER_SIGNAL_MASK(PWR_RSMRST) #define VALUE_VW_POWER \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK)) + POWER_SIGNAL_MASK(PWR_RSMRST) #define MASK_S0 \ (MASK_ALL_POWER_GOOD | \ @@ -93,7 +91,6 @@ #define MASK_S5 \ (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ POWER_SIGNAL_MASK(PWR_SLP_S3) | \ POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) -- cgit v1.2.1 From 5b3b6c6ca5028d7e5b3ad125aa9a6101d4c30215 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:06 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieebf2078309c245556ea5f6461d4fa5cc626c9c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730968 Reviewed-by: Jeremy Bettis --- .../ap_pwrseq/x86_non_dsx_common_pwrseq_console.c | 26 +++++++++------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c index 77f8134d10..4fef071b2e 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_console.c @@ -11,20 +11,19 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); /* Console commands */ static int powerinfo_handler(const struct shell *shell, size_t argc, - char **argv) + char **argv) { enum power_states_ndsx state = pwr_sm_get_state(); shell_fprintf(shell, SHELL_INFO, "power state %d = %s, in 0x%04x\n", - state, pwr_sm_get_state_name(state), - power_get_signals()); + state, pwr_sm_get_state_name(state), power_get_signals()); return 0; } SHELL_CMD_REGISTER(powerinfo, NULL, NULL, powerinfo_handler); static int powerindebug_handler(const struct shell *shell, size_t argc, - char **argv) + char **argv) { int i; char *e; @@ -44,7 +43,7 @@ static int powerindebug_handler(const struct shell *shell, size_t argc, current = power_get_signals(); shell_fprintf(shell, SHELL_INFO, "power in: 0x%05x\n", current); shell_fprintf(shell, SHELL_INFO, "debug mask: 0x%05x\n", - power_get_debug()); + power_get_debug()); /* Print the decode */ shell_fprintf(shell, SHELL_INFO, "bit meanings:\n"); @@ -52,21 +51,19 @@ static int powerindebug_handler(const struct shell *shell, size_t argc, power_signal_mask_t mask = POWER_SIGNAL_MASK(i); bool valid = (power_signal_get(i) >= 0); - shell_fprintf(shell, SHELL_INFO, " 0x%05x %d%s %s\n", - mask, (current & mask) ? 1 : 0, - valid ? " " : "!", - power_signal_name(i)); + shell_fprintf(shell, SHELL_INFO, " 0x%05x %d%s %s\n", mask, + (current & mask) ? 1 : 0, valid ? " " : "!", + power_signal_name(i)); } return 0; }; -SHELL_CMD_REGISTER(powerindebug, NULL, - "[mask] Get/set power input debug mask", powerindebug_handler); - +SHELL_CMD_REGISTER(powerindebug, NULL, "[mask] Get/set power input debug mask", + powerindebug_handler); static int apshutdown_handler(const struct shell *shell, size_t argc, - char **argv) + char **argv) { ap_power_force_shutdown(AP_POWER_SHUTDOWN_CONSOLE_CMD); return 0; @@ -74,8 +71,7 @@ static int apshutdown_handler(const struct shell *shell, size_t argc, SHELL_CMD_REGISTER(apshutdown, NULL, NULL, apshutdown_handler); -static int apreset_handler(const struct shell *shell, size_t argc, - char **argv) +static int apreset_handler(const struct shell *shell, size_t argc, char **argv) { ap_power_reset(AP_POWER_SHUTDOWN_CONSOLE_CMD); return 0; -- cgit v1.2.1 From f7f05bb09be506f55e3b7991af8a3c9f0ceee90f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:17 -0600 Subject: driver/accel_lis2dw12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4902607f4a4b57fefc0ebd4a12f113f1ccf36a2d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729889 Reviewed-by: Jeremy Bettis --- driver/accel_lis2dw12.c | 74 +++++++++++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/driver/accel_lis2dw12.c b/driver/accel_lis2dw12.c index eef1cc6f8f..d69a4bfbff 100644 --- a/driver/accel_lis2dw12.c +++ b/driver/accel_lis2dw12.c @@ -22,11 +22,11 @@ #define ACCEL_LIS2DW12_INT_ENABLE #endif -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCEL_LIS2DW12_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; /** * lis2dw12_enable_fifo - Enable/Disable FIFO in LIS2DW12 @@ -34,7 +34,7 @@ STATIC_IF(ACCEL_LIS2DW12_INT_ENABLE) * @mode: fifo_modes */ static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s, - enum lis2dw12_fmode mode) + enum lis2dw12_fmode mode) { return st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR, LIS2DW12_FIFO_MODE_MASK, mode); @@ -46,16 +46,17 @@ static __maybe_unused int lis2dw12_enable_fifo(const struct motion_sensor_t *s, * * Must works with interface mutex locked */ -static __maybe_unused int lis2dw12_config_interrupt( - const struct motion_sensor_t *s) +static __maybe_unused int +lis2dw12_config_interrupt(const struct motion_sensor_t *s) { /* Configure FIFO watermark level. */ RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_FIFO_CTRL_ADDR, - LIS2DW12_FIFO_THRESHOLD_MASK, 1)); + LIS2DW12_FIFO_THRESHOLD_MASK, 1)); /* Enable interrupt on FIFO watermark and route to int1. */ RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_FTH_ADDR, - LIS2DW12_INT1_FTH_MASK, LIS2DW12_EN_BIT)); + LIS2DW12_INT1_FTH_MASK, + LIS2DW12_EN_BIT)); if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) { /* @@ -63,27 +64,26 @@ static __maybe_unused int lis2dw12_config_interrupt( * For more details please refer to AN5038. */ RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_TAP_THS_X_ADDR, 0x09)); + LIS2DW12_TAP_THS_X_ADDR, 0x09)); RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_TAP_THS_Y_ADDR, 0x09)); + LIS2DW12_TAP_THS_Y_ADDR, 0x09)); RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_TAP_THS_Z_ADDR, 0xE9)); + LIS2DW12_TAP_THS_Z_ADDR, 0xE9)); RETURN_ERROR(st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_INT_DUR_ADDR, 0x7F)); + LIS2DW12_INT_DUR_ADDR, 0x7F)); /* Enable D-TAP event detection. */ - RETURN_ERROR(st_write_data_with_mask(s, - LIS2DW12_WAKE_UP_THS_ADDR, - LIS2DW12_SINGLE_DOUBLE_TAP, - LIS2DW12_EN_BIT)); + RETURN_ERROR(st_write_data_with_mask( + s, LIS2DW12_WAKE_UP_THS_ADDR, + LIS2DW12_SINGLE_DOUBLE_TAP, LIS2DW12_EN_BIT)); /* * Enable D-TAP detection on int_1 pad. In any case D-TAP event * can be detected only if ODR is over 200 Hz. */ RETURN_ERROR(st_write_data_with_mask(s, LIS2DW12_INT1_TAP_ADDR, - LIS2DW12_INT1_DTAP_MASK, - LIS2DW12_EN_BIT)); + LIS2DW12_INT1_DTAP_MASK, + LIS2DW12_EN_BIT)); } return EC_SUCCESS; } @@ -93,8 +93,7 @@ static __maybe_unused int lis2dw12_config_interrupt( * Load data from internal sensor FIFO. * @s: Motion sensor pointer */ -static int lis2dw12_load_fifo(struct motion_sensor_t *s, - int nsamples) +static int lis2dw12_load_fifo(struct motion_sensor_t *s, int nsamples) { int ret, left, length, i; uint32_t interrupt_timestamp = last_interrupt_timestamp; @@ -131,8 +130,8 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s, vect.data[Z] = axis[Z]; vect.flags = 0; vect.sensor_num = s - motion_sensors; - motion_sense_fifo_stage_data(&vect, s, 3, - interrupt_timestamp); + motion_sense_fifo_stage_data( + &vect, s, 3, interrupt_timestamp); } else { motion_sense_push_raw_xyz(s); } @@ -146,8 +145,7 @@ static int lis2dw12_load_fifo(struct motion_sensor_t *s, /** * lis2dw12_get_fifo_samples - check for stored FIFO samples. */ -static int lis2dw12_get_fifo_samples(struct motion_sensor_t *s, - int *nsamples) +static int lis2dw12_get_fifo_samples(struct motion_sensor_t *s, int *nsamples) { int ret, tmp; @@ -175,8 +173,7 @@ void lis2dw12_interrupt(enum gpio_signal signal) /** * lis2dw12_irq_handler - bottom half of the interrupt stack. */ -static int lis2dw12_irq_handler(struct motion_sensor_t *s, - uint32_t *event) +static int lis2dw12_irq_handler(struct motion_sensor_t *s, uint32_t *event) { bool commit_needed = false; int nsamples; @@ -194,7 +191,7 @@ static int lis2dw12_irq_handler(struct motion_sensor_t *s, LIS2DW12_STATUS_TAP, &status); if (status & LIS2DW12_DOUBLE_TAP) *event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_DOUBLE_TAP); + MOTIONSENSE_ACTIVITY_DOUBLE_TAP); } do { @@ -231,8 +228,7 @@ int lis2dw12_set_power_mode(const struct motion_sensor_t *s, { int ret = EC_SUCCESS; - if (mode == LIS2DW12_LOW_POWER && - lpmode == LIS2DW12_LOW_POWER_MODE_1) + if (mode == LIS2DW12_LOW_POWER && lpmode == LIS2DW12_LOW_POWER_MODE_1) return EC_ERROR_UNIMPLEMENTED; /* Set Mode and Low Power Mode. */ @@ -364,8 +360,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) if (reg_val > LIS2DW12_ODR_200HZ_VAL) ret = lis2dw12_set_power_mode(s, LIS2DW12_HIGH_PERF, 0); else - ret = lis2dw12_set_power_mode(s, LIS2DW12_LOW_POWER, - LIS2DW12_LOW_POWER_MODE_2); + ret = lis2dw12_set_power_mode( + s, LIS2DW12_LOW_POWER, + LIS2DW12_LOW_POWER_MODE_2); } ret = st_write_data_with_mask(s, LIS2DW12_ACC_ODR_ADDR, @@ -387,8 +384,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DW12_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) return ret; @@ -419,8 +416,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v) /* Read 6 bytes starting at xyz_reg. */ ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, - LIS2DW12_OUT_X_L_ADDR, raw, - OUT_XYZ_SIZE); + LIS2DW12_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type); return ret; @@ -466,7 +462,7 @@ static int init(struct motion_sensor_t *s) msleep(1); timeout += 1; ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2DW12_SOFT_RESET_ADDR, &status); + LIS2DW12_SOFT_RESET_ADDR, &status); } while (ret != EC_SUCCESS || (status & LIS2DW12_SOFT_RESET_MASK) != 0); /* Enable BDU. */ @@ -483,8 +479,8 @@ static int init(struct motion_sensor_t *s) /* Interrupt trigger level of power-on-reset is HIGH */ if (IS_ENABLED(ACCEL_LIS2DW12_INT_ENABLE)) { ret = st_write_data_with_mask(s, LIS2DW12_H_ACTIVE_ADDR, - LIS2DW12_H_ACTIVE_MASK, - LIS2DW12_EN_BIT); + LIS2DW12_H_ACTIVE_MASK, + LIS2DW12_EN_BIT); if (ret != EC_SUCCESS) goto err_unlock; } @@ -498,7 +494,7 @@ static int init(struct motion_sensor_t *s) else /* Set default Mode and Low Power Mode. */ ret = lis2dw12_set_power_mode(s, LIS2DW12_LOW_POWER, - LIS2DW12_LOW_POWER_MODE_2); + LIS2DW12_LOW_POWER_MODE_2); if (ret != EC_SUCCESS) goto err_unlock; -- cgit v1.2.1 From fd7957c9ed1ce6ce7770697d2013af3b3fc55ffa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:08 -0600 Subject: chip/npcx/gpio_chip-npcx5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I642db0b7dbf173f5b4b49d94e1d1fffaf456d8bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729395 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx5.h | 227 +++++++++++++++++++++++--------------------- 1 file changed, 120 insertions(+), 107 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h index 83916a421b..5d6170affa 100644 --- a/chip/npcx/gpio_chip-npcx5.h +++ b/chip/npcx/gpio_chip-npcx5.h @@ -245,7 +245,7 @@ #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ /* Clock module */ -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ #define NPCX_ALT_GPIO_E_7 ALT(E, 7, NPCX_ALT(A, 32KCLKIN_SL)) /* 32KCLKIN */ /* PS/2 module */ @@ -261,124 +261,137 @@ #define NPCX_ALT_GPIO_A_7 #endif -#define NPCX_ALT_TABLE { \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SOUT */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SIN */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_4 /* PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_7 /* PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_5 /* SPIP_CS1 */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB0SDA1 */ \ - NPCX_ALT_GPIO_B_3 /* SMB0SCL1 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_2 /* PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL */ \ - NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ -} +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 \ + & CR_SOUT */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SIN */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_4 /* PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_7 /* PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_5 /* SPIP_CS1 */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB0SDA1 */ \ + NPCX_ALT_GPIO_B_3 /* SMB0SCL1 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_2 /* PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL */ \ + NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ + } /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* 4 Low-Voltage Control Groups on npcx5 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX5_H */ -- cgit v1.2.1 From 3e13114ed48ab22d55f3652d0e9ebe90d48f0a6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:39 -0600 Subject: driver/accel_bma422.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6d8d4a9d36222adb2857174ad5a94de2a6cd6c1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729765 Reviewed-by: Jeremy Bettis --- driver/accel_bma422.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/accel_bma422.h b/driver/accel_bma422.h index 0ab580235c..9e8175ea7c 100644 --- a/driver/accel_bma422.h +++ b/driver/accel_bma422.h @@ -11,6 +11,6 @@ #include "accel_bma4xx.h" /* Chip ID of BMA422 */ -#define BMA422_CHIP_ID 0x12 +#define BMA422_CHIP_ID 0x12 #endif /* __CROS_EC_ACCEL_BMA422_H */ -- cgit v1.2.1 From d69983ef99492c1f40aa0c29d4d3069dde0b0b43 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:44 -0600 Subject: board/kingoftown/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic57390ff2b55813376029bdf064b0171836a51cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728533 Reviewed-by: Jeremy Bettis --- board/kingoftown/usbc_config.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/board/kingoftown/usbc_config.c b/board/kingoftown/usbc_config.c index 9343fa2256..ca0820da84 100644 --- a/board/kingoftown/usbc_config.c +++ b/board/kingoftown/usbc_config.c @@ -25,8 +25,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -132,16 +132,12 @@ void ppc_interrupt(enum gpio_signal signal) /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -234,7 +230,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -280,8 +276,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -309,7 +304,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -333,23 +327,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From d5bda50acac5f351f1c2edb663b3c4cc4d6eccd1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:44 -0600 Subject: driver/baro_bmp280.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d7f74bdda46789106028f78a6bc35cbe45cf37b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729928 Reviewed-by: Jeremy Bettis --- driver/baro_bmp280.c | 95 ++++++++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 48 deletions(-) diff --git a/driver/baro_bmp280.c b/driver/baro_bmp280.c index 037a77d963..4c995b742e 100644 --- a/driver/baro_bmp280.c +++ b/driver/baro_bmp280.c @@ -63,10 +63,12 @@ #include "i2c.h" #include "timer.h" -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) -static const uint16_t standby_durn[] = {1, 63, 125, 250, 500, 1000, 2000, 4000}; +static const uint16_t standby_durn[] = { + 1, 63, 125, 250, 500, 1000, 2000, 4000 +}; /* * This function is used to get calibration parameters used for @@ -95,19 +97,19 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s) { int ret; - uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = {0}; + uint8_t a_data_u8[BMP280_CALIB_DATA_SIZE] = { 0 }; struct bmp280_drv_data_t *data = BMP280_GET_DATA(s); ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, - BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG, - a_data_u8, BMP280_CALIB_DATA_SIZE); + BMP280_TEMPERATURE_CALIB_DIG_T1_LSB_REG, a_data_u8, + BMP280_CALIB_DATA_SIZE); if (ret) return ret; /* read calibration values*/ data->calib_param.dig_T1 = (a_data_u8[1] << 8) | a_data_u8[0]; - data->calib_param.dig_T2 = (a_data_u8[3] << 8 | a_data_u8[2]); + data->calib_param.dig_T2 = (a_data_u8[3] << 8 | a_data_u8[2]); data->calib_param.dig_T3 = (a_data_u8[5] << 8) | a_data_u8[4]; data->calib_param.dig_P1 = (a_data_u8[7] << 8) | a_data_u8[6]; @@ -124,21 +126,20 @@ static int bmp280_get_calib_param(const struct motion_sensor_t *s) } static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s, - int *uncomp_pres) + int *uncomp_pres) { int ret; - uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = {0}; + uint8_t a_data_u8[BMP280_PRESSURE_DATA_SIZE] = { 0 }; ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, - BMP280_PRESSURE_MSB_REG, - a_data_u8, BMP280_PRESSURE_DATA_SIZE); + BMP280_PRESSURE_MSB_REG, a_data_u8, + BMP280_PRESSURE_DATA_SIZE); if (ret) return ret; - *uncomp_pres = (int32_t)((a_data_u8[0] << 12) | - (a_data_u8[1] << 4) | - (a_data_u8[2] >> 4)); + *uncomp_pres = (int32_t)((a_data_u8[0] << 12) | (a_data_u8[1] << 4) | + (a_data_u8[2] >> 4)); return EC_SUCCESS; } @@ -153,34 +154,33 @@ static int bmp280_read_uncomp_pressure(const struct motion_sensor_t *s, * */ static int bmp280_compensate_pressure(const struct motion_sensor_t *s, - int uncomp_pressure) + int uncomp_pressure) { int var1, var2; uint32_t p; struct bmp280_drv_data_t *data = BMP280_GET_DATA(s); /* calculate x1 */ - var1 = (((int32_t)data->calib_param.t_fine) - >> 1) - 64000; + var1 = (((int32_t)data->calib_param.t_fine) >> 1) - 64000; /* calculate x2 */ - var2 = (((var1 >> 2) * (var1 >> 2)) >> 11) - * ((int32_t)data->calib_param.dig_P6); + var2 = (((var1 >> 2) * (var1 >> 2)) >> 11) * + ((int32_t)data->calib_param.dig_P6); var2 = var2 + ((var1 * ((int32_t)data->calib_param.dig_P5)) << 1); var2 = (var2 >> 2) + (((int32_t)data->calib_param.dig_P4) << 16); /* calculate x1 */ var1 = (((data->calib_param.dig_P3 * - (((var1 >> 2) * (var1 >> 2)) >> 13)) >> 3) + - ((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >> 18; - var1 = ((((32768 + var1)) * - ((int32_t)data->calib_param.dig_P1)) >> 15); + (((var1 >> 2) * (var1 >> 2)) >> 13)) >> + 3) + + ((((int32_t)data->calib_param.dig_P2) * var1) >> 1)) >> + 18; + var1 = ((((32768 + var1)) * ((int32_t)data->calib_param.dig_P1)) >> 15); /* Avoid exception caused by division by zero */ if (!var1) return 0; /* calculate pressure */ - p = (((uint32_t)((1048576) - uncomp_pressure) - - (var2 >> 12))) * 3125; + p = (((uint32_t)((1048576) - uncomp_pressure) - (var2 >> 12))) * 3125; /* check overflow */ if (p < 0x80000000) @@ -190,13 +190,14 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s, /* calculate x1 */ var1 = (((int32_t)data->calib_param.dig_P9) * - ((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >> 12; + ((int32_t)(((p >> 3) * (p >> 3)) >> 13))) >> + 12; /* calculate x2 */ - var2 = (((int32_t)(p >> 2)) * - ((int32_t)data->calib_param.dig_P8)) >> 13; + var2 = (((int32_t)(p >> 2)) * ((int32_t)data->calib_param.dig_P8)) >> + 13; /* calculate true pressure */ - return (uint32_t)((int32_t)p + ((var1 + var2 + - data->calib_param.dig_P7) >> 4)); + return (uint32_t)((int32_t)p + + ((var1 + var2 + data->calib_param.dig_P7) >> 4)); } /* @@ -214,38 +215,36 @@ static int bmp280_compensate_pressure(const struct motion_sensor_t *s, * 0x07 | 4000_MS */ static int bmp280_set_standby_durn(const struct motion_sensor_t *s, - uint8_t durn) + uint8_t durn) { int ret, val; - ret = i2c_read8(s->port, s->i2c_spi_addr_flags, - BMP280_CONFIG_REG, &val); + ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CONFIG_REG, + &val); if (ret == EC_SUCCESS) { val = (val & 0xE0) | ((durn << 5) & 0xE0); /* write the standby duration*/ ret = i2c_write8(s->port, s->i2c_spi_addr_flags, - BMP280_CONFIG_REG, val); + BMP280_CONFIG_REG, val); } return ret; } static int bmp280_set_power_mode(const struct motion_sensor_t *s, - uint8_t power_mode) + uint8_t power_mode) { int val; - val = (BMP280_OVERSAMP_TEMP << 5) + - (BMP280_OVERSAMP_PRES << 2) + power_mode; + val = (BMP280_OVERSAMP_TEMP << 5) + (BMP280_OVERSAMP_PRES << 2) + + power_mode; - return i2c_write8(s->port, s->i2c_spi_addr_flags, - BMP280_CTRL_MEAS_REG, val); + return i2c_write8(s->port, s->i2c_spi_addr_flags, BMP280_CTRL_MEAS_REG, + val); } -static int bmp280_set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int bmp280_set_range(struct motion_sensor_t *s, int range, int rnd) { struct bmp280_drv_data_t *data = BMP280_GET_DATA(s); /* @@ -272,8 +271,8 @@ static int bmp280_init(struct motion_sensor_t *s) return EC_ERROR_INVAL; /* Read chip id */ - ret = i2c_read8(s->port, s->i2c_spi_addr_flags, - BMP280_CHIP_ID_REG, &val); + ret = i2c_read8(s->port, s->i2c_spi_addr_flags, BMP280_CHIP_ID_REG, + &val); if (ret) return ret; @@ -314,7 +313,7 @@ static int bmp280_read(const struct motion_sensor_t *s, intv3_t v) * Calculate the delay (in ms) to apply. */ static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate, - int roundup) + int roundup) { struct bmp280_drv_data_t *data = BMP280_GET_DATA(s); int durn, i, ret; @@ -335,12 +334,12 @@ static int bmp280_set_data_rate(const struct motion_sensor_t *s, int rate, } durn = 0; - for (i = BMP280_STANDBY_CNT-1; i > 0; i--) { + for (i = BMP280_STANDBY_CNT - 1; i > 0; i--) { if (period >= standby_durn[i] + BMP280_COMPUTE_TIME) { durn = i; break; - } else if (period > standby_durn[i-1] + BMP280_COMPUTE_TIME) { - durn = roundup ? i-1 : i; + } else if (period > standby_durn[i - 1] + BMP280_COMPUTE_TIME) { + durn = roundup ? i - 1 : i; break; } } -- cgit v1.2.1 From f6cd93a174090a3f21a49450e86f0f2a134bc880 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:11 -0600 Subject: board/vilboz/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac621b4d4c278fab35685fdd1d96491023f457ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729069 Reviewed-by: Jeremy Bettis --- board/vilboz/battery.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/vilboz/battery.c b/board/vilboz/battery.c index 6f6bca7662..22187fa7df 100644 --- a/board/vilboz/battery.c +++ b/board/vilboz/battery.c @@ -387,9 +387,9 @@ struct chg_curr_step { }; static const struct chg_curr_step chg_curr_table[] = { - {.on = 0, .off = 35, .curr_ma = 2800}, - {.on = 36, .off = 35, .curr_ma = 1500}, - {.on = 39, .off = 38, .curr_ma = 1000}, + { .on = 0, .off = 35, .curr_ma = 2800 }, + { .on = 36, .off = 35, .curr_ma = 1500 }, + { .on = 39, .off = 38, .curr_ma = 1000 }, }; /* All charge current tables must have the same number of levels */ -- cgit v1.2.1 From c81f13aaa5a92ba9269c115931101f499891d571 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:17 -0600 Subject: board/agah/charger_isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib537ceedbfd67c593406e5ed38665475f4898e51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727970 Reviewed-by: Jeremy Bettis --- board/agah/charger_isl9241.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c index 6f041a7455..138c3841f7 100644 --- a/board/agah/charger_isl9241.c +++ b/board/agah/charger_isl9241.c @@ -19,8 +19,8 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -96,7 +96,7 @@ static int board_disable_vbus_sink(int port) */ r = ppc_vbus_sink_enable(i, 0); CPRINTS("%s to disable sink path C%d (%d).", - r ? "Failed" : "Succeeded", i, r); + r ? "Failed" : "Succeeded", i, r); rv |= r; } @@ -104,7 +104,7 @@ static int board_disable_vbus_sink(int port) } /* Minimum battery SoC required for switching source port. */ -#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1 +#define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1 /* * It should also work on POR with/without a battery: @@ -201,12 +201,11 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } static const struct charge_port_info bj_power = { @@ -216,7 +215,7 @@ static const struct charge_port_info bj_power = { }; /* Debounce time for BJ plug/unplug */ -#define BJ_DEBOUNCE_MS 1000 +#define BJ_DEBOUNCE_MS 1000 static void bj_connect_deferred(void) { -- cgit v1.2.1 From 02aab0842164f9013a293313fce03f82f41f08a3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:16 -0600 Subject: board/nami/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I67cfba119c5aef53f04974d8c3b684c321a1b83b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728718 Reviewed-by: Jeremy Bettis --- board/nami/board.h | 73 +++++++++++++++++++++++++++--------------------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/board/nami/board.h b/board/nami/board.h index dde32b65f8..4975ca08ba 100644 --- a/board/nami/board.h +++ b/board/nami/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages except ACPI and host event because * the sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) /* EC */ #define CONFIG_ADC @@ -87,8 +87,8 @@ #define CONFIG_BATTERY_SMART #define CONFIG_PWR_STATE_DISCHARGE_FULL #define CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD -#undef CONFIG_BATT_HOST_FULL_FACTOR -#define CONFIG_BATT_HOST_FULL_FACTOR 100 +#undef CONFIG_BATT_HOST_FULL_FACTOR +#define CONFIG_BATT_HOST_FULL_FACTOR 100 /* Charger */ #define CONFIG_CHARGE_MANAGER @@ -98,8 +98,8 @@ #define CONFIG_CHARGER_ISL9238 #define CONFIG_CHARGER_DISCHARGE_ON_AC #define CONFIG_CHARGER_INPUT_CURRENT 512 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 27000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 /* AP's thresholds. */ #define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3 #define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 27000 @@ -110,11 +110,11 @@ #define CONFIG_CMD_CHARGER_ADC_AMON_BMON #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6 #define CONFIG_POWER_COMMON #define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30 @@ -180,34 +180,33 @@ #define CONFIG_USBC_VCONN_SWAP #define CONFIG_USB_MUX_RUNTIME_CONFIG - /* BC 1.2 charger */ #define CONFIG_BC12_DETECT_PI3USB9281 #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_KBLIGHT NPCX_I2C_PORT2 -#define I2C_PORT_GYRO NPCX_I2C_PORT3 -#define I2C_PORT_ACCEL NPCX_I2C_PORT3 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 -#define I2C_PORT_ALS NPCX_I2C_PORT3 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_KBLIGHT NPCX_I2C_PORT2 +#define I2C_PORT_GYRO NPCX_I2C_PORT3 +#define I2C_PORT_ACCEL NPCX_I2C_PORT3 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3 +#define I2C_PORT_ALS NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_MP2949_FLAGS 0x20 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #ifndef __ASSEMBLER__ @@ -284,26 +283,26 @@ enum model_id { MODEL_BARD = 2, }; -#define SKU_ID_MASK_KBLIGHT BIT(0) -#define SKU_ID_MASK_CONVERTIBLE BIT(9) -#define SKU_ID_MASK_KEYPAD BIT(15) -#define SKU_ID_MASK_UK2 BIT(18) +#define SKU_ID_MASK_KBLIGHT BIT(0) +#define SKU_ID_MASK_CONVERTIBLE BIT(9) +#define SKU_ID_MASK_KEYPAD BIT(15) +#define SKU_ID_MASK_UK2 BIT(18) /* TODO(crosbug.com/p/61098): Verify the numbers below. */ /* * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 70000 -#define PD_MAX_CURRENT_MA 3500 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 70000 +#define PD_MAX_CURRENT_MA 3500 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ void board_reset_pd_mcu(void); @@ -319,7 +318,7 @@ extern uint32_t sku; extern uint8_t model; /* SKU_ID[24:31] are dedicated to OEM customization */ -#define CBI_SKU_CUSTOM_FIELD(val) ((val) >> 24) +#define CBI_SKU_CUSTOM_FIELD(val) ((val) >> 24) void ccd_mode_isr(enum gpio_signal signal); -- cgit v1.2.1 From 2f71e7b0c78fb7d24850cc6ca0367afde407fe15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:04 -0600 Subject: driver/battery/mm8013.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f15e3b57f6652f51718a54ac633525aa6fe1ddb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729952 Reviewed-by: Jeremy Bettis --- driver/battery/mm8013.h | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/driver/battery/mm8013.h b/driver/battery/mm8013.h index 2ffaca7b5d..82e17905e8 100644 --- a/driver/battery/mm8013.h +++ b/driver/battery/mm8013.h @@ -8,33 +8,32 @@ #ifndef __CROS_EC_MM8013_H #define __CROS_EC_MM8013_H -#define MM8013_ADDR_FLAGS 0x55 +#define MM8013_ADDR_FLAGS 0x55 -#define REG_TEMPERATURE 0x06 -#define REG_VOLTAGE 0x08 -#define REG_FLAGS 0x0a -#define REG_FULL_CHARGE_CAPACITY 0x0e -#define REG_REMAINING_CAPACITY 0x10 -#define REG_AVERAGE_CURRENT 0x14 -#define REG_AVERAGE_TIME_TO_EMPTY 0x16 -#define REG_AVERAGE_TIME_TO_FULL 0x18 -#define REG_STATE_OF_CHARGE 0x2c -#define REG_CYCLE_COUNT 0x2a -#define REG_DESIGN_CAPACITY 0x3c -#define REG_PRODUCT_INFORMATION 0x64 +#define REG_TEMPERATURE 0x06 +#define REG_VOLTAGE 0x08 +#define REG_FLAGS 0x0a +#define REG_FULL_CHARGE_CAPACITY 0x0e +#define REG_REMAINING_CAPACITY 0x10 +#define REG_AVERAGE_CURRENT 0x14 +#define REG_AVERAGE_TIME_TO_EMPTY 0x16 +#define REG_AVERAGE_TIME_TO_FULL 0x18 +#define REG_STATE_OF_CHARGE 0x2c +#define REG_CYCLE_COUNT 0x2a +#define REG_DESIGN_CAPACITY 0x3c +#define REG_PRODUCT_INFORMATION 0x64 /* Over Temperature in charge */ -#define MM8013_FLAG_OTC BIT(15) +#define MM8013_FLAG_OTC BIT(15) /* Over Temperature in discharge */ -#define MM8013_FLAG_OTD BIT(14) +#define MM8013_FLAG_OTD BIT(14) /* Over-charge */ -#define MM8013_FLAG_BATHI BIT(13) +#define MM8013_FLAG_BATHI BIT(13) /* Full Charge */ -#define MM8013_FLAG_FC BIT(9) +#define MM8013_FLAG_FC BIT(9) /* Charge allowed */ -#define MM8013_FLAG_CHG BIT(8) +#define MM8013_FLAG_CHG BIT(8) /* Discharge */ -#define MM8013_FLAG_DSG BIT(0) - +#define MM8013_FLAG_DSG BIT(0) #endif /* __CROS_EC_MM8013_H */ -- cgit v1.2.1 From d82a36d3cc672d3da37635acd418fbe62d807083 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:07 -0600 Subject: util/powerd_lock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb374b289e00c49421866db12b6dd3efc79cb0f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730654 Reviewed-by: Jeremy Bettis --- util/powerd_lock.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/powerd_lock.h b/util/powerd_lock.h index 86be184a19..b75564ed42 100644 --- a/util/powerd_lock.h +++ b/util/powerd_lock.h @@ -27,8 +27,8 @@ enum POWERD_ERROR_CODE { POWERD_OK = 0, POWERD_CREATE_LOCK_FILE_ERROR = 0x1, - POWERD_WRITE_LOCK_FILE_ERROR = 0x2, - POWERD_CLOSE_LOCK_FILE_ERROR = 0x4, + POWERD_WRITE_LOCK_FILE_ERROR = 0x2, + POWERD_CLOSE_LOCK_FILE_ERROR = 0x4, POWERD_DELETE_LOCK_FILE_ERROR = 0x8 }; @@ -38,4 +38,4 @@ int disable_power_management(void); /* Re-enable power management. */ int restore_power_management(void); -#endif /* __UTIL_POWERD_LOCK_H */ +#endif /* __UTIL_POWERD_LOCK_H */ -- cgit v1.2.1 From 12660da08364f934c74a0223d2d214cf2ca31613 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:30 -0600 Subject: common/mat33.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaaf374e6a074211fe1fd3f938a78c887bfa0e029 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729664 Reviewed-by: Jeremy Bettis --- common/mat33.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/mat33.c b/common/mat33.c index 87e335db26..2d806ef37a 100644 --- a/common/mat33.c +++ b/common/mat33.c @@ -59,8 +59,7 @@ void mat33_fp_swap_rows(mat33_fp_t A, const size_t i, const size_t j) * The i-th eigenvalue corresponds to the eigenvector in the i-th _row_ of * "eigenvecs". */ -void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals, - mat33_fp_t e_vecs) +void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t e_vals, mat33_fp_t e_vecs) { const size_t N = 3; sizev3_t ind; @@ -176,8 +175,8 @@ size_t mat33_fp_maxind(mat33_fp_t A, size_t k) return m; } -void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, - size_t k, size_t l, size_t i, size_t j) +void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i, + size_t j) { fp_t tmp = fp_mul(c, A[k][l]) - fp_mul(s, A[i][j]); A[i][j] = fp_mul(s, A[k][l]) + fp_mul(c, A[i][j]); -- cgit v1.2.1 From ae5b423fe405d0d3eaf3cd958f33490f33cba688 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:43 -0600 Subject: common/peripheral.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6d81950898a8268209b0a45177cc4670b0d21d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729684 Reviewed-by: Jeremy Bettis --- common/peripheral.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/peripheral.c b/common/peripheral.c index e70ec19347..27156c4a88 100644 --- a/common/peripheral.c +++ b/common/peripheral.c @@ -30,7 +30,8 @@ static enum ec_status hc_locate_chip(struct host_cmd_handler_args *args) #endif /* CONFIG_CBI_EEPROM */ break; case EC_CHIP_TYPE_TCPC: -#if defined(CONFIG_USB_POWER_DELIVERY) && defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC) +#if defined(CONFIG_USB_POWER_DELIVERY) && \ + defined(CONFIG_USB_PD_PORT_MAX_COUNT) && !defined(CONFIG_USB_PD_TCPC) if (params->index >= board_get_usb_pd_port_count()) return EC_RES_OVERFLOW; resp->bus_type = tcpc_config[params->index].bus_type; -- cgit v1.2.1 From 1bdbf2b36c0e5e7ab7eabfd960781c3b5e8b9f8b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:25 -0600 Subject: include/rma_auth.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id742ea9576e7d241409d2e1a2edba0672ce6a4d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730397 Reviewed-by: Jeremy Bettis --- include/rma_auth.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/rma_auth.h b/include/rma_auth.h index 0a4d7c7e71..8ccad7f5e4 100644 --- a/include/rma_auth.h +++ b/include/rma_auth.h @@ -10,16 +10,16 @@ #include -#include "common.h" /* For __packed. */ +#include "common.h" /* For __packed. */ /* Current challenge protocol version */ #define RMA_CHALLENGE_VERSION 0 /* Getters and setters for version_key_id byte */ #define RMA_CHALLENGE_VKID_BYTE(version, keyid) \ - (((version) << 6) | ((keyid) & 0x3f)) + (((version) << 6) | ((keyid)&0x3f)) #define RMA_CHALLENGE_GET_VERSION(vkidbyte) ((vkidbyte) >> 6) -#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte) & 0x3f) +#define RMA_CHALLENGE_GET_KEY_ID(vkidbyte) ((vkidbyte)&0x3f) #define RMA_DEVICE_ID_SIZE 8 -- cgit v1.2.1 From 24ced18d51533fa16bcd3d444059038fb3cc60ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:01 -0600 Subject: common/console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea71f2e53594aae4f6c0a62df66e5d1d66cf5599 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729618 Reviewed-by: Jeremy Bettis --- common/console.c | 64 +++++++++++++++++++++++--------------------------------- 1 file changed, 26 insertions(+), 38 deletions(-) diff --git a/common/console.c b/common/console.c index dc0d2655c0..53cb5e77fc 100644 --- a/common/console.c +++ b/common/console.c @@ -52,14 +52,14 @@ static int last_rx_was_cr; #ifndef CONFIG_EXPERIMENTAL_CONSOLE /* State of input escape code */ static enum { - ESC_OUTSIDE, /* Not in escape code */ - ESC_START, /* Got ESC */ - ESC_BAD, /* Bad escape sequence */ - ESC_BRACKET, /* Got ESC [ */ + ESC_OUTSIDE, /* Not in escape code */ + ESC_START, /* Got ESC */ + ESC_BAD, /* Bad escape sequence */ + ESC_BRACKET, /* Got ESC [ */ ESC_BRACKET_1, /* Got ESC [ 1 */ ESC_BRACKET_3, /* Got ESC [ 3 */ ESC_BRACKET_4, /* Got ESC [ 4 */ - ESC_O, /* Got ESC O */ + ESC_O, /* Got ESC O */ } esc_state; #endif /* !defined(CONFIG_EXPERIMENTAL_CONSOLE) */ @@ -151,18 +151,10 @@ static const struct console_command *find_command(char *name) return match; } - static const char *const errmsgs[] = { - "OK", - "Unknown error", - "Unimplemented", - "Overflow", - "Timeout", - "Invalid argument", - "Busy", - "Access Denied", - "Not Powered", - "Not Calibrated", + "OK", "Unknown error", "Unimplemented", "Overflow", + "Timeout", "Invalid argument", "Busy", "Access Denied", + "Not Powered", "Not Calibrated", }; /** @@ -205,10 +197,10 @@ static int handle_command(char *input) i = input[1] == '&' ? 2 : 1; /* Next, there should be 4 hex digits: XXYY + '&' */ - if (i+5 > input_len) + if (i + 5 > input_len) goto command_has_error; /* Replace the '&' with null so we can call strtoi(). */ - input[i+4] = 0; + input[i + 4] = 0; j = strtoi(input + i, &e, 16); if (*e) goto command_has_error; @@ -218,10 +210,10 @@ static int handle_command(char *input) i += 5; /* Lastly, verify the CRC8 of the command. */ - if (i+command_len > input_len) + if (i + command_len > input_len) goto command_has_error; if (packed_crc8 != cros_crc8(&input[i], command_len)) { -command_has_error: + command_has_error: /* Send back the error string. */ ccprintf("&&EE\n"); return EC_ERROR_UNKNOWN; @@ -248,7 +240,7 @@ command_has_error: rv = EC_ERROR_ACCESS_DENIED; else #endif - rv = cmd->handler(argc, argv); + rv = cmd->handler(argc, argv); if (rv == EC_SUCCESS) return rv; @@ -372,7 +364,7 @@ static void save_history(void) static void handle_backspace(void) { if (!input_pos) - return; /* Already at beginning of line */ + return; /* Already at beginning of line */ /* Move cursor back */ console_putc('\b'); @@ -380,8 +372,7 @@ static void handle_backspace(void) /* Print and move anything following the cursor position */ if (input_pos != input_len) { ccputs(input_buf + input_pos); - memmove(input_buf + input_pos - 1, - input_buf + input_pos, + memmove(input_buf + input_pos - 1, input_buf + input_pos, input_len - input_pos + 1); } else { input_buf[input_len - 1] = '\0'; @@ -511,7 +502,7 @@ static void console_handle_char(int c) #ifndef CONFIG_EXPERIMENTAL_CONSOLE case KEY_DEL: if (input_pos == input_len) - break; /* Already at end */ + break; /* Already at end */ move_cursor_right(); @@ -544,8 +535,8 @@ static void console_handle_char(int c) /* Save command in history buffer */ if (input_len) { save_history(); - history_next = (history_next + 1) % - CONFIG_CONSOLE_HISTORY; + history_next = + (history_next + 1) % CONFIG_CONSOLE_HISTORY; history_pos = history_next; } #endif @@ -692,7 +683,7 @@ void console_task(void *u) console_handle_char(c); } - task_wait_event(-1); /* Wait for more input */ + task_wait_event(-1); /* Wait for more input */ } } @@ -703,7 +694,7 @@ void console_task(void *u) static int command_help(int argc, char **argv) { const int ncmds = __cmds_end - __cmds; - const int cols = 5; /* printing in five columns */ + const int cols = 5; /* printing in five columns */ const int rows = (ncmds + cols - 1) / cols; int i, j; @@ -715,16 +706,15 @@ static int command_help(int argc, char **argv) #ifdef CONFIG_CONSOLE_COMMAND_FLAGS ccputs("Command Flags Description\n"); for (i = 0; i < ncmds; i++) { - ccprintf(" %-14s %x %s\n", - __cmds[i].name, __cmds[i].flags, - __cmds[i].help); + ccprintf(" %-14s %x %s\n", __cmds[i].name, + __cmds[i].flags, __cmds[i].help); cflush(); } #else ccputs("Known commands:\n"); for (i = 0; i < ncmds; i++) { - ccprintf(" %-15s%s\n", - __cmds[i].name, __cmds[i].help); + ccprintf(" %-15s%s\n", __cmds[i].name, + __cmds[i].help); cflush(); } #endif @@ -771,8 +761,7 @@ static int command_help(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(help, command_help, - "[ list | ]", +DECLARE_SAFE_CONSOLE_COMMAND(help, command_help, "[ list | ]", "Print command help"); #ifdef CONFIG_CONSOLE_HISTORY @@ -788,7 +777,6 @@ static int command_history(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(history, command_history, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(history, command_history, NULL, "Print console history"); #endif -- cgit v1.2.1 From 0f10a3f55055e38c4e0df084825df5da864ebd12 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:09 -0600 Subject: board/felwinter/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I789f4cf09675ef05e3f8f69d3e77543cb1dfef82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728356 Reviewed-by: Jeremy Bettis --- board/felwinter/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/felwinter/fw_config.c b/board/felwinter/fw_config.c index 4228394d5b..7db3b24f74 100644 --- a/board/felwinter/fw_config.c +++ b/board/felwinter/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union brya_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 10679e81fa7e2b63bb23559a9cfc3a703e530f07 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:33 -0600 Subject: chip/stm32/registers-stm32l5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I41032b05b20e59fd6198a8059d5cf948dd6e282a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729534 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32l5.h | 2061 ++++++++++++++++++++-------------------- 1 file changed, 1024 insertions(+), 1037 deletions(-) diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index e7b8daee62..84177f715b 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -19,93 +19,93 @@ #endif /****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 6 -#define STM32_IRQ_FLASH_S 7 -#define STM32_IRQ_RCC 9 -#define STM32_IRQ_RCC_S 10 -#define STM32_IRQ_EXTI0 11 -#define STM32_IRQ_EXTI1 12 -#define STM32_IRQ_EXTI2 13 -#define STM32_IRQ_EXTI3 14 -#define STM32_IRQ_EXTI4 15 -#define STM32_IRQ_EXTI5 16 -#define STM32_IRQ_EXTI6 17 -#define STM32_IRQ_EXTI7 18 -#define STM32_IRQ_EXTI8 19 -#define STM32_IRQ_EXTI9 20 -#define STM32_IRQ_EXTI10 21 -#define STM32_IRQ_EXTI11 22 -#define STM32_IRQ_EXTI12 23 -#define STM32_IRQ_EXTI13 24 -#define STM32_IRQ_EXTI14 25 -#define STM32_IRQ_EXTI15 26 -#define STM32_IRQ_DMAMUX_OVR 27 -#define STM32_IRQ_DMAMUX_OVR_S 28 -#define STM32_IRQ_DMA_CHANNEL_1 29 -#define STM32_IRQ_DMA_CHANNEL_2 30 -#define STM32_IRQ_DMA_CHANNEL_3 31 -#define STM32_IRQ_DMA_CHANNEL_4 32 -#define STM32_IRQ_DMA_CHANNEL_5 33 -#define STM32_IRQ_DMA_CHANNEL_6 34 -#define STM32_IRQ_DMA_CHANNEL_7 35 -#define STM32_IRQ_DMA_CHANNEL_8 36 -#define STM32_IRQ_ADC1 37 -#define STM32_IRQ_TIM1_BRK 41 -#define STM32_IRQ_TIM1_UP 42 -#define STM32_IRQ_TIM1_TRG_COM 43 -#define STM32_IRQ_TIM1_CC 44 -#define STM32_IRQ_TIM2 45 -#define STM32_IRQ_TIM3 46 -#define STM32_IRQ_TIM4 47 -#define STM32_IRQ_TIM5 48 -#define STM32_IRQ_TIM6 49 -#define STM32_IRQ_TIM7 50 -#define STM32_IRQ_TIM8_BRK 51 -#define STM32_IRQ_TIM8_UP 52 -#define STM32_IRQ_TIM8_TRG_COM 53 -#define STM32_IRQ_TIM8_CC 54 -#define STM32_IRQ_I2C1_EV 55 -#define STM32_IRQ_I2C1_ER 56 -#define STM32_IRQ_I2C2_EV 57 -#define STM32_IRQ_I2C2_ER 58 -#define STM32_IRQ_SPI1 59 -#define STM32_IRQ_SPI2 60 -#define STM32_IRQ_USART1 61 -#define STM32_IRQ_USART2 62 -#define STM32_IRQ_USART3 63 -#define STM32_IRQ_USART4 64 -#define STM32_IRQ_USART5 65 -#define STM32_IRQ_LPUART1 66 -#define STM32_IRQ_LPTIM1 67 -#define STM32_IRQ_LPTIM2 68 -#define STM32_IRQ_TIM15 69 -#define STM32_IRQ_TIM16 70 -#define STM32_IRQ_TIM17 71 -#define STM32_IRQ_COMP 72 -#define STM32_IRQ_USB_FS 73 -#define STM32_IRQ_CRS 74 -#define STM32_IRQ_FMC 75 -#define STM32_IRQ_DMA2_CHANNEL1 80 -#define STM32_IRQ_DMA2_CHANNEL2 81 -#define STM32_IRQ_DMA2_CHANNEL3 82 -#define STM32_IRQ_DMA2_CHANNEL4 83 -#define STM32_IRQ_DMA2_CHANNEL5 84 -#define STM32_IRQ_DMA2_CHANNEL6 85 -#define STM32_IRQ_DMA2_CHANNEL7 86 -#define STM32_IRQ_DMA2_CHANNEL8 87 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_RTC_ALARM 2 +#define STM32_IRQ_FLASH 6 +#define STM32_IRQ_FLASH_S 7 +#define STM32_IRQ_RCC 9 +#define STM32_IRQ_RCC_S 10 +#define STM32_IRQ_EXTI0 11 +#define STM32_IRQ_EXTI1 12 +#define STM32_IRQ_EXTI2 13 +#define STM32_IRQ_EXTI3 14 +#define STM32_IRQ_EXTI4 15 +#define STM32_IRQ_EXTI5 16 +#define STM32_IRQ_EXTI6 17 +#define STM32_IRQ_EXTI7 18 +#define STM32_IRQ_EXTI8 19 +#define STM32_IRQ_EXTI9 20 +#define STM32_IRQ_EXTI10 21 +#define STM32_IRQ_EXTI11 22 +#define STM32_IRQ_EXTI12 23 +#define STM32_IRQ_EXTI13 24 +#define STM32_IRQ_EXTI14 25 +#define STM32_IRQ_EXTI15 26 +#define STM32_IRQ_DMAMUX_OVR 27 +#define STM32_IRQ_DMAMUX_OVR_S 28 +#define STM32_IRQ_DMA_CHANNEL_1 29 +#define STM32_IRQ_DMA_CHANNEL_2 30 +#define STM32_IRQ_DMA_CHANNEL_3 31 +#define STM32_IRQ_DMA_CHANNEL_4 32 +#define STM32_IRQ_DMA_CHANNEL_5 33 +#define STM32_IRQ_DMA_CHANNEL_6 34 +#define STM32_IRQ_DMA_CHANNEL_7 35 +#define STM32_IRQ_DMA_CHANNEL_8 36 +#define STM32_IRQ_ADC1 37 +#define STM32_IRQ_TIM1_BRK 41 +#define STM32_IRQ_TIM1_UP 42 +#define STM32_IRQ_TIM1_TRG_COM 43 +#define STM32_IRQ_TIM1_CC 44 +#define STM32_IRQ_TIM2 45 +#define STM32_IRQ_TIM3 46 +#define STM32_IRQ_TIM4 47 +#define STM32_IRQ_TIM5 48 +#define STM32_IRQ_TIM6 49 +#define STM32_IRQ_TIM7 50 +#define STM32_IRQ_TIM8_BRK 51 +#define STM32_IRQ_TIM8_UP 52 +#define STM32_IRQ_TIM8_TRG_COM 53 +#define STM32_IRQ_TIM8_CC 54 +#define STM32_IRQ_I2C1_EV 55 +#define STM32_IRQ_I2C1_ER 56 +#define STM32_IRQ_I2C2_EV 57 +#define STM32_IRQ_I2C2_ER 58 +#define STM32_IRQ_SPI1 59 +#define STM32_IRQ_SPI2 60 +#define STM32_IRQ_USART1 61 +#define STM32_IRQ_USART2 62 +#define STM32_IRQ_USART3 63 +#define STM32_IRQ_USART4 64 +#define STM32_IRQ_USART5 65 +#define STM32_IRQ_LPUART1 66 +#define STM32_IRQ_LPTIM1 67 +#define STM32_IRQ_LPTIM2 68 +#define STM32_IRQ_TIM15 69 +#define STM32_IRQ_TIM16 70 +#define STM32_IRQ_TIM17 71 +#define STM32_IRQ_COMP 72 +#define STM32_IRQ_USB_FS 73 +#define STM32_IRQ_CRS 74 +#define STM32_IRQ_FMC 75 +#define STM32_IRQ_DMA2_CHANNEL1 80 +#define STM32_IRQ_DMA2_CHANNEL2 81 +#define STM32_IRQ_DMA2_CHANNEL3 82 +#define STM32_IRQ_DMA2_CHANNEL4 83 +#define STM32_IRQ_DMA2_CHANNEL5 84 +#define STM32_IRQ_DMA2_CHANNEL6 85 +#define STM32_IRQ_DMA2_CHANNEL7 86 +#define STM32_IRQ_DMA2_CHANNEL8 87 /* To simplify code generation, define DMA channel 9..16 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 +#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_16 STM32_IRQ_DMA2_CHANNEL8 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -113,270 +113,268 @@ #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV #define STM32_IRQ_USB_LP STM32_IRQ_USB_FS - -#define PERIPH_BASE 0x40000000UL +#define PERIPH_BASE 0x40000000UL /*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) /*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL) -#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) -#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) -#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL) -#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL) -#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL) -#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL) -#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL) -#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL) +#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define STM32_TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define STM32_TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define STM32_USART4_BASE (APB1PERIPH_BASE + 0x4c00UL) +#define STM32_USART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define STM32_I2C4_BASE (APB1PERIPH_BASE + 0x8400UL) +#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) +#define STM32_LPTIM3_BASE (APB1PERIPH_BASE + 0x9800UL) +#define STM32_FDCAN_RAM_BASE (APB1PERIPH_BASE + 0xA400UL) +#define STM32_CAN_RAM_BASE (APB1PERIPH_BASE + 0xAC00UL) +#define STM32_USB_FS_BASE (APB1PERIPH_BASE + 0xD400UL) +#define STM32_USB_CAN_SRAM_BASE (APB1PERIPH_BASE + 0xD800UL) +#define STM32_UCPD1_BASE (APB1PERIPH_BASE + 0xDC00UL) /*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define STM32_EXTI_BASE (AHB1PERIPH_BASE + 0xf400UL) +#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define STM32_TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define STM32_TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) /*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) +#define STM32_DMA1_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_DMAMUX_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) +#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL) -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) +#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x20000UL) +#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x20400UL) +#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x20800UL) +#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x20C00UL) +#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x21000UL) +#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x21400UL) +#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x21800UL) +#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) +#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) /* Debug MCU registers base address */ -#define STM32_PACKAGE_BASE 0x0BFA0500UL -#define STM32_UID_BASE 0x0BFA0590UL -#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL +#define STM32_PACKAGE_BASE 0x0BFA0500UL +#define STM32_UID_BASE 0x0BFA0590UL +#define STM32_FLASHSIZE_BASE 0x0BFA05E0UL -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE +#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE +#define STM32_UNIQUE_ID_BASE STM32_UID_BASE #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) + +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR3_WUFIE BIT(22) + +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - -#define STM32_PWR_CR2_IOSV_POS 9U -#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS) -#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK -#define STM32_PWR_CR2_USV_POS 10U -#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS) -#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK - +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) + +#define PWR_CR1_LPMS_POS 0U +#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) +#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK +#define PWR_CR1_LPMS_STOP0 (0x00000000UL) +#define PWR_CR1_LPMS_STOP1_POS 0U +#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) +#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK +#define PWR_CR1_LPMS_STOP2_POS 1U +#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) +#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK +#define PWR_CR1_LPMS_STANDBY_POS 0U +#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) +#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK +#define PWR_CR1_LPMS_SHUTDOWN_POS 2U +#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) +#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK +#define PWR_CR1_VOS_POS 9U +#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS PWR_CR1_VOS_MSK +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) + +#define STM32_PWR_CR2_IOSV_POS 9U +#define STM32_PWR_CR2_IOSV_MASK BIT(STM32_PWR_CR2_IOSV_POS) +#define STM32_PWR_CR2_IOSV STM32_PWR_CR2_IOSV_MASK +#define STM32_PWR_CR2_USV_POS 10U +#define STM32_PWR_CR2_USV_MASK BIT(STM32_PWR_CR2_USV_POS) +#define STM32_PWR_CR2_USV STM32_PWR_CR2_USV_MASK /* --- Macro usage in ec code --- */ #define STM32_RCC_AHB2ENR_GPIOMASK \ @@ -388,139 +386,137 @@ #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN +#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN +#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN +#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN +#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN #ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) +#define STM32_RCC_PB2_TIM8 BIT(13) #endif #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) +#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) +#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) +#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) +#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) +#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) +#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) +#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) +#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) /* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CCIPR_UART_PCLK 0 +#define STM32_RCC_CCIPR_UART_SYSCLK 1 +#define STM32_RCC_CCIPR_UART_HSI16 2 +#define STM32_RCC_CCIPR_UART_LSE 3 + +#define STM32_RCC_CCIPR_I2C_PCLK 0 +#define STM32_RCC_CCIPR_I2C_SYSCLK 1 +#define STM32_RCC_CCIPR_I2C_HSI16 2 + +#define STM32_RCC_CCIPR_LPTIM_PCLK 0 +#define STM32_RCC_CCIPR_LPTIM_LSI 1 +#define STM32_RCC_CCIPR_LPTIM_HSI16 2 +#define STM32_RCC_CCIPR_LPTIM_LSE 3 + +#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 +#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 +#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 +#define STM32_RCC_CCIPR_SAI_EXTCLK 3 + +#define STM32_RCC_CCIPR_CLK48_NONE 0 +#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 +#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 +#define STM32_RCC_CCIPR_CLK48_MSI 3 + +#define STM32_RCC_CCIPR_ADC_NONE 0 +#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 +#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 +#define STM32_RCC_CCIPR_ADC_SYSCLK 3 + +#define STM32_RCC_CCIPR_SWPMI_PCLK 0 +#define STM32_RCC_CCIPR_SWPMI_HSI16 1 + +#define STM32_RCC_CCIPR_DFSDM_PCLK 0 +#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_CCIPR STM32_RCC_CCIPR1 -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C) +#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) +#define STM32_RCC_CCIPR1 REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_CCIPR STM32_RCC_CCIPR1 +#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0C) #define STM32_RCC_PLLSAI1_SUPPORT #define STM32_RCC_PLLP_SUPPORT @@ -528,236 +524,236 @@ #define STM32_RCC_PLLP_DIV_2_31_SUPPORT #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 /******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK +#define STM32_RCC_CR_MSION_POS 0U +#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) +#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK +#define STM32_RCC_CR_MSIRDY_POS 1U +#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) +#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK +#define STM32_RCC_CR_MSIPLLEN_POS 2U +#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) +#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK +#define STM32_RCC_CR_MSIRGSEL_POS 3U +#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) +#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK +#define STM32_RCC_CR_MSIRANGE_POS 4U +#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) + +#define STM32_RCC_CR_HSION_POS 8U +#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) +#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK +#define STM32_RCC_CR_HSIKERON_POS 9U +#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) +#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK +#define STM32_RCC_CR_HSIRDY_POS 10U +#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) +#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK +#define STM32_RCC_CR_HSIASFS_POS 11U +#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) +#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK + +#define STM32_RCC_CR_HSEON_POS 16U +#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) +#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK +#define STM32_RCC_CR_HSERDY_POS 17U +#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) +#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK +#define STM32_RCC_CR_HSEBYP_POS 18U +#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) +#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK +#define STM32_RCC_CR_CSSON_POS 19U +#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) +#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK + +#define STM32_RCC_CR_PLLON_POS 24U +#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) +#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK +#define STM32_RCC_CR_PLLRDY_POS 25U +#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) +#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK +#define STM32_RCC_CR_PLLSAI1ON_POS 26U +#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) +#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK +#define STM32_RCC_CR_PLLSAI1RDY_POS 27U +#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) +#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK /******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ /*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_POS 0U +#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK +#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) /*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_POS 8U +#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK +#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) /*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_POS 16U +#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK +#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) /*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_POS 24U +#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK +#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) /**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ /*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_POS 0U +#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK +#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) +#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) +#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) +#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) /*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_POS 2U +#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK +#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) +#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) +#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) +#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) +#define STM32_RCC_CFGR_HPRE_POS 4U +#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK +#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) + +#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) +#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) +#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) +#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) +#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) +#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) +#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) +#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) +#define STM32_RCC_CFGR_PPRE1_POS 8U +#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK +#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) + +#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) +#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) +#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) +#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK +#define STM32_RCC_CFGR_PPRE2_POS 11U +#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK +#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) + +#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) +#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) +#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) +#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) + +#define STM32_RCC_CFGR_STOPWUCK_POS 15U +#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) +#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK /*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) +#define STM32_RCC_CFGR_MCOSEL_POS 24U +#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK +#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) + +#define STM32_RCC_CFGR_MCOPRE_POS 28U +#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK +#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) + +#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 +#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE +#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 +#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 +#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 +#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 +#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 /**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK @@ -772,59 +768,59 @@ #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK + +#define STM32_RCC_PLLCFGR_PLLM_POS 4U +#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK +#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) + +#define STM32_RCC_PLLCFGR_PLLN_POS 8U +#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK +#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) + +#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U +#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) +#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK +#define STM32_RCC_PLLCFGR_PLLP_POS 17U +#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) +#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK +#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U +#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) +#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK + +#define STM32_RCC_PLLCFGR_PLLQ_POS 21U +#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK +#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) + +#define STM32_RCC_PLLCFGR_PLLREN_POS 24U +#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) +#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK +#define STM32_RCC_PLLCFGR_PLLR_POS 25U +#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK +#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) + +#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U +#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK +#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) /**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U @@ -846,7 +842,7 @@ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK @@ -1226,7 +1222,8 @@ #define STM32_RCC_AHB1ENR_DMA2EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMA2EN_POS) #define STM32_RCC_AHB1ENR_DMA2EN STM32_RCC_AHB1ENR_DMA2EN_MSK #define STM32_RCC_AHB1ENR_DMAMUX1EN_POS 2U -#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) +#define STM32_RCC_AHB1ENR_DMAMUX1EN_MSK \ + (0x1UL << STM32_RCC_AHB1ENR_DMAMUX1EN_POS) #define STM32_RCC_AHB1ENR_DMAMUX1EN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK #define STM32_RCC_AHB1ENR_DMAMUXEN STM32_RCC_AHB1ENR_DMAMUX1EN_MSK #define STM32_RCC_AHB1ENR_FLASHEN_POS 8U @@ -1339,12 +1336,10 @@ (0x1UL << STM32_RCC_APB1ENR1_USART3EN_POS) #define STM32_RCC_APB1ENR1_USART3EN STM32_RCC_APB1ENR1_USART3EN_MSK #define STM32_RCC_APB1ENR1_UART4EN_POS 19U -#define STM32_RCC_APB1ENR1_UART4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS) +#define STM32_RCC_APB1ENR1_UART4EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART4EN_POS) #define STM32_RCC_APB1ENR1_UART4EN STM32_RCC_APB1ENR1_UART4EN_MSK #define STM32_RCC_APB1ENR1_UART5EN_POS 20U -#define STM32_RCC_APB1ENR1_UART5EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS) +#define STM32_RCC_APB1ENR1_UART5EN_MSK (0x1UL << STM32_RCC_APB1ENR1_UART5EN_POS) #define STM32_RCC_APB1ENR1_UART5EN STM32_RCC_APB1ENR1_UART5EN_MSK #define STM32_RCC_APB1ENR1_I2C1EN_POS 21U #define STM32_RCC_APB1ENR1_I2C1EN_MSK (0x1UL << STM32_RCC_APB1ENR1_I2C1EN_POS) @@ -1378,8 +1373,7 @@ (0x1UL << STM32_RCC_APB1ENR2_LPUART1EN_POS) #define STM32_RCC_APB1ENR2_LPUART1EN STM32_RCC_APB1ENR2_LPUART1EN_MSK #define STM32_RCC_APB1ENR2_I2C4EN_POS 1U -#define STM32_RCC_APB1ENR2_I2C4EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS) +#define STM32_RCC_APB1ENR2_I2C4EN_MSK (0x1UL << STM32_RCC_APB1ENR2_I2C4EN_POS) #define STM32_RCC_APB1ENR2_I2C4EN STM32_RCC_APB1ENR2_I2C4EN_MSK #define STM32_RCC_APB1ENR2_LPTIM2EN_POS 5U #define STM32_RCC_APB1ENR2_LPTIM2EN_MSK \ @@ -1394,12 +1388,10 @@ (0x1UL << STM32_RCC_APB1ENR2_FDCAN1EN_POS) #define STM32_RCC_APB1ENR2_FDCAN1EN STM32_RCC_APB1ENR2_FDCAN1EN_MSK #define STM32_RCC_APB1ENR2_USBFSEN_POS 21U -#define STM32_RCC_APB1ENR2_USBFSEN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS) +#define STM32_RCC_APB1ENR2_USBFSEN_MSK (0x1UL << STM32_RCC_APB1ENR2_USBFSEN_POS) #define STM32_RCC_APB1ENR2_USBFSEN STM32_RCC_APB1ENR2_USBFSEN_MSK #define STM32_RCC_APB1ENR2_UCPD1EN_POS 23U -#define STM32_RCC_APB1ENR2_UCPD1EN_MSK \ - (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS) +#define STM32_RCC_APB1ENR2_UCPD1EN_MSK (0x1UL << STM32_RCC_APB1ENR2_UCPD1EN_POS) #define STM32_RCC_APB1ENR2_UCPD1EN STM32_RCC_APB1ENR2_UCPD1EN_MSK /************** BIT DEFINITION FOR STM32_RCC_APB2ENR REGISTER ***************/ @@ -1930,8 +1922,6 @@ #define STM32_CRS_CR_SWSYNC_MSK (0x1UL << STM32_CRS_CR_SWSYNC_POS) #define STM32_CRS_CR_SWSYNC STM32_CRS_CR_SWSYNC_MSK - - /*!< HSI48CAL configuration */ #define STM32_RCC_CRRCR_HSI48CAL_POS 7U #define STM32_RCC_CRRCR_HSI48CAL_MSK (0x1FFUL << STM32_RCC_CRRCR_HSI48CAL_POS) @@ -1951,102 +1941,100 @@ #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_SYSCFGEN BIT(0) +#define STM32_RCC_PB2_USART1 BIT(14) -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) +#define STM32_RCC_HB2_GPIOA BIT(0) +#define STM32_RCC_HB2_GPIOB BIT(1) +#define STM32_RCC_HB2_GPIOC BIT(2) +#define STM32_RCC_HB2_GPIOD BIT(3) +#define STM32_RCC_HB2_GPIOE BIT(4) +#define STM32_RCC_HB2_GPIOH BIT(7) +#define STM32_RCC_HB2_ADC1 BIT(13) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) +#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xff000000 +#define RESET_CAUSE_RMVF BIT(23) /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR +#define RESET_CAUSE_SBF BIT(8) +#define RESET_CAUSE_SBF_CLR BIT(8) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_WUTE BIT(10) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_WUTIE BIT(14) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_WUTWF BIT(2) +#define STM32_RTC_ISR_INITS BIT(4) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_WUTF BIT(9) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) #define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - + (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ + (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 + +#define RTC_TR_PM_POS 22U +#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) +#define RTC_TR_PM RTC_TR_PM_MSK +#define RTC_TR_HT_POS 20U +#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) +#define RTC_TR_HT RTC_TR_HT_MSK +#define RTC_TR_HU_POS 16U +#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) +#define RTC_TR_HU RTC_TR_HU_MSK +#define RTC_TR_MNT_POS 12U +#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) +#define RTC_TR_MNT RTC_TR_MNT_MSK +#define RTC_TR_MNU_POS 8U +#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) +#define RTC_TR_MNU RTC_TR_MNU_MSK +#define RTC_TR_ST_POS 4U +#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) +#define RTC_TR_ST RTC_TR_ST_MSK +#define RTC_TR_SU_POS 0U +#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) +#define RTC_TR_SU RTC_TR_SU_MSK /* --- SPI --- */ @@ -2063,8 +2051,8 @@ struct stm32_spi_regs { unsigned int crcpr; unsigned int rxcrcr; unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ + unsigned int i2scfgr; /* STM32L only */ + unsigned int i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -2074,216 +2062,216 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x20) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_ERR_MASK (0xc3fa) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x28) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) +#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x30) +#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x40) +#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x58) +#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x5C) /* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE +#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE -#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR -#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR +#define STM32_OPTB_WRP1AR STM32_FLASH_WRP1AR +#define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_RTC_ALR_EVENT BIT(18) +#define EXTI_RTC_ALR_EVENT BIT(18) /* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC1_ISR_ADRDY BIT(0) +#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC1_IER_AWDIE BIT(7) +#define STM32_ADC1_IER_OVRIE BIT(4) +#define STM32_ADC1_IER_EOSEQIE BIT(3) +#define STM32_ADC1_IER_EOCIE BIT(2) +#define STM32_ADC1_IER_EOSMPIE BIT(1) +#define STM32_ADC1_IER_ADRDYIE BIT(0) + +#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC1_CR_ADEN BIT(0) +#define STM32_ADC1_CR_ADDIS BIT(1) +#define STM32_ADC1_CR_ADSTP BIT(4) +#define STM32_ADC1_CR_ADVREGEN BIT(28) +#define STM32_ADC1_CR_DEEPPWD BIT(29) +#define STM32_ADC1_CR_ADCAL BIT(31) +#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) +#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) +#define STM32_ADC1_CFGR_AWDEN BIT(23) +#define STM32_ADC1_CFGR_AWDSGL BIT(22) +#define STM32_ADC1_CFGR_AUTDLY BIT(14) /* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) +#define STM32_ADC1_CFGR_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) +#define STM32_ADC1_CFGR_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) +#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) +#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) +#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) +#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) +#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) +#define STM32_ADC1_CFGR_ALIGN BIT(5) /* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) +#define STM32_ADC1_CFGR_TRG0 (0 << 6) +#define STM32_ADC1_CFGR_TRG1 (1 << 6) +#define STM32_ADC1_CFGR_TRG2 (2 << 6) +#define STM32_ADC1_CFGR_TRG3 (3 << 6) +#define STM32_ADC1_CFGR_TRG4 (4 << 6) +#define STM32_ADC1_CFGR_TRG5 (5 << 6) +#define STM32_ADC1_CFGR_TRG6 (6 << 6) +#define STM32_ADC1_CFGR_TRG7 (7 << 6) +#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC1_CFGR_DMACFG BIT(1) +#define STM32_ADC1_CFGR_DMAEN BIT(0) +#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC1_SMPR_SMP(s) ((s)-1) +#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) +#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) +#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) +#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) +#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) +#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) + +#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) + +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) + +#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) + +#define STM32_USB_ISTR_EP_ID_MASK (0x000f) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) + +#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) -#define STM32_USB_BCDR_DPPU BIT(15) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) + +#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) +#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) +#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) +#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) + +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) +#define STM32_USB_BCDR_DPPU BIT(15) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -2293,8 +2281,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- DMA --- */ @@ -2346,11 +2334,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -2361,8 +2349,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -2371,78 +2359,77 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ /* DMAMUX registers */ -#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) -#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) -#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) -#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) -#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) -#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) +#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) +#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) +#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) +#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) +#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) +#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) enum dmamux1_request { DMAMUX_REQ_ADC1 = 5, @@ -2538,9 +2525,9 @@ enum dmamux1_request { }; /* LPUART gets accessed as UART9 in STM32 uart module */ -#define STM32_USART9_BASE STM32_LPUART1_BASE -#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 -#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX -#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX +#define STM32_USART9_BASE STM32_LPUART1_BASE +#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 +#define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX +#define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 7be2bd96ad0da5b385a1409fb942c726ec740e5b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:04 -0600 Subject: zephyr/projects/corsola/src/variant_db_detection.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3da9ad0e6509c7334057abe86df23e82b19d7c1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730769 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/variant_db_detection.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/projects/corsola/src/variant_db_detection.c b/zephyr/projects/corsola/src/variant_db_detection.c index e5058bdcd5..2fe93535dd 100644 --- a/zephyr/projects/corsola/src/variant_db_detection.c +++ b/zephyr/projects/corsola/src/variant_db_detection.c @@ -12,8 +12,8 @@ #include "variant_db_detection.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static void corsola_db_config(enum corsola_db_type type) { @@ -21,7 +21,7 @@ static void corsola_db_config(enum corsola_db_type type) case CORSOLA_DB_HDMI: /* EC_X_GPIO1 */ gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_hdmi_pwr), - GPIO_OUTPUT_HIGH); + GPIO_OUTPUT_HIGH); /* X_EC_GPIO2 */ gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_ec_dp_hpd), GPIO_INPUT); @@ -29,7 +29,7 @@ static void corsola_db_config(enum corsola_db_type type) GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2)); /* EC_X_GPIO3 */ gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_ps185_pwrdn_odl), - GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN); + GPIO_OUTPUT_HIGH | GPIO_OPEN_DRAIN); return; case CORSOLA_DB_TYPEC: /* EC_X_GPIO1 */ @@ -42,9 +42,8 @@ static void corsola_db_config(enum corsola_db_type type) gpio_enable_dt_interrupt( GPIO_INT_FROM_NODELABEL(int_x_ec_gpio2)); /* EC_X_GPIO3 */ - gpio_pin_configure_dt( - GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd), - GPIO_OUTPUT_LOW); + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_dp_in_hpd), + GPIO_OUTPUT_LOW); return; default: break; -- cgit v1.2.1 From a16c4ac6d8470717a99247f054ecd684b141240a Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Mon, 27 Jun 2022 11:44:52 +1000 Subject: nereid: reduce battery I2C frequency to 50 kHz Nominal 100 kHz is slightly higher than 100 kHz, which exceeds the battery specifications. In the absence of a way to tune that speed downward, reduce it to 50 kHz instead. BUG=b:235430194 TEST=Functional and SI testing succeeds at the new speed BRANCH=none Change-Id: I5e388aca3cf0110b0aa1020d529e1c6d19d03f79 Signed-off-by: Peter Marheine Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721954 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/nereid_overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index 158629b1e9..8f73dfbfc4 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -297,7 +297,7 @@ &i2c1 { label = "I2C_BATTERY"; - clock-frequency = ; + clock-frequency = <50000>; pinctrl-0 = <&i2c1_clk_gpc1_default &i2c1_data_gpc2_default>; pinctrl-names = "default"; -- cgit v1.2.1 From 6a2997983fab0be8857657e96a4419a7b46c4fa9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:43 -0600 Subject: board/drawcia_riscv/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I635e0998199ff4b657316abd1e940d00d5be13ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728240 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/board.h | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/board/drawcia_riscv/board.h b/board/drawcia_riscv/board.h index 45f16c9ac3..921d2e066e 100644 --- a/board/drawcia_riscv/board.h +++ b/board/drawcia_riscv/board.h @@ -37,20 +37,21 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -83,8 +84,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -95,8 +96,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -119,21 +120,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 83e5646eca60497c60769868bb456b138e36c519 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:21 -0600 Subject: zephyr/projects/corsola/include/baseboard_usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I748c6be66a2ee86e24c598552daf59efa53892dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730735 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/include/baseboard_usbc_config.h | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/zephyr/projects/corsola/include/baseboard_usbc_config.h b/zephyr/projects/corsola/include/baseboard_usbc_config.h index eb09a86865..865ca8b0d4 100644 --- a/zephyr/projects/corsola/include/baseboard_usbc_config.h +++ b/zephyr/projects/corsola/include/baseboard_usbc_config.h @@ -11,17 +11,10 @@ void ppc_interrupt(enum gpio_signal signal); /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); /** -- cgit v1.2.1 From 8666dd2d36bb3696c509aace95ecdcb894ac4cb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:34 -0600 Subject: board/primus/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f7365efb668ced55e91c68d311128f89b0f7388 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727761 Reviewed-by: Jeremy Bettis --- board/primus/fw_config.h | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/primus/fw_config.h b/board/primus/fw_config.h index f8792f1443..a985583af0 100644 --- a/board/primus/fw_config.h +++ b/board/primus/fw_config.h @@ -25,21 +25,18 @@ enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_mlb_usb { - MLB_USB_TBT = 0, - MLB_USB_USB4 = 1 -}; +enum ec_cfg_mlb_usb { MLB_USB_TBT = 0, MLB_USB_USB4 = 1 }; union primus_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; - uint32_t reserved_0 : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t cellular_db : 2; - enum ec_cfg_mlb_usb mlb_usb : 1; - uint32_t reserved_1 : 18; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t reserved_0 : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t cellular_db : 2; + enum ec_cfg_mlb_usb mlb_usb : 1; + uint32_t reserved_1 : 18; }; uint32_t raw_value; }; -- cgit v1.2.1 From 99da43b8556c8aab95754a5762d81906e0d74a53 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:52 -0600 Subject: board/taniks/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I30ba883b0322cda04b72e22e10ac78eb27135c97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729010 Reviewed-by: Jeremy Bettis --- board/taniks/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/taniks/fans.c b/board/taniks/fans.c index d50d3e5506..d3ffa45eb9 100644 --- a/board/taniks/fans.c +++ b/board/taniks/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From e58f9d72b56f52bd8b02969db8997d402bcbd12b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:39 -0600 Subject: board/yorp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ce61daad25ca2e40d71839523036b7378479e3e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729121 Reviewed-by: Jeremy Bettis --- board/yorp/board.h | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/board/yorp/board.h b/board/yorp/board.h index 7e4dea76df..25651a902f 100644 --- a/board/yorp/board.h +++ b/board/yorp/board.h @@ -26,8 +26,8 @@ #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -50,8 +50,8 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ ADC_CH_COUNT }; @@ -62,18 +62,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From a3656eb1e497cc96191853d9f2fd9a4a2248b8e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:48 -0600 Subject: driver/touchpad_elan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I284d4e74c98c8eba32a5362e85bfc0a6c9b6507c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730147 Reviewed-by: Jeremy Bettis --- driver/touchpad_elan.c | 207 ++++++++++++++++++++++++------------------------- 1 file changed, 100 insertions(+), 107 deletions(-) diff --git a/driver/touchpad_elan.c b/driver/touchpad_elan.c index 6df4f0f7de..13c7cdf805 100644 --- a/driver/touchpad_elan.c +++ b/driver/touchpad_elan.c @@ -25,73 +25,73 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_TOUCHPAD, outstr) -#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_TOUCHPAD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args) -#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0) +#define TASK_EVENT_POWER TASK_EVENT_CUSTOM_BIT(0) /******************************************************************************/ /* How to talk to the controller */ /******************************************************************************/ -#define ELAN_VENDOR_ID 0x04f3 +#define ELAN_VENDOR_ID 0x04f3 -#define ETP_I2C_RESET 0x0100 -#define ETP_I2C_WAKE_UP 0x0800 -#define ETP_I2C_SLEEP 0x0801 +#define ETP_I2C_RESET 0x0100 +#define ETP_I2C_WAKE_UP 0x0800 +#define ETP_I2C_SLEEP 0x0801 -#define ETP_I2C_STAND_CMD 0x0005 -#define ETP_I2C_UNIQUEID_CMD 0x0101 -#define ETP_I2C_FW_VERSION_CMD 0x0102 -#define ETP_I2C_OSM_VERSION_CMD 0x0103 -#define ETP_I2C_XY_TRACENUM_CMD 0x0105 -#define ETP_I2C_MAX_X_AXIS_CMD 0x0106 -#define ETP_I2C_MAX_Y_AXIS_CMD 0x0107 -#define ETP_I2C_RESOLUTION_CMD 0x0108 -#define ETP_I2C_IAP_VERSION_CMD 0x0110 -#define ETP_I2C_PRESSURE_CMD 0x010A -#define ETP_I2C_SET_CMD 0x0300 -#define ETP_I2C_IAP_TYPE_CMD 0x0304 -#define ETP_I2C_POWER_CMD 0x0307 -#define ETP_I2C_FW_CHECKSUM_CMD 0x030F +#define ETP_I2C_STAND_CMD 0x0005 +#define ETP_I2C_UNIQUEID_CMD 0x0101 +#define ETP_I2C_FW_VERSION_CMD 0x0102 +#define ETP_I2C_OSM_VERSION_CMD 0x0103 +#define ETP_I2C_XY_TRACENUM_CMD 0x0105 +#define ETP_I2C_MAX_X_AXIS_CMD 0x0106 +#define ETP_I2C_MAX_Y_AXIS_CMD 0x0107 +#define ETP_I2C_RESOLUTION_CMD 0x0108 +#define ETP_I2C_IAP_VERSION_CMD 0x0110 +#define ETP_I2C_PRESSURE_CMD 0x010A +#define ETP_I2C_SET_CMD 0x0300 +#define ETP_I2C_IAP_TYPE_CMD 0x0304 +#define ETP_I2C_POWER_CMD 0x0307 +#define ETP_I2C_FW_CHECKSUM_CMD 0x030F -#define ETP_ENABLE_ABS 0x0001 +#define ETP_ENABLE_ABS 0x0001 -#define ETP_DISABLE_POWER 0x0001 +#define ETP_DISABLE_POWER 0x0001 -#define ETP_I2C_REPORT_LEN 34 +#define ETP_I2C_REPORT_LEN 34 -#define ETP_MAX_FINGERS 5 -#define ETP_FINGER_DATA_LEN 5 +#define ETP_MAX_FINGERS 5 +#define ETP_FINGER_DATA_LEN 5 -#define ETP_PRESSURE_OFFSET 25 -#define ETP_FWIDTH_REDUCE 90 +#define ETP_PRESSURE_OFFSET 25 +#define ETP_FWIDTH_REDUCE 90 -#define ETP_REPORT_ID 0x5D -#define ETP_REPORT_ID_OFFSET 2 -#define ETP_TOUCH_INFO_OFFSET 3 -#define ETP_FINGER_DATA_OFFSET 4 -#define ETP_HOVER_INFO_OFFSET 30 -#define ETP_MAX_REPORT_LEN 34 +#define ETP_REPORT_ID 0x5D +#define ETP_REPORT_ID_OFFSET 2 +#define ETP_TOUCH_INFO_OFFSET 3 +#define ETP_FINGER_DATA_OFFSET 4 +#define ETP_HOVER_INFO_OFFSET 30 +#define ETP_MAX_REPORT_LEN 34 -#define ETP_IAP_START_ADDR 0x0083 +#define ETP_IAP_START_ADDR 0x0083 -#define ETP_I2C_IAP_RESET_CMD 0x0314 -#define ETP_I2C_IAP_RESET 0xF0F0 -#define ETP_I2C_IAP_CTRL_CMD 0x0310 -#define ETP_I2C_MAIN_MODE_ON BIT(9) -#define ETP_I2C_IAP_CMD 0x0311 -#define ETP_I2C_IAP_PASSWORD 0x1EA5 +#define ETP_I2C_IAP_RESET_CMD 0x0314 +#define ETP_I2C_IAP_RESET 0xF0F0 +#define ETP_I2C_IAP_CTRL_CMD 0x0310 +#define ETP_I2C_MAIN_MODE_ON BIT(9) +#define ETP_I2C_IAP_CMD 0x0311 +#define ETP_I2C_IAP_PASSWORD 0x1EA5 -#define ETP_I2C_IAP_REG_L 0x01 -#define ETP_I2C_IAP_REG_H 0x06 +#define ETP_I2C_IAP_REG_L 0x01 +#define ETP_I2C_IAP_REG_H 0x06 -#define ETP_FW_IAP_PAGE_ERR BIT(5) -#define ETP_FW_IAP_INTF_ERR BIT(4) +#define ETP_FW_IAP_PAGE_ERR BIT(5) +#define ETP_FW_IAP_INTF_ERR BIT(4) #ifdef CONFIG_USB_UPDATE /* The actual FW_SIZE depends on IC. */ -#define FW_SIZE CONFIG_TOUCHPAD_VIRTUAL_SIZE +#define FW_SIZE CONFIG_TOUCHPAD_VIRTUAL_SIZE #endif struct { @@ -124,8 +124,8 @@ static int elan_tp_read_cmd(uint16_t reg, uint16_t *val) buf[1] = reg >> 8; return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, - buf, sizeof(buf), (uint8_t *)val, sizeof(*val)); + CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf), + (uint8_t *)val, sizeof(*val)); } static int elan_tp_write_cmd(uint16_t reg, uint16_t val) @@ -138,8 +138,8 @@ static int elan_tp_write_cmd(uint16_t reg, uint16_t val) buf[3] = val >> 8; return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, - buf, sizeof(buf), NULL, 0); + CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, buf, sizeof(buf), NULL, + 0); } /* Power is on by default. */ @@ -171,7 +171,7 @@ out: return rv; } -static int finger_status[ETP_MAX_FINGERS] = {0}; +static int finger_status[ETP_MAX_FINGERS] = { 0 }; /* * Timestamp of last interrupt (32 bits are enough as we divide the value by 100 @@ -192,15 +192,14 @@ static int elan_tp_read_report(void) int i, ri; uint8_t touch_info; uint8_t hover_info; - uint8_t *finger = tp_buf+ETP_FINGER_DATA_OFFSET; + uint8_t *finger = tp_buf + ETP_FINGER_DATA_OFFSET; struct usb_hid_touchpad_report report; uint16_t timestamp; /* Compute and save timestamp early in case another interrupt comes. */ timestamp = irq_ts / USB_HID_TOUCHPAD_TIMESTAMP_UNIT; - rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, + rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, NULL, 0, tp_buf, ETP_I2C_REPORT_LEN); if (rv) { @@ -221,14 +220,14 @@ static int elan_tp_read_report(void) hover_info = tp_buf[ETP_HOVER_INFO_OFFSET]; for (i = 0; i < ETP_MAX_FINGERS; i++) { - int valid = touch_info & (1 << (3+i)); + int valid = touch_info & (1 << (3 + i)); if (valid) { int width = finger[3] & 0x0f; int height = (finger[3] & 0xf0) >> 4; int pressure = finger[4] + elan_tp_params.pressure_adj; pressure = DIV_ROUND_NEAREST(pressure * pressure_mult, - pressure_div); + pressure_div); width = MIN(4095, width * elan_tp_params.width_x); height = MIN(4095, height * elan_tp_params.width_y); @@ -240,8 +239,8 @@ static int elan_tp_read_report(void) report.finger[ri].id = i; report.finger[ri].width = width; report.finger[ri].height = height; - report.finger[ri].x = - ((finger[0] & 0xf0) << 4) | finger[1]; + report.finger[ri].x = ((finger[0] & 0xf0) << 4) | + finger[1]; report.finger[ri].y = elan_tp_params.max_y - (((finger[0] & 0x0f) << 8) | finger[2]); @@ -331,8 +330,7 @@ static void elan_tp_init(void) elan_tp_write_cmd(ETP_I2C_STAND_CMD, ETP_I2C_RESET); msleep(100); - rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, + rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, NULL, 0, val, sizeof(val)); CPRINTS("reset rv %d buf=%04x", rv, *((uint16_t *)val)); @@ -347,7 +345,7 @@ static void elan_tp_init(void) goto out; rv = elan_tp_read_cmd(ETP_I2C_IAP_VERSION_CMD, - &elan_tp_params.iap_version); + &elan_tp_params.iap_version); CPRINTS("%s: iap_version:%04X.", __func__, elan_tp_params.iap_version); elan_tp_params.iap_version >>= 8; if (rv) @@ -389,22 +387,22 @@ static void elan_tp_init(void) if (rv) goto out; - dpi_x = 10*val[0] + 790; - dpi_y = 10*val[1] + 790; + dpi_x = 10 * val[0] + 790; + dpi_y = 10 * val[1] + 790; - CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d", - elan_tp_params.max_x, elan_tp_params.max_y, - elan_tp_params.width_x, elan_tp_params.width_y, - elan_tp_params.pressure_adj, dpi_x, dpi_y); + CPRINTS("max=%d/%d width=%d/%d adj=%d dpi=%d/%d", elan_tp_params.max_x, + elan_tp_params.max_y, elan_tp_params.width_x, + elan_tp_params.width_y, elan_tp_params.pressure_adj, dpi_x, + dpi_y); #ifdef CONFIG_USB_HID_TOUCHPAD /* Validity check dimensions provided at build time. */ if (elan_tp_params.max_x != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X || elan_tp_params.max_y != CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y || calc_physical_dimension(dpi_x, elan_tp_params.max_x) != - CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X || + CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X || calc_physical_dimension(dpi_y, elan_tp_params.max_y) != - CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) { + CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y) { CPRINTS("*** TP mismatch!"); } #endif @@ -469,7 +467,7 @@ static int elan_read_write_iap_type(void) uint16_t val; if (elan_tp_write_cmd(ETP_I2C_IAP_TYPE_CMD, - elan_tp_params.page_size / 2)) + elan_tp_params.page_size / 2)) return EC_ERROR_UNKNOWN; if (elan_tp_read_cmd(ETP_I2C_IAP_TYPE_CMD, &val)) @@ -477,7 +475,6 @@ static int elan_read_write_iap_type(void) if (val == elan_tp_params.page_size / 2) return EC_SUCCESS; - } return EC_ERROR_UNKNOWN; } @@ -527,7 +524,7 @@ static int elan_prepare_for_update(void) static int touchpad_update_page(const uint8_t *data) { - const uint8_t cmd[2] = {ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H}; + const uint8_t cmd[2] = { ETP_I2C_IAP_REG_L, ETP_I2C_IAP_REG_H }; uint16_t checksum = 0; uint16_t rx_buf; int i, rv; @@ -539,13 +536,13 @@ static int touchpad_update_page(const uint8_t *data) i2c_lock(CONFIG_TOUCHPAD_I2C_PORT, 1); rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, - cmd, sizeof(cmd), NULL, 0, I2C_XFER_START); + CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, cmd, sizeof(cmd), + NULL, 0, I2C_XFER_START); if (rv) goto fail; rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, - data, elan_tp_params.page_size, NULL, 0, 0); + CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, data, + elan_tp_params.page_size, NULL, 0, 0); if (rv) goto fail; rv = i2c_xfer_unlocked(CONFIG_TOUCHPAD_I2C_PORT, @@ -564,8 +561,7 @@ fail: rv = elan_tp_read_cmd(ETP_I2C_IAP_CTRL_CMD, &rx_buf); if (rv || (rx_buf & (ETP_FW_IAP_PAGE_ERR | ETP_FW_IAP_INTF_ERR))) { - CPRINTS("%s: IAP reports failed write : %x.", - __func__, rx_buf); + CPRINTS("%s: IAP reports failed write : %x.", __func__, rx_buf); return EC_ERROR_UNKNOWN; } return 0; @@ -580,8 +576,8 @@ int touchpad_update_write(int offset, int size, const uint8_t *data) if (offset == 0) { /* Verify the IC type is aligned with defined firmware size */ - if (elan_tp_params.page_size * elan_tp_params.page_count - != FW_SIZE) { + if (elan_tp_params.page_size * elan_tp_params.page_count != + FW_SIZE) { CPRINTS("%s: IC(%d*%d) size and FW_SIZE(%d) mismatch", __func__, elan_tp_params.page_count, elan_tp_params.page_size, FW_SIZE); @@ -599,7 +595,8 @@ int touchpad_update_write(int offset, int size, const uint8_t *data) if (offset <= (ETP_IAP_START_ADDR * 2) && (ETP_IAP_START_ADDR * 2) < (offset + size)) { iap_addr = ((data[ETP_IAP_START_ADDR * 2 - offset + 1] << 8) | - data[ETP_IAP_START_ADDR * 2 - offset]) << 1; + data[ETP_IAP_START_ADDR * 2 - offset]) + << 1; CPRINTS("%s: payload starts from 0x%x.", __func__, iap_addr); } @@ -608,7 +605,7 @@ int touchpad_update_write(int offset, int size, const uint8_t *data) return EC_ERROR_INVAL; for (addr = offset; addr < (offset + size); - addr += elan_tp_params.page_size) { + addr += elan_tp_params.page_size) { if (iap_addr > addr) /* Skip chunk */ continue; rv = touchpad_update_page(data + addr - offset); @@ -632,21 +629,17 @@ int touchpad_update_write(int offset, int size, const uint8_t *data) #define TOUCHPAD_ELAN_DEBUG_CMD_LENGTH 50 #define TOUCHPAD_ELAN_DEBUG_NUM_CMD 2 -static const uint8_t -allowed_command_hashes[TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = { - { - 0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c, - 0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3, - 0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b, - 0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48 - }, - { - 0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76, - 0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9, - 0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d, - 0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74 - }, -}; +static const uint8_t allowed_command_hashes + [TOUCHPAD_ELAN_DEBUG_NUM_CMD][SHA256_DIGEST_SIZE] = { + { 0x0a, 0xf6, 0x37, 0x03, 0x93, 0xb2, 0xde, 0x8c, + 0x56, 0x7b, 0x86, 0xba, 0xa6, 0x79, 0xe3, 0xa3, + 0x8b, 0xc7, 0x15, 0xf2, 0x53, 0xcf, 0x71, 0x8b, + 0x3d, 0xe4, 0x81, 0xf9, 0xd9, 0xa8, 0x78, 0x48 }, + { 0xac, 0xe5, 0xbf, 0x17, 0x1f, 0xde, 0xce, 0x76, + 0x0c, 0x0e, 0xf8, 0xa2, 0xe9, 0x67, 0x2d, 0xc9, + 0x1b, 0xd4, 0xba, 0x34, 0x51, 0xca, 0xf6, 0x6d, + 0x7b, 0xb2, 0x1f, 0x14, 0x82, 0x1c, 0x0b, 0x74 }, + }; /* Debugging commands need to allocate a <=1k buffer. */ SHARED_MEM_CHECK_SIZE(1024); @@ -677,8 +670,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, uint8_t *command_hash; unsigned int offset = param[1]; unsigned int write_length = param[2]; - unsigned int read_length = - ((unsigned int)param[3] << 8) | param[4]; + unsigned int read_length = ((unsigned int)param[3] << 8) | + param[4]; int i; int match; int rv; @@ -688,13 +681,14 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, return EC_RES_INVALID_PARAM; SHA256_init(&ctx); - SHA256_update(&ctx, param+5, TOUCHPAD_ELAN_DEBUG_CMD_LENGTH-5); + SHA256_update(&ctx, param + 5, + TOUCHPAD_ELAN_DEBUG_CMD_LENGTH - 5); command_hash = SHA256_final(&ctx); match = 0; for (i = 0; i < TOUCHPAD_ELAN_DEBUG_NUM_CMD; i++) { if (!memcmp(command_hash, allowed_command_hashes[i], - sizeof(allowed_command_hashes[i]))) { + sizeof(allowed_command_hashes[i]))) { match = 1; break; } @@ -711,8 +705,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, buffer_size = read_length; if (read_length > 0) { - if (shared_mem_acquire(buffer_size, - (char **)&buffer) != EC_SUCCESS) { + if (shared_mem_acquire(buffer_size, (char **)&buffer) != + EC_SUCCESS) { buffer = NULL; buffer_size = 0; return EC_RES_BUSY; @@ -722,9 +716,8 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, } rv = i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, - CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, - ¶m[offset], write_length, - buffer, read_length); + CONFIG_TOUCHPAD_I2C_ADDR_FLAGS, ¶m[offset], + write_length, buffer, read_length); if (rv) return EC_RES_BUS_ERROR; @@ -796,7 +789,7 @@ static void touchpad_power_control(void) #ifdef CONFIG_USB_SUSPEND enable = enable && - (!usb_is_suspended() || usb_is_remote_wakeup_enabled()); + (!usb_is_suspended() || usb_is_remote_wakeup_enabled()); #endif #ifdef CONFIG_TABLET_MODE -- cgit v1.2.1 From 83259b0c9176ac8f0d6a6f92be1195ce3346f408 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:43 -0600 Subject: zephyr/projects/nissa/src/board_power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53f2ecd9adcb9322a88688eb5cb9bf28e0f7b333 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730782 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/board_power.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/zephyr/projects/nissa/src/board_power.c b/zephyr/projects/nissa/src/board_power.c index 8180b2c8af..b1eb83c145 100644 --- a/zephyr/projects/nissa/src/board_power.c +++ b/zephyr/projects/nissa/src/board_power.c @@ -19,7 +19,7 @@ LOG_MODULE_DECLARE(ap_pwrseq, LOG_LEVEL_INF); -#define X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS 5 +#define X86_NON_DSX_ADLP_NONPWRSEQ_FORCE_SHUTDOWN_TO_MS 5 static bool s0_stable; @@ -48,7 +48,7 @@ void board_ap_power_force_shutdown(void) power_signal_set(PWR_EC_SOC_DSW_PWROK, 0); while (power_signal_get(PWR_RSMRST) == 0 && - power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) { + power_signal_get(PWR_SLP_SUS) == 0 && timeout_ms > 0) { k_msleep(1); timeout_ms--; } @@ -88,10 +88,9 @@ void board_ap_power_action_g3_s5(void) power_signal_set(PWR_EN_PP3300_A, 1); power_wait_signals_timeout(IN_PGOOD_ALL_CORE, - AP_PWRSEQ_DT_VALUE(wait_signal_timeout)); + AP_PWRSEQ_DT_VALUE(wait_signal_timeout)); - generate_ec_soc_dsw_pwrok_handler( - AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay)); + generate_ec_soc_dsw_pwrok_handler(AP_PWRSEQ_DT_VALUE(dsw_pwrok_delay)); s0_stable = false; } @@ -132,8 +131,8 @@ int board_ap_power_assert_pch_power_ok(void) bool board_ap_power_check_power_rails_enabled(void) { return power_signal_get(PWR_EN_PP3300_A) && - power_signal_get(PWR_EN_PP5000_A) && - power_signal_get(PWR_EC_SOC_DSW_PWROK); + power_signal_get(PWR_EN_PP5000_A) && + power_signal_get(PWR_EC_SOC_DSW_PWROK); } int board_power_signal_get(enum power_signal signal) @@ -154,7 +153,7 @@ int board_power_signal_get(enum power_signal signal) return 0; } if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) { + GPIO_DT_FROM_NODELABEL(gpio_all_sys_pwrgd))) { return 0; } if (!power_signal_get(PWR_PG_PP1P05)) { -- cgit v1.2.1 From ea2e495bce7d680ea78711a226b2e15b5038fc84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:24 -0600 Subject: driver/accelgyro_bmi260.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0e11a92420e5caf73017c527481d10e8f9aa8d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729913 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi260.c | 154 +++++++++++++++++++--------------------------- 1 file changed, 65 insertions(+), 89 deletions(-) diff --git a/driver/accelgyro_bmi260.c b/driver/accelgyro_bmi260.c index cf2b019cb2..8b3f3acc13 100644 --- a/driver/accelgyro_bmi260.c +++ b/driver/accelgyro_bmi260.c @@ -23,7 +23,6 @@ #include "util.h" #include "watchdog.h" - #ifdef CONFIG_ACCELGYRO_BMI260_INT_EVENT #define ACCELGYRO_BMI260_INT_ENABLE #endif @@ -37,52 +36,43 @@ #include "bmi260/accelgyro_bmi260_config_tbin.h" #endif /* CONFIG_ACCELGYRO_BMI260 */ - #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCELGYRO_BMI260_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; /* * The gyro start-up time is 45ms in normal mode * 2ms in fast start-up mode */ -static int wakeup_time[] = { - [MOTIONSENSE_TYPE_ACCEL] = 2, - [MOTIONSENSE_TYPE_GYRO] = 45, - [MOTIONSENSE_TYPE_MAG] = 1 -}; +static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 2, + [MOTIONSENSE_TYPE_GYRO] = 45, + [MOTIONSENSE_TYPE_MAG] = 1 }; static int enable_sensor(const struct motion_sensor_t *s, int enable) { int ret; - ret = bmi_enable_reg8(s, BMI260_PWR_CTRL, - BMI260_PWR_EN(s->type), + ret = bmi_enable_reg8(s, BMI260_PWR_CTRL, BMI260_PWR_EN(s->type), enable); if (ret) return ret; if (s->type == MOTIONSENSE_TYPE_GYRO) { /* switch to performance mode */ - ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type), - BMI260_FILTER_PERF | - BMI260_GYR_NOISE_PERF, - enable); + ret = bmi_enable_reg8( + s, BMI_CONF_REG(s->type), + BMI260_FILTER_PERF | BMI260_GYR_NOISE_PERF, enable); } else { ret = bmi_enable_reg8(s, BMI_CONF_REG(s->type), - BMI260_FILTER_PERF, - enable); + BMI260_FILTER_PERF, enable); } return ret; - } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, - int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { int ret, normalized_rate; uint8_t reg_val; @@ -106,8 +96,7 @@ static int set_data_rate(const struct motion_sensor_t *s, msleep(wakeup_time[s->type]); } - ret = bmi_get_normalized_rate(s, rate, rnd, - &normalized_rate, ®_val); + ret = bmi_get_normalized_rate(s, rate, rnd, &normalized_rate, ®_val); if (ret) return ret; @@ -117,8 +106,7 @@ static int set_data_rate(const struct motion_sensor_t *s, */ mutex_lock(s->mutex); - ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), - reg_val, BMI_ODR_MASK); + ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK); if (ret != EC_SUCCESS) goto accel_cleanup; @@ -136,21 +124,20 @@ accel_cleanup: return ret; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { int ret, val98, val_nv_conf; intv3_t v = { offset[X], offset[Y], offset[Z] }; rotate_inv(v, *s->rot_standard_ref, v); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI260_OFFSET_EN_GYR98, &val98); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_OFFSET_EN_GYR98, + &val98); if (ret) return ret; - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI260_NV_CONF, &val_nv_conf); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF, + &val_nv_conf); if (ret) return ret; @@ -160,8 +147,7 @@ static int set_offset(const struct motion_sensor_t *s, if (ret != EC_SUCCESS) return ret; - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_NV_CONF, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_NV_CONF, val_nv_conf | BMI260_ACC_OFFSET_EN); break; case MOTIONSENSE_TYPE_GYRO: @@ -179,8 +165,8 @@ static int set_offset(const struct motion_sensor_t *s, return ret; } -static int wait_and_read_data(const struct motion_sensor_t *s, - intv3_t v, int try_cnt, int msec) +static int wait_and_read_data(const struct motion_sensor_t *s, intv3_t v, + int try_cnt, int msec) { uint8_t data[6]; int ret, status = 0; @@ -188,8 +174,8 @@ static int wait_and_read_data(const struct motion_sensor_t *s, /* Check if data is ready */ while (try_cnt && !(status & BMI260_DRDY_ACC)) { msleep(msec); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI260_STATUS, &status); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_STATUS, + &status); if (ret) return ret; try_cnt -= 1; @@ -197,18 +183,18 @@ static int wait_and_read_data(const struct motion_sensor_t *s, if (!(status & BMI260_DRDY_ACC)) return EC_ERROR_TIMEOUT; /* Read 6 bytes starting at xyz_reg */ - ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, - bmi_get_xyz_reg(s), data, 6); + ret = bmi_read_n(s->port, s->i2c_spi_addr_flags, bmi_get_xyz_reg(s), + data, 6); bmi_normalize(s, v, data); return ret; } -static int calibrate_offset(const struct motion_sensor_t *s, - int range, intv3_t target, int16_t *offset) +static int calibrate_offset(const struct motion_sensor_t *s, int range, + intv3_t target, int16_t *offset) { int ret = EC_ERROR_UNKNOWN; int i, n_sample = 32; - int data_diff[3] = {0}; + int data_diff[3] = { 0 }; /* Manually offset compensation */ for (i = 0; i < n_sample; ++i) { @@ -224,8 +210,9 @@ static int calibrate_offset(const struct motion_sensor_t *s, /* The data LSB: 1000 * range / 32768 (mdps | mg)*/ for (i = X; i <= Z; ++i) - offset[i] -= ((int64_t)(data_diff[i] / n_sample) * - 1000 * range) >> 15; + offset[i] -= + ((int64_t)(data_diff[i] / n_sample) * 1000 * range) >> + 15; return ret; } @@ -234,7 +221,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) int ret, rate; int16_t temp; int16_t offset[3]; - intv3_t target = {0, 0, 0}; + intv3_t target = { 0, 0, 0 }; /* Get sensor range for calibration*/ int range = s->current_range; @@ -266,7 +253,7 @@ static int perform_calib(struct motion_sensor_t *s, int enable) /* Unreachable due to sensor type check above. */ ASSERT(false); break; - /* LCOV_EXCL_STOP */ + /* LCOV_EXCL_STOP */ } /* Get the calibrated offset */ @@ -296,52 +283,45 @@ static __maybe_unused int config_interrupt(const struct motion_sensor_t *s) int ret; mutex_lock(s->mutex); - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_CMD_REG, BMI260_CMD_FIFO_FLUSH); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG, + BMI260_CMD_FIFO_FLUSH); /* configure int1 as an interrupt */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_INT1_IO_CTRL, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT1_IO_CTRL, BMI260_INT1_OUTPUT_EN); if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT)) /* TODO(chingkang): Test it if we want int2 as an interrupt */ /* configure int2 as an interrupt */ ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_INT2_IO_CTRL, - BMI260_INT2_OUTPUT_EN); + BMI260_INT2_IO_CTRL, BMI260_INT2_OUTPUT_EN); else /* configure int2 as an external input. */ ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_INT2_IO_CTRL, - BMI260_INT2_INPUT_EN); + BMI260_INT2_IO_CTRL, BMI260_INT2_INPUT_EN); /* map fifo water mark to int 1 */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_INT_MAP_DATA, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_INT_MAP_DATA, BMI260_INT_MAP_DATA_REG(1, FWM) | - BMI260_INT_MAP_DATA_REG(1, FFULL)); + BMI260_INT_MAP_DATA_REG(1, FFULL)); /* * Configure fifo watermark to int whenever there's any data in * there */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_FIFO_WTM_0, 1); - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_FIFO_WTM_1, 0); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_0, 1); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_WTM_1, 0); if (IS_ENABLED(CONFIG_ACCELGYRO_BMI260_INT2_OUTPUT)) ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_FIFO_CONFIG_1, - BMI260_FIFO_HEADER_EN); + BMI260_FIFO_CONFIG_1, BMI260_FIFO_HEADER_EN); else ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_CONFIG_1, - (BMI260_FIFO_TAG_INT_LEVEL << - BMI260_FIFO_TAG_INT2_EN_OFFSET) | - BMI260_FIFO_HEADER_EN); + (BMI260_FIFO_TAG_INT_LEVEL + << BMI260_FIFO_TAG_INT2_EN_OFFSET) | + BMI260_FIFO_HEADER_EN); /* disable FIFO sensortime frame */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_FIFO_CONFIG_0, 0); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_FIFO_CONFIG_0, + 0); mutex_unlock(s->mutex); return ret; } @@ -375,7 +355,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) int rv; if ((s->type != MOTIONSENSE_TYPE_ACCEL) || - (!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT))) + (!(*event & CONFIG_ACCELGYRO_BMI260_INT_EVENT))) return EC_ERROR_NOT_HANDLED; do { @@ -398,17 +378,17 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) return EC_SUCCESS; } -#endif /* ACCELGYRO_BMI260_INT_ENABLE */ +#endif /* ACCELGYRO_BMI260_INT_ENABLE */ /* * If the .init_rom section is not memory mapped, we need a static * buffer in RAM to access the BMI configuration data. */ #ifdef CONFIG_CHIP_INIT_ROM_REGION -#define BMI_RAM_BUFFER_SIZE 256 +#define BMI_RAM_BUFFER_SIZE 256 static uint8_t bmi_ram_buffer[BMI_RAM_BUFFER_SIZE]; #else -#define BMI_RAM_BUFFER_SIZE 0 +#define BMI_RAM_BUFFER_SIZE 0 static uint8_t *bmi_ram_buffer; #endif @@ -464,8 +444,7 @@ static int bmi_config_load(const struct motion_sensor_t *s) for (i = 0; i < bmi_config_tbin_len; i += burst_write_len) { uint8_t addr[2]; - const int len = MIN(burst_write_len, - bmi_config_tbin_len - i); + const int len = MIN(burst_write_len, bmi_config_tbin_len - i); addr[0] = (i / 2) & 0xF; addr[1] = (i / 2) >> 4; @@ -480,17 +459,17 @@ static int bmi_config_load(const struct motion_sensor_t *s) * data through a RAM buffer. */ ret = init_rom_copy((int)&bmi_config_tbin[i], len, - bmi_ram_buffer); + bmi_ram_buffer); if (ret) break; ret = bmi_write_n(s->port, s->i2c_spi_addr_flags, - BMI260_INIT_DATA, - bmi_ram_buffer, len); + BMI260_INIT_DATA, bmi_ram_buffer, + len); } else { ret = bmi_write_n(s->port, s->i2c_spi_addr_flags, - BMI260_INIT_DATA, - &bmi_config[i], len); + BMI260_INIT_DATA, &bmi_config[i], + len); } if (ret) @@ -530,7 +509,7 @@ static int init_config(const struct motion_sensor_t *s) for (i = 0; i < 15; ++i) { msleep(10); ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI260_INTERNAL_STATUS, &init_status); + BMI260_INTERNAL_STATUS, &init_status); if (ret) break; init_status &= BMI260_MESSAGE_MASK; @@ -547,8 +526,7 @@ static int init(struct motion_sensor_t *s) int ret = 0, tmp, i; struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI260_CHIP_ID, &tmp); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI260_CHIP_ID, &tmp); if (ret) return EC_ERROR_UNKNOWN; @@ -567,20 +545,18 @@ static int init(struct motion_sensor_t *s) return EC_ERROR_ACCESS_DENIED; } - if (s->type == MOTIONSENSE_TYPE_ACCEL) { struct bmi_drv_data_t *data = BMI_GET_DATA(s); /* Reset the chip to be in a good state */ - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI260_CMD_REG, BMI260_CMD_SOFT_RESET); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI260_CMD_REG, + BMI260_CMD_SOFT_RESET); msleep(2); if (init_config(s)) return EC_ERROR_INVALID_CONFIG; data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED | - (BMI_FIFO_ALL_MASK << - BMI_FIFO_FLAG_OFFSET)); + (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET)); } for (i = X; i <= Z; i++) -- cgit v1.2.1 From 9c233b9b7f9fb1eb0cc1f03460aa913ead97a704 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:53 -0600 Subject: chip/ish/ipc_heci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc7ac8f4c1cfbc3e215f4e57fe394ff27e1634f2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729183 Reviewed-by: Jeremy Bettis --- chip/ish/ipc_heci.c | 112 +++++++++++++++++++++++++--------------------------- 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index 9553e195c4..84dbba9866 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -34,8 +34,8 @@ #include "hwtimer.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) /* * comminucation protocol is defined in Linux Documentation @@ -44,57 +44,55 @@ /* MNG commands */ /* The ipc_mng_task manages IPC link. It should be the highest priority */ -#define MNG_RX_CMPL_ENABLE 0 -#define MNG_RX_CMPL_DISABLE 1 -#define MNG_RX_CMPL_INDICATION 2 -#define MNG_RESET_NOTIFY 3 -#define MNG_RESET_NOTIFY_ACK 4 -#define MNG_SYNC_FW_CLOCK 5 -#define MNG_ILLEGAL_CMD 0xFF +#define MNG_RX_CMPL_ENABLE 0 +#define MNG_RX_CMPL_DISABLE 1 +#define MNG_RX_CMPL_INDICATION 2 +#define MNG_RESET_NOTIFY 3 +#define MNG_RESET_NOTIFY_ACK 4 +#define MNG_SYNC_FW_CLOCK 5 +#define MNG_ILLEGAL_CMD 0xFF /* Doorbell */ -#define IPC_DB_MSG_LENGTH_FIELD 0x3FF -#define IPC_DB_MSG_LENGTH_SHIFT 0 +#define IPC_DB_MSG_LENGTH_FIELD 0x3FF +#define IPC_DB_MSG_LENGTH_SHIFT 0 #define IPC_DB_MSG_LENGTH_MASK \ - (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT) + (IPC_DB_MSG_LENGTH_FIELD << IPC_DB_MSG_LENGTH_SHIFT) -#define IPC_DB_PROTOCOL_FIELD 0x0F -#define IPC_DB_PROTOCOL_SHIFT 10 +#define IPC_DB_PROTOCOL_FIELD 0x0F +#define IPC_DB_PROTOCOL_SHIFT 10 #define IPC_DB_PROTOCOL_MASK (IPC_DB_PROTOCOL_FIELD << IPC_DB_PROTOCOL_SHIFT) -#define IPC_DB_CMD_FIELD 0x0F -#define IPC_DB_CMD_SHIFT 16 -#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) +#define IPC_DB_CMD_FIELD 0x0F +#define IPC_DB_CMD_SHIFT 16 +#define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) -#define IPC_DB_BUSY_SHIFT 31 -#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) +#define IPC_DB_BUSY_SHIFT 31 +#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) #define IPC_DB_MSG_LENGTH(drbl) \ - (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) + (((drbl)&IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) #define IPC_DB_PROTOCOL(drbl) \ - (((drbl) & IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT) -#define IPC_DB_CMD(drbl) \ - (((drbl) & IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT) -#define IPC_DB_BUSY(drbl) (!!((drbl) & IPC_DB_BUSY_MASK)) + (((drbl)&IPC_DB_PROTOCOL_MASK) >> IPC_DB_PROTOCOL_SHIFT) +#define IPC_DB_CMD(drbl) (((drbl)&IPC_DB_CMD_MASK) >> IPC_DB_CMD_SHIFT) +#define IPC_DB_BUSY(drbl) (!!((drbl)&IPC_DB_BUSY_MASK)) -#define IPC_BUILD_DB(length, proto, cmd, busy) \ +#define IPC_BUILD_DB(length, proto, cmd, busy) \ (((busy) << IPC_DB_BUSY_SHIFT) | ((cmd) << IPC_DB_CMD_SHIFT) | \ - ((proto) << IPC_DB_PROTOCOL_SHIFT) | \ - ((length) << IPC_DB_MSG_LENGTH_SHIFT)) + ((proto) << IPC_DB_PROTOCOL_SHIFT) | \ + ((length) << IPC_DB_MSG_LENGTH_SHIFT)) #define IPC_BUILD_MNG_DB(cmd, length) \ IPC_BUILD_DB(length, IPC_PROTOCOL_MNG, cmd, 1) -#define IPC_BUILD_HECI_DB(length) \ - IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1) +#define IPC_BUILD_HECI_DB(length) IPC_BUILD_DB(length, IPC_PROTOCOL_HECI, 0, 1) -#define IPC_MSG_MAX_SIZE 0x80 -#define IPC_HOST_MSG_QUEUE_SIZE 8 -#define IPC_PMC_MSG_QUEUE_SIZE 2 +#define IPC_MSG_MAX_SIZE 0x80 +#define IPC_HOST_MSG_QUEUE_SIZE 8 +#define IPC_PMC_MSG_QUEUE_SIZE 2 -#define IPC_HANDLE_PEER_ID_SHIFT 4 -#define IPC_HANDLE_PROTOCOL_SHIFT 0 -#define IPC_HANDLE_PROTOCOL_MASK 0x0F +#define IPC_HANDLE_PEER_ID_SHIFT 4 +#define IPC_HANDLE_PROTOCOL_SHIFT 0 +#define IPC_HANDLE_PROTOCOL_MASK 0x0F #define IPC_BUILD_HANDLE(peer_id, protocol) \ ((ipc_handle_t)(((peer_id) << IPC_HANDLE_PEER_ID_SHIFT) | (protocol))) #define IPC_BUILD_MNG_HANDLE(peer_id) \ @@ -103,10 +101,10 @@ #define IPC_HANDLE_PEER_ID(handle) \ ((uint32_t)(handle) >> IPC_HANDLE_PEER_ID_SHIFT) #define IPC_HANDLE_PROTOCOL(handle) \ - ((uint32_t)(handle) & IPC_HANDLE_PROTOCOL_MASK) -#define IPC_IS_VALID_HANDLE(handle) \ + ((uint32_t)(handle)&IPC_HANDLE_PROTOCOL_MASK) +#define IPC_IS_VALID_HANDLE(handle) \ (IPC_HANDLE_PEER_ID(handle) < IPC_PEERS_COUNT && \ - IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT) + IPC_HANDLE_PROTOCOL(handle) < IPC_PROTOCOL_COUNT) struct ipc_msg { uint32_t drbl; @@ -191,21 +189,20 @@ static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) IPC_PIMR &= ~ctx->pimr_2ish_bit; } -static inline void ipc_enable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) +static inline void +ipc_enable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx) { IPC_PIMR |= ctx->pimr_2host_clearing_bit; } -static inline void ipc_disable_pimr_clearing_interrupt( - const struct ipc_if_ctx *ctx) +static inline void +ipc_disable_pimr_clearing_interrupt(const struct ipc_if_ctx *ctx) { IPC_PIMR &= ~ctx->pimr_2host_clearing_bit; } static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx, - uint32_t drbl, - const uint8_t *payload, + uint32_t drbl, const uint8_t *payload, size_t payload_size) { memcpy((void *)(ctx->out_msg_reg), payload, payload_size); @@ -280,7 +277,7 @@ static int ipc_send_reset_notify(const ipc_handle_t handle) static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx) { - struct ipc_msg msg = {0}; + struct ipc_msg msg = { 0 }; msg.drbl = IPC_BUILD_MNG_DB(MNG_RX_CMPL_INDICATION, 0); ipc_write_raw(ctx, msg.drbl, msg.payload, IPC_DB_MSG_LENGTH(msg.drbl)); @@ -289,8 +286,8 @@ static int ipc_send_cmpl_indication(struct ipc_if_ctx *ctx) } static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, - const uint32_t protocol, - uint8_t *buf, const size_t buf_size) + const uint32_t protocol, uint8_t *buf, + const size_t buf_size) { int len = 0, payload_size; uint8_t *src = NULL, *dest = NULL; @@ -325,9 +322,8 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, } if (IS_ENABLED(IPC_HECI_DEBUG)) - CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", - protocol, drbl_val, - IPC_DB_MSG_LENGTH(drbl_val)); + CPRINTF("ipc p=%d, db=0x%0x, payload_size=%d\n", protocol, + drbl_val, IPC_DB_MSG_LENGTH(drbl_val)); switch (protocol) { case IPC_PROTOCOL_HECI: @@ -340,7 +336,7 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, msg->drbl = drbl_val; dest = msg->payload; break; - default : + default: break; } @@ -544,13 +540,11 @@ int ipc_write_timestamp(const ipc_handle_t handle, const void *buf, } ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, - const enum ipc_protocol protocol, - const uint32_t event) + const enum ipc_protocol protocol, const uint32_t event) { struct ipc_if_ctx *ctx; - if (protocol >= IPC_PROTOCOL_COUNT || - peer_id >= IPC_PEERS_COUNT) + if (protocol >= IPC_PROTOCOL_COUNT || peer_id >= IPC_PEERS_COUNT) return IPC_INVALID_HANDLE; ctx = ipc_get_if_ctx(peer_id); @@ -564,9 +558,9 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id, ctx->msg_events[protocol].enabled = 1; ctx->msg_events[protocol].event = event; - /* For HECI protocol, set HECI UP status when IPC link is ready */ - if (peer_id == IPC_PEER_ID_HOST && - protocol == IPC_PROTOCOL_HECI && ish_fwst_is_ilup_set()) + /* For HECI protocol, set HECI UP status when IPC link is ready */ + if (peer_id == IPC_PEER_ID_HOST && protocol == IPC_PROTOCOL_HECI && + ish_fwst_is_ilup_set()) ish_fwst_set_hup(); if (ctx->initialized == 0) { @@ -686,7 +680,7 @@ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, } /* event flag for MNG msg */ -#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0) +#define EVENT_FLAG_BIT_MNG_MSG TASK_EVENT_CUSTOM_BIT(0) /* * This task handles MNG messages -- cgit v1.2.1 From 7234cf02172ab9363d3a431cacd881e4274d9884 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:13 -0600 Subject: board/kukui_scp/vdec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I43d7ea0e534144b2cb41b72730846c086d59c891 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728598 Reviewed-by: Jeremy Bettis --- board/kukui_scp/vdec.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/board/kukui_scp/vdec.c b/board/kukui_scp/vdec.c index eb4f1f8fa1..13620e0211 100644 --- a/board/kukui_scp/vdec.c +++ b/board/kukui_scp/vdec.c @@ -20,19 +20,23 @@ static struct consumer const event_vdec_consumer; static void event_vdec_written(struct consumer const *consumer, size_t count); -static struct queue const event_vdec_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_consumer); +static struct queue const event_vdec_queue = + QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer); static struct consumer const event_vdec_consumer = { .queue = &event_vdec_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_vdec_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT8183 -void vdec_h264_service_init(void) {} -void vdec_h264_msg_handler(void *data) {} +void vdec_h264_service_init(void) +{ +} +void vdec_h264_msg_handler(void *data) +{ +} #endif static vdec_msg_handler mtk_vdec_msg_handle[VDEC_MAX]; -- cgit v1.2.1 From 1e4f298526a6aa6223a17b61ae341b81c5e64b08 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:19 -0600 Subject: zephyr/projects/intelrvp/include/intelrvp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib67a0b36848a812cf8bfc5e8d377cfbfbf6b1cd5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730775 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/include/intelrvp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/intelrvp/include/intelrvp.h b/zephyr/projects/intelrvp/include/intelrvp.h index ad6d12ae6f..4f25ae336d 100644 --- a/zephyr/projects/intelrvp/include/intelrvp.h +++ b/zephyr/projects/intelrvp/include/intelrvp.h @@ -10,7 +10,7 @@ #include "stdbool.h" /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 #define DC_JACK_MAX_VOLTAGE_MV 19000 -- cgit v1.2.1 From e54ef47d8a8f00b97e358e20257d4eb6555c6deb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:09 -0600 Subject: core/cortex-m0/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52d9c4fc140c48cd203b2bc34a4fa7fed121f8a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729831 Reviewed-by: Jeremy Bettis --- core/cortex-m0/irq_handler.h | 39 ++++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/core/cortex-m0/irq_handler.h b/core/cortex-m0/irq_handler.h index 302befe7a6..29118800e3 100644 --- a/core/cortex-m0/irq_handler.h +++ b/core/cortex-m0/irq_handler.h @@ -20,25 +20,26 @@ */ #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority) #ifdef CONFIG_TASK_PROFILING -#define DECLARE_IRQ_(irq, routine, priority) \ - static void routine(void); \ - void IRQ_HANDLER(irq)(void) \ - { \ - void *ret = __builtin_return_address(0); \ - task_start_irq_handler(ret); \ - routine(); \ - task_end_irq_handler(ret); \ - } \ - const struct irq_priority __keep IRQ_PRIORITY(irq) \ - __attribute__((section(".rodata.irqprio"))) \ - = {irq, priority} +#define DECLARE_IRQ_(irq, routine, priority) \ + static void routine(void); \ + void IRQ_HANDLER(irq)(void) \ + { \ + void *ret = __builtin_return_address(0); \ + task_start_irq_handler(ret); \ + routine(); \ + task_end_irq_handler(ret); \ + } \ + const struct irq_priority __keep IRQ_PRIORITY(irq) \ + __attribute__((section(".rodata.irqprio"))) = { irq, \ + priority } #else /* CONFIG_TASK_PROFILING */ /* No Profiling : connect directly the IRQ vector */ -#define DECLARE_IRQ_(irq, routine, priority) \ - static void __keep routine(void); \ - void IRQ_HANDLER(irq)(void) __attribute__((alias(STRINGIFY(routine))));\ - const struct irq_priority __keep IRQ_PRIORITY(irq) \ - __attribute__((section(".rodata.irqprio"))) \ - = {irq, priority} +#define DECLARE_IRQ_(irq, routine, priority) \ + static void __keep routine(void); \ + void IRQ_HANDLER(irq)(void) \ + __attribute__((alias(STRINGIFY(routine)))); \ + const struct irq_priority __keep IRQ_PRIORITY(irq) \ + __attribute__((section(".rodata.irqprio"))) = { irq, \ + priority } #endif /* CONFIG_TASK_PROFILING */ -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From b2858bd888126c940a9b33acb168e8981b422050 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:19 -0600 Subject: extra/i2c_pseudo/i2c-pseudo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I350401a185e27bc976cfbf4d3c1d8e53cdc55927 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730179 Reviewed-by: Jeremy Bettis --- extra/i2c_pseudo/i2c-pseudo.c | 490 +++++++++++++++++++++++------------------- 1 file changed, 263 insertions(+), 227 deletions(-) diff --git a/extra/i2c_pseudo/i2c-pseudo.c b/extra/i2c_pseudo/i2c-pseudo.c index 325d140663..7cb2904322 100644 --- a/extra/i2c_pseudo/i2c-pseudo.c +++ b/extra/i2c_pseudo/i2c-pseudo.c @@ -30,47 +30,47 @@ #include /* Minimum i2cp_limit module parameter value. */ -#define I2CP_ADAPTERS_MIN 0 +#define I2CP_ADAPTERS_MIN 0 /* Maximum i2cp_limit module parameter value. */ -#define I2CP_ADAPTERS_MAX 256 +#define I2CP_ADAPTERS_MAX 256 /* Default i2cp_limit module parameter value. */ -#define I2CP_DEFAULT_LIMIT 8 +#define I2CP_DEFAULT_LIMIT 8 /* Value for alloc_chrdev_region() baseminor arg. */ -#define I2CP_CDEV_BASEMINOR 0 -#define I2CP_TIMEOUT_MS_MIN 0 -#define I2CP_TIMEOUT_MS_MAX (60 * MSEC_PER_SEC) -#define I2CP_DEFAULT_TIMEOUT_MS (3 * MSEC_PER_SEC) +#define I2CP_CDEV_BASEMINOR 0 +#define I2CP_TIMEOUT_MS_MIN 0 +#define I2CP_TIMEOUT_MS_MAX (60 * MSEC_PER_SEC) +#define I2CP_DEFAULT_TIMEOUT_MS (3 * MSEC_PER_SEC) /* Used in struct device.kobj.name field. */ -#define I2CP_DEVICE_NAME "i2c-pseudo-controller" +#define I2CP_DEVICE_NAME "i2c-pseudo-controller" /* Value for alloc_chrdev_region() name arg. */ -#define I2CP_CHRDEV_NAME "i2c_pseudo" +#define I2CP_CHRDEV_NAME "i2c_pseudo" /* Value for class_create() name arg. */ -#define I2CP_CLASS_NAME "i2c-pseudo" +#define I2CP_CLASS_NAME "i2c-pseudo" /* Value for alloc_chrdev_region() count arg. Should always be 1. */ -#define I2CP_CDEV_COUNT 1 - -#define I2CP_ADAP_START_CMD "ADAPTER_START" -#define I2CP_ADAP_SHUTDOWN_CMD "ADAPTER_SHUTDOWN" -#define I2CP_GET_NUMBER_CMD "GET_ADAPTER_NUM" -#define I2CP_NUMBER_REPLY_CMD "I2C_ADAPTER_NUM" -#define I2CP_GET_PSEUDO_ID_CMD "GET_PSEUDO_ID" -#define I2CP_PSEUDO_ID_REPLY_CMD "I2C_PSEUDO_ID" -#define I2CP_SET_NAME_SUFFIX_CMD "SET_ADAPTER_NAME_SUFFIX" -#define I2CP_SET_TIMEOUT_CMD "SET_ADAPTER_TIMEOUT_MS" -#define I2CP_BEGIN_MXFER_REQ_CMD "I2C_BEGIN_XFER" -#define I2CP_COMMIT_MXFER_REQ_CMD "I2C_COMMIT_XFER" -#define I2CP_MXFER_REQ_CMD "I2C_XFER_REQ" -#define I2CP_MXFER_REPLY_CMD "I2C_XFER_REPLY" +#define I2CP_CDEV_COUNT 1 + +#define I2CP_ADAP_START_CMD "ADAPTER_START" +#define I2CP_ADAP_SHUTDOWN_CMD "ADAPTER_SHUTDOWN" +#define I2CP_GET_NUMBER_CMD "GET_ADAPTER_NUM" +#define I2CP_NUMBER_REPLY_CMD "I2C_ADAPTER_NUM" +#define I2CP_GET_PSEUDO_ID_CMD "GET_PSEUDO_ID" +#define I2CP_PSEUDO_ID_REPLY_CMD "I2C_PSEUDO_ID" +#define I2CP_SET_NAME_SUFFIX_CMD "SET_ADAPTER_NAME_SUFFIX" +#define I2CP_SET_TIMEOUT_CMD "SET_ADAPTER_TIMEOUT_MS" +#define I2CP_BEGIN_MXFER_REQ_CMD "I2C_BEGIN_XFER" +#define I2CP_COMMIT_MXFER_REQ_CMD "I2C_COMMIT_XFER" +#define I2CP_MXFER_REQ_CMD "I2C_XFER_REQ" +#define I2CP_MXFER_REPLY_CMD "I2C_XFER_REPLY" /* Maximum size of a controller command. */ -#define I2CP_CTRLR_CMD_LIMIT 255 +#define I2CP_CTRLR_CMD_LIMIT 255 /* Maximum number of controller read responses to allow enqueued at once. */ -#define I2CP_CTRLR_RSP_QUEUE_LIMIT 256 +#define I2CP_CTRLR_RSP_QUEUE_LIMIT 256 /* The maximum size of a single controller read response. */ -#define I2CP_MAX_MSG_BUF_SIZE 16384 +#define I2CP_MAX_MSG_BUF_SIZE 16384 /* Maximum size of a controller read or write. */ -#define I2CP_RW_SIZE_LIMIT 1048576 +#define I2CP_RW_SIZE_LIMIT 1048576 /* * Marks the end of a controller command or read response. @@ -85,11 +85,11 @@ * because of an assertion that the copy size (1) must match the size of the * string literal (2 with its trailing null). */ -static const char i2cp_ctrlr_end_char = '\n'; +static const char i2cp_ctrlr_end_char = '\n'; /* Separator between I2C message header fields in the controller bytestream. */ -static const char i2cp_ctrlr_header_sep_char = ' '; +static const char i2cp_ctrlr_header_sep_char = ' '; /* Separator between I2C message data bytes in the controller bytestream. */ -static const char i2cp_ctrlr_data_sep_char = ':'; +static const char i2cp_ctrlr_data_sep_char = ':'; /* * This used instead of strcmp(in_str, other_str) because in_str may have null @@ -99,10 +99,10 @@ static const char i2cp_ctrlr_data_sep_char = ':'; #define STRING_NEQ(in_str, in_size, other_str) \ (in_size != strlen(other_str) || memcmp(other_str, in_str, in_size)) -#define STR_HELPER(num) #num -#define STR(num) STR_HELPER(num) +#define STR_HELPER(num) #num +#define STR(num) STR_HELPER(num) -#define CONST_STRLEN(str) (sizeof(str) - 1) +#define CONST_STRLEN(str) (sizeof(str) - 1) /* * The number of pseudo I2C adapters permitted. This default value can be @@ -207,8 +207,8 @@ struct i2cp_cmd { * behavior with duplicate command names is undefined, subject to * change, and subject to become either a build-time or runtime error. */ - char *cmd_string; /* Must be non-NULL. */ - size_t cmd_size; /* Must be non-zero. */ + char *cmd_string; /* Must be non-NULL. */ + size_t cmd_size; /* Must be non-zero. */ /* * This is called once for each I2C pseudo controller to initialize @@ -308,7 +308,7 @@ struct i2cp_cmd { * This callback MUST NOT be NULL. */ int (*header_receiver)(void *data, char *in, size_t in_size, - bool non_blocking); + bool non_blocking); /* * This is called to process write command data, when requested by the * header_receiver() return value. @@ -347,7 +347,7 @@ struct i2cp_cmd { * should be NULL. Otherwise, this callback MUST NOT be NULL. */ int (*data_receiver)(void *data, char *in, size_t in_size, - bool non_blocking); + bool non_blocking); /* * This is called to complete processing of a command, after it has been * received in its entirety. @@ -394,7 +394,7 @@ struct i2cp_cmd { * This callback may be NULL. */ int (*cmd_completer)(void *data, struct i2cp_controller *pdata, - int receive_status, bool non_blocking); + int receive_status, bool non_blocking); }; /* @@ -749,13 +749,13 @@ struct i2cp_rsp_master_xfer { * Always initialize fields below here to zero. They are for internal * use by i2cp_rsp_master_xfer_formatter(). */ - int num_msgs_done; /* type of @num field */ + int num_msgs_done; /* type of @num field */ size_t buf_start_plus_one; }; /* vanprintf - See anprintf() documentation. */ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp, - const char *fmt, va_list ap) + const char *fmt, va_list ap) { int ret; ssize_t buf_size; @@ -790,9 +790,9 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp, *out = buf; return ret; - fail_before_args1: +fail_before_args1: va_end(args1); - fail_after_args1: +fail_after_args1: kfree(buf); if (ret >= 0) ret = -ENOTRECOVERABLE; @@ -833,7 +833,7 @@ static ssize_t vanprintf(char **out, ssize_t max_size, gfp_t gfp, * a bug. */ static ssize_t anprintf(char **out, ssize_t max_size, gfp_t gfp, - const char *fmt, ...) + const char *fmt, ...) { ssize_t ret; va_list args; @@ -905,24 +905,26 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out) * that no bytes were lost in kernel->userspace transmission. */ ret = anprintf(&buf_start, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL, - "%*s%c%u%c%d%c0x%04X%c0x%04X%c%u", - (int)strlen(I2CP_MXFER_REQ_CMD), I2CP_MXFER_REQ_CMD, - i2cp_ctrlr_header_sep_char, mxfer_rsp->id, - i2cp_ctrlr_header_sep_char, mxfer_rsp->num_msgs_done, - i2cp_ctrlr_header_sep_char, i2c_msg->addr, - i2cp_ctrlr_header_sep_char, i2c_msg->flags, - i2cp_ctrlr_header_sep_char, i2c_msg->len); + "%*s%c%u%c%d%c0x%04X%c0x%04X%c%u", + (int)strlen(I2CP_MXFER_REQ_CMD), + I2CP_MXFER_REQ_CMD, i2cp_ctrlr_header_sep_char, + mxfer_rsp->id, i2cp_ctrlr_header_sep_char, + mxfer_rsp->num_msgs_done, + i2cp_ctrlr_header_sep_char, i2c_msg->addr, + i2cp_ctrlr_header_sep_char, i2c_msg->flags, + i2cp_ctrlr_header_sep_char, i2c_msg->len); if (ret > 0) { *out = buf_start; mxfer_rsp->buf_start_plus_one = 1; - /* - * If we have a zero return value, it means the output buffer - * was allocated as size one, containing only a terminating null - * character. This would be a bug given the requested format - * string above. Also, formatter functions must not mutate *out - * when returning zero. So if this matches, free the useless - * buffer and return an error. - */ + /* + * If we have a zero return value, it means the output + * buffer was allocated as size one, containing only a + * terminating null character. This would be a bug + * given the requested format string above. Also, + * formatter functions must not mutate *out when + * returning zero. So if this matches, free the useless + * buffer and return an error. + */ } else if (ret == 0) { ret = -EINVAL; kfree(buf_start); @@ -932,7 +934,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out) byte_start = mxfer_rsp->buf_start_plus_one - 1; byte_limit = min_t(size_t, i2c_msg->len - byte_start, - I2CP_MAX_MSG_BUF_SIZE / 3); + I2CP_MAX_MSG_BUF_SIZE / 3); /* 3 chars per byte == 2 chars for hex + 1 char for separator */ buf_size = byte_limit * 3; @@ -943,34 +945,34 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out) } for (buf_pos = buf_start, i = 0; i < byte_limit; ++i) { - *buf_pos++ = (i || byte_start) ? - i2cp_ctrlr_data_sep_char : i2cp_ctrlr_header_sep_char; - buf_pos = hex_byte_pack_upper( - buf_pos, i2c_msg->buf[byte_start + i]); + *buf_pos++ = (i || byte_start) ? i2cp_ctrlr_data_sep_char : + i2cp_ctrlr_header_sep_char; + buf_pos = hex_byte_pack_upper(buf_pos, + i2c_msg->buf[byte_start + i]); } *out = buf_start; ret = buf_size; mxfer_rsp->buf_start_plus_one += i; - maybe_free: +maybe_free: if (ret <= 0) { if (mxfer_rsp->num_msgs_done >= mxfer_rsp->num) { kfree(mxfer_rsp->msgs); kfree(mxfer_rsp); - /* - * If we are returning an error but have not consumed all of - * mxfer_rsp yet, we must not attempt to output any more I2C - * messages from the same mxfer_rsp. Setting mxfer_rsp->msgs to - * NULL tells the remaining invocations with this mxfer_rsp to - * output nothing. - * - * There can be more invocations with the same mxfer_rsp even - * after returning an error here because - * i2cp_adapter_master_xfer() reuses a single - * struct i2cp_rsp_master_xfer (mxfer_rsp) across multiple - * struct i2cp_rsp (rsp_wrappers), one for each struct i2c_msg - * within the mxfer_rsp. - */ + /* + * If we are returning an error but have not consumed + * all of mxfer_rsp yet, we must not attempt to output + * any more I2C messages from the same mxfer_rsp. + * Setting mxfer_rsp->msgs to NULL tells the remaining + * invocations with this mxfer_rsp to output nothing. + * + * There can be more invocations with the same mxfer_rsp + * even after returning an error here because + * i2cp_adapter_master_xfer() reuses a single + * struct i2cp_rsp_master_xfer (mxfer_rsp) across + * multiple struct i2cp_rsp (rsp_wrappers), one for each + * struct i2c_msg within the mxfer_rsp. + */ } else if (ret < 0) { kfree(mxfer_rsp->msgs); mxfer_rsp->msgs = NULL; @@ -980,7 +982,7 @@ static ssize_t i2cp_rsp_master_xfer_formatter(void *data, char **out) } static ssize_t i2cp_id_show(struct device *dev, struct device_attribute *attr, - char *buf) + char *buf) { int ret; struct i2c_adapter *adap; @@ -1039,9 +1041,10 @@ static void i2cp_cmd_mxfer_reply_data_shutdown(void *data) cmd_data = data; mutex_lock(&cmd_data->reply_queue_lock); - list_for_each(list_ptr, &cmd_data->reply_queue_head) { + list_for_each(list_ptr, &cmd_data->reply_queue_head) + { mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply, - reply_queue_item); + reply_queue_item); mutex_lock(&mxfer_reply->lock); complete_all(&mxfer_reply->data_filled); mutex_unlock(&mxfer_reply->lock); @@ -1059,29 +1062,30 @@ static void i2cp_cmd_mxfer_reply_data_destroyer(void *data) kfree(data); } -static inline bool i2cp_mxfer_reply_is_current( - struct i2cp_cmd_mxfer_reply_data *cmd_data, - struct i2cp_cmd_mxfer_reply *mxfer_reply) +static inline bool +i2cp_mxfer_reply_is_current(struct i2cp_cmd_mxfer_reply_data *cmd_data, + struct i2cp_cmd_mxfer_reply *mxfer_reply) { int i; i = cmd_data->current_msg_idx; - return cmd_data->current_id == mxfer_reply->id && - i >= 0 && i < mxfer_reply->num_msgs && - cmd_data->current_addr == mxfer_reply->msgs[i].addr && - cmd_data->current_flags == mxfer_reply->msgs[i].flags; + return cmd_data->current_id == mxfer_reply->id && i >= 0 && + i < mxfer_reply->num_msgs && + cmd_data->current_addr == mxfer_reply->msgs[i].addr && + cmd_data->current_flags == mxfer_reply->msgs[i].flags; } /* cmd_data->reply_queue_lock must be held. */ -static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current( - struct i2cp_cmd_mxfer_reply_data *cmd_data) +static inline struct i2cp_cmd_mxfer_reply * +i2cp_mxfer_reply_find_current(struct i2cp_cmd_mxfer_reply_data *cmd_data) { struct list_head *list_ptr; struct i2cp_cmd_mxfer_reply *mxfer_reply; - list_for_each(list_ptr, &cmd_data->reply_queue_head) { + list_for_each(list_ptr, &cmd_data->reply_queue_head) + { mxfer_reply = list_entry(list_ptr, struct i2cp_cmd_mxfer_reply, - reply_queue_item); + reply_queue_item); if (i2cp_mxfer_reply_is_current(cmd_data, mxfer_reply)) return mxfer_reply; } @@ -1089,17 +1093,18 @@ static inline struct i2cp_cmd_mxfer_reply *i2cp_mxfer_reply_find_current( } /* cmd_data->reply_queue_lock must NOT already be held. */ -static inline void i2cp_mxfer_reply_update_current( - struct i2cp_cmd_mxfer_reply_data *cmd_data) +static inline void +i2cp_mxfer_reply_update_current(struct i2cp_cmd_mxfer_reply_data *cmd_data) { mutex_lock(&cmd_data->reply_queue_lock); - cmd_data->reply_queue_current_item = i2cp_mxfer_reply_find_current( - cmd_data); + cmd_data->reply_queue_current_item = + i2cp_mxfer_reply_find_current(cmd_data); mutex_unlock(&cmd_data->reply_queue_lock); } static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { int ret, reply_errno = 0; struct i2cp_cmd_mxfer_reply_data *cmd_data; @@ -1218,10 +1223,10 @@ static int i2cp_cmd_mxfer_reply_header_receiver(void *data, char *in, } static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, bool non_blocking) { int ret; - char u8_hex[3] = {0}; + char u8_hex[3] = { 0 }; struct i2cp_cmd_mxfer_reply_data *cmd_data; struct i2cp_cmd_mxfer_reply *mxfer_reply; struct i2c_msg *i2c_msg; @@ -1333,7 +1338,7 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in, * I2C_M_DMA_SAFE bit? Do we ever need to use copy_to_user()? */ ret = kstrtou8(u8_hex, 16, - &i2c_msg->buf[cmd_data->current_buf_idx]); + &i2c_msg->buf[cmd_data->current_buf_idx]); if (ret < 0) goto unlock; if (i2c_msg->flags & I2C_M_RECV_LEN) @@ -1346,13 +1351,15 @@ static int i2cp_cmd_mxfer_reply_data_receiver(void *data, char *in, /* Quietly ignore any bytes beyond the buffer size. */ ret = 0; - unlock: +unlock: mutex_unlock(&mxfer_reply->lock); return ret; } static int i2cp_cmd_mxfer_reply_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { int ret; struct i2cp_cmd_mxfer_reply_data *cmd_data; @@ -1399,7 +1406,7 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data, mutex_unlock(&mxfer_reply->lock); ret = 0; - reset_cmd_data: +reset_cmd_data: cmd_data->state = I2CP_CMD_MXFER_REPLY_STATE_CMD_NEXT; cmd_data->current_id = 0; cmd_data->current_addr = 0; @@ -1410,7 +1417,8 @@ static int i2cp_cmd_mxfer_reply_cmd_completer(void *data, } static int i2cp_cmd_adap_start_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * No more header fields or data are expected. This directs any further @@ -1421,7 +1429,7 @@ static int i2cp_cmd_adap_start_header_receiver(void *data, char *in, } static int i2cp_cmd_adap_start_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, bool non_blocking) { /* * Reaching here means the controller wrote extra data in the command @@ -1432,7 +1440,9 @@ static int i2cp_cmd_adap_start_data_receiver(void *data, char *in, } static int i2cp_cmd_adap_start_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { int ret; @@ -1466,13 +1476,14 @@ static int i2cp_cmd_adap_start_cmd_completer(void *data, ret = 0; - unlock: +unlock: mutex_unlock(&pdata->startstop_lock); return ret; } static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * No more header fields or data are expected. This directs any further @@ -1483,7 +1494,8 @@ static int i2cp_cmd_adap_shutdown_header_receiver(void *data, char *in, } static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * Reaching here means the controller wrote extra data in the command @@ -1494,7 +1506,9 @@ static int i2cp_cmd_adap_shutdown_data_receiver(void *data, char *in, } static int i2cp_cmd_adap_shutdown_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { /* Refuse to shutdown if there were errors processing this command. */ if (receive_status) @@ -1512,7 +1526,8 @@ static int i2cp_cmd_adap_shutdown_cmd_completer(void *data, } static int i2cp_cmd_get_number_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * No more header fields or data are expected. This directs any further @@ -1523,7 +1538,7 @@ static int i2cp_cmd_get_number_header_receiver(void *data, char *in, } static int i2cp_cmd_get_number_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, bool non_blocking) { /* * Reaching here means the controller wrote extra data in the command @@ -1534,7 +1549,9 @@ static int i2cp_cmd_get_number_data_receiver(void *data, char *in, } static int i2cp_cmd_get_number_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { ssize_t ret; int i2c_adap_nr; @@ -1572,9 +1589,9 @@ static int i2cp_cmd_get_number_cmd_completer(void *data, } ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL, - "%*s%c%d", - (int)strlen(I2CP_NUMBER_REPLY_CMD), I2CP_NUMBER_REPLY_CMD, - i2cp_ctrlr_header_sep_char, i2c_adap_nr); + "%*s%c%d", (int)strlen(I2CP_NUMBER_REPLY_CMD), + I2CP_NUMBER_REPLY_CMD, i2cp_ctrlr_header_sep_char, + i2c_adap_nr); if (ret < 0) { goto fail_after_rsp_buf_alloc; } else if (ret == 0) { @@ -1600,17 +1617,18 @@ static int i2cp_cmd_get_number_cmd_completer(void *data, mutex_unlock(&pdata->read_rsp_queue_lock); return 0; - fail_after_buf_alloc: +fail_after_buf_alloc: kfree(rsp_buf->buf); - fail_after_rsp_buf_alloc: +fail_after_rsp_buf_alloc: kfree(rsp_buf); - fail_after_rsp_wrapper_alloc: +fail_after_rsp_wrapper_alloc: kfree(rsp_wrapper); return ret; } static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * No more header fields or data are expected. This directs any further @@ -1621,7 +1639,8 @@ static int i2cp_cmd_get_pseudo_id_header_receiver(void *data, char *in, } static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { /* * Reaching here means the controller wrote extra data in the command @@ -1632,7 +1651,9 @@ static int i2cp_cmd_get_pseudo_id_data_receiver(void *data, char *in, } static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { ssize_t ret; struct i2cp_rsp_buffer *rsp_buf; @@ -1653,9 +1674,9 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data, } ret = anprintf(&rsp_buf->buf, I2CP_MAX_MSG_BUF_SIZE, GFP_KERNEL, - "%*s%c%u", - (int)strlen(I2CP_PSEUDO_ID_REPLY_CMD), I2CP_PSEUDO_ID_REPLY_CMD, - i2cp_ctrlr_header_sep_char, pdata->id); + "%*s%c%u", (int)strlen(I2CP_PSEUDO_ID_REPLY_CMD), + I2CP_PSEUDO_ID_REPLY_CMD, i2cp_ctrlr_header_sep_char, + pdata->id); if (ret < 0) { goto fail_after_rsp_buf_alloc; } else if (ret == 0) { @@ -1681,11 +1702,11 @@ static int i2cp_cmd_get_pseudo_id_cmd_completer(void *data, mutex_unlock(&pdata->read_rsp_queue_lock); return 0; - fail_after_buf_alloc: +fail_after_buf_alloc: kfree(rsp_buf->buf); - fail_after_rsp_buf_alloc: +fail_after_rsp_buf_alloc: kfree(rsp_buf); - fail_after_rsp_wrapper_alloc: +fail_after_rsp_wrapper_alloc: kfree(rsp_wrapper); return ret; } @@ -1707,13 +1728,15 @@ static void i2cp_cmd_set_name_suffix_data_destroyer(void *data) } static int i2cp_cmd_set_name_suffix_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { return 1; } static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { size_t remaining; struct i2cp_cmd_set_name_suffix_data *cmd_data; @@ -1730,7 +1753,9 @@ static int i2cp_cmd_set_name_suffix_data_receiver(void *data, char *in, } static int i2cp_cmd_set_name_suffix_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { int ret; struct i2cp_cmd_set_name_suffix_data *cmd_data; @@ -1753,14 +1778,14 @@ static int i2cp_cmd_set_name_suffix_cmd_completer(void *data, cmd_data = data; ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name), - "I2C pseudo ID %u %*s", pdata->id, - (int)cmd_data->name_suffix_len, cmd_data->name_suffix); + "I2C pseudo ID %u %*s", pdata->id, + (int)cmd_data->name_suffix_len, cmd_data->name_suffix); if (ret < 0) goto unlock; ret = 0; - unlock: +unlock: mutex_unlock(&pdata->startstop_lock); return ret; } @@ -1782,7 +1807,8 @@ static void i2cp_cmd_set_timeout_data_destroyer(void *data) } static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, + bool non_blocking) { int ret; struct i2cp_cmd_set_timeout_data *cmd_data; @@ -1802,7 +1828,7 @@ static int i2cp_cmd_set_timeout_header_receiver(void *data, char *in, } static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in, - size_t in_size, bool non_blocking) + size_t in_size, bool non_blocking) { /* * Reaching here means the controller wrote extra data in the command @@ -1812,7 +1838,9 @@ static int i2cp_cmd_set_timeout_data_receiver(void *data, char *in, } static int i2cp_cmd_set_timeout_cmd_completer(void *data, - struct i2cp_controller *pdata, int receive_status, bool non_blocking) + struct i2cp_controller *pdata, + int receive_status, + bool non_blocking) { int ret; struct i2cp_cmd_set_timeout_data *cmd_data; @@ -1835,7 +1863,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data, cmd_data = data; if (cmd_data->timeout_ms < I2CP_TIMEOUT_MS_MIN || - cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) { + cmd_data->timeout_ms > I2CP_TIMEOUT_MS_MAX) { ret = -ERANGE; goto unlock; } @@ -1843,7 +1871,7 @@ static int i2cp_cmd_set_timeout_cmd_completer(void *data, pdata->i2c_adapter.timeout = msecs_to_jiffies(cmd_data->timeout_ms); ret = 0; - unlock: +unlock: mutex_unlock(&pdata->startstop_lock); return ret; } @@ -1914,11 +1942,12 @@ static const struct i2cp_cmd i2cp_cmds[] = { static inline bool i2cp_poll_in(struct i2cp_controller *pdata) { return pdata->rsp_invalidated || pdata->rsp_buf_remaining != 0 || - !list_empty(&pdata->read_rsp_queue_head); + !list_empty(&pdata->read_rsp_queue_head); } static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper, - struct i2cp_rsp_buffer *rsp_buf, char *contents, size_t size) + struct i2cp_rsp_buffer *rsp_buf, + char *contents, size_t size) { rsp_buf->buf = kmemdup(contents, size, GFP_KERNEL); if (!rsp_buf->buf) @@ -1929,19 +1958,19 @@ static inline int i2cp_fill_rsp_buf(struct i2cp_rsp *rsp_wrapper, return 0; } -#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal)\ - i2cp_fill_rsp_buf(\ - rsp_wrapper, rsp_buf, str_literal, strlen(str_literal)) +#define I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrapper, rsp_buf, str_literal) \ + i2cp_fill_rsp_buf(rsp_wrapper, rsp_buf, str_literal, \ + strlen(str_literal)) static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) + struct i2c_msg *msgs, int num) { int i, ret = 0; long wait_ret; size_t wrappers_length, wrapper_idx = 0, rsp_bufs_idx = 0; struct i2cp_controller *pdata; struct i2cp_rsp **rsp_wrappers; - struct i2cp_rsp_buffer *rsp_bufs[2] = {0}; + struct i2cp_rsp_buffer *rsp_bufs[2] = { 0 }; struct i2cp_rsp_master_xfer *mxfer_rsp; struct i2cp_cmd_mxfer_reply_data *cmd_data; struct i2cp_cmd_mxfer_reply *mxfer_reply; @@ -1966,8 +1995,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, } wrappers_length = (size_t)num + ARRAY_SIZE(rsp_bufs); - rsp_wrappers = kcalloc(wrappers_length, sizeof(*rsp_wrappers), - GFP_KERNEL); + rsp_wrappers = + kcalloc(wrappers_length, sizeof(*rsp_wrappers), GFP_KERNEL); if (!rsp_wrappers) return -ENOMEM; @@ -1981,15 +2010,15 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, init_completion(&mxfer_reply->data_filled); mutex_init(&mxfer_reply->lock); - mxfer_reply->msgs = kcalloc(num, sizeof(*mxfer_reply->msgs), - GFP_KERNEL); + mxfer_reply->msgs = + kcalloc(num, sizeof(*mxfer_reply->msgs), GFP_KERNEL); if (!mxfer_reply->msgs) { ret = -ENOMEM; goto return_after_mxfer_reply_alloc; } - mxfer_reply->completed = kcalloc(num, sizeof(*mxfer_reply->completed), - GFP_KERNEL); + mxfer_reply->completed = + kcalloc(num, sizeof(*mxfer_reply->completed), GFP_KERNEL); if (!mxfer_reply->completed) { ret = -ENOMEM; goto return_after_reply_msgs_alloc; @@ -2034,8 +2063,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, if (msgs[i].flags & I2C_M_RD) continue; /* Copy the data, not the address. */ - mxfer_rsp->msgs[i].buf = kmemdup(msgs[i].buf, msgs[i].len, - GFP_KERNEL); + mxfer_rsp->msgs[i].buf = + kmemdup(msgs[i].buf, msgs[i].len, GFP_KERNEL); if (!mxfer_rsp->msgs[i].buf) { ret = -ENOMEM; goto fail_after_rsp_msgs_alloc; @@ -2051,7 +2080,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, } ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++], - rsp_bufs[rsp_bufs_idx++], I2CP_BEGIN_MXFER_REQ_CMD); + rsp_bufs[rsp_bufs_idx++], + I2CP_BEGIN_MXFER_REQ_CMD); if (ret < 0) goto fail_after_individual_rsp_wrappers_alloc; @@ -2062,7 +2092,8 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, } ret = I2CP_FILL_RSP_BUF_WITH_LITERAL(rsp_wrappers[wrapper_idx++], - rsp_bufs[rsp_bufs_idx++], I2CP_COMMIT_MXFER_REQ_CMD); + rsp_bufs[rsp_bufs_idx++], + I2CP_COMMIT_MXFER_REQ_CMD); if (ret < 0) goto fail_after_individual_rsp_wrappers_alloc; @@ -2082,12 +2113,12 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, mxfer_reply->id = mxfer_rsp->id; list_add_tail(&mxfer_reply->reply_queue_item, - &cmd_data->reply_queue_head); + &cmd_data->reply_queue_head); ++cmd_data->reply_queue_length; for (i = 0; i < wrappers_length; ++i) { list_add_tail(&rsp_wrappers[i]->queue, - &pdata->read_rsp_queue_head); + &pdata->read_rsp_queue_head); complete(&pdata->read_rsp_queued); } pdata->read_rsp_queue_length += wrappers_length; @@ -2132,31 +2163,31 @@ static int i2cp_adapter_master_xfer(struct i2c_adapter *adap, mutex_unlock(&cmd_data->reply_queue_lock); goto return_after_reply_msgs_alloc; - fail_with_reply_queue_lock: +fail_with_reply_queue_lock: mutex_unlock(&cmd_data->reply_queue_lock); - fail_with_read_rsp_queue_lock: +fail_with_read_rsp_queue_lock: mutex_unlock(&pdata->read_rsp_queue_lock); - fail_after_individual_rsp_wrappers_alloc: +fail_after_individual_rsp_wrappers_alloc: for (i = 0; i < wrappers_length; ++i) kfree(rsp_wrappers[i]); - fail_after_rsp_msgs_alloc: +fail_after_rsp_msgs_alloc: for (i = 0; i < num; ++i) kfree(mxfer_rsp->msgs[i].buf); kfree(mxfer_rsp->msgs); - fail_after_mxfer_rsp_alloc: +fail_after_mxfer_rsp_alloc: kfree(mxfer_rsp); - fail_after_individual_rsp_bufs_alloc: +fail_after_individual_rsp_bufs_alloc: for (i = 0; i < ARRAY_SIZE(rsp_bufs); ++i) { kfree(rsp_bufs[i]->buf); kfree(rsp_bufs[i]); } - return_after_reply_completed_alloc: +return_after_reply_completed_alloc: kfree(mxfer_reply->completed); - return_after_reply_msgs_alloc: +return_after_reply_msgs_alloc: kfree(mxfer_reply->msgs); - return_after_mxfer_reply_alloc: +return_after_mxfer_reply_alloc: kfree(mxfer_reply); - return_after_rsp_wrappers_ptrs_alloc: +return_after_rsp_wrappers_ptrs_alloc: kfree(rsp_wrappers); return ret; } @@ -2183,9 +2214,8 @@ static const struct i2c_algorithm i2cp_algorithm = { /* this_pseudo->counters.lock must _not_ be held when calling this. */ static void i2cp_remove_from_counters(struct i2cp_controller *pdata, - struct i2cp_device *this_pseudo) + struct i2cp_device *this_pseudo) { - mutex_lock(&this_pseudo->counters.lock); this_pseudo->counters.all_controllers[pdata->index] = NULL; --this_pseudo->counters.count; @@ -2290,7 +2320,7 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep) pdata->i2c_adapter.timeout = msecs_to_jiffies(i2cp_default_timeout_ms); pdata->i2c_adapter.dev.parent = &this_pseudo->device; ret = snprintf(pdata->i2c_adapter.name, sizeof(pdata->i2c_adapter.name), - "I2C pseudo ID %u", pdata->id); + "I2C pseudo ID %u", pdata->id); if (ret < 0) goto fail_after_counters_update; @@ -2298,9 +2328,9 @@ static int i2cp_cdev_open(struct inode *inodep, struct file *filep) filep->private_data = pdata; return 0; - fail_after_counters_update: +fail_after_counters_update: i2cp_remove_from_counters(pdata, this_pseudo); - fail_after_cmd_data_created: +fail_after_cmd_data_created: for (i = 0; i < num_cmd_data_created; ++i) if (i2cp_cmds[i].data_destroyer) i2cp_cmds[i].data_destroyer(pdata->cmd_data[i]); @@ -2317,7 +2347,7 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep) pdata = filep->private_data; this_pseudo = container_of(pdata->i2c_adapter.dev.parent, - struct i2cp_device, device); + struct i2cp_device, device); /* * The select(2) man page makes it clear that the behavior of pending @@ -2378,7 +2408,8 @@ static int i2cp_cdev_release(struct inode *inodep, struct file *filep) /* The caller must hold pdata->rsp_lock. */ /* Return value is whether or not to continue in calling loop. */ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, - ssize_t *ret, bool non_blocking, struct i2cp_controller *pdata) + ssize_t *ret, bool non_blocking, + struct i2cp_controller *pdata) { long wait_ret; ssize_t copy_size; @@ -2450,9 +2481,9 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, mutex_lock(&pdata->read_rsp_queue_lock); if (!list_empty(&pdata->read_rsp_queue_head)) - rsp_wrapper = list_first_entry( - &pdata->read_rsp_queue_head, - struct i2cp_rsp, queue); + rsp_wrapper = + list_first_entry(&pdata->read_rsp_queue_head, + struct i2cp_rsp, queue); /* * Avoid holding pdata->read_rsp_queue_lock while * executing a formatter, allocating memory, or doing @@ -2543,7 +2574,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, return false; } - write_end_char: + write_end_char: copy_size = sizeof(i2cp_ctrlr_end_char); /* * This assertion is just in case someone changes @@ -2554,8 +2585,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, * block, we already know it's greater than zero. */ BUILD_BUG_ON(copy_size != 1); - copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char, - copy_size); + copy_ret = copy_to_user(*buf, &i2cp_ctrlr_end_char, copy_size); copy_size -= copy_ret; /* * After writing to the userspace buffer, we need to @@ -2571,7 +2601,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, } copy_size = max_t(ssize_t, 0, - min_t(ssize_t, *count, pdata->rsp_buf_remaining)); + min_t(ssize_t, *count, pdata->rsp_buf_remaining)); copy_ret = copy_to_user(*buf, pdata->rsp_buf_pos, copy_size); copy_size -= copy_ret; pdata->rsp_buf_remaining -= copy_size; @@ -2584,14 +2614,14 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, pdata->rsp_buf_pos = NULL; } - /* - * When jumping here, the following variables should be set: - * copy_ret: Return value from copy_to_user() (bytes not copied). - * copy_size: The number of bytes successfully copied by copy_to_user(). In - * other words, this should be the size arg to copy_to_user() minus its - * return value (bytes not copied). - */ - after_copy_to_user: +/* + * When jumping here, the following variables should be set: + * copy_ret: Return value from copy_to_user() (bytes not copied). + * copy_size: The number of bytes successfully copied by copy_to_user(). In + * other words, this should be the size arg to copy_to_user() minus its + * return value (bytes not copied). + */ +after_copy_to_user: *ret += copy_size; *count -= copy_size; *buf += copy_size; @@ -2600,7 +2630,7 @@ static bool i2cp_cdev_read_iteration(char __user **buf, size_t *count, } static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf, - size_t count, loff_t *f_ps) + size_t count, loff_t *f_ps) { ssize_t ret = 0; bool non_blocking; @@ -2638,20 +2668,20 @@ static ssize_t i2cp_cdev_read(struct file *filep, char __user *buf, goto unlock; } - while (count > 0 && i2cp_cdev_read_iteration( - &buf, &count, &ret, non_blocking, pdata)) + while (count > 0 && i2cp_cdev_read_iteration(&buf, &count, &ret, + non_blocking, pdata)) ; - unlock: +unlock: mutex_unlock(&pdata->rsp_lock); return ret; } /* Must be called with pdata->cmd_lock held. */ /* Must never consume past first i2cp_ctrlr_end_char in @start. */ -static ssize_t i2cp_receive_ctrlr_cmd_header( - struct i2cp_controller *pdata, char *start, size_t remaining, - bool non_blocking) +static ssize_t i2cp_receive_ctrlr_cmd_header(struct i2cp_controller *pdata, + char *start, size_t remaining, + bool non_blocking) { int found_deliminator_char = 0; int i, cmd_idx; @@ -2665,7 +2695,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header( start[i] == i2cp_ctrlr_header_sep_char) { found_deliminator_char = 1; break; - } + } if (i <= buf_remaining) { copy_size = i; @@ -2695,7 +2725,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header( for (i = 0; i < ARRAY_SIZE(i2cp_cmds); ++i) if (i2cp_cmds[i].cmd_size == pdata->cmd_size && !memcmp(i2cp_cmds[i].cmd_string, pdata->cmd_buf, - pdata->cmd_size)) + pdata->cmd_size)) break; if (i >= ARRAY_SIZE(i2cp_cmds)) { /* unrecognized command */ @@ -2725,7 +2755,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_header( } } - clear_buffer: +clear_buffer: pdata->cmd_size = 0; /* * Ensure a trailing null character for the next header_receiver() or @@ -2745,7 +2775,8 @@ static ssize_t i2cp_receive_ctrlr_cmd_header( /* Must be called with pdata->cmd_lock held. */ /* Must never consume past first i2cp_ctrlr_end_char in @start. */ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata, - char *start, size_t remaining, bool non_blocking) + char *start, size_t remaining, + bool non_blocking) { ssize_t i, ret, size_holder; int cmd_idx; @@ -2755,13 +2786,14 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata, if (cmd_idx < 0) return -EINVAL; - size_holder = min_t(size_t, + size_holder = min_t( + size_t, (I2CP_CTRLR_CMD_LIMIT - (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment)) - - pdata->cmd_size, - (((pdata->cmd_size + remaining) / - pdata->cmd_data_increment) * - pdata->cmd_data_increment) - pdata->cmd_size); + pdata->cmd_size, + (((pdata->cmd_size + remaining) / pdata->cmd_data_increment) * + pdata->cmd_data_increment) - + pdata->cmd_size); /* Size of current buffer plus all remaining write bytes. */ size_holder = pdata->cmd_size + remaining; @@ -2791,8 +2823,10 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata, * buffer to end up with if there were unlimited write bytes * remaining (computed in-line below). */ - size_holder = min_t(ssize_t, size_holder, (I2CP_CTRLR_CMD_LIMIT - ( - I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment))); + size_holder = + min_t(ssize_t, size_holder, + (I2CP_CTRLR_CMD_LIMIT - + (I2CP_CTRLR_CMD_LIMIT % pdata->cmd_data_increment))); /* * Subtract the existing buffer size to get the number of bytes we * actually want to copy from the remaining write bytes in this loop @@ -2843,7 +2877,7 @@ static ssize_t i2cp_receive_ctrlr_cmd_data(struct i2cp_controller *pdata, /* Must be called with pdata->cmd_lock held. */ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata, - bool non_blocking) + bool non_blocking) { int ret = 0, cmd_idx; @@ -2851,8 +2885,9 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata, cmd_idx = pdata->cmd_idx_plus_one - 1; if (cmd_idx >= 0 && i2cp_cmds[cmd_idx].cmd_completer) { - ret = i2cp_cmds[cmd_idx].cmd_completer(pdata->cmd_data[cmd_idx], - pdata, pdata->cmd_receive_status, non_blocking); + ret = i2cp_cmds[cmd_idx].cmd_completer( + pdata->cmd_data[cmd_idx], pdata, + pdata->cmd_receive_status, non_blocking); if (ret > 0) ret = 0; } @@ -2872,7 +2907,7 @@ static int i2cp_receive_ctrlr_cmd_complete(struct i2cp_controller *pdata, } static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf, - size_t count, loff_t *f_ps) + size_t count, loff_t *f_ps) { ssize_t ret = 0; bool non_blocking; @@ -2949,8 +2984,8 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf, start += ret; if (ret > 0 && start[-1] == i2cp_ctrlr_end_char) { - ret = i2cp_receive_ctrlr_cmd_complete( - pdata, non_blocking); + ret = i2cp_receive_ctrlr_cmd_complete(pdata, + non_blocking); if (ret < 0) break; } @@ -2963,7 +2998,7 @@ static ssize_t i2cp_cdev_write(struct file *filep, const char __user *buf, /* If successful the whole write is always consumed. */ ret = count; - free_kbuf: +free_kbuf: kfree(kbuf); return ret; } @@ -3056,7 +3091,7 @@ static const struct file_operations i2cp_fileops = { }; static ssize_t i2cp_limit_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { int ret; @@ -3075,7 +3110,7 @@ static struct device_attribute i2cp_limit_dev_attr = { }; static ssize_t i2cp_count_show(struct device *dev, - struct device_attribute *attr, char *buf) + struct device_attribute *attr, char *buf) { int count, ret; struct i2cp_device *this_pseudo; @@ -3138,9 +3173,9 @@ static int __init i2cp_init(void) int ret = -1; if (i2cp_limit < I2CP_ADAPTERS_MIN || i2cp_limit > I2CP_ADAPTERS_MAX) { - pr_err("%s: i2cp_limit=%u, must be in range [" - STR(I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX) - "]\n", __func__, i2cp_limit); + pr_err("%s: i2cp_limit=%u, must be in range [" STR( + I2CP_ADAPTERS_MIN) ", " STR(I2CP_ADAPTERS_MAX) "]\n", + __func__, i2cp_limit); return -EINVAL; } @@ -3151,7 +3186,7 @@ static int __init i2cp_init(void) i2cp_class->dev_groups = i2cp_device_sysfs_groups; ret = alloc_chrdev_region(&i2cp_dev_num, I2CP_CDEV_BASEMINOR, - I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME); + I2CP_CDEV_COUNT, I2CP_CHRDEV_NAME); if (ret < 0) goto fail_after_class_create; @@ -3171,8 +3206,9 @@ static int __init i2cp_init(void) goto fail_after_device_init; mutex_init(&i2cp_device->counters.lock); - i2cp_device->counters.all_controllers = kcalloc(i2cp_limit, - sizeof(*i2cp_device->counters.all_controllers), GFP_KERNEL); + i2cp_device->counters.all_controllers = kcalloc( + i2cp_limit, sizeof(*i2cp_device->counters.all_controllers), + GFP_KERNEL); if (!i2cp_device->counters.all_controllers) { ret = -ENOMEM; goto fail_after_device_init; @@ -3187,11 +3223,11 @@ static int __init i2cp_init(void) return 0; - fail_after_device_init: +fail_after_device_init: put_device(&i2cp_device->device); - fail_after_chrdev_register: +fail_after_chrdev_register: unregister_chrdev_region(i2cp_dev_num, I2CP_CDEV_COUNT); - fail_after_class_create: +fail_after_class_create: i2c_p_class_destroy(); return ret; } -- cgit v1.2.1 From 81b83042a6d2f6ce3b03ae030bd97cedafa43c89 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:02 -0600 Subject: chip/mchp/qmspi_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0107106b588fbfe3bde34ca52ef6904cba3dc739 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729310 Reviewed-by: Jeremy Bettis --- chip/mchp/qmspi_chip.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/chip/mchp/qmspi_chip.h b/chip/mchp/qmspi_chip.h index 1db440b868..1795e5e11f 100644 --- a/chip/mchp/qmspi_chip.h +++ b/chip/mchp/qmspi_chip.h @@ -19,18 +19,17 @@ /* struct spi_device_t */ #include "spi.h" - int qmspi_transaction_flush(const struct spi_device_t *spi_device); int qmspi_transaction_wait(const struct spi_device_t *spi_device); int qmspi_transaction_sync(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); int qmspi_enable(int port, int enable); @@ -56,10 +55,9 @@ void qmspi_cfg_irq_start(uint8_t flags); * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR * or error (bit[7]==1) */ -uint8_t qmspi_xfr(const struct spi_device_t *spi_device, - uint32_t np_flags, - const uint8_t *txdata, uint32_t ntx, - uint8_t *rxdata, uint32_t nrx); +uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags, + const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata, + uint32_t nrx); #endif /* #ifndef _QMSPI_CHIP_H */ /** @} -- cgit v1.2.1 From 8bbad33269bc4b725b845cb263903de21c997e35 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:33 -0600 Subject: board/pazquel/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ice4e985a24cf7d4c4e7a795698cadd919b99fbc9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728813 Reviewed-by: Jeremy Bettis --- board/pazquel/board.c | 176 +++++++++++++++++++------------------------------- 1 file changed, 66 insertions(+), 110 deletions(-) diff --git a/board/pazquel/board.c b/board/pazquel/board.c index d3568a4bcb..0ec8b49364 100644 --- a/board/pazquel/board.c +++ b/board/pazquel/board.c @@ -33,8 +33,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -127,10 +127,8 @@ __override struct keyboard_scan_config keyscan_config = { * 2. T11 key not in keyboard (KSI_0,KSO_1): * change actual_key_mask[1] from 0xff to 0xfe */ - .actual_key_mask = { - 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x1c, 0xfe, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -141,41 +139,31 @@ __override struct keyboard_scan_config keyscan_config = { /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -183,58 +171,39 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, [PWM_CH_DISPLIGHT] = { .channel = 5, .flags = 0, .freq = 20000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -299,10 +268,8 @@ static void board_update_sensor_config_clamshell(void) motion_sensor_count = 0; gmr_tablet_switch_disable(); /* The sensors are not stuffed; don't allow lines to float */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_LID_ACCEL_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } DECLARE_HOOK(HOOK_INIT, board_update_sensor_config_clamshell, HOOK_PRIO_INIT_I2C + 2); @@ -352,9 +319,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); static void da9313_pvc_mode_ctrl(int enable) { @@ -364,12 +331,12 @@ static void da9313_pvc_mode_ctrl(int enable) */ if (enable) i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS, - DA9313_REG_PVC_CTRL, - DA9313_PVC_CTRL_PVC_MODE, MASK_SET); + DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE, + MASK_SET); else i2c_update8(I2C_PORT_POWER, DA9313_I2C_ADDR_FLAGS, - DA9313_REG_PVC_CTRL, - DA9313_PVC_CTRL_PVC_MODE, MASK_CLR); + DA9313_REG_PVC_CTRL, DA9313_PVC_CTRL_PVC_MODE, + MASK_CLR); } void da9313_init(void) @@ -377,7 +344,7 @@ void da9313_init(void) /* PVC operates in fixed frequency mode in S0. */ da9313_pvc_mode_ctrl(0); } -DECLARE_HOOK(HOOK_INIT, da9313_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, da9313_init, HOOK_PRIO_DEFAULT + 1); void board_hibernate(void) { @@ -387,10 +354,8 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); - gpio_set_flags(GPIO_LID_ACCEL_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_LID_ACCEL_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Enable the PPC power sink path before EC enters hibernate; @@ -435,8 +400,7 @@ static void board_shutdown_complete(void) } } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, board_shutdown_complete, - HOOK_PRIO_DEFAULT); - + HOOK_PRIO_DEFAULT); void board_set_switchcap_power(int enable) { @@ -495,8 +459,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -524,7 +487,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -548,23 +510,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) @@ -589,17 +549,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 4865cbb4cea9c9c8ad934b38fb59c3388d8892c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:32 -0600 Subject: common/spi_flash_reg.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I81700e6bf315124ee52c75324ddf741f08b99100 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729751 Reviewed-by: Jeremy Bettis --- common/spi_flash_reg.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/common/spi_flash_reg.c b/common/spi_flash_reg.c index ee8d31fa06..abcc321251 100644 --- a/common/spi_flash_reg.c +++ b/common/spi_flash_reg.c @@ -21,7 +21,7 @@ struct protect_range { enum bit_state cmp; enum bit_state sec; enum bit_state tb; - enum bit_state bp[3]; /* Ordered {BP2, BP1, BP0} */ + enum bit_state bp[3]; /* Ordered {BP2, BP1, BP0} */ uint32_t protect_start; uint32_t protect_len; }; @@ -39,7 +39,7 @@ struct protect_range { */ #if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B) static const struct protect_range spi_flash_protect_ranges[] = { - { IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { IGN, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ { IGN, IGN, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ { IGN, IGN, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */ }; @@ -49,17 +49,17 @@ static const struct protect_range spi_flash_protect_ranges[] = { /* For GD25LQ40, BP3 and BP4 have same meaning as TB and SEC */ static const struct protect_range spi_flash_protect_ranges[] = { /* CMP = 0 */ - { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ - { 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */ - { 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ + { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/4 */ + { 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ /* CMP = 1 */ - { 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ - { 1, 0, IGN, { 1, IGN, IGN }, 0, 0 }, /* None (W25Q40EW only) */ + { 1, 0, 0, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */ + { 1, 0, IGN, { 1, IGN, IGN }, 0, 0 }, /* None (W25Q40EW only) */ }; #elif defined(CONFIG_SPI_FLASH_W25Q64) static const struct protect_range spi_flash_protect_ranges[] = { - { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ { 0, 0, 1, { 1, 1, 0 }, 0, 0x400000 }, /* Lower 1/2 */ { 0, 0, 1, { 1, 0, 1 }, 0, 0x200000 }, /* Lower 1/4 */ }; @@ -67,7 +67,7 @@ static const struct protect_range spi_flash_protect_ranges[] = { #elif defined(CONFIG_SPI_FLASH_W25Q80) static const struct protect_range spi_flash_protect_ranges[] = { /* CMP = 0 */ - { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ { 0, 0, 1, { 0, 1, 0 }, 0, 0x20000 }, /* Lower 1/8 */ { 0, 0, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/4 */ { 0, 0, 1, { 1, 0, 0 }, 0, 0x80000 }, /* Lower 1/2 */ @@ -75,7 +75,7 @@ static const struct protect_range spi_flash_protect_ranges[] = { #elif defined(CONFIG_SPI_FLASH_W25Q128) static const struct protect_range spi_flash_protect_ranges[] = { /* CMP = 0 */ - { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ + { 0, IGN, IGN, { 0, 0, 0 }, 0, 0 }, /* No protection */ { 0, 0, 1, { 1, 0, 0 }, 0, 0x20000 }, /* Lower 1/8 */ { 0, 0, 1, { 1, 0, 1 }, 0, 0x40000 }, /* Lower 1/4 */ { 0, 0, 1, { 1, 1, 0 }, 0, 0x80000 }, /* Lower 1/2 */ @@ -107,8 +107,9 @@ int spi_flash_reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start, cmp = (sr2 & SPI_FLASH_SR2_CMP) ? 1 : 0; sec = (sr1 & SPI_FLASH_SR1_SEC) ? 1 : 0; tb = (sr1 & SPI_FLASH_SR1_TB) ? 1 : 0; - bp = (sr1 & (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0)) - >> 2; + bp = (sr1 & + (SPI_FLASH_SR1_BP2 | SPI_FLASH_SR1_BP1 | SPI_FLASH_SR1_BP0)) >> + 2; /* Bad pointers or invalid data */ if (!start || !len || sr1 == 0xff || sr2 == 0xff) @@ -174,12 +175,10 @@ int spi_flash_protect_to_reg(unsigned int start, unsigned int len, uint8_t *sr1, sec = GET_BIT(range->sec); tb = GET_BIT(range->tb); bp = GET_BIT(range->bp[0]) << 2 | - GET_BIT(range->bp[1]) << 1 | - GET_BIT(range->bp[2]); + GET_BIT(range->bp[1]) << 1 | GET_BIT(range->bp[2]); *sr1 = (sec ? SPI_FLASH_SR1_SEC : 0) | - (tb ? SPI_FLASH_SR1_TB : 0) | - (bp << 2); + (tb ? SPI_FLASH_SR1_TB : 0) | (bp << 2); *sr2 = (cmp ? SPI_FLASH_SR2_CMP : 0); return EC_SUCCESS; } -- cgit v1.2.1 From c62c12e0a3bbdc102408ea9ee838dec3957d3b2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:23 -0600 Subject: baseboard/intelrvp/usb_pd_policy_mecc_1_0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib048a27f36fcc7e582ac08720bbfde69a0d51ac3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727905 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/usb_pd_policy_mecc_1_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c index 8e06c9f0b3..5c871075e0 100644 --- a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c +++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c @@ -15,8 +15,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { -- cgit v1.2.1 From 43e6515f3b048eec48626c0ec5f59c4cd66388b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:15 -0600 Subject: driver/tcpm/raa489000.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I26a44c7ce72bf27d10bf2d96dccd530364119bdc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730084 Reviewed-by: Jeremy Bettis --- driver/tcpm/raa489000.h | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/driver/tcpm/raa489000.h b/driver/tcpm/raa489000.h index 2a4c7c6b3d..4e5ef82cd5 100644 --- a/driver/tcpm/raa489000.h +++ b/driver/tcpm/raa489000.h @@ -17,25 +17,25 @@ #define RAA489000_TCPC3_I2C_FLAGS 0x25 /* Vendor registers */ -#define RAA489000_TCPC_SETTING1 0x80 -#define RAA489000_VBUS_VOLTAGE_TARGET 0x90 -#define RAA489000_VBUS_CURRENT_TARGET 0x92 -#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 -#define RAA489000_TYPEC_SETTING1 0xC0 -#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 -#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 +#define RAA489000_TCPC_SETTING1 0x80 +#define RAA489000_VBUS_VOLTAGE_TARGET 0x90 +#define RAA489000_VBUS_CURRENT_TARGET 0x92 +#define RAA489000_VBUS_OCP_UV_THRESHOLD 0x94 +#define RAA489000_TYPEC_SETTING1 0xC0 +#define RAA489000_PD_PHYSICAL_SETTING1 0xE0 +#define RAA489000_PD_PHYSICAL_PARAMETER1 0xE8 /* TCPC_SETTING_1 */ -#define RAA489000_TCPCV1_0_EN BIT(0) -#define RAA489000_TCPC_PWR_CNTRL BIT(4) +#define RAA489000_TCPCV1_0_EN BIT(0) +#define RAA489000_TCPC_PWR_CNTRL BIT(4) /* VBUS_CURRENT_TARGET */ -#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */ -#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */ +#define RAA489000_VBUS_CURRENT_TARGET_3A 0x66 /* 3.0A + iOvershoot */ +#define RAA489000_VBUS_CURRENT_TARGET_1_5A 0x38 /* 1.5A + iOvershoot */ /* VBUS_VOLTAGE_TARGET */ -#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */ -#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */ +#define RAA489000_VBUS_VOLTAGE_TARGET_5160MV 0x102 /* 5.16V */ +#define RAA489000_VBUS_VOLTAGE_TARGET_5220MV 0x105 /* 5.22V */ /* VBUS_OCP_UV_THRESHOLD */ /* Detect voltage level of overcurrent protection during Sourcing VBUS */ @@ -43,26 +43,26 @@ /* TYPEC_SETTING1 - only older silicon */ /* Enables for reverse current protection */ -#define RAA489000_SETTING1_IP2_EN BIT(9) -#define RAA489000_SETTING1_IP1_EN BIT(8) +#define RAA489000_SETTING1_IP2_EN BIT(9) +#define RAA489000_SETTING1_IP1_EN BIT(8) /* Switches from dead-battery Rd */ -#define RAA489000_SETTING1_RDOE BIT(7) +#define RAA489000_SETTING1_RDOE BIT(7) /* CC comparator enables */ -#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6) -#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5) -#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4) -#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3) -#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2) -#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1) +#define RAA489000_SETTING1_CC2_CMP3_EN BIT(6) +#define RAA489000_SETTING1_CC2_CMP2_EN BIT(5) +#define RAA489000_SETTING1_CC2_CMP1_EN BIT(4) +#define RAA489000_SETTING1_CC1_CMP3_EN BIT(3) +#define RAA489000_SETTING1_CC1_CMP2_EN BIT(2) +#define RAA489000_SETTING1_CC1_CMP1_EN BIT(1) /* CC debounce enable */ -#define RAA489000_SETTING1_CC_DB_EN BIT(0) +#define RAA489000_SETTING1_CC_DB_EN BIT(0) /* PD_PHYSICAL_SETTING_1 */ #define RAA489000_PD_PHY_SETTING1_RECEIVER_EN BIT(9) -#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8) +#define RAA489000_PD_PHY_SETTING1_SQUELCH_EN BIT(8) #define RAA489000_PD_PHY_SETTING1_TX_LDO11_EN BIT(0) /* PD_PHYSICAL_PARMETER_1 */ -- cgit v1.2.1 From 48da0db42da5617c461dc770eeb46e323e9e6968 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:17 -0600 Subject: chip/stm32/clock-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I47ca0a89182b88321ae6e8bc65349349bb818ad5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729467 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32l.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index bb0da42d14..8edd6167ef 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -37,9 +37,9 @@ static int fake_hibernate; #define MSI_1MHZ_CLOCK BIT(20) enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed oscillator */ - OSC_MSI, /* Med-speed oscillator @ 1 MHz */ + OSC_INIT = 0, /* Uninitialized */ + OSC_HSI, /* High-speed oscillator */ + OSC_MSI, /* Med-speed oscillator @ 1 MHz */ }; static int freq; @@ -86,8 +86,8 @@ static void clock_set_osc(enum clock_osc osc) switch (osc) { case OSC_HSI: /* Ensure that HSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_HSION, STM32_RCC_CR_HSIRDY); + wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_HSION, + STM32_RCC_CR_HSIRDY); /* Disable LPSDSR */ STM32_PWR_CR &= ~STM32_PWR_CR_LPSDSR; @@ -122,7 +122,7 @@ static void clock_set_osc(enum clock_osc osc) STM32_RCC_CFGR = STM32_RCC_CFGR_SW_HSI; /* RM says to check SWS bits to make sure HSI is the sysclock */ while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_HSI) + STM32_RCC_CFGR_SWS_HSI) ; /* Disable MSI */ @@ -137,14 +137,14 @@ static void clock_set_osc(enum clock_osc osc) (STM32_RCC_ICSCR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | STM32_RCC_ICSCR_MSIRANGE_1MHZ; /* Ensure that MSI is ON */ - wait_for_ready(&STM32_RCC_CR, - STM32_RCC_CR_MSION, STM32_RCC_CR_MSIRDY); + wait_for_ready(&STM32_RCC_CR, STM32_RCC_CR_MSION, + STM32_RCC_CR_MSIRDY); /* Switch to MSI */ STM32_RCC_CFGR = STM32_RCC_CFGR_SW_MSI; /* RM says to check SWS bits to make sure MSI is the sysclock */ while ((STM32_RCC_CFGR & STM32_RCC_CFGR_SWS_MASK) != - STM32_RCC_CFGR_SWS_MSI) + STM32_RCC_CFGR_SWS_MSI) ; /* @@ -208,7 +208,6 @@ void clock_enable_module(enum module_id module, int enable) /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { - /* Flush UART before switching clock speed */ cflush(); @@ -314,7 +313,7 @@ static void fake_hibernate_power_button_hook(void) } } DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, fake_hibernate_power_button_hook, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void fake_hibernate_lid_hook(void) { @@ -379,6 +378,5 @@ static int command_clock(int argc, char **argv) ccprintf("Clock frequency is now %d Hz\n", freq); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | msi", +DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | msi", "Set clock frequency"); -- cgit v1.2.1 From 13c24a670aebefb7dcdd68009914bbeb3703c100 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:53 -0600 Subject: common/keyboard_backlight.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I542f826c5973b0f02ef672f0aa3330e72a16d720 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729641 Reviewed-by: Jeremy Bettis --- common/keyboard_backlight.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/common/keyboard_backlight.c b/common/keyboard_backlight.c index 62da361d73..9e4ae97c14 100644 --- a/common/keyboard_backlight.c +++ b/common/keyboard_backlight.c @@ -15,16 +15,20 @@ #include "timer.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) static struct kblight_conf kblight; static int current_percent; static uint8_t current_enable; -__overridable void board_kblight_init(void) {} +__overridable void board_kblight_init(void) +{ +} -__overridable void board_kblight_shutdown(void) {} +__overridable void board_kblight_shutdown(void) +{ +} static int kblight_init(void) { @@ -89,7 +93,6 @@ int kblight_get_enabled(void) return -1; } - int kblight_register(const struct kblight_drv *drv) { kblight.drv = drv; @@ -137,7 +140,7 @@ static void kblight_resume(void) } } DECLARE_HOOK(HOOK_CHIPSET_RESUME, kblight_resume, HOOK_PRIO_DEFAULT); -#endif /* CONFIG_AP_POWER_CONTROL */ +#endif /* CONFIG_AP_POWER_CONTROL */ #ifdef CONFIG_LID_SWITCH static void kblight_lid_change(void) @@ -162,12 +165,11 @@ static int cc_kblight(int argc, char **argv) if (kblight_enable(i > 0)) return EC_ERROR_PARAM1; } - ccprintf("Keyboard backlight: %d%% enabled: %d\n", - kblight_get(), kblight_get_enabled()); + ccprintf("Keyboard backlight: %d%% enabled: %d\n", kblight_get(), + kblight_get_enabled()); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(kblight, cc_kblight, - "percent", +DECLARE_CONSOLE_COMMAND(kblight, cc_kblight, "percent", "Get/set keyboard backlight"); static enum ec_status @@ -182,8 +184,7 @@ hc_get_keyboard_backlight(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT, - hc_get_keyboard_backlight, - EC_VER_MASK(0)); + hc_get_keyboard_backlight, EC_VER_MASK(0)); static enum ec_status hc_set_keyboard_backlight(struct host_cmd_handler_args *args) @@ -197,5 +198,4 @@ hc_set_keyboard_backlight(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT, - hc_set_keyboard_backlight, - EC_VER_MASK(0)); + hc_set_keyboard_backlight, EC_VER_MASK(0)); -- cgit v1.2.1 From ce2aa18189a10af5bc0b1edbf84d82d4e1d0bbde Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:33 -0600 Subject: zephyr/projects/corsola/src/kingler/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0c2f85cee71d5081b0f4f813aa39b4b415c31bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730739 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/kingler/usb_pd_policy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usb_pd_policy.c b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c index 51a05598b9..821b7475d5 100644 --- a/zephyr/projects/corsola/src/kingler/usb_pd_policy.c +++ b/zephyr/projects/corsola/src/kingler/usb_pd_policy.c @@ -14,8 +14,8 @@ #include "baseboard_usbc_config.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) void pd_power_supply_reset(int port) { @@ -39,7 +39,6 @@ void pd_power_supply_reset(int port) pd_send_host_event(PD_EVENT_POWER_CHANGE); } - int pd_set_power_supply_ready(int port) { int rv; -- cgit v1.2.1 From 8b13f0fd40d604c0d2804857c7f73428a25160ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:29 -0600 Subject: board/kracko/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifdec68b1d0d30d3dac7b439497cb4b4426704bff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728566 Reviewed-by: Jeremy Bettis --- board/kracko/board.c | 184 +++++++++++++++++++++++---------------------------- 1 file changed, 83 insertions(+), 101 deletions(-) diff --git a/board/kracko/board.c b/board/kracko/board.c index 3458f91a98..722c7ac3e2 100644 --- a/board/kracko/board.c +++ b/board/kracko/board.c @@ -43,7 +43,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -166,48 +166,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -282,23 +270,17 @@ static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_kx022_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_kx022_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Drivers */ struct motion_sensor_t kx022_lid_accel = { @@ -538,8 +520,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -547,11 +529,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -562,11 +544,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -671,33 +653,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -727,9 +707,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -748,14 +727,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 8fa8c85cf9de470b18649352bf492dcea6c2869f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:17 -0600 Subject: driver/ina3221.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib66d4a11bb683c9fe19329c6695e6e6ff2f0e6c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729982 Reviewed-by: Jeremy Bettis --- driver/ina3221.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/driver/ina3221.c b/driver/ina3221.c index 5b89f9694e..3220cebd23 100644 --- a/driver/ina3221.c +++ b/driver/ina3221.c @@ -14,12 +14,12 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) const static uint8_t ina3221_reg_map[INA3221_CHAN_COUNT][INA3221_MAX_REG] = { -{ 1, 2, 7, 8 }, /* Chan 1 */ -{ 3, 4, 9, 10 }, /* Chan 2 */ -{ 5, 6, 11, 12 } /* Chan 3 */ + { 1, 2, 7, 8 }, /* Chan 1 */ + { 3, 4, 9, 10 }, /* Chan 2 */ + { 5, 6, 11, 12 } /* Chan 3 */ }; static uint16_t ina3221_read(unsigned int unit, uint8_t reg) @@ -27,8 +27,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg) int res; int val; - res = i2c_read16(ina3221[unit].port, ina3221[unit].address, - reg, &val); + res = i2c_read16(ina3221[unit].port, ina3221[unit].address, reg, &val); if (res) { CPRINTS("INA3221 I2C read failed"); return 0x0bad; @@ -37,7 +36,7 @@ static uint16_t ina3221_read(unsigned int unit, uint8_t reg) } static uint16_t ina3221_chan_read(unsigned int unit, enum ina3221_channel chan, - enum ina3221_register reg) + enum ina3221_register reg) { if (chan >= INA3221_CHAN_COUNT || reg >= INA3221_MAX_REG) { CPRINTS("INA3221 Bad channel or register value"); @@ -51,8 +50,8 @@ static int ina3221_write(unsigned int unit, uint8_t reg, uint16_t val) int res; uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); - res = i2c_write16(ina3221[unit].port, ina3221[unit].address, - reg, be_val); + res = i2c_write16(ina3221[unit].port, ina3221[unit].address, reg, + be_val); if (res) CPRINTS("INA3221 I2C write failed"); return res; @@ -93,12 +92,12 @@ static void ina3221_dump(unsigned int unit) if (ina3221[unit].name[chan] != NULL) { sv[chan] = ina3221_chan_read(unit, chan, INA3221_SHUNT_VOLT); - bv[chan] = ina3221_chan_read(unit, chan, - INA3221_BUS_VOLT); - crit[chan] = ina3221_chan_read(unit, chan, - INA3221_CRITICAL); - warn[chan] = ina3221_chan_read(unit, chan, - INA3221_WARNING); + bv[chan] = + ina3221_chan_read(unit, chan, INA3221_BUS_VOLT); + crit[chan] = + ina3221_chan_read(unit, chan, INA3221_CRITICAL); + warn[chan] = + ina3221_chan_read(unit, chan, INA3221_WARNING); } } mask = ina3221_read(unit, INA3221_REG_MASK); @@ -109,9 +108,9 @@ static void ina3221_dump(unsigned int unit) if (ina3221[unit].name[chan] != NULL) { ccprintf("%d: %s:\n", chan, ina3221[unit].name[chan]); ccprintf(" Shunt voltage: %04x => %d uV\n", - sv[chan], INA3221_SHUNT_UV((int)sv[chan])); + sv[chan], INA3221_SHUNT_UV((int)sv[chan])); ccprintf(" Bus voltage : %04x => %d mV\n", - bv[chan], INA3221_BUS_MV((int)bv[chan])); + bv[chan], INA3221_BUS_MV((int)bv[chan])); ccprintf(" Warning : %04x\n", warn[chan]); ccprintf(" Critical : %04x\n", crit[chan]); } @@ -156,7 +155,6 @@ static int command_ina(int argc, char **argv) return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(ina, command_ina, - " [config|mask ]", +DECLARE_CONSOLE_COMMAND(ina, command_ina, " [config|mask ]", "INA3221 voltage sensing"); #endif -- cgit v1.2.1 From adcff512a0e301c202eee8223021d9e9cb03978b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:02 -0600 Subject: board/taniks/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea3372e7e1ceb23b4d5fa237613a6674b4e1e8b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729013 Reviewed-by: Jeremy Bettis --- board/taniks/keyboard.c | 61 ++++++++++++------------------------------------- 1 file changed, 15 insertions(+), 46 deletions(-) diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c index 4c055d292b..58a5d54ad0 100644 --- a/board/taniks/keyboard.c +++ b/board/taniks/keyboard.c @@ -66,58 +66,27 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, - LED( 0, 0), DELM, - LED( 1, 0), DELM, - LED( 2, 0), DELM, - LED( 3, 0), DELM, - LED( 4, 0), DELM, - LED( 5, 0), DELM, - LED( 6, 0), DELM, - LED( 7, 0), DELM, - LED( 0, 1), DELM, - LED( 1, 1), DELM, - LED( 2, 1), DELM, - LED( 3, 1), DELM, - LED( 4, 1), DELM, - LED( 5, 1), DELM, - LED( 6, 1), DELM, - LED( 7, 1), DELM, - LED( 0, 2), DELM, - LED( 1, 2), DELM, - LED( 2, 2), DELM, - LED( 3, 2), DELM, - LED( 4, 2), DELM, - LED( 5, 2), DELM, - LED( 6, 2), DELM, - LED( 7, 2), DELM, - LED( 0, 3), DELM, - LED( 1, 3), DELM, - LED( 2, 3), DELM, - LED( 3, 3), DELM, - LED( 4, 3), DELM, - LED( 5, 3), DELM, - LED( 6, 3), DELM, - LED( 7, 3), DELM, - LED( 0, 4), DELM, - LED( 1, 4), DELM, - LED( 2, 4), DELM, - LED( 3, 4), DELM, - LED( 4, 4), DELM, - LED( 5, 4), DELM, - LED( 6, 4), DELM, - LED( 7, 4), DELM, - DELM, + DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0), + DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0), + DELM, LED(0, 1), DELM, LED(1, 1), DELM, LED(2, 1), DELM, LED(3, 1), + DELM, LED(4, 1), DELM, LED(5, 1), DELM, LED(6, 1), DELM, LED(7, 1), + DELM, LED(0, 2), DELM, LED(1, 2), DELM, LED(2, 2), DELM, LED(3, 2), + DELM, LED(4, 2), DELM, LED(5, 2), DELM, LED(6, 2), DELM, LED(7, 2), + DELM, LED(0, 3), DELM, LED(1, 3), DELM, LED(2, 3), DELM, LED(3, 3), + DELM, LED(4, 3), DELM, LED(5, 3), DELM, LED(6, 3), DELM, LED(7, 3), + DELM, LED(0, 4), DELM, LED(1, 4), DELM, LED(2, 4), DELM, LED(3, 4), + DELM, LED(4, 4), DELM, LED(5, 4), DELM, LED(6, 4), DELM, LED(7, 4), + DELM, DELM, }; #undef LED #undef DELM const size_t rgbkbd_map_size = ARRAY_SIZE(rgbkbd_map); -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &taniks_kb; } -- cgit v1.2.1 From f4b7dbcae3bdb9531700e7be8307ce870ebcf360 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:19 -0600 Subject: board/crota/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib129b5a901f95379d2f1453ca3e9164ba9106d2c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728215 Reviewed-by: Jeremy Bettis --- board/crota/usbc_config.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/board/crota/usbc_config.c b/board/crota/usbc_config.c index a06631489f..7ff908c7fa 100644 --- a/board/crota/usbc_config.c +++ b/board/crota/usbc_config.c @@ -36,15 +36,11 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #ifdef CONFIG_ZEPHYR -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; #endif /* CONFIG_ZEPHYR */ /* USBC TCPC configuration */ @@ -204,8 +200,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } -- cgit v1.2.1 From 2e2be0da5f3eee481096aea4fc71de4b120ed6b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:22 -0600 Subject: common/motion_sense_fifo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a407a4e78ffffc5090d0ddda95da59f324130c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729695 Reviewed-by: Jeremy Bettis --- common/motion_sense_fifo.c | 63 +++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 34 deletions(-) diff --git a/common/motion_sense_fifo.c b/common/motion_sense_fifo.c index 5743d0fdcb..f045aa32ac 100644 --- a/common/motion_sense_fifo.c +++ b/common/motion_sense_fifo.c @@ -15,7 +15,7 @@ #include "online_calibration.h" #include "stdbool.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) /** * Staged metadata for the fifo queue. @@ -76,8 +76,8 @@ static int wake_up_needed; * @param data The data entry to check. * @return 1 if the entry is a timestamp, 0 otherwise. */ -static inline int is_timestamp( - const struct ec_response_motion_sensor_data *data) +static inline int +is_timestamp(const struct ec_response_motion_sensor_data *data) { return data->flags & MOTIONSENSE_SENSOR_FLAG_TIMESTAMP; } @@ -102,8 +102,8 @@ static inline bool is_data(const struct ec_response_motion_sensor_data *data) */ static inline struct ec_response_motion_sensor_data *get_fifo_head(void) { - return ((struct ec_response_motion_sensor_data *) fifo.buffer) + - (fifo.state->head & fifo.buffer_units_mask); + return ((struct ec_response_motion_sensor_data *)fifo.buffer) + + (fifo.state->head & fifo.buffer_units_mask); } /** @@ -229,10 +229,8 @@ static inline bool is_new_timestamp(uint8_t sensor_num) * @param sensor The sensor that generated the data * @param valid_data The number of readable data entries in the data. */ -static void fifo_stage_unit( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - int valid_data) +static void fifo_stage_unit(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, int valid_data) { struct queue_chunk chunk; int i; @@ -279,7 +277,8 @@ static void fifo_stage_unit( if (IS_ENABLED(CONFIG_TABLET_MODE)) data->flags |= (tablet_get_mode() ? - MOTIONSENSE_SENSOR_FLAG_TABLET_MODE : 0); + MOTIONSENSE_SENSOR_FLAG_TABLET_MODE : + 0); /* * Get the next writable block in the fifo. We don't need to lock this @@ -316,8 +315,7 @@ static void fifo_stage_unit( * If the new per-sensor sample count is greater than 1, we'll need to * spread. */ - if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) && - !is_timestamp(data) && + if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS) && !is_timestamp(data) && ++fifo_staged.sample_count[data->sensor_num] > 1) fifo_staged.requires_spreading = 1; @@ -351,8 +349,9 @@ static void fifo_stage_timestamp(uint32_t timestamp, uint8_t sensor_num) static inline struct ec_response_motion_sensor_data * peek_fifo_staged(size_t offset) { - return (struct ec_response_motion_sensor_data *) - queue_get_write_chunk(&fifo, offset).buffer; + return (struct ec_response_motion_sensor_data *)queue_get_write_chunk( + &fifo, offset) + .buffer; } void motion_sense_fifo_init(void) @@ -389,9 +388,8 @@ void motion_sense_fifo_reset_needed_flags(void) mutex_unlock(&g_sensor_mutex); } -void motion_sense_fifo_insert_async_event( - struct motion_sensor_t *sensor, - enum motion_sense_async_event event) +void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor, + enum motion_sense_async_event event) { struct ec_response_motion_sensor_data vector; @@ -409,11 +407,9 @@ inline void motion_sense_fifo_add_timestamp(uint32_t timestamp) motion_sense_fifo_commit_data(); } -void motion_sense_fifo_stage_data( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - int valid_data, - uint32_t time) +void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, + int valid_data, uint32_t time) { if (IS_ENABLED(CONFIG_SENSOR_TIGHT_TIMESTAMPS)) { /* First entry, save the time for spreading later. */ @@ -474,9 +470,9 @@ void motion_sense_fifo_commit_data(void) * window length / (sample count - 1). */ if (window && fifo_staged.sample_count[i] > 1) - period = MIN( - period, - window / (fifo_staged.sample_count[i] - 1)); + period = + MIN(period, + window / (fifo_staged.sample_count[i] - 1)); data_periods[i] = period; } @@ -531,9 +527,9 @@ commit_data_end: next_timestamp[sensor_num].prev = next_timestamp[sensor_num].next; next_timestamp[sensor_num].next += - fifo_staged.requires_spreading - ? data_periods[sensor_num] - : motion_sensors[sensor_num].collection_rate; + fifo_staged.requires_spreading ? + data_periods[sensor_num] : + motion_sensors[sensor_num].collection_rate; /* Update online calibration if enabled. */ data = peek_fifo_staged(i); @@ -559,8 +555,7 @@ commit_data_end: } void motion_sense_fifo_get_info( - struct ec_response_motion_sense_fifo_info *fifo_info, - int reset) + struct ec_response_motion_sense_fifo_info *fifo_info, int reset) { mutex_lock(&g_sensor_mutex); fifo_info->size = fifo.buffer_units; @@ -641,7 +636,8 @@ static int motion_sense_read_fifo(int argc, char **argv) memcpy(×tamp, v.data, sizeof(v.data)); ccprintf("Timestamp: 0x%016llx%s\n", timestamp, (v.flags & MOTIONSENSE_SENSOR_FLAG_FLUSH ? - " - Flush" : "")); + " - Flush" : + "")); } else { ccprintf("%d %d: %-5d %-5d %-5d\n", i, v.sensor_num, v.data[X], v.data[Y], v.data[Z]); @@ -650,7 +646,6 @@ static int motion_sense_read_fifo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo, - "id", - "Read Fifo sensor"); +DECLARE_CONSOLE_COMMAND(fiforead, motion_sense_read_fifo, "id", + "Read Fifo sensor"); #endif /* defined(CONFIG_CMD_ACCEL_FIFO) */ -- cgit v1.2.1 From 686b30dc729005687f8296d539533ba393136093 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:38 -0600 Subject: zephyr/include/emul/emul_common_i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I20af74fb79312c88f91656a2e14f6fc9dfc27610 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730720 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_common_i2c.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/include/emul/emul_common_i2c.h b/zephyr/include/emul/emul_common_i2c.h index 676308b027..cf8ccf0f3b 100644 --- a/zephyr/include/emul/emul_common_i2c.h +++ b/zephyr/include/emul/emul_common_i2c.h @@ -49,8 +49,8 @@ * Special register values used in @ref i2c_common_emul_set_read_fail_reg and * @ref i2c_common_emul_set_write_fail_reg */ -#define I2C_COMMON_EMUL_FAIL_ALL_REG (-1) -#define I2C_COMMON_EMUL_NO_FAIL_REG (-2) +#define I2C_COMMON_EMUL_FAIL_ALL_REG (-1) +#define I2C_COMMON_EMUL_NO_FAIL_REG (-2) /** * Describe if there is no ongoing I2C message or if there is message handled -- cgit v1.2.1 From 2392ea378368b37358af3dfcc0fbeb5fa0454134 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:11 -0600 Subject: chip/mt_scp/mt818x/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If973a2121ef5fea5a34db62bcab266aff6ea8d19 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729343 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/uart.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/mt_scp/mt818x/uart.c b/chip/mt_scp/mt818x/uart.c index 109f8b595b..4b3b45d8ea 100644 --- a/chip/mt_scp/mt818x/uart.c +++ b/chip/mt_scp/mt818x/uart.c @@ -16,7 +16,7 @@ #include "util.h" /* Console UART index */ -#define UARTN CONFIG_UART_CONSOLE +#define UARTN CONFIG_UART_CONSOLE #define UART_IDLE_WAIT_US 500 static uint8_t uart_done, tx_started; @@ -155,9 +155,8 @@ void uart_init(void) #endif /* Init and clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; + UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT; /* Line control: parity none, 8 bit, 1 stop bit */ UART_LCR(UARTN) = UART_LCR_WLEN8; /* For baud rate <= 115200 */ -- cgit v1.2.1 From 02f91292400be6c4d631b9fc452bb32245c12f01 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:01 -0600 Subject: board/driblee/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I707f1cebd0b9d5651a357b317e30df310f5c2cd3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728258 Reviewed-by: Jeremy Bettis --- board/driblee/board.c | 52 ++++++++++++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 28 deletions(-) diff --git a/board/driblee/board.c b/board/driblee/board.c index 5cf9b686ac..f5c7e0e3cc 100644 --- a/board/driblee/board.c +++ b/board/driblee/board.c @@ -41,13 +41,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) static uint8_t new_adc_key_state; @@ -77,8 +77,8 @@ static const struct ec_response_keybd_config driblee_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &driblee_keybd; } @@ -119,7 +119,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -165,22 +164,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -197,8 +196,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -271,13 +270,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -328,7 +325,7 @@ int board_set_active_charge_port(int port) /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || - tcpc_write(port, TCPC_REG_COMMAND, + tcpc_write(port, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { CPRINTS("p%d: sink path enable failed.", port); charger_discharge_on_ac(0); @@ -341,8 +338,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -398,9 +395,8 @@ static void hdmi_disable(void) } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, hdmi_disable, HOOK_PRIO_DEFAULT); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; -- cgit v1.2.1 From 4a0f19981cf952ebc7f0c2d1775151229f8a759d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:55 -0600 Subject: board/fizz/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2d1e67d046b072b39b6321685223b0960072469a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728370 Reviewed-by: Jeremy Bettis --- board/fizz/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/fizz/usb_pd_policy.c b/board/fizz/usb_pd_policy.c index 5fc495417f..ad6fac133f 100644 --- a/board/fizz/usb_pd_policy.c +++ b/board/fizz/usb_pd_policy.c @@ -23,8 +23,8 @@ #include "usb_pd_pdo.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int board_vbus_source_enabled(int port) { -- cgit v1.2.1 From 706c08fc8cc724f31efd8c7053d6bc7822aa5d04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:51 -0600 Subject: driver/ioexpander/pcal6408.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0099746e5ff5059e4f3e08bb6c3f40ee81beeeb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730009 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pcal6408.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/driver/ioexpander/pcal6408.h b/driver/ioexpander/pcal6408.h index fc9969aab1..a9eac4bfaf 100644 --- a/driver/ioexpander/pcal6408.h +++ b/driver/ioexpander/pcal6408.h @@ -8,28 +8,28 @@ #ifndef __CROS_EC_IOEXPANDER_PCAL6408_H #define __CROS_EC_IOEXPANDER_PCAL6408_H -#define PCAL6408_I2C_ADDR0 0x20 -#define PCAL6408_I2C_ADDR1 0x21 +#define PCAL6408_I2C_ADDR0 0x20 +#define PCAL6408_I2C_ADDR1 0x21 -#define PCAL6408_REG_INPUT 0x00 -#define PCAL6408_REG_OUTPUT 0x01 -#define PCAL6408_REG_POLARITY_INVERSION 0x02 -#define PCAL6408_REG_CONFIG 0x03 -#define PCAL6408_REG_OUT_STRENGTH0 0x40 -#define PCAL6408_REG_OUT_STRENGTH1 0x41 -#define PCAL6408_REG_INPUT_LATCH 0x42 -#define PCAL6408_REG_PULL_ENABLE 0x43 -#define PCAL6408_REG_PULL_UP_DOWN 0x44 -#define PCAL6408_REG_INT_MASK 0x45 -#define PCAL6408_REG_INT_STATUS 0x46 -#define PCAL6408_REG_OUT_CONFIG 0x4f +#define PCAL6408_REG_INPUT 0x00 +#define PCAL6408_REG_OUTPUT 0x01 +#define PCAL6408_REG_POLARITY_INVERSION 0x02 +#define PCAL6408_REG_CONFIG 0x03 +#define PCAL6408_REG_OUT_STRENGTH0 0x40 +#define PCAL6408_REG_OUT_STRENGTH1 0x41 +#define PCAL6408_REG_INPUT_LATCH 0x42 +#define PCAL6408_REG_PULL_ENABLE 0x43 +#define PCAL6408_REG_PULL_UP_DOWN 0x44 +#define PCAL6408_REG_INT_MASK 0x45 +#define PCAL6408_REG_INT_STATUS 0x46 +#define PCAL6408_REG_OUT_CONFIG 0x4f -#define PCAL6408_VALID_GPIO_MASK 0xff +#define PCAL6408_VALID_GPIO_MASK 0xff -#define PCAL6408_OUTPUT 0 -#define PCAL6408_INPUT 1 +#define PCAL6408_OUTPUT 0 +#define PCAL6408_INPUT 1 -#define PCAL6408_OUT_CONFIG_OPEN_DRAIN 0x01 +#define PCAL6408_OUT_CONFIG_OPEN_DRAIN 0x01 /* * Check which IO's interrupt event is triggered. If any, call its @@ -39,4 +39,4 @@ int pcal6408_ioex_event_handler(int ioex); extern const struct ioexpander_drv pcal6408_ioexpander_drv; -#endif /* __CROS_EC_IOEXPANDER_PCAL6408_H */ +#endif /* __CROS_EC_IOEXPANDER_PCAL6408_H */ -- cgit v1.2.1 From 5a558fa50d066a6fff06094d07332f850c5b7d41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:01 -0600 Subject: board/lalala/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9ff37e844cd09d39530211382701cdbc0bcdfb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728613 Reviewed-by: Jeremy Bettis --- board/lalala/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/lalala/led.c b/board/lalala/led.c index cfe6f9eb6a..a726ebcd84 100644 --- a/board/lalala/led.c +++ b/board/lalala/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 97938cb82360b4def9726993dcd62c0226401565 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:36 -0600 Subject: driver/ioexpander/pca9534.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I772d517940278cfa7728ae835eae4c9d308f1a71 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730007 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pca9534.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/driver/ioexpander/pca9534.c b/driver/ioexpander/pca9534.c index d56eb864cb..206b501e1a 100644 --- a/driver/ioexpander/pca9534.c +++ b/driver/ioexpander/pca9534.c @@ -8,8 +8,8 @@ #include "i2c.h" #include "pca9534.h" -static int pca9534_pin_read(const int port, const uint16_t addr_flags, - int reg, int pin, int *val) +static int pca9534_pin_read(const int port, const uint16_t addr_flags, int reg, + int pin, int *val) { int ret; ret = i2c_read8(port, addr_flags, reg, val); @@ -17,8 +17,8 @@ static int pca9534_pin_read(const int port, const uint16_t addr_flags, return ret; } -static int pca9534_pin_write(const int port, const uint16_t addr_flags, - int reg, int pin, int val) +static int pca9534_pin_write(const int port, const uint16_t addr_flags, int reg, + int pin, int val) { int ret, v; ret = i2c_read8(port, addr_flags, reg, &v); @@ -30,23 +30,23 @@ static int pca9534_pin_write(const int port, const uint16_t addr_flags, return i2c_write8(port, addr_flags, reg, v); } -int pca9534_get_level(const int port, const uint16_t addr_flags, - int pin, int *level) +int pca9534_get_level(const int port, const uint16_t addr_flags, int pin, + int *level) { - return pca9534_pin_read(port, addr_flags, - PCA9534_REG_INPUT, pin, level); + return pca9534_pin_read(port, addr_flags, PCA9534_REG_INPUT, pin, + level); } -int pca9534_set_level(const int port, const uint16_t addr_flags, - int pin, int level) +int pca9534_set_level(const int port, const uint16_t addr_flags, int pin, + int level) { - return pca9534_pin_write(port, addr_flags, - PCA9534_REG_OUTPUT, pin, level); + return pca9534_pin_write(port, addr_flags, PCA9534_REG_OUTPUT, pin, + level); } -int pca9534_config_pin(const int port, const uint16_t addr_flags, - int pin, int is_input) +int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin, + int is_input) { - return pca9534_pin_write(port, addr_flags, - PCA9534_REG_CONFIG, pin, is_input); + return pca9534_pin_write(port, addr_flags, PCA9534_REG_CONFIG, pin, + is_input); } -- cgit v1.2.1 From 504e8f3ac367c2b956e5964808a14c1ba492e62d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:38 -0600 Subject: util/comm-usb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62a14f04a49f691d654870be34c960372c7a6323 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730608 Reviewed-by: Jeremy Bettis --- util/comm-usb.c | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/util/comm-usb.c b/util/comm-usb.c index 9b362aa2f4..43ad95648f 100644 --- a/util/comm-usb.c +++ b/util/comm-usb.c @@ -17,9 +17,9 @@ #include "misc_util.h" #include "usb_descriptor.h" -#define USB_ERROR(m, r) \ - fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \ - m, r, libusb_strerror(r)) +#define USB_ERROR(m, r) \ + fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \ + r, libusb_strerror(r)) #ifdef DEBUG #define debug(fmt, arg...) printf("%s:%d: " fmt, __FILE__, __LINE__, ##arg) @@ -58,14 +58,12 @@ void comm_usb_exit(void) static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf, int inlen, int allow_less) { - int r, actual; /* Send data out */ if (outbuf && outlen) { actual = 0; - r = libusb_bulk_transfer(uep->devh, uep->ep_num, - outbuf, outlen, + r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen, &actual, 2000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); @@ -83,8 +81,7 @@ static int do_xfer(struct usb_endpoint *uep, void *outbuf, int outlen, if (inbuf && inlen) { actual = 0; r = libusb_bulk_transfer(uep->devh, uep->ep_num | USB_DIR_IN, - inbuf, inlen, - &actual, 5000); + inbuf, inlen, &actual, 5000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); return r; @@ -161,9 +158,8 @@ int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr) return 1; } -static libusb_device_handle *check_device(libusb_device *dev, - uint16_t vid, uint16_t pid, - char *serialno) +static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid, + uint16_t pid, char *serialno) { struct libusb_device_descriptor desc; libusb_device_handle *handle = NULL; @@ -181,7 +177,9 @@ static libusb_device_handle *check_device(libusb_device *dev, if (desc.iSerialNumber) { r = libusb_get_string_descriptor_ascii(handle, - desc.iSerialNumber, (unsigned char *)sn, sizeof(sn)); + desc.iSerialNumber, + (unsigned char *)sn, + sizeof(sn)); if (r > 0) snvalid = 1; } @@ -196,8 +194,8 @@ static libusb_device_handle *check_device(libusb_device *dev, return handle; } -static int find_endpoint(uint16_t vid, uint16_t pid, - char *serialno, struct usb_endpoint *uep) +static int find_endpoint(uint16_t vid, uint16_t pid, char *serialno, + struct usb_endpoint *uep) { int iface_num, r, i; libusb_device **devs; @@ -244,8 +242,8 @@ static int find_endpoint(uint16_t vid, uint16_t pid, return -1; } - debug("Found interface %d endpoint=%d, chunk_len=%d\n", - iface_num, uep->ep_num, uep->chunk_len); + debug("Found interface %d endpoint=%d, chunk_len=%d\n", iface_num, + uep->ep_num, uep->chunk_len); libusb_set_auto_detach_kernel_driver(uep->devh, 1); r = libusb_claim_interface(uep->devh, iface_num); @@ -270,9 +268,8 @@ static int sum_bytes(const void *data, int length) return sum; } -static int ec_command_usb(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_usb(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { struct ec_host_request *req; struct ec_host_response *res; @@ -289,7 +286,7 @@ static int ec_command_usb(int command, int version, if (req == NULL || res == NULL) goto out; - req->struct_version = EC_HOST_REQUEST_VERSION; /* 3 */ + req->struct_version = EC_HOST_REQUEST_VERSION; /* 3 */ req->checksum = 0; req->command = command; req->command_version = version; @@ -338,4 +335,3 @@ int comm_init_usb(uint16_t vid, uint16_t pid) return 0; } - -- cgit v1.2.1 From 1304d4ad8a29ae4f756078eb215719aa62610960 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:17 -0600 Subject: board/atlas/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9e476f5a1b10821846c7e461c1920e3341aa167 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727995 Reviewed-by: Jeremy Bettis --- board/atlas/board.h | 120 +++++++++++++++++++++++++--------------------------- 1 file changed, 58 insertions(+), 62 deletions(-) diff --git a/board/atlas/board.h b/board/atlas/board.h index c3ddafe2cb..6937b5d434 100644 --- a/board/atlas/board.h +++ b/board/atlas/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -147,29 +147,29 @@ #define CONFIG_USBC_VCONN_SWAP /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define CONFIG_HIBERNATE_PSL /* Enable PSL pins for wakeup */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define CONFIG_HIBERNATE_PSL /* Enable PSL pins for wakeup */ /* I2C ports */ -#define I2C_PORT_POWER NPCX_I2C_PORT0_0 /* pmic/charger */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT3_0 /* als */ -#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1 -#define I2C_PORT_GYRO NPCX_I2C_PORT5_0 /* accel/gyro */ - -#define I2C_PORT_ACCEL I2C_PORT_GYRO -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_PMIC I2C_PORT_POWER -#define I2C_PORT_THERMAL I2C_PORT_POWER +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 /* pmic/charger */ +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT3_0 /* als */ +#define I2C_PORT_BATTERY NPCX_I2C_PORT4_1 +#define I2C_PORT_GYRO NPCX_I2C_PORT5_0 /* accel/gyro */ + +#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_PMIC I2C_PORT_POWER +#define I2C_PORT_THERMAL I2C_PORT_POWER /* I2C addresses */ -#define I2C_ADDR_TCPC_FLAGS 0x0B -#define I2C_ADDR_MP2949_FLAGS 0x20 -#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_TCPC_FLAGS 0x0B +#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_BD99992_FLAGS 0x30 #ifndef __ASSEMBLER__ @@ -177,11 +177,11 @@ #include "registers.h" enum temp_sensor_id { - TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ - TEMP_SENSOR_SYSTHERM0, /* BD99992GW SYSTHERM0 */ - TEMP_SENSOR_SYSTHERM1, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_SYSTHERM2, /* BD99992GW SYSTHERM2 */ - TEMP_SENSOR_SYSTHERM3, /* BD99992GW SYSTHERM3 */ + TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ + TEMP_SENSOR_SYSTHERM0, /* BD99992GW SYSTHERM0 */ + TEMP_SENSOR_SYSTHERM1, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_SYSTHERM2, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_SYSTHERM3, /* BD99992GW SYSTHERM3 */ TEMP_SENSOR_COUNT }; @@ -202,28 +202,24 @@ enum sensor_id { }; /* LID_ALS needs to be polled */ -#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS) +#define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ALS) -enum adc_channel { - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ int board_get_version(void); @@ -236,33 +232,33 @@ void board_reset_pd_mcu(void); * vs. names hard-coded in various parts of the EC codebase. */ -#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK -#define GPIO_BATTERY_PRESENT_L GPIO_EC_BATT_PRES_L -#define GPIO_BOARD_VERSION1 GPIO_EC_BRD_ID1 -#define GPIO_BOARD_VERSION2 GPIO_EC_BRD_ID2 -#define GPIO_BOARD_VERSION3 GPIO_EC_BRD_ID3 -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KB_ROW02_INV -#define GPIO_PCH_ACOK GPIO_EC_PCH_ACPRESENT -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L -#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L -#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC -#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT -#define GPIO_USB_C0_PD_RST_L GPIO_USB_PD_RST_L -#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT -#define GPIO_USB_C1_PD_RST_L GPIO_USB_PD_RST_L -#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK +#define GPIO_BATTERY_PRESENT_L GPIO_EC_BATT_PRES_L +#define GPIO_BOARD_VERSION1 GPIO_EC_BRD_ID1 +#define GPIO_BOARD_VERSION2 GPIO_EC_BRD_ID2 +#define GPIO_BOARD_VERSION3 GPIO_EC_BRD_ID3 +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KB_ROW02_INV +#define GPIO_PCH_ACOK GPIO_EC_PCH_ACPRESENT +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_RSMRST_L +#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_L +#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK_EC +#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT +#define GPIO_USB_C0_PD_RST_L GPIO_USB_PD_RST_L +#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT +#define GPIO_USB_C1_PD_RST_L GPIO_USB_PD_RST_L +#define GPIO_WP_L GPIO_EC_WP_L /* ps8751 requires 1ms reset down assertion */ -#define PS8XXX_RST_L_RST_H_DELAY_MS 1 +#define PS8XXX_RST_L_RST_H_DELAY_MS 1 -#define ATLAS_REV_FIXED_EC_WP 4 +#define ATLAS_REV_FIXED_EC_WP 4 #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 2d3d9d531558354a9c0e445674438f3dee50c299 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:30 -0600 Subject: include/panic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I781b4eef6495d27f141f2eab836afb7030a5d59f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730376 Reviewed-by: Jeremy Bettis --- include/panic.h | 56 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/include/panic.h b/include/panic.h index 6e4f17fcb9..fa6e8d7027 100644 --- a/include/panic.h +++ b/include/panic.h @@ -66,21 +66,21 @@ struct cortex_panic_data { /* NDS32 N8 registers saved on panic */ struct nds32_n8_panic_data { uint32_t itype; - uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */ + uint32_t regs[16]; /* r0-r10, r15, fp, gp, lp, sp */ uint32_t ipc; uint32_t ipsw; }; /* RISC-V RV32I registers saved on panic */ struct rv32i_panic_data { - uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */ - uint32_t mepc; /* mepc */ - uint32_t mcause; /* mcause */ + uint32_t regs[31]; /* sp, ra, gp, tp, a0-a7, t0-t6, s0-s11 */ + uint32_t mepc; /* mepc */ + uint32_t mcause; /* mcause */ }; /* x86 registers saved on panic */ struct x86_panic_data { - uint32_t vector; /* Exception vector number */ + uint32_t vector; /* Exception vector number */ /* Data pushed when exception handler called */ uint32_t error_code; @@ -102,18 +102,18 @@ struct x86_panic_data { /* Data saved across reboots */ struct panic_data { - uint8_t arch; /* Architecture (PANIC_ARCH_*) */ - uint8_t struct_version; /* Structure version (currently 2) */ - uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */ - uint8_t reserved; /* Reserved; set 0 */ + uint8_t arch; /* Architecture (PANIC_ARCH_*) */ + uint8_t struct_version; /* Structure version (currently 2) */ + uint8_t flags; /* Flags (PANIC_DATA_FLAG_*) */ + uint8_t reserved; /* Reserved; set 0 */ /* core specific panic data */ union { - struct cortex_panic_data cm; /* Cortex-Mx registers */ + struct cortex_panic_data cm; /* Cortex-Mx registers */ struct nds32_n8_panic_data nds_n8; /* NDS32 N8 registers */ - struct x86_panic_data x86; /* Intel x86 */ + struct x86_panic_data x86; /* Intel x86 */ #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA - struct rv32i_panic_data riscv; /* RISC-V RV32I */ + struct rv32i_panic_data riscv; /* RISC-V RV32I */ #endif }; @@ -121,21 +121,21 @@ struct panic_data { * These fields go at the END of the struct so we can find it at the * end of memory. */ - uint32_t struct_size; /* Size of this struct */ - uint32_t magic; /* PANIC_SAVE_MAGIC if valid */ + uint32_t struct_size; /* Size of this struct */ + uint32_t magic; /* PANIC_SAVE_MAGIC if valid */ }; #ifdef CONFIG_RO_PANIC_DATA_SIZE BUILD_ASSERT(sizeof(struct panic_data) == CONFIG_RO_PANIC_DATA_SIZE); #endif -#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */ +#define PANIC_DATA_MAGIC 0x21636e50 /* "Pnc!" */ enum panic_arch { - PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */ - PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */ - PANIC_ARCH_X86 = 3, /* Intel x86 */ + PANIC_ARCH_CORTEX_M = 1, /* Cortex-M architecture */ + PANIC_ARCH_NDS32_N8 = 2, /* NDS32 N8 architecture */ + PANIC_ARCH_X86 = 3, /* Intel x86 */ #ifndef CONFIG_DO_NOT_INCLUDE_RV32I_PANIC_DATA - PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */ + PANIC_ARCH_RISCV_RV32I = 4, /* RISC-V RV32I */ #endif }; @@ -144,13 +144,13 @@ enum panic_arch { /* Flags for panic_data.flags */ /* panic_data.frame is valid */ -#define PANIC_DATA_FLAG_FRAME_VALID BIT(0) +#define PANIC_DATA_FLAG_FRAME_VALID BIT(0) /* Already printed at console */ -#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1) +#define PANIC_DATA_FLAG_OLD_CONSOLE BIT(1) /* Already returned via host command */ -#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2) +#define PANIC_DATA_FLAG_OLD_HOSTCMD BIT(2) /* Already reported via host event */ -#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3) +#define PANIC_DATA_FLAG_OLD_HOSTEVENT BIT(3) /** * Write a string to the panic reporting device @@ -170,8 +170,8 @@ void panic_puts(const char *s); * @param format printf-style format string * @param ... Arguments to process */ -__attribute__((__format__(__printf__, 1, 2))) -void panic_printf(const char *format, ...); +__attribute__((__format__(__printf__, 1, 2))) void +panic_printf(const char *format, ...); /* * Print saved panic information @@ -254,8 +254,8 @@ void ignore_bus_fault(int ignored); * Return a pointer to the saved data from a previous panic that can be * safely interpreted * - * @param pointer to the valid panic data, or NULL if none available (for example, - * the last reboot was not caused by a panic). + * @param pointer to the valid panic data, or NULL if none available (for + * example, the last reboot was not caused by a panic). */ struct panic_data *panic_get_data(void); @@ -294,4 +294,4 @@ void chip_panic_data_backup(void); } #endif -#endif /* __CROS_EC_PANIC_H */ +#endif /* __CROS_EC_PANIC_H */ -- cgit v1.2.1 From 6674437cd1bf168e6502df6b5ab238f65e44167e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:52 -0600 Subject: chip/mchp/port80.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f5ad8811d7d9f2c7fe23579550c45675785598e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729297 Reviewed-by: Jeremy Bettis --- chip/mchp/port80.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c index a32dc1b9c2..cb36683065 100644 --- a/chip/mchp/port80.c +++ b/chip/mchp/port80.c @@ -14,7 +14,6 @@ #include "task.h" #include "tfdp_chip.h" - #if defined(CHIP_FAMILY_MEC172X) /* * MEC172x family implements a new Port 0x80 capture block. -- cgit v1.2.1 From e9c9296077fc4c27f72fd94e8d6a6d8fd936b1d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:56 -0600 Subject: driver/touchpad_st.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9661624459f2d345dc2083af7acf35bab2fcfd17 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730150 Reviewed-by: Jeremy Bettis --- driver/touchpad_st.h | 211 +++++++++++++++++++++++++-------------------------- 1 file changed, 103 insertions(+), 108 deletions(-) diff --git a/driver/touchpad_st.h b/driver/touchpad_st.h index ef0960591b..a34e6f1c8c 100644 --- a/driver/touchpad_st.h +++ b/driver/touchpad_st.h @@ -10,71 +10,69 @@ #include "common.h" -#define ST_VENDOR_ID 0x0483 +#define ST_VENDOR_ID 0x0483 -#define ST_TP_EXTRA_BYTE 1 +#define ST_TP_EXTRA_BYTE 1 -#define ST_TP_CMD_READ_ALL_EVENTS 0x87 -#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT 0xA0 -#define ST_TP_CMD_WRITE_FEATURE_SELECT 0xA2 -#define ST_TP_CMD_WRITE_SYSTEM_COMMAND 0xA4 -#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY 0xA6 -#define ST_TP_CMD_READ_HOST_DATA_MEMORY 0xA7 -#define ST_TP_CMD_WRITE_FW_CONFIG 0xA8 -#define ST_TP_CMD_READ_FW_CONFIG 0xA9 -#define ST_TP_CMD_SPI_HOST_BUFFER_ACK 0xC0 -#define ST_TP_CMD_READ_SPI_HOST_BUFFER 0xC1 +#define ST_TP_CMD_READ_ALL_EVENTS 0x87 +#define ST_TP_CMD_WRITE_SCAN_MODE_SELECT 0xA0 +#define ST_TP_CMD_WRITE_FEATURE_SELECT 0xA2 +#define ST_TP_CMD_WRITE_SYSTEM_COMMAND 0xA4 +#define ST_TP_CMD_WRITE_HOST_DATA_MEMORY 0xA6 +#define ST_TP_CMD_READ_HOST_DATA_MEMORY 0xA7 +#define ST_TP_CMD_WRITE_FW_CONFIG 0xA8 +#define ST_TP_CMD_READ_FW_CONFIG 0xA9 +#define ST_TP_CMD_SPI_HOST_BUFFER_ACK 0xC0 +#define ST_TP_CMD_READ_SPI_HOST_BUFFER 0xC1 -#define ST_TP_CMD_WRITE_HW_REG 0xFA -#define ST_TP_CMD_READ_HW_REG 0xFB +#define ST_TP_CMD_WRITE_HW_REG 0xFA +#define ST_TP_CMD_READ_HW_REG 0xFB /* Max number of bytes that the DMA can burn on the flash in one shot in FTI */ -#define ST_TP_FLASH_BUFFER_SIZE (64 * 1024) +#define ST_TP_FLASH_BUFFER_SIZE (64 * 1024) /* Max number of bytes that can be written in I2C to the DMA */ -#define ST_TP_DMA_CHUNK_SIZE 32 +#define ST_TP_DMA_CHUNK_SIZE 32 -#define ST_HOST_BUFFER_DATA_VALID BIT(0) -#define ST_HOST_BUFFER_MT_READY BIT(3) -#define ST_HOST_BUFFER_SF_READY BIT(4) -#define ST_HOST_BUFFER_SS_READY BIT(5) +#define ST_HOST_BUFFER_DATA_VALID BIT(0) +#define ST_HOST_BUFFER_MT_READY BIT(3) +#define ST_HOST_BUFFER_SF_READY BIT(4) +#define ST_HOST_BUFFER_SS_READY BIT(5) -#define ST_TP_SCAN_MODE_ACTIVE 0x00 -#define ST_TP_SCAN_MODE_LOW_POWER 0x01 -#define ST_TP_SCAN_MODE_TUNING_WIZARD 0x02 -#define ST_TP_SCAN_MODE_LOCKED 0x03 +#define ST_TP_SCAN_MODE_ACTIVE 0x00 +#define ST_TP_SCAN_MODE_LOW_POWER 0x01 +#define ST_TP_SCAN_MODE_TUNING_WIZARD 0x02 +#define ST_TP_SCAN_MODE_LOCKED 0x03 -#define ST_TOUCH_ROWS (18) /* force len */ -#define ST_TOUCH_COLS (25) /* sense len */ +#define ST_TOUCH_ROWS (18) /* force len */ +#define ST_TOUCH_COLS (25) /* sense len */ -#define ST_TOUCH_HEADER_SIZE 32 +#define ST_TOUCH_HEADER_SIZE 32 -#define BYTES_PER_PIXEL 1 +#define BYTES_PER_PIXEL 1 /* Number of bits per pixel, this value is decided by experiments. */ -#define BITS_PER_PIXEL 8 +#define BITS_PER_PIXEL 8 -#define ST_TOUCH_FRAME_SIZE (ST_TOUCH_ROWS * ST_TOUCH_COLS * \ - BYTES_PER_PIXEL) -#define ST_TOUCH_FORCE_SIZE (ST_TOUCH_ROWS * BYTES_PER_PIXEL) -#define ST_TOUCH_SENSE_SIZE (ST_TOUCH_COLS * BYTES_PER_PIXEL) +#define ST_TOUCH_FRAME_SIZE (ST_TOUCH_ROWS * ST_TOUCH_COLS * BYTES_PER_PIXEL) +#define ST_TOUCH_FORCE_SIZE (ST_TOUCH_ROWS * BYTES_PER_PIXEL) +#define ST_TOUCH_SENSE_SIZE (ST_TOUCH_COLS * BYTES_PER_PIXEL) -#define ST_TP_MEM_ID_SYSTEM_INFO 0x01 - -#define ST_TP_FLASH_OFFSET_CODE (0x0000 << 2) -#define ST_TP_FLASH_OFFSET_PANEL_CFG (0x6800 << 2) -#define ST_TP_FLASH_OFFSET_CX (0x7000 << 2) -#define ST_TP_FLASH_OFFSET_CONFIG (0x7C00 << 2) +#define ST_TP_MEM_ID_SYSTEM_INFO 0x01 +#define ST_TP_FLASH_OFFSET_CODE (0x0000 << 2) +#define ST_TP_FLASH_OFFSET_PANEL_CFG (0x6800 << 2) +#define ST_TP_FLASH_OFFSET_CX (0x7000 << 2) +#define ST_TP_FLASH_OFFSET_CONFIG (0x7C00 << 2) struct st_tp_host_data_header_t { -#define ST_TP_HEADER_MAGIC 0xA5 - uint8_t magic; /* this should always be ST_TP_HEADER_MAGIC */ +#define ST_TP_HEADER_MAGIC 0xA5 + uint8_t magic; /* this should always be ST_TP_HEADER_MAGIC */ uint8_t host_data_mem_id; uint16_t count; } __packed; /* Compute offset of end of a member in given type */ -#define endof(type, member) (offsetof(type, member) + \ - sizeof(((type *)NULL)->member)) +#define endof(type, member) \ + (offsetof(type, member) + sizeof(((type *)NULL)->member)) struct st_tp_system_info_t { /* Part 1, basic info */ @@ -83,7 +81,7 @@ struct st_tp_system_info_t { uint8_t api_ver_minor; uint8_t api_ver_major; uint16_t chip0_ver; - uint8_t chip0_id[2]; /* should be 0x3936 */ + uint8_t chip0_id[2]; /* should be 0x3936 */ uint16_t chip1_ver; uint16_t chip1_id; uint16_t fw_ver; @@ -101,7 +99,7 @@ struct st_tp_system_info_t { uint32_t fw_crc; uint32_t cfg_crc; #define ST_TP_SYSTEM_INFO_PART_1_SIZE endof(struct st_tp_system_info_t, cfg_crc) -#define ST_TP_SYSTEM_INFO_PART_1_RESERVED 16 +#define ST_TP_SYSTEM_INFO_PART_1_RESERVED 16 uint16_t scr_res_x; uint16_t scr_res_y; @@ -109,20 +107,18 @@ struct st_tp_system_info_t { uint8_t scr_rx_len; uint8_t key_len; uint8_t frc_len; -#define ST_TP_SYSTEM_INFO_PART_2_SIZE (endof(struct st_tp_system_info_t, \ - frc_len) - \ - offsetof(struct st_tp_system_info_t, \ - scr_res_x)) -#define ST_TP_SYSTEM_INFO_PART_2_RESERVED 40 +#define ST_TP_SYSTEM_INFO_PART_2_SIZE \ + (endof(struct st_tp_system_info_t, frc_len) - \ + offsetof(struct st_tp_system_info_t, scr_res_x)) +#define ST_TP_SYSTEM_INFO_PART_2_RESERVED 40 -#if 0 /* the following parts are defined in spec, but not currently used. */ +#if 0 /* the following parts are defined in spec, but not currently used. */ uint16_t dbg_frame_addr; -#define ST_TP_SYSTEM_INFO_PART_3_SIZE (endof(struct st_tp_system_info_t, \ - dbg_frame_addr) - \ - offsetof(struct st_tp_system_info_t, \ - dbg_frame_addr)) -#define ST_TP_SYSTEM_INFO_PART_3_RESERVED 6 +#define ST_TP_SYSTEM_INFO_PART_3_SIZE \ + (endof(struct st_tp_system_info_t, dbg_frame_addr) - \ + offsetof(struct st_tp_system_info_t, dbg_frame_addr)) +#define ST_TP_SYSTEM_INFO_PART_3_RESERVED 6 uint16_t ms_scr_raw_addr; uint16_t ms_scr_filter_addr; @@ -160,24 +156,23 @@ struct st_tp_system_info_t { uint16_t ss_prx_rx_filter_addr; uint16_t ss_prx_rx_str_addr; uint16_t ss_prx_rx_bl_addr; -#define ST_TP_SYSTEM_INFO_PART_4_SIZE (endof(struct st_tp_system_info_t, \ - ss_prx_rx_bl_addr) - \ - offsetof(struct st_tp_system_info_t, \ - ms_scr_raw_addr)) -#endif /* if 0 */ +#define ST_TP_SYSTEM_INFO_PART_4_SIZE \ + (endof(struct st_tp_system_info_t, ss_prx_rx_bl_addr) - \ + offsetof(struct st_tp_system_info_t, ms_scr_raw_addr)) +#endif /* if 0 */ } __packed; -#define ST_TP_SYSTEM_INFO_LEN (sizeof(struct st_tp_system_info_t) + \ - ST_TP_SYSTEM_INFO_PART_1_RESERVED) +#define ST_TP_SYSTEM_INFO_LEN \ + (sizeof(struct st_tp_system_info_t) + ST_TP_SYSTEM_INFO_PART_1_RESERVED) struct st_tp_host_buffer_header_t { -#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0) -#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1) -#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4) -#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5) -#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6) +#define ST_TP_BUFFER_HEADER_DATA_VALID BIT(0) +#define ST_TP_BUFFER_HEADER_EVT_FIFO_NOT_EMPTY BIT(1) +#define ST_TP_BUFFER_HEADER_SYS_FAULT BIT(2) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_MT_RDY BIT(3) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SF_RDY BIT(4) +#define ST_TP_BUFFER_HEADER_HEAT_MAP_SS_RDY BIT(5) +#define ST_TP_BUFFER_HEADER_DOMESWITCH_LVL BIT(6) uint8_t flags; uint8_t reserved[3]; uint8_t heatmap_miss_count; @@ -187,56 +182,56 @@ struct st_tp_host_buffer_header_t { struct st_tp_host_buffer_heat_map_t { uint8_t frame[ST_TOUCH_FRAME_SIZE]; -#if 0 /* we are not using these now */ +#if 0 /* we are not using these now */ uint8_t force[ST_TOUCH_FORCE_SIZE]; uint8_t sense[ST_TOUCH_SENSE_SIZE]; #endif } __packed; struct st_tp_event_t { -#define ST_TP_EVENT_MAGIC 0x3 - unsigned magic:2; /* should always be 0x3 */ - unsigned major_high:2; -#define ST_TP_EVENT_ID_CONTROLLER_READY 0x0 -#define ST_TP_EVENT_ID_ENTER_POINTER 0x1 -#define ST_TP_EVENT_ID_MOTION_POINTER 0x2 -#define ST_TP_EVENT_ID_LEAVE_POINTER 0x3 -#define ST_TP_EVENT_ID_STATUS_REPORT 0x4 -#define ST_TP_EVENT_ID_USER_REPORT 0x5 -#define ST_TP_EVENT_ID_DEBUG_REPORT 0xe -#define ST_TP_EVENT_ID_ERROR_REPORT 0xf - unsigned evt_id:4; +#define ST_TP_EVENT_MAGIC 0x3 + unsigned magic : 2; /* should always be 0x3 */ + unsigned major_high : 2; +#define ST_TP_EVENT_ID_CONTROLLER_READY 0x0 +#define ST_TP_EVENT_ID_ENTER_POINTER 0x1 +#define ST_TP_EVENT_ID_MOTION_POINTER 0x2 +#define ST_TP_EVENT_ID_LEAVE_POINTER 0x3 +#define ST_TP_EVENT_ID_STATUS_REPORT 0x4 +#define ST_TP_EVENT_ID_USER_REPORT 0x5 +#define ST_TP_EVENT_ID_DEBUG_REPORT 0xe +#define ST_TP_EVENT_ID_ERROR_REPORT 0xf + unsigned evt_id : 4; union { struct { -#define ST_TP_TOUCH_TYPE_INVALID 0x0 -#define ST_TP_TOUCH_TYPE_FINGER 0x1 -#define ST_TP_TOUCH_TYPE_GLOVE 0x2 -#define ST_TP_TOUCH_TYPE_STYLUS 0x3 -#define ST_TP_TOUCH_TYPE_PALM 0x4 - unsigned touch_type:4; - unsigned touch_id:4; - unsigned y:12; - unsigned x:12; +#define ST_TP_TOUCH_TYPE_INVALID 0x0 +#define ST_TP_TOUCH_TYPE_FINGER 0x1 +#define ST_TP_TOUCH_TYPE_GLOVE 0x2 +#define ST_TP_TOUCH_TYPE_STYLUS 0x3 +#define ST_TP_TOUCH_TYPE_PALM 0x4 + unsigned touch_type : 4; + unsigned touch_id : 4; + unsigned y : 12; + unsigned x : 12; uint8_t z; - uint8_t minor:4; // need to be concat with minor_high - uint8_t major:4; // need to be concat with major_high + uint8_t minor : 4; // need to be concat with minor_high + uint8_t major : 4; // need to be concat with major_high } __packed finger; struct { -#define ST_TP_STATUS_CMD_ECHO 0x1 -#define ST_TP_STATUS_FRAME_DROP 0x3 -#define ST_TP_STATUS_FCAL 0x5 -#define ST_TP_STATUS_BEACON 0x9 +#define ST_TP_STATUS_CMD_ECHO 0x1 +#define ST_TP_STATUS_FRAME_DROP 0x3 +#define ST_TP_STATUS_FCAL 0x5 +#define ST_TP_STATUS_BEACON 0x9 uint8_t report_type; uint8_t info[4]; uint8_t reserved; } __packed report; - } __packed ; /* anonymous */ + } __packed; /* anonymous */ - unsigned minor_high:2; - unsigned reserved:1; - unsigned evt_left:5; + unsigned minor_high : 2; + unsigned reserved : 1; + unsigned evt_left : 5; } __packed; struct st_tp_fw_header_t { @@ -258,12 +253,12 @@ enum ST_TP_MODE { HEAT_MAP_MODE, }; -#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD 0x00 -#define ST_TP_DEBUG_CMD_CALIBRATE 0x01 -#define ST_TP_DEBUG_CMD_START_SCAN 0x02 -#define ST_TP_DEBUG_CMD_STOP_SCAN 0x03 -#define ST_TP_DEBUG_CMD_READ_BUF_HEADER 0x04 -#define ST_TP_DEBUG_CMD_READ_EVENTS 0x05 +#define ST_TP_DEBUG_CMD_RESET_TOUCHPAD 0x00 +#define ST_TP_DEBUG_CMD_CALIBRATE 0x01 +#define ST_TP_DEBUG_CMD_START_SCAN 0x02 +#define ST_TP_DEBUG_CMD_STOP_SCAN 0x03 +#define ST_TP_DEBUG_CMD_READ_BUF_HEADER 0x04 +#define ST_TP_DEBUG_CMD_READ_EVENTS 0x05 #define ST_TP_HEAT_MAP_THRESHOLD 10 -- cgit v1.2.1 From 19f4e88afaaec98586b03df6141ca6ff9ec7ed97 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:39 -0600 Subject: board/anahera/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87cb545f8aaa7a742896dc6764496fc43563ba6f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727989 Reviewed-by: Jeremy Bettis --- board/anahera/led.c | 67 ++++++++++++++++++++++++++++------------------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/board/anahera/led.c b/board/anahera/led.c index ce172c7b1e..b72fc45e2c 100644 --- a/board/anahera/led.c +++ b/board/anahera/led.c @@ -26,15 +26,13 @@ #define BATT_LOW_BCT 10 #define LED_TICK_INTERVAL_MS (500 * MSEC) -#define LED_CYCLE_TIME_MS (2000 * MSEC) -#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) -#define LED_ON_TIME_MS (1000 * MSEC) -#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED -}; +#define LED_CYCLE_TIME_MS (2000 * MSEC) +#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1000 * MSEC) +#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -42,22 +40,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LEFT_PORT = 0, - RIGHT_PORT -}; +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; static void led_set_color_battery(int port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L : - GPIO_C0_CHARGE_LED_AMBER_L); + GPIO_C0_CHARGE_LED_AMBER_L); white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L : - GPIO_C0_CHARGE_LED_WHITE_L); + GPIO_C0_CHARGE_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -129,10 +124,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -155,31 +150,39 @@ static void led_set_battery(void) */ if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < BATT_LOW_BCT) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { if (charge_get_percent() < BATT_LOW_BCT) - led_set_color_battery(LEFT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + LEFT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(LEFT_PORT, LED_OFF); } break; case PWR_STATE_ERROR: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { - led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ? + LED_AMBER : + LED_OFF); } break; case PWR_STATE_CHARGE_NEAR_FULL: @@ -187,9 +190,11 @@ static void led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From b21c4d3faccf373a65b6f11458f6ed0594c8026d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:14 -0600 Subject: power/rk3399.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb2a1d26359d9138d1aaccce434450c00dc92d01 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730466 Reviewed-by: Jeremy Bettis --- power/rk3399.c | 140 +++++++++++++++++++++++++-------------------------------- 1 file changed, 61 insertions(+), 79 deletions(-) diff --git a/power/rk3399.c b/power/rk3399.c index e0ea7ee483..ec034e2168 100644 --- a/power/rk3399.c +++ b/power/rk3399.c @@ -30,46 +30,46 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Input state flags */ #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1 - #define IN_PGOOD_PP1250_S3 POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD) - #define IN_PGOOD_PP900_S0 POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD) +#define IN_PGOOD_PP1250_S3 POWER_SIGNAL_MASK(PP1250_S3_PWR_GOOD) +#define IN_PGOOD_PP900_S0 POWER_SIGNAL_MASK(PP900_S0_PWR_GOOD) #else - #define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(PP5000_PWR_GOOD) - #define IN_PGOOD_SYS POWER_SIGNAL_MASK(SYS_PWR_GOOD) +#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(PP5000_PWR_GOOD) +#define IN_PGOOD_SYS POWER_SIGNAL_MASK(SYS_PWR_GOOD) #endif -#define IN_PGOOD_AP POWER_SIGNAL_MASK(AP_PWR_GOOD) -#define IN_SUSPEND_DEASSERTED POWER_SIGNAL_MASK(SUSPEND_DEASSERTED) +#define IN_PGOOD_AP POWER_SIGNAL_MASK(AP_PWR_GOOD) +#define IN_SUSPEND_DEASSERTED POWER_SIGNAL_MASK(SUSPEND_DEASSERTED) /* Rails requires for S3 and S0 */ #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1 - #define IN_PGOOD_S3 (IN_PGOOD_PP1250_S3) - #define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP) - /* This board can optionally wake-on-USB in S3 */ - #define S3_USB_WAKE - /* This board has non-INT power signal pins */ - #define POWER_SIGNAL_POLLING - /* This board supports CR50 deep sleep mode */ - #define CR50_DEEP_SLEEP - /* - * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the - * signal every 5ms, up to 200 times (~ 1 second timeout). - */ - #define PGOOD_S0_POLL_TIMEOUT (5 * MSEC) - #define PGOOD_S0_POLL_TRIES 200 +#define IN_PGOOD_S3 (IN_PGOOD_PP1250_S3) +#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_PP900_S0 | IN_PGOOD_AP) +/* This board can optionally wake-on-USB in S3 */ +#define S3_USB_WAKE +/* This board has non-INT power signal pins */ +#define POWER_SIGNAL_POLLING +/* This board supports CR50 deep sleep mode */ +#define CR50_DEEP_SLEEP +/* + * If AP_PWR_GOOD assertion does not trigger an interrupt, poll the + * signal every 5ms, up to 200 times (~ 1 second timeout). + */ +#define PGOOD_S0_POLL_TIMEOUT (5 * MSEC) +#define PGOOD_S0_POLL_TRIES 200 #else - #define IN_PGOOD_S3 (IN_PGOOD_PP5000) - #define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS) +#define IN_PGOOD_S3 (IN_PGOOD_PP5000) +#define IN_PGOOD_S0 (IN_PGOOD_S3 | IN_PGOOD_AP | IN_PGOOD_SYS) #endif /* All inputs in the right state for S0 */ -#define IN_ALL_S0 (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED) +#define IN_ALL_S0 (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED) /* Long power key press to force shutdown in S0 */ -#define FORCED_SHUTDOWN_DELAY (8 * SECOND) +#define FORCED_SHUTDOWN_DELAY (8 * SECOND) #define CHARGER_INITIALIZED_DELAY_MS 100 #define CHARGER_INITIALIZED_TRIES 40 @@ -126,12 +126,9 @@ static const struct power_seq_op s3s0_power_seq[] = { }; #else static const struct power_seq_op s3s0_power_seq[] = { - { GPIO_PPVAR_CLOGIC_EN, 1, 2 }, - { GPIO_PP900_DDRPLL_EN, 1, 2 }, - { GPIO_PP1800_AP_AVDD_EN_L, 0, 2 }, - { GPIO_AP_CORE_EN, 1, 2 }, - { GPIO_PP1800_S0_EN_L, 0, 2 }, - { GPIO_PP3300_S0_EN_L, 0, 0 }, + { GPIO_PPVAR_CLOGIC_EN, 1, 2 }, { GPIO_PP900_DDRPLL_EN, 1, 2 }, + { GPIO_PP1800_AP_AVDD_EN_L, 0, 2 }, { GPIO_AP_CORE_EN, 1, 2 }, + { GPIO_PP1800_S0_EN_L, 0, 2 }, { GPIO_PP3300_S0_EN_L, 0, 0 }, }; #endif @@ -151,12 +148,9 @@ static const struct power_seq_op s0s3_power_seq[] = { }; #else static const struct power_seq_op s0s3_power_seq[] = { - { GPIO_PP3300_S0_EN_L, 1, 20 }, - { GPIO_PP1800_S0_EN_L, 1, 1 }, - { GPIO_AP_CORE_EN, 0, 20 }, - { GPIO_PP1800_AP_AVDD_EN_L, 1, 1 }, - { GPIO_PP900_DDRPLL_EN, 0, 1 }, - { GPIO_PPVAR_CLOGIC_EN, 0, 0 }, + { GPIO_PP3300_S0_EN_L, 1, 20 }, { GPIO_PP1800_S0_EN_L, 1, 1 }, + { GPIO_AP_CORE_EN, 0, 20 }, { GPIO_PP1800_AP_AVDD_EN_L, 1, 1 }, + { GPIO_PP900_DDRPLL_EN, 0, 1 }, { GPIO_PPVAR_CLOGIC_EN, 0, 0 }, }; #endif @@ -173,28 +167,19 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = { /* The power sequence for POWER_S3S5 */ #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1 static const struct power_seq_op s3s5_power_seq[] = { - { GPIO_SYS_RST_L, 0, 0 }, - { GPIO_PP1250_S3_EN, 0, 2 }, - { GPIO_PP1800_S3_EN, 0, 2 }, - { GPIO_PP3300_S3_EN, 0, 2 }, + { GPIO_SYS_RST_L, 0, 0 }, { GPIO_PP1250_S3_EN, 0, 2 }, + { GPIO_PP1800_S3_EN, 0, 2 }, { GPIO_PP3300_S3_EN, 0, 2 }, { GPIO_PP900_S3_EN, 0, 0 }, }; #else static const struct power_seq_op s3s5_power_seq[] = { - { GPIO_PP1800_SENSOR_EN_L, 1, 0}, - { GPIO_PP1800_SIXAXIS_EN_L, 1, 0}, - { GPIO_PP1800_LID_EN_L, 1, 0 }, - { GPIO_PP3300_TRACKPAD_EN_L, 1, 0 }, - { GPIO_PP5000_EN, 0, 0 }, - { GPIO_PP3300_USB_EN_L, 1, 20 }, - { GPIO_PP1800_USB_EN_L, 1, 10 }, - { GPIO_LPDDR_PWR_EN, 0, 20 }, - { GPIO_PP1800_PMU_EN_L, 1, 2 }, - { GPIO_PP900_PLL_EN, 0, 0 }, - { GPIO_PP900_PMU_EN, 0, 0 }, - { GPIO_PP900_USB_EN, 0, 6 }, - { GPIO_PP900_PCIE_EN, 0, 0 }, - { GPIO_PP900_AP_EN, 0, 0 }, + { GPIO_PP1800_SENSOR_EN_L, 1, 0 }, { GPIO_PP1800_SIXAXIS_EN_L, 1, 0 }, + { GPIO_PP1800_LID_EN_L, 1, 0 }, { GPIO_PP3300_TRACKPAD_EN_L, 1, 0 }, + { GPIO_PP5000_EN, 0, 0 }, { GPIO_PP3300_USB_EN_L, 1, 20 }, + { GPIO_PP1800_USB_EN_L, 1, 10 }, { GPIO_LPDDR_PWR_EN, 0, 20 }, + { GPIO_PP1800_PMU_EN_L, 1, 2 }, { GPIO_PP900_PLL_EN, 0, 0 }, + { GPIO_PP900_PMU_EN, 0, 0 }, { GPIO_PP900_USB_EN, 0, 6 }, + { GPIO_PP900_PCIE_EN, 0, 0 }, { GPIO_PP900_AP_EN, 0, 0 }, { GPIO_PPVAR_LOGIC_EN, 0, 0 }, }; #endif @@ -268,18 +253,18 @@ DECLARE_DEFERRED(force_shutdown); * power sequencing, and immediately transition out of suspend if necessary. */ #define SLEEP_INTERVAL_MS 5 -#define MSLEEP_CHECK_ABORTED_SUSPEND(msec) \ - do { \ - int sleep_remain = msec; \ - do { \ - msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS)); \ - sleep_remain -= SLEEP_INTERVAL_MS; \ - if (!forcing_shutdown && \ - power_get_signals() & IN_SUSPEND_DEASSERTED) { \ - CPRINTS("suspend aborted"); \ - return POWER_S3S0; \ - } \ - } while (sleep_remain > 0); \ +#define MSLEEP_CHECK_ABORTED_SUSPEND(msec) \ + do { \ + int sleep_remain = msec; \ + do { \ + msleep(MIN(sleep_remain, SLEEP_INTERVAL_MS)); \ + sleep_remain -= SLEEP_INTERVAL_MS; \ + if (!forcing_shutdown && \ + power_get_signals() & IN_SUSPEND_DEASSERTED) { \ + CPRINTS("suspend aborted"); \ + return POWER_S3S0; \ + } \ + } while (sleep_remain > 0); \ } while (0) BUILD_ASSERT(POWER_S3S0 != 0); @@ -295,15 +280,14 @@ static int power_seq_run(const struct power_seq_op *power_seq_ops, int op_count) int i; for (i = 0; i < op_count; i++) { - gpio_set_level(power_seq_ops[i].signal, - power_seq_ops[i].level); + gpio_set_level(power_seq_ops[i].signal, power_seq_ops[i].level); if (!power_seq_ops[i].delay) continue; if ((power_seq_ops == s0s3_power_seq) #ifdef S3_USB_WAKE || (power_seq_ops == s0s3_usb_wake_power_seq) #endif - ) + ) MSLEEP_CHECK_ABORTED_SUSPEND(power_seq_ops[i].delay); else msleep(power_seq_ops[i].delay); @@ -340,8 +324,7 @@ enum power_state power_handle_state(enum power_state state) break; case POWER_S0: - if (!power_has_signals(IN_PGOOD_S3) || - forcing_shutdown || + if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown || !(power_get_signals() & IN_SUSPEND_DEASSERTED)) return POWER_S0S3; @@ -353,16 +336,15 @@ enum power_state power_handle_state(enum power_state state) * it here as well. */ if (power_wait_signals_timeout(IN_PGOOD_AP | IN_PGOOD_SYS, - PGOOD_AP_DEBOUNCE_TIMEOUT) - == EC_ERROR_TIMEOUT) + PGOOD_AP_DEBOUNCE_TIMEOUT) == + EC_ERROR_TIMEOUT) return POWER_S0S3; /* * power_wait_signals_timeout() can block and consume task * wake events, so re-verify the state of the world. */ - if (!power_has_signals(IN_PGOOD_S3) || - forcing_shutdown || + if (!power_has_signals(IN_PGOOD_S3) || forcing_shutdown || !(power_get_signals() & IN_SUSPEND_DEASSERTED)) return POWER_S0S3; #endif @@ -444,7 +426,8 @@ enum power_state power_handle_state(enum power_state state) * interrupt. */ while (power_wait_signals_timeout(IN_PGOOD_S0, - PGOOD_S0_POLL_TIMEOUT) == EC_ERROR_TIMEOUT && + PGOOD_S0_POLL_TIMEOUT) == + EC_ERROR_TIMEOUT && ++tries < PGOOD_S0_POLL_TRIES) ; @@ -553,8 +536,7 @@ static void power_button_changed(void) #endif } /* Delayed power down from S0/S3, cancel on PB release */ - hook_call_deferred(&force_shutdown_data, - FORCED_SHUTDOWN_DELAY); + hook_call_deferred(&force_shutdown_data, FORCED_SHUTDOWN_DELAY); } else { #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 1 if (tablet_boot_on_button_release) { -- cgit v1.2.1 From e501d184a4fd22627670aa1b8d42fcb5ad58f755 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:05 -0600 Subject: common/usbc/usb_pd_dp_ufp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e0932749a4c87a67d29a9427033e0df5e18310c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729785 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pd_dp_ufp.c | 52 ++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/common/usbc/usb_pd_dp_ufp.c b/common/usbc/usb_pd_dp_ufp.c index 0009b5c710..e0a5d493fc 100644 --- a/common/usbc/usb_pd_dp_ufp.c +++ b/common/usbc/usb_pd_dp_ufp.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "usb_pd_dp_ufp.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) enum hpd_state { LOW_WAIT, @@ -105,17 +104,17 @@ static void hpd_to_dp_attention(void) * the DP_STATUS VDO. */ svdm_header = VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) | - VDO_OPOS(opos) | CMD_ATTENTION; + VDO_OPOS(opos) | CMD_ATTENTION; vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, svdm_header); vdm[1] = VDO_DP_STATUS((evt == hpd_irq), /* IRQ_HPD */ - (evt != hpd_low), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - dock_get_mf_preference(), /* MF pref */ - 1, /* enabled */ - 0, /* power low */ - 0x2); + (evt != hpd_low), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + dock_get_mf_preference(), /* MF pref */ + 1, /* enabled */ + 0, /* power low */ + 0x2); /* Send request to DPM to send an attention VDM */ pd_request_vdm_attention(port, vdm, ARRAY_SIZE(vdm)); @@ -154,10 +153,10 @@ static void hpd_queue_event(enum hpd_event evt) * are kept in the queue. */ if (evt == hpd_irq) { - if ((hpd.count >= HPD_QUEUE_DEPTH) || ((hpd.count >= 2) && - (hpd.queue[hpd.count - 2] == hpd_irq))) { - CPRINTS("hpd: discard hpd: count - %d", - hpd.count); + if ((hpd.count >= HPD_QUEUE_DEPTH) || + ((hpd.count >= 2) && + (hpd.queue[hpd.count - 2] == hpd_irq))) { + CPRINTS("hpd: discard hpd: count - %d", hpd.count); return; } } @@ -238,13 +237,13 @@ static void hpd_to_pd_converter(int level, uint64_t ts) */ if (!level) { /* Still low, now wait for IRQ or LOW determination */ - hpd.timer = ts + (HPD_T_IRQ_MAX_PULSE - - HPD_T_IRQ_MIN_PULSE); + hpd.timer = ts + + (HPD_T_IRQ_MAX_PULSE - HPD_T_IRQ_MIN_PULSE); hpd.state = IRQ_CHECK; } else { uint64_t irq_ts = hpd.timer + HPD_T_IRQ_MAX_PULSE - - HPD_T_IRQ_MIN_PULSE; + HPD_T_IRQ_MIN_PULSE; /* * If hpd is high now, this must have been an edge * event, but still need to determine if the pulse width @@ -271,7 +270,7 @@ static void hpd_to_pd_converter(int level, uint64_t ts) if (ts <= hpd.timer) { hpd_queue_event(hpd_irq); } - } else if (ts > hpd.timer) { + } else if (ts > hpd.timer) { hpd.state = LOW_WAIT; hpd_queue_event(hpd_low); } @@ -287,7 +286,7 @@ static void manage_hpd(void) int level; uint64_t ts = get_time().val; uint32_t num_hpd_events = (hpd.edges.head - hpd.edges.tail) & - EDGE_QUEUE_MASK; + EDGE_QUEUE_MASK; /* * HPD edges are detected via GPIO interrupts. The ISR routine adds edge @@ -305,7 +304,7 @@ static void manage_hpd(void) } if (num_hpd_events) { - while(num_hpd_events-- > 0) { + while (num_hpd_events-- > 0) { int idx = hpd.edges.tail; level = hpd.edges.buffer[idx].level; @@ -331,9 +330,8 @@ static void manage_hpd(void) * a DP_ATTENTION message if a DP_CONFIG message has been * received and have passed the minimum spacing interval. */ - if (hpd.send_enable && - ((get_time().val - hpd.last_send_ts) > - HPD_T_MIN_DP_ATTEN)) { + if (hpd.send_enable && ((get_time().val - hpd.last_send_ts) > + HPD_T_MIN_DP_ATTEN)) { /* Generate DP_ATTENTION event pending in queue */ hpd_to_dp_attention(); } else { @@ -352,7 +350,7 @@ static void manage_hpd(void) * the minimum time spacing. */ callback_us = HPD_T_MIN_DP_ATTEN - - (get_time().val - hpd.last_send_ts); + (get_time().val - hpd.last_send_ts); if (callback_us <= 0 || callback_us > HPD_T_MIN_DP_ATTEN) callback_us = HPD_T_MIN_DP_ATTEN; @@ -403,7 +401,7 @@ void usb_pd_hpd_converter_enable(int enable) hpd.state = LOW_WAIT; hpd.count = 0; hpd.timer = 0; - hpd.last_send_ts = 0; + hpd.last_send_ts = 0; hpd.send_enable = 0; /* Reset hpd signal edges queue */ @@ -427,7 +425,7 @@ void usb_pd_hpd_converter_enable(int enable) void usb_pd_hpd_edge_event(int signal) { - int next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK; + int next_head = (hpd.edges.head + 1) & EDGE_QUEUE_MASK; struct hpd_mark mark; /* Get current timestamp and level */ -- cgit v1.2.1 From 15022ce5da40796b842bf4ce86e377e458bda156 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:08 -0600 Subject: driver/temp_sensor/f75303.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4affd18acb2aab45653ecfd65c0c6805a40bbee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730118 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/f75303.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/driver/temp_sensor/f75303.h b/driver/temp_sensor/f75303.h index bdfd2624f0..a782f3aeb2 100644 --- a/driver/temp_sensor/f75303.h +++ b/driver/temp_sensor/f75303.h @@ -9,9 +9,9 @@ #define __CROS_EC_F75303_H #ifdef BOARD_MUSHU -#define F75303_I2C_ADDR_FLAGS 0x4D +#define F75303_I2C_ADDR_FLAGS 0x4D #else -#define F75303_I2C_ADDR_FLAGS 0x4C +#define F75303_I2C_ADDR_FLAGS 0x4C #endif enum f75303_index { @@ -22,9 +22,9 @@ enum f75303_index { }; /* F75303 register */ -#define F75303_TEMP_LOCAL 0x00 -#define F75303_TEMP_REMOTE1 0x01 -#define F75303_TEMP_REMOTE2 0x23 +#define F75303_TEMP_LOCAL 0x00 +#define F75303_TEMP_REMOTE1 0x01 +#define F75303_TEMP_REMOTE2 0x23 /** * Get the last polled value of a sensor. @@ -37,4 +37,4 @@ enum f75303_index { */ int f75303_get_val(int idx, int *temp); -#endif /* __CROS_EC_F75303_H */ +#endif /* __CROS_EC_F75303_H */ -- cgit v1.2.1 From 70684b3d7c8bb560ea82a789e791a876f6cf5e97 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:25 -0600 Subject: common/mag_cal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4867273d8422799badd8b3f400d540d1ee16c3d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729669 Reviewed-by: Jeremy Bettis --- common/mag_cal.c | 50 ++++++++++++++++++++------------------------------ 1 file changed, 20 insertions(+), 30 deletions(-) diff --git a/common/mag_cal.c b/common/mag_cal.c index 13beb93af2..84e6e7f234 100644 --- a/common/mag_cal.c +++ b/common/mag_cal.c @@ -14,17 +14,17 @@ #include "util.h" /* Data from sensor is in 16th of uT, 0.0625 uT/LSB */ -#define MAG_CAL_RAW_UT 16 +#define MAG_CAL_RAW_UT 16 -#define MAX_EIGEN_RATIO FLOAT_TO_FP(25.0f) -#define MAX_EIGEN_MAG FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT) -#define MIN_EIGEN_MAG FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT) +#define MAX_EIGEN_RATIO FLOAT_TO_FP(25.0f) +#define MAX_EIGEN_MAG FLOAT_TO_FP(80.0f * MAG_CAL_RAW_UT) +#define MIN_EIGEN_MAG FLOAT_TO_FP(10.0f * MAG_CAL_RAW_UT) -#define MAX_FIT_MAG MAX_EIGEN_MAG -#define MIN_FIT_MAG MIN_EIGEN_MAG +#define MAX_FIT_MAG MAX_EIGEN_MAG +#define MIN_FIT_MAG MIN_EIGEN_MAG -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define PRINTF_FLOAT(x) ((int)((x) * 100.0f)) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define PRINTF_FLOAT(x) ((int)((x)*100.0f)) /** * Compute the covariance element: (avg(ab) - avg(a)*avg(b)) @@ -51,34 +51,25 @@ static int moc_eigen_test(struct mag_cal_t *moc) mat33_fp_t eigenvecs; fp_t evmax, evmin, evmag; fp_t inv = fp_div_dbz(FLOAT_TO_FP(1.0f), - INT_TO_FP((int) moc->kasa_fit.nsamples)); + INT_TO_FP((int)moc->kasa_fit.nsamples)); int eigen_pass; /* covariance matrix */ - S[0][0] = covariance_element(moc->kasa_fit.acc_xx, - moc->kasa_fit.acc_x, - moc->kasa_fit.acc_x, - inv); + S[0][0] = covariance_element(moc->kasa_fit.acc_xx, moc->kasa_fit.acc_x, + moc->kasa_fit.acc_x, inv); S[0][1] = S[1][0] = covariance_element(moc->kasa_fit.acc_xy, moc->kasa_fit.acc_x, - moc->kasa_fit.acc_y, - inv); + moc->kasa_fit.acc_y, inv); S[0][2] = S[2][0] = covariance_element(moc->kasa_fit.acc_xz, moc->kasa_fit.acc_x, - moc->kasa_fit.acc_z, - inv); - S[1][1] = covariance_element(moc->kasa_fit.acc_yy, - moc->kasa_fit.acc_y, - moc->kasa_fit.acc_y, - inv); + moc->kasa_fit.acc_z, inv); + S[1][1] = covariance_element(moc->kasa_fit.acc_yy, moc->kasa_fit.acc_y, + moc->kasa_fit.acc_y, inv); S[1][2] = S[2][1] = covariance_element(moc->kasa_fit.acc_yz, moc->kasa_fit.acc_y, - moc->kasa_fit.acc_z, - inv); - S[2][2] = covariance_element(moc->kasa_fit.acc_zz, - moc->kasa_fit.acc_z, - moc->kasa_fit.acc_z, - inv); + moc->kasa_fit.acc_z, inv); + S[2][2] = covariance_element(moc->kasa_fit.acc_zz, moc->kasa_fit.acc_z, + moc->kasa_fit.acc_z, inv); mat33_fp_get_eigenbasis(S, eigenvals, eigenvecs); @@ -90,9 +81,8 @@ static int moc_eigen_test(struct mag_cal_t *moc) evmag = fp_sqrtf(eigenvals[X] + eigenvals[Y] + eigenvals[Z]); - eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax) - && (evmag > MIN_EIGEN_MAG) - && (evmag < MAX_EIGEN_MAG); + eigen_pass = (fp_mul(evmin, MAX_EIGEN_RATIO) > evmax) && + (evmag > MIN_EIGEN_MAG) && (evmag < MAX_EIGEN_MAG); #if 0 CPRINTF("mag eigenvalues: (%.02d %.02d %.02d), ", -- cgit v1.2.1 From 972d465b81b58e8fd78b9c8a42c90976d7804f4f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:36 -0600 Subject: chip/mt_scp/mt818x/clock_mt8183.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e94f30026d57878c78e73e0acdc94a37e6a9b5e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729325 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/clock_mt8183.c | 40 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/chip/mt_scp/mt818x/clock_mt8183.c b/chip/mt_scp/mt818x/clock_mt8183.c index 1af0a3b893..6eda9e38ff 100644 --- a/chip/mt_scp/mt818x/clock_mt8183.c +++ b/chip/mt_scp/mt818x/clock_mt8183.c @@ -14,7 +14,7 @@ #include "timer.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) #define ULPOSC_DIV_MAX (1 << OSC_DIV_BITS) #define ULPOSC_CALI_MAX (1 << OSC_CALI_BITS) @@ -29,14 +29,14 @@ void clock_init(void) SCP_SYS_CTRL |= AUTO_DDREN; /* Initialize 26MHz system clock counter reset value to 1. */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1); + SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | + CLK_SYS_VAL(1); /* Initialize high frequency ULPOSC counter reset value to 1. */ - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1); + SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | + CLK_HIGH_VAL(1); /* Initialize sleep mode control VREQ counter. */ - SCP_CLK_SLEEP_CTRL = - (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1); + SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | + VREQ_COUNTER_VAL(1); /* Set normal wake clock */ SCP_WAKE_CKSW &= ~WAKE_CKSW_SEL_NORMAL_MASK; @@ -108,13 +108,12 @@ static unsigned int scp_measure_ulposc_freq(int osc) int cnt; /* Before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; + AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK; /* Select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); + AP_CLK_DBG_CFG = + (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | + (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2); /* Set meter divisor to 1, bit[31:24] = b00000000 */ AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | @@ -163,8 +162,7 @@ static int scp_ulposc_config_measure(int osc, int div, int cali) scp_ulposc_config(osc, div, cali); freq = scp_measure_ulposc_freq(osc); - CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", - osc + 1, div, cali, freq, + CPRINTF("ULPOSC%d: %d %d %d (%dkHz)\n", osc + 1, div, cali, freq, freq * 26 * 1000 / 1024); return freq; @@ -182,10 +180,10 @@ static int scp_calibrate_ulposc(int osc, int target_mhz) { int target_freq = DIV_ROUND_NEAREST(target_mhz * 1024, 26); struct ulposc { - int div; /* frequency divisor/multiplier */ - int cali; /* variable resistor calibrator */ - int freq; /* frequency counter measure result */ - } curr, prev = {0}; + int div; /* frequency divisor/multiplier */ + int cali; /* variable resistor calibrator */ + int freq; /* frequency counter measure result */ + } curr, prev = { 0 }; enum { STAGE_DIV, STAGE_CALI } stage = STAGE_DIV; int param, param_max; @@ -220,9 +218,9 @@ static int scp_calibrate_ulposc(int osc, int target_mhz) * frequency, pick the closest one. */ if (prev.freq && signum(target_freq - curr.freq) != - signum(target_freq - prev.freq)) { + signum(target_freq - prev.freq)) { if (abs(target_freq - prev.freq) < - abs(target_freq - curr.freq)) + abs(target_freq - curr.freq)) curr = prev; if (stage == STAGE_CALI) @@ -304,7 +302,7 @@ void scp_enable_clock(void) SCP_SYS_CTRL |= AUTO_DDREN; /* Set settle time */ - SCP_CLK_SYS_VAL = 1; /* System clock */ + SCP_CLK_SYS_VAL = 1; /* System clock */ SCP_CLK_HIGH_VAL = 1; /* ULPOSC */ SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | 2; -- cgit v1.2.1 From 9ce0031b4b18ee3d8cddb78a54d33c3c70391e9a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:46 -0600 Subject: board/pdeval-stm32f072/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50d41f0fd1c665a963b8efbfecdaab0105f6eb37 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728818 Reviewed-by: Jeremy Bettis --- board/pdeval-stm32f072/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/pdeval-stm32f072/board.h b/board/pdeval-stm32f072/board.h index c075772e9f..8554291ae0 100644 --- a/board/pdeval-stm32f072/board.h +++ b/board/pdeval-stm32f072/board.h @@ -40,14 +40,14 @@ #define CONFIG_USB_PD_PULLUP TYPEC_RP_USB /* fake board specific type-C power constants */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 650000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* I2C master port connected to the TCPC */ #define I2C_PORT_TCPC 0 @@ -66,12 +66,12 @@ /* USB interface indexes (use define rather than enum to expand them) */ #define USB_IFACE_CONSOLE 0 -#define USB_IFACE_COUNT 1 +#define USB_IFACE_COUNT 1 /* USB endpoint indexes (use define rather than enum to expand them) */ #define USB_EP_CONTROL 0 #define USB_EP_CONSOLE 1 -#define USB_EP_COUNT 2 +#define USB_EP_COUNT 2 /* Remove console commands / features for flash / RAM savings */ #undef CONFIG_WATCHDOG_HELP -- cgit v1.2.1 From 7a65dd42f52bcbe7ad223dc08ac13d8ce2a144ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:57 -0600 Subject: board/mchpevb1/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I853ff7b92bef44013bdeec1d43c47a79d68c8cd4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728656 Reviewed-by: Jeremy Bettis --- board/mchpevb1/board.h | 61 +++++++++++++++++++++++--------------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/board/mchpevb1/board.h b/board/mchpevb1/board.h index e16d0bb10f..74898cb028 100644 --- a/board/mchpevb1/board.h +++ b/board/mchpevb1/board.h @@ -88,7 +88,6 @@ * #define EVB_NO_ESPI_TEST_MODE */ - /* * DEBUG * Disable ARM Cortex-M4 write buffer so @@ -104,7 +103,7 @@ * Values in MHz are 20, 25, 33, 50, and 66 */ /* KBL + EVB fly-wire hook up only supports 20MHz */ -#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_20M +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_20M /* * EC eSPI advertises IO lanes @@ -114,7 +113,7 @@ * 3 = Single, Dual, and Quad */ /* KBL + EVB fly-wire hook up only support Single mode */ -#define CONFIG_HOSTCMD_ESPI_EC_MODE MCHP_ESPI_CAP1_SINGLE_MODE +#define CONFIG_HOSTCMD_ESPI_EC_MODE MCHP_ESPI_CAP1_SINGLE_MODE /* * Bit map of eSPI channels EC advertises @@ -123,7 +122,7 @@ * bit[2] = 1 OOB channel * bit[3] = 1 Flash channel */ -#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP +#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP #define CONFIG_MCHP_ESPI_VW_SAVE_ON_SLEEP @@ -146,7 +145,6 @@ /* #define CONFIG_CHARGE_MANAGER */ /* #define CONFIG_CHARGE_RAMP_SW */ - /* #define CONFIG_CHARGER */ /* #define CONFIG_CHARGER_DISCHARGE_ON_AC */ @@ -190,7 +188,6 @@ * #define CONFIG_LOW_POWER_IDLE */ - /* #define CONFIG_GPIO_POWER_DOWN */ /* @@ -270,8 +267,8 @@ * Configure for smaller flash is OK for testing except * for SPI flash lock bit. */ - #define CONFIG_FLASH_SIZE_BYTES 524288 - #define CONFIG_SPI_FLASH_W25X40 +#define CONFIG_FLASH_SIZE_BYTES 524288 +#define CONFIG_SPI_FLASH_W25X40 /* * #define CONFIG_FLASH_SIZE_BYTES 0x1000000 * #define CONFIG_SPI_FLASH_W25Q128 @@ -321,7 +318,7 @@ * Make sure to not include GPSPI in little-firmware(LFW) */ #ifndef LFW -#define CONFIG_MCHP_GPSPI 0x01 +#define CONFIG_MCHP_GPSPI 0x01 #endif /* SPI Accelerometer @@ -360,9 +357,8 @@ #define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2 /* I2C ports */ -#define I2C_CONTROLLER_COUNT 2 -#define I2C_PORT_COUNT 2 - +#define I2C_CONTROLLER_COUNT 2 +#define I2C_PORT_COUNT 2 /* * Map I2C Ports to Controllers for this board. @@ -377,26 +373,26 @@ * All other ports set to 0xff (not used) */ -#define I2C_PORT_PMIC MCHP_I2C_PORT10 -#define I2C_PORT_USB_CHARGER_1 MCHP_I2C_PORT2 -#define I2C_PORT_USB_MUX MCHP_I2C_PORT2 -#define I2C_PORT_USB_CHARGER_2 MCHP_I2C_PORT2 -#define I2C_PORT_PD_MCU MCHP_I2C_PORT3 -#define I2C_PORT_TCPC MCHP_I2C_PORT3 -#define I2C_PORT_ALS MCHP_I2C_PORT4 -#define I2C_PORT_ACCEL MCHP_I2C_PORT4 -#define I2C_PORT_BATTERY MCHP_I2C_PORT5 -#define I2C_PORT_CHARGER MCHP_I2C_PORT5 +#define I2C_PORT_PMIC MCHP_I2C_PORT10 +#define I2C_PORT_USB_CHARGER_1 MCHP_I2C_PORT2 +#define I2C_PORT_USB_MUX MCHP_I2C_PORT2 +#define I2C_PORT_USB_CHARGER_2 MCHP_I2C_PORT2 +#define I2C_PORT_PD_MCU MCHP_I2C_PORT3 +#define I2C_PORT_TCPC MCHP_I2C_PORT3 +#define I2C_PORT_ALS MCHP_I2C_PORT4 +#define I2C_PORT_ACCEL MCHP_I2C_PORT4 +#define I2C_PORT_BATTERY MCHP_I2C_PORT5 +#define I2C_PORT_CHARGER MCHP_I2C_PORT5 /* Thermal sensors read through PMIC ADC interface */ #if 0 -#define I2C_PORT_THERMAL I2C_PORT_PMIC +#define I2C_PORT_THERMAL I2C_PORT_PMIC #else -#define I2C_PORT_THERMAL MCHP_I2C_PORT4 +#define I2C_PORT_THERMAL MCHP_I2C_PORT4 #endif /* Ambient Light Sensor address */ -#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS +#define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS /* Modules we want to exclude */ #undef CONFIG_CMD_HASH @@ -425,9 +421,9 @@ enum temp_sensor_id { /* These temp sensors are only readable in S0 */ TEMP_SENSOR_AMBIENT, TEMP_SENSOR_CASE, -/* TEMP_SENSOR_CHARGER, */ -/* TEMP_SENSOR_DRAM, */ -/* TEMP_SENSOR_WIFI, */ + /* TEMP_SENSOR_CHARGER, */ + /* TEMP_SENSOR_DRAM, */ + /* TEMP_SENSOR_WIFI, */ TEMP_SENSOR_COUNT }; @@ -453,25 +449,24 @@ enum als_id { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 /* Try to negotiate to 20V since i2c noise problems should be fixed. */ -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_VOLTAGE_MV 20000 /* * include TFDP macros from mchp chip level */ #include "tfdp_chip.h" - /* Map I2C port to controller */ int board_i2c_p2c(int port); -- cgit v1.2.1 From 719cad825d27cefa32811c87ac00e938d485d242 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:35 -0600 Subject: board/volteer_ish/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac4283ff59d4a6fda455b2c8f01defde9489173f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729082 Reviewed-by: Jeremy Bettis --- board/volteer_ish/board.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/volteer_ish/board.c b/board/volteer_ish/board.c index 76c127056b..514a0bf5b9 100644 --- a/board/volteer_ish/board.c +++ b/board/volteer_ish/board.c @@ -20,11 +20,7 @@ /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 1000 - }, + { .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From fd9861f1a8a0b618fce5daefb478555678e8996c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:06 -0600 Subject: board/banshee/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea3eef003de34c3662455ff86600b1fe2c53fecc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728004 Reviewed-by: Jeremy Bettis --- board/banshee/usbc_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/banshee/usbc_config.h b/board/banshee/usbc_config.h index 9a7cf4caca..e1e0d53ea4 100644 --- a/board/banshee/usbc_config.h +++ b/board/banshee/usbc_config.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 4 +#define CONFIG_USB_PD_PORT_MAX_COUNT 4 enum usbc_port { USBC_PORT_C0 = 0, -- cgit v1.2.1 From 530ee9a40b161a004c0790c94a935ede9d6244cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:12 -0600 Subject: board/moli/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I84292f0e797304d3b026e7b9a7dade2c92837459 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728694 Reviewed-by: Jeremy Bettis --- board/moli/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/moli/usbc_config.c b/board/moli/usbc_config.c index a54564c34c..e191973a34 100644 --- a/board/moli/usbc_config.c +++ b/board/moli/usbc_config.c @@ -30,8 +30,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From a3c228fc58cee7915b1ba263ca5c932449974e0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:42 -0600 Subject: common/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If70078c11c4fdb72c5da5dd5214c283601ea1465 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729735 Reviewed-by: Jeremy Bettis --- common/system.c | 173 ++++++++++++++++++++++++-------------------------------- 1 file changed, 73 insertions(+), 100 deletions(-) diff --git a/common/system.c b/common/system.c index 013452c21a..5e215a0b4f 100644 --- a/common/system.c +++ b/common/system.c @@ -41,17 +41,17 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* Round up to a multiple of 4 */ #define ROUNDUP4(x) (((x) + 3) & ~3) /* Data for an individual jump tag */ struct jump_tag { - uint16_t tag; /* Tag ID */ - uint8_t data_size; /* Size of data which follows */ - uint8_t data_version; /* Data version */ + uint16_t tag; /* Tag ID */ + uint8_t data_size; /* Size of data which follows */ + uint8_t data_version; /* Data version */ /* Followed by data_size bytes of data */ }; @@ -59,10 +59,10 @@ struct jump_tag { /* Jump data (at end of RAM, or preceding panic data) */ static struct jump_data *jdata; -static uint32_t reset_flags; /* EC_RESET_FLAG_* */ +static uint32_t reset_flags; /* EC_RESET_FLAG_* */ static int jumped_to_image; -static int disable_jump; /* Disable ALL jumps if system is locked */ -static int force_locked; /* Force system locked even if WP isn't enabled */ +static int disable_jump; /* Disable ALL jumps if system is locked */ +static int force_locked; /* Force system locked even if WP isn't enabled */ static enum ec_reboot_cmd reboot_at_shutdown; static enum sysinfo_flags system_info_flags; @@ -83,8 +83,8 @@ static uint32_t ap_sku_id; #ifdef CONFIG_HOSTCMD_AP_SET_SKUID -#define AP_SKUID_SYSJUMP_TAG 0x4153 /* AS */ -#define AP_SKUID_HOOK_VERSION 1 +#define AP_SKUID_SYSJUMP_TAG 0x4153 /* AS */ +#define AP_SKUID_HOOK_VERSION 1 /** * Preserve AP SKUID across a sysjump. @@ -109,7 +109,7 @@ static void ap_sku_id_restore_state(void) AP_SKUID_SYSJUMP_TAG, &version, &size); if (prev_ap_sku_id && version == AP_SKUID_HOOK_VERSION && - size == sizeof(prev_ap_sku_id)) { + size == sizeof(prev_ap_sku_id)) { memcpy(&ap_sku_id, prev_ap_sku_id, sizeof(ap_sku_id)); } } @@ -271,8 +271,8 @@ static void print_reset_flags(uint32_t flags) { int count = 0; int i; - static const char * const reset_flag_descs[] = { - #include "reset_flag_desc.inc" + static const char *const reset_flag_descs[] = { +#include "reset_flag_desc.inc" }; if (!flags) { @@ -311,9 +311,8 @@ void system_print_banner(void) CPRINTS("UART initialized after sysjump"); else CPUTS("\n--- UART initialized after reboot ---\n"); - CPRINTF("[Image: %s, %s]\n", - system_get_image_copy_string(), - system_get_build_info()); + CPRINTF("[Image: %s, %s]\n", system_get_image_copy_string(), + system_get_build_info()); CPUTS("[Reset cause: "); system_print_reset_flags(); CPUTS("]\n"); @@ -416,8 +415,7 @@ void system_disable_jump(void) ret = mpu_protect_data_ram(); if (ret == EC_SUCCESS) { CPRINTS("data RAM locked. Exclusion %pP-%pP", - &__iram_text_start, - &__iram_text_end); + &__iram_text_start, &__iram_text_end); } else { CPRINTS("Failed to lock data RAM (%d)", ret); return; @@ -441,11 +439,11 @@ void system_disable_jump(void) */ switch (system_get_image_copy()) { case EC_IMAGE_RO: - ret = mpu_lock_rw_flash(); + ret = mpu_lock_rw_flash(); copy = EC_IMAGE_RW; break; case EC_IMAGE_RW: - ret = mpu_lock_ro_flash(); + ret = mpu_lock_ro_flash(); copy = EC_IMAGE_RO; break; default: @@ -453,8 +451,7 @@ void system_disable_jump(void) ret = !EC_SUCCESS; } if (ret == EC_SUCCESS) { - CPRINTS("%s image locked", - ec_image_to_string(copy)); + CPRINTS("%s image locked", ec_image_to_string(copy)); } else { CPRINTS("Failed to lock %s image (%d)", ec_image_to_string(copy), ret); @@ -477,8 +474,8 @@ test_mockable enum ec_image system_get_image_copy(void) /* Return which region is used in program memory */ return system_get_shrspi_image_copy(); #else - uintptr_t my_addr = (uintptr_t)system_get_image_copy - - CONFIG_PROGRAM_MEMORY_BASE; + uintptr_t my_addr = + (uintptr_t)system_get_image_copy - CONFIG_PROGRAM_MEMORY_BASE; if (my_addr >= CONFIG_RO_MEM_OFF && my_addr < (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)) @@ -541,9 +538,8 @@ const char *system_get_image_copy_string(void) const char *ec_image_to_string(enum ec_image copy) { - static const char * const image_names[] = { - "unknown", "RO", "RW", "RO_B", "RW_B" - }; + static const char *const image_names[] = { "unknown", "RO", "RW", + "RO_B", "RW_B" }; return image_names[copy < ARRAY_SIZE(image_names) ? copy : 0]; } @@ -604,7 +600,7 @@ static void jump_to_image(uintptr_t init_addr) jdata->magic = JUMP_DATA_MAGIC; jdata->version = JUMP_DATA_VERSION; jdata->reset_flags = reset_flags; - jdata->jump_tag_total = 0; /* Reset tags */ + jdata->jump_tag_total = 0; /* Reset tags */ jdata->struct_size = sizeof(struct jump_data); /* Call other hooks; these may add tags */ @@ -619,7 +615,7 @@ static void jump_to_image(uintptr_t init_addr) #endif /* CONFIG_DMA */ /* Jump to the reset vector */ - resetvec = (void(*)(void))init_addr; + resetvec = (void (*)(void))init_addr; resetvec(); } @@ -688,8 +684,8 @@ static int system_run_image_copy_with_flags(enum ec_image copy, if (copy == EC_IMAGE_RO) system_clear_reset_flags(EC_RESET_FLAG_EFS); - CPRINTS("Jumping to image %s (0x%08x)", - ec_image_to_string(copy), system_get_reset_flags()); + CPRINTS("Jumping to image %s (0x%08x)", ec_image_to_string(copy), + system_get_reset_flags()); jump_to_image(init_addr); @@ -715,9 +711,9 @@ enum ec_image system_get_active_copy(void) enum ec_image system_get_update_copy(void) { -#ifdef CONFIG_VBOOT_EFS /* Not needed for EFS2, which is single-slot. */ - return system_get_active_copy() == EC_IMAGE_RW_A ? - EC_IMAGE_RW_B : EC_IMAGE_RW_A; +#ifdef CONFIG_VBOOT_EFS /* Not needed for EFS2, which is single-slot. */ + return system_get_active_copy() == EC_IMAGE_RW_A ? EC_IMAGE_RW_B : + EC_IMAGE_RW_A; #else return EC_IMAGE_RW_A; #endif @@ -764,7 +760,7 @@ const struct image_data *system_get_image_data(enum ec_image copy) * it's the same offset as in the current image. Find that offset. */ addr = ((uintptr_t)¤t_image_data - - get_program_memory_addr(active_copy)); + get_program_memory_addr(active_copy)); /* * Read the version information from the proper location @@ -792,24 +788,23 @@ const struct image_data *system_get_image_data(enum ec_image copy) return NULL; } -__attribute__((weak)) /* Weird chips may need their own implementations */ -const char *system_get_version(enum ec_image copy) +__attribute__((weak)) /* Weird chips may need their own implementations */ +const char * +system_get_version(enum ec_image copy) { const struct image_data *data = system_get_image_data(copy); return data ? data->version : ""; } - const char *system_get_cros_fwid(enum ec_image copy) { const struct image_data *data; if (IS_ENABLED(CONFIG_CROS_FWID_VERSION)) { data = system_get_image_data(copy); - if (data && - (data->cookie3 & CROS_EC_IMAGE_DATA_COOKIE3_MASK) == - CROS_EC_IMAGE_DATA_COOKIE3) + if (data && (data->cookie3 & CROS_EC_IMAGE_DATA_COOKIE3_MASK) == + CROS_EC_IMAGE_DATA_COOKIE3) return data->cros_fwid; else return CROS_FWID_MISSING_STR; @@ -870,8 +865,9 @@ int system_get_board_version(void) return board_get_version(); } -__attribute__((weak)) /* Weird chips may need their own implementations */ -const char *system_get_build_info(void) +__attribute__((weak)) /* Weird chips may need their own implementations */ +const char * +system_get_build_info(void) { return build_info; } @@ -917,7 +913,7 @@ void system_common_pre_init(void) * the new fields below. */ if (jdata->version == 1) - delta = 0; /* No tags in v1, so no need for move */ + delta = 0; /* No tags in v1, so no need for move */ else if (jdata->version == 2) delta = sizeof(struct jump_data) - JUMP_DATA_SIZE_V2; else @@ -975,8 +971,8 @@ static int handle_pending_reboot(enum ec_reboot_cmd cmd) case EC_REBOOT_CANCEL: return EC_SUCCESS; case EC_REBOOT_JUMP_RO: - return system_run_image_copy_with_flags(EC_IMAGE_RO, - EC_RESET_FLAG_STAY_IN_RO); + return system_run_image_copy_with_flags( + EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO); case EC_REBOOT_JUMP_RW: return system_run_image_copy(system_get_active_copy()); case EC_REBOOT_COLD: @@ -1059,8 +1055,8 @@ void system_enter_hibernate(uint32_t seconds, uint32_t microseconds) * this is to prevent an action triggered by developers. * See: b/192259035 */ - if (IS_ENABLED(CONFIG_EXTPOWER) && IS_ENABLED(CONFIG_AP_POWER_CONTROL) - && extpower_is_present()) { + if (IS_ENABLED(CONFIG_EXTPOWER) && + IS_ENABLED(CONFIG_AP_POWER_CONTROL) && extpower_is_present()) { CPRINTS("AC on, skip hibernate"); return; } @@ -1160,8 +1156,7 @@ static int command_sysinfo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo, NULL, "Print system info"); static enum ec_status host_command_sysinfo(struct host_cmd_handler_args *args) @@ -1207,8 +1202,7 @@ static int command_scratchpad(int argc, char **argv) ccprintf("Scratchpad: 0x%08x\n", scratchpad_value); return rv; } -DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad, - "[val]", +DECLARE_CONSOLE_COMMAND(scratchpad, command_scratchpad, "[val]", "Get or set scratchpad value"); #endif /* CONFIG_CMD_SCRATCHPAD */ @@ -1238,8 +1232,7 @@ __maybe_unused static int command_hibernate(int argc, char **argv) return EC_SUCCESS; } #ifdef CONFIG_HIBERNATE -DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate, - "[sec] [usec]", +DECLARE_CONSOLE_COMMAND(hibernate, command_hibernate, "[sec] [usec]", "Hibernate the EC"); #endif /* CONFIG_HIBERNATE */ @@ -1353,9 +1346,7 @@ static int command_version(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(version, command_version, - NULL, - "Print versions"); +DECLARE_SAFE_CONSOLE_COMMAND(version, command_version, NULL, "Print versions"); #ifdef CONFIG_CMD_SYSJUMP static int command_sysjump(int argc, char **argv) @@ -1368,8 +1359,8 @@ static int command_sysjump(int argc, char **argv) /* Handle named images */ if (!strcasecmp(argv[1], "RO")) - return system_run_image_copy_with_flags(EC_IMAGE_RO, - EC_RESET_FLAG_STAY_IN_RO); + return system_run_image_copy_with_flags( + EC_IMAGE_RO, EC_RESET_FLAG_STAY_IN_RO); else if (!strcasecmp(argv[1], "RW") || !strcasecmp(argv[1], "A")) return system_run_image_copy(EC_IMAGE_RW); else if (!strcasecmp(argv[1], "B")) { @@ -1454,8 +1445,7 @@ static int command_system_lock(int argc, char **argv) force_locked = 1; return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(syslock, command_system_lock, NULL, "Lock the system, even if WP is disabled"); #endif @@ -1510,17 +1500,14 @@ static int command_jumptags(int argc, char **argv) t = (const struct jump_tag *)(system_usable_ram_end() + used); used += sizeof(struct jump_tag) + ROUNDUP4(t->data_size); - ccprintf("%08x: 0x%04x %c%c.%d %3d\n", - (uintptr_t)t, - t->tag, t->tag >> 8, (uint8_t)t->tag, - t->data_version, t->data_size); + ccprintf("%08x: 0x%04x %c%c.%d %3d\n", (uintptr_t)t, t->tag, + t->tag >> 8, (uint8_t)t->tag, t->data_version, + t->data_size); } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags, - NULL, - "List jump tags"); +DECLARE_CONSOLE_COMMAND(jumptags, command_jumptags, NULL, "List jump tags"); #endif /* CONFIG_CMD_JUMPTAGS */ #ifdef CONFIG_EMULATED_SYSRQ @@ -1535,8 +1522,7 @@ static int command_sysrq(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq, - "[key]", +DECLARE_CONSOLE_COMMAND(sysrq, command_sysrq, "[key]", "Simulate sysrq press (default: x)"); #endif /* CONFIG_EMULATED_SYSRQ */ @@ -1547,8 +1533,7 @@ static int command_rflags(int argc, char **argv) ccprintf("\n"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rflags, command_rflags, - NULL, +DECLARE_CONSOLE_COMMAND(rflags, command_rflags, NULL, "Print reset flags saved in non-volatile memory"); #endif @@ -1606,8 +1591,7 @@ host_command_get_version(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION, - host_command_get_version, +DECLARE_HOST_COMMAND(EC_CMD_GET_VERSION, host_command_get_version, EC_VER_MASK(0) | EC_VER_MASK(1)); #ifdef CONFIG_HOSTCMD_SKUID @@ -1621,8 +1605,7 @@ host_command_get_sku_id(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID, - host_command_get_sku_id, +DECLARE_HOST_COMMAND(EC_CMD_GET_SKU_ID, host_command_get_sku_id, EC_VER_MASK(0)); #endif @@ -1636,8 +1619,7 @@ host_command_set_sku_id(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID, - host_command_set_sku_id, +DECLARE_HOST_COMMAND(EC_CMD_SET_SKU_ID, host_command_set_sku_id, EC_VER_MASK(0)); #endif @@ -1652,8 +1634,7 @@ host_command_get_keyboard_id(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBOARD_ID, - host_command_get_keyboard_id, +DECLARE_HOST_COMMAND(EC_CMD_GET_KEYBOARD_ID, host_command_get_keyboard_id, EC_VER_MASK(0)); #endif @@ -1665,8 +1646,7 @@ host_command_build_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO, - host_command_build_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_BUILD_INFO, host_command_build_info, EC_VER_MASK(0)); static enum ec_status @@ -1682,8 +1662,7 @@ host_command_get_chip_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO, - host_command_get_chip_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_CHIP_INFO, host_command_get_chip_info, EC_VER_MASK(0)); static enum ec_status @@ -1703,8 +1682,7 @@ host_command_get_board_version(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION, - host_command_get_board_version, +DECLARE_HOST_COMMAND(EC_CMD_GET_BOARD_VERSION, host_command_get_board_version, EC_VER_MASK(0)); static enum ec_status host_command_reboot(struct host_cmd_handler_args *args) @@ -1738,10 +1716,8 @@ static enum ec_status host_command_reboot(struct host_cmd_handler_args *args) } #ifdef HAS_TASK_HOSTCMD - if (p.cmd == EC_REBOOT_JUMP_RO || - p.cmd == EC_REBOOT_JUMP_RW || - p.cmd == EC_REBOOT_COLD || - p.cmd == EC_REBOOT_HIBERNATE || + if (p.cmd == EC_REBOOT_JUMP_RO || p.cmd == EC_REBOOT_JUMP_RW || + p.cmd == EC_REBOOT_COLD || p.cmd == EC_REBOOT_HIBERNATE || p.cmd == EC_REBOOT_COLD_AP_OFF) { /* Clean busy bits on host for commands that won't return */ args->result = EC_RES_SUCCESS; @@ -1761,21 +1737,18 @@ static enum ec_status host_command_reboot(struct host_cmd_handler_args *args) return EC_RES_ERROR; } } -DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC, - host_command_reboot, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_REBOOT_EC, host_command_reboot, EC_VER_MASK(0)); int system_can_boot_ap(void) { int soc = -1; int pow = -1; -#if defined(CONFIG_BATTERY) && \ - defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) +#if defined(CONFIG_BATTERY) && defined(CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) /* Require a minimum battery level to power on. If battery isn't * present, battery_state_of_charge_abs returns false. */ if (battery_state_of_charge_abs(&soc) == EC_SUCCESS && - soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) + soc >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) return 1; #endif @@ -1816,7 +1789,7 @@ __overridable int board_write_serial(const char *serialno) else return EC_ERROR_UNIMPLEMENTED; } -#endif /* CONFIG_SERIALNO_LEN */ +#endif /* CONFIG_SERIALNO_LEN */ #ifdef CONFIG_MAC_ADDR_LEN /* By default, read MAC address from flash, can be overridden. */ @@ -1838,10 +1811,10 @@ __overridable int board_write_mac_addr(const char *mac_addr) else return EC_ERROR_UNIMPLEMENTED; } -#endif /* CONFIG_MAC_ADDR_LEN */ +#endif /* CONFIG_MAC_ADDR_LEN */ -__attribute__((weak)) -void clock_enable_module(enum module_id module, int enable) +__attribute__((weak)) void clock_enable_module(enum module_id module, + int enable) { /* * Default weak implementation - for chips that don't support this -- cgit v1.2.1 From 696de74ff3a954241870b09ca766866143fee417 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:09 -0600 Subject: driver/bc12/max14637.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d789de11b2774d7ae38e5435d449647f2138a6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729953 Reviewed-by: Jeremy Bettis --- driver/bc12/max14637.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/driver/bc12/max14637.c b/driver/bc12/max14637.c index 4c7cbffd18..df1f887f41 100644 --- a/driver/bc12/max14637.c +++ b/driver/bc12/max14637.c @@ -28,7 +28,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW) /** @@ -38,10 +38,10 @@ * @return 1 if charger detect is activated (high when active high or * low with active low), otherwise 0. */ -static int is_chg_det_activated(const struct max14637_config_t * const cfg) +static int is_chg_det_activated(const struct max14637_config_t *const cfg) { return !!gpio_get_level(cfg->chg_det_pin) ^ - !!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW); + !!(cfg->flags & MAX14637_FLAGS_CHG_DET_ACTIVE_LOW); } #endif @@ -52,12 +52,12 @@ static int is_chg_det_activated(const struct max14637_config_t * const cfg) * @param enable 1 to activate gpio (high for active high and low for active * low). */ -static void activate_chip_enable( - const struct max14637_config_t * const cfg, const int enable) +static void activate_chip_enable(const struct max14637_config_t *const cfg, + const int enable) { - gpio_set_level( - cfg->chip_enable_pin, - !!enable ^ !!(cfg->flags & MAX14637_FLAGS_ENABLE_ACTIVE_LOW)); + gpio_set_level(cfg->chip_enable_pin, + !!enable ^ !!(cfg->flags & + MAX14637_FLAGS_ENABLE_ACTIVE_LOW)); } /** @@ -67,7 +67,7 @@ static void activate_chip_enable( */ static void update_bc12_status_to_charger_manager(const int port) { - const struct max14637_config_t * const cfg = &max14637_config[port]; + const struct max14637_config_t *const cfg = &max14637_config[port]; struct charge_port_info new_chg; new_chg.voltage = USB_CHARGER_VOLTAGE_MV; @@ -100,7 +100,7 @@ static void update_bc12_status_to_charger_manager(const int port) */ static void bc12_detect(const int port) { - const struct max14637_config_t * const cfg = &max14637_config[port]; + const struct max14637_config_t *const cfg = &max14637_config[port]; /* * Enable the IC to begin detection and connect switches if @@ -176,7 +176,7 @@ static void detect_or_power_down_ic(const int port) static void max14637_usb_charger_task_init(const int port) { - const struct max14637_config_t * const cfg = &max14637_config[port]; + const struct max14637_config_t *const cfg = &max14637_config[port]; ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); /* -- cgit v1.2.1 From 04498a1a57cbd7d17a144a632ea1df507b3a6da9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:46 -0600 Subject: board/taniks/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibb78d1a0a5cd867d0162b67a9f082c800afea977 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729009 Reviewed-by: Jeremy Bettis --- board/taniks/board.h | 196 +++++++++++++++++++++++---------------------------- 1 file changed, 89 insertions(+), 107 deletions(-) diff --git a/board/taniks/board.h b/board/taniks/board.h index 0756395afa..645dde7992 100644 --- a/board/taniks/board.h +++ b/board/taniks/board.h @@ -40,15 +40,14 @@ #define CONFIG_LED_ONOFF_STATES /* Sensors */ -#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT - +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Change Request (b/211078551) * GYRO sensor change from ST LSM6DSOETR3TR to ST LSM6DS3TR-C * LSM6DSOETR3TR base accel/gyro if board id = 0 * LSM6DS3TR-C Base accel/gyro if board id > 0 */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_LSM6DSM @@ -63,29 +62,27 @@ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL)) /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_BMA4XX #define CONFIG_ACCEL_LIS2DWL - /* Sensor console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 1 +#define CONFIG_IO_EXPANDER_PORT_COUNT 1 /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_TCPM_PS8815 @@ -103,17 +100,17 @@ #define CONFIG_HOSTCMD_I2C_CONTROL /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* The lower the input voltage, the higher the power efficiency. */ #define PD_PREFER_LOW_VOLTAGE @@ -124,94 +121,94 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KSI_00 GPIO_EC_KSI_00 -#define GPIO_KSI_01 GPIO_EC_KSI_01 -#define GPIO_KSI_02 GPIO_EC_KSI_02 -#define GPIO_KSI_03 GPIO_EC_KSI_03 -#define GPIO_KSI_04 GPIO_EC_KSI_04 -#define GPIO_KSI_05 GPIO_EC_KSI_05 -#define GPIO_KSI_06 GPIO_EC_KSI_06 -#define GPIO_KSI_07 GPIO_EC_KSI_07 -#define GPIO_KSO_00 GPIO_EC_KSO_00 -#define GPIO_KSO_01 GPIO_EC_KSO_01 -#define GPIO_KSO_02 GPIO_EC_KSO_02_R -#define GPIO_KSO_03 GPIO_EC_KSO_03 -#define GPIO_KSO_04 GPIO_EC_KSO_04 -#define GPIO_KSO_05 GPIO_EC_KSO_05 -#define GPIO_KSO_06 GPIO_EC_KSO_06_R -#define GPIO_KSO_07 GPIO_EC_KSO_07_R -#define GPIO_KSO_08 GPIO_EC_KSO_08 -#define GPIO_KSO_09 GPIO_EC_KSO_09 -#define GPIO_KSO_10 GPIO_EC_KSO_10 -#define GPIO_KSO_11 GPIO_EC_KSO_11 -#define GPIO_KSO_12 GPIO_EC_KSO_12 -#define GPIO_KSO_13 GPIO_EC_KSO_13 -#define GPIO_KSO_14 GPIO_EC_KSO_14 -#define GPIO_RFR_KEY_L GPIO_EC_RFR_KEY_ODL_R -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KSI_00 GPIO_EC_KSI_00 +#define GPIO_KSI_01 GPIO_EC_KSI_01 +#define GPIO_KSI_02 GPIO_EC_KSI_02 +#define GPIO_KSI_03 GPIO_EC_KSI_03 +#define GPIO_KSI_04 GPIO_EC_KSI_04 +#define GPIO_KSI_05 GPIO_EC_KSI_05 +#define GPIO_KSI_06 GPIO_EC_KSI_06 +#define GPIO_KSI_07 GPIO_EC_KSI_07 +#define GPIO_KSO_00 GPIO_EC_KSO_00 +#define GPIO_KSO_01 GPIO_EC_KSO_01 +#define GPIO_KSO_02 GPIO_EC_KSO_02_R +#define GPIO_KSO_03 GPIO_EC_KSO_03 +#define GPIO_KSO_04 GPIO_EC_KSO_04 +#define GPIO_KSO_05 GPIO_EC_KSO_05 +#define GPIO_KSO_06 GPIO_EC_KSO_06_R +#define GPIO_KSO_07 GPIO_EC_KSO_07_R +#define GPIO_KSO_08 GPIO_EC_KSO_08 +#define GPIO_KSO_09 GPIO_EC_KSO_09 +#define GPIO_KSO_10 GPIO_EC_KSO_10 +#define GPIO_KSO_11 GPIO_EC_KSO_11 +#define GPIO_KSO_12 GPIO_EC_KSO_12 +#define GPIO_KSO_13 GPIO_EC_KSO_13 +#define GPIO_KSO_14 GPIO_EC_KSO_14 +#define GPIO_RFR_KEY_L GPIO_EC_RFR_KEY_ODL_R +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM #define CONFIG_KEYBOARD_BACKLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0 - -#define I2C_ADDR_EEPROM_FLAGS 0x50 - -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0 + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define I2C_ADDR_MP2964_FLAGS 0x20 /* Thermal features */ #define CONFIG_THERMISTOR #define CONFIG_TEMP_SENSOR -#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK +#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_SEQ_EC_DSW_PWROK #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Fan */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM /* 37h BIT7:2 VSYS_TH2 6.0V */ -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 60 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* 30h BIT13:12 Enable PSYS 00b */ #define CONFIG_CHARGER_BQ25710_PSYS_SENSING /* 30h BIT7 1.2V enable*/ @@ -232,24 +229,23 @@ #define CONFIG_CHARGER_BQ25710_PP_COMP /* 36h UVP 5600mV */ #define CONFIG_CHARGER_BQ25720_VSYS_UVP_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_UVP \ - BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 +#define CONFIG_CHARGER_BQ25720_VSYS_UVP BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 /* 3Eh BIT15:8 VSYS_MIN 6.1V */ #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_CUSTOM #define CONFIG_CHARGER_BQ25710_VSYS_MIN_VOLTAGE_MV 6100 /* RGB Keyboard */ -#define GPIO_RGBKBD_SDB_L GPIO_KBMCU_INT_ODL +#define GPIO_RGBKBD_SDB_L GPIO_KBMCU_INT_ODL #ifdef SECTION_IS_RW #define CONFIG_RGB_KEYBOARD -#define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ +#define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ #endif -#define RGB_GRID0_COL 8 -#define RGB_GRID0_ROW 6 +#define RGB_GRID0_COL 8 +#define RGB_GRID0_ROW 6 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -275,17 +271,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT }; enum battery_type { BATTERY_SMP_51W, @@ -295,19 +283,13 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_FAN, /* PWM5 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From cb07f219bf4d4352cc17ad78a7bb39cabb7ced60 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:29 -0600 Subject: board/mithrax/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f17624ac45d2e66dc53bebfe6f4723eabfc3fd5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728458 Reviewed-by: Jeremy Bettis --- board/mithrax/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mithrax/fans.c b/board/mithrax/fans.c index 1f75eb6ca3..a88af148f5 100644 --- a/board/mithrax/fans.c +++ b/board/mithrax/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From b3e11a08c9dd2e6cce70343e9afa158c3d3e4464 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:25 -0600 Subject: test/motion_angle_data_literals.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c381be8b8df9afc207f35fa680774e4d6450955 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730485 Reviewed-by: Jeremy Bettis --- test/motion_angle_data_literals.c | 1970 +++++++++++++++++++------------------ 1 file changed, 986 insertions(+), 984 deletions(-) diff --git a/test/motion_angle_data_literals.c b/test/motion_angle_data_literals.c index 74d00f8232..c6ec979a7f 100644 --- a/test/motion_angle_data_literals.c +++ b/test/motion_angle_data_literals.c @@ -12,991 +12,993 @@ * [ CONFIG_ACCEL_STD_REF_FRAME_OLD must be defined to used this array. ] */ const float kAccelerometerLaptopModeTestData[] = { - -0.166016f, -0.00488281f, 0.924805f, -0.770508f, -0.0488281f, - -0.510742f, -0.199219f, -0.0078125f, 0.953125f, -0.782227f, - -0.0244141f, -0.652344f, -0.177734f, -0.0136719f, 0.936523f, - -0.772461f, -0.0527344f, -0.59375f, -0.176758f, -0.00878906f, - 0.9375f, -0.777344f, -0.0419922f, -0.637695f, -0.165039f, - -0.00878906f, 0.942383f, -0.782227f, -0.046875f, -0.613281f, - -0.180664f, -0.00976562f, 0.943359f, -0.777344f, -0.0419922f, - -0.601562f, -0.189453f, -0.00488281f, 0.943359f, -0.776367f, - -0.0263672f, -0.613281f, -0.166992f, -0.00488281f, 0.935547f, - -0.78125f, -0.0380859f, -0.609375f, -0.176758f, -0.00878906f, - 0.947266f, -0.790039f, -0.0576172f, -0.585938f, -0.173828f, - -0.0126953f, 0.93457f, -0.780273f, -0.0654297f, -0.666016f, - -0.169922f, -0.00195312f, 0.928711f, -0.775391f, -0.0351562f, - -0.561523f, -0.193359f, 0.0f, 0.941406f, -0.795898f, - -0.0478516f, -0.640625f, -0.162109f, -0.00585938f, 0.917969f, - -0.768555f, -0.0146484f, -0.685547f, -0.166992f, -0.0136719f, - 0.921875f, -0.755859f, -0.0166016f, -0.425781f, -0.175781f, - -0.0810547f, 1.00098f, -0.802734f, -0.117188f, -0.585938f, - -0.210938f, 0.0214844f, 0.881836f, -0.750977f, -0.0302734f, - -0.677734f, -0.285156f, 0.00976562f, 0.967773f, -0.763672f, - -0.0283203f, -0.850586f, -0.222656f, -0.0136719f, 0.943359f, - -0.763672f, -0.0507812f, -0.640625f, -0.236328f, 0.0859375f, - 0.892578f, -0.742188f, 0.0302734f, -0.484375f, -0.269531f, - 0.0263672f, 0.913086f, -0.714844f, -0.00585938f, -0.745117f, - -0.275391f, 0.0927734f, 0.977539f, -0.776367f, -0.078125f, - -0.750977f, -0.155273f, -0.0341797f, 1.2334f, -1.06445f, - -0.0478516f, -0.823242f, -0.196289f, 0.046875f, 1.19141f, - -1.00391f, -0.140625f, -0.541016f, 0.0917969f, 0.21582f, - 0.717773f, -0.764648f, -0.0341797f, -0.607422f, -0.0351562f, - 0.0888672f, 0.207031f, -0.214844f, -0.18457f, -0.0664062f, - -0.0898438f, 0.0556641f, 0.418945f, -0.232422f, 0.43457f, - 0.0361328f, 0.143555f, 0.376953f, 1.23633f, -1.09082f, - 0.529297f, 0.0507812f, 0.205078f, 0.438477f, 1.66602f, - -1.59668f, 0.325195f, -1.20996f, -0.0791016f, 0.404297f, - 1.50977f, -1.40918f, 0.31543f, -1.30273f, -0.0654297f, - 0.141602f, 0.699219f, -0.589844f, 0.0732422f, -0.27832f, - 0.00488281f, 0.00683594f, 0.0566406f, -0.0410156f, -0.0292969f, - -0.0234375f, -0.0488281f, -0.00195312f, -0.0292969f, 0.0849609f, - -0.139648f, 0.0585938f, 0.677734f, 0.667969f, 1.36523f, - -1.11816f, 0.412109f, 0.844727f, 0.142578f, 0.790039f, - 1.73145f, -1.68066f, 0.464844f, -1.29492f, -0.0800781f, - 0.803711f, 0.879883f, -0.765625f, -0.0400391f, -0.616211f, - -0.170898f, 0.879883f, 0.510742f, 0.158203f, 0.381836f, - -0.270508f, -0.0693359f, 0.651367f, 0.431641f, 0.104492f, - 0.991211f, -0.0634766f, -0.0478516f, 0.750977f, 0.283203f, - -0.0332031f, 1.52051f, -0.00195312f, -0.201172f, 1.08984f, - 0.173828f, 0.0849609f, 1.44141f, -0.214844f, -0.0107422f, - 1.29785f, 0.520508f, 0.00488281f, 1.73047f, -0.523438f, - 0.136719f, 1.42188f, 0.987305f, 0.0527344f, 1.74707f, - -0.525391f, 0.34668f, 0.469727f, 0.428711f, 0.114258f, - -0.788086f, 0.177734f, 0.400391f, -0.106445f, 0.328125f, - -0.566406f, -0.948242f, 0.670898f, 0.467773f, -0.21875f, - 0.55957f, -0.767578f, -0.232422f, 0.195312f, 0.625f, - -0.271484f, 0.865234f, -0.765625f, 0.299805f, 0.0703125f, - 0.378906f, -0.526367f, 0.548828f, -0.231445f, -0.569336f, - 0.455078f, 0.303711f, -0.866211f, -0.485352f, 0.566406f, - -1.60547f, 0.481445f, 0.183594f, -0.782227f, -0.260742f, - 0.243164f, -1.41504f, 0.373047f, 0.172852f, -0.935547f, - -0.412109f, 0.133789f, -1.69727f, 0.178711f, 0.407227f, - -0.952148f, -0.227539f, 0.0751953f, -1.67188f, 0.339844f, - 0.498047f, -0.795898f, 0.209961f, 0.177734f, -1.3916f, - 0.458984f, 0.295898f, 0.0390625f, 0.697266f, 0.258789f, - -0.0703125f, -0.131836f, 0.56543f, 0.250977f, 0.913086f, - -0.353516f, 0.90332f, 0.191406f, 0.708008f, 0.352539f, - 0.853516f, -0.839844f, 0.955078f, 0.636719f, 0.657227f, - 0.389648f, 0.620117f, -0.725586f, 0.43457f, 0.485352f, - 0.424805f, 0.479492f, 0.287109f, -0.505859f, -0.209961f, - 0.0927734f, 0.21582f, 0.709961f, 0.492188f, -0.413086f, - -0.0869141f, 0.0673828f, -0.119141f, 1.20508f, 0.392578f, - 0.229492f, 0.927734f, -0.297852f, 0.142578f, 1.0293f, - 0.430664f, 0.0449219f, 1.71875f, -0.0283203f, 0.0107422f, - 1.18164f, 0.0517578f, 0.0751953f, 1.80273f, -0.0693359f, - -0.19043f, 1.1748f, 0.236328f, 0.0839844f, 1.78711f, - -0.472656f, -0.270508f, 1.10254f, 0.964844f, 0.118164f, - 1.75684f, -0.901367f, -0.211914f, 1.11133f, 0.65625f, - 0.308594f, 0.142578f, 0.396484f, 0.239258f, 0.0800781f, - 0.973633f, -0.824219f, -0.25293f, 0.485352f, 0.351562f, - -0.0771484f, 1.08984f, -0.632812f, 0.240234f, -0.258789f, - 0.436523f, -0.514648f, 0.491211f, 0.0664062f, -0.244141f, - -0.148438f, -0.171875f, -0.477539f, -0.459961f, 1.1084f, - -0.822266f, -0.114258f, -0.192383f, -0.608398f, -0.771484f, - 1.11133f, -1.25488f, 1.01953f, -0.0839844f, -0.620117f, - -0.794922f, 0.660156f, -0.876953f, 0.0957031f, -0.242188f, - -0.711914f, -0.55957f, 0.736328f, -0.649414f, -0.0263672f, - -0.258789f, -0.498047f, -0.973633f, 0.957031f, -0.660156f, - 0.186523f, -0.262695f, -0.595703f, -0.787109f, 0.893555f, - -0.429688f, -0.0234375f, -0.254883f, -0.449219f, -0.783203f, - 0.90918f, 0.106445f, -0.161133f, -0.287109f, -0.0800781f, - -0.729492f, 0.933594f, -0.126953f, -0.0742188f, -0.550781f, - -0.271484f, -0.989258f, 1.00098f, -0.879883f, 0.0234375f, - -0.543945f, -0.50293f, -1.18945f, 1.24023f, -1.33398f, - 0.325195f, -0.262695f, -0.307617f, -0.912109f, 1.39062f, - -1.06055f, 0.0107422f, -0.00292969f, -0.573242f, -0.4375f, - 1.15625f, -0.651367f, -0.310547f, 0.188477f, -0.730469f, - -0.121094f, 0.611328f, -0.779297f, 0.335938f, 0.731445f, - -0.475586f, -0.00390625f, 0.100586f, -0.693359f, 0.254883f, - 0.813477f, -0.345703f, 0.420898f, -0.400391f, -0.539062f, - 0.365234f, 0.720703f, 0.0214844f, 0.673828f, -0.370117f, - 0.0585938f, 0.499023f, 0.523438f, 0.198242f, 0.759766f, - -0.544922f, 0.543945f, 0.226562f, 0.473633f, 0.34082f, - 0.595703f, -0.682617f, 0.292969f, -0.217773f, 0.0742188f, - 0.553711f, 0.762695f, -0.504883f, 0.292969f, 0.0751953f, - 0.0126953f, 0.427734f, 0.769531f, -0.265625f, 0.552734f, - -0.0175781f, -0.30957f, 0.253906f, 0.322266f, 0.117188f, - 0.263672f, -0.706055f, -0.991211f, 0.266602f, 0.501953f, - 0.00585938f, 0.0341797f, -1.24805f, -1.21777f, 0.488281f, - 0.461914f, 0.0986328f, 0.362305f, -1.1709f, -1.17188f, - 0.50293f, 0.458984f, 0.108398f, 0.460938f, -1.52148f, - -1.27051f, 0.379883f, 0.90625f, 0.0400391f, 0.524414f, - -1.77832f, -0.951172f, 0.397461f, 0.589844f, 0.520508f, - 0.439453f, -1.99902f, -0.643555f, 0.313477f, 0.766602f, - 0.450195f, 0.286133f, -1.29883f, -0.375f, 0.225586f, - 0.697266f, 0.299805f, 0.108398f, -0.976562f, 0.09375f, - 0.0361328f, 0.851562f, -0.210938f, 0.0615234f, -0.0898438f, - 0.59082f, 0.313477f, 0.756836f, -0.731445f, 0.296875f, - -0.0927734f, 0.552734f, 0.223633f, 0.558594f, -0.806641f, - 0.00195312f, 0.03125f, 0.728516f, 0.276367f, 0.744141f, - -0.994141f, 0.197266f, -0.425781f, 0.316406f, 0.046875f, - 0.601562f, -0.633789f, -0.0576172f, -0.320312f, 0.786133f, - 0.0986328f, 1.0f, -1.19922f, 0.34668f, -0.546875f, - 0.481445f, 0.00390625f, 0.876953f, -1.04297f, -0.0507812f, - -0.775391f, 0.333984f, -0.0175781f, 1.02539f, -1.07129f, - -0.12207f, -0.212891f, 0.28125f, 0.00488281f, 0.998047f, - -0.97168f, 0.178711f, -0.444336f, 0.178711f, 0.0136719f, - 0.896484f, -0.9375f, 0.0117188f, -0.291992f, 0.132812f, - 0.0234375f, 0.975586f, -0.943359f, -0.0078125f, 0.0546875f, - 0.244141f, -0.0771484f, 1.05469f, -1.02148f, 0.313477f, - -0.349609f, 0.148438f, 0.0839844f, 0.619141f, -0.75f, - -0.589844f, -0.0488281f, 0.0263672f, -0.176758f, 0.697266f, - -0.691406f, -0.625977f, -0.417969f, 0.408203f, 0.265625f, - 1.01953f, -1.09863f, 0.106445f, 0.0117188f, 0.157227f, - 0.424805f, 1.07422f, -0.816406f, 0.498047f, 0.0996094f, - 0.00585938f, 0.53418f, 0.771484f, -0.610352f, 0.744141f, - 0.0195312f, 0.0478516f, 0.552734f, 0.734375f, -0.72168f, - 0.518555f, -0.144531f, -0.0361328f, 0.513672f, 0.822266f, - -0.736328f, 0.65918f, -0.179688f, -0.104492f, 0.425781f, - 1.00098f, -0.885742f, 0.739258f, -0.681641f, -0.443359f, - 0.375977f, 0.884766f, -0.724609f, 0.110352f, -0.289062f, - -0.414062f, 0.494141f, 0.53125f, -0.422852f, 0.216797f, - -0.786133f, -0.569336f, 0.749023f, 0.75293f, -0.529297f, - 0.730469f, -0.911133f, -0.68457f, 0.611328f, 0.959961f, - -0.623047f, 1.06543f, -0.499023f, -0.392578f, 0.761719f, - 0.43457f, -0.357422f, 0.631836f, -0.746094f, -0.370117f, - 0.777344f, 0.379883f, -0.225586f, 0.677734f, -0.478516f, - -0.358398f, 0.788086f, 0.569336f, -0.34082f, 0.939453f, - -0.238281f, -0.230469f, 0.861328f, 0.448242f, -0.219727f, - 0.966797f, -0.310547f, -0.242188f, 0.863281f, 0.369141f, - -0.0859375f, 0.87207f, -0.400391f, -0.385742f, 0.841797f, - 0.401367f, -0.0634766f, 0.912109f, -0.458008f, 0.0107422f, - 0.753906f, 0.758789f, -0.675781f, 0.765625f, -0.342773f, - -0.123047f, 0.855469f, 0.599609f, -0.490234f, 0.963867f, - -0.118164f, -0.0117188f, 0.889648f, 0.637695f, -0.607422f, - 0.803711f, -0.597656f, -0.242188f, 0.855469f, 0.550781f, - -0.607422f, 0.576172f, -0.759766f, -0.220703f, 0.832031f, - 0.477539f, -0.491211f, 0.470703f, -0.575195f, -0.0869141f, - 1.01074f, 0.371094f, -0.25293f, 0.678711f, -0.316406f, - -0.197266f, 1.04785f, 0.386719f, -0.046875f, 0.967773f, - -0.761719f, -0.282227f, 0.956055f, 0.270508f, 0.230469f, - 1.39746f, -0.864258f, -0.417969f, 0.761719f, 0.457031f, - 0.0263672f, 1.38379f, -0.714844f, -0.288086f, 0.535156f, - 0.689453f, -0.507812f, 0.68457f, -0.433594f, -0.0908203f, - 0.210938f, 0.825195f, -0.649414f, 0.326172f, -0.793945f, - 0.0527344f, 0.0546875f, 0.911133f, -0.616211f, -0.0214844f, - -0.00195312f, -0.229492f, -0.0253906f, 0.775391f, -0.611328f, - -0.360352f, 0.0371094f, 0.161133f, 0.0253906f, 0.625f, - -0.624023f, -0.344727f, -0.146484f, 0.371094f, 0.255859f, - 1.41797f, -1.27832f, 0.614258f, 0.764648f, 0.869141f, - 0.426758f, 0.758789f, -1.04395f, 0.401367f, 0.263672f, - 0.563477f, 0.450195f, 0.774414f, -0.908203f, 0.384766f, - -0.262695f, 0.664062f, 0.509766f, 0.798828f, -0.757812f, - 0.770508f, 0.491211f, 0.62207f, 0.487305f, 0.496094f, - -0.530273f, 0.375977f, 1.18652f, 0.736328f, 0.386719f, - 0.470703f, -0.647461f, 0.379883f, 0.47168f, 0.834961f, - 0.289062f, 0.475586f, -0.654297f, 0.448242f, 0.395508f, - 0.930664f, 0.0830078f, 0.157227f, -0.304688f, 0.0634766f, - 1.30078f, 0.905273f, -0.102539f, 0.0576172f, -0.303711f, - -0.334961f, 0.885742f, 0.709961f, -0.143555f, 0.0390625f, - -0.18457f, -0.498047f, 1.1084f, 0.744141f, 0.0283203f, - 0.383789f, -0.371094f, -0.126953f, 1.17285f, 0.506836f, - 0.109375f, 0.680664f, -0.244141f, -0.0830078f, 0.577148f, - 0.12793f, 0.25f, 0.972656f, -0.328125f, 0.34082f, - -0.234375f, -0.327148f, 0.470703f, 0.987305f, -0.535156f, - 0.730469f, -0.957031f, -0.509766f, 0.602539f, 0.938477f, - -0.640625f, 0.836914f, -1.13672f, -0.56543f, 0.450195f, - 0.737305f, -0.449219f, 0.649414f, -1.08105f, -0.364258f, - 0.338867f, 0.667969f, -0.533203f, 0.654297f, -1.0918f, - -0.505859f, 0.422852f, 0.745117f, -0.443359f, 0.319336f, - -0.753906f, -0.563477f, 0.374023f, 0.640625f, -0.435547f, - 0.220703f, -0.868164f, -0.701172f, 0.317383f, 0.702148f, - -0.527344f, 0.138672f, -0.848633f, -0.431641f, 0.220703f, - 0.329102f, -0.25293f, -0.232422f, -0.875977f, -0.442383f, - 0.550781f, 0.783203f, -0.441406f, 0.160156f, -0.107422f, - 0.0683594f, 0.317383f, 1.12012f, -1.02344f, 0.322266f, - -0.469727f, -0.151367f, 0.43457f, 0.65625f, -0.745117f, - 0.216797f, -1.03223f, -0.200195f, 0.240234f, 1.11035f, - -0.90332f, 0.239258f, 0.0429688f, -0.228516f, 0.00390625f, - 0.836914f, -0.770508f, -0.280273f, -0.18457f, 0.0117188f, - 0.214844f, 0.767578f, -0.774414f, -0.0703125f, -0.954102f, - -0.508789f, -0.046875f, 1.00391f, -0.930664f, 0.0292969f, - 0.407227f, -0.519531f, 0.0361328f, 0.753906f, -0.777344f, - -0.0214844f, 0.741211f, -0.27832f, -0.0332031f, 1.15625f, - -0.862305f, -0.115234f, 0.821289f, -0.598633f, 0.00488281f, - 0.929688f, -1.01172f, -0.0996094f, 0.351562f, -0.524414f, - 0.118164f, 1.1709f, -0.938477f, 0.00878906f, 0.948242f, - -0.475586f, 0.443359f, 0.893555f, -0.597656f, 0.0107422f, - 0.558594f, -0.87207f, 0.0810547f, 0.487305f, -0.808594f, - 0.212891f, 0.0878906f, -0.612305f, 0.263672f, 0.400391f, - -0.709961f, 0.380859f, -0.0839844f, -0.566406f, 0.466797f, - 0.445312f, -0.769531f, 0.636719f, -0.273438f, -0.648438f, - 0.34375f, 0.56543f, -0.829102f, 0.417969f, -0.272461f, - -0.746094f, 0.202148f, 0.421875f, -0.445312f, 0.229492f, - 0.178711f, -0.408203f, 0.477539f, 0.693359f, -0.675781f, - 0.145508f, 0.37207f, -0.576172f, 0.0449219f, 0.845703f, - -0.920898f, -0.0185547f, 0.487305f, -0.460938f, 0.0253906f, - 1.04785f, -0.87207f, 0.176758f, 0.356445f, -0.217773f, - 0.0332031f, 0.945312f, -0.556641f, -0.110352f, 0.725586f, - 0.0810547f, -0.0361328f, 1.11426f, -0.396484f, 0.00488281f, - 0.743164f, 0.27832f, 0.0175781f, 0.839844f, -0.0371094f, - -0.00878906f, 0.964844f, 0.547852f, 0.0224609f, 0.518555f, - 0.386719f, -0.0585938f, 1.11816f, 0.712891f, 0.19043f, - 0.523438f, 0.429688f, -0.179688f, 1.18164f, 0.40332f, - 0.241211f, 1.19043f, -0.0234375f, 0.119141f, 0.90918f, - -0.078125f, 0.250977f, 0.973633f, -0.277344f, 0.227539f, - 0.908203f, -0.232422f, 0.269531f, 0.807617f, -0.59668f, - 0.253906f, 0.398438f, -0.506836f, 0.255859f, 0.694336f, - -0.742188f, 0.345703f, 0.412109f, -0.576172f, 0.189453f, - 0.708984f, -0.808594f, 0.230469f, 0.242188f, -0.550781f, - 0.0693359f, 0.695312f, -0.856445f, -0.0253906f, 0.177734f, - -0.6875f, -0.00976562f, 0.731445f, -0.991211f, -0.03125f, - 0.0175781f, -0.805664f, -0.192383f, 0.827148f, -0.947266f, - 0.0820312f, 0.254883f, -0.504883f, -0.259766f, 0.87207f, - -0.693359f, -0.345703f, 0.639648f, -0.162109f, -0.443359f, - 1.05176f, -0.595703f, -0.496094f, 0.485352f, -0.0380859f, - -0.490234f, 0.763672f, -0.382812f, -0.634766f, 0.369141f, - 0.136719f, -0.650391f, 0.536133f, -0.126953f, -0.901367f, - 0.275391f, 0.155273f, -0.75293f, 0.476562f, -0.183594f, - -1.00488f, 0.206055f, -0.0908203f, -1.06836f, 0.3125f, - -0.183594f, -1.30762f, 0.37793f, -0.185547f, -0.885742f, - 0.496094f, -0.250977f, -1.14941f, 0.0517578f, -0.242188f, - -0.753906f, 0.395508f, -0.133789f, -1.10156f, 0.183594f, - -0.398438f, -0.767578f, 0.951172f, -0.359375f, -0.866211f, - 0.373047f, -0.0224609f, -0.0537109f, 0.921875f, -0.263672f, - -0.251953f, 0.455078f, 0.230469f, 0.485352f, 0.84082f, - 0.0351562f, 0.0810547f, 0.554688f, 0.186523f, 0.774414f, - 0.720703f, 0.381836f, 0.71875f, 0.495117f, 0.530273f, - 0.771484f, 0.90332f, 0.34668f, 0.897461f, 0.456055f, - 0.575195f, 0.560547f, 0.133789f, 0.62793f, 0.795898f, - 0.400391f, 0.594727f, 0.577148f, -0.142578f, 0.691406f, - 0.770508f, 0.12793f, 0.679688f, 0.751953f, -0.201172f, - 0.728516f, 0.805664f, -0.0175781f, 0.46875f, 0.655273f, - -0.608398f, 0.750977f, 0.540039f, -0.0166016f, 0.30957f, - 0.755859f, -0.563477f, 0.609375f, 0.763672f, -0.310547f, - 0.0791016f, 0.668945f, -0.575195f, 0.398438f, 0.767578f, - -0.47168f, -0.12793f, 0.631836f, -0.768555f, 0.293945f, - 0.760742f, -0.743164f, -0.311523f, 0.509766f, -0.755859f, - 0.15918f, 0.614258f, -0.832031f, -0.575195f, 0.448242f, - -0.771484f, -0.0605469f, 0.341797f, -0.652344f, -0.8125f, - 0.262695f, -0.205078f, -0.541992f, 0.337891f, -0.8125f, - -1.20996f, 0.179688f, -0.311523f, -0.682617f, 0.0556641f, - -0.944336f, -1.29102f, 0.09375f, 0.503906f, -0.87793f, - -0.0742188f, -0.805664f, -1.53613f, -0.107422f, 0.50293f, - -0.807617f, -0.423828f, 0.0888672f, -0.847656f, -0.342773f, - 0.719727f, -0.87793f, -0.336914f, 0.115234f, -0.500977f, - -0.487305f, 0.395508f, -0.398438f, -0.624023f, 0.3125f, - -0.0693359f, -0.605469f, 0.429688f, -0.283203f, -0.813477f, - 0.246094f, 0.0898438f, -0.764648f, 0.356445f, -0.106445f, - -1.05371f, 0.595703f, 0.251953f, -0.729492f, 0.336914f, - -0.0595703f, -1.06445f, 0.824219f, 0.320312f, -0.50293f, - 0.459961f, -0.161133f, -0.820312f, 0.516602f, 0.410156f, - -0.401367f, 0.407227f, -0.106445f, -0.740234f, 0.546875f, - 0.663086f, -0.170898f, 0.574219f, -0.419922f, -0.271484f, - -0.0273438f, 0.239258f, -0.0361328f, 0.80957f, -0.576172f, - 0.0664062f, 0.0332031f, 0.181641f, 0.245117f, 1.06641f, - -0.826172f, 0.30957f, -0.241211f, 0.03125f, 0.422852f, - 1.14648f, -0.916992f, 0.672852f, -0.242188f, 0.0234375f, - 0.425781f, 1.16895f, -1.08887f, 0.748047f, -0.384766f, - 0.102539f, 0.457031f, 0.992188f, -0.896484f, 0.65625f, - -0.144531f, 0.0332031f, 0.295898f, 0.8125f, -0.706055f, - 0.166016f, -0.237305f, 0.0996094f, 0.130859f, 0.723633f, - -0.769531f, -0.125f, -0.339844f, -0.277344f, -0.00390625f, - 1.2959f, -0.999023f, 0.0185547f, 0.0527344f, 0.270508f, - 0.104492f, 1.05469f, -1.0918f, 0.205078f, 0.00390625f, - 0.141602f, 0.000976562f, 1.15039f, -1.14844f, 0.0664062f, - -0.0566406f, 0.0732422f, 0.0302734f, 1.08398f, -1.04004f, - 0.124023f, -0.114258f, 0.19043f, 0.0263672f, 0.985352f, - -1.00293f, 0.0634766f, -0.0585938f, 0.257812f, -0.0527344f, - 0.96875f, -0.990234f, -0.0361328f, -0.179688f, 0.266602f, - -0.219727f, 0.882812f, -0.879883f, -0.289062f, -0.00292969f, - 0.351562f, -0.313477f, 0.826172f, -0.84668f, -0.322266f, - 0.337891f, 0.478516f, -0.426758f, 0.594727f, -0.621094f, - -0.435547f, 0.676758f, 0.47168f, -0.432617f, 0.333008f, - -0.338867f, -0.767578f, 0.419922f, 0.576172f, -0.673828f, - 0.321289f, -0.53125f, -0.96582f, 0.290039f, 0.426758f, - -0.526367f, 0.230469f, -0.508789f, -1.05859f, 0.195312f, - 0.493164f, -0.479492f, 0.78418f, -0.992188f, -0.453125f, - -0.185547f, 0.375977f, -0.291992f, 0.77832f, -0.884766f, - -0.361328f, 0.438477f, -0.118164f, -0.222656f, 0.923828f, - -0.796875f, 0.0234375f, -0.375f, 0.0332031f, -0.216797f, - 0.908203f, -0.984375f, -0.295898f, -0.384766f, 0.0234375f, - -0.305664f, 1.12695f, -1.04004f, -0.344727f, -0.136719f, - 0.119141f, -0.385742f, 1.06738f, -1.01855f, -0.245117f, - -0.106445f, -0.114258f, -0.365234f, 0.962891f, -0.923828f, - -0.430664f, -0.637695f, -0.347656f, -0.436523f, 0.702148f, - -0.547852f, -0.618164f, -0.447266f, -0.241211f, -0.462891f, - 0.729492f, -0.609375f, -0.578125f, -0.486328f, -0.0556641f, - -0.536133f, 0.50293f, -0.480469f, -0.526367f, -0.210938f, - -0.0585938f, -0.637695f, 0.723633f, -0.319336f, -0.348633f, - -0.00292969f, -0.305664f, -0.629883f, 0.431641f, 0.266602f, - -0.612305f, -0.260742f, 0.0166016f, -0.65332f, -0.272461f, - 0.800781f, -1.09863f, -0.166992f, -0.0859375f, -0.520508f, - -0.473633f, 0.586914f, -0.696289f, -0.682617f, -0.149414f, - 0.198242f, -0.805664f, 1.1377f, 0.444336f, -0.458984f, - -0.577148f, 0.522461f, -0.683594f, 1.25586f, 0.827148f, - -0.249023f, -0.851562f, 0.84668f, -0.448242f, 1.26953f, - 0.855469f, -0.155273f, -0.765625f, 1.0f, -0.337891f, - 0.973633f, 0.660156f, -0.0859375f, -0.476562f, 1.11035f, - -0.00976562f, 0.547852f, 0.958984f, -0.34082f, -0.504883f, - 0.853516f, 0.0664062f, 0.378906f, 0.758789f, -0.749023f, - -0.509766f, 0.739258f, 0.499023f, -0.144531f, 0.84668f, - -0.931641f, -0.329102f, 0.740234f, 0.791992f, -0.168945f, - 0.594727f, -0.435547f, -0.268555f, 0.336914f, 0.817383f, - -0.430664f, -0.0253906f, -0.735352f, -0.0683594f, 0.152344f, - 0.725586f, -0.68457f, -0.294922f, -1.25391f, -0.125f, - 0.0917969f, 0.907227f, -0.633789f, -0.28125f, -0.222656f, - 0.0f, 0.188477f, 1.06445f, -0.929688f, 0.144531f, - -0.139648f, -0.00390625f, -0.21582f, 1.21387f, -0.952148f, - -0.0253906f, -0.389648f, 0.148438f, -0.283203f, 1.14844f, - -0.890625f, -0.204102f, -0.222656f, -0.0332031f, -0.451172f, - 0.625f, -0.486328f, -0.716797f, -0.103516f, 0.265625f, - -0.667969f, 0.231445f, -0.385742f, -0.977539f, 0.111328f, - 0.222656f, -0.766602f, 0.300781f, -0.390625f, -1.07129f, - 0.230469f, 0.318359f, -0.787109f, 0.427734f, -0.512695f, - -0.886719f, 0.240234f, 0.260742f, -0.647461f, 0.566406f, - -0.686523f, -0.723633f, -0.198242f, 0.0722656f, -0.3125f, - 0.771484f, -0.725586f, -0.478516f, -0.176758f, -0.113281f, - -0.262695f, 0.78125f, -0.644531f, -0.210938f, -0.0126953f, - -0.317383f, 0.0673828f, 0.944336f, -0.764648f, 0.1875f, - -0.636719f, -0.401367f, 0.118164f, 0.982422f, -0.826172f, - 0.105469f, -1.0625f, -0.298828f, 0.0537109f, 0.949219f, - -0.788086f, 0.176758f, -0.611328f, -0.0322266f, 0.0439453f, - 0.885742f, -0.730469f, 0.301758f, -0.463867f, -0.144531f, - -0.180664f, 1.08398f, -0.97168f, -0.470703f, 0.128906f, - 0.0146484f, -0.112305f, 0.889648f, -0.946289f, -0.165039f, - -1.34277f, -0.258789f, -0.211914f, 0.962891f, -0.844727f, - -0.588867f, 0.144531f, -0.228516f, -0.207031f, 0.974609f, - -0.848633f, -0.0273438f, -0.570312f, -0.228516f, 0.00195312f, - 1.03125f, -0.977539f, -0.0605469f, -0.733398f, -0.0908203f, - 0.0996094f, 0.856445f, -0.854492f, -0.000976562f, -0.458008f, - -0.135742f, 0.222656f, 1.34082f, -1.13574f, 0.639648f, - 0.015625f, -0.234375f, 0.136719f, 0.835938f, -0.822266f, - -0.114258f, -0.673828f, -0.186523f, 0.169922f, 0.925781f, - -0.839844f, 0.175781f, -0.394531f, 0.224609f, -0.0458984f, - 0.94043f, -0.964844f, -0.0556641f, -0.15332f, 0.163086f, - -0.0175781f, 0.944336f, -0.951172f, -0.0478516f, -0.302734f, - 0.117188f, -0.00683594f, 0.973633f, -0.970703f, -0.0810547f, - -0.301758f, 0.09375f, -0.000976562f, 1.01953f, -0.978516f, - 0.0292969f, -0.293945f, 0.0683594f, -0.00683594f, 1.0127f, - -0.966797f, -0.0175781f, -0.314453f, 0.181641f, 0.0126953f, - 0.982422f, -0.990234f, 0.03125f, -0.194336f, 0.155273f, - -0.00292969f, 0.962891f, -0.932617f, -0.00390625f, -0.0976562f, - 0.144531f, -0.0205078f, 0.913086f, -0.914062f, -0.0908203f, - -0.296875f, 0.166992f, -0.015625f, 0.930664f, -0.950195f, - -0.0888672f, -0.28418f, 0.196289f, -0.0107422f, 0.953125f, - -0.960938f, -0.0273438f, -0.195312f, 0.125f, 0.0126953f, - 0.986328f, -0.951172f, 0.0634766f, -0.231445f, 0.162109f, - -0.0136719f, 0.981445f, -0.974609f, -0.0449219f, -0.0761719f, - 0.186523f, -0.015625f, 0.950195f, -0.962891f, -0.0576172f, - -0.162109f, 0.154297f, -0.0292969f, 0.970703f, -0.973633f, - -0.0136719f, -0.394531f, 0.102539f, -0.00878906f, 0.970703f, - -0.915039f, 0.0546875f, -0.313477f, 0.110352f, -0.0234375f, - 0.947266f, -0.922852f, -0.139648f, -0.181641f, 0.12207f, - 0.0625f, 0.780273f, -0.899414f, -0.84375f, -0.0888672f, - -0.318359f, 1.00781f, 0.888672f, 0.27832f, 0.0195312f, - -1.08594f, 0.137695f, 0.56543f, 1.12891f, -0.235352f, - 1.65039f, -0.0820312f, 0.100586f, 0.987305f, 0.261719f, - -0.0615234f, 1.32227f, 0.669922f, 0.0f, 1.04102f, - 0.231445f, -0.174805f, 1.11426f, -0.261719f, -0.0527344f, - 0.958008f, 0.332031f, -0.28418f, 1.26953f, -0.612305f, - 0.208984f, 0.964844f, 1.15625f, -0.486328f, 2.0f, - -0.760742f, 0.0458984f, 1.44629f, 1.21289f, 0.924805f, - 1.1875f, -0.259766f, 0.114258f, 0.210938f, 0.486328f, - -0.422852f, -0.984375f, 1.08789f, 0.453125f, -0.229492f, - 0.457031f, -0.682617f, -0.500977f, 0.210938f, 0.391602f, - -0.303711f, 0.725586f, -0.80957f, -0.391602f, 0.0976562f, - 0.958984f, 0.0185547f, 1.69922f, -1.36035f, 1.98242f, - -0.392578f, -0.461914f, -0.37793f, -0.0712891f, 0.928711f, - -1.60254f, 0.133789f, -0.0419922f, -1.12109f, -0.201172f, - 0.0732422f, -1.99902f, 0.629883f, -0.174805f, -0.894531f, - 0.0742188f, -0.147461f, -1.23633f, -0.259766f, 0.0410156f, - -1.00879f, -0.0166016f, -0.0205078f, -1.99902f, 0.267578f, - -0.0664062f, -0.164062f, 0.511719f, 0.825195f, -1.21191f, - -0.515625f, 0.46875f, 0.0898438f, 1.09766f, -0.144531f, - 1.59375f, 0.166016f, 0.428711f, 0.294922f, 0.8125f, - -0.770508f, 0.535156f, 0.280273f, 0.231445f, 0.504883f, - 0.864258f, -0.884766f, 0.524414f, -0.183594f, 0.0820312f, - 0.713867f, 0.405273f, -0.520508f, -0.326172f, 0.0126953f, - -0.310547f, 1.38086f, 0.831055f, 0.380859f, 1.3125f, - -1.60645f, 0.151367f, 1.01953f, 0.580078f, -0.0283203f, - 2.0f, 1.03516f, -0.0634766f, 1.03418f, 0.332031f, - -0.0859375f, 1.32129f, -0.234375f, 0.0917969f, 1.49219f, - 0.30957f, -0.118164f, 1.76953f, -0.717773f, 0.174805f, - 1.59863f, 0.0947266f, 1.1875f, 0.429688f, 0.442383f, - 0.00976562f, 0.435547f, 0.345703f, -0.114258f, 0.238281f, - -0.689453f, 0.30957f, 0.0732422f, 0.606445f, -0.650391f, - -0.0947266f, -0.03125f, 0.183594f, -0.144531f, 0.746094f, - -0.793945f, -0.574219f, -0.0742188f, 0.196289f, -0.199219f, - 1.13867f, -1.11816f, -0.227539f, -0.462891f, 0.0517578f, - -0.0341797f, 1.18945f, -1.1084f, -0.0283203f, -0.342773f, - 0.174805f, -0.0078125f, 1.05176f, -1.03906f, 0.0253906f, - -0.375977f, -0.169922f, 0.00292969f, 0.837891f, -0.716797f, - -0.0205078f, -0.373047f, 0.293945f, 0.0175781f, 0.833984f, - -0.916016f, -0.0996094f, -0.149414f, 0.200195f, -0.00195312f, - 0.865234f, -0.916016f, -0.0117188f, -0.390625f, 0.290039f, - 0.0234375f, 0.985352f, -0.987305f, 0.0439453f, -0.214844f, - 0.0917969f, 0.0615234f, 1.02832f, -1.00684f, 0.152344f, - -0.452148f, 0.0615234f, -0.00585938f, 1.02148f, -0.976562f, - -0.0927734f, -0.286133f, 0.189453f, -0.0644531f, 1.02539f, - -1.02246f, 0.0166016f, -0.243164f, 0.109375f, -0.09375f, - 0.981445f, -0.931641f, 0.0458984f, -0.460938f, 0.0537109f, - -0.0429688f, 1.05859f, -0.850586f, 0.0771484f, -0.0507812f, - 0.108398f, -0.177734f, 0.779297f, -0.74707f, -0.378906f, - -0.413086f, -0.205078f, -0.0488281f, 0.946289f, -0.760742f, - -0.180664f, -0.228516f, -0.208008f, -0.0615234f, 1.05371f, - -0.953125f, -0.34668f, -1.16797f, -0.0322266f, -0.276367f, - 1.06641f, -0.863281f, -0.0244141f, -0.290039f, -0.0429688f, - 0.0439453f, 1.28223f, -1.06348f, 0.181641f, -0.514648f, - -0.0214844f, 0.0f, 0.861328f, -0.738281f, -0.0449219f, - 0.0722656f, 0.125f, 0.193359f, 1.15039f, -1.0957f, - 0.225586f, -0.137695f, 0.12207f, -0.0400391f, 0.732422f, - -0.818359f, -0.40918f, -0.672852f, -0.425781f, 0.839844f, - 0.856445f, 0.198242f, -0.363281f, 0.206055f, -0.214844f, - 1.20215f, 0.943359f, 0.0195312f, 2.0f, 0.874023f, - 0.0839844f, 0.827148f, 0.587891f, -0.384766f, 1.57715f, - 0.108398f, -0.116211f, 0.952148f, 0.246094f, -0.336914f, - 0.463867f, -0.740234f, 0.0185547f, 0.950195f, 0.55957f, - -0.442383f, 1.09668f, 0.0585938f, 0.132812f, 1.37695f, - 2.0f, -0.59375f, 2.0f, -0.676758f, -0.199219f, - -0.0205078f, 0.268555f, -0.5f, -1.94629f, 1.2832f, - 0.0078125f, -0.201172f, 0.674805f, -0.708984f, -0.490234f, - -0.515625f, 0.0439453f, -0.0830078f, 1.14355f, -1.01953f, - -0.0224609f, -0.282227f, 0.0214844f, -0.078125f, 1.09668f, - -0.961914f, 0.0253906f, -0.56543f, 0.30957f, 0.964844f, - 1.56836f, -0.272461f, 1.91309f, -0.53418f, -0.695312f, - -0.878906f, -0.0146484f, 0.277344f, -1.6416f, 0.0244141f, - 0.0898438f, -0.785156f, 0.229492f, -0.259766f, -1.06055f, - -0.241211f, 0.0224609f, -0.769531f, 0.748047f, -0.680664f, - -0.629883f, -0.549805f, -0.195312f, -0.796875f, -0.399414f, - 0.0859375f, -1.99902f, 0.24707f, 0.208984f, 0.563477f, - 1.91797f, 0.0585938f, 2.0f, -0.990234f, 0.327148f, - -0.0917969f, 1.16797f, -0.94043f, 0.623047f, -1.1748f, - -0.0205078f, -0.0449219f, 0.883789f, -0.905273f, -0.370117f, - -0.601562f, 0.0332031f, -0.0527344f, 0.928711f, -0.833984f, - -0.180664f, -0.267578f, 0.0351562f, -0.0175781f, 0.998047f, - -0.922852f, -0.000976562f, -0.371094f, 0.0341797f, -0.0166016f, - 0.977539f, -0.900391f, -0.00292969f, -0.37207f, 0.0449219f, - -0.0439453f, 0.989258f, -0.904297f, -0.0576172f, -0.37207f, - 0.270508f, -0.368164f, 0.0576172f, -0.607422f, -1.95508f, - -0.182617f, -0.390625f, 1.62598f, 1.52734f, 1.2793f, - 2.0f, -1.99902f, 0.226562f, 1.01465f, 0.669922f, - -0.373047f, 1.71484f, 1.99707f, -0.0654297f, 1.00391f, - 0.330078f, -0.432617f, 0.704102f, -0.96875f, 0.0800781f, - 0.964844f, 0.702148f, -0.5625f, 1.39746f, -0.203125f, - 0.255859f, 1.74512f, 1.52539f, 0.417969f, 2.0f, - -0.0976562f, -0.482422f, 0.09375f, 0.151367f, -0.328125f, - -1.88867f, -0.0595703f, 0.117188f, 0.0751953f, 0.870117f, - -0.870117f, 0.046875f, -0.280273f, 0.125f, 0.124023f, - 1.0791f, -0.964844f, 0.338867f, -0.0791016f, 0.0751953f, - 0.12207f, 0.920898f, -0.888672f, 0.0273438f, -0.250977f, - 0.00488281f, 0.165039f, 1.01074f, -0.944336f, 0.137695f, - -0.387695f, -0.142578f, 0.238281f, 1.77246f, -1.42285f, - 0.90625f, -0.856445f, 0.0556641f, -0.219727f, -0.785156f, - 1.47266f, -1.99902f, 1.27246f, -0.132812f, -0.746094f, - 0.172852f, -0.0830078f, -1.3584f, 0.638672f, 0.0175781f, - -0.786133f, 0.754883f, -0.729492f, -0.808594f, -0.291992f, - 0.170898f, -0.746094f, 0.623047f, -0.667969f, -0.743164f, - -0.241211f, 0.0693359f, -0.725586f, 0.495117f, -0.545898f, - -0.969727f, -0.131836f, 0.0234375f, -0.52832f, 0.280273f, - -0.327148f, -1.0498f, -0.210938f, -0.253906f, 0.234375f, - 0.661133f, -0.0332031f, -0.708008f, -0.458984f, 0.31543f, - 0.480469f, 1.59082f, -1.22266f, 1.41602f, -0.270508f, - 0.263672f, 0.318359f, 1.21289f, -1.12207f, 0.853516f, - -0.272461f, 0.158203f, 1.84766f, 2.0f, 0.341797f, - 2.0f, -0.788086f, -0.264648f, -0.326172f, -1.25977f, - 0.842773f, -1.99902f, -0.947266f, 0.249023f, -0.642578f, - 0.745117f, -0.744141f, -0.404297f, -0.266602f, 0.0898438f, - -0.568359f, 0.501953f, -0.494141f, -0.858398f, 0.0722656f, - -0.543945f, 1.16895f, 1.12012f, 1.47461f, -1.12988f, - -0.27832f, 0.53125f, 0.875f, 0.845703f, -0.318359f, - 1.68555f, 1.29199f, -0.00195312f, 0.861328f, 0.601562f, - -0.519531f, 1.16211f, -1.05957f, 0.0507812f, 0.904297f, - 0.625977f, -0.525391f, 1.16797f, -0.163086f, 0.125977f, - 1.99902f, 2.0f, 2.0f, 2.0f, -0.00195312f, - -1.11719f, -0.3125f, -0.320312f, 0.585938f, -1.99902f, - 0.647461f, 0.198242f, -0.538086f, 0.993164f, -0.897461f, - -0.227539f, -0.354492f, 0.0976562f, -0.416016f, 0.623047f, - -0.682617f, -0.832031f, -0.223633f, -0.160156f, 0.0751953f, - -0.791992f, 1.13379f, -1.99902f, -0.755859f, 0.669922f, - 1.02637f, 1.26758f, -0.293945f, 2.0f, 1.93457f, - -0.0126953f, 0.773438f, 0.475586f, -0.59375f, 0.329102f, - -0.588867f, 0.113281f, 0.740234f, 0.749023f, -0.716797f, - 0.941406f, -0.0878906f, 0.71875f, 1.8125f, 2.0f, - -0.289062f, 2.0f, -1.01074f, 0.0117188f, -0.183594f, - -0.969727f, 0.893555f, -1.99902f, 0.333008f, 0.188477f, - -0.643555f, 0.504883f, -0.511719f, -0.804688f, -0.957031f, - 0.0546875f, -0.305664f, -0.0449219f, -0.145508f, -1.875f, - 0.0996094f, -0.155273f, 1.59668f, 1.5293f, 1.46973f, - 2.0f, -1.9834f, 0.375f, 1.20508f, 0.736328f, - -0.399414f, 2.0f, 2.0f, 0.123047f, 0.834961f, - 1.04004f, -0.808594f, 1.31934f, -0.634766f, 0.548828f, - 0.129883f, -1.64746f, 2.0f, -1.99902f, 0.819336f, - 0.0273438f, -0.254883f, 0.722656f, -0.691406f, -0.464844f, - -1.05566f, 0.0634766f, -0.206055f, 1.02148f, -0.90332f, - 0.0595703f, -0.03125f, 0.129883f, -0.177734f, 0.697266f, - -0.713867f, -0.351562f, -0.169922f, -0.119141f, -0.172852f, - 1.01855f, -0.989258f, -0.12793f, -0.670898f, -0.146484f, - -0.261719f, 1.16602f, -1.05664f, -0.302734f, -0.25293f, - -0.0458984f, -0.198242f, 0.90625f, -0.876953f, -0.144531f, - -0.424805f, -0.151367f, -0.147461f, 0.926758f, -0.835938f, - -0.191406f, -0.326172f, -0.128906f, -0.216797f, 0.910156f, - -0.851562f, -0.291992f, -0.549805f, -0.0517578f, -0.0869141f, - 1.07715f, -0.977539f, -0.0361328f, -0.418945f, -0.148438f, - -0.133789f, 0.907227f, -0.836914f, -0.213867f, -0.768555f, - -0.0664062f, 0.182617f, 1.0498f, -0.915039f, 0.400391f, - -0.523438f, 0.015625f, 0.0f, 1.13184f, -1.09961f, - -0.244141f, -0.330078f, -0.115234f, 0.0166016f, 0.944336f, - -0.868164f, -0.430664f, -0.246094f, -0.0185547f, -0.00976562f, - 0.819336f, -0.822266f, -0.380859f, -1.1709f, 0.0605469f, - -0.0498047f, 0.777344f, -0.703125f, 0.0800781f, -0.451172f, - 0.304688f, 0.0517578f, 0.825195f, -0.771484f, 0.145508f, - 0.495117f, -0.0888672f, -0.243164f, 1.48145f, -1.22168f, - 0.0615234f, -0.192383f, -0.0537109f, 0.0195312f, 1.21582f, - -1.06836f, 0.175781f, -0.394531f, 0.237305f, -0.0126953f, - 0.800781f, -0.920898f, -0.12207f, -0.391602f, -0.0917969f, - -0.0791016f, 1.08008f, -1.03613f, -0.0654297f, -0.423828f, - 0.0478516f, -0.0253906f, 0.873047f, -0.884766f, -0.0722656f, - -0.579102f, 0.0136719f, -0.0917969f, 0.954102f, -0.922852f, - -0.172852f, -0.244141f, 0.0f, -0.141602f, 0.929688f, - -0.894531f, -0.179688f, -0.291992f, 0.0283203f, -0.0947266f, - 0.961914f, -0.926758f, -0.135742f, -0.329102f, 0.0576172f, - -0.0351562f, 0.999023f, -0.958984f, -0.0498047f, -0.248047f, - 0.0869141f, -0.078125f, 1.01074f, -0.954102f, 0.00976562f, - -0.217773f, 0.0986328f, -0.0556641f, 0.916992f, -0.914062f, - -0.136719f, -0.219727f, 0.0488281f, -0.139648f, 0.985352f, - -0.952148f, -0.152344f, -0.286133f, 0.0166016f, -0.0917969f, - 1.0459f, -0.972656f, -0.0605469f, -0.228516f, 0.0507812f, - -0.0810547f, 0.956055f, -0.9375f, -0.18457f, -0.275391f, - 0.0703125f, -0.0986328f, 0.948242f, -0.928711f, -0.162109f, - -0.333008f}; + -0.166016f, -0.00488281f, 0.924805f, -0.770508f, -0.0488281f, + -0.510742f, -0.199219f, -0.0078125f, 0.953125f, -0.782227f, + -0.0244141f, -0.652344f, -0.177734f, -0.0136719f, 0.936523f, + -0.772461f, -0.0527344f, -0.59375f, -0.176758f, -0.00878906f, + 0.9375f, -0.777344f, -0.0419922f, -0.637695f, -0.165039f, + -0.00878906f, 0.942383f, -0.782227f, -0.046875f, -0.613281f, + -0.180664f, -0.00976562f, 0.943359f, -0.777344f, -0.0419922f, + -0.601562f, -0.189453f, -0.00488281f, 0.943359f, -0.776367f, + -0.0263672f, -0.613281f, -0.166992f, -0.00488281f, 0.935547f, + -0.78125f, -0.0380859f, -0.609375f, -0.176758f, -0.00878906f, + 0.947266f, -0.790039f, -0.0576172f, -0.585938f, -0.173828f, + -0.0126953f, 0.93457f, -0.780273f, -0.0654297f, -0.666016f, + -0.169922f, -0.00195312f, 0.928711f, -0.775391f, -0.0351562f, + -0.561523f, -0.193359f, 0.0f, 0.941406f, -0.795898f, + -0.0478516f, -0.640625f, -0.162109f, -0.00585938f, 0.917969f, + -0.768555f, -0.0146484f, -0.685547f, -0.166992f, -0.0136719f, + 0.921875f, -0.755859f, -0.0166016f, -0.425781f, -0.175781f, + -0.0810547f, 1.00098f, -0.802734f, -0.117188f, -0.585938f, + -0.210938f, 0.0214844f, 0.881836f, -0.750977f, -0.0302734f, + -0.677734f, -0.285156f, 0.00976562f, 0.967773f, -0.763672f, + -0.0283203f, -0.850586f, -0.222656f, -0.0136719f, 0.943359f, + -0.763672f, -0.0507812f, -0.640625f, -0.236328f, 0.0859375f, + 0.892578f, -0.742188f, 0.0302734f, -0.484375f, -0.269531f, + 0.0263672f, 0.913086f, -0.714844f, -0.00585938f, -0.745117f, + -0.275391f, 0.0927734f, 0.977539f, -0.776367f, -0.078125f, + -0.750977f, -0.155273f, -0.0341797f, 1.2334f, -1.06445f, + -0.0478516f, -0.823242f, -0.196289f, 0.046875f, 1.19141f, + -1.00391f, -0.140625f, -0.541016f, 0.0917969f, 0.21582f, + 0.717773f, -0.764648f, -0.0341797f, -0.607422f, -0.0351562f, + 0.0888672f, 0.207031f, -0.214844f, -0.18457f, -0.0664062f, + -0.0898438f, 0.0556641f, 0.418945f, -0.232422f, 0.43457f, + 0.0361328f, 0.143555f, 0.376953f, 1.23633f, -1.09082f, + 0.529297f, 0.0507812f, 0.205078f, 0.438477f, 1.66602f, + -1.59668f, 0.325195f, -1.20996f, -0.0791016f, 0.404297f, + 1.50977f, -1.40918f, 0.31543f, -1.30273f, -0.0654297f, + 0.141602f, 0.699219f, -0.589844f, 0.0732422f, -0.27832f, + 0.00488281f, 0.00683594f, 0.0566406f, -0.0410156f, -0.0292969f, + -0.0234375f, -0.0488281f, -0.00195312f, -0.0292969f, 0.0849609f, + -0.139648f, 0.0585938f, 0.677734f, 0.667969f, 1.36523f, + -1.11816f, 0.412109f, 0.844727f, 0.142578f, 0.790039f, + 1.73145f, -1.68066f, 0.464844f, -1.29492f, -0.0800781f, + 0.803711f, 0.879883f, -0.765625f, -0.0400391f, -0.616211f, + -0.170898f, 0.879883f, 0.510742f, 0.158203f, 0.381836f, + -0.270508f, -0.0693359f, 0.651367f, 0.431641f, 0.104492f, + 0.991211f, -0.0634766f, -0.0478516f, 0.750977f, 0.283203f, + -0.0332031f, 1.52051f, -0.00195312f, -0.201172f, 1.08984f, + 0.173828f, 0.0849609f, 1.44141f, -0.214844f, -0.0107422f, + 1.29785f, 0.520508f, 0.00488281f, 1.73047f, -0.523438f, + 0.136719f, 1.42188f, 0.987305f, 0.0527344f, 1.74707f, + -0.525391f, 0.34668f, 0.469727f, 0.428711f, 0.114258f, + -0.788086f, 0.177734f, 0.400391f, -0.106445f, 0.328125f, + -0.566406f, -0.948242f, 0.670898f, 0.467773f, -0.21875f, + 0.55957f, -0.767578f, -0.232422f, 0.195312f, 0.625f, + -0.271484f, 0.865234f, -0.765625f, 0.299805f, 0.0703125f, + 0.378906f, -0.526367f, 0.548828f, -0.231445f, -0.569336f, + 0.455078f, 0.303711f, -0.866211f, -0.485352f, 0.566406f, + -1.60547f, 0.481445f, 0.183594f, -0.782227f, -0.260742f, + 0.243164f, -1.41504f, 0.373047f, 0.172852f, -0.935547f, + -0.412109f, 0.133789f, -1.69727f, 0.178711f, 0.407227f, + -0.952148f, -0.227539f, 0.0751953f, -1.67188f, 0.339844f, + 0.498047f, -0.795898f, 0.209961f, 0.177734f, -1.3916f, + 0.458984f, 0.295898f, 0.0390625f, 0.697266f, 0.258789f, + -0.0703125f, -0.131836f, 0.56543f, 0.250977f, 0.913086f, + -0.353516f, 0.90332f, 0.191406f, 0.708008f, 0.352539f, + 0.853516f, -0.839844f, 0.955078f, 0.636719f, 0.657227f, + 0.389648f, 0.620117f, -0.725586f, 0.43457f, 0.485352f, + 0.424805f, 0.479492f, 0.287109f, -0.505859f, -0.209961f, + 0.0927734f, 0.21582f, 0.709961f, 0.492188f, -0.413086f, + -0.0869141f, 0.0673828f, -0.119141f, 1.20508f, 0.392578f, + 0.229492f, 0.927734f, -0.297852f, 0.142578f, 1.0293f, + 0.430664f, 0.0449219f, 1.71875f, -0.0283203f, 0.0107422f, + 1.18164f, 0.0517578f, 0.0751953f, 1.80273f, -0.0693359f, + -0.19043f, 1.1748f, 0.236328f, 0.0839844f, 1.78711f, + -0.472656f, -0.270508f, 1.10254f, 0.964844f, 0.118164f, + 1.75684f, -0.901367f, -0.211914f, 1.11133f, 0.65625f, + 0.308594f, 0.142578f, 0.396484f, 0.239258f, 0.0800781f, + 0.973633f, -0.824219f, -0.25293f, 0.485352f, 0.351562f, + -0.0771484f, 1.08984f, -0.632812f, 0.240234f, -0.258789f, + 0.436523f, -0.514648f, 0.491211f, 0.0664062f, -0.244141f, + -0.148438f, -0.171875f, -0.477539f, -0.459961f, 1.1084f, + -0.822266f, -0.114258f, -0.192383f, -0.608398f, -0.771484f, + 1.11133f, -1.25488f, 1.01953f, -0.0839844f, -0.620117f, + -0.794922f, 0.660156f, -0.876953f, 0.0957031f, -0.242188f, + -0.711914f, -0.55957f, 0.736328f, -0.649414f, -0.0263672f, + -0.258789f, -0.498047f, -0.973633f, 0.957031f, -0.660156f, + 0.186523f, -0.262695f, -0.595703f, -0.787109f, 0.893555f, + -0.429688f, -0.0234375f, -0.254883f, -0.449219f, -0.783203f, + 0.90918f, 0.106445f, -0.161133f, -0.287109f, -0.0800781f, + -0.729492f, 0.933594f, -0.126953f, -0.0742188f, -0.550781f, + -0.271484f, -0.989258f, 1.00098f, -0.879883f, 0.0234375f, + -0.543945f, -0.50293f, -1.18945f, 1.24023f, -1.33398f, + 0.325195f, -0.262695f, -0.307617f, -0.912109f, 1.39062f, + -1.06055f, 0.0107422f, -0.00292969f, -0.573242f, -0.4375f, + 1.15625f, -0.651367f, -0.310547f, 0.188477f, -0.730469f, + -0.121094f, 0.611328f, -0.779297f, 0.335938f, 0.731445f, + -0.475586f, -0.00390625f, 0.100586f, -0.693359f, 0.254883f, + 0.813477f, -0.345703f, 0.420898f, -0.400391f, -0.539062f, + 0.365234f, 0.720703f, 0.0214844f, 0.673828f, -0.370117f, + 0.0585938f, 0.499023f, 0.523438f, 0.198242f, 0.759766f, + -0.544922f, 0.543945f, 0.226562f, 0.473633f, 0.34082f, + 0.595703f, -0.682617f, 0.292969f, -0.217773f, 0.0742188f, + 0.553711f, 0.762695f, -0.504883f, 0.292969f, 0.0751953f, + 0.0126953f, 0.427734f, 0.769531f, -0.265625f, 0.552734f, + -0.0175781f, -0.30957f, 0.253906f, 0.322266f, 0.117188f, + 0.263672f, -0.706055f, -0.991211f, 0.266602f, 0.501953f, + 0.00585938f, 0.0341797f, -1.24805f, -1.21777f, 0.488281f, + 0.461914f, 0.0986328f, 0.362305f, -1.1709f, -1.17188f, + 0.50293f, 0.458984f, 0.108398f, 0.460938f, -1.52148f, + -1.27051f, 0.379883f, 0.90625f, 0.0400391f, 0.524414f, + -1.77832f, -0.951172f, 0.397461f, 0.589844f, 0.520508f, + 0.439453f, -1.99902f, -0.643555f, 0.313477f, 0.766602f, + 0.450195f, 0.286133f, -1.29883f, -0.375f, 0.225586f, + 0.697266f, 0.299805f, 0.108398f, -0.976562f, 0.09375f, + 0.0361328f, 0.851562f, -0.210938f, 0.0615234f, -0.0898438f, + 0.59082f, 0.313477f, 0.756836f, -0.731445f, 0.296875f, + -0.0927734f, 0.552734f, 0.223633f, 0.558594f, -0.806641f, + 0.00195312f, 0.03125f, 0.728516f, 0.276367f, 0.744141f, + -0.994141f, 0.197266f, -0.425781f, 0.316406f, 0.046875f, + 0.601562f, -0.633789f, -0.0576172f, -0.320312f, 0.786133f, + 0.0986328f, 1.0f, -1.19922f, 0.34668f, -0.546875f, + 0.481445f, 0.00390625f, 0.876953f, -1.04297f, -0.0507812f, + -0.775391f, 0.333984f, -0.0175781f, 1.02539f, -1.07129f, + -0.12207f, -0.212891f, 0.28125f, 0.00488281f, 0.998047f, + -0.97168f, 0.178711f, -0.444336f, 0.178711f, 0.0136719f, + 0.896484f, -0.9375f, 0.0117188f, -0.291992f, 0.132812f, + 0.0234375f, 0.975586f, -0.943359f, -0.0078125f, 0.0546875f, + 0.244141f, -0.0771484f, 1.05469f, -1.02148f, 0.313477f, + -0.349609f, 0.148438f, 0.0839844f, 0.619141f, -0.75f, + -0.589844f, -0.0488281f, 0.0263672f, -0.176758f, 0.697266f, + -0.691406f, -0.625977f, -0.417969f, 0.408203f, 0.265625f, + 1.01953f, -1.09863f, 0.106445f, 0.0117188f, 0.157227f, + 0.424805f, 1.07422f, -0.816406f, 0.498047f, 0.0996094f, + 0.00585938f, 0.53418f, 0.771484f, -0.610352f, 0.744141f, + 0.0195312f, 0.0478516f, 0.552734f, 0.734375f, -0.72168f, + 0.518555f, -0.144531f, -0.0361328f, 0.513672f, 0.822266f, + -0.736328f, 0.65918f, -0.179688f, -0.104492f, 0.425781f, + 1.00098f, -0.885742f, 0.739258f, -0.681641f, -0.443359f, + 0.375977f, 0.884766f, -0.724609f, 0.110352f, -0.289062f, + -0.414062f, 0.494141f, 0.53125f, -0.422852f, 0.216797f, + -0.786133f, -0.569336f, 0.749023f, 0.75293f, -0.529297f, + 0.730469f, -0.911133f, -0.68457f, 0.611328f, 0.959961f, + -0.623047f, 1.06543f, -0.499023f, -0.392578f, 0.761719f, + 0.43457f, -0.357422f, 0.631836f, -0.746094f, -0.370117f, + 0.777344f, 0.379883f, -0.225586f, 0.677734f, -0.478516f, + -0.358398f, 0.788086f, 0.569336f, -0.34082f, 0.939453f, + -0.238281f, -0.230469f, 0.861328f, 0.448242f, -0.219727f, + 0.966797f, -0.310547f, -0.242188f, 0.863281f, 0.369141f, + -0.0859375f, 0.87207f, -0.400391f, -0.385742f, 0.841797f, + 0.401367f, -0.0634766f, 0.912109f, -0.458008f, 0.0107422f, + 0.753906f, 0.758789f, -0.675781f, 0.765625f, -0.342773f, + -0.123047f, 0.855469f, 0.599609f, -0.490234f, 0.963867f, + -0.118164f, -0.0117188f, 0.889648f, 0.637695f, -0.607422f, + 0.803711f, -0.597656f, -0.242188f, 0.855469f, 0.550781f, + -0.607422f, 0.576172f, -0.759766f, -0.220703f, 0.832031f, + 0.477539f, -0.491211f, 0.470703f, -0.575195f, -0.0869141f, + 1.01074f, 0.371094f, -0.25293f, 0.678711f, -0.316406f, + -0.197266f, 1.04785f, 0.386719f, -0.046875f, 0.967773f, + -0.761719f, -0.282227f, 0.956055f, 0.270508f, 0.230469f, + 1.39746f, -0.864258f, -0.417969f, 0.761719f, 0.457031f, + 0.0263672f, 1.38379f, -0.714844f, -0.288086f, 0.535156f, + 0.689453f, -0.507812f, 0.68457f, -0.433594f, -0.0908203f, + 0.210938f, 0.825195f, -0.649414f, 0.326172f, -0.793945f, + 0.0527344f, 0.0546875f, 0.911133f, -0.616211f, -0.0214844f, + -0.00195312f, -0.229492f, -0.0253906f, 0.775391f, -0.611328f, + -0.360352f, 0.0371094f, 0.161133f, 0.0253906f, 0.625f, + -0.624023f, -0.344727f, -0.146484f, 0.371094f, 0.255859f, + 1.41797f, -1.27832f, 0.614258f, 0.764648f, 0.869141f, + 0.426758f, 0.758789f, -1.04395f, 0.401367f, 0.263672f, + 0.563477f, 0.450195f, 0.774414f, -0.908203f, 0.384766f, + -0.262695f, 0.664062f, 0.509766f, 0.798828f, -0.757812f, + 0.770508f, 0.491211f, 0.62207f, 0.487305f, 0.496094f, + -0.530273f, 0.375977f, 1.18652f, 0.736328f, 0.386719f, + 0.470703f, -0.647461f, 0.379883f, 0.47168f, 0.834961f, + 0.289062f, 0.475586f, -0.654297f, 0.448242f, 0.395508f, + 0.930664f, 0.0830078f, 0.157227f, -0.304688f, 0.0634766f, + 1.30078f, 0.905273f, -0.102539f, 0.0576172f, -0.303711f, + -0.334961f, 0.885742f, 0.709961f, -0.143555f, 0.0390625f, + -0.18457f, -0.498047f, 1.1084f, 0.744141f, 0.0283203f, + 0.383789f, -0.371094f, -0.126953f, 1.17285f, 0.506836f, + 0.109375f, 0.680664f, -0.244141f, -0.0830078f, 0.577148f, + 0.12793f, 0.25f, 0.972656f, -0.328125f, 0.34082f, + -0.234375f, -0.327148f, 0.470703f, 0.987305f, -0.535156f, + 0.730469f, -0.957031f, -0.509766f, 0.602539f, 0.938477f, + -0.640625f, 0.836914f, -1.13672f, -0.56543f, 0.450195f, + 0.737305f, -0.449219f, 0.649414f, -1.08105f, -0.364258f, + 0.338867f, 0.667969f, -0.533203f, 0.654297f, -1.0918f, + -0.505859f, 0.422852f, 0.745117f, -0.443359f, 0.319336f, + -0.753906f, -0.563477f, 0.374023f, 0.640625f, -0.435547f, + 0.220703f, -0.868164f, -0.701172f, 0.317383f, 0.702148f, + -0.527344f, 0.138672f, -0.848633f, -0.431641f, 0.220703f, + 0.329102f, -0.25293f, -0.232422f, -0.875977f, -0.442383f, + 0.550781f, 0.783203f, -0.441406f, 0.160156f, -0.107422f, + 0.0683594f, 0.317383f, 1.12012f, -1.02344f, 0.322266f, + -0.469727f, -0.151367f, 0.43457f, 0.65625f, -0.745117f, + 0.216797f, -1.03223f, -0.200195f, 0.240234f, 1.11035f, + -0.90332f, 0.239258f, 0.0429688f, -0.228516f, 0.00390625f, + 0.836914f, -0.770508f, -0.280273f, -0.18457f, 0.0117188f, + 0.214844f, 0.767578f, -0.774414f, -0.0703125f, -0.954102f, + -0.508789f, -0.046875f, 1.00391f, -0.930664f, 0.0292969f, + 0.407227f, -0.519531f, 0.0361328f, 0.753906f, -0.777344f, + -0.0214844f, 0.741211f, -0.27832f, -0.0332031f, 1.15625f, + -0.862305f, -0.115234f, 0.821289f, -0.598633f, 0.00488281f, + 0.929688f, -1.01172f, -0.0996094f, 0.351562f, -0.524414f, + 0.118164f, 1.1709f, -0.938477f, 0.00878906f, 0.948242f, + -0.475586f, 0.443359f, 0.893555f, -0.597656f, 0.0107422f, + 0.558594f, -0.87207f, 0.0810547f, 0.487305f, -0.808594f, + 0.212891f, 0.0878906f, -0.612305f, 0.263672f, 0.400391f, + -0.709961f, 0.380859f, -0.0839844f, -0.566406f, 0.466797f, + 0.445312f, -0.769531f, 0.636719f, -0.273438f, -0.648438f, + 0.34375f, 0.56543f, -0.829102f, 0.417969f, -0.272461f, + -0.746094f, 0.202148f, 0.421875f, -0.445312f, 0.229492f, + 0.178711f, -0.408203f, 0.477539f, 0.693359f, -0.675781f, + 0.145508f, 0.37207f, -0.576172f, 0.0449219f, 0.845703f, + -0.920898f, -0.0185547f, 0.487305f, -0.460938f, 0.0253906f, + 1.04785f, -0.87207f, 0.176758f, 0.356445f, -0.217773f, + 0.0332031f, 0.945312f, -0.556641f, -0.110352f, 0.725586f, + 0.0810547f, -0.0361328f, 1.11426f, -0.396484f, 0.00488281f, + 0.743164f, 0.27832f, 0.0175781f, 0.839844f, -0.0371094f, + -0.00878906f, 0.964844f, 0.547852f, 0.0224609f, 0.518555f, + 0.386719f, -0.0585938f, 1.11816f, 0.712891f, 0.19043f, + 0.523438f, 0.429688f, -0.179688f, 1.18164f, 0.40332f, + 0.241211f, 1.19043f, -0.0234375f, 0.119141f, 0.90918f, + -0.078125f, 0.250977f, 0.973633f, -0.277344f, 0.227539f, + 0.908203f, -0.232422f, 0.269531f, 0.807617f, -0.59668f, + 0.253906f, 0.398438f, -0.506836f, 0.255859f, 0.694336f, + -0.742188f, 0.345703f, 0.412109f, -0.576172f, 0.189453f, + 0.708984f, -0.808594f, 0.230469f, 0.242188f, -0.550781f, + 0.0693359f, 0.695312f, -0.856445f, -0.0253906f, 0.177734f, + -0.6875f, -0.00976562f, 0.731445f, -0.991211f, -0.03125f, + 0.0175781f, -0.805664f, -0.192383f, 0.827148f, -0.947266f, + 0.0820312f, 0.254883f, -0.504883f, -0.259766f, 0.87207f, + -0.693359f, -0.345703f, 0.639648f, -0.162109f, -0.443359f, + 1.05176f, -0.595703f, -0.496094f, 0.485352f, -0.0380859f, + -0.490234f, 0.763672f, -0.382812f, -0.634766f, 0.369141f, + 0.136719f, -0.650391f, 0.536133f, -0.126953f, -0.901367f, + 0.275391f, 0.155273f, -0.75293f, 0.476562f, -0.183594f, + -1.00488f, 0.206055f, -0.0908203f, -1.06836f, 0.3125f, + -0.183594f, -1.30762f, 0.37793f, -0.185547f, -0.885742f, + 0.496094f, -0.250977f, -1.14941f, 0.0517578f, -0.242188f, + -0.753906f, 0.395508f, -0.133789f, -1.10156f, 0.183594f, + -0.398438f, -0.767578f, 0.951172f, -0.359375f, -0.866211f, + 0.373047f, -0.0224609f, -0.0537109f, 0.921875f, -0.263672f, + -0.251953f, 0.455078f, 0.230469f, 0.485352f, 0.84082f, + 0.0351562f, 0.0810547f, 0.554688f, 0.186523f, 0.774414f, + 0.720703f, 0.381836f, 0.71875f, 0.495117f, 0.530273f, + 0.771484f, 0.90332f, 0.34668f, 0.897461f, 0.456055f, + 0.575195f, 0.560547f, 0.133789f, 0.62793f, 0.795898f, + 0.400391f, 0.594727f, 0.577148f, -0.142578f, 0.691406f, + 0.770508f, 0.12793f, 0.679688f, 0.751953f, -0.201172f, + 0.728516f, 0.805664f, -0.0175781f, 0.46875f, 0.655273f, + -0.608398f, 0.750977f, 0.540039f, -0.0166016f, 0.30957f, + 0.755859f, -0.563477f, 0.609375f, 0.763672f, -0.310547f, + 0.0791016f, 0.668945f, -0.575195f, 0.398438f, 0.767578f, + -0.47168f, -0.12793f, 0.631836f, -0.768555f, 0.293945f, + 0.760742f, -0.743164f, -0.311523f, 0.509766f, -0.755859f, + 0.15918f, 0.614258f, -0.832031f, -0.575195f, 0.448242f, + -0.771484f, -0.0605469f, 0.341797f, -0.652344f, -0.8125f, + 0.262695f, -0.205078f, -0.541992f, 0.337891f, -0.8125f, + -1.20996f, 0.179688f, -0.311523f, -0.682617f, 0.0556641f, + -0.944336f, -1.29102f, 0.09375f, 0.503906f, -0.87793f, + -0.0742188f, -0.805664f, -1.53613f, -0.107422f, 0.50293f, + -0.807617f, -0.423828f, 0.0888672f, -0.847656f, -0.342773f, + 0.719727f, -0.87793f, -0.336914f, 0.115234f, -0.500977f, + -0.487305f, 0.395508f, -0.398438f, -0.624023f, 0.3125f, + -0.0693359f, -0.605469f, 0.429688f, -0.283203f, -0.813477f, + 0.246094f, 0.0898438f, -0.764648f, 0.356445f, -0.106445f, + -1.05371f, 0.595703f, 0.251953f, -0.729492f, 0.336914f, + -0.0595703f, -1.06445f, 0.824219f, 0.320312f, -0.50293f, + 0.459961f, -0.161133f, -0.820312f, 0.516602f, 0.410156f, + -0.401367f, 0.407227f, -0.106445f, -0.740234f, 0.546875f, + 0.663086f, -0.170898f, 0.574219f, -0.419922f, -0.271484f, + -0.0273438f, 0.239258f, -0.0361328f, 0.80957f, -0.576172f, + 0.0664062f, 0.0332031f, 0.181641f, 0.245117f, 1.06641f, + -0.826172f, 0.30957f, -0.241211f, 0.03125f, 0.422852f, + 1.14648f, -0.916992f, 0.672852f, -0.242188f, 0.0234375f, + 0.425781f, 1.16895f, -1.08887f, 0.748047f, -0.384766f, + 0.102539f, 0.457031f, 0.992188f, -0.896484f, 0.65625f, + -0.144531f, 0.0332031f, 0.295898f, 0.8125f, -0.706055f, + 0.166016f, -0.237305f, 0.0996094f, 0.130859f, 0.723633f, + -0.769531f, -0.125f, -0.339844f, -0.277344f, -0.00390625f, + 1.2959f, -0.999023f, 0.0185547f, 0.0527344f, 0.270508f, + 0.104492f, 1.05469f, -1.0918f, 0.205078f, 0.00390625f, + 0.141602f, 0.000976562f, 1.15039f, -1.14844f, 0.0664062f, + -0.0566406f, 0.0732422f, 0.0302734f, 1.08398f, -1.04004f, + 0.124023f, -0.114258f, 0.19043f, 0.0263672f, 0.985352f, + -1.00293f, 0.0634766f, -0.0585938f, 0.257812f, -0.0527344f, + 0.96875f, -0.990234f, -0.0361328f, -0.179688f, 0.266602f, + -0.219727f, 0.882812f, -0.879883f, -0.289062f, -0.00292969f, + 0.351562f, -0.313477f, 0.826172f, -0.84668f, -0.322266f, + 0.337891f, 0.478516f, -0.426758f, 0.594727f, -0.621094f, + -0.435547f, 0.676758f, 0.47168f, -0.432617f, 0.333008f, + -0.338867f, -0.767578f, 0.419922f, 0.576172f, -0.673828f, + 0.321289f, -0.53125f, -0.96582f, 0.290039f, 0.426758f, + -0.526367f, 0.230469f, -0.508789f, -1.05859f, 0.195312f, + 0.493164f, -0.479492f, 0.78418f, -0.992188f, -0.453125f, + -0.185547f, 0.375977f, -0.291992f, 0.77832f, -0.884766f, + -0.361328f, 0.438477f, -0.118164f, -0.222656f, 0.923828f, + -0.796875f, 0.0234375f, -0.375f, 0.0332031f, -0.216797f, + 0.908203f, -0.984375f, -0.295898f, -0.384766f, 0.0234375f, + -0.305664f, 1.12695f, -1.04004f, -0.344727f, -0.136719f, + 0.119141f, -0.385742f, 1.06738f, -1.01855f, -0.245117f, + -0.106445f, -0.114258f, -0.365234f, 0.962891f, -0.923828f, + -0.430664f, -0.637695f, -0.347656f, -0.436523f, 0.702148f, + -0.547852f, -0.618164f, -0.447266f, -0.241211f, -0.462891f, + 0.729492f, -0.609375f, -0.578125f, -0.486328f, -0.0556641f, + -0.536133f, 0.50293f, -0.480469f, -0.526367f, -0.210938f, + -0.0585938f, -0.637695f, 0.723633f, -0.319336f, -0.348633f, + -0.00292969f, -0.305664f, -0.629883f, 0.431641f, 0.266602f, + -0.612305f, -0.260742f, 0.0166016f, -0.65332f, -0.272461f, + 0.800781f, -1.09863f, -0.166992f, -0.0859375f, -0.520508f, + -0.473633f, 0.586914f, -0.696289f, -0.682617f, -0.149414f, + 0.198242f, -0.805664f, 1.1377f, 0.444336f, -0.458984f, + -0.577148f, 0.522461f, -0.683594f, 1.25586f, 0.827148f, + -0.249023f, -0.851562f, 0.84668f, -0.448242f, 1.26953f, + 0.855469f, -0.155273f, -0.765625f, 1.0f, -0.337891f, + 0.973633f, 0.660156f, -0.0859375f, -0.476562f, 1.11035f, + -0.00976562f, 0.547852f, 0.958984f, -0.34082f, -0.504883f, + 0.853516f, 0.0664062f, 0.378906f, 0.758789f, -0.749023f, + -0.509766f, 0.739258f, 0.499023f, -0.144531f, 0.84668f, + -0.931641f, -0.329102f, 0.740234f, 0.791992f, -0.168945f, + 0.594727f, -0.435547f, -0.268555f, 0.336914f, 0.817383f, + -0.430664f, -0.0253906f, -0.735352f, -0.0683594f, 0.152344f, + 0.725586f, -0.68457f, -0.294922f, -1.25391f, -0.125f, + 0.0917969f, 0.907227f, -0.633789f, -0.28125f, -0.222656f, + 0.0f, 0.188477f, 1.06445f, -0.929688f, 0.144531f, + -0.139648f, -0.00390625f, -0.21582f, 1.21387f, -0.952148f, + -0.0253906f, -0.389648f, 0.148438f, -0.283203f, 1.14844f, + -0.890625f, -0.204102f, -0.222656f, -0.0332031f, -0.451172f, + 0.625f, -0.486328f, -0.716797f, -0.103516f, 0.265625f, + -0.667969f, 0.231445f, -0.385742f, -0.977539f, 0.111328f, + 0.222656f, -0.766602f, 0.300781f, -0.390625f, -1.07129f, + 0.230469f, 0.318359f, -0.787109f, 0.427734f, -0.512695f, + -0.886719f, 0.240234f, 0.260742f, -0.647461f, 0.566406f, + -0.686523f, -0.723633f, -0.198242f, 0.0722656f, -0.3125f, + 0.771484f, -0.725586f, -0.478516f, -0.176758f, -0.113281f, + -0.262695f, 0.78125f, -0.644531f, -0.210938f, -0.0126953f, + -0.317383f, 0.0673828f, 0.944336f, -0.764648f, 0.1875f, + -0.636719f, -0.401367f, 0.118164f, 0.982422f, -0.826172f, + 0.105469f, -1.0625f, -0.298828f, 0.0537109f, 0.949219f, + -0.788086f, 0.176758f, -0.611328f, -0.0322266f, 0.0439453f, + 0.885742f, -0.730469f, 0.301758f, -0.463867f, -0.144531f, + -0.180664f, 1.08398f, -0.97168f, -0.470703f, 0.128906f, + 0.0146484f, -0.112305f, 0.889648f, -0.946289f, -0.165039f, + -1.34277f, -0.258789f, -0.211914f, 0.962891f, -0.844727f, + -0.588867f, 0.144531f, -0.228516f, -0.207031f, 0.974609f, + -0.848633f, -0.0273438f, -0.570312f, -0.228516f, 0.00195312f, + 1.03125f, -0.977539f, -0.0605469f, -0.733398f, -0.0908203f, + 0.0996094f, 0.856445f, -0.854492f, -0.000976562f, -0.458008f, + -0.135742f, 0.222656f, 1.34082f, -1.13574f, 0.639648f, + 0.015625f, -0.234375f, 0.136719f, 0.835938f, -0.822266f, + -0.114258f, -0.673828f, -0.186523f, 0.169922f, 0.925781f, + -0.839844f, 0.175781f, -0.394531f, 0.224609f, -0.0458984f, + 0.94043f, -0.964844f, -0.0556641f, -0.15332f, 0.163086f, + -0.0175781f, 0.944336f, -0.951172f, -0.0478516f, -0.302734f, + 0.117188f, -0.00683594f, 0.973633f, -0.970703f, -0.0810547f, + -0.301758f, 0.09375f, -0.000976562f, 1.01953f, -0.978516f, + 0.0292969f, -0.293945f, 0.0683594f, -0.00683594f, 1.0127f, + -0.966797f, -0.0175781f, -0.314453f, 0.181641f, 0.0126953f, + 0.982422f, -0.990234f, 0.03125f, -0.194336f, 0.155273f, + -0.00292969f, 0.962891f, -0.932617f, -0.00390625f, -0.0976562f, + 0.144531f, -0.0205078f, 0.913086f, -0.914062f, -0.0908203f, + -0.296875f, 0.166992f, -0.015625f, 0.930664f, -0.950195f, + -0.0888672f, -0.28418f, 0.196289f, -0.0107422f, 0.953125f, + -0.960938f, -0.0273438f, -0.195312f, 0.125f, 0.0126953f, + 0.986328f, -0.951172f, 0.0634766f, -0.231445f, 0.162109f, + -0.0136719f, 0.981445f, -0.974609f, -0.0449219f, -0.0761719f, + 0.186523f, -0.015625f, 0.950195f, -0.962891f, -0.0576172f, + -0.162109f, 0.154297f, -0.0292969f, 0.970703f, -0.973633f, + -0.0136719f, -0.394531f, 0.102539f, -0.00878906f, 0.970703f, + -0.915039f, 0.0546875f, -0.313477f, 0.110352f, -0.0234375f, + 0.947266f, -0.922852f, -0.139648f, -0.181641f, 0.12207f, + 0.0625f, 0.780273f, -0.899414f, -0.84375f, -0.0888672f, + -0.318359f, 1.00781f, 0.888672f, 0.27832f, 0.0195312f, + -1.08594f, 0.137695f, 0.56543f, 1.12891f, -0.235352f, + 1.65039f, -0.0820312f, 0.100586f, 0.987305f, 0.261719f, + -0.0615234f, 1.32227f, 0.669922f, 0.0f, 1.04102f, + 0.231445f, -0.174805f, 1.11426f, -0.261719f, -0.0527344f, + 0.958008f, 0.332031f, -0.28418f, 1.26953f, -0.612305f, + 0.208984f, 0.964844f, 1.15625f, -0.486328f, 2.0f, + -0.760742f, 0.0458984f, 1.44629f, 1.21289f, 0.924805f, + 1.1875f, -0.259766f, 0.114258f, 0.210938f, 0.486328f, + -0.422852f, -0.984375f, 1.08789f, 0.453125f, -0.229492f, + 0.457031f, -0.682617f, -0.500977f, 0.210938f, 0.391602f, + -0.303711f, 0.725586f, -0.80957f, -0.391602f, 0.0976562f, + 0.958984f, 0.0185547f, 1.69922f, -1.36035f, 1.98242f, + -0.392578f, -0.461914f, -0.37793f, -0.0712891f, 0.928711f, + -1.60254f, 0.133789f, -0.0419922f, -1.12109f, -0.201172f, + 0.0732422f, -1.99902f, 0.629883f, -0.174805f, -0.894531f, + 0.0742188f, -0.147461f, -1.23633f, -0.259766f, 0.0410156f, + -1.00879f, -0.0166016f, -0.0205078f, -1.99902f, 0.267578f, + -0.0664062f, -0.164062f, 0.511719f, 0.825195f, -1.21191f, + -0.515625f, 0.46875f, 0.0898438f, 1.09766f, -0.144531f, + 1.59375f, 0.166016f, 0.428711f, 0.294922f, 0.8125f, + -0.770508f, 0.535156f, 0.280273f, 0.231445f, 0.504883f, + 0.864258f, -0.884766f, 0.524414f, -0.183594f, 0.0820312f, + 0.713867f, 0.405273f, -0.520508f, -0.326172f, 0.0126953f, + -0.310547f, 1.38086f, 0.831055f, 0.380859f, 1.3125f, + -1.60645f, 0.151367f, 1.01953f, 0.580078f, -0.0283203f, + 2.0f, 1.03516f, -0.0634766f, 1.03418f, 0.332031f, + -0.0859375f, 1.32129f, -0.234375f, 0.0917969f, 1.49219f, + 0.30957f, -0.118164f, 1.76953f, -0.717773f, 0.174805f, + 1.59863f, 0.0947266f, 1.1875f, 0.429688f, 0.442383f, + 0.00976562f, 0.435547f, 0.345703f, -0.114258f, 0.238281f, + -0.689453f, 0.30957f, 0.0732422f, 0.606445f, -0.650391f, + -0.0947266f, -0.03125f, 0.183594f, -0.144531f, 0.746094f, + -0.793945f, -0.574219f, -0.0742188f, 0.196289f, -0.199219f, + 1.13867f, -1.11816f, -0.227539f, -0.462891f, 0.0517578f, + -0.0341797f, 1.18945f, -1.1084f, -0.0283203f, -0.342773f, + 0.174805f, -0.0078125f, 1.05176f, -1.03906f, 0.0253906f, + -0.375977f, -0.169922f, 0.00292969f, 0.837891f, -0.716797f, + -0.0205078f, -0.373047f, 0.293945f, 0.0175781f, 0.833984f, + -0.916016f, -0.0996094f, -0.149414f, 0.200195f, -0.00195312f, + 0.865234f, -0.916016f, -0.0117188f, -0.390625f, 0.290039f, + 0.0234375f, 0.985352f, -0.987305f, 0.0439453f, -0.214844f, + 0.0917969f, 0.0615234f, 1.02832f, -1.00684f, 0.152344f, + -0.452148f, 0.0615234f, -0.00585938f, 1.02148f, -0.976562f, + -0.0927734f, -0.286133f, 0.189453f, -0.0644531f, 1.02539f, + -1.02246f, 0.0166016f, -0.243164f, 0.109375f, -0.09375f, + 0.981445f, -0.931641f, 0.0458984f, -0.460938f, 0.0537109f, + -0.0429688f, 1.05859f, -0.850586f, 0.0771484f, -0.0507812f, + 0.108398f, -0.177734f, 0.779297f, -0.74707f, -0.378906f, + -0.413086f, -0.205078f, -0.0488281f, 0.946289f, -0.760742f, + -0.180664f, -0.228516f, -0.208008f, -0.0615234f, 1.05371f, + -0.953125f, -0.34668f, -1.16797f, -0.0322266f, -0.276367f, + 1.06641f, -0.863281f, -0.0244141f, -0.290039f, -0.0429688f, + 0.0439453f, 1.28223f, -1.06348f, 0.181641f, -0.514648f, + -0.0214844f, 0.0f, 0.861328f, -0.738281f, -0.0449219f, + 0.0722656f, 0.125f, 0.193359f, 1.15039f, -1.0957f, + 0.225586f, -0.137695f, 0.12207f, -0.0400391f, 0.732422f, + -0.818359f, -0.40918f, -0.672852f, -0.425781f, 0.839844f, + 0.856445f, 0.198242f, -0.363281f, 0.206055f, -0.214844f, + 1.20215f, 0.943359f, 0.0195312f, 2.0f, 0.874023f, + 0.0839844f, 0.827148f, 0.587891f, -0.384766f, 1.57715f, + 0.108398f, -0.116211f, 0.952148f, 0.246094f, -0.336914f, + 0.463867f, -0.740234f, 0.0185547f, 0.950195f, 0.55957f, + -0.442383f, 1.09668f, 0.0585938f, 0.132812f, 1.37695f, + 2.0f, -0.59375f, 2.0f, -0.676758f, -0.199219f, + -0.0205078f, 0.268555f, -0.5f, -1.94629f, 1.2832f, + 0.0078125f, -0.201172f, 0.674805f, -0.708984f, -0.490234f, + -0.515625f, 0.0439453f, -0.0830078f, 1.14355f, -1.01953f, + -0.0224609f, -0.282227f, 0.0214844f, -0.078125f, 1.09668f, + -0.961914f, 0.0253906f, -0.56543f, 0.30957f, 0.964844f, + 1.56836f, -0.272461f, 1.91309f, -0.53418f, -0.695312f, + -0.878906f, -0.0146484f, 0.277344f, -1.6416f, 0.0244141f, + 0.0898438f, -0.785156f, 0.229492f, -0.259766f, -1.06055f, + -0.241211f, 0.0224609f, -0.769531f, 0.748047f, -0.680664f, + -0.629883f, -0.549805f, -0.195312f, -0.796875f, -0.399414f, + 0.0859375f, -1.99902f, 0.24707f, 0.208984f, 0.563477f, + 1.91797f, 0.0585938f, 2.0f, -0.990234f, 0.327148f, + -0.0917969f, 1.16797f, -0.94043f, 0.623047f, -1.1748f, + -0.0205078f, -0.0449219f, 0.883789f, -0.905273f, -0.370117f, + -0.601562f, 0.0332031f, -0.0527344f, 0.928711f, -0.833984f, + -0.180664f, -0.267578f, 0.0351562f, -0.0175781f, 0.998047f, + -0.922852f, -0.000976562f, -0.371094f, 0.0341797f, -0.0166016f, + 0.977539f, -0.900391f, -0.00292969f, -0.37207f, 0.0449219f, + -0.0439453f, 0.989258f, -0.904297f, -0.0576172f, -0.37207f, + 0.270508f, -0.368164f, 0.0576172f, -0.607422f, -1.95508f, + -0.182617f, -0.390625f, 1.62598f, 1.52734f, 1.2793f, + 2.0f, -1.99902f, 0.226562f, 1.01465f, 0.669922f, + -0.373047f, 1.71484f, 1.99707f, -0.0654297f, 1.00391f, + 0.330078f, -0.432617f, 0.704102f, -0.96875f, 0.0800781f, + 0.964844f, 0.702148f, -0.5625f, 1.39746f, -0.203125f, + 0.255859f, 1.74512f, 1.52539f, 0.417969f, 2.0f, + -0.0976562f, -0.482422f, 0.09375f, 0.151367f, -0.328125f, + -1.88867f, -0.0595703f, 0.117188f, 0.0751953f, 0.870117f, + -0.870117f, 0.046875f, -0.280273f, 0.125f, 0.124023f, + 1.0791f, -0.964844f, 0.338867f, -0.0791016f, 0.0751953f, + 0.12207f, 0.920898f, -0.888672f, 0.0273438f, -0.250977f, + 0.00488281f, 0.165039f, 1.01074f, -0.944336f, 0.137695f, + -0.387695f, -0.142578f, 0.238281f, 1.77246f, -1.42285f, + 0.90625f, -0.856445f, 0.0556641f, -0.219727f, -0.785156f, + 1.47266f, -1.99902f, 1.27246f, -0.132812f, -0.746094f, + 0.172852f, -0.0830078f, -1.3584f, 0.638672f, 0.0175781f, + -0.786133f, 0.754883f, -0.729492f, -0.808594f, -0.291992f, + 0.170898f, -0.746094f, 0.623047f, -0.667969f, -0.743164f, + -0.241211f, 0.0693359f, -0.725586f, 0.495117f, -0.545898f, + -0.969727f, -0.131836f, 0.0234375f, -0.52832f, 0.280273f, + -0.327148f, -1.0498f, -0.210938f, -0.253906f, 0.234375f, + 0.661133f, -0.0332031f, -0.708008f, -0.458984f, 0.31543f, + 0.480469f, 1.59082f, -1.22266f, 1.41602f, -0.270508f, + 0.263672f, 0.318359f, 1.21289f, -1.12207f, 0.853516f, + -0.272461f, 0.158203f, 1.84766f, 2.0f, 0.341797f, + 2.0f, -0.788086f, -0.264648f, -0.326172f, -1.25977f, + 0.842773f, -1.99902f, -0.947266f, 0.249023f, -0.642578f, + 0.745117f, -0.744141f, -0.404297f, -0.266602f, 0.0898438f, + -0.568359f, 0.501953f, -0.494141f, -0.858398f, 0.0722656f, + -0.543945f, 1.16895f, 1.12012f, 1.47461f, -1.12988f, + -0.27832f, 0.53125f, 0.875f, 0.845703f, -0.318359f, + 1.68555f, 1.29199f, -0.00195312f, 0.861328f, 0.601562f, + -0.519531f, 1.16211f, -1.05957f, 0.0507812f, 0.904297f, + 0.625977f, -0.525391f, 1.16797f, -0.163086f, 0.125977f, + 1.99902f, 2.0f, 2.0f, 2.0f, -0.00195312f, + -1.11719f, -0.3125f, -0.320312f, 0.585938f, -1.99902f, + 0.647461f, 0.198242f, -0.538086f, 0.993164f, -0.897461f, + -0.227539f, -0.354492f, 0.0976562f, -0.416016f, 0.623047f, + -0.682617f, -0.832031f, -0.223633f, -0.160156f, 0.0751953f, + -0.791992f, 1.13379f, -1.99902f, -0.755859f, 0.669922f, + 1.02637f, 1.26758f, -0.293945f, 2.0f, 1.93457f, + -0.0126953f, 0.773438f, 0.475586f, -0.59375f, 0.329102f, + -0.588867f, 0.113281f, 0.740234f, 0.749023f, -0.716797f, + 0.941406f, -0.0878906f, 0.71875f, 1.8125f, 2.0f, + -0.289062f, 2.0f, -1.01074f, 0.0117188f, -0.183594f, + -0.969727f, 0.893555f, -1.99902f, 0.333008f, 0.188477f, + -0.643555f, 0.504883f, -0.511719f, -0.804688f, -0.957031f, + 0.0546875f, -0.305664f, -0.0449219f, -0.145508f, -1.875f, + 0.0996094f, -0.155273f, 1.59668f, 1.5293f, 1.46973f, + 2.0f, -1.9834f, 0.375f, 1.20508f, 0.736328f, + -0.399414f, 2.0f, 2.0f, 0.123047f, 0.834961f, + 1.04004f, -0.808594f, 1.31934f, -0.634766f, 0.548828f, + 0.129883f, -1.64746f, 2.0f, -1.99902f, 0.819336f, + 0.0273438f, -0.254883f, 0.722656f, -0.691406f, -0.464844f, + -1.05566f, 0.0634766f, -0.206055f, 1.02148f, -0.90332f, + 0.0595703f, -0.03125f, 0.129883f, -0.177734f, 0.697266f, + -0.713867f, -0.351562f, -0.169922f, -0.119141f, -0.172852f, + 1.01855f, -0.989258f, -0.12793f, -0.670898f, -0.146484f, + -0.261719f, 1.16602f, -1.05664f, -0.302734f, -0.25293f, + -0.0458984f, -0.198242f, 0.90625f, -0.876953f, -0.144531f, + -0.424805f, -0.151367f, -0.147461f, 0.926758f, -0.835938f, + -0.191406f, -0.326172f, -0.128906f, -0.216797f, 0.910156f, + -0.851562f, -0.291992f, -0.549805f, -0.0517578f, -0.0869141f, + 1.07715f, -0.977539f, -0.0361328f, -0.418945f, -0.148438f, + -0.133789f, 0.907227f, -0.836914f, -0.213867f, -0.768555f, + -0.0664062f, 0.182617f, 1.0498f, -0.915039f, 0.400391f, + -0.523438f, 0.015625f, 0.0f, 1.13184f, -1.09961f, + -0.244141f, -0.330078f, -0.115234f, 0.0166016f, 0.944336f, + -0.868164f, -0.430664f, -0.246094f, -0.0185547f, -0.00976562f, + 0.819336f, -0.822266f, -0.380859f, -1.1709f, 0.0605469f, + -0.0498047f, 0.777344f, -0.703125f, 0.0800781f, -0.451172f, + 0.304688f, 0.0517578f, 0.825195f, -0.771484f, 0.145508f, + 0.495117f, -0.0888672f, -0.243164f, 1.48145f, -1.22168f, + 0.0615234f, -0.192383f, -0.0537109f, 0.0195312f, 1.21582f, + -1.06836f, 0.175781f, -0.394531f, 0.237305f, -0.0126953f, + 0.800781f, -0.920898f, -0.12207f, -0.391602f, -0.0917969f, + -0.0791016f, 1.08008f, -1.03613f, -0.0654297f, -0.423828f, + 0.0478516f, -0.0253906f, 0.873047f, -0.884766f, -0.0722656f, + -0.579102f, 0.0136719f, -0.0917969f, 0.954102f, -0.922852f, + -0.172852f, -0.244141f, 0.0f, -0.141602f, 0.929688f, + -0.894531f, -0.179688f, -0.291992f, 0.0283203f, -0.0947266f, + 0.961914f, -0.926758f, -0.135742f, -0.329102f, 0.0576172f, + -0.0351562f, 0.999023f, -0.958984f, -0.0498047f, -0.248047f, + 0.0869141f, -0.078125f, 1.01074f, -0.954102f, 0.00976562f, + -0.217773f, 0.0986328f, -0.0556641f, 0.916992f, -0.914062f, + -0.136719f, -0.219727f, 0.0488281f, -0.139648f, 0.985352f, + -0.952148f, -0.152344f, -0.286133f, 0.0166016f, -0.0917969f, + 1.0459f, -0.972656f, -0.0605469f, -0.228516f, 0.0507812f, + -0.0810547f, 0.956055f, -0.9375f, -0.18457f, -0.275391f, + 0.0703125f, -0.0986328f, 0.948242f, -0.928711f, -0.162109f, + -0.333008f +}; const size_t kAccelerometerLaptopModeTestDataLength = - ARRAY_SIZE(kAccelerometerLaptopModeTestData); + ARRAY_SIZE(kAccelerometerLaptopModeTestData); const float kAccelerometerFullyOpenTestData[] = { - 0.892578f, -0.0810547f, 0.0146484f, 0.929688f, -0.0644531f, - -0.0234375f, 0.996094f, -0.0136719f, 0.0185547f, 1.02344f, - -0.0615234f, -0.0449219f, 0.978516f, 0.125977f, 0.0400391f, - 0.996094f, 0.0332031f, -0.0117188f, 0.963867f, 0.107422f, - 0.0214844f, 0.980469f, 0.0185547f, -0.00683594f, 0.952148f, - 0.0361328f, 0.0253906f, 0.976562f, -0.00390625f, -0.0126953f, - 0.97168f, 0.0205078f, 0.0517578f, 1.01074f, 0.015625f, - -0.0234375f, 0.953125f, -0.000976562f, 0.0390625f, 0.977539f, - -0.0224609f, -0.00976562f, 0.954102f, 0.0244141f, 0.0439453f, - 0.986328f, 0.00292969f, -0.000976562f, 0.967773f, 0.0537109f, - 0.046875f, 0.99707f, 0.0175781f, -0.000976562f, 0.951172f, - 0.0390625f, 0.0341797f, 0.974609f, -0.00878906f, -0.000976562f, - 0.948242f, 0.0185547f, 0.0478516f, 0.976562f, -0.000976562f, - -0.00683594f, 0.958984f, 0.0263672f, 0.078125f, 0.982422f, - -0.0205078f, 0.0283203f, 0.930664f, 0.00878906f, 0.0664062f, - 0.970703f, 0.00390625f, -0.0078125f, 0.945312f, 0.0380859f, - -0.00585938f, 0.972656f, 0.0419922f, -0.0478516f, 1.01953f, - 0.240234f, -0.182617f, 1.00977f, 0.18457f, -0.126953f, - 1.05566f, 0.0751953f, -0.0888672f, 1.09766f, 0.0732422f, - -0.0898438f, 1.21484f, 0.119141f, -0.000976562f, 1.23633f, - 0.194336f, -0.447266f, 1.31445f, 0.213867f, -0.118164f, - 1.30762f, 0.0908203f, -0.260742f, 0.860352f, 0.141602f, - -0.166016f, 0.868164f, 0.0429688f, -0.258789f, 0.727539f, - 0.0419922f, -0.21875f, 0.740234f, 0.0126953f, -0.162109f, - 0.652344f, -0.00292969f, -0.185547f, 0.666992f, 0.0800781f, - -0.272461f, 0.852539f, -0.0478516f, -0.228516f, 0.819336f, - -0.0996094f, -0.180664f, 0.959961f, -0.0537109f, -0.240234f, - 0.935547f, -0.0917969f, -0.269531f, 0.988281f, -0.0507812f, - -0.197266f, 0.981445f, -0.0712891f, -0.323242f, 0.964844f, - -0.0683594f, -0.203125f, 0.941406f, -0.0898438f, -0.236328f, - 0.942383f, -0.0429688f, -0.206055f, 0.921875f, -0.0527344f, - -0.239258f, 0.976562f, -0.0742188f, -0.261719f, 0.958008f, - -0.09375f, -0.311523f, 0.949219f, -0.0839844f, -0.242188f, - 0.949219f, -0.0742188f, -0.323242f, 0.973633f, -0.0263672f, - -0.238281f, 0.958984f, -0.0488281f, -0.293945f, 0.931641f, - -0.0214844f, -0.225586f, 0.931641f, 0.0195312f, -0.225586f, - 0.810547f, -0.0947266f, -0.15332f, 0.947266f, 0.241211f, - -0.100586f, 0.326172f, 0.286133f, -0.12207f, 0.855469f, - 0.677734f, -0.228516f, 0.229492f, 1.08398f, 0.0224609f, - 0.822266f, 0.759766f, -0.0722656f, 0.294922f, 1.42676f, - 0.147461f, 0.239258f, 0.755859f, 0.142578f, -0.120117f, - 1.00977f, -0.0722656f, -0.154297f, 0.832031f, -0.0576172f, - -0.15332f, 1.10156f, -0.0273438f, -0.119141f, 1.05078f, - 0.0166016f, -0.0927734f, 1.09961f, -0.0703125f, -0.0751953f, - 1.04688f, -0.00195312f, -0.078125f, 0.897461f, -0.0625f, - -0.078125f, 0.854492f, -0.0947266f, -0.123047f, 0.811523f, - -0.0488281f, -0.113281f, 0.796875f, 0.0f, -0.0488281f, - 0.961914f, -0.177734f, -0.0898438f, 0.859375f, -0.172852f, - 0.0126953f, 1.1084f, -0.158203f, 0.0292969f, 1.0791f, - -0.152344f, 0.154297f, 1.29492f, -0.126953f, 0.134766f, - 1.23145f, -0.0878906f, -0.200195f, 0.667969f, -0.216797f, - -0.0888672f, 0.935547f, -0.143555f, 0.000976562f, 1.13281f, - -0.0498047f, 0.00195312f, 1.05469f, -0.231445f, 0.0927734f, - 0.956055f, -0.292969f, 0.0625f, 0.927734f, -0.112305f, - 0.0585938f, 0.975586f, -0.163086f, 0.0957031f, 1.03418f, - -0.229492f, 0.000976562f, 0.985352f, -0.09375f, -0.00585938f, - 0.945312f, -0.140625f, -0.0302734f, 0.998047f, -0.208008f, - -0.0507812f, 0.916016f, -0.112305f, 0.123047f, 0.981445f, - -0.205078f, 0.129883f, 1.02832f, -0.211914f, 0.105469f, - 1.01367f, -0.142578f, 0.111328f, 1.00098f, -0.110352f, - 0.0986328f, 0.999023f, -0.15918f, 0.0839844f, 0.922852f, - -0.223633f, 0.261719f, 1.06641f, -0.138672f, 0.240234f, - 0.916016f, -0.296875f, 0.00488281f, 1.04199f, -0.128906f, - 0.0341797f, 1.0791f, -0.265625f, 0.015625f, 0.963867f, - -0.161133f, 0.015625f, 0.958008f, -0.0722656f, -0.125f, - 1.03125f, -0.19043f, -0.0722656f, 1.16602f, -0.126953f, - -0.143555f, 1.12793f, -0.197266f, -0.120117f, 1.26465f, - -0.232422f, -0.226562f, 1.125f, -0.0712891f, -0.0927734f, - 1.26465f, -0.145508f, -0.551758f, 0.90918f, -0.163086f, - -0.228516f, 1.2041f, -0.0371094f, -0.493164f, 0.827148f, - 0.0371094f, -0.162109f, 0.568359f, -0.195312f, -0.641602f, - 0.438477f, -0.212891f, -0.513672f, 0.208008f, -0.0488281f, - -0.776367f, 0.0488281f, -0.115234f, -0.84375f, -0.314453f, - 0.106445f, -0.966797f, -0.0078125f, 0.00976562f, -1.01953f, - -0.220703f, -0.0322266f, -0.994141f, 0.0117188f, -0.248047f, - -0.975586f, 0.121094f, -0.0205078f, -0.947266f, 0.00292969f, - -0.160156f, -0.9375f, 0.0175781f, -0.0986328f, -0.916992f, - -0.0195312f, -0.208008f, -0.9375f, -0.0654297f, -0.134766f, - -0.948242f, -0.0185547f, -0.231445f, -0.977539f, -0.0537109f, - -0.198242f, -1.0166f, 0.0439453f, -0.433594f, -0.994141f, - -0.0595703f, -0.389648f, -1.07129f, 0.0859375f, -0.109375f, - -1.01953f, 0.0966797f, -0.12207f, -1.01074f, 0.125977f, - -0.192383f, -1.0f, 0.0820312f, -0.166016f, -1.04688f, - 0.0751953f, -0.265625f, -1.00879f, 0.139648f, -0.135742f, - -1.00977f, 0.0644531f, -0.235352f, -0.989258f, 0.100586f, - -0.144531f, -0.858398f, 0.0273438f, -0.22168f, -0.878906f, - -0.0634766f, -0.1875f, -0.905273f, -0.0195312f, -0.232422f, - -0.926758f, -0.0732422f, -0.319336f, -1.05078f, -0.00878906f, - -0.5625f, -1.05176f, 0.111328f, -0.456055f, -0.942383f, - -0.0146484f, -0.171875f, -0.946289f, -0.0224609f, -0.174805f, - -0.901367f, -0.0283203f, -0.332031f, -0.948242f, -0.0732422f, - -0.262695f, -0.867188f, 0.0351562f, -0.271484f, -0.913086f, - -0.0878906f, -0.259766f, -1.2793f, -0.226562f, -0.382812f, - -1.2334f, 0.0400391f, -0.260742f, -1.22949f, -0.216797f, - -0.432617f, -1.21191f, -0.131836f, -0.368164f, -1.10938f, - -0.323242f, -0.505859f, -1.01953f, -0.197266f, -0.405273f, - -1.25488f, -0.347656f, -0.448242f, -0.803711f, 0.0595703f, - -0.253906f, -0.489258f, -0.00390625f, 0.101562f, 0.15332f, - -0.423828f, -0.0195312f, 0.527344f, -0.350586f, -0.24707f, - 0.363281f, -1.33789f, -0.214844f, 0.322266f, -0.768555f, - -0.279297f, 0.266602f, -0.918945f, -0.320312f, 0.0634766f, - -0.97168f, -0.102539f, 0.114258f, -0.891602f, -0.158203f, - 0.0283203f, -0.998047f, -0.198242f, 0.0634766f, -0.931641f, - -0.239258f, 0.147461f, -0.963867f, -0.219727f, 0.142578f, - -1.02051f, -0.279297f, 0.105469f, -0.955078f, -0.238281f, - 0.104492f, -1.02637f, -0.291992f, -0.0302734f, -1.02637f, - -0.225586f, 0.000976562f, -0.907227f, -0.12793f, 0.03125f, - -0.979492f, -0.100586f, 0.0625f, -0.921875f, -0.155273f, - 0.146484f, -0.929688f, -0.158203f, 0.155273f, -0.981445f, - -0.171875f, 0.212891f, -0.927734f, -0.166992f, 0.198242f, - -1.05371f, -0.197266f, 0.189453f, -0.954102f, -0.113281f, - 0.189453f, -1.00293f, -0.180664f, 0.111328f, -0.967773f, - -0.109375f, 0.125977f, -0.966797f, -0.146484f, 0.0712891f, - -0.982422f, -0.0908203f, 0.112305f, -0.928711f, -0.149414f, - 0.0146484f, -1.00781f, -0.0996094f, 0.102539f, -0.810547f, - -0.157227f, -0.0117188f, -0.820312f, -0.0371094f, 0.28418f, - -0.446289f, -0.166016f, 0.208008f, -0.03125f, -0.0761719f, - 0.755859f, -0.280273f, -0.316406f, 1.42188f, 0.198242f, - -0.49707f, 1.37207f, -0.556641f, -0.382812f, 1.36523f, - 0.110352f, -0.342773f, 1.25391f, -0.225586f, -0.570312f, - 0.958984f, 0.0722656f, -0.237305f, 0.984375f, 0.0957031f, - -0.416992f, 0.853516f, 0.0400391f, -0.416016f, 0.873047f, - 0.0644531f, -0.370117f, 1.04004f, 0.0273438f, -0.408203f, - 0.920898f, -0.0986328f, -0.514648f, 0.956055f, 0.0527344f, - -0.428711f, 0.960938f, 0.109375f, -0.522461f, 0.801758f, - -0.277344f, -0.634766f, 0.882812f, 0.0527344f, -0.34668f, - 0.981445f, -0.09375f, -0.298828f, 0.952148f, -0.213867f, - -0.25293f, 0.90918f, -0.132812f, -0.493164f, 0.885742f, - -0.177734f, -0.525391f, 0.915039f, -0.0605469f, -0.439453f, - 0.87207f, -0.0986328f, -0.506836f, 0.905273f, -0.0732422f, - -0.462891f, 0.870117f, -0.0966797f, -0.511719f, 0.897461f, - -0.0234375f, -0.464844f, 0.868164f, -0.0283203f, -0.474609f, - 0.919922f, 0.0205078f, -0.34375f, 0.889648f, -0.00390625f, - -0.445312f, 0.804688f, -0.0263672f, -0.417969f, 0.806641f, - 0.0410156f, -0.399414f, 0.914062f, -0.0722656f, -0.386719f, - 0.890625f, -0.0615234f, -0.40625f, 0.928711f, 0.0253906f, - -0.118164f, 0.943359f, -0.000976562f, -0.398438f, 0.811523f, - -0.0605469f, -0.234375f, 0.879883f, 0.198242f, -0.509766f, - 0.958008f, 0.0361328f, -0.328125f, 0.938477f, -0.00976562f, - -0.429688f, 0.916016f, -0.0185547f, -0.266602f, 0.898438f, - -0.0380859f, -0.450195f, 0.870117f, 0.162109f, -0.210938f, - 0.899414f, 0.117188f, -0.517578f, 0.756836f, -0.0820312f, - -0.361328f, 0.868164f, -0.0576172f, -1.29883f, 0.515625f, - -0.00195312f, -1.13281f, 0.628906f, 0.00390625f, -0.103516f, - 0.485352f, -0.046875f, -0.922852f, 0.412109f, -0.108398f, - -0.898438f, 0.446289f, -0.111328f, -0.925781f, 0.375977f, - -0.125977f, -0.825195f, 0.446289f, -0.0966797f, -0.958008f, - 0.389648f, -0.0810547f, -1.00781f, 0.532227f, -0.104492f, - -1.0791f, 0.459961f, -0.138672f, -0.941406f, 0.509766f, - -0.107422f, -1.14062f, 0.447266f, -0.195312f, -0.867188f, - 0.474609f, -0.233398f, -0.751953f, 0.612305f, -0.126953f, - -0.661133f, 0.702148f, -0.199219f, -0.260742f, 0.856445f, - -0.0292969f, -0.743164f, 0.921875f, -0.0371094f, -0.293945f, - 0.902344f, -0.103516f, -0.416016f, 0.955078f, -0.00488281f, - -0.232422f, 0.951172f, -0.0498047f, -0.331055f, 0.871094f, - 0.00390625f, -0.186523f, 0.905273f, 0.0566406f, -0.249023f, - 0.677734f, 0.0253906f, 0.145508f, 0.826172f, 0.251953f, - -0.428711f, 0.764648f, 0.488281f, -0.265625f, 0.886719f, - 0.256836f, -0.408203f, 0.744141f, 0.689453f, -0.611328f, - 0.755859f, 0.431641f, -0.525391f, 0.588867f, 0.637695f, - -0.750977f, 0.578125f, 0.568359f, -0.540039f, 0.512695f, - 0.530273f, -0.722656f, 0.498047f, 0.526367f, -0.788086f, - 0.647461f, 0.522461f, -0.862305f, 0.567383f, 0.422852f, - -0.765625f, 0.648438f, 0.405273f, -0.938477f, 0.583008f, - 0.272461f, -1.15137f, 0.481445f, 0.00585938f, -0.788086f, - 0.454102f, -0.0615234f, -0.885742f, 0.306641f, -0.333984f, - -0.678711f, 0.322266f, -0.288086f, -0.615234f, 0.220703f, - -0.476562f, -0.748047f, 0.223633f, -0.396484f, -0.729492f, - 0.235352f, -0.510742f, -0.806641f, 0.227539f, -0.476562f, - -0.665039f, 0.275391f, -0.47168f, -0.938477f, 0.345703f, - -0.369141f, -0.709961f, 0.482422f, -0.393555f, -0.380859f, - 0.759766f, -0.143555f, -0.529297f, 0.956055f, -0.0185547f, - -0.12207f, 1.15527f, 0.0380859f, -0.529297f, 1.04102f, - 0.203125f, -0.0283203f, 1.11719f, 0.0888672f, -0.258789f, - 1.02734f, 0.297852f, -0.0244141f, 1.03223f, 0.211914f, - -0.0859375f, 0.798828f, 0.216797f, 0.19043f, 0.891602f, - 0.256836f, -0.102539f, 0.662109f, 0.263672f, 0.208984f, - 0.810547f, 0.380859f, -0.235352f, 0.707031f, 0.507812f, - -0.0800781f, 0.902344f, 0.470703f, -0.301758f, 0.577148f, - 0.674805f, -0.500977f, 0.748047f, 0.472656f, -0.493164f, - 0.478516f, 0.611328f, -1.04395f, 0.491211f, 0.651367f, - -0.581055f, 0.25293f, 0.325195f, -0.950195f, 0.224609f, - 0.404297f, -1.04883f, 0.116211f, -0.00292969f, -0.980469f, - 0.0566406f, 0.0195312f, -0.821289f, 0.0166016f, -0.141602f, - -0.959961f, -0.0322266f, -0.158203f, -0.837891f, 0.119141f, - -0.224609f, -1.00781f, 0.09375f, -0.151367f, -1.00684f, - 0.248047f, -0.238281f, -0.973633f, 0.271484f, -0.324219f, - -0.942383f, 0.443359f, -0.298828f, -0.845703f, 0.581055f, - -0.291992f, -0.700195f, 0.65918f, -0.319336f, -0.262695f, - 0.818359f, -0.286133f, -0.579102f, 0.827148f, -0.272461f, - -0.0908203f, 0.935547f, -0.233398f, -0.374023f, 0.920898f, - -0.137695f, 0.000976562f, 0.964844f, -0.12793f, -0.285156f, - 0.880859f, -0.0244141f, -0.0830078f, 0.930664f, 0.00976562f, - -0.15332f, 0.731445f, 0.172852f, 0.0380859f, 0.876953f, - 0.264648f, -0.194336f, 0.601562f, 0.613281f, -0.132812f, - 0.803711f, 0.53418f, -0.268555f, 0.933594f, 0.899414f, - -0.332031f, 0.923828f, 0.521484f, -0.425781f, 0.972656f, - 0.959961f, -0.506836f, 0.797852f, 0.506836f, -0.125977f, - 0.740234f, 0.756836f, -0.262695f, 0.783203f, 0.691406f, - -0.422852f, 0.474609f, 0.459961f, 0.00390625f, 0.683594f, - 0.941406f, -0.0625f, 0.0810547f, 1.06934f, 0.0625f, - 0.546875f, 0.967773f, 0.0351562f, 0.202148f, 1.32422f, - -0.148438f, 0.269531f, 0.818359f, -0.3125f, 0.0742188f, - 1.23633f, -0.188477f, -0.0263672f, 0.713867f, -0.139648f, - -0.230469f, 0.8125f, -0.134766f, -0.246094f, 0.734375f, - -0.09375f, -0.22168f, 1.17188f, -0.158203f, -0.209961f, - 1.09766f, -0.141602f, 0.00976562f, 0.991211f, -0.238281f, - 0.0341797f, 0.979492f, -0.207031f, -0.0166016f, 1.00293f, - -0.228516f, 0.0527344f, 1.28711f, -0.167969f, 0.164062f, - 0.925781f, -0.255859f, 0.170898f, 0.956055f, -0.256836f, - 0.191406f, 0.936523f, -0.145508f, 0.205078f, 0.904297f, - -0.257812f, 0.117188f, 0.870117f, -0.188477f, 0.166992f, - 1.02441f, -0.288086f, 0.163086f, 0.938477f, -0.262695f, - 0.138672f, 0.947266f, -0.219727f, 0.0947266f, 0.992188f, - -0.0732422f, 0.116211f, 1.00293f, -0.203125f, 0.0205078f, - 0.933594f, -0.235352f, -0.0126953f, 0.844727f, -0.0693359f, - 0.119141f, 1.00195f, -0.110352f, 0.135742f, 1.00391f, - -0.101562f, 0.0546875f, 1.06543f, -0.18457f, 0.0507812f, - 0.933594f, -0.112305f, 0.00976562f, 0.973633f, -0.193359f, - -0.0185547f, 0.885742f, -0.279297f, -0.0107422f, 1.02344f, - -0.078125f, -0.0107422f, 1.0127f, 0.140625f, -0.142578f, - 0.994141f, -0.132812f, -0.145508f, 0.90918f, -0.000976562f, - -0.22168f, 1.0498f, -0.148438f, -0.185547f, 1.2207f, - -0.172852f, -0.196289f, 1.0957f, -0.183594f, -0.0390625f, - 1.34863f, -0.21875f, -0.745117f, 0.952148f, 0.0126953f, - -0.196289f, 1.29492f, -0.150391f, -0.768555f, 0.853516f, - -0.163086f, -0.25f, 0.358398f, -0.0507812f, -0.80957f, - 0.139648f, 0.125f, -0.790039f, -0.257812f, 0.175781f, - -0.795898f, -0.135742f, 0.00585938f, -0.841797f, -0.279297f, - 0.0419922f, -0.708984f, 0.0175781f, -0.0957031f, -0.75f, - -0.204102f, 0.0419922f, -0.78125f, 0.0322266f, -0.125f, - -0.787109f, -0.0380859f, -0.0683594f, -1.06641f, 0.0947266f, - -0.238281f, -1.02148f, 0.117188f, -0.176758f, -1.77539f, - 0.0117188f, -0.31543f, -1.80566f, -0.0625f, -0.273438f, - -0.764648f, 0.143555f, -0.21875f, -0.746094f, 0.162109f, - -0.0351562f, -0.858398f, 0.186523f, -0.250977f, -0.918945f, - 0.0458984f, 0.135742f, -0.988281f, 0.241211f, -0.192383f, - -0.963867f, 0.277344f, -0.129883f, -0.994141f, 0.22168f, - -0.169922f, -0.96582f, 0.290039f, -0.217773f, -0.990234f, - 0.185547f, -0.152344f, -0.978516f, 0.169922f, -0.0361328f, - -0.912109f, 0.119141f, -0.352539f, -0.838867f, 0.183594f, - -0.0380859f, -0.753906f, 0.274414f, -0.575195f, -0.770508f, - 0.192383f, -0.482422f, -0.904297f, -0.0234375f, -0.498047f, - -0.817383f, 0.0527344f, -0.277344f, -0.428711f, 0.114258f, - -0.634766f, -0.427734f, -0.0429688f, -0.405273f, -0.318359f, - 0.118164f, -0.870117f, -0.193359f, 0.171875f, -0.938477f, - -0.1875f, 0.208008f, -1.04688f, -0.246094f, 0.0849609f, - -1.72461f, -0.353516f, 0.234375f, -1.05859f, -0.304688f, - 0.151367f, -1.38672f, -0.663086f, 0.242188f, -0.939453f, - -0.481445f, 0.189453f, -0.87793f, -0.831055f, 0.358398f, - -0.555664f, -0.621094f, 0.444336f, -0.287109f, -0.802734f, - 0.367188f, -0.25293f, -0.753906f, 0.413086f, 0.0126953f, - -1.0127f, 0.335938f, -0.250977f, -0.942383f, 0.563477f, - 0.000976562f, -1.33691f, 0.138672f, -0.365234f, -0.996094f, - 0.542969f, -0.0400391f, -1.44434f, 0.239258f, -0.655273f, - -0.625977f, 0.313477f, -0.444336f, -0.589844f, -0.106445f, - -0.217773f, 0.00585938f, -0.760742f, -0.219727f, 0.0654297f, - -0.626953f, -0.0439453f, 0.0732422f, -1.22168f, 0.0126953f, - 0.210938f, -0.754883f, -0.0839844f, 0.161133f, -0.980469f, - -0.124023f, 0.141602f, -0.828125f, -0.199219f, 0.152344f, - -0.80957f, -0.230469f, 0.231445f, -0.865234f, -0.259766f, - 0.232422f, -0.892578f, -0.305664f, 0.323242f, -0.87793f, - -0.294922f, 0.274414f, -1.0791f, -0.435547f, 0.222656f, - -0.863281f, -0.375f, 0.219727f, -1.0166f, -0.525391f, - 0.0341797f, -0.834961f, -0.454102f, 0.0371094f, -0.984375f, - -0.486328f, -0.135742f, -0.700195f, -0.339844f, -0.0078125f, - -1.20508f, -0.665039f, -0.791016f, 0.00390625f, -0.277344f, - 0.0136719f, -0.492188f, -0.779297f, -1.49316f, 0.0957031f, - -0.179688f, -0.587891f, 0.665039f, 0.398438f, -0.980469f, - 0.428711f, 0.254883f, -0.828125f, 0.724609f, 0.663086f, - -0.90625f, 0.555664f, 0.0791016f, -0.837891f, 0.591797f, - 0.257812f, -0.806641f, 0.609375f, 0.0458984f, -0.779297f, - 0.529297f, 0.00292969f, -0.829102f, 0.640625f, 0.0371094f, - -0.797852f, 0.583008f, 0.208984f, -0.864258f, 0.583984f, - -0.0615234f, -0.758789f, 0.72168f, 0.0947266f, -0.921875f, - 0.605469f, -0.264648f, -0.75293f, 0.701172f, 0.107422f, - -0.735352f, 0.44043f, -0.527344f, -0.398438f, 0.46875f, - -0.421875f, -0.424805f, 0.0810547f, -0.754883f, -0.241211f, - -0.107422f, -1.13574f, -0.410156f, -0.0400391f, -0.942383f, - -0.454102f, -0.12207f, -1.24902f, -0.509766f, -0.393555f, - -0.959961f, -0.511719f, -0.381836f, -1.04883f, -0.924805f, - -0.756836f, -1.17969f, -0.521484f, -0.105469f, -1.16504f, - -0.767578f, -0.477539f, -0.401367f, -0.0341797f, -0.341797f, - 0.0507812f, 0.389648f, -0.507812f, 0.186523f, 0.438477f, - -1.33594f, 0.625977f, 0.518555f, -0.671875f, 0.182617f, - 0.432617f, -1.18359f, 0.132812f, 0.414062f, -0.782227f, - 0.0615234f, 0.401367f, -1.30176f, -0.0683594f, -0.100586f, - -0.586914f, 0.0302734f, 0.191406f, -0.983398f, -0.0273438f, - -0.735352f, -0.224609f, -0.342773f, -0.241211f, -0.566406f, - 0.015625f, -1.1084f, -0.00976562f, -0.652344f, -0.75293f, - 0.239258f, -0.449219f, -1.08789f, 0.107422f, -0.572266f, - -0.887695f, 0.407227f, -0.423828f, -0.919922f, 0.173828f, - -0.705078f, -0.825195f, 0.411133f, -0.484375f, -0.799805f, - 0.237305f, -0.776367f, -0.745117f, 0.459961f, -0.819336f, - -0.749023f, 0.208008f, -0.788086f, -0.716797f, 0.226562f, - -0.795898f, -0.72168f, 0.123047f, -0.790039f, -0.705078f, - 0.101562f, -0.720703f, -0.745117f, -0.0517578f, -0.771484f, - -0.701172f, -0.0175781f, -0.758789f, -0.765625f, -0.0917969f, - -0.745117f, -0.751953f, -0.149414f, -0.6875f, -0.660156f, - -0.0166016f, -0.782227f, -0.592773f, -0.0205078f, -0.726562f, - -0.376953f, 0.119141f, -0.599609f, -0.371094f, 0.0107422f, - -0.736328f, -0.325195f, 0.0771484f, -0.768555f, -0.388672f, - -0.0273438f, -0.750977f, -0.477539f, 0.107422f, -0.919922f, - -0.514648f, 0.125f, -0.961914f, -0.37793f, 0.0136719f, - -0.981445f, -0.447266f, -0.0107422f, -0.823242f, -0.303711f, - 0.0986328f, -1.00684f, -0.366211f, 0.0986328f, -1.14551f, - -0.239258f, 0.140625f, -0.894531f, -0.297852f, 0.0849609f, - -0.949219f, -0.341797f, 0.131836f, -0.966797f, -0.380859f, - 0.0947266f, -0.75293f, -0.391602f, 0.0839844f, -0.908203f, - -0.40625f, 0.161133f, -0.860352f, -0.452148f, 0.1875f, - -0.950195f, -0.496094f, 0.200195f, -0.828125f, -0.581055f, - 0.0771484f, -0.93457f, -0.607422f, 0.0996094f, -0.863281f, - -0.59375f, 0.0927734f, -0.802734f, -0.604492f, 0.0947266f, - -0.807617f, -0.722656f, 0.101562f, -0.844727f, -0.711914f, - 0.149414f, -1.03125f, -0.77832f, 0.125977f, -0.78418f, - -0.740234f, 0.121094f, -0.891602f, -0.808594f, 0.164062f, - -0.650391f, -0.80957f, 0.0888672f, -0.416992f, -0.866211f, - 0.155273f, -0.382812f, -0.880859f, 0.0849609f, -0.264648f, - -0.775391f, 0.229492f, -0.389648f, -0.814453f, 0.0664062f, - -0.226562f, -0.625f, 0.414062f, -0.274414f, -0.681641f, - 0.0292969f, -0.0478516f, -0.711914f, 0.794922f, -0.388672f, - -0.584961f, 0.368164f, -0.257812f, -0.545898f, 1.09277f, - -0.277344f, -0.125977f, 0.822266f, -0.365234f, -0.467773f, - 0.714844f, -0.413086f, -0.136719f, 1.57227f, -0.0947266f, - -0.223633f, 0.817383f, -0.0556641f, -0.0322266f, 1.18945f, - -0.191406f, -0.498047f, 0.991211f, -0.231445f, -0.246094f, - 0.8125f, -0.239258f, -0.755859f, 0.853516f, -0.228516f, - -0.821289f, 0.503906f, -0.121094f, -0.795898f, 0.523438f, - -0.220703f, -0.773438f, 0.517578f, -0.274414f, -0.757812f, - 0.539062f, -0.222656f, -0.770508f, 0.396484f, -0.115234f, - -1.2334f, 0.485352f, -0.217773f, -0.94043f, 1.01758f, - -0.202148f, -0.605469f, 0.0546875f, 0.0957031f, -0.639648f, - -0.661133f, 0.245117f, -0.750977f, 0.0615234f, -0.726562f, - -0.879883f, -0.432617f, -1.05859f, -1.29688f, 0.00488281f, - 0.193359f, -0.939453f, 0.209961f, -0.209961f, -0.793945f, - 0.251953f, 0.722656f, -0.447266f, 0.0615234f, 0.855469f, - -0.454102f, -0.0126953f, 0.0527344f, -0.342773f, 0.154297f, - 1.3877f, -0.65918f, 0.133789f, 0.0576172f, -0.233398f, - -0.12207f, 0.46582f, -1.09961f, 0.438477f, -0.641602f, - -0.861328f, 0.197266f, -1.99902f, -0.932617f, 0.234375f, - 0.389648f, -0.792969f, -0.0908203f, 1.66797f, -1.0459f, - 0.0107422f, -0.543945f, -0.80957f, 0.206055f, -0.27832f, - -0.915039f, 0.104492f, -0.301758f, -0.891602f, 0.0556641f, - -0.681641f, -0.901367f, 0.0498047f, -0.461914f, -0.927734f, - -0.0390625f, -0.229492f, -1.04004f, 0.0869141f, -0.435547f, - -1.02148f, 0.0947266f, -0.527344f, -0.979492f, 0.0751953f, - 0.266602f, -0.786133f, -0.0224609f, -0.0947266f, -0.702148f, - -0.00683594f, -0.316406f, -0.698242f, -0.317383f, 1.92578f, - -1.0498f, 0.0273438f, -1.14258f, -0.226562f, 0.233398f, - -0.995117f, -0.9375f, 0.0146484f, -0.223633f, -0.49707f, - -0.0078125f, -1.95703f, -0.847656f, 0.157227f, 0.129883f, - -0.459961f, -0.114258f, 2.0f, -1.13574f, -0.0839844f, - -0.0878906f, -0.783203f, 0.131836f, -0.803711f, -0.90332f, - 0.208984f, -0.365234f, -0.97168f, -0.0322266f, 0.186523f, - -0.924805f, 0.00292969f, -0.272461f, -0.890625f, 0.015625f, - -0.333008f, -0.932617f, 0.180664f, -0.459961f, -0.90918f, - 0.240234f, -0.625977f, -1.1582f, 0.0996094f, -0.170898f, - -1.08887f, -0.00976562f, -0.849609f, -0.430664f, 0.139648f, - -0.308594f, -0.572266f, -0.722656f, 1.83496f, -1.00977f, - 0.387695f, 0.487305f, -0.268555f, 0.0712891f, -0.0136719f, - -1.5332f, 0.290039f, -0.0351562f, -0.861328f, 1.98535f, - -1.16602f, -0.602539f, 0.441406f, 0.175781f, -0.605469f, - -0.831055f, 0.686523f, -0.984375f, 0.494141f, -0.489258f, - -0.895508f, 0.371094f, -0.665039f, -1.14258f, -0.214844f, - -0.140625f, -1.06348f, -0.0996094f, 0.255859f, -0.874023f, - 0.193359f, -0.0947266f, -0.959961f, -0.0966797f, 0.00195312f, - -0.996094f, -0.0117188f, -0.174805f, -0.962891f, 0.106445f, - -0.162109f, -1.04297f, -0.0283203f, -0.306641f, -1.06738f, - -0.0224609f, -0.129883f, -1.03223f, 0.129883f, 0.195312f, - -1.08789f, -0.130859f, 0.649414f, -0.572266f, -0.0136719f, - -0.793945f, -0.382812f, 0.0f, -1.08301f, -0.78125f, - -0.0224609f, -0.339844f, -0.629883f, -0.0947266f, -1.83789f, - -1.01562f, 0.046875f, 0.223633f, -0.808594f, 0.0957031f, - 1.09766f, -0.756836f, -0.0488281f, 0.157227f, -0.59082f, - -0.103516f, 0.929688f, -0.816406f, -0.0322266f, -0.426758f, - -0.868164f, -0.209961f, -1.99902f, -0.986328f, -0.00878906f, - -0.365234f, -0.980469f, 0.0439453f, 0.59375f, -0.994141f, - 0.0253906f, 0.0371094f, -0.970703f, -0.0273438f, -0.120117f, - -0.935547f, 0.00195312f, -0.235352f, -0.952148f, -0.0263672f, - -0.194336f, -0.917969f, -0.0195312f, -0.261719f, -0.928711f, - -0.0234375f, -0.219727f, -0.945312f, 0.0107422f, -0.228516f, - -0.938477f, 0.00683594f, -0.178711f, -0.791016f, 0.03125f, - -0.255859f, -0.789062f, 0.0f, -0.141602f, -0.789062f, - 0.232422f, -0.285156f, -0.788086f, 0.228516f, -0.28125f, - -1.0f, 0.258789f, -0.277344f, -0.999023f, 0.28125f, - -0.25293f, -1.06152f, 0.046875f, -0.421875f, -1.07715f, - 0.0390625f, -0.224609f, -0.923828f, -0.0205078f, -0.335938f, - -0.984375f, -0.0966797f, -0.34668f, -0.990234f, -0.191406f, - -0.301758f, -1.03613f, -0.241211f, -0.37207f, -0.975586f, - -0.267578f, -0.460938f, -1.00977f, -0.320312f, -0.382812f, - -0.913086f, -0.257812f, -0.457031f, -0.925781f, -0.256836f, - -0.34668f, -0.889648f, -0.237305f, -0.393555f, -0.897461f, - -0.239258f, -0.429688f, -0.844727f, -0.21875f, -0.428711f, - -0.87207f, -0.203125f, -0.368164f, -0.84668f, -0.101562f, - -0.423828f, -0.875977f, -0.165039f, -0.363281f, -0.884766f, - -0.0625f, -0.473633f, -0.90332f, -0.078125f, -0.138672f, - -0.918945f, -0.198242f, -0.25f, -0.928711f, -0.138672f, - -0.267578f, -1.08203f, 0.00488281f, -0.575195f, -1.125f, - -0.0332031f, -0.4375f, -0.924805f, 0.078125f, -0.305664f, - -0.93457f, -0.0166016f, -0.475586f, -0.94043f, -0.00488281f, - -0.533203f, -0.956055f, 0.00292969f, -0.391602f, -1.00293f, - 0.0361328f, -0.711914f, -1.0166f, 0.0332031f, -0.448242f, - -0.806641f, -0.21582f, -0.556641f, -0.759766f, -0.0214844f, - -0.626953f, -0.700195f, -0.263672f, -0.308594f, -0.608398f, - -0.236328f, -0.253906f, -0.616211f, -0.378906f, 0.224609f, - -0.498047f, -0.399414f, 0.206055f, -0.516602f, -0.228516f, - 0.743164f, -0.174805f, -0.125f, 0.760742f, -0.0214844f, - -0.135742f, 0.966797f, 0.240234f, 0.0332031f, 1.01855f, - 0.105469f, 0.15332f, 0.950195f, 0.240234f, 0.0732422f, - 1.16895f, 0.245117f, 0.206055f, 0.952148f, 0.273438f, - -0.0390625f, 1.2793f, 0.404297f, 0.303711f, 0.720703f, - 0.369141f, 0.0966797f, 0.918945f, 0.329102f, 0.0390625f, - 0.991211f, 0.397461f, -0.124023f, 0.866211f, 0.210938f, - 0.130859f, 1.08789f, 0.317383f, 0.0537109f, 0.858398f, - 0.245117f, 0.0732422f, 0.741211f, 0.419922f, 0.0302734f, - 0.681641f, 0.485352f, -0.0214844f, 0.641602f, 0.520508f, - -0.129883f, 0.839844f, 0.490234f, 0.00390625f, 0.676758f, - 0.581055f, -0.0146484f, 0.692383f, 0.432617f, -0.0371094f, - 0.807617f, 0.664062f, 0.255859f, 0.216797f, 1.22559f, - 0.0195312f, 1.22168f, 1.2793f, -0.405273f, 1.72559f, - 0.708984f, -0.209961f, 0.579102f, 0.821289f, 0.0380859f, - 0.605469f, 0.80957f, 0.147461f, 0.419922f, 0.869141f, - 0.0390625f, 0.5625f, 0.786133f, 0.0654297f, 0.594727f, - 0.879883f, 0.0166016f, 0.480469f, 0.835938f, 0.00195312f, - 0.414062f, 0.899414f, -0.03125f, 0.344727f, 0.889648f, - 0.0185547f, 0.236328f, 0.932617f, -0.00585938f, 0.255859f, - 0.910156f, 0.0898438f, 0.262695f, 0.945312f, 0.0126953f, - 0.279297f, 0.860352f, 0.0507812f, 0.322266f, 0.913086f, - 0.00195312f, 0.296875f, 0.875977f, 0.0078125f, 0.373047f, - 0.922852f, -0.0244141f, 0.267578f, 0.884766f, 0.0117188f, - 0.347656f, 0.926758f, -0.0371094f, 0.266602f, 0.894531f, - -0.00683594f, 0.345703f, 0.926758f, -0.0478516f, 0.269531f, - 0.887695f, 0.0146484f, 0.360352f, 0.927734f, -0.03125f, - 0.272461f}; + 0.892578f, -0.0810547f, 0.0146484f, 0.929688f, -0.0644531f, + -0.0234375f, 0.996094f, -0.0136719f, 0.0185547f, 1.02344f, + -0.0615234f, -0.0449219f, 0.978516f, 0.125977f, 0.0400391f, + 0.996094f, 0.0332031f, -0.0117188f, 0.963867f, 0.107422f, + 0.0214844f, 0.980469f, 0.0185547f, -0.00683594f, 0.952148f, + 0.0361328f, 0.0253906f, 0.976562f, -0.00390625f, -0.0126953f, + 0.97168f, 0.0205078f, 0.0517578f, 1.01074f, 0.015625f, + -0.0234375f, 0.953125f, -0.000976562f, 0.0390625f, 0.977539f, + -0.0224609f, -0.00976562f, 0.954102f, 0.0244141f, 0.0439453f, + 0.986328f, 0.00292969f, -0.000976562f, 0.967773f, 0.0537109f, + 0.046875f, 0.99707f, 0.0175781f, -0.000976562f, 0.951172f, + 0.0390625f, 0.0341797f, 0.974609f, -0.00878906f, -0.000976562f, + 0.948242f, 0.0185547f, 0.0478516f, 0.976562f, -0.000976562f, + -0.00683594f, 0.958984f, 0.0263672f, 0.078125f, 0.982422f, + -0.0205078f, 0.0283203f, 0.930664f, 0.00878906f, 0.0664062f, + 0.970703f, 0.00390625f, -0.0078125f, 0.945312f, 0.0380859f, + -0.00585938f, 0.972656f, 0.0419922f, -0.0478516f, 1.01953f, + 0.240234f, -0.182617f, 1.00977f, 0.18457f, -0.126953f, + 1.05566f, 0.0751953f, -0.0888672f, 1.09766f, 0.0732422f, + -0.0898438f, 1.21484f, 0.119141f, -0.000976562f, 1.23633f, + 0.194336f, -0.447266f, 1.31445f, 0.213867f, -0.118164f, + 1.30762f, 0.0908203f, -0.260742f, 0.860352f, 0.141602f, + -0.166016f, 0.868164f, 0.0429688f, -0.258789f, 0.727539f, + 0.0419922f, -0.21875f, 0.740234f, 0.0126953f, -0.162109f, + 0.652344f, -0.00292969f, -0.185547f, 0.666992f, 0.0800781f, + -0.272461f, 0.852539f, -0.0478516f, -0.228516f, 0.819336f, + -0.0996094f, -0.180664f, 0.959961f, -0.0537109f, -0.240234f, + 0.935547f, -0.0917969f, -0.269531f, 0.988281f, -0.0507812f, + -0.197266f, 0.981445f, -0.0712891f, -0.323242f, 0.964844f, + -0.0683594f, -0.203125f, 0.941406f, -0.0898438f, -0.236328f, + 0.942383f, -0.0429688f, -0.206055f, 0.921875f, -0.0527344f, + -0.239258f, 0.976562f, -0.0742188f, -0.261719f, 0.958008f, + -0.09375f, -0.311523f, 0.949219f, -0.0839844f, -0.242188f, + 0.949219f, -0.0742188f, -0.323242f, 0.973633f, -0.0263672f, + -0.238281f, 0.958984f, -0.0488281f, -0.293945f, 0.931641f, + -0.0214844f, -0.225586f, 0.931641f, 0.0195312f, -0.225586f, + 0.810547f, -0.0947266f, -0.15332f, 0.947266f, 0.241211f, + -0.100586f, 0.326172f, 0.286133f, -0.12207f, 0.855469f, + 0.677734f, -0.228516f, 0.229492f, 1.08398f, 0.0224609f, + 0.822266f, 0.759766f, -0.0722656f, 0.294922f, 1.42676f, + 0.147461f, 0.239258f, 0.755859f, 0.142578f, -0.120117f, + 1.00977f, -0.0722656f, -0.154297f, 0.832031f, -0.0576172f, + -0.15332f, 1.10156f, -0.0273438f, -0.119141f, 1.05078f, + 0.0166016f, -0.0927734f, 1.09961f, -0.0703125f, -0.0751953f, + 1.04688f, -0.00195312f, -0.078125f, 0.897461f, -0.0625f, + -0.078125f, 0.854492f, -0.0947266f, -0.123047f, 0.811523f, + -0.0488281f, -0.113281f, 0.796875f, 0.0f, -0.0488281f, + 0.961914f, -0.177734f, -0.0898438f, 0.859375f, -0.172852f, + 0.0126953f, 1.1084f, -0.158203f, 0.0292969f, 1.0791f, + -0.152344f, 0.154297f, 1.29492f, -0.126953f, 0.134766f, + 1.23145f, -0.0878906f, -0.200195f, 0.667969f, -0.216797f, + -0.0888672f, 0.935547f, -0.143555f, 0.000976562f, 1.13281f, + -0.0498047f, 0.00195312f, 1.05469f, -0.231445f, 0.0927734f, + 0.956055f, -0.292969f, 0.0625f, 0.927734f, -0.112305f, + 0.0585938f, 0.975586f, -0.163086f, 0.0957031f, 1.03418f, + -0.229492f, 0.000976562f, 0.985352f, -0.09375f, -0.00585938f, + 0.945312f, -0.140625f, -0.0302734f, 0.998047f, -0.208008f, + -0.0507812f, 0.916016f, -0.112305f, 0.123047f, 0.981445f, + -0.205078f, 0.129883f, 1.02832f, -0.211914f, 0.105469f, + 1.01367f, -0.142578f, 0.111328f, 1.00098f, -0.110352f, + 0.0986328f, 0.999023f, -0.15918f, 0.0839844f, 0.922852f, + -0.223633f, 0.261719f, 1.06641f, -0.138672f, 0.240234f, + 0.916016f, -0.296875f, 0.00488281f, 1.04199f, -0.128906f, + 0.0341797f, 1.0791f, -0.265625f, 0.015625f, 0.963867f, + -0.161133f, 0.015625f, 0.958008f, -0.0722656f, -0.125f, + 1.03125f, -0.19043f, -0.0722656f, 1.16602f, -0.126953f, + -0.143555f, 1.12793f, -0.197266f, -0.120117f, 1.26465f, + -0.232422f, -0.226562f, 1.125f, -0.0712891f, -0.0927734f, + 1.26465f, -0.145508f, -0.551758f, 0.90918f, -0.163086f, + -0.228516f, 1.2041f, -0.0371094f, -0.493164f, 0.827148f, + 0.0371094f, -0.162109f, 0.568359f, -0.195312f, -0.641602f, + 0.438477f, -0.212891f, -0.513672f, 0.208008f, -0.0488281f, + -0.776367f, 0.0488281f, -0.115234f, -0.84375f, -0.314453f, + 0.106445f, -0.966797f, -0.0078125f, 0.00976562f, -1.01953f, + -0.220703f, -0.0322266f, -0.994141f, 0.0117188f, -0.248047f, + -0.975586f, 0.121094f, -0.0205078f, -0.947266f, 0.00292969f, + -0.160156f, -0.9375f, 0.0175781f, -0.0986328f, -0.916992f, + -0.0195312f, -0.208008f, -0.9375f, -0.0654297f, -0.134766f, + -0.948242f, -0.0185547f, -0.231445f, -0.977539f, -0.0537109f, + -0.198242f, -1.0166f, 0.0439453f, -0.433594f, -0.994141f, + -0.0595703f, -0.389648f, -1.07129f, 0.0859375f, -0.109375f, + -1.01953f, 0.0966797f, -0.12207f, -1.01074f, 0.125977f, + -0.192383f, -1.0f, 0.0820312f, -0.166016f, -1.04688f, + 0.0751953f, -0.265625f, -1.00879f, 0.139648f, -0.135742f, + -1.00977f, 0.0644531f, -0.235352f, -0.989258f, 0.100586f, + -0.144531f, -0.858398f, 0.0273438f, -0.22168f, -0.878906f, + -0.0634766f, -0.1875f, -0.905273f, -0.0195312f, -0.232422f, + -0.926758f, -0.0732422f, -0.319336f, -1.05078f, -0.00878906f, + -0.5625f, -1.05176f, 0.111328f, -0.456055f, -0.942383f, + -0.0146484f, -0.171875f, -0.946289f, -0.0224609f, -0.174805f, + -0.901367f, -0.0283203f, -0.332031f, -0.948242f, -0.0732422f, + -0.262695f, -0.867188f, 0.0351562f, -0.271484f, -0.913086f, + -0.0878906f, -0.259766f, -1.2793f, -0.226562f, -0.382812f, + -1.2334f, 0.0400391f, -0.260742f, -1.22949f, -0.216797f, + -0.432617f, -1.21191f, -0.131836f, -0.368164f, -1.10938f, + -0.323242f, -0.505859f, -1.01953f, -0.197266f, -0.405273f, + -1.25488f, -0.347656f, -0.448242f, -0.803711f, 0.0595703f, + -0.253906f, -0.489258f, -0.00390625f, 0.101562f, 0.15332f, + -0.423828f, -0.0195312f, 0.527344f, -0.350586f, -0.24707f, + 0.363281f, -1.33789f, -0.214844f, 0.322266f, -0.768555f, + -0.279297f, 0.266602f, -0.918945f, -0.320312f, 0.0634766f, + -0.97168f, -0.102539f, 0.114258f, -0.891602f, -0.158203f, + 0.0283203f, -0.998047f, -0.198242f, 0.0634766f, -0.931641f, + -0.239258f, 0.147461f, -0.963867f, -0.219727f, 0.142578f, + -1.02051f, -0.279297f, 0.105469f, -0.955078f, -0.238281f, + 0.104492f, -1.02637f, -0.291992f, -0.0302734f, -1.02637f, + -0.225586f, 0.000976562f, -0.907227f, -0.12793f, 0.03125f, + -0.979492f, -0.100586f, 0.0625f, -0.921875f, -0.155273f, + 0.146484f, -0.929688f, -0.158203f, 0.155273f, -0.981445f, + -0.171875f, 0.212891f, -0.927734f, -0.166992f, 0.198242f, + -1.05371f, -0.197266f, 0.189453f, -0.954102f, -0.113281f, + 0.189453f, -1.00293f, -0.180664f, 0.111328f, -0.967773f, + -0.109375f, 0.125977f, -0.966797f, -0.146484f, 0.0712891f, + -0.982422f, -0.0908203f, 0.112305f, -0.928711f, -0.149414f, + 0.0146484f, -1.00781f, -0.0996094f, 0.102539f, -0.810547f, + -0.157227f, -0.0117188f, -0.820312f, -0.0371094f, 0.28418f, + -0.446289f, -0.166016f, 0.208008f, -0.03125f, -0.0761719f, + 0.755859f, -0.280273f, -0.316406f, 1.42188f, 0.198242f, + -0.49707f, 1.37207f, -0.556641f, -0.382812f, 1.36523f, + 0.110352f, -0.342773f, 1.25391f, -0.225586f, -0.570312f, + 0.958984f, 0.0722656f, -0.237305f, 0.984375f, 0.0957031f, + -0.416992f, 0.853516f, 0.0400391f, -0.416016f, 0.873047f, + 0.0644531f, -0.370117f, 1.04004f, 0.0273438f, -0.408203f, + 0.920898f, -0.0986328f, -0.514648f, 0.956055f, 0.0527344f, + -0.428711f, 0.960938f, 0.109375f, -0.522461f, 0.801758f, + -0.277344f, -0.634766f, 0.882812f, 0.0527344f, -0.34668f, + 0.981445f, -0.09375f, -0.298828f, 0.952148f, -0.213867f, + -0.25293f, 0.90918f, -0.132812f, -0.493164f, 0.885742f, + -0.177734f, -0.525391f, 0.915039f, -0.0605469f, -0.439453f, + 0.87207f, -0.0986328f, -0.506836f, 0.905273f, -0.0732422f, + -0.462891f, 0.870117f, -0.0966797f, -0.511719f, 0.897461f, + -0.0234375f, -0.464844f, 0.868164f, -0.0283203f, -0.474609f, + 0.919922f, 0.0205078f, -0.34375f, 0.889648f, -0.00390625f, + -0.445312f, 0.804688f, -0.0263672f, -0.417969f, 0.806641f, + 0.0410156f, -0.399414f, 0.914062f, -0.0722656f, -0.386719f, + 0.890625f, -0.0615234f, -0.40625f, 0.928711f, 0.0253906f, + -0.118164f, 0.943359f, -0.000976562f, -0.398438f, 0.811523f, + -0.0605469f, -0.234375f, 0.879883f, 0.198242f, -0.509766f, + 0.958008f, 0.0361328f, -0.328125f, 0.938477f, -0.00976562f, + -0.429688f, 0.916016f, -0.0185547f, -0.266602f, 0.898438f, + -0.0380859f, -0.450195f, 0.870117f, 0.162109f, -0.210938f, + 0.899414f, 0.117188f, -0.517578f, 0.756836f, -0.0820312f, + -0.361328f, 0.868164f, -0.0576172f, -1.29883f, 0.515625f, + -0.00195312f, -1.13281f, 0.628906f, 0.00390625f, -0.103516f, + 0.485352f, -0.046875f, -0.922852f, 0.412109f, -0.108398f, + -0.898438f, 0.446289f, -0.111328f, -0.925781f, 0.375977f, + -0.125977f, -0.825195f, 0.446289f, -0.0966797f, -0.958008f, + 0.389648f, -0.0810547f, -1.00781f, 0.532227f, -0.104492f, + -1.0791f, 0.459961f, -0.138672f, -0.941406f, 0.509766f, + -0.107422f, -1.14062f, 0.447266f, -0.195312f, -0.867188f, + 0.474609f, -0.233398f, -0.751953f, 0.612305f, -0.126953f, + -0.661133f, 0.702148f, -0.199219f, -0.260742f, 0.856445f, + -0.0292969f, -0.743164f, 0.921875f, -0.0371094f, -0.293945f, + 0.902344f, -0.103516f, -0.416016f, 0.955078f, -0.00488281f, + -0.232422f, 0.951172f, -0.0498047f, -0.331055f, 0.871094f, + 0.00390625f, -0.186523f, 0.905273f, 0.0566406f, -0.249023f, + 0.677734f, 0.0253906f, 0.145508f, 0.826172f, 0.251953f, + -0.428711f, 0.764648f, 0.488281f, -0.265625f, 0.886719f, + 0.256836f, -0.408203f, 0.744141f, 0.689453f, -0.611328f, + 0.755859f, 0.431641f, -0.525391f, 0.588867f, 0.637695f, + -0.750977f, 0.578125f, 0.568359f, -0.540039f, 0.512695f, + 0.530273f, -0.722656f, 0.498047f, 0.526367f, -0.788086f, + 0.647461f, 0.522461f, -0.862305f, 0.567383f, 0.422852f, + -0.765625f, 0.648438f, 0.405273f, -0.938477f, 0.583008f, + 0.272461f, -1.15137f, 0.481445f, 0.00585938f, -0.788086f, + 0.454102f, -0.0615234f, -0.885742f, 0.306641f, -0.333984f, + -0.678711f, 0.322266f, -0.288086f, -0.615234f, 0.220703f, + -0.476562f, -0.748047f, 0.223633f, -0.396484f, -0.729492f, + 0.235352f, -0.510742f, -0.806641f, 0.227539f, -0.476562f, + -0.665039f, 0.275391f, -0.47168f, -0.938477f, 0.345703f, + -0.369141f, -0.709961f, 0.482422f, -0.393555f, -0.380859f, + 0.759766f, -0.143555f, -0.529297f, 0.956055f, -0.0185547f, + -0.12207f, 1.15527f, 0.0380859f, -0.529297f, 1.04102f, + 0.203125f, -0.0283203f, 1.11719f, 0.0888672f, -0.258789f, + 1.02734f, 0.297852f, -0.0244141f, 1.03223f, 0.211914f, + -0.0859375f, 0.798828f, 0.216797f, 0.19043f, 0.891602f, + 0.256836f, -0.102539f, 0.662109f, 0.263672f, 0.208984f, + 0.810547f, 0.380859f, -0.235352f, 0.707031f, 0.507812f, + -0.0800781f, 0.902344f, 0.470703f, -0.301758f, 0.577148f, + 0.674805f, -0.500977f, 0.748047f, 0.472656f, -0.493164f, + 0.478516f, 0.611328f, -1.04395f, 0.491211f, 0.651367f, + -0.581055f, 0.25293f, 0.325195f, -0.950195f, 0.224609f, + 0.404297f, -1.04883f, 0.116211f, -0.00292969f, -0.980469f, + 0.0566406f, 0.0195312f, -0.821289f, 0.0166016f, -0.141602f, + -0.959961f, -0.0322266f, -0.158203f, -0.837891f, 0.119141f, + -0.224609f, -1.00781f, 0.09375f, -0.151367f, -1.00684f, + 0.248047f, -0.238281f, -0.973633f, 0.271484f, -0.324219f, + -0.942383f, 0.443359f, -0.298828f, -0.845703f, 0.581055f, + -0.291992f, -0.700195f, 0.65918f, -0.319336f, -0.262695f, + 0.818359f, -0.286133f, -0.579102f, 0.827148f, -0.272461f, + -0.0908203f, 0.935547f, -0.233398f, -0.374023f, 0.920898f, + -0.137695f, 0.000976562f, 0.964844f, -0.12793f, -0.285156f, + 0.880859f, -0.0244141f, -0.0830078f, 0.930664f, 0.00976562f, + -0.15332f, 0.731445f, 0.172852f, 0.0380859f, 0.876953f, + 0.264648f, -0.194336f, 0.601562f, 0.613281f, -0.132812f, + 0.803711f, 0.53418f, -0.268555f, 0.933594f, 0.899414f, + -0.332031f, 0.923828f, 0.521484f, -0.425781f, 0.972656f, + 0.959961f, -0.506836f, 0.797852f, 0.506836f, -0.125977f, + 0.740234f, 0.756836f, -0.262695f, 0.783203f, 0.691406f, + -0.422852f, 0.474609f, 0.459961f, 0.00390625f, 0.683594f, + 0.941406f, -0.0625f, 0.0810547f, 1.06934f, 0.0625f, + 0.546875f, 0.967773f, 0.0351562f, 0.202148f, 1.32422f, + -0.148438f, 0.269531f, 0.818359f, -0.3125f, 0.0742188f, + 1.23633f, -0.188477f, -0.0263672f, 0.713867f, -0.139648f, + -0.230469f, 0.8125f, -0.134766f, -0.246094f, 0.734375f, + -0.09375f, -0.22168f, 1.17188f, -0.158203f, -0.209961f, + 1.09766f, -0.141602f, 0.00976562f, 0.991211f, -0.238281f, + 0.0341797f, 0.979492f, -0.207031f, -0.0166016f, 1.00293f, + -0.228516f, 0.0527344f, 1.28711f, -0.167969f, 0.164062f, + 0.925781f, -0.255859f, 0.170898f, 0.956055f, -0.256836f, + 0.191406f, 0.936523f, -0.145508f, 0.205078f, 0.904297f, + -0.257812f, 0.117188f, 0.870117f, -0.188477f, 0.166992f, + 1.02441f, -0.288086f, 0.163086f, 0.938477f, -0.262695f, + 0.138672f, 0.947266f, -0.219727f, 0.0947266f, 0.992188f, + -0.0732422f, 0.116211f, 1.00293f, -0.203125f, 0.0205078f, + 0.933594f, -0.235352f, -0.0126953f, 0.844727f, -0.0693359f, + 0.119141f, 1.00195f, -0.110352f, 0.135742f, 1.00391f, + -0.101562f, 0.0546875f, 1.06543f, -0.18457f, 0.0507812f, + 0.933594f, -0.112305f, 0.00976562f, 0.973633f, -0.193359f, + -0.0185547f, 0.885742f, -0.279297f, -0.0107422f, 1.02344f, + -0.078125f, -0.0107422f, 1.0127f, 0.140625f, -0.142578f, + 0.994141f, -0.132812f, -0.145508f, 0.90918f, -0.000976562f, + -0.22168f, 1.0498f, -0.148438f, -0.185547f, 1.2207f, + -0.172852f, -0.196289f, 1.0957f, -0.183594f, -0.0390625f, + 1.34863f, -0.21875f, -0.745117f, 0.952148f, 0.0126953f, + -0.196289f, 1.29492f, -0.150391f, -0.768555f, 0.853516f, + -0.163086f, -0.25f, 0.358398f, -0.0507812f, -0.80957f, + 0.139648f, 0.125f, -0.790039f, -0.257812f, 0.175781f, + -0.795898f, -0.135742f, 0.00585938f, -0.841797f, -0.279297f, + 0.0419922f, -0.708984f, 0.0175781f, -0.0957031f, -0.75f, + -0.204102f, 0.0419922f, -0.78125f, 0.0322266f, -0.125f, + -0.787109f, -0.0380859f, -0.0683594f, -1.06641f, 0.0947266f, + -0.238281f, -1.02148f, 0.117188f, -0.176758f, -1.77539f, + 0.0117188f, -0.31543f, -1.80566f, -0.0625f, -0.273438f, + -0.764648f, 0.143555f, -0.21875f, -0.746094f, 0.162109f, + -0.0351562f, -0.858398f, 0.186523f, -0.250977f, -0.918945f, + 0.0458984f, 0.135742f, -0.988281f, 0.241211f, -0.192383f, + -0.963867f, 0.277344f, -0.129883f, -0.994141f, 0.22168f, + -0.169922f, -0.96582f, 0.290039f, -0.217773f, -0.990234f, + 0.185547f, -0.152344f, -0.978516f, 0.169922f, -0.0361328f, + -0.912109f, 0.119141f, -0.352539f, -0.838867f, 0.183594f, + -0.0380859f, -0.753906f, 0.274414f, -0.575195f, -0.770508f, + 0.192383f, -0.482422f, -0.904297f, -0.0234375f, -0.498047f, + -0.817383f, 0.0527344f, -0.277344f, -0.428711f, 0.114258f, + -0.634766f, -0.427734f, -0.0429688f, -0.405273f, -0.318359f, + 0.118164f, -0.870117f, -0.193359f, 0.171875f, -0.938477f, + -0.1875f, 0.208008f, -1.04688f, -0.246094f, 0.0849609f, + -1.72461f, -0.353516f, 0.234375f, -1.05859f, -0.304688f, + 0.151367f, -1.38672f, -0.663086f, 0.242188f, -0.939453f, + -0.481445f, 0.189453f, -0.87793f, -0.831055f, 0.358398f, + -0.555664f, -0.621094f, 0.444336f, -0.287109f, -0.802734f, + 0.367188f, -0.25293f, -0.753906f, 0.413086f, 0.0126953f, + -1.0127f, 0.335938f, -0.250977f, -0.942383f, 0.563477f, + 0.000976562f, -1.33691f, 0.138672f, -0.365234f, -0.996094f, + 0.542969f, -0.0400391f, -1.44434f, 0.239258f, -0.655273f, + -0.625977f, 0.313477f, -0.444336f, -0.589844f, -0.106445f, + -0.217773f, 0.00585938f, -0.760742f, -0.219727f, 0.0654297f, + -0.626953f, -0.0439453f, 0.0732422f, -1.22168f, 0.0126953f, + 0.210938f, -0.754883f, -0.0839844f, 0.161133f, -0.980469f, + -0.124023f, 0.141602f, -0.828125f, -0.199219f, 0.152344f, + -0.80957f, -0.230469f, 0.231445f, -0.865234f, -0.259766f, + 0.232422f, -0.892578f, -0.305664f, 0.323242f, -0.87793f, + -0.294922f, 0.274414f, -1.0791f, -0.435547f, 0.222656f, + -0.863281f, -0.375f, 0.219727f, -1.0166f, -0.525391f, + 0.0341797f, -0.834961f, -0.454102f, 0.0371094f, -0.984375f, + -0.486328f, -0.135742f, -0.700195f, -0.339844f, -0.0078125f, + -1.20508f, -0.665039f, -0.791016f, 0.00390625f, -0.277344f, + 0.0136719f, -0.492188f, -0.779297f, -1.49316f, 0.0957031f, + -0.179688f, -0.587891f, 0.665039f, 0.398438f, -0.980469f, + 0.428711f, 0.254883f, -0.828125f, 0.724609f, 0.663086f, + -0.90625f, 0.555664f, 0.0791016f, -0.837891f, 0.591797f, + 0.257812f, -0.806641f, 0.609375f, 0.0458984f, -0.779297f, + 0.529297f, 0.00292969f, -0.829102f, 0.640625f, 0.0371094f, + -0.797852f, 0.583008f, 0.208984f, -0.864258f, 0.583984f, + -0.0615234f, -0.758789f, 0.72168f, 0.0947266f, -0.921875f, + 0.605469f, -0.264648f, -0.75293f, 0.701172f, 0.107422f, + -0.735352f, 0.44043f, -0.527344f, -0.398438f, 0.46875f, + -0.421875f, -0.424805f, 0.0810547f, -0.754883f, -0.241211f, + -0.107422f, -1.13574f, -0.410156f, -0.0400391f, -0.942383f, + -0.454102f, -0.12207f, -1.24902f, -0.509766f, -0.393555f, + -0.959961f, -0.511719f, -0.381836f, -1.04883f, -0.924805f, + -0.756836f, -1.17969f, -0.521484f, -0.105469f, -1.16504f, + -0.767578f, -0.477539f, -0.401367f, -0.0341797f, -0.341797f, + 0.0507812f, 0.389648f, -0.507812f, 0.186523f, 0.438477f, + -1.33594f, 0.625977f, 0.518555f, -0.671875f, 0.182617f, + 0.432617f, -1.18359f, 0.132812f, 0.414062f, -0.782227f, + 0.0615234f, 0.401367f, -1.30176f, -0.0683594f, -0.100586f, + -0.586914f, 0.0302734f, 0.191406f, -0.983398f, -0.0273438f, + -0.735352f, -0.224609f, -0.342773f, -0.241211f, -0.566406f, + 0.015625f, -1.1084f, -0.00976562f, -0.652344f, -0.75293f, + 0.239258f, -0.449219f, -1.08789f, 0.107422f, -0.572266f, + -0.887695f, 0.407227f, -0.423828f, -0.919922f, 0.173828f, + -0.705078f, -0.825195f, 0.411133f, -0.484375f, -0.799805f, + 0.237305f, -0.776367f, -0.745117f, 0.459961f, -0.819336f, + -0.749023f, 0.208008f, -0.788086f, -0.716797f, 0.226562f, + -0.795898f, -0.72168f, 0.123047f, -0.790039f, -0.705078f, + 0.101562f, -0.720703f, -0.745117f, -0.0517578f, -0.771484f, + -0.701172f, -0.0175781f, -0.758789f, -0.765625f, -0.0917969f, + -0.745117f, -0.751953f, -0.149414f, -0.6875f, -0.660156f, + -0.0166016f, -0.782227f, -0.592773f, -0.0205078f, -0.726562f, + -0.376953f, 0.119141f, -0.599609f, -0.371094f, 0.0107422f, + -0.736328f, -0.325195f, 0.0771484f, -0.768555f, -0.388672f, + -0.0273438f, -0.750977f, -0.477539f, 0.107422f, -0.919922f, + -0.514648f, 0.125f, -0.961914f, -0.37793f, 0.0136719f, + -0.981445f, -0.447266f, -0.0107422f, -0.823242f, -0.303711f, + 0.0986328f, -1.00684f, -0.366211f, 0.0986328f, -1.14551f, + -0.239258f, 0.140625f, -0.894531f, -0.297852f, 0.0849609f, + -0.949219f, -0.341797f, 0.131836f, -0.966797f, -0.380859f, + 0.0947266f, -0.75293f, -0.391602f, 0.0839844f, -0.908203f, + -0.40625f, 0.161133f, -0.860352f, -0.452148f, 0.1875f, + -0.950195f, -0.496094f, 0.200195f, -0.828125f, -0.581055f, + 0.0771484f, -0.93457f, -0.607422f, 0.0996094f, -0.863281f, + -0.59375f, 0.0927734f, -0.802734f, -0.604492f, 0.0947266f, + -0.807617f, -0.722656f, 0.101562f, -0.844727f, -0.711914f, + 0.149414f, -1.03125f, -0.77832f, 0.125977f, -0.78418f, + -0.740234f, 0.121094f, -0.891602f, -0.808594f, 0.164062f, + -0.650391f, -0.80957f, 0.0888672f, -0.416992f, -0.866211f, + 0.155273f, -0.382812f, -0.880859f, 0.0849609f, -0.264648f, + -0.775391f, 0.229492f, -0.389648f, -0.814453f, 0.0664062f, + -0.226562f, -0.625f, 0.414062f, -0.274414f, -0.681641f, + 0.0292969f, -0.0478516f, -0.711914f, 0.794922f, -0.388672f, + -0.584961f, 0.368164f, -0.257812f, -0.545898f, 1.09277f, + -0.277344f, -0.125977f, 0.822266f, -0.365234f, -0.467773f, + 0.714844f, -0.413086f, -0.136719f, 1.57227f, -0.0947266f, + -0.223633f, 0.817383f, -0.0556641f, -0.0322266f, 1.18945f, + -0.191406f, -0.498047f, 0.991211f, -0.231445f, -0.246094f, + 0.8125f, -0.239258f, -0.755859f, 0.853516f, -0.228516f, + -0.821289f, 0.503906f, -0.121094f, -0.795898f, 0.523438f, + -0.220703f, -0.773438f, 0.517578f, -0.274414f, -0.757812f, + 0.539062f, -0.222656f, -0.770508f, 0.396484f, -0.115234f, + -1.2334f, 0.485352f, -0.217773f, -0.94043f, 1.01758f, + -0.202148f, -0.605469f, 0.0546875f, 0.0957031f, -0.639648f, + -0.661133f, 0.245117f, -0.750977f, 0.0615234f, -0.726562f, + -0.879883f, -0.432617f, -1.05859f, -1.29688f, 0.00488281f, + 0.193359f, -0.939453f, 0.209961f, -0.209961f, -0.793945f, + 0.251953f, 0.722656f, -0.447266f, 0.0615234f, 0.855469f, + -0.454102f, -0.0126953f, 0.0527344f, -0.342773f, 0.154297f, + 1.3877f, -0.65918f, 0.133789f, 0.0576172f, -0.233398f, + -0.12207f, 0.46582f, -1.09961f, 0.438477f, -0.641602f, + -0.861328f, 0.197266f, -1.99902f, -0.932617f, 0.234375f, + 0.389648f, -0.792969f, -0.0908203f, 1.66797f, -1.0459f, + 0.0107422f, -0.543945f, -0.80957f, 0.206055f, -0.27832f, + -0.915039f, 0.104492f, -0.301758f, -0.891602f, 0.0556641f, + -0.681641f, -0.901367f, 0.0498047f, -0.461914f, -0.927734f, + -0.0390625f, -0.229492f, -1.04004f, 0.0869141f, -0.435547f, + -1.02148f, 0.0947266f, -0.527344f, -0.979492f, 0.0751953f, + 0.266602f, -0.786133f, -0.0224609f, -0.0947266f, -0.702148f, + -0.00683594f, -0.316406f, -0.698242f, -0.317383f, 1.92578f, + -1.0498f, 0.0273438f, -1.14258f, -0.226562f, 0.233398f, + -0.995117f, -0.9375f, 0.0146484f, -0.223633f, -0.49707f, + -0.0078125f, -1.95703f, -0.847656f, 0.157227f, 0.129883f, + -0.459961f, -0.114258f, 2.0f, -1.13574f, -0.0839844f, + -0.0878906f, -0.783203f, 0.131836f, -0.803711f, -0.90332f, + 0.208984f, -0.365234f, -0.97168f, -0.0322266f, 0.186523f, + -0.924805f, 0.00292969f, -0.272461f, -0.890625f, 0.015625f, + -0.333008f, -0.932617f, 0.180664f, -0.459961f, -0.90918f, + 0.240234f, -0.625977f, -1.1582f, 0.0996094f, -0.170898f, + -1.08887f, -0.00976562f, -0.849609f, -0.430664f, 0.139648f, + -0.308594f, -0.572266f, -0.722656f, 1.83496f, -1.00977f, + 0.387695f, 0.487305f, -0.268555f, 0.0712891f, -0.0136719f, + -1.5332f, 0.290039f, -0.0351562f, -0.861328f, 1.98535f, + -1.16602f, -0.602539f, 0.441406f, 0.175781f, -0.605469f, + -0.831055f, 0.686523f, -0.984375f, 0.494141f, -0.489258f, + -0.895508f, 0.371094f, -0.665039f, -1.14258f, -0.214844f, + -0.140625f, -1.06348f, -0.0996094f, 0.255859f, -0.874023f, + 0.193359f, -0.0947266f, -0.959961f, -0.0966797f, 0.00195312f, + -0.996094f, -0.0117188f, -0.174805f, -0.962891f, 0.106445f, + -0.162109f, -1.04297f, -0.0283203f, -0.306641f, -1.06738f, + -0.0224609f, -0.129883f, -1.03223f, 0.129883f, 0.195312f, + -1.08789f, -0.130859f, 0.649414f, -0.572266f, -0.0136719f, + -0.793945f, -0.382812f, 0.0f, -1.08301f, -0.78125f, + -0.0224609f, -0.339844f, -0.629883f, -0.0947266f, -1.83789f, + -1.01562f, 0.046875f, 0.223633f, -0.808594f, 0.0957031f, + 1.09766f, -0.756836f, -0.0488281f, 0.157227f, -0.59082f, + -0.103516f, 0.929688f, -0.816406f, -0.0322266f, -0.426758f, + -0.868164f, -0.209961f, -1.99902f, -0.986328f, -0.00878906f, + -0.365234f, -0.980469f, 0.0439453f, 0.59375f, -0.994141f, + 0.0253906f, 0.0371094f, -0.970703f, -0.0273438f, -0.120117f, + -0.935547f, 0.00195312f, -0.235352f, -0.952148f, -0.0263672f, + -0.194336f, -0.917969f, -0.0195312f, -0.261719f, -0.928711f, + -0.0234375f, -0.219727f, -0.945312f, 0.0107422f, -0.228516f, + -0.938477f, 0.00683594f, -0.178711f, -0.791016f, 0.03125f, + -0.255859f, -0.789062f, 0.0f, -0.141602f, -0.789062f, + 0.232422f, -0.285156f, -0.788086f, 0.228516f, -0.28125f, + -1.0f, 0.258789f, -0.277344f, -0.999023f, 0.28125f, + -0.25293f, -1.06152f, 0.046875f, -0.421875f, -1.07715f, + 0.0390625f, -0.224609f, -0.923828f, -0.0205078f, -0.335938f, + -0.984375f, -0.0966797f, -0.34668f, -0.990234f, -0.191406f, + -0.301758f, -1.03613f, -0.241211f, -0.37207f, -0.975586f, + -0.267578f, -0.460938f, -1.00977f, -0.320312f, -0.382812f, + -0.913086f, -0.257812f, -0.457031f, -0.925781f, -0.256836f, + -0.34668f, -0.889648f, -0.237305f, -0.393555f, -0.897461f, + -0.239258f, -0.429688f, -0.844727f, -0.21875f, -0.428711f, + -0.87207f, -0.203125f, -0.368164f, -0.84668f, -0.101562f, + -0.423828f, -0.875977f, -0.165039f, -0.363281f, -0.884766f, + -0.0625f, -0.473633f, -0.90332f, -0.078125f, -0.138672f, + -0.918945f, -0.198242f, -0.25f, -0.928711f, -0.138672f, + -0.267578f, -1.08203f, 0.00488281f, -0.575195f, -1.125f, + -0.0332031f, -0.4375f, -0.924805f, 0.078125f, -0.305664f, + -0.93457f, -0.0166016f, -0.475586f, -0.94043f, -0.00488281f, + -0.533203f, -0.956055f, 0.00292969f, -0.391602f, -1.00293f, + 0.0361328f, -0.711914f, -1.0166f, 0.0332031f, -0.448242f, + -0.806641f, -0.21582f, -0.556641f, -0.759766f, -0.0214844f, + -0.626953f, -0.700195f, -0.263672f, -0.308594f, -0.608398f, + -0.236328f, -0.253906f, -0.616211f, -0.378906f, 0.224609f, + -0.498047f, -0.399414f, 0.206055f, -0.516602f, -0.228516f, + 0.743164f, -0.174805f, -0.125f, 0.760742f, -0.0214844f, + -0.135742f, 0.966797f, 0.240234f, 0.0332031f, 1.01855f, + 0.105469f, 0.15332f, 0.950195f, 0.240234f, 0.0732422f, + 1.16895f, 0.245117f, 0.206055f, 0.952148f, 0.273438f, + -0.0390625f, 1.2793f, 0.404297f, 0.303711f, 0.720703f, + 0.369141f, 0.0966797f, 0.918945f, 0.329102f, 0.0390625f, + 0.991211f, 0.397461f, -0.124023f, 0.866211f, 0.210938f, + 0.130859f, 1.08789f, 0.317383f, 0.0537109f, 0.858398f, + 0.245117f, 0.0732422f, 0.741211f, 0.419922f, 0.0302734f, + 0.681641f, 0.485352f, -0.0214844f, 0.641602f, 0.520508f, + -0.129883f, 0.839844f, 0.490234f, 0.00390625f, 0.676758f, + 0.581055f, -0.0146484f, 0.692383f, 0.432617f, -0.0371094f, + 0.807617f, 0.664062f, 0.255859f, 0.216797f, 1.22559f, + 0.0195312f, 1.22168f, 1.2793f, -0.405273f, 1.72559f, + 0.708984f, -0.209961f, 0.579102f, 0.821289f, 0.0380859f, + 0.605469f, 0.80957f, 0.147461f, 0.419922f, 0.869141f, + 0.0390625f, 0.5625f, 0.786133f, 0.0654297f, 0.594727f, + 0.879883f, 0.0166016f, 0.480469f, 0.835938f, 0.00195312f, + 0.414062f, 0.899414f, -0.03125f, 0.344727f, 0.889648f, + 0.0185547f, 0.236328f, 0.932617f, -0.00585938f, 0.255859f, + 0.910156f, 0.0898438f, 0.262695f, 0.945312f, 0.0126953f, + 0.279297f, 0.860352f, 0.0507812f, 0.322266f, 0.913086f, + 0.00195312f, 0.296875f, 0.875977f, 0.0078125f, 0.373047f, + 0.922852f, -0.0244141f, 0.267578f, 0.884766f, 0.0117188f, + 0.347656f, 0.926758f, -0.0371094f, 0.266602f, 0.894531f, + -0.00683594f, 0.345703f, 0.926758f, -0.0478516f, 0.269531f, + 0.887695f, 0.0146484f, 0.360352f, 0.927734f, -0.03125f, + 0.272461f +}; const size_t kAccelerometerFullyOpenTestDataLength = - ARRAY_SIZE(kAccelerometerFullyOpenTestData); + ARRAY_SIZE(kAccelerometerFullyOpenTestData); -- cgit v1.2.1 From b4a162edcfb3992fe9faa92c62cee96be23493c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:10 -0600 Subject: chip/mec1322/port80.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I490e5c5816bb94cf896fc66faf35793501670605 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729320 Reviewed-by: Jeremy Bettis --- chip/mec1322/port80.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c index e2f02c81e5..dc6f917ee3 100644 --- a/chip/mec1322/port80.c +++ b/chip/mec1322/port80.c @@ -17,9 +17,8 @@ #define POLL_PERIOD_USEC 1000 /* After 30 seconds of no port 80 data, disable the timer interrupt. */ #define INTERRUPT_DISABLE_TIMEOUT_SEC 30 -#define INTERRUPT_DISABLE_IDLE_COUNT (INTERRUPT_DISABLE_TIMEOUT_SEC \ - * 1000000 \ - / POLL_PERIOD_USEC) +#define INTERRUPT_DISABLE_IDLE_COUNT \ + (INTERRUPT_DISABLE_TIMEOUT_SEC * 1000000 / POLL_PERIOD_USEC) /* Count the number of consecutive interrupts with no port 80 data. */ static int idle_count; -- cgit v1.2.1 From ebf1ae04fd4ad3231cca2514e67bfaecfbd2a6b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:28 -0600 Subject: zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1af664a79da6d78b21f695acc297be3b1cb24586 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730919 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h index 9bee8af826..85b4ffe2ff 100644 --- a/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h +++ b/zephyr/subsys/ap_pwrseq/include/ap_power_host_sleep.h @@ -22,8 +22,8 @@ void ap_power_set_active_wake_mask(void); * * @return 0 for success; -EINVAL if power state is not S3/S5/S0ix */ -int ap_power_get_lazy_wake_mask( - enum power_states_ndsx state, host_event_t *mask); +int ap_power_get_lazy_wake_mask(enum power_states_ndsx state, + host_event_t *mask); #if CONFIG_AP_PWRSEQ_S0IX /* For S0ix path, flag to notify sleep change */ -- cgit v1.2.1 From 3b08da5561d84b43b474b971cabb5a8357a39e20 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:59 -0600 Subject: chip/mec1322/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cc29c215014f6e151e349d36128c38caf31341d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729330 Reviewed-by: Jeremy Bettis --- chip/mec1322/i2c.c | 84 +++++++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index c282714265..58215adae7 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -16,7 +16,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_CLOCK 16000000 /* 16 MHz */ @@ -36,7 +36,7 @@ #define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_IDLE BIT(29) /* i2c bus is idle */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Maximum transfer of a SMBUS block transfer */ @@ -68,10 +68,8 @@ static struct { /* Map port number to port name in datasheet, for debug prints. */ static const char *i2c_port_names[MEC1322_I2C_PORT_COUNT] = { - [MEC1322_I2C0_0] = "0_0", - [MEC1322_I2C0_1] = "0_1", - [MEC1322_I2C1] = "1", - [MEC1322_I2C2] = "2", + [MEC1322_I2C0_0] = "0_0", [MEC1322_I2C0_1] = "0_1", + [MEC1322_I2C1] = "1", [MEC1322_I2C2] = "2", [MEC1322_I2C3] = "3", }; @@ -114,8 +112,8 @@ static void configure_controller(int controller, int kbps) MEC1322_I2C_CTRL(controller) = CTRL_PIN; MEC1322_I2C_OWN_ADDR(controller) = 0x0; configure_controller_speed(controller, kbps); - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_ACK | CTRL_ENI; + MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK | + CTRL_ENI; MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ /* Enable interrupt */ @@ -211,16 +209,15 @@ static void select_port(int port) MEC1322_I2C_CONFIG(controller) &= ~0xf; MEC1322_I2C_CONFIG(controller) |= port_sel; - } static inline int get_line_level(int controller) { int ret, ctrl; /* - * We need to enable BB (Bit Bang) mode in order to read line level - * properly, othervise line levels return always idle (0x60). - */ + * We need to enable BB (Bit Bang) mode in order to read line level + * properly, othervise line levels return always idle (0x60). + */ ctrl = MEC1322_I2C_BB_CTRL(controller); MEC1322_I2C_BB_CTRL(controller) |= 1; ret = (MEC1322_I2C_BB_CTRL(controller) >> 5) & 0x3; @@ -236,10 +233,8 @@ static inline void push_in_buf(uint8_t **in, uint8_t val, int skip) } } -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { int i; int controller; @@ -263,8 +258,7 @@ int chip_i2c_xfer(const int port, if (send_start && cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED && (((reg & (STS_BER | STS_LAB)) || !(reg & STS_NBB)) || - (get_line_level(controller) - != I2C_LINE_IDLE))) { + (get_line_level(controller) != I2C_LINE_IDLE))) { CPRINTS("i2c%s bad status 0x%02x, SCL=%d, SDA=%d", i2c_port_names[port], reg, get_line_level(controller) & I2C_LINE_SCL_HIGH, @@ -287,8 +281,7 @@ int chip_i2c_xfer(const int port, if (out_size) { if (send_start) { MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_STRIP_FLAGS(addr_flags) - << 1); + (uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1); /* Clock out the slave address, sending START bit */ MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | @@ -326,24 +319,20 @@ int chip_i2c_xfer(const int port, /* Repeated start case */ if (cdata[controller].transaction_state == I2C_TRANSACTION_OPEN) - MEC1322_I2C_CTRL(controller) = CTRL_ESO | - CTRL_STA | - CTRL_ACK | - CTRL_ENI; + MEC1322_I2C_CTRL(controller) = + CTRL_ESO | CTRL_STA | CTRL_ACK | + CTRL_ENI; MEC1322_I2C_DATA(controller) = - (uint8_t)(I2C_STRIP_FLAGS(addr_flags) - << 1) - | 0x01; + (uint8_t)(I2C_STRIP_FLAGS(addr_flags) << 1) | + 0x01; /* New transaction case, clock out slave address. */ if (cdata[controller].transaction_state == I2C_TRANSACTION_STOPPED) - MEC1322_I2C_CTRL(controller) = CTRL_ESO | - CTRL_STA | - CTRL_ACK | - CTRL_ENI | - CTRL_PIN; + MEC1322_I2C_CTRL(controller) = + CTRL_ESO | CTRL_STA | CTRL_ACK | + CTRL_ENI | CTRL_PIN; cdata[controller].transaction_state = I2C_TRANSACTION_OPEN; @@ -379,8 +368,8 @@ int chip_i2c_xfer(const int port, goto err_chip_i2c_xfer; /* Send STOP */ - MEC1322_I2C_CTRL(controller) = - CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_STO; + MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | + CTRL_ACK | CTRL_STO; cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; @@ -403,8 +392,8 @@ int chip_i2c_xfer(const int port, return EC_SUCCESS; err_chip_i2c_xfer: /* Send STOP and return error */ - MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | - CTRL_STO | CTRL_ACK; + MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_STO | + CTRL_ACK; cdata[controller].transaction_state = I2C_TRANSACTION_STOPPED; if (ret_done == STS_LRB) return EC_ERROR_BUSY; @@ -417,8 +406,7 @@ err_chip_i2c_xfer: */ reset_controller(controller); return EC_ERROR_TIMEOUT; - } - else + } else return EC_ERROR_UNKNOWN; } @@ -520,10 +508,22 @@ static void handle_interrupt(int controller) task_set_event(id, TASK_EVENT_I2C_IDLE); } -static void i2c0_interrupt(void) { handle_interrupt(0); } -static void i2c1_interrupt(void) { handle_interrupt(1); } -static void i2c2_interrupt(void) { handle_interrupt(2); } -static void i2c3_interrupt(void) { handle_interrupt(3); } +static void i2c0_interrupt(void) +{ + handle_interrupt(0); +} +static void i2c1_interrupt(void) +{ + handle_interrupt(1); +} +static void i2c2_interrupt(void) +{ + handle_interrupt(2); +} +static void i2c3_interrupt(void) +{ + handle_interrupt(3); +} DECLARE_IRQ(MEC1322_IRQ_I2C_0, i2c0_interrupt, 2); DECLARE_IRQ(MEC1322_IRQ_I2C_1, i2c1_interrupt, 2); -- cgit v1.2.1 From ff170c675dd3339f2e351e8bbc4af41da5612608 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:32 -0600 Subject: board/kuldax/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0f921a977af0b8cec3de2d91bb5d9dbd5b75a20 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728546 Reviewed-by: Jeremy Bettis --- board/kuldax/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kuldax/fw_config.c b/board/kuldax/fw_config.c index a5857ef48f..5b987f7ebc 100644 --- a/board/kuldax/fw_config.c +++ b/board/kuldax/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union brask_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From d5741043cfa2641ebe945142af82d97c08168d56 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:57 -0600 Subject: board/prism/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic1381bcbfd28bd5b7bdec52d420cb219f9420112 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727766 Reviewed-by: Jeremy Bettis --- board/prism/board.h | 66 ++++++++++++++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/board/prism/board.h b/board/prism/board.h index 1734624752..ec77c5e7b0 100644 --- a/board/prism/board.h +++ b/board/prism/board.h @@ -24,15 +24,15 @@ #ifdef SECTION_IS_RW #define CONFIG_KEYBOARD_BACKLIGHT #define CONFIG_RGB_KEYBOARD -#define GPIO_RGBKBD_SDB_L GPIO_SDB_L -#define GPIO_RGBKBD_POWER GPIO_L_POWER +#define GPIO_RGBKBD_SDB_L GPIO_SDB_L +#define GPIO_RGBKBD_POWER GPIO_L_POWER #define CONFIG_LED_DRIVER_IS31FL3743B -#define SPI_RGB0_DEVICE_ID 0 -#define SPI_RGB1_DEVICE_ID 1 -#define RGB_GRID0_COL 11 -#define RGB_GRID0_ROW 6 -#define RGB_GRID1_COL 11 -#define RGB_GRID1_ROW 6 +#define SPI_RGB0_DEVICE_ID 0 +#define SPI_RGB1_DEVICE_ID 1 +#define RGB_GRID0_COL 11 +#define RGB_GRID0_ROW 6 +#define RGB_GRID1_COL 11 +#define RGB_GRID1_ROW 6 /* Enable control of SPI over USB */ #define CONFIG_SPI_CONTROLLER @@ -74,27 +74,27 @@ /* Do not use a dedicated PSTATE bank */ #undef CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (44*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (44 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* The UART console is on USART1 (PA9/PA10) */ #undef CONFIG_UART_CONSOLE @@ -123,21 +123,21 @@ #define DEFAULT_SERIALNO "" /* USB interface indexes (use define rather than enum to expand them) */ -#undef CONFIG_HOSTCMD_EVENTS -#define USB_IFACE_UPDATE 0 +#undef CONFIG_HOSTCMD_EVENTS +#define USB_IFACE_UPDATE 0 #ifdef SECTION_IS_RW #define CONFIG_HOST_INTERFACE_USB -#define USB_IFACE_HOSTCMD 1 -#define USB_IFACE_COUNT 2 +#define USB_IFACE_HOSTCMD 1 +#define USB_IFACE_COUNT 2 #else -#define USB_IFACE_COUNT 1 +#define USB_IFACE_COUNT 1 #endif /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_UPDATE 1 -#define USB_EP_HOSTCMD 2 -#define USB_EP_COUNT 3 +#define USB_EP_CONTROL 0 +#define USB_EP_UPDATE 1 +#define USB_EP_HOSTCMD 2 +#define USB_EP_COUNT 3 /* Optional features */ #define CONFIG_BOARD_PRE_INIT @@ -192,10 +192,10 @@ #endif /* Maximum current to draw. */ -#define MAX_CURRENT_MA 2000 +#define MAX_CURRENT_MA 2000 /* Maximum current/voltage to provide over OTG. */ -#define MAX_OTG_CURRENT_MA 2000 -#define MAX_OTG_VOLTAGE_MV 20000 +#define MAX_OTG_CURRENT_MA 2000 +#define MAX_OTG_VOLTAGE_MV 20000 #ifndef __ASSEMBLER__ -- cgit v1.2.1 From f3e132dc99d5f8425ab994ba291568205b4538fb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:56 -0600 Subject: chip/stm32/clock-f.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I54820530257163f477b94aa6ffae754009990bec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729460 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-f.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/clock-f.h b/chip/stm32/clock-f.h index 4662b043cb..fa06e9c431 100644 --- a/chip/stm32/clock-f.h +++ b/chip/stm32/clock-f.h @@ -100,4 +100,4 @@ int is_host_wake_alarm_expired(timestamp_t ts); /* Set RTC wakeup based on the value saved in host_wake_time */ void restore_host_wake_alarm(void); -#endif /* __CROS_EC_CLOCK_F_H */ +#endif /* __CROS_EC_CLOCK_F_H */ -- cgit v1.2.1 From b351ec5a3da9f20a02b8f582328189d5fae3f918 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:42 -0600 Subject: common/extpower_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91c28ffecc4f14e4aba68d145fbe006d7872b11f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729626 Reviewed-by: Jeremy Bettis --- common/extpower_gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/extpower_gpio.c b/common/extpower_gpio.c index 4cdcb834f8..9bcda2e354 100644 --- a/common/extpower_gpio.c +++ b/common/extpower_gpio.c @@ -31,7 +31,6 @@ static void extpower_deferred(void) debounced_extpower_presence = extpower_presence; extpower_handle_update(extpower_presence); - } DECLARE_DEFERRED(extpower_deferred); @@ -39,7 +38,7 @@ void extpower_interrupt(enum gpio_signal signal) { /* Trigger deferred notification of external power change */ hook_call_deferred(&extpower_deferred_data, - CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC); + CONFIG_EXTPOWER_DEBOUNCE_MS * MSEC); } static void extpower_init(void) -- cgit v1.2.1 From a7f02c52ca77b14305ad785c7a3bf6cf507d61ee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:34 -0600 Subject: include/charger_profile_override.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I25b54c3a757a22c442172cf783e13910a32385aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730226 Reviewed-by: Jeremy Bettis --- include/charger_profile_override.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/charger_profile_override.h b/include/charger_profile_override.h index 091eb11946..a948638c40 100644 --- a/include/charger_profile_override.h +++ b/include/charger_profile_override.h @@ -10,7 +10,7 @@ #include "charge_state_v2.h" -#define TEMPC_TENTHS_OF_DEG(c) ((c) * 10) +#define TEMPC_TENTHS_OF_DEG(c) ((c)*10) #define CHARGER_PROF_TEMP_C_LAST_RANGE 0xFFFF @@ -69,10 +69,11 @@ int charger_profile_override(struct charge_state_data *curr); * <0 An error occurred. The poll time will be shorter than usual. * Too many errors in a row may trigger some corrective action. */ -int charger_profile_override_common(struct charge_state_data *curr, - const struct fast_charge_params *fast_chg_params, - const struct fast_charge_profile **prev_chg_prof_info, - int batt_vtg_max); +int charger_profile_override_common( + struct charge_state_data *curr, + const struct fast_charge_params *fast_chg_params, + const struct fast_charge_profile **prev_chg_prof_info, + int batt_vtg_max); /* * Access to custom profile params through host commands. -- cgit v1.2.1 From 373f8b949c220dc11d97f166c501bb69de477a84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:01 -0600 Subject: board/mushu/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieef035b2b8bf24f1b1403ac793d0bc29d23ee923 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728712 Reviewed-by: Jeremy Bettis --- board/mushu/board.c | 122 ++++++++++++++++++++++------------------------------ 1 file changed, 52 insertions(+), 70 deletions(-) diff --git a/board/mushu/board.c b/board/mushu/board.c index 8e46caa2ed..05ec281a35 100644 --- a/board/mushu/board.c +++ b/board/mushu/board.c @@ -44,8 +44,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO to enable/disable the USB Type-A port. */ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { @@ -111,18 +111,19 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_FAN2] = { .channel = 6, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -224,22 +225,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation * matrix can't be tested properly. This needs to be revisited after EVT to make * sure the rotation matrix for the lid sensor is correct. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -363,14 +360,14 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_1, /* Use MFT id to control fan */ + .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -394,61 +391,48 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, - [MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, + [MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_5V", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_CHARGER] = { - .name = "CHARGER", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1 - }, - [TEMP_5V] = { - .name = "5V", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2 - }, - [TEMP_GPU] = { - .name = "GPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_R19ME4070, - .idx = R19ME4070_LOCAL - }, - [TEMP_F75303_LOCAL] = { - .name = "F75303_Local", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = f75303_get_val, - .idx = F75303_IDX_LOCAL - }, - [TEMP_F75303_GPU] = { - .name = "F75303_GPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = f75303_get_val, - .idx = F75303_IDX_REMOTE1 - }, - [TEMP_F75303_GPU_POWER] = { - .name = "F75303_GPU_Power", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = f75303_get_val, - .idx = F75303_IDX_REMOTE2 - }, + [TEMP_CHARGER] = { .name = "CHARGER", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_5V] = { .name = "5V", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_GPU] = { .name = "GPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_R19ME4070, + .idx = R19ME4070_LOCAL }, + [TEMP_F75303_LOCAL] = { .name = "F75303_Local", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = f75303_get_val, + .idx = F75303_IDX_LOCAL }, + [TEMP_F75303_GPU] = { .name = "F75303_GPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = f75303_get_val, + .idx = F75303_IDX_REMOTE1 }, + [TEMP_F75303_GPU_POWER] = { .name = "F75303_GPU_Power", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = f75303_get_val, + .idx = F75303_IDX_REMOTE2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Hatch Temperature sensors */ /* * TODO(b/124316213): These setting need to be reviewed and set appropriately @@ -458,8 +442,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -478,8 +462,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -495,7 +479,6 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; } __maybe_unused static const struct ec_thermal_config thermal_b = THERMAL_B; - struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT]; static void setup_fans(void) @@ -536,7 +519,6 @@ static void board_gpio_set_pp5000(void) } else if (board_id >= 1) { reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW); } - } static void board_init(void) -- cgit v1.2.1 From 51fa1b1aba348f62e41bf9309e072e9deed1965b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:33 -0600 Subject: zephyr/shim/include/motionsense_sensors.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9be2fba55dfaac4aa3d53346946df30bd5cbca22 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730830 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/motionsense_sensors.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/zephyr/shim/include/motionsense_sensors.h b/zephyr/shim/include/motionsense_sensors.h index f3bd6befe0..85550c7c22 100644 --- a/zephyr/shim/include/motionsense_sensors.h +++ b/zephyr/shim/include/motionsense_sensors.h @@ -14,14 +14,14 @@ extern struct motion_sensor_t motion_sensors_alt[]; /* * Common macros. */ -#define SENSOR_ROT_STD_REF_NAME(id) DT_CAT(ROT_REF_, id) -#define SENSOR_ROT_REF_NODE DT_PATH(motionsense_rotation_ref) +#define SENSOR_ROT_STD_REF_NAME(id) DT_CAT(ROT_REF_, id) +#define SENSOR_ROT_REF_NODE DT_PATH(motionsense_rotation_ref) /* * Declare rotation parameters, since they may be * dynamically selected. */ -#define DECLARE_EXTERN_SENSOR_ROT_REF(id) \ +#define DECLARE_EXTERN_SENSOR_ROT_REF(id) \ extern const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id); #if DT_NODE_EXISTS(SENSOR_ROT_REF_NODE) @@ -45,18 +45,18 @@ int motion_sense_probe(enum sensor_alt_id alt_idx); */ void motion_sensors_check_ssfc(void); -#define ENABLE_ALT_MOTION_SENSOR(alt_id) \ +#define ENABLE_ALT_MOTION_SENSOR(alt_id) \ motion_sensors[SENSOR_ID(DT_PHANDLE(alt_id, alternate_for))] = \ motion_sensors_alt[SENSOR_ID(alt_id)]; /* * Replaces a default motion sensor with an alternate one pointed by nodelabel. */ -#define MOTIONSENSE_ENABLE_ALTERNATE(nodelabel) \ - do { \ - BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \ - "Motionsense alternate node does not exist"); \ - ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel)); \ +#define MOTIONSENSE_ENABLE_ALTERNATE(nodelabel) \ + do { \ + BUILD_ASSERT(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \ + "Motionsense alternate node does not exist"); \ + ENABLE_ALT_MOTION_SENSOR(DT_NODELABEL(nodelabel)); \ } while (0) /* -- cgit v1.2.1 From 51e37892d588dece6737cfacd20e3f64ca9a041b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:49 -0600 Subject: zephyr/shim/chip/npcx/shi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If34d4088b6bea5f4c7b0aa3a177f3720d1c629b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728334 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/shi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/zephyr/shim/chip/npcx/shi.c b/zephyr/shim/chip/npcx/shi.c index 9e52228e37..74dfca12cd 100644 --- a/zephyr/shim/chip/npcx/shi.c +++ b/zephyr/shim/chip/npcx/shi.c @@ -83,12 +83,11 @@ static void shi_init(void) ap_power_ev_init_callback(&cb, shi_power_change, #if CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK AP_POWER_RESUME_INIT | - AP_POWER_SUSPEND_COMPLETE + AP_POWER_SUSPEND_COMPLETE #else - AP_POWER_RESUME | - AP_POWER_SUSPEND + AP_POWER_RESUME | AP_POWER_SUSPEND #endif - ); + ); ap_power_ev_add_callback(&cb); if (IS_ENABLED(CONFIG_CROS_SHI_NPCX_DEBUG) || -- cgit v1.2.1 From c4821157f0e91f01a52b0dd5a817778b8d6f11c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:33 -0600 Subject: board/banshee/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic34174020723a4bff1b13da5dc5d362453251ff8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728018 Reviewed-by: Jeremy Bettis --- board/banshee/board.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/banshee/board.c b/board/banshee/board.c index 8f1d8bb811..adb233c85f 100644 --- a/board/banshee/board.c +++ b/board/banshee/board.c @@ -29,8 +29,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) @@ -50,25 +50,25 @@ void board_set_charger_current_limit_deferred(void) int rv; if (extpower_is_present() && - (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)) + (battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED)) /* AC only or AC+DC but battery is disconnect */ action = MASK_SET; else action = MASK_CLR; rv = i2c_update16(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - ISL9241_REG_CONTROL3, - ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, action); + chg_chips[CHARGER_SOLO].i2c_addr_flags, + ISL9241_REG_CONTROL3, + ISL9241_CONTROL3_INPUT_CURRENT_LIMIT, action); if (rv) - CPRINTF("Could not set charger input current limit! Error: %d\n" - , rv); + CPRINTF("Could not set charger input current limit! Error: %d\n", + rv); } DECLARE_DEFERRED(board_set_charger_current_limit_deferred); DECLARE_HOOK(HOOK_SECOND, board_set_charger_current_limit_deferred, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); void battery_present_interrupt(enum gpio_signal signal) { @@ -87,19 +87,19 @@ void board_init(void) gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH); gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH); gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(5)), - GPIO_ALT_FUNC_DEFAULT); + GPIO_ALT_FUNC_DEFAULT); } else if (board_id == 1) { /* keyboard_col4_inverted on board id 1 */ gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH); gpio_set_flags(GPIO_EC_KSO_05_INV, GPIO_ODR_HIGH); gpio_set_alternate_function(GPIO_PORT_1, (BIT(4) | BIT(7)), - GPIO_ALT_FUNC_DEFAULT); + GPIO_ALT_FUNC_DEFAULT); } else { /* keyboard_col5_inverted on board id 2 and later */ gpio_set_flags(GPIO_EC_KSO_02_INV, GPIO_ODR_HIGH); gpio_set_flags(GPIO_EC_KSO_04_INV, GPIO_ODR_HIGH); gpio_set_alternate_function(GPIO_PORT_1, (BIT(5) | BIT(7)), - GPIO_ALT_FUNC_DEFAULT); + GPIO_ALT_FUNC_DEFAULT); } board_id_keyboard_col_inverted(board_id); -- cgit v1.2.1 From 9ee82188d27181e7a9fa44e095dccda57aba8844 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:28 -0600 Subject: board/agah/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id12979151760145877228068624206e7fc56ca29 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727972 Reviewed-by: Jeremy Bettis --- board/agah/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/agah/i2c.c b/board/agah/i2c.c index dedf3b4c4f..0b8a465d9d 100644 --- a/board/agah/i2c.c +++ b/board/agah/i2c.c @@ -8,7 +8,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From f6ac09b09303ba56e9c3a6dd9b01ceb2187b013e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:45 -0600 Subject: driver/accelgyro_icm426xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0a92e3455836f231b282f66670938b2e5c1ae78c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729919 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm426xx.h | 351 ++++++++++++++++++++++---------------------- 1 file changed, 174 insertions(+), 177 deletions(-) diff --git a/driver/accelgyro_icm426xx.h b/driver/accelgyro_icm426xx.h index 9162f27b8c..6409f38932 100644 --- a/driver/accelgyro_icm426xx.h +++ b/driver/accelgyro_icm426xx.h @@ -15,72 +15,69 @@ * 7-bit address is 110100Xb. Where 'X' is determined * by the logic level on pin AP_AD0. */ -#define ICM426XX_ADDR0_FLAGS 0x68 -#define ICM426XX_ADDR1_FLAGS 0x69 +#define ICM426XX_ADDR0_FLAGS 0x68 +#define ICM426XX_ADDR1_FLAGS 0x69 /* Min and Max sampling frequency in mHz */ -#define ICM426XX_ACCEL_MIN_FREQ 3125 -#define ICM426XX_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(500000, 100000) -#define ICM426XX_GYRO_MIN_FREQ 12500 -#define ICM426XX_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000) +#define ICM426XX_ACCEL_MIN_FREQ 3125 +#define ICM426XX_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(500000, 100000) +#define ICM426XX_GYRO_MIN_FREQ 12500 +#define ICM426XX_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(4000000, 100000) /* Min and Max Accel FS in G */ -#define ICM426XX_ACCEL_FS_MIN_VAL 2 -#define ICM426XX_ACCEL_FS_MAX_VAL 16 +#define ICM426XX_ACCEL_FS_MIN_VAL 2 +#define ICM426XX_ACCEL_FS_MAX_VAL 16 /* Min and Max Gyro FS in dps */ -#define ICM426XX_GYRO_FS_MIN_VAL 125 -#define ICM426XX_GYRO_FS_MAX_VAL 2000 +#define ICM426XX_GYRO_FS_MIN_VAL 125 +#define ICM426XX_GYRO_FS_MAX_VAL 2000 /* accel stabilization time in us */ -#define ICM426XX_ACCEL_START_TIME 20000 -#define ICM426XX_ACCEL_STOP_TIME 0 +#define ICM426XX_ACCEL_START_TIME 20000 +#define ICM426XX_ACCEL_STOP_TIME 0 /* gyro stabilization time in us */ -#define ICM426XX_GYRO_START_TIME 60000 -#define ICM426XX_GYRO_STOP_TIME 150000 +#define ICM426XX_GYRO_START_TIME 60000 +#define ICM426XX_GYRO_STOP_TIME 150000 /* Reg value from Accel FS in G */ -#define ICM426XX_ACCEL_FS_TO_REG(_fs) ((_fs) < 2 ? 3 : \ - (_fs) > 16 ? 0 : \ - 3 - __fls((_fs) / 2)) +#define ICM426XX_ACCEL_FS_TO_REG(_fs) \ + ((_fs) < 2 ? 3 : (_fs) > 16 ? 0 : 3 - __fls((_fs) / 2)) /* Accel FSR in G from Reg value */ -#define ICM426XX_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2) +#define ICM426XX_ACCEL_REG_TO_FS(_reg) ((1 << (3 - (_reg))) * 2) /* Reg value from Gyro FS in dps */ -#define ICM426XX_GYRO_FS_TO_REG(_fs) ((_fs) < 125 ? 4 : \ - (_fs) > 2000 ? 0 : \ - 4 - __fls((_fs) / 125)) +#define ICM426XX_GYRO_FS_TO_REG(_fs) \ + ((_fs) < 125 ? 4 : (_fs) > 2000 ? 0 : 4 - __fls((_fs) / 125)) /* Gyro FSR in dps from Reg value */ -#define ICM426XX_GYRO_REG_TO_FS(_reg) ((1 << (4 - (_reg))) * 125) +#define ICM426XX_GYRO_REG_TO_FS(_reg) ((1 << (4 - (_reg))) * 125) /* Reg value from ODR in mHz */ -#define ICM426XX_ODR_TO_REG(_odr) ((_odr) <= 200000 ? \ - 13 - __fls((_odr) / 3125) : \ - (_odr) < 500000 ? 7 : \ - (_odr) < 1000000 ? 15 : \ - 6 - __fls((_odr) / 1000000)) +#define ICM426XX_ODR_TO_REG(_odr) \ + ((_odr) <= 200000 ? 13 - __fls((_odr) / 3125) : \ + (_odr) < 500000 ? 7 : \ + (_odr) < 1000000 ? 15 : \ + 6 - __fls((_odr) / 1000000)) /* ODR in mHz from Reg value */ -#define ICM426XX_REG_TO_ODR(_reg) ((_reg) == 15 ? 500000 : \ - (_reg) >= 7 ? \ - (1 << (13 - (_reg))) * 3125 : \ - (1 << (6 - (_reg))) * 1000000) +#define ICM426XX_REG_TO_ODR(_reg) \ + ((_reg) == 15 ? 500000 : \ + (_reg) >= 7 ? (1 << (13 - (_reg))) * 3125 : \ + (1 << (6 - (_reg))) * 1000000) /* Reg value for the next higher ODR */ -#define ICM426XX_ODR_REG_UP(_reg) ((_reg) == 15 ? 6 : \ - (_reg) == 7 ? 15 : \ - (_reg) - 1) +#define ICM426XX_ODR_REG_UP(_reg) \ + ((_reg) == 15 ? 6 : (_reg) == 7 ? 15 : (_reg)-1) /* * Register addresses are virtual address on 16 bits. * MSB is coding register bank and LSB real register address. * ex: bank 4, register 1F => 0x041F */ -#define ICM426XX_REG_DEVICE_CONFIG 0x0011 -#define ICM426XX_SOFT_RESET_CONFIG BIT(0) +#define ICM426XX_REG_DEVICE_CONFIG 0x0011 +#define ICM426XX_SOFT_RESET_CONFIG BIT(0) enum icm426xx_slew_rate { ICM426XX_SLEW_RATE_20NS_60NS, @@ -90,63 +87,63 @@ enum icm426xx_slew_rate { ICM426XX_SLEW_RATE_2NS_6NS, ICM426XX_SLEW_RATE_INF_2NS, }; -#define ICM426XX_REG_DRIVE_CONFIG 0x0013 -#define ICM426XX_DRIVE_CONFIG_MASK GENMASK(5, 0) -#define ICM426XX_I2C_SLEW_RATE(_s) (((_s) & 0x07) << 3) -#define ICM426XX_SPI_SLEW_RATE(_s) ((_s) & 0x07) +#define ICM426XX_REG_DRIVE_CONFIG 0x0013 +#define ICM426XX_DRIVE_CONFIG_MASK GENMASK(5, 0) +#define ICM426XX_I2C_SLEW_RATE(_s) (((_s)&0x07) << 3) +#define ICM426XX_SPI_SLEW_RATE(_s) ((_s)&0x07) /* default int configuration is pulsed mode, open drain, and active low */ -#define ICM426XX_REG_INT_CONFIG 0x0014 -#define ICM426XX_INT2_LATCHED BIT(5) -#define ICM426XX_INT2_PUSH_PULL BIT(4) -#define ICM426XX_INT2_ACTIVE_HIGH BIT(3) -#define ICM426XX_INT1_LATCHED BIT(2) -#define ICM426XX_INT1_PUSH_PULL BIT(1) -#define ICM426XX_INT1_ACTIVE_HIGH BIT(0) - -#define ICM426XX_REG_FIFO_CONFIG 0x0016 -#define ICM426XX_FIFO_MODE_BYPASS (0x00 << 6) -#define ICM426XX_FIFO_MODE_STREAM (0x01 << 6) -#define ICM426XX_FIFO_MODE_STOP_FULL (0x02 << 6) +#define ICM426XX_REG_INT_CONFIG 0x0014 +#define ICM426XX_INT2_LATCHED BIT(5) +#define ICM426XX_INT2_PUSH_PULL BIT(4) +#define ICM426XX_INT2_ACTIVE_HIGH BIT(3) +#define ICM426XX_INT1_LATCHED BIT(2) +#define ICM426XX_INT1_PUSH_PULL BIT(1) +#define ICM426XX_INT1_ACTIVE_HIGH BIT(0) + +#define ICM426XX_REG_FIFO_CONFIG 0x0016 +#define ICM426XX_FIFO_MODE_BYPASS (0x00 << 6) +#define ICM426XX_FIFO_MODE_STREAM (0x01 << 6) +#define ICM426XX_FIFO_MODE_STOP_FULL (0x02 << 6) /* data are 16 bits */ -#define ICM426XX_REG_TEMP_DATA 0x001D +#define ICM426XX_REG_TEMP_DATA 0x001D /* X + Y + Z: 3 * 16 bits */ -#define ICM426XX_REG_ACCEL_DATA_XYZ 0x001F -#define ICM426XX_REG_GYRO_DATA_XYZ 0x0025 +#define ICM426XX_REG_ACCEL_DATA_XYZ 0x001F +#define ICM426XX_REG_GYRO_DATA_XYZ 0x0025 -#define ICM426XX_INVALID_DATA -32768 +#define ICM426XX_INVALID_DATA -32768 -#define ICM426XX_REG_INT_STATUS 0x002D -#define ICM426XX_UI_FSYNC_INT BIT(6) -#define ICM426XX_PLL_RDY_INT BIT(5) -#define ICM426XX_RESET_DONE_INT BIT(4) -#define ICM426XX_DATA_RDY_INT BIT(3) -#define ICM426XX_FIFO_THS_INT BIT(2) -#define ICM426XX_FIFO_FULL_INT BIT(1) -#define ICM426XX_AGC_RDY_INT BIT(0) +#define ICM426XX_REG_INT_STATUS 0x002D +#define ICM426XX_UI_FSYNC_INT BIT(6) +#define ICM426XX_PLL_RDY_INT BIT(5) +#define ICM426XX_RESET_DONE_INT BIT(4) +#define ICM426XX_DATA_RDY_INT BIT(3) +#define ICM426XX_FIFO_THS_INT BIT(2) +#define ICM426XX_FIFO_FULL_INT BIT(1) +#define ICM426XX_AGC_RDY_INT BIT(0) /* FIFO count is 16 bits */ -#define ICM426XX_REG_FIFO_COUNT 0x002E -#define ICM426XX_REG_FIFO_DATA 0x0030 - -#define ICM426XX_REG_SIGNAL_PATH_RESET 0x004B -#define ICM426XX_ABORT_AND_RESET BIT(3) -#define ICM426XX_TMST_STROBE BIT(2) -#define ICM426XX_FIFO_FLUSH BIT(1) - -#define ICM426XX_REG_INTF_CONFIG0 0x004C -#define ICM426XX_DATA_CONF_MASK GENMASK(7, 4) -#define ICM426XX_FIFO_HOLD_LAST_DATA BIT(7) -#define ICM426XX_FIFO_COUNT_REC BIT(6) -#define ICM426XX_FIFO_COUNT_BE BIT(5) -#define ICM426XX_SENSOR_DATA_BE BIT(4) -#define ICM426XX_UI_SIFS_CFG_MASK GENMASK(1, 0) -#define ICM426XX_UI_SIFS_CFG_SPI_DIS 0x02 -#define ICM426XX_UI_SIFS_CFG_I2C_DIS 0x03 - -#define ICM426XX_REG_INTF_CONFIG1 0x004D -#define ICM426XX_ACCEL_LP_CLK_SEL BIT(3) +#define ICM426XX_REG_FIFO_COUNT 0x002E +#define ICM426XX_REG_FIFO_DATA 0x0030 + +#define ICM426XX_REG_SIGNAL_PATH_RESET 0x004B +#define ICM426XX_ABORT_AND_RESET BIT(3) +#define ICM426XX_TMST_STROBE BIT(2) +#define ICM426XX_FIFO_FLUSH BIT(1) + +#define ICM426XX_REG_INTF_CONFIG0 0x004C +#define ICM426XX_DATA_CONF_MASK GENMASK(7, 4) +#define ICM426XX_FIFO_HOLD_LAST_DATA BIT(7) +#define ICM426XX_FIFO_COUNT_REC BIT(6) +#define ICM426XX_FIFO_COUNT_BE BIT(5) +#define ICM426XX_SENSOR_DATA_BE BIT(4) +#define ICM426XX_UI_SIFS_CFG_MASK GENMASK(1, 0) +#define ICM426XX_UI_SIFS_CFG_SPI_DIS 0x02 +#define ICM426XX_UI_SIFS_CFG_I2C_DIS 0x03 + +#define ICM426XX_REG_INTF_CONFIG1 0x004D +#define ICM426XX_ACCEL_LP_CLK_SEL BIT(3) enum icm426xx_sensor_mode { ICM426XX_MODE_OFF, @@ -154,20 +151,20 @@ enum icm426xx_sensor_mode { ICM426XX_MODE_LOW_POWER, ICM426XX_MODE_LOW_NOISE, }; -#define ICM426XX_REG_PWR_MGMT0 0x004E -#define ICM426XX_TEMP_DIS BIT(5) -#define ICM426XX_IDLE BIT(4) -#define ICM426XX_GYRO_MODE_MASK GENMASK(3, 2) -#define ICM426XX_GYRO_MODE(_m) (((_m) & 0x03) << 2) -#define ICM426XX_ACCEL_MODE_MASK GENMASK(1, 0) -#define ICM426XX_ACCEL_MODE(_m) ((_m) & 0x03) - -#define ICM426XX_REG_GYRO_CONFIG0 0x004F -#define ICM426XX_REG_ACCEL_CONFIG0 0x0050 -#define ICM426XX_FS_MASK GENMASK(7, 5) -#define ICM426XX_FS_SEL(_fs) (((_fs) & 0x07) << 5) -#define ICM426XX_ODR_MASK GENMASK(3, 0) -#define ICM426XX_ODR(_odr) ((_odr) & 0x0F) +#define ICM426XX_REG_PWR_MGMT0 0x004E +#define ICM426XX_TEMP_DIS BIT(5) +#define ICM426XX_IDLE BIT(4) +#define ICM426XX_GYRO_MODE_MASK GENMASK(3, 2) +#define ICM426XX_GYRO_MODE(_m) (((_m)&0x03) << 2) +#define ICM426XX_ACCEL_MODE_MASK GENMASK(1, 0) +#define ICM426XX_ACCEL_MODE(_m) ((_m)&0x03) + +#define ICM426XX_REG_GYRO_CONFIG0 0x004F +#define ICM426XX_REG_ACCEL_CONFIG0 0x0050 +#define ICM426XX_FS_MASK GENMASK(7, 5) +#define ICM426XX_FS_SEL(_fs) (((_fs)&0x07) << 5) +#define ICM426XX_ODR_MASK GENMASK(3, 0) +#define ICM426XX_ODR(_odr) ((_odr)&0x0F) enum icm426xx_filter_bw { /* low noise mode */ @@ -178,87 +175,87 @@ enum icm426xx_filter_bw { ICM426XX_FILTER_BW_AVG_16X = 6, }; -#define ICM426XX_REG_GYRO_ACCEL_CONFIG0 0x0052 -#define ICM426XX_ACCEL_UI_FILT_MASK GENMASK(7, 4) -#define ICM426XX_ACCEL_UI_FILT_BW(_f) (((_f) & 0x0F) << 4) -#define ICM426XX_GYRO_UI_FILT_MASK GENMASK(3, 0) -#define ICM426XX_GYRO_UI_FILT_BW(_f) ((_f) & 0x0F) - -#define ICM426XX_REG_FIFO_CONFIG1 0x005F -#define ICM426XX_FIFO_PARTIAL_READ BIT(6) -#define ICM426XX_FIFO_WM_GT_TH BIT(5) -#define ICM426XX_FIFO_EN_MASK GENMASK(3, 0) -#define ICM426XX_FIFO_TMST_FSYNC_EN BIT(3) -#define ICM426XX_FIFO_TEMP_EN BIT(2) -#define ICM426XX_FIFO_GYRO_EN BIT(1) -#define ICM426XX_FIFO_ACCEL_EN BIT(0) +#define ICM426XX_REG_GYRO_ACCEL_CONFIG0 0x0052 +#define ICM426XX_ACCEL_UI_FILT_MASK GENMASK(7, 4) +#define ICM426XX_ACCEL_UI_FILT_BW(_f) (((_f)&0x0F) << 4) +#define ICM426XX_GYRO_UI_FILT_MASK GENMASK(3, 0) +#define ICM426XX_GYRO_UI_FILT_BW(_f) ((_f)&0x0F) + +#define ICM426XX_REG_FIFO_CONFIG1 0x005F +#define ICM426XX_FIFO_PARTIAL_READ BIT(6) +#define ICM426XX_FIFO_WM_GT_TH BIT(5) +#define ICM426XX_FIFO_EN_MASK GENMASK(3, 0) +#define ICM426XX_FIFO_TMST_FSYNC_EN BIT(3) +#define ICM426XX_FIFO_TEMP_EN BIT(2) +#define ICM426XX_FIFO_GYRO_EN BIT(1) +#define ICM426XX_FIFO_ACCEL_EN BIT(0) /* FIFO watermark value is 16 bits little endian */ -#define ICM426XX_REG_FIFO_WATERMARK 0x0060 - -#define ICM426XX_REG_INT_CONFIG1 0x0064 -#define ICM426XX_INT_PULSE_DURATION BIT(6) -#define ICM426XX_INT_TDEASSERT_DIS BIT(5) -#define ICM426XX_INT_ASYNC_RESET BIT(4) - -#define ICM426XX_REG_INT_SOURCE0 0x0065 -#define ICM426XX_UI_FSYNC_INT1_EN BIT(6) -#define ICM426XX_PLL_RDY_INT1_EN BIT(5) -#define ICM426XX_RESET_DONE_INT1_EN BIT(4) -#define ICM426XX_UI_DRDY_INT1_EN BIT(3) -#define ICM426XX_FIFO_THS_INT1_EN BIT(2) -#define ICM426XX_FIFO_FULL_INT1_EN BIT(1) -#define ICM426XX_UI_AGC_RDY_INT1_EN BIT(0) - -#define ICM426XX_REG_INT_SOURCE3 0x0068 -#define ICM426XX_UI_FSYNC_INT2_EN BIT(6) -#define ICM426XX_PLL_RDY_INT2_EN BIT(5) -#define ICM426XX_RESET_DONE_INT2_EN BIT(4) -#define ICM426XX_UI_DRDY_INT2_EN BIT(3) -#define ICM426XX_FIFO_THS_INT2_EN BIT(2) -#define ICM426XX_FIFO_FULL_INT2_EN BIT(1) -#define ICM426XX_UI_AGC_RDY_INT2_EN BIT(0) - -#define ICM426XX_REG_WHO_AM_I 0x0075 -#define ICM426XX_CHIP_ICM40608 0x39 -#define ICM426XX_CHIP_ICM42605 0x42 - -#define ICM426XX_REG_BANK_SEL 0x0076 -#define ICM426XX_BANK_SEL(_b) ((_b) & 0x07) - -#define ICM426XX_REG_INTF_CONFIG4 0x017A -#define ICM426XX_I3C_BUS_MODE BIT(6) -#define ICM426XX_SPI_AP_4WIRE BIT(1) - -#define ICM426XX_REG_INTF_CONFIG5 0x017B -#define ICM426XX_PIN9_FUNC_INT2 (0x00 << 1) -#define ICM426XX_PIN9_FUNC_FSYNC (0x01 << 1) - -#define ICM426XX_REG_INTF_CONFIG6 0x017C -#define ICM426XX_INTF_CONFIG6_MASK GENMASK(4, 0) -#define ICM426XX_I3C_EN BIT(4) -#define ICM426XX_I3C_IBI_BYTE_EN BIT(3) -#define ICM426XX_I3C_IBI_EN BIT(2) -#define ICM426XX_I3C_DDR_EN BIT(1) -#define ICM426XX_I3C_SDR_EN BIT(0) - -#define ICM426XX_REG_INT_SOURCE8 0x044F -#define ICM426XX_FSYNC_IBI_EN BIT(5) -#define ICM426XX_PLL_RDY_IBI_EN BIT(4) -#define ICM426XX_UI_DRDY_IBI_EN BIT(3) -#define ICM426XX_FIFO_THS_IBI_EN BIT(2) -#define ICM426XX_FIFO_FULL_IBI_EN BIT(1) -#define ICM426XX_AGC_RDY_IBI_EN BIT(0) - -#define ICM426XX_REG_OFFSET_USER0 0x0477 -#define ICM426XX_REG_OFFSET_USER1 0x0478 -#define ICM426XX_REG_OFFSET_USER2 0x0479 -#define ICM426XX_REG_OFFSET_USER3 0x047A -#define ICM426XX_REG_OFFSET_USER4 0x047B -#define ICM426XX_REG_OFFSET_USER5 0x047C -#define ICM426XX_REG_OFFSET_USER6 0x047D -#define ICM426XX_REG_OFFSET_USER7 0x047E -#define ICM426XX_REG_OFFSET_USER8 0x047F +#define ICM426XX_REG_FIFO_WATERMARK 0x0060 + +#define ICM426XX_REG_INT_CONFIG1 0x0064 +#define ICM426XX_INT_PULSE_DURATION BIT(6) +#define ICM426XX_INT_TDEASSERT_DIS BIT(5) +#define ICM426XX_INT_ASYNC_RESET BIT(4) + +#define ICM426XX_REG_INT_SOURCE0 0x0065 +#define ICM426XX_UI_FSYNC_INT1_EN BIT(6) +#define ICM426XX_PLL_RDY_INT1_EN BIT(5) +#define ICM426XX_RESET_DONE_INT1_EN BIT(4) +#define ICM426XX_UI_DRDY_INT1_EN BIT(3) +#define ICM426XX_FIFO_THS_INT1_EN BIT(2) +#define ICM426XX_FIFO_FULL_INT1_EN BIT(1) +#define ICM426XX_UI_AGC_RDY_INT1_EN BIT(0) + +#define ICM426XX_REG_INT_SOURCE3 0x0068 +#define ICM426XX_UI_FSYNC_INT2_EN BIT(6) +#define ICM426XX_PLL_RDY_INT2_EN BIT(5) +#define ICM426XX_RESET_DONE_INT2_EN BIT(4) +#define ICM426XX_UI_DRDY_INT2_EN BIT(3) +#define ICM426XX_FIFO_THS_INT2_EN BIT(2) +#define ICM426XX_FIFO_FULL_INT2_EN BIT(1) +#define ICM426XX_UI_AGC_RDY_INT2_EN BIT(0) + +#define ICM426XX_REG_WHO_AM_I 0x0075 +#define ICM426XX_CHIP_ICM40608 0x39 +#define ICM426XX_CHIP_ICM42605 0x42 + +#define ICM426XX_REG_BANK_SEL 0x0076 +#define ICM426XX_BANK_SEL(_b) ((_b)&0x07) + +#define ICM426XX_REG_INTF_CONFIG4 0x017A +#define ICM426XX_I3C_BUS_MODE BIT(6) +#define ICM426XX_SPI_AP_4WIRE BIT(1) + +#define ICM426XX_REG_INTF_CONFIG5 0x017B +#define ICM426XX_PIN9_FUNC_INT2 (0x00 << 1) +#define ICM426XX_PIN9_FUNC_FSYNC (0x01 << 1) + +#define ICM426XX_REG_INTF_CONFIG6 0x017C +#define ICM426XX_INTF_CONFIG6_MASK GENMASK(4, 0) +#define ICM426XX_I3C_EN BIT(4) +#define ICM426XX_I3C_IBI_BYTE_EN BIT(3) +#define ICM426XX_I3C_IBI_EN BIT(2) +#define ICM426XX_I3C_DDR_EN BIT(1) +#define ICM426XX_I3C_SDR_EN BIT(0) + +#define ICM426XX_REG_INT_SOURCE8 0x044F +#define ICM426XX_FSYNC_IBI_EN BIT(5) +#define ICM426XX_PLL_RDY_IBI_EN BIT(4) +#define ICM426XX_UI_DRDY_IBI_EN BIT(3) +#define ICM426XX_FIFO_THS_IBI_EN BIT(2) +#define ICM426XX_FIFO_FULL_IBI_EN BIT(1) +#define ICM426XX_AGC_RDY_IBI_EN BIT(0) + +#define ICM426XX_REG_OFFSET_USER0 0x0477 +#define ICM426XX_REG_OFFSET_USER1 0x0478 +#define ICM426XX_REG_OFFSET_USER2 0x0479 +#define ICM426XX_REG_OFFSET_USER3 0x047A +#define ICM426XX_REG_OFFSET_USER4 0x047B +#define ICM426XX_REG_OFFSET_USER5 0x047C +#define ICM426XX_REG_OFFSET_USER6 0x047D +#define ICM426XX_REG_OFFSET_USER7 0x047E +#define ICM426XX_REG_OFFSET_USER8 0x047F extern const struct accelgyro_drv icm426xx_drv; -- cgit v1.2.1 From ef595454825169b76d7cba54cf4947b0ad3df919 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:48 -0600 Subject: extra/usb_updater/desc_parser.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85737cb5b016e830d8b96b962b82ec4a276dc03e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730190 Reviewed-by: Jeremy Bettis --- extra/usb_updater/desc_parser.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/extra/usb_updater/desc_parser.c b/extra/usb_updater/desc_parser.c index 5bd996bdda..c0afe835ac 100644 --- a/extra/usb_updater/desc_parser.c +++ b/extra/usb_updater/desc_parser.c @@ -75,8 +75,7 @@ static int get_next_token(char *input, size_t expected_size, char **output) next_colon = strchr(input, ':'); if (next_colon) *next_colon = '\0'; - if (!next_colon || (expected_size && - strlen(input) != expected_size)) { + if (!next_colon || (expected_size && strlen(input) != expected_size)) { fprintf(stderr, "Invalid entry in section %d\n", section_count_); return -EINVAL; @@ -98,16 +97,15 @@ static int get_hex_value(char *input, char **output) value = strtol(input, &e, 16); if ((e && *e) || (strlen(input) > 8)) { - fprintf(stderr, "Invalid hex value %s in section %d\n", - input, section_count_); + fprintf(stderr, "Invalid hex value %s in section %d\n", input, + section_count_); return -EINVAL; } return value; } -static int parse_range(char *next_line, - size_t line_len, +static int parse_range(char *next_line, size_t line_len, struct addr_range *parsed_range) { char *line_cursor; @@ -299,7 +297,6 @@ int parser_get_next_range(struct addr_range **range) *range = new_range; return 0; - } int parser_find_board(const char *hash_file_name, const char *board_id) -- cgit v1.2.1 From 059242ab7717152bfe84886bf6913a567ba3d014 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:05 -0600 Subject: zephyr/shim/src/tcpc_nct38xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I791b97898c4176a8aa88d2d639ff67971805928c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730902 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/tcpc_nct38xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/zephyr/shim/src/tcpc_nct38xx.c b/zephyr/shim/src/tcpc_nct38xx.c index f8c73d1aa0..90a75ad4f9 100644 --- a/zephyr/shim/src/tcpc_nct38xx.c +++ b/zephyr/shim/src/tcpc_nct38xx.c @@ -18,10 +18,9 @@ ([TCPC_PORT(id)] = GPIO_DEV_WITH_COMMA(id)), ()) /* NCT38XX GPIO device pool for binding the TCPC port and NCT38XX GPIO device */ -static const struct device - *nct38xx_gpio_devices[CONFIG_USB_PD_PORT_MAX_COUNT] = { - DT_FOREACH_STATUS_OKAY(nuvoton_nct38xx, GPIO_DEV_BINDING) - }; +static const struct device *nct38xx_gpio_devices[CONFIG_USB_PD_PORT_MAX_COUNT] = { + DT_FOREACH_STATUS_OKAY(nuvoton_nct38xx, GPIO_DEV_BINDING) +}; const struct device *nct38xx_get_gpio_device_from_port(const int port) { -- cgit v1.2.1 From 9b7a5d1daf20c52f658a6f35275e98bab9310fad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:41 -0600 Subject: board/drawcia_riscv/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7476aaacacb0db1185a33aee815968a8b5bb11ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728239 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/board.c | 176 ++++++++++++++++++++------------------------ 1 file changed, 80 insertions(+), 96 deletions(-) diff --git a/board/drawcia_riscv/board.c b/board/drawcia_riscv/board.c index e770d17818..20d6d35e18 100644 --- a/board/drawcia_riscv/board.c +++ b/board/drawcia_riscv/board.c @@ -42,7 +42,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -165,48 +165,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -280,17 +268,13 @@ static struct accelgyro_saved_data_t g_bma253_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -496,8 +480,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -505,11 +489,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -520,11 +504,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -629,33 +613,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -685,9 +667,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -706,14 +687,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From d854d61d68005744b463b8a21123ad3b91d54db3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:39 -0600 Subject: chip/npcx/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I141d5682a65de557904909cbb97ca49d3385f7af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729377 Reviewed-by: Jeremy Bettis --- chip/npcx/config_chip.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index c397161e07..dd999b40e0 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -13,20 +13,20 @@ * Set the chip family version to 4 digits to keep the flexibility in case * we need the minor version for chip variants in a family. */ -#define NPCX_FAMILY_NPCX5 5000 -#define NPCX_FAMILY_NPCX7 7000 -#define NPCX_FAMILY_NPCX9 9000 +#define NPCX_FAMILY_NPCX5 5000 +#define NPCX_FAMILY_NPCX7 7000 +#define NPCX_FAMILY_NPCX9 9000 /* Features depend on chip family */ #if defined(CHIP_FAMILY_NPCX5) #include "config_chip-npcx5.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX5 #elif defined(CHIP_FAMILY_NPCX7) #include "config_chip-npcx7.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX7 #elif defined(CHIP_FAMILY_NPCX9) #include "config_chip-npcx9.h" -#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9 +#define NPCX_FAMILY_VERSION NPCX_FAMILY_NPCX9 #else #error "Unsupported chip family" #endif @@ -46,27 +46,27 @@ * Notice instant wake-up from deep-idle cannot exceed 200 ms */ #define HOOK_TICK_INTERVAL_MS 200 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 672 -#define LARGER_TASK_STACK_SIZE 800 -#define VENTI_TASK_STACK_SIZE 928 -#define ULTRA_TASK_STACK_SIZE 1056 -#define TRENTA_TASK_STACK_SIZE 1184 +#define IDLE_TASK_STACK_SIZE 672 +#define LARGER_TASK_STACK_SIZE 800 +#define VENTI_TASK_STACK_SIZE 928 +#define ULTRA_TASK_STACK_SIZE 1056 +#define TRENTA_TASK_STACK_SIZE 1184 -#define CHARGER_TASK_STACK_SIZE 800 -#define HOOKS_TASK_STACK_SIZE 800 -#define CONSOLE_TASK_STACK_SIZE 800 +#define CHARGER_TASK_STACK_SIZE 800 +#define HOOKS_TASK_STACK_SIZE 800 +#define CONSOLE_TASK_STACK_SIZE 800 /* Default task stack size */ -#define TASK_STACK_SIZE 672 +#define TASK_STACK_SIZE 672 /* Address of RAM log used by Booter */ -#define ADDR_BOOT_RAMLOG 0x100C7FC0 +#define ADDR_BOOT_RAMLOG 0x100C7FC0 #include "config_flash_layout.h" @@ -79,7 +79,7 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT /* Default use UART1 as console */ -#define CONFIG_CONSOLE_UART 0 +#define CONFIG_CONSOLE_UART 0 #define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) @@ -88,4 +88,4 @@ #define NPCX_SELECT_KSI_TO_GPIO #endif -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From 11b704e1d895896e3a574996ddb6997e28f77430 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:05 -0600 Subject: driver/accel_lis2dh.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I973448627feb52f78c05eaa67600acf3ad4604da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729908 Reviewed-by: Jeremy Bettis --- driver/accel_lis2dh.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/driver/accel_lis2dh.c b/driver/accel_lis2dh.c index 35d275b379..1bdcfbdf34 100644 --- a/driver/accel_lis2dh.c +++ b/driver/accel_lis2dh.c @@ -21,8 +21,8 @@ #include "driver/stm_mems_common.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /** * set_range - set full scale range @@ -78,9 +78,9 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) if (rate == 0) { /* Power Off device */ - ret = st_write_data_with_mask( - s, LIS2DH_CTRL1_ADDR, - LIS2DH_ACC_ODR_MASK, LIS2DH_ODR_0HZ_VAL); + ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR, + LIS2DH_ACC_ODR_MASK, + LIS2DH_ODR_0HZ_VAL); goto unlock_rate; } @@ -101,7 +101,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) * to write accel parameters until we are done */ ret = st_write_data_with_mask(s, LIS2DH_CTRL1_ADDR, LIS2DH_ACC_ODR_MASK, - reg_val); + reg_val); if (ret == EC_SUCCESS) data->base.odr = normalized_rate; @@ -114,8 +114,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2DH_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DH_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RS Error", s->name, s->type); return ret; @@ -147,8 +147,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v) } /* Read output data bytes starting at LIS2DH_OUT_X_L_ADDR */ - ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, - LIS2DH_OUT_X_L_ADDR, raw, OUT_XYZ_SIZE); + ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2DH_OUT_X_L_ADDR, + raw, OUT_XYZ_SIZE); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type); return ret; @@ -195,34 +195,34 @@ static int init(struct motion_sensor_t *s) * register must be restored to it's default. */ /* Enable all accel axes data and clear old settings */ - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL1_ADDR, LIS2DH_ENABLE_ALL_AXES); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL1_ADDR, + LIS2DH_ENABLE_ALL_AXES); if (ret != EC_SUCCESS) goto err_unlock; - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL2_ADDR, LIS2DH_CTRL2_RESET_VAL); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL2_ADDR, + LIS2DH_CTRL2_RESET_VAL); if (ret != EC_SUCCESS) goto err_unlock; - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL3_ADDR, LIS2DH_CTRL3_RESET_VAL); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL3_ADDR, + LIS2DH_CTRL3_RESET_VAL); if (ret != EC_SUCCESS) goto err_unlock; /* Enable BDU */ - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL4_ADDR, LIS2DH_BDU_MASK); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL4_ADDR, + LIS2DH_BDU_MASK); if (ret != EC_SUCCESS) goto err_unlock; - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL5_ADDR, LIS2DH_CTRL5_RESET_VAL); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL5_ADDR, + LIS2DH_CTRL5_RESET_VAL); if (ret != EC_SUCCESS) goto err_unlock; - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DH_CTRL6_ADDR, LIS2DH_CTRL6_RESET_VAL); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LIS2DH_CTRL6_ADDR, + LIS2DH_CTRL6_RESET_VAL); if (ret != EC_SUCCESS) goto err_unlock; -- cgit v1.2.1 From 448739ebdc49474439215254f703736bbb664295 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:07 -0600 Subject: chip/stm32/usb_dfu_runtime.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc316382d58b977cf0db6ed975385b357f72ec70 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729568 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dfu_runtime.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/chip/stm32/usb_dfu_runtime.c b/chip/stm32/usb_dfu_runtime.c index 7626faec8e..fa26640732 100644 --- a/chip/stm32/usb_dfu_runtime.c +++ b/chip/stm32/usb_dfu_runtime.c @@ -23,15 +23,15 @@ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_DFU) = { }; /* DFU Functional Descriptor. */ -const struct usb_runtime_dfu_functional_desc USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, - dfu, dfu_func_desc) = { - .bLength = USB_DFU_RUNTIME_DESC_SIZE, - .bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL, - .bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS, - .wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT, - .wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE, - .bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION, -}; +const struct usb_runtime_dfu_functional_desc + USB_CUSTOM_DESC_VAR(USB_IFACE_DFU, dfu, dfu_func_desc) = { + .bLength = USB_DFU_RUNTIME_DESC_SIZE, + .bDescriptorType = USB_DFU_RUNTIME_DESC_FUNCTIONAL, + .bmAttributes = USB_DFU_RUNTIME_DESC_ATTRS, + .wDetachTimeOut = USB_DFU_RUNTIME_DESC_DETACH_TIMEOUT, + .wTransferSize = USB_DFU_RUNTIME_DESC_TRANSFER_SIZE, + .bcdDFUVersion = USB_DFU_RUNTIME_DESC_DFU_VERSION, + }; static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) { @@ -40,21 +40,21 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) usb_read_setup_packet(ep0_buf_rx, &packet); btable_ep[0].tx_count = 0; if ((packet.bmRequestType == - (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) && - (packet.bRequest == USB_REQ_SET_INTERFACE)) { + (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE)) && + (packet.bRequest == USB_REQ_SET_INTERFACE)) { /* ACK the change alternative mode request. */ STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; } else if ((packet.bmRequestType == - (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) && - (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) { + (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) && + (packet.bRequest == USB_DFU_RUNTIME_REQ_DETACH)) { /* Host is requesting a jump from application to DFU mode. */ STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return dfu_bootmanager_enter_dfu(); } else if (packet.bmRequestType == - (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) { + (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) { if (packet.bRequest == USB_DFU_RUNTIME_REQ_GET_STATUS) { /* Return the Get Status response. */ @@ -63,8 +63,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) .bState = USB_DFU_RUNTIME_STATE_APP_IDLE, }; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &response, sizeof(response)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), + &response, sizeof(response)); btable_ep[0].tx_count = sizeof(response); STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; @@ -76,8 +76,8 @@ static int dfu_runtime_request(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) .bState = USB_DFU_RUNTIME_STATE_APP_IDLE, }; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &response, sizeof(response)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), + &response, sizeof(response)); btable_ep[0].tx_count = sizeof(response); STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; -- cgit v1.2.1 From 74b93703bc6dc51b483c5242bd61be7cacbb6a3c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:32 -0600 Subject: zephyr/emul/emul_tcs3400.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27655735b6a5c00dd2e062860f03a4a4578c9d3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730699 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_tcs3400.c | 162 ++++++++++++++++++++++----------------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/zephyr/emul/emul_tcs3400.c b/zephyr/emul/emul_tcs3400.c index 15a1bbe9c7..fe5d605232 100644 --- a/zephyr/emul/emul_tcs3400.c +++ b/zephyr/emul/emul_tcs3400.c @@ -20,7 +20,7 @@ LOG_MODULE_REGISTER(emul_tcs); #include "driver/als_tcs3400.h" -#define TCS_DATA_FROM_I2C_EMUL(_emul) \ +#define TCS_DATA_FROM_I2C_EMUL(_emul) \ CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ struct tcs_emul_data, common) @@ -170,31 +170,31 @@ void tcs_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set) /** Mask reserved bits in registers of TCS3400 */ static const uint8_t tcs_emul_rsvd_mask[] = { - [TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0xa4, - [TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0x00, - [0x2] = 0xff, /* Reserved */ - [TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00, - [0x8 ... 0xb] = 0xff, /* Reserved */ - [TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0xf0, - [TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x81, - [0xe] = 0xff, /* Reserved */ - [TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0xfc, - [TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0xdf, - [TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = 0xf0, - [TCS_I2C_ID - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x6e, - [TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00, - [TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0xa4, + [TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0x00, + [0x2] = 0xff, /* Reserved */ + [TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00, + [0x8 ... 0xb] = 0xff, /* Reserved */ + [TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0xf0, + [TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x81, + [0xe] = 0xff, /* Reserved */ + [TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0xfc, + [TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0xdf, + [TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = 0xf0, + [TCS_I2C_ID - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x6e, + [TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00, + [TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00, }; /** @@ -208,28 +208,28 @@ static void tcs_emul_reset(struct i2c_emul *emul) data = TCS_DATA_FROM_I2C_EMUL(emul); - data->reg[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0xff; - data->reg[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0xff; - data->reg[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x40; + data->reg[TCS_I2C_ENABLE - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG] = 0xff; + data->reg[TCS_I2C_WTIME - TCS_EMUL_FIRST_REG] = 0xff; + data->reg[TCS_I2C_AILTL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_AILTH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_AIHTL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_AIHTH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_PERS - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_CONFIG - TCS_EMUL_FIRST_REG] = 0x40; data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = data->revision; - data->reg[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = data->id; - data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00; - data->reg[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_AUX - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_REVID - TCS_EMUL_FIRST_REG] = data->revision; + data->reg[TCS_I2C_ID - TCS_EMUL_FIRST_REG] = data->id; + data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_CDATAL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_CDATAH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_RDATAL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_RDATAH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_GDATAL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_GDATAH - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_BDATAL - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_BDATAH - TCS_EMUL_FIRST_REG] = 0x00; data->ir_select = false; } @@ -280,7 +280,7 @@ static void tcs_emul_clear_int(struct i2c_emul *emul) data = TCS_DATA_FROM_I2C_EMUL(emul); - data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00; + data->reg[TCS_I2C_STATUS - TCS_EMUL_FIRST_REG] = 0x00; } /** @@ -388,8 +388,8 @@ static int tcs_emul_handle_write(struct i2c_emul *emul, int reg, int bytes) * @return 0 on success * @return -EIO when accessing MSB before LSB */ -static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg, - bool *lsb_read, bool lsb, unsigned int val) +static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg, bool *lsb_read, + bool lsb, unsigned int val) { struct tcs_emul_data *data; uint64_t reg_val; @@ -418,10 +418,10 @@ static int tcs_emul_get_reg_val(struct i2c_emul *emul, int reg, lsb_reg = (reg - TCS_EMUL_FIRST_REG) & ~(0x1); msb_reg = (reg - TCS_EMUL_FIRST_REG) | 0x1; - gain = tcs_emul_get_gain(data->reg[TCS_I2C_CONTROL - - TCS_EMUL_FIRST_REG]); - cycles = tcs_emul_get_cycles(data->reg[TCS_I2C_ATIME - - TCS_EMUL_FIRST_REG]); + gain = tcs_emul_get_gain( + data->reg[TCS_I2C_CONTROL - TCS_EMUL_FIRST_REG]); + cycles = tcs_emul_get_cycles( + data->reg[TCS_I2C_ATIME - TCS_EMUL_FIRST_REG]); /* * Internal value is with 256 cycles and x64 gain, so divide it to get * registers value @@ -487,12 +487,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf, break; case TCS_I2C_RDATAL: /* Shouldn't fail for LSB */ - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, - true, data->red); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, true, + data->red); break; case TCS_I2C_RDATAH: - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, - false, data->red); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_r_read, false, + data->red); if (ret) { LOG_ERR("MSB R read before LSB R"); return -EIO; @@ -500,12 +500,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf, break; case TCS_I2C_GDATAL: /* Shouldn't fail for LSB */ - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, - true, data->green); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, true, + data->green); break; case TCS_I2C_GDATAH: - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, - false, data->green); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_g_read, false, + data->green); if (ret) { LOG_ERR("MSB G read before LSB G"); return -EIO; @@ -513,12 +513,12 @@ static int tcs_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf, break; case TCS_I2C_BDATAL: /* Shouldn't fail for LSB */ - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, - true, data->blue); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, true, + data->blue); break; case TCS_I2C_BDATAH: - ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, - false, data->blue); + ret = tcs_emul_get_reg_val(emul, reg, &data->lsb_b_read, false, + data->blue); if (ret) { LOG_ERR("MSB B read before LSB B"); return -EIO; @@ -577,8 +577,7 @@ static int tcs_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val, * * @return 0 indicating success (always) */ -static int tcs_emul_init(const struct emul *emul, - const struct device *parent) +static int tcs_emul_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = cfg->data; @@ -597,7 +596,7 @@ static int tcs_emul_init(const struct emul *emul, return ret; } -#define TCS3400_EMUL(n) \ +#define TCS3400_EMUL(n) \ static struct tcs_emul_data tcs_emul_data_##n = { \ .revision = DT_INST_PROP(n, revision), \ .id = DT_STRING_TOKEN(DT_DRV_INST(n), device_id), \ @@ -619,27 +618,28 @@ static int tcs_emul_init(const struct emul *emul, .finish_read = NULL, \ .access_reg = NULL, \ }, \ - }; \ - \ - static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .data = &tcs_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(tcs_emul_init, DT_DRV_INST(n), &tcs_emul_cfg_##n, \ + }; \ + \ + static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .data = &tcs_emul_data_##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(tcs_emul_init, DT_DRV_INST(n), &tcs_emul_cfg_##n, \ &tcs_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL) -#define TCS3400_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &tcs_emul_data_##n.common.emul; +#define TCS3400_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &tcs_emul_data_##n.common.emul; /** Check description in emul_tcs3400.h */ struct i2c_emul *tcs_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(TCS3400_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From 9106dcd00e2bb337760cec4a2eb62e2c1c83a47f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:58 -0600 Subject: zephyr/projects/corsola/src/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c11e7e4c085cdc76c70b61a9d61d665a7735e88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730767 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/usb_pd_policy.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c index c9015de776..9f4c4ee5ae 100644 --- a/zephyr/projects/corsola/src/usb_pd_policy.c +++ b/zephyr/projects/corsola/src/usb_pd_policy.c @@ -20,8 +20,8 @@ #error Corsola reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) static int active_aux_port = -1; @@ -78,7 +78,6 @@ void svdm_set_hpd_gpio(int port, int en) } } - __override int svdm_dp_config(int port, uint32_t *payload) { int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); @@ -101,11 +100,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -122,9 +121,9 @@ __override void svdm_dp_post_config(int port) */ if (port == active_aux_port) { usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } dp_flags[port] |= DP_FLAGS_DP_ON; @@ -165,17 +164,14 @@ __override int svdm_dp_attention(int port, uint32_t *payload) if (lvl) { set_dp_aux_path_sel(port); - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) { + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) { /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. -- cgit v1.2.1 From ecc9b5008d381770122c5d8d0a0c85d8ea3e0106 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:07 -0600 Subject: board/servo_v4p1/pi3usb9201.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifadb65c8fab69cfcf88f1f3eb5f33f65a81cb35e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728933 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/pi3usb9201.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/servo_v4p1/pi3usb9201.c b/board/servo_v4p1/pi3usb9201.c index 102eaf790d..bb4a25f135 100644 --- a/board/servo_v4p1/pi3usb9201.c +++ b/board/servo_v4p1/pi3usb9201.c @@ -6,7 +6,7 @@ #include "i2c.h" #include "pi3usb9201.h" -#define PI3USB9201_ADDR 0x5f +#define PI3USB9201_ADDR 0x5f inline void init_pi3usb9201(void) { @@ -19,7 +19,7 @@ inline void init_pi3usb9201(void) } inline void write_pi3usb9201(enum pi3usb9201_reg_t reg, - enum pi3usb9201_dat_t dat) + enum pi3usb9201_dat_t dat) { i2c_write8(1, PI3USB9201_ADDR, reg, dat); } -- cgit v1.2.1 From 03ce80de021c82cdd2b501c8ffc58d182844c433 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:03 -0600 Subject: board/spherion/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I07d185ddcd096be8cf3a7c1b67bcb711c6419e65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728953 Reviewed-by: Jeremy Bettis --- board/spherion/board.h | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/board/spherion/board.h b/board/spherion/board.h index a27258bc94..aa862415a5 100644 --- a/board/spherion/board.h +++ b/board/spherion/board.h @@ -45,7 +45,7 @@ #define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT #define PD_MAX_VOLTAGE_MV 20000 #define PD_OPERATING_POWER_MW 15000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ #undef CONFIG_SYV682X_HV_ILIM #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 @@ -75,18 +75,15 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CHARGER, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_CHARGER, TEMP_SENSOR_COUNT }; enum adc_channel { - ADC_VBUS_C0, /* ADC 0 */ - ADC_BOARD_ID_0, /* ADC 1 */ - ADC_BOARD_ID_1, /* ADC 2 */ - ADC_CHARGER_AMON_R, /* ADC 3 */ - ADC_VBUS_C1, /* ADC 5 */ - ADC_CHARGER_PMON, /* ADC 6 */ + ADC_VBUS_C0, /* ADC 0 */ + ADC_BOARD_ID_0, /* ADC 1 */ + ADC_BOARD_ID_1, /* ADC 2 */ + ADC_CHARGER_AMON_R, /* ADC 3 */ + ADC_VBUS_C1, /* ADC 5 */ + ADC_CHARGER_PMON, /* ADC 6 */ ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */ /* Number of ADC channels */ ADC_CH_COUNT, -- cgit v1.2.1 From ab2e8e26fa3fa3344c50fe6b99b6844ee2cf1288 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:10 -0600 Subject: common/usbc/usb_pd_host.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ee9c5d3d23208f1ef55d828f7f6e0a76170802f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729787 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pd_host.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/common/usbc/usb_pd_host.c b/common/usbc/usb_pd_host.c index 01d0d1bb7f..959995e12d 100644 --- a/common/usbc/usb_pd_host.c +++ b/common/usbc/usb_pd_host.c @@ -15,8 +15,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Retrieve all discovery results for the given port and transmit type */ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args) @@ -35,8 +35,8 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args) if (p->partner_type > TYPEC_PARTNER_SOP_PRIME) return EC_RES_INVALID_PARAM; - type = p->partner_type == TYPEC_PARTNER_SOP ? - TCPCI_MSG_SOP : TCPCI_MSG_SOP_PRIME; + type = p->partner_type == TYPEC_PARTNER_SOP ? TCPCI_MSG_SOP : + TCPCI_MSG_SOP_PRIME; /* * Clear out access mask so we can track if tasks have touched data @@ -61,8 +61,9 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args) if (pd_get_modes_discovery(p->port, type) == PD_DISC_COMPLETE) { int svid_i; - int max_resp_svids = (args->response_max - args->response_size)/ - sizeof(struct svid_mode_info); + int max_resp_svids = + (args->response_max - args->response_size) / + sizeof(struct svid_mode_info); if (disc->svid_cnt > max_resp_svids) { CPRINTS("Warn: SVIDS exceeded HC response"); @@ -74,7 +75,7 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args) for (svid_i = 0; svid_i < r->svid_count; svid_i++) { r->svids[svid_i].svid = disc->svids[svid_i].svid; r->svids[svid_i].mode_count = - disc->svids[svid_i].mode_cnt; + disc->svids[svid_i].mode_cnt; memcpy(r->svids[svid_i].mode_vdo, disc->svids[svid_i].mode_vdo, sizeof(r->svids[svid_i].mode_vdo)); @@ -96,14 +97,12 @@ static enum ec_status hc_typec_discovery(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY, - hc_typec_discovery, +DECLARE_HOST_COMMAND(EC_CMD_TYPEC_DISCOVERY, hc_typec_discovery, EC_VER_MASK(0)); /* Default to feature unavailable, with boards supporting it overriding */ __overridable enum ec_status - board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply) +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) { return EC_RES_UNAVAILABLE; } @@ -134,15 +133,14 @@ static enum ec_status hc_typec_control(struct host_cmd_handler_args *args) if (!IS_ENABLED(CONFIG_USB_MUX_AP_CONTROL)) return EC_RES_INVALID_PARAM; - usb_mux_set_single(p->port, p->mux_params.mux_index, - mode, USB_SWITCH_CONNECT, + usb_mux_set_single(p->port, p->mux_params.mux_index, mode, + USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(p->port))); return EC_RES_SUCCESS; default: return EC_RES_INVALID_PARAM; } - return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_TYPEC_CONTROL, hc_typec_control, EC_VER_MASK(0)); @@ -180,13 +178,15 @@ static enum ec_status hc_typec_status(struct host_cmd_handler_args *args) r->events = pd_get_events(p->port); r->sop_revision = r->sop_connected ? - PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port, TCPCI_MSG_SOP)) : 0; + PD_STATUS_REV_SET_MAJOR( + pd_get_rev(p->port, TCPCI_MSG_SOP)) : + 0; r->sop_prime_revision = pd_get_identity_discovery(p->port, TCPCI_MSG_SOP_PRIME) == - PD_DISC_COMPLETE ? - PD_STATUS_REV_SET_MAJOR(pd_get_rev(p->port, - TCPCI_MSG_SOP_PRIME)) - : 0; + PD_DISC_COMPLETE ? + PD_STATUS_REV_SET_MAJOR( + pd_get_rev(p->port, TCPCI_MSG_SOP_PRIME)) : + 0; r->source_cap_count = pd_get_src_cap_cnt(p->port); memcpy(r->source_cap_pdos, pd_get_src_caps(p->port), -- cgit v1.2.1 From e2b57e9d2aa9480a5bd2faf5c89709ee52c58ba2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:53 -0600 Subject: zephyr/emul/emul_bmi260.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id31d65fed3eb41141c8d519f7a4fd7ad69d5c4e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730688 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_bmi260.c | 366 +++++++++++++++++++++++----------------------- 1 file changed, 180 insertions(+), 186 deletions(-) diff --git a/zephyr/emul/emul_bmi260.c b/zephyr/emul/emul_bmi260.c index 31da71316a..fe7c048728 100644 --- a/zephyr/emul/emul_bmi260.c +++ b/zephyr/emul/emul_bmi260.c @@ -21,100 +21,100 @@ LOG_MODULE_REGISTER(emul_bmi260); /** Mask reserved bits in each register of BMI260 */ static const uint8_t bmi_emul_260_rsvd_mask[] = { - [BMI260_CHIP_ID] = 0x00, - [0x01] = 0xff, /* Reserved */ - [BMI260_ERR_REG] = 0x20, - [BMI260_STATUS] = 0x0b, - [BMI260_AUX_X_L_G] = 0x00, - [BMI260_AUX_X_H_G] = 0x00, - [BMI260_AUX_Y_L_G] = 0x00, - [BMI260_AUX_Y_H_G] = 0x00, - [BMI260_AUX_Z_L_G] = 0x00, - [BMI260_AUX_Z_H_G] = 0x00, - [BMI260_AUX_R_L_G] = 0x00, - [BMI260_AUX_R_H_G] = 0x00, - [BMI260_ACC_X_L_G] = 0x00, - [BMI260_ACC_X_H_G] = 0x00, - [BMI260_ACC_Y_L_G] = 0x00, - [BMI260_ACC_Y_H_G] = 0x00, - [BMI260_ACC_Z_L_G] = 0x00, - [BMI260_ACC_Z_H_G] = 0x00, - [BMI260_GYR_X_L_G] = 0x00, - [BMI260_GYR_X_H_G] = 0x00, - [BMI260_GYR_Y_L_G] = 0x00, - [BMI260_GYR_Y_H_G] = 0x00, - [BMI260_GYR_Z_L_G] = 0x00, - [BMI260_GYR_Z_H_G] = 0x00, - [BMI260_SENSORTIME_0] = 0x00, - [BMI260_SENSORTIME_1] = 0x00, - [BMI260_SENSORTIME_2] = 0x00, - [BMI260_EVENT] = 0xe2, - [BMI260_INT_STATUS_0] = 0x00, - [BMI260_INT_STATUS_1] = 0x18, - [BMI260_SC_OUT_0] = 0x00, - [BMI260_SC_OUT_1] = 0x00, - [BMI260_ORIENT_ACT] = 0xe0, - [BMI260_INTERNAL_STATUS] = 0x00, - [BMI260_TEMPERATURE_0] = 0x00, - [BMI260_TEMPERATURE_1] = 0x00, - [BMI260_FIFO_LENGTH_0] = 0x00, - [BMI260_FIFO_LENGTH_1] = 0xc0, - [BMI160_FIFO_DATA] = 0x00, - [0x27 ... 0x2e] = 0xff, /* Reserved */ - [BMI260_FEAT_PAGE] = 0xf8, - [0x30 ... 0x3f] = 0x00, /* Features */ - [BMI260_ACC_CONF] = 0x00, - [BMI260_ACC_RANGE] = 0xfc, - [BMI260_GYR_CONF] = 0x00, - [BMI260_GYR_RANGE] = 0xf0, - [BMI260_AUX_CONF] = 0x00, - [BMI260_FIFO_DOWNS] = 0x00, - [BMI260_FIFO_WTM_0] = 0x00, - [BMI260_FIFO_WTM_1] = 0xe0, - [BMI260_FIFO_CONFIG_0] = 0xfc, - [BMI260_FIFO_CONFIG_1] = 0x00, - [BMI260_SATURATION] = 0xc0, - [BMI260_AUX_DEV_ID] = 0x01, - [BMI260_AUX_IF_CONF] = 0x30, - [BMI260_AUX_RD_ADDR] = 0x00, - [BMI260_AUX_WR_ADDR] = 0x00, - [BMI260_AUX_WR_DATA] = 0x00, - [0x50 ... 0x51] = 0xff, /* Reserved */ - [BMI260_ERR_REG_MSK] = 0x20, - [BMI260_INT1_IO_CTRL] = 0xe1, - [BMI260_INT2_IO_CTRL] = 0xe1, - [BMI260_INT_LATCH] = 0xfe, - [BMI260_INT1_MAP_FEAT] = 0x00, - [BMI260_INT2_MAP_FEAT] = 0x00, - [BMI260_INT_MAP_DATA] = 0x00, - [BMI260_INIT_CTRL] = 0x00, - [0x5a] = 0xff, /* Reserved */ - [BMI260_INIT_ADDR_0] = 0xf0, - [BMI260_INIT_ADDR_1] = 0x00, - [0x5d] = 0xff, /* Reserved */ - [BMI260_INIT_DATA] = 0x00, - [BMI260_INTERNAL_ERROR] = 0xe9, - [0x60 ... 0x67] = 0xff, /* Reserved */ - [BMI260_AUX_IF_TRIM] = 0xf8, - [BMI260_GYR_CRT_CONF] = 0xf2, - [BMI260_NVM_CONF] = 0xfd, - [BMI260_IF_CONF] = 0xcc, - [BMI260_DRV] = 0x00, - [BMI260_ACC_SELF_TEST] = 0xf2, - [BMI260_GYR_SELF_TEST_AXES] = 0xf0, - [0x6f] = 0xff, /* Reserved */ - [BMI260_NV_CONF] = 0xf0, - [BMI260_OFFSET_ACC70] = 0x00, - [BMI260_OFFSET_ACC70 + 1] = 0x00, - [BMI260_OFFSET_ACC70 + 2] = 0x00, - [BMI260_OFFSET_GYR70] = 0x00, - [BMI260_OFFSET_GYR70 + 1] = 0x00, - [BMI260_OFFSET_GYR70 + 2] = 0x00, - [BMI160_OFFSET_EN_GYR98] = 0x00, - [0x78 ... 0x7b] = 0xff, /* Reserved */ - [BMI260_PWR_CONF] = 0xf8, - [BMI260_PWR_CTRL] = 0xf0, - [BMI260_CMD_REG] = 0x00, + [BMI260_CHIP_ID] = 0x00, + [0x01] = 0xff, /* Reserved */ + [BMI260_ERR_REG] = 0x20, + [BMI260_STATUS] = 0x0b, + [BMI260_AUX_X_L_G] = 0x00, + [BMI260_AUX_X_H_G] = 0x00, + [BMI260_AUX_Y_L_G] = 0x00, + [BMI260_AUX_Y_H_G] = 0x00, + [BMI260_AUX_Z_L_G] = 0x00, + [BMI260_AUX_Z_H_G] = 0x00, + [BMI260_AUX_R_L_G] = 0x00, + [BMI260_AUX_R_H_G] = 0x00, + [BMI260_ACC_X_L_G] = 0x00, + [BMI260_ACC_X_H_G] = 0x00, + [BMI260_ACC_Y_L_G] = 0x00, + [BMI260_ACC_Y_H_G] = 0x00, + [BMI260_ACC_Z_L_G] = 0x00, + [BMI260_ACC_Z_H_G] = 0x00, + [BMI260_GYR_X_L_G] = 0x00, + [BMI260_GYR_X_H_G] = 0x00, + [BMI260_GYR_Y_L_G] = 0x00, + [BMI260_GYR_Y_H_G] = 0x00, + [BMI260_GYR_Z_L_G] = 0x00, + [BMI260_GYR_Z_H_G] = 0x00, + [BMI260_SENSORTIME_0] = 0x00, + [BMI260_SENSORTIME_1] = 0x00, + [BMI260_SENSORTIME_2] = 0x00, + [BMI260_EVENT] = 0xe2, + [BMI260_INT_STATUS_0] = 0x00, + [BMI260_INT_STATUS_1] = 0x18, + [BMI260_SC_OUT_0] = 0x00, + [BMI260_SC_OUT_1] = 0x00, + [BMI260_ORIENT_ACT] = 0xe0, + [BMI260_INTERNAL_STATUS] = 0x00, + [BMI260_TEMPERATURE_0] = 0x00, + [BMI260_TEMPERATURE_1] = 0x00, + [BMI260_FIFO_LENGTH_0] = 0x00, + [BMI260_FIFO_LENGTH_1] = 0xc0, + [BMI160_FIFO_DATA] = 0x00, + [0x27 ... 0x2e] = 0xff, /* Reserved */ + [BMI260_FEAT_PAGE] = 0xf8, + [0x30 ... 0x3f] = 0x00, /* Features */ + [BMI260_ACC_CONF] = 0x00, + [BMI260_ACC_RANGE] = 0xfc, + [BMI260_GYR_CONF] = 0x00, + [BMI260_GYR_RANGE] = 0xf0, + [BMI260_AUX_CONF] = 0x00, + [BMI260_FIFO_DOWNS] = 0x00, + [BMI260_FIFO_WTM_0] = 0x00, + [BMI260_FIFO_WTM_1] = 0xe0, + [BMI260_FIFO_CONFIG_0] = 0xfc, + [BMI260_FIFO_CONFIG_1] = 0x00, + [BMI260_SATURATION] = 0xc0, + [BMI260_AUX_DEV_ID] = 0x01, + [BMI260_AUX_IF_CONF] = 0x30, + [BMI260_AUX_RD_ADDR] = 0x00, + [BMI260_AUX_WR_ADDR] = 0x00, + [BMI260_AUX_WR_DATA] = 0x00, + [0x50 ... 0x51] = 0xff, /* Reserved */ + [BMI260_ERR_REG_MSK] = 0x20, + [BMI260_INT1_IO_CTRL] = 0xe1, + [BMI260_INT2_IO_CTRL] = 0xe1, + [BMI260_INT_LATCH] = 0xfe, + [BMI260_INT1_MAP_FEAT] = 0x00, + [BMI260_INT2_MAP_FEAT] = 0x00, + [BMI260_INT_MAP_DATA] = 0x00, + [BMI260_INIT_CTRL] = 0x00, + [0x5a] = 0xff, /* Reserved */ + [BMI260_INIT_ADDR_0] = 0xf0, + [BMI260_INIT_ADDR_1] = 0x00, + [0x5d] = 0xff, /* Reserved */ + [BMI260_INIT_DATA] = 0x00, + [BMI260_INTERNAL_ERROR] = 0xe9, + [0x60 ... 0x67] = 0xff, /* Reserved */ + [BMI260_AUX_IF_TRIM] = 0xf8, + [BMI260_GYR_CRT_CONF] = 0xf2, + [BMI260_NVM_CONF] = 0xfd, + [BMI260_IF_CONF] = 0xcc, + [BMI260_DRV] = 0x00, + [BMI260_ACC_SELF_TEST] = 0xf2, + [BMI260_GYR_SELF_TEST_AXES] = 0xf0, + [0x6f] = 0xff, /* Reserved */ + [BMI260_NV_CONF] = 0xf0, + [BMI260_OFFSET_ACC70] = 0x00, + [BMI260_OFFSET_ACC70 + 1] = 0x00, + [BMI260_OFFSET_ACC70 + 2] = 0x00, + [BMI260_OFFSET_GYR70] = 0x00, + [BMI260_OFFSET_GYR70 + 1] = 0x00, + [BMI260_OFFSET_GYR70 + 2] = 0x00, + [BMI160_OFFSET_EN_GYR98] = 0x00, + [0x78 ... 0x7b] = 0xff, /* Reserved */ + [BMI260_PWR_CONF] = 0xf8, + [BMI260_PWR_CTRL] = 0xf0, + [BMI260_CMD_REG] = 0x00, }; /** @@ -128,83 +128,83 @@ static void bmi260_emul_reset(uint8_t *regs, struct i2c_emul *emul) bool tag_time; bool header; - regs[BMI260_CHIP_ID] = 0x27; - regs[BMI260_ERR_REG] = 0x00; - regs[BMI260_STATUS] = 0x10; - regs[BMI260_AUX_X_L_G] = 0x00; - regs[BMI260_AUX_X_H_G] = 0x00; - regs[BMI260_AUX_Y_L_G] = 0x00; - regs[BMI260_AUX_Y_H_G] = 0x00; - regs[BMI260_AUX_Z_L_G] = 0x00; - regs[BMI260_AUX_Z_H_G] = 0x00; - regs[BMI260_AUX_R_L_G] = 0x00; - regs[BMI260_AUX_R_H_G] = 0x00; - regs[BMI260_ACC_X_L_G] = 0x00; - regs[BMI260_ACC_X_H_G] = 0x00; - regs[BMI260_ACC_Y_L_G] = 0x00; - regs[BMI260_ACC_Y_H_G] = 0x00; - regs[BMI260_ACC_Z_L_G] = 0x00; - regs[BMI260_ACC_Z_H_G] = 0x00; - regs[BMI260_GYR_X_L_G] = 0x00; - regs[BMI260_GYR_X_H_G] = 0x00; - regs[BMI260_GYR_Y_L_G] = 0x00; - regs[BMI260_GYR_Y_H_G] = 0x00; - regs[BMI260_GYR_Z_L_G] = 0x00; - regs[BMI260_GYR_Z_H_G] = 0x00; - regs[BMI260_SENSORTIME_0] = 0x00; - regs[BMI260_SENSORTIME_1] = 0x00; - regs[BMI260_SENSORTIME_2] = 0x00; - regs[BMI260_EVENT] = 0x01; - regs[BMI260_INT_STATUS_0] = 0x00; - regs[BMI260_INT_STATUS_1] = 0x00; - regs[BMI260_SC_OUT_0] = 0x00; - regs[BMI260_SC_OUT_1] = 0x00; - regs[BMI260_ORIENT_ACT] = 0x00; - regs[BMI260_INTERNAL_STATUS] = 0x00; - regs[BMI260_TEMPERATURE_0] = 0x00; - regs[BMI260_TEMPERATURE_1] = 0x80; - regs[BMI260_FIFO_LENGTH_0] = 0x00; - regs[BMI260_FIFO_LENGTH_1] = 0x00; - regs[BMI160_FIFO_DATA] = 0x00; - regs[BMI260_FEAT_PAGE] = 0x00; - regs[BMI260_ACC_CONF] = 0xa8; - regs[BMI260_ACC_RANGE] = 0x02; - regs[BMI260_GYR_CONF] = 0xa9; - regs[BMI260_GYR_RANGE] = 0x00; - regs[BMI260_AUX_CONF] = 0x46; - regs[BMI260_FIFO_DOWNS] = 0x88; - regs[BMI260_FIFO_WTM_0] = 0x00; - regs[BMI260_FIFO_WTM_1] = 0x02; - regs[BMI260_FIFO_CONFIG_0] = 0x02; - regs[BMI260_FIFO_CONFIG_1] = 0x10; - regs[BMI260_SATURATION] = 0x00; - regs[BMI260_AUX_DEV_ID] = 0x20; - regs[BMI260_AUX_IF_CONF] = 0x83; - regs[BMI260_AUX_RD_ADDR] = 0x42; - regs[BMI260_AUX_WR_ADDR] = 0x4c; - regs[BMI260_AUX_WR_DATA] = 0x02; - regs[BMI260_ERR_REG_MSK] = 0x00; - regs[BMI260_INT1_IO_CTRL] = 0x00; - regs[BMI260_INT2_IO_CTRL] = 0x00; - regs[BMI260_INT_LATCH] = 0x00; - regs[BMI260_INT1_MAP_FEAT] = 0x00; - regs[BMI260_INT2_MAP_FEAT] = 0x00; - regs[BMI260_INT_MAP_DATA] = 0x00; - regs[BMI260_INIT_CTRL] = 0x00; - regs[BMI260_INIT_ADDR_0] = 0x00; - regs[BMI260_INIT_ADDR_1] = 0x00; - regs[BMI260_INIT_DATA] = 0x00; - regs[BMI260_INTERNAL_ERROR] = 0x00; - regs[BMI260_AUX_IF_TRIM] = 0x01; - regs[BMI260_GYR_CRT_CONF] = 0x00; - regs[BMI260_NVM_CONF] = 0x00; - regs[BMI260_IF_CONF] = 0x00; - regs[BMI260_DRV] = 0xff; - regs[BMI260_ACC_SELF_TEST] = 0x00; - regs[BMI260_GYR_SELF_TEST_AXES] = 0x00; - regs[BMI260_PWR_CONF] = 0x03; - regs[BMI260_PWR_CTRL] = 0x00; - regs[BMI260_CMD_REG] = 0x00; + regs[BMI260_CHIP_ID] = 0x27; + regs[BMI260_ERR_REG] = 0x00; + regs[BMI260_STATUS] = 0x10; + regs[BMI260_AUX_X_L_G] = 0x00; + regs[BMI260_AUX_X_H_G] = 0x00; + regs[BMI260_AUX_Y_L_G] = 0x00; + regs[BMI260_AUX_Y_H_G] = 0x00; + regs[BMI260_AUX_Z_L_G] = 0x00; + regs[BMI260_AUX_Z_H_G] = 0x00; + regs[BMI260_AUX_R_L_G] = 0x00; + regs[BMI260_AUX_R_H_G] = 0x00; + regs[BMI260_ACC_X_L_G] = 0x00; + regs[BMI260_ACC_X_H_G] = 0x00; + regs[BMI260_ACC_Y_L_G] = 0x00; + regs[BMI260_ACC_Y_H_G] = 0x00; + regs[BMI260_ACC_Z_L_G] = 0x00; + regs[BMI260_ACC_Z_H_G] = 0x00; + regs[BMI260_GYR_X_L_G] = 0x00; + regs[BMI260_GYR_X_H_G] = 0x00; + regs[BMI260_GYR_Y_L_G] = 0x00; + regs[BMI260_GYR_Y_H_G] = 0x00; + regs[BMI260_GYR_Z_L_G] = 0x00; + regs[BMI260_GYR_Z_H_G] = 0x00; + regs[BMI260_SENSORTIME_0] = 0x00; + regs[BMI260_SENSORTIME_1] = 0x00; + regs[BMI260_SENSORTIME_2] = 0x00; + regs[BMI260_EVENT] = 0x01; + regs[BMI260_INT_STATUS_0] = 0x00; + regs[BMI260_INT_STATUS_1] = 0x00; + regs[BMI260_SC_OUT_0] = 0x00; + regs[BMI260_SC_OUT_1] = 0x00; + regs[BMI260_ORIENT_ACT] = 0x00; + regs[BMI260_INTERNAL_STATUS] = 0x00; + regs[BMI260_TEMPERATURE_0] = 0x00; + regs[BMI260_TEMPERATURE_1] = 0x80; + regs[BMI260_FIFO_LENGTH_0] = 0x00; + regs[BMI260_FIFO_LENGTH_1] = 0x00; + regs[BMI160_FIFO_DATA] = 0x00; + regs[BMI260_FEAT_PAGE] = 0x00; + regs[BMI260_ACC_CONF] = 0xa8; + regs[BMI260_ACC_RANGE] = 0x02; + regs[BMI260_GYR_CONF] = 0xa9; + regs[BMI260_GYR_RANGE] = 0x00; + regs[BMI260_AUX_CONF] = 0x46; + regs[BMI260_FIFO_DOWNS] = 0x88; + regs[BMI260_FIFO_WTM_0] = 0x00; + regs[BMI260_FIFO_WTM_1] = 0x02; + regs[BMI260_FIFO_CONFIG_0] = 0x02; + regs[BMI260_FIFO_CONFIG_1] = 0x10; + regs[BMI260_SATURATION] = 0x00; + regs[BMI260_AUX_DEV_ID] = 0x20; + regs[BMI260_AUX_IF_CONF] = 0x83; + regs[BMI260_AUX_RD_ADDR] = 0x42; + regs[BMI260_AUX_WR_ADDR] = 0x4c; + regs[BMI260_AUX_WR_DATA] = 0x02; + regs[BMI260_ERR_REG_MSK] = 0x00; + regs[BMI260_INT1_IO_CTRL] = 0x00; + regs[BMI260_INT2_IO_CTRL] = 0x00; + regs[BMI260_INT_LATCH] = 0x00; + regs[BMI260_INT1_MAP_FEAT] = 0x00; + regs[BMI260_INT2_MAP_FEAT] = 0x00; + regs[BMI260_INT_MAP_DATA] = 0x00; + regs[BMI260_INIT_CTRL] = 0x00; + regs[BMI260_INIT_ADDR_0] = 0x00; + regs[BMI260_INIT_ADDR_1] = 0x00; + regs[BMI260_INIT_DATA] = 0x00; + regs[BMI260_INTERNAL_ERROR] = 0x00; + regs[BMI260_AUX_IF_TRIM] = 0x01; + regs[BMI260_GYR_CRT_CONF] = 0x00; + regs[BMI260_NVM_CONF] = 0x00; + regs[BMI260_IF_CONF] = 0x00; + regs[BMI260_DRV] = 0xff; + regs[BMI260_ACC_SELF_TEST] = 0x00; + regs[BMI260_GYR_SELF_TEST_AXES] = 0x00; + regs[BMI260_PWR_CONF] = 0x03; + regs[BMI260_PWR_CTRL] = 0x00; + regs[BMI260_CMD_REG] = 0x00; /* Call generic reset */ tag_time = regs[BMI260_FIFO_CONFIG_0] & BMI260_FIFO_TIME_EN; @@ -354,8 +354,7 @@ static int bmi260_emul_access_reg(struct i2c_emul *emul, int reg, int byte, */ if (reg <= BMI260_FIFO_DATA && reg + byte >= BMI260_FIFO_DATA) { return BMI260_FIFO_DATA; - } else if (reg <= BMI260_INIT_DATA && - reg + byte >= BMI260_INIT_DATA) { + } else if (reg <= BMI260_INIT_DATA && reg + byte >= BMI260_INIT_DATA) { return BMI260_INIT_DATA; } @@ -395,7 +394,6 @@ static int bmi260_emul_handle_write(uint8_t *regs, struct i2c_emul *emul, return BMI_EMUL_ACCESS_E; } - /* Stop on going command if required */ if (regs[BMI260_CMD_REG] != 0 && bmi_emul_is_cmd_end(emul)) { bmi260_emul_end_cmd(regs, emul); @@ -513,8 +511,8 @@ static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul, bmi_emul_state_to_reg(emul, acc_shift, gyr_shift, BMI260_ACC_X_L_G, BMI260_GYR_X_L_G, - BMI260_SENSORTIME_0, - acc_off_en, gyr_off_en); + BMI260_SENSORTIME_0, acc_off_en, + gyr_off_en); } break; case BMI260_FIFO_LENGTH_0: @@ -538,16 +536,12 @@ static int bmi260_emul_handle_read(uint8_t *regs, struct i2c_emul *emul, } /** Registers backed in NVM by BMI260 */ -const int bmi260_nvm_reg[] = {BMI260_AUX_IF_TRIM, - BMI260_NV_CONF, - BMI260_DRV, - BMI260_OFFSET_ACC70, - BMI260_OFFSET_ACC70 + 1, - BMI260_OFFSET_ACC70 + 2, - BMI260_OFFSET_GYR70, - BMI260_OFFSET_GYR70 + 1, - BMI260_OFFSET_GYR70 + 2, - BMI260_OFFSET_EN_GYR98}; +const int bmi260_nvm_reg[] = { + BMI260_AUX_IF_TRIM, BMI260_NV_CONF, BMI260_DRV, + BMI260_OFFSET_ACC70, BMI260_OFFSET_ACC70 + 1, BMI260_OFFSET_ACC70 + 2, + BMI260_OFFSET_GYR70, BMI260_OFFSET_GYR70 + 1, BMI260_OFFSET_GYR70 + 2, + BMI260_OFFSET_EN_GYR98 +}; /** Confguration of BMI260 */ struct bmi_emul_type_data bmi260_emul = { -- cgit v1.2.1 From 95b64ff6e42cdb4201269c57396ca68093d6e9b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:11 -0600 Subject: zephyr/projects/nissa/src/nivviks/form_factor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia5d93a34de3519ab9c35afeed001644318094972 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730792 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nivviks/form_factor.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/nissa/src/nivviks/form_factor.c b/zephyr/projects/nissa/src/nivviks/form_factor.c index 16132e4a6c..018ed2b959 100644 --- a/zephyr/projects/nissa/src/nivviks/form_factor.c +++ b/zephyr/projects/nissa/src/nivviks/form_factor.c @@ -19,9 +19,9 @@ LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); * Mainboard orientation support. */ -#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted)) -#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) -#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) +#define ALT_MAT SENSOR_ROT_STD_REF_NAME(DT_NODELABEL(base_rot_inverted)) +#define BASE_SENSOR SENSOR_ID(DT_NODELABEL(base_accel)) +#define BASE_GYRO SENSOR_ID(DT_NODELABEL(base_gyro)) static void form_factor_init(void) { -- cgit v1.2.1 From 1061c6d2a91c64ee503feeb79b4f392d48fbea72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:53 -0600 Subject: zephyr/subsys/ap_pwrseq/signal_adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6399779bf537b3b72f43ad47f258e9a6ea44d61f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730967 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/signal_adc.c | 102 ++++++++++++++--------------------- 1 file changed, 41 insertions(+), 61 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/signal_adc.c b/zephyr/subsys/ap_pwrseq/signal_adc.c index eab01f2830..03c0b7c848 100644 --- a/zephyr/subsys/ap_pwrseq/signal_adc.c +++ b/zephyr/subsys/ap_pwrseq/signal_adc.c @@ -11,7 +11,7 @@ #include #include -#define MY_COMPAT intel_ap_pwrseq_adc +#define MY_COMPAT intel_ap_pwrseq_adc #if HAS_ADC_SIGNALS @@ -26,74 +26,59 @@ struct adc_config { enum power_signal signal; }; -#define ADC_HIGH_DEV(id) DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(id)) +#define ADC_HIGH_DEV(id) DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(id)) -#define ADC_HIGH_CHAN(id) DT_IO_CHANNELS_INPUT(id) +#define ADC_HIGH_CHAN(id) DT_IO_CHANNELS_INPUT(id) -#define ADC_THRESH(id) DT_PROP(id, threshold_mv) +#define ADC_THRESH(id) DT_PROP(id, threshold_mv) -#define INIT_ADC_CONFIG(id) \ -{ \ - .dev_trig_high = DEVICE_DT_GET(DT_PHANDLE(id, trigger_high)), \ - .dev_trig_low = DEVICE_DT_GET(DT_PHANDLE(id, trigger_low)), \ - .adc_dev = ADC_HIGH_DEV(DT_PHANDLE(id, trigger_high)), \ - .adc_ch = ADC_HIGH_CHAN(DT_PHANDLE(id, trigger_high)), \ - .threshold = ADC_THRESH(DT_PHANDLE(id, trigger_high)), \ - .signal = PWR_SIGNAL_ENUM(id), \ -}, +#define INIT_ADC_CONFIG(id) \ + { \ + .dev_trig_high = DEVICE_DT_GET(DT_PHANDLE(id, trigger_high)), \ + .dev_trig_low = DEVICE_DT_GET(DT_PHANDLE(id, trigger_low)), \ + .adc_dev = ADC_HIGH_DEV(DT_PHANDLE(id, trigger_high)), \ + .adc_ch = ADC_HIGH_CHAN(DT_PHANDLE(id, trigger_high)), \ + .threshold = ADC_THRESH(DT_PHANDLE(id, trigger_high)), \ + .signal = PWR_SIGNAL_ENUM(id), \ + }, -static const struct adc_config config[] = { -DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_ADC_CONFIG) -}; +static const struct adc_config config[] = { DT_FOREACH_STATUS_OKAY( + MY_COMPAT, INIT_ADC_CONFIG) }; /* * Bit allocations for atomic state */ -enum { - ADC_BIT_VALUE = 0, - ADC_BIT_LOW_ENABLED = 1, - ADC_BIT_HIGH_ENABLED = 2 -}; +enum { ADC_BIT_VALUE = 0, ADC_BIT_LOW_ENABLED = 1, ADC_BIT_HIGH_ENABLED = 2 }; atomic_t adc_state[ARRAY_SIZE(config)]; -static void set_trigger(const struct device *dev, - atomic_t *state, - int bit, +static void set_trigger(const struct device *dev, atomic_t *state, int bit, bool enable) { /* * Only enable or disable if the trigger is not * already enabled or disabled. */ - if (enable - ? !atomic_test_and_set_bit(state, bit) - : atomic_test_and_clear_bit(state, bit)) { + if (enable ? !atomic_test_and_set_bit(state, bit) : + atomic_test_and_clear_bit(state, bit)) { struct sensor_value val; val.val1 = enable; - sensor_attr_set(dev, - SENSOR_CHAN_VOLTAGE, - SENSOR_ATTR_ALERT, + sensor_attr_set(dev, SENSOR_CHAN_VOLTAGE, SENSOR_ATTR_ALERT, &val); } } static void set_low_trigger(enum pwr_sig_adc adc, bool enable) { - set_trigger(config[adc].dev_trig_low, - &adc_state[adc], - ADC_BIT_LOW_ENABLED, - enable); - + set_trigger(config[adc].dev_trig_low, &adc_state[adc], + ADC_BIT_LOW_ENABLED, enable); } static void set_high_trigger(enum pwr_sig_adc adc, bool enable) { - set_trigger(config[adc].dev_trig_high, - &adc_state[adc], - ADC_BIT_HIGH_ENABLED, - enable); + set_trigger(config[adc].dev_trig_high, &adc_state[adc], + ADC_BIT_HIGH_ENABLED, enable); } static void trigger_high(enum pwr_sig_adc adc) @@ -156,32 +141,28 @@ int power_signal_adc_disable(enum pwr_sig_adc adc) #define PWR_ADC_ENUM(id) TAG_ADC(PWR_SIG_TAG_ADC, PWR_SIGNAL_ENUM(id)) -#define ADC_CB(id, lev) cb_##lev##_##id +#define ADC_CB(id, lev) cb_##lev##_##id -#define ADC_CB_DEFINE(id, lev) \ -static void ADC_CB(id, lev)(const struct device *dev, \ - const struct sensor_trigger *trigger) \ -{ \ - trigger_##lev(PWR_ADC_ENUM(id)); \ -} +#define ADC_CB_DEFINE(id, lev) \ + static void ADC_CB(id, lev)(const struct device *dev, \ + const struct sensor_trigger *trigger) \ + { \ + trigger_##lev(PWR_ADC_ENUM(id)); \ + } DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_DEFINE, high) DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_DEFINE, low) -#define ADC_CB_COMMA(id, lev) ADC_CB(id, lev), +#define ADC_CB_COMMA(id, lev) ADC_CB(id, lev), void power_signal_adc_init(void) { - struct sensor_trigger trig = { - .type = SENSOR_TRIG_THRESHOLD, - .chan = SENSOR_CHAN_VOLTAGE - }; - sensor_trigger_handler_t low_cb[] = { - DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_COMMA, low) - }; - sensor_trigger_handler_t high_cb[] = { - DT_FOREACH_STATUS_OKAY_VARGS(MY_COMPAT, ADC_CB_COMMA, high) - }; + struct sensor_trigger trig = { .type = SENSOR_TRIG_THRESHOLD, + .chan = SENSOR_CHAN_VOLTAGE }; + sensor_trigger_handler_t low_cb[] = { DT_FOREACH_STATUS_OKAY_VARGS( + MY_COMPAT, ADC_CB_COMMA, low) }; + sensor_trigger_handler_t high_cb[] = { DT_FOREACH_STATUS_OKAY_VARGS( + MY_COMPAT, ADC_CB_COMMA, high) }; int i, rv; int32_t val = 0; @@ -202,11 +183,10 @@ void power_signal_adc_init(void) rv = adc_read(dev, &seq); if (rv) { - LOG_ERR("ADC %s:%d initial read failed", - dev->name, config[i].adc_ch); + LOG_ERR("ADC %s:%d initial read failed", dev->name, + config[i].adc_ch); } else { - adc_raw_to_millivolts(adc_ref_internal(dev), - ADC_GAIN_1, + adc_raw_to_millivolts(adc_ref_internal(dev), ADC_GAIN_1, CONFIG_PLATFORM_EC_ADC_RESOLUTION, &val); if (val >= config[i].threshold) { -- cgit v1.2.1 From 81ea405d3cfe8e6a9d027866a7e9372c354f4d57 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:59 -0600 Subject: test/usb_pd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0b30969e7192f2cee43d88b636e35d9564f9ed4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730549 Reviewed-by: Jeremy Bettis --- test/usb_pd.c | 205 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 108 insertions(+), 97 deletions(-) diff --git a/test/usb_pd.c b/test/usb_pd.c index 9fdb439b49..f68f5d98c1 100644 --- a/test/usb_pd.c +++ b/test/usb_pd.c @@ -14,8 +14,8 @@ #include "usb_pd_test_util.h" #include "util.h" -#define PORT0 0 -#define PORT1 1 +#define PORT0 0 +#define PORT1 1 #define BATTERY_DESIGN_VOLTAGE 7600 #define BATTERY_DESIGN_CAPACITY 5131 @@ -87,7 +87,7 @@ int pd_adc_read(int port, int cc) /* we are source connected to sink, return Rd/Open */ return (pd_port[port].partner_polarity == cc) ? 400 : 3000; else if (!pd_port[port].host_mode && - pd_port[port].partner_role == PD_ROLE_SOURCE) + pd_port[port].partner_role == PD_ROLE_SOURCE) /* we are sink connected to source, return Rp/Open */ return (pd_port[port].partner_polarity == cc) ? 1700 : 0; else if (pd_port[port].host_mode) @@ -179,39 +179,38 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt, static void simulate_wait(int port) { - uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + uint16_t header = PD_HEADER(PD_CTRL_WAIT, PD_ROLE_SOURCE, PD_ROLE_DFP, + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); } static void simulate_accept(int port) { - uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + uint16_t header = PD_HEADER(PD_CTRL_ACCEPT, PD_ROLE_SOURCE, PD_ROLE_DFP, + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); } static void simulate_reject(int port) { - uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + uint16_t header = PD_HEADER(PD_CTRL_REJECT, PD_ROLE_SOURCE, PD_ROLE_DFP, + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); } - #ifdef CONFIG_USB_PD_REV30 static void simulate_get_bat_cap(int port) { uint16_t msg[2]; uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_CAP, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 1, pd_port[port].rev, 1); + PD_ROLE_DFP, pd_port[port].msg_rx_id, 1, + pd_port[port].rev, 1); /* set extended header */ msg[0] = PD_EXT_HEADER(0, 0, 1); @@ -226,8 +225,8 @@ static void simulate_get_bat_status(int port) { uint16_t msg[2]; uint16_t header = PD_HEADER(PD_EXT_GET_BATTERY_STATUS, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 1, pd_port[port].rev, 1); + PD_ROLE_DFP, pd_port[port].msg_rx_id, 1, + pd_port[port].rev, 1); /* set extended header */ msg[0] = PD_EXT_HEADER(0, 0, 1); @@ -252,18 +251,20 @@ static void simulate_source_cap(int port, uint32_t cnt) static void simulate_goodcrc(int port, int role, int id) { - simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, - pd_port[port].rev, 0), 0, NULL); + simulate_rx_msg(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, + pd_port[port].rev, 0), + 0, NULL); } static int verify_goodcrc(int port, int role, int id) { - return pd_test_tx_msg_verify_sop(port) && - pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC, - role, role, id, 0, 0, 0)) && - pd_test_tx_msg_verify_crc(port) && - pd_test_tx_msg_verify_eop(port); + pd_test_tx_msg_verify_short(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, + role, id, 0, 0, 0)) && + pd_test_tx_msg_verify_crc(port) && + pd_test_tx_msg_verify_eop(port); } static void plug_in_source(int port, int polarity) @@ -296,7 +297,7 @@ static void unplug(int port) usleep(30 * MSEC); } -void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv) +void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv) { if (*ma == 3000) give_back_called = 1; @@ -304,9 +305,9 @@ void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv) static void simulate_ps_rdy(int port) { - uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + uint16_t header = PD_HEADER(PD_CTRL_PS_RDY, PD_ROLE_SOURCE, PD_ROLE_DFP, + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); } @@ -314,7 +315,8 @@ static void simulate_ps_rdy(int port) static void simulate_goto_min(int port) { uint16_t header = PD_HEADER(PD_CTRL_GOTO_MIN, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_rx_id, 0, pd_port[port].rev, 0); + PD_ROLE_DFP, pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); } @@ -324,8 +326,9 @@ static int test_request_with_wait_and_contract(void) #ifdef CONFIG_USB_PD_REV30 uint32_t expected_status_bsdo = BSDO_CAP(DIV_ROUND_NEAREST(BATTERY_REMAINING_CAPACITY * - BATTERY_DESIGN_VOLTAGE, 100000)) | - BSDO_PRESENT; + BATTERY_DESIGN_VOLTAGE, + 100000)) | + BSDO_PRESENT; uint16_t expected_cap_hdr = PD_EXT_HEADER(0, 0, 9); uint16_t expected_cap_vid = USB_VID_GOOGLE; #ifdef CONFIG_USB_PID @@ -333,12 +336,10 @@ static int test_request_with_wait_and_contract(void) #else uint16_t expected_cap_pid = 0; #endif - uint16_t expected_cap_des = - DIV_ROUND_NEAREST(BATTERY_DESIGN_CAPACITY * - BATTERY_DESIGN_VOLTAGE, 100000); - uint16_t expected_cap_ful = - DIV_ROUND_NEAREST(BATTERY_FULL_CHARGE_CAPACITY * - BATTERY_DESIGN_VOLTAGE, 100000); + uint16_t expected_cap_des = DIV_ROUND_NEAREST( + BATTERY_DESIGN_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000); + uint16_t expected_cap_ful = DIV_ROUND_NEAREST( + BATTERY_FULL_CHARGE_CAPACITY * BATTERY_DESIGN_VOLTAGE, 100000); uint16_t expected_cap_type = 0; #endif @@ -358,8 +359,8 @@ static int test_request_with_wait_and_contract(void) /* We're in SNK_DISCOVERY now. Let's send the source cap. */ simulate_source_cap(port, 1); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK, - pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -368,9 +369,10 @@ static int test_request_with_wait_and_contract(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -399,8 +401,8 @@ static int test_request_with_wait_and_contract(void) */ simulate_source_cap(port, 1); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, PD_ROLE_SINK, - pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -409,9 +411,10 @@ static int test_request_with_wait_and_contract(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -441,11 +444,10 @@ static int test_request_with_wait_and_contract(void) /* We had an explicit contract. So request should have been resent. */ /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, - pd_port[port].rev, 0 - ))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -492,9 +494,10 @@ static int test_request_with_wait_and_contract(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, PD_HEADER(PD_EXT_BATTERY_CAP, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1))); + pd_port[port].msg_tx_id, 3, pd_port[port].rev, 1))); TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_hdr)); TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_vid)); TEST_ASSERT(pd_test_tx_msg_verify_short(port, expected_cap_pid)); @@ -524,9 +527,10 @@ static int test_request_with_wait_and_contract(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_status_bsdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -564,7 +568,7 @@ static int test_request_with_wait(void) { #ifdef CONFIG_USB_PD_GIVE_BACK uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA, - RDO_CAP_MISMATCH | RDO_GIVE_BACK); + RDO_CAP_MISMATCH | RDO_GIVE_BACK); #else uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH); #endif @@ -578,8 +582,8 @@ static int test_request_with_wait(void) /* We're in SNK_DISCOVERY now. Let's send the source cap. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -588,9 +592,10 @@ static int test_request_with_wait(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -617,8 +622,8 @@ static int test_request_with_wait(void) /* Resend Source Cap. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -627,9 +632,10 @@ static int test_request_with_wait(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -652,7 +658,7 @@ static int test_request_with_wait_no_src_cap(void) { #ifdef CONFIG_USB_PD_GIVE_BACK uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA, - RDO_CAP_MISMATCH | RDO_GIVE_BACK); + RDO_CAP_MISMATCH | RDO_GIVE_BACK); #else uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH); #endif @@ -666,8 +672,8 @@ static int test_request_with_wait_no_src_cap(void) /* We're in SNK_DISCOVERY now. Let's send the source cap. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -676,9 +682,10 @@ static int test_request_with_wait_no_src_cap(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -711,9 +718,10 @@ static int test_request_with_wait_no_src_cap(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -736,7 +744,7 @@ static int test_request_with_reject(void) { #ifdef CONFIG_USB_PD_GIVE_BACK uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA, - RDO_CAP_MISMATCH | RDO_GIVE_BACK); + RDO_CAP_MISMATCH | RDO_GIVE_BACK); #else uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH); #endif @@ -750,8 +758,8 @@ static int test_request_with_reject(void) /* We're in SNK_DISCOVERY now. Let's send the source cap. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -760,9 +768,10 @@ static int test_request_with_reject(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -788,8 +797,8 @@ static int test_request_with_reject(void) /* We're in SNK_READY. Send source cap. again. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -798,9 +807,10 @@ static int test_request_with_reject(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -814,7 +824,7 @@ static int test_request(void) { #ifdef CONFIG_USB_PD_GIVE_BACK uint32_t expected_rdo = RDO_FIXED(1, 900, PD_MIN_CURRENT_MA, - RDO_CAP_MISMATCH | RDO_GIVE_BACK); + RDO_CAP_MISMATCH | RDO_GIVE_BACK); #else uint32_t expected_rdo = RDO_FIXED(1, 900, 900, RDO_CAP_MISMATCH); #endif @@ -828,8 +838,8 @@ static int test_request(void) /* We're in SNK_DISCOVERY now. Let's send the source cap. */ simulate_source_cap(port, 0); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); /* Wait for the power request */ task_wake(PD_PORT_TO_TASK_ID(port)); @@ -838,9 +848,10 @@ static int test_request(void) /* Process the request */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, - pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + pd_port[port].msg_tx_id, 1, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_rdo)); TEST_ASSERT(pd_test_tx_msg_verify_crc(port)); TEST_ASSERT(pd_test_tx_msg_verify_eop(port)); @@ -872,10 +883,10 @@ static int test_sink(void) /* The source cap should be sent */ TEST_ASSERT(pd_test_tx_msg_verify_sop(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE, - PD_ROLE_DFP, pd_port[port].msg_tx_id, - pd_src_pdo_cnt, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, PD_HEADER(PD_DATA_SOURCE_CAP, PD_ROLE_SOURCE, PD_ROLE_DFP, + pd_port[port].msg_tx_id, pd_src_pdo_cnt, + pd_port[port].rev, 0))); for (i = 0; i < pd_src_pdo_cnt; ++i) TEST_ASSERT(pd_test_tx_msg_verify_word(port, pd_src_pdo[i])); -- cgit v1.2.1 From 0d7a079275a5582206666100a1fa15397f1a6900 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:51 -0600 Subject: board/kinox/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16a4d7d620b62fee35ba6d00143aacc5f7b9a7ce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728534 Reviewed-by: Jeremy Bettis --- board/kinox/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kinox/fans.c b/board/kinox/fans.c index a82a61648d..4c5dbfc8c1 100644 --- a/board/kinox/fans.c +++ b/board/kinox/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP12000_FAN, }; -- cgit v1.2.1 From faf897bf7b723b768b9ec1915fcdd24a9256036e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:01 -0600 Subject: chip/stm32/ucpd-stm32gx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55e2b3736d1baf9c80c6d03f457c9f8c3c03c25c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729539 Reviewed-by: Jeremy Bettis --- chip/stm32/ucpd-stm32gx.h | 69 +++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 42 deletions(-) diff --git a/chip/stm32/ucpd-stm32gx.h b/chip/stm32/ucpd-stm32gx.h index d3af41e5bc..c8c040b163 100644 --- a/chip/stm32/ucpd-stm32gx.h +++ b/chip/stm32/ucpd-stm32gx.h @@ -37,7 +37,6 @@ #define UCPD_TRANSWIN_CNT 8 #define UCPD_IFRGAP_CNT 17 - /* * K-codes and ordered set defines. These codes and sets are used to encode * which type of USB-PD message is being sent. This information can be found in @@ -47,48 +46,36 @@ #define UCPD_SYNC1 0x18u #define UCPD_SYNC2 0x11u #define UCPD_SYNC3 0x06u -#define UCPD_RST1 0x07u -#define UCPD_RST2 0x19u -#define UCPD_EOP 0x0Du +#define UCPD_RST1 0x07u +#define UCPD_RST2 0x19u +#define UCPD_EOP 0x0Du /* This order of this enum matches tcpm_sop_type */ enum ucpd_tx_ordset { - TX_ORDERSET_SOP = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC1<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME = (UCPD_SYNC1 | - (UCPD_SYNC3<<5u) | - (UCPD_SYNC1<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_RST2<<10u) | - (UCPD_SYNC3<<15u)), - - TX_ORDERSET_SOP_PRIME_PRIME_DEBUG = (UCPD_SYNC1 | - (UCPD_RST2<<5u) | - (UCPD_SYNC3<<10u) | - (UCPD_SYNC2<<15u)), - - TX_ORDERSET_HARD_RESET = (UCPD_RST1 | - (UCPD_RST1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_RST2<<15u)), - - TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | - (UCPD_SYNC1<<5u) | - (UCPD_RST1<<10u) | - (UCPD_SYNC3<<15u)), -}; + TX_ORDERSET_SOP = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) | + (UCPD_SYNC1 << 10u) | (UCPD_SYNC2 << 15u)), + + TX_ORDERSET_SOP_PRIME = (UCPD_SYNC1 | (UCPD_SYNC1 << 5u) | + (UCPD_SYNC3 << 10u) | (UCPD_SYNC3 << 15u)), + + TX_ORDERSET_SOP_PRIME_PRIME = + (UCPD_SYNC1 | (UCPD_SYNC3 << 5u) | (UCPD_SYNC1 << 10u) | + (UCPD_SYNC3 << 15u)), + TX_ORDERSET_SOP_PRIME_DEBUG = + (UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_RST2 << 10u) | + (UCPD_SYNC3 << 15u)), + + TX_ORDERSET_SOP_PRIME_PRIME_DEBUG = + (UCPD_SYNC1 | (UCPD_RST2 << 5u) | (UCPD_SYNC3 << 10u) | + (UCPD_SYNC2 << 15u)), + + TX_ORDERSET_HARD_RESET = (UCPD_RST1 | (UCPD_RST1 << 5u) | + (UCPD_RST1 << 10u) | (UCPD_RST2 << 15u)), + + TX_ORDERSET_CABLE_RESET = (UCPD_RST1 | (UCPD_SYNC1 << 5u) | + (UCPD_RST1 << 10u) | (UCPD_SYNC3 << 15u)), +}; /** * STM32Gx UCPD implementation of tcpci .init method @@ -172,9 +159,7 @@ int stm32gx_ucpd_set_msg_header(int port, int power_role, int data_role); * @param *data -> pointer to message contents * @return EC_SUCCESS */ -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, +int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header, const uint32_t *data); /** -- cgit v1.2.1 From a8091d2bf2aa5991a7fe2fafdf9cb2b8b56dfaba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:12 -0600 Subject: common/gpio_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I72076574b721b72560690e5aec3279300bebe697 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729652 Reviewed-by: Jeremy Bettis --- common/gpio_commands.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/common/gpio_commands.c b/common/gpio_commands.c index 758a0ad8dc..eb80720f48 100644 --- a/common/gpio_commands.c +++ b/common/gpio_commands.c @@ -83,23 +83,18 @@ static enum ec_error_list set(const char *name, int value) /* Console commands */ struct gpio_flag_description { - const int bitfield; - const char* name; + const int bitfield; + const char *name; }; __maybe_unused static const struct gpio_flag_description gpio_descriptions[] = { - {GPIO_INPUT, "I"}, - {GPIO_OUTPUT, "O"}, - {GPIO_LOW, "L"}, - {GPIO_HIGH, "H"}, - {GPIO_OPEN_DRAIN, "ODR"}, - {GPIO_PULL_UP, "PU"}, - {GPIO_PULL_DOWN, "PD"}, - {GPIO_SEL_1P8V, "1P8"}, + { GPIO_INPUT, "I" }, { GPIO_OUTPUT, "O" }, + { GPIO_LOW, "L" }, { GPIO_HIGH, "H" }, + { GPIO_OPEN_DRAIN, "ODR" }, { GPIO_PULL_UP, "PU" }, + { GPIO_PULL_DOWN, "PD" }, { GPIO_SEL_1P8V, "1P8" }, #ifndef CONFIG_ZEPHYR - {GPIO_ANALOG, "A"}, - {GPIO_ALTERNATE, "ALT"}, - {GPIO_LOCKED, "LCK"} + { GPIO_ANALOG, "A" }, { GPIO_ALTERNATE, "ALT" }, + { GPIO_LOCKED, "LCK" } #endif }; @@ -108,12 +103,13 @@ static void print_gpio_info(int gpio) int changed, v, i; if (!gpio_is_implemented(gpio)) - return; /* Skip unsupported signals */ + return; /* Skip unsupported signals */ v = gpio_get_level(gpio); changed = last_val_changed(gpio, v); - /* Split the printf call into multiple calls to reduce the stack usage. */ + /* Split the printf call into multiple calls to reduce the stack usage. + */ ccprintf(" %d%c ", v, (changed ? '*' : ' ')); if (IS_ENABLED(CONFIG_CMD_GPIO_EXTENDED)) { @@ -148,15 +144,14 @@ static int command_gpio_get(int argc, char **argv) /* Otherwise print them all */ for (i = 0; i < GPIO_COUNT; i++) { if (!gpio_is_implemented(i)) - continue; /* Skip unsupported signals */ + continue; /* Skip unsupported signals */ print_gpio_info(i); } return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get, - "[name]", +DECLARE_SAFE_CONSOLE_COMMAND(gpioget, command_gpio_get, "[name]", "Read GPIO value(s)"); static int command_gpio_set(int argc, char **argv) @@ -222,9 +217,7 @@ DECLARE_CONSOLE_COMMAND_FLAGS(gpioset, command_gpio_set, #else "name <0 | 1>", #endif - "Set a GPIO", - CMD_FLAG_RESTRICTED -); + "Set a GPIO", CMD_FLAG_RESTRICTED); /*****************************************************************************/ /* Host commands */ @@ -267,7 +260,7 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args) i = p_v1->get_info.index; len = strlen(gpio_get_name(i)); - memcpy(r_v1->get_info.name, gpio_get_name(i), len+1); + memcpy(r_v1->get_info.name, gpio_get_name(i), len + 1); r_v1->get_info.val = gpio_get_level(i); r_v1->get_info.flags = gpio_get_default_flags(i); args->response_size = sizeof(r_v1->get_info); @@ -277,7 +270,6 @@ static enum ec_status gpio_command_get(struct host_cmd_handler_args *args) } return EC_RES_SUCCESS; - } DECLARE_HOST_COMMAND(EC_CMD_GPIO_GET, gpio_command_get, EC_VER_MASK(0) | EC_VER_MASK(1)); -- cgit v1.2.1 From 28aef252dc94ed3aa63affffc7cc9fea5911c45b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:20 -0600 Subject: zephyr/include/dt-bindings/gpio_defines.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c271656a88a2f62812e90b02b0ca003a3d7d7dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730714 Reviewed-by: Jeremy Bettis --- zephyr/include/dt-bindings/gpio_defines.h | 72 +++++++++++++------------------ 1 file changed, 30 insertions(+), 42 deletions(-) diff --git a/zephyr/include/dt-bindings/gpio_defines.h b/zephyr/include/dt-bindings/gpio_defines.h index fd63b5ac4a..3e61546b27 100644 --- a/zephyr/include/dt-bindings/gpio_defines.h +++ b/zephyr/include/dt-bindings/gpio_defines.h @@ -21,31 +21,31 @@ */ /** Enables pin as input. */ -#define GPIO_INPUT (1U << 16) +#define GPIO_INPUT (1U << 16) /** Enables pin as output, no change to the output state. */ -#define GPIO_OUTPUT (1U << 17) +#define GPIO_OUTPUT (1U << 17) /* Initializes output to a low state. */ -#define GPIO_OUTPUT_INIT_LOW (1U << 18) +#define GPIO_OUTPUT_INIT_LOW (1U << 18) /* Initializes output to a high state. */ -#define GPIO_OUTPUT_INIT_HIGH (1U << 19) +#define GPIO_OUTPUT_INIT_HIGH (1U << 19) /* Initializes output based on logic level */ #define GPIO_OUTPUT_INIT_LOGICAL (1U << 20) /* Configures GPIO pin as output and initializes it to a low state. */ -#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW) +#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW) /* Configures GPIO pin as output and initializes it to a high state. */ -#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH) +#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH) /* Configures GPIO pin as input with pull-up. */ -#define GPIO_INPUT_PULL_UP (GPIO_INPUT | GPIO_PULL_UP) +#define GPIO_INPUT_PULL_UP (GPIO_INPUT | GPIO_PULL_UP) /* Configures GPIO pin as input with pull-down. */ -#define GPIO_INPUT_PULL_DOWN (GPIO_INPUT | GPIO_PULL_DOWN) +#define GPIO_INPUT_PULL_DOWN (GPIO_INPUT | GPIO_PULL_DOWN) /** Configures GPIO pin as ODR output and initializes it to a low state. */ #define GPIO_ODR_LOW (GPIO_OUTPUT_LOW | GPIO_OPEN_DRAIN) @@ -61,17 +61,17 @@ */ /** Disables GPIO pin interrupt. */ -#define GPIO_INT_DISABLE (1U << 21) +#define GPIO_INT_DISABLE (1U << 21) /* Enables GPIO pin interrupt. */ -#define GPIO_INT_ENABLE (1U << 22) +#define GPIO_INT_ENABLE (1U << 22) /* GPIO interrupt is sensitive to logical levels. * * This is a component flag that should be combined with other * `GPIO_INT_*` flags to produce a meaningful configuration. */ -#define GPIO_INT_LEVELS_LOGICAL (1U << 23) +#define GPIO_INT_LEVELS_LOGICAL (1U << 23) /* GPIO interrupt is edge sensitive. * @@ -80,7 +80,7 @@ * This is a component flag that should be combined with other * `GPIO_INT_*` flags to produce a meaningful configuration. */ -#define GPIO_INT_EDGE (1U << 24) +#define GPIO_INT_EDGE (1U << 24) /* Trigger detection when input state is (or transitions to) physical low or * logical 0 level. @@ -88,7 +88,7 @@ * This is a component flag that should be combined with other * `GPIO_INT_*` flags to produce a meaningful configuration. */ -#define GPIO_INT_LOW_0 (1U << 25) +#define GPIO_INT_LOW_0 (1U << 25) /* Trigger detection on input state is (or transitions to) physical high or * logical 1 level. @@ -96,69 +96,57 @@ * This is a component flag that should be combined with other * `GPIO_INT_*` flags to produce a meaningful configuration. */ -#define GPIO_INT_HIGH_1 (1U << 26) +#define GPIO_INT_HIGH_1 (1U << 26) /** Configures GPIO interrupt to be triggered on pin rising edge and enables it. */ -#define GPIO_INT_EDGE_RISING (GPIO_INT_ENABLE | \ - GPIO_INT_EDGE | \ - GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_RISING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_HIGH_1) /** Configures GPIO interrupt to be triggered on pin falling edge and enables * it. */ -#define GPIO_INT_EDGE_FALLING (GPIO_INT_ENABLE | \ - GPIO_INT_EDGE | \ - GPIO_INT_LOW_0) +#define GPIO_INT_EDGE_FALLING (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0) /** Configures GPIO interrupt to be triggered on pin rising or falling edge and * enables it. */ -#define GPIO_INT_EDGE_BOTH (GPIO_INT_ENABLE | \ - GPIO_INT_EDGE | \ - GPIO_INT_LOW_0 | \ - GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_BOTH \ + (GPIO_INT_ENABLE | GPIO_INT_EDGE | GPIO_INT_LOW_0 | GPIO_INT_HIGH_1) /** Configures GPIO interrupt to be triggered on pin physical level low and * enables it. */ -#define GPIO_INT_LEVEL_LOW (GPIO_INT_ENABLE | \ - GPIO_INT_LOW_0) +#define GPIO_INT_LEVEL_LOW (GPIO_INT_ENABLE | GPIO_INT_LOW_0) /** Configures GPIO interrupt to be triggered on pin physical level high and * enables it. */ -#define GPIO_INT_LEVEL_HIGH (GPIO_INT_ENABLE | \ - GPIO_INT_HIGH_1) +#define GPIO_INT_LEVEL_HIGH (GPIO_INT_ENABLE | GPIO_INT_HIGH_1) /** Configures GPIO interrupt to be triggered on pin state change to logical * level 0 and enables it. */ -#define GPIO_INT_EDGE_TO_INACTIVE (GPIO_INT_ENABLE | \ - GPIO_INT_LEVELS_LOGICAL | \ - GPIO_INT_EDGE | \ - GPIO_INT_LOW_0) +#define GPIO_INT_EDGE_TO_INACTIVE \ + (GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \ + GPIO_INT_LOW_0) /** Configures GPIO interrupt to be triggered on pin state change to logical * level 1 and enables it. */ -#define GPIO_INT_EDGE_TO_ACTIVE (GPIO_INT_ENABLE | \ - GPIO_INT_LEVELS_LOGICAL | \ - GPIO_INT_EDGE | \ - GPIO_INT_HIGH_1) +#define GPIO_INT_EDGE_TO_ACTIVE \ + (GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_EDGE | \ + GPIO_INT_HIGH_1) /** Configures GPIO interrupt to be triggered on pin logical level 0 and enables * it. */ -#define GPIO_INT_LEVEL_INACTIVE (GPIO_INT_ENABLE | \ - GPIO_INT_LEVELS_LOGICAL | \ - GPIO_INT_LOW_0) +#define GPIO_INT_LEVEL_INACTIVE \ + (GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_LOW_0) /** Configures GPIO interrupt to be triggered on pin logical level 1 and enables * it. */ -#define GPIO_INT_LEVEL_ACTIVE (GPIO_INT_ENABLE | \ - GPIO_INT_LEVELS_LOGICAL | \ - GPIO_INT_HIGH_1) +#define GPIO_INT_LEVEL_ACTIVE \ + (GPIO_INT_ENABLE | GPIO_INT_LEVELS_LOGICAL | GPIO_INT_HIGH_1) #endif /* DT_BINDINGS_GPIO_DEFINES_H_ */ -- cgit v1.2.1 From 0e4e4d367f837528b4176f30c4acb56541888587 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:50 -0600 Subject: board/lalala/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6623b1119cadd60846ec155c205aebf48f929140 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728610 Reviewed-by: Jeremy Bettis --- board/lalala/board.c | 95 +++++++++++++++++++++++----------------------------- 1 file changed, 42 insertions(+), 53 deletions(-) diff --git a/board/lalala/board.c b/board/lalala/board.c index 59eb9fd4a8..1cf225b6f2 100644 --- a/board/lalala/board.c +++ b/board/lalala/board.c @@ -51,13 +51,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) static uint8_t new_adc_key_state; @@ -110,8 +110,8 @@ static const struct ec_response_keybd_config lalala_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &lalala_keybd; } @@ -152,7 +152,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -226,22 +225,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -258,8 +257,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -334,13 +333,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -400,8 +397,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -426,18 +423,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; - -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* BMA253 private data */ static struct accelgyro_saved_data_t g_bma253_data; @@ -445,11 +437,9 @@ static struct accelgyro_saved_data_t g_bma253_data; /* BMI160 private data */ static struct bmi_drv_data_t g_bmi160_data; -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* ICM426 private data */ static struct icm_drv_data_t g_icm426xx_data; @@ -633,7 +623,7 @@ void board_init(void) gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); } /* Turn on 5V if the system is on, otherwise turn it off. */ @@ -648,20 +638,19 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); void motion_interrupt(enum gpio_signal signal) { - switch (get_cbi_ssfc_base_sensor()) { - case SSFC_SENSOR_ICM426XX: - icm426xx_interrupt(signal); - break; - case SSFC_SENSOR_BMI160: - default: - bmi160_interrupt(signal); - break; - } + switch (get_cbi_ssfc_base_sensor()) { + case SSFC_SENSOR_ICM426XX: + icm426xx_interrupt(signal); + break; + case SSFC_SENSOR_BMI160: + default: + bmi160_interrupt(signal); + break; + } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; -- cgit v1.2.1 From 4c767c1e8fbda8b9e858a45773b7b1030f432be6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:52 -0600 Subject: power/intel_x86.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e1b359768f7f48af586971ed7cf3a061cde6a07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727061 Reviewed-by: Jeremy Bettis --- power/intel_x86.c | 55 ++++++++++++++++++++++++++----------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/power/intel_x86.c b/power/intel_x86.c index 35c0482831..4b489116d5 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -23,8 +23,8 @@ #include "wireless.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) enum sys_sleep_state { SYS_SLEEP_S3, @@ -44,7 +44,7 @@ static const int sleep_sig[] = { #endif }; -static int power_s5_up; /* Chipset is sequencing up or down */ +static int power_s5_up; /* Chipset is sequencing up or down */ #ifdef CONFIG_CHARGER /* Flag to indicate if power up was inhibited due to low battery SOC level. */ @@ -61,7 +61,7 @@ static int is_power_up_inhibited(void) const int power_button_pressed = 0; return charge_prevent_power_on(power_button_pressed) || - charge_want_shutdown(); + charge_want_shutdown(); } static void power_up_inhibited_cb(void) @@ -179,8 +179,7 @@ static void lpc_s0ix_resume_restore_masks(void) backup_sci_mask = backup_smi_mask = 0; } -__override void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { /* * Wake up the AP so they don't just chill in a non-suspended state and @@ -259,8 +258,8 @@ enum power_state power_chipset_init(void) CPRINTS("already in S0"); return POWER_S0; } - if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL) - == CHIPSET_G3S5_POWERUP_SIGNAL) { + if ((power_get_signals() & CHIPSET_G3S5_POWERUP_SIGNAL) == + CHIPSET_G3S5_POWERUP_SIGNAL) { /* case #2 & #3 */ CPRINTS("already in S5"); return POWER_S5; @@ -321,16 +320,16 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state) /* Power down to next state */ return POWER_S0S3; #ifdef CONFIG_POWER_S0IX - /* - * SLP_S0 may assert in system idle scenario without a kernel - * freeze call. This may cause interrupt storm since there is - * no freeze/unfreeze of threads/process in the idle scenario. - * Ignore the SLP_S0 assertions in idle scenario by checking - * the host sleep state. - */ - } else if (power_get_host_sleep_state() - == HOST_SLEEP_EVENT_S0IX_SUSPEND && - chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) { + /* + * SLP_S0 may assert in system idle scenario without a + * kernel freeze call. This may cause interrupt storm + * since there is no freeze/unfreeze of threads/process + * in the idle scenario. Ignore the SLP_S0 assertions in + * idle scenario by checking the host sleep state. + */ + } else if (power_get_host_sleep_state() == + HOST_SLEEP_EVENT_S0IX_SUSPEND && + chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 0) { return POWER_S0S0ix; } else { sleep_notify_transition(SLEEP_NOTIFY_RESUME, @@ -344,7 +343,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state) case POWER_S0ix: /* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */ if ((chipset_get_sleep_signal(SYS_SLEEP_S0IX) == 1) && - (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) { + (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) { return POWER_S0ixS0; } else if (!power_has_signals(IN_PGOOD_ALL_CORE)) { return POWER_S0; @@ -572,8 +571,8 @@ void common_intel_x86_handle_rsmrst(enum power_state state) board_before_rsmrst(rsmrst_in); /* Only passthrough RSMRST_L de-assertion on power up */ - if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_AFTER_S5) && - rsmrst_in && !power_s5_up) + if (IS_ENABLED(CONFIG_CHIPSET_X86_RSMRST_AFTER_S5) && rsmrst_in && + !power_s5_up) return; /* * Wait at least 10ms between power signals going high @@ -591,15 +590,15 @@ void common_intel_x86_handle_rsmrst(enum power_state state) #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__overridable void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__overridable void +power_board_handle_host_sleep_event(enum host_sleep_event state) { /* Default weak implementation -- no action required. */ } -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { power_board_handle_host_sleep_event(state); @@ -635,7 +634,6 @@ __override void power_chipset_handle_host_sleep_event( power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]); } #endif - } #endif @@ -687,8 +685,7 @@ enum ec_error_list intel_x86_wait_power_up_ok(void) * Allow charger to be initialized for up to defined tries, * in case we're trying to boot the AP with no battery. */ - while ((tries < CHARGER_INITIALIZED_TRIES) && - is_power_up_inhibited()) { + while ((tries < CHARGER_INITIALIZED_TRIES) && is_power_up_inhibited()) { msleep(CHARGER_INITIALIZED_DELAY_MS); tries++; } -- cgit v1.2.1 From 3a25ff56afbf5bc871f95be9d52c4a78f26039e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:04 -0600 Subject: board/crota/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I48f7b8b2c0dbfab8733554c396e15bc63022db3e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728192 Reviewed-by: Jeremy Bettis --- board/crota/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/crota/fw_config.c b/board/crota/fw_config.c index 35fc466fd1..e03c708d45 100644 --- a/board/crota/fw_config.c +++ b/board/crota/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union brya_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 8948147dd50eed1f3aab025d956c90ae6b049390 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:06 -0600 Subject: zephyr/include/ap_power/ap_power_interface.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic863e1efa19d92bcc536a7207bbc142c33312369 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730710 Reviewed-by: Jeremy Bettis --- zephyr/include/ap_power/ap_power_interface.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/zephyr/include/ap_power/ap_power_interface.h b/zephyr/include/ap_power/ap_power_interface.h index b82ef053f7..f834779fb9 100644 --- a/zephyr/include/ap_power/ap_power_interface.h +++ b/zephyr/include/ap_power/ap_power_interface.h @@ -87,17 +87,17 @@ enum power_states_ndsx { * @brief Represents the state of the AP as a mask. */ enum ap_power_state_mask { - AP_POWER_STATE_HARD_OFF = BIT(0), /* Hard off (G3) */ - AP_POWER_STATE_SOFT_OFF = BIT(1), /* Soft off (S5, S4) */ - AP_POWER_STATE_SUSPEND = BIT(2), /* Suspend (S3) */ - AP_POWER_STATE_ON = BIT(3), /* On (S0) */ - AP_POWER_STATE_STANDBY = BIT(4), /* Standby (S0ix) */ + AP_POWER_STATE_HARD_OFF = BIT(0), /* Hard off (G3) */ + AP_POWER_STATE_SOFT_OFF = BIT(1), /* Soft off (S5, S4) */ + AP_POWER_STATE_SUSPEND = BIT(2), /* Suspend (S3) */ + AP_POWER_STATE_ON = BIT(3), /* On (S0) */ + AP_POWER_STATE_STANDBY = BIT(4), /* Standby (S0ix) */ /* Common combinations, any off state */ - AP_POWER_STATE_ANY_OFF = (AP_POWER_STATE_HARD_OFF | - AP_POWER_STATE_SOFT_OFF), + AP_POWER_STATE_ANY_OFF = + (AP_POWER_STATE_HARD_OFF | AP_POWER_STATE_SOFT_OFF), /* This combination covers any kind of suspend i.e. S3 or S0ix. */ - AP_POWER_STATE_ANY_SUSPEND = (AP_POWER_STATE_SUSPEND | - AP_POWER_STATE_STANDBY), + AP_POWER_STATE_ANY_SUSPEND = + (AP_POWER_STATE_SUSPEND | AP_POWER_STATE_STANDBY), }; /** -- cgit v1.2.1 From 0973c9eccf4c425ab68561cd756cd988b5d43913 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:22 -0600 Subject: chip/ish/system_state_subsys.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I29b622b2264d735f70d6ed41813f11518f89fe6b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729189 Reviewed-by: Jeremy Bettis --- chip/ish/system_state_subsys.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/chip/ish/system_state_subsys.c b/chip/ish/system_state_subsys.c index 36b79c747a..5c17ac3585 100644 --- a/chip/ish/system_state_subsys.c +++ b/chip/ish/system_state_subsys.c @@ -10,24 +10,23 @@ #ifdef SS_SUBSYSTEM_DEBUG #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) #else #define CPUTS(outstr) #define CPRINTS(format, args...) #define CPRINTF(format, args...) #endif - /* the following "define"s and structures are from host driver * and they are slightly modified for look&feel purpose. */ -#define SYSTEM_STATE_SUBSCRIBE 0x1 -#define SYSTEM_STATE_STATUS 0x2 -#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3 -#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4 +#define SYSTEM_STATE_SUBSCRIBE 0x1 +#define SYSTEM_STATE_STATUS 0x2 +#define SYSTEM_STATE_QUERY_SUBSCRIBERS 0x3 +#define SYSTEM_STATE_STATE_CHANGE_REQ 0x4 -#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ +#define SUSPEND_STATE_BIT BIT(1) /* suspend/resume */ /* Cached state of ISH's requested power rails when AP suspends */ static uint32_t cached_vnn_request; @@ -67,7 +66,7 @@ struct ss_state_change_req { * "struct ss_subsys_device" in it and calls ss_subsys_register_client() like * HECI client. */ -#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS +#define MAX_SS_CLIENTS HECI_MAX_NUM_OF_CLIENTS struct ss_subsystem_context { uint32_t registered_state; @@ -103,7 +102,7 @@ static int ss_subsys_suspend(void) for (i = ss_subsys_ctx.num_of_ss_client - 1; i >= 0; i--) { if (ss_subsys_ctx.clients[i]->cbs->suspend) ss_subsys_ctx.clients[i]->cbs->suspend( - ss_subsys_ctx.clients[i]); + ss_subsys_ctx.clients[i]); } /* @@ -126,8 +125,7 @@ static int ss_subsys_resume(void) /* * Restore VNN power request from before suspend. */ - if (IS_ENABLED(CHIP_FAMILY_ISH5) && - cached_vnn_request) { + if (IS_ENABLED(CHIP_FAMILY_ISH5) && cached_vnn_request) { /* Request all cached power rails that are not already on. */ PMU_VNN_REQ = cached_vnn_request & ~PMU_VNN_REQ; /* Wait for power request to get acknowledged */ @@ -138,7 +136,7 @@ static int ss_subsys_resume(void) for (i = 0; i < ss_subsys_ctx.num_of_ss_client; i++) { if (ss_subsys_ctx.clients[i]->cbs->resume) ss_subsys_ctx.clients[i]->cbs->resume( - ss_subsys_ctx.clients[i]); + ss_subsys_ctx.clients[i]); } return EC_SUCCESS; -- cgit v1.2.1 From 7f39f3dc92fc76406c9614695d59825238d9ef2a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:02 -0600 Subject: chip/stm32/clock-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4227fa7ecea4064c049e7235f127daef34fd9683 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729462 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32f0.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index d791d63df3..5a57e289fa 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -22,7 +22,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* use 48Mhz USB-synchronized High-speed oscillator */ #define HSI48_CLOCK 48000000 @@ -54,13 +54,13 @@ static int dsleep_recovery_margin_us = 1000000; * we won't miss the host alarm. */ #ifdef CHIP_VARIANT_STM32F373 -#define STOP_MODE_LATENCY 500 /* us */ +#define STOP_MODE_LATENCY 500 /* us */ #elif defined(CHIP_VARIANT_STM32F05X) -#define STOP_MODE_LATENCY 300 /* us */ +#define STOP_MODE_LATENCY 300 /* us */ #elif (CPU_CLOCK == PLL_CLOCK) -#define STOP_MODE_LATENCY 300 /* us */ +#define STOP_MODE_LATENCY 300 /* us */ #else -#define STOP_MODE_LATENCY 50 /* us */ +#define STOP_MODE_LATENCY 50 /* us */ #endif #define SET_RTC_MATCH_DELAY 200 /* us */ @@ -137,9 +137,8 @@ void config_hispeed_clock(void) while ((STM32_RCC_CFGR & 0xc) != 0x8) ; /* F03X and F05X and F070 don't have HSI48 */ -#elif defined(CHIP_VARIANT_STM32F03X) || \ -defined(CHIP_VARIANT_STM32F05X) || \ -defined(CHIP_VARIANT_STM32F070) +#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \ + defined(CHIP_VARIANT_STM32F070) /* If PLL is the clock source, PLL has already been set up. */ if ((STM32_RCC_CFGR & 0xc) == 0x8) return; @@ -319,8 +318,8 @@ void __idle(void) * EC exits deep sleep mode. */ !is_host_wake_alarm_expired( - (timestamp_t)(next_delay + t0.val + SECOND + - RESTORE_HOST_ALARM_LATENCY)) && + (timestamp_t)(next_delay + t0.val + SECOND + + RESTORE_HOST_ALARM_LATENCY)) && #endif (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { /* Deep-sleep in STOP mode */ @@ -331,8 +330,8 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, - &rtc0, 0); + set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0, + 0); asm("wfi"); CPU_SCB_SYSCTRL &= ~0x4; @@ -374,7 +373,7 @@ void __idle(void) asm("wfi"); } #ifdef CONFIG_LOW_POWER_IDLE_LIMITED -en_int: + en_int: #endif interrupt_enable(); } @@ -489,15 +488,14 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_CMD_IDLE_STATS */ #endif -- cgit v1.2.1 From 52e16f1f8baceaf56eb7703832976ae6c8f1ae32 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:08 -0600 Subject: driver/accel_lis2dh.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5cd27e3a47f2d221b4ba2a736d46ddf5d8c3f9ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729909 Reviewed-by: Jeremy Bettis --- driver/accel_lis2dh.h | 93 ++++++++++++++++++++++++++------------------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/driver/accel_lis2dh.h b/driver/accel_lis2dh.h index 2a3108aab8..28dafad74b 100644 --- a/driver/accel_lis2dh.h +++ b/driver/accel_lis2dh.h @@ -16,8 +16,8 @@ * 7-bit address is 0011 00X b. Where 'X' is determined * by the voltage on the ADDR pin */ -#define LIS2DH_ADDR0_FLAGS 0x18 -#define LIS2DH_ADDR1_FLAGS 0x19 +#define LIS2DH_ADDR0_FLAGS 0x18 +#define LIS2DH_ADDR1_FLAGS 0x19 /* * LNG2DM: @@ -25,54 +25,54 @@ * 8-bit address is 0101 00XW b. Where 'X' is determined * by the voltage on the ADDR pin, and 'W' is read write bit */ -#define LNG2DM_ADDR0_FLAGS 0x28 -#define LNG2DM_ADDR1_FLAGS 0x29 +#define LNG2DM_ADDR0_FLAGS 0x28 +#define LNG2DM_ADDR1_FLAGS 0x29 /* Who Am I */ -#define LIS2DH_WHO_AM_I_REG 0x0f -#define LIS2DH_WHO_AM_I 0x33 +#define LIS2DH_WHO_AM_I_REG 0x0f +#define LIS2DH_WHO_AM_I 0x33 /* COMMON DEFINE FOR ACCEL SENSOR */ -#define LIS2DH_EN_BIT 0x01 -#define LIS2DH_DIS_BIT 0x00 +#define LIS2DH_EN_BIT 0x01 +#define LIS2DH_DIS_BIT 0x00 -#define LIS2DH_INT2_ON_INT1_ADDR 0x13 -#define LIS2DH_INT2_ON_INT1_MASK 0x20 +#define LIS2DH_INT2_ON_INT1_ADDR 0x13 +#define LIS2DH_INT2_ON_INT1_MASK 0x20 -#define LIS2DH_OUT_X_L_ADDR 0x28 +#define LIS2DH_OUT_X_L_ADDR 0x28 -#define LIS2DH_CTRL1_ADDR 0x20 -#define LIS2DH_INT2_ON_INT1_MASK 0x20 -#define LIS2DH_ENABLE_ALL_AXES 0x07 +#define LIS2DH_CTRL1_ADDR 0x20 +#define LIS2DH_INT2_ON_INT1_MASK 0x20 +#define LIS2DH_ENABLE_ALL_AXES 0x07 -#define LIS2DH_CTRL2_ADDR 0x21 -#define LIS2DH_CTRL2_RESET_VAL 0x00 +#define LIS2DH_CTRL2_ADDR 0x21 +#define LIS2DH_CTRL2_RESET_VAL 0x00 -#define LIS2DH_CTRL3_ADDR 0x22 -#define LIS2DH_CTRL3_RESET_VAL 0x00 +#define LIS2DH_CTRL3_ADDR 0x22 +#define LIS2DH_CTRL3_RESET_VAL 0x00 -#define LIS2DH_CTRL4_ADDR 0x23 -#define LIS2DH_BDU_MASK 0x80 +#define LIS2DH_CTRL4_ADDR 0x23 +#define LIS2DH_BDU_MASK 0x80 -#define LIS2DH_CTRL5_ADDR 0x24 -#define LIS2DH_CTRL5_RESET_VAL 0x00 +#define LIS2DH_CTRL5_ADDR 0x24 +#define LIS2DH_CTRL5_RESET_VAL 0x00 -#define LIS2DH_CTRL6_ADDR 0x25 -#define LIS2DH_CTRL6_RESET_VAL 0x00 +#define LIS2DH_CTRL6_ADDR 0x25 +#define LIS2DH_CTRL6_RESET_VAL 0x00 -#define LIS2DH_STATUS_REG 0x27 -#define LIS2DH_STS_XLDA_UP 0x80 +#define LIS2DH_STATUS_REG 0x27 +#define LIS2DH_STS_XLDA_UP 0x80 -#define LIS2DH_FS_2G_VAL 0x00 -#define LIS2DH_FS_4G_VAL 0x01 -#define LIS2DH_FS_8G_VAL 0x02 -#define LIS2DH_FS_16G_VAL 0x03 +#define LIS2DH_FS_2G_VAL 0x00 +#define LIS2DH_FS_4G_VAL 0x01 +#define LIS2DH_FS_8G_VAL 0x02 +#define LIS2DH_FS_16G_VAL 0x03 /* Interrupt source status register */ -#define LIS2DH_INT1_SRC_REG 0x31 +#define LIS2DH_INT1_SRC_REG 0x31 /* Output data rate Mask register */ -#define LIS2DH_ACC_ODR_MASK 0xf0 +#define LIS2DH_ACC_ODR_MASK 0xf0 /* Acc data rate */ enum lis2dh_odr { @@ -88,28 +88,29 @@ enum lis2dh_odr { }; /* Absolute maximum rate for sensor */ -#define LIS2DH_ODR_MIN_VAL 1000 -#define LIS2DH_ODR_MAX_VAL \ - MOTION_MAX_SENSOR_FREQUENCY(400000, 25000) +#define LIS2DH_ODR_MIN_VAL 1000 +#define LIS2DH_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(400000, 25000) /* Return ODR reg value based on data rate set */ -#define LIS2DH_ODR_TO_REG(_odr) \ - (_odr <= 1000) ? LIS2DH_ODR_1HZ_VAL : \ +#define LIS2DH_ODR_TO_REG(_odr) \ + (_odr <= 1000) ? LIS2DH_ODR_1HZ_VAL : \ (_odr <= 10000) ? LIS2DH_ODR_10HZ_VAL : \ - ((31 - __builtin_clz(_odr / 25000))) + 3 + ((31 - __builtin_clz(_odr / 25000))) + 3 /* Return ODR real value normalized to sensor capabilities */ #define LIS2DH_ODR_TO_NORMALIZE(_odr) \ - (_odr <= 1000) ? 1000 : (_odr <= 10000) ? 10000 : \ - (25000 * (1 << (31 - __builtin_clz(_odr / 25000)))) + (_odr <= 1000) ? 1000 : \ + (_odr <= 10000) ? 10000 : \ + (25000 * (1 << (31 - __builtin_clz(_odr / 25000)))) /* Return ODR real value normalized to sensor capabilities from reg value */ -#define LIS2DH_REG_TO_NORMALIZE(_reg) \ - (_reg == LIS2DH_ODR_1HZ_VAL) ? 1000 : \ - (_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : (25000 * (1 << (_reg - 3))) +#define LIS2DH_REG_TO_NORMALIZE(_reg) \ + (_reg == LIS2DH_ODR_1HZ_VAL) ? 1000 : \ + (_reg == LIS2DH_ODR_10HZ_VAL) ? 10000 : \ + (25000 * (1 << (_reg - 3))) /* Full scale range Mask register */ -#define LIS2DH_FS_MASK 0x30 +#define LIS2DH_FS_MASK 0x30 /* FS reg value from Full Scale */ #define LIS2DH_FS_TO_REG(_fs) (__fls(_fs) - 1) @@ -123,9 +124,9 @@ enum lis2dh_odr { * lis2de/lng2dm only support 8bit resolution. */ #if defined(CONFIG_ACCEL_LIS2DE) || defined(CONFIG_ACCEL_LNG2DM) -#define LIS2DH_RESOLUTION 8 +#define LIS2DH_RESOLUTION 8 #elif defined(CONFIG_ACCEL_LIS2DH) -#define LIS2DH_RESOLUTION 10 +#define LIS2DH_RESOLUTION 10 #endif extern const struct accelgyro_drv lis2dh_drv; -- cgit v1.2.1 From 7e5173ef1191d9c721a214f64ec0d64a190cabd7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:17 -0600 Subject: board/chocodile_vpdmcu/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5b7408e2ed98711b0ae098b17e5a99524b511c1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728123 Reviewed-by: Jeremy Bettis --- board/chocodile_vpdmcu/usb_pd_config.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/board/chocodile_vpdmcu/usb_pd_config.h b/board/chocodile_vpdmcu/usb_pd_config.h index 048bbf3988..dcf63588eb 100644 --- a/board/chocodile_vpdmcu/usb_pd_config.h +++ b/board/chocodile_vpdmcu/usb_pd_config.h @@ -55,7 +55,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 /* EXTI line 21 is connected to the CMP1 output */ #define EXTI_COMP1_MASK (1 << 21) @@ -95,13 +95,15 @@ static inline void pd_tx_spi_reset(int port) static inline void pd_tx_enable(int port, int polarity) { /* USB_CC_TX_DATA: PB4 is SPI1 MISO */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*4))) /* PB4 disable ADC */ - | (2 << (2*4)); /* Set as SPI1_MISO */ + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) /* PB4 disable ADC + */ + | (2 << (2 * 4)); /* Set as SPI1_MISO */ /* MCU ADC PA1 pin output low */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*1))) /* PA1 disable ADC */ - | (1 << (2*1)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 1))) /* PA1 disable ADC + */ + | (1 << (2 * 1)); /* Set as GPO */ gpio_set_level(GPIO_CC_VPDMCU, 0); } @@ -109,11 +111,10 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* Set CC_TX_DATA to Hi-Z, PB4 is SPI1 MISO */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*4))); + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))); /* set ADC PA1 pin to ADC function (Hi-Z) */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*1))); /* PA1 as ADC */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 1))); /* PA1 as ADC */ } /* we know the plug polarity, do the right configuration */ @@ -123,8 +124,8 @@ static inline void pd_select_polarity(int port, int polarity) * use the right comparator : CC1 -> PA1 (COMP1 INP) * use VrefInt / 2 as INM (about 600mV) */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; } /* Initialize pins used for TX and put them in Hi-Z */ -- cgit v1.2.1 From 5d8ec985f40e4989d45198e0b339f0d1c8885454 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:13 -0600 Subject: zephyr/shim/src/usb_muxes.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2f292fdd7cb1ba17ac41c40dab31fc6eb2e2b151 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730918 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/usb_muxes.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/src/usb_muxes.c b/zephyr/shim/src/usb_muxes.c index 188499aa30..d4361b8620 100644 --- a/zephyr/shim/src/usb_muxes.c +++ b/zephyr/shim/src/usb_muxes.c @@ -13,7 +13,7 @@ * argument. It allows to evaluate to "1 ||" for each named USBC port * that has usb-muxes property. */ -#define USB_MUX_PORT_HAS_MUX(unused1, unused2) 1 || +#define USB_MUX_PORT_HAS_MUX(unused1, unused2) 1 || /** * Check if there is any named USBC port with usb-muxes property. It evaluates @@ -39,9 +39,8 @@ * }, * [1] = { ... }, */ -MAYBE_CONST struct usb_mux usb_muxes[] = { - USB_MUX_FOREACH_USBC_PORT(USB_MUX_FIRST, USB_MUX_ARRAY) -}; +MAYBE_CONST struct usb_mux usb_muxes[] = { USB_MUX_FOREACH_USBC_PORT( + USB_MUX_FIRST, USB_MUX_ARRAY) }; /** * Define all USB muxes except roots e.g. @@ -65,10 +64,9 @@ USB_MUX_FOREACH_USBC_PORT(USB_MUX_NO_FIRST, USB_MUX_DEFINE) * @brief bb_controls array should be constant only if configuration cannot * change in runtime */ -#define BB_CONTROLS_CONST \ - COND_CODE_1( \ - CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG,\ - (), (const)) +#define BB_CONTROLS_CONST \ + COND_CODE_1(CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG, \ + (), (const)) /** * Define bb_controls for BB retimers in USB muxes chain e.g. -- cgit v1.2.1 From c9779339d9a0871b3dc69f3e1eb73571fa13295f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:33 -0600 Subject: include/display_7seg.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I445521595472bf8fdb4c8e5d6166ff132e71362a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730241 Reviewed-by: Jeremy Bettis --- include/display_7seg.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/display_7seg.h b/include/display_7seg.h index 4369502672..7b35bf3a65 100644 --- a/include/display_7seg.h +++ b/include/display_7seg.h @@ -9,9 +9,9 @@ #define __CROS_EC_DISPLAY_7SEG_H enum seven_seg_module_display { - SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */ - SEVEN_SEG_EC_DISPLAY, /* power state */ - SEVEN_SEG_PORT80_DISPLAY, /* port80 data */ + SEVEN_SEG_CONSOLE_DISPLAY, /* Console data */ + SEVEN_SEG_EC_DISPLAY, /* power state */ + SEVEN_SEG_PORT80_DISPLAY, /* port80 data */ }; /** @@ -23,4 +23,4 @@ enum seven_seg_module_display { */ int display_7seg_write(enum seven_seg_module_display module, uint16_t data); -#endif /* __CROS_EC_DISPLAY_7SEG_H */ +#endif /* __CROS_EC_DISPLAY_7SEG_H */ -- cgit v1.2.1 From 1599be0fd40e2570b790b0f9f1532268a5bae3bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:13 -0600 Subject: baseboard/guybrush/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I35d80d5963edf5193b2e99fceaf261d52eacbfbd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727519 Reviewed-by: Jeremy Bettis --- baseboard/guybrush/baseboard.h | 111 ++++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 62 deletions(-) diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h index 2e30dfcc27..96056acf5e 100644 --- a/baseboard/guybrush/baseboard.h +++ b/baseboard/guybrush/baseboard.h @@ -10,8 +10,8 @@ /* NPCX9 config */ #define CONFIG_PORT80_4_BYTE -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Optional features */ #define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT @@ -32,8 +32,8 @@ #define CONFIG_VBOOT_HASH #define CONFIG_VSTORE #define CONFIG_VSTORE_SLOT_COUNT 1 -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE /* CBI Config */ #define CONFIG_CBI_EEPROM @@ -41,7 +41,7 @@ /* Power Config */ #define CONFIG_CHIPSET_X86_RSMRST_DELAY -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_HIBERNATE_PSL @@ -54,19 +54,19 @@ #define CONFIG_POWER_SLEEP_FAILURE_DETECTION #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE #define G3_TO_PWRBTN_DELAY_MS 16 -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 -#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD -#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD -#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EN_PWR_A GPIO_EN_PWR_S5 +#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD +#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD +#define GPIO_S5_PGOOD GPIO_PG_PWR_S5 +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L #define SAFE_RESET_VBUS_DELAY_MS 900 #define SAFE_RESET_VBUS_MV 5000 /* @@ -86,12 +86,12 @@ #define CONFIG_TEMP_SENSOR_SB_TSI #define CONFIG_THERMISTOR #define CONFIG_CPU_PROCHOT_ACTIVE_LOW -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL /* Flash Config */ /* See config_chip-npcx9.h for SPI flash configuration */ #undef CONFIG_SPI_FLASH /* Don't enable external flash interface */ -#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_WP_L GPIO_EC_WP_L /* Host communication */ #define CONFIG_CMD_APTHROTTLE @@ -99,7 +99,7 @@ #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT -#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L +#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L /* Chipset config */ #define CONFIG_CHIPSET_CEZANNE @@ -114,15 +114,15 @@ #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_KEYBOARD_VIVALDI #define CONFIG_KBLIGHT_ENABLE_PIN -#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* Sensors */ #ifdef HAS_TASK_MOTIONSENSE #define CONFIG_TABLET_MODE #define CONFIG_GMR_TABLET_MODE -#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE +#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -138,7 +138,7 @@ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) -#endif /* HAS_TASK_MOTIONSENSE */ +#endif /* HAS_TASK_MOTIONSENSE */ /* Backlight config */ #define CONFIG_BACKLIGHT_LID @@ -146,7 +146,7 @@ #define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL /* Battery Config */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_REVIVE_DISCONNECT @@ -172,7 +172,7 @@ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on * Depthcharge to boot OS. */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000 /* * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging @@ -226,8 +226,8 @@ #define CONFIG_IO_EXPANDER_NCT38XX #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* USB-A config */ #define USB_PORT_COUNT USBA_PORT_COUNT @@ -260,21 +260,21 @@ #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_UPDATE_IF_CHANGED -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT4_1 -#define I2C_PORT_CHARGER I2C_PORT_POWER -#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 -#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT4_1 +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1 +#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Volume Button Config */ #define CONFIG_VOLUME_BUTTONS -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL /* Fan Config */ #define CONFIG_FANS FAN_CH_COUNT @@ -290,30 +290,22 @@ /* Power input signals */ enum power_signal { - X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ + X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ + X86_SLP_S3_N, /* SOC -> SLP_S3_L */ + X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ + X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ + X86_S5_PGOOD, /* PMIC -> S5_PWROK */ /* Number of X86 signals */ POWER_SIGNAL_COUNT, }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* TMP112 sensors */ enum tmp112_sensor { @@ -322,12 +314,7 @@ enum tmp112_sensor { TMP112_COUNT, }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* PWM Channels */ enum pwm_channel { -- cgit v1.2.1 From 1bdcca7d756468566304989e988ac9ab9709013f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:45 -0600 Subject: power/host_sleep.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a5612e3891ad0a9337276d5cb703d10b2fd97fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727060 Reviewed-by: Jeremy Bettis --- power/host_sleep.c | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/power/host_sleep.c b/power/host_sleep.c index e352e677f2..28d3f506a1 100644 --- a/power/host_sleep.c +++ b/power/host_sleep.c @@ -12,15 +12,15 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /* Track last reported sleep event */ static enum host_sleep_event host_sleep_state; -__overridable void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__overridable void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { /* Default weak implementation -- no action required. */ } @@ -71,8 +71,7 @@ host_command_host_sleep_event(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, - host_command_host_sleep_event, +DECLARE_HOST_COMMAND(EC_CMD_HOST_SLEEP_EVENT, host_command_host_sleep_event, EC_VER_MASK(0) | EC_VER_MASK(1)); enum host_sleep_event power_get_host_sleep_state(void) @@ -116,14 +115,13 @@ static enum sleep_hang_type timeout_hang_type; static void sleep_transition_timeout(void); DECLARE_DEFERRED(sleep_transition_timeout); -__overridable void power_board_handle_sleep_hang( - enum sleep_hang_type hang_type) +__overridable void power_board_handle_sleep_hang(enum sleep_hang_type hang_type) { /* Default empty implementation */ } -__overridable void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__overridable void +power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { /* Default empty implementation */ } @@ -231,7 +229,7 @@ static int command_sleep_fail_timeout(int argc, char **argv) if (val <= 0 || val >= EC_HOST_SLEEP_TIMEOUT_INFINITE) { ccprintf("Error: timeout range is 1..%d [msec]\n", - EC_HOST_SLEEP_TIMEOUT_INFINITE - 1); + EC_HOST_SLEEP_TIMEOUT_INFINITE - 1); return EC_ERROR_PARAM1; } @@ -242,19 +240,18 @@ static int command_sleep_fail_timeout(int argc, char **argv) ccprintf("Sleep failure detection timeout is disabled\n"); else ccprintf("Sleep failure detection timeout is %d [msec]\n", - host_sleep_timeout_default); + host_sleep_timeout_default); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(sleeptimeout, command_sleep_fail_timeout, - "[default | infinite | ]", - "Display or set host sleep failure detection timeout.\n" - "Valid arguments are:\n" - " default\n" - " infinite - disables the timeout\n" - " - custom length in milliseconds\n" - " - prints the current setting"); - + "[default | infinite | ]", + "Display or set host sleep failure detection timeout.\n" + "Valid arguments are:\n" + " default\n" + " infinite - disables the timeout\n" + " - custom length in milliseconds\n" + " - prints the current setting"); #else /* !CONFIG_POWER_SLEEP_FAILURE_DETECTION */ -- cgit v1.2.1 From 1279e478e0752d9fbdd8d3b0fb032c025f4116d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:41 -0600 Subject: chip/it83xx/spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id90f7f082098367af8f89b8a7bb9b8594958da74 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729215 Reviewed-by: Jeremy Bettis --- chip/it83xx/spi.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c index 23885f41a3..c5b3c1c7cb 100644 --- a/chip/it83xx/spi.c +++ b/chip/it83xx/spi.c @@ -20,8 +20,8 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #define SPI_RX_MAX_FIFO_SIZE 256 #define SPI_TX_MAX_FIFO_SIZE 256 @@ -31,8 +31,8 @@ /* Max data size for a version 3 request/response packet. */ #define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE -#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \ - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH) +#define SPI_MAX_RESPONSE_SIZE \ + (SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH) static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = { EC_SPI_PROCESSING, @@ -64,9 +64,9 @@ enum spi_peripheral_state_machine { static const int spi_response_state[] = { [SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY, - [SPI_STATE_RECEIVING] = EC_SPI_RECEIVING, - [SPI_STATE_PROCESSING] = EC_SPI_PROCESSING, - [SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA, + [SPI_STATE_RECEIVING] = EC_SPI_RECEIVING, + [SPI_STATE_PROCESSING] = EC_SPI_PROCESSING, + [SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA, }; BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT); @@ -145,11 +145,11 @@ static void spi_send_response_packet(struct host_packet *pkt) /* Append our past-end byte, which we reserved space for. */ for (i = 0; i < EC_SPI_PAST_END_LENGTH; i++) - ((uint8_t *)pkt->response)[pkt->response_size + i] - = EC_SPI_PAST_END; + ((uint8_t *)pkt->response)[pkt->response_size + i] = + EC_SPI_PAST_END; tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH + - EC_SPI_PAST_END_LENGTH; + EC_SPI_PAST_END_LENGTH; /* Transmit the reply */ spi_response_host_data(out_msg, tx_size); @@ -194,7 +194,7 @@ static void spi_parse_header(void) /* Store request data from Rx FIFO to in_msg buffer */ spi_host_request_data(in_msg + sizeof(*r), - pkt_size - sizeof(*r)); + pkt_size - sizeof(*r)); /* Set up parameters for host request */ spi_packet.send_response = spi_send_response_packet; @@ -327,8 +327,8 @@ static void spi_init(void) * bit3 : Rx FIFO1 will not be overwrited once it's full. * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high. */ - IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC - | IT83XX_SPI_RXFAR; + IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC | + IT83XX_SPI_RXFAR; /* * Interrupt mask register (0b:Enable, 1b:Mask) * bit5 : Rx byte reach interrupt mask @@ -395,9 +395,8 @@ static enum ec_status _spi_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - _spi_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, _spi_get_protocol_info, + EC_VER_MASK(0)); enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) { -- cgit v1.2.1 From 7e160ac103905cf9384ce11dc10b99451730c12f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:52 -0600 Subject: board/lalala/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic22cf58274f9869d6d98a1b6d32719edf73454cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728611 Reviewed-by: Jeremy Bettis --- board/lalala/board.h | 52 ++++++++++++++++++++++------------------------------ 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/board/lalala/board.h b/board/lalala/board.h index c8f40d518d..13abae1101 100644 --- a/board/lalala/board.h +++ b/board/lalala/board.h @@ -24,9 +24,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -44,7 +45,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -81,16 +82,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -99,15 +100,15 @@ #define CONFIG_CMD_ACCEL_INFO #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -143,25 +144,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From 0cda1e0446c5c1a84e02b10d36554946cb050a38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:42 -0600 Subject: board/host/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If42d7630bc99dc0e32f699e1a062d1aabddcaa4e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728326 Reviewed-by: Jeremy Bettis --- board/host/battery.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/host/battery.c b/board/host/battery.c index 58390133e4..93688973ed 100644 --- a/board/host/battery.c +++ b/board/host/battery.c @@ -14,8 +14,7 @@ static uint16_t mock_smart_battery[SB_MANUFACTURER_DATA + 1]; -int sb_i2c_xfer(int port, uint16_t addr_flags, - const uint8_t *out, int out_size, +int sb_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, int out_size, uint8_t *in, int in_size, int flags) { if (out_size == 0) @@ -23,7 +22,7 @@ int sb_i2c_xfer(int port, uint16_t addr_flags, if (port != I2C_PORT_BATTERY || addr_flags != BATTERY_ADDR_FLAGS) return EC_ERROR_INVAL; - if (out[0] >= ARRAY_SIZE(mock_smart_battery)) + if (out[0] >= ARRAY_SIZE(mock_smart_battery)) return EC_ERROR_UNIMPLEMENTED; if (out_size == 1) { /* Read */ @@ -56,12 +55,12 @@ static const struct battery_info bat_info = { * normal = 7.4V * min = 6.0V */ - .voltage_max = 8400, + .voltage_max = 8400, .voltage_normal = 7400, - .voltage_min = 6000, + .voltage_min = 6000, /* Pre-charge current: I <= 0.01C */ - .precharge_current = 64, /* mA */ + .precharge_current = 64, /* mA */ /* * Operational temperature range @@ -70,10 +69,10 @@ static const struct battery_info bat_info = { */ .start_charging_min_c = 0, .start_charging_max_c = 50, - .charging_min_c = 0, - .charging_max_c = 50, - .discharging_min_c = -20, - .discharging_max_c = 60, + .charging_min_c = 0, + .charging_max_c = 50, + .discharging_min_c = -20, + .discharging_max_c = 60, }; const struct battery_info *battery_get_info(void) -- cgit v1.2.1 From dcdfb1a1f1e139ada70863482071597ad1a3fd64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:17 -0600 Subject: test/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ica8750b1b26d67c5888d530999a17b585c035b89 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730475 Reviewed-by: Jeremy Bettis --- test/flash.c | 98 +++++++++++++++++++++++++++++++----------------------------- 1 file changed, 50 insertions(+), 48 deletions(-) diff --git a/test/flash.c b/test/flash.c index 4f9ca74016..a5f25fb164 100644 --- a/test/flash.c +++ b/test/flash.c @@ -103,60 +103,59 @@ static int verify_erase(int offset, int size) return EC_SUCCESS; } - -#define VERIFY_NO_WRITE(off, sz, d) \ - do { \ - record_flash(off, sz); \ +#define VERIFY_NO_WRITE(off, sz, d) \ + do { \ + record_flash(off, sz); \ TEST_ASSERT(host_command_write(off, sz, d) != EC_SUCCESS); \ - TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \ + TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \ } while (0) -#define VERIFY_NO_ERASE(off, sz) \ - do { \ - record_flash(off, sz); \ +#define VERIFY_NO_ERASE(off, sz) \ + do { \ + record_flash(off, sz); \ TEST_ASSERT(host_command_erase(off, sz) != EC_SUCCESS); \ - TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \ + TEST_ASSERT(verify_flash(off, sz) == EC_SUCCESS); \ } while (0) -#define VERIFY_WRITE(off, sz, d) \ - do { \ +#define VERIFY_WRITE(off, sz, d) \ + do { \ TEST_ASSERT(host_command_write(off, sz, d) == EC_SUCCESS); \ - TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS); \ + TEST_ASSERT(verify_write(off, sz, d) == EC_SUCCESS); \ } while (0) -#define VERIFY_ERASE(off, sz) \ - do { \ +#define VERIFY_ERASE(off, sz) \ + do { \ TEST_ASSERT(host_command_erase(off, sz) == EC_SUCCESS); \ - TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS); \ + TEST_ASSERT(verify_erase(off, sz) == EC_SUCCESS); \ } while (0) -#define SET_WP_FLAGS(m, f) \ - TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), \ - NULL, NULL, NULL) == EC_RES_SUCCESS) +#define SET_WP_FLAGS(m, f) \ + TEST_ASSERT(host_command_protect(m, ((f) ? m : 0), NULL, NULL, \ + NULL) == EC_RES_SUCCESS) -#define ASSERT_WP_FLAGS(f) \ - do { \ - uint32_t flags; \ +#define ASSERT_WP_FLAGS(f) \ + do { \ + uint32_t flags; \ TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \ - EC_RES_SUCCESS); \ - TEST_ASSERT(flags & (f)); \ + EC_RES_SUCCESS); \ + TEST_ASSERT(flags &(f)); \ } while (0) -#define ASSERT_WP_NO_FLAGS(f) \ - do { \ - uint32_t flags; \ +#define ASSERT_WP_NO_FLAGS(f) \ + do { \ + uint32_t flags; \ TEST_ASSERT(host_command_protect(0, 0, &flags, NULL, NULL) == \ - EC_RES_SUCCESS); \ - TEST_ASSERT((flags & (f)) == 0); \ + EC_RES_SUCCESS); \ + TEST_ASSERT((flags & (f)) == 0); \ } while (0) -#define VERIFY_REGION_INFO(r, o, s) \ - do { \ - uint32_t offset, size; \ +#define VERIFY_REGION_INFO(r, o, s) \ + do { \ + uint32_t offset, size; \ TEST_ASSERT(host_command_region_info(r, &offset, &size) == \ - EC_RES_SUCCESS); \ - TEST_ASSERT(offset == (o)); \ - TEST_ASSERT(size == (s)); \ + EC_RES_SUCCESS); \ + TEST_ASSERT(offset == (o)); \ + TEST_ASSERT(size == (s)); \ } while (0) int host_command_read(int offset, int size, char *out) @@ -195,9 +194,8 @@ int host_command_erase(int offset, int size) sizeof(params), NULL, 0); } -int host_command_protect(uint32_t mask, uint32_t flags, - uint32_t *flags_out, uint32_t *valid_out, - uint32_t *writable_out) +int host_command_protect(uint32_t mask, uint32_t flags, uint32_t *flags_out, + uint32_t *valid_out, uint32_t *writable_out) { struct ec_params_flash_protect params; struct ec_response_flash_protect resp; @@ -222,7 +220,7 @@ int host_command_protect(uint32_t mask, uint32_t flags, } int host_command_region_info(enum ec_flash_region reg, uint32_t *offset, - uint32_t *size) + uint32_t *size) { struct ec_params_flash_region_info params; struct ec_response_flash_region_info resp; @@ -350,8 +348,8 @@ static int test_flash_info(void) { struct ec_response_flash_info_1 resp; - TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, - &resp, sizeof(resp)) == EC_RES_SUCCESS); + TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, &resp, + sizeof(resp)) == EC_RES_SUCCESS); TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE_BYTES) && (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) && @@ -363,16 +361,17 @@ static int test_region_info(void) { VERIFY_REGION_INFO(EC_FLASH_REGION_RO, CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF, EC_FLASH_REGION_RO_SIZE); + CONFIG_RO_STORAGE_OFF, + EC_FLASH_REGION_RO_SIZE); VERIFY_REGION_INFO(EC_FLASH_REGION_ACTIVE, CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF, + CONFIG_RW_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_SIZE); - VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO, - CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE); + VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO, CONFIG_WP_STORAGE_OFF, + CONFIG_WP_STORAGE_SIZE); VERIFY_REGION_INFO(EC_FLASH_REGION_UPDATE, CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF, + CONFIG_RW_STORAGE_OFF, CONFIG_EC_WRITABLE_STORAGE_SIZE); return EC_SUCCESS; @@ -401,9 +400,11 @@ static int test_write_protect(void) /* Check we cannot erase anything */ TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF, - CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS); + CONFIG_FLASH_ERASE_SIZE) != + EC_SUCCESS); TEST_ASSERT(crec_flash_physical_erase(CONFIG_RW_STORAGE_OFF, - CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS); + CONFIG_FLASH_ERASE_SIZE) != + EC_SUCCESS); /* We should not even try to write/erase */ VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE); @@ -419,7 +420,8 @@ static int test_boot_write_protect(void) /* Check write protect state persists through reboot */ ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT); TEST_ASSERT(crec_flash_physical_erase(CONFIG_RO_STORAGE_OFF, - CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS); + CONFIG_FLASH_ERASE_SIZE) != + EC_SUCCESS); return EC_SUCCESS; } -- cgit v1.2.1 From 2eb12ab2f412687cd977621b92f352fec5e3d36c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:05 -0600 Subject: chip/stm32/usart-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11ab828955d9148c63e568173b94d8e5ee70cad4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729414 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32f3.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/chip/stm32/usart-stm32f3.c b/chip/stm32/usart-stm32f3.c index 887d79d21f..7bc6a8c8f5 100644 --- a/chip/stm32/usart-stm32f3.c +++ b/chip/stm32/usart-stm32f3.c @@ -22,7 +22,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -50,7 +50,7 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; @@ -72,12 +72,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -90,12 +90,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -108,12 +108,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif -- cgit v1.2.1 From 6ceb80f8e75d8410c00ba6645aed3d5d929e4d36 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:49 -0600 Subject: board/pdeval-stm32f072/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37dfe31f1567bc0cf7c1d67b513b0c3d8132816e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728819 Reviewed-by: Jeremy Bettis --- board/pdeval-stm32f072/usb_pd_policy.c | 53 ++++++++++++++-------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/board/pdeval-stm32f072/usb_pd_policy.c b/board/pdeval-stm32f072/usb_pd_policy.c index b7425ce66c..58bc05b990 100644 --- a/board/pdeval-stm32f072/usb_pd_policy.c +++ b/board/pdeval-stm32f072/usb_pd_policy.c @@ -17,18 +17,17 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Used to fake VBUS presence since no GPIO is available to read VBUS */ static int vbus_present; - #if defined(CONFIG_USB_PD_TCPM_MUX) && defined(CONFIG_USB_PD_TCPM_ANX7447) const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { .usb_port = 0, - .driver = &anx7447_usb_mux_driver, + .driver = &anx7447_usb_mux_driver, }, }; #endif @@ -81,8 +80,8 @@ void pd_power_supply_reset(int port) void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) { - CPRINTS("USBPD current limit port %d max %d mA %d mV", - port, max_ma, supply_voltage); + CPRINTS("USBPD current limit port %d max %d mA %d mV", port, max_ma, + supply_voltage); /* do some LED coding of the power we can sink */ if (max_ma) { if (supply_voltage > 6500) @@ -98,8 +97,8 @@ void pd_set_input_current_limit(int port, uint32_t max_ma, __override void typec_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) { - CPRINTS("TYPEC current limit port %d max %d mA %d mV", - port, max_ma, supply_voltage); + CPRINTS("TYPEC current limit port %d max %d mA %d mV", port, max_ma, + supply_voltage); gpio_set_level(GPIO_LED_R, !!max_ma); } @@ -116,17 +115,14 @@ static int command_vbus_toggle(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle, - "", - "Toggle VBUS detected"); +DECLARE_CONSOLE_COMMAND(vbus, command_vbus_toggle, "", "Toggle VBUS detected"); int pd_snk_is_vbus_provided(int port) { return vbus_present; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap */ return 1; @@ -144,22 +140,18 @@ int pd_check_vconn_swap(int port) } #endif -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { } /* ----------------- Vendor Defined Messages ------------------ */ const uint32_t vdo_idh = VDO_IDH(1, /* data caps as USB host */ 0, /* data caps as USB device */ - IDH_PTYPE_PERIPH, - 0, /* supports alt modes */ + IDH_PTYPE_PERIPH, 0, /* supports alt modes */ 0x0000); const uint32_t vdo_product = VDO_PRODUCT(0x0000, 0x0000); @@ -233,11 +225,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * board_set_usb_mux(port, USB_PD_MUX_DP_ENABLED, * polarity_rm_dts(pd_get_polarity(port))); */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; } @@ -252,9 +244,9 @@ __override void svdm_dp_post_config(int port) /* Note: Usage is deprecated, use usb_mux_hpd_update instead */ if (IS_ENABLED(CONFIG_USB_PD_TCPM_ANX7447)) - anx7447_tcpc_update_hpd_status(mux, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED, - &unused); + anx7447_tcpc_update_hpd_status( + mux, USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED, + &unused); } __override int svdm_dp_attention(int port, uint32_t *payload) @@ -265,10 +257,9 @@ __override int svdm_dp_attention(int port, uint32_t *payload) const struct usb_mux *mux = &usb_muxes[port]; bool unused; - mux_state_t mux_state = (lvl ? USB_PD_MUX_HPD_LVL : - USB_PD_MUX_HPD_LVL_DEASSERTED) | - (irq ? USB_PD_MUX_HPD_IRQ : - USB_PD_MUX_HPD_IRQ_DEASSERTED); + mux_state_t mux_state = + (lvl ? USB_PD_MUX_HPD_LVL : USB_PD_MUX_HPD_LVL_DEASSERTED) | + (irq ? USB_PD_MUX_HPD_IRQ : USB_PD_MUX_HPD_IRQ_DEASSERTED); /* Note: Usage is deprecated, use usb_mux_hpd_update instead */ CPRINTS("Attention: 0x%x", payload[1]); -- cgit v1.2.1 From af099c13377b25b3948acff3ad512b253f263f85 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:41 -0600 Subject: board/eve/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2f35e3496c3f4a201c734457ca4d12040fea8c7a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728348 Reviewed-by: Jeremy Bettis --- board/eve/usb_pd_policy.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/board/eve/usb_pd_policy.c b/board/eve/usb_pd_policy.c index d6dd5ad1be..2a47a73074 100644 --- a/board/eve/usb_pd_policy.c +++ b/board/eve/usb_pd_policy.c @@ -23,12 +23,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port) static void board_vbus_update_source_current(int port) { enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN; + GPIO_USB_C0_5V_EN; enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A : - GPIO_EN_USB_C0_3A; + GPIO_EN_USB_C0_3A; int flags; if (system_get_board_version() >= BOARD_VERSION_P1B) { @@ -50,8 +50,8 @@ static void board_vbus_update_source_current(int port) * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals * can remain outputs. */ - gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? - 1 : 0); + gpio_set_level(gpio_3a_en, + vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0); gpio_set_level(gpio_5v_en, vbus_en[port]); } else { /* @@ -65,8 +65,8 @@ static void board_vbus_update_source_current(int port) * 1505 mA. */ flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : - (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); gpio_set_level(gpio_5v_en, vbus_en[port]); gpio_set_flags(gpio_5v_en, flags); } @@ -120,15 +120,13 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_PMIC_SLP_SUS_L); } -void pd_execute_data_swap(int port, - enum pd_data_role data_role) +void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) return; - gpio_set_level(GPIO_USB2_OTG_ID, - (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0); gpio_set_level(GPIO_USB2_OTG_VBUSSENSE, - (data_role == PD_ROLE_UFP) ? 1 : 0); + (data_role == PD_ROLE_UFP) ? 1 : 0); } -- cgit v1.2.1 From 713821db50a3538bc8c925328b3ab0a444c90e4e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:15 -0600 Subject: zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4bd9171866f92c0f126ed6fb149afc6006e33ca7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730676 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h | 74 ++++++++++++++--------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h index dc4fcd24fc..433f2a355a 100644 --- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h +++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.h @@ -6,53 +6,53 @@ #ifndef __CROS_EC_RTC_PCF85063A_H #define __CROS_EC_RTC_PCF85063A_H -#define PCF85063A_REG_NUM 18 -#define SOFT_RESET 0x58 +#define PCF85063A_REG_NUM 18 +#define SOFT_RESET 0x58 #define CONTROL_1_DEFAULT_VALUE 0 -#define OS_BIT 0x80 -#define DISABLE_ALARM 0x80 -#define ENABLE_ALARM_INTERRUPT 0x80 -#define RTC_STOP_CLOCKS 0x20 -#define RTC_START_CLOCKS 0x00 +#define OS_BIT 0x80 +#define DISABLE_ALARM 0x80 +#define ENABLE_ALARM_INTERRUPT 0x80 +#define RTC_STOP_CLOCKS 0x20 +#define RTC_START_CLOCKS 0x00 -#define NUM_TIMER_REGS 7 -#define NUM_ALARM_REGS 4 +#define NUM_TIMER_REGS 7 +#define NUM_ALARM_REGS 4 -#define REG_CONTROL_1 0x00 -#define REG_CONTROL_2 0x01 -#define REG_OFFSET 0x02 -#define REG_RAM_BYTE 0x03 -#define REG_SECONDS 0x04 -#define REG_MINUTES 0x05 -#define REG_HOURS 0x06 -#define REG_DAYS 0x07 -#define REG_WEEKDAYS 0x08 -#define REG_MONTHS 0x09 -#define REG_YEARS 0x0a -#define REG_SECOND_ALARM 0x0b -#define REG_MINUTE_ALARM 0x0c -#define REG_HOUR_ALARM 0x0d -#define REG_DAY_ALARM 0x0e -#define REG_WEEKDAY_ALARM 0x0f -#define REG_TIMER_VALUE 0x10 -#define REG_TIMER_MODE 0x11 +#define REG_CONTROL_1 0x00 +#define REG_CONTROL_2 0x01 +#define REG_OFFSET 0x02 +#define REG_RAM_BYTE 0x03 +#define REG_SECONDS 0x04 +#define REG_MINUTES 0x05 +#define REG_HOURS 0x06 +#define REG_DAYS 0x07 +#define REG_WEEKDAYS 0x08 +#define REG_MONTHS 0x09 +#define REG_YEARS 0x0a +#define REG_SECOND_ALARM 0x0b +#define REG_MINUTE_ALARM 0x0c +#define REG_HOUR_ALARM 0x0d +#define REG_DAY_ALARM 0x0e +#define REG_WEEKDAY_ALARM 0x0f +#define REG_TIMER_VALUE 0x10 +#define REG_TIMER_MODE 0x11 /* Macros for indexing time_reg buffer */ -#define SECONDS 0 -#define MINUTES 1 -#define HOURS 2 -#define DAYS 3 -#define WEEKDAYS 4 -#define MONTHS 5 -#define YEARS 6 +#define SECONDS 0 +#define MINUTES 1 +#define HOURS 2 +#define DAYS 3 +#define WEEKDAYS 4 +#define MONTHS 5 +#define YEARS 6 enum bcd_mask { SECONDS_MASK = 0x70, MINUTES_MASK = 0x70, HOURS24_MASK = 0x30, - DAYS_MASK = 0x30, - MONTHS_MASK = 0x10, - YEARS_MASK = 0xf0 + DAYS_MASK = 0x30, + MONTHS_MASK = 0x10, + YEARS_MASK = 0xf0 }; #endif /* __CROS_EC_RTC_PCF85063A_H */ -- cgit v1.2.1 From d67a121d70b86be218841a8a268eeff3b3210a00 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:54 -0600 Subject: board/elemi/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I993bacaaf1e51b70eff405b0ecfb4b8bbf42168f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728288 Reviewed-by: Jeremy Bettis --- board/elemi/board.h | 93 ++++++++++++++++++++++++----------------------------- 1 file changed, 42 insertions(+), 51 deletions(-) diff --git a/board/elemi/board.h b/board/elemi/board.h index 1556a802b6..3699c52fb3 100644 --- a/board/elemi/board.h +++ b/board/elemi/board.h @@ -37,31 +37,31 @@ #undef CONFIG_ACCEL_FIFO_SIZE /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* Experimentally determined. See b/186079130. */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 10000 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 10000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #undef CONFIG_USB_PD_TCPM_TUSB422 #undef CONFIG_USB_MUX_RUNTIME_CONFIG @@ -74,8 +74,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -90,41 +90,40 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -136,17 +135,9 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From 8f58c9fdbd25dfeee1383d333f94c5d638ce5e96 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:42 -0600 Subject: core/host/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23fe8333715fa67e5d6888fb1a2e979f329d946d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729844 Reviewed-by: Jeremy Bettis --- core/host/task.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/core/host/task.c b/core/host/task.c index f8f8dfb661..4af894d6c3 100644 --- a/core/host/task.c +++ b/core/host/task.c @@ -96,22 +96,18 @@ void _run_test(void *d) run_test(0, NULL); } -#define TASK(n, r, d, s) {r, d}, +#define TASK(n, r, d, s) { r, d }, const struct task_args task_info[TASK_ID_COUNT] = { - {__idle, NULL}, - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST - {_run_test, NULL}, + { __idle, NULL }, + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST{ _run_test, + NULL }, }; #undef TASK #define TASK(n, r, d, s) #n, -static const char * const task_names[] = { +static const char *const task_names[] = { "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST "<< test runner >>", }; #undef TASK @@ -325,8 +321,7 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); static void _wait_for_task_started(int can_sleep) @@ -519,8 +514,8 @@ int task_start(void) */ pthread_mutex_lock(&interrupt_lock); - pthread_create(&interrupt_thread, NULL, - _task_int_generator_start, NULL); + pthread_create(&interrupt_thread, NULL, _task_int_generator_start, + NULL); /* * Tell the hooks task to continue so that it can call back to enable @@ -557,7 +552,6 @@ static void task_enable_all_tasks_callback(void) pthread_mutex_unlock(&interrupt_lock); pthread_cond_wait(&scheduler_cond, &run_lock); } - } void task_enable_all_tasks(void) -- cgit v1.2.1 From 39686fd0920961ed36a0deabaa32c72fa17727e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:06 -0600 Subject: common/gesture.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc1f02eaa545582bd1ddc723884e0cab48493d76 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729651 Reviewed-by: Jeremy Bettis --- common/gesture.c | 48 ++++++++++++++++++++---------------------------- 1 file changed, 20 insertions(+), 28 deletions(-) diff --git a/common/gesture.c b/common/gesture.c index 0ccd358d54..215159d061 100644 --- a/common/gesture.c +++ b/common/gesture.c @@ -19,9 +19,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_GESTURE, outstr) -#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_GESTURE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_GESTURE, format, ##args) /* * Double tap detection parameters @@ -34,16 +33,16 @@ * which to check for relatively calm periods. In between the two impulses * there is a minimum and maximum interstice time allowed. */ -#define OUTER_WINDOW \ +#define OUTER_WINDOW \ (CONFIG_GESTURE_TAP_OUTER_WINDOW_T / \ CONFIG_GESTURE_SAMPLING_INTERVAL_MS) -#define INNER_WINDOW \ +#define INNER_WINDOW \ (CONFIG_GESTURE_TAP_INNER_WINDOW_T / \ CONFIG_GESTURE_SAMPLING_INTERVAL_MS) -#define MIN_INTERSTICE \ +#define MIN_INTERSTICE \ (CONFIG_GESTURE_TAP_MIN_INTERSTICE_T / \ CONFIG_GESTURE_SAMPLING_INTERVAL_MS) -#define MAX_INTERSTICE \ +#define MAX_INTERSTICE \ (CONFIG_GESTURE_TAP_MAX_INTERSTICE_T / \ CONFIG_GESTURE_SAMPLING_INTERVAL_MS) #define MAX_WINDOW OUTER_WINDOW @@ -67,10 +66,10 @@ enum tap_states { /* Tap sensor to use */ static struct motion_sensor_t *sensor = -&motion_sensors[CONFIG_GESTURE_TAP_SENSOR]; + &motion_sensors[CONFIG_GESTURE_TAP_SENSOR]; /* Tap state information */ -static int history_z[MAX_WINDOW]; /* Changes in Z */ +static int history_z[MAX_WINDOW]; /* Changes in Z */ static int history_xy[MAX_WINDOW]; /* Changes in X and Y */ static int state, history_idx; static int history_initialized, history_init_index; @@ -166,7 +165,7 @@ static int gesture_tap_for_battery(void) (OUTER_WINDOW - INNER_WINDOW); delta_z_inner = sum_z_inner * 1000 / INNER_WINDOW; delta_xy_outer = (sum_xy_outer - sum_xy_inner) * 1000 / - (OUTER_WINDOW - INNER_WINDOW); + (OUTER_WINDOW - INNER_WINDOW); delta_xy_inner = sum_xy_inner * 1000 / INNER_WINDOW; state_cnt++; @@ -253,13 +252,11 @@ static int gesture_tap_for_battery(void) } /* On state transitions, print debug info */ - if (tap_debug && - (state != state_p || - (state_cnt % 10000 == 9999))) { + if (tap_debug && (state != state_p || (state_cnt % 10000 == 9999))) { /* make sure we don't divide by 0 */ if (delta_z_outer == 0 || delta_xy_inner == 0) - CPRINTS("tap st %d->%d, error div by 0", - state_p, state); + CPRINTS("tap st %d->%d, error div by 0", state_p, + state); else CPRINTS("tap st %d->%d, st_cnt %-3d " "Z_in:Z_out %-3d, Z_in:XY_in %-3d " @@ -267,10 +264,8 @@ static int gesture_tap_for_battery(void) "dZ_out %-8.3d", state_p, state, state_cnt, delta_z_inner / delta_z_outer, - delta_z_inner / delta_xy_inner, - delta_z_inner, - delta_z_inner_max, - delta_z_outer); + delta_z_inner / delta_xy_inner, delta_z_inner, + delta_z_inner_max, delta_z_outer); } return ret; @@ -281,8 +276,7 @@ static void gesture_chipset_resume(void) /* disable tap detection */ tap_detection = 0; } -DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume, - GESTURE_HOOK_PRIO); +DECLARE_HOOK(HOOK_CHIPSET_RESUME, gesture_chipset_resume, GESTURE_HOOK_PRIO); static void gesture_chipset_suspend(void) { @@ -295,8 +289,7 @@ static void gesture_chipset_suspend(void) state = TAP_IDLE; tap_detection = 1; } -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend, - GESTURE_HOOK_PRIO); +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, gesture_chipset_suspend, GESTURE_HOOK_PRIO); void gesture_calc(uint32_t *event) { @@ -306,7 +299,7 @@ void gesture_calc(uint32_t *event) if (gesture_tap_for_battery()) *event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_DOUBLE_TAP); + MOTIONSENSE_ACTIVITY_DOUBLE_TAP); } /*****************************************************************************/ @@ -315,8 +308,8 @@ static int command_tap_info(int argc, char **argv) { int val; - ccprintf("tap: %s\n", (tap_detection && !lid_is_open()) ? - "on" : "off"); + ccprintf("tap: %s\n", + (tap_detection && !lid_is_open()) ? "on" : "off"); if (argc > 1) { if (!parse_bool(argv[1], &val)) @@ -329,6 +322,5 @@ static int command_tap_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info, - "debug on/off", +DECLARE_CONSOLE_COMMAND(tapinfo, command_tap_info, "debug on/off", "Print tap information"); -- cgit v1.2.1 From 677b4ea1739f1edb951b21eec7cf38769a0308ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:18 -0600 Subject: include/task.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I648016ac91321e271ae99c07a0a0033b73a7c520 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730416 Reviewed-by: Jeremy Bettis --- include/task.h | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/include/task.h b/include/task.h index 0343644437..1b5d83796c 100644 --- a/include/task.h +++ b/include/task.h @@ -22,48 +22,47 @@ #define TASK_EVENT_SYSJUMP_READY BIT(16) /* Used to signal that IPC layer is available for sending new data */ -#define TASK_EVENT_IPC_READY BIT(17) +#define TASK_EVENT_IPC_READY BIT(17) -#define TASK_EVENT_PD_AWAKE BIT(18) +#define TASK_EVENT_PD_AWAKE BIT(18) /* npcx peci event */ -#define TASK_EVENT_PECI_DONE BIT(19) +#define TASK_EVENT_PECI_DONE BIT(19) /* I2C tx/rx interrupt handler completion event. */ #ifdef CHIP_STM32 -#define TASK_EVENT_I2C_COMPLETION(port) \ - (1 << ((port) + 20)) -#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0)) -#define TASK_EVENT_MAX_I2C 6 +#define TASK_EVENT_I2C_COMPLETION(port) (1 << ((port) + 20)) +#define TASK_EVENT_I2C_IDLE (TASK_EVENT_I2C_COMPLETION(0)) +#define TASK_EVENT_MAX_I2C 6 #ifdef I2C_PORT_COUNT #if (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) #error "Too many i2c ports for i2c events" #endif #endif #else -#define TASK_EVENT_I2C_IDLE BIT(20) -#define TASK_EVENT_PS2_DONE BIT(21) +#define TASK_EVENT_I2C_IDLE BIT(20) +#define TASK_EVENT_PS2_DONE BIT(21) #endif /* DMA transmit complete event */ -#define TASK_EVENT_DMA_TC BIT(26) +#define TASK_EVENT_DMA_TC BIT(26) /* ADC interrupt handler event */ -#define TASK_EVENT_ADC_DONE BIT(27) +#define TASK_EVENT_ADC_DONE BIT(27) /* * task_reset() that was requested has been completed * * For test-only builds, may be used by some tasks to restart themselves. */ -#define TASK_EVENT_RESET_DONE BIT(28) +#define TASK_EVENT_RESET_DONE BIT(28) /* task_wake() called on task */ -#define TASK_EVENT_WAKE BIT(29) +#define TASK_EVENT_WAKE BIT(29) /* Mutex unlocking */ -#define TASK_EVENT_MUTEX BIT(30) +#define TASK_EVENT_MUTEX BIT(30) /* * Timer expired. For example, task_wait_event() timed out before receiving * another event. */ -#define TASK_EVENT_TIMER (1U << 31) +#define TASK_EVENT_TIMER (1U << 31) /* Maximum time for task_wait_event() */ #define TASK_MAX_WAIT_US 0x7fffffff @@ -402,7 +401,7 @@ typedef struct mutex mutex_t; * initialize it. We provide the same macro for CrOS EC OS so that we * can use it in shared code. */ -#define K_MUTEX_DEFINE(name) static mutex_t name = { } +#define K_MUTEX_DEFINE(name) static mutex_t name = {} /** * Lock a mutex. @@ -456,8 +455,8 @@ struct irq_def { #define IRQ_HANDLER(irqname) CONCAT3(irq_, irqname, _handler) #define IRQ_HANDLER_OPT(irqname) CONCAT3(irq_, irqname, _handler_optional) #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority) -#define DECLARE_IRQ_(irq, routine, priority) \ - static void __keep routine(void); \ +#define DECLARE_IRQ_(irq, routine, priority) \ + static void __keep routine(void); \ void IRQ_HANDLER_OPT(irq)(void) __attribute__((alias(#routine))) /* Include ec.irqlist here for compilation dependency */ @@ -468,4 +467,4 @@ struct irq_def { #endif /* CONFIG_COMMON_RUNTIME */ #endif /* !CONFIG_ZEPHYR */ -#endif /* __CROS_EC_TASK_H */ +#endif /* __CROS_EC_TASK_H */ -- cgit v1.2.1 From ea46594b57ad313a8f94ac15008da3fccf8a49ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:45 -0600 Subject: board/nucleo-dartmonkey/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie51fe8cafa8f9835dfd1c9ae851e89493c657206 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728773 Reviewed-by: Jeremy Bettis --- board/nucleo-dartmonkey/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/nucleo-dartmonkey/board.c b/board/nucleo-dartmonkey/board.c index ea0d11eaf5..59226cea56 100644 --- a/board/nucleo-dartmonkey/board.c +++ b/board/nucleo-dartmonkey/board.c @@ -38,8 +38,8 @@ static void ap_deferred(void) * in S0: SLP_ALT_L is 1 and SLP_L is 1. * in S5/G3, the FP MCU should not be running. */ - int running = gpio_get_level(GPIO_SLP_ALT_L) - && gpio_get_level(GPIO_SLP_L); + int running = gpio_get_level(GPIO_SLP_ALT_L) && + gpio_get_level(GPIO_SLP_L); if (running) { /* S0 */ disable_sleep(SLEEP_MASK_AP_RUN); @@ -92,7 +92,7 @@ static void board_init(void) spi_configure(); ccprints("TRANSPORT_SEL: %s", - fp_transport_type_to_str(get_fp_transport_type())); + fp_transport_type_to_str(get_fp_transport_type())); /* Enable interrupt on PCH power signals */ gpio_enable_interrupt(GPIO_SLP_ALT_L); -- cgit v1.2.1 From cee392b1f8f3336e2484424101d91c627bd60139 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:53 -0600 Subject: chip/stm32/flash-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40e27b5997c08a9f8a9574504cf16215020c30f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729498 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32f4.c | 198 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 197 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/flash-stm32f4.c diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c deleted file mode 120000 index 6ff8130e17..0000000000 --- a/chip/stm32/flash-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -flash-stm32f3.c \ No newline at end of file diff --git a/chip/stm32/flash-stm32f4.c b/chip/stm32/flash-stm32f4.c new file mode 100644 index 0000000000..cfed457162 --- /dev/null +++ b/chip/stm32/flash-stm32f4.c @@ -0,0 +1,197 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Flash memory module for stm32f3 and stm32f4 */ + +#include +#include "common.h" +#include "flash.h" +#include "flash-f.h" +#include "flash-regs.h" +#include "hooks.h" +#include "registers.h" +#include "system.h" +#include "panic.h" + +/*****************************************************************************/ +/* Physical layer APIs */ +#ifdef CHIP_VARIANT_STM32F76X +/* + * 8 "erase" sectors : 32KB/32KB/32KB/32KB/128KB/256KB/256KB/256KB + */ +struct ec_flash_bank const flash_bank_array[] = { + { + .count = 4, + .size_exp = __fls(SIZE_32KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_32KB), + .protect_size_exp = __fls(SIZE_32KB), + }, + { + .count = 1, + .size_exp = __fls(SIZE_128KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_128KB), + .protect_size_exp = __fls(SIZE_128KB), + }, + { + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_256KB) / SIZE_256KB, + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .size_exp = __fls(SIZE_256KB), + .erase_size_exp = __fls(SIZE_256KB), + .protect_size_exp = __fls(SIZE_256KB), + }, +}; +#elif defined(CHIP_FAMILY_STM32F4) +/* + * STM32F412xE has 512 KB flash + * 8 "erase" sectors (512 KB) : 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB + * + * STM32F412xG has 1 MB flash + * 12 "erase" sectors (1024 KB) : + * 16KB/16KB/16KB/16KB/64KB/128KB/128KB/128KB/128KB/128KB/128KB/128KB + * + * https://www.st.com/resource/en/datasheet/stm32f412cg.pdf + */ +struct ec_flash_bank const flash_bank_array[] = { + { + .count = 4, + .size_exp = __fls(SIZE_16KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_16KB), + .protect_size_exp = __fls(SIZE_16KB), + }, + { + .count = 1, + .size_exp = __fls(SIZE_64KB), + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .erase_size_exp = __fls(SIZE_64KB), + .protect_size_exp = __fls(SIZE_64KB), + }, + { + .count = (CONFIG_FLASH_SIZE_BYTES - SIZE_128KB) / SIZE_128KB, + .write_size_exp = __fls(CONFIG_FLASH_WRITE_SIZE), + .size_exp = __fls(SIZE_128KB), + .erase_size_exp = __fls(SIZE_128KB), + .protect_size_exp = __fls(SIZE_128KB), + }, +}; +#endif + +/* Flag indicating whether we have locked down entire flash */ +static int entire_flash_locked; + +#define FLASH_SYSJUMP_TAG 0x5750 /* "WP" - Write Protect */ +#define FLASH_HOOK_VERSION 1 + +/* The previous write protect state before sys jump */ +struct flash_wp_state { + int entire_flash_locked; +}; + +/*****************************************************************************/ +/* Physical layer APIs */ + +int crec_flash_physical_get_protect(int block) +{ + return (entire_flash_locked || +#if defined(CHIP_FAMILY_STM32F3) + !(STM32_FLASH_WRPR & BIT(block)) +#elif defined(CHIP_FAMILY_STM32F4) + !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) +#endif + ); +} + +uint32_t crec_flash_physical_get_protect_flags(void) +{ + uint32_t flags = 0; + + /* Read all-protected state from our shadow copy */ + if (entire_flash_locked) + flags |= EC_FLASH_PROTECT_ALL_NOW; + +#if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) + if (is_flash_rdp_enabled()) + flags |= EC_FLASH_PROTECT_RO_AT_BOOT; +#endif + + return flags; +} + +int crec_flash_physical_protect_now(int all) +{ + if (all) { + disable_flash_control_register(); + entire_flash_locked = 1; + + return EC_SUCCESS; + } + + disable_flash_option_bytes(); + + return EC_SUCCESS; +} + +uint32_t crec_flash_physical_get_valid_flags(void) +{ + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | + EC_FLASH_PROTECT_ALL_NOW; +} + +uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) +{ + uint32_t ret = 0; + + /* If RO protection isn't enabled, its at-boot state can be changed. */ + if (!(cur_flags & EC_FLASH_PROTECT_RO_NOW)) + ret |= EC_FLASH_PROTECT_RO_AT_BOOT; + + /* + * If entire flash isn't protected at this boot, it can be enabled if + * the WP GPIO is asserted. + */ + if (!(cur_flags & EC_FLASH_PROTECT_ALL_NOW) && + (cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED)) + ret |= EC_FLASH_PROTECT_ALL_NOW; + + return ret; +} + +int crec_flash_physical_restore_state(void) +{ + uint32_t reset_flags = system_get_reset_flags(); + int version, size; + const struct flash_wp_state *prev; + + /* + * If we have already jumped between images, an earlier image could + * have applied write protection. Nothing additional needs to be done. + */ + if (reset_flags & EC_RESET_FLAG_SYSJUMP) { + prev = (const struct flash_wp_state *)system_get_jump_tag( + FLASH_SYSJUMP_TAG, &version, &size); + if (prev && version == FLASH_HOOK_VERSION && + size == sizeof(*prev)) + entire_flash_locked = prev->entire_flash_locked; + return 1; + } + + return 0; +} + +/*****************************************************************************/ +/* Hooks */ + +static void flash_preserve_state(void) +{ + struct flash_wp_state state; + + state.entire_flash_locked = entire_flash_locked; + + system_add_jump_tag(FLASH_SYSJUMP_TAG, FLASH_HOOK_VERSION, + sizeof(state), &state); +} +DECLARE_HOOK(HOOK_SYSJUMP, flash_preserve_state, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 1179d6e401d45f4a4dcc886b1eb68f2d4b5ec604 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:52 -0600 Subject: board/fizz/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6eb39f7ad208dfa10c1af6f861f2b4c4a6b4feba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728369 Reviewed-by: Jeremy Bettis --- board/fizz/usb_pd_pdo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/fizz/usb_pd_pdo.c b/board/fizz/usb_pd_pdo.c index bb612affef..b117ac6c7a 100644 --- a/board/fizz/usb_pd_pdo.c +++ b/board/fizz/usb_pd_pdo.c @@ -7,8 +7,8 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), -- cgit v1.2.1 From 4ac51e4f2afe51484b13c9876ad8b3a77dbb95fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:22 -0600 Subject: driver/temp_sensor/tmp006.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iadb01a42070f78841035fc69e56e4e3333b80eeb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729878 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp006.c | 98 +++++++++++++++++++-------------------------- 1 file changed, 41 insertions(+), 57 deletions(-) diff --git a/driver/temp_sensor/tmp006.c b/driver/temp_sensor/tmp006.c index 96922c857c..265d9d804e 100644 --- a/driver/temp_sensor/tmp006.c +++ b/driver/temp_sensor/tmp006.c @@ -19,7 +19,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) /* * Alg 0 was what's in the TMP006 User's Guide. Alg 1 is Alg 0, but with @@ -30,23 +30,23 @@ #define ALGORITHM_PARAMS 12 /* Flags for tdata->fail */ -#define FAIL_INIT BIT(0) /* Just initialized */ -#define FAIL_POWER BIT(1) /* Sensor not powered */ -#define FAIL_I2C BIT(2) /* I2C communication error */ -#define FAIL_NOT_READY BIT(3) /* Data not ready */ +#define FAIL_INIT BIT(0) /* Just initialized */ +#define FAIL_POWER BIT(1) /* Sensor not powered */ +#define FAIL_I2C BIT(2) /* I2C communication error */ +#define FAIL_NOT_READY BIT(3) /* Data not ready */ /* State and conversion factors to track for each sensor */ struct tmp006_data_t { /* chip info */ - int16_t v_raw; /* TMP006_REG_VOBJ */ - int16_t t_raw0; /* TMP006_REG_TDIE */ - int fail; /* Fail flags; non-zero if last read failed */ + int16_t v_raw; /* TMP006_REG_VOBJ */ + int16_t t_raw0; /* TMP006_REG_TDIE */ + int fail; /* Fail flags; non-zero if last read failed */ /* calibration params */ - float s0, a1, a2; /* Sensitivity factors */ - float b0, b1, b2; /* Self-heating correction */ - float c2; /* Seebeck effect */ - float d0, d1, ds; /* Tdie filter and slope adjustment */ - float e0, e1; /* Tobj output filter */ + float s0, a1, a2; /* Sensitivity factors */ + float b0, b1, b2; /* Self-heating correction */ + float c2; /* Seebeck effect */ + float d0, d1, ds; /* Tdie filter and slope adjustment */ + float e0, e1; /* Tobj output filter */ /* FIR filter stages */ float tdie1, tobj1; }; @@ -57,7 +57,7 @@ static const struct tmp006_data_t tmp006_data_default = { .fail = FAIL_INIT, /* Alg 0 params from User's Guide */ - .s0 = 0.0f, /* zero == "uncalibrated" */ + .s0 = 0.0f, /* zero == "uncalibrated" */ .a1 = 1.75e-3f, .a2 = -1.678e-5f, .b0 = -2.94e-5f, @@ -104,8 +104,7 @@ static void tmp006_poll_sensor(int sensor_id) * data ready; otherwise, we read garbage data. */ if (tdata->fail & (FAIL_POWER | FAIL_INIT)) { - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_CONFIG, &v); if (rv) { tdata->fail |= FAIL_I2C; @@ -117,16 +116,14 @@ static void tmp006_poll_sensor(int sensor_id) } } - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_TDIE, &t); if (rv) { tdata->fail |= FAIL_I2C; return; } - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_VOBJ, &v); if (rv) { tdata->fail |= FAIL_I2C; @@ -179,8 +176,7 @@ static int tmp006_read_die_temp_k(const struct tmp006_data_t *tdata, * This uses Tdie and Vobj and a bunch of magic parameters to calculate the * object temperature, Tobj. */ -static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata, - int *temp_ptr) +static int tmp006_read_object_temp_k(struct tmp006_data_t *tdata, int *temp_ptr) { float tdie, vobj; float tx, s, vos, vx, fv, tobj, t4; @@ -251,7 +247,7 @@ int tmp006_get_val(int idx, int *temp_ptr) * an I2C error. */ return (tdata->fail & FAIL_I2C) ? EC_ERROR_UNKNOWN : - EC_ERROR_NOT_POWERED; + EC_ERROR_NOT_POWERED; } /* Check the low bit to determine which temperature to read. */ @@ -277,26 +273,24 @@ static enum ec_status tmp006_get_calibration(struct host_cmd_handler_args *args) r1->algorithm = ALGORITHM_NUM; r1->num_params = ALGORITHM_PARAMS; - r1->val[0] = tdata->s0; - r1->val[1] = tdata->a1; - r1->val[2] = tdata->a2; - r1->val[3] = tdata->b0; - r1->val[4] = tdata->b1; - r1->val[5] = tdata->b2; - r1->val[6] = tdata->c2; - r1->val[7] = tdata->d0; - r1->val[8] = tdata->d1; - r1->val[9] = tdata->ds; + r1->val[0] = tdata->s0; + r1->val[1] = tdata->a1; + r1->val[2] = tdata->a2; + r1->val[3] = tdata->b0; + r1->val[4] = tdata->b1; + r1->val[5] = tdata->b2; + r1->val[6] = tdata->c2; + r1->val[7] = tdata->d0; + r1->val[8] = tdata->d1; + r1->val[9] = tdata->ds; r1->val[10] = tdata->e0; r1->val[11] = tdata->e1; - args->response_size = sizeof(*r1) + - r1->num_params * sizeof(r1->val[0]); + args->response_size = sizeof(*r1) + r1->num_params * sizeof(r1->val[0]); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION, - tmp006_get_calibration, +DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_CALIBRATION, tmp006_get_calibration, EC_VER_MASK(1)); static enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args) @@ -329,8 +323,7 @@ static enum ec_status tmp006_set_calibration(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION, - tmp006_set_calibration, +DECLARE_HOST_COMMAND(EC_CMD_TMP006_SET_CALIBRATION, tmp006_set_calibration, EC_VER_MASK(1)); static enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args) @@ -356,9 +349,7 @@ static enum ec_status tmp006_get_raw(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW, - tmp006_get_raw, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_TMP006_GET_RAW, tmp006_get_raw, EC_VER_MASK(0)); /*****************************************************************************/ /* Console commands */ @@ -375,7 +366,6 @@ static int tmp006_print(int idx) int d; int addr_flags = tmp006_sensors[idx].addr_flags; - ccprintf("Debug data from %s:\n", tmp006_sensors[idx].name); if (!tmp006_has_power(idx)) { @@ -383,36 +373,31 @@ static int tmp006_print(int idx) return EC_ERROR_UNKNOWN; } - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_MANUFACTURER_ID, &d); if (rv) return rv; ccprintf(" Manufacturer ID: 0x%04x\n", d); - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_DEVICE_ID, &d); ccprintf(" Device ID: 0x%04x\n", d); - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_CONFIG, &d); ccprintf(" Config: 0x%04x\n", d); - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_VOBJ, &vraw); v = ((int)vraw * 15625) / 100; ccprintf(" Voltage: 0x%04x = %d nV\n", vraw, v); - rv = i2c_read16(TMP006_PORT(addr_flags), - TMP006_REG(addr_flags), + rv = i2c_read16(TMP006_PORT(addr_flags), TMP006_REG(addr_flags), TMP006_REG_TDIE, &traw); t = (int)traw; - ccprintf(" Temperature: 0x%04x = %d.%02d C\n", - traw, t / 128, t > 0 ? t % 128 : 128 - (t % 128)); + ccprintf(" Temperature: 0x%04x = %d.%02d C\n", traw, t / 128, + t > 0 ? t % 128 : 128 - (t % 128)); return EC_SUCCESS; } @@ -442,8 +427,7 @@ static int command_sensor_info(int argc, char **argv) return rv1; } -DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info, - "[ ]", +DECLARE_CONSOLE_COMMAND(tmp006, command_sensor_info, "[ ]", "Print TMP006 sensors"); #endif -- cgit v1.2.1 From 15c9f39a4aab5ae0442c2739d01f975c608e01ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:02 -0600 Subject: include/usb_console.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37265d5a5edbbb88b81c532aee93681bfc518acf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730431 Reviewed-by: Jeremy Bettis --- include/usb_console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb_console.h b/include/usb_console.h index 2e0aa7dfa6..031ed9ce0e 100644 --- a/include/usb_console.h +++ b/include/usb_console.h @@ -80,7 +80,7 @@ int usb_console_tx_blocked(void); #define usb_getc(x) (-1) #define usb_va_start(x, y) #define usb_va_end(x) -#define usb_console_tx_blocked() (0) +#define usb_console_tx_blocked() (0) #endif #endif /* __CROS_EC_USB_CONSOLE_H */ -- cgit v1.2.1 From d011c69465f7bf0665abfdbf761df12a41bf2ea4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:26 -0600 Subject: chip/host/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0eea4e37e64410062693dff6a72886fc4edab44c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729147 Reviewed-by: Jeremy Bettis --- chip/host/config_chip.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index 84e254d8a0..7e45177401 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -20,11 +20,11 @@ extern char __host_flash[CONFIG_FLASH_SIZE_BYTES]; #define CONFIG_PROGRAM_MEMORY_BASE ((uintptr_t)__host_flash) -#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_ERASE_SIZE 0x0010 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 /* ideal write size */ -#define CONFIG_RAM_BASE 0x0 /* Not supported */ -#define CONFIG_RAM_SIZE 0x0 /* Not supported */ +#define CONFIG_RAM_BASE 0x0 /* Not supported */ +#define CONFIG_RAM_SIZE 0x0 /* Not supported */ #define CONFIG_FPU @@ -43,7 +43,7 @@ extern char __host_flash[CONFIG_FLASH_SIZE_BYTES]; /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* Do NOT use common panic code (designed to output information on the UART) */ #undef CONFIG_COMMON_PANIC_OUTPUT -- cgit v1.2.1 From 744c626d56bef96a450c394572d99717072d8394 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:11 -0600 Subject: zephyr/include/soc/microchip_xec/reg_def_cros.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1bb78ea841ca3a44dcbb832cee9771a0b3ffce1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730732 Reviewed-by: Jeremy Bettis --- zephyr/include/soc/microchip_xec/reg_def_cros.h | 46 ++++++++++++------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/zephyr/include/soc/microchip_xec/reg_def_cros.h b/zephyr/include/soc/microchip_xec/reg_def_cros.h index 4cc66be47d..55be15b6f6 100644 --- a/zephyr/include/soc/microchip_xec/reg_def_cros.h +++ b/zephyr/include/soc/microchip_xec/reg_def_cros.h @@ -13,29 +13,29 @@ /* RTC register structure */ struct rtc_hw { -__IOM uint8_t SECV; /*!< (@ 0x0000) RTC seconds value */ -__IOM uint8_t SECA; /*!< (@ 0x0001) RTC seconds alarm */ -__IOM uint8_t MINV; /*!< (@ 0x0002) RTC minutes value */ -__IOM uint8_t MINA; /*!< (@ 0x0003) RTC minutes alarm */ -__IOM uint8_t HRSV; /*!< (@ 0x0004) RTC hours value, AM/PM indicator */ -__IOM uint8_t HRSA; /*!< (@ 0x0005) RTC hours alarm */ -__IOM uint8_t DOWV; /*!< (@ 0x0006) RTC day of week value */ -__IOM uint8_t DOMV; /*!< (@ 0x0007) RTC day of month value */ -__IOM uint8_t MONV; /*!< (@ 0x0008) RTC month value */ -__IOM uint8_t YEARV; /*!< (@ 0x0009) RTC Year value */ -__IOM uint8_t REGA; /*!< (@ 0x000A) RTC register A */ -__IOM uint8_t REGB; /*!< (@ 0x000B) RTC register B */ -__IOM uint8_t REGC; /*!< (@ 0x000C) RTC register C */ -__IOM uint8_t REGD; /*!< (@ 0x000D) RTC register D */ -__IM uint16_t RESERVED; -__IOM uint8_t CTRL; /*!< (@ 0x0010) RTC control */ -__IM uint8_t RESERVED1; -__IM uint16_t RESERVED2; -__IOM uint8_t WKA; /*!< (@ 0x0014) RTC week alarm */ -__IM uint8_t RESERVED3; -__IM uint16_t RESERVED4; -__IOM uint32_t DLSF; /*!< (@ 0x0018) RTC daylight savings forward */ -__IOM uint32_t DLSB; /*!< (@ 0x001C) RTC daylight savings backward */ + __IOM uint8_t SECV; /*!< (@ 0x0000) RTC seconds value */ + __IOM uint8_t SECA; /*!< (@ 0x0001) RTC seconds alarm */ + __IOM uint8_t MINV; /*!< (@ 0x0002) RTC minutes value */ + __IOM uint8_t MINA; /*!< (@ 0x0003) RTC minutes alarm */ + __IOM uint8_t HRSV; /*!< (@ 0x0004) RTC hours value, AM/PM indicator */ + __IOM uint8_t HRSA; /*!< (@ 0x0005) RTC hours alarm */ + __IOM uint8_t DOWV; /*!< (@ 0x0006) RTC day of week value */ + __IOM uint8_t DOMV; /*!< (@ 0x0007) RTC day of month value */ + __IOM uint8_t MONV; /*!< (@ 0x0008) RTC month value */ + __IOM uint8_t YEARV; /*!< (@ 0x0009) RTC Year value */ + __IOM uint8_t REGA; /*!< (@ 0x000A) RTC register A */ + __IOM uint8_t REGB; /*!< (@ 0x000B) RTC register B */ + __IOM uint8_t REGC; /*!< (@ 0x000C) RTC register C */ + __IOM uint8_t REGD; /*!< (@ 0x000D) RTC register D */ + __IM uint16_t RESERVED; + __IOM uint8_t CTRL; /*!< (@ 0x0010) RTC control */ + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IOM uint8_t WKA; /*!< (@ 0x0014) RTC week alarm */ + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IOM uint32_t DLSF; /*!< (@ 0x0018) RTC daylight savings forward */ + __IOM uint32_t DLSB; /*!< (@ 0x001C) RTC daylight savings backward */ }; #endif /* _MICROCHIP_XEC_REG_DEF_CROS_H */ -- cgit v1.2.1 From 5ae5ce1ffec0c14bb51d2766e37c69f2b7bdeb4d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:14 -0600 Subject: common/usb_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6fed70ced93c35bdb9173d52dea2f7e30769d362 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729526 Reviewed-by: Jeremy Bettis --- common/usb_common.c | 123 ++++++++++++++++++++++++---------------------------- 1 file changed, 57 insertions(+), 66 deletions(-) diff --git a/common/usb_common.c b/common/usb_common.c index 12316f5ca3..022580af0d 100644 --- a/common/usb_common.c +++ b/common/usb_common.c @@ -36,8 +36,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -78,7 +78,7 @@ int hex8tou32(char *str, uint32_t *val) int remote_flashing(int argc, char **argv) { int port, cnt, cmd; - uint32_t data[VDO_MAX_SIZE-1]; + uint32_t data[VDO_MAX_SIZE - 1]; char *e; static int flash_offset[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -111,12 +111,11 @@ int remote_flashing(int argc, char **argv) argc -= 3; for (i = 0; i < argc; i++) - if (hex8tou32(argv[i+3], data + i)) + if (hex8tou32(argv[i + 3], data + i)) return EC_ERROR_INVAL; cmd = VDO_CMD_FLASH_WRITE; cnt = argc; - ccprintf("WRITE %d @%04x ...", argc * 4, - flash_offset[port]); + ccprintf("WRITE %d @%04x ...", argc * 4, flash_offset[port]); flash_offset[port] += argc * 4; } @@ -124,7 +123,7 @@ int remote_flashing(int argc, char **argv) /* Wait until VDM is done */ while (pd[port].vdm_state > 0) - task_wait_event(100*MSEC); + task_wait_event(100 * MSEC); ccprintf("DONE %d\n", pd[port].vdm_state); return EC_SUCCESS; @@ -151,11 +150,10 @@ bool pd_firmware_upgrade_check_power_readiness(int port) */ battery_get_params(&batt); if (batt.flags & BATT_FLAG_BAD_STATE_OF_CHARGE || - batt.state_of_charge < - MIN_BATTERY_FOR_PD_UPGRADE_PERCENT) { + batt.state_of_charge < MIN_BATTERY_FOR_PD_UPGRADE_PERCENT) { CPRINTS("C%d: Cannot suspend for upgrade, not " - "enough battery (%d%%)!", - port, batt.state_of_charge); + "enough battery (%d%%)!", + port, batt.state_of_charge); return false; } } else { @@ -181,8 +179,8 @@ int usb_get_battery_soc(void) #endif } -#if defined(CONFIG_USB_PD_PREFER_MV) && defined(PD_PREFER_LOW_VOLTAGE) + \ - defined(PD_PREFER_HIGH_VOLTAGE) > 1 +#if defined(CONFIG_USB_PD_PREFER_MV) && \ + defined(PD_PREFER_LOW_VOLTAGE) + defined(PD_PREFER_HIGH_VOLTAGE) > 1 #error "PD preferred voltage strategy should be mutually exclusive." #endif @@ -200,7 +198,8 @@ int usb_get_battery_soc(void) */ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2) { typec_current_t charge = 0; enum tcpc_cc_voltage_status cc; @@ -236,7 +235,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, } enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { /* The following assumes: * @@ -251,13 +250,13 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, } enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2) + enum tcpc_cc_voltage_status cc2) { return (cc1 == TYPEC_CC_VOLT_RD) ? POLARITY_CC1 : POLARITY_CC2; } -enum pd_cc_states pd_get_cc_state( - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2) +enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2) { /* Port partner is a SNK */ if (cc_is_snk_dbg_acc(cc1, cc2)) @@ -289,7 +288,7 @@ bool pd_is_debug_acc(int port) enum pd_cc_states cc_state = pd_get_task_cc_state(port); return cc_state == PD_CC_UFP_DEBUG_ACC || - cc_state == PD_CC_DFP_DEBUG_ACC; + cc_state == PD_CC_DFP_DEBUG_ACC; } __overridable int pd_board_check_request(uint32_t rdo, int pdo_cnt) @@ -303,7 +302,7 @@ int pd_get_source_pdo(const uint32_t **src_pdo_p, const int port) const uint32_t *src_pdo; const int pdo_cnt = dpm_get_source_pdo(&src_pdo, port); #elif defined(CONFIG_USB_PD_DYNAMIC_SRC_CAP) || \ - defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) + defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) const uint32_t *src_pdo; const int pdo_cnt = charge_manager_get_source_pdo(&src_pdo, port); #else @@ -346,8 +345,8 @@ int pd_check_requested_voltage(uint32_t rdo, const int port) return EC_ERROR_INVAL; /* too much max current */ CPRINTF("Requested %d mV %d mA (for %d/%d mA)\n", - ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, - op_ma * 10, max_ma * 10); + ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10, op_ma * 10, + max_ma * 10); /* Accept the requested voltage */ return EC_SUCCESS; @@ -382,16 +381,12 @@ int pd_get_retry_count(int port, enum tcpci_msg_type type) } enum pd_drp_next_states drp_auto_toggle_next_state( - uint64_t *drp_sink_time, - enum pd_power_role power_role, - enum pd_dual_role_states drp_state, - enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2, - bool auto_toggle_supported) + uint64_t *drp_sink_time, enum pd_power_role power_role, + enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported) { const bool hardware_debounced_unattached = - ((drp_state == PD_DRP_TOGGLE_ON) && - auto_toggle_supported); + ((drp_state == PD_DRP_TOGGLE_ON) && auto_toggle_supported); /* Set to appropriate port state */ if (cc_is_open(cc1, cc2)) { @@ -425,13 +420,13 @@ enum pd_drp_next_states drp_auto_toggle_next_state( return DRP_TC_DRP_AUTO_TOGGLE; } } else if ((cc_is_rp(cc1) || cc_is_rp(cc2)) && - drp_state != PD_DRP_FORCE_SOURCE) { + drp_state != PD_DRP_FORCE_SOURCE) { /* SNK allowed unless ForceSRC */ if (hardware_debounced_unattached) return DRP_TC_ATTACHED_WAIT_SNK; return DRP_TC_UNATTACHED_SNK; } else if (cc_is_at_least_one_rd(cc1, cc2) || - cc_is_audio_acc(cc1, cc2)) { + cc_is_audio_acc(cc1, cc2)) { /* * SRC allowed unless ForceSNK or Toggle Off * @@ -447,10 +442,10 @@ enum pd_drp_next_states drp_auto_toggle_next_state( * ready for a new connection. */ if (drp_state == PD_DRP_TOGGLE_OFF || - drp_state == PD_DRP_FORCE_SINK) { - if (get_time().val > *drp_sink_time + 200*MSEC) + drp_state == PD_DRP_FORCE_SINK) { + if (get_time().val > *drp_sink_time + 200 * MSEC) *drp_sink_time = get_time().val; - if (get_time().val < *drp_sink_time + 100*MSEC) + if (get_time().val < *drp_sink_time + 100 * MSEC) return DRP_TC_UNATTACHED_SNK; else return DRP_TC_DRP_AUTO_TOGGLE; @@ -502,8 +497,8 @@ mux_state_t get_mux_mode_to_set(int port) * conditions which are checked below. The default function returns * false, so only boards that override this check will be affected. */ - if (usb_ufp_check_usb3_enable(port) && pd_get_data_role(port) - == PD_ROLE_UFP) + if (usb_ufp_check_usb3_enable(port) && + pd_get_data_role(port) == PD_ROLE_UFP) return USB_PD_MUX_USB_ENABLED; /* If new data role isn't DFP & we only support DFP, also disconnect. */ @@ -544,21 +539,23 @@ void set_usb_mux_with_current_data_role(int port) if (IS_ENABLED(CONFIG_USBC_SS_MUX)) { mux_state_t mux_mode = get_mux_mode_to_set(port); enum usb_switch usb_switch_mode = - (mux_mode == USB_PD_MUX_NONE) ? - USB_SWITCH_DISCONNECT : USB_SWITCH_CONNECT; + (mux_mode == USB_PD_MUX_NONE) ? USB_SWITCH_DISCONNECT : + USB_SWITCH_CONNECT; usb_mux_set(port, mux_mode, usb_switch_mode, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); } } void usb_mux_set_safe_mode(int port) { if (IS_ENABLED(CONFIG_USBC_SS_MUX)) { - usb_mux_set(port, IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) ? - USB_PD_MUX_SAFE_MODE : USB_PD_MUX_NONE, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + usb_mux_set(port, + IS_ENABLED(CONFIG_USB_MUX_VIRTUAL) ? + USB_PD_MUX_SAFE_MODE : + USB_PD_MUX_NONE, + USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); } /* Isolate the SBU lines. */ @@ -617,8 +614,7 @@ __overridable int pd_board_checks(void) return EC_SUCCESS; } -__overridable int pd_check_data_swap(int port, - enum pd_data_role data_role) +__overridable int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Allow data swap if we are a UFP, otherwise don't allow. */ return (data_role == PD_ROLE_UFP) ? 1 : 0; @@ -639,8 +635,7 @@ __overridable int pd_check_power_swap(int port) return 0; } -__overridable void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__overridable void pd_execute_data_swap(int port, enum pd_data_role data_role) { } @@ -699,7 +694,7 @@ __overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload, case VDO_CMD_VERSION: /* guarantee last byte of payload is null character */ *(payload + cnt - 1) = 0; - CPRINTF("version: %s\n", (char *)(payload+1)); + CPRINTF("version: %s\n", (char *)(payload + 1)); break; case VDO_CMD_READ_INFO: case VDO_CMD_SEND_INFO: @@ -720,10 +715,8 @@ __overridable int pd_custom_vdm(int port, int cnt, uint32_t *payload, pd_send_host_event(PD_EVENT_UPDATE_DEVICE); CPRINTF("DevId:%d.%d SW:%d RW:%d\n", - HW_DEV_ID_MAJ(dev_id), - HW_DEV_ID_MIN(dev_id), - VDO_INFO_SW_DBG_VER(payload[6]), - is_rw); + HW_DEV_ID_MAJ(dev_id), HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), is_rw); } else if (cnt == 6) { /* really old devices don't have last byte */ pd_dev_store_rw_hash(port, dev_id, payload + 1, @@ -757,9 +750,9 @@ __overridable bool vboot_allow_usb_pd(void) static void pd_usb_billboard_deferred(void) { if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE) && - !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) && - !IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) && - IS_ENABLED(CONFIG_USB_BOS)) { + !IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP) && + !IS_ENABLED(CONFIG_USB_PD_SIMPLE_DFP) && + IS_ENABLED(CONFIG_USB_BOS)) { /* * TODO(tbroch) * 1. Will we have multiple type-C port UFPs @@ -859,10 +852,9 @@ __overridable int pd_snk_is_vbus_provided(int port) __overridable bool pd_check_vbus_level(int port, enum vbus_level level) { if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC) && - (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) { + (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC)) { return tcpm_check_vbus_level(port, level); - } - else if (level == VBUS_PRESENT) + } else if (level == VBUS_PRESENT) return pd_snk_is_vbus_provided(port); else return !pd_snk_is_vbus_provided(port); @@ -899,7 +891,7 @@ int pd_set_frs_enable(int port, int enable) * Dump TCPC registers. */ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg, - int count) + int count) { int i, val; @@ -907,18 +899,17 @@ void tcpc_dump_registers(int port, const struct tcpc_reg_dump_map *reg, switch (reg->size) { case 1: tcpc_read(port, reg->addr, &val); - ccprintf(" %-30s(0x%02x) = 0x%02x\n", - reg->name, reg->addr, (uint8_t)val); + ccprintf(" %-30s(0x%02x) = 0x%02x\n", reg->name, + reg->addr, (uint8_t)val); break; case 2: tcpc_read16(port, reg->addr, &val); - ccprintf(" %-30s(0x%02x) = 0x%04x\n", - reg->name, reg->addr, (uint16_t)val); + ccprintf(" %-30s(0x%02x) = 0x%04x\n", reg->name, + reg->addr, (uint16_t)val); break; } cflush(); } - } static int command_tcpc_dump(int argc, char **argv) @@ -995,7 +986,7 @@ void pd_srccaps_dump(int port) if (range_flag) ccprintf("-%dmV", min_mv); ccprintf("/%dm%c", max_ma, - pdo_mask == PDO_TYPE_BATTERY ? 'W' : 'A'); + pdo_mask == PDO_TYPE_BATTERY ? 'W' : 'A'); if (pdo & PDO_FIXED_DUAL_ROLE) ccprintf(" DRP"); -- cgit v1.2.1 From 161fcc6dd420718dbbe1ce8e4eb8fc082769a81b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:20 -0600 Subject: include/mat33.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3b18490ca200cad7b8e7e053a4542cf23b20d3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730349 Reviewed-by: Jeremy Bettis --- include/mat33.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/mat33.h b/include/mat33.h index fdd7e954ac..1a9a02f71f 100644 --- a/include/mat33.h +++ b/include/mat33.h @@ -26,6 +26,6 @@ void mat33_fp_get_eigenbasis(mat33_fp_t S, fpv3_t eigenvals, size_t mat33_fp_maxind(mat33_fp_t A, size_t k); -void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, - size_t k, size_t l, size_t i, size_t j); -#endif /* __CROS_EC_MAT_33_H */ +void mat33_fp_rotate(mat33_fp_t A, fp_t c, fp_t s, size_t k, size_t l, size_t i, + size_t j); +#endif /* __CROS_EC_MAT_33_H */ -- cgit v1.2.1 From 97fefaa792e6a3232d031038a19b2ddc74b0d13f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:40 -0600 Subject: core/riscv-rv32i/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I26ae239aab164d7d79309e95068c2b14349d61e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729867 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/riscv-rv32i/atomic.h b/core/riscv-rv32i/atomic.h index 4d6114cd53..3eb66ca178 100644 --- a/core/riscv-rv32i/atomic.h +++ b/core/riscv-rv32i/atomic.h @@ -53,4 +53,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From bff12ee5ac8eab325476eba44b5c6e0ad95ca880 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:39 -0600 Subject: baseboard/dedede/cbi_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7877cc20c23027b7a88d28beb82c0cae145757a8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727872 Reviewed-by: Jeremy Bettis --- baseboard/dedede/cbi_fw_config.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/baseboard/dedede/cbi_fw_config.c b/baseboard/dedede/cbi_fw_config.c index 65a8cbaad9..3c3ddf0f47 100644 --- a/baseboard/dedede/cbi_fw_config.c +++ b/baseboard/dedede/cbi_fw_config.c @@ -35,36 +35,36 @@ enum fw_config_db get_cbi_fw_config_db(void) enum fw_config_stylus get_cbi_fw_config_stylus(void) { - return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) - >> FW_CONFIG_STYLUS_OFFSET); + return ((cached_fw_config & FW_CONFIG_STYLUS_MASK) >> + FW_CONFIG_STYLUS_OFFSET); } enum fw_config_kblight_type get_cbi_fw_config_kblight(void) { - return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) - >> FW_CONFIG_KB_BL_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_BL_MASK) >> + FW_CONFIG_KB_BL_OFFSET); } enum fw_config_tablet_mode_type get_cbi_fw_config_tablet_mode(void) { - return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) - >> FW_CONFIG_TABLET_MODE_OFFSET); + return ((cached_fw_config & FW_CONFIG_TABLET_MODE_MASK) >> + FW_CONFIG_TABLET_MODE_OFFSET); } int get_cbi_fw_config_keyboard(void) { - return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) - >> FW_CONFIG_KB_LAYOUT_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_LAYOUT_MASK) >> + FW_CONFIG_KB_LAYOUT_OFFSET); } enum fw_config_numeric_pad_type get_cbi_fw_config_numeric_pad(void) { - return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) - >> FW_CONFIG_KB_NUMPAD_OFFSET); + return ((cached_fw_config & FW_CONFIG_KB_NUMPAD_MASK) >> + FW_CONFIG_KB_NUMPAD_OFFSET); } enum fw_config_hdmi_type get_cbi_fw_config_hdmi(void) { - return ((cached_fw_config & FW_CONFIG_HDMI_MASK) - >> FW_CONFIG_HDMI_OFFSET); + return ((cached_fw_config & FW_CONFIG_HDMI_MASK) >> + FW_CONFIG_HDMI_OFFSET); } -- cgit v1.2.1 From b50c3fe65a428f8e3709feadf2f826c1217bbf77 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:27 -0600 Subject: board/collis/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If4e9937478d14e583399f3ac3fe1dce80c89644a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728153 Reviewed-by: Jeremy Bettis --- board/collis/board.h | 112 ++++++++++++++++++++++++--------------------------- 1 file changed, 52 insertions(+), 60 deletions(-) diff --git a/board/collis/board.h b/board/collis/board.h index 22f7af1b6c..f98e3fc432 100644 --- a/board/collis/board.h +++ b/board/collis/board.h @@ -28,11 +28,11 @@ #define CONFIG_POWER_PP5000_CONTROL #undef NPCX_PWM1_SEL -#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */ +#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */ /* LED defines */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* Keyboard features */ #define CONFIG_KEYBOARD_VIVALDI @@ -57,34 +57,34 @@ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W, the limitation of 45W is for the Collis * board. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #undef CONFIG_USBC_RETIMER_INTEL_BB #undef CONFIG_USBC_RETIMER_INTEL_BB_RUNTIME_CONFIG /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ #undef CONFIG_USB_MUX_RUNTIME_CONFIG #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG @@ -99,8 +99,8 @@ #undef CONFIG_FANS /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -108,47 +108,46 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -159,10 +158,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -171,11 +167,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 7e6059bf58854b707e1b58a6da6b7ac434fa51fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:03 -0600 Subject: zephyr/test/drivers/src/usb_mux.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11d2dd5b7b6f633e4fe9564b99776658a227acf4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731007 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/usb_mux.c | 140 ++++++++++++++++---------------------- 1 file changed, 60 insertions(+), 80 deletions(-) diff --git a/zephyr/test/drivers/src/usb_mux.c b/zephyr/test/drivers/src/usb_mux.c index 09aa3c47d6..0a8dbcf38f 100644 --- a/zephyr/test/drivers/src/usb_mux.c +++ b/zephyr/test/drivers/src/usb_mux.c @@ -33,7 +33,7 @@ struct usb_mux usb_mux_c1; /** Number of usb mux proxies in chain */ -#define NUM_OF_PROXY 3 +#define NUM_OF_PROXY 3 /** Pointers to original usb muxes chain of port c1 */ const struct usb_mux *org_mux[NUM_OF_PROXY]; @@ -47,8 +47,7 @@ static int proxy_init_custom(const struct usb_mux *me) zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux"); - if (org_mux[i] != NULL && - org_mux[i]->driver->init != NULL) { + if (org_mux[i] != NULL && org_mux[i]->driver->init != NULL) { ec = org_mux[i]->driver->init(org_mux[i]); } @@ -72,8 +71,7 @@ static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state, zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux"); - if (org_mux[i] != NULL && - org_mux[i]->driver->set != NULL) { + if (org_mux[i] != NULL && org_mux[i]->driver->set != NULL) { ec = org_mux[i]->driver->set(org_mux[i], mux_state, ack_required); } @@ -110,15 +108,15 @@ static int proxy_get_custom(const struct usb_mux *me, mux_state_t *mux_state) zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux"); - if (org_mux[i] != NULL && - org_mux[i]->driver->get != NULL) { + if (org_mux[i] != NULL && org_mux[i]->driver->get != NULL) { ec = org_mux[i]->driver->get(org_mux[i], mux_state); } if (task_get_current() == TASK_ID_TEST_RUNNER) { zassert_true(proxy_get_mux_state_seq_idx < NUM_OF_PROXY, "%s called too many times without resetting " - "mux_state_seq", __func__); + "mux_state_seq", + __func__); *mux_state = proxy_get_mux_state_seq[proxy_get_mux_state_seq_idx]; proxy_get_mux_state_seq_idx++; @@ -164,8 +162,7 @@ static int proxy_chipset_reset_custom(const struct usb_mux *me) zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux"); - if (org_mux[i] != NULL && - org_mux[i]->driver->chipset_reset != NULL) { + if (org_mux[i] != NULL && org_mux[i]->driver->chipset_reset != NULL) { ec = org_mux[i]->driver->chipset_reset(org_mux[i]); } @@ -194,8 +191,7 @@ static void proxy_hpd_update_custom(const struct usb_mux *me, zassert_true(i < NUM_OF_PROXY, "Proxy called for non proxy usb_mux"); - if (org_mux[i] != NULL && - org_mux[i]->hpd_update != NULL) { + if (org_mux[i] != NULL && org_mux[i]->hpd_update != NULL) { org_mux[i]->hpd_update(org_mux[i], mux_state, ack_required); } @@ -264,7 +260,7 @@ static void reset_proxy_fakes(void) proxy_set_fake.custom_fake = proxy_set_custom; proxy_get_fake.custom_fake = proxy_get_custom; proxy_enter_low_power_mode_fake.custom_fake = - proxy_enter_low_power_mode_custom; + proxy_enter_low_power_mode_custom; proxy_chipset_reset_fake.custom_fake = proxy_chipset_reset_custom; proxy_hpd_update_fake.custom_fake = proxy_hpd_update_custom; mock_board_init_fake.custom_fake = mock_board_init_custom; @@ -305,7 +301,6 @@ struct usb_mux proxy_chain_0 = { .hpd_update = &proxy_hpd_update, }; - /** Setup first 3 usb muxes of port 1 with proxy */ static void setup_usb_mux_proxy_chain(void) { @@ -346,25 +341,22 @@ static void restore_usb_mux_chain(void) * pointer to the right proxy chain element. First argument is * const struct usb_mux * for all struct usb_mux_driver callbacks. */ -#define CHECK_PROXY_FAKE_CALL_CNT(proxy, num) \ - do { \ - zassert_equal(num, proxy##_fake.call_count, "%d != %d", \ - num, proxy##_fake.call_count); \ - if (num >= 1) { \ - zassert_equal(&usb_muxes[USBC_PORT_C1], \ - proxy##_fake.arg0_history[0], \ - NULL); \ - } \ - if (num >= 2) { \ - zassert_equal(&proxy_chain_1, \ - proxy##_fake.arg0_history[1], \ - NULL); \ - } \ - if (num >= 3) { \ - zassert_equal(&proxy_chain_2, \ - proxy##_fake.arg0_history[2], \ - NULL); \ - } \ +#define CHECK_PROXY_FAKE_CALL_CNT(proxy, num) \ + do { \ + zassert_equal(num, proxy##_fake.call_count, "%d != %d", num, \ + proxy##_fake.call_count); \ + if (num >= 1) { \ + zassert_equal(&usb_muxes[USBC_PORT_C1], \ + proxy##_fake.arg0_history[0], NULL); \ + } \ + if (num >= 2) { \ + zassert_equal(&proxy_chain_1, \ + proxy##_fake.arg0_history[1], NULL); \ + } \ + if (num >= 3) { \ + zassert_equal(&proxy_chain_2, \ + proxy##_fake.arg0_history[2], NULL); \ + } \ } while (0) /** @@ -372,33 +364,30 @@ static void restore_usb_mux_chain(void) * was the same as given state. hpd_update and set callback have mux_state_t * as second argument. */ -#define CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy, num, state) \ - do { \ - CHECK_PROXY_FAKE_CALL_CNT(proxy, num); \ - if (num >= 1) { \ - zassert_equal(state, \ - proxy##_fake.arg1_history[0], \ - "0x%x != 0x%x", state, \ - proxy##_fake.arg1_history[0]); \ - } \ - if (num >= 2) { \ - zassert_equal(state, \ - proxy##_fake.arg1_history[1], \ - "0x%x != 0x%x", state, \ - proxy##_fake.arg1_history[1]); \ - } \ - if (num >= 3) { \ - zassert_equal(state, \ - proxy##_fake.arg1_history[2], \ - "0x%x != 0x%x", state, \ - proxy##_fake.arg1_history[2]); \ - } \ +#define CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy, num, state) \ + do { \ + CHECK_PROXY_FAKE_CALL_CNT(proxy, num); \ + if (num >= 1) { \ + zassert_equal(state, proxy##_fake.arg1_history[0], \ + "0x%x != 0x%x", state, \ + proxy##_fake.arg1_history[0]); \ + } \ + if (num >= 2) { \ + zassert_equal(state, proxy##_fake.arg1_history[1], \ + "0x%x != 0x%x", state, \ + proxy##_fake.arg1_history[1]); \ + } \ + if (num >= 3) { \ + zassert_equal(state, proxy##_fake.arg1_history[2], \ + "0x%x != 0x%x", state, \ + proxy##_fake.arg1_history[2]); \ + } \ } while (0) /** Test usb_mux init */ ZTEST(usb_uninit_mux, test_usb_mux_init) { - int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_NOT_POWERED}; + int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED }; /* Set AP to normal state to init BB retimer */ test_set_chipset_to_s0(); @@ -432,7 +421,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_init) /** Test usb_mux setting mux mode */ ZTEST(usb_uninit_mux, test_usb_mux_set) { - int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_UNKNOWN}; + int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN }; mux_state_t exp_mode; /* Set flag for usb mux 1 to disable polarity setting */ @@ -514,7 +503,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_reset_in_g3) /** Test usb_mux getting mux mode */ ZTEST(usb_uninit_mux, test_usb_mux_get) { - int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_UNKNOWN}; + int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_UNKNOWN }; mux_state_t exp_mode, mode; /* Test getting mux mode */ @@ -551,7 +540,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_get) /** Test usb_mux entering and exiting low power mode */ ZTEST(usb_init_mux, test_usb_mux_low_power_mode) { - int fail_on_2nd_ret[] = {EC_SUCCESS, EC_ERROR_NOT_POWERED}; + int fail_on_2nd_ret[] = { EC_SUCCESS, EC_ERROR_NOT_POWERED }; mux_state_t exp_mode, mode; /* Test enter to low power mode */ @@ -713,8 +702,7 @@ ZTEST(usb_uninit_mux, test_usb_mux_hpd_update) usb_mux_hpd_update(USBC_PORT_C1, exp_mode); /* Check if PS8xxx mux mode is updated correctly */ tcpci_tcpm_usb_mux_driver.get(&usb_muxes[USBC_PORT_C1], &mode); - zassert_equal(0, mode, "mux mode is 0x%x (!= 0x%x)", - mode, 0); + zassert_equal(0, mode, "mux mode is 0x%x (!= 0x%x)", mode, 0); } ZTEST(usb_init_mux, test_usb_mux_fw_update_port_info) @@ -786,8 +774,7 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command) /* Test error on command with no argument */ zassert_equal(EC_ERROR_PARAM_COUNT, - shell_execute_cmd(get_ec_shell(), - "typec"), NULL); + shell_execute_cmd(get_ec_shell(), "typec"), NULL); /* * Test success on passing "debug" as first argument. This will enable @@ -795,49 +782,44 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command) * without accessing cprints output. */ zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec debug"), NULL); + shell_execute_cmd(get_ec_shell(), "typec debug"), NULL); /* Test error on port argument that is not a number */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "typec test1"), NULL); + shell_execute_cmd(get_ec_shell(), "typec test1"), NULL); /* Test error on invalid port number */ zassert_equal(EC_ERROR_PARAM1, - shell_execute_cmd(get_ec_shell(), - "typec 5"), NULL); + shell_execute_cmd(get_ec_shell(), "typec 5"), NULL); /* * Test success on correct port number. Command should print mux state * on console, but it is not possible to check that in unit test. */ set_proxy_get_mux_state_seq(USB_PD_MUX_TBT_COMPAT_ENABLED); - zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec 1"), NULL); + zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "typec 1"), + NULL); CHECK_PROXY_FAKE_CALL_CNT(proxy_get, NUM_OF_PROXY); /* Test setting none mode */ reset_proxy_fakes(); exp_mode = USB_PD_MUX_NONE; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec 1 none"), NULL); + shell_execute_cmd(get_ec_shell(), "typec 1 none"), NULL); CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode); /* Mux will enter low power mode */ CHECK_PROXY_FAKE_CALL_CNT(proxy_enter_low_power_mode, NUM_OF_PROXY); /* Polarity is set based on PD */ polarity = polarity_rm_dts(pd_get_polarity(USBC_PORT_C1)) ? - USB_PD_MUX_POLARITY_INVERTED : 0; + USB_PD_MUX_POLARITY_INVERTED : + 0; /* Test setting USB mode */ reset_proxy_fakes(); exp_mode = USB_PD_MUX_USB_ENABLED | polarity; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec 1 usb"), NULL); + shell_execute_cmd(get_ec_shell(), "typec 1 usb"), NULL); CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode); /* Mux will exit low power mode */ CHECK_PROXY_FAKE_CALL_CNT(proxy_init, NUM_OF_PROXY); @@ -846,16 +828,14 @@ ZTEST(usb_init_mux, test_usb_mux_typec_command) reset_proxy_fakes(); exp_mode = USB_PD_MUX_DP_ENABLED | polarity; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec 1 dp"), NULL); + shell_execute_cmd(get_ec_shell(), "typec 1 dp"), NULL); CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode); /* Test setting dock mode */ reset_proxy_fakes(); exp_mode = USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | polarity; zassert_equal(EC_SUCCESS, - shell_execute_cmd(get_ec_shell(), - "typec 1 dock"), NULL); + shell_execute_cmd(get_ec_shell(), "typec 1 dock"), NULL); CHECK_PROXY_FAKE_CALL_CNT_MUX_STATE(proxy_set, NUM_OF_PROXY, exp_mode); } -- cgit v1.2.1 From 0528defe998fad97f82119aaddb93528d8481b27 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:17 -0600 Subject: board/taeko/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c22f92a7b866f8774ffe0ba048a48d8ad34d5da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728981 Reviewed-by: Jeremy Bettis --- board/taeko/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/taeko/fans.c b/board/taeko/fans.c index e6273ec210..ae026fdd7e 100644 --- a/board/taeko/fans.c +++ b/board/taeko/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From b820b92efed32e2289a516e2e3d7b8680e17951e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:28 -0600 Subject: board/haboki/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia8ffbc3f92dfc4ea6fc1b2d9434383b82a1c5359 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728445 Reviewed-by: Jeremy Bettis --- board/haboki/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/haboki/cbi_ssfc.h b/board/haboki/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/haboki/cbi_ssfc.h +++ b/board/haboki/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From a22b4eae76ccd23dda435c7a3aaab81f089300f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:49 -0600 Subject: chip/stm32/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8bfe92c1844958343711af7a1ce4940f9d09f1d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729413 Reviewed-by: Jeremy Bettis --- chip/stm32/system.c | 125 ++++++++++++++++++++++++++-------------------------- 1 file changed, 62 insertions(+), 63 deletions(-) diff --git a/chip/stm32/system.c b/chip/stm32/system.c index d7388055a9..95d26fa1ab 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -28,10 +28,10 @@ #define BDCR_SRC BDCR_SRC_LSI #define BDCR_RDY 0 #endif -#define BDCR_ENABLE_VALUE (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | \ - BDCR_RDY) -#define BDCR_ENABLE_MASK (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | \ - STM32_RCC_BDCR_BDRST) +#define BDCR_ENABLE_VALUE \ + (STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC) | BDCR_RDY) +#define BDCR_ENABLE_MASK \ + (BDCR_ENABLE_VALUE | BDCR_RTCSEL_MASK | STM32_RCC_BDCR_BDRST) #ifdef CONFIG_USB_PD_DUAL_ROLE BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT <= 3); @@ -149,62 +149,61 @@ void chip_pre_init(void) uint32_t apb2fz_reg = 0; #if defined(CHIP_FAMILY_STM32F0) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | - STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; + STM32_RCC_PB2_TIM17 | STM32_RCC_PB2_TIM1; /* enable clock to debug module before writing */ STM32_RCC_APB2ENR |= STM32_RCC_DBGMCUEN; #elif defined(CHIP_FAMILY_STM32F3) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | STM32_RCC_PB2_TIM17; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16 | + STM32_RCC_PB2_TIM17; #elif defined(CHIP_FAMILY_STM32F4) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | STM32_RCC_PB1_TIM14| - STM32_RCC_PB1_RTC | STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | STM32_RCC_PB2_TIM9 | - STM32_RCC_PB2_TIM10 | STM32_RCC_PB2_TIM11; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_TIM12 | STM32_RCC_PB1_TIM13 | + STM32_RCC_PB1_TIM14 | STM32_RCC_PB1_RTC | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8 | + STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | + STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32L4) -#ifdef CHIP_VARIANT_STM32L431X - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | STM32_RCC_PB1_TIM6 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; - apb2fz_reg = - STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | STM32_RCC_PB2_TIM16; +#ifdef CHIP_VARIANT_STM32L431X + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_WWDG | + STM32_RCC_PB1_IWDG; + apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM15 | + STM32_RCC_PB2_TIM16; #else - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_TIM5 | STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_TIM5 | + STM32_RCC_PB1_TIM6 | STM32_RCC_PB1_TIM7 | + STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM1 | STM32_RCC_PB2_TIM8; #endif #elif defined(CHIP_FAMILY_STM32L) - apb1fz_reg = - STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 | - STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG; + apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | + STM32_RCC_PB1_TIM4 | STM32_RCC_PB1_WWDG | + STM32_RCC_PB1_IWDG; apb2fz_reg = STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 | - STM32_RCC_PB2_TIM11; + STM32_RCC_PB2_TIM11; #elif defined(CHIP_FAMILY_STM32G4) - apb1fz_reg = - STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | - STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | - STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | - STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | - STM32_DBGMCU_APB1FZ_IWDG; - apb2fz_reg = - STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | - STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | - STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; + apb1fz_reg = STM32_DBGMCU_APB1FZ_TIM2 | STM32_DBGMCU_APB1FZ_TIM3 | + STM32_DBGMCU_APB1FZ_TIM4 | STM32_DBGMCU_APB1FZ_TIM5 | + STM32_DBGMCU_APB1FZ_TIM6 | STM32_DBGMCU_APB1FZ_TIM7 | + STM32_DBGMCU_APB1FZ_RTC | STM32_DBGMCU_APB1FZ_WWDG | + STM32_DBGMCU_APB1FZ_IWDG; + apb2fz_reg = STM32_DBGMCU_APB2FZ_TIM1 | STM32_DBGMCU_APB2FZ_TIM8 | + STM32_DBGMCU_APB2FZ_TIM15 | STM32_DBGMCU_APB2FZ_TIM16 | + STM32_DBGMCU_APB2FZ_TIM17 | STM32_DBGMCU_APB2FZ_TIM20; #elif defined(CHIP_FAMILY_STM32H7) /* TODO(b/67081508) */ #endif @@ -274,7 +273,7 @@ void system_pre_init(void) /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 -#ifdef CHIP_FAMILY_STM32L4 +#ifdef CHIP_FAMILY_STM32L4 STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; #else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; @@ -322,10 +321,10 @@ void system_pre_init(void) /* Enable RTC and use LSI as clock source */ STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; } -#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32L5) || defined(CHIP_FAMILY_STM32F4) || \ - defined(CHIP_FAMILY_STM32H7) || defined(CHIP_FAMILY_STM32G4) +#elif defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) || \ + defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32L5) || \ + defined(CHIP_FAMILY_STM32F4) || defined(CHIP_FAMILY_STM32H7) || \ + defined(CHIP_FAMILY_STM32G4) if ((STM32_RCC_BDCR & BDCR_ENABLE_MASK) != BDCR_ENABLE_VALUE) { /* The RTC settings are bad, we need to reset it */ STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST; @@ -438,9 +437,9 @@ void system_reset(int flags) bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_REASON, reason); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_INFO, info); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, - exception); + exception); bkpdata_write(BKPDATA_INDEX_SAVED_PANIC_FLAGS, - panic_flags); + panic_flags); } #endif @@ -633,19 +632,19 @@ int system_is_reboot_warm(void) #elif defined(CHIP_FAMILY_STM32L) return ((STM32_RCC_AHBENR & 0x3f) == 0x3f); #elif defined(CHIP_FAMILY_STM32L4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + STM32_RCC_AHB2ENR_GPIOMASK); #elif defined(CHIP_FAMILY_STM32L5) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == STM32_RCC_AHB2ENR_GPIOMASK); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + STM32_RCC_AHB2ENR_GPIOMASK); #elif defined(CHIP_FAMILY_STM32F4) - return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) - == gpio_required_clocks()); + return ((STM32_RCC_AHB1ENR & STM32_RCC_AHB1ENR_GPIOMASK) == + gpio_required_clocks()); #elif defined(CHIP_FAMILY_STM32G4) - return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) - == gpio_required_clocks()); + return ((STM32_RCC_AHB2ENR & STM32_RCC_AHB2ENR_GPIOMASK) == + gpio_required_clocks()); #elif defined(CHIP_FAMILY_STM32H7) - return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) - == STM32_RCC_AHB4ENR_GPIOMASK); + return ((STM32_RCC_AHB4ENR & STM32_RCC_AHB4ENR_GPIOMASK) == + STM32_RCC_AHB4ENR_GPIOMASK); #endif } -- cgit v1.2.1 From 6b1e28430510ca0be99b356891c8ba28f7cad9f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:10 -0600 Subject: common/led_onoff_states.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I681b0bb746113dabcc9a8cd4cc8a571c905885d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729646 Reviewed-by: Jeremy Bettis --- common/led_onoff_states.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/common/led_onoff_states.c b/common/led_onoff_states.c index 48886e5de3..decf124e19 100644 --- a/common/led_onoff_states.c +++ b/common/led_onoff_states.c @@ -17,14 +17,14 @@ #include "system.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * In order to support the battery LED being optional (ex. for Chromeboxes), * set up default battery table, setter, and variables. */ -__overridable struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; +__overridable struct led_descriptor led_bat_state_table[LED_NUM_STATES] + [LED_NUM_PHASES]; __overridable const int led_charge_lvl_1; __overridable const int led_charge_lvl_2; __overridable void led_set_color_battery(enum ec_led_colors color) @@ -43,7 +43,7 @@ static int led_get_charge_percent(void) static enum led_states led_get_state(void) { - int charge_lvl; + int charge_lvl; enum led_states new_state = LED_NUM_STATES; if (!IS_ENABLED(CONFIG_CHARGER)) @@ -58,11 +58,10 @@ static enum led_states led_get_state(void) new_state = STATE_CHARGING_LVL_1; else if (charge_lvl < led_charge_lvl_2) new_state = STATE_CHARGING_LVL_2; + else if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + new_state = STATE_CHARGING_FULL_S5; else - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) - new_state = STATE_CHARGING_FULL_S5; - else - new_state = STATE_CHARGING_FULL_CHARGE; + new_state = STATE_CHARGING_FULL_CHARGE; break; case PWR_STATE_DISCHARGE_FULL: if (extpower_is_present()) { @@ -77,7 +76,7 @@ static enum led_states led_get_state(void) if (chipset_in_state(CHIPSET_STATE_ON)) { #ifdef CONFIG_LED_ONOFF_STATES_BAT_LOW if (led_get_charge_percent() < - CONFIG_LED_ONOFF_STATES_BAT_LOW) + CONFIG_LED_ONOFF_STATES_BAT_LOW) new_state = STATE_DISCHARGE_S0_BAT_LOW; else #endif @@ -147,14 +146,14 @@ static void led_update_battery(void) ticks = 0; period = led_bat_state_table[led_state][LED_PHASE_0].time + - led_bat_state_table[led_state][LED_PHASE_1].time; - + led_bat_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for battery state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_battery(LED_OFF); return; } @@ -163,8 +162,8 @@ static void led_update_battery(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_bat_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ @@ -176,7 +175,7 @@ static void led_update_battery(void) * table and setter */ __overridable const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; __overridable void led_set_color_power(enum ec_led_colors color) { } @@ -226,14 +225,14 @@ static void led_update_power(void) ticks = 0; period = led_pwr_state_table[led_state][LED_PHASE_0].time + - led_pwr_state_table[led_state][LED_PHASE_1].time; - + led_pwr_state_table[led_state][LED_PHASE_1].time; } /* If this state is undefined, turn the LED off */ if (period == 0) { CPRINTS("Undefined LED behavior for power state %d," - "turning off LED", led_state); + "turning off LED", + led_state); led_set_color_power(LED_OFF); return; } @@ -242,13 +241,12 @@ static void led_update_power(void) * Determine which phase of the state table to use. The phase is * determined if it falls within first phase time duration. */ - phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? - 0 : 1; + phase = ticks < led_pwr_state_table[led_state][LED_PHASE_0].time ? 0 : + 1; ticks = (ticks + 1) % period; /* Set the color for the given state and phase */ led_set_color_power(led_pwr_state_table[led_state][phase].color); - } static void led_init(void) @@ -260,7 +258,6 @@ static void led_init(void) /* If power LED is enabled, set it to "off" to start with */ if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) led_set_color_power(LED_OFF); - } DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From afcd7ef337723e243c38692518b50a976bf73afa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:22 -0600 Subject: driver/accelgyro_bmi160.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7e626f1f92e94f4b08a1106944b2db40c3aa7946 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729912 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi160.c | 249 ++++++++++++++++++++-------------------------- 1 file changed, 110 insertions(+), 139 deletions(-) diff --git a/driver/accelgyro_bmi160.c b/driver/accelgyro_bmi160.c index 184e20c9f5..366dadf2d0 100644 --- a/driver/accelgyro_bmi160.c +++ b/driver/accelgyro_bmi160.c @@ -25,25 +25,22 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) #ifdef CONFIG_ACCELGYRO_BMI160_INT_EVENT #define ACCELGYRO_BMI160_INT_ENABLE #endif -STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) void irq_set_orientation( - struct motion_sensor_t *s, - int interrupt); +STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) +void irq_set_orientation(struct motion_sensor_t *s, int interrupt); STATIC_IF(ACCELGYRO_BMI160_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; -static int wakeup_time[] = { - [MOTIONSENSE_TYPE_ACCEL] = 4, - [MOTIONSENSE_TYPE_GYRO] = 80, - [MOTIONSENSE_TYPE_MAG] = 1 -}; +static int wakeup_time[] = { [MOTIONSENSE_TYPE_ACCEL] = 4, + [MOTIONSENSE_TYPE_GYRO] = 80, + [MOTIONSENSE_TYPE_MAG] = 1 }; /** * Control access to the compass on the secondary i2c interface: @@ -51,14 +48,12 @@ static int wakeup_time[] = { * 1: manual access, we can issue i2c to the compass * 0: data access: BMI160 gather data periodically from the compass. */ -static __maybe_unused int bmi160_sec_access_ctrl( - const int port, - const uint16_t i2c_spi_addr_flags, - const int enable) +static __maybe_unused int +bmi160_sec_access_ctrl(const int port, const uint16_t i2c_spi_addr_flags, + const int enable) { int mag_if_ctrl; - bmi_read8(port, i2c_spi_addr_flags, - BMI160_MAG_IF_1, &mag_if_ctrl); + bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1, &mag_if_ctrl); if (enable) { mag_if_ctrl |= BMI160_MAG_MANUAL_EN; mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK; @@ -68,42 +63,36 @@ static __maybe_unused int bmi160_sec_access_ctrl( mag_if_ctrl &= ~BMI160_MAG_READ_BURST_MASK; mag_if_ctrl |= BMI160_MAG_READ_BURST_8; } - return bmi_write8(port, i2c_spi_addr_flags, - BMI160_MAG_IF_1, mag_if_ctrl); + return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_IF_1, + mag_if_ctrl); } /** * Read register from compass. * Assuming we are in manual access mode, read compass i2c register. */ -int bmi160_sec_raw_read8(const int port, - const uint16_t i2c_spi_addr_flags, +int bmi160_sec_raw_read8(const int port, const uint16_t i2c_spi_addr_flags, const uint8_t reg, int *data_ptr) { /* Only read 1 bytes */ - bmi_write8(port, i2c_spi_addr_flags, - BMI160_MAG_I2C_READ_ADDR, reg); - return bmi_read8(port, i2c_spi_addr_flags, - BMI160_MAG_I2C_READ_DATA, data_ptr); + bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_ADDR, reg); + return bmi_read8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_READ_DATA, + data_ptr); } /** * Write register from compass. * Assuming we are in manual access mode, write to compass i2c register. */ -int bmi160_sec_raw_write8(const int port, - const uint16_t i2c_spi_addr_flags, +int bmi160_sec_raw_write8(const int port, const uint16_t i2c_spi_addr_flags, const uint8_t reg, int data) { - bmi_write8(port, i2c_spi_addr_flags, - BMI160_MAG_I2C_WRITE_DATA, data); - return bmi_write8(port, i2c_spi_addr_flags, - BMI160_MAG_I2C_WRITE_ADDR, reg); + bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_DATA, data); + return bmi_write8(port, i2c_spi_addr_flags, BMI160_MAG_I2C_WRITE_ADDR, + reg); } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, - int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { int ret, normalized_rate; uint8_t reg_val; @@ -115,8 +104,7 @@ static int set_data_rate(const struct motion_sensor_t *s, bmi_enable_fifo(s, 0); /* go to suspend mode */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, BMI160_CMD_MODE_SUSPEND(s->type)); msleep(3); data->odr = 0; @@ -130,8 +118,7 @@ static int set_data_rate(const struct motion_sensor_t *s, return ret; } else if (data->odr == 0) { /* back from suspend mode. */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, BMI160_CMD_MODE_NORMAL(s->type)); msleep(wakeup_time[s->type]); } @@ -146,8 +133,7 @@ static int set_data_rate(const struct motion_sensor_t *s, */ mutex_lock(s->mutex); - ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), - reg_val, BMI_ODR_MASK); + ret = bmi_set_reg8(s, BMI_CONF_REG(s->type), reg_val, BMI_ODR_MASK); if (ret != EC_SUCCESS) goto accel_cleanup; @@ -165,9 +151,9 @@ static int set_data_rate(const struct motion_sensor_t *s, * for at least MIN_BATCH_WINDOW_US. * Given odr is in mHz, multiply by 1000x */ - moc->batch_size = MAX( - MAG_CAL_MIN_BATCH_SIZE, - (data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US)); + moc->batch_size = + MAX(MAG_CAL_MIN_BATCH_SIZE, + (data->odr * 1000) / (MAG_CAL_MIN_BATCH_WINDOW_US)); CPRINTS("Batch size: %d", moc->batch_size); } @@ -183,17 +169,16 @@ accel_cleanup: return ret; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { int ret, val98; intv3_t v = { offset[X], offset[Y], offset[Z] }; rotate_inv(v, *s->rot_standard_ref, v); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI160_OFFSET_EN_GYR98, &val98); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_OFFSET_EN_GYR98, + &val98); if (ret != 0) return ret; @@ -258,8 +243,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable) else val = BMI160_FOC_ACC_MINUS_1G; val = (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_X_OFFSET) | - (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) | - (val << BMI160_FOC_ACC_Z_OFFSET); + (BMI160_FOC_ACC_0G << BMI160_FOC_ACC_Y_OFFSET) | + (val << BMI160_FOC_ACC_Z_OFFSET); en_flag = BMI160_OFFSET_ACC_EN; /* * Temporary set range to minimum to run calibration with @@ -285,12 +270,11 @@ static int perform_calib(struct motion_sensor_t *s, int enable) /* Unreachable due to sensor type check above. */ ASSERT(false); return EC_RES_INVALID_PARAM; - /* LCOV_EXCL_STOP */ + /* LCOV_EXCL_STOP */ } - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_FOC_CONF, val); - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_START_FOC); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_FOC_CONF, val); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_START_FOC); deadline.val = get_time().val + timeout.val; do { if (timestamp_expired(deadline, NULL)) { @@ -298,8 +282,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable) goto end_perform_calib; } msleep(50); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI160_STATUS, &status); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_STATUS, + &status); if (ret != EC_SUCCESS) goto end_perform_calib; } while ((status & BMI160_FOC_RDY) == 0); @@ -319,8 +303,7 @@ end_perform_calib: */ #ifdef CONFIG_GESTURE_HOST_DETECTION static int manage_activity(const struct motion_sensor_t *s, - enum motionsensor_activity activity, - int enable, + enum motionsensor_activity activity, int enable, const struct ec_motion_sense_activity *param) { int ret; @@ -332,23 +315,23 @@ static int manage_activity(const struct motion_sensor_t *s, if (enable) { /* We should use parameters from caller */ bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_MOTION_3, - BMI160_MOTION_PROOF_TIME( - CONFIG_GESTURE_SIGMO_PROOF_MS) << - BMI160_MOTION_PROOF_OFF | - BMI160_MOTION_SKIP_TIME( - CONFIG_GESTURE_SIGMO_SKIP_MS) << - BMI160_MOTION_SKIP_OFF | - BMI160_MOTION_SIG_MOT_SEL); + BMI160_INT_MOTION_3, + BMI160_MOTION_PROOF_TIME( + CONFIG_GESTURE_SIGMO_PROOF_MS) + << BMI160_MOTION_PROOF_OFF | + BMI160_MOTION_SKIP_TIME( + CONFIG_GESTURE_SIGMO_SKIP_MS) + << BMI160_MOTION_SKIP_OFF | + BMI160_MOTION_SIG_MOT_SEL); bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_MOTION_1, - BMI160_MOTION_TH(s, - CONFIG_GESTURE_SIGMO_THRES_MG)); + BMI160_INT_MOTION_1, + BMI160_MOTION_TH( + s, CONFIG_GESTURE_SIGMO_THRES_MG)); } ret = bmi_enable_reg8(s, BMI160_INT_EN_0, BMI160_INT_ANYMO_X_EN | - BMI160_INT_ANYMO_Y_EN | - BMI160_INT_ANYMO_Z_EN, + BMI160_INT_ANYMO_Y_EN | + BMI160_INT_ANYMO_Z_EN, enable); if (ret) ret = EC_RES_UNAVAILABLE; @@ -358,8 +341,7 @@ static int manage_activity(const struct motion_sensor_t *s, #ifdef CONFIG_GESTURE_SENSOR_DOUBLE_TAP case MOTIONSENSE_ACTIVITY_DOUBLE_TAP: { /* Set double tap interrupt */ - ret = bmi_enable_reg8(s, BMI160_INT_EN_0, - BMI160_INT_D_TAP_EN, + ret = bmi_enable_reg8(s, BMI160_INT_EN_0, BMI160_INT_D_TAP_EN, enable); if (ret) ret = EC_RES_UNAVAILABLE; @@ -389,18 +371,18 @@ config_accel_interrupt(const struct motion_sensor_t *s) int ret, tmp; mutex_lock(s->mutex); - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_FIFO_FLUSH); - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_INT_RESET); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_FIFO_FLUSH); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_INT_RESET); if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP)) { - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_TAP_0, - BMI160_TAP_DUR(s, CONFIG_GESTURE_TAP_MAX_INTERSTICE_T)); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_TAP_0, + BMI160_TAP_DUR(s, + CONFIG_GESTURE_TAP_MAX_INTERSTICE_T)); ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_TAP_1, - BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG)); + BMI160_INT_TAP_1, + BMI160_TAP_TH(s, CONFIG_GESTURE_TAP_THRES_MG)); } /* only use orientation sensor on the lid sensor */ if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR) && @@ -415,17 +397,16 @@ config_accel_interrupt(const struct motion_sensor_t *s) if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT)) { ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_LATCH, BMI160_LATCH_5MS); + BMI160_INT_LATCH, BMI160_LATCH_5MS); } else { /* Also, configure int2 as an external input. */ ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_LATCH, - BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS); + BMI160_INT_LATCH, + BMI160_INT2_INPUT_EN | BMI160_LATCH_5MS); } /* configure int1 as an interrupt */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_OUT_CTRL, + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_OUT_CTRL, BMI160_INT_CTRL(1, OUTPUT_EN)); /* Map activity interrupt to int 1 */ @@ -439,15 +420,14 @@ config_accel_interrupt(const struct motion_sensor_t *s) /* enable orientation interrupt for lid sensor only */ tmp |= BMI160_INT_ORIENT; } - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_MAP_REG(1), tmp); + ret = bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_INT_MAP_REG(1), + tmp); if (IS_ENABLED(ACCELGYRO_BMI160_INT_ENABLE)) { /* map fifo water mark to int 1 */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_INT_FIFO_MAP, - BMI160_INT_MAP(1, FWM) | - BMI160_INT_MAP(1, FFULL)); + ret = bmi_write8( + s->port, s->i2c_spi_addr_flags, BMI160_INT_FIFO_MAP, + BMI160_INT_MAP(1, FWM) | BMI160_INT_MAP(1, FFULL)); /* * Configure fifo watermark to int whenever there's any data in @@ -457,13 +437,13 @@ config_accel_interrupt(const struct motion_sensor_t *s) BMI160_FIFO_CONFIG_0, 1); if (IS_ENABLED(CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT)) ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_FIFO_CONFIG_1, - BMI160_FIFO_HEADER_EN); + BMI160_FIFO_CONFIG_1, + BMI160_FIFO_HEADER_EN); else ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_FIFO_CONFIG_1, - BMI160_FIFO_TAG_INT2_EN | - BMI160_FIFO_HEADER_EN); + BMI160_FIFO_CONFIG_1, + BMI160_FIFO_TAG_INT2_EN | + BMI160_FIFO_HEADER_EN); /* Set fifo*/ bmi_enable_reg8(s, BMI160_INT_EN_1, @@ -475,17 +455,15 @@ config_accel_interrupt(const struct motion_sensor_t *s) #ifdef ACCELGYRO_BMI160_INT_ENABLE #ifdef CONFIG_BMI_ORIENTATION_SENSOR -static void irq_set_orientation(struct motion_sensor_t *s, - int interrupt) +static void irq_set_orientation(struct motion_sensor_t *s, int interrupt) { - int shifted_masked_orientation = - (interrupt >> 24) & BMI160_ORIENT_XY_MASK; + int shifted_masked_orientation = (interrupt >> 24) & + BMI160_ORIENT_XY_MASK; if (BMI_GET_DATA(s)->raw_orientation != shifted_masked_orientation) { enum motionsensor_orientation orientation = MOTIONSENSE_ORIENTATION_UNKNOWN; - BMI_GET_DATA(s)->raw_orientation = - shifted_masked_orientation; + BMI_GET_DATA(s)->raw_orientation = shifted_masked_orientation; switch (shifted_masked_orientation) { case BMI160_ORIENT_PORTRAIT: @@ -509,7 +487,7 @@ static void irq_set_orientation(struct motion_sensor_t *s, *motion_orientation_ptr(s) = orientation; } } -#endif /* CONFIG_BMI_ORIENTATION_SENSOR */ +#endif /* CONFIG_BMI_ORIENTATION_SENSOR */ /** * bmi160_interrupt - called when the sensor activates the interrupt line. @@ -531,15 +509,14 @@ void bmi160_interrupt(enum gpio_signal signal) * For now, we just print out. We should set a bitmask motion sense code will * act upon. */ -static int irq_handler(struct motion_sensor_t *s, - uint32_t *event) +static int irq_handler(struct motion_sensor_t *s, uint32_t *event) { uint32_t interrupt; int8_t has_read_fifo = 0; int rv; if ((s->type != MOTIONSENSE_TYPE_ACCEL) || - (!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT))) + (!(*event & CONFIG_ACCELGYRO_BMI160_INT_EVENT))) return EC_ERROR_NOT_HANDLED; do { @@ -554,11 +531,11 @@ static int irq_handler(struct motion_sensor_t *s, if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) && (interrupt & BMI160_D_TAP_INT)) *event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_DOUBLE_TAP); + MOTIONSENSE_ACTIVITY_DOUBLE_TAP); if (IS_ENABLED(CONFIG_GESTURE_SIGMO) && (interrupt & BMI160_SIGMOT_INT)) *event |= TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_SIG_MOTION); + MOTIONSENSE_ACTIVITY_SIG_MOTION); if (interrupt & (BMI160_FWM_INT | BMI160_FFULL_INT)) { bmi_load_fifo(s, last_interrupt_timestamp); has_read_fifo = 1; @@ -572,26 +549,25 @@ static int irq_handler(struct motion_sensor_t *s, return EC_SUCCESS; } -#endif /* ACCELGYRO_BMI160_INT_ENABLE */ +#endif /* ACCELGYRO_BMI160_INT_ENABLE */ static int init(struct motion_sensor_t *s) { int ret = 0, tmp, i; struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s); - ret = bmi_read8(s->port, s->i2c_spi_addr_flags, - BMI160_CHIP_ID, &tmp); + ret = bmi_read8(s->port, s->i2c_spi_addr_flags, BMI160_CHIP_ID, &tmp); if (ret) return EC_ERROR_UNKNOWN; if (tmp != BMI160_CHIP_ID_MAJOR && tmp != BMI168_CHIP_ID_MAJOR) { /* The device may be lock on paging mode. Try to unlock it. */ - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B0); - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B1); - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_EXT_MODE_EN_B2); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_EXT_MODE_EN_B0); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_EXT_MODE_EN_B1); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_EXT_MODE_EN_B2); bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_EXT_MODE_ADDR, BMI160_CMD_PAGING_EN); bmi_write8(s->port, s->i2c_spi_addr_flags, @@ -599,17 +575,15 @@ static int init(struct motion_sensor_t *s) return EC_ERROR_ACCESS_DENIED; } - if (s->type == MOTIONSENSE_TYPE_ACCEL) { struct bmi_drv_data_t *data = BMI_GET_DATA(s); /* Reset the chip to be in a good state */ - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_SOFT_RESET); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_SOFT_RESET); msleep(1); data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED | - (BMI_FIFO_ALL_MASK << - BMI_FIFO_FLAG_OFFSET)); + (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET)); if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { data->enabled_activities = 0; data->disabled_activities = 0; @@ -621,8 +595,8 @@ static int init(struct motion_sensor_t *s) BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP); } /* To avoid gyro wakeup */ - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_PMU_TRIGGER, 0); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_PMU_TRIGGER, + 0); } #ifdef CONFIG_BMI_SEC_I2C @@ -633,8 +607,8 @@ static int init(struct motion_sensor_t *s) * To be able to configure the real magnetometer, we must set * the BMI160 magnetometer part (a pass through) in normal mode. */ - bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_CMD_REG, BMI160_CMD_MODE_NORMAL(s->type)); + bmi_write8(s->port, s->i2c_spi_addr_flags, BMI160_CMD_REG, + BMI160_CMD_MODE_NORMAL(s->type)); msleep(wakeup_time[s->type]); if ((data->flags & BMI_FLAG_SEC_I2C_ENABLED) == 0) { @@ -670,21 +644,18 @@ static int init(struct motion_sensor_t *s) BMI160_CMD_EXT_MODE_ADDR, &ext_page_reg); /* Set the i2c address of the compass */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_MAG_IF_0, - I2C_STRIP_FLAGS( - CONFIG_ACCELGYRO_SEC_ADDR_FLAGS) - << 1); + ret = bmi_write8( + s->port, s->i2c_spi_addr_flags, BMI160_MAG_IF_0, + I2C_STRIP_FLAGS(CONFIG_ACCELGYRO_SEC_ADDR_FLAGS) + << 1); /* Enable the secondary interface as I2C */ - ret = bmi_write8(s->port, s->i2c_spi_addr_flags, - BMI160_IF_CONF, - BMI160_IF_MODE_AUTO_I2C << - BMI160_IF_MODE_OFF); + ret = bmi_write8( + s->port, s->i2c_spi_addr_flags, BMI160_IF_CONF, + BMI160_IF_MODE_AUTO_I2C << BMI160_IF_MODE_OFF); data->flags |= BMI_FLAG_SEC_I2C_ENABLED; } - bmi160_sec_access_ctrl(s->port, s->i2c_spi_addr_flags, 1); ret = bmm150_init(s); -- cgit v1.2.1 From e2e0c31661cd55f73b7f092c1610aff67a3ae94f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:27 -0600 Subject: board/terrador/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9cf6f7bdc9073fabeb5203361b6ebf8bf048cd7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729018 Reviewed-by: Jeremy Bettis --- board/terrador/sensors.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/terrador/sensors.c b/board/terrador/sensors.c index 77b26515c0..cce3807d91 100644 --- a/board/terrador/sensors.c +++ b/board/terrador/sensors.c @@ -85,17 +85,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From bbc39f5685e52fde13997075f7a9a746b1a33296 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:26 -0600 Subject: board/haboki/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0b5a76deef3e978e19b7af402cd53c73c1cdaa1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728444 Reviewed-by: Jeremy Bettis --- board/haboki/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/haboki/cbi_ssfc.c b/board/haboki/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/haboki/cbi_ssfc.c +++ b/board/haboki/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From d01b57072f33080bd9b5ba631c12c68c0b2b28b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:37 -0600 Subject: board/tigertail/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I226c52b3300b3a0f0b372871e8432538808a33c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729021 Reviewed-by: Jeremy Bettis --- board/tigertail/board.h | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/board/tigertail/board.h b/board/tigertail/board.h index 3b15c4c774..8c8f49d4da 100644 --- a/board/tigertail/board.h +++ b/board/tigertail/board.h @@ -40,19 +40,19 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_UPDATE 1 -#define USB_IFACE_USART1_STREAM 2 -#define USB_IFACE_I2C 3 -#define USB_IFACE_COUNT 4 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_UPDATE 1 +#define USB_IFACE_USART1_STREAM 2 +#define USB_IFACE_I2C 3 +#define USB_IFACE_COUNT 4 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_UPDATE 2 -#define USB_EP_USART1_STREAM 3 -#define USB_EP_I2C 4 -#define USB_EP_COUNT 5 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_UPDATE 2 +#define USB_EP_USART1_STREAM 3 +#define USB_EP_I2C 4 +#define USB_EP_COUNT 5 /* Enable console recasting of GPIO type. */ #define CONFIG_CMD_GPIO_EXTENDED @@ -77,14 +77,11 @@ */ #define CONFIG_SYSTEM_UNLOCKED - #ifndef __ASSEMBLER__ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 - - +#define TIM_ADC 3 #include "gpio_signal.h" -- cgit v1.2.1 From 5d84dcdacb6ad0e905cc79eabdb4c194858b61f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:45 -0600 Subject: board/kuldax/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I84c84f2151aae5265476c7a3a03483f0416d0e8a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728609 Reviewed-by: Jeremy Bettis --- board/kuldax/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kuldax/usbc_config.c b/board/kuldax/usbc_config.c index fddc9a449c..020a4696a5 100644 --- a/board/kuldax/usbc_config.c +++ b/board/kuldax/usbc_config.c @@ -32,8 +32,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { -- cgit v1.2.1 From 6f1983455d9466616edd6909cb7a0c8ec61a7bdd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:43 -0600 Subject: chip/stm32/adc_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4413610e683243205cf3404d3e4f5cecf558ec7b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729455 Reviewed-by: Jeremy Bettis --- chip/stm32/adc_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/adc_chip.h b/chip/stm32/adc_chip.h index 7e3c688c14..6e5ca3d824 100644 --- a/chip/stm32/adc_chip.h +++ b/chip/stm32/adc_chip.h @@ -48,7 +48,7 @@ struct adc_t { #endif #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32L4) - enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ + enum stm32_adc_smpr sample_rate; /* Sampling Rate of the channel */ #endif }; -- cgit v1.2.1 From 2fd01aaf557535a576a7bcbe97992e757de2b390 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:16 -0600 Subject: board/drallion_ish/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia07608cd8eff10d4668beeeab2b774ac59d45a9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728251 Reviewed-by: Jeremy Bettis --- board/drallion_ish/board.h | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/board/drallion_ish/board.h b/board/drallion_ish/board.h index a14656e701..019645d6e4 100644 --- a/board/drallion_ish/board.h +++ b/board/drallion_ish/board.h @@ -94,8 +94,8 @@ #define CONFIG_ISH_PM_D3 #define CONFIG_ISH_PM_RESET_PREP -#define CONFIG_ISH_D0I2_MIN_USEC (15*MSEC) -#define CONFIG_ISH_D0I3_MIN_USEC (100*MSEC) +#define CONFIG_ISH_D0I2_MIN_USEC (15 * MSEC) +#define CONFIG_ISH_D0I3_MIN_USEC (100 * MSEC) #ifndef __ASSEMBLER__ @@ -107,13 +107,7 @@ * Note: Since we aren't using LPC memory map to transmit sensor data, the * order of this enum does not need to be accel, accel, gyro */ -enum sensor_id { - LID_ACCEL, - LID_GYRO, - BASE_ACCEL, - LID_MAG, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, LID_GYRO, BASE_ACCEL, LID_MAG, SENSOR_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 374aa4418e310fcac7ec3cd1e20f7df673018541 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:28 -0600 Subject: board/gimble/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9763ea0f4f765afa0594c61b8b1f645628b5084 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728420 Reviewed-by: Jeremy Bettis --- board/gimble/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/gimble/usbc_config.h b/board/gimble/usbc_config.h index 87e601ee3e..56878a51f2 100644 --- a/board/gimble/usbc_config.h +++ b/board/gimble/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From 2f9ad3878c0c4c90a5f44cf41823efc27c170795 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:10 -0600 Subject: chip/stm32/usart-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59dd0e065c0cf35603d78fe695f14d22bf8bffd0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729416 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32l.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/chip/stm32/usart-stm32l.c b/chip/stm32/usart-stm32l.c index 8d23524bb0..a1eb7becd0 100644 --- a/chip/stm32/usart-stm32l.c +++ b/chip/stm32/usart-stm32l.c @@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; static void usart3_interrupt(void) -- cgit v1.2.1 From 54e5d57c65de57d32cd1606ee0f418abda349490 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:05 -0600 Subject: common/blink.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iafe8755f0f1cc496629ff2149477c012bd19dbbd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729592 Reviewed-by: Jeremy Bettis --- common/blink.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/blink.c b/common/blink.c index ed16146f5a..22523021dc 100644 --- a/common/blink.c +++ b/common/blink.c @@ -10,12 +10,12 @@ #include "hooks.h" #ifndef CONFIG_BLINK_LEDS - #error The macro CONFIG_BLINK_LEDS must be specified to use BLINK. +#error The macro CONFIG_BLINK_LEDS must be specified to use BLINK. #endif static const enum gpio_signal leds[] = { CONFIG_BLINK_LEDS }; -BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int)*8, "Too many LEDs to drive."); +BUILD_ASSERT(ARRAY_SIZE(leds) <= sizeof(int) * 8, "Too many LEDs to drive."); BUILD_ASSERT(ARRAY_SIZE(leds) > 0, "Must have at least one LED to blink."); static void blink(void) -- cgit v1.2.1 From 662b592c868995287a82174e5ed84205fa2230e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:17 -0600 Subject: include/aes-gcm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c336ba70c3a5a5536200b201491ec64c52326b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730201 Reviewed-by: Jeremy Bettis --- include/aes-gcm.h | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) mode change 120000 => 100644 include/aes-gcm.h diff --git a/include/aes-gcm.h b/include/aes-gcm.h deleted file mode 120000 index ba62939792..0000000000 --- a/include/aes-gcm.h +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/include/aes-gcm.h \ No newline at end of file diff --git a/include/aes-gcm.h b/include/aes-gcm.h new file mode 100644 index 0000000000..2227ddb384 --- /dev/null +++ b/include/aes-gcm.h @@ -0,0 +1,141 @@ +/* ==================================================================== + * Copyright (c) 2008 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== */ + +#ifndef __CROS_EC_AES_GCM_H +#define __CROS_EC_AES_GCM_H + +#include "common.h" +#include "util.h" + +// block128_f is the type of a 128-bit, block cipher. +typedef void (*block128_f)(const uint8_t in[16], uint8_t out[16], + const void *key); + +// GCM definitions +typedef struct { + uint64_t hi, lo; +} u128; + +// gmult_func multiplies |Xi| by the GCM key and writes the result back to +// |Xi|. +typedef void (*gmult_func)(uint64_t Xi[2], const u128 Htable[16]); + +// ghash_func repeatedly multiplies |Xi| by the GCM key and adds in blocks from +// |inp|. The result is written back to |Xi| and the |len| argument must be a +// multiple of 16. +typedef void (*ghash_func)(uint64_t Xi[2], const u128 Htable[16], + const uint8_t *inp, size_t len); + +// This differs from upstream's |gcm128_context| in that it does not have the +// |key| pointer, in order to make it |memcpy|-friendly. Rather the key is +// passed into each call that needs it. +struct gcm128_context { + // Following 6 names follow names in GCM specification + union { + uint64_t u[2]; + uint32_t d[4]; + uint8_t c[16]; + size_t t[16 / sizeof(size_t)]; + } Yi, EKi, EK0, len, Xi; + + // Note that the order of |Xi|, |H| and |Htable| is fixed by the + // MOVBE-based, x86-64, GHASH assembly. + u128 H; + u128 Htable[16]; + gmult_func gmult; + ghash_func ghash; + + unsigned int mres, ares; + block128_f block; +}; + +// GCM. +// +// This API differs from the upstream API slightly. The |GCM128_CONTEXT| does +// not have a |key| pointer that points to the key as upstream's version does. +// Instead, every function takes a |key| parameter. This way |GCM128_CONTEXT| +// can be safely copied. + +typedef struct gcm128_context GCM128_CONTEXT; + +// CRYPTO_gcm128_init initialises |ctx| to use |block| (typically AES) with +// the given key. |block_is_hwaes| is one if |block| is |aes_hw_encrypt|. +void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *key, block128_f block, + int block_is_hwaes); + +// CRYPTO_gcm128_setiv sets the IV (nonce) for |ctx|. The |key| must be the +// same key that was passed to |CRYPTO_gcm128_init|. +void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key, + const uint8_t *iv, size_t iv_len); + +// CRYPTO_gcm128_aad sets the authenticated data for an instance of GCM. +// This must be called before and data is encrypted. It returns one on success +// and zero otherwise. +int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len); + +// CRYPTO_gcm128_encrypt encrypts |len| bytes from |in| to |out|. The |key| +// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one +// on success and zero otherwise. +int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key, + const uint8_t *in, uint8_t *out, size_t len); + +// CRYPTO_gcm128_decrypt decrypts |len| bytes from |in| to |out|. The |key| +// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one +// on success and zero otherwise. +int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key, + const uint8_t *in, uint8_t *out, size_t len); + +// CRYPTO_gcm128_finish calculates the authenticator and compares it against +// |len| bytes of |tag|. It returns one on success and zero otherwise. +int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len); + +// CRYPTO_gcm128_tag calculates the authenticator and copies it into |tag|. +// The minimum of |len| and 16 bytes are copied into |tag|. +void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, uint8_t *tag, size_t len); + +#endif // __CROS_EC_AES_GCM_H -- cgit v1.2.1 From e276a6a50019204a8647b10a248bbc9541fecac2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:09 -0600 Subject: board/servo_micro/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifec15ae3f185d98411a77d70b0a217829ce803a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728903 Reviewed-by: Jeremy Bettis --- board/servo_micro/board.c | 150 ++++++++++++++++++---------------------------- 1 file changed, 58 insertions(+), 92 deletions(-) diff --git a/board/servo_micro/board.c b/board/servo_micro/board.c index f82376a15a..d66ec58556 100644 --- a/board/servo_micro/board.c +++ b/board/servo_micro/board.c @@ -45,21 +45,20 @@ void board_config_pre_init(void) * i2c : no dma * tim16/17: no dma */ - STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */ /* Remap SPI2 to DMA channels 6 and 7 */ /* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */ /* but cros_ec hardcodes a 6/7 assumption in registers.h */ STM32_SYSCFG_CFGR1 |= BIT(24); - } /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 32 -#define USB_STREAM_TX_SIZE 64 +#define USB_STREAM_RX_SIZE 32 +#define USB_STREAM_TX_SIZE 64 /****************************************************************************** * Forward USART2 (EC) as a simple USB serial interface. @@ -68,33 +67,22 @@ void board_config_pre_init(void) static struct usart_config const usart2; struct usb_stream_config const usart2_usb; -static struct queue const usart2_to_usb = QUEUE_DIRECT(1024, uint8_t, - usart2.producer, usart2_usb.consumer); -static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t, - usart2_usb.producer, usart2.consumer); +static struct queue const usart2_to_usb = + QUEUE_DIRECT(1024, uint8_t, usart2.producer, usart2_usb.consumer); +static struct queue const usb_to_usart2 = + QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer); static struct usart_rx_dma const usart2_rx_dma = USART_RX_DMA(STM32_DMAC_CH5, 32); static struct usart_config const usart2 = - USART_CONFIG(usart2_hw, - usart2_rx_dma.usart_rx, - usart_tx_interrupt, - 115200, - 0, - usart2_to_usb, - usb_to_usart2); - -USB_STREAM_CONFIG_USART_IFACE(usart2_usb, - USB_IFACE_USART2_STREAM, - USB_STR_USART2_STREAM_NAME, - USB_EP_USART2_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart2, - usart2_to_usb, - usart2) + USART_CONFIG(usart2_hw, usart2_rx_dma.usart_rx, usart_tx_interrupt, + 115200, 0, usart2_to_usb, usb_to_usart2); +USB_STREAM_CONFIG_USART_IFACE(usart2_usb, USB_IFACE_USART2_STREAM, + USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart2, usart2_to_usb, usart2) /****************************************************************************** * Forward USART3 (CPU) as a simple USB serial interface. @@ -103,33 +91,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart2_usb, static struct usart_config const usart3; struct usb_stream_config const usart3_usb; -static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t, - usart3.producer, usart3_usb.consumer); -static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t, - usart3_usb.producer, usart3.consumer); +static struct queue const usart3_to_usb = + QUEUE_DIRECT(1024, uint8_t, usart3.producer, usart3_usb.consumer); +static struct queue const usb_to_usart3 = + QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer); static struct usart_rx_dma const usart3_rx_dma = USART_RX_DMA(STM32_DMAC_CH3, 32); static struct usart_config const usart3 = - USART_CONFIG(usart3_hw, - usart3_rx_dma.usart_rx, - usart_tx_interrupt, - 115200, - 0, - usart3_to_usb, - usb_to_usart3); - -USB_STREAM_CONFIG_USART_IFACE(usart3_usb, - USB_IFACE_USART3_STREAM, - USB_STR_USART3_STREAM_NAME, - USB_EP_USART3_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart3, - usart3_to_usb, - usart3) + USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt, + 115200, 0, usart3_to_usb, usb_to_usart3); +USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM, + USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart3, usart3_to_usb, usart3) /****************************************************************************** * Forward USART4 (cr50) as a simple USB serial interface. @@ -139,29 +116,19 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG_USART_IFACE(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb, - usart4) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart4_to_usb, usb_to_usart4); + +USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart4, usart4_to_usb, usart4) /****************************************************************************** * Check parity setting on usarts. @@ -200,8 +167,7 @@ static int command_uart_parity(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, - "usart[2|3|4] [0|1|2]", +DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]", "Set parity on uart"); /****************************************************************************** @@ -233,8 +199,7 @@ static int command_uart_baud(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, - "usart[2|3|4] rate", +DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate", "Set baud rate on uart"); /****************************************************************************** @@ -297,7 +262,7 @@ static int command_hold_usart_low(int argc, char **argv) /* Print status for get and set case. */ ccprintf("USART status: %s\n", - usart_status & usart_mask ? "held low" : "normal"); + usart_status & usart_mask ? "held low" : "normal"); return EC_SUCCESS; } @@ -309,18 +274,18 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low, * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Servo Micro"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART3"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Servo Micro"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART3"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo Shell"), - [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"), - [USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("EC"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"), + [USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("EC"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -332,7 +297,7 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); /* SPI devices */ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS}, + { CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CS }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); @@ -373,17 +338,18 @@ USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /* Configure ITE flash support module */ const struct ite_dfu_config_t ite_dfu_config = { -- cgit v1.2.1 From 6ec5727d132e37da95e81cf188b045934ad650ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:32 -0600 Subject: include/thermal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I851fa80273b89f0d3c59469cd735457eb23f764b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730421 Reviewed-by: Jeremy Bettis --- include/thermal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/thermal.h b/include/thermal.h index 29d8073ca0..671d826805 100644 --- a/include/thermal.h +++ b/include/thermal.h @@ -27,4 +27,4 @@ int thermal_fan_percent(int low, int high, int cur); */ void board_override_fan_control(int fan, int *tmp); -#endif /* __CROS_EC_THERMAL_H */ +#endif /* __CROS_EC_THERMAL_H */ -- cgit v1.2.1 From f9b240492004554a59bf5fc64cb5df382ce2556b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:02 -0600 Subject: board/icarus/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f89498411c5330ffbdf33638f55f2a3ed92360a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728511 Reviewed-by: Jeremy Bettis --- board/icarus/board.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/icarus/board.h b/board/icarus/board.h index 0fe63af10c..bf664da5aa 100644 --- a/board/icarus/board.h +++ b/board/icarus/board.h @@ -48,14 +48,14 @@ #undef CONFIG_ACCEL_FIFO_THRES /* I2C ports */ -#define I2C_PORT_BC12 IT83XX_I2C_CH_C -#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_SENSORS IT83XX_I2C_CH_B -#define I2C_PORT_ACCEL I2C_PORT_SENSORS -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 IT83XX_I2C_CH_C +#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C +#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A +#define I2C_PORT_SENSORS IT83XX_I2C_CH_B +#define I2C_PORT_ACCEL I2C_PORT_SENSORS +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT @@ -114,7 +114,7 @@ enum battery_type { /* support factory keyboard test */ #define CONFIG_KEYBOARD_FACTORY_TEST -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV #ifdef SECTION_IS_RO /* Interrupt handler for AP jump to BL */ -- cgit v1.2.1 From 037a83444dd938098b0f103da7e324a531bdaa05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:59 -0600 Subject: board/kukui_scp/isp_p1_srv.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia600d2dc76f8f75f7f02f3968cd710ff18a16fa1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728541 Reviewed-by: Jeremy Bettis --- board/kukui_scp/isp_p1_srv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kukui_scp/isp_p1_srv.h b/board/kukui_scp/isp_p1_srv.h index ba6fa7d110..dbecef96d9 100644 --- a/board/kukui_scp/isp_p1_srv.h +++ b/board/kukui_scp/isp_p1_srv.h @@ -13,7 +13,8 @@ struct isp_msg { unsigned char msg[140]; }; -BUILD_ASSERT(member_size(struct isp_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE); +BUILD_ASSERT(member_size(struct isp_msg, msg) <= + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void isp_msg_handler(void *data); -- cgit v1.2.1 From 2d8ee17cd5da4d63763cdea824f4b17170cd1a2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:03 -0600 Subject: core/cortex-m0/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf6ec8c57eb942ea0f884dd78c1ef2b87fcb29e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729829 Reviewed-by: Jeremy Bettis --- core/cortex-m0/cpu.h | 50 ++++++++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index c30095fd65..48abf916d6 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -12,39 +12,39 @@ #include "compile_time_macros.h" /* Macro to access 32-bit registers */ -#define CPUREG(addr) (*(volatile uint32_t*)(addr)) +#define CPUREG(addr) (*(volatile uint32_t *)(addr)) /* Nested Vectored Interrupt Controller */ -#define CPU_NVIC_EN(x) CPUREG(0xe000e100) -#define CPU_NVIC_DIS(x) CPUREG(0xe000e180) -#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) -#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) +#define CPU_NVIC_EN(x) CPUREG(0xe000e100) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180) +#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) +#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* System Control Block */ -#define CPU_SCB_ICSR CPUREG(0xe000ed04) +#define CPU_SCB_ICSR CPUREG(0xe000ed04) /* SCB AIRCR : Application interrupt and reset control register */ -#define CPU_NVIC_APINT CPUREG(0xe000ed0c) -#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ -#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ -#define CPU_NVIC_APINT_KEY_RD (0U) -#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +#define CPU_NVIC_APINT_SYSRST BIT(2) /* System reset request */ +#define CPU_NVIC_APINT_ENDIAN BIT(15) /* Endianness */ +#define CPU_NVIC_APINT_KEY_RD (0U) +#define CPU_NVIC_APINT_KEY_WR (0x05FAU << 16) /* SCB SCR : System Control Register */ -#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) -#define CPU_NVIC_CCR CPUREG(0xe000ed14) -#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) -#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) +#define CPU_NVIC_CCR CPUREG(0xe000ed14) +#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) +#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) #define CPU_NVIC_CCR_UNALIGN_TRAP BIT(3) /* Bitfield values for EXC_RETURN. */ -#define EXC_RETURN_SPSEL_MASK BIT(2) -#define EXC_RETURN_SPSEL_MSP 0 -#define EXC_RETURN_SPSEL_PSP BIT(2) -#define EXC_RETURN_MODE_MASK BIT(3) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD BIT(3) +#define EXC_RETURN_SPSEL_MASK BIT(2) +#define EXC_RETURN_SPSEL_MSP 0 +#define EXC_RETURN_SPSEL_PSP BIT(2) +#define EXC_RETURN_MODE_MASK BIT(3) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD BIT(3) /* Set up the cpu to detect faults */ void cpu_init(void); @@ -57,10 +57,8 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) if (priority > 3) priority = 3; - CPU_NVIC_PRI(irq / 4) = - (CPU_NVIC_PRI(irq / 4) & - ~(3 << prio_shift)) | - (priority << prio_shift); + CPU_NVIC_PRI(irq / 4) = (CPU_NVIC_PRI(irq / 4) & ~(3 << prio_shift)) | + (priority << prio_shift); } #endif /* __CROS_EC_CPU_H */ -- cgit v1.2.1 From aeb66494e0b75e27bd5b78bceaa2d130ed074bdb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:55 -0600 Subject: board/dood/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4021c3ed32ddc819dc253f8237dfe042cb7d4d8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728233 Reviewed-by: Jeremy Bettis --- board/dood/board.c | 98 +++++++++++++++++++++++++----------------------------- 1 file changed, 46 insertions(+), 52 deletions(-) diff --git a/board/dood/board.c b/board/dood/board.c index cef4c21268..de107a2fc7 100644 --- a/board/dood/board.c +++ b/board/dood/board.c @@ -45,11 +45,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -59,17 +59,16 @@ static uint8_t sku_id; * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* Check PPC ID and board version to decide which one ppc is used. */ static bool support_syv_ppc(void) @@ -87,7 +86,6 @@ static bool support_syv_ppc(void) static void ppc_interrupt(enum gpio_signal signal) { - switch (signal) { case GPIO_USB_PD_C0_INT_ODL: if (support_syv_ppc()) @@ -113,31 +111,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -147,11 +145,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -274,8 +270,8 @@ void board_hibernate_late(void) const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_BAT_LED_WHITE_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) @@ -307,15 +303,15 @@ void board_overcurrent_event(int port, int is_overcurrented) } const struct ppc_config_t ppc_syv682x_port0 = { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; const struct ppc_config_t ppc_syv682x_port1 = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }; static void board_setup_ppc(void) @@ -323,12 +319,10 @@ static void board_setup_ppc(void) if (!support_syv_ppc()) return; - memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], - &ppc_syv682x_port0, - sizeof(struct ppc_config_t)); - memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], - &ppc_syv682x_port1, - sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0, + sizeof(struct ppc_config_t)); + memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1, + sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH); gpio_set_flags(GPIO_USB_PD_C1_INT_ODL, GPIO_INT_BOTH); -- cgit v1.2.1 From 7e205f695942520da6c9df717e410315fb9768d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:14 -0600 Subject: chip/npcx/uartn.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b4e86a814c5d498c191ae6b151c994139bb5038 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729445 Reviewed-by: Jeremy Bettis --- chip/npcx/uartn.c | 64 +++++++++++++++++++++++++++---------------------------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c index 2269e11e7c..4f486dcb56 100644 --- a/chip/npcx/uartn.c +++ b/chip/npcx/uartn.c @@ -17,60 +17,58 @@ #ifdef NPCX_UART_FIFO_SUPPORT /* Enable UART Tx FIFO empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_EN(n) \ - (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_EN(n) \ + (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* True if UART Tx FIFO empty interrupt is enabled */ -#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \ - (IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) \ + (IS_BIT_SET(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* Disable UART Tx FIFO empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_DIS(n) \ - (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) +#define NPCX_UART_TX_EMPTY_INT_DIS(n) \ + (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_TEMPTY_EN)) /* True if the Tx FIFO is not completely full */ -#define NPCX_UART_TX_IS_READY(n) \ - (!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0)) +#define NPCX_UART_TX_IS_READY(n) \ + (!(GET_FIELD(NPCX_UFTSTS(n), NPCX_UFTSTS_TEMPTY_LVL) == 0)) /* Enable UART Tx "not" in transmission interrupt */ -#define NPCX_UART_TX_NXMIP_INT_EN(n) \ - (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) +#define NPCX_UART_TX_NXMIP_INT_EN(n) \ + (SET_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) /* Disable UART Tx "not" in transmission interrupt */ -#define NPCX_UART_TX_NXMIP_INT_DIS(n) \ - (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) +#define NPCX_UART_TX_NXMIP_INT_DIS(n) \ + (CLEAR_BIT(NPCX_UFTCTL(n), NPCX_UFTCTL_NXMIPEN)) /* * True if Tx is in progress * (i.e. FIFO is not empty or last byte in TSFT (Transmit Shift register) * is not sent) */ -#define NPCX_UART_TX_IN_XMIT(n) \ - (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP)) +#define NPCX_UART_TX_IN_XMIT(n) (!IS_BIT_SET(NPCX_UFTSTS(n), NPCX_UFTSTS_NXMIP)) /* * Enable to generate interrupt when there is at least one byte * in the receive FIFO */ -#define NPCX_UART_RX_INT_EN(n) \ - (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN)) +#define NPCX_UART_RX_INT_EN(n) (SET_BIT(NPCX_UFRCTL(n), NPCX_UFRCTL_RNEMPTY_EN)) /* True if at least one byte is in the receive FIFO */ -#define NPCX_UART_RX_IS_AVAILABLE(n) \ - (IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS)) +#define NPCX_UART_RX_IS_AVAILABLE(n) \ + (IS_BIT_SET(NPCX_UFRSTS(n), NPCX_UFRSTS_RFIFO_NEMPTY_STS)) #else /* Enable UART Tx buffer empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20) +#define NPCX_UART_TX_EMPTY_INT_EN(n) (NPCX_UICTRL(n) |= 0x20) /* True if UART Tx buffer empty interrupt is enabled */ -#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20) +#define NPCX_UART_TX_EMPTY_INT_IS_EN(n) (NPCX_UICTRL(n) & 0x20) /* Disable UART Tx buffer empty interrupt */ -#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20) +#define NPCX_UART_TX_EMPTY_INT_DIS(n) (NPCX_UICTRL(n) &= ~0x20) /* True if 1-byte Tx buffer is empty */ -#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01) +#define NPCX_UART_TX_IS_READY(n) (NPCX_UICTRL(n) & 0x01) /* * True if Tx is in progress * (i.e. Tx buffer is not empty or last byte in TSFT (Transmit Shift register) * is not sent) */ -#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40) - /* Enable to generate interrupt when there is data in the receive buffer */ -#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40) +#define NPCX_UART_TX_IN_XMIT(n) (NPCX_USTAT(n) & 0x40) +/* Enable to generate interrupt when there is data in the receive buffer */ +#define NPCX_UART_RX_INT_EN(n) (NPCX_UICTRL(n) = 0x40) /* True if there is data in the 1-byte Receive buffer */ -#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02) +#define NPCX_UART_RX_IS_AVAILABLE(n) (NPCX_UICTRL(n) & 0x02) #endif struct uart_configs { @@ -79,9 +77,9 @@ struct uart_configs { uint32_t clk_en_msk; }; static const struct uart_configs uart_cfg[] = { - {NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK}, + { NPCX_IRQ_UART, CGC_OFFSET_UART, CGC_UART_MASK }, #ifdef NPCX_SECOND_UART - {NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK}, + { NPCX_IRQ_UART2, CGC_OFFSET_UART2, CGC_UART2_MASK }, #endif }; BUILD_ASSERT(ARRAY_SIZE(uart_cfg) == UART_MODULE_COUNT); @@ -144,7 +142,7 @@ void uartn_tx_start(uint8_t uart_num) void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable) { enable ? NPCX_UART_TX_NXMIP_INT_EN(uart_num) : - NPCX_UART_TX_NXMIP_INT_DIS(uart_num); + NPCX_UART_TX_NXMIP_INT_DIS(uart_num); } #endif @@ -198,7 +196,7 @@ int uartn_read_char(uint8_t uart_num) void uartn_clear_rx_fifo(int channel) { - int scratch __attribute__ ((unused)); + int scratch __attribute__((unused)); /* If '1', that means there is RX data on the FIFO register */ while (NPCX_UART_RX_IS_AVAILABLE(channel)) @@ -211,9 +209,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num) /* Enable the UART FIFO mode */ SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD); /* Disable all Tx interrupts */ - NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | - BIT(NPCX_UFTCTL_TEMPTY_EN) | - BIT(NPCX_UFTCTL_NXMIPEN)); + NPCX_UFTCTL(uart_num) &= + ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | BIT(NPCX_UFTCTL_TEMPTY_EN) | + BIT(NPCX_UFTCTL_NXMIPEN)); } #endif -- cgit v1.2.1 From e69ca7b12399147aa0edf9da7ed6d1da8fbe9823 Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Fri, 24 Jun 2022 19:23:09 +0800 Subject: cherry/dojo: Move board_set_charge_limit to board level BUG=none BRANCH=cherry TEST=make BOARD=cherry, dojo Signed-off-by: Tommy Chung Change-Id: I5868ce77b6d85b9755e74c16e9430224bdfe8dde Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721949 Reviewed-by: Devin Lu Reviewed-by: Ting Shen --- baseboard/cherry/baseboard.c | 7 ------- board/cherry/board.c | 9 +++++++++ board/dojo/board.c | 9 +++++++++ 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/baseboard/cherry/baseboard.c b/baseboard/cherry/baseboard.c index 223358d377..ff9b5316fd 100644 --- a/baseboard/cherry/baseboard.c +++ b/baseboard/cherry/baseboard.c @@ -368,13 +368,6 @@ void board_reset_pd_mcu(void) /* C1: Add code if TCPC chips need a reset */ } -void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, - int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) { /* diff --git a/board/cherry/board.c b/board/cherry/board.c index 69828d19b5..8160dafa62 100644 --- a/board/cherry/board.c +++ b/board/cherry/board.c @@ -4,6 +4,8 @@ */ /* Cherry board configuration */ +#include "charge_manager.h" +#include "charge_state_v2.h" #include "common.h" #include "console.h" #include "driver/accel_bma422.h" @@ -263,6 +265,13 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + /* Initialize board. */ static void board_init(void) { diff --git a/board/dojo/board.c b/board/dojo/board.c index 4d7178bfad..bb819b02d5 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -5,6 +5,8 @@ /* Dojo board configuration */ #include "cbi_fw_config.h" +#include "charge_manager.h" +#include "charge_state_v2.h" #include "common.h" #include "console.h" #include "cros_board_info.h" @@ -375,6 +377,13 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + /* Initialize board. */ static void board_init(void) { -- cgit v1.2.1 From f24199f2b06bbd70b8ac7070f66e108279509daf Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Fri, 24 Jun 2022 19:33:18 +0800 Subject: dojo: Set max input current limit to 2944mA Limit input current lower than 2944mA for safety. BUG=b:236911774 BRANCH=cherry TEST=make sure safety test pass. Signed-off-by: Tommy Chung Change-Id: Id7707a2d919889308d0cbbca6fe94a3fcf003b7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721950 Reviewed-by: Devin Lu Reviewed-by: Ting Shen --- board/dojo/board.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/dojo/board.c b/board/dojo/board.c index bb819b02d5..2de269c002 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -380,6 +380,9 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { + /* Limit input current lower than 2944 mA for safety */ + charge_ma = MIN(charge_ma, 2944); + charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 6c3251cb727cc683e6aec426e4a5d83bf00ca4e8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:08 -0600 Subject: board/gelarshie/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idbe9751d75a1904564a22e0ef643610c258f3563 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728392 Reviewed-by: Jeremy Bettis --- board/gelarshie/base_detect.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/gelarshie/base_detect.c b/board/gelarshie/base_detect.c index a5bbca427b..ecac6c7a85 100644 --- a/board/gelarshie/base_detect.c +++ b/board/gelarshie/base_detect.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Base detection and debouncing */ #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC) @@ -93,8 +93,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -144,12 +144,12 @@ void base_detect_interrupt(enum gpio_signal signal) { uint64_t time_now = get_time().val; int debounce_us; - + if (detect_pin_connected(signal)) debounce_us = BASE_DETECT_EN_DEBOUNCE_US; - else + else debounce_us = BASE_DETECT_DIS_DEBOUNCE_US; - + if (base_detect_debounce_time <= time_now) { /* * Detect and measure detection pin pulse, when base is @@ -211,7 +211,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From c0c29c28ae6c5b27a6510c757605f6f01e98a2b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:49 -0600 Subject: baseboard/asurada/it5205_sbu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5bf197a4934314b3fe0f76d88376cbe7951eba42 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727852 Reviewed-by: Jeremy Bettis --- baseboard/asurada/it5205_sbu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/asurada/it5205_sbu.c b/baseboard/asurada/it5205_sbu.c index 9ee59a5cc3..53c9defecf 100644 --- a/baseboard/asurada/it5205_sbu.c +++ b/baseboard/asurada/it5205_sbu.c @@ -12,8 +12,8 @@ #include "timer.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define OVP_RETRY_DELAY_US_MIN (100 * MSEC) -- cgit v1.2.1 From 6d861cdd77db9c147e1d5e8a6a65f73c5e23a7c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:50 -0600 Subject: zephyr/emul/emul_bmi160.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I76096148dbb5aacb4bac5ce06b41d419df297d33 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730687 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_bmi160.c | 383 +++++++++++++++++++++++----------------------- 1 file changed, 190 insertions(+), 193 deletions(-) diff --git a/zephyr/emul/emul_bmi160.c b/zephyr/emul/emul_bmi160.c index 9a2f4b5cf1..cc761fce6e 100644 --- a/zephyr/emul/emul_bmi160.c +++ b/zephyr/emul/emul_bmi160.c @@ -21,105 +21,105 @@ LOG_MODULE_REGISTER(emul_bmi160); /** Mask reserved bits in each register of BMI160 */ static const uint8_t bmi_emul_160_rsvd_mask[] = { - [BMI160_CHIP_ID] = 0x00, - [0x01] = 0xff, /* Reserved */ - [BMI160_ERR_REG] = 0x00, - [BMI160_PMU_STATUS] = 0xc0, - [BMI160_MAG_X_L_G] = 0x00, - [BMI160_MAG_X_H_G] = 0x00, - [BMI160_MAG_Y_L_G] = 0x00, - [BMI160_MAG_Y_H_G] = 0x00, - [BMI160_MAG_Z_L_G] = 0x00, - [BMI160_MAG_Z_H_G] = 0x00, - [BMI160_RHALL_L_G] = 0x00, - [BMI160_RHALL_H_G] = 0x00, - [BMI160_GYR_X_L_G] = 0x00, - [BMI160_GYR_X_H_G] = 0x00, - [BMI160_GYR_Y_L_G] = 0x00, - [BMI160_GYR_Y_H_G] = 0x00, - [BMI160_GYR_Z_L_G] = 0x00, - [BMI160_GYR_Z_H_G] = 0x00, - [BMI160_ACC_X_L_G] = 0x00, - [BMI160_ACC_X_H_G] = 0x00, - [BMI160_ACC_Y_L_G] = 0x00, - [BMI160_ACC_Y_H_G] = 0x00, - [BMI160_ACC_Z_L_G] = 0x00, - [BMI160_ACC_Z_H_G] = 0x00, - [BMI160_SENSORTIME_0] = 0x00, - [BMI160_SENSORTIME_1] = 0x00, - [BMI160_SENSORTIME_2] = 0x00, - [BMI160_STATUS] = 0x01, - [BMI160_INT_STATUS_0] = 0x00, - [BMI160_INT_STATUS_1] = 0x03, - [BMI160_INT_STATUS_2] = 0x00, - [BMI160_INT_STATUS_3] = 0x00, - [BMI160_TEMPERATURE_0] = 0x00, - [BMI160_TEMPERATURE_1] = 0x00, - [BMI160_FIFO_LENGTH_0] = 0x00, - [BMI160_FIFO_LENGTH_1] = 0xf8, - [BMI160_FIFO_DATA] = 0x00, - [0x25 ... 0x3f] = 0xff, /* Reserved */ - [BMI160_ACC_CONF] = 0x00, - [BMI160_ACC_RANGE] = 0xf0, - [BMI160_GYR_CONF] = 0xc0, - [BMI160_GYR_RANGE] = 0xf8, - [BMI160_MAG_CONF] = 0xf0, - [BMI160_FIFO_DOWNS] = 0x00, - [BMI160_FIFO_CONFIG_0] = 0x00, - [BMI160_FIFO_CONFIG_1] = 0x01, - [0x48 ... 0x4a] = 0xff, /* Reserved */ - [BMI160_MAG_IF_0] = 0x01, - [BMI160_MAG_IF_1] = 0x40, - [BMI160_MAG_IF_2] = 0x00, - [BMI160_MAG_IF_3] = 0x00, - [BMI160_MAG_IF_4] = 0x00, - [BMI160_INT_EN_0] = 0x08, - [BMI160_INT_EN_1] = 0x80, - [BMI160_INT_EN_2] = 0xf0, - [BMI160_INT_OUT_CTRL] = 0x00, - [BMI160_INT_LATCH] = 0xc0, - [BMI160_INT_MAP_0] = 0x00, - [BMI160_INT_MAP_1] = 0x00, - [BMI160_INT_MAP_2] = 0x00, - [BMI160_INT_DATA_0] = 0x77, - [BMI160_INT_DATA_1] = 0x7f, - [BMI160_INT_LOW_HIGH_0] = 0x00, - [BMI160_INT_LOW_HIGH_1] = 0x00, - [BMI160_INT_LOW_HIGH_2] = 0x3c, - [BMI160_INT_LOW_HIGH_3] = 0x00, - [BMI160_INT_LOW_HIGH_4] = 0x00, - [BMI160_INT_MOTION_0] = 0x00, - [BMI160_INT_MOTION_1] = 0x00, - [BMI160_INT_MOTION_2] = 0x00, - [BMI160_INT_MOTION_3] = 0xc0, - [BMI160_INT_TAP_0] = 0x38, - [BMI160_INT_TAP_1] = 0xe0, - [BMI160_INT_ORIENT_0] = 0x00, - [BMI160_INT_ORIENT_1] = 0x00, - [BMI160_INT_FLAT_0] = 0xc0, - [BMI160_INT_FLAT_1] = 0xc8, - [BMI160_FOC_CONF] = 0x80, - [BMI160_CONF] = 0xfd, - [BMI160_IF_CONF] = 0xce, - [BMI160_PMU_TRIGGER] = 0x80, - [BMI160_SELF_TEST] = 0xe0, - [0x6e] = 0xff, /* Reserved */ - [0x6f] = 0xff, /* Reserved */ - [BMI160_NV_CONF] = 0xf0, - [BMI160_OFFSET_ACC70] = 0x00, - [BMI160_OFFSET_ACC70 + 1] = 0x00, - [BMI160_OFFSET_ACC70 + 2] = 0x00, - [BMI160_OFFSET_GYR70] = 0x00, - [BMI160_OFFSET_GYR70 + 1] = 0x00, - [BMI160_OFFSET_GYR70 + 2] = 0x00, - [BMI160_OFFSET_EN_GYR98] = 0x00, - [BMI160_STEP_CNT_0] = 0x00, - [BMI160_STEP_CNT_1] = 0x00, - [BMI160_STEP_CONF_0] = 0x00, - [BMI160_STEP_CONF_1] = 0xf0, - [0x7c] = 0xff, /* Reserved */ - [0x7d] = 0xff, /* Reserved */ - [BMI160_CMD_REG] = 0x00, + [BMI160_CHIP_ID] = 0x00, + [0x01] = 0xff, /* Reserved */ + [BMI160_ERR_REG] = 0x00, + [BMI160_PMU_STATUS] = 0xc0, + [BMI160_MAG_X_L_G] = 0x00, + [BMI160_MAG_X_H_G] = 0x00, + [BMI160_MAG_Y_L_G] = 0x00, + [BMI160_MAG_Y_H_G] = 0x00, + [BMI160_MAG_Z_L_G] = 0x00, + [BMI160_MAG_Z_H_G] = 0x00, + [BMI160_RHALL_L_G] = 0x00, + [BMI160_RHALL_H_G] = 0x00, + [BMI160_GYR_X_L_G] = 0x00, + [BMI160_GYR_X_H_G] = 0x00, + [BMI160_GYR_Y_L_G] = 0x00, + [BMI160_GYR_Y_H_G] = 0x00, + [BMI160_GYR_Z_L_G] = 0x00, + [BMI160_GYR_Z_H_G] = 0x00, + [BMI160_ACC_X_L_G] = 0x00, + [BMI160_ACC_X_H_G] = 0x00, + [BMI160_ACC_Y_L_G] = 0x00, + [BMI160_ACC_Y_H_G] = 0x00, + [BMI160_ACC_Z_L_G] = 0x00, + [BMI160_ACC_Z_H_G] = 0x00, + [BMI160_SENSORTIME_0] = 0x00, + [BMI160_SENSORTIME_1] = 0x00, + [BMI160_SENSORTIME_2] = 0x00, + [BMI160_STATUS] = 0x01, + [BMI160_INT_STATUS_0] = 0x00, + [BMI160_INT_STATUS_1] = 0x03, + [BMI160_INT_STATUS_2] = 0x00, + [BMI160_INT_STATUS_3] = 0x00, + [BMI160_TEMPERATURE_0] = 0x00, + [BMI160_TEMPERATURE_1] = 0x00, + [BMI160_FIFO_LENGTH_0] = 0x00, + [BMI160_FIFO_LENGTH_1] = 0xf8, + [BMI160_FIFO_DATA] = 0x00, + [0x25 ... 0x3f] = 0xff, /* Reserved */ + [BMI160_ACC_CONF] = 0x00, + [BMI160_ACC_RANGE] = 0xf0, + [BMI160_GYR_CONF] = 0xc0, + [BMI160_GYR_RANGE] = 0xf8, + [BMI160_MAG_CONF] = 0xf0, + [BMI160_FIFO_DOWNS] = 0x00, + [BMI160_FIFO_CONFIG_0] = 0x00, + [BMI160_FIFO_CONFIG_1] = 0x01, + [0x48 ... 0x4a] = 0xff, /* Reserved */ + [BMI160_MAG_IF_0] = 0x01, + [BMI160_MAG_IF_1] = 0x40, + [BMI160_MAG_IF_2] = 0x00, + [BMI160_MAG_IF_3] = 0x00, + [BMI160_MAG_IF_4] = 0x00, + [BMI160_INT_EN_0] = 0x08, + [BMI160_INT_EN_1] = 0x80, + [BMI160_INT_EN_2] = 0xf0, + [BMI160_INT_OUT_CTRL] = 0x00, + [BMI160_INT_LATCH] = 0xc0, + [BMI160_INT_MAP_0] = 0x00, + [BMI160_INT_MAP_1] = 0x00, + [BMI160_INT_MAP_2] = 0x00, + [BMI160_INT_DATA_0] = 0x77, + [BMI160_INT_DATA_1] = 0x7f, + [BMI160_INT_LOW_HIGH_0] = 0x00, + [BMI160_INT_LOW_HIGH_1] = 0x00, + [BMI160_INT_LOW_HIGH_2] = 0x3c, + [BMI160_INT_LOW_HIGH_3] = 0x00, + [BMI160_INT_LOW_HIGH_4] = 0x00, + [BMI160_INT_MOTION_0] = 0x00, + [BMI160_INT_MOTION_1] = 0x00, + [BMI160_INT_MOTION_2] = 0x00, + [BMI160_INT_MOTION_3] = 0xc0, + [BMI160_INT_TAP_0] = 0x38, + [BMI160_INT_TAP_1] = 0xe0, + [BMI160_INT_ORIENT_0] = 0x00, + [BMI160_INT_ORIENT_1] = 0x00, + [BMI160_INT_FLAT_0] = 0xc0, + [BMI160_INT_FLAT_1] = 0xc8, + [BMI160_FOC_CONF] = 0x80, + [BMI160_CONF] = 0xfd, + [BMI160_IF_CONF] = 0xce, + [BMI160_PMU_TRIGGER] = 0x80, + [BMI160_SELF_TEST] = 0xe0, + [0x6e] = 0xff, /* Reserved */ + [0x6f] = 0xff, /* Reserved */ + [BMI160_NV_CONF] = 0xf0, + [BMI160_OFFSET_ACC70] = 0x00, + [BMI160_OFFSET_ACC70 + 1] = 0x00, + [BMI160_OFFSET_ACC70 + 2] = 0x00, + [BMI160_OFFSET_GYR70] = 0x00, + [BMI160_OFFSET_GYR70 + 1] = 0x00, + [BMI160_OFFSET_GYR70 + 2] = 0x00, + [BMI160_OFFSET_EN_GYR98] = 0x00, + [BMI160_STEP_CNT_0] = 0x00, + [BMI160_STEP_CNT_1] = 0x00, + [BMI160_STEP_CONF_0] = 0x00, + [BMI160_STEP_CONF_1] = 0xf0, + [0x7c] = 0xff, /* Reserved */ + [0x7d] = 0xff, /* Reserved */ + [BMI160_CMD_REG] = 0x00, }; /** @@ -187,90 +187,90 @@ static void bmi160_emul_reset(uint8_t *regs, struct i2c_emul *emul) bool tag_time; bool header; - regs[BMI160_CHIP_ID] = 0xd1; - regs[BMI160_ERR_REG] = 0x00; - regs[BMI160_PMU_STATUS] = 0x00; - regs[BMI160_MAG_X_L_G] = 0x00; - regs[BMI160_MAG_X_H_G] = 0x00; - regs[BMI160_MAG_Y_L_G] = 0x00; - regs[BMI160_MAG_Y_H_G] = 0x00; - regs[BMI160_MAG_Z_L_G] = 0x00; - regs[BMI160_MAG_Z_H_G] = 0x00; - regs[BMI160_RHALL_L_G] = 0x00; - regs[BMI160_RHALL_H_G] = 0x00; - regs[BMI160_GYR_X_L_G] = 0x00; - regs[BMI160_GYR_X_H_G] = 0x00; - regs[BMI160_GYR_Y_L_G] = 0x00; - regs[BMI160_GYR_Y_H_G] = 0x00; - regs[BMI160_GYR_Z_L_G] = 0x00; - regs[BMI160_GYR_Z_H_G] = 0x00; - regs[BMI160_ACC_X_L_G] = 0x00; - regs[BMI160_ACC_X_H_G] = 0x00; - regs[BMI160_ACC_Y_L_G] = 0x00; - regs[BMI160_ACC_Y_H_G] = 0x00; - regs[BMI160_ACC_Z_L_G] = 0x00; - regs[BMI160_ACC_Z_H_G] = 0x00; - regs[BMI160_SENSORTIME_0] = 0x00; - regs[BMI160_SENSORTIME_1] = 0x00; - regs[BMI160_SENSORTIME_2] = 0x00; - regs[BMI160_STATUS] = 0x01; - regs[BMI160_INT_STATUS_0] = 0x00; - regs[BMI160_INT_STATUS_1] = 0x00; - regs[BMI160_INT_STATUS_2] = 0x00; - regs[BMI160_INT_STATUS_3] = 0x00; - regs[BMI160_TEMPERATURE_0] = 0x00; - regs[BMI160_TEMPERATURE_1] = 0x00; - regs[BMI160_FIFO_LENGTH_0] = 0x00; - regs[BMI160_FIFO_LENGTH_1] = 0x00; - regs[BMI160_FIFO_DATA] = 0x00; - regs[BMI160_ACC_CONF] = 0x28; - regs[BMI160_ACC_RANGE] = 0x03; - regs[BMI160_GYR_CONF] = 0x28; - regs[BMI160_GYR_RANGE] = 0x00; - regs[BMI160_MAG_CONF] = 0x0b; - regs[BMI160_FIFO_DOWNS] = 0x88; - regs[BMI160_FIFO_CONFIG_0] = 0x80; - regs[BMI160_FIFO_CONFIG_1] = 0x10; - regs[BMI160_MAG_IF_0] = 0x20; - regs[BMI160_MAG_IF_1] = 0x80; - regs[BMI160_MAG_IF_2] = 0x42; - regs[BMI160_MAG_IF_3] = 0x4c; - regs[BMI160_MAG_IF_4] = 0x00; - regs[BMI160_INT_EN_0] = 0x00; - regs[BMI160_INT_EN_1] = 0x00; - regs[BMI160_INT_EN_2] = 0x00; - regs[BMI160_INT_OUT_CTRL] = 0x00; - regs[BMI160_INT_LATCH] = 0x00; - regs[BMI160_INT_MAP_0] = 0x00; - regs[BMI160_INT_MAP_1] = 0x00; - regs[BMI160_INT_MAP_2] = 0x00; - regs[BMI160_INT_DATA_0] = 0x00; - regs[BMI160_INT_DATA_1] = 0x00; - regs[BMI160_INT_LOW_HIGH_0] = 0x07; - regs[BMI160_INT_LOW_HIGH_1] = 0x30; - regs[BMI160_INT_LOW_HIGH_2] = 0x81; - regs[BMI160_INT_LOW_HIGH_3] = 0xdb; - regs[BMI160_INT_LOW_HIGH_4] = 0xc0; - regs[BMI160_INT_MOTION_0] = 0x00; - regs[BMI160_INT_MOTION_1] = 0x14; - regs[BMI160_INT_MOTION_2] = 0x14; - regs[BMI160_INT_MOTION_3] = 0x24; - regs[BMI160_INT_TAP_0] = 0x04; - regs[BMI160_INT_TAP_1] = 0xda; - regs[BMI160_INT_ORIENT_0] = 0x18; - regs[BMI160_INT_ORIENT_1] = 0x48; - regs[BMI160_INT_FLAT_0] = 0x08; - regs[BMI160_INT_FLAT_1] = 0x11; - regs[BMI160_FOC_CONF] = 0x00; - regs[BMI160_CONF] = 0x00; - regs[BMI160_IF_CONF] = 0x00; - regs[BMI160_PMU_TRIGGER] = 0x00; - regs[BMI160_SELF_TEST] = 0x00; - regs[BMI160_STEP_CNT_0] = 0x00; - regs[BMI160_STEP_CNT_1] = 0x00; - regs[BMI160_STEP_CONF_0] = 0x00; - regs[BMI160_STEP_CONF_1] = 0x15; - regs[BMI160_CMD_REG] = 0x03; + regs[BMI160_CHIP_ID] = 0xd1; + regs[BMI160_ERR_REG] = 0x00; + regs[BMI160_PMU_STATUS] = 0x00; + regs[BMI160_MAG_X_L_G] = 0x00; + regs[BMI160_MAG_X_H_G] = 0x00; + regs[BMI160_MAG_Y_L_G] = 0x00; + regs[BMI160_MAG_Y_H_G] = 0x00; + regs[BMI160_MAG_Z_L_G] = 0x00; + regs[BMI160_MAG_Z_H_G] = 0x00; + regs[BMI160_RHALL_L_G] = 0x00; + regs[BMI160_RHALL_H_G] = 0x00; + regs[BMI160_GYR_X_L_G] = 0x00; + regs[BMI160_GYR_X_H_G] = 0x00; + regs[BMI160_GYR_Y_L_G] = 0x00; + regs[BMI160_GYR_Y_H_G] = 0x00; + regs[BMI160_GYR_Z_L_G] = 0x00; + regs[BMI160_GYR_Z_H_G] = 0x00; + regs[BMI160_ACC_X_L_G] = 0x00; + regs[BMI160_ACC_X_H_G] = 0x00; + regs[BMI160_ACC_Y_L_G] = 0x00; + regs[BMI160_ACC_Y_H_G] = 0x00; + regs[BMI160_ACC_Z_L_G] = 0x00; + regs[BMI160_ACC_Z_H_G] = 0x00; + regs[BMI160_SENSORTIME_0] = 0x00; + regs[BMI160_SENSORTIME_1] = 0x00; + regs[BMI160_SENSORTIME_2] = 0x00; + regs[BMI160_STATUS] = 0x01; + regs[BMI160_INT_STATUS_0] = 0x00; + regs[BMI160_INT_STATUS_1] = 0x00; + regs[BMI160_INT_STATUS_2] = 0x00; + regs[BMI160_INT_STATUS_3] = 0x00; + regs[BMI160_TEMPERATURE_0] = 0x00; + regs[BMI160_TEMPERATURE_1] = 0x00; + regs[BMI160_FIFO_LENGTH_0] = 0x00; + regs[BMI160_FIFO_LENGTH_1] = 0x00; + regs[BMI160_FIFO_DATA] = 0x00; + regs[BMI160_ACC_CONF] = 0x28; + regs[BMI160_ACC_RANGE] = 0x03; + regs[BMI160_GYR_CONF] = 0x28; + regs[BMI160_GYR_RANGE] = 0x00; + regs[BMI160_MAG_CONF] = 0x0b; + regs[BMI160_FIFO_DOWNS] = 0x88; + regs[BMI160_FIFO_CONFIG_0] = 0x80; + regs[BMI160_FIFO_CONFIG_1] = 0x10; + regs[BMI160_MAG_IF_0] = 0x20; + regs[BMI160_MAG_IF_1] = 0x80; + regs[BMI160_MAG_IF_2] = 0x42; + regs[BMI160_MAG_IF_3] = 0x4c; + regs[BMI160_MAG_IF_4] = 0x00; + regs[BMI160_INT_EN_0] = 0x00; + regs[BMI160_INT_EN_1] = 0x00; + regs[BMI160_INT_EN_2] = 0x00; + regs[BMI160_INT_OUT_CTRL] = 0x00; + regs[BMI160_INT_LATCH] = 0x00; + regs[BMI160_INT_MAP_0] = 0x00; + regs[BMI160_INT_MAP_1] = 0x00; + regs[BMI160_INT_MAP_2] = 0x00; + regs[BMI160_INT_DATA_0] = 0x00; + regs[BMI160_INT_DATA_1] = 0x00; + regs[BMI160_INT_LOW_HIGH_0] = 0x07; + regs[BMI160_INT_LOW_HIGH_1] = 0x30; + regs[BMI160_INT_LOW_HIGH_2] = 0x81; + regs[BMI160_INT_LOW_HIGH_3] = 0xdb; + regs[BMI160_INT_LOW_HIGH_4] = 0xc0; + regs[BMI160_INT_MOTION_0] = 0x00; + regs[BMI160_INT_MOTION_1] = 0x14; + regs[BMI160_INT_MOTION_2] = 0x14; + regs[BMI160_INT_MOTION_3] = 0x24; + regs[BMI160_INT_TAP_0] = 0x04; + regs[BMI160_INT_TAP_1] = 0xda; + regs[BMI160_INT_ORIENT_0] = 0x18; + regs[BMI160_INT_ORIENT_1] = 0x48; + regs[BMI160_INT_FLAT_0] = 0x08; + regs[BMI160_INT_FLAT_1] = 0x11; + regs[BMI160_FOC_CONF] = 0x00; + regs[BMI160_CONF] = 0x00; + regs[BMI160_IF_CONF] = 0x00; + regs[BMI160_PMU_TRIGGER] = 0x00; + regs[BMI160_SELF_TEST] = 0x00; + regs[BMI160_STEP_CNT_0] = 0x00; + regs[BMI160_STEP_CNT_1] = 0x00; + regs[BMI160_STEP_CONF_0] = 0x00; + regs[BMI160_STEP_CONF_1] = 0x15; + regs[BMI160_CMD_REG] = 0x03; /* Call generic reset */ tag_time = regs[BMI160_FIFO_CONFIG_1] & BMI160_FIFO_TAG_TIME_EN; @@ -714,8 +714,8 @@ static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul, bmi_emul_state_to_reg(emul, acc_shift, gyr_shift, BMI160_ACC_X_L_G, BMI160_GYR_X_L_G, - BMI160_SENSORTIME_0, - acc_off_en, gyr_off_en); + BMI160_SENSORTIME_0, acc_off_en, + gyr_off_en); } break; case BMI160_FIFO_LENGTH_0: @@ -739,14 +739,11 @@ static int bmi160_emul_handle_read(uint8_t *regs, struct i2c_emul *emul, } /** Registers backed in NVM by BMI160 */ -const int bmi160_nvm_reg[] = {BMI160_NV_CONF, - BMI160_OFFSET_ACC70, - BMI160_OFFSET_ACC70 + 1, - BMI160_OFFSET_ACC70 + 2, - BMI160_OFFSET_GYR70, - BMI160_OFFSET_GYR70 + 1, - BMI160_OFFSET_GYR70 + 2, - BMI160_OFFSET_EN_GYR98}; +const int bmi160_nvm_reg[] = { + BMI160_NV_CONF, BMI160_OFFSET_ACC70, BMI160_OFFSET_ACC70 + 1, + BMI160_OFFSET_ACC70 + 2, BMI160_OFFSET_GYR70, BMI160_OFFSET_GYR70 + 1, + BMI160_OFFSET_GYR70 + 2, BMI160_OFFSET_EN_GYR98 +}; /** Confguration of BMI160 */ struct bmi_emul_type_data bmi160_emul = { -- cgit v1.2.1 From b681aa2ac7820ba84e9ecd5c50638bb7df685a82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:27 -0600 Subject: board/kindred/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9b5b47c943e42d8bb3dbad4f9e4da2e0c75cb36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728547 Reviewed-by: Jeremy Bettis --- board/kindred/board.h | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/board/kindred/board.h b/board/kindred/board.h index f85742d27e..d3150078ea 100644 --- a/board/kindred/board.h +++ b/board/kindred/board.h @@ -12,7 +12,7 @@ #include "baseboard.h" #define CONFIG_POWER_BUTTON -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2 #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_LED_COMMON @@ -111,16 +111,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -131,9 +131,9 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC3 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC3 */ ADC_CH_COUNT }; @@ -144,11 +144,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From 8d06f607b9cfad14317406282b55e26357e7ae88 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:40 -0600 Subject: baseboard/zork/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5191cdeccbd1ce783022e3941bddc8495357fa99 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727958 Reviewed-by: Jeremy Bettis --- baseboard/zork/cbi_ssfc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c index 1078ec6486..f5b997d803 100644 --- a/baseboard/zork/cbi_ssfc.c +++ b/baseboard/zork/cbi_ssfc.c @@ -38,11 +38,10 @@ enum ec_ssfc_spkr_auto_mode get_cbi_ssfc_spkr_auto_mode(void) enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void) { return (cached_ssfc & SSFC_EDP_PHY_ALT_TUNING_MASK) >> - SSFC_EDP_PHY_ALT_TUNING_OFFSET; + SSFC_EDP_PHY_ALT_TUNING_OFFSET; } enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void) { - return (cached_ssfc & SSFC_C1_MUX_MASK) >> - SSFC_C1_MUX_OFFSET; + return (cached_ssfc & SSFC_C1_MUX_MASK) >> SSFC_C1_MUX_OFFSET; } -- cgit v1.2.1 From 8fa509fedb6bad4643fce269bd9e58ef1de9f6f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:34 -0600 Subject: common/audio_codec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5adfe7f0b323abe281633d8b9628ddd5d3119ec2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729564 Reviewed-by: Jeremy Bettis --- common/audio_codec.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/common/audio_codec.c b/common/audio_codec.c index 3f7203ad15..719adb5d08 100644 --- a/common/audio_codec.c +++ b/common/audio_codec.c @@ -9,15 +9,14 @@ #include "host_command.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) -static const uint32_t capabilities = - 0 +static const uint32_t capabilities = 0 #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM - | BIT(EC_CODEC_CAP_WOV_AUDIO_SHM) + | BIT(EC_CODEC_CAP_WOV_AUDIO_SHM) #endif #ifdef CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM - | BIT(EC_CODEC_CAP_WOV_LANG_SHM) + | BIT(EC_CODEC_CAP_WOV_LANG_SHM) #endif ; @@ -122,8 +121,8 @@ int audio_codec_capable(uint8_t cap) return capabilities & BIT(cap); } -int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, - uintptr_t *addr, uint32_t len, uint8_t type) +int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, uintptr_t *addr, + uint32_t len, uint8_t type) { if (shm_id >= EC_CODEC_SHM_ID_LAST) return EC_ERROR_INVAL; @@ -140,8 +139,8 @@ int audio_codec_register_shm(uint8_t shm_id, uint8_t cap, return EC_SUCCESS; } -__attribute__((weak)) -int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, uintptr_t *ec_addr) +__attribute__((weak)) int audio_codec_memmap_ap_to_ec(uintptr_t ap_addr, + uintptr_t *ec_addr) { return EC_ERROR_UNIMPLEMENTED; } -- cgit v1.2.1 From d70cb7c8aeba56514ff084c9e3552acac508ad78 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:40 -0600 Subject: baseboard/kalista/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d0f9745fe478c58a03bced13e04fd5e0040ed81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727912 Reviewed-by: Jeremy Bettis --- baseboard/kalista/usb_pd_pdo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/baseboard/kalista/usb_pd_pdo.c b/baseboard/kalista/usb_pd_pdo.c index 0addbcc51c..30b6c30a7b 100644 --- a/baseboard/kalista/usb_pd_pdo.c +++ b/baseboard/kalista/usb_pd_pdo.c @@ -7,9 +7,8 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS (PDO_FIXED_UNCONSTRAINED | \ - PDO_FIXED_DATA_SWAP | \ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_UNCONSTRAINED | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), -- cgit v1.2.1 From a64accc7e2116e70cabb72cf30d64c444f1820e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:25 -0600 Subject: board/bobba/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9647bfe5b9d83373696ffca14306e07b94d4373b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728062 Reviewed-by: Jeremy Bettis --- board/bobba/led.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/board/bobba/led.c b/board/bobba/led.c index d247ad0128..bf987d322a 100644 --- a/board/bobba/led.c +++ b/board/bobba/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100; /* Bobba: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From a6e49676204857ec058c32ea8ff2703d6cd74bff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:10 -0600 Subject: chip/stm32/config-stm32l552xe.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12e82c6905a3b2b520fd27dbf21595643bede41f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729485 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l552xe.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/chip/stm32/config-stm32l552xe.h b/chip/stm32/config-stm32l552xe.h index 1b9c34c4aa..346da9320a 100644 --- a/chip/stm32/config-stm32l552xe.h +++ b/chip/stm32/config-stm32l552xe.h @@ -4,36 +4,36 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 kB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 109 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x4000D800 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x4000D800 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Number of DMA channels supported (8 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 16 /* DFU Address */ -#define STM32_DFU_BASE 0x0bf90000 +#define STM32_DFU_BASE 0x0bf90000 -- cgit v1.2.1 From a37b8fa0738f6355d7355a04bf9e1fadf379cdb0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:41 -0600 Subject: board/ghost/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I068e680b52f8f783b3a0f0371811d2e9159aa0c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728403 Reviewed-by: Jeremy Bettis --- board/ghost/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/ghost/charger.c b/board/ghost/charger.c index 6e14119a77..ad47ee74bc 100644 --- a/board/ghost/charger.c +++ b/board/ghost/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) #ifndef CONFIG_ZEPHYR /* Charger Chip Configuration */ @@ -86,7 +85,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 83de023619b605d7de9e1d5ab38831ecfc815ee5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:33 -0600 Subject: board/agah/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6116e28ed0ad2aaada18a147491bb66d6b6664fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727973 Reviewed-by: Jeremy Bettis --- board/agah/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/agah/led.c b/board/agah/led.c index 12a7c3e09f..1a979ddd8d 100644 --- a/board/agah/led.c +++ b/board/agah/led.c @@ -30,13 +30,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. Cap at 50% to save power. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, White */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 50 }, - [EC_LED_COLOR_AMBER] = { 50, 0 }, + /* Amber, White */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 50 }, [EC_LED_COLOR_AMBER] = { 50, 0 }, }; /* Two logical LEDs with amber and white channels. */ -- cgit v1.2.1 From c24b1166c25b73cc3a5aff56b7a5861f6dce8121 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:32 -0600 Subject: board/lazor/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I66ff908093c1d682f71952b32a3859406b863adc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728632 Reviewed-by: Jeremy Bettis --- board/lazor/usbc_config.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/board/lazor/usbc_config.c b/board/lazor/usbc_config.c index 59951223ec..fdf68b44de 100644 --- a/board/lazor/usbc_config.c +++ b/board/lazor/usbc_config.c @@ -27,8 +27,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -149,16 +149,12 @@ void tcpc_alert_event(enum gpio_signal signal) /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -271,7 +267,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -316,8 +312,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -345,7 +340,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -369,23 +363,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From 800271a85fb123d50629636e8258f95f746f995a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:33 -0600 Subject: driver/charger/bq24715.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I58de10cc7a1102c0834ffd75119c0b38abc6de09 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729957 Reviewed-by: Jeremy Bettis --- driver/charger/bq24715.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/driver/charger/bq24715.c b/driver/charger/bq24715.c index d2eb0e432a..3420d33c3e 100644 --- a/driver/charger/bq24715.c +++ b/driver/charger/bq24715.c @@ -16,37 +16,35 @@ /* Sense resistor configurations and macros */ #define DEFAULT_SENSE_RESISTOR 10 #define R_SNS CONFIG_CHARGER_SENSE_RESISTOR -#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC -#define REG_TO_CURRENT(REG, RS) ((REG) * DEFAULT_SENSE_RESISTOR / (RS)) +#define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC +#define REG_TO_CURRENT(REG, RS) ((REG)*DEFAULT_SENSE_RESISTOR / (RS)) #define CURRENT_TO_REG(CUR, RS) ((CUR) * (RS) / DEFAULT_SENSE_RESISTOR) /* Note: it is assumed that the sense resistors are 10mOhm. */ static const struct charger_info bq24715_charger_info = { - .name = "bq24715", - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = "bq24715", + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS), - .current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS), + .current_max = REG_TO_CURRENT(CHARGE_I_MAX, R_SNS), + .current_min = REG_TO_CURRENT(CHARGE_I_MIN, R_SNS), .current_step = REG_TO_CURRENT(CHARGE_I_STEP, R_SNS), - .input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC), - .input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC), + .input_current_max = REG_TO_CURRENT(INPUT_I_MAX, R_AC), + .input_current_min = REG_TO_CURRENT(INPUT_I_MIN, R_AC), .input_current_step = REG_TO_CURRENT(INPUT_I_STEP, R_AC), }; static inline enum ec_error_list sbc_read(int chgnum, int cmd, int *param) { return i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - cmd, param); + chg_chips[chgnum].i2c_addr_flags, cmd, param); } static inline enum ec_error_list sbc_write(int chgnum, int cmd, int param) { return i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - cmd, param); + chg_chips[chgnum].i2c_addr_flags, cmd, param); } static enum ec_error_list bq24715_set_input_current_limit(int chgnum, -- cgit v1.2.1 From ce32de7909f2660f779608d8e45a59662abc1b7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:49 -0600 Subject: include/driver/accelgyro_bmi160.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia320bb93a4e459f30501f50316284afbb5c36832 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730247 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi160.h | 607 +++++++++++++++++++------------------- 1 file changed, 303 insertions(+), 304 deletions(-) diff --git a/include/driver/accelgyro_bmi160.h b/include/driver/accelgyro_bmi160.h index bd5637c2ba..6bb676fde3 100644 --- a/include/driver/accelgyro_bmi160.h +++ b/include/driver/accelgyro_bmi160.h @@ -12,253 +12,251 @@ #include "driver/accelgyro_bmi160_public.h" #include "mag_bmm150.h" -#define BMI160_CHIP_ID 0x00 -#define BMI160_CHIP_ID_MAJOR 0xd1 -#define BMI168_CHIP_ID_MAJOR 0xd2 - -#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 -#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 -#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 - - -#define BMI160_ERR_REG 0x02 -#define BMI160_PMU_STATUS 0x03 -#define BMI160_PMU_MAG_OFFSET 0 -#define BMI160_PMU_GYR_OFFSET 2 -#define BMI160_PMU_ACC_OFFSET 4 +#define BMI160_CHIP_ID 0x00 +#define BMI160_CHIP_ID_MAJOR 0xd1 +#define BMI168_CHIP_ID_MAJOR 0xd2 + +#define BMI160_SPEC_ACC_STARTUP_TIME_MS 10 +#define BMI160_SPEC_GYR_STARTUP_TIME_MS 80 +#define BMI160_SPEC_MAG_STARTUP_TIME_MS 60 + +#define BMI160_ERR_REG 0x02 +#define BMI160_PMU_STATUS 0x03 +#define BMI160_PMU_MAG_OFFSET 0 +#define BMI160_PMU_GYR_OFFSET 2 +#define BMI160_PMU_ACC_OFFSET 4 #define BMI160_PMU_SENSOR_STATUS(_sensor_type, _val) \ (((_val) >> (4 - 2 * (_sensor_type))) & 0x3) -#define BMI160_PMU_SUSPEND 0 -#define BMI160_PMU_NORMAL 1 -#define BMI160_PMU_LOW_POWER 2 -#define BMI160_PMU_FAST_STARTUP 3 - -#define BMI160_MAG_X_L_G 0x04 -#define BMI160_MAG_X_H_G 0x05 -#define BMI160_MAG_Y_L_G 0x06 -#define BMI160_MAG_Y_H_G 0x07 -#define BMI160_MAG_Z_L_G 0x08 -#define BMI160_MAG_Z_H_G 0x09 -#define BMI160_RHALL_L_G 0x0a -#define BMI160_RHALL_H_G 0x0b -#define BMI160_GYR_X_L_G 0x0c -#define BMI160_GYR_X_H_G 0x0d -#define BMI160_GYR_Y_L_G 0x0e -#define BMI160_GYR_Y_H_G 0x0f -#define BMI160_GYR_Z_L_G 0x10 -#define BMI160_GYR_Z_H_G 0x11 -#define BMI160_ACC_X_L_G 0x12 -#define BMI160_ACC_X_H_G 0x13 -#define BMI160_ACC_Y_L_G 0x14 -#define BMI160_ACC_Y_H_G 0x15 -#define BMI160_ACC_Z_L_G 0x16 -#define BMI160_ACC_Z_H_G 0x17 - -#define BMI160_SENSORTIME_0 0x18 -#define BMI160_SENSORTIME_1 0x19 -#define BMI160_SENSORTIME_2 0x1a - -#define BMI160_STATUS 0x1b -#define BMI160_POR_DETECTED BIT(0) -#define BMI160_GYR_SLF_TST BIT(1) -#define BMI160_MAG_MAN_OP BIT(2) -#define BMI160_FOC_RDY BIT(3) -#define BMI160_NVM_RDY BIT(4) -#define BMI160_DRDY_MAG BIT(5) -#define BMI160_DRDY_GYR BIT(6) -#define BMI160_DRDY_ACC BIT(7) -#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) +#define BMI160_PMU_SUSPEND 0 +#define BMI160_PMU_NORMAL 1 +#define BMI160_PMU_LOW_POWER 2 +#define BMI160_PMU_FAST_STARTUP 3 + +#define BMI160_MAG_X_L_G 0x04 +#define BMI160_MAG_X_H_G 0x05 +#define BMI160_MAG_Y_L_G 0x06 +#define BMI160_MAG_Y_H_G 0x07 +#define BMI160_MAG_Z_L_G 0x08 +#define BMI160_MAG_Z_H_G 0x09 +#define BMI160_RHALL_L_G 0x0a +#define BMI160_RHALL_H_G 0x0b +#define BMI160_GYR_X_L_G 0x0c +#define BMI160_GYR_X_H_G 0x0d +#define BMI160_GYR_Y_L_G 0x0e +#define BMI160_GYR_Y_H_G 0x0f +#define BMI160_GYR_Z_L_G 0x10 +#define BMI160_GYR_Z_H_G 0x11 +#define BMI160_ACC_X_L_G 0x12 +#define BMI160_ACC_X_H_G 0x13 +#define BMI160_ACC_Y_L_G 0x14 +#define BMI160_ACC_Y_H_G 0x15 +#define BMI160_ACC_Z_L_G 0x16 +#define BMI160_ACC_Z_H_G 0x17 + +#define BMI160_SENSORTIME_0 0x18 +#define BMI160_SENSORTIME_1 0x19 +#define BMI160_SENSORTIME_2 0x1a + +#define BMI160_STATUS 0x1b +#define BMI160_POR_DETECTED BIT(0) +#define BMI160_GYR_SLF_TST BIT(1) +#define BMI160_MAG_MAN_OP BIT(2) +#define BMI160_FOC_RDY BIT(3) +#define BMI160_NVM_RDY BIT(4) +#define BMI160_DRDY_MAG BIT(5) +#define BMI160_DRDY_GYR BIT(6) +#define BMI160_DRDY_ACC BIT(7) +#define BMI160_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI160_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) /* first 2 bytes are the interrupt reasons, next 2 some qualifier */ -#define BMI160_INT_STATUS_0 0x1c -#define BMI160_STEP_INT BIT(0) -#define BMI160_SIGMOT_INT BIT(1) -#define BMI160_ANYM_INT BIT(2) -#define BMI160_PMU_TRIGGER_INT BIT(3) -#define BMI160_D_TAP_INT BIT(4) -#define BMI160_S_TAP_INT BIT(5) -#define BMI160_ORIENT_INT BIT(6) -#define BMI160_FLAT_INT BIT(7) -#define BMI160_ORIENT_XY_MASK 0x30 -#define BMI160_ORIENT_PORTRAIT (0 << 4) -#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) -#define BMI160_ORIENT_LANDSCAPE (2 << 4) -#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) - - -#define BMI160_INT_STATUS_1 0x1d -#define BMI160_HIGHG_INT (1 << (2 + 8)) -#define BMI160_LOWG_INT (1 << (3 + 8)) -#define BMI160_DRDY_INT (1 << (4 + 8)) -#define BMI160_FFULL_INT (1 << (5 + 8)) -#define BMI160_FWM_INT (1 << (6 + 8)) -#define BMI160_NOMO_INT (1 << (7 + 8)) - -#define BMI160_INT_MASK 0xFFFF - -#define BMI160_INT_STATUS_2 0x1e -#define BMI160_INT_STATUS_3 0x1f -#define BMI160_FIRST_X (1 << (0 + 16)) -#define BMI160_FIRST_Y (1 << (1 + 16)) -#define BMI160_FIRST_Z (1 << (2 + 16)) -#define BMI160_SIGN (1 << (3 + 16)) -#define BMI160_ANYM_OFFSET 0 -#define BMI160_TAP_OFFSET 4 -#define BMI160_HIGH_OFFSET 8 +#define BMI160_INT_STATUS_0 0x1c +#define BMI160_STEP_INT BIT(0) +#define BMI160_SIGMOT_INT BIT(1) +#define BMI160_ANYM_INT BIT(2) +#define BMI160_PMU_TRIGGER_INT BIT(3) +#define BMI160_D_TAP_INT BIT(4) +#define BMI160_S_TAP_INT BIT(5) +#define BMI160_ORIENT_INT BIT(6) +#define BMI160_FLAT_INT BIT(7) +#define BMI160_ORIENT_XY_MASK 0x30 +#define BMI160_ORIENT_PORTRAIT (0 << 4) +#define BMI160_ORIENT_PORTRAIT_INVERT BIT(4) +#define BMI160_ORIENT_LANDSCAPE (2 << 4) +#define BMI160_ORIENT_LANDSCAPE_INVERT (3 << 4) + +#define BMI160_INT_STATUS_1 0x1d +#define BMI160_HIGHG_INT (1 << (2 + 8)) +#define BMI160_LOWG_INT (1 << (3 + 8)) +#define BMI160_DRDY_INT (1 << (4 + 8)) +#define BMI160_FFULL_INT (1 << (5 + 8)) +#define BMI160_FWM_INT (1 << (6 + 8)) +#define BMI160_NOMO_INT (1 << (7 + 8)) + +#define BMI160_INT_MASK 0xFFFF + +#define BMI160_INT_STATUS_2 0x1e +#define BMI160_INT_STATUS_3 0x1f +#define BMI160_FIRST_X (1 << (0 + 16)) +#define BMI160_FIRST_Y (1 << (1 + 16)) +#define BMI160_FIRST_Z (1 << (2 + 16)) +#define BMI160_SIGN (1 << (3 + 16)) +#define BMI160_ANYM_OFFSET 0 +#define BMI160_TAP_OFFSET 4 +#define BMI160_HIGH_OFFSET 8 #define BMI160_INT_INFO(_type, _data) \ -(CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) - -#define BMI160_ORIENT_Z (1 << (6 + 24)) -#define BMI160_FLAT (1 << (7 + 24)) - -#define BMI160_TEMPERATURE_0 0x20 -#define BMI160_TEMPERATURE_1 0x21 - - -#define BMI160_FIFO_LENGTH_0 0x22 -#define BMI160_FIFO_LENGTH_1 0x23 -#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) -#define BMI160_FIFO_DATA 0x24 - -#define BMI160_ACC_CONF 0x40 -#define BMI160_ACC_BW_OFFSET 4 -#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) - -#define BMI160_ACC_RANGE 0x41 -#define BMI160_GSEL_2G 0x03 -#define BMI160_GSEL_4G 0x05 -#define BMI160_GSEL_8G 0x08 -#define BMI160_GSEL_16G 0x0c - -#define BMI160_GYR_CONF 0x42 -#define BMI160_GYR_BW_OFFSET 4 -#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) - -#define BMI160_GYR_RANGE 0x43 -#define BMI160_DPS_SEL_2000 0x00 -#define BMI160_DPS_SEL_1000 0x01 -#define BMI160_DPS_SEL_500 0x02 -#define BMI160_DPS_SEL_250 0x03 -#define BMI160_DPS_SEL_125 0x04 - -#define BMI160_MAG_CONF 0x44 - -#define BMI160_FIFO_DOWNS 0x45 -#define BMI160_FIFO_CONFIG_0 0x46 -#define BMI160_FIFO_CONFIG_1 0x47 -#define BMI160_FIFO_TAG_TIME_EN BIT(1) -#define BMI160_FIFO_TAG_INT2_EN BIT(2) -#define BMI160_FIFO_TAG_INT1_EN BIT(3) -#define BMI160_FIFO_HEADER_EN BIT(4) -#define BMI160_FIFO_MAG_EN BIT(5) -#define BMI160_FIFO_ACC_EN BIT(6) -#define BMI160_FIFO_GYR_EN BIT(7) -#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) -#define BMI160_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI160_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ - BMI160_FIFO_MAG_EN)) - -#define BMI160_MAG_IF_0 0x4b + (CONCAT2(BMI160_, _data) << CONCAT3(BMI160_, _type, _OFFSET)) + +#define BMI160_ORIENT_Z (1 << (6 + 24)) +#define BMI160_FLAT (1 << (7 + 24)) + +#define BMI160_TEMPERATURE_0 0x20 +#define BMI160_TEMPERATURE_1 0x21 + +#define BMI160_FIFO_LENGTH_0 0x22 +#define BMI160_FIFO_LENGTH_1 0x23 +#define BMI160_FIFO_LENGTH_MASK (BIT(11) - 1) +#define BMI160_FIFO_DATA 0x24 + +#define BMI160_ACC_CONF 0x40 +#define BMI160_ACC_BW_OFFSET 4 +#define BMI160_ACC_BW_MASK (0x7 << BMI160_ACC_BW_OFFSET) + +#define BMI160_ACC_RANGE 0x41 +#define BMI160_GSEL_2G 0x03 +#define BMI160_GSEL_4G 0x05 +#define BMI160_GSEL_8G 0x08 +#define BMI160_GSEL_16G 0x0c + +#define BMI160_GYR_CONF 0x42 +#define BMI160_GYR_BW_OFFSET 4 +#define BMI160_GYR_BW_MASK (0x3 << BMI160_GYR_BW_OFFSET) + +#define BMI160_GYR_RANGE 0x43 +#define BMI160_DPS_SEL_2000 0x00 +#define BMI160_DPS_SEL_1000 0x01 +#define BMI160_DPS_SEL_500 0x02 +#define BMI160_DPS_SEL_250 0x03 +#define BMI160_DPS_SEL_125 0x04 + +#define BMI160_MAG_CONF 0x44 + +#define BMI160_FIFO_DOWNS 0x45 +#define BMI160_FIFO_CONFIG_0 0x46 +#define BMI160_FIFO_CONFIG_1 0x47 +#define BMI160_FIFO_TAG_TIME_EN BIT(1) +#define BMI160_FIFO_TAG_INT2_EN BIT(2) +#define BMI160_FIFO_TAG_INT1_EN BIT(3) +#define BMI160_FIFO_HEADER_EN BIT(4) +#define BMI160_FIFO_MAG_EN BIT(5) +#define BMI160_FIFO_ACC_EN BIT(6) +#define BMI160_FIFO_GYR_EN BIT(7) +#define BMI160_FIFO_TARG_INT(_i) CONCAT3(BMI160_FIFO_TAG_INT, _i, _EN) +#define BMI160_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI160_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI160_FIFO_GYR_EN : \ + BMI160_FIFO_MAG_EN)) + +#define BMI160_MAG_IF_0 0x4b #define BMI160_MAG_I2C_ADDRESS BMI160_MAG_IF_0 -#define BMI160_MAG_IF_1 0x4c +#define BMI160_MAG_IF_1 0x4c #define BMI160_MAG_I2C_CONTROL BMI160_MAG_IF_1 #define BMI160_MAG_READ_BURST_MASK 3 -#define BMI160_MAG_READ_BURST_1 0 -#define BMI160_MAG_READ_BURST_2 1 -#define BMI160_MAG_READ_BURST_6 2 -#define BMI160_MAG_READ_BURST_8 3 -#define BMI160_MAG_OFFSET_OFF 3 -#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) -#define BMI160_MAG_MANUAL_EN BIT(7) - -#define BMI160_MAG_IF_2 0x4d -#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 -#define BMI160_MAG_IF_3 0x4e -#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 -#define BMI160_MAG_IF_4 0x4f -#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 -#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G - -#define BMI160_INT_EN_0 0x50 -#define BMI160_INT_ANYMO_X_EN BIT(0) -#define BMI160_INT_ANYMO_Y_EN BIT(1) -#define BMI160_INT_ANYMO_Z_EN BIT(2) -#define BMI160_INT_D_TAP_EN BIT(4) -#define BMI160_INT_S_TAP_EN BIT(5) -#define BMI160_INT_ORIENT_EN BIT(6) -#define BMI160_INT_FLAT_EN BIT(7) -#define BMI160_INT_EN_1 0x51 -#define BMI160_INT_HIGHG_X_EN BIT(0) -#define BMI160_INT_HIGHG_Y_EN BIT(1) -#define BMI160_INT_HIGHG_Z_EN BIT(2) -#define BMI160_INT_LOW_EN BIT(3) -#define BMI160_INT_DRDY_EN BIT(4) -#define BMI160_INT_FFUL_EN BIT(5) -#define BMI160_INT_FWM_EN BIT(6) -#define BMI160_INT_EN_2 0x52 -#define BMI160_INT_NOMOX_EN BIT(0) -#define BMI160_INT_NOMOY_EN BIT(1) -#define BMI160_INT_NOMOZ_EN BIT(2) -#define BMI160_INT_STEP_DET_EN BIT(3) - -#define BMI160_INT_OUT_CTRL 0x53 -#define BMI160_INT_EDGE_CTRL BIT(0) -#define BMI160_INT_LVL_CTRL BIT(1) -#define BMI160_INT_OD BIT(2) -#define BMI160_INT_OUTPUT_EN BIT(3) -#define BMI160_INT1_CTRL_OFFSET 0 -#define BMI160_INT2_CTRL_OFFSET 4 +#define BMI160_MAG_READ_BURST_1 0 +#define BMI160_MAG_READ_BURST_2 1 +#define BMI160_MAG_READ_BURST_6 2 +#define BMI160_MAG_READ_BURST_8 3 +#define BMI160_MAG_OFFSET_OFF 3 +#define BMI160_MAG_OFFSET_MASK (0xf << BMI160_MAG_OFFSET_OFF) +#define BMI160_MAG_MANUAL_EN BIT(7) + +#define BMI160_MAG_IF_2 0x4d +#define BMI160_MAG_I2C_READ_ADDR BMI160_MAG_IF_2 +#define BMI160_MAG_IF_3 0x4e +#define BMI160_MAG_I2C_WRITE_ADDR BMI160_MAG_IF_3 +#define BMI160_MAG_IF_4 0x4f +#define BMI160_MAG_I2C_WRITE_DATA BMI160_MAG_IF_4 +#define BMI160_MAG_I2C_READ_DATA BMI160_MAG_X_L_G + +#define BMI160_INT_EN_0 0x50 +#define BMI160_INT_ANYMO_X_EN BIT(0) +#define BMI160_INT_ANYMO_Y_EN BIT(1) +#define BMI160_INT_ANYMO_Z_EN BIT(2) +#define BMI160_INT_D_TAP_EN BIT(4) +#define BMI160_INT_S_TAP_EN BIT(5) +#define BMI160_INT_ORIENT_EN BIT(6) +#define BMI160_INT_FLAT_EN BIT(7) +#define BMI160_INT_EN_1 0x51 +#define BMI160_INT_HIGHG_X_EN BIT(0) +#define BMI160_INT_HIGHG_Y_EN BIT(1) +#define BMI160_INT_HIGHG_Z_EN BIT(2) +#define BMI160_INT_LOW_EN BIT(3) +#define BMI160_INT_DRDY_EN BIT(4) +#define BMI160_INT_FFUL_EN BIT(5) +#define BMI160_INT_FWM_EN BIT(6) +#define BMI160_INT_EN_2 0x52 +#define BMI160_INT_NOMOX_EN BIT(0) +#define BMI160_INT_NOMOY_EN BIT(1) +#define BMI160_INT_NOMOZ_EN BIT(2) +#define BMI160_INT_STEP_DET_EN BIT(3) + +#define BMI160_INT_OUT_CTRL 0x53 +#define BMI160_INT_EDGE_CTRL BIT(0) +#define BMI160_INT_LVL_CTRL BIT(1) +#define BMI160_INT_OD BIT(2) +#define BMI160_INT_OUTPUT_EN BIT(3) +#define BMI160_INT1_CTRL_OFFSET 0 +#define BMI160_INT2_CTRL_OFFSET 4 #define BMI160_INT_CTRL(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) - -#define BMI160_INT_LATCH 0x54 -#define BMI160_INT1_INPUT_EN BIT(4) -#define BMI160_INT2_INPUT_EN BIT(5) -#define BMI160_LATCH_MASK 0xf -#define BMI160_LATCH_NONE 0 -#define BMI160_LATCH_5MS 5 -#define BMI160_LATCH_FOREVER 0xf - -#define BMI160_INT_MAP_0 0x55 -#define BMI160_INT_LOWG_STEP BIT(0) -#define BMI160_INT_HIGHG BIT(1) -#define BMI160_INT_ANYMOTION BIT(2) -#define BMI160_INT_NOMOTION BIT(3) -#define BMI160_INT_D_TAP BIT(4) -#define BMI160_INT_S_TAP BIT(5) -#define BMI160_INT_ORIENT BIT(6) -#define BMI160_INT_FLAT BIT(7) - -#define BMI160_INT_MAP_1 0x56 -#define BMI160_INT_PMU_TRIG BIT(0) -#define BMI160_INT_FFULL BIT(1) -#define BMI160_INT_FWM BIT(2) -#define BMI160_INT_DRDY BIT(3) -#define BMI160_INT1_MAP_OFFSET 4 -#define BMI160_INT2_MAP_OFFSET 0 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _CTRL_OFFSET)) + +#define BMI160_INT_LATCH 0x54 +#define BMI160_INT1_INPUT_EN BIT(4) +#define BMI160_INT2_INPUT_EN BIT(5) +#define BMI160_LATCH_MASK 0xf +#define BMI160_LATCH_NONE 0 +#define BMI160_LATCH_5MS 5 +#define BMI160_LATCH_FOREVER 0xf + +#define BMI160_INT_MAP_0 0x55 +#define BMI160_INT_LOWG_STEP BIT(0) +#define BMI160_INT_HIGHG BIT(1) +#define BMI160_INT_ANYMOTION BIT(2) +#define BMI160_INT_NOMOTION BIT(3) +#define BMI160_INT_D_TAP BIT(4) +#define BMI160_INT_S_TAP BIT(5) +#define BMI160_INT_ORIENT BIT(6) +#define BMI160_INT_FLAT BIT(7) + +#define BMI160_INT_MAP_1 0x56 +#define BMI160_INT_PMU_TRIG BIT(0) +#define BMI160_INT_FFULL BIT(1) +#define BMI160_INT_FWM BIT(2) +#define BMI160_INT_DRDY BIT(3) +#define BMI160_INT1_MAP_OFFSET 4 +#define BMI160_INT2_MAP_OFFSET 0 #define BMI160_INT_MAP(_i, _bit) \ -(CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) -#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 + (CONCAT2(BMI160_INT_, _bit) << CONCAT3(BMI160_INT, _i, _MAP_OFFSET)) +#define BMI160_INT_FIFO_MAP BMI160_INT_MAP_1 -#define BMI160_INT_MAP_2 0x57 +#define BMI160_INT_MAP_2 0x57 -#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 -#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 -#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) +#define BMI160_INT_MAP_INT_1 BMI160_INT_MAP_0 +#define BMI160_INT_MAP_INT_2 BMI160_INT_MAP_2 +#define BMI160_INT_MAP_REG(_i) CONCAT2(BMI160_INT_MAP_INT_, _i) -#define BMI160_INT_DATA_0 0x58 -#define BMI160_INT_DATA_1 0x59 +#define BMI160_INT_DATA_0 0x58 +#define BMI160_INT_DATA_1 0x59 -#define BMI160_INT_LOW_HIGH_0 0x5a -#define BMI160_INT_LOW_HIGH_1 0x5b -#define BMI160_INT_LOW_HIGH_2 0x5c -#define BMI160_INT_LOW_HIGH_3 0x5d -#define BMI160_INT_LOW_HIGH_4 0x5e +#define BMI160_INT_LOW_HIGH_0 0x5a +#define BMI160_INT_LOW_HIGH_1 0x5b +#define BMI160_INT_LOW_HIGH_2 0x5c +#define BMI160_INT_LOW_HIGH_3 0x5d +#define BMI160_INT_LOW_HIGH_4 0x5e -#define BMI160_INT_MOTION_0 0x5f -#define BMI160_INT_MOTION_1 0x60 +#define BMI160_INT_MOTION_0 0x5f +#define BMI160_INT_MOTION_1 0x60 /* * The formula is defined in 2.11.25 (any motion interrupt [1]). * @@ -268,11 +266,11 @@ * x = a * 1000 / range * 1953 */ #define BMI160_MOTION_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 1953), 0xff)) -#define BMI160_INT_MOTION_2 0x61 -#define BMI160_INT_MOTION_3 0x62 -#define BMI160_MOTION_NO_MOT_SEL BIT(0) -#define BMI160_MOTION_SIG_MOT_SEL BIT(1) + (MIN(((_mg)*1000) / ((_s)->current_range * 1953), 0xff)) +#define BMI160_INT_MOTION_2 0x61 +#define BMI160_INT_MOTION_3 0x62 +#define BMI160_MOTION_NO_MOT_SEL BIT(0) +#define BMI160_MOTION_SIG_MOT_SEL BIT(1) #define BMI160_MOTION_SKIP_OFF 2 #define BMI160_MOTION_SKIP_MASK 0x3 #define BMI160_MOTION_SKIP_TIME(_ms) \ @@ -282,74 +280,75 @@ #define BMI160_MOTION_PROOF_TIME(_ms) \ (MIN(__fls((_ms) / 250), BMI160_MOTION_PROOF_MASK)) -#define BMI160_INT_TAP_0 0x63 -#define BMI160_TAP_DUR(_s, _ms) \ +#define BMI160_INT_TAP_0 0x63 +#define BMI160_TAP_DUR(_s, _ms) \ ((_ms) <= 250 ? MAX((_ms), 50) / 50 - 1 : \ - (_ms) <= 500 ? 4 + ((_ms) - 250) / 125 : \ - (_ms) < 700 ? 6 : 7) + (_ms) <= 500 ? 4 + ((_ms)-250) / 125 : \ + (_ms) < 700 ? 6 : \ + 7) -#define BMI160_INT_TAP_1 0x64 +#define BMI160_INT_TAP_1 0x64 #define BMI160_TAP_TH(_s, _mg) \ - (MIN(((_mg) * 1000) / ((_s)->current_range * 31250), 0x1f)) + (MIN(((_mg)*1000) / ((_s)->current_range * 31250), 0x1f)) -#define BMI160_INT_ORIENT_0 0x65 +#define BMI160_INT_ORIENT_0 0x65 /* No hysterisis, theta block, int on slope > 0.2 or axis > 1.5, symmetrical */ -#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 +#define BMI160_INT_ORIENT_0_INIT_VAL 0x48 -#define BMI160_INT_ORIENT_1 0x66 +#define BMI160_INT_ORIENT_1 0x66 /* no axes remap, no int on up/down, no blocking angle */ -#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 - -#define BMI160_INT_FLAT_0 0x67 -#define BMI160_INT_FLAT_1 0x68 - -#define BMI160_FOC_CONF 0x69 -#define BMI160_FOC_GYRO_EN BIT(6) -#define BMI160_FOC_ACC_PLUS_1G 1 -#define BMI160_FOC_ACC_MINUS_1G 2 -#define BMI160_FOC_ACC_0G 3 -#define BMI160_FOC_ACC_Z_OFFSET 0 -#define BMI160_FOC_ACC_Y_OFFSET 2 -#define BMI160_FOC_ACC_X_OFFSET 4 - -#define BMI160_CONF 0x6a -#define BMI160_IF_CONF 0x6b -#define BMI160_IF_MODE_OFF 4 -#define BMI160_IF_MODE_MASK 3 +#define BMI160_INT_ORIENT_1_INIT_VAL 0x00 + +#define BMI160_INT_FLAT_0 0x67 +#define BMI160_INT_FLAT_1 0x68 + +#define BMI160_FOC_CONF 0x69 +#define BMI160_FOC_GYRO_EN BIT(6) +#define BMI160_FOC_ACC_PLUS_1G 1 +#define BMI160_FOC_ACC_MINUS_1G 2 +#define BMI160_FOC_ACC_0G 3 +#define BMI160_FOC_ACC_Z_OFFSET 0 +#define BMI160_FOC_ACC_Y_OFFSET 2 +#define BMI160_FOC_ACC_X_OFFSET 4 + +#define BMI160_CONF 0x6a +#define BMI160_IF_CONF 0x6b +#define BMI160_IF_MODE_OFF 4 +#define BMI160_IF_MODE_MASK 3 #define BMI160_IF_MODE_AUTO_OFF 0 -#define BMI160_IF_MODE_I2C_IOS 1 +#define BMI160_IF_MODE_I2C_IOS 1 #define BMI160_IF_MODE_AUTO_I2C 2 -#define BMI160_PMU_TRIGGER 0x6c -#define BMI160_SELF_TEST 0x6d +#define BMI160_PMU_TRIGGER 0x6c +#define BMI160_SELF_TEST 0x6d -#define BMI160_NV_CONF 0x70 +#define BMI160_NV_CONF 0x70 -#define BMI160_OFFSET_ACC70 0x71 -#define BMI160_OFFSET_GYR70 0x74 -#define BMI160_OFFSET_EN_GYR98 0x77 -#define BMI160_OFFSET_ACC_EN BIT(6) -#define BMI160_OFFSET_GYRO_EN BIT(7) +#define BMI160_OFFSET_ACC70 0x71 +#define BMI160_OFFSET_GYR70 0x74 +#define BMI160_OFFSET_EN_GYR98 0x77 +#define BMI160_OFFSET_ACC_EN BIT(6) +#define BMI160_OFFSET_GYRO_EN BIT(7) -#define BMI160_STEP_CNT_0 0x78 -#define BMI160_STEP_CNT_1 0x79 -#define BMI160_STEP_CONF_0 0x7a -#define BMI160_STEP_CONF_1 0x7b +#define BMI160_STEP_CNT_0 0x78 +#define BMI160_STEP_CNT_1 0x79 +#define BMI160_STEP_CONF_0 0x7a +#define BMI160_STEP_CONF_1 0x7b -#define BMI160_CMD_REG 0x7e -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_NOOP 0x00 -#define BMI160_CMD_START_FOC 0x03 +#define BMI160_CMD_REG 0x7e +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_NOOP 0x00 +#define BMI160_CMD_START_FOC 0x03 #define BMI160_CMD_ACC_MODE_OFFSET 0x10 -#define BMI160_CMD_ACC_MODE_SUSP 0x10 +#define BMI160_CMD_ACC_MODE_SUSP 0x10 #define BMI160_CMD_ACC_MODE_NORMAL 0x11 #define BMI160_CMD_ACC_MODE_LOWPOWER 0x12 -#define BMI160_CMD_GYR_MODE_SUSP 0x14 +#define BMI160_CMD_GYR_MODE_SUSP 0x14 #define BMI160_CMD_GYR_MODE_NORMAL 0x15 #define BMI160_CMD_GYR_MODE_FAST_STARTUP 0x17 -#define BMI160_CMD_MAG_MODE_SUSP 0x18 +#define BMI160_CMD_MAG_MODE_SUSP 0x18 #define BMI160_CMD_MAG_MODE_NORMAL 0x19 #define BMI160_CMD_MAG_MODE_LOWPOWER 0x1a #define BMI160_CMD_MODE_SUSPEND(_sensor_type) \ @@ -357,31 +356,31 @@ #define BMI160_CMD_MODE_NORMAL(_sensor_type) \ (BMI160_CMD_ACC_MODE_OFFSET | (_sensor_type) << 2 | BMI160_PMU_NORMAL) -#define BMI160_CMD_FIFO_FLUSH 0xb0 -#define BMI160_CMD_INT_RESET 0xb1 -#define BMI160_CMD_SOFT_RESET 0xb6 -#define BMI160_CMD_EXT_MODE_EN_B0 0x37 -#define BMI160_CMD_EXT_MODE_EN_B1 0x9a -#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 +#define BMI160_CMD_FIFO_FLUSH 0xb0 +#define BMI160_CMD_INT_RESET 0xb1 +#define BMI160_CMD_SOFT_RESET 0xb6 +#define BMI160_CMD_EXT_MODE_EN_B0 0x37 +#define BMI160_CMD_EXT_MODE_EN_B1 0x9a +#define BMI160_CMD_EXT_MODE_EN_B2 0xc0 -#define BMI160_CMD_EXT_MODE_ADDR 0x7f -#define BMI160_CMD_PAGING_EN BIT(7) -#define BMI160_CMD_TARGET_PAGE BIT(4) +#define BMI160_CMD_EXT_MODE_ADDR 0x7f +#define BMI160_CMD_PAGING_EN BIT(7) +#define BMI160_CMD_TARGET_PAGE BIT(4) #define BMI160_COM_C_TRIM_ADDR 0x85 -#define BMI160_COM_C_TRIM (3 << 4) +#define BMI160_COM_C_TRIM (3 << 4) -#define BMI160_CMD_TGT_PAGE 0 -#define BMI160_CMD_TGT_PAGE_COM 1 -#define BMI160_CMD_TGT_PAGE_ACC 2 -#define BMI160_CMD_TGT_PAGE_GYR 3 +#define BMI160_CMD_TGT_PAGE 0 +#define BMI160_CMD_TGT_PAGE_COM 1 +#define BMI160_CMD_TGT_PAGE_ACC 2 +#define BMI160_CMD_TGT_PAGE_GYR 3 -#define BMI160_FF_FRAME_LEN_TS 4 -#define BMI160_FF_DATA_LEN_ACC 6 -#define BMI160_FF_DATA_LEN_GYR 6 -#define BMI160_FF_DATA_LEN_MAG 8 +#define BMI160_FF_FRAME_LEN_TS 4 +#define BMI160_FF_DATA_LEN_ACC 6 +#define BMI160_FF_DATA_LEN_GYR 6 +#define BMI160_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100 Hz accelerometer, units: ug */ -#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 +#define BMI160_ACCEL_RMS_NOISE_100HZ 1300 /* Functions to access the secondary device through the accel/gyro. */ int bmi160_sec_raw_read8(const int port, const uint16_t addr_flags, @@ -404,6 +403,6 @@ int bmi160_sec_raw_write8(const int port, const uint16_t addr_flags, #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI160_H */ -- cgit v1.2.1 From c41cba66dde3f347335faa69cedb25c5e3213c74 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:45 -0600 Subject: zephyr/projects/nissa/src/common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I02fa4629fac7edb346dcf0b35c2475aacfcce321 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730783 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/nissa/src/common.c b/zephyr/projects/nissa/src/common.c index e1e7aaf7e9..c752b96295 100644 --- a/zephyr/projects/nissa/src/common.c +++ b/zephyr/projects/nissa/src/common.c @@ -81,8 +81,8 @@ static void board_setup_init(void) */ DECLARE_HOOK(HOOK_INIT, board_setup_init, HOOK_PRIO_INIT_I2C); -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -124,7 +124,7 @@ enum nissa_sub_board_type nissa_get_sb_type(void) if (sb != NISSA_SB_UNKNOWN) return sb; - sb = NISSA_SB_NONE; /* Defaults to none */ + sb = NISSA_SB_NONE; /* Defaults to none */ ret = cros_cbi_get_fw_config(FW_SUB_BOARD, &val); if (ret != 0) { LOG_WRN("Error retrieving CBI FW_CONFIG field %d", -- cgit v1.2.1 From 4f237a4c6fdedc724b3f0300de85eac393f3cf75 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:16 -0600 Subject: board/magolor/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2f4c10ea32d2145753fa1adfba842d3d08c8466 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728649 Reviewed-by: Jeremy Bettis --- board/magolor/board.c | 165 ++++++++++++++++++++++---------------------------- 1 file changed, 73 insertions(+), 92 deletions(-) diff --git a/board/magolor/board.c b/board/magolor/board.c index 710a94f54a..f98b4ff6a8 100644 --- a/board/magolor/board.c +++ b/board/magolor/board.c @@ -52,13 +52,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) static uint8_t new_adc_key_state; @@ -165,8 +165,7 @@ static const struct ec_response_keybd_config magma_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override -uint8_t board_keyboard_row_refresh(void) +__override uint8_t board_keyboard_row_refresh(void) { if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID)) return 3; @@ -174,16 +173,15 @@ uint8_t board_keyboard_row_refresh(void) return 2; } -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_cbi_fw_config_numeric_pad()) { if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID)) return &magma_keybd; else return &magpie_keybd; - } - else { + } else { if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID)) return &magister_keybd; else @@ -198,16 +196,15 @@ __override const struct ec_response_keybd_config * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* C0 interrupt line shared by BC 1.2 and charger */ static void check_c0_line(void); @@ -245,7 +242,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -326,22 +322,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -358,8 +354,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -443,7 +439,7 @@ static void reconfigure_5v_gpio(void) gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW); } } -DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1); #endif /* BOARD_WADDLEDOO */ static void set_5v_gpio(int level) @@ -492,8 +488,8 @@ __override void board_power_5v_enable(int enable) gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } else { if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", + enable ? "en" : "dis"); if (!enable) return; @@ -503,7 +499,7 @@ __override void board_power_5v_enable(int enable) */ if (get_cbi_ssfc_usb_mux() == SSFC_USBMUX_PS8762) hook_call_deferred(&ps8762_chaddr_deferred_data, - 15 * MSEC); + 15 * MSEC); } } @@ -529,13 +525,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -599,8 +593,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -625,25 +619,18 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Matrices to rotate accelerometers into the magister reference. */ -static const mat33_fp_t lid_magister_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; - -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_magister_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* BMA253 private data */ static struct accelgyro_saved_data_t g_bma253_data; @@ -652,11 +639,9 @@ static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; #ifdef BOARD_MAGOLOR -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* ICM426 private data */ static struct icm_drv_data_t g_icm426xx_data; @@ -814,7 +799,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); static void pendetect_deferred(void) { int pen_charge_enable = !gpio_get_level(GPIO_PEN_DET_ODL) && - !chipset_in_state(CHIPSET_STATE_ANY_OFF); + !chipset_in_state(CHIPSET_STATE_ANY_OFF); if (pen_charge_enable) gpio_set_level(GPIO_EN_PP5000_PEN, 1); @@ -839,7 +824,6 @@ static void pen_charge_check(void) DECLARE_HOOK(HOOK_CHIPSET_STARTUP, pen_charge_check, HOOK_PRIO_LAST); DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, pen_charge_check, HOOK_PRIO_LAST); - /***************************************************************************** * USB-C MUX/Retimer dynamic configuration */ @@ -862,16 +846,17 @@ void board_init(void) if (get_cbi_fw_config_db() == DB_1A_HDMI) { /* Disable i2c on HDMI pins */ - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0); - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, + 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, + 0); /* Set HDMI and sub-rail enables to output */ gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, chipset_in_state(CHIPSET_STATE_ON) ? - GPIO_ODR_LOW : GPIO_ODR_HIGH); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + GPIO_ODR_LOW : + GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -881,8 +866,7 @@ void board_init(void) } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT); /* Enable C1 interrupt and check if it needs processing */ gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL); @@ -907,8 +891,8 @@ void board_init(void) ccprints("LID_ACCEL is KX022"); } else { if (system_get_board_version() >= 5) { - motion_sensors[LID_ACCEL] - .rot_standard_ref = &lid_magister_ref; + motion_sensors[LID_ACCEL].rot_standard_ref = + &lid_magister_ref; } ccprints("LID_ACCEL is BMA253"); } @@ -921,7 +905,7 @@ void board_init(void) gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); } if (get_cbi_fw_config_stylus() == STYLUS_PRESENT) { @@ -930,8 +914,7 @@ void board_init(void) pen_charge_check(); } else { gpio_disable_interrupt(GPIO_PEN_DET_ODL); - gpio_set_flags(GPIO_PEN_DET_ODL, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN); } /* Turn on 5V if the system is on, otherwise turn it off. */ @@ -944,32 +927,30 @@ void board_init(void) #ifdef BOARD_MAGOLOR /* Support Keyboard Pad */ - board_update_no_keypad_by_fwconfig(); + board_update_no_keypad_by_fwconfig(); #endif - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); void motion_interrupt(enum gpio_signal signal) { #ifdef BOARD_MAGOLOR - switch (get_cbi_ssfc_base_sensor()) { - case SSFC_SENSOR_ICM426XX: - icm426xx_interrupt(signal); - break; - case SSFC_SENSOR_BMI160: - default: - bmi160_interrupt(signal); - break; - } - #else + switch (get_cbi_ssfc_base_sensor()) { + case SSFC_SENSOR_ICM426XX: + icm426xx_interrupt(signal); + break; + case SSFC_SENSOR_BMI160: + default: bmi160_interrupt(signal); + break; + } +#else + bmi160_interrupt(signal); #endif } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -1082,7 +1063,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { + !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) -- cgit v1.2.1 From 8c2fca489854954cc011987e7d6f7d86cc6f1582 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:12 -0600 Subject: driver/usb_mux/anx3443.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa2247abac5d551ab7e57b49386a7f37d681014f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730156 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx3443.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/driver/usb_mux/anx3443.h b/driver/usb_mux/anx3443.h index a8e84d5e5e..41a4eb2c20 100644 --- a/driver/usb_mux/anx3443.h +++ b/driver/usb_mux/anx3443.h @@ -9,36 +9,36 @@ #ifndef __CROS_EC_USB_MUX_ANX3443_H #define __CROS_EC_USB_MUX_ANX3443_H -#define ANX3443_I2C_READY_DELAY (30 * MSEC) +#define ANX3443_I2C_READY_DELAY (30 * MSEC) /* I2C interface addresses */ -#define ANX3443_I2C_ADDR0_FLAGS 0x10 -#define ANX3443_I2C_ADDR1_FLAGS 0x14 -#define ANX3443_I2C_ADDR2_FLAGS 0x16 -#define ANX3443_I2C_ADDR3_FLAGS 0x11 +#define ANX3443_I2C_ADDR0_FLAGS 0x10 +#define ANX3443_I2C_ADDR1_FLAGS 0x14 +#define ANX3443_I2C_ADDR2_FLAGS 0x16 +#define ANX3443_I2C_ADDR3_FLAGS 0x11 /* This register is not documented in datasheet. */ -#define ANX3443_REG_POWER_CNTRL 0x2B -#define ANX3443_POWER_CNTRL_OFF 0xFF +#define ANX3443_REG_POWER_CNTRL 0x2B +#define ANX3443_POWER_CNTRL_OFF 0xFF -#define ANX3443_REG_USB_STATUS 0xD7 +#define ANX3443_REG_USB_STATUS 0xD7 /* status of downstream RX term */ -#define ANX3443_DN_EN_RTERM_ST BIT(7) +#define ANX3443_DN_EN_RTERM_ST BIT(7) /* status of upstream RX term */ -#define ANX3443_UP_EN_RTERM_ST BIT(6) +#define ANX3443_UP_EN_RTERM_ST BIT(6) /* Ultra low power control register */ -#define ANX3443_REG_ULTRA_LOW_POWER 0xE6 -#define ANX3443_ULTRA_LOW_POWER_EN 0x06 -#define ANX3443_ULTRA_LOW_POWER_DIS 0x00 +#define ANX3443_REG_ULTRA_LOW_POWER 0xE6 +#define ANX3443_ULTRA_LOW_POWER_EN 0x06 +#define ANX3443_ULTRA_LOW_POWER_DIS 0x00 /* Mux control register */ -#define ANX3443_REG_ULP_CFG_MODE 0xF8 -#define ANX3443_ULP_CFG_MODE_EN BIT(4) -#define ANX3443_ULP_CFG_MODE_SWAP BIT(3) -#define ANX3443_ULP_CFG_MODE_FLIP BIT(2) -#define ANX3443_ULP_CFG_MODE_DP_EN BIT(1) -#define ANX3443_ULP_CFG_MODE_USB_EN BIT(0) +#define ANX3443_REG_ULP_CFG_MODE 0xF8 +#define ANX3443_ULP_CFG_MODE_EN BIT(4) +#define ANX3443_ULP_CFG_MODE_SWAP BIT(3) +#define ANX3443_ULP_CFG_MODE_FLIP BIT(2) +#define ANX3443_ULP_CFG_MODE_DP_EN BIT(1) +#define ANX3443_ULP_CFG_MODE_USB_EN BIT(0) extern const struct usb_mux_driver anx3443_usb_mux_driver; -- cgit v1.2.1 From b31e84f13b1800091dd4a6975b78f5cce0b9ffe0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:43 -0600 Subject: board/treeya/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2dd703c845efe326a8cd6e943e1d3d56be7a91d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729022 Reviewed-by: Jeremy Bettis --- board/treeya/board.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/treeya/board.h b/board/treeya/board.h index e1bae50532..2fb817b91c 100644 --- a/board/treeya/board.h +++ b/board/treeya/board.h @@ -30,7 +30,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -61,7 +61,7 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) /* Second set of sensor drivers */ @@ -72,7 +72,6 @@ #ifndef __ASSEMBLER__ - enum battery_type { BATTERY_SMP, BATTERY_LGC, -- cgit v1.2.1 From 0320cee07f6c1b6eb2375582f21b29388dddb29e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:06 -0600 Subject: board/volmar/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ab89a28a21a10f3956ee2d027ccc65bab9e9c12 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729087 Reviewed-by: Jeremy Bettis --- board/volmar/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/volmar/led.c b/board/volmar/led.c index 7634437b0d..1174adf474 100644 --- a/board/volmar/led.c +++ b/board/volmar/led.c @@ -21,23 +21,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From b0ba8772958d90d61f2afa3631b95aba40b40ed6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:22 -0600 Subject: board/stm32f446e-eval/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iffe945ec16ed14b2f83777a3f824f5818a9a2682 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728955 Reviewed-by: Jeremy Bettis --- board/stm32f446e-eval/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/stm32f446e-eval/board.h b/board/stm32f446e-eval/board.h index aa498d6caa..10eeef7675 100644 --- a/board/stm32f446e-eval/board.h +++ b/board/stm32f446e-eval/board.h @@ -43,12 +43,12 @@ /* USB interface indexes (use define rather than enum to expand them) */ #define USB_IFACE_CONSOLE 0 -#define USB_IFACE_COUNT 1 +#define USB_IFACE_COUNT 1 /* USB endpoint indexes (use define rather than enum to expand them) */ #define USB_EP_CONTROL 0 #define USB_EP_CONSOLE 1 -#define USB_EP_COUNT 2 +#define USB_EP_COUNT 2 /* This is not actually an EC so disable some features. */ #undef CONFIG_WATCHDOG_HELP -- cgit v1.2.1 From b09d36210e413e222e41ff6ca2282c5392e6e594 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:07 -0600 Subject: util/ecst.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52e9b7b48aca68fe8865bbc107ec52f96c5f8d18 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730617 Reviewed-by: Jeremy Bettis --- util/ecst.h | 343 ++++++++++++++++++++++++++++-------------------------------- 1 file changed, 162 insertions(+), 181 deletions(-) diff --git a/util/ecst.h b/util/ecst.h index 628eaebe9b..9361418d97 100644 --- a/util/ecst.h +++ b/util/ecst.h @@ -16,149 +16,146 @@ #include #include - /*--------------------------------------------------------------------------- Defines --------------------------------------------------------------------------*/ /* For the beauty */ -#define TRUE 1 -#define FALSE 0 +#define TRUE 1 +#define FALSE 0 /* CHANGEME when the version is updated */ -#define T_VER 1 -#define T_REV_MAJOR 0 -#define T_REV_MINOR 3 +#define T_VER 1 +#define T_REV_MAJOR 0 +#define T_REV_MINOR 3 /* Header starts by default at 0x20000 */ -#define FIRMWARE_OFFSET_FROM_HEADER 0x40 +#define FIRMWARE_OFFSET_FROM_HEADER 0x40 -#define ARM_FW_ENTRY_POINT_OFFSET 0x04 +#define ARM_FW_ENTRY_POINT_OFFSET 0x04 /* Some useful offsets inside the header */ -#define HDR_ANCHOR_OFFSET 0 -#define HDR_EXTENDED_ANCHOR_OFFSET 4 -#define HDR_SPI_MAX_CLK_OFFSET 6 -#define HDR_SPI_READ_MODE_OFFSET 7 -#define HDR_ERR_DETECTION_CONF_OFFSET 8 -#define HDR_FW_LOAD_START_ADDR_OFFSET 9 -#define HDR_FW_ENTRY_POINT_OFFSET 13 -#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17 -#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21 -#define HDR_FW_LENGTH_OFFSET 25 -#define HDR_FLASH_SIZE_OFFSET 29 -#define HDR_RESERVED 30 -#define HDR_FW_HEADER_SIG_OFFSET 56 -#define HDR_FW_IMAGE_SIG_OFFSET 60 - - -#define FIRMW_CKSM_OFFSET 0x3C +#define HDR_ANCHOR_OFFSET 0 +#define HDR_EXTENDED_ANCHOR_OFFSET 4 +#define HDR_SPI_MAX_CLK_OFFSET 6 +#define HDR_SPI_READ_MODE_OFFSET 7 +#define HDR_ERR_DETECTION_CONF_OFFSET 8 +#define HDR_FW_LOAD_START_ADDR_OFFSET 9 +#define HDR_FW_ENTRY_POINT_OFFSET 13 +#define HDR_FW_ERR_DETECT_START_ADDR_OFFSET 17 +#define HDR_FW_ERR_DETECT_END_ADDR_OFFSET 21 +#define HDR_FW_LENGTH_OFFSET 25 +#define HDR_FLASH_SIZE_OFFSET 29 +#define HDR_RESERVED 30 +#define HDR_FW_HEADER_SIG_OFFSET 56 +#define HDR_FW_IMAGE_SIG_OFFSET 60 + +#define FIRMW_CKSM_OFFSET 0x3C /* Header field known values */ -#define FW_HDR_ANCHOR 0x2A3B4D5E -#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E -#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1 -#define FW_CRC_DISABLE 0x00 -#define FW_CRC_ENABLE 0x02 -#define HEADER_CRC_FIELDS_SIZE 8 +#define FW_HDR_ANCHOR 0x2A3B4D5E +#define FW_HDR_EXT_ANCHOR_ENABLE 0xAB1E +#define FW_HDR_EXT_ANCHOR_DISABLE 0x54E1 +#define FW_CRC_DISABLE 0x00 +#define FW_CRC_ENABLE 0x02 +#define HEADER_CRC_FIELDS_SIZE 8 -#define HDR_PTR_SIGNATURE 0x55AA650E +#define HDR_PTR_SIGNATURE 0x55AA650E -#define CKSMCRC_INV_BIT_OFFSET 0x1 +#define CKSMCRC_INV_BIT_OFFSET 0x1 /* Some common Sizes */ -#define STR_SIZE 200 -#define ARG_SIZE 100 -#define NAME_SIZE 160 -#define BUFF_SIZE 0x400 -#define HEADER_SIZE 64 -#define TMP_STR_SIZE 21 -#define PAD_VALUE 0x00 - +#define STR_SIZE 200 +#define ARG_SIZE 100 +#define NAME_SIZE 160 +#define BUFF_SIZE 0x400 +#define HEADER_SIZE 64 +#define TMP_STR_SIZE 21 +#define PAD_VALUE 0x00 -#define MAX_ARGS 100 +#define MAX_ARGS 100 /* Text Colors */ -#define TDBG 0x02 /* Dark Green */ -#define TPAS 0x0A /* light green */ -#define TINF 0x0B /* light turquise */ -#define TERR 0x0C /* light red */ -#define TUSG 0x0E /* light yellow */ +#define TDBG 0x02 /* Dark Green */ +#define TPAS 0x0A /* light green */ +#define TINF 0x0B /* light turquise */ +#define TERR 0x0C /* light red */ +#define TUSG 0x0E /* light yellow */ /* Indicates bin Command line parameters */ -#define BIN_FW_HDR_CRC_DISABLE 0x0001 -#define BIN_FW_CRC_DISABLE 0x0002 -#define BIN_FW_START 0x0004 -#define BIN_FW_SIZE 0x0008 -#define BIN_CK_FIRMWARE 0x0010 -#define BIN_FW_CKS_START 0x0020 -#define BIN_FW_CKS_SIZE 0x0040 -#define BIN_FW_CHANGE_SIG 0x0080 -#define BIN_FW_SPI_MAX_CLK 0x0100 -#define BIN_FW_LOAD_START_ADDR 0x0200 -#define BIN_FW_ENTRY_POINT 0x0400 -#define BIN_FW_LENGTH 0x0800 -#define BIN_FW_HDR_OFFSET 0x1000 -#define BIN_FW_USER_ARM_RESET 0x2000 -#define BIN_UNLIM_BURST_ENABLE 0x4000 - -#define ECRP_OFFSET 0x01 -#define ECRP_INPUT_FILE 0x02 -#define ECRP_OUTPUT_FILE 0x04 - -#define SPI_MAX_CLOCK_20_MHZ_VAL 20 -#define SPI_MAX_CLOCK_25_MHZ_VAL 25 -#define SPI_MAX_CLOCK_33_MHZ_VAL 33 -#define SPI_MAX_CLOCK_40_MHZ_VAL 40 -#define SPI_MAX_CLOCK_50_MHZ_VAL 50 - -#define SPI_MAX_CLOCK_20_MHZ 0x00 -#define SPI_MAX_CLOCK_25_MHZ 0x01 -#define SPI_MAX_CLOCK_33_MHZ 0x02 -#define SPI_MAX_CLOCK_40_MHZ 0x03 -#define SPI_MAX_CLOCK_50_MHZ 0x04 -#define SPI_MAX_CLOCK_MASK 0xF8 - -#define SPI_CLOCK_RATIO_1_VAL 1 -#define SPI_CLOCK_RATIO_2_VAL 2 - -#define SPI_CLOCK_RATIO_1 0x07 -#define SPI_CLOCK_RATIO_2 0x08 - -#define SPI_NORMAL_MODE_VAL "normal" -#define SPI_SINGLE_MODE_VAL "fast" -#define SPI_DUAL_MODE_VAL "dual" -#define SPI_QUAD_MODE_VAL "quad" - -#define SPI_NORMAL_MODE 0x00 -#define SPI_SINGLE_MODE 0x01 -#define SPI_DUAL_MODE 0x03 -#define SPI_QUAD_MODE 0x04 - -#define SPI_UNLIMITED_BURST_ENABLE 0x08 - -#define FLASH_SIZE_1_MBYTES_VAL 1 -#define FLASH_SIZE_2_MBYTES_VAL 2 -#define FLASH_SIZE_4_MBYTES_VAL 4 -#define FLASH_SIZE_8_MBYTES_VAL 8 -#define FLASH_SIZE_16_MBYTES_VAL 16 - -#define FLASH_SIZE_1_MBYTES 0x01 -#define FLASH_SIZE_2_MBYTES 0x03 -#define FLASH_SIZE_4_MBYTES 0x07 -#define FLASH_SIZE_8_MBYTES 0x0F -#define FLASH_SIZE_16_MBYTES 0x1F +#define BIN_FW_HDR_CRC_DISABLE 0x0001 +#define BIN_FW_CRC_DISABLE 0x0002 +#define BIN_FW_START 0x0004 +#define BIN_FW_SIZE 0x0008 +#define BIN_CK_FIRMWARE 0x0010 +#define BIN_FW_CKS_START 0x0020 +#define BIN_FW_CKS_SIZE 0x0040 +#define BIN_FW_CHANGE_SIG 0x0080 +#define BIN_FW_SPI_MAX_CLK 0x0100 +#define BIN_FW_LOAD_START_ADDR 0x0200 +#define BIN_FW_ENTRY_POINT 0x0400 +#define BIN_FW_LENGTH 0x0800 +#define BIN_FW_HDR_OFFSET 0x1000 +#define BIN_FW_USER_ARM_RESET 0x2000 +#define BIN_UNLIM_BURST_ENABLE 0x4000 + +#define ECRP_OFFSET 0x01 +#define ECRP_INPUT_FILE 0x02 +#define ECRP_OUTPUT_FILE 0x04 + +#define SPI_MAX_CLOCK_20_MHZ_VAL 20 +#define SPI_MAX_CLOCK_25_MHZ_VAL 25 +#define SPI_MAX_CLOCK_33_MHZ_VAL 33 +#define SPI_MAX_CLOCK_40_MHZ_VAL 40 +#define SPI_MAX_CLOCK_50_MHZ_VAL 50 + +#define SPI_MAX_CLOCK_20_MHZ 0x00 +#define SPI_MAX_CLOCK_25_MHZ 0x01 +#define SPI_MAX_CLOCK_33_MHZ 0x02 +#define SPI_MAX_CLOCK_40_MHZ 0x03 +#define SPI_MAX_CLOCK_50_MHZ 0x04 +#define SPI_MAX_CLOCK_MASK 0xF8 + +#define SPI_CLOCK_RATIO_1_VAL 1 +#define SPI_CLOCK_RATIO_2_VAL 2 + +#define SPI_CLOCK_RATIO_1 0x07 +#define SPI_CLOCK_RATIO_2 0x08 + +#define SPI_NORMAL_MODE_VAL "normal" +#define SPI_SINGLE_MODE_VAL "fast" +#define SPI_DUAL_MODE_VAL "dual" +#define SPI_QUAD_MODE_VAL "quad" + +#define SPI_NORMAL_MODE 0x00 +#define SPI_SINGLE_MODE 0x01 +#define SPI_DUAL_MODE 0x03 +#define SPI_QUAD_MODE 0x04 + +#define SPI_UNLIMITED_BURST_ENABLE 0x08 + +#define FLASH_SIZE_1_MBYTES_VAL 1 +#define FLASH_SIZE_2_MBYTES_VAL 2 +#define FLASH_SIZE_4_MBYTES_VAL 4 +#define FLASH_SIZE_8_MBYTES_VAL 8 +#define FLASH_SIZE_16_MBYTES_VAL 16 + +#define FLASH_SIZE_1_MBYTES 0x01 +#define FLASH_SIZE_2_MBYTES 0x03 +#define FLASH_SIZE_4_MBYTES 0x07 +#define FLASH_SIZE_8_MBYTES 0x0F +#define FLASH_SIZE_16_MBYTES 0x1F /* Header fields default values. */ -#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL -#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE -#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL -#define FW_CRC_START_ADDR 0x00000000 +#define SPI_MAX_CLOCK_DEFAULT SPI_MAX_CLOCK_20_MHZ_VAL +#define SPI_READ_MODE_DEFAULT SPI_NORMAL_MODE +#define FLASH_SIZE_DEFAULT FLASH_SIZE_16_MBYTES_VAL +#define FW_CRC_START_ADDR 0x00000000 -#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F -#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003 +#define ADDR_16_BYTES_ALIGNED_MASK 0x0000000F +#define ADDR_4_BYTES_ALIGNED_MASK 0x00000003 -#define MAX_FLASH_SIZE 0x03ffffff +#define MAX_FLASH_SIZE 0x03ffffff /* Chips: convert from name to index. */ enum npcx_chip_ram_variant { @@ -172,25 +169,25 @@ enum npcx_chip_ram_variant { NPCX_CHIP_RAM_VAR_NONE }; -#define DEFAULT_CHIP NPCX5M5G +#define DEFAULT_CHIP NPCX5M5G /* NPCX5 */ -#define NPCX5M5G_RAM_ADDR 0x100A8000 -#define NPCX5M5G_RAM_SIZE 0x20000 -#define NPCX5M6G_RAM_ADDR 0x10088000 -#define NPCX5M6G_RAM_SIZE 0x40000 +#define NPCX5M5G_RAM_ADDR 0x100A8000 +#define NPCX5M5G_RAM_SIZE 0x20000 +#define NPCX5M6G_RAM_ADDR 0x10088000 +#define NPCX5M6G_RAM_SIZE 0x40000 /* NPCX7 */ -#define NPCX7M5X_RAM_ADDR 0x100A8000 -#define NPCX7M5X_RAM_SIZE 0x20000 -#define NPCX7M6X_RAM_ADDR 0x10090000 -#define NPCX7M6X_RAM_SIZE 0x40000 -#define NPCX7M7X_RAM_ADDR 0x10070000 -#define NPCX7M7X_RAM_SIZE 0x60000 +#define NPCX7M5X_RAM_ADDR 0x100A8000 +#define NPCX7M5X_RAM_SIZE 0x20000 +#define NPCX7M6X_RAM_ADDR 0x10090000 +#define NPCX7M6X_RAM_SIZE 0x40000 +#define NPCX7M7X_RAM_ADDR 0x10070000 +#define NPCX7M7X_RAM_SIZE 0x60000 /* NPCX9 */ -#define NPCX9M3X_RAM_ADDR 0x10080000 -#define NPCX9M3X_RAM_SIZE 0x50000 -#define NPCX9M6X_RAM_ADDR 0x10090000 -#define NPCX9M6X_RAM_SIZE 0x40000 +#define NPCX9M3X_RAM_ADDR 0x10080000 +#define NPCX9M3X_RAM_SIZE 0x50000 +#define NPCX9M6X_RAM_ADDR 0x10090000 +#define NPCX9M6X_RAM_SIZE 0x40000 /*--------------------------------------------------------------------------- Typedefs @@ -198,47 +195,39 @@ enum npcx_chip_ram_variant { /* Parameters for Binary manipulation */ struct tbinparams { - unsigned int anchor; - unsigned short ext_anchor; - unsigned char spi_max_clk; - unsigned char spi_clk_ratio; - unsigned char spi_read_mode; - unsigned char err_detec_cnf; - unsigned int fw_load_addr; - unsigned int fw_ep; - unsigned int fw_err_detec_s_addr; - unsigned int fw_err_detec_e_addr; - unsigned int fw_len; - unsigned int flash_size; - unsigned int hdr_crc; - unsigned int fw_crc; - unsigned int fw_hdr_offset; - unsigned int bin_params; + unsigned int anchor; + unsigned short ext_anchor; + unsigned char spi_max_clk; + unsigned char spi_clk_ratio; + unsigned char spi_read_mode; + unsigned char err_detec_cnf; + unsigned int fw_load_addr; + unsigned int fw_ep; + unsigned int fw_err_detec_s_addr; + unsigned int fw_err_detec_e_addr; + unsigned int fw_len; + unsigned int flash_size; + unsigned int hdr_crc; + unsigned int fw_crc; + unsigned int fw_hdr_offset; + unsigned int bin_params; } bin_params_struct; -enum verbose_level { - NO_VERBOSE = 0, - REGULAR_VERBOSE, - SUPER_VERBOSE -}; +enum verbose_level { NO_VERBOSE = 0, REGULAR_VERBOSE, SUPER_VERBOSE }; -enum calc_type { - CALC_TYPE_NONE = 0, - CALC_TYPE_CHECKSUM , - CALC_TYPE_CRC -}; +enum calc_type { CALC_TYPE_NONE = 0, CALC_TYPE_CHECKSUM, CALC_TYPE_CRC }; struct chip_info { - unsigned int ram_addr; - unsigned int ram_size; + unsigned int ram_addr; + unsigned int ram_size; } chip_info_struct; /*------------------------------------------------------------------------*/ /* CRC Variable bit operation macros */ /*------------------------------------------------------------------------*/ -#define NUM_OF_BYTES 32 -#define READ_VAR_BIT(var, nb) (((var) >> (nb)) & 0x1) -#define SET_VAR_BIT(var, nb, val) ((var) |= ((val)<<(nb))) +#define NUM_OF_BYTES 32 +#define READ_VAR_BIT(var, nb) (((var) >> (nb)) & 0x1) +#define SET_VAR_BIT(var, nb, val) ((var) |= ((val) << (nb))) /*--------------------------------------------------------------------------- Functions Declaration @@ -254,35 +243,27 @@ void init_calculation(unsigned int *check_sum_crc); void finalize_calculation(unsigned int *check_sum_crc); void update_calculation_information(unsigned char crc_con_dat); - /* Checksum calculation etc. (BIN Specific) */ int calc_header_crc_bin(unsigned int *pointer_header_checksum); -int calc_firmware_csum_bin(unsigned int *p_cksum, - unsigned int fw_offset, - unsigned int fw_length); +int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset, + unsigned int fw_length); /* Checksum calculation etc. (ERP Specific) */ int calc_erp_csum_bin(unsigned short *region_pointer_header_checksum, - unsigned int region_pointer_ofs); + unsigned int region_pointer_ofs); /* No words - General */ void exit_with_usage(void); -int copy_file_to_file(char *dst_file_name, - char *src_file_name, - int offset, - int origin); -int write_to_file(unsigned int write_value, - unsigned int offset, - unsigned char num_of_bytes, - char *print_string); -int read_from_file(unsigned int offset, - unsigned char size_to_read, - unsigned int *read_value, - char *print_string); +int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset, + int origin); +int write_to_file(unsigned int write_value, unsigned int offset, + unsigned char num_of_bytes, char *print_string); +int read_from_file(unsigned int offset, unsigned char size_to_read, + unsigned int *read_value, char *print_string); /* Nice Particular Printf - General */ -__attribute__((__format__(__printf__, 2, 3))) -void my_printf(int error_level, char *fmt, ...); +__attribute__((__format__(__printf__, 2, 3))) void my_printf(int error_level, + char *fmt, ...); int str_cmp_no_case(const char *s1, const char *s2); int get_file_length(FILE *stream); -- cgit v1.2.1 From d04173325fe40f0bfbc9d460e84441ad1e6c14c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:58 -0600 Subject: common/pstore_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie912103a587276592e230b82d665b26258c6ad8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729702 Reviewed-by: Jeremy Bettis --- common/pstore_commands.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/common/pstore_commands.c b/common/pstore_commands.c index 469af6a054..ed4c8221a8 100644 --- a/common/pstore_commands.c +++ b/common/pstore_commands.c @@ -23,8 +23,7 @@ pstore_command_get_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO, - pstore_command_get_info, +DECLARE_HOST_COMMAND(EC_CMD_PSTORE_INFO, pstore_command_get_info, EC_VER_MASK(0)); static enum ec_status pstore_command_read(struct host_cmd_handler_args *args) @@ -60,9 +59,7 @@ static enum ec_status pstore_command_read(struct host_cmd_handler_args *args) args->response_size = p->size; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ, - pstore_command_read, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_PSTORE_READ, pstore_command_read, EC_VER_MASK(0)); static enum ec_status pstore_command_write(struct host_cmd_handler_args *args) { @@ -97,6 +94,4 @@ static enum ec_status pstore_command_write(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE, - pstore_command_write, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_PSTORE_WRITE, pstore_command_write, EC_VER_MASK(0)); -- cgit v1.2.1 From f3258a7dcf00d6eb5fe22ad03bbce978aaf73666 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:04 -0600 Subject: driver/sensorhub_lsm6dsm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a4b3592aa953449044559b73aeab4956b77ba62 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730064 Reviewed-by: Jeremy Bettis --- driver/sensorhub_lsm6dsm.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/driver/sensorhub_lsm6dsm.h b/driver/sensorhub_lsm6dsm.h index 07b19046df..f453565810 100644 --- a/driver/sensorhub_lsm6dsm.h +++ b/driver/sensorhub_lsm6dsm.h @@ -25,8 +25,8 @@ * @return EC_SUCCESS on success, EC error codes on failure. */ int sensorhub_config_ext_reg(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint8_t reg, uint8_t val); + const uint16_t slv_addr_flags, uint8_t reg, + uint8_t val); /** * Configure the sensor hub to read data from a specific register of an @@ -39,8 +39,8 @@ int sensorhub_config_ext_reg(const struct motion_sensor_t *s, * @return EC_SUCCESS on success, EC error codes on failure. */ int sensorhub_config_slv0_read(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint8_t reg, int len); + const uint16_t slv_addr_flags, uint8_t reg, + int len); /** * Reads the data from the register bank that is associated with the slave0 @@ -65,7 +65,7 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw); * @return EC_SUCCESS on success, EC error codes on failure. */ int sensorhub_check_and_rst(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint8_t whoami_reg, uint8_t whoami_val, - uint8_t rst_reg, uint8_t rst_val); + const uint16_t slv_addr_flags, uint8_t whoami_reg, + uint8_t whoami_val, uint8_t rst_reg, + uint8_t rst_val); #endif /* __CROS_EC_SENSORHUB_LSM6DSM_H */ -- cgit v1.2.1 From b71804c998145f60e33b6e9f3ee6aa45b76b0a57 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:16 -0600 Subject: util/usb_if.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icefc6c35830490cb7f7120dbb2cb707f787ff4d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730657 Reviewed-by: Jeremy Bettis --- util/usb_if.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/util/usb_if.h b/util/usb_if.h index 8cc1088c6e..587880f483 100644 --- a/util/usb_if.h +++ b/util/usb_if.h @@ -13,7 +13,7 @@ struct usb_endpoint { struct libusb_device_handle *devh; uint8_t ep_num; - int chunk_len; + int chunk_len; }; /* @@ -34,9 +34,8 @@ int usb_findit(const char *serialno, uint16_t vid, uint16_t pid, * pointer, if provided along with 'allow_less', lets the caller know how many * bytes were received. */ -int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, - void *inbuf, int inlen, int allow_less, - size_t *rxed_count); +int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf, + int inlen, int allow_less, size_t *rxed_count); /* * This function should be called for graceful tear down of the USB interface @@ -46,8 +45,8 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, */ void usb_shut_down(struct usb_endpoint *uep); -#define USB_ERROR(m, r) \ - fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, \ - m, r, libusb_strerror(r)) +#define USB_ERROR(m, r) \ + fprintf(stderr, "%s:%d, %s returned %d (%s)\n", __FILE__, __LINE__, m, \ + r, libusb_strerror(r)) -#endif /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */ +#endif /* ! __EC_EXTRA_USB_UPDATER_USB_IF_H */ -- cgit v1.2.1 From 134e4afa658cb21bb1c3fb9548183a05ce0c483d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:40 -0600 Subject: driver/temp_sensor/tmp432.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9f20bf7f21640ef015ce340c9d0468bfc082ba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729884 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp432.h | 138 ++++++++++++++++++++++---------------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/driver/temp_sensor/tmp432.h b/driver/temp_sensor/tmp432.h index e58e39a4a0..a04a6dc75f 100644 --- a/driver/temp_sensor/tmp432.h +++ b/driver/temp_sensor/tmp432.h @@ -8,85 +8,85 @@ #ifndef __CROS_EC_TMP432_H #define __CROS_EC_TMP432_H -#define TMP432_I2C_ADDR_FLAGS 0x4C +#define TMP432_I2C_ADDR_FLAGS 0x4C -#define TMP432_IDX_LOCAL 0 -#define TMP432_IDX_REMOTE1 1 -#define TMP432_IDX_REMOTE2 2 -#define TMP432_IDX_COUNT 3 +#define TMP432_IDX_LOCAL 0 +#define TMP432_IDX_REMOTE1 1 +#define TMP432_IDX_REMOTE2 2 +#define TMP432_IDX_COUNT 3 /* Chip-specific registers */ -#define TMP432_LOCAL 0x00 -#define TMP432_REMOTE1 0x01 -#define TMP432_STATUS 0x02 -#define TMP432_CONFIGURATION1_R 0x03 -#define TMP432_CONVERSION_RATE_R 0x04 -#define TMP432_LOCAL_HIGH_LIMIT_R 0x05 -#define TMP432_LOCAL_LOW_LIMIT_R 0x06 -#define TMP432_REMOTE1_HIGH_LIMIT_R 0x07 -#define TMP432_REMOTE1_LOW_LIMIT_R 0x08 -#define TMP432_CONFIGURATION1_W 0x09 -#define TMP432_CONVERSION_RATE_W 0x0a -#define TMP432_LOCAL_HIGH_LIMIT_W 0x0b -#define TMP432_LOCAL_LOW_LIMIT_W 0x0c -#define TMP432_REMOTE1_HIGH_LIMIT_W 0x0d -#define TMP432_REMOTE1_LOW_LIMIT_W 0x0e -#define TMP432_ONESHOT 0x0f -#define TMP432_REMOTE1_EXTD 0x10 -#define TMP432_REMOTE1_HIGH_LIMIT_EXTD 0x13 -#define TMP432_REMOTE1_LOW_LIMIT_EXTD 0x14 -#define TMP432_REMOTE2_HIGH_LIMIT_R 0x15 -#define TMP432_REMOTE2_HIGH_LIMIT_W 0x15 -#define TMP432_REMOTE2_LOW_LIMIT_R 0x16 -#define TMP432_REMOTE2_LOW_LIMIT_W 0x16 -#define TMP432_REMOTE2_HIGH_LIMIT_EXTD 0x17 -#define TMP432_REMOTE2_LOW_LIMIT_EXTD 0x18 -#define TMP432_REMOTE1_THERM_LIMIT 0x19 -#define TMP432_REMOTE2_THERM_LIMIT 0x1a -#define TMP432_STATUS_FAULT 0x1b -#define TMP432_CHANNEL_MASK 0x1f -#define TMP432_LOCAL_THERM_LIMIT 0x20 -#define TMP432_THERM_HYSTERESIS 0x21 -#define TMP432_CONSECUTIVE_ALERT 0x22 -#define TMP432_REMOTE2 0x23 -#define TMP432_REMOTE2_EXTD 0x24 -#define TMP432_BETA_RANGE_CH1 0x25 -#define TMP432_BETA_RANGE_CH2 0x26 -#define TMP432_NFACTOR_REMOTE1 0x27 -#define TMP432_NFACTOR_REMOTE2 0x28 -#define TMP432_LOCAL_EXTD 0x29 -#define TMP432_STATUS_LIMIT_HIGH 0x35 -#define TMP432_STATUS_LIMIT_LOW 0x36 -#define TMP432_STATUS_THERM 0x37 -#define TMP432_LOCAL_HIGH_LIMIT_EXTD 0x3d -#define TMP432_LOCAL_LOW_LIMIT_EXTD 0x3e -#define TMP432_CONFIGURATION2_R 0x3f -#define TMP432_CONFIGURATION2_W 0x3f -#define TMP432_RESET_W 0xfc -#define TMP432_DEVICE_ID 0xfd -#define TMP432_MANUFACTURER_ID 0xfe +#define TMP432_LOCAL 0x00 +#define TMP432_REMOTE1 0x01 +#define TMP432_STATUS 0x02 +#define TMP432_CONFIGURATION1_R 0x03 +#define TMP432_CONVERSION_RATE_R 0x04 +#define TMP432_LOCAL_HIGH_LIMIT_R 0x05 +#define TMP432_LOCAL_LOW_LIMIT_R 0x06 +#define TMP432_REMOTE1_HIGH_LIMIT_R 0x07 +#define TMP432_REMOTE1_LOW_LIMIT_R 0x08 +#define TMP432_CONFIGURATION1_W 0x09 +#define TMP432_CONVERSION_RATE_W 0x0a +#define TMP432_LOCAL_HIGH_LIMIT_W 0x0b +#define TMP432_LOCAL_LOW_LIMIT_W 0x0c +#define TMP432_REMOTE1_HIGH_LIMIT_W 0x0d +#define TMP432_REMOTE1_LOW_LIMIT_W 0x0e +#define TMP432_ONESHOT 0x0f +#define TMP432_REMOTE1_EXTD 0x10 +#define TMP432_REMOTE1_HIGH_LIMIT_EXTD 0x13 +#define TMP432_REMOTE1_LOW_LIMIT_EXTD 0x14 +#define TMP432_REMOTE2_HIGH_LIMIT_R 0x15 +#define TMP432_REMOTE2_HIGH_LIMIT_W 0x15 +#define TMP432_REMOTE2_LOW_LIMIT_R 0x16 +#define TMP432_REMOTE2_LOW_LIMIT_W 0x16 +#define TMP432_REMOTE2_HIGH_LIMIT_EXTD 0x17 +#define TMP432_REMOTE2_LOW_LIMIT_EXTD 0x18 +#define TMP432_REMOTE1_THERM_LIMIT 0x19 +#define TMP432_REMOTE2_THERM_LIMIT 0x1a +#define TMP432_STATUS_FAULT 0x1b +#define TMP432_CHANNEL_MASK 0x1f +#define TMP432_LOCAL_THERM_LIMIT 0x20 +#define TMP432_THERM_HYSTERESIS 0x21 +#define TMP432_CONSECUTIVE_ALERT 0x22 +#define TMP432_REMOTE2 0x23 +#define TMP432_REMOTE2_EXTD 0x24 +#define TMP432_BETA_RANGE_CH1 0x25 +#define TMP432_BETA_RANGE_CH2 0x26 +#define TMP432_NFACTOR_REMOTE1 0x27 +#define TMP432_NFACTOR_REMOTE2 0x28 +#define TMP432_LOCAL_EXTD 0x29 +#define TMP432_STATUS_LIMIT_HIGH 0x35 +#define TMP432_STATUS_LIMIT_LOW 0x36 +#define TMP432_STATUS_THERM 0x37 +#define TMP432_LOCAL_HIGH_LIMIT_EXTD 0x3d +#define TMP432_LOCAL_LOW_LIMIT_EXTD 0x3e +#define TMP432_CONFIGURATION2_R 0x3f +#define TMP432_CONFIGURATION2_W 0x3f +#define TMP432_RESET_W 0xfc +#define TMP432_DEVICE_ID 0xfd +#define TMP432_MANUFACTURER_ID 0xfe /* Config register bits */ -#define TMP432_CONFIG1_TEMP_RANGE BIT(2) +#define TMP432_CONFIG1_TEMP_RANGE BIT(2) /* TMP432_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP432_CONFIG1_MODE BIT(5) -#define TMP432_CONFIG1_RUN_L BIT(6) -#define TMP432_CONFIG1_ALERT_MASK_L BIT(7) -#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2) -#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3) -#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4) -#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5) +#define TMP432_CONFIG1_MODE BIT(5) +#define TMP432_CONFIG1_RUN_L BIT(6) +#define TMP432_CONFIG1_ALERT_MASK_L BIT(7) +#define TMP432_CONFIG2_RESISTANCE_CORRECTION BIT(2) +#define TMP432_CONFIG2_LOCAL_ENABLE BIT(3) +#define TMP432_CONFIG2_REMOTE1_ENABLE BIT(4) +#define TMP432_CONFIG2_REMOTE2_ENABLE BIT(5) /* Status register bits */ -#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1) -#define TMP432_STATUS_OPEN BIT(2) -#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3) -#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4) -#define TMP432_STATUS_BUSY BIT(7) +#define TMP432_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP432_STATUS_OPEN BIT(2) +#define TMP432_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP432_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP432_STATUS_BUSY BIT(7) /* Limintaions */ -#define TMP432_HYSTERESIS_HIGH_LIMIT 255 -#define TMP432_HYSTERESIS_LOW_LIMIT 0 +#define TMP432_HYSTERESIS_HIGH_LIMIT 255 +#define TMP432_HYSTERESIS_LOW_LIMIT 0 enum tmp432_power_state { TMP432_POWER_OFF = 0, -- cgit v1.2.1 From ac123b940959625797ef8c53487cffa617ac0f75 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:09 -0600 Subject: board/redrix/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic4957dac65b6220652fb10499a00c70b1d0da1bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728880 Reviewed-by: Jeremy Bettis --- board/redrix/led.c | 69 +++++++++++++++++++++++++++++------------------------- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/board/redrix/led.c b/board/redrix/led.c index 86e60b725a..187fcd1e78 100644 --- a/board/redrix/led.c +++ b/board/redrix/led.c @@ -24,16 +24,14 @@ #define POWER_LED_OFF 1 #define LED_TICK_INTERVAL_MS (500 * MSEC) -#define LED_CYCLE_TIME_MS (2000 * MSEC) -#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) -#define LED_ON_TIME_MS (1000 * MSEC) -#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +#define LED_CYCLE_TIME_MS (2000 * MSEC) +#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1000 * MSEC) +#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -41,22 +39,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LEFT_PORT = 0, - RIGHT_PORT -}; +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; static void led_set_color_battery(int port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_AMBER_L : - GPIO_C0_CHARGE_LED_AMBER_L); + GPIO_C0_CHARGE_LED_AMBER_L); white_led = (port == RIGHT_PORT ? GPIO_C1_CHARGE_LED_WHITE_L : - GPIO_C0_CHARGE_LED_WHITE_L); + GPIO_C0_CHARGE_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -151,10 +146,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -172,31 +167,39 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(LEFT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + LEFT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(LEFT_PORT, LED_OFF); } break; case PWR_STATE_ERROR: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { - led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ? + LED_AMBER : + LED_OFF); } break; case PWR_STATE_CHARGE_NEAR_FULL: @@ -204,9 +207,11 @@ static void led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 1c369b4ae7b5c30cf03880b24b10be0735788b72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:01 -0600 Subject: board/asurada/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0a1c51f33847b741771bcfdc5a74d8ff8f7f9ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728011 Reviewed-by: Jeremy Bettis --- board/asurada/board.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/asurada/board.h b/board/asurada/board.h index 85b10e69b3..e2315f44c2 100644 --- a/board/asurada/board.h +++ b/board/asurada/board.h @@ -41,7 +41,7 @@ #define PD_MAX_VOLTAGE_MV 20000 #define PD_MAX_POWER_MW 60000 #endif -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* Optional console commands */ @@ -49,7 +49,7 @@ #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_STACKOVERFLOW -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 /* Sensor */ #define CONFIG_GMR_TABLET_MODE @@ -118,12 +118,12 @@ enum sensor_id { }; enum adc_channel { - ADC_VBUS_C0, /* ADC 0 */ - ADC_BOARD_ID_0, /* ADC 1 */ - ADC_BOARD_ID_1, /* ADC 2 */ - ADC_CHARGER_AMON_R, /* ADC 3 */ - ADC_VBUS_C1, /* ADC 5 */ - ADC_CHARGER_PMON, /* ADC 6 */ + ADC_VBUS_C0, /* ADC 0 */ + ADC_BOARD_ID_0, /* ADC 1 */ + ADC_BOARD_ID_1, /* ADC 2 */ + ADC_CHARGER_AMON_R, /* ADC 3 */ + ADC_VBUS_C1, /* ADC 5 */ + ADC_CHARGER_PMON, /* ADC 6 */ /* Number of ADC channels */ ADC_CH_COUNT, -- cgit v1.2.1 From 4f0bab37053806e559044ff2d94b55b041cfffd4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:11 -0600 Subject: common/usb_charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I964aae70868d123c43fe37484ee1fd3e406bbcf0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729525 Reviewed-by: Jeremy Bettis --- common/usb_charger.c | 35 ++++++++++++----------------------- 1 file changed, 12 insertions(+), 23 deletions(-) diff --git a/common/usb_charger.c b/common/usb_charger.c index d0b6dd3ca1..3e4b66a412 100644 --- a/common/usb_charger.c +++ b/common/usb_charger.c @@ -48,7 +48,7 @@ BUILD_ASSERT(BIT(3) == TASK_EVENT_CUSTOM_BIT(3)); static void update_vbus_supplier(int port, int vbus_level) { - struct charge_port_info charge = {0}; + struct charge_port_info charge = { 0 }; if (vbus_level && !usb_charger_port_is_sourcing_vbus(port)) { charge.voltage = USB_CHARGER_VOLTAGE_MV; @@ -104,7 +104,7 @@ void usb_charger_vbus_change(int port, int vbus_level) #endif if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_CHARGER) || - (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) { + (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_PPC)) { /* USB PD task */ task_wake(PD_PORT_TO_TASK_ID(port)); } @@ -112,29 +112,19 @@ void usb_charger_vbus_change(int port, int vbus_level) void usb_charger_reset_charge(int port) { - charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, - port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_PROPRIETARY, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_CDP, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_DCP, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_BC12_SDP, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_OTHER, port, NULL); #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 - charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, port, NULL); #endif #ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP, - port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP, - port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP, port, NULL); + charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP, port, NULL); #endif - } void usb_charger_task_set_event(int port, uint8_t event) @@ -185,8 +175,7 @@ void usb_charger_task_shared(void *u) } port_evt = PORT_EVENT_UNPACK( - port, - atomic_get(&usb_charger_port_events)); + port, atomic_get(&usb_charger_port_events)); atomic_and(&usb_charger_port_events, ~PORT_EVENT_PACK(port, port_evt)); -- cgit v1.2.1 From bf481d4c36c70e4e1cd3da9fa8ddd183c4c9a799 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:30 -0600 Subject: board/tglrvp_ish/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I06c975f7a1d54af980f5168fb9b427a8676f8b69 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729031 Reviewed-by: Jeremy Bettis --- board/tglrvp_ish/board.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/tglrvp_ish/board.c b/board/tglrvp_ish/board.c index a0584410b3..e6412b5067 100644 --- a/board/tglrvp_ish/board.c +++ b/board/tglrvp_ish/board.c @@ -19,11 +19,7 @@ /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 1000 - }, + { .name = "sensor", .port = I2C_PORT_SENSOR, .kbps = 1000 }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From d3db636b67218b3d95e27a9d015741073406a20d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:28 -0600 Subject: common/cbi_eeprom.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0891009f625db01245b20cb97ecf31c95204564f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729612 Reviewed-by: Jeremy Bettis --- common/cbi_eeprom.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/common/cbi_eeprom.c b/common/cbi_eeprom.c index ef20fdc7e2..68998ab94f 100644 --- a/common/cbi_eeprom.c +++ b/common/cbi_eeprom.c @@ -14,20 +14,20 @@ #include "util.h" #include "write_protect.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args) /* * We allow EEPROMs with page size of 8 or 16. Use 8 to be the most compatible. * This causes a little more overhead for writes, but we are not writing to the * EEPROM outside of the factory process. */ -#define EEPROM_PAGE_WRITE_SIZE 8 -#define EEPROM_PAGE_WRITE_MS 5 +#define EEPROM_PAGE_WRITE_SIZE 8 +#define EEPROM_PAGE_WRITE_MS 5 static int eeprom_read(uint8_t offset, uint8_t *data, int len) { - return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, - offset, data, len); + return i2c_read_block(I2C_PORT_EEPROM, I2C_ADDR_EEPROM_FLAGS, offset, + data, len); } static int eeprom_is_write_protected(void) -- cgit v1.2.1 From 953e775eb97f038b430678ff7982c3d5a784b19d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:14 -0600 Subject: board/palkia/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I75dbeee745fbeca6860fd0a2a266b5ac27445193 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728806 Reviewed-by: Jeremy Bettis --- board/palkia/board.c | 73 ++++++++++++++++++++++++++-------------------------- 1 file changed, 36 insertions(+), 37 deletions(-) diff --git a/board/palkia/board.c b/board/palkia/board.c index cbf0e3178e..c1bce997b7 100644 --- a/board/palkia/board.c +++ b/board/palkia/board.c @@ -39,13 +39,12 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static const uint8_t actual_key_mask[KEYBOARD_COLS_MAX] = { - 0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff, - 0xff, 0xff, 0x03, 0xfd, 0x48, 0x03, 0xff, - 0xf7, 0x16 /* full set */ + 0x01, 0x68, 0xbd, 0x03, 0x7e, 0xff, 0xff, 0xff, + 0xff, 0x03, 0xfd, 0x48, 0x03, 0xff, 0xf7, 0x16 /* full set */ }; /* GPIO to enable/disable the USB Type-A port. */ @@ -119,16 +118,16 @@ static void board_lid_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -165,7 +164,7 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -184,40 +183,40 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_4] = { - "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_AMB", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_4] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Temp3", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "Temp4", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Temp3", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "Temp4", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -225,8 +224,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ -- cgit v1.2.1 From 0f532151fdf2d2da5f8796369a86ed518b084a7f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:00 -0600 Subject: board/spherion/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9f505e30771c53db3f11ae248eb185afb4cb07b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728945 Reviewed-by: Jeremy Bettis --- board/spherion/board.c | 50 +++++++++++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/board/spherion/board.c b/board/spherion/board.c index 95fa0a06de..63d443d5f8 100644 --- a/board/spherion/board.c +++ b/board/spherion/board.c @@ -46,30 +46,30 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0}, - {"BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1}, - {"BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2}, + { "VBUS_C0", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH0 }, + { "BOARD_ID_0", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH1 }, + { "BOARD_ID_1", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH2 }, /* AMON/BMON gain = 17.97 */ - {"CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH3}, - {"VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5}, - {"CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6}, - {"TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH7}, + { "CHARGER_AMON_R", ADC_MAX_MVOLT * 1000 / 17.97, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH3 }, + { "VBUS_C1", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, CHIP_ADC_CH5 }, + { "CHARGER_PMON", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, CHIP_ADC_CH6 }, + { "TEMP_SENSOR_CHARGER", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH7 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -82,12 +82,10 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); * number of pwm channel greater than three. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = PWM_HW_CH_DCR2, - .flags = 0, - .freq_hz = 10000, - .pcfsr_sel = PWM_PRESCALER_C4 - }, + [PWM_CH_KBLIGHT] = { .channel = PWM_HW_CH_DCR2, + .flags = 0, + .freq_hz = 10000, + .pcfsr_sel = PWM_PRESCALER_C4 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -106,13 +104,11 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, kb_backlight_disable, HOOK_PRIO_DEFAULT); void board_usb_mux_init(void) { if (board_get_sub_board() == SUB_BOARD_TYPEC) { - ps8743_tune_usb_eq(&usb_muxes[1], - PS8743_USB_EQ_TX_12_8_DB, + ps8743_tune_usb_eq(&usb_muxes[1], PS8743_USB_EQ_TX_12_8_DB, PS8743_USB_EQ_RX_12_8_DB); - ps8743_field_update(&usb_muxes[1], - PS8743_REG_DCI_CONFIG_2, - PS8743_AUTO_DCI_MODE_MASK, - PS8743_AUTO_DCI_MODE_FORCE_USB); + ps8743_field_update(&usb_muxes[1], PS8743_REG_DCI_CONFIG_2, + PS8743_AUTO_DCI_MODE_MASK, + PS8743_AUTO_DCI_MODE_FORCE_USB); } } DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); -- cgit v1.2.1 From aca1f9245195f35928110f660173caede0d7ac4a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:51 -0600 Subject: chip/stm32/charger_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6b84cd50056d8b2e2703bc39274ff26af7d1fdc9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729458 Reviewed-by: Jeremy Bettis --- chip/stm32/charger_detect.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/stm32/charger_detect.c b/chip/stm32/charger_detect.c index b32b9f3ac0..fa0d38474d 100644 --- a/chip/stm32/charger_detect.c +++ b/chip/stm32/charger_detect.c @@ -33,7 +33,6 @@ static uint16_t detect_type(uint16_t det_type) return STM32_USB_BCDR; } - int charger_detect_get_device_type(void) { uint16_t pdet_result; -- cgit v1.2.1 From 46008e51f5f3d3e29c9ebf89b2ba1ad4ef112125 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:59 -0600 Subject: include/driver/accelgyro_bmi260_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98ad2f622399587bd76c33ef3bf3b5df3ff93f65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730267 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi260_public.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/driver/accelgyro_bmi260_public.h b/include/driver/accelgyro_bmi260_public.h index 9b93ef65ae..e8d165275a 100644 --- a/include/driver/accelgyro_bmi260_public.h +++ b/include/driver/accelgyro_bmi260_public.h @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI260_ADDR0_FLAGS 0x68 +#define BMI260_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi260_drv; -- cgit v1.2.1 From 9ee863978ff93e915188ba72498ac48d294b9e7e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:47 -0600 Subject: board/marzipan/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6b45c95a1dec56fcabb6d9f98837e2042fab764 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728654 Reviewed-by: Jeremy Bettis --- board/marzipan/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/marzipan/usbc_config.c b/board/marzipan/usbc_config.c index e8fc9e76a3..da3eccb251 100644 --- a/board/marzipan/usbc_config.c +++ b/board/marzipan/usbc_config.c @@ -11,8 +11,8 @@ #include "usb_pd.h" #include "usbc_config.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 4bb340186e5013d99bfcb8fe381d9f0b9bb6e380 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:31 -0600 Subject: driver/tcpm/stm32gx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44bee1945fabc08bab2a6fe0709d831fb7cad12b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730099 Reviewed-by: Jeremy Bettis --- driver/tcpm/stm32gx.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/driver/tcpm/stm32gx.h b/driver/tcpm/stm32gx.h index de6a803d52..d93abe3891 100644 --- a/driver/tcpm/stm32gx.h +++ b/driver/tcpm/stm32gx.h @@ -7,8 +7,6 @@ #ifndef __CROS_EC_DRIVER_TCPM_STM32GX_H #define __CROS_EC_DRIVER_TCPM_STM32GX_H - extern const struct tcpm_drv stm32gx_tcpm_drv; - #endif /* __CROS_EC_DRIVER_TCPM_STM32GX_H */ -- cgit v1.2.1 From 8e0fcd95431605b75e0344b9cfd66e5e7f0a2b7d Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Wed, 29 Jun 2022 15:50:54 +0800 Subject: dojo: Set KB_BL PWM freq to 2400Hz To make the variation of KB_BL brightness clear, lower the PWM signal freq to 2400Hz. BUG=b:237232105 BRANCH=cherry TEST=adjust the KB_BL brightness and see the variation. Signed-off-by: Tommy Chung Change-Id: I630869a90cfa5c5be8fac36211567dade1e0ceb7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733880 Reviewed-by: Ting Shen --- board/dojo/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index 2de269c002..7ca737f337 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -298,7 +298,7 @@ const struct pwm_t pwm_channels[] = { }, [PWM_CH_KBLIGHT] = { .channel = 3, - .freq_hz = 10000, + .freq_hz = 2400, .pcfsr_sel = PWM_PRESCALER_C6, }, [PWM_CH_LED_C0_WHITE] = { -- cgit v1.2.1 From 37cd24c0e6e7c14d0962a931cafab833b75c5fb7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:19 -0600 Subject: common/usbc/usb_pe_drp_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I451c827b7ebb4b89cd0147c899224eb45a0bfef2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729790 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pe_drp_sm.c | 912 +++++++++++++++++++++----------------------- 1 file changed, 435 insertions(+), 477 deletions(-) diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index 7c7dfde6c2..0852914cd9 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -47,41 +47,42 @@ */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) #endif -#define CPRINTF_LX(x, format, args...) \ - do { \ - if (pe_debug_level >= x) \ - CPRINTF(format, ## args); \ +#define CPRINTF_LX(x, format, args...) \ + do { \ + if (pe_debug_level >= x) \ + CPRINTF(format, ##args); \ } while (0) -#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ## args) -#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ## args) -#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ## args) - -#define CPRINTS_LX(x, format, args...) \ - do { \ - if (pe_debug_level >= x) \ - CPRINTS(format, ## args); \ +#define CPRINTF_L1(format, args...) CPRINTF_LX(1, format, ##args) +#define CPRINTF_L2(format, args...) CPRINTF_LX(2, format, ##args) +#define CPRINTF_L3(format, args...) CPRINTF_LX(3, format, ##args) + +#define CPRINTS_LX(x, format, args...) \ + do { \ + if (pe_debug_level >= x) \ + CPRINTS(format, ##args); \ } while (0) -#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ## args) -#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ## args) -#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ## args) - -#define PE_SET_FN(port, _fn) atomic_or(ATOMIC_ELEM(pe[port].flags_a, (_fn)), \ - ATOMIC_MASK(_fn)) -#define PE_CLR_FN(port, _fn) atomic_clear_bits(ATOMIC_ELEM(pe[port].flags_a, \ - (_fn)), ATOMIC_MASK(_fn)) -#define PE_CHK_FN(port, _fn) (pe[port].flags_a[ATOMIC_ELEM(0, (_fn))] & \ - ATOMIC_MASK(_fn)) - -#define PE_SET_FLAG(port, name) PE_SET_FN(port, (name ## _FN)) -#define PE_CLR_FLAG(port, name) PE_CLR_FN(port, (name ## _FN)) -#define PE_CHK_FLAG(port, name) PE_CHK_FN(port, (name ## _FN)) +#define CPRINTS_L1(format, args...) CPRINTS_LX(1, format, ##args) +#define CPRINTS_L2(format, args...) CPRINTS_LX(2, format, ##args) +#define CPRINTS_L3(format, args...) CPRINTS_LX(3, format, ##args) + +#define PE_SET_FN(port, _fn) \ + atomic_or(ATOMIC_ELEM(pe[port].flags_a, (_fn)), ATOMIC_MASK(_fn)) +#define PE_CLR_FN(port, _fn) \ + atomic_clear_bits(ATOMIC_ELEM(pe[port].flags_a, (_fn)), \ + ATOMIC_MASK(_fn)) +#define PE_CHK_FN(port, _fn) \ + (pe[port].flags_a[ATOMIC_ELEM(0, (_fn))] & ATOMIC_MASK(_fn)) + +#define PE_SET_FLAG(port, name) PE_SET_FN(port, (name##_FN)) +#define PE_CLR_FLAG(port, name) PE_CLR_FN(port, (name##_FN)) +#define PE_CHK_FLAG(port, name) PE_CHK_FN(port, (name##_FN)) /* * TODO(b/229655319): support more than 32 bits @@ -99,10 +100,11 @@ #define PE_CHK_DPM_REQUEST(port, req) (pe[port].dpm_request & (req)) /* Message flags which should not persist on returning to ready state */ -#define PE_MASK_READY_CLR (BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | \ - BIT(PE_FLAGS_MSG_DISCARDED_FN) | \ - BIT(PE_FLAGS_VDM_REQUEST_TIMEOUT_FN) | \ - BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN)) +#define PE_MASK_READY_CLR \ + (BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | \ + BIT(PE_FLAGS_MSG_DISCARDED_FN) | \ + BIT(PE_FLAGS_VDM_REQUEST_TIMEOUT_FN) | \ + BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN)) /* * Combination to check whether a reply to a message was received. Our message @@ -113,8 +115,9 @@ * on the same run cycle. With chunking, received message will take an * additional cycle to be flagged. */ -#define PE_CHK_REPLY(port) (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \ - !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) +#define PE_CHK_REPLY(port) \ + (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED) && \ + !PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) /* 6.7.3 Hard Reset Counter */ #define N_HARD_RESET_COUNT 2 @@ -136,20 +139,20 @@ * solely from VCONN. Limit the number of retries without a contract to * ensure we attempt some cable discovery after a contract is in place. */ -#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT 2 +#define N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT 2 /* * Once this limit of SOP' Discover Identity messages has been set, downgrade * to PD 2.0 in case the cable is non-compliant about GoodCRC-ing higher * revisions. This limit should be higher than the precontract limit. */ -#define N_DISCOVER_IDENTITY_PD3_0_LIMIT 4 +#define N_DISCOVER_IDENTITY_PD3_0_LIMIT 4 /* * tDiscoverIdentity is only defined while an explicit contract is in place, so * extend the interval between retries pre-contract. */ -#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT (200*MSEC) +#define PE_T_DISCOVER_IDENTITY_NO_CONTRACT (200 * MSEC) /* * Only VCONN source can communicate with the cable plug. Hence, try VCONN swap @@ -316,15 +319,14 @@ static const struct usb_state pe_states[]; * If we can't print or the CONFIG_USB_PD_DEBUG_LEVEL is defined to be 0 * then the DEBUG LABELS will be removed from the build. */ -#if defined(CONFIG_COMMON_RUNTIME) && \ - (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \ - (CONFIG_USB_PD_DEBUG_LEVEL > 0)) +#if defined(CONFIG_COMMON_RUNTIME) && (!defined(CONFIG_USB_PD_DEBUG_LEVEL) || \ + (CONFIG_USB_PD_DEBUG_LEVEL > 0)) #define USB_PD_DEBUG_LABELS #endif /* List of human readable state names for console debugging */ -__maybe_unused static __const_data const char * const pe_state_names[] = { - /* Super States */ +__maybe_unused static __const_data const char *const pe_state_names[] = { +/* Super States */ #ifdef CONFIG_USB_PD_REV30 [PE_PRS_FRS_SHARED] = "SS:PE_PRS_FRS_SHARED", #endif @@ -381,7 +383,7 @@ __maybe_unused static __const_data const char * const pe_state_names[] = { #endif [PE_VDM_IDENTITY_REQUEST_CBL] = "PE_VDM_Identity_Request_Cbl", [PE_INIT_PORT_VDM_IDENTITY_REQUEST] = - "PE_INIT_PORT_VDM_Identity_Request", + "PE_INIT_PORT_VDM_Identity_Request", [PE_INIT_VDM_SVIDS_REQUEST] = "PE_INIT_VDM_SVIDs_Request", [PE_INIT_VDM_MODES_REQUEST] = "PE_INIT_VDM_Modes_Request", [PE_VDM_REQUEST_DPM] = "PE_VDM_Request_DPM", @@ -389,12 +391,12 @@ __maybe_unused static __const_data const char * const pe_state_names[] = { [PE_HANDLE_CUSTOM_VDM_REQUEST] = "PE_Handle_Custom_Vdm_Request", [PE_WAIT_FOR_ERROR_RECOVERY] = "PE_Wait_For_Error_Recovery", [PE_BIST_TX] = "PE_Bist_TX", - [PE_DEU_SEND_ENTER_USB] = "PE_DEU_Send_Enter_USB", + [PE_DEU_SEND_ENTER_USB] = "PE_DEU_Send_Enter_USB", [PE_DR_GET_SINK_CAP] = "PE_DR_Get_Sink_Cap", [PE_DR_SNK_GIVE_SOURCE_CAP] = "PE_DR_SNK_Give_Source_Cap", [PE_DR_SRC_GET_SOURCE_CAP] = "PE_DR_SRC_Get_Source_Cap", - /* PD3.0 only states below here*/ +/* PD3.0 only states below here*/ #ifdef CONFIG_USB_PD_REV30 [PE_FRS_SNK_SRC_START_AMS] = "PE_FRS_SNK_SRC_Start_Ams", [PE_GET_REVISION] = "PE_Get_Revision", @@ -416,7 +418,7 @@ __maybe_unused static __const_data const char * const pe_state_names[] = { [PE_UDR_TURN_OFF_VCONN] = "PE_UDR_Turn_Off_VCONN", [PE_UDR_SEND_PS_RDY] = "PE_UDR_Send_Ps_Rdy", [PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE] = - "PE_UDR_Wait_For_Data_Reset_Complete", + "PE_UDR_Wait_For_Data_Reset_Complete", [PE_DDR_SEND_DATA_RESET] = "PE_DDR_Send_Data_Reset", [PE_DDR_DATA_RESET_RECEIVED] = "PE_DDR_Data_Reset_Received", [PE_DDR_WAIT_FOR_VCONN_OFF] = "PE_DDR_Wait_For_VCONN_Off", @@ -529,12 +531,12 @@ static enum sm_local_state local_state[CONFIG_USB_PD_PORT_MAX_COUNT]; * what ever is needed to handle the Discard. */ enum pe_msg_check { - PE_MSG_SEND_PENDING = BIT(0), - PE_MSG_SENT = BIT(1), - PE_MSG_DISCARDED = BIT(2), + PE_MSG_SEND_PENDING = BIT(0), + PE_MSG_SENT = BIT(1), + PE_MSG_DISCARDED = BIT(2), - PE_MSG_SEND_COMPLETED = BIT(3) | PE_MSG_SENT, - PE_MSG_DPM_DISCARDED = BIT(4) | PE_MSG_DISCARDED, + PE_MSG_SEND_COMPLETED = BIT(3) | PE_MSG_SENT, + PE_MSG_DPM_DISCARDED = BIT(4) | PE_MSG_DISCARDED, }; static void pe_sender_response_msg_entry(const int port); static enum pe_msg_check pe_sender_response_msg_run(const int port); @@ -654,7 +656,7 @@ static struct policy_engine { /* Attached ChromeOS device id, RW hash, and current RO / RW image */ uint16_t dev_id; - uint32_t dev_rw_hash[PD_RW_HASH_SIZE/4]; + uint32_t dev_rw_hash[PD_RW_HASH_SIZE / 4]; enum ec_image current_image; } pe[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -713,8 +715,8 @@ static inline void send_data_msg(int port, enum tcpci_msg_type type, prl_send_data_msg(port, type, msg); } -static __maybe_unused inline void send_ext_data_msg( - int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg) +static __maybe_unused inline void +send_ext_data_msg(int port, enum tcpci_msg_type type, enum pd_ext_msg_type msg) { /* Clear any previous TX status before sending a new message */ PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE); @@ -744,15 +746,15 @@ static void init_cable_rev(int port) * also be PD 2.0 */ if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) { - /* - * If the cable supports PD 3.0, but the port partner supports PD 2.0, - * redo the cable discover with PD 2.0 - */ + /* + * If the cable supports PD 3.0, but the port partner supports + * PD 2.0, redo the cable discover with PD 2.0 + */ if (prl_get_rev(port, TCPCI_MSG_SOP_PRIME) == PD_REV30 && pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) == - PD_DISC_COMPLETE) { + PD_DISC_COMPLETE) { pd_set_identity_discovery(port, TCPCI_MSG_SOP_PRIME, - PD_DISC_NEEDED); + PD_DISC_NEEDED); } set_cable_rev(port, PD_REV20); } @@ -850,8 +852,8 @@ void pe_run(int port, int evt, int en) DPM_REQUEST_HARD_RESET_SEND); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); } else { - pe_set_dpm_curr_request(port, - DPM_REQUEST_HARD_RESET_SEND); + pe_set_dpm_curr_request( + port, DPM_REQUEST_HARD_RESET_SEND); pe_set_hard_reset(port); } } @@ -864,7 +866,7 @@ void pe_run(int port, int evt, int en) * make sure to handle it immediately. */ if (IS_ENABLED(CONFIG_USB_PD_REV30) && - PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) { + PE_CHK_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED)) { PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_SIGNALED); set_state_pe(port, PE_FRS_SNK_SRC_START_AMS); } @@ -968,13 +970,13 @@ static void pe_set_frs_enable(int port, int enable) pd_set_frs_enable(port, enable); if (enable) { - int curr_limit = *pd_get_snk_caps(port) - & PDO_FIXED_FRS_CURR_MASK; + int curr_limit = *pd_get_snk_caps(port) & + PDO_FIXED_FRS_CURR_MASK; - typec_select_src_current_limit_rp(port, - curr_limit == - PDO_FIXED_FRS_CURR_3A0_AT_5V ? - TYPEC_RP_3A0 : TYPEC_RP_1A5); + typec_select_src_current_limit_rp( + port, curr_limit == PDO_FIXED_FRS_CURR_3A0_AT_5V ? + TYPEC_RP_3A0 : + TYPEC_RP_1A5); PE_SET_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED); } else { PE_CLR_FLAG(port, PE_FLAGS_FAST_ROLE_SWAP_ENABLED); @@ -1026,7 +1028,7 @@ void pe_set_snk_caps(int port, int cnt, uint32_t *snk_caps) memcpy(pe[port].snk_caps, snk_caps, sizeof(uint32_t) * cnt); } -const uint32_t * const pd_get_snk_caps(int port) +const uint32_t *const pd_get_snk_caps(int port) { return pe[port].snk_caps; } @@ -1066,12 +1068,12 @@ static bool pe_can_send_sop_prime(int port) if (PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT)) { if (prl_get_rev(port, TCPCI_MSG_SOP) == PD_REV20) return tc_is_vconn_src(port) && - pe[port].data_role == PD_ROLE_DFP; + pe[port].data_role == PD_ROLE_DFP; else return tc_is_vconn_src(port); } else { return tc_is_vconn_src(port) && - pe[port].power_role == PD_ROLE_SOURCE; + pe[port].power_role == PD_ROLE_SOURCE; } } else { return false; @@ -1146,9 +1148,9 @@ static bool pe_check_outgoing_discard(int port) * Version 2.0 Specification. */ if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED) && - PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { + PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { enum tcpci_msg_type sop = - PD_HEADER_GET_SOP(rx_emsg[port].header); + PD_HEADER_GET_SOP(rx_emsg[port].header); PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED); PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); @@ -1190,28 +1192,26 @@ void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type) * TODO(b/150774779): TCPMv2: Improve pe_error documentation */ if ((get_state_pe(port) == PE_SRC_SEND_CAPABILITIES || - get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY || - get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP || - get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON || - get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON || - get_state_pe(port) == PE_SRC_DISABLED || - get_state_pe(port) == PE_SRC_DISCOVERY || - get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET || - get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) || - (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && - (get_state_pe(port) == PE_UDR_SEND_DATA_RESET || - get_state_pe(port) == PE_UDR_DATA_RESET_RECEIVED || - get_state_pe(port) == PE_UDR_TURN_OFF_VCONN || - get_state_pe(port) == PE_UDR_SEND_PS_RDY || - get_state_pe(port) == - PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE || - get_state_pe(port) == PE_DDR_SEND_DATA_RESET || - get_state_pe(port) == PE_DDR_DATA_RESET_RECEIVED || - get_state_pe(port) == PE_DDR_WAIT_FOR_VCONN_OFF || - get_state_pe(port) == PE_DDR_PERFORM_DATA_RESET)) || - (pe_in_frs_mode(port) && - get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP) - ) { + get_state_pe(port) == PE_SRC_TRANSITION_SUPPLY || + get_state_pe(port) == PE_PRS_SNK_SRC_EVALUATE_SWAP || + get_state_pe(port) == PE_PRS_SNK_SRC_SOURCE_ON || + get_state_pe(port) == PE_PRS_SRC_SNK_WAIT_SOURCE_ON || + get_state_pe(port) == PE_SRC_DISABLED || + get_state_pe(port) == PE_SRC_DISCOVERY || + get_state_pe(port) == PE_VCS_CBL_SEND_SOFT_RESET || + get_state_pe(port) == PE_VDM_IDENTITY_REQUEST_CBL) || + (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && + (get_state_pe(port) == PE_UDR_SEND_DATA_RESET || + get_state_pe(port) == PE_UDR_DATA_RESET_RECEIVED || + get_state_pe(port) == PE_UDR_TURN_OFF_VCONN || + get_state_pe(port) == PE_UDR_SEND_PS_RDY || + get_state_pe(port) == PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE || + get_state_pe(port) == PE_DDR_SEND_DATA_RESET || + get_state_pe(port) == PE_DDR_DATA_RESET_RECEIVED || + get_state_pe(port) == PE_DDR_WAIT_FOR_VCONN_OFF || + get_state_pe(port) == PE_DDR_PERFORM_DATA_RESET)) || + (pe_in_frs_mode(port) && + get_state_pe(port) == PE_PRS_SNK_SRC_SEND_SWAP)) { PE_SET_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); task_wake(PD_PORT_TO_TASK_ID(port)); return; @@ -1234,10 +1234,10 @@ void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type) */ /* All error types besides transmit errors are Protocol Errors. */ if ((e != ERR_TCH_XMIT && - !PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS)) - || e == ERR_TCH_XMIT - || (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) && - type == TCPCI_MSG_SOP)) { + !PE_CHK_FLAG(port, PE_FLAGS_INTERRUPTIBLE_AMS)) || + e == ERR_TCH_XMIT || + (!PE_CHK_FLAG(port, PE_FLAGS_EXPLICIT_CONTRACT) && + type == TCPCI_MSG_SOP)) { pe_send_soft_reset(port, type); } /* @@ -1262,7 +1262,7 @@ void pe_got_soft_reset(int port) } __overridable bool pd_can_charge_from_device(int port, const int pdo_cnt, - const uint32_t *pdos) + const uint32_t *pdos) { /* * Don't attempt to charge from a device we have no SrcCaps from. Or, if @@ -1292,9 +1292,7 @@ __overridable bool pd_can_charge_from_device(int port, const int pdo_cnt, * Get max power that the partner offers (not necessarily what * this board will request) */ - pd_find_pdo_index(pdo_cnt, pdos, - PD_REV3_MAX_VOLTAGE, - &max_pdo); + pd_find_pdo_index(pdo_cnt, pdos, PD_REV3_MAX_VOLTAGE, &max_pdo); pd_extract_pdo_power(max_pdo, &max_ma, &max_mv, &unused); max_mw = max_ma * max_mv / 1000; @@ -1351,14 +1349,15 @@ void pe_message_sent(int port) } void pd_send_vdm(int port, uint32_t vid, int cmd, const uint32_t *data, - int count) + int count) { /* Copy VDM Header */ pe[port].vdm_data[0] = - VDO(vid, ((vid & USB_SID_PD) == USB_SID_PD) ? 1 : - (PD_VDO_CMD(cmd) <= CMD_ATTENTION), - VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) | - cmd); + VDO(vid, + ((vid & USB_SID_PD) == USB_SID_PD) ? + 1 : + (PD_VDO_CMD(cmd) <= CMD_ATTENTION), + VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)) | cmd); /* * Copy VDOs after the VDM Header. Note that the count refers to VDO @@ -1485,21 +1484,21 @@ static void pe_update_waiting_batt_flag(void) * flag and perform Hard Reset. */ PE_CLR_FLAG(i, PE_FLAGS_SNK_WAITING_BATT); - CPRINTS("C%d: Battery has enough charge (%d%%) " \ - "to withstand a hard reset", i, batt_soc); + CPRINTS("C%d: Battery has enough charge (%d%%) " + "to withstand a hard reset", + i, batt_soc); pd_dpm_request(i, DPM_REQUEST_HARD_RESET_SEND); } } } DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, pe_update_waiting_batt_flag, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); #endif /* * Private functions */ -static void pe_set_dpm_curr_request(const int port, - const int request) +static void pe_set_dpm_curr_request(const int port, const int request) { PE_CLR_DPM_REQUEST(port, request); pe[port].dpm_curr_request = request; @@ -1528,27 +1527,23 @@ test_export_static enum usb_pe_state get_state_pe(const int port) static bool common_src_snk_dpm_requests(int port) { if (IS_ENABLED(CONFIG_USBC_VCONN) && - PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) { + PE_CHK_DPM_REQUEST(port, DPM_REQUEST_VCONN_SWAP)) { pe_set_dpm_curr_request(port, DPM_REQUEST_VCONN_SWAP); set_state_pe(port, PE_VCS_SEND_SWAP); return true; - } else if (PE_CHK_DPM_REQUEST(port, - DPM_REQUEST_BIST_TX)) { + } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_BIST_TX)) { pe_set_dpm_curr_request(port, DPM_REQUEST_BIST_TX); set_state_pe(port, PE_BIST_TX); return true; - } else if (PE_CHK_DPM_REQUEST(port, - DPM_REQUEST_SNK_STARTUP)) { + } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SNK_STARTUP)) { pe_set_dpm_curr_request(port, DPM_REQUEST_SNK_STARTUP); set_state_pe(port, PE_SNK_STARTUP); return true; - } else if (PE_CHK_DPM_REQUEST(port, - DPM_REQUEST_SRC_STARTUP)) { + } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SRC_STARTUP)) { pe_set_dpm_curr_request(port, DPM_REQUEST_SRC_STARTUP); set_state_pe(port, PE_SRC_STARTUP); return true; - } else if (PE_CHK_DPM_REQUEST(port, - DPM_REQUEST_SOFT_RESET_SEND)) { + } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOFT_RESET_SEND)) { pe_set_dpm_curr_request(port, DPM_REQUEST_SOFT_RESET_SEND); /* Currently only support sending soft reset to SOP */ pe_send_soft_reset(port, TCPCI_MSG_SOP); @@ -1588,14 +1583,13 @@ static bool common_src_snk_dpm_requests(int port) dpm_set_mode_exit_request(port); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SNK_CAPS)) { - pe_set_dpm_curr_request(port, - DPM_REQUEST_GET_SNK_CAPS); + pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SNK_CAPS); set_state_pe(port, PE_DR_GET_SINK_CAP); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND)) { pe_set_dpm_curr_request(port, - DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND); + DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND); pe[port].tx_type = TCPCI_MSG_SOP_PRIME; set_state_pe(port, PE_VCS_CBL_SEND_SOFT_RESET); return true; @@ -1612,7 +1606,7 @@ static bool common_src_snk_dpm_requests(int port) set_state_pe(port, PE_DRS_SEND_SWAP); return true; } else if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && - PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) { + PE_CHK_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET)) { if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) { PE_CLR_DPM_REQUEST(port, DPM_REQUEST_DATA_RESET); dpm_data_reset_complete(port); @@ -1635,7 +1629,7 @@ static bool common_src_snk_dpm_requests(int port) set_state_pe(port, PE_GET_REVISION); return true; } else if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && - PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) { + PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT)) { if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) { PE_CLR_DPM_REQUEST(port, DPM_REQUEST_SEND_ALERT); return false; @@ -1645,7 +1639,6 @@ static bool common_src_snk_dpm_requests(int port) return true; } - return false; } @@ -1664,9 +1657,9 @@ static bool source_dpm_requests(int port) * DPM_REQURST_FRS_DET_DISABLE */ PE_CLR_DPM_REQUEST(port, DPM_REQUEST_NEW_POWER_LEVEL | - DPM_REQUEST_SOURCE_CAP | - DPM_REQUEST_FRS_DET_ENABLE | - DPM_REQUEST_FRS_DET_DISABLE); + DPM_REQUEST_SOURCE_CAP | + DPM_REQUEST_FRS_DET_ENABLE | + DPM_REQUEST_FRS_DET_DISABLE); if (pe[port].dpm_request) { uint32_t dpm_request = pe[port].dpm_request; @@ -1678,8 +1671,7 @@ static bool source_dpm_requests(int port) set_state_pe(port, PE_PRS_SRC_SNK_SEND_SWAP); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN)) { - pe_set_dpm_curr_request(port, - DPM_REQUEST_GOTO_MIN); + pe_set_dpm_curr_request(port, DPM_REQUEST_GOTO_MIN); set_state_pe(port, PE_SRC_TRANSITION_SUPPLY); return true; } else if (PE_CHK_DPM_REQUEST(port, @@ -1689,21 +1681,18 @@ static bool source_dpm_requests(int port) set_state_pe(port, PE_SRC_SEND_CAPABILITIES); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_GET_SRC_CAPS)) { - pe_set_dpm_curr_request(port, - DPM_REQUEST_GET_SRC_CAPS); + pe_set_dpm_curr_request(port, DPM_REQUEST_GET_SRC_CAPS); set_state_pe(port, PE_DR_SRC_GET_SOURCE_CAP); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SEND_PING)) { - pe_set_dpm_curr_request(port, - DPM_REQUEST_SEND_PING); + pe_set_dpm_curr_request(port, DPM_REQUEST_SEND_PING); set_state_pe(port, PE_SRC_PING); return true; } else if (common_src_snk_dpm_requests(port)) { return true; } - CPRINTF("Unhandled DPM Request %x received\n", - dpm_request); + CPRINTF("Unhandled DPM Request %x received\n", dpm_request); PE_CLR_DPM_REQUEST(port, dpm_request); PE_CLR_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS); } @@ -1724,8 +1713,8 @@ static bool sink_dpm_requests(int port) * DPM_REQUEST_SEND_PING */ PE_CLR_DPM_REQUEST(port, DPM_REQUEST_GOTO_MIN | - DPM_REQUEST_SRC_CAP_CHANGE | - DPM_REQUEST_SEND_PING); + DPM_REQUEST_SRC_CAP_CHANGE | + DPM_REQUEST_SEND_PING); if (pe[port].dpm_request) { uint32_t dpm_request = pe[port].dpm_request; @@ -1737,8 +1726,7 @@ static bool sink_dpm_requests(int port) set_state_pe(port, PE_PRS_SNK_SRC_SEND_SWAP); return true; } else if (PE_CHK_DPM_REQUEST(port, DPM_REQUEST_SOURCE_CAP)) { - pe_set_dpm_curr_request(port, - DPM_REQUEST_SOURCE_CAP); + pe_set_dpm_curr_request(port, DPM_REQUEST_SOURCE_CAP); set_state_pe(port, PE_SNK_GET_SOURCE_CAP); return true; } else if (PE_CHK_DPM_REQUEST(port, @@ -1785,13 +1773,12 @@ static void print_current_state(const int port) { const char *mode = ""; - if (IS_ENABLED(CONFIG_USB_PD_REV30) && - pe_in_frs_mode(port)) + if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port)) mode = " FRS-MODE"; if (IS_ENABLED(USB_PD_DEBUG_LABELS)) CPRINTS_L1("C%d: %s%s", port, - pe_state_names[get_state_pe(port)], mode); + pe_state_names[get_state_pe(port)], mode); else CPRINTS("C%d: pe-st%d", port, get_state_pe(port)); } @@ -1827,20 +1814,20 @@ static void pe_send_request_msg(int port) * might need adjusting. */ if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) && - is_vpd_ct_supported(port)) { - union vpd_vdo vpd = pd_get_am_discovery(port, - TCPCI_MSG_SOP_PRIME)->identity.product_t1.vpd; + is_vpd_ct_supported(port)) { + union vpd_vdo vpd = + pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME) + ->identity.product_t1.vpd; /* The raw vpd_vdo is passed to pd_build_request */ vpd_vdo = vpd.raw_value; } /* Build and send request RDO */ - pd_build_request(vpd_vdo, &rdo, &curr_limit, - &supply_voltage, port); + pd_build_request(vpd_vdo, &rdo, &curr_limit, &supply_voltage, port); - CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo), - supply_voltage, curr_limit); + CPRINTF("C%d: Req [%d] %dmV %dmA", port, RDO_POS(rdo), supply_voltage, + curr_limit); if (rdo & RDO_CAP_MISMATCH) CPRINTF(" Mismatch"); CPRINTF("\n"); @@ -1941,8 +1928,9 @@ __maybe_unused static bool pe_attempt_port_discovery(int port) return false; /* Apply Port Discovery DR Swap Policy */ - if (port_discovery_dr_swap_policy(port, pe[port].data_role, - PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) { + if (port_discovery_dr_swap_policy( + port, pe[port].data_role, + PE_CHK_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP))) { PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS); PE_CLR_FLAG(port, PE_FLAGS_DR_SWAP_TO_DFP); set_state_pe(port, PE_DRS_SEND_SWAP); @@ -1951,8 +1939,8 @@ __maybe_unused static bool pe_attempt_port_discovery(int port) /* Apply Port Discovery VCONN Swap Policy */ if (IS_ENABLED(CONFIG_USBC_VCONN) && - port_discovery_vconn_swap_policy(port, - PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) { + port_discovery_vconn_swap_policy( + port, PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON))) { PE_SET_FLAG(port, PE_FLAGS_LOCALLY_INITIATED_AMS); PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_TO_ON); set_state_pe(port, PE_VCS_SEND_SWAP); @@ -1971,36 +1959,35 @@ __maybe_unused static bool pe_attempt_port_discovery(int port) */ if (pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) { if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) == - PD_DISC_NEEDED) { + PD_DISC_NEEDED) { pe[port].tx_type = TCPCI_MSG_SOP_PRIME; set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL); return true; } else if (pd_get_identity_discovery(port, TCPCI_MSG_SOP) == - PD_DISC_NEEDED && - pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) { + PD_DISC_NEEDED && + pe_can_send_sop_vdm(port, CMD_DISCOVER_IDENT)) { pe[port].tx_type = TCPCI_MSG_SOP; - set_state_pe(port, - PE_INIT_PORT_VDM_IDENTITY_REQUEST); + set_state_pe(port, PE_INIT_PORT_VDM_IDENTITY_REQUEST); return true; } else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP) == - PD_DISC_NEEDED && - pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) { + PD_DISC_NEEDED && + pe_can_send_sop_vdm(port, CMD_DISCOVER_SVID)) { pe[port].tx_type = TCPCI_MSG_SOP; set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST); return true; } else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP) == - PD_DISC_NEEDED && - pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) { + PD_DISC_NEEDED && + pe_can_send_sop_vdm(port, CMD_DISCOVER_MODES)) { pe[port].tx_type = TCPCI_MSG_SOP; set_state_pe(port, PE_INIT_VDM_MODES_REQUEST); return true; - } else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME) - == PD_DISC_NEEDED) { + } else if (pd_get_svids_discovery(port, TCPCI_MSG_SOP_PRIME) == + PD_DISC_NEEDED) { pe[port].tx_type = TCPCI_MSG_SOP_PRIME; set_state_pe(port, PE_INIT_VDM_SVIDS_REQUEST); return true; } else if (pd_get_modes_discovery(port, TCPCI_MSG_SOP_PRIME) == - PD_DISC_NEEDED) { + PD_DISC_NEEDED) { pe[port].tx_type = TCPCI_MSG_SOP_PRIME; set_state_pe(port, PE_INIT_VDM_MODES_REQUEST); return true; @@ -2010,8 +1997,8 @@ __maybe_unused static bool pe_attempt_port_discovery(int port) return false; } -bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, - uint32_t *vdm, uint32_t vdo_cnt) +bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm, + uint32_t vdo_cnt) { if (vdo_cnt < VDO_HDR_SIZE || vdo_cnt > VDO_MAX_SIZE) return false; @@ -2024,7 +2011,7 @@ bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, } int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash, - uint32_t current_image) + uint32_t current_image) { pe[port].dev_id = dev_id; memcpy(pe[port].dev_rw_hash, rw_hash, PD_RW_HASH_SIZE); @@ -2048,7 +2035,7 @@ int pd_dev_store_rw_hash(int port, uint16_t dev_id, uint32_t *rw_hash, } void pd_dev_get_rw_hash(int port, uint16_t *dev_id, uint8_t *rw_hash, - uint32_t *current_image) + uint32_t *current_image) { *dev_id = pe[port].dev_id; *current_image = pe[port].current_image; @@ -2089,7 +2076,7 @@ static void pe_update_wait_and_add_jitter_timer(int port) pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER)) { pd_timer_enable(port, PE_TIMER_WAIT_AND_ADD_JITTER, SRC_SNK_READY_HOLD_OFF_US + - (get_time().le.lo & 0xf) * 23 * MSEC); + (get_time().le.lo & 0xf) * 23 * MSEC); } } @@ -2273,8 +2260,7 @@ static void pe_src_startup_entry(int port) /* Request partner sink caps if a feature requires them */ if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) || - CONFIG_USB_PD_3A_PORTS > 0 || - IS_ENABLED(CONFIG_USB_PD_FRS)) + CONFIG_USB_PD_3A_PORTS > 0 || IS_ENABLED(CONFIG_USB_PD_FRS)) pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS); /* @@ -2283,7 +2269,6 @@ static void pe_src_startup_entry(int port) * revision 3.0 */ pd_dpm_request(port, DPM_REQUEST_GET_REVISION); - } } @@ -2351,10 +2336,12 @@ static void pe_src_discovery_run(int port) * contract in place. If it has been discovered, notify * the AP. */ - if (pd_get_identity_discovery( - port, TCPCI_MSG_SOP_PRIME) == PD_DISC_COMPLETE) { + if (pd_get_identity_discovery(port, + TCPCI_MSG_SOP_PRIME) == + PD_DISC_COMPLETE) { pd_notify_event( - port, PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + port, + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } set_state_pe(port, PE_SRC_DISABLED); @@ -2368,11 +2355,11 @@ static void pe_src_discovery_run(int port) * requests properly. */ if (pd_get_identity_discovery(port, TCPCI_MSG_SOP_PRIME) == - PD_DISC_NEEDED - && pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY) - && pe_can_send_sop_prime(port) - && (pe[port].discover_identity_counter < - N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) { + PD_DISC_NEEDED && + pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY) && + pe_can_send_sop_prime(port) && + (pe[port].discover_identity_counter < + N_DISCOVER_IDENTITY_PRECONTRACT_LIMIT)) { pe[port].tx_type = TCPCI_MSG_SOP_PRIME; set_state_pe(port, PE_VDM_IDENTITY_REQUEST_CBL); return; @@ -2462,15 +2449,14 @@ static void pe_src_send_capabilities_run(int port) * Request Message Received? */ if (PD_HEADER_CNT(rx_emsg[port].header) > 0 && - PD_HEADER_TYPE(rx_emsg[port].header) == - PD_DATA_REQUEST) { - + PD_HEADER_TYPE(rx_emsg[port].header) == PD_DATA_REQUEST) { /* * Set to highest revision supported by both * ports. */ prl_set_rev(port, TCPCI_MSG_SOP, - MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header))); + MIN(PD_REVISION, + PD_HEADER_REV(rx_emsg[port].header))); init_cable_rev(port); @@ -2641,7 +2627,7 @@ static void pe_src_transition_supply_run(int port) if (!pe_is_explicit_contract(port)) { PE_SET_FLAG(port, PE_FLAGS_FIRST_MSG); pd_timer_disable(port, - PE_TIMER_WAIT_AND_ADD_JITTER); + PE_TIMER_WAIT_AND_ADD_JITTER); } /* NOTE: Second pass through this code block */ @@ -2701,13 +2687,13 @@ static void extended_message_not_supported(int port, uint32_t *payload) uint16_t ext_header = GET_EXT_HEADER(*payload); if (IS_ENABLED(CONFIG_USB_PD_REV30) && - !IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && - PD_EXT_HEADER_CHUNKED(ext_header) && - PD_EXT_HEADER_DATA_SIZE(ext_header) > - PD_MAX_EXTENDED_MSG_CHUNK_LEN) { - set_state_pe(port, - pe[port].power_role == PD_ROLE_SOURCE ? - PE_SRC_CHUNK_RECEIVED : PE_SNK_CHUNK_RECEIVED); + !IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && + PD_EXT_HEADER_CHUNKED(ext_header) && + PD_EXT_HEADER_DATA_SIZE(ext_header) > + PD_MAX_EXTENDED_MSG_CHUNK_LEN) { + set_state_pe(port, pe[port].power_role == PD_ROLE_SOURCE ? + PE_SRC_CHUNK_RECEIVED : + PE_SNK_CHUNK_RECEIVED); return; } @@ -2774,13 +2760,14 @@ static void pe_src_ready_run(int port) break; case PD_DATA_VENDOR_DEF: if (PD_HEADER_TYPE(rx_emsg[port].header) == - PD_DATA_VENDOR_DEF) { + PD_DATA_VENDOR_DEF) { if (PD_VDO_SVDM(*payload)) { set_state_pe(port, - PE_VDM_RESPONSE); + PE_VDM_RESPONSE); } else - set_state_pe(port, - PE_HANDLE_CUSTOM_VDM_REQUEST); + set_state_pe( + port, + PE_HANDLE_CUSTOM_VDM_REQUEST); } return; case PD_DATA_BIST: @@ -2810,7 +2797,7 @@ static void pe_src_ready_run(int port) break; case PD_CTRL_PR_SWAP: set_state_pe(port, - PE_PRS_SRC_SNK_EVALUATE_SWAP); + PE_PRS_SRC_SNK_EVALUATE_SWAP); return; case PD_CTRL_DR_SWAP: if (PE_CHK_FLAG(port, @@ -2824,10 +2811,10 @@ static void pe_src_ready_run(int port) case PD_CTRL_VCONN_SWAP: if (IS_ENABLED(CONFIG_USBC_VCONN)) set_state_pe(port, - PE_VCS_EVALUATE_SWAP); + PE_VCS_EVALUATE_SWAP); else set_state_pe(port, - PE_SEND_NOT_SUPPORTED); + PE_SEND_NOT_SUPPORTED); return; /* * USB PD 3.0 6.8.1: @@ -2838,16 +2825,19 @@ static void pe_src_ready_run(int port) case PD_CTRL_REJECT: case PD_CTRL_WAIT: case PD_CTRL_PS_RDY: - pe_send_soft_reset(port, - PD_HEADER_GET_SOP(rx_emsg[port].header)); + pe_send_soft_reset( + port, PD_HEADER_GET_SOP( + rx_emsg[port].header)); return; #ifdef CONFIG_USB_PD_DATA_RESET_MSG case PD_CTRL_DATA_RESET: if (pe[port].data_role == PD_ROLE_DFP) - set_state_pe(port, + set_state_pe( + port, PE_DDR_DATA_RESET_RECEIVED); else - set_state_pe(port, + set_state_pe( + port, PE_UDR_DATA_RESET_RECEIVED); return; #endif /* CONFIG_USB_PD_DATA_RESET_MSG */ @@ -2856,10 +2846,11 @@ static void pe_src_ready_run(int port) set_state_pe(port, PE_GIVE_STATUS); return; #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ - /* - * Receiving an unknown or unsupported message - * shall be responded to with a not supported message. - */ + /* + * Receiving an unknown or unsupported message + * shall be responded to with a not supported + * message. + */ default: set_state_pe(port, PE_SEND_NOT_SUPPORTED); @@ -2889,7 +2880,6 @@ static void pe_src_ready_run(int port) if (pd_timer_is_disabled(port, PE_TIMER_WAIT_AND_ADD_JITTER) || pd_timer_is_expired(port, PE_TIMER_WAIT_AND_ADD_JITTER)) { - PE_CLR_FLAG(port, PE_FLAGS_FIRST_MSG); pd_timer_disable(port, PE_TIMER_WAIT_AND_ADD_JITTER); @@ -2919,7 +2909,7 @@ static void pe_src_disabled_entry(int port) print_current_state(port); if ((get_usb_pd_cable_type(port) == IDH_PTYPE_VPD) && - is_vpd_ct_supported(port)) { + is_vpd_ct_supported(port)) { /* * Inform the Device Policy Manager that a Charge-Through VCONN * Powered Device was detected. @@ -3009,10 +2999,9 @@ static void pe_src_hard_reset_entry(int port) pd_timer_enable(port, PE_TIMER_PS_HARD_RESET, PD_T_PS_HARD_RESET); /* Clear error flags */ - PE_CLR_MASK(port, - BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) | - BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | - BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN)); + PE_CLR_MASK(port, BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) | + BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | + BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN)); } static void pe_src_hard_reset_run(int port) @@ -3179,9 +3168,8 @@ static void pe_snk_startup_entry(int port) * Swap, then the Policy Engine Shall do the following: * - Send a Get_Sink_Cap Message */ - if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) || - CONFIG_USB_PD_3A_PORTS > 0 || - IS_ENABLED(CONFIG_USB_PD_FRS)) + if (IS_ENABLED(CONFIG_USB_PD_HOST_CMD) || CONFIG_USB_PD_3A_PORTS > 0 || + IS_ENABLED(CONFIG_USB_PD_FRS)) pd_dpm_request(port, DPM_REQUEST_GET_SNK_CAPS); /* @@ -3190,7 +3178,6 @@ static void pe_snk_startup_entry(int port) * revision 3.0 */ pd_dpm_request(port, DPM_REQUEST_GET_REVISION); - } static void pe_snk_startup_run(int port) @@ -3285,7 +3272,7 @@ static void pe_snk_evaluate_capability_entry(int port) /* Set to highest revision supported by both ports. */ prl_set_rev(port, TCPCI_MSG_SOP, - MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header))); + MIN(PD_REVISION, PD_HEADER_REV(rx_emsg[port].header))); init_cable_rev(port); @@ -3406,7 +3393,7 @@ static void pe_snk_select_capability_run(int port) * Reject or Wait Message Received */ else if (type == PD_CTRL_REJECT || - type == PD_CTRL_WAIT) { + type == PD_CTRL_WAIT) { if (type == PD_CTRL_WAIT) PE_SET_FLAG(port, PE_FLAGS_WAIT); @@ -3424,7 +3411,8 @@ static void pe_snk_select_capability_run(int port) * to PE_SNK_Wait_For_Capabilities */ else - set_state_pe(port, + set_state_pe( + port, PE_SNK_WAIT_FOR_CAPABILITIES); return; } @@ -3485,8 +3473,7 @@ static void pe_snk_transition_sink_run(int port) * PS_RDY message received */ if ((PD_HEADER_CNT(rx_emsg[port].header) == 0) && - (PD_HEADER_TYPE(rx_emsg[port].header) == - PD_CTRL_PS_RDY)) { + (PD_HEADER_TYPE(rx_emsg[port].header) == PD_CTRL_PS_RDY)) { /* * Set first message flag to trigger a wait and add * jitter delay when operating in PD2.0 mode. @@ -3509,8 +3496,8 @@ static void pe_snk_transition_sink_run(int port) * already available */ if (pd_get_snk_cap_cnt(port) > 0) - dpm_evaluate_sink_fixed_pdo(port, - *pd_get_snk_caps(port)); + dpm_evaluate_sink_fixed_pdo( + port, *pd_get_snk_caps(port)); set_state_pe(port, PE_SNK_READY); } else { @@ -3536,13 +3523,13 @@ static void pe_snk_transition_sink_run(int port) static void pe_snk_transition_sink_exit(int port) { /* Transition Sink's power supply to the new power level */ - pd_set_input_current_limit(port, - pe[port].curr_limit, pe[port].supply_voltage); + pd_set_input_current_limit(port, pe[port].curr_limit, + pe[port].supply_voltage); if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) /* Set ceiling based on what's negotiated */ - charge_manager_set_ceil(port, - CEIL_REQUESTOR_PD, pe[port].curr_limit); + charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, + pe[port].curr_limit); pd_timer_disable(port, PE_TIMER_PS_TRANSITION); @@ -3551,7 +3538,6 @@ static void pe_snk_transition_sink_exit(int port) dps_update_stabilized_time(port); } - /** * PE_SNK_Ready State */ @@ -3572,8 +3558,7 @@ static void pe_snk_ready_entry(int port) */ if (PE_CHK_FLAG(port, PE_FLAGS_WAIT)) { PE_CLR_FLAG(port, PE_FLAGS_WAIT); - pd_timer_enable(port, PE_TIMER_SINK_REQUEST, - PD_T_SINK_REQUEST); + pd_timer_enable(port, PE_TIMER_SINK_REQUEST, PD_T_SINK_REQUEST); } /* @@ -3617,18 +3602,18 @@ static void pe_snk_ready_run(int port) else if (cnt > 0) { switch (type) { case PD_DATA_SOURCE_CAP: - set_state_pe(port, - PE_SNK_EVALUATE_CAPABILITY); + set_state_pe(port, PE_SNK_EVALUATE_CAPABILITY); break; case PD_DATA_VENDOR_DEF: if (PD_HEADER_TYPE(rx_emsg[port].header) == - PD_DATA_VENDOR_DEF) { + PD_DATA_VENDOR_DEF) { if (PD_VDO_SVDM(*payload)) set_state_pe(port, - PE_VDM_RESPONSE); + PE_VDM_RESPONSE); else - set_state_pe(port, - PE_HANDLE_CUSTOM_VDM_REQUEST); + set_state_pe( + port, + PE_HANDLE_CUSTOM_VDM_REQUEST); } break; case PD_DATA_BIST: @@ -3659,30 +3644,32 @@ static void pe_snk_ready_run(int port) return; case PD_CTRL_PR_SWAP: set_state_pe(port, - PE_PRS_SNK_SRC_EVALUATE_SWAP); + PE_PRS_SNK_SRC_EVALUATE_SWAP); return; case PD_CTRL_DR_SWAP: if (PE_CHK_FLAG(port, PE_FLAGS_MODAL_OPERATION)) pe_set_hard_reset(port); else set_state_pe(port, - PE_DRS_EVALUATE_SWAP); + PE_DRS_EVALUATE_SWAP); return; case PD_CTRL_VCONN_SWAP: if (IS_ENABLED(CONFIG_USBC_VCONN)) set_state_pe(port, - PE_VCS_EVALUATE_SWAP); + PE_VCS_EVALUATE_SWAP); else set_state_pe(port, - PE_SEND_NOT_SUPPORTED); + PE_SEND_NOT_SUPPORTED); return; #ifdef CONFIG_USB_PD_DATA_RESET_MSG case PD_CTRL_DATA_RESET: if (pe[port].data_role == PD_ROLE_DFP) - set_state_pe(port, + set_state_pe( + port, PE_DDR_DATA_RESET_RECEIVED); else - set_state_pe(port, + set_state_pe( + port, PE_UDR_DATA_RESET_RECEIVED); return; #endif /* CONFIG_USB_PD_DATA_RESET_MSG */ @@ -3703,8 +3690,9 @@ static void pe_snk_ready_run(int port) case PD_CTRL_REJECT: case PD_CTRL_WAIT: case PD_CTRL_PS_RDY: - pe_send_soft_reset(port, - PD_HEADER_GET_SOP(rx_emsg[port].header)); + pe_send_soft_reset( + port, PD_HEADER_GET_SOP( + rx_emsg[port].header)); return; /* * Receiving an unknown or unsupported message @@ -3756,7 +3744,6 @@ static void pe_snk_ready_run(int port) /* No DPM requests; attempt mode entry/exit if needed */ dpm_run(port); - } } @@ -3777,7 +3764,7 @@ static void pe_snk_hard_reset_entry(int port) * Source is non-responsive. */ if (PE_CHK_FLAG(port, PE_FLAGS_SNK_WAIT_CAP_TIMEOUT) && - pe[port].hard_reset_counter > N_HARD_RESET_COUNT) { + pe[port].hard_reset_counter > N_HARD_RESET_COUNT) { set_state_pe(port, PE_SRC_DISABLED); return; } @@ -3797,13 +3784,13 @@ static void pe_snk_hard_reset_entry(int port) if (IS_ENABLED(CONFIG_BATTERY) && (battery_is_present() == BP_NO) && IS_ENABLED(CONFIG_CHARGE_MANAGER) && ((port == charge_manager_get_active_charge_port() || - (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) && + (charge_manager_get_active_charge_port() == CHARGE_PORT_NONE))) && system_get_reset_flags() & EC_RESET_FLAG_SYSJUMP) { CPRINTS("C%d: Disabling port to avoid brown out, " - "please reboot EC to enable port again", port); + "please reboot EC to enable port again", + port); set_state_pe(port, PE_SRC_DISABLED); return; - } #ifdef CONFIG_USB_PD_RESET_MIN_BATT_SOC @@ -3824,19 +3811,18 @@ static void pe_snk_hard_reset_entry(int port) if (batt_soc < CONFIG_USB_PD_RESET_MIN_BATT_SOC || battery_get_disconnect_state() != BATTERY_NOT_DISCONNECTED) { PE_SET_FLAG(port, PE_FLAGS_SNK_WAITING_BATT); - CPRINTS("C%d: Battery low %d%%! Stay in disabled state " \ - "until battery level reaches %d%%", port, batt_soc, - CONFIG_USB_PD_RESET_MIN_BATT_SOC); + CPRINTS("C%d: Battery low %d%%! Stay in disabled state " + "until battery level reaches %d%%", + port, batt_soc, CONFIG_USB_PD_RESET_MIN_BATT_SOC); set_state_pe(port, PE_SRC_DISABLED); return; } #endif - PE_CLR_MASK(port, - BIT(PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN) | - BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) | - BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | - BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN)); + PE_CLR_MASK(port, BIT(PE_FLAGS_SNK_WAIT_CAP_TIMEOUT_FN) | + BIT(PE_FLAGS_VDM_REQUEST_NAKED_FN) | + BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | + BIT(PE_FLAGS_VDM_REQUEST_BUSY_FN)); /* Request the generation of Hard Reset Signaling by the PHY Layer */ prl_execute_hard_reset(port); @@ -3853,11 +3839,11 @@ static void pe_snk_hard_reset_entry(int port) /* Transition Sink's power supply to the new power level */ pd_set_input_current_limit(port, pe[port].curr_limit, - pe[port].supply_voltage); + pe[port].supply_voltage); if (IS_ENABLED(CONFIG_CHARGE_MANAGER)) /* Set ceiling based on what's negotiated */ charge_manager_set_ceil(port, CEIL_REQUESTOR_PD, - pe[port].curr_limit); + pe[port].curr_limit); } } @@ -3964,8 +3950,8 @@ static void pe_send_soft_reset_run(int port) * unexpected incoming message type */ /* Send Soft Reset message */ - send_ctrl_msg(port, - pe[port].soft_reset_sop, PD_CTRL_SOFT_RESET); + send_ctrl_msg(port, pe[port].soft_reset_sop, + PD_CTRL_SOFT_RESET); return; } @@ -3999,10 +3985,9 @@ static void pe_send_soft_reset_run(int port) if ((ext == 0) && (cnt == 0) && (type == PD_CTRL_ACCEPT)) { if (pe[port].power_role == PD_ROLE_SINK) set_state_pe(port, - PE_SNK_WAIT_FOR_CAPABILITIES); + PE_SNK_WAIT_FOR_CAPABILITIES); else - set_state_pe(port, - PE_SRC_SEND_CAPABILITIES); + set_state_pe(port, PE_SRC_SEND_CAPABILITIES); return; } } @@ -4012,7 +3997,7 @@ static void pe_send_soft_reset_run(int port) * Response Timer Timeout or Protocol Layer or Protocol Error */ if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) || - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); pe_set_hard_reset(port); return; @@ -4035,7 +4020,7 @@ static void pe_soft_reset_entry(int port) send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT); } -static void pe_soft_reset_run(int port) +static void pe_soft_reset_run(int port) { if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) { PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE); @@ -4075,7 +4060,6 @@ static void pe_send_not_supported_run(int port) if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) { PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE); pe_set_ready_state(port); - } } @@ -4197,32 +4181,28 @@ static void pe_give_battery_cap_entry(int port) */ msg[BCDB_FULL_CAP] = 0xffff; - if (IS_ENABLED(HAS_TASK_HOSTCMD) && *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) { int design_volt, design_cap, full_cap; - design_volt = *(int *)host_get_memmap( - EC_MEMMAP_BATT_DVLT); - design_cap = *(int *)host_get_memmap( - EC_MEMMAP_BATT_DCAP); - full_cap = *(int *)host_get_memmap( - EC_MEMMAP_BATT_LFCC); + design_volt = + *(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT); + design_cap = + *(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP); + full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC); /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ msg[BCDB_DESIGN_CAP] = DIV_ROUND_NEAREST( - (design_cap * design_volt), - 100000); + (design_cap * design_volt), 100000); /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST( - (design_cap * full_cap), - 100000); + (design_cap * full_cap), 100000); } else { uint32_t v; uint32_t c; @@ -4234,24 +4214,19 @@ static void pe_give_battery_cap_entry(int port) * 10th of a Wh = Wh * 10 */ msg[BCDB_DESIGN_CAP] = - DIV_ROUND_NEAREST( - (c * v), - 100000); + DIV_ROUND_NEAREST((c * v), + 100000); } - if (battery_full_charge_capacity(&c) - == 0) { + if (battery_full_charge_capacity(&c) == 0) { /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ - msg[BCDB_FULL_CAP] = - DIV_ROUND_NEAREST( - (c * v), - 100000); + msg[BCDB_FULL_CAP] = DIV_ROUND_NEAREST( + (c * v), 100000); } } - } /* Valid battery selected */ msg[BCDB_BATT_TYPE] = 0; @@ -4307,24 +4282,23 @@ static void pe_give_battery_status_entry(int port) if (IS_ENABLED(HAS_TASK_HOSTCMD) && *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0) { v = *(int *)host_get_memmap( - EC_MEMMAP_BATT_DVLT); - c = *(int *)host_get_memmap( - EC_MEMMAP_BATT_CAP); + EC_MEMMAP_BATT_DVLT); + c = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP); /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ - *msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v), - 100000)); + *msg = BSDO_CAP( + DIV_ROUND_NEAREST((c * v), 100000)); } else if (battery_design_voltage(&v) == 0 && battery_remaining_capacity(&c) == 0) { /* * Wh = (c * v) / 1000000 * 10th of a Wh = Wh * 10 */ - *msg = BSDO_CAP(DIV_ROUND_NEAREST((c * v), - 100000)); + *msg = BSDO_CAP( + DIV_ROUND_NEAREST((c * v), 100000)); } /* Battery is present */ @@ -4398,7 +4372,6 @@ static void pe_give_status_run(int port) } } - /** * PE_SRC_Send_Source_Alert and * PE_SNK_Send_Sink_Alert @@ -4560,8 +4533,8 @@ static void pe_drs_send_swap_run(int port) set_state_pe(port, PE_DRS_CHANGE); return; } else if ((type == PD_CTRL_REJECT) || - (type == PD_CTRL_WAIT) || - (type == PD_CTRL_NOT_SUPPORTED)) { + (type == PD_CTRL_WAIT) || + (type == PD_CTRL_NOT_SUPPORTED)) { pe_set_ready_state(port); return; } @@ -4763,8 +4736,7 @@ static void pe_prs_src_snk_wait_source_on_run(int port) static void pe_prs_src_snk_wait_source_on_exit(int port) { pd_timer_disable(port, PE_TIMER_PS_SOURCE); - tc_pr_swap_complete(port, - PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)); + tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)); } /** @@ -4815,7 +4787,7 @@ static void pe_prs_src_snk_send_swap_run(int port) pe[port].src_snk_pr_swap_counter = 0; tc_request_power_swap(port); set_state_pe(port, - PE_PRS_SRC_SNK_TRANSITION_TO_OFF); + PE_PRS_SRC_SNK_TRANSITION_TO_OFF); } else if (type == PD_CTRL_REJECT) { pe[port].src_snk_pr_swap_counter = 0; set_state_pe(port, PE_SRC_READY); @@ -4823,7 +4795,7 @@ static void pe_prs_src_snk_send_swap_run(int port) if (pe[port].src_snk_pr_swap_counter < N_SNK_SRC_PR_SWAP_COUNT) { PE_SET_FLAG(port, - PE_FLAGS_WAITING_PR_SWAP); + PE_FLAGS_WAITING_PR_SWAP); pd_timer_enable(port, PE_TIMER_PR_SWAP_WAIT, PD_T_PR_SWAP_WAIT); @@ -4923,8 +4895,7 @@ static void pe_prs_snk_src_transition_to_off_entry(int port) { print_current_state(port); - if (!IS_ENABLED(CONFIG_USB_PD_REV30) || - !pe_in_frs_mode(port)) + if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port)) tc_snk_power_off(port); pd_timer_enable(port, PE_TIMER_PS_SOURCE, PD_T_PS_SOURCE_OFF); @@ -4991,8 +4962,7 @@ static void pe_prs_snk_src_assert_rp_run(int port) { /* Wait until TypeC is in the Attached.SRC state */ if (tc_is_attached_src(port)) { - if (!IS_ENABLED(CONFIG_USB_PD_REV30) || - !pe_in_frs_mode(port)) { + if (!IS_ENABLED(CONFIG_USB_PD_REV30) || !pe_in_frs_mode(port)) { /* Contract is invalid now */ pe_invalidate_explicit_contract(port); } @@ -5053,8 +5023,7 @@ static void pe_prs_snk_src_source_on_run(int port) static void pe_prs_snk_src_source_on_exit(int port) { pd_timer_disable(port, PE_TIMER_PS_SOURCE); - tc_pr_swap_complete(port, - PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)); + tc_pr_swap_complete(port, PE_CHK_FLAG(port, PE_FLAGS_PR_SWAP_COMPLETE)); } /** @@ -5077,11 +5046,9 @@ static void pe_prs_snk_src_send_swap_entry(int port) * Request the Protocol Layer to send a FR_Swap Message. */ if (IS_ENABLED(CONFIG_USB_PD_REV30)) { - send_ctrl_msg(port, - TCPCI_MSG_SOP, - pe_in_frs_mode(port) - ? PD_CTRL_FR_SWAP - : PD_CTRL_PR_SWAP); + send_ctrl_msg(port, TCPCI_MSG_SOP, + pe_in_frs_mode(port) ? PD_CTRL_FR_SWAP : + PD_CTRL_PR_SWAP); } else { send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_PR_SWAP); } @@ -5134,12 +5101,13 @@ static void pe_prs_snk_src_send_swap_run(int port) set_state_pe(port, PE_PRS_SNK_SRC_TRANSITION_TO_OFF); } else if ((type == PD_CTRL_REJECT) || - (type == PD_CTRL_WAIT)) { + (type == PD_CTRL_WAIT)) { if (IS_ENABLED(CONFIG_USB_PD_REV30)) - set_state_pe(port, - pe_in_frs_mode(port) - ? PE_WAIT_FOR_ERROR_RECOVERY - : PE_SNK_READY); + set_state_pe( + port, + pe_in_frs_mode(port) ? + PE_WAIT_FOR_ERROR_RECOVERY : + PE_SNK_READY); else set_state_pe(port, PE_SNK_READY); } @@ -5154,10 +5122,9 @@ static void pe_prs_snk_src_send_swap_run(int port) */ if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) { if (IS_ENABLED(CONFIG_USB_PD_REV30)) - set_state_pe(port, - pe_in_frs_mode(port) - ? PE_WAIT_FOR_ERROR_RECOVERY - : PE_SNK_READY); + set_state_pe(port, pe_in_frs_mode(port) ? + PE_WAIT_FOR_ERROR_RECOVERY : + PE_SNK_READY); else set_state_pe(port, PE_SNK_READY); return; @@ -5168,9 +5135,8 @@ static void pe_prs_snk_src_send_swap_run(int port) * has not been received). A soft reset Shall Not be initiated in * this case. */ - if (IS_ENABLED(CONFIG_USB_PD_REV30) && - pe_in_frs_mode(port) && - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + if (IS_ENABLED(CONFIG_USB_PD_REV30) && pe_in_frs_mode(port) && + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); } @@ -5436,10 +5402,10 @@ static enum vdm_response_result parse_vdm_response_common(int port) cnt = PD_HEADER_CNT(rx_emsg[port].header); ext = PD_HEADER_EXT(rx_emsg[port].header); - if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1 - && ext == 0) { + if (sop == pe[port].tx_type && type == PD_DATA_VENDOR_DEF && cnt >= 1 && + ext == 0) { if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_ACK && - cnt >= pe[port].vdm_ack_min_data_objects) { + cnt >= pe[port].vdm_ack_min_data_objects) { /* Handle ACKs in state-specific code. */ return VDM_RESULT_ACK; } else if (PD_VDO_CMDT(payload[0]) == CMDT_RSP_NAK) { @@ -5451,7 +5417,7 @@ static enum vdm_response_result parse_vdm_response_common(int port) * tVDMBusy */ CPRINTS("C%d: Partner BUSY, request will be retried", - port); + port); pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, PD_T_VDM_BUSY); @@ -5469,11 +5435,11 @@ static enum vdm_response_result parse_vdm_response_common(int port) * Partner gave us an incorrect size or command; mark discovery * as failed. */ - CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x", - port, rx_emsg[port].header, payload[0]); + CPRINTS("C%d: Unexpected VDM response: 0x%04x 0x%04x", port, + rx_emsg[port].header, payload[0]); return VDM_RESULT_NAK; } else if (sop == pe[port].tx_type && ext == 0 && cnt == 0 && - type == PD_CTRL_NOT_SUPPORTED) { + type == PD_CTRL_NOT_SUPPORTED) { /* * A NAK would be more expected here, but Not Supported is still * allowed with the same meaning. @@ -5504,16 +5470,16 @@ static void pe_vdm_send_request_entry(int port) if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME || pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) && - !tc_is_vconn_src(port) && port_discovery_vconn_swap_policy(port, - BIT(PE_FLAGS_VCONN_SWAP_TO_ON_FN))) { + !tc_is_vconn_src(port) && + port_discovery_vconn_swap_policy( + port, BIT(PE_FLAGS_VCONN_SWAP_TO_ON_FN))) { if (port_try_vconn_swap(port)) return; } /* All VDM sequences are Interruptible */ - PE_SET_MASK(port, - BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | - BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN)); + PE_SET_MASK(port, BIT(PE_FLAGS_LOCALLY_INITIATED_AMS_FN) | + BIT(PE_FLAGS_INTERRUPTIBLE_AMS_FN)); } static void pe_vdm_send_request_run(int port) @@ -5525,8 +5491,7 @@ static void pe_vdm_send_request_run(int port) /* Start no response timer */ /* TODO(b/155890173): Support DPM-supplied timeout */ - pd_timer_enable(port, PE_TIMER_VDM_RESPONSE, - PD_T_VDM_SNDR_RSP); + pd_timer_enable(port, PE_TIMER_VDM_RESPONSE, PD_T_VDM_SNDR_RSP); } if (PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { @@ -5544,8 +5509,7 @@ static void pe_vdm_send_request_run(int port) */ if (pd_timer_is_expired(port, PE_TIMER_VDM_RESPONSE)) { CPRINTF("VDM %s Response Timeout\n", - pe[port].tx_type == TCPCI_MSG_SOP ? - "Port" : "Cable"); + pe[port].tx_type == TCPCI_MSG_SOP ? "Port" : "Cable"); /* * Flag timeout so child state can mark appropriate discovery * item as failed. @@ -5593,8 +5557,8 @@ static void pe_vdm_identity_request_cbl_entry(int port) } msg[0] = VDO(USB_SID_PD, 1, - VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | - CMD_DISCOVER_IDENT); + VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | + CMD_DISCOVER_IDENT); tx_emsg[port].len = sizeof(uint32_t); send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF); @@ -5611,7 +5575,7 @@ static void pe_vdm_identity_request_cbl_entry(int port) static void pe_vdm_identity_request_cbl_run(int port) { /* Retrieve the message information */ - uint32_t *payload = (uint32_t *) rx_emsg[port].buf; + uint32_t *payload = (uint32_t *)rx_emsg[port].buf; int sop = PD_HEADER_GET_SOP(rx_emsg[port].header); uint8_t type = PD_HEADER_TYPE(rx_emsg[port].header); uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header); @@ -5644,9 +5608,8 @@ static void pe_vdm_identity_request_cbl_run(int port) * state. */ if (get_last_state_pe(port) == PE_SRC_DISCOVERY && - (sop != pe[port].tx_type || - type != PD_DATA_VENDOR_DEF || - cnt == 0 || ext != 0)) { + (sop != pe[port].tx_type || type != PD_DATA_VENDOR_DEF || + cnt == 0 || ext != 0)) { /* * Unexpected non-VDM received: Before an explicit * contract, an unexpected message shall generate a soft @@ -5710,10 +5673,9 @@ static void pe_vdm_identity_request_cbl_exit(int port) * Not send any further SOP’/SOP’’ Messages. */ if (pe[port].discover_identity_counter >= N_DISCOVER_IDENTITY_COUNT) - pd_set_identity_discovery(port, pe[port].tx_type, - PD_DISC_FAIL); + pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL); else if (pe[port].discover_identity_counter == - N_DISCOVER_IDENTITY_PD3_0_LIMIT) + N_DISCOVER_IDENTITY_PD3_0_LIMIT) /* * Downgrade to PD 2.0 if the partner hasn't replied before * all retries are exhausted in case the cable is @@ -5724,8 +5686,9 @@ static void pe_vdm_identity_request_cbl_exit(int port) /* * Set discover identity timer unless BUSY case already did so. */ - if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_NEEDED - && pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) { + if (pd_get_identity_discovery(port, pe[port].tx_type) == + PD_DISC_NEEDED && + pd_timer_is_expired(port, PE_TIMER_DISCOVER_IDENTITY)) { /* * The tDiscoverIdentity timer is used during an explicit * contract when discovering whether a cable is PD capable. @@ -5735,17 +5698,18 @@ static void pe_vdm_identity_request_cbl_exit(int port) * power the SOP' responder from VBUS instead of VCONN. */ pd_timer_enable(port, PE_TIMER_DISCOVER_IDENTITY, - pe_is_explicit_contract(port) - ? PD_T_DISCOVER_IDENTITY - : PE_T_DISCOVER_IDENTITY_NO_CONTRACT); + pe_is_explicit_contract(port) ? + PD_T_DISCOVER_IDENTITY : + PE_T_DISCOVER_IDENTITY_NO_CONTRACT); } /* Do not attempt further discovery if identity discovery failed. */ if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) { pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL); - pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ? - PD_STATUS_EVENT_SOP_DISC_DONE : - PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + pd_notify_event(port, + pe[port].tx_type == TCPCI_MSG_SOP ? + PD_STATUS_EVENT_SOP_DISC_DONE : + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } } @@ -5764,8 +5728,8 @@ static void pe_init_port_vdm_identity_request_entry(int port) print_current_state(port); msg[0] = VDO(USB_SID_PD, 1, - VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | - CMD_DISCOVER_IDENT); + VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | + CMD_DISCOVER_IDENT); tx_emsg[port].len = sizeof(uint32_t); send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF); @@ -5792,7 +5756,7 @@ static void pe_init_port_vdm_identity_request_run(int port) break; case VDM_RESULT_ACK: { /* Retrieve the message information. */ - uint32_t *payload = (uint32_t *) rx_emsg[port].buf; + uint32_t *payload = (uint32_t *)rx_emsg[port].buf; int sop = PD_HEADER_GET_SOP(rx_emsg[port].header); uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header); @@ -5800,7 +5764,7 @@ static void pe_init_port_vdm_identity_request_run(int port) dfp_consume_identity(port, sop, cnt, payload); break; - } + } case VDM_RESULT_NAK: /* PE_INIT_PORT_VDM_IDENTITY_NAKed embedded here */ pd_set_identity_discovery(port, pe[port].tx_type, PD_DISC_FAIL); @@ -5830,9 +5794,10 @@ static void pe_init_port_vdm_identity_request_exit(int port) /* Do not attempt further discovery if identity discovery failed. */ if (pd_get_identity_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) { pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL); - pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ? - PD_STATUS_EVENT_SOP_DISC_DONE : - PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + pd_notify_event(port, + pe[port].tx_type == TCPCI_MSG_SOP ? + PD_STATUS_EVENT_SOP_DISC_DONE : + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } } @@ -5859,8 +5824,8 @@ static void pe_init_vdm_svids_request_entry(int port) } msg[0] = VDO(USB_SID_PD, 1, - VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | - CMD_DISCOVER_SVID); + VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | + CMD_DISCOVER_SVID); tx_emsg[port].len = sizeof(uint32_t); send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF); @@ -5887,14 +5852,14 @@ static void pe_init_vdm_svids_request_run(int port) break; case VDM_RESULT_ACK: { /* Retrieve the message information. */ - uint32_t *payload = (uint32_t *) rx_emsg[port].buf; + uint32_t *payload = (uint32_t *)rx_emsg[port].buf; int sop = PD_HEADER_GET_SOP(rx_emsg[port].header); uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header); /* PE_INIT_VDM_SVIDs_ACKed embedded here */ dfp_consume_svids(port, sop, cnt, payload); break; - } + } case VDM_RESULT_NAK: /* PE_INIT_VDM_SVIDs_NAKed embedded here */ pd_set_svids_discovery(port, pe[port].tx_type, PD_DISC_FAIL); @@ -5923,9 +5888,10 @@ static void pe_init_vdm_svids_request_exit(int port) /* If SVID discovery failed, discovery is done at this point */ if (pd_get_svids_discovery(port, pe[port].tx_type) == PD_DISC_FAIL) - pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ? - PD_STATUS_EVENT_SOP_DISC_DONE : - PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); + pd_notify_event(port, + pe[port].tx_type == TCPCI_MSG_SOP ? + PD_STATUS_EVENT_SOP_DISC_DONE : + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } /** @@ -5956,14 +5922,14 @@ static void pe_init_vdm_modes_request_entry(int port) * is still disabled, there's nothing left to try. */ pd_set_modes_discovery(port, pe[port].tx_type, svid, - PD_DISC_FAIL); + PD_DISC_FAIL); set_state_pe(port, get_last_state_pe(port)); return; } - msg[0] = VDO((uint16_t) svid, 1, - VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | - CMD_DISCOVER_MODES); + msg[0] = VDO((uint16_t)svid, 1, + VDO_SVDM_VERS(pd_get_vdo_ver(port, pe[port].tx_type)) | + CMD_DISCOVER_MODES); tx_emsg[port].len = sizeof(uint32_t); send_data_msg(port, pe[port].tx_type, PD_DATA_VENDOR_DEF); @@ -5999,10 +5965,10 @@ static void pe_init_vdm_modes_request_run(int port) break; case VDM_RESULT_ACK: { /* Retrieve the message information. */ - uint32_t *payload = (uint32_t *) rx_emsg[port].buf; + uint32_t *payload = (uint32_t *)rx_emsg[port].buf; int sop = PD_HEADER_GET_SOP(rx_emsg[port].header); uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header); - uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]); + uint16_t response_svid = (uint16_t)PD_VDO_VID(payload[0]); /* * Accept ACK if the request and response SVIDs are equal; @@ -6016,12 +5982,12 @@ static void pe_init_vdm_modes_request_run(int port) dfp_consume_modes(port, sop, cnt, payload); break; } - } + } /* Fall Through */ case VDM_RESULT_NAK: /* PE_INIT_VDM_Modes_NAKed embedded here */ pd_set_modes_discovery(port, pe[port].tx_type, requested_svid, - PD_DISC_FAIL); + PD_DISC_FAIL); break; } @@ -6033,10 +5999,10 @@ static void pe_init_vdm_modes_request_exit(int port) { if (pd_get_modes_discovery(port, pe[port].tx_type) != PD_DISC_NEEDED) /* Mode discovery done, notify the AP */ - pd_notify_event(port, pe[port].tx_type == TCPCI_MSG_SOP ? - PD_STATUS_EVENT_SOP_DISC_DONE : - PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); - + pd_notify_event(port, + pe[port].tx_type == TCPCI_MSG_SOP ? + PD_STATUS_EVENT_SOP_DISC_DONE : + PD_STATUS_EVENT_SOP_PRIME_DISC_DONE); } /** @@ -6051,7 +6017,7 @@ static void pe_vdm_request_dpm_entry(int port) if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME || pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) && - !pe_can_send_sop_prime(port)) { + !pe_can_send_sop_prime(port)) { /* * The parent state already tried to enable SOP' traffic. If it * is still disabled, there's nothing left to try. @@ -6066,9 +6032,8 @@ static void pe_vdm_request_dpm_entry(int port) /* Copy Vendor Data Objects (VDOs) into message buffer */ if (pe[port].vdm_cnt > 0) { /* Copy data after header */ - memcpy(&tx_emsg[port].buf, - (uint8_t *)pe[port].vdm_data, - pe[port].vdm_cnt * 4); + memcpy(&tx_emsg[port].buf, (uint8_t *)pe[port].vdm_data, + pe[port].vdm_cnt * 4); /* Update len with the number of VDO bytes */ tx_emsg[port].len = pe[port].vdm_cnt * 4; } @@ -6106,8 +6071,8 @@ static void pe_vdm_request_dpm_run(int port) * transmit is complete. */ vdm_hdr = pe[port].vdm_data[0]; - if(PD_VDO_SVDM(vdm_hdr) && - (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) { + if (PD_VDO_SVDM(vdm_hdr) && + (PD_VDO_CMD(vdm_hdr) == CMD_ATTENTION)) { if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE)) { PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE); break; @@ -6129,7 +6094,7 @@ static void pe_vdm_request_dpm_run(int port) break; case VDM_RESULT_ACK: { /* Retrieve the message information. */ - uint32_t *payload = (uint32_t *) rx_emsg[port].buf; + uint32_t *payload = (uint32_t *)rx_emsg[port].buf; int sop = PD_HEADER_GET_SOP(rx_emsg[port].header); uint8_t cnt = PD_HEADER_CNT(rx_emsg[port].header); uint16_t svid = PD_VDO_VID(payload[0]); @@ -6142,11 +6107,11 @@ static void pe_vdm_request_dpm_run(int port) dpm_vdm_acked(port, sop, cnt, payload); if (sop == TCPCI_MSG_SOP && svid == USB_SID_DISPLAYPORT && - vdm_cmd == CMD_DP_CONFIG) { + vdm_cmd == CMD_DP_CONFIG) { PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE); } break; - } + } case VDM_RESULT_NAK: /* * PE initiator VDM-NAKed state for requested VDM, like @@ -6160,8 +6125,8 @@ static void pe_vdm_request_dpm_run(int port) * Extract the needed information from the sent VDM. */ dpm_vdm_naked(port, pe[port].tx_type, - PD_VDO_VID(pe[port].vdm_data[0]), - PD_VDO_CMD(pe[port].vdm_data[0])); + PD_VDO_VID(pe[port].vdm_data[0]), + PD_VDO_CMD(pe[port].vdm_data[0])); break; } @@ -6344,11 +6309,9 @@ static void pe_vdm_response_run(int port) if (PE_CHK_FLAG(port, PE_FLAGS_TX_COMPLETE) || PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) || PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { - - PE_CLR_MASK(port, - BIT(PE_FLAGS_TX_COMPLETE_FN) | - BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | - BIT(PE_FLAGS_MSG_DISCARDED_FN)); + PE_CLR_MASK(port, BIT(PE_FLAGS_TX_COMPLETE_FN) | + BIT(PE_FLAGS_PROTOCOL_ERROR_FN) | + BIT(PE_FLAGS_MSG_DISCARDED_FN)); pe_set_ready_state(port); } @@ -6381,7 +6344,7 @@ static void pe_enter_usb_entry(int port) if ((pe[port].tx_type == TCPCI_MSG_SOP_PRIME || pe[port].tx_type == TCPCI_MSG_SOP_PRIME_PRIME) && - !tc_is_vconn_src(port)) { + !tc_is_vconn_src(port)) { if (port_try_vconn_swap(port)) return; } @@ -6587,11 +6550,12 @@ static void pe_vcs_send_swap_run(int port) */ if (type == PD_CTRL_ACCEPT) { if (tc_is_vconn_src(port)) { - set_state_pe(port, + set_state_pe( + port, PE_VCS_WAIT_FOR_VCONN_SWAP); } else { set_state_pe(port, - PE_VCS_TURN_ON_VCONN_SWAP); + PE_VCS_TURN_ON_VCONN_SWAP); } return; } @@ -6614,7 +6578,7 @@ static void pe_vcs_send_swap_run(int port) */ if (type == PD_CTRL_NOT_SUPPORTED) { if (IS_ENABLED(CONFIG_USB_PD_REV30) && - !tc_is_vconn_src(port)) + !tc_is_vconn_src(port)) set_state_pe(port, PE_VCS_FORCE_VCONN); else pe_set_ready_state(port); @@ -6696,8 +6660,8 @@ static void pe_vcs_wait_for_vconn_swap_run(int port) * the incoming message. */ PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); - pe_send_soft_reset(port, - PD_HEADER_GET_SOP(rx_emsg[port].header)); + pe_send_soft_reset( + port, PD_HEADER_GET_SOP(rx_emsg[port].header)); return; } } @@ -6739,7 +6703,6 @@ static void pe_vcs_turn_on_vconn_swap_entry(int port) static void pe_vcs_turn_on_vconn_swap_run(int port) { - /* * Transition to the PE_VCS_Send_Ps_Rdy state when: * 1) The Port’s VCONN is on. @@ -6799,7 +6762,7 @@ static void pe_vcs_send_ps_rdy_swap_entry(int port) /* Check for any interruptions to this non-interruptible AMS */ if (PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { enum tcpci_msg_type sop = - PD_HEADER_GET_SOP(rx_emsg[port].header); + PD_HEADER_GET_SOP(rx_emsg[port].header); PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); @@ -6927,7 +6890,7 @@ static void pe_vcs_cbl_send_soft_reset_run(int port) /* Got ACCEPT or REJECT from Cable Plug */ if ((msg_check & PE_MSG_SENT) && - PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { + PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); cable_soft_reset_complete = true; @@ -7024,16 +6987,17 @@ static void pe_dr_get_sink_cap_run(int port) if ((cnt > 0) && (type == PD_DATA_SINK_CAP)) { uint32_t *payload = (uint32_t *)rx_emsg[port].buf; - uint8_t cap_cnt = rx_emsg[port].len / - sizeof(uint32_t); + uint8_t cap_cnt = + rx_emsg[port].len / sizeof(uint32_t); pe_set_snk_caps(port, cap_cnt, payload); dpm_evaluate_sink_fixed_pdo(port, payload[0]); pe_set_ready_state(port); return; - } else if (cnt == 0 && (type == PD_CTRL_REJECT || - type == PD_CTRL_NOT_SUPPORTED)) { + } else if (cnt == 0 && + (type == PD_CTRL_REJECT || + type == PD_CTRL_NOT_SUPPORTED)) { pe_set_ready_state(port); return; } @@ -7147,12 +7111,13 @@ static void pe_dr_src_get_source_cap_run(int port) */ if (IS_ENABLED(CONFIG_CHARGE_MANAGER) && pd_get_partner_dual_role_power(port)) - charge_manager_update_dualrole(port, - CAP_DUALROLE); + charge_manager_update_dualrole( + port, CAP_DUALROLE); set_state_pe(port, PE_SRC_READY); - } else if ((cnt == 0) && (type == PD_CTRL_REJECT || - type == PD_CTRL_NOT_SUPPORTED)) { + } else if ((cnt == 0) && + (type == PD_CTRL_REJECT || + type == PD_CTRL_NOT_SUPPORTED)) { pd_set_src_caps(port, -1, NULL); set_state_pe(port, PE_SRC_READY); } else { @@ -7209,7 +7174,7 @@ __maybe_unused static void pe_get_revision_run(int port) msg_check = pe_sender_response_msg_run(port); if ((msg_check & PE_MSG_SENT) && - PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { + PE_CHK_FLAG(port, PE_FLAGS_MSG_RECEIVED)) { PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); type = PD_HEADER_TYPE(rx_emsg[port].header); @@ -7219,7 +7184,7 @@ __maybe_unused static void pe_get_revision_run(int port) if (ext == 0 && cnt == 1 && type == PD_DATA_REVISION) { /* Revision returned by partner */ pe[port].partner_rmdo = - *((struct rmdo *) rx_emsg[port].buf); + *((struct rmdo *)rx_emsg[port].buf); } else if (type != PD_CTRL_NOT_SUPPORTED) { /* * If the partner response with a message other than @@ -7244,7 +7209,6 @@ __maybe_unused static void pe_get_revision_run(int port) if ((msg_check & PE_MSG_DISCARDED) || pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE)) pe_set_ready_state(port); - } __maybe_unused static void pe_get_revision_exit(int port) @@ -7290,17 +7254,17 @@ static void pe_udr_send_data_reset_run(int port) PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP && - PD_HEADER_CNT(hdr) == 0 && - !PD_HEADER_EXT(hdr) && - PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) { - set_state_pe(port, tc_is_vconn_src(port) ? + PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) && + PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) { + set_state_pe( + port, + tc_is_vconn_src(port) ? PE_UDR_TURN_OFF_VCONN : PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE); return; } else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP && - PD_HEADER_CNT(hdr) == 0 && - !PD_HEADER_EXT(hdr) && - PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) { + PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) && + PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) { /* Just pretend it worked. */ dpm_data_reset_complete(port); pe_set_ready_state(port); @@ -7312,7 +7276,7 @@ static void pe_udr_send_data_reset_run(int port) } if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) || - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); return; @@ -7339,10 +7303,9 @@ static void pe_udr_data_reset_received_run(int port) if (tc_is_vconn_src(port)) set_state_pe(port, PE_UDR_TURN_OFF_VCONN); else - set_state_pe(port, - PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE); + set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE); } else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) || - PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { + PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); @@ -7361,7 +7324,7 @@ static void pe_udr_turn_off_vconn_run(int port) { /* Wait until VCONN is fully discharged */ if (pd_timer_is_disabled(port, PE_TIMER_TIMEOUT) && - PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) { + PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) { PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE); pd_timer_enable(port, PE_TIMER_TIMEOUT, CONFIG_USBC_VCONN_SWAP_DELAY_US); @@ -7385,7 +7348,7 @@ static void pe_udr_send_ps_rdy_run(int port) PE_CLR_FLAG(port, PE_FLAGS_TX_COMPLETE); set_state_pe(port, PE_UDR_WAIT_FOR_DATA_RESET_COMPLETE); } else if (PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR) || - PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { + PE_CHK_FLAG(port, PE_FLAGS_MSG_DISCARDED)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); PE_CLR_FLAG(port, PE_FLAGS_MSG_DISCARDED); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); @@ -7467,9 +7430,8 @@ static void pe_ddr_send_data_reset_run(int port) PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP && - PD_HEADER_CNT(hdr) == 0 && - !PD_HEADER_EXT(hdr) && - PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) { + PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) && + PD_HEADER_TYPE(hdr) == PD_CTRL_ACCEPT) { /* * Start DataResetFailTimer NOTE: This timer continues * to run in every state until it is stopped or it times @@ -7478,13 +7440,12 @@ static void pe_ddr_send_data_reset_run(int port) pd_timer_enable(port, PE_TIMER_DATA_RESET_FAIL, PD_T_DATA_RESET_FAIL); set_state_pe(port, tc_is_vconn_src(port) ? - PE_DDR_PERFORM_DATA_RESET : - PE_DDR_WAIT_FOR_VCONN_OFF); + PE_DDR_PERFORM_DATA_RESET : + PE_DDR_WAIT_FOR_VCONN_OFF); return; } else if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP && - PD_HEADER_CNT(hdr) == 0 && - !PD_HEADER_EXT(hdr) && - PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) { + PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) && + PD_HEADER_TYPE(hdr) == PD_CTRL_NOT_SUPPORTED) { /* Just pretend it worked. */ dpm_data_reset_complete(port); pe_set_ready_state(port); @@ -7496,7 +7457,7 @@ static void pe_ddr_send_data_reset_run(int port) } if (pd_timer_is_expired(port, PE_TIMER_SENDER_RESPONSE) || - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); return; @@ -7560,9 +7521,8 @@ static void pe_ddr_wait_for_vconn_off_run(int port) PE_CLR_FLAG(port, PE_FLAGS_MSG_RECEIVED); if (PD_HEADER_GET_SOP(hdr) == TCPCI_MSG_SOP && - PD_HEADER_CNT(hdr) == 0 && - !PD_HEADER_EXT(hdr) && - PD_HEADER_TYPE(hdr) == PD_CTRL_PS_RDY) { + PD_HEADER_CNT(hdr) == 0 && !PD_HEADER_EXT(hdr) && + PD_HEADER_TYPE(hdr) == PD_CTRL_PS_RDY) { /* PS_RDY message received */ pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED, PD_T_VCONN_REAPPLIED); @@ -7575,7 +7535,7 @@ static void pe_ddr_wait_for_vconn_off_run(int port) } if (pd_timer_is_expired(port, PE_TIMER_VCONN_DISCHARGE) || - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); return; @@ -7602,7 +7562,7 @@ static void pe_ddr_perform_data_reset_entry(int port) * c) If operating in [USB4] drive the port’s SBTX to a logic low. */ usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); /* 2) Both the DFP and UFP Shall exit all Alternate Modes if any. */ if (IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) { @@ -7641,18 +7601,18 @@ static void pe_ddr_perform_data_reset_run(int port) * expires. At this point, the Data Reset process is complete. */ if (IS_ENABLED(CONFIG_USBC_VCONN) && !tc_is_vconn_src(port) && - PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) { + PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE)) { PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE); /* Wait until VCONN has discharged to start tVconnReapplied. */ pd_timer_enable(port, PE_TIMER_TIMEOUT, - CONFIG_USBC_VCONN_SWAP_DELAY_US); + CONFIG_USBC_VCONN_SWAP_DELAY_US); } else if (IS_ENABLED(CONFIG_USBC_VCONN) && - pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) { + pd_timer_is_expired(port, PE_TIMER_TIMEOUT)) { pd_timer_disable(port, PE_TIMER_TIMEOUT); pd_timer_enable(port, PE_TIMER_VCONN_REAPPLIED, PD_T_VCONN_REAPPLIED); } else if (IS_ENABLED(CONFIG_USBC_VCONN) && - pd_timer_is_expired(port, PE_TIMER_VCONN_REAPPLIED)) { + pd_timer_is_expired(port, PE_TIMER_VCONN_REAPPLIED)) { pd_request_vconn_swap_on(port); pd_timer_disable(port, PE_TIMER_VCONN_REAPPLIED); @@ -7670,14 +7630,14 @@ static void pe_ddr_perform_data_reset_run(int port) * ambiguity and update this implementation. */ usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); } else if (IS_ENABLED(CONFIG_USBC_VCONN) && - PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE) && - tc_is_vconn_src(port)) { + PE_CHK_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE) && + tc_is_vconn_src(port)) { PE_CLR_FLAG(port, PE_FLAGS_VCONN_SWAP_COMPLETE); PE_SET_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE); } else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE) && - !pd_timer_is_disabled(port, PE_TIMER_DATA_RESET_FAIL)) { + !pd_timer_is_disabled(port, PE_TIMER_DATA_RESET_FAIL)) { pd_timer_disable(port, PE_TIMER_DATA_RESET_FAIL); send_ctrl_msg(port, TCPCI_MSG_SOP, PD_CTRL_DATA_RESET_COMPLETE); } else if (PE_CHK_FLAG(port, PE_FLAGS_DATA_RESET_COMPLETE)) { @@ -7695,7 +7655,7 @@ static void pe_ddr_perform_data_reset_run(int port) } return; } else if (pd_timer_is_expired(port, PE_TIMER_DATA_RESET_FAIL) || - PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { + PE_CHK_FLAG(port, PE_FLAGS_PROTOCOL_ERROR)) { PE_CLR_FLAG(port, PE_FLAGS_PROTOCOL_ERROR); set_state_pe(port, PE_WAIT_FOR_ERROR_RECOVERY); return; @@ -7719,7 +7679,7 @@ static void pe_ddr_perform_data_reset_exit(int port) } #endif /* CONFIG_USB_PD_DATA_RESET_MSG */ -const uint32_t * const pd_get_src_caps(int port) +const uint32_t *const pd_get_src_caps(int port) { return pe[port].src_caps; } @@ -7752,7 +7712,6 @@ void pd_dfp_discovery_init(int port) BIT(task_get_current())); memset(pe[port].discovery, 0, sizeof(pe[port].discovery)); - } void pd_dfp_mode_init(int port) @@ -7761,9 +7720,8 @@ void pd_dfp_mode_init(int port) * Clear the VDM Setup Done and Modal Operation flags so we will * have a fresh discovery */ - PE_CLR_MASK(port, - BIT(PE_FLAGS_VDM_SETUP_DONE_FN) | - BIT(PE_FLAGS_MODAL_OPERATION_FN)); + PE_CLR_MASK(port, BIT(PE_FLAGS_VDM_SETUP_DONE_FN) | + BIT(PE_FLAGS_MODAL_OPERATION_FN)); memset(pe[port].partner_amodes, 0, sizeof(pe[port].partner_amodes)); @@ -7782,7 +7740,7 @@ void pd_dfp_mode_init(int port) } __maybe_unused void pd_discovery_access_clear(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) assert(0); @@ -7791,7 +7749,7 @@ __maybe_unused void pd_discovery_access_clear(int port, } __maybe_unused bool pd_discovery_access_validate(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) assert(0); @@ -7799,15 +7757,15 @@ __maybe_unused bool pd_discovery_access_validate(int port, return !(task_access[port][type] & ~BIT(task_get_current())); } -__maybe_unused struct pd_discovery *pd_get_am_discovery_and_notify_access( - int port, enum tcpci_msg_type type) +__maybe_unused struct pd_discovery * +pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type) { atomic_or(&task_access[port][type], BIT(task_get_current())); return (struct pd_discovery *)pd_get_am_discovery(port, type); } -__maybe_unused const struct pd_discovery *pd_get_am_discovery(int port, - enum tcpci_msg_type type) +__maybe_unused const struct pd_discovery * +pd_get_am_discovery(int port, enum tcpci_msg_type type) { if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) assert(0); @@ -7816,8 +7774,8 @@ __maybe_unused const struct pd_discovery *pd_get_am_discovery(int port, return &pe[port].discovery[type]; } -__maybe_unused struct partner_active_modes *pd_get_partner_active_modes( - int port, enum tcpci_msg_type type) +__maybe_unused struct partner_active_modes * +pd_get_partner_active_modes(int port, enum tcpci_msg_type type) { if (!IS_ENABLED(CONFIG_USB_PD_ALT_MODE_DFP)) assert(0); @@ -7853,7 +7811,7 @@ uint32_t pe_get_flags(int port) } static __const_data const struct usb_state pe_states[] = { - /* Super States */ +/* Super States */ #ifdef CONFIG_USB_PD_REV30 [PE_PRS_FRS_SHARED] = { .entry = pe_prs_frs_shared_entry, -- cgit v1.2.1 From 449920d1365c4790ddc6268a152b206d91b1f20f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:26 -0600 Subject: driver/pmic_tps650x30.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6b56d6156e2d17411426d6167c67d3fc8afc1fdf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730023 Reviewed-by: Jeremy Bettis --- driver/pmic_tps650x30.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/driver/pmic_tps650x30.h b/driver/pmic_tps650x30.h index f03bef5f05..198b58edc1 100644 --- a/driver/pmic_tps650x30.h +++ b/driver/pmic_tps650x30.h @@ -9,29 +9,29 @@ #define __CROS_EC_PMIC_TPS650X30_H /* I2C interface */ -#define TPS650X30_I2C_ADDR1_FLAGS 0x30 -#define TPS650X30_I2C_ADDR2_FLAGS 0x32 -#define TPS650X30_I2C_ADDR3_FLAGS 0x34 +#define TPS650X30_I2C_ADDR1_FLAGS 0x30 +#define TPS650X30_I2C_ADDR2_FLAGS 0x32 +#define TPS650X30_I2C_ADDR3_FLAGS 0x34 /* TPS650X30 registers */ -#define TPS650X30_REG_VENDORID 0x00 -#define TPS650X30_REG_PBCONFIG 0x14 -#define TPS650X30_REG_PGMASK1 0x18 -#define TPS650X30_REG_VCCIOCNT 0x30 -#define TPS650X30_REG_V5ADS3CNT 0x31 -#define TPS650X30_REG_V33ADSWCNT 0x32 -#define TPS650X30_REG_V18ACNT 0x34 -#define TPS650X30_REG_V1P2UCNT 0x36 -#define TPS650X30_REG_V100ACNT 0x37 -#define TPS650X30_REG_VRMODECTRL 0x3B -#define TPS650X30_REG_DISCHCNT1 0x3C -#define TPS650X30_REG_DISCHCNT2 0x3D -#define TPS650X30_REG_DISCHCNT3 0x3E -#define TPS650X30_REG_DISCHCNT4 0x3F -#define TPS650X30_REG_PWFAULT_MASK1 0xE5 -#define TPS650X30_REG_PWFAULT_MASK2 0xE6 +#define TPS650X30_REG_VENDORID 0x00 +#define TPS650X30_REG_PBCONFIG 0x14 +#define TPS650X30_REG_PGMASK1 0x18 +#define TPS650X30_REG_VCCIOCNT 0x30 +#define TPS650X30_REG_V5ADS3CNT 0x31 +#define TPS650X30_REG_V33ADSWCNT 0x32 +#define TPS650X30_REG_V18ACNT 0x34 +#define TPS650X30_REG_V1P2UCNT 0x36 +#define TPS650X30_REG_V100ACNT 0x37 +#define TPS650X30_REG_VRMODECTRL 0x3B +#define TPS650X30_REG_DISCHCNT1 0x3C +#define TPS650X30_REG_DISCHCNT2 0x3D +#define TPS650X30_REG_DISCHCNT3 0x3E +#define TPS650X30_REG_DISCHCNT4 0x3F +#define TPS650X30_REG_PWFAULT_MASK1 0xE5 +#define TPS650X30_REG_PWFAULT_MASK2 0xE6 /* TPS650X30 register values */ -#define TPS650X30_VENDOR_ID 0x22 +#define TPS650X30_VENDOR_ID 0x22 -#endif /* __CROS_EC_PMIC_TPS650X30_H */ +#endif /* __CROS_EC_PMIC_TPS650X30_H */ -- cgit v1.2.1 From 12f0bce53cb89500393b7fd59ea1fb563586884e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:46 -0600 Subject: baseboard/dedede/variant_ec_npcx796fc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife3826b119be29541c6b50d4031e66965b3e25b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727875 Reviewed-by: Jeremy Bettis --- baseboard/dedede/variant_ec_npcx796fc.c | 84 ++++++++++++++------------------- 1 file changed, 36 insertions(+), 48 deletions(-) diff --git a/baseboard/dedede/variant_ec_npcx796fc.c b/baseboard/dedede/variant_ec_npcx796fc.c index aa2709b33b..b4a2270698 100644 --- a/baseboard/dedede/variant_ec_npcx796fc.c +++ b/baseboard/dedede/variant_ec_npcx796fc.c @@ -21,8 +21,8 @@ #include "timer.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) void pp3300_a_pgood_high(void) { @@ -79,7 +79,7 @@ static void set_up_adc_irqs(void) npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); } -DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC+1); +DECLARE_HOOK(HOOK_INIT, set_up_adc_irqs, HOOK_PRIO_INIT_ADC + 1); static void disable_adc_irqs_deferred(void) { @@ -144,8 +144,8 @@ static void enable_adc_irqs(void) if (chipset_in_or_transitioning_to_state(CHIPSET_STATE_ANY_OFF)) { CPRINTS("%s", __func__); hook_call_deferred(&disable_adc_irqs_deferred_data, -1); - npcx_set_adc_repetitive(adc_channels[ADC_VSNS_PP3300_A].input_ch, - 1); + npcx_set_adc_repetitive( + adc_channels[ADC_VSNS_PP3300_A].input_ch, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH1, 1); npcx_adc_thresh_int_enable(NPCX_ADC_THRESH2, 1); } @@ -162,56 +162,44 @@ DECLARE_HOOK(HOOK_LID_CHANGE, enable_adc_irqs_via_lid, HOOK_PRIO_DEFAULT); /* I2C Ports */ __attribute__((weak)) const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 1000, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 1000, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, #ifdef HAS_TASK_MOTIONSENSE - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, #endif - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif #ifdef BOARD_BUGZZY - { - .name = "lcd", - .port = I2C_PORT_LCD, - .kbps = 400, - .scl = GPIO_EC_I2C_LCD_SCL, - .sda = GPIO_EC_I2C_LCD_SDA - }, + { .name = "lcd", + .port = I2C_PORT_LCD, + .kbps = 400, + .scl = GPIO_EC_I2C_LCD_SCL, + .sda = GPIO_EC_I2C_LCD_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From 406a4b59a777d39c1bb063dd60cf3bc87c82c075 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:26 -0600 Subject: zephyr/test/drivers/include/test/drivers/test_mocks.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I422463bcc5c0e0719b8ca4ff5dbcb499541267e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730936 Reviewed-by: Jeremy Bettis --- .../test/drivers/include/test/drivers/test_mocks.h | 64 +++++++++++----------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/zephyr/test/drivers/include/test/drivers/test_mocks.h b/zephyr/test/drivers/include/test/drivers/test_mocks.h index f29cce97cc..815d8c3740 100644 --- a/zephyr/test/drivers/include/test/drivers/test_mocks.h +++ b/zephyr/test/drivers/include/test/drivers/test_mocks.h @@ -42,27 +42,27 @@ * @param EXPECTED_VAL - The 8-bit value that was supposed to be written, or * `MOCK_IGNORE_VALUE` to suppress this check. */ -#define MOCK_ASSERT_I2C_WRITE(FAKE, CALL_NUM, EXPECTED_REG, EXPECTED_VAL) \ - do { \ - zassert_true((CALL_NUM) < FAKE##_fake.call_count, \ - "Call #%d did not occur (%d I2C writes total)", \ - (CALL_NUM), FAKE##_fake.call_count); \ - zassert_equal( \ - FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \ - "Expected I2C write #%d to register 0x%02x (" \ - #EXPECTED_REG ") but wrote to reg 0x%02x", \ - (CALL_NUM), (EXPECTED_REG), \ - FAKE##_fake.arg1_history[(CALL_NUM)]); \ - if ((EXPECTED_VAL) != MOCK_IGNORE_VALUE) { \ - zassert_equal( \ - FAKE##_fake.arg2_history[(CALL_NUM)], \ - (EXPECTED_VAL), \ - "Expected I2C write #%d to register 0x%02x (" \ - #EXPECTED_REG ") to write 0x%02x (" \ - #EXPECTED_VAL ") but wrote 0x%02x", \ - (CALL_NUM), (EXPECTED_REG), (EXPECTED_VAL), \ - FAKE##_fake.arg2_history[(CALL_NUM)]); \ - } \ +#define MOCK_ASSERT_I2C_WRITE(FAKE, CALL_NUM, EXPECTED_REG, EXPECTED_VAL) \ + do { \ + zassert_true((CALL_NUM) < FAKE##_fake.call_count, \ + "Call #%d did not occur (%d I2C writes total)", \ + (CALL_NUM), FAKE##_fake.call_count); \ + zassert_equal( \ + FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \ + "Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG \ + ") but wrote to reg 0x%02x", \ + (CALL_NUM), (EXPECTED_REG), \ + FAKE##_fake.arg1_history[(CALL_NUM)]); \ + if ((EXPECTED_VAL) != MOCK_IGNORE_VALUE) { \ + zassert_equal( \ + FAKE##_fake.arg2_history[(CALL_NUM)], \ + (EXPECTED_VAL), \ + "Expected I2C write #%d to register 0x%02x (" #EXPECTED_REG \ + ") to write 0x%02x (" #EXPECTED_VAL \ + ") but wrote 0x%02x", \ + (CALL_NUM), (EXPECTED_REG), (EXPECTED_VAL), \ + FAKE##_fake.arg2_history[(CALL_NUM)]); \ + } \ } while (0) /** @brief Value to pass to MOCK_ASSERT_I2C_WRITE to ignore the actual value @@ -81,17 +81,17 @@ * @param EXPECTED_REG - The register address that was supposed to be read * from. */ -#define MOCK_ASSERT_I2C_READ(FAKE, CALL_NUM, EXPECTED_REG) \ - do { \ - zassert_true((CALL_NUM) < FAKE##_fake.call_count, \ - "Call #%d did not occur (%d I2C reads total)", \ - (CALL_NUM), FAKE##_fake.call_count); \ - zassert_equal( \ - FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \ - "Expected I2C read #%d from register 0x%02x (" \ - #EXPECTED_REG ") but read from reg 0x%02x", \ - (CALL_NUM), (EXPECTED_REG), \ - FAKE##_fake.arg1_history[(CALL_NUM)]); \ +#define MOCK_ASSERT_I2C_READ(FAKE, CALL_NUM, EXPECTED_REG) \ + do { \ + zassert_true((CALL_NUM) < FAKE##_fake.call_count, \ + "Call #%d did not occur (%d I2C reads total)", \ + (CALL_NUM), FAKE##_fake.call_count); \ + zassert_equal( \ + FAKE##_fake.arg1_history[(CALL_NUM)], (EXPECTED_REG), \ + "Expected I2C read #%d from register 0x%02x (" #EXPECTED_REG \ + ") but read from reg 0x%02x", \ + (CALL_NUM), (EXPECTED_REG), \ + FAKE##_fake.arg1_history[(CALL_NUM)]); \ } while (0) /* -- cgit v1.2.1 From 390bb881720fca208026bc641db7a8f537c7b9e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:37 -0600 Subject: common/mkbp_event.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95dc837089f449b23845507b8209962a9c0159d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729666 Reviewed-by: Jeremy Bettis --- common/mkbp_event.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/common/mkbp_event.c b/common/mkbp_event.c index d67951c3b3..b499789e04 100644 --- a/common/mkbp_event.c +++ b/common/mkbp_event.c @@ -18,8 +18,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_COMMAND, outstr) -#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args) +#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) /* * Tracks the current state of the MKBP interrupt send from the EC to the AP. @@ -165,7 +165,7 @@ static int mkbp_set_host_active(int active, uint32_t *timestamp) return mkbp_set_host_active_via_custom(active, timestamp); #elif defined(CONFIG_MKBP_USE_HOST_EVENT) return mkbp_set_host_active_via_event(active, timestamp); -#elif defined(CONFIG_MKBP_USE_GPIO) ||\ +#elif defined(CONFIG_MKBP_USE_GPIO) || \ defined(CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT) return mkbp_set_host_active_via_gpio(active, timestamp); #elif defined(CONFIG_MKBP_USE_HECI) @@ -185,10 +185,9 @@ static inline int host_is_sleeping(void) #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE enum host_sleep_event sleep_state = power_get_host_sleep_state(); - is_sleeping |= - (sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND || - sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND || - sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND); + is_sleeping |= (sleep_state == HOST_SLEEP_EVENT_S0IX_SUSPEND || + sleep_state == HOST_SLEEP_EVENT_S3_SUSPEND || + sleep_state == HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND); #endif return is_sleeping; } @@ -216,16 +215,16 @@ static void activate_mkbp_with_events(uint32_t events_to_add) */ if (events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT) || events_to_add == BIT(EC_MKBP_EVENT_HOST_EVENT64)) - skip_interrupt = host_is_sleeping() && - !(host_get_events() & - mkbp_host_event_wake_mask); + skip_interrupt = + host_is_sleeping() && + !(host_get_events() & mkbp_host_event_wake_mask); #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */ #ifdef CONFIG_MKBP_EVENT_WAKEUP_MASK /* Check to see if this MKBP event should wake the system. */ if (!skip_interrupt) skip_interrupt = host_is_sleeping() && - !(events_to_add & mkbp_event_wake_mask); + !(events_to_add & mkbp_event_wake_mask); #endif /* CONFIG_MKBP_EVENT_WAKEUP_MASK */ mutex_lock(&state.lock); @@ -257,8 +256,8 @@ static void activate_mkbp_with_events(uint32_t events_to_add) if (state.interrupt == INTERRUPT_INACTIVE_TO_ACTIVE && interrupt_id == state.interrupt_id) { schedule_deferred = 1; - state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE - : INTERRUPT_INACTIVE; + state.interrupt = rv == EC_SUCCESS ? INTERRUPT_ACTIVE : + INTERRUPT_INACTIVE; } mutex_unlock(&state.lock); @@ -308,8 +307,8 @@ static void force_mkbp_if_events(void) * of events or we exceed number of attempts, so marking * interrupt as INACTIVE doesn't affect failed_attempts counter. * If we need to send interrupt once again - * activate_mkbp_with_events() will set interrupt state to ACTIVE - * before this function will be called. + * activate_mkbp_with_events() will set interrupt state to + * ACTIVE before this function will be called. */ if (++state.failed_attempts < 3) { send_mkbp_interrupt = 1; @@ -456,8 +455,7 @@ static enum ec_status mkbp_get_next_event(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT, - mkbp_get_next_event, +DECLARE_HOST_COMMAND(EC_CMD_GET_NEXT_EVENT, mkbp_get_next_event, EC_VER_MASK(0) | EC_VER_MASK(1) | EC_VER_MASK(2)); #ifdef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK @@ -473,12 +471,11 @@ mkbp_get_host_event_wake_mask(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK, - mkbp_get_host_event_wake_mask, - EC_VER_MASK(0)); + mkbp_get_host_event_wake_mask, EC_VER_MASK(0)); #endif /* CONFIG_MKBP_USE_HOST_EVENT */ #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */ -#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) || \ +#if defined(CONFIG_MKBP_EVENT_WAKEUP_MASK) || \ defined(CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK) static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args) { @@ -517,8 +514,7 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args) case EC_MKBP_HOST_EVENT_WAKE_MASK: CPRINTF("MKBP hostevent mask updated to: 0x%08x " "(was 0x%08x)\n", - p->new_wake_mask, - mkbp_host_event_wake_mask); + p->new_wake_mask, mkbp_host_event_wake_mask); mkbp_host_event_wake_mask = p->new_wake_mask; break; #endif /* CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK */ @@ -543,9 +539,7 @@ static enum ec_status hc_mkbp_wake_mask(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK, - hc_mkbp_wake_mask, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_MKBP_WAKE_MASK, hc_mkbp_wake_mask, EC_VER_MASK(0)); static int command_mkbp_wake_mask(int argc, char **argv) { -- cgit v1.2.1 From 64c35b4552be92cc7466929840b5aa512998dade Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:50 -0600 Subject: board/lindar/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia5b7da1172eeb61d58ebf54f320b48517ef0b3d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728634 Reviewed-by: Jeremy Bettis --- board/lindar/board.c | 49 ++++++++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 27 deletions(-) diff --git a/board/lindar/board.c b/board/lindar/board.c index 79ef3a4cbb..23d58fbf28 100644 --- a/board/lindar/board.c +++ b/board/lindar/board.c @@ -41,8 +41,8 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -113,7 +113,7 @@ __override void lid_angle_peripheral_enable(int enable) { if (ec_cfg_has_tabletmode()) { if (chipset_in_state(CHIPSET_STATE_ANY_OFF) || - tablet_get_mode()) + tablet_get_mode()) enable = 0; keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE); } @@ -130,17 +130,13 @@ static struct stprivate_data g_lis2dh_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate lid and base sensor into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -225,7 +221,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -261,8 +257,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -289,8 +285,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -425,8 +421,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -437,16 +432,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -454,7 +449,7 @@ void board_reset_pd_mcu(void) { ps8815_reset(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } /******************************************************************************/ -- cgit v1.2.1 From 9a7f3ad00837c3fee5b1f2cca9b9500fcfc05634 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:05 -0600 Subject: driver/accelgyro_lsm6dso.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic5ec7746ab4f0e06915b4cc24e8275d6f19158be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729922 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6dso.h | 141 ++++++++++++++++++++++----------------------- 1 file changed, 70 insertions(+), 71 deletions(-) diff --git a/driver/accelgyro_lsm6dso.h b/driver/accelgyro_lsm6dso.h index 6b7f1138b6..1730715665 100644 --- a/driver/accelgyro_lsm6dso.h +++ b/driver/accelgyro_lsm6dso.h @@ -12,78 +12,77 @@ #include "stm_mems_common.h" /* Access to embedded sensor hub register bank */ -#define LSM6DSO_FUNC_CFG_ACC_ADDR 0x01 -#define LSM6DSO_FUNC_CFG_EN 0x80 +#define LSM6DSO_FUNC_CFG_ACC_ADDR 0x01 +#define LSM6DSO_FUNC_CFG_EN 0x80 /* Who Am I */ -#define LSM6DSO_WHO_AM_I_REG 0x0f -#define LSM6DSO_WHO_AM_I 0x6c +#define LSM6DSO_WHO_AM_I_REG 0x0f +#define LSM6DSO_WHO_AM_I 0x6c /* Common defines for Acc and Gyro sensors */ -#define LSM6DSO_EN_BIT 0x01 -#define LSM6DSO_DIS_BIT 0x00 +#define LSM6DSO_EN_BIT 0x01 +#define LSM6DSO_DIS_BIT 0x00 -#define LSM6DSO_GYRO_OUT_X_L_ADDR 0x22 -#define LSM6DSO_ACCEL_OUT_X_L_ADDR 0x28 +#define LSM6DSO_GYRO_OUT_X_L_ADDR 0x22 +#define LSM6DSO_ACCEL_OUT_X_L_ADDR 0x28 -#define LSM6DSO_CTRL1_ADDR 0x10 -#define LSM6DSO_CTRL2_ADDR 0x11 -#define LSM6DSO_CTRL3_ADDR 0x12 -#define LSM6DSO_SW_RESET 0x01 -#define LSM6DSO_IF_INC 0x04 -#define LSM6DSO_PP_OD 0x10 -#define LSM6DSO_H_L_ACTIVE 0x20 -#define LSM6DSO_BDU 0x40 +#define LSM6DSO_CTRL1_ADDR 0x10 +#define LSM6DSO_CTRL2_ADDR 0x11 +#define LSM6DSO_CTRL3_ADDR 0x12 +#define LSM6DSO_SW_RESET 0x01 +#define LSM6DSO_IF_INC 0x04 +#define LSM6DSO_PP_OD 0x10 +#define LSM6DSO_H_L_ACTIVE 0x20 +#define LSM6DSO_BDU 0x40 -#define LSM6DSO_CTRL4_ADDR 0x13 -#define LSM6DSO_INT2_ON_INT1_MASK 0x20 +#define LSM6DSO_CTRL4_ADDR 0x13 +#define LSM6DSO_INT2_ON_INT1_MASK 0x20 -#define LSM6DSO_CTRL5_ADDR 0x14 -#define LSM6DSO_CTRL6_ADDR 0x15 -#define LSM6DSO_CTRL7_ADDR 0x16 -#define LSM6DSO_CTRL8_ADDR 0x17 -#define LSM6DSO_CTRL9_ADDR 0x18 +#define LSM6DSO_CTRL5_ADDR 0x14 +#define LSM6DSO_CTRL6_ADDR 0x15 +#define LSM6DSO_CTRL7_ADDR 0x16 +#define LSM6DSO_CTRL8_ADDR 0x17 +#define LSM6DSO_CTRL9_ADDR 0x18 -#define LSM6DSO_CTRL10_ADDR 0x19 -#define LSM6DSO_TIMESTAMP_EN 0x20 +#define LSM6DSO_CTRL10_ADDR 0x19 +#define LSM6DSO_TIMESTAMP_EN 0x20 -#define LSM6DSO_STATUS_REG 0x1e +#define LSM6DSO_STATUS_REG 0x1e /* Output data rate registers and masks */ -#define LSM6DSO_ODR_REG(_sensor) \ - (LSM6DSO_CTRL1_ADDR + (_sensor)) -#define LSM6DSO_ODR_MASK 0xf0 +#define LSM6DSO_ODR_REG(_sensor) (LSM6DSO_CTRL1_ADDR + (_sensor)) +#define LSM6DSO_ODR_MASK 0xf0 /* FIFO decimator registers and bitmask */ -#define LSM6DSO_FIFO_CTRL1_ADDR 0x07 -#define LSM6DSO_FIFO_CTRL2_ADDR 0x08 +#define LSM6DSO_FIFO_CTRL1_ADDR 0x07 +#define LSM6DSO_FIFO_CTRL2_ADDR 0x08 -#define LSM6DSO_FIFO_CTRL3_ADDR 0x09 -#define LSM6DSO_FIFO_ODR_XL_MASK 0x0f -#define LSM6DSO_FIFO_ODR_G_MASK 0xf0 +#define LSM6DSO_FIFO_CTRL3_ADDR 0x09 +#define LSM6DSO_FIFO_ODR_XL_MASK 0x0f +#define LSM6DSO_FIFO_ODR_G_MASK 0xf0 -#define LSM6DSO_FIFO_CTRL4_ADDR 0x0a -#define LSM6DSO_FIFO_MODE_MASK 0x07 +#define LSM6DSO_FIFO_CTRL4_ADDR 0x0a +#define LSM6DSO_FIFO_MODE_MASK 0x07 -#define LSM6DSO_INT1_CTRL 0x0d -#define LSM6DSO_INT2_CTRL 0x0e -#define LSM6DSO_INT_FIFO_TH 0x08 -#define LSM6DSO_INT_FIFO_OVR 0x10 -#define LSM6DSO_INT_FIFO_FULL 0x20 +#define LSM6DSO_INT1_CTRL 0x0d +#define LSM6DSO_INT2_CTRL 0x0e +#define LSM6DSO_INT_FIFO_TH 0x08 +#define LSM6DSO_INT_FIFO_OVR 0x10 +#define LSM6DSO_INT_FIFO_FULL 0x20 -#define LSM6DSO_FIFO_STS1_ADDR 0x3a -#define LSM6DSO_FIFO_STS2_ADDR 0x3b -#define LSM6DSO_FIFO_DIFF_MASK 0x07ff -#define LSM6DSO_FIFO_FULL 0x2000 -#define LSM6DSO_FIFO_DATA_OVR 0x4000 -#define LSM6DSO_FIFO_WATERMARK 0x8000 +#define LSM6DSO_FIFO_STS1_ADDR 0x3a +#define LSM6DSO_FIFO_STS2_ADDR 0x3b +#define LSM6DSO_FIFO_DIFF_MASK 0x07ff +#define LSM6DSO_FIFO_FULL 0x2000 +#define LSM6DSO_FIFO_DATA_OVR 0x4000 +#define LSM6DSO_FIFO_WATERMARK 0x8000 /* Out FIFO data register */ -#define LSM6DSO_FIFO_DATA_ADDR_TAG 0x78 +#define LSM6DSO_FIFO_DATA_ADDR_TAG 0x78 /* Registers value for supported FIFO mode */ -#define LSM6DSO_FIFO_MODE_BYPASS_VAL 0x00 -#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL 0x06 +#define LSM6DSO_FIFO_MODE_BYPASS_VAL 0x00 +#define LSM6DSO_FIFO_MODE_CONTINUOUS_VAL 0x06 /* Define device available in FIFO pattern */ enum lsm6dso_dev_fifo { @@ -94,8 +93,8 @@ enum lsm6dso_dev_fifo { }; /* Define FIFO data pattern, tag and len */ -#define LSM6DSO_TAG_SIZE 1 -#define LSM6DSO_FIFO_SAMPLE_SIZE (OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE) +#define LSM6DSO_TAG_SIZE 1 +#define LSM6DSO_FIFO_SAMPLE_SIZE (OUT_XYZ_SIZE + LSM6DSO_TAG_SIZE) enum lsm6dso_tag_fifo { LSM6DSO_GYRO_TAG = 0x01, @@ -110,32 +109,32 @@ struct lsm6dso_fstatus { /* ODR reg value from selected data rate in mHz */ #define LSM6DSO_ODR_TO_REG(_odr) (__fls(_odr / LSM6DSO_ODR_MIN_VAL) + 1) -#define LSM6DSO_FIFO_ODR_MASK(_s) \ +#define LSM6DSO_FIFO_ODR_MASK(_s) \ (_s->type == MOTIONSENSE_TYPE_ACCEL ? LSM6DSO_FIFO_ODR_XL_MASK : \ - LSM6DSO_FIFO_ODR_G_MASK) + LSM6DSO_FIFO_ODR_G_MASK) /* Normalized ODR values from selected data rate in mHz */ #define LSM6DSO_REG_TO_ODR(_reg) (LSM6DSO_ODR_MIN_VAL << (_reg - 1)) /* Full Scale ranges value and gain for Acc */ -#define LSM6DSO_FS_LIST_NUM 4 +#define LSM6DSO_FS_LIST_NUM 4 -#define LSM6DSO_ACCEL_FS_ADDR 0x10 -#define LSM6DSO_ACCEL_FS_MASK 0x0c +#define LSM6DSO_ACCEL_FS_ADDR 0x10 +#define LSM6DSO_ACCEL_FS_MASK 0x0c -#define LSM6DSO_ACCEL_FS_2G_VAL 0x00 -#define LSM6DSO_ACCEL_FS_4G_VAL 0x02 -#define LSM6DSO_ACCEL_FS_8G_VAL 0x03 -#define LSM6DSO_ACCEL_FS_16G_VAL 0x01 +#define LSM6DSO_ACCEL_FS_2G_VAL 0x00 +#define LSM6DSO_ACCEL_FS_4G_VAL 0x02 +#define LSM6DSO_ACCEL_FS_8G_VAL 0x03 +#define LSM6DSO_ACCEL_FS_16G_VAL 0x01 -#define LSM6DSO_ACCEL_FS_MAX_VAL 16 +#define LSM6DSO_ACCEL_FS_MAX_VAL 16 /* Accel reg value from Full Scale range */ static inline uint8_t lsm6dso_accel_fs_reg(int fs) { uint8_t ret; - switch(fs) { + switch (fs) { case 2: ret = LSM6DSO_ACCEL_FS_2G_VAL; break; @@ -154,8 +153,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs) #define LSM6DSO_ACCEL_NORMALIZE_FS(_fs) (1 << __fls(_fs)) /* Full Scale range value and gain for Gyro */ -#define LSM6DSO_GYRO_FS_ADDR 0x11 -#define LSM6DSO_GYRO_FS_MASK 0x0c +#define LSM6DSO_GYRO_FS_ADDR 0x11 +#define LSM6DSO_GYRO_FS_MASK 0x0c /* Minimal Gyro range in mDPS */ #define LSM6DSO_GYRO_FS_MIN_VAL_MDPS ((8750 << 15) / 1000) @@ -170,8 +169,8 @@ static inline uint8_t lsm6dso_accel_fs_reg(int fs) ((LSM6DSO_GYRO_FS_MIN_VAL_MDPS << (_reg)) / 1000) /* FS register address/mask for Acc/Gyro sensors */ -#define LSM6DSO_RANGE_REG(_sensor) (LSM6DSO_ACCEL_FS_ADDR + (_sensor)) -#define LSM6DSO_RANGE_MASK 0x0c +#define LSM6DSO_RANGE_REG(_sensor) (LSM6DSO_ACCEL_FS_ADDR + (_sensor)) +#define LSM6DSO_RANGE_MASK 0x0c /* Status register bit for Acc/Gyro data ready */ enum lsm6dso_status { @@ -181,11 +180,11 @@ enum lsm6dso_status { }; /* Status register bitmask for Acc/Gyro data ready */ -#define LSM6DSO_STS_XLDA_MASK 0x01 -#define LSM6DSO_STS_GDA_MASK 0x02 +#define LSM6DSO_STS_XLDA_MASK 0x01 +#define LSM6DSO_STS_GDA_MASK 0x02 /* Sensor resolution in number of bits: fixed 16 bit */ -#define LSM6DSO_RESOLUTION 16 +#define LSM6DSO_RESOLUTION 16 /* Aggregate private data for all supported sensor (Acc, Gyro) */ struct lsm6dso_data { @@ -224,6 +223,6 @@ void lsm6dso_interrupt(enum gpio_signal signal); #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(lsm6dso_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_H */ -- cgit v1.2.1 From e1b9d9b477c5f079a5d09450e718f1b59996bdc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:29 -0600 Subject: zephyr/shim/chip/npcx/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16bb66ad406b6f86ec74b6000a75cc02ad0f0c15 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730821 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/clock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c index 4fc9bd12c0..48f47855ca 100644 --- a/zephyr/shim/chip/npcx/clock.c +++ b/zephyr/shim/chip/npcx/clock.c @@ -16,9 +16,9 @@ LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) +#define CDCG_NODE DT_INST(0, nuvoton_npcx_pcc) #define HAL_CDCG_REG_BASE_ADDR \ - ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) + ((struct cdcg_reg *)DT_REG_ADDR_BY_IDX(CDCG_NODE, 1)) int clock_get_freq(void) { @@ -63,7 +63,7 @@ void clock_normal(void) struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; cdcg_base->HFCGP = ((FPRED_VAL << 4) | AHB6DIV_VAL); - cdcg_base->HFCBCD = (FIUDIV_VAL << 4); + cdcg_base->HFCBCD = (FIUDIV_VAL << 4); } void clock_enable_module(enum module_id module, int enable) -- cgit v1.2.1 From 517ef13832a08fe493ceb8123dea805a10bbeaec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:24 -0600 Subject: board/mithrax/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3bbecff7e7128fa81f61b6038a34f292b7076eba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728456 Reviewed-by: Jeremy Bettis --- board/mithrax/board.h | 151 +++++++++++++++++++++++--------------------------- 1 file changed, 68 insertions(+), 83 deletions(-) diff --git a/board/mithrax/board.h b/board/mithrax/board.h index 704904ffc4..0660757d38 100644 --- a/board/mithrax/board.h +++ b/board/mithrax/board.h @@ -29,11 +29,11 @@ /* LED */ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 -#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L -#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L +#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L +#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L /* Sensors */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -49,8 +49,8 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_LIS2DWL #define CONFIG_ACCEL_LIS2DW_AS_BASE #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \ @@ -61,13 +61,13 @@ #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_TCPM_PS8815 #define CONFIG_USBC_RETIMER_INTEL_BB @@ -82,17 +82,17 @@ #define CONFIG_USBC_PPC_NX20P3483 /* TODO: b/177608416 - measure and check these values on mithrax */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -100,68 +100,68 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_KEYBOARD_BACKLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_KBMCU NPCX_I2C_PORT3_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* * */ -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -178,26 +178,26 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* RGB Keyboard */ #ifdef SECTION_IS_RW #define CONFIG_RGB_KEYBOARD -#define CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ -#define TLC59116F_I2C_ADDR_FLAG TLC59116F_ADDR3_FLAG +#define CONFIG_LED_DRIVER_TLC59116F /* TLC59116F on I2C */ +#define TLC59116F_I2C_ADDR_FLAG TLC59116F_ADDR3_FLAG #endif /* SECTION_IS_RW */ -#define RGB_GRID0_COL 4 -#define RGB_GRID0_ROW 1 +#define RGB_GRID0_COL 4 +#define RGB_GRID0_ROW 1 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -215,18 +215,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C2_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; enum battery_type { BATTERY_C536, @@ -236,20 +227,14 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void pen_detect_interrupt(enum gpio_signal s); -- cgit v1.2.1 From c281af749dd7d3ffa68f82d765971642e9b2c4bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:46 -0600 Subject: driver/led/tlc59116f.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iece237a7f8c0719471c6110a0ee2cee27d0d59e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730003 Reviewed-by: Jeremy Bettis --- driver/led/tlc59116f.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/driver/led/tlc59116f.c b/driver/led/tlc59116f.c index b1c16a921b..dc40bfe7c9 100644 --- a/driver/led/tlc59116f.c +++ b/driver/led/tlc59116f.c @@ -14,13 +14,13 @@ #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "TLC59116F: " fmt, ##args) #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "TLC59116F: " fmt, ##args) -#define TLC59116F_BUF_SIZE (SIZE_OF_RGB * TLC59116F_GRID_SIZE) -#define TLC59116_MODE_BIT_SLEEP 4 +#define TLC59116F_BUF_SIZE (SIZE_OF_RGB * TLC59116F_GRID_SIZE) +#define TLC59116_MODE_BIT_SLEEP 4 static int tlc59116f_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value) { - return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, - &addr, sizeof(addr), value, sizeof(*value)); + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, &addr, + sizeof(addr), value, sizeof(*value)); } static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) @@ -30,8 +30,8 @@ static int tlc59116f_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) [1] = value, }; - return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, - buf, sizeof(buf), NULL, 0); + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf, + sizeof(buf), NULL, 0); } static int tlc59116f_reset(struct rgbkbd *ctx) @@ -75,7 +75,7 @@ static int tlc59116f_enable(struct rgbkbd *ctx, bool enable) } static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset, - struct rgb_s *color, uint8_t len) + struct rgb_s *color, uint8_t len) { uint8_t buf[sizeof(offset) + TLC59116F_BUF_SIZE]; const int frame_len = len * SIZE_OF_RGB + sizeof(offset); @@ -86,20 +86,19 @@ static int tlc59116f_set_color(struct rgbkbd *ctx, uint8_t offset, return EC_ERROR_OVERFLOW; } - buf[0] = TLC59116_AI_BRIGHTNESS_ONLY | - (frame_offset + TLC59116F_PWM0); + buf[0] = TLC59116_AI_BRIGHTNESS_ONLY | (frame_offset + TLC59116F_PWM0); for (i = 0; i < len; i++) { buf[i * SIZE_OF_RGB + 1] = color[i].r; buf[i * SIZE_OF_RGB + 2] = color[i].g; buf[i * SIZE_OF_RGB + 3] = color[i].b; } - return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, - buf, frame_len, NULL, 0); + return i2c_xfer(ctx->cfg->i2c, TLC59116F_I2C_ADDR_FLAG, buf, frame_len, + NULL, 0); } static int tlc59116f_set_scale(struct rgbkbd *ctx, uint8_t offset, - struct rgb_s scale, uint8_t len) + struct rgb_s scale, uint8_t len) { /* tlc59116f not support scale function */ return EC_SUCCESS; -- cgit v1.2.1 From a5fa87dbe34fa3bc061bf3a15db380b67491d42f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:23 -0600 Subject: common/dptf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I538b37b68a2451aed9d9f87626740b24fd1d1db9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729605 Reviewed-by: Jeremy Bettis --- common/dptf.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/common/dptf.c b/common/dptf.c index 28ccff34f2..f43dd68c68 100644 --- a/common/dptf.c +++ b/common/dptf.c @@ -19,14 +19,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DPTF, outstr) -#define CPRINTS(format, args...) cprints(CC_DPTF, format, ## args) +#define CPRINTS(format, args...) cprints(CC_DPTF, format, ##args) /*****************************************************************************/ /* DPTF temperature thresholds */ static struct { - int temp; /* degrees K, negative for disabled */ - cond_t over; /* watch for crossings */ + int temp; /* degrees K, negative for disabled */ + cond_t over; /* watch for crossings */ } dptf_threshold[TEMP_SENSOR_COUNT][DPTF_THRESHOLDS_PER_SENSOR]; _STATIC_ASSERT(TEMP_SENSOR_COUNT > 0, "CONFIG_PLATFORM_EC_DPTF enabled, but no temp sensors"); @@ -40,7 +40,6 @@ static void dptf_init(void) dptf_threshold[id][t].temp = -1; cond_init(&dptf_threshold[id][t].over, 0); } - } DECLARE_HOOK(HOOK_INIT, dptf_init, HOOK_PRIO_DEFAULT); @@ -72,9 +71,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp) } for (i = 0; i < DPTF_THRESHOLDS_PER_SENSOR; i++) { - max = dptf_threshold[sensor_id][i].temp; - if (max < 0) /* disabled? */ + if (max < 0) /* disabled? */ continue; if (temp >= max) @@ -83,14 +81,12 @@ static int dptf_check_temp_threshold(int sensor_id, int temp) cond_set_false(&dptf_threshold[sensor_id][i].over); if (cond_went_true(&dptf_threshold[sensor_id][i].over)) { - CPRINTS("DPTF over threshold [%d][%d", - sensor_id, i); + CPRINTS("DPTF over threshold [%d][%d", sensor_id, i); atomic_or(&dptf_seen, BIT(sensor_id)); tripped = 1; } if (cond_went_false(&dptf_threshold[sensor_id][i].over)) { - CPRINTS("DPTF under threshold [%d][%d", - sensor_id, i); + CPRINTS("DPTF under threshold [%d][%d", sensor_id, i); atomic_or(&dptf_seen, BIT(sensor_id)); tripped = 1; } @@ -101,8 +97,8 @@ static int dptf_check_temp_threshold(int sensor_id, int temp) void dptf_set_temp_threshold(int sensor_id, int temp, int idx, int enable) { - CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled", - sensor_id, K_TO_C(temp), idx, enable ? "en" : "dis"); + CPRINTS("DPTF sensor %d, threshold %d C, index %d, %sabled", sensor_id, + K_TO_C(temp), idx, enable ? "en" : "dis"); if ((sensor_id >= TEMP_SENSOR_COUNT) || (idx >= DPTF_THRESHOLDS_PER_SENSOR)) { @@ -201,6 +197,5 @@ static int command_dptftemp(int argc, char **argv) ccprintf("AP seen mask: 0x%08x\n", (int)dptf_seen); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp, - NULL, +DECLARE_CONSOLE_COMMAND(dptftemp, command_dptftemp, NULL, "Print DPTF thermal parameters (degrees Kelvin)"); -- cgit v1.2.1 From ca614f88cd8629df0a8bf27da2a58ab6ba579e69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:49 -0600 Subject: chip/mchp/lpc_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifa890bb1ade5355793a2f2ca3503aafd828a41e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729246 Reviewed-by: Jeremy Bettis --- chip/mchp/lpc_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h index 434b307968..96a9542d2b 100644 --- a/chip/mchp/lpc_chip.h +++ b/chip/mchp/lpc_chip.h @@ -12,7 +12,7 @@ #include "espi.h" -#define MCHP_HOST_IF_LPC (0) +#define MCHP_HOST_IF_LPC (0) #define MCHP_HOST_IF_ESPI (1) /* eSPI Initialization functions */ -- cgit v1.2.1 From 8e16847d8fdab88a8eab978af00854f7a8b76c1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:57 -0600 Subject: chip/it83xx/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib9d9c7353bdc4fee0423e1326aff2368b4a5d419 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729209 Reviewed-by: Jeremy Bettis --- chip/it83xx/espi.c | 184 +++++++++++++++++++++-------------------------------- 1 file changed, 74 insertions(+), 110 deletions(-) diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index bef877449e..a67b3096ea 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -18,151 +18,119 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) struct vw_channel_t { - uint8_t index; /* VW index of signal */ - uint8_t level_mask; /* level bit of signal */ - uint8_t valid_mask; /* valid bit of signal */ + uint8_t index; /* VW index of signal */ + uint8_t level_mask; /* level bit of signal */ + uint8_t valid_mask; /* valid bit of signal */ }; /* VW settings after the controller enables the VW channel. */ static const struct vw_channel_t en_vw_setting[] = { - /* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */ +/* EC sends SUS_ACK# = 1 VW to PCH. That does not apply to GLK SoC. */ #ifndef CONFIG_CHIPSET_GEMINILAKE - {ESPI_SYSTEM_EVENT_VW_IDX_40, - VW_LEVEL_FIELD(0), - VW_VALID_FIELD(VW_IDX_40_SUS_ACK)}, + { ESPI_SYSTEM_EVENT_VW_IDX_40, VW_LEVEL_FIELD(0), + VW_VALID_FIELD(VW_IDX_40_SUS_ACK) }, #endif }; /* VW settings after the controller enables the OOB channel. */ static const struct vw_channel_t en_oob_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(0), - VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)}, + { ESPI_SYSTEM_EVENT_VW_IDX_4, VW_LEVEL_FIELD(0), + VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK) }, }; /* VW settings after the controller enables the flash channel. */ static const struct vw_channel_t en_flash_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE), - VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)}, + { ESPI_SYSTEM_EVENT_VW_IDX_5, VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE), + VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE) }, }; /* VW settings at host startup */ static const struct vw_channel_t vw_host_startup_setting[] = { - {ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | - VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK), - VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | - VW_IDX_6_RCIN | VW_IDX_6_HOST_RST_ACK)}, + { ESPI_SYSTEM_EVENT_VW_IDX_6, + VW_LEVEL_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN | + VW_IDX_6_HOST_RST_ACK), + VW_VALID_FIELD(VW_IDX_6_SCI | VW_IDX_6_SMI | VW_IDX_6_RCIN | + VW_IDX_6_HOST_RST_ACK) }, }; #define VW_CHAN(name, idx, level, valid) \ - [(name - VW_SIGNAL_START)] = {idx, level, valid} + [(name - VW_SIGNAL_START)] = { idx, level, valid } /* VW signals used in eSPI (NOTE: must match order of enum espi_vw_signal). */ static const struct vw_channel_t vw_channel_list[] = { /* index 02h: controller to peripheral. */ - VW_CHAN(VW_SLP_S3_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, + VW_CHAN(VW_SLP_S3_L, ESPI_SYSTEM_EVENT_VW_IDX_2, VW_LEVEL_FIELD(VW_IDX_2_SLP_S3), VW_VALID_FIELD(VW_IDX_2_SLP_S3)), - VW_CHAN(VW_SLP_S4_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, + VW_CHAN(VW_SLP_S4_L, ESPI_SYSTEM_EVENT_VW_IDX_2, VW_LEVEL_FIELD(VW_IDX_2_SLP_S4), VW_VALID_FIELD(VW_IDX_2_SLP_S4)), - VW_CHAN(VW_SLP_S5_L, - ESPI_SYSTEM_EVENT_VW_IDX_2, + VW_CHAN(VW_SLP_S5_L, ESPI_SYSTEM_EVENT_VW_IDX_2, VW_LEVEL_FIELD(VW_IDX_2_SLP_S5), VW_VALID_FIELD(VW_IDX_2_SLP_S5)), /* index 03h: controller to peripheral. */ - VW_CHAN(VW_SUS_STAT_L, - ESPI_SYSTEM_EVENT_VW_IDX_3, + VW_CHAN(VW_SUS_STAT_L, ESPI_SYSTEM_EVENT_VW_IDX_3, VW_LEVEL_FIELD(VW_IDX_3_SUS_STAT), VW_VALID_FIELD(VW_IDX_3_SUS_STAT)), - VW_CHAN(VW_PLTRST_L, - ESPI_SYSTEM_EVENT_VW_IDX_3, + VW_CHAN(VW_PLTRST_L, ESPI_SYSTEM_EVENT_VW_IDX_3, VW_LEVEL_FIELD(VW_IDX_3_PLTRST), VW_VALID_FIELD(VW_IDX_3_PLTRST)), - VW_CHAN(VW_OOB_RST_WARN, - ESPI_SYSTEM_EVENT_VW_IDX_3, + VW_CHAN(VW_OOB_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_3, VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN), VW_VALID_FIELD(VW_IDX_3_OOB_RST_WARN)), /* index 04h: peripheral to controller. */ - VW_CHAN(VW_OOB_RST_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_4, + VW_CHAN(VW_OOB_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_4, VW_LEVEL_FIELD(VW_IDX_4_OOB_RST_ACK), VW_VALID_FIELD(VW_IDX_4_OOB_RST_ACK)), - VW_CHAN(VW_WAKE_L, - ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(VW_IDX_4_WAKE), - VW_VALID_FIELD(VW_IDX_4_WAKE)), - VW_CHAN(VW_PME_L, - ESPI_SYSTEM_EVENT_VW_IDX_4, - VW_LEVEL_FIELD(VW_IDX_4_PME), - VW_VALID_FIELD(VW_IDX_4_PME)), + VW_CHAN(VW_WAKE_L, ESPI_SYSTEM_EVENT_VW_IDX_4, + VW_LEVEL_FIELD(VW_IDX_4_WAKE), VW_VALID_FIELD(VW_IDX_4_WAKE)), + VW_CHAN(VW_PME_L, ESPI_SYSTEM_EVENT_VW_IDX_4, + VW_LEVEL_FIELD(VW_IDX_4_PME), VW_VALID_FIELD(VW_IDX_4_PME)), /* index 05h: peripheral to controller. */ - VW_CHAN(VW_ERROR_FATAL, - ESPI_SYSTEM_EVENT_VW_IDX_5, - VW_LEVEL_FIELD(VW_IDX_5_FATAL), - VW_VALID_FIELD(VW_IDX_5_FATAL)), - VW_CHAN(VW_ERROR_NON_FATAL, - ESPI_SYSTEM_EVENT_VW_IDX_5, + VW_CHAN(VW_ERROR_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5, + VW_LEVEL_FIELD(VW_IDX_5_FATAL), VW_VALID_FIELD(VW_IDX_5_FATAL)), + VW_CHAN(VW_ERROR_NON_FATAL, ESPI_SYSTEM_EVENT_VW_IDX_5, VW_LEVEL_FIELD(VW_IDX_5_NON_FATAL), VW_VALID_FIELD(VW_IDX_5_NON_FATAL)), - VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE, - ESPI_SYSTEM_EVENT_VW_IDX_5, + VW_CHAN(VW_PERIPHERAL_BTLD_STATUS_DONE, ESPI_SYSTEM_EVENT_VW_IDX_5, VW_LEVEL_FIELD(VW_IDX_5_BTLD_STATUS_DONE), VW_VALID_FIELD(VW_IDX_5_BTLD_STATUS_DONE)), /* index 06h: peripheral to controller. */ - VW_CHAN(VW_SCI_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SCI), - VW_VALID_FIELD(VW_IDX_6_SCI)), - VW_CHAN(VW_SMI_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_SMI), - VW_VALID_FIELD(VW_IDX_6_SMI)), - VW_CHAN(VW_RCIN_L, - ESPI_SYSTEM_EVENT_VW_IDX_6, - VW_LEVEL_FIELD(VW_IDX_6_RCIN), - VW_VALID_FIELD(VW_IDX_6_RCIN)), - VW_CHAN(VW_HOST_RST_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_6, + VW_CHAN(VW_SCI_L, ESPI_SYSTEM_EVENT_VW_IDX_6, + VW_LEVEL_FIELD(VW_IDX_6_SCI), VW_VALID_FIELD(VW_IDX_6_SCI)), + VW_CHAN(VW_SMI_L, ESPI_SYSTEM_EVENT_VW_IDX_6, + VW_LEVEL_FIELD(VW_IDX_6_SMI), VW_VALID_FIELD(VW_IDX_6_SMI)), + VW_CHAN(VW_RCIN_L, ESPI_SYSTEM_EVENT_VW_IDX_6, + VW_LEVEL_FIELD(VW_IDX_6_RCIN), VW_VALID_FIELD(VW_IDX_6_RCIN)), + VW_CHAN(VW_HOST_RST_ACK, ESPI_SYSTEM_EVENT_VW_IDX_6, VW_LEVEL_FIELD(VW_IDX_6_HOST_RST_ACK), VW_VALID_FIELD(VW_IDX_6_HOST_RST_ACK)), /* index 07h: controller to peripheral. */ - VW_CHAN(VW_HOST_RST_WARN, - ESPI_SYSTEM_EVENT_VW_IDX_7, + VW_CHAN(VW_HOST_RST_WARN, ESPI_SYSTEM_EVENT_VW_IDX_7, VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN), VW_VALID_FIELD(VW_IDX_7_HOST_RST_WARN)), /* index 40h: peripheral to controller. */ - VW_CHAN(VW_SUS_ACK, - ESPI_SYSTEM_EVENT_VW_IDX_40, + VW_CHAN(VW_SUS_ACK, ESPI_SYSTEM_EVENT_VW_IDX_40, VW_LEVEL_FIELD(VW_IDX_40_SUS_ACK), VW_VALID_FIELD(VW_IDX_40_SUS_ACK)), /* index 41h: controller to peripheral. */ - VW_CHAN(VW_SUS_WARN_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, + VW_CHAN(VW_SUS_WARN_L, ESPI_SYSTEM_EVENT_VW_IDX_41, VW_LEVEL_FIELD(VW_IDX_41_SUS_WARN), VW_VALID_FIELD(VW_IDX_41_SUS_WARN)), - VW_CHAN(VW_SUS_PWRDN_ACK_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, + VW_CHAN(VW_SUS_PWRDN_ACK_L, ESPI_SYSTEM_EVENT_VW_IDX_41, VW_LEVEL_FIELD(VW_IDX_41_SUS_PWRDN_ACK), VW_VALID_FIELD(VW_IDX_41_SUS_PWRDN_ACK)), - VW_CHAN(VW_SLP_A_L, - ESPI_SYSTEM_EVENT_VW_IDX_41, + VW_CHAN(VW_SLP_A_L, ESPI_SYSTEM_EVENT_VW_IDX_41, VW_LEVEL_FIELD(VW_IDX_41_SLP_A), VW_VALID_FIELD(VW_IDX_41_SLP_A)), /* index 42h: controller to peripheral. */ - VW_CHAN(VW_SLP_LAN, - ESPI_SYSTEM_EVENT_VW_IDX_42, + VW_CHAN(VW_SLP_LAN, ESPI_SYSTEM_EVENT_VW_IDX_42, VW_LEVEL_FIELD(VW_IDX_42_SLP_LAN), VW_VALID_FIELD(VW_IDX_42_SLP_LAN)), - VW_CHAN(VW_SLP_WLAN, - ESPI_SYSTEM_EVENT_VW_IDX_42, + VW_CHAN(VW_SLP_WLAN, ESPI_SYSTEM_EVENT_VW_IDX_42, VW_LEVEL_FIELD(VW_IDX_42_SLP_WLAN), VW_VALID_FIELD(VW_IDX_42_SLP_WLAN)), }; @@ -221,11 +189,11 @@ int espi_vw_get_wire(enum espi_vw_signal signal) /* Not valid */ if (!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) & - vw_channel_list[i].valid_mask)) + vw_channel_list[i].valid_mask)) return 0; return !!(IT83XX_ESPI_VWIDX(vw_channel_list[i].index) & - vw_channel_list[i].level_mask); + vw_channel_list[i].level_mask); } /** @@ -265,7 +233,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal) /* Configure virtual wire outputs */ static void espi_configure_vw(const struct vw_channel_t *settings, - size_t entries) + size_t entries) { size_t i; @@ -277,13 +245,13 @@ static void espi_configure_vw(const struct vw_channel_t *settings, static void espi_vw_host_startup(void) { espi_configure_vw(vw_host_startup_setting, - ARRAY_SIZE(vw_host_startup_setting)); + ARRAY_SIZE(vw_host_startup_setting)); } static void espi_vw_no_isr(uint8_t flag_changed, uint8_t vw_evt) { CPRINTS("espi VW interrupt event is ignored! (bit%d at VWCTRL1)", - vw_evt); + vw_evt); } #ifndef CONFIG_CHIPSET_GEMINILAKE @@ -298,7 +266,7 @@ static void espi_vw_idx7_isr(uint8_t flag_changed, uint8_t vw_evt) { if (flag_changed & VW_LEVEL_FIELD(VW_IDX_7_HOST_RST_WARN)) espi_vw_set_wire(VW_HOST_RST_ACK, - espi_vw_get_wire(VW_HOST_RST_WARN)); + espi_vw_get_wire(VW_HOST_RST_WARN)); } #ifdef CONFIG_CHIPSET_RESET_HOOK @@ -329,7 +297,7 @@ static void espi_vw_idx3_isr(uint8_t flag_changed, uint8_t vw_evt) if (flag_changed & VW_LEVEL_FIELD(VW_IDX_3_OOB_RST_WARN)) espi_vw_set_wire(VW_OOB_RST_ACK, - espi_vw_get_wire(VW_OOB_RST_WARN)); + espi_vw_get_wire(VW_OOB_RST_WARN)); } static void espi_vw_idx2_isr(uint8_t flag_changed, uint8_t vw_evt) @@ -353,25 +321,25 @@ struct vw_interrupt_t { */ #ifdef CONFIG_CHIPSET_GEMINILAKE static const struct vw_interrupt_t vw_isr_list[] = { - [0] = {espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2}, - [1] = {espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3}, - [2] = {espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7}, - [3] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_41}, - [4] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42}, - [5] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43}, - [6] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44}, - [7] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47}, + [0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 }, + [1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 }, + [2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 }, + [3] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 }, + [4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 }, + [5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 }, + [6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 }, + [7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 }, }; #else static const struct vw_interrupt_t vw_isr_list[] = { - [0] = {espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2}, - [1] = {espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3}, - [2] = {espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7}, - [3] = {espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41}, - [4] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42}, - [5] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43}, - [6] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44}, - [7] = {espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47}, + [0] = { espi_vw_idx2_isr, ESPI_SYSTEM_EVENT_VW_IDX_2 }, + [1] = { espi_vw_idx3_isr, ESPI_SYSTEM_EVENT_VW_IDX_3 }, + [2] = { espi_vw_idx7_isr, ESPI_SYSTEM_EVENT_VW_IDX_7 }, + [3] = { espi_vw_idx41_isr, ESPI_SYSTEM_EVENT_VW_IDX_41 }, + [4] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_42 }, + [5] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_43 }, + [6] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_44 }, + [7] = { espi_vw_no_isr, ESPI_SYSTEM_EVENT_VW_IDX_47 }, }; #endif @@ -490,7 +458,7 @@ static void espi_enable_reset(void) #endif IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) | - (config << IT83XX_GPIO_GCR_LPC_RST_POS); + (config << IT83XX_GPIO_GCR_LPC_RST_POS); /* enable interrupt of EC's espi_reset pin */ gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L); @@ -537,14 +505,10 @@ static void espi_no_isr(uint8_t evt) * IT83XX_ESPI_ESGCTRL0 register. */ static void (*espi_isr[])(uint8_t evt) = { - [0] = espi_no_isr, - [1] = espi_vw_en_asserted, - [2] = espi_oob_en_asserted, - [3] = espi_flash_en_asserted, - [4] = espi_no_isr, - [5] = espi_no_isr, - [6] = espi_no_isr, - [7] = espi_no_isr, + [0] = espi_no_isr, [1] = espi_vw_en_asserted, + [2] = espi_oob_en_asserted, [3] = espi_flash_en_asserted, + [4] = espi_no_isr, [5] = espi_no_isr, + [6] = espi_no_isr, [7] = espi_no_isr, }; void espi_interrupt(void) -- cgit v1.2.1 From c30218268ccf81fc9b22867dbccc170ac85083da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:29 -0600 Subject: zephyr/include/dt-bindings/wake_mask_event_defines.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia80624c5b99e86f214226ee251d41e73e1c5db6f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730717 Reviewed-by: Jeremy Bettis --- .../include/dt-bindings/wake_mask_event_defines.h | 92 +++++++++++----------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/zephyr/include/dt-bindings/wake_mask_event_defines.h b/zephyr/include/dt-bindings/wake_mask_event_defines.h index 168c8425e5..b399410639 100644 --- a/zephyr/include/dt-bindings/wake_mask_event_defines.h +++ b/zephyr/include/dt-bindings/wake_mask_event_defines.h @@ -19,52 +19,52 @@ * defined in this file. */ -#define MKBP_EVENT_KEY_MATRIX BIT(0) -#define MKBP_EVENT_HOST_EVENT BIT(1) -#define MKBP_EVENT_SENSOR_FIFO BIT(2) -#define MKBP_EVENT_BUTTON BIT(3) -#define MKBP_EVENT_SWITCH BIT(4) -#define MKBP_EVENT_FINGERPRINT BIT(5) -#define MKBP_EVENT_SYSRQ BIT(6) -#define MKBP_EVENT_HOST_EVENT64 BIT(7) -#define MKBP_EVENT_CEC_EVENT BIT(8) -#define MKBP_EVENT_CEC_MESSAGE BIT(9) -#define MKBP_EVENT_DP_ALT_MODE_ENTERED BIT(10) -#define MKBP_EVENT_ONLINE_CALIBRATION BIT(11) -#define MKBP_EVENT_PCHG BIT(12) +#define MKBP_EVENT_KEY_MATRIX BIT(0) +#define MKBP_EVENT_HOST_EVENT BIT(1) +#define MKBP_EVENT_SENSOR_FIFO BIT(2) +#define MKBP_EVENT_BUTTON BIT(3) +#define MKBP_EVENT_SWITCH BIT(4) +#define MKBP_EVENT_FINGERPRINT BIT(5) +#define MKBP_EVENT_SYSRQ BIT(6) +#define MKBP_EVENT_HOST_EVENT64 BIT(7) +#define MKBP_EVENT_CEC_EVENT BIT(8) +#define MKBP_EVENT_CEC_MESSAGE BIT(9) +#define MKBP_EVENT_DP_ALT_MODE_ENTERED BIT(10) +#define MKBP_EVENT_ONLINE_CALIBRATION BIT(11) +#define MKBP_EVENT_PCHG BIT(12) -#define HOST_EVENT_NONE 0 -#define HOST_EVENT_LID_CLOSED BIT(0) -#define HOST_EVENT_LID_OPEN BIT(1) -#define HOST_EVENT_POWER_BUTTON BIT(2) -#define HOST_EVENT_AC_CONNECTED BIT(3) -#define HOST_EVENT_AC_DISCONNECTED BIT(4) -#define HOST_EVENT_BATTERY_LOW BIT(5) -#define HOST_EVENT_BATTERY_CRITICAL BIT(6) -#define HOST_EVENT_BATTERY BIT(7) -#define HOST_EVENT_THERMAL_THRESHOLD BIT(8) -#define HOST_EVENT_DEVICE BIT(9) -#define HOST_EVENT_THERMAL BIT(10) -#define HOST_EVENT_USB_CHARGER BIT(11) -#define HOST_EVENT_KEY_PRESSED BIT(12) -#define HOST_EVENT_INTERFACE_READY BIT(13) -#define HOST_EVENT_KEYBOARD_RECOVERY BIT(14) -#define HOST_EVENT_THERMAL_SHUTDOWN BIT(15) -#define HOST_EVENT_BATTERY_SHUTDOWN BIT(16) -#define HOST_EVENT_THROTTLE_START BIT(17) -#define HOST_EVENT_THROTTLE_STOP BIT(18) -#define HOST_EVENT_HANG_DETECT BIT(19) -#define HOST_EVENT_HANG_REBOOT BIT(20) -#define HOST_EVENT_PD_MCU BIT(21) -#define HOST_EVENT_BATTERY_STATUS BIT(22) -#define HOST_EVENT_PANIC BIT(23) -#define HOST_EVENT_KEYBOARD_FASTBOOT BIT(24) -#define HOST_EVENT_RTC BIT(25) -#define HOST_EVENT_MKBP BIT(26) -#define HOST_EVENT_USB_MUX BIT(27) -#define HOST_EVENT_MODE_CHANGE BIT(28) -#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT BIT(29) -#define HOST_EVENT_WOV BIT(30) -#define HOST_EVENT_INVALID BIT(31) +#define HOST_EVENT_NONE 0 +#define HOST_EVENT_LID_CLOSED BIT(0) +#define HOST_EVENT_LID_OPEN BIT(1) +#define HOST_EVENT_POWER_BUTTON BIT(2) +#define HOST_EVENT_AC_CONNECTED BIT(3) +#define HOST_EVENT_AC_DISCONNECTED BIT(4) +#define HOST_EVENT_BATTERY_LOW BIT(5) +#define HOST_EVENT_BATTERY_CRITICAL BIT(6) +#define HOST_EVENT_BATTERY BIT(7) +#define HOST_EVENT_THERMAL_THRESHOLD BIT(8) +#define HOST_EVENT_DEVICE BIT(9) +#define HOST_EVENT_THERMAL BIT(10) +#define HOST_EVENT_USB_CHARGER BIT(11) +#define HOST_EVENT_KEY_PRESSED BIT(12) +#define HOST_EVENT_INTERFACE_READY BIT(13) +#define HOST_EVENT_KEYBOARD_RECOVERY BIT(14) +#define HOST_EVENT_THERMAL_SHUTDOWN BIT(15) +#define HOST_EVENT_BATTERY_SHUTDOWN BIT(16) +#define HOST_EVENT_THROTTLE_START BIT(17) +#define HOST_EVENT_THROTTLE_STOP BIT(18) +#define HOST_EVENT_HANG_DETECT BIT(19) +#define HOST_EVENT_HANG_REBOOT BIT(20) +#define HOST_EVENT_PD_MCU BIT(21) +#define HOST_EVENT_BATTERY_STATUS BIT(22) +#define HOST_EVENT_PANIC BIT(23) +#define HOST_EVENT_KEYBOARD_FASTBOOT BIT(24) +#define HOST_EVENT_RTC BIT(25) +#define HOST_EVENT_MKBP BIT(26) +#define HOST_EVENT_USB_MUX BIT(27) +#define HOST_EVENT_MODE_CHANGE BIT(28) +#define HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT BIT(29) +#define HOST_EVENT_WOV BIT(30) +#define HOST_EVENT_INVALID BIT(31) #endif /* DT_BINDINGS_WAKE_MASK_EVENT_DEFINES_H_ */ -- cgit v1.2.1 From 35d95a54393df25c274753737f8064fb2eb78199 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:39 -0600 Subject: board/copano/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe6ad3a5385bb96cb42c80800d51fa832e7cc858 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728176 Reviewed-by: Jeremy Bettis --- board/copano/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/copano/led.c b/board/copano/led.c index a5b535000a..fbd97d7a5d 100644 --- a/board/copano/led.c +++ b/board/copano/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 03fd7a7d21c7644348b5da9ee4734778b3043dc1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:26 -0600 Subject: driver/als_isl29035.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68834cb0f78540f8b55bff25e1df241334e573e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729926 Reviewed-by: Jeremy Bettis --- driver/als_isl29035.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/als_isl29035.h b/driver/als_isl29035.h index 153ba148f9..ad544e2590 100644 --- a/driver/als_isl29035.h +++ b/driver/als_isl29035.h @@ -11,4 +11,4 @@ int isl29035_init(void); int isl29035_read_lux(int *lux, int af); -#endif /* __CROS_EC_ALS_ISL29035_H */ +#endif /* __CROS_EC_ALS_ISL29035_H */ -- cgit v1.2.1 From 5fe1e4b667a81a4d0fc1b41f03040b14fc609783 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:56 -0600 Subject: board/volmar/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I96b6bcda48802e459fdce4f54061d0a88c10ae66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729066 Reviewed-by: Jeremy Bettis --- board/volmar/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/volmar/fw_config.c b/board/volmar/fw_config.c index da56362496..5d2cc0fe3f 100644 --- a/board/volmar/fw_config.c +++ b/board/volmar/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union volmar_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From ba55ffd89f44f4510095478d694b9721ae3bc333 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:17 -0600 Subject: common/motion_orientation.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ce2fc3bbaccbab8062712bda1dc82996104eb99 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729679 Reviewed-by: Jeremy Bettis --- common/motion_orientation.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/common/motion_orientation.c b/common/motion_orientation.c index 9a20ff8499..a8a87294db 100644 --- a/common/motion_orientation.c +++ b/common/motion_orientation.c @@ -18,9 +18,9 @@ static const intv3_t orientation_modes[] = { [MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE] = { 0, 1, 0 }, }; -enum motionsensor_orientation motion_orientation_remap( - const struct motion_sensor_t *s, - enum motionsensor_orientation orientation) +enum motionsensor_orientation +motion_orientation_remap(const struct motion_sensor_t *s, + enum motionsensor_orientation orientation) { enum motionsensor_orientation rotated_orientation; const intv3_t *orientation_v; @@ -31,7 +31,8 @@ enum motionsensor_orientation motion_orientation_remap( orientation_v = &orientation_modes[orientation]; rotate(*orientation_v, *s->rot_standard_ref, rotated_orientation_v); - rotated_orientation = ((2 * rotated_orientation_v[1] + - rotated_orientation_v[0] + 4) % 5); + rotated_orientation = + ((2 * rotated_orientation_v[1] + rotated_orientation_v[0] + 4) % + 5); return rotated_orientation; } -- cgit v1.2.1 From 538bca302ee12db6a240d51076341f5f36c2fc5c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:11 -0600 Subject: include/capsense.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50159b190196faed88122f7e021e894e0e1bce30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730219 Reviewed-by: Jeremy Bettis --- include/capsense.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/capsense.h b/include/capsense.h index 2c0734aa4d..87fac926c3 100644 --- a/include/capsense.h +++ b/include/capsense.h @@ -11,4 +11,4 @@ void capsense_interrupt(enum gpio_signal signal); -#endif /* __CROS_EC_CAPSENSE_H */ +#endif /* __CROS_EC_CAPSENSE_H */ -- cgit v1.2.1 From 9b2f977173c1a4115fee1c92ef758893e6c68f3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:07 -0600 Subject: chip/mchp/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I786fc7a77136b1639bc4067ac549b5ced78ffc87 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729226 Reviewed-by: Jeremy Bettis --- chip/mchp/config_chip.h | 80 ++++++++++++++++++++++++------------------------- 1 file changed, 39 insertions(+), 41 deletions(-) diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index cf7ead512a..fed77a010c 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -20,11 +20,11 @@ /* Use a bigger console output buffer */ #undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 1024 +#define CONFIG_UART_TX_BUF_SIZE 1024 /* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL_MS 250 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* * Enable chip_pre_init called from main @@ -48,14 +48,14 @@ * addresses. Define fake peripheral addresses that aren't used by * peripherals on the board. */ -#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C4_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C5_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C6_SLAVE_ADDRS 0xE3E1 -#define CONFIG_MCHP_I2C7_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C1_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C2_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C3_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C4_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C5_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C6_SLAVE_ADDRS 0xE3E1 +#define CONFIG_MCHP_I2C7_SLAVE_ADDRS 0xE3E1 /************************************************************************/ /* Memory mapping */ @@ -74,45 +74,44 @@ /* Define our RAM layout. */ #if defined(CHIP_FAMILY_MEC172X) -#define CONFIG_MEC_SRAM_BASE_START 0x000C0000 -#define CONFIG_MEC_SRAM_BASE_END (0x00128000 - (2 * 1024)) +#define CONFIG_MEC_SRAM_BASE_START 0x000C0000 +#define CONFIG_MEC_SRAM_BASE_END (0x00128000 - (2 * 1024)) #else -#define CONFIG_MEC_SRAM_BASE_START 0x000E0000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 +#define CONFIG_MEC_SRAM_BASE_START 0x000E0000 +#define CONFIG_MEC_SRAM_BASE_END 0x00120000 #endif -#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_MEC_SRAM_BASE_START) +#define CONFIG_MEC_SRAM_SIZE \ + (CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START) /* 64k Data RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00010000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_RAM_SIZE) +#define CONFIG_RAM_SIZE 0x00010000 +#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE) /* System stack size */ /* was 1024, temporarily expanded to 2048 for debug */ -#define CONFIG_STACK_SIZE 2048 +#define CONFIG_STACK_SIZE 2048 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 672 -#define LARGER_TASK_STACK_SIZE 800 -#define VENTI_TASK_STACK_SIZE 928 -#define ULTRA_TASK_STACK_SIZE 1056 -#define TRENTA_TASK_STACK_SIZE 1184 +#define IDLE_TASK_STACK_SIZE 672 +#define LARGER_TASK_STACK_SIZE 800 +#define VENTI_TASK_STACK_SIZE 928 +#define ULTRA_TASK_STACK_SIZE 1056 +#define TRENTA_TASK_STACK_SIZE 1184 -#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */ -#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */ -#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */ -#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */ +#define CHARGER_TASK_STACK_SIZE 1024 /* 640 */ +#define HOOKS_TASK_STACK_SIZE 1024 /* 640 */ +#define CONSOLE_TASK_STACK_SIZE 1024 /* 640 */ +#define HOST_CMD_TASK_STACK_SIZE 1024 /* 640 */ /* * TODO: Large stack consumption * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 */ /* original = 800, if stack exceptions expand to 1024 for debug */ -#define PD_TASK_STACK_SIZE 2048 +#define PD_TASK_STACK_SIZE 2048 /* Default task stack size */ -#define TASK_STACK_SIZE 672 +#define TASK_STACK_SIZE 672 /************************************************************************/ /* Define our flash layout. */ @@ -134,20 +133,20 @@ #endif /* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 +#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 +#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* Program memory base address */ #if defined(CHIP_FAMILY_MEC172X) -#define CONFIG_PROGRAM_MEMORY_BASE 0x000C0000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x000C0000 #else -#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x000E0000 #endif /* @@ -232,14 +231,13 @@ * GPIO(PCH_SLP_S0_L, PIN(0x89), GPIO_INPUT | GPIO_PULL_DOWN) */ #define GPIO_BANK(index) ((index) >> 5) -#define GPIO_BANK_MASK(index) (1ul << ((index) & 0x1F)) +#define GPIO_BANK_MASK(index) (1ul << ((index)&0x1F)) #define GPIO_PIN(index) GPIO_BANK(index), GPIO_BANK_MASK(index) #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) #ifndef __ASSEMBLER__ - #endif /* #ifndef __ASSEMBLER__ */ -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From fa61825b75e43c3bced78cdfac1f69c1194bd397 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:21 -0600 Subject: chip/npcx/audio_codec_i2s_rx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I845aa68c80e85337f410fa07562dfb5b581b7b49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729366 Reviewed-by: Jeremy Bettis --- chip/npcx/audio_codec_i2s_rx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/npcx/audio_codec_i2s_rx.c b/chip/npcx/audio_codec_i2s_rx.c index 12c4173048..fc44b35d5f 100644 --- a/chip/npcx/audio_codec_i2s_rx.c +++ b/chip/npcx/audio_codec_i2s_rx.c @@ -8,7 +8,7 @@ #include "ec_commands.h" #include "wov_chip.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) int audio_codec_i2s_rx_enable(void) { -- cgit v1.2.1 From 32c00d82db25783f3ba7a644e258fb378e989d81 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:24 -0600 Subject: board/anahera/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If43cc3efe63e554dfaca729f5de528c26612ecca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727104 Reviewed-by: Jeremy Bettis --- board/anahera/board.h | 126 +++++++++++++++++++++++--------------------------- 1 file changed, 58 insertions(+), 68 deletions(-) diff --git a/board/anahera/board.h b/board/anahera/board.h index 4730eba213..4a38765a65 100644 --- a/board/anahera/board.h +++ b/board/anahera/board.h @@ -29,7 +29,7 @@ #undef CONFIG_VOLUME_BUTTONS /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB #define CONFIG_USBC_RETIMER_PS8811 @@ -38,7 +38,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_FRS_PPC @@ -48,17 +48,17 @@ #define CONFIG_USBC_PPC_NX20P3483 /* TODO: b/193452481 - measure and check these values on redrix */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -66,64 +66,64 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_USB_A0_RETIMER NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_A1_RETIMER NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_A0_RETIMER NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_A1_RETIMER NPCX_I2C_PORT6_1 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x58 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -141,17 +141,17 @@ #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Fan features */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT #define CONFIG_CUSTOM_FAN_CONTROL -#define RPM_DEVIATION 1 +#define RPM_DEVIATION 1 /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* Keyboard features */ #define CONFIG_KEYBOARD_FACTORY_TEST @@ -160,7 +160,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -180,11 +180,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; enum battery_type { BATTERY_SIMPLO_HIGHPOWER, @@ -193,20 +189,14 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #ifdef CONFIG_KEYBOARD_FACTORY_TEST extern const int keyboard_factory_scan_pins[][2]; -- cgit v1.2.1 From 49d5a3e672530100ba361bb9b1dc57edd91f0db8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:40 -0600 Subject: zephyr/include/emul/emul_lis2dw12.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe0d6ed0ad0a008e4bc7d0d0faca9195f7a8c370 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730721 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_lis2dw12.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/include/emul/emul_lis2dw12.h b/zephyr/include/emul/emul_lis2dw12.h index c61751183e..a0ca6be8b5 100644 --- a/zephyr/include/emul/emul_lis2dw12.h +++ b/zephyr/include/emul/emul_lis2dw12.h @@ -87,8 +87,7 @@ uint8_t lis2dw12_emul_peek_lpmode(struct i2c_emul *emul); * @param reading array of int X, Y, and Z readings. * @return 0 on success, or -EINVAL if readings are out of bounds. */ -int lis2dw12_emul_set_accel_reading(const struct emul *emul, - intv3_t reading); +int lis2dw12_emul_set_accel_reading(const struct emul *emul, intv3_t reading); /** * @brief Clears the current accelerometer reading and resets the -- cgit v1.2.1 From 04e7397198c8ef62ca9c267220b9efff62481a47 Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Wed, 29 Jun 2022 14:50:48 +0800 Subject: tentacruel: Add AS3GXXE3KA C140254 for tentacruel Config the EC battery setting. BUG=b:237432841 TEST=zmake build tentacruel --clobber BRANCH=None Signed-off-by: jeffrey_lin Change-Id: I97533da69c1f22814452ebb009b93c513a7946fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733874 Reviewed-by: Ting Shen --- .../dts/bindings/battery/as3gxxe3ka,c140254.yaml | 56 ++++++++++++++++++++++ zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/projects/corsola/battery_tentacruel.dts | 4 +- 3 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 zephyr/dts/bindings/battery/as3gxxe3ka,c140254.yaml diff --git a/zephyr/dts/bindings/battery/as3gxxe3ka,c140254.yaml b/zephyr/dts/bindings/battery/as3gxxe3ka,c140254.yaml new file mode 100644 index 0000000000..313657b58b --- /dev/null +++ b/zephyr/dts/bindings/battery/as3gxxe3ka,c140254.yaml @@ -0,0 +1,56 @@ +description: "AS3GXXe3KA C140254" +compatible: "as3gxxe3ka,c140254" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "as3gxxe3ka,c140254" + + # Fuel gauge + manuf_name: + default: "AS3GXXe3KA" + device_name: + default: "C140254" + ship_mode_reg_addr: + default: 0x00 + ship_mode_reg_data: + default: [ 0x0010, 0x0010 ] + # Documentation: b/150833879 + # Charging/Discharging FETs Status + # Register SBS_PackStatus_ACCESS (0x99) + # Bit-3: XDSG + # Bit-2: XCHG + fet_reg_addr: + default: 0x99 + fet_reg_mask: + default: 0x0C + fet_disconnect_val: + default: 0x0C + fet_cfet_mask: + default: 0x04 + fet_cfet_off_val: + default: 0x04 + + # Battery info + voltage_max: + default: 8900 + voltage_normal: + default: 7970 + voltage_min: + default: 6000 + precharge_current: + default: 256 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 45 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 60 \ No newline at end of file diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index edcb239703..93118e50de 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -13,6 +13,7 @@ properties: enum: - "aec,5477109" - "as3gwrc3ka,c235-41" + - "as3gxxe3ka,c140254" - "byd,l22b3pg0" - "celxpert,l22c3pg0" - "cosmx,l22x3pg0" diff --git a/zephyr/projects/corsola/battery_tentacruel.dts b/zephyr/projects/corsola/battery_tentacruel.dts index 05dcc4de05..d106fca6b3 100644 --- a/zephyr/projects/corsola/battery_tentacruel.dts +++ b/zephyr/projects/corsola/battery_tentacruel.dts @@ -5,8 +5,8 @@ / { batteries { - default_battery: c235 { - compatible = "as3gwrc3ka,c235-41", "battery-smart"; + default_battery: as3gxxe3ka_c140254 { + compatible = "as3gxxe3ka,c140254", "battery-smart"; }; }; }; -- cgit v1.2.1 From b4e7f345aaae910e3ac859ea022237ba385f7002 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:19 -0600 Subject: include/keyboard_8042_sharedlib.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibbf93e5314f62f905a413a004a7b575d8ec92309 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730295 Reviewed-by: Jeremy Bettis --- include/keyboard_8042_sharedlib.h | 140 +++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 70 deletions(-) diff --git a/include/keyboard_8042_sharedlib.h b/include/keyboard_8042_sharedlib.h index e4a2e9a77f..91249888b8 100644 --- a/include/keyboard_8042_sharedlib.h +++ b/include/keyboard_8042_sharedlib.h @@ -47,42 +47,42 @@ extern const uint8_t scancode_translate_table[]; extern uint8_t scancode_translate_set2_to_1(uint8_t code); #ifdef CONFIG_KEYBOARD_DEBUG -#define KEYCAP_LONG_LABEL_BIT (0x80) -#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT) +#define KEYCAP_LONG_LABEL_BIT (0x80) +#define KEYCAP_LONG_LABEL_INDEX_BITMASK (~KEYCAP_LONG_LABEL_BIT) enum keycap_long_label_idx { - KLLI_UNKNO = 0x80, /* UNKNOWN */ - KLLI_F1 = 0x81, /* F1 or PREVIOUS */ - KLLI_F2 = 0x82, /* F2 or NEXT */ - KLLI_F3 = 0x83, /* F3 or REFRESH */ - KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */ - KLLI_F5 = 0x85, /* F5 or OVERVIEW */ - KLLI_F6 = 0x86, /* F6 or DIM */ - KLLI_F7 = 0x87, /* F7 or BRIGHT */ - KLLI_F8 = 0x88, /* F8 or MUTE */ - KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */ - KLLI_F10 = 0x8A, /* F10 or VOLUME UP */ - KLLI_F11 = 0x8B, /* F11 or POWER */ - KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */ - KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */ - KLLI_F14 = 0x8E, /* F14 */ - KLLI_F15 = 0x8F, /* F15 */ - KLLI_L_ALT = 0x90, /* LEFT ALT */ - KLLI_R_ALT = 0x91, /* RIGHT ALT */ - KLLI_L_CTR = 0x92, /* LEFT CONTROL */ - KLLI_R_CTR = 0x93, /* RIGHT CONTROL */ - KLLI_L_SHT = 0x94, /* LEFT SHIFT */ - KLLI_R_SHT = 0x95, /* RIGHT SHIFT */ - KLLI_ENTER = 0x96, /* ENTER */ - KLLI_SPACE = 0x97, /* SPACE */ - KLLI_B_SPC = 0x98, /* BACk SPACE*/ - KLLI_TAB = 0x99, /* TAB */ - KLLI_SEARC = 0x9A, /* SEARCH */ - KLLI_LEFT = 0x9B, /* LEFT ARROW */ - KLLI_RIGHT = 0x9C, /* RIGHT ARROW */ - KLLI_DOWN = 0x9D, /* DOWN ARROW */ - KLLI_UP = 0x9E, /* UP ARROW */ - KLLI_ESC = 0x9F, /* ESCAPE */ + KLLI_UNKNO = 0x80, /* UNKNOWN */ + KLLI_F1 = 0x81, /* F1 or PREVIOUS */ + KLLI_F2 = 0x82, /* F2 or NEXT */ + KLLI_F3 = 0x83, /* F3 or REFRESH */ + KLLI_F4 = 0x84, /* F4 or FULL_SCREEN */ + KLLI_F5 = 0x85, /* F5 or OVERVIEW */ + KLLI_F6 = 0x86, /* F6 or DIM */ + KLLI_F7 = 0x87, /* F7 or BRIGHT */ + KLLI_F8 = 0x88, /* F8 or MUTE */ + KLLI_F9 = 0x89, /* F9 or VOLUME DOWN */ + KLLI_F10 = 0x8A, /* F10 or VOLUME UP */ + KLLI_F11 = 0x8B, /* F11 or POWER */ + KLLI_F12 = 0x8C, /* F12 or DEV TOOLS */ + KLLI_F13 = 0x8D, /* F13 or GOOGLE ASSISTANT */ + KLLI_F14 = 0x8E, /* F14 */ + KLLI_F15 = 0x8F, /* F15 */ + KLLI_L_ALT = 0x90, /* LEFT ALT */ + KLLI_R_ALT = 0x91, /* RIGHT ALT */ + KLLI_L_CTR = 0x92, /* LEFT CONTROL */ + KLLI_R_CTR = 0x93, /* RIGHT CONTROL */ + KLLI_L_SHT = 0x94, /* LEFT SHIFT */ + KLLI_R_SHT = 0x95, /* RIGHT SHIFT */ + KLLI_ENTER = 0x96, /* ENTER */ + KLLI_SPACE = 0x97, /* SPACE */ + KLLI_B_SPC = 0x98, /* BACk SPACE*/ + KLLI_TAB = 0x99, /* TAB */ + KLLI_SEARC = 0x9A, /* SEARCH */ + KLLI_LEFT = 0x9B, /* LEFT ARROW */ + KLLI_RIGHT = 0x9C, /* RIGHT ARROW */ + KLLI_DOWN = 0x9D, /* DOWN ARROW */ + KLLI_UP = 0x9E, /* UP ARROW */ + KLLI_ESC = 0x9F, /* ESCAPE */ KLLI_MAX }; @@ -127,41 +127,41 @@ enum scancode_values { SCANCODE_B = 0x0032, SCANCODE_T = 0x002c, - SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */ - SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */ - SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */ - SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */ - SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */ - SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */ - SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */ - SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */ - SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */ - SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */ - SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */ - SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */ - SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */ - SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */ - SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */ - - SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */ - SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */ - SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */ - SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */ - SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */ - SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */ - SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */ - SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */ - SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */ - SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */ - SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */ - SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */ - SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */ - SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */ - SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */ - SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */ - SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */ + SCANCODE_F1 = 0x0005, /* Translates to 3b in codeset 1 */ + SCANCODE_F2 = 0x0006, /* Translates to 3c in codeset 1 */ + SCANCODE_F3 = 0x0004, /* Translates to 3d in codeset 1 */ + SCANCODE_F4 = 0x000c, /* Translates to 3e in codeset 1 */ + SCANCODE_F5 = 0x0003, /* Translates to 3f in codeset 1 */ + SCANCODE_F6 = 0x000b, /* Translates to 40 in codeset 1 */ + SCANCODE_F7 = 0x0083, /* Translates to 41 in codeset 1 */ + SCANCODE_F8 = 0x000a, /* Translates to 42 in codeset 1 */ + SCANCODE_F9 = 0x0001, /* Translates to 43 in codeset 1 */ + SCANCODE_F10 = 0x0009, /* Translates to 44 in codeset 1 */ + SCANCODE_F11 = 0x0078, /* Translates to 57 in codeset 1 */ + SCANCODE_F12 = 0x0007, /* Translates to 58 in codeset 1 */ + SCANCODE_F13 = 0x000f, /* Translates to 59 in codeset 1 */ + SCANCODE_F14 = 0x0017, /* Translates to 5a in codeset 1 */ + SCANCODE_F15 = 0x001f, /* Translates to 5b in codeset 1 */ + + SCANCODE_BACK = 0xe038, /* e06a in codeset 1 */ + SCANCODE_REFRESH = 0xe020, /* e067 in codeset 1 */ + SCANCODE_FORWARD = 0xe030, /* e069 in codeset 1 */ + SCANCODE_FULLSCREEN = 0xe01d, /* e011 in codeset 1 */ + SCANCODE_OVERVIEW = 0xe024, /* e012 in codeset 1 */ + SCANCODE_SNAPSHOT = 0xe02d, /* e013 in codeset 1 */ + SCANCODE_BRIGHTNESS_DOWN = 0xe02c, /* e014 in codeset 1 */ + SCANCODE_BRIGHTNESS_UP = 0xe035, /* e015 in codeset 1 */ + SCANCODE_PRIVACY_SCRN_TOGGLE = 0xe03c, /* e016 in codeset 1 */ + SCANCODE_VOLUME_MUTE = 0xe023, /* e020 in codeset 1 */ + SCANCODE_VOLUME_DOWN = 0xe021, /* e02e in codeset 1 */ + SCANCODE_VOLUME_UP = 0xe032, /* e030 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_DOWN = 0xe043, /* e017 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_UP = 0xe044, /* e018 in codeset 1 */ + SCANCODE_KBD_BKLIGHT_TOGGLE = 0xe01c, /* e01e in codeset 1 */ + SCANCODE_NEXT_TRACK = 0xe04d, /* e019 in codeset 1 */ + SCANCODE_PREV_TRACK = 0xe015, /* e010 in codeset 1 */ + SCANCODE_PLAY_PAUSE = 0xe054, /* e01a in codeset 1 */ + SCANCODE_MICMUTE = 0xe05b, /* e01b in codeset 1 */ SCANCODE_UP = 0xe075, SCANCODE_DOWN = 0xe072, @@ -173,7 +173,7 @@ enum scancode_values { SCANCODE_LEFT_ALT = 0x0011, SCANCODE_RIGHT_ALT = 0xe011, - SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */ + SCANCODE_LEFT_WIN = 0xe01f, /* Also known as GUI or Super key. */ SCANCODE_RIGHT_WIN = 0xe027, SCANCODE_MENU = 0xe02f, -- cgit v1.2.1 From 480f9d89de92489afb84c047f638ba57ce39382f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:26 -0600 Subject: chip/stm32/dfu_bootmanager_main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc18532655c27cdea7614c8fe92d12337edebd94 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729490 Reviewed-by: Jeremy Bettis --- chip/stm32/dfu_bootmanager_main.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/chip/stm32/dfu_bootmanager_main.c b/chip/stm32/dfu_bootmanager_main.c index 462dd08b60..4524d5effc 100644 --- a/chip/stm32/dfu_bootmanager_main.c +++ b/chip/stm32/dfu_bootmanager_main.c @@ -93,7 +93,7 @@ static void dfu_bootmanager_init(void) { /* enable clock on Power module */ #ifndef CHIP_FAMILY_STM32H7 -#ifdef CHIP_FAMILY_STM32L4 +#ifdef CHIP_FAMILY_STM32L4 STM32_RCC_APB1ENR1 |= STM32_RCC_PWREN; #else STM32_RCC_APB1ENR |= STM32_RCC_PWREN; @@ -122,8 +122,8 @@ static void jump_to_rw(void) { void (*addr)(void); - addr = (void (*)(void)) (*((uint32_t *) (CONFIG_PROGRAM_MEMORY_BASE + - CONFIG_RW_MEM_OFF + 4))); + addr = (void (*)(void))(*((uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + + CONFIG_RW_MEM_OFF + 4))); addr(); } @@ -132,7 +132,7 @@ static void jump_to_dfu(void) { void (*addr)(void); - addr = (void (*)(void)) (*((uint32_t *) (STM32_DFU_BASE + 4))); + addr = (void (*)(void))(*((uint32_t *)(STM32_DFU_BASE + 4))); /* Clear the scratchpad. */ dfu_bootmanager_backup_write(DFU_BOOTMANAGER_VALUE_CLEAR); @@ -170,10 +170,18 @@ void exception_panic(void) * need to worry about concurrent access. */ -void task_clear_pending_irq(int irq) {} -void interrupt_disable(void) {} -void mutex_lock(mutex_t *mtx) {} -void mutex_unlock(mutex_t *mtx) {} +void task_clear_pending_irq(int irq) +{ +} +void interrupt_disable(void) +{ +} +void mutex_lock(mutex_t *mtx) +{ +} +void mutex_unlock(mutex_t *mtx) +{ +} bool in_interrupt_context(void) { -- cgit v1.2.1 From 61760ade1186d019b9d04a52444e4d03db5dbde2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:36 -0600 Subject: board/reef_it8320/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida3b00ea987e2c829e39bce6f5bfd4d385aa3adf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728887 Reviewed-by: Jeremy Bettis --- board/reef_it8320/battery.c | 55 ++++++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/board/reef_it8320/battery.c b/board/reef_it8320/battery.c index 1b16a672b2..6d33867861 100644 --- a/board/reef_it8320/battery.c +++ b/board/reef_it8320/battery.c @@ -20,7 +20,7 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) enum battery_type { BATTERY_SONY_CORP, @@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 46, .charging_min_c = 0, @@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 45, .charging_min_c = 0, @@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void) int batt_status; return battery_status(&batt_status) ? 0 : - batt_status & STATUS_INITIALIZED; + batt_status & STATUS_INITIALIZED; } static int batt_sony_corp_init(void) @@ -411,8 +411,9 @@ static int batt_sony_corp_init(void) * : 0b - Allowed to Discharge * : 1b - Not Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); } static int batt_panasonic_init(void) @@ -425,8 +426,9 @@ static int batt_panasonic_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); } static int batt_c22n1626_init(void) @@ -439,8 +441,9 @@ static int batt_c22n1626_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_PACK_STATUS, &batt_status) ? 0 : - !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_PACK_STATUS, &batt_status) ? + 0 : + !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); } static const struct ship_mode_info ship_mode_info_smp_cos4870 = { @@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT); static inline const struct board_batt_params *board_get_batt_params(void) { return &info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type]; + DEFAULT_BATTERY_TYPE : + board_battery_type]; } enum battery_present battery_hw_present(void) @@ -540,8 +544,9 @@ static int board_get_battery_type(void) /* Initialize fast charging parameters */ chg_params = board_get_batt_params()->fast_chg_params; - prev_chg_profile_info = &chg_params->chg_profile_info[ - chg_params->default_temp_range_profile]; + prev_chg_profile_info = + &chg_params->chg_profile_info + [chg_params->default_temp_range_profile]; return board_battery_type; } @@ -571,11 +576,11 @@ int board_cut_off_battery(void) { int rv; const struct ship_mode_info *ship_mode_inf = - board_get_batt_params()->ship_mode_inf; + board_get_batt_params()->ship_mode_inf; /* Ship mode command must be sent twice to take effect */ rv = sb_write(ship_mode_inf->ship_mode_reg, - ship_mode_inf->ship_mode_data); + ship_mode_inf->ship_mode_data); if (rv != EC_SUCCESS) return rv; @@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) /* Do not discharge on AC if the battery is still waking up */ if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - !(curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.status & STATUS_FULLY_CHARGED)) return 0; /* @@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) * and suspend USB charging and DC/DC converter. */ if (!battery_is_cut_off() && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; /* @@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr) return 0; } - return charger_profile_override_common(curr, - board_get_batt_params()->fast_chg_params, - &prev_chg_profile_info, - board_get_batt_params()->batt_info->voltage_max); + return charger_profile_override_common( + curr, board_get_batt_params()->fast_chg_params, + &prev_chg_profile_info, + board_get_batt_params()->batt_info->voltage_max); } /* @@ -671,7 +676,7 @@ enum battery_present battery_is_present(void) * Battery status will be inactive until it is initialized. */ if (batt_pres == BP_YES && batt_pres_prev != batt_pres && - !battery_is_cut_off()) { + !battery_is_cut_off()) { /* Re-init board battery if battery presence status changes */ if (board_get_battery_type() == BATTERY_TYPE_COUNT) { if (bd9995x_get_battery_voltage() >= -- cgit v1.2.1 From d9f2bb1302e6725064b03c51c844eaf69cdec6bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:31 -0600 Subject: zephyr/projects/corsola/src/kingler/led_steelix.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee929572c98ca2d0f4e28d6c23e0d5f24d6b869a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730738 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/kingler/led_steelix.c | 56 +++++++++++++---------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c index f15f31c8ee..8a97253557 100644 --- a/zephyr/projects/corsola/src/kingler/led_steelix.c +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -29,29 +29,36 @@ static const struct board_led_pwm_dt_channel board_led_power_white = __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -73,8 +80,8 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); - LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", - ch->dev->name, percent, pulse_ns); + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, + percent, pulse_ns); rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, ch->flags); @@ -90,8 +97,7 @@ static bool device_is_clamshell(void) ret = cros_cbi_get_fw_config(FROM_FACTOR, &val); if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", - FROM_FACTOR); + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FROM_FACTOR); return false; } -- cgit v1.2.1 From a3ddef2ef2a77b448176587e11ab16d4cfaeddcc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:15 -0600 Subject: baseboard/brya/battery_presence.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic77b6c61fcecce042f4e92a8b58a338dc5bce5ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727862 Reviewed-by: Jeremy Bettis --- baseboard/brya/battery_presence.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/baseboard/brya/battery_presence.c b/baseboard/brya/battery_presence.c index 94c9926820..34fffda436 100644 --- a/baseboard/brya/battery_presence.c +++ b/baseboard/brya/battery_presence.c @@ -18,8 +18,9 @@ __overridable bool board_battery_is_initialized(void) { int batt_status; - return battery_status(&batt_status) != EC_SUCCESS ? false : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) != EC_SUCCESS ? + false : + !!(batt_status & STATUS_INITIALIZED); } /* -- cgit v1.2.1 From 1f431f69b0865092846987b16da18c5226319d30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:39 -0600 Subject: board/ghost/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e873534f155b43384e5ece8e1cf5f4bfacf398f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728402 Reviewed-by: Jeremy Bettis --- board/ghost/board.h | 114 ++++++++++++++++++++++++---------------------------- 1 file changed, 53 insertions(+), 61 deletions(-) diff --git a/board/ghost/board.h b/board/ghost/board.h index 79be17ac2f..54391bcfec 100644 --- a/board/ghost/board.h +++ b/board/ghost/board.h @@ -44,7 +44,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_FRS_PPC @@ -53,17 +53,17 @@ #define CONFIG_USBC_PPC_SYV682X /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -71,58 +71,58 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_IMVP9_VRRDY_OD GPIO_IMVP91_VRRDY_OD -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_IMVP9_VRRDY_OD GPIO_IMVP91_VRRDY_OD +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_RT NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_RT NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_RT NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_RT NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT5_0 -#define I2C_PORT_MISC NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT5_0 +#define I2C_PORT_MISC NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM I2C_PORT_MISC -#define I2C_PORT_MP2964 I2C_PORT_MISC +#define I2C_PORT_EEPROM I2C_PORT_MISC +#define I2C_PORT_MP2964 I2C_PORT_MISC -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x57 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -141,12 +141,12 @@ /* Charger defines */ #define CONFIG_CHARGER_ISL9241 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -166,24 +166,16 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; -enum battery_type { - BATTERY_POWER_TECH, - BATTERY_SWD_ATL, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_POWER_TECH, BATTERY_SWD_ATL, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_LED1 = 0, /* PWM0 */ - PWM_CH_LED2, /* PWM1 */ - PWM_CH_FAN2, /* PWM2 */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN1, /* PWM5 */ + PWM_CH_LED1 = 0, /* PWM0 */ + PWM_CH_LED2, /* PWM1 */ + PWM_CH_FAN2, /* PWM2 */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN1, /* PWM5 */ PWM_CH_COUNT }; -- cgit v1.2.1 From fb73ec2520953eca5ecb6ebcb3b8afa0065625b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:57 -0600 Subject: board/bugzzy/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6cc902b1e5145f1c630cee6d3d97f4e6cdd1652e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728127 Reviewed-by: Jeremy Bettis --- board/bugzzy/led.c | 70 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/board/bugzzy/led.c b/board/bugzzy/led.c index 17da244534..bb4c7c2cd5 100644 --- a/board/bugzzy/led.c +++ b/board/bugzzy/led.c @@ -12,8 +12,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 1; @@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100; /* bugzzy : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -57,7 +60,7 @@ __override void led_set_color_power(enum ec_led_colors color) /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -70,8 +73,7 @@ __override void led_set_color_power(enum ec_led_colors color) return; } - if (color == EC_LED_COLOR_BLUE) - { + if (color == EC_LED_COLOR_BLUE) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL); @@ -87,7 +89,7 @@ __override void led_set_color_battery(enum ec_led_colors color) /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -140,12 +142,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, - !brightness[EC_LED_COLOR_GREEN]); + !brightness[EC_LED_COLOR_GREEN]); gpio_set_level(GPIO_BAT_LED_RED_L, - !brightness[EC_LED_COLOR_RED]); + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, - !brightness[EC_LED_COLOR_BLUE]); + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 79c73ba60ab3bdf201572f2437c392099823c2ca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:54 -0600 Subject: board/bugzzy/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic54ae0ad402cb30bb5d15c3e7bcc8faa255d3090 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728106 Reviewed-by: Jeremy Bettis --- board/bugzzy/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/bugzzy/cbi_ssfc.h b/board/bugzzy/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/bugzzy/cbi_ssfc.h +++ b/board/bugzzy/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From d4fd32176b05c90162667ffe6ab740de8fc45cf1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:42 -0600 Subject: common/mkbp_input_devices.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2049c8a35f7097e1573c5d45ffdcd1d27c01f466 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729673 Reviewed-by: Jeremy Bettis --- common/mkbp_input_devices.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/common/mkbp_input_devices.c b/common/mkbp_input_devices.c index 7cba670eb1..1a51ac107d 100644 --- a/common/mkbp_input_devices.c +++ b/common/mkbp_input_devices.c @@ -20,7 +20,7 @@ #include "tablet_mode.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) /* Buttons and switch state. */ static uint32_t mkbp_button_state; @@ -69,7 +69,7 @@ void mkbp_button_update(enum keyboard_button_type button, int is_pressed) CPRINTS("mkbp buttons: %x", mkbp_button_state); mkbp_fifo_add(EC_MKBP_EVENT_BUTTON, - (const uint8_t *)&mkbp_button_state); + (const uint8_t *)&mkbp_button_state); }; void mkbp_update_switches(uint32_t sw, int state) @@ -86,10 +86,9 @@ void mkbp_update_switches(uint32_t sw, int state) */ if (mkbp_init_done) mkbp_fifo_add(EC_MKBP_EVENT_SWITCH, - (const uint8_t *)&mkbp_switch_state); + (const uint8_t *)&mkbp_switch_state); } - /*****************************************************************************/ /* Hooks */ @@ -99,8 +98,7 @@ void mkbp_update_switches(uint32_t sw, int state) */ static void keyboard_power_button(void) { - mkbp_button_update(KEYBOARD_BUTTON_POWER, - power_button_is_pressed()); + mkbp_button_update(KEYBOARD_BUTTON_POWER, power_button_is_pressed()); } DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, keyboard_power_button, HOOK_PRIO_DEFAULT); @@ -142,7 +140,7 @@ static void mkbp_report_switch_on_init(void) /* All switches initialized, report switch state to AP */ mkbp_init_done = true; mkbp_fifo_add(EC_MKBP_EVENT_SWITCH, - (const uint8_t *)&mkbp_switch_state); + (const uint8_t *)&mkbp_switch_state); } DECLARE_HOOK(HOOK_INIT, mkbp_report_switch_on_init, HOOK_PRIO_LAST); @@ -188,7 +186,7 @@ uint8_t keyboard_cols = KEYBOARD_COLS_MAX; static void simulate_key(int row, int col, int pressed) { if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row)) - return; /* No change */ + return; /* No change */ simulated_key[col] &= ~BIT(row); if (pressed) @@ -239,7 +237,6 @@ static int command_mkbp_keyboard_press(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(kbpress, command_mkbp_keyboard_press, - "[col row [0 | 1]]", - "Simulate keypress"); + "[col row [0 | 1]]", "Simulate keypress"); #endif /* !defined(HAS_TASK_KEYSCAN) */ -- cgit v1.2.1 From 5172350675512a98b4df3ec876fc67e2b140866a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:35 -0600 Subject: board/pazquel/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3834a6af0ac016dc933569e4831199670bc807ff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728814 Reviewed-by: Jeremy Bettis --- board/pazquel/board.h | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/board/pazquel/board.h b/board/pazquel/board.h index dc80fc9829..f7f2fd4619 100644 --- a/board/pazquel/board.h +++ b/board/pazquel/board.h @@ -11,7 +11,7 @@ #include "baseboard.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -77,12 +77,7 @@ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -92,11 +87,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; enum battery_type { BATTERY_GANFENG, -- cgit v1.2.1 From cf48090918ceb1c4b71caace3853c4ac7a3992de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:48 -0600 Subject: board/bugzzy/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32d0b8f629cbeba8aa40f9cc285ece096ef76937 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728109 Reviewed-by: Jeremy Bettis --- board/bugzzy/board.c | 138 ++++++++++++++++++++++----------------------------- 1 file changed, 58 insertions(+), 80 deletions(-) diff --git a/board/bugzzy/board.c b/board/bugzzy/board.c index 25fc04a20a..ea9d2251cb 100644 --- a/board/bugzzy/board.c +++ b/board/bugzzy/board.c @@ -44,8 +44,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -85,7 +85,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -120,7 +119,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -181,22 +179,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Skin1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "Skin2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Skin1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "Skin2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -212,16 +210,17 @@ void board_init(void) if (get_cbi_fw_config_db() == DB_1A_HDMI) { /* Disable i2c on HDMI pins */ - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0); - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, + 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, + 0); /* Set HDMI and sub-rail enables to output */ gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, chipset_in_state(CHIPSET_STATE_ON) ? - GPIO_ODR_LOW : GPIO_ODR_HIGH); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + GPIO_ODR_LOW : + GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -230,8 +229,7 @@ void board_init(void) gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL); } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT); /* Enable C1 interrupt and check if it needs processing */ gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL); @@ -300,10 +298,9 @@ __override void board_power_5v_enable(int enable) gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } else { if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", + enable ? "en" : "dis"); } - } __override uint8_t board_get_usb_pd_port_count(void) @@ -328,13 +325,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -398,8 +393,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -426,23 +421,17 @@ static struct mutex g_base_mutex; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref_lsm = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref_lsm = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t ldm6dsm_base_accel = { .name = "Base Accel", @@ -481,8 +470,7 @@ struct motion_sensor_t ldm6dsm_base_gyro = { .location = MOTIONSENSE_LOC_BASE, .drv = &lsm6dsm_drv, .mutex = &g_base_mutex, - .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, - MOTIONSENSE_TYPE_GYRO), + .drv_data = LSM6DSM_ST_DATA(lsm6dsm_data, MOTIONSENSE_TYPE_GYRO), .port = I2C_PORT_ACCEL, .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, .default_range = 1000 | ROUND_UP_FLAG, /* dps */ @@ -601,9 +589,8 @@ void motion_interrupt(enum gpio_signal signal) lsm6dsm_interrupt(signal); } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -690,25 +677,19 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB Mux C0 : board_init of PS8743 */ static int ps8743_tune_mux_c0(const struct usb_mux *me) { - ps8743_tune_usb_eq(me, - PS8743_USB_EQ_TX_3_6_DB, - PS8743_USB_EQ_RX_16_0_DB); + ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, + PS8743_USB_EQ_RX_16_0_DB); return EC_SUCCESS; } /* USB Mux C1 : board_init of PS8743 */ static int ps8743_tune_mux_c1(const struct usb_mux *me) { - ps8743_tune_usb_eq(me, - PS8743_USB_EQ_TX_3_6_DB, - PS8743_USB_EQ_RX_16_0_DB); + ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, + PS8743_USB_EQ_RX_16_0_DB); - ps8743_write(me, - PS8743_REG_USB_SWING, - PS8743_LFPS_SWG_TD); - ps8743_write(me, - PS8743_REG_DP_SETTING, - PS8743_DP_SWG_ADJ_P15P); + ps8743_write(me, PS8743_REG_USB_SWING, PS8743_LFPS_SWG_TD); + ps8743_write(me, PS8743_REG_DP_SETTING, PS8743_DP_SWG_ADJ_P15P); return EC_SUCCESS; } @@ -735,7 +716,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { + !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) @@ -765,8 +746,8 @@ static const struct ec_response_keybd_config keybd1 = { /* No function keys, no numeric keypad, has screenlock key */ .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { /* * Future boards should use fw_config if needed. @@ -830,11 +811,11 @@ static void panel_power_change_deferred(void) gpio_set_level(GPIO_EN_LCD_ENN, signal); } else if (signal != 0) { i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, - ISL98607_REG_VBST_OUT, ISL98607_VBST_OUT_5P65); + ISL98607_REG_VBST_OUT, ISL98607_VBST_OUT_5P65); i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, - ISL98607_REG_VN_OUT, ISL98607_VN_OUT_5P5); + ISL98607_REG_VN_OUT, ISL98607_VN_OUT_5P5); i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, - ISL98607_REG_VP_OUT, ISL98607_VP_OUT_5P5); + ISL98607_REG_VP_OUT, ISL98607_VP_OUT_5P5); } gpio_set_level(GPIO_TSP_TA, signal & extpower_is_present()); } @@ -878,9 +859,8 @@ static void lcd_reset_change_deferred(void) if (signal == 0) return; - i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, - ISL98607_REG_ENABLE, ISL97607_VP_VN_VBST_DIS); - + i2c_write8(I2C_PORT_LCD, I2C_ADDR_ISL98607_FLAGS, ISL98607_REG_ENABLE, + ISL97607_VP_VN_VBST_DIS); } DECLARE_DEFERRED(lcd_reset_change_deferred); void lcd_reset_change_interrupt(enum gpio_signal signal) @@ -927,8 +907,6 @@ void backlit_gpio_tick(void) if (board_id >= 4 && signal == 1) i2c_write16(I2C_PORT_LCD, I2C_ADDR_MP3372_FLAGS, - MP3372_REG_ISET_CHEN, - MP3372_ISET_15P3_CHEN_ALL); - + MP3372_REG_ISET_CHEN, MP3372_ISET_15P3_CHEN_ALL); } DECLARE_HOOK(HOOK_TICK, backlit_gpio_tick, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 93684a28bab194d51c8a11dd564060bc8a4b29b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:31 -0600 Subject: zephyr/shim/src/bc12_rt9490.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I47ea47f8444876f5f9e8ab0edf72512535500e8c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730863 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/bc12_rt9490.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/src/bc12_rt9490.c b/zephyr/shim/src/bc12_rt9490.c index abecfcfa3a..14d64edcb8 100644 --- a/zephyr/shim/src/bc12_rt9490.c +++ b/zephyr/shim/src/bc12_rt9490.c @@ -19,15 +19,14 @@ static void rt9490_bc12_enable_irqs(void) } DECLARE_HOOK(HOOK_INIT, rt9490_bc12_enable_irqs, HOOK_PRIO_DEFAULT); -#define GPIO_SIGNAL_FROM_INST(inst) \ +#define GPIO_SIGNAL_FROM_INST(inst) \ GPIO_SIGNAL(DT_PHANDLE(DT_INST_PHANDLE(inst, irq), irq_pin)) -#define RT9490_DISPATCH_INTERRUPT(inst) \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \ - (case GPIO_SIGNAL_FROM_INST(inst): \ - rt9490_interrupt(USBC_PORT_FROM_INST(inst)); \ - break; \ - )) +#define RT9490_DISPATCH_INTERRUPT(inst) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \ + (case GPIO_SIGNAL_FROM_INST(inst) \ + : rt9490_interrupt(USBC_PORT_FROM_INST(inst)); \ + break;)) void rt9490_bc12_dt_interrupt(enum gpio_signal signal) { -- cgit v1.2.1 From efe48b8794a1af7f470bccdd06d1cbc449da6e4f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:16 -0600 Subject: board/jacuzzi/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6924b546a951ac59d95d7ea8aeda6c330ad256f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728516 Reviewed-by: Jeremy Bettis --- board/jacuzzi/board.h | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/board/jacuzzi/board.h b/board/jacuzzi/board.h index da66312411..616c257897 100644 --- a/board/jacuzzi/board.h +++ b/board/jacuzzi/board.h @@ -58,7 +58,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -71,7 +71,6 @@ #define CONFIG_ALS #define CONFIG_CMD_ACCEL_INFO - #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL @@ -84,24 +83,24 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #ifdef BOARD_JACUZZI -#define I2C_PORT_BATTERY 1 +#define I2C_PORT_BATTERY 1 #else /* Juniper */ -#define I2C_PORT_BATTERY 2 +#define I2C_PORT_BATTERY 2 #endif /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From b9b5197cafbff224f23c4cc9e7414d3695ffce72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:04 -0600 Subject: board/volmar/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf2eb86c2eb13cbe16e84387b7a4e47faf21783a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729078 Reviewed-by: Jeremy Bettis --- board/volmar/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/volmar/keyboard.c b/board/volmar/keyboard.c index 598e187d00..c6d46c37d7 100644 --- a/board/volmar/keyboard.c +++ b/board/volmar/keyboard.c @@ -40,8 +40,8 @@ static const struct ec_response_keybd_config volmar_kb = { }, .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &volmar_kb; } -- cgit v1.2.1 From d0638550ff342f97b37644e3468f04757c3d1021 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:11 -0600 Subject: zephyr/shim/include/usbc/anx7483_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic145af1d12323e2c891aced92ddff90de526176d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730831 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/anx7483_usb_mux.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/usbc/anx7483_usb_mux.h b/zephyr/shim/include/usbc/anx7483_usb_mux.h index 606928b016..35c859ff2e 100644 --- a/zephyr/shim/include/usbc/anx7483_usb_mux.h +++ b/zephyr/shim/include/usbc/anx7483_usb_mux.h @@ -8,15 +8,15 @@ #include "driver/retimer/anx7483_public.h" -#define ANX7483_USB_MUX_COMPAT analogix_anx7483 +#define ANX7483_USB_MUX_COMPAT analogix_anx7483 -#define USB_MUX_CONFIG_ANX7483(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &anx7483_usb_retimer_driver, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = \ - DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_ANX7483(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &anx7483_usb_retimer_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ } #endif /* __ZEPHYR_SHIM_ANX7483_USB_MUX_H */ -- cgit v1.2.1 From 38109128f3c9327a9f0e4ddcf4f1b5523a0967d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:39 -0600 Subject: common/switch.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a9738b6283499e4c52d11f2cbe9b38f5ea9ea91 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729752 Reviewed-by: Jeremy Bettis --- common/switch.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/common/switch.c b/common/switch.c index 40a5ab217f..8581614d16 100644 --- a/common/switch.c +++ b/common/switch.c @@ -19,7 +19,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SWITCH, outstr) -#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args) static uint8_t *memmap_switches; @@ -105,12 +105,8 @@ static int command_mmapinfo(int argc, char **argv) uint8_t val = *memmap_switches; int i; const char *explanation[] = { - "lid_open", - "powerbtn", - "wp_off", - "kbd_rec", - "gpio_rec", - "fake_dev", + "lid_open", "powerbtn", "wp_off", + "kbd_rec", "gpio_rec", "fake_dev", }; ccprintf("memmap switches = 0x%x\n", val); for (i = 0; i < ARRAY_SIZE(explanation); i++) @@ -119,7 +115,6 @@ static int command_mmapinfo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo, - NULL, +DECLARE_CONSOLE_COMMAND(mmapinfo, command_mmapinfo, NULL, "Print memmap switch state"); #endif -- cgit v1.2.1 From 1d2c37c0c872c5a286ccddb5ca5ba3b9a4b928a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:54 -0600 Subject: board/stryke/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1674549174a462103ca4ab00822926231865abfa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728974 Reviewed-by: Jeremy Bettis --- board/stryke/led.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/board/stryke/led.c b/board/stryke/led.c index 4e210f34e2..3ef9a3cdfd 100644 --- a/board/stryke/led.c +++ b/board/stryke/led.c @@ -19,22 +19,26 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From e79482d092c712347f0257433d1d5a6f3750dc2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:21 -0600 Subject: util/export_taskinfo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia69e2149f028191a1dd81058d57eb4c022cb99b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730621 Reviewed-by: Jeremy Bettis --- util/export_taskinfo.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/util/export_taskinfo.c b/util/export_taskinfo.c index 4c09bafb90..0e2dac7837 100644 --- a/util/export_taskinfo.c +++ b/util/export_taskinfo.c @@ -25,14 +25,13 @@ struct taskinfo { uint32_t stack_size; }; -#define TASK(n, r, d, s, ...) { \ - .name = #n, \ - .routine = #r, \ - .stack_size = s, \ -}, -static const struct taskinfo taskinfos[] = { - CONFIG_TASK_LIST -}; +#define TASK(n, r, d, s, ...) \ + { \ + .name = #n, \ + .routine = #r, \ + .stack_size = s, \ + }, +static const struct taskinfo taskinfos[] = { CONFIG_TASK_LIST }; #undef TASK uint32_t GET_TASKINFOS_FUNC(const struct taskinfo **infos) -- cgit v1.2.1 From d93389af500648ec79b30d2fd911932cf64f2b66 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:06 -0600 Subject: board/elm/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6746271e94d1a8d0650cf164413702eb58ad182e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728291 Reviewed-by: Jeremy Bettis --- board/elm/board.h | 56 +++++++++++++++++++++++++++---------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/board/elm/board.h b/board/elm/board.h index 8bb8c2bf15..f7ff1e0aa2 100644 --- a/board/elm/board.h +++ b/board/elm/board.h @@ -27,7 +27,7 @@ #define CONFIG_LID_ANGLE_UPDATE #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG /* AC adaptor, charger, battery */ #define CONFIG_BATTERY_CUT_OFF @@ -75,10 +75,10 @@ #define CONFIG_SPI_CONTROLLER #define CONFIG_STM_HWTIMER32 #define CONFIG_VBOOT_HASH -#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_WATCHDOG_HELP #define CONFIG_SWITCH #define CONFIG_BOARD_VERSION_GPIO -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 #define CONFIG_TEMP_SENSOR #define CONFIG_DPTF @@ -102,7 +102,7 @@ #define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_DETECT_TCPC -#undef CONFIG_TCPC_I2C_BASE_ADDR_FLAGS +#undef CONFIG_TCPC_I2C_BASE_ADDR_FLAGS #define CONFIG_TCPC_I2C_BASE_ADDR_FLAGS 0x2C #define CONFIG_USB_PD_ANX7688 @@ -144,11 +144,11 @@ #undef CONFIG_EC_WRITABLE_STORAGE_OFF #undef CONFIG_EC_WRITABLE_STORAGE_SIZE #undef CONFIG_WP_STORAGE_SIZE -#define CONFIG_RW_MEM_OFF (128 * 1024) -#define CONFIG_RW_SIZE (128 * 1024) -#define CONFIG_EC_WRITABLE_STORAGE_OFF (128 * 1024) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (128 * 1024) -#define CONFIG_WP_STORAGE_SIZE (128 * 1024) +#define CONFIG_RW_MEM_OFF (128 * 1024) +#define CONFIG_RW_SIZE (128 * 1024) +#define CONFIG_EC_WRITABLE_STORAGE_OFF (128 * 1024) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE (128 * 1024) +#define CONFIG_WP_STORAGE_SIZE (128 * 1024) /* Drivers */ #ifndef __ASSEMBLER__ @@ -160,30 +160,30 @@ #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D /* 2 I2C master ports, connect to battery, charger, pd and USB switches */ -#define I2C_PORT_MASTER 0 -#define I2C_PORT_ACCEL 0 +#define I2C_PORT_MASTER 0 +#define I2C_PORT_ACCEL 0 #define I2C_PORT_BATTERY 0 #define I2C_PORT_CHARGER 0 #define I2C_PORT_PERICOM 0 #define I2C_PORT_THERMAL 0 -#define I2C_PORT_PD_MCU 1 +#define I2C_PORT_PD_MCU 1 #define I2C_PORT_USB_MUX 1 -#define I2C_PORT_TCPC 1 +#define I2C_PORT_TCPC 1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */ /* Timer selection */ #define TIM_CLOCK32 2 #define TIM_WATCHDOG 4 /* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)) #include "gpio_signal.h" @@ -201,9 +201,9 @@ enum pwm_channel { }; enum adc_channel { - ADC_PSYS = 0, /* PC1: STM32_AIN(2) */ + ADC_PSYS = 0, /* PC1: STM32_AIN(2) */ ADC_AMON_BMON, /* PC0: STM32_AIN(10) */ - ADC_VBUS, /* PA2: STM32_AIN(11) */ + ADC_VBUS, /* PA2: STM32_AIN(11) */ ADC_CH_COUNT }; @@ -231,16 +231,16 @@ enum sensor_id { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT +#define PD_MAX_VOLTAGE_MV 20000 /* The lower the input voltage, the higher the power efficiency. */ #define PD_PREFER_LOW_VOLTAGE @@ -250,6 +250,6 @@ void board_reset_pd_mcu(void); /* Set AP reset pin according to parameter */ void board_set_ap_reset(int asserted); -#endif /* !__ASSEMBLER__ */ +#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BOARD_H */ +#endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 866da6e5b04858316b142b2a567e3677a90cd5d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:06 -0600 Subject: board/willow/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17ebaee8fb8cd74c022757fb71f19e89d74cb69f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729132 Reviewed-by: Jeremy Bettis --- board/willow/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/willow/led.c b/board/willow/led.c index c579cb6165..527ecea72a 100644 --- a/board/willow/led.c +++ b/board/willow/led.c @@ -15,22 +15,27 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From 830e568a898d521d11f121e3f722c6d486d9f067 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:37 -0600 Subject: board/discovery-stm32f072/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5289a919e0d84007cd798287a0c76548119b6393 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728228 Reviewed-by: Jeremy Bettis --- board/discovery-stm32f072/board.h | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/discovery-stm32f072/board.h b/board/discovery-stm32f072/board.h index b889ebc8fe..d9be019aaa 100644 --- a/board/discovery-stm32f072/board.h +++ b/board/discovery-stm32f072/board.h @@ -32,27 +32,26 @@ #define CONFIG_USB_CONSOLE /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_STREAM 0 -#define USB_IFACE_GPIO 1 -#define USB_IFACE_SPI 2 +#define USB_IFACE_STREAM 0 +#define USB_IFACE_GPIO 1 +#define USB_IFACE_SPI 2 #define USB_IFACE_CONSOLE 3 -#define USB_IFACE_COUNT 4 +#define USB_IFACE_COUNT 4 /* USB endpoint indexes (use define rather than enum to expand them) */ #define USB_EP_CONTROL 0 -#define USB_EP_STREAM 1 -#define USB_EP_GPIO 2 -#define USB_EP_SPI 3 +#define USB_EP_STREAM 1 +#define USB_EP_GPIO 2 +#define USB_EP_SPI 3 #define USB_EP_CONSOLE 4 -#define USB_EP_COUNT 5 +#define USB_EP_COUNT 5 /* Enable control of GPIOs over USB */ #define CONFIG_USB_GPIO /* Enable control of SPI over USB */ #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */ - +#define CONFIG_SPI_FLASH_PORT 0 /* First SPI controller port */ #define CONFIG_USB_SPI -- cgit v1.2.1 From 89014d3ef3c6dade7a3e63b8f9acbf54bc0d099c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:57 -0600 Subject: include/driver/usb_mux/ps8743_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide78aaec549cccbdea074c44c4a36e353128b9cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730259 Reviewed-by: Jeremy Bettis --- include/driver/usb_mux/ps8743_public.h | 110 ++++++++++++++++----------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/include/driver/usb_mux/ps8743_public.h b/include/driver/usb_mux/ps8743_public.h index c20b948d07..8b9f323d5f 100644 --- a/include/driver/usb_mux/ps8743_public.h +++ b/include/driver/usb_mux/ps8743_public.h @@ -10,69 +10,69 @@ #include -#define PS8743_I2C_ADDR0_FLAG 0x10 -#define PS8743_I2C_ADDR1_FLAG 0x11 -#define PS8743_I2C_ADDR2_FLAG 0x19 -#define PS8743_I2C_ADDR3_FLAG 0x1a +#define PS8743_I2C_ADDR0_FLAG 0x10 +#define PS8743_I2C_ADDR1_FLAG 0x11 +#define PS8743_I2C_ADDR2_FLAG 0x19 +#define PS8743_I2C_ADDR3_FLAG 0x1a /* Mode register for setting mux */ #define PS8743_REG_MODE 0x00 -#define PS8743_MODE_IN_HPD_ASSERT BIT(0) -#define PS8743_MODE_IN_HPD_CONTROL BIT(1) -#define PS8743_MODE_FLIP_ENABLE BIT(2) +#define PS8743_MODE_IN_HPD_ASSERT BIT(0) +#define PS8743_MODE_IN_HPD_CONTROL BIT(1) +#define PS8743_MODE_FLIP_ENABLE BIT(2) #define PS8743_MODE_FLIP_REG_CONTROL BIT(3) -#define PS8743_MODE_USB_ENABLE BIT(4) -#define PS8743_MODE_USB_REG_CONTROL BIT(5) -#define PS8743_MODE_DP_ENABLE BIT(6) -#define PS8743_MODE_DP_REG_CONTROL BIT(7) +#define PS8743_MODE_USB_ENABLE BIT(4) +#define PS8743_MODE_USB_REG_CONTROL BIT(5) +#define PS8743_MODE_DP_ENABLE BIT(6) +#define PS8743_MODE_DP_REG_CONTROL BIT(7) /* To reset the state machine to default */ -#define PS8743_MODE_POWER_DOWN (PS8743_MODE_USB_REG_CONTROL | \ - PS8743_MODE_DP_REG_CONTROL) +#define PS8743_MODE_POWER_DOWN \ + (PS8743_MODE_USB_REG_CONTROL | PS8743_MODE_DP_REG_CONTROL) /* DP output setting */ -#define PS8743_REG_DP_SETTING 0x07 -#define PS8743_DP_SWG_ADJ_DFLT 0x00 -#define PS8743_DP_SWG_ADJ_N20P 0x40 -#define PS8743_DP_SWG_ADJ_N15P 0x80 -#define PS8743_DP_SWG_ADJ_P15P 0xc0 -#define PS8743_DP_OUT_SWG_400 0x00 -#define PS8743_DP_OUT_SWG_600 0x10 -#define PS8743_DP_OUT_SWG_800 0x20 -#define PS8743_DP_OUT_SWG_1000 0x30 -#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 +#define PS8743_REG_DP_SETTING 0x07 +#define PS8743_DP_SWG_ADJ_DFLT 0x00 +#define PS8743_DP_SWG_ADJ_N20P 0x40 +#define PS8743_DP_SWG_ADJ_N15P 0x80 +#define PS8743_DP_SWG_ADJ_P15P 0xc0 +#define PS8743_DP_OUT_SWG_400 0x00 +#define PS8743_DP_OUT_SWG_600 0x10 +#define PS8743_DP_OUT_SWG_800 0x20 +#define PS8743_DP_OUT_SWG_1000 0x30 +#define PS8743_DP_OUT_PRE_EM_0_DB 0x00 #define PS8743_DP_OUT_PRE_EM_3_5_DB 0x04 #define PS8743_DP_OUT_PRE_EM_6_0_DB 0x08 #define PS8743_DP_OUT_PRE_EM_9_5_DB 0x0c -#define PS8743_DP_POST_CUR2_0_DB 0x00 +#define PS8743_DP_POST_CUR2_0_DB 0x00 #define PS8743_DP_POST_CUR2_NEG_0_9_DB 0x01 #define PS8743_DP_POST_CUR2_NEG_1_9_DB 0x02 #define PS8743_DP_POST_CUR2_NEG_3_1_DB 0x03 /* USB equalization settings for Host to Mux */ -#define PS8743_REG_USB_EQ_TX 0x32 +#define PS8743_REG_USB_EQ_TX 0x32 #define PS8743_USB_EQ_TX_12_8_DB 0x00 -#define PS8743_USB_EQ_TX_17_DB 0x20 -#define PS8743_USB_EQ_TX_7_7_DB 0x40 -#define PS8743_USB_EQ_TX_3_6_DB 0x60 -#define PS8743_USB_EQ_TX_15_DB 0x80 +#define PS8743_USB_EQ_TX_17_DB 0x20 +#define PS8743_USB_EQ_TX_7_7_DB 0x40 +#define PS8743_USB_EQ_TX_3_6_DB 0x60 +#define PS8743_USB_EQ_TX_15_DB 0x80 #define PS8743_USB_EQ_TX_10_9_DB 0xc0 -#define PS8743_USB_EQ_TX_4_5_DB 0xe0 +#define PS8743_USB_EQ_TX_4_5_DB 0xe0 /* USB swing adjust for Mux to Type-C connector */ -#define PS8743_REG_USB_SWING 0x36 -#define PS8743_OUT_SWG_DEFAULT 0x00 -#define PS8743_OUT_SWG_NEG_20 0x40 -#define PS8743_OUT_SWG_NEG_15 0x80 -#define PS8743_OUT_SWG_POS_15 0xc0 -#define PS8743_LFPS_SWG_DEFAULT 0x00 -#define PS8743_LFPS_SWG_TD 0x08 +#define PS8743_REG_USB_SWING 0x36 +#define PS8743_OUT_SWG_DEFAULT 0x00 +#define PS8743_OUT_SWG_NEG_20 0x40 +#define PS8743_OUT_SWG_NEG_15 0x80 +#define PS8743_OUT_SWG_POS_15 0xc0 +#define PS8743_LFPS_SWG_DEFAULT 0x00 +#define PS8743_LFPS_SWG_TD 0x08 /* USB equalization settings for Connector to Mux */ -#define PS8743_REG_USB_EQ_RX 0x3b -#define PS8743_USB_EQ_RX_2_4_DB 0x00 -#define PS8743_USB_EQ_RX_5_DB 0x10 -#define PS8743_USB_EQ_RX_6_5_DB 0x20 -#define PS8743_USB_EQ_RX_7_4_DB 0x30 -#define PS8743_USB_EQ_RX_8_7_DB 0x40 +#define PS8743_REG_USB_EQ_RX 0x3b +#define PS8743_USB_EQ_RX_2_4_DB 0x00 +#define PS8743_USB_EQ_RX_5_DB 0x10 +#define PS8743_USB_EQ_RX_6_5_DB 0x20 +#define PS8743_USB_EQ_RX_7_4_DB 0x30 +#define PS8743_USB_EQ_RX_8_7_DB 0x40 #define PS8743_USB_EQ_RX_10_9_DB 0x50 #define PS8743_USB_EQ_RX_12_8_DB 0x60 #define PS8743_USB_EQ_RX_13_8_DB 0x70 @@ -85,21 +85,21 @@ #define PS8743_USB_EQ_RX_22_2_DB 0xe0 /* USB High Speed Signal Detector thershold adjustment */ -#define PS8743_REG_HS_DET_THRESHOLD 0x3c +#define PS8743_REG_HS_DET_THRESHOLD 0x3c #define PS8743_USB_HS_THRESH_DEFAULT 0x00 -#define PS8743_USB_HS_THRESH_POS_10 0x20 -#define PS8743_USB_HS_THRESH_POS_33 0x40 -#define PS8743_USB_HS_THRESH_NEG_10 0x60 -#define PS8743_USB_HS_THRESH_NEG_25 0x80 -#define PS8743_USB_HS_THRESH_POS_25 0xa0 -#define PS8743_USB_HS_THRESH_NEG_45 0xc0 -#define PS8743_USB_HS_THRESH_NEG_35 0xe0 +#define PS8743_USB_HS_THRESH_POS_10 0x20 +#define PS8743_USB_HS_THRESH_POS_33 0x40 +#define PS8743_USB_HS_THRESH_NEG_10 0x60 +#define PS8743_USB_HS_THRESH_NEG_25 0x80 +#define PS8743_USB_HS_THRESH_POS_25 0xa0 +#define PS8743_USB_HS_THRESH_NEG_45 0xc0 +#define PS8743_USB_HS_THRESH_NEG_35 0xe0 /* DCI config: 0x45~0x4D */ -#define PS8743_REG_DCI_CONFIG_2 0x47 -#define PS8743_AUTO_DCI_MODE_SHIFT 6 -#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) -#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_REG_DCI_CONFIG_2 0x47 +#define PS8743_AUTO_DCI_MODE_SHIFT 6 +#define PS8743_AUTO_DCI_MODE_MASK (3 << PS8743_AUTO_DCI_MODE_SHIFT) +#define PS8743_AUTO_DCI_MODE_ENABLE (0 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_USB (2 << PS8743_AUTO_DCI_MODE_SHIFT) #define PS8743_AUTO_DCI_MODE_FORCE_DCI (3 << PS8743_AUTO_DCI_MODE_SHIFT) -- cgit v1.2.1 From 2e911894a70cb378edd54ab3ed9abc4a02f87fb8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:03 -0600 Subject: board/corori/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I60b525e5f25f3d473a74193d40865f8044d61f2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728179 Reviewed-by: Jeremy Bettis --- board/corori/board.c | 113 ++++++++++++++++++++++----------------------------- 1 file changed, 49 insertions(+), 64 deletions(-) diff --git a/board/corori/board.c b/board/corori/board.c index 3453fccef4..b4a8c2a8ef 100644 --- a/board/corori/board.c +++ b/board/corori/board.c @@ -40,14 +40,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 -#define ADC_VOL_UP_MASK BIT(0) -#define ADC_VOL_DOWN_MASK BIT(1) - +#define ADC_VOL_UP_MASK BIT(0) +#define ADC_VOL_DOWN_MASK BIT(1) /******************************************************************************/ /* USB-A Configuration */ @@ -73,8 +72,8 @@ static const struct ec_response_keybd_config corori_keybd = { /* No function keys, no numeric keypad, no screenlock key */ }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &corori_keybd; } @@ -115,7 +114,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -154,22 +152,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ @@ -186,8 +184,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -249,13 +247,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -315,8 +311,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -353,9 +349,8 @@ void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -446,46 +441,36 @@ static void board_extpower(void) DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT); const struct i2c_port_t i2c_ports[] = { - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C_BATTERY_SCL, - .sda = GPIO_EC_I2C_BATTERY_SDA - }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C_BATTERY_SCL, + .sda = GPIO_EC_I2C_BATTERY_SDA }, #ifdef HAS_TASK_MOTIONSENSE - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, #endif - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_SCL, - .sda = GPIO_EC_I2C_USB_C0_SDA - }, + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_SCL, + .sda = GPIO_EC_I2C_USB_C0_SDA }, #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - { - .name = "sub_usbc1", - .port = I2C_PORT_SUB_USB_C1, - .kbps = 1000, - .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, - .sda = GPIO_EC_I2C_SUB_USB_C1_SDA - }, + { .name = "sub_usbc1", + .port = I2C_PORT_SUB_USB_C1, + .kbps = 1000, + .scl = GPIO_EC_I2C_SUB_USB_C1_SCL, + .sda = GPIO_EC_I2C_SUB_USB_C1_SDA }, #endif }; -- cgit v1.2.1 From dd4b4ecf4f66ed476281002b16dc2fbd9c4ce491 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:30 -0600 Subject: board/felwinter/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I937f48cb6e685055b49d4f7698d889fd4ce86d49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728362 Reviewed-by: Jeremy Bettis --- board/felwinter/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/felwinter/usbc_config.h b/board/felwinter/usbc_config.h index 9f0a26210f..22247e67cc 100644 --- a/board/felwinter/usbc_config.h +++ b/board/felwinter/usbc_config.h @@ -8,15 +8,11 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #define CONFIG_USB_MUX_RUNTIME_CONFIG -enum usbc_port { - USBC_PORT_C2 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); void db_update_usb4_config_from_config(void); -- cgit v1.2.1 From 128a321084c18587ff657e63d93182e7690dfb11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:07 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91ebe3238f60914b22c0836bd1c71c193b54df49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730941 Reviewed-by: Jeremy Bettis --- .../src/integration/usbc/usb_5v_3a_pd_sink.c | 25 ++++++++++------------ 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c index 830e6246e9..6380eaecf2 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c @@ -54,9 +54,8 @@ connect_sink_to_port(struct usb_attach_5v_3a_pd_sink_fixture *fixture) tcpci_tcpc_alert(0); k_sleep(K_SECONDS(1)); - zassume_ok(tcpci_partner_connect_to_tcpci( - &fixture->sink_5v_3a, - fixture->tcpci_emul), + zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->sink_5v_3a, + fixture->tcpci_emul), NULL); /* Wait for PD negotiation and current ramp. @@ -65,8 +64,8 @@ connect_sink_to_port(struct usb_attach_5v_3a_pd_sink_fixture *fixture) k_sleep(K_SECONDS(10)); } -static inline void disconnect_sink_from_port( - struct usb_attach_5v_3a_pd_sink_fixture *fixture) +static inline void +disconnect_sink_from_port(struct usb_attach_5v_3a_pd_sink_fixture *fixture) { zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); k_sleep(K_SECONDS(1)); @@ -98,9 +97,8 @@ static void usb_attach_5v_3a_pd_sink_before(void *data) /* Initialized the sink to request 5V and 3A */ tcpci_partner_init(&test_fixture->sink_5v_3a, PD_REV20); - test_fixture->sink_5v_3a.extensions = - tcpci_snk_emul_init(&test_fixture->snk_ext, - &test_fixture->sink_5v_3a, NULL); + test_fixture->sink_5v_3a.extensions = tcpci_snk_emul_init( + &test_fixture->snk_ext, &test_fixture->sink_5v_3a, NULL); test_fixture->snk_ext.pdo[0] = TEST_INITIAL_SINK_CAP; test_fixture->snk_ext.pdo[1] = TEST_ADDITIONAL_SINK_CAP; connect_sink_to_port(test_fixture); @@ -113,8 +111,7 @@ static void usb_attach_5v_3a_pd_sink_after(void *data) } ZTEST_SUITE(usb_attach_5v_3a_pd_sink, drivers_predicate_post_main, - usb_attach_5v_3a_pd_sink_setup, - usb_attach_5v_3a_pd_sink_before, + usb_attach_5v_3a_pd_sink_setup, usb_attach_5v_3a_pd_sink_before, usb_attach_5v_3a_pd_sink_after, NULL); ZTEST_F(usb_attach_5v_3a_pd_sink, test_partner_pd_completed) @@ -171,11 +168,11 @@ ZTEST(usb_attach_5v_3a_pd_sink, test_power_info) "Current max expected to be 1500mV, but was %dmV", info.meas.current_max); zassert_equal(info.meas.current_lim, 0, - "VBUS max is set to 0mA, but PD is reporting %dmA", - info.meas.current_lim); + "VBUS max is set to 0mA, but PD is reporting %dmA", + info.meas.current_lim); zassert_equal(info.max_power, 0, - "Charging expected to be at %duW, but PD max is %duW", - 0, info.max_power); + "Charging expected to be at %duW, but PD max is %duW", 0, + info.max_power); } ZTEST_F(usb_attach_5v_3a_pd_sink, test_disconnect_battery_discharging) -- cgit v1.2.1 From 921b30006eb53b6769c3f936c86a4dfce3960120 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:41 -0600 Subject: chip/stm32/spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia589cc9e9c8d82921464a5c0daa5a938a9275a07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729410 Reviewed-by: Jeremy Bettis --- chip/stm32/spi.c | 49 ++++++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index 268b7880e6..5d78e9c89a 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -24,8 +24,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) /* SPI FIFO registers */ #ifdef CHIP_FAMILY_STM32H7 @@ -41,7 +41,7 @@ static const struct dma_option dma_tx_option = { STM32_DMAC_SPI1_TX, (void *)&SPI_TXDR, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(STM32_SPI1_TX_REQ_CH) #endif }; @@ -49,7 +49,7 @@ static const struct dma_option dma_rx_option = { STM32_DMAC_SPI1_RX, (void *)&SPI_RXDR, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT #ifdef CHIP_FAMILY_STM32F4 - | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) + | STM32_DMA_CCR_CHANNEL(STM32_SPI1_RX_REQ_CH) #endif }; @@ -71,8 +71,8 @@ static const struct dma_option dma_rx_option = { * the AP will have a known and identifiable value. */ #define SPI_PROTO2_OFFSET (EC_PROTO2_RESPONSE_HEADER_BYTES + 2) -#define SPI_PROTO2_OVERHEAD (SPI_PROTO2_OFFSET + \ - EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) +#define SPI_PROTO2_OVERHEAD \ + (SPI_PROTO2_OFFSET + EC_PROTO2_RESPONSE_TRAILER_BYTES + 1) #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ /* * Max data size for a version 3 request/response packet. This is big enough @@ -92,10 +92,8 @@ static const struct dma_option dma_rx_option = { * 32-bit aligned. */ static const uint8_t out_preamble[4] = { - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_PROCESSING, - EC_SPI_FRAME_START, /* This is the byte which matters */ + EC_SPI_PROCESSING, EC_SPI_PROCESSING, EC_SPI_PROCESSING, + EC_SPI_FRAME_START, /* This is the byte which matters */ }; /* @@ -117,7 +115,7 @@ static const uint8_t out_preamble[4] = { * message, including protocol overhead, and must be 32-bit aligned. */ static uint8_t out_msg[SPI_MAX_RESPONSE_SIZE + sizeof(out_preamble) + - EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; + EC_SPI_PAST_END_LENGTH] __aligned(4) __uncached; static uint8_t in_msg[SPI_MAX_REQUEST_SIZE] __aligned(4) __uncached; static uint8_t enabled; #ifdef CONFIG_SPI_PROTOCOL_V2 @@ -172,8 +170,7 @@ enum spi_state { * @param nss GPIO signal for NSS control line * @return 0 if bytes received, -1 if we hit a timeout or NSS went high */ -static int wait_for_bytes(dma_chan_t *rxdma, int needed, - enum gpio_signal nss) +static int wait_for_bytes(dma_chan_t *rxdma, int needed, enum gpio_signal nss) { timestamp_t deadline; @@ -230,8 +227,8 @@ static int wait_for_bytes(dma_chan_t *rxdma, int needed, * SPI_PROTO2_OFFSET bytes into out_msg * @param msg_len Number of message bytes to send */ -static void reply(dma_chan_t *txdma, - enum ec_status status, char *msg_ptr, int msg_len) +static void reply(dma_chan_t *txdma, enum ec_status status, char *msg_ptr, + int msg_len) { char *msg = out_msg; int need_copy = msg_ptr != msg + SPI_PROTO2_OFFSET; @@ -438,8 +435,10 @@ static void spi_send_response_packet(struct host_packet *pkt) /* Transmit the reply */ txdma = dma_get_channel(STM32_DMAC_SPI1_TX); - dma_prepare_tx(&dma_tx_option, sizeof(out_preamble) + pkt->response_size - + EC_SPI_PAST_END_LENGTH, out_msg); + dma_prepare_tx(&dma_tx_option, + sizeof(out_preamble) + pkt->response_size + + EC_SPI_PAST_END_LENGTH, + out_msg); dma_go(txdma); #ifdef CHIP_FAMILY_STM32H7 /* clear any previous underrun */ @@ -544,8 +543,9 @@ void spi_event(enum gpio_signal signal) memcpy(out_msg, out_preamble, sizeof(out_preamble)); spi_packet.response = out_msg + sizeof(out_preamble); /* Reserve space for the preamble and trailing past-end byte */ - spi_packet.response_max = sizeof(out_msg) - - sizeof(out_preamble) - EC_SPI_PAST_END_LENGTH; + spi_packet.response_max = sizeof(out_msg) - + sizeof(out_preamble) - + EC_SPI_PAST_END_LENGTH; spi_packet.response_size = 0; spi_packet.driver_result = EC_RES_SUCCESS; @@ -608,7 +608,7 @@ void spi_event(enum gpio_signal signal) #endif /* defined(CONFIG_SPI_PROTOCOL_V2) */ } - spi_event_error: +spi_event_error: /* Error, timeout, or protocol we can't handle. Ignore data. */ tx_status(EC_SPI_RX_BAD_DATA); state = SPI_STATE_RX_BAD; @@ -701,14 +701,13 @@ static void spi_init(void) #ifdef CHIP_FAMILY_STM32H7 spi->cfg2 = 0; spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | - STM32_SPI_CFG1_CRCSIZE(8) | - STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN | - STM32_SPI_CFG1_UDRCFG_CONST | - STM32_SPI_CFG1_UDRDET_BEGIN_FRM; + STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CFG1_TXDMAEN | + STM32_SPI_CFG1_RXDMAEN | STM32_SPI_CFG1_UDRCFG_CONST | + STM32_SPI_CFG1_UDRDET_BEGIN_FRM; spi->cr1 = 0; #else /* !CHIP_FAMILY_STM32H7 */ spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); + STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); /* Enable the SPI peripheral */ spi->cr1 |= STM32_SPI_CR1_SPE; -- cgit v1.2.1 From a2bc278cbd14226443bbfef64434d2734bed69e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:05 -0600 Subject: board/pico/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id077ed44b405ab4f2bf5eb1517b3cac69626558e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728825 Reviewed-by: Jeremy Bettis --- board/pico/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/pico/led.c b/board/pico/led.c index 076199b2ed..c0e6db6874 100644 --- a/board/pico/led.c +++ b/board/pico/led.c @@ -14,22 +14,27 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From 8907883338526605630b20d61c57d2185c8e4ff0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:14 -0600 Subject: board/driblee/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a652ae91ece72a64dc8989fe269c9dd17ce8bfa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728261 Reviewed-by: Jeremy Bettis --- board/driblee/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/driblee/led.c b/board/driblee/led.c index cd34613a7c..9f417d2c0c 100644 --- a/board/driblee/led.c +++ b/board/driblee/led.c @@ -19,23 +19,32 @@ __override const int led_charge_lvl_1 = 10; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 09a1da151e41412d3ba7cdf4ffb551d7d7f48d95 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:53 -0600 Subject: common/throttle_ap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I29a63a1849bb23b0dbd2d592e289f551b27a81f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729755 Reviewed-by: Jeremy Bettis --- common/throttle_ap.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/common/throttle_ap.c b/common/throttle_ap.c index 33e004ba7b..c47f509c6d 100644 --- a/common/throttle_ap.c +++ b/common/throttle_ap.c @@ -19,15 +19,15 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) /* * When C10 deasserts, PROCHOT may also change state when the corresponding * power rail is turned back on. Recheck PROCHOT directly from the C10 exit * using a shorter debounce than the PROCHOT interrupt. */ -#define PROCHOT_IN_DEBOUNCE_US (100 * MSEC) -#define C10_IN_DEBOUNCE_US (10 * MSEC) +#define PROCHOT_IN_DEBOUNCE_US (100 * MSEC) +#define C10_IN_DEBOUNCE_US (10 * MSEC) /*****************************************************************************/ /* This enforces the virtual OR of all throttling sources. */ @@ -36,8 +36,7 @@ static uint32_t throttle_request[NUM_THROTTLE_TYPES]; static int debounced_prochot_in; static const struct prochot_cfg *prochot_cfg; -void throttle_ap(enum throttle_level level, - enum throttle_type type, +void throttle_ap(enum throttle_level level, enum throttle_type type, enum throttle_sources source) { uint32_t tmpval, bitmask; @@ -55,7 +54,7 @@ void throttle_ap(enum throttle_level level, break; } - tmpval = throttle_request[type]; /* save for printing */ + tmpval = throttle_request[type]; /* save for printing */ switch (type) { case THROTTLE_SOFT: @@ -79,9 +78,8 @@ void throttle_ap(enum throttle_level level, mutex_unlock(&throttle_mutex); /* print outside the mutex */ - CPRINTS("set AP throttling type %d to %s (0x%08x)", - type, tmpval ? "on" : "off", tmpval); - + CPRINTS("set AP throttling type %d to %s (0x%08x)", type, + tmpval ? "on" : "off", tmpval); } void throttle_ap_config_prochot(const struct prochot_cfg *cfg) @@ -163,7 +161,7 @@ void throttle_ap_prochot_input_interrupt(enum gpio_signal signal) * any pulses that are too short. */ hook_call_deferred(&prochot_input_deferred_data, - PROCHOT_IN_DEBOUNCE_US); + PROCHOT_IN_DEBOUNCE_US); } #ifdef CONFIG_CPU_PROCHOT_GATE_ON_C10 @@ -197,7 +195,6 @@ static int command_apthrottle(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle, - NULL, +DECLARE_CONSOLE_COMMAND(apthrottle, command_apthrottle, NULL, "Display the AP throttling state"); #endif -- cgit v1.2.1 From 7fc827643e361bd2a549e28369ee9f9da0dfb2d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:25 -0600 Subject: test/fp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ed7eef29e78c46ec031d4ba8f43c287a97242ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730477 Reviewed-by: Jeremy Bettis --- test/fp.c | 125 +++++++++++++++++++++++++++++--------------------------------- 1 file changed, 59 insertions(+), 66 deletions(-) diff --git a/test/fp.c b/test/fp.c index 2d9aa1ed5e..f13b70036b 100644 --- a/test/fp.c +++ b/test/fp.c @@ -36,9 +36,9 @@ #error "No such test configuration." #endif -#define IS_FPV3_VECTOR_EQUAL(a, b, diff) \ - (IS_FP_EQUAL((a)[0], (b)[0], (diff)) && \ - IS_FP_EQUAL((a)[1], (b)[1], (diff)) && \ +#define IS_FPV3_VECTOR_EQUAL(a, b, diff) \ + (IS_FP_EQUAL((a)[0], (b)[0], (diff)) && \ + IS_FP_EQUAL((a)[1], (b)[1], (diff)) && \ IS_FP_EQUAL((a)[2], (b)[2], (diff))) #define IS_FP_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff)) #define IS_FLOAT_EQUAL(a, b, diff) IS_FP_EQUAL(a, b, diff) @@ -47,9 +47,9 @@ static int test_fpv3_scalar_mul(void) { const int N = 3; const float s = 2.0f; - floatv3_t r = {1.0f, 2.0f, 4.0f}; + floatv3_t r = { 1.0f, 2.0f, 4.0f }; /* Golden result g = s * r; */ - const floatv3_t g = {2.0f, 4.0f, 8.0f}; + const floatv3_t g = { 2.0f, 4.0f, 8.0f }; int i; fpv3_t a; @@ -68,8 +68,8 @@ static int test_fpv3_dot(void) { const int N = 3; int i; - floatv3_t a = {1.8f, 2.12f, 4.12f}; - floatv3_t b = {3.1f, 4.3f, 5.8f}; + floatv3_t a = { 1.8f, 2.12f, 4.12f }; + floatv3_t b = { 3.1f, 4.3f, 5.8f }; /* Golden result g = dot(a, b). */ float g = 38.592f; fpv3_t fpa, fpb; @@ -81,8 +81,7 @@ static int test_fpv3_dot(void) } result = fpv3_dot(fpa, fpb); - TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), - DOT_TOLERANCE)); + TEST_ASSERT(IS_FP_EQUAL(result, FLOAT_TO_FP(g), DOT_TOLERANCE)); return EC_SUCCESS; } @@ -91,7 +90,7 @@ static int test_fpv3_norm_squared(void) { const int N = 3; int i; - floatv3_t a = {3.0f, 4.0f, 5.0f}; + floatv3_t a = { 3.0f, 4.0f, 5.0f }; /* Golden result g = norm_squared(a). */ float g = 50.0f; fpv3_t fpa; @@ -108,7 +107,7 @@ static int test_fpv3_norm_squared(void) static int test_fpv3_norm(void) { const int N = 3; - floatv3_t a = {3.1f, 4.2f, 5.3f}; + floatv3_t a = { 3.1f, 4.2f, 5.3f }; /* Golden result g = norm(a). */ float g = 7.439086f; int i; @@ -188,17 +187,14 @@ static int test_mat33_fp_scalar_mul(void) { const int N = 3; float scale = 3.11f; - mat33_float_t a = { - {1.0f, 2.0f, 3.0f}, - {1.1f, 2.2f, 3.3f}, - {0.38f, 13.2f, 88.3f} - }; + mat33_float_t a = { { 1.0f, 2.0f, 3.0f }, + { 1.1f, 2.2f, 3.3f }, + { 0.38f, 13.2f, 88.3f } }; /* Golden result g = scalar_mul(a, scale). */ - mat33_float_t g = {{3.11f, 6.22f, 9.33f}, - {3.421f, 6.842f, 10.263f}, - {1.18179988861083984375f, 41.051998138427734375f, - 274.613006591796875f} - }; + mat33_float_t g = { { 3.11f, 6.22f, 9.33f }, + { 3.421f, 6.842f, 10.263f }, + { 1.18179988861083984375f, 41.051998138427734375f, + 274.613006591796875f } }; int i, j; mat33_fp_t fpa; @@ -219,9 +215,9 @@ static int test_mat33_fp_scalar_mul(void) static int test_mat33_fp_get_eigenbasis(void) { mat33_fp_t s = { - {FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f)}, - {FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f)}, - {FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f)} + { FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f) }, + { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f), FLOAT_TO_FP(2.0f) }, + { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(2.0f), FLOAT_TO_FP(4.0f) } }; fpv3_t e_vals; mat33_fp_t e_vecs; @@ -229,15 +225,15 @@ static int test_mat33_fp_get_eigenbasis(void) /* Golden result from float version. */ mat33_fp_t gold_vecs = { - {FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f), - FLOAT_TO_FP(0.55735206f)}, - {FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f), - FLOAT_TO_FP(0.0f)}, - {FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f), - FLOAT_TO_FP(0.81649655f)} + { FLOAT_TO_FP(0.55735206f), FLOAT_TO_FP(0.55735206f), + FLOAT_TO_FP(0.55735206f) }, + { FLOAT_TO_FP(0.70710677f), FLOAT_TO_FP(-0.70710677f), + FLOAT_TO_FP(0.0f) }, + { FLOAT_TO_FP(-0.40824828f), FLOAT_TO_FP(-0.40824828f), + FLOAT_TO_FP(0.81649655f) } }; - fpv3_t gold_vals = {FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f), - FLOAT_TO_FP(2.0f)}; + fpv3_t gold_vals = { FLOAT_TO_FP(8.0f), FLOAT_TO_FP(2.0f), + FLOAT_TO_FP(2.0f) }; mat33_fp_get_eigenbasis(s, e_vals, e_vecs); @@ -257,28 +253,26 @@ static int test_mat44_fp_decompose_lup(void) { int i, j; sizev4_t pivot; - mat44_fp_t fpa = { - {FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f), - FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f)}, - {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f), - FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f)}, - {FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f), - FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f)}, - {FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f), - FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f)} - }; + mat44_fp_t fpa = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(9.0f), + FLOAT_TO_FP(24.0f), FLOAT_TO_FP(2.0f) }, + { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(5.0f), + FLOAT_TO_FP(2.0f), FLOAT_TO_FP(6.0f) }, + { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(17.0f), + FLOAT_TO_FP(18.0f), FLOAT_TO_FP(1.0f) }, + { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(5.0f), + FLOAT_TO_FP(7.0f), FLOAT_TO_FP(1.0f) } }; /* Golden result from float version. */ mat44_fp_t gold_lu = { - {FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f), - FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)}, - {FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f), - FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f)}, - {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f), - FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f)}, - {FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f), - FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f)} + { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f), + FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) }, + { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545455f), + FLOAT_TO_FP(0.78749999f), FLOAT_TO_FP(0.031249999f) }, + { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f), + FLOAT_TO_FP(-3.4749996f), FLOAT_TO_FP(-1.6366909f) }, + { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f), + FLOAT_TO_FP(-0.012500112f), FLOAT_TO_FP(0.5107912f) } }; - sizev4_t gold_pivot = {0, 2, 2, 3}; + sizev4_t gold_pivot = { 0, 2, 2, 3 }; mat44_fp_decompose_lup(fpa, pivot); @@ -296,22 +290,21 @@ static int test_mat44_fp_solve(void) { int i; fpv4_t x; - mat44_fp_t A = { - {FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f), - FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f)}, - {FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454), - FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f)}, - {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f), - FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f)}, - {FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f), - FLOAT_TO_FP(-0.012500286f), FLOAT_TO_FP(0.5107909f)} - }; - sizev4_t pivot = {0, 2, 2, 3}; - fpv4_t b = {FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f), - FLOAT_TO_FP(8.9f)}; + mat44_fp_t A = { { FLOAT_TO_FP(11.0f), FLOAT_TO_FP(0.8181818f), + FLOAT_TO_FP(2.1818182f), FLOAT_TO_FP(0.18181819f) }, + { FLOAT_TO_FP(3.0f), FLOAT_TO_FP(14.545454), + FLOAT_TO_FP(0.7875f), FLOAT_TO_FP(0.03125f) }, + { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(4.181818f), + FLOAT_TO_FP(-3.4750001f), FLOAT_TO_FP(-1.6366906f) }, + { FLOAT_TO_FP(2.0f), FLOAT_TO_FP(3.3636365f), + FLOAT_TO_FP(-0.012500286f), + FLOAT_TO_FP(0.5107909f) } }; + sizev4_t pivot = { 0, 2, 2, 3 }; + fpv4_t b = { FLOAT_TO_FP(1.0f), FLOAT_TO_FP(3.3f), FLOAT_TO_FP(0.8f), + FLOAT_TO_FP(8.9f) }; /* Golden result from float version. */ - fpv4_t gold_x = {FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f), - FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f)}; + fpv4_t gold_x = { FLOAT_TO_FP(-43.507435f), FLOAT_TO_FP(-21.459525f), + FLOAT_TO_FP(26.629248f), FLOAT_TO_FP(16.80776f) }; mat44_fp_solve(A, x, b, pivot); -- cgit v1.2.1 From f39b586a84bfc90d1ebb03142179e0f662a25da8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:04 -0600 Subject: board/scout/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I89dce772179d8fee284f688debf63854dac8fa97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728902 Reviewed-by: Jeremy Bettis --- board/scout/board.h | 94 +++++++++++++++++++++++++---------------------------- 1 file changed, 45 insertions(+), 49 deletions(-) diff --git a/board/scout/board.h b/board/scout/board.h index 53958b1686..636bcee8fd 100644 --- a/board/scout/board.h +++ b/board/scout/board.h @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -50,7 +50,7 @@ #define CONFIG_SHA256 /* Sensor */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (1000 * MSEC) #define CONFIG_CMD_ACCEL_INFO /* Enable sensor fifo, must also define the _SIZE and _THRES */ @@ -139,14 +139,14 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_SCALER NPCX_I2C_PORT2_0 -#define I2C_PORT_SENSORS NPCX_I2C_PORT3_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_SCALER NPCX_I2C_PORT2_0 +#define I2C_PORT_SENSORS NPCX_I2C_PORT3_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -164,12 +164,12 @@ enum board_version { }; enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -194,11 +194,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_WIFI, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_WIFI, TEMP_SENSOR_COUNT }; enum sensor_id { CLEAR_ALS, @@ -218,20 +214,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) int ec_config_get_usb4_present(void); @@ -240,30 +236,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 85f40e43d169e02c04dc36b70a550cc949ea13d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:46 -0600 Subject: board/treeya/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e83902b07fc351c410304d463539d4c7ae31535 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729033 Reviewed-by: Jeremy Bettis --- board/treeya/led.c | 53 ++++++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 25 deletions(-) diff --git a/board/treeya/led.c b/board/treeya/led.c index 9647b45e74..872cb290c3 100644 --- a/board/treeya/led.c +++ b/board/treeya/led.c @@ -8,40 +8,43 @@ #include "led_common.h" #include "gpio.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 6d4b73ac406acf77293659f425f17c9b0441d1eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:42 -0600 Subject: zephyr/shim/src/chipset_state_check.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e6a6f3b5e64691a8ae44b6e626e6a0408b9c7e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730889 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/chipset_state_check.h | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/zephyr/shim/src/chipset_state_check.h b/zephyr/shim/src/chipset_state_check.h index 879f700d89..78f3add6fb 100644 --- a/zephyr/shim/src/chipset_state_check.h +++ b/zephyr/shim/src/chipset_state_check.h @@ -9,19 +9,12 @@ #include "chipset.h" #include "ap_power/ap_power_interface.h" -BUILD_ASSERT((int)AP_POWER_STATE_HARD_OFF == - (int)CHIPSET_STATE_HARD_OFF); -BUILD_ASSERT((int)AP_POWER_STATE_SOFT_OFF == - (int)CHIPSET_STATE_SOFT_OFF); -BUILD_ASSERT((int)AP_POWER_STATE_SUSPEND == - (int)CHIPSET_STATE_SUSPEND); -BUILD_ASSERT((int)AP_POWER_STATE_ON == - (int)CHIPSET_STATE_ON); -BUILD_ASSERT((int)AP_POWER_STATE_STANDBY == - (int)CHIPSET_STATE_STANDBY); -BUILD_ASSERT((int)AP_POWER_STATE_ANY_OFF == - (int)CHIPSET_STATE_ANY_OFF); -BUILD_ASSERT((int)AP_POWER_STATE_ANY_SUSPEND == - (int)CHIPSET_STATE_ANY_SUSPEND); +BUILD_ASSERT((int)AP_POWER_STATE_HARD_OFF == (int)CHIPSET_STATE_HARD_OFF); +BUILD_ASSERT((int)AP_POWER_STATE_SOFT_OFF == (int)CHIPSET_STATE_SOFT_OFF); +BUILD_ASSERT((int)AP_POWER_STATE_SUSPEND == (int)CHIPSET_STATE_SUSPEND); +BUILD_ASSERT((int)AP_POWER_STATE_ON == (int)CHIPSET_STATE_ON); +BUILD_ASSERT((int)AP_POWER_STATE_STANDBY == (int)CHIPSET_STATE_STANDBY); +BUILD_ASSERT((int)AP_POWER_STATE_ANY_OFF == (int)CHIPSET_STATE_ANY_OFF); +BUILD_ASSERT((int)AP_POWER_STATE_ANY_SUSPEND == (int)CHIPSET_STATE_ANY_SUSPEND); #endif /* __CHIPSET_STATE_CHECK_H__ */ -- cgit v1.2.1 From 9f6fde7f1c26081efc9a3cd9ae88bb9d6f39e624 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:14 -0600 Subject: common/hooks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic50de12d20ced5b05ab07929fcc10ba1b4eecfe4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729632 Reviewed-by: Jeremy Bettis --- common/hooks.c | 64 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/common/hooks.c b/common/hooks.c index ed626d2638..61904eea59 100644 --- a/common/hooks.c +++ b/common/hooks.c @@ -14,7 +14,7 @@ #ifdef CONFIG_HOOK_DEBUG #define CPUTS(outstr) cputs(CC_HOOK, outstr) -#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args) #else #define CPUTS(outstr) #define CPRINTS(format, args...) @@ -32,38 +32,38 @@ struct hook_ptrs { * order as enum hook_type. */ static const struct hook_ptrs hook_list[] = { - {__hooks_init, __hooks_init_end}, - {__hooks_pre_freq_change, __hooks_pre_freq_change_end}, - {__hooks_freq_change, __hooks_freq_change_end}, - {__hooks_sysjump, __hooks_sysjump_end}, - {__hooks_chipset_pre_init, __hooks_chipset_pre_init_end}, - {__hooks_chipset_startup, __hooks_chipset_startup_end}, - {__hooks_chipset_resume, __hooks_chipset_resume_end}, - {__hooks_chipset_suspend, __hooks_chipset_suspend_end}, + { __hooks_init, __hooks_init_end }, + { __hooks_pre_freq_change, __hooks_pre_freq_change_end }, + { __hooks_freq_change, __hooks_freq_change_end }, + { __hooks_sysjump, __hooks_sysjump_end }, + { __hooks_chipset_pre_init, __hooks_chipset_pre_init_end }, + { __hooks_chipset_startup, __hooks_chipset_startup_end }, + { __hooks_chipset_resume, __hooks_chipset_resume_end }, + { __hooks_chipset_suspend, __hooks_chipset_suspend_end }, #ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK - {__hooks_chipset_resume_init, __hooks_chipset_resume_init_end}, - {__hooks_chipset_suspend_complete, - __hooks_chipset_suspend_complete_end}, + { __hooks_chipset_resume_init, __hooks_chipset_resume_init_end }, + { __hooks_chipset_suspend_complete, + __hooks_chipset_suspend_complete_end }, #endif - {__hooks_chipset_shutdown, __hooks_chipset_shutdown_end}, - {__hooks_chipset_shutdown_complete, - __hooks_chipset_shutdown_complete_end}, - {__hooks_chipset_hard_off, __hooks_chipset_hard_off_end}, - {__hooks_chipset_reset, __hooks_chipset_reset_end}, - {__hooks_ac_change, __hooks_ac_change_end}, - {__hooks_lid_change, __hooks_lid_change_end}, - {__hooks_tablet_mode_change, __hooks_tablet_mode_change_end}, - {__hooks_base_attached_change, __hooks_base_attached_change_end}, - {__hooks_pwrbtn_change, __hooks_pwrbtn_change_end}, - {__hooks_battery_soc_change, __hooks_battery_soc_change_end}, + { __hooks_chipset_shutdown, __hooks_chipset_shutdown_end }, + { __hooks_chipset_shutdown_complete, + __hooks_chipset_shutdown_complete_end }, + { __hooks_chipset_hard_off, __hooks_chipset_hard_off_end }, + { __hooks_chipset_reset, __hooks_chipset_reset_end }, + { __hooks_ac_change, __hooks_ac_change_end }, + { __hooks_lid_change, __hooks_lid_change_end }, + { __hooks_tablet_mode_change, __hooks_tablet_mode_change_end }, + { __hooks_base_attached_change, __hooks_base_attached_change_end }, + { __hooks_pwrbtn_change, __hooks_pwrbtn_change_end }, + { __hooks_battery_soc_change, __hooks_battery_soc_change_end }, #ifdef CONFIG_USB_SUSPEND - {__hooks_usb_change, __hooks_usb_change_end}, + { __hooks_usb_change, __hooks_usb_change_end }, #endif - {__hooks_tick, __hooks_tick_end}, - {__hooks_second, __hooks_second_end}, - {__hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end}, - {__hooks_usb_pd_connect, __hooks_usb_pd_connect_end}, - {__hooks_power_supply_change, __hooks_power_supply_change_end}, + { __hooks_tick, __hooks_tick_end }, + { __hooks_second, __hooks_second_end }, + { __hooks_usb_pd_disconnect, __hooks_usb_pd_disconnect_end }, + { __hooks_usb_pd_connect, __hooks_usb_pd_connect_end }, + { __hooks_power_supply_change, __hooks_power_supply_change_end }, }; /* Times for deferrable functions */ @@ -150,7 +150,7 @@ int hook_call_deferred(const struct deferred_data *data, int us) int i = data - __deferred_funcs; if (data < __deferred_funcs || data >= __deferred_funcs_end) - return EC_ERROR_INVAL; /* Routine not registered */ + return EC_ERROR_INVAL; /* Routine not registered */ if (us == -1) { /* Cancel */ @@ -284,7 +284,5 @@ static int command_stats(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hookstats, command_stats, - NULL, - "Print stats of hooks"); +DECLARE_CONSOLE_COMMAND(hookstats, command_stats, NULL, "Print stats of hooks"); #endif -- cgit v1.2.1 From 6f3db01e5e2400f3ca3d2f24dc0562a0a296758b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:58 -0600 Subject: core/minute-ia/ia_structs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I33873c9eafa69085dfcc604842aaaf96d5d39240 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729850 Reviewed-by: Jeremy Bettis --- core/minute-ia/ia_structs.h | 70 ++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/core/minute-ia/ia_structs.h b/core/minute-ia/ia_structs.h index 29bbb6c005..14b65af1c3 100644 --- a/core/minute-ia/ia_structs.h +++ b/core/minute-ia/ia_structs.h @@ -10,7 +10,6 @@ #include "common.h" - /** * IA32/x86 architecture related data structure definitions. * including: Global Descriptor Table (GDT), Local Descriptor Table (LDT), @@ -24,16 +23,16 @@ struct gdt_entry { union { struct { - uint32_t dword_lo; /* lower dword */ - uint32_t dword_up; /* upper dword */ + uint32_t dword_lo; /* lower dword */ + uint32_t dword_up; /* upper dword */ }; struct { - uint16_t limit_lw; /* limit (0:15) */ - uint16_t base_addr_lw; /* base address (0:15) */ - uint8_t base_addr_mb; /* base address (16:23) */ - uint8_t flags; /* flags */ - uint8_t limit_ub; /* limit (16:19) */ - uint8_t base_addr_ub; /* base address (24:31) */ + uint16_t limit_lw; /* limit (0:15) */ + uint16_t base_addr_lw; /* base address (0:15) */ + uint8_t base_addr_mb; /* base address (16:23) */ + uint8_t flags; /* flags */ + uint8_t limit_ub; /* limit (16:19) */ + uint8_t base_addr_ub; /* base address (24:31) */ }; }; @@ -43,32 +42,32 @@ typedef struct gdt_entry ldt_entry; /* GDT header */ struct gdt_header { - uint16_t limit; /* GDT limit size */ - struct gdt_entry *entries; /* pointer to GDT entries */ + uint16_t limit; /* GDT limit size */ + struct gdt_entry *entries; /* pointer to GDT entries */ } __packed; /* IDT entry descriptor */ struct idt_entry { union { struct { - uint32_t dword_lo; /* lower dword */ - uint32_t dword_up; /* upper dword */ + uint32_t dword_lo; /* lower dword */ + uint32_t dword_up; /* upper dword */ }; struct { - uint16_t offset_lw; /* offset (0:15) */ - uint16_t seg_selector; /* segment selector */ - uint8_t zero; /* must be set to zero */ - uint8_t flags; /* flags */ - uint16_t offset_uw; /* offset (16:31) */ + uint16_t offset_lw; /* offset (0:15) */ + uint16_t seg_selector; /* segment selector */ + uint8_t zero; /* must be set to zero */ + uint8_t flags; /* flags */ + uint16_t offset_uw; /* offset (16:31) */ }; }; } __packed; /* IDT header */ struct idt_header { - uint16_t limit; /* IDT limit size */ - struct idt_entry *entries; /* pointer to IDT entries */ + uint16_t limit; /* IDT limit size */ + struct idt_entry *entries; /* pointer to IDT entries */ } __packed; /* TSS entry descriptor */ @@ -117,22 +116,22 @@ struct tss_entry { #endif /* code segment flag, E/R, Present = 1, DPL = 0, Acesssed = 1 */ -#define GDT_DESC_CODE_FLAGS (0x9B) +#define GDT_DESC_CODE_FLAGS (0x9B) /* data segment flag, R/W, Present = 1, DPL = 0, Acesssed = 1 */ -#define GDT_DESC_DATA_FLAGS (0x93) +#define GDT_DESC_DATA_FLAGS (0x93) /* TSS segment limit size */ -#define GDT_DESC_TSS_LIMIT (0x67) +#define GDT_DESC_TSS_LIMIT (0x67) /* TSS segment flag, Present = 1, DPL = 0, Acesssed = 1 */ -#define GDT_DESC_TSS_FLAGS (0x89) +#define GDT_DESC_TSS_FLAGS (0x89) /* LDT segment flag, Present = 1, DPL = 0 */ -#define GDT_DESC_LDT_FLAGS (0x82) +#define GDT_DESC_LDT_FLAGS (0x82) /* IDT descriptor flag, Present = 1, DPL = 0, 32-bit interrupt gate */ -#define IDT_DESC_FLAGS (0x8E) +#define IDT_DESC_FLAGS (0x8E) /** * macros helper to create a GDT entry descriptor @@ -141,21 +140,20 @@ struct tss_entry { * limit: 32bit limit size of bytes (will covert to unit of 4096-byte pages) * flags: 8bit flags */ -#define GEN_GDT_DESC_LO(base, limit, flags) \ - ((((limit) >> 12) & 0xFFFF) | (((base) & 0xFFFF) << 16)) - -#define GEN_GDT_DESC_UP(base, limit, flags) \ - ((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \ - (((limit) >> 12) & 0xFF0000) | ((base) & 0xFF000000) | 0xc00000) +#define GEN_GDT_DESC_LO(base, limit, flags) \ + ((((limit) >> 12) & 0xFFFF) | (((base)&0xFFFF) << 16)) +#define GEN_GDT_DESC_UP(base, limit, flags) \ + ((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \ + (((limit) >> 12) & 0xFF0000) | ((base)&0xFF000000) | 0xc00000) /** * macro helper to create a IDT entry descriptor */ -#define GEN_IDT_DESC_LO(offset, selector, flags) \ - (((uint32_t)(offset) & 0xFFFF) | (((selector) & 0xFFFF) << 16)) +#define GEN_IDT_DESC_LO(offset, selector, flags) \ + (((uint32_t)(offset)&0xFFFF) | (((selector)&0xFFFF) << 16)) -#define GEN_IDT_DESC_UP(offset, selector, flags) \ - (((uint32_t)(offset) & 0xFFFF0000) | (((flags) & 0xFF) << 8)) +#define GEN_IDT_DESC_UP(offset, selector, flags) \ + (((uint32_t)(offset)&0xFFFF0000) | (((flags)&0xFF) << 8)) #endif /* __CROS_EC_IA_STRUCTS_H */ -- cgit v1.2.1 From 180d440fd83d676493bced461f2429061453e803 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:08 -0600 Subject: board/nocturne/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7f91f172e119235c0dd3673be9f08eaf59844486 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728759 Reviewed-by: Jeremy Bettis --- board/nocturne/board.h | 97 ++++++++++++++++++++++++-------------------------- 1 file changed, 46 insertions(+), 51 deletions(-) diff --git a/board/nocturne/board.h b/board/nocturne/board.h index 2a21392313..5975053622 100644 --- a/board/nocturne/board.h +++ b/board/nocturne/board.h @@ -12,14 +12,14 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX7 config */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ -#define NPCX_TACH_SEL2 0 /* No tach. */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ #define CONFIG_HIBERNATE_PSL /* Internal SPI flash on NPCX7 */ @@ -56,7 +56,7 @@ #define CONFIG_BATTERY_SMART #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 /* Buttons / Switches */ #define CONFIG_BASE_ATTACHED_SWITCH @@ -85,7 +85,7 @@ /* MKBP */ #define CONFIG_MKBP_EVENT -#define CONFIG_MKBP_EVENT_WAKEUP_MASK (1< Date: Mon, 27 Jun 2022 15:41:14 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b01efd7a7ec21f0b3c226372b0ca860553c9b2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730942 Reviewed-by: Jeremy Bettis --- .../src/integration/usbc/usb_malfunction_sink.c | 56 +++++++++++----------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c index 7c46abc34f..275817164f 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c @@ -26,8 +26,7 @@ struct usb_malfunction_sink_fixture { struct tcpci_faulty_snk_action actions[2]; }; -static void -connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture) +static void connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture) { /* * TODO(b/221439302) Updating the TCPCI emulator registers, updating the @@ -56,8 +55,8 @@ connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture) k_sleep(K_SECONDS(10)); } -static inline void disconnect_sink_from_port( - struct usb_malfunction_sink_fixture *fixture) +static inline void +disconnect_sink_from_port(struct usb_malfunction_sink_fixture *fixture) { zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); k_sleep(K_SECONDS(1)); @@ -73,16 +72,14 @@ static void *usb_malfunction_sink_setup(void) test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - tcpc_config[0].flags = tcpc_config[0].flags | - TCPC_FLAGS_TCPCI_REV2_0; + tcpc_config[0].flags = tcpc_config[0].flags | TCPC_FLAGS_TCPCI_REV2_0; /* Initialized the sink to request 5V and 3A */ tcpci_partner_init(&test_fixture.sink, PD_REV20); - test_fixture.sink.extensions = - tcpci_faulty_snk_emul_init( - &test_fixture.faulty_snk_ext, &test_fixture.sink, - tcpci_snk_emul_init(&test_fixture.snk_ext, - &test_fixture.sink, NULL)); + test_fixture.sink.extensions = tcpci_faulty_snk_emul_init( + &test_fixture.faulty_snk_ext, &test_fixture.sink, + tcpci_snk_emul_init(&test_fixture.snk_ext, &test_fixture.sink, + NULL)); test_fixture.snk_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); @@ -96,7 +93,6 @@ static void usb_malfunction_sink_before(void *data) /* TODO(b/214401892): Check why need to give time TCPM to spin */ k_sleep(K_SECONDS(1)); - } static void usb_malfunction_sink_after(void *data) @@ -109,8 +105,7 @@ static void usb_malfunction_sink_after(void *data) } ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main, - usb_malfunction_sink_setup, - usb_malfunction_sink_before, + usb_malfunction_sink_setup, usb_malfunction_sink_before, usb_malfunction_sink_after, NULL); ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable) @@ -177,11 +172,11 @@ ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect) "Current max expected to be 1500mV, but was %dmV", info.meas.current_max); zassert_equal(info.meas.current_lim, 0, - "VBUS max is set to 0mA, but PD is reporting %dmA", - info.meas.current_lim); + "VBUS max is set to 0mA, but PD is reporting %dmA", + info.meas.current_lim); zassert_equal(info.max_power, 0, - "Charging expected to be at %duW, but PD max is %duW", - 0, info.max_power); + "Charging expected to be at %duW, but PD max is %duW", 0, + info.max_power); } ZTEST_F(usb_malfunction_sink, test_ignore_source_cap) @@ -207,23 +202,26 @@ ZTEST_F(usb_malfunction_sink, test_ignore_source_cap) */ /* Check if SourceCapability message alternate with HardReset */ - SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node) { + SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node) + { if (expect_hard_reset) { zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET, "Expected message %d to be hard reset", msg_cnt); } else { header = sys_get_le16(msg->buf); - zassert_equal(msg->sop, TCPCI_MSG_SOP, - "Expected message %d to be SOP message, not 0x%x", - msg_cnt, msg->sop); - zassert_not_equal(PD_HEADER_CNT(header), 0, - "Expected message %d to has at least one data object", - msg_cnt); - zassert_equal(PD_HEADER_TYPE(header), - PD_DATA_SOURCE_CAP, - "Expected message %d to be SourceCapabilities, not 0x%x", - msg_cnt, PD_HEADER_TYPE(header)); + zassert_equal( + msg->sop, TCPCI_MSG_SOP, + "Expected message %d to be SOP message, not 0x%x", + msg_cnt, msg->sop); + zassert_not_equal( + PD_HEADER_CNT(header), 0, + "Expected message %d to has at least one data object", + msg_cnt); + zassert_equal( + PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, + "Expected message %d to be SourceCapabilities, not 0x%x", + msg_cnt, PD_HEADER_TYPE(header)); } msg_cnt++; -- cgit v1.2.1 From 2773798bc9650c894a839b9165c35802fa7740dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:17 -0600 Subject: board/palkia/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97cdd041f68c36a13c3727512578342aebe91e21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728807 Reviewed-by: Jeremy Bettis --- board/palkia/board.h | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/board/palkia/board.h b/board/palkia/board.h index 783f01c444..e7aeea49b9 100644 --- a/board/palkia/board.h +++ b/board/palkia/board.h @@ -46,7 +46,7 @@ * Palkia' battery takes several seconds to come back out of its disconnect * state (~4.2 seconds on the unit I have, so give it a little more for margin). */ -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6 /* BC 1.2 */ @@ -70,16 +70,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -87,18 +87,14 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC3 */ - ADC_TEMP_SENSOR_4, /* ADC2 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC3 */ + ADC_TEMP_SENSOR_4, /* ADC2 */ ADC_CH_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From d2c9f8e25ee78e5e8c5879ce1e7cb60a9d4d238b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:13 -0600 Subject: driver/tcpm/raa489000.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia5474e1ebbc042d39b137ddeba930f7044e1dd73 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730083 Reviewed-by: Jeremy Bettis --- driver/tcpm/raa489000.c | 94 ++++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 48 deletions(-) diff --git a/driver/tcpm/raa489000.c b/driver/tcpm/raa489000.c index db169f19f1..92c228a840 100644 --- a/driver/tcpm/raa489000.c +++ b/driver/tcpm/raa489000.c @@ -18,10 +18,10 @@ #define DEFAULT_R_AC 20 #define R_AC CONFIG_CHARGER_SENSE_RESISTOR_AC -#define AC_CURRENT_TO_REG(CUR) ((CUR) * R_AC / DEFAULT_R_AC) +#define AC_CURRENT_TO_REG(CUR) ((CUR)*R_AC / DEFAULT_R_AC) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static int dev_id[CONFIG_USB_PD_PORT_MAX_COUNT] = { -1 }; @@ -47,14 +47,13 @@ int raa489000_set_output_current(int port, enum tcpc_rp_value rp) { int regval; int selected_cur = rp == TYPEC_RP_3A0 ? - RAA489000_VBUS_CURRENT_TARGET_3A : - RAA489000_VBUS_CURRENT_TARGET_1_5A; + RAA489000_VBUS_CURRENT_TARGET_3A : + RAA489000_VBUS_CURRENT_TARGET_1_5A; regval = AC_CURRENT_TO_REG(selected_cur) + - selected_cur % (DEFAULT_R_AC/R_AC); + selected_cur % (DEFAULT_R_AC / R_AC); - return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET, - regval); + return tcpc_write16(port, RAA489000_VBUS_CURRENT_TARGET, regval); } int raa489000_init(int port) @@ -94,11 +93,11 @@ int raa489000_init(int port) * can get the correct voltage. */ i2c_port = tcpc_config[port].i2c_info.port; - rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS, - ISL9238_REG_CONTROL3, ®val); + rv = i2c_read16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3, + ®val); regval |= RAA489000_ENABLE_ADC; - rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, - ISL9238_REG_CONTROL3, regval); + rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, ISL9238_REG_CONTROL3, + regval); if (rv) CPRINTS("c%d: failed to enable ADCs", port); @@ -108,7 +107,6 @@ int raa489000_init(int port) if (rv) CPRINTS("c%d: failed to enable vbus detect cmd", port); - /* * If VBUS is present, start sinking from it if we haven't already * chosen a charge port and no battery is connected. This is @@ -131,7 +129,7 @@ int raa489000_init(int port) ISL9238_REG_CONTROL3, ®val); regval &= ~RAA489000_ENABLE_ADC; rv |= i2c_write16(i2c_port, ISL923X_ADDR_FLAGS, - ISL9238_REG_CONTROL3, regval); + ISL9238_REG_CONTROL3, regval); if (rv) CPRINTS("c%d: failed to disable ADCs", port); } @@ -172,14 +170,14 @@ int raa489000_init(int port) */ if (device_id <= 1) { rv = tcpc_write16(port, RAA489000_TYPEC_SETTING1, - RAA489000_SETTING1_RDOE | - RAA489000_SETTING1_CC2_CMP3_EN | - RAA489000_SETTING1_CC2_CMP2_EN | - RAA489000_SETTING1_CC2_CMP1_EN | - RAA489000_SETTING1_CC1_CMP3_EN | - RAA489000_SETTING1_CC1_CMP2_EN | - RAA489000_SETTING1_CC1_CMP1_EN | - RAA489000_SETTING1_CC_DB_EN); + RAA489000_SETTING1_RDOE | + RAA489000_SETTING1_CC2_CMP3_EN | + RAA489000_SETTING1_CC2_CMP2_EN | + RAA489000_SETTING1_CC2_CMP1_EN | + RAA489000_SETTING1_CC1_CMP3_EN | + RAA489000_SETTING1_CC1_CMP2_EN | + RAA489000_SETTING1_CC1_CMP1_EN | + RAA489000_SETTING1_CC_DB_EN); if (rv) CPRINTS("c%d: failed to enable CC comparators", port); } @@ -187,8 +185,8 @@ int raa489000_init(int port) /* Set Rx enable for receiver comparator */ rv = tcpc_read16(port, RAA489000_PD_PHYSICAL_SETTING1, ®val); regval |= RAA489000_PD_PHY_SETTING1_RECEIVER_EN | - RAA489000_PD_PHY_SETTING1_SQUELCH_EN | - RAA489000_PD_PHY_SETTING1_TX_LDO11_EN; + RAA489000_PD_PHY_SETTING1_SQUELCH_EN | + RAA489000_PD_PHY_SETTING1_TX_LDO11_EN; rv |= tcpc_write16(port, RAA489000_PD_PHYSICAL_SETTING1, regval); if (rv) CPRINTS("c%d: failed to set PD PHY setting1", port); @@ -231,13 +229,13 @@ int raa489000_init(int port) * Set Vbus OCP UV here, PD tasks will set target current */ rv = tcpc_write16(port, RAA489000_VBUS_OCP_UV_THRESHOLD, - RAA489000_OCP_THRESHOLD_VALUE); + RAA489000_OCP_THRESHOLD_VALUE); if (rv) CPRINTS("c%d: failed to set OCP threshold", port); /* Set Vbus Target Voltage */ rv = tcpc_write16(port, RAA489000_VBUS_VOLTAGE_TARGET, - RAA489000_VBUS_VOLTAGE_TARGET_5160MV); + RAA489000_VBUS_VOLTAGE_TARGET_5160MV); if (rv) CPRINTS("c%d: failed to set Vbus Target Voltage", port); @@ -278,7 +276,7 @@ int raa489000_debug_detach(int port) RETURN_ERROR(tcpc_read(port, TCPC_REG_POWER_STATUS, &power_status)); if (!pd_is_battery_capable() && - (power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS)) + (power_status & TCPC_REG_POWER_STATUS_SINKING_VBUS)) return EC_SUCCESS; tcpci_tcpc_enable_auto_discharge_disconnect(port, 1); @@ -292,37 +290,37 @@ int raa489000_debug_detach(int port) /* RAA489000 is a TCPCI compatible port controller */ const struct tcpm_drv raa489000_tcpm_drv = { - .init = &raa489000_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &raa489000_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &raa489000_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &raa489000_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tcpci_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, + .get_chip_info = &tcpci_get_chip_info, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &raa489000_enter_low_power_mode, - .wake_low_power_mode = &tcpci_wake_low_power_mode, + .enter_low_power_mode = &raa489000_enter_low_power_mode, + .wake_low_power_mode = &tcpci_wake_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, .tcpc_enable_auto_discharge_disconnect = &tcpci_tcpc_enable_auto_discharge_disconnect, - .debug_detach = &raa489000_debug_detach, + .debug_detach = &raa489000_debug_detach, }; -- cgit v1.2.1 From 7d89813c3da82651f055e7665999a962a4b20ccd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:39 -0600 Subject: baseboard/honeybuns/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icd49188dc3f45848603f55b2d756d92d49bf9563 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727888 Reviewed-by: Jeremy Bettis --- baseboard/honeybuns/baseboard.c | 57 +++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 33 deletions(-) diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c index e7df1b6ef4..58d07168c8 100644 --- a/baseboard/honeybuns/baseboard.c +++ b/baseboard/honeybuns/baseboard.c @@ -18,20 +18,17 @@ #include "driver/tcpm/tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define POWER_BUTTON_SHORT_USEC (300 * MSEC) #define POWER_BUTTON_LONG_USEC (5000 * MSEC) #define POWER_BUTTON_DEBOUNCE_USEC (30) -#define BUTTON_EVT_CHANGE BIT(0) -#define BUTTON_EVT_INFO BIT(1) +#define BUTTON_EVT_CHANGE BIT(0) +#define BUTTON_EVT_INFO BIT(1) -enum power { - POWER_OFF, - POWER_ON -}; +enum power { POWER_OFF, POWER_ON }; enum button { BUTTON_RELEASE, @@ -66,7 +63,7 @@ __maybe_unused static void board_power_sequence(int enable) int i; if (enable) { - for(i = 0; i < board_power_seq_count; i++) { + for (i = 0; i < board_power_seq_count; i++) { gpio_set_level(board_power_seq[i].signal, board_power_seq[i].level); CPRINTS("power seq: rail = %d", i); @@ -74,7 +71,7 @@ __maybe_unused static void board_power_sequence(int enable) msleep(board_power_seq[i].delay_ms); } } else { - for(i = board_power_seq_count - 1; i >= 0; i--) { + for (i = board_power_seq_count - 1; i >= 0; i--) { gpio_set_level(board_power_seq[i].signal, !board_power_seq[i].level); CPRINTS("sequence[%d]: level = %d", i, @@ -89,20 +86,16 @@ __maybe_unused static void board_power_sequence(int enable) /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "i2c1", - .port = I2C_PORT_I2C1, - .kbps = 400, - .scl = GPIO_EC_I2C1_SCL, - .sda = GPIO_EC_I2C1_SDA - }, - { - .name = "i2c3", - .port = I2C_PORT_I2C3, - .kbps = 400, - .scl = GPIO_EC_I2C3_SCL, - .sda = GPIO_EC_I2C3_SDA - }, + { .name = "i2c1", + .port = I2C_PORT_I2C1, + .kbps = 400, + .scl = GPIO_EC_I2C1_SCL, + .sda = GPIO_EC_I2C1_SDA }, + { .name = "i2c3", + .port = I2C_PORT_I2C3, + .kbps = 400, + .scl = GPIO_EC_I2C3_SCL, + .sda = GPIO_EC_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -246,7 +239,7 @@ static void baseboard_init(void) #else /* Set up host port usbc to present Rd on CC lines */ - if(baseboard_usbc_init(USB_PD_PORT_HOST)) + if (baseboard_usbc_init(USB_PD_PORT_HOST)) CPRINTS("usbc: Failed to set up sink path"); else CPRINTS("usbc: sink path configure success!"); @@ -381,11 +374,11 @@ void power_button_task(void *u) * Default wait state: Only need to check if the button * is pressed and start the short press timer. */ - if (evt & BUTTON_EVT_CHANGE && button_level == - BUTTON_PRESSED_LEVEL) { + if (evt & BUTTON_EVT_CHANGE && + button_level == BUTTON_PRESSED_LEVEL) { state = BUTTON_PRESS; timer_us = (POWER_BUTTON_SHORT_USEC - - POWER_BUTTON_DEBOUNCE_USEC); + POWER_BUTTON_DEBOUNCE_USEC); } break; case BUTTON_PRESS: @@ -399,7 +392,7 @@ void power_button_task(void *u) } else { /* Start long press timer */ timer_us = POWER_BUTTON_LONG_USEC - - POWER_BUTTON_SHORT_USEC; + POWER_BUTTON_SHORT_USEC; /* * If dock is currently off, then change to the * power on state. If dock is already on, then @@ -407,7 +400,7 @@ void power_button_task(void *u) */ if (dock_state == POWER_OFF) { baseboard_power_on(); - state = BUTTON_PRESS_POWER_ON; + state = BUTTON_PRESS_POWER_ON; } else { state = BUTTON_PRESS_SHORT; } @@ -476,7 +469,6 @@ void baseboard_power_button_evt(int level) static int command_pwr_btn(int argc, char **argv) { - if (argc == 1) { task_set_event(TASK_ID_POWER_BUTTON, BUTTON_EVT_INFO); return EC_SUCCESS; @@ -494,8 +486,7 @@ static int command_pwr_btn(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, - "", +DECLARE_CONSOLE_COMMAND(pwr_btn, command_pwr_btn, "", "Simulate Power Button Press"); #endif -- cgit v1.2.1 From dff1026222b16383301e2c963abb8c2fb6081f06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:45 -0600 Subject: core/riscv-rv32i/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59efbf82a107052607f7cdeb4766c268fd079f74 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729869 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/riscv-rv32i/cpu.h b/core/riscv-rv32i/cpu.h index e46b893ad6..7bc5c81b04 100644 --- a/core/riscv-rv32i/cpu.h +++ b/core/riscv-rv32i/cpu.h @@ -25,7 +25,7 @@ /* write Exception Program Counter register */ static inline void set_mepc(uint32_t val) { - asm volatile ("csrw mepc, %0" : : "r"(val)); + asm volatile("csrw mepc, %0" : : "r"(val)); } /* read Exception Program Counter register */ @@ -33,7 +33,7 @@ static inline uint32_t get_mepc(void) { uint32_t ret; - asm volatile ("csrr %0, mepc" : "=r"(ret)); + asm volatile("csrr %0, mepc" : "=r"(ret)); return ret; } @@ -42,7 +42,7 @@ static inline uint32_t get_mcause(void) { uint32_t ret; - asm volatile ("csrr %0, mcause" : "=r"(ret)); + asm volatile("csrr %0, mcause" : "=r"(ret)); return ret; } -- cgit v1.2.1 From 9670cc1daf7e459fdd4f656a8743ac44110bd525 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:21 -0600 Subject: zephyr/shim/chip/mchp/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie30c855be2bd68883b6a6943c429063d4c9846a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730818 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/system.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c index 25fdfc9897..09ddefd6ee 100644 --- a/zephyr/shim/chip/mchp/system.c +++ b/zephyr/shim/chip/mchp/system.c @@ -11,8 +11,7 @@ LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR); -#define GET_BBRAM_OFS(node) \ - DT_PROP(DT_PATH(named_bbram_regions, node), offset) +#define GET_BBRAM_OFS(node) DT_PROP(DT_PATH(named_bbram_regions, node), offset) #define GET_BBRAM_SZ(node) DT_PROP(DT_PATH(named_bbram_regions, node), size) /* -- cgit v1.2.1 From a7644695acb61ccc2dfc4bac39ae0ad7bb7e7d41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:54 -0600 Subject: zephyr/test/drivers/src/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia61f96946df595f622db1447a918390b37710444 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730988 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/espi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/zephyr/test/drivers/src/espi.c b/zephyr/test/drivers/src/espi.c index 67fc3c6f90..1b7c1d9b70 100644 --- a/zephyr/test/drivers/src/espi.c +++ b/zephyr/test/drivers/src/espi.c @@ -10,15 +10,13 @@ #include "host_command.h" #include "test/drivers/test_state.h" - #define PORT 0 ZTEST_USER(espi, test_host_command_get_protocol_info) { struct ec_response_get_protocol_info response; - struct host_cmd_handler_args args = - BUILD_HOST_COMMAND_RESPONSE(EC_CMD_GET_PROTOCOL_INFO, 0, - response); + struct host_cmd_handler_args args = BUILD_HOST_COMMAND_RESPONSE( + EC_CMD_GET_PROTOCOL_INFO, 0, response); zassert_ok(host_command_process(&args), NULL); zassert_ok(args.result, NULL); -- cgit v1.2.1 From 0198e21a99149b14d9962fbdba78ecf7a8b65e94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:52 -0600 Subject: board/galtic/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icc5c6b5ddfeb2ef12f7db75279733ff1a6ded4d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728387 Reviewed-by: Jeremy Bettis --- board/galtic/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/galtic/led.c b/board/galtic/led.c index ecd40dc973..e65536e4bd 100644 --- a/board/galtic/led.c +++ b/board/galtic/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {LED_OFF, 2 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { LED_OFF, 2 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 5feb1e1c621134aad1ae084aecc25862896fe0e2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:22 -0600 Subject: board/palkia/keyboard_customization.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6320b6423436c48b9bfff19f2955226a2b1b8e9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728809 Reviewed-by: Jeremy Bettis --- board/palkia/keyboard_customization.h | 74 +++++++++++++++++------------------ 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/board/palkia/keyboard_customization.h b/board/palkia/keyboard_customization.h index 37ce1cf61f..a21190028c 100644 --- a/board/palkia/keyboard_customization.h +++ b/board/palkia/keyboard_customization.h @@ -25,47 +25,47 @@ extern uint8_t keyboard_cols; #define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) /* Columns and masks for keys we particularly care about */ -#define KEYBOARD_COL_DOWN 8 -#define KEYBOARD_ROW_DOWN 1 -#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) -#define KEYBOARD_COL_ESC 5 -#define KEYBOARD_ROW_ESC 7 -#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) -#define KEYBOARD_COL_KEY_H 7 -#define KEYBOARD_ROW_KEY_H 2 -#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) -#define KEYBOARD_COL_KEY_R 6 -#define KEYBOARD_ROW_KEY_R 6 -#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) -#define KEYBOARD_COL_LEFT_ALT 3 -#define KEYBOARD_ROW_LEFT_ALT 1 -#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) -#define KEYBOARD_COL_REFRESH 4 -#define KEYBOARD_ROW_REFRESH 6 -#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) -#define KEYBOARD_COL_RIGHT_ALT 3 -#define KEYBOARD_ROW_RIGHT_ALT 0 -#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) -#define KEYBOARD_DEFAULT_COL_VOL_UP 8 -#define KEYBOARD_DEFAULT_ROW_VOL_UP 4 -#define KEYBOARD_COL_LEFT_CTRL 12 -#define KEYBOARD_ROW_LEFT_CTRL 1 +#define KEYBOARD_COL_DOWN 8 +#define KEYBOARD_ROW_DOWN 1 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 5 +#define KEYBOARD_ROW_ESC 7 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 7 +#define KEYBOARD_ROW_KEY_H 2 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 6 +#define KEYBOARD_ROW_KEY_R 6 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 3 +#define KEYBOARD_ROW_LEFT_ALT 1 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 4 +#define KEYBOARD_ROW_REFRESH 6 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 3 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 8 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 4 +#define KEYBOARD_COL_LEFT_CTRL 12 +#define KEYBOARD_ROW_LEFT_CTRL 1 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) #define KEYBOARD_COL_RIGHT_CTRL 12 #define KEYBOARD_ROW_RIGHT_CTRL 0 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) -#define KEYBOARD_COL_SEARCH 2 -#define KEYBOARD_ROW_SEARCH 3 -#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) -#define KEYBOARD_COL_KEY_0 13 -#define KEYBOARD_ROW_KEY_0 4 -#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) -#define KEYBOARD_COL_KEY_1 2 -#define KEYBOARD_ROW_KEY_1 5 -#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) -#define KEYBOARD_COL_KEY_2 5 -#define KEYBOARD_ROW_KEY_2 5 -#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_SEARCH 2 +#define KEYBOARD_ROW_SEARCH 3 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 13 +#define KEYBOARD_ROW_KEY_0 4 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 2 +#define KEYBOARD_ROW_KEY_1 5 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 5 +#define KEYBOARD_ROW_KEY_2 5 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) #define KEYBOARD_COL_LEFT_SHIFT 9 #define KEYBOARD_ROW_LEFT_SHIFT 1 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) -- cgit v1.2.1 From 811485f61db05d0fea114e38819bbee65da5bdc6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:26 -0600 Subject: zephyr/test/drivers/src/ln9310.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb8f2129521b71f8e10de7a07acc32f03cbd1047 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730975 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/ln9310.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/zephyr/test/drivers/src/ln9310.c b/zephyr/test/drivers/src/ln9310.c index e4bf37c4bd..e83e2df0a5 100644 --- a/zephyr/test/drivers/src/ln9310.c +++ b/zephyr/test/drivers/src/ln9310.c @@ -366,7 +366,6 @@ ZTEST(ln9310, test_ln9310_lion_ctrl_reg_fails) I2C_COMMON_EMUL_NO_FAIL_REG); } - struct precharge_timeout_data { timestamp_t time_to_mock; bool handled_clearing_standby_en_bit_timeout; @@ -481,8 +480,8 @@ ZTEST(ln9310, test_ln9310_interrupt_reg_fail) zassert_ok(ln9310_init(), NULL); zassert_true(ln9310_emul_is_init(emulator), NULL); - i2c_common_emul_set_read_func( - i2c_emul, mock_read_intercept_reg_to_fail, &test_data); + i2c_common_emul_set_read_func(i2c_emul, mock_read_intercept_reg_to_fail, + &test_data); /* Fail in beginning of software enable */ test_data.reg_access_to_fail = LN9310_REG_INT1; -- cgit v1.2.1 From a3513991b88ea85265abea67b8ba0a6cc08d043a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:08 -0600 Subject: cts/common/cts_testlist.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15510c38f0d4b4adcf5438e98343de03563dc9a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729757 Reviewed-by: Jeremy Bettis --- cts/common/cts_testlist.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cts/common/cts_testlist.h b/cts/common/cts_testlist.h index 1586c1348e..43a48f19e5 100644 --- a/cts/common/cts_testlist.h +++ b/cts/common/cts_testlist.h @@ -22,7 +22,7 @@ #undef CTS_TEST #define CTS_TEST(test, th_rc, th_string, dut_rc, dut_string) \ - {test, STRINGIFY(test)}, + { test, STRINGIFY(test) }, struct cts_test tests[] = { #include "cts.testlist" }; -- cgit v1.2.1 From 285df5930f4332ebeb182dfc8ab8c962bbfb0634 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:52 -0600 Subject: include/mock/tcpci_i2c_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09cdf5f2a23a472b4e1a50e7e4026e51c96516b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730362 Reviewed-by: Jeremy Bettis --- include/mock/tcpci_i2c_mock.h | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/include/mock/tcpci_i2c_mock.h b/include/mock/tcpci_i2c_mock.h index 1d4a986ebe..85f90c19b0 100644 --- a/include/mock/tcpci_i2c_mock.h +++ b/include/mock/tcpci_i2c_mock.h @@ -28,15 +28,11 @@ int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type, int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout); + enum pd_data_msg_type data_msg, int timeout); int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type, - enum pd_data_msg_type data_msg, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout); + enum pd_data_msg_type data_msg, uint8_t *data, + int data_bytes, int *msg_len, int timeout); struct possible_tx { enum tcpci_msg_type tx_type; @@ -44,13 +40,9 @@ struct possible_tx { enum pd_data_msg_type data_msg; }; -int verify_tcpci_possible_tx(struct possible_tx possible[], - int possible_cnt, - int *found_index, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout); +int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt, + int *found_index, uint8_t *data, int data_bytes, + int *msg_len, int timeout); void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header, uint32_t *payload); -- cgit v1.2.1 From 4270f6ae6e9aeb65e3930e2c5d0dcd3b1a8a21fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:58 -0600 Subject: driver/retimer/tusb544.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40d01a40c796fe2fc8cd84a634938c6f7a269a2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730061 Reviewed-by: Jeremy Bettis --- driver/retimer/tusb544.h | 113 +++++++++++++++++++++++------------------------ 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/driver/retimer/tusb544.h b/driver/retimer/tusb544.h index e1599c78ca..2a5f50f051 100644 --- a/driver/retimer/tusb544.h +++ b/driver/retimer/tusb544.h @@ -9,55 +9,54 @@ #ifndef __CROS_EC_USB_REDRIVER_TUSB544_H #define __CROS_EC_USB_REDRIVER_TUSB544_H - #define TUSB544_I2C_ADDR_FLAGS0 0x44 -#define TUSB544_REG_GENERAL4 0x0A -#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0) -#define TUSB544_GEN4_FLIP_SEL BIT(2) -#define TUSB544_GEN4_HPDIN BIT(3) -#define TUSB544_GEN4_EQ_OVRD BIT(4) -#define TUSB544_GEN4_SWAP_SEL BIT(5) +#define TUSB544_REG_GENERAL4 0x0A +#define TUSB544_GEN4_CTL_SEL GENMASK(1, 0) +#define TUSB544_GEN4_FLIP_SEL BIT(2) +#define TUSB544_GEN4_HPDIN BIT(3) +#define TUSB544_GEN4_EQ_OVRD BIT(4) +#define TUSB544_GEN4_SWAP_SEL BIT(5) -#define TUSB544_REG_DISPLAYPORT_1 0x10 -#define TUSB544_REG_DISPLAYPORT_2 0x11 -#define TUSB544_REG_USB3_1_1 0x20 -#define TUSB544_REG_USB3_1_2 0x21 -#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0) -#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1) -#define TUSB544_EQ_RX_DFP_17_UFP_0 (2) -#define TUSB544_EQ_RX_DFP_32_UFP_14 (3) -#define TUSB544_EQ_RX_DFP_41_UFP_24 (4) -#define TUSB544_EQ_RX_DFP_52_UFP_35 (5) -#define TUSB544_EQ_RX_DFP_61_UFP_43 (6) -#define TUSB544_EQ_RX_DFP_69_UFP_52 (7) -#define TUSB544_EQ_RX_DFP_77_UFP_60 (8) -#define TUSB544_EQ_RX_DFP_83_UFP_66 (9) -#define TUSB544_EQ_RX_DFP_88_UFP_72 (10) -#define TUSB544_EQ_RX_DFP_94_UFP_77 (11) -#define TUSB544_EQ_RX_DFP_98_UFP_81 (12) -#define TUSB544_EQ_RX_DFP_103_UFP_86 (13) -#define TUSB544_EQ_RX_DFP_106_UFP_90 (14) -#define TUSB544_EQ_RX_DFP_110_UFP_94 (15) -#define TUSB544_EQ_RX_MASK (0x0F) +#define TUSB544_REG_DISPLAYPORT_1 0x10 +#define TUSB544_REG_DISPLAYPORT_2 0x11 +#define TUSB544_REG_USB3_1_1 0x20 +#define TUSB544_REG_USB3_1_2 0x21 +#define TUSB544_EQ_RX_DFP_MINUS14_UFP_MINUS33 (0) +#define TUSB544_EQ_RX_DFP_04_UFP_MINUS15 (1) +#define TUSB544_EQ_RX_DFP_17_UFP_0 (2) +#define TUSB544_EQ_RX_DFP_32_UFP_14 (3) +#define TUSB544_EQ_RX_DFP_41_UFP_24 (4) +#define TUSB544_EQ_RX_DFP_52_UFP_35 (5) +#define TUSB544_EQ_RX_DFP_61_UFP_43 (6) +#define TUSB544_EQ_RX_DFP_69_UFP_52 (7) +#define TUSB544_EQ_RX_DFP_77_UFP_60 (8) +#define TUSB544_EQ_RX_DFP_83_UFP_66 (9) +#define TUSB544_EQ_RX_DFP_88_UFP_72 (10) +#define TUSB544_EQ_RX_DFP_94_UFP_77 (11) +#define TUSB544_EQ_RX_DFP_98_UFP_81 (12) +#define TUSB544_EQ_RX_DFP_103_UFP_86 (13) +#define TUSB544_EQ_RX_DFP_106_UFP_90 (14) +#define TUSB544_EQ_RX_DFP_110_UFP_94 (15) +#define TUSB544_EQ_RX_MASK (0x0F) -#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4) -#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4) -#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4) -#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4) -#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4) -#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4) -#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4) -#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4) -#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4) -#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4) -#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4) -#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4) -#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4) -#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4) -#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4) -#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4) -#define TUSB544_EQ_TX_MASK (0xF0) +#define TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33 (0 << 4) +#define TUSB544_EQ_TX_DFP_04_UFP_MINUS15 (1 << 4) +#define TUSB544_EQ_TX_DFP_17_UFP_0 (2 << 4) +#define TUSB544_EQ_TX_DFP_32_UFP_14 (3 << 4) +#define TUSB544_EQ_TX_DFP_41_UFP_24 (4 << 4) +#define TUSB544_EQ_TX_DFP_52_UFP_35 (5 << 4) +#define TUSB544_EQ_TX_DFP_61_UFP_43 (6 << 4) +#define TUSB544_EQ_TX_DFP_69_UFP_52 (7 << 4) +#define TUSB544_EQ_TX_DFP_77_UFP_60 (8 << 4) +#define TUSB544_EQ_TX_DFP_83_UFP_66 (9 << 4) +#define TUSB544_EQ_TX_DFP_88_UFP_72 (10 << 4) +#define TUSB544_EQ_TX_DFP_94_UFP_77 (11 << 4) +#define TUSB544_EQ_TX_DFP_98_UFP_81 (12 << 4) +#define TUSB544_EQ_TX_DFP_103_UFP_86 (13 << 4) +#define TUSB544_EQ_TX_DFP_106_UFP_90 (14 << 4) +#define TUSB544_EQ_TX_DFP_110_UFP_94 (15 << 4) +#define TUSB544_EQ_TX_MASK (0xF0) enum tusb544_ct_sel { TUSB544_CTL_SEL_DISABLED, @@ -66,10 +65,10 @@ enum tusb544_ct_sel { TUSB544_CTL_SEL_DP_USB, }; -#define TUSB544_REG_GENERAL6 0x0C -#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0) -#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2) -#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6) +#define TUSB544_REG_GENERAL6 0x0C +#define TUSB544_GEN6_DIR_SEL GENMASK(1, 0) +#define TUSB544_VOD_DCGAIN_SEL GENMASK(5, 2) +#define TUSB544_VOD_DCGAIN_OVERRIDE BIT(6) enum tusb544_dir_sel { TUSB544_DIR_SEL_USB_DP_SRC, @@ -93,17 +92,17 @@ enum tusb544_vod_dcgain_sel { * Note: TUSB544 automatically snoops DP lanes to enable, but may be manually * directed which lanes to turn on when snoop is disabled */ -#define TUSB544_REG_DP4 0x13 -#define TUSB544_DP4_DP0_DISABLE BIT(0) -#define TUSB544_DP4_DP1_DISABLE BIT(1) -#define TUSB544_DP4_DP2_DISABLE BIT(2) -#define TUSB544_DP4_DP3_DISABLE BIT(3) -#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4) -#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7) +#define TUSB544_REG_DP4 0x13 +#define TUSB544_DP4_DP0_DISABLE BIT(0) +#define TUSB544_DP4_DP1_DISABLE BIT(1) +#define TUSB544_DP4_DP2_DISABLE BIT(2) +#define TUSB544_DP4_DP3_DISABLE BIT(3) +#define TUSB544_DP4_AUX_SBU_OVR GENMASK(5, 4) +#define TUSB544_DP4_AUX_SNOOP_DISABLE BIT(7) extern const struct usb_mux_driver tusb544_drv; int tusb544_i2c_field_update8(const struct usb_mux *me, int offset, - uint8_t field_mask, uint8_t set_value); + uint8_t field_mask, uint8_t set_value); #endif -- cgit v1.2.1 From 0b93e5a80e322fb5ce8a8e8b0041794896b5cdb2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:42 -0600 Subject: driver/temp_sensor/adt7481.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44a2315383b935913d9f265c003dcccdc3414d8d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730110 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/adt7481.c | 45 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 26 deletions(-) diff --git a/driver/temp_sensor/adt7481.c b/driver/temp_sensor/adt7481.c index 738fdb776a..f9f771271f 100644 --- a/driver/temp_sensor/adt7481.c +++ b/driver/temp_sensor/adt7481.c @@ -34,14 +34,14 @@ static int has_power(void) static int raw_read8(const int offset, int *data_ptr) { - return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset, + data_ptr); } static int raw_write8(const int offset, int data) { - return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, - offset, data); + return i2c_write8(I2C_PORT_THERMAL, ADT7481_I2C_ADDR_FLAGS, offset, + data); } static int get_temp(const int offset, int *temp_ptr) @@ -145,7 +145,7 @@ int adt7481_set_therm_limit(int channel, int limit_c, int hysteresis) return EC_ERROR_INVAL; if (hysteresis > ADT7481_HYSTERESIS_HIGH_LIMIT || - hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT) + hysteresis < ADT7481_HYSTERESIS_LOW_LIMIT) return EC_ERROR_INVAL; /* hysteresis must be less than high limit */ @@ -197,12 +197,10 @@ static void adt7481_temp_sensor_poll(void) DECLARE_HOOK(HOOK_SECOND, adt7481_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR); #ifdef CONFIG_CMD_TEMP_SENSOR -static void print_temps( - const char *name, - const int adt7481_temp_reg, - const int adt7481_therm_limit_reg, - const int adt7481_high_limit_reg, - const int adt7481_low_limit_reg) +static void print_temps(const char *name, const int adt7481_temp_reg, + const int adt7481_therm_limit_reg, + const int adt7481_high_limit_reg, + const int adt7481_low_limit_reg) { int value; @@ -230,20 +228,14 @@ static int print_status(void) { int value; - print_temps("Local", ADT7481_LOCAL, - ADT7481_LOCAL_THERM_LIMIT, - ADT7481_LOCAL_HIGH_LIMIT_R, - ADT7481_LOCAL_LOW_LIMIT_R); + print_temps("Local", ADT7481_LOCAL, ADT7481_LOCAL_THERM_LIMIT, + ADT7481_LOCAL_HIGH_LIMIT_R, ADT7481_LOCAL_LOW_LIMIT_R); - print_temps("Remote1", ADT7481_REMOTE1, - ADT7481_REMOTE1_THERM_LIMIT, - ADT7481_REMOTE1_HIGH_LIMIT_R, - ADT7481_REMOTE1_LOW_LIMIT_R); + print_temps("Remote1", ADT7481_REMOTE1, ADT7481_REMOTE1_THERM_LIMIT, + ADT7481_REMOTE1_HIGH_LIMIT_R, ADT7481_REMOTE1_LOW_LIMIT_R); - print_temps("Remote2", ADT7481_REMOTE2, - ADT7481_REMOTE2_THERM_LIMIT, - ADT7481_REMOTE2_HIGH_LIMIT, - ADT7481_REMOTE2_LOW_LIMIT); + print_temps("Remote2", ADT7481_REMOTE2, ADT7481_REMOTE2_THERM_LIMIT, + ADT7481_REMOTE2_HIGH_LIMIT, ADT7481_REMOTE2_LOW_LIMIT); ccprintf("\n"); @@ -307,8 +299,8 @@ static int command_adt7481(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", - offset, BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is %pb\n", offset, + BINARY_VALUE(data, 8)); return rv; } @@ -331,7 +323,8 @@ static int command_adt7481(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(adt7481, command_adt7481, +DECLARE_CONSOLE_COMMAND( + adt7481, command_adt7481, "[settemp|setbyte ] or [getbyte ] or" "[power ]. " "Temps in Celsius.", -- cgit v1.2.1 From 93d9e2a017a09563d2337b218c434a2f847003c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:57 -0600 Subject: common/mock/tcpc_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I02ee54a27f40d037c3ba81f39a679b5e6e42e724 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729690 Reviewed-by: Jeremy Bettis --- common/mock/tcpc_mock.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/mock/tcpc_mock.c b/common/mock/tcpc_mock.c index a9bb12b356..9501d45051 100644 --- a/common/mock/tcpc_mock.c +++ b/common/mock/tcpc_mock.c @@ -125,8 +125,7 @@ static int mock_set_msg_header(int port, int power_role, int data_role) return EC_SUCCESS; ccprints("[TCPC] Setting TCPM-side header to %s %s", - from_pd_power_role(power_role), - from_pd_data_role(data_role)); + from_pd_power_role(power_role), from_pd_data_role(data_role)); return EC_SUCCESS; } @@ -141,8 +140,8 @@ static int mock_get_message_raw(int port, uint32_t *payload, int *head) return EC_SUCCESS; } -static int mock_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data) +static int mock_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data) { return EC_SUCCESS; } -- cgit v1.2.1 From dff5c9fb0ab830cde7809d5651f1b3e8c78c17a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:04 -0600 Subject: driver/mcdp28x0.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6fdcd20d712ba961f4fde85ebd13478756cf9215 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730028 Reviewed-by: Jeremy Bettis --- driver/mcdp28x0.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/mcdp28x0.h b/driver/mcdp28x0.h index 4352a3899e..e3e4685b90 100644 --- a/driver/mcdp28x0.h +++ b/driver/mcdp28x0.h @@ -11,11 +11,11 @@ #define MCDP_OUTBUF_MAX 16 #define MCDP_INBUF_MAX 16 -#define MCDP_CMD_GETINFO 0x40 -#define MCDP_CMD_GETDEVID 0x30 -#define MCDP_CMD_APPSTEST 0x12 +#define MCDP_CMD_GETINFO 0x40 +#define MCDP_CMD_GETDEVID 0x30 +#define MCDP_CMD_APPSTEST 0x12 #define MCDP_CMD_APPSTESTPARAM 0x11 -#define MCDP_CMD_ACK 0x0c +#define MCDP_CMD_ACK 0x0c /* packet header (2 bytes: length + cmd) + data + footer (1byte: checksum) */ #define MCDP_RSP_LEN(len) (len + 3) @@ -48,6 +48,6 @@ void mcdp_disable(void); * @info pointer to mcdp_info structure * @return zero if success, error code otherwise. */ -int mcdp_get_info(struct mcdp_info *info); +int mcdp_get_info(struct mcdp_info *info); #endif -- cgit v1.2.1 From a39f3e38a074266996025afd505caa625b5f56af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:03 -0600 Subject: zephyr/shim/chip/it8xxx2/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0e72cbc4b9b41fd2c7a55741f8748524ed0f759 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730812 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/it8xxx2/clock.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/zephyr/shim/chip/it8xxx2/clock.c b/zephyr/shim/chip/it8xxx2/clock.c index 0e7b7cb39e..da57bbeb50 100644 --- a/zephyr/shim/chip/it8xxx2/clock.c +++ b/zephyr/shim/chip/it8xxx2/clock.c @@ -16,21 +16,13 @@ LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) -#define HAL_ECPM_REG_BASE_ADDR \ - ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) -#define PLLFREQ_MASK 0xf +#define ECPM_NODE DT_INST(0, ite_it8xxx2_ecpm) +#define HAL_ECPM_REG_BASE_ADDR \ + ((struct ecpm_reg *)DT_REG_ADDR_BY_IDX(ECPM_NODE, 0)) +#define PLLFREQ_MASK 0xf -static const int pll_reg_to_freq[8] = { - MHZ(8), - MHZ(16), - MHZ(24), - MHZ(32), - MHZ(48), - MHZ(64), - MHZ(72), - MHZ(96) -}; +static const int pll_reg_to_freq[8] = { MHZ(8), MHZ(16), MHZ(24), MHZ(32), + MHZ(48), MHZ(64), MHZ(72), MHZ(96) }; int clock_get_freq(void) { -- cgit v1.2.1 From 1ab8066ecaff16c31392bee43f0758531edbfeb2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:27 -0600 Subject: driver/accelgyro_bmi323.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38e5a3a09e589f7176f4f8f81bbac6319d4e36a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729914 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi323.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/accelgyro_bmi323.h b/driver/accelgyro_bmi323.h index 544e9a4527..5efa0a385f 100644 --- a/driver/accelgyro_bmi323.h +++ b/driver/accelgyro_bmi323.h @@ -10,6 +10,6 @@ #include "accelgyro_bmi3xx.h" -#define BMI323_CHIP_ID 0x43 +#define BMI323_CHIP_ID 0x43 #endif /* __CROS_EC_ACCELGYRO_BMI323_H */ -- cgit v1.2.1 From 782819cff2d0e536c583d38644b77b6a8a6d21d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:25 -0600 Subject: baseboard/volteer/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If9f4e969fd4f73988a89e49c42a6d935b01a0668 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727952 Reviewed-by: Jeremy Bettis --- baseboard/volteer/charger.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/baseboard/volteer/charger.c b/baseboard/volteer/charger.c index a674b98f41..70d07c2591 100644 --- a/baseboard/volteer/charger.c +++ b/baseboard/volteer/charger.c @@ -16,8 +16,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -30,8 +30,7 @@ const struct charger_config_t chg_chips[] = { int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -52,7 +51,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -83,11 +81,10 @@ int board_set_active_charge_port(int port) } __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_overcurrent_event(int port, int is_overcurrented) -- cgit v1.2.1 From 14c96a660e18b7111cd3b946029c7dae901e1710 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:18 -0600 Subject: chip/mchp/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4effabed30115d0762a571c523613c462609efa9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729289 Reviewed-by: Jeremy Bettis --- chip/mchp/espi.c | 252 ++++++++++++++++++++++--------------------------------- 1 file changed, 102 insertions(+), 150 deletions(-) diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c index 763b82ece2..f63262072b 100644 --- a/chip/mchp/espi.c +++ b/chip/mchp/espi.c @@ -36,7 +36,7 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #endif #else #define CPUTS(...) @@ -46,26 +46,26 @@ /* Default config to use maximum frequency */ #ifndef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ #if defined(CHIP_FAMILY_MEC172X) -#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_66M +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_66M #else -#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_50M +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_50M #endif #endif /* Default config to support all modes */ #ifndef CONFIG_HOSTCMD_ESPI_EC_MODE -#define CONFIG_HOSTCMD_ESPI_EC_MODE MCHP_ESPI_CAP1_ALL_MODE +#define CONFIG_HOSTCMD_ESPI_EC_MODE MCHP_ESPI_CAP1_ALL_MODE #endif /* Default config to support all channels */ #ifndef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP -#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP +#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP #endif /* * eSPI slave to master virtual wire pulse timeout. */ -#define ESPI_S2M_VW_PULSE_LOOP_CNT 50 -#define ESPI_S2M_VW_PULSE_LOOP_DLY_US 10 +#define ESPI_S2M_VW_PULSE_LOOP_CNT 50 +#define ESPI_S2M_VW_PULSE_LOOP_DLY_US 10 /* * eSPI master enable virtual wire channel timeout. @@ -104,16 +104,15 @@ static uint32_t espi_channels_ready; * */ struct vw_info_t { - uint16_t name; /* signal name */ - uint8_t host_idx; /* Host VWire index of signal */ - uint8_t reset_val; /* reset value of VWire */ - uint8_t flags; /* b[0]=0(MSVW), =1(SMVW) */ - uint8_t reg_idx; /* MSVW or SMVW index */ - uint8_t src_num; /* SRC number */ - uint8_t rsvd; + uint16_t name; /* signal name */ + uint8_t host_idx; /* Host VWire index of signal */ + uint8_t reset_val; /* reset value of VWire */ + uint8_t flags; /* b[0]=0(MSVW), =1(SMVW) */ + uint8_t reg_idx; /* MSVW or SMVW index */ + uint8_t src_num; /* SRC number */ + uint8_t rsvd; }; - /* VW signals used in eSPI */ /* * MEC1701H VWire mapping based on eSPI Spec 1.0, @@ -193,41 +192,40 @@ static const struct vw_info_t vw_info_tbl[] = { * index value flags index num rsvd */ /* MSVW00 Host index 02h (In) */ - {VW_SLP_S3_L, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00}, - {VW_SLP_S4_L, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00}, - {VW_SLP_S5_L, 0x02, 0x00, 0x10, 0x00, 0x02, 0x00}, + { VW_SLP_S3_L, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { VW_SLP_S4_L, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00 }, + { VW_SLP_S5_L, 0x02, 0x00, 0x10, 0x00, 0x02, 0x00 }, /* MSVW01 Host index 03h (In) */ - {VW_SUS_STAT_L, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00}, - {VW_PLTRST_L, 0x03, 0x00, 0x10, 0x01, 0x01, 0x00}, - {VW_OOB_RST_WARN, 0x03, 0x00, 0x10, 0x01, 0x02, 0x00}, + { VW_SUS_STAT_L, 0x03, 0x00, 0x10, 0x01, 0x00, 0x00 }, + { VW_PLTRST_L, 0x03, 0x00, 0x10, 0x01, 0x01, 0x00 }, + { VW_OOB_RST_WARN, 0x03, 0x00, 0x10, 0x01, 0x02, 0x00 }, /* SMVW00 Host Index 04h (Out) */ - {VW_OOB_RST_ACK, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00}, - {VW_WAKE_L, 0x04, 0x01, 0x01, 0x00, 0x02, 0x00}, - {VW_PME_L, 0x04, 0x01, 0x01, 0x00, 0x03, 0x00}, + { VW_OOB_RST_ACK, 0x04, 0x00, 0x01, 0x00, 0x00, 0x00 }, + { VW_WAKE_L, 0x04, 0x01, 0x01, 0x00, 0x02, 0x00 }, + { VW_PME_L, 0x04, 0x01, 0x01, 0x00, 0x03, 0x00 }, /* SMVW01 Host index 05h (Out) */ - {VW_ERROR_FATAL, 0x05, 0x00, 0x01, 0x01, 0x01, 0x00}, - {VW_ERROR_NON_FATAL, 0x05, 0x00, 0x01, 0x01, 0x02, 0x00}, - {VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00}, + { VW_ERROR_FATAL, 0x05, 0x00, 0x01, 0x01, 0x01, 0x00 }, + { VW_ERROR_NON_FATAL, 0x05, 0x00, 0x01, 0x01, 0x02, 0x00 }, + { VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x00, 0x01, 0x01, 0x30, 0x00 }, /* SMVW02 Host index 06h (Out) */ - {VW_SCI_L, 0x06, 0x01, 0x01, 0x02, 0x00, 0x00}, - {VW_SMI_L, 0x06, 0x01, 0x01, 0x02, 0x01, 0x00}, - {VW_RCIN_L, 0x06, 0x01, 0x01, 0x02, 0x02, 0x00}, - {VW_HOST_RST_ACK, 0x06, 0x00, 0x01, 0x02, 0x03, 0x00}, + { VW_SCI_L, 0x06, 0x01, 0x01, 0x02, 0x00, 0x00 }, + { VW_SMI_L, 0x06, 0x01, 0x01, 0x02, 0x01, 0x00 }, + { VW_RCIN_L, 0x06, 0x01, 0x01, 0x02, 0x02, 0x00 }, + { VW_HOST_RST_ACK, 0x06, 0x00, 0x01, 0x02, 0x03, 0x00 }, /* MSVW02 Host index 07h (In) */ - {VW_HOST_RST_WARN, 0x07, 0x00, 0x10, 0x02, 0x00, 0x00}, + { VW_HOST_RST_WARN, 0x07, 0x00, 0x10, 0x02, 0x00, 0x00 }, /* SMVW03 Host Index 40h (Out) */ - {VW_SUS_ACK, 0x40, 0x00, 0x01, 0x03, 0x00, 0x00}, + { VW_SUS_ACK, 0x40, 0x00, 0x01, 0x03, 0x00, 0x00 }, /* MSVW03 Host Index 41h (In) */ - {VW_SUS_WARN_L, 0x41, 0x00, 0x10, 0x03, 0x00, 0x00}, - {VW_SUS_PWRDN_ACK_L, 0x41, 0x00, 0x10, 0x03, 0x01, 0x00}, - {VW_SLP_A_L, 0x41, 0x00, 0x10, 0x03, 0x03, 0x00}, + { VW_SUS_WARN_L, 0x41, 0x00, 0x10, 0x03, 0x00, 0x00 }, + { VW_SUS_PWRDN_ACK_L, 0x41, 0x00, 0x10, 0x03, 0x01, 0x00 }, + { VW_SLP_A_L, 0x41, 0x00, 0x10, 0x03, 0x03, 0x00 }, /* MSVW04 Host index 42h (In) */ - {VW_SLP_LAN, 0x42, 0x00, 0x10, 0x04, 0x00, 0x00}, - {VW_SLP_WLAN, 0x42, 0x00, 0x10, 0x04, 0x01, 0x00} + { VW_SLP_LAN, 0x42, 0x00, 0x10, 0x04, 0x00, 0x00 }, + { VW_SLP_WLAN, 0x42, 0x00, 0x10, 0x04, 0x01, 0x00 } }; BUILD_ASSERT(ARRAY_SIZE(vw_info_tbl) == VW_SIGNAL_COUNT); - /************************************************************************/ /* eSPI internal utilities */ @@ -244,14 +242,12 @@ static int espi_vw_get_signal_index(enum espi_vw_signal event) return -1; } - /* * Initialize eSPI hardware upon ESPI_RESET# de-assertion */ #ifdef CONFIG_MCHP_ESPI_RESET_DEASSERT_INIT static void espi_reset_deassert_init(void) { - } #endif @@ -341,7 +337,6 @@ static void espi_vw_restore(void) r = MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP); MCHP_VBAT_RAM(MCHP_VBAT_VWIRE_BACKUP) = r & 0xFFFFFF00; - } #endif @@ -362,8 +357,8 @@ static uint8_t __attribute__((unused)) espi_msvw_srcs_get(uint8_t msvw_id) return msvw; } -static void __attribute__((unused)) espi_msvw_srcs_set(uint8_t msvw_id, - uint8_t src_bitmap) +static void __attribute__((unused)) +espi_msvw_srcs_set(uint8_t msvw_id, uint8_t src_bitmap) { if (msvw_id < MSVW_MAX) { uint32_t r = (src_bitmap & 0x08) << 21; @@ -392,8 +387,8 @@ static uint8_t __attribute__((unused)) espi_smvw_srcs_get(uint8_t smvw_id) return smvw; } -static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id, - uint8_t src_bitmap) +static void __attribute__((unused)) +espi_smvw_srcs_set(uint8_t smvw_id, uint8_t src_bitmap) { if (smvw_id < SMVW_MAX) { uint32_t r = (src_bitmap & 0x08) << 21; @@ -405,7 +400,6 @@ static void __attribute__((unused)) espi_smvw_srcs_set(uint8_t smvw_id, } } - /* * Called before releasing RSMRST# * ESPI_RESET# is asserted @@ -466,7 +460,6 @@ static void espi_vw_pre_init(void) CPRINTS("eSPI VW Pre-Init Done"); } - /* * If VWire, Flash, and OOB channels have been enabled * then set VWires SLAVE_BOOT_LOAD_STATUS = SLAVE_BOOT_LOAD_DONE = 1 @@ -488,7 +481,6 @@ static void espi_send_boot_load_done(void) CPRINTS("eSPI Send SLAVE_BOOT_LOAD_STATUS/DONE = 1"); } - /* * Called when eSPI PLTRST# VWire de-asserts * Re-initialize any hardware that was reset while PLTRST# was @@ -541,7 +533,6 @@ static void espi_host_init(void) /* PC enable & Mastering enable changes */ MCHP_ESPI_PC_IEN = (1ul << 25) + (1ul << 28); - /* Sufficiently initialized */ lpc_set_init_done(1); @@ -561,7 +552,6 @@ static void espi_host_init(void) } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, espi_host_init, HOOK_PRIO_FIRST); - /* * Called in response to VWire OOB_RST_WARN==1 from * espi_vw_evt_oob_rst_warn. @@ -573,7 +563,6 @@ static void espi_oob_flush(void) { } - /* * Called in response to VWire HOST_RST_WARN==1 from * espi_vw_evt_host_rst_warn. @@ -589,13 +578,12 @@ static void espi_pc_flush(void) void espi_vw_power_signal_interrupt(enum espi_vw_signal signal) { CPRINTS("eSPI power signal interrupt for VW %d", signal); - power_signal_interrupt((enum gpio_signal) signal); + power_signal_interrupt((enum gpio_signal)signal); } /************************************************************************/ /* IC specific low-level driver */ - /** * Set eSPI Virtual-Wire signal to Host * @@ -632,8 +620,8 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level) } #ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("eSPI VW Set Wire %s = %d", - espi_vw_get_wire_name(signal), level); + CPRINTS("eSPI VW Set Wire %s = %d", espi_vw_get_wire_name(signal), + level); #endif return EC_SUCCESS; @@ -649,16 +637,14 @@ int espi_vw_set_wire(enum espi_vw_signal signal, uint8_t level) * happen quickly is bus is idle. Poll for hardware clearing change bit * until timeout. */ -static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num, - uint8_t level) +static int espi_vw_s2m_set_w4m(uint32_t ridx, uint32_t src_num, uint8_t level) { uint32_t i; MCHP_ESPI_VW_S2M_SRC(ridx, src_num) = level & 0x01; for (i = 0; i < ESPI_S2M_VW_PULSE_LOOP_CNT; i++) { - if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) & - (1u << src_num)) == 0) + if ((MCHP_ESPI_VW_S2M_CHANGE(ridx) & (1u << src_num)) == 0) return EC_SUCCESS; udelay(ESPI_S2M_VW_PULSE_LOOP_DLY_US); } @@ -699,8 +685,8 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level) level = 1; #ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("eSPI VW Pulse Wire %s to %d", - espi_vw_get_wire_name(signal), level); + CPRINTS("eSPI VW Pulse Wire %s to %d", espi_vw_get_wire_name(signal), + level); #endif /* set requested inactive state */ @@ -741,8 +727,8 @@ int espi_vw_get_wire(enum espi_vw_signal signal) src_num = vw_info_tbl[tidx].src_num; vw = MCHP_ESPI_VW_M2S_SRC(ridx, src_num) & 0x01; #ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW GetWire %s = %d", - espi_vw_get_wire_name(signal), vw); + CPRINTS("VW GetWire %s = %d", espi_vw_get_wire_name(signal), + vw); #endif } @@ -769,8 +755,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal) return EC_ERROR_PARAM1; /* signal is Slave-to-Master */ #ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW IntrEn for VW[%s]", - espi_vw_get_wire_name(signal)); + CPRINTS("VW IntrEn for VW[%s]", espi_vw_get_wire_name(signal)); #endif ridx = vw_info_tbl[tidx].reg_idx; @@ -783,7 +768,7 @@ int espi_vw_enable_wire_int(enum espi_vw_signal signal) * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25]) */ MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = - MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES; + MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES; girq_num = 24; if (ridx > 6) { @@ -818,8 +803,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal) return EC_ERROR_PARAM1; /* signal is Slave-to-Master */ #ifdef CONFIG_MCHP_ESPI_DEBUG - CPRINTS("VW IntrDis for VW[%s]", - espi_vw_get_wire_name(signal)); + CPRINTS("VW IntrDis for VW[%s]", espi_vw_get_wire_name(signal)); #endif ridx = vw_info_tbl[tidx].reg_idx; @@ -831,8 +815,7 @@ int espi_vw_disable_wire_int(enum espi_vw_signal signal) * GIRQ24 MSVW00[0:3] through MSVW06[0:3] (bits[0:27]) * GIRQ25 MSVW07[0:3] through MSVW10[0:3] (bits[0:25]) */ - MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = - MCHP_ESPI_MSVW_IRQSEL_DISABLED; + MCHP_ESPI_VW_M2S_IRQSEL(ridx, src_num) = MCHP_ESPI_MSVW_IRQSEL_DISABLED; if (ridx < 7) { bpos = (ridx << 2) + src_num; @@ -857,7 +840,6 @@ static void espi_chipset_reset(void) DECLARE_DEFERRED(espi_chipset_reset); #endif - /* SLP_Sx event handler */ void espi_vw_evt_slp_s3_n(uint32_t wire_state, uint32_t bpos) { @@ -894,7 +876,6 @@ void espi_vw_evt_pltrst_n(uint32_t wire_state, uint32_t bpos) #ifdef CONFIG_CHIPSET_RESET_HOOK hook_call_deferred(&espi_chipset_reset_data, MSEC); #endif - } /* OOB Reset Warn event handler */ @@ -966,7 +947,6 @@ void espi_vw_evt_slp_lan_n(uint32_t wire_state, uint32_t bpos) void espi_vw_evt_slp_wlan_n(uint32_t wire_state, uint32_t bpos) { CPRINTS("VW SLP_WLAN: %d", wire_state); - } void espi_vw_evt_host_c10(uint32_t wire_state, uint32_t bpos) @@ -1024,13 +1004,13 @@ void espi_vw_evt2_dflt(uint32_t wire_state, uint32_t bpos) typedef void (*FPVW)(uint32_t, uint32_t); -#define MCHP_GIRQ24_NUM_M2S (7 * 4) +#define MCHP_GIRQ24_NUM_M2S (7 * 4) const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = { - espi_vw_evt_slp_s3_n, /* MSVW00, Host M2S 02h */ + espi_vw_evt_slp_s3_n, /* MSVW00, Host M2S 02h */ espi_vw_evt_slp_s4_n, espi_vw_evt_slp_s5_n, espi_vw_evt1_dflt, - espi_vw_evt_sus_stat_n, /* MSVW01, Host M2S 03h */ + espi_vw_evt_sus_stat_n, /* MSVW01, Host M2S 03h */ espi_vw_evt_pltrst_n, espi_vw_evt_oob_rst_warn, espi_vw_evt1_dflt, @@ -1038,42 +1018,34 @@ const FPVW girq24_vw_handlers[MCHP_GIRQ24_NUM_M2S] = { espi_vw_evt1_dflt, espi_vw_evt1_dflt, espi_vw_evt1_dflt, - espi_vw_evt_sus_warn_n, /* MSVW03, Host M2S 41h */ + espi_vw_evt_sus_warn_n, /* MSVW03, Host M2S 41h */ espi_vw_evt_sus_pwrdn_ack, espi_vw_evt1_dflt, espi_vw_evt_slp_a_n, - espi_vw_evt_slp_lan_n, /* MSVW04, Host M2S 42h */ + espi_vw_evt_slp_lan_n, /* MSVW04, Host M2S 42h */ espi_vw_evt_slp_wlan_n, espi_vw_evt1_dflt, espi_vw_evt1_dflt, - espi_vw_evt1_dflt, /* MSVW05, Host M2S 43h */ + espi_vw_evt1_dflt, /* MSVW05, Host M2S 43h */ espi_vw_evt1_dflt, espi_vw_evt1_dflt, espi_vw_evt1_dflt, - espi_vw_evt1_dflt, /* MSVW06, Host M2S 44h */ + espi_vw_evt1_dflt, /* MSVW06, Host M2S 44h */ espi_vw_evt1_dflt, espi_vw_evt1_dflt, espi_vw_evt1_dflt }; -#define MCHP_GIRQ25_NUM_M2S (4 * 4) +#define MCHP_GIRQ25_NUM_M2S (4 * 4) const FPVW girq25_vw_handlers[MCHP_GIRQ25_NUM_M2S] = { - espi_vw_evt_host_c10, /* MSVW07, Host M2S 47h */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW08 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW09 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, /* MSVW10 unassigned */ - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, - espi_vw_evt2_dflt, + espi_vw_evt_host_c10, /* MSVW07, Host M2S 47h */ + espi_vw_evt2_dflt, espi_vw_evt2_dflt, espi_vw_evt2_dflt, + espi_vw_evt2_dflt, /* MSVW08 unassigned */ + espi_vw_evt2_dflt, espi_vw_evt2_dflt, espi_vw_evt2_dflt, + espi_vw_evt2_dflt, /* MSVW09 unassigned */ + espi_vw_evt2_dflt, espi_vw_evt2_dflt, espi_vw_evt2_dflt, + espi_vw_evt2_dflt, /* MSVW10 unassigned */ + espi_vw_evt2_dflt, espi_vw_evt2_dflt, espi_vw_evt2_dflt, }; /* Interrupt handler for eSPI virtual wires in MSVW00 - MSVW01 */ @@ -1087,8 +1059,9 @@ static void espi_mswv1_interrupt(void) bpos = __builtin_ctz(girq24_result); /* rbit, clz sequence */ while (bpos != 32) { - d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 + - (12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01; + d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + 8 + (12 * (bpos >> 2)) + + (bpos & 0x03)) & + 0x01; (girq24_vw_handlers[bpos])(d, bpos); girq24_result &= ~(1ul << bpos); bpos = __builtin_ctz(girq24_result); @@ -1096,7 +1069,6 @@ static void espi_mswv1_interrupt(void) } DECLARE_IRQ(MCHP_IRQ_GIRQ24, espi_mswv1_interrupt, 2); - /* Interrupt handler for eSPI virtual wires in MSVW07 - MSVW10 */ static void espi_msvw2_interrupt(void) { @@ -1109,7 +1081,8 @@ static void espi_msvw2_interrupt(void) bpos = __builtin_ctz(girq25_result); /* rbit, clz sequence */ while (bpos != 32) { d = *(uint8_t *)(MCHP_ESPI_MSVW_BASE + (12 * 7) + 8 + - (12 * (bpos >> 2)) + (bpos & 0x03)) & 0x01; + (12 * (bpos >> 2)) + (bpos & 0x03)) & + 0x01; (girq25_vw_handlers[bpos])(d, bpos); girq25_result &= ~(1ul << bpos); bpos = __builtin_ctz(girq25_result); @@ -1117,8 +1090,6 @@ static void espi_msvw2_interrupt(void) } DECLARE_IRQ(MCHP_IRQ_GIRQ25, espi_msvw2_interrupt, 2); - - /* * NOTES: * While ESPI_RESET# is asserted, all eSPI blocks are held in reset and @@ -1167,27 +1138,21 @@ static void espi_reset_isr(void) MCHP_ESPI_IO_RESET_STATUS = erst; MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT; if (erst & (1ul << 1)) { /* rising edge - reset de-asserted */ - MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); + MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = + (MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT + + MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT); MCHP_ESPI_OOB_TX_IEN = (1ul << 1); MCHP_ESPI_FC_IEN = (1ul << 1); MCHP_ESPI_PC_IEN = (1ul << 25); CPRINTS("eSPI Reset de-assert"); } else { /* falling edge - reset asserted */ - MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = ( - MCHP_ESPI_PC_GIRQ_BIT + - MCHP_ESPI_OOB_TX_GIRQ_BIT + - MCHP_ESPI_FC_GIRQ_BIT + - MCHP_ESPI_VW_EN_GIRQ_BIT); + MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = + (MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT + + MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT); + MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = + (MCHP_ESPI_PC_GIRQ_BIT + MCHP_ESPI_OOB_TX_GIRQ_BIT + + MCHP_ESPI_FC_GIRQ_BIT + MCHP_ESPI_VW_EN_GIRQ_BIT); espi_channels_ready = 0; chipset_handle_espi_reset_assert(); @@ -1217,7 +1182,6 @@ static void espi_vw_en_isr(void) } DECLARE_IRQ(MCHP_IRQ_ESPI_VW_EN, espi_vw_en_isr, 2); - /* * eSPI OOB TX and OOB channel enable change interrupt handler */ @@ -1246,7 +1210,6 @@ static void espi_oob_tx_isr(void) } DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_UP, espi_oob_tx_isr, 2); - /* eSPI OOB RX interrupt handler */ static void espi_oob_rx_isr(void) { @@ -1260,7 +1223,6 @@ static void espi_oob_rx_isr(void) } DECLARE_IRQ(MCHP_IRQ_ESPI_OOB_DN, espi_oob_rx_isr, 2); - /* * eSPI Flash Channel enable change and data transfer * interrupt handler @@ -1291,7 +1253,6 @@ static void espi_fc_isr(void) } DECLARE_IRQ(MCHP_IRQ_ESPI_FC, espi_fc_isr, 2); - /* eSPI Peripheral Channel interrupt handler */ static void espi_pc_isr(void) { @@ -1317,7 +1278,6 @@ static void espi_pc_isr(void) } DECLARE_IRQ(MCHP_IRQ_ESPI_PC, espi_pc_isr, 2); - /************************************************************************/ /* @@ -1328,25 +1288,21 @@ static void espi_reset_ictrl(int enable, int clr_status) { if (enable) { if (clr_status) { - MCHP_ESPI_IO_RESET_STATUS = - MCHP_ESPI_RST_CHG_STS; + MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS; MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; + MCHP_ESPI_RESET_GIRQ_BIT; } MCHP_ESPI_IO_RESET_IEN |= MCHP_ESPI_RST_IEN; - MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; + MCHP_INT_ENABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT; task_enable_irq(MCHP_IRQ_ESPI_RESET); } else { task_disable_irq(MCHP_IRQ_ESPI_RESET); - MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; + MCHP_INT_DISABLE(MCHP_ESPI_GIRQ) = MCHP_ESPI_RESET_GIRQ_BIT; MCHP_ESPI_IO_RESET_IEN &= ~(MCHP_ESPI_RST_IEN); if (clr_status) { - MCHP_ESPI_IO_RESET_STATUS = - MCHP_ESPI_RST_CHG_STS; + MCHP_ESPI_IO_RESET_STATUS = MCHP_ESPI_RST_CHG_STS; MCHP_INT_SOURCE(MCHP_ESPI_GIRQ) = - MCHP_ESPI_RESET_GIRQ_BIT; + MCHP_ESPI_RESET_GIRQ_BIT; } } } @@ -1382,12 +1338,11 @@ void espi_init(void) MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP; /* Set eSPI frequency & mode */ - MCHP_ESPI_IO_CAP1 = (MCHP_ESPI_IO_CAP1 & - (~(MCHP_ESPI_CAP1_MAX_FREQ_MASK | - MCHP_ESPI_CAP1_IO_MASK))) | - CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ | - (CONFIG_HOSTCMD_ESPI_EC_MODE - << MCHP_ESPI_CAP1_IO_BITPOS); + MCHP_ESPI_IO_CAP1 = + (MCHP_ESPI_IO_CAP1 & + (~(MCHP_ESPI_CAP1_MAX_FREQ_MASK | MCHP_ESPI_CAP1_IO_MASK))) | + CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ | + (CONFIG_HOSTCMD_ESPI_EC_MODE << MCHP_ESPI_CAP1_IO_BITPOS); #ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW; @@ -1395,8 +1350,7 @@ void espi_init(void) MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_PIN; #endif - MCHP_PCR_PWR_RST_CTL &= - ~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS); + MCHP_PCR_PWR_RST_CTL &= ~(1ul << MCHP_PCR_PWR_HOST_RST_SEL_BITPOS); MCHP_ESPI_ACTIVATE = 1; @@ -1443,7 +1397,6 @@ void espi_init(void) CPRINTS("eSPI - espi_init - done"); } - #ifdef CONFIG_MCHP_ESPI_EC_CMD static int command_espi(int argc, char **argv) { @@ -1452,7 +1405,7 @@ static int command_espi(int argc, char **argv) if (argc == 1) { return EC_ERROR_INVAL; - /* Get value of eSPI registers */ + /* Get value of eSPI registers */ } else if (argc == 2) { int i; @@ -1470,8 +1423,8 @@ static int command_espi(int argc, char **argv) w0 = MSVW(i, 0); w1 = MSVW(i, 1); w2 = MSVW(i, 2); - ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i, - w2, w1, w0); + ccprintf("MSVW%d: 0x%08x:%08x:%08x\n", i, w2, + w1, w0); } } else if (strcasecmp(argv[1], "vms") == 0) { for (i = 0; i < SMVW_MAX; i++) { @@ -1480,9 +1433,9 @@ static int command_espi(int argc, char **argv) ccprintf("SMVW%d: 0x%08x:%08x\n", i, w1, w0); } } - /* Enable/Disable the channels of eSPI */ + /* Enable/Disable the channels of eSPI */ } else if (argc == 3) { - uint32_t m = (uint32_t) strtoi(argv[2], &e, 0); + uint32_t m = (uint32_t)strtoi(argv[2], &e, 0); if (*e) return EC_ERROR_PARAM2; @@ -1502,7 +1455,6 @@ static int command_espi(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(espi, command_espi, - "cfg/vms/vsm/en/dis [channel]", +DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]", "eSPI configurations"); #endif -- cgit v1.2.1 From c677b5143f47e973f245b6945e0445863f9bec98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:42 -0600 Subject: test/stress.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0d4bb17cb13641fc32578e8687c1527f3da43704 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730525 Reviewed-by: Jeremy Bettis --- test/stress.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/test/stress.c b/test/stress.c index 91a65197f8..de53d58a7c 100644 --- a/test/stress.c +++ b/test/stress.c @@ -46,8 +46,7 @@ struct i2c_test_param_t { /* period between 500us and 32ms */ #define RAND_US() (((prng_no_seed() % 64) + 1) * 500) -static int stress(const char *name, - int (*test_routine)(void), +static int stress(const char *name, int (*test_routine)(void), const int iteration) { int i; @@ -65,12 +64,12 @@ static int stress(const char *name, return EC_SUCCESS; } -#define RUN_STRESS_TEST(n, r, iter) \ - do { \ +#define RUN_STRESS_TEST(n, r, iter) \ + do { \ if (stress(n, r, iter) != EC_SUCCESS) { \ - ccputs("Fail\n"); \ - error_count++; \ - } \ + ccputs("Fail\n"); \ + error_count++; \ + } \ } while (0) /*****************************************************************************/ @@ -81,26 +80,27 @@ static int test_i2c(void) int res = EC_ERROR_UNKNOWN; int mock_data; struct i2c_test_param_t *param; - param = i2c_test_params + (prng_no_seed() % (sizeof(i2c_test_params) / - sizeof(struct i2c_test_param_t))); + param = i2c_test_params + + (prng_no_seed() % + (sizeof(i2c_test_params) / sizeof(struct i2c_test_param_t))); if (param->width == 8 && param->data == -1) - res = i2c_read8(param->port, param->addr, - param->offset, &mock_data); + res = i2c_read8(param->port, param->addr, param->offset, + &mock_data); else if (param->width == 8 && param->data >= 0) - res = i2c_write8(param->port, param->addr, - param->offset, param->data); + res = i2c_write8(param->port, param->addr, param->offset, + param->data); else if (param->width == 16 && param->data == -1) - res = i2c_read16(param->port, param->addr, - param->offset, &mock_data); + res = i2c_read16(param->port, param->addr, param->offset, + &mock_data); else if (param->width == 16 && param->data >= 0) - res = i2c_write16(param->port, param->addr, - param->offset, param->data); + res = i2c_write16(param->port, param->addr, param->offset, + param->data); else if (param->width == 32 && param->data == -1) - res = i2c_read32(param->port, param->addr, - param->offset, &mock_data); + res = i2c_read32(param->port, param->addr, param->offset, + &mock_data); else if (param->width == 32 && param->data >= 0) - res = i2c_write32(param->port, param->addr, - param->offset, param->data); + res = i2c_write32(param->port, param->addr, param->offset, + param->data); return res; } -- cgit v1.2.1 From 88a970c061112392f351f36584e29d27bfb1551c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:39 -0600 Subject: driver/ppc/nx20p348x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9034d5db29cb7b803f0b616a92f36aada72fee4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730047 Reviewed-by: Jeremy Bettis --- driver/ppc/nx20p348x.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index e05d7e60a7..d1d315a027 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -19,8 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ @@ -37,17 +37,13 @@ static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int nx20p348x_set_ovp_limit(int port) @@ -76,7 +72,7 @@ static int nx20p348x_is_sourcing_vbus(int port) } static int nx20p348x_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) + enum tcpc_rp_value rp) { int regval; int status; @@ -103,7 +99,6 @@ static int nx20p348x_set_vbus_source_current_limit(int port, break; }; - return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval); } @@ -166,7 +161,8 @@ __maybe_unused static int nx20p3481_vbus_sink_enable(int port, int enable) return rv; return (status & NX20P348X_SWITCH_STATUS_HVSNK) == control ? - EC_SUCCESS : EC_ERROR_UNKNOWN; + EC_SUCCESS : + EC_ERROR_UNKNOWN; } __maybe_unused static int nx20p3481_vbus_source_enable(int port, int enable) @@ -242,7 +238,7 @@ __maybe_unused static int nx20p3483_vbus_sink_enable(int port, int enable) return rv; is_sink = (ds & NX20P3483_DEVICE_MODE_MASK) == - NX20P3483_MODE_HV_SNK; + NX20P3483_MODE_HV_SNK; if (enable == is_sink) return EC_SUCCESS; @@ -409,7 +405,7 @@ static void nx20p348x_handle_interrupt(int port) NX20P348X_DB_EXIT_FAIL_THRESHOLD) { ppc_prints("failed to exit DB mode", port); if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG, - &mask_reg)) { + &mask_reg)) { mask_reg |= NX20P348X_INT1_DBEXIT_ERR; write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask_reg); @@ -502,8 +498,8 @@ static int nx20p348x_dump(int port) int rv; ccprintf("Port %d NX20P348X registers\n", port); - for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <= - NX20P348X_DEVICE_CONTROL_REG; reg_addr++) { + for (reg_addr = NX20P348X_DEVICE_ID_REG; + reg_addr <= NX20P348X_DEVICE_CONTROL_REG; reg_addr++) { rv = read_reg(port, reg_addr, ®); if (rv) { ccprintf("nx20p: Failed to read register 0x%x\n", -- cgit v1.2.1 From 9727f1890ef6a10bbe3baf3709199682a249d71e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:24 -0600 Subject: zephyr/projects/nissa/src/pujjo/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6c961b1494998fde015f933d8fd827db8ac73e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730797 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/pujjo/usbc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/nissa/src/pujjo/usbc.c b/zephyr/projects/nissa/src/pujjo/usbc.c index 020f78dbdd..16a763efb0 100644 --- a/zephyr/projects/nissa/src/pujjo/usbc.c +++ b/zephyr/projects/nissa/src/pujjo/usbc.c @@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port) usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); } -static inline void poll_usb_gpio(int port, - const struct gpio_dt_spec *gpio, +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, const struct deferred_data *ud) { if (!gpio_pin_get_dt(gpio)) { @@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port, } } -static void poll_c0_int (void) +static void poll_c0_int(void) { - poll_usb_gpio(0, - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), &poll_c0_int_data); } -static void poll_c1_int (void) +static void poll_c1_int(void) { - poll_usb_gpio(1, - GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), &poll_c1_int_data); } -- cgit v1.2.1 From 504b0f326249b009c21c77de043bcc9502c190fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:22 -0600 Subject: chip/ish/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb08ada21e53b7d68e8fdd4352bc8f6c43afff51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729157 Reviewed-by: Jeremy Bettis --- chip/ish/gpio.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c index 6c7a27e1e7..110630a01c 100644 --- a/chip/ish/gpio.c +++ b/chip/ish/gpio.c @@ -24,7 +24,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) if (g->port == UNIMPLEMENTED_GPIO_BANK) return 0; - return !!(ISH_GPIO_GPLR & g->mask); + return !!(ISH_GPIO_GPLR & g->mask); } void gpio_set_level(enum gpio_signal signal, int value) @@ -55,8 +55,8 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) } /* ISH 3 can't support both rising and falling edge */ - if (IS_ENABLED(CHIP_FAMILY_ISH3) && - (flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) { + if (IS_ENABLED(CHIP_FAMILY_ISH3) && (flags & GPIO_INT_F_RISING) && + (flags & GPIO_INT_F_FALLING)) { ccprintf("\n\nISH 2/3 does not support both rising & falling " "edge for %d 0x%02x\n\n", port, mask); @@ -65,7 +65,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* GPSR/GPCR Output high/low */ if (flags & GPIO_HIGH) /* Output high */ ISH_GPIO_GPSR |= mask; - else if (flags & GPIO_LOW) /* output low */ + else if (flags & GPIO_LOW) /* output low */ ISH_GPIO_GPCR |= mask; /* GPDR pin direction 1 = output, 0 = input*/ @@ -123,7 +123,6 @@ void gpio_pre_init(void) const struct gpio_info *g = gpio_list; for (i = 0; i < GPIO_COUNT; i++, g++) { - flags = g->flags; if (flags & GPIO_DEFAULT) -- cgit v1.2.1 From c9501c326e164dceab6c87da57fa96c224c57155 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:12 -0600 Subject: common/curve25519.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic57d4d91cd4de1fb5ca35e9720f58464f158ab56 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729603 Reviewed-by: Jeremy Bettis --- common/curve25519.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) mode change 120000 => 100644 common/curve25519.c diff --git a/common/curve25519.c b/common/curve25519.c deleted file mode 120000 index aa9bebe86e..0000000000 --- a/common/curve25519.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/common/curve25519.c \ No newline at end of file diff --git a/common/curve25519.c b/common/curve25519.c new file mode 100644 index 0000000000..19be3a63a7 --- /dev/null +++ b/common/curve25519.c @@ -0,0 +1,69 @@ +/* Copyright 2015, Google Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ + +/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP + * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as + * public domain but this file has the ISC license just to keep licencing + * simple. + * + * The field functions are shared by Ed25519 and X25519 where possible. */ + +#include "common.h" +#include "curve25519.h" +#include "trng.h" +#include "util.h" +#define CRYPTO_memcmp safe_memcmp + +#ifdef CONFIG_RNG +void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) +{ + rand_bytes(out_private_key, 32); + + /* All X25519 implementations should decode scalars correctly (see + * https://tools.ietf.org/html/rfc7748#section-5). However, if an + * implementation doesn't then it might interoperate with random keys a + * fraction of the time because they'll, randomly, happen to be + * correctly formed. + * + * Thus we do the opposite of the masking here to make sure that our + * private keys are never correctly masked and so, hopefully, any + * incorrect implementations are deterministically broken. + * + * This does not affect security because, although we're throwing away + * entropy, a valid implementation of scalarmult should throw away the + * exact same bits anyway. */ + out_private_key[0] |= 7; + out_private_key[31] &= 63; + out_private_key[31] |= 128; + + X25519_public_from_private(out_public_value, out_private_key); +} +#endif + +int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32], + const uint8_t peer_public_value[32]) +{ + static const uint8_t kZeros[32] = { 0 }; + x25519_scalar_mult(out_shared_key, private_key, peer_public_value); + /* The all-zero output results when the input is a point of small order. + */ + return CRYPTO_memcmp(kZeros, out_shared_key, 32) != 0; +} + +void X25519_public_from_private(uint8_t out_public_value[32], + const uint8_t private_key[32]) +{ + static const uint8_t kMongomeryBasePoint[32] = { 9 }; + x25519_scalar_mult(out_public_value, private_key, kMongomeryBasePoint); +} -- cgit v1.2.1 From 381aebf339594639f9974a9dfe8ae40aaaed51d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:35 -0600 Subject: include/rwsig.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iceaec0efa614001ea29961dd24f46f5e5691a49f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730401 Reviewed-by: Jeremy Bettis --- include/rwsig.h | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/include/rwsig.h b/include/rwsig.h index 425618490b..a1a231366d 100644 --- a/include/rwsig.h +++ b/include/rwsig.h @@ -77,22 +77,21 @@ void rwsig_jump_now(void); #endif /* ! CONFIG_RO_PUBKEY_SIZE */ #ifndef CONFIG_RO_PUBKEY_ADDR #ifdef CONFIG_RWSIG_TYPE_RWSIG -#define CONFIG_RO_PUBKEY_STORAGE_OFF (CONFIG_RO_STORAGE_OFF \ - + CONFIG_RO_SIZE \ - - CONFIG_RO_PUBKEY_SIZE) +#define CONFIG_RO_PUBKEY_STORAGE_OFF \ + (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_RO_PUBKEY_SIZE) /* The pubkey resides at the end of the RO image */ -#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE \ - + CONFIG_EC_PROTECTED_STORAGE_OFF \ - + CONFIG_RO_PUBKEY_STORAGE_OFF) +#define CONFIG_RO_PUBKEY_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF + \ + CONFIG_RO_PUBKEY_STORAGE_OFF) #else /* * usbpd1 type assumes pubkey location at the end of first half of flash, * which might actually be in the PSTATE region. */ -#define CONFIG_RO_PUBKEY_ADDR (CONFIG_PROGRAM_MEMORY_BASE \ - + (CONFIG_FLASH_SIZE_BYTES / 2) \ - - CONFIG_RO_PUBKEY_SIZE) +#define CONFIG_RO_PUBKEY_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + (CONFIG_FLASH_SIZE_BYTES / 2) - \ + CONFIG_RO_PUBKEY_SIZE) #endif #endif /* CONFIG_RO_PUBKEY_ADDR */ @@ -108,19 +107,19 @@ void rwsig_jump_now(void); #endif #endif /* ! CONFIG_RW_SIG_SIZE */ /* The signature resides at the end of each RW copy */ -#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define RW_A_ADDR (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_EC_WRITABLE_STORAGE_OFF + \ - CONFIG_RW_STORAGE_OFF) +#define RW_SIG_OFFSET (CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define RW_A_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \ + CONFIG_RW_STORAGE_OFF) /* Assume the layout is same as RW_A and it sits right after RW_A */ -#define RW_B_ADDR (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_EC_WRITABLE_STORAGE_OFF + \ - CONFIG_RW_B_STORAGE_OFF) +#define RW_B_ADDR \ + (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF + \ + CONFIG_RW_B_STORAGE_OFF) #ifndef CONFIG_RW_SIG_ADDR -#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET) +#define CONFIG_RW_SIG_ADDR (RW_A_ADDR + RW_SIG_OFFSET) #endif #ifndef CONFIG_RW_B_SIG_ADDR -#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET) +#define CONFIG_RW_B_SIG_ADDR (RW_B_ADDR + RW_SIG_OFFSET) #endif #endif /* __CROS_EC_RWSIG_H */ -- cgit v1.2.1 From f5dcd6986e69d47f42291eaabd7e564b1bca0f54 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:21 -0600 Subject: zephyr/projects/nissa/src/pujjo/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1271137c5a7536c9af8d7ad3cfbe23ab3f88550f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730796 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/pujjo/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/nissa/src/pujjo/keyboard.c b/zephyr/projects/nissa/src/pujjo/keyboard.c index e6d819e348..8a619a95f6 100644 --- a/zephyr/projects/nissa/src/pujjo/keyboard.c +++ b/zephyr/projects/nissa/src/pujjo/keyboard.c @@ -22,8 +22,8 @@ static const struct ec_response_keybd_config pujjo_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &pujjo_kb; } -- cgit v1.2.1 From 552cffcfc981ad8a3a7d88a687d555bba0335b09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:38 -0600 Subject: baseboard/zork/cbi_ec_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I815ab251475743534049d86953b1a295c882a5f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727957 Reviewed-by: Jeremy Bettis --- baseboard/zork/cbi_ec_fw_config.h | 74 +++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 42 deletions(-) diff --git a/baseboard/zork/cbi_ec_fw_config.h b/baseboard/zork/cbi_ec_fw_config.h index c3ed5b654c..d5f30be098 100644 --- a/baseboard/zork/cbi_ec_fw_config.h +++ b/baseboard/zork/cbi_ec_fw_config.h @@ -19,11 +19,9 @@ * get_cbi_ec_cfg_usb_db() will return the DB option number. * The option number will be defined in a variant or board level enumeration */ -#define EC_CFG_USB_DB_L 0 -#define EC_CFG_USB_DB_H 3 -#define EC_CFG_USB_DB_MASK \ - GENMASK(EC_CFG_USB_DB_H,\ - EC_CFG_USB_DB_L) +#define EC_CFG_USB_DB_L 0 +#define EC_CFG_USB_DB_H 3 +#define EC_CFG_USB_DB_MASK GENMASK(EC_CFG_USB_DB_H, EC_CFG_USB_DB_L) /* * USB Main Board (4 bits) @@ -31,11 +29,9 @@ * get_cbi_ec_cfg_usb_mb() will return the MB option number. * The option number will be defined in a variant or board level enumeration */ -#define EC_CFG_USB_MB_L 4 -#define EC_CFG_USB_MB_H 7 -#define EC_CFG_USB_MB_MASK \ - GENMASK(EC_CFG_USB_MB_H,\ - EC_CFG_USB_MB_L) +#define EC_CFG_USB_MB_L 4 +#define EC_CFG_USB_MB_H 7 +#define EC_CFG_USB_MB_MASK GENMASK(EC_CFG_USB_MB_H, EC_CFG_USB_MB_L) /* * Lid Accelerometer Sensor (3 bits) @@ -47,22 +43,20 @@ enum ec_cfg_lid_accel_sensor_type { LID_ACCEL_KX022 = 1, LID_ACCEL_LIS2DWL = 2, }; -#define EC_CFG_LID_ACCEL_SENSOR_L 8 -#define EC_CFG_LID_ACCEL_SENSOR_H 10 -#define EC_CFG_LID_ACCEL_SENSOR_MASK \ - GENMASK(EC_CFG_LID_ACCEL_SENSOR_H,\ - EC_CFG_LID_ACCEL_SENSOR_L) +#define EC_CFG_LID_ACCEL_SENSOR_L 8 +#define EC_CFG_LID_ACCEL_SENSOR_H 10 +#define EC_CFG_LID_ACCEL_SENSOR_MASK \ + GENMASK(EC_CFG_LID_ACCEL_SENSOR_H, EC_CFG_LID_ACCEL_SENSOR_L) /* * Base Gyro Sensor (3 bits) * * ec_config_has_base_gyro_sensor() will return ec_cfg_base_gyro_sensor_type */ -#define EC_CFG_BASE_GYRO_SENSOR_L 11 -#define EC_CFG_BASE_GYRO_SENSOR_H 13 -#define EC_CFG_BASE_GYRO_SENSOR_MASK \ - GENMASK(EC_CFG_BASE_GYRO_SENSOR_H,\ - EC_CFG_BASE_GYRO_SENSOR_L) +#define EC_CFG_BASE_GYRO_SENSOR_L 11 +#define EC_CFG_BASE_GYRO_SENSOR_H 13 +#define EC_CFG_BASE_GYRO_SENSOR_MASK \ + GENMASK(EC_CFG_BASE_GYRO_SENSOR_H, EC_CFG_BASE_GYRO_SENSOR_L) /* * PWM Keyboard Backlight (1 bit) @@ -73,11 +67,11 @@ enum ec_cfg_pwm_keyboard_backlight_type { PWM_KEYBOARD_BACKLIGHT_NO = 0, PWM_KEYBOARD_BACKLIGHT_YES = 1, }; -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14 -#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \ - GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H,\ - EC_CFG_PWM_KEYBOARD_BACKLIGHT_L) +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_L 14 +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_H 14 +#define EC_CFG_PWM_KEYBOARD_BACKLIGHT_MASK \ + GENMASK(EC_CFG_PWM_KEYBOARD_BACKLIGHT_H, \ + EC_CFG_PWM_KEYBOARD_BACKLIGHT_L) /* * Lid Angle Tablet Mode (1 bit) @@ -88,11 +82,10 @@ enum ec_cfg_lid_angle_tablet_mode_type { LID_ANGLE_TABLET_MODE_NO = 0, LID_ANGLE_TABLET_MODE_YES = 1, }; -#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15 -#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15 +#define EC_CFG_LID_ANGLE_TABLET_MODE_L 15 +#define EC_CFG_LID_ANGLE_TABLET_MODE_H 15 #define EC_CFG_LID_ANGLE_TABLET_MODE_MASK \ - GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H,\ - EC_CFG_LID_ANGLE_TABLET_MODE_L) + GENMASK(EC_CFG_LID_ANGLE_TABLET_MODE_H, EC_CFG_LID_ANGLE_TABLET_MODE_L) /* * LTE Modem Present (1 bit) @@ -103,11 +96,10 @@ enum ec_cfg_lte_present_type { LTE_NONE = 0, LTE_PRESENT = 1, }; -#define EC_CFG_LTE_PRESENT_L 29 -#define EC_CFG_LTE_PRESENT_H 29 +#define EC_CFG_LTE_PRESENT_L 29 +#define EC_CFG_LTE_PRESENT_H 29 #define EC_CFG_LTE_PRESENT_MASK \ - GENMASK(EC_CFG_LTE_PRESENT_H,\ - EC_CFG_LTE_PRESENT_L) + GENMASK(EC_CFG_LTE_PRESENT_H, EC_CFG_LTE_PRESENT_L) /* * Keyboard Layout (2 bit) @@ -118,22 +110,20 @@ enum ec_cfg_keyboard_layout_type { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1, }; -#define EC_CFG_KEYBOARD_LAYOUT_L 30 -#define EC_CFG_KEYBOARD_LAYOUT_H 31 +#define EC_CFG_KEYBOARD_LAYOUT_L 30 +#define EC_CFG_KEYBOARD_LAYOUT_H 31 #define EC_CFG_KEYBOARD_LAYOUT_MASK \ - GENMASK(EC_CFG_KEYBOARD_LAYOUT_H,\ - EC_CFG_KEYBOARD_LAYOUT_L) - + GENMASK(EC_CFG_KEYBOARD_LAYOUT_H, EC_CFG_KEYBOARD_LAYOUT_L) uint32_t get_cbi_fw_config(void); enum ec_cfg_usb_db_type ec_config_get_usb_db(void); enum ec_cfg_usb_mb_type ec_config_get_usb_mb(void); enum ec_cfg_lid_accel_sensor_type ec_config_has_lid_accel_sensor(void); enum ec_ssfc_base_gyro_sensor ec_config_has_base_gyro_sensor(void); -enum ec_cfg_pwm_keyboard_backlight_type ec_config_has_pwm_keyboard_backlight( - void); -enum ec_cfg_lid_angle_tablet_mode_type ec_config_has_lid_angle_tablet_mode( - void); +enum ec_cfg_pwm_keyboard_backlight_type +ec_config_has_pwm_keyboard_backlight(void); +enum ec_cfg_lid_angle_tablet_mode_type +ec_config_has_lid_angle_tablet_mode(void); enum ec_cfg_lte_present_type ec_config_lte_present(void); enum ec_cfg_keyboard_layout_type ec_config_keyboard_layout(void); -- cgit v1.2.1 From 6d1cec5231723f3427a4d21151396db8eed8fa26 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:39 -0600 Subject: board/liara/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2186c72abd73689f7f75a7627e4c66873ce276f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728621 Reviewed-by: Jeremy Bettis --- board/liara/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/liara/led.c b/board/liara/led.c index 371c08ce40..db4e00bc2f 100644 --- a/board/liara/led.c +++ b/board/liara/led.c @@ -19,13 +19,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* White, Amber */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 100, 0 }, - [EC_LED_COLOR_AMBER] = { 0, 100 }, + /* White, Amber */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 100, 0 }, [EC_LED_COLOR_AMBER] = { 0, 100 }, }; /* One logical LED with amber and blue channels. */ -- cgit v1.2.1 From 7eed8ce79a8330d92526726f6340c400bbe7513f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:52 -0600 Subject: board/dewatt/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I13ca74f42230bb0be15693fdc131f5bbc906fbbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728198 Reviewed-by: Jeremy Bettis --- board/dewatt/board.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/dewatt/board.h b/board/dewatt/board.h index 5d34f8324a..ff01f1ab23 100644 --- a/board/dewatt/board.h +++ b/board/dewatt/board.h @@ -26,7 +26,7 @@ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCEL_BMA4XX -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* EC console commands */ #define CONFIG_CMD_ACCELS @@ -37,11 +37,11 @@ #define CONFIG_USB_MUX_ANX7451 #define CONFIG_USBC_RETIMER_ANX7451 -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* Max Power = 65 W */ -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) /* USB Type A Features */ -- cgit v1.2.1 From 2f2c786b032443cd6a6a26970b4d1b5c275e3d35 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:36 -0600 Subject: include/keyboard_test.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie78bbae6a35b5d8d821c5bff41a4277d4a0467e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730310 Reviewed-by: Jeremy Bettis --- include/keyboard_test.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/keyboard_test.h b/include/keyboard_test.h index 142cff5e53..13065a2cc1 100644 --- a/include/keyboard_test.h +++ b/include/keyboard_test.h @@ -16,9 +16,9 @@ * logic. */ struct keyscan_item { - timestamp_t abs_time; /* absolute timestamp to present this item */ - uint32_t time_us; /* time for this item relative to test start */ - uint8_t done; /* 1 if we managed to present this */ + timestamp_t abs_time; /* absolute timestamp to present this item */ + uint32_t time_us; /* time for this item relative to test start */ + uint8_t done; /* 1 if we managed to present this */ uint8_t scan[KEYBOARD_COLS_MAX]; }; -- cgit v1.2.1 From dadfcfbca2c9fe24ca05c20be7cdc9ee2e54b733 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:28 -0600 Subject: chip/mchp/gpio_cmds.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c9c28fab25a2dfbb9771e625ddb1f2fb90f43d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729242 Reviewed-by: Jeremy Bettis --- chip/mchp/gpio_cmds.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/chip/mchp/gpio_cmds.c b/chip/mchp/gpio_cmds.c index 7263909c9c..abbe366367 100644 --- a/chip/mchp/gpio_cmds.c +++ b/chip/mchp/gpio_cmds.c @@ -17,9 +17,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - - +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) static int cmd_gp_get_config(int argc, char **argv) { @@ -43,7 +41,7 @@ static int cmd_gp_get_config(int argc, char **argv) } else { /* Otherwise print them all */ for (i = 0; i < GPIO_COUNT; i++) { if (!gpio_is_implemented(i)) - continue; /* Skip unsupported signals */ + continue; /* Skip unsupported signals */ gctrl = MCHP_GPIO_CTRL(i); @@ -56,8 +54,7 @@ static int cmd_gp_get_config(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config, - "[number]", +DECLARE_CONSOLE_COMMAND(gpgetcfg, cmd_gp_get_config, "[number]", "Read GPIO config"); static int cmd_gp_set_config(int argc, char **argv) @@ -91,6 +88,5 @@ static int cmd_gp_set_config(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config, - "gp_num val", +DECLARE_CONSOLE_COMMAND(gpsetcfg, cmd_gp_set_config, "gp_num val", "Set GPIO config"); -- cgit v1.2.1 From c53ba8e52810b7587d4db04868cd45736a3ebb30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:49 -0600 Subject: board/voxel/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id962c188879ec373fc7a05c52ff39d117e7ff56d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729085 Reviewed-by: Jeremy Bettis --- board/voxel/sensors.c | 29 +++++++++++------------------ 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/board/voxel/sensors.c b/board/voxel/sensors.c index ac444ad840..b65897cd37 100644 --- a/board/voxel/sensors.c +++ b/board/voxel/sensors.c @@ -25,7 +25,7 @@ #include "tablet_mode.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) /******************************************************************************/ /* Sensors */ static struct mutex g_lid_accel_mutex; @@ -40,23 +40,17 @@ static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t kx022_lid_accel = { .name = "Lid Accel", @@ -283,8 +277,7 @@ static void board_sensors_init(void) motion_sensor_count = 0; gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ - gpio_set_flags(GPIO_EC_IMU_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_EC_IMU_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } } DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 7601df3bc0c934ff8b496522843c68c9b927d729 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:38 -0600 Subject: chip/host/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4341e5fb521ff6059d928a35dfb19be2a6d4ab7b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729167 Reviewed-by: Jeremy Bettis --- chip/host/i2c.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/chip/host/i2c.c b/chip/host/i2c.c index ba4ab376d2..32c138cf0f 100644 --- a/chip/host/i2c.c +++ b/chip/host/i2c.c @@ -52,8 +52,7 @@ int test_attach_i2c(const int port, const uint16_t addr_flags) int i; for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i) - if (detached_devs[i].valid && - detached_devs[i].port == port && + if (detached_devs[i].valid && detached_devs[i].port == port && detached_devs[i].addr_flags == addr_flags) break; @@ -64,22 +63,19 @@ int test_attach_i2c(const int port, const uint16_t addr_flags) return EC_SUCCESS; } -static int test_check_detached(const int port, - const uint16_t addr_flags) +static int test_check_detached(const int port, const uint16_t addr_flags) { int i; for (i = 0; i < MAX_DETACHED_DEV_COUNT; ++i) - if (detached_devs[i].valid && - detached_devs[i].port == port && + if (detached_devs[i].valid && detached_devs[i].port == port && detached_devs[i].addr_flags == addr_flags) return 1; return 0; } -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { const struct test_i2c_xfer *p; int rv; @@ -87,9 +83,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, if (test_check_detached(port, addr_flags)) return EC_ERROR_UNKNOWN; for (p = __test_i2c_xfer; p < __test_i2c_xfer_end; ++p) { - rv = p->routine(port, addr_flags, - out, out_size, - in, in_size, flags); + rv = p->routine(port, addr_flags, out, out_size, in, in_size, + flags); if (rv != EC_ERROR_INVAL) return rv; } -- cgit v1.2.1 From 5e135cefdb19e3ab16da6683b9aec5138f310ccc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:00 -0600 Subject: board/pico/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6270071b89f74f0f6b8f630026e4fb2468b28d77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728823 Reviewed-by: Jeremy Bettis --- board/pico/board.c | 107 ++++++++++++++++++++++++----------------------------- 1 file changed, 49 insertions(+), 58 deletions(-) diff --git a/board/pico/board.c b/board/pico/board.c index 093a34d54d..309f51df27 100644 --- a/board/pico/board.c +++ b/board/pico/board.c @@ -43,8 +43,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -55,17 +55,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -171,18 +167,21 @@ int board_sensor_at_360(void) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1}, - {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3}, - {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4}, - {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5}, - {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7}, - {GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1}, - {GPIO_KSO_H, 6}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { -1, -1 }, { -1, -1 }, { GPIO_KSO_L, 5 }, + { GPIO_KSO_L, 6 }, { -1, -1 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { GPIO_KSO_H, 5 }, + { -1, -1 }, { GPIO_KSO_H, 6 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* Wake-up pins for hibernate */ const enum gpio_signal hibernate_wake_pins[] = { @@ -195,39 +194,33 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH1}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH2}, - [ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH0}, + [ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH1 }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH2 }, + [ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 400, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "battery", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, + { .name = "typec", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 400, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "battery", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -235,8 +228,8 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -259,8 +252,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -324,12 +316,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -401,8 +393,7 @@ static void board_motion_init(void) /* Disable tablet mode. */ tablet_set_mode(0, TABLET_TRIGGER_LID); gmr_tablet_switch_disable(); - gpio_set_flags(GPIO_TABLET_MODE_L, - GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_TABLET_MODE_L, GPIO_INPUT | GPIO_PULL_UP); } } DECLARE_HOOK(HOOK_INIT, board_motion_init, HOOK_PRIO_DEFAULT + 1); -- cgit v1.2.1 From 31cd890a2bb2ffd684ff090146b2c778ee904356 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:23 -0600 Subject: driver/temp_sensor/oti502.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic3a8f748d670d296b779b9aa6ac0c3f319986984 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730121 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/oti502.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/driver/temp_sensor/oti502.h b/driver/temp_sensor/oti502.h index 4e846282c1..97e9ef93c4 100644 --- a/driver/temp_sensor/oti502.h +++ b/driver/temp_sensor/oti502.h @@ -8,10 +8,10 @@ #ifndef __CROS_EC_OTI502_H #define __CROS_EC_OTI502_H -#define OTI502_I2C_ADDR_FLAGS 0x10 +#define OTI502_I2C_ADDR_FLAGS 0x10 -#define OTI502_IDX_AMBIENT 0 -#define OTI502_IDX_OBJECT 1 +#define OTI502_IDX_AMBIENT 0 +#define OTI502_IDX_OBJECT 1 /** * Get the last polled value of a sensor. @@ -24,4 +24,4 @@ */ int oti502_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_OTI502_H */ +#endif /* __CROS_EC_OTI502_H */ -- cgit v1.2.1 From d026ec8210131d47e37eab608907a05c70fd057d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:47 -0600 Subject: board/boten/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2097631ad9257224cb48101169b7b65b3630d42d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728039 Reviewed-by: Jeremy Bettis --- board/boten/led.c | 57 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/board/boten/led.c b/board/boten/led.c index 93675966b3..90e6bab217 100644 --- a/board/boten/led.c +++ b/board/boten/led.c @@ -11,41 +11,46 @@ #include "gpio.h" #include "pwm.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 08224051e27eb7aeb40793626baa157fb235bd78 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:53 -0600 Subject: board/pompom/board_revs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e95787a938292c8f021300367bc5c6ca5c0461b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727749 Reviewed-by: Jeremy Bettis --- board/pompom/board_revs.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/pompom/board_revs.h b/board/pompom/board_revs.h index 1ac5ee1337..5b6f850a1b 100644 --- a/board/pompom/board_revs.h +++ b/board/pompom/board_revs.h @@ -8,7 +8,7 @@ #define POMPOM_REV0 0 #define POMPOM_REV1 1 -#define POMPOM_REV_LAST POMPOM_REV1 +#define POMPOM_REV_LAST POMPOM_REV1 #define POMPOM_REV_DEFAULT POMPOM_REV1 #if !defined(BOARD_REV) @@ -19,5 +19,4 @@ #error "Board revision out of range" #endif - #endif /* __CROS_EC_BOARD_REVS_H */ -- cgit v1.2.1 From 23afd26208d2b1e89a17be6acb64d0a64ca53595 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:08 -0600 Subject: zephyr/shim/src/host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4df7af36d8ee0f38d26da726b432573faa6deb4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730896 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/host_command.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/src/host_command.c b/zephyr/shim/src/host_command.c index 7bf61ee551..27e9583622 100644 --- a/zephyr/shim/src/host_command.c +++ b/zephyr/shim/src/host_command.c @@ -10,7 +10,8 @@ struct host_command *zephyr_find_host_command(int command) { - STRUCT_SECTION_FOREACH(host_command, cmd) { + STRUCT_SECTION_FOREACH(host_command, cmd) + { if (cmd->command == command) return cmd; } -- cgit v1.2.1 From 6f7c2df57fb3f863a33fa7bc40a3c9d9cf458f98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:12 -0600 Subject: board/crota/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ec088cfdc7ea0fbcbe07f5d5be7c99c15d66c1a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728212 Reviewed-by: Jeremy Bettis --- board/crota/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/crota/keyboard.c b/board/crota/keyboard.c index d193ac9034..30ae99a6a1 100644 --- a/board/crota/keyboard.c +++ b/board/crota/keyboard.c @@ -41,8 +41,8 @@ static const struct ec_response_keybd_config crota_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &crota_kb; } -- cgit v1.2.1 From 3a95669fa75e048f3083c2a98b93216dd8ba3a25 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:21 -0600 Subject: board/sasuke/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie2138c60b9f99c3625333fb1beeeb51151e6b6ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728898 Reviewed-by: Jeremy Bettis --- board/sasuke/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/sasuke/usb_pd_policy.c b/board/sasuke/usb_pd_policy.c index 3190595596..9edc5a181d 100644 --- a/board/sasuke/usb_pd_policy.c +++ b/board/sasuke/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 229f2eed81a96167ac691df65a54cb01e110a48d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:39 -0600 Subject: common/mkbp_fifo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61f3b3325ba1bf8770ec5f00cc28286f54eab89c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729672 Reviewed-by: Jeremy Bettis --- common/mkbp_fifo.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/common/mkbp_fifo.c b/common/mkbp_fifo.c index c394d9fc77..90c519112f 100644 --- a/common/mkbp_fifo.c +++ b/common/mkbp_fifo.c @@ -15,7 +15,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) /* * Common FIFO depth. This needs to be big enough not to overflow if a @@ -26,9 +26,9 @@ * which is non-trivial but not horrible. */ -static uint32_t fifo_start; /* first entry */ -static uint32_t fifo_end; /* last entry */ -static atomic_t fifo_entries; /* number of existing entries */ +static uint32_t fifo_start; /* first entry */ +static uint32_t fifo_end; /* last entry */ +static atomic_t fifo_entries; /* number of existing entries */ static uint8_t fifo_max_depth = FIFO_DEPTH; static struct ec_response_get_next_event fifo[FIFO_DEPTH]; @@ -114,7 +114,6 @@ void mkbp_fifo_depth_update(uint8_t new_max_depth) fifo_max_depth = new_max_depth; } - void mkbp_fifo_clear_keyboard(void) { int i, new_fifo_entries = 0; @@ -180,8 +179,7 @@ test_mockable int mkbp_fifo_add(uint8_t event_type, const uint8_t *buffp) mutex_lock(&fifo_add_mutex); if (fifo_entries >= fifo_max_depth) { mutex_unlock(&fifo_add_mutex); - CPRINTS("MKBP common FIFO depth %d reached", - fifo_max_depth); + CPRINTS("MKBP common FIFO depth %d reached", fifo_max_depth); return EC_ERROR_OVERFLOW; } -- cgit v1.2.1 From 1d0b4cff372c636fee04c5a721900da8fe95b6c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:17 -0600 Subject: board/beadrix/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie381d09215e2a0caf64ef4a571a168866346b151 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728028 Reviewed-by: Jeremy Bettis --- board/beadrix/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/beadrix/cbi_ssfc.h b/board/beadrix/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/beadrix/cbi_ssfc.h +++ b/board/beadrix/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 91f1170a7d7e18c72265856aa6b37435dbd20abe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:43 -0600 Subject: chip/mchp/lfw/ec_lfw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I89ab0d89dd6d1add0d86817f880192d96c008a1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729295 Reviewed-by: Jeremy Bettis --- chip/mchp/lfw/ec_lfw.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/mchp/lfw/ec_lfw.h b/chip/mchp/lfw/ec_lfw.h index c989a3bc1b..0815531927 100644 --- a/chip/mchp/lfw/ec_lfw.h +++ b/chip/mchp/lfw/ec_lfw.h @@ -30,12 +30,12 @@ void fault_handler(void) __attribute__((naked)); extern uint32_t lfw_stack_top[]; struct int_vector_t { - void *stack_ptr; - void *reset_vector; - void *nmi; - void *hard_fault; - void *bus_fault; - void *usage_fault; + void *stack_ptr; + void *reset_vector; + void *nmi; + void *hard_fault; + void *bus_fault; + void *usage_fault; }; -#define SPI_CHUNK_SIZE 1024 +#define SPI_CHUNK_SIZE 1024 -- cgit v1.2.1 From 7fce53afa856af2e1293a4c8b159796bf20a7a7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:12 -0600 Subject: zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If80d5d64605ecd27b3c25a36e1aa8f25fdcc0a13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730675 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c | 85 ++++++++++++++--------------- 1 file changed, 40 insertions(+), 45 deletions(-) diff --git a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c index e7821c1dac..046fe9c7e1 100644 --- a/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c +++ b/zephyr/drivers/cros_rtc/nxp_rtc_pcf85063a.c @@ -58,12 +58,12 @@ static int pcf85063a_read_time_regs(const struct device *dev, bool is_alarm) num_reg = NUM_TIMER_REGS; } - return i2c_burst_read(config->bus, - config->i2c_addr_flags, start_reg, data->time_reg, num_reg); + return i2c_burst_read(config->bus, config->i2c_addr_flags, start_reg, + data->time_reg, num_reg); } -static int pcf85063a_read_reg(const struct device *dev, - uint8_t reg, uint8_t *val) +static int pcf85063a_read_reg(const struct device *dev, uint8_t reg, + uint8_t *val) { const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev); @@ -95,13 +95,12 @@ static int pcf85063a_write_time_regs(const struct device *dev, bool is_alarm) tx_buf[i] = data->time_reg[i]; } - return i2c_burst_write(config->bus, - config->i2c_addr_flags, start_reg, tx_buf, num_reg); + return i2c_burst_write(config->bus, config->i2c_addr_flags, start_reg, + tx_buf, num_reg); } - -static int pcf85063a_write_reg(const struct device *dev, - uint8_t reg, uint8_t val) +static int pcf85063a_write_reg(const struct device *dev, uint8_t reg, + uint8_t val) { const struct nxp_rtc_pcf85063a_config *const config = DRV_CONFIG(dev); uint8_t tx_buf[2]; @@ -109,8 +108,8 @@ static int pcf85063a_write_reg(const struct device *dev, tx_buf[0] = reg; tx_buf[1] = val; - return i2c_write(config->bus, - tx_buf, sizeof(tx_buf), config->i2c_addr_flags); + return i2c_write(config->bus, tx_buf, sizeof(tx_buf), + config->i2c_addr_flags); } /* @@ -138,7 +137,7 @@ static uint8_t dec_to_bcd(uint32_t val, enum bcd_mask mask) } static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev, - uint32_t *value, bool is_alarm) + uint32_t *value, bool is_alarm) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); struct calendar_date time; @@ -152,31 +151,30 @@ static int nxp_rtc_pcf85063a_read_seconds(const struct device *dev, if (is_alarm) { *value = (bcd_to_dec(data->time_reg[DAYS], DAYS_MASK) * - SECS_PER_DAY) + - (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); + SECS_PER_DAY) + + (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); } else { time.year = bcd_to_dec(data->time_reg[YEARS], YEARS_MASK); - time.month = - bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK); + time.month = bcd_to_dec(data->time_reg[MONTHS], MONTHS_MASK); time.day = bcd_to_dec(data->time_reg[DAYS], DAYS_MASK); *value = date_to_sec(time) - SECS_TILL_YEAR_2K + - (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * - SECS_PER_HOUR) + - (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * - SECS_PER_MINUTE) + - bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); + (bcd_to_dec(data->time_reg[HOURS], HOURS24_MASK) * + SECS_PER_HOUR) + + (bcd_to_dec(data->time_reg[MINUTES], MINUTES_MASK) * + SECS_PER_MINUTE) + + bcd_to_dec(data->time_reg[SECONDS], SECONDS_MASK); } return ret; } static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, - uint32_t value, bool is_alarm) + uint32_t value, bool is_alarm) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); struct calendar_date time; @@ -186,8 +184,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, if (!is_alarm) { data->time_reg[YEARS] = dec_to_bcd(time.year, YEARS_MASK); - data->time_reg[MONTHS] = - dec_to_bcd(time.month, MONTHS_MASK); + data->time_reg[MONTHS] = dec_to_bcd(time.month, MONTHS_MASK); } data->time_reg[DAYS] = dec_to_bcd(time.day, DAYS_MASK); @@ -223,7 +220,7 @@ static int nxp_rtc_pcf85063a_write_seconds(const struct device *dev, } static int nxp_rtc_pcf85063a_configure(const struct device *dev, - cros_rtc_alarm_callback_t callback) + cros_rtc_alarm_callback_t callback) { struct nxp_rtc_pcf85063a_data *data = DRV_DATA(dev); @@ -237,7 +234,7 @@ static int nxp_rtc_pcf85063a_configure(const struct device *dev, } static int nxp_rtc_pcf85063a_get_value(const struct device *dev, - uint32_t *value) + uint32_t *value) { return nxp_rtc_pcf85063a_read_seconds(dev, value, false); } @@ -248,7 +245,8 @@ static int nxp_rtc_pcf85063a_set_value(const struct device *dev, uint32_t value) } static int nxp_rtc_pcf85063a_get_alarm(const struct device *dev, - uint32_t *seconds, uint32_t *microseconds) + uint32_t *seconds, + uint32_t *microseconds) { *microseconds = 0; return nxp_rtc_pcf85063a_read_seconds(dev, seconds, true); @@ -275,7 +273,7 @@ static int nxp_rtc_pcf85063a_reset_alarm(const struct device *dev) } static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev, - uint32_t seconds, uint32_t microseconds) + uint32_t seconds, uint32_t microseconds) { int ret; @@ -297,7 +295,7 @@ static int nxp_rtc_pcf85063a_set_alarm(const struct device *dev, } static void nxp_pcf85063a_isr(const struct device *port, - struct gpio_callback *cb, uint32_t pin) + struct gpio_callback *cb, uint32_t pin) { struct nxp_rtc_pcf85063a_data *data = CONTAINER_OF(cb, struct nxp_rtc_pcf85063a_data, gpio_cb); @@ -400,8 +398,8 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) return ret; } - gpio_init_callback(&data->gpio_cb, - nxp_pcf85063a_isr, BIT(config->gpio_alert.pin)); + gpio_init_callback(&data->gpio_cb, nxp_pcf85063a_isr, + BIT(config->gpio_alert.pin)); ret = gpio_add_callback(config->gpio_alert.port, &data->gpio_cb); @@ -416,8 +414,7 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) GPIO_INT_EDGE_FALLING); } -#define PCF85063A_INT_GPIOS \ - DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin) +#define PCF85063A_INT_GPIOS DT_PHANDLE(DT_NODELABEL(pcf85063a), int_pin) /* * dt_flags is a uint8_t type. However, for platform/ec @@ -426,19 +423,17 @@ static int nxp_rtc_pcf85063a_init(const struct device *dev) * Cast back to a gpio_dt_flags to compile, discarding the bits * that are not supported by the Zephyr GPIO API. */ -#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ - { \ - .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ - .pin = DT_GPIO_PIN(node_id, prop), \ - .dt_flags = \ - (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ +#define CROS_EC_GPIO_DT_SPEC_GET(node_id, prop) \ + { \ + .port = DEVICE_DT_GET(DT_GPIO_CTLR(node_id, prop)), \ + .pin = DT_GPIO_PIN(node_id, prop), \ + .dt_flags = (gpio_dt_flags_t)DT_GPIO_FLAGS(node_id, prop), \ } static const struct nxp_rtc_pcf85063a_config nxp_rtc_pcf85063a_cfg_0 = { .bus = DEVICE_DT_GET(DT_INST_BUS(0)), .i2c_addr_flags = DT_INST_REG_ADDR(0), - .gpio_alert = - CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios) + .gpio_alert = CROS_EC_GPIO_DT_SPEC_GET(PCF85063A_INT_GPIOS, gpios) }; static struct nxp_rtc_pcf85063a_data nxp_rtc_pcf85063a_data_0; -- cgit v1.2.1 From 3797326049dc084fc48b301a02402eecc174171c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:31 -0600 Subject: zephyr/shim/include/usbc/ppc_sn5s330.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iebb8cc4010a20ff74e984f5d9e081da0581a5edf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730835 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/ppc_sn5s330.h | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h index 1c48777107..7ec9b434a8 100644 --- a/zephyr/shim/include/usbc/ppc_sn5s330.h +++ b/zephyr/shim/include/usbc/ppc_sn5s330.h @@ -7,9 +7,7 @@ #define SN5S330_COMPAT ti_sn5s330 -#define PPC_CHIP_SN5S330(id) \ - { \ - .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ - .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ - .drv = &sn5s330_drv \ - }, +#define PPC_CHIP_SN5S330(id) \ + { .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ + .drv = &sn5s330_drv }, -- cgit v1.2.1 From ab4a3d8ff78ac63f61c54434fb4fd75efdbe13c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:16 -0600 Subject: zephyr/shim/src/led_driver/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09b767bc19465392efb3349d770786eeddde8e89 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730911 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/led_driver/led.c | 84 +++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 44 deletions(-) diff --git a/zephyr/shim/src/led_driver/led.c b/zephyr/shim/src/led_driver/led.c index 127c786ddf..14737f31df 100644 --- a/zephyr/shim/src/led_driver/led.c +++ b/zephyr/shim/src/led_driver/led.c @@ -24,7 +24,7 @@ #include LOG_MODULE_REGISTER(led, LOG_LEVEL_ERR); -#define LED_COLOR_NODE DT_PATH(led_colors) +#define LED_COLOR_NODE DT_PATH(led_colors) struct led_color_node_t { struct led_pins_node_t *pins_node; @@ -37,8 +37,7 @@ enum led_extra_flag_t { LED_CHFLAG_DEFAULT, }; -#define DECLARE_PINS_NODE(id) \ -extern struct led_pins_node_t PINS_NODE(id); +#define DECLARE_PINS_NODE(id) extern struct led_pins_node_t PINS_NODE(id); #if DT_HAS_COMPAT_STATUS_OKAY(COMPAT_PWM_LED) DT_FOREACH_CHILD(PWM_LED_PINS_NODE, DECLARE_PINS_NODE) @@ -59,7 +58,7 @@ DT_FOREACH_CHILD(GPIO_LED_PINS_NODE, DECLARE_PINS_NODE) * 3, 4, 5 < period_3 -> LED_COLOR_3 for 3 secs * 6, 7, 8 < period_4 -> LED_COLOR_4 for 3 secs */ -#define MAX_COLOR 4 +#define MAX_COLOR 4 struct node_prop_t { enum charge_state pwr_state; @@ -80,53 +79,50 @@ struct node_prop_t { * HOOT_TICK_INTERVAL_MS */ -#define PERIOD_VAL(id) COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms), \ - (DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0)) +#define PERIOD_VAL(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, period_ms), \ + (DT_PROP(id, period_ms) / HOOK_TICK_INTERVAL_MS), (0)) -#define LED_PERIOD(color_num, state_id) \ +#define LED_PERIOD(color_num, state_id) \ PERIOD_VAL(DT_CHILD(state_id, color_##color_num)) -#define LED_PLUS_PERIOD(color_num, state_id) \ - + LED_PERIOD(color_num, state_id) +#define LED_PLUS_PERIOD(color_num, state_id) +LED_PERIOD(color_num, state_id) -#define ACC_PERIOD(color_num, state_id) \ +#define ACC_PERIOD(color_num, state_id) \ (0 LISTIFY(color_num, LED_PLUS_PERIOD, (), state_id)) -#define PINS_NODE_ADDR(id) DT_PHANDLE(id, led_color) -#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id) \ -{ \ - .pins_node = COND_CODE_1( \ - DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)), \ - (&PINS_NODE(PINS_NODE_ADDR( \ - DT_CHILD(state_id, color_##color_num)))), \ - (NULL)), \ - .acc_period = ACC_PERIOD(color_num_plus_one, state_id) \ -} +#define PINS_NODE_ADDR(id) DT_PHANDLE(id, led_color) +#define LED_COLOR_INIT(color_num, color_num_plus_one, state_id) \ + { \ + .pins_node = COND_CODE_1( \ + DT_NODE_EXISTS(DT_CHILD(state_id, color_##color_num)), \ + (&PINS_NODE(PINS_NODE_ADDR( \ + DT_CHILD(state_id, color_##color_num)))), \ + (NULL)), \ + .acc_period = ACC_PERIOD(color_num_plus_one, state_id) \ + } /* * Initialize node_array struct with prop listed in dts */ -#define SET_LED_VALUES(state_id) \ -{ \ - .pwr_state = GET_PROP(state_id, charge_state), \ - .chipset_state = GET_PROP(state_id, chipset_state), \ - .led_extra_flag = GET_PROP(state_id, extra_flag), \ - .batt_lvl = COND_CODE_1( \ - DT_NODE_HAS_PROP(state_id, batt_lvl), \ - (DT_PROP(state_id, batt_lvl)), ({-1, -1})), \ - .charge_port = COND_CODE_1( \ - DT_NODE_HAS_PROP(state_id, charge_port), \ - (DT_PROP(state_id, charge_port)), (-1)), \ - .led_colors = {LED_COLOR_INIT(0, 1, state_id), \ - LED_COLOR_INIT(1, 2, state_id), \ - LED_COLOR_INIT(2, 3, state_id), \ - LED_COLOR_INIT(3, 4, state_id), \ - } \ -}, - -static const struct node_prop_t node_array[] = { - DT_FOREACH_CHILD(LED_COLOR_NODE, SET_LED_VALUES) -}; +#define SET_LED_VALUES(state_id) \ + { .pwr_state = GET_PROP(state_id, charge_state), \ + .chipset_state = GET_PROP(state_id, chipset_state), \ + .led_extra_flag = GET_PROP(state_id, extra_flag), \ + .batt_lvl = COND_CODE_1(DT_NODE_HAS_PROP(state_id, batt_lvl), \ + (DT_PROP(state_id, batt_lvl)), \ + ({ -1, -1 })), \ + .charge_port = COND_CODE_1(DT_NODE_HAS_PROP(state_id, charge_port), \ + (DT_PROP(state_id, charge_port)), (-1)), \ + .led_colors = { \ + LED_COLOR_INIT(0, 1, state_id), \ + LED_COLOR_INIT(1, 2, state_id), \ + LED_COLOR_INIT(2, 3, state_id), \ + LED_COLOR_INIT(3, 4, state_id), \ + } }, + +static const struct node_prop_t node_array[] = { DT_FOREACH_CHILD( + LED_COLOR_NODE, SET_LED_VALUES) }; static enum power_state get_chipset_state(void) { @@ -159,7 +155,7 @@ static bool find_node_with_extra_flag(int i) case LED_CHFLAG_DEFAULT: if (chflags & CHARGE_FLAG_FORCE_IDLE) { if (node_array[i].led_extra_flag == - LED_CHFLAG_FORCE_IDLE) + LED_CHFLAG_FORCE_IDLE) found_node = true; } else { if (node_array[i].led_extra_flag == LED_CHFLAG_DEFAULT) @@ -168,14 +164,14 @@ static bool find_node_with_extra_flag(int i) break; default: LOG_ERR("Invalid led extra flag %d", - node_array[i].led_extra_flag); + node_array[i].led_extra_flag); break; } return found_node; } -#define GET_PERIOD(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].acc_period +#define GET_PERIOD(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].acc_period #define GET_PIN_NODE(n_idx, c_idx) node_array[n_idx].led_colors[c_idx].pins_node static void set_color(int node_idx, uint32_t ticks) -- cgit v1.2.1 From dcd6ab725880fbb522bca4fd36f5e6ffba649a08 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:48 -0600 Subject: driver/led/tlc59116f.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98a5b6f2119076d469560025bd6739780ae1b00e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730004 Reviewed-by: Jeremy Bettis --- driver/led/tlc59116f.h | 112 ++++++++++++++++++++++++------------------------- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/driver/led/tlc59116f.h b/driver/led/tlc59116f.h index 68ce218517..7960761c12 100644 --- a/driver/led/tlc59116f.h +++ b/driver/led/tlc59116f.h @@ -7,68 +7,68 @@ #define __CROS_EC_DRIVER_LED_TLC59116F_H /* TLC59116F secondary address */ -#define TLC59116F_ADDR0_FLAG 0x60 -#define TLC59116F_ADDR1_FLAG 0x61 -#define TLC59116F_ADDR2_FLAG 0x62 -#define TLC59116F_ADDR3_FLAG 0x63 -#define TLC59116F_ADDR4_FLAG 0x64 -#define TLC59116F_ADDR5_FLAG 0x65 -#define TLC59116F_ADDR6_FLAG 0x66 -#define TLC59116F_ADDR7_FLAG 0x67 -#define TLC59116F_ADDR8_FLAG 0x68 -#define TLC59116F_ADDR9_FLAG 0x69 -#define TLC59116F_ADDR10_FLAG 0x6A -#define TLC59116F_RESET 0x6B -#define TLC59116F_ADDR12_FLAG 0x6C -#define TLC59116F_ADDR13_FLAG 0x6D -#define TLC59116F_ADDR14_FLAG 0x6E -#define TLC59116F_ADDR15_FLAG 0x6F +#define TLC59116F_ADDR0_FLAG 0x60 +#define TLC59116F_ADDR1_FLAG 0x61 +#define TLC59116F_ADDR2_FLAG 0x62 +#define TLC59116F_ADDR3_FLAG 0x63 +#define TLC59116F_ADDR4_FLAG 0x64 +#define TLC59116F_ADDR5_FLAG 0x65 +#define TLC59116F_ADDR6_FLAG 0x66 +#define TLC59116F_ADDR7_FLAG 0x67 +#define TLC59116F_ADDR8_FLAG 0x68 +#define TLC59116F_ADDR9_FLAG 0x69 +#define TLC59116F_ADDR10_FLAG 0x6A +#define TLC59116F_RESET 0x6B +#define TLC59116F_ADDR12_FLAG 0x6C +#define TLC59116F_ADDR13_FLAG 0x6D +#define TLC59116F_ADDR14_FLAG 0x6E +#define TLC59116F_ADDR15_FLAG 0x6F -#define TLC59116F_ROW_SIZE 1 -#define TLC59116F_COL_SIZE 5 -#define TLC59116F_GRID_SIZE (TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE) +#define TLC59116F_ROW_SIZE 1 +#define TLC59116F_COL_SIZE 5 +#define TLC59116F_GRID_SIZE (TLC59116F_COL_SIZE * TLC59116F_ROW_SIZE) /* TLC59116F registers */ -#define TLC59116F_MODE1 0x00 -#define TLC59116F_MODE2 0x01 -#define TLC59116F_PWM0 0x02 -#define TLC59116F_PWM1 0x03 -#define TLC59116F_PWM2 0x04 -#define TLC59116F_PWM3 0x05 -#define TLC59116F_PWM4 0x06 -#define TLC59116F_PWM5 0x07 -#define TLC59116F_PWM6 0x08 -#define TLC59116F_PWM7 0x09 -#define TLC59116F_PWM8 0x0A -#define TLC59116F_PWM9 0x0B -#define TLC59116F_PWM10 0x0C -#define TLC59116F_PWM11 0x0D -#define TLC59116F_PWM12 0x0E -#define TLC59116F_PWM13 0x0F -#define TLC59116F_PWM14 0x10 -#define TLC59116F_PWM15 0x11 -#define TLC59116F_GRPPWM 0x12 -#define TLC59116F_GRPFREQ 0x13 -#define TLC59116F_LEDOUT0 0x14 -#define TLC59116F_LEDOUT1 0x15 -#define TLC59116F_LEDOUT2 0x16 -#define TLC59116F_LEDOUT3 0x17 -#define TLC59116F_SUBADR1 0x18 -#define TLC59116F_SUBADR2 0x19 -#define TLC59116F_SUBADR3 0x1A -#define TLC59116F_ALLCALLADR 0x1B +#define TLC59116F_MODE1 0x00 +#define TLC59116F_MODE2 0x01 +#define TLC59116F_PWM0 0x02 +#define TLC59116F_PWM1 0x03 +#define TLC59116F_PWM2 0x04 +#define TLC59116F_PWM3 0x05 +#define TLC59116F_PWM4 0x06 +#define TLC59116F_PWM5 0x07 +#define TLC59116F_PWM6 0x08 +#define TLC59116F_PWM7 0x09 +#define TLC59116F_PWM8 0x0A +#define TLC59116F_PWM9 0x0B +#define TLC59116F_PWM10 0x0C +#define TLC59116F_PWM11 0x0D +#define TLC59116F_PWM12 0x0E +#define TLC59116F_PWM13 0x0F +#define TLC59116F_PWM14 0x10 +#define TLC59116F_PWM15 0x11 +#define TLC59116F_GRPPWM 0x12 +#define TLC59116F_GRPFREQ 0x13 +#define TLC59116F_LEDOUT0 0x14 +#define TLC59116F_LEDOUT1 0x15 +#define TLC59116F_LEDOUT2 0x16 +#define TLC59116F_LEDOUT3 0x17 +#define TLC59116F_SUBADR1 0x18 +#define TLC59116F_SUBADR2 0x19 +#define TLC59116F_SUBADR3 0x1A +#define TLC59116F_ALLCALLADR 0x1B -#define TLC59116_LEDOUT_OFF 0x00 -#define TLC59116_LEDOUT_ON 0x55 -#define TLC59116_LEDOUT_PWM 0xAA -#define TLC59116_LEDOUT_GROUP 0xFF +#define TLC59116_LEDOUT_OFF 0x00 +#define TLC59116_LEDOUT_ON 0x55 +#define TLC59116_LEDOUT_PWM 0xAA +#define TLC59116_LEDOUT_GROUP 0xFF /* Auto Increment flag */ -#define TLC59116_AI_NONE 0 -#define TLC59116_AI_ALL BIT(7) -#define TLC59116_AI_BRIGHTNESS_ONLY (BIT(7) | BIT(5)) -#define TLC59116_AI_GCR_ONLY (BIT(7) | BIT(6)) +#define TLC59116_AI_NONE 0 +#define TLC59116_AI_ALL BIT(7) +#define TLC59116_AI_BRIGHTNESS_ONLY (BIT(7) | BIT(5)) +#define TLC59116_AI_GCR_ONLY (BIT(7) | BIT(6)) extern const struct rgbkbd_drv tlc59116f_drv; -#endif /* __CROS_EC_DRIVER_LED_TLC59116F_H */ +#endif /* __CROS_EC_DRIVER_LED_TLC59116F_H */ -- cgit v1.2.1 From beb6ad2dfb7d853d9ce168c5d1a1d0be97bfa324 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:09 -0600 Subject: board/woomax/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0614baa20e17ea2527f85bf1d70aae08d163724c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729133 Reviewed-by: Jeremy Bettis --- board/woomax/board.c | 365 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 236 insertions(+), 129 deletions(-) diff --git a/board/woomax/board.c b/board/woomax/board.c index e45fd91623..27274f63a9 100644 --- a/board/woomax/board.c +++ b/board/woomax/board.c @@ -44,8 +44,8 @@ #include "gpio_list.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Motion sensors */ static struct mutex g_lid_mutex; @@ -64,15 +64,15 @@ static const mat33_fp_t lid_standard_ref = { }; static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)}, + { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; static const mat33_fp_t base_standard_ref_icm = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)}, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ @@ -294,8 +294,8 @@ static void board_chipset_resume(void) int val; rv = i2c_read8(I2C_PORT_USBA0, - PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); + PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1, + PS8811_REG1_USB_BEQ_LEVEL, &val); if (!rv) break; } @@ -307,8 +307,7 @@ static void board_chipset_resume(void) if (ec_config_has_hdmi_retimer_pi3hdx1204()) { ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, hpd); } } @@ -319,9 +318,7 @@ static void board_chipset_suspend(void) ioex_set_level(IOEX_USB_A0_RETIMER_EN, 0); if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0); } @@ -340,35 +337,31 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_18DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_18DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_18DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_18DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -376,11 +369,10 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -391,21 +383,18 @@ static int woomax_ps8818_mux_set(const struct usb_mux *me, } if (!(mux_state & USB_PD_MUX_POLARITY_INVERTED)) { - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_CRX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_CRX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1, - PS8818_REG1_APRX1_DE_LEVEL, 0x02); + PS8818_REG1_APRX1_DE_LEVEL, 0x02); } /* set the RX input termination */ - rv |= ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - PS8818_RX_INPUT_TERM_85_OHM); + rv |= ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + PS8818_RX_INPUT_TERM_85_OHM); /* set register 0x40 ICP1 for 1G PD loop */ rv |= ps8818_i2c_write(me, PS8818_REG_PAGE1, 0x40, 0x84); @@ -425,11 +414,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2, + PS8802_REG2_USB_SSEQ_LEVEL, + PS8802_USBEQ_LEVEL_UP_MASK, + PS8802_USBEQ_LEVEL_UP_19DB); if (rv) return rv; } @@ -437,11 +425,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /*Boost the DP gain */ - rv = ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_19DB); + rv = ps8802_i2c_field_update16(me, PS8802_REG_PAGE2, + PS8802_REG2_DPEQ_LEVEL, + PS8802_DPEQ_LEVEL_UP_MASK, + PS8802_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -453,11 +440,10 @@ static int woomax_ps8802_mux_set(const struct usb_mux *me, } /* Set extra swing level tuning at 800mV/P0 */ - rv = ps8802_i2c_field_update8(me, - PS8802_REG_PAGE1, - PS8802_800MV_LEVEL_TUNING, - PS8802_EXTRA_SWING_LEVEL_P0_MASK, - PS8802_EXTRA_SWING_LEVEL_P0_UP_1); + rv = ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, + PS8802_800MV_LEVEL_TUNING, + PS8802_EXTRA_SWING_LEVEL_P0_MASK, + PS8802_EXTRA_SWING_LEVEL_P0_UP_1); return rv; } @@ -481,8 +467,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the PS8802 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_ps8802, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_ps8802, sizeof(struct usb_mux)); /* Set the AMD FP5 as the secondary MUX */ @@ -501,8 +486,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the PS8818 as the secondary MUX */ @@ -510,82 +494,206 @@ static void setup_mux(void) } } -enum pi3dpx1207_usb_conf { - USB_DP = 0, - USB_DP_INV, - USB, - USB_INV, - DP, - DP_INV -}; +enum pi3dpx1207_usb_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV }; static uint8_t pi3dpx1207_picasso_eq[] = { /*usb_dp*/ - 0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B, - 0x07, 0x03, 0x40, 0xFC, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x62, + 0x06, + 0x5B, + 0x5B, + 0x07, + 0x03, + 0x40, + 0xFC, + 0x42, + 0x71, /*usb_dp_inv */ - 0x13, 0x11, 0x20, 0x72, 0x06, 0x03, 0x07, - 0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x72, + 0x06, + 0x03, + 0x07, + 0x5B, + 0x5B, + 0x23, + 0xFC, + 0x42, + 0x71, /*usb*/ - 0x13, 0x11, 0x20, 0x42, 0x00, 0x03, 0x07, - 0x07, 0x03, 0x00, 0x42, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x42, + 0x00, + 0x03, + 0x07, + 0x07, + 0x03, + 0x00, + 0x42, + 0x42, + 0x71, /*usb_inv*/ - 0x13, 0x11, 0x20, 0x52, 0x00, 0x03, 0x07, - 0x07, 0x03, 0x02, 0x42, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x52, + 0x00, + 0x03, + 0x07, + 0x07, + 0x03, + 0x02, + 0x42, + 0x42, + 0x71, /*dp*/ - 0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B, - 0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71, + 0x13, + 0x11, + 0x20, + 0x22, + 0x06, + 0x5B, + 0x5B, + 0x5B, + 0x5B, + 0x60, + 0xFC, + 0xFC, + 0x71, /*dp_inv*/ - 0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B, - 0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71, + 0x13, + 0x11, + 0x20, + 0x32, + 0x06, + 0x5B, + 0x5B, + 0x5B, + 0x5B, + 0x63, + 0xFC, + 0xFC, + 0x71, }; static uint8_t pi3dpx1207_dali_eq[] = { /*usb_dp*/ - 0x13, 0x11, 0x20, 0x62, 0x06, 0x5B, 0x5B, - 0x07, 0x07, 0x40, 0xFC, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x62, + 0x06, + 0x5B, + 0x5B, + 0x07, + 0x07, + 0x40, + 0xFC, + 0x42, + 0x71, /*usb_dp_inv*/ - 0x13, 0x11, 0x20, 0x72, 0x06, 0x07, 0x07, - 0x5B, 0x5B, 0x23, 0xFC, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x72, + 0x06, + 0x07, + 0x07, + 0x5B, + 0x5B, + 0x23, + 0xFC, + 0x42, + 0x71, /*usb*/ - 0x13, 0x11, 0x20, 0x42, 0x00, 0x07, 0x07, - 0x07, 0x07, 0x00, 0x42, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x42, + 0x00, + 0x07, + 0x07, + 0x07, + 0x07, + 0x00, + 0x42, + 0x42, + 0x71, /*usb_inv*/ - 0x13, 0x11, 0x20, 0x52, 0x00, 0x07, 0x07, - 0x07, 0x07, 0x02, 0x42, 0x42, 0x71, + 0x13, + 0x11, + 0x20, + 0x52, + 0x00, + 0x07, + 0x07, + 0x07, + 0x07, + 0x02, + 0x42, + 0x42, + 0x71, /*dp*/ - 0x13, 0x11, 0x20, 0x22, 0x06, 0x5B, 0x5B, - 0x5B, 0x5B, 0x60, 0xFC, 0xFC, 0x71, + 0x13, + 0x11, + 0x20, + 0x22, + 0x06, + 0x5B, + 0x5B, + 0x5B, + 0x5B, + 0x60, + 0xFC, + 0xFC, + 0x71, /*dp_inv*/ - 0x13, 0x11, 0x20, 0x32, 0x06, 0x5B, 0x5B, - 0x5B, 0x5B, 0x63, 0xFC, 0xFC, 0x71, + 0x13, + 0x11, + 0x20, + 0x32, + 0x06, + 0x5B, + 0x5B, + 0x5B, + 0x5B, + 0x63, + 0xFC, + 0xFC, + 0x71, }; static int board_pi3dpx1207_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { - int rv = EC_SUCCESS; + int rv = EC_SUCCESS; enum pi3dpx1207_usb_conf usb_mode = 0; /* USB */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_DP_INV - : USB_DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_DP_INV : + USB_DP; } /* USB without DP */ else { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_INV - : USB; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_INV : + USB; } } /* DP without USB */ else if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? DP_INV - : DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV : + DP; } /* Nothing enabled */ else @@ -594,10 +702,11 @@ static int board_pi3dpx1207_mux_set(const struct usb_mux *me, /* Write the retimer config byte */ if (ec_config_has_usbc1_retimer_ps8802()) rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - &pi3dpx1207_dali_eq[usb_mode*13], 13, NULL, 0); + &pi3dpx1207_dali_eq[usb_mode * 13], 13, NULL, 0); else rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - &pi3dpx1207_picasso_eq[usb_mode*13], 13, NULL, 0); + &pi3dpx1207_picasso_eq[usb_mode * 13], 13, NULL, + 0); return rv; } @@ -667,7 +776,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -758,8 +867,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_THERMISTOR \ - { \ +#define THERMAL_THERMISTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(95), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -774,8 +883,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(95), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -813,8 +922,8 @@ static const struct ec_response_keybd_config woomax_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &woomax_kb; } @@ -833,10 +942,9 @@ static void hdmi_hpd_handler(void) { int hpd = gpio_get_level(GPIO_DP1_HPD_EC_IN); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && hpd); + pi3hdx1204_enable( + I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd); } DECLARE_DEFERRED(hdmi_hpd_handler); @@ -856,9 +964,8 @@ int board_usbc_port_to_hpd_gpio_or_ioex(int port) * USB-C1 OPT3 DB use GPIO_USB_C1_HPD_IN_DB for board version 2 */ else if (ec_config_has_mst_hub_rtd2141b()) - return (board_ver >= 2) - ? GPIO_USB_C1_HPD_IN_DB - : IOEX_USB_C1_HPD_IN_DB; + return (board_ver >= 2) ? GPIO_USB_C1_HPD_IN_DB : + IOEX_USB_C1_HPD_IN_DB; /* USB-C1 OPT1 DB use DP2_HPD. */ return GPIO_DP2_HPD; -- cgit v1.2.1 From 203a84195162941f6f8283f5be61794b94334d09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:28 -0600 Subject: extra/lightbar/simulation.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I725be1b8c902f477705d1dc3663121c115716fdd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730182 Reviewed-by: Jeremy Bettis --- extra/lightbar/simulation.h | 40 +++++++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/extra/lightbar/simulation.h b/extra/lightbar/simulation.h index edbe5f340e..c9263c8e54 100644 --- a/extra/lightbar/simulation.h +++ b/extra/lightbar/simulation.h @@ -38,13 +38,12 @@ int fake_consolecmd_lightbar(int argc, char *argv[]); #define CONFIG_LIGHTBAR_POWER_RAILS #endif - /* Stuff that's too interleaved with the rest of the EC to just include */ /* Test an important condition at compile time, not run time */ -#define _BA1_(cond, line) \ - extern int __build_assertion_ ## line[1 - 2*!(cond)] \ - __attribute__ ((unused)) +#define _BA1_(cond, line) \ + extern int __build_assertion_##line[1 - 2 * !(cond)] \ + __attribute__((unused)) #define _BA0_(c, x) _BA1_(c, x) #define BUILD_ASSERT(cond) _BA0_(cond, __LINE__) @@ -61,14 +60,14 @@ void cprints(int zero, const char *fmt, ...); /* Task events */ #define TASK_EVENT_CUSTOM_BIT(x) BUILD_CHECK_INLINE(BIT(x), BIT(x) & 0x0fffffff) -#define TASK_EVENT_I2C_IDLE 0x10000000 -#define TASK_EVENT_WAKE 0x20000000 -#define TASK_EVENT_MUTEX 0x40000000 -#define TASK_EVENT_TIMER 0x80000000 +#define TASK_EVENT_I2C_IDLE 0x10000000 +#define TASK_EVENT_WAKE 0x20000000 +#define TASK_EVENT_MUTEX 0x40000000 +#define TASK_EVENT_TIMER 0x80000000 /* Time units in usecs */ -#define MSEC 1000 -#define SECOND 1000000 +#define MSEC 1000 +#define SECOND 1000000 #define TASK_ID_LIGHTBAR 0 #define CC_LIGHTBAR 0 @@ -103,15 +102,22 @@ int system_add_jump_tag(uint16_t tag, int version, int size, const void *data); uint8_t *system_get_jump_tag(uint16_t tag, int *version, int *size); /* Export unused static functions to avoid compiler warnings. */ -#define DECLARE_HOOK(X, fn, Y) \ - void fake_hook_##fn(void) { fn(); } +#define DECLARE_HOOK(X, fn, Y) \ + void fake_hook_##fn(void) \ + { \ + fn(); \ + } -#define DECLARE_HOST_COMMAND(X, fn, Y) \ +#define DECLARE_HOST_COMMAND(X, fn, Y) \ enum ec_status fake_hostcmd_##fn(struct host_cmd_handler_args *args) \ - { return fn(args); } + { \ + return fn(args); \ + } -#define DECLARE_CONSOLE_COMMAND(X, fn, Y...) \ +#define DECLARE_CONSOLE_COMMAND(X, fn, Y...) \ int fake_consolecmd_##X(int argc, char *argv[]) \ - { return fn(argc, argv); } + { \ + return fn(argc, argv); \ + } -#endif /* __EXTRA_SIMULATION_H */ +#endif /* __EXTRA_SIMULATION_H */ -- cgit v1.2.1 From 27bad460e2c35132406e838ae78a0d1e38ac8605 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:17 -0600 Subject: zephyr/shim/include/zephyr_mkbp_event.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I522ba0d925cdcf613cc791c73f83a00cf941ab86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730860 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_mkbp_event.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/zephyr_mkbp_event.h b/zephyr/shim/include/zephyr_mkbp_event.h index 159aebc8e1..00e12b6c0f 100644 --- a/zephyr/shim/include/zephyr_mkbp_event.h +++ b/zephyr/shim/include/zephyr_mkbp_event.h @@ -3,21 +3,20 @@ * found in the LICENSE file. */ -#if !defined(__CROS_EC_MKBP_EVENT_H) || \ - defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H) +#if !defined(__CROS_EC_MKBP_EVENT_H) || defined(__CROS_EC_ZEPHYR_MKBP_EVENT_H) #error "This file must only be included from mkbp_event.h. " \ "Include mkbp_event.h directly" #endif #define __CROS_EC_ZEPHYR_MKBP_EVENT_H -const struct mkbp_event_source *zephyr_find_mkbp_event_source( - uint8_t event_type); +const struct mkbp_event_source * +zephyr_find_mkbp_event_source(uint8_t event_type); /** * See include/mkbp_event.h for documentation. */ -#define DECLARE_EVENT_SOURCE(_type, _func) \ - STRUCT_SECTION_ITERABLE(mkbp_event_source, _cros_evtsrc_##_func) = { \ - .event_type = _type, \ - .get_data = _func, \ +#define DECLARE_EVENT_SOURCE(_type, _func) \ + STRUCT_SECTION_ITERABLE(mkbp_event_source, _cros_evtsrc_##_func) = { \ + .event_type = _type, \ + .get_data = _func, \ } -- cgit v1.2.1 From e050d1d4121e9b97541b23f9f2aa9f5cf7e3f22d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:00 -0600 Subject: chip/mchp/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I457c326f837f2d7668c822eaac1ac07731209052 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729224 Reviewed-by: Jeremy Bettis --- chip/mchp/clock.c | 218 ++++++++++++++++++++++++------------------------------ 1 file changed, 95 insertions(+), 123 deletions(-) diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index e646470ac6..0a9a8f219c 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -25,17 +25,17 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) #ifdef CONFIG_LOW_POWER_IDLE -#define HTIMER_DIV_1_US_MAX (1998848) -#define HTIMER_DIV_1_1SEC (0x8012) +#define HTIMER_DIV_1_US_MAX (1998848) +#define HTIMER_DIV_1_1SEC (0x8012) /* Recovery time for HvySlp2 is 0 us */ -#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 +#define HEAVY_SLEEP_RECOVER_TIME_USEC 75 -#define SET_HTIMER_DELAY_USEC 200 +#define SET_HTIMER_DELAY_USEC 200 static int idle_sleep_cnt; static int idle_dsleep_cnt; @@ -52,7 +52,7 @@ static uint32_t ecia_result[MCHP_INT_GIRQ_NUM]; * boot in order to give a permanent window in which the heavy sleep * mode is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) static int console_in_use_timeout_sec = 60; static timestamp_t console_expire_time; #endif /*CONFIG_LOW_POWER_IDLE */ @@ -62,7 +62,8 @@ static int freq = 48000000; void clock_wait_cycles(uint32_t cycles) { asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); + " bne 1b\n" + : "+r"(cycles)); } int clock_get_freq(void) @@ -80,15 +81,13 @@ int clock_get_freq(void) /* 32 KHz crystal connected in parallel */ static inline void config_32k_src_crystal(void) { - MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN - | MCHP_VBAT_CSS_SRC_XTAL; + MCHP_VBAT_CSS = MCHP_VBAT_CSS_XTAL_EN | MCHP_VBAT_CSS_SRC_XTAL; } /* 32 KHz source is 32KHZ_IN pin which must be configured */ static inline void config_32k_src_se_input(void) { - MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN - | MCHP_VBAT_CSS_SRC_SWPS; + MCHP_VBAT_CSS = MCHP_VBAT_CSS_SIL32K_EN | MCHP_VBAT_CSS_SRC_SWPS; } static inline void config_32k_src_sil_osc(void) @@ -99,21 +98,21 @@ static inline void config_32k_src_sil_osc(void) #else static void config_32k_src_crystal(void) { - MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR - | MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL; + MCHP_VBAT_CE = MCHP_VBAT_CE_XOSEL_PAR | + MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL; } /* 32 KHz source is 32KHZ_IN pin which must be configured */ static inline void config_32k_src_se_input(void) { - MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN - | MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT; + MCHP_VBAT_CE = MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN | + MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT; } static inline void config_32k_src_sil_osc(void) { - MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN - | MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL); + MCHP_VBAT_CE = ~(MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN | + MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL); } #endif @@ -173,9 +172,7 @@ static void clock_turbo_disable(void) /* Use 12 MHz processor clock for power savings */ MCHP_PCR_PROC_CLK_CTL = MCHP_PCR_CLK_CTL_12MHZ; } -DECLARE_HOOK(HOOK_INIT, - clock_turbo_disable, - HOOK_PRIO_INIT_VBOOT_HASH + 1); +DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); /** * initialization of Hibernation timer 0 @@ -208,8 +205,7 @@ void htimer_init(void) * 1 is divide by 4096 for 0.125 s per LSB for a maximum of ~2 hours. * 65535 * 0.125 s ~ 8192 s = 2.27 hours */ -void system_set_htimer_alarm(uint32_t seconds, - uint32_t microseconds) +void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds) { uint32_t hcnt, ns; uint8_t hctrl; @@ -226,7 +222,7 @@ void system_set_htimer_alarm(uint32_t seconds, } if (seconds > 1) { - hcnt = (seconds << 3); /* divide by 0.125 */ + hcnt = (seconds << 3); /* divide by 0.125 */ if (hcnt > 0xfffful) hcnt = 0xfffful; hctrl = 1; @@ -236,7 +232,7 @@ void system_set_htimer_alarm(uint32_t seconds, * seconds / 30.5e-6 + microseconds / 30.5 */ hcnt = (seconds << 15) + (microseconds >> 5) + - (microseconds >> 10); + (microseconds >> 10); hctrl = 0; } @@ -254,19 +250,18 @@ static timestamp_t system_get_htimer(void) uint16_t count; timestamp_t time; - count = MCHP_HTIMER_COUNT(0); - + count = MCHP_HTIMER_COUNT(0); if (MCHP_HTIMER_CONTROL(0) == 1) /* if > 2 sec */ /* 0.125 sec per count */ time.le.lo = (uint32_t)(count * 125000); - else /* if < 2 sec */ + else /* if < 2 sec */ /* 30.5(=61/2) us per count */ time.le.lo = (uint32_t)(count * 61 / 2); time.le.hi = 0; - return time; /* in uSec */ + return time; /* in uSec */ } /** @@ -275,8 +270,7 @@ static timestamp_t system_get_htimer(void) static void system_reset_htimer_alarm(void) { MCHP_HTIMER_PRELOAD(0) = 0; - MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = - MCHP_HTIMER_GIRQ_BIT(0); + MCHP_INT_SOURCE(MCHP_HTIMER_GIRQ) = MCHP_HTIMER_GIRQ_BIT(0); } #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG @@ -286,10 +280,10 @@ static void print_pcr_regs(void) trace0(0, MEC, 0, "Current PCR registers"); for (i = 0; i < 5; i++) { - trace12(0, MEC, 0, "REG SLP_EN[%d] = 0x%08X", - i, MCHP_PCR_SLP_EN(i)); - trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X", - i, MCHP_PCR_CLK_REQ(i)); + trace12(0, MEC, 0, "REG SLP_EN[%d] = 0x%08X", i, + MCHP_PCR_SLP_EN(i)); + trace12(0, MEC, 0, "REG CLK_REQ[%d] = 0x%08X", i, + MCHP_PCR_CLK_REQ(i)); } } @@ -298,10 +292,9 @@ static void print_ecia_regs(void) int i; trace0(0, MEC, 0, "Current GIRQn.Result registers"); - for (i = MCHP_INT_GIRQ_FIRST; - i <= MCHP_INT_GIRQ_LAST; i++) - trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X", - i, MCHP_INT_RESULT(i)); + for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; i++) + trace12(0, MEC, 0, "GIRQ[%d].Result = 0x%08X", i, + MCHP_INT_RESULT(i)); } static void save_regs(void) @@ -314,8 +307,7 @@ static void save_regs(void) } for (i = 0; i < MCHP_INT_GIRQ_NUM; i++) - ecia_result[i] = - MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i); + ecia_result[i] = MCHP_INT_RESULT(MCHP_INT_GIRQ_FIRST + i); } static void print_saved_regs(void) @@ -324,21 +316,29 @@ static void print_saved_regs(void) trace0(0, BRD, 0, "Before sleep saved registers"); for (i = 0; i < MCHP_PCR_SLP_RST_REG_MAX; i++) { - trace12(0, BRD, 0, "PCR_SLP_EN[%d] = 0x%08X", - i, pcr_slp_en[i]); - trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X", - i, pcr_clk_req[i]); + trace12(0, BRD, 0, "PCR_SLP_EN[%d] = 0x%08X", i, + pcr_slp_en[i]); + trace12(0, BRD, 0, "PCR_CLK_REQ[%d] = 0x%08X", i, + pcr_clk_req[i]); } for (i = 0; i < MCHP_INT_GIRQ_NUM; i++) trace12(0, BRD, 0, "GIRQ[%d].Result = 0x%08X", - (i+MCHP_INT_GIRQ_FIRST), ecia_result[i]); + (i + MCHP_INT_GIRQ_FIRST), ecia_result[i]); } #else -static __maybe_unused void print_pcr_regs(void) {} -static __maybe_unused void print_ecia_regs(void) {} -static __maybe_unused void save_regs(void) {} -static __maybe_unused void print_saved_regs(void) {} +static __maybe_unused void print_pcr_regs(void) +{ +} +static __maybe_unused void print_ecia_regs(void) +{ +} +static __maybe_unused void save_regs(void) +{ +} +static __maybe_unused void print_saved_regs(void) +{ +} #endif /* #ifdef CONFIG_MCHP_DEEP_SLP_DEBUG */ /** @@ -377,24 +377,19 @@ static void prepare_for_deep_sleep(void) MCHP_TMR32_CTL(1) &= ~1; #ifdef CONFIG_WATCHDOG_HELP MCHP_TMR16_CTL(0) &= ~1; - MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); - MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); + MCHP_INT_DISABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0); + MCHP_INT_SOURCE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0); #endif MCHP_INT_DISABLE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); + MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1); MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); + MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1); #ifdef CONFIG_WATCHDOG /* Stop watchdog */ MCHP_WDG_CTL &= ~1; #endif - #ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; @@ -448,7 +443,7 @@ static void prepare_for_deep_sleep(void) static void resume_from_deep_sleep(void) { - MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */ + MCHP_PCR_SYS_SLP_CTL = 0x00; /* default */ /* Disable assertion of DeepSleep signal when core executes WFI */ CPU_SCB_SYSCTRL &= ~BIT(2); @@ -476,19 +471,19 @@ static void resume_from_deep_sleep(void) MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0); #ifdef CONFIG_HOST_INTERFACE_ESPI - #ifdef CONFIG_POWER_S0IX +#ifdef CONFIG_POWER_S0IX MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; - #else +#else MCHP_ESPI_ACTIVATE |= 1; - #endif +#endif #else - #ifdef CONFIG_POWER_S0IX +#ifdef CONFIG_POWER_S0IX MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_LPC; MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_LPC; - #else +#else MCHP_LPC_ACT |= 1; - #endif +#endif #endif /* re-enable Port 80 capture */ @@ -505,10 +500,8 @@ static void resume_from_deep_sleep(void) MCHP_TMR32_CTL(1) |= 1; MCHP_TMR16_CTL(0) |= 1; MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); - MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = - MCHP_TMR16_GIRQ_BIT(0); + MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1); + MCHP_INT_ENABLE(MCHP_TMR16_GIRQ) = MCHP_TMR16_GIRQ_BIT(0); /* Enable watchdog */ #ifdef CONFIG_WATCHDOG @@ -521,7 +514,6 @@ static void resume_from_deep_sleep(void) #endif } - void clock_refresh_console_in_use(void) { disable_sleep(SLEEP_MASK_CONSOLE); @@ -547,9 +539,7 @@ void __idle(void) htimer_init(); /* hibernation timer initialize */ disable_sleep(SLEEP_MASK_CONSOLE); - console_expire_time.val = get_time().val + - CONSOLE_IN_USE_ON_BOOT_TIME; - + console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; /* * Print when the idle task starts. This is the lowest priority @@ -562,17 +552,15 @@ void __idle(void) /* Disable interrupts */ interrupt_disable(); - t0 = get_time(); /* uSec */ + t0 = get_time(); /* uSec */ /* __hw_clock_event_get() is next programmed timer event */ next_delay = __hw_clock_event_get() - t0.le.lo; - time_for_dsleep = next_delay > - (HEAVY_SLEEP_RECOVER_TIME_USEC + - SET_HTIMER_DELAY_USEC); + time_for_dsleep = next_delay > (HEAVY_SLEEP_RECOVER_TIME_USEC + + SET_HTIMER_DELAY_USEC); - max_sleep_time = next_delay - - HEAVY_SLEEP_RECOVER_TIME_USEC; + max_sleep_time = next_delay - HEAVY_SLEEP_RECOVER_TIME_USEC; /* check if there enough time for deep sleep */ if (DEEP_SLEEP_ALLOWED && time_for_dsleep) { @@ -582,7 +570,7 @@ void __idle(void) * interrupt. */ if ((sleep_mask & SLEEP_MASK_CONSOLE) && - t0.val > console_expire_time.val) { + t0.val > console_expire_time.val) { /* allow console to sleep. */ enable_sleep(SLEEP_MASK_CONSOLE); @@ -598,12 +586,10 @@ void __idle(void) "in deep sleep"); } - /* UART is not being used */ uart_ready_for_deepsleep = LOW_SPEED_DEEP_SLEEP_ALLOWED && - !uart_tx_in_progress() && - uart_buffer_empty(); + !uart_tx_in_progress() && uart_buffer_empty(); /* * Since MCHP's heavy sleep mode requires all @@ -612,7 +598,6 @@ void __idle(void) * heavy sleep of EC. */ if (uart_ready_for_deepsleep) { - idle_dsleep_cnt++; /* @@ -630,18 +615,14 @@ void __idle(void) * interrupt triggers only after 'wfi' * completes its execution. */ - max_sleep_time -= - (get_time().le.lo - t0.le.lo); + max_sleep_time -= (get_time().le.lo - t0.le.lo); /* setup/enable htimer wakeup interrupt */ - system_set_htimer_alarm(0, - max_sleep_time); + system_set_htimer_alarm(0, max_sleep_time); /* set sleep all just before WFI */ - MCHP_PCR_SYS_SLP_CTL |= - MCHP_PCR_SYS_SLP_HEAVY; - MCHP_PCR_SYS_SLP_CTL |= - MCHP_PCR_SYS_SLP_ALL; + MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_HEAVY; + MCHP_PCR_SYS_SLP_CTL |= MCHP_PCR_SYS_SLP_ALL; } else { idle_sleep_cnt++; @@ -654,7 +635,6 @@ void __idle(void) asm("nop"); if (uart_ready_for_deepsleep) { - resume_from_deep_sleep(); /* @@ -673,9 +653,8 @@ void __idle(void) /* disable/clear htimer wakeup interrupt */ system_reset_htimer_alarm(); - t1.val = t0.val + - (uint64_t)(max_sleep_time - - ht_t1.le.lo); + t1.val = t0.val + (uint64_t)(max_sleep_time - + ht_t1.le.lo); force_time(t1); @@ -685,7 +664,7 @@ void __idle(void) /* Record time spent in deep sleep. */ total_idle_dsleep_time_us += (uint64_t)(max_sleep_time - - ht_t1.le.lo); + ht_t1.le.lo); } } else { /* CPU 'Sleep' mode */ @@ -693,7 +672,6 @@ void __idle(void) idle_sleep_cnt++; asm("wfi"); - } interrupt_enable(); @@ -709,23 +687,19 @@ static int command_idle_stats(int argc, char **argv) { timestamp_t ts = get_time(); - ccprintf("Num idle calls that sleep: %d\n", - idle_sleep_cnt); - ccprintf("Num idle calls that deep-sleep: %d\n", - idle_dsleep_cnt); + ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); + ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Total Time spent in deep-sleep(sec): %.6lld(s)\n", - total_idle_dsleep_time_us); - ccprintf("Total time on: %.6llds\n\n", - ts.val); + total_idle_dsleep_time_us); + ccprintf("Total time on: %.6llds\n\n", ts.val); if (IS_ENABLED(CONFIG_MCHP_DEEP_SLP_DEBUG)) - print_pcr_regs(); /* debug */ + print_pcr_regs(); /* debug */ return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* defined(CONFIG_CMD_IDLE_STATS) */ @@ -742,12 +716,10 @@ static int command_dsleep(int argc, char **argv) * Force deep sleep not to use heavy sleep mode or * allow it to use the heavy sleep mode. */ - if (v) /* 'on' */ - disable_sleep( - SLEEP_MASK_FORCE_NO_LOW_SPEED); - else /* 'off' */ - enable_sleep( - SLEEP_MASK_FORCE_NO_LOW_SPEED); + if (v) /* 'on' */ + disable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); + else /* 'off' */ + enable_sleep(SLEEP_MASK_FORCE_NO_LOW_SPEED); } else { /* Set console in use timeout. */ char *e; @@ -765,16 +737,16 @@ static int command_dsleep(int argc, char **argv) ccprintf("Sleep mask: %08x\n", (int)sleep_mask); ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); + console_in_use_timeout_sec); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep NOT to enter heavy sleep mode.\nUse 'off' to " - "allow deep sleep to use heavy sleep whenever conditions " - "allow.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleep mask'."); +DECLARE_CONSOLE_COMMAND( + dsleep, command_dsleep, "[ on | off | sec]", + "Deep sleep clock settings:\nUse 'on' to force deep " + "sleep NOT to enter heavy sleep mode.\nUse 'off' to " + "allow deep sleep to use heavy sleep whenever conditions " + "allow.\n" + "Give a timeout value for the console in use timeout.\n" + "See also 'sleep mask'."); #endif /* CONFIG_LOW_POWER_IDLE */ -- cgit v1.2.1 From de80e05cbd5999333abc91076429125197b0262c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:30 -0600 Subject: board/volteer/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic756d31e020967504c2ae449920cc84468bc0dca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729092 Reviewed-by: Jeremy Bettis --- board/volteer/usbc_config.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/volteer/usbc_config.c b/board/volteer/usbc_config.c index 748e1e9599..f28588f296 100644 --- a/board/volteer/usbc_config.c +++ b/board/volteer/usbc_config.c @@ -279,8 +279,8 @@ __override bool board_is_tbt_usb4_port(int port) * TODO (b/147732807): All the USB-C ports need to support same * features. Need to fix once USB-C feature set is known for Volteer. */ - return ((port == USBC_PORT_C1) - && ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3))); + return ((port == USBC_PORT_C1) && + ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3))); } static void ps8815_reset(void) @@ -288,8 +288,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -300,16 +299,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -321,8 +320,9 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ if (usb_db == DB_USB3_ACTIVE) { ps8815_reset(); - usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(USBC_PORT_C1, + USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); } } -- cgit v1.2.1 From e8fc765fa3ef136a28acd9f498367d9707806078 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:04 -0600 Subject: test/crc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ad89ab41b6ba246bc80d59c02b54cf331370c13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730497 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/crc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/crc.c b/test/crc.c index e65be72ace..b757d117e6 100644 --- a/test/crc.c +++ b/test/crc.c @@ -37,7 +37,7 @@ static int test_8(void) { uint32_t crc; const uint32_t input = 0xdeadbeef; - const uint8_t *p = (const uint8_t *) &input; + const uint8_t *p = (const uint8_t *)&input; int i; crc32_init(); -- cgit v1.2.1 From 11868f1dcdedae8f12f9ae0b97fe92cb60f7a071 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:32 -0600 Subject: board/brya/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifddd44ca31ea9ed6a4968efc80c1b5620218b65b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728103 Reviewed-by: Jeremy Bettis --- board/brya/led.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/brya/led.c b/board/brya/led.c index 78c10e65b8..cddf8c971f 100644 --- a/board/brya/led.c +++ b/board/brya/led.c @@ -30,13 +30,10 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * both LEDs being off. Cap at 50% to save power. */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, White */ - [EC_LED_COLOR_RED] = { 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, - [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 50 }, - [EC_LED_COLOR_AMBER] = { 50, 0 }, + /* Amber, White */ + [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 50 }, [EC_LED_COLOR_AMBER] = { 50, 0 }, }; /* Two logical LEDs with amber and white channels. */ -- cgit v1.2.1 From 7b91899aeb58681b7dd2570b14108229c8decced Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:38 -0600 Subject: zephyr/drivers/cros_system/cros_system_xec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73a547c4c018d600df8e5f4279992519dec8fae8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730683 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_system/cros_system_xec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/drivers/cros_system/cros_system_xec.c b/zephyr/drivers/cros_system/cros_system_xec.c index 8d0c8f864c..0e128fe0f3 100644 --- a/zephyr/drivers/cros_system/cros_system_xec.c +++ b/zephyr/drivers/cros_system/cros_system_xec.c @@ -38,7 +38,7 @@ struct cros_system_xec_data { #define HAL_WDOG_INST(dev) (struct wdt_regs *)(DRV_CONFIG(dev)->base_wdog) /* Get saved reset flag address in battery-backed ram */ -#define BBRAM_SAVED_RESET_FLAG_ADDR \ +#define BBRAM_SAVED_RESET_FLAG_ADDR \ (DT_REG_ADDR(DT_INST(0, microchip_xec_bbram)) + \ DT_PROP(DT_PATH(named_bbram_regions, saved_reset_flags), offset)) @@ -46,8 +46,8 @@ struct cros_system_xec_data { static int system_xec_watchdog_stop(void) { if (IS_ENABLED(CONFIG_WATCHDOG)) { - const struct device *wdt_dev = DEVICE_DT_GET( - DT_NODELABEL(wdog)); + const struct device *wdt_dev = + DEVICE_DT_GET(DT_NODELABEL(wdog)); if (!device_is_ready(wdt_dev)) { LOG_ERR("Error: device %s is not ready", wdt_dev->name); return -ENODEV; @@ -130,8 +130,8 @@ noreturn static int cros_system_xec_soc_reset(const struct device *dev) /* return 0; */ } -static int cros_system_xec_hibernate(const struct device *dev, - uint32_t seconds, uint32_t microseconds) +static int cros_system_xec_hibernate(const struct device *dev, uint32_t seconds, + uint32_t microseconds) { /* Disable interrupt first */ interrupt_disable_all(); -- cgit v1.2.1 From 244ac624c47010cfb8e312dd41b7a818e6d4d3d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:16 -0600 Subject: board/poppy/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2979108fdae9a0b3bc952de0654056c3cdbff26 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727755 Reviewed-by: Jeremy Bettis --- board/poppy/usb_pd_policy.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/board/poppy/usb_pd_policy.c b/board/poppy/usb_pd_policy.c index a32b77bbe7..0362ab4212 100644 --- a/board/poppy/usb_pd_policy.c +++ b/board/poppy/usb_pd_policy.c @@ -22,12 +22,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -48,8 +48,8 @@ static void board_vbus_update_source_current(int port) * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals * can remain outputs. */ - gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? - 1 : 0); + gpio_set_level(gpio_3a_en, + vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0); gpio_set_level(gpio_5v_en, vbus_en[port]); } else { /* @@ -61,8 +61,8 @@ static void board_vbus_update_source_current(int port) * 1505 mA. */ int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : - (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); gpio_set_level(gpio_5v_en, vbus_en[port]); gpio_set_flags(gpio_5v_en, flags); } @@ -79,8 +79,7 @@ void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 1); + gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1); /* Ensure we advertise the proper available current quota */ charge_manager_source_port(port, 1); @@ -131,15 +130,13 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_PMIC_SLP_SUS_L); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) return; - gpio_set_level(GPIO_USB2_OTG_ID, - (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0); gpio_set_level(GPIO_USB2_OTG_VBUSSENSE, - (data_role == PD_ROLE_UFP) ? 1 : 0); + (data_role == PD_ROLE_UFP) ? 1 : 0); } -- cgit v1.2.1 From dbed67f6238f6cc21caf657371acec5fdc4f45a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:02 -0600 Subject: board/poppy/base_detect_poppy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I149e77e2156871a56203b82d9fd43d5130d40200 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727751 Reviewed-by: Jeremy Bettis --- board/poppy/base_detect_poppy.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/poppy/base_detect_poppy.c b/board/poppy/base_detect_poppy.c index 0fde6fb8e6..49a58bb963 100644 --- a/board/poppy/base_detect_poppy.c +++ b/board/poppy/base_detect_poppy.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* Base detection and debouncing */ #define BASE_DETECT_DEBOUNCE_US (20 * MSEC) @@ -101,7 +101,6 @@ static void base_detect_change(enum base_status status) acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_ATTACHED); else acpi_dptf_set_profile_num(DPTF_PROFILE_BASE_DETACHED); - } /* Measure detection pin pulse duration (used to wake AP from deep S3). */ @@ -110,8 +109,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -243,7 +242,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From 93c73d6d3310814089e25c7250634a222dbf427b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:06 -0600 Subject: chip/ish/aontaskfw/ish_aontask.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6211f44887f37628eedde187190dcb0e24f1173f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729172 Reviewed-by: Jeremy Bettis --- chip/ish/aontaskfw/ish_aontask.c | 204 ++++++++++++++++----------------------- 1 file changed, 83 insertions(+), 121 deletions(-) diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index e2106abf0a..0e5833eeba 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -64,9 +64,9 @@ * AON_IDT_ENTRY_VEC_FIRST ~ AON_IDT_ENTRY_VEC_LAST */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC #else -#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC #endif #ifdef CONFIG_ISH_PM_RESET_PREP @@ -76,16 +76,16 @@ * (if CONFIG_ISH_PM_RESET_PREP defined) */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_RESET_PREP_VEC #else -#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_RESET_PREP_VEC #endif #else /* only need handle single PMU wakeup interrupt */ #ifdef CONFIG_ISH_NEW_PM -#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_FIRST ISH_PMU_WAKEUP_VEC #else -#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC +#define AON_IDT_ENTRY_VEC_LAST ISH_PMU_WAKEUP_VEC #endif #endif @@ -101,7 +101,7 @@ static void pmu_wakeup_isr(void) IOAPIC_EOI_REG = ISH_PMU_WAKEUP_VEC; LAPIC_EOI_REG = 0x0; - __asm__ volatile ("iret;"); + __asm__ volatile("iret;"); __builtin_unreachable(); } @@ -157,14 +157,15 @@ static void reset_prep_isr(void) * --------------------------- */ -static struct idt_entry aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST + 1]; +static struct idt_entry + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST + 1]; static struct idt_header aon_idt_hdr = { .limit = (sizeof(struct idt_entry) * (AON_IDT_ENTRY_VEC_LAST + 1)) - 1, .entries = (struct idt_entry *)((uint32_t)&aon_idt - - (sizeof(struct idt_entry) * AON_IDT_ENTRY_VEC_FIRST)) + (sizeof(struct idt_entry) * + AON_IDT_ENTRY_VEC_FIRST)) }; /** @@ -245,13 +246,9 @@ static ldt_entry aon_ldt[2] = { * limit: 0xFFFFFFFF * flag: 0x9B, Present = 1, DPL = 0, code segment */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS), + { .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS), - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_CODE_FLAGS) - }, + .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_CODE_FLAGS) }, /** * entry 1 for data segment @@ -259,16 +256,11 @@ static ldt_entry aon_ldt[2] = { * limit: 0xFFFFFFFF * flag: 0x93, Present = 1, DPL = 0, data segment */ - { - .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS), + { .dword_lo = GEN_GDT_DESC_LO(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS), - .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, - GDT_DESC_DATA_FLAGS) - } + .dword_up = GEN_GDT_DESC_UP(0x0, 0xFFFFFFFF, GDT_DESC_DATA_FLAGS) } }; - /* shared data structure between main FW and aon task */ struct ish_aon_share aon_share = { .magic_id = AON_MAGIC_ID, @@ -282,15 +274,14 @@ struct ish_aon_share aon_share = { /* snowball structure */ #if defined(CHIP_FAMILY_ISH3) /* on ISH3, reused ISH2PMC IPC message registers */ -#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE #else /* from ISH4, used reserved rom part of AON memory */ -#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) +#define SNOWBALL_BASE (CONFIG_AON_PERSISTENT_BASE + 256) #endif struct snowball_struct *snowball = (void *)SNOWBALL_BASE; - /* In IMR DDR, ISH FW image has a manifest header */ #define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000) @@ -324,30 +315,24 @@ static int store_main_fw(void) uint64_t imr_fw_rw_addr; imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + + snowball->uma_base_lo + snowball->fw_offset + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); + imr_fw_rw_addr = + (imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE); /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ disable_dma_bcg(); /* store main FW's read and write data region to IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - imr_fw_rw_addr, - aon_share.main_fw_rw_addr, - aon_share.main_fw_rw_size, - SRAM_TO_UMA); + ret = ish_dma_copy(PAGING_CHAN, imr_fw_rw_addr, + aon_share.main_fw_rw_addr, aon_share.main_fw_rw_size, + SRAM_TO_UMA); /* enable BCG for DMA, DMA can't be accessed now */ enable_dma_bcg(); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -365,31 +350,24 @@ static int restore_main_fw(void) uint64_t imr_fw_rw_addr; imr_fw_addr = (((uint64_t)snowball->uma_base_hi << 32) + - snowball->uma_base_lo + - snowball->fw_offset + + snowball->uma_base_lo + snowball->fw_offset + ISH_FW_IMAGE_MANIFEST_HEADER_SIZE); - imr_fw_ro_addr = (imr_fw_addr - + aon_share.main_fw_ro_addr - - CONFIG_RAM_BASE); + imr_fw_ro_addr = + (imr_fw_addr + aon_share.main_fw_ro_addr - CONFIG_RAM_BASE); - imr_fw_rw_addr = (imr_fw_addr - + aon_share.main_fw_rw_addr - - CONFIG_RAM_BASE); + imr_fw_rw_addr = + (imr_fw_addr + aon_share.main_fw_rw_addr - CONFIG_RAM_BASE); /* disable BCG (Block Clock Gating) for DMA, DMA can be accessed now */ disable_dma_bcg(); /* restore main FW's read only code and data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_ro_addr, - imr_fw_ro_addr, - aon_share.main_fw_ro_size, - UMA_TO_SRAM); + ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_ro_addr, + imr_fw_ro_addr, aon_share.main_fw_ro_size, + UMA_TO_SRAM); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -400,19 +378,14 @@ static int restore_main_fw(void) } /* restore main FW's read and write data region from IMR/UMA DDR */ - ret = ish_dma_copy( - PAGING_CHAN, - aon_share.main_fw_rw_addr, - imr_fw_rw_addr, - aon_share.main_fw_rw_size, - UMA_TO_SRAM - ); + ret = ish_dma_copy(PAGING_CHAN, aon_share.main_fw_rw_addr, + imr_fw_rw_addr, aon_share.main_fw_rw_size, + UMA_TO_SRAM); /* enable BCG for DMA, DMA can't be accessed now */ enable_dma_bcg(); if (ret != DMA_RC_OK) { - aon_share.last_error = AON_ERROR_DMA_FAILED; aon_share.error_count++; @@ -424,10 +397,10 @@ static int restore_main_fw(void) #if defined(CHIP_FAMILY_ISH3) /* on ISH3, the last SRAM bank is reserved for AON use */ -#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1) +#define SRAM_POWER_OFF_BANKS (CONFIG_RAM_BANKS - 1) #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) /* ISH4 and ISH5 have separate AON memory, can power off entire main SRAM */ -#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS +#define SRAM_POWER_OFF_BANKS CONFIG_RAM_BANKS #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif @@ -436,33 +409,33 @@ static int restore_main_fw(void) * check SRAM bank i power gated status in PMU_SRAM_PG_EN register * 1: power gated 0: not power gated */ -#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) +#define BANK_PG_STATUS(i) (PMU_SRAM_PG_EN & (0x1 << (i))) /* enable power gate of a SRAM bank */ -#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) +#define BANK_PG_ENABLE(i) (PMU_SRAM_PG_EN |= (0x1 << (i))) /* disable power gate of a SRAM bank */ -#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) +#define BANK_PG_DISABLE(i) (PMU_SRAM_PG_EN &= ~(0x1 << (i))) /** * check SRAM bank i disabled status in ISH_SRAM_CTRL_CSFGR register * 1: disabled 0: enabled */ -#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) +#define BANK_DISABLE_STATUS(i) (ISH_SRAM_CTRL_CSFGR & (0x1 << ((i) + 4))) /* enable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) +#define BANK_ENABLE(i) (ISH_SRAM_CTRL_CSFGR &= ~(0x1 << ((i) + 4))) /* disable a SRAM bank in ISH_SRAM_CTRL_CSFGR register */ -#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) +#define BANK_DISABLE(i) (ISH_SRAM_CTRL_CSFGR |= (0x1 << ((i) + 4))) /* SRAM needs time to warm up after power on */ -#define SRAM_WARM_UP_DELAY_CNT 10 +#define SRAM_WARM_UP_DELAY_CNT 10 /* SRAM needs time to enter retention mode */ -#define CYCLES_PER_US 100 -#define SRAM_RETENTION_US_DELAY 5 -#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) +#define CYCLES_PER_US 100 +#define SRAM_RETENTION_US_DELAY 5 +#define SRAM_RETENTION_CYCLES_DELAY (SRAM_RETENTION_US_DELAY * CYCLES_PER_US) static void sram_power(int on) { @@ -485,10 +458,9 @@ static void sram_power(int on) erase_cfg = (((bank_size - 4) >> 2) << 2) | 0x1; for (i = 0; i < SRAM_POWER_OFF_BANKS; i++) { - - if (on && (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) - && BANK_DISABLE_STATUS(i)))) { - + if (on && + (BANK_PG_STATUS(i) || (!IS_ENABLED(CONFIG_ISH_NEW_PM) && + BANK_DISABLE_STATUS(i)))) { /* power on and enable a bank */ BANK_PG_DISABLE(i); @@ -519,13 +491,12 @@ static void sram_power(int on) * booting ISH */ ISH_SRAM_CTRL_INTR = 0xFFFFFFFF; - } } #define RTC_TICKS_IN_SECOND 32768 -static __maybe_unused uint64_t get_rtc(void) +static __maybe_unused uint64_t get_rtc(void) { uint32_t lower; uint32_t upper; @@ -645,8 +616,7 @@ static void handle_d0i2(void) } /* set main SRAM into retention mode*/ - PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT - | PMU_LDO_RETENTION_BIT; + PMU_LDO_CTRL = PMU_LDO_ENABLE_BIT | PMU_LDO_RETENTION_BIT; /* delay some cycles before halt */ delay(SRAM_RETENTION_CYCLES_DELAY); @@ -670,7 +640,8 @@ static void handle_d0i2(void) clear_vnnred_aoncg(); - if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) + if (IS_ENABLED(CONFIG_ISH_NEW_PM) && + (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) handle_reset(ISH_PM_STATE_RESET_PREP); /* set main SRAM intto normal mode */ @@ -728,7 +699,8 @@ static void handle_d0i3(void) clear_vnnred_aoncg(); - if (IS_ENABLED(CONFIG_ISH_NEW_PM) && (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) + if (IS_ENABLED(CONFIG_ISH_NEW_PM) && + (PMU_RST_PREP & PMU_RST_PREP_AVAIL)) handle_reset(ISH_PM_STATE_RESET_PREP); /* power on main SRAM */ @@ -809,7 +781,6 @@ static void handle_reset(enum ish_pm_state pm_state) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM) || (IPC_ISH_RMP2 & DMA_ENABLED_MASK)) { - /* clear ISH2HOST doorbell register */ *IPC_ISH2HOST_DOORBELL_ADDR = 0; @@ -834,7 +805,6 @@ static void handle_reset(enum ish_pm_state pm_state) ish_mia_halt(); } - } static void handle_unknown_state(void) @@ -847,22 +817,21 @@ static void handle_unknown_state(void) void ish_aon_main(void) { - /* set PMU wakeup interrupt gate using LDT code segment selector(0x4) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_lo = + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_up = + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); } else { - aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[0].dword_lo = + GEN_IDT_DESC_LO(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[0].dword_up = GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[0].dword_up = + GEN_IDT_DESC_UP(&pmu_wakeup_isr, 0x4, IDT_DESC_FLAGS); } if (IS_ENABLED(CONFIG_ISH_PM_RESET_PREP)) { @@ -871,39 +840,34 @@ void ish_aon_main(void) * selector(0x4) */ if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - aon_idt[0].dword_lo = GEN_IDT_DESC_LO(&reset_prep_isr, - 0x4, IDT_DESC_FLAGS); + aon_idt[0].dword_lo = GEN_IDT_DESC_LO( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); - aon_idt[0].dword_up = GEN_IDT_DESC_UP(&reset_prep_isr, - 0x4, IDT_DESC_FLAGS); + aon_idt[0].dword_up = GEN_IDT_DESC_UP( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); } else { - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_lo = - GEN_IDT_DESC_LO(&reset_prep_isr, 0x4, - IDT_DESC_FLAGS); - - aon_idt[AON_IDT_ENTRY_VEC_LAST - - AON_IDT_ENTRY_VEC_FIRST].dword_up = - GEN_IDT_DESC_UP(&reset_prep_isr, 0x4, - IDT_DESC_FLAGS); + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_lo = GEN_IDT_DESC_LO( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); + + aon_idt[AON_IDT_ENTRY_VEC_LAST - AON_IDT_ENTRY_VEC_FIRST] + .dword_up = GEN_IDT_DESC_UP( + &reset_prep_isr, 0x4, IDT_DESC_FLAGS); } } while (1) { - /** * will start to run from here when switched to aontask from * the second time */ /* save main FW's IDT and load aontask's IDT */ - __asm__ volatile ( - "sidtl %0;\n" - "lidtl %1;\n" - : - : "m" (aon_share.main_fw_idt_hdr), - "m" (aon_idt_hdr) - ); + __asm__ volatile("sidtl %0;\n" + "lidtl %1;\n" + : + : "m"(aon_share.main_fw_idt_hdr), + "m"(aon_idt_hdr)); aon_share.last_error = AON_SUCCESS; @@ -934,11 +898,9 @@ void ish_aon_main(void) } /* restore main FW's IDT and switch back to main FW */ - __asm__ volatile( - "lidtl %0;\n" - : - : "m" (aon_share.main_fw_idt_hdr) - ); + __asm__ volatile("lidtl %0;\n" + : + : "m"(aon_share.main_fw_idt_hdr)); if (IS_ENABLED(CONFIG_ISH_IPAPG) && aon_share.pg_exit) { mainfw_gdt.entries[tr / sizeof(struct gdt_entry)] @@ -946,6 +908,6 @@ void ish_aon_main(void) pg_exit_restore_ctx(); } - __asm__ volatile ("iret;"); + __asm__ volatile("iret;"); } } -- cgit v1.2.1 From f75b2aaed044fcb0900302a1a977b415d1a95341 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:26 -0600 Subject: board/stm32l476g-eval/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c2e515ec7dbf82aa8e17882419b02e764654c4b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728956 Reviewed-by: Jeremy Bettis --- board/stm32l476g-eval/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/stm32l476g-eval/board.h b/board/stm32l476g-eval/board.h index e8ce99845f..95582284df 100644 --- a/board/stm32l476g-eval/board.h +++ b/board/stm32l476g-eval/board.h @@ -10,8 +10,8 @@ #ifdef CTS_MODULE /* CTS tests are small. We can use smaller size to expedite flash time. */ -#undef CONFIG_FLASH_SIZE_BYTES -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256k */ +#undef CONFIG_FLASH_SIZE_BYTES +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256k */ #endif /* Optional features */ @@ -54,18 +54,18 @@ #undef CONFIG_FLASH_PHYSICAL /* Timer selection */ -#define TIM_CLOCK32 5 +#define TIM_CLOCK32 5 /* External clock speeds (8 MHz) */ #define STM32_HSE_CLOCK 8000000 /* PLL configuration. Freq = STM32_HSE_CLOCK * n/m/r */ #undef STM32_PLLM -#define STM32_PLLM 1 +#define STM32_PLLM 1 #undef STM32_PLLN -#define STM32_PLLN 10 +#define STM32_PLLN 10 #undef STM32_PLLR -#define STM32_PLLR 2 +#define STM32_PLLR 2 #include "gpio_signal.h" -- cgit v1.2.1 From ecae9d01b50c3b0692802b96fdbf5a6298316009 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:55 -0600 Subject: chip/stm32/usb_isochronous.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9720cb153d869f6b05323fd15ecfc76f477e90d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729557 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_isochronous.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/chip/stm32/usb_isochronous.c b/chip/stm32/usb_isochronous.c index 792507aa75..32ed1af3e3 100644 --- a/chip/stm32/usb_isochronous.c +++ b/chip/stm32/usb_isochronous.c @@ -13,10 +13,9 @@ #include "usb_hw.h" #include "usb_isochronous.h" - /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) /* * Currently, we only support TX direction for USB isochronous transfer. @@ -65,8 +64,7 @@ static usb_uint *get_app_addr(struct usb_isochronous_config const *config, * Sets number of bytes written to application buffer. */ static void set_app_count(struct usb_isochronous_config const *config, - int dtog_value, - usb_uint count) + int dtog_value, usb_uint count) { if (dtog_value) btable_ep[config->endpoint].tx_count = count; @@ -74,13 +72,9 @@ static void set_app_count(struct usb_isochronous_config const *config, btable_ep[config->endpoint].rx_count = count; } -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit) +int usb_isochronous_write_buffer(struct usb_isochronous_config const *config, + const uint8_t *src, size_t n, + size_t dst_offset, int *buffer_id, int commit) { int dtog_value = get_tx_dtog(config); usb_uint *buffer = get_app_addr(config, dtog_value); @@ -142,15 +136,13 @@ void usb_isochronous_tx(struct usb_isochronous_config const *config) } int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx) + usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx) { int ret = -1; - if (ep0_buf_rx[0] == (USB_DIR_OUT | - USB_TYPE_STANDARD | - USB_RECIP_INTERFACE | - USB_REQ_SET_INTERFACE << 8)) { + if (ep0_buf_rx[0] == + (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE | + USB_REQ_SET_INTERFACE << 8)) { ret = config->set_interface(ep0_buf_rx[1], ep0_buf_rx[2]); if (ret == 0) { -- cgit v1.2.1 From 2447f419af9ea3c3c18456fb3654b20ca6860290 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:52 -0600 Subject: driver/accelgyro_lsm6ds0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d771c725047970ace0da8c82a3a3a4a98298503 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729921 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6ds0.c | 118 +++++++++++++++++++-------------------------- 1 file changed, 49 insertions(+), 69 deletions(-) diff --git a/driver/accelgyro_lsm6ds0.c b/driver/accelgyro_lsm6ds0.c index beee41b815..c9d0dadbed 100644 --- a/driver/accelgyro_lsm6ds0.c +++ b/driver/accelgyro_lsm6ds0.c @@ -19,8 +19,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /* * Struct for pairing an engineering value with the register value for a @@ -32,25 +32,21 @@ struct accel_param_pair { }; /* List of range values in +/-G's and their associated register values. */ -static const struct accel_param_pair g_ranges[] = { - {2, LSM6DS0_GSEL_2G}, - {4, LSM6DS0_GSEL_4G}, - {8, LSM6DS0_GSEL_8G} -}; +static const struct accel_param_pair g_ranges[] = { { 2, LSM6DS0_GSEL_2G }, + { 4, LSM6DS0_GSEL_4G }, + { 8, LSM6DS0_GSEL_8G } }; /* * List of angular rate range values in +/-dps's * and their associated register values. */ -const struct accel_param_pair dps_ranges[] = { - {245, LSM6DS0_DPS_SEL_245}, - {500, LSM6DS0_DPS_SEL_500}, - {1000, LSM6DS0_DPS_SEL_1000}, - {2000, LSM6DS0_DPS_SEL_2000} -}; +const struct accel_param_pair dps_ranges[] = { { 245, LSM6DS0_DPS_SEL_245 }, + { 500, LSM6DS0_DPS_SEL_500 }, + { 1000, LSM6DS0_DPS_SEL_1000 }, + { 2000, LSM6DS0_DPS_SEL_2000 } }; -static inline const struct accel_param_pair *get_range_table( - enum motionsensor_type type, int *psize) +static inline const struct accel_param_pair * +get_range_table(enum motionsensor_type type, int *psize) { if (MOTIONSENSE_TYPE_ACCEL == type) { if (psize) @@ -65,28 +61,22 @@ static inline const struct accel_param_pair *get_range_table( /* List of ODR (gyro off) values in mHz and their associated register values.*/ const struct accel_param_pair gyro_on_odr[] = { - {0, LSM6DS0_ODR_PD}, - {15000, LSM6DS0_ODR_15HZ}, - {59000, LSM6DS0_ODR_59HZ}, - {119000, LSM6DS0_ODR_119HZ}, - {238000, LSM6DS0_ODR_238HZ}, - {476000, LSM6DS0_ODR_476HZ}, - {952000, LSM6DS0_ODR_952HZ} + { 0, LSM6DS0_ODR_PD }, { 15000, LSM6DS0_ODR_15HZ }, + { 59000, LSM6DS0_ODR_59HZ }, { 119000, LSM6DS0_ODR_119HZ }, + { 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ }, + { 952000, LSM6DS0_ODR_952HZ } }; /* List of ODR (gyro on) values in mHz and their associated register values. */ const struct accel_param_pair gyro_off_odr[] = { - {0, LSM6DS0_ODR_PD}, - {10000, LSM6DS0_ODR_10HZ}, - {50000, LSM6DS0_ODR_50HZ}, - {119000, LSM6DS0_ODR_119HZ}, - {238000, LSM6DS0_ODR_238HZ}, - {476000, LSM6DS0_ODR_476HZ}, - {952000, LSM6DS0_ODR_952HZ} + { 0, LSM6DS0_ODR_PD }, { 10000, LSM6DS0_ODR_10HZ }, + { 50000, LSM6DS0_ODR_50HZ }, { 119000, LSM6DS0_ODR_119HZ }, + { 238000, LSM6DS0_ODR_238HZ }, { 476000, LSM6DS0_ODR_476HZ }, + { 952000, LSM6DS0_ODR_952HZ } }; -static inline const struct accel_param_pair *get_odr_table( - enum motionsensor_type type, int *psize) +static inline const struct accel_param_pair * +get_odr_table(enum motionsensor_type type, int *psize) { if (MOTIONSENSE_TYPE_ACCEL == type) { if (psize) @@ -101,14 +91,14 @@ static inline const struct accel_param_pair *get_odr_table( static inline int get_ctrl_reg(enum motionsensor_type type) { - return (MOTIONSENSE_TYPE_ACCEL == type) ? - LSM6DS0_CTRL_REG6_XL : LSM6DS0_CTRL_REG1_G; + return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_CTRL_REG6_XL : + LSM6DS0_CTRL_REG1_G; } static inline int get_xyz_reg(enum motionsensor_type type) { - return (MOTIONSENSE_TYPE_ACCEL == type) ? - LSM6DS0_OUT_X_L_XL : LSM6DS0_OUT_X_L_G; + return (MOTIONSENSE_TYPE_ACCEL == type) ? LSM6DS0_OUT_X_L_XL : + LSM6DS0_OUT_X_L_G; } /** @@ -118,14 +108,14 @@ static inline int get_xyz_reg(enum motionsensor_type type) * outside the range of values, it returns the closest valid reg value. */ static int get_reg_val(const int eng_val, const int round_up, - const struct accel_param_pair *pairs, const int size) + const struct accel_param_pair *pairs, const int size) { int i; for (i = 0; i < size - 1; i++) { if (eng_val <= pairs[i].val) break; - if (eng_val < pairs[i+1].val) { + if (eng_val < pairs[i + 1].val) { if (round_up) i += 1; break; @@ -138,7 +128,8 @@ static int get_reg_val(const int eng_val, const int round_up, * @return engineering value that matches the given reg val */ static int get_engineering_val(const int reg_val, - const struct accel_param_pair *pairs, const int size) + const struct accel_param_pair *pairs, + const int size) { int i; for (i = 0; i < size; i++) { @@ -166,9 +157,7 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags, return i2c_write8(port, i2c_addr_flags, reg, data); } -static int set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int set_range(struct motion_sensor_t *s, int range, int rnd) { int ret, ctrl_val, range_tbl_size; uint8_t ctrl_reg, reg_val; @@ -185,19 +174,17 @@ static int set_range(struct motion_sensor_t *s, */ mutex_lock(s->mutex); - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - ctrl_reg, &ctrl_val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, ctrl_reg, &ctrl_val); if (ret != EC_SUCCESS) goto accel_cleanup; ctrl_val = (ctrl_val & ~LSM6DS0_RANGE_MASK) | reg_val; - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - ctrl_reg, ctrl_val); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, ctrl_val); /* Now that we have set the range, update the driver's value. */ if (ret == EC_SUCCESS) - s->current_range = get_engineering_val(reg_val, ranges, - range_tbl_size); + s->current_range = + get_engineering_val(reg_val, ranges, range_tbl_size); accel_cleanup: mutex_unlock(s->mutex); @@ -209,9 +196,7 @@ static int get_resolution(const struct motion_sensor_t *s) return LSM6DS0_RESOLUTION; } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, - int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { int ret, val, odr_tbl_size; uint8_t ctrl_reg, reg_val; @@ -237,8 +222,8 @@ static int set_data_rate(const struct motion_sensor_t *s, /* Now that we have set the odr, update the driver's value. */ if (ret == EC_SUCCESS) - data->base.odr = get_engineering_val(reg_val, data_rates, - odr_tbl_size); + data->base.odr = + get_engineering_val(reg_val, data_rates, odr_tbl_size); /* CTRL_REG3_G 12h * [7] low-power mode = 0; @@ -254,8 +239,8 @@ static int set_data_rate(const struct motion_sensor_t *s, goto accel_cleanup; val &= ~(0x3 << 4); /* clear bit [5:4] */ val = (rate > 119000) ? - (val | (1<<7)) /* set high-power mode */ : - (val & ~(1<<7)); /* set low-power mode */ + (val | (1 << 7)) /* set high-power mode */ : + (val & ~(1 << 7)); /* set low-power mode */ ret = raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DS0_CTRL_REG3_G, val); } @@ -272,9 +257,8 @@ static int get_data_rate(const struct motion_sensor_t *s) return data->base.odr; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { /* temperature is ignored */ struct lsm6ds0_data *data = s->drv_data; @@ -284,9 +268,8 @@ static int set_offset(const struct motion_sensor_t *s, return EC_SUCCESS; } -static int get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) +static int get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct lsm6ds0_data *data = s->drv_data; offset[X] = data->offset[X]; @@ -300,8 +283,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DS0_STATUS_REG, &tmp); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RS Error", s->name, s->type); @@ -341,12 +324,10 @@ static int read(const struct motion_sensor_t *s, intv3_t v) xyz_reg = get_xyz_reg(s->type); /* Read 6 bytes starting at xyz_reg */ - ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, - xyz_reg, raw, 6); + ret = i2c_read_block(s->port, s->i2c_spi_addr_flags, xyz_reg, raw, 6); if (ret != EC_SUCCESS) { - CPRINTS("%s type:0x%X RD XYZ Error", - s->name, s->type); + CPRINTS("%s type:0x%X RD XYZ Error", s->name, s->type); return ret; } @@ -366,8 +347,8 @@ static int init(struct motion_sensor_t *s) { int ret = 0, tmp; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DS0_WHO_AM_I_REG, &tmp); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_WHO_AM_I_REG, + &tmp); if (ret) return EC_ERROR_UNKNOWN; @@ -387,7 +368,6 @@ static int init(struct motion_sensor_t *s) * SW_RESET is down for accel only! */ if (MOTIONSENSE_TYPE_ACCEL == s->type) { - mutex_lock(s->mutex); ret = raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DS0_CTRL_REG8, &tmp); -- cgit v1.2.1 From f422d3193b3e7f9bee3b198c3ee51635bc448893 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:43 -0600 Subject: board/vell/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaed36ceb9695acab152b32aec255346c17f79614 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729052 Reviewed-by: Jeremy Bettis --- board/vell/charger.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/board/vell/charger.c b/board/vell/charger.c index 0b35b7ba29..233c06a75d 100644 --- a/board/vell/charger.c +++ b/board/vell/charger.c @@ -16,9 +16,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -82,17 +81,16 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 96% negotiated limit, * to account for the charger chip margin. */ charge_ma = charge_ma * 96 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } static void set_ac_prochot(void) -- cgit v1.2.1 From 1c1f6d66f1f1f5a6cf8ee55d0a321d8d943cdf8a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:34 -0600 Subject: common/panic_output.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc32e5d4099bb59319cbca01ecc8324856fd2e43 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729681 Reviewed-by: Jeremy Bettis --- common/panic_output.c | 54 +++++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/common/panic_output.c b/common/panic_output.c index 45fd1f732a..bba4a82f46 100644 --- a/common/panic_output.c +++ b/common/panic_output.c @@ -30,17 +30,13 @@ static struct panic_data zephyr_panic_data; #define CONFIG_PANIC_DATA_BASE (&zephyr_panic_data) #endif /* Panic data goes at the end of RAM. */ -static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; +static struct panic_data *const pdata_ptr = PANIC_DATA_PTR; /* Common SW Panic reasons strings */ -const char * const panic_sw_reasons[] = { +const char *const panic_sw_reasons[] = { #ifdef CONFIG_SOFTWARE_PANIC - "PANIC_SW_DIV_ZERO", - "PANIC_SW_STACK_OVERFLOW", - "PANIC_SW_PD_CRASH", - "PANIC_SW_ASSERT", - "PANIC_SW_WATCHDOG", - "PANIC_SW_RNG", + "PANIC_SW_DIV_ZERO", "PANIC_SW_STACK_OVERFLOW", "PANIC_SW_PD_CRASH", + "PANIC_SW_ASSERT", "PANIC_SW_WATCHDOG", "PANIC_SW_RNG", "PANIC_SW_PMIC_FAULT", #endif }; @@ -52,8 +48,7 @@ const char * const panic_sw_reasons[] = { */ int panic_sw_reason_is_valid(uint32_t reason) { - return (IS_ENABLED(CONFIG_SOFTWARE_PANIC) && - reason >= PANIC_SW_BASE && + return (IS_ENABLED(CONFIG_SOFTWARE_PANIC) && reason >= PANIC_SW_BASE && (reason - PANIC_SW_BASE) < ARRAY_SIZE(panic_sw_reasons)); } @@ -143,8 +138,8 @@ void panic_assert_fail(const char *fname, int linenum) void panic_assert_fail(const char *msg, const char *func, const char *fname, int linenum) { - panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n", - msg, func, fname, linenum); + panic_printf("\nASSERTION FAILURE '%s' in %s() at %s:%d\n", msg, func, + fname, linenum); complete_panic(linenum); } #endif @@ -179,9 +174,8 @@ uintptr_t get_panic_data_start(void) if (IS_ENABLED(CONFIG_BOARD_NATIVE_POSIX)) return (uintptr_t)pdata_ptr; - return ((uintptr_t)CONFIG_PANIC_DATA_BASE - + CONFIG_PANIC_DATA_SIZE - - pdata_ptr->struct_size); + return ((uintptr_t)CONFIG_PANIC_DATA_BASE + CONFIG_PANIC_DATA_SIZE - + pdata_ptr->struct_size); } static uint32_t get_panic_data_size(void) @@ -212,7 +206,7 @@ struct panic_data *get_panic_data_write(void) * and magic is safe because it is always placed at the * end of RAM. */ - struct panic_data * const pdata_ptr = PANIC_DATA_PTR; + struct panic_data *const pdata_ptr = PANIC_DATA_PTR; const struct jump_data *jdata_ptr; uintptr_t data_begin; size_t move_size; @@ -249,8 +243,8 @@ struct panic_data *get_panic_data_write(void) * anything and can just return pdata_ptr (clear memory, set magic * and struct_size first). */ - if (jdata_ptr->magic != JUMP_DATA_MAGIC || - jdata_ptr->version < 1 || jdata_ptr->version > 3) { + if (jdata_ptr->magic != JUMP_DATA_MAGIC || jdata_ptr->version < 1 || + jdata_ptr->version > 3) { memset(pdata_ptr, 0, CONFIG_PANIC_DATA_SIZE); pdata_ptr->magic = PANIC_DATA_MAGIC; pdata_ptr->struct_size = CONFIG_PANIC_DATA_SIZE; @@ -273,7 +267,8 @@ struct panic_data *get_panic_data_write(void) if (move_size != 0) { /* Move jump_tags and jump_data */ - memmove((void *)(data_begin - delta), (void *)data_begin, move_size); + memmove((void *)(data_begin - delta), (void *)data_begin, + move_size); } /* @@ -322,7 +317,7 @@ static void stack_overflow_recurse(int n) */ msleep(10); - stack_overflow_recurse(n+1); + stack_overflow_recurse(n + 1); /* * Do work after the recursion, or else the compiler uses tail-chaining @@ -382,22 +377,23 @@ static int command_crash(int argc, char **argv) return EC_ERROR_UNKNOWN; } DECLARE_CONSOLE_COMMAND(crash, command_crash, - "[assert | divzero | udivzero" + "[assert | divzero | udivzero" #ifdef CONFIG_CMD_STACKOVERFLOW " | stack" #endif " | unaligned | watchdog | hang]", - "Crash the system (for testing)"); + "Crash the system (for testing)"); #endif /* CONFIG_CMD_CRASH */ static int command_panicinfo(int argc, char **argv) { - struct panic_data * const pdata_ptr = panic_get_data(); + struct panic_data *const pdata_ptr = panic_get_data(); if (pdata_ptr) { ccprintf("Saved panic data:%s\n", (pdata_ptr->flags & PANIC_DATA_FLAG_OLD_CONSOLE ? - "" : " (NEW)")); + "" : + " (NEW)")); panic_data_print(pdata_ptr); @@ -405,12 +401,11 @@ static int command_panicinfo(int argc, char **argv) pdata_ptr->flags |= PANIC_DATA_FLAG_OLD_CONSOLE; } else { ccprintf("No saved panic data available " - "or panic data can't be safely interpreted.\n"); + "or panic data can't be safely interpreted.\n"); } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo, - NULL, +DECLARE_CONSOLE_COMMAND(panicinfo, command_panicinfo, NULL, "Print info from a previous panic"); /*****************************************************************************/ @@ -421,7 +416,7 @@ host_command_panic_info(struct host_cmd_handler_args *args) { uint32_t pdata_size = get_panic_data_size(); uintptr_t pdata_start = get_panic_data_start(); - struct panic_data * pdata; + struct panic_data *pdata; if (pdata_start && pdata_size > 0) { ASSERT(pdata_size <= args->response_max); @@ -437,6 +432,5 @@ host_command_panic_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO, - host_command_panic_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PANIC_INFO, host_command_panic_info, EC_VER_MASK(0)); -- cgit v1.2.1 From 3b76fe0edbc458efe9c2ebf20a499f4324e4f43d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:54 -0600 Subject: include/bluetooth_le_ll.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b43fbb695e4dcffa372da533c63c35e822be1c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730213 Reviewed-by: Jeremy Bettis --- include/bluetooth_le_ll.h | 134 ++++++++++++++++++++++------------------------ 1 file changed, 65 insertions(+), 69 deletions(-) diff --git a/include/bluetooth_le_ll.h b/include/bluetooth_le_ll.h index 9f540102da..018a7d3fe0 100644 --- a/include/bluetooth_le_ll.h +++ b/include/bluetooth_le_ll.h @@ -17,33 +17,30 @@ enum ll_state_t { TEST_TX, }; -#define LL_ADV_INTERVAL_UNIT_US 625 -#define LL_ADV_TIMEOUT_UNIT_US 1000000 +#define LL_ADV_INTERVAL_UNIT_US 625 +#define LL_ADV_TIMEOUT_UNIT_US 1000000 -#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */ -#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */ +#define LL_ADV_DIRECT_INTERVAL_US 3750 /* 3.75 ms */ +#define LL_ADV_DIRECT_TIMEOUT_US 1280000 /* 1.28 s */ -#define LL_MAX_DATA_PACKET_LENGTH 27 -#define LL_MAX_DATA_PACKETS 4 +#define LL_MAX_DATA_PACKET_LENGTH 27 +#define LL_MAX_DATA_PACKETS 4 /* BTLE Spec 4.0: Vol 6, Part B, Section 4.5.3 */ -#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250 +#define TRANSMIT_WINDOW_OFFSET_CONSTANT 1250 -#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS) +#define LL_MAX_BUFFER_SIZE (LL_MAX_DATA_PACKET_LENGTH * LL_MAX_DATA_PACKETS) -#define LL_SUPPORTED_FEATURES (HCI_LE_FTR_ENCRYPTION | \ - HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \ - HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \ - HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE) +#define LL_SUPPORTED_FEATURES \ + (HCI_LE_FTR_ENCRYPTION | HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST | \ + HCI_LE_FTR_EXTENDED_REJECT_INDICATION | \ + HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE) -#define LL_SUPPORTED_STATES (HCI_LE_STATE_NONCON_ADV | \ - HCI_LE_STATE_SCANNABLE_ADV | \ - HCI_LE_STATE_CONNECTABLE_ADV | \ - HCI_LE_STATE_DIRECT_ADV | \ - HCI_LE_STATE_PASSIVE_SCAN | \ - HCI_LE_STATE_ACTIVE_SCAN | \ - HCI_LE_STATE_INITIATE | \ - HCI_LE_STATE_SLAVE) +#define LL_SUPPORTED_STATES \ + (HCI_LE_STATE_NONCON_ADV | HCI_LE_STATE_SCANNABLE_ADV | \ + HCI_LE_STATE_CONNECTABLE_ADV | HCI_LE_STATE_DIRECT_ADV | \ + HCI_LE_STATE_PASSIVE_SCAN | HCI_LE_STATE_ACTIVE_SCAN | \ + HCI_LE_STATE_INITIATE | HCI_LE_STATE_SLAVE) /* * 4.6.1 LE Encryption @@ -60,64 +57,63 @@ enum ll_state_t { */ /*Link Layer Control PDU Opcodes */ -#define LL_CONNECTION_UPDATE_REQ 0x00 -#define LL_CHANNEL_MAP_REQ 0x01 -#define LL_TERMINATE_IND 0x02 -#define LL_ENC_REQ 0x03 -#define LL_ENC_RSP 0x04 -#define LL_START_ENC_REQ 0x05 -#define LL_START_ENC_RSP 0x06 -#define LL_UNKNOWN_RSP 0x07 -#define LL_FEATURE_REQ 0x08 -#define LL_FEATURE_RSP 0x09 -#define LL_PAUSE_ENC_REQ 0x0A -#define LL_PAUSE_ENC_RSP 0x0B -#define LL_VERSION_IND 0x0C -#define LL_REJECT_IND 0x0D -#define LL_SLAVE_FEATURE_REQ 0x0E -#define LL_CONNECTION_PARAM_REQ 0x0F -#define LL_CONNECTION_PARAM_RSP 0x10 -#define LL_REJECT_IND_EXT 0x11 -#define LL_PING_REQ 0x12 -#define LL_PING_RSP 0x13 +#define LL_CONNECTION_UPDATE_REQ 0x00 +#define LL_CHANNEL_MAP_REQ 0x01 +#define LL_TERMINATE_IND 0x02 +#define LL_ENC_REQ 0x03 +#define LL_ENC_RSP 0x04 +#define LL_START_ENC_REQ 0x05 +#define LL_START_ENC_RSP 0x06 +#define LL_UNKNOWN_RSP 0x07 +#define LL_FEATURE_REQ 0x08 +#define LL_FEATURE_RSP 0x09 +#define LL_PAUSE_ENC_REQ 0x0A +#define LL_PAUSE_ENC_RSP 0x0B +#define LL_VERSION_IND 0x0C +#define LL_REJECT_IND 0x0D +#define LL_SLAVE_FEATURE_REQ 0x0E +#define LL_CONNECTION_PARAM_REQ 0x0F +#define LL_CONNECTION_PARAM_RSP 0x10 +#define LL_REJECT_IND_EXT 0x11 +#define LL_PING_REQ 0x12 +#define LL_PING_RSP 0x13 /* BLE 4.1 Vol 6 2.3.3.1 Connection information */ -#define CONNECT_REQ_INITA_LEN 6 -#define CONNECT_REQ_ADVA_LEN 6 -#define CONNECT_REQ_ACCESS_ADDR_LEN 4 -#define CONNECT_REQ_CRC_INIT_VAL_LEN 3 -#define CONNECT_REQ_WIN_SIZE_LEN 1 -#define CONNECT_REQ_WIN_OFFSET_LEN 2 -#define CONNECT_REQ_INTERVAL_LEN 2 -#define CONNECT_REQ_LATENCY_LEN 2 -#define CONNECT_REQ_TIMEOUT_LEN 2 -#define CONNECT_REQ_CHANNEL_MAP_LEN 5 -#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1 +#define CONNECT_REQ_INITA_LEN 6 +#define CONNECT_REQ_ADVA_LEN 6 +#define CONNECT_REQ_ACCESS_ADDR_LEN 4 +#define CONNECT_REQ_CRC_INIT_VAL_LEN 3 +#define CONNECT_REQ_WIN_SIZE_LEN 1 +#define CONNECT_REQ_WIN_OFFSET_LEN 2 +#define CONNECT_REQ_INTERVAL_LEN 2 +#define CONNECT_REQ_LATENCY_LEN 2 +#define CONNECT_REQ_TIMEOUT_LEN 2 +#define CONNECT_REQ_CHANNEL_MAP_LEN 5 +#define CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN 1 struct ble_connection_params { - uint8_t init_a[CONNECT_REQ_INITA_LEN]; - uint8_t adv_a[CONNECT_REQ_ADVA_LEN]; - uint32_t access_addr; - uint32_t crc_init_val; - uint8_t win_size; - uint16_t win_offset; - uint16_t interval; - uint16_t latency; - uint16_t timeout; - uint64_t channel_map; - uint8_t hop_increment; - uint8_t sleep_clock_accuracy; - uint32_t transmitWindowOffset; - uint32_t transmitWindowSize; - uint32_t connInterval; - uint16_t connLatency; - uint32_t connSupervisionTimeout; + uint8_t init_a[CONNECT_REQ_INITA_LEN]; + uint8_t adv_a[CONNECT_REQ_ADVA_LEN]; + uint32_t access_addr; + uint32_t crc_init_val; + uint8_t win_size; + uint16_t win_offset; + uint16_t interval; + uint16_t latency; + uint16_t timeout; + uint64_t channel_map; + uint8_t hop_increment; + uint8_t sleep_clock_accuracy; + uint32_t transmitWindowOffset; + uint32_t transmitWindowSize; + uint32_t connInterval; + uint16_t connLatency; + uint32_t connSupervisionTimeout; }; uint8_t ll_reset(void); uint8_t ll_set_tx_power(uint8_t *params); - /* LE Information */ uint8_t ll_read_buffer_size(uint8_t *return_params); uint8_t ll_read_local_supported_features(uint8_t *return_params); -- cgit v1.2.1 From 24ca5e8922fe0c273dad2e3af5658b5c7846ecc5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:43 -0600 Subject: include/driver/accel_bma2x2_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic5c6a58fdb3e9eb0b9fbdc9104f304410b2e18bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730245 Reviewed-by: Jeremy Bettis --- include/driver/accel_bma2x2_public.h | 43 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/include/driver/accel_bma2x2_public.h b/include/driver/accel_bma2x2_public.h index 731fcebbc9..a7b99d88ba 100644 --- a/include/driver/accel_bma2x2_public.h +++ b/include/driver/accel_bma2x2_public.h @@ -14,27 +14,27 @@ extern const struct accelgyro_drv bma2x2_accel_drv; /* I2C ADDRESS DEFINITIONS */ /* The following definition of I2C address is used for the following sensors -* BMA253 -* BMA255 -* BMA355 -* BMA280 -* BMA282 -* BMA223 -* BMA254 -* BMA284 -* BMA250E -* BMA222E -*/ -#define BMA2x2_I2C_ADDR1_FLAGS 0x18 -#define BMA2x2_I2C_ADDR2_FLAGS 0x19 + * BMA253 + * BMA255 + * BMA355 + * BMA280 + * BMA282 + * BMA223 + * BMA254 + * BMA284 + * BMA250E + * BMA222E + */ +#define BMA2x2_I2C_ADDR1_FLAGS 0x18 +#define BMA2x2_I2C_ADDR2_FLAGS 0x19 /* The following definition of I2C address is used for the following sensors -* BMC150 -* BMC056 -* BMC156 -*/ -#define BMA2x2_I2C_ADDR3_FLAGS 0x10 -#define BMA2x2_I2C_ADDR4_FLAGS 0x11 + * BMC150 + * BMC056 + * BMC156 + */ +#define BMA2x2_I2C_ADDR3_FLAGS 0x10 +#define BMA2x2_I2C_ADDR4_FLAGS 0x11 /* * Min and Max sampling frequency in mHz. @@ -43,8 +43,7 @@ extern const struct accelgyro_drv bma2x2_accel_drv; * (see CONFIG_MOTION_MIN_SENSE_WAIT_TIME), we may read too early when * other sensors are active. */ -#define BMA255_ACCEL_MIN_FREQ 7810 -#define BMA255_ACCEL_MAX_FREQ \ - MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) +#define BMA255_ACCEL_MIN_FREQ 7810 +#define BMA255_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(125000, 15625) #endif /* CROS_EC_DRIVER_ACCEL_BMA2x2_PUBLIC_H */ -- cgit v1.2.1 From 3263e2d6beab113a6e659ad158a903ee6f9e7aac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:12 -0600 Subject: chip/ish/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3dc5a04182ae8c8a9882d0b1c461df20e6e38ef1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729174 Reviewed-by: Jeremy Bettis --- chip/ish/config_chip.h | 67 +++++++++++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 4c884d00cc..19de517099 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -15,18 +15,18 @@ #endif /* Number of IRQ vectors on the ISH */ -#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1) +#define CONFIG_IRQ_COUNT (VEC_TO_IRQ(255) + 1) /* Use a bigger console output buffer */ #undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 +#define CONFIG_UART_TX_BUF_SIZE 2048 /* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL_MS 250 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* Maximum number of deferrable functions */ -#define DEFERRABLE_MAX_COUNT 8 +#define DEFERRABLE_MAX_COUNT 8 /* this macro causes 'pause' and reduces loop counts inside loop. */ #define CPU_RELAX() asm volatile("rep; nop" ::: "memory") @@ -36,49 +36,48 @@ /*****************************************************************************/ #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_RAM_BASE 0xFF200000 +#define CONFIG_RAM_BASE 0xFF200000 #else -#define CONFIG_RAM_BASE 0xFF000000 +#define CONFIG_RAM_BASE 0xFF000000 #endif -#define CONFIG_RAM_SIZE 0x000A0000 +#define CONFIG_RAM_SIZE 0x000A0000 #ifdef CHIP_VARIANT_ISH5P4 -#define CONFIG_RAM_BANK_SIZE 0x00010000 +#define CONFIG_RAM_BANK_SIZE 0x00010000 #else -#define CONFIG_RAM_BANK_SIZE 0x00008000 +#define CONFIG_RAM_BANK_SIZE 0x00008000 #endif #if defined(CHIP_FAMILY_ISH3) /* On ISH3, there is no separate AON memory; use last 4KB of SRAM */ -#define CONFIG_AON_RAM_BASE 0xFF09F000 -#define CONFIG_AON_RAM_SIZE 0x00001000 +#define CONFIG_AON_RAM_BASE 0xFF09F000 +#define CONFIG_AON_RAM_SIZE 0x00001000 #elif defined(CHIP_FAMILY_ISH4) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00001000 +#define CONFIG_AON_RAM_BASE 0xFF800000 +#define CONFIG_AON_RAM_SIZE 0x00001000 #elif defined(CHIP_FAMILY_ISH5) -#define CONFIG_AON_RAM_BASE 0xFF800000 -#define CONFIG_AON_RAM_SIZE 0x00002000 +#define CONFIG_AON_RAM_BASE 0xFF800000 +#define CONFIG_AON_RAM_SIZE 0x00002000 #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif /* The end of the AON memory is reserved for read-only use */ -#define CONFIG_AON_PERSISTENT_SIZE 0x180 -#define CONFIG_AON_PERSISTENT_BASE (CONFIG_AON_RAM_BASE \ - + CONFIG_AON_RAM_SIZE \ - - CONFIG_AON_PERSISTENT_SIZE) +#define CONFIG_AON_PERSISTENT_SIZE 0x180 +#define CONFIG_AON_PERSISTENT_BASE \ + (CONFIG_AON_RAM_BASE + CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE) /* Store persistent panic data in AON memory. */ -#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data)) +#define CONFIG_PANIC_DATA_BASE (&(ish_persistent_data.panic_data)) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 640 -#define LARGER_TASK_STACK_SIZE 1024 -#define HUGE_TASK_STACK_SIZE 2048 +#define IDLE_TASK_STACK_SIZE 640 +#define LARGER_TASK_STACK_SIZE 1024 +#define HUGE_TASK_STACK_SIZE 2048 /* Default task stack size */ -#define TASK_STACK_SIZE 640 +#define TASK_STACK_SIZE 640 /****************************************************************************/ /* Define our flash layout. */ @@ -87,13 +86,13 @@ */ /* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00000000 +#define CONFIG_FLASH_ERASE_SIZE 0x00000000 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000000 +#define CONFIG_FLASH_WRITE_SIZE 0x00000000 /* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 #include "config_flash_layout.h" @@ -101,16 +100,16 @@ /* Watchdog Timer Configuration */ /*****************************************************************************/ #if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define WDT_CLOCK_HZ (120000000) /* 120 MHz */ +#define WDT_CLOCK_HZ (120000000) /* 120 MHz */ #elif defined(CHIP_FAMILY_ISH4) -#define WDT_CLOCK_HZ (100000000) /* 100 MHz */ +#define WDT_CLOCK_HZ (100000000) /* 100 MHz */ #else #error "CHIP_FAMILY_ISH(3|4|5) must be defined" #endif /* Provide WDT vec number to Minute-IA core implementation */ #undef CONFIG_MIA_WDT_VEC -#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC +#define CONFIG_MIA_WDT_VEC ISH_WDT_VEC /****************************************************************************/ /* Customize the build */ @@ -133,4 +132,4 @@ #define CONFIG_ISH_CLEAR_FABRIC_ERRORS #endif -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From 25e662b29c08c4d3fab0755badc2f511a11302ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:25 -0600 Subject: board/agah/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7860b5ad48db518de73d9ae4c4b6f3fab556e6b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727097 Reviewed-by: Jeremy Bettis --- board/agah/fw_config.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/agah/fw_config.h b/board/agah/fw_config.h index fe9fa24135..9507811e8d 100644 --- a/board/agah/fw_config.h +++ b/board/agah/fw_config.h @@ -21,9 +21,9 @@ enum ec_cfg_keyboard_backlight_type { union agah_cbi_fw_config { struct { - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From 1eba5b17197db2f1f8c424a92443b44716e57634 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:46 -0600 Subject: chip/it83xx/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec6c6a399b7d2c70db2207349045ce76ada039c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729216 Reviewed-by: Jeremy Bettis --- chip/it83xx/system.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index ae7fd627bf..2d6778b910 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -44,7 +44,7 @@ static int delayed_clear_reset_flags; static void clear_reset_flags(void) { if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) && - delayed_clear_reset_flags) { + delayed_clear_reset_flags) { chip_save_reset_flags(0); } } @@ -68,8 +68,12 @@ static void system_restore_panic_data_from_bram(void) } BUILD_ASSERT(BRAM_PANIC_LEN >= CONFIG_PANIC_DATA_SIZE); #else -static void system_save_panic_data_to_bram(void) {} -static void system_restore_panic_data_from_bram(void) {} +static void system_save_panic_data_to_bram(void) +{ +} +static void system_restore_panic_data_from_bram(void) +{ +} #endif static void system_reset_ec_by_gpg1(void) @@ -132,7 +136,7 @@ static void check_reset_cause(void) * we know this is the first reset. */ if (IS_ENABLED(CONFIG_BOARD_RESET_AFTER_POWER_ON) && - (flags & EC_RESET_FLAG_POWER_ON)) { + (flags & EC_RESET_FLAG_POWER_ON)) { if (flags & EC_RESET_FLAG_INITIAL_PWR) { /* Second boot, clear the flag immediately */ chip_save_reset_flags(0); @@ -146,7 +150,7 @@ static void check_reset_cause(void) * fine because we will have the correct flag anyway. */ chip_save_reset_flags(chip_read_reset_flags() | - EC_RESET_FLAG_INITIAL_PWR); + EC_RESET_FLAG_INITIAL_PWR); /* * Schedule chip_save_reset_flags(0) later. @@ -163,13 +167,13 @@ static void check_reset_cause(void) /* Clear PD contract recorded in bram if this is a power-on reset. */ if (IS_ENABLED(CONFIG_IT83XX_RESET_PD_CONTRACT_IN_BRAM) && - (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) { + (flags == (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) { for (int i = 0; i < MAX_SYSTEM_BBRAM_IDX_PD_PORTS; i++) system_set_bbram((SYSTEM_BBRAM_IDX_PD0 + i), 0); } if ((IS_ENABLED(CONFIG_IT83XX_HARD_RESET_BY_GPG1)) && - (flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) + (flags & ~(EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_RESET_PIN))) system_restore_panic_data_from_bram(); } @@ -183,7 +187,7 @@ static void system_reset_cause_is_unknown(void) * eg: Andes core (jral5: LP=PC+2, jal: LP=PC+4) */ ccprintf("===Unknown reset! jump from %x or %x===\n", - ec_reset_lp - 4, ec_reset_lp - 2); + ec_reset_lp - 4, ec_reset_lp - 2); } DECLARE_HOOK(HOOK_INIT, system_reset_cause_is_unknown, HOOK_PRIO_FIRST); @@ -239,7 +243,7 @@ void chip_pre_init(void) IT83XX_GCTRL_WMCR |= BIT(7); } -#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ +#define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ #define BRAM_VALID_MAGIC_FIELD0 (BRAM_VALID_MAGIC & 0xff) #define BRAM_VALID_MAGIC_FIELD1 ((BRAM_VALID_MAGIC >> 8) & 0xff) #define BRAM_VALID_MAGIC_FIELD2 ((BRAM_VALID_MAGIC >> 16) & 0xff) @@ -269,8 +273,8 @@ void chip_bram_valid(void) if (BRAM_EC_LOG_STATUS == EC_LOG_SAVED_IN_FLASH) { /* Restore EC logs from flash. */ memcpy((void *)__preserved_logs_start, - (const void *)CHIP_FLASH_PRESERVE_LOGS_BASE, - (uintptr_t)__preserved_logs_size); + (const void *)CHIP_FLASH_PRESERVE_LOGS_BASE, + (uintptr_t)__preserved_logs_size); } BRAM_EC_LOG_STATUS = 0; #endif @@ -279,7 +283,6 @@ void chip_bram_valid(void) void system_pre_init(void) { /* No initialization required */ - } uint32_t chip_read_reset_flags(void) @@ -313,9 +316,10 @@ void system_reset(int flags) #if defined(CONFIG_PRESERVE_LOGS) && defined(CONFIG_IT83XX_HARD_RESET_BY_GPG1) /* Saving EC logs into flash before reset. */ crec_flash_physical_erase(CHIP_FLASH_PRESERVE_LOGS_BASE, - CHIP_FLASH_PRESERVE_LOGS_SIZE); + CHIP_FLASH_PRESERVE_LOGS_SIZE); crec_flash_physical_write(CHIP_FLASH_PRESERVE_LOGS_BASE, - (uintptr_t)__preserved_logs_size, __preserved_logs_start); + (uintptr_t)__preserved_logs_size, + __preserved_logs_start); BRAM_EC_LOG_STATUS = EC_LOG_SAVED_IN_FLASH; #endif @@ -384,7 +388,7 @@ static uint32_t system_get_chip_id(void) { #ifdef IT83XX_CHIP_ID_3BYTES return (IT83XX_GCTRL_CHIPID1 << 16) | (IT83XX_GCTRL_CHIPID2 << 8) | - IT83XX_GCTRL_CHIPID3; + IT83XX_GCTRL_CHIPID3; #else return (IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2; #endif @@ -410,7 +414,7 @@ const char *system_get_chip_vendor(void) const char *system_get_chip_name(void) { - static char buf[8] = {'i', 't'}; + static char buf[8] = { 'i', 't' }; int num = (IS_ENABLED(IT83XX_CHIP_ID_3BYTES) ? 4 : 3); uint32_t chip_id = system_get_chip_id(); -- cgit v1.2.1 From 6e84ca6adeb32638e39dbfdfdbddb547f8107a5f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:54 -0600 Subject: driver/battery/bq4050.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f3e611bb01a118fc243acf2206fe2836f472deb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729930 Reviewed-by: Jeremy Bettis --- driver/battery/bq4050.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/driver/battery/bq4050.c b/driver/battery/bq4050.c index 32fc858d08..6893e2d4a6 100644 --- a/driver/battery/bq4050.c +++ b/driver/battery/bq4050.c @@ -18,9 +18,8 @@ int battery_bq4050_imbalance_mv(void) * returns a voltage for each cell, regardless of the number of cells * actually installed in the pack. Unpopulated cells read exactly zero. */ - static const uint8_t cell_voltage_address[4] = { - 0x3c, 0x3d, 0x3e, 0x3f - }; + static const uint8_t cell_voltage_address[4] = { 0x3c, 0x3d, 0x3e, + 0x3f }; int i, res, cell_voltage; int n_cells = 0; int max_voltage = 0; -- cgit v1.2.1 From 9cb8346f35ab493763eb6483e9784b43e46414c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:51 -0600 Subject: board/nipperkin/board_fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea081822cad907f86edc2a1c8c40c4154ea7d5cd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728752 Reviewed-by: Jeremy Bettis --- board/nipperkin/board_fw_config.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/nipperkin/board_fw_config.c b/board/nipperkin/board_fw_config.c index c9fa01bc7a..747158507c 100644 --- a/board/nipperkin/board_fw_config.c +++ b/board/nipperkin/board_fw_config.c @@ -9,7 +9,8 @@ bool board_has_kblight(void) { return (get_fw_config_field(FW_CONFIG_KBLIGHT_OFFSET, - FW_CONFIG_KBLIGHT_WIDTH) == FW_CONFIG_KBLIGHT_YES); + FW_CONFIG_KBLIGHT_WIDTH) == + FW_CONFIG_KBLIGHT_YES); } enum board_usb_c1_mux board_get_usb_c1_mux(void) @@ -25,6 +26,6 @@ enum board_usb_a1_retimer board_get_usb_a1_retimer(void) bool board_has_privacy_panel(void) { return (get_fw_config_field(FW_CONFIG_KEYBOARD_OFFSET, - FW_CONFIG_KEYBOARD_WIDTH) == - FW_CONFIG_KEYBOARD_PRIVACY_YES); + FW_CONFIG_KEYBOARD_WIDTH) == + FW_CONFIG_KEYBOARD_PRIVACY_YES); } -- cgit v1.2.1 From 29a166bbda77efef6ef8b4ecd2e6226ad463ce12 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:24 -0600 Subject: zephyr/shim/chip/mchp/system_download_from_flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9904ab09f9da42808908646c72c26e1059461472 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730819 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/system_download_from_flash.c | 48 +++++++++++----------- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/zephyr/shim/chip/mchp/system_download_from_flash.c b/zephyr/shim/chip/mchp/system_download_from_flash.c index 99026fe822..409f84dd4b 100644 --- a/zephyr/shim/chip/mchp/system_download_from_flash.c +++ b/zephyr/shim/chip/mchp/system_download_from_flash.c @@ -10,30 +10,28 @@ #include "system_chip.h" /* Modules Map */ -#define WDT_NODE DT_INST(0, microchip_xec_watchdog) -#define STRUCT_WDT_REG_BASE_ADDR \ - ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE))) +#define WDT_NODE DT_INST(0, microchip_xec_watchdog) +#define STRUCT_WDT_REG_BASE_ADDR ((struct wdt_regs *)(DT_REG_ADDR(WDT_NODE))) -#define PCR_NODE DT_INST(0, microchip_xec_pcr) +#define PCR_NODE DT_INST(0, microchip_xec_pcr) #define STRUCT_PCR_REG_BASE_ADDR \ - ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) + ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) -#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma) +#define QSPI_NODE DT_INST(0, microchip_xec_qmspi_ldma) #define STRUCT_QSPI_REG_BASE_ADDR \ - ((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE))) + ((struct qmspi_regs *)(DT_REG_ADDR(QSPI_NODE))) -#define SPI_READ_111 0x03 -#define SPI_READ_111_FAST 0x0b -#define SPI_READ_112_FAST 0x3b +#define SPI_READ_111 0x03 +#define SPI_READ_111_FAST 0x0b +#define SPI_READ_112_FAST 0x3b -#define QSPI_STATUS_DONE \ - (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE) +#define QSPI_STATUS_DONE (MCHP_QMSPI_STS_DONE | MCHP_QMSPI_STS_DMA_DONE) -#define QSPI_STATUS_ERR \ - (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ +#define QSPI_STATUS_ERR \ + (MCHP_QMSPI_STS_TXB_ERR | MCHP_QMSPI_STS_RXB_ERR | \ MCHP_QMSPI_STS_PROG_ERR | MCHP_QMSPI_STS_LDMA_RX_ERR) -noreturn void __keep __attribute__ ((section(".code_in_sram2"))) +noreturn void __keep __attribute__((section(".code_in_sram2"))) __start_qspi(uint32_t resetVectAddr) { struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR; @@ -79,7 +77,7 @@ uintptr_t __lfw_sram_start = CONFIG_CROS_EC_RAM_BASE + CONFIG_CROS_EC_RAM_SIZE; typedef void (*START_QSPI_IN_SRAM_FP)(uint32_t); void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t resetVectAddr) + uint32_t size, uint32_t resetVectAddr) { struct pcr_regs *pcr = STRUCT_PCR_REG_BASE_ADDR; struct qmspi_regs *qspi = STRUCT_QSPI_REG_BASE_ADDR; @@ -102,16 +100,16 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, qspi->CTRL = BIT(MCHP_QMSPI_C_DESCR_EN_POS); /* Transmit 4 bytes(opcode + 24-bit address) on IO0 */ - qspi->DESCR[0] = (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | - MCHP_QMSPI_C_XFR_UNITS_1 | - MCHP_QMSPI_C_XFR_NUNITS(4) | - MCHP_QMSPI_C_NEXT_DESCR(1)); + qspi->DESCR[0] = + (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | + MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4) | + MCHP_QMSPI_C_NEXT_DESCR(1)); /* Transmit 8 clocks with IO0 and IO1 tri-stated */ - qspi->DESCR[1] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | - MCHP_QMSPI_C_XFR_UNITS_1 | - MCHP_QMSPI_C_XFR_NUNITS(2) | - MCHP_QMSPI_C_NEXT_DESCR(2)); + qspi->DESCR[1] = + (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | + MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2) | + MCHP_QMSPI_C_NEXT_DESCR(2)); /* Read using LDMA RX Chan 0, IFM=2x, Last Descriptor, close */ qspi->DESCR[2] = (MCHP_QMSPI_C_IFM_2X | MCHP_QMSPI_C_TX_DIS | @@ -147,7 +145,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) { *((uint32_t *)__lfw_sram_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); } /* Call into SRAM routine to start QSPI */ -- cgit v1.2.1 From bfe144c2623152fe596aa2b85f1b21e14141f3f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:51 -0600 Subject: driver/accel_kionix.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6dc8db5f8d5a64c1259811bece0eb6c2def44cee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729745 Reviewed-by: Jeremy Bettis --- driver/accel_kionix.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/driver/accel_kionix.h b/driver/accel_kionix.h index 5ec83411e9..b8f84e6f2a 100644 --- a/driver/accel_kionix.h +++ b/driver/accel_kionix.h @@ -47,30 +47,26 @@ extern const struct accelgyro_drv kionix_accel_drv; * | SPI device ID | 1 | * +-------------------------------+---+ */ -#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 + \ - (v) * (KXCJ9_CTRL1 - KX022_CNTL1)) -#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 + \ - (v) * (KXCJ9_CTRL2 - KX022_CNTL2)) -#define KIONIX_ODR_REG(v) (KX022_ODCNTL + \ - (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL)) -#define KIONIX_ODR_FIELD(v) (KX022_OSA_FIELD + \ - (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD)) -#define KIONIX_PC1_FIELD(v) (KX022_CNTL1_PC1 + \ - (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1)) -#define KIONIX_RANGE_FIELD(v) (KX022_GSEL_FIELD + \ - (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD)) -#define KIONIX_RES_FIELD(v) (KX022_RES_16BIT + \ - (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT)) -#define KIONIX_RESET_FIELD(v) (KX022_CNTL2_SRST + \ - (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST)) -#define KIONIX_XOUT_L(v) (KX022_XOUT_L + \ - (v) * (KXCJ9_XOUT_L - KX022_XOUT_L)) +#define KIONIX_CTRL1_REG(v) (KX022_CNTL1 + (v) * (KXCJ9_CTRL1 - KX022_CNTL1)) +#define KIONIX_CTRL2_REG(v) (KX022_CNTL2 + (v) * (KXCJ9_CTRL2 - KX022_CNTL2)) +#define KIONIX_ODR_REG(v) \ + (KX022_ODCNTL + (v) * (KXCJ9_DATA_CTRL - KX022_ODCNTL)) +#define KIONIX_ODR_FIELD(v) \ + (KX022_OSA_FIELD + (v) * (KXCJ9_OSA_FIELD - KX022_OSA_FIELD)) +#define KIONIX_PC1_FIELD(v) \ + (KX022_CNTL1_PC1 + (v) * (KXCJ9_CTRL1_PC1 - KX022_CNTL1_PC1)) +#define KIONIX_RANGE_FIELD(v) \ + (KX022_GSEL_FIELD + (v) * (KXCJ9_GSEL_ALL - KX022_GSEL_FIELD)) +#define KIONIX_RES_FIELD(v) \ + (KX022_RES_16BIT + (v) * (KXCJ9_RES_12BIT - KX022_RES_16BIT)) +#define KIONIX_RESET_FIELD(v) \ + (KX022_CNTL2_SRST + (v) * (KXCJ9_CTRL2_SRST - KX022_CNTL2_SRST)) +#define KIONIX_XOUT_L(v) (KX022_XOUT_L + (v) * (KXCJ9_XOUT_L - KX022_XOUT_L)) -#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + \ - (v) * (KXCJ9_WHOAMI - KX022_WHOAMI)) +#define KIONIX_WHO_AM_I(v) (KX022_WHOAMI + (v) * (KXCJ9_WHOAMI - KX022_WHOAMI)) -#define KIONIX_WHO_AM_I_VAL(v) (KX022_WHO_AM_I_VAL + \ - (v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL)) +#define KIONIX_WHO_AM_I_VAL(v) \ + (KX022_WHO_AM_I_VAL + (v) * (KXCJ9_WHO_AM_I_VAL - KX022_WHO_AM_I_VAL)) #ifdef CONFIG_CMD_I2C_STRESS_TEST_ACCEL extern struct i2c_stress_test_dev kionix_i2c_stress_test_dev; -- cgit v1.2.1 From 0f5684c5f7ccce127263cb54b9ea7c4711e8ba22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:03 -0600 Subject: include/power/skylake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7474590e12b94190eb0c47123efd697f94ac454e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730389 Reviewed-by: Jeremy Bettis --- include/power/skylake.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/power/skylake.h b/include/power/skylake.h index c8a656c6c5..9d9186afd4 100644 --- a/include/power/skylake.h +++ b/include/power/skylake.h @@ -12,13 +12,13 @@ * Input state flags. * TODO: Normalize the power signal masks from board defines to SoC headers. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) /* * DPWROK is NC / stuffing option on initial boards. -- cgit v1.2.1 From 8ba4dce4b0a07a208081d37bfe88eaca661d811d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:19 -0600 Subject: board/stm32f446e-eval/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0437961704fe5ab8b0917b3b52ea7cc3f9144622 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728969 Reviewed-by: Jeremy Bettis --- board/stm32f446e-eval/board.c | 74 ++++++++++++++++++++----------------------- 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/board/stm32f446e-eval/board.c b/board/stm32f446e-eval/board.c index fd6ff8bbe2..dafc98f9e3 100644 --- a/board/stm32f446e-eval/board.c +++ b/board/stm32f446e-eval/board.c @@ -20,12 +20,12 @@ * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("stm32f446-eval"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC Shell"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("stm32f446-eval"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("EC Shell"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -43,25 +43,21 @@ struct dwc_usb usb_ctl = { /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "i2c1", - .port = I2C_PORT_0, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "fmpi2c4", - .port = FMPI2C_PORT_3, - .kbps = 100, - .scl = GPIO_FMPI2C_SCL, - .sda = GPIO_FMPI2C_SDA - }, + { .name = "i2c1", + .port = I2C_PORT_0, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "fmpi2c4", + .port = FMPI2C_PORT_3, + .kbps = 100, + .scl = GPIO_FMPI2C_SCL, + .sda = GPIO_FMPI2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -#define GPIO_SET_HS(bank, number) \ - (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2))) +#define GPIO_SET_HS(bank, number) \ + (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2))) void board_config_post_gpio_init(void) { @@ -74,27 +70,27 @@ void board_config_post_gpio_init(void) GPIO_SET_HS(A, 11); GPIO_SET_HS(A, 12); - GPIO_SET_HS(C, 3); - GPIO_SET_HS(C, 2); - GPIO_SET_HS(C, 0); - GPIO_SET_HS(A, 5); + GPIO_SET_HS(C, 3); + GPIO_SET_HS(C, 2); + GPIO_SET_HS(C, 0); + GPIO_SET_HS(A, 5); - GPIO_SET_HS(B, 5); + GPIO_SET_HS(B, 5); GPIO_SET_HS(B, 13); GPIO_SET_HS(B, 12); - GPIO_SET_HS(B, 2); + GPIO_SET_HS(B, 2); GPIO_SET_HS(B, 10); - GPIO_SET_HS(B, 1); - GPIO_SET_HS(B, 0); - GPIO_SET_HS(A, 3); + GPIO_SET_HS(B, 1); + GPIO_SET_HS(B, 0); + GPIO_SET_HS(A, 3); /* Set I2C GPIO to HS */ - GPIO_SET_HS(B, 6); - GPIO_SET_HS(B, 7); - GPIO_SET_HS(F, 1); - GPIO_SET_HS(F, 0); - GPIO_SET_HS(A, 8); - GPIO_SET_HS(B, 4); - GPIO_SET_HS(C, 6); - GPIO_SET_HS(C, 7); + GPIO_SET_HS(B, 6); + GPIO_SET_HS(B, 7); + GPIO_SET_HS(F, 1); + GPIO_SET_HS(F, 0); + GPIO_SET_HS(A, 8); + GPIO_SET_HS(B, 4); + GPIO_SET_HS(C, 6); + GPIO_SET_HS(C, 7); } -- cgit v1.2.1 From 8e7f4ae06937580e843dde4ed503eff4ef31dce1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:23 -0600 Subject: baseboard/volteer/cbi_ec_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I917fe07f2cff9cbd0326bfa19a204f117cabaf07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727951 Reviewed-by: Jeremy Bettis --- baseboard/volteer/cbi_ec_fw_config.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/baseboard/volteer/cbi_ec_fw_config.h b/baseboard/volteer/cbi_ec_fw_config.h index 0a44e1f9e4..3917dfcec1 100644 --- a/baseboard/volteer/cbi_ec_fw_config.h +++ b/baseboard/volteer/cbi_ec_fw_config.h @@ -43,23 +43,20 @@ enum ec_cfg_numeric_pad_type { NUMERIC_PAD_ENABLED = 1 }; -enum ec_cfg_keyboard_layout { - KB_LAYOUT_DEFAULT = 0, - KB_LAYOUT_1 = 1 -}; +enum ec_cfg_keyboard_layout { KB_LAYOUT_DEFAULT = 0, KB_LAYOUT_1 = 1 }; union volteer_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t thermal : 4; - uint32_t audio : 3; - enum ec_cfg_tabletmode_type tabletmode : 1; - uint32_t lte_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - enum ec_cfg_numeric_pad_type num_pad : 1; - uint32_t sd_db : 4; - enum ec_cfg_keyboard_layout kb_layout : 2; - uint32_t reserved_2 : 10; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t thermal : 4; + uint32_t audio : 3; + enum ec_cfg_tabletmode_type tabletmode : 1; + uint32_t lte_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + enum ec_cfg_numeric_pad_type num_pad : 1; + uint32_t sd_db : 4; + enum ec_cfg_keyboard_layout kb_layout : 2; + uint32_t reserved_2 : 10; }; uint32_t raw_value; }; -- cgit v1.2.1 From 6f382e255462a3cb4069111ffc6e8e6c9bb1343e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:03 -0600 Subject: board/taeko/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide425398abcd7a2d58e32d39ddb6fb85a1e82c50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728977 Reviewed-by: Jeremy Bettis --- board/taeko/battery.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/taeko/battery.c b/board/taeko/battery.c index 0fd9c9fab2..835b2a1e7b 100644 --- a/board/taeko/battery.c +++ b/board/taeko/battery.c @@ -151,7 +151,9 @@ __override bool board_battery_is_initialized(void) bool batt_initialization_state; int batt_status; - batt_initialization_state = (battery_status(&batt_status) ? false : - !!(batt_status & STATUS_INITIALIZED)); + batt_initialization_state = + (battery_status(&batt_status) ? + false : + !!(batt_status & STATUS_INITIALIZED)); return batt_initialization_state; } -- cgit v1.2.1 From bda9654738235054727b375ee84569b093c9e5f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:16 -0600 Subject: chip/ish/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic509c33706d3744ef61fccea9671a20820d868f8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729188 Reviewed-by: Jeremy Bettis --- chip/ish/system.c | 34 +++++++++++++--------------------- 1 file changed, 13 insertions(+), 21 deletions(-) diff --git a/chip/ish/system.c b/chip/ish/system.c index 30a2576e5e..0f76e17f5e 100644 --- a/chip/ish/system.c +++ b/chip/ish/system.c @@ -23,8 +23,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) int system_is_reboot_warm(void) { @@ -57,8 +57,7 @@ uint32_t chip_read_reset_flags(void) * Used when the watchdog timer exceeds max retries and we want to * disable ISH completely. */ -noreturn -static void system_halt(void) +noreturn static void system_halt(void) { cflush(); @@ -66,9 +65,8 @@ static void system_halt(void) disable_all_interrupts(); WDT_CONTROL = 0; CCU_TCG_EN = 1; - __asm__ volatile ( - "cli\n" - "hlt\n"); + __asm__ volatile("cli\n" + "hlt\n"); } } @@ -90,8 +88,8 @@ void system_reset(int flags) if (flags & SYSTEM_RESET_AP_WATCHDOG) { save_flags |= EC_RESET_FLAG_WATCHDOG; ish_persistent_data.watchdog_counter += 1; - if (ish_persistent_data.watchdog_counter - >= CONFIG_WATCHDOG_MAX_RETRIES) { + if (ish_persistent_data.watchdog_counter >= + CONFIG_WATCHDOG_MAX_RETRIES) { CPRINTS("Halting ISH due to max watchdog resets"); system_halt(); } @@ -175,19 +173,13 @@ void system_set_image_copy(enum ec_image copy) { } -#define HBW_FABRIC_BASE 0x10000000 -#define PER0_FABRIC_BASE 0x04000000 -#define AGENT_STS 0x28 -#define ERROR_LOG 0x58 +#define HBW_FABRIC_BASE 0x10000000 +#define PER0_FABRIC_BASE 0x04000000 +#define AGENT_STS 0x28 +#define ERROR_LOG 0x58 -static uint16_t hbw_ia_offset[] = { - 0x1000, - 0x3400, - 0x3800, - 0x5000, - 0x5800, - 0x6000 -}; +static uint16_t hbw_ia_offset[] = { 0x1000, 0x3400, 0x3800, + 0x5000, 0x5800, 0x6000 }; static inline void clear_register(uint32_t reg) { -- cgit v1.2.1 From ffe7b92d1c2a665383567cbd1e5d1c88a1b740db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:05 -0600 Subject: board/ambassador/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I86b3cc83f0bfd8684c58e4062b478726cbbe58d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727981 Reviewed-by: Jeremy Bettis --- board/ambassador/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/ambassador/led.c b/board/ambassador/led.c index 659a63a483..e140a393e3 100644 --- a/board/ambassador/led.c +++ b/board/ambassador/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From 76b326d38403164234c3966f1d9114fd07ad70bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:54 -0600 Subject: board/aleena/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53399fba0ecab7fbdfdb3fa3e2fa75c25c8eacb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727100 Reviewed-by: Jeremy Bettis --- board/aleena/board.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/aleena/board.h b/board/aleena/board.h index dab6f3de3a..dfca82a3cc 100644 --- a/board/aleena/board.h +++ b/board/aleena/board.h @@ -16,7 +16,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -37,7 +37,7 @@ #define CONFIG_ACCELGYRO_BMI160 #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel second source*/ #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCEL_KX022 @@ -51,17 +51,14 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) #define CONFIG_KEYBOARD_FACTORY_TEST #ifndef __ASSEMBLER__ -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; enum battery_type { BATTERY_PANASONIC, -- cgit v1.2.1 From daa8a089f5057de8de03778feb411bc830db838b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:04 -0600 Subject: board/burnet/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39ae80703892eeead36b132c8291cfe183e5aa74 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728129 Reviewed-by: Jeremy Bettis --- board/burnet/board.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/burnet/board.h b/board/burnet/board.h index 1cc103d6fc..8702502d69 100644 --- a/board/burnet/board.h +++ b/board/burnet/board.h @@ -52,9 +52,9 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ #define CONFIG_ACCEL_KX022 -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* ICM42607 Base accel/gyro */ @@ -75,20 +75,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 2 -#define I2C_PORT_CHARGER 1 -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 2 +#define I2C_PORT_CHARGER 1 +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 09f3a06909e40ac5ee0786fae6434ff0fa98e7dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:49 -0600 Subject: include/software_panic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id68a1cc62812a8ca9957cdaafcffb91bdfc629da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730406 Reviewed-by: Jeremy Bettis --- include/software_panic.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/software_panic.h b/include/software_panic.h index 2702c6dc92..6ac8701e78 100644 --- a/include/software_panic.h +++ b/include/software_panic.h @@ -9,23 +9,23 @@ #define __CROS_EC_SOFTWARE_PANIC_H /* Holds software panic reason PANIC_SW_* */ -#define SOFTWARE_PANIC_REASON_REG r4 -#define SOFTWARE_PANIC_INFO_REG r5 +#define SOFTWARE_PANIC_REASON_REG r4 +#define SOFTWARE_PANIC_INFO_REG r5 -#define PANIC_SW_BASE 0xDEAD6660 +#define PANIC_SW_BASE 0xDEAD6660 /* Software panic reasons */ -#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0) -#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1) -#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2) -#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3) -#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4) -#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5) -#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6) +#define PANIC_SW_DIV_ZERO (PANIC_SW_BASE + 0) +#define PANIC_SW_STACK_OVERFLOW (PANIC_SW_BASE + 1) +#define PANIC_SW_PD_CRASH (PANIC_SW_BASE + 2) +#define PANIC_SW_ASSERT (PANIC_SW_BASE + 3) +#define PANIC_SW_WATCHDOG (PANIC_SW_BASE + 4) +#define PANIC_SW_BAD_RNG (PANIC_SW_BASE + 5) +#define PANIC_SW_PMIC_FAULT (PANIC_SW_BASE + 6) #ifndef __ASSEMBLER__ -extern const char * const panic_sw_reasons[]; +extern const char *const panic_sw_reasons[]; extern int panic_sw_reason_is_valid(uint32_t vec); #endif -#endif /* __CROS_EC_SOFTWARE_PANIC_H */ +#endif /* __CROS_EC_SOFTWARE_PANIC_H */ -- cgit v1.2.1 From 31423602b5c810cfc7190324418d8b2857e4a50c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:35 -0600 Subject: extra/sps_errs/prog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec0464940c67062c7ac8f2df08ef7e5b2e058e8b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730185 Reviewed-by: Jeremy Bettis --- extra/sps_errs/prog.c | 62 ++++++++++++++++++--------------------------------- 1 file changed, 22 insertions(+), 40 deletions(-) diff --git a/extra/sps_errs/prog.c b/extra/sps_errs/prog.c index b649199068..d80b4418d2 100644 --- a/extra/sps_errs/prog.c +++ b/extra/sps_errs/prog.c @@ -23,7 +23,7 @@ static struct mpsse_context *mpsse; /* enum ec_status meaning */ static const char *ec_strerr(enum ec_status r) { - static const char * const strs[] = { + static const char *const strs[] = { "SUCCESS", "INVALID_COMMAND", "ERROR", @@ -48,10 +48,9 @@ static const char *ec_strerr(enum ec_status r) return ""; }; - -/**************************************************************************** - * Debugging output - */ + /**************************************************************************** + * Debugging output + */ #define LINELEN 16 @@ -65,8 +64,7 @@ static void showline(uint8_t *buf, int len) printf(" "); printf(" "); for (i = 0; i < len; i++) - printf("%c", - (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.'); + printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.'); printf("\n"); } @@ -105,8 +103,8 @@ static uint8_t txbuf[128]; * Load the output buffer with a proto v3 request (header, then data, with * checksum correct in header). */ -static size_t prepare_request(int cmd, int version, - const uint8_t *data, size_t data_len) +static size_t prepare_request(int cmd, int version, const uint8_t *data, + size_t data_len) { struct ec_host_request *request; size_t i, total_len; @@ -114,8 +112,8 @@ static size_t prepare_request(int cmd, int version, total_len = sizeof(*request) + data_len; if (total_len > sizeof(txbuf)) { - printf("Request too large (%zd > %zd)\n", - total_len, sizeof(txbuf)); + printf("Request too large (%zd > %zd)\n", total_len, + sizeof(txbuf)); return -1; } @@ -139,7 +137,6 @@ static size_t prepare_request(int cmd, int version, return total_len; } - /* Timeout flag, so we don't wait forever */ static int timedout; static void alarm_handler(int sig) @@ -151,11 +148,8 @@ static void alarm_handler(int sig) * Send command, wait for result. Return zero if communication succeeded; check * response to see if the EC liked the command. */ -static int send_cmd(int cmd, int version, - void *outbuf, - size_t outsize, - struct ec_host_response *hdr, - void *bodydest, +static int send_cmd(int cmd, int version, void *outbuf, size_t outsize, + struct ec_host_response *hdr, void *bodydest, size_t bodylen) { uint8_t *tptr, *hptr = 0, *bptr = 0; @@ -166,15 +160,13 @@ static int send_cmd(int cmd, int version, size_t bytes_left = stop_after; size_t bytes_sent = 0; - /* Load up the txbuf with the stuff to send */ len = prepare_request(cmd, version, outbuf, outsize); if (len < 0) return -1; if (MPSSE_OK != Start(mpsse)) { - fprintf(stderr, "Start failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse)); return -1; } @@ -189,8 +181,7 @@ static int send_cmd(int cmd, int version, bytes_left -= len; bytes_sent += len; if (!tptr) { - fprintf(stderr, "Transfer failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse)); goto out; } @@ -278,8 +269,7 @@ static int send_cmd(int cmd, int version, bytes_left -= len; bytes_sent += len; if (!hptr) { - fprintf(stderr, "Read failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse)); goto out; } show("Header(%d):\n", hptr, sizeof(*hdr)); @@ -288,14 +278,12 @@ static int send_cmd(int cmd, int version, /* Check the header */ if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) { printf("HEY: response version %d (should be %d)\n", - hdr->struct_version, - EC_HOST_RESPONSE_VERSION); + hdr->struct_version, EC_HOST_RESPONSE_VERSION); goto out; } if (hdr->data_len > bodylen) { - printf("HEY: response data_len %d is > %zd\n", - hdr->data_len, + printf("HEY: response data_len %d is > %zd\n", hdr->data_len, bodylen); goto out; } @@ -341,15 +329,13 @@ out: free(bptr); if (MPSSE_OK != Stop(mpsse)) { - fprintf(stderr, "Stop failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse)); return -1; } return 0; } - /****************************************************************************/ /** @@ -372,10 +358,7 @@ static int hello(void) p.in_data = 0xa5a5a5a5; expected = p.in_data + 0x01020304; - retval = send_cmd(EC_CMD_HELLO, 0, - &p, sizeof(p), - &resp, - &r, sizeof(r)); + retval = send_cmd(EC_CMD_HELLO, 0, &p, sizeof(p), &resp, &r, sizeof(r)); if (retval) { printf("Transmission error\n"); @@ -383,14 +366,13 @@ static int hello(void) } if (EC_RES_SUCCESS != resp.result) { - printf("EC result is %d: %s\n", - resp.result, ec_strerr(resp.result)); + printf("EC result is %d: %s\n", resp.result, + ec_strerr(resp.result)); return -1; } - printf("sent %08x, expected %08x, got %08x => %s\n", - p.in_data, expected, r.out_data, - expected == r.out_data ? "yay" : "boo"); + printf("sent %08x, expected %08x, got %08x => %s\n", p.in_data, + expected, r.out_data, expected == r.out_data ? "yay" : "boo"); return !(expected == r.out_data); } -- cgit v1.2.1 From b70b97769b43a04e0ef5430fe9739fad9a18305c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:15 -0600 Subject: board/kodama/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iafa9a915971f1d413b29c20c97f4e7f0e16e045a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728560 Reviewed-by: Jeremy Bettis --- board/kodama/board.c | 83 +++++++++++++++++++++++----------------------------- 1 file changed, 36 insertions(+), 47 deletions(-) diff --git a/board/kodama/board.c b/board/kodama/board.c index 2fa3ae8a3e..8ced756a83 100644 --- a/board/kodama/board.c +++ b/board/kodama/board.c @@ -40,8 +40,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -53,56 +53,50 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, - [ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, + [ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0, + STM32_AIN(6) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA, - .flags = I2C_PORT_FLAG_DYNAMIC_SPEED - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA, + .flags = I2C_PORT_FLAG_DYNAMIC_SPEED }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ @@ -122,8 +116,7 @@ struct mt6370_thermal_bound thermal_bound = { .err = 4, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -136,7 +129,6 @@ static void board_hpd_status(const struct usb_mux *me, host_set_single_event(EC_HOST_EVENT_USB_MUX); } - __override const struct rt946x_init_setting *board_rt946x_init_setting(void) { static const struct rt946x_init_setting battery_init_setting = { @@ -238,9 +230,8 @@ int extpower_is_present(void) if (board_vbus_source_enabled(CHARGE_PORT_USB_C)) usb_c_extpower_present = 0; else - usb_c_extpower_present = tcpm_check_vbus_level( - CHARGE_PORT_USB_C, - VBUS_PRESENT); + usb_c_extpower_present = + tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT); return usb_c_extpower_present; } @@ -260,11 +251,11 @@ static void board_init(void) #ifdef SECTION_IS_RW int val; - i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS, - RT946X_REG_CHGCTRL1, &val); + i2c_read8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS, RT946X_REG_CHGCTRL1, + &val); val &= RT946X_MASK_OPA_MODE; i2c_write8(I2C_PORT_CHARGER, CHARGER_I2C_ADDR_FLAGS, - RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN)); + RT946X_REG_CHGCTRL1, (val | RT946X_MASK_STAT_EN)); #endif /* If the reset cause is external, pulse PMIC force reset. */ @@ -317,7 +308,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); static void board_i2c_init(void) { if (board_get_version() < 2) - i2c_set_freq(1, I2C_FREQ_100KHZ); + i2c_set_freq(1, I2C_FREQ_100KHZ); } DECLARE_HOOK(HOOK_INIT, board_i2c_init, HOOK_PRIO_INIT_I2C); @@ -329,11 +320,9 @@ static struct mutex g_lid_mutex; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelerometer into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From f7605fcbf316e4de4078666cdb32d652dce27d34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:59 -0600 Subject: zephyr/emul/emul_flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I811a3e32401a34c14c4da50af783cb2fbcd604e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730690 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_flash.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/zephyr/emul/emul_flash.c b/zephyr/emul/emul_flash.c index 2fa88916f3..0d1b691bca 100644 --- a/zephyr/emul/emul_flash.c +++ b/zephyr/emul/emul_flash.c @@ -98,7 +98,6 @@ static int cros_flash_emul_get_status(const struct device *dev, uint8_t *sr1, return -EINVAL; } - static const struct cros_flash_driver_api emul_cros_flash_driver_api = { .init = cros_flash_emul_init, .physical_write = cros_flash_emul_write, @@ -118,17 +117,15 @@ static int flash_emul_init(const struct device *dev) return 0; } -#define FLASH_EMUL(n) \ - static struct flash_emul_data flash_emul_data_##n = { \ - }; \ - \ - static const struct flash_emul_cfg flash_emul_cfg_##n = { \ - .dev_label = DT_INST_LABEL(n), \ - .data = &flash_emul_data_##n, \ - }; \ - DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL, \ - &flash_emul_data_##n, &flash_emul_cfg_##n, \ - PRE_KERNEL_1, \ - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ +#define FLASH_EMUL(n) \ + static struct flash_emul_data flash_emul_data_##n = {}; \ + \ + static const struct flash_emul_cfg flash_emul_cfg_##n = { \ + .dev_label = DT_INST_LABEL(n), \ + .data = &flash_emul_data_##n, \ + }; \ + DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL, &flash_emul_data_##n, \ + &flash_emul_cfg_##n, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \ &emul_cros_flash_driver_api) DT_INST_FOREACH_STATUS_OKAY(FLASH_EMUL); -- cgit v1.2.1 From c156da88ff968554cd39f7793556d969ea56b9b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:29 -0600 Subject: board/npcx9_evb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id40c793a4d510e5a10315d76e2bfbf7490ebcb62 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728767 Reviewed-by: Jeremy Bettis --- board/npcx9_evb/board.c | 102 ++++++++++++++++++++++++------------------------ 1 file changed, 52 insertions(+), 50 deletions(-) diff --git a/board/npcx9_evb/board.c b/board/npcx9_evb/board.c index b412fe8b30..fd1e2276e4 100644 --- a/board/npcx9_evb/board.c +++ b/board/npcx9_evb/board.c @@ -36,25 +36,37 @@ /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_3] = {"ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_4] = {"ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_5] = {"ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_6] = {"ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_7] = {"ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_8] = {"ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_9] = {"ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_10] = {"ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_11] = {"ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_3] = { "ADC3", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_4] = { "ADC4", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_5] = { "ADC5", NPCX_ADC_CH5, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_6] = { "ADC6", NPCX_ADC_CH6, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_7] = { "ADC7", NPCX_ADC_CH7, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_8] = { "ADC8", NPCX_ADC_CH8, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_9] = { "ADC9", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_10] = { "ADC10", NPCX_ADC_CH10, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_11] = { "ADC11", NPCX_ADC_CH11, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 }, [PWM_CH_KBLIGHT] = { 2, 0, 10000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -63,7 +75,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = 0, /* Use MFT id to control fan */ + .ch = 0, /* Use MFT id to control fan */ .pgood_gpio = GPIO_PGOOD_FAN, .enable_gpio = -1, }; @@ -96,48 +108,38 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master0-0", - .port = NPCX_I2C_PORT0_0, - .kbps = 100, - .scl = GPIO_I2C0_SCL0, - .sda = GPIO_I2C0_SDA0 - }, - { - .name = "master1-0", - .port = NPCX_I2C_PORT1_0, - .kbps = 100, - .scl = GPIO_I2C1_SCL0, - .sda = GPIO_I2C1_SDA0 - }, - { - .name = "master2-0", - .port = NPCX_I2C_PORT2_0, - .kbps = 100, - .scl = GPIO_I2C2_SCL0, - .sda = GPIO_I2C2_SDA0 - }, - { - .name = "master3-0", - .port = NPCX_I2C_PORT3_0, - .kbps = 100, - .scl = GPIO_I2C3_SCL0, - .sda = GPIO_I2C3_SDA0 - }, - { - .name = "master7-0", - .port = NPCX_I2C_PORT7_0, - .kbps = 100, - .scl = GPIO_I2C7_SCL0, - .sda = GPIO_I2C7_SDA0 - }, + { .name = "master0-0", + .port = NPCX_I2C_PORT0_0, + .kbps = 100, + .scl = GPIO_I2C0_SCL0, + .sda = GPIO_I2C0_SDA0 }, + { .name = "master1-0", + .port = NPCX_I2C_PORT1_0, + .kbps = 100, + .scl = GPIO_I2C1_SCL0, + .sda = GPIO_I2C1_SDA0 }, + { .name = "master2-0", + .port = NPCX_I2C_PORT2_0, + .kbps = 100, + .scl = GPIO_I2C2_SCL0, + .sda = GPIO_I2C2_SDA0 }, + { .name = "master3-0", + .port = NPCX_I2C_PORT3_0, + .kbps = 100, + .scl = GPIO_I2C3_SCL0, + .sda = GPIO_I2C3_SDA0 }, + { .name = "master7-0", + .port = NPCX_I2C_PORT7_0, + .kbps = 100, + .scl = GPIO_I2C7_SCL0, + .sda = GPIO_I2C7_SDA0 }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From 310315b6dd66c0affab9387de74ca1256cfbeb37 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:15 -0600 Subject: zephyr/shim/include/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a84314646a9f9fa1c4ce48bb035725c5fb172df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730566 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/config_chip.h | 150 +++++++++++++++++++------------------- 1 file changed, 73 insertions(+), 77 deletions(-) diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index a498e6909e..05a927796f 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -9,9 +9,9 @@ #include #include -#define SENSOR_NODE DT_PATH(motionsense_sensor) -#define SENSOR_INFO_NODE DT_PATH(motionsense_sensor_info) -#define SENSOR_ALT_NODE DT_PATH(motionsense_sensor_alt) +#define SENSOR_NODE DT_PATH(motionsense_sensor) +#define SENSOR_INFO_NODE DT_PATH(motionsense_sensor_info) +#define SENSOR_ALT_NODE DT_PATH(motionsense_sensor_alt) /* * The battery enum is used in various drivers and these assume that it is @@ -66,14 +66,16 @@ #undef CONFIG_CONSOLE_UART /* Only used by the Chromium EC chip drivers */ #undef CONFIG_I2C_MULTI_PORT_CONTROLLER /* Not required by I2C shim */ #undef CONFIG_IRQ_COUNT /* Only used by Chromium EC core drivers */ -#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers */ +#undef CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Used by the Chromium EC chip drivers \ + */ #undef CONFIG_LTO /* Link time optimization enabled by Zephyr build system */ #undef CONFIG_STACK_SIZE /* Only used in Chromium EC core init code */ #ifndef CONFIG_FPU #undef CONFIG_FPU /* Used in Zephyr as well, enabled in Kconfig directly */ #endif #ifndef CONFIG_WATCHDOG -#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly */ +#undef CONFIG_WATCHDOG /* Used in Zephyr as well, enabled in Kconfig directly \ + */ #endif /* @@ -103,8 +105,8 @@ #endif /* EC chipset configuration */ -#define HOOK_TICK_INTERVAL CONFIG_CROS_EC_HOOK_TICK_INTERVAL -#define HOOK_TICK_INTERVAL_MS (HOOK_TICK_INTERVAL / 1000) +#define HOOK_TICK_INTERVAL CONFIG_CROS_EC_HOOK_TICK_INTERVAL +#define HOOK_TICK_INTERVAL_MS (HOOK_TICK_INTERVAL / 1000) /* Chipset and power configuration */ #ifdef CONFIG_AP_ARM_QUALCOMM_SC7180 @@ -242,7 +244,7 @@ #undef CONFIG_BATTERY_PRESENT_GPIO #ifdef CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO /* This is always GPIO_BATT_PRES_ODL with Zephyr */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BATT_PRES_ODL #endif #undef CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF @@ -283,9 +285,9 @@ #undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV #if defined(CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV) && \ - (CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0) + (CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV > 0) #define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV \ - CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV + CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV #endif #undef CONFIG_BOARD_RESET_AFTER_POWER_ON @@ -479,16 +481,16 @@ extern struct jump_data mock_jump_data; #define CONFIG_RW_MEM_OFF CONFIG_CROS_EC_RW_MEM_OFF #define CONFIG_RW_MEM_SIZE CONFIG_CROS_EC_RW_MEM_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE -#define CONFIG_RO_SIZE CONFIG_CROS_EC_RO_SIZE -#define CONFIG_RW_SIZE CONFIG_CROS_EC_RW_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_RO_SIZE CONFIG_CROS_EC_RO_SIZE +#define CONFIG_RW_SIZE CONFIG_CROS_EC_RW_SIZE /* * ROM resident area in flash used to store data objects that are not copied * into code RAM. Enable using the CONFIG_CHIP_INIT_ROM_REGION option. */ -#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE +#define CONFIG_RO_ROM_RESIDENT_MEM_OFF CONFIG_RO_SIZE #define CONFIG_RO_ROM_RESIDENT_SIZE \ (CONFIG_EC_PROTECTED_STORAGE_SIZE - CONFIG_RO_SIZE) @@ -496,7 +498,7 @@ extern struct jump_data mock_jump_data; * RW firmware in program memory - Identical to RO, only one image loaded at * a time. */ -#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE +#define CONFIG_RW_ROM_RESIDENT_MEM_OFF CONFIG_RW_SIZE #define CONFIG_RW_ROM_RESIDENT_SIZE \ (CONFIG_EC_WRITABLE_STORAGE_SIZE - CONFIG_RW_SIZE) @@ -659,7 +661,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_KEYBOARD_DISCRETE #ifdef CONFIG_PLATFORM_EC_KEYBOARD_DISCRETE #define CONFIG_KEYBOARD_DISCRETE -#define KB_DISCRETE_I2C_ADDR_FLAGS DT_REG_ADDR(DT_NODELABEL(kb_discrete)) +#define KB_DISCRETE_I2C_ADDR_FLAGS DT_REG_ADDR(DT_NODELABEL(kb_discrete)) #endif #undef CONFIG_MKBP_INPUT_DEVICES @@ -669,16 +671,16 @@ extern struct jump_data mock_jump_data; #undef CONFIG_MKBP_EVENT_WAKEUP_MASK #if defined(CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK) && \ - DT_NODE_EXISTS(DT_PATH(ec_mkbp_event_wakeup_mask)) + DT_NODE_EXISTS(DT_PATH(ec_mkbp_event_wakeup_mask)) #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - DT_PROP(DT_PATH(ec_mkbp_event_wakeup_mask), wakeup_mask) + DT_PROP(DT_PATH(ec_mkbp_event_wakeup_mask), wakeup_mask) #endif #undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK #if defined(CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK) && \ - DT_NODE_EXISTS(DT_PATH(ec_mkbp_host_event_wakeup_mask)) + DT_NODE_EXISTS(DT_PATH(ec_mkbp_host_event_wakeup_mask)) #define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - DT_PROP(DT_PATH(ec_mkbp_host_event_wakeup_mask), wakeup_mask) + DT_PROP(DT_PATH(ec_mkbp_host_event_wakeup_mask), wakeup_mask) #endif #undef CONFIG_CMD_KEYBOARD @@ -689,12 +691,12 @@ extern struct jump_data mock_jump_data; #undef CONFIG_KEYBOARD_COL2_INVERTED #ifdef CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_COL2_INVERTED -#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */ +#endif /* CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED */ #undef CONFIG_KEYBOARD_REFRESH_ROW3 #ifdef CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 #define CONFIG_KEYBOARD_REFRESH_ROW3 -#endif /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */ +#endif /* CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3 */ #undef CONFIG_KEYBOARD_KEYPAD #ifdef CONFIG_PLATFORM_EC_KEYBOARD_KEYPAD @@ -765,8 +767,7 @@ extern struct jump_data mock_jump_data; #ifdef CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR #undef CONFIG_LED_PWM_CHARGE_COLOR -#define CONFIG_LED_PWM_CHARGE_COLOR \ - CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR +#define CONFIG_LED_PWM_CHARGE_COLOR CONFIG_PLATFORM_EC_LED_PWM_CHARGE_COLOR #endif #ifdef CONFIG_PLATFORM_EC_LED_PWM_NEAR_FULL_COLOR @@ -783,8 +784,7 @@ extern struct jump_data mock_jump_data; #ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR #undef CONFIG_LED_PWM_SOC_ON_COLOR -#define CONFIG_LED_PWM_SOC_ON_COLOR \ - CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR +#define CONFIG_LED_PWM_SOC_ON_COLOR CONFIG_PLATFORM_EC_LED_PWM_SOC_ON_COLOR #endif #ifdef CONFIG_PLATFORM_EC_LED_PWM_SOC_SUSPEND_COLOR @@ -795,8 +795,7 @@ extern struct jump_data mock_jump_data; #ifdef CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR #undef CONFIG_LED_PWM_LOW_BATT_COLOR -#define CONFIG_LED_PWM_LOW_BATT_COLOR \ - CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR +#define CONFIG_LED_PWM_LOW_BATT_COLOR CONFIG_PLATFORM_EC_LED_PWM_LOW_BATT_COLOR #endif #undef CONFIG_CMD_LEDTEST @@ -812,7 +811,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_LED_ONOFF_STATES_BAT_LOW #ifdef CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW #define CONFIG_LED_ONOFF_STATES_BAT_LOW \ - CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW + CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW #endif #undef CONFIG_PWM_DISPLIGHT @@ -872,8 +871,7 @@ extern struct jump_data mock_jump_data; #endif #undef CONFIG_POWER_S0IX -#if defined(CONFIG_PLATFORM_EC_POWERSEQ_S0IX) || \ - defined(CONFIG_AP_PWRSEQ_S0IX) +#if defined(CONFIG_PLATFORM_EC_POWERSEQ_S0IX) || defined(CONFIG_AP_PWRSEQ_S0IX) #define CONFIG_POWER_S0IX #endif @@ -898,7 +896,6 @@ extern struct jump_data mock_jump_data; CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT #endif - #undef CONFIG_POWERSEQ_FAKE_CONTROL #ifdef CONFIG_PLATFORM_EC_POWERSEQ_FAKE_CONTROL #define CONFIG_POWERSEQ_FAKE_CONTROL @@ -931,19 +928,19 @@ extern struct jump_data mock_jump_data; #undef CONFIG_CMD_GETTIME #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME #define CONFIG_CMD_GETTIME -#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */ +#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_GETTIME */ #undef CONFIG_CMD_TIMERINFO #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO #define CONFIG_CMD_TIMERINFO -#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */ +#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */ #undef CONFIG_CMD_WAITMS #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_WAITMS #define CONFIG_CMD_WAITMS -#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */ +#endif /* CONFIG_PLATFORM_EC_CONSOLE_CMD_TIMERINFO */ -#endif /* CONFIG_PLATFORM_EC_TIMER */ +#endif /* CONFIG_PLATFORM_EC_TIMER */ /* USB-C things */ #ifdef CONFIG_PLATFORM_EC_USBC @@ -959,13 +956,13 @@ extern struct jump_data mock_jump_data; * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ #endif #undef CONFIG_CMD_PPC_DUMP @@ -990,8 +987,8 @@ extern struct jump_data mock_jump_data; #define CONFIG_CHARGER /* TODO: Put these charger defines in the devicetree? */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #endif @@ -1013,31 +1010,31 @@ extern struct jump_data mock_jump_data; #undef CONFIG_CHARGER_INPUT_CURRENT #ifdef CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT -#define CONFIG_CHARGER_INPUT_CURRENT CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT +#define CONFIG_CHARGER_INPUT_CURRENT CONFIG_PLATFORM_EC_CHARGER_INPUT_CURRENT #endif #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON \ - CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON + CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON #endif #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC #define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC \ - CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC + CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC #endif #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT \ - CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT + CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT #endif #undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON #ifdef CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON \ - CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON + CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON #endif #undef CONFIG_CHARGE_RAMP_SW @@ -1062,22 +1059,22 @@ extern struct jump_data mock_jump_data; #undef CONFIG_USB_PID #ifdef CONFIG_PLATFORM_EC_USB_PID -#define CONFIG_USB_PID CONFIG_PLATFORM_EC_USB_PID +#define CONFIG_USB_PID CONFIG_PLATFORM_EC_USB_PID #endif #undef CONFIG_USB_BCD_DEV #ifdef CONFIG_PLATFORM_EC_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV CONFIG_PLATFORM_EC_USB_BCD_DEV +#define CONFIG_USB_BCD_DEV CONFIG_PLATFORM_EC_USB_BCD_DEV #endif #undef CONFIG_USB_VID #ifdef CONFIG_PLATFORM_EC_USB_VID -#define CONFIG_USB_VID CONFIG_PLATFORM_EC_USB_VID +#define CONFIG_USB_VID CONFIG_PLATFORM_EC_USB_VID #endif #undef CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR #ifdef CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR -#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR \ +#define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR \ CONFIG_PLATFORM_EC_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR #endif @@ -1365,7 +1362,7 @@ extern struct jump_data mock_jump_data; #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* TODO(b:189855648): hard-code a few things here; move to zephyr? */ -#define IT83XX_USBPD_PHY_PORT_COUNT 2 +#define IT83XX_USBPD_PHY_PORT_COUNT 2 #endif #undef CONFIG_USB_PD_TCPM_DRIVER_IT8XXX2 @@ -1594,13 +1591,13 @@ extern struct jump_data mock_jump_data; #ifdef CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB #define USBC_PORT_C0_HB_RETIMER_I2C_ADDR \ - DT_REG_ADDR(DT_NODELABEL(usb_c0_hb_retimer)) + DT_REG_ADDR(DT_NODELABEL(usb_c0_hb_retimer)) #define USBC_PORT_C1_HB_RETIMER_I2C_ADDR \ - DT_REG_ADDR(DT_NODELABEL(usb_c1_hb_retimer)) + DT_REG_ADDR(DT_NODELABEL(usb_c1_hb_retimer)) #define USBC_PORT_C2_HB_RETIMER_I2C_ADDR \ - DT_REG_ADDR(DT_NODELABEL(usb_c2_hb_retimer)) + DT_REG_ADDR(DT_NODELABEL(usb_c2_hb_retimer)) #define USBC_PORT_C3_HB_RETIMER_I2C_ADDR \ - DT_REG_ADDR(DT_NODELABEL(usb_c3_hb_retimer)) + DT_REG_ADDR(DT_NODELABEL(usb_c3_hb_retimer)) #define CONFIG_USBC_RETIMER_INTEL_HB #endif @@ -1731,18 +1728,18 @@ extern struct jump_data mock_jump_data; #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER #define CONFIG_USB_PD_TCPC_LOW_POWER #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE \ - CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US + CONFIG_PLATFORM_EC_USB_PD_TCPC_LPM_EXIT_DEBOUNCE_US #endif /* CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER */ #undef CONFIG_USB_PD_DEBUG_LEVEL #ifdef CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL -#define CONFIG_USB_PD_DEBUG_LEVEL CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL +#define CONFIG_USB_PD_DEBUG_LEVEL CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL #endif #undef CONFIG_USB_PD_STARTUP_DELAY_MS #ifdef CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS -#define CONFIG_USB_PD_STARTUP_DELAY_MS \ - CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS +#define CONFIG_USB_PD_STARTUP_DELAY_MS \ + CONFIG_PLATFORM_EC_USB_PD_STARTUP_DELAY_MS #endif #undef CONFIG_USB_PD_3A_PORTS @@ -1837,7 +1834,7 @@ extern struct jump_data mock_jump_data; #undef VSTORE_SLOT_COUNT #ifdef CONFIG_PLATFORM_EC_VSTORE #define CONFIG_VSTORE -#define CONFIG_VSTORE_SLOT_COUNT CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT +#define CONFIG_VSTORE_SLOT_COUNT CONFIG_PLATFORM_EC_VSTORE_SLOT_COUNT #endif /* motion sense */ @@ -1871,7 +1868,8 @@ extern struct jump_data mock_jump_data; #undef CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ #ifdef CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ -#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ \ + CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ #endif #undef CONFIG_CMD_ACCEL_SPOOF @@ -2130,14 +2128,14 @@ extern struct jump_data mock_jump_data; #undef CONFIG_RO_HDR_MEM_OFF #ifdef CONFIG_PLATFORM_EC_RO_HEADER_OFFSET -#define CONFIG_RO_HDR_MEM_OFF CONFIG_PLATFORM_EC_RO_HEADER_OFFSET +#define CONFIG_RO_HDR_MEM_OFF CONFIG_PLATFORM_EC_RO_HEADER_OFFSET #else #define CONFIG_RO_HDR_MEM_OFF 0 #endif #undef CONFIG_RO_HDR_SIZE #ifdef CONFIG_PLATFORM_EC_RO_HEADER_SIZE -#define CONFIG_RO_HDR_SIZE CONFIG_PLATFORM_EC_RO_HEADER_SIZE +#define CONFIG_RO_HDR_SIZE CONFIG_PLATFORM_EC_RO_HEADER_SIZE #else #define CONFIG_RO_HDR_SIZE 0 #endif @@ -2204,7 +2202,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_WATCHDOG_WARNING_LEADING_TIME_MS #if defined(CONFIG_PLATFORM_EC_WATCHDOG_WARNING_LEADING_TIME_MS) || \ - defined(CONFIG_WDT_NPCX_DELAY_CYCLES) || \ + defined(CONFIG_WDT_NPCX_DELAY_CYCLES) || \ defined(CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS) /* * Note: @@ -2324,7 +2322,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_BATTERY_DEVICE_CHEMISTRY #ifdef CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY -#define CONFIG_BATTERY_DEVICE_CHEMISTRY \ +#define CONFIG_BATTERY_DEVICE_CHEMISTRY \ CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY #endif @@ -2371,13 +2369,13 @@ extern struct jump_data mock_jump_data; #undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR \ +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR \ CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR #endif #undef CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC #ifdef CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC \ +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC \ CONFIG_PLATFORM_EC_CHARGER_BQ25710_SENSE_RESISTOR_AC #endif @@ -2418,13 +2416,12 @@ extern struct jump_data mock_jump_data; #undef CONFIG_CHARGER_SENSE_RESISTOR #ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR -#define CONFIG_CHARGER_SENSE_RESISTOR \ - CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR +#define CONFIG_CHARGER_SENSE_RESISTOR CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR #endif #undef CONFIG_CHARGER_SENSE_RESISTOR_AC #ifdef CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC -#define CONFIG_CHARGER_SENSE_RESISTOR_AC \ +#define CONFIG_CHARGER_SENSE_RESISTOR_AC \ CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC #endif @@ -2459,8 +2456,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_MP2964 #ifdef CONFIG_PLATFORM_EC_MP2964 #define CONFIG_MP2964 -#define I2C_ADDR_MP2964_FLAGS \ - DT_REG_ADDR(DT_NODELABEL(pmic_mp2964)) +#define I2C_ADDR_MP2964_FLAGS DT_REG_ADDR(DT_NODELABEL(pmic_mp2964)) #endif #undef CONFIG_ACCELGYRO_ICM_COMM_SPI @@ -2602,4 +2598,4 @@ extern struct jump_data mock_jump_data; #define CONFIG_IO_EXPANDER_CCGXXF #endif -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From d1b61771242938b047c0e0a811b7e739b75aa853 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:47 -0600 Subject: driver/accelgyro_icm_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id3577139da282c5be22236116d3fc3bd4e515189 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729893 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm_common.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/accelgyro_icm_common.c b/driver/accelgyro_icm_common.c index 94db99407d..7b810946b8 100644 --- a/driver/accelgyro_icm_common.c +++ b/driver/accelgyro_icm_common.c @@ -16,12 +16,12 @@ #include "driver/accelgyro_icm426xx.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) #ifdef CONFIG_ACCELGYRO_ICM_COMM_SPI -static int icm_spi_raw_read(const int addr, const uint8_t reg, - uint8_t *data, const int len) +static int icm_spi_raw_read(const int addr, const uint8_t reg, uint8_t *data, + const int len) { uint8_t cmd = 0x80 | reg; @@ -151,8 +151,7 @@ int icm_read16(const struct motion_sensor_t *s, const int reg, int *data_ptr) } } #else - ret = i2c_read16(s->port, s->i2c_spi_addr_flags, - addr, data_ptr); + ret = i2c_read16(s->port, s->i2c_spi_addr_flags, addr, data_ptr); #endif return ret; @@ -287,12 +286,12 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale, } /* FIFO header: 1 byte */ -#define ICM_FIFO_HEADER_MSG BIT(7) -#define ICM_FIFO_HEADER_ACCEL BIT(6) -#define ICM_FIFO_HEADER_GYRO BIT(5) -#define ICM_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2) -#define ICM_FIFO_HEADER_ODR_ACCEL BIT(1) -#define ICM_FIFO_HEADER_ODR_GYRO BIT(0) +#define ICM_FIFO_HEADER_MSG BIT(7) +#define ICM_FIFO_HEADER_ACCEL BIT(6) +#define ICM_FIFO_HEADER_GYRO BIT(5) +#define ICM_FIFO_HEADER_TMST_FSYNC GENMASK(3, 2) +#define ICM_FIFO_HEADER_ODR_ACCEL BIT(1) +#define ICM_FIFO_HEADER_ODR_GYRO BIT(0) /* FIFO data packet */ struct icm_fifo_sensor_data { @@ -306,7 +305,7 @@ struct icm_fifo_1sensor_packet { struct icm_fifo_sensor_data data; int8_t temp; } __packed; -#define ICM_FIFO_1SENSOR_PACKET_SIZE 8 +#define ICM_FIFO_1SENSOR_PACKET_SIZE 8 struct icm_fifo_2sensors_packet { uint8_t header; @@ -315,10 +314,10 @@ struct icm_fifo_2sensors_packet { int8_t temp; uint16_t timestamp; } __packed; -#define ICM_FIFO_2SENSORS_PACKET_SIZE 16 +#define ICM_FIFO_2SENSORS_PACKET_SIZE 16 ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel, - const uint8_t **gyro) + const uint8_t **gyro) { const struct icm_fifo_1sensor_packet *pack1 = packet; const struct icm_fifo_2sensors_packet *pack2 = packet; -- cgit v1.2.1 From 649793803d1a8f38fad8cbada083ea3694e63494 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:30 -0600 Subject: board/taeko/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a8f7e13d01119c6a893dacb8a3047b35b56038a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728985 Reviewed-by: Jeremy Bettis --- board/taeko/pwm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/taeko/pwm.c b/board/taeko/pwm.c index b5fef384f9..985305449b 100644 --- a/board/taeko/pwm.c +++ b/board/taeko/pwm.c @@ -32,7 +32,6 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); static void board_pwm_init(void) { - pwm_enable(PWM_CH_KBLIGHT, 1); pwm_set_duty(PWM_CH_KBLIGHT, 50); } -- cgit v1.2.1 From fdc180d5064a38729a90336b2ab11a5783636354 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:20 -0600 Subject: common/motion_sense.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c926ba079e9e0eacca41e0bed9f8de1203a3073 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729680 Reviewed-by: Jeremy Bettis --- common/motion_sense.c | 330 +++++++++++++++++++++++--------------------------- 1 file changed, 154 insertions(+), 176 deletions(-) diff --git a/common/motion_sense.c b/common/motion_sense.c index f61b8dfdf1..776949b8aa 100644 --- a/common/motion_sense.c +++ b/common/motion_sense.c @@ -33,9 +33,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_MOTION_SENSE, outstr) -#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_MOTION_SENSE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_MOTION_SENSE, format, ##args) /* Delay between FIFO interruption. */ static unsigned int ap_event_interval; @@ -67,10 +66,10 @@ test_export_static enum chipset_state_mask sensor_active; test_export_static int wait_us; STATIC_IF(CONFIG_ACCEL_SPOOF_MODE) void print_spoof_mode_status(int id); -STATIC_IF(CONFIG_GESTURE_DETECTION) void check_and_queue_gestures( - uint32_t *event); -STATIC_IF(CONFIG_MOTION_FILL_LPC_SENSE_DATA) void update_sense_data( - uint8_t *lpc_status, int *psample_id); +STATIC_IF(CONFIG_GESTURE_DETECTION) +void check_and_queue_gestures(uint32_t *event); +STATIC_IF(CONFIG_MOTION_FILL_LPC_SENSE_DATA) +void update_sense_data(uint8_t *lpc_status, int *psample_id); /* Flags to control whether to send an ODR change event for a sensor */ static atomic_t odr_event_required; @@ -90,8 +89,8 @@ static int init_sensor_mutex(const struct device *dev) SYS_INIT(init_sensor_mutex, POST_KERNEL, 50); #endif /* CONFIG_ZEPHYR */ -static inline int motion_sensor_in_forced_mode( - const struct motion_sensor_t *sensor) +static inline int +motion_sensor_in_forced_mode(const struct motion_sensor_t *sensor) { #ifdef CONFIG_ACCEL_FORCE_MODE_MASK /* Sensor not in force mode, its irq_handler is getting data. */ @@ -105,8 +104,9 @@ static inline int motion_sensor_in_forced_mode( } /* Minimal amount of time since last collection before triggering a new one */ -static inline int motion_sensor_time_to_read(const timestamp_t *ts, - const struct motion_sensor_t *sensor) +static inline int +motion_sensor_time_to_read(const timestamp_t *ts, + const struct motion_sensor_t *sensor) { if (sensor->collection_rate == 0) return 0; @@ -173,8 +173,8 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor) sensor->name, odr, roundup, config_id, BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr)); else - CPRINTS("%c%d ODR %d rup %d cfg %d AP %d", - sensor->name[0], sensor->type, odr, roundup, config_id, + CPRINTS("%c%d ODR %d rup %d cfg %d AP %d", sensor->name[0], + sensor->type, odr, roundup, config_id, BASE_ODR(sensor->config[SENSOR_CONFIG_AP].odr)); mutex_lock(&g_sensor_mutex); @@ -203,9 +203,9 @@ int motion_sense_set_data_rate(struct motion_sensor_t *sensor) return 0; } -static int motion_sense_set_ec_rate_from_ap( - const struct motion_sensor_t *sensor, - unsigned int new_rate_us) +static int +motion_sense_set_ec_rate_from_ap(const struct motion_sensor_t *sensor, + unsigned int new_rate_us) { int odr_mhz = sensor->drv->get_data_rate(sensor); @@ -238,7 +238,6 @@ end_set_ec_rate_from_ap: return MAX(new_rate_us, motion_min_interval); } - /* * motion_sense_select_ec_rate * @@ -253,10 +252,9 @@ end_set_ec_rate_from_ap: * * return rate in us. */ -static int motion_sense_select_ec_rate( - const struct motion_sensor_t *sensor, - enum sensor_config config_id, - int interrupt) +static int motion_sense_select_ec_rate(const struct motion_sensor_t *sensor, + enum sensor_config config_id, + int interrupt) { if (interrupt == 0 && motion_sensor_in_forced_mode(sensor)) { int rate_mhz = BASE_ODR(sensor->config[config_id].odr); @@ -283,11 +281,11 @@ static int motion_sense_ec_rate(struct motion_sensor_t *sensor) /* Check the AP setting first. */ if (sensor_active != SENSOR_ACTIVE_S5) - ec_rate = motion_sense_select_ec_rate( - sensor, SENSOR_CONFIG_AP, 0); + ec_rate = motion_sense_select_ec_rate(sensor, SENSOR_CONFIG_AP, + 0); ec_rate_from_cfg = motion_sense_select_ec_rate( - sensor, motion_sense_get_ec_config(), 0); + sensor, motion_sense_get_ec_config(), 0); if (ec_rate_from_cfg != 0) if (ec_rate == 0 || ec_rate_from_cfg < ec_rate) @@ -315,7 +313,7 @@ static void motion_sense_set_motion_intervals(void) continue; sensor_ec_rate = motion_sense_select_ec_rate( - sensor, SENSOR_CONFIG_AP, 1); + sensor, SENSOR_CONFIG_AP, 1); if (ec_int_rate == 0 || (sensor_ec_rate && sensor_ec_rate < ec_int_rate)) ec_int_rate = sensor_ec_rate; @@ -365,8 +363,8 @@ int sensor_init_done(struct motion_sensor_t *s) !!(s->current_range & ROUND_UP_FLAG)); if (ret == EC_RES_SUCCESS) { if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE)) - CPRINTS("%s: MS Done Init type:0x%X range:%d", - s->name, s->type, s->current_range); + CPRINTS("%s: MS Done Init type:0x%X range:%d", s->name, + s->type, s->current_range); else CPRINTS("%c%d InitDone r:%d", s->name[0], s->type, s->current_range); @@ -396,15 +394,14 @@ static void motion_sense_switch_sensor_rate(void) * set. */ if (sensor->state == SENSOR_INITIALIZED) { - sensor->drv->set_range(sensor, - sensor->current_range, - 1); + sensor->drv->set_range( + sensor, sensor->current_range, 1); sensor_setup_mask |= BIT(i); } else { ret = motion_sense_init(sensor); if (ret != EC_SUCCESS) CPRINTS("%s: %d: init failed: %d", - sensor->name, i, ret); + sensor->name, i, ret); else sensor_setup_mask |= BIT(i); /* @@ -468,19 +465,20 @@ static void motion_sense_switch_sensor_rate(void) sensor = &motion_sensors[i]; if (sensor->state != SENSOR_INITIALIZED) continue; - sensor->drv->list_activities(sensor, - &enabled, &disabled); + sensor->drv->list_activities(sensor, &enabled, + &disabled); /* exclude double tap, it is used internally. */ enabled &= ~BIT(MOTIONSENSE_ACTIVITY_DOUBLE_TAP); while (enabled) { int activity = get_next_bit(&enabled); - sensor->drv->manage_activity( - sensor, activity, 0, NULL); + sensor->drv->manage_activity(sensor, activity, + 0, NULL); } /* Re-enable double tap in case AP disabled it */ - sensor->drv->manage_activity(sensor, - MOTIONSENSE_ACTIVITY_DOUBLE_TAP, 1, NULL); + sensor->drv->manage_activity( + sensor, MOTIONSENSE_ACTIVITY_DOUBLE_TAP, 1, + NULL); } } } @@ -544,8 +542,7 @@ static void motion_sense_resume(void) hook_call_deferred(&motion_sense_switch_sensor_rate_data, CONFIG_MOTION_SENSE_RESUME_DELAY_US); } -DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume, - MOTION_SENSE_HOOK_PRIO); +DECLARE_HOOK(HOOK_CHIPSET_RESUME, motion_sense_resume, MOTION_SENSE_HOOK_PRIO); static void motion_sense_startup(void) { @@ -561,8 +558,7 @@ static void motion_sense_startup(void) if (chipset_in_state(SENSOR_ACTIVE_S0)) motion_sense_resume(); } -DECLARE_HOOK(HOOK_INIT, motion_sense_startup, - MOTION_SENSE_HOOK_PRIO); +DECLARE_HOOK(HOOK_INIT, motion_sense_startup, MOTION_SENSE_HOOK_PRIO); /* Write to LPC status byte to represent that accelerometers are present. */ static inline void set_present(uint8_t *lpc_status) @@ -620,15 +616,14 @@ static void update_sense_data(uint8_t *lpc_status, int *psample_id) for (i = 0; i < EC_ALS_ENTRIES && i < ALS_COUNT; i++) lpc_als[i] = ec_motion_sensor_clamp_u16( - motion_als_sensors[i]->xyz[X]); + motion_als_sensors[i]->xyz[X]); } /* * Increment sample id and clear busy bit to signal we finished * updating data. */ - *psample_id = (*psample_id + 1) & - EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK; + *psample_id = (*psample_id + 1) & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK; *lpc_status = EC_MEMMAP_ACC_STATUS_PRESENCE_BIT | *psample_id; } #endif @@ -650,7 +645,6 @@ static int motion_sense_read(struct motion_sensor_t *sensor) return sensor->drv->read(sensor, sensor->raw_xyz); } - static inline void increment_sensor_collection(struct motion_sensor_t *sensor, const timestamp_t *ts) { @@ -708,8 +702,7 @@ void motion_sense_push_raw_xyz(struct motion_sensor_t *s) } } -static int motion_sense_process(struct motion_sensor_t *sensor, - uint32_t *event, +static int motion_sense_process(struct motion_sensor_t *sensor, uint32_t *event, const timestamp_t *ts) { int ret = EC_SUCCESS; @@ -758,8 +751,8 @@ static int motion_sense_process(struct motion_sensor_t *sensor, int flush_pending = atomic_clear(&sensor->flush_pending); for (; flush_pending > 0; flush_pending--) { - motion_sense_fifo_insert_async_event( - sensor, ASYNC_EVENT_FLUSH); + motion_sense_fifo_insert_async_event(sensor, + ASYNC_EVENT_FLUSH); } } @@ -768,8 +761,8 @@ static int motion_sense_process(struct motion_sensor_t *sensor, motion_sense_set_data_rate(sensor); motion_sense_set_motion_intervals(); if (IS_ENABLED(CONFIG_ACCEL_FIFO)) - motion_sense_fifo_insert_async_event( - sensor, ASYNC_EVENT_ODR); + motion_sense_fifo_insert_async_event(sensor, + ASYNC_EVENT_ODR); } if (has_data_read) { /* Run gesture recognition engine */ @@ -783,13 +776,12 @@ static int motion_sense_process(struct motion_sensor_t *sensor, return ret; } - #ifdef CONFIG_GESTURE_DETECTION static void check_and_queue_gestures(uint32_t *event) { if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) && (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) { + MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) { if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { struct ec_response_motion_sensor_data vector; @@ -799,14 +791,15 @@ static void check_and_queue_gestures(uint32_t *event) * AP is ignoring double tap event, do no wake up and no * automatic disable. */ - if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST)) + if (IS_ENABLED( + CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST)) vector.flags |= MOTIONSENSE_SENSOR_FLAG_WAKEUP; vector.activity_data.activity = - MOTIONSENSE_ACTIVITY_DOUBLE_TAP; + MOTIONSENSE_ACTIVITY_DOUBLE_TAP; vector.activity_data.state = 1 /* triggered */; vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID; motion_sense_fifo_stage_data(&vector, NULL, 0, - __hw_clock_source_read()); + __hw_clock_source_read()); motion_sense_fifo_commit_data(); } /* Call board specific function to process tap */ @@ -814,7 +807,7 @@ static void check_and_queue_gestures(uint32_t *event) } if (IS_ENABLED(CONFIG_GESTURE_SIGMO) && (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( - MOTIONSENSE_ACTIVITY_SIG_MOTION))) { + MOTIONSENSE_ACTIVITY_SIG_MOTION))) { struct motion_sensor_t *activity_sensor; if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { struct ec_response_motion_sensor_data vector; @@ -823,19 +816,18 @@ static void check_and_queue_gestures(uint32_t *event) vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP | MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO; vector.activity_data.activity = - MOTIONSENSE_ACTIVITY_SIG_MOTION; + MOTIONSENSE_ACTIVITY_SIG_MOTION; vector.activity_data.state = 1 /* triggered */; vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID; motion_sense_fifo_stage_data(&vector, NULL, 0, - __hw_clock_source_read()); + __hw_clock_source_read()); motion_sense_fifo_commit_data(); } /* Disable further detection */ activity_sensor = &motion_sensors[CONFIG_GESTURE_SIGMO_SENSOR]; activity_sensor->drv->manage_activity( - activity_sensor, - MOTIONSENSE_ACTIVITY_SIG_MOTION, - 0, NULL); + activity_sensor, MOTIONSENSE_ACTIVITY_SIG_MOTION, 0, + NULL); } if (IS_ENABLED(CONFIG_ORIENTATION_SENSOR)) { const struct motion_sensor_t *sensor = @@ -852,24 +844,22 @@ static void check_and_queue_gestures(uint32_t *event) mutex_lock(sensor->mutex); if (motion_orientation_changed(sensor) && - (*motion_orientation_ptr(sensor) != - MOTIONSENSE_ORIENTATION_UNKNOWN)) { + (*motion_orientation_ptr(sensor) != + MOTIONSENSE_ORIENTATION_UNKNOWN)) { motion_orientation_update(sensor); vector.activity_data.state = *motion_orientation_ptr(sensor); - motion_sense_fifo_stage_data(&vector, NULL, 0, - __hw_clock_source_read()); + motion_sense_fifo_stage_data( + &vector, NULL, 0, + __hw_clock_source_read()); motion_sense_fifo_commit_data(); if (IS_ENABLED(CONFIG_DEBUG_ORIENTATION)) { - static const char * const mode[] = { - "Landscape", - "Portrait", - "Inv_Portrait", - "Inv_Landscape", + static const char *const mode[] = { + "Landscape", "Portrait", + "Inv_Portrait", "Inv_Landscape", "Unknown" }; - CPRINTS(mode[ - vector.activity_data.state]); + CPRINTS(mode[vector.activity_data.state]); } } mutex_unlock(sensor->mutex); @@ -910,7 +900,6 @@ void motion_sense_task(void *u) while (1) { ts_begin_task = get_time(); for (i = 0; i < motion_sensor_count; ++i) { - sensor = &motion_sensors[i]; /* if the sensor is active in the current power state */ @@ -920,7 +909,7 @@ void motion_sense_task(void *u) } ret = motion_sense_process(sensor, &event, - &ts_begin_task); + &ts_begin_task); if (ret != EC_SUCCESS) continue; ready_status |= BIT(i); @@ -944,13 +933,12 @@ void motion_sense_task(void *u) } } if (IS_ENABLED(CONFIG_CMD_ACCEL_INFO) && (accel_disp)) { - CPRINTF("[%pT event 0x%08x ", - PRINTF_TIMESTAMP_NOW, event); + CPRINTF("[%pT event 0x%08x ", PRINTF_TIMESTAMP_NOW, + event); for (i = 0; i < motion_sensor_count; ++i) { sensor = &motion_sensors[i]; CPRINTF("%s=%-5d, %-5d, %-5d ", sensor->name, - sensor->xyz[X], - sensor->xyz[Y], + sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]); } if (IS_ENABLED(CONFIG_LID_ANGLE)) @@ -986,9 +974,9 @@ void motion_sense_task(void *u) * will resume listening until it is suspended again. */ if ((IS_ENABLED(CONFIG_MKBP_EVENT) && - ((fifo_int_enabled && - sensor_active == SENSOR_ACTIVE_S0) || - motion_sense_fifo_wake_up_needed()))) { + ((fifo_int_enabled && + sensor_active == SENSOR_ACTIVE_S0) || + motion_sense_fifo_wake_up_needed()))) { mkbp_send_event(EC_MKBP_EVENT_SENSOR_FIFO); } if (motion_sense_fifo_bypass_needed()) @@ -1003,7 +991,7 @@ void motion_sense_task(void *u) struct motion_sensor_t *sensor = &motion_sensors[i]; if (!motion_sensor_in_forced_mode(sensor) || - sensor->collection_rate == 0) + sensor->collection_rate == 0) continue; time_diff = time_until(ts_end_task.le.lo, @@ -1021,9 +1009,9 @@ void motion_sense_task(void *u) if (wait_us >= 0 && wait_us < motion_min_interval) { /* - * Guarantee some minimum delay to allow other lower - * priority tasks to run. - */ + * Guarantee some minimum delay to allow other lower + * priority tasks to run. + */ wait_us = motion_min_interval; } @@ -1035,8 +1023,7 @@ void motion_sense_task(void *u) /* Host commands */ /* Function to map host sensor IDs to motion sensor. */ -static struct motion_sensor_t - *host_sensor_id_to_real_sensor(int host_id) +static struct motion_sensor_t *host_sensor_id_to_real_sensor(int host_id) { struct motion_sensor_t *sensor; @@ -1052,8 +1039,7 @@ static struct motion_sensor_t return NULL; } -static struct motion_sensor_t - *host_sensor_id_to_motion_sensor(int host_id) +static struct motion_sensor_t *host_sensor_id_to_motion_sensor(int host_id) { /* Return the info for the first sensor that support some gestures. */ if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) && @@ -1081,7 +1067,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) out->dump.module_flags = (*(host_get_memmap(EC_MEMMAP_ACC_STATUS)) & EC_MEMMAP_ACC_STATUS_PRESENCE_BIT) ? - MOTIONSENSE_MODULE_FLAG_ACTIVE : 0; + MOTIONSENSE_MODULE_FLAG_ACTIVE : + 0; out->dump.sensor_count = ALL_MOTION_SENSORS; args->response_size = sizeof(out->dump); reported = MIN(ALL_MOTION_SENSORS, in->dump.max_sensor_count); @@ -1099,13 +1086,14 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) } } mutex_unlock(&g_sensor_mutex); - args->response_size += reported * + args->response_size += + reported * sizeof(struct ec_response_motion_sensor_data); break; case MOTIONSENSE_CMD_DATA: sensor = host_sensor_id_to_real_sensor( - in->sensor_odr.sensor_num); + in->sensor_odr.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; @@ -1120,7 +1108,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_INFO: sensor = host_sensor_id_to_motion_sensor( - in->sensor_odr.sensor_num); + in->sensor_odr.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; @@ -1139,7 +1127,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) if (args->version >= 3) { out->info_3.min_frequency = sensor->min_frequency; out->info_3.max_frequency = sensor->max_frequency; - out->info_3.fifo_max_event_count = CONFIG_ACCEL_FIFO_SIZE; + out->info_3.fifo_max_event_count = + CONFIG_ACCEL_FIFO_SIZE; args->response_size = sizeof(out->info_3); } if (args->version >= 4) { @@ -1152,8 +1141,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) break; case MOTIONSENSE_CMD_EC_RATE: - sensor = host_sensor_id_to_real_sensor( - in->ec_rate.sensor_num); + sensor = host_sensor_id_to_real_sensor(in->ec_rate.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; @@ -1181,7 +1169,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_SENSOR_ODR: /* Verify sensor number is valid. */ sensor = host_sensor_id_to_real_sensor( - in->sensor_odr.sensor_num); + in->sensor_odr.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; @@ -1210,7 +1198,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_SENSOR_RANGE: /* Verify sensor number is valid. */ sensor = host_sensor_id_to_real_sensor( - in->sensor_range.sensor_num); + in->sensor_range.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; /* Set new range if the data arg has a value. */ @@ -1218,10 +1206,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) if (!sensor->drv->set_range) return EC_RES_INVALID_COMMAND; - if (sensor->drv->set_range(sensor, - in->sensor_range.data, - in->sensor_range.roundup) - != EC_SUCCESS) { + if (sensor->drv->set_range( + sensor, in->sensor_range.data, + in->sensor_range.roundup) != EC_SUCCESS) { return EC_RES_INVALID_PARAM; } } @@ -1233,7 +1220,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_SENSOR_OFFSET: /* Verify sensor number is valid. */ sensor = host_sensor_id_to_real_sensor( - in->sensor_offset.sensor_num); + in->sensor_offset.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; /* Set new range if the data arg has a value. */ @@ -1242,9 +1229,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) return EC_RES_INVALID_COMMAND; in_offset = in->sensor_offset.offset; - ret = sensor->drv->set_offset(sensor, - in_offset, - in->sensor_offset.temp); + ret = sensor->drv->set_offset(sensor, in_offset, + in->sensor_offset.temp); if (ret != EC_SUCCESS) return ret; } @@ -1264,7 +1250,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_SENSOR_SCALE: /* Verify sensor number is valid. */ sensor = host_sensor_id_to_real_sensor( - in->sensor_scale.sensor_num); + in->sensor_scale.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; /* Set new range if the data arg has a value. */ @@ -1273,8 +1259,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) return EC_RES_INVALID_COMMAND; in_scale = in->sensor_scale.scale; - ret = sensor->drv->set_scale(sensor, - in_scale, + ret = sensor->drv->set_scale(sensor, in_scale, in->sensor_scale.temp); if (ret != EC_SUCCESS) return ret; @@ -1284,8 +1269,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) return EC_RES_INVALID_COMMAND; out_scale = out->sensor_scale.scale; - ret = sensor->drv->get_scale(sensor, out_scale, - &out_temp); + ret = sensor->drv->get_scale(sensor, out_scale, &out_temp); if (ret != EC_SUCCESS) return ret; @@ -1296,14 +1280,14 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_CMD_PERFORM_CALIB: /* Verify sensor number is valid. */ sensor = host_sensor_id_to_real_sensor( - in->perform_calib.sensor_num); + in->perform_calib.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; if (!sensor->drv->perform_calib) return EC_RES_INVALID_COMMAND; - ret = sensor->drv->perform_calib( - sensor, in->perform_calib.enable); + ret = sensor->drv->perform_calib(sensor, + in->perform_calib.enable); if (ret != EC_SUCCESS) return ret; @@ -1320,7 +1304,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) if (!IS_ENABLED(CONFIG_ACCEL_FIFO)) return EC_RES_INVALID_PARAM; sensor = host_sensor_id_to_real_sensor( - in->sensor_odr.sensor_num); + in->sensor_odr.sensor_num); if (sensor == NULL) return EC_RES_INVALID_PARAM; @@ -1345,7 +1329,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) motion_sensors[i].lost = 0; } args->response_size = sizeof(out->fifo_info) + - sizeof(uint16_t) * motion_sensor_count; + sizeof(uint16_t) * motion_sensor_count; break; case MOTIONSENSE_CMD_FIFO_READ: @@ -1353,8 +1337,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; out->fifo_read.number_data = motion_sense_fifo_read( args->response_max - sizeof(out->fifo_read), - in->fifo_read.max_data_vector, - out->fifo_read.data, + in->fifo_read.max_data_vector, out->fifo_read.data, &(args->response_size)); args->response_size += sizeof(out->fifo_read); break; @@ -1384,9 +1367,9 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) out_calib_read = &out->online_calib_read; args->response_size = - online_calibration_read(sensor, out_calib_read) - ? sizeof(struct ec_response_online_calibration_data) - : 0; + online_calibration_read(sensor, out_calib_read) ? + sizeof(struct ec_response_online_calibration_data) : + 0; break; #ifdef CONFIG_GESTURE_HOST_DETECTION case MOTIONSENSE_CMD_LIST_ACTIVITIES: { @@ -1399,8 +1382,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) while (mask && ret == EC_RES_SUCCESS) { i = get_next_bit(&mask); sensor = &motion_sensors[i]; - ret = sensor->drv->list_activities(sensor, - &enabled, &disabled); + ret = sensor->drv->list_activities(sensor, &enabled, + &disabled); if (ret == EC_RES_SUCCESS) { out->list_activities.enabled |= enabled; out->list_activities.disabled |= disabled; @@ -1408,11 +1391,11 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) } if (IS_ENABLED(CONFIG_BODY_DETECTION)) { if (body_detect_get_enable()) { - out->list_activities.enabled |= - BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION); + out->list_activities.enabled |= BIT( + MOTIONSENSE_ACTIVITY_BODY_DETECTION); } else { - out->list_activities.disabled |= - BIT(MOTIONSENSE_ACTIVITY_BODY_DETECTION); + out->list_activities.disabled |= BIT( + MOTIONSENSE_ACTIVITY_BODY_DETECTION); } } if (ret != EC_RES_SUCCESS) @@ -1428,18 +1411,18 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) while (mask && ret == EC_RES_SUCCESS) { i = get_next_bit(&mask); sensor = &motion_sensors[i]; - sensor->drv->list_activities(sensor, - &enabled, &disabled); + sensor->drv->list_activities(sensor, &enabled, + &disabled); if ((1 << in->set_activity.activity) & (enabled | disabled)) - ret = sensor->drv->manage_activity(sensor, - in->set_activity.activity, - in->set_activity.enable, - &in->set_activity); + ret = sensor->drv->manage_activity( + sensor, in->set_activity.activity, + in->set_activity.enable, + &in->set_activity); } if (IS_ENABLED(CONFIG_BODY_DETECTION) && (in->set_activity.activity == - MOTIONSENSE_ACTIVITY_BODY_DETECTION)) + MOTIONSENSE_ACTIVITY_BODY_DETECTION)) body_detect_set_enable(in->set_activity.enable); if (ret != EC_RES_SUCCESS) return ret; @@ -1450,8 +1433,8 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) if (IS_ENABLED(CONFIG_BODY_DETECTION) && (in->get_activity.activity == MOTIONSENSE_ACTIVITY_BODY_DETECTION)) { - out->get_activity.state = (uint8_t) - body_detect_get_state(); + out->get_activity.state = + (uint8_t)body_detect_get_state(); ret = EC_RES_SUCCESS; } else { ret = EC_RES_INVALID_PARAM; @@ -1549,7 +1532,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) case MOTIONSENSE_SPOOF_MODE_QUERY: /* Querying the spoof status of the sensor. */ out->spoof.ret = !!(sensor->flags & - MOTIONSENSE_FLAG_IN_SPOOF_MODE); + MOTIONSENSE_FLAG_IN_SPOOF_MODE); args->response_size = sizeof(out->spoof); break; @@ -1570,7 +1553,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) default: /* Call other users of the motion task */ if (IS_ENABLED(CONFIG_LID_ANGLE) && - (ret == EC_RES_INVALID_PARAM)) + (ret == EC_RES_INVALID_PARAM)) ret = host_cmd_motion_lid(args); return ret; } @@ -1580,7 +1563,7 @@ static enum ec_status host_cmd_motion_sense(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_MOTION_SENSE_CMD, host_cmd_motion_sense, EC_VER_MASK(1) | EC_VER_MASK(2) | EC_VER_MASK(3) | - EC_VER_MASK(4)); + EC_VER_MASK(4)); /*****************************************************************************/ /* Console commands */ @@ -1618,9 +1601,8 @@ static int command_accelrange(int argc, char **argv) * Write new range, if it returns invalid arg, then return * a parameter error. */ - if (sensor->drv->set_range(sensor, - data, - round) == EC_ERROR_INVAL) + if (sensor->drv->set_range(sensor, data, round) == + EC_ERROR_INVAL) return EC_ERROR_PARAM2; } else { ccprintf("Sensor %d range: %d\n", id, sensor->current_range); @@ -1628,9 +1610,8 @@ static int command_accelrange(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange, - "id [data [roundup]]", - "Read or write accelerometer range"); +DECLARE_CONSOLE_COMMAND(accelrange, command_accelrange, "id [data [roundup]]", + "Read or write accelerometer range"); static int command_accelresolution(int argc, char **argv) { @@ -1666,8 +1647,8 @@ static int command_accelresolution(int argc, char **argv) * return a parameter error. */ if (sensor->drv->set_resolution && - sensor->drv->set_resolution(sensor, data, round) - == EC_ERROR_INVAL) + sensor->drv->set_resolution(sensor, data, round) == + EC_ERROR_INVAL) return EC_ERROR_PARAM2; } else { ccprintf("Resolution for sensor %d: %d\n", id, @@ -1677,8 +1658,8 @@ static int command_accelresolution(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(accelres, command_accelresolution, - "id [data [roundup]]", - "Read or write accelerometer resolution"); + "id [data [roundup]]", + "Read or write accelerometer resolution"); static int command_accel_data_rate(int argc, char **argv) { @@ -1717,8 +1698,8 @@ static int command_accel_data_rate(int argc, char **argv) */ config_id = motion_sense_get_ec_config(); sensor->config[SENSOR_CONFIG_AP].odr = 0; - sensor->config[config_id].odr = - data | (round ? ROUND_UP_FLAG : 0); + sensor->config[config_id].odr = data | + (round ? ROUND_UP_FLAG : 0); atomic_or(&odr_event_required, 1 << (sensor - motion_sensors)); task_set_event(TASK_ID_MOTIONSENSE, @@ -1734,8 +1715,8 @@ static int command_accel_data_rate(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(accelrate, command_accel_data_rate, - "id [data [roundup]]", - "Read or write accelerometer ODR"); + "id [data [roundup]]", + "Read or write accelerometer ODR"); static int command_accel_read_xyz(int argc, char **argv) { @@ -1761,20 +1742,19 @@ static int command_accel_read_xyz(int argc, char **argv) while ((n-- > 0)) { ret = sensor->drv->read(sensor, v); if (ret == 0) - ccprintf("Current data %d: %-5d %-5d %-5d\n", - id, v[X], v[Y], v[Z]); + ccprintf("Current data %d: %-5d %-5d %-5d\n", id, v[X], + v[Y], v[Z]); else ccprintf("vector not ready\n"); - ccprintf("Last calib. data %d: %-5d %-5d %-5d\n", - id, sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]); + ccprintf("Last calib. data %d: %-5d %-5d %-5d\n", id, + sensor->xyz[X], sensor->xyz[Y], sensor->xyz[Z]); task_wait_event(motion_min_interval); } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz, - "id [n]", - "Read sensor x/y/z"); +DECLARE_CONSOLE_COMMAND(accelread, command_accel_read_xyz, "id [n]", + "Read sensor x/y/z"); static int command_accel_init(int argc, char **argv) { @@ -1797,9 +1777,7 @@ static int command_accel_init(int argc, char **argv) ccprintf("%s: state %d - %d\n", sensor->name, sensor->state, ret); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init, - "id", - "Init sensor"); +DECLARE_CONSOLE_COMMAND(accelinit, command_accel_init, "id", "Init sensor"); #ifdef CONFIG_CMD_ACCEL_INFO static int command_display_accel_info(int argc, char **argv) @@ -1819,17 +1797,17 @@ static int command_display_accel_info(int argc, char **argv) ccprintf("type: %d\n", motion_sensors[i].type); ccprintf("location: %d\n", motion_sensors[i].location); ccprintf("port: %d\n", motion_sensors[i].port); - ccprintf("addr: %d\n", I2C_STRIP_FLAGS(motion_sensors[i] - .i2c_spi_addr_flags)); + ccprintf("addr: %d\n", + I2C_STRIP_FLAGS(motion_sensors[i].i2c_spi_addr_flags)); ccprintf("range: %d\n", motion_sensors[i].current_range); ccprintf("min_freq: %d\n", motion_sensors[i].min_frequency); ccprintf("max_freq: %d\n", motion_sensors[i].max_frequency); ccprintf("config:\n"); for (j = 0; j < SENSOR_CONFIG_MAX; j++) { ccprintf("%d - odr: %umHz, ec_rate: %uus\n", j, - motion_sensors[i].config[j].odr & - ~ROUND_UP_FLAG, - motion_sensors[i].config[j].ec_rate); + motion_sensors[i].config[j].odr & + ~ROUND_UP_FLAG, + motion_sensors[i].config[j].ec_rate); } } @@ -1843,9 +1821,8 @@ static int command_display_accel_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info, - "on/off", - "Print motion sensor info, lid angle calculations."); +DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info, "on/off", + "Print motion sensor info, lid angle calculations."); #endif /* CONFIG_CMD_ACCEL_INFO */ #endif /* CONFIG_CMD_ACCELS */ @@ -1854,8 +1831,9 @@ DECLARE_CONSOLE_COMMAND(accelinfo, command_display_accel_info, static void print_spoof_mode_status(int id) { CPRINTS("Sensor %d spoof mode is %s. <%d, %d, %d>", id, - (motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE) - ? "enabled" : "disabled", + (motion_sensors[id].flags & MOTIONSENSE_FLAG_IN_SPOOF_MODE) ? + "enabled" : + "disabled", motion_sensors[id].spoof_xyz[X], motion_sensors[id].spoof_xyz[Y], motion_sensors[id].spoof_xyz[Z]); @@ -1897,8 +1875,8 @@ static int command_accelspoof(int argc, char **argv) */ if (argc == 6) { for (i = 0; i < 3; i++) - s->spoof_xyz[i] = strtoi(argv[3 + i], - &e, 0); + s->spoof_xyz[i] = + strtoi(argv[3 + i], &e, 0); } else if (argc == 3) { for (i = X; i <= Z; i++) s->spoof_xyz[i] = s->raw_xyz[i]; -- cgit v1.2.1 From 6161bbaf299b4852714f5bd44c6239719e123473 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:02 -0600 Subject: driver/charger/rt946x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2db4563c4cfdfed11305e2ca35630843a664a35f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729967 Reviewed-by: Jeremy Bettis --- driver/charger/rt946x.h | 942 ++++++++++++++++++++++++------------------------ 1 file changed, 470 insertions(+), 472 deletions(-) diff --git a/driver/charger/rt946x.h b/driver/charger/rt946x.h index 8c8cdf03ff..3d5886b67b 100644 --- a/driver/charger/rt946x.h +++ b/driver/charger/rt946x.h @@ -10,693 +10,691 @@ /* Registers for rt9466, rt9467 */ #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467) -#define RT946X_REG_CORECTRL0 0x00 -#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL0 -#define RT946X_REG_CHGCTRL1 0x01 -#define RT946X_REG_CHGCTRL2 0x02 -#define RT946X_REG_CHGCTRL3 0x03 -#define RT946X_REG_CHGCTRL4 0x04 -#define RT946X_REG_CHGCTRL5 0x05 -#define RT946X_REG_CHGCTRL6 0x06 -#define RT946X_REG_CHGCTRL7 0x07 -#define RT946X_REG_CHGCTRL8 0x08 -#define RT946X_REG_CHGCTRL9 0x09 -#define RT946X_REG_CHGCTRL10 0x0A -#define RT946X_REG_CHGCTRL11 0x0B -#define RT946X_REG_CHGCTRL12 0x0C -#define RT946X_REG_CHGCTRL13 0x0D -#define RT946X_REG_CHGCTRL14 0x0E -#define RT946X_REG_CHGCTRL15 0x0F -#define RT946X_REG_CHGCTRL16 0x10 -#define RT946X_REG_CHGADC 0x11 +#define RT946X_REG_CORECTRL0 0x00 +#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL0 +#define RT946X_REG_CHGCTRL1 0x01 +#define RT946X_REG_CHGCTRL2 0x02 +#define RT946X_REG_CHGCTRL3 0x03 +#define RT946X_REG_CHGCTRL4 0x04 +#define RT946X_REG_CHGCTRL5 0x05 +#define RT946X_REG_CHGCTRL6 0x06 +#define RT946X_REG_CHGCTRL7 0x07 +#define RT946X_REG_CHGCTRL8 0x08 +#define RT946X_REG_CHGCTRL9 0x09 +#define RT946X_REG_CHGCTRL10 0x0A +#define RT946X_REG_CHGCTRL11 0x0B +#define RT946X_REG_CHGCTRL12 0x0C +#define RT946X_REG_CHGCTRL13 0x0D +#define RT946X_REG_CHGCTRL14 0x0E +#define RT946X_REG_CHGCTRL15 0x0F +#define RT946X_REG_CHGCTRL16 0x10 +#define RT946X_REG_CHGADC 0x11 #ifdef CONFIG_CHARGER_RT9467 -#define RT946X_REG_DPDM1 0x12 -#define RT946X_REG_DPDM2 0x13 -#define RT946X_REG_DPDM3 0x14 +#define RT946X_REG_DPDM1 0x12 +#define RT946X_REG_DPDM2 0x13 +#define RT946X_REG_DPDM3 0x14 #endif -#define RT946X_REG_CHGCTRL19 0x18 -#define RT946X_REG_CHGCTRL17 0x19 -#define RT946X_REG_CHGCTRL18 0x1A -#define RT946X_REG_CHGHIDDENCTRL2 0x21 -#define RT946X_REG_CHGHIDDENCTRL4 0x23 -#define RT946X_REG_CHGHIDDENCTRL6 0x25 -#define RT946X_REG_CHGHIDDENCTRL7 0x26 -#define RT946X_REG_CHGHIDDENCTRL8 0x27 -#define RT946X_REG_CHGHIDDENCTRL9 0x28 -#define RT946X_REG_CHGHIDDENCTRL15 0x2E -#define RT946X_REG_DEVICEID 0x40 -#define RT946X_REG_CHGSTAT 0x42 -#define RT946X_REG_CHGNTC 0x43 -#define RT946X_REG_ADCDATAH 0x44 -#define RT946X_REG_ADCDATAL 0x45 -#define RT946X_REG_CHGSTATC 0x50 -#define RT946X_REG_CHGFAULT 0x51 -#define RT946X_REG_TSSTATC 0x52 -#define RT946X_REG_CHGIRQ1 0x53 -#define RT946X_REG_CHGIRQ2 0x54 -#define RT946X_REG_CHGIRQ3 0x55 +#define RT946X_REG_CHGCTRL19 0x18 +#define RT946X_REG_CHGCTRL17 0x19 +#define RT946X_REG_CHGCTRL18 0x1A +#define RT946X_REG_CHGHIDDENCTRL2 0x21 +#define RT946X_REG_CHGHIDDENCTRL4 0x23 +#define RT946X_REG_CHGHIDDENCTRL6 0x25 +#define RT946X_REG_CHGHIDDENCTRL7 0x26 +#define RT946X_REG_CHGHIDDENCTRL8 0x27 +#define RT946X_REG_CHGHIDDENCTRL9 0x28 +#define RT946X_REG_CHGHIDDENCTRL15 0x2E +#define RT946X_REG_DEVICEID 0x40 +#define RT946X_REG_CHGSTAT 0x42 +#define RT946X_REG_CHGNTC 0x43 +#define RT946X_REG_ADCDATAH 0x44 +#define RT946X_REG_ADCDATAL 0x45 +#define RT946X_REG_CHGSTATC 0x50 +#define RT946X_REG_CHGFAULT 0x51 +#define RT946X_REG_TSSTATC 0x52 +#define RT946X_REG_CHGIRQ1 0x53 +#define RT946X_REG_CHGIRQ2 0x54 +#define RT946X_REG_CHGIRQ3 0x55 #ifdef CONFIG_CHARGER_RT9467 -#define RT946X_REG_DPDMIRQ 0x56 +#define RT946X_REG_DPDMIRQ 0x56 #endif -#define RT946X_REG_CHGSTATCCTRL 0x60 -#define RT946X_REG_CHGFAULTCTRL 0x61 -#define RT946X_REG_TSSTATCCTRL 0x62 -#define RT946X_REG_CHGIRQ1CTRL 0x63 -#define RT946X_REG_CHGIRQ2CTRL 0x64 -#define RT946X_REG_CHGIRQ3CTRL 0x65 +#define RT946X_REG_CHGSTATCCTRL 0x60 +#define RT946X_REG_CHGFAULTCTRL 0x61 +#define RT946X_REG_TSSTATCCTRL 0x62 +#define RT946X_REG_CHGIRQ1CTRL 0x63 +#define RT946X_REG_CHGIRQ2CTRL 0x64 +#define RT946X_REG_CHGIRQ3CTRL 0x65 #ifdef CONFIG_CHARGER_RT9467 -#define RT946X_REG_DPDMIRQCTRL 0x66 +#define RT946X_REG_DPDMIRQCTRL 0x66 #endif #elif defined(CONFIG_CHARGER_MT6370) /* Registers for mt6370 */ -#define RT946X_REG_DEVICEID 0x00 -#define RT946X_REG_CORECTRL1 0x01 -#define RT946X_REG_CORECTRL2 0x02 -#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL2 -#define MT6370_REG_RSTPASCODE1 0x03 -#define MT6370_REG_RSTPASCODE2 0x04 -#define MT6370_REG_HIDDENPASCODE1 0x07 -#define MT6370_REG_HIDDENPASCODE2 0x08 -#define MT6370_REG_HIDDENPASCODE3 0x09 -#define MT6370_REG_HIDDENPASCODE4 0x0A -#define MT6370_REG_IRQIND 0x0B -#define MT6370_REG_IRQMASK 0x0C -#define MT6370_REG_OSCCTRL 0x10 -#define RT946X_REG_CHGCTRL1 0x11 -#define RT946X_REG_CHGCTRL2 0x12 -#define RT946X_REG_CHGCTRL3 0x13 -#define RT946X_REG_CHGCTRL4 0x14 -#define RT946X_REG_CHGCTRL5 0x15 -#define RT946X_REG_CHGCTRL6 0x16 -#define RT946X_REG_CHGCTRL7 0x17 -#define RT946X_REG_CHGCTRL8 0x18 -#define RT946X_REG_CHGCTRL9 0x19 -#define RT946X_REG_CHGCTRL10 0x1A -#define RT946X_REG_CHGCTRL11 0x1B -#define RT946X_REG_CHGCTRL12 0x1C -#define RT946X_REG_CHGCTRL13 0x1D -#define RT946X_REG_CHGCTRL14 0x1E -#define RT946X_REG_CHGCTRL15 0x1F -#define RT946X_REG_CHGCTRL16 0x20 -#define RT946X_REG_CHGADC 0x21 -#define MT6370_REG_DEVICETYPE 0x22 -#define RT946X_REG_DPDM1 MT6370_REG_DEVICETYPE -#define MT6370_REG_USBSTATUS1 0x27 -#define MT6370_REG_QCSTATUS2 0x29 -#define RT946X_REG_CHGCTRL17 0X2B -#define RT946X_REG_CHGCTRL18 0X2C -#define RT946X_REG_CHGHIDDENCTRL7 0x36 -#define MT6370_REG_CHGHIDDENCTRL15 0x3E -#define RT946X_REG_CHGSTAT 0X4A -#define RT946X_REG_CHGNTC 0X4B -#define RT946X_REG_ADCDATAH 0X4C -#define RT946X_REG_ADCDATAL 0X4D +#define RT946X_REG_DEVICEID 0x00 +#define RT946X_REG_CORECTRL1 0x01 +#define RT946X_REG_CORECTRL2 0x02 +#define RT946X_REG_CORECTRL_RST RT946X_REG_CORECTRL2 +#define MT6370_REG_RSTPASCODE1 0x03 +#define MT6370_REG_RSTPASCODE2 0x04 +#define MT6370_REG_HIDDENPASCODE1 0x07 +#define MT6370_REG_HIDDENPASCODE2 0x08 +#define MT6370_REG_HIDDENPASCODE3 0x09 +#define MT6370_REG_HIDDENPASCODE4 0x0A +#define MT6370_REG_IRQIND 0x0B +#define MT6370_REG_IRQMASK 0x0C +#define MT6370_REG_OSCCTRL 0x10 +#define RT946X_REG_CHGCTRL1 0x11 +#define RT946X_REG_CHGCTRL2 0x12 +#define RT946X_REG_CHGCTRL3 0x13 +#define RT946X_REG_CHGCTRL4 0x14 +#define RT946X_REG_CHGCTRL5 0x15 +#define RT946X_REG_CHGCTRL6 0x16 +#define RT946X_REG_CHGCTRL7 0x17 +#define RT946X_REG_CHGCTRL8 0x18 +#define RT946X_REG_CHGCTRL9 0x19 +#define RT946X_REG_CHGCTRL10 0x1A +#define RT946X_REG_CHGCTRL11 0x1B +#define RT946X_REG_CHGCTRL12 0x1C +#define RT946X_REG_CHGCTRL13 0x1D +#define RT946X_REG_CHGCTRL14 0x1E +#define RT946X_REG_CHGCTRL15 0x1F +#define RT946X_REG_CHGCTRL16 0x20 +#define RT946X_REG_CHGADC 0x21 +#define MT6370_REG_DEVICETYPE 0x22 +#define RT946X_REG_DPDM1 MT6370_REG_DEVICETYPE +#define MT6370_REG_USBSTATUS1 0x27 +#define MT6370_REG_QCSTATUS2 0x29 +#define RT946X_REG_CHGCTRL17 0X2B +#define RT946X_REG_CHGCTRL18 0X2C +#define RT946X_REG_CHGHIDDENCTRL7 0x36 +#define MT6370_REG_CHGHIDDENCTRL15 0x3E +#define RT946X_REG_CHGSTAT 0X4A +#define RT946X_REG_CHGNTC 0X4B +#define RT946X_REG_ADCDATAH 0X4C +#define RT946X_REG_ADCDATAL 0X4D /* FLED */ -#define MT6370_REG_FLEDEN 0x7E +#define MT6370_REG_FLEDEN 0x7E /* LDO */ -#define MT6370_REG_LDOCFG 0X80 -#define MT6370_REG_LDOVOUT 0X81 +#define MT6370_REG_LDOCFG 0X80 +#define MT6370_REG_LDOVOUT 0X81 /* RGB led */ -#define MT6370_REG_RGBDIM_BASE 0x81 -#define MT6370_REG_RGB1DIM 0x82 -#define MT6370_REG_RGB2DIM 0x83 -#define MT6370_REG_RGB3DIM 0x84 -#define MT6370_REG_RGBEN 0x85 -#define MT6370_REG_RGBISNK_BASE 0x85 -#define MT6370_REG_RGB1ISNK 0x86 -#define MT6370_REG_RGB2ISNK 0x87 -#define MT6370_REG_RGB3ISNK 0x88 -#define MT6370_REG_RGBCHRINDDIM 0x92 -#define MT6370_REG_RGBCHRINDCTRL 0x93 +#define MT6370_REG_RGBDIM_BASE 0x81 +#define MT6370_REG_RGB1DIM 0x82 +#define MT6370_REG_RGB2DIM 0x83 +#define MT6370_REG_RGB3DIM 0x84 +#define MT6370_REG_RGBEN 0x85 +#define MT6370_REG_RGBISNK_BASE 0x85 +#define MT6370_REG_RGB1ISNK 0x86 +#define MT6370_REG_RGB2ISNK 0x87 +#define MT6370_REG_RGB3ISNK 0x88 +#define MT6370_REG_RGBCHRINDDIM 0x92 +#define MT6370_REG_RGBCHRINDCTRL 0x93 /* backlight */ -#define MT6370_BACKLIGHT_BLEN 0xA0 -#define MT6370_BACKLIGHT_BLPWM 0xA2 -#define MT6370_BACKLIGHT_BLDIM2 0xA4 -#define MT6370_BACKLIGHT_BLDIM 0xA5 +#define MT6370_BACKLIGHT_BLEN 0xA0 +#define MT6370_BACKLIGHT_BLPWM 0xA2 +#define MT6370_BACKLIGHT_BLDIM2 0xA4 +#define MT6370_BACKLIGHT_BLDIM 0xA5 /* Display bias */ -#define MT6370_REG_DBCTRL1 0XB0 -#define MT6370_REG_DBCTRL2 0XB1 -#define MT6370_REG_DBVBST 0XB2 -#define MT6370_REG_DBVPOS 0XB3 -#define MT6370_REG_DBVNEG 0XB4 -#define MT6370_REG_CHGIRQ1 0xC0 -#define RT946X_REG_DPDMIRQ 0xC6 +#define MT6370_REG_DBCTRL1 0XB0 +#define MT6370_REG_DBCTRL2 0XB1 +#define MT6370_REG_DBVBST 0XB2 +#define MT6370_REG_DBVPOS 0XB3 +#define MT6370_REG_DBVNEG 0XB4 +#define MT6370_REG_CHGIRQ1 0xC0 +#define RT946X_REG_DPDMIRQ 0xC6 /* status event */ -#define MT6370_REG_CHGSTAT1 0xD0 -#define RT946X_REG_CHGSTATC MT6370_REG_CHGSTAT1 -#define MT6370_REG_CHGSTAT2 0xD1 -#define RT946X_REG_CHGFAULT MT6370_REG_CHGSTAT2 -#define MT6370_REG_CHGSTAT3 0xD2 -#define MT6370_REG_CHGSTAT4 0xD3 -#define MT6370_REG_CHGSTAT5 0xD4 -#define MT6370_REG_CHGSTAT6 0xD5 -#define MT6370_REG_DPDMSTAT 0xD6 -#define MT6370_REG_DICHGSTAT 0xD7 -#define MT6370_REG_OVPCTRLSTAT 0xD8 -#define MT6370_REG_FLEDSTAT1 0xD9 -#define MT6370_REG_FLEDSTAT2 0xDA -#define MT6370_REG_BASESTAT 0xDB -#define MT6370_REG_LDOSTAT 0xDC -#define MT6370_REG_RGBSTAT 0xDD -#define MT6370_REG_BLSTAT 0xDE -#define MT6370_REG_DBSTAT 0xDF +#define MT6370_REG_CHGSTAT1 0xD0 +#define RT946X_REG_CHGSTATC MT6370_REG_CHGSTAT1 +#define MT6370_REG_CHGSTAT2 0xD1 +#define RT946X_REG_CHGFAULT MT6370_REG_CHGSTAT2 +#define MT6370_REG_CHGSTAT3 0xD2 +#define MT6370_REG_CHGSTAT4 0xD3 +#define MT6370_REG_CHGSTAT5 0xD4 +#define MT6370_REG_CHGSTAT6 0xD5 +#define MT6370_REG_DPDMSTAT 0xD6 +#define MT6370_REG_DICHGSTAT 0xD7 +#define MT6370_REG_OVPCTRLSTAT 0xD8 +#define MT6370_REG_FLEDSTAT1 0xD9 +#define MT6370_REG_FLEDSTAT2 0xDA +#define MT6370_REG_BASESTAT 0xDB +#define MT6370_REG_LDOSTAT 0xDC +#define MT6370_REG_RGBSTAT 0xDD +#define MT6370_REG_BLSTAT 0xDE +#define MT6370_REG_DBSTAT 0xDF /* irq mask */ -#define MT6370_REG_CHGMASK1 0xE0 -#define RT946X_REG_CHGSTATCCTRL MT6370_REG_CHGMASK1 -#define MT6370_REG_CHGMASK2 0xE1 -#define MT6370_REG_CHGMASK3 0xE2 -#define MT6370_REG_CHGMASK4 0xE3 -#define MT6370_REG_CHGMASK5 0xE4 -#define MT6370_REG_CHGMASK6 0xE5 -#define MT6370_REG_DPDMMASK1 0xE6 -#define MT6370_REG_DICHGMASK 0xE7 -#define MT6370_REG_OVPCTRLMASK 0xE8 -#define MT6370_REG_FLEDMASK1 0xE9 -#define MT6370_REG_FLEDMASK2 0xEA -#define MT6370_REG_BASEMASK 0xEB -#define MT6370_REG_LDOMASK 0xEC -#define MT6370_REG_RGBMASK 0xED -#define MT6370_REG_BLMASK 0xEE -#define MT6370_REG_DBMASK 0xEF -#define MT6370_REG_TM_PAS_CODE1 0xF0 -#define MT6370_REG_BANK 0xFF +#define MT6370_REG_CHGMASK1 0xE0 +#define RT946X_REG_CHGSTATCCTRL MT6370_REG_CHGMASK1 +#define MT6370_REG_CHGMASK2 0xE1 +#define MT6370_REG_CHGMASK3 0xE2 +#define MT6370_REG_CHGMASK4 0xE3 +#define MT6370_REG_CHGMASK5 0xE4 +#define MT6370_REG_CHGMASK6 0xE5 +#define MT6370_REG_DPDMMASK1 0xE6 +#define MT6370_REG_DICHGMASK 0xE7 +#define MT6370_REG_OVPCTRLMASK 0xE8 +#define MT6370_REG_FLEDMASK1 0xE9 +#define MT6370_REG_FLEDMASK2 0xEA +#define MT6370_REG_BASEMASK 0xEB +#define MT6370_REG_LDOMASK 0xEC +#define MT6370_REG_RGBMASK 0xED +#define MT6370_REG_BLMASK 0xEE +#define MT6370_REG_DBMASK 0xEF +#define MT6370_REG_TM_PAS_CODE1 0xF0 +#define MT6370_REG_BANK 0xFF /* TM REGISTER */ -#define MT6370_TM_REG_BL3 0x34 -#define MT6370_TM_REG_DSV1 0x37 +#define MT6370_TM_REG_BL3 0x34 +#define MT6370_TM_REG_DSV1 0x37 #else #error "No suitable charger option defined" #endif /* EOC current */ -#define RT946X_IEOC_MIN 100 -#define RT946X_IEOC_MAX 850 -#define RT946X_IEOC_STEP 50 +#define RT946X_IEOC_MIN 100 +#define RT946X_IEOC_MAX 850 +#define RT946X_IEOC_STEP 50 /* Minimum Input Voltage Regulator */ -#define RT946X_MIVR_MIN 3900 -#define RT946X_MIVR_MAX 13400 -#define RT946X_MIVR_STEP 100 +#define RT946X_MIVR_MIN 3900 +#define RT946X_MIVR_MAX 13400 +#define RT946X_MIVR_STEP 100 /* Boost voltage */ -#define RT946X_BOOST_VOLTAGE_MIN 4425 -#define RT946X_BOOST_VOLTAGE_MAX 5825 -#define RT946X_BOOST_VOLTAGE_STEP 25 +#define RT946X_BOOST_VOLTAGE_MIN 4425 +#define RT946X_BOOST_VOLTAGE_MAX 5825 +#define RT946X_BOOST_VOLTAGE_STEP 25 /* IR compensation resistor */ -#define RT946X_IRCMP_RES_MIN 0 -#define RT946X_IRCMP_RES_MAX 175 -#define RT946X_IRCMP_RES_STEP 25 +#define RT946X_IRCMP_RES_MIN 0 +#define RT946X_IRCMP_RES_MAX 175 +#define RT946X_IRCMP_RES_STEP 25 /* IR compensation voltage clamp */ -#define RT946X_IRCMP_VCLAMP_MIN 0 -#define RT946X_IRCMP_VCLAMP_MAX 224 -#define RT946X_IRCMP_VCLAMP_STEP 32 +#define RT946X_IRCMP_VCLAMP_MIN 0 +#define RT946X_IRCMP_VCLAMP_MAX 224 +#define RT946X_IRCMP_VCLAMP_STEP 32 /* Pre-charge mode threshold voltage */ -#define RT946X_VPREC_MIN 2000 -#define RT946X_VPREC_MAX 3500 -#define RT946X_VPREC_STEP 100 +#define RT946X_VPREC_MIN 2000 +#define RT946X_VPREC_MAX 3500 +#define RT946X_VPREC_STEP 100 /* Pre-charge current */ -#define RT946X_IPREC_MIN 100 -#define RT946X_IPREC_MAX 850 -#define RT946X_IPREC_STEP 50 +#define RT946X_IPREC_MIN 100 +#define RT946X_IPREC_MAX 850 +#define RT946X_IPREC_STEP 50 /* AICLVTH */ -#define RT946X_AICLVTH_MIN 4100 -#define RT946X_AICLVTH_MAX 4800 -#define RT946X_AICLVTH_STEP 100 +#define RT946X_AICLVTH_MIN 4100 +#define RT946X_AICLVTH_MAX 4800 +#define RT946X_AICLVTH_STEP 100 /* NTC */ -#define RT946X_BATTEMP_NORMAL 0x00 -#define RT946X_BATTEMP_WARM 0x02 -#define RT946X_BATTEMP_COOL 0x03 -#define RT946X_BATTEMP_COLD 0x05 -#define RT946X_BATTEMP_HOT 0x06 +#define RT946X_BATTEMP_NORMAL 0x00 +#define RT946X_BATTEMP_WARM 0x02 +#define RT946X_BATTEMP_COOL 0x03 +#define RT946X_BATTEMP_COLD 0x05 +#define RT946X_BATTEMP_HOT 0x06 /* LDO voltage */ -#define MT6370_LDO_MIN 1600 -#define MT6370_LDO_MAX 4000 -#define MT6370_LDO_STEP 200 +#define MT6370_LDO_MIN 1600 +#define MT6370_LDO_MAX 4000 +#define MT6370_LDO_STEP 200 /* ========== CORECTRL0 0x00 ============ */ -#define RT946X_SHIFT_RST 7 -#define RT946X_SHIFT_CHG_RST 6 -#define RT946X_SHIFT_FLED_RST 5 -#define RT946X_SHIFT_LDO_RST 4 -#define RT946X_SHIFT_RGB_RST 3 -#define RT946X_SHIFT_BL_RST 2 -#define RT946X_SHIFT_DB_RST 1 -#define RT946X_SHIFT_REG_RST 0 - -#define RT946X_MASK_RST BIT(RT946X_SHIFT_RST) -#define RT946X_MASK_CHG_RST BIT(RT946X_SHIFT_CHG_RST) -#define RT946X_MASK_FLED_RST BIT(RT946X_SHIFT_FLED_RST) -#define RT946X_MASK_LDO_RST BIT(RT946X_SHIFT_LDO_RST) -#define RT946X_MASK_RGB_RST BIT(RT946X_SHIFT_RGB_RST) -#define RT946X_MASK_BL_RST BIT(RT946X_SHIFT_BL_RST) -#define RT946X_MASK_DB_RST BIT(RT946X_SHIFT_DB_RST) -#define RT946X_MASK_REG_RST BIT(RT946X_SHIFT_REG_RST) -#define RT946X_MASK_SOFT_RST \ - (RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST | \ - RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST | \ +#define RT946X_SHIFT_RST 7 +#define RT946X_SHIFT_CHG_RST 6 +#define RT946X_SHIFT_FLED_RST 5 +#define RT946X_SHIFT_LDO_RST 4 +#define RT946X_SHIFT_RGB_RST 3 +#define RT946X_SHIFT_BL_RST 2 +#define RT946X_SHIFT_DB_RST 1 +#define RT946X_SHIFT_REG_RST 0 + +#define RT946X_MASK_RST BIT(RT946X_SHIFT_RST) +#define RT946X_MASK_CHG_RST BIT(RT946X_SHIFT_CHG_RST) +#define RT946X_MASK_FLED_RST BIT(RT946X_SHIFT_FLED_RST) +#define RT946X_MASK_LDO_RST BIT(RT946X_SHIFT_LDO_RST) +#define RT946X_MASK_RGB_RST BIT(RT946X_SHIFT_RGB_RST) +#define RT946X_MASK_BL_RST BIT(RT946X_SHIFT_BL_RST) +#define RT946X_MASK_DB_RST BIT(RT946X_SHIFT_DB_RST) +#define RT946X_MASK_REG_RST BIT(RT946X_SHIFT_REG_RST) +#define RT946X_MASK_SOFT_RST \ + (RT946X_MASK_CHG_RST | RT946X_MASK_FLED_RST | RT946X_MASK_LDO_RST | \ + RT946X_MASK_RGB_RST | RT946X_MASK_BL_RST | RT946X_MASK_DB_RST | \ RT946X_MASK_REG_RST) /* ========== CHGCTRL1 0x01 ============ */ -#define RT946X_SHIFT_OPA_MODE 0 -#define RT946X_SHIFT_HZ_EN 2 -#define RT946X_SHIFT_STAT_EN 4 +#define RT946X_SHIFT_OPA_MODE 0 +#define RT946X_SHIFT_HZ_EN 2 +#define RT946X_SHIFT_STAT_EN 4 -#define RT946X_MASK_OPA_MODE BIT(RT946X_SHIFT_OPA_MODE) -#define RT946X_MASK_HZ_EN BIT(RT946X_SHIFT_HZ_EN) -#define RT946X_MASK_STAT_EN BIT(RT946X_SHIFT_STAT_EN) +#define RT946X_MASK_OPA_MODE BIT(RT946X_SHIFT_OPA_MODE) +#define RT946X_MASK_HZ_EN BIT(RT946X_SHIFT_HZ_EN) +#define RT946X_MASK_STAT_EN BIT(RT946X_SHIFT_STAT_EN) /* ========== CHGCTRL2 0x02 ============ */ -#define RT946X_SHIFT_SHIP_MODE 7 -#define RT946X_SHIFT_BATDET_DIS_DLY 6 -#define RT946X_SHIFT_TE 4 -#define RT946X_SHIFT_ILMTSEL 2 -#define RT946X_SHIFT_CFO_EN 1 -#define RT946X_SHIFT_CHG_EN 0 - -#define RT946X_MASK_SHIP_MODE BIT(RT946X_SHIFT_SHIP_MODE) -#define RT946X_MASK_TE BIT(RT946X_SHIFT_TE) -#define RT946X_MASK_ILMTSEL (0x3 << RT946X_SHIFT_ILMTSEL) -#define RT946X_MASK_CFO_EN BIT(RT946X_SHIFT_CFO_EN) -#define RT946X_MASK_CHG_EN BIT(RT946X_SHIFT_CHG_EN) +#define RT946X_SHIFT_SHIP_MODE 7 +#define RT946X_SHIFT_BATDET_DIS_DLY 6 +#define RT946X_SHIFT_TE 4 +#define RT946X_SHIFT_ILMTSEL 2 +#define RT946X_SHIFT_CFO_EN 1 +#define RT946X_SHIFT_CHG_EN 0 + +#define RT946X_MASK_SHIP_MODE BIT(RT946X_SHIFT_SHIP_MODE) +#define RT946X_MASK_TE BIT(RT946X_SHIFT_TE) +#define RT946X_MASK_ILMTSEL (0x3 << RT946X_SHIFT_ILMTSEL) +#define RT946X_MASK_CFO_EN BIT(RT946X_SHIFT_CFO_EN) +#define RT946X_MASK_CHG_EN BIT(RT946X_SHIFT_CHG_EN) /* ========== RSTPASCODE1 0x03 (mt6370) ============ */ -#define MT6370_MASK_RSTPASCODE1 0xA9 +#define MT6370_MASK_RSTPASCODE1 0xA9 /* ========== CHGCTRL3 0x03 ============ */ -#define RT946X_SHIFT_AICR 2 -#define RT946X_SHIFT_ILIMEN 0 +#define RT946X_SHIFT_AICR 2 +#define RT946X_SHIFT_ILIMEN 0 -#define RT946X_MASK_AICR (0x3F << RT946X_SHIFT_AICR) -#define RT946X_MASK_ILIMEN BIT(RT946X_SHIFT_ILIMEN) +#define RT946X_MASK_AICR (0x3F << RT946X_SHIFT_AICR) +#define RT946X_MASK_ILIMEN BIT(RT946X_SHIFT_ILIMEN) /* * The accuracy of AICR is 7%. So if AICR = 2150, * then Max=2150, Typ=2000, Min=1860. And plus 25 since the AICR * is 50ma a step. */ -#define RT946X_AICR_TYP2MAX(x) ((x) * 107 / 100 + 25) +#define RT946X_AICR_TYP2MAX(x) ((x)*107 / 100 + 25) /* ========== RSTPASCODE2 0x04 (mt6370) ============ */ -#define MT6370_MASK_RSTPASCODE2 0x96 +#define MT6370_MASK_RSTPASCODE2 0x96 /* ========== CHGCTRL4 0x04 ============ */ -#define RT946X_SHIFT_CV 1 +#define RT946X_SHIFT_CV 1 -#define RT946X_MASK_CV 0xFE +#define RT946X_MASK_CV 0xFE /* ========== CHGCTRL5 0x05 ============ */ -#define RT946X_SHIFT_BOOST_VOLTAGE 2 +#define RT946X_SHIFT_BOOST_VOLTAGE 2 -#define RT946X_MASK_BOOST_VOLTAGE 0xFC +#define RT946X_MASK_BOOST_VOLTAGE 0xFC /* ========== CHGCTRL6 0x06 ============ */ -#define RT946X_SHIFT_MIVR 1 +#define RT946X_SHIFT_MIVR 1 -#define RT946X_MASK_MIVR (0x7F << RT946X_SHIFT_MIVR) +#define RT946X_MASK_MIVR (0x7F << RT946X_SHIFT_MIVR) /* ========== CHGCTRL7 0x07 ============ */ -#define RT946X_SHIFT_ICHG 2 +#define RT946X_SHIFT_ICHG 2 -#define RT946X_MASK_ICHG (0x3F << RT946X_SHIFT_ICHG) +#define RT946X_MASK_ICHG (0x3F << RT946X_SHIFT_ICHG) /* ========== CHGCTRL8 0x08 ============ */ -#define RT946X_SHIFT_VPREC 4 -#define RT946X_SHIFT_IPREC 0 +#define RT946X_SHIFT_VPREC 4 +#define RT946X_SHIFT_IPREC 0 -#define RT946X_MASK_VPREC (0xF << RT946X_SHIFT_VPREC) -#define RT946X_MASK_IPREC (0xF << RT946X_SHIFT_IPREC) +#define RT946X_MASK_VPREC (0xF << RT946X_SHIFT_VPREC) +#define RT946X_MASK_IPREC (0xF << RT946X_SHIFT_IPREC) /* ========== CHGCTRL9 0x09 ============ */ -#define RT946X_SHIFT_EOC 3 -#define RT946X_SHIFT_IEOC 4 +#define RT946X_SHIFT_EOC 3 +#define RT946X_SHIFT_IEOC 4 -#define RT946X_MASK_EOC BIT(RT946X_SHIFT_EOC) -#define RT946X_MASK_IEOC (0xF << RT946X_SHIFT_IEOC) +#define RT946X_MASK_EOC BIT(RT946X_SHIFT_EOC) +#define RT946X_MASK_IEOC (0xF << RT946X_SHIFT_IEOC) /* ========== CHGCTRL10 0x0A ============ */ -#define RT946X_SHIFT_BOOST_CURRENT 0 +#define RT946X_SHIFT_BOOST_CURRENT 0 -#define RT946X_MASK_BOOST_CURRENT 0x07 +#define RT946X_MASK_BOOST_CURRENT 0x07 /* ========== CHGCTRL12 0x0C ============ */ -#define RT946X_SHIFT_TMR_EN 1 -#define MT6370_IRQ_MASK_ALL 0xFE +#define RT946X_SHIFT_TMR_EN 1 +#define MT6370_IRQ_MASK_ALL 0xFE -#define RT946X_MASK_TMR_EN BIT(RT946X_SHIFT_TMR_EN) +#define RT946X_MASK_TMR_EN BIT(RT946X_SHIFT_TMR_EN) /* ========== CHGCTRL13 0x0D ============ */ -#define RT946X_SHIFT_WDT_EN 7 +#define RT946X_SHIFT_WDT_EN 7 -#define RT946X_MASK_WDT_EN BIT(RT946X_SHIFT_WDT_EN) +#define RT946X_MASK_WDT_EN BIT(RT946X_SHIFT_WDT_EN) /* ========== CHGCTRL14 0x0E ============ */ -#define RT946X_SHIFT_AICLMEAS 7 -#define RT946X_SHIFT_AICLVTH 0 +#define RT946X_SHIFT_AICLMEAS 7 +#define RT946X_SHIFT_AICLVTH 0 -#define RT946X_MASK_AICLMEAS BIT(RT946X_SHIFT_AICLMEAS) -#define RT946X_MASK_AICLVTH 0x07 +#define RT946X_MASK_AICLMEAS BIT(RT946X_SHIFT_AICLMEAS) +#define RT946X_MASK_AICLVTH 0x07 /* ========== CHGCTRL16 0x10 ============ */ -#define RT946X_SHIFT_JEITA_EN 4 +#define RT946X_SHIFT_JEITA_EN 4 -#define RT946X_MASK_JEITA_EN BIT(RT946X_SHIFT_JEITA_EN) +#define RT946X_MASK_JEITA_EN BIT(RT946X_SHIFT_JEITA_EN) /* ========== CHGADC 0x11 ============ */ -#define RT946X_SHIFT_ADC_IN_SEL 4 -#define RT946X_SHIFT_ADC_START 0 +#define RT946X_SHIFT_ADC_IN_SEL 4 +#define RT946X_SHIFT_ADC_START 0 -#define RT946X_MASK_ADC_IN_SEL (0xF << RT946X_SHIFT_ADC_IN_SEL) -#define RT946X_MASK_ADC_START BIT(RT946X_SHIFT_ADC_START) +#define RT946X_MASK_ADC_IN_SEL (0xF << RT946X_SHIFT_ADC_IN_SEL) +#define RT946X_MASK_ADC_START BIT(RT946X_SHIFT_ADC_START) /* ========== CHGDPDM1 0x12 (rt946x) DEVICETYPE 0x22 (mt6370) ============ */ -#define RT946X_SHIFT_USBCHGEN 7 -#define RT946X_SHIFT_DCDTIMEOUT 6 -#define RT946X_SHIFT_DCP 2 -#define RT946X_SHIFT_CDP 1 -#define RT946X_SHIFT_SDP 0 - -#define RT946X_MASK_USBCHGEN BIT(RT946X_SHIFT_USBCHGEN) -#define RT946X_MASK_DCDTIMEOUT BIT(RT946X_SHIFT_DCDTIMEOUT) -#define RT946X_MASK_DCP BIT(RT946X_SHIFT_DCP) -#define RT946X_MASK_CDP BIT(RT946X_SHIFT_CDP) -#define RT946X_MASK_SDP BIT(RT946X_SHIFT_SDP) - -#define RT946X_MASK_BC12_TYPE (RT946X_MASK_DCP | \ - RT946X_MASK_CDP | \ - RT946X_MASK_SDP) +#define RT946X_SHIFT_USBCHGEN 7 +#define RT946X_SHIFT_DCDTIMEOUT 6 +#define RT946X_SHIFT_DCP 2 +#define RT946X_SHIFT_CDP 1 +#define RT946X_SHIFT_SDP 0 + +#define RT946X_MASK_USBCHGEN BIT(RT946X_SHIFT_USBCHGEN) +#define RT946X_MASK_DCDTIMEOUT BIT(RT946X_SHIFT_DCDTIMEOUT) +#define RT946X_MASK_DCP BIT(RT946X_SHIFT_DCP) +#define RT946X_MASK_CDP BIT(RT946X_SHIFT_CDP) +#define RT946X_MASK_SDP BIT(RT946X_SHIFT_SDP) + +#define RT946X_MASK_BC12_TYPE \ + (RT946X_MASK_DCP | RT946X_MASK_CDP | RT946X_MASK_SDP) /* ========== USBSTATUS1 0x27 (mt6370) ============ */ -#define MT6370_SHIFT_DCD_TIMEOUT 2 -#define MT6370_SHIFT_USB_STATUS 4 +#define MT6370_SHIFT_DCD_TIMEOUT 2 +#define MT6370_SHIFT_USB_STATUS 4 -#define MT6370_MASK_USB_STATUS 0x70 +#define MT6370_MASK_USB_STATUS 0x70 -#define MT6370_CHG_TYPE_NOVBUS 0 -#define MT6370_CHG_TYPE_BUSY 1 -#define MT6370_CHG_TYPE_SDP 2 -#define MT6370_CHG_TYPE_SDPNSTD 3 -#define MT6370_CHG_TYPE_DCP 4 -#define MT6370_CHG_TYPE_CDP 5 -#define MT6370_CHG_TYPE_SAMSUNG_CHARGER 6 -#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER 7 -#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER 8 -#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER 9 -#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER 10 +#define MT6370_CHG_TYPE_NOVBUS 0 +#define MT6370_CHG_TYPE_BUSY 1 +#define MT6370_CHG_TYPE_SDP 2 +#define MT6370_CHG_TYPE_SDPNSTD 3 +#define MT6370_CHG_TYPE_DCP 4 +#define MT6370_CHG_TYPE_CDP 5 +#define MT6370_CHG_TYPE_SAMSUNG_CHARGER 6 +#define MT6370_CHG_TYPE_APPLE_0_5A_CHARGER 7 +#define MT6370_CHG_TYPE_APPLE_1_0A_CHARGER 8 +#define MT6370_CHG_TYPE_APPLE_2_1A_CHARGER 9 +#define MT6370_CHG_TYPE_APPLE_2_4A_CHARGER 10 -#define MT6370_MASK_DCD_TIMEOUT BIT(MT6370_SHIFT_DCD_TIMEOUT) +#define MT6370_MASK_DCD_TIMEOUT BIT(MT6370_SHIFT_DCD_TIMEOUT) /* ========== QCSTATUS2 0x29 (mt6370) ============ */ -#define MT6370_SHIFT_APP_OUT 5 -#define MT6370_SHIFT_SS_OUT 4 -#define MT6370_SHIFT_APP_REF 3 -#define MT6370_SHIFT_APP_DPDM_IN 2 -#define MT6370_SHIFT_APP_SS_PL 1 -#define MT6370_SHIFT_APP_SS_EN 0 - -#define MT6370_MASK_APP_OUT BIT(MT6370_SHIFT_APP_OUT) -#define MT6370_MASK_SS_OUT BIT(MT6370_SHIFT_SS_OUT) -#define MT6370_MASK_APP_REF BIT(MT6370_SHIFT_APP_REF) -#define MT6370_MASK_APP_DPDM_IN BIT(MT6370_SHIFT_APP_DPDM_IN) -#define MT6370_MASK_APP_SS_PL BIT(MT6370_SHIFT_APP_SS_PL) -#define MT6370_MASK_APP_SS_EN BIT(MT6370_SHIFT_APP_SS_EN) - -#define MT6360_MASK_CHECK_DPDM (MT6370_MASK_APP_SS_EN | \ - MT6370_MASK_APP_SS_PL | \ - MT6370_MASK_APP_DPDM_IN | \ - MT6370_MASK_APP_REF) +#define MT6370_SHIFT_APP_OUT 5 +#define MT6370_SHIFT_SS_OUT 4 +#define MT6370_SHIFT_APP_REF 3 +#define MT6370_SHIFT_APP_DPDM_IN 2 +#define MT6370_SHIFT_APP_SS_PL 1 +#define MT6370_SHIFT_APP_SS_EN 0 + +#define MT6370_MASK_APP_OUT BIT(MT6370_SHIFT_APP_OUT) +#define MT6370_MASK_SS_OUT BIT(MT6370_SHIFT_SS_OUT) +#define MT6370_MASK_APP_REF BIT(MT6370_SHIFT_APP_REF) +#define MT6370_MASK_APP_DPDM_IN BIT(MT6370_SHIFT_APP_DPDM_IN) +#define MT6370_MASK_APP_SS_PL BIT(MT6370_SHIFT_APP_SS_PL) +#define MT6370_MASK_APP_SS_EN BIT(MT6370_SHIFT_APP_SS_EN) + +#define MT6360_MASK_CHECK_DPDM \ + (MT6370_MASK_APP_SS_EN | MT6370_MASK_APP_SS_PL | \ + MT6370_MASK_APP_DPDM_IN | MT6370_MASK_APP_REF) /* ========= CHGHIDDENCTRL7 0x36 (mt6370) ======== */ -#define RT946X_ENABLE_VSYS_PROTECT 0x40 +#define RT946X_ENABLE_VSYS_PROTECT 0x40 -#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT 5 +#define RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT 5 #define RT946X_MASK_HIDDENCTRL7_VSYS_PROTECT \ (0x3 << RT946X_SHIFT_HIDDENCTRL7_VSYS_PROTECT) /* ========== CHGCTRL18 0x1A ============ */ -#define RT946X_SHIFT_IRCMP_RES 3 -#define RT946X_SHIFT_IRCMP_VCLAMP 0 +#define RT946X_SHIFT_IRCMP_RES 3 +#define RT946X_SHIFT_IRCMP_VCLAMP 0 -#define RT946X_MASK_IRCMP_RES (0x7 << RT946X_SHIFT_IRCMP_RES) -#define RT946X_MASK_IRCMP_VCLAMP (0x7 << RT946X_SHIFT_IRCMP_VCLAMP) +#define RT946X_MASK_IRCMP_RES (0x7 << RT946X_SHIFT_IRCMP_RES) +#define RT946X_MASK_IRCMP_VCLAMP (0x7 << RT946X_SHIFT_IRCMP_VCLAMP) /* ========== HIDDEN CTRL15 0x3E ============ */ -#define MT6370_SHIFT_ADC_TS_AUTO 0 -#define MT6370_MASK_ADC_TS_AUTO BIT(MT6370_SHIFT_ADC_TS_AUTO) +#define MT6370_SHIFT_ADC_TS_AUTO 0 +#define MT6370_MASK_ADC_TS_AUTO BIT(MT6370_SHIFT_ADC_TS_AUTO) /* ========== DEVICE_ID 0x40 ============ */ -#define RT946X_MASK_VENDOR_ID 0xF0 -#define RT946X_MASK_CHIP_REV 0x0F +#define RT946X_MASK_VENDOR_ID 0xF0 +#define RT946X_MASK_CHIP_REV 0x0F /* ========== CHGSTAT 0x42 ============ */ -#define RT946X_SHIFT_CHG_STAT 6 -#define RT946X_SHIFT_ADC_STAT 0 +#define RT946X_SHIFT_CHG_STAT 6 +#define RT946X_SHIFT_ADC_STAT 0 -#define RT946X_MASK_CHG_STAT (0x3 << RT946X_SHIFT_CHG_STAT) -#define RT946X_MASK_ADC_STAT BIT(RT946X_SHIFT_ADC_STAT) +#define RT946X_MASK_CHG_STAT (0x3 << RT946X_SHIFT_CHG_STAT) +#define RT946X_MASK_ADC_STAT BIT(RT946X_SHIFT_ADC_STAT) /* ========== CHGNTC 0x43 ============ */ -#define RT946X_SHIFT_BATNTC_FAULT 4 +#define RT946X_SHIFT_BATNTC_FAULT 4 -#define RT946X_MASK_BATNTC_FAULT 0x70 +#define RT946X_MASK_BATNTC_FAULT 0x70 /* ========== CHGSTATC 0x50 (rt946x) ============ */ -#define RT946X_SHIFT_PWR_RDY 7 +#define RT946X_SHIFT_PWR_RDY 7 -#define RT946X_MASK_PWR_RDY BIT(RT946X_SHIFT_PWR_RDY) +#define RT946X_MASK_PWR_RDY BIT(RT946X_SHIFT_PWR_RDY) /* ========== CHGFAULT 0x51 (rt946x) ============ */ #if defined(CONFIG_CHARGER_RT9466) || defined(CONFIG_CHARGER_RT9467) -#define RT946X_SHIFT_CHG_VSYSUV 4 -#define RT946X_SHIFT_CHG_VSYSOV 5 -#define RT946X_SHIFT_CHG_VBATOV 6 -#define RT946X_SHIFT_CHG_VBUSOV 7 - -#define RT946X_MASK_CHG_VSYSUV BIT(RT946X_SHIFT_CHG_VSYSUV) -#define RT946X_MASK_CHG_VSYSOV BIT(RT946X_SHIFT_CHG_VSYSOV) -#define RT946X_MASK_CHG_VBATOV BIT(RT946X_SHIFT_CHG_VBATOV) -#define RT946X_MASK_CHG_VBUSOV BIT(RT946X_SHIFT_CHG_VBUSOV) +#define RT946X_SHIFT_CHG_VSYSUV 4 +#define RT946X_SHIFT_CHG_VSYSOV 5 +#define RT946X_SHIFT_CHG_VBATOV 6 +#define RT946X_SHIFT_CHG_VBUSOV 7 + +#define RT946X_MASK_CHG_VSYSUV BIT(RT946X_SHIFT_CHG_VSYSUV) +#define RT946X_MASK_CHG_VSYSOV BIT(RT946X_SHIFT_CHG_VSYSOV) +#define RT946X_MASK_CHG_VBATOV BIT(RT946X_SHIFT_CHG_VBATOV) +#define RT946X_MASK_CHG_VBUSOV BIT(RT946X_SHIFT_CHG_VBUSOV) #endif /* ========== DPDMIRQ 0x56 ============ */ #if defined(CONFIG_CHARGER_RT9467) || defined(CONFIG_CHARGER_MT6370) -#define RT946X_SHIFT_DPDMIRQ_DETACH 1 -#define RT946X_SHIFT_DPDMIRQ_ATTACH 0 +#define RT946X_SHIFT_DPDMIRQ_DETACH 1 +#define RT946X_SHIFT_DPDMIRQ_ATTACH 0 -#define RT946X_MASK_DPDMIRQ_DETACH BIT(RT946X_SHIFT_DPDMIRQ_DETACH) -#define RT946X_MASK_DPDMIRQ_ATTACH BIT(RT946X_SHIFT_DPDMIRQ_ATTACH) +#define RT946X_MASK_DPDMIRQ_DETACH BIT(RT946X_SHIFT_DPDMIRQ_DETACH) +#define RT946X_MASK_DPDMIRQ_ATTACH BIT(RT946X_SHIFT_DPDMIRQ_ATTACH) #endif /* ========== FLED EN 0x7E (mt6370) ============ */ -#define MT6370_STROBE_EN_MASK 0x04 +#define MT6370_STROBE_EN_MASK 0x04 /* ========== LDOCFG 0x80 (mt6370) ============ */ -#define MT6370_SHIFT_LDOCFG_OMS 6 +#define MT6370_SHIFT_LDOCFG_OMS 6 -#define MT6370_MASK_LDOCFG_OMS BIT(MT6370_SHIFT_LDOCFG_OMS) +#define MT6370_MASK_LDOCFG_OMS BIT(MT6370_SHIFT_LDOCFG_OMS) /* ========== LDOVOUT 0x81 (mt6370) ============ */ -#define MT6370_SHIFT_LDOVOUT_EN 7 -#define MT6370_SHIFT_LDOVOUT_VOUT 0 +#define MT6370_SHIFT_LDOVOUT_EN 7 +#define MT6370_SHIFT_LDOVOUT_VOUT 0 -#define MT6370_MASK_LDOVOUT_EN BIT(MT6370_SHIFT_LDOVOUT_EN) -#define MT6370_MASK_LDOVOUT_VOUT (0xf << MT6370_SHIFT_LDOVOUT_VOUT) +#define MT6370_MASK_LDOVOUT_EN BIT(MT6370_SHIFT_LDOVOUT_EN) +#define MT6370_MASK_LDOVOUT_VOUT (0xf << MT6370_SHIFT_LDOVOUT_VOUT) /* ========== RGBDIM 0x82/0x83/0x84 (mt6370) ============ */ -#define MT6370_LED_PWM_DIMDUTY_MIN 0x00 -#define MT6370_LED_PWM_DIMDUTY_MAX 0x1f +#define MT6370_LED_PWM_DIMDUTY_MIN 0x00 +#define MT6370_LED_PWM_DIMDUTY_MAX 0x1f -#define MT6370_SHIFT_RGB_DIMMODE 5 -#define MT6370_SHIFT_RGB_DIMDUTY 0 +#define MT6370_SHIFT_RGB_DIMMODE 5 +#define MT6370_SHIFT_RGB_DIMDUTY 0 -#define MT6370_MASK_RGB_DIMMODE (3 << MT6370_SHIFT_RGB_DIMMODE) -#define MT6370_MASK_RGB_DIMDUTY (0x1f << MT6370_SHIFT_RGB_DIMDUTY) +#define MT6370_MASK_RGB_DIMMODE (3 << MT6370_SHIFT_RGB_DIMMODE) +#define MT6370_MASK_RGB_DIMDUTY (0x1f << MT6370_SHIFT_RGB_DIMDUTY) /* ========== RGBEN 0x85 (mt6370) ============ */ -#define MT6370_SHIFT_RGB_ISNK1DIM 7 -#define MT6370_SHIFT_RGB_ISNK2DIM 6 -#define MT6370_SHIFT_RGB_ISNK3DIM 5 -#define MT6370_SHIFT_RGB_ISNKDIM_BASE 8 - -#define MT6370_MASK_RGB_ISNK1DIM_EN BIT(MT6370_SHIFT_RGB_ISNK1DIM) -#define MT6370_MASK_RGB_ISNK2DIM_EN BIT(MT6370_SHIFT_RGB_ISNK2DIM) -#define MT6370_MASK_RGB_ISNK3DIM_EN BIT(MT6370_SHIFT_RGB_ISNK3DIM) -#define MT6370_MASK_RGB_ISNK_ALL_EN (MT6370_MASK_RGB_ISNK1DIM_EN | \ - MT6370_MASK_RGB_ISNK2DIM_EN | \ - MT6370_MASK_RGB_ISNK3DIM_EN) +#define MT6370_SHIFT_RGB_ISNK1DIM 7 +#define MT6370_SHIFT_RGB_ISNK2DIM 6 +#define MT6370_SHIFT_RGB_ISNK3DIM 5 +#define MT6370_SHIFT_RGB_ISNKDIM_BASE 8 + +#define MT6370_MASK_RGB_ISNK1DIM_EN BIT(MT6370_SHIFT_RGB_ISNK1DIM) +#define MT6370_MASK_RGB_ISNK2DIM_EN BIT(MT6370_SHIFT_RGB_ISNK2DIM) +#define MT6370_MASK_RGB_ISNK3DIM_EN BIT(MT6370_SHIFT_RGB_ISNK3DIM) +#define MT6370_MASK_RGB_ISNK_ALL_EN \ + (MT6370_MASK_RGB_ISNK1DIM_EN | MT6370_MASK_RGB_ISNK2DIM_EN | \ + MT6370_MASK_RGB_ISNK3DIM_EN) /* ========== RGB_ISNK 0x86/0x87/0x88 (mt6370) ============ */ #define MT6370_LED_BRIGHTNESS_MIN 0 #define MT6370_LED_BRIGHTNESS_MAX 7 -#define MT6370_SHIFT_RGBISNK_CURSEL 0 -#define MT6370_SHIFT_RGBISNK_DIMFSEL 3 -#define MT6370_MASK_RGBISNK_CURSEL (0x7 << MT6370_SHIFT_RGBISNK_CURSEL) -#define MT6370_MASK_RGBISNK_DIMFSEL (0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL) +#define MT6370_SHIFT_RGBISNK_CURSEL 0 +#define MT6370_SHIFT_RGBISNK_DIMFSEL 3 +#define MT6370_MASK_RGBISNK_CURSEL (0x7 << MT6370_SHIFT_RGBISNK_CURSEL) +#define MT6370_MASK_RGBISNK_DIMFSEL (0x7 << MT6370_SHIFT_RGBISNK_DIMFSEL) /* ========== DBCTRL1 (mt6370) ============ */ -#define MT6370_SHIFT_DB_EXT_EN 0 -#define MT6370_SHIFT_DB_PERIODIC_FIX 4 -#define MT6370_SHIFT_DB_SINGLE_PIN 5 -#define MT6370_SHIFT_DB_FREQ_PM 6 -#define MT6370_SHIFT_DB_PERIODIC_MODE 7 - -#define MT6370_MASK_DB_EXT_EN 1 -#define MT6370_MASK_DB_PERIODIC_FIX 1 -#define MT6370_MASK_DB_SINGLE_PIN 1 -#define MT6370_MASK_DB_FREQ_PM 1 -#define MT6370_MASK_DB_PERIODIC_MODE 1 +#define MT6370_SHIFT_DB_EXT_EN 0 +#define MT6370_SHIFT_DB_PERIODIC_FIX 4 +#define MT6370_SHIFT_DB_SINGLE_PIN 5 +#define MT6370_SHIFT_DB_FREQ_PM 6 +#define MT6370_SHIFT_DB_PERIODIC_MODE 7 + +#define MT6370_MASK_DB_EXT_EN 1 +#define MT6370_MASK_DB_PERIODIC_FIX 1 +#define MT6370_MASK_DB_SINGLE_PIN 1 +#define MT6370_MASK_DB_FREQ_PM 1 +#define MT6370_MASK_DB_PERIODIC_MODE 1 /* ========== DBCTRL1 (mt6370) ============ */ -#define MT6370_MASK_DB_VNEG_DISC BIT(2) -#define MT6370_MASK_DB_VPOS_DISC BIT(5) +#define MT6370_MASK_DB_VNEG_DISC BIT(2) +#define MT6370_MASK_DB_VPOS_DISC BIT(5) /* ========== DBVBST (mt6370) ============ */ -#define MT6370_SHIFT_DB_VBST 0 +#define MT6370_SHIFT_DB_VBST 0 -#define MT6370_MASK_DB_VBST 0x3f +#define MT6370_MASK_DB_VBST 0x3f -#define MT6370_DB_VBST_MAX 6200 -#define MT6370_DB_VBST_MIN 4000 -#define MT6370_DB_VBST_STEP 50 +#define MT6370_DB_VBST_MAX 6200 +#define MT6370_DB_VBST_MIN 4000 +#define MT6370_DB_VBST_STEP 50 /* ========== DBVPOS (mt6370) ============ */ -#define MT6370_SHIFT_DB_VPOS 0 +#define MT6370_SHIFT_DB_VPOS 0 -#define MT6370_MASK_DB_VPOS 0x3f +#define MT6370_MASK_DB_VPOS 0x3f -#define MT6370_DB_VPOS_MAX 6000 -#define MT6370_DB_VPOS_MIN 4000 -#define MT6370_DB_VPOS_STEP 50 +#define MT6370_DB_VPOS_MAX 6000 +#define MT6370_DB_VPOS_MIN 4000 +#define MT6370_DB_VPOS_STEP 50 /* ========== DBVNEG (mt6370) ============ */ -#define MT6370_SHIFT_DB_VNEG 0 +#define MT6370_SHIFT_DB_VNEG 0 -#define MT6370_MASK_DB_VNEG 0x3f +#define MT6370_MASK_DB_VNEG 0x3f -#define MT6370_DB_VNEG_MAX 6000 -#define MT6370_DB_VNEG_MIN 4000 -#define MT6370_DB_VNEG_STEP 50 +#define MT6370_DB_VNEG_MAX 6000 +#define MT6370_DB_VNEG_MIN 4000 +#define MT6370_DB_VNEG_STEP 50 /* ========== BLEN 0xA0 (mt6370) ============ */ -#define MT6370_SHIFT_BLED_EXT_EN 7 -#define MT6370_SHIFT_BLED_EN 6 -#define MT6370_SHIFT_BLED_1CH_EN 5 -#define MT6370_SHIFT_BLED_2CH_EN 4 -#define MT6370_SHIFT_BLED_3CH_EN 3 -#define MT6370_SHIFT_BLED_4CH_EN 2 -#define MT6370_SHIFT_BLED_CODE 1 -#define MT6370_SHIFT_BLED_CONFIG 0 - -#define MT6370_MASK_BLED_EXT_EN BIT(MT6370_SHIFT_BLED_EXT_EN) -#define MT6370_MASK_BLED_EN BIT(MT6370_SHIFT_BLED_EN) -#define MT6370_MASK_BLED_1CH_EN BIT(MT6370_SHIFT_BLED_1CH_EN) -#define MT6370_MASK_BLED_2CH_EN BIT(MT6370_SHIFT_BLED_2CH_EN) -#define MT6370_MASK_BLED_3CH_EN BIT(MT6370_SHIFT_BLED_3CH_EN) -#define MT6370_MASK_BLED_4CH_EN BIT(MT6370_SHIFT_BLED_4CH_EN) - -#define MT6370_BLED_CODE_LINEAR BIT(MT6370_SHIFT_BLED_CODE) -#define MT6370_BLED_CODE_EXP 0 - -#define MT6370_BLED_CONFIG_ACTIVE_HIGH BIT(MT6370_SHIFT_BLED_CONFIG) -#define MT6370_BLED_CONFIG_ACTIVE_LOW 0 +#define MT6370_SHIFT_BLED_EXT_EN 7 +#define MT6370_SHIFT_BLED_EN 6 +#define MT6370_SHIFT_BLED_1CH_EN 5 +#define MT6370_SHIFT_BLED_2CH_EN 4 +#define MT6370_SHIFT_BLED_3CH_EN 3 +#define MT6370_SHIFT_BLED_4CH_EN 2 +#define MT6370_SHIFT_BLED_CODE 1 +#define MT6370_SHIFT_BLED_CONFIG 0 + +#define MT6370_MASK_BLED_EXT_EN BIT(MT6370_SHIFT_BLED_EXT_EN) +#define MT6370_MASK_BLED_EN BIT(MT6370_SHIFT_BLED_EN) +#define MT6370_MASK_BLED_1CH_EN BIT(MT6370_SHIFT_BLED_1CH_EN) +#define MT6370_MASK_BLED_2CH_EN BIT(MT6370_SHIFT_BLED_2CH_EN) +#define MT6370_MASK_BLED_3CH_EN BIT(MT6370_SHIFT_BLED_3CH_EN) +#define MT6370_MASK_BLED_4CH_EN BIT(MT6370_SHIFT_BLED_4CH_EN) + +#define MT6370_BLED_CODE_LINEAR BIT(MT6370_SHIFT_BLED_CODE) +#define MT6370_BLED_CODE_EXP 0 + +#define MT6370_BLED_CONFIG_ACTIVE_HIGH BIT(MT6370_SHIFT_BLED_CONFIG) +#define MT6370_BLED_CONFIG_ACTIVE_LOW 0 /* ========== BLPWM 0xA2 (mt6370) ============ */ -#define MT6370_SHIFT_BLPWM_BLED_PWM 7 +#define MT6370_SHIFT_BLPWM_BLED_PWM 7 -#define MT6370_MASK_BLPWM_BLED_PWM BIT(MT6370_SHIFT_BLPWM_BLED_PWM) +#define MT6370_MASK_BLPWM_BLED_PWM BIT(MT6370_SHIFT_BLPWM_BLED_PWM) /* ========== BLDIM2 0xA4 (mt6370) ============ */ -#define MT6370_MASK_BLDIM2 0x7 +#define MT6370_MASK_BLDIM2 0x7 /* ========== BLDIM 0xA5 (mt6370) ============ */ -#define MT6370_SHIFT_BLDIM_MSB 3 -#define MT6370_MASK_BLDIM 0xff +#define MT6370_SHIFT_BLDIM_MSB 3 +#define MT6370_MASK_BLDIM 0xff -#define MT6370_BLDIM_DEFAULT 0x7ff +#define MT6370_BLDIM_DEFAULT 0x7ff /* ========== CHG_IRQ1 0xC0 (mt6370) ============ */ -#define MT6370_SHIFT_MIVR_EVT 6 -#define MT6370_MASK_MIVR_EVT BIT(MT6370_SHIFT_MIVR_EVT) +#define MT6370_SHIFT_MIVR_EVT 6 +#define MT6370_MASK_MIVR_EVT BIT(MT6370_SHIFT_MIVR_EVT) /* ========== CHGSTAT2 0xD0 (mt6370) ============ */ -#define MT6370_SHIFT_MIVR_STAT 6 +#define MT6370_SHIFT_MIVR_STAT 6 /* ========== CHGSTAT2 0xD1 (mt6370) ============ */ #ifdef CONFIG_CHARGER_MT6370 -#define MT6370_SHIFT_CHG_VBUSOV_STAT 7 -#define MT6370_SHIFT_CHG_VBATOV_STAT 6 +#define MT6370_SHIFT_CHG_VBUSOV_STAT 7 +#define MT6370_SHIFT_CHG_VBATOV_STAT 6 -#define RT946X_MASK_CHG_VBATOV MT6370_SHIFT_CHG_VBATOV_STAT +#define RT946X_MASK_CHG_VBATOV MT6370_SHIFT_CHG_VBATOV_STAT -#define MT6370_MASK_CHG_VBUSOV_STAT BIT(MT6370_SHIFT_CHG_VBUSOV_STAT) -#define MT6370_MASK_CHG_VBATOV_STAT BIT(MT6370_SHIFT_CHG_VBATOV_STAT) +#define MT6370_MASK_CHG_VBUSOV_STAT BIT(MT6370_SHIFT_CHG_VBUSOV_STAT) +#define MT6370_MASK_CHG_VBATOV_STAT BIT(MT6370_SHIFT_CHG_VBATOV_STAT) #endif /* ========== TM PAS CODE1 0xF0 (mt6370) ============ */ -#define MT6370_LEAVE_TM 0x00 +#define MT6370_LEAVE_TM 0x00 /* ========== BANK REG 0xFF (mt6370) ============ */ -#define MT6370_MASK_REG_TM 0x69 +#define MT6370_MASK_REG_TM 0x69 /* ========== TM REG 0x34 (mt6370) ============ */ -#define MT6370_TM_MASK_BL3_SL 0xC0 -#define MT6370_TM_REDUCE_BL3_SL 0xC0 +#define MT6370_TM_MASK_BL3_SL 0xC0 +#define MT6370_TM_REDUCE_BL3_SL 0xC0 /* ========== TM REG 0x37 (mt6370) ============ */ -#define MT6370_TM_MASK_DSV1_SL 0xC0 -#define MT6370_TM_REDUCE_DSV1_SL 0x00 +#define MT6370_TM_MASK_DSV1_SL 0xC0 +#define MT6370_TM_REDUCE_DSV1_SL 0x00 /* ADC unit/offset */ -#define MT6370_ADC_UNIT_VBUS_DIV5 25000 /* uV */ -#define MT6370_ADC_UNIT_VBUS_DIV2 10000 /* uV */ -#define MT6370_ADC_UNIT_VSYS 5000 /* uV */ -#define MT6370_ADC_UNIT_VBAT 5000 /* uV */ -#define MT6370_ADC_UNIT_TS_BAT 25 /* 0.01% */ -#define MT6370_ADC_UNIT_IBUS 50000 /* uA */ -#define MT6370_ADC_UNIT_IBAT 50000 /* uA */ -#define MT6370_ADC_UNIT_CHG_VDDP 5000 /* uV */ -#define MT6370_ADC_UNIT_TEMP_JC 2 /* degree */ - -#define MT6370_ADC_OFFSET_VBUS_DIV5 0 /* mV */ -#define MT6370_ADC_OFFSET_VBUS_DIV2 0 /* mV */ -#define MT6370_ADC_OFFSET_VSYS 0 /* mV */ -#define MT6370_ADC_OFFSET_VBAT 0 /* mV */ -#define MT6370_ADC_OFFSET_TS_BAT 0 /* % */ -#define MT6370_ADC_OFFSET_IBUS 0 /* mA */ -#define MT6370_ADC_OFFSET_IBAT 0 /* mA */ -#define MT6370_ADC_OFFSET_CHG_VDDP 0 /* mV */ -#define MT6370_ADC_OFFSET_TEMP_JC (-40) /* degree */ +#define MT6370_ADC_UNIT_VBUS_DIV5 25000 /* uV */ +#define MT6370_ADC_UNIT_VBUS_DIV2 10000 /* uV */ +#define MT6370_ADC_UNIT_VSYS 5000 /* uV */ +#define MT6370_ADC_UNIT_VBAT 5000 /* uV */ +#define MT6370_ADC_UNIT_TS_BAT 25 /* 0.01% */ +#define MT6370_ADC_UNIT_IBUS 50000 /* uA */ +#define MT6370_ADC_UNIT_IBAT 50000 /* uA */ +#define MT6370_ADC_UNIT_CHG_VDDP 5000 /* uV */ +#define MT6370_ADC_UNIT_TEMP_JC 2 /* degree */ + +#define MT6370_ADC_OFFSET_VBUS_DIV5 0 /* mV */ +#define MT6370_ADC_OFFSET_VBUS_DIV2 0 /* mV */ +#define MT6370_ADC_OFFSET_VSYS 0 /* mV */ +#define MT6370_ADC_OFFSET_VBAT 0 /* mV */ +#define MT6370_ADC_OFFSET_TS_BAT 0 /* % */ +#define MT6370_ADC_OFFSET_IBUS 0 /* mA */ +#define MT6370_ADC_OFFSET_IBAT 0 /* mA */ +#define MT6370_ADC_OFFSET_CHG_VDDP 0 /* mV */ +#define MT6370_ADC_OFFSET_TEMP_JC (-40) /* degree */ /* ========== Variant-specific configuration ============ */ #if defined(CONFIG_CHARGER_RT9466) - #define RT946X_CHARGER_NAME "rt9466" - #define RT946X_VENDOR_ID 0x80 - #define RT946X_ADDR_FLAGS 0x53 +#define RT946X_CHARGER_NAME "rt9466" +#define RT946X_VENDOR_ID 0x80 +#define RT946X_ADDR_FLAGS 0x53 #elif defined(CONFIG_CHARGER_RT9467) - #define RT946X_CHARGER_NAME "rt9467" - #define RT946X_VENDOR_ID 0x90 - #define RT946X_ADDR_FLAGS 0x5B +#define RT946X_CHARGER_NAME "rt9467" +#define RT946X_VENDOR_ID 0x90 +#define RT946X_ADDR_FLAGS 0x5B #elif defined(CONFIG_CHARGER_MT6370) - #define RT946X_CHARGER_NAME "mt6370" - #define RT946X_VENDOR_ID 0xE0 - #define RT946X_ADDR_FLAGS 0x34 +#define RT946X_CHARGER_NAME "mt6370" +#define RT946X_VENDOR_ID 0xE0 +#define RT946X_ADDR_FLAGS 0x34 #else - #error "No suitable charger option defined" +#error "No suitable charger option defined" #endif /* RT946x specific interface functions */ -- cgit v1.2.1 From 4303c950e5e029eca3800cf5ea612a9a118eea35 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:08 -0600 Subject: board/taniks/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8baed98822f5a7ceee89fb51aa203705e362342f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729027 Reviewed-by: Jeremy Bettis --- board/taniks/pwm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/board/taniks/pwm.c b/board/taniks/pwm.c index 7e834385bf..468a83788b 100644 --- a/board/taniks/pwm.c +++ b/board/taniks/pwm.c @@ -11,10 +11,8 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From 61227431e170c7f7fc8ced4ed2f100f0f3553283 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:28 -0600 Subject: board/voema/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9ef6498089abba4c60f196034feb019f7765284f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729059 Reviewed-by: Jeremy Bettis --- board/voema/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/voema/led.c b/board/voema/led.c index 25e71c262d..817fb80b3e 100644 --- a/board/voema/led.c +++ b/board/voema/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 1a667cc33eaa02fecefff7696966c7940717f377 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:34 -0600 Subject: board/beetley/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I797411dd4ccaec6c5c398dc9a1ef7004fdf48ef3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728031 Reviewed-by: Jeremy Bettis --- board/beetley/led.c | 58 ++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/board/beetley/led.c b/board/beetley/led.c index bf64b33dcf..e29b61c514 100644 --- a/board/beetley/led.c +++ b/board/beetley/led.c @@ -11,42 +11,46 @@ #include "gpio.h" #include "pwm.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From 5d70535a848a521d38b2cd542842bcf0b0e57a8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:04 -0600 Subject: include/config_std_internal_flash.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a914e002349c64dee288b7f14e0e93f30043daf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730233 Reviewed-by: Jeremy Bettis --- include/config_std_internal_flash.h | 42 +++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h index d272f5136c..f2d0156d35 100644 --- a/include/config_std_internal_flash.h +++ b/include/config_std_internal_flash.h @@ -37,42 +37,38 @@ * This is NOT a globally defined config, and is only used in this file * for convenience. */ -#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_SHAREDLIB_SIZE) / 2) +#define _IMAGE_SIZE ((CONFIG_FLASH_SIZE_BYTES - CONFIG_SHAREDLIB_SIZE) / 2) /* * The EC uses the one bank of flash to emulate a SPI-like write protect * register with persistent state. */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) /* * By default, there is no shared objects library. However, if configured, the * shared objects library will be placed after the RO image. */ -#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + \ - _IMAGE_SIZE) -#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + \ - _IMAGE_SIZE) -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_MEM_OFF (CONFIG_RO_MEM_OFF + _IMAGE_SIZE) +#define CONFIG_SHAREDLIB_STORAGE_OFF (CONFIG_RO_STORAGE_OFF + _IMAGE_SIZE) +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + \ - CONFIG_SHAREDLIB_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _IMAGE_SIZE +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_MEM_OFF (CONFIG_SHAREDLIB_MEM_OFF + CONFIG_SHAREDLIB_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE _IMAGE_SIZE -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */ -- cgit v1.2.1 From 2b001917e22a896f7174c9da4775f502a2506496 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:19 -0600 Subject: board/palkia/keyboard_customization.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf9bc7798a43f814e5ab73c258e3ff164546a142 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728808 Reviewed-by: Jeremy Bettis --- board/palkia/keyboard_customization.c | 88 ++++++++++++++++------------------- 1 file changed, 40 insertions(+), 48 deletions(-) diff --git a/board/palkia/keyboard_customization.c b/board/palkia/keyboard_customization.c index b39bf09f08..7cd37070be 100644 --- a/board/palkia/keyboard_customization.c +++ b/board/palkia/keyboard_customization.c @@ -12,22 +12,22 @@ #include "keyboard_raw.h" static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c}, - {0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000}, - {0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076}, - {0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b}, - {0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b}, - {0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b}, - {0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042}, - {0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000}, - {0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, - {0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c}, - {0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023}, - {0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, + { 0x0021, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x0015, 0x0000, 0x0014, 0x000d, 0x000e, 0x0016, 0x0000, 0x001c }, + { 0xe011, 0x0011, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x0000, 0x0029, 0x0024, 0x000c, 0xe01f, 0x0026, 0x0004, 0x0000 }, + { 0x0022, 0x001a, 0x0006, 0x0005, 0x001b, 0x001e, 0x001d, 0x0076 }, + { 0x002a, 0x0032, 0x0034, 0x002c, 0x002e, 0x0025, 0x002d, 0x002b }, + { 0x003a, 0x0031, 0x0033, 0x0035, 0x0036, 0x003d, 0x003c, 0x003b }, + { 0x0049, 0xe072, 0x005d, 0x0044, 0x0009, 0x0046, 0x0000, 0x004b }, + { 0x0059, 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x0041, 0x0000, 0x0083, 0x000b, 0x0003, 0x003e, 0x0043, 0x0042 }, + { 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0xe06b, 0x0000 }, + { 0xe014, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, + { 0x004a, 0xe075, 0x004e, 0x0000, 0x0045, 0x004d, 0x0054, 0x004c }, + { 0x0052, 0x005a, 0x0000, 0x0000, 0x0055, 0x0066, 0x005b, 0x0023 }, + { 0x0000, 0x000a, 0xe074, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, }; uint16_t get_scancode_set2(uint8_t row, uint8_t col) @@ -64,38 +64,30 @@ void board_keyboard_drive_col(int col) #ifdef CONFIG_KEYBOARD_DEBUG static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', - '1', KLLI_UNKNO, 'a'}, - {KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, - KLLI_SEARC, '3', KLLI_F3, KLLI_UNKNO}, - {'x', 'z', KLLI_F2, KLLI_F1, - 's', '2', 'w', KLLI_ESC}, - {'v', 'b', 'g', 't', - '5', '4', 'r', 'f'}, - {'m', 'n', 'h', 'y', - '6', '7', 'u', 'j'}, - {'.', KLLI_DOWN, '\\', 'o', - KLLI_F10, '9', KLLI_UNKNO, 'l'}, - {KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {',', KLLI_UNKNO, KLLI_F7, KLLI_F6, - KLLI_F5, '8', 'i', 'k'}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, - KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT, KLLI_UNKNO}, - {KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'/', KLLI_UP, '-', KLLI_UNKNO, - '0', 'p', '[', ';'}, - {'\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, - '=', KLLI_B_SPC, ']', 'd'}, - {KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + { 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' }, + { KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3, + KLLI_UNKNO }, + { 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC }, + { 'v', 'b', 'g', 't', '5', '4', 'r', 'f' }, + { 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' }, + { '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' }, + { KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO, + KLLI_LEFT, KLLI_UNKNO }, + { KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' }, + { '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' }, + { KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, }; char get_keycap_label(uint8_t row, uint8_t col) -- cgit v1.2.1 From 96b65e39f76eff95cb0a3b7d585c258871f8a177 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:51 -0600 Subject: board/mithrax/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2ec61c1814e8aab099daa2168e1d44e7db8eff2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728687 Reviewed-by: Jeremy Bettis --- board/mithrax/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/mithrax/usbc_config.h b/board/mithrax/usbc_config.h index aaf1d02b10..d8ff043afd 100644 --- a/board/mithrax/usbc_config.h +++ b/board/mithrax/usbc_config.h @@ -8,15 +8,11 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #define CONFIG_USB_MUX_RUNTIME_CONFIG -enum usbc_port { - USBC_PORT_C2 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C2 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); void db_update_usb4_config_from_config(void); -- cgit v1.2.1 From 161e390bac59f065fa0481a99cec22ad64f87a92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:03 -0600 Subject: chip/stm32/usart-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc2c655411a776be4fa7799dbfdc1377204a4f79 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729540 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32f0.c | 51 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/chip/stm32/usart-stm32f0.c b/chip/stm32/usart-stm32f0.c index 740d3929bc..ca618608ee 100644 --- a/chip/stm32/usart-stm32f0.c +++ b/chip/stm32/usart-stm32f0.c @@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -54,8 +54,7 @@ static void usart_variant_disable(struct usart_config const *config) * Only disable the shared interrupt for USART3/4 if both USARTs are * now disabled. */ - if ((index == 0) || - (index == 1) || + if ((index == 0) || (index == 1) || (index == 2 && configs[3] == NULL) || (index == 3 && configs[2] == NULL)) task_disable_irq(config->hw->irq); @@ -64,18 +63,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -98,12 +97,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -116,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -134,23 +133,23 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3_4, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3_4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; #endif #if defined(CONFIG_STREAM_USART4) struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART3_4, + .index = 3, + .base = STM32_USART4_BASE, + .irq = STM32_IRQ_USART3_4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART4, + .ops = &usart_variant_hw_ops, }; #endif -- cgit v1.2.1 From 6b9d281735eea5db6b376438d489539e26ab37db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:18 -0600 Subject: driver/temp_sensor/g78x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3145fe4eb05e0870aaf6579a76027b870687a304 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730105 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/g78x.h | 192 +++++++++++++++++++++++----------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/driver/temp_sensor/g78x.h b/driver/temp_sensor/g78x.h index fdd987fcbd..f80da3b708 100644 --- a/driver/temp_sensor/g78x.h +++ b/driver/temp_sensor/g78x.h @@ -12,118 +12,118 @@ #error Cannot support both G781 and G782 together! #endif -#define G78X_I2C_ADDR_FLAGS 0x4C +#define G78X_I2C_ADDR_FLAGS 0x4C -#define G78X_IDX_INTERNAL 0 -#define G78X_IDX_EXTERNAL1 1 -#define G78X_IDX_EXTERNAL2 2 +#define G78X_IDX_INTERNAL 0 +#define G78X_IDX_EXTERNAL1 1 +#define G78X_IDX_EXTERNAL2 2 #if defined(CONFIG_TEMP_SENSOR_G781) /* G781 register */ -#define G78X_TEMP_LOCAL 0x00 -#define G78X_TEMP_REMOTE1 0x01 -#define G78X_STATUS 0x02 -#define G78X_CONFIGURATION_R 0x03 -#define G78X_CONVERSION_RATE_R 0x04 -#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x05 -#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x06 -#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x07 -#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x08 -#define G78X_CONFIGURATION_W 0x09 -#define G78X_CONVERSION_RATE_W 0x0a -#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x0b -#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x0c -#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x0d -#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x0e -#define G78X_ONESHOT 0x0f -#define G78X_REMOTE1_TEMP_EXTENDED 0x10 -#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x11 -#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x12 -#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x13 -#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x14 -#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x19 -#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20 -#define G78X_THERM_HYSTERESIS 0x21 -#define G78X_ALERT_FAULT_QUEUE_CODE 0x22 -#define G78X_MANUFACTURER_ID 0xFE -#define G78X_DEVICE_ID 0xFF +#define G78X_TEMP_LOCAL 0x00 +#define G78X_TEMP_REMOTE1 0x01 +#define G78X_STATUS 0x02 +#define G78X_CONFIGURATION_R 0x03 +#define G78X_CONVERSION_RATE_R 0x04 +#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x05 +#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x06 +#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x07 +#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x08 +#define G78X_CONFIGURATION_W 0x09 +#define G78X_CONVERSION_RATE_W 0x0a +#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x0b +#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x0c +#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x0d +#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x0e +#define G78X_ONESHOT 0x0f +#define G78X_REMOTE1_TEMP_EXTENDED 0x10 +#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x11 +#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x12 +#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x13 +#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x14 +#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x19 +#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20 +#define G78X_THERM_HYSTERESIS 0x21 +#define G78X_ALERT_FAULT_QUEUE_CODE 0x22 +#define G78X_MANUFACTURER_ID 0xFE +#define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_STANDBY BIT(6) -#define G78X_CONFIGURATION_ALERT_MASK BIT(7) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1) -#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4) -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) -#define G78X_STATUS_BUSY BIT(7) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(0) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(1) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(2) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(4) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define G78X_STATUS_BUSY BIT(7) #elif defined(CONFIG_TEMP_SENSOR_G782) /* G782 register */ -#define G78X_TEMP_LOCAL 0x00 -#define G78X_TEMP_REMOTE1 0x01 -#define G78X_TEMP_REMOTE2 0x02 -#define G78X_STATUS 0x03 -#define G78X_CONFIGURATION_R 0x04 -#define G78X_CONFIGURATION_W 0x04 -#define G78X_CONVERSION_RATE_R 0x05 -#define G78X_CONVERSION_RATE_W 0x05 -#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x06 -#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x06 -#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x07 -#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x07 -#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x08 -#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x08 -#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x09 -#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x09 -#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R 0x0a -#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W 0x0a -#define G78X_REMOTE2_TEMP_LOW_LIMIT_R 0x0b -#define G78X_REMOTE2_TEMP_LOW_LIMIT_W 0x0b -#define G78X_ONESHOT 0x0c -#define G78X_REMOTE1_TEMP_EXTENDED 0x0d -#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x0e -#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x0f -#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x10 -#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x11 -#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x12 -#define G78X_REMOTE2_TEMP_EXTENDED 0x13 -#define G78X_REMOTE2_TEMP_OFFSET_HIGH 0x14 -#define G78X_REMOTE2_TEMP_OFFSET_EXTD 0x15 -#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD 0x16 -#define G78X_REMOTE2_T_LOW_LIMIT_EXTD 0x17 -#define G78X_REMOTE2_TEMP_THERM_LIMIT 0x18 -#define G78X_STATUS1 0x19 -#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20 -#define G78X_THERM_HYSTERESIS 0x21 -#define G78X_ALERT_FAULT_QUEUE_CODE 0x22 -#define G78X_MANUFACTURER_ID 0xFE -#define G78X_DEVICE_ID 0xFF +#define G78X_TEMP_LOCAL 0x00 +#define G78X_TEMP_REMOTE1 0x01 +#define G78X_TEMP_REMOTE2 0x02 +#define G78X_STATUS 0x03 +#define G78X_CONFIGURATION_R 0x04 +#define G78X_CONFIGURATION_W 0x04 +#define G78X_CONVERSION_RATE_R 0x05 +#define G78X_CONVERSION_RATE_W 0x05 +#define G78X_LOCAL_TEMP_HIGH_LIMIT_R 0x06 +#define G78X_LOCAL_TEMP_HIGH_LIMIT_W 0x06 +#define G78X_LOCAL_TEMP_LOW_LIMIT_R 0x07 +#define G78X_LOCAL_TEMP_LOW_LIMIT_W 0x07 +#define G78X_REMOTE1_TEMP_HIGH_LIMIT_R 0x08 +#define G78X_REMOTE1_TEMP_HIGH_LIMIT_W 0x08 +#define G78X_REMOTE1_TEMP_LOW_LIMIT_R 0x09 +#define G78X_REMOTE1_TEMP_LOW_LIMIT_W 0x09 +#define G78X_REMOTE2_TEMP_HIGH_LIMIT_R 0x0a +#define G78X_REMOTE2_TEMP_HIGH_LIMIT_W 0x0a +#define G78X_REMOTE2_TEMP_LOW_LIMIT_R 0x0b +#define G78X_REMOTE2_TEMP_LOW_LIMIT_W 0x0b +#define G78X_ONESHOT 0x0c +#define G78X_REMOTE1_TEMP_EXTENDED 0x0d +#define G78X_REMOTE1_TEMP_OFFSET_HIGH 0x0e +#define G78X_REMOTE1_TEMP_OFFSET_EXTD 0x0f +#define G78X_REMOTE1_T_HIGH_LIMIT_EXTD 0x10 +#define G78X_REMOTE1_T_LOW_LIMIT_EXTD 0x11 +#define G78X_REMOTE1_TEMP_THERM_LIMIT 0x12 +#define G78X_REMOTE2_TEMP_EXTENDED 0x13 +#define G78X_REMOTE2_TEMP_OFFSET_HIGH 0x14 +#define G78X_REMOTE2_TEMP_OFFSET_EXTD 0x15 +#define G78X_REMOTE2_T_HIGH_LIMIT_EXTD 0x16 +#define G78X_REMOTE2_T_LOW_LIMIT_EXTD 0x17 +#define G78X_REMOTE2_TEMP_THERM_LIMIT 0x18 +#define G78X_STATUS1 0x19 +#define G78X_LOCAL_TEMP_THERM_LIMIT 0x20 +#define G78X_THERM_HYSTERESIS 0x21 +#define G78X_ALERT_FAULT_QUEUE_CODE 0x22 +#define G78X_MANUFACTURER_ID 0xFE +#define G78X_DEVICE_ID 0xFF /* Config register bits */ -#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5) -#define G78X_CONFIGURATION_STANDBY BIT(6) -#define G78X_CONFIGURATION_ALERT_MASK BIT(7) +#define G78X_CONFIGURATION_REMOTE2_DIS BIT(5) +#define G78X_CONFIGURATION_STANDBY BIT(6) +#define G78X_CONFIGURATION_ALERT_MASK BIT(7) /* Status register bits */ -#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0) -#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1) -#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2) -#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3) -#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4) -#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5) -#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6) -#define G78X_STATUS_BUSY BIT(7) +#define G78X_STATUS_LOCAL_TEMP_LOW_ALARM BIT(0) +#define G78X_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(1) +#define G78X_STATUS_LOCAL_TEMP_THERM_ALARM BIT(2) +#define G78X_STATUS_REMOTE2_TEMP_THERM_ALARM BIT(3) +#define G78X_STATUS_REMOTE1_TEMP_THERM_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_FAULT BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_FAULT BIT(6) +#define G78X_STATUS_BUSY BIT(7) /* Status1 register bits */ -#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4) -#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5) -#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6) -#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7) +#define G78X_STATUS_REMOTE2_TEMP_LOW_ALARM BIT(4) +#define G78X_STATUS_REMOTE2_TEMP_HIGH_ALARM BIT(5) +#define G78X_STATUS_REMOTE1_TEMP_LOW_ALARM BIT(6) +#define G78X_STATUS_REMOTE1_TEMP_HIGH_ALARM BIT(7) #endif /** @@ -137,4 +137,4 @@ */ int g78x_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_G78X_H */ +#endif /* __CROS_EC_G78X_H */ -- cgit v1.2.1 From 054076505f1adcac064900cb4ab3250469ec484e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:43 -0600 Subject: zephyr/include/emul/emul_smart_battery.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0cc3f1c7d5ce5f6c8407229eee2673be1b1d172c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730722 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/emul_smart_battery.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/include/emul/emul_smart_battery.h b/zephyr/include/emul/emul_smart_battery.h index 034cb6915b..f5eab1524d 100644 --- a/zephyr/include/emul/emul_smart_battery.h +++ b/zephyr/include/emul/emul_smart_battery.h @@ -38,11 +38,11 @@ */ /* Value used to indicate that no command is selected */ -#define SBAT_EMUL_NO_CMD -1 +#define SBAT_EMUL_NO_CMD -1 /* Maximum size of data that can be returned in SMBus block transaction */ -#define MAX_BLOCK_SIZE 32 +#define MAX_BLOCK_SIZE 32 /* Maximum length of command to send is maximum size of data + len byte + PEC */ -#define MSG_BUF_LEN (MAX_BLOCK_SIZE + 2) +#define MSG_BUF_LEN (MAX_BLOCK_SIZE + 2) /** @brief Emulated smart battery properties */ struct sbat_emul_bat_data { -- cgit v1.2.1 From 9f56f18d68f7da8bb1c12463d4ba9ceaa81c8ae4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:46 -0600 Subject: include/battery_fuel_gauge.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I203f39133d491931c46ded19cf94398a4187661a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730210 Reviewed-by: Jeremy Bettis --- include/battery_fuel_gauge.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/battery_fuel_gauge.h b/include/battery_fuel_gauge.h index 7589a68190..ed3d2d70b4 100644 --- a/include/battery_fuel_gauge.h +++ b/include/battery_fuel_gauge.h @@ -67,7 +67,6 @@ struct board_batt_params { extern const struct board_batt_params board_battery_info[]; extern const enum battery_type DEFAULT_BATTERY_TYPE; - #ifdef CONFIG_BATTERY_MEASURE_IMBALANCE /** * Report the absolute difference between the highest and lowest cell voltage in -- cgit v1.2.1 From cf50057bf9b96b069d885d259fcff2473ac71908 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:42 -0600 Subject: driver/ppc/nx20p348x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I179e7b2fc3a8d49793a9b3c667681d2c1c81fd96 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730048 Reviewed-by: Jeremy Bettis --- driver/ppc/nx20p348x.h | 116 ++++++++++++++++++++++++------------------------- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index 001a43f489..ebda50da39 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -28,63 +28,63 @@ #define NX20P348X_SAFE_RESET_VBUS_MV 5000 /* NX20P348x register addresses */ -#define NX20P348X_DEVICE_ID_REG 0x00 -#define NX20P348X_DEVICE_STATUS_REG 0x01 -#define NX20P348X_SWITCH_CONTROL_REG 0x02 -#define NX20P348X_SWITCH_STATUS_REG 0x03 -#define NX20P348X_INTERRUPT1_REG 0x04 -#define NX20P348X_INTERRUPT2_REG 0x05 -#define NX20P348X_INTERRUPT1_MASK_REG 0x06 -#define NX20P348X_INTERRUPT2_MASK_REG 0x07 -#define NX20P348X_OVLO_THRESHOLD_REG 0x08 -#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG 0x09 -#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG 0x0A -#define NX20P348X_DEVICE_CONTROL_REG 0x0B +#define NX20P348X_DEVICE_ID_REG 0x00 +#define NX20P348X_DEVICE_STATUS_REG 0x01 +#define NX20P348X_SWITCH_CONTROL_REG 0x02 +#define NX20P348X_SWITCH_STATUS_REG 0x03 +#define NX20P348X_INTERRUPT1_REG 0x04 +#define NX20P348X_INTERRUPT2_REG 0x05 +#define NX20P348X_INTERRUPT1_MASK_REG 0x06 +#define NX20P348X_INTERRUPT2_MASK_REG 0x07 +#define NX20P348X_OVLO_THRESHOLD_REG 0x08 +#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG 0x09 +#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG 0x0A +#define NX20P348X_DEVICE_CONTROL_REG 0x0B /* Device Control Register (0x0B) */ -#define NX20P3483_CTRL_FRS_AT BIT(3) -#define NX20P348X_CTRL_DB_EXIT BIT(2) -#define NX20P348X_CTRL_VBUSDIS_EN BIT(1) -#define NX20P348X_CTRL_LDO_SD BIT(0) +#define NX20P3483_CTRL_FRS_AT BIT(3) +#define NX20P348X_CTRL_DB_EXIT BIT(2) +#define NX20P348X_CTRL_VBUSDIS_EN BIT(1) +#define NX20P348X_CTRL_LDO_SD BIT(0) /* Device Status Modes (0x01) */ -#define NX20P3481_DEVICE_MODE_MASK 0x3 -#define NX20P3483_DEVICE_MODE_MASK 0x7 -#define NX20P348X_MODE_DEAD_BATTERY 0 +#define NX20P3481_DEVICE_MODE_MASK 0x3 +#define NX20P3483_DEVICE_MODE_MASK 0x7 +#define NX20P348X_MODE_DEAD_BATTERY 0 /* After dead battery, mode values are different between 3481 and 3483 */ -#define NX20P3481_MODE_NORMAL 1 -#define NX20P3481_MODE_FRS 2 -#define NX20P3481_MODE_STANDBY 3 +#define NX20P3481_MODE_NORMAL 1 +#define NX20P3481_MODE_FRS 2 +#define NX20P3481_MODE_STANDBY 3 -#define NX20P3483_MODE_HV_SNK 1 -#define NX20P3483_MODE_5V_SRC 2 -#define NX20P3483_MODE_HV_SRC 3 -#define NX20P3483_MODE_STANDBY 4 +#define NX20P3483_MODE_HV_SNK 1 +#define NX20P3483_MODE_5V_SRC 2 +#define NX20P3483_MODE_HV_SRC 3 +#define NX20P3483_MODE_STANDBY 4 /* Switch Control Register (0x02) */ -#define NX20P3481_SWITCH_CONTROL_5VSRC BIT(2) -#define NX20P3481_SWITCH_CONTROL_HVSRC BIT(1) -#define NX20P3481_SWITCH_CONTROL_HVSNK BIT(0) +#define NX20P3481_SWITCH_CONTROL_5VSRC BIT(2) +#define NX20P3481_SWITCH_CONTROL_HVSRC BIT(1) +#define NX20P3481_SWITCH_CONTROL_HVSNK BIT(0) /* Switch Status Register (0x03) */ -#define NX20P348X_SWITCH_STATUS_5VSRC BIT(2) -#define NX20P348X_SWITCH_STATUS_HVSRC BIT(1) -#define NX20P348X_SWITCH_STATUS_HVSNK BIT(0) +#define NX20P348X_SWITCH_STATUS_5VSRC BIT(2) +#define NX20P348X_SWITCH_STATUS_HVSRC BIT(1) +#define NX20P348X_SWITCH_STATUS_HVSNK BIT(0) #define NX20P348X_SWITCH_STATUS_DEBOUNCE_MSEC 25 -#define NX20P348X_SWITCH_STATUS_MASK 0x7 +#define NX20P348X_SWITCH_STATUS_MASK 0x7 /* Internal 5V VBUS Switch Current Limit Settings (min) */ #define NX20P348X_ILIM_MASK 0xF -#define NX20P348X_ILIM_0_400 0 -#define NX20P348X_ILIM_0_600 1 -#define NX20P348X_ILIM_0_800 2 -#define NX20P348X_ILIM_1_000 3 -#define NX20P348X_ILIM_1_200 4 -#define NX20P348X_ILIM_1_400 5 -#define NX20P348X_ILIM_1_600 6 -#define NX20P348X_ILIM_1_800 7 -#define NX20P348X_ILIM_2_000 8 -#define NX20P348X_ILIM_2_200 9 +#define NX20P348X_ILIM_0_400 0 +#define NX20P348X_ILIM_0_600 1 +#define NX20P348X_ILIM_0_800 2 +#define NX20P348X_ILIM_1_000 3 +#define NX20P348X_ILIM_1_200 4 +#define NX20P348X_ILIM_1_400 5 +#define NX20P348X_ILIM_1_600 6 +#define NX20P348X_ILIM_1_800 7 +#define NX20P348X_ILIM_2_000 8 +#define NX20P348X_ILIM_2_200 9 #define NX20P348X_ILIM_2_400 10 #define NX20P348X_ILIM_2_600 11 #define NX20P348X_ILIM_2_800 12 @@ -103,23 +103,23 @@ #define NX20P348X_OVLO_23_0 6 /* Interrupt 1 Register Bits (0x04) */ -#define NX20P348X_INT1_DBEXIT_ERR BIT(7) -#define NX20P3481_INT1_FRS_DET BIT(6) -#define NX20P348X_INT1_OV_5VSRC BIT(4) -#define NX20P348X_INT1_RCP_5VSRC BIT(3) -#define NX20P348X_INT1_SC_5VSRC BIT(2) -#define NX20P348X_INT1_OC_5VSRC BIT(1) -#define NX20P348X_INT1_OTP BIT(0) +#define NX20P348X_INT1_DBEXIT_ERR BIT(7) +#define NX20P3481_INT1_FRS_DET BIT(6) +#define NX20P348X_INT1_OV_5VSRC BIT(4) +#define NX20P348X_INT1_RCP_5VSRC BIT(3) +#define NX20P348X_INT1_SC_5VSRC BIT(2) +#define NX20P348X_INT1_OC_5VSRC BIT(1) +#define NX20P348X_INT1_OTP BIT(0) /* Interrupt 2 Register Bits (0x05) */ -#define NX20P348X_INT2_EN_ERR BIT(7) -#define NX20P348X_INT2_RCP_HVSNK BIT(6) -#define NX20P348X_INT2_SC_HVSNK BIT(5) -#define NX20P348X_INT2_OV_HVSNK BIT(4) -#define NX20P348X_INT2_RCP_HVSRC BIT(3) -#define NX20P348X_INT2_SC_HVSRC BIT(2) -#define NX20P348X_INT2_OC_HVSRC BIT(1) -#define NX20P348X_INT2_OV_HVSRC BIT(0) +#define NX20P348X_INT2_EN_ERR BIT(7) +#define NX20P348X_INT2_RCP_HVSNK BIT(6) +#define NX20P348X_INT2_SC_HVSNK BIT(5) +#define NX20P348X_INT2_OV_HVSNK BIT(4) +#define NX20P348X_INT2_RCP_HVSRC BIT(3) +#define NX20P348X_INT2_SC_HVSRC BIT(2) +#define NX20P348X_INT2_OC_HVSRC BIT(1) +#define NX20P348X_INT2_OV_HVSRC BIT(0) struct ppc_drv; extern const struct ppc_drv nx20p348x_drv; -- cgit v1.2.1 From 40976cc038d0ef83bc8029420349ae8b7503517b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:47 -0600 Subject: board/nucleo-dartmonkey/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia52547326e8546310b18b0a583338487210ba185 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728774 Reviewed-by: Jeremy Bettis --- board/nucleo-dartmonkey/board.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/board/nucleo-dartmonkey/board.h b/board/nucleo-dartmonkey/board.h index 9e220db7dc..4b17ba253b 100644 --- a/board/nucleo-dartmonkey/board.h +++ b/board/nucleo-dartmonkey/board.h @@ -33,27 +33,27 @@ /* SPI configuration for the fingerprint sensor */ #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */ +#define CONFIG_SPI_FP_PORT 2 /* SPI4: third master config */ #define CONFIG_FINGERPRINT_MCU #ifdef SECTION_IS_RW - /* Select fingerprint sensor */ -# define CONFIG_FP_SENSOR_FPC1145 -# define CONFIG_CMD_FPSENSOR_DEBUG - /* Special memory regions to store large arrays */ -# define FP_FRAME_SECTION __SECTION(ahb4) -# define FP_TEMPLATE_SECTION __SECTION(ahb) - /* - * Use the malloc code only in the RW section (for the private library), - * we cannot enable it in RO since it is not compatible with the RW - * verification (shared_mem_init done too late). - */ -# define CONFIG_MALLOC +/* Select fingerprint sensor */ +#define CONFIG_FP_SENSOR_FPC1145 +#define CONFIG_CMD_FPSENSOR_DEBUG +/* Special memory regions to store large arrays */ +#define FP_FRAME_SECTION __SECTION(ahb4) +#define FP_TEMPLATE_SECTION __SECTION(ahb) +/* + * Use the malloc code only in the RW section (for the private library), + * we cannot enable it in RO since it is not compatible with the RW + * verification (shared_mem_init done too late). + */ +#define CONFIG_MALLOC #endif /* SECTION_IS_RW */ #ifndef __ASSEMBLER__ - void fps_event(enum gpio_signal signal); +void fps_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ #endif /* __BOARD_H */ -- cgit v1.2.1 From 7cd2bb7fa465d57e1998bb8ce34d9e5a29c02df5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:15 -0600 Subject: board/moli/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68f5bdb5d64fd0ad5076aa65375d75c31d74fdc8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728695 Reviewed-by: Jeremy Bettis --- board/moli/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/moli/usbc_config.h b/board/moli/usbc_config.h index 002f4803b7..db4249dcf5 100644 --- a/board/moli/usbc_config.h +++ b/board/moli/usbc_config.h @@ -8,12 +8,8 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; #endif /* __CROS_EC_USBC_CONFIG_H */ -- cgit v1.2.1 From 3750e2793051596b4187ed06c87ad6cc778da1bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:35 -0600 Subject: board/banshee/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibbeb30006a23f424f83980c138b488c9c48c2d11 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728019 Reviewed-by: Jeremy Bettis --- board/banshee/board.h | 129 +++++++++++++++++++++++--------------------------- 1 file changed, 58 insertions(+), 71 deletions(-) diff --git a/board/banshee/board.h b/board/banshee/board.h index e412fcc7d2..e90e1f84f0 100644 --- a/board/banshee/board.h +++ b/board/banshee/board.h @@ -58,13 +58,12 @@ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS) - /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 4 +#define CONFIG_IO_EXPANDER_PORT_COUNT 4 #define CONFIG_USB_PD_FRS_PPC @@ -79,17 +78,17 @@ #define CONFIG_USBC_PPC_SYV682X #define CONFIG_USB_PD_PPC -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -97,61 +96,61 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL +#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_PPC_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_PPC_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 -#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -175,13 +174,13 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* * Older boards have a different ADC assignment. @@ -191,7 +190,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -209,10 +208,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - CLEAR_ALS = 0, - SENSOR_COUNT -}; +enum sensor_id { CLEAR_ALS = 0, SENSOR_COUNT }; enum ioex_port { IOEX_C0_NCT38XX = 0, @@ -222,30 +218,21 @@ enum ioex_port { IOEX_PORT_COUNT }; -enum battery_type { - BATTERY_NVT, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_NVT, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_SIDE_LED_R = 0, /* PWM0 (Red charger) */ - PWM_CH_SIDE_LED_G, /* PWM1 (Green charger) */ - PWM_CH_SIDE_LED_B, /* PWM2 (Blue charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_POWER_LED_W, /* PWM7 (white LED) */ + PWM_CH_SIDE_LED_R = 0, /* PWM0 (Red charger) */ + PWM_CH_SIDE_LED_G, /* PWM1 (Green charger) */ + PWM_CH_SIDE_LED_B, /* PWM2 (Blue charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_POWER_LED_W, /* PWM7 (white LED) */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void battery_present_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From c5f53c7137078c7514d6c6c6680f7454f461d0f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:34 -0600 Subject: common/memory_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I88beb735a470e01ed19e91e0daf9aff7f1fd9c07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729671 Reviewed-by: Jeremy Bettis --- common/memory_commands.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/common/memory_commands.c b/common/memory_commands.c index 98c64d918b..4a4812b696 100644 --- a/common/memory_commands.c +++ b/common/memory_commands.c @@ -10,7 +10,6 @@ #include "util.h" #include "watchdog.h" - enum format { FMT_WORD, FMT_HALF, @@ -106,11 +105,10 @@ static int command_mem_dump(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND_FLAGS - (md, command_mem_dump, - "[.b|.h|.s] addr [count]", - "dump memory values, optionally specifying the format", - CMD_FLAG_RESTRICTED); +DECLARE_CONSOLE_COMMAND_FLAGS( + md, command_mem_dump, "[.b|.h|.s] addr [count]", + "dump memory values, optionally specifying the format", + CMD_FLAG_RESTRICTED); #endif /* CONFIG_CMD_MD */ #ifdef CONFIG_CMD_RW @@ -149,16 +147,16 @@ static int command_read_word(int argc, char **argv) if ((argc - argc_offs) < 3) { switch (access_size) { case 1: - ccprintf("read 0x%pP = 0x%02x\n", - address, *((uint8_t *)address)); + ccprintf("read 0x%pP = 0x%02x\n", address, + *((uint8_t *)address)); break; case 2: - ccprintf("read 0x%pP = 0x%04x\n", - address, *((uint16_t *)address)); + ccprintf("read 0x%pP = 0x%04x\n", address, + *((uint16_t *)address)); break; default: - ccprintf("read 0x%pP = 0x%08x\n", address, *address); + ccprintf("read 0x%pP = 0x%08x\n", address, *address); break; } return EC_SUCCESS; @@ -172,7 +170,7 @@ static int command_read_word(int argc, char **argv) switch (access_size) { case 1: ccprintf("write 0x%pP = 0x%02x\n", address, (uint8_t)value); - cflush(); /* Flush before writing in case this crashes */ + cflush(); /* Flush before writing in case this crashes */ *((uint8_t *)address) = (uint8_t)value; break; case 2: @@ -190,9 +188,8 @@ static int command_read_word(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND_FLAGS - (rw, command_read_word, - "[.b|.h] addr [value]", - "Read or write a word in memory optionally specifying the size", - CMD_FLAG_RESTRICTED); -#endif /* CONFIG_CMD_RW */ +DECLARE_CONSOLE_COMMAND_FLAGS( + rw, command_read_word, "[.b|.h] addr [value]", + "Read or write a word in memory optionally specifying the size", + CMD_FLAG_RESTRICTED); +#endif /* CONFIG_CMD_RW */ -- cgit v1.2.1 From 153d6251a5f313ac246b8ca7c9bb244efbd92db8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:24 -0600 Subject: board/genesis/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0feb01da4c718adb9949eb3db631bb06b2fc146 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728397 Reviewed-by: Jeremy Bettis --- board/genesis/board.c | 141 ++++++++++++++++++++++---------------------------- 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/board/genesis/board.c b/board/genesis/board.c index 5305c8d630..c34f86bd0a 100644 --- a/board/genesis/board.c +++ b/board/genesis/board.c @@ -36,8 +36,8 @@ #include "usb_common.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -49,14 +49,14 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1500) -#define PWR_FRONT_LOW (5*900) -#define PWR_REAR (5*1500) -#define PWR_HDMI (5*562) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1500) +#define PWR_FRONT_LOW (5 * 900) +#define PWR_REAR (5 * 1500) +#define PWR_HDMI (5 * 562) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -112,69 +112,56 @@ static void port_ocp_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_WHITE] = { .channel = 2, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_WHITE] = { .channel = 2, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "pse", - .port = I2C_PORT_PSE, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "pse", + .port = I2C_PORT_PSE, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -230,15 +217,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -257,7 +243,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -266,8 +252,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ @@ -420,23 +406,23 @@ void board_enable_s0_rails(int enable) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -449,8 +435,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ -- cgit v1.2.1 From 80549d670f032d6cd981315f8fddd080a0abe1f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:48 -0600 Subject: chip/stm32/flash-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17baab6ed7dd29ab9066d344978d9c30df492c3e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729496 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32f0.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index f790a657c8..b0b2595e58 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -65,8 +65,7 @@ uint32_t crec_flash_physical_get_protect_flags(void) /* Default: RW. */ int region = FLASH_REGION_RW; - if (i >= WP_BANK_OFFSET && - i < WP_BANK_OFFSET + WP_BANK_COUNT) + if (i >= WP_BANK_OFFSET && i < WP_BANK_OFFSET + WP_BANK_COUNT) region = FLASH_REGION_RO; #ifdef CONFIG_ROLLBACK if (i >= ROLLBACK_BANK_OFFSET && @@ -95,11 +94,11 @@ uint32_t crec_flash_physical_get_protect_flags(void) for (i = 0; i < FLASH_REGION_COUNT; i++) { if (!(wrp01 & wrp_mask[i][0]) && - (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) + (wrp01 & wrp_mask[i][0] << 8) == (wrp_mask[i][0] << 8)) #if CONFIG_FLASH_SIZE_BYTES > 64 * 1024 if (!(wrp23 & wrp_mask[i][1]) && - (wrp23 & wrp_mask[i][1] << 8) == - (wrp_mask[i][1] << 8)) + (wrp23 & wrp_mask[i][1] << 8) == + (wrp_mask[i][1] << 8)) #endif flags |= mask_flags[i]; } @@ -127,18 +126,15 @@ int crec_flash_physical_restore_state(void) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | #ifdef CONFIG_FLASH_PROTECT_RW - EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_RW_NOW | + EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_RW_NOW | #endif #ifdef CONFIG_ROLLBACK EC_FLASH_PROTECT_ROLLBACK_AT_BOOT | EC_FLASH_PROTECT_ROLLBACK_NOW | #endif - EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_ALL_NOW; + EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_ALL_NOW; } uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) @@ -153,13 +149,13 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) * ALL/RW at-boot state can be set if WP GPIO is asserted and can always * be cleared. */ - if (cur_flags & (EC_FLASH_PROTECT_ALL_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_ALL_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_ALL_AT_BOOT; #ifdef CONFIG_FLASH_PROTECT_RW - if (cur_flags & (EC_FLASH_PROTECT_RW_AT_BOOT | - EC_FLASH_PROTECT_GPIO_ASSERTED)) + if (cur_flags & + (EC_FLASH_PROTECT_RW_AT_BOOT | EC_FLASH_PROTECT_GPIO_ASSERTED)) ret |= EC_FLASH_PROTECT_RW_AT_BOOT; #endif -- cgit v1.2.1 From 759c83ec24dfd5900e3f985bda80efebf9097957 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:50 -0600 Subject: include/hotword_dsp_api.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc3c998aeaa98cc14dceda627d0a74edb4cd81b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730281 Reviewed-by: Jeremy Bettis --- include/hotword_dsp_api.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hotword_dsp_api.h b/include/hotword_dsp_api.h index 369af00ede..f7a21f5020 100644 --- a/include/hotword_dsp_api.h +++ b/include/hotword_dsp_api.h @@ -44,4 +44,4 @@ int GoogleHotwordDspGetMaximumAudioPreambleMs(void); /* Returns an internal version number that this library was built at. */ extern int GoogleHotwordVersion(void); -#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */ +#endif /* SPEECH_MICRO_API_HOTWORD_DSP_API_H_ */ -- cgit v1.2.1 From 5e3586240b1ed29966ce07528f6e2400124c11e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:43 -0600 Subject: board/ghost/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2bc8c895a1a4f69d0f7273e44c150b1dd0ea8509 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728404 Reviewed-by: Jeremy Bettis --- board/ghost/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ghost/fw_config.c b/board/ghost/fw_config.c index 4a968caccd..40bb066b3e 100644 --- a/board/ghost/fw_config.c +++ b/board/ghost/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union ghost_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From bf7b858103ca476704462d351054678278111d3a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:11 -0600 Subject: test/usb_pe_drp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I99b08f8e6012af6feedefd5f92ceb1e07049e3a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730542 Reviewed-by: Jeremy Bettis --- test/usb_pe_drp.c | 117 ++++++++++++++++++++++++++---------------------------- 1 file changed, 57 insertions(+), 60 deletions(-) diff --git a/test/usb_pe_drp.c b/test/usb_pe_drp.c index 5130c4a4a9..894d825b87 100644 --- a/test/usb_pe_drp.c +++ b/test/usb_pe_drp.c @@ -28,11 +28,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .driver = &mock_usb_mux_driver, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .driver = &mock_usb_mux_driver, +} }; void before_test(void) { @@ -57,8 +55,7 @@ void before_test(void) test_static void rx_message(enum tcpci_msg_type sop, enum pd_ctrl_msg_type ctrl_msg, enum pd_data_msg_type data_msg, - enum pd_power_role prole, - enum pd_data_role drole, + enum pd_power_role prole, enum pd_data_role drole, uint32_t data) { int type, cnt; @@ -70,8 +67,9 @@ test_static void rx_message(enum tcpci_msg_type sop, type = data_msg; cnt = 1; } - rx_emsg[PORT0].header = (PD_HEADER_SOP(sop) - | PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0)); + rx_emsg[PORT0].header = + (PD_HEADER_SOP(sop) | + PD_HEADER(type, prole, drole, 0, cnt, PD_REV30, 0)); rx_emsg[PORT0].len = cnt * 4; *(uint32_t *)rx_emsg[PORT0].buf = data; mock_prl_message_received(PORT0); @@ -94,8 +92,8 @@ test_static int finish_src_discovery(int startup_cable_probes) EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); - rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); + rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK, + PD_ROLE_UFP, 0); /* Expect GET_REVISION, reply NOT_SUPPORTED. */ TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, @@ -103,29 +101,28 @@ test_static int finish_src_discovery(int startup_cable_probes) EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); - rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); + rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK, + PD_ROLE_UFP, 0); /* * Cable identity discovery is attempted 6 times total. 1 was done * above, so expect 5 more now. */ for (i = startup_cable_probes; i < 6; i++) { - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, - 0, PD_DATA_VENDOR_DEF, - 60 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0, + PD_DATA_VENDOR_DEF, 60 * MSEC), EC_SUCCESS, "%d"); mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME); } /* Expect VENDOR_DEF for partner identity, reply NOT_SUPPORTED. */ - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_VENDOR_DEF, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_VENDOR_DEF, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); - rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); + rx_message(TCPCI_MSG_SOP, PD_CTRL_NOT_SUPPORTED, 0, PD_ROLE_SINK, + PD_ROLE_UFP, 0); return EC_SUCCESS; } @@ -140,8 +137,8 @@ test_static int test_send_caps_error_before_connected(void) mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE; mock_tc_port[PORT0].pd_enable = 1; mock_tc_port[PORT0].vconn_src = true; - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_SOURCE_CAP, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_SOURCE_CAP, 10 * MSEC), EC_SUCCESS, "%d"); /* @@ -155,8 +152,8 @@ test_static int test_send_caps_error_before_connected(void) * We should have gone to PE_SRC_Discovery on above error, so expect * VENDOR_DEF for cable identity, simulate no cable. */ - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, - 0, PD_DATA_VENDOR_DEF, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP_PRIME, 0, + PD_DATA_VENDOR_DEF, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_report_error(PORT0, ERR_TCH_XMIT, TCPCI_MSG_SOP_PRIME); @@ -164,8 +161,8 @@ test_static int test_send_caps_error_before_connected(void) * Expect SOURCE_CAP again. This is a retry since the first one above * got ERR_TCH_XMIT. Now simulate success (ie GoodCRC). */ - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_SOURCE_CAP, 110 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_SOURCE_CAP, 110 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); @@ -179,14 +176,14 @@ test_static int test_send_caps_error_before_connected(void) */ /* REQUEST 5V, expect ACCEPT, PS_RDY. */ - rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, - PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0)); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_ACCEPT, 0, 10 * MSEC), + rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + RDO_FIXED(1, 500, 500, 0)); + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT, + 0, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_PS_RDY, 0, 35 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY, + 0, 35 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); @@ -207,21 +204,21 @@ test_static int test_send_caps_error_when_connected(void) mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE; mock_tc_port[PORT0].pd_enable = 1; mock_tc_port[PORT0].vconn_src = true; - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_SOURCE_CAP, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_SOURCE_CAP, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); /* REQUEST 5V, expect ACCEPT, PS_RDY. */ - rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, - PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0)); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_ACCEPT, 0, 10 * MSEC), + rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + RDO_FIXED(1, 500, 500, 0)); + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT, + 0, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_PS_RDY, 0, 35 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY, + 0, 35 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); @@ -233,10 +230,10 @@ test_static int test_send_caps_error_when_connected(void) * Now connected. Send GET_SOURCE_CAP, to check how error sending * SOURCE_CAP is handled. */ - rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_SOURCE_CAP, 10 * MSEC), + rx_message(TCPCI_MSG_SOP, PD_CTRL_GET_SOURCE_CAP, 0, PD_ROLE_SINK, + PD_ROLE_UFP, 0); + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_SOURCE_CAP, 10 * MSEC), EC_SUCCESS, "%d"); /* Simulate error sending SOURCE_CAP. */ @@ -269,21 +266,21 @@ test_static int test_interrupting_pr_swap(void) mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE; mock_tc_port[PORT0].pd_enable = 1; mock_tc_port[PORT0].vconn_src = true; - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - 0, PD_DATA_SOURCE_CAP, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, 0, + PD_DATA_SOURCE_CAP, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(10 * MSEC); /* REQUEST 5V, expect ACCEPT, PS_RDY. */ - rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, - PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0)); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_ACCEPT, 0, 10 * MSEC), + rx_message(TCPCI_MSG_SOP, 0, PD_DATA_REQUEST, PD_ROLE_SINK, PD_ROLE_UFP, + RDO_FIXED(1, 500, 500, 0)); + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT, + 0, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_PS_RDY, 0, 35 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_PS_RDY, + 0, 35 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); @@ -295,26 +292,26 @@ test_static int test_interrupting_pr_swap(void) * Now connected. Initiate a PR swap and then interrupt it after the * Accept, when power is transitioning to off. */ - rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); + rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP, + 0); - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, - PD_CTRL_ACCEPT, 0, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_SOP, PD_CTRL_ACCEPT, + 0, 10 * MSEC), EC_SUCCESS, "%d"); mock_prl_message_sent(PORT0); task_wait_event(5 * SECOND); /* Interrupt the non-interruptible AMS */ - rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, - PD_ROLE_SINK, PD_ROLE_UFP, 0); + rx_message(TCPCI_MSG_SOP, PD_CTRL_PR_SWAP, 0, PD_ROLE_SINK, PD_ROLE_UFP, + 0); /* * Expect a hard reset since power was transitioning during this * interruption */ - TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET, - 0, 0, 10 * MSEC), + TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPCI_MSG_TX_HARD_RESET, 0, 0, + 10 * MSEC), EC_SUCCESS, "%d"); return EC_SUCCESS; -- cgit v1.2.1 From c2c4ebc4b495679d218073136fa304453dbaae15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:31 -0600 Subject: zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic376a20daae54775269618b80c4f2875c11ca463 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730949 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h index 229bfb7e60..fbe5201323 100644 --- a/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h +++ b/zephyr/subsys/ap_pwrseq/include/ap_power_override_functions.h @@ -75,7 +75,7 @@ bool board_ap_power_check_power_rails_enabled(void); /** * @brief macro to access configuration properties from DTS */ -#define AP_PWRSEQ_DT_VALUE(p) \ - DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p) \ +#define AP_PWRSEQ_DT_VALUE(p) \ + DT_PROP(DT_COMPAT_GET_ANY_STATUS_OKAY(intel_ap_pwrseq), p) #endif /* __AP_PWRSEQ_AP_POWER_BOARD_FUNCTIONS_H__ */ -- cgit v1.2.1 From 67201cc1b3ee014174b9a78a268a7cfdc625db22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:42 -0600 Subject: chip/max32660/tmr_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38b0f6f2478233b2dcc2ef9f3d889157d3bdd56b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729236 Reviewed-by: Jeremy Bettis --- chip/max32660/tmr_regs.h | 296 +++++++++++++++++++++++++---------------------- 1 file changed, 158 insertions(+), 138 deletions(-) diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h index 946cacbc50..8292d1f9e7 100644 --- a/chip/max32660/tmr_regs.h +++ b/chip/max32660/tmr_regs.h @@ -42,11 +42,11 @@ extern "C" { * Structure type to access the TMR Registers. */ typedef struct { - __IO uint32_t cnt; /**< \b 0x00:<\tt> TMR CNT Register */ - __IO uint32_t cmp; /**< \b 0x04:<\tt> TMR CMP Register */ - __IO uint32_t pwm; /**< \b 0x08:<\tt> TMR PWM Register */ - __IO uint32_t intr; /**< \b 0x0C:<\tt> TMR INTR Register */ - __IO uint32_t cn; /**< \b 0x10:<\tt> TMR CN Register */ + __IO uint32_t cnt; /**< \b 0x00:<\tt> TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04:<\tt> TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08:<\tt> TMR PWM Register */ + __IO uint32_t intr; /**< \b 0x0C:<\tt> TMR INTR Register */ + __IO uint32_t cn; /**< \b 0x10:<\tt> TMR CN Register */ __IO uint32_t nolcmp; /**< \b 0x14:<\tt> TMR NOLCMP Register */ } mxc_tmr_regs_t; @@ -54,23 +54,23 @@ typedef struct { * TMR Peripheral Register Offsets from the TMR Base Peripheral * Address. */ -#define MXC_R_TMR_CNT \ - ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_CNT \ + ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: \ 0x0x000 */ -#define MXC_R_TMR_CMP \ - ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_CMP \ + ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: \ 0x0x004 */ -#define MXC_R_TMR_PWM \ - ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_PWM \ + ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: \ 0x0x008 */ -#define MXC_R_TMR_INTR \ - ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_INTR \ + ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: \ 0x0x00C */ -#define MXC_R_TMR_CN \ - ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_CN \ + ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: \ 0x0x010 */ -#define MXC_R_TMR_NOLCMP \ - ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: \ +#define MXC_R_TMR_NOLCMP \ + ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: \ 0x0x014 */ /** @@ -78,199 +78,219 @@ typedef struct { * clears the associated interrupt. */ #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */ -#define MXC_F_TMR_INTR_IRQ_CLR \ - ((uint32_t)(0x1UL \ - << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */ +#define MXC_F_TMR_INTR_IRQ_CLR \ + ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR \ + Mask */ /** * Timer Control Register. */ #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ -#define MXC_F_TMR_CN_TMODE \ +#define MXC_F_TMR_CN_TMODE \ ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ -#define MXC_V_TMR_CN_TMODE_ONESHOT \ +#define MXC_V_TMR_CN_TMODE_ONESHOT \ ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ -#define MXC_S_TMR_CN_TMODE_ONESHOT \ - (MXC_V_TMR_CN_TMODE_ONESHOT \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ -#define MXC_V_TMR_CN_TMODE_CONTINUOUS \ +#define MXC_S_TMR_CN_TMODE_ONESHOT \ + (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_ONESHOT \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CONTINUOUS \ ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ -#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ - (MXC_V_TMR_CN_TMODE_CONTINUOUS \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ -#define MXC_V_TMR_CN_TMODE_COUNTER \ +#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ + (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CONTINUOUS \ + Setting \ + */ +#define MXC_V_TMR_CN_TMODE_COUNTER \ ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ -#define MXC_S_TMR_CN_TMODE_COUNTER \ - (MXC_V_TMR_CN_TMODE_COUNTER \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ +#define MXC_S_TMR_CN_TMODE_COUNTER \ + (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COUNTER \ + Setting */ #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ -#define MXC_S_TMR_CN_TMODE_PWM \ - (MXC_V_TMR_CN_TMODE_PWM \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURE \ +#define MXC_S_TMR_CN_TMODE_PWM \ + (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CAPTURE \ ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURE \ - (MXC_V_TMR_CN_TMODE_CAPTURE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ -#define MXC_V_TMR_CN_TMODE_COMPARE \ +#define MXC_S_TMR_CN_TMODE_CAPTURE \ + (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURE \ + Setting */ +#define MXC_V_TMR_CN_TMODE_COMPARE \ ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ -#define MXC_S_TMR_CN_TMODE_COMPARE \ - (MXC_V_TMR_CN_TMODE_COMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ -#define MXC_V_TMR_CN_TMODE_GATED \ - ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ +#define MXC_S_TMR_CN_TMODE_COMPARE \ + (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COMPARE \ + Setting */ +#define MXC_V_TMR_CN_TMODE_GATED \ + ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ */ #define MXC_S_TMR_CN_TMODE_GATED \ - (MXC_V_TMR_CN_TMODE_GATED \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ -#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ + (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_GATED \ + Setting */ +#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ - (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ - << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ +#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ + (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURECOMPARE \ + Setting \ + */ #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ -#define MXC_F_TMR_CN_PRES \ +#define MXC_F_TMR_CN_PRES \ ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ -#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ -#define MXC_S_TMR_CN_PRES_DIV1 \ - (MXC_V_TMR_CN_PRES_DIV1 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ +#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ +#define MXC_S_TMR_CN_PRES_DIV1 \ + (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ -#define MXC_S_TMR_CN_PRES_DIV2 \ - (MXC_V_TMR_CN_PRES_DIV2 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ +#define MXC_S_TMR_CN_PRES_DIV2 \ + (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ -#define MXC_S_TMR_CN_PRES_DIV4 \ - (MXC_V_TMR_CN_PRES_DIV4 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ +#define MXC_S_TMR_CN_PRES_DIV4 \ + (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ -#define MXC_S_TMR_CN_PRES_DIV8 \ - (MXC_V_TMR_CN_PRES_DIV8 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ +#define MXC_S_TMR_CN_PRES_DIV8 \ + (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ -#define MXC_S_TMR_CN_PRES_DIV16 \ - (MXC_V_TMR_CN_PRES_DIV16 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ +#define MXC_S_TMR_CN_PRES_DIV16 \ + (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ -#define MXC_S_TMR_CN_PRES_DIV32 \ - (MXC_V_TMR_CN_PRES_DIV32 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ +#define MXC_S_TMR_CN_PRES_DIV32 \ + (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 \ + Setting */ #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ -#define MXC_S_TMR_CN_PRES_DIV64 \ - (MXC_V_TMR_CN_PRES_DIV64 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ -#define MXC_V_TMR_CN_PRES_DIV128 \ - ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \ +#define MXC_S_TMR_CN_PRES_DIV64 \ + (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 \ + Setting */ +#define MXC_V_TMR_CN_PRES_DIV128 \ + ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value \ */ -#define MXC_S_TMR_CN_PRES_DIV128 \ - (MXC_V_TMR_CN_PRES_DIV128 \ - << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ +#define MXC_S_TMR_CN_PRES_DIV128 \ + (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< \ + CN_PRES_DIV128 \ + Setting */ #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ -#define MXC_F_TMR_CN_TPOL \ +#define MXC_F_TMR_CN_TPOL \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ -#define MXC_V_TMR_CN_TPOL_ACTIVEHI \ +#define MXC_V_TMR_CN_TPOL_ACTIVEHI \ ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ - (MXC_V_TMR_CN_TPOL_ACTIVEHI \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ -#define MXC_V_TMR_CN_TPOL_ACTIVELO \ +#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ + (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVEHI \ + Setting */ +#define MXC_V_TMR_CN_TPOL_ACTIVELO \ ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVELO \ - (MXC_V_TMR_CN_TPOL_ACTIVELO \ - << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ +#define MXC_S_TMR_CN_TPOL_ACTIVELO \ + (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVELO \ + Setting */ #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ -#define MXC_F_TMR_CN_TEN \ +#define MXC_F_TMR_CN_TEN \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ -#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ +#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ #define MXC_S_TMR_CN_TEN_DIS \ - (MXC_V_TMR_CN_TEN_DIS \ - << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ + (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting \ + */ #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ -#define MXC_S_TMR_CN_TEN_EN \ - (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \ +#define MXC_S_TMR_CN_TEN_EN \ + (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting \ */ #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ -#define MXC_F_TMR_CN_PRES3 \ +#define MXC_F_TMR_CN_PRES3 \ ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ -#define MXC_F_TMR_CN_PWMSYNC \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \ +#define MXC_F_TMR_CN_PWMSYNC \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask \ */ -#define MXC_V_TMR_CN_PWMSYNC_DIS \ - ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ +#define MXC_V_TMR_CN_PWMSYNC_DIS \ + ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ */ -#define MXC_S_TMR_CN_PWMSYNC_DIS \ - (MXC_V_TMR_CN_PWMSYNC_DIS \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ +#define MXC_S_TMR_CN_PWMSYNC_DIS \ + (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ + CN_PWMSYNC_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ #define MXC_S_TMR_CN_PWMSYNC_EN \ - (MXC_V_TMR_CN_PWMSYNC_EN \ - << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ + (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ + CN_PWMSYNC_EN \ + Setting */ #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ -#define MXC_F_TMR_CN_NOLHPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \ +#define MXC_F_TMR_CN_NOLHPOL \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask \ */ -#define MXC_V_TMR_CN_NOLHPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ +#define MXC_V_TMR_CN_NOLHPOL_DIS \ + ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLHPOL_DIS \ - (MXC_V_TMR_CN_NOLHPOL_DIS \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */ +#define MXC_S_TMR_CN_NOLHPOL_DIS \ + (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ + CN_NOLHPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ #define MXC_S_TMR_CN_NOLHPOL_EN \ - (MXC_V_TMR_CN_NOLHPOL_EN \ - << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */ + (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ + CN_NOLHPOL_EN \ + Setting */ #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ -#define MXC_F_TMR_CN_NOLLPOL \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \ +#define MXC_F_TMR_CN_NOLLPOL \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask \ */ -#define MXC_V_TMR_CN_NOLLPOL_DIS \ - ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ +#define MXC_V_TMR_CN_NOLLPOL_DIS \ + ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLLPOL_DIS \ - (MXC_V_TMR_CN_NOLLPOL_DIS \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */ +#define MXC_S_TMR_CN_NOLLPOL_DIS \ + (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ + CN_NOLLPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ #define MXC_S_TMR_CN_NOLLPOL_EN \ - (MXC_V_TMR_CN_NOLLPOL_EN \ - << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */ + (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ + CN_NOLLPOL_EN \ + Setting */ #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ -#define MXC_F_TMR_CN_PWMCKBD \ - ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \ +#define MXC_F_TMR_CN_PWMCKBD \ + ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask \ */ -#define MXC_V_TMR_CN_PWMCKBD_DIS \ - ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ +#define MXC_V_TMR_CN_PWMCKBD_DIS \ + ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ */ -#define MXC_S_TMR_CN_PWMCKBD_DIS \ - (MXC_V_TMR_CN_PWMCKBD_DIS \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ +#define MXC_S_TMR_CN_PWMCKBD_DIS \ + (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ + CN_PWMCKBD_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ #define MXC_S_TMR_CN_PWMCKBD_EN \ - (MXC_V_TMR_CN_PWMCKBD_EN \ - << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ + (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ + CN_PWMCKBD_EN \ + Setting */ /** * Timer Non-Overlapping Compare Register. */ #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ #define MXC_F_TMR_NOLCMP_NOLLCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ + ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< \ + NOLCMP_NOLLCMP \ + Mask */ #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ #define MXC_F_TMR_NOLCMP_NOLHCMP \ - ((uint32_t)( \ - 0xFFUL \ - << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ + ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< \ + NOLCMP_NOLHCMP \ + Mask */ #ifdef __cplusplus } -- cgit v1.2.1 From 0540f0c975edd4fa0a210b5287d62255836f3b62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:46 -0600 Subject: include/driver/accel_lis2dw12_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic39738e28e9ee2de329c325ec5e1cd9f6ad7a271 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730246 Reviewed-by: Jeremy Bettis --- include/driver/accel_lis2dw12_public.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/driver/accel_lis2dw12_public.h b/include/driver/accel_lis2dw12_public.h index 751df15f86..5f705590b4 100644 --- a/include/driver/accel_lis2dw12_public.h +++ b/include/driver/accel_lis2dw12_public.h @@ -17,18 +17,18 @@ extern const struct accelgyro_drv lis2dw12_drv; * 7-bit address is 011000Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define LIS2DW12_ADDR0 0x18 -#define LIS2DW12_ADDR1 0x19 +#define LIS2DW12_ADDR0 0x18 +#define LIS2DW12_ADDR1 0x19 -#define LIS2DWL_ADDR0_FLAGS 0x18 -#define LIS2DWL_ADDR1_FLAGS 0x19 +#define LIS2DWL_ADDR0_FLAGS 0x18 +#define LIS2DWL_ADDR1_FLAGS 0x19 -#define LIS2DW12_EN_BIT 0x01 -#define LIS2DW12_DIS_BIT 0x00 +#define LIS2DW12_EN_BIT 0x01 +#define LIS2DW12_DIS_BIT 0x00 /* Absolute Acc rate. */ -#define LIS2DW12_ODR_MIN_VAL 12500 -#define LIS2DW12_ODR_MAX_VAL \ +#define LIS2DW12_ODR_MIN_VAL 12500 +#define LIS2DW12_ODR_MAX_VAL \ MOTION_MAX_SENSOR_FREQUENCY(1600000, LIS2DW12_ODR_MIN_VAL) void lis2dw12_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 8ebfd86cb667187151aeb83be6bd0fedf8522f74 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:57 -0600 Subject: power/mt817x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7482769e700776433d906d6a5cc9c3dde10402ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730465 Reviewed-by: Jeremy Bettis --- power/mt817x.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/power/mt817x.c b/power/mt817x.c index 30d3ffed1e..abaab82358 100644 --- a/power/mt817x.c +++ b/power/mt817x.c @@ -40,38 +40,38 @@ #include "test_util.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) -#define INT_BOTH_PULL_UP (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH) +#define INT_BOTH_PULL_UP (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH) /* masks for power signals */ #define IN_POWER_GOOD POWER_SIGNAL_MASK(MTK_POWER_GOOD) #define IN_SUSPEND POWER_SIGNAL_MASK(MTK_SUSPEND_ASSERTED) /* Long power key press to force shutdown */ -#define DELAY_FORCE_SHUTDOWN (8000 * MSEC) /* 8 seconds */ +#define DELAY_FORCE_SHUTDOWN (8000 * MSEC) /* 8 seconds */ /* * The power signal from SoC should be kept at least 50ms. */ -#define POWER_DEBOUNCE_TIME (50 * MSEC) +#define POWER_DEBOUNCE_TIME (50 * MSEC) /* * The suspend signal from SoC should be kept at least 50ms. */ -#define SUSPEND_DEBOUNCE_TIME (50 * MSEC) +#define SUSPEND_DEBOUNCE_TIME (50 * MSEC) /* * The time to bootup the PMIC from power-off to power-on. */ -#define PMIC_PWRON_PRESS_TIME (5000 * MSEC) +#define PMIC_PWRON_PRESS_TIME (5000 * MSEC) /* * The minimum time to assert the PMIC THERM pin is 32us. However, * it needs to be extended to about 50ms to let the 5V rail * dissipate fully. */ -#define PMIC_THERM_HOLD_TIME (50 * MSEC) +#define PMIC_THERM_HOLD_TIME (50 * MSEC) /* * If the power key is pressed to turn on, then held for this long, we @@ -81,7 +81,7 @@ * into the inner loop, waiting for next event to occur (power button * press or POWER_GOOD == 0). */ -#define DELAY_SHUTDOWN_ON_POWER_HOLD (8000 * MSEC) /* 8 seconds */ +#define DELAY_SHUTDOWN_ON_POWER_HOLD (8000 * MSEC) /* 8 seconds */ /* * The hold time for pulling down the PMIC_WARM_RESET_H pin so that @@ -387,9 +387,8 @@ static void mtk_lid_event(void) /* Override the panel backlight enable signal from SoC, * force the backlight off on lid close. */ - bl_override = lid_is_open() ? - MTK_BACKLIGHT_CONTROL_BY_SOC : - MTK_BACKLIGHT_FORCE_OFF; + bl_override = lid_is_open() ? MTK_BACKLIGHT_CONTROL_BY_SOC : + MTK_BACKLIGHT_FORCE_OFF; mtk_backlight_override(bl_override); /* Power task only cares about lid-open events */ @@ -539,7 +538,8 @@ static int check_for_power_on_event(void) CPRINTS("system is on, but EC_RESET_FLAG_AP_OFF is on"); return POWER_ON_CANCEL; } else { - CPRINTS("system is on, thus clear " "auto_power_on"); + CPRINTS("system is on, thus clear " + "auto_power_on"); /* no need to arrange another power on */ auto_power_on = 0; return POWER_ON_BY_IN_POWER_GOOD; @@ -784,7 +784,7 @@ enum power_state_t { PSTATE_COUNT, }; -static const char * const state_name[] = { +static const char *const state_name[] = { "unknown", "off", "suspend", @@ -819,6 +819,4 @@ static int command_power(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(power, command_power, - "on/off", - "Turn AP power on/off"); +DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off"); -- cgit v1.2.1 From ce7daff481481406aa80b4f402a43b65384323b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:35 -0600 Subject: board/taeko/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib737fa9f280bd8cf3a5959b34e0a147d2b33d3f8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728964 Reviewed-by: Jeremy Bettis --- board/taeko/usbc_config.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/board/taeko/usbc_config.c b/board/taeko/usbc_config.c index 0a1b7ff194..02a67cc5bc 100644 --- a/board/taeko/usbc_config.c +++ b/board/taeko/usbc_config.c @@ -34,13 +34,13 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #if 0 /* Debug only! */ -#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBPD, format, ##args) #else #define CPRINTSUSB(format, args...) #define CPRINTFUSB(format, args...) @@ -169,21 +169,20 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + &val) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); else { CPRINTS("delay 10ms to make sure PS8815 is waken from idle"); msleep(10); } - - if (i2c_write8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x0f, + &val) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -209,10 +208,11 @@ static void board_init_ps8815_detection(void) CPRINTSUSB("%s", __func__); - rv = i2c_read8(I2C_PORT_USB_C1_TCPC, - PS8XXX_I2C_ADDR1_FLAGS, 0x00, &val); + rv = i2c_read8(I2C_PORT_USB_C1_TCPC, PS8XXX_I2C_ADDR1_FLAGS, 0x00, + &val); - db_usb_hw_pres = (rv == EC_SUCCESS)?DB_USB_PRESENT:DB_USB_NOT_PRESENT; + db_usb_hw_pres = (rv == EC_SUCCESS) ? DB_USB_PRESENT : + DB_USB_NOT_PRESENT; if (db_usb_hw_pres == DB_USB_NOT_PRESENT) CPRINTS("DB isn't plugged or something went wrong!"); @@ -230,7 +230,7 @@ static bool board_detect_ps8815_db(void) return true; if (ec_cfg_usb_db_type() == DB_USB3_PS8815 && - db_usb_hw_pres == DB_USB_PRESENT) + db_usb_hw_pres == DB_USB_PRESENT) return true; CPRINTSUSB("No PS8815 DB"); @@ -257,8 +257,7 @@ void board_reset_pd_mcu(void) /* * delay for power-on to reset-off and min. assertion time */ - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1); gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1); @@ -274,7 +273,7 @@ void board_reset_pd_mcu(void) */ board_init_ps8815_detection(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } static void board_tcpc_init(void) @@ -385,7 +384,7 @@ __override bool board_is_dts_port(int port) __override uint8_t board_get_usb_pd_port_count(void) { - CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current()); + CPRINTSUSB("%s is called by task_id:%d", __func__, task_get_current()); if (board_detect_ps8815_db()) return CONFIG_USB_PD_PORT_MAX_COUNT; -- cgit v1.2.1 From b43cba8f78ca6b3c4f7a2f2d82452d8b12729ca0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:32 -0600 Subject: chip/stm32/usart_rx_dma.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib419c18df1d0ac737fed91b1d65f81e4d85522ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729546 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_dma.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/usart_rx_dma.h b/chip/stm32/usart_rx_dma.h index 064ab8046c..30c5d60d30 100644 --- a/chip/stm32/usart_rx_dma.h +++ b/chip/stm32/usart_rx_dma.h @@ -44,7 +44,7 @@ * reasonable stress test the "DMA RX max_bytes" value will be a reasonable * size for the FIFO (perhaps +10% for safety). */ -#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ +#define USART_RX_DMA(CHANNEL, FIFO_SIZE) \ ((struct usart_rx_dma const) { \ .usart_rx = { \ .producer_ops = { \ @@ -88,7 +88,7 @@ struct usart_rx_dma { struct usart_rx_dma_state volatile *state; uint8_t *fifo_buffer; - size_t fifo_size; + size_t fifo_size; enum dma_channel channel; }; -- cgit v1.2.1 From b132c4723f49933cc2f9b32af34de596c03206a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:48 -0600 Subject: board/osiris/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6359b6356110812f8f5993e77a42eac62336d090 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728796 Reviewed-by: Jeremy Bettis --- board/osiris/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/osiris/charger.c b/board/osiris/charger.c index 85e0de90fe..32dd2ddddb 100644 --- a/board/osiris/charger.c +++ b/board/osiris/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From c14abdaef6eb41a140617807b9b9c6040d3236fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:27 -0600 Subject: include/atomic_t.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ec9b8d683d1db152a69db7f743fe43133e7d721 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730205 Reviewed-by: Jeremy Bettis --- include/atomic_t.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/atomic_t.h b/include/atomic_t.h index d7c1a99147..a1235c5f62 100644 --- a/include/atomic_t.h +++ b/include/atomic_t.h @@ -19,4 +19,4 @@ typedef atomic_t atomic_val_t; #include #endif -#endif /* __CROS_EC_ATOMIC_T_H */ +#endif /* __CROS_EC_ATOMIC_T_H */ -- cgit v1.2.1 From 2c87ee528d344d2bbbc3e6b2a2baf0aefd3381e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:04 -0600 Subject: include/usb_descriptor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If33ce87de88b6f14ab9c0cbdc0243c82994876f6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730432 Reviewed-by: Jeremy Bettis --- include/usb_descriptor.h | 376 +++++++++++++++++++++++------------------------ 1 file changed, 187 insertions(+), 189 deletions(-) diff --git a/include/usb_descriptor.h b/include/usb_descriptor.h index 47f6e8805e..a3e9de3c6b 100644 --- a/include/usb_descriptor.h +++ b/include/usb_descriptor.h @@ -15,17 +15,17 @@ /* USB 2.0 chapter 9 definitions */ /* Descriptor types */ -#define USB_DT_DEVICE 0x01 -#define USB_DT_CONFIGURATION 0x02 -#define USB_DT_STRING 0x03 -#define USB_DT_INTERFACE 0x04 -#define USB_DT_ENDPOINT 0x05 -#define USB_DT_DEVICE_QUALIFIER 0x06 -#define USB_DT_OTHER_SPEED_CONFIG 0x07 -#define USB_DT_INTERFACE_POWER 0x08 -#define USB_DT_DEBUG 0x0a -#define USB_DT_BOS 0x0f -#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIGURATION 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +#define USB_DT_DEBUG 0x0a +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 /* USB Device Descriptor */ struct usb_device_descriptor { @@ -44,7 +44,7 @@ struct usb_device_descriptor { uint8_t iSerialNumber; uint8_t bNumConfigurations; } __packed; -#define USB_DT_DEVICE_SIZE 18 +#define USB_DT_DEVICE_SIZE 18 /* BOS Descriptor ( USB3.1 rev1 Section 9.6.2 ) */ struct bos_context { @@ -55,133 +55,135 @@ struct bos_context { struct usb_bos_hdr_descriptor { uint8_t bLength; uint8_t bDescriptorType; /* USB_DT_BOS */ - uint16_t wTotalLength; /* Total length of of hdr + all dev caps */ - uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */ + uint16_t wTotalLength; /* Total length of of hdr + all dev caps */ + uint8_t bNumDeviceCaps; /* Container ID Descriptor + others */ } __packed; #define USB_DT_BOS_SIZE 5 /* Container ID Descriptor */ struct usb_contid_caps_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ - uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */ - uint8_t bReserved; /* SBZ */ - uint8_t ContainerID[16]; /* UUID */ + uint8_t bLength; + uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ + uint8_t bDevCapabilityType; /* USB_DC_DTYPE_xxx */ + uint8_t bReserved; /* SBZ */ + uint8_t ContainerID[16]; /* UUID */ } __packed; -#define USB_DT_CONTID_SIZE 20 +#define USB_DT_CONTID_SIZE 20 /* Device Cap Type Codes ( offset 2 of Device Capability Descriptor */ -#define USB_DC_DTYPE_WIRELESS 0x01 -#define USB_DC_DTYPE_USB20EXT 0x02 -#define USB_DC_DTYPE_USBSS 0x03 -#define USB_DC_DTYPE_CONTID 0x04 -#define USB_DC_DTYPE_PLATFORM 0x05 -#define USB_DC_DTYPE_PD 0x06 -#define USB_DC_DTYPE_BATTINFO 0x07 -#define USB_DC_DTYPE_CONSUMER 0x08 -#define USB_DC_DTYPE_PRODUCER 0x09 -#define USB_DC_DTYPE_USBSSP 0x0a -#define USB_DC_DTYPE_PCSTIME 0x0b -#define USB_DC_DTYPE_WUSBEXT 0x0c +#define USB_DC_DTYPE_WIRELESS 0x01 +#define USB_DC_DTYPE_USB20EXT 0x02 +#define USB_DC_DTYPE_USBSS 0x03 +#define USB_DC_DTYPE_CONTID 0x04 +#define USB_DC_DTYPE_PLATFORM 0x05 +#define USB_DC_DTYPE_PD 0x06 +#define USB_DC_DTYPE_BATTINFO 0x07 +#define USB_DC_DTYPE_CONSUMER 0x08 +#define USB_DC_DTYPE_PRODUCER 0x09 +#define USB_DC_DTYPE_USBSSP 0x0a +#define USB_DC_DTYPE_PCSTIME 0x0b +#define USB_DC_DTYPE_WUSBEXT 0x0c #define USB_DC_DTYPE_BILLBOARD 0x0d /* RESERVED 0x00, 0xOe - 0xff */ /* Platform descriptor */ struct usb_platform_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ - uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */ - uint8_t bReserved; /* SBZ */ - uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */ - uint16_t bcdVersion; /* 0x0100 */ - uint8_t bVendorCode; - uint8_t iLandingPage; + uint8_t bLength; + uint8_t bDescriptorType; /* USB_DT_DEVICE_CAPABILITY */ + uint8_t bDevCapabilityType; /* USB_DC_DTYPE_PLATFORM */ + uint8_t bReserved; /* SBZ */ + uint8_t PlatformCapUUID[16]; /* USB_PLAT_CAP_xxx */ + uint16_t bcdVersion; /* 0x0100 */ + uint8_t bVendorCode; + uint8_t iLandingPage; } __packed; -#define USB_DT_PLATFORM_SIZE 24 +#define USB_DT_PLATFORM_SIZE 24 /* Platform Capability UUIDs */ -#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \ - {0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, \ - 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65} +#define USB_PLAT_CAP_WEBUSB /*{3408b638-09a9-47a0-8bfd-a0768815b665}*/ \ + { \ + 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, 0x8B, 0xFD, \ + 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65 \ + } /* Qualifier Descriptor */ struct usb_qualifier_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; } __packed; -#define USB_DT_QUALIFIER_SIZE 10 +#define USB_DT_QUALIFIER_SIZE 10 /* Configuration Descriptor */ struct usb_config_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; } __packed; -#define USB_DT_CONFIG_SIZE 9 +#define USB_DT_CONFIG_SIZE 9 /* String Descriptor */ struct usb_string_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; + uint8_t bLength; + uint8_t bDescriptorType; uint16_t wData[1]; } __packed; /* Interface Descriptor */ struct usb_interface_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; } __packed; -#define USB_DT_INTERFACE_SIZE 9 +#define USB_DT_INTERFACE_SIZE 9 /* Endpoint Descriptor */ struct usb_endpoint_descriptor { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; uint16_t wMaxPacketSize; - uint8_t bInterval; + uint8_t bInterval; } __packed; -#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_SIZE 7 /* USB Class codes */ -#define USB_CLASS_PER_INTERFACE 0x00 -#define USB_CLASS_AUDIO 0x01 -#define USB_CLASS_COMM 0x02 -#define USB_CLASS_HID 0x03 -#define USB_CLASS_PHYSICAL 0x05 -#define USB_CLASS_STILL_IMAGE 0x06 -#define USB_CLASS_PRINTER 0x07 -#define USB_CLASS_MASS_STORAGE 0x08 -#define USB_CLASS_HUB 0x09 -#define USB_CLASS_CDC_DATA 0x0a -#define USB_CLASS_CSCID 0x0b -#define USB_CLASS_CONTENT_SEC 0x0d -#define USB_CLASS_VIDEO 0x0e -#define USB_CLASS_BILLBOARD 0x11 -#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 -#define USB_CLASS_MISC 0xef -#define USB_CLASS_APP_SPEC 0xfe -#define USB_CLASS_VENDOR_SPEC 0xff +#define USB_CLASS_PER_INTERFACE 0x00 +#define USB_CLASS_AUDIO 0x01 +#define USB_CLASS_COMM 0x02 +#define USB_CLASS_HID 0x03 +#define USB_CLASS_PHYSICAL 0x05 +#define USB_CLASS_STILL_IMAGE 0x06 +#define USB_CLASS_PRINTER 0x07 +#define USB_CLASS_MASS_STORAGE 0x08 +#define USB_CLASS_HUB 0x09 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b +#define USB_CLASS_CONTENT_SEC 0x0d +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_BILLBOARD 0x11 +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff /* USB Vendor ID assigned to Google Inc. */ #define USB_VID_GOOGLE 0x18d1 @@ -190,23 +192,23 @@ struct usb_endpoint_descriptor { #define USB_SUBCLASS_GOOGLE_SERIAL 0x50 #define USB_PROTOCOL_GOOGLE_SERIAL 0x01 -#define USB_SUBCLASS_GOOGLE_SPI 0x51 -#define USB_PROTOCOL_GOOGLE_SPI 0x02 +#define USB_SUBCLASS_GOOGLE_SPI 0x51 +#define USB_PROTOCOL_GOOGLE_SPI 0x02 -#define USB_SUBCLASS_GOOGLE_I2C 0x52 -#define USB_PROTOCOL_GOOGLE_I2C 0x01 +#define USB_SUBCLASS_GOOGLE_I2C 0x52 +#define USB_PROTOCOL_GOOGLE_I2C 0x01 #define USB_SUBCLASS_GOOGLE_UPDATE 0x53 #define USB_PROTOCOL_GOOGLE_UPDATE 0xff /* Double define for cr50 code freeze. * TODO(vbendeb): dedupe this. */ -#define USB_SUBCLASS_GOOGLE_CR50 0x53 +#define USB_SUBCLASS_GOOGLE_CR50 0x53 /* We can use any protocol we want */ #define USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE 0xff -#define USB_SUBCLASS_GOOGLE_POWER 0x54 -#define USB_PROTOCOL_GOOGLE_POWER 0x01 +#define USB_SUBCLASS_GOOGLE_POWER 0x54 +#define USB_PROTOCOL_GOOGLE_POWER 0x01 #define USB_SUBCLASS_GOOGLE_HEATMAP 0x55 #define USB_PROTOCOL_GOOGLE_HEATMAP 0x01 @@ -218,72 +220,71 @@ struct usb_endpoint_descriptor { /* bRequestType fields */ /* direction field */ -#define USB_DIR_OUT 0 /* from host to uC */ -#define USB_DIR_IN 0x80 /* from uC to host */ +#define USB_DIR_OUT 0 /* from host to uC */ +#define USB_DIR_IN 0x80 /* from uC to host */ /* type field */ -#define USB_TYPE_MASK (0x03 << 5) -#define USB_TYPE_STANDARD (0x00 << 5) -#define USB_TYPE_CLASS (0x01 << 5) -#define USB_TYPE_VENDOR (0x02 << 5) -#define USB_TYPE_RESERVED (0x03 << 5) +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) /* recipient field */ -#define USB_RECIP_MASK 0x1f -#define USB_RECIP_DEVICE 0x00 -#define USB_RECIP_INTERFACE 0x01 -#define USB_RECIP_ENDPOINT 0x02 -#define USB_RECIP_OTHER 0x03 +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 /* Standard requests for bRequest field in a SETUP packet. */ -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0) +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_GET_STATUS_SELF_POWERED BIT(0) #define USB_REQ_GET_STATUS_REMOTE_WAKEUP BIT(1) -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_FEATURE_ENDPOINT_HALT 0x0000 #define USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP 0x0001 -#define USB_REQ_FEATURE_TEST_MODE 0x0002 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_FEATURE_TEST_MODE 0x0002 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C /* WebUSB URL descriptors */ -#define WEBUSB_REQ_GET_URL 0x02 -#define USB_DT_WEBUSB_URL 0x03 +#define WEBUSB_REQ_GET_URL 0x02 +#define USB_DT_WEBUSB_URL 0x03 -#define USB_URL_SCHEME_HTTP 0x00 -#define USB_URL_SCHEME_HTTPS 0x01 -#define USB_URL_SCHEME_NONE 0xff +#define USB_URL_SCHEME_HTTP 0x00 +#define USB_URL_SCHEME_HTTPS 0x01 +#define USB_URL_SCHEME_NONE 0xff /* * URL descriptor helper. * (similar to string descriptor but UTF-8 instead of UTF-16) */ -#define USB_URL_DESC(scheme, str) \ - (const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - uint8_t _scheme; \ - char _data[sizeof(str)]; \ - }) { \ - /* Total size of the descriptor is : \ +#define USB_URL_DESC(scheme, str) \ + (const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + uint8_t _scheme; \ + char _data[sizeof(str)]; \ + }) \ + { \ + /* Total size of the descriptor is : \ * size of the UTF-8 text plus the len/type fields \ - * minus the string 0-termination \ - */ \ - sizeof(str) + 3 - 1, \ - USB_DT_WEBUSB_URL, \ - USB_URL_SCHEME_##scheme, \ - str \ + * minus the string 0-termination \ + */ \ + sizeof(str) + 3 - 1, USB_DT_WEBUSB_URL, \ + USB_URL_SCHEME_##scheme, str \ } /* Setup Packet */ struct usb_setup_packet { - uint8_t bmRequestType; - uint8_t bRequest; + uint8_t bmRequestType; + uint8_t bRequest; uint16_t wValue; uint16_t wIndex; uint16_t wLength; @@ -326,19 +327,18 @@ struct usb_ms_ext_compat_id_desc { #define WIDESTR(quote) WIDESTR2(quote) #define WIDESTR2(quote) L##quote -#define USB_STRING_DESC(str) \ - (const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(str)]; \ - }) { \ - /* Total size of the descriptor is : \ - * size of the UTF-16 text plus the len/type fields \ - * minus the string 0-termination \ - */ \ - sizeof(WIDESTR(str)) + 2 - 2, \ - USB_DT_STRING, \ - WIDESTR(str) \ +#define USB_STRING_DESC(str) \ + (const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(str)]; \ + }) \ + { \ + /* Total size of the descriptor is : \ + * size of the UTF-16 text plus the len/type fields \ + * minus the string 0-termination \ + */ \ + sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) \ } /* @@ -346,21 +346,21 @@ struct usb_ms_ext_compat_id_desc { * windows to request a MS Compatible ID Descriptor and then enables Windows OS * to load the correct driver for a USB-EP */ -#define USB_MS_STRING_DESC(str) \ - ((const void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(str) - 1]; \ - uint16_t _vendor; \ - }) { \ - /* Total size of the descriptor is : \ - * size of the UTF-16 text plus the len/type fields \ +#define USB_MS_STRING_DESC(str) \ + ((const void *)&(const struct { \ + uint8_t _len; \ + uint8_t _type; \ + wchar_t _data[sizeof(str) - 1]; \ + uint16_t _vendor; \ + }){ \ + /* Total size of the descriptor is : \ + * size of the UTF-16 text plus the len/type fields \ * plus 2 bytes for vendor code minus the string 0-termination \ - */ \ - sizeof(WIDESTR(str)) + 2 - 2 + 2, \ - USB_DT_STRING, \ - WIDESTR(str), \ - USB_MS_STRING_DESC_VENDOR_CODE, \ + */ \ + sizeof(WIDESTR(str)) + 2 - 2 + 2, \ + USB_DT_STRING, \ + WIDESTR(str), \ + USB_MS_STRING_DESC_VENDOR_CODE, \ }) #ifdef CONFIG_USB_SERIALNO @@ -370,22 +370,20 @@ struct usb_string_desc { uint8_t _type; wchar_t _data[CONFIG_SERIALNO_LEN]; }; -#define USB_WR_STRING_DESC(str) \ - (&(struct usb_string_desc) { \ +#define USB_WR_STRING_DESC(str) \ + (&(struct usb_string_desc){ \ /* As above, two bytes metadata, no null terminator. */ \ - sizeof(WIDESTR(str)) + 2 - 2, \ - USB_DT_STRING, \ - WIDESTR(str) \ -}) + sizeof(WIDESTR(str)) + 2 - 2, USB_DT_STRING, WIDESTR(str) }) extern struct usb_string_desc *usb_serialno_desc; #endif /* Use these macros for declaring descriptors, to order them properly */ -#define USB_CONF_DESC_VAR(name, varname) varname \ - __keep __attribute__((section(".rodata.usb_desc_" STRINGIFY(name)))) +#define USB_CONF_DESC_VAR(name, varname) \ + varname __keep \ + __attribute__((section(".rodata.usb_desc_" STRINGIFY(name)))) #define USB_CONF_DESC(name) USB_CONF_DESC_VAR(name, CONCAT2(usb_desc_, name)) #define USB_IFACE_DESC(num) USB_CONF_DESC(CONCAT3(iface, num, _0iface)) -#define USB_CUSTOM_DESC_VAR(i, name, varname) \ +#define USB_CUSTOM_DESC_VAR(i, name, varname) \ USB_CONF_DESC_VAR(CONCAT4(iface, i, _1, name), varname) #define USB_CUSTOM_DESC(i, name) USB_CONF_DESC(CONCAT4(iface, i, _1, name)) #define USB_EP_DESC(i, num) USB_CONF_DESC(CONCAT4(iface, i, _2ep, num)) @@ -396,10 +394,10 @@ extern const uint8_t __usb_desc_end[]; #define USB_DESC_SIZE (__usb_desc_end - __usb_desc) /* These descriptors defined in board code */ -extern const void * const usb_strings[]; +extern const void *const usb_strings[]; extern const uint8_t usb_string_desc[]; /* USB string descriptor with the firmware version */ -extern const void * const usb_fw_version; +extern const void *const usb_fw_version; extern const struct bos_context bos_ctx; extern const void *webusb_url; -- cgit v1.2.1 From 57d6f9cf244d7b198c817849131128a3d88c86a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:10 -0600 Subject: include/sysjump.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9073a97149d7325351cf6638b2a054ba7d00a197 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730413 Reviewed-by: Jeremy Bettis --- include/sysjump.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/sysjump.h b/include/sysjump.h index f5bf5f5a09..5e094e8ca8 100644 --- a/include/sysjump.h +++ b/include/sysjump.h @@ -16,10 +16,10 @@ * images. */ -#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */ +#define JUMP_DATA_MAGIC 0x706d754a /* "Jump" */ #define JUMP_DATA_VERSION 3 -#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */ -#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */ +#define JUMP_DATA_SIZE_V1 12 /* Size of version 1 jump data struct */ +#define JUMP_DATA_SIZE_V2 16 /* Size of version 2 jump data struct */ struct jump_data { /* @@ -29,19 +29,19 @@ struct jump_data { */ /* Fields from version 3 */ - uint8_t reserved0; /* (used in proto1 to signal recovery mode) */ - int struct_size; /* Size of struct jump_data */ + uint8_t reserved0; /* (used in proto1 to signal recovery mode) */ + int struct_size; /* Size of struct jump_data */ /* Fields from version 2 */ - int jump_tag_total; /* Total size of all jump tags */ + int jump_tag_total; /* Total size of all jump tags */ /* Fields from version 1 */ uint32_t reset_flags; /* Reset flags from the previous boot */ - int version; /* Version (JUMP_DATA_VERSION) */ - int magic; /* Magic number (JUMP_DATA_MAGIC). If this - * doesn't match at pre-init time, assume no valid - * data from the previous image. - */ + int version; /* Version (JUMP_DATA_VERSION) */ + int magic; /* Magic number (JUMP_DATA_MAGIC). If this + * doesn't match at pre-init time, assume no valid + * data from the previous image. + */ }; /** @@ -49,4 +49,4 @@ struct jump_data { */ struct jump_data *get_jump_data(void); -#endif /* __CROS_EC_SYSJUMP_IMPL_H */ +#endif /* __CROS_EC_SYSJUMP_IMPL_H */ -- cgit v1.2.1 From e190bf034471f0b865e3cbffe25aa8f2c017775d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:56 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci_partner_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c828a3704968437e55ded67fcc99c47d2ac64b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730727 Reviewed-by: Jeremy Bettis --- .../include/emul/tcpc/emul_tcpci_partner_common.h | 57 ++++++++++------------ 1 file changed, 25 insertions(+), 32 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index 9648a03e8a..f995246de6 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -31,21 +31,20 @@ */ /** Timeout for other side to respond to PD message */ -#define TCPCI_PARTNER_RESPONSE_TIMEOUT_MS 30 -#define TCPCI_PARTNER_RESPONSE_TIMEOUT \ - K_MSEC(TCPCI_PARTNER_RESPONSE_TIMEOUT_MS) +#define TCPCI_PARTNER_RESPONSE_TIMEOUT_MS 30 +#define TCPCI_PARTNER_RESPONSE_TIMEOUT K_MSEC(TCPCI_PARTNER_RESPONSE_TIMEOUT_MS) /** Timeout for source to transition to requested state after accept */ -#define TCPCI_PARTNER_TRANSITION_TIMEOUT_MS 550 -#define TCPCI_PARTNER_TRANSITION_TIMEOUT \ - K_MSEC(TCPCI_PARTNER_TRANSITION_TIMEOUT_MS) +#define TCPCI_PARTNER_TRANSITION_TIMEOUT_MS 550 +#define TCPCI_PARTNER_TRANSITION_TIMEOUT \ + K_MSEC(TCPCI_PARTNER_TRANSITION_TIMEOUT_MS) /** Timeout for source to send capability again after failure */ -#define TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS 150 -#define TCPCI_SOURCE_CAPABILITY_TIMEOUT \ - K_MSEC(TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS) +#define TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS 150 +#define TCPCI_SOURCE_CAPABILITY_TIMEOUT \ + K_MSEC(TCPCI_SOURCE_CAPABILITY_TIMEOUT_MS) /** Timeout for source to send capability message after power swap */ -#define TCPCI_SWAP_SOURCE_START_TIMEOUT_MS 20 -#define TCPCI_SWAP_SOURCE_START_TIMEOUT \ - K_MSEC(TCPCI_SWAP_SOURCE_START_TIMEOUT_MS) +#define TCPCI_SWAP_SOURCE_START_TIMEOUT_MS 20 +#define TCPCI_SWAP_SOURCE_START_TIMEOUT \ + K_MSEC(TCPCI_SWAP_SOURCE_START_TIMEOUT_MS) /** Common data for TCPCI partner device emulators */ struct tcpci_partner_data { @@ -100,7 +99,7 @@ struct tcpci_partner_data { */ bool in_soft_reset; /** Current AMS Control request being handled */ - enum pd_ctrl_msg_type cur_ams_ctrl_req; + enum pd_ctrl_msg_type cur_ams_ctrl_req; /** * If common code should send GoodCRC for each message. If false, * then one of extensions should call tcpci_emul_partner_msg_status(). @@ -265,9 +264,8 @@ struct tcpci_partner_extension_ops { * @param ext Pointer to partner extension * @param common_data Pointer to TCPCI partner emulator */ - void (*hard_reset)( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data); + void (*hard_reset)(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data); /** * @brief Function called when SoftReset message is received @@ -275,9 +273,8 @@ struct tcpci_partner_extension_ops { * @param ext Pointer to partner extension * @param common_data Pointer to TCPCI partner emulator */ - void (*soft_reset)( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data); + void (*soft_reset)(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data); /** * @brief Function called when partner emulator is disconnected from @@ -286,9 +283,8 @@ struct tcpci_partner_extension_ops { * @param ext Pointer to partner extension * @param common_data Pointer to TCPCI partner emulator */ - void (*disconnect)( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data); + void (*disconnect)(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data); /** * @brief Function called when partner emulator is connected to TCPM. @@ -300,9 +296,8 @@ struct tcpci_partner_extension_ops { * @return Negative value on error * @return 0 on success */ - int (*connect)( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data); + int (*connect)(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data); }; /** @@ -360,8 +355,7 @@ int tcpci_partner_send_msg(struct tcpci_partner_data *data, * @return negative on failure */ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, - enum pd_ctrl_msg_type type, - uint64_t delay); + enum pd_ctrl_msg_type type, uint64_t delay); /** * @brief Send data message with optional delay. Data objects are copied to @@ -380,9 +374,8 @@ int tcpci_partner_send_control_msg(struct tcpci_partner_data *data, * @return negative on failure */ int tcpci_partner_send_data_msg(struct tcpci_partner_data *data, - enum pd_data_msg_type type, - uint32_t *data_obj, int data_obj_num, - uint64_t delay); + enum pd_data_msg_type type, uint32_t *data_obj, + int data_obj_num, uint64_t delay); /** * @brief Send an extended PD message to the port partner @@ -395,8 +388,8 @@ int tcpci_partner_send_data_msg(struct tcpci_partner_data *data, * @return negative on failure, 0 on success */ int tcpci_partner_send_extended_msg(struct tcpci_partner_data *data, - enum pd_ext_msg_type type, uint64_t delay, - uint8_t *payload, size_t payload_size); + enum pd_ext_msg_type type, uint64_t delay, + uint8_t *payload, size_t payload_size); /** * @brief Remove all messages that are in delayed message queue -- cgit v1.2.1 From 5f04da6beb460a21f54e4f33b8b13dcbd3346334 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:12 -0600 Subject: include/extpower.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I196f1dea27953130f29d1176621c4fee837fb86d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730265 Reviewed-by: Jeremy Bettis --- include/extpower.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/extpower.h b/include/extpower.h index 1e9f7976e6..edc4bb105e 100644 --- a/include/extpower.h +++ b/include/extpower.h @@ -10,7 +10,7 @@ #include "common.h" -enum gpio_signal; /* from gpio_signal.h */ +enum gpio_signal; /* from gpio_signal.h */ /** * Run board specific code to update extpower status. The default @@ -37,4 +37,4 @@ void extpower_interrupt(enum gpio_signal signal); */ void extpower_handle_update(int is_present); -#endif /* __CROS_EC_EXTPOWER_H */ +#endif /* __CROS_EC_EXTPOWER_H */ -- cgit v1.2.1 From f4a82a89dcab71e72608865900a0180b031edd32 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:56 -0600 Subject: test/is_enabled_error.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0bee4ba2ffbc7ccfd685e44e218777dae108e215 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730509 Reviewed-by: Jeremy Bettis --- test/is_enabled_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/is_enabled_error.c b/test/is_enabled_error.c index 3fcd80afe0..45ab4ed6bd 100644 --- a/test/is_enabled_error.c +++ b/test/is_enabled_error.c @@ -7,7 +7,7 @@ #include "common.h" #include "test_util.h" -#define CONFIG_VALUE TEST_VALUE +#define CONFIG_VALUE TEST_VALUE static int test_invalid_value(void) { -- cgit v1.2.1 From 26581af827fd2653b8777a3175ffe26809ffbff7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:46 -0600 Subject: core/minute-ia/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I86cbf35982329f98093daee5cce401cc318a0ed2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729846 Reviewed-by: Jeremy Bettis --- core/minute-ia/atomic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/minute-ia/atomic.h b/core/minute-ia/atomic.h index dbcd04b7de..96f0e4b74e 100644 --- a/core/minute-ia/atomic.h +++ b/core/minute-ia/atomic.h @@ -13,13 +13,13 @@ #include "util.h" static inline int bool_compare_and_swap_u32(uint32_t *var, uint32_t old_value, - uint32_t new_value) + uint32_t new_value) { uint32_t _old_value = old_value; __asm__ __volatile__(ASM_LOCK_PREFIX "cmpxchgl %2, %1" - : "=a" (old_value), "+m" (*var) - : "r" (new_value), "0" (old_value) + : "=a"(old_value), "+m"(*var) + : "r"(new_value), "0"(old_value) : "memory"); return (_old_value == old_value); @@ -65,4 +65,4 @@ static inline atomic_val_t atomic_clear(atomic_t *addr) return __atomic_exchange_n(addr, 0, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 63a61dab2332678ecda6fe0f1a5f54984d7aa3fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:52 -0600 Subject: driver/battery/bq27621_g1.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf76d53dacf66ac6f9f81682bd7f5b3a4337222a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729948 Reviewed-by: Jeremy Bettis --- driver/battery/bq27621_g1.c | 259 +++++++++++++++++++++----------------------- 1 file changed, 126 insertions(+), 133 deletions(-) diff --git a/driver/battery/bq27621_g1.c b/driver/battery/bq27621_g1.c index 96b0ed6975..76a63f7247 100644 --- a/driver/battery/bq27621_g1.c +++ b/driver/battery/bq27621_g1.c @@ -13,95 +13,95 @@ #include "util.h" #include "timer.h" -#define BQ27621_ADDR_FLAGS 0x55 -#define BQ27621_TYPE_ID 0x0621 - -#define REG_CTRL 0x00 -#define REG_TEMPERATURE 0x02 -#define REG_VOLTAGE 0x04 -#define REG_FLAGS 0x06 -#define REG_NOMINAL_CAPACITY 0x08 -#define REG_FULL_AVAILABLE_CAPACITY 0x0a -#define REG_REMAINING_CAPACITY 0x0c -#define REG_FULL_CHARGE_CAPACITY 0x0e -#define REG_EFFECTIVE_CURRENT 0x10 -#define REG_AVERAGE_POWER 0x18 -#define REG_STATE_OF_CHARGE 0x1c -#define REG_INTERNAL_TEMPERATURE 0x1e -#define REG_REMAINING_CAPACITY_UNFILTERED 0x28 -#define REG_REMAINING_CAPACITY_FILTERED 0x2a +#define BQ27621_ADDR_FLAGS 0x55 +#define BQ27621_TYPE_ID 0x0621 + +#define REG_CTRL 0x00 +#define REG_TEMPERATURE 0x02 +#define REG_VOLTAGE 0x04 +#define REG_FLAGS 0x06 +#define REG_NOMINAL_CAPACITY 0x08 +#define REG_FULL_AVAILABLE_CAPACITY 0x0a +#define REG_REMAINING_CAPACITY 0x0c +#define REG_FULL_CHARGE_CAPACITY 0x0e +#define REG_EFFECTIVE_CURRENT 0x10 +#define REG_AVERAGE_POWER 0x18 +#define REG_STATE_OF_CHARGE 0x1c +#define REG_INTERNAL_TEMPERATURE 0x1e +#define REG_REMAINING_CAPACITY_UNFILTERED 0x28 +#define REG_REMAINING_CAPACITY_FILTERED 0x2a #define REG_FULL_CHARGE_CAPACITY_UNFILTERED 0x28 -#define REG_FULL_CHARGE_CAPACITY_FILTERED 0x2a -#define REG_STATE_OF_CHARGE_UNFILTERED 0x30 -#define REG_OP_CONFIG 0x3a -#define REG_DESIGN_CAPACITY 0x3c -#define REG_DATA_CLASS 0x3e -#define REG_DATA_BLOCK 0x3f -#define REG_BLOCK_DATA_CHECKSUM 0x60 -#define REG_BLOCK_DATA_CONTROL 0x61 - -#define REGISTERS_BLOCK_OFFSET 64 -#define REGISTERS_BLOCK_OP_CONFIG 0x40 -#define REGISTERS_BLOCK_OP_CONFIG_B 0x42 -#define REGISTERS_BLOCK_DF_VERSION 0x43 +#define REG_FULL_CHARGE_CAPACITY_FILTERED 0x2a +#define REG_STATE_OF_CHARGE_UNFILTERED 0x30 +#define REG_OP_CONFIG 0x3a +#define REG_DESIGN_CAPACITY 0x3c +#define REG_DATA_CLASS 0x3e +#define REG_DATA_BLOCK 0x3f +#define REG_BLOCK_DATA_CHECKSUM 0x60 +#define REG_BLOCK_DATA_CONTROL 0x61 + +#define REGISTERS_BLOCK_OFFSET 64 +#define REGISTERS_BLOCK_OP_CONFIG 0x40 +#define REGISTERS_BLOCK_OP_CONFIG_B 0x42 +#define REGISTERS_BLOCK_DF_VERSION 0x43 /* State block */ -#define STATE_BLOCK_OFFSET 82 -#define STATE_BLOCK_DESIGN_CAPACITY 0x43 -#define STATE_BLOCK_DESIGN_ENERGY 0x45 -#define STATE_BLOCK_TERMINATE_VOLTAGE 0x49 -#define STATE_BLOCK_TAPER_RATE 0x54 +#define STATE_BLOCK_OFFSET 82 +#define STATE_BLOCK_DESIGN_CAPACITY 0x43 +#define STATE_BLOCK_DESIGN_ENERGY 0x45 +#define STATE_BLOCK_TERMINATE_VOLTAGE 0x49 +#define STATE_BLOCK_TAPER_RATE 0x54 /* BQ27621 Control subcommands */ -#define CONTROL_CONTROL_STATUS 0x00 -#define CONTROL_DEVICE_TYPE 0x01 -#define CONTROL_FW_VERSION 0x02 -#define CONTROL_PREV_MACWRITE 0x07 -#define CONTROL_CHEM_ID 0x08 -#define CONTROL_BAT_INSERT 0x0C -#define CONTROL_BAT_REMOVE 0x0D -#define CONTROL_TOGGLE_POWERMIN 0x10 -#define CONTROL_SET_HIBERNATE 0x11 -#define CONTROL_CLEAR_HIBERNATE 0x12 -#define CONTROL_SET_CFGUPDATE 0x13 -#define CONTROL_SHUTDOWN_ENABLE 0x1B -#define CONTROL_SHUTDOWN 0x1C -#define CONTROL_SEALED 0x20 -#define CONTROL_TOGGLE_GPOUT 0x23 -#define CONTROL_ALT_CHEM1 0x31 -#define CONTROL_ALT_CHEM2 0x32 -#define CONTROL_RESET 0x41 -#define CONTROL_SOFT_RESET 0x42 -#define CONTROL_EXIT_CFGUPDATE 0x43 -#define CONTROL_EXIT_RESIM 0x44 -#define CONTROL_UNSEAL 0x8000 +#define CONTROL_CONTROL_STATUS 0x00 +#define CONTROL_DEVICE_TYPE 0x01 +#define CONTROL_FW_VERSION 0x02 +#define CONTROL_PREV_MACWRITE 0x07 +#define CONTROL_CHEM_ID 0x08 +#define CONTROL_BAT_INSERT 0x0C +#define CONTROL_BAT_REMOVE 0x0D +#define CONTROL_TOGGLE_POWERMIN 0x10 +#define CONTROL_SET_HIBERNATE 0x11 +#define CONTROL_CLEAR_HIBERNATE 0x12 +#define CONTROL_SET_CFGUPDATE 0x13 +#define CONTROL_SHUTDOWN_ENABLE 0x1B +#define CONTROL_SHUTDOWN 0x1C +#define CONTROL_SEALED 0x20 +#define CONTROL_TOGGLE_GPOUT 0x23 +#define CONTROL_ALT_CHEM1 0x31 +#define CONTROL_ALT_CHEM2 0x32 +#define CONTROL_RESET 0x41 +#define CONTROL_SOFT_RESET 0x42 +#define CONTROL_EXIT_CFGUPDATE 0x43 +#define CONTROL_EXIT_RESIM 0x44 +#define CONTROL_UNSEAL 0x8000 /* BQ27621 Status bits */ -#define STATUS_SHUTDOWNEN 0x8000 -#define STATUS_WDRESET 0x4000 -#define STATUS_SS 0x2000 -#define STATUS_CALMODE 0x1000 -#define STATUS_OCVCMDCOMP 0x0200 -#define STATUS_OCVFAIL 0x0100 -#define STATUS_INITCOMP 0x0080 -#define STATUS_HIBERNATE 0x0040 -#define STATUS_POWERMIN 0x0020 -#define STATUS_SLEEP 0x0010 -#define STATUS_LDMD 0x0008 -#define STATUS_CHEMCHNG 0x0001 +#define STATUS_SHUTDOWNEN 0x8000 +#define STATUS_WDRESET 0x4000 +#define STATUS_SS 0x2000 +#define STATUS_CALMODE 0x1000 +#define STATUS_OCVCMDCOMP 0x0200 +#define STATUS_OCVFAIL 0x0100 +#define STATUS_INITCOMP 0x0080 +#define STATUS_HIBERNATE 0x0040 +#define STATUS_POWERMIN 0x0020 +#define STATUS_SLEEP 0x0010 +#define STATUS_LDMD 0x0008 +#define STATUS_CHEMCHNG 0x0001 /* BQ27621 Flags bits */ -#define FLAGS_OT 0x8000 -#define FLAGS_UT 0x4000 -#define FLAGS_FC 0x0200 -#define FLAGS_CHG 0x0100 -#define FLAGS_OCVTAKEN 0x0080 -#define FLAGS_ITPOR 0x0020 -#define FLAGS_CFGUPD 0x0010 -#define FLAGS_BAT_DET 0x0008 -#define FLAGS_SOC1 0x0004 -#define FLAGS_SOCF 0x0002 -#define FLAGS_DSG 0x0001 +#define FLAGS_OT 0x8000 +#define FLAGS_UT 0x4000 +#define FLAGS_FC 0x0200 +#define FLAGS_CHG 0x0100 +#define FLAGS_OCVTAKEN 0x0080 +#define FLAGS_ITPOR 0x0020 +#define FLAGS_CFGUPD 0x0010 +#define FLAGS_BAT_DET 0x0008 +#define FLAGS_SOC1 0x0004 +#define FLAGS_SOCF 0x0002 +#define FLAGS_DSG 0x0001 /* * There are some parameters that need to be defined in the board file: @@ -119,19 +119,23 @@ * */ -#define BQ27621_SCALE_FACTOR (BQ27621_DESIGN_CAPACITY < 150 ? 10.0 : \ - (BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1)) +#define BQ27621_SCALE_FACTOR \ + (BQ27621_DESIGN_CAPACITY < 150 ? \ + 10.0 : \ + (BQ27621_DESIGN_CAPACITY > 6000 ? 0.1 : 1)) -#define BQ27621_UNSCALE(x) (BQ27621_SCALE_FACTOR == 10 ? (x) / 10 : \ - (BQ27621_SCALE_FACTOR == 0.1 ? (x) * 10 : (x))) +#define BQ27621_UNSCALE(x) \ + (BQ27621_SCALE_FACTOR == 10 ? \ + (x) / 10 : \ + (BQ27621_SCALE_FACTOR == 0.1 ? (x)*10 : (x))) -#define BQ27621_TAPER_RATE ((int)(BQ27621_DESIGN_CAPACITY/ \ - (0.1 * BQ27621_TAPER_CURRENT))) +#define BQ27621_TAPER_RATE \ + ((int)(BQ27621_DESIGN_CAPACITY / (0.1 * BQ27621_TAPER_CURRENT))) -#define BQ27621_SCALED_DESIGN_CAPACITY ((int)(BQ27621_DESIGN_CAPACITY * \ - BQ27621_SCALE_FACTOR)) -#define BQ27621_SCALED_DESIGN_ENERGY ((int)(BQ27621_DESIGN_CAPACITY * \ - BQ27621_SCALE_FACTOR)) +#define BQ27621_SCALED_DESIGN_CAPACITY \ + ((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR)) +#define BQ27621_SCALED_DESIGN_ENERGY \ + ((int)(BQ27621_DESIGN_CAPACITY * BQ27621_SCALE_FACTOR)) /* *Everything is LSB first. Parameters need to be converted. @@ -139,11 +143,11 @@ * The values from the data sheet are already LSB-first. */ -#define ENDIAN_SWAP_2B(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8)) -#define DESIGN_CAPACITY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY) -#define DESIGN_ENERGY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY) -#define TAPER_RATE ENDIAN_SWAP_2B(BQ27621_TAPER_RATE) -#define TERMINATE_VOLTAGE ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE) +#define ENDIAN_SWAP_2B(x) ((((x)&0xff) << 8) | (((x)&0xff00) >> 8)) +#define DESIGN_CAPACITY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_CAPACITY) +#define DESIGN_ENERGY ENDIAN_SWAP_2B(BQ27621_SCALED_DESIGN_ENERGY) +#define TAPER_RATE ENDIAN_SWAP_2B(BQ27621_TAPER_RATE) +#define TERMINATE_VOLTAGE ENDIAN_SWAP_2B(BQ27621_TERMINATE_VOLTAGE) struct battery_info battery_params; @@ -192,7 +196,7 @@ static int bq27621_probe(void) static inline int bq27621_unseal(void) { return bq27621_write(REG_CTRL, CONTROL_UNSEAL) | - bq27621_write(REG_CTRL, CONTROL_UNSEAL); + bq27621_write(REG_CTRL, CONTROL_UNSEAL); } static int bq27621_enter_config_update(void) @@ -200,8 +204,9 @@ static int bq27621_enter_config_update(void) int tries, flags = 0, rv = EC_SUCCESS; /* Enter Config Update Mode (Can take up to a second) */ - for (tries = 2000; tries > 0 && !(flags & FLAGS_CFGUPD) && - (rv == EC_SUCCESS); tries--) { + for (tries = 2000; + tries > 0 && !(flags & FLAGS_CFGUPD) && (rv == EC_SUCCESS); + tries--) { rv |= bq27621_write(REG_CTRL, CONTROL_SET_CFGUPDATE); rv |= bq27621_read(REG_FLAGS, &flags); } @@ -255,7 +260,7 @@ static int bq27621_seal(void) rv = bq27621_read8(REGISTERS_BLOCK_OP_CONFIG_B, ¶m); checksum -= param; /* 1B */ - param |= 1<<5; /* Set DEF_SEAL */ + param |= 1 << 5; /* Set DEF_SEAL */ rv = bq27621_write8(REGISTERS_BLOCK_OP_CONFIG_B, param); checksum += param; /* 1B */ @@ -273,7 +278,7 @@ static int bq27621_seal(void) return rv; } -#define CHECKSUM_2B(x) ((x & 0xff) + ((x>>8) & 0xff)) +#define CHECKSUM_2B(x) ((x & 0xff) + ((x >> 8) & 0xff)) static int bq27621_init(void) { @@ -308,18 +313,18 @@ static int bq27621_init(void) if (BQ27621_CHEM_ID == 0x1210) rv |= bq27621_write(REG_CTRL, - CONTROL_ALT_CHEM1); + CONTROL_ALT_CHEM1); if (BQ27621_CHEM_ID == 0x0354) rv |= bq27621_write(REG_CTRL, - CONTROL_ALT_CHEM2); + CONTROL_ALT_CHEM2); - /* - * The datasheet recommends checking the status here. - * - * If the CHEMCHG is active, it wasn't successful. - * - * There's no recommendation for what to do if it isn't. - */ + /* + * The datasheet recommends checking the status here. + * + * If the CHEMCHG is active, it wasn't successful. + * + * There's no recommendation for what to do if it isn't. + */ rv |= bq27621_write(REG_CTRL, CONTROL_EXIT_CFGUPDATE); } @@ -374,7 +379,6 @@ static int bq27621_init(void) checksum = 0xff - (0xff & checksum); - if (rv) return rv; @@ -403,7 +407,7 @@ static void probe_type_id_init(void) if (rv) { /* Try it once more */ rv = bq27621_write(REG_CTRL, CONTROL_RESET); - rv |= bq27621_init(); + rv |= bq27621_init(); } } @@ -555,9 +559,9 @@ int battery_wait_for_stable(void) } #ifdef CONFIG_CMD_BATDEBUG - #define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) #else - #define CPRINTF(format, args...) +#define CPRINTF(format, args...) #endif #ifdef CONFIG_CMD_BATDEBUG @@ -574,9 +578,7 @@ static int command_fgunseal(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal, - "", - "Unseal the fg"); +DECLARE_CONSOLE_COMMAND(fgunseal, command_fgunseal, "", "Unseal the fg"); static int command_fgseal(int argc, char **argv) { @@ -590,9 +592,7 @@ static int command_fgseal(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal, - "", - "Seal the fg"); +DECLARE_CONSOLE_COMMAND(fgseal, command_fgseal, "", "Seal the fg"); static int command_fginit(int argc, char **argv) { @@ -625,9 +625,7 @@ static int command_fginit(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fginit, command_fginit, - "[force]", - "Initialize the fg"); +DECLARE_CONSOLE_COMMAND(fginit, command_fginit, "[force]", "Initialize the fg"); static int command_fgprobe(int argc, char **argv) { @@ -641,9 +639,7 @@ static int command_fgprobe(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe, - "", - "Probe the fg"); +DECLARE_CONSOLE_COMMAND(fgprobe, command_fgprobe, "", "Probe the fg"); static int command_fgrd(int argc, char **argv) { @@ -675,8 +671,7 @@ static int command_fgrd(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd, - "cmd len", +DECLARE_CONSOLE_COMMAND(fgrd, command_fgrd, "cmd len", "Read _len_ words from the fg"); static int command_fgcmd(int argc, char **argv) @@ -708,11 +703,9 @@ static int command_fgcmd(int argc, char **argv) CPRINTF("Write 2 bytes @0xaa %0x: 0x%0x\n", cmd, data); return bq27621_write(cmd, data); } - } -DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd, - "cmd data [byte]", +DECLARE_CONSOLE_COMMAND(fgcmd, command_fgcmd, "cmd data [byte]", "Send a cmd to the fg"); static int command_fgcmdrd(int argc, char **argv) @@ -739,8 +732,8 @@ static int command_fgcmdrd(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(fgcmdrd, command_fgcmdrd, - "cmd data", - "Send a 2-byte cmd to the fg, read back the 2-byte result"); +DECLARE_CONSOLE_COMMAND( + fgcmdrd, command_fgcmdrd, "cmd data", + "Send a 2-byte cmd to the fg, read back the 2-byte result"); #endif /* CONFIG_CMD_BATDEBUG */ -- cgit v1.2.1 From eb554841abb1bd08d75ac7ff35dd65a6fd4b2b82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:15 -0600 Subject: board/atlas/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifbbb52d5b23068fdce5cd0bcd37c46a227f410b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728015 Reviewed-by: Jeremy Bettis --- board/atlas/board.c | 169 +++++++++++++++++++++++----------------------------- 1 file changed, 75 insertions(+), 94 deletions(-) diff --git a/board/atlas/board.c b/board/atlas/board.c index 64d0789dd9..9b888e0cac 100644 --- a/board/atlas/board.c +++ b/board/atlas/board.c @@ -46,8 +46,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -85,19 +85,19 @@ __override struct keyboard_scan_config keyscan_config = { /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { 3, 0, 10000 }, - [PWM_CH_DB0_LED_BLUE] = { - 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, - [PWM_CH_DB0_LED_RED] = { - 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, - [PWM_CH_DB0_LED_GREEN] = { - 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, - [PWM_CH_DB1_LED_BLUE] = { - 1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, - [PWM_CH_DB1_LED_RED] = { - 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, - [PWM_CH_DB1_LED_GREEN] = { - 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 2400 }, + [PWM_CH_KBLIGHT] = { 3, 0, 10000 }, + [PWM_CH_DB0_LED_BLUE] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, + [PWM_CH_DB0_LED_RED] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, + [PWM_CH_DB0_LED_GREEN] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, + [PWM_CH_DB1_LED_BLUE] = { 1, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, + [PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, + [PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 2400 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -114,66 +114,46 @@ const struct adc_t adc_channels[] = { * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT*1000/18, - ADC_READ_MAX+1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read * 0.8V @ 45 W, i.e. 56250 uW/mV. Using ADC_MAX_VOLT*56250 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C0_POWER_SCL, - .sda = GPIO_EC_I2C0_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C1_USB_C0_SCL, - .sda = GPIO_EC_I2C1_USB_C0_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C2_USB_C1_SCL, - .sda = GPIO_EC_I2C2_USB_C1_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 100, - .scl = GPIO_EC_I2C3_SENSOR_3V3_SCL, - .sda = GPIO_EC_I2C3_SENSOR_3V3_SDA - }, - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C4_BATTERY_SCL, - .sda = GPIO_EC_I2C4_BATTERY_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C0_POWER_SCL, + .sda = GPIO_EC_I2C0_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C1_USB_C0_SCL, + .sda = GPIO_EC_I2C1_USB_C0_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C2_USB_C1_SCL, + .sda = GPIO_EC_I2C2_USB_C1_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 100, + .scl = GPIO_EC_I2C3_SENSOR_3V3_SCL, + .sda = GPIO_EC_I2C3_SENSOR_3V3_SDA }, + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C4_BATTERY_SCL, + .sda = GPIO_EC_I2C4_BATTERY_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -247,9 +227,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { @@ -269,16 +249,16 @@ uint16_t tcpc_get_alert_status(void) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* BD99992GW temp sensors are only readable in S0 */ - {"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, - {"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM3}, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, + { "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -304,12 +284,12 @@ static void board_report_pmic_fault(const char *str) /* VRFAULT has occurred, print VRFAULT status bits. */ /* PWRSTAT1 */ - i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - BD99992GW_REG_PWRSTAT1, &pwrstat1); + i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT1, + &pwrstat1); /* PWRSTAT2 */ - i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - BD99992GW_REG_PWRSTAT2, &pwrstat2); + i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_PWRSTAT2, + &pwrstat2); CPRINTS("PMIC VRFAULT: %s", str); CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1, @@ -350,8 +330,8 @@ static void board_pmic_disable_slp_s0_vr_decay(void) * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - BD99992GW_REG_V18ACNT, 0x2a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT, + 0x2a); /* * V085ACNT: @@ -383,8 +363,8 @@ static void board_pmic_enable_slp_s0_vr_decay(void) * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - BD99992GW_REG_V18ACNT, 0x6a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, BD99992GW_REG_V18ACNT, + 0x6a); /* * V085ACNT: @@ -397,8 +377,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void) BD99992GW_REG_V085ACNT, 0x6a); } -__override void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__override void power_board_handle_host_sleep_event(enum host_sleep_event state) { if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) board_pmic_enable_slp_s0_vr_decay(); @@ -517,8 +496,8 @@ int board_set_active_charge_port(int charge_port) int is_real_port = (charge_port >= 0 && charge_port < CONFIG_USB_PD_PORT_MAX_COUNT); /* check if we are sourcing VBUS on the port */ - int is_source = gpio_get_level(charge_port == 0 ? - GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN); + int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN : + GPIO_USB_C1_5V_EN); if (is_real_port && is_source) { CPRINTS("No charging from p%d", charge_port); @@ -534,10 +513,12 @@ int board_set_active_charge_port(int charge_port) } else { /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_EN_USB_C0_CHARGE_L : - GPIO_EN_USB_C1_CHARGE_L, 1); + GPIO_EN_USB_C1_CHARGE_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_EN_USB_C1_CHARGE_L : - GPIO_EN_USB_C0_CHARGE_L, 0); + GPIO_EN_USB_C0_CHARGE_L, + 0); } return EC_SUCCESS; @@ -568,12 +549,12 @@ DECLARE_HOOK(HOOK_INIT, board_charger_init, HOOK_PRIO_DEFAULT); * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = charger_derate(charge_ma); - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } static void board_chipset_suspend(void) -- cgit v1.2.1 From 2b563bee547a3a2adc01150640861f1c7d6aca8e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:35 -0600 Subject: driver/charger/bq24715.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ad863daf5fa5936b39dd450e814aa38d392a0e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729958 Reviewed-by: Jeremy Bettis --- driver/charger/bq24715.h | 187 +++++++++++++++++++++++------------------------ 1 file changed, 93 insertions(+), 94 deletions(-) diff --git a/driver/charger/bq24715.h b/driver/charger/bq24715.h index 644f995f2e..62fc4f0f7f 100644 --- a/driver/charger/bq24715.h +++ b/driver/charger/bq24715.h @@ -14,118 +14,117 @@ */ /* Chip specific registers */ -#define BQ24715_CHARGE_OPTION 0x12 -#define BQ24715_CHARGE_CURRENT 0x14 -#define BQ24715_MAX_CHARGE_VOLTAGE 0x15 -#define BQ24715_MIN_SYSTEM_VOLTAGE 0x3e -#define BQ24715_INPUT_CURRENT 0x3f -#define BQ24715_MANUFACTURER_ID 0xfe -#define BQ24715_DEVICE_ID 0xff +#define BQ24715_CHARGE_OPTION 0x12 +#define BQ24715_CHARGE_CURRENT 0x14 +#define BQ24715_MAX_CHARGE_VOLTAGE 0x15 +#define BQ24715_MIN_SYSTEM_VOLTAGE 0x3e +#define BQ24715_INPUT_CURRENT 0x3f +#define BQ24715_MANUFACTURER_ID 0xfe +#define BQ24715_DEVICE_ID 0xff /* ChargeOption Register - 0x12 */ -#define OPT_LOWPOWER_MASK BIT(15) -#define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15) -#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15) -#define OPT_WATCHDOG_MASK (3 << 13) -#define OPT_WATCHDOG_DISABLE (0 << 13) -#define OPT_WATCHDOG_44SEC BIT(13) -#define OPT_WATCHDOG_88SEC (2 << 13) -#define OPT_WATCHDOG_175SEC (3 << 13) -#define OPT_SYSOVP_MASK BIT(12) -#define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12) -#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12) -#define OPT_SYSOVP_STATUS_MASK BIT(11) -#define OPT_SYSOVP_STATUS BIT(11) -#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10) -#define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10) -#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10) -#define OPT_SWITCH_FREQ_MASK (3 << 8) -#define OPT_SWITCH_FREQ_600KHZ (0 << 8) -#define OPT_SWITCH_FREQ_800KHZ BIT(8) -#define OPT_SWITCH_FREQ_1MHZ (2 << 8) -#define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8) -#define OPT_ACOC_MASK BIT(7) -#define OPT_ACOC_DISABLED (0 << 7) -#define OPT_ACOC_333PCT_IPDM BIT(7) -#define OPT_LSFET_OCP_MASK BIT(6) -#define OPT_LSFET_OCP_250MV (0 << 6) -#define OPT_LSFET_OCP_350MV BIT(6) -#define OPT_LEARN_MASK BIT(5) -#define OPT_LEARN_DISABLE (0 << 5) -#define OPT_LEARN_ENABLE BIT(5) -#define OPT_IOUT_MASK BIT(4) -#define OPT_IOUT_40X (0 << 4) -#define OPT_IOUT_16X BIT(4) -#define OPT_FIX_IOUT_MASK BIT(3) -#define OPT_FIX_IOUT_IDPM_EN (0 << 3) -#define OPT_FIX_IOUT_ALWAYS BIT(3) -#define OPT_LDO_MODE_MASK BIT(2) -#define OPT_LDO_DISABLE (0 << 2) -#define OPT_LDO_ENABLE BIT(2) -#define OPT_IDPM_MASK BIT(1) -#define OPT_IDPM_DISABLE (0 << 1) -#define OPT_IDPM_ENABLE BIT(1) -#define OPT_CHARGE_INHIBIT_MASK BIT(0) -#define OPT_CHARGE_ENABLE (0 << 0) -#define OPT_CHARGE_DISABLE BIT(0) - +#define OPT_LOWPOWER_MASK BIT(15) +#define OPT_LOWPOWER_DSCHRG_I_MON_ON (0 << 15) +#define OPT_LOWPOWER_DSCHRG_I_MON_OFF BIT(15) +#define OPT_WATCHDOG_MASK (3 << 13) +#define OPT_WATCHDOG_DISABLE (0 << 13) +#define OPT_WATCHDOG_44SEC BIT(13) +#define OPT_WATCHDOG_88SEC (2 << 13) +#define OPT_WATCHDOG_175SEC (3 << 13) +#define OPT_SYSOVP_MASK BIT(12) +#define OPT_SYSOVP_15P1_3SEC_10P1_2SEC (0 << 12) +#define OPT_SYSOVP_17P0_3SEC_11P3_2SEC BIT(12) +#define OPT_SYSOVP_STATUS_MASK BIT(11) +#define OPT_SYSOVP_STATUS BIT(11) +#define OPT_AUDIO_FREQ_LIMIT_MASK BIT(10) +#define OPT_AUDIO_FREQ_NO_LIMIT (0 << 10) +#define OPT_AUDIO_FREQ_40KHZ_LIMIT BIT(10) +#define OPT_SWITCH_FREQ_MASK (3 << 8) +#define OPT_SWITCH_FREQ_600KHZ (0 << 8) +#define OPT_SWITCH_FREQ_800KHZ BIT(8) +#define OPT_SWITCH_FREQ_1MHZ (2 << 8) +#define OPT_SWITCH_FREQ_800KHZ_DUP (3 << 8) +#define OPT_ACOC_MASK BIT(7) +#define OPT_ACOC_DISABLED (0 << 7) +#define OPT_ACOC_333PCT_IPDM BIT(7) +#define OPT_LSFET_OCP_MASK BIT(6) +#define OPT_LSFET_OCP_250MV (0 << 6) +#define OPT_LSFET_OCP_350MV BIT(6) +#define OPT_LEARN_MASK BIT(5) +#define OPT_LEARN_DISABLE (0 << 5) +#define OPT_LEARN_ENABLE BIT(5) +#define OPT_IOUT_MASK BIT(4) +#define OPT_IOUT_40X (0 << 4) +#define OPT_IOUT_16X BIT(4) +#define OPT_FIX_IOUT_MASK BIT(3) +#define OPT_FIX_IOUT_IDPM_EN (0 << 3) +#define OPT_FIX_IOUT_ALWAYS BIT(3) +#define OPT_LDO_MODE_MASK BIT(2) +#define OPT_LDO_DISABLE (0 << 2) +#define OPT_LDO_ENABLE BIT(2) +#define OPT_IDPM_MASK BIT(1) +#define OPT_IDPM_DISABLE (0 << 1) +#define OPT_IDPM_ENABLE BIT(1) +#define OPT_CHARGE_INHIBIT_MASK BIT(0) +#define OPT_CHARGE_ENABLE (0 << 0) +#define OPT_CHARGE_DISABLE BIT(0) /* ChargeCurrent Register - 0x14 * The ChargeCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_I_64MA BIT(6) -#define CHARGE_I_128MA BIT(7) -#define CHARGE_I_256MA BIT(8) -#define CHARGE_I_512MA BIT(9) -#define CHARGE_I_1024MA BIT(10) -#define CHARGE_I_2048MA BIT(11) -#define CHARGE_I_4096MA BIT(12) -#define CHARGE_I_OFF (0) -#define CHARGE_I_MIN (128) -#define CHARGE_I_MAX (8128) -#define CHARGE_I_STEP (64) +#define CHARGE_I_64MA BIT(6) +#define CHARGE_I_128MA BIT(7) +#define CHARGE_I_256MA BIT(8) +#define CHARGE_I_512MA BIT(9) +#define CHARGE_I_1024MA BIT(10) +#define CHARGE_I_2048MA BIT(11) +#define CHARGE_I_4096MA BIT(12) +#define CHARGE_I_OFF (0) +#define CHARGE_I_MIN (128) +#define CHARGE_I_MAX (8128) +#define CHARGE_I_STEP (64) /* MaxChargeVoltage Register - 0x15 * The MaxChargeVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define CHARGE_V_16MV BIT(4) -#define CHARGE_V_32MV BIT(5) -#define CHARGE_V_64MV BIT(6) -#define CHARGE_V_128MV BIT(7) -#define CHARGE_V_256MV BIT(8) -#define CHARGE_V_512MV BIT(9) -#define CHARGE_V_1024MV BIT(10) -#define CHARGE_V_2048MV BIT(11) -#define CHARGE_V_4096MV BIT(12) -#define CHARGE_V_8192MV BIT(13) -#define CHARGE_V_MIN (4096) -#define CHARGE_V_MAX (0x3ff0) -#define CHARGE_V_STEP (16) +#define CHARGE_V_16MV BIT(4) +#define CHARGE_V_32MV BIT(5) +#define CHARGE_V_64MV BIT(6) +#define CHARGE_V_128MV BIT(7) +#define CHARGE_V_256MV BIT(8) +#define CHARGE_V_512MV BIT(9) +#define CHARGE_V_1024MV BIT(10) +#define CHARGE_V_2048MV BIT(11) +#define CHARGE_V_4096MV BIT(12) +#define CHARGE_V_8192MV BIT(13) +#define CHARGE_V_MIN (4096) +#define CHARGE_V_MAX (0x3ff0) +#define CHARGE_V_STEP (16) /* MinSystemVoltage Register - 0x3e * The MinSystemVoltage register controls a DAC. Therefore * the below definitions are cummulative. */ -#define MIN_SYS_V_256MV BIT(8) -#define MIN_SYS_V_512MV BIT(9) -#define MIN_SYS_V_1024MV BIT(10) -#define MIN_SYS_V_2048MV BIT(11) -#define MIN_SYS_V_4096MV BIT(12) -#define MIN_SYS_V_8192MV BIT(13) -#define MIN_SYS_V_MIN (4096) +#define MIN_SYS_V_256MV BIT(8) +#define MIN_SYS_V_512MV BIT(9) +#define MIN_SYS_V_1024MV BIT(10) +#define MIN_SYS_V_2048MV BIT(11) +#define MIN_SYS_V_4096MV BIT(12) +#define MIN_SYS_V_8192MV BIT(13) +#define MIN_SYS_V_MIN (4096) /* InputCurrent Register - 0x3f * The InputCurrent register controls a DAC. Therefore * the below definitions are cummulative. */ -#define INPUT_I_64MA BIT(6) -#define INPUT_I_128MA BIT(7) -#define INPUT_I_256MA BIT(8) -#define INPUT_I_512MA BIT(9) -#define INPUT_I_1024MA BIT(10) -#define INPUT_I_2048MA BIT(11) -#define INPUT_I_4096MA BIT(12) -#define INPUT_I_MIN (128) -#define INPUT_I_MAX (8064) -#define INPUT_I_STEP (64) +#define INPUT_I_64MA BIT(6) +#define INPUT_I_128MA BIT(7) +#define INPUT_I_256MA BIT(8) +#define INPUT_I_512MA BIT(9) +#define INPUT_I_1024MA BIT(10) +#define INPUT_I_2048MA BIT(11) +#define INPUT_I_4096MA BIT(12) +#define INPUT_I_MIN (128) +#define INPUT_I_MAX (8064) +#define INPUT_I_STEP (64) extern const struct charger_drv bq24715_drv; -- cgit v1.2.1 From 265cafe3aa061a1df294ae11e6e617bf7278358e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:37 -0600 Subject: chip/it83xx/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70307291826ecff5f6aaecf0121ee0e3c1dc994e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729205 Reviewed-by: Jeremy Bettis --- chip/it83xx/registers.h | 2678 +++++++++++++++++++++++------------------------ 1 file changed, 1336 insertions(+), 1342 deletions(-) diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index b752f012d8..1a33cfea32 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -15,772 +15,772 @@ /* IRQ numbers */ /* Group 0 */ -#define IT83XX_IRQ_WKO20 1 -#define IT83XX_IRQ_KBC_OUT 2 -#define IT83XX_IRQ_PMC_OUT 3 -#define IT83XX_IRQ_SMB_D 4 -#define IT83XX_IRQ_WKINTAD 5 -#define IT83XX_IRQ_WKO23 6 -#define IT83XX_IRQ_PWM 7 +#define IT83XX_IRQ_WKO20 1 +#define IT83XX_IRQ_KBC_OUT 2 +#define IT83XX_IRQ_PMC_OUT 3 +#define IT83XX_IRQ_SMB_D 4 +#define IT83XX_IRQ_WKINTAD 5 +#define IT83XX_IRQ_WKO23 6 +#define IT83XX_IRQ_PWM 7 /* Group 1 */ -#define IT83XX_IRQ_ADC 8 -#define IT83XX_IRQ_SMB_A 9 -#define IT83XX_IRQ_SMB_B 10 -#define IT83XX_IRQ_KB_MATRIX 11 -#define IT83XX_IRQ_WKO26 12 -#define IT83XX_IRQ_WKINTC 13 -#define IT83XX_IRQ_WKO25 14 -#define IT83XX_IRQ_CIR 15 +#define IT83XX_IRQ_ADC 8 +#define IT83XX_IRQ_SMB_A 9 +#define IT83XX_IRQ_SMB_B 10 +#define IT83XX_IRQ_KB_MATRIX 11 +#define IT83XX_IRQ_WKO26 12 +#define IT83XX_IRQ_WKINTC 13 +#define IT83XX_IRQ_WKO25 14 +#define IT83XX_IRQ_CIR 15 /* Group 2 */ -#define IT83XX_IRQ_SMB_C 16 -#define IT83XX_IRQ_WKO24 17 -#define IT83XX_IRQ_PS2_2 18 -#define IT83XX_IRQ_PS2_1 19 -#define IT83XX_IRQ_PS2_0 20 -#define IT83XX_IRQ_WKO22 21 -#define IT83XX_IRQ_SMFI 22 -#define IT83XX_IRQ_USB 23 +#define IT83XX_IRQ_SMB_C 16 +#define IT83XX_IRQ_WKO24 17 +#define IT83XX_IRQ_PS2_2 18 +#define IT83XX_IRQ_PS2_1 19 +#define IT83XX_IRQ_PS2_0 20 +#define IT83XX_IRQ_WKO22 21 +#define IT83XX_IRQ_SMFI 22 +#define IT83XX_IRQ_USB 23 /* Group 3 */ -#define IT83XX_IRQ_KBC_IN 24 -#define IT83XX_IRQ_PMC_IN 25 -#define IT83XX_IRQ_PMC2_OUT 26 -#define IT83XX_IRQ_PMC2_IN 27 -#define IT83XX_IRQ_GINT 28 -#define IT83XX_IRQ_EGPC 29 -#define IT83XX_IRQ_EXT_TIMER1 30 -#define IT83XX_IRQ_WKO21 31 +#define IT83XX_IRQ_KBC_IN 24 +#define IT83XX_IRQ_PMC_IN 25 +#define IT83XX_IRQ_PMC2_OUT 26 +#define IT83XX_IRQ_PMC2_IN 27 +#define IT83XX_IRQ_GINT 28 +#define IT83XX_IRQ_EGPC 29 +#define IT83XX_IRQ_EXT_TIMER1 30 +#define IT83XX_IRQ_WKO21 31 /* Group 4 */ -#define IT83XX_IRQ_GPINT0 32 -#define IT83XX_IRQ_GPINT1 33 -#define IT83XX_IRQ_GPINT2 34 -#define IT83XX_IRQ_GPINT3 35 -#define IT83XX_IRQ_CIR_GPINT 36 -#define IT83XX_IRQ_SSPI 37 -#define IT83XX_IRQ_UART1 38 -#define IT83XX_IRQ_UART2 39 +#define IT83XX_IRQ_GPINT0 32 +#define IT83XX_IRQ_GPINT1 33 +#define IT83XX_IRQ_GPINT2 34 +#define IT83XX_IRQ_GPINT3 35 +#define IT83XX_IRQ_CIR_GPINT 36 +#define IT83XX_IRQ_SSPI 37 +#define IT83XX_IRQ_UART1 38 +#define IT83XX_IRQ_UART2 39 /* Group 5 */ -#define IT83XX_IRQ_WKO50 40 -#define IT83XX_IRQ_WKO51 41 -#define IT83XX_IRQ_WKO52 42 -#define IT83XX_IRQ_WKO53 43 -#define IT83XX_IRQ_WKO54 44 -#define IT83XX_IRQ_WKO55 45 -#define IT83XX_IRQ_WKO56 46 -#define IT83XX_IRQ_WKO57 47 +#define IT83XX_IRQ_WKO50 40 +#define IT83XX_IRQ_WKO51 41 +#define IT83XX_IRQ_WKO52 42 +#define IT83XX_IRQ_WKO53 43 +#define IT83XX_IRQ_WKO54 44 +#define IT83XX_IRQ_WKO55 45 +#define IT83XX_IRQ_WKO56 46 +#define IT83XX_IRQ_WKO57 47 /* Group 6 */ -#define IT83XX_IRQ_WKO60 48 -#define IT83XX_IRQ_WKO61 49 -#define IT83XX_IRQ_WKO62 50 -#define IT83XX_IRQ_WKO63 51 -#define IT83XX_IRQ_WKO64 52 -#define IT83XX_IRQ_WKO65 53 -#define IT83XX_IRQ_WKO66 54 -#define IT83XX_IRQ_WKO67 55 +#define IT83XX_IRQ_WKO60 48 +#define IT83XX_IRQ_WKO61 49 +#define IT83XX_IRQ_WKO62 50 +#define IT83XX_IRQ_WKO63 51 +#define IT83XX_IRQ_WKO64 52 +#define IT83XX_IRQ_WKO65 53 +#define IT83XX_IRQ_WKO66 54 +#define IT83XX_IRQ_WKO67 55 /* Group 7 */ -#define IT83XX_IRQ_RTCT_ALARM1 56 -#define IT83XX_IRQ_RTCT_ALARM2 57 -#define IT83XX_IRQ_EXT_TIMER2 58 -#define IT83XX_IRQ_DEFERRED_SPI 59 -#define IT83XX_IRQ_TMR_A0 60 -#define IT83XX_IRQ_TMR_A1 61 -#define IT83XX_IRQ_TMR_B0 62 -#define IT83XX_IRQ_TMR_B1 63 +#define IT83XX_IRQ_RTCT_ALARM1 56 +#define IT83XX_IRQ_RTCT_ALARM2 57 +#define IT83XX_IRQ_EXT_TIMER2 58 +#define IT83XX_IRQ_DEFERRED_SPI 59 +#define IT83XX_IRQ_TMR_A0 60 +#define IT83XX_IRQ_TMR_A1 61 +#define IT83XX_IRQ_TMR_B0 62 +#define IT83XX_IRQ_TMR_B1 63 /* Group 8 */ -#define IT83XX_IRQ_PMC2EX_OUT 64 -#define IT83XX_IRQ_PMC2EX_IN 65 -#define IT83XX_IRQ_PMC3_OUT 66 -#define IT83XX_IRQ_PMC3_IN 67 -#define IT83XX_IRQ_PMC4_OUT 68 -#define IT83XX_IRQ_PMC4_IN 69 -#define IT83XX_IRQ_I2BRAM 71 +#define IT83XX_IRQ_PMC2EX_OUT 64 +#define IT83XX_IRQ_PMC2EX_IN 65 +#define IT83XX_IRQ_PMC3_OUT 66 +#define IT83XX_IRQ_PMC3_IN 67 +#define IT83XX_IRQ_PMC4_OUT 68 +#define IT83XX_IRQ_PMC4_IN 69 +#define IT83XX_IRQ_I2BRAM 71 /* Group 9 */ -#define IT83XX_IRQ_WKO70 72 -#define IT83XX_IRQ_WKO71 73 -#define IT83XX_IRQ_WKO72 74 -#define IT83XX_IRQ_WKO73 75 -#define IT83XX_IRQ_WKO74 76 -#define IT83XX_IRQ_WKO75 77 -#define IT83XX_IRQ_WKO76 78 -#define IT83XX_IRQ_WKO77 79 +#define IT83XX_IRQ_WKO70 72 +#define IT83XX_IRQ_WKO71 73 +#define IT83XX_IRQ_WKO72 74 +#define IT83XX_IRQ_WKO73 75 +#define IT83XX_IRQ_WKO74 76 +#define IT83XX_IRQ_WKO75 77 +#define IT83XX_IRQ_WKO76 78 +#define IT83XX_IRQ_WKO77 79 /* Group 10 */ -#define IT83XX_IRQ_EXT_TMR8 80 +#define IT83XX_IRQ_EXT_TMR8 80 #define IT83XX_IRQ_SMB_CLOCK_HELD 81 -#define IT83XX_IRQ_CEC 82 -#define IT83XX_IRQ_H2RAM_LPC 83 -#define IT83XX_IRQ_HW_KB_SCAN 84 -#define IT83XX_IRQ_WKO88 85 -#define IT83XX_IRQ_WKO89 86 -#define IT83XX_IRQ_WKO90 87 +#define IT83XX_IRQ_CEC 82 +#define IT83XX_IRQ_H2RAM_LPC 83 +#define IT83XX_IRQ_HW_KB_SCAN 84 +#define IT83XX_IRQ_WKO88 85 +#define IT83XX_IRQ_WKO89 86 +#define IT83XX_IRQ_WKO90 87 /* Group 11 */ -#define IT83XX_IRQ_WKO80 88 -#define IT83XX_IRQ_WKO81 89 -#define IT83XX_IRQ_WKO82 90 -#define IT83XX_IRQ_WKO83 91 -#define IT83XX_IRQ_WKO84 92 -#define IT83XX_IRQ_WKO85 93 -#define IT83XX_IRQ_WKO86 94 -#define IT83XX_IRQ_WKO87 95 +#define IT83XX_IRQ_WKO80 88 +#define IT83XX_IRQ_WKO81 89 +#define IT83XX_IRQ_WKO82 90 +#define IT83XX_IRQ_WKO83 91 +#define IT83XX_IRQ_WKO84 92 +#define IT83XX_IRQ_WKO85 93 +#define IT83XX_IRQ_WKO86 94 +#define IT83XX_IRQ_WKO87 95 /* Group 12 */ -#define IT83XX_IRQ_WKO91 96 -#define IT83XX_IRQ_WKO92 97 -#define IT83XX_IRQ_WKO93 98 -#define IT83XX_IRQ_WKO94 99 -#define IT83XX_IRQ_WKO95 100 -#define IT83XX_IRQ_WKO96 101 -#define IT83XX_IRQ_WKO97 102 -#define IT83XX_IRQ_WKO98 103 +#define IT83XX_IRQ_WKO91 96 +#define IT83XX_IRQ_WKO92 97 +#define IT83XX_IRQ_WKO93 98 +#define IT83XX_IRQ_WKO94 99 +#define IT83XX_IRQ_WKO95 100 +#define IT83XX_IRQ_WKO96 101 +#define IT83XX_IRQ_WKO97 102 +#define IT83XX_IRQ_WKO98 103 /* Group 13 */ -#define IT83XX_IRQ_WKO99 104 -#define IT83XX_IRQ_WKO100 105 -#define IT83XX_IRQ_WKO101 106 -#define IT83XX_IRQ_WKO102 107 -#define IT83XX_IRQ_WKO103 108 -#define IT83XX_IRQ_WKO104 109 -#define IT83XX_IRQ_WKO105 110 -#define IT83XX_IRQ_WKO106 111 +#define IT83XX_IRQ_WKO99 104 +#define IT83XX_IRQ_WKO100 105 +#define IT83XX_IRQ_WKO101 106 +#define IT83XX_IRQ_WKO102 107 +#define IT83XX_IRQ_WKO103 108 +#define IT83XX_IRQ_WKO104 109 +#define IT83XX_IRQ_WKO105 110 +#define IT83XX_IRQ_WKO106 111 /* Group 14 */ -#define IT83XX_IRQ_WKO107 112 -#define IT83XX_IRQ_WKO108 113 -#define IT83XX_IRQ_WKO109 114 -#define IT83XX_IRQ_WKO110 115 -#define IT83XX_IRQ_WKO111 116 -#define IT83XX_IRQ_WKO112 117 -#define IT83XX_IRQ_WKO113 118 -#define IT83XX_IRQ_WKO114 119 +#define IT83XX_IRQ_WKO107 112 +#define IT83XX_IRQ_WKO108 113 +#define IT83XX_IRQ_WKO109 114 +#define IT83XX_IRQ_WKO110 115 +#define IT83XX_IRQ_WKO111 116 +#define IT83XX_IRQ_WKO112 117 +#define IT83XX_IRQ_WKO113 118 +#define IT83XX_IRQ_WKO114 119 /* Group 15 */ -#define IT83XX_IRQ_WKO115 120 -#define IT83XX_IRQ_WKO116 121 -#define IT83XX_IRQ_WKO117 122 -#define IT83XX_IRQ_WKO118 123 -#define IT83XX_IRQ_WKO119 124 -#define IT83XX_IRQ_WKO120 125 -#define IT83XX_IRQ_WKO121 126 -#define IT83XX_IRQ_WKO122 127 +#define IT83XX_IRQ_WKO115 120 +#define IT83XX_IRQ_WKO116 121 +#define IT83XX_IRQ_WKO117 122 +#define IT83XX_IRQ_WKO118 123 +#define IT83XX_IRQ_WKO119 124 +#define IT83XX_IRQ_WKO120 125 +#define IT83XX_IRQ_WKO121 126 +#define IT83XX_IRQ_WKO122 127 /* Group 16 */ -#define IT83XX_IRQ_WKO128 128 -#define IT83XX_IRQ_WKO129 129 -#define IT83XX_IRQ_WKO130 130 -#define IT83XX_IRQ_WKO131 131 -#define IT83XX_IRQ_WKO132 132 -#define IT83XX_IRQ_WKO133 133 -#define IT83XX_IRQ_WKO134 134 -#define IT83XX_IRQ_WKO135 135 +#define IT83XX_IRQ_WKO128 128 +#define IT83XX_IRQ_WKO129 129 +#define IT83XX_IRQ_WKO130 130 +#define IT83XX_IRQ_WKO131 131 +#define IT83XX_IRQ_WKO132 132 +#define IT83XX_IRQ_WKO133 133 +#define IT83XX_IRQ_WKO134 134 +#define IT83XX_IRQ_WKO135 135 /* Group 17 */ -#define IT83XX_IRQ_WKO136 136 -#define IT83XX_IRQ_WKO137 137 -#define IT83XX_IRQ_WKO138 138 -#define IT83XX_IRQ_WKO139 139 -#define IT83XX_IRQ_WKO140 140 -#define IT83XX_IRQ_WKO141 141 -#define IT83XX_IRQ_WKO142 142 -#define IT83XX_IRQ_WKO143 143 +#define IT83XX_IRQ_WKO136 136 +#define IT83XX_IRQ_WKO137 137 +#define IT83XX_IRQ_WKO138 138 +#define IT83XX_IRQ_WKO139 139 +#define IT83XX_IRQ_WKO140 140 +#define IT83XX_IRQ_WKO141 141 +#define IT83XX_IRQ_WKO142 142 +#define IT83XX_IRQ_WKO143 143 /* Group 18 */ -#define IT83XX_IRQ_WKO123 144 -#define IT83XX_IRQ_WKO124 145 -#define IT83XX_IRQ_WKO125 146 -#define IT83XX_IRQ_WKO126 147 -#define IT83XX_IRQ_PMC5_OUT 149 -#define IT83XX_IRQ_PMC5_IN 150 -#define IT83XX_IRQ_V_COMP 151 +#define IT83XX_IRQ_WKO123 144 +#define IT83XX_IRQ_WKO124 145 +#define IT83XX_IRQ_WKO125 146 +#define IT83XX_IRQ_WKO126 147 +#define IT83XX_IRQ_PMC5_OUT 149 +#define IT83XX_IRQ_PMC5_IN 150 +#define IT83XX_IRQ_V_COMP 151 /* Group 19 */ -#define IT83XX_IRQ_SMB_E 152 -#define IT83XX_IRQ_SMB_F 153 -#define IT83XX_IRQ_OSC_DMA 154 -#define IT83XX_IRQ_EXT_TIMER3 155 -#define IT83XX_IRQ_EXT_TIMER4 156 -#define IT83XX_IRQ_EXT_TIMER5 157 -#define IT83XX_IRQ_EXT_TIMER6 158 -#define IT83XX_IRQ_EXT_TIMER7 159 +#define IT83XX_IRQ_SMB_E 152 +#define IT83XX_IRQ_SMB_F 153 +#define IT83XX_IRQ_OSC_DMA 154 +#define IT83XX_IRQ_EXT_TIMER3 155 +#define IT83XX_IRQ_EXT_TIMER4 156 +#define IT83XX_IRQ_EXT_TIMER5 157 +#define IT83XX_IRQ_EXT_TIMER6 158 +#define IT83XX_IRQ_EXT_TIMER7 159 /* Group 20 */ -#define IT83XX_IRQ_PECI 160 -#define IT83XX_IRQ_SOFTWARE 161 -#define IT83XX_IRQ_ESPI 162 -#define IT83XX_IRQ_ESPI_VW 163 -#define IT83XX_IRQ_PCH_P80 164 -#define IT83XX_IRQ_USBPD0 165 -#define IT83XX_IRQ_USBPD1 166 +#define IT83XX_IRQ_PECI 160 +#define IT83XX_IRQ_SOFTWARE 161 +#define IT83XX_IRQ_ESPI 162 +#define IT83XX_IRQ_ESPI_VW 163 +#define IT83XX_IRQ_PCH_P80 164 +#define IT83XX_IRQ_USBPD0 165 +#define IT83XX_IRQ_USBPD1 166 /* Group 21 */ #if defined(CHIP_FAMILY_IT8320) -#define IT83XX_IRQ_WKO40 168 -#define IT83XX_IRQ_WKO45 169 -#define IT83XX_IRQ_WKO46 170 -#define IT83XX_IRQ_WKO144 171 -#define IT83XX_IRQ_WKO145 172 -#define IT83XX_IRQ_WKO146 173 -#define IT83XX_IRQ_WKO147 174 -#define IT83XX_IRQ_WKO148 175 +#define IT83XX_IRQ_WKO40 168 +#define IT83XX_IRQ_WKO45 169 +#define IT83XX_IRQ_WKO46 170 +#define IT83XX_IRQ_WKO144 171 +#define IT83XX_IRQ_WKO145 172 +#define IT83XX_IRQ_WKO146 173 +#define IT83XX_IRQ_WKO147 174 +#define IT83XX_IRQ_WKO148 175 /* Group 22 */ -#define IT83XX_IRQ_WKO149 176 -#define IT83XX_IRQ_WKO150 177 +#define IT83XX_IRQ_WKO149 176 +#define IT83XX_IRQ_WKO150 177 -#define IT83XX_IRQ_COUNT 178 +#define IT83XX_IRQ_COUNT 178 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) /* Group 21 */ -#define IT83XX_IRQ_AUDIO_IF 170 +#define IT83XX_IRQ_AUDIO_IF 170 #define IT83XX_IRQ_SPI_PERIPHERAL 171 -#define IT83XX_IRQ_DSP_ENGINE 172 -#define IT83XX_IRQ_NN_ENGINE 173 -#define IT83XX_IRQ_USBPD2 174 -#define IT83XX_IRQ_CRYPTO 175 +#define IT83XX_IRQ_DSP_ENGINE 172 +#define IT83XX_IRQ_NN_ENGINE 173 +#define IT83XX_IRQ_USBPD2 174 +#define IT83XX_IRQ_CRYPTO 175 /* Group 22 */ -#define IT83XX_IRQ_WKO40 176 -#define IT83XX_IRQ_WKO45 177 -#define IT83XX_IRQ_WKO46 178 -#define IT83XX_IRQ_WKO144 179 -#define IT83XX_IRQ_WKO145 180 -#define IT83XX_IRQ_WKO146 181 -#define IT83XX_IRQ_WKO147 182 -#define IT83XX_IRQ_WKO148 183 +#define IT83XX_IRQ_WKO40 176 +#define IT83XX_IRQ_WKO45 177 +#define IT83XX_IRQ_WKO46 178 +#define IT83XX_IRQ_WKO144 179 +#define IT83XX_IRQ_WKO145 180 +#define IT83XX_IRQ_WKO146 181 +#define IT83XX_IRQ_WKO147 182 +#define IT83XX_IRQ_WKO148 183 /* Group 23 */ -#define IT83XX_IRQ_WKO149 184 -#define IT83XX_IRQ_WKO150 185 -#define IT83XX_IRQ_SSPI1 191 +#define IT83XX_IRQ_WKO149 184 +#define IT83XX_IRQ_WKO150 185 +#define IT83XX_IRQ_SSPI1 191 /* Group 24 */ -#define IT83XX_IRQ_XLPIN0 192 -#define IT83XX_IRQ_XLPIN1 193 -#define IT83XX_IRQ_XLPIN2 194 -#define IT83XX_IRQ_XLPIN3 195 -#define IT83XX_IRQ_XLPIN4 196 -#define IT83XX_IRQ_XLPIN5 197 -#define IT83XX_IRQ_WEEK_ALARM 199 +#define IT83XX_IRQ_XLPIN0 192 +#define IT83XX_IRQ_XLPIN1 193 +#define IT83XX_IRQ_XLPIN2 194 +#define IT83XX_IRQ_XLPIN3 195 +#define IT83XX_IRQ_XLPIN4 196 +#define IT83XX_IRQ_XLPIN5 197 +#define IT83XX_IRQ_WEEK_ALARM 199 /* Group 25 */ -#define IT83XX_IRQ_GPO0 200 -#define IT83XX_IRQ_GPO1 201 -#define IT83XX_IRQ_GPO2 202 -#define IT83XX_IRQ_GPO3 203 +#define IT83XX_IRQ_GPO0 200 +#define IT83XX_IRQ_GPO1 201 +#define IT83XX_IRQ_GPO2 202 +#define IT83XX_IRQ_GPO3 203 /* Group 26 */ -#define IT83XX_IRQ_GPP0 208 -#define IT83XX_IRQ_GPP1 209 -#define IT83XX_IRQ_GPP2 210 -#define IT83XX_IRQ_GPP3 211 -#define IT83XX_IRQ_GPP4 212 -#define IT83XX_IRQ_GPP5 213 -#define IT83XX_IRQ_GPP6 214 +#define IT83XX_IRQ_GPP0 208 +#define IT83XX_IRQ_GPP1 209 +#define IT83XX_IRQ_GPP2 210 +#define IT83XX_IRQ_GPP3 211 +#define IT83XX_IRQ_GPP4 212 +#define IT83XX_IRQ_GPP5 213 +#define IT83XX_IRQ_GPP6 214 /* Group 27 */ -#define IT83XX_IRQ_GPQ0 216 -#define IT83XX_IRQ_GPQ1 217 -#define IT83XX_IRQ_GPQ2 218 -#define IT83XX_IRQ_GPQ3 219 -#define IT83XX_IRQ_GPQ4 220 -#define IT83XX_IRQ_GPQ5 221 +#define IT83XX_IRQ_GPQ0 216 +#define IT83XX_IRQ_GPQ1 217 +#define IT83XX_IRQ_GPQ2 218 +#define IT83XX_IRQ_GPQ3 219 +#define IT83XX_IRQ_GPQ4 220 +#define IT83XX_IRQ_GPQ5 221 /* Group 28 */ -#define IT83XX_IRQ_GPR0 224 -#define IT83XX_IRQ_GPR1 225 -#define IT83XX_IRQ_GPR2 226 -#define IT83XX_IRQ_GPR3 227 -#define IT83XX_IRQ_GPR4 228 -#define IT83XX_IRQ_GPR5 229 - -#define IT83XX_IRQ_COUNT 230 +#define IT83XX_IRQ_GPR0 224 +#define IT83XX_IRQ_GPR1 225 +#define IT83XX_IRQ_GPR2 226 +#define IT83XX_IRQ_GPR3 227 +#define IT83XX_IRQ_GPR4 228 +#define IT83XX_IRQ_GPR5 229 + +#define IT83XX_IRQ_COUNT 230 #endif /* !defined(CHIP_FAMILY_IT8320) */ /* IRQ dispatching to CPU INT vectors */ -#define IT83XX_CPU_INT_IRQ_1 2 -#define IT83XX_CPU_INT_IRQ_2 5 -#define IT83XX_CPU_INT_IRQ_3 4 -#define IT83XX_CPU_INT_IRQ_4 6 -#define IT83XX_CPU_INT_IRQ_5 2 -#define IT83XX_CPU_INT_IRQ_6 2 -#define IT83XX_CPU_INT_IRQ_7 4 -#define IT83XX_CPU_INT_IRQ_8 7 -#define IT83XX_CPU_INT_IRQ_9 6 -#define IT83XX_CPU_INT_IRQ_10 6 -#define IT83XX_CPU_INT_IRQ_11 5 -#define IT83XX_CPU_INT_IRQ_12 2 -#define IT83XX_CPU_INT_IRQ_13 2 -#define IT83XX_CPU_INT_IRQ_14 2 -#define IT83XX_CPU_INT_IRQ_15 8 -#define IT83XX_CPU_INT_IRQ_16 6 -#define IT83XX_CPU_INT_IRQ_17 2 -#define IT83XX_CPU_INT_IRQ_18 8 -#define IT83XX_CPU_INT_IRQ_19 8 -#define IT83XX_CPU_INT_IRQ_20 8 -#define IT83XX_CPU_INT_IRQ_21 2 -#define IT83XX_CPU_INT_IRQ_22 12 -#define IT83XX_CPU_INT_IRQ_23 12 -#define IT83XX_CPU_INT_IRQ_24 5 -#define IT83XX_CPU_INT_IRQ_25 4 -#define IT83XX_CPU_INT_IRQ_26 4 -#define IT83XX_CPU_INT_IRQ_27 4 -#define IT83XX_CPU_INT_IRQ_28 11 -#define IT83XX_CPU_INT_IRQ_29 11 -#define IT83XX_CPU_INT_IRQ_30 3 -#define IT83XX_CPU_INT_IRQ_31 2 -#define IT83XX_CPU_INT_IRQ_32 11 -#define IT83XX_CPU_INT_IRQ_33 11 -#define IT83XX_CPU_INT_IRQ_34 11 -#define IT83XX_CPU_INT_IRQ_35 11 -#define IT83XX_CPU_INT_IRQ_36 8 -#define IT83XX_CPU_INT_IRQ_37 9 -#define IT83XX_CPU_INT_IRQ_38 9 -#define IT83XX_CPU_INT_IRQ_39 9 -#define IT83XX_CPU_INT_IRQ_40 2 -#define IT83XX_CPU_INT_IRQ_41 2 -#define IT83XX_CPU_INT_IRQ_42 2 -#define IT83XX_CPU_INT_IRQ_43 2 -#define IT83XX_CPU_INT_IRQ_44 2 -#define IT83XX_CPU_INT_IRQ_45 2 -#define IT83XX_CPU_INT_IRQ_46 2 -#define IT83XX_CPU_INT_IRQ_47 2 -#define IT83XX_CPU_INT_IRQ_48 2 -#define IT83XX_CPU_INT_IRQ_49 2 -#define IT83XX_CPU_INT_IRQ_50 2 -#define IT83XX_CPU_INT_IRQ_51 2 -#define IT83XX_CPU_INT_IRQ_52 2 -#define IT83XX_CPU_INT_IRQ_53 2 -#define IT83XX_CPU_INT_IRQ_54 2 -#define IT83XX_CPU_INT_IRQ_55 2 -#define IT83XX_CPU_INT_IRQ_56 10 -#define IT83XX_CPU_INT_IRQ_57 10 -#define IT83XX_CPU_INT_IRQ_58 3 -#define IT83XX_CPU_INT_IRQ_59 12 -#define IT83XX_CPU_INT_IRQ_60 3 -#define IT83XX_CPU_INT_IRQ_61 3 -#define IT83XX_CPU_INT_IRQ_62 3 -#define IT83XX_CPU_INT_IRQ_63 3 -#define IT83XX_CPU_INT_IRQ_64 4 -#define IT83XX_CPU_INT_IRQ_65 4 -#define IT83XX_CPU_INT_IRQ_66 4 -#define IT83XX_CPU_INT_IRQ_67 4 -#define IT83XX_CPU_INT_IRQ_68 4 -#define IT83XX_CPU_INT_IRQ_69 4 -#define IT83XX_CPU_INT_IRQ_71 12 -#define IT83XX_CPU_INT_IRQ_72 2 -#define IT83XX_CPU_INT_IRQ_73 2 -#define IT83XX_CPU_INT_IRQ_74 2 -#define IT83XX_CPU_INT_IRQ_75 2 -#define IT83XX_CPU_INT_IRQ_76 2 -#define IT83XX_CPU_INT_IRQ_77 2 -#define IT83XX_CPU_INT_IRQ_78 2 -#define IT83XX_CPU_INT_IRQ_79 2 -#define IT83XX_CPU_INT_IRQ_80 3 -#define IT83XX_CPU_INT_IRQ_81 6 -#define IT83XX_CPU_INT_IRQ_82 12 -#define IT83XX_CPU_INT_IRQ_83 12 -#define IT83XX_CPU_INT_IRQ_84 5 -#define IT83XX_CPU_INT_IRQ_85 2 -#define IT83XX_CPU_INT_IRQ_86 2 -#define IT83XX_CPU_INT_IRQ_87 2 -#define IT83XX_CPU_INT_IRQ_88 2 -#define IT83XX_CPU_INT_IRQ_89 2 -#define IT83XX_CPU_INT_IRQ_90 2 -#define IT83XX_CPU_INT_IRQ_91 2 -#define IT83XX_CPU_INT_IRQ_92 2 -#define IT83XX_CPU_INT_IRQ_93 2 -#define IT83XX_CPU_INT_IRQ_94 2 -#define IT83XX_CPU_INT_IRQ_95 2 -#define IT83XX_CPU_INT_IRQ_96 2 -#define IT83XX_CPU_INT_IRQ_97 2 -#define IT83XX_CPU_INT_IRQ_98 2 -#define IT83XX_CPU_INT_IRQ_99 2 -#define IT83XX_CPU_INT_IRQ_100 2 -#define IT83XX_CPU_INT_IRQ_101 2 -#define IT83XX_CPU_INT_IRQ_102 2 -#define IT83XX_CPU_INT_IRQ_103 2 -#define IT83XX_CPU_INT_IRQ_104 2 -#define IT83XX_CPU_INT_IRQ_105 2 -#define IT83XX_CPU_INT_IRQ_106 2 -#define IT83XX_CPU_INT_IRQ_107 2 -#define IT83XX_CPU_INT_IRQ_108 2 -#define IT83XX_CPU_INT_IRQ_109 2 -#define IT83XX_CPU_INT_IRQ_110 2 -#define IT83XX_CPU_INT_IRQ_111 2 -#define IT83XX_CPU_INT_IRQ_112 2 -#define IT83XX_CPU_INT_IRQ_113 2 -#define IT83XX_CPU_INT_IRQ_114 2 -#define IT83XX_CPU_INT_IRQ_115 2 -#define IT83XX_CPU_INT_IRQ_116 2 -#define IT83XX_CPU_INT_IRQ_117 2 -#define IT83XX_CPU_INT_IRQ_118 2 -#define IT83XX_CPU_INT_IRQ_119 2 -#define IT83XX_CPU_INT_IRQ_120 2 -#define IT83XX_CPU_INT_IRQ_121 2 -#define IT83XX_CPU_INT_IRQ_122 2 -#define IT83XX_CPU_INT_IRQ_123 2 -#define IT83XX_CPU_INT_IRQ_124 2 -#define IT83XX_CPU_INT_IRQ_125 2 -#define IT83XX_CPU_INT_IRQ_126 2 -#define IT83XX_CPU_INT_IRQ_127 2 -#define IT83XX_CPU_INT_IRQ_128 2 -#define IT83XX_CPU_INT_IRQ_129 2 -#define IT83XX_CPU_INT_IRQ_130 2 -#define IT83XX_CPU_INT_IRQ_131 2 -#define IT83XX_CPU_INT_IRQ_132 2 -#define IT83XX_CPU_INT_IRQ_133 2 -#define IT83XX_CPU_INT_IRQ_134 2 -#define IT83XX_CPU_INT_IRQ_135 2 -#define IT83XX_CPU_INT_IRQ_136 2 -#define IT83XX_CPU_INT_IRQ_137 2 -#define IT83XX_CPU_INT_IRQ_138 2 -#define IT83XX_CPU_INT_IRQ_139 2 -#define IT83XX_CPU_INT_IRQ_140 2 -#define IT83XX_CPU_INT_IRQ_141 2 -#define IT83XX_CPU_INT_IRQ_142 2 -#define IT83XX_CPU_INT_IRQ_143 2 -#define IT83XX_CPU_INT_IRQ_144 2 -#define IT83XX_CPU_INT_IRQ_145 2 -#define IT83XX_CPU_INT_IRQ_146 2 -#define IT83XX_CPU_INT_IRQ_147 2 -#define IT83XX_CPU_INT_IRQ_149 4 -#define IT83XX_CPU_INT_IRQ_150 4 -#define IT83XX_CPU_INT_IRQ_151 7 -#define IT83XX_CPU_INT_IRQ_152 6 -#define IT83XX_CPU_INT_IRQ_153 6 -#define IT83XX_CPU_INT_IRQ_154 12 -#define IT83XX_CPU_INT_IRQ_155 3 -#define IT83XX_CPU_INT_IRQ_156 3 -#define IT83XX_CPU_INT_IRQ_157 3 -#define IT83XX_CPU_INT_IRQ_158 3 -#define IT83XX_CPU_INT_IRQ_159 3 -#define IT83XX_CPU_INT_IRQ_160 12 -#define IT83XX_CPU_INT_IRQ_161 12 -#define IT83XX_CPU_INT_IRQ_162 12 -#define IT83XX_CPU_INT_IRQ_163 12 -#define IT83XX_CPU_INT_IRQ_164 12 -#define IT83XX_CPU_INT_IRQ_165 12 -#define IT83XX_CPU_INT_IRQ_166 12 -#define IT83XX_CPU_INT_IRQ_167 12 -#define IT83XX_CPU_INT_IRQ_168 2 -#define IT83XX_CPU_INT_IRQ_169 2 +#define IT83XX_CPU_INT_IRQ_1 2 +#define IT83XX_CPU_INT_IRQ_2 5 +#define IT83XX_CPU_INT_IRQ_3 4 +#define IT83XX_CPU_INT_IRQ_4 6 +#define IT83XX_CPU_INT_IRQ_5 2 +#define IT83XX_CPU_INT_IRQ_6 2 +#define IT83XX_CPU_INT_IRQ_7 4 +#define IT83XX_CPU_INT_IRQ_8 7 +#define IT83XX_CPU_INT_IRQ_9 6 +#define IT83XX_CPU_INT_IRQ_10 6 +#define IT83XX_CPU_INT_IRQ_11 5 +#define IT83XX_CPU_INT_IRQ_12 2 +#define IT83XX_CPU_INT_IRQ_13 2 +#define IT83XX_CPU_INT_IRQ_14 2 +#define IT83XX_CPU_INT_IRQ_15 8 +#define IT83XX_CPU_INT_IRQ_16 6 +#define IT83XX_CPU_INT_IRQ_17 2 +#define IT83XX_CPU_INT_IRQ_18 8 +#define IT83XX_CPU_INT_IRQ_19 8 +#define IT83XX_CPU_INT_IRQ_20 8 +#define IT83XX_CPU_INT_IRQ_21 2 +#define IT83XX_CPU_INT_IRQ_22 12 +#define IT83XX_CPU_INT_IRQ_23 12 +#define IT83XX_CPU_INT_IRQ_24 5 +#define IT83XX_CPU_INT_IRQ_25 4 +#define IT83XX_CPU_INT_IRQ_26 4 +#define IT83XX_CPU_INT_IRQ_27 4 +#define IT83XX_CPU_INT_IRQ_28 11 +#define IT83XX_CPU_INT_IRQ_29 11 +#define IT83XX_CPU_INT_IRQ_30 3 +#define IT83XX_CPU_INT_IRQ_31 2 +#define IT83XX_CPU_INT_IRQ_32 11 +#define IT83XX_CPU_INT_IRQ_33 11 +#define IT83XX_CPU_INT_IRQ_34 11 +#define IT83XX_CPU_INT_IRQ_35 11 +#define IT83XX_CPU_INT_IRQ_36 8 +#define IT83XX_CPU_INT_IRQ_37 9 +#define IT83XX_CPU_INT_IRQ_38 9 +#define IT83XX_CPU_INT_IRQ_39 9 +#define IT83XX_CPU_INT_IRQ_40 2 +#define IT83XX_CPU_INT_IRQ_41 2 +#define IT83XX_CPU_INT_IRQ_42 2 +#define IT83XX_CPU_INT_IRQ_43 2 +#define IT83XX_CPU_INT_IRQ_44 2 +#define IT83XX_CPU_INT_IRQ_45 2 +#define IT83XX_CPU_INT_IRQ_46 2 +#define IT83XX_CPU_INT_IRQ_47 2 +#define IT83XX_CPU_INT_IRQ_48 2 +#define IT83XX_CPU_INT_IRQ_49 2 +#define IT83XX_CPU_INT_IRQ_50 2 +#define IT83XX_CPU_INT_IRQ_51 2 +#define IT83XX_CPU_INT_IRQ_52 2 +#define IT83XX_CPU_INT_IRQ_53 2 +#define IT83XX_CPU_INT_IRQ_54 2 +#define IT83XX_CPU_INT_IRQ_55 2 +#define IT83XX_CPU_INT_IRQ_56 10 +#define IT83XX_CPU_INT_IRQ_57 10 +#define IT83XX_CPU_INT_IRQ_58 3 +#define IT83XX_CPU_INT_IRQ_59 12 +#define IT83XX_CPU_INT_IRQ_60 3 +#define IT83XX_CPU_INT_IRQ_61 3 +#define IT83XX_CPU_INT_IRQ_62 3 +#define IT83XX_CPU_INT_IRQ_63 3 +#define IT83XX_CPU_INT_IRQ_64 4 +#define IT83XX_CPU_INT_IRQ_65 4 +#define IT83XX_CPU_INT_IRQ_66 4 +#define IT83XX_CPU_INT_IRQ_67 4 +#define IT83XX_CPU_INT_IRQ_68 4 +#define IT83XX_CPU_INT_IRQ_69 4 +#define IT83XX_CPU_INT_IRQ_71 12 +#define IT83XX_CPU_INT_IRQ_72 2 +#define IT83XX_CPU_INT_IRQ_73 2 +#define IT83XX_CPU_INT_IRQ_74 2 +#define IT83XX_CPU_INT_IRQ_75 2 +#define IT83XX_CPU_INT_IRQ_76 2 +#define IT83XX_CPU_INT_IRQ_77 2 +#define IT83XX_CPU_INT_IRQ_78 2 +#define IT83XX_CPU_INT_IRQ_79 2 +#define IT83XX_CPU_INT_IRQ_80 3 +#define IT83XX_CPU_INT_IRQ_81 6 +#define IT83XX_CPU_INT_IRQ_82 12 +#define IT83XX_CPU_INT_IRQ_83 12 +#define IT83XX_CPU_INT_IRQ_84 5 +#define IT83XX_CPU_INT_IRQ_85 2 +#define IT83XX_CPU_INT_IRQ_86 2 +#define IT83XX_CPU_INT_IRQ_87 2 +#define IT83XX_CPU_INT_IRQ_88 2 +#define IT83XX_CPU_INT_IRQ_89 2 +#define IT83XX_CPU_INT_IRQ_90 2 +#define IT83XX_CPU_INT_IRQ_91 2 +#define IT83XX_CPU_INT_IRQ_92 2 +#define IT83XX_CPU_INT_IRQ_93 2 +#define IT83XX_CPU_INT_IRQ_94 2 +#define IT83XX_CPU_INT_IRQ_95 2 +#define IT83XX_CPU_INT_IRQ_96 2 +#define IT83XX_CPU_INT_IRQ_97 2 +#define IT83XX_CPU_INT_IRQ_98 2 +#define IT83XX_CPU_INT_IRQ_99 2 +#define IT83XX_CPU_INT_IRQ_100 2 +#define IT83XX_CPU_INT_IRQ_101 2 +#define IT83XX_CPU_INT_IRQ_102 2 +#define IT83XX_CPU_INT_IRQ_103 2 +#define IT83XX_CPU_INT_IRQ_104 2 +#define IT83XX_CPU_INT_IRQ_105 2 +#define IT83XX_CPU_INT_IRQ_106 2 +#define IT83XX_CPU_INT_IRQ_107 2 +#define IT83XX_CPU_INT_IRQ_108 2 +#define IT83XX_CPU_INT_IRQ_109 2 +#define IT83XX_CPU_INT_IRQ_110 2 +#define IT83XX_CPU_INT_IRQ_111 2 +#define IT83XX_CPU_INT_IRQ_112 2 +#define IT83XX_CPU_INT_IRQ_113 2 +#define IT83XX_CPU_INT_IRQ_114 2 +#define IT83XX_CPU_INT_IRQ_115 2 +#define IT83XX_CPU_INT_IRQ_116 2 +#define IT83XX_CPU_INT_IRQ_117 2 +#define IT83XX_CPU_INT_IRQ_118 2 +#define IT83XX_CPU_INT_IRQ_119 2 +#define IT83XX_CPU_INT_IRQ_120 2 +#define IT83XX_CPU_INT_IRQ_121 2 +#define IT83XX_CPU_INT_IRQ_122 2 +#define IT83XX_CPU_INT_IRQ_123 2 +#define IT83XX_CPU_INT_IRQ_124 2 +#define IT83XX_CPU_INT_IRQ_125 2 +#define IT83XX_CPU_INT_IRQ_126 2 +#define IT83XX_CPU_INT_IRQ_127 2 +#define IT83XX_CPU_INT_IRQ_128 2 +#define IT83XX_CPU_INT_IRQ_129 2 +#define IT83XX_CPU_INT_IRQ_130 2 +#define IT83XX_CPU_INT_IRQ_131 2 +#define IT83XX_CPU_INT_IRQ_132 2 +#define IT83XX_CPU_INT_IRQ_133 2 +#define IT83XX_CPU_INT_IRQ_134 2 +#define IT83XX_CPU_INT_IRQ_135 2 +#define IT83XX_CPU_INT_IRQ_136 2 +#define IT83XX_CPU_INT_IRQ_137 2 +#define IT83XX_CPU_INT_IRQ_138 2 +#define IT83XX_CPU_INT_IRQ_139 2 +#define IT83XX_CPU_INT_IRQ_140 2 +#define IT83XX_CPU_INT_IRQ_141 2 +#define IT83XX_CPU_INT_IRQ_142 2 +#define IT83XX_CPU_INT_IRQ_143 2 +#define IT83XX_CPU_INT_IRQ_144 2 +#define IT83XX_CPU_INT_IRQ_145 2 +#define IT83XX_CPU_INT_IRQ_146 2 +#define IT83XX_CPU_INT_IRQ_147 2 +#define IT83XX_CPU_INT_IRQ_149 4 +#define IT83XX_CPU_INT_IRQ_150 4 +#define IT83XX_CPU_INT_IRQ_151 7 +#define IT83XX_CPU_INT_IRQ_152 6 +#define IT83XX_CPU_INT_IRQ_153 6 +#define IT83XX_CPU_INT_IRQ_154 12 +#define IT83XX_CPU_INT_IRQ_155 3 +#define IT83XX_CPU_INT_IRQ_156 3 +#define IT83XX_CPU_INT_IRQ_157 3 +#define IT83XX_CPU_INT_IRQ_158 3 +#define IT83XX_CPU_INT_IRQ_159 3 +#define IT83XX_CPU_INT_IRQ_160 12 +#define IT83XX_CPU_INT_IRQ_161 12 +#define IT83XX_CPU_INT_IRQ_162 12 +#define IT83XX_CPU_INT_IRQ_163 12 +#define IT83XX_CPU_INT_IRQ_164 12 +#define IT83XX_CPU_INT_IRQ_165 12 +#define IT83XX_CPU_INT_IRQ_166 12 +#define IT83XX_CPU_INT_IRQ_167 12 +#define IT83XX_CPU_INT_IRQ_168 2 +#define IT83XX_CPU_INT_IRQ_169 2 #if defined(CHIP_FAMILY_IT8320) -#define IT83XX_CPU_INT_IRQ_170 2 -#define IT83XX_CPU_INT_IRQ_171 2 -#define IT83XX_CPU_INT_IRQ_172 2 -#define IT83XX_CPU_INT_IRQ_173 2 -#define IT83XX_CPU_INT_IRQ_174 2 -#define IT83XX_CPU_INT_IRQ_175 2 +#define IT83XX_CPU_INT_IRQ_170 2 +#define IT83XX_CPU_INT_IRQ_171 2 +#define IT83XX_CPU_INT_IRQ_172 2 +#define IT83XX_CPU_INT_IRQ_173 2 +#define IT83XX_CPU_INT_IRQ_174 2 +#define IT83XX_CPU_INT_IRQ_175 2 #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) -#define IT83XX_CPU_INT_IRQ_170 12 -#define IT83XX_CPU_INT_IRQ_171 12 -#define IT83XX_CPU_INT_IRQ_172 12 -#define IT83XX_CPU_INT_IRQ_173 12 -#define IT83XX_CPU_INT_IRQ_174 12 -#define IT83XX_CPU_INT_IRQ_175 12 +#define IT83XX_CPU_INT_IRQ_170 12 +#define IT83XX_CPU_INT_IRQ_171 12 +#define IT83XX_CPU_INT_IRQ_172 12 +#define IT83XX_CPU_INT_IRQ_173 12 +#define IT83XX_CPU_INT_IRQ_174 12 +#define IT83XX_CPU_INT_IRQ_175 12 #endif -#define IT83XX_CPU_INT_IRQ_176 2 -#define IT83XX_CPU_INT_IRQ_177 2 -#define IT83XX_CPU_INT_IRQ_178 2 -#define IT83XX_CPU_INT_IRQ_179 2 -#define IT83XX_CPU_INT_IRQ_180 2 -#define IT83XX_CPU_INT_IRQ_181 2 -#define IT83XX_CPU_INT_IRQ_182 2 -#define IT83XX_CPU_INT_IRQ_183 2 -#define IT83XX_CPU_INT_IRQ_184 2 -#define IT83XX_CPU_INT_IRQ_185 2 -#define IT83XX_CPU_INT_IRQ_191 2 -#define IT83XX_CPU_INT_IRQ_192 2 -#define IT83XX_CPU_INT_IRQ_193 2 -#define IT83XX_CPU_INT_IRQ_194 2 -#define IT83XX_CPU_INT_IRQ_195 2 -#define IT83XX_CPU_INT_IRQ_196 2 -#define IT83XX_CPU_INT_IRQ_197 2 -#define IT83XX_CPU_INT_IRQ_199 2 -#define IT83XX_CPU_INT_IRQ_200 2 -#define IT83XX_CPU_INT_IRQ_201 2 -#define IT83XX_CPU_INT_IRQ_202 2 -#define IT83XX_CPU_INT_IRQ_203 2 -#define IT83XX_CPU_INT_IRQ_208 2 -#define IT83XX_CPU_INT_IRQ_209 2 -#define IT83XX_CPU_INT_IRQ_210 2 -#define IT83XX_CPU_INT_IRQ_211 2 -#define IT83XX_CPU_INT_IRQ_212 2 -#define IT83XX_CPU_INT_IRQ_213 2 -#define IT83XX_CPU_INT_IRQ_214 2 -#define IT83XX_CPU_INT_IRQ_216 2 -#define IT83XX_CPU_INT_IRQ_217 2 -#define IT83XX_CPU_INT_IRQ_218 2 -#define IT83XX_CPU_INT_IRQ_219 2 -#define IT83XX_CPU_INT_IRQ_220 2 -#define IT83XX_CPU_INT_IRQ_221 2 -#define IT83XX_CPU_INT_IRQ_224 2 -#define IT83XX_CPU_INT_IRQ_225 2 -#define IT83XX_CPU_INT_IRQ_226 2 -#define IT83XX_CPU_INT_IRQ_227 2 -#define IT83XX_CPU_INT_IRQ_228 2 -#define IT83XX_CPU_INT_IRQ_229 2 +#define IT83XX_CPU_INT_IRQ_176 2 +#define IT83XX_CPU_INT_IRQ_177 2 +#define IT83XX_CPU_INT_IRQ_178 2 +#define IT83XX_CPU_INT_IRQ_179 2 +#define IT83XX_CPU_INT_IRQ_180 2 +#define IT83XX_CPU_INT_IRQ_181 2 +#define IT83XX_CPU_INT_IRQ_182 2 +#define IT83XX_CPU_INT_IRQ_183 2 +#define IT83XX_CPU_INT_IRQ_184 2 +#define IT83XX_CPU_INT_IRQ_185 2 +#define IT83XX_CPU_INT_IRQ_191 2 +#define IT83XX_CPU_INT_IRQ_192 2 +#define IT83XX_CPU_INT_IRQ_193 2 +#define IT83XX_CPU_INT_IRQ_194 2 +#define IT83XX_CPU_INT_IRQ_195 2 +#define IT83XX_CPU_INT_IRQ_196 2 +#define IT83XX_CPU_INT_IRQ_197 2 +#define IT83XX_CPU_INT_IRQ_199 2 +#define IT83XX_CPU_INT_IRQ_200 2 +#define IT83XX_CPU_INT_IRQ_201 2 +#define IT83XX_CPU_INT_IRQ_202 2 +#define IT83XX_CPU_INT_IRQ_203 2 +#define IT83XX_CPU_INT_IRQ_208 2 +#define IT83XX_CPU_INT_IRQ_209 2 +#define IT83XX_CPU_INT_IRQ_210 2 +#define IT83XX_CPU_INT_IRQ_211 2 +#define IT83XX_CPU_INT_IRQ_212 2 +#define IT83XX_CPU_INT_IRQ_213 2 +#define IT83XX_CPU_INT_IRQ_214 2 +#define IT83XX_CPU_INT_IRQ_216 2 +#define IT83XX_CPU_INT_IRQ_217 2 +#define IT83XX_CPU_INT_IRQ_218 2 +#define IT83XX_CPU_INT_IRQ_219 2 +#define IT83XX_CPU_INT_IRQ_220 2 +#define IT83XX_CPU_INT_IRQ_221 2 +#define IT83XX_CPU_INT_IRQ_224 2 +#define IT83XX_CPU_INT_IRQ_225 2 +#define IT83XX_CPU_INT_IRQ_226 2 +#define IT83XX_CPU_INT_IRQ_227 2 +#define IT83XX_CPU_INT_IRQ_228 2 +#define IT83XX_CPU_INT_IRQ_229 2 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */ -#define CPU_INT_2_ALL_GPIOS 255 -#define IT83XX_CPU_INT_IRQ_255 2 +#define CPU_INT_2_ALL_GPIOS 255 +#define IT83XX_CPU_INT_IRQ_255 2 -#define CPU_INT_GROUP_5 254 -#define IT83XX_CPU_INT_IRQ_254 5 +#define CPU_INT_GROUP_5 254 +#define IT83XX_CPU_INT_IRQ_254 5 -#define CPU_INT_GROUP_4 252 -#define IT83XX_CPU_INT_IRQ_252 4 +#define CPU_INT_GROUP_4 252 +#define IT83XX_CPU_INT_IRQ_252 4 -#define CPU_INT_GROUP_12 253 -#define IT83XX_CPU_INT_IRQ_253 12 +#define CPU_INT_GROUP_12 253 +#define IT83XX_CPU_INT_IRQ_253 12 -#define CPU_INT_GROUP_3 251 -#define IT83XX_CPU_INT_IRQ_251 3 +#define CPU_INT_GROUP_3 251 +#define IT83XX_CPU_INT_IRQ_251 3 -#define CPU_INT_GROUP_6 250 -#define IT83XX_CPU_INT_IRQ_250 6 +#define CPU_INT_GROUP_6 250 +#define IT83XX_CPU_INT_IRQ_250 6 -#define CPU_INT_GROUP_9 249 -#define IT83XX_CPU_INT_IRQ_249 9 +#define CPU_INT_GROUP_9 249 +#define IT83XX_CPU_INT_IRQ_249 9 -#define CPU_INT_GROUP_7 248 -#define IT83XX_CPU_INT_IRQ_248 7 +#define CPU_INT_GROUP_7 248 +#define IT83XX_CPU_INT_IRQ_248 7 #define CPU_INT(irq) CONCAT2(IT83XX_CPU_INT_IRQ_, irq) /* --- INTC --- */ -#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE - -#define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE+(n)) - -#define IT83XX_INTC_AIVCT REG8(IT83XX_INTC_BASE+0x10) - -#define IT83XX_INTC_IER0 REG8(IT83XX_INTC_BASE+0x04) -#define IT83XX_INTC_IER1 REG8(IT83XX_INTC_BASE+0x05) -#define IT83XX_INTC_IER2 REG8(IT83XX_INTC_BASE+0x06) -#define IT83XX_INTC_IER3 REG8(IT83XX_INTC_BASE+0x07) -#define IT83XX_INTC_IER4 REG8(IT83XX_INTC_BASE+0x15) -#define IT83XX_INTC_IER5 REG8(IT83XX_INTC_BASE+0x19) -#define IT83XX_INTC_IER6 REG8(IT83XX_INTC_BASE+0x1d) -#define IT83XX_INTC_IER7 REG8(IT83XX_INTC_BASE+0x21) -#define IT83XX_INTC_IER8 REG8(IT83XX_INTC_BASE+0x25) -#define IT83XX_INTC_IER9 REG8(IT83XX_INTC_BASE+0x29) -#define IT83XX_INTC_IER10 REG8(IT83XX_INTC_BASE+0x2d) -#define IT83XX_INTC_IER11 REG8(IT83XX_INTC_BASE+0x31) -#define IT83XX_INTC_IER12 REG8(IT83XX_INTC_BASE+0x35) -#define IT83XX_INTC_IER13 REG8(IT83XX_INTC_BASE+0x39) -#define IT83XX_INTC_IER14 REG8(IT83XX_INTC_BASE+0x3d) -#define IT83XX_INTC_IER15 REG8(IT83XX_INTC_BASE+0x41) -#define IT83XX_INTC_IER16 REG8(IT83XX_INTC_BASE+0x45) -#define IT83XX_INTC_IER17 REG8(IT83XX_INTC_BASE+0x49) -#define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE+0x4d) -#define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE+0x51) -#define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE+0x55) -#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE+0x59) -#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE+0x5d) -#define IT83XX_INTC_IER23 REG8(IT83XX_INTC_BASE+0x91) -#define IT83XX_INTC_IER24 REG8(IT83XX_INTC_BASE+0x95) -#define IT83XX_INTC_IER25 REG8(IT83XX_INTC_BASE+0x99) -#define IT83XX_INTC_IER26 REG8(IT83XX_INTC_BASE+0x9d) -#define IT83XX_INTC_IER27 REG8(IT83XX_INTC_BASE+0xa1) -#define IT83XX_INTC_IER28 REG8(IT83XX_INTC_BASE+0xa5) - -#define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE+0x00) -#define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE+0x01) -#define IT83XX_INTC_ISR2 REG8(IT83XX_INTC_BASE+0x02) -#define IT83XX_INTC_ISR3 REG8(IT83XX_INTC_BASE+0x03) -#define IT83XX_INTC_ISR4 REG8(IT83XX_INTC_BASE+0x14) -#define IT83XX_INTC_ISR5 REG8(IT83XX_INTC_BASE+0x18) -#define IT83XX_INTC_ISR6 REG8(IT83XX_INTC_BASE+0x1c) -#define IT83XX_INTC_ISR7 REG8(IT83XX_INTC_BASE+0x20) -#define IT83XX_INTC_ISR8 REG8(IT83XX_INTC_BASE+0x24) -#define IT83XX_INTC_ISR9 REG8(IT83XX_INTC_BASE+0x28) -#define IT83XX_INTC_ISR10 REG8(IT83XX_INTC_BASE+0x2c) -#define IT83XX_INTC_ISR11 REG8(IT83XX_INTC_BASE+0x30) -#define IT83XX_INTC_ISR12 REG8(IT83XX_INTC_BASE+0x34) -#define IT83XX_INTC_ISR13 REG8(IT83XX_INTC_BASE+0x38) -#define IT83XX_INTC_ISR14 REG8(IT83XX_INTC_BASE+0x3c) -#define IT83XX_INTC_ISR15 REG8(IT83XX_INTC_BASE+0x40) -#define IT83XX_INTC_ISR16 REG8(IT83XX_INTC_BASE+0x44) -#define IT83XX_INTC_ISR17 REG8(IT83XX_INTC_BASE+0x48) -#define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE+0x4c) -#define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE+0x50) -#define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE+0x54) -#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE+0x58) -#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE+0x5c) -#define IT83XX_INTC_ISR23 REG8(IT83XX_INTC_BASE+0x90) -#define IT83XX_INTC_ISR24 REG8(IT83XX_INTC_BASE+0x94) -#define IT83XX_INTC_ISR25 REG8(IT83XX_INTC_BASE+0x98) -#define IT83XX_INTC_ISR26 REG8(IT83XX_INTC_BASE+0x9c) -#define IT83XX_INTC_ISR27 REG8(IT83XX_INTC_BASE+0xa0) -#define IT83XX_INTC_ISR28 REG8(IT83XX_INTC_BASE+0xa4) - -#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E) -#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F) -#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52) -#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53) +#define IT83XX_INTC_BASE CHIP_EC_INTC_BASE + +#define IT83XX_INTC_REG(n) REG8(IT83XX_INTC_BASE + (n)) + +#define IT83XX_INTC_AIVCT REG8(IT83XX_INTC_BASE + 0x10) + +#define IT83XX_INTC_IER0 REG8(IT83XX_INTC_BASE + 0x04) +#define IT83XX_INTC_IER1 REG8(IT83XX_INTC_BASE + 0x05) +#define IT83XX_INTC_IER2 REG8(IT83XX_INTC_BASE + 0x06) +#define IT83XX_INTC_IER3 REG8(IT83XX_INTC_BASE + 0x07) +#define IT83XX_INTC_IER4 REG8(IT83XX_INTC_BASE + 0x15) +#define IT83XX_INTC_IER5 REG8(IT83XX_INTC_BASE + 0x19) +#define IT83XX_INTC_IER6 REG8(IT83XX_INTC_BASE + 0x1d) +#define IT83XX_INTC_IER7 REG8(IT83XX_INTC_BASE + 0x21) +#define IT83XX_INTC_IER8 REG8(IT83XX_INTC_BASE + 0x25) +#define IT83XX_INTC_IER9 REG8(IT83XX_INTC_BASE + 0x29) +#define IT83XX_INTC_IER10 REG8(IT83XX_INTC_BASE + 0x2d) +#define IT83XX_INTC_IER11 REG8(IT83XX_INTC_BASE + 0x31) +#define IT83XX_INTC_IER12 REG8(IT83XX_INTC_BASE + 0x35) +#define IT83XX_INTC_IER13 REG8(IT83XX_INTC_BASE + 0x39) +#define IT83XX_INTC_IER14 REG8(IT83XX_INTC_BASE + 0x3d) +#define IT83XX_INTC_IER15 REG8(IT83XX_INTC_BASE + 0x41) +#define IT83XX_INTC_IER16 REG8(IT83XX_INTC_BASE + 0x45) +#define IT83XX_INTC_IER17 REG8(IT83XX_INTC_BASE + 0x49) +#define IT83XX_INTC_IER18 REG8(IT83XX_INTC_BASE + 0x4d) +#define IT83XX_INTC_IER19 REG8(IT83XX_INTC_BASE + 0x51) +#define IT83XX_INTC_IER20 REG8(IT83XX_INTC_BASE + 0x55) +#define IT83XX_INTC_IER21 REG8(IT83XX_INTC_BASE + 0x59) +#define IT83XX_INTC_IER22 REG8(IT83XX_INTC_BASE + 0x5d) +#define IT83XX_INTC_IER23 REG8(IT83XX_INTC_BASE + 0x91) +#define IT83XX_INTC_IER24 REG8(IT83XX_INTC_BASE + 0x95) +#define IT83XX_INTC_IER25 REG8(IT83XX_INTC_BASE + 0x99) +#define IT83XX_INTC_IER26 REG8(IT83XX_INTC_BASE + 0x9d) +#define IT83XX_INTC_IER27 REG8(IT83XX_INTC_BASE + 0xa1) +#define IT83XX_INTC_IER28 REG8(IT83XX_INTC_BASE + 0xa5) + +#define IT83XX_INTC_ISR0 REG8(IT83XX_INTC_BASE + 0x00) +#define IT83XX_INTC_ISR1 REG8(IT83XX_INTC_BASE + 0x01) +#define IT83XX_INTC_ISR2 REG8(IT83XX_INTC_BASE + 0x02) +#define IT83XX_INTC_ISR3 REG8(IT83XX_INTC_BASE + 0x03) +#define IT83XX_INTC_ISR4 REG8(IT83XX_INTC_BASE + 0x14) +#define IT83XX_INTC_ISR5 REG8(IT83XX_INTC_BASE + 0x18) +#define IT83XX_INTC_ISR6 REG8(IT83XX_INTC_BASE + 0x1c) +#define IT83XX_INTC_ISR7 REG8(IT83XX_INTC_BASE + 0x20) +#define IT83XX_INTC_ISR8 REG8(IT83XX_INTC_BASE + 0x24) +#define IT83XX_INTC_ISR9 REG8(IT83XX_INTC_BASE + 0x28) +#define IT83XX_INTC_ISR10 REG8(IT83XX_INTC_BASE + 0x2c) +#define IT83XX_INTC_ISR11 REG8(IT83XX_INTC_BASE + 0x30) +#define IT83XX_INTC_ISR12 REG8(IT83XX_INTC_BASE + 0x34) +#define IT83XX_INTC_ISR13 REG8(IT83XX_INTC_BASE + 0x38) +#define IT83XX_INTC_ISR14 REG8(IT83XX_INTC_BASE + 0x3c) +#define IT83XX_INTC_ISR15 REG8(IT83XX_INTC_BASE + 0x40) +#define IT83XX_INTC_ISR16 REG8(IT83XX_INTC_BASE + 0x44) +#define IT83XX_INTC_ISR17 REG8(IT83XX_INTC_BASE + 0x48) +#define IT83XX_INTC_ISR18 REG8(IT83XX_INTC_BASE + 0x4c) +#define IT83XX_INTC_ISR19 REG8(IT83XX_INTC_BASE + 0x50) +#define IT83XX_INTC_ISR20 REG8(IT83XX_INTC_BASE + 0x54) +#define IT83XX_INTC_ISR21 REG8(IT83XX_INTC_BASE + 0x58) +#define IT83XX_INTC_ISR22 REG8(IT83XX_INTC_BASE + 0x5c) +#define IT83XX_INTC_ISR23 REG8(IT83XX_INTC_BASE + 0x90) +#define IT83XX_INTC_ISR24 REG8(IT83XX_INTC_BASE + 0x94) +#define IT83XX_INTC_ISR25 REG8(IT83XX_INTC_BASE + 0x98) +#define IT83XX_INTC_ISR26 REG8(IT83XX_INTC_BASE + 0x9c) +#define IT83XX_INTC_ISR27 REG8(IT83XX_INTC_BASE + 0xa0) +#define IT83XX_INTC_ISR28 REG8(IT83XX_INTC_BASE + 0xa4) + +#define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE + 0x2E) +#define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE + 0x2F) +#define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE + 0x52) +#define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE + 0x53) #define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n)) -#define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE+0x80+(i)) +#define IT83XX_INTC_IVCT(i) REG8(IT83XX_INTC_BASE + 0x80 + (i)) /* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */ -#define IT83XX_EC2I_BASE 0x00F01200 +#define IT83XX_EC2I_BASE 0x00F01200 -#define IT83XX_EC2I_IHIOA REG8(IT83XX_EC2I_BASE+0x00) -#define IT83XX_EC2I_IHD REG8(IT83XX_EC2I_BASE+0x01) -#define IT83XX_EC2I_LSIOHA REG8(IT83XX_EC2I_BASE+0x02) -#define IT83XX_EC2I_SIOLV REG8(IT83XX_EC2I_BASE+0x03) -#define IT83XX_EC2I_IBMAE REG8(IT83XX_EC2I_BASE+0x04) -#define IT83XX_EC2I_IBCTL REG8(IT83XX_EC2I_BASE+0x05) +#define IT83XX_EC2I_IHIOA REG8(IT83XX_EC2I_BASE + 0x00) +#define IT83XX_EC2I_IHD REG8(IT83XX_EC2I_BASE + 0x01) +#define IT83XX_EC2I_LSIOHA REG8(IT83XX_EC2I_BASE + 0x02) +#define IT83XX_EC2I_SIOLV REG8(IT83XX_EC2I_BASE + 0x03) +#define IT83XX_EC2I_IBMAE REG8(IT83XX_EC2I_BASE + 0x04) +#define IT83XX_EC2I_IBCTL REG8(IT83XX_EC2I_BASE + 0x05) /* --- System Wake-UP Control (SWUC) --- */ -#define IT83XX_SWUC_BASE 0x00F01400 -#define IT83XX_SWUC_SWCTL1 REG8(IT83XX_SWUC_BASE+0x00) +#define IT83XX_SWUC_BASE 0x00F01400 +#define IT83XX_SWUC_SWCTL1 REG8(IT83XX_SWUC_BASE + 0x00) /* --- Wake-Up Control (WUC) --- */ -#define IT83XX_WUC_BASE 0x00F01B00 +#define IT83XX_WUC_BASE 0x00F01B00 -#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE+0x00) -#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c) -#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04) -#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d) -#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c) -#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f) +#define IT83XX_WUC_WUEMR1 (IT83XX_WUC_BASE + 0x00) +#define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE + 0x0c) +#define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE + 0x04) +#define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE + 0x0d) +#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE + 0x3c) +#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE + 0x0f) -#define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE+0x21) -#define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE+0x25) +#define IT83XX_WUC_WUESR10 REG8(IT83XX_WUC_BASE + 0x21) +#define IT83XX_WUC_WUESR11 REG8(IT83XX_WUC_BASE + 0x25) -#define IT83XX_WUC_WUEMR3 REG8(IT83XX_WUC_BASE+0x02) -#define IT83XX_WUC_WUESR3 REG8(IT83XX_WUC_BASE+0x06) -#define IT83XX_WUC_WUENR3 REG8(IT83XX_WUC_BASE+0x0A) +#define IT83XX_WUC_WUEMR3 REG8(IT83XX_WUC_BASE + 0x02) +#define IT83XX_WUC_WUESR3 REG8(IT83XX_WUC_BASE + 0x06) +#define IT83XX_WUC_WUENR3 REG8(IT83XX_WUC_BASE + 0x0A) -#define IT83XX_WUC_WUEMR4 REG8(IT83XX_WUC_BASE+0x03) -#define IT83XX_WUC_WUESR4 REG8(IT83XX_WUC_BASE+0x07) -#define IT83XX_WUC_WUENR4 REG8(IT83XX_WUC_BASE+0x0B) +#define IT83XX_WUC_WUEMR4 REG8(IT83XX_WUC_BASE + 0x03) +#define IT83XX_WUC_WUESR4 REG8(IT83XX_WUC_BASE + 0x07) +#define IT83XX_WUC_WUENR4 REG8(IT83XX_WUC_BASE + 0x0B) /* --- UART --- */ #define IT83XX_UART0_BASE 0x00F02700 #define IT83XX_UART1_BASE 0x00F02800 -#define IT83XX_UART_BASE(n) CONCAT3(IT83XX_UART, n, _BASE) +#define IT83XX_UART_BASE(n) CONCAT3(IT83XX_UART, n, _BASE) #define IT83XX_UART_REG(n, offset) REG8(IT83XX_UART_BASE(n) + (offset)) -#define IT83XX_UART_DLL(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_DLM(n) IT83XX_UART_REG(n, 0x01) -#define IT83XX_UART_RBR(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_THR(n) IT83XX_UART_REG(n, 0x00) -#define IT83XX_UART_IER(n) IT83XX_UART_REG(n, 0x01) -#define IT83XX_UART_IIR(n) IT83XX_UART_REG(n, 0x02) -#define IT83XX_UART_FCR(n) IT83XX_UART_REG(n, 0x02) -#define IT83XX_UART_LCR(n) IT83XX_UART_REG(n, 0x03) -#define IT83XX_UART_MCR(n) IT83XX_UART_REG(n, 0x04) -#define IT83XX_UART_LSR(n) IT83XX_UART_REG(n, 0x05) -#define IT83XX_UART_MSR(n) IT83XX_UART_REG(n, 0x06) -#define IT83XX_UART_SCR(n) IT83XX_UART_REG(n, 0x07) -#define IT83XX_UART_ECSMPR(n) IT83XX_UART_REG(n, 0x08) -#define IT83XX_UART_CSSR(n) IT83XX_UART_REG(n, 0x09) +#define IT83XX_UART_DLL(n) IT83XX_UART_REG(n, 0x00) +#define IT83XX_UART_DLM(n) IT83XX_UART_REG(n, 0x01) +#define IT83XX_UART_RBR(n) IT83XX_UART_REG(n, 0x00) +#define IT83XX_UART_THR(n) IT83XX_UART_REG(n, 0x00) +#define IT83XX_UART_IER(n) IT83XX_UART_REG(n, 0x01) +#define IT83XX_UART_IIR(n) IT83XX_UART_REG(n, 0x02) +#define IT83XX_UART_FCR(n) IT83XX_UART_REG(n, 0x02) +#define IT83XX_UART_LCR(n) IT83XX_UART_REG(n, 0x03) +#define IT83XX_UART_MCR(n) IT83XX_UART_REG(n, 0x04) +#define IT83XX_UART_LSR(n) IT83XX_UART_REG(n, 0x05) +#define IT83XX_UART_MSR(n) IT83XX_UART_REG(n, 0x06) +#define IT83XX_UART_SCR(n) IT83XX_UART_REG(n, 0x07) +#define IT83XX_UART_ECSMPR(n) IT83XX_UART_REG(n, 0x08) +#define IT83XX_UART_CSSR(n) IT83XX_UART_REG(n, 0x09) /* --- GPIO --- */ -#define IT83XX_GPIO_BASE 0x00F01600 +#define IT83XX_GPIO_BASE 0x00F01600 #define IT83XX_GPIO2_BASE 0x00F03E00 -#define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE+0x00) -#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1 -#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2 +#define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE + 0x00) +#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1 +#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2 #define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3 -#define IT83XX_GPIO_GCR_LPC_RST_POS 1 - -#define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE+0x01) -#define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE+0x02) -#define IT83XX_GPIO_GPDRC REG8(IT83XX_GPIO_BASE+0x03) -#define IT83XX_GPIO_GPDRE REG8(IT83XX_GPIO_BASE+0x05) -#define IT83XX_GPIO_GPDRF REG8(IT83XX_GPIO_BASE+0x06) -#define IT83XX_GPIO_GPDRH REG8(IT83XX_GPIO_BASE+0x08) - -#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE+0x10) -#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE+0x11) -#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE+0x12) -#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE+0x13) -#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE+0x14) -#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE+0x15) -#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE+0x16) -#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE+0x17) - -#define IT83XX_GPIO_GPCRB0 REG8(IT83XX_GPIO_BASE+0x18) -#define IT83XX_GPIO_GPCRB1 REG8(IT83XX_GPIO_BASE+0x19) -#define IT83XX_GPIO_GPCRB2 REG8(IT83XX_GPIO_BASE+0x1A) -#define IT83XX_GPIO_GPCRB3 REG8(IT83XX_GPIO_BASE+0x1B) -#define IT83XX_GPIO_GPCRB4 REG8(IT83XX_GPIO_BASE+0x1C) -#define IT83XX_GPIO_GPCRB5 REG8(IT83XX_GPIO_BASE+0x1D) -#define IT83XX_GPIO_GPCRB6 REG8(IT83XX_GPIO_BASE+0x1E) -#define IT83XX_GPIO_GPCRB7 REG8(IT83XX_GPIO_BASE+0x1F) - -#define IT83XX_GPIO_GPCRC0 REG8(IT83XX_GPIO_BASE+0x20) -#define IT83XX_GPIO_GPCRC1 REG8(IT83XX_GPIO_BASE+0x21) -#define IT83XX_GPIO_GPCRC2 REG8(IT83XX_GPIO_BASE+0x22) -#define IT83XX_GPIO_GPCRC3 REG8(IT83XX_GPIO_BASE+0x23) -#define IT83XX_GPIO_GPCRC4 REG8(IT83XX_GPIO_BASE+0x24) -#define IT83XX_GPIO_GPCRC5 REG8(IT83XX_GPIO_BASE+0x25) -#define IT83XX_GPIO_GPCRC6 REG8(IT83XX_GPIO_BASE+0x26) -#define IT83XX_GPIO_GPCRC7 REG8(IT83XX_GPIO_BASE+0x27) - -#define IT83XX_GPIO_GPCRE0 REG8(IT83XX_GPIO_BASE+0x30) -#define IT83XX_GPIO_GPCRE1 REG8(IT83XX_GPIO_BASE+0x31) -#define IT83XX_GPIO_GPCRE2 REG8(IT83XX_GPIO_BASE+0x32) -#define IT83XX_GPIO_GPCRE3 REG8(IT83XX_GPIO_BASE+0x33) -#define IT83XX_GPIO_GPCRE4 REG8(IT83XX_GPIO_BASE+0x34) -#define IT83XX_GPIO_GPCRE5 REG8(IT83XX_GPIO_BASE+0x35) -#define IT83XX_GPIO_GPCRE6 REG8(IT83XX_GPIO_BASE+0x36) -#define IT83XX_GPIO_GPCRE7 REG8(IT83XX_GPIO_BASE+0x37) - -#define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE+0x38) -#define IT83XX_GPIO_GPCRF1 REG8(IT83XX_GPIO_BASE+0x39) -#define IT83XX_GPIO_GPCRF2 REG8(IT83XX_GPIO_BASE+0x3A) -#define IT83XX_GPIO_GPCRF3 REG8(IT83XX_GPIO_BASE+0x3B) -#define IT83XX_GPIO_GPCRF4 REG8(IT83XX_GPIO_BASE+0x3C) -#define IT83XX_GPIO_GPCRF5 REG8(IT83XX_GPIO_BASE+0x3D) -#define IT83XX_GPIO_GPCRF6 REG8(IT83XX_GPIO_BASE+0x3E) -#define IT83XX_GPIO_GPCRF7 REG8(IT83XX_GPIO_BASE+0x3F) - -#define IT83XX_GPIO_GPCRH0 REG8(IT83XX_GPIO_BASE+0x48) -#define IT83XX_GPIO_GPCRH1 REG8(IT83XX_GPIO_BASE+0x49) -#define IT83XX_GPIO_GPCRH2 REG8(IT83XX_GPIO_BASE+0x4A) -#define IT83XX_GPIO_GPCRH3 REG8(IT83XX_GPIO_BASE+0x4B) -#define IT83XX_GPIO_GPCRH4 REG8(IT83XX_GPIO_BASE+0x4C) -#define IT83XX_GPIO_GPCRH5 REG8(IT83XX_GPIO_BASE+0x4D) -#define IT83XX_GPIO_GPCRH6 REG8(IT83XX_GPIO_BASE+0x4E) -#define IT83XX_GPIO_GPCRH7 REG8(IT83XX_GPIO_BASE+0x4F) - -#define IT83XX_GPIO_GPCRI0 REG8(IT83XX_GPIO_BASE+0x50) -#define IT83XX_GPIO_GPCRI1 REG8(IT83XX_GPIO_BASE+0x51) -#define IT83XX_GPIO_GPCRI2 REG8(IT83XX_GPIO_BASE+0x52) -#define IT83XX_GPIO_GPCRI3 REG8(IT83XX_GPIO_BASE+0x53) -#define IT83XX_GPIO_GPCRI4 REG8(IT83XX_GPIO_BASE+0x54) -#define IT83XX_GPIO_GPCRI5 REG8(IT83XX_GPIO_BASE+0x55) -#define IT83XX_GPIO_GPCRI6 REG8(IT83XX_GPIO_BASE+0x56) -#define IT83XX_GPIO_GPCRI7 REG8(IT83XX_GPIO_BASE+0x57) - -#define IT83XX_GPIO_GPCRM5 REG8(IT83XX_GPIO_BASE+0xA5) - -#define IT83XX_GPIO_GPDMRA REG8(IT83XX_GPIO_BASE+0x61) -#define IT83XX_GPIO_GPDMRB REG8(IT83XX_GPIO_BASE+0x62) -#define IT83XX_GPIO_GPDMRC REG8(IT83XX_GPIO_BASE+0x63) -#define IT83XX_GPIO_GPDMRE REG8(IT83XX_GPIO_BASE+0x65) -#define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE+0x66) -#define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE+0x68) - -#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE+0x98) -#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE+0x99) -#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE+0x9A) -#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE+0x9B) -#define IT83XX_GPIO_GPCRP0 REG8(IT83XX_GPIO2_BASE+0x18) -#define IT83XX_GPIO_GPCRP1 REG8(IT83XX_GPIO2_BASE+0x19) - -#define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE+0xF0) -#define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE+0xF1) -#define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE+0xF2) -#define IT83XX_GPIO_GRC4 REG8(IT83XX_GPIO_BASE+0xF3) -#define IT83XX_GPIO_GRC5 REG8(IT83XX_GPIO_BASE+0xF4) -#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE+0xF5) -#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE+0xF6) -#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE+0xF7) -#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE+0xE4) -#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE+0xE5) -#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE+0xE6) -#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE+0xE7) -#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE+0xE8) -#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE+0xE9) -#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE+0xD1) -#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE+0xD2) -#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE+0xD3) -#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE+0xD4) -#define IT83XX_GPIO_GCR29 REG8(IT83XX_GPIO_BASE+0xEE) -#define IT83XX_GPIO_GCR30 REG8(IT83XX_GPIO_BASE+0xED) -#define IT83XX_GPIO_GCR31 REG8(IT83XX_GPIO_BASE+0xD5) -#define IT83XX_GPIO_GCR32 REG8(IT83XX_GPIO_BASE+0xD6) -#define IT83XX_GPIO_GCR33 REG8(IT83XX_GPIO_BASE+0xD7) - -#define IT83XX_VBATPC_BGPOPSCR REG8(IT83XX_GPIO2_BASE+0xF0) -#define IT83XX_VBATPC_XLPIER REG8(IT83XX_GPIO2_BASE+0xF5) +#define IT83XX_GPIO_GCR_LPC_RST_POS 1 + +#define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE + 0x01) +#define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE + 0x02) +#define IT83XX_GPIO_GPDRC REG8(IT83XX_GPIO_BASE + 0x03) +#define IT83XX_GPIO_GPDRE REG8(IT83XX_GPIO_BASE + 0x05) +#define IT83XX_GPIO_GPDRF REG8(IT83XX_GPIO_BASE + 0x06) +#define IT83XX_GPIO_GPDRH REG8(IT83XX_GPIO_BASE + 0x08) + +#define IT83XX_GPIO_GPCRA0 REG8(IT83XX_GPIO_BASE + 0x10) +#define IT83XX_GPIO_GPCRA1 REG8(IT83XX_GPIO_BASE + 0x11) +#define IT83XX_GPIO_GPCRA2 REG8(IT83XX_GPIO_BASE + 0x12) +#define IT83XX_GPIO_GPCRA3 REG8(IT83XX_GPIO_BASE + 0x13) +#define IT83XX_GPIO_GPCRA4 REG8(IT83XX_GPIO_BASE + 0x14) +#define IT83XX_GPIO_GPCRA5 REG8(IT83XX_GPIO_BASE + 0x15) +#define IT83XX_GPIO_GPCRA6 REG8(IT83XX_GPIO_BASE + 0x16) +#define IT83XX_GPIO_GPCRA7 REG8(IT83XX_GPIO_BASE + 0x17) + +#define IT83XX_GPIO_GPCRB0 REG8(IT83XX_GPIO_BASE + 0x18) +#define IT83XX_GPIO_GPCRB1 REG8(IT83XX_GPIO_BASE + 0x19) +#define IT83XX_GPIO_GPCRB2 REG8(IT83XX_GPIO_BASE + 0x1A) +#define IT83XX_GPIO_GPCRB3 REG8(IT83XX_GPIO_BASE + 0x1B) +#define IT83XX_GPIO_GPCRB4 REG8(IT83XX_GPIO_BASE + 0x1C) +#define IT83XX_GPIO_GPCRB5 REG8(IT83XX_GPIO_BASE + 0x1D) +#define IT83XX_GPIO_GPCRB6 REG8(IT83XX_GPIO_BASE + 0x1E) +#define IT83XX_GPIO_GPCRB7 REG8(IT83XX_GPIO_BASE + 0x1F) + +#define IT83XX_GPIO_GPCRC0 REG8(IT83XX_GPIO_BASE + 0x20) +#define IT83XX_GPIO_GPCRC1 REG8(IT83XX_GPIO_BASE + 0x21) +#define IT83XX_GPIO_GPCRC2 REG8(IT83XX_GPIO_BASE + 0x22) +#define IT83XX_GPIO_GPCRC3 REG8(IT83XX_GPIO_BASE + 0x23) +#define IT83XX_GPIO_GPCRC4 REG8(IT83XX_GPIO_BASE + 0x24) +#define IT83XX_GPIO_GPCRC5 REG8(IT83XX_GPIO_BASE + 0x25) +#define IT83XX_GPIO_GPCRC6 REG8(IT83XX_GPIO_BASE + 0x26) +#define IT83XX_GPIO_GPCRC7 REG8(IT83XX_GPIO_BASE + 0x27) + +#define IT83XX_GPIO_GPCRE0 REG8(IT83XX_GPIO_BASE + 0x30) +#define IT83XX_GPIO_GPCRE1 REG8(IT83XX_GPIO_BASE + 0x31) +#define IT83XX_GPIO_GPCRE2 REG8(IT83XX_GPIO_BASE + 0x32) +#define IT83XX_GPIO_GPCRE3 REG8(IT83XX_GPIO_BASE + 0x33) +#define IT83XX_GPIO_GPCRE4 REG8(IT83XX_GPIO_BASE + 0x34) +#define IT83XX_GPIO_GPCRE5 REG8(IT83XX_GPIO_BASE + 0x35) +#define IT83XX_GPIO_GPCRE6 REG8(IT83XX_GPIO_BASE + 0x36) +#define IT83XX_GPIO_GPCRE7 REG8(IT83XX_GPIO_BASE + 0x37) + +#define IT83XX_GPIO_GPCRF0 REG8(IT83XX_GPIO_BASE + 0x38) +#define IT83XX_GPIO_GPCRF1 REG8(IT83XX_GPIO_BASE + 0x39) +#define IT83XX_GPIO_GPCRF2 REG8(IT83XX_GPIO_BASE + 0x3A) +#define IT83XX_GPIO_GPCRF3 REG8(IT83XX_GPIO_BASE + 0x3B) +#define IT83XX_GPIO_GPCRF4 REG8(IT83XX_GPIO_BASE + 0x3C) +#define IT83XX_GPIO_GPCRF5 REG8(IT83XX_GPIO_BASE + 0x3D) +#define IT83XX_GPIO_GPCRF6 REG8(IT83XX_GPIO_BASE + 0x3E) +#define IT83XX_GPIO_GPCRF7 REG8(IT83XX_GPIO_BASE + 0x3F) + +#define IT83XX_GPIO_GPCRH0 REG8(IT83XX_GPIO_BASE + 0x48) +#define IT83XX_GPIO_GPCRH1 REG8(IT83XX_GPIO_BASE + 0x49) +#define IT83XX_GPIO_GPCRH2 REG8(IT83XX_GPIO_BASE + 0x4A) +#define IT83XX_GPIO_GPCRH3 REG8(IT83XX_GPIO_BASE + 0x4B) +#define IT83XX_GPIO_GPCRH4 REG8(IT83XX_GPIO_BASE + 0x4C) +#define IT83XX_GPIO_GPCRH5 REG8(IT83XX_GPIO_BASE + 0x4D) +#define IT83XX_GPIO_GPCRH6 REG8(IT83XX_GPIO_BASE + 0x4E) +#define IT83XX_GPIO_GPCRH7 REG8(IT83XX_GPIO_BASE + 0x4F) + +#define IT83XX_GPIO_GPCRI0 REG8(IT83XX_GPIO_BASE + 0x50) +#define IT83XX_GPIO_GPCRI1 REG8(IT83XX_GPIO_BASE + 0x51) +#define IT83XX_GPIO_GPCRI2 REG8(IT83XX_GPIO_BASE + 0x52) +#define IT83XX_GPIO_GPCRI3 REG8(IT83XX_GPIO_BASE + 0x53) +#define IT83XX_GPIO_GPCRI4 REG8(IT83XX_GPIO_BASE + 0x54) +#define IT83XX_GPIO_GPCRI5 REG8(IT83XX_GPIO_BASE + 0x55) +#define IT83XX_GPIO_GPCRI6 REG8(IT83XX_GPIO_BASE + 0x56) +#define IT83XX_GPIO_GPCRI7 REG8(IT83XX_GPIO_BASE + 0x57) + +#define IT83XX_GPIO_GPCRM5 REG8(IT83XX_GPIO_BASE + 0xA5) + +#define IT83XX_GPIO_GPDMRA REG8(IT83XX_GPIO_BASE + 0x61) +#define IT83XX_GPIO_GPDMRB REG8(IT83XX_GPIO_BASE + 0x62) +#define IT83XX_GPIO_GPDMRC REG8(IT83XX_GPIO_BASE + 0x63) +#define IT83XX_GPIO_GPDMRE REG8(IT83XX_GPIO_BASE + 0x65) +#define IT83XX_GPIO_GPDMRF REG8(IT83XX_GPIO_BASE + 0x66) +#define IT83XX_GPIO_GPDMRH REG8(IT83XX_GPIO_BASE + 0x68) + +#define IT83XX_GPIO_GPCRL0 REG8(IT83XX_GPIO_BASE + 0x98) +#define IT83XX_GPIO_GPCRL1 REG8(IT83XX_GPIO_BASE + 0x99) +#define IT83XX_GPIO_GPCRL2 REG8(IT83XX_GPIO_BASE + 0x9A) +#define IT83XX_GPIO_GPCRL3 REG8(IT83XX_GPIO_BASE + 0x9B) +#define IT83XX_GPIO_GPCRP0 REG8(IT83XX_GPIO2_BASE + 0x18) +#define IT83XX_GPIO_GPCRP1 REG8(IT83XX_GPIO2_BASE + 0x19) + +#define IT83XX_GPIO_GRC1 REG8(IT83XX_GPIO_BASE + 0xF0) +#define IT83XX_GPIO_GRC2 REG8(IT83XX_GPIO_BASE + 0xF1) +#define IT83XX_GPIO_GRC3 REG8(IT83XX_GPIO_BASE + 0xF2) +#define IT83XX_GPIO_GRC4 REG8(IT83XX_GPIO_BASE + 0xF3) +#define IT83XX_GPIO_GRC5 REG8(IT83XX_GPIO_BASE + 0xF4) +#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE + 0xF5) +#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE + 0xF6) +#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE + 0xF7) +#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE + 0xE4) +#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE + 0xE5) +#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE + 0xE6) +#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE + 0xE7) +#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE + 0xE8) +#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE + 0xE9) +#define IT83XX_GPIO_GCR25 REG8(IT83XX_GPIO_BASE + 0xD1) +#define IT83XX_GPIO_GCR26 REG8(IT83XX_GPIO_BASE + 0xD2) +#define IT83XX_GPIO_GCR27 REG8(IT83XX_GPIO_BASE + 0xD3) +#define IT83XX_GPIO_GCR28 REG8(IT83XX_GPIO_BASE + 0xD4) +#define IT83XX_GPIO_GCR29 REG8(IT83XX_GPIO_BASE + 0xEE) +#define IT83XX_GPIO_GCR30 REG8(IT83XX_GPIO_BASE + 0xED) +#define IT83XX_GPIO_GCR31 REG8(IT83XX_GPIO_BASE + 0xD5) +#define IT83XX_GPIO_GCR32 REG8(IT83XX_GPIO_BASE + 0xD6) +#define IT83XX_GPIO_GCR33 REG8(IT83XX_GPIO_BASE + 0xD7) + +#define IT83XX_VBATPC_BGPOPSCR REG8(IT83XX_GPIO2_BASE + 0xF0) +#define IT83XX_VBATPC_XLPIER REG8(IT83XX_GPIO2_BASE + 0xF5) enum { /* GPIO group index */ @@ -839,26 +839,26 @@ struct gpio_reg_t { /* GPIO group index convert to GPIO data/output type/ctrl group address */ static const struct gpio_reg_t gpio_group_to_reg[] = { /* GPDR(set), GPDMR(get), GPOTR, GPCR */ - [GPIO_A] = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 }, - [GPIO_B] = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 }, - [GPIO_C] = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 }, - [GPIO_D] = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 }, - [GPIO_E] = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 }, - [GPIO_F] = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 }, - [GPIO_G] = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 }, - [GPIO_H] = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 }, - [GPIO_I] = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 }, - [GPIO_J] = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 }, - [GPIO_K] = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 }, - [GPIO_L] = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 }, - [GPIO_M] = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 }, + [GPIO_A] = { 0x00F01601, 0x00F01661, 0x00F01671, 0x00F01610 }, + [GPIO_B] = { 0x00F01602, 0x00F01662, 0x00F01672, 0x00F01618 }, + [GPIO_C] = { 0x00F01603, 0x00F01663, 0x00F01673, 0x00F01620 }, + [GPIO_D] = { 0x00F01604, 0x00F01664, 0x00F01674, 0x00F01628 }, + [GPIO_E] = { 0x00F01605, 0x00F01665, 0x00F01675, 0x00F01630 }, + [GPIO_F] = { 0x00F01606, 0x00F01666, 0x00F01676, 0x00F01638 }, + [GPIO_G] = { 0x00F01607, 0x00F01667, 0x00F01677, 0x00F01640 }, + [GPIO_H] = { 0x00F01608, 0x00F01668, 0x00F01678, 0x00F01648 }, + [GPIO_I] = { 0x00F01609, 0x00F01669, 0x00F01679, 0x00F01650 }, + [GPIO_J] = { 0x00F0160A, 0x00F0166A, 0x00F0167A, 0x00F01658 }, + [GPIO_K] = { 0x00F0160B, 0x00F0166B, 0x00F0167B, 0x00F01690 }, + [GPIO_L] = { 0x00F0160C, 0x00F0166C, 0x00F0167C, 0x00F01698 }, + [GPIO_M] = { 0x00F0160D, 0x00F0166D, 0x00F0167D, 0x00F016a0 }, #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [GPIO_O] = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 }, - [GPIO_P] = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 }, - [GPIO_Q] = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 }, - [GPIO_R] = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 }, + [GPIO_O] = { 0x00F03E01, 0x00F03E61, 0x00F03E71, 0x00F03E10 }, + [GPIO_P] = { 0x00F03E02, 0x00F03E62, 0x00F03E72, 0x00F03E18 }, + [GPIO_Q] = { 0x00F03E03, 0x00F03E63, 0x00F03E73, 0x00F03E20 }, + [GPIO_R] = { 0x00F03E04, 0x00F03E64, 0x00F03E74, 0x00F03E28 }, #endif - [GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF }, + [GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, 0xFFFFFFFF }, [GPIO_KSO_H] = { 0x00F01D01, 0x00F01D0C, 0x00F01D27, 0xFFFFFFFF }, [GPIO_KSO_L] = { 0x00F01D00, 0x00F01D0F, 0x00F01D28, 0xFFFFFFFF }, }; @@ -866,43 +866,40 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT)); #define UNIMPLEMENTED_GPIO_BANK GPIO_A -#define IT83XX_GPIO_DATA(port) \ - REG8(gpio_group_to_reg[port].reg_gpdr) -#define IT83XX_GPIO_DATA_MIRROR(port) \ - REG8(gpio_group_to_reg[port].reg_gpdmr) -#define IT83XX_GPIO_GPOT(port) \ - REG8(gpio_group_to_reg[port].reg_gpotr) -#define IT83XX_GPIO_CTRL(port, pin_offset) \ +#define IT83XX_GPIO_DATA(port) REG8(gpio_group_to_reg[port].reg_gpdr) +#define IT83XX_GPIO_DATA_MIRROR(port) REG8(gpio_group_to_reg[port].reg_gpdmr) +#define IT83XX_GPIO_GPOT(port) REG8(gpio_group_to_reg[port].reg_gpotr) +#define IT83XX_GPIO_CTRL(port, pin_offset) \ REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset) -#define GPCR_PORT_PIN_MODE_INPUT BIT(7) -#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) -#define GPCR_PORT_PIN_MODE_PULLUP BIT(2) -#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) +#define GPCR_PORT_PIN_MODE_INPUT BIT(7) +#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6) +#define GPCR_PORT_PIN_MODE_PULLUP BIT(2) +#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1) /* --- Clock and Power Management (ECPM) --- */ -#define IT83XX_ECPM_BASE 0x00F01E00 +#define IT83XX_ECPM_BASE 0x00F01E00 #define IT83XX_ECPM_CGCTRL1R_OFF 0x01 #define IT83XX_ECPM_CGCTRL2R_OFF 0x02 #define IT83XX_ECPM_CGCTRL3R_OFF 0x05 #define IT83XX_ECPM_CGCTRL4R_OFF 0x09 -#define IT83XX_ECPM_PLLCTRL REG8(IT83XX_ECPM_BASE+0x03) +#define IT83XX_ECPM_PLLCTRL REG8(IT83XX_ECPM_BASE + 0x03) enum ec_pll_ctrl { EC_PLL_DOZE = 0, EC_PLL_SLEEP = 1, EC_PLL_DEEP_DOZE = 3, }; -#define IT83XX_ECPM_AUTOCG REG8(IT83XX_ECPM_BASE+0x04) -#define IT83XX_ECPM_PLLFREQR REG8(IT83XX_ECPM_BASE+0x06) -#define IT83XX_ECPM_PLLCSS REG8(IT83XX_ECPM_BASE+0x08) -#define IT83XX_ECPM_SCDCR0 REG8(IT83XX_ECPM_BASE+0x0c) -#define IT83XX_ECPM_SCDCR1 REG8(IT83XX_ECPM_BASE+0x0d) -#define IT83XX_ECPM_SCDCR2 REG8(IT83XX_ECPM_BASE+0x0e) -#define IT83XX_ECPM_SCDCR3 REG8(IT83XX_ECPM_BASE+0x0f) -#define IT83XX_ECPM_SCDCR4 REG8(IT83XX_ECPM_BASE+0x10) +#define IT83XX_ECPM_AUTOCG REG8(IT83XX_ECPM_BASE + 0x04) +#define IT83XX_ECPM_PLLFREQR REG8(IT83XX_ECPM_BASE + 0x06) +#define IT83XX_ECPM_PLLCSS REG8(IT83XX_ECPM_BASE + 0x08) +#define IT83XX_ECPM_SCDCR0 REG8(IT83XX_ECPM_BASE + 0x0c) +#define IT83XX_ECPM_SCDCR1 REG8(IT83XX_ECPM_BASE + 0x0d) +#define IT83XX_ECPM_SCDCR2 REG8(IT83XX_ECPM_BASE + 0x0e) +#define IT83XX_ECPM_SCDCR3 REG8(IT83XX_ECPM_BASE + 0x0f) +#define IT83XX_ECPM_SCDCR4 REG8(IT83XX_ECPM_BASE + 0x10) /* * The clock gate offsets combine the register offset from ECPM_BASE and the @@ -910,528 +907,528 @@ enum ec_pll_ctrl { * clock_enable_peripheral() and clock_disable_peripheral() */ enum clock_gate_offsets { - CGC_OFFSET_EGPC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40), - CGC_OFFSET_CIR = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20), - CGC_OFFSET_SWUC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10), - CGC_OFFSET_USB = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20), - CGC_OFFSET_PECI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08), - CGC_OFFSET_UART = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04), - CGC_OFFSET_SSPI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02), - CGC_OFFSET_DBGR = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01), - CGC_OFFSET_SMBF = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80), - CGC_OFFSET_SMBE = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40), - CGC_OFFSET_SMBD = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20), - CGC_OFFSET_SMBC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10), - CGC_OFFSET_SMBB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08), - CGC_OFFSET_SMBA = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04), - CGC_OFFSET_SMB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02), - CGC_OFFSET_CEC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01) + CGC_OFFSET_EGPC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x40), + CGC_OFFSET_CIR = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x20), + CGC_OFFSET_SWUC = ((IT83XX_ECPM_CGCTRL2R_OFF << 8) | 0x10), + CGC_OFFSET_USB = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x20), + CGC_OFFSET_PECI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x08), + CGC_OFFSET_UART = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x04), + CGC_OFFSET_SSPI = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x02), + CGC_OFFSET_DBGR = ((IT83XX_ECPM_CGCTRL3R_OFF << 8) | 0x01), + CGC_OFFSET_SMBF = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x80), + CGC_OFFSET_SMBE = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x40), + CGC_OFFSET_SMBD = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x20), + CGC_OFFSET_SMBC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x10), + CGC_OFFSET_SMBB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08), + CGC_OFFSET_SMBA = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04), + CGC_OFFSET_SMB = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x02), + CGC_OFFSET_CEC = ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x01) }; /* --- Timer (TMR) --- */ -#define IT83XX_TMR_BASE 0x00F02900 - -#define IT83XX_TMR_PRSC REG8(IT83XX_TMR_BASE+0x00) -#define IT83XX_TMR_GCSMS REG8(IT83XX_TMR_BASE+0x01) -#define IT83XX_TMR_CTR_A0 REG8(IT83XX_TMR_BASE+0x02) -#define IT83XX_TMR_CTR_A1 REG8(IT83XX_TMR_BASE+0x03) -#define IT83XX_TMR_CTR_B0 REG8(IT83XX_TMR_BASE+0x04) -#define IT83XX_TMR_CTR_B1 REG8(IT83XX_TMR_BASE+0x05) -#define IT83XX_TMR_DCR_A0 REG8(IT83XX_TMR_BASE+0x06) -#define IT83XX_TMR_DCR_A1 REG8(IT83XX_TMR_BASE+0x07) -#define IT83XX_TMR_DCR_B0 REG8(IT83XX_TMR_BASE+0x08) -#define IT83XX_TMR_DCR_B1 REG8(IT83XX_TMR_BASE+0x09) -#define IT83XX_TMR_CCGSR REG8(IT83XX_TMR_BASE+0x0A) -#define IT83XX_TMR_TMRCE REG8(IT83XX_TMR_BASE+0x0B) -#define IT83XX_TMR_TMRIE REG8(IT83XX_TMR_BASE+0x0C) +#define IT83XX_TMR_BASE 0x00F02900 + +#define IT83XX_TMR_PRSC REG8(IT83XX_TMR_BASE + 0x00) +#define IT83XX_TMR_GCSMS REG8(IT83XX_TMR_BASE + 0x01) +#define IT83XX_TMR_CTR_A0 REG8(IT83XX_TMR_BASE + 0x02) +#define IT83XX_TMR_CTR_A1 REG8(IT83XX_TMR_BASE + 0x03) +#define IT83XX_TMR_CTR_B0 REG8(IT83XX_TMR_BASE + 0x04) +#define IT83XX_TMR_CTR_B1 REG8(IT83XX_TMR_BASE + 0x05) +#define IT83XX_TMR_DCR_A0 REG8(IT83XX_TMR_BASE + 0x06) +#define IT83XX_TMR_DCR_A1 REG8(IT83XX_TMR_BASE + 0x07) +#define IT83XX_TMR_DCR_B0 REG8(IT83XX_TMR_BASE + 0x08) +#define IT83XX_TMR_DCR_B1 REG8(IT83XX_TMR_BASE + 0x09) +#define IT83XX_TMR_CCGSR REG8(IT83XX_TMR_BASE + 0x0A) +#define IT83XX_TMR_TMRCE REG8(IT83XX_TMR_BASE + 0x0B) +#define IT83XX_TMR_TMRIE REG8(IT83XX_TMR_BASE + 0x0C) /* --- External Timer and Watchdog (ETWD) --- */ -#define IT83XX_ETWD_BASE 0x00F01F00 - -#define IT83XX_ETWD_ETWCFG REG8(IT83XX_ETWD_BASE+0x01) -#define IT83XX_ETWD_ET1PSR REG8(IT83XX_ETWD_BASE+0x02) -#define IT83XX_ETWD_ET1CNTLHR REG8(IT83XX_ETWD_BASE+0x03) -#define IT83XX_ETWD_ET1CNTLLR REG8(IT83XX_ETWD_BASE+0x04) -#define IT83XX_ETWD_ETWCTRL REG8(IT83XX_ETWD_BASE+0x05) -#define IT83XX_ETWD_EWDCNTLLR REG8(IT83XX_ETWD_BASE+0x06) -#define IT83XX_ETWD_EWDKEYR REG8(IT83XX_ETWD_BASE+0x07) -#define IT83XX_ETWD_EWDCNTLHR REG8(IT83XX_ETWD_BASE+0x09) -#define IT83XX_ETWD_ETXCTRL(n) REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3)) -#define IT83XX_ETWD_ETXPSR(n) REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3)) -#define IT83XX_ETWD_ETXCNTLR(n) REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3)) -#define IT83XX_ETWD_ETXCNTOR(n) REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2)) +#define IT83XX_ETWD_BASE 0x00F01F00 + +#define IT83XX_ETWD_ETWCFG REG8(IT83XX_ETWD_BASE + 0x01) +#define IT83XX_ETWD_ET1PSR REG8(IT83XX_ETWD_BASE + 0x02) +#define IT83XX_ETWD_ET1CNTLHR REG8(IT83XX_ETWD_BASE + 0x03) +#define IT83XX_ETWD_ET1CNTLLR REG8(IT83XX_ETWD_BASE + 0x04) +#define IT83XX_ETWD_ETWCTRL REG8(IT83XX_ETWD_BASE + 0x05) +#define IT83XX_ETWD_EWDCNTLLR REG8(IT83XX_ETWD_BASE + 0x06) +#define IT83XX_ETWD_EWDKEYR REG8(IT83XX_ETWD_BASE + 0x07) +#define IT83XX_ETWD_EWDCNTLHR REG8(IT83XX_ETWD_BASE + 0x09) +#define IT83XX_ETWD_ETXCTRL(n) REG8(IT83XX_ETWD_BASE + 0x10 + (n << 3)) +#define IT83XX_ETWD_ETXPSR(n) REG8(IT83XX_ETWD_BASE + 0x11 + (n << 3)) +#define IT83XX_ETWD_ETXCNTLR(n) REG32(IT83XX_ETWD_BASE + 0x14 + (n << 3)) +#define IT83XX_ETWD_ETXCNTOR(n) REG32(IT83XX_ETWD_BASE + 0x48 + (n << 2)) /* --- General Control (GCTRL) --- */ #define IT83XX_GCTRL_BASE 0x00F02000 #ifdef IT83XX_CHIP_ID_3BYTES -#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x85) -#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x86) -#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE+0x87) +#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x85) +#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x86) +#define IT83XX_GCTRL_CHIPID3 REG8(IT83XX_GCTRL_BASE + 0x87) #else -#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE+0x00) -#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE+0x01) +#define IT83XX_GCTRL_CHIPID1 REG8(IT83XX_GCTRL_BASE + 0x00) +#define IT83XX_GCTRL_CHIPID2 REG8(IT83XX_GCTRL_BASE + 0x01) #endif -#define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE+0x02) -#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE+0x03) -#define IT83XX_SMB_DBGR BIT(0) -#define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE+0x0B) -#define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE+0x06) -#define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE+0x0A) -#define IT83XX_GCTRL_SPCTRL1 REG8(IT83XX_GCTRL_BASE+0x0D) -#define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE+0x10) -#define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE+0x11) -#define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE+0x1C) -#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE+0x20) -#define IT83XX_GCTRL_SPISLVPFE BIT(6) -#define IT83XX_GCTRL_RSTC5 REG8(IT83XX_GCTRL_BASE+0x21) -#define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE+0x30) -#define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE+0x32) -#define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE+0x33) -#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37) -#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41) -#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) -#define IT83XX_GCTRL_PIN_MUX0 REG8(IT83XX_GCTRL_BASE+0x46) -#define IT83XX_DLM14_ENABLE BIT(5) -#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) -#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) -#define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE+0x4C) -#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE+0x53) +#define IT83XX_GCTRL_CHIPVER REG8(IT83XX_GCTRL_BASE + 0x02) +#define IT83XX_GCTRL_DBGROS REG8(IT83XX_GCTRL_BASE + 0x03) +#define IT83XX_SMB_DBGR BIT(0) +#define IT83XX_GCTRL_WNCKR REG8(IT83XX_GCTRL_BASE + 0x0B) +#define IT83XX_GCTRL_RSTS REG8(IT83XX_GCTRL_BASE + 0x06) +#define IT83XX_GCTRL_BADRSEL REG8(IT83XX_GCTRL_BASE + 0x0A) +#define IT83XX_GCTRL_SPCTRL1 REG8(IT83XX_GCTRL_BASE + 0x0D) +#define IT83XX_GCTRL_RSTDMMC REG8(IT83XX_GCTRL_BASE + 0x10) +#define IT83XX_GCTRL_RSTC4 REG8(IT83XX_GCTRL_BASE + 0x11) +#define IT83XX_GCTRL_SPCTRL4 REG8(IT83XX_GCTRL_BASE + 0x1C) +#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE + 0x20) +#define IT83XX_GCTRL_SPISLVPFE BIT(6) +#define IT83XX_GCTRL_RSTC5 REG8(IT83XX_GCTRL_BASE + 0x21) +#define IT83XX_GCTRL_MCCR REG8(IT83XX_GCTRL_BASE + 0x30) +#define IT83XX_GCTRL_PMER1 REG8(IT83XX_GCTRL_BASE + 0x32) +#define IT83XX_GCTRL_PMER2 REG8(IT83XX_GCTRL_BASE + 0x33) +#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE + 0x37) +#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE + 0x41) +#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE + 0x44) +#define IT83XX_GCTRL_PIN_MUX0 REG8(IT83XX_GCTRL_BASE + 0x46) +#define IT83XX_DLM14_ENABLE BIT(5) +#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE + 0x4A) +#define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE + 0x4B) +#define IT83XX_GCTRL_WMCR REG8(IT83XX_GCTRL_BASE + 0x4C) +#define IT83XX_GCTRL_H2ROFSR REG8(IT83XX_GCTRL_BASE + 0x53) /* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ -#define ETWD_HW_RST_EN BIT(0) -#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) -#define ILMCR_ILM0_ENABLE BIT(0) -#define ILMCR_ILM2_ENABLE BIT(2) -#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) -#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) -#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i) +#define ETWD_HW_RST_EN BIT(0) +#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE + 0x5D) +#define ILMCR_ILM0_ENABLE BIT(0) +#define ILMCR_ILM2_ENABLE BIT(2) +#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE + 0x60 + i) +#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE + 0xA0 + i) +#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE + 0xC0 + i) /* --- Pulse Width Modulation (PWM) --- */ -#define IT83XX_PWM_BASE 0x00F01800 - -#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE+0x00) -#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE+0x01) -#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE+0x02) -#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE+0x03) -#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE+0x04) -#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE+0x05) -#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE+0x06) -#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE+0x07) -#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE+0x08) -#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE+0x09) -#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE+0x0A) -#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE+0x0B) -#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE+0x0C) -#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE+0x0D) -#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE+0x0E) -#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE+0x0F) -#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE+0x10) -#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE+0x1E) -#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE+0x1F) -#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE+0x20) -#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE+0x21) -#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE+0x22) -#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE+0x23) -#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE+0x24) -#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE+0x27) -#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE+0x28) -#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE+0x2B) -#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE+0x2C) -#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE+0x2D) -#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE+0x2E) -#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE+0x40) -#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE+0x41) -#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE+0x42) -#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE+0x43) -#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE+0x44) -#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE+0x45) -#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE+0x46) -#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE+0x47) -#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE+0x48) -#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE+0x49) +#define IT83XX_PWM_BASE 0x00F01800 + +#define IT83XX_PWM_C0CPRS REG8(IT83XX_PWM_BASE + 0x00) +#define IT83XX_PWM_CTR REG8(IT83XX_PWM_BASE + 0x01) +#define IT83XX_PWM_DCR0 REG8(IT83XX_PWM_BASE + 0x02) +#define IT83XX_PWM_DCR1 REG8(IT83XX_PWM_BASE + 0x03) +#define IT83XX_PWM_DCR2 REG8(IT83XX_PWM_BASE + 0x04) +#define IT83XX_PWM_DCR3 REG8(IT83XX_PWM_BASE + 0x05) +#define IT83XX_PWM_DCR4 REG8(IT83XX_PWM_BASE + 0x06) +#define IT83XX_PWM_DCR5 REG8(IT83XX_PWM_BASE + 0x07) +#define IT83XX_PWM_DCR6 REG8(IT83XX_PWM_BASE + 0x08) +#define IT83XX_PWM_DCR7 REG8(IT83XX_PWM_BASE + 0x09) +#define IT83XX_PWM_PWMPOL REG8(IT83XX_PWM_BASE + 0x0A) +#define IT83XX_PWM_PCFSR REG8(IT83XX_PWM_BASE + 0x0B) +#define IT83XX_PWM_PCSSGL REG8(IT83XX_PWM_BASE + 0x0C) +#define IT83XX_PWM_PCSSGH REG8(IT83XX_PWM_BASE + 0x0D) +#define IT83XX_PWM_CR256PCSSG REG8(IT83XX_PWM_BASE + 0x0E) +#define IT83XX_PWM_PCSGR REG8(IT83XX_PWM_BASE + 0x0F) +#define IT83XX_PWM_CTR1M REG8(IT83XX_PWM_BASE + 0x10) +#define IT83XX_PWM_F1TLRR REG8(IT83XX_PWM_BASE + 0x1E) +#define IT83XX_PWM_F1TMRR REG8(IT83XX_PWM_BASE + 0x1F) +#define IT83XX_PWM_F2TLRR REG8(IT83XX_PWM_BASE + 0x20) +#define IT83XX_PWM_F2TMRR REG8(IT83XX_PWM_BASE + 0x21) +#define IT83XX_PWM_ZINTSCR REG8(IT83XX_PWM_BASE + 0x22) +#define IT83XX_PWM_ZTIER REG8(IT83XX_PWM_BASE + 0x23) +#define IT83XX_PWM_TSWCTLR REG8(IT83XX_PWM_BASE + 0x24) +#define IT83XX_PWM_C4CPRS REG8(IT83XX_PWM_BASE + 0x27) +#define IT83XX_PWM_C4MCPRS REG8(IT83XX_PWM_BASE + 0x28) +#define IT83XX_PWM_C6CPRS REG8(IT83XX_PWM_BASE + 0x2B) +#define IT83XX_PWM_C6MCPRS REG8(IT83XX_PWM_BASE + 0x2C) +#define IT83XX_PWM_C7CPRS REG8(IT83XX_PWM_BASE + 0x2D) +#define IT83XX_PWM_C7MCPRS REG8(IT83XX_PWM_BASE + 0x2E) +#define IT83XX_PWM_CLK6MSEL REG8(IT83XX_PWM_BASE + 0x40) +#define IT83XX_PWM_CTR1 REG8(IT83XX_PWM_BASE + 0x41) +#define IT83XX_PWM_CTR2 REG8(IT83XX_PWM_BASE + 0x42) +#define IT83XX_PWM_CTR3 REG8(IT83XX_PWM_BASE + 0x43) +#define IT83XX_PWM_PWM5TOCTRL REG8(IT83XX_PWM_BASE + 0x44) +#define IT83XX_PWM_CFLRR REG8(IT83XX_PWM_BASE + 0x45) +#define IT83XX_PWM_CFMRR REG8(IT83XX_PWM_BASE + 0x46) +#define IT83XX_PWM_CFINTCTRL REG8(IT83XX_PWM_BASE + 0x47) +#define IT83XX_PWM_TSWCTRL REG8(IT83XX_PWM_BASE + 0x48) +#define IT83XX_PWM_PWMODENR REG8(IT83XX_PWM_BASE + 0x49) /* Analog to Digital Converter (ADC) */ -#define IT83XX_ADC_BASE 0x00F01900 - -#define IT83XX_ADC_ADCSTS REG8(IT83XX_ADC_BASE+0x00) -#define IT83XX_ADC_ADCCFG REG8(IT83XX_ADC_BASE+0x01) -#define IT83XX_ADC_ADCCTL REG8(IT83XX_ADC_BASE+0x02) -#define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE+0x03) -#define IT83XX_ADC_DBKEN BIT(7) /* ADC data buffer keep enable. */ -#define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE+0x04) -#define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE+0x05) -#define IT83XX_ADC_AHCE BIT(7) -#define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE+0x06) -#define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE+0x07) -#define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE+0x08) -#define IT83XX_ADC_VCH2CTL REG8(IT83XX_ADC_BASE+0x09) -#define IT83XX_ADC_VCH2DATL REG8(IT83XX_ADC_BASE+0x0A) -#define IT83XX_ADC_VCH2DATM REG8(IT83XX_ADC_BASE+0x0B) -#define IT83XX_ADC_VCH3CTL REG8(IT83XX_ADC_BASE+0x0C) -#define IT83XX_ADC_VCH3DATL REG8(IT83XX_ADC_BASE+0x0D) -#define IT83XX_ADC_VCH3DATM REG8(IT83XX_ADC_BASE+0x0E) -#define IT83XX_ADC_VHSCDBL REG8(IT83XX_ADC_BASE+0x14) -#define IT83XX_ADC_VHSCDBM REG8(IT83XX_ADC_BASE+0x15) -#define IT83XX_ADC_VCH0DATL REG8(IT83XX_ADC_BASE+0x18) -#define IT83XX_ADC_VCH0DATM REG8(IT83XX_ADC_BASE+0x19) -#define IT83XX_ADC_VHSGCDBL REG8(IT83XX_ADC_BASE+0x1C) -#define IT83XX_ADC_VHSGCDBM REG8(IT83XX_ADC_BASE+0x1D) -#define IT83XX_ADC_ADCSAR REG8(IT83XX_ADC_BASE+0x32) -#define IT83XX_ADC_VCMPSCP REG8(IT83XX_ADC_BASE+0x37) -#define IT83XX_ADC_VCH4CTL REG8(IT83XX_ADC_BASE+0x38) -#define IT83XX_ADC_VCH4DATM REG8(IT83XX_ADC_BASE+0x39) -#define IT83XX_ADC_VCH4DATL REG8(IT83XX_ADC_BASE+0x3A) -#define IT83XX_ADC_VCH5CTL REG8(IT83XX_ADC_BASE+0x3B) -#define IT83XX_ADC_VCH5DATM REG8(IT83XX_ADC_BASE+0x3C) -#define IT83XX_ADC_VCH5DATL REG8(IT83XX_ADC_BASE+0x3D) -#define IT83XX_ADC_VCH6CTL REG8(IT83XX_ADC_BASE+0x3E) -#define IT83XX_ADC_VCH6DATM REG8(IT83XX_ADC_BASE+0x3F) -#define IT83XX_ADC_VCH6DATL REG8(IT83XX_ADC_BASE+0x40) -#define IT83XX_ADC_VCH7CTL REG8(IT83XX_ADC_BASE+0x41) -#define IT83XX_ADC_VCH7DATM REG8(IT83XX_ADC_BASE+0x42) -#define IT83XX_ADC_VCH7DATL REG8(IT83XX_ADC_BASE+0x43) -#define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE+0x44) -#define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE+0x45) -#define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE+0x46) -#define ADC_VCMP_CMPEN BIT(7) -#define ADC_VCMP_CMPINTEN BIT(6) -#define ADC_VCMP_GREATER_THRESHOLD BIT(5) -#define ADC_VCMP_EDGE_TRIGGER BIT(4) -#define ADC_VCMP_GPIO_ACTIVE_LOW BIT(3) -#define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE+0x47) -#define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE+0x48) -#define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE+0x49) -#define IT83XX_ADC_CMP1THRDATM REG8(IT83XX_ADC_BASE+0x4A) -#define IT83XX_ADC_CMP1THRDATL REG8(IT83XX_ADC_BASE+0x4B) -#define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE+0x4C) -#define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE+0x4D) -#define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE+0x4E) -#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE+0x60) -#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE+0x61) -#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE+0x62) -#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE+0x63) -#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE+0x64) -#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE+0x65) -#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE+0x66) -#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE+0x67) -#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE+0x68) -#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE+0x69) -#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE+0x6A) -#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE+0x6B) -#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE+0x6C) -#define IT83XX_ADC_VCMPSTS2 REG8(IT83XX_ADC_BASE+0x6D) -#define IT83XX_ADC_VCMP3CTL REG8(IT83XX_ADC_BASE+0x6E) -#define IT83XX_ADC_CMP3THRDATM REG8(IT83XX_ADC_BASE+0x6F) -#define IT83XX_ADC_CMP3THRDATL REG8(IT83XX_ADC_BASE+0x70) -#define IT83XX_ADC_VCMP4CTL REG8(IT83XX_ADC_BASE+0x71) -#define IT83XX_ADC_CMP4THRDATM REG8(IT83XX_ADC_BASE+0x72) -#define IT83XX_ADC_CMP4THRDATL REG8(IT83XX_ADC_BASE+0x73) -#define IT83XX_ADC_VCMP5CTL REG8(IT83XX_ADC_BASE+0x74) -#define IT83XX_ADC_CMP5THRDATM REG8(IT83XX_ADC_BASE+0x75) -#define IT83XX_ADC_CMP5THRDATL REG8(IT83XX_ADC_BASE+0x76) -#define IT83XX_ADC_VCMP0CSELM REG8(IT83XX_ADC_BASE+0x77) -#define ADC_VCMP_VCMPCSELM BIT(0) -#define IT83XX_ADC_VCMP1CSELM REG8(IT83XX_ADC_BASE+0x78) -#define IT83XX_ADC_VCMP2CSELM REG8(IT83XX_ADC_BASE+0x79) -#define IT83XX_ADC_VCMP3CSELM REG8(IT83XX_ADC_BASE+0x7A) -#define IT83XX_ADC_VCMP4CSELM REG8(IT83XX_ADC_BASE+0x7B) -#define IT83XX_ADC_VCMP5CSELM REG8(IT83XX_ADC_BASE+0x7C) +#define IT83XX_ADC_BASE 0x00F01900 + +#define IT83XX_ADC_ADCSTS REG8(IT83XX_ADC_BASE + 0x00) +#define IT83XX_ADC_ADCCFG REG8(IT83XX_ADC_BASE + 0x01) +#define IT83XX_ADC_ADCCTL REG8(IT83XX_ADC_BASE + 0x02) +#define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE + 0x03) +#define IT83XX_ADC_DBKEN BIT(7) /* ADC data buffer keep enable. */ +#define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE + 0x04) +#define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE + 0x05) +#define IT83XX_ADC_AHCE BIT(7) +#define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE + 0x06) +#define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE + 0x07) +#define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE + 0x08) +#define IT83XX_ADC_VCH2CTL REG8(IT83XX_ADC_BASE + 0x09) +#define IT83XX_ADC_VCH2DATL REG8(IT83XX_ADC_BASE + 0x0A) +#define IT83XX_ADC_VCH2DATM REG8(IT83XX_ADC_BASE + 0x0B) +#define IT83XX_ADC_VCH3CTL REG8(IT83XX_ADC_BASE + 0x0C) +#define IT83XX_ADC_VCH3DATL REG8(IT83XX_ADC_BASE + 0x0D) +#define IT83XX_ADC_VCH3DATM REG8(IT83XX_ADC_BASE + 0x0E) +#define IT83XX_ADC_VHSCDBL REG8(IT83XX_ADC_BASE + 0x14) +#define IT83XX_ADC_VHSCDBM REG8(IT83XX_ADC_BASE + 0x15) +#define IT83XX_ADC_VCH0DATL REG8(IT83XX_ADC_BASE + 0x18) +#define IT83XX_ADC_VCH0DATM REG8(IT83XX_ADC_BASE + 0x19) +#define IT83XX_ADC_VHSGCDBL REG8(IT83XX_ADC_BASE + 0x1C) +#define IT83XX_ADC_VHSGCDBM REG8(IT83XX_ADC_BASE + 0x1D) +#define IT83XX_ADC_ADCSAR REG8(IT83XX_ADC_BASE + 0x32) +#define IT83XX_ADC_VCMPSCP REG8(IT83XX_ADC_BASE + 0x37) +#define IT83XX_ADC_VCH4CTL REG8(IT83XX_ADC_BASE + 0x38) +#define IT83XX_ADC_VCH4DATM REG8(IT83XX_ADC_BASE + 0x39) +#define IT83XX_ADC_VCH4DATL REG8(IT83XX_ADC_BASE + 0x3A) +#define IT83XX_ADC_VCH5CTL REG8(IT83XX_ADC_BASE + 0x3B) +#define IT83XX_ADC_VCH5DATM REG8(IT83XX_ADC_BASE + 0x3C) +#define IT83XX_ADC_VCH5DATL REG8(IT83XX_ADC_BASE + 0x3D) +#define IT83XX_ADC_VCH6CTL REG8(IT83XX_ADC_BASE + 0x3E) +#define IT83XX_ADC_VCH6DATM REG8(IT83XX_ADC_BASE + 0x3F) +#define IT83XX_ADC_VCH6DATL REG8(IT83XX_ADC_BASE + 0x40) +#define IT83XX_ADC_VCH7CTL REG8(IT83XX_ADC_BASE + 0x41) +#define IT83XX_ADC_VCH7DATM REG8(IT83XX_ADC_BASE + 0x42) +#define IT83XX_ADC_VCH7DATL REG8(IT83XX_ADC_BASE + 0x43) +#define IT83XX_ADC_ADCDVSTS REG8(IT83XX_ADC_BASE + 0x44) +#define IT83XX_ADC_VCMPSTS REG8(IT83XX_ADC_BASE + 0x45) +#define IT83XX_ADC_VCMP0CTL REG8(IT83XX_ADC_BASE + 0x46) +#define ADC_VCMP_CMPEN BIT(7) +#define ADC_VCMP_CMPINTEN BIT(6) +#define ADC_VCMP_GREATER_THRESHOLD BIT(5) +#define ADC_VCMP_EDGE_TRIGGER BIT(4) +#define ADC_VCMP_GPIO_ACTIVE_LOW BIT(3) +#define IT83XX_ADC_CMP0THRDATM REG8(IT83XX_ADC_BASE + 0x47) +#define IT83XX_ADC_CMP0THRDATL REG8(IT83XX_ADC_BASE + 0x48) +#define IT83XX_ADC_VCMP1CTL REG8(IT83XX_ADC_BASE + 0x49) +#define IT83XX_ADC_CMP1THRDATM REG8(IT83XX_ADC_BASE + 0x4A) +#define IT83XX_ADC_CMP1THRDATL REG8(IT83XX_ADC_BASE + 0x4B) +#define IT83XX_ADC_VCMP2CTL REG8(IT83XX_ADC_BASE + 0x4C) +#define IT83XX_ADC_CMP2THRDATM REG8(IT83XX_ADC_BASE + 0x4D) +#define IT83XX_ADC_CMP2THRDATL REG8(IT83XX_ADC_BASE + 0x4E) +#define IT83XX_ADC_VCH13CTL REG8(IT83XX_ADC_BASE + 0x60) +#define IT83XX_ADC_VCH13DATM REG8(IT83XX_ADC_BASE + 0x61) +#define IT83XX_ADC_VCH13DATL REG8(IT83XX_ADC_BASE + 0x62) +#define IT83XX_ADC_VCH14CTL REG8(IT83XX_ADC_BASE + 0x63) +#define IT83XX_ADC_VCH14DATM REG8(IT83XX_ADC_BASE + 0x64) +#define IT83XX_ADC_VCH14DATL REG8(IT83XX_ADC_BASE + 0x65) +#define IT83XX_ADC_VCH15CTL REG8(IT83XX_ADC_BASE + 0x66) +#define IT83XX_ADC_VCH15DATM REG8(IT83XX_ADC_BASE + 0x67) +#define IT83XX_ADC_VCH15DATL REG8(IT83XX_ADC_BASE + 0x68) +#define IT83XX_ADC_VCH16CTL REG8(IT83XX_ADC_BASE + 0x69) +#define IT83XX_ADC_VCH16DATM REG8(IT83XX_ADC_BASE + 0x6A) +#define IT83XX_ADC_VCH16DATL REG8(IT83XX_ADC_BASE + 0x6B) +#define IT83XX_ADC_ADCDVSTS2 REG8(IT83XX_ADC_BASE + 0x6C) +#define IT83XX_ADC_VCMPSTS2 REG8(IT83XX_ADC_BASE + 0x6D) +#define IT83XX_ADC_VCMP3CTL REG8(IT83XX_ADC_BASE + 0x6E) +#define IT83XX_ADC_CMP3THRDATM REG8(IT83XX_ADC_BASE + 0x6F) +#define IT83XX_ADC_CMP3THRDATL REG8(IT83XX_ADC_BASE + 0x70) +#define IT83XX_ADC_VCMP4CTL REG8(IT83XX_ADC_BASE + 0x71) +#define IT83XX_ADC_CMP4THRDATM REG8(IT83XX_ADC_BASE + 0x72) +#define IT83XX_ADC_CMP4THRDATL REG8(IT83XX_ADC_BASE + 0x73) +#define IT83XX_ADC_VCMP5CTL REG8(IT83XX_ADC_BASE + 0x74) +#define IT83XX_ADC_CMP5THRDATM REG8(IT83XX_ADC_BASE + 0x75) +#define IT83XX_ADC_CMP5THRDATL REG8(IT83XX_ADC_BASE + 0x76) +#define IT83XX_ADC_VCMP0CSELM REG8(IT83XX_ADC_BASE + 0x77) +#define ADC_VCMP_VCMPCSELM BIT(0) +#define IT83XX_ADC_VCMP1CSELM REG8(IT83XX_ADC_BASE + 0x78) +#define IT83XX_ADC_VCMP2CSELM REG8(IT83XX_ADC_BASE + 0x79) +#define IT83XX_ADC_VCMP3CSELM REG8(IT83XX_ADC_BASE + 0x7A) +#define IT83XX_ADC_VCMP4CSELM REG8(IT83XX_ADC_BASE + 0x7B) +#define IT83XX_ADC_VCMP5CSELM REG8(IT83XX_ADC_BASE + 0x7C) /* Digital to Analog Converter (DAC) */ -#define IT83XX_DAC_BASE 0x00F01A00 +#define IT83XX_DAC_BASE 0x00F01A00 -#define IT83XX_DAC_DACPDREG REG8(IT83XX_DAC_BASE+0x01) -#define IT83XX_DAC_POWDN(ch) BIT(ch) -#define IT83XX_DAC_DACDAT(ch) REG8(IT83XX_DAC_BASE+0x02+ch) +#define IT83XX_DAC_DACPDREG REG8(IT83XX_DAC_BASE + 0x01) +#define IT83XX_DAC_POWDN(ch) BIT(ch) +#define IT83XX_DAC_DACDAT(ch) REG8(IT83XX_DAC_BASE + 0x02 + ch) /* Keyboard Controller (KBC) */ -#define IT83XX_KBC_BASE 0x00F01300 +#define IT83XX_KBC_BASE 0x00F01300 -#define IT83XX_KBC_KBHICR REG8(IT83XX_KBC_BASE+0x00) -#define IT83XX_KBC_KBIRQR REG8(IT83XX_KBC_BASE+0x02) -#define IT83XX_KBC_KBHISR REG8(IT83XX_KBC_BASE+0x04) -#define IT83XX_KBC_KBHIKDOR REG8(IT83XX_KBC_BASE+0x06) -#define IT83XX_KBC_KBHIMDOR REG8(IT83XX_KBC_BASE+0x08) -#define IT83XX_KBC_KBHIDIR REG8(IT83XX_KBC_BASE+0x0A) +#define IT83XX_KBC_KBHICR REG8(IT83XX_KBC_BASE + 0x00) +#define IT83XX_KBC_KBIRQR REG8(IT83XX_KBC_BASE + 0x02) +#define IT83XX_KBC_KBHISR REG8(IT83XX_KBC_BASE + 0x04) +#define IT83XX_KBC_KBHIKDOR REG8(IT83XX_KBC_BASE + 0x06) +#define IT83XX_KBC_KBHIMDOR REG8(IT83XX_KBC_BASE + 0x08) +#define IT83XX_KBC_KBHIDIR REG8(IT83XX_KBC_BASE + 0x0A) /* Power Management Channel (PMC) */ -#define IT83XX_PMC_BASE 0x00F01500 - -#define IT83XX_PMC_PM1STS REG8(IT83XX_PMC_BASE+0x00) -#define IT83XX_PMC_PM1DO REG8(IT83XX_PMC_BASE+0x01) -#define IT83XX_PMC_PM1DOSCI REG8(IT83XX_PMC_BASE+0x02) -#define IT83XX_PMC_PM1DOSMI REG8(IT83XX_PMC_BASE+0x03) -#define IT83XX_PMC_PM1DI REG8(IT83XX_PMC_BASE+0x04) -#define IT83XX_PMC_PM1DISCI REG8(IT83XX_PMC_BASE+0x05) -#define IT83XX_PMC_PM1CTL REG8(IT83XX_PMC_BASE+0x06) -#define IT83XX_PMC_PM1IC REG8(IT83XX_PMC_BASE+0x07) -#define IT83XX_PMC_PM1IE REG8(IT83XX_PMC_BASE+0x08) -#define IT83XX_PMC_PM2STS REG8(IT83XX_PMC_BASE+0x10) -#define IT83XX_PMC_PM2DO REG8(IT83XX_PMC_BASE+0x11) -#define IT83XX_PMC_PM2DOSCI REG8(IT83XX_PMC_BASE+0x12) -#define IT83XX_PMC_PM2DOSMI REG8(IT83XX_PMC_BASE+0x13) -#define IT83XX_PMC_PM2DI REG8(IT83XX_PMC_BASE+0x14) -#define IT83XX_PMC_PM2DISCI REG8(IT83XX_PMC_BASE+0x15) -#define IT83XX_PMC_PM2CTL REG8(IT83XX_PMC_BASE+0x16) -#define IT83XX_PMC_PM2IC REG8(IT83XX_PMC_BASE+0x17) -#define IT83XX_PMC_PM2IE REG8(IT83XX_PMC_BASE+0x18) -#define IT83XX_PMC_PM3STS REG8(IT83XX_PMC_BASE+0x20) -#define IT83XX_PMC_PM3DO REG8(IT83XX_PMC_BASE+0x21) -#define IT83XX_PMC_PM3DI REG8(IT83XX_PMC_BASE+0x22) -#define IT83XX_PMC_PM3CTL REG8(IT83XX_PMC_BASE+0x23) -#define IT83XX_PMC_PM3IC REG8(IT83XX_PMC_BASE+0x24) -#define IT83XX_PMC_PM3IE REG8(IT83XX_PMC_BASE+0x25) -#define IT83XX_PMC_PM4STS REG8(IT83XX_PMC_BASE+0x30) -#define IT83XX_PMC_PM4DO REG8(IT83XX_PMC_BASE+0x31) -#define IT83XX_PMC_PM4DI REG8(IT83XX_PMC_BASE+0x32) -#define IT83XX_PMC_PM4CTL REG8(IT83XX_PMC_BASE+0x33) -#define IT83XX_PMC_PM4IC REG8(IT83XX_PMC_BASE+0x34) -#define IT83XX_PMC_PM4IE REG8(IT83XX_PMC_BASE+0x35) -#define IT83XX_PMC_PM5STS REG8(IT83XX_PMC_BASE+0x40) -#define IT83XX_PMC_PM5DO REG8(IT83XX_PMC_BASE+0x41) -#define IT83XX_PMC_PM5DI REG8(IT83XX_PMC_BASE+0x42) -#define IT83XX_PMC_PM5CTL REG8(IT83XX_PMC_BASE+0x43) -#define IT83XX_PMC_PM5IC REG8(IT83XX_PMC_BASE+0x44) -#define IT83XX_PMC_PM5IE REG8(IT83XX_PMC_BASE+0x45) -#define IT83XX_PMC_MBXCTRL REG8(IT83XX_PMC_BASE+0x19) -#define IT83XX_PMC_MBXEC_00 REG8(IT83XX_PMC_BASE+0xF0) -#define IT83XX_PMC_MBXEC_01 REG8(IT83XX_PMC_BASE+0xF1) -#define IT83XX_PMC_MBXEC_02 REG8(IT83XX_PMC_BASE+0xF2) -#define IT83XX_PMC_MBXEC_03 REG8(IT83XX_PMC_BASE+0xF3) -#define IT83XX_PMC_MBXEC_04 REG8(IT83XX_PMC_BASE+0xF4) -#define IT83XX_PMC_MBXEC_05 REG8(IT83XX_PMC_BASE+0xF5) -#define IT83XX_PMC_MBXEC_06 REG8(IT83XX_PMC_BASE+0xF6) -#define IT83XX_PMC_MBXEC_07 REG8(IT83XX_PMC_BASE+0xF7) -#define IT83XX_PMC_MBXEC_08 REG8(IT83XX_PMC_BASE+0xF8) -#define IT83XX_PMC_MBXEC_09 REG8(IT83XX_PMC_BASE+0xF9) -#define IT83XX_PMC_MBXEC_10 REG8(IT83XX_PMC_BASE+0xFA) -#define IT83XX_PMC_MBXEC_11 REG8(IT83XX_PMC_BASE+0xFB) -#define IT83XX_PMC_MBXEC_12 REG8(IT83XX_PMC_BASE+0xFC) -#define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE+0xFD) -#define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE+0xFE) -#define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE+0xFF) -#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4)) -#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4)) -#define IT83XX_PMC_PMDI(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4)) -#define IT83XX_PMC_PMCTL(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4)) -#define IT83XX_PMC_PMIE(ch) \ -REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) +#define IT83XX_PMC_BASE 0x00F01500 + +#define IT83XX_PMC_PM1STS REG8(IT83XX_PMC_BASE + 0x00) +#define IT83XX_PMC_PM1DO REG8(IT83XX_PMC_BASE + 0x01) +#define IT83XX_PMC_PM1DOSCI REG8(IT83XX_PMC_BASE + 0x02) +#define IT83XX_PMC_PM1DOSMI REG8(IT83XX_PMC_BASE + 0x03) +#define IT83XX_PMC_PM1DI REG8(IT83XX_PMC_BASE + 0x04) +#define IT83XX_PMC_PM1DISCI REG8(IT83XX_PMC_BASE + 0x05) +#define IT83XX_PMC_PM1CTL REG8(IT83XX_PMC_BASE + 0x06) +#define IT83XX_PMC_PM1IC REG8(IT83XX_PMC_BASE + 0x07) +#define IT83XX_PMC_PM1IE REG8(IT83XX_PMC_BASE + 0x08) +#define IT83XX_PMC_PM2STS REG8(IT83XX_PMC_BASE + 0x10) +#define IT83XX_PMC_PM2DO REG8(IT83XX_PMC_BASE + 0x11) +#define IT83XX_PMC_PM2DOSCI REG8(IT83XX_PMC_BASE + 0x12) +#define IT83XX_PMC_PM2DOSMI REG8(IT83XX_PMC_BASE + 0x13) +#define IT83XX_PMC_PM2DI REG8(IT83XX_PMC_BASE + 0x14) +#define IT83XX_PMC_PM2DISCI REG8(IT83XX_PMC_BASE + 0x15) +#define IT83XX_PMC_PM2CTL REG8(IT83XX_PMC_BASE + 0x16) +#define IT83XX_PMC_PM2IC REG8(IT83XX_PMC_BASE + 0x17) +#define IT83XX_PMC_PM2IE REG8(IT83XX_PMC_BASE + 0x18) +#define IT83XX_PMC_PM3STS REG8(IT83XX_PMC_BASE + 0x20) +#define IT83XX_PMC_PM3DO REG8(IT83XX_PMC_BASE + 0x21) +#define IT83XX_PMC_PM3DI REG8(IT83XX_PMC_BASE + 0x22) +#define IT83XX_PMC_PM3CTL REG8(IT83XX_PMC_BASE + 0x23) +#define IT83XX_PMC_PM3IC REG8(IT83XX_PMC_BASE + 0x24) +#define IT83XX_PMC_PM3IE REG8(IT83XX_PMC_BASE + 0x25) +#define IT83XX_PMC_PM4STS REG8(IT83XX_PMC_BASE + 0x30) +#define IT83XX_PMC_PM4DO REG8(IT83XX_PMC_BASE + 0x31) +#define IT83XX_PMC_PM4DI REG8(IT83XX_PMC_BASE + 0x32) +#define IT83XX_PMC_PM4CTL REG8(IT83XX_PMC_BASE + 0x33) +#define IT83XX_PMC_PM4IC REG8(IT83XX_PMC_BASE + 0x34) +#define IT83XX_PMC_PM4IE REG8(IT83XX_PMC_BASE + 0x35) +#define IT83XX_PMC_PM5STS REG8(IT83XX_PMC_BASE + 0x40) +#define IT83XX_PMC_PM5DO REG8(IT83XX_PMC_BASE + 0x41) +#define IT83XX_PMC_PM5DI REG8(IT83XX_PMC_BASE + 0x42) +#define IT83XX_PMC_PM5CTL REG8(IT83XX_PMC_BASE + 0x43) +#define IT83XX_PMC_PM5IC REG8(IT83XX_PMC_BASE + 0x44) +#define IT83XX_PMC_PM5IE REG8(IT83XX_PMC_BASE + 0x45) +#define IT83XX_PMC_MBXCTRL REG8(IT83XX_PMC_BASE + 0x19) +#define IT83XX_PMC_MBXEC_00 REG8(IT83XX_PMC_BASE + 0xF0) +#define IT83XX_PMC_MBXEC_01 REG8(IT83XX_PMC_BASE + 0xF1) +#define IT83XX_PMC_MBXEC_02 REG8(IT83XX_PMC_BASE + 0xF2) +#define IT83XX_PMC_MBXEC_03 REG8(IT83XX_PMC_BASE + 0xF3) +#define IT83XX_PMC_MBXEC_04 REG8(IT83XX_PMC_BASE + 0xF4) +#define IT83XX_PMC_MBXEC_05 REG8(IT83XX_PMC_BASE + 0xF5) +#define IT83XX_PMC_MBXEC_06 REG8(IT83XX_PMC_BASE + 0xF6) +#define IT83XX_PMC_MBXEC_07 REG8(IT83XX_PMC_BASE + 0xF7) +#define IT83XX_PMC_MBXEC_08 REG8(IT83XX_PMC_BASE + 0xF8) +#define IT83XX_PMC_MBXEC_09 REG8(IT83XX_PMC_BASE + 0xF9) +#define IT83XX_PMC_MBXEC_10 REG8(IT83XX_PMC_BASE + 0xFA) +#define IT83XX_PMC_MBXEC_11 REG8(IT83XX_PMC_BASE + 0xFB) +#define IT83XX_PMC_MBXEC_12 REG8(IT83XX_PMC_BASE + 0xFC) +#define IT83XX_PMC_MBXEC_13 REG8(IT83XX_PMC_BASE + 0xFD) +#define IT83XX_PMC_MBXEC_14 REG8(IT83XX_PMC_BASE + 0xFE) +#define IT83XX_PMC_MBXEC_15 REG8(IT83XX_PMC_BASE + 0xFF) +#define IT83XX_PMC_PMSTS(ch) REG8(IT83XX_PMC_BASE + 0x00 + (ch << 4)) +#define IT83XX_PMC_PMDO(ch) REG8(IT83XX_PMC_BASE + 0x01 + (ch << 4)) +#define IT83XX_PMC_PMDI(ch) \ + REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 2 : 4) + (ch << 4)) +#define IT83XX_PMC_PMCTL(ch) \ + REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 3 : 6) + (ch << 4)) +#define IT83XX_PMC_PMIE(ch) \ + REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4)) /* Keyboard Matrix Scan control (KBS) */ -#define IT83XX_KBS_BASE 0x00F01D00 - -#define IT83XX_KBS_KSOL REG8(IT83XX_KBS_BASE+0x00) -#define IT83XX_KBS_KSOH1 REG8(IT83XX_KBS_BASE+0x01) -#define IT83XX_KBS_KSOCTRL REG8(IT83XX_KBS_BASE+0x02) -#define IT83XX_KBS_KSOH2 REG8(IT83XX_KBS_BASE+0x03) -#define IT83XX_KBS_KSI REG8(IT83XX_KBS_BASE+0x04) -#define IT83XX_KBS_KSICTRL REG8(IT83XX_KBS_BASE+0x05) -#define IT83XX_KBS_KSIGCTRL REG8(IT83XX_KBS_BASE+0x06) -#define IT83XX_KBS_KSIGOEN REG8(IT83XX_KBS_BASE+0x07) -#define IT83XX_KBS_KSIGDAT REG8(IT83XX_KBS_BASE+0x08) -#define IT83XX_KBS_KSIGDMRR REG8(IT83XX_KBS_BASE+0x09) -#define IT83XX_KBS_KSOHGCTRL REG8(IT83XX_KBS_BASE+0x0A) -#define IT83XX_KBS_KSOHGOEN REG8(IT83XX_KBS_BASE+0x0B) -#define IT83XX_KBS_KSOHGDMRR REG8(IT83XX_KBS_BASE+0x0C) -#define IT83XX_KBS_KSOLGCTRL REG8(IT83XX_KBS_BASE+0x0D) -#define IT83XX_KBS_KSOLGOEN REG8(IT83XX_KBS_BASE+0x0E) -#define IT83XX_KBS_KSOLGDMRR REG8(IT83XX_KBS_BASE+0x0F) -#define IT83XX_KBS_KSO0LSDR REG8(IT83XX_KBS_BASE+0x10) -#define IT83XX_KBS_KSO1LSDR REG8(IT83XX_KBS_BASE+0x11) -#define IT83XX_KBS_KSO2LSDR REG8(IT83XX_KBS_BASE+0x12) -#define IT83XX_KBS_KSO3LSDR REG8(IT83XX_KBS_BASE+0x13) -#define IT83XX_KBS_KSO4LSDR REG8(IT83XX_KBS_BASE+0x14) -#define IT83XX_KBS_KSO5LSDR REG8(IT83XX_KBS_BASE+0x15) -#define IT83XX_KBS_KSO6LSDR REG8(IT83XX_KBS_BASE+0x16) -#define IT83XX_KBS_KSO7LSDR REG8(IT83XX_KBS_BASE+0x17) -#define IT83XX_KBS_KSO8LSDR REG8(IT83XX_KBS_BASE+0x18) -#define IT83XX_KBS_KSO9LSDR REG8(IT83XX_KBS_BASE+0x19) -#define IT83XX_KBS_KSO10LSDR REG8(IT83XX_KBS_BASE+0x1A) -#define IT83XX_KBS_KSO11LSDR REG8(IT83XX_KBS_BASE+0x1B) -#define IT83XX_KBS_KSO12LSDR REG8(IT83XX_KBS_BASE+0x1C) -#define IT83XX_KBS_KSO13LSDR REG8(IT83XX_KBS_BASE+0x1D) -#define IT83XX_KBS_KSO14LSDR REG8(IT83XX_KBS_BASE+0x1E) -#define IT83XX_KBS_KSO15LSDR REG8(IT83XX_KBS_BASE+0x1F) -#define IT83XX_KBS_KSO16LSDR REG8(IT83XX_KBS_BASE+0x20) -#define IT83XX_KBS_KSO17LSDR REG8(IT83XX_KBS_BASE+0x21) -#define IT83XX_KBS_SDC1R REG8(IT83XX_KBS_BASE+0x22) -#define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE+0x23) -#define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE+0x24) -#define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE+0x25) -#define IT83XX_KBS_KSIGPODR REG8(IT83XX_KBS_BASE+0x26) -#define IT83XX_KBS_KSOHGPODR REG8(IT83XX_KBS_BASE+0x27) -#define IT83XX_KBS_KSOLGPODR REG8(IT83XX_KBS_BASE+0x28) +#define IT83XX_KBS_BASE 0x00F01D00 + +#define IT83XX_KBS_KSOL REG8(IT83XX_KBS_BASE + 0x00) +#define IT83XX_KBS_KSOH1 REG8(IT83XX_KBS_BASE + 0x01) +#define IT83XX_KBS_KSOCTRL REG8(IT83XX_KBS_BASE + 0x02) +#define IT83XX_KBS_KSOH2 REG8(IT83XX_KBS_BASE + 0x03) +#define IT83XX_KBS_KSI REG8(IT83XX_KBS_BASE + 0x04) +#define IT83XX_KBS_KSICTRL REG8(IT83XX_KBS_BASE + 0x05) +#define IT83XX_KBS_KSIGCTRL REG8(IT83XX_KBS_BASE + 0x06) +#define IT83XX_KBS_KSIGOEN REG8(IT83XX_KBS_BASE + 0x07) +#define IT83XX_KBS_KSIGDAT REG8(IT83XX_KBS_BASE + 0x08) +#define IT83XX_KBS_KSIGDMRR REG8(IT83XX_KBS_BASE + 0x09) +#define IT83XX_KBS_KSOHGCTRL REG8(IT83XX_KBS_BASE + 0x0A) +#define IT83XX_KBS_KSOHGOEN REG8(IT83XX_KBS_BASE + 0x0B) +#define IT83XX_KBS_KSOHGDMRR REG8(IT83XX_KBS_BASE + 0x0C) +#define IT83XX_KBS_KSOLGCTRL REG8(IT83XX_KBS_BASE + 0x0D) +#define IT83XX_KBS_KSOLGOEN REG8(IT83XX_KBS_BASE + 0x0E) +#define IT83XX_KBS_KSOLGDMRR REG8(IT83XX_KBS_BASE + 0x0F) +#define IT83XX_KBS_KSO0LSDR REG8(IT83XX_KBS_BASE + 0x10) +#define IT83XX_KBS_KSO1LSDR REG8(IT83XX_KBS_BASE + 0x11) +#define IT83XX_KBS_KSO2LSDR REG8(IT83XX_KBS_BASE + 0x12) +#define IT83XX_KBS_KSO3LSDR REG8(IT83XX_KBS_BASE + 0x13) +#define IT83XX_KBS_KSO4LSDR REG8(IT83XX_KBS_BASE + 0x14) +#define IT83XX_KBS_KSO5LSDR REG8(IT83XX_KBS_BASE + 0x15) +#define IT83XX_KBS_KSO6LSDR REG8(IT83XX_KBS_BASE + 0x16) +#define IT83XX_KBS_KSO7LSDR REG8(IT83XX_KBS_BASE + 0x17) +#define IT83XX_KBS_KSO8LSDR REG8(IT83XX_KBS_BASE + 0x18) +#define IT83XX_KBS_KSO9LSDR REG8(IT83XX_KBS_BASE + 0x19) +#define IT83XX_KBS_KSO10LSDR REG8(IT83XX_KBS_BASE + 0x1A) +#define IT83XX_KBS_KSO11LSDR REG8(IT83XX_KBS_BASE + 0x1B) +#define IT83XX_KBS_KSO12LSDR REG8(IT83XX_KBS_BASE + 0x1C) +#define IT83XX_KBS_KSO13LSDR REG8(IT83XX_KBS_BASE + 0x1D) +#define IT83XX_KBS_KSO14LSDR REG8(IT83XX_KBS_BASE + 0x1E) +#define IT83XX_KBS_KSO15LSDR REG8(IT83XX_KBS_BASE + 0x1F) +#define IT83XX_KBS_KSO16LSDR REG8(IT83XX_KBS_BASE + 0x20) +#define IT83XX_KBS_KSO17LSDR REG8(IT83XX_KBS_BASE + 0x21) +#define IT83XX_KBS_SDC1R REG8(IT83XX_KBS_BASE + 0x22) +#define IT83XX_KBS_SDC2R REG8(IT83XX_KBS_BASE + 0x23) +#define IT83XX_KBS_SDC3R REG8(IT83XX_KBS_BASE + 0x24) +#define IT83XX_KBS_SDSR REG8(IT83XX_KBS_BASE + 0x25) +#define IT83XX_KBS_KSIGPODR REG8(IT83XX_KBS_BASE + 0x26) +#define IT83XX_KBS_KSOHGPODR REG8(IT83XX_KBS_BASE + 0x27) +#define IT83XX_KBS_KSOLGPODR REG8(IT83XX_KBS_BASE + 0x28) /* Shared Memory Flash Interface Bridge (SMFI) */ -#define IT83XX_SMFI_BASE 0x00F01000 - -#define IT83XX_SMFI_SMECCS REG8(IT83XX_SMFI_BASE+0x20) -#define IT83XX_SMFI_MASK_HOSTWA BIT(5) -#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE+0x5A) -#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE+0x5B) -#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE+0x5C) -#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE+0x5D) -#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE+0x5E) -#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE+0x76) -#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE+0x77) -#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE+0x78) -#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE+0x79) -#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE+0x7A) -#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE+0x7B) -#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE+0x7C) -#define IT83XX_SMFI_ECINDAR0 REG8(IT83XX_SMFI_BASE+0x3B) -#define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE+0x3C) -#define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE+0x3D) -#define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE+0x3E) +#define IT83XX_SMFI_BASE 0x00F01000 + +#define IT83XX_SMFI_SMECCS REG8(IT83XX_SMFI_BASE + 0x20) +#define IT83XX_SMFI_MASK_HOSTWA BIT(5) +#define IT83XX_SMFI_HRAMWC REG8(IT83XX_SMFI_BASE + 0x5A) +#define IT83XX_SMFI_HRAMW0BA REG8(IT83XX_SMFI_BASE + 0x5B) +#define IT83XX_SMFI_HRAMW1BA REG8(IT83XX_SMFI_BASE + 0x5C) +#define IT83XX_SMFI_HRAMW0AAS REG8(IT83XX_SMFI_BASE + 0x5D) +#define IT83XX_SMFI_HRAMW1AAS REG8(IT83XX_SMFI_BASE + 0x5E) +#define IT83XX_SMFI_HRAMW2BA REG8(IT83XX_SMFI_BASE + 0x76) +#define IT83XX_SMFI_HRAMW3BA REG8(IT83XX_SMFI_BASE + 0x77) +#define IT83XX_SMFI_HRAMW2AAS REG8(IT83XX_SMFI_BASE + 0x78) +#define IT83XX_SMFI_HRAMW3AAS REG8(IT83XX_SMFI_BASE + 0x79) +#define IT83XX_SMFI_H2RAMECSIE REG8(IT83XX_SMFI_BASE + 0x7A) +#define IT83XX_SMFI_H2RAMECSA REG8(IT83XX_SMFI_BASE + 0x7B) +#define IT83XX_SMFI_H2RAMHSS REG8(IT83XX_SMFI_BASE + 0x7C) +#define IT83XX_SMFI_ECINDAR0 REG8(IT83XX_SMFI_BASE + 0x3B) +#define IT83XX_SMFI_ECINDAR1 REG8(IT83XX_SMFI_BASE + 0x3C) +#define IT83XX_SMFI_ECINDAR2 REG8(IT83XX_SMFI_BASE + 0x3D) +#define IT83XX_SMFI_ECINDAR3 REG8(IT83XX_SMFI_BASE + 0x3E) #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) -#define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE+0x3F) -#define IT83XX_SMFI_SCAR0L REG8(IT83XX_SMFI_BASE+0x40) -#define IT83XX_SMFI_SCAR0M REG8(IT83XX_SMFI_BASE+0x41) -#define IT83XX_SMFI_SCAR0H REG8(IT83XX_SMFI_BASE+0x42) -#define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE+0x46) -#define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE+0x47) -#define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE+0x48) -#define IT83XX_SMFI_FLHCTRL3R REG8(IT83XX_SMFI_BASE+0x63) -#define IT83XX_SMFI_STCDMACR REG8(IT83XX_SMFI_BASE+0x80) -#define IT83XX_SMFI_FLHCTRL6R REG8(IT83XX_SMFI_BASE+0xA2) +#define IT83XX_SMFI_ECINDDR REG8(IT83XX_SMFI_BASE + 0x3F) +#define IT83XX_SMFI_SCAR0L REG8(IT83XX_SMFI_BASE + 0x40) +#define IT83XX_SMFI_SCAR0M REG8(IT83XX_SMFI_BASE + 0x41) +#define IT83XX_SMFI_SCAR0H REG8(IT83XX_SMFI_BASE + 0x42) +#define IT83XX_SMFI_SCAR2L REG8(IT83XX_SMFI_BASE + 0x46) +#define IT83XX_SMFI_SCAR2M REG8(IT83XX_SMFI_BASE + 0x47) +#define IT83XX_SMFI_SCAR2H REG8(IT83XX_SMFI_BASE + 0x48) +#define IT83XX_SMFI_FLHCTRL3R REG8(IT83XX_SMFI_BASE + 0x63) +#define IT83XX_SMFI_STCDMACR REG8(IT83XX_SMFI_BASE + 0x80) +#define IT83XX_SMFI_FLHCTRL6R REG8(IT83XX_SMFI_BASE + 0xA2) /* Enable EC-indirect page program command */ #define IT83XX_SMFI_MASK_ECINDPP BIT(3) /* Serial Peripheral Interface (SSPI) */ -#define IT83XX_SSPI_BASE 0x00F02600 +#define IT83XX_SSPI_BASE 0x00F02600 -#define IT83XX_SSPI_SPIDATA REG8(IT83XX_SSPI_BASE+0x00) -#define IT83XX_SSPI_SPICTRL1 REG8(IT83XX_SSPI_BASE+0x01) -#define IT83XX_SSPI_SPICTRL2 REG8(IT83XX_SSPI_BASE+0x02) -#define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE+0x03) -#define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE+0x04) +#define IT83XX_SSPI_SPIDATA REG8(IT83XX_SSPI_BASE + 0x00) +#define IT83XX_SSPI_SPICTRL1 REG8(IT83XX_SSPI_BASE + 0x01) +#define IT83XX_SSPI_SPICTRL2 REG8(IT83XX_SSPI_BASE + 0x02) +#define IT83XX_SSPI_SPISTS REG8(IT83XX_SSPI_BASE + 0x03) +#define IT83XX_SSPI_SPICTRL3 REG8(IT83XX_SSPI_BASE + 0x04) /* Serial Peripheral Interface (SPI) */ -#define IT83XX_SPI_BASE 0x00F03A00 - -#define IT83XX_SPI_SPISGCR REG8(IT83XX_SPI_BASE+0x00) -#define IT83XX_SPI_SPISCEN BIT(0) -#define IT83XX_SPI_TXRXFAR REG8(IT83XX_SPI_BASE+0x01) -#define IT83XX_SPI_CPURXF2A BIT(4) -#define IT83XX_SPI_CPURXF1A BIT(3) -#define IT83XX_SPI_CPUTFA BIT(1) -#define IT83XX_SPI_TXFCR REG8(IT83XX_SPI_BASE+0x02) -#define IT83XX_SPI_TXFCMR BIT(2) -#define IT83XX_SPI_TXFR BIT(1) -#define IT83XX_SPI_TXFS BIT(0) -#define IT83XX_SPI_GCR2 REG8(IT83XX_SPI_BASE+0x03) -#define IT83XX_SPI_RXF2OC BIT(4) -#define IT83XX_SPI_RXF1OC BIT(3) -#define IT83XX_SPI_RXFAR BIT(0) -#define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE+0x04) -#define IT83XX_SPI_RX_FIFO_FULL BIT(7) -#define IT83XX_SPI_RX_REACH BIT(5) -#define IT83XX_SPI_EDIM BIT(2) -#define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE+0x05) -#define IT83XX_SPI_TXFSR REG8(IT83XX_SPI_BASE+0x06) -#define IT83XX_SPI_ENDDETECTINT BIT(2) -#define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE+0x07) -#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) -#define IT83XX_SPI_RXF2FS BIT(2) -#define IT83XX_SPI_RXF1FS BIT(1) +#define IT83XX_SPI_BASE 0x00F03A00 + +#define IT83XX_SPI_SPISGCR REG8(IT83XX_SPI_BASE + 0x00) +#define IT83XX_SPI_SPISCEN BIT(0) +#define IT83XX_SPI_TXRXFAR REG8(IT83XX_SPI_BASE + 0x01) +#define IT83XX_SPI_CPURXF2A BIT(4) +#define IT83XX_SPI_CPURXF1A BIT(3) +#define IT83XX_SPI_CPUTFA BIT(1) +#define IT83XX_SPI_TXFCR REG8(IT83XX_SPI_BASE + 0x02) +#define IT83XX_SPI_TXFCMR BIT(2) +#define IT83XX_SPI_TXFR BIT(1) +#define IT83XX_SPI_TXFS BIT(0) +#define IT83XX_SPI_GCR2 REG8(IT83XX_SPI_BASE + 0x03) +#define IT83XX_SPI_RXF2OC BIT(4) +#define IT83XX_SPI_RXF1OC BIT(3) +#define IT83XX_SPI_RXFAR BIT(0) +#define IT83XX_SPI_IMR REG8(IT83XX_SPI_BASE + 0x04) +#define IT83XX_SPI_RX_FIFO_FULL BIT(7) +#define IT83XX_SPI_RX_REACH BIT(5) +#define IT83XX_SPI_EDIM BIT(2) +#define IT83XX_SPI_ISR REG8(IT83XX_SPI_BASE + 0x05) +#define IT83XX_SPI_TXFSR REG8(IT83XX_SPI_BASE + 0x06) +#define IT83XX_SPI_ENDDETECTINT BIT(2) +#define IT83XX_SPI_RXFSR REG8(IT83XX_SPI_BASE + 0x07) +#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3)) +#define IT83XX_SPI_RXF2FS BIT(2) +#define IT83XX_SPI_RXF1FS BIT(1) #ifdef CHIP_VARIANT_IT83202BX -#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE+0x08) +#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x08) #else -#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE+0x0b) +#define IT83XX_SPI_SPISRDR REG8(IT83XX_SPI_BASE + 0x0b) #endif -#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE+0x08) -#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE+0x09) -#define IT83XX_SPI_SPISRTXF BIT(2) -#define IT83XX_SPI_RXFR BIT(1) -#define IT83XX_SPI_RXFCMR BIT(0) -#define IT83XX_SPI_RXFRDRB0 REG32(IT83XX_SPI_BASE+0x0C) -#define IT83XX_SPI_FTCB0R REG8(IT83XX_SPI_BASE+0x18) -#define IT83XX_SPI_FTCB1R REG8(IT83XX_SPI_BASE+0x19) -#define IT83XX_SPI_TCCB0 REG8(IT83XX_SPI_BASE+0x1A) -#define IT83XX_SPI_TCCB1 REG8(IT83XX_SPI_BASE+0x1B) -#define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE+0x1E) -#define IT83XX_SPI_EMMCBMR REG8(IT83XX_SPI_BASE+0x21) -#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ -#define IT83XX_SPI_RX_VLISMR REG8(IT83XX_SPI_BASE+0x26) -#define IT83XX_SPI_RVLIM BIT(0) -#define IT83XX_SPI_RX_VLISR REG8(IT83XX_SPI_BASE+0x27) -#define IT83XX_SPI_RVLI BIT(0) +#define IT83XX_SPI_CPUWTFDB0 REG32(IT83XX_SPI_BASE + 0x08) +#define IT83XX_SPI_FCR REG8(IT83XX_SPI_BASE + 0x09) +#define IT83XX_SPI_SPISRTXF BIT(2) +#define IT83XX_SPI_RXFR BIT(1) +#define IT83XX_SPI_RXFCMR BIT(0) +#define IT83XX_SPI_RXFRDRB0 REG32(IT83XX_SPI_BASE + 0x0C) +#define IT83XX_SPI_FTCB0R REG8(IT83XX_SPI_BASE + 0x18) +#define IT83XX_SPI_FTCB1R REG8(IT83XX_SPI_BASE + 0x19) +#define IT83XX_SPI_TCCB0 REG8(IT83XX_SPI_BASE + 0x1A) +#define IT83XX_SPI_TCCB1 REG8(IT83XX_SPI_BASE + 0x1B) +#define IT83XX_SPI_HPR2 REG8(IT83XX_SPI_BASE + 0x1E) +#define IT83XX_SPI_EMMCBMR REG8(IT83XX_SPI_BASE + 0x21) +#define IT83XX_SPI_EMMCABM BIT(1) /* eMMC Alternative Boot Mode */ +#define IT83XX_SPI_RX_VLISMR REG8(IT83XX_SPI_BASE + 0x26) +#define IT83XX_SPI_RVLIM BIT(0) +#define IT83XX_SPI_RX_VLISR REG8(IT83XX_SPI_BASE + 0x27) +#define IT83XX_SPI_RVLI BIT(0) /* Platform Environment Control Interface (PECI) */ -#define IT83XX_PECI_BASE 0x00F02C00 - -#define IT83XX_PECI_HOSTAR REG8(IT83XX_PECI_BASE+0x00) -#define IT83XX_PECI_HOCTLR REG8(IT83XX_PECI_BASE+0x01) -#define IT83XX_PECI_HOCMDR REG8(IT83XX_PECI_BASE+0x02) -#define IT83XX_PECI_HOTRADDR REG8(IT83XX_PECI_BASE+0x03) -#define IT83XX_PECI_HOWRLR REG8(IT83XX_PECI_BASE+0x04) -#define IT83XX_PECI_HORDLR REG8(IT83XX_PECI_BASE+0x05) -#define IT83XX_PECI_HOWRDR REG8(IT83XX_PECI_BASE+0x06) -#define IT83XX_PECI_HORDDR REG8(IT83XX_PECI_BASE+0x07) -#define IT83XX_PECI_HOCTL2R REG8(IT83XX_PECI_BASE+0x08) -#define IT83XX_PECI_RWFCSV REG8(IT83XX_PECI_BASE+0x09) -#define IT83XX_PECI_RRFCSV REG8(IT83XX_PECI_BASE+0x0A) -#define IT83XX_PECI_WFCSV REG8(IT83XX_PECI_BASE+0x0B) -#define IT83XX_PECI_RFCSV REG8(IT83XX_PECI_BASE+0x0C) -#define IT83XX_PECI_AWFCSV REG8(IT83XX_PECI_BASE+0x0D) -#define IT83XX_PECI_PADCTLR REG8(IT83XX_PECI_BASE+0x0E) +#define IT83XX_PECI_BASE 0x00F02C00 + +#define IT83XX_PECI_HOSTAR REG8(IT83XX_PECI_BASE + 0x00) +#define IT83XX_PECI_HOCTLR REG8(IT83XX_PECI_BASE + 0x01) +#define IT83XX_PECI_HOCMDR REG8(IT83XX_PECI_BASE + 0x02) +#define IT83XX_PECI_HOTRADDR REG8(IT83XX_PECI_BASE + 0x03) +#define IT83XX_PECI_HOWRLR REG8(IT83XX_PECI_BASE + 0x04) +#define IT83XX_PECI_HORDLR REG8(IT83XX_PECI_BASE + 0x05) +#define IT83XX_PECI_HOWRDR REG8(IT83XX_PECI_BASE + 0x06) +#define IT83XX_PECI_HORDDR REG8(IT83XX_PECI_BASE + 0x07) +#define IT83XX_PECI_HOCTL2R REG8(IT83XX_PECI_BASE + 0x08) +#define IT83XX_PECI_RWFCSV REG8(IT83XX_PECI_BASE + 0x09) +#define IT83XX_PECI_RRFCSV REG8(IT83XX_PECI_BASE + 0x0A) +#define IT83XX_PECI_WFCSV REG8(IT83XX_PECI_BASE + 0x0B) +#define IT83XX_PECI_RFCSV REG8(IT83XX_PECI_BASE + 0x0C) +#define IT83XX_PECI_AWFCSV REG8(IT83XX_PECI_BASE + 0x0D) +#define IT83XX_PECI_PADCTLR REG8(IT83XX_PECI_BASE + 0x0E) /* * The count number of the counter for 25 ms register. * The 25 ms register is calculated by (count number *1.024 kHz). */ -#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ +#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */ /* SMBus/I2C Interface (SMB/I2C) */ -#define IT83XX_SMB_BASE 0x00F01C00 - -#define IT83XX_SMB_4P7USL REG8(IT83XX_SMB_BASE+0x00) -#define IT83XX_SMB_4P0USL REG8(IT83XX_SMB_BASE+0x01) -#define IT83XX_SMB_300NS REG8(IT83XX_SMB_BASE+0x02) -#define IT83XX_SMB_250NS REG8(IT83XX_SMB_BASE+0x03) -#define IT83XX_SMB_25MS REG8(IT83XX_SMB_BASE+0x04) -#define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE+0x05) -#define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE+0x06) -#define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE+0x07) -#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE+0x08) -#define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE+0x09+ch) -#define IT83XX_SMB_CHSEF REG8(IT83XX_SMB_BASE+0x11) -#define IT83XX_SMB_CHSAB REG8(IT83XX_SMB_BASE+0x20) -#define IT83XX_SMB_CHSCD REG8(IT83XX_SMB_BASE+0x21) -#define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE+0x40+(ch << 6)) -#define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE+0x41+(ch << 6)) -#define IT83XX_SMB_HOCMD(ch) REG8(IT83XX_SMB_BASE+0x42+(ch << 6)) -#define IT83XX_SMB_TRASLA(ch) REG8(IT83XX_SMB_BASE+0x43+(ch << 6)) -#define IT83XX_SMB_D0REG(ch) REG8(IT83XX_SMB_BASE+0x44+(ch << 6)) -#define IT83XX_SMB_D1REG(ch) REG8(IT83XX_SMB_BASE+0x45+(ch << 6)) -#define IT83XX_SMB_HOBDB(ch) REG8(IT83XX_SMB_BASE+0x46+(ch << 6)) -#define IT83XX_SMB_PECERC(ch) REG8(IT83XX_SMB_BASE+0x47+(ch << 6)) -#define IT83XX_SMB_SMBPCTL(ch) REG8(IT83XX_SMB_BASE+0x4A+(ch << 6)) -#define IT83XX_SMB_HOCTL2(ch) REG8(IT83XX_SMB_BASE+0x50+(ch << 6)) -#define IT83XX_SMB_SLVEN (1 << 5) -#define IT83XX_SMB_RESLADR REG8(IT83XX_SMB_BASE+0x48) -#define IT83XX_SMB_SLDA REG8(IT83XX_SMB_BASE+0x49) -#define IT83XX_SMB_SLSTA REG8(IT83XX_SMB_BASE+0x4B) -#define IT83XX_SMB_SPDS (1 << 5) -#define IT83XX_SMB_RCS (1 << 3) -#define IT83XX_SMB_STS (1 << 2) -#define IT83XX_SMB_SDS (1 << 1) -#define IT83XX_SMB_SICR REG8(IT83XX_SMB_BASE+0x4C) -#define IT83XX_SMB_RESLADR2 REG8(IT83XX_SMB_BASE+0x51) -#define IT83XX_SMB_ENADDR2 (1 << 7) -#define IT83XX_SMB_SFFCTL REG8(IT83XX_SMB_BASE+0x55) -#define IT83XX_SMB_HSAPE BIT(1) -#define IT83XX_SMB_SAFE (1 << 0) -#define IT83XX_SMB_SFFSTA REG8(IT83XX_SMB_BASE+0x56) -#define IT83XX_SMB_SFFFULL (1 << 6) +#define IT83XX_SMB_BASE 0x00F01C00 + +#define IT83XX_SMB_4P7USL REG8(IT83XX_SMB_BASE + 0x00) +#define IT83XX_SMB_4P0USL REG8(IT83XX_SMB_BASE + 0x01) +#define IT83XX_SMB_300NS REG8(IT83XX_SMB_BASE + 0x02) +#define IT83XX_SMB_250NS REG8(IT83XX_SMB_BASE + 0x03) +#define IT83XX_SMB_25MS REG8(IT83XX_SMB_BASE + 0x04) +#define IT83XX_SMB_45P3USL REG8(IT83XX_SMB_BASE + 0x05) +#define IT83XX_SMB_45P3USH REG8(IT83XX_SMB_BASE + 0x06) +#define IT83XX_SMB_4P7A4P0H REG8(IT83XX_SMB_BASE + 0x07) +#define IT83XX_SMB_SLVISELR REG8(IT83XX_SMB_BASE + 0x08) +#define IT83XX_SMB_SCLKTS(ch) REG8(IT83XX_SMB_BASE + 0x09 + ch) +#define IT83XX_SMB_CHSEF REG8(IT83XX_SMB_BASE + 0x11) +#define IT83XX_SMB_CHSAB REG8(IT83XX_SMB_BASE + 0x20) +#define IT83XX_SMB_CHSCD REG8(IT83XX_SMB_BASE + 0x21) +#define IT83XX_SMB_HOSTA(ch) REG8(IT83XX_SMB_BASE + 0x40 + (ch << 6)) +#define IT83XX_SMB_HOCTL(ch) REG8(IT83XX_SMB_BASE + 0x41 + (ch << 6)) +#define IT83XX_SMB_HOCMD(ch) REG8(IT83XX_SMB_BASE + 0x42 + (ch << 6)) +#define IT83XX_SMB_TRASLA(ch) REG8(IT83XX_SMB_BASE + 0x43 + (ch << 6)) +#define IT83XX_SMB_D0REG(ch) REG8(IT83XX_SMB_BASE + 0x44 + (ch << 6)) +#define IT83XX_SMB_D1REG(ch) REG8(IT83XX_SMB_BASE + 0x45 + (ch << 6)) +#define IT83XX_SMB_HOBDB(ch) REG8(IT83XX_SMB_BASE + 0x46 + (ch << 6)) +#define IT83XX_SMB_PECERC(ch) REG8(IT83XX_SMB_BASE + 0x47 + (ch << 6)) +#define IT83XX_SMB_SMBPCTL(ch) REG8(IT83XX_SMB_BASE + 0x4A + (ch << 6)) +#define IT83XX_SMB_HOCTL2(ch) REG8(IT83XX_SMB_BASE + 0x50 + (ch << 6)) +#define IT83XX_SMB_SLVEN (1 << 5) +#define IT83XX_SMB_RESLADR REG8(IT83XX_SMB_BASE + 0x48) +#define IT83XX_SMB_SLDA REG8(IT83XX_SMB_BASE + 0x49) +#define IT83XX_SMB_SLSTA REG8(IT83XX_SMB_BASE + 0x4B) +#define IT83XX_SMB_SPDS (1 << 5) +#define IT83XX_SMB_RCS (1 << 3) +#define IT83XX_SMB_STS (1 << 2) +#define IT83XX_SMB_SDS (1 << 1) +#define IT83XX_SMB_SICR REG8(IT83XX_SMB_BASE + 0x4C) +#define IT83XX_SMB_RESLADR2 REG8(IT83XX_SMB_BASE + 0x51) +#define IT83XX_SMB_ENADDR2 (1 << 7) +#define IT83XX_SMB_SFFCTL REG8(IT83XX_SMB_BASE + 0x55) +#define IT83XX_SMB_HSAPE BIT(1) +#define IT83XX_SMB_SAFE (1 << 0) +#define IT83XX_SMB_SFFSTA REG8(IT83XX_SMB_BASE + 0x56) +#define IT83XX_SMB_SFFFULL (1 << 6) /* BRAM */ -#define IT83XX_BRAM_BASE 0x00F02200 +#define IT83XX_BRAM_BASE 0x00F02200 /* offset 0 ~ 0x7f */ -#define IT83XX_BRAM_BANK0(i) REG8(IT83XX_BRAM_BASE + i) +#define IT83XX_BRAM_BANK0(i) REG8(IT83XX_BRAM_BASE + i) /* Battery backed RAM indices. */ enum bram_indices { /* reset flags uses 4 bytes */ @@ -1441,21 +1438,21 @@ enum bram_indices { BRAM_IDX_RESET_FLAGS3 = 3, /* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */ - BRAM_IDX_PD0 = 4, - BRAM_IDX_PD1 = 5, - BRAM_IDX_PD2 = 6, + BRAM_IDX_PD0 = 4, + BRAM_IDX_PD1 = 5, + BRAM_IDX_PD2 = 6, /* index 7 is reserved */ - BRAM_IDX_SCRATCHPAD0 = 8, - BRAM_IDX_SCRATCHPAD1 = 9, - BRAM_IDX_SCRATCHPAD2 = 0xa, - BRAM_IDX_SCRATCHPAD3 = 0xb, + BRAM_IDX_SCRATCHPAD0 = 8, + BRAM_IDX_SCRATCHPAD1 = 9, + BRAM_IDX_SCRATCHPAD2 = 0xa, + BRAM_IDX_SCRATCHPAD3 = 0xb, /* EC logs status */ BRAM_IDX_EC_LOG_STATUS = 0xc, - /* offset 0x0d ~ 0x1f are reserved for future use. */ +/* offset 0x0d ~ 0x1f are reserved for future use. */ #if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI) /* * offset 0x20 ~ 0x7b are reserved for future use. @@ -1463,45 +1460,42 @@ enum bram_indices { */ /* This field is used to indicate BRAM is valid or not. */ - BRAM_IDX_VALID_FLAGS0 = 0x7c, - BRAM_IDX_VALID_FLAGS1 = 0x7d, - BRAM_IDX_VALID_FLAGS2 = 0x7e, - BRAM_IDX_VALID_FLAGS3 = 0x7f - /* offset 0x7f is the end of BRAM bank 0. */ + BRAM_IDX_VALID_FLAGS0 = 0x7c, + BRAM_IDX_VALID_FLAGS1 = 0x7d, + BRAM_IDX_VALID_FLAGS2 = 0x7e, + BRAM_IDX_VALID_FLAGS3 = 0x7f +/* offset 0x7f is the end of BRAM bank 0. */ #else /* panic data uses 144 bytes (offset 0x20 ~ 0xaf) */ - BRAM_PANIC_DATA_START = 0x20, - BRAM_PANIC_DATA_END = 0xaf, + BRAM_PANIC_DATA_START = 0x20, + BRAM_PANIC_DATA_END = 0xaf, /* This field is used to indicate BRAM is valid or not. */ - BRAM_IDX_VALID_FLAGS0 = 0xbc, - BRAM_IDX_VALID_FLAGS1 = 0xbd, - BRAM_IDX_VALID_FLAGS2 = 0xbe, - BRAM_IDX_VALID_FLAGS3 = 0xbf - /* offset 0xbf is the end of BRAM bank 1. */ + BRAM_IDX_VALID_FLAGS0 = 0xbc, + BRAM_IDX_VALID_FLAGS1 = 0xbd, + BRAM_IDX_VALID_FLAGS2 = 0xbe, + BRAM_IDX_VALID_FLAGS3 = 0xbf +/* offset 0xbf is the end of BRAM bank 1. */ #endif }; -#define BRAM_RESET_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0) -#define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1) -#define BRAM_RESET_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2) -#define BRAM_RESET_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3) - -#define BRAM_SCRATCHPAD0 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0) -#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1) -#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2) -#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3) - -#define BRAM_EC_LOG_STATUS IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS) -enum bram_ec_logs_status { - EC_LOG_SAVED_IN_FLASH = 1, - EC_LOG_SAVED_IN_MEMORY -}; +#define BRAM_RESET_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS0) +#define BRAM_RESET_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS1) +#define BRAM_RESET_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS2) +#define BRAM_RESET_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_RESET_FLAGS3) + +#define BRAM_SCRATCHPAD0 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD0) +#define BRAM_SCRATCHPAD1 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD1) +#define BRAM_SCRATCHPAD2 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD2) +#define BRAM_SCRATCHPAD3 IT83XX_BRAM_BANK0(BRAM_IDX_SCRATCHPAD3) + +#define BRAM_EC_LOG_STATUS IT83XX_BRAM_BANK0(BRAM_IDX_EC_LOG_STATUS) +enum bram_ec_logs_status { EC_LOG_SAVED_IN_FLASH = 1, EC_LOG_SAVED_IN_MEMORY }; -#define BRAM_VALID_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0) -#define BRAM_VALID_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1) -#define BRAM_VALID_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2) -#define BRAM_VALID_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3) +#define BRAM_VALID_FLAGS0 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS0) +#define BRAM_VALID_FLAGS1 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS1) +#define BRAM_VALID_FLAGS2 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS2) +#define BRAM_VALID_FLAGS3 IT83XX_BRAM_BANK0(BRAM_IDX_VALID_FLAGS3) /* * These 128 bytes are use to latch port 80h data on x86 platform. @@ -1510,7 +1504,7 @@ enum bram_ec_logs_status { */ #if defined(CONFIG_HOST_INTERFACE_LPC) || defined(CONFIG_HOST_INTERFACE_ESPI) /* offset 0x80 ~ 0xbf */ -#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i) +#define IT83XX_BRAM_BANK1(i) REG8(IT83XX_BRAM_BASE + 0x80 + i) #else /* Length of bram panic data */ #define BRAM_PANIC_LEN (BRAM_PANIC_DATA_END - BRAM_PANIC_DATA_START + 1) @@ -1521,153 +1515,153 @@ enum bram_ec_logs_status { * Ch_D: 0x00F03680 , Ch_E: 0x00F03500 , Ch_F: 0x00F03580 * Ch_D: ch = 0x03 , Ch_E: ch = 0x00 , Ch_F: ch = 0x01 */ -#define IT83XX_I2C_BASE 0x00F03500 - -#define IT83XX_I2C_DRR(ch) REG8(IT83XX_I2C_BASE+0x00+(ch << 7)) -#define IT83XX_I2C_PSR(ch) REG8(IT83XX_I2C_BASE+0x01+(ch << 7)) -#define IT83XX_I2C_HSPR(ch) REG8(IT83XX_I2C_BASE+0x02+(ch << 7)) -#define IT83XX_I2C_STR(ch) REG8(IT83XX_I2C_BASE+0x03+(ch << 7)) -#define IT83XX_I2C_BB (1 << 5) -#define IT83XX_I2C_TIME_OUT (1 << 3) -#define IT83XX_I2C_RW (1 << 2) -#define IT83XX_I2C_INTPEND (1 << 1) -#define IT83XX_I2C_DHTR(ch) REG8(IT83XX_I2C_BASE+0x04+(ch << 7)) -#define IT83XX_I2C_TOR(ch) REG8(IT83XX_I2C_BASE+0x05+(ch << 7)) -#define IT83XX_I2C_DTR(ch) REG8(IT83XX_I2C_BASE+0x08+(ch << 7)) -#define IT83XX_I2C_CTR(ch) REG8(IT83XX_I2C_BASE+0x09+(ch << 7)) -#define IT83XX_I2C_INTEN (1 << 6) -#define IT83XX_I2C_MODE (1 << 5) -#define IT83XX_I2C_STARST (1 << 4) -#define IT83XX_I2C_ACK (1 << 3) -#define IT83XX_I2C_HALT (1 << 0) -#define IT83XX_I2C_CTR1(ch) REG8(IT83XX_I2C_BASE+0x0A+(ch << 7)) -#define IT83XX_I2C_COMQ_EN (1 << 7) -#define IT83XX_I2C_MDL_EN (1 << 1) -#define IT83XX_I2C_BYTE_CNT_L(ch) REG8(IT83XX_I2C_BASE+0x0C+(ch << 7)) -#define IT83XX_I2C_IRQ_ST(ch) REG8(IT83XX_I2C_BASE+0x0D+(ch << 7)) -#define IT83XX_I2C_IDW_CLR (1 << 3) -#define IT83XX_I2C_IDR_CLR (1 << 2) -#define IT83XX_I2C_SLVDATAFLG (1 << 1) -#define IT83XX_I2C_P_CLR (1 << 0) -#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE+0x06+(ch << 7)) -#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE+0x07+(ch << 7)) -#define IT83XX_I2C_CLK_STR (1 << 7) -#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE+0x12+(ch << 7)) -#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE+0x13+(ch << 7)) -#define IT83XX_I2C_NST_CNS BIT(7) -#define IT83XX_I2C_NST_ID_NACK BIT(3) -#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE+0x18+(ch << 7)) -#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE+0x19+(ch << 7)) -#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0) -#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE+0x1b+(ch << 7)) -#define IT83XX_I2C_FST_DEV1_IRQ BIT(4) -#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE+0x1c+(ch << 7)) -#define IT83XX_I2C_EM_DEV1_IRQ BIT(4) -#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE+0x1d+(ch << 7)) -#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE+0x1F+(ch << 7)) -#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE+0x20+(ch << 7)) -#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE+0x23+(ch << 7)) -#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE+0x24+(ch << 7)) -#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE+0x2B+(ch << 7)) -#define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE+0x2C+(ch << 7)) -#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE+0x25+(ch << 7)) -#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE+0x26+(ch << 7)) -#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE+0x50+(ch << 7)) -#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE+0x52+(ch << 7)) +#define IT83XX_I2C_BASE 0x00F03500 + +#define IT83XX_I2C_DRR(ch) REG8(IT83XX_I2C_BASE + 0x00 + (ch << 7)) +#define IT83XX_I2C_PSR(ch) REG8(IT83XX_I2C_BASE + 0x01 + (ch << 7)) +#define IT83XX_I2C_HSPR(ch) REG8(IT83XX_I2C_BASE + 0x02 + (ch << 7)) +#define IT83XX_I2C_STR(ch) REG8(IT83XX_I2C_BASE + 0x03 + (ch << 7)) +#define IT83XX_I2C_BB (1 << 5) +#define IT83XX_I2C_TIME_OUT (1 << 3) +#define IT83XX_I2C_RW (1 << 2) +#define IT83XX_I2C_INTPEND (1 << 1) +#define IT83XX_I2C_DHTR(ch) REG8(IT83XX_I2C_BASE + 0x04 + (ch << 7)) +#define IT83XX_I2C_TOR(ch) REG8(IT83XX_I2C_BASE + 0x05 + (ch << 7)) +#define IT83XX_I2C_DTR(ch) REG8(IT83XX_I2C_BASE + 0x08 + (ch << 7)) +#define IT83XX_I2C_CTR(ch) REG8(IT83XX_I2C_BASE + 0x09 + (ch << 7)) +#define IT83XX_I2C_INTEN (1 << 6) +#define IT83XX_I2C_MODE (1 << 5) +#define IT83XX_I2C_STARST (1 << 4) +#define IT83XX_I2C_ACK (1 << 3) +#define IT83XX_I2C_HALT (1 << 0) +#define IT83XX_I2C_CTR1(ch) REG8(IT83XX_I2C_BASE + 0x0A + (ch << 7)) +#define IT83XX_I2C_COMQ_EN (1 << 7) +#define IT83XX_I2C_MDL_EN (1 << 1) +#define IT83XX_I2C_BYTE_CNT_L(ch) REG8(IT83XX_I2C_BASE + 0x0C + (ch << 7)) +#define IT83XX_I2C_IRQ_ST(ch) REG8(IT83XX_I2C_BASE + 0x0D + (ch << 7)) +#define IT83XX_I2C_IDW_CLR (1 << 3) +#define IT83XX_I2C_IDR_CLR (1 << 2) +#define IT83XX_I2C_SLVDATAFLG (1 << 1) +#define IT83XX_I2C_P_CLR (1 << 0) +#define IT83XX_I2C_IDR(ch) REG8(IT83XX_I2C_BASE + 0x06 + (ch << 7)) +#define IT83XX_I2C_TOS(ch) REG8(IT83XX_I2C_BASE + 0x07 + (ch << 7)) +#define IT83XX_I2C_CLK_STR (1 << 7) +#define IT83XX_I2C_STR2(ch) REG8(IT83XX_I2C_BASE + 0x12 + (ch << 7)) +#define IT83XX_I2C_NST(ch) REG8(IT83XX_I2C_BASE + 0x13 + (ch << 7)) +#define IT83XX_I2C_NST_CNS BIT(7) +#define IT83XX_I2C_NST_ID_NACK BIT(3) +#define IT83XX_I2C_TO_ARB_ST(ch) REG8(IT83XX_I2C_BASE + 0x18 + (ch << 7)) +#define IT83XX_I2C_ERR_ST(ch) REG8(IT83XX_I2C_BASE + 0x19 + (ch << 7)) +#define IT83XX_I2C_ERR_ST_DEV1_EIRQ BIT(0) +#define IT83XX_I2C_FST(ch) REG8(IT83XX_I2C_BASE + 0x1b + (ch << 7)) +#define IT83XX_I2C_FST_DEV1_IRQ BIT(4) +#define IT83XX_I2C_EM(ch) REG8(IT83XX_I2C_BASE + 0x1c + (ch << 7)) +#define IT83XX_I2C_EM_DEV1_IRQ BIT(4) +#define IT83XX_I2C_MODE_SEL(ch) REG8(IT83XX_I2C_BASE + 0x1d + (ch << 7)) +#define IT83XX_I2C_IDR2(ch) REG8(IT83XX_I2C_BASE + 0x1F + (ch << 7)) +#define IT83XX_I2C_CTR2(ch) REG8(IT83XX_I2C_BASE + 0x20 + (ch << 7)) +#define IT83XX_I2C_RAMHA(ch) REG8(IT83XX_I2C_BASE + 0x23 + (ch << 7)) +#define IT83XX_I2C_RAMLA(ch) REG8(IT83XX_I2C_BASE + 0x24 + (ch << 7)) +#define IT83XX_I2C_RAMHA2(ch) REG8(IT83XX_I2C_BASE + 0x2B + (ch << 7)) +#define IT83XX_I2C_RAMLA2(ch) REG8(IT83XX_I2C_BASE + 0x2C + (ch << 7)) +#define IT83XX_I2C_CMD_ADDH(ch) REG8(IT83XX_I2C_BASE + 0x25 + (ch << 7)) +#define IT83XX_I2C_CMD_ADDL(ch) REG8(IT83XX_I2C_BASE + 0x26 + (ch << 7)) +#define IT83XX_I2C_RAMH2A(ch) REG8(IT83XX_I2C_BASE + 0x50 + (ch << 7)) +#define IT83XX_I2C_CMD_ADDH2(ch) REG8(IT83XX_I2C_BASE + 0x52 + (ch << 7)) enum i2c_channels { - IT83XX_I2C_CH_A, /* GPIO.B3/B4 */ - IT83XX_I2C_CH_B, /* GPIO.C1/C2 */ - IT83XX_I2C_CH_C, /* GPIO.F6/F7 or GPIO.C7/F7 */ - IT83XX_I2C_CH_D, /* GPIO.H1/H2 */ - IT83XX_I2C_CH_E, /* GPIO.E0/E7 */ - IT83XX_I2C_CH_F, /* GPIO.A4/A5 (for util/iteflash) */ + IT83XX_I2C_CH_A, /* GPIO.B3/B4 */ + IT83XX_I2C_CH_B, /* GPIO.C1/C2 */ + IT83XX_I2C_CH_C, /* GPIO.F6/F7 or GPIO.C7/F7 */ + IT83XX_I2C_CH_D, /* GPIO.H1/H2 */ + IT83XX_I2C_CH_E, /* GPIO.E0/E7 */ + IT83XX_I2C_CH_F, /* GPIO.A4/A5 (for util/iteflash) */ IT83XX_I2C_PORT_COUNT, }; #define USB_VID_ITE 0x048d -#define IT83XX_ESPI_BASE 0x00F03100 +#define IT83XX_ESPI_BASE 0x00F03100 -#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE+0x05) -#define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE+0x90) -#define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE+0xA0) -#define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE+0xA1) -#define IT83XX_ESPI_ESGCTRL2 REG8(IT83XX_ESPI_BASE+0xA2) +#define IT83XX_ESPI_GCAC1 REG8(IT83XX_ESPI_BASE + 0x05) +#define IT83XX_ESPI_ESPCTRL0 REG8(IT83XX_ESPI_BASE + 0x90) +#define IT83XX_ESPI_ESGCTRL0 REG8(IT83XX_ESPI_BASE + 0xA0) +#define IT83XX_ESPI_ESGCTRL1 REG8(IT83XX_ESPI_BASE + 0xA1) +#define IT83XX_ESPI_ESGCTRL2 REG8(IT83XX_ESPI_BASE + 0xA2) /* eSPI VW */ -#define IT83XX_ESPI_VW_BASE 0x00F03200 -#define IT83XX_ESPI_VWIDX(i) REG8(IT83XX_ESPI_VW_BASE+(i)) +#define IT83XX_ESPI_VW_BASE 0x00F03200 +#define IT83XX_ESPI_VWIDX(i) REG8(IT83XX_ESPI_VW_BASE + (i)) -#define VW_LEVEL_FIELD(f) ((f) << 0) -#define VW_VALID_FIELD(f) ((f) << 4) +#define VW_LEVEL_FIELD(f) ((f) << 0) +#define VW_VALID_FIELD(f) ((f) << 4) #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2 -#define VW_IDX_2_SLP_S3 BIT(0) -#define VW_IDX_2_SLP_S4 BIT(1) -#define VW_IDX_2_SLP_S5 BIT(2) +#define VW_IDX_2_SLP_S3 BIT(0) +#define VW_IDX_2_SLP_S4 BIT(1) +#define VW_IDX_2_SLP_S5 BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3 -#define VW_IDX_3_SUS_STAT BIT(0) -#define VW_IDX_3_PLTRST BIT(1) -#define VW_IDX_3_OOB_RST_WARN BIT(2) +#define VW_IDX_3_SUS_STAT BIT(0) +#define VW_IDX_3_PLTRST BIT(1) +#define VW_IDX_3_OOB_RST_WARN BIT(2) #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4 -#define VW_IDX_4_OOB_RST_ACK BIT(0) -#define VW_IDX_4_WAKE BIT(2) -#define VW_IDX_4_PME BIT(3) +#define VW_IDX_4_OOB_RST_ACK BIT(0) +#define VW_IDX_4_WAKE BIT(2) +#define VW_IDX_4_PME BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5 -#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0) -#define VW_IDX_5_FATAL BIT(1) -#define VW_IDX_5_NON_FATAL BIT(2) +#define VW_IDX_5_SLAVE_BTLD_DONE BIT(0) +#define VW_IDX_5_FATAL BIT(1) +#define VW_IDX_5_NON_FATAL BIT(2) #define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3) -#define VW_IDX_5_BTLD_STATUS_DONE (VW_IDX_5_SLAVE_BTLD_DONE | \ - VW_IDX_5_SLAVE_BTLD_STATUS) +#define VW_IDX_5_BTLD_STATUS_DONE \ + (VW_IDX_5_SLAVE_BTLD_DONE | VW_IDX_5_SLAVE_BTLD_STATUS) #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6 -#define VW_IDX_6_SCI BIT(0) -#define VW_IDX_6_SMI BIT(1) -#define VW_IDX_6_RCIN BIT(2) -#define VW_IDX_6_HOST_RST_ACK BIT(3) +#define VW_IDX_6_SCI BIT(0) +#define VW_IDX_6_SMI BIT(1) +#define VW_IDX_6_RCIN BIT(2) +#define VW_IDX_6_HOST_RST_ACK BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7 -#define VW_IDX_7_HOST_RST_WARN BIT(0) +#define VW_IDX_7_HOST_RST_WARN BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40 -#define VW_IDX_40_SUS_ACK BIT(0) +#define VW_IDX_40_SUS_ACK BIT(0) #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41 -#define VW_IDX_41_SUS_WARN BIT(0) -#define VW_IDX_41_SUS_PWRDN_ACK BIT(1) -#define VW_IDX_41_SLP_A BIT(3) +#define VW_IDX_41_SUS_WARN BIT(0) +#define VW_IDX_41_SUS_PWRDN_ACK BIT(1) +#define VW_IDX_41_SLP_A BIT(3) #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42 -#define VW_IDX_42_SLP_LAN BIT(0) -#define VW_IDX_42_SLP_WLAN BIT(1) +#define VW_IDX_42_SLP_LAN BIT(0) +#define VW_IDX_42_SLP_WLAN BIT(1) #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47 -#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE+0x90) +#define IT83XX_ESPI_VWCTRL0 REG8(IT83XX_ESPI_VW_BASE + 0x90) #define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7) -#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE+0x91) -#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE+0x92) -#define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE+0x93) +#define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE + 0x91) +#define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE + 0x92) +#define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE + 0x93) /* eSPI Queue 0 */ -#define IT83XX_ESPI_QUEUE_BASE 0x00F03300 +#define IT83XX_ESPI_QUEUE_BASE 0x00F03300 /* PUT_PC data byte 0 - 63 */ -#define IT83XX_ESPI_QUEUE_PUT_PC(i) REG8(IT83XX_ESPI_QUEUE_BASE+(i)) +#define IT83XX_ESPI_QUEUE_PUT_PC(i) REG8(IT83XX_ESPI_QUEUE_BASE + (i)) /* PUT_OOB data byte 0 - 79 */ -#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE+0x80+(i)) +#define IT83XX_ESPI_QUEUE_PUT_OOB(i) REG8(IT83XX_ESPI_QUEUE_BASE + 0x80 + (i)) /* USB Controller */ -#define IT83XX_USB_BASE 0x00F02F00 +#define IT83XX_USB_BASE 0x00F02F00 -#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE+0xE4) +#define IT83XX_USB_P0MCR REG8(IT83XX_USB_BASE + 0xE4) #define USB_DP_DM_PULL_DOWN_EN BIT(4) /* Wake pin definitions, defined at board-level */ @@ -1681,11 +1675,11 @@ extern int hibernate_wake_pins_used; /* --- MISC (not implemented yet) --- */ -#define IT83XX_PS2_BASE 0x00F01700 +#define IT83XX_PS2_BASE 0x00F01700 #define IT83XX_EGPIO_BASE 0x00F02100 -#define IT83XX_CIR_BASE 0x00F02300 -#define IT83XX_DBGR_BASE 0x00F02500 -#define IT83XX_OW_BASE 0x00F02A00 -#define IT83XX_CEC_BASE 0x00F02E00 +#define IT83XX_CIR_BASE 0x00F02300 +#define IT83XX_DBGR_BASE 0x00F02500 +#define IT83XX_OW_BASE 0x00F02A00 +#define IT83XX_CEC_BASE 0x00F02E00 #endif /* __CROS_EC_REGISTERS_H */ -- cgit v1.2.1 From 4e63a75740787db52ee99710e899a040abc783bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:18 -0600 Subject: chip/stm32/usart.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6039fd89de14d5bd508fa0a4c04389ef6136bc9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729542 Reviewed-by: Jeremy Bettis --- chip/stm32/usart.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/stm32/usart.h b/chip/stm32/usart.h index 491bd66a04..6999df5ac0 100644 --- a/chip/stm32/usart.h +++ b/chip/stm32/usart.h @@ -97,12 +97,12 @@ extern struct usart_tx const usart_tx_interrupt; * structure are provided by each variants driver, one per physical USART. */ struct usart_hw_config { - int index; + int index; intptr_t base; - int irq; + int irq; uint32_t volatile *clock_register; - uint32_t clock_enable; + uint32_t clock_enable; struct usart_hw_ops const *ops; }; @@ -160,7 +160,7 @@ struct usart_config { * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ +#define USART_CONFIG(HW, RX, TX, BAUD, FLAGS, RX_QUEUE, TX_QUEUE) \ ((struct usart_config const) { \ .hw = &HW, \ .rx = &RX, \ @@ -208,9 +208,9 @@ void usart_tx_start(struct usart_config const *config); * change. The baud rate divisor input frequency is passed in Hertz. */ void usart_set_baud_f0_l(struct usart_config const *config, int baud, - int frequency_hz); + int frequency_hz); void usart_set_baud_f(struct usart_config const *config, int baud, - int frequency_hz); + int frequency_hz); /* * Allow specification of parity for this usart. @@ -249,7 +249,7 @@ struct usart_configs { * * configs[i]->hw->index == i; */ - struct usart_config const * const *configs; + struct usart_config const *const *configs; /* * The total possible number of configs that this family supports. -- cgit v1.2.1 From 6f3e6db15ef7de7748a8bbbeaa1302336fa04f7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:40 -0600 Subject: board/banshee/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d93e867024348ec5f98052af6cc264c8f9646d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727998 Reviewed-by: Jeremy Bettis --- board/banshee/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/banshee/fans.c b/board/banshee/fans.c index 73bd0dcd77..295dce6baa 100644 --- a/board/banshee/fans.c +++ b/board/banshee/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 555935c71dcb298083e42f76b2c9655900f69ec1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:36 -0600 Subject: driver/led/mp3385.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I54703b8a313a2e024addf891186233c2d8a06686 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730017 Reviewed-by: Jeremy Bettis --- driver/led/mp3385.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/driver/led/mp3385.c b/driver/led/mp3385.c index 278e333ae1..babe17f849 100644 --- a/driver/led/mp3385.c +++ b/driver/led/mp3385.c @@ -13,10 +13,10 @@ #include "task.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) -#define I2C_ADDR_MP3385_FLAGS 0x31 +#define I2C_ADDR_MP3385_FLAGS 0x31 struct mp3385_value { uint8_t offset; @@ -40,36 +40,36 @@ static struct mp3385_value mp3385_conf[] = { * Frequency selection: 300(KHz) * Short circuit protection: 8(V) */ - {.offset = 1, .data = 0x43}, + { .offset = 1, .data = 0x43 }, /* * Register 0x02: LED current Full-Scale Register * ISET Resistor: 127(Kohm) * Maximum LED current: 20196/127 = 159(mA) * Setting LED current: 62(mA) */ - {.offset = 2, .data = 0x65}, + { .offset = 2, .data = 0x65 }, - /* Register 0x03: RO - ignored */ + /* Register 0x03: RO - ignored */ /* * Register 0x04: Internal LED Dimming Brightness Register * SMBus PWM function: None Use */ - {.offset = 4, .data = 0x00}, + { .offset = 4, .data = 0x00 }, /* * Register 0x05: OVP, OCP Threshold Register * Over Current Protection: 0.5(V) * Panel LED Voltage(Max): 47.8(V) * OVP setting: 54(V) */ - {.offset = 5, .data = 0x97}, + { .offset = 5, .data = 0x97 }, /* * Register 0x00: Dimming mode Register * String Selection: 4(Number) * Interface Selection: 1 * Brightness mode: 3 */ - {.offset = 0, .data = 0xF2}, + { .offset = 0, .data = 0xF2 }, }; static const int mp3385_conf_size = ARRAY_SIZE(mp3385_conf); @@ -78,12 +78,12 @@ static void set_mp3385_reg(void) int i; for (i = 0; i < mp3385_conf_size; ++i) { - int rv = i2c_write8(I2C_PORT_BACKLIGHT, - I2C_ADDR_MP3385_FLAGS, + int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_MP3385_FLAGS, mp3385_conf[i].offset, mp3385_conf[i].data); if (rv) { CPRINTS("Write MP3385 register %d " - "failed rv=%d", i, rv); + "failed rv=%d", + i, rv); return; } } @@ -113,7 +113,7 @@ void mp3385_interrupt(enum gpio_signal signal) * |- t2 -| : 1 second is enough */ hook_call_deferred(&mp3385_backlight_enable_deferred_data, - MP3385_POWER_BACKLIGHT_DELAY); + MP3385_POWER_BACKLIGHT_DELAY); } int mp3385_set_config(int offset, int data) -- cgit v1.2.1 From eb63980fa66b3f48da41b9110a63fa6c3ac34802 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:06 -0600 Subject: board/nocturne/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4edf306b877b61ed5e4877d396b84a84c939a78a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728758 Reviewed-by: Jeremy Bettis --- board/nocturne/board.c | 170 +++++++++++++++++++++---------------------------- 1 file changed, 74 insertions(+), 96 deletions(-) diff --git a/board/nocturne/board.c b/board/nocturne/board.c index ac29dfb942..e4c703847f 100644 --- a/board/nocturne/board.c +++ b/board/nocturne/board.c @@ -46,8 +46,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal s) { @@ -101,80 +101,67 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); const struct adc_t adc_channels[] = { - [ADC_BASE_ATTACH] = { - "BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, + [ADC_BASE_ATTACH] = { "BASE ATTACH", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, - [ADC_BASE_DETACH] = { - "BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, + [ADC_BASE_DETACH] = { "BASE DETACH", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_DB0_LED_RED] = { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - 986 }, + [PWM_CH_DB0_LED_RED] = { 3, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 986 }, [PWM_CH_DB0_LED_GREEN] = { 0, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 986 }, - [PWM_CH_DB0_LED_BLUE] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - 986 }, - [PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - 986 }, + [PWM_CH_DB0_LED_BLUE] = { 2, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 986 }, + [PWM_CH_DB1_LED_RED] = { 7, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 986 }, [PWM_CH_DB1_LED_GREEN] = { 5, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, 986 }, - [PWM_CH_DB1_LED_BLUE] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - 986 }, + [PWM_CH_DB1_LED_BLUE] = { 6, PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + 986 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_EC_I2C4_BATTERY_SCL, - .sda = GPIO_EC_I2C4_BATTERY_SDA - }, - - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C0_POWER_SCL, - .sda = GPIO_EC_I2C0_POWER_SDA - }, - - { - .name = "als_gyro", - .port = I2C_PORT_ALS_GYRO, - .kbps = 400, - .scl = GPIO_EC_I2C5_ALS_GYRO_SCL, - .sda = GPIO_EC_I2C5_ALS_GYRO_SDA - }, - - { - .name = "usbc0", - .port = I2C_PORT_USB_C0, - .kbps = 100, - .scl = GPIO_USB_C0_SCL, - .sda = GPIO_USB_C0_SDA - }, - - { - .name = "usbc1", - .port = I2C_PORT_USB_C1, - .kbps = 100, - .scl = GPIO_USB_C1_SCL, - .sda = GPIO_USB_C1_SDA - }, + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_EC_I2C4_BATTERY_SCL, + .sda = GPIO_EC_I2C4_BATTERY_SDA }, + + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C0_POWER_SCL, + .sda = GPIO_EC_I2C0_POWER_SDA }, + + { .name = "als_gyro", + .port = I2C_PORT_ALS_GYRO, + .kbps = 400, + .scl = GPIO_EC_I2C5_ALS_GYRO_SCL, + .sda = GPIO_EC_I2C5_ALS_GYRO_SDA }, + + { .name = "usbc0", + .port = I2C_PORT_USB_C0, + .kbps = 100, + .scl = GPIO_USB_C0_SCL, + .sda = GPIO_USB_C0_SDA }, + + { .name = "usbc1", + .port = I2C_PORT_USB_C1, + .kbps = 100, + .scl = GPIO_USB_C1_SCL, + .sda = GPIO_USB_C1_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - /* * Motion Sense */ @@ -191,11 +178,9 @@ static struct opt3001_drv_data_t g_opt3001_data = { }; /* Matrix to rotate accel/gyro into standard reference frame. */ -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -303,11 +288,9 @@ static void enable_sensor_irqs(void) DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_sensor_irqs, HOOK_PRIO_DEFAULT); struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_USB_C0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, { .i2c_port = I2C_PORT_USB_C1, .i2c_addr_flags = SN5S330_ADDR0_FLAGS, @@ -366,8 +349,7 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); static void imvp8_tune_deferred(void) { /* For the IMVP8, reduce the steps during decay from 3 to 1. */ - if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS, - 0xFA, 0x0AC5)) + if (i2c_write16(I2C_PORT_POWER, I2C_ADDR_MP2949_FLAGS, 0xFA, 0x0AC5)) CPRINTS("Failed to change step decay!"); } DECLARE_DEFERRED(imvp8_tune_deferred); @@ -522,8 +504,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void) i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x6a); } -__override void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__override void power_board_handle_host_sleep_event(enum host_sleep_event state) { if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) board_pmic_enable_slp_s0_vr_decay(); @@ -536,8 +517,7 @@ static void board_pmic_init(void) int pgmask1; /* Mask V5A_DS3_PG from PMIC PGMASK1. */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - 0x18, &pgmask1)) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, &pgmask1)) return; pgmask1 |= BIT(2); i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x18, pgmask1); @@ -611,19 +591,19 @@ static int read_gyro_sensor_temp(int idx, int *temp_ptr) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* These BD99992GW temp sensors are only readable in S0 */ - {"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, - {"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM3}, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, + { "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM3 }, /* The Gyro temperature sensor is only readable in S0. */ - {"Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO} + { "Gyro", TEMP_SENSOR_TYPE_BOARD, read_gyro_sensor_temp, LID_GYRO } }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -633,16 +613,15 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); */ struct ec_thermal_config thermal_params[] = { /* {Twarn, Thigh, Thalt}, fan_off, fan_max */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* Battery */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* Ambient */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* Charger */ - {{0, C_TO_K(52), 0}, {0, 0, 0}, 0, 0}, /* DRAM */ - {{0, 0, 0}, {0, 0, 0}, 0, 0}, /* eMMC */ - {{0, 0, 0}, {0, 0, 0}, 0, 0} /* Gyro */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Battery */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Ambient */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* Charger */ + { { 0, C_TO_K(52), 0 }, { 0, 0, 0 }, 0, 0 }, /* DRAM */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 }, /* eMMC */ + { { 0, 0, 0 }, { 0, 0, 0 }, 0, 0 } /* Gyro */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); - /* * Check if PMIC fault registers indicate VR fault. If yes, print out fault * register info to console. Additionally, set panic reason so that the OS can @@ -655,8 +634,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) != + EC_SUCCESS) return; if (!(vrfault & BIT(4))) @@ -709,8 +688,7 @@ void board_set_tcpc_power_mode(int port, int mode) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; int old_port; @@ -775,8 +753,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); -- cgit v1.2.1 From 59197d57935723c8baf411ddbbb986b25bfdebd1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:51 -0600 Subject: zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I96460ef3600e1a95f9caa24bb5e618748d69bbc4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730706 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c index c71b4bc833..eb98e6525d 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_faulty_snk.c @@ -42,9 +42,8 @@ static void tcpci_faulty_snk_emul_reduce_action_count( k_fifo_get(&data->action_list, K_FOREVER); } -void tcpci_faulty_snk_emul_append_action( - struct tcpci_faulty_snk_emul_data *data, - struct tcpci_faulty_snk_action *action) +void tcpci_faulty_snk_emul_append_action(struct tcpci_faulty_snk_emul_data *data, + struct tcpci_faulty_snk_action *action) { k_fifo_put(&data->action_list, action); } @@ -67,10 +66,10 @@ void tcpci_faulty_snk_emul_clear_actions_list( * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled */ -static enum tcpci_partner_handler_res tcpci_faulty_snk_emul_handle_sop_msg( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data, - const struct tcpci_emul_msg *msg) +static enum tcpci_partner_handler_res +tcpci_faulty_snk_emul_handle_sop_msg(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data, + const struct tcpci_emul_msg *msg) { struct tcpci_faulty_snk_emul_data *data = CONTAINER_OF(ext, struct tcpci_faulty_snk_emul_data, ext); @@ -106,8 +105,7 @@ static enum tcpci_partner_handler_res tcpci_faulty_snk_emul_handle_sop_msg( tcpci_partner_received_msg_status( common_data, TCPCI_EMUL_TX_DISCARDED); tcpci_partner_send_control_msg( - common_data, - PD_CTRL_ACCEPT, 0); + common_data, PD_CTRL_ACCEPT, 0); tcpci_faulty_snk_emul_reduce_action_count(data); return TCPCI_PARTNER_COMMON_MSG_HANDLED; } @@ -140,10 +138,10 @@ struct tcpci_partner_extension_ops tcpci_faulty_snk_emul_ops = { .connect = NULL, }; -struct tcpci_partner_extension *tcpci_faulty_snk_emul_init( - struct tcpci_faulty_snk_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext) +struct tcpci_partner_extension * +tcpci_faulty_snk_emul_init(struct tcpci_faulty_snk_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext) { struct tcpci_partner_extension *snk_ext = &data->ext; -- cgit v1.2.1 From d613ac551187475bbeb05d5c022b438fba65a555 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:48 -0600 Subject: chip/stm32/bkpdata.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I880bf35c8c397a7cf81c7abfdf42fd7584faf174 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729457 Reviewed-by: Jeremy Bettis --- chip/stm32/bkpdata.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/chip/stm32/bkpdata.h b/chip/stm32/bkpdata.h index 199ed213a9..f974769c86 100644 --- a/chip/stm32/bkpdata.h +++ b/chip/stm32/bkpdata.h @@ -20,27 +20,27 @@ * compatibility. */ enum bkpdata_index { - BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ - BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ + BKPDATA_INDEX_SCRATCHPAD, /* General-purpose scratchpad */ + BKPDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ #ifdef CONFIG_STM32_EXTENDED_RESET_FLAGS - BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ + BKPDATA_INDEX_SAVED_RESET_FLAGS_2, /* Saved reset flags (cont) */ #endif #ifdef CONFIG_SOFTWARE_PANIC - BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ - BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ + BKPDATA_INDEX_SAVED_PANIC_REASON, /* Saved panic reason */ + BKPDATA_INDEX_SAVED_PANIC_INFO, /* Saved panic data */ BKPDATA_INDEX_SAVED_PANIC_EXCEPTION, /* Saved panic exception code */ #endif #ifdef CONFIG_USB_PD_DUAL_ROLE - BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ - BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ - BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ + BKPDATA_INDEX_PD0, /* USB-PD saved port0 state */ + BKPDATA_INDEX_PD1, /* USB-PD saved port1 state */ + BKPDATA_INDEX_PD2, /* USB-PD saved port2 state */ #endif #ifdef CONFIG_SOFTWARE_PANIC /** * Saving the panic flags in case that AP thinks the panic is new * after a hard reset. */ - BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */ + BKPDATA_INDEX_SAVED_PANIC_FLAGS, /* Saved panic flags */ #endif BKPDATA_COUNT }; -- cgit v1.2.1 From aad120b0d538d941089286c80b779452e8752185 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:53 -0600 Subject: driver/ppc/sn5s330.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23b01861eeeb75000d0ab46dc82e8aad89be2f2a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730050 Reviewed-by: Jeremy Bettis --- driver/ppc/sn5s330.c | 123 +++++++++++++++++++++------------------------------ 1 file changed, 51 insertions(+), 72 deletions(-) diff --git a/driver/ppc/sn5s330.c b/driver/ppc/sn5s330.c index 6a157b005e..75258e1925 100644 --- a/driver/ppc/sn5s330.c +++ b/driver/ppc/sn5s330.c @@ -23,8 +23,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -32,17 +32,13 @@ static int source_enabled[CONFIG_USB_PD_PORT_MAX_COUNT]; static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int set_flags(const int port, const int addr, const int flags_to_set) @@ -58,7 +54,6 @@ static int set_flags(const int port, const int addr, const int flags_to_set) return write_reg(port, addr, val); } - static int clr_flags(const int port, const int addr, const int flags_to_clear) { int val, rv; @@ -85,9 +80,7 @@ static int sn5s330_dump(int port) for (i = SN5S330_FUNC_SET1; i <= SN5S330_FUNC_SET12; i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("FUNC_SET%d [%02Xh] = 0x%02x\n", - i - SN5S330_FUNC_SET1 + 1, - i, - data); + i - SN5S330_FUNC_SET1 + 1, i, data); } cflush(); @@ -95,9 +88,7 @@ static int sn5s330_dump(int port) for (i = SN5S330_INT_STATUS_REG1; i <= SN5S330_INT_STATUS_REG4; i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("INT_STATUS_REG%d [%02Xh] = 0x%02x\n", - i - SN5S330_INT_STATUS_REG1 + 1, - i, - data); + i - SN5S330_INT_STATUS_REG1 + 1, i, data); } cflush(); @@ -106,9 +97,7 @@ static int sn5s330_dump(int port) i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("INT_TRIP_RISE_REG%d [%02Xh] = 0x%02x\n", - i - SN5S330_INT_TRIP_RISE_REG1 + 1, - i, - data); + i - SN5S330_INT_TRIP_RISE_REG1 + 1, i, data); } cflush(); @@ -117,9 +106,7 @@ static int sn5s330_dump(int port) i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("INT_TRIP_FALL_REG%d [%02Xh] = 0x%02x\n", - i - SN5S330_INT_TRIP_FALL_REG1 + 1, - i, - data); + i - SN5S330_INT_TRIP_FALL_REG1 + 1, i, data); } cflush(); @@ -128,9 +115,7 @@ static int sn5s330_dump(int port) i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("INT_MASK_RISE_REG%d [%02Xh] = 0x%02x\n", - i - SN5S330_INT_MASK_RISE_REG1 + 1, - i, - data); + i - SN5S330_INT_MASK_RISE_REG1 + 1, i, data); } cflush(); @@ -139,9 +124,7 @@ static int sn5s330_dump(int port) i++) { i2c_read8(i2c_port, i2c_addr_flags, i, &data); ccprintf("INT_MASK_FALL_REG%d [%02Xh] = 0x%02x\n", - i - SN5S330_INT_MASK_FALL_REG1 + 1, - i, - data); + i - SN5S330_INT_MASK_FALL_REG1 + 1, i, data); } cflush(); @@ -165,8 +148,8 @@ static int sn5s330_pp_fet_enable(uint8_t port, enum sn5s330_pp_idx pp, return EC_ERROR_INVAL; /* LCOV_EXCL_STOP */ - status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit) - : clr_flags(port, SN5S330_FUNC_SET3, pp_bit); + status = enable ? set_flags(port, SN5S330_FUNC_SET3, pp_bit) : + clr_flags(port, SN5S330_FUNC_SET3, pp_bit); if (status) { ppc_prints("Failed to set FUNC_SET3!", port); @@ -185,7 +168,7 @@ static int sn5s330_init(int port) int status; int retries; int reg; - const int i2c_port = ppc_chips[port].i2c_port; + const int i2c_port = ppc_chips[port].i2c_port; const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags; #ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT @@ -213,11 +196,10 @@ static int sn5s330_init(int port) */ retries = 0; do { - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET1, regval); + status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET1, + regval); if (status) { - ppc_prints("Failed to set FUNC_SET1! Retrying..", - port); + ppc_prints("Failed to set FUNC_SET1! Retrying..", port); retries++; msleep(1); } else { @@ -227,24 +209,24 @@ static int sn5s330_init(int port) /* Set Vbus OVP threshold to ~22.325V. */ regval = 0x37; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET5, regval); + status = + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET5, regval); if (status) { ppc_prints("Failed to set FUNC_SET5!", port); return status; } /* Set Vbus UVP threshold to ~2.75V. */ - status = i2c_read8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET6, ®val); + status = + i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, ®val); if (status) { ppc_prints("Failed to read FUNC_SET6!", port); return status; } regval &= ~0x3F; regval |= 1; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET6, regval); + status = + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET6, regval); if (status) { ppc_prints("Failed to write FUNC_SET6!", port); return status; @@ -252,8 +234,8 @@ static int sn5s330_init(int port) /* Enable SBU Fets and set PP2 current limit to ~3A. */ regval = SN5S330_SBU_EN | 0x8; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET2, regval); + status = + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET2, regval); if (status) { ppc_prints("Failed to set FUNC_SET2!", port); return status; @@ -272,8 +254,8 @@ static int sn5s330_init(int port) * low voltage protection). */ regval = SN5S330_OVP_EN_CC | SN5S330_PP2_CONFIG | SN5S330_CONFIG_UVP; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET9, regval); + status = + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET9, regval); if (status) { ppc_prints("Failed to set FUNC_SET9!", port); return status; @@ -284,7 +266,7 @@ static int sn5s330_init(int port) * set 1000 us for PP2 for compatibility. */ regval = (PPX_ILIM_DEGLITCH_0_US_200 << 3) | - PPX_ILIM_DEGLITCH_0_US_1000; + PPX_ILIM_DEGLITCH_0_US_1000; status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET11, regval); if (status) { @@ -299,16 +281,16 @@ static int sn5s330_init(int port) * reset default (20 us). */ regval = 0; - status = i2c_read8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET8, ®val); + status = + i2c_read8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, ®val); if (status) { ppc_prints("Failed to read FUNC_SET8!", port); return status; } regval &= ~SN5S330_VCONN_DEGLITCH_MASK; regval |= SN5S330_VCONN_DEGLITCH_640_US; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_FUNC_SET8, regval); + status = + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_FUNC_SET8, regval); if (status) { ppc_prints("Failed to set FUNC_SET8!", port); return status; @@ -366,8 +348,8 @@ static int sn5s330_init(int port) * is checked below. */ regval = SN5S330_DIG_RES | SN5S330_VSAFE0V_MASK; - status = i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_INT_STATUS_REG4, regval); + status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4, + regval); if (status) { ppc_prints("Failed to write INT_STATUS_REG4!", port); return status; @@ -418,7 +400,7 @@ static int sn5s330_init(int port) regval = ~SN5S330_VBUS_GOOD_MASK; #else regval = 0xFF; -#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */ +#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */ status = i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_MASK_RISE_REG3, regval); @@ -436,24 +418,21 @@ static int sn5s330_init(int port) /* Now clear any pending interrupts. */ for (reg = SN5S330_INT_TRIP_RISE_REG1; - reg <= SN5S330_INT_TRIP_FALL_REG3; - reg++) { - status = i2c_write8(i2c_port, i2c_addr_flags, - reg, 0xFF); + reg <= SN5S330_INT_TRIP_FALL_REG3; reg++) { + status = i2c_write8(i2c_port, i2c_addr_flags, reg, 0xFF); if (status) { - CPRINTS("ppc p%d: Failed to write reg 0x%2x!", - port, reg); + CPRINTS("ppc p%d: Failed to write reg 0x%2x!", port, + reg); return status; } } - /* * For PP2, check to see if we booted in dead battery mode. If we * booted in dead battery mode, the PP2 FET will already be enabled. */ - status = i2c_read8(i2c_port, i2c_addr_flags, - SN5S330_INT_STATUS_REG4, ®val); + status = i2c_read8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4, + ®val); if (status) { ppc_prints("Failed to read INT_STATUS_REG4!", port); return status; @@ -464,8 +443,8 @@ static int sn5s330_init(int port) * Clear the bit by writing 1 and keep vSafe0V_MASK * unchanged. */ - i2c_write8(i2c_port, i2c_addr_flags, - SN5S330_INT_STATUS_REG4, regval); + i2c_write8(i2c_port, i2c_addr_flags, SN5S330_INT_STATUS_REG4, + regval); /* * Turn on PP2 FET. @@ -559,13 +538,13 @@ static int sn5s330_set_vbus_source_current_limit(int port, static int sn5s330_discharge_vbus(int port, int enable) { int status = enable ? set_flags(port, SN5S330_FUNC_SET3, - SN5S330_VBUS_DISCH_EN) - : clr_flags(port, SN5S330_FUNC_SET3, + SN5S330_VBUS_DISCH_EN) : + clr_flags(port, SN5S330_FUNC_SET3, SN5S330_VBUS_DISCH_EN); if (status) { - CPRINTS("ppc p%d: Failed to %s vbus discharge", - port, enable ? "enable" : "disable"); + CPRINTS("ppc p%d: Failed to %s vbus discharge", port, + enable ? "enable" : "disable"); return status; } @@ -681,7 +660,8 @@ static void sn5s330_handle_interrupt(int port) if (attempt > 1) ppc_prints("Could not clear interrupts on first " - "try, retrying", port); + "try, retrying", + port); read_reg(port, SN5S330_INT_TRIP_RISE_REG1, &rise); read_reg(port, SN5S330_INT_TRIP_FALL_REG1, &fall); @@ -719,16 +699,15 @@ static void sn5s330_handle_interrupt(int port) read_reg(port, SN5S330_INT_TRIP_FALL_REG3, &fall); /* Inform other modules about VBUS level */ - if (rise & SN5S330_VBUS_GOOD_MASK - || fall & SN5S330_VBUS_GOOD_MASK) + if (rise & SN5S330_VBUS_GOOD_MASK || + fall & SN5S330_VBUS_GOOD_MASK) usb_charger_vbus_change(port, sn5s330_is_vbus_present(port)); /* Clear the interrupt sources. */ write_reg(port, SN5S330_INT_TRIP_RISE_REG3, rise); write_reg(port, SN5S330_INT_TRIP_FALL_REG3, fall); -#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */ - +#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */ } } -- cgit v1.2.1 From a1defa96c334e58bdfa99f6f9b5459a6492a8110 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:49 -0600 Subject: zephyr/shim/src/pwm_led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d4de18b7f9101d0211f39903af90a14521a65e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730899 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/pwm_led.c | 97 +++++++++++++++++++++++------------------------ 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/zephyr/shim/src/pwm_led.c b/zephyr/shim/src/pwm_led.c index 09fbd009b4..2e4712e98e 100644 --- a/zephyr/shim/src/pwm_led.c +++ b/zephyr/shim/src/pwm_led.c @@ -25,15 +25,14 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, BUILD_ASSERT(DT_INST_PROP_LEN(0, leds) <= 2, "Unsupported number of LEDs defined"); -#define PWM_LED_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency)) +#define PWM_LED_PERIOD_NS (NSEC_PER_SEC / DT_INST_PROP(0, frequency)) #define PWM_SIDESEL_PERIOD_NS (PWM_LED_PERIOD_NS * 2) #define PWM_LED_NAME(node_id) DT_STRING_UPPER_TOKEN(node_id, ec_led_name) #define PWM_LED_NAME_WITH_COMMA(node_id) PWM_LED_NAME(node_id), -const enum ec_led_id supported_led_ids[] = { - DT_INST_FOREACH_CHILD(0, PWM_LED_NAME_WITH_COMMA) -}; +const enum ec_led_id supported_led_ids[] = { DT_INST_FOREACH_CHILD( + 0, PWM_LED_NAME_WITH_COMMA) }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); BUILD_ASSERT(ARRAY_SIZE(supported_led_ids) == DT_INST_PROP_LEN(0, leds), @@ -65,68 +64,68 @@ static void pwm_led_set_duty(const struct pwm_led_dt_channel *ch, int percent) .dev = DEVICE_DT_GET(DT_PWMS_CTLR_BY_IDX(node_id, led_ch)), \ .channel = DT_PWMS_CHANNEL_BY_IDX(node_id, led_ch), \ .flags = DT_PWMS_FLAGS_BY_IDX(node_id, led_ch), \ - .period_ns = _period_ns, \ + .period_ns = _period_ns, \ } -#define PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch) \ - static const struct pwm_led_dt_channel _pwm_led_dt_##idx##_ch_##led_ch = \ - PWM_CHANNEL_DT_BY_IDX_INIT( \ - DT_PHANDLE_BY_IDX(node_id, prop, idx), led_ch, \ +#define PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch) \ + static const struct pwm_led_dt_channel \ + _pwm_led_dt_##idx##_ch_##led_ch = PWM_CHANNEL_DT_BY_IDX_INIT( \ + DT_PHANDLE_BY_IDX(node_id, prop, idx), led_ch, \ PWM_LED_PERIOD_NS); -#define PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, led_ch) \ - IF_ENABLED(DT_PROP_HAS_IDX( \ - DT_PHANDLE_BY_IDX(node_id, prop, idx), pwms, led_ch), \ - (PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch)) \ - ) +#define PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, led_ch) \ + IF_ENABLED(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \ + pwms, led_ch), \ + (PWM_CHANNEL_DT_BY_IDX(node_id, prop, idx, led_ch))) -#define PWM_LED_DT_INIT(node_id, prop, idx) \ +#define PWM_LED_DT_INIT(node_id, prop, idx) \ PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 0) \ PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 1) \ PWM_CHANNEL_DT_BY_IDX_COND(node_id, prop, idx, 2) DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_DT_INIT) -#define PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, led_ch) \ - COND_CODE_1(DT_PROP_HAS_IDX( \ - DT_PHANDLE_BY_IDX(node_id, prop, idx), pwms, led_ch), \ - (&_pwm_led_dt_##idx##_ch_##led_ch), \ - (PWM_LED_NO_CHANNEL)) +#define PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, led_ch) \ + COND_CODE_1(DT_PROP_HAS_IDX(DT_PHANDLE_BY_IDX(node_id, prop, idx), \ + pwms, led_ch), \ + (&_pwm_led_dt_##idx##_ch_##led_ch), (PWM_LED_NO_CHANNEL)) -#define PWM_LED_INIT(node_id, prop, idx) \ - [PWM_LED##idx] = { \ +#define PWM_LED_INIT(node_id, prop, idx) \ + [PWM_LED##idx] = { \ .ch0 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 0), \ .ch1 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 1), \ .ch2 = PWM_CHANNEL_BY_IDX_COND(node_id, prop, idx, 2), \ - .set_duty = &pwm_led_set_duty, \ + .set_duty = &pwm_led_set_duty, \ }, -struct pwm_led pwm_leds[] = { - DT_INST_FOREACH_PROP_ELEM(0, leds, PWM_LED_INIT) -}; +struct pwm_led pwm_leds[] = { DT_INST_FOREACH_PROP_ELEM(0, leds, + PWM_LED_INIT) }; -#define EC_LED_COLOR_BLANK {0} +#define EC_LED_COLOR_BLANK \ + { \ + 0 \ + } struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - [EC_LED_COLOR_RED] = DT_INST_PROP_OR(0, color_map_red, - EC_LED_COLOR_BLANK), - [EC_LED_COLOR_GREEN] = DT_INST_PROP_OR(0, color_map_green, - EC_LED_COLOR_BLANK), - [EC_LED_COLOR_BLUE] = DT_INST_PROP_OR(0, color_map_blue, - EC_LED_COLOR_BLANK), - [EC_LED_COLOR_YELLOW] = DT_INST_PROP_OR(0, color_map_yellow, - EC_LED_COLOR_BLANK), - [EC_LED_COLOR_WHITE] = DT_INST_PROP_OR(0, color_map_white, - EC_LED_COLOR_BLANK), - [EC_LED_COLOR_AMBER] = DT_INST_PROP_OR(0, color_map_amber, - EC_LED_COLOR_BLANK), + [EC_LED_COLOR_RED] = + DT_INST_PROP_OR(0, color_map_red, EC_LED_COLOR_BLANK), + [EC_LED_COLOR_GREEN] = + DT_INST_PROP_OR(0, color_map_green, EC_LED_COLOR_BLANK), + [EC_LED_COLOR_BLUE] = + DT_INST_PROP_OR(0, color_map_blue, EC_LED_COLOR_BLANK), + [EC_LED_COLOR_YELLOW] = + DT_INST_PROP_OR(0, color_map_yellow, EC_LED_COLOR_BLANK), + [EC_LED_COLOR_WHITE] = + DT_INST_PROP_OR(0, color_map_white, EC_LED_COLOR_BLANK), + [EC_LED_COLOR_AMBER] = + DT_INST_PROP_OR(0, color_map_amber, EC_LED_COLOR_BLANK), }; BUILD_ASSERT(DT_INST_PROP_LEN(0, brightness_range) == EC_LED_COLOR_COUNT, "brightness_range must have exactly EC_LED_COLOR_COUNT values"); -static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] = DT_INST_PROP( - 0, brightness_range); +static const uint8_t dt_brigthness_range[EC_LED_COLOR_COUNT] = + DT_INST_PROP(0, brightness_range); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { @@ -135,8 +134,8 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) sizeof(dt_brigthness_range)); } -#define PWM_NAME_TO_ID(node_id) \ - case PWM_LED_NAME(node_id): \ +#define PWM_NAME_TO_ID(node_id) \ + case PWM_LED_NAME(node_id): \ pwm_id = DT_REG_ADDR(node_id); \ break; @@ -145,7 +144,7 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) enum pwm_led_id pwm_id; switch (led_id) { - DT_INST_FOREACH_CHILD(0, PWM_NAME_TO_ID) + DT_INST_FOREACH_CHILD(0, PWM_NAME_TO_ID) default: return EC_ERROR_UNKNOWN; } @@ -154,19 +153,19 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) brightness[EC_LED_COLOR_RED]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_RED); } else if (DT_INST_NODE_HAS_PROP(0, color_map_green) && - brightness[EC_LED_COLOR_GREEN]) { + brightness[EC_LED_COLOR_GREEN]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_GREEN); } else if (DT_INST_NODE_HAS_PROP(0, color_map_blue) && - brightness[EC_LED_COLOR_BLUE]) { + brightness[EC_LED_COLOR_BLUE]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE); } else if (DT_INST_NODE_HAS_PROP(0, color_map_yellow) && - brightness[EC_LED_COLOR_YELLOW]) { + brightness[EC_LED_COLOR_YELLOW]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_YELLOW); } else if (DT_INST_NODE_HAS_PROP(0, color_map_white) && - brightness[EC_LED_COLOR_WHITE]) { + brightness[EC_LED_COLOR_WHITE]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE); } else if (DT_INST_NODE_HAS_PROP(0, color_map_amber) && - brightness[EC_LED_COLOR_AMBER]) { + brightness[EC_LED_COLOR_AMBER]) { set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER); } else { /* Otherwise, the "color" is "off". */ -- cgit v1.2.1 From 7ce0bcf5d9464b33fbd7b3c5365da9c7c731a042 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:12 -0600 Subject: driver/bc12/max14637.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5976a3e0b692ea4850633deff5f8c6dc164128cf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729932 Reviewed-by: Jeremy Bettis --- driver/bc12/max14637.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/driver/bc12/max14637.h b/driver/bc12/max14637.h index 2b18bc222b..744b1f78bd 100644 --- a/driver/bc12/max14637.h +++ b/driver/bc12/max14637.h @@ -7,8 +7,8 @@ #include "gpio.h" -#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0) -#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1) +#define MAX14637_FLAGS_ENABLE_ACTIVE_LOW BIT(0) +#define MAX14637_FLAGS_CHG_DET_ACTIVE_LOW BIT(1) struct max14637_config_t { /* @@ -29,5 +29,5 @@ struct max14637_config_t { * Array that contains boards-specific configuration for BC 1.2 charging chips. */ extern const struct max14637_config_t - max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT]; + max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT]; extern const struct bc12_drv max14637_drv; -- cgit v1.2.1 From ca11bc2825cb76363df23cc0a2f4f789f4a9837f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:01 -0600 Subject: board/meep/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f2de64cbbc86502cee3614d7d11eb9c22fe1bdb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728448 Reviewed-by: Jeremy Bettis --- board/meep/led.c | 65 +++++++++++++++++++++++++++++++------------------------- 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/board/meep/led.c b/board/meep/led.c index e20a88d268..825a7817fb 100644 --- a/board/meep/led.c +++ b/board/meep/led.c @@ -11,8 +11,8 @@ #include "led_onoff_states.h" #include "hooks.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -20,36 +20,43 @@ __override const int led_charge_lvl_2 = 100; /* Meep: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - /* STATE_DISCHARGE_S3 will changed if sku is clamshells */ - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_WHITE, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + /* STATE_DISCHARGE_S3 will changed if sku is clamshells */ + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; static void s3_led_init(void) { -- cgit v1.2.1 From bd9cf2bd7a81cd11bcb9f0f904823c9345399b6e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:16 -0600 Subject: driver/als_bh1730.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16b0068ca6efa0e32a2adfce9c41dfa99db8ce83 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729900 Reviewed-by: Jeremy Bettis --- driver/als_bh1730.h | 92 ++++++++++++++++++++++++++--------------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/driver/als_bh1730.h b/driver/als_bh1730.h index f4bbc37a13..e0161707bb 100644 --- a/driver/als_bh1730.h +++ b/driver/als_bh1730.h @@ -9,42 +9,42 @@ #define __CROS_EC_ALS_BH1730_H /* I2C interface */ -#define BH1730_I2C_ADDR_FLAGS 0x29 +#define BH1730_I2C_ADDR_FLAGS 0x29 /* BH1730 registers */ -#define BH1730_CONTROL 0x80 -#define BH1730_TIMING 0x81 -#define BH1730_INTERRUPT 0x82 -#define BH1730_THLLOW 0x83 -#define BH1730_THLHIGH 0x84 -#define BH1730_THHLOW 0x85 -#define BH1730_THHHIGH 0x86 -#define BH1730_GAIN 0x87 -#define BH1730_OPART_ID 0x92 -#define BH1730_DATA0LOW 0x94 -#define BH1730_DATA0HIGH 0x95 -#define BH1730_DATA1LOW 0x96 -#define BH1730_DATA1HIGH 0x97 +#define BH1730_CONTROL 0x80 +#define BH1730_TIMING 0x81 +#define BH1730_INTERRUPT 0x82 +#define BH1730_THLLOW 0x83 +#define BH1730_THLHIGH 0x84 +#define BH1730_THHLOW 0x85 +#define BH1730_THHHIGH 0x86 +#define BH1730_GAIN 0x87 +#define BH1730_OPART_ID 0x92 +#define BH1730_DATA0LOW 0x94 +#define BH1730_DATA0HIGH 0x95 +#define BH1730_DATA1LOW 0x96 +#define BH1730_DATA1HIGH 0x97 /* Software reset */ -#define BH1730_RESET 0xE4 +#define BH1730_RESET 0xE4 /* Registers bits */ -#define BH1730_CONTROL_ADC_INTR_INACTIVE (0x00 << 5) -#define BH1730_CONTROL_ADC_INTR_ACTIVE (0x01 << 5) -#define BH1730_CONTROL_ADC_VALID (0x01 << 4) -#define BH1730_CONTROL_ONE_TIME_CONTINOUS (0x00 << 3) -#define BH1730_CONTROL_ONE_TIME_ONETIME (0x01 << 3) -#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1 (0x00 << 2) -#define BH1730_CONTROL_DATA_SEL_TYPE0 (0x01 << 2) -#define BH1730_CONTROL_ADC_EN_DISABLE (0x00 << 1) -#define BH1730_CONTROL_ADC_EN_ENABLE (0x01 << 1) -#define BH1730_CONTROL_POWER_DISABLE (0x00 << 0) -#define BH1730_CONTROL_POWER_ENABLE (0x01 << 0) +#define BH1730_CONTROL_ADC_INTR_INACTIVE (0x00 << 5) +#define BH1730_CONTROL_ADC_INTR_ACTIVE (0x01 << 5) +#define BH1730_CONTROL_ADC_VALID (0x01 << 4) +#define BH1730_CONTROL_ONE_TIME_CONTINOUS (0x00 << 3) +#define BH1730_CONTROL_ONE_TIME_ONETIME (0x01 << 3) +#define BH1730_CONTROL_DATA_SEL_TYPE0_AND_1 (0x00 << 2) +#define BH1730_CONTROL_DATA_SEL_TYPE0 (0x01 << 2) +#define BH1730_CONTROL_ADC_EN_DISABLE (0x00 << 1) +#define BH1730_CONTROL_ADC_EN_ENABLE (0x01 << 1) +#define BH1730_CONTROL_POWER_DISABLE (0x00 << 0) +#define BH1730_CONTROL_POWER_ENABLE (0x01 << 0) -#define BH1730_GAIN_GAIN_X1_GAIN (0x00 << 0) -#define BH1730_GAIN_GAIN_X2_GAIN (0x01 << 0) -#define BH1730_GAIN_GAIN_X64_GAIN (0x02 << 0) -#define BH1730_GAIN_GAIN_X128_GAIN (0x03 << 0) +#define BH1730_GAIN_GAIN_X1_GAIN (0x00 << 0) +#define BH1730_GAIN_GAIN_X2_GAIN (0x01 << 0) +#define BH1730_GAIN_GAIN_X64_GAIN (0x02 << 0) +#define BH1730_GAIN_GAIN_X128_GAIN (0x03 << 0) /* Sensor configuration */ /* Select Gain */ @@ -54,10 +54,10 @@ /* Select Itime, 0xDA is 102.6ms = 38*2.7ms */ #define BH1730_CONF_ITIME 0xDA #define ITIME_MS_X_10 ((256 - BH1730_CONF_ITIME) * 27) -#define ITIME_MS_X_1K (ITIME_MS_X_10*100) +#define ITIME_MS_X_1K (ITIME_MS_X_10 * 100) /* default Itime is about 10Hz */ -#define BH1730_10000_MHZ (10*1000) +#define BH1730_10000_MHZ (10 * 1000) #define BH1730_MAX_FREQ BH1730_10000_MHZ /* * 10Hz is too fast for the AP: allow the AP query data less often, the EC will @@ -70,21 +70,21 @@ * parameters are not defined. */ #ifndef CONFIG_ALS_BH1730_LUXTH_PARAMS -#define BH1730_LUXTH1_1K 260 -#define BH1730_LUXTH1_D0_1K 1290 -#define BH1730_LUXTH1_D1_1K 2733 -#define BH1730_LUXTH2_1K 550 -#define BH1730_LUXTH2_D0_1K 797 -#define BH1730_LUXTH2_D1_1K 859 -#define BH1730_LUXTH3_1K 1090 -#define BH1730_LUXTH3_D0_1K 510 -#define BH1730_LUXTH3_D1_1K 345 -#define BH1730_LUXTH4_1K 2130 -#define BH1730_LUXTH4_D0_1K 276 -#define BH1730_LUXTH4_D1_1K 130 +#define BH1730_LUXTH1_1K 260 +#define BH1730_LUXTH1_D0_1K 1290 +#define BH1730_LUXTH1_D1_1K 2733 +#define BH1730_LUXTH2_1K 550 +#define BH1730_LUXTH2_D0_1K 797 +#define BH1730_LUXTH2_D1_1K 859 +#define BH1730_LUXTH3_1K 1090 +#define BH1730_LUXTH3_D0_1K 510 +#define BH1730_LUXTH3_D1_1K 345 +#define BH1730_LUXTH4_1K 2130 +#define BH1730_LUXTH4_D0_1K 276 +#define BH1730_LUXTH4_D1_1K 130 #endif -#define BH1730_GET_DATA(_s) ((struct bh1730_drv_data_t *)(_s)->drv_data) +#define BH1730_GET_DATA(_s) ((struct bh1730_drv_data_t *)(_s)->drv_data) struct bh1730_drv_data_t { int rate; @@ -93,4 +93,4 @@ struct bh1730_drv_data_t { extern const struct accelgyro_drv bh1730_drv; -#endif /* __CROS_EC_ALS_BH1730_H */ +#endif /* __CROS_EC_ALS_BH1730_H */ -- cgit v1.2.1 From de7c2884da46847367f5e8156e95d2186864dcc2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:06 -0600 Subject: include/espi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia54e136b51aa252f5e056e924e18aaf0255cb13c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730263 Reviewed-by: Jeremy Bettis --- include/espi.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/include/espi.h b/include/espi.h index a717e7e414..f5f23001fe 100644 --- a/include/espi.h +++ b/include/espi.h @@ -14,29 +14,29 @@ enum espi_vw_signal { /* The first valid VW signal is 0x2000 */ VW_SIGNAL_START = IOEX_LIMIT + 1, - VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In) */ + VW_SLP_S3_L = VW_SIGNAL_START, /* index 02h (In) */ VW_SLP_S4_L, VW_SLP_S5_L, - VW_SUS_STAT_L, /* index 03h (In) */ + VW_SUS_STAT_L, /* index 03h (In) */ VW_PLTRST_L, VW_OOB_RST_WARN, - VW_OOB_RST_ACK, /* index 04h (Out) */ + VW_OOB_RST_ACK, /* index 04h (Out) */ VW_WAKE_L, VW_PME_L, - VW_ERROR_FATAL, /* index 05h (Out) */ + VW_ERROR_FATAL, /* index 05h (Out) */ VW_ERROR_NON_FATAL, /* Merge bit 3/0 into one signal. Need to set them simultaneously */ VW_PERIPHERAL_BTLD_STATUS_DONE, - VW_SCI_L, /* index 06h (Out) */ + VW_SCI_L, /* index 06h (Out) */ VW_SMI_L, VW_RCIN_L, VW_HOST_RST_ACK, - VW_HOST_RST_WARN, /* index 07h (In) */ - VW_SUS_ACK, /* index 40h (Out) */ - VW_SUS_WARN_L, /* index 41h (In) */ + VW_HOST_RST_WARN, /* index 07h (In) */ + VW_SUS_ACK, /* index 40h (Out) */ + VW_SUS_WARN_L, /* index 41h (In) */ VW_SUS_PWRDN_ACK_L, VW_SLP_A_L, - VW_SLP_LAN, /* index 42h (In) */ + VW_SLP_LAN, /* index 42h (In) */ VW_SLP_WLAN, VW_SIGNAL_END, VW_LIMIT = 0x2FFF @@ -99,6 +99,6 @@ int espi_signal_is_vw(int signal); * @param timeout max time in microseconds to poll. */ void espi_wait_vw_not_dirty(enum espi_vw_signal signal, - unsigned int timeout_us); + unsigned int timeout_us); -#endif /* __CROS_EC_ESPI_H */ +#endif /* __CROS_EC_ESPI_H */ -- cgit v1.2.1 From f1d43d953ca5a371497f0c1138fd5259f38a6ff9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:00 -0600 Subject: chip/stm32/flash-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I64644fd602454da8338dbc10912e5c4f2f5f1984 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729501 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32l.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index f34200219a..592f8f50bf 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -34,7 +34,8 @@ static void lock(void) ignore_bus_fault(1); STM32_FLASH_PECR = STM32_FLASH_PECR_PE_LOCK | - STM32_FLASH_PECR_PRG_LOCK | STM32_FLASH_PECR_OPT_LOCK; + STM32_FLASH_PECR_PRG_LOCK | + STM32_FLASH_PECR_OPT_LOCK; ignore_bus_fault(0); } @@ -105,8 +106,8 @@ static uint16_t read_optb(int offset) */ static void write_optb(int offset, uint16_t value) { - REG32(STM32_OPTB_BASE + offset) = - (uint32_t)value | ((uint32_t)(~value) << 16); + REG32(STM32_OPTB_BASE + offset) = (uint32_t)value | + ((uint32_t)(~value) << 16); } /** @@ -115,7 +116,7 @@ static void write_optb(int offset, uint16_t value) static uint32_t read_optb_wrp(void) { return read_optb(STM32_OPTB_WRP1L) | - ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); + ((uint32_t)read_optb(STM32_OPTB_WRP1H) << 16); } /** @@ -133,8 +134,8 @@ static void write_optb_wrp(uint32_t value) * This function lives in internal RAM, as we cannot read flash during writing. * You must not call other functions from this one or declare it static. */ -void __attribute__((section(".iram.text"))) - iram_flash_write(uint32_t *addr, uint32_t *data) +void __attribute__((section(".iram.text"))) +iram_flash_write(uint32_t *addr, uint32_t *data) { int i; @@ -189,7 +190,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* Update flash timeout based on current clock speed */ flash_timeout_loop = FLASH_TIMEOUT_MS * (clock_get_freq() / MSEC) / - CYCLE_PER_FLASH_LOOP; + CYCLE_PER_FLASH_LOOP; while (size > 0) { /* @@ -204,7 +205,8 @@ int crec_flash_physical_write(int offset, int size, const char *data) /* Wait for writes to complete */ for (i = 0; ((STM32_FLASH_SR & 9) != 8) && - (i < flash_timeout_loop); i++) + (i < flash_timeout_loop); + i++) ; size -= sizeof(uint32_t); @@ -257,13 +259,13 @@ int crec_flash_physical_erase(int offset, int size) for (address = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); size > 0; size -= CONFIG_FLASH_ERASE_SIZE, - address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { + address += CONFIG_FLASH_ERASE_SIZE / sizeof(uint32_t)) { timestamp_t deadline; /* Do nothing if already erased */ if (crec_flash_is_erased((uint32_t)address - - CONFIG_PROGRAM_MEMORY_BASE, - CONFIG_FLASH_ERASE_SIZE)) + CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_FLASH_ERASE_SIZE)) continue; /* Start erase */ @@ -336,7 +338,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) prot &= ~mask; if (prot == read_optb_wrp()) - return EC_SUCCESS; /* No bits changed */ + return EC_SUCCESS; /* No bits changed */ /* Unlock option bytes */ rv = unlock(STM32_FLASH_PECR_OPT_LOCK); @@ -402,8 +404,7 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -458,7 +459,7 @@ int crec_flash_pre_init(void) * Set it back to a good state and reboot. */ crec_flash_protect_at_boot(prot_flags & - EC_FLASH_PROTECT_RO_AT_BOOT); + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else if (prot_flags & (EC_FLASH_PROTECT_RO_NOW | -- cgit v1.2.1 From c29af88682e45897ca9abfbe5e39102bcbe1e199 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:14 -0600 Subject: board/volmar/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4340489d62a2fbb1627ddf8db03f8889250073c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729088 Reviewed-by: Jeremy Bettis --- board/volmar/usbc_config.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/volmar/usbc_config.c b/board/volmar/usbc_config.c index 5f70a16c21..23ed58fa54 100644 --- a/board/volmar/usbc_config.c +++ b/board/volmar/usbc_config.c @@ -34,8 +34,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -156,8 +156,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -177,7 +177,6 @@ void config_usb_db_type(void) CPRINTS("Configured USB DB type number is %d", db_type); } - void board_reset_pd_mcu(void) { /* -- cgit v1.2.1 From 8d15248f6cc67da3be667915ad6b8c8e684ad976 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:17 -0600 Subject: board/kodama/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I832a15b6500218b98c7d68286b5954832dfaea35 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728561 Reviewed-by: Jeremy Bettis --- board/kodama/board.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/board/kodama/board.h b/board/kodama/board.h index de953cba0b..9bfc0ff89f 100644 --- a/board/kodama/board.h +++ b/board/kodama/board.h @@ -15,7 +15,6 @@ #define VARIANT_KUKUI_TABLET_PWRBTN #undef CONFIG_CMD_MFALLOW - #ifndef SECTION_IS_RW #define VARIANT_KUKUI_NO_SENSORS #endif /* SECTION_IS_RW */ @@ -39,7 +38,7 @@ #define CONFIG_SMBUS_PEC /* Battery */ -#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */ +#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */ #define CONFIG_CHARGER_MT6370_BACKLIGHT #define CONFIG_CHARGER_MAINTAIN_VBAT @@ -53,19 +52,18 @@ /* Camera VSYNC */ #define CONFIG_SYNC #define CONFIG_SYNC_COMMAND -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #endif /* SECTION_IS_RW */ /* Disable verbose output in EC pd */ #define CONFIG_CMD_PD_SRCCAPS_REDUCED_SIZE /* I2C ports */ -#define I2C_PORT_CHARGER 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_ACCEL 1 -#define I2C_PORT_BATTERY board_get_battery_i2c() +#define I2C_PORT_CHARGER 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_ACCEL 1 +#define I2C_PORT_BATTERY board_get_battery_i2c() #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* Define the host events which are allowed to wakeup AP in S3. */ -- cgit v1.2.1 From 0bab203837b56aa65b37347f0f2d06e3ec641cbd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:59 -0600 Subject: chip/stm32/keyboard_raw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d18d7fc4a6630e9b43d22fa5dc8694d73395b63 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729404 Reviewed-by: Jeremy Bettis --- chip/stm32/keyboard_raw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/stm32/keyboard_raw.c b/chip/stm32/keyboard_raw.c index 219676968a..7da32a365b 100644 --- a/chip/stm32/keyboard_raw.c +++ b/chip/stm32/keyboard_raw.c @@ -86,12 +86,12 @@ test_mockable void keyboard_raw_drive_column(int out) } } - #ifdef CONFIG_KEYBOARD_COL2_INVERTED +#ifdef CONFIG_KEYBOARD_COL2_INVERTED if (bsrr & (gpio_list[GPIO_KB_OUT02].mask << 16 | - gpio_list[GPIO_KB_OUT02].mask)) + gpio_list[GPIO_KB_OUT02].mask)) bsrr ^= (gpio_list[GPIO_KB_OUT02].mask << 16 | gpio_list[GPIO_KB_OUT02].mask); - #endif +#endif if (bsrr) STM32_GPIO_BSRR(kb_out_ports[i]) = bsrr; @@ -131,9 +131,9 @@ void keyboard_raw_enable_interrupt(int enable) * Clear them before enable interrupt. */ STM32_EXTI_PR |= irq_mask; - STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ + STM32_EXTI_IMR |= irq_mask; /* 1: unmask interrupt */ } else { - STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ + STM32_EXTI_IMR &= ~irq_mask; /* 0: mask interrupts */ } } -- cgit v1.2.1 From 69f83881bb43d4163702568eeb575b4fe3486b36 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:04 -0600 Subject: chip/npcx/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife59f77792f4de1e5298d0da8fe403cd5755ada3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729381 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio.c | 72 +++++++++++++++++++++++++++----------------------------- 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 5f1e3c78b6..55310b1ebf 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -25,7 +25,7 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_GPIO, outstr) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) #endif /* Constants for GPIO interrupt mapping */ @@ -40,12 +40,12 @@ #define UNIMPLEMENTED(name) #endif static const struct npcx_wui gpio_wui_table[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; struct npcx_gpio { - uint8_t port : 4; - uint8_t bit : 3; + uint8_t port : 4; + uint8_t bit : 3; uint8_t valid : 1; }; @@ -54,21 +54,21 @@ BUILD_ASSERT(sizeof(struct npcx_gpio) == 1); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 struct npcx_alt { uint8_t group; - uint8_t bit : 3; - uint8_t inverted : 1; - uint8_t reserved : 4; + uint8_t bit : 3; + uint8_t inverted : 1; + uint8_t reserved : 4; }; #else struct npcx_alt { - uint8_t group : 4; - uint8_t bit : 3; - uint8_t inverted : 1; + uint8_t group : 4; + uint8_t bit : 3; + uint8_t inverted : 1; }; #endif struct gpio_alt_map { struct npcx_gpio gpio; - struct npcx_alt alt; + struct npcx_alt alt; }; #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 @@ -101,8 +101,7 @@ static uint8_t gpio_is_alt_sel(uint8_t port, uint8_t bit) struct gpio_alt_map const *map; uint8_t alt_mask, devalt; - for (map = ARRAY_BEGIN(gpio_alt_table); - map < ARRAY_END(gpio_alt_table); + for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table); map++) { if (gpio_match(port, bit, map->gpio)) { alt_mask = 1 << map->alt.bit; @@ -127,8 +126,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, { struct gpio_alt_map const *map; - for (map = ARRAY_BEGIN(gpio_alt_table); - map < ARRAY_END(gpio_alt_table); + for (map = ARRAY_BEGIN(gpio_alt_table); map < ARRAY_END(gpio_alt_table); map++) { if (gpio_match(port, bit, map->gpio)) { uint8_t alt_mask = 1 << map->alt.bit; @@ -140,7 +138,7 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, if ((func < GPIO_ALT_FUNC_DEFAULT) ^ map->alt.inverted) NPCX_DEVALT(map->alt.group) &= ~alt_mask; else - NPCX_DEVALT(map->alt.group) |= alt_mask; + NPCX_DEVALT(map->alt.group) |= alt_mask; return 1; } @@ -183,7 +181,7 @@ static void gpio_interrupt_type_sel(enum gpio_signal signal, uint32_t flags) NPCX_WKMOD(table, group) &= ~pmask; /* Handle interrupting on both edges */ if ((flags & GPIO_INT_F_RISING) && - (flags & GPIO_INT_F_FALLING)) { + (flags & GPIO_INT_F_FALLING)) { /* Enable any edge */ NPCX_WKAEDG(table, group) |= pmask; } @@ -252,7 +250,7 @@ void gpio_low_voltage_level_sel(uint8_t port, uint8_t bit, uint8_t low_voltage) if (low_voltage) CPRINTS("Warn! No low voltage support in port:0x%x, bit:%d", - port, bit); + port, bit); } /* Set the low voltage detection level by mask */ @@ -290,7 +288,7 @@ static void gpio_enable_wake_up_input(enum gpio_signal signal, int enable) SET_BIT(NPCX_WKINEN(wui->table, wui->group), wui->bit); else CLEAR_BIT(NPCX_WKINEN(wui->table, wui->group), - wui->bit); + wui->bit); } } @@ -317,7 +315,7 @@ BUILD_ASSERT(ARRAY_SIZE(gpio_lvol_table[0].lvol_gpio) == 8); /* IC specific low-level driver */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* Enable alternative pins by func */ int pin; @@ -340,7 +338,7 @@ void gpio_set_level(enum gpio_signal signal, int value) ASSERT(signal_is_gpio(signal)); if (value) - NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask; + NPCX_PDOUT(gpio_list[signal].port) |= gpio_list[signal].mask; else NPCX_PDOUT(gpio_list[signal].port) &= ~gpio_list[signal].mask; } @@ -410,14 +408,14 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) if (flags & GPIO_PULL_UP) { if (flags & GPIO_SEL_1P8V) { CPRINTS("Warn! enable internal PU and low voltage mode" - " at the same time is illegal. port 0x%x, mask 0x%x", - port, mask); + " at the same time is illegal. port 0x%x, mask 0x%x", + port, mask); } else { - NPCX_PPUD(port) &= ~mask; + NPCX_PPUD(port) &= ~mask; NPCX_PPULL(port) |= mask; /* enable pull down/up */ } } else if (flags & GPIO_PULL_DOWN) { - NPCX_PPUD(port) |= mask; + NPCX_PPUD(port) |= mask; NPCX_PPULL(port) |= mask; /* enable pull down/up */ } else { /* No pull up/down */ @@ -455,7 +453,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) if (flags & GPIO_OUTPUT) NPCX_PDIR(port) |= mask; - /* Lock GPIO output and configuration if need */ + /* Lock GPIO output and configuration if need */ #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 if (flags & GPIO_LOCKED) NPCX_PLOCK_CTL(port) |= mask; @@ -598,7 +596,7 @@ void gpio_pre_init(void) * which may or may not be as a GPIO. */ gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); + GPIO_ALT_FUNC_NONE); } /* The bypass of low voltage IOs for better power consumption */ @@ -649,8 +647,8 @@ void gpio_interrupt(struct npcx_wui wui_int) uint8_t pin_mask = 1 << gpio_wui_table[i].bit; if ((gpio_wui_table[i].table == table) && - (gpio_wui_table[i].group == group) && - (wui_mask & pin_mask)) { + (gpio_wui_table[i].group == group) && + (wui_mask & pin_mask)) { /* Clear pending bit of GPIO */ NPCX_WKPCL(table, group) = pin_mask; /* Execute GPIO's ISR */ @@ -691,7 +689,7 @@ static int command_gpiodisable(int argc, char **argv) ccprintf("Total GPIO declaration: %d\n", GPIO_COUNT); ccprintf("Total Non-ISR GPIO declaration: %d\n", - non_isr_gpio_num); + non_isr_gpio_num); ccprintf("Next GPIO Num to check by "); ccprintf("\"gpiodisable next\"\n"); ccprintf(" offset: %d\n", offset); @@ -714,8 +712,8 @@ static int command_gpiodisable(int argc, char **argv) offset = idx + GPIO_IH_COUNT; g_list = gpio_list + offset; flags = g_list->flags; - ccprintf("current GPIO : %d %s --> ", - offset, g_list->name); + ccprintf("current GPIO : %d %s --> ", offset, + g_list->name); if (gpio_is_i2c_pin(offset)) { ccprintf("Ignore I2C pin!\n"); idx++; @@ -726,10 +724,10 @@ static int command_gpiodisable(int argc, char **argv) continue; } else { if ((flags & GPIO_INPUT) || - (flags & GPIO_OPEN_DRAIN)) { + (flags & GPIO_OPEN_DRAIN)) { ccprintf("Disable WKINEN!\n"); gpio_enable_wake_up_input( - offset, 0); + offset, 0); idx++; break; } @@ -759,7 +757,7 @@ static int command_gpiodisable(int argc, char **argv) } return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(gpiodisable, command_gpiodisable, - "info/list/next/ on|off", - "Disable GPIO input buffer to investigate power consumption"); +DECLARE_CONSOLE_COMMAND( + gpiodisable, command_gpiodisable, "info/list/next/ on|off", + "Disable GPIO input buffer to investigate power consumption"); #endif -- cgit v1.2.1 From f96060a9292da7c4fef06669b10158483af391ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:15 -0600 Subject: chip/npcx/apm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idcc9c6f2bd8f272626f5e259ce629c6908e9a07c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729365 Reviewed-by: Jeremy Bettis --- chip/npcx/apm.c | 77 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/chip/npcx/apm.c b/chip/npcx/apm.c index 4ab64774c1..88a782cd97 100644 --- a/chip/npcx/apm.c +++ b/chip/npcx/apm.c @@ -12,13 +12,12 @@ #include "wov_chip.h" static struct apm_config apm_conf; -static struct apm_auto_gain_config apm_gain_conf; - +static struct apm_auto_gain_config apm_gain_conf; static uint32_t apm_indirect_reg[][3] = { - {(NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038)}, - {(NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050)}, - {(NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060)} + { (NPCX_APM_BASE_ADDR + 0x034), (NPCX_APM_BASE_ADDR + 0x038) }, + { (NPCX_APM_BASE_ADDR + 0x04C), (NPCX_APM_BASE_ADDR + 0x050) }, + { (NPCX_APM_BASE_ADDR + 0x05C), (NPCX_APM_BASE_ADDR + 0x060) } }; #define APM_CNTRL_REG 0 @@ -37,11 +36,11 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset, { /* Set the indirect access address. */ SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_ADD, indirect_addr); + NPCX_APM_CONTROL_ADD, indirect_addr); /* Read command. */ CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); /* Get the data. */ return REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]); @@ -57,20 +56,20 @@ static uint8_t apm_read_indirect_data(enum apm_indirect_reg_offset reg_offset, * @return None */ static void apm_write_indirect_data(enum apm_indirect_reg_offset reg_offset, - uint8_t indirect_addr, uint8_t value) + uint8_t indirect_addr, uint8_t value) { /* Set the data. */ REG8(apm_indirect_reg[reg_offset][APM_DATA_REG]) = value; /* Set the indirect access address. */ SET_FIELD(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_ADD, indirect_addr); + NPCX_APM_CONTROL_ADD, indirect_addr); /* Write command. */ SET_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); CLEAR_BIT(REG8(apm_indirect_reg[reg_offset][APM_CNTRL_REG]), - NPCX_APM_CONTROL_LOAD); + NPCX_APM_CONTROL_LOAD); } /** @@ -83,13 +82,13 @@ void apm_set_adc_dmic_config_l(enum apm_dmic_rate rate) { if (rate == APM_DMIC_RATE_0_75) SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - APM_DMIC_RATE_3_0); + APM_DMIC_RATE_3_0); else if (rate == APM_DMIC_RATE_1_2) SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - APM_DMIC_RATE_2_4); + APM_DMIC_RATE_2_4); else SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_RATE, - rate); + rate); } /** @@ -108,7 +107,7 @@ void apm_set_vad_dmic_rate_l(enum apm_dmic_rate rate) /* Set VAD_0 register. */ if (rate == APM_DMIC_RATE_0_75) SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, - APM_DMIC_RATE_3_0); + APM_DMIC_RATE_3_0); else if (rate == APM_DMIC_RATE_1_2) SET_FIELD(vad_data, NPCX_VAD_0_VAD_DMIC_FREQ, APM_DMIC_RATE_2_4); @@ -172,15 +171,15 @@ void apm_init(void) apm_conf.left_chan_gain = 0; apm_conf.right_chan_gain = 0; - apm_gain_conf.stereo_enable = 0; - apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5; - apm_gain_conf.nois_gate_en = 0; + apm_gain_conf.stereo_enable = 0; + apm_gain_conf.agc_target = APM_ADC_MAX_TARGET_LEVEL_19_5; + apm_gain_conf.nois_gate_en = 0; apm_gain_conf.nois_gate_thold = APM_MIN_NOISE_GET_THRESHOLD; - apm_gain_conf.hold_time = APM_HOLD_TIME_128; - apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160; - apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160; - apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5; - apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0; + apm_gain_conf.hold_time = APM_HOLD_TIME_128; + apm_gain_conf.attack_time = APM_GAIN_RAMP_TIME_160; + apm_gain_conf.decay_time = APM_GAIN_RAMP_TIME_160; + apm_gain_conf.gain_max = APM_GAIN_VALUE_42_5; + apm_gain_conf.gain_min = APM_GAIN_VALUE_0_0; } /** @@ -226,11 +225,11 @@ void apm_enable_vad_interrupt(int enable) void apm_adc_wov_enable(int enable) { if (enable) { - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x00); } else { - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x03); } } @@ -244,12 +243,12 @@ void apm_adc_enable(int enable) { if (enable) { CLEAR_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC); - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x00); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x00); } else { SET_BIT(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_PD_AICR_ADC); - SET_FIELD(NPCX_APM_AICR_ADC, - NPCX_APM_AICR_ADC_ADC_AUDIOIF, 0x03); + SET_FIELD(NPCX_APM_AICR_ADC, NPCX_APM_AICR_ADC_ADC_AUDIOIF, + 0x03); } } @@ -273,8 +272,8 @@ void apm_adc_set_freq(enum apm_adc_frequency adc_freq) * @return None */ void apm_adc_config(int hpf_enable, - enum apm_adc_wind_noise_filter_mode filter_mode, - enum apm_adc_frequency adc_freq) + enum apm_adc_wind_noise_filter_mode filter_mode, + enum apm_adc_frequency adc_freq) { if (hpf_enable) SET_BIT(NPCX_APM_FCR_ADC, NPCX_APM_FCR_ADC_ADC_HPF); @@ -491,7 +490,8 @@ void apm_vad_restart(void) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list apm_adc_gain_config(enum apm_adc_gain_coupling gain_coupling, - uint8_t left_chan_gain, uint8_t right_chan_gain) + uint8_t left_chan_gain, + uint8_t right_chan_gain) { /* Check parameters validity. */ if ((left_chan_gain > 0x2B) || (right_chan_gain > 0x2B)) @@ -538,8 +538,8 @@ void apm_auto_gain_cntrl_enable(int enable) * @param gain_cfg - struct of apm auto gain config * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list apm_adc_auto_gain_config( - struct apm_auto_gain_config *gain_cfg) +enum ec_error_list +apm_adc_auto_gain_config(struct apm_auto_gain_config *gain_cfg) { uint8_t gain_data = 0; @@ -668,9 +668,8 @@ void apm_set_mode(enum wov_modes wov_mode) break; } - apm_adc_gain_config(apm_conf.gain_coupling, - apm_conf.left_chan_gain, - apm_conf.right_chan_gain); + apm_adc_gain_config(apm_conf.gain_coupling, apm_conf.left_chan_gain, + apm_conf.right_chan_gain); apm_adc_auto_gain_config(&apm_gain_conf); -- cgit v1.2.1 From d5645208c83b227250fe09cc5c4b31b316a314d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:31 -0600 Subject: board/servo_v4/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b34209196c024ca48faa4298bd2ba09de8ec478 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728927 Reviewed-by: Jeremy Bettis --- board/servo_v4/usb_pd_policy.c | 218 ++++++++++++++++++++--------------------- 1 file changed, 105 insertions(+), 113 deletions(-) diff --git a/board/servo_v4/usb_pd_policy.c b/board/servo_v4/usb_pd_policy.c index 61931cda8b..4e67d6ecf2 100644 --- a/board/servo_v4/usb_pd_policy.c +++ b/board/servo_v4/usb_pd_policy.c @@ -28,55 +28,55 @@ #include "usb_pd_pdo.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define DUT_PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) -#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new) +#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new) /* Macros to config the PD role */ #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear)) -#define CONF_SRC(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_SNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP) -#define CONF_DRP(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_SNK_WITH_PD) -#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \ - 0, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \ - CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) -#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SRC(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_SNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_PDSNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP) +#define CONF_DRP(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_SNK_WITH_PD) +#define CONF_SRCDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SNKDTS(c) \ + CONF_SET_CLEAR(c, 0, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \ + CC_SNK_WITH_PD) +#define CONF_PDSNKDTS(c) \ + CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) +#define CONF_DRPDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_DISABLE_DTS | CC_SNK_WITH_PD) /* Macros to apply Rd/Rp to CC lines */ -#define DUT_ACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC2_, r) : \ - CONCAT2(GPIO_USB_DUT_CC1_, r), \ +#define DUT_ACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC2_, r) : \ + CONCAT2(GPIO_USB_DUT_CC1_, r), \ flags) -#define DUT_INACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC1_, r) : \ - CONCAT2(GPIO_USB_DUT_CC2_, r), \ +#define DUT_INACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC1_, r) : \ + CONCAT2(GPIO_USB_DUT_CC2_, r), \ flags) -#define DUT_BOTH_CC_SET(r, flags) \ - do { \ +#define DUT_BOTH_CC_SET(r, flags) \ + do { \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \ } while (0) @@ -94,15 +94,15 @@ static int cc_config = CC_ALLOW_SRC; /* Voltage thresholds for no connect in DTS mode */ static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV}, - {PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV}, - {PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV}, + { PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV }, + { PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV }, + { PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV }, }; /* Voltage thresholds for Ra attach in DTS mode */ static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV}, - {PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV }, + { PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, }; /* Voltage thresholds for no connect in normal SRC mode */ static int pd_src_vnc[TYPEC_RP_RESERVED] = { @@ -139,7 +139,8 @@ static uint8_t allow_dr_swap = 1; static uint32_t max_supported_voltage(void) { int board_max_mv = board_get_version() >= BOARD_VERSION_BLACK ? - PD_MAX_VOLTAGE_MV : MAX_MV_RED_BLUE; + PD_MAX_VOLTAGE_MV : + MAX_MV_RED_BLUE; return board_max_mv < user_limited_max_mv ? board_max_mv : user_limited_max_mv; @@ -263,8 +264,8 @@ static void update_ports(void) break; /* Find the 'best' PDO <= voltage */ - pdo_index = - pd_find_pdo_index(pd_get_src_cap_cnt(CHG), + pdo_index = pd_find_pdo_index( + pd_get_src_cap_cnt(CHG), pd_get_src_caps(CHG), pd_src_voltages_mv[i], &pdo); /* Don't duplicate PDOs */ @@ -287,9 +288,9 @@ static void update_ports(void) } else { /* 5V PDO */ pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) | - PDO_FIXED_CURR(vbus[CHG].ma) | - DUT_PDO_FIXED_FLAGS | - PDO_FIXED_UNCONSTRAINED; + PDO_FIXED_CURR(vbus[CHG].ma) | + DUT_PDO_FIXED_FLAGS | + PDO_FIXED_UNCONSTRAINED; chg_pdo_cnt = 1; } @@ -314,8 +315,8 @@ int board_set_active_charge_port(int charge_port) return 0; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { if (port != CHG) return; @@ -361,8 +362,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) nc = cc_volt >= pd_src_vnc[rp_index]; else - nc = cc_volt >= pd_src_vnc_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + nc = cc_volt >= + pd_src_vnc_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : cc_sel]; return nc; } @@ -388,8 +390,10 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) ra = cc_volt < pd_src_rd_threshold[rp_index]; else - ra = cc_volt < pd_src_rd_threshold_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + ra = cc_volt < + pd_src_rd_threshold_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : + cc_sel]; return ra; } @@ -548,7 +552,6 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value) DUT_ACTIVE_CC_PD(RD); else DUT_BOTH_CC_PD(RD); - } rp_value_stored = rp_value; @@ -591,8 +594,7 @@ __override void pd_transition_voltage(int idx) /* Wait for CHG transition */ deadline.val = get_time().val + PD_T_PS_TRANSITION; CPRINTS("Waiting for CHG port transition"); - while (charge_port_is_active() && - vbus[CHG].mv != mv && + while (charge_port_is_active() && vbus[CHG].mv != mv && get_time().val < deadline.val) msleep(10); @@ -652,9 +654,7 @@ void pd_power_supply_reset(int port) int pd_snk_is_vbus_provided(int port) { - - return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : - GPIO_USB_DET_PP_CHG); + return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG); } __override int pd_check_power_swap(int port) @@ -671,7 +671,8 @@ __override int pd_check_power_swap(int port) if (port == CHG) return 0; - if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC)) + if (pd_get_power_role(port) == PD_ROLE_SINK && + !(cc_config & CC_ALLOW_SRC)) return 0; if (pd_snk_is_vbus_provided(CHG)) @@ -680,8 +681,7 @@ __override int pd_check_power_swap(int port) return 0; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* * Servo should allow data role swaps to let DUT see the USB hub, but @@ -693,8 +693,7 @@ __override int pd_check_data_swap(int port, return allow_dr_swap; } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* * TODO(b/137887386): Turn on the fastboot/DFU path when data swap to @@ -702,8 +701,7 @@ __override void pd_execute_data_swap(int port, */ } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { /* @@ -714,9 +712,7 @@ __override void pd_check_pr_role(int port, */ } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { if (port == CHG) return; @@ -726,15 +722,14 @@ __override void pd_check_dr_role(int port, pd_request_data_swap(port); } - /* ----------------- Vendor Defined Messages ------------------ */ /* * DP alt-mode config, user configurable. * Default is the mode disabled, supporting the C and D pin assignment, * multi-function preferred, and a plug. */ -static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | - ALT_DP_PLUG); +static int alt_dp_config = + (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG); /** * Get the pins based on the user config. @@ -769,8 +764,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 0, /* Vbus power required */ @@ -808,13 +803,13 @@ uint32_t vdo_dp_mode[MODE_CNT]; static int svdm_response_modes(int port, uint32_t *payload) { - vdo_dp_mode[0] = - VDO_MODE_DP(0, /* UFP pin cfg supported: none */ - alt_dp_config_pins(), /* DFP pin */ - 1, /* no usb2.0 signalling in AMode */ - alt_dp_config_cable(), /* plug or receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK); /* Its a sink only */ + vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */ + alt_dp_config_pins(), /* DFP pin */ + 1, /* no usb2.0 signalling in AMode */ + alt_dp_config_cable(), /* plug or + receptacle */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK); /* Its a sink only */ /* CCD uses the SBU lines; don't enable DP when dts-mode enabled */ if (!(cc_config & CC_DISABLE_DTS)) @@ -881,17 +876,17 @@ static int dp_status(int port, uint32_t *payload) int hpd = get_hpd_level(); if (opos != OPOS) - return 0; /* NAK */ - - payload[1] = VDO_DP_STATUS( - 0, /* IRQ_HPD */ - hpd, /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF pref */ - is_typec_dp_muxed(), - 0, /* power low */ - hpd ? 0x2 : 0); + return 0; /* NAK */ + + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + hpd, /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF + pref + */ + is_typec_dp_muxed(), 0, /* power low */ + hpd ? 0x2 : 0); return 2; } @@ -911,7 +906,7 @@ static int svdm_enter_mode(int port, uint32_t *payload) /* SID & mode request is valid */ if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) || (PD_VDO_OPOS(payload[0]) != OPOS)) - return 0; /* NAK */ + return 0; /* NAK */ alt_mode = OPOS; return 1; @@ -950,7 +945,7 @@ const struct svdm_response svdm_rsp = { }; __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { int cmd = PD_VDO_CMD(payload[0]); @@ -962,7 +957,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, case VDO_CMD_VERSION: /* guarantee last byte of payload is null character */ *(payload + cnt - 1) = 0; - CPRINTF("ver: %s\n", (char *)(payload+1)); + CPRINTF("ver: %s\n", (char *)(payload + 1)); break; case VDO_CMD_CURRENT: CPRINTF("Current: %dmA\n", payload[1]); @@ -984,12 +979,10 @@ static void print_cc_mode(void) gpio_get_level(GPIO_DUT_CHG_EN) ? "on" : "off"); ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off"); ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off"); - ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : - "cc1"); + ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1"); ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off"); } - static void do_cc(int cc_config_new) { int chargeable; @@ -1150,8 +1143,8 @@ static int cmd_fake_disconnect(int argc, char *argv[]) fake_pd_disconnect_duration_us = duration_ms * MSEC; hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC); - ccprintf("Fake disconnect for %d ms starting in %d ms.\n", - duration_ms, delay_ms); + ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms, + delay_ms); return EC_SUCCESS; } @@ -1161,7 +1154,7 @@ DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect, static int cmd_ada_srccaps(int argc, char *argv[]) { int i; - const uint32_t * const ada_srccaps = pd_get_src_caps(CHG); + const uint32_t *const ada_srccaps = pd_get_src_caps(CHG); for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) { uint32_t max_ma, max_mv, unused; @@ -1176,8 +1169,7 @@ static int cmd_ada_srccaps(int argc, char *argv[]) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, - "", +DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "", "Print adapter SrcCap"); static int cmd_dp_action(int argc, char *argv[]) @@ -1199,8 +1191,8 @@ static int cmd_dp_action(int argc, char *argv[]) alt_dp_config &= ~ALT_DP_ENABLE; } else if (!strcasecmp(argv[1], "pins")) { if (argc >= 3) { - alt_dp_config &= ~(ALT_DP_PIN_C | ALT_DP_PIN_D | - ALT_DP_PIN_E); + alt_dp_config &= + ~(ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_PIN_E); for (i = 0; i < 3; i++) { if (!argv[2][i]) break; @@ -1273,10 +1265,10 @@ static int cmd_dp_action(int argc, char *argv[]) } } CPRINTS("HPD source: %s", - (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" - : "external"); + (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" : + "external"); CPRINTS("HPD level: %d", get_hpd_level()); - } else if (!strcasecmp(argv[1], "help")) { + } else if (!strcasecmp(argv[1], "help")) { CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|" "plug]"); } -- cgit v1.2.1 From bff3bf984241ba646f720261e6ca0b1f368b79a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:30 -0600 Subject: util/comm-lpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8deb7cde63e6ad2a2e05fb31bc22af3049d9633 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730326 Reviewed-by: Jeremy Bettis --- util/comm-lpc.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/util/comm-lpc.c b/util/comm-lpc.c index d1ce761fc2..41a9a11e84 100644 --- a/util/comm-lpc.c +++ b/util/comm-lpc.c @@ -14,7 +14,7 @@ #include "comm-host.h" -#define INITIAL_UDELAY 5 /* 5 us */ +#define INITIAL_UDELAY 5 /* 5 us */ #define MAXIMUM_UDELAY 10000 /* 10 ms */ /* @@ -43,12 +43,11 @@ static int wait_for_ec(int status_addr, int timeout_usec) if (i > 20) delay = MIN(delay * 2, MAXIMUM_UDELAY); } - return -1; /* Timeout */ + return -1; /* Timeout */ } -static int ec_command_lpc(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_lpc(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { struct ec_lpc_host_args args; const uint8_t *d; @@ -112,8 +111,7 @@ static int ec_command_lpc(int command, int version, csum = command + args.flags + args.command_version + args.data_size; /* Read response and update checksum */ - for (i = 0, dout = (uint8_t *)indata; i < args.data_size; - i++, dout++) { + for (i = 0, dout = (uint8_t *)indata; i < args.data_size; i++, dout++) { *dout = inb(EC_LPC_ADDR_HOST_PARAM + i); csum += *dout; } @@ -128,9 +126,8 @@ static int ec_command_lpc(int command, int version, return args.data_size; } -static int ec_command_lpc_3(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_lpc_3(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { struct ec_host_request rq; struct ec_host_response rs; @@ -231,10 +228,10 @@ static int ec_readmem_lpc(int offset, int bytes, void *dest) if (offset >= EC_MEMMAP_SIZE - bytes) return -1; - if (bytes) { /* fixed length */ + if (bytes) { /* fixed length */ for (; cnt < bytes; i++, s++, cnt++) *s = inb(EC_LPC_ADDR_MEMMAP + i); - } else { /* string */ + } else { /* string */ for (; i < EC_MEMMAP_SIZE; i++, s++) { *s = inb(EC_LPC_ADDR_MEMMAP + i); cnt++; @@ -294,9 +291,9 @@ int comm_init_lpc(void) /* Protocol version 3 */ ec_command_proto = ec_command_lpc_3; ec_max_outsize = EC_LPC_HOST_PACKET_SIZE - - sizeof(struct ec_host_request); + sizeof(struct ec_host_request); ec_max_insize = EC_LPC_HOST_PACKET_SIZE - - sizeof(struct ec_host_response); + sizeof(struct ec_host_response); } else if (i & EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED) { /* Protocol version 2 */ -- cgit v1.2.1 From 99e98cf2c9bd37a074e5ea3d95182b0b3cb188e8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:43 -0600 Subject: board/delbin/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f7b24d7c209f1ed6847cdf78fff5ebf5bc53fb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728221 Reviewed-by: Jeremy Bettis --- board/delbin/led.c | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/board/delbin/led.c b/board/delbin/led.c index d7c1df491f..aa7295e4c5 100644 --- a/board/delbin/led.c +++ b/board/delbin/led.c @@ -17,29 +17,37 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 9140b096f923155eeaa0844baf908edeb2c9d94e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:48 -0600 Subject: common/mock/charge_manager_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id058c3aa2481e0c20091e7b41529a9ce15a8748e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729674 Reviewed-by: Jeremy Bettis --- common/mock/charge_manager_mock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/mock/charge_manager_mock.c b/common/mock/charge_manager_mock.c index 11661d2b2e..3a459ef74c 100644 --- a/common/mock/charge_manager_mock.c +++ b/common/mock/charge_manager_mock.c @@ -47,4 +47,4 @@ void mock_charge_manager_set_vbus_voltage(int voltage_mv) } struct mock_ctrl_charge_manager mock_ctrl_charge_manager = -MOCK_CTRL_DEFAULT_CHARGE_MANAGER; + MOCK_CTRL_DEFAULT_CHARGE_MANAGER; -- cgit v1.2.1 From 3e7e4763b54f21db43334cc896ce88f0812de8a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:13 -0600 Subject: zephyr/shim/src/ioex.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e65930ba40a3db466514ff4f14bd3ae0275118c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730910 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/ioex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/src/ioex.c b/zephyr/shim/src/ioex.c index 56b10d1f48..18410b4b68 100644 --- a/zephyr/shim/src/ioex.c +++ b/zephyr/shim/src/ioex.c @@ -42,8 +42,8 @@ static int ioex_init_default(const struct device *unused) for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; i++) { /* IO Expander has been initialized, skip re-initializing */ - if (ioex_config[i].flags & (IOEX_FLAGS_INITIALIZED | - IOEX_FLAGS_DEFAULT_INIT_DISABLED)) + if (ioex_config[i].flags & + (IOEX_FLAGS_INITIALIZED | IOEX_FLAGS_DEFAULT_INIT_DISABLED)) continue; ret = ioex_init(i); -- cgit v1.2.1 From a81f9444d0b944e1df4d601f568ab7c4d7fb6ff1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:33 -0600 Subject: board/genesis/pse.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3dc538b797e5a03c2ca1585ff15b7f8b4c5b3465 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728400 Reviewed-by: Jeremy Bettis --- board/genesis/pse.c | 81 ++++++++++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/board/genesis/pse.c b/board/genesis/pse.c index 671288ccf5..9983c3fa52 100644 --- a/board/genesis/pse.c +++ b/board/genesis/pse.c @@ -18,44 +18,44 @@ #include "timer.h" #include "util.h" -#define LTC4291_I2C_ADDR 0x2C - -#define LTC4291_REG_SUPEVN_COR 0x0B -#define LTC4291_REG_STATPWR 0x10 -#define LTC4291_REG_STATPIN 0x11 -#define LTC4291_REG_OPMD 0x12 -#define LTC4291_REG_DISENA 0x13 -#define LTC4291_REG_DETENA 0x14 -#define LTC4291_REG_DETPB 0x18 -#define LTC4291_REG_PWRPB 0x19 -#define LTC4291_REG_RSTPB 0x1A -#define LTC4291_REG_ID 0x1B -#define LTC4291_REG_DEVID 0x43 -#define LTC4291_REG_HPMD1 0x46 -#define LTC4291_REG_HPMD2 0x4B -#define LTC4291_REG_HPMD3 0x50 -#define LTC4291_REG_HPMD4 0x55 -#define LTC4291_REG_LPWRPB 0x6E - -#define LTC4291_FLD_STATPIN_AUTO BIT(0) -#define LTC4291_FLD_RSTPB_RSTALL BIT(4) - -#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) -#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) -#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) -#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) - -#define LTC4291_OPMD_AUTO 0xFF -#define LTC4291_DISENA_ALL 0x0F -#define LTC4291_DETENA_ALL 0xFF -#define LTC4291_ID 0x64 -#define LTC4291_DEVID 0x38 -#define LTC4291_HPMD_MIN 0x00 -#define LTC4291_HPMD_MAX 0xA8 - -#define LTC4291_PORT_MAX 4 - -#define LTC4291_RESET_DELAY_US (20 * MSEC) +#define LTC4291_I2C_ADDR 0x2C + +#define LTC4291_REG_SUPEVN_COR 0x0B +#define LTC4291_REG_STATPWR 0x10 +#define LTC4291_REG_STATPIN 0x11 +#define LTC4291_REG_OPMD 0x12 +#define LTC4291_REG_DISENA 0x13 +#define LTC4291_REG_DETENA 0x14 +#define LTC4291_REG_DETPB 0x18 +#define LTC4291_REG_PWRPB 0x19 +#define LTC4291_REG_RSTPB 0x1A +#define LTC4291_REG_ID 0x1B +#define LTC4291_REG_DEVID 0x43 +#define LTC4291_REG_HPMD1 0x46 +#define LTC4291_REG_HPMD2 0x4B +#define LTC4291_REG_HPMD3 0x50 +#define LTC4291_REG_HPMD4 0x55 +#define LTC4291_REG_LPWRPB 0x6E + +#define LTC4291_FLD_STATPIN_AUTO BIT(0) +#define LTC4291_FLD_RSTPB_RSTALL BIT(4) + +#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) +#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) +#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) +#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) + +#define LTC4291_OPMD_AUTO 0xFF +#define LTC4291_DISENA_ALL 0x0F +#define LTC4291_DETENA_ALL 0xFF +#define LTC4291_ID 0x64 +#define LTC4291_DEVID 0x38 +#define LTC4291_HPMD_MIN 0x00 +#define LTC4291_HPMD_MAX 0xA8 + +#define LTC4291_PORT_MAX 4 + +#define LTC4291_RESET_DELAY_US (20 * MSEC) #define I2C_PSE_READ(reg, data) \ i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) @@ -63,7 +63,7 @@ #define I2C_PSE_WRITE(reg, data) \ i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static int pse_write_hpmd(int port, int val) { @@ -205,8 +205,7 @@ static int command_pse(int argc, char **argv) else return EC_ERROR_PARAM2; } -DECLARE_CONSOLE_COMMAND(pse, command_pse, - " ", +DECLARE_CONSOLE_COMMAND(pse, command_pse, " ", "Set PSE port power"); static int ec_command_pse_status(int port, uint8_t *status) -- cgit v1.2.1 From 165ce2a1c9639ef3c179b537d15e9d0f4dbd521e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:57 -0600 Subject: board/taniks/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I51d8dbe2b1f0c22dfec2cdd45953b0f89d298ea2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728966 Reviewed-by: Jeremy Bettis --- board/taniks/fw_config.h | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/board/taniks/fw_config.h b/board/taniks/fw_config.h index 9e1b0ebdf1..7b708716c9 100644 --- a/board/taniks/fw_config.h +++ b/board/taniks/fw_config.h @@ -14,20 +14,14 @@ * Source of truth is the project/taniks/taniks/config.star configuration file. */ -enum ec_cfg_usb_db_type { - DB_USB_ABSENT = 0, - DB_USB3_PS8815 = 1 -}; +enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 }; enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_tabletmode_type { - TABLETMODE_DISABLED = 0, - TABLETMODE_ENABLED = 1 -}; +enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 }; enum ec_cfg_nvme_status { NVME_DISABLED = 0, @@ -40,11 +34,11 @@ enum ec_cfg_emmc_status { union taniks_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 2; - uint32_t sd_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 4; + enum ec_cfg_usb_db_type usb_db : 2; + uint32_t sd_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 4; /* b/211079131 - Fw config structure * b/211076082 - Move tablet mode to bit14 * bit8-9: kb_layout @@ -52,10 +46,10 @@ union taniks_cbi_fw_config { * bit12: nvme * bit13: emmc */ - enum ec_cfg_nvme_status nvme_status : 1; - enum ec_cfg_emmc_status emmc_status : 1; - enum ec_cfg_tabletmode_type tabletmode : 1; - uint32_t reserved_2 : 17; + enum ec_cfg_nvme_status nvme_status : 1; + enum ec_cfg_emmc_status emmc_status : 1; + enum ec_cfg_tabletmode_type tabletmode : 1; + uint32_t reserved_2 : 17; }; uint32_t raw_value; }; -- cgit v1.2.1 From 0a01862b141a5497acc9ca9fd971e95399c3aed8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:27 -0600 Subject: baseboard/hatch/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73b48fd48cc676ee63a98c071d569786be2df427 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727524 Reviewed-by: Jeremy Bettis --- baseboard/hatch/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/hatch/usb_pd_policy.c b/baseboard/hatch/usb_pd_policy.c index a66bfefe87..ba12681b35 100644 --- a/baseboard/hatch/usb_pd_policy.c +++ b/baseboard/hatch/usb_pd_policy.c @@ -19,8 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 50866a38f32fca7da857ce7db9e2ce4a9ec5741a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:51 -0600 Subject: common/usb_port_power_smart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I71005927bdaaa2147b0656651fed909d46460c45 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729779 Reviewed-by: Jeremy Bettis --- common/usb_port_power_smart.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c index 3143bdf400..74912de773 100644 --- a/common/usb_port_power_smart.c +++ b/common/usb_port_power_smart.c @@ -16,15 +16,15 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) #ifndef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE #define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_SDP2 #endif struct charge_mode_t { - uint8_t mode:7; - uint8_t inhibit_charging_in_suspend:1; + uint8_t mode : 7; + uint8_t inhibit_charging_in_suspend : 1; } __pack; static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT]; @@ -34,7 +34,9 @@ static struct charge_mode_t charge_mode[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT]; * If we only support CDP and SDP, the control signals are hard-wired so * there's nothing to do. The only to do is set ILIM_SEL. */ -static void usb_charge_set_control_mode(int port_id, int mode) {} +static void usb_charge_set_control_mode(int port_id, int mode) +{ +} #else /* !defined(CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY) */ static void usb_charge_set_control_mode(int port_id, int mode) { @@ -74,7 +76,7 @@ static void usb_charge_set_ilim(int port_id, int sel) { int ilim_sel; -#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) || \ +#if defined(CONFIG_USB_PORT_POWER_SMART_SIMPLE) || \ defined(CONFIG_USB_PORT_POWER_SMART_INVERTED) /* ILIM_SEL is inverted. */ sel = !sel; @@ -152,7 +154,7 @@ static int command_set_mode(int argc, char **argv) if (argc == 1) { for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++) ccprintf("Port %d: %d,%d\n", i, charge_mode[i].mode, - charge_mode[i].inhibit_charging_in_suspend); + charge_mode[i].inhibit_charging_in_suspend); return EC_SUCCESS; } @@ -188,14 +190,13 @@ usb_charge_command_set_mode(struct host_cmd_handler_args *args) { const struct ec_params_usb_charge_set_mode *p = args->params; - if (usb_charge_set_mode(p->usb_port_id, p->mode, - p->inhibit_charge) != EC_SUCCESS) + if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) != + EC_SUCCESS) return EC_RES_ERROR; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, - usb_charge_command_set_mode, +DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_charge_command_set_mode, EC_VER_MASK(0)); /*****************************************************************************/ @@ -213,18 +214,18 @@ static void usb_charge_init(void) const struct charge_mode_t *prev; int version, size, i; - prev = (const struct charge_mode_t *)system_get_jump_tag(USB_SYSJUMP_TAG, - &version, &size); + prev = (const struct charge_mode_t *)system_get_jump_tag( + USB_SYSJUMP_TAG, &version, &size); if (!prev || version != USB_HOOK_VERSION || - size != sizeof(charge_mode)) { + size != sizeof(charge_mode)) { usb_charge_all_ports_ctrl(USB_CHARGE_MODE_DISABLED); return; } for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++) usb_charge_set_mode(i, prev[i].mode, - prev[i].inhibit_charging_in_suspend); + prev[i].inhibit_charging_in_suspend); } DECLARE_HOOK(HOOK_INIT, usb_charge_init, HOOK_PRIO_DEFAULT); @@ -234,9 +235,8 @@ static void usb_charge_resume(void) /* Turn on USB ports on as we go into S0 from S3 or S5. */ for (i = 0; i < CONFIG_USB_PORT_POWER_SMART_PORT_COUNT; i++) - usb_charge_set_mode(i, - CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE, - charge_mode[i].inhibit_charging_in_suspend); + usb_charge_set_mode(i, CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE, + charge_mode[i].inhibit_charging_in_suspend); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, usb_charge_resume, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From df640541e8ca3e9d3b8561a695ae26104f14b00a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:14 -0600 Subject: chip/mchp/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icb1d193d1f94b23ab3238b0e933f0275398f88dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729299 Reviewed-by: Jeremy Bettis --- chip/mchp/registers.h | 1135 ++++++++++++++++++++++++------------------------- 1 file changed, 549 insertions(+), 586 deletions(-) diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index 65936caa2d..3272ab88bb 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -10,7 +10,6 @@ #include "common.h" #include "compile_time_macros.h" - #if defined(CHIP_FAMILY_MEC152X) #include "registers-mec152x.h" #elif defined(CHIP_FAMILY_MEC170X) @@ -23,530 +22,526 @@ /* Common registers */ /* EC Interrupt aggregator (ECIA) */ -#define MCHP_INT_SOURCE(x) REG32(MCHP_INTx_BASE(x) + 0x0) -#define MCHP_INT_ENABLE(x) REG32(MCHP_INTx_BASE(x) + 0x4) -#define MCHP_INT_RESULT(x) REG32(MCHP_INTx_BASE(x) + 0x8) -#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc) -#define MCHP_INT_BLK_EN REG32(MCHP_INT_BASE + 0x200) -#define MCHP_INT_BLK_DIS REG32(MCHP_INT_BASE + 0x204) -#define MCHP_INT_BLK_IRQ REG32(MCHP_INT_BASE + 0x208) +#define MCHP_INT_SOURCE(x) REG32(MCHP_INTx_BASE(x) + 0x0) +#define MCHP_INT_ENABLE(x) REG32(MCHP_INTx_BASE(x) + 0x4) +#define MCHP_INT_RESULT(x) REG32(MCHP_INTx_BASE(x) + 0x8) +#define MCHP_INT_DISABLE(x) REG32(MCHP_INTx_BASE(x) + 0xc) +#define MCHP_INT_BLK_EN REG32(MCHP_INT_BASE + 0x200) +#define MCHP_INT_BLK_DIS REG32(MCHP_INT_BASE + 0x204) +#define MCHP_INT_BLK_IRQ REG32(MCHP_INT_BASE + 0x208) /* EC Chip Configuration */ -#define MCHP_CHIP_LEGACY_DEV_ID REG8(MCHP_CHIP_BASE + 0x20) -#define MCHP_CHIP_LEGACY_DEV_REV REG8(MCHP_CHIP_BASE + 0x21) +#define MCHP_CHIP_LEGACY_DEV_ID REG8(MCHP_CHIP_BASE + 0x20) +#define MCHP_CHIP_LEGACY_DEV_REV REG8(MCHP_CHIP_BASE + 0x21) /* Power/Clocks/Resets */ -#define MCHP_PCR_SYS_SLP_CTL REG32(MCHP_PCR_BASE + 0x00) -#define MCHP_PCR_PROC_CLK_CTL REG32(MCHP_PCR_BASE + 0x04) -#define MCHP_PCR_SLOW_CLK_CTL REG32(MCHP_PCR_BASE + 0x08) -#define MCHP_PCR_CHIP_OSC_ID REG32(MCHP_PCR_BASE + 0x0C) -#define MCHP_PCR_PWR_RST_STS REG32(MCHP_PCR_BASE + 0x10) -#define MCHP_PCR_PWR_RST_CTL REG32(MCHP_PCR_BASE + 0x14) -#define MCHP_PCR_SYS_RST REG32(MCHP_PCR_BASE + 0x18) -#define MCHP_PCR_SLP_EN0 REG32(MCHP_PCR_BASE + 0x30) -#define MCHP_PCR_SLP_EN1 REG32(MCHP_PCR_BASE + 0x34) -#define MCHP_PCR_SLP_EN2 REG32(MCHP_PCR_BASE + 0x38) -#define MCHP_PCR_SLP_EN3 REG32(MCHP_PCR_BASE + 0x3C) -#define MCHP_PCR_SLP_EN4 REG32(MCHP_PCR_BASE + 0x40) -#define MCHP_PCR_CLK_REQ0 REG32(MCHP_PCR_BASE + 0x50) -#define MCHP_PCR_CLK_REQ1 REG32(MCHP_PCR_BASE + 0x54) -#define MCHP_PCR_CLK_REQ2 REG32(MCHP_PCR_BASE + 0x58) -#define MCHP_PCR_CLK_REQ3 REG32(MCHP_PCR_BASE + 0x5C) -#define MCHP_PCR_CLK_REQ4 REG32(MCHP_PCR_BASE + 0x60) -#define MCHP_PCR_RST_EN0 REG32(MCHP_PCR_BASE + 0x70) -#define MCHP_PCR_RST_EN1 REG32(MCHP_PCR_BASE + 0x74) -#define MCHP_PCR_RST_EN2 REG32(MCHP_PCR_BASE + 0x78) -#define MCHP_PCR_RST_EN3 REG32(MCHP_PCR_BASE + 0x7C) -#define MCHP_PCR_RST_EN4 REG32(MCHP_PCR_BASE + 0x80) -#define MCHP_PCR_SLP_EN(x) REG32(MCHP_PCR_BASE + 0x30 + ((x)<<2)) -#define MCHP_PCR_CLK_REQ(x) REG32(MCHP_PCR_BASE + 0x50 + ((x)<<2)) -#define MCHP_PCR_RST_EN(x) REG32(MCHP_PCR_BASE + 0x70 + ((x)<<2)) +#define MCHP_PCR_SYS_SLP_CTL REG32(MCHP_PCR_BASE + 0x00) +#define MCHP_PCR_PROC_CLK_CTL REG32(MCHP_PCR_BASE + 0x04) +#define MCHP_PCR_SLOW_CLK_CTL REG32(MCHP_PCR_BASE + 0x08) +#define MCHP_PCR_CHIP_OSC_ID REG32(MCHP_PCR_BASE + 0x0C) +#define MCHP_PCR_PWR_RST_STS REG32(MCHP_PCR_BASE + 0x10) +#define MCHP_PCR_PWR_RST_CTL REG32(MCHP_PCR_BASE + 0x14) +#define MCHP_PCR_SYS_RST REG32(MCHP_PCR_BASE + 0x18) +#define MCHP_PCR_SLP_EN0 REG32(MCHP_PCR_BASE + 0x30) +#define MCHP_PCR_SLP_EN1 REG32(MCHP_PCR_BASE + 0x34) +#define MCHP_PCR_SLP_EN2 REG32(MCHP_PCR_BASE + 0x38) +#define MCHP_PCR_SLP_EN3 REG32(MCHP_PCR_BASE + 0x3C) +#define MCHP_PCR_SLP_EN4 REG32(MCHP_PCR_BASE + 0x40) +#define MCHP_PCR_CLK_REQ0 REG32(MCHP_PCR_BASE + 0x50) +#define MCHP_PCR_CLK_REQ1 REG32(MCHP_PCR_BASE + 0x54) +#define MCHP_PCR_CLK_REQ2 REG32(MCHP_PCR_BASE + 0x58) +#define MCHP_PCR_CLK_REQ3 REG32(MCHP_PCR_BASE + 0x5C) +#define MCHP_PCR_CLK_REQ4 REG32(MCHP_PCR_BASE + 0x60) +#define MCHP_PCR_RST_EN0 REG32(MCHP_PCR_BASE + 0x70) +#define MCHP_PCR_RST_EN1 REG32(MCHP_PCR_BASE + 0x74) +#define MCHP_PCR_RST_EN2 REG32(MCHP_PCR_BASE + 0x78) +#define MCHP_PCR_RST_EN3 REG32(MCHP_PCR_BASE + 0x7C) +#define MCHP_PCR_RST_EN4 REG32(MCHP_PCR_BASE + 0x80) +#define MCHP_PCR_SLP_EN(x) REG32(MCHP_PCR_BASE + 0x30 + ((x) << 2)) +#define MCHP_PCR_CLK_REQ(x) REG32(MCHP_PCR_BASE + 0x50 + ((x) << 2)) +#define MCHP_PCR_RST_EN(x) REG32(MCHP_PCR_BASE + 0x70 + ((x) << 2)) /* Bit definitions for MCHP_PCR_SYS_SLP_CTL */ -#define MCHP_PCR_SYS_SLP_LIGHT (0ul << 0) -#define MCHP_PCR_SYS_SLP_HEAVY (1ul << 0) -#define MCHP_PCR_SYS_SLP_ALL (1ul << 3) +#define MCHP_PCR_SYS_SLP_LIGHT (0ul << 0) +#define MCHP_PCR_SYS_SLP_HEAVY (1ul << 0) +#define MCHP_PCR_SYS_SLP_ALL (1ul << 3) /* * Set/clear PCR sleep enable bit for single device * d bits[10:8] = register 0 - 4 * d bits[4:0] = register bit position */ #define MCHP_PCR_SLP_EN_DEV(d) \ - (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d) & 0x1f))) + (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) |= (1ul << ((d)&0x1f))) #define MCHP_PCR_SLP_DIS_DEV(d) \ - (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d) & 0x1f))) + (MCHP_PCR_SLP_EN(((d) >> 8) & 0x07) &= ~(1ul << ((d)&0x1f))) /* * Set/clear bit pattern specified by mask in a single PCR sleep enable * register. * id = zero based ID of sleep enable register (0-4) * m = bit mask of bits to change */ -#define MCHP_PCR_SLP_EN_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) |= (m)) -#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) &= ~(m)) +#define MCHP_PCR_SLP_EN_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) |= (m)) +#define MCHP_PCR_SLP_DIS_DEV_MASK(id, m) (MCHP_PCR_SLP_EN((id)) &= ~(m)) /* Slow Clock Control Mask */ -#define MCHP_PCR_SLOW_CLK_CTL_MASK 0x03FFul +#define MCHP_PCR_SLOW_CLK_CTL_MASK 0x03FFul /* TFDP */ -#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) -#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) +#define MCHP_TFDP_DATA REG8(MCHP_TFDP_BASE + 0x00) +#define MCHP_TFDP_CTRL REG8(MCHP_TFDP_BASE + 0x04) /* UART */ -#define MCHP_UART_ACT(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0x30) -#define MCHP_UART_CFG(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0) +#define MCHP_UART_ACT(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0x30) +#define MCHP_UART_CFG(x) REG8(MCHP_UART_CONFIG_BASE(x) + 0xf0) /* DLAB=0 */ -#define MCHP_UART_RB(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_TB(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_IER(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) +#define MCHP_UART_RB(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) +#define MCHP_UART_TB(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) +#define MCHP_UART_IER(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) /* DLAB=1 */ -#define MCHP_UART_PBRG0(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) -#define MCHP_UART_PBRG1(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) -#define MCHP_UART_FCR(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) -#define MCHP_UART_IIR(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) -#define MCHP_UART_LCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3) -#define MCHP_UART_MCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4) -#define MCHP_UART_LSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5) -#define MCHP_UART_MSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6) -#define MCHP_UART_SCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7) +#define MCHP_UART_PBRG0(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x0) +#define MCHP_UART_PBRG1(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x1) +#define MCHP_UART_FCR(x) /*W*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) +#define MCHP_UART_IIR(x) /*R*/ REG8(MCHP_UART_RUNTIME_BASE(x) + 0x2) +#define MCHP_UART_LCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x3) +#define MCHP_UART_MCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x4) +#define MCHP_UART_LSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x5) +#define MCHP_UART_MSR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x6) +#define MCHP_UART_SCR(x) REG8(MCHP_UART_RUNTIME_BASE(x) + 0x7) /* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY BIT(5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* Timer */ -#define MCHP_TMR16_CNT(x) REG32(MCHP_TMR16_BASE(x) + 0x0) -#define MCHP_TMR16_PRE(x) REG32(MCHP_TMR16_BASE(x) + 0x4) -#define MCHP_TMR16_STS(x) REG32(MCHP_TMR16_BASE(x) + 0x8) -#define MCHP_TMR16_IEN(x) REG32(MCHP_TMR16_BASE(x) + 0xc) -#define MCHP_TMR16_CTL(x) REG32(MCHP_TMR16_BASE(x) + 0x10) -#define MCHP_TMR32_CNT(x) REG32(MCHP_TMR32_BASE(x) + 0x0) -#define MCHP_TMR32_PRE(x) REG32(MCHP_TMR32_BASE(x) + 0x4) -#define MCHP_TMR32_STS(x) REG32(MCHP_TMR32_BASE(x) + 0x8) -#define MCHP_TMR32_IEN(x) REG32(MCHP_TMR32_BASE(x) + 0xc) -#define MCHP_TMR32_CTL(x) REG32(MCHP_TMR32_BASE(x) + 0x10) +#define MCHP_TMR16_CNT(x) REG32(MCHP_TMR16_BASE(x) + 0x0) +#define MCHP_TMR16_PRE(x) REG32(MCHP_TMR16_BASE(x) + 0x4) +#define MCHP_TMR16_STS(x) REG32(MCHP_TMR16_BASE(x) + 0x8) +#define MCHP_TMR16_IEN(x) REG32(MCHP_TMR16_BASE(x) + 0xc) +#define MCHP_TMR16_CTL(x) REG32(MCHP_TMR16_BASE(x) + 0x10) +#define MCHP_TMR32_CNT(x) REG32(MCHP_TMR32_BASE(x) + 0x0) +#define MCHP_TMR32_PRE(x) REG32(MCHP_TMR32_BASE(x) + 0x4) +#define MCHP_TMR32_STS(x) REG32(MCHP_TMR32_BASE(x) + 0x8) +#define MCHP_TMR32_IEN(x) REG32(MCHP_TMR32_BASE(x) + 0xc) +#define MCHP_TMR32_CTL(x) REG32(MCHP_TMR32_BASE(x) + 0x10) /* RTimer */ -#define MCHP_RTMR_COUNTER REG32(MCHP_RTMR_BASE + 0x00) -#define MCHP_RTMR_PRELOAD REG32(MCHP_RTMR_BASE + 0x04) -#define MCHP_RTMR_CONTROL REG8(MCHP_RTMR_BASE + 0x08) -#define MCHP_RTMR_SOFT_INTR REG8(MCHP_RTMR_BASE + 0x0c) +#define MCHP_RTMR_COUNTER REG32(MCHP_RTMR_BASE + 0x00) +#define MCHP_RTMR_PRELOAD REG32(MCHP_RTMR_BASE + 0x04) +#define MCHP_RTMR_CONTROL REG8(MCHP_RTMR_BASE + 0x08) +#define MCHP_RTMR_SOFT_INTR REG8(MCHP_RTMR_BASE + 0x0c) /* Watch dog timer */ -#define MCHP_WDG_LOAD REG16(MCHP_WDG_BASE + 0x0) -#define MCHP_WDG_CTL REG16(MCHP_WDG_BASE + 0x4) -#define MCHP_WDG_KICK REG8(MCHP_WDG_BASE + 0x8) -#define MCHP_WDG_CNT REG16(MCHP_WDG_BASE + 0xc) -#define MCHP_WDT_CTL_ENABLE BIT(0) -#define MCHP_WDT_CTL_HTMR_STALL_EN BIT(2) -#define MCHP_WDT_CTL_WKTMR_STALL_EN BIT(3) -#define MCHP_WDT_CTL_JTAG_STALL_EN BIT(4) +#define MCHP_WDG_LOAD REG16(MCHP_WDG_BASE + 0x0) +#define MCHP_WDG_CTL REG16(MCHP_WDG_BASE + 0x4) +#define MCHP_WDG_KICK REG8(MCHP_WDG_BASE + 0x8) +#define MCHP_WDG_CNT REG16(MCHP_WDG_BASE + 0xc) +#define MCHP_WDT_CTL_ENABLE BIT(0) +#define MCHP_WDT_CTL_HTMR_STALL_EN BIT(2) +#define MCHP_WDT_CTL_WKTMR_STALL_EN BIT(3) +#define MCHP_WDT_CTL_JTAG_STALL_EN BIT(4) /* Blinking-Breathing LED */ -#define MCHP_BBLED_CONFIG(x) REG32(MCHP_BBLED_BASE(x) + 0x00) -#define MCHP_BBLED_LIMITS(x) REG32(MCHP_BBLED_BASE(x) + 0x04) -#define MCHP_BBLED_LIMIT_MIN(x) REG8(MCHP_BBLED_BASE(x) + 0x04) -#define MCHP_BBLED_LIMIT_MAX(x) REG8(MCHP_BBLED_BASE(x) + 0x06) -#define MCHP_BBLED_DELAY(x) REG32(MCHP_BBLED_BASE(x) + 0x08) -#define MCHP_BBLED_UPDATE_STEP(x) REG32(MCHP_BBLED_BASE(x) + 0x0C) -#define MCHP_BBLED_UPDATE_INTV(x) REG32(MCHP_BBLED_BASE(x) + 0x10) -#define MCHP_BBLED_OUTPUT_DLY(x) REG8(MCHP_BBLED_BASE(x) + 0x14) +#define MCHP_BBLED_CONFIG(x) REG32(MCHP_BBLED_BASE(x) + 0x00) +#define MCHP_BBLED_LIMITS(x) REG32(MCHP_BBLED_BASE(x) + 0x04) +#define MCHP_BBLED_LIMIT_MIN(x) REG8(MCHP_BBLED_BASE(x) + 0x04) +#define MCHP_BBLED_LIMIT_MAX(x) REG8(MCHP_BBLED_BASE(x) + 0x06) +#define MCHP_BBLED_DELAY(x) REG32(MCHP_BBLED_BASE(x) + 0x08) +#define MCHP_BBLED_UPDATE_STEP(x) REG32(MCHP_BBLED_BASE(x) + 0x0C) +#define MCHP_BBLED_UPDATE_INTV(x) REG32(MCHP_BBLED_BASE(x) + 0x10) +#define MCHP_BBLED_OUTPUT_DLY(x) REG8(MCHP_BBLED_BASE(x) + 0x14) /* BBLED Configuration Register */ -#define MCHP_BBLED_ASYMMETRIC BIT(16) -#define MCHP_BBLED_WDT_RELOAD_BITPOS 8 -#define MCHP_BBLED_WDT_RELOAD_MASK0 0xFFul -#define MCHP_BBLED_WDT_RELOAD_MASK (0xFFul << 8) -#define MCHP_BBLED_RESET BIT(7) -#define MCHP_BBLED_EN_UPDATE BIT(6) -#define MCHP_BBLED_PWM_SIZE_BITPOS 4 -#define MCHP_BBLED_PWM_SIZE_MASK0 0x03ul -#define MCHP_BBLED_PWM_SIZE_MASK (0x03ul << 4) -#define MCHP_BBLED_PWM_SIZE_6BIT (0x02ul << 4) -#define MCHP_BBLED_PWM_SIZE_7BIT (0x01ul << 4) -#define MCHP_BBLED_PWM_SIZE_8BIT (0x00ul << 4) -#define MCHP_BBLED_SYNC BIT(3) -#define MCHP_BBLED_CLK_48M BIT(2) -#define MCHP_BBLED_CLK_32K 0 -#define MCHP_BBLED_CTRL_MASK 0x03ul -#define MCHP_BBLED_CTRL_ALWAYS_ON 0x03ul -#define MCHP_BBLED_CTRL_BLINK 0x02ul -#define MCHP_BBLED_CTRL_BREATHE 0x01ul -#define MCHP_BBLED_CTRL_OFF 0x00ul +#define MCHP_BBLED_ASYMMETRIC BIT(16) +#define MCHP_BBLED_WDT_RELOAD_BITPOS 8 +#define MCHP_BBLED_WDT_RELOAD_MASK0 0xFFul +#define MCHP_BBLED_WDT_RELOAD_MASK (0xFFul << 8) +#define MCHP_BBLED_RESET BIT(7) +#define MCHP_BBLED_EN_UPDATE BIT(6) +#define MCHP_BBLED_PWM_SIZE_BITPOS 4 +#define MCHP_BBLED_PWM_SIZE_MASK0 0x03ul +#define MCHP_BBLED_PWM_SIZE_MASK (0x03ul << 4) +#define MCHP_BBLED_PWM_SIZE_6BIT (0x02ul << 4) +#define MCHP_BBLED_PWM_SIZE_7BIT (0x01ul << 4) +#define MCHP_BBLED_PWM_SIZE_8BIT (0x00ul << 4) +#define MCHP_BBLED_SYNC BIT(3) +#define MCHP_BBLED_CLK_48M BIT(2) +#define MCHP_BBLED_CLK_32K 0 +#define MCHP_BBLED_CTRL_MASK 0x03ul +#define MCHP_BBLED_CTRL_ALWAYS_ON 0x03ul +#define MCHP_BBLED_CTRL_BLINK 0x02ul +#define MCHP_BBLED_CTRL_BREATHE 0x01ul +#define MCHP_BBLED_CTRL_OFF 0x00ul /* BBLED Delay Register */ -#define MCHP_BBLED_DLY_MASK 0x0FFFul -#define MCHP_BBLED_DLY_LO_BITPOS 0 -#define MCHP_BBLED_DLY_LO_MASK 0x0FFFul -#define MCHP_BBLED_DLY_HI_BITPOS 12 -#define MCHP_BBLED_DLY_HI_MASK (0x0FFFul << 12) +#define MCHP_BBLED_DLY_MASK 0x0FFFul +#define MCHP_BBLED_DLY_LO_BITPOS 0 +#define MCHP_BBLED_DLY_LO_MASK 0x0FFFul +#define MCHP_BBLED_DLY_HI_BITPOS 12 +#define MCHP_BBLED_DLY_HI_MASK (0x0FFFul << 12) /* * BBLED Update Step Register * 8 update fields numbered 0 - 7 */ -#define MCHP_BBLED_UPD_STEP_MASK0 0x0Ful -#define MCHP_BBLED_UPD_STEP_MASK(u) (0x0Ful << (((u) & 0x07) + 4)) +#define MCHP_BBLED_UPD_STEP_MASK0 0x0Ful +#define MCHP_BBLED_UPD_STEP_MASK(u) (0x0Ful << (((u)&0x07) + 4)) /* * BBLED Update Interval Register * 8 interval fields numbered 0 - 7 */ -#define MCHP_BBLED_UPD_INTV_MASK0 0x0Ful -#define MCHP_BBLED_UPD_INTV_MASK(i) (0x0Ful << (((i) & 0x07) + 4)) +#define MCHP_BBLED_UPD_INTV_MASK0 0x0Ful +#define MCHP_BBLED_UPD_INTV_MASK(i) (0x0Ful << (((i)&0x07) + 4)) /* EMI */ -#define MCHP_EMI_H2E_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x0) -#define MCHP_EMI_E2H_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x1) -#define MCHP_EMI_MBA0(n) REG32(MCHP_EMI_BASE(n) + 0x4) -#define MCHP_EMI_MRL0(n) REG16(MCHP_EMI_BASE(n) + 0x8) -#define MCHP_EMI_MWL0(n) REG16(MCHP_EMI_BASE(n) + 0xa) -#define MCHP_EMI_MBA1(n) REG32(MCHP_EMI_BASE(n) + 0xc) -#define MCHP_EMI_MRL1(n) REG16(MCHP_EMI_BASE(n) + 0x10) -#define MCHP_EMI_MWL1(n) REG16(MCHP_EMI_BASE(n) + 0x12) -#define MCHP_EMI_ISR(n) REG16(MCHP_EMI_BASE(n) + 0x14) -#define MCHP_EMI_HCE(n) REG16(MCHP_EMI_BASE(n) + 0x16) -#define MCHP_EMI_ISR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0x8) -#define MCHP_EMI_ISR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0x9) -#define MCHP_EMI_IMR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0xa) -#define MCHP_EMI_IMR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0xb) +#define MCHP_EMI_H2E_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x0) +#define MCHP_EMI_E2H_MBX(n) REG8(MCHP_EMI_BASE(n) + 0x1) +#define MCHP_EMI_MBA0(n) REG32(MCHP_EMI_BASE(n) + 0x4) +#define MCHP_EMI_MRL0(n) REG16(MCHP_EMI_BASE(n) + 0x8) +#define MCHP_EMI_MWL0(n) REG16(MCHP_EMI_BASE(n) + 0xa) +#define MCHP_EMI_MBA1(n) REG32(MCHP_EMI_BASE(n) + 0xc) +#define MCHP_EMI_MRL1(n) REG16(MCHP_EMI_BASE(n) + 0x10) +#define MCHP_EMI_MWL1(n) REG16(MCHP_EMI_BASE(n) + 0x12) +#define MCHP_EMI_ISR(n) REG16(MCHP_EMI_BASE(n) + 0x14) +#define MCHP_EMI_HCE(n) REG16(MCHP_EMI_BASE(n) + 0x16) +#define MCHP_EMI_ISR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0x8) +#define MCHP_EMI_ISR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0x9) +#define MCHP_EMI_IMR_B0(n) REG8(MCHP_EMI_RT_BASE(n) + 0xa) +#define MCHP_EMI_IMR_B1(n) REG8(MCHP_EMI_RT_BASE(n) + 0xb) /* Mailbox */ -#define MCHP_MBX_INDEX REG8(MCHP_MBX_RT_BASE + 0x0) -#define MCHP_MBX_DATA REG8(MCHP_MBX_RT_BASE + 0x1) -#define MCHP_MBX_H2E_MBX REG8(MCHP_MBX_BASE + 0x0) -#define MCHP_MBX_E2H_MBX REG8(MCHP_MBX_BASE + 0x4) -#define MCHP_MBX_ISR REG8(MCHP_MBX_BASE + 0x8) -#define MCHP_MBX_IMR REG8(MCHP_MBX_BASE + 0xc) -#define MCHP_MBX_REG(x) REG8(MCHP_MBX_BASE + 0x10 + (x)) +#define MCHP_MBX_INDEX REG8(MCHP_MBX_RT_BASE + 0x0) +#define MCHP_MBX_DATA REG8(MCHP_MBX_RT_BASE + 0x1) +#define MCHP_MBX_H2E_MBX REG8(MCHP_MBX_BASE + 0x0) +#define MCHP_MBX_E2H_MBX REG8(MCHP_MBX_BASE + 0x4) +#define MCHP_MBX_ISR REG8(MCHP_MBX_BASE + 0x8) +#define MCHP_MBX_IMR REG8(MCHP_MBX_BASE + 0xc) +#define MCHP_MBX_REG(x) REG8(MCHP_MBX_BASE + 0x10 + (x)) /* PWM */ -#define MCHP_PWM_ON(x) REG32(MCHP_PWM_BASE(x) + 0x00) -#define MCHP_PWM_OFF(x) REG32(MCHP_PWM_BASE(x) + 0x04) -#define MCHP_PWM_CFG(x) REG32(MCHP_PWM_BASE(x) + 0x08) +#define MCHP_PWM_ON(x) REG32(MCHP_PWM_BASE(x) + 0x00) +#define MCHP_PWM_OFF(x) REG32(MCHP_PWM_BASE(x) + 0x04) +#define MCHP_PWM_CFG(x) REG32(MCHP_PWM_BASE(x) + 0x08) /* TACH */ -#define MCHP_TACH_CTRL(x) REG32(MCHP_TACH_BASE(x)) -#define MCHP_TACH_CTRL_LO(x) REG16(MCHP_TACH_BASE(x) + 0x00) -#define MCHP_TACH_CTRL_CNT(x) REG16(MCHP_TACH_BASE(x) + 0x02) -#define MCHP_TACH_STATUS(x) REG8(MCHP_TACH_BASE(x) + 0x04) -#define MCHP_TACH_LIMIT_HI(x) REG16(MCHP_TACH_BASE(x) + 0x08) -#define MCHP_TACH_LIMIT_LO(x) REG16(MCHP_TACH_BASE(x) + 0x0C) +#define MCHP_TACH_CTRL(x) REG32(MCHP_TACH_BASE(x)) +#define MCHP_TACH_CTRL_LO(x) REG16(MCHP_TACH_BASE(x) + 0x00) +#define MCHP_TACH_CTRL_CNT(x) REG16(MCHP_TACH_BASE(x) + 0x02) +#define MCHP_TACH_STATUS(x) REG8(MCHP_TACH_BASE(x) + 0x04) +#define MCHP_TACH_LIMIT_HI(x) REG16(MCHP_TACH_BASE(x) + 0x08) +#define MCHP_TACH_LIMIT_LO(x) REG16(MCHP_TACH_BASE(x) + 0x0C) /* ACPI */ -#define MCHP_ACPI_EC_EC2OS(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y)) -#define MCHP_ACPI_EC_STATUS(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x104) -#define MCHP_ACPI_EC_BYTE_CTL(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x105) -#define MCHP_ACPI_EC_OS2EC(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y)) -#define MCHP_ACPI_PM1_STS1 REG8(MCHP_ACPI_PM_RT_BASE + 0x0) -#define MCHP_ACPI_PM1_STS2 REG8(MCHP_ACPI_PM_RT_BASE + 0x1) -#define MCHP_ACPI_PM1_EN1 REG8(MCHP_ACPI_PM_RT_BASE + 0x2) -#define MCHP_ACPI_PM1_EN2 REG8(MCHP_ACPI_PM_RT_BASE + 0x3) -#define MCHP_ACPI_PM1_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x4) -#define MCHP_ACPI_PM1_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x5) -#define MCHP_ACPI_PM2_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x6) -#define MCHP_ACPI_PM2_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x7) -#define MCHP_ACPI_PM_STS REG8(MCHP_ACPI_PM_EC_BASE + 0x10) +#define MCHP_ACPI_EC_EC2OS(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x100 + (y)) +#define MCHP_ACPI_EC_STATUS(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x104) +#define MCHP_ACPI_EC_BYTE_CTL(x) REG8(MCHP_ACPI_EC_BASE(x) + 0x105) +#define MCHP_ACPI_EC_OS2EC(x, y) REG8(MCHP_ACPI_EC_BASE(x) + 0x108 + (y)) +#define MCHP_ACPI_PM1_STS1 REG8(MCHP_ACPI_PM_RT_BASE + 0x0) +#define MCHP_ACPI_PM1_STS2 REG8(MCHP_ACPI_PM_RT_BASE + 0x1) +#define MCHP_ACPI_PM1_EN1 REG8(MCHP_ACPI_PM_RT_BASE + 0x2) +#define MCHP_ACPI_PM1_EN2 REG8(MCHP_ACPI_PM_RT_BASE + 0x3) +#define MCHP_ACPI_PM1_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x4) +#define MCHP_ACPI_PM1_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x5) +#define MCHP_ACPI_PM2_CTL1 REG8(MCHP_ACPI_PM_RT_BASE + 0x6) +#define MCHP_ACPI_PM2_CTL2 REG8(MCHP_ACPI_PM_RT_BASE + 0x7) +#define MCHP_ACPI_PM_STS REG8(MCHP_ACPI_PM_EC_BASE + 0x10) /* 8042 */ -#define MCHP_8042_OBF_CLR REG8(MCHP_8042_BASE + 0x0) -#define MCHP_8042_H2E REG8(MCHP_8042_BASE + 0x100) -#define MCHP_8042_E2H REG8(MCHP_8042_BASE + 0x100) -#define MCHP_8042_STS REG8(MCHP_8042_BASE + 0x104) -#define MCHP_8042_KB_CTRL REG8(MCHP_8042_BASE + 0x108) -#define MCHP_8042_PCOBF REG8(MCHP_8042_BASE + 0x114) -#define MCHP_8042_ACT REG8(MCHP_8042_BASE + 0x330) +#define MCHP_8042_OBF_CLR REG8(MCHP_8042_BASE + 0x0) +#define MCHP_8042_H2E REG8(MCHP_8042_BASE + 0x100) +#define MCHP_8042_E2H REG8(MCHP_8042_BASE + 0x100) +#define MCHP_8042_STS REG8(MCHP_8042_BASE + 0x104) +#define MCHP_8042_KB_CTRL REG8(MCHP_8042_BASE + 0x108) +#define MCHP_8042_PCOBF REG8(MCHP_8042_BASE + 0x114) +#define MCHP_8042_ACT REG8(MCHP_8042_BASE + 0x330) /* PROCHOT */ -#define MCHP_PCHOT_CUM_CNT REG32(MCHP_PROCHOT_BASE + 0x00) -#define MCHP_PCHOT_DTY_CYC_CNT REG32(MCHP_PROCHOT_BASE + 0x04) -#define MCHP_PCHOT_DTY_PRD_CNT REG32(MCHP_PROCHOT_BASE + 0x08) -#define MCHP_PCHOT_STS_CTRL REG32(MCHP_PROCHOT_BASE + 0x0C) -#define MCHP_PCHOT_ASERT_CNT REG32(MCHP_PROCHOT_BASE + 0x10) -#define MCHP_PCHOT_ASERT_CNT_LMT REG32(MCHP_PROCHOT_BASE + 0x14) -#define MCHP_PCHOT_TEST REG32(MCHP_PROCHOT_BASE + 0x18) +#define MCHP_PCHOT_CUM_CNT REG32(MCHP_PROCHOT_BASE + 0x00) +#define MCHP_PCHOT_DTY_CYC_CNT REG32(MCHP_PROCHOT_BASE + 0x04) +#define MCHP_PCHOT_DTY_PRD_CNT REG32(MCHP_PROCHOT_BASE + 0x08) +#define MCHP_PCHOT_STS_CTRL REG32(MCHP_PROCHOT_BASE + 0x0C) +#define MCHP_PCHOT_ASERT_CNT REG32(MCHP_PROCHOT_BASE + 0x10) +#define MCHP_PCHOT_ASERT_CNT_LMT REG32(MCHP_PROCHOT_BASE + 0x14) +#define MCHP_PCHOT_TEST REG32(MCHP_PROCHOT_BASE + 0x18) /* I2C registers access given controller base address */ -#define MCHP_I2C_CTRL(addr) REG8(addr) -#define MCHP_I2C_STATUS(addr) REG8(addr) -#define MCHP_I2C_OWN_ADDR(addr) REG16(addr + 0x4) -#define MCHP_I2C_DATA(addr) REG8(addr + 0x8) -#define MCHP_I2C_MASTER_CMD(addr) REG32(addr + 0xc) -#define MCHP_I2C_SLAVE_CMD(addr) REG32(addr + 0x10) -#define MCHP_I2C_PEC(addr) REG8(addr + 0x14) -#define MCHP_I2C_DATA_TIM_2(addr) REG8(addr + 0x18) -#define MCHP_I2C_COMPLETE(addr) REG32(addr + 0x20) -#define MCHP_I2C_IDLE_SCALE(addr) REG32(addr + 0x24) -#define MCHP_I2C_CONFIG(addr) REG32(addr + 0x28) -#define MCHP_I2C_BUS_CLK(addr) REG16(addr + 0x2c) -#define MCHP_I2C_BLK_ID(addr) REG8(addr + 0x30) -#define MCHP_I2C_REV(addr) REG8(addr + 0x34) -#define MCHP_I2C_BB_CTRL(addr) REG8(addr + 0x38) -#define MCHP_I2C_TST_DATA_TIM(addr) REG32(addr + 0x3c) -#define MCHP_I2C_DATA_TIM(addr) REG32(addr + 0x40) -#define MCHP_I2C_TOUT_SCALE(addr) REG32(addr + 0x44) -#define MCHP_I2C_SLAVE_TX_BUF(addr) REG8(addr + 0x48) -#define MCHP_I2C_SLAVE_RX_BUF(addr) REG8(addr + 0x4c) -#define MCHP_I2C_MASTER_TX_BUF(addr) REG8(addr + 0x50) -#define MCHP_I2C_MASTER_RX_BUF(addr) REG8(addr + 0x54) -#define MCHP_I2C_TEST_1(addr) REG32(addr + 0x58) -#define MCHP_I2C_TEST_2(addr) REG32(addr + 0x5c) -#define MCHP_I2C_WAKE_STS(addr) REG8(addr + 0x60) -#define MCHP_I2C_WAKE_EN(addr) REG8(addr + 0x64) -#define MCHP_I2C_TEST_3(addr) REG32(addr + 0x68) +#define MCHP_I2C_CTRL(addr) REG8(addr) +#define MCHP_I2C_STATUS(addr) REG8(addr) +#define MCHP_I2C_OWN_ADDR(addr) REG16(addr + 0x4) +#define MCHP_I2C_DATA(addr) REG8(addr + 0x8) +#define MCHP_I2C_MASTER_CMD(addr) REG32(addr + 0xc) +#define MCHP_I2C_SLAVE_CMD(addr) REG32(addr + 0x10) +#define MCHP_I2C_PEC(addr) REG8(addr + 0x14) +#define MCHP_I2C_DATA_TIM_2(addr) REG8(addr + 0x18) +#define MCHP_I2C_COMPLETE(addr) REG32(addr + 0x20) +#define MCHP_I2C_IDLE_SCALE(addr) REG32(addr + 0x24) +#define MCHP_I2C_CONFIG(addr) REG32(addr + 0x28) +#define MCHP_I2C_BUS_CLK(addr) REG16(addr + 0x2c) +#define MCHP_I2C_BLK_ID(addr) REG8(addr + 0x30) +#define MCHP_I2C_REV(addr) REG8(addr + 0x34) +#define MCHP_I2C_BB_CTRL(addr) REG8(addr + 0x38) +#define MCHP_I2C_TST_DATA_TIM(addr) REG32(addr + 0x3c) +#define MCHP_I2C_DATA_TIM(addr) REG32(addr + 0x40) +#define MCHP_I2C_TOUT_SCALE(addr) REG32(addr + 0x44) +#define MCHP_I2C_SLAVE_TX_BUF(addr) REG8(addr + 0x48) +#define MCHP_I2C_SLAVE_RX_BUF(addr) REG8(addr + 0x4c) +#define MCHP_I2C_MASTER_TX_BUF(addr) REG8(addr + 0x50) +#define MCHP_I2C_MASTER_RX_BUF(addr) REG8(addr + 0x54) +#define MCHP_I2C_TEST_1(addr) REG32(addr + 0x58) +#define MCHP_I2C_TEST_2(addr) REG32(addr + 0x5c) +#define MCHP_I2C_WAKE_STS(addr) REG8(addr + 0x60) +#define MCHP_I2C_WAKE_EN(addr) REG8(addr + 0x64) +#define MCHP_I2C_TEST_3(addr) REG32(addr + 0x68) /* Keyboard scan matrix */ -#define MCHP_KS_KSO_SEL REG32(MCHP_KEYSCAN_BASE + 0x4) -#define MCHP_KS_KSI_INPUT REG32(MCHP_KEYSCAN_BASE + 0x8) -#define MCHP_KS_KSI_STATUS REG32(MCHP_KEYSCAN_BASE + 0xc) -#define MCHP_KS_KSI_INT_EN REG32(MCHP_KEYSCAN_BASE + 0x10) -#define MCHP_KS_EXT_CTRL REG32(MCHP_KEYSCAN_BASE + 0x14) +#define MCHP_KS_KSO_SEL REG32(MCHP_KEYSCAN_BASE + 0x4) +#define MCHP_KS_KSI_INPUT REG32(MCHP_KEYSCAN_BASE + 0x8) +#define MCHP_KS_KSI_STATUS REG32(MCHP_KEYSCAN_BASE + 0xc) +#define MCHP_KS_KSI_INT_EN REG32(MCHP_KEYSCAN_BASE + 0x10) +#define MCHP_KS_EXT_CTRL REG32(MCHP_KEYSCAN_BASE + 0x14) /* ADC */ -#define MCHP_ADC_CTRL REG32(MCHP_ADC_BASE + 0x0) -#define MCHP_ADC_DELAY REG32(MCHP_ADC_BASE + 0x4) -#define MCHP_ADC_STS REG32(MCHP_ADC_BASE + 0x8) -#define MCHP_ADC_SINGLE REG32(MCHP_ADC_BASE + 0xc) -#define MCHP_ADC_REPEAT REG32(MCHP_ADC_BASE + 0x10) -#define MCHP_ADC_READ(x) REG32(MCHP_ADC_BASE + 0x14 + ((x) * 0x4)) +#define MCHP_ADC_CTRL REG32(MCHP_ADC_BASE + 0x0) +#define MCHP_ADC_DELAY REG32(MCHP_ADC_BASE + 0x4) +#define MCHP_ADC_STS REG32(MCHP_ADC_BASE + 0x8) +#define MCHP_ADC_SINGLE REG32(MCHP_ADC_BASE + 0xc) +#define MCHP_ADC_REPEAT REG32(MCHP_ADC_BASE + 0x10) +#define MCHP_ADC_READ(x) REG32(MCHP_ADC_BASE + 0x14 + ((x)*0x4)) /* Hibernation timer */ -#define MCHP_HTIMER_PRELOAD(x) REG16(MCHP_HTIMER_ADDR(x) + 0x0) -#define MCHP_HTIMER_CONTROL(x) REG16(MCHP_HTIMER_ADDR(x) + 0x4) -#define MCHP_HTIMER_COUNT(x) REG16(MCHP_HTIMER_ADDR(x) + 0x8) +#define MCHP_HTIMER_PRELOAD(x) REG16(MCHP_HTIMER_ADDR(x) + 0x0) +#define MCHP_HTIMER_CONTROL(x) REG16(MCHP_HTIMER_ADDR(x) + 0x4) +#define MCHP_HTIMER_COUNT(x) REG16(MCHP_HTIMER_ADDR(x) + 0x8) /* Week timer and BGPO control */ -#define MCHP_WKTIMER_CTRL REG32(MCHP_WKTIMER_BASE + 0) -#define MCHP_WKTIMER_ALARM_CNT REG32(MCHP_WKTIMER_BASE + 0x04) -#define MCHP_WKTIMER_COMPARE REG32(MCHP_WKTIMER_BASE + 0x08) -#define MCHP_WKTIMER_CLK_DIV REG32(MCHP_WKTIMER_BASE + 0x0c) -#define MCHP_WKTIMER_SUBSEC_ISEL REG32(MCHP_WKTIMER_BASE + 0x10) -#define MCHP_WKTIMER_SUBWK_CTRL REG32(MCHP_WKTIMER_BASE + 0x14) -#define MCHP_WKTIMER_SUBWK_ALARM REG32(MCHP_WKTIMER_BASE + 0x18) -#define MCHP_WKTIMER_BGPO_DATA REG32(MCHP_WKTIMER_BASE + 0x1c) -#define MCHP_WKTIMER_BGPO_POWER REG32(MCHP_WKTIMER_BASE + 0x20) -#define MCHP_WKTIMER_BGPO_RESET REG32(MCHP_WKTIMER_BASE + 0x24) +#define MCHP_WKTIMER_CTRL REG32(MCHP_WKTIMER_BASE + 0) +#define MCHP_WKTIMER_ALARM_CNT REG32(MCHP_WKTIMER_BASE + 0x04) +#define MCHP_WKTIMER_COMPARE REG32(MCHP_WKTIMER_BASE + 0x08) +#define MCHP_WKTIMER_CLK_DIV REG32(MCHP_WKTIMER_BASE + 0x0c) +#define MCHP_WKTIMER_SUBSEC_ISEL REG32(MCHP_WKTIMER_BASE + 0x10) +#define MCHP_WKTIMER_SUBWK_CTRL REG32(MCHP_WKTIMER_BASE + 0x14) +#define MCHP_WKTIMER_SUBWK_ALARM REG32(MCHP_WKTIMER_BASE + 0x18) +#define MCHP_WKTIMER_BGPO_DATA REG32(MCHP_WKTIMER_BASE + 0x1c) +#define MCHP_WKTIMER_BGPO_POWER REG32(MCHP_WKTIMER_BASE + 0x20) +#define MCHP_WKTIMER_BGPO_RESET REG32(MCHP_WKTIMER_BASE + 0x24) /* Quad Master SPI (QMSPI) */ -#define MCHP_QMSPI0_MODE REG32(MCHP_QMSPI0_BASE + 0x00) -#define MCHP_QMSPI0_MODE_ACT_SRST REG8(MCHP_QMSPI0_BASE + 0x00) -#define MCHP_QMSPI0_MODE_SPI_MODE REG8(MCHP_QMSPI0_BASE + 0x01) -#define MCHP_QMSPI0_MODE_FDIV REG8(MCHP_QMSPI0_BASE + 0x02) -#define MCHP_QMSPI0_CTRL REG32(MCHP_QMSPI0_BASE + 0x04) -#define MCHP_QMSPI0_EXE REG8(MCHP_QMSPI0_BASE + 0x08) -#define MCHP_QMSPI0_IFCTRL REG8(MCHP_QMSPI0_BASE + 0x0C) -#define MCHP_QMSPI0_STS REG32(MCHP_QMSPI0_BASE + 0x10) -#define MCHP_QMSPI0_BUFCNT_STS REG32(MCHP_QMSPI0_BASE + 0x14) -#define MCHP_QMSPI0_IEN REG32(MCHP_QMSPI0_BASE + 0x18) -#define MCHP_QMSPI0_BUFCNT_TRIG REG32(MCHP_QMSPI0_BASE + 0x1C) -#define MCHP_QMSPI0_TX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_TX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x20) -#define MCHP_QMSPI0_RX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_RX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x24) -#define MCHP_QMSPI0_DESCR(x) \ - REG32(MCHP_QMSPI0_BASE + 0x30 + ((x) * 4)) +#define MCHP_QMSPI0_MODE REG32(MCHP_QMSPI0_BASE + 0x00) +#define MCHP_QMSPI0_MODE_ACT_SRST REG8(MCHP_QMSPI0_BASE + 0x00) +#define MCHP_QMSPI0_MODE_SPI_MODE REG8(MCHP_QMSPI0_BASE + 0x01) +#define MCHP_QMSPI0_MODE_FDIV REG8(MCHP_QMSPI0_BASE + 0x02) +#define MCHP_QMSPI0_CTRL REG32(MCHP_QMSPI0_BASE + 0x04) +#define MCHP_QMSPI0_EXE REG8(MCHP_QMSPI0_BASE + 0x08) +#define MCHP_QMSPI0_IFCTRL REG8(MCHP_QMSPI0_BASE + 0x0C) +#define MCHP_QMSPI0_STS REG32(MCHP_QMSPI0_BASE + 0x10) +#define MCHP_QMSPI0_BUFCNT_STS REG32(MCHP_QMSPI0_BASE + 0x14) +#define MCHP_QMSPI0_IEN REG32(MCHP_QMSPI0_BASE + 0x18) +#define MCHP_QMSPI0_BUFCNT_TRIG REG32(MCHP_QMSPI0_BASE + 0x1C) +#define MCHP_QMSPI0_TX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x20) +#define MCHP_QMSPI0_TX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x20) +#define MCHP_QMSPI0_TX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x20) +#define MCHP_QMSPI0_TX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x20) +#define MCHP_QMSPI0_RX_FIFO_ADDR (MCHP_QMSPI0_BASE + 0x24) +#define MCHP_QMSPI0_RX_FIFO8 REG8(MCHP_QMSPI0_BASE + 0x24) +#define MCHP_QMSPI0_RX_FIFO16 REG16(MCHP_QMSPI0_BASE + 0x24) +#define MCHP_QMSPI0_RX_FIFO32 REG32(MCHP_QMSPI0_BASE + 0x24) +#define MCHP_QMSPI0_DESCR(x) REG32(MCHP_QMSPI0_BASE + 0x30 + ((x)*4)) /* Bits in MCHP_QMSPI0_MODE */ -#define MCHP_QMSPI_M_ACTIVATE BIT(0) -#define MCHP_QMSPI_M_SOFT_RESET BIT(1) -#define MCHP_QMSPI_M_SPI_MODE_MASK (0x7ul << 8) -#define MCHP_QMSPI_M_SPI_MODE0 (0x0ul << 8) -#define MCHP_QMSPI_M_SPI_MODE3 (0x3ul << 8) -#define MCHP_QMSPI_M_SPI_MODE0_48M (0x4ul << 8) -#define MCHP_QMSPI_M_SPI_MODE3_48M (0x7ul << 8) +#define MCHP_QMSPI_M_ACTIVATE BIT(0) +#define MCHP_QMSPI_M_SOFT_RESET BIT(1) +#define MCHP_QMSPI_M_SPI_MODE_MASK (0x7ul << 8) +#define MCHP_QMSPI_M_SPI_MODE0 (0x0ul << 8) +#define MCHP_QMSPI_M_SPI_MODE3 (0x3ul << 8) +#define MCHP_QMSPI_M_SPI_MODE0_48M (0x4ul << 8) +#define MCHP_QMSPI_M_SPI_MODE3_48M (0x7ul << 8) /* * clock divider is 8-bit field in bits[23:16] * [1, 255] -> 48MHz / [1, 255], 0 -> 48MHz / 256 */ -#define MCHP_QMSPI_M_CLKDIV_BITPOS 16 -#define MCHP_QMSPI_M_CLKDIV_48M (1ul << 16) -#define MCHP_QMSPI_M_CLKDIV_24M (2ul << 16) -#define MCHP_QMSPI_M_CLKDIV_16M (3ul << 16) -#define MCHP_QMSPI_M_CLKDIV_12M (4ul << 16) -#define MCHP_QMSPI_M_CLKDIV_8M (6ul << 16) -#define MCHP_QMSPI_M_CLKDIV_6M (8ul << 16) -#define MCHP_QMSPI_M_CLKDIV_1M (48ul << 16) -#define MCHP_QMSPI_M_CLKDIV_188K (0x100ul << 16) +#define MCHP_QMSPI_M_CLKDIV_BITPOS 16 +#define MCHP_QMSPI_M_CLKDIV_48M (1ul << 16) +#define MCHP_QMSPI_M_CLKDIV_24M (2ul << 16) +#define MCHP_QMSPI_M_CLKDIV_16M (3ul << 16) +#define MCHP_QMSPI_M_CLKDIV_12M (4ul << 16) +#define MCHP_QMSPI_M_CLKDIV_8M (6ul << 16) +#define MCHP_QMSPI_M_CLKDIV_6M (8ul << 16) +#define MCHP_QMSPI_M_CLKDIV_1M (48ul << 16) +#define MCHP_QMSPI_M_CLKDIV_188K (0x100ul << 16) /* Bits in MCHP_QMSPI0_CTRL and MCHP_QMSPI_DESCR(x) */ -#define MCHP_QMSPI_C_1X (0ul << 0) /* Full Duplex */ -#define MCHP_QMSPI_C_2X (1ul << 0) /* Dual IO */ -#define MCHP_QMSPI_C_4X (2ul << 0) /* Quad IO */ -#define MCHP_QMSPI_C_TX_DIS (0ul << 2) -#define MCHP_QMSPI_C_TX_DATA (1ul << 2) -#define MCHP_QMSPI_C_TX_ZEROS (2ul << 2) -#define MCHP_QMSPI_C_TX_ONES (3ul << 2) -#define MCHP_QMSPI_C_TX_DMA_DIS (0ul << 4) -#define MCHP_QMSPI_C_TX_DMA_1B (1ul << 4) -#define MCHP_QMSPI_C_TX_DMA_2B (2ul << 4) -#define MCHP_QMSPI_C_TX_DMA_4B (3ul << 4) -#define MCHP_QMSPI_C_TX_DMA_MASK (3ul << 4) -#define MCHP_QMSPI_C_RX_DIS 0 -#define MCHP_QMSPI_C_RX_EN BIT(6) -#define MCHP_QMSPI_C_RX_DMA_DIS (0ul << 7) -#define MCHP_QMSPI_C_RX_DMA_1B (1ul << 7) -#define MCHP_QMSPI_C_RX_DMA_2B (2ul << 7) -#define MCHP_QMSPI_C_RX_DMA_4B (3ul << 7) -#define MCHP_QMSPI_C_RX_DMA_MASK (3ul << 7) -#define MCHP_QMSPI_C_NO_CLOSE 0 -#define MCHP_QMSPI_C_CLOSE BIT(9) -#define MCHP_QMSPI_C_XFRU_BITS (0ul << 10) -#define MCHP_QMSPI_C_XFRU_1B (1ul << 10) -#define MCHP_QMSPI_C_XFRU_4B (2ul << 10) -#define MCHP_QMSPI_C_XFRU_16B (3ul << 10) -#define MCHP_QMSPI_C_XFRU_MASK (3ul << 10) +#define MCHP_QMSPI_C_1X (0ul << 0) /* Full Duplex */ +#define MCHP_QMSPI_C_2X (1ul << 0) /* Dual IO */ +#define MCHP_QMSPI_C_4X (2ul << 0) /* Quad IO */ +#define MCHP_QMSPI_C_TX_DIS (0ul << 2) +#define MCHP_QMSPI_C_TX_DATA (1ul << 2) +#define MCHP_QMSPI_C_TX_ZEROS (2ul << 2) +#define MCHP_QMSPI_C_TX_ONES (3ul << 2) +#define MCHP_QMSPI_C_TX_DMA_DIS (0ul << 4) +#define MCHP_QMSPI_C_TX_DMA_1B (1ul << 4) +#define MCHP_QMSPI_C_TX_DMA_2B (2ul << 4) +#define MCHP_QMSPI_C_TX_DMA_4B (3ul << 4) +#define MCHP_QMSPI_C_TX_DMA_MASK (3ul << 4) +#define MCHP_QMSPI_C_RX_DIS 0 +#define MCHP_QMSPI_C_RX_EN BIT(6) +#define MCHP_QMSPI_C_RX_DMA_DIS (0ul << 7) +#define MCHP_QMSPI_C_RX_DMA_1B (1ul << 7) +#define MCHP_QMSPI_C_RX_DMA_2B (2ul << 7) +#define MCHP_QMSPI_C_RX_DMA_4B (3ul << 7) +#define MCHP_QMSPI_C_RX_DMA_MASK (3ul << 7) +#define MCHP_QMSPI_C_NO_CLOSE 0 +#define MCHP_QMSPI_C_CLOSE BIT(9) +#define MCHP_QMSPI_C_XFRU_BITS (0ul << 10) +#define MCHP_QMSPI_C_XFRU_1B (1ul << 10) +#define MCHP_QMSPI_C_XFRU_4B (2ul << 10) +#define MCHP_QMSPI_C_XFRU_16B (3ul << 10) +#define MCHP_QMSPI_C_XFRU_MASK (3ul << 10) /* Control */ -#define MCHP_QMSPI_C_START_DESCR_BITPOS 12 -#define MCHP_QMSPI_C_START_DESCR_MASK (0xFul << 12) -#define MCHP_QMSPI_C_DESCR_MODE_EN BIT(16) +#define MCHP_QMSPI_C_START_DESCR_BITPOS 12 +#define MCHP_QMSPI_C_START_DESCR_MASK (0xFul << 12) +#define MCHP_QMSPI_C_DESCR_MODE_EN BIT(16) /* Descriptors, indicates the current descriptor is the last */ -#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS 12 -#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0xFul -#define MCHP_QMSPI_C_NEXT_DESCR_MASK \ - ((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12) +#define MCHP_QMSPI_C_NEXT_DESCR_BITPOS 12 +#define MCHP_QMSPI_C_NEXT_DESCR_MASK0 0xFul +#define MCHP_QMSPI_C_NEXT_DESCR_MASK ((MCHP_QMSPI_C_NEXT_DESCR_MASK0) << 12) #define MCHP_QMSPI_C_NXTD(n) ((n) << 12) -#define MCHP_QMSPI_C_DESCR_LAST BIT(16) +#define MCHP_QMSPI_C_DESCR_LAST BIT(16) /* * Total transfer length is the count in this field * scaled by units in MCHP_QMSPI_CTRL_XFRU_xxxx */ -#define MCHP_QMSPI_C_NUM_UNITS_BITPOS 17 -#define MCHP_QMSPI_C_MAX_UNITS 0x7ffful -#define MCHP_QMSPI_C_NUM_UNITS_MASK0 0x7ffful -#define MCHP_QMSPI_C_NUM_UNITS_MASK \ - ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17) +#define MCHP_QMSPI_C_NUM_UNITS_BITPOS 17 +#define MCHP_QMSPI_C_MAX_UNITS 0x7ffful +#define MCHP_QMSPI_C_NUM_UNITS_MASK0 0x7ffful +#define MCHP_QMSPI_C_NUM_UNITS_MASK ((MCHP_QMSPI_C_NUM_UNITS_MASK0) << 17) /* Bits in MCHP_QMSPI0_EXE */ -#define MCHP_QMSPI_EXE_START BIT(0) -#define MCHP_QMSPI_EXE_STOP BIT(1) -#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) +#define MCHP_QMSPI_EXE_START BIT(0) +#define MCHP_QMSPI_EXE_STOP BIT(1) +#define MCHP_QMSPI_EXE_CLR_FIFOS BIT(2) /* MCHP QMSPI FIFO Sizes */ -#define MCHP_QMSPI_TX_FIFO_LEN 8 -#define MCHP_QMSPI_RX_FIFO_LEN 8 +#define MCHP_QMSPI_TX_FIFO_LEN 8 +#define MCHP_QMSPI_RX_FIFO_LEN 8 /* Bits in MCHP_QMSPI0_STS and MCHP_QMSPI0_IEN */ -#define MCHP_QMSPI_STS_DONE BIT(0) -#define MCHP_QMSPI_STS_DMA_DONE BIT(1) -#define MCHP_QMSPI_STS_TX_BUFF_ERR BIT(2) -#define MCHP_QMSPI_STS_RX_BUFF_ERR BIT(3) -#define MCHP_QMSPI_STS_PROG_ERR BIT(4) -#define MCHP_QMSPI_STS_TX_BUFF_FULL BIT(8) -#define MCHP_QMSPI_STS_TX_BUFF_EMPTY BIT(9) -#define MCHP_QMSPI_STS_TX_BUFF_REQ BIT(10) -#define MCHP_QMSPI_STS_TX_BUFF_STALL BIT(11) /* status only */ -#define MCHP_QMSPI_STS_RX_BUFF_FULL BIT(12) -#define MCHP_QMSPI_STS_RX_BUFF_EMPTY BIT(13) -#define MCHP_QMSPI_STS_RX_BUFF_REQ BIT(14) -#define MCHP_QMSPI_STS_RX_BUFF_STALL BIT(15) /* status only */ -#define MCHP_QMSPI_STS_ACTIVE BIT(16) /* status only */ +#define MCHP_QMSPI_STS_DONE BIT(0) +#define MCHP_QMSPI_STS_DMA_DONE BIT(1) +#define MCHP_QMSPI_STS_TX_BUFF_ERR BIT(2) +#define MCHP_QMSPI_STS_RX_BUFF_ERR BIT(3) +#define MCHP_QMSPI_STS_PROG_ERR BIT(4) +#define MCHP_QMSPI_STS_TX_BUFF_FULL BIT(8) +#define MCHP_QMSPI_STS_TX_BUFF_EMPTY BIT(9) +#define MCHP_QMSPI_STS_TX_BUFF_REQ BIT(10) +#define MCHP_QMSPI_STS_TX_BUFF_STALL BIT(11) /* status only */ +#define MCHP_QMSPI_STS_RX_BUFF_FULL BIT(12) +#define MCHP_QMSPI_STS_RX_BUFF_EMPTY BIT(13) +#define MCHP_QMSPI_STS_RX_BUFF_REQ BIT(14) +#define MCHP_QMSPI_STS_RX_BUFF_STALL BIT(15) /* status only */ +#define MCHP_QMSPI_STS_ACTIVE BIT(16) /* status only */ /* Bits in MCHP_QMSPI0_BUFCNT (read-only) */ -#define MCHP_QMSPI_BUFCNT_TX_BITPOS 0 -#define MCHP_QMSPI_BUFCNT_TX_MASK 0xFFFFul -#define MCHP_QMSPI_BUFCNT_RX_BITPOS 16 -#define MCHP_QMSPI_BUFCNT_RX_MASK (0xFFFFul << 16) -#define MCHP_QMSPI0_ID 0 +#define MCHP_QMSPI_BUFCNT_TX_BITPOS 0 +#define MCHP_QMSPI_BUFCNT_TX_MASK 0xFFFFul +#define MCHP_QMSPI_BUFCNT_RX_BITPOS 16 +#define MCHP_QMSPI_BUFCNT_RX_MASK (0xFFFFul << 16) +#define MCHP_QMSPI0_ID 0 /* eSPI */ /* eSPI IO Component */ /* Peripheral Channel Registers */ -#define MCHP_ESPI_PC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x114) -#define MCHP_ESPI_PC_IEN REG32(MCHP_ESPI_IO_BASE + 0x118) -#define MCHP_ESPI_PC_BAR_INHIBIT_LO REG32(MCHP_ESPI_IO_BASE + 0x120) -#define MCHP_ESPI_PC_BAR_INHIBIT_HI REG32(MCHP_ESPI_IO_BASE + 0x124) -#define MCHP_ESPI_PC_BAR_INIT_LD_0C REG16(MCHP_ESPI_IO_BASE + 0x128) -#define MCHP_ESPI_PC_EC_IRQ REG8(MCHP_ESPI_IO_BASE + 0x12C) +#define MCHP_ESPI_PC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x114) +#define MCHP_ESPI_PC_IEN REG32(MCHP_ESPI_IO_BASE + 0x118) +#define MCHP_ESPI_PC_BAR_INHIBIT_LO REG32(MCHP_ESPI_IO_BASE + 0x120) +#define MCHP_ESPI_PC_BAR_INHIBIT_HI REG32(MCHP_ESPI_IO_BASE + 0x124) +#define MCHP_ESPI_PC_BAR_INIT_LD_0C REG16(MCHP_ESPI_IO_BASE + 0x128) +#define MCHP_ESPI_PC_EC_IRQ REG8(MCHP_ESPI_IO_BASE + 0x12C) /* LTR Registers */ -#define MCHP_ESPI_IO_LTR_STATUS REG16(MCHP_ESPI_IO_BASE + 0x220) -#define MCHP_ESPI_IO_LTR_IEN REG8(MCHP_ESPI_IO_BASE + 0x224) -#define MCHP_ESPI_IO_LTR_CTRL REG16(MCHP_ESPI_IO_BASE + 0x228) -#define MCHP_ESPI_IO_LTR_MSG REG16(MCHP_ESPI_IO_BASE + 0x22C) +#define MCHP_ESPI_IO_LTR_STATUS REG16(MCHP_ESPI_IO_BASE + 0x220) +#define MCHP_ESPI_IO_LTR_IEN REG8(MCHP_ESPI_IO_BASE + 0x224) +#define MCHP_ESPI_IO_LTR_CTRL REG16(MCHP_ESPI_IO_BASE + 0x228) +#define MCHP_ESPI_IO_LTR_MSG REG16(MCHP_ESPI_IO_BASE + 0x22C) /* OOB Channel Registers */ -#define MCHP_ESPI_OOB_RX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x240) -#define MCHP_ESPI_OOB_RX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x244) -#define MCHP_ESPI_OOB_TX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x248) -#define MCHP_ESPI_OOB_TX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x24C) -#define MCHP_ESPI_OOB_RX_LEN REG32(MCHP_ESPI_IO_BASE + 0x250) -#define MCHP_ESPI_OOB_TX_LEN REG32(MCHP_ESPI_IO_BASE + 0x254) -#define MCHP_ESPI_OOB_RX_CTL REG32(MCHP_ESPI_IO_BASE + 0x258) -#define MCHP_ESPI_OOB_RX_IEN REG8(MCHP_ESPI_IO_BASE + 0x25C) -#define MCHP_ESPI_OOB_RX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x260) -#define MCHP_ESPI_OOB_TX_CTL REG32(MCHP_ESPI_IO_BASE + 0x264) -#define MCHP_ESPI_OOB_TX_IEN REG8(MCHP_ESPI_IO_BASE + 0x268) -#define MCHP_ESPI_OOB_TX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x26C) +#define MCHP_ESPI_OOB_RX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x240) +#define MCHP_ESPI_OOB_RX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x244) +#define MCHP_ESPI_OOB_TX_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x248) +#define MCHP_ESPI_OOB_TX_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x24C) +#define MCHP_ESPI_OOB_RX_LEN REG32(MCHP_ESPI_IO_BASE + 0x250) +#define MCHP_ESPI_OOB_TX_LEN REG32(MCHP_ESPI_IO_BASE + 0x254) +#define MCHP_ESPI_OOB_RX_CTL REG32(MCHP_ESPI_IO_BASE + 0x258) +#define MCHP_ESPI_OOB_RX_IEN REG8(MCHP_ESPI_IO_BASE + 0x25C) +#define MCHP_ESPI_OOB_RX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x260) +#define MCHP_ESPI_OOB_TX_CTL REG32(MCHP_ESPI_IO_BASE + 0x264) +#define MCHP_ESPI_OOB_TX_IEN REG8(MCHP_ESPI_IO_BASE + 0x268) +#define MCHP_ESPI_OOB_TX_STATUS REG32(MCHP_ESPI_IO_BASE + 0x26C) /* Flash Channel Registers */ -#define MCHP_ESPI_FC_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x280) -#define MCHP_ESPI_FC_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x284) -#define MCHP_ESPI_FC_BUF_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x288) -#define MCHP_ESPI_FC_BUF_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x28C) -#define MCHP_ESPI_FC_XFR_LEN REG32(MCHP_ESPI_IO_BASE + 0x290) -#define MCHP_ESPI_FC_CTL REG32(MCHP_ESPI_IO_BASE + 0x294) -#define MCHP_ESPI_FC_IEN REG8(MCHP_ESPI_IO_BASE + 0x298) -#define MCHP_ESPI_FC_CONFIG REG32(MCHP_ESPI_IO_BASE + 0x29C) -#define MCHP_ESPI_FC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x2A0) +#define MCHP_ESPI_FC_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x280) +#define MCHP_ESPI_FC_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x284) +#define MCHP_ESPI_FC_BUF_ADDR_LO REG32(MCHP_ESPI_IO_BASE + 0x288) +#define MCHP_ESPI_FC_BUF_ADDR_HI REG32(MCHP_ESPI_IO_BASE + 0x28C) +#define MCHP_ESPI_FC_XFR_LEN REG32(MCHP_ESPI_IO_BASE + 0x290) +#define MCHP_ESPI_FC_CTL REG32(MCHP_ESPI_IO_BASE + 0x294) +#define MCHP_ESPI_FC_IEN REG8(MCHP_ESPI_IO_BASE + 0x298) +#define MCHP_ESPI_FC_CONFIG REG32(MCHP_ESPI_IO_BASE + 0x29C) +#define MCHP_ESPI_FC_STATUS REG32(MCHP_ESPI_IO_BASE + 0x2A0) /* VWire Channel Registers */ -#define MCHP_ESPI_VW_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2B0) +#define MCHP_ESPI_VW_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2B0) /* Global Registers */ /* 32-bit register containing CAP_ID/CAP0/CAP1/PC_CAP */ -#define MCHP_ESPI_IO_REG32_A REG32(MCHP_ESPI_IO_BASE + 0x2E0) -#define MCHP_ESPI_IO_CAP_ID REG8(MCHP_ESPI_IO_BASE + 0x2E0) -#define MCHP_ESPI_IO_CAP0 REG8(MCHP_ESPI_IO_BASE + 0x2E1) -#define MCHP_ESPI_IO_CAP1 REG8(MCHP_ESPI_IO_BASE + 0x2E2) -#define MCHP_ESPI_IO_PC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E3) +#define MCHP_ESPI_IO_REG32_A REG32(MCHP_ESPI_IO_BASE + 0x2E0) +#define MCHP_ESPI_IO_CAP_ID REG8(MCHP_ESPI_IO_BASE + 0x2E0) +#define MCHP_ESPI_IO_CAP0 REG8(MCHP_ESPI_IO_BASE + 0x2E1) +#define MCHP_ESPI_IO_CAP1 REG8(MCHP_ESPI_IO_BASE + 0x2E2) +#define MCHP_ESPI_IO_PC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E3) /* 32-bit register containing VW_CAP/OOB_CAP/FC_CAP/PC_READY */ -#define MCHP_ESPI_IO_REG32_B REG32(MCHP_ESPI_IO_BASE + 0x2E4) -#define MCHP_ESPI_IO_VW_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E4) -#define MCHP_ESPI_IO_OOB_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E5) -#define MCHP_ESPI_IO_FC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E6) -#define MCHP_ESPI_IO_PC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E7) +#define MCHP_ESPI_IO_REG32_B REG32(MCHP_ESPI_IO_BASE + 0x2E4) +#define MCHP_ESPI_IO_VW_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E4) +#define MCHP_ESPI_IO_OOB_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E5) +#define MCHP_ESPI_IO_FC_CAP REG8(MCHP_ESPI_IO_BASE + 0x2E6) +#define MCHP_ESPI_IO_PC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E7) /* 32-bit register containing OOB_READY/FC_READY/RESET_STATUS/RESET_IEN */ -#define MCHP_ESPI_IO_REG32_C REG32(MCHP_ESPI_IO_BASE + 0x2E8) -#define MCHP_ESPI_IO_OOB_READY REG8(MCHP_ESPI_IO_BASE + 0x2E8) -#define MCHP_ESPI_IO_FC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E9) -#define MCHP_ESPI_IO_RESET_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2EA) -#define MCHP_ESPI_IO_RESET_IEN REG8(MCHP_ESPI_IO_BASE + 0x2EB) +#define MCHP_ESPI_IO_REG32_C REG32(MCHP_ESPI_IO_BASE + 0x2E8) +#define MCHP_ESPI_IO_OOB_READY REG8(MCHP_ESPI_IO_BASE + 0x2E8) +#define MCHP_ESPI_IO_FC_READY REG8(MCHP_ESPI_IO_BASE + 0x2E9) +#define MCHP_ESPI_IO_RESET_STATUS REG8(MCHP_ESPI_IO_BASE + 0x2EA) +#define MCHP_ESPI_IO_RESET_IEN REG8(MCHP_ESPI_IO_BASE + 0x2EB) /* 32-bit register containing PLTRST_SRC/VW_READY */ -#define MCHP_ESPI_IO_REG32_D REG32(MCHP_ESPI_IO_BASE + 0x2EC) -#define MCHP_ESPI_IO_PLTRST_SRC REG8(MCHP_ESPI_IO_BASE + 0x2EC) -#define MCHP_ESPI_IO_VW_READY REG8(MCHP_ESPI_IO_BASE + 0x2ED) +#define MCHP_ESPI_IO_REG32_D REG32(MCHP_ESPI_IO_BASE + 0x2EC) +#define MCHP_ESPI_IO_PLTRST_SRC REG8(MCHP_ESPI_IO_BASE + 0x2EC) +#define MCHP_ESPI_IO_VW_READY REG8(MCHP_ESPI_IO_BASE + 0x2ED) /* Bits in MCHP_ESPI_IO_CAP0 */ -#define MCHP_ESPI_CAP0_PC_SUPP 0x01 -#define MCHP_ESPI_CAP0_VW_SUPP 0x02 -#define MCHP_ESPI_CAP0_OOB_SUPP 0x04 -#define MCHP_ESPI_CAP0_FC_SUPP 0x08 -#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP (MCHP_ESPI_CAP0_PC_SUPP | \ - MCHP_ESPI_CAP0_VW_SUPP | \ - MCHP_ESPI_CAP0_OOB_SUPP | \ - MCHP_ESPI_CAP0_FC_SUPP) +#define MCHP_ESPI_CAP0_PC_SUPP 0x01 +#define MCHP_ESPI_CAP0_VW_SUPP 0x02 +#define MCHP_ESPI_CAP0_OOB_SUPP 0x04 +#define MCHP_ESPI_CAP0_FC_SUPP 0x08 +#define MCHP_ESPI_CAP0_ALL_CHAN_SUPP \ + (MCHP_ESPI_CAP0_PC_SUPP | MCHP_ESPI_CAP0_VW_SUPP | \ + MCHP_ESPI_CAP0_OOB_SUPP | MCHP_ESPI_CAP0_FC_SUPP) /* Bits in MCHP_ESPI_IO_CAP1 */ -#define MCHP_ESPI_CAP1_RW_MASK 0x37 -#define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07 -#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0 -#define MCHP_ESPI_CAP1_MAX_FREQ_25M 1 -#define MCHP_ESPI_CAP1_MAX_FREQ_33M 2 -#define MCHP_ESPI_CAP1_MAX_FREQ_50M 3 -#define MCHP_ESPI_CAP1_MAX_FREQ_66M 4 -#define MCHP_ESPI_CAP1_SINGLE_MODE 0 -#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE BIT(0) -#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE BIT(1) -#define MCHP_ESPI_CAP1_ALL_MODE (MCHP_ESPI_CAP1_SINGLE_MODE | \ - MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \ - MCHP_ESPI_CAP1_SINGLE_QUAD_MODE) -#define MCHP_ESPI_CAP1_IO_BITPOS 4 -#define MCHP_ESPI_CAP1_IO_MASK0 0x03 -#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << MCHP_ESPI_CAP1_IO_BITPOS) -#define MCHP_ESPI_CAP1_IO1_VAL 0x00 -#define MCHP_ESPI_CAP1_IO12_VAL 0x01 -#define MCHP_ESPI_CAP1_IO24_VAL 0x02 -#define MCHP_ESPI_CAP1_IO124_VAL 0x03 -#define MCHP_ESPI_CAP1_IO1 (0x00 << 4) -#define MCHP_ESPI_CAP1_IO12 (0x01 << 4) -#define MCHP_ESPI_CAP1_IO24 (0x02 << 4) -#define MCHP_ESPI_CAP1_IO124 (0x03 << 4) +#define MCHP_ESPI_CAP1_RW_MASK 0x37 +#define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07 +#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0 +#define MCHP_ESPI_CAP1_MAX_FREQ_25M 1 +#define MCHP_ESPI_CAP1_MAX_FREQ_33M 2 +#define MCHP_ESPI_CAP1_MAX_FREQ_50M 3 +#define MCHP_ESPI_CAP1_MAX_FREQ_66M 4 +#define MCHP_ESPI_CAP1_SINGLE_MODE 0 +#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE BIT(0) +#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE BIT(1) +#define MCHP_ESPI_CAP1_ALL_MODE \ + (MCHP_ESPI_CAP1_SINGLE_MODE | MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \ + MCHP_ESPI_CAP1_SINGLE_QUAD_MODE) +#define MCHP_ESPI_CAP1_IO_BITPOS 4 +#define MCHP_ESPI_CAP1_IO_MASK0 0x03 +#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << MCHP_ESPI_CAP1_IO_BITPOS) +#define MCHP_ESPI_CAP1_IO1_VAL 0x00 +#define MCHP_ESPI_CAP1_IO12_VAL 0x01 +#define MCHP_ESPI_CAP1_IO24_VAL 0x02 +#define MCHP_ESPI_CAP1_IO124_VAL 0x03 +#define MCHP_ESPI_CAP1_IO1 (0x00 << 4) +#define MCHP_ESPI_CAP1_IO12 (0x01 << 4) +#define MCHP_ESPI_CAP1_IO24 (0x02 << 4) +#define MCHP_ESPI_CAP1_IO124 (0x03 << 4) /* Bits in MCHP_ESPI_IO_RESET_STATUS and MCHP_ESPI_IO_RESET_IEN */ -#define MCHP_ESPI_RST_PIN_MASK BIT(1) -#define MCHP_ESPI_RST_CHG_STS BIT(0) -#define MCHP_ESPI_RST_IEN BIT(0) +#define MCHP_ESPI_RST_PIN_MASK BIT(1) +#define MCHP_ESPI_RST_CHG_STS BIT(0) +#define MCHP_ESPI_RST_IEN BIT(0) /* Bits in MCHP_ESPI_IO_PLTRST_SRC */ -#define MCHP_ESPI_PLTRST_SRC_VW 0 -#define MCHP_ESPI_PLTRST_SRC_PIN 1 +#define MCHP_ESPI_PLTRST_SRC_VW 0 +#define MCHP_ESPI_PLTRST_SRC_PIN 1 /* * eSPI Slave Activate Register * bit[0] = 0 de-active block is clock-gates * bit[0] = 1 block is powered and functional */ -#define MCHP_ESPI_ACTIVATE REG8(MCHP_ESPI_IO_BASE + 0x330) +#define MCHP_ESPI_ACTIVATE REG8(MCHP_ESPI_IO_BASE + 0x330) /* * IO BAR's starting at offset 0x134 * b[16]=virtualized R/W @@ -554,30 +549,24 @@ * b[13:8]=Logical Device Number RO * b[7:0]=mask */ -#define MCHP_ESPI_IO_BAR_CTL(x) \ - REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134) +#define MCHP_ESPI_IO_BAR_CTL(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134) /* access mask field of eSPI IO BAR Control register */ -#define MCHP_ESPI_IO_BAR_CTL_MASK(x) \ - REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x134) +#define MCHP_ESPI_IO_BAR_CTL_MASK(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x134) /* * IO BAR's starting at offset 0x334 * b[31:16] = I/O address * b[15:1]=0 reserved * b[0] = valid */ -#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334) -#define MCHP_ESPI_IO_BAR_VALID(x) \ - REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x334) -#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) \ - REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336) -#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) \ - REG8(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x337) -#define MCHP_ESPI_IO_BAR_ADDR(x) \ - REG16(MCHP_ESPI_IO_BASE + ((x) * 4) + 0x336) +#define MCHP_ESPI_IO_BAR(x) REG32(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334) +#define MCHP_ESPI_IO_BAR_VALID(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x334) +#define MCHP_ESPI_IO_BAR_ADDR_LSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336) +#define MCHP_ESPI_IO_BAR_ADDR_MSB(x) REG8(MCHP_ESPI_IO_BASE + ((x)*4) + 0x337) +#define MCHP_ESPI_IO_BAR_ADDR(x) REG16(MCHP_ESPI_IO_BASE + ((x)*4) + 0x336) /* eSPI Serial IRQ registers */ -#define MCHP_ESPI_IO_SERIRQ_REG(x) REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x)) +#define MCHP_ESPI_IO_SERIRQ_REG(x) REG8(MCHP_ESPI_IO_BASE + 0x3ac + (x)) /* eSPI Virtual Wire Error Register */ -#define MCHP_ESPI_IO_VW_ERROR REG8(MCHP_ESPI_IO_BASE + 0x3f0) +#define MCHP_ESPI_IO_VW_ERROR REG8(MCHP_ESPI_IO_BASE + 0x3f0) /* * eSPI Logical Device Memory Host BAR's to specify Host memory * base address and valid bit. @@ -586,16 +575,15 @@ * b[15:1]=0(reserved) * b[79:16]=eSPI bus memory address(Host address space) */ -#define MCHP_ESPI_MBAR_VALID(x) \ - REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x130) +#define MCHP_ESPI_MBAR_VALID(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x130) #define MCHP_ESPI_MBAR_HOST_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x132) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x132) #define MCHP_ESPI_MBAR_HOST_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x134) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x134) #define MCHP_ESPI_MBAR_HOST_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x136) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x136) #define MCHP_ESPI_MBAR_HOST_ADDR_48_63(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x138) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x138) /* * eSPI SRAM BAR's * b[0,3,8:15] = 0 reserved @@ -603,28 +591,27 @@ * b[7:4] = size * b[79:16] = Host address */ -#define MCHP_ESPI_SRAM_BAR_CFG(x) \ - REG8(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ac) +#define MCHP_ESPI_SRAM_BAR_CFG(x) REG8(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ac) #define MCHP_ESPI_SRAM_BAR_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1ae) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1ae) #define MCHP_ESPI_SRAM_BAR_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b0) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b0) #define MCHP_ESPI_SRAM_BAR_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b2) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b2) #define MCHP_ESPI_SRAM_BAR_ADDR_48_63(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x1b4) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x1b4) /* eSPI Memory Bus Master Registers */ -#define MCHP_ESPI_BM_STATUS REG32(MCHP_ESPI_MEM_BASE + 0x200) -#define MCHP_ESPI_BM_IEN REG32(MCHP_ESPI_MEM_BASE + 0x204) -#define MCHP_ESPI_BM_CONFIG REG32(MCHP_ESPI_MEM_BASE + 0x208) -#define MCHP_ESPI_BM1_CTL REG32(MCHP_ESPI_MEM_BASE + 0x210) -#define MCHP_ESPI_BM1_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x214) -#define MCHP_ESPI_BM1_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x218) -#define MCHP_ESPI_BM1_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x21c) -#define MCHP_ESPI_BM2_CTL REG32(MCHP_ESPI_MEM_BASE + 0x224) -#define MCHP_ESPI_BM2_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x228) -#define MCHP_ESPI_BM2_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x22c) -#define MCHP_ESPI_BM2_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x230) +#define MCHP_ESPI_BM_STATUS REG32(MCHP_ESPI_MEM_BASE + 0x200) +#define MCHP_ESPI_BM_IEN REG32(MCHP_ESPI_MEM_BASE + 0x204) +#define MCHP_ESPI_BM_CONFIG REG32(MCHP_ESPI_MEM_BASE + 0x208) +#define MCHP_ESPI_BM1_CTL REG32(MCHP_ESPI_MEM_BASE + 0x210) +#define MCHP_ESPI_BM1_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x214) +#define MCHP_ESPI_BM1_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x218) +#define MCHP_ESPI_BM1_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x21c) +#define MCHP_ESPI_BM2_CTL REG32(MCHP_ESPI_MEM_BASE + 0x224) +#define MCHP_ESPI_BM2_HOST_ADDR_LO REG32(MCHP_ESPI_MEM_BASE + 0x228) +#define MCHP_ESPI_BM2_HOST_ADDR_HI REG32(MCHP_ESPI_MEM_BASE + 0x22c) +#define MCHP_ESPI_BM2_EC_ADDR REG32(MCHP_ESPI_MEM_BASE + 0x230) /* * eSPI Memory BAR's for Logical Devices * b[0] = Valid @@ -637,30 +624,29 @@ * * BAR's start at offset 0x330 */ -#define MCHP_ESPI_MBAR_EC_VSIZE(x) \ - REG32(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x330) +#define MCHP_ESPI_MBAR_EC_VSIZE(x) REG32(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x330) #define MCHP_ESPI_MBAR_EC_ADDR_0_15(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x332) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x332) #define MCHP_ESPI_MBAR_EC_ADDR_16_31(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x334) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x334) #define MCHP_ESPI_MBAR_EC_ADDR_32_47(x) \ - REG16(MCHP_ESPI_MEM_BASE + ((x) * 10) + 0x336) + REG16(MCHP_ESPI_MEM_BASE + ((x)*10) + 0x336) /* eSPI Virtual Wire registers */ -#define MCHP_ESPI_MSVW_LEN 12 -#define MCHP_ESPI_SMVW_LEN 8 +#define MCHP_ESPI_MSVW_LEN 12 +#define MCHP_ESPI_SMVW_LEN 8 #define MCHP_ESPI_MSVW_ADDR(n) \ ((MCHP_ESPI_MSVW_BASE) + ((n) * (MCHP_ESPI_MSVW_LEN))) #define MCHP_ESPI_MSVW_MTOS_BITPOS 4 -#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO 0 -#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI 1 -#define MCHP_ESPI_MSVW_IRQSEL_DISABLED 4 -#define MCHP_ESPI_MSVW_IRQSEL_RISING 0x0d -#define MCHP_ESPI_MSVW_IRQSEL_FALLING 0x0e -#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES 0x0f +#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_LO 0 +#define MCHP_ESPI_MSVW_IRQSEL_LEVEL_HI 1 +#define MCHP_ESPI_MSVW_IRQSEL_DISABLED 4 +#define MCHP_ESPI_MSVW_IRQSEL_RISING 0x0d +#define MCHP_ESPI_MSVW_IRQSEL_FALLING 0x0e +#define MCHP_ESPI_MSVW_IRQSEL_BOTH_EDGES 0x0f /* * Mapping of eSPI Master Host VWire group indices to @@ -668,73 +654,60 @@ * MSVW_xy where xy = PCH VWire number. * Each PCH VWire number controls 4 virtual wires. */ -#define MSVW_H02 0 -#define MSVW_H03 1 -#define MSVW_H07 2 -#define MSVW_H41 3 -#define MSVW_H42 4 -#define MSVW_H43 5 -#define MSVW_H44 6 -#define MSVW_H47 7 -#define MSVW_H4A 8 -#define MSVW_HSPARE0 9 -#define MSVW_HSPARE1 10 -#define MSVW_MAX 11 +#define MSVW_H02 0 +#define MSVW_H03 1 +#define MSVW_H07 2 +#define MSVW_H41 3 +#define MSVW_H42 4 +#define MSVW_H43 5 +#define MSVW_H44 6 +#define MSVW_H47 7 +#define MSVW_H4A 8 +#define MSVW_HSPARE0 9 +#define MSVW_HSPARE1 10 +#define MSVW_MAX 11 /* Access 32-bit word in 96-bit MSVW register. 0 <= w <= 2 */ -#define MSVW(id, w) \ - REG32(MCHP_ESPI_MSVW_BASE + ((id) * 12) + (((w) & 0x03) * 4)) +#define MSVW(id, w) REG32(MCHP_ESPI_MSVW_BASE + ((id)*12) + (((w)&0x03) * 4)) /* Access index value in byte 0 */ -#define MCHP_ESPI_VW_M2S_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id) * 12)) +#define MCHP_ESPI_VW_M2S_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12)) /* * Access MTOS_SOURCE and MTOS_STATE in byte 1 * MTOS_SOURCE = b[1:0] specifies reset source * MTOS_STATE = b[7:4] are states loaded into SRC[0:3] on reset event */ -#define MCHP_ESPI_VW_M2S_MTOS(id) \ - REG8(MCHP_ESPI_VW_BASE + 1 + ((id) * 12)) +#define MCHP_ESPI_VW_M2S_MTOS(id) REG8(MCHP_ESPI_VW_BASE + 1 + ((id)*12)) /* * Access Index, MTOS Source, and MTOS State as 16-bit quantity. * Index in b[7:0] * MTOS Source in b[9:8] * MTOS State in b[15:12] */ -#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) \ - REG16(MCHP_ESPI_VW_BASE + ((id) * 12)) +#define MCHP_ESPI_VW_M2S_INDEX_MTOS(id) REG16(MCHP_ESPI_VW_BASE + ((id)*12)) /* Access SRCn IRQ Select bit fields */ -#define MCHP_ESPI_VW_M2S_IRQSEL0(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4) -#define MCHP_ESPI_VW_M2S_IRQSEL1(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 5) -#define MCHP_ESPI_VW_M2S_IRQSEL2(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 6) -#define MCHP_ESPI_VW_M2S_IRQSEL3(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 7) +#define MCHP_ESPI_VW_M2S_IRQSEL0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4) +#define MCHP_ESPI_VW_M2S_IRQSEL1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 5) +#define MCHP_ESPI_VW_M2S_IRQSEL2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 6) +#define MCHP_ESPI_VW_M2S_IRQSEL3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 7) #define MCHP_ESPI_VW_M2S_IRQSEL(id, src) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 4 + ((src) & 0x03)) -#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) \ - REG32(MCHP_ESPI_VW_BASE + ((id) * 12) + 4) + REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 4 + ((src)&0x03)) +#define MCHP_ESPI_VW_M2S_IRQSEL_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*12) + 4) /* Access individual source bits */ -#define MCHP_ESPI_VW_M2S_SRC0(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 8) -#define MCHP_ESPI_VW_M2S_SRC1(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 9) -#define MCHP_ESPI_VW_M2S_SRC2(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 10) -#define MCHP_ESPI_VW_M2S_SRC3(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 12) + 11) +#define MCHP_ESPI_VW_M2S_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 8) +#define MCHP_ESPI_VW_M2S_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 9) +#define MCHP_ESPI_VW_M2S_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 10) +#define MCHP_ESPI_VW_M2S_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*12) + 11) /* * Access all four Source bits as 32-bit value, Source bits are located * at bits[0, 8, 16, 24] of 32-bit word. */ -#define MCHP_ESPI_VW_M2S_SRC_ALL(id) \ - REG32(MCHP_ESPI_VW_BASE + 8 + ((id) * 12)) +#define MCHP_ESPI_VW_M2S_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + 8 + ((id)*12)) /* * Access an individual Source bit as byte where * bit[0] contains the source bit. */ #define MCHP_ESPI_VW_M2S_SRC(id, src) \ - REG8(MCHP_ESPI_VW_BASE + 8 + ((id) * 8) + ((src) & 0x03)) + REG8(MCHP_ESPI_VW_BASE + 8 + ((id)*8) + ((src)&0x03)) /* * Indices of Slave to Master Virtual Wire registers. @@ -745,124 +718,114 @@ * MCHP maps Host indices into its Slave to Master * 64-bit registers. */ -#define SMVW_H04 0 -#define SMVW_H05 1 -#define SMVW_H06 2 -#define SMVW_H40 3 -#define SMVW_H45 4 -#define SMVW_H46 5 -#define SMVW_HSPARE6 6 -#define SMVW_HSPARE7 7 -#define SMVW_HSPARE8 8 -#define SMVW_HSPARE9 9 -#define SMVW_HSPARE10 10 -#define SMVW_MAX 11 +#define SMVW_H04 0 +#define SMVW_H05 1 +#define SMVW_H06 2 +#define SMVW_H40 3 +#define SMVW_H45 4 +#define SMVW_H46 5 +#define SMVW_HSPARE6 6 +#define SMVW_HSPARE7 7 +#define SMVW_HSPARE8 8 +#define SMVW_HSPARE9 9 +#define SMVW_HSPARE10 10 +#define SMVW_MAX 11 /* Access 32-bit word of 64-bit SMVW register, 0 <= w <= 1 */ #define SMVW(id, w) \ - REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200 + (((w) & 0x01) * 4)) + REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200 + (((w)&0x01) * 4)) /* Access Index in b[7:0] of byte 0 */ -#define MCHP_ESPI_VW_S2M_INDEX(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200) +#define MCHP_ESPI_VW_S2M_INDEX(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200) /* Access STOM_SOURCE and STOM_STATE in byte 1 * STOM_SOURCE = b[1:0] * STOM_STATE = b[7:4] */ -#define MCHP_ESPI_VW_S2M_STOM(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x201) +#define MCHP_ESPI_VW_S2M_STOM(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x201) /* Access Index, STOM_SOURCE, and STOM_STATE in bytes[1:0] * Index = b[7:0] * STOM_SOURCE = b[9:8] * STOM_STATE = [15:12] */ #define MCHP_ESPI_VW_S2M_INDEX_STOM(id) \ - REG16(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x200) + REG16(MCHP_ESPI_VW_BASE + ((id)*8) + 0x200) /* Access Change[0:3] RO bits. Set to 1 if any of SRC[0:3] change */ -#define MCHP_ESPI_VW_S2M_CHANGE(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x202) +#define MCHP_ESPI_VW_S2M_CHANGE(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x202) /* Access individual SRC bits * bit[0] = SRCn */ -#define MCHP_ESPI_VW_S2M_SRC0(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204) -#define MCHP_ESPI_VW_S2M_SRC1(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x205) -#define MCHP_ESPI_VW_S2M_SRC2(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x206) -#define MCHP_ESPI_VW_S2M_SRC3(id) \ - REG8(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x207) +#define MCHP_ESPI_VW_S2M_SRC0(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204) +#define MCHP_ESPI_VW_S2M_SRC1(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x205) +#define MCHP_ESPI_VW_S2M_SRC2(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x206) +#define MCHP_ESPI_VW_S2M_SRC3(id) REG8(MCHP_ESPI_VW_BASE + ((id)*8) + 0x207) /* * Access specified source bit as byte read/write. * Source bit is in bit[0] of byte. */ #define MCHP_ESPI_VW_S2M_SRC(id, src) \ - REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id) * 8) + ((src) & 0x03)) + REG8(MCHP_ESPI_VW_BASE + 0x204 + ((id)*8) + ((src)&0x03)) /* Access SRC[0:3] as 32-bit word * SRC0 = b[0] * SRC1 = b[8] * SRC2 = b[16] * SRC3 = b[24] */ -#define MCHP_ESPI_VW_S2M_SRC_ALL(id) \ - REG32(MCHP_ESPI_VW_BASE + ((id) * 8) + 0x204) +#define MCHP_ESPI_VW_S2M_SRC_ALL(id) REG32(MCHP_ESPI_VW_BASE + ((id)*8) + 0x204) /* DMA */ #define MCHP_DMA_MAIN_CTRL REG8(MCHP_DMA_BASE + 0x00) #define MCHP_DMA_MAIN_PKT_RO REG32(MCHP_DMA_BASE + 0x04) #define MCHP_DMA_MAIN_FSM_RO REG8(MCHP_DMA_BASE + 0x08) /* DMA Channel Registers */ -#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS)) +#define MCHP_DMA_CH_ACT(n) REG8(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS)) #define MCHP_DMA_CH_MEM_START(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x04) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x04) #define MCHP_DMA_CH_MEM_END(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x08) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x08) #define MCHP_DMA_CH_DEV_ADDR(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x0c) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x0c) #define MCHP_DMA_CH_CTRL(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x10) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x10) #define MCHP_DMA_CH_ISTS(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x14) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x14) #define MCHP_DMA_CH_IEN(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x18) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x18) #define MCHP_DMA_CH_FSM_RO(n) \ - REG32(MCHP_DMA_CH_BASE + ((n) * MCHP_DMA_CH_OFS) + 0x1c) + REG32(MCHP_DMA_CH_BASE + ((n)*MCHP_DMA_CH_OFS) + 0x1c) /* * DMA Channel 0 implements CRC-32 feature */ -#define MCHP_DMA_CH0_CRC32_EN REG8(MCHP_DMA_CH_BASE + 0x20) -#define MCHP_DMA_CH0_CRC32_DATA REG32(MCHP_DMA_CH_BASE + 0x24) -#define MCHP_DMA_CH0_CRC32_POST_STS REG8(MCHP_DMA_CH_BASE + 0x28) +#define MCHP_DMA_CH0_CRC32_EN REG8(MCHP_DMA_CH_BASE + 0x20) +#define MCHP_DMA_CH0_CRC32_DATA REG32(MCHP_DMA_CH_BASE + 0x24) +#define MCHP_DMA_CH0_CRC32_POST_STS REG8(MCHP_DMA_CH_BASE + 0x28) /* * DMA Channel 1 implements memory fill feature */ -#define MCHP_DMA_CH1_FILL_EN \ - REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20) -#define MCHP_DMA_CH1_FILL_DATA \ - REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24) +#define MCHP_DMA_CH1_FILL_EN REG8(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x20) +#define MCHP_DMA_CH1_FILL_DATA REG32(MCHP_DMA_CH_BASE + MCHP_DMA_CH_OFS + 0x24) /* Bits for DMA Main Control */ -#define MCHP_DMA_MAIN_CTRL_ACT BIT(0) -#define MCHP_DMA_MAIN_CTRL_SRST BIT(1) +#define MCHP_DMA_MAIN_CTRL_ACT BIT(0) +#define MCHP_DMA_MAIN_CTRL_SRST BIT(1) /* Bits for DMA channel regs */ -#define MCHP_DMA_ACT_EN BIT(0) +#define MCHP_DMA_ACT_EN BIT(0) /* DMA Channel Control */ -#define MCHP_DMA_ABORT BIT(25) -#define MCHP_DMA_SW_GO BIT(24) -#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20) -#define MCHP_DMA_XFER_SIZE(x) ((x) << 20) -#define MCHP_DMA_DIS_HW_FLOW BIT(19) -#define MCHP_DMA_INC_DEV BIT(17) -#define MCHP_DMA_INC_MEM BIT(16) -#define MCHP_DMA_DEV(x) ((x) << 9) -#define MCHP_DMA_DEV_MASK0 (0x7f) -#define MCHP_DMA_DEV_MASK (0x7f << 9) -#define MCHP_DMA_TO_DEV BIT(8) -#define MCHP_DMA_DONE BIT(2) -#define MCHP_DMA_RUN BIT(0) +#define MCHP_DMA_ABORT BIT(25) +#define MCHP_DMA_SW_GO BIT(24) +#define MCHP_DMA_XFER_SIZE_MASK (7ul << 20) +#define MCHP_DMA_XFER_SIZE(x) ((x) << 20) +#define MCHP_DMA_DIS_HW_FLOW BIT(19) +#define MCHP_DMA_INC_DEV BIT(17) +#define MCHP_DMA_INC_MEM BIT(16) +#define MCHP_DMA_DEV(x) ((x) << 9) +#define MCHP_DMA_DEV_MASK0 (0x7f) +#define MCHP_DMA_DEV_MASK (0x7f << 9) +#define MCHP_DMA_TO_DEV BIT(8) +#define MCHP_DMA_DONE BIT(2) +#define MCHP_DMA_RUN BIT(0) /* DMA Channel Status */ -#define MCHP_DMA_STS_ALU_DONE BIT(3) -#define MCHP_DMA_STS_DONE BIT(2) -#define MCHP_DMA_STS_HWFL_ERR BIT(1) -#define MCHP_DMA_STS_BUS_ERR BIT(0) +#define MCHP_DMA_STS_ALU_DONE BIT(3) +#define MCHP_DMA_STS_DONE BIT(2) +#define MCHP_DMA_STS_HWFL_ERR BIT(1) +#define MCHP_DMA_STS_BUS_ERR BIT(0) /* * Required structure typedef for common/dma.h interface @@ -871,19 +834,19 @@ * We can't remove dma_chan_t as its used in DMA API header. */ struct MCHP_dma_chan { - uint32_t act; /* Activate */ - uint32_t mem_start; /* Memory start address */ - uint32_t mem_end; /* Memory end address */ - uint32_t dev; /* Device address */ - uint32_t ctrl; /* Control */ - uint32_t int_status; /* Interrupt status */ - uint32_t int_enabled; /* Interrupt enabled */ - uint32_t chfsm; /* channel fsm read-only */ - uint32_t alu_en; /* channels 0 & 1 only */ - uint32_t alu_data; /* channels 0 & 1 only */ - uint32_t alu_sts; /* channel 0 only */ - uint32_t alu_ro; /* channel 0 only */ - uint32_t rsvd[4]; /* 0x30 - 0x3F */ + uint32_t act; /* Activate */ + uint32_t mem_start; /* Memory start address */ + uint32_t mem_end; /* Memory end address */ + uint32_t dev; /* Device address */ + uint32_t ctrl; /* Control */ + uint32_t int_status; /* Interrupt status */ + uint32_t int_enabled; /* Interrupt enabled */ + uint32_t chfsm; /* channel fsm read-only */ + uint32_t alu_en; /* channels 0 & 1 only */ + uint32_t alu_data; /* channels 0 & 1 only */ + uint32_t alu_sts; /* channel 0 only */ + uint32_t alu_ro; /* channel 0 only */ + uint32_t rsvd[4]; /* 0x30 - 0x3F */ }; /* Common code and header file must use this */ -- cgit v1.2.1 From 4401a85f08616193cb8082c30b5883b669881df0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:36 -0600 Subject: chip/npcx/i2c-npcx5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I196ae9596ffe994655d08cd31397b8b078923925 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729384 Reviewed-by: Jeremy Bettis --- chip/npcx/i2c-npcx5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c index 89b5ec8072..09b5b51882 100644 --- a/chip/npcx/i2c-npcx5.c +++ b/chip/npcx/i2c-npcx5.c @@ -32,7 +32,7 @@ void i2c_select_port(int port) /* Select IO pins for multi-ports I2C controllers */ UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL, - (port == NPCX_I2C_PORT0_1)); + (port == NPCX_I2C_PORT0_1)); } int i2c_is_raw_mode(int port) -- cgit v1.2.1 From 1b77669c04991df883b479ff40c5ba7be4770bf1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:47 -0600 Subject: zephyr/test/drivers/src/tcpci_test_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iab2f835cb1c5dbb629b2e30130e449a41f997572 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730959 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/tcpci_test_common.c | 114 ++++++++++++++-------------- 1 file changed, 59 insertions(+), 55 deletions(-) diff --git a/zephyr/test/drivers/src/tcpci_test_common.c b/zephyr/test/drivers/src/tcpci_test_common.c index ccd250e11f..3bf3ff14c5 100644 --- a/zephyr/test/drivers/src/tcpci_test_common.c +++ b/zephyr/test/drivers/src/tcpci_test_common.c @@ -34,8 +34,8 @@ void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg, zassert_ok(tcpci_emul_get_reg(emul, reg, ®_val), "Failed tcpci_emul_get_reg(); line: %d", line); zassert_equal(exp_val & mask, reg_val & mask, - "Expected 0x%x, got 0x%x, mask 0x%x; line: %d", - exp_val, reg_val, mask, line); + "Expected 0x%x, got 0x%x, mask 0x%x; line: %d", exp_val, + reg_val, mask, line); } /** Test TCPCI init and vbus level */ @@ -84,7 +84,7 @@ void test_tcpci_init(const struct emul *emul, enum usbc_port port) /* Set TCPCI emulator VBUS to present (connected, above 4V) */ tcpci_emul_set_reg(emul, TCPC_REG_POWER_STATUS, TCPC_REG_POWER_STATUS_VBUS_PRES | - TCPC_REG_POWER_STATUS_VBUS_DET); + TCPC_REG_POWER_STATUS_VBUS_DET); /* Test init with VBUS present without vSafe0V tcpc config flag */ zassert_equal(EC_SUCCESS, drv->init(port), NULL); @@ -165,61 +165,61 @@ void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port) } test_param[] = { /* Test DRP with open state */ { - .cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN}, + .cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_OPEN }, .connect_result = false, .drp = TYPEC_DRP, }, /* Test DRP with cc1 open state, cc2 src RA */ { - .cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA}, + .cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA }, .connect_result = false, .drp = TYPEC_DRP, }, /* Test DRP with cc1 src RA, cc2 src RD */ { - .cc = {TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD}, + .cc = { TYPEC_CC_VOLT_RA, TYPEC_CC_VOLT_RD }, .connect_result = false, .drp = TYPEC_DRP, }, /* Test DRP with cc1 snk open, cc2 snk default */ { - .cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF}, + .cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RP_DEF }, .connect_result = true, .drp = TYPEC_DRP, }, /* Test DRP with cc1 snk 1.5, cc2 snk 3.0 */ { - .cc = {TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0}, + .cc = { TYPEC_CC_VOLT_RP_1_5, TYPEC_CC_VOLT_RP_3_0 }, .connect_result = true, .drp = TYPEC_DRP, }, /* Test no DRP with cc1 src open, cc2 src RA */ { - .cc = {TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA}, + .cc = { TYPEC_CC_VOLT_OPEN, TYPEC_CC_VOLT_RA }, .connect_result = false, .drp = TYPEC_NO_DRP, - .role_cc = {TYPEC_CC_RP, TYPEC_CC_RP}, + .role_cc = { TYPEC_CC_RP, TYPEC_CC_RP }, }, /* Test no DRP with cc1 src RD, cc2 snk default */ { - .cc = {TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RP_DEF}, + .cc = { TYPEC_CC_VOLT_RD, TYPEC_CC_VOLT_RP_DEF }, .connect_result = false, .drp = TYPEC_NO_DRP, - .role_cc = {TYPEC_CC_RP, TYPEC_CC_RD}, + .role_cc = { TYPEC_CC_RP, TYPEC_CC_RD }, }, /* Test no DRP with cc1 snk default, cc2 snk open */ { - .cc = {TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN}, + .cc = { TYPEC_CC_VOLT_RP_DEF, TYPEC_CC_VOLT_OPEN }, .connect_result = false, .drp = TYPEC_NO_DRP, - .role_cc = {TYPEC_CC_RD, TYPEC_CC_RD}, + .role_cc = { TYPEC_CC_RD, TYPEC_CC_RD }, }, /* Test no DRP with cc1 snk 3.0, cc2 snk 1.5 */ { - .cc = {TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5}, + .cc = { TYPEC_CC_VOLT_RP_3_0, TYPEC_CC_VOLT_RP_1_5 }, .connect_result = false, .drp = TYPEC_NO_DRP, - .role_cc = {TYPEC_CC_RD, TYPEC_CC_RD}, + .role_cc = { TYPEC_CC_RD, TYPEC_CC_RD }, }, }; @@ -233,17 +233,18 @@ void test_tcpci_get_cc(const struct emul *emul, enum usbc_port port) test_param[i].cc[1]); tcpci_emul_set_reg(emul, TCPC_REG_ROLE_CTRL, role_ctrl); tcpci_emul_set_reg(emul, TCPC_REG_CC_STATUS, cc_status); - zassert_equal(EC_SUCCESS, drv->get_cc(port, &cc1, &cc2), - "Failed to get CC in test case %d (CC 0x%x, role 0x%x)", - i, cc_status, role_ctrl); - zassert_equal(test_param[i].cc[0], cc1, - "0x%x != (cc1 = 0x%x) in test case %d (CC 0x%x, role 0x%x)", - test_param[i].cc[0], cc1, i, cc_status, - role_ctrl); - zassert_equal(test_param[i].cc[1], cc2, - "0x%x != (cc2 = 0x%x) in test case %d (CC 0x%x, role 0x%x)", - test_param[i].cc[0], cc1, i, cc_status, - role_ctrl); + zassert_equal( + EC_SUCCESS, drv->get_cc(port, &cc1, &cc2), + "Failed to get CC in test case %d (CC 0x%x, role 0x%x)", + i, cc_status, role_ctrl); + zassert_equal( + test_param[i].cc[0], cc1, + "0x%x != (cc1 = 0x%x) in test case %d (CC 0x%x, role 0x%x)", + test_param[i].cc[0], cc1, i, cc_status, role_ctrl); + zassert_equal( + test_param[i].cc[1], cc2, + "0x%x != (cc2 = 0x%x) in test case %d (CC 0x%x, role 0x%x)", + test_param[i].cc[0], cc1, i, cc_status, role_ctrl); } } @@ -380,32 +381,37 @@ void test_tcpci_set_msg_header(const struct emul *emul, enum usbc_port port) /* Test error on failed header set */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_MSG_HDR_INFO); - zassert_equal(EC_ERROR_INVAL, drv->set_msg_header(port, PD_ROLE_SINK, - PD_ROLE_UFP), NULL); + zassert_equal(EC_ERROR_INVAL, + drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP), + NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test setting sink UFP */ - zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SINK, - PD_ROLE_UFP), NULL); + zassert_equal(EC_SUCCESS, + drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_UFP), + NULL); check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SINK)); /* Test setting sink DFP */ - zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SINK, - PD_ROLE_DFP), NULL); + zassert_equal(EC_SUCCESS, + drv->set_msg_header(port, PD_ROLE_SINK, PD_ROLE_DFP), + NULL); check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SINK)); /* Test setting source UFP */ - zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SOURCE, - PD_ROLE_UFP), NULL); + zassert_equal(EC_SUCCESS, + drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_UFP), + NULL); check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_UFP, PD_ROLE_SOURCE)); /* Test setting source DFP */ - zassert_equal(EC_SUCCESS, drv->set_msg_header(port, PD_ROLE_SOURCE, - PD_ROLE_DFP), NULL); + zassert_equal(EC_SUCCESS, + drv->set_msg_header(port, PD_ROLE_SOURCE, PD_ROLE_DFP), + NULL); check_tcpci_reg(emul, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_SET(PD_ROLE_DFP, PD_ROLE_SOURCE)); } @@ -455,8 +461,7 @@ void test_tcpci_set_rx_detect(const struct emul *emul, enum usbc_port port) } /** Test TCPCI get raw message from TCPC */ -void test_tcpci_get_rx_message_raw(const struct emul *emul, - enum usbc_port port) +void test_tcpci_get_rx_message_raw(const struct emul *emul, enum usbc_port port) { const struct tcpm_drv *drv = tcpc_config[port].drv; struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul); @@ -528,8 +533,8 @@ void test_tcpci_get_rx_message_raw(const struct emul *emul, */ exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf[1] << 8) | buf[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf + 2, size, NULL); } @@ -573,8 +578,7 @@ void test_tcpci_transmit(const struct emul *emul, enum usbc_port port) /* Test transmit fail on rx buffer */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_TX_BUFFER); zassert_equal(EC_ERROR_INVAL, - drv->transmit(port, TCPCI_MSG_SOP_PRIME, 0, data), - NULL); + drv->transmit(port, TCPCI_MSG_SOP_PRIME, 0, data), NULL); i2c_common_emul_set_write_fail_reg(i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -693,8 +697,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) NULL); exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf1 + 2, size, NULL); zassert_false(tcpm_has_pending_message(port), NULL); @@ -714,8 +718,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) NULL); exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf1 + 2, size, NULL); /* Check if msg2 is in queue */ zassert_true(tcpm_has_pending_message(port), NULL); @@ -723,8 +727,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) NULL); exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf2 + 2, size, NULL); zassert_false(tcpm_has_pending_message(port), NULL); @@ -747,8 +751,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) NULL); exp_head = (TCPCI_MSG_SOP_PRIME << 28) | (buf2[1] << 8) | buf2[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf2 + 2, size, NULL); zassert_false(tcpm_has_pending_message(port), NULL); @@ -774,8 +778,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) zassert_equal(EC_SUCCESS, tcpm_dequeue_message(port, payload, &head), NULL); zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf1 + 2, size, NULL); } tcpm_clear_pending_messages(port); @@ -791,8 +795,8 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) NULL); exp_head = (TCPCI_MSG_SOP << 28) | (buf1[1] << 8) | buf1[0]; zassert_equal(exp_head, head, - "Received header 0x%08lx, expected 0x%08lx", - head, exp_head); + "Received header 0x%08lx, expected 0x%08lx", head, + exp_head); zassert_mem_equal(payload, buf1 + 2, size, NULL); zassert_false(tcpm_has_pending_message(port), NULL); } -- cgit v1.2.1 From 764383ec83bfc084a35615e76abd9aae6f06e506 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:36 -0600 Subject: test/genvif/src/helper.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib994b615931bb7b58522ab6d11deff23ef7fe498 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730505 Reviewed-by: Jeremy Bettis --- test/genvif/src/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/genvif/src/helper.c b/test/genvif/src/helper.c index d604e63cfa..61360ea210 100644 --- a/test/genvif/src/helper.c +++ b/test/genvif/src/helper.c @@ -7,8 +7,8 @@ #include "usb_pd.h" #ifndef CONFIG_USB_PD_CUSTOM_PDO -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), -- cgit v1.2.1 From 72e193f224fbde901187234936259062806230ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:06 -0600 Subject: chip/stm32/pwm_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e535b7c445dfba99481040a558e7f9e17d6120b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729527 Reviewed-by: Jeremy Bettis --- chip/stm32/pwm_chip.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h index baa793090a..2ae5c152dd 100644 --- a/chip/stm32/pwm_chip.h +++ b/chip/stm32/pwm_chip.h @@ -29,7 +29,10 @@ struct pwm_t { extern const struct pwm_t pwm_channels[]; /* Macro to fill in both timer ID and register base */ -#define STM32_TIM(x) {x, STM32_TIM_BASE(x)} +#define STM32_TIM(x) \ + { \ + x, STM32_TIM_BASE(x) \ + } /* Plain ID mapping for readability */ #define STM32_TIM_CH(x) (x) -- cgit v1.2.1 From 16557860739a7a77ddb1476509e95c98b6ecb49e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:00 -0600 Subject: board/nucleo-f412zg/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib9dc539a2d48686d98a965ef6bafd471f12c331b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728779 Reviewed-by: Jeremy Bettis --- board/nucleo-f412zg/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/nucleo-f412zg/board.c b/board/nucleo-f412zg/board.c index da3b4a3d4d..e1c84aaecc 100644 --- a/board/nucleo-f412zg/board.c +++ b/board/nucleo-f412zg/board.c @@ -31,8 +31,8 @@ static void ap_deferred(void) * in S0: SLP_S3_L is 1 and SLP_S0_L is 1. * in S5/G3, the FP MCU should not be running. */ - int running = gpio_get_level(GPIO_PCH_SLP_S3_L) - && gpio_get_level(GPIO_PCH_SLP_S0_L); + int running = gpio_get_level(GPIO_PCH_SLP_S3_L) && + gpio_get_level(GPIO_PCH_SLP_S0_L); if (running) { /* S0 */ disable_sleep(SLEEP_MASK_AP_RUN); -- cgit v1.2.1 From fedd0ff073796317d946eeed4529cb181400493c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:13 -0600 Subject: board/nocturne/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If12a1fe8a45ef3af769b21809030277fa2b7fd27 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728761 Reviewed-by: Jeremy Bettis --- board/nocturne/usb_pd_policy.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/board/nocturne/usb_pd_policy.c b/board/nocturne/usb_pd_policy.c index 14329b61b3..68763ad797 100644 --- a/board/nocturne/usb_pd_policy.c +++ b/board/nocturne/usb_pd_policy.c @@ -16,8 +16,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -25,8 +25,7 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_EN_5V); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { int level; @@ -96,9 +95,8 @@ int pd_set_power_supply_ready(int port) __override void svdm_safe_dp_mode(int port) { /* make DP interface safe until configure */ - usb_mux_set(port, USB_PD_MUX_NONE, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); /* * Isolate the SBU lines. -- cgit v1.2.1 From 2641ecbd46731a78f48745a94646460baaa806da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:10 -0600 Subject: board/coffeecake/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea88fab539bd6a4a539e4392e731c4a37766f3a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728151 Reviewed-by: Jeremy Bettis --- board/coffeecake/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/coffeecake/board.h b/board/coffeecake/board.h index cabbb0bf4e..50c42a5a1e 100644 --- a/board/coffeecake/board.h +++ b/board/coffeecake/board.h @@ -50,7 +50,7 @@ #define CONFIG_USB_PD_IDENTITY_HW_VERS 1 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 #define CONFIG_USB_PD_LOGGING -#undef CONFIG_EVENT_LOG_SIZE +#undef CONFIG_EVENT_LOG_SIZE #define CONFIG_EVENT_LOG_SIZE 256 #define CONFIG_USB_PD_CUSTOM_PDO #define CONFIG_USB_PD_PORT_MAX_COUNT 1 @@ -80,7 +80,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" @@ -106,21 +106,21 @@ enum usb_strings { }; /* 3.0A Rp */ -#define PD_SRC_VNC PD_SRC_3_0_VNC_MV -#define PD_SRC_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV +#define PD_SRC_VNC PD_SRC_3_0_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV /* delay necessary for the voltage transition on the power supply */ /* TODO (code.google.com/p/chrome-os-partner/issues/detail?id=37078) * Need to measure these and adjust for honeybuns. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 1000 -#define PD_MAX_POWER_MW 22500 -#define PD_MAX_CURRENT_MA 2500 -#define PD_MAX_VOLTAGE_MV 9000 +#define PD_MAX_POWER_MW 22500 +#define PD_MAX_CURRENT_MA 2500 +#define PD_MAX_VOLTAGE_MV 9000 /* Board interfaces */ void board_set_usb_output_voltage(int mv); @@ -131,11 +131,11 @@ void board_set_usb_output_voltage(int mv); #define USB_DEV_CLASS USB_CLASS_BILLBOARD /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_COUNT 0 +#define USB_IFACE_COUNT 0 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_COUNT 1 +#define USB_EP_CONTROL 0 +#define USB_EP_COUNT 1 /* I2C ports */ #define I2C_PORT_SY21612 0 -- cgit v1.2.1 From 299ff65c6242b185fa370212b6802c0f5ee7c816 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:11 -0600 Subject: board/poppy/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I418fc661e0fb6bf9416a7b9f707edadc608bb70f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727754 Reviewed-by: Jeremy Bettis --- board/poppy/board.h | 64 ++++++++++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/board/poppy/board.h b/board/poppy/board.h index 46a6fa19d3..8f365dc8df 100644 --- a/board/poppy/board.h +++ b/board/poppy/board.h @@ -101,8 +101,8 @@ #define CONFIG_CMD_CHARGER_ADC_AMON_BMON #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON @@ -141,7 +141,7 @@ #define CONFIG_TABLET_MODE #define CONFIG_TABLET_MODE_SWITCH -#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 2048 /* USB */ @@ -172,28 +172,28 @@ #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_0 -#define I2C_PORT_ALS NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_MP2949 NPCX_I2C_PORT2 -#define I2C_PORT_GYRO NPCX_I2C_PORT3 -#define I2C_PORT_BARO NPCX_I2C_PORT3 -#define I2C_PORT_ACCEL I2C_PORT_GYRO -#define I2C_PORT_THERMAL I2C_PORT_PMIC +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_0 +#define I2C_PORT_ALS NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT1 +#define I2C_PORT_BATTERY NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_MP2949 NPCX_I2C_PORT2 +#define I2C_PORT_GYRO NPCX_I2C_PORT3 +#define I2C_PORT_BARO NPCX_I2C_PORT3 +#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_THERMAL I2C_PORT_PMIC /* I2C addresses */ -#define I2C_ADDR_BD99992_FLAGS 0x30 -#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_MP2949_FLAGS 0x20 #ifndef __ASSEMBLER__ @@ -201,11 +201,11 @@ #include "registers.h" enum temp_sensor_id { - TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ - TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ - TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ + TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ + TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ TEMP_SENSOR_COUNT }; @@ -238,16 +238,16 @@ enum adc_channel { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ int board_get_version(void); -- cgit v1.2.1 From 2966f357b2bfb37949e2b955117c89377f16d7c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:13 -0600 Subject: board/chocodile_vpdmcu/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie74eac266c4bf7b4f05a8b0065d830a04b0cc6c8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728144 Reviewed-by: Jeremy Bettis --- board/chocodile_vpdmcu/board.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/board/chocodile_vpdmcu/board.c b/board/chocodile_vpdmcu/board.c index b3e49fc547..5cf52dd1fd 100644 --- a/board/chocodile_vpdmcu/board.c +++ b/board/chocodile_vpdmcu/board.c @@ -20,7 +20,7 @@ #include "util.h" #include "vpd_api.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) void board_config_pre_init(void) { @@ -40,26 +40,26 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_VCONN_VSENSE] = { - "VCONN_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_VCONN_VSENSE)}, - [ADC_CC_VPDMCU] = { - "CC_VPDMCU", 3000, 4096, 0, STM32_AIN(ADC_CC_VPDMCU)}, - [ADC_CC_RP3A0_RD_L] = { - "CC_RP3A0_RD_L", 3000, 4096, 0, STM32_AIN(ADC_CC_RP3A0_RD_L)}, - [ADC_RDCONNECT_REF] = { - "RDCONNECT_REF", 3000, 4096, 0, STM32_AIN(ADC_RDCONNECT_REF)}, - [ADC_CC1_RP3A0_RD_L] = { - "CC1_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RP3A0_RD_L)}, - [ADC_CC2_RP3A0_RD_L] = { - "CC2_RP1A5_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RP3A0_RD_L)}, - [ADC_HOST_VBUS_VSENSE] = { - "HOST_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_HOST_VBUS_VSENSE)}, - [ADC_CHARGE_VBUS_VSENSE] = { - "CHARGE_VBUS_VSENSE", 3000, 4096, 0, STM32_AIN(ADC_CHARGE_VBUS_VSENSE)}, - [ADC_CC1_RPUSB_ODH] = { - "CC1_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC1_RPUSB_ODH)}, - [ADC_CC2_RPUSB_ODH] = { - "CC2_RPUSB_ODH", 3000, 4096, 0, STM32_AIN(ADC_CC2_RPUSB_ODH)}, + [ADC_VCONN_VSENSE] = { "VCONN_VSENSE", 3000, 4096, 0, + STM32_AIN(ADC_VCONN_VSENSE) }, + [ADC_CC_VPDMCU] = { "CC_VPDMCU", 3000, 4096, 0, + STM32_AIN(ADC_CC_VPDMCU) }, + [ADC_CC_RP3A0_RD_L] = { "CC_RP3A0_RD_L", 3000, 4096, 0, + STM32_AIN(ADC_CC_RP3A0_RD_L) }, + [ADC_RDCONNECT_REF] = { "RDCONNECT_REF", 3000, 4096, 0, + STM32_AIN(ADC_RDCONNECT_REF) }, + [ADC_CC1_RP3A0_RD_L] = { "CC1_RP1A5_ODH", 3000, 4096, 0, + STM32_AIN(ADC_CC1_RP3A0_RD_L) }, + [ADC_CC2_RP3A0_RD_L] = { "CC2_RP1A5_ODH", 3000, 4096, 0, + STM32_AIN(ADC_CC2_RP3A0_RD_L) }, + [ADC_HOST_VBUS_VSENSE] = { "HOST_VBUS_VSENSE", 3000, 4096, 0, + STM32_AIN(ADC_HOST_VBUS_VSENSE) }, + [ADC_CHARGE_VBUS_VSENSE] = { "CHARGE_VBUS_VSENSE", 3000, 4096, 0, + STM32_AIN(ADC_CHARGE_VBUS_VSENSE) }, + [ADC_CC1_RPUSB_ODH] = { "CC1_RPUSB_ODH", 3000, 4096, 0, + STM32_AIN(ADC_CC1_RPUSB_ODH) }, + [ADC_CC2_RPUSB_ODH] = { "CC2_RPUSB_ODH", 3000, 4096, 0, + STM32_AIN(ADC_CC2_RPUSB_ODH) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -- cgit v1.2.1 From 50bc95b469ec27adbd31418f93960a7733366a7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:27 -0600 Subject: chip/stm32/usart_info_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia8567fab8d7cad2c4ede768b2611626767268a38 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729418 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_info_command.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/chip/stm32/usart_info_command.c b/chip/stm32/usart_info_command.c index 7b7dc1362a..3f36603eda 100644 --- a/chip/stm32/usart_info_command.c +++ b/chip/stm32/usart_info_command.c @@ -39,7 +39,5 @@ static int command_usart_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(usart_info, - command_usart_info, - NULL, +DECLARE_CONSOLE_COMMAND(usart_info, command_usart_info, NULL, "Display USART info"); -- cgit v1.2.1 From d2b6835080c93677772386c8f6684ae4c9dc3de2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:22 -0600 Subject: include/online_calibration.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6f5a71135e5f30018064bf952acd4cfc44461b81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730373 Reviewed-by: Jeremy Bettis --- include/online_calibration.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/online_calibration.h b/include/online_calibration.h index e3b259e14d..4094c0a85e 100644 --- a/include/online_calibration.h +++ b/include/online_calibration.h @@ -22,10 +22,9 @@ void online_calibration_init(void); * @param timestamp The time associated with the sample * @return EC_SUCCESS when successful. */ -int online_calibration_process_data( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - uint32_t timestamp); +int online_calibration_process_data(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, + uint32_t timestamp); /** * Check if new calibration values are available since the last read. -- cgit v1.2.1 From c7af9ff1bc6a883353d163865d51350de5099123 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:35 -0600 Subject: board/fusb307bgevb/lcd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4bbcb77c81f7e97eeb6810b056c3425e2c27263e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728381 Reviewed-by: Jeremy Bettis --- board/fusb307bgevb/lcd.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/fusb307bgevb/lcd.c b/board/fusb307bgevb/lcd.c index 892888329e..268801146b 100644 --- a/board/fusb307bgevb/lcd.c +++ b/board/fusb307bgevb/lcd.c @@ -26,17 +26,17 @@ static struct lcd_state_info state = { /* write either command or data */ static void expander_write(uint8_t data) { - i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00, data | - state.backlightval); + i2c_write8(I2C_PORT_TCPC, LCD_SLAVE_ADDR, 0x00, + data | state.backlightval); } static void pulse_enable(uint8_t data) { - expander_write(data | LCD_EN);/* En high */ - usleep(1); /* enable pulse must be >450ns */ + expander_write(data | LCD_EN); /* En high */ + usleep(1); /* enable pulse must be >450ns */ - expander_write(data & ~LCD_EN);/* En low */ - usleep(50); /* commands need > 37us to settle */ + expander_write(data & ~LCD_EN); /* En low */ + usleep(50); /* commands need > 37us to settle */ } static void write_4bits(uint8_t value) @@ -63,8 +63,8 @@ static void command(uint8_t value) /********** high level commands, for the user! */ void lcd_clear(void) { - command(LCD_CLEAR_DISPLAY);/* clear display, set cursor to zero */ - usleep(2000); /* this command takes a long time! */ + command(LCD_CLEAR_DISPLAY); /* clear display, set cursor to zero */ + usleep(2000); /* this command takes a long time! */ } void lcd_set_cursor(uint8_t col, uint8_t row) -- cgit v1.2.1 From 34226d97dc7650ba34fcb33fa89f426fb9531381 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:50 -0600 Subject: board/osiris/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e16cc0bb054db3773904fdf09685db373367721 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728797 Reviewed-by: Jeremy Bettis --- board/osiris/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/osiris/fans.c b/board/osiris/fans.c index fa5a8dc09a..44c70265b1 100644 --- a/board/osiris/fans.c +++ b/board/osiris/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 4aedf5621678d97f63a23e7de582e861e96a864d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:25 -0600 Subject: chip/max32660/i2c_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24478569ece4dd3f0eefba49caabbb91cbde2c19 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729221 Reviewed-by: Jeremy Bettis --- chip/max32660/i2c_chip.c | 143 +++++++++++++++++++++++++---------------------- 1 file changed, 75 insertions(+), 68 deletions(-) diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c index 4daaf31207..7120ff276d 100644 --- a/chip/max32660/i2c_chip.c +++ b/chip/max32660/i2c_chip.c @@ -25,9 +25,9 @@ #define EC_PADDING_BYTE 0xec /* **** Definitions **** */ -#define I2C_ERROR \ - (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \ - MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \ +#define I2C_ERROR \ + (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \ + MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \ MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \ MXC_F_I2C_INT_FL0_STOP_ER) @@ -35,7 +35,7 @@ #define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */ #define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */ #define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */ -#define T_AF_MIN (10) /* tAF minimun in nanoseconds */ +#define T_AF_MIN (10) /* tAF minimun in nanoseconds */ /** * typedef i2c_speed_t - I2C speed modes. @@ -170,10 +170,10 @@ static struct i2c_port_data pdata[I2C_PORT_COUNT]; /* **** Function Prototypes **** */ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed); static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, const uint8_t *data, int len, - int restart); + int stop, const uint8_t *data, int len, + int restart); static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, uint8_t *data, int len, int restart); + int stop, uint8_t *data, int len, int restart); #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS static void init_i2cs(int port); @@ -182,7 +182,7 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c); #endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */ /* Port address for each I2C */ -static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1}; +static mxc_i2c_regs_t *i2c_bus_ports[] = { MXC_I2C0, MXC_I2C1 }; #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS @@ -224,15 +224,16 @@ int chip_i2c_xfer(int port, const uint16_t addr_flags, const uint8_t *out, if (out_size) { status = i2c_controller_write(i2c_bus_ports[port], addr_flags, - xfer_start, xfer_stop, out, out_size, - 1); + xfer_start, xfer_stop, out, + out_size, 1); if (status != EC_SUCCESS) { return status; } } if (in_size) { status = i2c_controller_read(i2c_bus_ports[port], addr_flags, - xfer_start, xfer_stop, in, in_size, 0); + xfer_start, xfer_stop, in, in_size, + 0); if (status != EC_SUCCESS) { return status; } @@ -301,7 +302,6 @@ void i2c_init(void) CONFIG_BOARD_I2C_ADDR_FLAGS; #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */ #endif /* CONFIG_HOSTCMD_I2C_ADDR_FLAGS */ - } /** @@ -309,7 +309,7 @@ void i2c_init(void) */ #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS /* IRQ for each I2C */ -static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn}; +static uint32_t i2c_bus_irqs[] = { EC_I2C0_IRQn, EC_I2C1_IRQn }; /** * Buffer for received host command packets (including prefix byte on request, @@ -398,9 +398,9 @@ void i2c_target_service(i2c_req_t *req) req->tx_remain = -1; #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS if (req->addr_match_flag != 0x1) { - i2c_process_board_command( - 0, CONFIG_BOARD_I2C_ADDR_FLAGS, - req->received_count); + i2c_process_board_command(0, + CONFIG_BOARD_I2C_ADDR_FLAGS, + req->received_count); } else #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */ { @@ -440,8 +440,9 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req) * a possible done bit, address match, or multiple target address * flags. */ - i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH | - MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE); + i2c->int_fl0 = i2c->int_fl0 & + ~(MXC_F_I2C_INT_FL0_ADDR_MATCH | + MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE); i2c->int_fl1 = i2c->int_fl1; /* * If there is nothing to transmit to the EC HOST, then default @@ -459,7 +460,7 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req) req->response_pending = false; /* Fill the FIFO with data to transimit to the I2C Controller */ while ((req->tx_remain > 0) && - !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { i2c->fifo = *(req->tx_data)++; req->tx_remain--; } @@ -477,10 +478,10 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req) } /* Set the threshold for TX, the threshold is a four bit field. */ i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | - (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); + (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); /* Enable interrupts of interest. */ i2c->int_en0 = MXC_F_I2C_INT_EN0_TX_THRESH | MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; + I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; } /** @@ -491,8 +492,9 @@ static void i2c_target_service_read(mxc_i2c_regs_t *i2c, i2c_req_t *req) static void i2c_target_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req) { /* Clear all flags except address matching and done. */ - i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH | - MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE); + i2c->int_fl0 = i2c->int_fl0 & + ~(MXC_F_I2C_INT_FL0_ADDR_MATCH | + MXC_F_I2C_INT_FL0_MAMI_MASK | MXC_F_I2C_INT_FL0_DONE); i2c->int_fl1 = i2c->int_fl1; /* Read out any data in the RX FIFO. */ while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { @@ -500,13 +502,12 @@ static void i2c_target_service_write(mxc_i2c_regs_t *i2c, i2c_req_t *req) req->received_count++; } /* Set the RX threshold interrupt level. */ - i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & - ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | - (MXC_I2C_FIFO_DEPTH - 1) - << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + i2c->rx_ctrl0 = + ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); /* Enable interrupts of interest. */ i2c->int_en0 = MXC_F_I2C_INT_EN0_RX_THRESH | MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; + I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; } /** @@ -525,15 +526,15 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) /* Get the request context for this interrupt. */ req = states[MXC_I2C_GET_IDX(i2c)].req; - /* Check for an address match flag. */ - if ((req->expecting_start) && (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) { + if ((req->expecting_start) && + (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH)) { req->expecting_done = true; req->expecting_start = false; /* - * Save the address match index to identify - * targeted target address. - */ + * Save the address match index to identify + * targeted target address. + */ req->addr_match_flag = (i2c->int_fl0 & MXC_F_I2C_INT_FL0_MAMI_MASK) >> MXC_F_I2C_INT_FL0_MAMI_POS; @@ -543,8 +544,8 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) i2c->int_fl1 = i2c->int_fl1; /* Only enable done, error and address match interrupts. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; + i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | + MXC_F_I2C_INT_EN0_ADDR_MATCH; /* Check if Controller is writing to the target. */ if (!(i2c->ctrl & MXC_F_I2C_CTRL_READ)) { @@ -564,10 +565,11 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) */ req->response_pending = false; /* Set the RX threshold interrupt level. */ - i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & - ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | - (MXC_I2C_FIFO_DEPTH - 2) - << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + i2c->rx_ctrl0 = + ((i2c->rx_ctrl0 & + ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (MXC_I2C_FIFO_DEPTH - 2) + << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); } else { /* * The Controller is reading from the target. @@ -576,25 +578,28 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) */ req->tx_data = host_buffer; req->state = I2C_TARGET_ADDR_MATCH_READ; - /* Set the threshold for TX, the threshold is a four bit field. */ - i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | - (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); + /* Set the threshold for TX, the threshold is a four bit + * field. */ + i2c->tx_ctrl0 = + ((i2c->tx_ctrl0 & + ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | + (2 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); #ifdef CONFIG_BOARD_I2C_ADDR_FLAGS /* - * If this is a board address match and there is not - * already a pending response to the I2C Controller then - * fulfill this board read request. - */ + * If this is a board address match and there is not + * already a pending response to the I2C Controller then + * fulfill this board read request. + */ if ((req->response_pending == 0) && - (req->addr_match_flag != 0x1)) { + (req->addr_match_flag != 0x1)) { i2c_process_board_command( 1, CONFIG_BOARD_I2C_ADDR_FLAGS, 0); } #endif /* CONFIG_BOARD_I2C_ADDR_FLAGS */ } /* Only enable done, error and address match interrupts. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; + i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | + MXC_F_I2C_INT_EN0_ADDR_MATCH; /* Inhibit sleep mode when addressed until STOPF flag is set. */ disable_sleep(SLEEP_MASK_I2C_PERIPHERAL); } @@ -605,14 +610,15 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) req->expecting_done = false; /* Clear all interrupts except a possible address match. */ i2c->int_fl0 = i2c->int_fl0 & ~(MXC_F_I2C_INT_FL0_ADDR_MATCH | - MXC_F_I2C_INT_FL0_MAMI_MASK); + MXC_F_I2C_INT_FL0_MAMI_MASK); i2c->int_fl1 = i2c->int_fl1; /* Only enable done, error and address match interrupts. */ - i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | - I2C_ERROR | MXC_F_I2C_INT_EN0_ADDR_MATCH; + i2c->int_en0 = MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | + MXC_F_I2C_INT_EN0_ADDR_MATCH; i2c->int_en1 = 0; - /* If this was a DONE after a write then read the fifo until empty. */ + /* If this was a DONE after a write then read the fifo until + * empty. */ if (req->state == I2C_TARGET_ADDR_MATCH_WRITE) { /* Read out any data in the RX FIFO. */ while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { @@ -654,7 +660,6 @@ static void i2c_target_handler(mxc_i2c_regs_t *i2c) /* Service a write request from the I2C Controller. */ i2c_target_service_write(i2c, req); } - } /** @@ -713,10 +718,9 @@ static int i2c_target_async(mxc_i2c_regs_t *i2c, i2c_req_t *req) i2c->int_fl1 = i2c->int_fl1; /* Set the RX threshold interrupt level. */ - i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & - ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | - (MXC_I2C_FIFO_DEPTH - 2) - << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + i2c->rx_ctrl0 = + ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (MXC_I2C_FIFO_DEPTH - 2) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); /* Only enable the I2C Address match interrupt. */ i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH; @@ -734,7 +738,6 @@ static void i2c_send_board_response(int len) req_target.response_pending = true; } - static void i2c_process_board_command(int read, int addr, int len) { board_i2c_process(read, addr, len, &host_buffer[0], @@ -774,15 +777,17 @@ static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed) time_scl_min = 1000000 / (target_bus_freq / 1000); clock_low_min = ((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) / - time_pclk) - 1; + time_pclk) - + 1; clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) - - T_AF_MIN) / - time_pclk) - 1; + T_AF_MIN) / + time_pclk) - + 1; clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2; - ticks_lo = (clock_low_min > (clock_min - clock_high_min)) - ? (clock_low_min) - : (clock_min - clock_high_min); + ticks_lo = (clock_low_min > (clock_min - clock_high_min)) ? + (clock_low_min) : + (clock_min - clock_high_min); ticks_hi = clock_high_min; if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >> @@ -900,7 +905,8 @@ static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed) * Return EC_SUCCESS, or non-zero if error. */ static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, const uint8_t *data, int len, int restart) + int stop, const uint8_t *data, int len, + int restart) { if (len == 0) { return EC_SUCCESS; @@ -1019,7 +1025,7 @@ static int i2c_controller_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start, * Return: EC_SUCCESS if successful, otherwise returns a common error code */ static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start, - int stop, uint8_t *data, int len, int restart) + int stop, uint8_t *data, int len, int restart) { volatile int length = len; int interactive_receive_mode; @@ -1077,7 +1083,8 @@ static int i2c_controller_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start, return EC_ERROR_UNKNOWN; } - /* If in interactive receive mode then ack each received byte. */ + /* If in interactive receive mode then ack each received byte. + */ if (interactive_receive_mode) { while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE)) ; -- cgit v1.2.1 From 80929b0a0ce2eb29205ca4dbe59dde4c8ae7ba5d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:41 -0600 Subject: baseboard/asurada/baseboard_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70abc05642af625bcee1c8a2cc17440449e6f386 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727849 Reviewed-by: Jeremy Bettis --- baseboard/asurada/baseboard_common.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/baseboard/asurada/baseboard_common.h b/baseboard/asurada/baseboard_common.h index 0245ae42bf..abd5a9b5c6 100644 --- a/baseboard/asurada/baseboard_common.h +++ b/baseboard/asurada/baseboard_common.h @@ -9,12 +9,12 @@ #define __CROS_EC_BASEBOARD_COMMON_H /* GPIO name remapping */ -#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 -#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 +#define GPIO_EN_HDMI_PWR GPIO_EC_X_GPIO1 +#define GPIO_USB_C1_FRS_EN GPIO_EC_X_GPIO1 #define GPIO_USB_C1_PPC_INT_ODL GPIO_X_EC_GPIO2 -#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 -#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 -#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 +#define GPIO_PS185_EC_DP_HPD GPIO_X_EC_GPIO2 +#define GPIO_USB_C1_DP_IN_HPD GPIO_EC_X_GPIO3 +#define GPIO_PS185_PWRDN_ODL GPIO_EC_X_GPIO3 #ifndef __ASSEMBLER__ -- cgit v1.2.1 From b1e8c6b8ad8df9059a0441e754e02e9663ae285b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:37 -0600 Subject: baseboard/dedede/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4218f2b0bb2d66183f2a78c442ac289a6cd624a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727871 Reviewed-by: Jeremy Bettis --- baseboard/dedede/baseboard.h | 139 ++++++++++++++++++++----------------------- 1 file changed, 66 insertions(+), 73 deletions(-) diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index 0085c48ec3..dff4cd5e7f 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -12,7 +12,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -20,39 +20,37 @@ * Variant EC defines. Pick one: * VARIANT_DEDEDE_EC_NPCX796FC */ -#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || \ - defined(VARIANT_KEEBY_EC_NPCX797FC) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* No tach. */ - - /* Internal SPI flash on NPCX7 */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_A - #define I2C_PORT_BATTERY IT83XX_I2C_CH_B - #define I2C_PORT_SENSOR IT83XX_I2C_CH_C - #define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_C0 IT83XX_I2C_CH_F - - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - #define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ - - #undef CONFIG_UART_TX_BUF_SIZE /* UART */ - #define CONFIG_UART_TX_BUF_SIZE 4096 - - /* - * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at - * 48MHz core cpu clock. - */ - #define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 +#if defined(VARIANT_DEDEDE_EC_NPCX796FC) || defined(VARIANT_KEEBY_EC_NPCX797FC) +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ +#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320) +/* IT83XX config */ +#define CONFIG_IT83XX_VCC_1P8V +/* I2C Bus Configuration */ +#define I2C_PORT_EEPROM IT83XX_I2C_CH_A +#define I2C_PORT_BATTERY IT83XX_I2C_CH_B +#define I2C_PORT_SENSOR IT83XX_I2C_CH_C +#define I2C_PORT_SUB_USB_C1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_C0 IT83XX_I2C_CH_F + +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +#define CONFIG_ADC_VOLTAGE_COMPARATOR /* ITE ADC thresholds */ + +#undef CONFIG_UART_TX_BUF_SIZE /* UART */ +#define CONFIG_UART_TX_BUF_SIZE 4096 + +/* + * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at + * 48MHz core cpu clock. + */ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 #else #error "Must define a VARIANT_[DEDEDE|KEEBY]_EC!" #endif @@ -71,36 +69,36 @@ * Remapping of schematic GPIO names to common GPIO names expected (hardcoded) * in the EC code base. */ -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L -#define GPIO_EN_PP5000 GPIO_EN_PP5000_U -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_MKBP_INT_L +#define GPIO_EN_PP5000 GPIO_EN_PP5000_U +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV #if !KEEBY_VARIANT -#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE +#define GPIO_PACKET_MODE_EN GPIO_ECH1_PACKET_MODE #endif -#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK -#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_AP_DPWROK +#define GPIO_PCH_PWRBTN_L GPIO_EC_AP_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_AP_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_AP_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_PCH_WAKE_L GPIO_EC_AP_WAKE_ODL +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L #if KEEBY_VARIANT -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL #else -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL #endif -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD -#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_WP GPIO_EC_WP_OD -#define GPIO_TABLET_MODE_L GPIO_LID_360_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_USB_C0_DP_HPD GPIO_EC_AP_USB_C0_HPD +#define GPIO_USB_C1_DP_HPD GPIO_EC_AP_USB_C1_HDMI_HPD +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_WP GPIO_EC_WP_OD +#define GPIO_TABLET_MODE_L GPIO_LID_360_L /* Common EC defines */ @@ -175,7 +173,7 @@ /* Backlight */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD +#define GPIO_ENABLE_BACKLIGHT GPIO_EN_BL_OD /* LED */ #define CONFIG_LED_COMMON @@ -206,7 +204,7 @@ /* Temp Sensor */ #define CONFIG_TEMP_SENSOR_POWER -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A #define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 /* USB PD */ @@ -238,14 +236,14 @@ #endif /* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 45000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 45000 #define PD_OPERATING_POWER_MW 15000 /* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ #ifndef __ASSEMBLER__ @@ -255,13 +253,8 @@ /* Common enums */ #if defined(VARIANT_DEDEDE_EC_NPCX796FC) -#elif defined(VARIANT_DEDEDE_EC_IT8320) || \ - defined(VARIANT_KEEBY_EC_IT8320) - enum board_vcmp { - VCMP_SNS_PP3300_LOW, - VCMP_SNS_PP3300_HIGH, - VCMP_COUNT - }; +#elif defined(VARIANT_DEDEDE_EC_IT8320) || defined(VARIANT_KEEBY_EC_IT8320) +enum board_vcmp { VCMP_SNS_PP3300_LOW, VCMP_SNS_PP3300_HIGH, VCMP_COUNT }; #endif /* Interrupt handler for signals that are used to generate ALL_SYS_PGOOD. */ -- cgit v1.2.1 From c3a3a4d0841ebccfb84d90b4bd76bb4635d44fbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:34 -0600 Subject: board/damu/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4dc56eeea9a1bbfcb011f9193f17814cb7c2839c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728219 Reviewed-by: Jeremy Bettis --- board/damu/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/damu/board.h b/board/damu/board.h index 1d2993443a..4ca152f58b 100644 --- a/board/damu/board.h +++ b/board/damu/board.h @@ -55,7 +55,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -71,20 +71,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 2 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 2 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 82ccd262f37ac7b1b6beeed1ab55d645a2b77ef7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:03 -0600 Subject: baseboard/intelrvp/chg_usb_pd_mecc_1_0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I93b6d867bc4813f3937638adc257365825f719dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727897 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/chg_usb_pd_mecc_1_0.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c index 38bd3cef9e..95d9897ee8 100644 --- a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c +++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c @@ -19,8 +19,8 @@ #include "intelrvp.h" #endif /* CONFIG_ZEPHYR */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Reset PD MCU */ void board_reset_pd_mcu(void) @@ -97,7 +97,7 @@ void ppc_interrupt(enum gpio_signal signal) for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { if (tcpc_aic_gpios[i].ppc_intr_handler && - signal == tcpc_aic_gpios[i].ppc_alert) { + signal == tcpc_aic_gpios[i].ppc_alert) { tcpc_aic_gpios[i].ppc_intr_handler(i); break; } @@ -107,6 +107,6 @@ void ppc_interrupt(enum gpio_signal signal) void board_charging_enable(int port, int enable) { if (ppc_vbus_sink_enable(port, enable)) - CPRINTS("C%d: sink path %s failed", - port, enable ? "en" : "dis"); + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); } -- cgit v1.2.1 From 4e35122258a2958a06866404e703370efcbe7c31 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:26 -0600 Subject: common/aes.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I658c833765dea48c5d00d9f311ccfed9a2a97d26 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729584 Reviewed-by: Jeremy Bettis --- common/aes.c | 831 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 830 insertions(+), 1 deletion(-) mode change 120000 => 100644 common/aes.c diff --git a/common/aes.c b/common/aes.c deleted file mode 120000 index ed10836943..0000000000 --- a/common/aes.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/common/aes.c \ No newline at end of file diff --git a/common/aes.c b/common/aes.c new file mode 100644 index 0000000000..beebc9d2fc --- /dev/null +++ b/common/aes.c @@ -0,0 +1,830 @@ +/* ==================================================================== + * Copyright (c) 2002-2006 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== */ + +#include "aes.h" +#include "common.h" +#include "endian.h" + +static inline uint32_t GETU32(const void *in) +{ + return be32toh(*(uint32_t *)in); +} + +static inline void PUTU32(void *out, uint32_t v) +{ + *(uint32_t *)out = htobe32(v); +} + +// Te0[x] = S [x].[02, 01, 01, 03]; +// Te1[x] = S [x].[03, 02, 01, 01]; +// Te2[x] = S [x].[01, 03, 02, 01]; +// Te3[x] = S [x].[01, 01, 03, 02]; +// +// Td0[x] = Si[x].[0e, 09, 0d, 0b]; +// Td1[x] = Si[x].[0b, 0e, 09, 0d]; +// Td2[x] = Si[x].[0d, 0b, 0e, 09]; +// Td3[x] = Si[x].[09, 0d, 0b, 0e]; +// Td4[x] = Si[x].[01]; + +static const uint32_t Te0[256] = { + 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, 0xfff2f20dU, + 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, 0x60303050U, 0x02010103U, + 0xce6767a9U, 0x562b2b7dU, 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, + 0xec76769aU, 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, + 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, 0x41adadecU, + 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, 0x239c9cbfU, 0x53a4a4f7U, + 0xe4727296U, 0x9bc0c05bU, 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, + 0x4c26266aU, 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, + 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, 0xe2717193U, + 0xabd8d873U, 0x62313153U, 0x2a15153fU, 0x0804040cU, 0x95c7c752U, + 0x46232365U, 0x9dc3c35eU, 0x30181828U, 0x379696a1U, 0x0a05050fU, + 0x2f9a9ab5U, 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, + 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, 0x1209091bU, + 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, 0x361b1b2dU, 0xdc6e6eb2U, + 0xb45a5aeeU, 0x5ba0a0fbU, 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, + 0x7db3b3ceU, 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, + 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, 0x40202060U, + 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, 0xd46a6abeU, 0x8dcbcb46U, + 0x67bebed9U, 0x7239394bU, 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, + 0x85cfcf4aU, 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, + 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, 0x8a4545cfU, + 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, 0xa05050f0U, 0x783c3c44U, + 0x259f9fbaU, 0x4ba8a8e3U, 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, + 0x058f8f8aU, 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, + 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, 0x20101030U, + 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, 0x81cdcd4cU, 0x180c0c14U, + 0x26131335U, 0xc3ecec2fU, 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, + 0x2e171739U, 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, + 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, 0xc06060a0U, + 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, 0x44222266U, 0x542a2a7eU, + 0x3b9090abU, 0x0b888883U, 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, + 0x2814143cU, 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, + 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, 0x924949dbU, + 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, 0x9fc2c25dU, 0xbdd3d36eU, + 0x43acacefU, 0xc46262a6U, 0x399191a8U, 0x319595a4U, 0xd3e4e437U, + 0xf279798bU, 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, + 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, 0xd86c6cb4U, + 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, 0xca6565afU, 0xf47a7a8eU, + 0x47aeaee9U, 0x10080818U, 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, + 0x5c2e2e72U, 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, + 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, 0x964b4bddU, + 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, 0xe0707090U, 0x7c3e3e42U, + 0x71b5b5c4U, 0xcc6666aaU, 0x904848d8U, 0x06030305U, 0xf7f6f601U, + 0x1c0e0e12U, 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, + 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, 0xd9e1e138U, + 0xebf8f813U, 0x2b9898b3U, 0x22111133U, 0xd26969bbU, 0xa9d9d970U, + 0x078e8e89U, 0x339494a7U, 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, + 0xc9e9e920U, 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, + 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, 0x65bfbfdaU, + 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, 0x824141c3U, 0x299999b0U, + 0x5a2d2d77U, 0x1e0f0f11U, 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, + 0x2c16163aU, +}; + +static const uint32_t Te1[256] = { + 0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU, 0x0dfff2f2U, + 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U, 0x50603030U, 0x03020101U, + 0xa9ce6767U, 0x7d562b2bU, 0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, + 0x9aec7676U, 0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU, + 0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U, 0xec41adadU, + 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU, 0xbf239c9cU, 0xf753a4a4U, + 0x96e47272U, 0x5b9bc0c0U, 0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, + 0x6a4c2626U, 0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU, + 0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U, 0x93e27171U, + 0x73abd8d8U, 0x53623131U, 0x3f2a1515U, 0x0c080404U, 0x5295c7c7U, + 0x65462323U, 0x5e9dc3c3U, 0x28301818U, 0xa1379696U, 0x0f0a0505U, + 0xb52f9a9aU, 0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U, + 0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U, 0x1b120909U, + 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU, 0x2d361b1bU, 0xb2dc6e6eU, + 0xeeb45a5aU, 0xfb5ba0a0U, 0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, + 0xce7db3b3U, 0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U, + 0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU, 0x60402020U, + 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU, 0xbed46a6aU, 0x468dcbcbU, + 0xd967bebeU, 0x4b723939U, 0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, + 0x4a85cfcfU, 0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU, + 0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U, 0xcf8a4545U, + 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU, 0xf0a05050U, 0x44783c3cU, + 0xba259f9fU, 0xe34ba8a8U, 0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, + 0x8a058f8fU, 0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U, + 0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U, 0x30201010U, + 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U, 0x4c81cdcdU, 0x14180c0cU, + 0x35261313U, 0x2fc3ececU, 0xe1be5f5fU, 0xa2359797U, 0xcc884444U, + 0x392e1717U, 0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU, + 0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U, 0xa0c06060U, + 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU, 0x66442222U, 0x7e542a2aU, + 0xab3b9090U, 0x830b8888U, 0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, + 0x3c281414U, 0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU, + 0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU, 0xdb924949U, + 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU, 0x5d9fc2c2U, 0x6ebdd3d3U, + 0xef43acacU, 0xa6c46262U, 0xa8399191U, 0xa4319595U, 0x37d3e4e4U, + 0x8bf27979U, 0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU, + 0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U, 0xb4d86c6cU, + 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU, 0xafca6565U, 0x8ef47a7aU, + 0xe947aeaeU, 0x18100808U, 0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, + 0x725c2e2eU, 0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U, + 0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU, 0xdd964b4bU, + 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU, 0x90e07070U, 0x427c3e3eU, + 0xc471b5b5U, 0xaacc6666U, 0xd8904848U, 0x05060303U, 0x01f7f6f6U, + 0x121c0e0eU, 0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U, + 0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU, 0x38d9e1e1U, + 0x13ebf8f8U, 0xb32b9898U, 0x33221111U, 0xbbd26969U, 0x70a9d9d9U, + 0x89078e8eU, 0xa7339494U, 0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, + 0x20c9e9e9U, 0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU, + 0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU, 0xda65bfbfU, + 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U, 0xc3824141U, 0xb0299999U, + 0x775a2d2dU, 0x111e0f0fU, 0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, + 0x3a2c1616U, +}; + +static const uint32_t Te2[256] = { + 0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU, 0xf20dfff2U, + 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U, 0x30506030U, 0x01030201U, + 0x67a9ce67U, 0x2b7d562bU, 0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, + 0x769aec76U, 0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU, + 0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U, 0xadec41adU, + 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU, 0x9cbf239cU, 0xa4f753a4U, + 0x7296e472U, 0xc05b9bc0U, 0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, + 0x266a4c26U, 0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU, + 0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U, 0x7193e271U, + 0xd873abd8U, 0x31536231U, 0x153f2a15U, 0x040c0804U, 0xc75295c7U, + 0x23654623U, 0xc35e9dc3U, 0x18283018U, 0x96a13796U, 0x050f0a05U, + 0x9ab52f9aU, 0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U, + 0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U, 0x091b1209U, + 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU, 0x1b2d361bU, 0x6eb2dc6eU, + 0x5aeeb45aU, 0xa0fb5ba0U, 0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, + 0xb3ce7db3U, 0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U, + 0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU, 0x20604020U, + 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU, 0x6abed46aU, 0xcb468dcbU, + 0xbed967beU, 0x394b7239U, 0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, + 0xcf4a85cfU, 0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU, + 0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U, 0x45cf8a45U, + 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU, 0x50f0a050U, 0x3c44783cU, + 0x9fba259fU, 0xa8e34ba8U, 0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, + 0x8f8a058fU, 0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U, + 0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U, 0x10302010U, + 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U, 0xcd4c81cdU, 0x0c14180cU, + 0x13352613U, 0xec2fc3ecU, 0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, + 0x17392e17U, 0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU, + 0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U, 0x60a0c060U, + 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU, 0x22664422U, 0x2a7e542aU, + 0x90ab3b90U, 0x88830b88U, 0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, + 0x143c2814U, 0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU, + 0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU, 0x49db9249U, + 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU, 0xc25d9fc2U, 0xd36ebdd3U, + 0xacef43acU, 0x62a6c462U, 0x91a83991U, 0x95a43195U, 0xe437d3e4U, + 0x798bf279U, 0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU, + 0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U, 0x6cb4d86cU, + 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU, 0x65afca65U, 0x7a8ef47aU, + 0xaee947aeU, 0x08181008U, 0xbad56fbaU, 0x7888f078U, 0x256f4a25U, + 0x2e725c2eU, 0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U, + 0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU, 0x4bdd964bU, + 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU, 0x7090e070U, 0x3e427c3eU, + 0xb5c471b5U, 0x66aacc66U, 0x48d89048U, 0x03050603U, 0xf601f7f6U, + 0x0e121c0eU, 0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U, + 0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU, 0xe138d9e1U, + 0xf813ebf8U, 0x98b32b98U, 0x11332211U, 0x69bbd269U, 0xd970a9d9U, + 0x8e89078eU, 0x94a73394U, 0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, + 0xe920c9e9U, 0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU, + 0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU, 0xbfda65bfU, + 0xe631d7e6U, 0x42c68442U, 0x68b8d068U, 0x41c38241U, 0x99b02999U, + 0x2d775a2dU, 0x0f111e0fU, 0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, + 0x163a2c16U, +}; + +static const uint32_t Te3[256] = { + 0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U, 0xf2f20dffU, + 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U, 0x30305060U, 0x01010302U, + 0x6767a9ceU, 0x2b2b7d56U, 0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, + 0x76769aecU, 0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU, + 0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU, 0xadadec41U, + 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U, 0x9c9cbf23U, 0xa4a4f753U, + 0x727296e4U, 0xc0c05b9bU, 0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, + 0x26266a4cU, 0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U, + 0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U, 0x717193e2U, + 0xd8d873abU, 0x31315362U, 0x15153f2aU, 0x04040c08U, 0xc7c75295U, + 0x23236546U, 0xc3c35e9dU, 0x18182830U, 0x9696a137U, 0x05050f0aU, + 0x9a9ab52fU, 0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU, + 0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU, 0x09091b12U, + 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U, 0x1b1b2d36U, 0x6e6eb2dcU, + 0x5a5aeeb4U, 0xa0a0fb5bU, 0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, + 0xb3b3ce7dU, 0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U, + 0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U, 0x20206040U, + 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U, 0x6a6abed4U, 0xcbcb468dU, + 0xbebed967U, 0x39394b72U, 0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, + 0xcfcf4a85U, 0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU, + 0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U, 0x4545cf8aU, + 0xf9f910e9U, 0x02020604U, 0x7f7f81feU, 0x5050f0a0U, 0x3c3c4478U, + 0x9f9fba25U, 0xa8a8e34bU, 0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, + 0x8f8f8a05U, 0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U, + 0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U, 0x10103020U, + 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU, 0xcdcd4c81U, 0x0c0c1418U, + 0x13133526U, 0xecec2fc3U, 0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, + 0x1717392eU, 0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU, + 0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U, 0x6060a0c0U, + 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U, 0x22226644U, 0x2a2a7e54U, + 0x9090ab3bU, 0x8888830bU, 0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, + 0x14143c28U, 0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU, + 0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U, 0x4949db92U, + 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U, 0xc2c25d9fU, 0xd3d36ebdU, + 0xacacef43U, 0x6262a6c4U, 0x9191a839U, 0x9595a431U, 0xe4e437d3U, + 0x79798bf2U, 0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU, + 0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U, 0x6c6cb4d8U, + 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU, 0x6565afcaU, 0x7a7a8ef4U, + 0xaeaee947U, 0x08081810U, 0xbabad56fU, 0x787888f0U, 0x25256f4aU, + 0x2e2e725cU, 0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U, + 0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU, 0x4b4bdd96U, + 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU, 0x707090e0U, 0x3e3e427cU, + 0xb5b5c471U, 0x6666aaccU, 0x4848d890U, 0x03030506U, 0xf6f601f7U, + 0x0e0e121cU, 0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U, + 0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U, 0xe1e138d9U, + 0xf8f813ebU, 0x9898b32bU, 0x11113322U, 0x6969bbd2U, 0xd9d970a9U, + 0x8e8e8907U, 0x9494a733U, 0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, + 0xe9e920c9U, 0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U, + 0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU, 0xbfbfda65U, + 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U, 0x4141c382U, 0x9999b029U, + 0x2d2d775aU, 0x0f0f111eU, 0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, + 0x16163a2cU, +}; + +static const uint32_t Td0[256] = { + 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, 0x3bab6bcbU, + 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, 0x2030fa55U, 0xad766df6U, + 0x88cc7691U, 0xf5024c25U, 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, + 0xb562a38fU, 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, + 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, 0x038f5fe7U, + 0x15929c95U, 0xbf6d7aebU, 0x955259daU, 0xd4be832dU, 0x587421d3U, + 0x49e06929U, 0x8ec9c844U, 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, + 0x27b971ddU, 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, + 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, 0xb16477e0U, + 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, 0x70486858U, 0x8f45fd19U, + 0x94de6c87U, 0x527bf8b7U, 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, + 0x6655ab2aU, 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, + 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, 0x8acf1c2bU, + 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, 0x65daf4cdU, 0x0605bed5U, + 0xd134621fU, 0xc4a6fe8aU, 0x342e539dU, 0xa2f355a0U, 0x058ae132U, + 0xa4f6eb75U, 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, + 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, 0x91548db5U, + 0x71c45d05U, 0x0406d46fU, 0x605015ffU, 0x1998fb24U, 0xd6bde997U, + 0x894043ccU, 0x67d99e77U, 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, + 0x79c8eedbU, 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, + 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, 0xfd0efffbU, + 0x0f853856U, 0x3daed51eU, 0x362d3927U, 0x0a0fd964U, 0x685ca621U, + 0x9b5b54d1U, 0x24362e3aU, 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, + 0x1b9b919eU, 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, + 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, 0x0e090d0bU, + 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, 0x57f11985U, 0xaf75074cU, + 0xee99ddbbU, 0xa37f60fdU, 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, + 0x5bfb7e34U, 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, + 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, 0x854a247dU, + 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, 0x1d9e2f4bU, 0xdcb230f3U, + 0x0d8652ecU, 0x77c1e3d0U, 0x2bb3166cU, 0xa970b999U, 0x119448faU, + 0x47e96422U, 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, + 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, 0xa6f581cfU, + 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, 0x2c3a9de4U, 0x5078920dU, + 0x6a5fcc9bU, 0x547e4662U, 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, + 0x82c3aff5U, 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, + 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, 0xcd267809U, + 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, 0xe6956e65U, 0xaaffe67eU, + 0x21bccf08U, 0xef15e8e6U, 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, + 0x29b07cd6U, 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, + 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, 0xf104984aU, + 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, 0x764dd68dU, 0x43efb04dU, + 0xccaa4d54U, 0xe49604dfU, 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, + 0x4665517fU, 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, + 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, 0x9ad7618cU, + 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, 0xcea927eeU, 0xb761c935U, + 0xe11ce5edU, 0x7a47b13cU, 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, + 0x73c737bfU, 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, + 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, 0x161dc372U, + 0xbce2250cU, 0x283c498bU, 0xff0d9541U, 0x39a80171U, 0x080cb3deU, + 0xd8b4e49cU, 0x6456c190U, 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, + 0xd0b85742U, +}; + +static const uint32_t Td1[256] = { + 0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU, 0xcb3bab6bU, + 0xf11f9d45U, 0xabacfa58U, 0x934be303U, 0x552030faU, 0xf6ad766dU, + 0x9188cc76U, 0x25f5024cU, 0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, + 0x8fb562a3U, 0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U, + 0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U, 0xe7038f5fU, + 0x9515929cU, 0xebbf6d7aU, 0xda955259U, 0x2dd4be83U, 0xd3587421U, + 0x2949e069U, 0x448ec9c8U, 0x6a75c289U, 0x78f48e79U, 0x6b99583eU, + 0xdd27b971U, 0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU, + 0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU, 0xe0b16477U, + 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU, 0x58704868U, 0x198f45fdU, + 0x8794de6cU, 0xb7527bf8U, 0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, + 0x2a6655abU, 0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U, + 0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U, 0x2b8acf1cU, + 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U, 0xcd65daf4U, 0xd50605beU, + 0x1fd13462U, 0x8ac4a6feU, 0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, + 0x75a4f6ebU, 0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U, + 0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU, 0xb591548dU, + 0x0571c45dU, 0x6f0406d4U, 0xff605015U, 0x241998fbU, 0x97d6bde9U, + 0xcc894043U, 0x7767d99eU, 0xbdb0e842U, 0x8807898bU, 0x38e7195bU, + 0xdb79c8eeU, 0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U, + 0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U, 0xfbfd0effU, + 0x560f8538U, 0x1e3daed5U, 0x27362d39U, 0x640a0fd9U, 0x21685ca6U, + 0xd19b5b54U, 0x3a24362eU, 0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, + 0x9e1b9b91U, 0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU, + 0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U, 0x0b0e090dU, + 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U, 0x8557f119U, 0x4caf7507U, + 0xbbee99ddU, 0xfda37f60U, 0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, + 0x345bfb7eU, 0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U, + 0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U, 0x7d854a24U, + 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U, 0x4b1d9e2fU, 0xf3dcb230U, + 0xec0d8652U, 0xd077c1e3U, 0x6c2bb316U, 0x99a970b9U, 0xfa119448U, + 0x2247e964U, 0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U, + 0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU, 0xcfa6f581U, + 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU, 0xe42c3a9dU, 0x0d507892U, + 0x9b6a5fccU, 0x62547e46U, 0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, + 0xf582c3afU, 0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U, + 0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU, 0x09cd2678U, + 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU, 0x65e6956eU, 0x7eaaffe6U, + 0x0821bccfU, 0xe6ef15e8U, 0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, + 0xd629b07cU, 0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U, + 0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U, 0x4af10498U, + 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U, 0x8d764dd6U, 0x4d43efb0U, + 0x54ccaa4dU, 0xdfe49604U, 0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, + 0x7f466551U, 0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U, + 0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U, 0x8c9ad761U, + 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU, 0xeecea927U, 0x35b761c9U, + 0xede11ce5U, 0x3c7a47b1U, 0x599cd2dfU, 0x3f55f273U, 0x791814ceU, + 0xbf73c737U, 0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU, + 0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U, 0x72161dc3U, + 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U, 0x7139a801U, 0xde080cb3U, + 0x9cd8b4e4U, 0x906456c1U, 0x617bcb84U, 0x70d532b6U, 0x74486c5cU, + 0x42d0b857U, +}; + +static const uint32_t Td2[256] = { + 0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U, 0x6bcb3babU, + 0x45f11f9dU, 0x58abacfaU, 0x03934be3U, 0xfa552030U, 0x6df6ad76U, + 0x769188ccU, 0x4c25f502U, 0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, + 0xa38fb562U, 0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU, + 0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U, 0x5fe7038fU, + 0x9c951592U, 0x7aebbf6dU, 0x59da9552U, 0x832dd4beU, 0x21d35874U, + 0x692949e0U, 0xc8448ec9U, 0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, + 0x71dd27b9U, 0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU, + 0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U, 0x77e0b164U, + 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U, 0x68587048U, 0xfd198f45U, + 0x6c8794deU, 0xf8b7527bU, 0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, + 0xab2a6655U, 0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U, + 0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U, 0x1c2b8acfU, + 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U, 0xf4cd65daU, 0xbed50605U, + 0x621fd134U, 0xfe8ac4a6U, 0x539d342eU, 0x55a0a2f3U, 0xe132058aU, + 0xeb75a4f6U, 0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU, + 0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U, 0x8db59154U, + 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U, 0xfb241998U, 0xe997d6bdU, + 0x43cc8940U, 0x9e7767d9U, 0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, + 0xeedb79c8U, 0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U, + 0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU, 0xfffbfd0eU, + 0x38560f85U, 0xd51e3daeU, 0x3927362dU, 0xd9640a0fU, 0xa621685cU, + 0x54d19b5bU, 0x2e3a2436U, 0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, + 0x919e1b9bU, 0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U, + 0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU, 0x0d0b0e09U, + 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU, 0x198557f1U, 0x074caf75U, + 0xddbbee99U, 0x60fda37fU, 0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, + 0x7e345bfbU, 0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U, + 0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U, 0x247d854aU, + 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U, 0x2f4b1d9eU, 0x30f3dcb2U, + 0x52ec0d86U, 0xe3d077c1U, 0x166c2bb3U, 0xb999a970U, 0x48fa1194U, + 0x642247e9U, 0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U, + 0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U, 0x81cfa6f5U, + 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU, 0x9de42c3aU, 0x920d5078U, + 0xcc9b6a5fU, 0x4662547eU, 0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, + 0xaff582c3U, 0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U, + 0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU, 0x7809cd26U, + 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU, 0x6e65e695U, 0xe67eaaffU, + 0xcf0821bcU, 0xe8e6ef15U, 0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, + 0x7cd629b0U, 0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U, + 0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U, 0x984af104U, + 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U, 0xd68d764dU, 0xb04d43efU, + 0x4d54ccaaU, 0x04dfe496U, 0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, + 0x517f4665U, 0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU, + 0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U, 0x618c9ad7U, + 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U, 0x27eecea9U, 0xc935b761U, + 0xe5ede11cU, 0xb13c7a47U, 0xdf599cd2U, 0x733f55f2U, 0xce791814U, + 0x37bf73c7U, 0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U, + 0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U, 0xc372161dU, + 0x250cbce2U, 0x498b283cU, 0x9541ff0dU, 0x017139a8U, 0xb3de080cU, + 0xe49cd8b4U, 0xc1906456U, 0x84617bcbU, 0xb670d532U, 0x5c74486cU, + 0x5742d0b8U, +}; + +static const uint32_t Td3[256] = { + 0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU, 0xab6bcb3bU, + 0x9d45f11fU, 0xfa58abacU, 0xe303934bU, 0x30fa5520U, 0x766df6adU, + 0xcc769188U, 0x024c25f5U, 0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, + 0x62a38fb5U, 0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU, + 0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU, 0x8f5fe703U, + 0x929c9515U, 0x6d7aebbfU, 0x5259da95U, 0xbe832dd4U, 0x7421d358U, + 0xe0692949U, 0xc9c8448eU, 0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, + 0xb971dd27U, 0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU, + 0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U, 0x6477e0b1U, + 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U, 0x48685870U, 0x45fd198fU, + 0xde6c8794U, 0x7bf8b752U, 0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, + 0x55ab2a66U, 0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U, + 0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU, 0xcf1c2b8aU, + 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU, 0xdaf4cd65U, 0x05bed506U, + 0x34621fd1U, 0xa6fe8ac4U, 0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, + 0xf6eb75a4U, 0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU, + 0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU, 0x548db591U, + 0xc45d0571U, 0x06d46f04U, 0x5015ff60U, 0x98fb2419U, 0xbde997d6U, + 0x4043cc89U, 0xd99e7767U, 0xe842bdb0U, 0x898b8807U, 0x195b38e7U, + 0xc8eedb79U, 0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U, + 0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU, 0x0efffbfdU, + 0x8538560fU, 0xaed51e3dU, 0x2d392736U, 0x0fd9640aU, 0x5ca62168U, + 0x5b54d19bU, 0x362e3a24U, 0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, + 0x9b919e1bU, 0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU, + 0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U, 0x090d0b0eU, + 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U, 0xf1198557U, 0x75074cafU, + 0x99ddbbeeU, 0x7f60fda3U, 0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, + 0xfb7e345bU, 0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U, + 0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U, 0x4a247d85U, + 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U, 0x9e2f4b1dU, 0xb230f3dcU, + 0x8652ec0dU, 0xc1e3d077U, 0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, + 0xe9642247U, 0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U, + 0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U, 0xf581cfa6U, + 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU, 0x3a9de42cU, 0x78920d50U, + 0x5fcc9b6aU, 0x7e466254U, 0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, + 0xc3aff582U, 0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU, + 0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU, 0x267809cdU, + 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U, 0x956e65e6U, 0xffe67eaaU, + 0xbccf0821U, 0x15e8e6efU, 0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, + 0xb07cd629U, 0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U, + 0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U, 0x04984af1U, + 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U, 0x4dd68d76U, 0xefb04d43U, + 0xaa4d54ccU, 0x9604dfe4U, 0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, + 0x65517f46U, 0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU, + 0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU, 0xd7618c9aU, + 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU, 0xa927eeceU, 0x61c935b7U, + 0x1ce5ede1U, 0x47b13c7aU, 0xd2df599cU, 0xf2733f55U, 0x14ce7918U, + 0xc737bf73U, 0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U, + 0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U, 0x1dc37216U, + 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU, 0xa8017139U, 0x0cb3de08U, + 0xb4e49cd8U, 0x56c19064U, 0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, + 0xb85742d0U, +}; + +static const uint8_t Td4[256] = { + 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, 0xbfU, 0x40U, + 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, 0x7cU, 0xe3U, 0x39U, 0x82U, + 0x9bU, 0x2fU, 0xffU, 0x87U, 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, + 0xe9U, 0xcbU, 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, + 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, 0x08U, 0x2eU, + 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, 0x76U, 0x5bU, 0xa2U, 0x49U, + 0x6dU, 0x8bU, 0xd1U, 0x25U, 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, + 0x98U, 0x16U, 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, + 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, 0x5eU, 0x15U, + 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, 0x90U, 0xd8U, 0xabU, 0x00U, + 0x8cU, 0xbcU, 0xd3U, 0x0aU, 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, + 0x45U, 0x06U, 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, + 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, 0x3aU, 0x91U, + 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, 0x97U, 0xf2U, 0xcfU, 0xceU, + 0xf0U, 0xb4U, 0xe6U, 0x73U, 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, + 0x35U, 0x85U, 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, + 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, 0x6fU, 0xb7U, + 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, 0xfcU, 0x56U, 0x3eU, 0x4bU, + 0xc6U, 0xd2U, 0x79U, 0x20U, 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, + 0x5aU, 0xf4U, 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, + 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, 0x60U, 0x51U, + 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, 0x2dU, 0xe5U, 0x7aU, 0x9fU, + 0x93U, 0xc9U, 0x9cU, 0xefU, 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, + 0xf5U, 0xb0U, 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, + 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, 0xe1U, 0x69U, + 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, +}; + +static const uint32_t rcon[] = { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + // for 128-bit blocks, Rijndael never uses more than 10 rcon values +}; + +int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits, AES_KEY *aeskey) +{ + uint32_t *rk; + int i = 0; + uint32_t temp; + + if (!key || !aeskey) { + return -1; + } + + switch (bits) { + case 128: + aeskey->rounds = 10; + break; + case 192: + aeskey->rounds = 12; + break; + case 256: + aeskey->rounds = 14; + break; + default: + return -2; + } + + rk = aeskey->rd_key; + + rk[0] = GETU32(key); + rk[1] = GETU32(key + 4); + rk[2] = GETU32(key + 8); + rk[3] = GETU32(key + 12); + if (bits == 128) { + while (1) { + temp = rk[3]; + rk[4] = rk[0] ^ + (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ + (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ + (Te0[(temp)&0xff] & 0x0000ff00) ^ + (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; + rk[5] = rk[1] ^ rk[4]; + rk[6] = rk[2] ^ rk[5]; + rk[7] = rk[3] ^ rk[6]; + if (++i == 10) { + return 0; + } + rk += 4; + } + } + rk[4] = GETU32(key + 16); + rk[5] = GETU32(key + 20); + if (bits == 192) { + while (1) { + temp = rk[5]; + rk[6] = rk[0] ^ + (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ + (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ + (Te0[(temp)&0xff] & 0x0000ff00) ^ + (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; + rk[7] = rk[1] ^ rk[6]; + rk[8] = rk[2] ^ rk[7]; + rk[9] = rk[3] ^ rk[8]; + if (++i == 8) { + return 0; + } + rk[10] = rk[4] ^ rk[9]; + rk[11] = rk[5] ^ rk[10]; + rk += 6; + } + } + rk[6] = GETU32(key + 24); + rk[7] = GETU32(key + 28); + if (bits == 256) { + while (1) { + temp = rk[7]; + rk[8] = rk[0] ^ + (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ + (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ + (Te0[(temp)&0xff] & 0x0000ff00) ^ + (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; + rk[9] = rk[1] ^ rk[8]; + rk[10] = rk[2] ^ rk[9]; + rk[11] = rk[3] ^ rk[10]; + if (++i == 7) { + return 0; + } + temp = rk[11]; + rk[12] = rk[4] ^ (Te2[(temp >> 24)] & 0xff000000) ^ + (Te3[(temp >> 16) & 0xff] & 0x00ff0000) ^ + (Te0[(temp >> 8) & 0xff] & 0x0000ff00) ^ + (Te1[(temp)&0xff] & 0x000000ff); + rk[13] = rk[5] ^ rk[12]; + rk[14] = rk[6] ^ rk[13]; + rk[15] = rk[7] ^ rk[14]; + + rk += 8; + } + } + return 0; +} + +int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits, AES_KEY *aeskey) +{ + uint32_t *rk; + int i, j, status; + uint32_t temp; + + // first, start with an encryption schedule + status = AES_set_encrypt_key(key, bits, aeskey); + if (status < 0) { + return status; + } + + rk = aeskey->rd_key; + + // invert the order of the round keys: + for (i = 0, j = 4 * aeskey->rounds; i < j; i += 4, j -= 4) { + temp = rk[i]; + rk[i] = rk[j]; + rk[j] = temp; + temp = rk[i + 1]; + rk[i + 1] = rk[j + 1]; + rk[j + 1] = temp; + temp = rk[i + 2]; + rk[i + 2] = rk[j + 2]; + rk[j + 2] = temp; + temp = rk[i + 3]; + rk[i + 3] = rk[j + 3]; + rk[j + 3] = temp; + } + // apply the inverse MixColumn transform to all round keys but the first + // and the last: + for (i = 1; i < (int)aeskey->rounds; i++) { + rk += 4; + rk[0] = Td0[Te1[(rk[0] >> 24)] & 0xff] ^ + Td1[Te1[(rk[0] >> 16) & 0xff] & 0xff] ^ + Td2[Te1[(rk[0] >> 8) & 0xff] & 0xff] ^ + Td3[Te1[(rk[0]) & 0xff] & 0xff]; + rk[1] = Td0[Te1[(rk[1] >> 24)] & 0xff] ^ + Td1[Te1[(rk[1] >> 16) & 0xff] & 0xff] ^ + Td2[Te1[(rk[1] >> 8) & 0xff] & 0xff] ^ + Td3[Te1[(rk[1]) & 0xff] & 0xff]; + rk[2] = Td0[Te1[(rk[2] >> 24)] & 0xff] ^ + Td1[Te1[(rk[2] >> 16) & 0xff] & 0xff] ^ + Td2[Te1[(rk[2] >> 8) & 0xff] & 0xff] ^ + Td3[Te1[(rk[2]) & 0xff] & 0xff]; + rk[3] = Td0[Te1[(rk[3] >> 24)] & 0xff] ^ + Td1[Te1[(rk[3] >> 16) & 0xff] & 0xff] ^ + Td2[Te1[(rk[3] >> 8) & 0xff] & 0xff] ^ + Td3[Te1[(rk[3]) & 0xff] & 0xff]; + } + return 0; +} + +void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key) +{ + const uint32_t *rk; + uint32_t s0, s1, s2, s3, t0, t1, t2, t3; + int r; + + rk = key->rd_key; + + // map byte array block to cipher state + // and add initial round key: + s0 = GETU32(in) ^ rk[0]; + s1 = GETU32(in + 4) ^ rk[1]; + s2 = GETU32(in + 8) ^ rk[2]; + s3 = GETU32(in + 12) ^ rk[3]; + + // Nr - 1 full rounds: + r = key->rounds >> 1; + for (;;) { + t0 = Te0[(s0 >> 24)] ^ Te1[(s1 >> 16) & 0xff] ^ + Te2[(s2 >> 8) & 0xff] ^ Te3[(s3)&0xff] ^ rk[4]; + t1 = Te0[(s1 >> 24)] ^ Te1[(s2 >> 16) & 0xff] ^ + Te2[(s3 >> 8) & 0xff] ^ Te3[(s0)&0xff] ^ rk[5]; + t2 = Te0[(s2 >> 24)] ^ Te1[(s3 >> 16) & 0xff] ^ + Te2[(s0 >> 8) & 0xff] ^ Te3[(s1)&0xff] ^ rk[6]; + t3 = Te0[(s3 >> 24)] ^ Te1[(s0 >> 16) & 0xff] ^ + Te2[(s1 >> 8) & 0xff] ^ Te3[(s2)&0xff] ^ rk[7]; + + rk += 8; + if (--r == 0) { + break; + } + + s0 = Te0[(t0 >> 24)] ^ Te1[(t1 >> 16) & 0xff] ^ + Te2[(t2 >> 8) & 0xff] ^ Te3[(t3)&0xff] ^ rk[0]; + s1 = Te0[(t1 >> 24)] ^ Te1[(t2 >> 16) & 0xff] ^ + Te2[(t3 >> 8) & 0xff] ^ Te3[(t0)&0xff] ^ rk[1]; + s2 = Te0[(t2 >> 24)] ^ Te1[(t3 >> 16) & 0xff] ^ + Te2[(t0 >> 8) & 0xff] ^ Te3[(t1)&0xff] ^ rk[2]; + s3 = Te0[(t3 >> 24)] ^ Te1[(t0 >> 16) & 0xff] ^ + Te2[(t1 >> 8) & 0xff] ^ Te3[(t2)&0xff] ^ rk[3]; + } + + // apply last round and map cipher state to byte array block: + s0 = (Te2[(t0 >> 24)] & 0xff000000) ^ + (Te3[(t1 >> 16) & 0xff] & 0x00ff0000) ^ + (Te0[(t2 >> 8) & 0xff] & 0x0000ff00) ^ + (Te1[(t3)&0xff] & 0x000000ff) ^ rk[0]; + PUTU32(out, s0); + s1 = (Te2[(t1 >> 24)] & 0xff000000) ^ + (Te3[(t2 >> 16) & 0xff] & 0x00ff0000) ^ + (Te0[(t3 >> 8) & 0xff] & 0x0000ff00) ^ + (Te1[(t0)&0xff] & 0x000000ff) ^ rk[1]; + PUTU32(out + 4, s1); + s2 = (Te2[(t2 >> 24)] & 0xff000000) ^ + (Te3[(t3 >> 16) & 0xff] & 0x00ff0000) ^ + (Te0[(t0 >> 8) & 0xff] & 0x0000ff00) ^ + (Te1[(t1)&0xff] & 0x000000ff) ^ rk[2]; + PUTU32(out + 8, s2); + s3 = (Te2[(t3 >> 24)] & 0xff000000) ^ + (Te3[(t0 >> 16) & 0xff] & 0x00ff0000) ^ + (Te0[(t1 >> 8) & 0xff] & 0x0000ff00) ^ + (Te1[(t2)&0xff] & 0x000000ff) ^ rk[3]; + PUTU32(out + 12, s3); +} + +void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key) +{ + const uint32_t *rk; + uint32_t s0, s1, s2, s3, t0, t1, t2, t3; + int r; + + rk = key->rd_key; + + // map byte array block to cipher state + // and add initial round key: + s0 = GETU32(in) ^ rk[0]; + s1 = GETU32(in + 4) ^ rk[1]; + s2 = GETU32(in + 8) ^ rk[2]; + s3 = GETU32(in + 12) ^ rk[3]; + + // Nr - 1 full rounds: + r = key->rounds >> 1; + for (;;) { + t0 = Td0[(s0 >> 24)] ^ Td1[(s3 >> 16) & 0xff] ^ + Td2[(s2 >> 8) & 0xff] ^ Td3[(s1)&0xff] ^ rk[4]; + t1 = Td0[(s1 >> 24)] ^ Td1[(s0 >> 16) & 0xff] ^ + Td2[(s3 >> 8) & 0xff] ^ Td3[(s2)&0xff] ^ rk[5]; + t2 = Td0[(s2 >> 24)] ^ Td1[(s1 >> 16) & 0xff] ^ + Td2[(s0 >> 8) & 0xff] ^ Td3[(s3)&0xff] ^ rk[6]; + t3 = Td0[(s3 >> 24)] ^ Td1[(s2 >> 16) & 0xff] ^ + Td2[(s1 >> 8) & 0xff] ^ Td3[(s0)&0xff] ^ rk[7]; + + rk += 8; + if (--r == 0) { + break; + } + + s0 = Td0[(t0 >> 24)] ^ Td1[(t3 >> 16) & 0xff] ^ + Td2[(t2 >> 8) & 0xff] ^ Td3[(t1)&0xff] ^ rk[0]; + s1 = Td0[(t1 >> 24)] ^ Td1[(t0 >> 16) & 0xff] ^ + Td2[(t3 >> 8) & 0xff] ^ Td3[(t2)&0xff] ^ rk[1]; + s2 = Td0[(t2 >> 24)] ^ Td1[(t1 >> 16) & 0xff] ^ + Td2[(t0 >> 8) & 0xff] ^ Td3[(t3)&0xff] ^ rk[2]; + s3 = Td0[(t3 >> 24)] ^ Td1[(t2 >> 16) & 0xff] ^ + Td2[(t1 >> 8) & 0xff] ^ Td3[(t0)&0xff] ^ rk[3]; + } + + // apply last round and + // map cipher state to byte array block: + s0 = ((uint32_t)Td4[(t0 >> 24)] << 24) ^ + ((uint32_t)Td4[(t3 >> 16) & 0xff] << 16) ^ + ((uint32_t)Td4[(t2 >> 8) & 0xff] << 8) ^ + ((uint32_t)Td4[(t1)&0xff]) ^ rk[0]; + PUTU32(out, s0); + s1 = ((uint32_t)Td4[(t1 >> 24)] << 24) ^ + ((uint32_t)Td4[(t0 >> 16) & 0xff] << 16) ^ + ((uint32_t)Td4[(t3 >> 8) & 0xff] << 8) ^ + ((uint32_t)Td4[(t2)&0xff]) ^ rk[1]; + PUTU32(out + 4, s1); + s2 = ((uint32_t)Td4[(t2 >> 24)] << 24) ^ + ((uint32_t)Td4[(t1 >> 16) & 0xff] << 16) ^ + ((uint32_t)Td4[(t0 >> 8) & 0xff] << 8) ^ + ((uint32_t)Td4[(t3)&0xff]) ^ rk[2]; + PUTU32(out + 8, s2); + s3 = ((uint32_t)Td4[(t3 >> 24)] << 24) ^ + ((uint32_t)Td4[(t2 >> 16) & 0xff] << 16) ^ + ((uint32_t)Td4[(t1 >> 8) & 0xff] << 8) ^ + ((uint32_t)Td4[(t0)&0xff]) ^ rk[3]; + PUTU32(out + 12, s3); +} -- cgit v1.2.1 From e7cf17a0c150f64e2a92b1c30c26247ced8da1c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:37 -0600 Subject: board/kano/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb5c97591fc00d0ff030f53bbdd69b8613eaf4ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728478 Reviewed-by: Jeremy Bettis --- board/kano/board.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/board/kano/board.c b/board/kano/board.c index 7ed766698c..d59a1d03da 100644 --- a/board/kano/board.c +++ b/board/kano/board.c @@ -27,8 +27,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -80,8 +80,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -108,15 +108,14 @@ enum battery_present battery_hw_present(void) * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From ce1db09f42b60b176185446a3756e0abfa089577 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:50 -0600 Subject: driver/accelgyro_icm_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I911d672bfc6206c271067677703f0373bc3bd6d6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729920 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm_common.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/driver/accelgyro_icm_common.h b/driver/accelgyro_icm_common.h index c6e6ce2ff2..89586a482f 100644 --- a/driver/accelgyro_icm_common.h +++ b/driver/accelgyro_icm_common.h @@ -20,9 +20,9 @@ #ifdef CONFIG_ACCEL_FIFO /* reserve maximum 4 samples of 16 bytes */ -#define ICM_FIFO_BUFFER 64 +#define ICM_FIFO_BUFFER 64 #else -#define ICM_FIFO_BUFFER 0 +#define ICM_FIFO_BUFFER 0 #endif struct icm_drv_data_t { @@ -35,21 +35,19 @@ struct icm_drv_data_t { uint8_t fifo_buffer[ICM_FIFO_BUFFER] __aligned(sizeof(long)); }; -#define ICM_GET_DATA(_s) \ - ((struct icm_drv_data_t *)(_s)->drv_data) -#define ICM_GET_SAVED_DATA(_s) \ - (&ICM_GET_DATA(_s)->saved_data[(_s)->type]) +#define ICM_GET_DATA(_s) ((struct icm_drv_data_t *)(_s)->drv_data) +#define ICM_GET_SAVED_DATA(_s) (&ICM_GET_DATA(_s)->saved_data[(_s)->type]) /* * Virtual register address is 16 bits: * - 8 bits MSB coding bank number * - 8 bits LSB coding physical address */ -#define ICM426XX_REG_GET_BANK(_r) (((_r) & 0xFF00) >> 8) -#define ICM426XX_REG_GET_ADDR(_r) ((_r) & 0x00FF) +#define ICM426XX_REG_GET_BANK(_r) (((_r)&0xFF00) >> 8) +#define ICM426XX_REG_GET_ADDR(_r) ((_r)&0x00FF) /* Sensor resolution in number of bits */ -#define ICM_RESOLUTION 16 +#define ICM_RESOLUTION 16 /** * sign_extend - sign extend a standard int value using the given sign-bit @@ -105,7 +103,7 @@ int icm_get_scale(const struct motion_sensor_t *s, uint16_t *scale, int16_t *temp); ssize_t icm_fifo_decode_packet(const void *packet, const uint8_t **accel, - const uint8_t **gyro); + const uint8_t **gyro); static inline void icm_set_stabilize_ts(const struct motion_sensor_t *s, uint32_t delay) @@ -125,9 +123,8 @@ static inline void icm_reset_stabilize_ts(const struct motion_sensor_t *s) st->stabilize_ts[s->type] = 0; } -static inline -int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s, - uint32_t ts) +static inline int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s, + uint32_t ts) { struct icm_drv_data_t *st = ICM_GET_DATA(s); uint32_t stabilize_ts = st->stabilize_ts[s->type]; @@ -138,4 +135,4 @@ int32_t icm_get_sensor_stabilized(const struct motion_sensor_t *s, return time_until(ts, stabilize_ts); } -#endif /* __CROS_EC_ACCELGYRO_ICM_COMMON_H */ +#endif /* __CROS_EC_ACCELGYRO_ICM_COMMON_H */ -- cgit v1.2.1 From 1acc3abcb7a801e82b5d8cd909b387462f265d36 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:33 -0600 Subject: board/reef/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3ba605baaf7e1b65900aff9c3a0e693af70840c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728866 Reviewed-by: Jeremy Bettis --- board/reef/usb_pd_policy.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/board/reef/usb_pd_policy.c b/board/reef/usb_pd_policy.c index 2d2ef416b2..dbc7aa96d1 100644 --- a/board/reef/usb_pd_policy.c +++ b/board/reef/usb_pd_policy.c @@ -23,12 +23,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port) { enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); /* * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance -- cgit v1.2.1 From 94f6bbdbf79d397cb9dd806f56d8cd55d3a9951d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:44 -0600 Subject: include/hooks.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2bc43cfc647a262352dd7e276e4346e6eee62ec6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730279 Reviewed-by: Jeremy Bettis --- include/hooks.h | 44 +++++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/include/hooks.h b/include/hooks.h index ae450085d7..6ff72bebf2 100644 --- a/include/hooks.h +++ b/include/hooks.h @@ -12,12 +12,12 @@ enum hook_priority { /* Generic values across all hooks */ - HOOK_PRIO_FIRST = 1, /* Highest priority */ + HOOK_PRIO_FIRST = 1, /* Highest priority */ HOOK_PRIO_POST_FIRST = HOOK_PRIO_FIRST + 1, - HOOK_PRIO_DEFAULT = 5000, /* Default priority */ + HOOK_PRIO_DEFAULT = 5000, /* Default priority */ HOOK_PRIO_PRE_DEFAULT = HOOK_PRIO_DEFAULT - 1, HOOK_PRIO_POST_DEFAULT = HOOK_PRIO_DEFAULT + 1, - HOOK_PRIO_LAST = 9999, /* Lowest priority */ + HOOK_PRIO_LAST = 9999, /* Lowest priority */ /* Specific hook vales for HOOK_INIT */ /* DMA inits before ADC, I2C, SPI */ @@ -266,7 +266,7 @@ enum hook_type { HOOK_TEST_1, HOOK_TEST_2, HOOK_TEST_3, -#endif /* TEST_BUILD */ +#endif /* TEST_BUILD */ /* * Not a hook type (instead the number of hooks). This should @@ -351,11 +351,12 @@ int hook_call_deferred(const struct deferred_data *data, int us); * unless there's a compelling reason to care about the * order in which hooks are called. */ -#define DECLARE_HOOK(hooktype, routine, priority) \ - const struct hook_data __keep __no_sanitize_address \ - CONCAT4(__hook_, hooktype, _, routine) \ - __attribute__((section(".rodata." STRINGIFY(hooktype)))) \ - = {routine, priority} +#define DECLARE_HOOK(hooktype, routine, priority) \ + const struct hook_data __keep __no_sanitize_address CONCAT4( \ + __hook_, hooktype, _, routine) \ + __attribute__((section(".rodata." STRINGIFY(hooktype)))) = { \ + routine, priority \ + } /** * Register a deferred function call. @@ -376,21 +377,26 @@ int hook_call_deferred(const struct deferred_data *data, int us); * * @param routine Function pointer, with prototype void routine(void) */ -#define DECLARE_DEFERRED(routine) \ - const struct deferred_data __keep __no_sanitize_address \ - CONCAT2(routine, _data) \ - __attribute__((section(".rodata.deferred"))) \ - = {routine} +#define DECLARE_DEFERRED(routine) \ + const struct deferred_data __keep __no_sanitize_address CONCAT2( \ + routine, _data) \ + __attribute__((section(".rodata.deferred"))) = { routine } #else /* * Stub implementation in case hooks are disabled (neither * CONFIG_COMMON_RUNTIME nor CONFIG_PLATFORM_EC_HOOKS is defined) */ #define hook_call_deferred(unused1, unused2) -1 -#define DECLARE_HOOK(t, func, p) \ - void CONCAT2(unused_hook_, func)(void) { func(); } -#define DECLARE_DEFERRED(func) \ - void CONCAT2(unused_deferred_, func)(void) { func(); } +#define DECLARE_HOOK(t, func, p) \ + void CONCAT2(unused_hook_, func)(void) \ + { \ + func(); \ + } +#define DECLARE_DEFERRED(func) \ + void CONCAT2(unused_deferred_, func)(void) \ + { \ + func(); \ + } #endif -#endif /* __CROS_EC_HOOKS_H */ +#endif /* __CROS_EC_HOOKS_H */ -- cgit v1.2.1 From a2e74ca7a1469771dcd43d8bc12598c164d15371 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:20 -0600 Subject: chip/it83xx/irq.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f0c25c9fe77b9887b57b8e637f7eb5fcce9aeae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729213 Reviewed-by: Jeremy Bettis --- chip/it83xx/irq.c | 81 ++++++++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index fb01309721..0ba31c6d0c 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -10,56 +10,59 @@ #include "registers.h" #include "util.h" -#define IRQ_GROUP(n, cpu_ints...) \ - {(uint32_t)&CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \ - (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - IT83XX_INTC_BASE, \ - ##cpu_ints} +#define IRQ_GROUP(n, cpu_ints...) \ + { \ + (uint32_t) & CONCAT2(IT83XX_INTC_ISR, n) - IT83XX_INTC_BASE, \ + (uint32_t)&CONCAT2(IT83XX_INTC_IER, n) - \ + IT83XX_INTC_BASE, \ + ##cpu_ints \ + } static const struct { uint8_t isr_off; uint8_t ier_off; uint8_t cpu_int[8]; } irq_groups[] = { - IRQ_GROUP(0, {-1, 2, 5, 4, 6, 2, 2, 4}), - IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8}), - IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12}), - IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2}), - IRQ_GROUP(4, {11, 11, 11, 11, 8, 9, 9, 9}), - IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(7, {10, 10, 3, 12, 3, 3, 3, 3}), - IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12}), - IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2}), - IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7}), - IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3}), - IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}), + IRQ_GROUP(0, { -1, 2, 5, 4, 6, 2, 2, 4 }), + IRQ_GROUP(1, { 7, 6, 6, 5, 2, 2, 2, 8 }), + IRQ_GROUP(2, { 6, 2, 8, 8, 8, 2, 12, 12 }), + IRQ_GROUP(3, { 5, 4, 4, 4, 11, 11, 3, 2 }), + IRQ_GROUP(4, { 11, 11, 11, 11, 8, 9, 9, 9 }), + IRQ_GROUP(5, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(6, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(7, { 10, 10, 3, 12, 3, 3, 3, 3 }), + IRQ_GROUP(8, { 4, 4, 4, 4, 4, 4, -1, 12 }), + IRQ_GROUP(9, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(10, { 3, 6, 12, 12, 5, 2, 2, 2 }), + IRQ_GROUP(11, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(12, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(13, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(14, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(15, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(16, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(17, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(18, { 2, 2, 2, 2, -1, 4, 4, 7 }), + IRQ_GROUP(19, { 6, 6, 12, 3, 3, 3, 3, 3 }), + IRQ_GROUP(20, { 12, 12, 12, 12, 12, 12, 12, -1 }), #if defined(IT83XX_INTC_GROUP_21_22_SUPPORT) - IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2}), - IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1}), + IRQ_GROUP(21, { 2, 2, 2, 2, 2, 2, 2, 2 }), + IRQ_GROUP(22, { 2, 2, -1, -1, -1, -1, -1, -1 }), #elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}), - IRQ_GROUP(22, { 2, 2, 2, 2, 2, 2, 2, 2}), + IRQ_GROUP(21, { -1, -1, 12, 12, 12, 12, 12, 12 }), + IRQ_GROUP(22, { 2, 2, 2, 2, 2, 2, 2, 2 }), #else - IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}), - IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}), + IRQ_GROUP(21, { -1, -1, -1, -1, -1, -1, -1, -1 }), + IRQ_GROUP(22, { -1, -1, -1, -1, -1, -1, -1, -1 }), #endif - IRQ_GROUP(23, { 2, 2, -1, -1, -1, -1, -1, 2}), - IRQ_GROUP(24, { 2, 2, 2, 2, 2, 2, -1, 2}), - IRQ_GROUP(25, { 2, 2, 2, 2, -1, -1, -1, -1}), - IRQ_GROUP(26, { 2, 2, 2, 2, 2, 2, 2, -1}), - IRQ_GROUP(27, { 2, 2, 2, 2, 2, 2, -1, -1}), - IRQ_GROUP(28, { 2, 2, 2, 2, 2, 2, -1, -1}), + IRQ_GROUP(23, { 2, 2, -1, -1, -1, -1, -1, 2 }), + IRQ_GROUP(24, { 2, 2, 2, 2, 2, 2, -1, 2 }), + IRQ_GROUP(25, { 2, 2, 2, 2, -1, -1, -1, -1 }), + IRQ_GROUP(26, { 2, 2, 2, 2, 2, 2, 2, -1 }), + IRQ_GROUP(27, { 2, 2, 2, 2, 2, 2, -1, -1 }), + IRQ_GROUP(28, { 2, 2, 2, 2, 2, 2, -1, -1 }), }; -#if defined(CHIP_FAMILY_IT8320) /* N8 core */ +#if defined(CHIP_FAMILY_IT8320) /* N8 core */ /* Number of CPU hardware interrupts (HW0 ~ HW15) */ int cpu_int_entry_number; #endif @@ -68,7 +71,7 @@ int chip_get_ec_int(void) { extern volatile int ec_int; -#if defined(CHIP_FAMILY_IT8320) /* N8 core */ +#if defined(CHIP_FAMILY_IT8320) /* N8 core */ int i; for (i = 0; i < IT83XX_IRQ_COUNT; i++) { -- cgit v1.2.1 From ceaf71986a9eb31d2f17d2994ac73a7529645fd6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:20 -0600 Subject: include/usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I785d57d1c3928e64cff928c0d429fefeba1465f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730437 Reviewed-by: Jeremy Bettis --- include/usb_mux.h | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/include/usb_mux.h b/include/usb_mux.h index 0d43257994..1d345b0b8f 100644 --- a/include/usb_mux.h +++ b/include/usb_mux.h @@ -157,8 +157,7 @@ struct usb_mux { * @param[out] ack_required: indication of whether this function * requires a wait for an AP ACK after */ - void (*hpd_update)(const struct usb_mux *me, - mux_state_t mux_state, + void (*hpd_update)(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); }; @@ -193,30 +192,30 @@ void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state, #ifdef CONFIG_USB_PD_TCPM_MUX static inline int mux_write(const struct usb_mux *me, int reg, int val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_write(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_write(me->usb_port, reg, val); } static inline int mux_read(const struct usb_mux *me, int reg, int *val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_read(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_read(me->usb_port, reg, val); } static inline int mux_write16(const struct usb_mux *me, int reg, int val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_write16(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_write16(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_write16(me->usb_port, reg, val); } static inline int mux_read16(const struct usb_mux *me, int reg, int *val) { - return me->flags & USB_MUX_FLAG_NOT_TCPC - ? i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) - : tcpc_read16(me->usb_port, reg, val); + return me->flags & USB_MUX_FLAG_NOT_TCPC ? + i2c_read16(me->i2c_port, me->i2c_addr_flags, reg, val) : + tcpc_read16(me->usb_port, reg, val); } #endif /* CONFIG_USB_PD_TCPM_MUX */ @@ -235,8 +234,8 @@ void usb_mux_init(int port); * @param usb_config usb2.0 selected function. * @param polarity plug polarity (0=CC1, 1=CC2). */ -void usb_mux_set(int port, mux_state_t mux_mode, - enum usb_switch usb_config, int polarity); +void usb_mux_set(int port, mux_state_t mux_mode, enum usb_switch usb_config, + int polarity); /** * Configure superspeed muxes on type-C port for only one index in the mux -- cgit v1.2.1 From 4bef93290480bec06ebde8a73c74592eaf1cd361 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:03 -0600 Subject: board/nocturne/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia73f7602e8e1d07ca4c3fb9a297995e0f7a181bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728757 Reviewed-by: Jeremy Bettis --- board/nocturne/battery.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/nocturne/battery.c b/board/nocturne/battery.c index 0e568ca6f9..9603243347 100644 --- a/board/nocturne/battery.c +++ b/board/nocturne/battery.c @@ -21,26 +21,26 @@ #include "usb_pd.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHUTDOWN_DATA 0x0010 /* * We need to stop charging the battery when the DRAM temperature sensor gets * over 47 C (320 K), and resume charging once it cools back down. */ -#define DRAM_STOPCHARGE_TEMP_K 320 +#define DRAM_STOPCHARGE_TEMP_K 320 /* Battery info */ static const struct battery_info info = { - .voltage_max = 8880, - .voltage_normal = 7700, - .voltage_min = 6000, - .precharge_current = 160, - .start_charging_min_c = 10, - .start_charging_max_c = 50, - .charging_min_c = 10, - .charging_max_c = 50, - .discharging_min_c = -20, - .discharging_max_c = 60, + .voltage_max = 8880, + .voltage_normal = 7700, + .voltage_min = 6000, + .precharge_current = 160, + .start_charging_min_c = 10, + .start_charging_max_c = 50, + .charging_min_c = 10, + .charging_max_c = 50, + .discharging_min_c = -20, + .discharging_max_c = 60, }; int board_cut_off_battery(void) @@ -78,8 +78,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void) return BATTERY_NOT_DISCONNECTED; /* Check if battery discharge FET is disabled. */ - rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return BATTERY_DISCONNECT_ERROR; if (~data[3] & (BATTERY_DISCHARGING_DISABLED)) { @@ -91,8 +91,8 @@ enum battery_disconnect_state battery_get_disconnect_state(void) * Battery discharge FET is disabled. Verify that we didn't enter this * state due to a safety fault. */ - rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_SAFETY_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv || data[2] || data[3] || data[4] || data[5]) return BATTERY_DISCONNECT_ERROR; -- cgit v1.2.1 From b48dbba9c53a557f7032ae96d3f7a44eba58621f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:32 -0600 Subject: baseboard/mtscp-rv32i/venc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ed06d1beceefd3a081c799136d77470d3a275db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727932 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/venc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/mtscp-rv32i/venc.h b/baseboard/mtscp-rv32i/venc.h index 47454c4507..673e91da68 100644 --- a/baseboard/mtscp-rv32i/venc.h +++ b/baseboard/mtscp-rv32i/venc.h @@ -18,7 +18,7 @@ struct venc_msg { unsigned char msg[288]; }; BUILD_ASSERT(member_size(struct venc_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void venc_h264_msg_handler(void *data); -- cgit v1.2.1 From 6bea672315958097e7ee413d050848790106f6fd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:38 -0600 Subject: board/pazquel/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1719368b542ea15f1222e0e011d7abcfe3a246df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728815 Reviewed-by: Jeremy Bettis --- board/pazquel/led.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/pazquel/led.c b/board/pazquel/led.c index aabf33f3f0..addea27afa 100644 --- a/board/pazquel/led.c +++ b/board/pazquel/led.c @@ -31,15 +31,15 @@ enum led_color { LED_OFF = 0, LED_RED, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C1, - (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_W_C1, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From dee9179ac54e4ae6fa877c03091809a003b8936d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:39 -0600 Subject: common/charge_ramp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic2594979f93d83954f9a725277e004124d1eb94c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729615 Reviewed-by: Jeremy Bettis --- common/charge_ramp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/charge_ramp.c b/common/charge_ramp.c index 32e0d21ddb..2db9dbb2f5 100644 --- a/common/charge_ramp.c +++ b/common/charge_ramp.c @@ -41,7 +41,7 @@ test_mockable int chg_ramp_allowed(int port, int supplier) case CHARGE_SUPPLIER_PD: case CHARGE_SUPPLIER_TYPEC: return 0; - /* default: fall through */ + /* default: fall through */ } /* Otherwise ask the BC1.2 detect module */ @@ -59,7 +59,7 @@ test_mockable int chg_ramp_max(int port, int supplier, int sup_curr) * we may brownout the systems they are connected to. */ return sup_curr; - /* default: fall through */ + /* default: fall through */ } /* Otherwise ask the BC1.2 detect module */ -- cgit v1.2.1 From 9d6b64d476e4fded4423b41838fbe1c30891f2d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:02 -0600 Subject: zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib1ea3e96c3dcb1e85271e8b94f4aded220135e8b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730672 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c index 31dcfdd29d..75e7a42634 100644 --- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c +++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_xec.c @@ -103,7 +103,7 @@ static int cros_kb_raw_xec_drive_column(const struct device *dev, int col) /* Drive all lines to low for detection any key press */ else if (col == KEYBOARD_COLUMN_ALL) { mchp_soc_ecia_girq_src_dis(MCHP_GIRQ21_ID, - MCHP_KEYSCAN_GIRQ_POS); + MCHP_KEYSCAN_GIRQ_POS); inst->KSO_SEL = MCHP_KSCAN_KSO_ALL; /* Set logical level low on COL2 */ cros_kb_raw_set_col2(0); @@ -122,7 +122,7 @@ static int cros_kb_raw_xec_drive_column(const struct device *dev, int col) kb_raw_xec_clr_src(dev); } mchp_soc_ecia_girq_src_en(MCHP_GIRQ21_ID, - MCHP_KEYSCAN_GIRQ_POS); + MCHP_KEYSCAN_GIRQ_POS); } /* Drive one line to low for determining * which key's state changed. @@ -164,7 +164,7 @@ static int cros_kb_raw_xec_init(const struct device *dev) /* Set up Kscan IRQ and ISR */ IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), - cros_kb_raw_xec_ksi_isr, DEVICE_DT_INST_GET(0), 0); + cros_kb_raw_xec_ksi_isr, DEVICE_DT_INST_GET(0), 0); /* Disable Kscan NVIC and source interrupts */ irq_disable(cfg->irq); -- cgit v1.2.1 From 084c0a9fb05323daa299581131d4f409c588fa23 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:02 -0600 Subject: common/battery_v2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifff62f01aab8933b603e76e71f57503d65cdc296 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729591 Reviewed-by: Jeremy Bettis --- common/battery_v2.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/common/battery_v2.c b/common/battery_v2.c index 27ae0285ac..1ed7205b65 100644 --- a/common/battery_v2.c +++ b/common/battery_v2.c @@ -15,8 +15,8 @@ #include "printf.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* * Store battery information in these 2 structures. Main (lid) battery is always @@ -135,8 +135,7 @@ host_command_battery_get_static(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC, - host_command_battery_get_static, +DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_STATIC, host_command_battery_get_static, EC_VER_MASK(0) | EC_VER_MASK(1)); static enum ec_status @@ -154,8 +153,7 @@ host_command_battery_get_dynamic(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_BATTERY_GET_DYNAMIC, - host_command_battery_get_dynamic, - EC_VER_MASK(0)); + host_command_battery_get_dynamic, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_BATTERY_V2 */ void battery_memmap_refresh(enum battery_index index) @@ -222,8 +220,8 @@ int update_static_battery_info(void) /* Smart battery serial number is 16 bits */ rv = battery_serial_number(&batt_serial); if (!rv) - snprintf(bs->serial_ext, sizeof(bs->serial_ext), - "%04X", batt_serial); + snprintf(bs->serial_ext, sizeof(bs->serial_ext), "%04X", + batt_serial); /* Design Capacity of Full */ ret = battery_design_capacity(&val); @@ -344,17 +342,17 @@ void update_dynamic_battery_info(void) * to Chrome OS powerd. */ if (curr->batt.remaining_capacity == 0 && - !curr->batt_is_charging) + !curr->batt_is_charging) bd->remaining_capacity = 1; else bd->remaining_capacity = curr->batt.remaining_capacity; } if (!(curr->batt.flags & BATT_FLAG_BAD_FULL_CAPACITY) && - (curr->batt.full_capacity <= - (bd->full_capacity - LFCC_EVENT_THRESH) || - curr->batt.full_capacity >= - (bd->full_capacity + LFCC_EVENT_THRESH))) { + (curr->batt.full_capacity <= + (bd->full_capacity - LFCC_EVENT_THRESH) || + curr->batt.full_capacity >= + (bd->full_capacity + LFCC_EVENT_THRESH))) { bd->full_capacity = curr->batt.full_capacity; /* Poke the AP if the full_capacity changes. */ send_batt_info_event++; @@ -366,7 +364,7 @@ void update_dynamic_battery_info(void) tmp |= EC_BATT_FLAG_LEVEL_CRITICAL; tmp |= curr->batt_is_charging ? EC_BATT_FLAG_CHARGING : - EC_BATT_FLAG_DISCHARGING; + EC_BATT_FLAG_DISCHARGING; /* Tell the AP to re-read battery status if charge state changes */ if (bd->flags != tmp) -- cgit v1.2.1 From d0e98252a380c5e9997c1ddd39a90c9afe652ef3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:51 -0600 Subject: include/spi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68d38c92f96c9856f49f3aefec66097bd8e24cb0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730407 Reviewed-by: Jeremy Bettis --- include/spi.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/spi.h b/include/spi.h index 28fc166f73..b5ad375f59 100644 --- a/include/spi.h +++ b/include/spi.h @@ -89,8 +89,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable); * @param rxlen number of bytes in rxdata or SPI_READBACK_ALL. */ int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); /* * Similar to spi_transaction(), but hands over to DMA for reading response. @@ -100,8 +100,8 @@ int spi_transaction(const struct spi_device_t *spi_device, * SPI port, it's up to the caller to ensure proper mutual exclusion if needed. */ int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); /* Wait for async response received */ int spi_transaction_flush(const struct spi_device_t *spi_device); @@ -131,4 +131,4 @@ static inline void spi_event(enum gpio_signal signal) #endif -#endif /* __CROS_EC_SPI_H */ +#endif /* __CROS_EC_SPI_H */ -- cgit v1.2.1 From d957ad57d4c70e4ece5d44f82de23ed2767ec310 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:12 -0600 Subject: board/felwinter/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b46accb62a163af4aa88e58233505da5ae8419a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728357 Reviewed-by: Jeremy Bettis --- board/felwinter/fw_config.h | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/board/felwinter/fw_config.h b/board/felwinter/fw_config.h index 5f5f956b61..10e9b69536 100644 --- a/board/felwinter/fw_config.h +++ b/board/felwinter/fw_config.h @@ -14,37 +14,28 @@ * Source of truth is the project/brya/felwinter/config.star configuration file. */ -enum ec_cfg_usb_db_type { - DB_USB3_PS8815 = 1, - DB_USB4_NCT3807 = 2 -}; +enum ec_cfg_usb_db_type { DB_USB3_PS8815 = 1, DB_USB4_NCT3807 = 2 }; enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_usb_mb_type { - MB_USB4_TBT = 0, - MB_USB3_NON_TBT = 1 -}; +enum ec_cfg_usb_mb_type { MB_USB4_TBT = 0, MB_USB3_NON_TBT = 1 }; -enum ec_cfg_stylus_type { - STYLUS_ABSENT = 0, - STYLUS_PRSENT = 1 -}; +enum ec_cfg_stylus_type { STYLUS_ABSENT = 0, STYLUS_PRSENT = 1 }; union brya_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 3; - uint32_t wifi : 2; - enum ec_cfg_stylus_type stylus : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t thermal : 2; - uint32_t table_mode : 1; - enum ec_cfg_usb_mb_type usb_mb : 3; - uint32_t reserved_1 : 16; + enum ec_cfg_usb_db_type usb_db : 3; + uint32_t wifi : 2; + enum ec_cfg_stylus_type stylus : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t thermal : 2; + uint32_t table_mode : 1; + enum ec_cfg_usb_mb_type usb_mb : 3; + uint32_t reserved_1 : 16; }; uint32_t raw_value; }; -- cgit v1.2.1 From 2bff04d25974f620c23a4c0f1b54d931f645013b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:36 -0600 Subject: core/nds32/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I782502292b73a768be492e2992aae5c7f0692017 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729865 Reviewed-by: Jeremy Bettis --- core/nds32/panic.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/core/nds32/panic.c b/core/nds32/panic.c index 70e2cae3e0..ea3022e0d0 100644 --- a/core/nds32/panic.c +++ b/core/nds32/panic.c @@ -17,7 +17,7 @@ /* General purpose register (r6) for saving software panic reason */ #define SOFT_PANIC_GPR_REASON 6 /* General purpose register (r7) for saving software panic information */ -#define SOFT_PANIC_GPR_INFO 7 +#define SOFT_PANIC_GPR_INFO 7 #ifdef CONFIG_DEBUG_EXCEPTIONS /** @@ -46,7 +46,7 @@ * All other exceptions not in the abovetable should have the INST field of * the ITYPE register set to 0. */ -static const char * const itype_inst[2] = { +static const char *const itype_inst[2] = { "a data memory access", "an instruction fetch access", }; @@ -54,7 +54,7 @@ static const char * const itype_inst[2] = { /** * bit[3-0] @ ITYPE, general exception type information. */ -static const char * const itype_exc_type[16] = { +static const char *const itype_exc_type[16] = { "Alignment check", "Reserved instruction", "Trap", @@ -78,8 +78,8 @@ static const char * const itype_exc_type[16] = { #ifdef CONFIG_SOFTWARE_PANIC void software_panic(uint32_t reason, uint32_t info) { - asm volatile ("mov55 $r6, %0" : : "r"(reason)); - asm volatile ("mov55 $r7, %0" : : "r"(info)); + asm volatile("mov55 $r6, %0" : : "r"(reason)); + asm volatile("mov55 $r7, %0" : : "r"(info)); if (in_interrupt_context()) asm("j excep_handler"); else @@ -94,7 +94,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) * If it was called earlier (eg. when saving nds_n8.ipc) calling it * once again won't remove any data */ - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t warning_ipc; uint32_t *regs; @@ -121,7 +121,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *regs; if (pdata && pdata->struct_version == 2) { @@ -136,17 +136,17 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) #endif /* CONFIG_SOFTWARE_PANIC */ static void print_panic_information(uint32_t *regs, uint32_t itype, - uint32_t ipc, uint32_t ipsw) + uint32_t ipc, uint32_t ipsw) { panic_printf("=== EXCEP: ITYPE=%x ===\n", itype); - panic_printf("R0 %08x R1 %08x R2 %08x R3 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - panic_printf("R4 %08x R5 %08x R6 %08x R7 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - panic_printf("R8 %08x R9 %08x R10 %08x R15 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - panic_printf("FP %08x GP %08x LP %08x SP %08x\n", - regs[12], regs[13], regs[14], regs[15]); + panic_printf("R0 %08x R1 %08x R2 %08x R3 %08x\n", regs[0], regs[1], + regs[2], regs[3]); + panic_printf("R4 %08x R5 %08x R6 %08x R7 %08x\n", regs[4], regs[5], + regs[6], regs[7]); + panic_printf("R8 %08x R9 %08x R10 %08x R15 %08x\n", regs[8], regs[9], + regs[10], regs[11]); + panic_printf("FP %08x GP %08x LP %08x SP %08x\n", regs[12], + regs[13], regs[14], regs[15]); panic_printf("IPC %08x IPSW %05x\n", ipc, ipsw); if ((ipsw & PSW_INTL_MASK) == (2 << PSW_INTL_SHIFT)) { /* 2nd level exception */ @@ -161,16 +161,16 @@ static void print_panic_information(uint32_t *regs, uint32_t itype, if (panic_sw_reason_is_valid(regs[SOFT_PANIC_GPR_REASON])) { #ifdef CONFIG_SOFTWARE_PANIC panic_printf("Software panic reason %s\n", - panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - - PANIC_SW_BASE)]); + panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - + PANIC_SW_BASE)]); panic_printf("Software panic info 0x%x\n", - regs[SOFT_PANIC_GPR_INFO]); + regs[SOFT_PANIC_GPR_INFO]); #endif } else { panic_printf("Exception type: General exception [%s]\n", - itype_exc_type[(itype & 0xf)]); + itype_exc_type[(itype & 0xf)]); panic_printf("Exception is caused by %s\n", - itype_inst[(itype & BIT(4))]); + itype_inst[(itype & BIT(4))]); } #endif } @@ -178,7 +178,7 @@ static void print_panic_information(uint32_t *regs, uint32_t itype, void report_panic(uint32_t *regs, uint32_t itype) { int i; - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); pdata->magic = PANIC_DATA_MAGIC; pdata->struct_size = CONFIG_PANIC_DATA_SIZE; -- cgit v1.2.1 From 4b1c2bd29837b900188a46d761a4e485cc0f7165 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:57 -0600 Subject: chip/npcx/system-npcx5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23a3560a6c62c30f3c5344df25eb3655bf53e4d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729439 Reviewed-by: Jeremy Bettis --- chip/npcx/system-npcx5.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/chip/npcx/system-npcx5.c b/chip/npcx/system-npcx5.c index 4dd12fbae2..2fffacd055 100644 --- a/chip/npcx/system-npcx5.c +++ b/chip/npcx/system-npcx5.c @@ -39,9 +39,9 @@ void system_mpu_config(void) CPU_MPU_CTRL = 0x7; /* Create a new MPU Region to allow execution from low-power ram */ - CPU_MPU_RNR = REGION_CHIP_RESERVED; + CPU_MPU_RNR = REGION_CHIP_RESERVED; CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ + CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ /* * Set region size & attribute and enable region * [31:29] - Reserved. @@ -61,7 +61,7 @@ void system_mpu_config(void) /** * hibernate function in low power ram for npcx5 series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram"))) +noreturn void __keep __attribute__((section(".lowpower_ram"))) __enter_hibernate_in_lpram(void) { /* @@ -69,10 +69,8 @@ __enter_hibernate_in_lpram(void) * Our bypass needs stack instructions but FW will turn off main ram * later for better power consumption. */ - asm ( - "ldr r0, =0x40001800\n" - "mov sp, r0\n" - ); + asm("ldr r0, =0x40001800\n" + "mov sp, r0\n"); /* Disable Code RAM first */ SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS); @@ -88,13 +86,12 @@ __enter_hibernate_in_lpram(void) * wake-up from deep idle. * Workaround: Apply the same bypass of idle but don't enable interrupt. */ - asm ( - "push {r0-r5}\n" /* Save needed registers */ - "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */ - "wfi\n" /* Wait for int to enter idle */ - "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ - "pop {r0-r5}\n" /* Restore regs before enabling ints */ - "isb\n" /* Flush the cpu pipeline */ + asm("push {r0-r5}\n" /* Save needed registers */ + "ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */ + "wfi\n" /* Wait for int to enter idle */ + "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ + "pop {r0-r5}\n" /* Restore regs before enabling ints */ + "isb\n" /* Flush the cpu pipeline */ ); /* RTC wake-up */ @@ -129,7 +126,7 @@ void __hibernate_npcx_series(void) { int i; void (*__hibernate_in_lpram)(void) = - (void(*)(void))(__lpram_fw_start | 0x01); + (void (*)(void))(__lpram_fw_start | 0x01); /* Enable power for the Low Power RAM */ CLEAR_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6), 6); @@ -140,7 +137,7 @@ void __hibernate_npcx_series(void) /* Copy the __enter_hibernate_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lpfw_end - &__flash_lpfw_start; i++) *((uint32_t *)__lpram_fw_start + i) = - *(&__flash_lpfw_start + i); + *(&__flash_lpfw_start + i); /* execute hibernate func in LPRAM */ __hibernate_in_lpram(); @@ -148,7 +145,7 @@ void __hibernate_npcx_series(void) #ifdef CONFIG_EXTERNAL_STORAGE /* Sysjump utilities in low power ram for npcx5 series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) +noreturn void __keep __attribute__((section(".lowpower_ram2"))) __start_gdma(uint32_t exeAddr) { /* Enable GDMA now */ @@ -159,7 +156,7 @@ __start_gdma(uint32_t exeAddr) /* Wait for transfer to complete/fail */ while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) && - !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) + !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) ; /* Disable GDMA now */ @@ -186,7 +183,7 @@ __start_gdma(uint32_t exeAddr) /* Bypass for GMDA issue of ROM api utilities only on npcx5 series. */ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr) + uint32_t size, uint32_t exeAddr) { int i; uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */ @@ -195,7 +192,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * it's a thumb branch for cortex-m series CPU. */ void (*__start_gdma_in_lpram)(uint32_t) = - (void(*)(uint32_t))(__lpram_lfw_start | 0x01); + (void (*)(uint32_t))(__lpram_lfw_start | 0x01); /* * Before enabling burst mode for better performance of GDMA, it's @@ -203,7 +200,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * are 16 bytes aligned in case failure occurs. */ ASSERT((size % chunkSize) == 0 && (srcAddr % chunkSize) == 0 && - (dstAddr % chunkSize) == 0); + (dstAddr % chunkSize) == 0); /* Check valid address for jumpiing */ ASSERT(exeAddr != 0x0); @@ -253,7 +250,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) *((uint32_t *)__lpram_lfw_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); /* Start GDMA in Suspend RAM */ __start_gdma_in_lpram(exeAddr); -- cgit v1.2.1 From ecda6d663e2d97e4ff84a93bc5f8f358ad3d7fd5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:29 -0600 Subject: include/test_util.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8ff62ee4f2babfe185edc11062a0a52437193454 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730420 Reviewed-by: Jeremy Bettis --- include/test_util.h | 147 +++++++++++++++++++++++++++------------------------- 1 file changed, 75 insertions(+), 72 deletions(-) diff --git a/include/test_util.h b/include/test_util.h index 9dcb31297f..03058fdaaf 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -20,48 +20,48 @@ /* This allows tests to be easily commented out in run_test for debugging */ #define test_static static __attribute__((unused)) -#define RUN_TEST(n) \ - do { \ +#define RUN_TEST(n) \ + do { \ ccprintf("Running %s...\n", #n); \ - cflush(); \ - before_test(); \ - if (n() == EC_SUCCESS) { \ - ccputs("OK\n"); \ - } else { \ - ccputs("Fail\n"); \ - __test_error_count++; \ - } \ - after_test(); \ + cflush(); \ + before_test(); \ + if (n() == EC_SUCCESS) { \ + ccputs("OK\n"); \ + } else { \ + ccputs("Fail\n"); \ + __test_error_count++; \ + } \ + after_test(); \ } while (0) -#define TEST_ASSERT(n) \ - do { \ - if (!(n)) { \ - ccprintf("%s:%d: ASSERTION failed: %s\n", \ - __FILE__, __LINE__, #n); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ +#define TEST_ASSERT(n) \ + do { \ + if (!(n)) { \ + ccprintf("%s:%d: ASSERTION failed: %s\n", __FILE__, \ + __LINE__, #n); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) #if defined(__cplusplus) && !defined(__auto_type) #define __auto_type auto #endif -#define TEST_OPERATOR(a, b, op, fmt) \ - do { \ - __auto_type _a = (a); \ - __auto_type _b = (b); \ - if (!(_a op _b)) { \ - ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \ - __FILE__, __LINE__, #a, #b); \ - ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", \ - _a, _b); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } else { \ - ccprintf("Pass: %s " #op " %s\n", #a, #b); \ - } \ +#define TEST_OPERATOR(a, b, op, fmt) \ + do { \ + __auto_type _a = (a); \ + __auto_type _b = (b); \ + if (!(_a op _b)) { \ + ccprintf("%s:%d: ASSERTION failed: %s " #op " %s\n", \ + __FILE__, __LINE__, #a, #b); \ + ccprintf("\t\tEVAL: " fmt " " #op " " fmt "\n", _a, \ + _b); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } else { \ + ccprintf("Pass: %s " #op " %s\n", #a, #b); \ + } \ } while (0) #define TEST_EQ(a, b, fmt) TEST_OPERATOR(a, b, ==, fmt) @@ -70,8 +70,8 @@ #define TEST_LE(a, b, fmt) TEST_OPERATOR(a, b, <=, fmt) #define TEST_GT(a, b, fmt) TEST_OPERATOR(a, b, >, fmt) #define TEST_GE(a, b, fmt) TEST_OPERATOR(a, b, >=, fmt) -#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a & (int)bits, (int)bits, ==, "%u") -#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a & (int)bits, 0, ==, "%u") +#define TEST_BITS_SET(a, bits) TEST_OPERATOR(a &(int)bits, (int)bits, ==, "%u") +#define TEST_BITS_CLEARED(a, bits) TEST_OPERATOR(a &(int)bits, 0, ==, "%u") #define TEST_NEAR(a, b, epsilon, fmt) \ TEST_OPERATOR(ABS((a) - (b)), epsilon, <, fmt) @@ -79,39 +79,39 @@ #define TEST_ASSERT_ABS_LESS(n, t) TEST_OPERATOR(__ABS(n), t, <, "%d") -#define TEST_ASSERT_ARRAY_EQ(s, d, n) \ - do { \ - int __i; \ - for (__i = 0; __i < n; ++__i) \ - if ((s)[__i] != (d)[__i]) { \ +#define TEST_ASSERT_ARRAY_EQ(s, d, n) \ + do { \ + int __i; \ + for (__i = 0; __i < n; ++__i) \ + if ((s)[__i] != (d)[__i]) { \ ccprintf("%s:%d: ASSERT_ARRAY_EQ failed at " \ - "index=%d: %d != %d\n", \ - __FILE__, __LINE__, \ - __i, (int)(s)[__i], (int)(d)[__i]); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ + "index=%d: %d != %d\n", \ + __FILE__, __LINE__, __i, \ + (int)(s)[__i], (int)(d)[__i]); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) -#define TEST_ASSERT_MEMSET(d, c, n) \ - do { \ - int __i; \ - for (__i = 0; __i < n; ++__i) \ - if ((d)[__i] != (c)) { \ +#define TEST_ASSERT_MEMSET(d, c, n) \ + do { \ + int __i; \ + for (__i = 0; __i < n; ++__i) \ + if ((d)[__i] != (c)) { \ ccprintf("%s:%d: ASSERT_MEMSET failed at " \ - "index=%d: %d != %d\n", \ - __FILE__, __LINE__, \ - __i, (int)(d)[__i], (c)); \ - task_dump_trace(); \ - return EC_ERROR_UNKNOWN; \ - } \ + "index=%d: %d != %d\n", \ + __FILE__, __LINE__, __i, \ + (int)(d)[__i], (c)); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ } while (0) -#define TEST_CHECK(n) \ - do { \ - if (n) \ - return EC_SUCCESS; \ - else \ +#define TEST_CHECK(n) \ + do { \ + if (n) \ + return EC_SUCCESS; \ + else \ return EC_ERROR_UNKNOWN; \ } while (0) @@ -195,8 +195,12 @@ void interrupt_generator_udelay(unsigned us); void wait_for_task_started(void); void wait_for_task_started_nosleep(void); #else -static inline void wait_for_task_started(void) { } -static inline void wait_for_task_started_nosleep(void) { } +static inline void wait_for_task_started(void) +{ +} +static inline void wait_for_task_started_nosleep(void) +{ +} #endif uint32_t prng(uint32_t seed); @@ -271,8 +275,8 @@ struct test_i2c_read_string_dev { struct test_i2c_xfer { /* I2C xfer handler */ int (*routine)(const int port, const uint16_t i2c_addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); }; struct test_i2c_write_dev { @@ -290,11 +294,10 @@ struct test_i2c_write_dev { * * @param routine Function pointer, with the same prototype as i2c_xfer() */ -#define DECLARE_TEST_I2C_XFER(routine) \ - const struct test_i2c_xfer __no_sanitize_address \ - __test_i2c_xfer_##routine \ - __attribute__((section(".rodata.test_i2c.xfer"))) \ - = {routine} +#define DECLARE_TEST_I2C_XFER(routine) \ + const struct test_i2c_xfer __no_sanitize_address \ + __test_i2c_xfer_##routine __attribute__(( \ + section(".rodata.test_i2c.xfer"))) = { routine } /* * Detach an I2C device. Once detached, any read/write command regarding the @@ -413,7 +416,7 @@ struct unit_test { */ #define ztest_unit_test_setup_teardown(fn, setup, teardown) \ { \ - #fn, fn, setup, teardown \ +#fn, fn, setup, teardown \ } /** -- cgit v1.2.1 From 4d055c6c2d85cd814b7dd6f3a6db6fb10b41dc9b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:07 -0600 Subject: include/usb_dp_alt_mode.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I841927d49d26a8412a8bda4436f412e070acbedf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730433 Reviewed-by: Jeremy Bettis --- include/usb_dp_alt_mode.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h index 40b7c321dd..f7c2df77ef 100644 --- a/include/usb_dp_alt_mode.h +++ b/include/usb_dp_alt_mode.h @@ -52,7 +52,7 @@ bool dp_entry_is_done(int port); * @param vdm VDM from ACK */ void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Handles NAKed (or Not Supported or timed out) DisplayPort VDM requests. @@ -77,4 +77,4 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd); enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, uint32_t *vdm); -#endif /* __CROS_EC_USB_DP_ALT_MODE_H */ +#endif /* __CROS_EC_USB_DP_ALT_MODE_H */ -- cgit v1.2.1 From 59c7f637b646e82c233a9cc938d67aece63c82a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:12 -0600 Subject: include/vec4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I086f7a69cb402efd66b41cb85db8d325000b4b5b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730456 Reviewed-by: Jeremy Bettis --- include/vec4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/vec4.h b/include/vec4.h index f1724d955e..0a75981c4d 100644 --- a/include/vec4.h +++ b/include/vec4.h @@ -12,4 +12,4 @@ typedef float floatv4_t[4]; typedef fp_t fpv4_t[4]; -#endif /* __CROS_EC_VEC_4_H */ +#endif /* __CROS_EC_VEC_4_H */ -- cgit v1.2.1 From d8bf09fc72007231c57249f2acd48ccd765b596e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:58 -0600 Subject: baseboard/brask/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fe51ba5d1853a9eb1e4a8db1968de1c58a5e768 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727856 Reviewed-by: Jeremy Bettis --- baseboard/brask/baseboard.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/baseboard/brask/baseboard.c b/baseboard/brask/baseboard.c index 2e60b565f8..042aa7d386 100644 --- a/baseboard/brask/baseboard.c +++ b/baseboard/brask/baseboard.c @@ -9,6 +9,5 @@ #include "gpio_signal.h" /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); -- cgit v1.2.1 From 94fea06422317ed9085547cca5b1ebeed0600c9f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:39 -0600 Subject: board/bellis/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5631555a64ee40e33eb4829ef724927c7b04749c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728032 Reviewed-by: Jeremy Bettis --- board/bellis/board.c | 109 ++++++++++++++++++++++----------------------------- 1 file changed, 47 insertions(+), 62 deletions(-) diff --git a/board/bellis/board.c b/board/bellis/board.c index 7c7392e4d5..1a318cffdc 100644 --- a/board/bellis/board.c +++ b/board/bellis/board.c @@ -44,8 +44,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -57,42 +57,36 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(5), - STM32_RANK(1)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15), - STM32_RANK(2)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5), + STM32_RANK(1) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15), + STM32_RANK(2) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 2, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 2, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 3, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 3, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -100,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -157,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -239,12 +232,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -314,8 +307,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -333,8 +325,7 @@ static void board_spi_disable(void) STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; #endif } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -373,17 +364,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ /* Lid accel private data */ @@ -471,7 +458,7 @@ struct motion_sensor_t motion_sensors[] = { const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct it8801_pwm_t it8801_pwm_channels[] = { - [IT8801_PWM_CH_KBLIGHT] = {.index = 4}, + [IT8801_PWM_CH_KBLIGHT] = { .index = 4 }, }; void board_kblight_init(void) @@ -487,11 +474,11 @@ bool board_has_kb_backlight(void) #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* Battery functions */ -#define SB_SMARTCHARGE 0x26 +#define SB_SMARTCHARGE 0x26 /* Quick charge enable bit */ -#define SMART_QUICK_CHARGE 0x02 +#define SMART_QUICK_CHARGE 0x02 /* Quick charge support bit */ -#define MODE_QUICK_CHARGE_SUPPORT 0x01 +#define MODE_QUICK_CHARGE_SUPPORT 0x01 static void sb_quick_charge_mode(int enable) { @@ -562,8 +549,8 @@ int board_get_battery_i2c(void) } #ifdef SECTION_IS_RW -static int it8801_get_target_channel(enum pwm_channel *channel, - int type, int index) +static int it8801_get_target_channel(enum pwm_channel *channel, int type, + int index) { switch (type) { case EC_PWM_TYPE_GENERIC: @@ -586,14 +573,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - duty = (uint32_t) p->duty * 255 / 65535; + duty = (uint32_t)p->duty * 255 / 65535; it8801_pwm_set_raw_duty(channel, duty); it8801_pwm_enable(channel, p->duty > 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); static enum ec_status @@ -607,12 +593,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255; + r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255; args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); #endif -- cgit v1.2.1 From bc270aec7f3871908e4e373252f9dc67ea1d3d20 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:41 -0600 Subject: board/kingoftown/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98f45b4e0918cda9497d961b4cea27dc35d1014f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728551 Reviewed-by: Jeremy Bettis --- board/kingoftown/led.c | 50 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/board/kingoftown/led.c b/board/kingoftown/led.c index a543bb5403..412c14ef2f 100644 --- a/board/kingoftown/led.c +++ b/board/kingoftown/led.c @@ -36,15 +36,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void side_led_set_color(int port, enum led_color color) { gpio_set_level(port ? GPIO_EC_CHG_LED_Y_C1 : GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(port ? GPIO_EC_CHG_LED_W_C1 : GPIO_EC_CHG_LED_W_C0, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -107,15 +107,16 @@ static void board_led_set_battery(void) * charging. */ if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC); side_led_set_color(0, (led_blink_cycle < TIMES_TICK_ONE_SEC) ? - LED_WHITE : LED_OFF); + LED_WHITE : + LED_OFF); side_led_set_color(1, (led_blink_cycle < TIMES_TICK_ONE_SEC) ? - LED_WHITE : LED_OFF); + LED_WHITE : + LED_OFF); return; } @@ -128,15 +129,18 @@ static void board_led_set_battery(void) break; case PWR_STATE_DISCHARGE: if (charge_get_percent() <= 10) { - led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC); + led_blink_cycle = + battery_ticks % (2 * TIMES_TICK_ONE_SEC); if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) - side_led_set_color(1, - (led_blink_cycle < TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + side_led_set_color(1, (led_blink_cycle < + TIMES_TICK_ONE_SEC) ? + LED_AMBER : + LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(0, - (led_blink_cycle < TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + side_led_set_color(0, (led_blink_cycle < + TIMES_TICK_ONE_SEC) ? + LED_AMBER : + LED_OFF); } else { if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) side_led_set_color(1, LED_OFF); @@ -147,21 +151,27 @@ static void board_led_set_battery(void) case PWR_STATE_ERROR: led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC; if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) - side_led_set_color(1, (led_blink_cycle < TIMES_TICK_HALF_SEC) ? - LED_AMBER : LED_OFF); + side_led_set_color(1, (led_blink_cycle < + TIMES_TICK_HALF_SEC) ? + LED_AMBER : + LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - side_led_set_color(0, (led_blink_cycle < TIMES_TICK_HALF_SEC) ? - LED_AMBER : LED_OFF); + side_led_set_color(0, (led_blink_cycle < + TIMES_TICK_HALF_SEC) ? + LED_AMBER : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) { - led_blink_cycle = battery_ticks % (2 * TIMES_TICK_ONE_SEC); + led_blink_cycle = + battery_ticks % (2 * TIMES_TICK_ONE_SEC); set_active_port_color( (led_blink_cycle < TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + LED_AMBER : + LED_OFF); } else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 0020a932fecc3970c105af3af6e6fb15141b5af3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:16 -0600 Subject: power/sdm845.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I18232463d656fc5e86a375f586287b5e7b2a8a14 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730487 Reviewed-by: Jeremy Bettis --- power/sdm845.c | 52 +++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/power/sdm845.c b/power/sdm845.c index 7463e00069..dcb09ec266 100644 --- a/power/sdm845.c +++ b/power/sdm845.c @@ -34,15 +34,14 @@ #include "task.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Masks for power signals */ -#define IN_POWER_GOOD POWER_SIGNAL_MASK(SDM845_POWER_GOOD) -#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED) - +#define IN_POWER_GOOD POWER_SIGNAL_MASK(SDM845_POWER_GOOD) +#define IN_AP_RST_ASSERTED POWER_SIGNAL_MASK(SDM845_AP_RST_ASSERTED) /* Long power key press to force shutdown */ -#define DELAY_FORCE_SHUTDOWN (8 * SECOND) +#define DELAY_FORCE_SHUTDOWN (8 * SECOND) /* * If the power button is pressed to turn on, then held for this long, we @@ -52,40 +51,40 @@ * into the inner loop, waiting for next event to occur (power button * press or POWER_GOOD == 0). */ -#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) +#define DELAY_SHUTDOWN_ON_POWER_HOLD (8 * SECOND) /* * After trigger PMIC power sequence, how long it triggers AP to turn on * or off. Observed that the worst case is ~150ms. Pick a safe vale. */ -#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC) +#define PMIC_POWER_AP_RESPONSE_TIMEOUT (350 * MSEC) /* * After force off the switch cap, how long the PMIC/AP totally off. * Observed that the worst case is 2s. Pick a safe vale. */ -#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND) +#define FORCE_OFF_RESPONSE_TIMEOUT (4 * SECOND) /* Wait for polling the AP on signal */ -#define PMIC_POWER_AP_WAIT (1 * MSEC) +#define PMIC_POWER_AP_WAIT (1 * MSEC) /* The length of an issued low pulse to the PMIC_RESIN_L signal */ -#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC) +#define PMIC_RESIN_PULSE_LENGTH (20 * MSEC) /* The timeout of the check if the system can boot AP */ -#define CAN_BOOT_AP_CHECK_TIMEOUT (500 * MSEC) +#define CAN_BOOT_AP_CHECK_TIMEOUT (500 * MSEC) /* Wait for polling if the system can boot AP */ -#define CAN_BOOT_AP_CHECK_WAIT (100 * MSEC) +#define CAN_BOOT_AP_CHECK_WAIT (100 * MSEC) /* The timeout of the check if the switchcap outputs good voltage */ -#define SWITCHCAP_PG_CHECK_TIMEOUT (50 * MSEC) +#define SWITCHCAP_PG_CHECK_TIMEOUT (50 * MSEC) /* Wait for polling if the switchcap outputs good voltage */ -#define SWITCHCAP_PG_CHECK_WAIT (5 * MSEC) +#define SWITCHCAP_PG_CHECK_WAIT (5 * MSEC) /* Delay between power-on the system and power-on the PMIC */ -#define SYSTEM_POWER_ON_DELAY (10 * MSEC) +#define SYSTEM_POWER_ON_DELAY (10 * MSEC) /* TODO(crosbug.com/p/25047): move to HOOK_POWER_BUTTON_CHANGE */ /* 1 if the power button was pressed last time we checked */ @@ -182,9 +181,11 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal) */ ap_rst_overdriven = 1; gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | - GPIO_SEL_1P8V | GPIO_OUT_HIGH); + GPIO_SEL_1P8V | + GPIO_OUT_HIGH); gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | - GPIO_SEL_1P8V | GPIO_OUT_LOW); + GPIO_SEL_1P8V | + GPIO_OUT_LOW); } else { /* * The pull-up rail POWER_GOOD drops. @@ -192,10 +193,10 @@ void chipset_warm_reset_interrupt(enum gpio_signal signal) * High-Z both AP_RST_L and PS_HOLD to restore their * states. */ - gpio_set_flags(GPIO_AP_RST_L, GPIO_INT_BOTH | - GPIO_SEL_1P8V); - gpio_set_flags(GPIO_PS_HOLD, GPIO_INT_BOTH | - GPIO_SEL_1P8V); + gpio_set_flags(GPIO_AP_RST_L, + GPIO_INT_BOTH | GPIO_SEL_1P8V); + gpio_set_flags(GPIO_PS_HOLD, + GPIO_INT_BOTH | GPIO_SEL_1P8V); ap_rst_overdriven = 0; } } else { @@ -268,7 +269,6 @@ static void wait_switchcap_power_good(int enable) else CPRINTS("SWITCHCAP STILL POWER GOOD!"); } - } /** @@ -500,7 +500,7 @@ static int power_is_enough(void) * waste the time and exit the loop. */ while (!system_can_boot_ap() && !charge_want_shutdown() && - get_time().val < poll_deadline.val) { + get_time().val < poll_deadline.val) { usleep(CAN_BOOT_AP_CHECK_WAIT); } @@ -850,7 +850,7 @@ enum power_state_t { PSTATE_COUNT, }; -static const char * const state_name[] = { +static const char *const state_name[] = { "unknown", "off", "on", @@ -882,6 +882,4 @@ static int command_power(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(power, command_power, - "on/off", - "Turn AP power on/off"); +DECLARE_CONSOLE_COMMAND(power, command_power, "on/off", "Turn AP power on/off"); -- cgit v1.2.1 From f53634f8141f640b2940687f80d4a66780ff6ede Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:57 -0600 Subject: util/ec_sb_firmware_update.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27401f80770c2ef705a97126f2d1607a21b08edb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730614 Reviewed-by: Jeremy Bettis --- util/ec_sb_firmware_update.c | 272 ++++++++++++++++++------------------------- 1 file changed, 114 insertions(+), 158 deletions(-) diff --git a/util/ec_sb_firmware_update.c b/util/ec_sb_firmware_update.c index a959cd6fe9..c8172a3691 100644 --- a/util/ec_sb_firmware_update.c +++ b/util/ec_sb_firmware_update.c @@ -21,8 +21,8 @@ /* Subcommands: [check|update] */ enum { OP_UNKNOWN = 0, - OP_CHECK = 1, - OP_UPDATE = 2, + OP_CHECK = 1, + OP_UPDATE = 2, }; struct delay_value { @@ -33,54 +33,50 @@ struct delay_value { /* Default retry counter on errors */ #define SB_FW_UPDATE_DEFAULT_RETRY_CNT 3 /* Default delay value */ -#define SB_FW_UPDATE_DEFAULT_DELAY 1000 +#define SB_FW_UPDATE_DEFAULT_DELAY 1000 -#define DELAY_US_BEGIN 500000 -#define DELAY_US_END 1000000 -#define DELAY_US_BUSY 1000000 -#define DELAY_US_WRITE_END 50000 +#define DELAY_US_BEGIN 500000 +#define DELAY_US_END 1000000 +#define DELAY_US_BUSY 1000000 +#define DELAY_US_WRITE_END 50000 static struct delay_value sb_delays[] = { - {1, 100000}, - {2, 9000000}, - {4, 100000}, - {771, 30000}, - {2200, 10000}, - {0xFFFFFF, 50000}, + { 1, 100000 }, { 2, 9000000 }, { 4, 100000 }, + { 771, 30000 }, { 2200, 10000 }, { 0xFFFFFF, 50000 }, }; enum fw_update_state { - S0_READ_STATUS = 0, - S1_READ_INFO = 1, + S0_READ_STATUS = 0, + S1_READ_INFO = 1, S2_WRITE_PREPARE = 2, - S3_READ_STATUS = 3, - S4_WRITE_UPDATE = 4, - S5_READ_STATUS = 5, - S6_WRITE_BLOCK = 6, - S7_READ_STATUS = 7, - S8_WRITE_END = 8, - S9_READ_STATUS = 9, - S10_TERMINAL = 10 + S3_READ_STATUS = 3, + S4_WRITE_UPDATE = 4, + S5_READ_STATUS = 5, + S6_WRITE_BLOCK = 6, + S7_READ_STATUS = 7, + S8_WRITE_END = 8, + S9_READ_STATUS = 9, + S10_TERMINAL = 10 }; #define MAX_FW_IMAGE_NAME_SIZE 80 /* Firmware Update Control Flags */ enum { - F_AC_PRESENT = 0x1, /* AC Present */ + F_AC_PRESENT = 0x1, /* AC Present */ F_VERSION_CHECK = 0x2, /* do firmware version check */ - F_UPDATE = 0x4, /* do firmware update */ - F_NEED_UPDATE = 0x8, /* need firmware update */ - F_POWERD_DISABLED = 0x10, /* powerd is disabled */ - F_LFCC_ZERO = 0x20, /* last full charge is zero */ - F_BATT_DISCHARGE = 0x40 /* battery discharging */ + F_UPDATE = 0x4, /* do firmware update */ + F_NEED_UPDATE = 0x8, /* need firmware update */ + F_POWERD_DISABLED = 0x10, /* powerd is disabled */ + F_LFCC_ZERO = 0x20, /* last full charge is zero */ + F_BATT_DISCHARGE = 0x40 /* battery discharging */ }; struct fw_update_ctrl { uint32_t flags; /* fw update control flags */ - int size; /* size of battery firmware image */ - char *ptr; /* current read pointer of the firmware image */ - int offset; /* current block write offset */ + int size; /* size of battery firmware image */ + char *ptr; /* current read pointer of the firmware image */ + int offset; /* current block write offset */ struct sb_fw_header *fw_img_hdr; /*pointer to firmware image header*/ struct sb_fw_update_status status; struct sb_fw_update_info info; @@ -106,76 +102,59 @@ static uint32_t get_delay_value(uint32_t offset, uint32_t step_size) if (offset <= sb_delays[i].steps * step_size) return sb_delays[i].value; } - return sb_delays[sz-1].value; + return sb_delays[sz - 1].value; } -static void print_battery_firmware_image_hdr( - struct sb_fw_header *hdr) +static void print_battery_firmware_image_hdr(struct sb_fw_header *hdr) { printf("Latest Battery Firmware:\n"); - printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n", - hdr->signature[0], - hdr->signature[1], - hdr->signature[2], - hdr->signature[3], - hdr->hdr_version, hdr->pkg_version_major_minor); + printf("\t%c%c%c%c hdr_ver:%04x major_minor:%04x\n", hdr->signature[0], + hdr->signature[1], hdr->signature[2], hdr->signature[3], + hdr->hdr_version, hdr->pkg_version_major_minor); printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n", - hdr->vendor_id, hdr->battery_type, hdr->fw_version, - hdr->data_table_version); + hdr->vendor_id, hdr->battery_type, hdr->fw_version, + hdr->data_table_version); printf("\tbinary offset:0x%08x size:0x%08x chk_sum:0x%02x\n", - hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum); + hdr->fw_binary_offset, hdr->fw_binary_size, hdr->checksum); } static void print_info(struct sb_fw_update_info *info) { printf("\nCurrent Battery Firmware:\n"); printf("\tmaker:0x%04x hwid:0x%04x fw_ver:0x%04x tbl_ver:0x%04x\n", - info->maker_id, - info->hardware_id, - info->fw_version, - info->data_version); + info->maker_id, info->hardware_id, info->fw_version, + info->data_version); return; } static void print_status(struct sb_fw_update_status *sts) { printf("f_maker_id:%d f_hw_id:%d f_fw_ver:%d f_permnent:%d\n", - sts->v_fail_maker_id, - sts->v_fail_hw_id, - sts->v_fail_fw_version, - sts->v_fail_permanent); + sts->v_fail_maker_id, sts->v_fail_hw_id, sts->v_fail_fw_version, + sts->v_fail_permanent); printf("permanent failure:%d abnormal:%d fw_update:%d\n", - sts->permanent_failure, - sts->abnormal_condition, - sts->fw_update_supported); + sts->permanent_failure, sts->abnormal_condition, + sts->fw_update_supported); printf("fw_update_mode:%d fw_corrupted:%d cmd_reject:%d\n", - sts->fw_update_mode, - sts->fw_corrupted, - sts->cmd_reject); + sts->fw_update_mode, sts->fw_corrupted, sts->cmd_reject); printf("invliad data:%d fw_fatal_err:%d fec_err:%d busy:%d\n", - sts->invalid_data, - sts->fw_fatal_error, - sts->fec_error, - sts->busy); + sts->invalid_data, sts->fw_fatal_error, sts->fec_error, + sts->busy); printf("\n"); return; } /* @return 1 (True) if img signature is valid */ -static int check_battery_firmware_image_signature( - struct sb_fw_header *hdr) +static int check_battery_firmware_image_signature(struct sb_fw_header *hdr) { - return (hdr->signature[0] == 'B') && - (hdr->signature[1] == 'T') && - (hdr->signature[2] == 'F') && - (hdr->signature[3] == 'W'); + return (hdr->signature[0] == 'B') && (hdr->signature[1] == 'T') && + (hdr->signature[2] == 'F') && (hdr->signature[3] == 'W'); } /* @return 1 (True) if img checksum is valid. */ -static int check_battery_firmware_image_checksum( - struct sb_fw_header *hdr) +static int check_battery_firmware_image_checksum(struct sb_fw_header *hdr) { int i; uint8_t sum = 0; @@ -189,22 +168,19 @@ static int check_battery_firmware_image_checksum( } /* @return 1 (True) if img versions are ok to update. */ -static int check_battery_firmware_image_version( - struct sb_fw_header *hdr, - struct sb_fw_update_info *p) +static int check_battery_firmware_image_version(struct sb_fw_header *hdr, + struct sb_fw_update_info *p) { /* * If the battery firmware has a newer fw version * or a newer data table version, then it is ok to update. */ - return (hdr->fw_version > p->fw_version) - || (hdr->data_table_version > p->data_version); + return (hdr->fw_version > p->fw_version) || + (hdr->data_table_version > p->data_version); } - -static int check_battery_firmware_ids( - struct sb_fw_header *hdr, - struct sb_fw_update_info *p) +static int check_battery_firmware_ids(struct sb_fw_header *hdr, + struct sb_fw_update_info *p) { return ((hdr->vendor_id == p->maker_id) && (hdr->battery_type == p->hardware_id)); @@ -213,33 +189,30 @@ static int check_battery_firmware_ids( /* check_if_need_update_fw * @return 1 (true) if need; 0 (false) if not. */ -static int check_if_valid_fw( - struct sb_fw_header *hdr, - struct sb_fw_update_info *info) +static int check_if_valid_fw(struct sb_fw_header *hdr, + struct sb_fw_update_info *info) { - return check_battery_firmware_image_signature(hdr) - && check_battery_firmware_ids(hdr, info) - && check_battery_firmware_image_checksum(hdr); + return check_battery_firmware_image_signature(hdr) && + check_battery_firmware_ids(hdr, info) && + check_battery_firmware_image_checksum(hdr); } /* check_if_need_update_fw * @return 1 (true) if need; 0 (false) if not. */ -static int check_if_need_update_fw( - struct sb_fw_header *hdr, - struct sb_fw_update_info *info) +static int check_if_need_update_fw(struct sb_fw_header *hdr, + struct sb_fw_update_info *info) { return check_battery_firmware_image_version(hdr, info); } static void log_msg(struct fw_update_ctrl *fw_update, - enum fw_update_state state, const char *msg) + enum fw_update_state state, const char *msg) { - sprintf(fw_update->msg, - "Battery Firmware Updater State:%d %s", state, msg); + sprintf(fw_update->msg, "Battery Firmware Updater State:%d %s", state, + msg); } - static char *read_fw_image(struct fw_update_ctrl *fw_update) { int size; @@ -259,11 +232,11 @@ static char *read_fw_image(struct fw_update_ctrl *fw_update) print_battery_firmware_image_hdr(fw_update->fw_img_hdr); if (fw_update->fw_img_hdr->fw_binary_offset >= fw_update->size || - fw_update->size < 256) { + fw_update->size < 256) { printf("Load Firmware Image[%s] Error offset:%d size:%d\n", - fw_update->image_name, - fw_update->fw_img_hdr->fw_binary_offset, - fw_update->size); + fw_update->image_name, + fw_update->fw_img_hdr->fw_binary_offset, + fw_update->size); free(buf); return NULL; } @@ -284,9 +257,9 @@ static int get_status(struct sb_fw_update_status *status) param->hdr.subcmd = EC_SB_FW_UPDATE_STATUS; do { usleep(SB_FW_UPDATE_DEFAULT_DELAY); - rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, - param, sizeof(struct ec_sb_fw_update_header), - resp, SB_FW_UPDATE_CMD_STATUS_SIZE); + rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param, + sizeof(struct ec_sb_fw_update_header), resp, + SB_FW_UPDATE_CMD_STATUS_SIZE); } while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT)); if (rv < 0) { @@ -312,9 +285,9 @@ static int get_info(struct sb_fw_update_info *info) param->hdr.subcmd = EC_SB_FW_UPDATE_INFO; do { usleep(SB_FW_UPDATE_DEFAULT_DELAY); - rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, - param, sizeof(struct ec_sb_fw_update_header), - resp, SB_FW_UPDATE_CMD_INFO_SIZE); + rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param, + sizeof(struct ec_sb_fw_update_header), resp, + SB_FW_UPDATE_CMD_INFO_SIZE); } while ((rv < 0) && (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT)); if (rv < 0) { @@ -334,8 +307,8 @@ static int send_subcmd(int subcmd) (struct ec_params_sb_fw_update *)ec_outbuf; param->hdr.subcmd = subcmd; - rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, - param, sizeof(struct ec_sb_fw_update_header), NULL, 0); + rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param, + sizeof(struct ec_sb_fw_update_header), NULL, 0); if (rv < 0) { printf("Firmware Update subcmd:%d Error\n", subcmd); return -EC_RES_ERROR; @@ -343,22 +316,21 @@ static int send_subcmd(int subcmd) return EC_RES_SUCCESS; } -static int write_block(struct fw_update_ctrl *fw_update, - int offset, int bsize) +static int write_block(struct fw_update_ctrl *fw_update, int offset, int bsize) { int rv; struct ec_params_sb_fw_update *param = (struct ec_params_sb_fw_update *)ec_outbuf; - memcpy(param->write.data, fw_update->ptr+offset, bsize); + memcpy(param->write.data, fw_update->ptr + offset, bsize); param->hdr.subcmd = EC_SB_FW_UPDATE_WRITE; - rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, - param, sizeof(struct ec_params_sb_fw_update), NULL, 0); + rv = ec_command(EC_CMD_SB_FW_UPDATE, 0, param, + sizeof(struct ec_params_sb_fw_update), NULL, 0); if (rv < 0) { printf("Firmware Update Write Error ptr:%p offset@%x\n", - fw_update->ptr, offset); + fw_update->ptr, offset); return -EC_RES_ERROR; } return EC_RES_SUCCESS; @@ -373,7 +345,7 @@ static void dump_data(char *data, int offset, int size) printf("Offset:0x%X\n", offset); for (i = 0; i < size; i++) { - if ((i%16) == 0) + if ((i % 16) == 0) printf("\n"); printf("%02X ", data[i]); } @@ -397,8 +369,8 @@ static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update) return S10_TERMINAL; } - if (!((fw_update->status.abnormal_condition == 0) - && (fw_update->status.fw_update_supported == 1))) { + if (!((fw_update->status.abnormal_condition == 0) && + (fw_update->status.fw_update_supported == 1))) { return S0_READ_STATUS; } @@ -409,8 +381,8 @@ static enum fw_update_state s0_read_status(struct fw_update_ctrl *fw_update) return S1_READ_INFO; } -static enum fw_update_state s1_read_battery_info( - struct fw_update_ctrl *fw_update) +static enum fw_update_state +s1_read_battery_info(struct fw_update_ctrl *fw_update) { int rv; @@ -431,9 +403,8 @@ static enum fw_update_state s1_read_battery_info( print_info(&fw_update->info); sprintf(fw_update->image_name, - "/lib/firmware/battery/maker.%04x.hwid.%04x.bin", - fw_update->info.maker_id, - fw_update->info.hardware_id); + "/lib/firmware/battery/maker.%04x.hwid.%04x.bin", + fw_update->info.maker_id, fw_update->info.hardware_id); if (NULL == read_fw_image(fw_update)) { fw_update->rv = 0; @@ -520,7 +491,6 @@ static enum fw_update_state s3_read_status(struct fw_update_ctrl *fw_update) return S10_TERMINAL; } return S4_WRITE_UPDATE; - } static enum fw_update_state s4_write_update(struct fw_update_ctrl *fw_update) @@ -589,7 +559,7 @@ static enum fw_update_state s6_write_block(struct fw_update_ctrl *fw_update) * Add more delays after the last few (3) block writes. * 3 is chosen based on current test results. */ - if ((offset + 3*fw_update->step_size) >= fw_update->size) + if ((offset + 3 * fw_update->step_size) >= fw_update->size) usleep(DELAY_US_WRITE_END); usleep(get_delay_value(offset, fw_update->step_size)); @@ -609,38 +579,36 @@ static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update) usleep(SB_FW_UPDATE_DEFAULT_DELAY); rv = get_status(&fw_update->status); if (rv) { - dump_data(fw_update->ptr+offset, offset, bsize); + dump_data(fw_update->ptr + offset, offset, bsize); print_status(&fw_update->status); fw_update->rv = -1; log_msg(fw_update, S7_READ_STATUS, "Interface Error"); return S10_TERMINAL; } } while (fw_update->status.busy && - (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT)); + (cnt++ < SB_FW_UPDATE_DEFAULT_RETRY_CNT)); if (fw_update->status.fec_error) { - dump_data(fw_update->ptr+offset, offset, bsize); + dump_data(fw_update->ptr + offset, offset, bsize); print_status(&fw_update->status); fw_update->rv = 0; return S6_WRITE_BLOCK; } if (fw_update->status.permanent_failure || - fw_update->status.v_fail_permanent) { - dump_data(fw_update->ptr+offset, offset, bsize); + fw_update->status.v_fail_permanent) { + dump_data(fw_update->ptr + offset, offset, bsize); print_status(&fw_update->status); fw_update->rv = -1; log_msg(fw_update, S7_READ_STATUS, "Battery Permanent Error"); return S8_WRITE_END; } if (fw_update->status.v_fail_maker_id || - fw_update->status.v_fail_hw_id || - fw_update->status.v_fail_fw_version || - fw_update->status.fw_corrupted || - fw_update->status.cmd_reject || - fw_update->status.invalid_data || - fw_update->status.fw_fatal_error) { - - dump_data(fw_update->ptr+offset, offset, bsize); + fw_update->status.v_fail_hw_id || + fw_update->status.v_fail_fw_version || + fw_update->status.fw_corrupted || fw_update->status.cmd_reject || + fw_update->status.invalid_data || + fw_update->status.fw_fatal_error) { + dump_data(fw_update->ptr + offset, offset, bsize); print_status(&fw_update->status); fw_update->rv = 0; return S1_READ_INFO; @@ -651,7 +619,6 @@ static enum fw_update_state s7_read_status(struct fw_update_ctrl *fw_update) return S6_WRITE_BLOCK; } - static enum fw_update_state s8_write_end(struct fw_update_ctrl *fw_update) { int rv; @@ -686,8 +653,8 @@ static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update) log_msg(fw_update, S9_READ_STATUS, "Interface Error"); return S10_TERMINAL; } - if ((fw_update->status.fw_update_mode == 1) - || (fw_update->status.busy == 1)) { + if ((fw_update->status.fw_update_mode == 1) || + (fw_update->status.busy == 1)) { usleep(SB_FW_UPDATE_DEFAULT_DELAY); fw_update->busy_retry_cnt--; return S9_READ_STATUS; @@ -697,22 +664,13 @@ static enum fw_update_state s9_read_status(struct fw_update_ctrl *fw_update) return S10_TERMINAL; } - typedef enum fw_update_state (*fw_state_func)(struct fw_update_ctrl *fw_update); -fw_state_func state_table[] = { - s0_read_status, - s1_read_battery_info, - s2_write_prepare, - s3_read_status, - s4_write_update, - s5_read_status, - s6_write_block, - s7_read_status, - s8_write_end, - s9_read_status -}; - +fw_state_func state_table[] = { s0_read_status, s1_read_battery_info, + s2_write_prepare, s3_read_status, + s4_write_update, s5_read_status, + s6_write_block, s7_read_status, + s8_write_end, s9_read_status }; /** * Update Smart Battery Firmware @@ -740,13 +698,13 @@ static int ec_sb_firmware_update(struct fw_update_ctrl *fw_update) return fw_update->rv; } -#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */ +#define GEC_LOCK_TIMEOUT_SECS 30 /* 30 secs */ void usage(char *argv[]) { printf("Usage: %s [check|update]\n" - " check: check if AC Adaptor is connected.\n" - " update: trigger battery firmware update.\n", - argv[0]); + " check: check if AC Adaptor is connected.\n" + " update: trigger battery firmware update.\n", + argv[0]); } int main(int argc, char *argv[]) @@ -827,10 +785,8 @@ int main(int argc, char *argv[]) fw_update.flags |= F_VERSION_CHECK; rv = ec_sb_firmware_update(&fw_update); - printf("Battery Firmware Update:0x%02x %s\n%s\n", - fw_update.flags, - ((rv) ? "FAIL " : " "), - fw_update.msg); + printf("Battery Firmware Update:0x%02x %s\n%s\n", fw_update.flags, + ((rv) ? "FAIL " : " "), fw_update.msg); /* Update battery firmware update interface to be protected */ if (!(fw_update.flags & F_NEED_UPDATE)) -- cgit v1.2.1 From 96513e1137486585b4705bc52c253bfe555d23fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:00 -0600 Subject: board/gimble/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibeff87f748796b4b24d08dbeaf2c9bfbf47af510 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728410 Reviewed-by: Jeremy Bettis --- board/gimble/board.h | 140 +++++++++++++++++++++++---------------------------- 1 file changed, 63 insertions(+), 77 deletions(-) diff --git a/board/gimble/board.h b/board/gimble/board.h index 32b2945abe..3593ccac0d 100644 --- a/board/gimble/board.h +++ b/board/gimble/board.h @@ -25,7 +25,7 @@ /* BMA253 accelerometer in lid */ #define CONFIG_ACCEL_BMA255 -#define CONFIG_ACCELGYRO_BMI160 /* Base accel/gyro */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel/gyro */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -42,8 +42,8 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* Enable sensor fifo, must also define the _SIZE and _THRES */ #define CONFIG_ACCEL_FIFO @@ -57,13 +57,13 @@ #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 1 +#define CONFIG_IO_EXPANDER_PORT_COUNT 1 #define CONFIG_USB_PD_TCPM_PS8815 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID @@ -78,9 +78,9 @@ #define CONFIG_USB_PD_FRS_PPC /* measure and check these values on gimble */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* I2C speed console command */ #define CONFIG_CMD_I2C_SPEED @@ -91,10 +91,10 @@ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -102,33 +102,33 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT @@ -139,28 +139,28 @@ /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT4_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 /* define this to aviod error on CONFIG_ACCELGYRO_BMI_COMM_I2C */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* Disabling Thunderbolt-compatible mode */ #undef CONFIG_USB_PD_TBT_COMPAT_MODE @@ -191,14 +191,14 @@ /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING /* PROCHOT defines */ -#define BATT_MAX_CONTINUE_DISCHARGE_WATT 45 +#define BATT_MAX_CONTINUE_DISCHARGE_WATT 45 /* Prochot assertion/deassertion ratios*/ #define PROCHOT_ADAPTER_WATT_RATIO 97 @@ -213,7 +213,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -232,17 +232,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT }; enum battery_type { BATTERY_SIMPLO_HIGHPOWER, @@ -251,24 +243,18 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_LED2 = 0, /* PWM0 (white charger) */ - PWM_CH_LED3, /* PWM1 (orange on DB) */ - PWM_CH_LED1, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED4, /* PWM7 (white on DB) */ + PWM_CH_LED2 = 0, /* PWM0 (white charger) */ + PWM_CH_LED3, /* PWM1 (orange on DB) */ + PWM_CH_LED1, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED4, /* PWM7 (white on DB) */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From eb74f717ba455092f95a2f6131616d2f238ddedd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:26 -0600 Subject: common/host_event_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8b415d8440a8a98303243de84dcd6600cef5279 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729654 Reviewed-by: Jeremy Bettis --- common/host_event_commands.c | 104 +++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 58 deletions(-) diff --git a/common/host_event_commands.c b/common/host_event_commands.c index 2a008c6a78..dee249ba4c 100644 --- a/common/host_event_commands.c +++ b/common/host_event_commands.c @@ -19,13 +19,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_EVENTS, outstr) -#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args) +#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args) /* * This is used to avoid 64-bit shifts which might require a new library * function. */ -#define HOST_EVENT_32BIT_MASK(x) (1UL << ((x) - 1)) +#define HOST_EVENT_32BIT_MASK(x) (1UL << ((x)-1)) static void host_event_set_bit(host_event_t *ev, uint8_t bit) { uint32_t *ptr = (uint32_t *)ev; @@ -49,7 +49,7 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit) #ifdef CONFIG_HOSTCMD_X86 -#define LPC_SYSJUMP_TAG 0x4c50 /* "LP" */ +#define LPC_SYSJUMP_TAG 0x4c50 /* "LP" */ #define LPC_SYSJUMP_OLD_VERSION 1 #define LPC_SYSJUMP_VERSION 2 @@ -72,14 +72,14 @@ static void host_event_set_bit(host_event_t *ev, uint8_t bit) * - EC_HOST_EVENT_MKBP * */ -#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) | \ +#define LPC_HOST_EVENT_ALWAYS_REPORT_DEFAULT_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_REBOOT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)) static host_event_t lpc_host_events; @@ -136,7 +136,7 @@ host_event_t lpc_get_host_events(void) int lpc_get_next_host_event(void) { host_event_t ev; - int evt_idx = __builtin_ffs(lpc_host_events); + int evt_idx = __builtin_ffs(lpc_host_events); #ifdef CONFIG_HOST_EVENT64 if (evt_idx == 0) { @@ -175,7 +175,7 @@ static int lpc_post_sysjump_restore_mask(void) int size, version; prev_mask = (const host_event_t *)system_get_jump_tag(LPC_SYSJUMP_TAG, - &version, &size); + &version, &size); if (!prev_mask || size != sizeof(lpc_host_event_mask) || (version != LPC_SYSJUMP_VERSION && version != LPC_SYSJUMP_OLD_VERSION)) @@ -332,7 +332,7 @@ void host_set_events(host_event_t mask) HOST_EVENT_CPRINTS("event set", mask); if (!IS_ENABLED(CONFIG_ZTEST) && - (mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY))) + (mask & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY))) system_enter_manual_recovery(); host_events_atomic_or(&events, mask); @@ -347,8 +347,8 @@ void host_set_events(host_event_t mask) #error "Config error: MKBP must not be on top of host event" #endif host_events_send_mkbp_event(events); -#endif /* CONFIG_MKBP_EVENT */ -#endif /* !CONFIG_HOSTCMD_X86 */ +#endif /* CONFIG_MKBP_EVENT */ +#endif /* !CONFIG_HOSTCMD_X86 */ } void host_set_single_event(enum host_event_code event) @@ -391,7 +391,7 @@ void host_clear_events(host_event_t mask) #ifdef CONFIG_MKBP_EVENT host_events_send_mkbp_event(events); #endif -#endif /* !CONFIG_HOSTCMD_X86 */ +#endif /* !CONFIG_HOSTCMD_X86 */ } #ifndef CONFIG_HOSTCMD_X86 @@ -494,19 +494,21 @@ static int command_host_event(int argc, char **argv) HOST_EVENT_CCPRINTF("Events-B: ", events_copy_b); #ifdef CONFIG_HOSTCMD_X86 HOST_EVENT_CCPRINTF("SMI mask: ", - lpc_get_host_event_mask(LPC_HOST_EVENT_SMI)); + lpc_get_host_event_mask(LPC_HOST_EVENT_SMI)); HOST_EVENT_CCPRINTF("SCI mask: ", - lpc_get_host_event_mask(LPC_HOST_EVENT_SCI)); + lpc_get_host_event_mask(LPC_HOST_EVENT_SCI)); HOST_EVENT_CCPRINTF("Wake mask: ", - lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE)); - HOST_EVENT_CCPRINTF("Always report mask: ", - lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT)); + lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE)); + HOST_EVENT_CCPRINTF( + "Always report mask: ", + lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT)); #endif return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hostevent, command_host_event, - "[set | clear | clearb | smi | sci | wake | always_report] [mask]", - "Print / set host event state"); +DECLARE_CONSOLE_COMMAND( + hostevent, command_host_event, + "[set | clear | clearb | smi | sci | wake | always_report] [mask]", + "Print / set host event state"); /*****************************************************************************/ /* Host commands */ @@ -523,8 +525,7 @@ host_event_get_smi_mask(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK, - host_event_get_smi_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SMI_MASK, host_event_get_smi_mask, EC_VER_MASK(0)); static enum ec_status @@ -537,8 +538,7 @@ host_event_get_sci_mask(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK, - host_event_get_sci_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_SCI_MASK, host_event_get_sci_mask, EC_VER_MASK(0)); static enum ec_status @@ -551,8 +551,7 @@ host_event_get_wake_mask(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK, - host_event_get_wake_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_WAKE_MASK, host_event_get_wake_mask, EC_VER_MASK(0)); static enum ec_status @@ -563,8 +562,7 @@ host_event_set_smi_mask(struct host_cmd_handler_args *args) lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, p->mask); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK, - host_event_set_smi_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SMI_MASK, host_event_set_smi_mask, EC_VER_MASK(0)); static enum ec_status @@ -575,8 +573,7 @@ host_event_set_sci_mask(struct host_cmd_handler_args *args) lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, p->mask); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK, - host_event_set_sci_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_SCI_MASK, host_event_set_sci_mask, EC_VER_MASK(0)); static enum ec_status @@ -588,8 +585,7 @@ host_event_set_wake_mask(struct host_cmd_handler_args *args) active_wm_set_by_host = !!p->mask; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK, - host_event_set_wake_mask, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_SET_WAKE_MASK, host_event_set_wake_mask, EC_VER_MASK(0)); uint8_t lpc_is_active_wm_set_by_host(void) @@ -597,7 +593,7 @@ uint8_t lpc_is_active_wm_set_by_host(void) return active_wm_set_by_host; } -#endif /* CONFIG_HOSTCMD_X86 */ +#endif /* CONFIG_HOSTCMD_X86 */ static enum ec_status host_event_get_b(struct host_cmd_handler_args *args) { @@ -608,9 +604,7 @@ static enum ec_status host_event_get_b(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B, - host_event_get_b, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_GET_B, host_event_get_b, EC_VER_MASK(0)); static enum ec_status host_event_clear(struct host_cmd_handler_args *args) { @@ -619,9 +613,7 @@ static enum ec_status host_event_clear(struct host_cmd_handler_args *args) host_clear_events(p->mask); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR, - host_event_clear, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR, host_event_clear, EC_VER_MASK(0)); static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args) { @@ -630,8 +622,7 @@ static enum ec_status host_event_clear_b(struct host_cmd_handler_args *args) host_clear_events_b(p->mask); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B, - host_event_clear_b, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT_CLEAR_B, host_event_clear_b, EC_VER_MASK(0)); static enum ec_status host_event_action_get(struct host_cmd_handler_args *args) @@ -658,8 +649,8 @@ static enum ec_status host_event_action_get(struct host_cmd_handler_args *args) r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI); break; case EC_HOST_EVENT_ALWAYS_REPORT_MASK: - r->value = lpc_get_host_event_mask - (LPC_HOST_EVENT_ALWAYS_REPORT); + r->value = + lpc_get_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT); break; case EC_HOST_EVENT_ACTIVE_WAKE_MASK: r->value = lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE); @@ -704,7 +695,7 @@ static enum ec_status host_event_action_set(struct host_cmd_handler_args *args) break; case EC_HOST_EVENT_ALWAYS_REPORT_MASK: lpc_set_host_event_mask(LPC_HOST_EVENT_ALWAYS_REPORT, - mask_value); + mask_value); break; case EC_HOST_EVENT_ACTIVE_WAKE_MASK: active_wm_set_by_host = !!mask_value; @@ -783,12 +774,11 @@ host_command_host_event(struct host_cmd_handler_args *args) } } -DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT, - host_command_host_event, +DECLARE_HOST_COMMAND(EC_CMD_HOST_EVENT, host_command_host_event, EC_VER_MASK(0)); -#define LAZY_WAKE_MASK_SYSJUMP_TAG 0x4C4D /* LM - Lazy Mask*/ -#define LAZY_WAKE_MASK_HOOK_VERSION 1 +#define LAZY_WAKE_MASK_SYSJUMP_TAG 0x4C4D /* LM - Lazy Mask*/ +#define LAZY_WAKE_MASK_HOOK_VERSION 1 #ifdef CONFIG_HOSTCMD_X86 int get_lazy_wake_mask(enum power_state state, host_event_t *mask) @@ -818,8 +808,7 @@ int get_lazy_wake_mask(enum power_state state, host_event_t *mask) static void preserve_lazy_wm(void) { system_add_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG, - LAZY_WAKE_MASK_HOOK_VERSION, - sizeof(lazy_wm), + LAZY_WAKE_MASK_HOOK_VERSION, sizeof(lazy_wm), &lazy_wm); } DECLARE_HOOK(HOOK_SYSJUMP, preserve_lazy_wm, HOOK_PRIO_DEFAULT); @@ -829,9 +818,8 @@ static void restore_lazy_wm(void) const struct lazy_wake_masks *wm_state; int version, size; - wm_state = (const struct lazy_wake_masks *) - system_get_jump_tag(LAZY_WAKE_MASK_SYSJUMP_TAG, - &version, &size); + wm_state = (const struct lazy_wake_masks *)system_get_jump_tag( + LAZY_WAKE_MASK_SYSJUMP_TAG, &version, &size); if (wm_state && (version == LAZY_WAKE_MASK_HOOK_VERSION) && (size == sizeof(lazy_wm))) { -- cgit v1.2.1 From 9cd4efe20a024936dd45beb3fcfffb5e3a2ff263 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:38 -0600 Subject: zephyr/shim/chip/npcx/include/system_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53a878319e615355e127ec46fa3a587de1eed8c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728331 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/include/system_chip.h | 40 ++++++++++++++--------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/zephyr/shim/chip/npcx/include/system_chip.h b/zephyr/shim/chip/npcx/include/system_chip.h index c77c2a8338..f446d6b634 100644 --- a/zephyr/shim/chip/npcx/include/system_chip.h +++ b/zephyr/shim/chip/npcx/include/system_chip.h @@ -6,24 +6,24 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) /* TODO(b:179900857) Clean this up too */ #undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) /*****************************************************************************/ /* Memory mapping */ -#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define CONFIG_LPRAM_BASE 0x40001400 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) /* * Region assignment. 7 as the highest, a higher index has a higher priority. @@ -35,18 +35,18 @@ * made mutually exclusive. */ enum mpu_region { - REGION_DATA_RAM = 0, /* For internal data RAM */ - REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ - REGION_CODE_RAM = 2, /* For internal code RAM */ - REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ - REGION_STORAGE = 4, /* For mapped internal storage */ - REGION_STORAGE2 = 5, /* Second region for unaligned size */ - REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ - REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ + REGION_DATA_RAM = 0, /* For internal data RAM */ + REGION_DATA_RAM2 = 1, /* Second region for unaligned size */ + REGION_CODE_RAM = 2, /* For internal code RAM */ + REGION_CODE_RAM2 = 3, /* Second region for unaligned size */ + REGION_STORAGE = 4, /* For mapped internal storage */ + REGION_STORAGE2 = 5, /* Second region for unaligned size */ + REGION_DATA_RAM_TEXT = 6, /* Exempt region of data RAM */ + REGION_CHIP_RESERVED = 7, /* Reserved for use in chip/ */ /* only for chips with MPU supporting 16 regions */ - REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ - REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ - REGION_ROLLBACK = 10, /* For rollback */ + REGION_UNCACHED_RAM = 8, /* For uncached data RAM */ + REGION_UNCACHED_RAM2 = 9, /* Second region for unaligned size */ + REGION_ROLLBACK = 10, /* For rollback */ }; /* -- cgit v1.2.1 From efcb45664d7f5810c09176a5527dbeb72713ebc3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:58 -0600 Subject: test/powerdemo.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0566ee2b1dc0e110f494214ff2f48e9a0862ca44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730517 Reviewed-by: Jeremy Bettis --- test/powerdemo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/powerdemo.h b/test/powerdemo.h index 17ed482042..0b77cc0a0a 100644 --- a/test/powerdemo.h +++ b/test/powerdemo.h @@ -13,4 +13,4 @@ /* Initializes the module. */ int power_demo_init(void); -#endif /* __TEST_POWERDEMO_H */ +#endif /* __TEST_POWERDEMO_H */ -- cgit v1.2.1 From cd47201f32cad0f9c43b394627fec7e851a9df01 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:04 -0600 Subject: baseboard/brask/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37a5db8c62d98fd7c936c116f5e7aa63fdcef583 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727858 Reviewed-by: Jeremy Bettis --- baseboard/brask/cbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/brask/cbi.c b/baseboard/brask/cbi.c index 038a491f05..cee5755b2d 100644 --- a/baseboard/brask/cbi.c +++ b/baseboard/brask/cbi.c @@ -10,8 +10,8 @@ #include "cros_board_info.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) static uint8_t board_id; -- cgit v1.2.1 From ae8cde5bac796e186c5497ca46bdebcd5b8cc737 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:18 -0600 Subject: board/driblee/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I267b7d9dd20ac6d9c80fb9a2fee473193ada029e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728262 Reviewed-by: Jeremy Bettis --- board/driblee/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/driblee/usb_pd_policy.c b/board/driblee/usb_pd_policy.c index 19dd01d37b..18fada590e 100644 --- a/board/driblee/usb_pd_policy.c +++ b/board/driblee/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/charger/isl923x_public.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From e78db01b7c1aba297afd232ba4c22f11da25420e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:40 -0600 Subject: board/homestar/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2df28345a3d3934cf3233d14ccfc24c7c65ada24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728325 Reviewed-by: Jeremy Bettis --- board/homestar/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/homestar/usbc_config.c b/board/homestar/usbc_config.c index aac136415d..73666d087c 100644 --- a/board/homestar/usbc_config.c +++ b/board/homestar/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 1997c1a079e409afb5fa42123664e6b37b9c227b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:55 -0600 Subject: include/i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic23f086c835ab80c6add9fff11b1af6a623d9729 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730283 Reviewed-by: Jeremy Bettis --- include/i2c.h | 181 +++++++++++++++++++++++----------------------------------- 1 file changed, 72 insertions(+), 109 deletions(-) diff --git a/include/i2c.h b/include/i2c.h index c799b9599d..b4517e730e 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -34,15 +34,15 @@ * used here and in motion_sense to give specific meaning to the * address that is pertinent to its use. */ -#define I2C_ADDR_MASK 0x03FF -#define I2C_FLAG_PEC BIT(13) -#define I2C_FLAG_BIG_ENDIAN BIT(14) +#define I2C_ADDR_MASK 0x03FF +#define I2C_FLAG_PEC BIT(13) +#define I2C_FLAG_BIG_ENDIAN BIT(14) /* BIT(15) SPI_FLAG - used in motion_sense to overload address */ -#define I2C_FLAG_ADDR_IS_SPI BIT(15) +#define I2C_FLAG_ADDR_IS_SPI BIT(15) -#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags) & I2C_ADDR_MASK) -#define I2C_USE_PEC(addr_flags) ((addr_flags) & I2C_FLAG_PEC) -#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags) & I2C_FLAG_BIG_ENDIAN) +#define I2C_STRIP_FLAGS(addr_flags) ((addr_flags)&I2C_ADDR_MASK) +#define I2C_USE_PEC(addr_flags) ((addr_flags)&I2C_FLAG_PEC) +#define I2C_IS_BIG_ENDIAN(addr_flags) ((addr_flags)&I2C_FLAG_BIG_ENDIAN) /* * All 7-bit addresses in the following formats @@ -51,8 +51,8 @@ * are reserved for various purposes. Valid 7-bit client adderesses start at * 0x08 and end at 0x77 inclusive. */ -#define I2C_FIRST_VALID_ADDR 0x08 -#define I2C_LAST_VALID_ADDR 0x77 +#define I2C_FIRST_VALID_ADDR 0x08 +#define I2C_LAST_VALID_ADDR 0x77 /* * Max data size for a version 3 request/response packet. This is @@ -67,7 +67,7 @@ #define I2C_RESPONSE_HEADER_SIZE 2 /* This port allows changing speed at runtime */ -#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0) +#define I2C_PORT_FLAG_DYNAMIC_SPEED BIT(0) /* * Supported I2C CLK frequencies. @@ -85,13 +85,10 @@ enum i2c_freq { * MASK_SET will OR the mask into the old value * MASK_CLR will AND the ~mask from the old value */ -enum mask_update_action { - MASK_CLR, - MASK_SET -}; +enum mask_update_action { MASK_CLR, MASK_SET }; struct i2c_info_t { - uint16_t port; /* Physical port for device */ + uint16_t port; /* Physical port for device */ uint16_t addr_flags; }; @@ -99,17 +96,16 @@ struct i2c_port_t; /* forward declaration */ struct i2c_drv { int (*xfer)(const struct i2c_port_t *i2c_port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, + const uint16_t addr_flags, const uint8_t *out, int out_size, uint8_t *in, int in_size, int flags); }; /* Data structure to define I2C port configuration. */ struct i2c_port_t { - int port; /* Port */ + int port; /* Port */ #ifndef CONFIG_ZEPHYR - const char *name; /* Port name */ - int kbps; /* Speed in kbps */ + const char *name; /* Port name */ + int kbps; /* Speed in kbps */ enum gpio_signal scl; /* Port SCL GPIO line */ enum gpio_signal sda; /* Port SDA GPIO line */ #endif /* CONFIG_ZEPHYR */ @@ -118,7 +114,7 @@ struct i2c_port_t { int (*passthru_allowed)(const struct i2c_port_t *port, uint16_t addr_flags); const struct i2c_drv *drv; - uint16_t flags; /* I2C_PORT_FLAG_* flags */ + uint16_t flags; /* I2C_PORT_FLAG_* flags */ }; extern const struct i2c_port_t i2c_ports[]; @@ -126,27 +122,25 @@ extern const unsigned int i2c_ports_used; #ifdef CONFIG_CMD_I2C_STRESS_TEST struct i2c_test_reg_info { - int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */ - int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */ - int write_reg; /* Read/Write reg which doesn't impact the system */ + int read_reg; /* Read register (WHO_AM_I, DEV_ID, MAN_ID) */ + int read_val; /* Expected val (WHO_AM_I, DEV_ID, MAN_ID) */ + int write_reg; /* Read/Write reg which doesn't impact the system */ }; struct i2c_test_results { - int read_success; /* Successful read count */ - int read_fail; /* Read fail count */ + int read_success; /* Successful read count */ + int read_fail; /* Read fail count */ int write_success; /* Successful write count */ - int write_fail; /* Write fail count */ + int write_fail; /* Write fail count */ }; /* Data structure to define I2C test configuration. */ struct i2c_stress_test_dev { struct i2c_test_reg_info reg_info; struct i2c_test_results test_results; - int (*i2c_read)(const int port, - const uint16_t addr_flags, + int (*i2c_read)(const int port, const uint16_t addr_flags, const int reg, int *data); - int (*i2c_write)(const int port, - const uint16_t addr_flags, + int (*i2c_write)(const int port, const uint16_t addr_flags, const int reg, int data); int (*i2c_read_dev)(const int reg, int *data); int (*i2c_write_dev)(const int reg, int data); @@ -166,15 +160,15 @@ extern const int i2c_test_dev_used; * Data structure to define I2C Parameters for a command */ struct i2c_cmd_desc_t { - uint8_t port; /* I2C port */ - uint16_t addr_flags; /* Peripheral address and flags */ - uint8_t cmd; /* command, only valid on write operations */ + uint8_t port; /* I2C port */ + uint16_t addr_flags; /* Peripheral address and flags */ + uint8_t cmd; /* command, only valid on write operations */ }; /* Flags for i2c_xfer_unlocked() */ -#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */ -#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */ -#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */ +#define I2C_XFER_START BIT(0) /* Start smbus session from idle state */ +#define I2C_XFER_STOP BIT(1) /* Terminate smbus session with stop bit */ +#define I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) /* One transaction */ /** * Transmit one block of raw data, then receive one block of raw data. However, @@ -190,10 +184,8 @@ struct i2c_cmd_desc_t { * @param in_size Number of bytes to receive * @return EC_SUCCESS, or non-zero if error. */ -int i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size); +int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size); /** * Same as i2c_xfer, but the bus is not implicitly locked. It must be called @@ -201,10 +193,9 @@ int i2c_xfer(const int port, * * @param flags Flags (see I2C_XFER_* above) */ -int i2c_xfer_unlocked(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int i2c_xfer_unlocked(const int port, const uint16_t addr_flags, + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); #define I2C_LINE_SCL_HIGH BIT(0) #define I2C_LINE_SDA_HIGH BIT(1) @@ -305,54 +296,46 @@ void i2c_set_timeout(int port, uint32_t timeout); * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_read32(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read32(const int port, const uint16_t addr_flags, int offset, + int *data); /** * Write a 32-bit register to the peripheral at 7-bit peripheral address * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_write32(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write32(const int port, const uint16_t addr_flags, int offset, + int data); /** * Read a 16-bit register from the peripheral at 7-bit peripheral address * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_read16(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read16(const int port, const uint16_t addr_flags, int offset, + int *data); /** * Write a 16-bit register to the peripheral at 7-bit peripheral address * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_write16(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write16(const int port, const uint16_t addr_flags, int offset, + int data); /** * Read an 8-bit register from the peripheral at 7-bit peripheral address * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_read8(const int port, - const uint16_t addr_flags, - int offset, int *data); +int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data); /** * Write an 8-bit register to the peripheral at 7-bit peripheral address * , at the specified 8-bit in the peripheral's address * space. */ -int i2c_write8(const int port, - const uint16_t addr_flags, - int offset, int data); +int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data); /** * Read, modify, write an i2c register to the peripheral at 7-bit peripheral @@ -362,17 +345,11 @@ int i2c_write8(const int port, * is the same as the original value of the register, the write will not be * performed. */ -int i2c_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t mask, - const enum mask_update_action action); +int i2c_update8(const int port, const uint16_t addr_flags, const int offset, + const uint8_t mask, const enum mask_update_action action); -int i2c_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t mask, - const enum mask_update_action action); +int i2c_update16(const int port, const uint16_t addr_flags, const int offset, + const uint16_t mask, const enum mask_update_action action); /** * Read, modify, write field of an i2c register to the peripheral at 7-bit @@ -383,48 +360,40 @@ int i2c_update16(const int port, * new value is not the same as the original value, the new value will be * written back out to the device, otherwise no write will be performed. */ -int i2c_field_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t field_mask, +int i2c_field_update8(const int port, const uint16_t addr_flags, + const int offset, const uint8_t field_mask, const uint8_t set_value); -int i2c_field_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t field_mask, +int i2c_field_update16(const int port, const uint16_t addr_flags, + const int offset, const uint16_t field_mask, const uint16_t set_value); /** * Read one or two bytes data from the peripheral at 7-bit peripheral address * , at 16-bit in the peripheral's address space. */ -int i2c_read_offset16(const int port, - const uint16_t addr_flags, +int i2c_read_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int *data, int len); /** * Write one or two bytes data to the peripheral at 7-bit peripheral address * , at 16-bit in the peripheral's address space. */ -int i2c_write_offset16(const int port, - const uint16_t addr_flags, +int i2c_write_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int data, int len); /** * Read bytes block data from the peripheral at 7-bit peripheral address * * , at 16-bit in the peripheral's address space. */ -int i2c_read_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_read_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, uint8_t *data, int len); /** * Write bytes block data to the peripheral at 7-bit peripheral address * , at 16-bit in the peripheral's address space. */ -int i2c_write_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_write_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, const uint8_t *data, int len); /** @@ -448,9 +417,8 @@ int i2c_unwedge(int port); * * : the max length of receiving buffer */ -int i2c_read_sized_block(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int max_len, int *read_len); +int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int max_len, int *read_len); /** * Read ascii string using smbus read block protocol. @@ -462,27 +430,24 @@ int i2c_read_sized_block(const int port, * terminating 0. Similar to strlcpy, the terminating null is * always written into the output buffer. */ -int i2c_read_string(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int len); +int i2c_read_string(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int len); /** * Read a data block of 8-bit transfers from the peripheral at 7-bit * peripheral address , at the specified 8-bit in the * peripheral's address space. */ -int i2c_read_block(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int len); +int i2c_read_block(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int len); /** * Write a data block of 8-bit transfers to the peripheral at 7-bit * peripheral address , at the specified 8-bit in the * peripheral's address space. */ -int i2c_write_block(const int port, - const uint16_t addr_flags, - int offset, const uint8_t *data, int len); +int i2c_write_block(const int port, const uint16_t addr_flags, int offset, + const uint8_t *data, int len); /** * Convert port number to controller number, for multi-port controllers. @@ -548,8 +513,7 @@ int board_is_i2c_port_powered(int port); * @param addr_flags: Peripheral device address * */ -void i2c_start_xfer_notify(const int port, - const uint16_t addr_flags); +void i2c_start_xfer_notify(const int port, const uint16_t addr_flags); /** * Function to allow board to take any action after an i2c transaction on a @@ -560,8 +524,7 @@ void i2c_start_xfer_notify(const int port, * @param addr_flags: Peripheral device address * */ -void i2c_end_xfer_notify(const int port, - const uint16_t addr_flags); +void i2c_end_xfer_notify(const int port, const uint16_t addr_flags); /** * Defined in common/i2c_trace.c, used by i2c controller to notify tracing @@ -575,9 +538,9 @@ void i2c_end_xfer_notify(const int port, * @param in_size: size of data read * @param ret: return of i2c transaction (EC_SUCCESS or otherwise on failure) */ -void i2c_trace_notify(int port, uint16_t addr_flags, - const uint8_t *out_data, size_t out_size, - const uint8_t *in_data, size_t in_size, int ret); +void i2c_trace_notify(int port, uint16_t addr_flags, const uint8_t *out_data, + size_t out_size, const uint8_t *in_data, size_t in_size, + int ret); /** * Convert an enum i2c_freq constant to numeric frequency in kHz. @@ -636,4 +599,4 @@ const struct i2c_port_t *get_i2c_port(const int port); */ int i2c_get_physical_port(int enum_port); -#endif /* __CROS_EC_I2C_H */ +#endif /* __CROS_EC_I2C_H */ -- cgit v1.2.1 From 1a559914791182ac81210ab5d7316e90b2357390 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:38 -0600 Subject: board/marzipan/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff924c2950936ce11b3a286ded65feb214877ec9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728646 Reviewed-by: Jeremy Bettis --- board/marzipan/board.c | 176 +++++++++++++++++++------------------------------ 1 file changed, 67 insertions(+), 109 deletions(-) diff --git a/board/marzipan/board.c b/board/marzipan/board.c index e5e12a1afc..28bfe034b5 100644 --- a/board/marzipan/board.c +++ b/board/marzipan/board.c @@ -39,8 +39,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -91,10 +91,8 @@ __override struct keyboard_scan_config keyscan_config = { * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key); * as it still uses the legacy location (KSO_01/KSI_00). */ - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -105,41 +103,31 @@ __override struct keyboard_scan_config keyscan_config = { /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -147,37 +135,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -190,16 +163,12 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -271,29 +240,21 @@ enum base_accelgyro_type { }; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref_bmi160 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref_icm426xx = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref_bma255 = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref_kx022 = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -465,7 +426,7 @@ static void board_detect_motionsensor(void) /* Check lid accel chip */ ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS, - BMA2x2_CHIP_ID_ADDR, &val); + BMA2x2_CHIP_ID_ADDR, &val); if (ret) motion_sensors[LID_ACCEL] = kx022_lid_accel; @@ -478,10 +439,11 @@ static void board_detect_motionsensor(void) motion_sensors[BASE_GYRO] = icm426xx_base_gyro; } - base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) - ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160; - CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) - ? "ICM40608" : "BMI160"); + base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ? + BASE_GYRO_ICM426XX : + BASE_GYRO_BMI160; + CPRINTS("Base Accelgyro: %s", + (val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160"); } /* Initialize board. */ @@ -539,9 +501,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); /* Called on AP S0 -> S3 transition */ static void board_chipset_suspend(void) @@ -606,8 +568,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -635,7 +596,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -659,23 +619,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From fd6f50e613e62306d32e939434c1bc9bed83cf86 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:16 -0600 Subject: common/device_event.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2f33bab9a9571ddf6c79cdfb85adae882aaa12db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729621 Reviewed-by: Jeremy Bettis --- common/device_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/device_event.c b/common/device_event.c index 748a98ae8f..3b9a76c8e0 100644 --- a/common/device_event.c +++ b/common/device_event.c @@ -15,7 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_EVENTS, outstr) -#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ## args) +#define CPRINTS(format, args...) cprints(CC_EVENTS, format, ##args) static atomic_t device_current_events; static atomic_t device_enabled_events; -- cgit v1.2.1 From 06d522a4ef01706cc22bf46876896be2d0990f7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:03 -0600 Subject: board/garg/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id31ddabdddd0ad0bf8de522b7414e41a808ca718 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728390 Reviewed-by: Jeremy Bettis --- board/garg/board.h | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/board/garg/board.h b/board/garg/board.h index 638c8c93a0..e35baef6c8 100644 --- a/board/garg/board.h +++ b/board/garg/board.h @@ -19,16 +19,16 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* I2C bus configuraiton */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define CONFIG_LED_COMMON /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ -#define CONFIG_ACCELGYRO_BMI260 /* 3rd Base accel */ -#define CONFIG_ACCELGYRO_ICM426XX /* 2nd Base accel */ -#define CONFIG_SYNC /* Camera VSYNC */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_BMI260 /* 3rd Base accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* 2nd Base accel */ +#define CONFIG_SYNC /* Camera VSYNC */ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Sensors without hardware FIFO are in forced mode */ @@ -42,8 +42,7 @@ #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -68,10 +67,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -83,13 +82,7 @@ enum temp_sensor_id { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - VSYNC, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 1c86bf4cf38a803a3f7cedb700d2c67ab5bf8844 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:21 -0600 Subject: board/haboki/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib954b2bd465f336894823672a44d55e77bbafb16 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728442 Reviewed-by: Jeremy Bettis --- board/haboki/board.c | 176 +++++++++++++++++++++++---------------------------- 1 file changed, 80 insertions(+), 96 deletions(-) diff --git a/board/haboki/board.c b/board/haboki/board.c index 3a33787603..d3a57be9f4 100644 --- a/board/haboki/board.c +++ b/board/haboki/board.c @@ -41,7 +41,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -164,48 +164,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -279,17 +267,13 @@ static struct accelgyro_saved_data_t g_bma253_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -480,8 +464,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -489,11 +473,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -504,11 +488,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -613,33 +597,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -669,9 +651,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -690,14 +671,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 17e54b581f14310193d91063fa963de310b6b710 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:10 -0600 Subject: zephyr/shim/include/zephyr_gpio_signal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9b0b1c50c0ff65373d37f7006a16f68cae90c44f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730857 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_gpio_signal.h | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h index 8949826987..3f56ccf259 100644 --- a/zephyr/shim/include/zephyr_gpio_signal.h +++ b/zephyr/shim/include/zephyr_gpio_signal.h @@ -34,20 +34,19 @@ * a GPIO signal name from either the enum-name or a * unique name generated using the DTS ordinal. */ -#define GPIO_SIGNAL_NAME(id) \ - COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \ - (GPIO_SIGNAL_NAME_FROM_ENUM(id)), \ - (GPIO_SIGNAL_NAME_FROM_ORD(id ## _ORD))) - -#define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id) -#define GPIO_SIGNAL_WITH_COMMA(id) \ - GPIO_SIGNAL(id), +#define GPIO_SIGNAL_NAME(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \ + (GPIO_SIGNAL_NAME_FROM_ENUM(id)), \ + (GPIO_SIGNAL_NAME_FROM_ORD(id##_ORD))) + +#define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id) +#define GPIO_SIGNAL_WITH_COMMA(id) GPIO_SIGNAL(id), enum gpio_signal { GPIO_UNIMPLEMENTED = -1, #if DT_NODE_EXISTS(DT_PATH(named_gpios)) DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_SIGNAL_WITH_COMMA) #endif - GPIO_COUNT, + GPIO_COUNT, GPIO_LIMIT = 0x0FFF, IOEX_SIGNAL_START = GPIO_LIMIT + 1, @@ -118,8 +117,8 @@ BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT); */ struct gpio_dt_spec; -#define GPIO_DT_PTR_DECL(id) extern const struct gpio_dt_spec * const \ - GPIO_DT_NAME(GPIO_SIGNAL(id)); +#define GPIO_DT_PTR_DECL(id) \ + extern const struct gpio_dt_spec *const GPIO_DT_NAME(GPIO_SIGNAL(id)); DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_PTR_DECL) @@ -127,14 +126,13 @@ DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_PTR_DECL) #endif /* DT_NODE_EXISTS(DT_PATH(named_gpios)) */ - #define IOEXPANDER_ID_EXPAND(id) ioex_chip_##id #define IOEXPANDER_ID(id) IOEXPANDER_ID_EXPAND(id) #define IOEXPANDER_ID_FROM_INST_WITH_COMMA(id) IOEXPANDER_ID(id), enum ioexpander_id { DT_FOREACH_STATUS_OKAY(cros_ioex_chip, - IOEXPANDER_ID_FROM_INST_WITH_COMMA) - CONFIG_IO_EXPANDER_PORT_COUNT + IOEXPANDER_ID_FROM_INST_WITH_COMMA) + CONFIG_IO_EXPANDER_PORT_COUNT }; /** -- cgit v1.2.1 From a0088f524f5215a62a9484de78f60bfa7e4137c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:02 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I357a0172467701f4687a23f4ad94fcdf67ae5c08 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730920 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c index 375e93c74f..f7d34b5712 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c @@ -20,8 +20,7 @@ static int check_pch_out_of_suspend(void) /* * Wait for SLP_SUS deasserted. */ - ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS, - 0, + ret = power_wait_mask_signals_timeout(IN_PCH_SLP_SUS, 0, IN_PCH_SLP_SUS_WAIT_TIME_MS); if (ret == 0) { LOG_DBG("SLP_SUS now %d", power_signal_get(PWR_SLP_SUS)); @@ -42,10 +41,10 @@ int all_sys_pwrgd_handler(void) k_msleep(AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout)); if (power_signal_get(PWR_DSW_PWROK) == 0) { - /* Todo: Remove workaround for the retry - * without this change the system hits G3 as it detects - * ALL_SYS_PWRGD as 0 and then 1 as a glitch - */ + /* Todo: Remove workaround for the retry + * without this change the system hits G3 as it detects + * ALL_SYS_PWRGD as 0 and then 1 as a glitch + */ while (power_signal_get(PWR_ALL_SYS_PWRGD) == 0) { if (++retry > 2) { LOG_ERR("PG_EC_ALL_SYS_PWRGD not ok"); -- cgit v1.2.1 From 49e01a4838c00b4b570ca4494869fdcbe535eb6e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:23 -0600 Subject: board/felwinter/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id73558c9a97bacb5613398afdff3342e883b25a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728360 Reviewed-by: Jeremy Bettis --- board/felwinter/sensors.c | 58 ++++++++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/board/felwinter/sensors.c b/board/felwinter/sensors.c index fd3f721947..6e9e956245 100644 --- a/board/felwinter/sensors.c +++ b/board/felwinter/sensors.c @@ -46,18 +46,14 @@ K_MUTEX_DEFINE(g_base_accel_mutex); static struct stprivate_data g_lis2dw12_data; static struct lsm6dso_data lsm6dso_data; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* TODO(b/184779743): verify orientation matrix */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -146,24 +142,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_FAN] = { - .name = "FAN", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_FAN - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_FAN] = { .name = "FAN", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_FAN }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -177,8 +167,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -207,8 +197,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(60), \ [EC_TEMP_THRESH_HALT] = C_TO_K(70), \ @@ -221,8 +211,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; } __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From dd9d64a7626139783ae29a6683e59608d42634b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:02 -0600 Subject: board/willow/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibae6eeaf463d4e64dd187e10d0747da0a7176321 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729131 Reviewed-by: Jeremy Bettis --- board/willow/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/willow/board.h b/board/willow/board.h index 5bfc06d615..70b384c685 100644 --- a/board/willow/board.h +++ b/board/willow/board.h @@ -50,7 +50,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -67,20 +67,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_BATTERY 2 +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BATTERY 2 /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From bbbcb4ee1bc1e46ae557b41230ba93818ed07af2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:34 -0600 Subject: board/chronicler/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib91e3f7fda3017b146066b342933f992e9cacaf2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728148 Reviewed-by: Jeremy Bettis --- board/chronicler/led.c | 53 +++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 26 deletions(-) diff --git a/board/chronicler/led.c b/board/chronicler/led.c index dfa7fefa1b..af4d401e70 100644 --- a/board/chronicler/led.c +++ b/board/chronicler/led.c @@ -21,10 +21,10 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -#define LED_CYCLE_TIME_MS (2 * 1000) +#define LED_CYCLE_TIME_MS (2 * 1000) #define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / HOOK_TICK_INTERVAL_MS) -#define LED_ON_TIME_MS (1 * 1000) -#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1 * 1000) +#define LED_ON_TICKS (LED_ON_TIME_MS / HOOK_TICK_INTERVAL_MS) const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, @@ -37,22 +37,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - RIGHT_PORT = 0, - LEFT_PORT -}; +enum led_port { RIGHT_PORT = 0, LEFT_PORT }; static void led_set_color_battery(enum led_port port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L : - GPIO_C1_CHARGE_LED_AMBER_L); + GPIO_C1_CHARGE_LED_AMBER_L); white_led = (port == RIGHT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L : - GPIO_C1_CHARGE_LED_WHITE_L); + GPIO_C1_CHARGE_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -124,10 +121,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -144,14 +141,13 @@ static void led_set_battery(void) * LEDs to indicate system suspend without charging state. */ if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - + charge_get_state() != PWR_STATE_CHARGE) { suspend_ticks++; - led_set_color_battery(RIGHT_PORT, suspend_ticks & 0x4 ? - LED_WHITE : LED_OFF); - led_set_color_battery(LEFT_PORT, suspend_ticks & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF); + led_set_color_battery( + LEFT_PORT, suspend_ticks & 0x4 ? LED_WHITE : LED_OFF); return; } @@ -165,9 +161,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } @@ -176,17 +175,19 @@ static void led_set_battery(void) led_set_color_battery(LEFT_PORT, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From de883ab4a293c6bbc3e69c8415a451df0b2b7979 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:29 -0600 Subject: driver/accelgyro_bmi3xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14ef117514aa2ce9b21f48a1c09ddbd4ff10ed26 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729915 Reviewed-by: Jeremy Bettis --- driver/accelgyro_bmi3xx.c | 236 +++++++++++++++++++++++----------------------- 1 file changed, 116 insertions(+), 120 deletions(-) diff --git a/driver/accelgyro_bmi3xx.c b/driver/accelgyro_bmi3xx.c index 6c14768708..cd17004810 100644 --- a/driver/accelgyro_bmi3xx.c +++ b/driver/accelgyro_bmi3xx.c @@ -28,15 +28,15 @@ #endif #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) /* Sensor definition */ STATIC_IF(CONFIG_BMI_ORIENTATION_SENSOR) - void irq_set_orientation(struct motion_sensor_t *s); +void irq_set_orientation(struct motion_sensor_t *s); STATIC_IF(ACCELGYRO_BMI3XX_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; static inline int bmi3_read_n(const struct motion_sensor_t *s, const int reg, uint8_t *data_ptr, const int len) @@ -61,7 +61,7 @@ static void irq_set_orientation(struct motion_sensor_t *s) uint8_t orient_data; enum motionsensor_orientation orientation = - MOTIONSENSE_ORIENTATION_UNKNOWN; + MOTIONSENSE_ORIENTATION_UNKNOWN; RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_EVENT_EXT, reg_data, 4)); @@ -94,7 +94,7 @@ static void irq_set_orientation(struct motion_sensor_t *s) } } -#endif /* CONFIG_BMI_ORIENTATION_SENSOR */ +#endif /* CONFIG_BMI_ORIENTATION_SENSOR */ /* * bmi3xx_interrupt - called when the sensor activates the interrupt line. @@ -121,14 +121,14 @@ static int enable_fifo(const struct motion_sensor_t *s, int enable) if (s->type == MOTIONSENSE_TYPE_ACCEL) reg_data[3] |= BMI3_FIFO_ACC_EN; else - reg_data[3] |= BMI3_FIFO_GYR_EN; + reg_data[3] |= BMI3_FIFO_GYR_EN; data->flags |= 1 << (s->type + BMI_FIFO_FLAG_OFFSET); } else { if (s->type == MOTIONSENSE_TYPE_ACCEL) reg_data[3] &= ~BMI3_FIFO_ACC_EN; else - reg_data[3] &= ~BMI3_FIFO_GYR_EN; + reg_data[3] &= ~BMI3_FIFO_GYR_EN; data->flags &= ~(1 << (s->type + BMI_FIFO_FLAG_OFFSET)); } @@ -139,7 +139,7 @@ static int enable_fifo(const struct motion_sensor_t *s, int enable) static int config_interrupt(const struct motion_sensor_t *s) { int ret; - uint8_t reg_data[6] = {0}; + uint8_t reg_data[6] = { 0 }; if (s->type != MOTIONSENSE_TYPE_ACCEL) return EC_SUCCESS; @@ -162,8 +162,8 @@ static int config_interrupt(const struct motion_sensor_t *s) reg_data[5] = BMI3_SET_BITS(reg_data[5], BMI3_FFULL_INT, BMI3_INT1); if (IS_ENABLED(CONFIG_BMI_ORIENTATION_SENSOR)) { /* Map orientation to INT1 pin */ - reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT, - BMI3_INT1); + reg_data[2] = + BMI3_SET_BITS(reg_data[2], BMI3_ORIENT_INT, BMI3_INT1); } ret = bmi3_write_n(s, BMI3_REG_INT_MAP1, ®_data[2], 4); @@ -186,8 +186,8 @@ static int config_interrupt(const struct motion_sensor_t *s) reg_data[2] = BMI3_SET_BIT_POS0(reg_data[2], BMI3_INT1_LVL, BMI3_INT_ACTIVE_LOW); - reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD, - BMI3_INT_PUSH_PULL); + reg_data[2] = + BMI3_SET_BITS(reg_data[2], BMI3_INT1_OD, BMI3_INT_PUSH_PULL); reg_data[2] = BMI3_SET_BITS(reg_data[2], BMI3_INT1_OUTPUT_EN, BMI3_INT_OUTPUT_ENABLE); @@ -287,17 +287,17 @@ static void bmi3_parse_fifo_data(struct motion_sensor_t *s, rotate(v, *sens_output->rot_standard_ref, v); if (IS_ENABLED(CONFIG_ACCEL_FIFO)) { - struct ec_response_motion_sensor_data vect; + struct ec_response_motion_sensor_data + vect; vect.data[X] = v[X]; vect.data[Y] = v[Y]; vect.data[Z] = v[Z]; vect.flags = 0; - vect.sensor_num = sens_output - - motion_sensors; - motion_sense_fifo_stage_data(&vect, - sens_output, 3, - last_ts); + vect.sensor_num = + sens_output - motion_sensors; + motion_sense_fifo_stage_data( + &vect, sens_output, 3, last_ts); } else { motion_sense_push_raw_xyz(sens_output); } @@ -313,8 +313,7 @@ static void bmi3_parse_fifo_data(struct motion_sensor_t *s, * For now, we just print out. We should set a bitmask motion sense code will * act upon. */ -static int irq_handler(struct motion_sensor_t *s, - uint32_t *event) +static int irq_handler(struct motion_sensor_t *s, uint32_t *event) { bool has_read_fifo = false; uint16_t int_status[2]; @@ -335,15 +334,15 @@ static int irq_handler(struct motion_sensor_t *s, irq_set_orientation(s); if ((int_status[1] & - (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0) + (BMI3_INT_STATUS_FWM | BMI3_INT_STATUS_FFULL)) == 0) break; /* Get the FIFO fill level in words */ RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_FILL_LVL, (uint8_t *)reg_data, 4)); - reg_data[1] = BMI3_GET_BIT_POS0(reg_data[1], - BMI3_FIFO_FILL_LVL); + reg_data[1] = + BMI3_GET_BIT_POS0(reg_data[1], BMI3_FIFO_FILL_LVL); /* Add space for the initial 16bit read. */ fifo_frame.available_fifo_len = reg_data[1] + 1; @@ -354,16 +353,15 @@ static int irq_handler(struct motion_sensor_t *s, */ if (fifo_frame.available_fifo_len > ARRAY_SIZE(fifo_frame.data)) CPRINTS("unexpected large FIFO: %d", - fifo_frame.available_fifo_len); + fifo_frame.available_fifo_len); fifo_frame.available_fifo_len = MIN(fifo_frame.available_fifo_len, - ARRAY_SIZE(fifo_frame.data)); + ARRAY_SIZE(fifo_frame.data)); /* Read FIFO data */ - RETURN_ERROR(bmi3_read_n(s, BMI3_REG_FIFO_DATA, - (uint8_t *)fifo_frame.data, - fifo_frame.available_fifo_len * - sizeof(uint16_t))); + RETURN_ERROR(bmi3_read_n( + s, BMI3_REG_FIFO_DATA, (uint8_t *)fifo_frame.data, + fifo_frame.available_fifo_len * sizeof(uint16_t))); bmi3_parse_fifo_data(s, &fifo_frame, last_interrupt_timestamp); has_read_fifo = true; @@ -387,20 +385,21 @@ static int reset_offset(const struct motion_sensor_t *s, uint8_t offset_en) uint8_t reg_data[4] = { 0 }; /* Reset the existing offset values by setting the bits in DMA*/ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, - offset_sel, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, offset_sel, 2)); reg_data[0] = offset_en; reg_data[1] = 0; - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - reg_data, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 2)); /* Update the offset change to the sensor engine */ - reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_LOW_BYTE); + reg_data[0] = + (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & BMI3_SET_LOW_BYTE); reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_HIGH_BYTE) >> 8); + BMI3_SET_HIGH_BYTE) >> + 8); RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2)); /* Delay time for offset update */ @@ -409,9 +408,9 @@ static int reset_offset(const struct motion_sensor_t *s, uint8_t offset_en) /* Read the configuration from the feature engine register */ RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4)); - if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) - && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) - == BMI3_FEATURE_IO_1_NO_ERROR)) { + if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) && + ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) == + BMI3_FEATURE_IO_1_NO_ERROR)) { return EC_SUCCESS; } @@ -448,18 +447,17 @@ static int write_gyro_offset(const struct motion_sensor_t *s, int *val) uint8_t offset_sel[2] = { BMI3_REG_UGAIN_OFF_SEL, 0 }; /* Enable user gain/offset update*/ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, - offset_sel, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, offset_sel, 2)); reg_data[0] = 0; reg_data[1] = 0; - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - reg_data, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 2)); /* * Set the user gyro offset base address to feature engine * transmission address to start DMA transaction */ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, - base_addr, 2)); + RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2)); reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE); reg_data[1] = (uint8_t)((val[0] & 0x0300) >> 8); @@ -469,14 +467,15 @@ static int write_gyro_offset(const struct motion_sensor_t *s, int *val) reg_data[5] = (uint8_t)((val[2] & 0x0300) >> 8); /* Set the configuration to the feature engine register */ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - reg_data, 6)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 6)); /* Update the offset to the sensor engine */ - reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_LOW_BYTE); + reg_data[0] = + (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & BMI3_SET_LOW_BYTE); reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_HIGH_BYTE) >> 8); + BMI3_SET_HIGH_BYTE) >> + 8); RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2)); msleep(OFFSET_UPDATE_DELAY); @@ -484,9 +483,9 @@ static int write_gyro_offset(const struct motion_sensor_t *s, int *val) /* Read the configuration from the feature engine register */ RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4)); - if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) - && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) - == BMI3_FEATURE_IO_1_NO_ERROR)) { + if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) && + ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) == + BMI3_FEATURE_IO_1_NO_ERROR)) { return EC_SUCCESS; } @@ -501,7 +500,7 @@ int set_gyro_offset(const struct motion_sensor_t *s, intv3_t v) for (i = X; i <= Z; ++i) { val[i] = round_divide((int64_t)v[i] * BMI_OFFSET_GYRO_DIV_MDS, - BMI_OFFSET_GYRO_MULTI_MDS); + BMI_OFFSET_GYRO_MULTI_MDS); if (val[i] > 511) val[i] = 511; if (val[i] < -512) @@ -559,21 +558,20 @@ static int write_accel_offsets(const struct motion_sensor_t *s, int *val) { uint8_t base_addr[2] = { BMI3_ACC_OFFSET_ADDR, 0 }; uint8_t offset_sel[2] = { BMI3_REG_UGAIN_OFF_SEL, 0 }; - uint8_t reg_data[6] = {0}; + uint8_t reg_data[6] = { 0 }; /* Enable user gain/offset update*/ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, - offset_sel, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, offset_sel, 2)); reg_data[0] = 0; reg_data[1] = 0; - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - reg_data, 2)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 2)); /* * Set the user accel offset base address to feature engine * transmission address to start DMA transaction */ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, - base_addr, 2)); + RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2)); reg_data[0] = (uint8_t)(val[0] & BMI3_SET_LOW_BYTE); reg_data[1] = (uint8_t)((val[0] & 0x1F00) >> 8); @@ -583,15 +581,16 @@ static int write_accel_offsets(const struct motion_sensor_t *s, int *val) reg_data[5] = (uint8_t)((val[2] & 0x1F00) >> 8); /* Set the configuration to the feature engine register */ - RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - reg_data, 6)); + RETURN_ERROR( + bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 6)); /* Update the offset to the sensor engine */ - reg_data[0] = (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_LOW_BYTE); + reg_data[0] = + (uint8_t)(BMI3_CMD_USR_GAIN_OFFS_UPDATE & BMI3_SET_LOW_BYTE); reg_data[1] = (uint8_t)((BMI3_CMD_USR_GAIN_OFFS_UPDATE & - BMI3_SET_HIGH_BYTE) >> 8); + BMI3_SET_HIGH_BYTE) >> + 8); RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2)); @@ -600,9 +599,9 @@ static int write_accel_offsets(const struct motion_sensor_t *s, int *val) /* Read the configuration from the feature engine register */ RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_IO_1, reg_data, 4)); - if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) - && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) - == BMI3_FEATURE_IO_1_NO_ERROR)) { + if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) && + ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) == + BMI3_FEATURE_IO_1_NO_ERROR)) { return EC_SUCCESS; } @@ -610,7 +609,7 @@ static int write_accel_offsets(const struct motion_sensor_t *s, int *val) } int set_accel_offset(const struct motion_sensor_t *s, intv3_t v, - uint8_t reset_en) + uint8_t reset_en) { uint8_t reg_data[4] = { 0 }; uint8_t saved_conf[6] = { 0 }; @@ -655,7 +654,7 @@ int set_accel_offset(const struct motion_sensor_t *s, intv3_t v, static int wait_and_read_data(const struct motion_sensor_t *s, intv3_t accel_data) { - uint8_t reg_data[8] = {0}; + uint8_t reg_data[8] = { 0 }; /* Retry 5 times */ uint8_t try_cnt = FOC_TRY_COUNT; @@ -692,13 +691,12 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target, int sens_range) { intv3_t accel_data, offset; - int32_t delta_value[3] = {0, 0, 0}; + int32_t delta_value[3] = { 0, 0, 0 }; /* Variable to define count */ uint8_t i, loop, sample_count = 0; for (loop = 0; loop < BMI3_FOC_SAMPLE_LIMIT; loop++) { - RETURN_ERROR(wait_and_read_data(s, accel_data)); sample_count++; @@ -711,8 +709,10 @@ static int8_t perform_accel_foc(struct motion_sensor_t *s, int *target, /* The data is in LSB so -> [(LSB)*1000*range/2^15] (mdps | mg) */ for (i = X; i <= Z; ++i) { - offset[i] = (((int64_t)(delta_value[i] * 1000 * sens_range - / sample_count) >> 15) * -1); + offset[i] = (((int64_t)(delta_value[i] * 1000 * sens_range / + sample_count) >> + 15) * + -1); } rotate_inv(offset, *s->rot_standard_ref, offset); @@ -737,8 +737,8 @@ static int set_gyro_foc_config(struct motion_sensor_t *s) RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX, base_addr, 2)); /* Read the configuration from the feature engine register */ - RETURN_ERROR(bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, - 4)); + RETURN_ERROR( + bmi3_read_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, reg_data, 4)); /* Enable self calibration */ reg_data[2] |= 0x07; @@ -746,12 +746,12 @@ static int set_gyro_foc_config(struct motion_sensor_t *s) /* Set the configuration to the feature engine register */ RETURN_ERROR(bmi3_write_n(s, BMI3_FEATURE_ENGINE_DMA_TX_DATA, - ®_data[2], 2)); + ®_data[2], 2)); /* Trigger bmi3 gyro self calibration */ reg_data[0] = (uint8_t)(BMI3_CMD_SELF_CALIB & BMI3_SET_LOW_BYTE); - reg_data[1] = (uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE) - >> 8); + reg_data[1] = + (uint8_t)((BMI3_CMD_SELF_CALIB & BMI3_SET_HIGH_BYTE) >> 8); RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2)); @@ -771,9 +771,9 @@ static int get_calib_result(struct motion_sensor_t *s) switch (s->type) { case MOTIONSENSE_TYPE_ACCEL: - if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) - && ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) - == BMI3_FEATURE_IO_1_NO_ERROR)) { + if ((reg_data[3] & BMI3_UGAIN_OFFS_UPD_COMPLETE) && + ((reg_data[2] & BMI3_FEATURE_IO_1_ERROR_MASK) == + BMI3_FEATURE_IO_1_NO_ERROR)) { return EC_SUCCESS; } break; @@ -795,22 +795,21 @@ static int get_calib_result(struct motion_sensor_t *s) static int perform_calib(struct motion_sensor_t *s, int enable) { int ret; - intv3_t target = {0, 0, 0}; - uint8_t saved_conf[6] = {0}; + intv3_t target = { 0, 0, 0 }; + uint8_t saved_conf[6] = { 0 }; /* Sensor is configured to be in 16G range */ int sens_range = 16; /* Variable to set the accelerometer configuration value 50Hz for FOC */ - uint8_t acc_conf_data[2] = {BMI3_FOC_ACC_CONF_VAL_LSB, - BMI3_FOC_ACC_CONF_VAL_MSB}; + uint8_t acc_conf_data[2] = { BMI3_FOC_ACC_CONF_VAL_LSB, + BMI3_FOC_ACC_CONF_VAL_MSB }; if (!enable) return EC_SUCCESS; /* Get default configurations for the type of feature selected. */ - RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, - 6)); + RETURN_ERROR(bmi3_read_n(s, BMI3_REG_ACC_CONF, saved_conf, 6)); ret = bmi3_write_n(s, BMI3_REG_ACC_CONF, acc_conf_data, 2); if (ret) @@ -849,7 +848,6 @@ static int perform_calib(struct motion_sensor_t *s, int enable) goto end_calib; } - end_calib: /* Restore ACC_CONF before exiting */ RETURN_ERROR(bmi3_write_n(s, BMI3_REG_ACC_CONF, &saved_conf[2], 4)); @@ -858,7 +856,7 @@ end_calib: } static int get_offset(const struct motion_sensor_t *s, int16_t *offset, - int16_t *temp) + int16_t *temp) { int i; intv3_t v; @@ -891,9 +889,8 @@ static int get_offset(const struct motion_sensor_t *s, int16_t *offset, return EC_SUCCESS; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { intv3_t v = { offset[X], offset[Y], offset[Z] }; (void)temp; @@ -936,7 +933,7 @@ static int set_scale(const struct motion_sensor_t *s, const uint16_t *scale, } static int get_scale(const struct motion_sensor_t *s, uint16_t *scale, - int16_t *temp) + int16_t *temp) { struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s); @@ -949,7 +946,6 @@ static int get_scale(const struct motion_sensor_t *s, uint16_t *scale, return EC_SUCCESS; } - static int get_data_rate(const struct motion_sensor_t *s) { struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s); @@ -957,8 +953,7 @@ static int get_data_rate(const struct motion_sensor_t *s) return saved_data->odr; } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { int ret; int normalized_rate = 0; @@ -968,8 +963,8 @@ static int set_data_rate(const struct motion_sensor_t *s, struct accelgyro_saved_data_t *saved_data = BMI_GET_SAVED_DATA(s); if (rate > 0) - RETURN_ERROR(bmi_get_normalized_rate(s, rate, rnd, - &normalized_rate, ®_val)); + RETURN_ERROR(bmi_get_normalized_rate( + s, rate, rnd, &normalized_rate, ®_val)); /* * Lock accel resource to prevent another task from attempting @@ -997,8 +992,8 @@ static int set_data_rate(const struct motion_sensor_t *s, * Accel does not have suspend mode. */ reg_data[3] = BMI3_SET_BITS(reg_data[3], - BMI3_POWER_MODE, - BMI3_ACC_MODE_DISABLE); + BMI3_POWER_MODE, + BMI3_ACC_MODE_DISABLE); saved_data->odr = 0; } else if (saved_data->odr == 0) { @@ -1007,8 +1002,8 @@ static int set_data_rate(const struct motion_sensor_t *s, * normal */ reg_data[3] = BMI3_SET_BITS(reg_data[3], - BMI3_POWER_MODE, - BMI3_ACC_MODE_NORMAL); + BMI3_POWER_MODE, + BMI3_ACC_MODE_NORMAL); } } else if (s->type == MOTIONSENSE_TYPE_GYRO) { if (rate == 0) { @@ -1021,8 +1016,8 @@ static int set_data_rate(const struct motion_sensor_t *s, * however keep internal driver enabled */ reg_data[3] = BMI3_SET_BITS(reg_data[3], - BMI3_POWER_MODE, - BMI3_GYR_MODE_SUSPEND); + BMI3_POWER_MODE, + BMI3_GYR_MODE_SUSPEND); saved_data->odr = 0; } else if (saved_data->odr == 0) { @@ -1030,8 +1025,8 @@ static int set_data_rate(const struct motion_sensor_t *s, * normal */ reg_data[3] = BMI3_SET_BITS(reg_data[3], - BMI3_POWER_MODE, - BMI3_GYR_MODE_NORMAL); + BMI3_POWER_MODE, + BMI3_GYR_MODE_NORMAL); } } @@ -1068,7 +1063,7 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd) int ret; uint8_t index, sens_size = 0; uint8_t reg_data[4] = { 0 }; - int (*sensor_range)[2]; + int(*sensor_range)[2]; int acc_sensor_range[4][2] = { { 2, BMI3_ACC_RANGE_2G }, @@ -1119,8 +1114,8 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd) sensor_range[index][1]); /* Set the accel/gyro configurations. */ - ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, - ®_data[2], 2); + ret = bmi3_write_n(s, BMI3_REG_ACC_CONF + s->type, ®_data[2], + 2); /* Now that we have set the range, update the driver's value. */ if (ret == EC_SUCCESS) @@ -1198,8 +1193,8 @@ static int init(struct motion_sensor_t *s) * BMI3xx driver only supports MOTIONSENSE_TYPE_ACCEL and * MOTIONSENSE_TYPE_GYR0 */ - if (s->type != MOTIONSENSE_TYPE_ACCEL - && s->type != MOTIONSENSE_TYPE_GYRO) + if (s->type != MOTIONSENSE_TYPE_ACCEL && + s->type != MOTIONSENSE_TYPE_GYRO) return EC_ERROR_UNIMPLEMENTED; /* Read chip id */ @@ -1210,10 +1205,11 @@ static int init(struct motion_sensor_t *s) if (s->type == MOTIONSENSE_TYPE_ACCEL) { /* Reset bmi3 device */ - reg_data[0] = (uint8_t)(BMI3_CMD_SOFT_RESET - & BMI3_SET_LOW_BYTE); - reg_data[1] = (uint8_t)((BMI3_CMD_SOFT_RESET - & BMI3_SET_HIGH_BYTE) >> 8); + reg_data[0] = + (uint8_t)(BMI3_CMD_SOFT_RESET & BMI3_SET_LOW_BYTE); + reg_data[1] = + (uint8_t)((BMI3_CMD_SOFT_RESET & BMI3_SET_HIGH_BYTE) >> + 8); RETURN_ERROR(bmi3_write_n(s, BMI3_REG_CMD, reg_data, 2)); @@ -1238,8 +1234,8 @@ static int init(struct motion_sensor_t *s) saved_data->odr = 0; /* Flags used in FIFO parsing */ - data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED - | (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET)); + data->flags &= ~(BMI_FLAG_SEC_I2C_ENABLED | + (BMI_FIFO_ALL_MASK << BMI_FIFO_FLAG_OFFSET)); return sensor_init_done(s); } -- cgit v1.2.1 From 34e23e09f9c3334dd7833389da21232a77b6cdd3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:47 -0600 Subject: test/i2c_bitbang.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c027acfe43c8e17b6c777128e136b6fbea2b314 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730507 Reviewed-by: Jeremy Bettis --- test/i2c_bitbang.c | 104 ++++++++++++++++++++++++++--------------------------- 1 file changed, 50 insertions(+), 54 deletions(-) diff --git a/test/i2c_bitbang.c b/test/i2c_bitbang.c index dd84c0b83a..41ae383d78 100644 --- a/test/i2c_bitbang.c +++ b/test/i2c_bitbang.c @@ -10,15 +10,11 @@ #include "test_util.h" #include "util.h" -const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "", - .port = 0, - .kbps = 100, - .scl = GPIO_I2C_SCL, - .sda = GPIO_I2C_SDA - } -}; +const struct i2c_port_t i2c_bitbang_ports[] = { { .name = "", + .port = 0, + .kbps = 100, + .scl = GPIO_I2C_SCL, + .sda = GPIO_I2C_SDA } }; const unsigned int i2c_bitbang_ports_used = 1; struct pin_state { @@ -29,7 +25,7 @@ int history_count; void reset_state(void) { - history[0] = (struct pin_state) {1, 1}; + history[0] = (struct pin_state){ 1, 1 }; history_count = 1; bitbang_set_started(0); } @@ -48,7 +44,7 @@ void gpio_set_level(enum gpio_signal signal, int level) new.scl = level; if (new.scl != history[history_count - 1].scl || - new.sda != history[history_count - 1].sda) + new.sda != history[history_count - 1].sda) history[history_count++] = new; } @@ -66,12 +62,12 @@ static int test_i2c_start_stop(void) { struct pin_state expected[] = { /* start */ - {1, 1}, - {1, 0}, - {0, 0}, + { 1, 1 }, + { 1, 0 }, + { 0, 0 }, /* stop */ - {1, 0}, - {1, 1}, + { 1, 0 }, + { 1, 1 }, }; int i; @@ -94,14 +90,14 @@ static int test_i2c_repeated_start(void) { struct pin_state expected[] = { /* start */ - {1, 1}, - {1, 0}, - {0, 0}, + { 1, 1 }, + { 1, 0 }, + { 0, 0 }, /* repeated start */ - {0, 1}, - {1, 1}, - {1, 0}, - {0, 0}, + { 0, 1 }, + { 1, 1 }, + { 1, 0 }, + { 0, 0 }, }; int i; @@ -124,47 +120,47 @@ static int test_i2c_write(void) { struct pin_state expected[] = { /* start */ - {1, 1}, - {1, 0}, - {0, 0}, + { 1, 1 }, + { 1, 0 }, + { 0, 0 }, /* bit 7: 0 */ - {1, 0}, - {0, 0}, + { 1, 0 }, + { 0, 0 }, /* bit 6: 1 */ - {0, 1}, - {1, 1}, - {0, 1}, + { 0, 1 }, + { 1, 1 }, + { 0, 1 }, /* bit 5: 0 */ - {0, 0}, - {1, 0}, - {0, 0}, + { 0, 0 }, + { 1, 0 }, + { 0, 0 }, /* bit 4: 1 */ - {0, 1}, - {1, 1}, - {0, 1}, + { 0, 1 }, + { 1, 1 }, + { 0, 1 }, /* bit 3: 0 */ - {0, 0}, - {1, 0}, - {0, 0}, + { 0, 0 }, + { 1, 0 }, + { 0, 0 }, /* bit 2: 1 */ - {0, 1}, - {1, 1}, - {0, 1}, + { 0, 1 }, + { 1, 1 }, + { 0, 1 }, /* bit 1: 1 */ - {1, 1}, - {0, 1}, + { 1, 1 }, + { 0, 1 }, /* bit 0: 0 */ - {0, 0}, - {1, 0}, - {0, 0}, + { 0, 0 }, + { 1, 0 }, + { 0, 0 }, /* read bit */ - {0, 1}, - {1, 1}, - {0, 1}, + { 0, 1 }, + { 1, 1 }, + { 0, 1 }, /* stop */ - {0, 0}, - {1, 0}, - {1, 1}, + { 0, 0 }, + { 1, 0 }, + { 1, 1 }, }; int i, ret; -- cgit v1.2.1 From c5d701455db66b2f052d8b09eaa5f7eb76838efd Mon Sep 17 00:00:00 2001 From: Sue Chen Date: Wed, 29 Jun 2022 10:09:12 +0800 Subject: Quackingstick: Delay 2s on the first power on Delay 2s on first power on because it was found that the battery return wrong D-FET status after resume from cut off. BUG=b:231911921 BRANCH=trogdor TEST=there's no power loss after the battery resume from cutoff Signed-off-by: Sue Chen Change-Id: I1b124023b8dc8a07b40695749ed2493be86c23e0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3734267 Commit-Queue: Wai-Hong Tam Reviewed-by: Wai-Hong Tam --- board/quackingstick/board.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/quackingstick/board.c b/board/quackingstick/board.c index 0c51a27250..5b2a3a3f0f 100644 --- a/board/quackingstick/board.c +++ b/board/quackingstick/board.c @@ -434,6 +434,22 @@ void board_tcpc_init(void) } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); +void board_delay_on_first_power_on(void) +{ + /* + * b/231911921: It's found that the D-FET status is incorrect + * when the battery resume from cut off. The battery needs + * about 2s to ready to discharge so delay 2s before charge + * manager init. + */ + if (system_get_reset_flags() == EC_RESET_FLAG_POWER_ON) { + CPRINTS("Delay 2s on the first power on."); + sleep(2); + } +} +DECLARE_HOOK(HOOK_INIT, board_delay_on_first_power_on, + HOOK_PRIO_INIT_CHARGE_MANAGER - 1); + void board_hibernate(void) { int i; -- cgit v1.2.1 From f27d3887d5db257f6cd8ab63cd7139f25057a3f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:49 -0600 Subject: board/drawcia_riscv/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a0729576df8d19604ffeabd8340642c677f0bfb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728256 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/drawcia_riscv/cbi_ssfc.h b/board/drawcia_riscv/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/drawcia_riscv/cbi_ssfc.h +++ b/board/drawcia_riscv/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 6fbeefde0e435eb1d7f536f62b323adc36fd0e32 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:27 -0600 Subject: test/base32.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id21980730b1fd999ae0645bee15ccffc6846109f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730470 Reviewed-by: Jeremy Bettis --- test/base32.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/test/base32.c b/test/base32.c index faaefc266f..27e8d8d059 100644 --- a/test/base32.c +++ b/test/base32.c @@ -54,8 +54,7 @@ DECLARE_EC_TEST(test_crc5) return EC_SUCCESS; } -static int enctest(const void *src, int srcbits, int crc_every, - const char *enc) +static int enctest(const void *src, int srcbits, int crc_every, const char *enc) { char dest[32]; @@ -73,7 +72,7 @@ static int enctest(const void *src, int srcbits, int crc_every, DECLARE_EC_TEST(test_encode) { - const uint8_t src1[5] = {0xff, 0x00, 0xff, 0x00, 0xff}; + const uint8_t src1[5] = { 0xff, 0x00, 0xff, 0x00, 0xff }; char enc[32]; /* Test for enough space; error produces null string */ @@ -104,10 +103,9 @@ DECLARE_EC_TEST(test_encode) /* CRC requires exact multiple of symbol count */ ENCTEST("\xff\x00\xff\x00\xff", 40, 4, "96ARU8AH9D"); ENCTEST("\xff\x00\xff\x00\xff", 40, 8, "96AR8AH9L"); - zassert_equal( - base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff", - 40, 6), - EC_ERROR_INVAL, NULL); + zassert_equal(base32_encode(enc, 16, (uint8_t *)"\xff\x00\xff\x00\xff", + 40, 6), + EC_ERROR_INVAL, NULL); /* But what matters is symbol count, not bit count */ ENCTEST("\xff\x00\xff\x00\xfe", 39, 4, "96ARU8AH8P"); @@ -201,8 +199,7 @@ DECLARE_EC_TEST(test_decode) TEST_MAIN() { - ztest_test_suite(test_base32_lib, - ztest_unit_test(test_crc5), + ztest_test_suite(test_base32_lib, ztest_unit_test(test_crc5), ztest_unit_test(test_encode), ztest_unit_test(test_decode)); ztest_run_test_suite(test_base32_lib); -- cgit v1.2.1 From a4f1f7ed17ff06608abb56cc053759883f93063e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:39 -0600 Subject: board/chronicler/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe468d063a9d4f171abd21d71b0bfdec9cc65119 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728149 Reviewed-by: Jeremy Bettis --- board/chronicler/usbc_config.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/chronicler/usbc_config.c b/board/chronicler/usbc_config.c index c2783dd755..c03f00576b 100644 --- a/board/chronicler/usbc_config.c +++ b/board/chronicler/usbc_config.c @@ -23,7 +23,7 @@ #include "driver/tcpm/tusb422_public.h" #include "driver/tcpm/tcpci.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* * USB3 DB mux configuration - the top level mux still needs to be set to the @@ -124,8 +124,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -136,16 +135,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -207,7 +206,7 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ ps8815_reset(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } static void board_tcpc_init(void) -- cgit v1.2.1 From 6e54c32990c85722aa8dd024045f08b01c828840 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:43 -0600 Subject: board/kukui/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I878676141511fb7ca59b20c5b1a10b786d5c53ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728590 Reviewed-by: Jeremy Bettis --- board/kukui/board.c | 86 ++++++++++++++++++++++------------------------------- 1 file changed, 36 insertions(+), 50 deletions(-) diff --git a/board/kukui/board.c b/board/kukui/board.c index a3468b62ca..2379ef2456 100644 --- a/board/kukui/board.c +++ b/board/kukui/board.c @@ -43,8 +43,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -65,30 +65,27 @@ static void motion_interrupt(enum gpio_signal signal); /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, - [ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, + [ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0, + STM32_AIN(6) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -96,15 +93,14 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ @@ -134,8 +130,7 @@ void board_set_dp_mux_control(int output_enable, int polarity) gpio_set_level(GPIO_USB_C0_DP_POLARITY, polarity); } -static void board_hpd_update(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -266,9 +261,8 @@ int extpower_is_present(void) if (board_vbus_source_enabled(CHARGE_PORT_USB_C)) usb_c_extpower_present = 0; else - usb_c_extpower_present = tcpm_check_vbus_level( - CHARGE_PORT_USB_C, - VBUS_PRESENT); + usb_c_extpower_present = + tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT); return usb_c_extpower_present || kukui_pogo_extpower_present(); } @@ -357,8 +351,8 @@ static void board_rev_init(void) /* configure PI3USB9201 to USB Path ON Mode */ i2c_write8(I2C_PORT_BC12, BC12_I2C_ADDR_FLAGS, PI3USB9201_REG_CTRL_1, - (PI3USB9201_USB_PATH_ON << - PI3USB9201_REG_CTRL_1_MODE_SHIFT)); + (PI3USB9201_USB_PATH_ON + << PI3USB9201_REG_CTRL_1_MODE_SHIFT)); } if (board_get_version() < 5) { @@ -438,26 +432,20 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { /* Matrix to rotate accelerometer into standard reference frame */ #ifdef BOARD_KUKUI -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; #else -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; #endif /* BOARD_KUKUI */ #ifdef CONFIG_MAG_BMI_BMM150 /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t mag_standard_ref = { - {0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t mag_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; #endif /* CONFIG_MAG_BMI_BMM150 */ struct motion_sensor_t motion_sensors[] = { @@ -632,7 +620,6 @@ static void motion_interrupt(enum gpio_signal signal) #elif !defined(VARIANT_KUKUI_NO_SENSORS) bmi160_interrupt(signal); #endif /* BOARD_KRANE, !VARIANT_KUKUI_NO_SENSORS */ - } #endif /* SECTION_IS_RW */ @@ -669,9 +656,8 @@ __override int board_charge_port_is_connected(int port) return gpio_get_level(GPIO_POGO_VBUS_PRESENT); } -__override -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r) +__override void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r) { r->meas.voltage_now = 3300; r->meas.voltage_max = 3300; -- cgit v1.2.1 From 78848a164845b77c866497919da5ba8c616007d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:53 -0600 Subject: board/osiris/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2a505c57d7ae865a9996adce3126e468bb28be88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728798 Reviewed-by: Jeremy Bettis --- board/osiris/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/osiris/fw_config.c b/board/osiris/fw_config.c index 6a4469163b..67f23349cf 100644 --- a/board/osiris/fw_config.c +++ b/board/osiris/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union osiris_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From d1b46d1ca7d2e921faa9376b75c92c09fb33a0c0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:33 -0600 Subject: test/genvif/src/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01991cfe362c233fbef6815a2592fc017ff5c3e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730504 Reviewed-by: Jeremy Bettis --- test/genvif/src/board.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/genvif/src/board.h b/test/genvif/src/board.h index 06122eeab9..f4037f761c 100644 --- a/test/genvif/src/board.h +++ b/test/genvif/src/board.h @@ -3,10 +3,10 @@ * found in the LICENSE file. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* Stubs required by the shared code */ #define GPIO_PIN(port, index) (GPIO_##port, BIT(index)) -- cgit v1.2.1 From 16f580965a7e624e9d2e4c5bcc6b3ad875322a4a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:22 -0600 Subject: include/keyboard_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icd3b054eb6673729ea6da9f4301915632db554ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730296 Reviewed-by: Jeremy Bettis --- include/keyboard_config.h | 86 +++++++++++++++++++++++------------------------ 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/include/keyboard_config.h b/include/keyboard_config.h index 2e6a6eb80d..d25a74232c 100644 --- a/include/keyboard_config.h +++ b/include/keyboard_config.h @@ -20,8 +20,8 @@ #endif /* Keyboard matrix is 13 (or 15 with keypad) output columns x 8 input rows */ -#define KEYBOARD_COLS_WITH_KEYPAD 15 -#define KEYBOARD_COLS_NO_KEYPAD 13 +#define KEYBOARD_COLS_WITH_KEYPAD 15 +#define KEYBOARD_COLS_NO_KEYPAD 13 /* * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate @@ -44,59 +44,59 @@ extern uint8_t keyboard_cols; #define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) /* Columns and masks for keys we particularly care about */ -#define KEYBOARD_COL_DOWN 11 -#define KEYBOARD_ROW_DOWN 6 -#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) -#define KEYBOARD_COL_ESC 1 -#define KEYBOARD_ROW_ESC 1 -#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) -#define KEYBOARD_COL_KEY_H 6 -#define KEYBOARD_ROW_KEY_H 1 -#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) -#define KEYBOARD_COL_KEY_R 3 -#define KEYBOARD_ROW_KEY_R 7 -#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) -#define KEYBOARD_COL_LEFT_ALT 10 -#define KEYBOARD_ROW_LEFT_ALT 6 -#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) -#define KEYBOARD_COL_REFRESH 2 +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 6 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 #ifdef CONFIG_KEYBOARD_REFRESH_ROW3 -#define KEYBOARD_ROW_REFRESH 3 +#define KEYBOARD_ROW_REFRESH 3 #else -#define KEYBOARD_ROW_REFRESH 2 +#define KEYBOARD_ROW_REFRESH 2 #endif -#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) -#define KEYBOARD_COL_RIGHT_ALT 10 -#define KEYBOARD_ROW_RIGHT_ALT 0 -#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) -#define KEYBOARD_DEFAULT_COL_VOL_UP 4 -#define KEYBOARD_DEFAULT_ROW_VOL_UP 0 -#define KEYBOARD_COL_LEFT_CTRL 0 -#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 0 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) #define KEYBOARD_COL_RIGHT_CTRL 0 #define KEYBOARD_ROW_RIGHT_CTRL 4 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) -#define KEYBOARD_COL_SEARCH 1 -#define KEYBOARD_ROW_SEARCH 0 -#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) -#define KEYBOARD_COL_KEY_0 8 -#define KEYBOARD_ROW_KEY_0 6 -#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) -#define KEYBOARD_COL_KEY_1 1 -#define KEYBOARD_ROW_KEY_1 6 -#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) -#define KEYBOARD_COL_KEY_2 4 -#define KEYBOARD_ROW_KEY_2 6 -#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_SEARCH 1 +#define KEYBOARD_ROW_SEARCH 0 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 8 +#define KEYBOARD_ROW_KEY_0 6 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 6 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) #define KEYBOARD_COL_LEFT_SHIFT 7 #define KEYBOARD_ROW_LEFT_SHIFT 5 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) #ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2) +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2) #elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3) -#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3) +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3) #endif #endif /* CONFIG_KEYBOARD_CUSTOMIZATION */ -#endif /* __CROS_EC_KEYBOARD_CONFIG_H */ +#endif /* __CROS_EC_KEYBOARD_CONFIG_H */ -- cgit v1.2.1 From ca5298e10ab3efb13776a0525d5c7cdfec9428ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:25 -0600 Subject: common/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d68e68e8098b86aff1ed991c510256d01a70bb7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729596 Reviewed-by: Jeremy Bettis --- common/cbi.c | 61 +++++++++++++++++++++++++++++------------------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/common/cbi.c b/common/cbi.c index e18f15e5a9..678f429530 100644 --- a/common/cbi.c +++ b/common/cbi.c @@ -31,8 +31,8 @@ uint8_t cbi_crc8(const struct cbi_header *h) h->total_size - sizeof(h->magic) - sizeof(h->crc)); } -uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, - const void *buf, int size) +uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf, + int size) { struct cbi_data *d = (struct cbi_data *)p; @@ -77,11 +77,11 @@ struct cbi_data *cbi_find_tag(const void *buf, enum cbi_data_tag tag) */ #ifndef HOST_TOOLS_BUILD -#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, "CBI " format, ##args) static int cache_status = CBI_CACHE_STATUS_INVALID; static uint8_t cbi[CBI_IMAGE_SIZE]; -static struct cbi_header * const head = (struct cbi_header *)cbi; +static struct cbi_header *const head = (struct cbi_header *)cbi; int cbi_create(void) { @@ -133,21 +133,21 @@ static int do_cbi_read(void) * buffer has practical limitation. */ if (head->total_size < sizeof(*head) || - head->total_size > CBI_IMAGE_SIZE) { + head->total_size > CBI_IMAGE_SIZE) { CPRINTS("Bad size: %d", head->total_size); return EC_ERROR_OVERFLOW; } /* Read the data */ if (cbi_config.drv->load(sizeof(*head), head->data, - head->total_size - sizeof(*head))) { + head->total_size - sizeof(*head))) { CPRINTS("Failed to read body"); return EC_ERROR_INVAL; } /* Check CRC. This supports new fields unknown to this parser. */ if (cbi_config.storage_type != CBI_STORAGE_TYPE_GPIO && - cbi_crc8(head) != head->crc) { + cbi_crc8(head) != head->crc) { CPRINTS("Bad CRC"); return EC_ERROR_INVAL; } @@ -175,8 +175,8 @@ static int cbi_read(void) return rv; } -__attribute__((weak)) -int cbi_board_override(enum cbi_data_tag tag, uint8_t *buf, uint8_t *size) +__attribute__((weak)) int cbi_board_override(enum cbi_data_tag tag, + uint8_t *buf, uint8_t *size) { return EC_SUCCESS; } @@ -294,8 +294,7 @@ int cbi_get_ssfc(uint32_t *ssfc) { uint8_t size = sizeof(*ssfc); - return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc, - &size); + return cbi_get_board_info(CBI_TAG_SSFC, (uint8_t *)ssfc, &size); } int cbi_get_pcb_supplier(uint32_t *pcb_supplier) @@ -303,7 +302,7 @@ int cbi_get_pcb_supplier(uint32_t *pcb_supplier) uint8_t size = sizeof(*pcb_supplier); return cbi_get_board_info(CBI_TAG_PCB_SUPPLIER, (uint8_t *)pcb_supplier, - &size); + &size); } int cbi_get_rework_id(uint64_t *id) @@ -326,19 +325,16 @@ static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args) args->response_size = size; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO, - hc_cbi_get, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_CROS_BOARD_INFO, hc_cbi_get, EC_VER_MASK(0)); -static enum ec_status common_cbi_set(const struct __ec_align4 - ec_params_set_cbi * p) +static enum ec_status +common_cbi_set(const struct __ec_align4 ec_params_set_cbi *p) { /* * If we ultimately cannot write to the flash, then fail early unless * we are explicitly trying to write to the in-memory CBI only */ - if (cbi_config.drv->is_protected() && - !(p->flag & CBI_SET_NO_SYNC)) { + if (cbi_config.drv->is_protected() && !(p->flag & CBI_SET_NO_SYNC)) { CPRINTS("Failed to write due to WP"); return EC_RES_ACCESS_DENIED; } @@ -386,7 +382,7 @@ static enum ec_status common_cbi_set(const struct __ec_align4 static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args) { - const struct __ec_align4 ec_params_set_cbi * p = args->params; + const struct __ec_align4 ec_params_set_cbi *p = args->params; /* Given data size exceeds the packet size. */ if (args->params_size < sizeof(*p) + p->size) @@ -394,12 +390,10 @@ static enum ec_status hc_cbi_set(struct host_cmd_handler_args *args) return common_cbi_set(p); } -DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO, - hc_cbi_set, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_SET_CROS_BOARD_INFO, hc_cbi_set, EC_VER_MASK(0)); #ifdef CONFIG_CMD_CBI -static void print_tag(const char * const tag, int rv, const uint32_t *val) +static void print_tag(const char *const tag, int rv, const uint32_t *val) { ccprintf("%s", tag); if (rv == EC_SUCCESS && val) @@ -408,7 +402,7 @@ static void print_tag(const char * const tag, int rv, const uint32_t *val) ccprintf(": (Error %d)\n", rv); } -static void print_uint64_tag(const char * const tag, int rv, +static void print_uint64_tag(const char *const tag, int rv, const uint64_t *lval) { ccprintf("%s", tag); @@ -429,7 +423,8 @@ static void dump_cbi(void) cbi_read(); if (cbi_get_cache_status() != CBI_CACHE_STATUS_SYNCED) { - ccprintf("Cannot Read CBI (Error %d)\n", cbi_get_cache_status()); + ccprintf("Cannot Read CBI (Error %d)\n", + cbi_get_cache_status()); return; } @@ -450,12 +445,12 @@ static void dump_cbi(void) * Space for the set command (does not include data space) plus maximum * possible console input */ -static uint8_t buf[sizeof(struct ec_params_set_cbi) + \ - CONFIG_CONSOLE_INPUT_LINE_SIZE]; +static uint8_t + buf[sizeof(struct ec_params_set_cbi) + CONFIG_CONSOLE_INPUT_LINE_SIZE]; static int cc_cbi(int argc, char **argv) { - struct __ec_align4 ec_params_set_cbi * setter = + struct __ec_align4 ec_params_set_cbi *setter = (struct __ec_align4 ec_params_set_cbi *)buf; int last_arg; char *e; @@ -494,8 +489,9 @@ static int cc_cbi(int argc, char **argv) if (setter->size < 1) { ccprintf("Set size too small\n"); return EC_ERROR_PARAM4; - } else if ((setter->size > 8) || (setter->size > 4 && - setter->tag != CBI_TAG_REWORK_ID)) { + } else if ((setter->size > 8) || + (setter->size > 4 && + setter->tag != CBI_TAG_REWORK_ID)) { ccprintf("Set size too large\n"); return EC_ERROR_PARAM4; } @@ -542,7 +538,8 @@ static int cc_cbi(int argc, char **argv) return EC_ERROR_UNKNOWN; } -DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, "[set | " +DECLARE_CONSOLE_COMMAND(cbi, cc_cbi, + "[set | " "remove ] [init | skip_write]", "Print or change Cros Board Info from flash"); #endif /* CONFIG_CMD_CBI */ -- cgit v1.2.1 From 63a35eb757486151f9a64fbc4e1bc6db5ac02ec4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:52 -0600 Subject: chip/it83xx/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idfc118387ac3981e85ae0afbf6b670d4d07edbd3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729218 Reviewed-by: Jeremy Bettis --- chip/it83xx/watchdog.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c index 345a100922..e88e2e46bc 100644 --- a/chip/it83xx/watchdog.c +++ b/chip/it83xx/watchdog.c @@ -24,9 +24,9 @@ static int wdt_warning_fired; */ /* Magic value to tickle the watchdog register. */ -#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C +#define ITE83XX_WATCHDOG_MAGIC_WORD 0x5C /* Start to print warning message. */ -#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS +#define ITE83XX_WATCHDOG_WARNING_MS CONFIG_AUX_TIMER_PERIOD_MS /* The interval to print warning message at critical period. */ #define ITE83XX_WATCHDOG_CRITICAL_MS 30 @@ -39,7 +39,7 @@ static void watchdog_set_warning_timer(int32_t ms, int init) void watchdog_warning_irq(void) { #ifdef CONFIG_SOFTWARE_PANIC - struct panic_data * const pdata_ptr = get_panic_data_write(); + struct panic_data *const pdata_ptr = get_panic_data_write(); #if defined(CHIP_CORE_NDS32) pdata_ptr->nds_n8.ipc = get_ipc(); @@ -64,10 +64,10 @@ void watchdog_warning_irq(void) * LP = PC+4 after a jump and link instruction (jal). */ panic_printf("Pre-WDT warning! IPC:%08x LP:%08x TASK_ID:%d\n", - get_ipc(), ilp, task_get_current()); + get_ipc(), ilp, task_get_current()); #elif defined(CHIP_CORE_RISCV) panic_printf("Pre-WDT warning! MEPC:%08x RA:%08x TASK_ID:%d\n", - get_mepc(), ira, task_get_current()); + get_mepc(), ira, task_get_current()); #endif if (!wdt_warning_fired++) -- cgit v1.2.1 From 5d575a59830cf03cb52f600434d808e45270eea1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:12 -0600 Subject: board/redrix/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I767ffd788ff072951f28734022c136e24828e1cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728861 Reviewed-by: Jeremy Bettis --- board/redrix/sensors.c | 72 +++++++++++++++++++++----------------------------- 1 file changed, 30 insertions(+), 42 deletions(-) diff --git a/board/redrix/sensors.c b/board/redrix/sensors.c index df0e94f518..f33b98efeb 100644 --- a/board/redrix/sensors.c +++ b/board/redrix/sensors.c @@ -57,17 +57,13 @@ static struct accelgyro_saved_data_t g_bma253_data; static struct accelgyro_saved_data_t g_bma422_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TCS3400 private data */ static struct als_drv_data_t g_tcs3400_data = { @@ -291,38 +287,30 @@ DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR] = { - .name = "DDR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR - }, - [TEMP_SENSOR_2_SOC] = { - .name = "SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_SOC - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, - [TEMP_SENSOR_4_REGULATOR] = { - .name = "Regulator", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_REGULATOR - }, + [TEMP_SENSOR_1_DDR] = { .name = "DDR", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR }, + [TEMP_SENSOR_2_SOC] = { .name = "SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_SOC }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, + [TEMP_SENSOR_4_REGULATOR] = { .name = "Regulator", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_REGULATOR }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_DDR \ - { \ +#define THERMAL_DDR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -341,8 +329,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -356,8 +344,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -372,8 +360,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_REGULATOR \ - { \ +#define THERMAL_REGULATOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ -- cgit v1.2.1 From 4b3e08964c29382d300401d95c703320ed717784 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:20 -0600 Subject: board/brya/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia87e329e22e4906f2f70030a2b65e5c37c904f39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728044 Reviewed-by: Jeremy Bettis --- board/brya/charger.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/brya/charger.c diff --git a/board/brya/charger.c b/board/brya/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/brya/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/brya/charger.c b/board/brya/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/brya/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From 5aa17b087f9ba956d77efd8eec292383c38fe4e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:48 -0600 Subject: zephyr/test/drivers/src/console_cmd/charge_manager.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I401bdf237c85534a4b0580966428f0feff216942 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730926 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/console_cmd/charge_manager.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/zephyr/test/drivers/src/console_cmd/charge_manager.c b/zephyr/test/drivers/src/console_cmd/charge_manager.c index 64716b1ced..e4756bbb1b 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_manager.c +++ b/zephyr/test/drivers/src/console_cmd/charge_manager.c @@ -25,8 +25,7 @@ static void connect_sink_to_port(const struct emul *charger_emul, tcpci_emul_set_reg(tcpci_emul, TCPC_REG_EXT_STATUS, TCPC_REG_EXT_STATUS_SAFE0V); tcpci_tcpc_alert(0); - zassume_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul), - NULL); + zassume_ok(tcpci_partner_connect_to_tcpci(partner, tcpci_emul), NULL); /* Wait for PD negotiation and current ramp. * TODO(b/213906889): Check message timing and contents. @@ -60,9 +59,8 @@ static void *console_cmd_charge_manager_setup(void) /* Initialized the sink to request 5V and 3A */ tcpci_partner_init(&test_fixture.sink_5v_3a, PD_REV20); - test_fixture.sink_5v_3a.extensions = - tcpci_snk_emul_init(&test_fixture.sink_ext, - &test_fixture.sink_5v_3a, NULL); + test_fixture.sink_5v_3a.extensions = tcpci_snk_emul_init( + &test_fixture.sink_ext, &test_fixture.sink_5v_3a, NULL); test_fixture.sink_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); -- cgit v1.2.1 From ebf825a72a25d49d989981febd4b39aec311b338 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:07 -0600 Subject: board/it8xxx2_pdevb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I78b7d23ccc42f44af826f0bd953ffc43909a82ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728513 Reviewed-by: Jeremy Bettis --- board/it8xxx2_pdevb/board.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/it8xxx2_pdevb/board.c b/board/it8xxx2_pdevb/board.c index 9161b2ce2e..46198f406b 100644 --- a/board/it8xxx2_pdevb/board.c +++ b/board/it8xxx2_pdevb/board.c @@ -14,12 +14,12 @@ #include "timer.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define USB_PD_PORT_ITE_0 0 -#define USB_PD_PORT_ITE_1 1 -#define USB_PD_PORT_ITE_2 2 -#define RESISTIVE_DIVIDER 11 +#define USB_PD_PORT_ITE_0 0 +#define USB_PD_PORT_ITE_1 1 +#define USB_PD_PORT_ITE_2 2 +#define RESISTIVE_DIVIDER 11 int board_get_battery_soc(void) { @@ -83,7 +83,7 @@ void board_pd_vbus_ctrl(int port, int enabled) gpio_set_level(GPIO_USBPD_PORTA_VBUS_OUTPUT, enabled); if (!enabled) { gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 1); - udelay(10*MSEC); /* 10ms is a try and error value */ + udelay(10 * MSEC); /* 10ms is a try and error value */ } gpio_set_level(GPIO_USBPD_PORTA_VBUS_DROP, 0); } else if (port == USBPD_PORT_B) { @@ -91,7 +91,7 @@ void board_pd_vbus_ctrl(int port, int enabled) gpio_set_level(GPIO_USBPD_PORTB_VBUS_OUTPUT, enabled); if (!enabled) { gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 1); - udelay(10*MSEC); /* 10ms is a try and error value */ + udelay(10 * MSEC); /* 10ms is a try and error value */ } gpio_set_level(GPIO_USBPD_PORTB_VBUS_DROP, 0); } else if (port == USBPD_PORT_C) { @@ -99,13 +99,13 @@ void board_pd_vbus_ctrl(int port, int enabled) gpio_set_level(GPIO_USBPD_PORTC_VBUS_OUTPUT, enabled); if (!enabled) { gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 1); - udelay(10*MSEC); /* 10ms is a try and error value */ + udelay(10 * MSEC); /* 10ms is a try and error value */ } gpio_set_level(GPIO_USBPD_PORTC_VBUS_DROP, 0); } if (enabled) - udelay(10*MSEC); /* 10ms is a try and error value */ + udelay(10 * MSEC); /* 10ms is a try and error value */ } void pd_set_input_current_limit(int port, uint32_t max_ma, @@ -120,8 +120,7 @@ void pd_set_input_current_limit(int port, uint32_t max_ma, * so use the same frequency and prescaler register setting is required if * number of pwm channel greater than three. */ -const struct pwm_t pwm_channels[] = { -}; +const struct pwm_t pwm_channels[] = {}; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ -- cgit v1.2.1 From b4490ae4907b1f36838dd41939106d77106a8c7f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:05 -0600 Subject: board/icarus/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b114460d5e2a33361076b77b469a34e06dd4601 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728512 Reviewed-by: Jeremy Bettis --- board/icarus/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/icarus/led.c b/board/icarus/led.c index 076199b2ed..c0e6db6874 100644 --- a/board/icarus/led.c +++ b/board/icarus/led.c @@ -14,22 +14,27 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From d8aad74514351a7e88a379c4afa0ead8850b386a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:15 -0600 Subject: chip/stm32/registers-stm32f4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9264aeb205217ae4c6788ac78cf0429ae9668bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729529 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f4.h | 1555 ++++++++++++++++++++-------------------- 1 file changed, 771 insertions(+), 784 deletions(-) diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index 12bfe31063..cccc430fd2 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -22,104 +22,103 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ #if defined(CHIP_VARIANT_STM32F412) -#define STM32_IRQ_TIM9 24 /* STM32F412 only */ +#define STM32_IRQ_TIM9 24 /* STM32F412 only */ #else -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ #endif -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -134,279 +133,276 @@ * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - +#define STM32_ADC1_BASE 0x40012000 +#define STM32_ADC_BASE 0x40012300 + +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 + +#define STM32_DBGMCU_BASE 0xE0042000 + +#define STM32_DMA1_BASE 0x40026000 +#define STM32_DMA2_BASE 0x40026400 + +#define STM32_EXTI_BASE 0x40013C00 + +#define STM32_FLASH_REGS_BASE 0x40023c00 + +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ +#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOH_BASE 0x40021C00 + +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 + +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 + +#define STM32_OPTB_BASE 0x1FFFC000 +#define STM32_OTP_BASE 0x1FFF7800 + +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 + +#define STM32_RCC_BASE 0x40023800 + +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ + +#define STM32_SYSCFG_BASE 0x40013800 + +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ +#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ +#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ + +#define STM32_UNIQUE_ID_BASE 0x1fff7a10 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 + +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 + +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_UE BIT(13) +#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) /* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) +#define STM32_USART_TDR(base) STM32_USART_DR(base) +#define STM32_USART_RDR(base) STM32_USART_DR(base) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) + +#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define FMPI2C_CR1_PE BIT(0) +#define FMPI2C_CR1_TXDMAEN BIT(14) +#define FMPI2C_CR1_RXDMAEN BIT(15) +#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define FMPI2C_CR2_RD_WRN BIT(10) +#define FMPI2C_READ 1 +#define FMPI2C_WRITE 0 +#define FMPI2C_CR2_START BIT(13) +#define FMPI2C_CR2_STOP BIT(14) +#define FMPI2C_CR2_NACK BIT(15) +#define FMPI2C_CR2_RELOAD BIT(24) +#define FMPI2C_CR2_AUTOEND BIT(25) +#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff) +#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) +#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16) +#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) +#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 +#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28) +#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20) +#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16) +#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8) +#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0) +#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) + +#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define FMPI2C_ISR_TXE BIT(0) +#define FMPI2C_ISR_TXIS BIT(1) +#define FMPI2C_ISR_RXNE BIT(2) +#define FMPI2C_ISR_ADDR BIT(3) +#define FMPI2C_ISR_NACKF BIT(4) +#define FMPI2C_ISR_STOPF BIT(5) +#define FMPI2C_ISR_BERR BIT(8) +#define FMPI2C_ISR_ARLO BIT(9) +#define FMPI2C_ISR_BUSY BIT(15) +#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) + +#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #if defined(CHIP_VARIANT_STM32F446) /* Required or recommended clocks for stm32f446 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 42000000 +#define STM32F4_IO_CLOCK 42000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 336000000 #define STM32F4_HSI_CLOCK 16000000 @@ -416,15 +412,15 @@ #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_LATENCY BIT(0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F412) /* Required or recommended clocks for stm32f412 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 +#define STM32F4_IO_CLOCK 48000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 384000000 #define STM32F4_HSI_CLOCK 16000000 @@ -434,15 +430,15 @@ #define STM32F4_AHB_PRE 0x0 #define STM32F4_APB1_PRE 0x4 #define STM32F4_APB2_PRE 0x4 -#define STM32_FLASH_ACR_LATENCY (3 << 0) +#define STM32_FLASH_ACR_LATENCY (3 << 0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F411) /* Required or recommended clocks for stm32f411 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 -#define STM32F4_IO_CLOCK 48000000 +#define STM32F4_IO_CLOCK 48000000 #define STM32F4_USB_REQ 48000000 #define STM32F4_VCO_CLOCK 384000000 #define STM32F4_HSI_CLOCK 16000000 @@ -452,204 +448,204 @@ #define STM32F4_AHB_PRE 0x8 #define STM32F4_APB1_PRE 0x0 #define STM32F4_APB2_PRE 0x0 -#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_LATENCY BIT(0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #elif defined(CHIP_VARIANT_STM32F76X) /* Required or recommended clocks for stm32f767/769 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ +#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ +#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ +#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) +#define STM32_FLASH_ACR_LATENCY (5 << 0) /* optimized flash latency for < 30Mhz clock (0-WS) e.g. HSI/HSE */ -#define STM32_FLASH_ACR_LATENCY_SLOW 0 +#define STM32_FLASH_ACR_LATENCY_SLOW 0 #else #error "No valid clocks defined" #endif -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 0 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLN_OFF 6 +#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF) /* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLP_OFF 16 +#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF) -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) +#define PLLCFGR_PLLSRC_HSI (0 << 22) +#define PLLCFGR_PLLSRC_HSE BIT(22) /* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLQ_OFF 24 +#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF) /* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define PLLCFGR_PLLR_OFF 28 +#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF) + +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSE (1 << 0) +#define STM32_RCC_CFGR_SW_PLL (2 << 0) +#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSE (1 << 2) +#define STM32_RCC_CFGR_SWS_PLL (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 10 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 13 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) - -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) - -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) - -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) - -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) + +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define RCC_AHB1RSTR_OTGHSRST BIT(29) + +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) + +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) + +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_AHB1ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB1ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB1ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB1ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB1ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB1ENR_GPIO_PORTF BIT(5) +#define STM32_RCC_AHB1ENR_GPIO_PORTG BIT(6) +#define STM32_RCC_AHB1ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) +#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) /* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM8 BIT(1) -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - +#define STM32_RCC_HB1_DMA1 BIT(21) +#define STM32_RCC_HB1_DMA2 BIT(22) +#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) +#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) + +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_PWREN BIT(28) +#define STM32_RCC_I2C1EN BIT(21) +#define STM32_RCC_I2C2EN BIT(22) +#define STM32_RCC_I2C3EN BIT(23) +#define STM32_RCC_FMPI2C4EN BIT(24) + +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ + +#define STM32_RCC_PB2_USART6 BIT(5) +#define STM32_RCC_SYSCFGEN BIT(14) + +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM8 BIT(1) +#define STM32_RCC_PB2_TIM9 BIT(16) +#define STM32_RCC_PB2_TIM10 BIT(17) +#define STM32_RCC_PB2_TIM11 BIT(18) + +#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) +#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22) +#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) +#define FMPI2C1SEL_APB 0x0 + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* Peripheral bits for RCC_APB/AHB regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG (BIT(30)|BIT(29)) -#define RESET_CAUSE_SFT BIT(28) -#define RESET_CAUSE_POR BIT(27) -#define RESET_CAUSE_PIN BIT(26) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)) -#define RESET_CAUSE_RMVF BIT(24) +#define RESET_CAUSE_WDG (BIT(30) | BIT(29)) +#define RESET_CAUSE_SFT BIT(28) +#define RESET_CAUSE_POR BIT(27) +#define RESET_CAUSE_PIN BIT(26) +#define RESET_CAUSE_OTHER \ + (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25)) +#define RESET_CAUSE_RMVF BIT(24) /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define RESET_CAUSE_SBF BIT(1) +#define RESET_CAUSE_SBF BIT(1) #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF_CLR BIT(3) +#define RESET_CAUSE_SBF_CLR BIT(3) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -666,8 +662,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -677,185 +673,181 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6) -#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7) -#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23) -#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24) -#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25) -#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1) -#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18) +#define STM32_DBGMCU_CR_SLEEP BIT(0) +#define STM32_DBGMCU_CR_STOP BIT(1) +#define STM32_DBGMCU_CR_STBY BIT(2) +#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define STM32_DBGMCU_CR_TRACE_EN BIT(5) +#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7)) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) +#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) +#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) +#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) +#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) +#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) +#define STM32_DBGMCU_APB1FZ_TIM12 BIT(6) +#define STM32_DBGMCU_APB1FZ_TIM13 BIT(7) +#define STM32_DBGMCU_APB1FZ_TIM14 BIT(8) +#define STM32_DBGMCU_APB1FZ_RTC BIT(10) +#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) +#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) +#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) +#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) +#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(23) +#define STM32_DBGMCU_APB1FZ_I2CFMP_SMBUS_TIMEOUT BIT(24) +#define STM32_DBGMCU_APB1FZ_CAN1 BIT(25) +#define STM32_DBGMCU_APB1FZ_CAN2 BIT(26) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB2FZ_TIM1 BIT(0) +#define STM32_DBGMCU_APB2FZ_TIM8 BIT(1) +#define STM32_DBGMCU_APB2FZ_TIM9 BIT(16) +#define STM32_DBGMCU_APB2FZ_TIM10 BIT(17) +#define STM32_DBGMCU_APB2FZ_TIM11 BIT(18) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_SHIFT 0 +#define STM32_FLASH_ACR_LAT_MASK 0xf +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_EOP BIT(0) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_PGPERR BIT(6) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_RDERR BIT(8) +#define FLASH_SR_ALL_ERR \ (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define FLASH_OPTCR_RDP_SHIFT (8) -#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_SR_BUSY BIT(16) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_MER BIT(2) +#define STM32_FLASH_CR_SNB_OFFSET (3) +#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET) +#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) +#define STM32_FLASH_CR_PSIZE_OFFSET (8) +#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET) +#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_LOCK BIT(31) +#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_OPTLOCK BIT(0) +#define FLASH_OPTSTRT BIT(1) +#define STM32_FLASH_BOR_LEV_OFFSET (2) +#define FLASH_OPTCR_RDP_SHIFT (8) +#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_RDP_LEVEL_0 (0xAA << FLASH_OPTCR_RDP_SHIFT) /* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) -#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 +#define FLASH_OPTCR_RDP_LEVEL_1 (0x00 << FLASH_OPTCR_RDP_SHIFT) +#define FLASH_OPTCR_RDP_LEVEL_2 (0xCC << FLASH_OPTCR_RDP_SHIFT) +#define STM32_FLASH_nWRP_OFFSET (16) +#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) + +#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) +#define STM32_OPTB_nWRP(_bank) BIT(_bank) +#define STM32_OPTB_nWRP_ALL (0xFF) + +#define STM32_OPTB_COMPL_SHIFT 8 + +#define STM32_OTP_BLOCK_NB 16 +#define STM32_OTP_BLOCK_SIZE 32 #define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4) +#define STM32_OTP_UNLOCK_BYTE 0x00 +#define STM32_OTP_LOCK_BYTE 0xFF +#define STM32_OTP_LOCK_BASE \ (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) +#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) +#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -963,12 +955,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -977,12 +969,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -993,109 +984,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) + +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -1105,28 +1093,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From c4d60e1b7731f9bc1660570138f29871ed23b8f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:18 -0600 Subject: include/watchdog.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifa56ecd8d1fe1d73152fec203f8c95c50baca8e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730458 Reviewed-by: Jeremy Bettis --- include/watchdog.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/watchdog.h b/include/watchdog.h index 036f722d97..fe17fbef6f 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -49,7 +49,9 @@ void watchdog_stop_and_unlock(void); #ifdef CONFIG_WATCHDOG void watchdog_reload(void); #else -static inline void watchdog_reload(void) { } +static inline void watchdog_reload(void) +{ +} #endif #endif /* __CROS_EC_WATCHDOG_H */ -- cgit v1.2.1 From c200bdf940b186d465a215988081843a630891fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:34 -0600 Subject: driver/retimer/pi3hdx1204.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifa7073e92e54fd841136711fd6d1611225b306ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730046 Reviewed-by: Jeremy Bettis --- driver/retimer/pi3hdx1204.h | 69 ++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 35 deletions(-) diff --git a/driver/retimer/pi3hdx1204.h b/driver/retimer/pi3hdx1204.h index f758149c10..817115fc32 100644 --- a/driver/retimer/pi3hdx1204.h +++ b/driver/retimer/pi3hdx1204.h @@ -8,62 +8,61 @@ #ifndef __CROS_EC_USB_RETIMER_PI3HDX1204_H #define __CROS_EC_USB_RETIMER_PI3HDX1204_H -#define PI3HDX1204_I2C_ADDR_FLAGS 0x60 +#define PI3HDX1204_I2C_ADDR_FLAGS 0x60 /* Register Offset 0 - Activity */ -#define PI3HDX1204_ACTIVITY_OFFSET 0 +#define PI3HDX1204_ACTIVITY_OFFSET 0 /* Register Offset 1 - Not Used */ -#define PI3HDX1204_NOT_USED_OFFSET 1 +#define PI3HDX1204_NOT_USED_OFFSET 1 /* Register Offset 2 - Enable */ -#define PI3HDX1204_ENABLE_OFFSET 2 -#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0 +#define PI3HDX1204_ENABLE_OFFSET 2 +#define PI3HDX1204_ENABLE_ALL_CHANNELS 0xF0 /* Register Offset 3 - EQ setting BIT7-4:CH1, BIT3-0:CH0 */ -#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3 +#define PI3HDX1204_EQ_CH0_CH1_OFFSET 3 /* Register Offset 4 - EQ setting BIT7-4:CH3, BIT3-0:CH2 */ -#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4 +#define PI3HDX1204_EQ_CH2_CH3_OFFSET 4 /* EQ setting for two channel */ -#define PI3HDX1204_EQ_DB25 0x00 -#define PI3HDX1204_EQ_DB80 0x11 -#define PI3HDX1204_EQ_DB110 0x22 -#define PI3HDX1204_EQ_DB220 0x33 -#define PI3HDX1204_EQ_DB410 0x44 -#define PI3HDX1204_EQ_DB710 0x55 -#define PI3HDX1204_EQ_DB900 0x66 -#define PI3HDX1204_EQ_DB1030 0x77 -#define PI3HDX1204_EQ_DB1180 0x88 -#define PI3HDX1204_EQ_DB1390 0x99 -#define PI3HDX1204_EQ_DB1530 0xAA -#define PI3HDX1204_EQ_DB1690 0xBB -#define PI3HDX1204_EQ_DB1790 0xCC -#define PI3HDX1204_EQ_DB1920 0xDD -#define PI3HDX1204_EQ_DB2050 0xEE -#define PI3HDX1204_EQ_DB2220 0xFF +#define PI3HDX1204_EQ_DB25 0x00 +#define PI3HDX1204_EQ_DB80 0x11 +#define PI3HDX1204_EQ_DB110 0x22 +#define PI3HDX1204_EQ_DB220 0x33 +#define PI3HDX1204_EQ_DB410 0x44 +#define PI3HDX1204_EQ_DB710 0x55 +#define PI3HDX1204_EQ_DB900 0x66 +#define PI3HDX1204_EQ_DB1030 0x77 +#define PI3HDX1204_EQ_DB1180 0x88 +#define PI3HDX1204_EQ_DB1390 0x99 +#define PI3HDX1204_EQ_DB1530 0xAA +#define PI3HDX1204_EQ_DB1690 0xBB +#define PI3HDX1204_EQ_DB1790 0xCC +#define PI3HDX1204_EQ_DB1920 0xDD +#define PI3HDX1204_EQ_DB2050 0xEE +#define PI3HDX1204_EQ_DB2220 0xFF /* Register Offset 5 - Output Voltage Swing Setting */ -#define PI3HDX1204_VOD_OFFSET 5 -#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00 -#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55 -#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA -#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF +#define PI3HDX1204_VOD_OFFSET 5 +#define PI3HDX1204_VOD_80_ALL_CHANNELS 0x00 +#define PI3HDX1204_VOD_95_ALL_CHANNELS 0x55 +#define PI3HDX1204_VOD_115_ALL_CHANNELS 0xAA +#define PI3HDX1204_VOD_130_ALL_CHANNELS 0xFF /* Register Offset 6 - Output De-emphasis Setting */ -#define PI3HDX1204_DE_OFFSET 6 -#define PI3HDX1204_DE_DB_0 0x00 -#define PI3HDX1204_DE_DB_MINUS5 0x55 -#define PI3HDX1204_DE_DB_MINUS7 0xAA -#define PI3HDX1204_DE_DB_MINUS10 0xFF +#define PI3HDX1204_DE_OFFSET 6 +#define PI3HDX1204_DE_DB_0 0x00 +#define PI3HDX1204_DE_DB_MINUS5 0x55 +#define PI3HDX1204_DE_DB_MINUS7 0xAA +#define PI3HDX1204_DE_DB_MINUS10 0xFF /* Delay for I2C to be ready after power on. */ #define PI3HDX1204_POWER_ON_DELAY_MS 13 /* Enable or disable the PI3HDX1204. */ -int pi3hdx1204_enable(const int i2c_port, - const uint16_t i2c_addr_flags, +int pi3hdx1204_enable(const int i2c_port, const uint16_t i2c_addr_flags, const int enable); struct pi3hdx1204_tuning { -- cgit v1.2.1 From ac28750528e95aa31275a89492bf4a24b2b654fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:17 -0600 Subject: board/woomax/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2c97230cc5882680b41e6759f9b487d46022983a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729117 Reviewed-by: Jeremy Bettis --- board/woomax/thermal.c | 48 +++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 25 deletions(-) diff --git a/board/woomax/thermal.c b/board/woomax/thermal.c index 98a46aad11..7c35bdea7c 100644 --- a/board/woomax/thermal.c +++ b/board/woomax/thermal.c @@ -16,7 +16,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -38,56 +38,56 @@ struct fan_step { static const struct fan_step fan_step_table[] = { { /* level 0 */ - .on = {-1, -1, 36}, - .off = {-1, -1, 99}, + .on = { -1, -1, 36 }, + .off = { -1, -1, 99 }, .rpm = 0, }, { /* level 1 */ - .on = {-1, -1, 40}, - .off = {-1, -1, 32}, + .on = { -1, -1, 40 }, + .off = { -1, -1, 32 }, .rpm = 2244, }, { /* level 2 */ - .on = {-1, -1, 45}, - .off = {-1, -1, 35}, + .on = { -1, -1, 45 }, + .off = { -1, -1, 35 }, .rpm = 2580, }, { /* level 3 */ - .on = {-1, -1, 50}, - .off = {-1, -1, 40}, + .on = { -1, -1, 50 }, + .off = { -1, -1, 40 }, .rpm = 2824, }, { /* level 4 */ - .on = {-1, -1, 55}, - .off = {-1, -1, 45}, + .on = { -1, -1, 55 }, + .off = { -1, -1, 45 }, .rpm = 3120, }, { /* level 5 */ - .on = {-1, -1, 60}, - .off = {-1, -1, 50}, + .on = { -1, -1, 60 }, + .off = { -1, -1, 50 }, .rpm = 3321, }, { /* level 6 */ - .on = {-1, -1, 70}, - .off = {-1, -1, 55}, + .on = { -1, -1, 70 }, + .off = { -1, -1, 55 }, .rpm = 3780, }, { /* level 7 */ - .on = {-1, -1, 80}, - .off = {-1, -1, 60}, + .on = { -1, -1, 80 }, + .off = { -1, -1, 60 }, .rpm = 4330, }, { /* level 8 */ - .on = {-1, -1, 99}, - .off = {-1, -1, 74}, + .on = { -1, -1, 99 }, + .off = { -1, -1, 74 }, .rpm = 4915, }, }; @@ -109,11 +109,11 @@ int fan_table_to_rpm(int fan, int *temp) */ if (temp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) { if (temp[TEMP_SENSOR_CPU] < - fan_step_table[current_level].off[TEMP_SENSOR_CPU]) + fan_step_table[current_level].off[TEMP_SENSOR_CPU]) current_level = current_level - 1; } else if (temp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) { if (temp[TEMP_SENSOR_CPU] > - fan_step_table[current_level].on[TEMP_SENSOR_CPU]) + fan_step_table[current_level].on[TEMP_SENSOR_CPU]) current_level = current_level + 1; } @@ -130,10 +130,8 @@ int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } -- cgit v1.2.1 From 8560e20a38e7464525dcc7457470703c06e94a18 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:35 -0600 Subject: zephyr/test/drivers/src/bb_retimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb12c6ba58b1164ad7aacced27be4533c4efcc12 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730953 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bb_retimer.c | 285 +++++++++++++++++++---------------- 1 file changed, 154 insertions(+), 131 deletions(-) diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/src/bb_retimer.c index dbe4d3143f..7aab7b4dfa 100644 --- a/zephyr/test/drivers/src/bb_retimer.c +++ b/zephyr/test/drivers/src/bb_retimer.c @@ -26,8 +26,8 @@ #define GPIO_USB_C1_LS_EN_PATH DT_PATH(named_gpios, usb_c1_ls_en) #define GPIO_USB_C1_LS_EN_PORT DT_GPIO_PIN(GPIO_USB_C1_LS_EN_PATH, gpios) #define GPIO_USB_C1_RT_RST_ODL_PATH DT_PATH(named_gpios, usb_c1_rt_rst_odl) -#define GPIO_USB_C1_RT_RST_ODL_PORT \ - DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios) +#define GPIO_USB_C1_RT_RST_ODL_PORT \ + DT_GPIO_PIN(GPIO_USB_C1_RT_RST_ODL_PATH, gpios) #define EMUL_LABEL DT_NODELABEL(usb_c1_bb_retimer_emul) #define BB_RETIMER_ORD DT_DEP_ORD(EMUL_LABEL) @@ -70,9 +70,10 @@ ZTEST_USER(bb_retimer, test_bb_set_state) /* Test none mode */ bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_NONE, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_NONE, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); /* Only UFP mode is set */ @@ -82,9 +83,10 @@ ZTEST_USER(bb_retimer, test_bb_set_state) /* Test USB3 gen1 mode */ prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV10); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_USB_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_USB_ENABLED, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | @@ -94,26 +96,28 @@ ZTEST_USER(bb_retimer, test_bb_set_state) exp_conn, conn); /* Test USB3 gen2 mode */ - disc = pd_get_am_discovery_and_notify_access( - USBC_PORT_C1, TCPCI_MSG_SOP_PRIME); + disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1, + TCPCI_MSG_SOP_PRIME); disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2; prl_set_rev(USBC_PORT_C1, TCPCI_MSG_SOP_PRIME, PD_REV30); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_USB_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_USB_ENABLED, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_USB_3_CONNECTION | - BB_RETIMER_USB_3_SPEED; + BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); /* Test TBT mode */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | @@ -123,35 +127,38 @@ ZTEST_USER(bb_retimer, test_bb_set_state) exp_conn, conn); /* Test USB4 mode */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_USB4_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_USB4_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | - BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_USB4_ENABLED; + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_USB4_ENABLED; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); /* Test USB4 mode with polarity inverted */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_USB4_ENABLED | - USB_PD_MUX_POLARITY_INVERTED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_USB4_ENABLED | + USB_PD_MUX_POLARITY_INVERTED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_CONNECTION_ORIENTATION | - BB_RETIMER_USB4_ENABLED; + BB_RETIMER_CONNECTION_ORIENTATION | BB_RETIMER_USB4_ENABLED; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); /* Test DP mode */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_DP_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_DP_ENABLED, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | @@ -160,29 +167,31 @@ ZTEST_USER(bb_retimer, test_bb_set_state) zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_DP_ENABLED | - USB_PD_MUX_HPD_IRQ, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_DP_ENABLED | + USB_PD_MUX_HPD_IRQ, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_DP_CONNECTION | - BB_RETIMER_IRQ_HPD; + BB_RETIMER_DP_CONNECTION | BB_RETIMER_IRQ_HPD; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_DP_ENABLED | - USB_PD_MUX_HPD_LVL, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_DP_ENABLED | + USB_PD_MUX_HPD_LVL, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_DP_CONNECTION | - BB_RETIMER_HPD_LVL; + BB_RETIMER_DP_CONNECTION | BB_RETIMER_HPD_LVL; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); } @@ -205,9 +214,10 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) /* Test PD mux none mode with DFP should clear all bits in state */ bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678); - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_NONE, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_NONE, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = 0; @@ -215,8 +225,8 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) exp_conn, conn); /* Set active cable type */ - disc = pd_get_am_discovery_and_notify_access( - USBC_PORT_C1, TCPCI_MSG_SOP_PRIME); + disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1, + TCPCI_MSG_SOP_PRIME); disc->identity.idh.product_type = IDH_PTYPE_ACABLE; disc->identity.product_t2.a2_rev30.active_elem = ACTIVE_RETIMER; disc->identity.product_t1.p_rev30.ss = USB_R30_SS_U32_U40_GEN2; @@ -237,8 +247,8 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) disc->svids[0].mode_vdo[0] = cable_resp.raw_value; /* Set device VDO */ - dev_disc = pd_get_am_discovery_and_notify_access( - USBC_PORT_C1, TCPCI_MSG_SOP); + dev_disc = pd_get_am_discovery_and_notify_access(USBC_PORT_C1, + TCPCI_MSG_SOP); dev_disc->svid_cnt = 1; dev_disc->svids[0].svid = USB_VID_INTEL; dev_disc->svids[0].discovery = PD_DISC_COMPLETE; @@ -251,42 +261,43 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value; /* Test USB mode with active cable */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_USB_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_USB_ENABLED, &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_USB_3_CONNECTION | - BB_RETIMER_USB_3_SPEED | - BB_RETIMER_RE_TIMER_DRIVER | - BB_RETIMER_ACTIVE_PASSIVE; + BB_RETIMER_USB_3_CONNECTION | BB_RETIMER_USB_3_SPEED | + BB_RETIMER_RE_TIMER_DRIVER | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); /* Test TBT mode with active cable */ - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_ACTIVE_PASSIVE; + BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); /* Test TBT mode with retimer */ cable_resp.retimer_type = USB_RETIMER; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_RE_TIMER_DRIVER | + BB_RETIMER_TBT_CONNECTION | BB_RETIMER_RE_TIMER_DRIVER | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -295,14 +306,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.retimer_type = USB_NOT_RETIMER; cable_resp.tbt_cable = TBT_CABLE_OPTICAL; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_TBT_CABLE_TYPE | + BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_CABLE_TYPE | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -311,15 +323,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.tbt_cable = TBT_CABLE_NON_OPTICAL; cable_resp.lsrx_comm = UNIDIR_LSRX_COMM; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); - exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_TBT_ACTIVE_LINK_TRAINING | - BB_RETIMER_ACTIVE_PASSIVE; + exp_conn = + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION | + BB_RETIMER_TBT_ACTIVE_LINK_TRAINING | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -327,9 +340,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.lsrx_comm = BIDIR_LSRX_COMM; cable_resp.tbt_cable_speed = TBT_SS_U31_GEN1; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | @@ -341,9 +356,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | @@ -355,9 +372,11 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.tbt_cable_speed = TBT_SS_TBT_GEN3; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | @@ -371,15 +390,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) cable_resp.tbt_cable_speed = TBT_SS_RES_0; cable_resp.tbt_rounded = TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED; disc->svids[0].mode_vdo[0] = cable_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); - exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_TBT_CABLE_GENERATION(1) | - BB_RETIMER_ACTIVE_PASSIVE; + exp_conn = + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION | + BB_RETIMER_TBT_CABLE_GENERATION(1) | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -388,14 +408,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) disc->svids[0].mode_vdo[0] = cable_resp.raw_value; device_resp.tbt_adapter = TBT_ADAPTER_TBT2_LEGACY; dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_TBT_TYPE | + BB_RETIMER_TBT_CONNECTION | BB_RETIMER_TBT_TYPE | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -404,14 +425,15 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) device_resp.tbt_adapter = TBT_ADAPTER_TBT3; device_resp.intel_spec_b0 = VENDOR_SPECIFIC_SUPPORTED; dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_ACTIVE_PASSIVE; + BB_RETIMER_TBT_CONNECTION | BB_RETIMER_ACTIVE_PASSIVE; if (IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE)) exp_conn |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE; @@ -423,15 +445,16 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) device_resp.intel_spec_b0 = VENDOR_SPECIFIC_NOT_SUPPORTED; device_resp.vendor_spec_b1 = VENDOR_SPECIFIC_SUPPORTED; dev_disc->svids[0].mode_vdo[0] = device_resp.raw_value; - zassert_equal(EC_SUCCESS, bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], - USB_PD_MUX_TBT_COMPAT_ENABLED, - &ack_required), NULL); + zassert_equal(EC_SUCCESS, + bb_usb_retimer.set(&usb_muxes[USBC_PORT_C1], + USB_PD_MUX_TBT_COMPAT_ENABLED, + &ack_required), + NULL); zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); - exp_conn = BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_TBT_CONNECTION | - BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE | - BB_RETIMER_ACTIVE_PASSIVE; + exp_conn = + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_TBT_CONNECTION | + BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE | BB_RETIMER_ACTIVE_PASSIVE; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); } @@ -458,9 +481,9 @@ ZTEST_USER(bb_retimer, test_bb_init) /* Enable pins should be set always after init, when AP is on */ zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT), NULL); - zassert_equal(1, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); /* Setup wrong vendor ID */ i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -470,9 +493,9 @@ ZTEST_USER(bb_retimer, test_bb_init) bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL); zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT), NULL); - zassert_equal(1, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); /* Setup emulator fail on device ID read */ i2c_common_emul_set_read_fail_reg(emul, BB_RETIMER_REG_DEVICE_ID); @@ -482,9 +505,9 @@ ZTEST_USER(bb_retimer, test_bb_init) bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL); zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT), NULL); - zassert_equal(1, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); /* Setup wrong device ID */ i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -494,9 +517,9 @@ ZTEST_USER(bb_retimer, test_bb_init) bb_usb_retimer.init(&usb_muxes[USBC_PORT_C1]), NULL); zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT), NULL); - zassert_equal(1, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); /* Test successful init */ bb_emul_set_reg(emul, BB_RETIMER_REG_DEVICE_ID, BB_RETIMER_DEVICE_ID); @@ -504,9 +527,9 @@ ZTEST_USER(bb_retimer, test_bb_init) NULL); zassert_equal(1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_LS_EN_PORT), NULL); - zassert_equal(1, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 1, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); /* Set AP to off state and wait for chipset task */ test_set_chipset_to_g3(); @@ -518,9 +541,9 @@ ZTEST_USER(bb_retimer, test_bb_init) NULL); msleep(1); - zassert_equal(0, gpio_emul_output_get(gpio_dev, - GPIO_USB_C1_RT_RST_ODL_PORT), - NULL); + zassert_equal( + 0, gpio_emul_output_get(gpio_dev, GPIO_USB_C1_RT_RST_ODL_PORT), + NULL); } /** Test BB retimer console command */ -- cgit v1.2.1 From ee550514d7d113191d0f3848772fd94d0d2ec0c0 Mon Sep 17 00:00:00 2001 From: Bobby Casey Date: Wed, 29 Jun 2022 09:21:55 -0400 Subject: chip/stm32/debug_printf.h: Fix header guard The include guard on debug_printf.h was __CROS_EC_DEBUG_H rather than __CROS_EC_DEBUG_PRINTF_H. Unfortunately, debug.h also used __CROS_EC_DEBUG_H which resulted in errors if both were included by a single compilation unit. BRANCH=none BUG=b:180144572 TEST=./util/compare_build.sh -b all -j90 Signed-off-by: Bobby Casey Change-Id: I2354181644e1d50bf06a20ec51d432f4d583b50a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735349 Reviewed-by: Tom Hughes --- chip/stm32/debug_printf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/stm32/debug_printf.h b/chip/stm32/debug_printf.h index dba843985d..6986fb9e61 100644 --- a/chip/stm32/debug_printf.h +++ b/chip/stm32/debug_printf.h @@ -4,8 +4,8 @@ */ /* Synchronous UART debug printf */ -#ifndef __CROS_EC_DEBUG_H -#define __CROS_EC_DEBUG_H +#ifndef __CROS_EC_DEBUG_PRINTF_H +#define __CROS_EC_DEBUG_PRINTF_H #ifdef CONFIG_DEBUG_PRINTF __attribute__((__format__(__printf__, 1, 2))) void @@ -14,4 +14,4 @@ debug_printf(const char *format, ...); #define debug_printf(...) #endif -#endif /* __CROS_EC_DEBUG_H */ +#endif /* __CROS_EC_DEBUG_PRINTF_H */ -- cgit v1.2.1 From 1641c8a4ae88e5fb5e9213f20f16f8a71dca82e0 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 13:44:19 -0600 Subject: zephyr: test: Wrap TYPEC_CONTROL in util function Define host_cmd_typec_control to make it easier to use HOST_CMD_TYPEC_CONTROL in tests. For the time being, only support sub-commands that don't require extra arguments or that require a mode SVID (enter mode). BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I7eb91f0b7fa8ba6414263efe1d578b52420b2185 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724159 Reviewed-by: Aaron Massey --- zephyr/test/drivers/include/test/drivers/utils.h | 14 ++++++++++++++ zephyr/test/drivers/src/utils.c | 13 +++++++++++++ 2 files changed, 27 insertions(+) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index c3fe4db868..d934144a67 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -8,6 +8,7 @@ #include #include +#include #include #include "charger.h" @@ -451,6 +452,19 @@ int host_cmd_motion_sense_spoof(uint8_t sensor_num, uint8_t enable, void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type, void *response, size_t response_size); +/** + * Run the host command to control PD port behavior. For now, this function only + * supports entering and exiting modes. + * + * @param port The USB-C port number + * @param command Sub-command to perform on the port + * @param mode The mode to enter if command is + * TYPEC_CONTROL_COMMAND_ENTER_MODE. + * @param response_size Number of bytes in response + */ +void host_cmd_typec_control(int port, enum typec_control_command command, + enum typec_mode mode); + #define GPIO_ACOK_OD_NODE DT_NODELABEL(gpio_acok_od) #define GPIO_ACOK_OD_PIN DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios) diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/src/utils.c index b46f87f83c..e7c4e2d145 100644 --- a/zephyr/test/drivers/src/utils.c +++ b/zephyr/test/drivers/src/utils.c @@ -367,6 +367,19 @@ void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type, "Failed to get Type-C state for port %d", port); } +void host_cmd_typec_control(int port, enum typec_control_command command, + enum typec_mode mode) +{ + struct ec_params_typec_control params = { .port = port, + .command = command, + .mode_to_enter = mode }; + struct host_cmd_handler_args args = + BUILD_HOST_COMMAND_PARAMS(EC_CMD_TYPEC_CONTROL, 0, params); + + zassume_ok(host_command_process(&args), + "Failed to send Type-C control for port %d", port); +} + K_HEAP_DEFINE(test_heap, 2048); void *test_malloc(size_t bytes) -- cgit v1.2.1 From b9dc7344a8a06f3fe557eefff25ae03fd4570987 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 23 Jun 2022 13:09:34 -0700 Subject: charge_manager: Export is_pd_port is_pd_port tells whether a port is a PD port or not. This patch makes it available to other compilation units. BUG=b:216206104 BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri Change-Id: I12dde5032b9e6422eed504591d1d005895b1daac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733414 Reviewed-by: Tim Wawrzynczak --- common/charge_manager.c | 2 +- include/charge_manager.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index 9d90aa6e19..c5eb93f704 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -155,7 +155,7 @@ enum charge_manager_change_type { CHANGE_DUALROLE, }; -static int is_pd_port(int port) +int is_pd_port(int port) { return port >= 0 && port < board_get_usb_pd_port_count(); } diff --git a/include/charge_manager.h b/include/charge_manager.h index a579674bb0..cca8c9ce25 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -372,4 +372,7 @@ board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r); * @param port Dedicated charge port. */ __override_proto int board_get_vbus_voltage(int port); + +int is_pd_port(int port); + #endif /* __CROS_EC_CHARGE_MANAGER_H */ -- cgit v1.2.1 From 4e3333699f1846ef490b6765048227ac658653c7 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 23 Jun 2022 20:34:12 +0000 Subject: throttle_ap: Add throttle_gpu and THROTTLE_SRC_AC throttle_gpu will be used to throttle a GPU. THROTTLE_SRC_AC indicates throttling is needed for a charger change. BUG=b:216485035 BRANCH=None TEST=None Signed-off-by: Daisuke Nojiri Change-Id: Ide3094d0a757b36db2730e148d35f5ca9b0e12d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733415 Reviewed-by: Tim Wawrzynczak --- include/throttle_ap.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/throttle_ap.h b/include/throttle_ap.h index 09669d70b1..20ce3ecf59 100644 --- a/include/throttle_ap.h +++ b/include/throttle_ap.h @@ -32,6 +32,7 @@ enum throttle_sources { THROTTLE_SRC_THERMAL = 0, THROTTLE_SRC_BAT_DISCHG_CURRENT, THROTTLE_SRC_BAT_VOLTAGE, + THROTTLE_SRC_AC, }; /** @@ -105,4 +106,8 @@ static inline void throttle_ap(enum throttle_level level, {} #endif +void throttle_gpu(enum throttle_level level, + enum throttle_type type, + enum throttle_sources source); + #endif /* __CROS_EC_THROTTLE_AP_H */ -- cgit v1.2.1 From e82473e6eed1a19cf9e83b196c305dfae0ff16a6 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 19:08:12 +0000 Subject: charger: Add get_vsys_voltage get_vsys_voltage returns a Vsys voltage measured by the charger if it's supported by the charger. BUG=None BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri Change-Id: I49a024860504ee4c8ec172b025dbb3cdaf3ac214 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733416 Reviewed-by: Tim Wawrzynczak --- common/charger.c | 27 +++++++++++++++++++++++++-- include/charger.h | 7 +++++++ 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/common/charger.c b/common/charger.c index e29f433509..c3f032f908 100644 --- a/common/charger.c +++ b/common/charger.c @@ -500,7 +500,7 @@ enum ec_error_list charger_enable_bypass_mode(int chgnum, int enable) return chg_chips[chgnum].drv->enable_bypass_mode(chgnum, enable); } -enum ec_error_list charger_get_vbus_voltage(int port, int *voltage) +static int charger_get_valid_chgnum(int port) { int chgnum = 0; @@ -510,15 +510,38 @@ enum ec_error_list charger_get_vbus_voltage(int port, int *voltage) if ((chgnum < 0) || (chgnum >= board_get_charger_chip_count())) { CPRINTS("%s(%d) Invalid charger!", __func__, chgnum); - return 0; + return -1; } + return chgnum; +} + +enum ec_error_list charger_get_vbus_voltage(int port, int *voltage) +{ + int chgnum = charger_get_valid_chgnum(port); + + if (chgnum < 0) + return EC_ERROR_INVAL; + if (!chg_chips[chgnum].drv->get_vbus_voltage) return EC_ERROR_UNIMPLEMENTED; return chg_chips[chgnum].drv->get_vbus_voltage(chgnum, port, voltage); } +enum ec_error_list charger_get_vsys_voltage(int port, int *voltage) +{ + int chgnum = charger_get_valid_chgnum(port); + + if (chgnum < 0) + return EC_ERROR_INVAL; + + if (!chg_chips[chgnum].drv->get_vsys_voltage) + return EC_ERROR_UNIMPLEMENTED; + + return chg_chips[chgnum].drv->get_vsys_voltage(chgnum, port, voltage); +} + enum ec_error_list charger_set_input_current_limit(int chgnum, int input_current) { diff --git a/include/charger.h b/include/charger.h index 66130ce3a5..5a7188f4e3 100644 --- a/include/charger.h +++ b/include/charger.h @@ -98,6 +98,10 @@ struct charger_drv { enum ec_error_list (*get_vbus_voltage)(int chgnum, int port, int *voltage); + /* Get the Vsys voltage (mV) from the charger */ + enum ec_error_list (*get_vsys_voltage)(int chgnum, int port, + int *voltage); + /* Set desired input current value */ enum ec_error_list (*set_input_current_limit)(int chgnum, int input_current); @@ -277,6 +281,9 @@ enum ec_error_list charger_discharge_on_ac(int enable); /* Get the VBUS voltage (mV) from the charger */ enum ec_error_list charger_get_vbus_voltage(int port, int *voltage); +/* Get the Vsys voltage (mV) from the charger */ +enum ec_error_list charger_get_vsys_voltage(int port, int *voltage); + /* Custom board function to discharge battery when on AC power */ int board_discharge_on_ac(int enable); -- cgit v1.2.1 From 23d32e0599f0d2e4e06675776e15e2639e9793a2 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Wed, 29 Jun 2022 11:56:19 -0600 Subject: test: add shuffle utility for testing team The testing team is working to find test order dependency bugs. This small script helps us run the tests _n_ times quickly to verify or detect new bugs. It should be removed in a month or so. BRANCH=none BUG=none TEST=./util/shuffle_test.h bmi260.c: Signed-off-by: Yuval Peress Change-Id: I8fcfb006644ee51205cb41c4c4cc63d4dcecd7a2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735631 Reviewed-by: Jeremy Bettis --- util/shuffle_test.sh | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100755 util/shuffle_test.sh diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh new file mode 100755 index 0000000000..55c9055e06 --- /dev/null +++ b/util/shuffle_test.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +set +x + +zmake build --clobber test-drivers || exit 1 + +echo "Searching for '${1}'..." +found_errors=0 +loop_count=100 +EXECUTABLE=./build/zephyr/test-drivers/build-singleimage/zephyr/zephyr.exe +while [ "${loop_count}" -gt 0 ]; do + seed=${RANDOM} + echo "[$((100 - loop_count))] Using seed=${seed}" + error_count=$(timeout 150s "${EXECUTABLE}" -seed="${seed}" 2>&1 | + grep -c "${1}") + status=$? + + if [ "${status}" -eq 124 ]; then + echo " Timeout" + elif [ "${status}" -ne 0 ]; then + echo " Error/timeout" + fi + if [ "${error_count}" -gt 0 ]; then + echo " Found ${error_count} errors matching '${1}'" + fi + + found_errors=$((found_errors + error_count)) + loop_count=$((loop_count - 1)) +done + +if [ "${found_errors}" -ne 0 ]; then + exit 1 +fi -- cgit v1.2.1 From f1c50a774a609b8dc3d616071824dbc4ef78af87 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 13:49:20 -0600 Subject: zephyr: test: Enter DisplayPort via host command Enable AP-driven mode entry in the test-drivers config. Use a host command to drive DP mode entry in tests. This covers a bit more DPM code related to mode entry and supports future testing of TBT3 and USB4 mode entry using the flow from production systems. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I6e5587d76fcedd1e97496abe0565ba7ebc3802f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724160 Reviewed-by: Aaron Massey --- zephyr/test/drivers/prj.conf | 1 + zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/zephyr/test/drivers/prj.conf b/zephyr/test/drivers/prj.conf index f006bc0117..152dc2d8db 100644 --- a/zephyr/test/drivers/prj.conf +++ b/zephyr/test/drivers/prj.conf @@ -119,6 +119,7 @@ CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815_FORCE_DID=y CONFIG_PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_REQUIRE_AP_MODE_ENTRY=y CONFIG_ESPI=y CONFIG_ESPI_EMUL=y diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 851f3c0da2..41cbe0a988 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -207,6 +207,12 @@ ZTEST_F(usbc_alt_mode, verify_discovery) ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) { + /* TODO(b/237553647): Test EC-driven mode entry (requires a separate + * config). + */ + host_cmd_typec_control(TEST_PORT, + TYPEC_CONTROL_COMMAND_ENTER_MODE, TYPEC_MODE_DP); k_sleep(K_SECONDS(1)); + /* Verify host command when VDOs are present. */ struct ec_params_usb_pd_get_mode_request params = { .port = TEST_PORT, -- cgit v1.2.1 From 85990309dc63d80cf3f1b940df2dc06129fef2e9 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 13:53:14 -0600 Subject: zephyr: emul: Support Exit Mode in PD partner Respond to SOP Exit Mode REQ VDMs in USB PD partner emulator. For now, only support exiting DisplayPort mode. This supports testing Exit Mode flows in the TCPM. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I92ee8046932c076f99c103523ec9873089cf1a85 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724161 Reviewed-by: Aaron Massey --- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 21725f11f0..9c9d3d8268 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -647,6 +647,24 @@ tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data, 0); } return TCPCI_PARTNER_COMMON_MSG_HANDLED; + case CMD_EXIT_MODE: + if (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT) { + uint32_t response_vdm_header; + + if (data->displayport_configured) { + data->displayport_configured = false; + response_vdm_header = VDO( + USB_SID_DISPLAYPORT, true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_EXIT_MODE); + } else { + response_vdm_header = VDO( + USB_SID_DISPLAYPORT, true, + VDO_CMDT(CMDT_RSP_NAK) | CMD_EXIT_MODE); + } + tcpci_partner_send_data_msg(data, PD_DATA_VENDOR_DEF, + &response_vdm_header, 1, 0); + } + return TCPCI_PARTNER_COMMON_MSG_HANDLED; case CMD_DP_STATUS: if (data->dp_status_vdos > 0 && (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT)) { -- cgit v1.2.1 From 0b941e9b00189c6e6fc388c9935c2a5596782a80 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 14:04:12 -0600 Subject: zephyr: test: Verify DisplayPort mode reentry Verify that TCPM can enter DP mode, then exit, then re-enter. Cover Exit Mode flow in DPM and DP state machines. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I823b07989b6036fb13fd03a50947af98c2634ed2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724162 Reviewed-by: Aaron Massey --- .../drivers/src/integration/usbc/usb_alt_mode.c | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 41cbe0a988..5d457b846e 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -236,5 +236,45 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) zassert_true(fixture->partner.displayport_configured, NULL); } +ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + /* DPM configures the partner on DP mode entry */ + /* Verify port partner thinks its configured for DisplayPort */ + zassert_true(fixture->partner.displayport_configured, NULL); + + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_EXIT_MODES, 0); + k_sleep(K_SECONDS(1)); + zassert_false(fixture->partner.displayport_configured, NULL); + + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + zassert_true(fixture->partner.displayport_configured, NULL); + + /* Verify that DisplayPort is the active alternate mode. */ + /* TODO(b/235984702): Wrap EC_CMD_USB_PD_GET_AMODE in a function. */ + struct ec_params_usb_pd_get_mode_request params = { + .port = TEST_PORT, + .svid_idx = 0, + }; + struct ec_params_usb_pd_get_mode_response response; + struct host_cmd_handler_args args = BUILD_HOST_COMMAND( + EC_CMD_USB_PD_GET_AMODE, 0, response, params); + + zassume_ok(host_command_process(&args), NULL); + zassume_ok(args.result, NULL); + + /* Response should be populated with a DisplayPort VDO */ + zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); + zassert_equal(response.vdo[0], + fixture->partner.modes_vdm[response.opos], NULL); + +} + ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, usbc_alt_mode_before, usbc_alt_mode_after, NULL); -- cgit v1.2.1 From e4c264209e509db0b4ed674dab7012f40ca00d32 Mon Sep 17 00:00:00 2001 From: Jonathon Murphy Date: Wed, 29 Jun 2022 20:04:22 +0000 Subject: Revert "Skyrim: Enable SoC OCP and thermal interrupts" This reverts commit f5dfa5378ab30df20ccc40d1a30d3bf635432d48. Reason for revert: 15W SKUs are pulling OCP, need to understand and debug. This is causing 15W SKUs not to boot Original change's description: > Skyrim: Enable SoC OCP and thermal interrupts > > Enable interrupts for SoC OCP and thermal warnings, and shutdown on each > with a console print to log the scenario. > > BRANCH=None > BUG=b:231996265 > TEST=on skyrim, run a normal boot/shutdown sequence and verify neither > interrupt is erroneously detected > > Signed-off-by: Diana Z > Change-Id: Ic5af489965a6a2e88e5eba23e35d13bdfb1bdb8b > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712024 > Reviewed-by: Robert Zieba > Commit-Queue: Robert Zieba Bug: b:231996265 Change-Id: If3128e5b1d8aeec1ec58ee39be745f39c87d17b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735637 Commit-Queue: Diana Z Tested-by: Jonathon Murphy Reviewed-by: Diana Z Auto-Submit: Jonathon Murphy --- zephyr/projects/skyrim/interrupts.dts | 10 ---------- zephyr/projects/skyrim/power_signals.c | 29 ----------------------------- zephyr/projects/skyrim/skyrim.dts | 6 ++++-- 3 files changed, 4 insertions(+), 41 deletions(-) diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index c72e468b58..14a01c8402 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -42,16 +42,6 @@ flags = ; handler = "baseboard_set_en_pwr_pcore"; }; - int_soc_pcore_ocp: soc_pcore_ocp { - irq-pin = <&gpio_pcore_ocp_r_l>; - flags = ; - handler = "baseboard_soc_pcore_ocp"; - }; - int_soc_thermtrip: soc_thermtrip { - irq-pin = <&gpio_soc_thermtrip_odl>; - flags = ; - handler = "baseboard_soc_thermtrip"; - }; int_volume_up: volume_up { irq-pin = <&gpio_volup_btn_odl>; flags = ; diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index 3b226eb0f9..16847ba608 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -76,26 +76,9 @@ static void baseboard_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3)); - - /* Enable thermtrip interrupt */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip)); } DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); -static void baseboard_resume(void) -{ - /* Enable Pcore OCP interrupt, which is powered in S0 */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_resume, HOOK_PRIO_DEFAULT); - -static void baseboard_suspend(void) -{ - /* Disable Pcore OCP interrupt */ - gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_pcore_ocp)); -} -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_suspend, HOOK_PRIO_DEFAULT); - /** * b/227296844: On G3->S5, wait for RSMRST_L to be deasserted before asserting * PCH_PWRBTN_L. This can be as long as ~65ms after cold boot. Then wait an @@ -209,15 +192,3 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal) /* Chain off the normal power signal interrupt handler */ power_signal_interrupt(signal); } - -void baseboard_soc_thermtrip(enum gpio_signal signal) -{ - ccprints("SoC thermtrip reported, shutting down"); - chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); -} - -void baseboard_soc_pcore_ocp(enum gpio_signal signal) -{ - ccprints("SoC Pcore OCP reported, shutting down"); - chipset_force_shutdown(CHIPSET_SHUTDOWN_BOARD_CUSTOM); -} diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 5fc8b52907..ebccda5eb9 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -24,7 +24,8 @@ gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { gpios = <&gpioa 3 GPIO_INPUT>; }; - gpio_soc_thermtrip_odl: soc_thermtrip_odl { + /* TODO: Add interrupt handler */ + soc_thermtrip_odl { gpios = <&gpio9 5 GPIO_INPUT>; }; gpio_hub_rst: hub_rst { @@ -37,7 +38,8 @@ gpio_ec_soc_pwr_good: ec_soc_pwr_good { gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; }; - gpio_pcore_ocp_r_l: pcore_ocp_r_l { + /* TODO: Add interrupt handler to shut down */ + pcore_ocp_r_l { gpios = <&gpioa 5 GPIO_INPUT>; }; gpio_usb_hub_fault_q_odl: usb_hub_fault_q_odl { -- cgit v1.2.1 From d32978f7d43da4fb7844e87749685fcc8a4cc91d Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 12:13:02 -0700 Subject: chgstv2: Support bypass mode This patch adds bypass mode to charge_state_v2. Bypass mode allows a charger to deliver the input power directly from an adapter to the system, avoiding loss in buck-boost conversion. BUG=b:214057333 BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri Change-Id: Ia3c244190416cd9b9d89dac67cccf9bc033ed691 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733417 Reviewed-by: Tim Wawrzynczak --- common/charge_state_v2.c | 17 +++++++++++++++++ include/battery_smart.h | 1 + include/charge_state_v2.h | 7 +++++++ 3 files changed, 25 insertions(+) diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index 396e841d07..6e2ee3642f 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -945,6 +945,11 @@ test_mockable int calc_is_full(void) return ret; } +__overridable int board_should_charger_bypass(void) +{ + return false; +} + /* * Ask the charger for some voltage and current. If either value is 0, * charging is disabled; otherwise it's enabled. Negative values are ignored. @@ -953,6 +958,7 @@ static int charge_request(int voltage, int current) { int r1 = EC_SUCCESS, r2 = EC_SUCCESS, r3 = EC_SUCCESS, r4 = EC_SUCCESS; static int prev_volt, prev_curr; + bool should_bypass; if (!voltage || !current) { #ifdef CONFIG_CHARGER_NARROW_VDC @@ -979,6 +985,17 @@ static int charge_request(int voltage, int current) CPRINTS("%s(%dmV, %dmA)", __func__, voltage, current); } + /* + * Enable bypass mode if applicable. Transition from Bypass to Bypass + + * CHRG or backward is done after this call (by set_current & set_mode) + * thus not done here. Similarly, when bypass is disabled, transitioning + * from nvdc + chrg will be done separately. + */ + should_bypass = board_should_charger_bypass(); + if ((should_bypass && !(curr.chg.status & CHARGER_BYPASS_MODE)) + || (!should_bypass && (curr.chg.status & CHARGER_BYPASS_MODE))) + charger_enable_bypass_mode(0, should_bypass); + /* * Set current before voltage so that if we are just starting * to charge, we allow some time (i2c delay) for charging circuit to diff --git a/include/battery_smart.h b/include/battery_smart.h index c37b7c692c..cdc69e4ffd 100644 --- a/include/battery_smart.h +++ b/include/battery_smart.h @@ -150,6 +150,7 @@ #define CHARGER_POWER_FAIL BIT(13) #define CHARGER_BATTERY_PRESENT BIT(14) #define CHARGER_AC_PRESENT BIT(15) +#define CHARGER_BYPASS_MODE BIT(16) /* Charger specification info */ #define INFO_CHARGER_SPEC(INFO) ((INFO) & 0xf) #define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h index cdf6872aab..e94a31c242 100644 --- a/include/charge_state_v2.h +++ b/include/charge_state_v2.h @@ -223,4 +223,11 @@ __test_only void reset_prev_disp_charge(void); */ __test_only bool charging_progress_displayed(void); +/** + * Callback for boards to request charger to enable bypass mode on/off. + * + * @return True for requesting bypass on. False for requesting bypass off. + */ +int board_should_charger_bypass(void); + #endif /* __CROS_EC_CHARGE_STATE_V2_H */ -- cgit v1.2.1 From 411dc5ddce1718bb741a6fb4147e79116d3cd275 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 21:50:25 +0000 Subject: chgstv2: Wake on HOOK_POWER_SUPPLY_CHANGE This patch makes the charger task wake on HOOK_POWER_SUPPLY_CHANGE so that it can respond to power supplier changes (of the same port). BUG=b:214057333 BRANCH=None TEST=Agah. Plug USB-C & BJ adapters. Unplug USB-C & BJ adapters. Signed-off-by: Daisuke Nojiri Change-Id: Ic050e872871b110f0c6da44ad1b376a169fb2103 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733418 Reviewed-by: Tim Wawrzynczak --- common/charge_state_v2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index 6e2ee3642f..ba46a4f194 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -1465,6 +1465,7 @@ static void charge_wakeup(void) } DECLARE_HOOK(HOOK_CHIPSET_RESUME, charge_wakeup, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_AC_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, charge_wakeup, HOOK_PRIO_DEFAULT); #ifdef CONFIG_EC_EC_COMM_BATTERY_CLIENT /* Reset the base on S5->S0 transition. */ -- cgit v1.2.1 From 58f0246dbebf877084bd09ffc841abeff2367866 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:19 -0600 Subject: board/nocturne_fp/board_ro.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Ie68d506cc96702fec0c9443b7a4ed2d53bf04778 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728763 Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- board/nocturne_fp/board_ro.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/nocturne_fp/board_ro.c b/board/nocturne_fp/board_ro.c index 7f20002435..25c1114024 100644 --- a/board/nocturne_fp/board_ro.c +++ b/board/nocturne_fp/board_ro.c @@ -15,7 +15,6 @@ #error "This file should only be built for RO." #endif - /** * Disable restricted commands when the system is locked. * -- cgit v1.2.1 From e0589cd5e299588fbc6ff5aadb48894e658c3772 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:29 -0600 Subject: driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Ic49ad37fcb46834d5743c2c5f61540124edf971d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729944 Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/bep/fpc1035_private.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/fingerprint/fpc/bep/fpc1035_private.h b/driver/fingerprint/fpc/bep/fpc1035_private.h index 695228898b..a876a840ab 100644 --- a/driver/fingerprint/fpc/bep/fpc1035_private.h +++ b/driver/fingerprint/fpc/bep/fpc1035_private.h @@ -13,19 +13,19 @@ #define FP_SENSOR_NAME "FPC1035" /* Sensor pixel resolution */ -#define FP_SENSOR_RES_X (112) /**< Sensor width */ -#define FP_SENSOR_RES_Y (88) /**< Sensor height */ -#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel */ +#define FP_SENSOR_RES_X (112) /**< Sensor width */ +#define FP_SENSOR_RES_Y (88) /**< Sensor height */ +#define FP_SENSOR_RES_BPP (8) /**< Resolution bits per pixel */ /* * Sensor image size * * Value from fpc_bep_image_get_buffer_size(): (112*88)+660 */ -#define FP_SENSOR_IMAGE_SIZE (10516) -#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y) +#define FP_SENSOR_IMAGE_SIZE (10516) +#define FP_SENSOR_REAL_IMAGE_SIZE (FP_SENSOR_RES_X * FP_SENSOR_RES_Y) /* Offset of image data in fp_buffer */ -#define FP_SENSOR_IMAGE_OFFSET (400) +#define FP_SENSOR_IMAGE_OFFSET (400) /* * Constant value for the enrollment data size @@ -41,9 +41,9 @@ * * Template size + alignment padding + size of template size variable */ -#define FP_ALGORITHM_TEMPLATE_SIZE (14373 + 3 + 4) +#define FP_ALGORITHM_TEMPLATE_SIZE (14373 + 3 + 4) /* Max number of templates stored / matched against */ -#define FP_MAX_FINGER_COUNT (5) +#define FP_MAX_FINGER_COUNT (5) #endif /* __CROS_EC_FPC1035_PRIVATE_H */ -- cgit v1.2.1 From 6e7b6118216bf3c6ac9118f36eec1bae158cb112 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:32 -0600 Subject: driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I561f719b6da27d3f6bc65836e23ec26327dd2620 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729945 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes --- driver/fingerprint/fpc/bep/fpc_bio_algorithm.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h index 1bf598a3ee..08a4d7c7e1 100644 --- a/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h +++ b/driver/fingerprint/fpc/bep/fpc_bio_algorithm.h @@ -66,12 +66,12 @@ int bio_algorithm_exit(void); * - BIO_TEMPLATE_LOW_COVERAGE when matching could not be performed due to * finger covering too little area of the sensor */ -#define BIO_TEMPLATE_NO_MATCH 0 -#define BIO_TEMPLATE_MATCH 1 -#define BIO_TEMPLATE_MATCH_UPDATED 3 +#define BIO_TEMPLATE_NO_MATCH 0 +#define BIO_TEMPLATE_MATCH 1 +#define BIO_TEMPLATE_MATCH_UPDATED 3 #define BIO_TEMPLATE_MATCH_UPDATE_FAILED 5 -#define BIO_TEMPLATE_LOW_QUALITY 2 -#define BIO_TEMPLATE_LOW_COVERAGE 4 +#define BIO_TEMPLATE_LOW_QUALITY 2 +#define BIO_TEMPLATE_LOW_COVERAGE 4 int bio_template_image_match_list(bio_template_t templ, uint32_t num_templ, bio_image_t image, int32_t *match_index, @@ -101,14 +101,14 @@ int bio_enrollment_begin(bio_enrollment_t *enrollment); * finger covering too little area of the sensor * - BIO_ENROLLMENT_INTERNAL_ERROR when an internal error occurred */ -#define BIO_ENROLLMENT_OK 0 -#define BIO_ENROLLMENT_LOW_QUALITY 1 -#define BIO_ENROLLMENT_IMMOBILE 2 -#define BIO_ENROLLMENT_LOW_COVERAGE 3 -#define BIO_ENROLLMENT_INTERNAL_ERROR 5 +#define BIO_ENROLLMENT_OK 0 +#define BIO_ENROLLMENT_LOW_QUALITY 1 +#define BIO_ENROLLMENT_IMMOBILE 2 +#define BIO_ENROLLMENT_LOW_COVERAGE 3 +#define BIO_ENROLLMENT_INTERNAL_ERROR 5 /* Can be used to detect if image was usable for enrollment or not. */ -#define BIO_ENROLLMENT_PROBLEM_MASK 1 +#define BIO_ENROLLMENT_PROBLEM_MASK 1 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image); /* * Returns percent of coverage accumulated during enrollment process. -- cgit v1.2.1 From eb1e1bed8d0dfa221271097e112ad25b08fbdeb6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:42 -0600 Subject: driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Ibfea8a03a8b66b5a6323a07aa242bea9eb59153d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729973 Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/libfp/fpc1145_private.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc1145_private.h b/driver/fingerprint/fpc/libfp/fpc1145_private.h index 399c75118b..e5cf9f57ca 100644 --- a/driver/fingerprint/fpc/libfp/fpc1145_private.h +++ b/driver/fingerprint/fpc/libfp/fpc1145_private.h @@ -21,9 +21,9 @@ #define FP_SENSOR_NAME "FPC1145" /* Sensor pixel resolution */ -#define FP_SENSOR_RES_Y 192 -#define FP_SENSOR_RES_X 56 -#define FP_SENSOR_RES_BPP 8 +#define FP_SENSOR_RES_Y 192 +#define FP_SENSOR_RES_X 56 +#define FP_SENSOR_RES_BPP 8 /* Acquired finger frame definitions */ #define FP_SENSOR_IMAGE_SIZE_MODE_VENDOR (35460) @@ -33,17 +33,17 @@ * corresponding value in the MQT tool fputils.py must be changed too. * See b/111443750 for context. */ -#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL (24408) +#define FP_SENSOR_IMAGE_SIZE_MODE_QUAL (24408) -#define FP_SENSOR_IMAGE_SIZE FP_SENSOR_IMAGE_SIZE_MODE_VENDOR +#define FP_SENSOR_IMAGE_SIZE FP_SENSOR_IMAGE_SIZE_MODE_VENDOR #define FP_SENSOR_IMAGE_OFFSET 2340 /* Opaque FPC context */ #define FP_SENSOR_CONTEXT_SIZE 4944 /* Algorithm buffer sizes */ -#define FP_ALGORITHM_ENROLLMENT_SIZE 28 -#define FP_ALGORITHM_TEMPLATE_SIZE 47552 +#define FP_ALGORITHM_ENROLLMENT_SIZE 28 +#define FP_ALGORITHM_TEMPLATE_SIZE 47552 /* Max number of templates stored / matched against */ #define FP_MAX_FINGER_COUNT 5 -- cgit v1.2.1 From c1f9dd3cf88621c76344d5f2e9cb1aa39b2b0ece Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:45 -0600 Subject: driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: Ieda9ca814ea98ca1d0fe1a270f13bfe9b29fb586 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729974 Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h index 9c00b14640..3b9db033da 100644 --- a/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h +++ b/driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h @@ -196,12 +196,12 @@ int bio_enrollment_begin(bio_sensor_t sensor, bio_enrollment_t *enrollment); * - BIO_ENROLLMENT_LOW_COVERAGE when image could not be used due to * finger covering too little area of the sensor */ -#define BIO_ENROLLMENT_OK 0 -#define BIO_ENROLLMENT_IMMOBILE 2 -#define BIO_ENROLLMENT_LOW_QUALITY 1 -#define BIO_ENROLLMENT_LOW_COVERAGE 3 +#define BIO_ENROLLMENT_OK 0 +#define BIO_ENROLLMENT_IMMOBILE 2 +#define BIO_ENROLLMENT_LOW_QUALITY 1 +#define BIO_ENROLLMENT_LOW_COVERAGE 3 /* Can be used to detect if image was usable for enrollment or not. */ -#define BIO_ENROLLMENT_PROBLEM_MASK 1 +#define BIO_ENROLLMENT_PROBLEM_MASK 1 int bio_enrollment_add_image(bio_enrollment_t enrollment, bio_image_t image); /* * Indicates whether there is enough data in the enrollment for it to be @@ -236,10 +236,10 @@ int bio_enrollment_get_percent_complete(bio_enrollment_t enrollment); int bio_enrollment_finish(bio_enrollment_t enrollment, bio_template_t *tmpl); typedef struct { - int32_t coverage; /* Sensor coverage in range [0..100] */ - int32_t quality; /* Image quality in range [0..100] */ + int32_t coverage; /* Sensor coverage in range [0..100] */ + int32_t quality; /* Image quality in range [0..100] */ int32_t min_coverage; /* Minimum coverage accepted by enroll */ - int32_t min_quality; /* Minimum image quality accepted by enroll */ + int32_t min_quality; /* Minimum image quality accepted by enroll */ } bio_image_status_t; /* -- cgit v1.2.1 From 5e9c85c9b1ccec4a471fc1e6592dc64cd60a203c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:52 -0600 Subject: driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I07dc3df1f97ece2d11a26fee8c2330060079cae8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729977 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis Commit-Queue: Tom Hughes --- driver/fingerprint/fpc/libfp/fpc_sensor_pal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c index 35c07b464a..2ac4d9d7a6 100644 --- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c +++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.c @@ -14,8 +14,8 @@ #include "uart.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args) -#define CPRINTS(format, args...) cprints(CC_FP, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args) +#define CPRINTS(format, args...) cprints(CC_FP, format, ##args) void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...) { -- cgit v1.2.1 From 45a5c1427b8da6117046cbef8eb0ab94aa37abc7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:30 -0600 Subject: test/fpsensor_hw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4921435a853da5a79d9f404bfb22600ac9b58b7f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730503 Reviewed-by: Jeremy Bettis Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes --- test/fpsensor_hw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/test/fpsensor_hw.c b/test/fpsensor_hw.c index f420001665..306046e2a2 100644 --- a/test/fpsensor_hw.c +++ b/test/fpsensor_hw.c @@ -32,7 +32,6 @@ test_static int test_fp_check_hwid(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { RUN_TEST(test_fp_check_hwid); -- cgit v1.2.1 From 0f1f79a07b8019a2375dbedcf15d9d0f7d3d0041 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:38 -0600 Subject: test/stm32f_rtc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id33ec7f442223a25bd1fde3050638596865f5148 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730524 Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/stm32f_rtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/stm32f_rtc.c b/test/stm32f_rtc.c index b9b48ec043..77e6e5d256 100644 --- a/test/stm32f_rtc.c +++ b/test/stm32f_rtc.c @@ -67,7 +67,7 @@ test_static int test_rtc_match_delay(void) } ccprintf("Expected number of RTC alarm interrupts %d\n", - rtc_match_delay_iterations); + rtc_match_delay_iterations); ccprintf("Actual number of RTC alarm interrupts %d\n", rtc_fired); /* Make sure each set_rtc_alarm() generated the interrupt. */ -- cgit v1.2.1 From 582d959fa5d21cf1c4dd4fb5d7c6924d5ae056e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:48 -0600 Subject: test/system_is_locked.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaaae0e420e256e4927a2f9ef90010e12f7dd61b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730526 Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/system_is_locked.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/system_is_locked.c b/test/system_is_locked.c index 9870f77ebc..f4e5e64159 100644 --- a/test/system_is_locked.c +++ b/test/system_is_locked.c @@ -60,7 +60,7 @@ void test_run_step(uint32_t state) else if (write_protect_enabled) { ccprintf("Request RO protection at boot\n"); crec_flash_set_protect(EC_FLASH_PROTECT_RO_AT_BOOT, - EC_FLASH_PROTECT_RO_AT_BOOT); + EC_FLASH_PROTECT_RO_AT_BOOT); test_reboot_to_next_step(TEST_STATE_STEP_2); } else { /* Write protect is disabled, nothing else to do */ -- cgit v1.2.1 From a0751778f42b9e333e6ab20cad6ce9673a5f339d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:21 -0600 Subject: board/nocturne_fp/ro_workarounds.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I5099ad5aa2c16e76cd7c68da7abb93861b57a1a8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728764 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes --- board/nocturne_fp/ro_workarounds.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/board/nocturne_fp/ro_workarounds.c b/board/nocturne_fp/ro_workarounds.c index e6417ddc08..1dcf6d5602 100644 --- a/board/nocturne_fp/ro_workarounds.c +++ b/board/nocturne_fp/ro_workarounds.c @@ -19,7 +19,7 @@ #include "watchdog.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* * We only patch RW to ensure that future ROs have correct behavior. @@ -30,7 +30,7 @@ * Add in ap-off flag to be able to detect on next boot. * No other code in this build uses this ap-off reset flag. */ -#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON|EC_RESET_FLAG_AP_OFF) +#define FORGE_PORFLAG_FLAGS (EC_RESET_FLAG_POWER_ON | EC_RESET_FLAG_AP_OFF) static void wp_change_deferred(void) { @@ -75,8 +75,7 @@ void wp_event(enum gpio_signal signal) * This function is also called from system_reset to set the final save * reset flags, before an actual planned reset. */ -__override -void bkpdata_write_reset_flags(uint32_t save_flags) +__override void bkpdata_write_reset_flags(uint32_t save_flags) { /* Preserve flags in case a reset pulse occurs */ if (!gpio_get_level(GPIO_WP)) -- cgit v1.2.1 From f80da163f2a09ec49e26bcf03ad4f6a9d20b8f42 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:49 -0600 Subject: driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I510e7201e5155bc60bd369dc4f3454dd9268266a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729976 Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- driver/fingerprint/fpc/libfp/fpc_private.h | 166 ++++++++++++++++------------- 1 file changed, 93 insertions(+), 73 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_private.h b/driver/fingerprint/fpc/libfp/fpc_private.h index bd9ff711b6..adb0e7c0ea 100644 --- a/driver/fingerprint/fpc/libfp/fpc_private.h +++ b/driver/fingerprint/fpc/libfp/fpc_private.h @@ -10,83 +10,103 @@ /* External error codes from FPC's sensor library */ enum fpc_error_code_external { - FPC_ERROR_NONE = 0, - FPC_ERROR_NOT_FOUND = 1, - FPC_ERROR_CAN_BE_USED_2 = 2, - FPC_ERROR_CAN_BE_USED_3 = 3, - FPC_ERROR_CAN_BE_USED_4 = 4, - FPC_ERROR_PAL = 5, - FPC_ERROR_IO = 6, - FPC_ERROR_CANCELLED = 7, - FPC_ERROR_UNKNOWN = 8, - FPC_ERROR_MEMORY = 9, - FPC_ERROR_PARAMETER = 10, - FPC_ERROR_TEST_FAILED = 11, - FPC_ERROR_TIMEDOUT = 12, - FPC_ERROR_SENSOR = 13, - FPC_ERROR_SPI = 14, - FPC_ERROR_NOT_SUPPORTED = 15, - FPC_ERROR_OTP = 16, - FPC_ERROR_STATE = 17, - FPC_ERROR_PN = 18, - FPC_ERROR_DEAD_PIXELS = 19, - FPC_ERROR_TEMPLATE_CORRUPTED = 20, - FPC_ERROR_CRC = 21, - FPC_ERROR_STORAGE = 22, /**< Errors related to storage **/ - FPC_ERROR_MAXIMUM_REACHED = 23, /**< The allowed maximum has been reached **/ - FPC_ERROR_MINIMUM_NOT_REACHED = 24, /**< The required minimum was not reached **/ - FPC_ERROR_SENSOR_LOW_COVERAGE = 25, /**< Minimum sensor coverage was not reached **/ - FPC_ERROR_SENSOR_LOW_QUALITY = 26, /**< Sensor image is considered low quality **/ - FPC_ERROR_SENSOR_FINGER_NOT_STABLE = 27, /**< Finger was not stable during image capture **/ + FPC_ERROR_NONE = 0, + FPC_ERROR_NOT_FOUND = 1, + FPC_ERROR_CAN_BE_USED_2 = 2, + FPC_ERROR_CAN_BE_USED_3 = 3, + FPC_ERROR_CAN_BE_USED_4 = 4, + FPC_ERROR_PAL = 5, + FPC_ERROR_IO = 6, + FPC_ERROR_CANCELLED = 7, + FPC_ERROR_UNKNOWN = 8, + FPC_ERROR_MEMORY = 9, + FPC_ERROR_PARAMETER = 10, + FPC_ERROR_TEST_FAILED = 11, + FPC_ERROR_TIMEDOUT = 12, + FPC_ERROR_SENSOR = 13, + FPC_ERROR_SPI = 14, + FPC_ERROR_NOT_SUPPORTED = 15, + FPC_ERROR_OTP = 16, + FPC_ERROR_STATE = 17, + FPC_ERROR_PN = 18, + FPC_ERROR_DEAD_PIXELS = 19, + FPC_ERROR_TEMPLATE_CORRUPTED = 20, + FPC_ERROR_CRC = 21, + FPC_ERROR_STORAGE = 22, /**< Errors related to storage **/ + FPC_ERROR_MAXIMUM_REACHED = 23, /**< The allowed maximum has been + reached **/ + FPC_ERROR_MINIMUM_NOT_REACHED = 24, /**< The required minimum was not + reached **/ + FPC_ERROR_SENSOR_LOW_COVERAGE = 25, /**< Minimum sensor coverage was not + reached **/ + FPC_ERROR_SENSOR_LOW_QUALITY = 26, /**< Sensor image is considered low + quality **/ + FPC_ERROR_SENSOR_FINGER_NOT_STABLE = 27, /**< Finger was not stable + during image capture **/ }; /* Internal error codes from FPC's sensor library */ enum fpc_error_code_internal { - FPC_ERROR_INTERNAL_0 = 0, /* Indicates that no internal code was set. */ - FPC_ERROR_INTERNAL_1 = 1, /* Not supported by sensor. */ - FPC_ERROR_INTERNAL_2 = 2, /* Sensor got a NULL response (from other module). */ - FPC_ERROR_INTERNAL_3 = 3, /* Runtime config not supported by firmware. */ - FPC_ERROR_INTERNAL_4 = 4, /* CAC has not been created. */ - FPC_ERROR_INTERNAL_5 = 5, /* CAC returned an error to the sensor. */ - FPC_ERROR_INTERNAL_6 = 6, /* CAC fasttap image capture failed. */ - FPC_ERROR_INTERNAL_7 = 7, /* CAC fasttap image capture failed. */ - FPC_ERROR_INTERNAL_8 = 8, /* CAC Simple image capture failed. */ - FPC_ERROR_INTERNAL_9 = 9, /* CAC custom image capture failed. */ - FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed. */ - FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed. */ - FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size. */ - FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size. */ - FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid. */ - FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid. */ - FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid. */ - FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid. */ - FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid. */ - FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid. */ - FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be extracted. */ - FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component. */ - FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed. */ - FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed. */ - FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be extracted. */ - FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be extracted. */ - FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid. */ - FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read. */ - FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs rrs. */ - FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed. */ - FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp calibration. */ - FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image. */ - FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration. */ - FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid. */ - FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed. */ - FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete. */ - FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after calibration. */ - FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size. */ - FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when calibrating finger detect. */ - FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is larger than max. */ - FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows */ - FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a too high or low value */ - FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL configuration */ - FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw descriptor */ - FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test */ + FPC_ERROR_INTERNAL_0 = 0, /* Indicates that no internal code was set. */ + FPC_ERROR_INTERNAL_1 = 1, /* Not supported by sensor. */ + FPC_ERROR_INTERNAL_2 = 2, /* Sensor got a NULL response (from other + module). */ + FPC_ERROR_INTERNAL_3 = 3, /* Runtime config not supported by firmware. + */ + FPC_ERROR_INTERNAL_4 = 4, /* CAC has not been created. */ + FPC_ERROR_INTERNAL_5 = 5, /* CAC returned an error to the sensor. */ + FPC_ERROR_INTERNAL_6 = 6, /* CAC fasttap image capture failed. */ + FPC_ERROR_INTERNAL_7 = 7, /* CAC fasttap image capture failed. */ + FPC_ERROR_INTERNAL_8 = 8, /* CAC Simple image capture failed. */ + FPC_ERROR_INTERNAL_9 = 9, /* CAC custom image capture failed. */ + FPC_ERROR_INTERNAL_10 = 10, /* CAC MQT image capture failed. */ + FPC_ERROR_INTERNAL_11 = 11, /* CAC PN image capture failed. */ + FPC_ERROR_INTERNAL_12 = 12, /* Reading CAC context size. */ + FPC_ERROR_INTERNAL_13 = 13, /* Reading CAC context size. */ + FPC_ERROR_INTERNAL_14 = 14, /* Sensor context invalid. */ + FPC_ERROR_INTERNAL_15 = 15, /* Buffer reference is invalid. */ + FPC_ERROR_INTERNAL_16 = 16, /* Buffer size reference is invalid. */ + FPC_ERROR_INTERNAL_17 = 17, /* Image data reference is invalid. */ + FPC_ERROR_INTERNAL_18 = 18, /* Capture type specified is invalid. */ + FPC_ERROR_INTERNAL_19 = 19, /* Capture config specified is invalid. */ + FPC_ERROR_INTERNAL_20 = 20, /* Sensor type in hw desc could not be + extracted. */ + FPC_ERROR_INTERNAL_21 = 21, /* Failed to create BNC component. */ + FPC_ERROR_INTERNAL_22 = 22, /* BN calibration failed. */ + FPC_ERROR_INTERNAL_23 = 23, /* BN memory allocation failed. */ + FPC_ERROR_INTERNAL_24 = 24, /* Companion type in hw desc could not be + extracted. */ + FPC_ERROR_INTERNAL_25 = 25, /* Coating type in hw desc could not be + extracted. */ + FPC_ERROR_INTERNAL_26 = 26, /* Sensor mode type is invalid. */ + FPC_ERROR_INTERNAL_27 = 27, /* Wrong Sensor state in OTP read. */ + FPC_ERROR_INTERNAL_28 = 28, /* Mismatch of register size in overlay vs + rrs. */ + FPC_ERROR_INTERNAL_29 = 29, /* Checkerboard capture failed. */ + FPC_ERROR_INTERNAL_30 = 30, /* Error converting to fpc_image in dp + calibration. */ + FPC_ERROR_INTERNAL_31 = 31, /* Failed to capture reset pixel image. */ + FPC_ERROR_INTERNAL_32 = 32, /* API level not support in dp calibration. + */ + FPC_ERROR_INTERNAL_33 = 33, /* The image data in parameter is invalid. + */ + FPC_ERROR_INTERNAL_34 = 34, /* PAL delay function has failed. */ + FPC_ERROR_INTERNAL_35 = 35, /* AFD sensor commad did not complete. */ + FPC_ERROR_INTERNAL_36 = 36, /* AFD wrong runlevel detected after + calibration. */ + FPC_ERROR_INTERNAL_37 = 37, /* Wrong rrs size. */ + FPC_ERROR_INTERNAL_38 = 38, /* There was a finger on the sensor when + calibrating finger detect. */ + FPC_ERROR_INTERNAL_39 = 39, /* The calculated calibration value is + larger than max. */ + FPC_ERROR_INTERNAL_40 = 40, /* The sensor fifo always underflows */ + FPC_ERROR_INTERNAL_41 = 41, /* The oscillator calibration resulted in a + too high or low value */ + FPC_ERROR_INTERNAL_42 = 42, /* Sensor driver was opened with NULL + configuration */ + FPC_ERROR_INTERNAL_43 = 43, /* Sensor driver as opened with NULL hw + descriptor */ + FPC_ERROR_INTERNAL_44 = 44, /* Error occured during image drive test */ }; /* FPC specific initialization function to fill their context */ -- cgit v1.2.1 From 1622e5e7ba7b85e3f8eca30b35e5c0dfd6ed1d10 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 12:21:57 -0700 Subject: Make vbus command print vsys as well This patch makes vbus console command print vsys as well. > vbus VBUS VSYS P0 19008mV 16416mV P1 19008mV 16416mV P2 19008mV 16416mV BUG=None BRANCH=None TEST=On Agah. See above. Signed-off-by: Daisuke Nojiri Change-Id: I3c4e56b945773a552967bde845b996419e58040f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733419 Reviewed-by: Tim Wawrzynczak --- common/charge_manager.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index c5eb93f704..d74410ebe8 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -411,21 +411,30 @@ static int command_vbus(int argc, char **argv) { /* port = -1 to print all the ports */ int port = -1; + int vbus, vsys; if (argc == 2) port = atoi(argv[1]); - for (int i = 0; i < board_get_usb_pd_port_count(); i++) { - if (port < 0 || i == port) - ccprintf("VBUS C%d = %d mV\n", i, - charge_manager_get_vbus_voltage(i)); + ccprintf(" VBUS VSYS\n"); + for (int i = 0; i < CHARGE_PORT_COUNT; i++) { + if (port < 0 || i == port) { + vbus = charge_manager_get_vbus_voltage(i); + if (charger_get_vsys_voltage(i, &vsys)) + vsys = -1; + ccprintf(" P%d %6dmV ", i, vbus); + if (vsys >= 0) + ccprintf("%6dmV\n", vsys); + else + ccprintf("(unknown)\n"); + } } return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(vbus, command_vbus, "[port]", - "VBUS of the given port"); + "Print VBUS & VSYS of the given port"); #endif /** -- cgit v1.2.1 From c7b8e0212e9a062c554fb93e25f88206e2d5b952 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 20:16:15 +0000 Subject: volteer: Disable commands to create ROM space BUG=None BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri Change-Id: Ida7cdfcec94c7129f4d08a1693ac34dcd4aa4691 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733420 Reviewed-by: Tim Wawrzynczak --- board/volteer/board.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/volteer/board.h b/board/volteer/board.h index 02b07c1f1d..10fd23486f 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -163,8 +163,11 @@ #undef CONFIG_CMD_CBI #undef CONFIG_CMD_CHARGER #undef CONFIG_CMD_CHARGE_SUPPLIER_INFO +#undef CONFIG_CMD_CRASH +#undef CONFIG_CMD_DEVICE_EVENT #undef CONFIG_CMD_FLASH_WP #undef CONFIG_CMD_HASH +#undef CONFIG_CMD_I2C_XFER #undef CONFIG_CMD_IDLE_STATS #undef CONFIG_CMD_INA #undef CONFIG_CMD_MFALLOW -- cgit v1.2.1 From ef39a975c3037f763fe32d8e79c23dd341c3b5f6 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 20:16:15 +0000 Subject: adlrvpp_mchp1521: Disable commands to create ROM space BUG=None BRANCH=None TEST=buildall Signed-off-by: Daisuke Nojiri Change-Id: I1a3f92e541c8a11c57c9841712e083ea2c65ea06 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733421 Reviewed-by: Tim Wawrzynczak --- board/adlrvpp_mchp1521/board.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h index 3867cab1a1..7a4f3ba728 100644 --- a/board/adlrvpp_mchp1521/board.h +++ b/board/adlrvpp_mchp1521/board.h @@ -17,6 +17,10 @@ #include "adlrvp.h" +#undef CONFIG_CMD_ADC +#undef CONFIG_CMD_APTHROTTLE +#undef CONFIG_CMD_BATTFAKE + /* * Macros for GPIO signals used in common code that don't match the * schematic names. Signal names in gpio.inc match the schematic and are -- cgit v1.2.1 From e77450cc45f4b83823c14950768f7ae0d6841d08 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 12:25:50 -0700 Subject: isl9241: Add get_vsys_voltage This patch implements get_vsys_voltage for isl9241. BUG=None BRANCH=None TEST=On agah. Print vsys by vbus command with/without AC. Signed-off-by: Daisuke Nojiri Change-Id: I73afd0138291d99eb2e79565d8422c345b905125 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733422 Reviewed-by: Tim Wawrzynczak --- driver/charger/isl9241.c | 33 +++++++++++++++++++++++++++++++++ driver/charger/isl9241.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c index 586f0db8cf..362167fa10 100644 --- a/driver/charger/isl9241.c +++ b/driver/charger/isl9241.c @@ -316,6 +316,38 @@ error: return rv; } +static enum ec_error_list isl9241_get_vsys_voltage(int chgnum, int port, + int *voltage) +{ + int val = 0; + int rv; + + rv = isl9241_update(chgnum, ISL9241_REG_CONTROL3, + ISL9241_CONTROL3_ENABLE_ADC, MASK_SET); + if (rv) { + CPRINTS("Could not enable ADC for Vsys. (rv=%d)", rv); + return rv; + } + + usleep(ISL9241_ADC_POLLING_TIME_US); + + /* Read voltage ADC value */ + rv = isl9241_read(chgnum, ISL9241_REG_VSYS_ADC_RESULTS, &val); + if (rv) { + CPRINTS("Could not read Vsys. (rv=%d)", rv); + isl9241_update(chgnum, ISL9241_REG_CONTROL3, + ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR); + return rv; + } + + /* Adjust adc_val. Same as Vin. */ + val >>= ISL9241_VIN_ADC_BIT_OFFSET; + val *= ISL9241_VIN_ADC_STEP_MV; + *voltage = val; + + return EC_SUCCESS; +} + static enum ec_error_list isl9241_post_init(int chgnum) { return EC_SUCCESS; @@ -876,6 +908,7 @@ const struct charger_drv isl9241_drv = { .set_voltage = &isl9241_set_voltage, .discharge_on_ac = &isl9241_discharge_on_ac, .get_vbus_voltage = &isl9241_get_vbus_voltage, + .get_vsys_voltage = &isl9241_get_vsys_voltage, .set_input_current_limit = &isl9241_set_input_current_limit, .get_input_current_limit = &isl9241_get_input_current_limit, .manufacturer_id = &isl9241_manufacturer_id, diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h index 769ee9c921..5272d6d371 100644 --- a/driver/charger/isl9241.h +++ b/driver/charger/isl9241.h @@ -151,6 +151,8 @@ #define ISL9241_VIN_ADC_BIT_OFFSET 6 #define ISL9241_VIN_ADC_STEP_MV 96 +#define ISL9241_ADC_POLLING_TIME_US 400 + /* * Used to reset ACOKref register to normal value to detect low voltage (5V or * 9V) adapter during next plug in event -- cgit v1.2.1 From 02bd4146b1f807938a9f2f510ae7d54e66b3ef93 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 12:30:33 -0700 Subject: isl9241: Get bypass mode status This patch makes isl9241's get_status additionally get the bypass gate status. BUG=b:214057333 BRANCH=None TEST=On Agah. Signed-off-by: Daisuke Nojiri Change-Id: I704b64a0bc21108906ec4c9a6ba952a77070edb3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733423 Reviewed-by: Tim Wawrzynczak --- driver/charger/isl9241.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c index 362167fa10..1ac311a8b3 100644 --- a/driver/charger/isl9241.c +++ b/driver/charger/isl9241.c @@ -181,6 +181,19 @@ static const struct charger_info *isl9241_get_info(int chgnum) return &isl9241_charger_info; } +static enum ec_error_list isl9241_bypass_mode_enabled(int chgnum, int *enabled) +{ + int reg, rv; + + rv = isl9241_read(chgnum, ISL9241_REG_CONTROL0, ®); + if (rv) + return rv; + + *enabled = !!(reg & ISL9241_CONTROL0_EN_BYPASS_GATE); + + return EC_SUCCESS; +} + static enum ec_error_list isl9241_get_status(int chgnum, int *status) { int rv; @@ -205,6 +218,13 @@ static enum ec_error_list isl9241_get_status(int chgnum, int *status) if (reg & ISL9241_INFORMATION2_ACOK_PIN) *status |= CHARGER_AC_PRESENT; + /* Bypass mode status */ + rv = isl9241_bypass_mode_enabled(chgnum, ®); + if (rv) + return rv; + if (reg) + *status |= CHARGER_BYPASS_MODE; + return EC_SUCCESS; } -- cgit v1.2.1 From 8d9a5c873a739513fe72c4e3b6ad28ce4e39279a Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 28 Jun 2022 12:34:50 -0700 Subject: isl9241: Fix bypass mode This patch fixes isl9241's enable_bypass_mode. Test1: 0. Boot on battery. 1. Plug BJ. Bypass mode enabled. 2. Plug USB-C. No switching. 3. Unplug BJ. Switch to USB-C. Bypass mode disabled. 4. Unplug USB-C. Test2: 0. Boot on battery. 1. Plug USB-C. 2. Plug BJ. Switch to BJ. Bypass mode enabled. 3. Unplug USB-C. 4. Unplug BJ. BUG=b:214057333, b:236852816 BRANCH=None TEST=On Agah. See above. Signed-off-by: Daisuke Nojiri Change-Id: Ife4ea0454a4c231ce033ff4a8a1646081357efca Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733424 Reviewed-by: Tim Wawrzynczak --- driver/charger/isl9241.c | 178 ++++++++++++++++++++++++++++++++++------------- driver/charger/isl9241.h | 6 ++ 2 files changed, 136 insertions(+), 48 deletions(-) diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c index 1ac311a8b3..12d5a2d55a 100644 --- a/driver/charger/isl9241.c +++ b/driver/charger/isl9241.c @@ -42,7 +42,7 @@ #define AC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS1) / ISL9241_DEFAULT_RS1) /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, "ISL9241 " format, ## args) static int learn_mode; @@ -498,22 +498,29 @@ static enum ec_error_list isl9241_bypass_to_bat(int chgnum) { const struct battery_info *bi = battery_get_info(); + CPRINTS("bypass -> bat"); + /* 1: Disable force forward buck/reverse boost. */ isl9241_update(chgnum, ISL9241_REG_CONTROL4, ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR); + /* * 2: Turn off BYPSG, turn on NGATE, disable charge pump 100%, disable * Vinvoltage_max); + /* 4: Disable ADC. */ isl9241_update(chgnum, ISL9241_REG_CONTROL3, ISL9241_CONTROL3_ENABLE_ADC, MASK_CLR); + /* 5: Set BGATE to normal operation. */ isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, MASK_CLR); + /* 6: Set ACOK reference to normal value. TODO: Revisit. */ isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE, ISL9241_MV_TO_ACOK_REFERENCE( @@ -527,6 +534,8 @@ static enum ec_error_list isl9241_bypass_to_bat(int chgnum) */ static enum ec_error_list isl9241_bypass_chrg_to_bat(int chgnum) { + CPRINTS("bypass_chrg -> bat"); + /* 1: Disable force forward buck/reverse boost. */ isl9241_update(chgnum, ISL9241_REG_CONTROL4, ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR); @@ -559,6 +568,8 @@ static enum ec_error_list isl9241_nvdc_chrg_to_nvdc(int chgnum) { enum ec_error_list rv; + CPRINTS("nvdc_chrg -> nvdc"); + /* L: If we're in NVDC+Chg, first transition to NVDC. */ /* 1: Disable fast charge. */ rv = isl9241_set_current(chgnum, 0); @@ -580,52 +591,82 @@ static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable); */ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) { - int voltage; + const struct battery_info *bi = battery_get_info(); + const int charge_current = charge_manager_get_charger_current(); + const int charge_voltage = charge_manager_get_charger_voltage(); + int vsys, vsys_target; + timestamp_t deadline; + + CPRINTS("nvdc -> bypass"); /* 1: Set adapter current limit. */ - isl9241_set_input_current_limit(chgnum, - charge_manager_get_charger_current()); + isl9241_set_input_current_limit(chgnum, charge_current); + /* 2: Set charge pumps to 100%. */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_EN_CHARGE_PUMPS, MASK_SET); + /* 3: Enable ADC. */ isl9241_update(chgnum, ISL9241_REG_CONTROL3, ISL9241_CONTROL3_ENABLE_ADC, MASK_SET); + /* 4: Turn on Vin/Vout comparator. */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_EN_VIN_VOUT_COMP, MASK_SET); - /* 5: Set ACOK reference higher than battery full voltage. + + /* 5: Set ACOK reference higher than battery full voltage. */ isl9241_write(chgnum, ISL9241_REG_ACOK_REFERENCE, - ISL9241_MV_TO_ACOK_REFERENCE( - battery_full_voltage_mv + 800)); - */ + ISL9241_MV_TO_ACOK_REFERENCE(bi->voltage_max + 800)); + /* 6*: Reduce system load below ACLIM. */ /* 7: Turn off BGATE */ isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, MASK_SET); + /* 8*: Set MaxSysVoltage to VADP. */ - isl9241_get_vbus_voltage(chgnum, 0, &voltage); - isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage - 256); + vsys_target = MIN(charge_voltage - 256, CHARGE_V_MAX); + isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, vsys_target); + /* 9*: Wait until VSYS == MaxSysVoltage. */ + deadline.val = get_time().val + ISL9241_BYPASS_VSYS_TIMEOUT_MS * MSEC; + do { + msleep(ISL9241_BYPASS_VSYS_TIMEOUT_MS / 10); + if (isl9241_get_vsys_voltage(chgnum, 0, &vsys)) { + CPRINTS("Aborting bypass mode. Vsys is unknown."); + return EC_ERROR_UNKNOWN; + } + if (timestamp_expired(deadline, NULL)) { + CPRINTS("Aborting bypass mode. Vsys too low (%d < %d)", + vsys, vsys_target); + return EC_ERROR_TIMEOUT; + } + } while (vsys < vsys_target - 256); + /* 10*: Turn on Bypass gate */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_SET); + /* 11: Wait 1 ms. */ msleep(1); + /* 12*: Turn off NGATE. */ isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF, MASK_SET); + /* 14*: Stop switching. */ isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0); + /* 15: Set BGATE to normal operation. */ isl9241_update(chgnum, ISL9241_REG_CONTROL1, ISL9241_CONTROL1_BGATE_OFF, MASK_CLR); - /* - * Suggestion-1: If ACOK goes low before step A16, stop here - * then execute the steps for Bypass to BAT to abort. - */ + if (!isl9241_is_ac_present(chgnum)) - return isl9241_enable_bypass_mode(chgnum, false); + /* + * Suggestion: If ACOK goes low before step A16, stop + * executing commands and complete steps for Bypass to BAT. + */ + return EC_ERROR_PARAM1; + /* 16: Enable 10 mA discharge on CSOP. */ /* 17: Read diode emulation active bit. */ /* 18: Disable 10mA discharge on CSOP. */ @@ -633,12 +674,12 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) isl9241_update(chgnum, ISL9241_REG_CONTROL4, ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_SET); - /* - * Suggestion-2 and 3: If AC is removed on or after A16, - * complete all steps then execute Bypass to BAT to revert. - */ if (!isl9241_is_ac_present(chgnum)) - return isl9241_enable_bypass_mode(chgnum, false); + /* + * Suggestion: If AC is removed on or after A16, complete all + * 19 steps then execute Bypass to BAT. + */ + return EC_ERROR_PARAM2; return EC_SUCCESS; } @@ -648,12 +689,24 @@ static enum ec_error_list isl9241_nvdc_to_bypass(int chgnum) */ static enum ec_error_list isl9241_bypass_chrg_to_bypass(int chgnum) { + int rv; + + CPRINTS("bypass_chrg -> bypass"); + /* 1: Stop switching. */ - isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0); + rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, 0); + if (rv) + return rv; + /* 2: Disable fast charge. */ - isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0); + rv = isl9241_write(chgnum, ISL9241_REG_CHG_CURRENT_LIMIT, 0); + if (rv) + return rv; + /* 3: Disable trickle charge. */ - isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0); + rv = isl9241_write(chgnum, ISL9241_REG_MIN_SYSTEM_VOLTAGE, 0); + if (rv) + return rv; return EC_SUCCESS; } @@ -665,26 +718,44 @@ static enum ec_error_list isl9241_bypass_to_nvdc(int chgnum) { const struct battery_info *bi = battery_get_info(); int voltage; + int rv; + + CPRINTS("bypass -> nvdc"); /* 1*: Reduce system load below ACLIM. */ /* 3*: Disable force forward buck/reverse boost. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL4, - ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR); + rv = isl9241_update(chgnum, ISL9241_REG_CONTROL4, + ISL9241_CONTROL4_FORCE_BUCK_MODE, MASK_CLR); + if (rv) + return rv; + /* 6*: Set MaxSysVoltage to VADP. */ - isl9241_get_vbus_voltage(chgnum, 0, &voltage); - isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, voltage - 256); + rv = isl9241_get_vbus_voltage(chgnum, 0, &voltage); + if (rv) + return rv; + rv = isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, + voltage - 256); + if (rv) + return rv; + /* 7*: Wait until VSYS == MaxSysVoltage. */ msleep(1); + /* 8*: Turn on NGATE. */ - isl9241_update(chgnum, ISL9241_REG_CONTROL0, ISL9241_CONTROL0_NGATE_OFF, - MASK_CLR); + rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0, + ISL9241_CONTROL0_NGATE_OFF, MASK_CLR); + if (rv) + return rv; + /* 10*: Turn off Bypass gate */ - isl9241_update(chgnum, ISL9241_REG_CONTROL0, - ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR); - /* 12*: Set MaxSysVoltage to full charge. */ - isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, bi->voltage_max); + rv = isl9241_update(chgnum, ISL9241_REG_CONTROL0, + ISL9241_CONTROL0_EN_BYPASS_GATE, MASK_CLR); + if (rv) + return rv; - return EC_SUCCESS; + /* 12*: Set MaxSysVoltage to full charge. */ + return isl9241_write(chgnum, ISL9241_REG_MAX_SYSTEM_VOLTAGE, + bi->voltage_max); } static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable) @@ -696,37 +767,48 @@ static enum ec_error_list isl9241_enable_bypass_mode(int chgnum, bool enable) if (isl9241_is_in_chrg(chgnum)) { /* (Optional) L (then A) */ rv = isl9241_nvdc_chrg_to_nvdc(chgnum); - CPRINTS("%s nvdc_chrg -> nvdc", - rv ? "Failed" : "Succeeded"); + if (rv) + CPRINTS("nvdc_chrg -> nvdc failed(%d)", rv); } /* A */ rv = isl9241_nvdc_to_bypass(chgnum); - CPRINTS("%s nvdc -> bypass", rv ? "Failed" : "Succeeded"); + if (rv == EC_ERROR_PARAM1 || rv == EC_ERROR_PARAM2) { + CPRINTS("AC removed (%d) in nvdc -> bypass mode", rv); + return isl9241_bypass_to_bat(chgnum); + } else if (rv) { + CPRINTS("Failed to enable bypass mode(%d)", rv); + return isl9241_bypass_to_nvdc(chgnum); + } return rv; - } else if (isl9241_is_ac_present(chgnum)) { - /* Switch to NVDC (e.g. BJ -> Type-C) */ + } + + /* Disable */ + if (isl9241_is_ac_present(chgnum)) { + /* Switch to another AC (e.g. BJ -> Type-C) */ if (isl9241_is_in_chrg(chgnum)) { /* J (then B) */ rv = isl9241_bypass_chrg_to_bypass(chgnum); - CPRINTS("%s bypass_chrg -> bypass", - rv ? "Failed" : "Succeeded"); + if (rv) + CPRINTS("bypass_chrg -> bypass failed(%d)", rv); } /* B */ rv = isl9241_bypass_to_nvdc(chgnum); - CPRINTS("%s bypass -> nvdc", rv ? "Failed" : "Succeeded"); + if (rv) + CPRINTS("bypass -> nvdc failed(%d)", rv); return rv; } else { /* AC removal */ if (isl9241_is_in_chrg(chgnum)) { /* M */ rv = isl9241_bypass_chrg_to_bat(chgnum); - CPRINTS("%s bypass_chrg -> bat", - rv ? "Failed" : "Succeeded"); - return rv; + if (rv) + CPRINTS("bypass_chrg -> bat failed(%d)", rv); + } else { + /* M' */ + rv = isl9241_bypass_to_bat(chgnum); + if (rv) + CPRINTS("bypass -> bat failed(%d)", rv); } - /* M */ - rv = isl9241_bypass_to_bat(chgnum); - CPRINTS("%s bypass -> bat", rv ? "Failed" : "Succeeded"); return rv; } diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h index 5272d6d371..adddd1fc77 100644 --- a/driver/charger/isl9241.h +++ b/driver/charger/isl9241.h @@ -159,4 +159,10 @@ */ #define ISL9241_ACOK_REF_LOW_VOLTAGE_ADAPTER_MV 3600 +/* + * Max wait time for Vsys to be close to Vin (Vadp) before turning on the bypass + * gate. See 2.5.1 of application notes for details. + */ +#define ISL9241_BYPASS_VSYS_TIMEOUT_MS 500 + #endif /* __CROS_EC_ISL9241_H */ -- cgit v1.2.1 From 122ce784c72a2c623dd9615eda5d2ff6a0fe2c94 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Tue, 21 Jun 2022 21:52:03 +0000 Subject: GPU: Add Nvidia GPU D-Notify driver (Based on the driver written by Tim Wawrzynczak.) This patch adds Nvidia GPU D-Notify driver. It asserts a GPIO, sends a host event, and sets D-Notify level in shared memory when power availability changes (i.e. AC plug/unplug, battery charge/discharge). BUG=b:216485035 BRANCH=None TEST=make run-nvidia_gpu && make buildall Signed-off-by: Daisuke Nojiri Change-Id: I231619157fe03fb357882540ffa34b4d48fba253 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716794 Reviewed-by: Tim Wawrzynczak --- driver/build.mk | 5 +- driver/nvidia_gpu.c | 154 +++++++++++++++++++++++++++++++++ driver/nvidia_gpu.h | 59 +++++++++++++ include/charge_manager.h | 2 +- include/config.h | 12 ++- include/console_channel.inc | 3 + include/ec_commands.h | 6 +- include/extpower.h | 2 +- test/build.mk | 2 + test/nvidia_gpu.c | 204 ++++++++++++++++++++++++++++++++++++++++++++ test/nvidia_gpu.tasklist | 10 +++ test/test_config.h | 5 ++ zephyr/Kconfig.throttle_ap | 10 +++ 13 files changed, 468 insertions(+), 6 deletions(-) create mode 100644 driver/nvidia_gpu.c create mode 100644 driver/nvidia_gpu.h create mode 100644 test/nvidia_gpu.c create mode 100644 test/nvidia_gpu.tasklist diff --git a/driver/build.mk b/driver/build.mk index f8abe50742..81955294eb 100644 --- a/driver/build.mk +++ b/driver/build.mk @@ -118,6 +118,9 @@ driver-$(CONFIG_LED_DRIVER_TLC59116F)+=led/tlc59116f.o # 7-segment display driver-$(CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY)+=led/max695x.o +# Nvidia GPU D-Notify driver +driver-$(CONFIG_GPU_NVIDIA)+=nvidia_gpu.o + # Voltage regulators driver-$(CONFIG_REGULATOR_IR357X)+=regulator_ir357x.o @@ -241,4 +244,4 @@ driver-$(CONFIG_MP2964)+=mp2964.o # SOC Interface driver-$(CONFIG_AMD_SB_RMI)+=sb_rmi.o -driver-$(CONFIG_AMD_STT)+=amd_stt.o +driver-$(CONFIG_AMD_STT)+=amd_stt.o \ No newline at end of file diff --git a/driver/nvidia_gpu.c b/driver/nvidia_gpu.c new file mode 100644 index 0000000000..3737b4ecd0 --- /dev/null +++ b/driver/nvidia_gpu.c @@ -0,0 +1,154 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Nvidia GPU D-Notify driver + */ + +#include + +#include "charge_manager.h" +#include "charge_state.h" +#include "compile_time_macros.h" +#include "console.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "host_command.h" +#include "nvidia_gpu.h" +#include "throttle_ap.h" +#include "timer.h" + +#define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ## args) +#define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ## args) + +/* + * BIT0~2: D-Notify level (0:D1, ... 4:D5) + * note: may need a bit for disabling dynamic boost. + */ +#define MEMMAP_D_NOTIFY_MASK GENMASK(2, 0) + +test_export_static enum d_notify_level d_notify_level = D_NOTIFY_1; +test_export_static bool policy_initialized = false; +test_export_static const struct d_notify_policy *d_notify_policy = NULL; + +void nvidia_gpu_init_policy(const struct d_notify_policy *policy) +{ + if (policy) { + d_notify_policy = policy; + policy_initialized = true; + } +} + +static void set_d_notify_level(enum d_notify_level level) +{ + uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU); + + if (level == d_notify_level) + return; + + d_notify_level = level; + *memmap_gpu = (*memmap_gpu & ~MEMMAP_D_NOTIFY_MASK) | d_notify_level; + host_set_single_event(EC_HOST_EVENT_GPU); + CPRINTS("Set D-notify level to D%c", ('1' + (int)d_notify_level)); +} + +static void evaluate_d_notify_level(void) +{ + enum d_notify_level lvl; + const struct d_notify_policy *policy = d_notify_policy; + + /* + * We don't need to care about 'transitioning to S0' because throttling + * is unlikely required when the system is about to start. + */ + if (!chipset_in_state(CHIPSET_STATE_ON)) + return; + + if (!policy_initialized) { + CPRINTS("WARN: %s called before policies are set.", __func__); + return; + } + + if (extpower_is_present()) { + const int watts = charge_manager_get_power_limit_uw() / 1000000; + + for (lvl = D_NOTIFY_1; lvl <= D_NOTIFY_5; lvl++) { + if (policy[lvl].power_source != D_NOTIFY_AC && + policy[lvl].power_source != D_NOTIFY_AC_DC) + continue; + + if (policy[lvl].power_source == D_NOTIFY_AC) { + if (watts >= policy[lvl].ac.min_charger_watts) { + set_d_notify_level(lvl); + break; + } + } else { + set_d_notify_level(lvl); + break; + } + } + } else { + const int soc = charge_get_percent(); + + for (lvl = D_NOTIFY_5; lvl >= D_NOTIFY_1; lvl--) { + if (policy[lvl].power_source == D_NOTIFY_DC) { + if (soc <= policy[lvl].dc.min_battery_soc) { + set_d_notify_level(lvl); + break; + } + } else if (policy[lvl].power_source == D_NOTIFY_AC_DC) { + set_d_notify_level(lvl); + break; + } + } + } +} + +static void disable_gpu_acoff(void) +{ + gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 1); + evaluate_d_notify_level(); +} +DECLARE_DEFERRED(disable_gpu_acoff); + +static void handle_battery_soc_change(void) +{ + evaluate_d_notify_level(); +} +DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, handle_battery_soc_change, + HOOK_PRIO_DEFAULT); + +/* + * This function enables and disables both hard and soft throttles. (Thus, + * has no meaning.). + * + * When throttling, it hard-throttles the GPU and sets the D-level to D5. It + * also schedules a deferred call to disable the hard throttle. So, it's not + * necessary to call it for unthrottling. + * + * Currently, it's upto each board when this is called. For example, it can be + * called from board_set_active_charge_port since board_set_active_charge_port + * is called whenever (and prior to) active port or active supplier or both + * changes. + */ +void throttle_gpu(enum throttle_level level, + enum throttle_type type, /* not used */ + enum throttle_sources source) +{ + if (level == THROTTLE_ON) { + /* Cancel pending deferred call. */ + hook_call_deferred(&disable_gpu_acoff_data, -1); + /* Toggle hardware throttle immediately. */ + gpio_set_level(GPIO_NVIDIA_GPU_ACOFF_ODL, 0); + /* + * Switch to the lowest (D5) first then move up as the situation + * improves. + */ + set_d_notify_level(D_NOTIFY_5); + hook_call_deferred(&disable_gpu_acoff_data, + NVIDIA_GPU_ACOFF_DURATION); + } else { + disable_gpu_acoff(); + } +} diff --git a/driver/nvidia_gpu.h b/driver/nvidia_gpu.h new file mode 100644 index 0000000000..267f6643f5 --- /dev/null +++ b/driver/nvidia_gpu.h @@ -0,0 +1,59 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Nvidia GPU D-Notify driver header file + */ + +#ifndef DRIVER_NVIDIA_GPU_H +#define DRIVER_NVIDIA_GPU_H + +#define NVIDIA_GPU_ACOFF_DURATION (100 * MSEC) + +enum d_notify_level { + D_NOTIFY_1 = 0, + D_NOTIFY_2, + D_NOTIFY_3, + D_NOTIFY_4, + D_NOTIFY_5, + D_NOTIFY_COUNT, +}; + +enum d_notify_policy_type { + /* High- or low-power A/C */ + D_NOTIFY_AC, + /* Too low of A/C to still charge or DC with high battery SOC */ + D_NOTIFY_AC_DC, + /* DC with medium or low battery SOC */ + D_NOTIFY_DC, +}; + +struct d_notify_policy { + enum d_notify_policy_type power_source; + union { + struct { + unsigned int min_charger_watts; + } ac; + struct { + unsigned int min_battery_soc; + } dc; + }; +}; + +#define AC_ATLEAST_W(W) { \ + .power_source = D_NOTIFY_AC, \ + .ac.min_charger_watts = (W), \ + } + +#define AC_DC { \ + .power_source = D_NOTIFY_AC_DC, \ + } + +#define DC_ATLEAST_SOC(S) { \ + .power_source = D_NOTIFY_DC, \ + .dc.min_battery_soc = (S), \ + } + +void nvidia_gpu_init_policy(const struct d_notify_policy *policies); + +#endif /* DRIVER_NVIDIA_GPU_H */ diff --git a/include/charge_manager.h b/include/charge_manager.h index cca8c9ce25..0545be594c 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -235,7 +235,7 @@ int charge_manager_get_selected_charge_port(void); * * @return Power limit (uW). */ -int charge_manager_get_power_limit_uw(void); +test_mockable int charge_manager_get_power_limit_uw(void); /** * Get the charger current (mA) value. diff --git a/include/config.h b/include/config.h index 87c4582642..b116c5d347 100644 --- a/include/config.h +++ b/include/config.h @@ -2338,6 +2338,11 @@ /* Support getting gpio flags. */ #undef CONFIG_GPIO_GET_EXTENDED +/* + * GPU Drivers + */ +#undef CONFIG_GPU_NVIDIA + /* Do we want to detect the lid angle? */ #undef CONFIG_LID_ANGLE @@ -6862,4 +6867,9 @@ #define CONFIG_S5_EXIT_WAIT 4 #endif -#endif /* __CROS_EC_CONFIG_H */ +/* HAS_GPU_DRIVER enables D-Notify and throttling. */ +#if defined(CONFIG_GPU_NVIDIA) +#define HAS_GPU_DRIVER +#endif + +#endif /* __CROS_EC_CONFIG_H */ diff --git a/include/console_channel.inc b/include/console_channel.inc index 96691c21c3..705a8209df 100644 --- a/include/console_channel.inc +++ b/include/console_channel.inc @@ -110,3 +110,6 @@ CONSOLE_CHANNEL(CC_USBPD, "usbpd") #endif CONSOLE_CHANNEL(CC_VBOOT, "vboot") CONSOLE_CHANNEL(CC_HOOK, "hook") +#ifdef HAS_GPU_DRIVER +CONSOLE_CHANNEL(CC_GPU, "gpu") +#endif diff --git a/include/ec_commands.h b/include/ec_commands.h index 24f53e449b..bddf95ca32 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -169,7 +169,8 @@ extern "C" { /* 0x94 - 0x99: 1st Accelerometer */ /* 0x9a - 0x9f: 2nd Accelerometer */ #define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */ -/* Unused 0xa6 - 0xdf */ +#define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ +/* Unused 0xa7 - 0xdf */ /* * ACPI is unable to access memory mapped data at or above this offset due to @@ -671,7 +672,8 @@ enum host_event_code { /* Event generated by a device attached to the EC */ EC_HOST_EVENT_DEVICE = 10, EC_HOST_EVENT_THERMAL = 11, - EC_HOST_EVENT_USB_CHARGER = 12, + /* GPU related event. Formerly named EC_HOST_EVENT_USB_CHARGER. */ + EC_HOST_EVENT_GPU = 12, EC_HOST_EVENT_KEY_PRESSED = 13, /* * EC has finished initializing the host interface. The host can check diff --git a/include/extpower.h b/include/extpower.h index edc4bb105e..aa15d1f605 100644 --- a/include/extpower.h +++ b/include/extpower.h @@ -21,7 +21,7 @@ __override_proto void board_check_extpower(void); /** * Return non-zero if external power is present. */ -int extpower_is_present(void); +test_mockable int extpower_is_present(void); /** * Interrupt handler for external power GPIOs. diff --git a/test/build.mk b/test/build.mk index fac9544ca4..8c1b4b0d53 100644 --- a/test/build.mk +++ b/test/build.mk @@ -66,6 +66,7 @@ test-list-host += motion_lid test-list-host += motion_sense_fifo test-list-host += mutex test-list-host += newton_fit +test-list-host += nvidia_gpu test-list-host += online_calibration test-list-host += online_calibration_spoof test-list-host += pingpong @@ -191,6 +192,7 @@ motion_angle-y=motion_angle.o motion_angle_data_literals.o motion_common.o motion_angle_tablet-y=motion_angle_tablet.o motion_angle_data_literals_tablet.o motion_common.o motion_lid-y=motion_lid.o motion_sense_fifo-y=motion_sense_fifo.o +nvidia_gpu-y=nvidia_gpu.o online_calibration-y=online_calibration.o online_calibration_spoof-y=online_calibration_spoof.o gyro_cal_init_for_test.o rgb_keyboard-y=rgb_keyboard.o diff --git a/test/nvidia_gpu.c b/test/nvidia_gpu.c new file mode 100644 index 0000000000..c408fa429e --- /dev/null +++ b/test/nvidia_gpu.c @@ -0,0 +1,204 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Tests for Nvidia GPU. + */ +#include + +#include "charge_manager.h" +#include "charge_state.h" +#include "common.h" +#include "console.h" +#include "hooks.h" +#include "host_command.h" +#include "task.h" +#include "test_util.h" +#include "throttle_ap.h" +#include "timer.h" +#include "util.h" + +#include "driver/nvidia_gpu.h" + +struct d_notify_policy d_notify_policies[] = { + AC_ATLEAST_W(100), + AC_ATLEAST_W(65), + AC_DC, + DC_ATLEAST_SOC(20), + DC_ATLEAST_SOC(5), +}; + +extern enum d_notify_level d_notify_level; +extern bool policy_initialized; +extern const struct d_notify_policy *d_notify_policy; +static int extpower_presence = 1; +static int nvidia_gpu_acoff_odl = 1; +static int charge_percent = 100; +static int charge_power = 100; +static uint8_t *memmap_gpu; + +__override int charge_get_percent(void) +{ + return charge_percent; +} + +__override int charge_manager_get_power_limit_uw(void) +{ + return charge_power * 1000000; +} + +__override int extpower_is_present(void) +{ + return extpower_presence; +} + +__override int gpio_get_level(enum gpio_signal signal) +{ + if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL) + return nvidia_gpu_acoff_odl; + return 0; +} + +__override void gpio_set_level(enum gpio_signal signal, int value) +{ + if (signal == GPIO_NVIDIA_GPU_ACOFF_ODL) + nvidia_gpu_acoff_odl = value; +} + +static void setup(int extpower, int gpio_acoff, int percent, int power, + enum d_notify_level level) +{ + extpower_presence = extpower; + nvidia_gpu_acoff_odl = gpio_acoff; + charge_percent = percent; + charge_power = power; + d_notify_level = level; + *memmap_gpu = level; +} + +static void plug_ac(int plug) +{ + extpower_presence = plug; + hook_notify(HOOK_AC_CHANGE); +} + +static int check_d_notify_level(enum d_notify_level expected_level) +{ + TEST_EQ(d_notify_level, expected_level, "%d"); + TEST_EQ(*memmap_gpu, expected_level, "%d"); + + return EC_SUCCESS; +} + +static int test_startup(void) +{ + /* Test initial values after HOOK_INIT. Don't call setup(). */ + + TEST_ASSERT(IS_ENABLED(HAS_GPU_DRIVER)); + TEST_ASSERT(policy_initialized); + TEST_NE(d_notify_policy, NULL, "%p"); + TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d"); + + return EC_SUCCESS; +} + +static int test_ac_unplug(void) +{ + setup(1, 1, 100, 100, D_NOTIFY_1); + + /* Unplug AC. D1 -> D5 */ + plug_ac(0); + throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC); + TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + /* Wait half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D5. */ + usleep(NVIDIA_GPU_ACOFF_DURATION / 2); + TEST_EQ(nvidia_gpu_acoff_odl, 0, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d"); + TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU)); + + /* Wait another half of NVIDIA_GPU_ACOFF_DURATION. D5 -> D3. */ + usleep(NVIDIA_GPU_ACOFF_DURATION / 2); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + /* Discharge to 60%. D3 -> D3. */ + charge_percent = 60; + hook_notify(HOOK_BATTERY_SOC_CHANGE); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d"); + TEST_ASSERT(!host_is_event_set(EC_HOST_EVENT_GPU)); + + /* Discharge to 20%. D3 -> D4 */ + charge_percent = 20; + hook_notify(HOOK_BATTERY_SOC_CHANGE); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_4), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + /* Discharge to 5%. D4 -> D5 */ + charge_percent = 5; + hook_notify(HOOK_BATTERY_SOC_CHANGE); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_5), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + return EC_SUCCESS; +} + +static int test_ac_plug(void) +{ + /* Plug 100W AC. D5 -> D1. */ + setup(0, 1, 5, 100, D_NOTIFY_5); + plug_ac(1); + throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_1), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + /* Plug 65W AC. D5 -> D2. */ + setup(0, 1, 5, 65, D_NOTIFY_5); + plug_ac(1); + throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_2), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + /* Plug 35W AC. D5 -> D3. */ + setup(0, 1, 5, 35, D_NOTIFY_5); + plug_ac(1); + throttle_gpu(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC); + TEST_EQ(nvidia_gpu_acoff_odl, 1, "%d"); + TEST_EQ(check_d_notify_level(D_NOTIFY_3), EC_SUCCESS, "%d"); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + host_clear_events(EC_HOST_EVENT_MASK(EC_HOST_EVENT_GPU)); + + return EC_SUCCESS; +} + +static void board_gpu_init(void) +{ + nvidia_gpu_init_policy(d_notify_policies); +} +DECLARE_HOOK(HOOK_INIT, board_gpu_init, HOOK_PRIO_DEFAULT); + +void run_test(int argc, char **argv) +{ + memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU); + + test_chipset_on(); + + RUN_TEST(test_startup); + RUN_TEST(test_ac_unplug); + RUN_TEST(test_ac_plug); + test_print_result(); +} diff --git a/test/nvidia_gpu.tasklist b/test/nvidia_gpu.tasklist new file mode 100644 index 0000000000..b16ca2ffc0 --- /dev/null +++ b/test/nvidia_gpu.tasklist @@ -0,0 +1,10 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST \ + TASK_TEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) diff --git a/test/test_config.h b/test/test_config.h index 67615182b3..f4370cd80e 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -142,6 +142,11 @@ #define CONFIG_RGBKBD_DEMO_DOT #endif +#ifdef TEST_NVIDIA_GPU +#define CONFIG_GPU_NVIDIA +#define GPIO_NVIDIA_GPU_ACOFF_ODL 123 +#endif + #ifdef TEST_STILLNESS_DETECTOR #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO diff --git a/zephyr/Kconfig.throttle_ap b/zephyr/Kconfig.throttle_ap index ad5bfe9c77..74498a4e9f 100644 --- a/zephyr/Kconfig.throttle_ap +++ b/zephyr/Kconfig.throttle_ap @@ -58,4 +58,14 @@ config PLATFORM_EC_THROTTLE_AP_ON_BAT_LOW_VOLTAGE_THRESH default 0 endif +config PLATFORM_EC_GPU_NVIDIA + bool "Nvidia GPU supports throttling" + default n + help + Enable GPU throttling. When the GPU is throttled, a software (D-Notify) + and a hardware throttle (GPIO_NVIDIA_GPU_ACOFF_ODL) are enabled. A + hardware throttle will be automatically disabled after a fixed period + of time but a software throttle may remain and keep changing as the + situation changes. + endif # PLATFORM_EC_THROTTLE_AP -- cgit v1.2.1 From bd8cdbe80c41895a39591a3cb79d5a7f7f9d19fb Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Thu, 9 Jun 2022 10:01:41 -0600 Subject: Agah: Enable Nvidia GPU D-Notify driver This patch enables Nvidia GPU D-Notify driver for Agah. BUG=b:216485035, b:236674641 BRANCH=None TEST=On Agah, plug & unplug BJ & USB-C and verify expected modes (nvdc, nvdc_chrg, bypass, bypass_chrg, bat) are selected. TEST=On Agah, plug & unplug BJ & USB-C and verify expected D-levels are selected. Signed-off-by: Daisuke Nojiri Change-Id: I17b60e6054c91c60a7c1931e10a738607951055c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704268 Reviewed-by: Tim Wawrzynczak --- board/agah/board.c | 13 +++ board/agah/board.h | 5 + board/agah/charger_isl9241.c | 218 ++++++++++++++++++++++++------------------- board/agah/gpio.inc | 8 +- 4 files changed, 146 insertions(+), 98 deletions(-) diff --git a/board/agah/board.c b/board/agah/board.c index 979c9a38aa..47f2628fbb 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -26,6 +26,8 @@ #include "usbc_config.h" #include "util.h" +#include "driver/nvidia_gpu.h" + #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ @@ -34,6 +36,15 @@ static int block_sequence; +struct d_notify_policy d_notify_policies[] = { + AC_ATLEAST_W(100), + AC_ATLEAST_W(65), + AC_DC, + DC_ATLEAST_SOC(20), + DC_ATLEAST_SOC(5), +}; +BUILD_ASSERT(ARRAY_SIZE(d_notify_policies) == D_NOTIFY_COUNT); + __override void board_cbi_init(void) { } @@ -63,6 +74,8 @@ static void board_init(void) } gpio_enable_interrupt(GPIO_PG_PP3300_S5_OD); gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL); + + nvidia_gpu_init_policy(d_notify_policies); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/agah/board.h b/board/agah/board.h index d4ce9f23d1..d03aba2580 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -13,6 +13,11 @@ /* Baseboard features */ #include "baseboard.h" +/* + * Nvidia GPU + */ +#define CONFIG_GPU_NVIDIA + /* * This will happen automatically on NPCX9 ES2 and later. Do not remove * until we can confirm all earlier chips are out of service. diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c index 138c3841f7..1bc77c0ee4 100644 --- a/board/agah/charger_isl9241.c +++ b/board/agah/charger_isl9241.c @@ -3,6 +3,36 @@ * found in the LICENSE file. */ +/* + * + * We need to deal with plug / unplug of AC chargers: + * + * +---------+ +USB +---------+ + * | BATTERY |------------>| BATTERY | + * | |<------------| +USB | + * +---------+ -USB +---------+ + * | ^ | ^ + * +BJ | | -BJ +BJ | | -BJ + * v | v | + * +---------+ +USB +---------+ + * | BATTERY |------------>| BATTERY | + * | +BJ |<------------| +BJ+USB | + * +---------+ -USB +---------+ + * + * Depending on available battery charge, power rating of the new charger, and + * the system power state, transition/throttling may or may not occur but + * switching chargers is handled as follows: + * + * 1. Detects a new charger or removal of an existing charger. + * 2. charge_manager_update_charge is called with new charger's info. + * 3. board_set_active_charge_port is called. + * 3.1 It triggers hard & soft throttling for AP & GPU. + * 3.2 It disable active port then enables the new port. + * 4. HOOK_POWER_SUPPLY_CHANGE is called. We disables hard throttling. + * 5. charger task wakes up on HOOK_POWER_SUPPLY_CHANGE, enables (or disables) + * bypass mode. + */ + #include "common.h" #include "charge_manager.h" @@ -15,6 +45,7 @@ #include "gpio.h" #include "hooks.h" #include "stdbool.h" +#include "throttle_ap.h" #include "usbc_ppc.h" #include "usb_pd.h" #include "util.h" @@ -32,71 +63,42 @@ const struct charger_config_t chg_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); -static int board_disable_bj_port(void) +static int board_enable_bj_port(bool enable) { - gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1); - /* If the current port is BJ, disable bypass mode. */ - if (charge_manager_get_supplier() == CHARGE_SUPPLIER_DEDICATED) - return charger_enable_bypass_mode(0, 0); + if (enable) { + if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) + return EC_ERROR_INVAL; + gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0); + } else { + gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1); + } - CPRINTS("BJ power is disabled"); + CPRINTS("BJ power is %sabled", enable ? "en" : "dis"); return EC_SUCCESS; } -static int board_enable_bj_port(void) -{ - if (gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) - return EC_ERROR_INVAL; - gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 0); - - CPRINTS("BJ power is enabled"); - - return charger_enable_bypass_mode(0, 1); -} - -/* - * TODO: - * - * When AC is being plugged in (including switching source port), - * 1. Deassert NVIDIA_GPU_ACOFF_ODL. - * 2. Call evaluate_d_notify. - * - * When AC is being lost, - * 1. Assert NVIDIA_GPU_ACOFF_ODL. - * 2. Set D-Notify to D5. - * 3. Differ-call - * a. Deassert NVIDIA_GPU_ACOFF_ODL. - * b. evaluate_d_notify - */ -static int board_throttle_ap_gpu(bool enable) +static void board_throttle_ap_gpu(void) { - int rv = EC_SUCCESS; - - if (!chipset_in_state(CHIPSET_STATE_ON)) - return EC_SUCCESS; - - CPRINTS("TODO: %s to %s AP & GPU (%d)", rv ? "Failed" : "Succeeded", - enable ? "throttle" : "unthrottle", rv); - - return rv; + throttle_ap(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC); + throttle_gpu(THROTTLE_ON, THROTTLE_HARD, THROTTLE_SRC_AC); } /* Disable all VBUS sink ports except . = -1 disables all ports. */ -static int board_disable_vbus_sink(int port) +static int board_disable_other_vbus_sink(int except_port) { int i, r, rv = EC_SUCCESS; for (i = 0; i < ppc_cnt; i++) { - if (i == port) + if (i == except_port) continue; /* * Do not return early if one fails otherwise we can get into a * boot loop assertion failure. */ r = ppc_vbus_sink_enable(i, 0); - CPRINTS("%s to disable sink path C%d (%d).", - r ? "Failed" : "Succeeded", i, r); + if (r) + CPRINTS("Failed to disable sink path C%d (%d)", i, r); rv |= r; } @@ -107,74 +109,71 @@ static int board_disable_vbus_sink(int port) #define MIN_BATT_FOR_SWITCHING_SOURCE_PORT 1 /* - * It should also work on POR with/without a battery: - * - * 1. EC gathers power info of all ports. - * 2. Identify the highest power port. - * 3. If - * 1. battery soc = 0% --> Exit - * 2. BJ_ADP_PRESENT_ODL = 1 --> Exit - * 3. highest power port == active port --> Exit - * 4. If - * 1. in S0, throttle AP & GPU to the DC rating. - * 5. Turn off the current active port. - * 6. Turn on the highest power port. - * 7. If - * 1. in S0, throttle AP & GPU back. - * - * TODO: Are the following cases covered? - * 1. Two AC adapters are plugged. Then, the active adapter is removed. - * * TODO: Recover from incomplete execution: - * 1. Failed to turn on/off PPC. */ int board_set_active_charge_port(int port) { - enum charge_supplier supplier = charge_manager_get_supplier(); + enum charge_supplier active_supplier = charge_manager_get_supplier(); int active_port = charge_manager_get_active_charge_port(); - CPRINTS("Changing charge port to %d (current port=%d supplier=%d)", - port, active_port, supplier); + CPRINTS("Switching charger from P%d (supplier=%d) to P%d", + active_port, active_supplier, port); if (port == CHARGE_PORT_NONE) { CPRINTS("Disabling all charger ports"); - board_throttle_ap_gpu(1); - - board_disable_bj_port(); - board_disable_vbus_sink(-1); + board_enable_bj_port(false); + board_disable_other_vbus_sink(-1); return EC_SUCCESS; } + /* Return on invalid or no-op call. */ if (port < 0 || CHARGE_PORT_COUNT <= port) { return EC_ERROR_INVAL; } else if (port == active_port) { return EC_SUCCESS; } else if (board_vbus_source_enabled(port)) { /* Don't charge from a USBC source port */ - CPRINTS("Don't enable C%d. It's sourcing.", port); + CPRINTS("Don't enable P%d. It's sourcing.", port); return EC_ERROR_INVAL; } + /* + * If we're in S0, throttle AP and GPU. They'll be unthrottled when + * a port/supply switch completes (via HOOK_POWER_SUPPLY_CHANGE). + * + * If we're running currently on a battery (active_supplier == NONE), we + * don't need to throttle because we're not disabling any port. + */ + if (chipset_in_state(CHIPSET_STATE_ON) + && active_supplier != CHARGE_SUPPLIER_NONE) + board_throttle_ap_gpu(); + + /* + * We're here for the two cases: + * 1. A new charger was connected. + * 2. One charger was disconnected and we're switching to another. + */ + /* * We need to check the battery if we're switching a source port. If * we're just starting up or no AC was previously plugged, we shouldn't * check the battery. Both cases can be caught by supplier == NONE. */ - if (supplier != CHARGE_SUPPLIER_NONE) { + if (active_supplier != CHARGE_SUPPLIER_NONE) { if (charge_get_percent() < MIN_BATT_FOR_SWITCHING_SOURCE_PORT) return EC_ERROR_NOT_POWERED; } /* Turn off other ports' sink paths before enabling requested port. */ - if (port == CHARGE_PORT_TYPEC0 || port == CHARGE_PORT_TYPEC1) { + if (is_pd_port(port)) { /* - * BJ port is on POR. So, we need to turn it off even if we're - * not previously on BJ. + * BJ port is enabled on start-up. So, we need to turn it off + * even if we were not previously on BJ. */ - board_disable_bj_port(); - if (board_disable_vbus_sink(port)) + board_enable_bj_port(false); + if (board_disable_other_vbus_sink(port)) return EC_ERROR_UNCHANGED; /* Enable requested USBC charge port. */ @@ -187,16 +186,12 @@ int board_set_active_charge_port(int port) * We can't proceed unless both ports are successfully * disconnected as sources. */ - if (board_disable_vbus_sink(-1)) + if (board_disable_other_vbus_sink(-1)) return EC_ERROR_UNKNOWN; - board_enable_bj_port(); + board_enable_bj_port(true); } - /* Switching port is complete. Turn off throttling. */ - if (supplier != CHARGE_SUPPLIER_NONE) - board_throttle_ap_gpu(0); - - CPRINTS("New charger p%d", port); + CPRINTS("New charger P%d", port); return EC_SUCCESS; } @@ -215,31 +210,62 @@ static const struct charge_port_info bj_power = { }; /* Debounce time for BJ plug/unplug */ -#define BJ_DEBOUNCE_MS 1000 +#define BJ_DEBOUNCE_MS CONFIG_EXTPOWER_DEBOUNCE_MS + +int board_should_charger_bypass(void) +{ + return charge_manager_get_active_charge_port() == DEDICATED_CHARGE_PORT; +} -static void bj_connect_deferred(void) +static void bj_connect(void) { static int8_t bj_connected = -1; - const struct charge_port_info *pi = NULL; int connected = !gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL); + /* Debounce */ if (connected == bj_connected) return; - if (connected) - pi = &bj_power; + bj_connected = connected; + CPRINTS("BJ %sconnected", connected ? "" : "dis"); charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, - DEDICATED_CHARGE_PORT, pi); - bj_connected = connected; - CPRINTS("BJ %s", connected ? "connected" : "disconnected"); + DEDICATED_CHARGE_PORT, + connected ? &bj_power : NULL); } -DECLARE_DEFERRED(bj_connect_deferred); +DECLARE_DEFERRED(bj_connect); +/* This handler shouldn't be needed if ACOK from isl9241 is working. */ void bj_present_interrupt(enum gpio_signal signal) { - hook_call_deferred(&bj_connect_deferred_data, BJ_DEBOUNCE_MS * MSEC); + hook_call_deferred(&bj_connect_data, BJ_DEBOUNCE_MS * MSEC); +} + +void ac_change(void) +{ + /* + * Serialize. We don't handle USB-C here because we'll get a + * notification from TCPC. + */ + hook_call_deferred(&bj_connect_data, 0); +} +DECLARE_HOOK(HOOK_AC_CHANGE, ac_change, HOOK_PRIO_DEFAULT); + + +static void power_supply_changed(void) +{ + /* + * We've switched to a new charge port (or no port). Hardware throttles + * can be removed now. Software throttles may stay enabled and change + * as the situation changes. + */ + throttle_ap(THROTTLE_OFF, THROTTLE_HARD, THROTTLE_SRC_AC); + /* + * Unthrottling GPU is done through a deferred call scheduled when it + * was throttled. + */ } +DECLARE_HOOK(HOOK_POWER_SUPPLY_CHANGE, power_supply_changed, HOOK_PRIO_DEFAULT); static void bj_state_init(void) { @@ -252,6 +278,6 @@ static void bj_state_init(void) charge_manager_update_charge(j, i, NULL); } - bj_connect_deferred(); + bj_connect(); } DECLARE_HOOK(HOOK_INIT, bj_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index b708231cc4..7f38c87057 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -67,8 +67,13 @@ GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) GPIO(EN_USB_A_LOW_POWER, PIN(9, 3), GPIO_OUT_LOW) GPIO(PG_PP3300_S5_EC_SEQ_OD, PIN(B, 5), GPIO_OUT_LOW) GPIO(USB_C2_FRS_EN, PIN(D, 4), GPIO_OUT_LOW) +GPIO(NVIDIA_GPU_ACOFF_ODL, PIN(9, 5), GPIO_ODR_HIGH) -/* Barreljack */ +/* + * Barrel-jack adapter enable switch. When starting up on a depleted battery, + * we'll be powered by either BJ or USB-C but not both. The EC will detect BJ + * or USBC and disable the other ports. + */ GPIO(EN_PPVAR_BJ_ADP_L, PIN(A, 2), GPIO_OUT_LOW) /* @@ -122,7 +127,6 @@ UNUSED(PIN(0, 2)) /* GPIO02 */ UNUSED(PIN(6, 6)) /* GPIO66 */ UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ UNUSED(PIN(8, 1)) /* GPIO81 */ -UNUSED(PIN(9, 5)) /* GPIO95 */ UNUSED(PIN(7, 3)) /* GPIO73 */ UNUSED(PIN(5, 0)) /* GPIO50 */ UNUSED(PIN(6, 0)) /* GPIO60 */ -- cgit v1.2.1 From a11e8ae9dcdd295122e36105f5a4ab14abb2348d Mon Sep 17 00:00:00 2001 From: Peter Chi Date: Mon, 16 May 2022 09:32:25 +0800 Subject: crota: add custom fan control BUG=b:232656160 BRANCH=none TEST=make -j BOARD=crota Signed-off-by: Peter Chi Change-Id: I1dbafced042678af75f714121d421ff0f263dba7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3650086 Reviewed-by: Boris Mittelberg --- board/crota/board.h | 16 +++--- board/crota/fans.c | 83 ++++++++++++++++++++++++++----- board/crota/sensors.c | 133 +++++++++++--------------------------------------- 3 files changed, 110 insertions(+), 122 deletions(-) diff --git a/board/crota/board.h b/board/crota/board.h index 3b0bea06dc..e972cf3425 100644 --- a/board/crota/board.h +++ b/board/crota/board.h @@ -188,6 +188,10 @@ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +/* Fan features */ +#define CONFIG_CUSTOM_FAN_CONTROL +#define CONFIG_FAN_DYNAMIC + /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM @@ -204,18 +208,18 @@ #include "usbc_config.h" enum adc_channel { - ADC_TEMP_SENSOR_1_DDR_SOC, - ADC_TEMP_SENSOR_2_AMBIENT, + ADC_TEMP_SENSOR_1_SOC, + ADC_TEMP_SENSOR_2_DDR, ADC_TEMP_SENSOR_3_CHARGER, - ADC_TEMP_SENSOR_4_WWAN, + ADC_TEMP_SENSOR_4_AMBIENT, ADC_CH_COUNT }; enum temp_sensor_id { - TEMP_SENSOR_1_DDR_SOC, - TEMP_SENSOR_2_AMBIENT, + TEMP_SENSOR_1_SOC, + TEMP_SENSOR_2_DDR, TEMP_SENSOR_3_CHARGER, - TEMP_SENSOR_4_WWAN, + TEMP_SENSOR_4_AMBIENT, TEMP_SENSOR_COUNT }; diff --git a/board/crota/fans.c b/board/crota/fans.c index 443ccf13d3..e09519385f 100644 --- a/board/crota/fans.c +++ b/board/crota/fans.c @@ -12,6 +12,8 @@ #include "fan.h" #include "hooks.h" #include "pwm.h" +#include "thermal.h" +#include "util.h" /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { @@ -30,20 +32,19 @@ static const struct fan_conf fan_conf_0 = { .enable_gpio = GPIO_EN_PP5000_FAN, }; -/* - * TOOD(b/181271666): thermistor placement and calibration - * - * Prototype fan spins at about 4200 RPM at 100% PWM, this - * is specific to board ID 2 and might also apears in later - * boards as well. - */ static const struct fan_rpm fan_rpm_0 = { - .rpm_min = 2200, - .rpm_start = 2200, - .rpm_max = 4200, + .rpm_min = 3500, + .rpm_start = 3500, + .rpm_max = 4300, }; -const struct fan_t fans[FAN_CH_COUNT] = { +static const struct fan_rpm fan_rpm_1 = { + .rpm_min = 4300, + .rpm_start = 4300, + .rpm_max = 4700, +}; + +struct fan_t fans[FAN_CH_COUNT] = { [FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, @@ -87,3 +88,63 @@ DECLARE_HOOK(HOOK_CHIPSET_RESET, fan_max, HOOK_PRIO_FIRST); DECLARE_HOOK(HOOK_CHIPSET_RESUME, fan_max, HOOK_PRIO_DEFAULT); #endif /* CONFIG_FANS */ + +static void fan_set_percent(int fan, int pct, bool fan_triggered) +{ + int new_rpm; + + if (fan_triggered) + fans[fan].rpm = &fan_rpm_1; + else + fans[fan].rpm = &fan_rpm_0; + + new_rpm = fan_percent_to_rpm(fan, pct); + + fan_set_rpm_target(FAN_CH(fan), new_rpm); +} + +void board_override_fan_control(int fan, int *tmp) +{ + /* + * Crota's fan speed is control by three sensors. + * + * Sensor SOC control high loading's speed. + * Sensor ambient control low loading's speed. + * Sensor charger control the speed when system's temperature + * is too high. + * + * When sensor charger is not triggered, the fan is control + * and choose the smaller speed between SOC and ambient. + * + * When sensor charger is triggered, the fan speed is only + * control by sensor charger, avoid heat damage to system. + */ + + int pct; + int sensor_soc; + int sensor_ambient; + int sensor_charger; + bool fan_triggered; + + sensor_soc = thermal_fan_percent(thermal_params[0].temp_fan_off, + thermal_params[0].temp_fan_max, + C_TO_K(tmp[0])); + sensor_ambient = thermal_fan_percent(thermal_params[3].temp_fan_off, + thermal_params[3].temp_fan_max, + C_TO_K(tmp[3])); + sensor_charger = thermal_fan_percent(thermal_params[2].temp_fan_off, + thermal_params[2].temp_fan_max, + C_TO_K(tmp[2])); + + if (sensor_charger){ + fan_triggered = true; + pct = sensor_charger; + } + else{ + fan_triggered = false; + pct = MIN(sensor_soc, sensor_ambient); + } + + /* transfer percent to rpm */ + fan_set_percent(fan, pct, fan_triggered); +} diff --git a/board/crota/sensors.c b/board/crota/sensors.c index baa82f7b56..05eae65783 100644 --- a/board/crota/sensors.c +++ b/board/crota/sensors.c @@ -9,7 +9,6 @@ #include "adc.h" #include "driver/accel_lis2dw12.h" #include "driver/accelgyro_lsm6dso.h" -#include "driver/als_tcs3400_public.h" #include "gpio.h" #include "hooks.h" #include "motion_sense.h" @@ -19,15 +18,15 @@ /* ADC configuration */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1_DDR_SOC] = { - .name = "TEMP_DDR_SOC", + [ADC_TEMP_SENSOR_1_SOC] = { + .name = "TEMP_SOC", .input_ch = NPCX_ADC_CH0, .factor_mul = ADC_MAX_VOLT, .factor_div = ADC_READ_MAX + 1, .shift = 0, }, - [ADC_TEMP_SENSOR_2_AMBIENT] = { - .name = "TEMP_AMBIENT", + [ADC_TEMP_SENSOR_2_DDR] = { + .name = "TEMP_DDR", .input_ch = NPCX_ADC_CH1, .factor_mul = ADC_MAX_VOLT, .factor_div = ADC_READ_MAX + 1, @@ -40,8 +39,8 @@ const struct adc_t adc_channels[] = { .factor_div = ADC_READ_MAX + 1, .shift = 0, }, - [ADC_TEMP_SENSOR_4_WWAN] = { - .name = "TEMP_WWAN", + [ADC_TEMP_SENSOR_4_AMBIENT] = { + .name = "TEMP_AMBIENT", .input_ch = NPCX_ADC_CH7, .factor_mul = ADC_MAX_VOLT, .factor_div = ADC_READ_MAX + 1, @@ -156,17 +155,17 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", + [TEMP_SENSOR_1_SOC] = { + .name = "SOC", .type = TEMP_SENSOR_TYPE_BOARD, .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC, + .idx = ADC_TEMP_SENSOR_1_SOC, }, - [TEMP_SENSOR_2_AMBIENT] = { - .name = "Ambient", + [TEMP_SENSOR_2_DDR] = { + .name = "DDR", .type = TEMP_SENSOR_TYPE_BOARD, .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_AMBIENT, + .idx = ADC_TEMP_SENSOR_2_DDR, }, [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", @@ -174,124 +173,48 @@ const struct temp_sensor_t temp_sensors[] = { .read = get_temp_3v3_30k9_47k_4050b, .idx = ADC_TEMP_SENSOR_3_CHARGER, }, - [TEMP_SENSOR_4_WWAN] = { - .name = "WWAN", + [TEMP_SENSOR_4_AMBIENT] = { + .name = "Ambient", .type = TEMP_SENSOR_TYPE_BOARD, .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_WWAN, + .idx = ADC_TEMP_SENSOR_4_AMBIENT, }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -/* - * TODO(b/180681346): update for Alder Lake/brya - * - * Alder Lake specifies 100 C as maximum TDP temperature. THRMTRIP# occurs at - * 130 C. However, sensor is located next to DDR, so we need to use the lower - * DDR temperature limit (85 C) - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ #define THERMAL_CPU \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(77), \ + [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(77), \ }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_off = C_TO_K(39), \ + .temp_fan_max = C_TO_K(52), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -/* - * TODO(b/180681346): update for Alder Lake/brya - * - * Inductor limits - used for both charger and PP3300 regulator - * - * Need to use the lower of the charger IC, PP3300 regulator, and the inductors - * - * Charger max recommended temperature 100C, max absolute temperature 125C - * PP3300 regulator: operating range -40 C to 145 C - * - * Inductors: limit of 125c - * PCB: limit is 80c - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ -#define THERMAL_AMBIENT \ - { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ - }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ - } -__maybe_unused static const struct ec_thermal_config thermal_ambient = - THERMAL_AMBIENT; - -/* - * Inductor limits - used for both charger and PP3300 regulator - * - * Need to use the lower of the charger IC, PP3300 regulator, and the inductors - * - * Charger max recommended temperature 125C, max absolute temperature 150C - * PP3300 regulator: operating range -40 C to 125 C - * - * Inductors: limit of 125c - * PCB: limit is 80c - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ #define THERMAL_CHARGER \ { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(105), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(120), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ - }, \ - .temp_fan_off = C_TO_K(35), \ + .temp_fan_off = C_TO_K(59), \ .temp_fan_max = C_TO_K(65), \ } __maybe_unused static const struct ec_thermal_config thermal_charger = THERMAL_CHARGER; -/* - * TODO(b/180681346): update for brya WWAN module - */ -/* - * TODO(b/202062363): Remove when clang is fixed. - */ -#define THERMAL_WWAN \ +#define THERMAL_AMBIENT \ { \ - .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ - }, \ - .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ - }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(60), \ + .temp_fan_off = C_TO_K(26), \ + .temp_fan_max = C_TO_K(31), \ } -__maybe_unused static const struct ec_thermal_config thermal_wwan = - THERMAL_WWAN; +__maybe_unused static const struct ec_thermal_config thermal_ambient = + THERMAL_AMBIENT; struct ec_thermal_config thermal_params[] = { - [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, - [TEMP_SENSOR_2_AMBIENT] = THERMAL_AMBIENT, + [TEMP_SENSOR_1_SOC] = THERMAL_CPU, [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, - [TEMP_SENSOR_4_WWAN] = THERMAL_WWAN, + [TEMP_SENSOR_4_AMBIENT] = THERMAL_AMBIENT, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From e00695c0d4d6864147dd6f21f45fa410a24462fd Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Tue, 21 Jun 2022 19:36:39 -0600 Subject: zephyr: tests: Add test for USB-PD Rev 3 Get_Battery_Capabilities Add a new test suite to verify the functionality of USB-PD rev 3 support and the Get_Battery_Capabilities request and its response handler. The new tests validate that a response from the TCPC is received and contains correct battery data BUG=b:223452169 BRANCH=None TEST=zmake test test-drivers Signed-off-by: Tristan Honscheid Change-Id: I85403fdfa220a4edb2ee2f1673a2dcaaffca1620 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715699 Reviewed-by: Abe Levkoy --- zephyr/test/drivers/CMakeLists.txt | 1 + .../drivers/src/integration/usbc/usb_pd_rev3.c | 162 +++++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index 14608a659e..4cfecb9224 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -56,6 +56,7 @@ if(subproject_path STREQUAL "") src/integration/usbc/usb_alt_mode.c src/integration/usbc/usb_attach_src_snk.c src/integration/usbc/usb_pd_ctrl_msg.c + src/integration/usbc/usb_pd_rev3.c src/integration/usbc/usb_malfunction_sink.c src/i2c_passthru.c src/isl923x.c diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c new file mode 100644 index 0000000000..f4022a026d --- /dev/null +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c @@ -0,0 +1,162 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "battery.h" +#include "battery_smart.h" +#include "emul/emul_isl923x.h" +#include "emul/emul_smart_battery.h" +#include "emul/tcpc/emul_tcpci_partner_src.h" +#include "hooks.h" +#include "test/drivers/stubs.h" +#include "test/drivers/test_state.h" +#include "test/drivers/utils.h" +#include "usb_pd.h" +#include "usb_prl_sm.h" +#include "util.h" + +#define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) + +#define TEST_USB_PORT USBC_PORT_C0 + +struct usb_attach_5v_3a_pd_source_rev3_fixture { + struct tcpci_partner_data source_5v_3a; + struct tcpci_src_emul_data src_ext; + const struct emul *tcpci_emul; + const struct emul *charger_emul; +}; + +static void *usb_attach_5v_3a_pd_source_setup(void) +{ + static struct usb_attach_5v_3a_pd_source_rev3_fixture test_fixture; + + /* Get references for the emulators */ + test_fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + test_fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + /* Configure TCPCI revision in board config and emulator */ + tcpc_config[TEST_USB_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); + + /* Initialized the charger to supply 5V and 3A */ + tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV30); + test_fixture.source_5v_3a.extensions = tcpci_src_emul_init( + &test_fixture.src_ext, &test_fixture.source_5v_3a, NULL); + test_fixture.src_ext.pdo[1] = + PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + + return &test_fixture; +} + +static void usb_attach_5v_3a_pd_source_before(void *data) +{ + struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data; + + connect_source_to_port(&fixture->source_5v_3a, &fixture->src_ext, 1, + fixture->tcpci_emul, fixture->charger_emul); +} + +static void usb_attach_5v_3a_pd_source_after(void *data) +{ + struct usb_attach_5v_3a_pd_source_rev3_fixture *fixture = data; + + disconnect_source_from_port(fixture->tcpci_emul, fixture->charger_emul); +} + +ZTEST_SUITE(usb_attach_5v_3a_pd_source_rev3, drivers_predicate_post_main, + usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before, + usb_attach_5v_3a_pd_source_after, NULL); + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap) +{ + int battery_index = 0; + + tcpci_partner_common_send_get_battery_capabilities( + &fixture->source_5v_3a, battery_index); + + /* Allow some time for TCPC to process and respond */ + k_sleep(K_SECONDS(1)); + + zassert_true(fixture->source_5v_3a.battery_capabilities + .have_response[battery_index], + "No battery capabilities response stored."); + + /* The response */ + struct pd_bcdb *bcdb = + &fixture->source_5v_3a.battery_capabilities.bcdb[battery_index]; + + zassert_equal(USB_VID_GOOGLE, bcdb->vid, "Incorrect battery VID"); + zassert_equal(CONFIG_USB_PID, bcdb->pid, "Incorrect battery PID"); + zassert_false((bcdb->battery_type) & BIT(0), + "Invalid battery ref bit should not be set"); + + /* Verify the battery capacity and last full charge capacity. These + * fields require that the battery is present and that we can + * access information about the nominal voltage and capacity. + * + * TODO(b/237427945): Add test for case when battery is not present + */ + + /* See pe_give_battery_cap_entry() in common/usbc/usb_pe_drp_sm.c */ + + zassume_true(battery_is_present(), "Battery must be present"); + zassume_true(IS_ENABLED(HAS_TASK_HOSTCMD) && + *host_get_memmap(EC_MEMMAP_BATTERY_VERSION) != 0, + "Cannot access battery data"); + + /* Millivolts */ + int design_volt = *(int *)host_get_memmap(EC_MEMMAP_BATT_DVLT); + + /* Milliamphours */ + int design_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_DCAP); + int full_cap = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC); + + /* Multiply millivolts by milliamphours and scale to deciwatthours + * (0.1 Wh), the unit of energy used in the PD messages. + */ + + int expected_design_cap = + DIV_ROUND_NEAREST((design_cap * design_volt), 1000 * 1000 / 10); + + int expected_last_charge_cap = + DIV_ROUND_NEAREST((design_cap * full_cap), 1000 * 1000 / 10); + + zassert_equal(expected_design_cap, bcdb->design_cap, + "Design capacity not correct. Expected %d but got %d", + expected_design_cap, bcdb->design_cap); + zassert_equal( + expected_last_charge_cap, bcdb->last_full_charge_cap, + "Last full charge capacity not correct. Expected %d but got %d", + expected_last_charge_cap, bcdb->last_full_charge_cap); +} + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap_invalid) +{ + /* Request data on a battery that does not exist. The PD stack only + * supports battery 0. + */ + + int battery_index = 5; + + tcpci_partner_common_send_get_battery_capabilities( + &fixture->source_5v_3a, battery_index); + + /* Allow some time for TCPC to process and respond */ + k_sleep(K_SECONDS(1)); + + /* Ensure we get a response that says our battery index was invalid */ + + zassert_true(fixture->source_5v_3a.battery_capabilities + .have_response[battery_index], + "No battery capabilities response stored."); + zassert_true( + (fixture->source_5v_3a.battery_capabilities.bcdb[battery_index] + .battery_type) & + BIT(0), + "Invalid battery ref bit should be set"); +} -- cgit v1.2.1 From c0df853cfea2b395bb101025fbf799144c2d74b3 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Tue, 28 Jun 2022 20:28:04 -0700 Subject: Zephyr: intelrvp: make BOARD_RESET_AFTER_POWER_ON common flag CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON is common flag for RVP. And it needs to be set for both shim power sequencing and native power sequencing. Without this flag, after reboot plug in Type-C device for first time, the device is not getting detected. BUG=none BRANCH=none TEST=Boot up MTL RVP, plug in Type-C pen drive, detected. Signed-off-by: Li Feng Change-Id: I376b171c76753908755d9fd1a7d4425f7b1200b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3734449 Reviewed-by: Andrew McRae Reviewed-by: Vijay P Hiremath --- zephyr/projects/intelrvp/legacy_ec_pwrseq.conf | 1 - zephyr/projects/intelrvp/prj.conf | 3 +++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf index cdcfbc2b13..3fa6d2aadb 100644 --- a/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf +++ b/zephyr/projects/intelrvp/legacy_ec_pwrseq.conf @@ -9,5 +9,4 @@ CONFIG_PLATFORM_EC_POWERSEQ_INTEL=y CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY=y CONFIG_PLATFORM_EC_POWERSEQ_S0IX=y CONFIG_PLATFORM_EC_POWERSEQ_S4=y -CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y CONFIG_PLATFORM_EC_THROTTLE_AP=y diff --git a/zephyr/projects/intelrvp/prj.conf b/zephyr/projects/intelrvp/prj.conf index 51b9245200..3bff9d50e9 100644 --- a/zephyr/projects/intelrvp/prj.conf +++ b/zephyr/projects/intelrvp/prj.conf @@ -22,6 +22,9 @@ CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT=15000 CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=15001 +#Power Sequencing +CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y + # Host command CONFIG_PLATFORM_EC_HOSTCMD_AP_RESET=y -- cgit v1.2.1 From 5b7c2cff927423721922b6a986a3b61f24806886 Mon Sep 17 00:00:00 2001 From: Jacky_Wang Date: Mon, 30 May 2022 14:19:06 +0800 Subject: Delbin-G: Support second keyboard matrix Support second keyboard. BUG=b:232737379 BRANCH=firmware-volteer-13672.B TEST=make BOARD=delbin Signed-off-by: Jacky_Wang Change-Id: I4ed722d56969cbfd2cb6009cf5bd17dec9176973 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3676893 Commit-Queue: Kenny Pan Reviewed-by: Kenny Pan --- baseboard/volteer/cbi_ssfc.c | 5 + baseboard/volteer/cbi_ssfc.h | 19 +++- board/delbin/board.c | 46 ++++++++- board/delbin/board.h | 3 + board/delbin/build.mk | 1 + board/delbin/keyboard_customization.c | 169 ++++++++++++++++++++++++++++++++++ board/delbin/keyboard_customization.h | 130 ++++++++++++++++++++++++++ common/keyboard_scan.c | 57 ++++++++++-- include/config.h | 5 + include/keyboard_scan.h | 34 ++++++- util/config_allowed.txt | 1 + 11 files changed, 461 insertions(+), 9 deletions(-) create mode 100644 board/delbin/keyboard_customization.c create mode 100644 board/delbin/keyboard_customization.h diff --git a/baseboard/volteer/cbi_ssfc.c b/baseboard/volteer/cbi_ssfc.c index 42b11c4a1c..3238cfc933 100644 --- a/baseboard/volteer/cbi_ssfc.c +++ b/baseboard/volteer/cbi_ssfc.c @@ -39,3 +39,8 @@ enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void) { return cached_ssfc.lightbar; } + +enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void) +{ + return cached_ssfc.keyboard; +} diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h index e3431129bc..a9f39e17b0 100644 --- a/baseboard/volteer/cbi_ssfc.h +++ b/baseboard/volteer/cbi_ssfc.h @@ -40,12 +40,22 @@ enum ec_ssfc_lightbar { SSFC_LIGHTBAR_12_LED = 2 }; +/* + * Keyboard Type (Bit 11) + */ +enum ec_ssfc_keyboard { + SSFC_KEYBOARD_DEFAULT = 0, + SSFC_KEYBOARD_GAMING = 1 +}; + union volteer_cbi_ssfc { struct { enum ec_ssfc_base_sensor base_sensor : 3; enum ec_ssfc_lid_sensor lid_sensor : 3; enum ec_ssfc_lightbar lightbar : 2; - uint32_t reserved_2 : 24; + uint32_t reserved_2 : 4; + enum ec_ssfc_keyboard keyboard : 1; + uint32_t reserved_3 : 19; }; uint32_t raw_value; }; @@ -71,4 +81,11 @@ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); */ enum ec_ssfc_lightbar get_cbi_ssfc_lightbar(void); +/** + * Get keyboard type from SSFC_CONFIG. + * + * @return the keyboard type. + */ +enum ec_ssfc_keyboard get_cbi_ssfc_keyboard(void); + #endif /* _Volteer_CBI_SSFC__H_ */ diff --git a/board/delbin/board.c b/board/delbin/board.c index 068d453e8d..0e84dd2da6 100644 --- a/board/delbin/board.c +++ b/board/delbin/board.c @@ -8,6 +8,7 @@ #include "common.h" #include "accelgyro.h" #include "cbi_ec_fw_config.h" +#include "cbi_ssfc.h" #include "driver/accel_bma2x2.h" #include "driver/accelgyro_bmi260.h" #include "driver/bc12/pi3usb9201.h" @@ -22,6 +23,7 @@ #include "gpio.h" #include "hooks.h" #include "keyboard_scan.h" +#include "keyboard_customization.h" #include "lid_switch.h" #include "power.h" #include "power_button.h" @@ -60,6 +62,28 @@ __override struct keyboard_scan_config keyscan_config = { }, }; +__override struct key { + uint8_t row; + uint8_t col; +} vivaldi_keys[] = { + {.row = 0, .col = 2}, /* T1 */ + {.row = 3, .col = 2}, /* T2 */ + {.row = 2, .col = 2}, /* T3 */ + {.row = 1, .col = 2}, /* T4 */ + {.row = 3, .col = 4}, /* T5 */ + {.row = 2, .col = 4}, /* T6 */ + {.row = 1, .col = 4}, /* T7 */ + {.row = 2, .col = 9}, /* T8 */ + {.row = 1, .col = 9}, /* T9 */ + {.row = 0, .col = 4}, /* T10 */ + {.row = 0, .col = 1}, /* T11 */ + {.row = 1, .col = 5}, /* T12 */ + {.row = 3, .col = 5}, /* T13 */ + {.row = 0, .col = 9}, /* T14 */ + {.row = 0, .col = 11}, /* T15 */ +}; +BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); + /******************************************************************************/ /* * FW_CONFIG defaults for Delbin if the CBI data is not initialized. @@ -70,8 +94,28 @@ union volteer_cbi_fw_config fw_config_defaults = { static void board_init(void) { + key_choose(); + + if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING) { + keyscan_config.actual_key_mask[1] = 0xfa; + keyscan_config.actual_key_mask[4] = 0xfe; + keyscan_config.actual_key_mask[7] = 0x86; + keyscan_config.actual_key_mask[9] = 0xff; + keyscan_config.actual_key_mask[11] = 0xff; + + vivaldi_keys[0].row = 4; + vivaldi_keys[0].col = 2; + vivaldi_keys[4].row = 4; + vivaldi_keys[4].col = 4; + vivaldi_keys[5].row = 3; + vivaldi_keys[5].col = 4; + vivaldi_keys[6].row = 2; + vivaldi_keys[6].col = 4; + vivaldi_keys[9].row = 1; + vivaldi_keys[9].col = 4; + } } -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_PRE_DEFAULT); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ diff --git a/board/delbin/board.h b/board/delbin/board.h index c889d65b47..46b7a9b648 100644 --- a/board/delbin/board.h +++ b/board/delbin/board.h @@ -39,6 +39,9 @@ /* Keyboard features */ #define CONFIG_KEYBOARD_VIVALDI #define CONFIG_KEYBOARD_REFRESH_ROW3 +#define CONFIG_KEYBOARD_CUSTOMIZATION +#define CONFIG_KEYBOARD_MULTIPLE + /* Sensors */ /* BMA253 accelerometer in base */ diff --git a/board/delbin/build.mk b/board/delbin/build.mk index 66ad809f59..003b3d871d 100644 --- a/board/delbin/build.mk +++ b/board/delbin/build.mk @@ -16,3 +16,4 @@ board-y=board.o board-y+=battery.o board-y+=led.o board-y+=sensors.o +board-$(CONFIG_KEYBOARD_CUSTOMIZATION)+=keyboard_customization.o diff --git a/board/delbin/keyboard_customization.c b/board/delbin/keyboard_customization.c new file mode 100644 index 0000000000..0ccda5ce70 --- /dev/null +++ b/board/delbin/keyboard_customization.c @@ -0,0 +1,169 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "cbi_ssfc.h" +#include "gpio.h" +#include "keyboard_customization.h" +#include "keyboard_8042_sharedlib.h" +#include "keyboard_config.h" +#include "keyboard_protocol.h" +#include "keyboard_raw.h" +#include "keyboard_scan.h" + +static uint16_t (*scancode_set2)[KEYBOARD_ROWS]; + +static uint16_t KB2scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000}, + {0x0000, 0x0076, 0x0000, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016}, + {0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a}, + {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d}, + {0xe01f, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d}, + {0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043}, + {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c}, + {0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059}, + {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d}, + {0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a}, + {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, + {0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066}, + {0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d}, + {0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021}, + {0x0023, 0x005a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007D, 0x0069}, +}; + +/* The standard Chrome OS keyboard matrix table in scan code set 2. */ +static uint16_t KB1scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { + {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000}, + {0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015}, + {0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024}, + {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d}, + {0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d}, + {0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043}, + {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c}, + {0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059}, + {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d}, + {0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044}, + {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, +#ifndef CONFIG_KEYBOARD_KEYPAD + {0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, + {0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b}, +#else + {0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, + {0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b}, + {0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070}, + {0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a}, +#endif +}; + +uint16_t get_scancode_set2(uint8_t row, uint8_t col) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { + return *(*(scancode_set2 + col)+row); + } + return 0; +} + +void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val) +{ + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { + *(*(scancode_set2 + col)+row) = val; + } +} + +void board_keyboard_drive_col(int col) +{ + /* Drive all lines to high */ + if (col == KEYBOARD_COLUMN_NONE) + gpio_set_level(GPIO_KBD_KSO2, 0); + + /* Set KBSOUT to zero to detect key-press */ + else if (col == KEYBOARD_COLUMN_ALL) + gpio_set_level(GPIO_KBD_KSO2, 1); + + /* Drive one line for detection */ + else { + if (col == 2) + gpio_set_level(GPIO_KBD_KSO2, 1); + else + gpio_set_level(GPIO_KBD_KSO2, 0); + } +} + +struct keyboard_type key_typ = { + .col_esc = KEYBOARD_COL_ESC, + .row_esc = KEYBOARD_ROW_ESC, + .col_down = KEYBOARD_COL_DOWN, + .row_down = KEYBOARD_ROW_DOWN, + .col_left_shift = KEYBOARD_COL_LEFT_SHIFT, + .row_left_shift = KEYBOARD_ROW_LEFT_SHIFT, + .col_refresh = KEYBOARD_COL_REFRESH, + .row_refresh = KEYBOARD_ROW_REFRESH, + .col_right_alt = KEYBOARD_COL_RIGHT_ALT, + .row_right_alt = KEYBOARD_ROW_RIGHT_ALT, + .col_left_alt = KEYBOARD_COL_LEFT_ALT, + .row_left_alt = KEYBOARD_ROW_LEFT_ALT, + .col_key_r = KEYBOARD_COL_KEY_R, + .row_key_r = KEYBOARD_ROW_KEY_R, + .col_key_h = KEYBOARD_COL_KEY_H, + .row_key_h = KEYBOARD_ROW_KEY_H, +}; + +int keyboard_choose(void) +{ + if (get_cbi_ssfc_keyboard() == SSFC_KEYBOARD_GAMING) + return 1; + + return 0; +} + +void key_choose(void) +{ + if (keyboard_choose() == 1) { + key_typ.col_esc = KEYBOARD2_COL_ESC; + key_typ.row_esc = KEYBOARD2_ROW_ESC; + key_typ.col_down = KEYBOARD2_COL_DOWN; + key_typ.row_down = KEYBOARD2_ROW_DOWN; + key_typ.col_left_shift = KEYBOARD2_COL_LEFT_SHIFT; + key_typ.row_left_shift = KEYBOARD2_ROW_LEFT_SHIFT; + key_typ.col_refresh = KEYBOARD2_COL_REFRESH; + key_typ.row_refresh = KEYBOARD2_ROW_REFRESH; + key_typ.col_right_alt = KEYBOARD2_COL_RIGHT_ALT; + key_typ.row_right_alt = KEYBOARD2_ROW_RIGHT_ALT; + key_typ.col_left_alt = KEYBOARD2_COL_LEFT_ALT; + key_typ.row_left_alt = KEYBOARD2_ROW_LEFT_ALT; + key_typ.col_key_r = KEYBOARD2_COL_KEY_R; + key_typ.row_key_r = KEYBOARD2_ROW_KEY_R; + key_typ.col_key_h = KEYBOARD2_COL_KEY_H; + key_typ.row_key_h = KEYBOARD2_ROW_KEY_H; + + boot_key_list[0].col = KEYBOARD2_COL_ESC; + boot_key_list[0].row = KEYBOARD2_ROW_ESC; + boot_key_list[1].col = KEYBOARD2_COL_DOWN; + boot_key_list[1].row = KEYBOARD2_ROW_DOWN; + boot_key_list[2].col = KEYBOARD2_COL_LEFT_SHIFT; + boot_key_list[2].row = KEYBOARD2_ROW_LEFT_SHIFT; + + scancode_set2 = KB2scancode_set2; + } else { + key_typ.col_esc = KEYBOARD_COL_ESC; + key_typ.row_esc = KEYBOARD_ROW_ESC; + key_typ.col_down = KEYBOARD_COL_DOWN; + key_typ.row_down = KEYBOARD_ROW_DOWN; + key_typ.col_left_shift = KEYBOARD_COL_LEFT_SHIFT; + key_typ.row_left_shift = KEYBOARD_ROW_LEFT_SHIFT; + key_typ.col_refresh = KEYBOARD_COL_REFRESH; + key_typ.row_refresh = KEYBOARD_ROW_REFRESH; + key_typ.col_right_alt = KEYBOARD_COL_RIGHT_ALT; + key_typ.row_right_alt = KEYBOARD_ROW_RIGHT_ALT; + key_typ.col_left_alt = KEYBOARD_COL_LEFT_ALT; + key_typ.row_left_alt = KEYBOARD_ROW_LEFT_ALT; + key_typ.col_key_r = KEYBOARD_COL_KEY_R; + key_typ.row_key_r = KEYBOARD_ROW_KEY_R; + key_typ.col_key_h = KEYBOARD_COL_KEY_H; + key_typ.row_key_h = KEYBOARD_ROW_KEY_H; + + scancode_set2 = KB1scancode_set2; + } +} diff --git a/board/delbin/keyboard_customization.h b/board/delbin/keyboard_customization.h new file mode 100644 index 0000000000..3c26193f9f --- /dev/null +++ b/board/delbin/keyboard_customization.h @@ -0,0 +1,130 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Keyboard configuration */ + +#ifndef __KEYBOARD_CUSTOMIZATION_H +#define __KEYBOARD_CUSTOMIZATION_H + +/* + * KEYBOARD_COLS_MAX has the build time column size. It's used to allocate + * exact spaces for arrays. Actual keyboard scanning is done using + * keyboard_cols, which holds a runtime column size. + */ +#define KEYBOARD_COLS_MAX 16 +#define KEYBOARD_ROWS 8 + +/* + * WARNING: Do not directly modify it. You should call keyboard_raw_set_cols, + * instead. It checks whether you're eligible or not. + */ +extern uint8_t keyboard_cols; + +#define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) + +#define KEYBOARD_COL_DOWN 11 +#define KEYBOARD_ROW_DOWN 6 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 1 +#define KEYBOARD_ROW_ESC 1 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 6 +#define KEYBOARD_ROW_KEY_H 1 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 3 +#define KEYBOARD_ROW_KEY_R 7 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 10 +#define KEYBOARD_ROW_LEFT_ALT 6 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 2 +#ifdef CONFIG_KEYBOARD_REFRESH_ROW3 +#define KEYBOARD_ROW_REFRESH 3 +#else +#define KEYBOARD_ROW_REFRESH 2 +#endif +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 10 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 0 +#define KEYBOARD_COL_LEFT_CTRL 0 +#define KEYBOARD_ROW_LEFT_CTRL 2 +#define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) +#define KEYBOARD_COL_RIGHT_CTRL 0 +#define KEYBOARD_ROW_RIGHT_CTRL 4 +#define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) +#define KEYBOARD_COL_SEARCH 1 +#define KEYBOARD_ROW_SEARCH 0 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 8 +#define KEYBOARD_ROW_KEY_0 6 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 1 +#define KEYBOARD_ROW_KEY_1 6 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 4 +#define KEYBOARD_ROW_KEY_2 6 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_LEFT_SHIFT 7 +#define KEYBOARD_ROW_LEFT_SHIFT 5 +#define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) +#ifdef CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(2) +#elif defined(CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3) +#define KEYBOARD_MASK_PWRBTN KEYBOARD_ROW_TO_MASK(3) +#endif + +/* Columns and masks for keys we particularly care about */ +#define KEYBOARD2_COL_DOWN 11 +#define KEYBOARD2_ROW_DOWN 5 +#define KEYBOARD2_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_DOWN) +#define KEYBOARD2_COL_ESC 1 +#define KEYBOARD2_ROW_ESC 1 +#define KEYBOARD2_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_ESC) +#define KEYBOARD2_COL_KEY_H 6 +#define KEYBOARD2_ROW_KEY_H 1 +#define KEYBOARD2_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_H) +#define KEYBOARD2_COL_KEY_R 3 +#define KEYBOARD2_ROW_KEY_R 7 +#define KEYBOARD2_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_R) +#define KEYBOARD2_COL_LEFT_ALT 10 +#define KEYBOARD2_ROW_LEFT_ALT 6 +#define KEYBOARD2_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_ALT) +#define KEYBOARD2_COL_REFRESH 2 +#define KEYBOARD2_ROW_REFRESH 3 +#define KEYBOARD2_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_REFRESH) +#define KEYBOARD2_COL_RIGHT_ALT 10 +#define KEYBOARD2_ROW_RIGHT_ALT 0 +#define KEYBOARD2_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_ALT) +#define KEYBOARD2_DEFAULT_COL_VOL_UP 4 +#define KEYBOARD2_DEFAULT_ROW_VOL_UP 1 +#define KEYBOARD2_COL_LEFT_CTRL 0 +#define KEYBOARD2_ROW_LEFT_CTRL 2 +#define KEYBOARD2_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_CTRL) +#define KEYBOARD2_COL_RIGHT_CTRL 0 +#define KEYBOARD2_ROW_RIGHT_CTRL 4 +#define KEYBOARD2_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_RIGHT_CTRL) +#define KEYBOARD2_COL_SEARCH 4 +#define KEYBOARD2_ROW_SEARCH 0 +#define KEYBOARD2_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_SEARCH) +#define KEYBOARD2_COL_KEY_0 9 +#define KEYBOARD2_ROW_KEY_0 0 +#define KEYBOARD2_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_0) +#define KEYBOARD2_COL_KEY_1 1 +#define KEYBOARD2_ROW_KEY_1 7 +#define KEYBOARD2_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_1) +#define KEYBOARD2_COL_KEY_2 4 +#define KEYBOARD2_ROW_KEY_2 6 +#define KEYBOARD2_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_KEY_2) +#define KEYBOARD2_COL_LEFT_SHIFT 7 +#define KEYBOARD2_ROW_LEFT_SHIFT 1 +#define KEYBOARD2_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_SHIFT) + +int keyboard_choose(void); +void key_choose(void); + +#endif /* __KEYBOARD_CUSTOMIZATION_H */ diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c index 26ffde96dc..0edeca5867 100644 --- a/common/keyboard_scan.c +++ b/common/keyboard_scan.c @@ -27,6 +27,10 @@ #include "usb_api.h" #include "util.h" +#ifdef CONFIG_KEYBOARD_MULTIPLE +#include "keyboard_customization.h" +#endif + /* Console output macros */ #define CPUTS(outstr) cputs(CC_KEYSCAN, outstr) #define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args) @@ -78,18 +82,20 @@ __overridable struct keyboard_scan_config keyscan_config = { }, }; -/* Boot key list. Must be in same order as enum boot_key. */ -struct boot_key_entry { - uint8_t col; - uint8_t row; -}; - #ifdef CONFIG_KEYBOARD_BOOT_KEYS +#ifndef CONFIG_KEYBOARD_MULTIPLE static const struct boot_key_entry boot_key_list[] = { {KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC}, /* Esc */ {KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN}, /* Down-arrow */ {KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT}, /* Left-Shift */ }; +#else +struct boot_key_entry boot_key_list[] = { + {KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC}, /* Esc */ + {KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN}, /* Down-arrow */ + {KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT}, /* Left-Shift */ +}; +#endif static uint32_t boot_key_value = BOOT_KEY_NONE; #endif @@ -226,10 +232,17 @@ static int keyboard_read_adc_rows(void) */ static void keyboard_read_refresh_key(uint8_t *state) { + #ifndef CONFIG_KEYBOARD_MULTIPLE if (!gpio_get_level(GPIO_RFR_KEY_L)) state[KEYBOARD_COL_REFRESH] |= BIT(KEYBOARD_ROW_REFRESH); else state[KEYBOARD_COL_REFRESH] &= ~BIT(KEYBOARD_ROW_REFRESH); + #else + if (!gpio_get_level(GPIO_RFR_KEY_L)) + state[key_typ.col_refresh] |= BIT(key_typ.row_refresh); + else + state[key_typ.col_refresh] &= ~BIT(key_typ.row_refresh); + #endif } #endif @@ -437,9 +450,15 @@ static int check_runtime_keys(const uint8_t *state) if (state[key_vol_up_col] != KEYBOARD_ROW_TO_MASK(key_vol_up_row)) return 0; + #ifndef CONFIG_KEYBOARD_MULTIPLE if (state[KEYBOARD_COL_RIGHT_ALT] != KEYBOARD_MASK_RIGHT_ALT && state[KEYBOARD_COL_LEFT_ALT] != KEYBOARD_MASK_LEFT_ALT) return 0; + #else + if (state[key_typ.col_right_alt] != KEYBOARD_MASK_RIGHT_ALT && + state[key_typ.col_left_alt] != KEYBOARD_MASK_LEFT_ALT) + return 0; + #endif /* * Count number of columns with keys pressed. We know two columns are @@ -454,6 +473,7 @@ static int check_runtime_keys(const uint8_t *state) if (num_press != 3) return 0; + #ifndef CONFIG_KEYBOARD_MULTIPLE /* Check individual keys */ if (state[KEYBOARD_COL_KEY_R] == KEYBOARD_MASK_KEY_R) { /* R = reboot */ @@ -467,6 +487,21 @@ static int check_runtime_keys(const uint8_t *state) system_enter_hibernate(0, 0); return 1; } + #else + /* Check individual keys */ + if (state[key_typ.col_key_r] == KEYBOARD_MASK_KEY_R) { + /* R = reboot */ + CPRINTS("KB warm reboot"); + keyboard_clear_buffer(); + chipset_reset(CHIPSET_RESET_KB_WARM_REBOOT); + return 1; + } else if (state[key_typ.col_key_h] == KEYBOARD_MASK_KEY_H) { + /* H = hibernate */ + CPRINTS("KB hibernate"); + system_enter_hibernate(0, 0); + return 1; + } + #endif return 0; } @@ -680,7 +715,11 @@ static uint32_t check_key_list(const uint8_t *state) curr_state[c] &= ~KEYBOARD_MASK_PWRBTN; #endif + #ifndef CONFIG_KEYBOARD_MULTIPLE curr_state[KEYBOARD_COL_REFRESH] &= ~keyboard_mask_refresh; + #else + curr_state[key_typ.col_refresh] &= ~keyboard_mask_refresh; + #endif /* Update mask with all boot keys that were pressed. */ k = boot_key_list; @@ -746,9 +785,15 @@ static uint32_t check_boot_key(const uint8_t *state) return BOOT_KEY_NONE; /* If reset was not caused by reset pin, refresh must be held down */ + #ifndef CONFIG_KEYBOARD_MULTIPLE if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) && !(state[KEYBOARD_COL_REFRESH] & keyboard_mask_refresh)) return BOOT_KEY_NONE; + #else + if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) && + !(state[key_typ.col_refresh] & keyboard_mask_refresh)) + return BOOT_KEY_NONE; + #endif return check_key_list(state); } diff --git a/include/config.h b/include/config.h index b116c5d347..1a4460032a 100644 --- a/include/config.h +++ b/include/config.h @@ -3010,6 +3010,11 @@ */ #undef CONFIG_KEYBOARD_CUSTOMIZATION +/* + * Allow support multiple keyboard matrix for speical key. + */ +#undef CONFIG_KEYBOARD_MULTIPLE + /* * Allow board-specific 8042 keyboard callback when a key state is changed. */ diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h index 77c7ef9c27..9b0bec1191 100644 --- a/include/keyboard_scan.h +++ b/include/keyboard_scan.h @@ -38,6 +38,13 @@ struct keyboard_scan_config { #endif }; +/* Boot key list. Must be in same order as enum boot_key. */ +struct boot_key_entry { + uint8_t col; + uint8_t row; +}; + + /** * Initializes the module. */ @@ -152,4 +159,29 @@ extern const int keyboard_factory_scan_pins[][2]; extern const int keyboard_factory_scan_pins_used; #endif -#endif /* __CROS_EC_KEYBOARD_SCAN_H */ +#ifdef CONFIG_KEYBOARD_MULTIPLE +extern struct boot_key_entry boot_key_list[3]; + +struct keyboard_type { + int col_esc; + int row_esc; + int col_down; + int row_down; + int col_left_shift; + int row_left_shift; + int col_refresh; + int row_refresh; + int col_right_alt; + int row_right_alt; + int col_left_alt; + int row_left_alt; + int col_key_r; + int row_key_r; + int col_key_h; + int row_key_h; +}; + +extern struct keyboard_type key_typ; +#endif + +#endif /* __CROS_EC_KEYBOARD_SCAN_H */ diff --git a/util/config_allowed.txt b/util/config_allowed.txt index d6f2f2f807..37936cab97 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -581,6 +581,7 @@ CONFIG_KEYBOARD_IRQ_GPIO CONFIG_KEYBOARD_KSO_BASE CONFIG_KEYBOARD_KSO_HIGH_DRIVE CONFIG_KEYBOARD_LANGUAGE_ID +CONFIG_KEYBOARD_MULTIPLE CONFIG_KEYBOARD_POST_SCAN_CLOCKS CONFIG_KEYBOARD_PRINT_SCAN_TIMES CONFIG_KEYBOARD_RUNTIME_KEYS -- cgit v1.2.1 From 74f94ec700dae4932622a1964d427c4617f175b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Tue, 28 Jun 2022 14:50:25 -0600 Subject: zephyr: Make a minimal example project directory Similar to posix-ec, make a minimal project example for npcx9 and it8xxx2 as well. This deprecates the posix-ec project as well, replacing it with minimal-posix (with a very similar set of features enabled). BUG=b:237431976 BRANCH=none TEST=zmake build -a Signed-off-by: Jack Rosenthal Change-Id: Ifa1698502f05d55ed2bd39c1651da6cc613382b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3732803 Reviewed-by: Andrew McRae --- zephyr/projects/minimal/BUILD.py | 22 ++++++++++++++++++++ zephyr/projects/minimal/CMakeLists.txt | 9 ++++++++ zephyr/projects/minimal/README.md | 32 +++++++++++++++++++++++++++++ zephyr/projects/minimal/include/gpio_map.h | 14 +++++++++++++ zephyr/projects/minimal/it8xxx2.dts | 18 ++++++++++++++++ zephyr/projects/minimal/npcx9.dts | 24 ++++++++++++++++++++++ zephyr/projects/minimal/prj.conf | 18 ++++++++++++++++ zephyr/projects/posix-ec/BUILD.py | 7 ------- zephyr/projects/posix-ec/CMakeLists.txt | 10 --------- zephyr/projects/posix-ec/include/gpio_map.h | 4 ---- zephyr/projects/posix-ec/prj.conf | 11 ---------- 11 files changed, 137 insertions(+), 32 deletions(-) create mode 100644 zephyr/projects/minimal/BUILD.py create mode 100644 zephyr/projects/minimal/CMakeLists.txt create mode 100644 zephyr/projects/minimal/README.md create mode 100644 zephyr/projects/minimal/include/gpio_map.h create mode 100644 zephyr/projects/minimal/it8xxx2.dts create mode 100644 zephyr/projects/minimal/npcx9.dts create mode 100644 zephyr/projects/minimal/prj.conf delete mode 100644 zephyr/projects/posix-ec/BUILD.py delete mode 100644 zephyr/projects/posix-ec/CMakeLists.txt delete mode 100644 zephyr/projects/posix-ec/include/gpio_map.h delete mode 100644 zephyr/projects/posix-ec/prj.conf diff --git a/zephyr/projects/minimal/BUILD.py b/zephyr/projects/minimal/BUILD.py new file mode 100644 index 0000000000..bd79e32adb --- /dev/null +++ b/zephyr/projects/minimal/BUILD.py @@ -0,0 +1,22 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Minimal example project.""" + +register_host_project( + project_name="minimal-posix", + zephyr_board="native_posix", +) + +register_npcx_project( + project_name="minimal-npcx9", + zephyr_board="npcx9m3f", + dts_overlays=[here / "npcx9.dts"], +) + +register_binman_project( + project_name="minimal-it8xxx2", + zephyr_board="it8xxx2", + dts_overlays=[here / "it8xxx2.dts"], +) diff --git a/zephyr/projects/minimal/CMakeLists.txt b/zephyr/projects/minimal/CMakeLists.txt new file mode 100644 index 0000000000..8a0349bb24 --- /dev/null +++ b/zephyr/projects/minimal/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.20.5) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(ec) + +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") diff --git a/zephyr/projects/minimal/README.md b/zephyr/projects/minimal/README.md new file mode 100644 index 0000000000..72c092dfce --- /dev/null +++ b/zephyr/projects/minimal/README.md @@ -0,0 +1,32 @@ +# Minimal Example Zephyr EC Project + +This directory is intended to be an extremely minimal example of a +project. Should you like, you can use it as a bring up a new program, +or as reference as you require. + +If you're bringing up a new variant of a program, you don't need a +whole project directory with a `BUILD.py` and all, and this example is +likely not of use to you. Check out the [project config +documentation] for instructions on adding a new variant. + +[project config documentation]: ../../../docs/zephyr/project_config.md + +# Building + +To build the `native_posix` example, run: + +``` shellsession +(chroot) $ zmake build minimal-posix +``` + +To build the NPCX9 example, run: + +``` shellsession +(chroot) $ zmake build minimal-npcx9 +``` + +For the IT8XXX2 example, run: + +``` shellsession +(chroot) $ zmake build minimal-it8xxx2 +``` diff --git a/zephyr/projects/minimal/include/gpio_map.h b/zephyr/projects/minimal/include/gpio_map.h new file mode 100644 index 0000000000..e3009f49d5 --- /dev/null +++ b/zephyr/projects/minimal/include/gpio_map.h @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +/* GPIO_ENTERING_RW implemented by GPIO emulator on native_posix */ +#ifndef CONFIG_BOARD_NATIVE_POSIX +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#endif + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/minimal/it8xxx2.dts b/zephyr/projects/minimal/it8xxx2.dts new file mode 100644 index 0000000000..f199cfa87e --- /dev/null +++ b/zephyr/projects/minimal/it8xxx2.dts @@ -0,0 +1,18 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &ec_wp_l; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + }; +}; diff --git a/zephyr/projects/minimal/npcx9.dts b/zephyr/projects/minimal/npcx9.dts new file mode 100644 index 0000000000..b0184d769e --- /dev/null +++ b/zephyr/projects/minimal/npcx9.dts @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &ec_wp_l; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + }; +}; + +&cros_kb_raw { + status = "okay"; + pinctrl-0 = <>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/minimal/prj.conf b/zephyr/projects/minimal/prj.conf new file mode 100644 index 0000000000..0b810096b4 --- /dev/null +++ b/zephyr/projects/minimal/prj.conf @@ -0,0 +1,18 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_PLATFORM_EC=y +CONFIG_CROS_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_SYSCON=y + +# Disable default features we don't want in a minimal example. +CONFIG_ADC=n +CONFIG_I2C=n +CONFIG_PWM=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_POWER_BUTTON=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n diff --git a/zephyr/projects/posix-ec/BUILD.py b/zephyr/projects/posix-ec/BUILD.py deleted file mode 100644 index a324f2ad39..0000000000 --- a/zephyr/projects/posix-ec/BUILD.py +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -"""Define zmake projects for posix-ec.""" - -register_host_project(project_name="posix-ec") diff --git a/zephyr/projects/posix-ec/CMakeLists.txt b/zephyr/projects/posix-ec/CMakeLists.txt deleted file mode 100644 index 165de682a8..0000000000 --- a/zephyr/projects/posix-ec/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2020 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.13.1) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(posix-ec) - -zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") diff --git a/zephyr/projects/posix-ec/include/gpio_map.h b/zephyr/projects/posix-ec/include/gpio_map.h deleted file mode 100644 index 93e5f644ba..0000000000 --- a/zephyr/projects/posix-ec/include/gpio_map.h +++ /dev/null @@ -1,4 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ diff --git a/zephyr/projects/posix-ec/prj.conf b/zephyr/projects/posix-ec/prj.conf deleted file mode 100644 index f6549c7839..0000000000 --- a/zephyr/projects/posix-ec/prj.conf +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -CONFIG_CROS_EC=y -CONFIG_PLATFORM_EC=y - -# Disable shimmed code. Can enabled selectively later -CONFIG_SHIMMED_TASKS=n -CONFIG_PLATFORM_EC_KEYBOARD=n -CONFIG_PLATFORM_EC_HOSTCMD=n -- cgit v1.2.1 From 01e8075a2c6b3642fe47c665eaaae82c816129a1 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Thu, 5 May 2022 16:19:20 -0700 Subject: zephyr: mtlrvp: enable zephyr inbuilt pwrseq BUG=b:223985632 BRANCH=none TEST=MTL RVP boot up to kernel Signed-off-by: Li Feng Change-Id: I2371d9bb85434bb8ddbd4d4d8ff326b30218bc0a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3630884 Reviewed-by: Tanu Malhotra Reviewed-by: Andrew McRae Reviewed-by: Vijay P Hiremath --- zephyr/projects/intelrvp/BUILD.py | 3 ++- zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt | 1 + .../projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts | 15 --------------- zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf | 3 +++ zephyr/projects/intelrvp/mtlrvp/prj.conf | 2 +- zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf | 8 ++++++++ 6 files changed, 15 insertions(+), 17 deletions(-) create mode 100644 zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py index 755b6479a6..93e0b64c4a 100644 --- a/zephyr/projects/intelrvp/BUILD.py +++ b/zephyr/projects/intelrvp/BUILD.py @@ -69,10 +69,11 @@ register_intelrvp_project( here / "mtlrvp/mtlrvpp_npcx/interrupts.dts", here / "mtlrvp/ioex.dts", here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", + here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts", here / "adlrvp/adlrvp_npcx/temp_sensor.dts", ], extra_kconfig_files=[ - here / "legacy_ec_pwrseq.conf", + here / "zephyr_ap_pwrseq.conf", here / "mtlrvp/mtlrvpp_npcx/prj.conf", ], ) diff --git a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt index 75015a1068..d47b23c77f 100644 --- a/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/mtlrvp/CMakeLists.txt @@ -3,3 +3,4 @@ # found in the LICENSE file. zephyr_library_sources("src/mtlrvp.c") +zephyr_library_sources("src/board_power.c") diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts index 234acb3447..acf1630a71 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts @@ -21,21 +21,6 @@ flags = ; handler = "extpower_interrupt"; }; - int_slp_s0: slp_s0 { - irq-pin = <&pch_slp_s0_n>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_rsmrst_pwrgd: rsmrst_pwrgd { - irq-pin = <&rsmrst_pwrgd>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_all_sys_pwrgd: all_sys_pwrgd { - irq-pin = <&all_sys_pwrgd>; - flags = ; - handler = "power_signal_interrupt"; - }; int_ioex_kbd_intr_n: ioex_kbd_intr_n { irq-pin = <&ioex_kbd_intr_n>; flags = ; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf index 9a90e99a38..42abe0eeb1 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/prj.conf @@ -16,3 +16,6 @@ CONFIG_TACH_NPCX=y #RTC CONFIG_PLATFORM_EC_RTC=y + +#Zephyr debug options +CONFIG_LOG=y diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf index ecd3751b90..e89098701b 100644 --- a/zephyr/projects/intelrvp/mtlrvp/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -4,9 +4,9 @@ # Power Sequencing CONFIG_AP_X86_INTEL_MTL=y +CONFIG_X86_NON_DSX_PWRSEQ_MTL=y CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE=n CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_POWERSEQ_METEORLAKE=y # Battery CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y diff --git a/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf new file mode 100644 index 0000000000..3420d21d3b --- /dev/null +++ b/zephyr/projects/intelrvp/zephyr_ap_pwrseq.conf @@ -0,0 +1,8 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Inbuilt AP Power Sequencing Config +CONFIG_AP_PWRSEQ=y +CONFIG_X86_NON_DSX_PWRSEQ_CONSOLE=y +CONFIG_AP_PWRSEQ_S0IX=y -- cgit v1.2.1 From 5107e6f9b2b35e31e460fbd0d09df667b1f00d98 Mon Sep 17 00:00:00 2001 From: lschyi Date: Wed, 29 Jun 2022 15:44:33 +0800 Subject: corsola: Restructure Kconfigs of kingler and steelix Steelix shares most of configurations from kingler. Add an intermediate Kconfig to share the base configuration for projects use npcx993, then kingler and steelix share this base Kconfig. BUG=b:236769856 BRANCH=none TEST=run build for each project, can get firmwares without an error (1) zmake build kingler --clobber (2) zmake build steelix --clobber Also checked before/after of the file build/zephyr/$PROJECT/build-rw/zephyr/include/generated/autoconf.h, content of files are the same. Signed-off-by: lschyi Change-Id: Ie4051c632d1d6fe436c187759ea58f4f58138712 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733881 Reviewed-by: Ting Shen Commit-Queue: Sung-Chi Li Reviewed-by: Eric Yilun Lin Tested-by: Sung-Chi Li --- zephyr/projects/corsola/BUILD.py | 7 +- zephyr/projects/corsola/prj_kingler.conf | 129 ------------------------- zephyr/projects/corsola/prj_npcx993_base.conf | 134 ++++++++++++++++++++++++++ zephyr/projects/corsola/prj_steelix.conf | 5 +- 4 files changed, 140 insertions(+), 135 deletions(-) create mode 100644 zephyr/projects/corsola/prj_npcx993_base.conf diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index 8585f4e3aa..564eba5935 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -64,7 +64,10 @@ register_corsola_project( here / "usbc_kingler.dts", here / "default_gpio_pinctrl_kingler.dts", ], - extra_kconfig_files=[here / "prj_kingler.conf"], + extra_kconfig_files=[ + here / "prj_npcx993_base.conf", + here / "prj_kingler.conf", + ], ) register_corsola_project( @@ -88,7 +91,7 @@ register_corsola_project( here / "default_gpio_pinctrl_kingler.dts", ], extra_kconfig_files=[ - here / "prj_kingler.conf", + here / "prj_npcx993_base.conf", here / "prj_steelix.conf", ], ) diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf index 525d94a886..74fde119d9 100644 --- a/zephyr/projects/corsola/prj_kingler.conf +++ b/zephyr/projects/corsola/prj_kingler.conf @@ -2,138 +2,9 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# Cros EC -CONFIG_CROS_EC=y -CONFIG_PLATFORM_EC=y -CONFIG_PLATFORM_EC_BRINGUP=y -CONFIG_SHIMMED_TASKS=y -CONFIG_PLATFORM_EC_SWITCH=y - # Variant config CONFIG_BOARD_KINGLER=y CONFIG_VARIANT_CORSOLA_DB_DETECTION=y -# Shell features -CONFIG_KERNEL_SHELL=y -CONFIG_SHELL_HELP=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - -# Bring up options -CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y - -# ADC -CONFIG_ADC=y -CONFIG_PLATFORM_EC_ADC=y - -# Battery -CONFIG_PLATFORM_EC_BATTERY=y -CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y -CONFIG_PLATFORM_EC_BATTERY_SMART=y -CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y -CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y -CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y -CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y - -# CBI -CONFIG_EEPROM=y -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_SHELL=n -CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y -CONFIG_PLATFORM_EC_CBI_EEPROM=y - -# Charger -CONFIG_PLATFORM_EC_CHARGER=y -CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y -CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y -CONFIG_PLATFORM_EC_CHARGER_PSYS=y -CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y -CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 -CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 -CONFIG_PLATFORM_EC_CHARGE_MANAGER=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y - -# Host command -CONFIG_PLATFORM_EC_HOSTCMD=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - # LED -CONFIG_PLATFORM_EC_LED_COMMON=y -CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_LED_PWM=y - -# Math -CONFIG_PLATFORM_EC_MATH_UTIL=y - -# Power sequencing -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8186=y -CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y -CONFIG_PLATFORM_EC_POWERSEQ=y -CONFIG_PLATFORM_EC_POWERSEQ_S4=n -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n - -# Button -CONFIG_PLATFORM_EC_POWER_BUTTON=y -CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y -CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y - -# Sensors -CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y -CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y -CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y -CONFIG_PLATFORM_EC_ACCEL_FIFO=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y -CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y -CONFIG_PLATFORM_EC_LID_ANGLE=y -CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y -CONFIG_PLATFORM_EC_LID_SWITCH=y -CONFIG_PLATFORM_EC_MOTIONSENSE=y -CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y -CONFIG_PLATFORM_EC_TABLET_MODE=y -CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y - -# USBA -CONFIG_PLATFORM_EC_USBA=y - -# USBC -CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y -CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n -CONFIG_PLATFORM_EC_USBC=y -CONFIG_PLATFORM_EC_USBC_PPC=y -CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y -CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y -CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y -CONFIG_PLATFORM_EC_USB_MUX_PS8743=y -CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y -CONFIG_PLATFORM_EC_USB_PD_FRS=y -CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_LOGGING=y -CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y -CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 -CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y - -# External power -CONFIG_PLATFORM_EC_BACKLIGHT_LID=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y - -# Keyboard -CONFIG_CROS_KB_RAW_NPCX=y -CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y - -CONFIG_SYSCON=y - -CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf new file mode 100644 index 0000000000..09124a1511 --- /dev/null +++ b/zephyr/projects/corsola/prj_npcx993_base.conf @@ -0,0 +1,134 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Cros EC +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_BRINGUP=y +CONFIG_SHIMMED_TASKS=y +CONFIG_PLATFORM_EC_SWITCH=y + +# Shell features +CONFIG_KERNEL_SHELL=y +CONFIG_SHELL_HELP=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y +CONFIG_SHELL_HISTORY=y + +# Bring up options +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y + +# ADC +CONFIG_ADC=y +CONFIG_PLATFORM_EC_ADC=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_CBI_EEPROM=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CHARGE_MANAGER=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y + +# Host command +CONFIG_PLATFORM_EC_HOSTCMD=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y + +# Math +CONFIG_PLATFORM_EC_MATH_UTIL=y + +# Power sequencing +CONFIG_AP=y +CONFIG_AP_ARM_MTK_MT8186=y +CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_S4=n +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n + +# Button +CONFIG_PLATFORM_EC_POWER_BUTTON=y +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y + +# Sensors +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_LID_SWITCH=y +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# USBA +CONFIG_PLATFORM_EC_USBA=y + +# USBC +CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y +CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n +CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USBC_PPC=y +CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y +CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y +CONFIG_PLATFORM_EC_USB_MUX_PS8743=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y +CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 +CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y + +# External power +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y + +# Keyboard +CONFIG_CROS_KB_RAW_NPCX=y +CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE=y + +CONFIG_SYSCON=y + +CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=n diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf index 48971c9ed4..a22c3ece43 100644 --- a/zephyr/projects/corsola/prj_steelix.conf +++ b/zephyr/projects/corsola/prj_steelix.conf @@ -3,11 +3,8 @@ # found in the LICENSE file. # Variant config -CONFIG_BOARD_KINGLER=n CONFIG_BOARD_STEELIX=y +CONFIG_VARIANT_CORSOLA_DB_DETECTION=y # steelix only use D2, drop the workaround config for H1 CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n - -# LED -CONFIG_PLATFORM_EC_LED_PWM=n -- cgit v1.2.1 From 700936478a9c1f243763870398542c74f4a50468 Mon Sep 17 00:00:00 2001 From: lschyi Date: Wed, 29 Jun 2022 15:54:46 +0800 Subject: corsola: Restructure Kconfigs of krabby and tentacruel Tentacruel shares most of of configurations from krabby. Add an intermediate Kconfig to share the base configuration for projects use it81202, then krabby and tentacruel share this base Kconfig. BUG=b:236769856 BRANCH=none TEST=run build for each project, can get firmwares without an error (1) zmake build krabby --clobber (2) zmake build tentacruel --clobber Also checked before/after of the file build/zephyr/$PROJECT/build-rw/zephyr/include/generated/autoconf.h, content of files are the same. Signed-off-by: lschyi Change-Id: I8b9094fcb820d0fda93c41806112da6c3316b8f9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733882 Reviewed-by: Ting Shen Reviewed-by: Eric Yilun Lin Commit-Queue: Sung-Chi Li Tested-by: Sung-Chi Li --- zephyr/projects/corsola/BUILD.py | 7 +- zephyr/projects/corsola/prj_it81202_base.conf | 137 ++++++++++++++++++++++++++ zephyr/projects/corsola/prj_krabby.conf | 137 +------------------------- zephyr/projects/corsola/prj_tentacruel.conf | 1 - 4 files changed, 144 insertions(+), 138 deletions(-) create mode 100644 zephyr/projects/corsola/prj_it81202_base.conf diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index 564eba5935..baa595a0ca 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -44,7 +44,10 @@ register_corsola_project( here / "motionsense_krabby.dts", here / "usbc_krabby.dts", ], - extra_kconfig_files=[here / "prj_krabby.conf"], + extra_kconfig_files=[ + here / "prj_it81202_base.conf", + here / "prj_krabby.conf", + ], ) register_corsola_project( @@ -111,7 +114,7 @@ register_corsola_project( here / "usbc_krabby.dts", ], extra_kconfig_files=[ - here / "prj_krabby.conf", + here / "prj_it81202_base.conf", here / "prj_tentacruel.conf", ], ) diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf new file mode 100644 index 0000000000..e7f8ca467e --- /dev/null +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -0,0 +1,137 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_SHIMMED_TASKS=y + +# AP SoC configuration +CONFIG_AP=y +CONFIG_AP_ARM_MTK_MT8186=y + +# Bring up options +CONFIG_KERNEL_SHELL=y +CONFIG_SHELL_HISTORY_BUFFER=256 +CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y +CONFIG_PLATFORM_EC_BRINGUP=y + +# VARIANT config +CONFIG_VARIANT_CORSOLA_DB_DETECTION=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_CBI_EEPROM=y + +# Power Sequencing +CONFIG_PLATFORM_EC_POWERSEQ=y +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y + +# Lid Switch +CONFIG_PLATFORM_EC_LID_SWITCH=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000 +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGE_MANAGER=y +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_RT9490=y +CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y +CONFIG_PLATFORM_EC_CHARGER_OTG=y +CONFIG_PLATFORM_EC_CHARGER_PSYS=y +CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y +# BOARD_RS2 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 +# BOARD_RS1 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y + +# Host Commands +CONFIG_PLATFORM_EC_HOSTCMD=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y +CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y +CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y +CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 + +# Keyboard +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y +CONFIG_PLATFORM_EC_CMD_BUTTON=y + +# Sensors +CONFIG_PLATFORM_EC_MOTIONSENSE=y +CONFIG_PLATFORM_EC_ACCEL_FIFO=y +CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y +CONFIG_PLATFORM_EC_LID_ANGLE=y +CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y +CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_PLATFORM_EC_TABLET_MODE=y +CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y + +# Sensor Drivers +CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y +CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y + +# Tasks +CONFIG_TASK_CHARGER_STACK_SIZE=1024 +CONFIG_TASK_CHIPSET_STACK_SIZE=1440 +CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024 +CONFIG_TASK_PD_STACK_SIZE=1280 + +# USB-A +CONFIG_PLATFORM_EC_USBA=y + +# USB-C +CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n +CONFIG_PLATFORM_EC_SMBUS_PEC=y +CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y +CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y +CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y +CONFIG_PLATFORM_EC_USB_MUX_IT5205=y +CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y +CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y +CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT=2 +CONFIG_PLATFORM_EC_USB_PD_LOGGING=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n +CONFIG_PLATFORM_EC_USB_PD_USB4=n +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n + +# TODO(b/180980668): bring these features up +CONFIG_LTO=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/projects/corsola/prj_krabby.conf b/zephyr/projects/corsola/prj_krabby.conf index 0cd8181b6d..384dfe5cdd 100644 --- a/zephyr/projects/corsola/prj_krabby.conf +++ b/zephyr/projects/corsola/prj_krabby.conf @@ -1,139 +1,6 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The Chromium OS Authors. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -CONFIG_CROS_EC=y -CONFIG_PLATFORM_EC=y -CONFIG_SHIMMED_TASKS=y - +# Variant config CONFIG_BOARD_KRABBY=y - -# AP SoC configuration -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8186=y - -# Bring up options -CONFIG_KERNEL_SHELL=y -CONFIG_SHELL_HISTORY_BUFFER=256 -CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y -CONFIG_PLATFORM_EC_BRINGUP=y - -# VARIANT config -CONFIG_VARIANT_CORSOLA_DB_DETECTION=y - -# CBI -CONFIG_EEPROM=y -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_SHELL=n -CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y -CONFIG_PLATFORM_EC_CBI_EEPROM=y - -# Power Sequencing -CONFIG_PLATFORM_EC_POWERSEQ=y -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y -CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y - -# Lid Switch -CONFIG_PLATFORM_EC_LID_SWITCH=y - -# Battery -CONFIG_PLATFORM_EC_BATTERY=y -CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y -CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y -CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y -CONFIG_PLATFORM_EC_BATTERY_SMART=y -CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000 -CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y -CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y - -# Charger -CONFIG_PLATFORM_EC_CHARGER=y -CONFIG_PLATFORM_EC_CHARGE_MANAGER=y -CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y -CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y -CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y -CONFIG_PLATFORM_EC_CHARGER_RT9490=y -CONFIG_PLATFORM_EC_CHARGER_MAINTAIN_VBAT=y -CONFIG_PLATFORM_EC_CHARGER_OTG=y -CONFIG_PLATFORM_EC_CHARGER_PSYS=y -CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y -# BOARD_RS2 -CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 -# BOARD_RS1 -CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 -CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y - -# Host Commands -CONFIG_PLATFORM_EC_HOSTCMD=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y -CONFIG_PLATFORM_EC_CONSOLE_CMD_SYSINFO=y -CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y - -# LED -CONFIG_PLATFORM_EC_LED_COMMON=y -CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y -CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 - -# Keyboard -CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y -CONFIG_PLATFORM_EC_CMD_BUTTON=y - -# Sensors -CONFIG_PLATFORM_EC_MOTIONSENSE=y -CONFIG_PLATFORM_EC_ACCEL_FIFO=y -CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y -CONFIG_PLATFORM_EC_LID_ANGLE=y -CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y -CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y -CONFIG_PLATFORM_EC_SWITCH=y -CONFIG_PLATFORM_EC_TABLET_MODE=y -CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y - -# Sensor Drivers -CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y -CONFIG_PLATFORM_EC_ACCELGYRO_ICM42607=y -CONFIG_PLATFORM_EC_ACCELGYRO_ICM_COMM_I2C=y - -# Tasks -CONFIG_TASK_CHARGER_STACK_SIZE=1024 -CONFIG_TASK_CHIPSET_STACK_SIZE=1440 -CONFIG_TASK_MOTIONSENSE_STACK_SIZE=1024 -CONFIG_TASK_PD_STACK_SIZE=1280 - -# USB-A -CONFIG_PLATFORM_EC_USBA=y - -# USB-C -CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n -CONFIG_PLATFORM_EC_SMBUS_PEC=y -CONFIG_PLATFORM_EC_USBC=y -CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y -CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y -CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y -CONFIG_PLATFORM_EC_USBC_PPC_SYV682X=y -CONFIG_PLATFORM_EC_USB_MUX_IT5205=y -CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y -CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y -CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y -CONFIG_PLATFORM_EC_USB_PD_FRS=y -CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y -CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT=2 -CONFIG_PLATFORM_EC_USB_PD_LOGGING=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y -CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y -CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n -CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n -CONFIG_PLATFORM_EC_USB_PD_USB4=n -CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n - -# TODO(b/180980668): bring these features up -CONFIG_LTO=n -CONFIG_PLATFORM_EC_BACKLIGHT_LID=n diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf index 4949b28351..9d05fd5bfb 100644 --- a/zephyr/projects/corsola/prj_tentacruel.conf +++ b/zephyr/projects/corsola/prj_tentacruel.conf @@ -3,5 +3,4 @@ # found in the LICENSE file. # Variant config -CONFIG_BOARD_KRABBY=n CONFIG_BOARD_TENTACRUEL=y -- cgit v1.2.1 From f2b8cbcd518b6c34a637cf79d679a7f66614c334 Mon Sep 17 00:00:00 2001 From: lschyi Date: Thu, 30 Jun 2022 13:39:14 +0800 Subject: corsola: Cleanup project wise Kconfig Cleanup shared project wise config from npcx993_base, it81202_base, and some from device specific Kconfig files. BUG=b:236769856 BRANCH=none TEST=run build for each project, can get firmwares without an error (1) zmake build kingler --clobber (2) zmake build steelix --clobber (3) zmake build krabby --clobber (4) zmake build tentacruel --clobber Also checked before/after of the file build/zephyr/$PROJECT/build-rw/zephyr/include/generated/autoconf.h, content of files are the same. Signed-off-by: lschyi Change-Id: I40e3e930dccc41b127153924bed584c6adec97ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3736405 Reviewed-by: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Sung-Chi Li Tested-by: Sung-Chi Li --- zephyr/projects/corsola/prj.conf | 51 +++++++++++++++++++++++++++ zephyr/projects/corsola/prj_it81202_base.conf | 40 --------------------- zephyr/projects/corsola/prj_kingler.conf | 1 - zephyr/projects/corsola/prj_npcx993_base.conf | 37 ------------------- zephyr/projects/corsola/prj_steelix.conf | 1 - 5 files changed, 51 insertions(+), 79 deletions(-) diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index a49660c7cf..27dbefcdde 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -6,6 +6,29 @@ # http://google3/hardware/standards/usb/ CONFIG_PLATFORM_EC_USB_PID=0x505C +# CROS EC +CONFIG_CROS_EC=y +CONFIG_PLATFORM_EC=y +CONFIG_PLATFORM_EC_SWITCH=y +CONFIG_SHIMMED_TASKS=y + +# AP SoC configuration +CONFIG_AP=y +CONFIG_AP_ARM_MTK_MT8186=y + +# Variant config +CONFIG_VARIANT_CORSOLA_DB_DETECTION=y + +# Shell features +CONFIG_KERNEL_SHELL=y + +# CBI +CONFIG_EEPROM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_SHELL=n +CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y +CONFIG_PLATFORM_EC_CBI_EEPROM=y + # I2C CONFIG_I2C=y @@ -29,9 +52,18 @@ CONFIG_PLATFORM_EC_USB_PD_USB4=n CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y +# USB-C +CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y +CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y +CONFIG_PLATFORM_EC_USB_PD_FRS=y + # Power Seq CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y +CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y +CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y +CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y # Optional features @@ -39,3 +71,22 @@ CONFIG_FLASH_SHELL=n # EEPROM CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y + +# Host Commands +CONFIG_PLATFORM_EC_HOSTCMD=y + +# Battery +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y +CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGE_MANAGER=y + +# Button +CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf index e7f8ca467e..b9c1713f1b 100644 --- a/zephyr/projects/corsola/prj_it81202_base.conf +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -2,52 +2,21 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -CONFIG_CROS_EC=y -CONFIG_PLATFORM_EC=y -CONFIG_SHIMMED_TASKS=y - -# AP SoC configuration -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8186=y - # Bring up options -CONFIG_KERNEL_SHELL=y CONFIG_SHELL_HISTORY_BUFFER=256 CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y CONFIG_PLATFORM_EC_BRINGUP=y -# VARIANT config -CONFIG_VARIANT_CORSOLA_DB_DETECTION=y - -# CBI -CONFIG_EEPROM=y -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_SHELL=n -CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y -CONFIG_PLATFORM_EC_CBI_EEPROM=y - # Power Sequencing -CONFIG_PLATFORM_EC_POWERSEQ=y -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y # Lid Switch CONFIG_PLATFORM_EC_LID_SWITCH=y # Battery -CONFIG_PLATFORM_EC_BATTERY=y -CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y -CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y -CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y -CONFIG_PLATFORM_EC_BATTERY_SMART=y CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=9000 -CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y -CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y # Charger -CONFIG_PLATFORM_EC_CHARGER=y -CONFIG_PLATFORM_EC_CHARGE_MANAGER=y CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y @@ -63,7 +32,6 @@ CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_DUMP=y # Host Commands -CONFIG_PLATFORM_EC_HOSTCMD=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y @@ -76,7 +44,6 @@ CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 # Keyboard -CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y CONFIG_PLATFORM_EC_CMD_BUTTON=y # Sensors @@ -86,7 +53,6 @@ CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y CONFIG_PLATFORM_EC_LID_ANGLE=y CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y -CONFIG_PLATFORM_EC_SWITCH=y CONFIG_PLATFORM_EC_TABLET_MODE=y CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y @@ -107,7 +73,6 @@ CONFIG_PLATFORM_EC_USBA=y # USB-C CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n CONFIG_PLATFORM_EC_SMBUS_PEC=y -CONFIG_PLATFORM_EC_USBC=y CONFIG_PLATFORM_EC_USBC_PPC_DEDICATED_INT=y CONFIG_PLATFORM_EC_USBC_PPC_RT1739=y CONFIG_PLATFORM_EC_USBC_PPC_SYV682C=y @@ -116,9 +81,6 @@ CONFIG_PLATFORM_EC_USB_MUX_IT5205=y CONFIG_PLATFORM_EC_USB_MUX_TUSB546=y CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y -CONFIG_PLATFORM_EC_USB_PD_FRS=y CONFIG_PLATFORM_EC_USB_PD_FRS_PPC=y CONFIG_PLATFORM_EC_USB_PD_ITE_ACTIVE_PORT_COUNT=2 CONFIG_PLATFORM_EC_USB_PD_LOGGING=y @@ -129,8 +91,6 @@ CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n -CONFIG_PLATFORM_EC_USB_PD_USB4=n -CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n # TODO(b/180980668): bring these features up CONFIG_LTO=n diff --git a/zephyr/projects/corsola/prj_kingler.conf b/zephyr/projects/corsola/prj_kingler.conf index 74fde119d9..ed5f402c0c 100644 --- a/zephyr/projects/corsola/prj_kingler.conf +++ b/zephyr/projects/corsola/prj_kingler.conf @@ -4,7 +4,6 @@ # Variant config CONFIG_BOARD_KINGLER=y -CONFIG_VARIANT_CORSOLA_DB_DETECTION=y # LED CONFIG_PLATFORM_EC_LED_PWM=y diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf index 09124a1511..0160760ba8 100644 --- a/zephyr/projects/corsola/prj_npcx993_base.conf +++ b/zephyr/projects/corsola/prj_npcx993_base.conf @@ -3,14 +3,9 @@ # found in the LICENSE file. # Cros EC -CONFIG_CROS_EC=y -CONFIG_PLATFORM_EC=y CONFIG_PLATFORM_EC_BRINGUP=y -CONFIG_SHIMMED_TASKS=y -CONFIG_PLATFORM_EC_SWITCH=y # Shell features -CONFIG_KERNEL_SHELL=y CONFIG_SHELL_HELP=y CONFIG_SHELL_TAB=y CONFIG_SHELL_TAB_AUTOCOMPLETION=y @@ -23,36 +18,14 @@ CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y CONFIG_ADC=y CONFIG_PLATFORM_EC_ADC=y -# Battery -CONFIG_PLATFORM_EC_BATTERY=y -CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y -CONFIG_PLATFORM_EC_BATTERY_SMART=y -CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y -CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y -CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y -CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y - -# CBI -CONFIG_EEPROM=y -CONFIG_EEPROM_AT24=y -CONFIG_EEPROM_SHELL=n -CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y -CONFIG_PLATFORM_EC_CBI_EEPROM=y - # Charger -CONFIG_PLATFORM_EC_CHARGER=y CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y CONFIG_PLATFORM_EC_CHARGER_ISL9238C=y CONFIG_PLATFORM_EC_CHARGER_PSYS=y CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10 CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20 -CONFIG_PLATFORM_EC_CHARGE_MANAGER=y CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y - -# Host command -CONFIG_PLATFORM_EC_HOSTCMD=y # PWM CONFIG_PWM=y @@ -66,16 +39,11 @@ CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_MATH_UTIL=y # Power sequencing -CONFIG_AP=y -CONFIG_AP_ARM_MTK_MT8186=y CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y -CONFIG_PLATFORM_EC_POWERSEQ=y CONFIG_PLATFORM_EC_POWERSEQ_S4=n -CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n # Button CONFIG_PLATFORM_EC_POWER_BUTTON=y -CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y # Sensors @@ -100,17 +68,13 @@ CONFIG_PLATFORM_EC_USBA=y # USBC CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n -CONFIG_PLATFORM_EC_USBC=y CONFIG_PLATFORM_EC_USBC_PPC=y CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y CONFIG_PLATFORM_EC_USB_MUX_PS8743=y CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y -CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y -CONFIG_PLATFORM_EC_USB_PD_FRS=y CONFIG_PLATFORM_EC_USB_PD_FRS_TCPC=y CONFIG_PLATFORM_EC_USB_PD_LOGGING=y CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y @@ -123,7 +87,6 @@ CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_BY_BOARD=y # External power CONFIG_PLATFORM_EC_BACKLIGHT_LID=n -CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y # Keyboard CONFIG_CROS_KB_RAW_NPCX=y diff --git a/zephyr/projects/corsola/prj_steelix.conf b/zephyr/projects/corsola/prj_steelix.conf index a22c3ece43..b7f861ba60 100644 --- a/zephyr/projects/corsola/prj_steelix.conf +++ b/zephyr/projects/corsola/prj_steelix.conf @@ -4,7 +4,6 @@ # Variant config CONFIG_BOARD_STEELIX=y -CONFIG_VARIANT_CORSOLA_DB_DETECTION=y # steelix only use D2, drop the workaround config for H1 CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=n -- cgit v1.2.1 From 7e05c7daed529c50ceda92e0ffcf0ebda3719c76 Mon Sep 17 00:00:00 2001 From: lschyi Date: Thu, 30 Jun 2022 15:30:35 +0800 Subject: corsola: Unify common configurations Unify common configurations used in Corsola projects for npcx993 and it81202. BUG=b:236769856 BRANCH=none TEST=run build for each project, can get firmwares without an error (1) zmake build kingler --clobber (2) zmake build steelix --clobber (3) zmake build krabby --clobber (4) zmake build tentacruel --clobber Signed-off-by: lschyi Change-Id: Ic159257d192c06f0bca82c39a0d4bcba7218e7f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3737662 Commit-Queue: Sung-Chi Li Reviewed-by: Eric Yilun Lin Tested-by: Sung-Chi Li --- zephyr/projects/corsola/prj.conf | 8 ++++++++ zephyr/projects/corsola/prj_it81202_base.conf | 4 ---- zephyr/projects/corsola/prj_npcx993_base.conf | 8 -------- 3 files changed, 8 insertions(+), 12 deletions(-) diff --git a/zephyr/projects/corsola/prj.conf b/zephyr/projects/corsola/prj.conf index 27dbefcdde..a7ab75e215 100644 --- a/zephyr/projects/corsola/prj.conf +++ b/zephyr/projects/corsola/prj.conf @@ -21,6 +21,10 @@ CONFIG_VARIANT_CORSOLA_DB_DETECTION=y # Shell features CONFIG_KERNEL_SHELL=y +CONFIG_SHELL_HELP=y +CONFIG_SHELL_HISTORY=y +CONFIG_SHELL_TAB=y +CONFIG_SHELL_TAB_AUTOCOMPLETION=y # CBI CONFIG_EEPROM=y @@ -47,6 +51,7 @@ CONFIG_PLATFORM_EC_VBOOT_EFS2=y # USB CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=n +CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n CONFIG_PLATFORM_EC_USB_PD_USB4=n # TODO(b/226411332): fix single task USB_CHG for Corsola CONFIG_PLATFORM_EC_USB_CHARGER_SINGLE_TASK=n @@ -54,6 +59,7 @@ CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB_CUSTOM_HOOK=y # USB-C CONFIG_PLATFORM_EC_USBC=y +CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO=y CONFIG_PLATFORM_EC_USB_PD_DP_HPD_GPIO_CUSTOM=y CONFIG_PLATFORM_EC_USB_PD_FRS=y @@ -89,4 +95,6 @@ CONFIG_PLATFORM_EC_CHARGER=y CONFIG_PLATFORM_EC_CHARGE_MANAGER=y # Button +CONFIG_PLATFORM_EC_CMD_BUTTON=y +CONFIG_PLATFORM_EC_POWER_BUTTON=y CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf index b9c1713f1b..34267c423e 100644 --- a/zephyr/projects/corsola/prj_it81202_base.conf +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -43,9 +43,6 @@ CONFIG_PLATFORM_EC_LED_COMMON=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 -# Keyboard -CONFIG_PLATFORM_EC_CMD_BUTTON=y - # Sensors CONFIG_PLATFORM_EC_MOTIONSENSE=y CONFIG_PLATFORM_EC_ACCEL_FIFO=y @@ -90,7 +87,6 @@ CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_MEASURE_ADC_EACH_PORT=y CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=n -CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n # TODO(b/180980668): bring these features up CONFIG_LTO=n diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf index 0160760ba8..4d4a6f8bde 100644 --- a/zephyr/projects/corsola/prj_npcx993_base.conf +++ b/zephyr/projects/corsola/prj_npcx993_base.conf @@ -5,12 +5,6 @@ # Cros EC CONFIG_PLATFORM_EC_BRINGUP=y -# Shell features -CONFIG_SHELL_HELP=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y - # Bring up options CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y @@ -43,7 +37,6 @@ CONFIG_PLATFORM_EC_POWERSEQ_MT8186=y CONFIG_PLATFORM_EC_POWERSEQ_S4=n # Button -CONFIG_PLATFORM_EC_POWER_BUTTON=y CONFIG_PLATFORM_EC_BUTTONS_RUNTIME_CONFIG=y # Sensors @@ -71,7 +64,6 @@ CONFIG_PLATFORM_EC_BC12_SINGLE_DRIVER=n CONFIG_PLATFORM_EC_USBC_PPC=y CONFIG_PLATFORM_EC_USBC_PPC_NX20P3483=y CONFIG_PLATFORM_EC_USBC_PPC_RT1718S=y -CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y CONFIG_PLATFORM_EC_USB_MUX_PS8743=y CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y -- cgit v1.2.1 From 0c7b1d9720377c5c6922ab9cc9d692aca6fb8bf5 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Thu, 30 Jun 2022 08:54:28 +0000 Subject: Revert "burnet: Replace 2nd source base accel sensor" This reverts commit 2d90081520b78e1124688c914cd03b26aa543d8c. Reason for revert: deprecate ICM-42607 and resume ICM-40608 Original change's description: > burnet: Replace 2nd source base accel sensor > > This patch replaces 2nd source base accelerometer to ICM-42607. > > BUG=b:230553688 > BRANCH=firmware-kukui-12573.B > TEST=On Burnet. Sensor works. > > Signed-off-by: Devin Lu > Change-Id: Ia5456f2f87d644821371ac0ffdea16c07a5c3fff > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508936 > Reviewed-by: Eric Yilun Lin Bug: b:230553688 Change-Id: I4e085c55e4ed790ced3506ff9a39dae6ffb91c26 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3737695 Reviewed-by: Ting Shen Tested-by: Devin Lu Commit-Queue: Devin Lu --- board/burnet/board.c | 48 ++++++++++++++++++++++++------------------------ board/burnet/board.h | 6 +++--- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/board/burnet/board.c b/board/burnet/board.c index 23abc2dad9..3e99529f81 100644 --- a/board/burnet/board.c +++ b/board/burnet/board.c @@ -17,7 +17,7 @@ #include "driver/accel_kionix.h" #include "driver/accelgyro_bmi_common.h" #include "driver/accelgyro_icm_common.h" -#include "driver/accelgyro_icm42607.h" +#include "driver/accelgyro_icm426xx.h" #include "driver/battery/max17055.h" #include "driver/bc12/pi3usb9201.h" #include "driver/charger/isl923x.h" @@ -339,7 +339,7 @@ static const mat33_fp_t base_bmi160_ref = { {0, 0, FLOAT_TO_FP(-1)} }; -static const mat33_fp_t base_icm42607_ref = { +static const mat33_fp_t base_icm426xx_ref = { {0, FLOAT_TO_FP(-1), 0}, {FLOAT_TO_FP(-1), 0, 0}, {0, 0, FLOAT_TO_FP(-1)} @@ -349,7 +349,7 @@ static const mat33_fp_t base_icm42607_ref = { static struct accelgyro_saved_data_t g_bma253_data; static struct kionix_accel_data g_kx022_data; static struct bmi_drv_data_t g_bmi160_data; -static struct icm_drv_data_t g_icm42607_data; +static struct icm_drv_data_t g_icm426xx_data; struct motion_sensor_t lid_accel_kx022 = { .name = "Lid Accel", @@ -374,21 +374,21 @@ struct motion_sensor_t lid_accel_kx022 = { }, }; -struct motion_sensor_t base_accel_icm42607 = { +struct motion_sensor_t base_accel_icm426xx = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, + .chip = MOTIONSENSE_CHIP_ICM426XX, .type = MOTIONSENSE_TYPE_ACCEL, .location = MOTIONSENSE_LOC_BASE, - .drv = &icm42607_drv, + .drv = &icm426xx_drv, .mutex = &g_base_mutex, - .drv_data = &g_icm42607_data, + .drv_data = &g_icm426xx_data, .port = CONFIG_SPI_ACCEL_PORT, .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT), .default_range = 4, - .rot_standard_ref = &base_icm42607_ref, - .min_frequency = ICM42607_ACCEL_MIN_FREQ, - .max_frequency = ICM42607_ACCEL_MAX_FREQ, + .rot_standard_ref = &base_icm426xx_ref, + .min_frequency = ICM426XX_ACCEL_MIN_FREQ, + .max_frequency = ICM426XX_ACCEL_MAX_FREQ, .config = { /* EC use accel for angle detection */ [SENSOR_CONFIG_EC_S0] = { @@ -401,21 +401,21 @@ struct motion_sensor_t base_accel_icm42607 = { }, }; -struct motion_sensor_t base_gyro_icm42607 = { +struct motion_sensor_t base_gyro_icm426xx = { .name = "Base Gyro", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, + .chip = MOTIONSENSE_CHIP_ICM426XX, .type = MOTIONSENSE_TYPE_GYRO, .location = MOTIONSENSE_LOC_BASE, - .drv = &icm42607_drv, + .drv = &icm426xx_drv, .mutex = &g_base_mutex, - .drv_data = &g_icm42607_data, + .drv_data = &g_icm426xx_data, .port = CONFIG_SPI_ACCEL_PORT, .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT), .default_range = 1000, /* dps */ - .rot_standard_ref = &base_icm42607_ref, - .min_frequency = ICM42607_GYRO_MIN_FREQ, - .max_frequency = ICM42607_GYRO_MAX_FREQ, + .rot_standard_ref = &base_icm426xx_ref, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; struct motion_sensor_t motion_sensors[] = { @@ -500,8 +500,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); void sensor_interrupt(enum gpio_signal signal) { switch (motion_sensors[BASE_ACCEL].chip) { - case MOTIONSENSE_CHIP_ICM42607: - icm42607_interrupt(signal); + case MOTIONSENSE_CHIP_ICM426XX: + icm426xx_interrupt(signal); break; case MOTIONSENSE_CHIP_BMI160: default: @@ -522,12 +522,12 @@ static void board_update_config(void) if (rv == EC_SUCCESS) motion_sensors[LID_ACCEL] = lid_accel_kx022; - /* Read icm-42607 chip content */ - rv = icm_read8(&base_accel_icm42607, ICM42607_REG_WHO_AM_I, &val); + /* Read icm-40608 chip content */ + rv = icm_read8(&base_accel_icm426xx, ICM426XX_REG_WHO_AM_I, &val); - if (rv == EC_SUCCESS && val == ICM42607_CHIP_ICM42607P) { - motion_sensors[BASE_ACCEL] = base_accel_icm42607; - motion_sensors[BASE_GYRO] = base_gyro_icm42607; + if (rv == EC_SUCCESS && val == ICM426XX_CHIP_ICM40608) { + motion_sensors[BASE_ACCEL] = base_accel_icm426xx; + motion_sensors[BASE_GYRO] = base_gyro_icm426xx; } CPRINTS("Lid Accel Chip: %d", motion_sensors[LID_ACCEL].chip); diff --git a/board/burnet/board.h b/board/burnet/board.h index 8702502d69..b367f42eb8 100644 --- a/board/burnet/board.h +++ b/board/burnet/board.h @@ -57,9 +57,9 @@ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -/* ICM42607 Base accel/gyro */ -#define CONFIG_ACCELGYRO_ICM42607 -#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ +/* ICM426XX Base accel/gyro */ +#define CONFIG_ACCELGYRO_ICM426XX +#define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ALS #define CONFIG_CMD_ACCEL_INFO -- cgit v1.2.1 From 3ad5afaa8678d8a8310879a91e762f7be5f78f12 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Wed, 29 Jun 2022 15:07:53 +0200 Subject: zephyr: tests: init the TCPCI revision Some tests don't initialize the TCPCI revision. It causes failures when the order of test runs is changed. Add ZTEST_RULE to initialize the revision to 2.0. Tests that need the revision 1.0 have to reconfigure it. BUG=b:233645785 TEST=enable the test shuffling; make sure there is no "defined only for revision" string in the output BRANCH=main Signed-off-by: Dawid Niedzwiecki Change-Id: I94ab33f56f1e582d1e8420eaf87617d616309c7e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735402 Reviewed-by: Yuval Peress Commit-Queue: Dawid Niedzwiecki --- .../test/drivers/src/console_cmd/charge_manager.c | 1 - zephyr/test/drivers/src/integration/usbc/usb.c | 1 + .../src/integration/usbc/usb_5v_3a_pd_sink.c | 1 - .../src/integration/usbc/usb_5v_3a_pd_source.c | 4 ---- .../drivers/src/integration/usbc/usb_alt_mode.c | 3 --- .../src/integration/usbc/usb_attach_src_snk.c | 6 ------ .../src/integration/usbc/usb_malfunction_sink.c | 2 -- .../drivers/src/integration/usbc/usb_pd_ctrl_msg.c | 2 -- .../drivers/src/integration/usbc/usb_pd_rev3.c | 4 ---- zephyr/test/drivers/src/tcpci.c | 8 ++------ zephyr/test/drivers/src/tcpci_test_common.c | 13 +----------- zephyr/test/drivers/src/test_rules.c | 23 ++++++++++++++++++++++ 12 files changed, 27 insertions(+), 41 deletions(-) diff --git a/zephyr/test/drivers/src/console_cmd/charge_manager.c b/zephyr/test/drivers/src/console_cmd/charge_manager.c index e4756bbb1b..e604570443 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_manager.c +++ b/zephyr/test/drivers/src/console_cmd/charge_manager.c @@ -55,7 +55,6 @@ static void *console_cmd_charge_manager_setup(void) emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); /* Initialized the sink to request 5V and 3A */ tcpci_partner_init(&test_fixture.sink_5v_3a, PD_REV20); diff --git a/zephyr/test/drivers/src/integration/usbc/usb.c b/zephyr/test/drivers/src/integration/usbc/usb.c index 2344ca5935..93a37a356f 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb.c +++ b/zephyr/test/drivers/src/integration/usbc/usb.c @@ -58,6 +58,7 @@ static void integration_usb_before(void *state) */ zassert_ok(tcpc_config[0].drv->init(0), NULL); zassert_ok(tcpc_config[1].drv->init(1), NULL); + tcpc_config[USBC_PORT_C0].flags &= ~TCPC_FLAGS_TCPCI_REV2_0; tcpci_emul_set_rev(tcpci_emul, TCPCI_EMUL_REV1_0_VER1_0); pd_set_suspend(0, 0); pd_set_suspend(1, 0); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c index 6380eaecf2..f7f73d42b0 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c @@ -80,7 +80,6 @@ static void *usb_attach_5v_3a_pd_sink_setup(void) emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); return &test_fixture; } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c index 95e3b47feb..9258c4cee0 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c @@ -37,10 +37,6 @@ static void *usb_attach_5v_3a_pd_source_setup(void) test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - /* Configure TCPCI revision in board config and emulator */ - tcpc_config[0].flags |= TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - /* Initialized the charger to supply 5V and 3A */ tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV20); test_fixture.source_5v_3a.extensions = diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 5d457b846e..04b98b4a28 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -142,9 +142,6 @@ static void *usbc_alt_mode_setup(void) /* Get references for the emulators */ fixture.tcpci_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); - /* The configured TCPCI rev must match the emulator's supported rev. */ - tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c index 90409b2a83..5205952522 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_attach_src_snk.c @@ -167,9 +167,6 @@ static void attach_emulated_snk(struct emul_state *my_emul_state) struct tcpci_partner_data *my_snk = &my_emul_state->my_snk; uint16_t power_reg_val; - /* Attach emulated sink */ - tcpci_emul_set_rev(tcpci_emul_snk, TCPCI_EMUL_REV2_0_VER1_1); - /* Turn on VBUS detection */ /* * TODO(b/223901282): integration tests should not be setting vbus @@ -200,9 +197,6 @@ static void attach_emulated_src(struct emul_state *my_emul_state) struct tcpci_partner_data *my_src = &my_emul_state->my_src; uint16_t power_reg_val; - /* Attach emulated charger. */ - tcpci_emul_set_rev(tcpci_emul_src, TCPCI_EMUL_REV2_0_VER1_1); - /* Turn on VBUS detection */ /* * TODO(b/223901282): integration tests should not be setting vbus diff --git a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c index 275817164f..2f1fd572c0 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c @@ -71,8 +71,6 @@ static void *usb_malfunction_sink_setup(void) emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - tcpc_config[0].flags = tcpc_config[0].flags | TCPC_FLAGS_TCPCI_REV2_0; /* Initialized the sink to request 5V and 3A */ tcpci_partner_init(&test_fixture.sink, PD_REV20); diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c index 6aee4b86d8..a049b92ccc 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c @@ -80,8 +80,6 @@ static void *usb_pd_ctrl_msg_setup_emul(void) fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - return &fixture; } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c index f4022a026d..a12521f19e 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c @@ -39,10 +39,6 @@ static void *usb_attach_5v_3a_pd_source_setup(void) test_fixture.charger_emul = emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - /* Configure TCPCI revision in board config and emulator */ - tcpc_config[TEST_USB_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(test_fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - /* Initialized the charger to supply 5V and 3A */ tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV30); test_fixture.source_5v_3a.extensions = tcpci_src_emul_init( diff --git a/zephyr/test/drivers/src/tcpci.c b/zephyr/test/drivers/src/tcpci.c index 8e7edcf786..18a3341c27 100644 --- a/zephyr/test/drivers/src/tcpci.c +++ b/zephyr/test/drivers/src/tcpci.c @@ -91,9 +91,7 @@ ZTEST(tcpci, test_generic_tcpci_get_rx_message_raw_rev2) { const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL)); - tcpc_config[USBC_PORT_C0].flags = TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); - + /* Revision 2.0 is set by default in test_rules */ test_tcpci_get_rx_message_raw(emul, USBC_PORT_C0); } @@ -113,9 +111,7 @@ ZTEST(tcpci, test_generic_tcpci_transmit_rev2) { const struct emul *emul = emul_get_binding(DT_LABEL(EMUL_LABEL)); - tcpc_config[USBC_PORT_C0].flags = TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); - + /* Revision 2.0 is set by default in test_rules */ test_tcpci_transmit(emul, USBC_PORT_C0); } diff --git a/zephyr/test/drivers/src/tcpci_test_common.c b/zephyr/test/drivers/src/tcpci_test_common.c index 3bf3ff14c5..df2f14e3c4 100644 --- a/zephyr/test/drivers/src/tcpci_test_common.c +++ b/zephyr/test/drivers/src/tcpci_test_common.c @@ -45,9 +45,7 @@ void test_tcpci_init(const struct emul *emul, enum usbc_port port) struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul); uint16_t exp_mask; - tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0 & - TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); + tcpc_config[port].flags |= TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V; /* Test fail on power status read */ i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_POWER_STATUS); @@ -612,9 +610,6 @@ void test_tcpci_alert(const struct emul *emul, enum usbc_port port) const struct tcpm_drv *drv = tcpc_config[port].drv; struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul); - tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); - /* Test alert read fail */ i2c_common_emul_set_read_fail_reg(i2c_emul, TCPC_REG_ALERT); drv->tcpc_alert(port); @@ -664,8 +659,6 @@ void test_tcpci_alert_rx_message(const struct emul *emul, enum usbc_port port) int i, head; int size; - tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); tcpci_emul_set_reg(emul, TCPC_REG_DEV_CAP_2, TCPC_REG_DEV_CAP_2_LONG_MSG); tcpci_emul_set_reg(emul, TCPC_REG_RX_DETECT, @@ -832,10 +825,6 @@ void test_tcpci_drp_toggle(const struct emul *emul, enum usbc_port port) struct i2c_emul *i2c_emul = tcpci_emul_get_i2c_emul(emul); uint8_t exp_tcpc_ctrl, exp_role_ctrl, initial_tcpc_ctrl; - /* Set TCPCI to revision 2 */ - tcpc_config[port].flags = TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(emul, TCPCI_EMUL_REV2_0_VER1_1); - /* Test error on failed role CTRL set */ i2c_common_emul_set_write_fail_reg(i2c_emul, TCPC_REG_ROLE_CTRL); zassert_equal(EC_ERROR_INVAL, drv->drp_toggle(port), NULL); diff --git a/zephyr/test/drivers/src/test_rules.c b/zephyr/test/drivers/src/test_rules.c index 0266fa3cdf..d0595452c7 100644 --- a/zephyr/test/drivers/src/test_rules.c +++ b/zephyr/test/drivers/src/test_rules.c @@ -5,7 +5,10 @@ #include +#include "emul/tcpc/emul_tcpci.h" #include "motion_sense_fifo.h" +#include "test/drivers/stubs.h" +#include "usb_pd_tcpm.h" static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test, void *data) @@ -15,3 +18,23 @@ static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test, motion_sense_fifo_reset(); } ZTEST_RULE(motion_sense_fifo_reset, motion_sense_fifo_reset_before, NULL); + +static void tcpci_revision_reset_before(const struct ztest_unit_test *test, + void *data) +{ + ARG_UNUSED(test); + ARG_UNUSED(data); + const struct emul *tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + const struct emul *ps8xxx_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(ps8xxx_emul))); + + + /* Set TCPCI to revision 2 for both emulators */ + tcpc_config[USBC_PORT_C0].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); + + tcpc_config[USBC_PORT_C1].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(ps8xxx_emul, TCPCI_EMUL_REV2_0_VER1_1); +} +ZTEST_RULE(tcpci_revision_reset, tcpci_revision_reset_before, NULL); -- cgit v1.2.1 From 4aa148e556c2a413c89d7e33d14f451e82197813 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:52 -0600 Subject: chip/npcx/gpio-npcx5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8ed45542fdf2b40c0bf562fd38367ce9163cf087 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729392 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio-npcx5.c | 52 ++++++++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/chip/npcx/gpio-npcx5.c b/chip/npcx/gpio-npcx5.c index 6742f19369..e2f3bb0b60 100644 --- a/chip/npcx/gpio-npcx5.c +++ b/chip/npcx/gpio-npcx5.c @@ -48,11 +48,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); * the port, then call the master handler above. */ -#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ -static void _irq_func(void) \ -{ \ - gpio_interrupt(wui_int); \ -} +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } /* If we need to handle the other type interrupts except GPIO, add code here */ static void __gpio_wk0efgh_interrupt(void) @@ -60,7 +60,7 @@ static void __gpio_wk0efgh_interrupt(void) if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { /* Pending bit 7 or 6 or 5? */ if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { /* Disable host wake-up */ CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); /* Clear pending bit of WUI */ @@ -68,16 +68,18 @@ static void __gpio_wk0efgh_interrupt(void) return; } if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { espi_espirst_handler(); return; } } else { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { lpc_lreset_pltrst_handler(); return; } @@ -169,30 +171,30 @@ GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); #endif DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); #ifdef NPCX_SELECT_KSI_TO_GPIO -DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); #ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to * accommodate P3 CS interrupt. */ -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #else -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); #if defined(CHIP_FAMILY_NPCX7) -DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); #endif #undef GPIO_IRQ_FUNC -- cgit v1.2.1 From 5fc8ccb9e96e0163015442ae3da3082c084bdccb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:50 -0600 Subject: board/coral/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b7c92f64dc050842cbf39d5bfdae8249a9042a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728177 Reviewed-by: Jeremy Bettis --- board/coral/board.h | 59 ++++++++++++++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/board/coral/board.h b/board/coral/board.h index 4a1709e7a9..1b06a70772 100644 --- a/board/coral/board.h +++ b/board/coral/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages except Events: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_EVENTS)) +#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_EVENTS)) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -23,14 +23,14 @@ #define CONFIG_CMD_ACCEL_INFO #define CONFIG_CMD_BATT_MFG_ACCESS #define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define BD9995X_IOUT_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V + BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V #define CONFIG_CHARGER_PSYS_READ #define BD9995X_PSYS_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW + BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW #define CONFIG_CMD_I2C_STRESS_TEST #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL @@ -44,7 +44,7 @@ #define CONFIG_PORT80_HISTORY_LEN 256 /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_HW_PRESENT_CUSTOM #define CONFIG_BATTERY_LEVEL_NEAR_FULL 94 @@ -90,7 +90,7 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ +#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ #define CONFIG_USB_PD_TCPM_ANX3429 #define CONFIG_USB_PD_TCPM_PS8751 #define CONFIG_USB_PD_TCPM_TCPCI @@ -117,11 +117,11 @@ /* EC */ #define CONFIG_ADC #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_FPU /* Region sizes are not a power of 2 so we can't use MPU */ -#undef CONFIG_MPU +#undef CONFIG_MPU #define CONFIG_HOSTCMD_FLASH_SPI_INFO #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -150,7 +150,7 @@ #define CONFIG_WIRELESS #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER #define CONFIG_WLAN_POWER_ACTIVE_LOW -#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER +#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER #define CONFIG_PWR_STATE_DISCHARGE_FULL /* @@ -168,7 +168,7 @@ #define CONFIG_FLASH_SIZE_BYTES 524288 #define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ +#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ /* * Enable 1 slot of secure temporary storage to support @@ -178,19 +178,19 @@ #define CONFIG_VSTORE_SLOT_COUNT 1 /* Optional feature - used by nuvoton */ -#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ +#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ /* FIXME(dhendrix): these pins are just normal GPIOs on Coral. Do we need * to change some other setting to put them in GPIO mode? */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_GYRO NPCX_I2C_PORT1 -#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 -#define I2C_PORT_BATTERY NPCX_I2C_PORT3 -#define I2C_PORT_CHARGER NPCX_I2C_PORT3 +#define I2C_PORT_GYRO NPCX_I2C_PORT1 +#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 +#define I2C_PORT_BATTERY NPCX_I2C_PORT3 +#define I2C_PORT_CHARGER NPCX_I2C_PORT3 /* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_ACCEL I2C_PORT_GYRO /* Sensors */ #define CONFIG_MKBP_EVENT @@ -213,7 +213,6 @@ /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -221,11 +220,11 @@ /* ADC signal */ enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ - ADC_TEMP_SENSOR_AMB, /* ADC1 */ - ADC_BOARD_ID, /* ADC2 */ - ADC_BOARD_SKU_1, /* ADC3 */ - ADC_BOARD_SKU_0, /* ADC4 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ + ADC_TEMP_SENSOR_AMB, /* ADC1 */ + ADC_BOARD_ID, /* ADC2 */ + ADC_BOARD_SKU_1, /* ADC3 */ + ADC_BOARD_SKU_0, /* ADC4 */ ADC_CH_COUNT }; @@ -283,16 +282,16 @@ enum coral_board_version { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Reset PD MCU */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From 03b6e251bc1301a0aec6215331533a853d01ef4d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:06 -0600 Subject: board/cherry/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaeb831ff79f0e92293bfe557d17da1840453dd63 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728120 Reviewed-by: Jeremy Bettis --- board/cherry/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/cherry/led.c b/board/cherry/led.c index c177a1b48f..c1e3aaf7bc 100644 --- a/board/cherry/led.c +++ b/board/cherry/led.c @@ -10,28 +10,37 @@ #include "led_onoff_states.h" #include "pwm.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_S5] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_S5] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 38ea25002ecca449cc490500db1c995b3a99481c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:45 -0600 Subject: test/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc1d0c1b62bf99b07a2b500c4bd63457773ad422 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730538 Reviewed-by: Jeremy Bettis --- test/system.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/system.c b/test/system.c index 79383b82d9..75757f4237 100644 --- a/test/system.c +++ b/test/system.c @@ -13,8 +13,8 @@ #include "timer.h" #include "util.h" -#define TEST_STATE_STEP_2 (1 << 0) -#define TEST_STATE_FAIL (1 << 1) +#define TEST_STATE_STEP_2 (1 << 0) +#define TEST_STATE_FAIL (1 << 1) static int test_reboot_on_shutdown(void) { -- cgit v1.2.1 From 7ca38a899ba890e04cabe6d5fb61f6322dbc46b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:23 -0600 Subject: extra/lightbar/input.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I545833c2b5c8c25b0f34da5277375729c9836a43 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730180 Reviewed-by: Jeremy Bettis --- extra/lightbar/input.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/extra/lightbar/input.c b/extra/lightbar/input.c index e6c5485e39..48a97563a4 100644 --- a/extra/lightbar/input.c +++ b/extra/lightbar/input.c @@ -32,7 +32,7 @@ char *get_input(const char *prompt) return line; } -#else /* no readline */ +#else /* no readline */ char *get_input(const char *prompt) { -- cgit v1.2.1 From 5c4bb6743566d678c965228fce27dad057b446e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:59 -0600 Subject: zephyr/emul/tcpc/emul_tcpci_partner_src.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia459e46935e165da7ea559b0d8ac47258f7cfb24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730708 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci_partner_src.c | 59 ++++++++++++++----------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_src.c b/zephyr/emul/tcpc/emul_tcpci_partner_src.c index 8efc4327c8..00af0764c8 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_src.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_src.c @@ -35,11 +35,11 @@ static void tcpci_src_emul_start_source_capability_custom_time( * * @param data Pointer to USB-C source device emulator data */ -static void tcpci_src_emul_start_source_capability_timer( - struct tcpci_src_emul_data *data) +static void +tcpci_src_emul_start_source_capability_timer(struct tcpci_src_emul_data *data) { tcpci_src_emul_start_source_capability_custom_time( - data, TCPCI_SOURCE_CAPABILITY_TIMEOUT); + data, TCPCI_SOURCE_CAPABILITY_TIMEOUT); } /** @@ -47,8 +47,8 @@ static void tcpci_src_emul_start_source_capability_timer( * * @param data Pointer to USB-C source device emulator data */ -static void tcpci_src_emul_stop_source_capability_timer( - struct tcpci_src_emul_data *data) +static void +tcpci_src_emul_stop_source_capability_timer(struct tcpci_src_emul_data *data) { k_work_cancel_delayable(&data->source_capability_timeout); } @@ -66,21 +66,19 @@ int tcpci_src_emul_send_capability_msg(struct tcpci_src_emul_data *data, } } - return tcpci_partner_send_data_msg(common_data, - PD_DATA_SOURCE_CAP, + return tcpci_partner_send_data_msg(common_data, PD_DATA_SOURCE_CAP, data->pdo, pdos, delay); } int tcpci_src_emul_send_capability_msg_with_timer( struct tcpci_src_emul_data *data, - struct tcpci_partner_data *common_data, - uint64_t delay) + struct tcpci_partner_data *common_data, uint64_t delay) { int ret; if (delay > 0) { tcpci_src_emul_start_source_capability_custom_time( - data, K_MSEC(delay)); + data, K_MSEC(delay)); return TCPCI_EMUL_TX_SUCCESS; } @@ -119,10 +117,10 @@ void tcpci_src_emul_clear_status_received(struct tcpci_src_emul_data *data) * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled */ -static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data, - const struct tcpci_emul_msg *msg) +static enum tcpci_partner_handler_res +tcpci_src_emul_handle_sop_msg(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data, + const struct tcpci_emul_msg *msg) { struct tcpci_src_emul_data *data = CONTAINER_OF(ext, struct tcpci_src_emul_data, ext); @@ -171,9 +169,8 @@ static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg( return TCPCI_PARTNER_COMMON_MSG_HANDLED; case PD_CTRL_GET_REVISION: rmdo = 0x31000000; - tcpci_partner_send_data_msg(common_data, - PD_DATA_REVISION, - &rmdo, 1, 0); + tcpci_partner_send_data_msg( + common_data, PD_DATA_REVISION, &rmdo, 1, 0); return TCPCI_PARTNER_COMMON_MSG_HANDLED; default: return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; @@ -189,9 +186,8 @@ static enum tcpci_partner_handler_res tcpci_src_emul_handle_sop_msg( static void tcpci_src_emul_source_capability_timeout(struct k_work *work) { struct k_work_delayable *dwork = k_work_delayable_from_work(work); - struct tcpci_src_emul_data *data = - CONTAINER_OF(dwork, struct tcpci_src_emul_data, - source_capability_timeout); + struct tcpci_src_emul_data *data = CONTAINER_OF( + dwork, struct tcpci_src_emul_data, source_capability_timeout); struct tcpci_partner_data *common_data = data->common_data; if (k_mutex_lock(&common_data->transmit_mutex, K_NO_WAIT) != 0) { @@ -278,9 +274,9 @@ static void tcpci_src_emul_disconnect(struct tcpci_partner_extension *ext, * @return 0 on success * @return negative on TCPCI connect error */ -static int tcpci_src_emul_connect_to_tcpci( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data) +static int +tcpci_src_emul_connect_to_tcpci(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data) { struct tcpci_src_emul_data *data = CONTAINER_OF(ext, struct tcpci_src_emul_data, ext); @@ -298,15 +294,14 @@ static int tcpci_src_emul_connect_to_tcpci( * capabilities, but it is permit. Timeout is obligatory for power swap. */ tcpci_src_emul_send_capability_msg_with_timer( - data, common_data, - TCPCI_SWAP_SOURCE_START_TIMEOUT_MS); + data, common_data, TCPCI_SWAP_SOURCE_START_TIMEOUT_MS); return 0; } -#define PDO_FIXED_FLAGS_MASK \ - (PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED | \ - PDO_FIXED_COMM_CAP | PDO_FIXED_DATA_SWAP) +#define PDO_FIXED_FLAGS_MASK \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_UNCONSTRAINED | PDO_FIXED_COMM_CAP | \ + PDO_FIXED_DATA_SWAP) enum check_pdos_res tcpci_src_emul_check_pdos(struct tcpci_src_emul_data *data) { @@ -411,10 +406,10 @@ struct tcpci_partner_extension_ops tcpci_src_emul_ops = { .connect = tcpci_src_emul_connect_to_tcpci, }; -struct tcpci_partner_extension *tcpci_src_emul_init( - struct tcpci_src_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext) +struct tcpci_partner_extension * +tcpci_src_emul_init(struct tcpci_src_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext) { struct tcpci_partner_extension *src_ext = &data->ext; -- cgit v1.2.1 From 02035702555b6f657e83b7f06b91a630cc950841 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:54 -0600 Subject: baseboard/goroh/board_id.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I804480328bc4cead8a6a1736630886828c3154b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727512 Reviewed-by: Jeremy Bettis --- baseboard/goroh/board_id.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/baseboard/goroh/board_id.c b/baseboard/goroh/board_id.c index fd2001d8a3..b1184572f9 100644 --- a/baseboard/goroh/board_id.c +++ b/baseboard/goroh/board_id.c @@ -34,21 +34,8 @@ * 14 | 47 | 680 | 3086.7 */ const static int voltage_map[] = { - 136, - 388, - 584, - 785, - 993, - 1220, - 1432, - 1650, - 1875, - 2084, - 2273, - 2461, - 2672, - 2888, - 3086, + 136, 388, 584, 785, 993, 1220, 1432, 1650, + 1875, 2084, 2273, 2461, 2672, 2888, 3086, }; const int threshold_mv = 100; -- cgit v1.2.1 From b3b604a1c4c6fd5e8952fbc08739f086388fb683 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:07 -0600 Subject: baseboard/trogdor/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b50c913ed47458e257aefcad9b0b377cacbd887 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727945 Reviewed-by: Jeremy Bettis --- baseboard/trogdor/usb_pd_policy.c | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/baseboard/trogdor/usb_pd_policy.c b/baseboard/trogdor/usb_pd_policy.c index 56ca4514d5..a4f2b31f33 100644 --- a/baseboard/trogdor/usb_pd_policy.c +++ b/baseboard/trogdor/usb_pd_policy.c @@ -12,8 +12,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -233,8 +230,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv IRQ. HPD->1", port); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; @@ -242,8 +239,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) CPRINTS("C%d: Recv lvl. HPD->%d", port, lvl); gpio_set_level(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -259,7 +256,7 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); CPRINTS("C%d: DP exit. HPD->0", port); gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); } -- cgit v1.2.1 From f209c9e03d9d68ed1c3db3848de8b45f446d4d4e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:33 -0600 Subject: chip/mchp/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8442d71daacb71b98093e93a4399f644335045b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729314 Reviewed-by: Jeremy Bettis --- chip/mchp/watchdog.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/chip/mchp/watchdog.c b/chip/mchp/watchdog.c index b8f986f5cd..91fc9f8029 100644 --- a/chip/mchp/watchdog.c +++ b/chip/mchp/watchdog.c @@ -43,11 +43,10 @@ static void wdg_intr_enable(int enable) #else static void wdg_intr_enable(int enable) { - (void) enable; + (void)enable; } #endif - /* * MEC1701 WDG asserts chip reset on LOAD count expiration. * WDG interrupt is simulated using a 16-bit general purpose @@ -81,8 +80,8 @@ int watchdog_init(void) MCHP_TMR16_CTL(0) |= BIT(0); /* Prescaler = 48000 -> 1kHz -> Period = 1 ms */ - MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU) - | (47999 << 16); + MCHP_TMR16_CTL(0) = (MCHP_TMR16_CTL(0) & 0xffffU) | + (47999 << 16); /* No auto restart */ MCHP_TMR16_CTL(0) &= ~BIT(3); @@ -116,8 +115,8 @@ int watchdog_init(void) * counting if a debug cable is attached to JTAG_RST#. */ if (IS_ENABLED(CONFIG_CHIPSET_DEBUG)) - MCHP_WDG_CTL |= (MCHP_WDT_CTL_ENABLE - | MCHP_WDT_CTL_JTAG_STALL_EN); + MCHP_WDG_CTL |= + (MCHP_WDT_CTL_ENABLE | MCHP_WDT_CTL_JTAG_STALL_EN); else MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE; @@ -142,32 +141,29 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) MCHP_WDG_CTL = 0; /* clear enable to allow write to load register */ MCHP_WDG_LOAD = 2; MCHP_WDG_CTL |= MCHP_WDT_CTL_ENABLE; - } /* ISR for watchdog warning naked will keep SP & LR */ -void -IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked)); +void IRQ_HANDLER(MCHP_IRQ_WDG)(void) __keep __attribute__((naked)); void IRQ_HANDLER(MCHP_IRQ_WDG)(void) { /* Naked call so we can extract raw LR and SP */ asm volatile("mov r0, lr\n" - "mov r1, sp\n" - /* - * Must push registers in pairs to keep 64-bit aligned - * stack for ARM EABI. This also conveniently saves - * R0=LR so we can pass it to task_resched_if_needed. - */ - "push {r0, lr}\n" - "bl watchdog_check\n" - "pop {r0, lr}\n" - "b task_resched_if_needed\n"); + "mov r1, sp\n" + /* + * Must push registers in pairs to keep 64-bit aligned + * stack for ARM EABI. This also conveniently saves + * R0=LR so we can pass it to task_resched_if_needed. + */ + "push {r0, lr}\n" + "bl watchdog_check\n" + "pop {r0, lr}\n" + "b task_resched_if_needed\n"); } /* put the watchdog at the highest priority */ const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_WDG) -__attribute__((section(".rodata.irqprio"))) -= {MCHP_IRQ_WDG, 0}; + __attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_WDG, 0 }; #else /* @@ -185,8 +181,7 @@ void __keep watchdog_check(uint32_t excep_lr, uint32_t excep_sp) watchdog_trace(excep_lr, excep_sp); } -void -IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked)); +void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) __keep __attribute__((naked)); void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) { /* Naked call so we can extract raw LR and SP */ @@ -205,8 +200,7 @@ void IRQ_HANDLER(MCHP_IRQ_TIMER16_0)(void) /* Put the watchdog at the highest interrupt priority. */ const struct irq_priority __keep IRQ_PRIORITY(MCHP_IRQ_TIMER16_0) - __attribute__((section(".rodata.irqprio"))) - = {MCHP_IRQ_TIMER16_0, 0}; + __attribute__((section(".rodata.irqprio"))) = { MCHP_IRQ_TIMER16_0, 0 }; #endif /* #ifdef CONFIG_WATCHDOG_HELP */ #endif /* #if defined(CHIP_FAMILY_MEC152X) || defined(CHIP_FAMILY_MEC172X) */ -- cgit v1.2.1 From 2435abfd50afff99b44c17381bbac7f9496495d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:30 -0600 Subject: board/twinkie/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52c986ce2d6756a1524f331db6906e7bec703e49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729048 Reviewed-by: Jeremy Bettis --- board/twinkie/usb_pd_config.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/board/twinkie/usb_pd_config.h b/board/twinkie/usb_pd_config.h index 1c20a9df77..17512c95c6 100644 --- a/board/twinkie/usb_pd_config.h +++ b/board/twinkie/usb_pd_config.h @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define DMAC_TIM_RX(p) STM32_DMAC_CH2 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) (BIT(21) | BIT(22)) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -102,11 +102,11 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* TX_DATA on PB4 is an output low GPIO to disable the FET */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*4))) - | (1 << (2*4)); + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4)); /* TX_DATA on PA6 is an output low GPIO to disable the FET */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2*6))) - | (1 << (2*6)); + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6)); /* * Tri-state the low side after the high side * to ensure we are not going above Vnc @@ -119,11 +119,12 @@ static inline void pd_tx_disable(int port, int polarity) static inline void pd_select_polarity(int port, int polarity) { /* use the right comparator */ - STM32_COMP_CSR = (STM32_COMP_CSR - & ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK - |STM32_COMP_CMP1EN | STM32_COMP_CMP2EN)) - | STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4 - | (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN); + STM32_COMP_CSR = + (STM32_COMP_CSR & + ~(STM32_COMP_CMP1INSEL_MASK | STM32_COMP_CMP2INSEL_MASK | + STM32_COMP_CMP1EN | STM32_COMP_CMP2EN)) | + STM32_COMP_CMP1INSEL_INM4 | STM32_COMP_CMP2INSEL_INM4 | + (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN); } /* Initialize pins used for clocking */ -- cgit v1.2.1 From 02f01fb049f93a5856917b282dad2c7c0a1cda58 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:29 -0600 Subject: board/primus/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I69007158c484fd90aff2e7d6026c57e176674825 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727759 Reviewed-by: Jeremy Bettis --- board/primus/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/primus/fans.c b/board/primus/fans.c index 001c6fde5c..79eed79630 100644 --- a/board/primus/fans.c +++ b/board/primus/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From f3958103f4f71186920c5fe5dbd68d1c85a56543 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:23 -0600 Subject: driver/led/lm3630a.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf491c3fa8082aa4bc84bab1a03bd895fce87358 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729998 Reviewed-by: Jeremy Bettis --- driver/led/lm3630a.h | 88 ++++++++++++++++++++++++++-------------------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/driver/led/lm3630a.h b/driver/led/lm3630a.h index d43304b66e..9c9cdaf442 100644 --- a/driver/led/lm3630a.h +++ b/driver/led/lm3630a.h @@ -8,56 +8,56 @@ #ifndef __CROS_EC_LM3630A_H #define __CROS_EC_LM3630A_H -#define LM3630A_REG_CONTROL 0x00 -#define LM3630A_REG_CONFIG 0x01 -#define LM3630A_REG_BOOST_CONTROL 0x02 -#define LM3630A_REG_A_BRIGHTNESS 0x03 -#define LM3630A_REG_B_BRIGHTNESS 0x04 -#define LM3630A_REG_A_CURRENT 0x05 -#define LM3630A_REG_B_CURRENT 0x06 -#define LM3630A_REG_ONOFF_RAMP 0x07 -#define LM3630A_REG_RUN_RAMP 0x08 -#define LM3630A_REG_INT_STATUS 0x09 -#define LM3630A_REG_INT_ENABLE 0x0a -#define LM3630A_REG_FAULT_STATUS 0x0b -#define LM3630A_REG_SW_RESET 0x0f -#define LM3630A_REG_PWM_OUT_LOW 0x12 -#define LM3630A_REG_PWM_OUT_HIGH 0x13 -#define LM3630A_REG_REVISION 0x1f -#define LM3630A_REG_FILTER_STRENGTH 0x50 +#define LM3630A_REG_CONTROL 0x00 +#define LM3630A_REG_CONFIG 0x01 +#define LM3630A_REG_BOOST_CONTROL 0x02 +#define LM3630A_REG_A_BRIGHTNESS 0x03 +#define LM3630A_REG_B_BRIGHTNESS 0x04 +#define LM3630A_REG_A_CURRENT 0x05 +#define LM3630A_REG_B_CURRENT 0x06 +#define LM3630A_REG_ONOFF_RAMP 0x07 +#define LM3630A_REG_RUN_RAMP 0x08 +#define LM3630A_REG_INT_STATUS 0x09 +#define LM3630A_REG_INT_ENABLE 0x0a +#define LM3630A_REG_FAULT_STATUS 0x0b +#define LM3630A_REG_SW_RESET 0x0f +#define LM3630A_REG_PWM_OUT_LOW 0x12 +#define LM3630A_REG_PWM_OUT_HIGH 0x13 +#define LM3630A_REG_REVISION 0x1f +#define LM3630A_REG_FILTER_STRENGTH 0x50 /* Control register bits */ -#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7) -#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6) -#define LM3630A_CTRL_BIT_LINEAR_A BIT(4) -#define LM3630A_CTRL_BIT_LINEAR_B BIT(3) -#define LM3630A_CTRL_BIT_LED_EN_A BIT(2) -#define LM3630A_CTRL_BIT_LED_EN_B BIT(1) -#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0) +#define LM3630A_CTRL_BIT_SLEEP_CMD BIT(7) +#define LM3630A_CTRL_BIT_SLEEP_STAT BIT(6) +#define LM3630A_CTRL_BIT_LINEAR_A BIT(4) +#define LM3630A_CTRL_BIT_LINEAR_B BIT(3) +#define LM3630A_CTRL_BIT_LED_EN_A BIT(2) +#define LM3630A_CTRL_BIT_LED_EN_B BIT(1) +#define LM3630A_CTRL_BIT_LED2_ON_A BIT(0) /* Config register bits */ -#define LM3630A_CFG_BIT_FB_EN_B BIT(4) -#define LM3630A_CFG_BIT_FB_EN_A BIT(3) -#define LM3630A_CFG_BIT_PWM_LOW BIT(2) -#define LM3630A_CFG_BIT_PWM_EN_B BIT(1) -#define LM3630A_CFG_BIT_PWM_EN_A BIT(0) +#define LM3630A_CFG_BIT_FB_EN_B BIT(4) +#define LM3630A_CFG_BIT_FB_EN_A BIT(3) +#define LM3630A_CFG_BIT_PWM_LOW BIT(2) +#define LM3630A_CFG_BIT_PWM_EN_B BIT(1) +#define LM3630A_CFG_BIT_PWM_EN_A BIT(0) /* Boost control register bits */ -#define LM3630A_BOOST_OVP_16V (0 << 5) -#define LM3630A_BOOST_OVP_24V BIT(5) -#define LM3630A_BOOST_OVP_32V (2 << 5) -#define LM3630A_BOOST_OVP_40V (3 << 5) -#define LM3630A_BOOST_OCP_600MA (0 << 3) -#define LM3630A_BOOST_OCP_800MA BIT(3) -#define LM3630A_BOOST_OCP_1000MA (2 << 3) -#define LM3630A_BOOST_OCP_1200MA (3 << 3) -#define LM3630A_BOOST_SLOW_START BIT(2) -#define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */ -#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */ -#define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */ -#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */ -#define LM3630A_FMODE_500KHZ (0 << 0) -#define LM3630A_FMODE_1000KHZ BIT(0) +#define LM3630A_BOOST_OVP_16V (0 << 5) +#define LM3630A_BOOST_OVP_24V BIT(5) +#define LM3630A_BOOST_OVP_32V (2 << 5) +#define LM3630A_BOOST_OVP_40V (3 << 5) +#define LM3630A_BOOST_OCP_600MA (0 << 3) +#define LM3630A_BOOST_OCP_800MA BIT(3) +#define LM3630A_BOOST_OCP_1000MA (2 << 3) +#define LM3630A_BOOST_OCP_1200MA (3 << 3) +#define LM3630A_BOOST_SLOW_START BIT(2) +#define LM3630A_SHIFT_500KHZ (0 << 1) /* FMODE=0 */ +#define LM3630A_SHIFT_560KHZ BIT(1) /* FMODE=0 */ +#define LM3630A_SHIFT_1000KHZ (0 << 1) /* FMODE=1 */ +#define LM3630A_SHIFT_1120KHZ BIT(1) /* FMODE=1 */ +#define LM3630A_FMODE_500KHZ (0 << 0) +#define LM3630A_FMODE_1000KHZ BIT(0) /* Power on and initialize LM3630A. */ int lm3630a_poweron(void); -- cgit v1.2.1 From f82aa91293cd2b51b0ce4252f75727f45706108e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:06 -0600 Subject: zephyr/shim/include/zephyr_adc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b67566d3e8993412dab9f399291f4eee24b6dd3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730845 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_adc.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/include/zephyr_adc.h b/zephyr/shim/include/zephyr_adc.h index aff6d7a5b6..5ceca5725e 100644 --- a/zephyr/shim/include/zephyr_adc.h +++ b/zephyr/shim/include/zephyr_adc.h @@ -11,13 +11,13 @@ #ifdef CONFIG_PLATFORM_EC_ADC #define ZSHIM_ADC_ID(node_id) DT_STRING_UPPER_TOKEN(node_id, enum_name) -#define ADC_ID_WITH_COMMA(node_id) ZSHIM_ADC_ID(node_id), +#define ADC_ID_WITH_COMMA(node_id) ZSHIM_ADC_ID(node_id), enum adc_channel { #if DT_NODE_EXISTS(DT_INST(0, named_adc_channels)) DT_FOREACH_CHILD(DT_INST(0, named_adc_channels), ADC_ID_WITH_COMMA) #endif /* named_adc_channels */ - ADC_CH_COUNT + ADC_CH_COUNT }; #undef ADC_ID_WITH_COMMA @@ -38,9 +38,7 @@ extern struct adc_t adc_channels[]; #endif /* CONFIG_ADC_CHANNELS_RUNTIME_CONFIG */ #else /* Empty declaration to avoid warnings if adc.h is included */ -enum adc_channel { - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_COUNT }; #endif /* CONFIG_PLATFORM_EC_ADC */ #endif /* __CROS_EC_ZEPHYR_ADC_H */ -- cgit v1.2.1 From bf2c03084e0db45178070283959334cf9e68e914 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:40 -0600 Subject: zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3d16dcc47681995c1257d8b821c1fb838e9554e0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730822 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c index c5ffd40fb5..8b135f66cc 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c +++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.c @@ -54,7 +54,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -81,7 +81,7 @@ void sspi_flash_wait_ready(void) sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ @@ -113,7 +113,7 @@ void sspi_flash_set_address(uint32_t dest_addr) } void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down. */ @@ -202,7 +202,7 @@ void sspi_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { + offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { /* Enable write */ sspi_flash_write_enable(); /* Set erase address */ @@ -226,7 +226,7 @@ int sspi_flash_verify(int offset, int size, const char *data) uint8_t cmp_data; ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; + ptr_mram = (uint8_t *)data; result = 1; /* Disable tri-state */ @@ -260,12 +260,11 @@ int sspi_flash_get_image_used(const char *fw_base) for (size--; size > 0 && image[size] != 0xea; size--) ; - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ } /* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) +uint32_t __attribute__((section(".startup_text"))) sspi_flash_upload(int spi_offset, int spi_size) { /* @@ -320,7 +319,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* Start to write */ if (image_base != NULL) sspi_flash_physical_write(spi_offset, sz_image, - image_base); + image_base); /* Verify data */ if (sspi_flash_verify(spi_offset, sz_image, image_base)) *flag_upload |= 0x02; -- cgit v1.2.1 From 7fc9de186573fd7160ea2d21fcb6b6753813a80c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:57 -0600 Subject: common/util_stdlib.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie66a610cb3a35082b8e819715c9a48f048eb496f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729804 Reviewed-by: Jeremy Bettis --- common/util_stdlib.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/common/util_stdlib.c b/common/util_stdlib.c index 7e59b0fbc5..04394feead 100644 --- a/common/util_stdlib.c +++ b/common/util_stdlib.c @@ -134,8 +134,7 @@ __stdlib_compat int atoi(const char *nptr) return neg ? -result : result; } -__keep -__stdlib_compat int memcmp(const void *s1, const void *s2, size_t len) +__keep __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len) { const char *sa = s1; const char *sb = s2; @@ -151,17 +150,16 @@ __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len) } #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep -__stdlib_compat void *memcpy(void *dest, const void *src, size_t len) +__keep __stdlib_compat void *memcpy(void *dest, const void *src, size_t len) { char *d = (char *)dest; const char *s = (const char *)src; uint32_t *dw; const uint32_t *sw; char *head; - char * const tail = (char *)dest + len; + char *const tail = (char *)dest + len; /* Set 'body' to the last word boundary */ - uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3); + uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { /* Misaligned. no body, no tail. */ @@ -197,18 +195,17 @@ __stdlib_compat void *memcpy(void *dest, const void *src, size_t len) #endif /* address_sanitizer || memory_sanitizer */ #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep -__stdlib_compat __visible void *memset(void *dest, int c, size_t len) +__keep __stdlib_compat __visible void *memset(void *dest, int c, size_t len) { char *d = (char *)dest; uint32_t cccc; uint32_t *dw; char *head; - char * const tail = (char *)dest + len; + char *const tail = (char *)dest + len; /* Set 'body' to the last word boundary */ - uint32_t * const body = (uint32_t *)((uintptr_t)tail & ~3); + uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); - c &= 0xff; /* Clear upper bits before ORing below */ + c &= 0xff; /* Clear upper bits before ORing below */ cccc = c | (c << 8) | (c << 16) | (c << 24); if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3)) @@ -237,8 +234,7 @@ __stdlib_compat __visible void *memset(void *dest, int c, size_t len) #endif /* address_sanitizer || memory_sanitizer */ #if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep -__stdlib_compat void *memmove(void *dest, const void *src, size_t len) +__keep __stdlib_compat void *memmove(void *dest, const void *src, size_t len) { if ((uintptr_t)dest <= (uintptr_t)src || (uintptr_t)dest >= (uintptr_t)src + len) { @@ -253,9 +249,9 @@ __stdlib_compat void *memmove(void *dest, const void *src, size_t len) uint32_t *dw; const uint32_t *sw; char *head; - char * const tail = (char *)dest; + char *const tail = (char *)dest; /* Set 'body' to the last word boundary */ - uint32_t * const body = (uint32_t *)(((uintptr_t)tail+3) & ~3); + uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3); if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { /* Misaligned. no body, no tail. */ @@ -326,7 +322,6 @@ __stdlib_compat int strncmp(const char *s1, const char *s2, size_t n) break; s1++; s2++; - } return 0; } -- cgit v1.2.1 From a628b862104684077862e50fc8e168ea27cdca24 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:45 -0600 Subject: board/ghost/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2c7992be537af13edeacdc0e4a197c0aba0244a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728405 Reviewed-by: Jeremy Bettis --- board/ghost/fw_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/ghost/fw_config.h b/board/ghost/fw_config.h index df2ceae238..436f616eb1 100644 --- a/board/ghost/fw_config.h +++ b/board/ghost/fw_config.h @@ -23,12 +23,12 @@ enum ec_cfg_keyboard_backlight_type { union ghost_cbi_fw_config { struct { - uint32_t reserved_1 : 4; - uint32_t sd_db : 2; - uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_2 : 21; + uint32_t reserved_1 : 4; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_2 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From 8360c76e984fb04a5f52975546d9705955c17e89 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:29 -0600 Subject: driver/usb_mux/it5205.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5788251edab9deea64436515e99db91da0f88aea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730162 Reviewed-by: Jeremy Bettis --- driver/usb_mux/it5205.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/driver/usb_mux/it5205.h b/driver/usb_mux/it5205.h index 0fb9f009f6..46094d2bf8 100644 --- a/driver/usb_mux/it5205.h +++ b/driver/usb_mux/it5205.h @@ -19,18 +19,17 @@ #define IT5205_REG_CHIP_ID0 0x7 /* MUX power down register */ -#define IT5205_REG_MUXPDR 0x10 -#define IT5205_MUX_POWER_DOWN BIT(0) +#define IT5205_REG_MUXPDR 0x10 +#define IT5205_MUX_POWER_DOWN BIT(0) /* MUX control register */ -#define IT5205_REG_MUXCR 0x11 +#define IT5205_REG_MUXCR 0x11 #define IT5205_POLARITY_INVERTED BIT(4) -#define IT5205_DP_USB_CTRL_MASK 0x0f -#define IT5205_DP 0x0f -#define IT5205_DP_USB 0x03 -#define IT5205_USB 0x07 - +#define IT5205_DP_USB_CTRL_MASK 0x0f +#define IT5205_DP 0x0f +#define IT5205_DP_USB 0x03 +#define IT5205_USB 0x07 /* IT5205-H SBU module */ @@ -38,27 +37,27 @@ #define IT5205H_SBU_I2C_ADDR_FLAGS 0x6a /* Vref Select Register */ -#define IT5205H_REG_VSR 0x10 -#define IT5205H_VREF_SELECT_MASK 0x30 -#define IT5205H_VREF_SELECT_3_3V 0x00 -#define IT5205H_VREF_SELECT_OFF 0x20 +#define IT5205H_REG_VSR 0x10 +#define IT5205H_VREF_SELECT_MASK 0x30 +#define IT5205H_VREF_SELECT_3_3V 0x00 +#define IT5205H_VREF_SELECT_OFF 0x20 /* CSBU OVP Select Register */ -#define IT5205H_REG_CSBUOVPSR 0x1e -#define IT5205H_OVP_SELECT_MASK 0x30 -#define IT5205H_OVP_3_90V 0x00 -#define IT5205H_OVP_3_68V 0x10 -#define IT5205H_OVP_3_62V 0x20 -#define IT5205H_OVP_3_57V 0x30 +#define IT5205H_REG_CSBUOVPSR 0x1e +#define IT5205H_OVP_SELECT_MASK 0x30 +#define IT5205H_OVP_3_90V 0x00 +#define IT5205H_OVP_3_68V 0x10 +#define IT5205H_OVP_3_62V 0x20 +#define IT5205H_OVP_3_57V 0x30 /* CSBU Switch Register */ -#define IT5205H_REG_CSBUSR 0x22 -#define IT5205H_CSBUSR_SWITCH BIT(0) +#define IT5205H_REG_CSBUSR 0x22 +#define IT5205H_CSBUSR_SWITCH BIT(0) /* Interrupt Switch Register */ -#define IT5205H_REG_ISR 0x25 -#define IT5205H_ISR_CSBU_MASK BIT(4) -#define IT5205H_ISR_CSBU_OVP BIT(0) +#define IT5205H_REG_ISR 0x25 +#define IT5205H_ISR_CSBU_MASK BIT(4) +#define IT5205H_ISR_CSBU_OVP BIT(0) enum ec_error_list it5205h_enable_csbu_switch(const struct usb_mux *me, bool en); -- cgit v1.2.1 From 1b3f2d8818e0e4432d8af94ecce446309f068d58 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:22 -0600 Subject: util/uut/cmd.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6976de7c00ea95e8ec8ea45cbbc818799340238e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730659 Reviewed-by: Jeremy Bettis --- util/uut/cmd.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/util/uut/cmd.h b/util/uut/cmd.h index 44cebbe989..2ca1e825c7 100644 --- a/util/uut/cmd.h +++ b/util/uut/cmd.h @@ -18,17 +18,17 @@ #define MAX_RESP_BUF_SIZE 512 enum uart_protocol_cmd { - UFPP_H2D_SYNC_CMD = 0x55, /* Single-Byte Host to Device */ - /* synchronization command */ - UFPP_D2H_SYNC_CMD = 0x5A, /* Single-Byte Device to Host */ - /* synchronization response */ - UFPP_WRITE_CMD = 0x07, /* Write command and response */ - UFPP_READ_CMD = 0x1C, /* Read command and response */ - UFPP_READ_CRC_CMD = 0x89, /* Read CRC command and response */ - UFPP_FCALL_CMD = 0x70, /* Call function command */ + UFPP_H2D_SYNC_CMD = 0x55, /* Single-Byte Host to Device */ + /* synchronization command */ + UFPP_D2H_SYNC_CMD = 0x5A, /* Single-Byte Device to Host */ + /* synchronization response */ + UFPP_WRITE_CMD = 0x07, /* Write command and response */ + UFPP_READ_CMD = 0x1C, /* Read command and response */ + UFPP_READ_CRC_CMD = 0x89, /* Read CRC command and response */ + UFPP_FCALL_CMD = 0x70, /* Call function command */ UFPP_FCALL_RSLT_CMD = 0x73, /* Call function response */ - UFPP_SPI_CMD = 0x92, /* SPI specific command */ - UFPP_ERROR_CMD = 0xFF /* Error response */ + UFPP_SPI_CMD = 0x92, /* SPI specific command */ + UFPP_ERROR_CMD = 0xFF /* Error response */ }; struct command_node { @@ -44,22 +44,22 @@ struct command_node { void cmd_create_sync(uint8_t *cmd_info, uint32_t *cmd_len); void cmd_create_write(uint32_t addr, uint32_t size, uint8_t *data_buf, - uint8_t *cmd_info, uint32_t *cmd_len); + uint8_t *cmd_info, uint32_t *cmd_len); void cmd_create_read(uint32_t addr, uint8_t size, uint8_t *cmd_info, - uint32_t *cmd_len); + uint32_t *cmd_len); void cmd_create_exec(uint32_t addr, uint8_t *cmd_info, uint32_t *cmd_len); void cmd_build_sync(struct command_node *cmd_buf, uint32_t *cmd_num); void cmd_build_exec_exit(uint32_t addr, struct command_node *cmd_buf, - uint32_t *cmd_num); + uint32_t *cmd_num); void cmd_build_exec_ret(uint32_t addr, struct command_node *cmd_buf, - uint32_t *cmd_num); + uint32_t *cmd_num); bool cmd_disp_sync(uint8_t *resp_buf); bool cmd_disp_write(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num, - uint32_t total_size); + uint32_t total_size); bool cmd_disp_read(uint8_t *resp_buf, uint32_t resp_size, uint32_t resp_num, - uint32_t total_size); + uint32_t total_size); void cmd_disp_data(uint8_t *resp_buf, uint32_t resp_size); void cmd_disp_flash_erase_dev(uint8_t *resp_buf, uint32_t dev_num); void cmd_disp_flash_erase_sect(uint8_t *resp_buf, uint32_t dev_num); -- cgit v1.2.1 From 1710769e2abf3548f2bf11f414f7329ebebe12a2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:34 -0600 Subject: driver/ppc/ktu1125.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I206fa57d33e81b2cc51d3bc0f8283fd5973c48c8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730033 Reviewed-by: Jeremy Bettis --- driver/ppc/ktu1125.c | 97 ++++++++++++++++++++++------------------------------ 1 file changed, 41 insertions(+), 56 deletions(-) diff --git a/driver/ppc/ktu1125.c b/driver/ppc/ktu1125.c index 9c01cfa358..aebb3ad86b 100644 --- a/driver/ppc/ktu1125.c +++ b/driver/ppc/ktu1125.c @@ -18,25 +18,21 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int set_flags(const int port, const int addr, const int flags_to_set) @@ -80,7 +76,6 @@ static int set_field(const int port, const int addr, const int shift, return set_flags(port, addr, val); } - #ifdef CONFIG_CMD_PPC_DUMP static int ktu1125_dump(int port) { @@ -102,15 +97,14 @@ static int ktu1125_dump(int port) static int ktu1125_power_path_control(int port, int enable) { int status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_SW_AB_EN) - : clr_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_SW_AB_EN | - KTU1125_CC1S_VCONN | - KTU1125_CC2S_VCONN); + KTU1125_SW_AB_EN) : + clr_flags(port, KTU1125_CTRL_SW_CFG, + KTU1125_SW_AB_EN | KTU1125_CC1S_VCONN | + KTU1125_CC2S_VCONN); if (status) { - CPRINTS("ppc p%d: Failed to %s power path", - port, enable ? "enable" : "disable"); + CPRINTS("ppc p%d: Failed to %s power path", port, + enable ? "enable" : "disable"); } return status; @@ -138,7 +132,6 @@ static int ktu1125_init(int port) return regval; } - /* * Setting control register CTRL_SW_CFG */ @@ -230,7 +223,7 @@ static int ktu1125_init(int port) */ /* Leave SYSA_OK and FRS masked for SNK group of interrupts */ - regval = KTU1125_SNK_MASK_ALL & (KTU1125_SYSA_OK | KTU1125_FR_SWAP); + regval = KTU1125_SNK_MASK_ALL & (KTU1125_SYSA_OK | KTU1125_FR_SWAP); status = write_reg(port, KTU1125_INTMASK_SNK, regval); if (status) { ppc_err_prints("Failed to write INTMASK_SNK!", port, status); @@ -291,8 +284,7 @@ static int ktu1125_set_polarity(int port, int polarity) if (polarity) { /* CC2 active. */ clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_CC2S_VCONN); - return set_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_CC1S_VCONN); + return set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_CC1S_VCONN); } /* else CC1 active. */ @@ -326,9 +318,8 @@ static int ktu1125_set_vbus_src_current_limit(int port, enum tcpc_rp_value rp) break; }; - status = set_field(port, KTU1125_SET_SW_CFG, KTU1125_SYSB_CLP_SHIFT, - KTU1125_SYSB_CLP_LEN, regval); + KTU1125_SYSB_CLP_LEN, regval); if (status) ppc_prints("Failed to set KTU1125_SET_SW_CFG!", port); @@ -338,13 +329,13 @@ static int ktu1125_set_vbus_src_current_limit(int port, enum tcpc_rp_value rp) static int ktu1125_discharge_vbus(int port, int enable) { int status = enable ? set_flags(port, KTU1125_SET_SW2_CFG, - KTU1125_VBUS_DIS_EN) - : clr_flags(port, KTU1125_SET_SW2_CFG, + KTU1125_VBUS_DIS_EN) : + clr_flags(port, KTU1125_SET_SW2_CFG, KTU1125_VBUS_DIS_EN); if (status) { - CPRINTS("ppc p%d: Failed to %s vbus discharge", - port, enable ? "enable" : "disable"); + CPRINTS("ppc p%d: Failed to %s vbus discharge", port, + enable ? "enable" : "disable"); return status; } @@ -355,11 +346,10 @@ static int ktu1125_discharge_vbus(int port, int enable) static int ktu1125_set_vconn(int port, int enable) { int status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_VCONN_EN) - : clr_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_VCONN_EN | - KTU1125_CC1S_VCONN | - KTU1125_CC2S_VCONN); + KTU1125_VCONN_EN) : + clr_flags(port, KTU1125_CTRL_SW_CFG, + KTU1125_VCONN_EN | KTU1125_CC1S_VCONN | + KTU1125_CC2S_VCONN); return status; } @@ -369,10 +359,9 @@ static int ktu1125_set_vconn(int port, int enable) static int ktu1125_set_frs_enable(int port, int enable) { /* Enable/Disable FR_SWAP Interrupt */ - int status = enable ? clr_flags(port, KTU1125_INTMASK_SNK, - KTU1125_FR_SWAP) - : set_flags(port, KTU1125_INTMASK_SNK, - KTU1125_FR_SWAP); + int status = + enable ? clr_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP) : + set_flags(port, KTU1125_INTMASK_SNK, KTU1125_FR_SWAP); if (status) { ppc_prints("Failed to write KTU1125_INTMASK_SNK!", port); @@ -380,10 +369,8 @@ static int ktu1125_set_frs_enable(int port, int enable) } /* Set the FRS_EN bit */ - status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_FRS_EN) - : clr_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_FRS_EN); + status = enable ? set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN) : + clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_FRS_EN); return status; } @@ -418,14 +405,14 @@ static int ktu1125_vbus_source_enable(int port, int enable) #ifdef CONFIG_USBC_PPC_SBU static int ktu1125_set_sbu(int port, int enable) { - int status = enable ? clr_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_SBU_SHUT) - : set_flags(port, KTU1125_CTRL_SW_CFG, - KTU1125_SBU_SHUT); + int status = + enable ? + clr_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT) : + set_flags(port, KTU1125_CTRL_SW_CFG, KTU1125_SBU_SHUT); if (status) { - CPRINTS("ppc p%d: Failed to %s sbu", - port, enable ? "enable" : "disable"); + CPRINTS("ppc p%d: Failed to %s sbu", port, + enable ? "enable" : "disable"); } return status; @@ -452,31 +439,29 @@ static void ktu1125_handle_interrupt(int port) attempt++; if (attempt > 1) ppc_prints("Could not clear interrupts on first " - "try, retrying", port); + "try, retrying", + port); /* Clear the interrupt by reading all 3 registers */ read_reg(port, KTU1125_INT_SNK, &snk); read_reg(port, KTU1125_INT_SRC, &src); read_reg(port, KTU1125_INT_DATA, &data); - CPRINTS("ppc p%d: INTERRUPT snk=%02X src=%02X data=%02X", - port, snk, src, data); + CPRINTS("ppc p%d: INTERRUPT snk=%02X src=%02X data=%02X", port, + snk, src, data); if (snk & KTU1125_FR_SWAP) pd_got_frs_signal(port); - if (snk & (KTU1125_SYSA_SCP | - KTU1125_SYSA_OCP | - KTU1125_VBUS_OVP)) { + if (snk & + (KTU1125_SYSA_SCP | KTU1125_SYSA_OCP | KTU1125_VBUS_OVP)) { /* Log and PD reset */ pd_handle_overcurrent(port); } - if (src & (KTU1125_SYSB_CLP | - KTU1125_SYSB_OCP | - KTU1125_SYSB_SCP | - KTU1125_VCONN_CLP | - KTU1125_VCONN_SCP)) { + if (src & + (KTU1125_SYSB_CLP | KTU1125_SYSB_OCP | KTU1125_SYSB_SCP | + KTU1125_VCONN_CLP | KTU1125_VCONN_SCP)) { /* Log and PD reset */ pd_handle_overcurrent(port); } -- cgit v1.2.1 From b6807f2a89e01735e977106c6db471031f2091a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:16 -0600 Subject: common/accel_cal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id84447ff4fe8ed3d4b3df5ab3d2fd649acf9c645 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729561 Reviewed-by: Jeremy Bettis --- common/accel_cal.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/common/accel_cal.c b/common/accel_cal.c index 533a14fbc4..ecb9fcfac3 100644 --- a/common/accel_cal.c +++ b/common/accel_cal.c @@ -23,17 +23,17 @@ void accel_cal_reset(struct accel_cal *cal) static inline int compute_temp_gate(const struct accel_cal *cal, fp_t temp) { - int gate = (int) fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP, - INT_TO_FP(cal->num_temp_windows)), - TEMP_RANGE); + int gate = (int)fp_div(fp_mul(temp - CONFIG_ACCEL_CAL_MIN_TEMP, + INT_TO_FP(cal->num_temp_windows)), + TEMP_RANGE); - return gate < cal->num_temp_windows - ? gate : (cal->num_temp_windows - 1); + return gate < cal->num_temp_windows ? gate : + (cal->num_temp_windows - 1); } -test_mockable bool accel_cal_accumulate( - struct accel_cal *cal, uint32_t timestamp, fp_t x, fp_t y, fp_t z, - fp_t temp) +test_mockable bool accel_cal_accumulate(struct accel_cal *cal, + uint32_t timestamp, fp_t x, fp_t y, + fp_t z, fp_t temp) { struct accel_cal_algo *algo; -- cgit v1.2.1 From 4609c387e22bfd33f87d10594a98c33cab5140eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:43 -0600 Subject: common/usbc/usbc_task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a9fa978ec7fd824775858c513d05a9f2e39d206 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729799 Reviewed-by: Jeremy Bettis --- common/usbc/usbc_task.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/usbc/usbc_task.c b/common/usbc/usbc_task.c index 915827b692..4faf36cff4 100644 --- a/common/usbc/usbc_task.c +++ b/common/usbc/usbc_task.c @@ -36,8 +36,8 @@ #define USBC_EVENT_TIMEOUT (5 * MSEC) #define USBC_MIN_EVENT_TIMEOUT (1 * MSEC) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* * If CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT is not defined then -- cgit v1.2.1 From bcc3ad6536e34151fb238910359bf7945c93c00f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:45 -0600 Subject: board/anahera/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia53e9037366ac9bfab4e98cf99eb24a3a10c4748 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728008 Reviewed-by: Jeremy Bettis --- board/anahera/thermal.c | 66 ++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 34 deletions(-) diff --git a/board/anahera/thermal.c b/board/anahera/thermal.c index 8bd670c22a..86b1ecd2d3 100644 --- a/board/anahera/thermal.c +++ b/board/anahera/thermal.c @@ -15,7 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -37,45 +37,45 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {53, 51, 0, -1}, - .off = {99, 99, 99, -1}, - .rpm = {0}, + .on = { 53, 51, 0, -1 }, + .off = { 99, 99, 99, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {54, 52, 0, -1}, - .off = {52, 50, 99, -1}, - .rpm = {3000}, + .on = { 54, 52, 0, -1 }, + .off = { 52, 50, 99, -1 }, + .rpm = { 3000 }, }, { /* level 2 */ - .on = {55, 53, 0, -1}, - .off = {53, 51, 99, -1}, - .rpm = {3400}, + .on = { 55, 53, 0, -1 }, + .off = { 53, 51, 99, -1 }, + .rpm = { 3400 }, }, { /* level 3 */ - .on = {56, 54, 0, -1}, - .off = {54, 52, 99, -1}, - .rpm = {3800}, + .on = { 56, 54, 0, -1 }, + .off = { 54, 52, 99, -1 }, + .rpm = { 3800 }, }, { /* level 4 */ - .on = {57, 55, 54, -1}, - .off = {55, 53, 51, -1}, - .rpm = {4100}, + .on = { 57, 55, 54, -1 }, + .off = { 55, 53, 51, -1 }, + .rpm = { 4100 }, }, { /* level 5 */ - .on = {58, 56, 60, -1}, - .off = {56, 54, 52, -1}, - .rpm = {4400}, + .on = { 58, 56, 60, -1 }, + .off = { 56, 54, 52, -1 }, + .rpm = { 4400 }, }, { /* level 6 */ - .on = {100, 100, 100, -1}, - .off = {57, 59, 58, -1}, - .rpm = {4900}, + .on = { 100, 100, 100, -1 }, + .off = { 57, 59, 58, -1 }, + .rpm = { 4900 }, }, }; @@ -99,11 +99,11 @@ int fan_table_to_rpm(int fan, int *temp) temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) { for (i = current_level; i > 0; i--) { if (temp[TEMP_SENSOR_1_FAN] < - fan_table[i].off[TEMP_SENSOR_1_FAN] && + fan_table[i].off[TEMP_SENSOR_1_FAN] && temp[TEMP_SENSOR_3_CHARGER] < - fan_table[i].off[TEMP_SENSOR_3_CHARGER] && + fan_table[i].off[TEMP_SENSOR_3_CHARGER] && temp[TEMP_SENSOR_2_SOC] < - fan_table[i].off[TEMP_SENSOR_2_SOC]) + fan_table[i].off[TEMP_SENSOR_2_SOC]) current_level = i - 1; else break; @@ -111,14 +111,14 @@ int fan_table_to_rpm(int fan, int *temp) } else if (temp[TEMP_SENSOR_1_FAN] > prev_tmp[TEMP_SENSOR_1_FAN] || temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] || temp[TEMP_SENSOR_3_CHARGER] > - prev_tmp[TEMP_SENSOR_3_CHARGER]) { + prev_tmp[TEMP_SENSOR_3_CHARGER]) { for (i = current_level; i < NUM_FAN_LEVELS; i++) { if ((temp[TEMP_SENSOR_1_FAN] > - fan_table[i].on[TEMP_SENSOR_1_FAN] && - temp[TEMP_SENSOR_3_CHARGER] > - fan_table[i].on[TEMP_SENSOR_3_CHARGER]) || + fan_table[i].on[TEMP_SENSOR_1_FAN] && + temp[TEMP_SENSOR_3_CHARGER] > + fan_table[i].on[TEMP_SENSOR_3_CHARGER]) || temp[TEMP_SENSOR_2_SOC] > - fan_table[i].on[TEMP_SENSOR_2_SOC]) + fan_table[i].on[TEMP_SENSOR_2_SOC]) current_level = i + 1; else break; @@ -139,10 +139,8 @@ int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } -- cgit v1.2.1 From ff0b722336191e241316d980c39ffd405a8af2bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:49 -0600 Subject: board/vell/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0723f4e4c2ca829a866a70d6407f5f75d23ec02d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729045 Reviewed-by: Jeremy Bettis --- board/vell/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/vell/fw_config.c b/board/vell/fw_config.c index 9c28c3ca58..7b5549dc89 100644 --- a/board/vell/fw_config.c +++ b/board/vell/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union brya_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From d35ee8c554962aa7be3ed7f5e46b5ee7abdd5eb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:04 -0600 Subject: driver/regulator_ir357x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I610dcf185d9f3614124929ce631a268bccbbc6a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730037 Reviewed-by: Jeremy Bettis --- driver/regulator_ir357x.c | 136 +++++++++++++++++++++++----------------------- 1 file changed, 67 insertions(+), 69 deletions(-) diff --git a/driver/regulator_ir357x.c b/driver/regulator_ir357x.c index 4721146367..3120bbc0ab 100644 --- a/driver/regulator_ir357x.c +++ b/driver/regulator_ir357x.c @@ -14,7 +14,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) /* I2C address */ #define IR357x_I2C_ADDR_FLAGS 0x08 @@ -25,73 +25,72 @@ struct ir_setting { }; static struct ir_setting ir3570_settings[] = { - {0x10, 0x22}, {0x11, 0x22}, {0x12, 0x88}, {0x13, 0x10}, - {0x14, 0x0d}, {0x15, 0x21}, {0x16, 0x21}, {0x17, 0x00}, - {0x18, 0x00}, {0x19, 0x00}, {0x1a, 0x00}, {0x1b, 0x00}, - {0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00}, {0x1f, 0x00}, - {0x20, 0x00}, {0x21, 0x00}, {0x22, 0x60}, {0x23, 0x60}, - {0x24, 0x74}, {0x25, 0x4e}, {0x26, 0xff}, {0x27, 0x80}, - {0x28, 0x00}, {0x29, 0x20}, {0x2a, 0x15}, {0x2b, 0x26}, - {0x2c, 0xb6}, {0x2d, 0x21}, {0x2e, 0x11}, {0x2f, 0x20}, - {0x30, 0xab}, {0x31, 0x14}, {0x32, 0x90}, {0x33, 0x4d}, - {0x34, 0x75}, {0x35, 0x64}, {0x36, 0x64}, {0x37, 0x09}, - {0x38, 0xc4}, {0x39, 0x20}, {0x3a, 0x80}, {0x3b, 0x00}, - {0x3c, 0x00}, {0x3d, 0xaa}, {0x3e, 0x00}, {0x3f, 0x05}, - {0x40, 0x50}, {0x41, 0x40}, {0x42, 0x00}, {0x43, 0x00}, - {0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x00}, - {0x48, 0x1c}, {0x49, 0x0c}, {0x4a, 0x0f}, {0x4b, 0x40}, - {0x4c, 0x80}, {0x4d, 0x40}, {0x4e, 0x80}, - {0x51, 0x00}, {0x52, 0x45}, {0x53, 0x59}, - {0x54, 0x23}, {0x55, 0xae}, {0x56, 0x68}, {0x57, 0x24}, - {0x58, 0x62}, {0x59, 0x42}, {0x5a, 0x34}, {0x5b, 0x00}, - {0x5c, 0x30}, {0x5d, 0x05}, {0x5e, 0x02}, {0x5f, 0x35}, - {0x60, 0x30}, {0x61, 0x00}, {0x62, 0xd8}, {0x63, 0x00}, - {0x64, 0x52}, {0x65, 0x28}, {0x66, 0x14}, {0x67, 0x87}, - {0x68, 0x80}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00}, - {0x6c, 0x00}, {0x6d, 0xff}, {0x6e, 0x06}, {0x6f, 0xff}, - {0x70, 0xff}, {0x71, 0x20}, {0x72, 0x00}, {0x73, 0x01}, - {0x74, 0x00}, {0x75, 0x00}, {0x76, 0x00}, {0x77, 0x00}, - {0x78, 0x00}, {0x79, 0x00}, {0x7a, 0x00}, {0x7b, 0x00}, - {0x7c, 0x15}, {0x7d, 0x15}, {0x7e, 0x00}, {0x7f, 0x00}, - {0x80, 0x00}, {0x81, 0x00}, {0x82, 0x00}, {0x83, 0x00}, - {0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00}, - {0x88, 0x88}, {0x89, 0x88}, {0x8a, 0x01}, {0x8b, 0x42}, - {0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x1f}, - {0, 0} + { 0x10, 0x22 }, { 0x11, 0x22 }, { 0x12, 0x88 }, { 0x13, 0x10 }, + { 0x14, 0x0d }, { 0x15, 0x21 }, { 0x16, 0x21 }, { 0x17, 0x00 }, + { 0x18, 0x00 }, { 0x19, 0x00 }, { 0x1a, 0x00 }, { 0x1b, 0x00 }, + { 0x1c, 0x00 }, { 0x1d, 0x00 }, { 0x1e, 0x00 }, { 0x1f, 0x00 }, + { 0x20, 0x00 }, { 0x21, 0x00 }, { 0x22, 0x60 }, { 0x23, 0x60 }, + { 0x24, 0x74 }, { 0x25, 0x4e }, { 0x26, 0xff }, { 0x27, 0x80 }, + { 0x28, 0x00 }, { 0x29, 0x20 }, { 0x2a, 0x15 }, { 0x2b, 0x26 }, + { 0x2c, 0xb6 }, { 0x2d, 0x21 }, { 0x2e, 0x11 }, { 0x2f, 0x20 }, + { 0x30, 0xab }, { 0x31, 0x14 }, { 0x32, 0x90 }, { 0x33, 0x4d }, + { 0x34, 0x75 }, { 0x35, 0x64 }, { 0x36, 0x64 }, { 0x37, 0x09 }, + { 0x38, 0xc4 }, { 0x39, 0x20 }, { 0x3a, 0x80 }, { 0x3b, 0x00 }, + { 0x3c, 0x00 }, { 0x3d, 0xaa }, { 0x3e, 0x00 }, { 0x3f, 0x05 }, + { 0x40, 0x50 }, { 0x41, 0x40 }, { 0x42, 0x00 }, { 0x43, 0x00 }, + { 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x00 }, + { 0x48, 0x1c }, { 0x49, 0x0c }, { 0x4a, 0x0f }, { 0x4b, 0x40 }, + { 0x4c, 0x80 }, { 0x4d, 0x40 }, { 0x4e, 0x80 }, { 0x51, 0x00 }, + { 0x52, 0x45 }, { 0x53, 0x59 }, { 0x54, 0x23 }, { 0x55, 0xae }, + { 0x56, 0x68 }, { 0x57, 0x24 }, { 0x58, 0x62 }, { 0x59, 0x42 }, + { 0x5a, 0x34 }, { 0x5b, 0x00 }, { 0x5c, 0x30 }, { 0x5d, 0x05 }, + { 0x5e, 0x02 }, { 0x5f, 0x35 }, { 0x60, 0x30 }, { 0x61, 0x00 }, + { 0x62, 0xd8 }, { 0x63, 0x00 }, { 0x64, 0x52 }, { 0x65, 0x28 }, + { 0x66, 0x14 }, { 0x67, 0x87 }, { 0x68, 0x80 }, { 0x69, 0x00 }, + { 0x6a, 0x00 }, { 0x6b, 0x00 }, { 0x6c, 0x00 }, { 0x6d, 0xff }, + { 0x6e, 0x06 }, { 0x6f, 0xff }, { 0x70, 0xff }, { 0x71, 0x20 }, + { 0x72, 0x00 }, { 0x73, 0x01 }, { 0x74, 0x00 }, { 0x75, 0x00 }, + { 0x76, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 }, { 0x79, 0x00 }, + { 0x7a, 0x00 }, { 0x7b, 0x00 }, { 0x7c, 0x15 }, { 0x7d, 0x15 }, + { 0x7e, 0x00 }, { 0x7f, 0x00 }, { 0x80, 0x00 }, { 0x81, 0x00 }, + { 0x82, 0x00 }, { 0x83, 0x00 }, { 0x84, 0x00 }, { 0x85, 0x00 }, + { 0x86, 0x00 }, { 0x87, 0x00 }, { 0x88, 0x88 }, { 0x89, 0x88 }, + { 0x8a, 0x01 }, { 0x8b, 0x42 }, { 0x8d, 0x00 }, { 0x8e, 0x00 }, + { 0x8f, 0x1f }, { 0, 0 } }; static struct ir_setting ir3571_settings[] = { - {0x18, 0x22}, {0x19, 0x22}, {0x1a, 0x08}, {0x1b, 0x10}, - {0x1c, 0x06}, {0x1d, 0x21}, {0x1e, 0x21}, {0x1f, 0x83}, - {0x20, 0x83}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00}, - {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x34}, - {0x28, 0x34}, {0x29, 0x74}, {0x2a, 0x4e}, {0x2b, 0xff}, - {0x2c, 0x00}, {0x2d, 0x1d}, {0x2e, 0x14}, {0x2f, 0x1f}, - {0x30, 0x88}, {0x31, 0x9a}, {0x32, 0x1e}, {0x33, 0x19}, - {0x34, 0xe9}, {0x35, 0x40}, {0x36, 0x90}, {0x37, 0x6d}, - {0x38, 0x75}, {0x39, 0xa0}, {0x3a, 0x84}, {0x3b, 0x08}, - {0x3c, 0xc5}, {0x3d, 0xa0}, {0x3e, 0x80}, {0x3f, 0xaa}, - {0x40, 0x50}, {0x41, 0x4b}, {0x42, 0x02}, {0x43, 0x04}, - {0x44, 0x00}, {0x45, 0x00}, {0x46, 0x00}, {0x47, 0x78}, - {0x48, 0x56}, {0x49, 0x18}, {0x4a, 0x88}, {0x4b, 0x00}, - {0x4c, 0x80}, {0x4d, 0x60}, {0x4e, 0x60}, {0x4f, 0xff}, - {0x50, 0xff}, {0x51, 0x00}, {0x52, 0x9b}, {0x53, 0xaa}, - {0x54, 0xd8}, {0x55, 0x56}, {0x56, 0x31}, {0x57, 0x1a}, - {0x58, 0x12}, {0x59, 0x63}, {0x5a, 0x00}, {0x5b, 0x09}, - {0x5c, 0x02}, {0x5d, 0x00}, {0x5e, 0xea}, {0x5f, 0x00}, - {0x60, 0xb0}, {0x61, 0x1e}, {0x62, 0x00}, {0x63, 0x56}, - {0x64, 0x00}, {0x65, 0x00}, {0x66, 0x00}, {0x67, 0x00}, - {0x68, 0x28}, {0x69, 0x00}, {0x6a, 0x00}, {0x6b, 0x00}, - {0x6c, 0x00}, {0x6d, 0x00}, {0x6e, 0x00}, {0x6f, 0x00}, - {0x70, 0x80}, {0x71, 0x00}, {0x72, 0x00}, {0x73, 0x00}, - {0x74, 0x00}, {0x75, 0xbf}, {0x76, 0x06}, {0x77, 0xff}, - {0x78, 0xff}, {0x79, 0x04}, {0x7a, 0x00}, {0x7b, 0x1d}, - {0x7c, 0xa0}, {0x7d, 0x10}, {0x7e, 0x00}, {0x7f, 0x8a}, - {0x80, 0x1b}, {0x81, 0x11}, {0x82, 0x00}, {0x83, 0x00}, - {0x84, 0x00}, {0x85, 0x00}, {0x86, 0x00}, {0x87, 0x00}, - {0x88, 0x00}, {0x89, 0x00}, {0x8a, 0x00}, {0x8b, 0x00}, - {0x8c, 0x00}, {0x8d, 0x00}, {0x8e, 0x00}, {0x8f, 0x00}, - {0, 0} + { 0x18, 0x22 }, { 0x19, 0x22 }, { 0x1a, 0x08 }, { 0x1b, 0x10 }, + { 0x1c, 0x06 }, { 0x1d, 0x21 }, { 0x1e, 0x21 }, { 0x1f, 0x83 }, + { 0x20, 0x83 }, { 0x21, 0x00 }, { 0x22, 0x00 }, { 0x23, 0x00 }, + { 0x24, 0x00 }, { 0x25, 0x00 }, { 0x26, 0x00 }, { 0x27, 0x34 }, + { 0x28, 0x34 }, { 0x29, 0x74 }, { 0x2a, 0x4e }, { 0x2b, 0xff }, + { 0x2c, 0x00 }, { 0x2d, 0x1d }, { 0x2e, 0x14 }, { 0x2f, 0x1f }, + { 0x30, 0x88 }, { 0x31, 0x9a }, { 0x32, 0x1e }, { 0x33, 0x19 }, + { 0x34, 0xe9 }, { 0x35, 0x40 }, { 0x36, 0x90 }, { 0x37, 0x6d }, + { 0x38, 0x75 }, { 0x39, 0xa0 }, { 0x3a, 0x84 }, { 0x3b, 0x08 }, + { 0x3c, 0xc5 }, { 0x3d, 0xa0 }, { 0x3e, 0x80 }, { 0x3f, 0xaa }, + { 0x40, 0x50 }, { 0x41, 0x4b }, { 0x42, 0x02 }, { 0x43, 0x04 }, + { 0x44, 0x00 }, { 0x45, 0x00 }, { 0x46, 0x00 }, { 0x47, 0x78 }, + { 0x48, 0x56 }, { 0x49, 0x18 }, { 0x4a, 0x88 }, { 0x4b, 0x00 }, + { 0x4c, 0x80 }, { 0x4d, 0x60 }, { 0x4e, 0x60 }, { 0x4f, 0xff }, + { 0x50, 0xff }, { 0x51, 0x00 }, { 0x52, 0x9b }, { 0x53, 0xaa }, + { 0x54, 0xd8 }, { 0x55, 0x56 }, { 0x56, 0x31 }, { 0x57, 0x1a }, + { 0x58, 0x12 }, { 0x59, 0x63 }, { 0x5a, 0x00 }, { 0x5b, 0x09 }, + { 0x5c, 0x02 }, { 0x5d, 0x00 }, { 0x5e, 0xea }, { 0x5f, 0x00 }, + { 0x60, 0xb0 }, { 0x61, 0x1e }, { 0x62, 0x00 }, { 0x63, 0x56 }, + { 0x64, 0x00 }, { 0x65, 0x00 }, { 0x66, 0x00 }, { 0x67, 0x00 }, + { 0x68, 0x28 }, { 0x69, 0x00 }, { 0x6a, 0x00 }, { 0x6b, 0x00 }, + { 0x6c, 0x00 }, { 0x6d, 0x00 }, { 0x6e, 0x00 }, { 0x6f, 0x00 }, + { 0x70, 0x80 }, { 0x71, 0x00 }, { 0x72, 0x00 }, { 0x73, 0x00 }, + { 0x74, 0x00 }, { 0x75, 0xbf }, { 0x76, 0x06 }, { 0x77, 0xff }, + { 0x78, 0xff }, { 0x79, 0x04 }, { 0x7a, 0x00 }, { 0x7b, 0x1d }, + { 0x7c, 0xa0 }, { 0x7d, 0x10 }, { 0x7e, 0x00 }, { 0x7f, 0x8a }, + { 0x80, 0x1b }, { 0x81, 0x11 }, { 0x82, 0x00 }, { 0x83, 0x00 }, + { 0x84, 0x00 }, { 0x85, 0x00 }, { 0x86, 0x00 }, { 0x87, 0x00 }, + { 0x88, 0x00 }, { 0x89, 0x00 }, { 0x8a, 0x00 }, { 0x8b, 0x00 }, + { 0x8c, 0x00 }, { 0x8d, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 }, + { 0, 0 } }; static uint8_t ir357x_read(uint8_t reg) @@ -186,8 +185,8 @@ static int ir357x_check(void) for (; settings->reg; settings++) { val = ir357x_read(settings->reg); if (val != settings->value) { - ccprintf("DIFF reg 0x%02x %02x->%02x\n", - settings->reg, settings->value, val); + ccprintf("DIFF reg 0x%02x %02x->%02x\n", settings->reg, + settings->value, val); cflush(); diff++; } @@ -234,8 +233,7 @@ static int command_ir357x(int argc, char **argv) return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x, - "[check|write]", +DECLARE_CONSOLE_COMMAND(ir357x, command_ir357x, "[check|write]", "IR357x core regulator control"); #endif -- cgit v1.2.1 From 260e7891d9479571e30d0210c44c3f2a709afe39 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:18 -0600 Subject: board/dratini/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I387ddb9f04e99e978063407b4161ad5bf42ffed3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726421 Reviewed-by: Jeremy Bettis --- board/dratini/board.c | 99 ++++++++++++++++++++++++--------------------------- 1 file changed, 47 insertions(+), 52 deletions(-) diff --git a/board/dratini/board.c b/board/dratini/board.c index 61634d3a7b..428c4316d4 100644 --- a/board/dratini/board.c +++ b/board/dratini/board.c @@ -43,8 +43,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void check_reboot_deferred(void); DECLARE_DEFERRED(check_reboot_deferred); @@ -128,16 +128,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -201,17 +201,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -291,7 +287,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -310,44 +306,43 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "5V Reg", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "5V Reg", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Dratini Temperature sensors */ /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(73), \ @@ -366,8 +361,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(68), \ @@ -404,8 +399,8 @@ bool board_is_convertible(void) * Dratini is not. * Unprovisioned SKU 255. */ - return sku_id == 21 || sku_id == 22 || sku_id == 23 || - sku_id == 24 || sku_id == 255; + return sku_id == 21 || sku_id == 22 || sku_id == 23 || sku_id == 24 || + sku_id == 255; } static void board_update_sensor_config_from_sku(void) @@ -485,7 +480,7 @@ bool board_has_kb_backlight(void) * Unprovisioned: 255 */ return sku_id == 2 || sku_id == 3 || sku_id == 5 || sku_id == 8 || - sku_id == 22 || sku_id == 24 || sku_id == 255; + sku_id == 22 || sku_id == 24 || sku_id == 255; } __override uint32_t board_override_feature_flags0(uint32_t flags0) @@ -503,15 +498,15 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif /* Disable HDMI power while AP is suspended / off */ @@ -540,7 +535,7 @@ __override void board_chipset_forced_shutdown(void) hook_call_deferred(&check_reboot_deferred_data, -1); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void check_reboot_deferred(void) { -- cgit v1.2.1 From 009e390a769a4295b9fc33ffa468b4bd48cf1802 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:25 -0600 Subject: board/twinkie/simpletrace.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a0eaa52ca3651e7ec58553ec0c7b66b8d2b4697 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729041 Reviewed-by: Jeremy Bettis --- board/twinkie/simpletrace.c | 95 ++++++++++++++++++++++----------------------- 1 file changed, 46 insertions(+), 49 deletions(-) diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c index 811bd428fd..6f9e6d1da3 100644 --- a/board/twinkie/simpletrace.c +++ b/board/twinkie/simpletrace.c @@ -25,61 +25,57 @@ int trace_mode; /* The FSM is waiting for the following command (0 == None) */ uint8_t expected_cmd; -static const char * const ctrl_msg_name[] = { - [0] = "RSVD-C0", - [PD_CTRL_GOOD_CRC] = "GOODCRC", - [PD_CTRL_GOTO_MIN] = "GOTOMIN", - [PD_CTRL_ACCEPT] = "ACCEPT", - [PD_CTRL_REJECT] = "REJECT", - [PD_CTRL_PING] = "PING", - [PD_CTRL_PS_RDY] = "PSRDY", +static const char *const ctrl_msg_name[] = { + [0] = "RSVD-C0", + [PD_CTRL_GOOD_CRC] = "GOODCRC", + [PD_CTRL_GOTO_MIN] = "GOTOMIN", + [PD_CTRL_ACCEPT] = "ACCEPT", + [PD_CTRL_REJECT] = "REJECT", + [PD_CTRL_PING] = "PING", + [PD_CTRL_PS_RDY] = "PSRDY", [PD_CTRL_GET_SOURCE_CAP] = "GSRCCAP", - [PD_CTRL_GET_SINK_CAP] = "GSNKCAP", - [PD_CTRL_DR_SWAP] = "DRSWAP", - [PD_CTRL_PR_SWAP] = "PRSWAP", - [PD_CTRL_VCONN_SWAP] = "VCONNSW", - [PD_CTRL_WAIT] = "WAIT", - [PD_CTRL_SOFT_RESET] = "SFT-RST", - [14] = "RSVD-C14", - [15] = "RSVD-C15", + [PD_CTRL_GET_SINK_CAP] = "GSNKCAP", + [PD_CTRL_DR_SWAP] = "DRSWAP", + [PD_CTRL_PR_SWAP] = "PRSWAP", + [PD_CTRL_VCONN_SWAP] = "VCONNSW", + [PD_CTRL_WAIT] = "WAIT", + [PD_CTRL_SOFT_RESET] = "SFT-RST", + [14] = "RSVD-C14", + [15] = "RSVD-C15", }; -static const char * const data_msg_name[] = { - [0] = "RSVD-D0", - [PD_DATA_SOURCE_CAP] = "SRCCAP", - [PD_DATA_REQUEST] = "REQUEST", - [PD_DATA_BIST] = "BIST", - [PD_DATA_SINK_CAP] = "SNKCAP", +static const char *const data_msg_name[] = { + [0] = "RSVD-D0", + [PD_DATA_SOURCE_CAP] = "SRCCAP", + [PD_DATA_REQUEST] = "REQUEST", + [PD_DATA_BIST] = "BIST", + [PD_DATA_SINK_CAP] = "SNKCAP", /* 5-14 Reserved */ - [PD_DATA_VENDOR_DEF] = "VDM", + [PD_DATA_VENDOR_DEF] = "VDM", }; -static const char * const svdm_cmd_name[] = { - [CMD_DISCOVER_IDENT] = "DISCID", - [CMD_DISCOVER_SVID] = "DISCSVID", - [CMD_DISCOVER_MODES] = "DISCMODE", - [CMD_ENTER_MODE] = "ENTER", - [CMD_EXIT_MODE] = "EXIT", - [CMD_ATTENTION] = "ATTN", - [CMD_DP_STATUS] = "DPSTAT", - [CMD_DP_CONFIG] = "DPCFG", +static const char *const svdm_cmd_name[] = { + [CMD_DISCOVER_IDENT] = "DISCID", [CMD_DISCOVER_SVID] = "DISCSVID", + [CMD_DISCOVER_MODES] = "DISCMODE", [CMD_ENTER_MODE] = "ENTER", + [CMD_EXIT_MODE] = "EXIT", [CMD_ATTENTION] = "ATTN", + [CMD_DP_STATUS] = "DPSTAT", [CMD_DP_CONFIG] = "DPCFG", }; -static const char * const svdm_cmdt_name[] = { - [CMDT_INIT] = "INI", - [CMDT_RSP_ACK] = "ACK", - [CMDT_RSP_NAK] = "NAK", +static const char *const svdm_cmdt_name[] = { + [CMDT_INIT] = "INI", + [CMDT_RSP_ACK] = "ACK", + [CMDT_RSP_NAK] = "NAK", [CMDT_RSP_BUSY] = "BSY", }; static void print_pdo(uint32_t word) { if ((word & PDO_TYPE_MASK) == PDO_TYPE_BATTERY) - ccprintf(" %dmV/%dmW", ((word>>10)&0x3ff)*50, - (word&0x3ff)*250); + ccprintf(" %dmV/%dmW", ((word >> 10) & 0x3ff) * 50, + (word & 0x3ff) * 250); else - ccprintf(" %dmV/%dmA", ((word>>10)&0x3ff)*50, - (word&0x3ff)*10); + ccprintf(" %dmV/%dmA", ((word >> 10) & 0x3ff) * 50, + (word & 0x3ff) * 10); } static void print_rdo(uint32_t word) @@ -119,8 +115,8 @@ static void print_packet(int head, uint32_t *payload) } name = cnt ? data_msg_name[typ] : ctrl_msg_name[typ]; prole = head & (PD_ROLE_SOURCE << 8) ? "SRC" : "SNK"; - ccprintf("%pT %s/%d [%04x]%s", - PRINTF_TIMESTAMP_NOW, prole, id, head, name); + ccprintf("%pT %s/%d [%04x]%s", PRINTF_TIMESTAMP_NOW, prole, id, head, + name); if (!cnt) { /* Control message : we are done */ ccputs("\n"); return; @@ -144,7 +140,7 @@ static void print_packet(int head, uint32_t *payload) break; default: ccprintf(" %08x", payload[i]); - } + } ccputs("\n"); } @@ -176,19 +172,20 @@ static void rx_event(void) if (pending & (1 << (21 + i))) { rx_edge_ts[i][rx_edge_ts_idx[i]].val = get_time().val; next_idx = (rx_edge_ts_idx[i] == - PD_RX_TRANSITION_COUNT - 1) ? - 0 : rx_edge_ts_idx[i] + 1; + PD_RX_TRANSITION_COUNT - 1) ? + 0 : + rx_edge_ts_idx[i] + 1; /* * If we have seen enough edges in a certain amount of * time, then trigger RX start. */ if ((rx_edge_ts[i][rx_edge_ts_idx[i]].val - - rx_edge_ts[i][next_idx].val) - < PD_RX_TRANSITION_WINDOW) { + rx_edge_ts[i][next_idx].val) < + PD_RX_TRANSITION_WINDOW) { /* acquire the message only on the active CC */ - STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN - : STM32_COMP_CMP2EN); + STM32_COMP_CSR &= ~(i ? STM32_COMP_CMP1EN : + STM32_COMP_CMP2EN); /* start sampling */ pd_rx_start(0); /* -- cgit v1.2.1 From ef802086ba60f74c55b52cfef9628770d2d3b4db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:37 -0600 Subject: board/servo_v4p1/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic865ed99c5195b72f7c7aca21346f68b993dea70 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728928 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/board.h | 87 +++++++++++++++++++++++------------------------- 1 file changed, 42 insertions(+), 45 deletions(-) diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h index 86367a5d0b..49f2811188 100644 --- a/board/servo_v4p1/board.h +++ b/board/servo_v4p1/board.h @@ -58,31 +58,30 @@ #define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE - #define CONFIG_FLASH_PSTATE #define CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (92*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (92 * 1024) -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* Enable USART1,3,4 and USB streams */ #define CONFIG_STREAM_USART @@ -106,7 +105,7 @@ * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a * falling voltage threshold of min:2.09V, max:2.27V. */ -#define PVD_THRESHOLD (1) +#define PVD_THRESHOLD (1) /* USB Configuration */ #define CONFIG_USB @@ -125,23 +124,23 @@ #define DEFAULT_MAC_ADDR "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_EMPTY 1 -#define USB_IFACE_I2C 2 -#define USB_IFACE_USART3_STREAM 3 -#define USB_IFACE_USART4_STREAM 4 -#define USB_IFACE_UPDATE 5 -#define USB_IFACE_COUNT 6 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_EMPTY 1 +#define USB_IFACE_I2C 2 +#define USB_IFACE_USART3_STREAM 3 +#define USB_IFACE_USART4_STREAM 4 +#define USB_IFACE_UPDATE 5 +#define USB_IFACE_COUNT 6 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_EMPTY 2 -#define USB_EP_I2C 3 -#define USB_EP_USART3_STREAM 4 -#define USB_EP_USART4_STREAM 5 -#define USB_EP_UPDATE 6 -#define USB_EP_COUNT 7 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_EMPTY 2 +#define USB_EP_I2C 3 +#define USB_EP_USART3_STREAM 4 +#define USB_EP_USART4_STREAM 5 +#define USB_EP_UPDATE 6 +#define USB_EP_COUNT 7 /* Enable console recasting of GPIO type. */ #define CONFIG_CMD_GPIO_EXTENDED @@ -182,7 +181,7 @@ /* PD features */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_BOARD_PRE_INIT /* * If task profiling is enabled then the rx falling edge detection interrupts @@ -196,7 +195,7 @@ #define CONFIG_USB_HUB_GL3590 #define CONFIG_INA231 #define CONFIG_CHARGE_MANAGER -#undef CONFIG_CHARGE_MANAGER_SAFE_MODE +#undef CONFIG_CHARGE_MANAGER_SAFE_MODE #define CONFIG_USB_MUX_TUSB1064 #define CONFIG_USB_POWER_DELIVERY #define CONFIG_USB_PD_TCPMV1 @@ -221,8 +220,8 @@ #define CONFIG_USB_PD_INITIAL_DRP_STATE PD_DRP_FORCE_SINK /* Variable-current Rp no connect and Ra attach macros */ -#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) -#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) +#define CC_NC(port, cc, sel) (pd_tcpc_cc_nc(port, cc, sel)) +#define CC_RA(port, cc, sel) (pd_tcpc_cc_ra(port, cc, sel)) /* * These power-supply timing values are now set towards maximum spec limit, @@ -231,14 +230,14 @@ * Currently tuned with the Apple 96W adapter. * TODO: Change to EVENT-based PS_RDY notification (b/214216304) */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY (121*MSEC) -#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461*MSEC) +#define PD_POWER_SUPPLY_TURN_ON_DELAY (121 * MSEC) +#define PD_POWER_SUPPLY_TURN_OFF_DELAY (461 * MSEC) /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Add the raw option to the i2c_xfer command */ #define CONFIG_CMD_I2C_XFER_RAW @@ -266,8 +265,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 - +#define TIM_ADC 3 #include "gpio_signal.h" @@ -286,7 +284,6 @@ enum usb_strings { USB_STR_COUNT }; - /* ADC signal */ enum adc_channel { ADC_CHG_CC1_PD, -- cgit v1.2.1 From 0346accd82a493a92de735a681b9452c49057bae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:17 -0600 Subject: chip/ish/dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2935e915568ccf6604ce907e5715bf4c38e61684 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729155 Reviewed-by: Jeremy Bettis --- chip/ish/dma.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/chip/ish/dma.c b/chip/ish/dma.c index b9744fd234..a14e1284d6 100644 --- a/chip/ish/dma.c +++ b/chip/ish/dma.c @@ -112,8 +112,8 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, mode |= NON_SNOOP; MISC_DMA_CTL_REG(chan) = mode; /* Set transfer direction */ - DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */ - DMA_LLP(chan_reg) = 0; /* Linked lists are not used */ + DMA_CFG_REG = DMA_ENABLE; /* Enable DMA module */ + DMA_LLP(chan_reg) = 0; /* Linked lists are not used */ DMA_CTL_LOW(chan_reg) = 0 /* Set transfer parameters */ | (DMA_CTL_TT_FC_M2M_DMAC << DMA_CTL_TT_FC_SHIFT) | @@ -126,24 +126,26 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, interrupt_unlock(eflags); while (length) { - chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE - : length; + chunk = (length > DMA_MAX_BLOCK_SIZE) ? DMA_MAX_BLOCK_SIZE : + length; if (rc != DMA_RC_OK) break; eflags = interrupt_lock(); MISC_CHID_CFG_REG = chan; /* Set channel to configure */ - DMA_CTL_HIGH(chan_reg) = - chunk; /* Set number of bytes to transfer */ + DMA_CTL_HIGH(chan_reg) = chunk; /* Set number of bytes to + transfer */ DMA_DAR(chan_reg) = dst; /* Destination address */ DMA_SAR(chan_reg) = src; /* Source address */ - DMA_EN_REG = DMA_CH_EN_BIT(chan) | - DMA_CH_EN_WE_BIT(chan); /* Enable the channel */ + DMA_EN_REG = DMA_CH_EN_BIT(chan) | DMA_CH_EN_WE_BIT(chan); /* Enable + the + channel + */ interrupt_unlock(eflags); - rc = ish_wait_for_dma_done( - chan); /* Wait for trans completion */ + rc = ish_wait_for_dma_done(chan); /* Wait for trans completion + */ dst += chunk; src += chunk; -- cgit v1.2.1 From 6ce7693ceae2f795b5e8b3a8f531aa8e61989f3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:51 -0600 Subject: board/waddledee/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd4a6ccf237053b1a00bfa102a4c16b851a2f56e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729096 Reviewed-by: Jeremy Bettis --- board/waddledee/board.c | 74 +++++++++++++++++++++---------------------------- 1 file changed, 32 insertions(+), 42 deletions(-) diff --git a/board/waddledee/board.c b/board/waddledee/board.c index 90d1f7f2bd..90bb4efa6d 100644 --- a/board/waddledee/board.c +++ b/board/waddledee/board.c @@ -40,7 +40,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -127,34 +127,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -239,7 +231,6 @@ void board_init(void) c1_int_line = GPIO_USB_C1_INT_V1_ODL; } - gpio_enable_interrupt(GPIO_USB_C0_INT_ODL); gpio_enable_interrupt(c1_int_line); @@ -403,9 +394,8 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) gpio_set_level(GPIO_EN_USB_C0_CC2_VCONN, !!enabled); } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 14; @@ -463,7 +453,7 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Sensor Data */ -static struct kionix_accel_data g_kx022_data; +static struct kionix_accel_data g_kx022_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Drivers */ @@ -543,14 +533,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From a2f72f74e578398bd7525d457cdf445e2ded1291 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:56 -0600 Subject: driver/mag_lis2mdl.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3416b2c51961fba4f38a7054cd27a8f005196a00 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730018 Reviewed-by: Jeremy Bettis --- driver/mag_lis2mdl.c | 79 ++++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 43 deletions(-) diff --git a/driver/mag_lis2mdl.c b/driver/mag_lis2mdl.c index c0f7dff90d..64bb413b16 100644 --- a/driver/mag_lis2mdl.c +++ b/driver/mag_lis2mdl.c @@ -24,11 +24,9 @@ #endif #endif -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) -void lis2mdl_normalize(const struct motion_sensor_t *s, - intv3_t v, - uint8_t *raw) +void lis2mdl_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *raw) { struct mag_cal_t *cal = LIS2MDL_CAL(s); int i; @@ -82,8 +80,8 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd) * @offset: offset vector * @temp: Temp */ -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { struct mag_cal_t *cal = LIS2MDL_CAL(s); @@ -100,8 +98,8 @@ static int set_offset(const struct motion_sensor_t *s, * @offset: offset vector * @temp: Temp */ -static int get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp) +static int get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct mag_cal_t *cal = LIS2MDL_CAL(s); intv3_t offset_int; @@ -139,26 +137,24 @@ int lis2mdl_thru_lsm6dsm_init(struct motion_sensor_t *s) mutex_lock(s->mutex); /* Magnetometer in cascade mode */ - ret = sensorhub_check_and_rst( - LSM6DSM_MAIN_SENSOR(s), - CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, - LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I, - LIS2MDL_CFG_REG_A_ADDR, LIS2MDL_FLAG_SW_RESET); + ret = sensorhub_check_and_rst(LSM6DSM_MAIN_SENSOR(s), + CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, + LIS2MDL_WHO_AM_I_REG, LIS2MDL_WHO_AM_I, + LIS2MDL_CFG_REG_A_ADDR, + LIS2MDL_FLAG_SW_RESET); if (ret != EC_SUCCESS) goto err_unlock; - ret = sensorhub_config_ext_reg( - LSM6DSM_MAIN_SENSOR(s), - CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, - LIS2MDL_CFG_REG_A_ADDR, - LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT); + ret = sensorhub_config_ext_reg(LSM6DSM_MAIN_SENSOR(s), + CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, + LIS2MDL_CFG_REG_A_ADDR, + LIS2MDL_ODR_50HZ | LIS2MDL_MODE_CONT); if (ret != EC_SUCCESS) goto err_unlock; - ret = sensorhub_config_slv0_read( - LSM6DSM_MAIN_SENSOR(s), - CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, - LIS2MDL_OUT_REG, OUT_XYZ_SIZE); + ret = sensorhub_config_slv0_read(LSM6DSM_MAIN_SENSOR(s), + CONFIG_ACCELGYRO_SEC_ADDR_FLAGS, + LIS2MDL_OUT_REG, OUT_XYZ_SIZE); if (ret != EC_SUCCESS) goto err_unlock; @@ -197,8 +193,8 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2MDL_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2MDL_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { *ready = 0; return ret; @@ -206,7 +202,6 @@ static int lis2mdl_is_data_ready(const struct motion_sensor_t *s, int *ready) *ready = tmp & LIS2MDL_XYZ_DIRTY_MASK; return EC_SUCCESS; - } /** @@ -239,8 +234,8 @@ int lis2mdl_read(const struct motion_sensor_t *s, intv3_t v) } mutex_lock(s->mutex); - ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, - LIS2MDL_OUT_REG, raw, OUT_XYZ_SIZE); + ret = st_raw_read_n(s->port, s->i2c_spi_addr_flags, LIS2MDL_OUT_REG, + raw, OUT_XYZ_SIZE); mutex_unlock(s->mutex); if (ret == EC_SUCCESS) { lis2mdl_normalize(s, v, raw); @@ -280,8 +275,7 @@ int lis2mdl_init(struct motion_sensor_t *s) mutex_lock(s->mutex); /* Reset the sensor */ - ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS, - LIS2MDL_CFG_REG_A_ADDR, + ret = st_raw_write8(s->port, LIS2MDL_ADDR_FLAGS, LIS2MDL_CFG_REG_A_ADDR, LIS2MDL_FLAG_SW_RESET); if (ret != EC_SUCCESS) goto lis2mdl_init_error; @@ -330,20 +324,20 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) if (rate > 0) { if (rnd) /* Round up */ - reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ - : rate <= 20000 ? LIS2MDL_ODR_20HZ - : LIS2MDL_ODR_50HZ; + reg_val = rate <= 10000 ? LIS2MDL_ODR_10HZ : + rate <= 20000 ? LIS2MDL_ODR_20HZ : + LIS2MDL_ODR_50HZ; else /* Round down */ - reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ - : rate < 50000 ? LIS2MDL_ODR_20HZ - : LIS2MDL_ODR_50HZ; + reg_val = rate < 20000 ? LIS2MDL_ODR_10HZ : + rate < 50000 ? LIS2MDL_ODR_20HZ : + LIS2MDL_ODR_50HZ; } - normalized_rate = rate <= 0 ? 0 - : reg_val == LIS2MDL_ODR_10HZ ? 10000 - : reg_val == LIS2MDL_ODR_20HZ ? 20000 - : 50000; + normalized_rate = rate <= 0 ? 0 : + reg_val == LIS2MDL_ODR_10HZ ? 10000 : + reg_val == LIS2MDL_ODR_20HZ ? 20000 : + 50000; /* * If no change is needed just bail. Not doing so will require a reset @@ -356,10 +350,9 @@ int lis2mdl_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) init_mag_cal(cal); if (normalized_rate > 0) - cal->batch_size = MAX( - MAG_CAL_MIN_BATCH_SIZE, - (normalized_rate * 1000) / - MAG_CAL_MIN_BATCH_WINDOW_US); + cal->batch_size = MAX(MAG_CAL_MIN_BATCH_SIZE, + (normalized_rate * 1000) / + MAG_CAL_MIN_BATCH_WINDOW_US); else cal->batch_size = 0; -- cgit v1.2.1 From 58aa72d38ee8fdaea080bde6b3ef0e6921f6f685 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:57 -0600 Subject: board/aleena/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iadb2973ea5ec62ee8fc514ca3424d413346d7b1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727101 Reviewed-by: Jeremy Bettis --- board/aleena/led.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/board/aleena/led.c b/board/aleena/led.c index 4774a39045..f2fdbc2b80 100644 --- a/board/aleena/led.c +++ b/board/aleena/led.c @@ -10,10 +10,10 @@ #include "hooks.h" #include "console.h" -#define CPRINTS(format, args...) cprints(CC_HOOK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOOK, format, ##args) -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -29,18 +29,24 @@ static enum gpio_signal led_blue = GPIO_BAT_LED_2_L; /* Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; @@ -48,10 +54,9 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); static void board_led_init(void) { - int board_id = - (gpio_get_level(GPIO_BOARD_VERSION3) << 2) | - (gpio_get_level(GPIO_BOARD_VERSION2) << 1) | - (gpio_get_level(GPIO_BOARD_VERSION1) << 0); + int board_id = (gpio_get_level(GPIO_BOARD_VERSION3) << 2) | + (gpio_get_level(GPIO_BOARD_VERSION2) << 1) | + (gpio_get_level(GPIO_BOARD_VERSION1) << 0); CPRINTS("board_id=%d", board_id); @@ -60,7 +65,6 @@ static void board_led_init(void) led_blue = GPIO_BAT_LED_1_L; CPRINTS("LED: switch LED"); } - } DECLARE_HOOK(HOOK_INIT, board_led_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 0d7f02fea54ef2fbcb101db1973a327b344930f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:43 -0600 Subject: driver/led/oz554.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieac274a3cc8854174f2736d98f76289672628038 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730002 Reviewed-by: Jeremy Bettis --- driver/led/oz554.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/driver/led/oz554.c b/driver/led/oz554.c index 4b661a592c..9f898b9daf 100644 --- a/driver/led/oz554.c +++ b/driver/led/oz554.c @@ -13,10 +13,10 @@ #include "task.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) -#define I2C_ADDR_OZ554_FLAGS 0x31 +#define I2C_ADDR_OZ554_FLAGS 0x31 struct oz554_value { uint8_t offset; @@ -40,38 +40,38 @@ static struct oz554_value oz554_conf[] = { * Frequency selection: 300(KHz) * Short circuit protection: 8(V) */ - {.offset = 1, .data = 0x43}, + { .offset = 1, .data = 0x43 }, /* * Reigster 0x02: LED current amplitude control * ISET Resistor: 10.2(Kohm) * Maximum LED current: 1636/10.2 = 160.4(mA) * Setting LED current: 65(mA) */ - {.offset = 2, .data = 0x65}, + { .offset = 2, .data = 0x65 }, /* * Reigster 0x03: LED backlight Status * Status function: Read only */ - {.offset = 3, .data = 0x00}, + { .offset = 3, .data = 0x00 }, /* * Reigster 0x04: LED current control with SMBus * SMBus PWM function: None Use */ - {.offset = 4, .data = 0x00}, + { .offset = 4, .data = 0x00 }, /* * Reigster 0x05: OVP, OCP control * Over Current Protection: 0.5(V) * Panel LED Voltage(Max): 47.8(V) * OVP setting: 54(V) */ - {.offset = 5, .data = 0x97}, + { .offset = 5, .data = 0x97 }, /* * Reigster 0x00: Dimming mode and string ON/OFF control * String Selection: 4(Number) * Interface Selection: 1 * Brightness mode: 3 */ - {.offset = 0, .data = 0xF2}, + { .offset = 0, .data = 0xF2 }, }; static const int oz554_conf_size = ARRAY_SIZE(oz554_conf); @@ -80,11 +80,10 @@ static void set_oz554_reg(void) int i; for (i = 0; i < oz554_conf_size; ++i) { - int rv = i2c_write8(I2C_PORT_BACKLIGHT, - I2C_ADDR_OZ554_FLAGS, + int rv = i2c_write8(I2C_PORT_BACKLIGHT, I2C_ADDR_OZ554_FLAGS, oz554_conf[i].offset, oz554_conf[i].data); if (rv) { - CPRINTS("Write OZ554 register %d failed rv=%d" , i, rv); + CPRINTS("Write OZ554 register %d failed rv=%d", i, rv); return; } } @@ -114,7 +113,7 @@ void oz554_interrupt(enum gpio_signal signal) * |- t2 -| : 1 second is enough */ hook_call_deferred(&backlight_enable_deferred_data, - OZ554_POWER_BACKLIGHT_DELAY); + OZ554_POWER_BACKLIGHT_DELAY); } int oz554_set_config(int offset, int data) -- cgit v1.2.1 From 011ca9d7791c3cf005a28d329b2ae3927831c6d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:23 -0600 Subject: board/kuldax/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e8caf27c6ae24ee7248346097fcee79d6c1f7b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728545 Reviewed-by: Jeremy Bettis --- board/kuldax/board.c | 75 ++++++++++++++++++++++++++-------------------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/board/kuldax/board.c b/board/kuldax/board.c index 631aca2bdd..dff60f4986 100644 --- a/board/kuldax/board.c +++ b/board/kuldax/board.c @@ -27,8 +27,8 @@ #include "fw_config.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -140,21 +140,21 @@ static int32_t base_5v_power_z1; */ /* PP5000_S5 loads */ -#define PWR_S5_BASE_LOAD (5*1431) -#define PWR_S5_FRONT_HIGH (5*1737) -#define PWR_S5_FRONT_LOW (5*1055) -#define PWR_S5_REAR_HIGH (5*1737) -#define PWR_S5_REAR_LOW (5*1055) -#define PWR_S5_HDMI (5*580) -#define PWR_S5_MAX (5*10000) -#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW) -#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW) +#define PWR_S5_BASE_LOAD (5 * 1431) +#define PWR_S5_FRONT_HIGH (5 * 1737) +#define PWR_S5_FRONT_LOW (5 * 1055) +#define PWR_S5_REAR_HIGH (5 * 1737) +#define PWR_S5_REAR_LOW (5 * 1055) +#define PWR_S5_HDMI (5 * 580) +#define PWR_S5_MAX (5 * 10000) +#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW) +#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW) /* PP5000_Z1 loads */ -#define PWR_Z1_BASE_LOAD (5*5) -#define PWR_Z1_C_HIGH (5*3600) -#define PWR_Z1_C_LOW (5*2000) -#define PWR_Z1_MAX (5*9000) +#define PWR_Z1_BASE_LOAD (5 * 5) +#define PWR_Z1_C_HIGH (5 * 3600) +#define PWR_Z1_C_LOW (5 * 2000) +#define PWR_Z1_MAX (5 * 9000) /* * Update the 5V power usage, assuming no throttling, * and invoke the power monitoring. @@ -228,7 +228,7 @@ static void port_ocp_interrupt(enum gpio_signal signal) * only do that if the system is off since it might still brown out. */ -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -328,26 +328,26 @@ void board_overcurrent_event(int port, int is_overcurrented) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A_FRONT BIT(0) -#define THROT_TYPE_A_REAR BIT(1) -#define THROT_TYPE_C0 BIT(2) -#define THROT_TYPE_C1 BIT(3) -#define THROT_TYPE_C2 BIT(4) -#define THROT_PROCHOT BIT(5) +#define THROT_TYPE_A_FRONT BIT(0) +#define THROT_TYPE_A_REAR BIT(1) +#define THROT_TYPE_C0 BIT(2) +#define THROT_TYPE_C1 BIT(3) +#define THROT_TYPE_C2 BIT(4) +#define THROT_PROCHOT BIT(5) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -363,8 +363,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -392,7 +391,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -419,8 +418,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -551,24 +549,27 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C0) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); pd_update_contract(0); } if (diff & THROT_TYPE_C1) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(1, rp); tcpm_select_rp_value(1, rp); pd_update_contract(1); } if (diff & THROT_TYPE_C2) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(2, rp); tcpm_select_rp_value(2, rp); -- cgit v1.2.1 From fa9400b1870c8cd315d02dc121f8d8b2e186b280 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:53 -0600 Subject: chip/mt_scp/rv32i_common/ipi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7dc5864e0311de224dd545e2f2de82cd6b0c84b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729359 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/ipi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/mt_scp/rv32i_common/ipi.c b/chip/mt_scp/rv32i_common/ipi.c index a7fc720d42..2361774d58 100644 --- a/chip/mt_scp/rv32i_common/ipi.c +++ b/chip/mt_scp/rv32i_common/ipi.c @@ -177,7 +177,7 @@ static void irq_group7_handler(void) if (SCP_GIPC_IN_SET & GIPC_IN(0)) { ipi_handler(); SCP_GIPC_IN_CLR = GIPC_IN(0); - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); } } -- cgit v1.2.1 From 37458bc358ae4869019add7118752e235e54ea2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:03 -0600 Subject: test/usb_tcpmv2_td_pd_ll_e4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8531567319e556f7e397d06f60df49b3d57c765b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730573 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_ll_e4.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_ll_e4.c b/test/usb_tcpmv2_td_pd_ll_e4.c index cb6aa8e8b6..6908eff649 100644 --- a/test/usb_tcpmv2_td_pd_ll_e4.c +++ b/test/usb_tcpmv2_td_pd_ll_e4.c @@ -31,8 +31,8 @@ static int td_pd_ll_e4(enum pd_data_role data_role) /* * a) Run PROC.PD.E1 Bring-up according to the UUT role. */ - TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), - EC_SUCCESS, "%d"); + TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS, + "%d"); /* * Make sure we are idle. Reject everything that is pending @@ -44,13 +44,11 @@ static int td_pd_ll_e4(enum pd_data_role data_role) * and do not send GoodCrc for nRetryCount + 1 times * (nRetryCount equals 3 since PD 2.1). */ - partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_GET_SINK_CAP, - 0, 0, NULL); + partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_GET_SINK_CAP, 0, 0, NULL); retries = 3; TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, PD_DATA_SINK_CAP, - retries), + retries), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_FAILED); @@ -60,7 +58,7 @@ static int td_pd_ll_e4(enum pd_data_role data_role) */ retries = 3; TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, - 0, retries), + 0, retries), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_FAILED); task_wait_event(1 * MSEC); @@ -68,8 +66,8 @@ static int td_pd_ll_e4(enum pd_data_role data_role) /* * d) Check that the UUT issues a Hard Reset. */ - TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), - TCPCI_MSG_TX_HARD_RESET, "%d"); + TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET, + "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED); mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0); task_wait_event(1 * MSEC); -- cgit v1.2.1 From 20bf24221f49c32c6731259ac1f8c03ad13f5f0a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:02 -0600 Subject: chip/stm32/usb_power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I283408fda98bce440266c3f2b5efbe115de88854 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729578 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_power.c | 276 +++++++++++++++++++++++-------------------------- 1 file changed, 129 insertions(+), 147 deletions(-) diff --git a/chip/stm32/usb_power.c b/chip/stm32/usb_power.c index 3e159d646f..8024239d74 100644 --- a/chip/stm32/usb_power.c +++ b/chip/stm32/usb_power.c @@ -14,7 +14,7 @@ #include "usb_power.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) static int usb_power_init_inas(struct usb_power_config const *config); static int usb_power_read(struct usb_power_config const *config); @@ -42,16 +42,15 @@ void usb_power_deferred_tx(struct usb_power_config const *config) state->reports_xmit_active = state->reports_tail; /* Wait for the next command */ - usb_read_ep(config->endpoint, - config->ep->out_databuffer_max, - config->ep->out_databuffer); + usb_read_ep(config->endpoint, config->ep->out_databuffer_max, + config->ep->out_databuffer); return; } } /* Reset stream */ void usb_power_event(struct usb_power_config const *config, - enum usb_ep_event evt) + enum usb_ep_event evt) { if (evt != USB_EVENT_RESET) return; @@ -68,15 +67,15 @@ void usb_power_event(struct usb_power_config const *config, hook_call_deferred(config->ep->tx_deferred, 0); } - /* Write one or more power records to USB */ static int usb_power_write_line(struct usb_power_config const *config) { struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_tail)); + struct usb_power_report *r = + (struct usb_power_report *)(state->reports_data_area + + (USB_POWER_RECORD_SIZE( + state->ina_count) * + state->reports_tail)); /* status + size + timestamps + power list */ size_t bytes = USB_POWER_RECORD_SIZE(state->ina_count); @@ -89,12 +88,12 @@ static int usb_power_write_line(struct usb_power_config const *config) recordcount = config->state->reports_head - config->state->reports_tail; else - recordcount = state->max_cached - - config->state->reports_tail; + recordcount = + state->max_cached - config->state->reports_tail; state->reports_xmit_active = state->reports_tail; - state->reports_tail = (state->reports_tail + recordcount) % - state->max_cached; + state->reports_tail = + (state->reports_tail + recordcount) % state->max_cached; usb_write_ep(config->endpoint, bytes * recordcount, r); return bytes; @@ -103,7 +102,6 @@ static int usb_power_write_line(struct usb_power_config const *config) return 0; } - static int usb_power_state_reset(struct usb_power_config const *config) { struct usb_power_state *state = config->state; @@ -117,7 +115,6 @@ static int usb_power_state_reset(struct usb_power_config const *config) return USB_POWER_SUCCESS; } - static int usb_power_state_stop(struct usb_power_config const *config) { struct usb_power_state *state = config->state; @@ -137,8 +134,6 @@ static int usb_power_state_stop(struct usb_power_config const *config) return USB_POWER_SUCCESS; } - - static int usb_power_state_start(struct usb_power_config const *config, union usb_power_command_data *cmd, int count) { @@ -182,13 +177,12 @@ static int usb_power_state_start(struct usb_power_config const *config, return USB_POWER_SUCCESS; } - static int usb_power_state_settime(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) + union usb_power_command_data *cmd, int count) { if (count != sizeof(struct usb_power_command_settime)) { - CPRINTS("[SETTIME] Error: count %d is not %d", - (int)count, sizeof(struct usb_power_command_settime)); + CPRINTS("[SETTIME] Error: count %d is not %d", (int)count, + sizeof(struct usb_power_command_settime)); return USB_POWER_ERROR_READ_SIZE; } @@ -201,9 +195,8 @@ static int usb_power_state_settime(struct usb_power_config const *config, return USB_POWER_SUCCESS; } - static int usb_power_state_addina(struct usb_power_config const *config, - union usb_power_command_data *cmd, int count) + union usb_power_command_data *cmd, int count) { struct usb_power_state *state = config->state; struct usb_power_ina_cfg *ina; @@ -217,8 +210,8 @@ static int usb_power_state_addina(struct usb_power_config const *config, } if (count != sizeof(struct usb_power_command_addina)) { - CPRINTS("[ADDINA] Error count %d is not %d", - (int)count, sizeof(struct usb_power_command_addina)); + CPRINTS("[ADDINA] Error count %d is not %d", (int)count, + sizeof(struct usb_power_command_addina)); return USB_POWER_ERROR_READ_SIZE; } @@ -286,8 +279,8 @@ static int usb_power_read(struct usb_power_config const *config) * If there is a USB packet waiting we process it and generate a * response. */ - uint8_t count = rx_ep_pending(config->endpoint); - uint8_t result = USB_POWER_SUCCESS; + uint8_t count = rx_ep_pending(config->endpoint); + uint8_t result = USB_POWER_SUCCESS; union usb_power_command_data *cmd = (union usb_power_command_data *)config->ep->out_databuffer; @@ -314,14 +307,14 @@ static int usb_power_read(struct usb_power_config const *config) result = usb_power_state_start(config, cmd, count); if (result == USB_POWER_SUCCESS) { /* Send back actual integration time. */ - ep->in_databuffer[1] = - (state->integration_us >> 0) & 0xff; - ep->in_databuffer[2] = - (state->integration_us >> 8) & 0xff; - ep->in_databuffer[3] = - (state->integration_us >> 16) & 0xff; - ep->in_databuffer[4] = - (state->integration_us >> 24) & 0xff; + ep->in_databuffer[1] = (state->integration_us >> 0) & + 0xff; + ep->in_databuffer[2] = (state->integration_us >> 8) & + 0xff; + ep->in_databuffer[3] = (state->integration_us >> 16) & + 0xff; + ep->in_databuffer[4] = (state->integration_us >> 24) & + 0xff; in_msgsize += 4; } break; @@ -363,8 +356,6 @@ static int usb_power_read(struct usb_power_config const *config) return EC_SUCCESS; } - - /****************************************************************************** * INA231 interface. * List the registers and fields here. @@ -374,20 +365,19 @@ static int usb_power_read(struct usb_power_config const *config) #define INA231_REG_CONF 0 #define INA231_REG_RSHV 1 #define INA231_REG_BUSV 2 -#define INA231_REG_PWR 3 +#define INA231_REG_PWR 3 #define INA231_REG_CURR 4 -#define INA231_REG_CAL 5 -#define INA231_REG_EN 6 - - -#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) -#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) -#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) -#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) -#define INA231_MODE_OFF 0x0 -#define INA231_MODE_SHUNT 0x5 -#define INA231_MODE_BUS 0x6 -#define INA231_MODE_BOTH 0x7 +#define INA231_REG_CAL 5 +#define INA231_REG_EN 6 + +#define INA231_CONF_AVG(val) (((int)(val & 0x7)) << 9) +#define INA231_CONF_BUS_TIME(val) (((int)(val & 0x7)) << 6) +#define INA231_CONF_SHUNT_TIME(val) (((int)(val & 0x7)) << 3) +#define INA231_CONF_MODE(val) (((int)(val & 0x7)) << 0) +#define INA231_MODE_OFF 0x0 +#define INA231_MODE_SHUNT 0x5 +#define INA231_MODE_BUS 0x6 +#define INA231_MODE_BOTH 0x7 int reg_type_mapping(enum usb_power_ina_type ina_type) { @@ -411,36 +401,32 @@ uint16_t ina2xx_readagain(uint8_t port, uint16_t addr_flags) int res; uint16_t val; - res = i2c_xfer(port, addr_flags, - NULL, 0, (uint8_t *)&val, sizeof(uint16_t)); + res = i2c_xfer(port, addr_flags, NULL, 0, (uint8_t *)&val, + sizeof(uint16_t)); if (res) { - CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", - (int)port, (int)I2C_STRIP_FLAGS(addr_flags)); + CPRINTS("INA2XX I2C readagain failed p:%d a:%02x", (int)port, + (int)I2C_STRIP_FLAGS(addr_flags)); return 0x0bad; } return (val >> 8) | ((val & 0xff) << 8); } - -uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, - uint8_t reg) +uint16_t ina2xx_read(uint8_t port, uint16_t addr_flags, uint8_t reg) { int res; int val; res = i2c_read16(port, addr_flags, reg, &val); if (res) { - CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", - (int)port, (int)I2C_STRIP_FLAGS(addr_flags), - (int)reg); + CPRINTS("INA2XX I2C read failed p:%d a:%02x, r:%02x", (int)port, + (int)I2C_STRIP_FLAGS(addr_flags), (int)reg); return 0x0bad; } return (val >> 8) | ((val & 0xff) << 8); } -int ina2xx_write(uint8_t port, uint16_t addr_flags, - uint8_t reg, uint16_t val) +int ina2xx_write(uint8_t port, uint16_t addr_flags, uint8_t reg, uint16_t val) { int res; uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); @@ -451,8 +437,6 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags, return res; } - - /****************************************************************************** * Background tasks * @@ -462,11 +446,10 @@ int ina2xx_write(uint8_t port, uint16_t addr_flags, */ /* INA231 integration and averaging time presets, indexed by register value */ -#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) -static const int average_settings[] = { - 1, 4, 16, 64, 128, 256, 512, 1024}; -static const int conversion_time_us[] = { - 140, 204, 332, 588, 1100, 2116, 4156, 8244}; +#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) +static const int average_settings[] = { 1, 4, 16, 64, 128, 256, 512, 1024 }; +static const int conversion_time_us[] = { 140, 204, 332, 588, + 1100, 2116, 4156, 8244 }; static int usb_power_init_inas(struct usb_power_config const *config) { @@ -491,8 +474,7 @@ static int usb_power_init_inas(struct usb_power_config const *config) /* Find an averaging setting from the INA presets that fits. */ while (avg < (NELEMS(average_settings) - 1)) { if ((conversion_time_us[shunt_time] * - average_settings[avg + 1]) - > target_us) + average_settings[avg + 1]) > target_us) break; avg++; } @@ -507,15 +489,15 @@ static int usb_power_init_inas(struct usb_power_config const *config) #ifdef USB_POWER_VERBOSE { - int conf, cal; - - conf = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - cal = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - conf, cal); + int conf, cal; + + conf = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CONF); + cal = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CAL); + CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, cal:%x", i, + ina->port, I2C_STRIP_FLAGS(ina->addr_flags), + conf, cal); } #endif /* @@ -536,54 +518,53 @@ static int usb_power_init_inas(struct usb_power_config const *config) if (ina->scale == 0) return -1; value = (5120000 * 100) / (ina->scale * ina->rs); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CAL, value); + ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CAL, + value); if (ret != EC_SUCCESS) { CPRINTS("[CAP] usb_power_init_inas CAL FAIL: %d", ret); return ret; } #ifdef USB_POWER_VERBOSE { - int actual; + int actual; - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CAL); - CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", - ina->scale / 100, ina->scale*25/100, value, actual); + actual = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CAL); + CPRINTS("[CAP] scale: %d uA/div, %d uW/div, cal:%x act:%x", + ina->scale / 100, ina->scale * 25 / 100, value, + actual); } #endif /* Conversion time, shunt + bus, set average. */ value = INA231_CONF_MODE(INA231_MODE_BOTH) | INA231_CONF_SHUNT_TIME(shunt_time) | - INA231_CONF_BUS_TIME(shunt_time) | - INA231_CONF_AVG(avg); - ret = ina2xx_write(ina->port, ina->addr_flags, - INA231_REG_CONF, value); + INA231_CONF_BUS_TIME(shunt_time) | INA231_CONF_AVG(avg); + ret = ina2xx_write(ina->port, ina->addr_flags, INA231_REG_CONF, + value); if (ret != EC_SUCCESS) { CPRINTS("[CAP] usb_power_init_inas CONF FAIL: %d", ret); return ret; } #ifdef USB_POWER_VERBOSE { - int actual; + int actual; - actual = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CONF); - CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - value, actual); + actual = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CONF); + CPRINTS("[CAP] %d (%d,0x%02x): conf:%x, act:%x", i, + ina->port, I2C_STRIP_FLAGS(ina->addr_flags), + value, actual); } #endif #ifdef USB_POWER_VERBOSE { - int busv_mv = - (ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV) - * 125) / 100; - - CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - busv_mv); + int busv_mv = (ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_BUSV) * + 125) / + 100; + + CPRINTS("[CAP] %d (%d,0x%02x): busv:%dmv", i, ina->port, + I2C_STRIP_FLAGS(ina->addr_flags), busv_mv); } #endif /* Initialize read from power register. This register address @@ -600,7 +581,6 @@ static int usb_power_init_inas(struct usb_power_config const *config) return EC_SUCCESS; } - /* * Read each INA's power integration measurement. * @@ -614,19 +594,20 @@ static int usb_power_get_samples(struct usb_power_config const *config) { uint64_t time = get_time().val; struct usb_power_state *state = config->state; - struct usb_power_report *r = (struct usb_power_report *)( - state->reports_data_area + - (USB_POWER_RECORD_SIZE(state->ina_count) - * state->reports_head)); + struct usb_power_report *r = + (struct usb_power_report *)(state->reports_data_area + + (USB_POWER_RECORD_SIZE( + state->ina_count) * + state->reports_head)); struct usb_power_ina_cfg *inas = state->ina_cfg; int i; /* TODO(nsanders): Would we prefer to evict oldest? */ - if (((state->reports_head + 1) % USB_POWER_MAX_CACHED(state->ina_count)) - == state->reports_xmit_active) { - CPRINTS("Overflow! h:%d a:%d t:%d (%d)", - state->reports_head, state->reports_xmit_active, - state->reports_tail, + if (((state->reports_head + 1) % + USB_POWER_MAX_CACHED(state->ina_count)) == + state->reports_xmit_active) { + CPRINTS("Overflow! h:%d a:%d t:%d (%d)", state->reports_head, + state->reports_xmit_active, state->reports_tail, USB_POWER_MAX_CACHED(state->ina_count)); return USB_POWER_ERROR_OVERFLOW; } @@ -650,47 +631,48 @@ static int usb_power_get_samples(struct usb_power_config const *config) */ if (ina->shared) regval = ina2xx_read(ina->port, ina->addr_flags, - reg_type_mapping(ina->type)); + reg_type_mapping(ina->type)); else - regval = ina2xx_readagain(ina->port, - ina->addr_flags); + regval = ina2xx_readagain(ina->port, ina->addr_flags); r->power[i] = regval; #ifdef USB_POWER_VERBOSE { - int current; - int power; - int voltage; - int bvoltage; - - voltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_RSHV); - bvoltage = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_BUSV); - current = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_CURR); - power = ina2xx_read(ina->port, ina->addr_flags, - INA231_REG_PWR); - { - int uV = ((int)voltage * 25) / 10; - int mV = ((int)bvoltage * 125) / 100; - int uA = (uV * 1000) / ina->rs; - int CuA = (((int)current * ina->scale) / 100); - int uW = (((int)power * ina->scale*25)/100); - - CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", - i, ina->port, I2C_STRIP_FLAGS(ina->addr_flags), - uV/1000, ina->rs, uA/1000); - CPRINTS("[CAP] %duV %dmV %duA %dCuA " - "%duW v:%04x, b:%04x, p:%04x", - uV, mV, uA, CuA, uW, voltage, bvoltage, power); - } + int current; + int power; + int voltage; + int bvoltage; + + voltage = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_RSHV); + bvoltage = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_BUSV); + current = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_CURR); + power = ina2xx_read(ina->port, ina->addr_flags, + INA231_REG_PWR); + { + int uV = ((int)voltage * 25) / 10; + int mV = ((int)bvoltage * 125) / 100; + int uA = (uV * 1000) / ina->rs; + int CuA = (((int)current * ina->scale) / 100); + int uW = (((int)power * ina->scale * 25) / 100); + + CPRINTS("[CAP] %d (%d,0x%02x): %dmV / %dmO = %dmA", + i, ina->port, + I2C_STRIP_FLAGS(ina->addr_flags), + uV / 1000, ina->rs, uA / 1000); + CPRINTS("[CAP] %duV %dmV %duA %dCuA " + "%duW v:%04x, b:%04x, p:%04x", + uV, mV, uA, CuA, uW, voltage, bvoltage, + power); + } } #endif } /* Mark this slot as used. */ state->reports_head = (state->reports_head + 1) % - USB_POWER_MAX_CACHED(state->ina_count); + USB_POWER_MAX_CACHED(state->ina_count); return EC_SUCCESS; } -- cgit v1.2.1 From 4db6d29ac9b0ea86e315d9d7f0dbf4412fbd4d6b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:30 -0600 Subject: chip/npcx/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2b669a38694fe827a157f11f29450ccff3a8f66b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729398 Reviewed-by: Jeremy Bettis --- chip/npcx/hwtimer.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index b479f237c0..324fadcabb 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -19,10 +19,10 @@ #include "util.h" /* Depth of event timer */ -#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */ -#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */ +#define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */ +#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */ #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */ -#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */ +#define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */ /* Time when event will be expired unit:us */ static volatile uint32_t evt_expired_us; @@ -39,7 +39,7 @@ static volatile uint32_t cur_cnt_us_dbg; #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) #endif /*****************************************************************************/ @@ -48,7 +48,7 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source) { /* Select which clock to use for this timer */ UPDATE_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_CKSEL, - source != ITIM_SOURCE_CLOCK_APB2); + source != ITIM_SOURCE_CLOCK_APB2); /* Clear timeout status */ SET_BIT(NPCX_ITCTS(itim_no), NPCX_ITCTS_TO_STS); @@ -64,8 +64,8 @@ void init_hw_timer(int itim_no, enum ITIM_SOURCE_CLOCK_T source) /* HWTimer event handlers */ void __hw_clock_event_set(uint32_t deadline) { - fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK/(float)SECOND); - int32_t evt_cnt_us; + fp_t inv_evt_tick = FLOAT_TO_FP(INT_32K_CLOCK / (float)SECOND); + int32_t evt_cnt_us; /* Is deadline min value? */ if (evt_expired_us != 0 && evt_expired_us < deadline) return; @@ -87,10 +87,10 @@ void __hw_clock_event_set(uint32_t deadline) * ITIM count down : event expired : Unit: 1/32768 sec * It must exceed evt_expired_us for process_timers function */ - evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us) * inv_evt_tick); + evt_cnt = FP_TO_INT((fp_inter_t)(evt_cnt_us)*inv_evt_tick); if (evt_cnt > TICK_EVT_MAX_CNT) { - CPRINTS("Event overflow! 0x%08x, us is %d", - evt_cnt, evt_cnt_us); + CPRINTS("Event overflow! 0x%08x, us is %d", evt_cnt, + evt_cnt_us); evt_cnt = TICK_EVT_MAX_CNT; } @@ -136,16 +136,17 @@ uint16_t __hw_clock_event_count(void) /* Returns time delay cause of deep idle */ uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt) { - fp_t evt_tick = FLOAT_TO_FP(SECOND/(float)INT_32K_CLOCK); + fp_t evt_tick = FLOAT_TO_FP(SECOND / (float)INT_32K_CLOCK); uint32_t sleep_time; uint16_t cnt = __hw_clock_event_count(); /* Event has been triggered but timer ISR doesn't handle it */ if (IS_BIT_SET(NPCX_ITCTS(ITIM_EVENT_NO), NPCX_ITCTS_TO_STS)) - sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1) * evt_tick); + sleep_time = + FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1) * evt_tick); /* Event hasn't been triggered */ else - sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt+1 - cnt) * + sleep_time = FP_TO_INT((fp_inter_t)(pre_evt_cnt + 1 - cnt) * evt_tick); return sleep_time; @@ -194,7 +195,6 @@ static void __hw_clock_event_irq(void) if (evt_expired_us == 0) __hw_clock_event_set(EVT_MAX_EXPIRED_US); #endif - } DECLARE_IRQ(ITIM_INT(ITIM_EVENT_NO), __hw_clock_event_irq, 3); @@ -295,10 +295,9 @@ static void update_prescaler(void) * Ttick_unit = (PRE_8+1) * Tapb2_clk * PRE_8 = (Ttick_unit/Tapb2_clk) -1 */ - NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1; + NPCX_ITPRE(ITIM_SYSTEM_NO) = (clock_get_apb2_freq() / SECOND) - 1; /* Set event tick unit = 1/32768 sec */ NPCX_ITPRE(ITIM_EVENT_NO) = 0; - } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); @@ -311,10 +310,10 @@ void __hw_early_init_hwtimer(uint32_t start_t) /* Enable clock for ITIM peripheral */ clock_enable_peripheral(CGC_OFFSET_TIMER, CGC_TIMER_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* init tick & event timer first */ - init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2); + init_hw_timer(ITIM_SYSTEM_NO, ITIM_SOURCE_CLOCK_APB2); init_hw_timer(ITIM_EVENT_NO, ITIM_SOURCE_CLOCK_32K); /* Set initial prescaler */ -- cgit v1.2.1 From ce0393174fce8e7caae666a4667c0ee87e49a64b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:30 -0600 Subject: cts/mutex/th.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0876be7b13b905e53f049f65c8abbd854cbdcfa4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729762 Reviewed-by: Jeremy Bettis --- cts/mutex/th.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cts/mutex/th.c b/cts/mutex/th.c index 9cbbd8badb..3e9a8ca7c2 100644 --- a/cts/mutex/th.c +++ b/cts/mutex/th.c @@ -23,7 +23,7 @@ static struct mutex mtx; int mutex_random_task(void *unused) { - char letter = 'A'+(TASK_ID_MTX3A - task_get_current()); + char letter = 'A' + (TASK_ID_MTX3A - task_get_current()); /* wait to be activated */ while (1) { -- cgit v1.2.1 From 3ed900c683c2b27544b08d9b7105079fbb71bbcb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:47 -0600 Subject: chip/stm32/config-stm32h7x3.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib70381c21bfa26de57df1cc8c88034813dbfcba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729478 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32h7x3.h | 48 +++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index 11da24b849..f08efbe17e 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -4,17 +4,17 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) -#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_ERASE_SIZE (128 * 1024) /* erase bank size */ /* always use 256-bit writes due to ECC */ -#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 +#define CONFIG_FLASH_WRITE_SIZE 32 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 32 /* * What the code is calling 'bank' is really the size of the block used for * write-protected, here it's 128KB sector (same as erase size). */ -#define CONFIG_FLASH_BANK_SIZE (128 * 1024) +#define CONFIG_FLASH_BANK_SIZE (128 * 1024) /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -27,28 +27,28 @@ /* (D2) AHB-SRAM3: 32kB 0x30040000 - 0x30047FFF */ /* (D3) AHB-SRAM4: 64kB 0x38000000 - 0x3800FFFF */ /* (D3) backup RAM: 4kB 0x38800000 - 0x38800FFF */ -#define CONFIG_RAM_BASE 0x24000000 -#define CONFIG_RAM_SIZE 0x00080000 +#define CONFIG_RAM_BASE 0x24000000 +#define CONFIG_RAM_SIZE 0x00080000 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (512 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (128 * 1024) +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_SIZE (512 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* * Cannot use PSTATE: @@ -58,7 +58,7 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 150 +#define CONFIG_IRQ_COUNT 150 /* the Cortex-M7 core has 'standard' ARMv7-M caches */ #define CONFIG_ARMV7M_CACHE @@ -68,9 +68,9 @@ #define CONFIG_CHIP_UNCACHED_REGION ahb4 /* Override MPU attribute settings to match the chip requirements */ /* Code is Normal memory type / non-shareable / write-through */ -#define MPU_ATTR_FLASH_MEMORY 0x02 +#define MPU_ATTR_FLASH_MEMORY 0x02 /* SRAM Data is Normal memory type / non-shareable / write-back, write-alloc */ #define MPU_ATTR_INTERNAL_SRAM 0x0B /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 -- cgit v1.2.1 From 9b8ac31c994905888548e74862ba7ab24219e600 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:43 -0600 Subject: board/cret/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a96aa4c992dfd6e844945f6cbf9f473916e322f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728207 Reviewed-by: Jeremy Bettis --- board/cret/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cret/cbi_ssfc.c b/board/cret/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/cret/cbi_ssfc.c +++ b/board/cret/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From d44af7d1751aaead95fd60fea93b0feec996b6d0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:29 -0600 Subject: baseboard/zork/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I770f47b197ef077ccfb7c1804fa92baebf980b2a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727954 Reviewed-by: Jeremy Bettis --- baseboard/zork/baseboard.c | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c index 0b48d1075b..d10f8a4190 100644 --- a/baseboard/zork/baseboard.c +++ b/baseboard/zork/baseboard.c @@ -59,15 +59,15 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* * In the AOZ1380 PPC, there are no programmable features. We use * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -__overridable int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +__overridable int +board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; @@ -96,11 +96,10 @@ static void baseboard_chipset_resume(void) DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /* Keyboard scan setting */ @@ -134,19 +133,19 @@ __override struct keyboard_scan_config keyscan_config = { * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. */ const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} + { 2761 / THERMISTOR_SCALING_FACTOR, 0 }, + { 2492 / THERMISTOR_SCALING_FACTOR, 10 }, + { 2167 / THERMISTOR_SCALING_FACTOR, 20 }, + { 1812 / THERMISTOR_SCALING_FACTOR, 30 }, + { 1462 / THERMISTOR_SCALING_FACTOR, 40 }, + { 1146 / THERMISTOR_SCALING_FACTOR, 50 }, + { 878 / THERMISTOR_SCALING_FACTOR, 60 }, + { 665 / THERMISTOR_SCALING_FACTOR, 70 }, + { 500 / THERMISTOR_SCALING_FACTOR, 80 }, + { 434 / THERMISTOR_SCALING_FACTOR, 85 }, + { 376 / THERMISTOR_SCALING_FACTOR, 90 }, + { 326 / THERMISTOR_SCALING_FACTOR, 95 }, + { 283 / THERMISTOR_SCALING_FACTOR, 100 } }; const struct thermistor_info thermistor_info = { @@ -293,8 +292,7 @@ static int command_temps_log(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, - "seconds", +DECLARE_CONSOLE_COMMAND(tempslog, command_temps_log, "seconds", "Print temp sensors periodically"); /* -- cgit v1.2.1 From cc96b4516df440f77bf97542565d65ab15daf760 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:26 -0600 Subject: board/npcx7_evb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id86e62cb38cc061b87fd268d1e6a2d8f15b052e6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728766 Reviewed-by: Jeremy Bettis --- board/npcx7_evb/board.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/board/npcx7_evb/board.h b/board/npcx7_evb/board.h index ab8b850d94..498ca6a9e8 100644 --- a/board/npcx7_evb/board.h +++ b/board/npcx7_evb/board.h @@ -15,11 +15,11 @@ * npcx7m6f/npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc */ #if defined(CHIP_VARIANT_NPCX7M6G) -#define BOARD_VERSION 1 -#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ +#define BOARD_VERSION 1 +#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \ defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) -#define BOARD_VERSION 2 +#define BOARD_VERSION 2 #endif /* EC modules */ @@ -39,9 +39,9 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ #define CONFIG_POWER_BUTTON -#undef CONFIG_PSTORE +#undef CONFIG_PSTORE #define CONFIG_PWM_KBLIGHT #define CONFIG_VBOOT_HASH #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */ @@ -57,7 +57,7 @@ /* I2C port for CONFIG_CMD_I2CWEDGE */ #define I2C_PORT_MASTER NPCX_I2C_PORT0_0 -#define I2C_PORT_HOST 0 +#define I2C_PORT_HOST 0 /* Fans for testing */ #define CONFIG_FANS 1 @@ -95,20 +95,20 @@ /* Select which UART Controller is the Console UART */ #undef CONFIG_CONSOLE_UART -#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ +#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ /* * This definition below actually doesn't define which UART controller to be * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are * connected to "UART1" controller. */ #if (BOARD_VERSION == 2) -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ #else -#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */ +#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 as UART1 */ #endif -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ -#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX7_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 (only in npcx7) */ #ifndef __ASSEMBLER__ -- cgit v1.2.1 From ac796e6f82b4277448ff4f01f1174f380aabbe67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:24 -0600 Subject: common/vstore.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I840193e9e1b07db7c681a1d1d4afefee2a23da9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729813 Reviewed-by: Jeremy Bettis --- common/vstore.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/vstore.c b/common/vstore.c index 9b4636397c..085c7b81c9 100644 --- a/common/vstore.c +++ b/common/vstore.c @@ -22,7 +22,7 @@ #include "system.h" #include "util.h" -#define VSTORE_SYSJUMP_TAG 0x5653 /* "VS" */ +#define VSTORE_SYSJUMP_TAG 0x5653 /* "VS" */ #define VSTORE_HOOK_VERSION 1 struct vstore_slot { @@ -32,7 +32,7 @@ struct vstore_slot { static struct vstore_slot vstore_slots[CONFIG_VSTORE_SLOT_COUNT]; static const int vstore_size = - sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT; + sizeof(struct vstore_slot) * CONFIG_VSTORE_SLOT_COUNT; BUILD_ASSERT(ARRAY_SIZE(vstore_slots) <= EC_VSTORE_SLOT_MAX); /* -- cgit v1.2.1 From d05f0e251ec2ff24d97afce112caea4303e9e5a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:13 -0600 Subject: board/elm/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a8562b8f9cab9113fd60b882a3dc6beabe7dd00 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728312 Reviewed-by: Jeremy Bettis --- board/elm/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/elm/usb_pd_policy.c b/board/elm/usb_pd_policy.c index 2eeab736d9..8165caeb4e 100644 --- a/board/elm/usb_pd_policy.c +++ b/board/elm/usb_pd_policy.c @@ -21,8 +21,8 @@ #include "usb_mux.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { -- cgit v1.2.1 From 44b5cf1df3efc92f23efed585b877c78425e8d06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:24 -0600 Subject: board/waddledoo/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0cccb4831b419727d4b3ce03ff6d2a1fc00d5531 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729110 Reviewed-by: Jeremy Bettis --- board/waddledoo/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledoo/usb_pd_policy.c b/board/waddledoo/usb_pd_policy.c index 3190595596..9edc5a181d 100644 --- a/board/waddledoo/usb_pd_policy.c +++ b/board/waddledoo/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From e151701e5ae0058fa52bce622aea73a0abd7cdfb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:53 -0600 Subject: core/cortex-m/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2ee2c076a6c87b8919373d40de44bb2e03fd91ae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729825 Reviewed-by: Jeremy Bettis --- core/cortex-m/panic.c | 69 +++++++++++++++++++++++++-------------------------- 1 file changed, 34 insertions(+), 35 deletions(-) diff --git a/core/cortex-m/panic.c b/core/cortex-m/panic.c index 2f71080392..dba403d130 100644 --- a/core/cortex-m/panic.c +++ b/core/cortex-m/panic.c @@ -20,9 +20,8 @@ /* Whether bus fault is ignored */ static int bus_fault_ignored; - /* Panic data goes at the end of RAM. */ -static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; +static struct panic_data *const pdata_ptr = PANIC_DATA_PTR; /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */ static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7; @@ -77,7 +76,7 @@ static int32_t is_frame_in_handler_stack(const uint32_t exc_return) #ifdef CONFIG_DEBUG_EXCEPTIONS /* Names for each of the bits in the cfs register, starting at bit 0 */ -static const char * const cfsr_name[32] = { +static const char *const cfsr_name[32] = { /* MMFSR */ [0] = "Instruction access violation", [1] = "Data access violation", @@ -101,11 +100,9 @@ static const char * const cfsr_name[32] = { }; /* Names for the first 5 bits in the DFSR */ -static const char * const dfsr_name[] = { - "Halt request", - "Breakpoint", - "Data watchpoint/trace", - "Vector catch", +static const char *const dfsr_name[] = { + "Halt request", "Breakpoint", + "Data watchpoint/trace", "Vector catch", "External debug request", }; @@ -281,7 +278,7 @@ void panic_data_print(const struct panic_data *pdata) print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12); print_reg(13, lregs, in_handler ? CORTEX_PANIC_REGISTER_MSP : - CORTEX_PANIC_REGISTER_PSP); + CORTEX_PANIC_REGISTER_PSP); print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR); print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC); @@ -310,24 +307,23 @@ void __keep report_panic(void) sp = is_frame_in_handler_stack( pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ? pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] : - pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; + pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; /* If stack is valid, copy exception frame to pdata */ - if ((sp & 3) == 0 && - sp >= CONFIG_RAM_BASE && + if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE && sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) { const uint32_t *sregs = (const uint32_t *)sp; int i; /* Skip r0-r3 and r12 registers if necessary */ for (i = CORTEX_PANIC_FRAME_REGISTER_R0; - i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++) + i <= CORTEX_PANIC_FRAME_REGISTER_R12; i++) if (IS_ENABLED(CONFIG_PANIC_STRIP_GPR)) pdata->cm.frame[i] = 0; else pdata->cm.frame[i] = sregs[i]; for (i = CORTEX_PANIC_FRAME_REGISTER_LR; - i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++) + i < NUM_CORTEX_PANIC_FRAME_REGISTERS; i++) pdata->cm.frame[i] = sregs[i]; pdata->flags |= PANIC_DATA_FLAG_FRAME_VALID; @@ -401,38 +397,41 @@ void exception_panic(void) #endif "stmia %[pregs], {r1-r11, lr}\n" "mov sp, %[pstack]\n" - "bl report_panic\n" : : - [pregs] "r" (pdata_ptr->cm.regs), - [pstack] "r" (pstack_addr) : - /* Constraints protecting these from being clobbered. - * Gcc should be using r0 & r12 for pregs and pstack. */ - "r1", "r2", "r3", "r4", "r5", "r6", - /* clang warns that we're clobbering a reserved register: - * inline asm clobber list contains reserved registers: R7 - * [-Werror,-Winline-asm]. The intent of the clobber list is - * to force pregs and pstack to be in R0 and R12, which - * still holds. - */ + "bl report_panic\n" + : + : [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr) + : + /* Constraints protecting these from being clobbered. + * Gcc should be using r0 & r12 for pregs and pstack. */ + "r1", "r2", "r3", "r4", "r5", "r6", + /* clang warns that we're clobbering a reserved register: + * inline asm clobber list contains reserved registers: R7 + * [-Werror,-Winline-asm]. The intent of the clobber list is + * to force pregs and pstack to be in R0 and R12, which + * still holds. + */ #ifndef __clang__ - "r7", + "r7", #endif - "r8", "r9", "r10", "r11", "cc", "memory" - ); + "r8", "r9", "r10", "r11", "cc", "memory"); } #ifdef CONFIG_SOFTWARE_PANIC void software_panic(uint32_t reason, uint32_t info) { - __asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n" - "mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n" - "bl exception_panic\n" - : : "r"(info), "r"(reason)); + __asm__("mov " STRINGIFY( + SOFTWARE_PANIC_INFO_REG) ", %0\n" + "mov " STRINGIFY( + SOFTWARE_PANIC_REASON_REG) ", %1\n" + "bl exception_panic\n" + : + : "r"(info), "r"(reason)); __builtin_unreachable(); } void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t *lregs; lregs = pdata->cm.regs; @@ -452,7 +451,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *lregs; if (pdata && pdata->struct_version == 2) { -- cgit v1.2.1 From 400275d3547418a7cdea853c43ab4eb28ffd91e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:53 -0600 Subject: board/nipperkin/board_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f73139b4643081d48709cf8f90ff33d9a71ea1b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728753 Reviewed-by: Jeremy Bettis --- board/nipperkin/board_fw_config.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/nipperkin/board_fw_config.h b/board/nipperkin/board_fw_config.h index 77306ccb6f..f542892075 100644 --- a/board/nipperkin/board_fw_config.h +++ b/board/nipperkin/board_fw_config.h @@ -13,10 +13,10 @@ /* * Keyboard Backlight (1 bit) */ -#define FW_CONFIG_KBLIGHT_OFFSET 0 -#define FW_CONFIG_KBLIGHT_WIDTH 1 -#define FW_CONFIG_KBLIGHT_NO 0 -#define FW_CONFIG_KBLIGHT_YES 1 +#define FW_CONFIG_KBLIGHT_OFFSET 0 +#define FW_CONFIG_KBLIGHT_WIDTH 1 +#define FW_CONFIG_KBLIGHT_NO 0 +#define FW_CONFIG_KBLIGHT_YES 1 /* * Bit 1 ~ 6 not related to EC function @@ -25,10 +25,10 @@ /* * Keyboard (1 bit) */ -#define FW_CONFIG_KEYBOARD_OFFSET 7 -#define FW_CONFIG_KEYBOARD_WIDTH 1 -#define FW_CONFIG_KEYBOARD_PRIVACY_YES 0 -#define FW_CONFIG_KEYBOARD_PRIVACY_NO 1 +#define FW_CONFIG_KEYBOARD_OFFSET 7 +#define FW_CONFIG_KEYBOARD_WIDTH 1 +#define FW_CONFIG_KEYBOARD_PRIVACY_YES 0 +#define FW_CONFIG_KEYBOARD_PRIVACY_NO 1 bool board_has_privacy_panel(void); -- cgit v1.2.1 From 448ccacba39f54c66150c841f9262b955c957518 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:04 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5e1dc3771d716cc9d10705dbee761afcee8c2f8b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730921 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c index 73d2819a2d..d928bf6f7e 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_chipset_power_state.c @@ -85,8 +85,7 @@ enum power_states_ndsx chipset_pwr_seq_get_state(void) /* * Unable to determine state, force to G3. */ - LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", - sig); + LOG_INF("Unable to determine CPU state (%#x), forcing shutdown", sig); ap_power_force_shutdown(AP_POWER_SHUTDOWN_G3); return SYS_POWER_STATE_G3; } -- cgit v1.2.1 From 726e6262091dc0f7d0f2470c1564c81fdf809dd1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:27 -0600 Subject: board/oak/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icffff71ba091a3c6f90d1533733298c29c93785a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728790 Reviewed-by: Jeremy Bettis --- board/oak/board.h | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/board/oak/board.h b/board/oak/board.h index b40215a7bf..56468b6eaf 100644 --- a/board/oak/board.h +++ b/board/oak/board.h @@ -23,7 +23,7 @@ #endif #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #if BOARD_REV >= OAK_REV5 /* Add for Ambient Light Sensor */ @@ -107,10 +107,10 @@ #define CONFIG_SPI_CONTROLLER #define CONFIG_STM_HWTIMER32 #define CONFIG_VBOOT_HASH -#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_WATCHDOG_HELP #define CONFIG_SWITCH #define CONFIG_BOARD_VERSION_GPIO -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_TMP432 @@ -149,19 +149,19 @@ #define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C, GPIO_D /* 2 I2C master ports, connect to battery, charger, pd and USB switches */ -#define I2C_PORT_MASTER 0 -#define I2C_PORT_ACCEL 0 -#define I2C_PORT_ALS 0 +#define I2C_PORT_MASTER 0 +#define I2C_PORT_ACCEL 0 +#define I2C_PORT_ALS 0 #define I2C_PORT_BATTERY 0 #define I2C_PORT_CHARGER 0 #define I2C_PORT_PERICOM 0 #define I2C_PORT_THERMAL 0 -#define I2C_PORT_PD_MCU 1 +#define I2C_PORT_PD_MCU 1 #define I2C_PORT_USB_MUX 1 -#define I2C_PORT_TCPC 1 +#define I2C_PORT_TCPC 1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* First SPI controller port (SPI2) */ /* Ambient Light Sensor address */ #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS @@ -171,12 +171,12 @@ #define TIM_WATCHDOG 4 /* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)) #include "gpio_signal.h" @@ -194,9 +194,9 @@ enum pwm_channel { }; enum adc_channel { - ADC_PSYS = 0, /* PC1: STM32_AIN(2) */ + ADC_PSYS = 0, /* PC1: STM32_AIN(2) */ ADC_AMON_BMON, /* PC0: STM32_AIN(10) */ - ADC_VBUS, /* PA2: STM32_AIN(11) */ + ADC_VBUS, /* PA2: STM32_AIN(11) */ ADC_CH_COUNT }; @@ -235,16 +235,16 @@ enum als_id { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA CONFIG_CHARGER_MAX_INPUT_CURRENT +#define PD_MAX_VOLTAGE_MV 20000 /* Reset PD MCU */ void board_reset_pd_mcu(void); @@ -256,6 +256,6 @@ void board_typec_dp_on(int port); void board_typec_dp_off(int port, int *dp_flags); void board_typec_dp_set(int port, int level); -#endif /* !__ASSEMBLER__ */ +#endif /* !__ASSEMBLER__ */ -#endif /* __CROS_EC_BOARD_H */ +#endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From f4ab1cb8447d7cc6b6c16ed0003989b1f53834c1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:37 -0600 Subject: zephyr/emul/include/flash_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifad0a3f615bba0abfd528c7c503d976d41d4238e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730701 Reviewed-by: Jeremy Bettis --- zephyr/emul/include/flash_chip.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/emul/include/flash_chip.h b/zephyr/emul/include/flash_chip.h index 0060935b98..e99767f9ab 100644 --- a/zephyr/emul/include/flash_chip.h +++ b/zephyr/emul/include/flash_chip.h @@ -6,11 +6,11 @@ #ifndef __EMUL_INCLUDE_FLASH_CHIP_H #define __EMUL_INCLUDE_FLASH_CHIP_H -#define CONFIG_RO_STORAGE_OFF 0x0 -#define CONFIG_RW_STORAGE_OFF 0x0 -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_RO_STORAGE_OFF 0x0 +#define CONFIG_RW_STORAGE_OFF 0x0 +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE #endif /* __EMUL_INCLUDE_FLASH_CHIP_H */ -- cgit v1.2.1 From a1df99292c7670cda43f626f06441dc911d8eb2a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:41 -0600 Subject: chip/stm32/config-stm32g41xb.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf58ba209e9b20473526c173d37e257732461f46 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729476 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32g41xb.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index d6ec8696fb..5a4d403957 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -17,12 +17,11 @@ * PSTATE in single bank memories with a write size > 4 bytes. */ -#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (128 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE - /* Erasing 128K can take up to 2s, need to defer erase. */ #define CONFIG_FLASH_DEFERRED_ERASE @@ -37,11 +36,11 @@ * • 10 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased * at 0x2000 5800 address to be accessed by all bus controllers. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 3 +#define I2C_PORT_COUNT 3 /* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */ #define DMAC_COUNT 12 @@ -51,13 +50,13 @@ #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 101 +#define CONFIG_IRQ_COUNT 101 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 -- cgit v1.2.1 From 432ef4a30fd08387b9749dd87726e20e5a1f72ae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:57 -0600 Subject: board/redrix/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idb6f7b37987c69b482bff92bca19fbd6b765d96f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728857 Reviewed-by: Jeremy Bettis --- board/redrix/charger.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/redrix/charger.c diff --git a/board/redrix/charger.c b/board/redrix/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/redrix/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/redrix/charger.c b/board/redrix/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/redrix/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From b1034a5556fa37bd7668a4dc52fac3622421bc62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:45 -0600 Subject: chip/npcx/spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e5e326f4f165ae09675875922b58407d4423576 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729435 Reviewed-by: Jeremy Bettis --- chip/npcx/spi.c | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/chip/npcx/spi.c b/chip/npcx/spi.c index 55fa8f85ab..03c394d1f6 100644 --- a/chip/npcx/spi.c +++ b/chip/npcx/spi.c @@ -22,11 +22,11 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #endif /* SPI IP as SPI controller */ -#define SPI_CLK 8000000 +#define SPI_CLK 8000000 /** * Clear SPI data buffer. * @@ -49,19 +49,20 @@ static void clear_databuf(void) */ void spi_freq_changed(void) { - uint8_t prescaler_divider = 0; + uint8_t prescaler_divider = 0; /* Set clock prescaler divider to SPI module*/ - prescaler_divider = (uint8_t)((uint32_t)clock_get_apb2_freq() - / 2 / SPI_CLK); + prescaler_divider = + (uint8_t)((uint32_t)clock_get_apb2_freq() / 2 / SPI_CLK); if (prescaler_divider >= 1) prescaler_divider = prescaler_divider - 1; if (prescaler_divider > 0x7F) prescaler_divider = 0x7F; /* Set core clock division factor in order to obtain the SPI clock */ - NPCX_SPI_CTL1 = (NPCX_SPI_CTL1&(~(((1<<7)-1)<gpio_cs; @@ -143,7 +143,7 @@ int spi_transaction(const struct spi_device_t *spi_device, while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY)) ; /* Write the data */ - NPCX_SPI_DATA = txdata[i]; + NPCX_SPI_DATA = txdata[i]; CPRINTS("txdata[i]=%x", txdata[i]); /* Waiting till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) @@ -158,7 +158,7 @@ int spi_transaction(const struct spi_device_t *spi_device, while (IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_BSY)) ; /* Write the (unused) data */ - NPCX_SPI_DATA = 0; + NPCX_SPI_DATA = 0; /* Wait till reading is finished */ while (!IS_BIT_SET(NPCX_SPI_STAT, NPCX_SPI_STAT_RBF)) ; @@ -184,7 +184,7 @@ static void spi_init(void) int i; /* Enable clock for SPI peripheral */ clock_enable_peripheral(CGC_OFFSET_SPI, CGC_SPI_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Disabling spi module */ for (i = 0; i < spi_devices_used; i++) @@ -205,8 +205,8 @@ static void spi_init(void) CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SCIDL); CPRINTS("nSPI_COMP=%x", IS_BIT_SET(NPCX_STRPST, NPCX_STRPST_SPI_COMP)); - CPRINTS("SPI_SP_SEL=%x", IS_BIT_SET(NPCX_DEV_CTL4, - NPCX_DEV_CTL4_SPI_SP_SEL)); + CPRINTS("SPI_SP_SEL=%x", + IS_BIT_SET(NPCX_DEV_CTL4, NPCX_DEV_CTL4_SPI_SP_SEL)); /* Cleaning junk data in the buffer */ clear_databuf(); } @@ -216,7 +216,7 @@ DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_INIT_SPI); /* Console commands */ #ifdef CONFIG_CMD_SPI_FLASH static int printrx(const char *desc, const uint8_t *txdata, int txlen, - int rxlen) + int rxlen) { uint8_t rxdata[32]; int rv; @@ -235,11 +235,11 @@ static int printrx(const char *desc, const uint8_t *txdata, int txlen, static int command_spirom(int argc, char **argv) { - uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00}; - uint8_t txjedec[] = {0x9f}; - uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00}; - uint8_t txsr1[] = {0x05}; - uint8_t txsr2[] = {0x35}; + uint8_t txmandev[] = { 0x90, 0x00, 0x00, 0x00 }; + uint8_t txjedec[] = { 0x9f }; + uint8_t txunique[] = { 0x4b, 0x00, 0x00, 0x00, 0x00 }; + uint8_t txsr1[] = { 0x05 }; + uint8_t txsr2[] = { 0x35 }; spi_enable(SPI_FLASH_DEVICE, 1); @@ -253,7 +253,6 @@ static int command_spirom(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(spirom, command_spirom, - NULL, - "Test reading SPI EEPROM"); +DECLARE_CONSOLE_COMMAND(spirom, command_spirom, NULL, + "Test reading SPI EEPROM"); #endif -- cgit v1.2.1 From 63f0fb69f6b7bcde6d8535095ba081ac3a2c45c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:47 -0600 Subject: board/primus/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0604abbb7b56cffa5b11247d86112173ee5ffbbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728845 Reviewed-by: Jeremy Bettis --- board/primus/thermal.c | 64 +++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 34 deletions(-) diff --git a/board/primus/thermal.c b/board/primus/thermal.c index f5e200b14c..be6ced03f0 100644 --- a/board/primus/thermal.c +++ b/board/primus/thermal.c @@ -14,9 +14,7 @@ #include "util.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) - - +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -36,51 +34,51 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {40, -1, -1, -1, -1}, - .off = {0, -1, -1, -1, -1}, - .rpm = {0}, + .on = { 40, -1, -1, -1, -1 }, + .off = { 0, -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {42, -1, -1, -1, -1}, - .off = {40, -1, -1, -1, -1}, - .rpm = {1800}, + .on = { 42, -1, -1, -1, -1 }, + .off = { 40, -1, -1, -1, -1 }, + .rpm = { 1800 }, }, { /* level 2 */ - .on = {43, -1, -1, -1, -1}, - .off = {42, -1, -1, -1, -1}, - .rpm = {2000}, + .on = { 43, -1, -1, -1, -1 }, + .off = { 42, -1, -1, -1, -1 }, + .rpm = { 2000 }, }, { /* level 3 */ - .on = {44, -1, -1, -1, -1}, - .off = {43, -1, -1, -1, -1}, - .rpm = {2200}, + .on = { 44, -1, -1, -1, -1 }, + .off = { 43, -1, -1, -1, -1 }, + .rpm = { 2200 }, }, { /* level 4 */ - .on = {45, -1, -1, -1, -1}, - .off = {44, -1, -1, -1, -1}, - .rpm = {2500}, + .on = { 45, -1, -1, -1, -1 }, + .off = { 44, -1, -1, -1, -1 }, + .rpm = { 2500 }, }, { /* level 5 */ - .on = {46, -1, -1, -1, -1}, - .off = {45, -1, -1, -1, -1}, - .rpm = {2800}, + .on = { 46, -1, -1, -1, -1 }, + .off = { 45, -1, -1, -1, -1 }, + .rpm = { 2800 }, }, { /* level 6 */ - .on = {47, -1, -1, -1, -1}, - .off = {46, -1, -1, -1, -1}, - .rpm = {3000}, + .on = { 47, -1, -1, -1, -1 }, + .off = { 46, -1, -1, -1, -1 }, + .rpm = { 3000 }, }, { /* level 7 */ - .on = {75, -1, -1, -1, -1}, - .off = {72, -1, -1, -1, -1}, - .rpm = {3200}, + .on = { 75, -1, -1, -1, -1 }, + .off = { 72, -1, -1, -1, -1 }, + .rpm = { 3200 }, }, }; const int num_fan_levels = ARRAY_SIZE(fan_table); @@ -106,17 +104,14 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor) */ if (temp[temp_sensor] < prev_temp[temp_sensor]) { for (i = current_level; i > 0; i--) { - if (temp[temp_sensor] < - fan_table[i].off[temp_sensor]) + if (temp[temp_sensor] < fan_table[i].off[temp_sensor]) current_level = i - 1; else break; } - } else if (temp[temp_sensor] > - prev_temp[temp_sensor]) { + } else if (temp[temp_sensor] > prev_temp[temp_sensor]) { for (i = current_level; i < num_fan_levels; i++) { - if (temp[temp_sensor] > - fan_table[i].on[temp_sensor]) + if (temp[temp_sensor] > fan_table[i].on[temp_sensor]) current_level = i + 1; else break; @@ -148,7 +143,8 @@ void board_override_fan_control(int fan, int *temp) if (chipset_in_state(CHIPSET_STATE_ON)) { fan_set_rpm_mode(FAN_CH(fan), 1); fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_1_DDR_SOC)); + fan_table_to_rpm(FAN_CH(fan), temp, + TEMP_SENSOR_1_DDR_SOC)); } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Stop fan when enter S0ix */ fan_set_rpm_mode(FAN_CH(fan), 1); -- cgit v1.2.1 From 134ffc238e026e99747b852ea1e5066b9c05e26e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:24 -0600 Subject: include/ap_hang_detect.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e5f0bf1e3f3ce8d2950ca320b90b05dd083f24a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730204 Reviewed-by: Jeremy Bettis --- include/ap_hang_detect.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/ap_hang_detect.h b/include/ap_hang_detect.h index 9526bb0a84..c26a9d9166 100644 --- a/include/ap_hang_detect.h +++ b/include/ap_hang_detect.h @@ -17,4 +17,4 @@ */ void hang_detect_stop_on_host_command(void); -#endif /* __CROS_EC_AP_HANG_DETECT_H */ +#endif /* __CROS_EC_AP_HANG_DETECT_H */ -- cgit v1.2.1 From ad2709eef9236b186f7f86cd57cfc87ffd168a7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:02 -0600 Subject: board/redrix/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ied7d270d01c42a8e3f65aba69ab2f2cbe76b90ae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728859 Reviewed-by: Jeremy Bettis --- board/redrix/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/redrix/fw_config.c b/board/redrix/fw_config.c index e59688b17d..aca12c984e 100644 --- a/board/redrix/fw_config.c +++ b/board/redrix/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union redrix_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From a939c33d9c7035d5d5643072aa71e98642c5114e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:50 -0600 Subject: board/casta/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc845bb878c47ee4ef3944b09608f357378d5b03 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728141 Reviewed-by: Jeremy Bettis --- board/casta/led.c | 88 +++++++++++++++++++++++++++++-------------------------- 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/board/casta/led.c b/board/casta/led.c index 2c4cc63f80..cb0518a4e7 100644 --- a/board/casta/led.c +++ b/board/casta/led.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Power and battery LED control for Casta + * Power and battery LED control for Casta */ #include "chipset.h" @@ -12,8 +12,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 1; @@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100; /* Casta : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -55,14 +58,13 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; - } + } - if (color == EC_LED_COLOR_BLUE) - { - gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); + if (color == EC_LED_COLOR_BLUE) { + gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); + gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL); } else { /* LED_OFF and unsupported colors */ @@ -74,17 +76,16 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; - } + } /* Battery leds must be turn off when blue led is on * because casta has 3-in-1 led. */ - if(!gpio_get_level(GPIO_PWR_LED_BLUE_L)) - { + if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/ - gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/ + gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/ return; } @@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]); - gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]); + gpio_set_level(GPIO_BAT_LED_GREEN_L, + !brightness[EC_LED_COLOR_GREEN]); + gpio_set_level(GPIO_BAT_LED_RED_L, + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { - gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]); + gpio_set_level(GPIO_PWR_LED_BLUE_L, + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 27029571700293708cb534b5b44e0fcdd73192fd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:41 -0600 Subject: common/peci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e9878349c759bd1040a5162db22655001360e32 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729683 Reviewed-by: Jeremy Bettis --- common/peci.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/common/peci.c b/common/peci.c index e0f03c95dd..dc17f86a56 100644 --- a/common/peci.c +++ b/common/peci.c @@ -13,7 +13,7 @@ static int peci_get_cpu_temp(int *cpu_temp) { int rv; - uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = {0}; + uint8_t r_buf[PECI_GET_TEMP_READ_LENGTH] = { 0 }; struct peci_data peci = { .cmd_code = PECI_CMD_GET_TEMP, .addr = PECI_TARGET_ADDRESS, @@ -74,8 +74,8 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr) #ifdef CONFIG_CMD_PECI static int peci_cmd(int argc, char **argv) { - uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = {0}; - uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = {0}; + uint8_t r_buf[PECI_READ_DATA_FIFO_SIZE] = { 0 }; + uint8_t w_buf[PECI_WRITE_DATA_FIFO_SIZE] = { 0 }; struct peci_data peci = { .w_buf = w_buf, .r_buf = r_buf, @@ -143,8 +143,7 @@ static int peci_cmd(int argc, char **argv) ccprintf("PECI read data: %ph\n", HEX_BUF(r_buf, peci.r_len)); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(peci, peci_cmd, - "addr wlen rlen cmd timeout(us)", +DECLARE_CONSOLE_COMMAND(peci, peci_cmd, "addr wlen rlen cmd timeout(us)", "PECI command"); static int command_peci_temp(int argc, char **argv) @@ -159,7 +158,6 @@ static int command_peci_temp(int argc, char **argv) ccprintf("CPU temp: %d K, %d C\n", t, K_TO_C(t)); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, - NULL, +DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL, "Print CPU temperature"); #endif /* CONFIG_CMD_PECI */ -- cgit v1.2.1 From a4472e0a6b188fe4ee2f1c52ca979552057e2959 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:00 -0600 Subject: zephyr/shim/src/gpio_id.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3cb1c7b3013f42ae594f0b94621e8967aae765a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730893 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/gpio_id.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/zephyr/shim/src/gpio_id.c b/zephyr/shim/src/gpio_id.c index b562f405bc..2329832f7d 100644 --- a/zephyr/shim/src/gpio_id.c +++ b/zephyr/shim/src/gpio_id.c @@ -11,10 +11,8 @@ #include "gpio.h" #include "util.h" -#define IS_BOARD_COMPATIBLE \ - DT_NODE_HAS_COMPAT(DT_PATH(board), cros_ec_gpio_id) -#define IS_SKU_COMPATIBLE \ - DT_NODE_HAS_COMPAT(DT_PATH(sku), cros_ec_gpio_id) +#define IS_BOARD_COMPATIBLE DT_NODE_HAS_COMPAT(DT_PATH(board), cros_ec_gpio_id) +#define IS_SKU_COMPATIBLE DT_NODE_HAS_COMPAT(DT_PATH(sku), cros_ec_gpio_id) #define CONVERT_NUMERAL_SYSTEM_EVAL(system, bits, nbits) \ system##_from_bits(bits, nbits) @@ -32,11 +30,8 @@ __override uint32_t board_get_sku_id(void) static uint32_t sku_id = (uint32_t)-1; if (sku_id == (uint32_t)-1) { - int bits[] = { - DT_FOREACH_PROP_ELEM(DT_PATH(sku), - bits, - READ_PIN_FROM_PHANDLE) - }; + int bits[] = { DT_FOREACH_PROP_ELEM(DT_PATH(sku), bits, + READ_PIN_FROM_PHANDLE) }; if (sizeof(bits) == 0) return (uint32_t)-1; @@ -58,11 +53,8 @@ __override int board_get_version(void) static int board_version = -1; if (board_version == -1) { - int bits[] = { - DT_FOREACH_PROP_ELEM(DT_PATH(board), - bits, - READ_PIN_FROM_PHANDLE) - }; + int bits[] = { DT_FOREACH_PROP_ELEM(DT_PATH(board), bits, + READ_PIN_FROM_PHANDLE) }; if (sizeof(bits) == 0) return -1; -- cgit v1.2.1 From 902109ba45220d5d0defce4890160bdb4dbce50a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:21 -0600 Subject: board/jinlon/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d662602a721bb4215da667eaed6dab9e7be30be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728518 Reviewed-by: Jeremy Bettis --- board/jinlon/board.c | 117 ++++++++++++++++++++++++--------------------------- 1 file changed, 56 insertions(+), 61 deletions(-) diff --git a/board/jinlon/board.c b/board/jinlon/board.c index 58e7e1b427..b5f9f863a3 100644 --- a/board/jinlon/board.c +++ b/board/jinlon/board.c @@ -44,8 +44,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void check_reboot_deferred(void); DECLARE_DEFERRED(check_reboot_deferred); @@ -114,18 +114,19 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_FAN2] = {.channel = 6, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 100 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_FAN2] = { .channel = 6, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -188,17 +189,13 @@ static struct bmi_drv_data_t g_bmi160_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -278,14 +275,14 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_1, /* Use MFT id to control fan */ + .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN2, }; @@ -311,49 +308,48 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, - [MFT_CH_1] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, + [MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_5V_REG", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_CPU", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "5v Reg", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "IR Sensor", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = oti502_get_val, - .idx = OTI502_IDX_OBJECT}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "5v Reg", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "IR Sensor", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = oti502_get_val, + .idx = OTI502_IDX_OBJECT }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Dratini Temperature sensors */ /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -368,8 +364,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -438,8 +434,8 @@ static const struct ec_response_keybd_config keybd2 = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { /* * Future boards should use fw_config instead of SKU ID @@ -487,15 +483,15 @@ void board_overcurrent_event(int port, int is_overcurrented) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif bool board_is_convertible(void) @@ -503,10 +499,9 @@ bool board_is_convertible(void) const uint8_t sku = get_board_sku(); return (sku == 255) || (sku == 1) || (sku == 2) || (sku == 21) || - (sku == 22); + (sku == 22); } - void all_sys_pgood_check_reboot(void) { hook_call_deferred(&check_reboot_deferred_data, 3000 * MSEC); @@ -517,7 +512,7 @@ __override void board_chipset_forced_shutdown(void) hook_call_deferred(&check_reboot_deferred_data, -1); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void check_reboot_deferred(void) { -- cgit v1.2.1 From 3c680b65f04f70a39a14e4d7cd8037bad64037cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:41 -0600 Subject: chip/mec1322/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6becce210abfaca4da53e2e9e76df09af30b09f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729306 Reviewed-by: Jeremy Bettis --- chip/mec1322/config_chip.h | 55 +++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 951de3fb4f..4d61174e68 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -10,15 +10,15 @@ #include "core/cortex-m/config_core.h" /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 93 +#define CONFIG_IRQ_COUNT 93 /* Use a bigger console output buffer */ #undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 +#define CONFIG_UART_TX_BUF_SIZE 2048 /* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL_MS 250 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one @@ -26,8 +26,8 @@ */ #define CONFIG_I2C_MULTI_PORT_CONTROLLER -#define I2C_CONTROLLER_COUNT 4 -#define I2C_PORT_COUNT 5 +#define I2C_CONTROLLER_COUNT 4 +#define I2C_PORT_COUNT 5 /****************************************************************************/ /* Memory mapping */ @@ -45,52 +45,51 @@ /****************************************************************************/ /* Define our RAM layout. */ -#define CONFIG_MEC_SRAM_BASE_START 0x00100000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 -#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_MEC_SRAM_BASE_START) +#define CONFIG_MEC_SRAM_BASE_START 0x00100000 +#define CONFIG_MEC_SRAM_BASE_END 0x00120000 +#define CONFIG_MEC_SRAM_SIZE \ + (CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START) /* 20k RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00005000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_RAM_SIZE) +#define CONFIG_RAM_SIZE 0x00005000 +#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 640 +#define IDLE_TASK_STACK_SIZE 512 +#define LARGER_TASK_STACK_SIZE 640 -#define CHARGER_TASK_STACK_SIZE 640 -#define HOOKS_TASK_STACK_SIZE 640 -#define CONSOLE_TASK_STACK_SIZE 640 -#define HOST_CMD_TASK_STACK_SIZE 640 +#define CHARGER_TASK_STACK_SIZE 640 +#define HOOKS_TASK_STACK_SIZE 640 +#define CONSOLE_TASK_STACK_SIZE 640 +#define HOST_CMD_TASK_STACK_SIZE 640 /* * TODO: Large stack consumption * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 */ -#define PD_TASK_STACK_SIZE 800 +#define PD_TASK_STACK_SIZE 800 /* Default task stack size */ -#define TASK_STACK_SIZE 512 +#define TASK_STACK_SIZE 512 /****************************************************************************/ /* Define our flash layout. */ /* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 +#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 +#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 #include "config_flash_layout.h" @@ -110,4 +109,4 @@ #define GPIO_PIN(index) (index / 10), (1 << (index % 10)) #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From 747ea5039ea5e19fe30e1543e805e3b0c6a8b0a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:10 -0600 Subject: common/vboot_hash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4b277652c96ae03ca4a7d3d351cac0ba567df16 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729809 Reviewed-by: Jeremy Bettis --- common/vboot_hash.c | 55 +++++++++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/common/vboot_hash.c b/common/vboot_hash.c index 33172e7c74..fe32f774eb 100644 --- a/common/vboot_hash.c +++ b/common/vboot_hash.c @@ -23,7 +23,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_VBOOT, outstr) -#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args) +#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args) struct vboot_hash_tag { uint8_t hash[SHA256_DIGEST_SIZE]; @@ -31,8 +31,8 @@ struct vboot_hash_tag { uint32_t size; }; -#define CHUNK_SIZE 1024 /* Bytes to hash per deferred call */ -#define WORK_INTERVAL_US 100 /* Delay between deferred calls */ +#define CHUNK_SIZE 1024 /* Bytes to hash per deferred call */ +#define WORK_INTERVAL_US 100 /* Delay between deferred calls */ /* Check that CHUNK_SIZE fits in shared memory. */ SHARED_MEM_CHECK_SIZE(CHUNK_SIZE); @@ -40,11 +40,11 @@ SHARED_MEM_CHECK_SIZE(CHUNK_SIZE); static uint32_t data_offset; static uint32_t data_size; static uint32_t curr_pos; -static const uint8_t *hash; /* Hash, or NULL if not valid */ +static const uint8_t *hash; /* Hash, or NULL if not valid */ static int want_abort; static int in_progress; -#define VBOOT_HASH_DEFERRED true -#define VBOOT_HASH_BLOCKING false +#define VBOOT_HASH_DEFERRED true +#define VBOOT_HASH_BLOCKING false static struct sha256_ctx ctx; @@ -117,9 +117,10 @@ static void hash_next_chunk(size_t size) { #ifdef CONFIG_MAPPED_STORAGE crec_flash_lock_mapped_storage(1); - SHA256_update(&ctx, (const uint8_t *) - ((uintptr_t)CONFIG_MAPPED_STORAGE_BASE + - data_offset + curr_pos), size); + SHA256_update(&ctx, + (const uint8_t *)((uintptr_t)CONFIG_MAPPED_STORAGE_BASE + + data_offset + curr_pos), + size); crec_flash_lock_mapped_storage(0); #else if (read_and_hash_chunk(data_offset + curr_pos, size) != EC_SUCCESS) @@ -271,9 +272,9 @@ int vboot_hash_invalidate(int offset, int size) */ static uint32_t get_rw_size(void) { -#ifdef CONFIG_VBOOT_EFS /* Only needed for EFS, which signs and verifies - * entire RW, thus not needed for EFS2, which - * verifies only the used image size. */ +#ifdef CONFIG_VBOOT_EFS /* Only needed for EFS, which signs and verifies \ + * entire RW, thus not needed for EFS2, which \ + * verifies only the used image size. */ return CONFIG_RW_SIZE; #else return system_get_image_used(EC_IMAGE_RW); @@ -329,8 +330,8 @@ static int get_offset(int offset) #ifdef CONFIG_CMD_HASH static int command_hash(int argc, char **argv) { - uint32_t offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + uint32_t offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; uint32_t size = CONFIG_RW_SIZE; char *e; @@ -356,15 +357,14 @@ static int command_hash(int argc, char **argv) return EC_SUCCESS; } else if (!strcasecmp(argv[1], "rw")) { return vboot_hash_start( - get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE), - get_rw_size(), - NULL, 0, VBOOT_HASH_DEFERRED); + get_offset(EC_VBOOT_HASH_OFFSET_ACTIVE), + get_rw_size(), NULL, 0, VBOOT_HASH_DEFERRED); } else if (!strcasecmp(argv[1], "ro")) { return vboot_hash_start( CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF, - system_get_image_used(EC_IMAGE_RO), - NULL, 0, VBOOT_HASH_DEFERRED); + CONFIG_RO_STORAGE_OFF, + system_get_image_used(EC_IMAGE_RO), NULL, 0, + VBOOT_HASH_DEFERRED); } return EC_ERROR_PARAM2; } @@ -384,12 +384,11 @@ static int command_hash(int argc, char **argv) if (*e) return EC_ERROR_PARAM3; - return vboot_hash_start(offset, size, - (const uint8_t *)&nonce, + return vboot_hash_start(offset, size, (const uint8_t *)&nonce, sizeof(nonce), VBOOT_HASH_DEFERRED); } else - return vboot_hash_start(offset, size, - NULL, 0, VBOOT_HASH_DEFERRED); + return vboot_hash_start(offset, size, NULL, 0, + VBOOT_HASH_DEFERRED); } DECLARE_CONSOLE_COMMAND(hash, command_hash, "[abort | ro | rw] | [ []]", @@ -399,8 +398,7 @@ DECLARE_CONSOLE_COMMAND(hash, command_hash, /* Host commands */ /* Fill in the response with the current hash status */ -static void fill_response(struct ec_response_vboot_hash *r, - int request_offset) +static void fill_response(struct ec_response_vboot_hash *r, int request_offset) { if (in_progress) r->status = EC_VBOOT_HASH_STATUS_BUSY; @@ -439,7 +437,7 @@ static int host_start_hash(const struct ec_params_vboot_hash *p) if (offset == EC_VBOOT_HASH_OFFSET_RO) size = system_get_image_used(EC_IMAGE_RO); else if ((offset == EC_VBOOT_HASH_OFFSET_ACTIVE) || - (offset == EC_VBOOT_HASH_OFFSET_UPDATE)) + (offset == EC_VBOOT_HASH_OFFSET_UPDATE)) size = get_rw_size(); offset = get_offset(offset); rv = vboot_hash_start(offset, size, p->nonce_data, p->nonce_size, @@ -493,6 +491,5 @@ host_command_vboot_hash(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; } } -DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH, - host_command_vboot_hash, +DECLARE_HOST_COMMAND(EC_CMD_VBOOT_HASH, host_command_vboot_hash, EC_VER_MASK(0)); -- cgit v1.2.1 From 33637f299d82e31fc41660cdf0e889f1424c17c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:24 -0600 Subject: chip/stm32/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39775a445c62c2ffd82b54a3b4b391abf0a8b678 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729509 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c index 20d9223351..58a1f3581a 100644 --- a/chip/stm32/gpio.c +++ b/chip/stm32/gpio.c @@ -16,7 +16,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* For each EXTI bit, record which GPIO entry is using it */ static uint8_t exti_events[16]; @@ -83,8 +83,8 @@ test_mockable int gpio_get_level(enum gpio_signal signal) void gpio_set_level(enum gpio_signal signal, int value) { - STM32_GPIO_BSRR(gpio_list[signal].port) = - gpio_list[signal].mask << (value ? 0 : 16); + STM32_GPIO_BSRR(gpio_list[signal].port) = gpio_list[signal].mask + << (value ? 0 : 16); } int gpio_enable_interrupt(enum gpio_signal signal) @@ -103,8 +103,8 @@ int gpio_enable_interrupt(enum gpio_signal signal) g_old += exti_events[bit]; if ((exti_events[bit]) && (exti_events[bit] != signal)) { - CPRINTS("Overriding %s with %s on EXTI%d", - g_old->name, g->name, bit); + CPRINTS("Overriding %s with %s on EXTI%d", g_old->name, g->name, + bit); } exti_events[bit] = signal; @@ -112,8 +112,9 @@ int gpio_enable_interrupt(enum gpio_signal signal) shift = (bit % 4) * 4; bank = (g->port - STM32_GPIOA_BASE) / 0x400; - STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) & - ~(0xF << shift)) | (bank << shift); + STM32_SYSCFG_EXTICR(group) = + (STM32_SYSCFG_EXTICR(group) & ~(0xF << shift)) | + (bank << shift); STM32_EXTI_IMR |= g->mask; return EC_SUCCESS; -- cgit v1.2.1 From 5f37310145baf034ac3504cfed46ee31338c9d08 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:41 -0600 Subject: board/kracko/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2bda2a3539538c7040d649c9730c9e6b0bbd8cfa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728539 Reviewed-by: Jeremy Bettis --- board/kracko/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kracko/usb_pd_policy.c b/board/kracko/usb_pd_policy.c index 3ff7152541..6c3370ca2f 100644 --- a/board/kracko/usb_pd_policy.c +++ b/board/kracko/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 4526b7560d8612289982c09a8288a56f3d701a8e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:56 -0600 Subject: chip/stm32/i2c_ite_flash_support.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6b8fdfe691767100f4f3b6d91035f11a43085df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729403 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c_ite_flash_support.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/chip/stm32/i2c_ite_flash_support.c b/chip/stm32/i2c_ite_flash_support.c index 916a8c364c..590748776c 100644 --- a/chip/stm32/i2c_ite_flash_support.c +++ b/chip/stm32/i2c_ite_flash_support.c @@ -33,10 +33,10 @@ * (1<<9)-6 reads, leaving 6012 bytes of RAM available, down from 7356 bytes of * RAM available with the default 60 byte limits. */ -#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1<<9) - 4) +#if CONFIG_USB_I2C_MAX_WRITE_COUNT != ((1 << 9) - 4) #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 4) #endif -#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1<<9) - 6) +#if CONFIG_USB_I2C_MAX_READ_COUNT != ((1 << 9) - 6) #error Must set CONFIG_USB_I2C_MAX_WRITE_COUNT to ((1<<9) - 6) #endif @@ -97,16 +97,15 @@ static int ite_i2c_read_register(uint8_t register_offset, uint8_t *output) int ret; /* Tell the ITE EC which register we want to read. */ ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_CMD_ADDR_FLAGS, - ®ister_offset, sizeof(register_offset), - NULL, 0, I2C_XFER_SINGLE); + ITE_DFU_I2C_CMD_ADDR_FLAGS, ®ister_offset, + sizeof(register_offset), NULL, 0, + I2C_XFER_SINGLE); if (ret != EC_SUCCESS) return ret; /* Read in the 1 byte register value. */ ret = i2c_xfer_unlocked(ite_dfu_config.i2c_port, - ITE_DFU_I2C_DATA_ADDR_FLAGS, - NULL, 0, - output, sizeof(*output), I2C_XFER_SINGLE); + ITE_DFU_I2C_DATA_ADDR_FLAGS, NULL, 0, output, + sizeof(*output), I2C_XFER_SINGLE); return ret; } @@ -212,7 +211,7 @@ unlock: } ccprintf("ITE EC info: CHIPID1=0x%02X CHIPID2=0x%02X CHIPVER=0x%02X ", - chipid1[0], chipid2[0], chipver[0]); + chipid1[0], chipid2[0], chipver[0]); ccprintf("version=%d flash_bytes=%d\n", chip_version, flash_kb << 10); /* @@ -236,8 +235,8 @@ static int command_enable_ite_dfu(int argc, char **argv) return EC_ERROR_ACCESS_DENIED; /* Enable peripheral clocks. */ - STM32_RCC_APB2ENR |= - STM32_RCC_APB2ENR_TIM16EN | STM32_RCC_APB2ENR_TIM17EN; + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_TIM16EN | + STM32_RCC_APB2ENR_TIM17EN; /* Reset timer registers which are not otherwise set below. */ STM32_TIM_CR2(16) = 0x0000; @@ -265,10 +264,10 @@ static int command_enable_ite_dfu(int argc, char **argv) STM32_TIM_ARR(17) = (MHz / SMDAT_WAVEFORM_PERIOD_HZ) - 1; /* Set output compare 1 mode to PWM mode 1 and enable preload. */ - STM32_TIM_CCMR1(16) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; - STM32_TIM_CCMR1(17) = - STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | STM32_TIM_CCMR1_OC1PE; + STM32_TIM_CCMR1(16) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | + STM32_TIM_CCMR1_OC1PE; + STM32_TIM_CCMR1(17) = STM32_TIM_CCMR1_OC1M_PWM_MODE_1 | + STM32_TIM_CCMR1_OC1PE; /* * Enable output compare 1 (or its N counterpart). Note that if only @@ -335,9 +334,8 @@ static int command_enable_ite_dfu(int argc, char **argv) return cprint_ite_chip_id(); } -DECLARE_CONSOLE_COMMAND( - enable_ite_dfu, command_enable_ite_dfu, "", - "Enable ITE Direct Firmware Update (DFU) mode"); +DECLARE_CONSOLE_COMMAND(enable_ite_dfu, command_enable_ite_dfu, "", + "Enable ITE Direct Firmware Update (DFU) mode"); /* Read ITE chip ID. Can be used to verify ITE DFU mode. */ static int command_get_ite_chipid(int argc, char **argv) -- cgit v1.2.1 From 7766e8c75bf4af59b9cbc8216e5b8ebbbc5eff7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:24 -0600 Subject: zephyr/shim/src/led_driver/led_pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia70dd0ced03306b61560ad07d2af683f7540a55b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727464 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/led_driver/led_pwm.c | 69 ++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 38 deletions(-) diff --git a/zephyr/shim/src/led_driver/led_pwm.c b/zephyr/shim/src/led_driver/led_pwm.c index 7935bc0d8a..37bd03d69a 100644 --- a/zephyr/shim/src/led_driver/led_pwm.c +++ b/zephyr/shim/src/led_driver/led_pwm.c @@ -28,53 +28,48 @@ LOG_MODULE_REGISTER(pwm_led, LOG_LEVEL_ERR); * duty_cycle = 50 %, pulse_ns = (2000000*50)/100 = 1000000ns */ const uint32_t period_ns = - (NSEC_PER_SEC / DT_PROP(PWM_LED_PINS_NODE, pwm_frequency)); - -#define SET_PIN(node_id, prop, i) \ -{ \ - .pwm = DEVICE_DT_GET( \ - DT_PWMS_CTLR(DT_PHANDLE_BY_IDX(node_id, prop, i))), \ - .channel = DT_PWMS_CHANNEL( \ - DT_PHANDLE_BY_IDX(node_id, prop, i)), \ - .flags = DT_PWMS_FLAGS(DT_PHANDLE_BY_IDX(node_id, prop, i)), \ - .pulse_ns = DIV_ROUND_NEAREST( \ - period_ns * DT_PHA_BY_IDX(node_id, prop, i, value), 100), \ -}, - -#define SET_PWM_PIN(node_id) \ -{ \ - DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) \ -}; - -#define GEN_PINS_ARRAY(id) \ -struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id) + (NSEC_PER_SEC / DT_PROP(PWM_LED_PINS_NODE, pwm_frequency)); + +#define SET_PIN(node_id, prop, i) \ + { \ + .pwm = DEVICE_DT_GET( \ + DT_PWMS_CTLR(DT_PHANDLE_BY_IDX(node_id, prop, i))), \ + .channel = \ + DT_PWMS_CHANNEL(DT_PHANDLE_BY_IDX(node_id, prop, i)), \ + .flags = DT_PWMS_FLAGS(DT_PHANDLE_BY_IDX(node_id, prop, i)), \ + .pulse_ns = DIV_ROUND_NEAREST( \ + period_ns * DT_PHA_BY_IDX(node_id, prop, i, value), \ + 100), \ + }, + +#define SET_PWM_PIN(node_id) \ + { DT_FOREACH_PROP_ELEM(node_id, led_pins, SET_PIN) }; + +#define GEN_PINS_ARRAY(id) struct pwm_pin_t PINS_ARRAY(id)[] = SET_PWM_PIN(id) DT_FOREACH_CHILD(PWM_LED_PINS_NODE, GEN_PINS_ARRAY) -#define SET_PIN_NODE(node_id) \ -{ \ - .led_color = GET_PROP(node_id, led_color), \ - .led_id = GET_PROP(node_id, led_id), \ - .br_color = GET_PROP_NVE(node_id, br_color), \ - .pwm_pins = PINS_ARRAY(node_id), \ - .pins_count = DT_PROP_LEN(node_id, led_pins) \ -}; +#define SET_PIN_NODE(node_id) \ + { .led_color = GET_PROP(node_id, led_color), \ + .led_id = GET_PROP(node_id, led_id), \ + .br_color = GET_PROP_NVE(node_id, br_color), \ + .pwm_pins = PINS_ARRAY(node_id), \ + .pins_count = DT_PROP_LEN(node_id, led_pins) }; /* * Initialize led_pins_node_t struct for each pin node defined */ -#define GEN_PINS_NODES(id) \ -const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id) +#define GEN_PINS_NODES(id) \ + const struct led_pins_node_t PINS_NODE(id) = SET_PIN_NODE(id) DT_FOREACH_CHILD(PWM_LED_PINS_NODE, GEN_PINS_NODES) /* * Array of pointers to each pin node */ -#define PINS_NODE_PTR(id) &PINS_NODE(id), -const struct led_pins_node_t *pins_node[] = { - DT_FOREACH_CHILD(PWM_LED_PINS_NODE, PINS_NODE_PTR) -}; +#define PINS_NODE_PTR(id) &PINS_NODE(id), +const struct led_pins_node_t *pins_node[] = { DT_FOREACH_CHILD( + PWM_LED_PINS_NODE, PINS_NODE_PTR) }; /* * Set all the PWM channels defined in the node to the defined value, @@ -84,10 +79,8 @@ const struct led_pins_node_t *pins_node[] = { void led_set_color_with_node(const struct led_pins_node_t *pins_node) { for (int j = 0; j < pins_node->pins_count; j++) { - pwm_set( - pins_node->pwm_pins[j].pwm, - pins_node->pwm_pins[j].channel, - period_ns, + pwm_set(pins_node->pwm_pins[j].pwm, + pins_node->pwm_pins[j].channel, period_ns, pins_node->pwm_pins[j].pulse_ns, pins_node->pwm_pins[j].flags); } -- cgit v1.2.1 From dcbc85fa87bb6aab743f6de80602054e5f8f9eed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:12 -0600 Subject: include/console.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5430e033cc89107860670fae0a2bab5596fabcbc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730234 Reviewed-by: Jeremy Bettis --- include/console.h | 94 ++++++++++++++++++++++++++----------------------------- 1 file changed, 44 insertions(+), 50 deletions(-) diff --git a/include/console.h b/include/console.h index 457d24cc95..addee30386 100644 --- a/include/console.h +++ b/include/console.h @@ -54,10 +54,9 @@ struct hex_buffer_params { uint16_t size; }; -#define HEX_BUF(_buffer, _size) (&(const struct hex_buffer_params){ \ - .buffer = (_buffer), \ - .size = (_size) \ -}) +#define HEX_BUF(_buffer, _size) \ + (&(const struct hex_buffer_params){ .buffer = (_buffer), \ + .size = (_size) }) /* * Define parameters to printing in binary: the value to print, and the number @@ -69,10 +68,9 @@ struct binary_print_params { uint8_t count; }; -#define BINARY_VALUE(_value, _count) (&(const struct binary_print_params){ \ - .value = (_value), \ - .count = (_count) \ -}) +#define BINARY_VALUE(_value, _count) \ + (&(const struct binary_print_params){ .value = (_value), \ + .count = (_count) }) #define PRINTF_TIMESTAMP_NOW NULL @@ -94,7 +92,7 @@ struct console_command { }; /* Flag bits for when CONFIG_CONSOLE_COMMAND_FLAGS is enabled */ -#define CMD_FLAG_RESTRICTED 0x00000001 +#define CMD_FLAG_RESTRICTED 0x00000001 /* The default .flags value can be overridden in board.h */ #ifndef CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT @@ -116,19 +114,19 @@ static inline int console_is_restricted(void) /* Console channels */ enum console_channel { - #define CONSOLE_CHANNEL(enumeration, string) enumeration, - #include "console_channel.inc" - #undef CONSOLE_CHANNEL +#define CONSOLE_CHANNEL(enumeration, string) enumeration, +#include "console_channel.inc" +#undef CONSOLE_CHANNEL /* Channel count; not itself a channel */ CC_CHANNEL_COUNT }; /* Mask in channel_mask for a particular channel */ -#define CC_MASK(channel) (1U << (channel)) +#define CC_MASK(channel) (1U << (channel)) /* Mask to use to enable all channels */ -#define CC_ALL 0xffffffffU +#define CC_ALL 0xffffffffU /** * Enable a console channel by name @@ -178,8 +176,8 @@ int cputs(enum console_channel channel, const char *outstr); * * @return non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 2, 3))) -int cprintf(enum console_channel channel, const char *format, ...); +__attribute__((__format__(__printf__, 2, 3))) int +cprintf(enum console_channel channel, const char *format, ...); /** * Print formatted output with timestamp. This is like: @@ -190,8 +188,8 @@ int cprintf(enum console_channel channel, const char *format, ...); * * @return non-zero if output was truncated. */ -__attribute__((__format__(__printf__, 2, 3))) -int cprints(enum console_channel channel, const char *format, ...); +__attribute__((__format__(__printf__, 2, 3))) int +cprints(enum console_channel channel, const char *format, ...); /** * Flush the console output for all channels. @@ -205,8 +203,8 @@ void cflush(void); #define ccputs(outstr) cputs(CC_COMMAND, outstr) /* gcc allows variable arg lists in macros; see * http://gcc.gnu.org/onlinedocs/gcc/Variadic-Macros.html */ -#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ## args) -#define ccprints(format, args...) cprints(CC_COMMAND, format, ## args) +#define ccprintf(format, args...) cprintf(CC_COMMAND, format, ##args) +#define ccprints(format, args...) cprints(CC_COMMAND, format, ##args) /** * Called by UART when a line of input is pending. @@ -227,45 +225,41 @@ void console_has_input(void); * @param flags Per-command flags, if needed. */ #if !defined(HAS_TASK_CONSOLE) && !defined(CONFIG_ZEPHYR) -#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) -#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) +#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + static int(ROUTINE)(int argc, char **argv) __attribute__((unused)) +#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + static int(ROUTINE)(int argc, char **argv) __attribute__((unused)) #define DECLARE_CONSOLE_COMMAND_FLAGS(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ - static int (ROUTINE)(int argc, char **argv) __attribute__((unused)) + static int(ROUTINE)(int argc, char **argv) __attribute__((unused)) #elif defined(HAS_TASK_CONSOLE) /* We always provde help args, but we may discard them to save space. */ #if defined(CONFIG_CONSOLE_CMDHELP) -#define _HELP_ARGS(A, H) \ - .argdesc = A, \ - .help = H, +#define _HELP_ARGS(A, H) .argdesc = A, .help = H, #else #define _HELP_ARGS(A, H) #endif /* We may or may not have a .flags field */ #ifdef CONFIG_CONSOLE_COMMAND_FLAGS -#define _FLAG_ARGS(F) \ - .flags = F, +#define _FLAG_ARGS(F) .flags = F, #else #define _FLAG_ARGS(F) #endif /* This macro takes all possible args and discards the ones we don't use */ -#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ - static int (ROUTINE)(int argc, char **argv); \ - static const char __con_cmd_label_##NAME[] = #NAME; \ - _STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16, \ - "command name '" #NAME "' is too long"); \ - const struct console_command __keep __no_sanitize_address \ - __con_cmd_##NAME \ - __attribute__((section(".rodata.cmds." #NAME))) = \ - { .name = __con_cmd_label_##NAME, \ - .handler = ROUTINE, \ - _HELP_ARGS(ARGDESC, HELP) \ - _FLAG_ARGS(FLAGS) \ - } +#define _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) \ + static int(ROUTINE)(int argc, char **argv); \ + static const char __con_cmd_label_##NAME[] = #NAME; \ + _STATIC_ASSERT(sizeof(__con_cmd_label_##NAME) < 16, \ + "command name '" #NAME "' is too long"); \ + const struct console_command __keep __no_sanitize_address \ + __con_cmd_##NAME \ + __attribute__((section(".rodata.cmds." #NAME))) = { \ + .name = __con_cmd_label_##NAME, \ + .handler = ROUTINE, \ + _HELP_ARGS(ARGDESC, HELP) _FLAG_ARGS(FLAGS) \ + } /* * If the .flags field exists, we can use this to specify its value. If not, @@ -275,8 +269,8 @@ void console_has_input(void); _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, FLAGS) /* This works as before, for the same reason. */ -#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ +#define DECLARE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT) /* @@ -284,11 +278,11 @@ void console_has_input(void); * the command is never restricted. BE CAREFUL! You should only use this for * commands that either do nothing or that do only safe things. */ -#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ - _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ - (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT & \ +#define DECLARE_SAFE_CONSOLE_COMMAND(NAME, ROUTINE, ARGDESC, HELP) \ + _DCL_CON_CMD_ALL(NAME, ROUTINE, ARGDESC, HELP, \ + (CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT & \ ~CMD_FLAG_RESTRICTED)) -#endif /* HAS_TASK_CONSOLE */ +#endif /* HAS_TASK_CONSOLE */ -#endif /* __CROS_EC_CONSOLE_H */ +#endif /* __CROS_EC_CONSOLE_H */ -- cgit v1.2.1 From 85d997d3ff8a01c9a08d8a6b9990c6bf372884d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:38 -0600 Subject: zephyr/shim/src/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01028c2433d4943a202004c4b46eb6a52ff26aa4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730865 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/charger.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/src/charger.c b/zephyr/shim/src/charger.c index 08aa121a19..9c2b3b2fbe 100644 --- a/zephyr/shim/src/charger.c +++ b/zephyr/shim/src/charger.c @@ -21,22 +21,26 @@ struct charger_config_t chg_chips[] = { #endif DT_FOREACH_STATUS_OKAY_VARGS(BQ25710_CHG_COMPAT, CHG_CHIP, CHG_CONFIG_BQ25710) - DT_FOREACH_STATUS_OKAY_VARGS(ISL923X_CHG_COMPAT, CHG_CHIP, - CHG_CONFIG_ISL923X) - DT_FOREACH_STATUS_OKAY_VARGS(ISL9241_CHG_COMPAT, CHG_CHIP, - CHG_CONFIG_ISL9241) - DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, CHG_CHIP, - CHG_CONFIG_RT9490) - DT_FOREACH_STATUS_OKAY_VARGS(SM5803_CHG_COMPAT, CHG_CHIP, - CHG_CONFIG_SM5803) + DT_FOREACH_STATUS_OKAY_VARGS(ISL923X_CHG_COMPAT, CHG_CHIP, + CHG_CONFIG_ISL923X) + DT_FOREACH_STATUS_OKAY_VARGS(ISL9241_CHG_COMPAT, + CHG_CHIP, + CHG_CONFIG_ISL9241) + DT_FOREACH_STATUS_OKAY_VARGS(RT9490_CHG_COMPAT, + CHG_CHIP, + CHG_CONFIG_RT9490) + DT_FOREACH_STATUS_OKAY_VARGS( + SM5803_CHG_COMPAT, CHG_CHIP, + CHG_CONFIG_SM5803) }; #ifdef CONFIG_PLATFORM_EC_CHARGER_SINGLE_CHIP BUILD_ASSERT(ARRAY_SIZE(chg_chips) == 1, - "For the CHARGER_SINGLE_CHIP config, the number of defined charger " - "chips must equal 1."); + "For the CHARGER_SINGLE_CHIP config, the number of defined charger " + "chips must equal 1."); #else -BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CONFIG_USB_PD_PORT_MAX_COUNT, +BUILD_ASSERT( + ARRAY_SIZE(chg_chips) == CONFIG_USB_PD_PORT_MAX_COUNT, "For the OCPC config, the number of defined charger chips must equal " "the number of USB-C ports."); #endif -- cgit v1.2.1 From e621d5b501232e442d6ce3c6e9728ee91260f12f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:31 -0600 Subject: board/genesis/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id35adf9264a282d76ebdb35ce2d2db498cd6317c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728399 Reviewed-by: Jeremy Bettis --- board/genesis/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/genesis/led.c b/board/genesis/led.c index c562dff27e..92f88d4cd7 100644 --- a/board/genesis/led.c +++ b/board/genesis/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -89,9 +89,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From cbd975149047fd2592233ff98753064836892e76 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:16 -0600 Subject: driver/mp4245.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I176c65f699c5d87e2a2e16d34dfd212cc801e958 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730021 Reviewed-by: Jeremy Bettis --- driver/mp4245.h | 98 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 48 insertions(+), 50 deletions(-) diff --git a/driver/mp4245.h b/driver/mp4245.h index b453ad2076..b234827809 100644 --- a/driver/mp4245.h +++ b/driver/mp4245.h @@ -5,62 +5,60 @@ /* MPS MP4245 Buck-Boost converter driver definitions */ /* I2C addresses */ -#define MP4245_I2C_ADDR_0_FLAGS 0x61 /* R1 -> GND */ -#define MP4245_I2C_ADDR_1_FLAGS 0x62 /* R1 -> 15.0k */ -#define MP4245_I2C_ADDR_2_FLAGS 0x63 /* R1 -> 25.5k */ -#define MP4245_I2C_ADDR_3_FLAGS 0x64 /* R1 -> 35.7k */ -#define MP4245_I2C_ADDR_4_FLAGS 0x65 /* R1 -> 45.3k */ -#define MP4245_I2C_ADDR_5_FLAGS 0x66 /* R1 -> 56.0k */ -#define MP4245_I2C_ADDR_6_FLAGS 0x67 /* R1 -> VCC */ - +#define MP4245_I2C_ADDR_0_FLAGS 0x61 /* R1 -> GND */ +#define MP4245_I2C_ADDR_1_FLAGS 0x62 /* R1 -> 15.0k */ +#define MP4245_I2C_ADDR_2_FLAGS 0x63 /* R1 -> 25.5k */ +#define MP4245_I2C_ADDR_3_FLAGS 0x64 /* R1 -> 35.7k */ +#define MP4245_I2C_ADDR_4_FLAGS 0x65 /* R1 -> 45.3k */ +#define MP4245_I2C_ADDR_5_FLAGS 0x66 /* R1 -> 56.0k */ +#define MP4245_I2C_ADDR_6_FLAGS 0x67 /* R1 -> VCC */ /* MP4245 CMD Offsets */ -#define MP4245_CMD_OPERATION 0x01 -#define MP4245_CMD_CLEAR_FAULTS 0x03 -#define MP4245_CMD_WRITE_PROTECT 0x10 -#define MP4245_CMD_STORE_USER_ALL 0x15 -#define MP4245_CMD_RESTORE_USER_ALL 0x16 -#define MP4245_CMD_VOUT_MODE 0x20 -#define MP4245_CMD_VOUT_COMMAND 0x21 -#define MP4245_CMD_VOUT_SCALE_LOOP 0x29 -#define MP4245_CMD_STATUS_BYTE 0x78 -#define MP4245_CMD_STATUS_WORD 0x79 -#define MP4245_CMD_STATUS_VOUT 0x7A -#define MP4245_CMD_STATUS_INPUT 0x7C -#define MP4245_CMD_STATUS_TEMP 0x7D -#define MP4245_CMD_STATUS_CML 0x7E -#define MP4245_CMD_READ_VIN 0x88 -#define MP4245_CMD_READ_VOUT 0x8B -#define MP4245_CMD_READ_IOUT 0x8C -#define MP4245_CMD_READ_TEMP 0x8D -#define MP4245_CMD_MFR_MODE_CTRL 0xD0 -#define MP4245_CMD_MFR_CURRENT_LIM 0xD1 -#define MP4245_CMD_MFR_LINE_DROP 0xD2 -#define MP4245_CMD_MFR_OT_FAULT_LIM 0xD3 -#define MP4245_CMD_MFR_OT_WARN_LIM 0xD4 -#define MP4245_CMD_MFR_CRC_ERROR 0xD5 -#define MP4245_CMD_MFF_MTP_CFG_CODE 0xD6 -#define MP4245_CMD_MFR_MTP_REV_NUM 0xD7 -#define MP4245_CMD_MFR_STATUS_MASK 0xD8 - -#define MP4245_CMD_OPERATION_ON BIT(7) +#define MP4245_CMD_OPERATION 0x01 +#define MP4245_CMD_CLEAR_FAULTS 0x03 +#define MP4245_CMD_WRITE_PROTECT 0x10 +#define MP4245_CMD_STORE_USER_ALL 0x15 +#define MP4245_CMD_RESTORE_USER_ALL 0x16 +#define MP4245_CMD_VOUT_MODE 0x20 +#define MP4245_CMD_VOUT_COMMAND 0x21 +#define MP4245_CMD_VOUT_SCALE_LOOP 0x29 +#define MP4245_CMD_STATUS_BYTE 0x78 +#define MP4245_CMD_STATUS_WORD 0x79 +#define MP4245_CMD_STATUS_VOUT 0x7A +#define MP4245_CMD_STATUS_INPUT 0x7C +#define MP4245_CMD_STATUS_TEMP 0x7D +#define MP4245_CMD_STATUS_CML 0x7E +#define MP4245_CMD_READ_VIN 0x88 +#define MP4245_CMD_READ_VOUT 0x8B +#define MP4245_CMD_READ_IOUT 0x8C +#define MP4245_CMD_READ_TEMP 0x8D +#define MP4245_CMD_MFR_MODE_CTRL 0xD0 +#define MP4245_CMD_MFR_CURRENT_LIM 0xD1 +#define MP4245_CMD_MFR_LINE_DROP 0xD2 +#define MP4245_CMD_MFR_OT_FAULT_LIM 0xD3 +#define MP4245_CMD_MFR_OT_WARN_LIM 0xD4 +#define MP4245_CMD_MFR_CRC_ERROR 0xD5 +#define MP4245_CMD_MFF_MTP_CFG_CODE 0xD6 +#define MP4245_CMD_MFR_MTP_REV_NUM 0xD7 +#define MP4245_CMD_MFR_STATUS_MASK 0xD8 -#define MP4245_VOUT_1V BIT(10) -#define MP4245_VOUT_FROM_MV (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000) -#define MP4245_VOUT_TO_MV(v) ((v * 1000) / MP4245_VOUT_1V) -#define MP4245_IOUT_TO_MA(i) (((i & 0x7ff) * 1000) / BIT(6)) -#define MP4245_ILIM_STEP_MA 50 -#define MP4245_VOUT_5V_DELAY_MS 10 +#define MP4245_CMD_OPERATION_ON BIT(7) +#define MP4245_VOUT_1V BIT(10) +#define MP4245_VOUT_FROM_MV (MP4245_VOUT_1V * MP4245_VOUT_1V / 1000) +#define MP4245_VOUT_TO_MV(v) ((v * 1000) / MP4245_VOUT_1V) +#define MP4245_IOUT_TO_MA(i) (((i & 0x7ff) * 1000) / BIT(6)) +#define MP4245_ILIM_STEP_MA 50 +#define MP4245_VOUT_5V_DELAY_MS 10 -#define MP4245_MFR_STATUS_MASK_VOUT BIT(7) -#define MP4245_MFR_STATUS_MASK_IOUT BIT(6) -#define MP4245_MFR_STATUS_MASK_INPUT BIT(5) -#define MP4245_MFR_STATUS_MASK_TEMP BIT(4) -#define MP4245_MFR_STATUS_MASK_PG_STATUS BIT(3) +#define MP4245_MFR_STATUS_MASK_VOUT BIT(7) +#define MP4245_MFR_STATUS_MASK_IOUT BIT(6) +#define MP4245_MFR_STATUS_MASK_INPUT BIT(5) +#define MP4245_MFR_STATUS_MASK_TEMP BIT(4) +#define MP4245_MFR_STATUS_MASK_PG_STATUS BIT(3) #define MP4245_MFR_STATUS_MASK_PG_ALT_EDGE BIT(2) -#define MP4245_MFR_STATUS_MASK_OTHER BIT(1) -#define MP4245_MFR_STATUS_MASK_UNKNOWN BIT(0) +#define MP4245_MFR_STATUS_MASK_OTHER BIT(1) +#define MP4245_MFR_STATUS_MASK_UNKNOWN BIT(0) /** * MP4245 set output voltage level -- cgit v1.2.1 From f9c2b40ac39e08e08484745efec710b1313d45de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:44 -0600 Subject: include/usb_pd_vdo.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I28f19a77ad9cccf0476e95c183276b9db58f69b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730446 Reviewed-by: Jeremy Bettis --- include/usb_pd_vdo.h | 78 +++++++++++++++++++++++----------------------------- 1 file changed, 34 insertions(+), 44 deletions(-) diff --git a/include/usb_pd_vdo.h b/include/usb_pd_vdo.h index 9f6e35e117..49e55af199 100644 --- a/include/usb_pd_vdo.h +++ b/include/usb_pd_vdo.h @@ -134,20 +134,20 @@ struct product_vdo { #define PD_PRODUCT_IS_TBT3(vdo) ((vdo) >> 3 & BIT(0)) /* UFP VDO Version 1.2; update the value when UFP VDO version changes */ -#define VDO_UFP1(cap, ctype, alt, speed) \ - ((0x2) << 29 | ((cap) & 0xf) << 24 \ - | ((ctype) & 0x3) << 22 | ((alt) & 0x7) << 3 | ((speed) & 0x7)) +#define VDO_UFP1(cap, ctype, alt, speed) \ + ((0x2) << 29 | ((cap)&0xf) << 24 | ((ctype)&0x3) << 22 | \ + ((alt)&0x7) << 3 | ((speed)&0x7)) /* UFP VDO 1 Alternate Modes */ -#define VDO_UFP1_ALT_MODE_TBT3 BIT(0) -#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1) +#define VDO_UFP1_ALT_MODE_TBT3 BIT(0) +#define VDO_UFP1_ALT_MODE_RECONFIGURE BIT(1) #define VDO_UFP1_ALT_MODE_NO_RECONFIGURE BIT(2) /* UFP VDO 1 Device Capability */ -#define VDO_UFP1_CAPABILITY_USB20 BIT(0) +#define VDO_UFP1_CAPABILITY_USB20 BIT(0) #define VDO_UFP1_CAPABILITY_USB20_BILLBOARD BIT(1) -#define VDO_UFP1_CAPABILITY_USB32 BIT(2) -#define VDO_UFP1_CAPABILITY_USB4 BIT(3) +#define VDO_UFP1_CAPABILITY_USB32 BIT(2) +#define VDO_UFP1_CAPABILITY_USB4 BIT(3) /*****************************************************************************/ /* * Table 6-37 DFP VDO @@ -170,15 +170,13 @@ struct product_vdo { * <4:0> : Port number */ /* DFP VDO Version 1.1; update the value when DFP VDO version changes */ -#define VDO_DFP(cap, ctype, port) \ - ((0x1) << 29 | ((cap) & 0x7) << 24 \ - | ((ctype) & 0x3) << 22 | ((port) & 0x1f)) +#define VDO_DFP(cap, ctype, port) \ + ((0x1) << 29 | ((cap)&0x7) << 24 | ((ctype)&0x3) << 22 | ((port)&0x1f)) /* DFP VDO Host Capability */ #define VDO_DFP_HOST_CAPABILITY_USB20 BIT(0) #define VDO_DFP_HOST_CAPABILITY_USB32 BIT(1) -#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2) - +#define VDO_DFP_HOST_CAPABILITY_USB4 BIT(2) /*****************************************************************************/ /* @@ -267,7 +265,7 @@ enum usb_vbus_cur { union passive_cable_vdo_rev30 { struct { - enum usb_rev30_ss ss: 3; + enum usb_rev30_ss ss : 3; uint32_t reserved0 : 2; enum usb_vbus_cur vbus_cur : 2; uint32_t reserved1 : 2; @@ -355,7 +353,7 @@ enum vdo_version { union active_cable_vdo1_rev30 { struct { - enum usb_rev30_ss ss: 3; + enum usb_rev30_ss ss : 3; uint32_t sop_p_p : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -541,17 +539,11 @@ union active_cable_vdo2_rev30 { * 1b – the VPD supports Charge Through * 0b – the VPD does not support Charge Through */ -#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts) \ - (((hw) & 0xf) << 28 | ((fw) & 0xf) << 24 \ - | ((vbus) & 0x3) << 15 \ - | ((ctc) & 0x1) << 14 \ - | ((vbusz) & 0x3f) << 7 \ - | ((gndz) & 0x3f) << 1 | (cts)) - -enum vpd_ctc_support { - VPD_CT_CURRENT_3A, - VPD_CT_CURRENT_5A -}; +#define VDO_VPD(hw, fw, vbus, ctc, vbusz, gndz, cts) \ + (((hw)&0xf) << 28 | ((fw)&0xf) << 24 | ((vbus)&0x3) << 15 | \ + ((ctc)&0x1) << 14 | ((vbusz)&0x3f) << 7 | ((gndz)&0x3f) << 1 | (cts)) + +enum vpd_ctc_support { VPD_CT_CURRENT_3A, VPD_CT_CURRENT_5A }; enum vpd_vbus { VPD_MAX_VBUS_20V, @@ -566,12 +558,12 @@ enum vpd_cts_support { }; #define VPD_VDO_MAX_VBUS(vdo) (((vdo) >> 15) & 0x3) -#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1) +#define VPD_VDO_CURRENT(vdo) (((vdo) >> 14) & 1) #define VPD_VDO_VBUS_IMP(vdo) (((vdo) >> 7) & 0x3f) -#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f) -#define VPD_VDO_CTS(vdo) ((vdo) & 1) -#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1) -#define VPD_GND_IMP(mo) (mo) +#define VPD_VDO_GND_IMP(vdo) (((vdo) >> 1) & 0x3f) +#define VPD_VDO_CTS(vdo) ((vdo)&1) +#define VPD_VBUS_IMP(mo) ((mo + 1) >> 1) +#define VPD_GND_IMP(mo) (mo) /* * ############################################################################ @@ -625,11 +617,10 @@ enum idh_ptype { * - Table 6-29 ID Header VDO PD spec 3.0 version 2.0 and * - Table 6-23 ID Header VDO PD spec 2.0 version 1.3. */ -#define IS_PD_IDH_UFP_PTYPE(ptype) (ptype == IDH_PTYPE_HUB || \ - ptype == IDH_PTYPE_PERIPH || \ - ptype == IDH_PTYPE_PSD || \ - ptype == IDH_PTYPE_AMA || \ - ptype == IDH_PTYPE_VPD) +#define IS_PD_IDH_UFP_PTYPE(ptype) \ + (ptype == IDH_PTYPE_HUB || ptype == IDH_PTYPE_PERIPH || \ + ptype == IDH_PTYPE_PSD || ptype == IDH_PTYPE_AMA || \ + ptype == IDH_PTYPE_VPD) struct id_header_vdo_rev20 { uint16_t usb_vendor_id; @@ -715,7 +706,7 @@ enum usb_rev20_ss { union passive_cable_vdo_rev20 { struct { - enum usb_rev20_ss ss: 3; + enum usb_rev20_ss ss : 3; uint32_t reserved0 : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -798,7 +789,7 @@ union passive_cable_vdo_rev20 { */ union active_cable_vdo_rev20 { struct { - enum usb_rev20_ss ss: 3; + enum usb_rev20_ss ss : 3; uint32_t sop_p_p : 1; uint32_t vbus_cable : 1; enum usb_vbus_cur vbus_cur : 2; @@ -866,14 +857,13 @@ union active_cable_vdo_rev20 { * 011b = [USB 2.0] billboard only * 100b..111b = Reserved, Shall Not be used */ -#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ - (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \ - | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \ - | ((vcpwr) & 0x3) << 5 | (vcr) << 4 | (vbr) << 3 \ - | ((usbss) & 0x7)) +#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \ + (((hw)&0x7) << 28 | ((fw)&0x7) << 24 | (tx1d) << 11 | (tx2d) << 10 | \ + (rx1d) << 9 | (rx2d) << 8 | ((vcpwr)&0x3) << 5 | (vcr) << 4 | \ + (vbr) << 3 | ((usbss)&0x7)) #define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1) -#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) +#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1) enum ama_usb_ss { AMA_USBSS_U2_ONLY, -- cgit v1.2.1 From aef5eb50254dc5c88dc5e92d1fdb4393b5ec7ab6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:20 -0600 Subject: baseboard/mtscp-rv32i/mdp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70e9198c0f6fd65bb829a3448bbc4af56c731167 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727928 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/mdp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/mtscp-rv32i/mdp.h b/baseboard/mtscp-rv32i/mdp.h index eea3ffb289..15c82846ea 100644 --- a/baseboard/mtscp-rv32i/mdp.h +++ b/baseboard/mtscp-rv32i/mdp.h @@ -11,10 +11,10 @@ struct mdp_msg_service { unsigned char msg[20]; }; BUILD_ASSERT(member_size(struct mdp_msg_service, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void mdp_common_init(void); void mdp_ipi_task_handler(void *pvParameters); -#endif /* __CROS_EC_SCP_MDP_H */ +#endif /* __CROS_EC_SCP_MDP_H */ -- cgit v1.2.1 From 3c6360362fed4e7785ffa2b11338a445cd3fa948 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:03 -0600 Subject: include/driver/accelgyro_bmi_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7cac80a05792dbc09d65a0c6df0875e55ba900fa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730268 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi_common.h | 208 +++++++++++++++++----------------- 1 file changed, 106 insertions(+), 102 deletions(-) diff --git a/include/driver/accelgyro_bmi_common.h b/include/driver/accelgyro_bmi_common.h index 6e1ed122b3..5647d8776d 100644 --- a/include/driver/accelgyro_bmi_common.h +++ b/include/driver/accelgyro_bmi_common.h @@ -18,18 +18,18 @@ #error "BMI must use either SPI or I2C communication" #endif -#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) -#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) +#define BMI_CONF_REG(_sensor) (0x40 + 2 * (_sensor)) +#define BMI_RANGE_REG(_sensor) (0x41 + 2 * (_sensor)) -#define BMI_ODR_MASK 0x0F +#define BMI_ODR_MASK 0x0F /* odr = 100 / (1 << (8 - reg)) , within limit */ -#define BMI_ODR_0_78HZ 0x01 -#define BMI_ODR_100HZ 0x08 +#define BMI_ODR_0_78HZ 0x01 +#define BMI_ODR_100HZ 0x08 -#define BMI_REG_TO_ODR(_regval) \ +#define BMI_REG_TO_ODR(_regval) \ ((_regval) < BMI_ODR_100HZ ? 100000 / (1 << (8 - (_regval))) : \ - 100000 * (1 << ((_regval) - 8))) -#define BMI_ODR_TO_REG(_odr) \ + 100000 * (1 << ((_regval)-8))) +#define BMI_ODR_TO_REG(_odr) \ ((_odr) < 100000 ? (__builtin_clz(100000 / ((_odr) + 1)) - 24) : \ (39 - __builtin_clz((_odr) / 100000))) @@ -40,92 +40,100 @@ enum fifo_header { BMI_FH_CONFIG = 0x48 }; -#define BMI_FH_MODE_MASK 0xc0 -#define BMI_FH_PARM_OFFSET 2 -#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) -#define BMI_FH_EXT_MASK 0x03 +#define BMI_FH_MODE_MASK 0xc0 +#define BMI_FH_PARM_OFFSET 2 +#define BMI_FH_PARM_MASK (0x7 << BMI_FH_PARM_OFFSET) +#define BMI_FH_EXT_MASK 0x03 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMI_RESOLUTION 16 +#define BMI_RESOLUTION 16 /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) enum bmi_running_mode { - STANDARD_UI_9DOF_FIFO = 0, - STANDARD_UI_IMU_FIFO = 1, - STANDARD_UI_IMU = 2, - STANDARD_UI_ADVANCEPOWERSAVE = 3, - ACCEL_PEDOMETER = 4, - APPLICATION_HEAD_TRACKING = 5, - APPLICATION_NAVIGATION = 6, - APPLICATION_REMOTE_CONTROL = 7, - APPLICATION_INDOOR_NAVIGATION = 8, + STANDARD_UI_9DOF_FIFO = 0, + STANDARD_UI_IMU_FIFO = 1, + STANDARD_UI_IMU = 2, + STANDARD_UI_ADVANCEPOWERSAVE = 3, + ACCEL_PEDOMETER = 4, + APPLICATION_HEAD_TRACKING = 5, + APPLICATION_NAVIGATION = 6, + APPLICATION_REMOTE_CONTROL = 7, + APPLICATION_INDOOR_NAVIGATION = 8, }; -#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) -#define BMI_FIFO_FLAG_OFFSET 4 -#define BMI_FIFO_ALL_MASK 7 - -#define BMI_GET_DATA(_s) \ - ((struct bmi_drv_data_t *)(_s)->drv_data) -#define BMI_GET_SAVED_DATA(_s) \ - (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) - -#define BMI_ACC_DATA(v) (BMI160_ACC_X_L_G + \ - (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) -#define BMI_GYR_DATA(v) (BMI160_GYR_X_L_G + \ - (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) -#define BMI_AUX_DATA(v) (BMI160_MAG_X_L_G + \ - (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) - -#define BMI_FIFO_CONFIG_0(v) (BMI160_FIFO_CONFIG_0 + \ - (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) -#define BMI_FIFO_CONFIG_1(v) (BMI160_FIFO_CONFIG_1 + \ - (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) -#define BMI_FIFO_SENSOR_EN(v, _sensor) (BMI160_FIFO_SENSOR_EN(_sensor) + \ - (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - BMI160_FIFO_SENSOR_EN(_sensor))) - -#define BMI_TEMPERATURE_0(v) (BMI160_TEMPERATURE_0 + \ - (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) -#define BMI_INVALID_TEMP 0x8000 - -#define BMI_STATUS(v) (BMI160_STATUS + \ - (v) * (BMI260_STATUS - BMI160_STATUS)) -#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) - -#define BMI_OFFSET_ACC70(v) (BMI160_OFFSET_ACC70 + \ - (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) -#define BMI_OFFSET_GYR70(v) (BMI160_OFFSET_GYR70 + \ - (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) +#define BMI_FLAG_SEC_I2C_ENABLED BIT(0) +#define BMI_FIFO_FLAG_OFFSET 4 +#define BMI_FIFO_ALL_MASK 7 + +#define BMI_GET_DATA(_s) ((struct bmi_drv_data_t *)(_s)->drv_data) +#define BMI_GET_SAVED_DATA(_s) (&BMI_GET_DATA(_s)->saved_data[(_s)->type]) + +#define BMI_ACC_DATA(v) \ + (BMI160_ACC_X_L_G + (v) * (BMI260_ACC_X_L_G - BMI160_ACC_X_L_G)) +#define BMI_GYR_DATA(v) \ + (BMI160_GYR_X_L_G + (v) * (BMI260_GYR_X_L_G - BMI160_GYR_X_L_G)) +#define BMI_AUX_DATA(v) \ + (BMI160_MAG_X_L_G + (v) * (BMI260_AUX_X_L_G - BMI160_MAG_X_L_G)) + +#define BMI_FIFO_CONFIG_0(v) \ + (BMI160_FIFO_CONFIG_0 + \ + (v) * (BMI260_FIFO_CONFIG_0 - BMI160_FIFO_CONFIG_0)) +#define BMI_FIFO_CONFIG_1(v) \ + (BMI160_FIFO_CONFIG_1 + \ + (v) * (BMI260_FIFO_CONFIG_1 - BMI160_FIFO_CONFIG_1)) +#define BMI_FIFO_SENSOR_EN(v, _sensor) \ + (BMI160_FIFO_SENSOR_EN(_sensor) + \ + (v) * (BMI260_FIFO_SENSOR_EN(_sensor) - \ + BMI160_FIFO_SENSOR_EN(_sensor))) + +#define BMI_TEMPERATURE_0(v) \ + (BMI160_TEMPERATURE_0 + \ + (v) * (BMI260_TEMPERATURE_0 - BMI160_TEMPERATURE_0)) +#define BMI_INVALID_TEMP 0x8000 + +#define BMI_STATUS(v) (BMI160_STATUS + (v) * (BMI260_STATUS - BMI160_STATUS)) +#define BMI_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI_DRDY_MASK(_sensor) (1 << BMI160_DRDY_OFF(_sensor)) + +#define BMI_OFFSET_ACC70(v) \ + (BMI160_OFFSET_ACC70 + \ + (v) * (BMI260_OFFSET_ACC70 - BMI160_OFFSET_ACC70)) +#define BMI_OFFSET_GYR70(v) \ + (BMI160_OFFSET_GYR70 + \ + (v) * (BMI260_OFFSET_GYR70 - BMI160_OFFSET_GYR70)) /* * There is some bits in this register that differ between BMI160 and BMI260 * Only use this macro for gyro offset 9:8 (BMI_OFFSET_EN_GYR98 5:0). */ -#define BMI_OFFSET_EN_GYR98(v) (BMI160_OFFSET_EN_GYR98 + \ - (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) -#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) -#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) -#define BMI_OFFSET_ACC_DIV_MG 1000000 +#define BMI_OFFSET_EN_GYR98(v) \ + (BMI160_OFFSET_EN_GYR98 + \ + (v) * (BMI260_OFFSET_EN_GYR98 - BMI160_OFFSET_EN_GYR98)) +#define BMI_OFFSET_GYR98_MASK (BIT(6) - 1) +#define BMI_OFFSET_ACC_MULTI_MG (3900 * 1024) +#define BMI_OFFSET_ACC_DIV_MG 1000000 #define BMI_OFFSET_GYRO_MULTI_MDS (61 * 1024) -#define BMI_OFFSET_GYRO_DIV_MDS 1000 - -#define BMI_FIFO_LENGTH_0(v) (BMI160_FIFO_LENGTH_0 + \ - (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) -#define BMI_FIFO_LENGTH_MASK(v) (BMI160_FIFO_LENGTH_MASK + \ - (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) -#define BMI_FIFO_DATA(v) (BMI160_FIFO_DATA + \ - (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) - -#define BMI_CMD_REG(v) (BMI160_CMD_REG + \ - (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) +#define BMI_OFFSET_GYRO_DIV_MDS 1000 + +#define BMI_FIFO_LENGTH_0(v) \ + (BMI160_FIFO_LENGTH_0 + \ + (v) * (BMI260_FIFO_LENGTH_0 - BMI160_FIFO_LENGTH_0)) +#define BMI_FIFO_LENGTH_MASK(v) \ + (BMI160_FIFO_LENGTH_MASK + \ + (v) * (BMI260_FIFO_LENGTH_MASK - BMI160_FIFO_LENGTH_MASK)) +#define BMI_FIFO_DATA(v) \ + (BMI160_FIFO_DATA + (v) * (BMI260_FIFO_DATA - BMI160_FIFO_DATA)) + +#define BMI_CMD_REG(v) \ + (BMI160_CMD_REG + (v) * (BMI260_CMD_REG - BMI160_CMD_REG)) #define BMI_CMD_FIFO_FLUSH 0xb0 -#define BMI_ACCEL_RMS_NOISE_100HZ(v) (BMI160_ACCEL_RMS_NOISE_100HZ + \ - (v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ)) +#define BMI_ACCEL_RMS_NOISE_100HZ(v) \ + (BMI160_ACCEL_RMS_NOISE_100HZ + \ + (v) * (BMI260_ACCEL_RMS_NOISE_100HZ - BMI160_ACCEL_RMS_NOISE_100HZ)) #define BMI_ACCEL_100HZ 100 /* @@ -145,8 +153,8 @@ int bmi_get_xyz_reg(const struct motion_sensor_t *s); * * @return Range table of the type. */ -const struct bmi_accel_param_pair *bmi_get_range_table( - const struct motion_sensor_t *s, int *psize); +const struct bmi_accel_param_pair * +bmi_get_range_table(const struct motion_sensor_t *s, int *psize); /** * @return reg value that matches the given engineering value passed in. @@ -155,8 +163,7 @@ const struct bmi_accel_param_pair *bmi_get_range_table( * outside the range of values, it returns the closest valid reg value. */ int bmi_get_reg_val(const int eng_val, const int round_up, - const struct bmi_accel_param_pair *pairs, - const int size); + const struct bmi_accel_param_pair *pairs, const int size); /** * @return engineering value that matches the given reg val @@ -168,14 +175,14 @@ int bmi_get_engineering_val(const int reg_val, /** * Read 8bit register from accelerometer. */ -int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int *data_ptr); +int bmi_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int *data_ptr); /** * Write 8bit register from accelerometer. */ -int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, - const int reg, int data); +int bmi_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, + int data); /** * Read 16bit register from accelerometer. @@ -210,14 +217,14 @@ int bmi_write_n(const int port, const uint16_t i2c_spi_addr_flags, /* * Enable/Disable specific bit set of a 8-bit reg. */ -int bmi_enable_reg8(const struct motion_sensor_t *s, - int reg, uint8_t bits, int enable); +int bmi_enable_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int enable); /* * Set specific bit set to certain value of a 8-bit reg. */ -int bmi_set_reg8(const struct motion_sensor_t *s, int reg, - uint8_t bits, int mask); +int bmi_set_reg8(const struct motion_sensor_t *s, int reg, uint8_t bits, + int mask); /* * @s: base sensor. @@ -237,9 +244,8 @@ void bmi_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *input); * @bp: current pointer in the buffer, updated when processing the header. * @ep: pointer to the end of the valid data in the buffer. */ -int bmi_decode_header(struct motion_sensor_t *accel, - enum fifo_header hdr, uint32_t last_ts, - uint8_t **bp, uint8_t *ep); +int bmi_decode_header(struct motion_sensor_t *accel, enum fifo_header hdr, + uint32_t last_ts, uint8_t **bp, uint8_t *ep); /** * Retrieve hardware FIFO from sensor, * - put data in Sensor Hub fifo. @@ -261,9 +267,8 @@ int bmi_set_range(struct motion_sensor_t *s, int range, int rnd); int bmi_get_data_rate(const struct motion_sensor_t *s); - -int bmi_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp); +int bmi_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp); int bmi_get_resolution(const struct motion_sensor_t *s); @@ -271,11 +276,11 @@ int bmi_get_resolution(const struct motion_sensor_t *s); int bmi_get_rms_noise(const struct motion_sensor_t *s); #endif -int bmi_set_scale(const struct motion_sensor_t *s, - const uint16_t *scale, int16_t temp); +int bmi_set_scale(const struct motion_sensor_t *s, const uint16_t *scale, + int16_t temp); -int bmi_get_scale(const struct motion_sensor_t *s, - uint16_t *scale, int16_t *temp); +int bmi_get_scale(const struct motion_sensor_t *s, uint16_t *scale, + int16_t *temp); /* Start/Stop the FIFO collecting events */ int bmi_enable_fifo(const struct motion_sensor_t *s, int enable); @@ -311,9 +316,8 @@ int bmi_set_accel_offset(const struct motion_sensor_t *accel, intv3_t v); /* Set the gyroscope offset */ int bmi_set_gyro_offset(const struct motion_sensor_t *gyro, intv3_t v, - int *val98_ptr); + int *val98_ptr); -int bmi_list_activities(const struct motion_sensor_t *s, - uint32_t *enabled, +int bmi_list_activities(const struct motion_sensor_t *s, uint32_t *enabled, uint32_t *disabled); #endif /* __CROS_EC_ACCELGYRO_BMI_COMMON_H */ -- cgit v1.2.1 From 8b1056cf3e7405a95946d58f317973ed22022627 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:27 -0600 Subject: board/kohaku/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97e000ff9425f56731757cb426487a7544e45ea5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728565 Reviewed-by: Jeremy Bettis --- board/kohaku/led.c | 74 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 35 deletions(-) diff --git a/board/kohaku/led.c b/board/kohaku/led.c index 029cf5c315..afb6122fa3 100644 --- a/board/kohaku/led.c +++ b/board/kohaku/led.c @@ -12,8 +12,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -21,32 +21,35 @@ __override const int led_charge_lvl_2 = 100; /* Kohaku : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -54,12 +57,11 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } - if (color == EC_LED_COLOR_BLUE) - { + if (color == EC_LED_COLOR_BLUE) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL); @@ -73,15 +75,14 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } /* Battery leds must be turn off when blue led is on * because kohaku has 3-in-1 led. */ - if(!gpio_get_level(GPIO_PWR_LED_BLUE_L)) - { + if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); return; @@ -117,10 +118,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]); - gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]); + gpio_set_level(GPIO_BAT_LED_GREEN_L, + !brightness[EC_LED_COLOR_GREEN]); + gpio_set_level(GPIO_BAT_LED_RED_L, + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { - gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]); + gpio_set_level(GPIO_PWR_LED_BLUE_L, + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 4136dd10224458a0a05f6e41d92a887390223467 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:58 -0600 Subject: common/usbc/tbt_alt_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15f4db3d5f3dd38f8535a8390ccd99cd24edfaf2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729782 Reviewed-by: Jeremy Bettis --- common/usbc/tbt_alt_mode.c | 116 +++++++++++++++++++++------------------------ 1 file changed, 55 insertions(+), 61 deletions(-) diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index 5baf9d1a73..479d83644a 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -57,8 +57,8 @@ */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -70,8 +70,8 @@ * with a partner. It may be fixed in b/159495742, in which case this * logic is unneeded. */ -#define TBT_FLAG_RETRY_DONE BIT(0) -#define TBT_FLAG_EXIT_DONE BIT(1) +#define TBT_FLAG_RETRY_DONE BIT(0) +#define TBT_FLAG_EXIT_DONE BIT(1) #define TBT_FLAG_CABLE_ENTRY_DONE BIT(2) static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -123,14 +123,12 @@ void tbt_init(int port) bool tbt_is_active(int port) { - return tbt_state[port] != TBT_INACTIVE && - tbt_state[port] != TBT_START; + return tbt_state[port] != TBT_INACTIVE && tbt_state[port] != TBT_START; } bool tbt_entry_is_done(int port) { - return tbt_state[port] == TBT_ACTIVE || - tbt_state[port] == TBT_INACTIVE; + return tbt_state[port] == TBT_ACTIVE || tbt_state[port] == TBT_INACTIVE; } bool tbt_cable_entry_is_done(int port) @@ -140,13 +138,15 @@ bool tbt_cable_entry_is_done(int port) static void tbt_exit_done(int port) { - /* - * If the EC exits an alt mode autonomously, don't try to enter it again. If - * the AP commands the EC to exit DP mode, it might command the EC to enter - * again later, so leave the state machine ready for that possibility. - */ - tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) - ? TBT_START : TBT_INACTIVE; + /* + * If the EC exits an alt mode autonomously, don't try to enter it + * again. If the AP commands the EC to exit DP mode, it might command + * the EC to enter again later, so leave the state machine ready for + * that possibility. + */ + tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? + TBT_START : + TBT_INACTIVE; TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE); TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE); @@ -180,18 +180,20 @@ void tbt_exit_mode_request(int port) * with Thunderbolt mode for SOP prime. Hence, on request to * exit, only exit Thunderbolt mode SOP prime */ - tbt_state[port] = - cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ? - TBT_EXIT_SOP_PRIME : TBT_EXIT_SOP_PRIME_PRIME; + tbt_state[port] = cable_mode_resp.tbt_active_passive == + TBT_CABLE_ACTIVE ? + TBT_EXIT_SOP_PRIME : + TBT_EXIT_SOP_PRIME_PRIME; } } -static bool tbt_response_valid(int port, enum tcpci_msg_type type, - char *cmdt, int vdm_cmd) +static bool tbt_response_valid(int port, enum tcpci_msg_type type, char *cmdt, + int vdm_cmd) { enum tbt_states st = tbt_state[port]; union tbt_mode_resp_cable cable_mode_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) + }; /* * Check for an unexpected response. @@ -245,7 +247,7 @@ bool tbt_cable_entry_required_for_usb4(int port) return false; cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) return true; @@ -254,14 +256,14 @@ bool tbt_cable_entry_required_for_usb4(int port) disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 || disc_sop_prime->identity.product_t1.a_rev30.vdo_ver < - VDO_VERSION_1_3) + VDO_VERSION_1_3) return true; } return false; } void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { const struct pd_discovery *disc; const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]); @@ -277,7 +279,7 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, case TBT_ENTER_SOP_PRIME: tbt_prints("enter mode SOP'", port); cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); /* For LRD cables, Enter mode SOP' -> Enter mode SOP */ if (disc->identity.product_t1.a_rev20.sop_p_p && cable_mode_resp.tbt_active_passive != TBT_CABLE_ACTIVE) { @@ -330,13 +332,12 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, * Exit mode process is complete; go to inactive state. */ tbt_exit_done(port); - opos_sop_prime = - pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL); + opos_sop_prime = pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); /* Clear Thunderbolt related signals */ pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL, opos_sop_prime); + USB_VID_INTEL, opos_sop_prime); set_usb_mux_with_current_data_role(port); } else { tbt_retry_enter_mode(port); @@ -351,8 +352,8 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, break; default: /* Invalid or unexpected negotiation state */ - CPRINTF("%s called with invalid state %d\n", - __func__, tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + tbt_state[port]); tbt_exit_done(port); break; } @@ -406,8 +407,8 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) } break; default: - CPRINTS("C%d: NAK for cmd %d in state %d", port, - vdm_cmd, tbt_state[port]); + CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd, + tbt_state[port]); tbt_exit_done(port); break; } @@ -416,7 +417,7 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) static bool tbt_mode_is_supported(int port, int vdo_count) { const struct pd_discovery *disc = - pd_get_am_discovery(port, TCPCI_MSG_SOP); + pd_get_am_discovery(port, TCPCI_MSG_SOP); if (!disc->identity.idh.modal_support) return false; @@ -430,8 +431,8 @@ static bool tbt_mode_is_supported(int port, int vdo_count) * SVID USB_VID_INTEL to enter Thunderbolt alt mode */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE && - !pd_is_mode_discovered_for_svid( - port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL)) + !pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL)) return false; return true; @@ -486,14 +487,12 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, *tx_type = TCPCI_MSG_SOP_PRIME; break; case TBT_ENTER_SOP_PRIME_PRIME: - vdo_count_ret = - enter_tbt_compat_mode( - port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); + vdo_count_ret = enter_tbt_compat_mode( + port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_ENTER_SOP: - vdo_count_ret = - enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); + vdo_count_ret = enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); break; case TBT_ACTIVE: /* @@ -515,43 +514,38 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, return MSG_SETUP_MUX_WAIT; case TBT_EXIT_SOP: /* DPM will only call this after safe state set is done */ - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP, USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS( - pd_get_vdo_ver(port, TCPCI_MSG_SOP)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)); vdo_count_ret = 1; break; case TBT_EXIT_SOP_PRIME_PRIME: - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver(port, - TCPCI_MSG_SOP_PRIME_PRIME)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver( + port, TCPCI_MSG_SOP_PRIME_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_EXIT_SOP_PRIME: - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver(port, - TCPCI_MSG_SOP_PRIME)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS( + pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME; break; @@ -559,8 +553,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, /* Thunderbolt mode is inactive */ return MSG_SETUP_UNSUPPORTED; default: - CPRINTF("%s called with invalid state %d\n", - __func__, tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + tbt_state[port]); return MSG_SETUP_ERROR; } -- cgit v1.2.1 From d2e674b699f0ceef21cfd7b0bd11f23bd4af6913 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:05 -0600 Subject: board/kano/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6cc9bb69d09dc15bddeedffbe80c353b3d1de345 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728485 Reviewed-by: Jeremy Bettis --- board/kano/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/kano/usbc_config.h b/board/kano/usbc_config.h index 38fce7d2cf..0422f9fc58 100644 --- a/board/kano/usbc_config.h +++ b/board/kano/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From d36b6ee3bd07b03f5336929baca8a8acc6ddfd47 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:46 -0600 Subject: include/update_fw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c9b3790699a4385368fc3963e7eda57b5e37c0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730426 Reviewed-by: Jeremy Bettis --- include/update_fw.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/include/update_fw.h b/include/update_fw.h index d345c4f667..35c911911b 100644 --- a/include/update_fw.h +++ b/include/update_fw.h @@ -43,8 +43,8 @@ * block_base: offset of this PDU into the flash SPI. */ struct update_command { - uint32_t block_digest; - uint32_t block_base; + uint32_t block_digest; + uint32_t block_base; /* The actual payload goes here. */ } __packed; @@ -112,8 +112,8 @@ struct first_response_pdu { /* cr50 (header_type = UPDATE_HEADER_TYPE_CR50) */ struct { /* The below fields are present in versions 3 and up. */ - uint32_t backup_ro_offset; - uint32_t backup_rw_offset; + uint32_t backup_ro_offset; + uint32_t backup_rw_offset; /* The below fields are present in versions 4 and up. */ /* @@ -154,8 +154,8 @@ enum first_response_pdu_header_type { }; /* TODO: Handle this in update_fw.c, not usb_update.c */ -#define UPDATE_DONE 0xB007AB1E -#define UPDATE_EXTRA_CMD 0xB007AB1F +#define UPDATE_DONE 0xB007AB1E +#define UPDATE_EXTRA_CMD 0xB007AB1F enum update_extra_command { UPDATE_EXTRA_CMD_IMMEDIATE_RESET = 0, @@ -235,8 +235,7 @@ struct touchpad_info { */ BUILD_ASSERT(sizeof(struct touchpad_info) <= 50); -void fw_update_command_handler(void *body, - size_t cmd_size, +void fw_update_command_handler(void *body, size_t cmd_size, size_t *response_size); /* Used to tell fw update the update ran successfully and is finished */ @@ -286,4 +285,4 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, /* SHA256 hash of the touchpad firmware expected by this image. */ extern const uint8_t touchpad_fw_full_hash[32]; -#endif /* ! __CROS_EC_UPDATE_FW_H */ +#endif /* ! __CROS_EC_UPDATE_FW_H */ -- cgit v1.2.1 From b0e8de4155e0cce579be0b391df5cff44fc3a693 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:00 -0600 Subject: chip/max32660/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1216cabe2ca1d5dac5bea523fc32774d7e661507 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729228 Reviewed-by: Jeremy Bettis --- chip/max32660/config_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/max32660/config_chip.h b/chip/max32660/config_chip.h index c97c246bb7..bdaa71beca 100644 --- a/chip/max32660/config_chip.h +++ b/chip/max32660/config_chip.h @@ -50,7 +50,7 @@ #define TASK_STACK_SIZE 512 #define CONFIG_PROGRAM_MEMORY_BASE 0x00000000 -#define CONFIG_FLASH_BANK_SIZE 0x00002000 /* protect bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x00002000 /* protect bank size */ #define CONFIG_FLASH_ERASE_SIZE 0x00002000 /* erase bank size */ #define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* minimum write size */ -- cgit v1.2.1 From 009928b12bb00c61a4958f4cf726862ccbcecb72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:00 -0600 Subject: board/gumboz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8fafe34700b239bd85ab6041e3082488f44feef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728433 Reviewed-by: Jeremy Bettis --- board/gumboz/board.c | 55 +++++++++++++++++++++------------------------------- 1 file changed, 22 insertions(+), 33 deletions(-) diff --git a/board/gumboz/board.c b/board/gumboz/board.c index f90902f765..e3119dc6f6 100644 --- a/board/gumboz/board.c +++ b/board/gumboz/board.c @@ -36,8 +36,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* This I2C moved. Temporarily detect and support the V0 HW. */ int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1; @@ -49,21 +49,17 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* sensor private data */ -static struct kionix_accel_data g_kx022_data; +static struct kionix_accel_data g_kx022_data; static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ struct motion_sensor_t motion_sensors[] = { @@ -268,8 +264,7 @@ void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -290,7 +285,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -392,7 +386,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -463,11 +456,9 @@ int board_pd_set_frs_enable(int port, int enable) /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -539,14 +530,13 @@ int usb_port_enable[USBA_PORT_COUNT] = { * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, - {1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1}, - {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, - {2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2}, - {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, { 1, 4 }, + { 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, + { 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, + { 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif #define CHARGING_CURRENT_500MA 500 @@ -586,12 +576,11 @@ int charger_profile_override(struct charge_state_data *curr) if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) return 0; - curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA - : curr->batt.desired_current; + curr->requested_current = (limit_charge) ? CHARGING_CURRENT_500MA : + curr->batt.desired_current; if (limit_usbc_power != limit_usbc_power_backup) { - rp = (limit_usbc_power) ? TYPEC_RP_1A5 - : TYPEC_RP_3A0; + rp = (limit_usbc_power) ? TYPEC_RP_1A5 : TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); @@ -605,13 +594,13 @@ int charger_profile_override(struct charge_state_data *curr) } enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { return EC_RES_INVALID_PARAM; } -- cgit v1.2.1 From c2f0edecfa198ed855e526a7d24305c6cfb74890 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:00 -0600 Subject: board/brask/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie89a3d46915434352e27d3793243356ff3d1ddef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728093 Reviewed-by: Jeremy Bettis --- board/brask/fw_config.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/board/brask/fw_config.h b/board/brask/fw_config.h index 5ddb3b02a1..ff1f3583fe 100644 --- a/board/brask/fw_config.h +++ b/board/brask/fw_config.h @@ -13,15 +13,9 @@ * * Source of truth is the project/brask/brask/config.star configuration file. */ -enum ec_cfg_audio_type { - DB_AUDIO_UNKNOWN = 0, - DB_NAU88L25B_I2S = 1 -}; +enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 }; -enum ec_cfg_bj_power { - BJ_135W = 0, - BJ_230W = 1 -}; +enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 }; union brask_cbi_fw_config { struct { -- cgit v1.2.1 From 87ea38dd1ad52460a3194f726722d81fd8c98a73 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:57 -0600 Subject: board/wheelie/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5213f5a4af8dfe8ad693e6cc92b95e5dc7b195a6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729129 Reviewed-by: Jeremy Bettis --- board/wheelie/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/wheelie/usb_pd_policy.c b/board/wheelie/usb_pd_policy.c index 02ae21a420..ec6e91269a 100644 --- a/board/wheelie/usb_pd_policy.c +++ b/board/wheelie/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 0843a77044cfd28fd05f210f63bad8fdb1d56999 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:32 -0600 Subject: board/shotzo/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc898c733c41285aaa31b003dfcd9f175a5943bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728939 Reviewed-by: Jeremy Bettis --- board/shotzo/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/shotzo/cbi_ssfc.c b/board/shotzo/cbi_ssfc.c index 9f1383b455..37bd3d1520 100644 --- a/board/shotzo/cbi_ssfc.c +++ b/board/shotzo/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 090f6912efccf65ed6027dc7bfb9e8bc04039d5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:07 -0600 Subject: driver/mp2964.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I96050e7e824efdad020b2eec123c347de506150e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730029 Reviewed-by: Jeremy Bettis --- driver/mp2964.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/driver/mp2964.c b/driver/mp2964.c index 21a23a8f4c..e5a94fecc2 100644 --- a/driver/mp2964.c +++ b/driver/mp2964.c @@ -11,22 +11,18 @@ #include "timer.h" #include "util.h" -#define MP2964_STARTUP_WAIT_US (50 * MSEC) -#define MP2964_STORE_WAIT_US (300 * MSEC) -#define MP2964_RESTORE_WAIT_US (2 * MSEC) +#define MP2964_STARTUP_WAIT_US (50 * MSEC) +#define MP2964_STORE_WAIT_US (300 * MSEC) +#define MP2964_RESTORE_WAIT_US (2 * MSEC) -enum reg_page { - REG_PAGE_0, - REG_PAGE_1, - REG_PAGE_COUNT -}; +enum reg_page { REG_PAGE_0, REG_PAGE_1, REG_PAGE_COUNT }; static int mp2964_write8(uint8_t reg, uint8_t value) { const uint8_t tx[2] = { reg, value }; - return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, - tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE); + return i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx, + sizeof(tx), NULL, 0, I2C_XFER_SINGLE); } static void mp2964_read16(uint8_t reg, uint16_t *value) @@ -34,8 +30,8 @@ static void mp2964_read16(uint8_t reg, uint16_t *value) const uint8_t tx[1] = { reg }; uint8_t rx[2]; - i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, - tx, sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE); + i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx, + sizeof(tx), rx, sizeof(rx), I2C_XFER_SINGLE); *value = (rx[1] << 8) | rx[0]; } @@ -43,8 +39,8 @@ static void mp2964_write16(uint8_t reg, uint16_t value) { const uint8_t tx[3] = { reg, value & 0xff, value >> 8 }; - i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, - tx, sizeof(tx), NULL, 0, I2C_XFER_SINGLE); + i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, tx, + sizeof(tx), NULL, 0, I2C_XFER_SINGLE); } static int mp2964_select_page(enum reg_page page) @@ -92,15 +88,15 @@ static int mp2964_store_user_all(void) ccprintf("%s: updating persistent settings\n", __func__); - status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, - &wr, sizeof(wr), NULL, 0, I2C_XFER_SINGLE); + status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &wr, + sizeof(wr), NULL, 0, I2C_XFER_SINGLE); if (status != EC_SUCCESS) return status; usleep(MP2964_STORE_WAIT_US); - status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, - &rd, sizeof(rd), NULL, 0, I2C_XFER_SINGLE); + status = i2c_xfer_unlocked(I2C_PORT_MP2964, I2C_ADDR_MP2964_FLAGS, &rd, + sizeof(rd), NULL, 0, I2C_XFER_SINGLE); if (status != EC_SUCCESS) return status; @@ -110,8 +106,7 @@ static int mp2964_store_user_all(void) } static void mp2964_patch_rail(enum reg_page page, - const struct mp2964_reg_val *page_vals, - int count, + const struct mp2964_reg_val *page_vals, int count, int *delta) { if (mp2964_select_page(page) != EC_SUCCESS) -- cgit v1.2.1 From 40ff5d21ffb18f3a80cbc52f4632f74dc8004925 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:42 -0600 Subject: driver/temp_sensor/tmp468.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8492b721a71d35ce58f13692df7467439fa9c4e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729885 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp468.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/temp_sensor/tmp468.c b/driver/temp_sensor/tmp468.c index 46e77ca696..a14296768e 100644 --- a/driver/temp_sensor/tmp468.c +++ b/driver/temp_sensor/tmp468.c @@ -15,9 +15,9 @@ #include "tmp468.h" - -static int fake_temp[TMP468_CHANNEL_COUNT] = {-1, -1, -1, -1, -1, -1, -1 , -1, -1}; -static int temp_val[TMP468_CHANNEL_COUNT] = {0, 0, 0, 0, 0, 0, 0 , 0, 0}; +static int fake_temp[TMP468_CHANNEL_COUNT] = { -1, -1, -1, -1, -1, + -1, -1, -1, -1 }; +static int temp_val[TMP468_CHANNEL_COUNT] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }; static uint8_t is_sensor_shutdown; static int has_power(void) @@ -27,14 +27,14 @@ static int has_power(void) static int raw_read16(const int offset, int *data_ptr) { - return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset, + data_ptr); } static int raw_write16(const int offset, int data_ptr) { - return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_write16(I2C_PORT_THERMAL, TMP468_I2C_ADDR_FLAGS, offset, + data_ptr); } static int tmp468_shutdown(uint8_t want_shutdown) @@ -64,7 +64,7 @@ static int tmp468_shutdown(uint8_t want_shutdown) int tmp468_get_val(int idx, int *temp_ptr) { - if(!has_power()) + if (!has_power()) return EC_ERROR_NOT_POWERED; if (idx < TMP468_CHANNEL_COUNT) { -- cgit v1.2.1 From c65fceee11eb577555f2ee81811e1a8631acaf8f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:51 -0600 Subject: zephyr/test/drivers/src/console_cmd/charge_state.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6106ff351a8cbf620c4c0882840cee1200d70a8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730987 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/console_cmd/charge_state.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/zephyr/test/drivers/src/console_cmd/charge_state.c b/zephyr/test/drivers/src/console_cmd/charge_state.c index f66aa518db..384e7d84e3 100644 --- a/zephyr/test/drivers/src/console_cmd/charge_state.c +++ b/zephyr/test/drivers/src/console_cmd/charge_state.c @@ -180,9 +180,8 @@ static void *console_cmd_charge_state_setup(void) /* Initialized the source to supply 5V and 3A */ tcpci_partner_init(&fixture.source_5v_3a, PD_REV20); - fixture.source_5v_3a.extensions = - tcpci_src_emul_init(&fixture.source_ext, - &fixture.source_5v_3a, NULL); + fixture.source_5v_3a.extensions = tcpci_src_emul_init( + &fixture.source_ext, &fixture.source_5v_3a, NULL); fixture.source_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); -- cgit v1.2.1 From 8a16a5e84a48651acce0d976656a932020b099cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:04 -0600 Subject: board/redrix/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09c8503f167cb195ea97a26f64bcc1a707b10682 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728860 Reviewed-by: Jeremy Bettis --- board/redrix/fw_config.h | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/board/redrix/fw_config.h b/board/redrix/fw_config.h index 9a73890f7d..1153ee0e3e 100644 --- a/board/redrix/fw_config.h +++ b/board/redrix/fw_config.h @@ -19,20 +19,17 @@ enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_eps_type { - EPS_DISABLED = 0, - EPS_ENABLED = 1 -}; +enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 }; union redrix_cbi_fw_config { struct { - uint32_t sd_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t lte_db : 2; - uint32_t ufc : 2; - enum ec_cfg_eps_type eps : 1; - uint32_t reserved_1 : 21; + uint32_t sd_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t lte_db : 2; + uint32_t ufc : 2; + enum ec_cfg_eps_type eps : 1; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From 99836d146fa826c477af554ce864b9f07379f5a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:40 -0600 Subject: board/treeya/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2b451872c92580b596b8ff589b493e7dc7a5b5de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729032 Reviewed-by: Jeremy Bettis --- board/treeya/board.c | 104 ++++++++++++++++++++++----------------------------- 1 file changed, 45 insertions(+), 59 deletions(-) diff --git a/board/treeya/board.c b/board/treeya/board.c index 642948dbd0..0ee3baaca5 100644 --- a/board/treeya/board.c +++ b/board/treeya/board.c @@ -32,45 +32,35 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -83,19 +73,15 @@ static struct stprivate_data g_lis2dwl_data; /* Base accel private data */ static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA; - /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t lsm6dsm_base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lsm6dsm_base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, + FLOAT_TO_FP(1) } }; -static const mat33_fp_t treeya_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t treeya_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t lid_accel_1 = { .name = "Lid Accel", @@ -162,8 +148,7 @@ struct motion_sensor_t base_gyro_1 = { .location = MOTIONSENSE_LOC_BASE, .drv = &lsm6dsm_drv, .mutex = &g_base_mutex_1, - .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, - MOTIONSENSE_TYPE_GYRO), + .drv_data = LSM6DSM_ST_DATA(g_lsm6dsm_data, MOTIONSENSE_TYPE_GYRO), .port = I2C_PORT_ACCEL, .i2c_spi_addr_flags = LSM6DSM_ADDR0_FLAGS, .default_range = 1000 | ROUND_UP_FLAG, /* dps */ @@ -177,8 +162,8 @@ static int board_use_st_sensor(void) /* sku_id 0xa8-0xa9, 0xbe, 0xbf use ST sensors */ uint32_t sku_id = system_get_sku_id(); - if (sku_id == 0xa8 || sku_id == 0xa9 || - sku_id == 0xbe || sku_id == 0xbf) + if (sku_id == 0xa8 || sku_id == 0xa9 || sku_id == 0xbe || + sku_id == 0xbf) return 1; else return 0; @@ -197,10 +182,12 @@ void board_update_sensor_config_from_sku(void) motion_sensors[LID_ACCEL] = lid_accel_1; motion_sensors[BASE_ACCEL] = base_accel_1; motion_sensors[BASE_GYRO] = base_gyro_1; - } else{ + } else { /*Need to change matrix for treeya*/ - motion_sensors[BASE_ACCEL].rot_standard_ref = &treeya_standard_ref; - motion_sensors[BASE_GYRO].rot_standard_ref = &treeya_standard_ref; + motion_sensors[BASE_ACCEL].rot_standard_ref = + &treeya_standard_ref; + motion_sensors[BASE_GYRO].rot_standard_ref = + &treeya_standard_ref; } /* Enable Gyro interrupts */ @@ -210,12 +197,11 @@ void board_update_sensor_config_from_sku(void) /* Device is clamshell only */ tablet_set_mode(0, TABLET_TRIGGER_LID); /* Gyro is not present, don't allow line to float */ - gpio_set_flags(GPIO_6AXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_6AXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } - if (sku_id == 160 || sku_id == 168 || sku_id == 169 || - sku_id == 190 || sku_id == 191) { + if (sku_id == 160 || sku_id == 168 || sku_id == 169 || sku_id == 190 || + sku_id == 191) { is_psl_hibernate = 0; } else { is_psl_hibernate = 1; @@ -312,7 +298,7 @@ void board_hibernate_late(void) } /* Clear all pending IRQ otherwise wfi will have no affect */ - for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++) + for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++) task_clear_pending_irq(i); __enter_hibernate_in_psl(); -- cgit v1.2.1 From c23ad60ae2404f1ac280f3777eabad80d7079591 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:30 -0600 Subject: board/agah/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I71ba9504652a274acee781a0fff3be3c10a0c355 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727098 Reviewed-by: Jeremy Bettis --- board/agah/keyboard.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/agah/keyboard.c b/board/agah/keyboard.c index d234dfd64e..da5174ee37 100644 --- a/board/agah/keyboard.c +++ b/board/agah/keyboard.c @@ -45,7 +45,6 @@ static const struct ec_response_keybd_config keybd = { .capabilities = KEYBD_CAP_NUMERIC_KEYPAD, }; - __override const struct ec_response_keybd_config * board_vivaldi_keybd_config(void) { -- cgit v1.2.1 From 9d81a0b39501c8bf23b20595097df3b311b56b0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:28 -0600 Subject: driver/ioexpander/it8300.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0e063b2509ff5c25c965ce441ae7e05f76a1ed5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729984 Reviewed-by: Jeremy Bettis --- driver/ioexpander/it8300.h | 150 ++++++++++++++++++++++----------------------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/driver/ioexpander/it8300.h b/driver/ioexpander/it8300.h index 2b47e7f3e1..fa4a251fcd 100644 --- a/driver/ioexpander/it8300.h +++ b/driver/ioexpander/it8300.h @@ -11,96 +11,96 @@ #include "i2c.h" /* Gather Interrupt Status Register */ -#define IT8300_GISR 0x0 +#define IT8300_GISR 0x0 /* Interrupt Status Registers */ -#define IT8300_ISR_A 0x6 -#define IT8300_ISR_B 0x7 -#define IT8300_ISR_C 0x28 -#define IT8300_ISR_D 0x2E -#define IT8300_ISR_E 0x2F +#define IT8300_ISR_A 0x6 +#define IT8300_ISR_B 0x7 +#define IT8300_ISR_C 0x28 +#define IT8300_ISR_D 0x2E +#define IT8300_ISR_E 0x2F /* Port Data Register Groups */ -#define IT8300_PDGR_A 0x1 -#define IT8300_PDGR_B 0x2 -#define IT8300_PDGR_C 0x3 -#define IT8300_PDGR_D 0x4 -#define IT8300_PDGR_E 0x5 +#define IT8300_PDGR_A 0x1 +#define IT8300_PDGR_B 0x2 +#define IT8300_PDGR_C 0x3 +#define IT8300_PDGR_D 0x4 +#define IT8300_PDGR_E 0x5 /* GPIO Port Control n Registers */ -#define IT8300_GPCR_A0 0x10 -#define IT8300_GPCR_A1 0x11 -#define IT8300_GPCR_A2 0x12 -#define IT8300_GPCR_A3 0x13 -#define IT8300_GPCR_A4 0x14 -#define IT8300_GPCR_A5 0x15 -#define IT8300_GPCR_A6 0x16 -#define IT8300_GPCR_A7 0x17 - -#define IT8300_GPCR_B0 0x18 -#define IT8300_GPCR_B1 0x19 -#define IT8300_GPCR_B2 0x1A -#define IT8300_GPCR_B3 0x1B -#define IT8300_GPCR_B4 0x1C -#define IT8300_GPCR_B5 0x1D -#define IT8300_GPCR_B6 0x1E - -#define IT8300_GPCR_C0 0x20 -#define IT8300_GPCR_C1 0x21 -#define IT8300_GPCR_C2 0x22 -#define IT8300_GPCR_C3 0x23 -#define IT8300_GPCR_C4 0x24 -#define IT8300_GPCR_C5 0x25 -#define IT8300_GPCR_C6 0x26 - -#define IT8300_GPCR_D0 0x08 -#define IT8300_GPCR_D1 0x09 -#define IT8300_GPCR_D2 0x0A -#define IT8300_GPCR_D3 0x0B -#define IT8300_GPCR_D4 0x0C -#define IT8300_GPCR_D5 0x0D - -#define IT8300_GPCR_E0 0x32 - -#define IT8300_GPCR_E2 0x34 -#define IT8300_GPCR_E3 0x35 -#define IT8300_GPCR_E4 0x36 -#define IT8300_GPCR_E5 0x37 -#define IT8300_GPCR_E6 0x38 - -#define IT8300_GPCR_GPI_MODE BIT(7) -#define IT8300_GPCR_GP0_MODE BIT(6) -#define IT8300_GPCR_PULL_UP_EN BIT(2) -#define IT8300_GPCR_PULL_DN_EN BIT(1) +#define IT8300_GPCR_A0 0x10 +#define IT8300_GPCR_A1 0x11 +#define IT8300_GPCR_A2 0x12 +#define IT8300_GPCR_A3 0x13 +#define IT8300_GPCR_A4 0x14 +#define IT8300_GPCR_A5 0x15 +#define IT8300_GPCR_A6 0x16 +#define IT8300_GPCR_A7 0x17 + +#define IT8300_GPCR_B0 0x18 +#define IT8300_GPCR_B1 0x19 +#define IT8300_GPCR_B2 0x1A +#define IT8300_GPCR_B3 0x1B +#define IT8300_GPCR_B4 0x1C +#define IT8300_GPCR_B5 0x1D +#define IT8300_GPCR_B6 0x1E + +#define IT8300_GPCR_C0 0x20 +#define IT8300_GPCR_C1 0x21 +#define IT8300_GPCR_C2 0x22 +#define IT8300_GPCR_C3 0x23 +#define IT8300_GPCR_C4 0x24 +#define IT8300_GPCR_C5 0x25 +#define IT8300_GPCR_C6 0x26 + +#define IT8300_GPCR_D0 0x08 +#define IT8300_GPCR_D1 0x09 +#define IT8300_GPCR_D2 0x0A +#define IT8300_GPCR_D3 0x0B +#define IT8300_GPCR_D4 0x0C +#define IT8300_GPCR_D5 0x0D + +#define IT8300_GPCR_E0 0x32 + +#define IT8300_GPCR_E2 0x34 +#define IT8300_GPCR_E3 0x35 +#define IT8300_GPCR_E4 0x36 +#define IT8300_GPCR_E5 0x37 +#define IT8300_GPCR_E6 0x38 + +#define IT8300_GPCR_GPI_MODE BIT(7) +#define IT8300_GPCR_GP0_MODE BIT(6) +#define IT8300_GPCR_PULL_UP_EN BIT(2) +#define IT8300_GPCR_PULL_DN_EN BIT(1) /* EXGPIO Clear Alert */ -#define IT8300_ECA 0x30 +#define IT8300_ECA 0x30 /* EXGPIO Alert Enable */ -#define IT8300_EAE 0x31 +#define IT8300_EAE 0x31 /* Port Data Mirror Registers */ -#define IT8300_PDMRA_A 0x29 -#define IT8300_PDMRA_B 0x2A -#define IT8300_PDMRA_C 0x2B -#define IT8300_PDMRA_D 0x2C -#define IT8300_PDMRA_E 0x2D +#define IT8300_PDMRA_A 0x29 +#define IT8300_PDMRA_B 0x2A +#define IT8300_PDMRA_C 0x2B +#define IT8300_PDMRA_D 0x2C +#define IT8300_PDMRA_E 0x2D /* Output Open-Drain Enable Registers */ -#define IT8300_OODER_A 0x39 -#define IT8300_OODER_B 0x3A -#define IT8300_OODER_C 0x3B -#define IT8300_OODER_D 0x3C -#define IT8300_OODER_E 0x3D +#define IT8300_OODER_A 0x39 +#define IT8300_OODER_B 0x3A +#define IT8300_OODER_C 0x3B +#define IT8300_OODER_D 0x3C +#define IT8300_OODER_E 0x3D /* IT83200 Port GPIOs */ -#define IT8300_GPX_0 BIT(0) -#define IT8300_GPX_1 BIT(1) -#define IT8300_GPX_2 BIT(2) -#define IT8300_GPX_3 BIT(3) -#define IT8300_GPX_4 BIT(4) -#define IT8300_GPX_5 BIT(5) -#define IT8300_GPX_6 BIT(6) -#define IT8300_GPX_7 BIT(7) +#define IT8300_GPX_0 BIT(0) +#define IT8300_GPX_1 BIT(1) +#define IT8300_GPX_2 BIT(2) +#define IT8300_GPX_3 BIT(3) +#define IT8300_GPX_4 BIT(4) +#define IT8300_GPX_5 BIT(5) +#define IT8300_GPX_6 BIT(6) +#define IT8300_GPX_7 BIT(7) #endif /* __CROS_EC_IOEXPANDER_IT8300_H */ -- cgit v1.2.1 From 2a6dec3e383d0008354fcb86c921c2308effacfd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:46 -0600 Subject: board/shuboz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib115d67f9762ff4b8556ecef2bd68fadb3a69680 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728942 Reviewed-by: Jeremy Bettis --- board/shuboz/board.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/board/shuboz/board.c b/board/shuboz/board.c index 027a6ee634..220ca09541 100644 --- a/board/shuboz/board.c +++ b/board/shuboz/board.c @@ -39,8 +39,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* This I2C moved. Temporarily detect and support the V0 HW. */ int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1; @@ -62,15 +62,13 @@ static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, { 0, 0, FLOAT_TO_FP(-1) }, }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static const mat33_fp_t base_standard_ref_icm = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(-1)}, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) }, }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ @@ -226,8 +224,7 @@ static void board_chipset_suspend(void) } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int res; @@ -242,7 +239,6 @@ static int board_ps8743_mux_set(const struct usb_mux *me, return res; } - /***************************************************************************** * USB-C */ @@ -350,8 +346,7 @@ void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -372,7 +367,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -474,7 +468,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -545,11 +538,9 @@ int board_pd_set_frs_enable(int port, int enable) /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; -- cgit v1.2.1 From 596352119453f356c9aa258df81da05a734e2181 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:31 -0600 Subject: board/kindred/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4622b97f80445241406ec82f3abec05569c1fdab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728532 Reviewed-by: Jeremy Bettis --- board/kindred/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/kindred/led.c b/board/kindred/led.c index ff91d15424..87e7f9d1ca 100644 --- a/board/kindred/led.c +++ b/board/kindred/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 9e60f84db53298d1af662f971ece206a2654856b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:45 -0600 Subject: driver/usb_mux/ps8743.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I81a848f4a3b4d95f6268ded44c619e7f4020b301 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730168 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8743.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/driver/usb_mux/ps8743.h b/driver/usb_mux/ps8743.h index 8e3a9d9b4c..daa33111ff 100644 --- a/driver/usb_mux/ps8743.h +++ b/driver/usb_mux/ps8743.h @@ -14,30 +14,30 @@ /* Status register for checking mux state */ #define PS8743_REG_STATUS 0x09 #define PS8743_STATUS_POLARITY_INVERTED BIT(2) -#define PS8743_STATUS_USB_ENABLED BIT(3) -#define PS8743_STATUS_DP_ENABLED BIT(4) -#define PS8743_STATUS_HPD_ASSERTED BIT(7) +#define PS8743_STATUS_USB_ENABLED BIT(3) +#define PS8743_STATUS_DP_ENABLED BIT(4) +#define PS8743_STATUS_HPD_ASSERTED BIT(7) /* Chip ID / revision registers and expected fused values */ #define PS8743_REG_REVISION_ID1 0xf0 #define PS8743_REG_REVISION_ID2 0xf1 -#define PS8743_REG_CHIP_ID1 0xf2 -#define PS8743_REG_CHIP_ID2 0xf3 -#define PS8743_REVISION_ID1_0 0x00 -#define PS8743_REVISION_ID1_1 0x01 -#define PS8743_REVISION_ID2 0x0b -#define PS8743_CHIP_ID1 0x41 -#define PS8743_CHIP_ID2 0x87 +#define PS8743_REG_CHIP_ID1 0xf2 +#define PS8743_REG_CHIP_ID2 0xf3 +#define PS8743_REVISION_ID1_0 0x00 +#define PS8743_REVISION_ID1_1 0x01 +#define PS8743_REVISION_ID2 0x0b +#define PS8743_CHIP_ID1 0x41 +#define PS8743_CHIP_ID2 0x87 /* Misc register for checking DCI / SS pair mode status */ -#define PS8743_MISC_DCI_SS_MODES 0x42 +#define PS8743_MISC_DCI_SS_MODES 0x42 #define PS8743_SSTX_NORMAL_OPERATION_MODE BIT(4) -#define PS8743_SSTX_POWER_SAVING_MODE BIT(5) -#define PS8743_SSTX_SUSPEND_MODE BIT(6) +#define PS8743_SSTX_POWER_SAVING_MODE BIT(5) +#define PS8743_SSTX_SUSPEND_MODE BIT(6) /* Misc resiger for checking HPD / DP / USB / FLIP mode status */ #define PS8743_MISC_HPD_DP_USB_FLIP 0x09 -#define PS8743_USB_MODE_STATUS BIT(3) -#define PS8743_DP_MODE_STATUS BIT(4) +#define PS8743_USB_MODE_STATUS BIT(3) +#define PS8743_DP_MODE_STATUS BIT(4) #endif /* __CROS_EC_PS8743_H */ -- cgit v1.2.1 From f82b4c352b5556fb37dea799f5df672f43af4e2d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:53 -0600 Subject: driver/temp_sensor/bd99992gw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iece4dcc6c911cf28efe39cb6ca134fcb7975d0d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730113 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/bd99992gw.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/driver/temp_sensor/bd99992gw.c b/driver/temp_sensor/bd99992gw.c index e66642224c..f74f0448b4 100644 --- a/driver/temp_sensor/bd99992gw.c +++ b/driver/temp_sensor/bd99992gw.c @@ -23,7 +23,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) /* List of active channels, ordered by pointer register */ static enum bd99992gw_adc_channel @@ -39,8 +39,8 @@ static enum bd99992gw_adc_channel static int raw_read8(const int offset, int *data_ptr) { int ret; - ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, - offset, data_ptr); + ret = i2c_read8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset, + data_ptr); if (ret != EC_SUCCESS) CPRINTS("bd99992gw read fail %d", ret); return ret; @@ -49,8 +49,8 @@ static int raw_read8(const int offset, int *data_ptr) static int raw_write8(const int offset, int data) { int ret; - ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, - offset, data); + ret = i2c_write8(I2C_PORT_THERMAL, BD99992GW_I2C_ADDR_FLAGS, offset, + data); if (ret != EC_SUCCESS) CPRINTS("bd99992gw write fail %d", ret); return ret; @@ -79,9 +79,11 @@ static void bd99992gw_init(void) /* Now write pointer regs with channel to monitor */ for (i = 0; i < active_channel_count; ++i) /* Write stop bit on last channel */ - if (raw_write8(pointer_reg + i, active_channels[i] | - ((i == active_channel_count - 1) ? - BD99992GW_ADC1ADDR_STOP : 0))) + if (raw_write8(pointer_reg + i, + active_channels[i] | + ((i == active_channel_count - 1) ? + BD99992GW_ADC1ADDR_STOP : + 0))) return; /* Enable ADC interrupts */ @@ -96,7 +98,8 @@ static void bd99992gw_init(void) /* Start round-robin conversions at 27ms period */ raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD | - BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT); + BD99992GW_ADC1CNTL1_ADEN | + BD99992GW_ADC1CNTL1_ADSTRT); } /* * Some regs only work in S0, so we must initialize on AP startup in @@ -130,24 +133,20 @@ int bd99992gw_get_val(int idx, int *temp_ptr) /* Find requested channel */ for (i = 0; i < ARRAY_SIZE(active_channels); ++i) { channel = active_channels[i]; - if (channel == idx || - channel == BD99992GW_ADC_CHANNEL_NONE) + if (channel == idx || channel == BD99992GW_ADC_CHANNEL_NONE) break; } /* Make sure we found it */ - if (i == ARRAY_SIZE(active_channels) || - active_channels[i] != idx) { + if (i == ARRAY_SIZE(active_channels) || active_channels[i] != idx) { CPRINTS("Bad ADC channel %d", idx); return EC_ERROR_INVAL; } /* Pause conversions */ - ret = raw_write8(0x80, - ADC_LOOP_PERIOD | - BD99992GW_ADC1CNTL1_ADEN | - BD99992GW_ADC1CNTL1_ADSTRT | - BD99992GW_ADC1CNTL1_ADPAUSE); + ret = raw_write8(0x80, ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN | + BD99992GW_ADC1CNTL1_ADSTRT | + BD99992GW_ADC1CNTL1_ADPAUSE); if (ret) return ret; @@ -173,8 +172,9 @@ int bd99992gw_get_val(int idx, int *temp_ptr) return ret; /* Resume conversions */ - ret = raw_write8(BD99992GW_REG_ADC1CNTL1, ADC_LOOP_PERIOD | - BD99992GW_ADC1CNTL1_ADEN | BD99992GW_ADC1CNTL1_ADSTRT); + ret = raw_write8(BD99992GW_REG_ADC1CNTL1, + ADC_LOOP_PERIOD | BD99992GW_ADC1CNTL1_ADEN | + BD99992GW_ADC1CNTL1_ADSTRT); if (ret) return ret; -- cgit v1.2.1 From a19c1410e48baeb4c9db0d0e218a17872b94f5ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:41 -0600 Subject: include/clock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I573da1da9c2fe0adcd8017818fb0f4f0c539e46a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730228 Reviewed-by: Jeremy Bettis --- include/clock.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/clock.h b/include/clock.h index c64cfe4db5..fc21a45ac6 100644 --- a/include/clock.h +++ b/include/clock.h @@ -78,10 +78,10 @@ enum bus_type { void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles); /* Clock gate control modes for clock_enable_peripheral() */ -#define CGC_MODE_RUN BIT(0) -#define CGC_MODE_SLEEP BIT(1) +#define CGC_MODE_RUN BIT(0) +#define CGC_MODE_SLEEP BIT(1) #define CGC_MODE_DSLEEP BIT(2) -#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP) +#define CGC_MODE_ALL (CGC_MODE_RUN | CGC_MODE_SLEEP | CGC_MODE_DSLEEP) /** * Enable clock to peripheral by setting the CGC register pertaining @@ -108,4 +108,4 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode); */ void clock_refresh_console_in_use(void); -#endif /* __CROS_EC_CLOCK_H */ +#endif /* __CROS_EC_CLOCK_H */ -- cgit v1.2.1 From 6b73a382cb4e4107dd3da667aa34eca7e876a3c1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:53 -0600 Subject: zephyr/shim/src/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8faa6e36dac7495d740fb0cb5647b14e22145992 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730891 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/fan.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c index 3531941a08..48a452fc13 100644 --- a/zephyr/shim/src/fan.c +++ b/zephyr/shim/src/fan.c @@ -25,8 +25,8 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define FAN_CONFIGS(node_id) \ const struct fan_conf node_id##_conf = { \ - .flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode), \ - (0), (FAN_USE_RPM_MODE))) | \ + .flags = (COND_CODE_1(DT_PROP(node_id, not_use_rpm_mode), (0), \ + (FAN_USE_RPM_MODE))) | \ (COND_CODE_1(DT_PROP(node_id, use_fast_start), \ (FAN_USE_FAST_START), (0))), \ .ch = node_id, \ @@ -45,26 +45,24 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, .rpm_max = DT_PROP(node_id, rpm_max), \ }; -#define FAN_INST(node_id) \ - [node_id] = { \ +#define FAN_INST(node_id) \ + [node_id] = { \ .conf = &node_id##_conf, \ .rpm = &node_id##_rpm, \ }, -#define FAN_CONTROL_INST(node_id) \ - [node_id] = { \ - .pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ - .channel = DT_PWMS_CHANNEL(node_id), \ - .flags = DT_PWMS_FLAGS(node_id), \ - .period_ns = (NSEC_PER_SEC/DT_PROP(node_id, pwm_frequency)), \ - .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ +#define FAN_CONTROL_INST(node_id) \ + [node_id] = { \ + .pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ + .channel = DT_PWMS_CHANNEL(node_id), \ + .flags = DT_PWMS_FLAGS(node_id), \ + .period_ns = (NSEC_PER_SEC / DT_PROP(node_id, pwm_frequency)), \ + .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ }, DT_INST_FOREACH_CHILD(0, FAN_CONFIGS) -const struct fan_t fans[FAN_CH_COUNT] = { - DT_INST_FOREACH_CHILD(0, FAN_INST) -}; +const struct fan_t fans[FAN_CH_COUNT] = { DT_INST_FOREACH_CHILD(0, FAN_INST) }; /* Rpm deviation (Unit:percent) */ #ifndef RPM_DEVIATION @@ -130,8 +128,8 @@ static void fan_pwm_update(int ch) } if (data->pwm_enabled) { - pulse_ns = DIV_ROUND_NEAREST( - cfg->period_ns * data->pwm_percent, 100); + pulse_ns = DIV_ROUND_NEAREST(cfg->period_ns * data->pwm_percent, + 100); } else { pulse_ns = 0; } @@ -320,8 +318,8 @@ void fan_tick_func(void) fan_tick_func_duty(ch); break; default: - LOG_ERR("Invalid fan %d mode: %d", - ch, fan_data[ch].current_fan_mode); + LOG_ERR("Invalid fan %d mode: %d", ch, + fan_data[ch].current_fan_mode); } } } -- cgit v1.2.1 From 26bf84f75c1413ca7198099522e694259ef1b4fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:35 -0600 Subject: chip/stm32/usart_rx_interrupt-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibec02e99a0b8b5fb749b54e486487258769d82f3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729419 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_interrupt-stm32f0.c | 50 ++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/usart_rx_interrupt-stm32f0.c diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c deleted file mode 120000 index a756455f9b..0000000000 --- a/chip/stm32/usart_rx_interrupt-stm32f0.c +++ /dev/null @@ -1 +0,0 @@ -usart_rx_interrupt.c \ No newline at end of file diff --git a/chip/stm32/usart_rx_interrupt-stm32f0.c b/chip/stm32/usart_rx_interrupt-stm32f0.c new file mode 100644 index 0000000000..4d5060a26e --- /dev/null +++ b/chip/stm32/usart_rx_interrupt-stm32f0.c @@ -0,0 +1,49 @@ +/* Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Interrupt based USART RX driver for STM32F0 and STM32F3 */ + +#include "usart.h" + +#include "atomic.h" +#include "common.h" +#include "queue.h" +#include "registers.h" + +static void usart_rx_init(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + + STM32_USART_CR1(base) |= STM32_USART_CR1_RXNEIE; + STM32_USART_CR1(base) |= STM32_USART_CR1_RE; + STM32_USART_CR3(base) |= STM32_USART_CR3_OVRDIS; +} + +static void usart_rx_interrupt_handler(struct usart_config const *config) +{ + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); + + if (status & STM32_USART_SR_RXNE) { + uint8_t byte = STM32_USART_RDR(base); + + if (!queue_add_unit(config->producer.queue, &byte)) + atomic_add((atomic_t *)&(config->state->rx_dropped), 1); + } +} + +struct usart_rx const usart_rx_interrupt = { + .producer_ops = { + /* + * Nothing to do here, we either had enough space in the queue + * when a character came in or we dropped it already. + */ + .read = NULL, + }, + + .init = usart_rx_init, + .interrupt = usart_rx_interrupt_handler, + .info = NULL, +}; -- cgit v1.2.1 From c9e044d78b9684ad281be0f2de98b99942990147 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:23 -0600 Subject: core/nds32/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2ca7ce26eb0e1022726105aff0d66da7a4b75e0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729859 Reviewed-by: Jeremy Bettis --- core/nds32/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/nds32/atomic.h b/core/nds32/atomic.h index 592834faae..4d640a1cdb 100644 --- a/core/nds32/atomic.h +++ b/core/nds32/atomic.h @@ -85,4 +85,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return ret; } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 4fcae145da6e6c53f60c1a0e105bcb0125d8f578 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:16 -0600 Subject: zephyr/test/ap_power/src/events.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2e5528dc1a1603871ad8fecf82144659ba31b32 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730923 Reviewed-by: Jeremy Bettis --- zephyr/test/ap_power/src/events.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/zephyr/test/ap_power/src/events.c b/zephyr/test/ap_power/src/events.c index 426f879177..b464ce4fb2 100644 --- a/zephyr/test/ap_power/src/events.c +++ b/zephyr/test/ap_power/src/events.c @@ -68,7 +68,7 @@ ZTEST(events, test_registration) ap_power_ev_remove_callback(&cb.cb); ap_power_ev_send_callbacks(AP_POWER_RESET); zassert_equal(1, cb.count, "Callback called"); - cb.count = 0; /* Reset to make it clear */ + cb.count = 0; /* Reset to make it clear */ cb.event = 0; /* Add it twice */ ap_power_ev_add_callback(&cb.cb); @@ -177,9 +177,9 @@ ZTEST(events, test_hooks) zassert_equal(0, count_hook_shutdown, "shutdown hook called"); zassert_equal(1, count_hook_startup, "startup hook not called"); zassert_equal(0, count_hook_shutdown, - "reset event, shutdown hook called"); + "reset event, shutdown hook called"); zassert_equal(1, count_hook_startup, - "reset event, startup hook called"); + "reset event, startup hook called"); ap_power_ev_send_callbacks(AP_POWER_SHUTDOWN); zassert_equal(1, count_hook_shutdown, "shutdown hook not called"); zassert_equal(1, count_hook_startup, "startup hook called"); @@ -188,5 +188,4 @@ ZTEST(events, test_hooks) /** * @brief Test Suite: Verifies AP power notification functionality. */ -ZTEST_SUITE(events, ap_power_predicate_post_main, - NULL, NULL, NULL, NULL); +ZTEST_SUITE(events, ap_power_predicate_post_main, NULL, NULL, NULL, NULL); -- cgit v1.2.1 From 7f43631c38a7024f8b51df0519e43ca4ea74cc8f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:20 -0600 Subject: board/beadrix/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6dd04fd50bf6535f2058f79a3eb1b9dd4a956b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728029 Reviewed-by: Jeremy Bettis --- board/beadrix/led.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/board/beadrix/led.c b/board/beadrix/led.c index ab011d49d4..8b81f6fea8 100644 --- a/board/beadrix/led.c +++ b/board/beadrix/led.c @@ -19,27 +19,25 @@ #include "util.h" #define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define BAT_LED_ON 0 -#define BAT_LED_OFF 1 +#define BAT_LED_ON 0 +#define BAT_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { LED_OFF = 0, LED_RED, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_LED_R_ODL, - (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_LED_B_ODL, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From 16313ab6c4d6158650a9243784495060b61f6ee6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:18 -0600 Subject: zephyr/shim/src/led_driver/led.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie005916fb68efea716ab9c35636f9b61c3184ba9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727424 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/led_driver/led.h | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/zephyr/shim/src/led_driver/led.h b/zephyr/shim/src/led_driver/led.h index 8c4e7654d5..ddde50a347 100644 --- a/zephyr/shim/src/led_driver/led.h +++ b/zephyr/shim/src/led_driver/led.h @@ -11,34 +11,32 @@ #include #define COMPAT_GPIO_LED cros_ec_gpio_led_pins -#define COMPAT_PWM_LED cros_ec_pwm_led_pins +#define COMPAT_PWM_LED cros_ec_pwm_led_pins -#define PINS_NODE(id) DT_CAT(PIN_NODE_, id) -#define PINS_ARRAY(id) DT_CAT(PINS_ARRAY_, id) +#define PINS_NODE(id) DT_CAT(PIN_NODE_, id) +#define PINS_ARRAY(id) DT_CAT(PINS_ARRAY_, id) /* * Return string-token if the property exists, otherwise return 0 */ -#define GET_PROP(id, prop) \ - COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \ - (DT_STRING_UPPER_TOKEN(id, prop)), \ - (0)) +#define GET_PROP(id, prop) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \ + (DT_STRING_UPPER_TOKEN(id, prop)), (0)) /* * Return string-token if the property exists, otherwise return -1 */ -#define GET_PROP_NVE(id, prop) \ - COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \ - (DT_STRING_UPPER_TOKEN(id, prop)), \ - (-1)) +#define GET_PROP_NVE(id, prop) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, prop), \ + (DT_STRING_UPPER_TOKEN(id, prop)), (-1)) -#define LED_ENUM(id, enum_name) DT_STRING_TOKEN(id, enum_name) -#define LED_ENUM_WITH_COMMA(id, enum_name) \ - COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \ - (LED_ENUM(id, enum_name),), ()) +#define LED_ENUM(id, enum_name) DT_STRING_TOKEN(id, enum_name) +#define LED_ENUM_WITH_COMMA(id, enum_name) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, enum_name), \ + (LED_ENUM(id, enum_name), ), ()) #define GPIO_LED_PINS_NODE DT_PATH(gpio_led_pins) -#define PWM_LED_PINS_NODE DT_PATH(pwm_led_pins) +#define PWM_LED_PINS_NODE DT_PATH(pwm_led_pins) enum led_color { LED_OFF, @@ -48,7 +46,7 @@ enum led_color { LED_YELLOW, LED_WHITE, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; /* -- cgit v1.2.1 From 145e19e34732556103477514cc17b5fef1771543 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:49 -0600 Subject: common/test_util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0c31ca36f935c97081287c75168406162b19baa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729753 Reviewed-by: Jeremy Bettis --- common/test_util.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/common/test_util.c b/common/test_util.c index 37cc42000c..f7be95f767 100644 --- a/common/test_util.c +++ b/common/test_util.c @@ -29,16 +29,24 @@ struct test_util_tag { int __test_error_count; /* Weak reference function as an entry point for unit test */ -test_mockable void run_test(int argc, char **argv) { } +test_mockable void run_test(int argc, char **argv) +{ +} /* Default mock test init */ -test_mockable void test_init(void) { } +test_mockable void test_init(void) +{ +} /* Default mock before test */ -test_mockable void before_test(void) { } +test_mockable void before_test(void) +{ +} /* Default mock after test */ -test_mockable void after_test(void) { } +test_mockable void after_test(void) +{ +} #ifdef TEST_COVERAGE extern void __gcov_flush(void); @@ -167,7 +175,7 @@ int test_send_host_command(int command, int version, const void *params, return host_command_process(&args); } -#endif /* TASK_HAS_HOSTCMD */ +#endif /* TASK_HAS_HOSTCMD */ /* Linear congruential pseudo random number generator */ uint32_t prng(uint32_t seed) @@ -188,8 +196,7 @@ static void restore_state(void) tag = (const struct test_util_tag *)system_get_jump_tag( TEST_UTIL_SYSJUMP_TAG, &version, &size); - if (tag && version == TEST_UTIL_SYSJUMP_VERSION && - size == sizeof(*tag)) + if (tag && version == TEST_UTIL_SYSJUMP_VERSION && size == sizeof(*tag)) __test_error_count = tag->error_count; else __test_error_count = 0; @@ -210,8 +217,7 @@ static int command_run_test(int argc, char **argv) run_test(argc, argv); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(runtest, command_run_test, - NULL, NULL); +DECLARE_CONSOLE_COMMAND(runtest, command_run_test, NULL, NULL); #ifndef CONFIG_ZEPHYR void z_ztest_run_test_suite(const char *name, struct unit_test *suite) -- cgit v1.2.1 From 9478d8da03d4baa497046205e6067bd49f82313c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:01 -0600 Subject: driver/tcpm/nct38xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I90bf1cfdc9f2b737edae32bda4aa01b694dd73a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730096 Reviewed-by: Jeremy Bettis --- driver/tcpm/nct38xx.c | 126 ++++++++++++++++++++++---------------------------- 1 file changed, 56 insertions(+), 70 deletions(-) diff --git a/driver/tcpm/nct38xx.c b/driver/tcpm/nct38xx.c index 8b6690524c..16e0866ca6 100644 --- a/driver/tcpm/nct38xx.c +++ b/driver/tcpm/nct38xx.c @@ -30,8 +30,8 @@ #error "Please upgrade your board configuration" #endif -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static enum nct38xx_boot_type boot_type[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -74,9 +74,10 @@ static int nct38xx_init(int port) * accessory and change this bit (see b/186799392). */ if ((boot_type[port] == NCT38XX_BOOT_DEAD_BATTERY) && - (reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON)) + (reg & TCPC_REG_POWER_STATUS_DEBUG_ACC_CON)) CPRINTS("C%d: Booted in dead battery mode, not changing debug" - " control", port); + " control", + port); else if (tcpc_config[port].flags & TCPC_FLAGS_NO_DEBUG_ACC_CONTROL) CPRINTS("C%d: NO_DEBUG_ACC_CONTROL", port); else @@ -90,8 +91,7 @@ static int nct38xx_init(int port) * [2] - SNKEN : VBUS sink enable output enable * [0] - SRCEN : VBUS source voltage enable output enable */ - reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN | - NCT38XX_REG_CTRL_OUT_EN_SNKEN | + reg = NCT38XX_REG_CTRL_OUT_EN_SRCEN | NCT38XX_REG_CTRL_OUT_EN_SNKEN | NCT38XX_REG_CTRL_OUT_EN_CONNDIREN; rv = tcpc_write(port, NCT38XX_REG_CTRL_OUT_EN, reg); @@ -99,16 +99,13 @@ static int nct38xx_init(int port) return rv; /* Disable OVP */ - rv = tcpc_update8(port, - TCPC_REG_FAULT_CTRL, - TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, - MASK_SET); + rv = tcpc_update8(port, TCPC_REG_FAULT_CTRL, + TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, MASK_SET); if (rv) return rv; /* Enable VBus monitor and Disable FRS */ - rv = tcpc_update8(port, - TCPC_REG_POWER_CTRL, + rv = tcpc_update8(port, TCPC_REG_POWER_CTRL, (TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS | TCPC_REG_POWER_CTRL_FRS_ENABLE), MASK_CLR); @@ -159,10 +156,7 @@ static int nct38xx_init(int port) reg |= TCPC_REG_ALERT_VENDOR_DEF; } - rv = tcpc_update16(port, - TCPC_REG_ALERT_MASK, - reg, - MASK_SET); + rv = tcpc_update16(port, TCPC_REG_ALERT_MASK, reg, MASK_SET); if (rv) return rv; @@ -172,10 +166,7 @@ static int nct38xx_init(int port) NCT38XX_REG_VBC_FAULT_CTL_VC_SCP_EN | NCT38XX_REG_VBC_FAULT_CTL_FAULT_VC_OFF; - rv = tcpc_update8(port, - NCT38XX_REG_VBC_FAULT_CTL, - reg, - MASK_SET); + rv = tcpc_update8(port, NCT38XX_REG_VBC_FAULT_CTL, reg, MASK_SET); return rv; } @@ -218,13 +209,11 @@ static int nct38xx_tcpm_set_cc(int port, int pull) */ int rv; enum mask_update_action action = - pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ? - MASK_CLR : MASK_SET; + pull == TYPEC_CC_OPEN && tcpm_get_snk_ctrl(port) ? MASK_CLR : + MASK_SET; - rv = tcpc_update8(port, - NCT38XX_REG_CTRL_OUT_EN, - NCT38XX_REG_CTRL_OUT_EN_SNKEN, - action); + rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN, + NCT38XX_REG_CTRL_OUT_EN_SNKEN, action); if (rv) return rv; @@ -240,10 +229,8 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable) * USB_Cx_TCPC_VBSNK_EN_L will be driven high. */ if (!enable) { - rv = tcpc_update8(port, - NCT38XX_REG_CTRL_OUT_EN, - NCT38XX_REG_CTRL_OUT_EN_SNKEN, - MASK_SET); + rv = tcpc_update8(port, NCT38XX_REG_CTRL_OUT_EN, + NCT38XX_REG_CTRL_OUT_EN_SNKEN, MASK_SET); if (rv) return rv; } @@ -253,9 +240,9 @@ static int nct38xx_tcpm_set_snk_ctrl(int port, int enable) static inline int tcpc_read_alert_no_lpm_exit(int port, int *val) { - return tcpc_addr_read16_no_lpm_exit(port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_ALERT, val); + return tcpc_addr_read16_no_lpm_exit( + port, tcpc_config[port].i2c_info.addr_flags, TCPC_REG_ALERT, + val); } /* Map Type-C port to IOEX port */ @@ -326,10 +313,10 @@ static int nct3807_handle_fault(int port, int fault) /* We don't use TCPC OVP, so just disable it */ if (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE) { /* Disable OVP */ - rv = tcpc_update8(port, - TCPC_REG_FAULT_CTRL, - TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, - MASK_SET); + rv = tcpc_update8( + port, TCPC_REG_FAULT_CTRL, + TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS, + MASK_SET); if (rv) return rv; } @@ -354,57 +341,56 @@ __maybe_unused static int nct38xx_set_frs_enable(int port, int enable) * 2. Enable the FRS interrupt (already done in TCPCI alert init) * 3. Set POWER_CONTORL.FastRoleSwapEnable to 1 */ - RETURN_ERROR(tcpc_write16(port, - TCPC_REG_VBUS_SINK_DISCONNECT_THRESH, - enable ? 0x0000 : - TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT)); + RETURN_ERROR(tcpc_write16( + port, TCPC_REG_VBUS_SINK_DISCONNECT_THRESH, + enable ? 0x0000 : + TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT)); - return tcpc_update8(port, - TCPC_REG_POWER_CTRL, + return tcpc_update8(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_FRS_ENABLE, enable ? MASK_SET : MASK_CLR); } const struct tcpm_drv nct38xx_tcpm_drv = { - .init = &nct38xx_tcpm_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &nct38xx_tcpm_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &nct38xx_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &nct38xx_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &nct38xx_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &nct38xx_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif .tcpc_enable_auto_discharge_disconnect = - &tcpci_tcpc_enable_auto_discharge_disconnect, - .debug_accessory = &tcpci_tcpc_debug_accessory, + &tcpci_tcpc_enable_auto_discharge_disconnect, + .debug_accessory = &tcpci_tcpc_debug_accessory, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, - .set_snk_ctrl = &nct38xx_tcpm_set_snk_ctrl, - .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, - .get_chip_info = &tcpci_get_chip_info, + .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, + .set_snk_ctrl = &nct38xx_tcpm_set_snk_ctrl, + .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &tcpci_get_chip_info, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &tcpci_enter_low_power_mode, + .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_USB_PD_FRS - .set_frs_enable = &nct38xx_set_frs_enable, + .set_frs_enable = &nct38xx_set_frs_enable, #endif - .handle_fault = &nct3807_handle_fault, + .handle_fault = &nct3807_handle_fault, }; -- cgit v1.2.1 From ac118ca7dcebf38aedac47fcf96c82de0067978a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:11 -0600 Subject: board/nami/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61fb49e917f2fa9627a349f13a3b79db9827d735 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728716 Reviewed-by: Jeremy Bettis --- board/nami/battery.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/board/nami/battery.c b/board/nami/battery.c index 149272c8c1..f9ad0e8841 100644 --- a/board/nami/battery.c +++ b/board/nami/battery.c @@ -16,8 +16,8 @@ #include "hooks.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Default, Nami, Vayne */ static const struct battery_info info_0 = { @@ -243,8 +243,9 @@ static int battery_init(void) if (batt_status & STATUS_INITIALIZED) return 1; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } enum battery_disconnect_grace_period { @@ -278,13 +279,13 @@ static int battery_check_disconnect_ti_bq40z50(void) uint8_t data[6]; /* Check if battery charging + discharging is disabled. */ - rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return BATTERY_DISCONNECT_ERROR; - if ((data[3] & (BATTERY_DISCHARGING_DISABLED | - BATTERY_CHARGING_DISABLED)) == + if ((data[3] & + (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) == (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) { if (oem != PROJECT_SONA) return BATTERY_DISCONNECTED; @@ -298,10 +299,10 @@ static int battery_check_disconnect_ti_bq40z50(void) * stop charging and avoid damaging the battery. */ if (disconnect_grace_period == - BATTERY_DISCONNECT_GRACE_PERIOD_OVER) + BATTERY_DISCONNECT_GRACE_PERIOD_OVER) return BATTERY_DISCONNECTED; if (disconnect_grace_period == - BATTERY_DISCONNECT_GRACE_PERIOD_OFF) + BATTERY_DISCONNECT_GRACE_PERIOD_OFF) hook_call_deferred(&battery_disconnect_timer_data, 5 * SECOND); ccprintf("Battery disconnect grace period\n"); -- cgit v1.2.1 From 817412c000f987ad77ce0fe22418893e9785b835 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:01 -0600 Subject: board/helios/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib6fb1d287673adbce3915cdaebc8fb6ba725f766 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728301 Reviewed-by: Jeremy Bettis --- board/helios/board.h | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/board/helios/board.h b/board/helios/board.h index 174c5157b6..f5c31bc3ab 100644 --- a/board/helios/board.h +++ b/board/helios/board.h @@ -56,7 +56,7 @@ * Helios' battery takes several seconds to come back out of its disconnect * state (~4.2 seconds on the unit I have, so give it a little more for margin). */ -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 6 /* BC 1.2 */ @@ -85,16 +85,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -102,10 +102,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC3 */ - ADC_TEMP_SENSOR_4, /* ADC2 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC3 */ + ADC_TEMP_SENSOR_4, /* ADC2 */ ADC_CH_COUNT }; @@ -117,11 +117,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From 6edf9ab0c271ef86d133b460593b2e6ef8ff3da8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:16 -0600 Subject: board/felwinter/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46f88f3799c2844759fa98d049e349d2ff087012 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728358 Reviewed-by: Jeremy Bettis --- board/felwinter/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/felwinter/keyboard.c b/board/felwinter/keyboard.c index a8cbf72238..e854eb4d3e 100644 --- a/board/felwinter/keyboard.c +++ b/board/felwinter/keyboard.c @@ -41,8 +41,8 @@ static const struct ec_response_keybd_config felwinter_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &felwinter_kb; } -- cgit v1.2.1 From 3ca5468a96377218bf726f35231ebd735f9e950b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:09 -0600 Subject: zephyr/shim/include/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibcf7f7f1cebb24e03ae0454180e9a644b73e80a8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730581 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/board.h b/zephyr/shim/include/board.h index 1c8da8b209..c1a391b56a 100644 --- a/zephyr/shim/include/board.h +++ b/zephyr/shim/include/board.h @@ -37,4 +37,4 @@ #include "charger_enum.h" #endif -#endif /* __BOARD_H */ +#endif /* __BOARD_H */ -- cgit v1.2.1 From bf0fe706efcda52023cfa8a43316f9cdae9fc98a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:04 -0600 Subject: chip/npcx/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2c400b8f53ddfd2546d2251dbf6bc1e77e42a3fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729442 Reviewed-by: Jeremy Bettis --- chip/npcx/system.c | 200 ++++++++++++++++++++++++++--------------------------- 1 file changed, 98 insertions(+), 102 deletions(-) diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 4a2450ee5f..d85dc3cdde 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -27,27 +27,27 @@ /* Delay after writing TTC for value to latch */ #define MTC_TTC_LOAD_DELAY_US 250 -#define MTC_ALARM_MASK (BIT(25) - 1) -#define MTC_WUI_GROUP MIWU_GROUP_4 -#define MTC_WUI_MASK MASK_PIN7 +#define MTC_ALARM_MASK (BIT(25) - 1) +#define MTC_WUI_GROUP MIWU_GROUP_4 +#define MTC_WUI_MASK MASK_PIN7 /* ROM address of chip revision */ #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 -#define CHIP_REV_ADDR 0x0000FFFC -#define CHIP_REV_STR_SIZE 12 +#define CHIP_REV_ADDR 0x0000FFFC +#define CHIP_REV_STR_SIZE 12 #define PWDWN_8_RESERVED_SET_MASK 0x30 #else -#define CHIP_REV_ADDR 0x00007FFC -#define CHIP_REV_STR_SIZE 6 +#define CHIP_REV_ADDR 0x00007FFC +#define CHIP_REV_STR_SIZE 6 #endif /* Legacy SuperI/O Configuration D register offset */ -#define SIOCFD_REG_OFFSET 0x2D +#define SIOCFD_REG_OFFSET 0x2D /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #if defined(NPCX_LCT_SUPPORT) /* A flag for waking up from hibernate mode by RTC overflow event */ @@ -91,8 +91,7 @@ void system_watchdog_reset(void) /* Return true if index is stored as a single byte in bbram */ static int bbram_is_byte_access(enum bbram_data_index index) { - return index == BBRM_DATA_INDEX_PD0 || - index == BBRM_DATA_INDEX_PD1 || + return index == BBRM_DATA_INDEX_PD0 || index == BBRM_DATA_INDEX_PD1 || index == BBRM_DATA_INDEX_PD2 || index == BBRM_DATA_INDEX_PANIC_FLAGS; } @@ -106,7 +105,7 @@ void system_check_bbram_on_reset(void) * dropped, print a warning message. */ if (IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_SCRATCH) || - IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) + IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS)) CPRINTF("VBAT drop!\n"); /* @@ -177,7 +176,7 @@ static int bbram_data_write(enum bbram_data_index index, uint32_t value) /* Write BBRAM */ NPCX_BBRAM(index) = value & 0xFF; if (bytes == 4) { - NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF; + NPCX_BBRAM(index + 1) = (value >> 8) & 0xFF; NPCX_BBRAM(index + 2) = (value >> 16) & 0xFF; NPCX_BBRAM(index + 3) = (value >> 24) & 0xFF; } @@ -260,14 +259,14 @@ void system_set_rtc(uint32_t seconds) * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of * software panic. */ -#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) -#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) -#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) -#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) -#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) -#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) +#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) +#define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) +#define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) +#define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) +#define BKUP_LREG3 (BBRM_DATA_INDEX_PANIC_BKUP + 16) +#define BKUP_LREG4 (BBRM_DATA_INDEX_PANIC_BKUP + 20) -#define BKUP_PANIC_DATA_VALID BIT(0) +#define BKUP_PANIC_DATA_VALID BIT(0) void chip_panic_data_backup(void) { @@ -336,10 +335,10 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags) #ifdef NPCX_LCT_SUPPORT if (npcx_lct_is_event_set()) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; /* Is RTC overflow event? */ if (bbram_data_read(BBRM_DATA_INDEX_LCT_TIME) == - NPCX_LCT_MAX) { + NPCX_LCT_MAX) { /* * Mark it as RTC overflow event and handle it * in hook init function later for logging info. @@ -350,22 +349,21 @@ static void chip_set_hib_flag(uint32_t *flags, uint32_t hib_wake_flags) return; } #endif - *flags |= EC_RESET_FLAG_WAKE_PIN | - EC_RESET_FLAG_HIBERNATE; + *flags |= EC_RESET_FLAG_WAKE_PIN | EC_RESET_FLAG_HIBERNATE; } else { /* Hibernate via non-PSL */ #ifdef NPCX_LCT_SUPPORT if (hib_wake_flags & HIBERNATE_WAKE_LCT) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; return; } #endif if (hib_wake_flags & HIBERNATE_WAKE_PIN) { *flags |= EC_RESET_FLAG_WAKE_PIN | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; } else if (hib_wake_flags & HIBERNATE_WAKE_MTC) { *flags |= EC_RESET_FLAG_RTC_ALARM | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_HIBERNATE; } } } @@ -420,9 +418,9 @@ static void check_reset_cause(void) * clear the flag so later code will * not wait for the second reset. */ - flags = - (flags & ~EC_RESET_FLAG_INITIAL_PWR) - | EC_RESET_FLAG_POWER_ON; + flags = (flags & + ~EC_RESET_FLAG_INITIAL_PWR) | + EC_RESET_FLAG_POWER_ON; else /* * No previous power-on flag, @@ -452,8 +450,8 @@ static void check_reset_cause(void) * No second reset after power-on, so * set the flags according to the restart reason. */ - flags |= reset ? EC_RESET_FLAG_RESET_PIN - : EC_RESET_FLAG_POWER_ON; + flags |= reset ? EC_RESET_FLAG_RESET_PIN : + EC_RESET_FLAG_POWER_ON; #endif } chip_save_reset_flags(chip_flags); @@ -480,7 +478,7 @@ static void check_reset_cause(void) * cause is panic reason or not. */ if (!(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) + EC_RESET_FLAG_HIBERNATE))) flags |= EC_RESET_FLAG_WATCHDOG; /* Clear watchdog reset status initially*/ @@ -499,10 +497,10 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void) int table, i; /* Disable all MIWU inputs before entering hibernate */ - for (table = MIWU_TABLE_0 ; table < MIWU_TABLE_2 ; table++) { - for (i = 0 ; i < 8 ; i++) { + for (table = MIWU_TABLE_0; table < MIWU_TABLE_2; table++) { + for (i = 0; i < 8; i++) { /* Disable all wake-ups */ - NPCX_WKEN(table, i) = 0x00; + NPCX_WKEN(table, i) = 0x00; /* Clear all pending bits of wake-ups */ NPCX_WKPCL(table, i) = 0xFF; /* @@ -515,7 +513,7 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void) #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 /* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */ - NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; + NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF; NPCX_WKINEN(MIWU_TABLE_2, MIWU_GROUP_6) = 0x00; #endif @@ -553,9 +551,9 @@ static void system_set_lct_alarm(uint32_t seconds, uint32_t microseconds) npcx_lct_config(seconds, 0, 1); task_disable_irq(NPCX_IRQ_LCT_WKINTF_2); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; task_enable_irq(NPCX_IRQ_LCT_WKINTF_2); #endif npcx_lct_enable(1); @@ -628,10 +626,10 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) board_hibernate_late(); /* Clear all pending IRQ otherwise wfi will have no affect */ - for (i = NPCX_IRQ_0 ; i < NPCX_IRQ_COUNT ; i++) + for (i = NPCX_IRQ_0; i < NPCX_IRQ_COUNT; i++) task_clear_pending_irq(i); - /* Set the timer interrupt for wake up. */ + /* Set the timer interrupt for wake up. */ #ifdef NPCX_LCT_SUPPORT if (seconds || microseconds) { system_set_lct_alarm(seconds, microseconds); @@ -726,9 +724,9 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds) task_enable_irq(NPCX_IRQ_MTC); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_0, MTC_WUI_GROUP) |= MTC_WUI_MASK; } void system_reset_rtc_alarm(void) @@ -835,7 +833,7 @@ void chip_pre_init(void) } #else if (GET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD) == - NPCX_JEN_CTL1_JEN_EN_ENA) { + NPCX_JEN_CTL1_JEN_EN_ENA) { SET_FIELD(NPCX_JEN_CTL1, NPCX_JEN_CTL1_JEN_EN_FIELD, NPCX_JEN_CTL1_JEN_EN_DIS); system_disable_host_sel_jtag(); @@ -871,20 +869,20 @@ void system_pre_init(void) pwdwn6 = 0x70 | #if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7 - /* - * Don't set PD of ITIM6 for NPCX9 and later chips because - * they use it as the system timer. - */ - BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | + /* + * Don't set PD of ITIM6 for NPCX9 and later chips because + * they use it as the system timer. + */ + BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | #endif - BIT(NPCX_PWDWN_CTL6_ITIM4_PD); + BIT(NPCX_PWDWN_CTL6_ITIM4_PD); #if !defined(CONFIG_HOST_INTERFACE_ESPI) pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; #endif NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6; #if defined(CHIP_FAMILY_NPCX7) -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) /* Power down UART2, SMB5-7, ITIM64, and WoV */ @@ -949,34 +947,34 @@ void system_pre_init(void) * hibernation. */ SET_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL); + NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL); /* Disable VCC_RST Pull-Up */ SET_BIT(NPCX_DEVALT(ALT_GROUP_G), - NPCX_DEVALTG_VCC1_RST_PUD); + NPCX_DEVALTG_VCC1_RST_PUD); /* * Lock this bit itself and VCC1_RST_PSL in the * PSL_MCTL1 register to read-only. */ SET_BIT(NPCX_GLUE_PSL_MCTL2, - NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK); + NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK); } /* Don't set PSL_OUT to open-drain if it is the level mode */ ASSERT((opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) || - !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)); + !(opt_flag & NPCX_PSL_CFG_PSL_OUT_OD)); if (opt_flag & NPCX_PSL_CFG_PSL_OUT_OD) SET_BIT(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_OD_EN); else CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_OD_EN); + NPCX_GLUE_PSL_MCTL1_OD_EN); if (opt_flag & NPCX_PSL_CFG_PSL_OUT_PULSE) SET_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_PLS_EN); + NPCX_GLUE_PSL_MCTL1_PLS_EN); else CLEAR_BIT(NPCX_GLUE_PSL_MCTL1, - NPCX_GLUE_PSL_MCTL1_PLS_EN); + NPCX_GLUE_PSL_MCTL1_PLS_EN); } #endif } @@ -1027,7 +1025,7 @@ const char *system_get_chip_vendor(void) case 0x20: return "Nuvoton"; default: - *p = system_to_hex(fam_id >> 4); + *p = system_to_hex(fam_id >> 4); *(p + 1) = system_to_hex(fam_id); *(p + 2) = '\0'; return str; @@ -1070,7 +1068,7 @@ const char *system_get_chip_name(void) return "NPCX993F"; #endif default: - *p = system_to_hex(chip_id >> 4); + *p = system_to_hex(chip_id >> 4); *(p + 1) = system_to_hex(chip_id); *(p + 2) = '\0'; return str; @@ -1106,7 +1104,7 @@ const char *system_get_chip_revision(void) break; case 0x07: if (chip_id == NPCX796F_A_B_CHIP_ID || - chip_id == NPCX797W_B_CHIP_ID) + chip_id == NPCX797W_B_CHIP_ID) *p++ = 'B'; else *p++ = 'C'; @@ -1188,7 +1186,7 @@ static void system_init_check_rtc_wakeup_event(void) * also supported, determine whether ec is woken up by RTC with overflow * event (16 weeks). If so, let it go to hibernate mode immediately. */ - if (is_rtc_overflow_event){ + if (is_rtc_overflow_event) { CPRINTS("Hibernate due to RTC overflow event"); system_hibernate(0, 0); } @@ -1224,9 +1222,8 @@ static int command_system_rtc(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, - "[set ]", - "Get/set real-time clock"); +DECLARE_CONSOLE_COMMAND(rtc, command_system_rtc, "[set ]", + "Get/set real-time clock"); #ifdef CONFIG_CMD_RTC_ALARM /** @@ -1244,13 +1241,11 @@ static int command_rtc_alarm_test(int argc, char **argv) s = strtoi(argv[1], &e, 10); if (*e) return EC_ERROR_PARAM1; - } if (argc > 2) { us = strtoi(argv[2], &e, 10); if (*e) return EC_ERROR_PARAM2; - } system_set_rtc_alarm(s, us); @@ -1258,8 +1253,7 @@ static int command_rtc_alarm_test(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(rtc_alarm, command_rtc_alarm_test, - "[seconds [microseconds]]", - "Test alarm"); + "[seconds [microseconds]]", "Test alarm"); #endif /* CONFIG_CMD_RTC_ALARM */ #endif /* CONFIG_CMD_RTC */ @@ -1276,9 +1270,8 @@ static enum ec_status system_rtc_get_value(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, - system_rtc_get_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_VALUE, system_rtc_get_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) { @@ -1287,9 +1280,8 @@ static enum ec_status system_rtc_set_value(struct host_cmd_handler_args *args) system_set_rtc(p->time); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, - system_rtc_set_value, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_VALUE, system_rtc_set_value, + EC_VER_MASK(0)); static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) { @@ -1298,9 +1290,8 @@ static enum ec_status system_rtc_set_alarm(struct host_cmd_handler_args *args) system_set_rtc_alarm(p->time, 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, - system_rtc_set_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_SET_ALARM, system_rtc_set_alarm, + EC_VER_MASK(0)); static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) { @@ -1311,9 +1302,8 @@ static enum ec_status system_rtc_get_alarm(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, - system_rtc_get_alarm, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RTC_GET_ALARM, system_rtc_get_alarm, + EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_RTC */ #ifdef CONFIG_EXTERNAL_STORAGE @@ -1330,28 +1320,28 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; + CONFIG_RW_B_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #endif case EC_IMAGE_RO: default: /* Jump to RO by default */ - flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF; + flash_offset = + CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF; flash_used = CONFIG_RO_SIZE; break; } /* Make sure the reset vector is inside the destination image */ - addr_entry = *(uintptr_t *)(flash_offset + - CONFIG_MAPPED_STORAGE_BASE + 4); + addr_entry = + *(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4); /* * Speed up FW download time by increasing clock freq of EC. It will @@ -1361,20 +1351,25 @@ void system_jump_to_booter(void) /* Bypass for GMDA issue of ROM api utilities */ #if defined(CHIP_FAMILY_NPCX5) - system_download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - addr_entry /* jump to this address after download */ + system_download_from_flash(flash_offset, /* The offset of the data in + spi flash */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded + data */ + flash_used, /* Number of bytes to download */ + addr_entry /* jump to this address after + download */ ); #else - download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - SIGN_NO_CHECK, /* Need CRC check or not */ - addr_entry, /* jump to this address after download */ - &status /* Status fo download */ + download_from_flash(flash_offset, /* The offset of the data in spi flash + */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded data */ + flash_used, /* Number of bytes to download */ + SIGN_NO_CHECK, /* Need CRC check or not */ + addr_entry, /* jump to this address after download + */ + &status /* Status fo download */ ); #endif } @@ -1410,7 +1405,8 @@ void system_set_image_copy(enum ec_image copy) #endif default: CPRINTS("Invalid copy (%d) is requested as a jump destination. " - "Change it to %d.", copy, EC_IMAGE_RO); + "Change it to %d.", + copy, EC_IMAGE_RO); /* Fall through to EC_IMAGE_RO */ case EC_IMAGE_RO: SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION); -- cgit v1.2.1 From a9602b19c5bbc9673a7240b50081122b71656029 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:52 -0600 Subject: board/nucleo-f072rb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f9b177e179e18f8701fe4d8e69ccb917358775f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728776 Reviewed-by: Jeremy Bettis --- board/nucleo-f072rb/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/nucleo-f072rb/board.h b/board/nucleo-f072rb/board.h index 0ec675ab61..8bc3d3a342 100644 --- a/board/nucleo-f072rb/board.h +++ b/board/nucleo-f072rb/board.h @@ -20,7 +20,7 @@ #ifdef CTS_MODULE #undef STM32_IRQ_EXT2_3_PRIORITY -#define STM32_IRQ_EXT2_3_PRIORITY 2 +#define STM32_IRQ_EXT2_3_PRIORITY 2 #ifdef CTS_MODULE_I2C #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -- cgit v1.2.1 From 5b7df6dcbd94ad36e9517a330d6e2d3a5ac2913b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:09 -0600 Subject: include/motion_orientation.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91a1cc6b067632ce817ea1659bbb999a4e626657 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730368 Reviewed-by: Jeremy Bettis --- include/motion_orientation.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/motion_orientation.h b/include/motion_orientation.h index 641f97a799..7e78337573 100644 --- a/include/motion_orientation.h +++ b/include/motion_orientation.h @@ -12,13 +12,13 @@ #include "ec_commands.h" #include "motion_sense.h" -enum motionsensor_orientation motion_orientation_remap( - const struct motion_sensor_t *s, - enum motionsensor_orientation orientation); +enum motionsensor_orientation +motion_orientation_remap(const struct motion_sensor_t *s, + enum motionsensor_orientation orientation); bool motion_orientation_changed(const struct motion_sensor_t *s); -enum motionsensor_orientation *motion_orientation_ptr( - const struct motion_sensor_t *s); +enum motionsensor_orientation * +motion_orientation_ptr(const struct motion_sensor_t *s); void motion_orientation_update(const struct motion_sensor_t *s); -#endif /* __CROS_EC_MOTION_ORIENTATION_H */ +#endif /* __CROS_EC_MOTION_ORIENTATION_H */ -- cgit v1.2.1 From afc0b691e1307a06f8b967f89ea03908b40a4067 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:29 -0600 Subject: board/brya/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4446552677c42ac4294311ed09f07f41c41dff55 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728102 Reviewed-by: Jeremy Bettis --- board/brya/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brya/i2c.c b/board/brya/i2c.c index 1e405f4216..15322ffa9f 100644 --- a/board/brya/i2c.c +++ b/board/brya/i2c.c @@ -9,7 +9,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From 9ef2f1ee7a90d629960c669be78f2446200505bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:43 -0600 Subject: board/taniks/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97b57149a73c53056d962250e8b6b7be2b8a4bd9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729008 Reviewed-by: Jeremy Bettis --- board/taniks/board.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/taniks/board.c b/board/taniks/board.c index 894e055b9a..98775a10fd 100644 --- a/board/taniks/board.c +++ b/board/taniks/board.c @@ -34,8 +34,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -102,8 +102,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -119,7 +119,7 @@ enum battery_present battery_hw_present(void) } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Follow OEM request to limit the input current to @@ -127,7 +127,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From d7c95c8d58bfe69d5e535dd82d14d820b6a7be8c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:51 -0600 Subject: driver/ln9310.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id3553eebf1a6556351bc2c7f68ececc3d89071b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730005 Reviewed-by: Jeremy Bettis --- driver/ln9310.c | 219 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 109 insertions(+), 110 deletions(-) diff --git a/driver/ln9310.c b/driver/ln9310.c index 4214b3b514..23410723dc 100644 --- a/driver/ln9310.c +++ b/driver/ln9310.c @@ -14,8 +14,8 @@ #include "timer.h" #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) static int power_good; static int startup_workaround_required; @@ -27,19 +27,15 @@ int ln9310_power_good(void) static inline int raw_read8(int offset, int *value) { - return i2c_read8(ln9310_config.i2c_port, - ln9310_config.i2c_addr_flags, - offset, - value); + return i2c_read8(ln9310_config.i2c_port, ln9310_config.i2c_addr_flags, + offset, value); } static inline int field_update8(int offset, int mask, int value) { /* Clear mask and then set value in i2c reg value */ return i2c_field_update8(ln9310_config.i2c_port, - ln9310_config.i2c_addr_flags, - offset, - mask, + ln9310_config.i2c_addr_flags, offset, mask, value); } @@ -87,11 +83,12 @@ static int is_battery_gt_10v(bool *out) * Turn on INFET_OUT_SWITCH_OK comparator; * configure INFET_OUT_SWITCH_OK to 10V. */ - status = field_update8(LN9310_REG_TRACK_CTRL, - LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK | - LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK, - LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON | - LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V); + status = + field_update8(LN9310_REG_TRACK_CTRL, + LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK | + LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_MASK, + LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_ON | + LN9310_TRACK_INFET_OUT_SWITCH_OK_CFG_10V); if (status != EC_SUCCESS) return status; @@ -112,8 +109,8 @@ static int is_battery_gt_10v(bool *out) /* Turn off INFET_OUT_SWITCH_OK comparator */ status = field_update8(LN9310_REG_TRACK_CTRL, - LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK, - LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF); + LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_MASK, + LN9310_TRACK_INFET_OUT_SWITCH_OK_EN_OFF); return status; } @@ -237,11 +234,11 @@ static int ln9310_init_2to1(void) /* Enable 2:1 operation mode */ rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_OP_MODE_MASK, - LN9310_PWR_OP_MODE_SWITCH21); + LN9310_PWR_OP_MODE_SWITCH21); /* 2S lower bound delta configurations */ rc |= field_update8(LN9310_REG_LB_CTRL, LN9310_LB_DELTA_MASK, - LN9310_LB_DELTA_2S); + LN9310_LB_DELTA_2S); /* * TODO(waihong): The LN9310_REG_SYS_CTR was set to a wrong value @@ -263,23 +260,24 @@ static int ln9310_update_infet(void) /* Update Infet register settings */ rc |= field_update8(LN9310_REG_CFG_5, LN9310_CFG_5_INGATE_PD_EN_MASK, - LN9310_CFG_5_INGATE_PD_EN_OFF); + LN9310_CFG_5_INGATE_PD_EN_OFF); rc |= field_update8(LN9310_REG_CFG_5, - LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK, - LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST); + LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_MASK, + LN9310_CFG_5_INFET_CP_PD_BIAS_CFG_LOWEST); /* enable automatic infet control */ - rc |= field_update8(LN9310_REG_PWR_CTRL, LN9310_PWR_INFET_AUTO_MODE_MASK, - LN9310_PWR_INFET_AUTO_MODE_ON); + rc |= field_update8(LN9310_REG_PWR_CTRL, + LN9310_PWR_INFET_AUTO_MODE_MASK, + LN9310_PWR_INFET_AUTO_MODE_ON); /* disable LS_HELPER during IDLE by setting MSK bit high */ rc |= field_update8(LN9310_REG_CFG_0, - LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK, - LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON); + LN9310_CFG_0_LS_HELPER_IDLE_MSK_MASK, + LN9310_CFG_0_LS_HELPER_IDLE_MSK_ON); rc |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK, - LN9310_LION_CTRL_LOCK); + LN9310_LION_CTRL_LOCK); return rc == EC_SUCCESS ? EC_SUCCESS : EC_ERROR_UNKNOWN; } @@ -290,40 +288,40 @@ static int ln9310_precharge_cfly(uint64_t *precharge_timeout) CPRINTS("LN9310 precharge cfly"); /* Unlock registers and enable test mode */ - status |= field_update8(LN9310_REG_LION_CTRL, - LN9310_LION_CTRL_MASK, - LN9310_LION_CTRL_UNLOCK_AND_EN_TM); + status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK, + LN9310_LION_CTRL_UNLOCK_AND_EN_TM); /* disable test mode overrides */ status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF); + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF); /* Configure test mode target values for precharge ckts. */ - status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1, - LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK, - LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON); + status |= field_update8( + LN9310_REG_FORCE_SC21_CTRL_1, + LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK, + LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_ON); /* Force SCOUT precharge/predischarge overrides */ - status |= field_update8(LN9310_REG_TEST_MODE_CTRL, - LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK | + status |= field_update8( + LN9310_REG_TEST_MODE_CTRL, + LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK | LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK, - LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON | + LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_ON | LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_ON); /* Force enable CFLY precharge overrides */ status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON); + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_ON); /* delay long enough to ensure CFLY has time to fully precharge */ usleep(LN9310_CFLY_PRECHARGE_DELAY); /* locking and leaving test mode will stop CFLY precharge */ *precharge_timeout = get_time().val + LN9310_CFLY_PRECHARGE_TIMEOUT; - status |= field_update8(LN9310_REG_LION_CTRL, - LN9310_LION_CTRL_MASK, - LN9310_LION_CTRL_LOCK); + status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK, + LN9310_LION_CTRL_LOCK); return status; } @@ -334,30 +332,30 @@ static int ln9310_precharge_cfly_reset(void) CPRINTS("LN9310 precharge cfly reset"); /* set known initial state for config bits related to cfly precharge */ - status |= field_update8(LN9310_REG_LION_CTRL, - LN9310_LION_CTRL_MASK, - LN9310_LION_CTRL_UNLOCK); + status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK, + LN9310_LION_CTRL_UNLOCK); /* Force off SCOUT precharge/predischarge overrides */ - status |= field_update8(LN9310_REG_TEST_MODE_CTRL, - LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK | + status |= field_update8( + LN9310_REG_TEST_MODE_CTRL, + LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_MASK | LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_MASK, - LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF | + LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PRECHARGE_OFF | LN9310_TEST_MODE_CTRL_FORCE_SC_OUT_PREDISCHARGE_OFF); /* disable test mode overrides */ status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_2, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, - LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF); + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_MASK, + LN9310_FORCE_SC21_CTRL_2_FORCE_SW_CTRL_REQ_OFF); /* disable CFLY and SC_OUT precharge control */ - status |= field_update8(LN9310_REG_FORCE_SC21_CTRL_1, - LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK, - LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF); + status |= field_update8( + LN9310_REG_FORCE_SC21_CTRL_1, + LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_MASK, + LN9310_FORCE_SC21_CTRL_1_TM_SC_OUT_CFLY_PRECHARGE_OFF); - status |= field_update8(LN9310_REG_LION_CTRL, - LN9310_LION_CTRL_MASK, - LN9310_LION_CTRL_LOCK); + status |= field_update8(LN9310_REG_LION_CTRL, LN9310_LION_CTRL_MASK, + LN9310_LION_CTRL_LOCK); return status; } @@ -368,9 +366,7 @@ int ln9310_init(void) enum battery_cell_type batt; /* Make sure initial state of LN9310 is STANDBY (i.e. output is off) */ - field_update8(LN9310_REG_STARTUP_CTRL, - LN9310_STARTUP_STANDBY_EN, - 1); + field_update8(LN9310_REG_STARTUP_CTRL, LN9310_STARTUP_STANDBY_EN, 1); /* * LN9310 software startup is only required for earlier silicon revs. @@ -383,7 +379,8 @@ int ln9310_init(void) return status; } chip_revision = val & LN9310_BC_STS_C_CHIP_REV_MASK; - startup_workaround_required = chip_revision < LN9310_BC_STS_C_CHIP_REV_FIXED; + startup_workaround_required = chip_revision < + LN9310_BC_STS_C_CHIP_REV_FIXED; /* Update INFET configuration */ status = ln9310_update_infet(); @@ -400,8 +397,7 @@ int ln9310_init(void) LN9310_PWR_OP_MODE_MANUAL_UPDATE_MASK, LN9310_PWR_OP_MODE_MANUAL_UPDATE_OFF); - field_update8(LN9310_REG_TIMER_CTRL, - LN9310_TIMER_OP_SELF_SYNC_EN_MASK, + field_update8(LN9310_REG_TIMER_CTRL, LN9310_TIMER_OP_SELF_SYNC_EN_MASK, LN9310_TIMER_OP_SELF_SYNC_EN_ON); /* @@ -409,16 +405,13 @@ int ln9310_init(void) * circuit time to settle. */ field_update8(LN9310_REG_STARTUP_CTRL, - LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR, - 0); + LN9310_STARTUP_SELECT_EXT_5V_FOR_VDR, 0); - field_update8(LN9310_REG_LB_CTRL, - LN9310_LB_MIN_FREQ_EN, + field_update8(LN9310_REG_LB_CTRL, LN9310_LB_MIN_FREQ_EN, LN9310_LB_MIN_FREQ_EN); /* Set minimum switching frequency to 25 kHz */ - field_update8(LN9310_REG_SPARE_0, - LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK, + field_update8(LN9310_REG_SPARE_0, LN9310_SPARE_0_LB_MIN_FREQ_SEL_MASK, LN9310_SPARE_0_LB_MIN_FREQ_SEL_ON); usleep(LN9310_CDC_DELAY); @@ -445,9 +438,7 @@ int ln9310_init(void) return status; /* Unmask the MODE change interrupt */ - field_update8(LN9310_REG_INT1_MSK, - LN9310_INT1_MODE, - 0); + field_update8(LN9310_REG_INT1_MSK, LN9310_INT1_MODE, 0); return EC_SUCCESS; } @@ -495,20 +486,22 @@ void ln9310_software_enable(int enable) if (startup_workaround_required) { if (enable) { /* - * Software modification of LN9310 startup sequence w/ retry - * loop. - * - * (1) Clear interrupts - * (2) Precharge Cfly w/ overrides of internal LN9310 signals - * (3) disable overrides -> stop precharging Cfly - * (4.1) if < 100 ms elapsed since (2) -> trigger LN9310 internal - * startup seq. - * (4.2) else -> abort and optionally retry from step 2 - */ + * Software modification of LN9310 startup sequence w/ + * retry loop. + * + * (1) Clear interrupts + * (2) Precharge Cfly w/ overrides of internal LN9310 + * signals (3) disable overrides -> stop precharging + * Cfly (4.1) if < 100 ms elapsed since (2) -> trigger + * LN9310 internal startup seq. (4.2) else -> abort and + * optionally retry from step 2 + */ retry_count = 0; - while (!ln9310_init_completed && retry_count < LN9310_INIT_RETRY_COUNT) { + while (!ln9310_init_completed && + retry_count < LN9310_INIT_RETRY_COUNT) { /* Precharge CFLY before starting up */ - status = ln9310_precharge_cfly(&precharge_timeout); + status = ln9310_precharge_cfly( + &precharge_timeout); if (status != EC_SUCCESS) { CPRINTS("LN9310 failed to run Cfly precharge sequence"); status = ln9310_precharge_cfly_reset(); @@ -517,58 +510,64 @@ void ln9310_software_enable(int enable) } /* - * Only start the SC if the cfly precharge - * hasn't timed out (i.e. ended too long ago) - */ + * Only start the SC if the cfly precharge + * hasn't timed out (i.e. ended too long ago) + */ if (get_time().val < precharge_timeout) { - /* Clear the STANDBY_EN bit to enable the SC */ + /* Clear the STANDBY_EN bit to enable + * the SC */ field_update8(LN9310_REG_STARTUP_CTRL, - LN9310_STARTUP_STANDBY_EN, - 0); - if (get_time().val > precharge_timeout ) { + LN9310_STARTUP_STANDBY_EN, + 0); + if (get_time().val > + precharge_timeout) { /* - * if timed out during previous I2C command, abort - * startup attempt - */ - field_update8(LN9310_REG_STARTUP_CTRL, + * if timed out during previous + * I2C command, abort startup + * attempt + */ + field_update8( + LN9310_REG_STARTUP_CTRL, LN9310_STARTUP_STANDBY_EN, 1); } else { - /* all other paths should reattempt startup */ + /* all other paths should + * reattempt startup */ ln9310_init_completed = true; } } - /* Reset to known state for config bits related to cfly precharge */ + /* Reset to known state for config bits related + * to cfly precharge */ ln9310_precharge_cfly_reset(); retry_count++; } if (!ln9310_init_completed) { CPRINTS("LN9310 failed to start after %d retry attempts", - retry_count); + retry_count); } } else { /* - * Internal LN9310 shutdown sequence is ok as is, so just reset - * the state to prepare for subsequent startup sequences. - * - * (1) set STANDBY_EN=1 to be sure the part turns off even if nEN=0 - * (2) reset cfly precharge related registers to known initial state - */ + * Internal LN9310 shutdown sequence is ok as is, so + * just reset the state to prepare for subsequent + * startup sequences. + * + * (1) set STANDBY_EN=1 to be sure the part turns off + * even if nEN=0 (2) reset cfly precharge related + * registers to known initial state + */ field_update8(LN9310_REG_STARTUP_CTRL, - LN9310_STARTUP_STANDBY_EN, - 1); + LN9310_STARTUP_STANDBY_EN, 1); ln9310_precharge_cfly_reset(); } } else { /* - * for newer LN9310 revsisions, the startup workaround is not required - * so the STANDBY_EN bit can just be set directly - */ + * for newer LN9310 revsisions, the startup workaround is not + * required so the STANDBY_EN bit can just be set directly + */ field_update8(LN9310_REG_STARTUP_CTRL, - LN9310_STARTUP_STANDBY_EN, - !enable); + LN9310_STARTUP_STANDBY_EN, !enable); } return; } -- cgit v1.2.1 From 6e686cae0326b9cb566d0f2f73c18ad915a618bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:18 -0600 Subject: driver/usb_mux/anx7440.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1bd0a36f27039cb2a9957e9783940a8b2f6db0f6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730158 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx7440.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/driver/usb_mux/anx7440.h b/driver/usb_mux/anx7440.h index 2147e3146a..0e790dc9da 100644 --- a/driver/usb_mux/anx7440.h +++ b/driver/usb_mux/anx7440.h @@ -16,25 +16,25 @@ #define I2C_ADDR_USB_MUX1_FLAGS ANX7440_I2C_ADDR2_FLAGS /* Vendor / Device Id registers and expected fused values */ -#define ANX7440_REG_VENDOR_ID_L 0x00 -#define ANX7440_VENDOR_ID_L 0xaa -#define ANX7440_REG_VENDOR_ID_H 0x01 -#define ANX7440_VENDOR_ID_H 0xaa -#define ANX7440_REG_DEVICE_ID_L 0x02 -#define ANX7440_DEVICE_ID_L 0x40 -#define ANX7440_REG_DEVICE_ID_H 0x03 -#define ANX7440_DEVICE_ID_H 0x74 +#define ANX7440_REG_VENDOR_ID_L 0x00 +#define ANX7440_VENDOR_ID_L 0xaa +#define ANX7440_REG_VENDOR_ID_H 0x01 +#define ANX7440_VENDOR_ID_H 0xaa +#define ANX7440_REG_DEVICE_ID_L 0x02 +#define ANX7440_DEVICE_ID_L 0x40 +#define ANX7440_REG_DEVICE_ID_H 0x03 +#define ANX7440_DEVICE_ID_H 0x74 #define ANX7440_REG_DEVICE_VERSION 0x04 -#define ANX7440_DEVICE_VERSION 0xCB +#define ANX7440_DEVICE_VERSION 0xCB /* Chip control register for checking mux state */ -#define ANX7440_REG_CHIP_CTRL 0x05 -#define ANX7440_CHIP_CTRL_FINAL_FLIP BIT(6) -#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP BIT(5) +#define ANX7440_REG_CHIP_CTRL 0x05 +#define ANX7440_CHIP_CTRL_FINAL_FLIP BIT(6) +#define ANX7440_CHIP_CTRL_OP_MODE_FINAL_DP BIT(5) #define ANX7440_CHIP_CTRL_OP_MODE_FINAL_USB BIT(4) -#define ANX7440_CHIP_CTRL_SW_FLIP BIT(2) -#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP BIT(1) -#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB BIT(0) -#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR 0x7 +#define ANX7440_CHIP_CTRL_SW_FLIP BIT(2) +#define ANX7440_CHIP_CTRL_SW_OP_MODE_DP BIT(1) +#define ANX7440_CHIP_CTRL_SW_OP_MODE_USB BIT(0) +#define ANX7440_CHIP_CTRL_SW_OP_MODE_CLEAR 0x7 #endif /* __CROS_EC_USB_MUX_ANX7440_H */ -- cgit v1.2.1 From 3bf4b87e7d1fafdfab3f6ab8e7f6f7a1232539af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:21 -0600 Subject: include/wireless.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3a913536a59d708087757a5d7f1a885053655afd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730459 Reviewed-by: Jeremy Bettis --- include/wireless.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/include/wireless.h b/include/wireless.h index d209d69fed..95836d6da9 100644 --- a/include/wireless.h +++ b/include/wireless.h @@ -11,11 +11,7 @@ #include "common.h" /* Wireless power state for wireless_set_state() */ -enum wireless_power_state { - WIRELESS_OFF, - WIRELESS_SUSPEND, - WIRELESS_ON -}; +enum wireless_power_state { WIRELESS_OFF, WIRELESS_SUSPEND, WIRELESS_ON }; /** * Set wireless power state. @@ -23,7 +19,9 @@ enum wireless_power_state { #ifdef CONFIG_WIRELESS void wireless_set_state(enum wireless_power_state state); #else -static inline void wireless_set_state(enum wireless_power_state state) { } +static inline void wireless_set_state(enum wireless_power_state state) +{ +} #endif -#endif /* __CROS_EC_WIRELESS_H */ +#endif /* __CROS_EC_WIRELESS_H */ -- cgit v1.2.1 From 4c3365ef9e389b16bba552ec58f7bc31bf2a7ca9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:41 -0600 Subject: board/nightfury/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I455fbbacfb4851f0caac1fae6da1b6277534feab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728748 Reviewed-by: Jeremy Bettis --- board/nightfury/board.h | 58 +++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/board/nightfury/board.h b/board/nightfury/board.h index 67e55f974e..fdfc1af5dd 100644 --- a/board/nightfury/board.h +++ b/board/nightfury/board.h @@ -45,7 +45,7 @@ /* BH1730 and TCS3400 ALS */ #define CONFIG_ALS #define ALS_COUNT 1 -#define I2C_PORT_ALS I2C_PORT_SENSOR +#define I2C_PORT_ALS I2C_PORT_SENSOR #define CONFIG_ALS_OPT3001 #define OPT3001_I2C_ADDR_FLAGS OPT3001_I2C_ADDR1_FLAGS @@ -66,18 +66,18 @@ * Nightfury will not use both BH1730_LUXTH3_1K condition * and BH1730_LUXTH4_1K condition. */ -#define BH1730_LUXTH1_1K 270 -#define BH1730_LUXTH1_D0_1K 19200 -#define BH1730_LUXTH1_D1_1K 30528 -#define BH1730_LUXTH2_1K 655360000 -#define BH1730_LUXTH2_D0_1K 11008 -#define BH1730_LUXTH2_D1_1K 10752 -#define BH1730_LUXTH3_1K 1030 -#define BH1730_LUXTH3_D0_1K 11008 -#define BH1730_LUXTH3_D1_1K 10752 -#define BH1730_LUXTH4_1K 3670 -#define BH1730_LUXTH4_D0_1K 11008 -#define BH1730_LUXTH4_D1_1K 10752 +#define BH1730_LUXTH1_1K 270 +#define BH1730_LUXTH1_D0_1K 19200 +#define BH1730_LUXTH1_D1_1K 30528 +#define BH1730_LUXTH2_1K 655360000 +#define BH1730_LUXTH2_D0_1K 11008 +#define BH1730_LUXTH2_D1_1K 10752 +#define BH1730_LUXTH3_1K 1030 +#define BH1730_LUXTH3_D0_1K 11008 +#define BH1730_LUXTH3_D1_1K 10752 +#define BH1730_LUXTH4_1K 3670 +#define BH1730_LUXTH4_D0_1K 11008 +#define BH1730_LUXTH4_D1_1K 10752 /* USB Type C and USB PD defines */ #define CONFIG_USB_MUX_RUNTIME_CONFIG @@ -132,16 +132,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -152,9 +152,9 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC3 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC3 */ ADC_CH_COUNT }; @@ -166,11 +166,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From eb9ec5c49fe1d9023ce75db16062f4f744b9ba66 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:52 -0600 Subject: zephyr/projects/nissa/src/joxer/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc56eaea4e90722c4c4c1e6769c19507eb535652 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730786 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/joxer/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/nissa/src/joxer/keyboard.c b/zephyr/projects/nissa/src/joxer/keyboard.c index 9deb799d13..2694445ca0 100644 --- a/zephyr/projects/nissa/src/joxer/keyboard.c +++ b/zephyr/projects/nissa/src/joxer/keyboard.c @@ -22,8 +22,8 @@ static const struct ec_response_keybd_config joxer_kb_legacy = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &joxer_kb_legacy; } -- cgit v1.2.1 From 9a122e5194e664251151d3b3a45e2444774791d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:40 -0600 Subject: board/vell/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida4636bf56a5444ecf95027f1bf716e519277e81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729051 Reviewed-by: Jeremy Bettis --- board/vell/board.h | 131 ++++++++++++++++++++++++----------------------------- 1 file changed, 60 insertions(+), 71 deletions(-) diff --git a/board/vell/board.h b/board/vell/board.h index b7ce13760e..38efba5c7e 100644 --- a/board/vell/board.h +++ b/board/vell/board.h @@ -45,13 +45,12 @@ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(CLEAR_ALS) - /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 4 +#define CONFIG_IO_EXPANDER_PORT_COUNT 4 #define CONFIG_USB_PD_FRS_PPC @@ -63,16 +62,16 @@ #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* USB Type C and USB PD defines */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Max Power = 100 W */ -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) /* * Macros for GPIO signals used in common code that don't match the @@ -80,68 +79,68 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_RIGHT_LED_AMBER_L GPIO_LED_1_L -#define GPIO_RIGHT_LED_WHITE_L GPIO_LED_2_L -#define GPIO_LEFT_LED_AMBER_L GPIO_LED_3_L -#define GPIO_LEFT_LED_WHITE_L GPIO_LED_4_L +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_RIGHT_LED_AMBER_L GPIO_LED_1_L +#define GPIO_RIGHT_LED_WHITE_L GPIO_LED_2_L +#define GPIO_LEFT_LED_AMBER_L GPIO_LED_3_L +#define GPIO_LEFT_LED_WHITE_L GPIO_LED_4_L /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C2_C3_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C2_C3_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C2_C3_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C2_C3_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C2_C3_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C2_C3_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 -#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C3_BB_RETIMER_I2C_ADDR 0x59 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -166,22 +165,22 @@ #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B /* Fan features */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT #define CONFIG_CUSTOM_FAN_CONTROL -#define RPM_DEVIATION 1 +#define RPM_DEVIATION 1 /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 5 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 5 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Keyboard features */ #define CONFIG_KEYBOARD_FACTORY_TEST #define CONFIG_KEYBOARD_REFRESH_ROW3 #undef CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE -#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3 +#define CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE 3 /* * Older boards have a different ADC assignment. @@ -191,7 +190,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -213,11 +212,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - CLEAR_ALS = 0, - RGB_ALS, - SENSOR_COUNT -}; +enum sensor_id { CLEAR_ALS = 0, RGB_ALS, SENSOR_COUNT }; enum ioex_port { IOEX_C0_NCT38XX = 0, @@ -234,20 +229,14 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #ifdef CONFIG_KEYBOARD_FACTORY_TEST extern const int keyboard_factory_scan_pins[][2]; -- cgit v1.2.1 From dcbab4bbb31a1ea4c0098ec3a01b544d049f2f6c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:18 -0600 Subject: board/lantis/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a95a99c880ce5b0eeece546a30573dfcbaf23d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728617 Reviewed-by: Jeremy Bettis --- board/lantis/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lantis/usb_pd_policy.c b/board/lantis/usb_pd_policy.c index 7046e25d6c..042adc0a86 100644 --- a/board/lantis/usb_pd_policy.c +++ b/board/lantis/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From b98d59479ae6434a9137cba5b6714e3cfe7a1875 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:47 -0600 Subject: chip/it83xx/config_chip_it8xxx2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8ff365598628abf915f5a9b1bc08ce89786ff58 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729194 Reviewed-by: Jeremy Bettis --- chip/it83xx/config_chip_it8xxx2.h | 49 ++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 0bbfe89b59..45a92a3d82 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -15,7 +15,7 @@ #define CHIP_CORE_RISCV #define CHIP_ILM_DLM_ORDER /* The base address of EC interrupt controller registers. */ -#define CHIP_EC_INTC_BASE 0x00F03F00 +#define CHIP_EC_INTC_BASE 0x00F03F00 #define CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* * ILM/DLM size register. @@ -27,11 +27,11 @@ /****************************************************************************/ /* Memory mapping */ -#define CHIP_ILM_BASE 0x80000000 -#define CHIP_EXTRA_STACK_SPACE 128 +#define CHIP_ILM_BASE 0x80000000 +#define CHIP_EXTRA_STACK_SPACE 128 /* We reserve 12KB space for ramcode, h2ram, and immu sections. */ -#define CHIP_RAM_SPACE_RESERVED 0x3000 -#define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE) +#define CHIP_RAM_SPACE_RESERVED 0x3000 +#define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE) /****************************************************************************/ /* Chip IT83202 is used with IT8XXX2 TCPM driver */ @@ -39,9 +39,9 @@ #if defined(CHIP_VARIANT_IT83202BX) /* TODO(b/133460224): enable properly chip config option. */ -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 -#define CONFIG_RAM_BASE 0x80080000 -#define CONFIG_RAM_SIZE 0x00010000 +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 +#define CONFIG_RAM_BASE 0x80080000 +#define CONFIG_RAM_SIZE 0x00010000 /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD @@ -80,12 +80,12 @@ /* Enable detect type-c plug in and out interrupt. */ #define IT83XX_INTC_PLUG_IN_OUT_SUPPORT /* Chip IT83202BX actually has TCPC physical port count. */ -#define IT83XX_USBPD_PHY_PORT_COUNT 3 -#elif defined(CHIP_VARIANT_IT81302AX_1024) \ -|| defined(CHIP_VARIANT_IT81202AX_1024) \ -|| defined(CHIP_VARIANT_IT81302BX_1024) \ -|| defined(CHIP_VARIANT_IT81302BX_512) \ -|| defined(CHIP_VARIANT_IT81202BX_1024) +#define IT83XX_USBPD_PHY_PORT_COUNT 3 +#elif defined(CHIP_VARIANT_IT81302AX_1024) || \ + defined(CHIP_VARIANT_IT81202AX_1024) || \ + defined(CHIP_VARIANT_IT81302BX_1024) || \ + defined(CHIP_VARIANT_IT81302BX_512) || \ + defined(CHIP_VARIANT_IT81202BX_1024) /* * Workaround mul instruction bug, see: @@ -95,16 +95,16 @@ #define CONFIG_IT8XXX2_MUL_WORKAROUND #if defined(CHIP_VARIANT_IT81302BX_512) -#define CONFIG_FLASH_SIZE_BYTES 0x00080000 -#define CONFIG_RAM_BASE 0x80080000 +#define CONFIG_FLASH_SIZE_BYTES 0x00080000 +#define CONFIG_RAM_BASE 0x80080000 #else -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 -#define CONFIG_RAM_BASE 0x80100000 +#define CONFIG_FLASH_SIZE_BYTES 0x00100000 +#define CONFIG_RAM_BASE 0x80100000 /* Set ILM (instruction local memory) size up to 1M bytes */ #define IT83XX_CHIP_FLASH_SIZE_1MB #endif -#define CONFIG_RAM_SIZE 0x0000f000 +#define CONFIG_RAM_SIZE 0x0000f000 /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD @@ -151,14 +151,15 @@ /* Individual setting CC1 and CC2 resistance. */ #define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE /* Chip actually has TCPC physical port count. */ -#define IT83XX_USBPD_PHY_PORT_COUNT 2 +#define IT83XX_USBPD_PHY_PORT_COUNT 2 #else #error "Unsupported chip variant!" #endif -#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */ -#define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */ -#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */ +#define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */ +#define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */ +#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF \ + */ #ifdef BASEBOARD_KUKUI /* @@ -173,4 +174,4 @@ #define CONFIG_FLASH_SIZE_BYTES CHIP_FLASH_PRESERVE_LOGS_BASE #endif -#endif /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */ +#endif /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */ -- cgit v1.2.1 From 8161b6a9b961700d37edf3c7f318368c14a3aef6 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Wed, 15 Jun 2022 00:59:02 -0700 Subject: chip/stm32: Add support for USB forwarding of LPUART The LPUART is treated as UART9 by the EC codebase, for the purpose of running the system console. This CL adds the option of performing USB forwarding on the LPUART, in the same way as the ordinary numbered UARTS. In particular, the LPUART clock divisor formula is different by a factor of 256, which was already handled in uart.c, but not in usart.c. BUG=b:192262089 TEST=Observed UART forwarding on HyperDebug BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: I1661c7dbbc48ddf556fc14d02e9f438ab2773fcc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3706579 Reviewed-by: Aseda Aboagye --- chip/stm32/usart-stm32l5.c | 20 +++++++++++++++++++- chip/stm32/usart-stm32l5.h | 1 + chip/stm32/usart.c | 10 ++++++++++ util/config_allowed.txt | 2 ++ 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 2306f54606..4753370560 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -17,7 +17,7 @@ * each USART, an entry will be NULL if no USART driver is initialized for the * corresponding hardware instance. */ -#define STM32_USARTS_MAX 5 +#define STM32_USARTS_MAX 6 static struct usart_config const *configs[STM32_USARTS_MAX]; @@ -166,3 +166,21 @@ static void usart5_interrupt(void) DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2); #endif + +#if defined(CONFIG_STREAM_USART9) +struct usart_hw_config const usart9_hw = { + .index = 5, + .base = STM32_USART9_BASE, + .irq = STM32_IRQ_USART9, + .clock_register = &STM32_RCC_APB1ENR2, + .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, + .ops = &usart_variant_hw_ops, +}; + +static void usart9_interrupt(void) +{ + usart_interrupt(configs[5]); +} + +DECLARE_IRQ(STM32_IRQ_USART9, usart9_interrupt, 2); +#endif diff --git a/chip/stm32/usart-stm32l5.h b/chip/stm32/usart-stm32l5.h index cf4f8cdd1f..5bac6e0291 100644 --- a/chip/stm32/usart-stm32l5.h +++ b/chip/stm32/usart-stm32l5.h @@ -16,5 +16,6 @@ extern struct usart_hw_config const usart2_hw; extern struct usart_hw_config const usart3_hw; extern struct usart_hw_config const usart4_hw; extern struct usart_hw_config const usart5_hw; +extern struct usart_hw_config const usart9_hw; /* LPUART1 */ #endif /* __CROS_EC_USART_STM32L5_H */ diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index c4f3f9bf74..423ef3904a 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -92,6 +92,11 @@ void usart_set_baud_f0_l(struct usart_config const *config, int baud, int div = DIV_ROUND_NEAREST(frequency_hz, baud); intptr_t base = config->hw->base; +#ifdef STM32_USART9_BASE + if (config->hw->base == STM32_USART9_BASE) /* LPUART */ + div *= 256; +#endif + if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -114,6 +119,11 @@ void usart_set_baud_f(struct usart_config const *config, int baud, { int div = DIV_ROUND_NEAREST(frequency_hz, baud); +#ifdef STM32_USART9_BASE + if (config->hw->base == STM32_USART9_BASE) /* LPUART */ + div *= 256; +#endif + /* STM32F only supports x16 oversampling */ STM32_USART_BRR(config->hw->base) = div; } diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 37936cab97..58317b8384 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -857,6 +857,8 @@ CONFIG_STREAM_USART1 CONFIG_STREAM_USART2 CONFIG_STREAM_USART3 CONFIG_STREAM_USART4 +CONFIG_STREAM_USART5 +CONFIG_STREAM_USART9 CONFIG_STREAM_USB CONFIG_SUPPORT_CHIP_HIBERNATION CONFIG_SUPPRESSED_HOST_COMMANDS -- cgit v1.2.1 From c17f1b7eb70109b407edb798e2e5dc4d3b6c6c78 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:15 -0600 Subject: chip/npcx/registers-npcx7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I235438b63d1e41a452f98c875ac75057d33ab897 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727026 Reviewed-by: Jeremy Bettis --- chip/npcx/registers-npcx7.h | 645 ++++++++++++++++++++++---------------------- 1 file changed, 321 insertions(+), 324 deletions(-) diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h index 535abfbf0f..98545dee24 100644 --- a/chip/npcx/registers-npcx7.h +++ b/chip/npcx/registers-npcx7.h @@ -24,106 +24,104 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 #ifdef NPCX_WOV_SUPPORT -#define NPCX_IRQ4_NOUSED NPCX_IRQ_4 +#define NPCX_IRQ4_NOUSED NPCX_IRQ_4 #else -#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ_PECI NPCX_IRQ_4 #endif -#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 -#define NPCX_IRQ_SMB8 NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ_SMB7 NPCX_IRQ_16 -#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ_SMB5 NPCX_IRQ_19 -#define NPCX_IRQ_SMB6 NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 +#define NPCX_IRQ_SMB8 NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ_SMB7 NPCX_IRQ_16 +#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ_SMB5 NPCX_IRQ_19 +#define NPCX_IRQ_SMB6 NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 #ifdef NPCX_WOV_SUPPORT -#define NPCX_IRQ_WOV NPCX_IRQ_22 +#define NPCX_IRQ_WOV NPCX_IRQ_22 #else -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 #endif -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 -#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ_UART2 NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 -#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 -#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 -#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 +#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ_UART2 NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 +#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 +#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 +#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 #ifdef NPCX_ITIM64_SUPPORT -#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 +#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 #else -#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 +#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 #endif -#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - -#define NPCX_ITIM32_BASE_ADDR 0x400BC000 -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - ((mdl) < 4) ? \ - (0x400C0000 + (((mdl) - 2) * 0x2000L)) : \ - ((mdl) == 4) ? \ - (0x40008000) : \ - (0x40017000 + (((mdl) - 5) * 0x1000L))) - -#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) -#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 + +#define NPCX_ITIM32_BASE_ADDR 0x400BC000 +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L)) +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + ((mdl) < 4) ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \ + ((mdl) == 4) ? (0x40008000) : \ + (0x40017000 + (((mdl)-5) * 0x1000L))) + +#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) +#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) enum { NPCX_UART_PORT0 = 0, /* UART port 0 */ @@ -135,44 +133,44 @@ enum { #ifdef NPCX_UART_FIFO_SUPPORT /* UART registers only used for FIFO mode */ -#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) -#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) -#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) -#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) +#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) +#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) +#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) +#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) /* UART FIFO register fields */ -#define NPCX_UMDSL_FIFO_MD 0 - -#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) -#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 -#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 -#define NPCX_UFTSTS_NXMIP 7 - -#define NPCX_UFRSTS_RFULL_LVL_STS 5 -#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 -#define NPCX_UFRSTS_ERR 7 - -#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) -#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 -#define NPCX_UFTCTL_TEMPTY_EN 6 -#define NPCX_UFTCTL_NXMIPEN 7 - -#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) -#define NPCX_UFRCTL_RFULL_LVL_EN 5 -#define NPCX_UFRCTL_RNEMPTY_EN 6 -#define NPCX_UFRCTL_ERR_EN 7 +#define NPCX_UMDSL_FIFO_MD 0 + +#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) +#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 +#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 +#define NPCX_UFTSTS_NXMIP 7 + +#define NPCX_UFRSTS_RFULL_LVL_STS 5 +#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 +#define NPCX_UFRSTS_ERR 7 + +#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) +#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 +#define NPCX_UFTCTL_TEMPTY_EN 6 +#define NPCX_UFTCTL_NXMIPEN 7 + +#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) +#define NPCX_UFRCTL_RFULL_LVL_EN 5 +#define NPCX_UFRCTL_RNEMPTY_EN 6 +#define NPCX_UFRCTL_ERR_EN 7 #endif /* KBSCAN register fields */ -#define NPCX_KBHDRV_FIELD FIELD(6, 2) +#define NPCX_KBHDRV_FIELD FIELD(6, 2) /* GLUE registers */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) +#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) #endif /* GPIO registers */ -#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) +#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) /* System Configuration (SCFG) Registers */ @@ -197,112 +195,112 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ - (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ - (NPCX_SCFG_BASE_ADDR + 0x026)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) +#define NPCX_LV_GPIO_CTL_ADDR(n) \ + (((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \ + (NPCX_SCFG_BASE_ADDR + 0x026)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C7_0_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C6_0_SL 3 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C5_0_SL 5 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#define NPCX_DEVALT2_I2C4_0_SL 7 -#define NPCX_DEVALT6_I2C6_1_SL 5 -#define NPCX_DEVALT6_I2C5_1_SL 6 -#define NPCX_DEVALT6_I2C4_1_SL 7 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C7_0_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C6_0_SL 3 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C5_0_SL 5 +#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT2_I2C4_0_SL 7 +#define NPCX_DEVALT6_I2C6_1_SL 5 +#define NPCX_DEVALT6_I2C5_1_SL 6 +#define NPCX_DEVALT6_I2C4_1_SL 7 /* pin-mux for JTAG */ -#define NPCX_DEVALT5_NJEN1_EN 1 -#define NPCX_DEVALT5_NJEN0_EN 2 +#define NPCX_DEVALT5_NJEN1_EN 1 +#define NPCX_DEVALT5_NJEN0_EN 2 /* pin-mux for ADC */ -#define NPCX_DEVALTF_ADC5_SL 0 -#define NPCX_DEVALTF_ADC6_SL 1 -#define NPCX_DEVALTF_ADC7_SL 2 -#define NPCX_DEVALTF_ADC8_SL 3 -#define NPCX_DEVALTF_ADC9_SL 4 +#define NPCX_DEVALTF_ADC5_SL 0 +#define NPCX_DEVALTF_ADC6_SL 1 +#define NPCX_DEVALTF_ADC7_SL 2 +#define NPCX_DEVALTF_ADC8_SL 3 +#define NPCX_DEVALTF_ADC9_SL 4 /* pin-mux for PSL */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_DEVALTD_PSL_IN1_AHI 0 -#define NPCX_DEVALTD_NPSL_IN1_SL 1 -#define NPCX_DEVALTD_PSL_IN2_AHI 2 -#define NPCX_DEVALTD_NPSL_IN2_SL 3 -#define NPCX_DEVALTD_PSL_IN3_AHI 4 -#define NPCX_DEVALTD_PSL_IN3_SL 5 -#define NPCX_DEVALTD_PSL_IN4_AHI 6 -#define NPCX_DEVALTD_PSL_IN4_SL 7 +#define NPCX_DEVALTD_PSL_IN1_AHI 0 +#define NPCX_DEVALTD_NPSL_IN1_SL 1 +#define NPCX_DEVALTD_PSL_IN2_AHI 2 +#define NPCX_DEVALTD_NPSL_IN2_SL 3 +#define NPCX_DEVALTD_PSL_IN3_AHI 4 +#define NPCX_DEVALTD_PSL_IN3_SL 5 +#define NPCX_DEVALTD_PSL_IN4_AHI 6 +#define NPCX_DEVALTD_PSL_IN4_SL 7 #endif #ifdef CHIP_VARIANT_NPCX7M6G /* External 32KHz crytal osc. input support */ -#define NPCX_DEVALTA_32KCLKIN_SL 3 +#define NPCX_DEVALTA_32KCLKIN_SL 3 #endif /* pin-mux for UART */ -#define NPCX_DEVALTA_UART_SL1 7 -#define NPCX_DEVALTC_UART_SL2 0 +#define NPCX_DEVALTA_UART_SL1 7 +#define NPCX_DEVALTC_UART_SL2 0 #ifdef NPCX_SECOND_UART /* Secondary UART selection */ -#define NPCX_DEVALTA_UART2_SL 5 +#define NPCX_DEVALTA_UART2_SL 5 #endif /* SHI module version 2 enable bit */ -#define NPCX_DEVALTF_SHI_NEW 7 +#define NPCX_DEVALTF_SHI_NEW 7 #ifdef NPCX_WOV_SUPPORT /* pin-mux for WoV */ -#define NPCX_DEVALTE_WOV_SL 0 -#define NPCX_DEVALTE_I2S_SL 1 -#define NPCX_DEVALTE_DMCLK_FAST 2 +#define NPCX_DEVALTE_WOV_SL 0 +#define NPCX_DEVALTE_I2S_SL 1 +#define NPCX_DEVALTE_DMCLK_FAST 2 #endif /* SMBus register fields */ -#define NPCX_SMBSEL_SMB4SEL 4 -#define NPCX_SMBSEL_SMB5SEL 5 -#define NPCX_SMBSEL_SMB6SEL 6 +#define NPCX_SMBSEL_SMB4SEL 4 +#define NPCX_SMBSEL_SMB5SEL 5 +#define NPCX_SMBSEL_SMB6SEL 6 /* SMB enumeration: I2C port definitions */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ - NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ - NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ + NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ + NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ #ifdef CHIP_VARIANT_NPCX7M6G - NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */ + NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */ #endif - NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ - NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ - NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ - NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ - NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ - NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ + NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ + NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ + NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ + NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ + NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ + NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ NPCX_I2C_COUNT, }; /* Power Management Controller (PMC) Registers */ -#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) -#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) +#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) /* PMC register fields */ -#define NPCX_PWDWN_CTL3_SMB4_PD 4 -#define NPCX_PWDWN_CTL7_SMB5_PD 0 -#define NPCX_PWDWN_CTL7_SMB6_PD 1 -#define NPCX_PWDWN_CTL7_SMB7_PD 2 +#define NPCX_PWDWN_CTL3_SMB4_PD 4 +#define NPCX_PWDWN_CTL7_SMB5_PD 0 +#define NPCX_PWDWN_CTL7_SMB6_PD 1 +#define NPCX_PWDWN_CTL7_SMB7_PD 2 #ifdef NPCX_ITIM64_SUPPORT -#define NPCX_PWDWN_CTL7_ITIM64_PD 5 +#define NPCX_PWDWN_CTL7_ITIM64_PD 5 #endif #ifdef NPCX_SECOND_UART -#define NPCX_PWDWN_CTL7_UART2_PD 6 +#define NPCX_PWDWN_CTL7_UART2_PD 6 #endif #ifdef NPCX_WOV_SUPPORT -#define NPCX_PWDWN_CTL7_WOV_PD 7 +#define NPCX_PWDWN_CTL7_WOV_PD 7 #endif /* @@ -328,7 +326,7 @@ enum { CGC_OFFSET_UART2 = 6, #endif #ifdef NPCX_WOV_SUPPORT - CGC_OFFSET_WOV = 6, + CGC_OFFSET_WOV = 6, #endif }; @@ -343,53 +341,52 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB7_PD)) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB4_PD)) +#define CGC_I2C_MASK2 \ + (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB7_PD)) #ifdef NPCX_SECOND_UART -#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) +#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) #endif #ifdef NPCX_WOV_SUPPORT -#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) +#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) #endif /* BBRAM register fields */ -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) -#define NPCX_BKUP_STS_VSBY_STS 1 -#define NPCX_BKUP_STS_VCC1_STS 0 -#define NPCX_BKUP_STS_ALL_MASK \ +#define NPCX_BKUP_STS_VSBY_STS 1 +#define NPCX_BKUP_STS_VCC1_STS 0 +#define NPCX_BKUP_STS_ALL_MASK \ (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ - BIT(NPCX_BKUP_STS_VCC1_STS)) -#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ + BIT(NPCX_BKUP_STS_VCC1_STS)) +#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ #else #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) -#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ +#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ #endif /* ITIM16 registers */ -#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) -#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) +#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) +#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) /* ITIM32 registers */ -#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) +#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT16 +#define NPCX_ITCNT NPCX_ITCNT16 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM16_1 +#define ITIM_EVENT_NO ITIM16_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM16_5 +#define ITIM_WDG_NO ITIM16_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32 +#define ITIM_SYSTEM_NO ITIM32 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -404,56 +401,56 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */ -#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) -#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) -#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) -#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) -#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) +#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) +#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) +#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) +#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) +#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) /* SHI register fields */ -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 /* eSPI register fields */ -#define NPCX_ESPIIE_BMTXDONEIE 19 -#define NPCX_ESPIIE_PBMRXIE 20 -#define NPCX_ESPIIE_PMSGRXIE 21 -#define NPCX_ESPIIE_BMBURSTERRIE 22 -#define NPCX_ESPIIE_BMBURSTDONEIE 23 - -#define NPCX_ESPIWE_PBMRXWE 20 -#define NPCX_ESPIWE_PMSGRXWE 21 - -#define NPCX_ESPISTS_VWUPDW 17 -#define NPCX_ESPISTS_BMTXDONE 19 -#define NPCX_ESPISTS_PBMRX 20 -#define NPCX_ESPISTS_PMSGRX 21 -#define NPCX_ESPISTS_BMBURSTERR 22 -#define NPCX_ESPISTS_BMBURSTDONE 23 -#define NPCX_ESPISTS_ESPIRST_LVL 24 - -#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) - -#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) +#define NPCX_ESPIIE_BMTXDONEIE 19 +#define NPCX_ESPIIE_PBMRXIE 20 +#define NPCX_ESPIIE_PMSGRXIE 21 +#define NPCX_ESPIIE_BMBURSTERRIE 22 +#define NPCX_ESPIIE_BMBURSTDONEIE 23 + +#define NPCX_ESPIWE_PBMRXWE 20 +#define NPCX_ESPIWE_PMSGRXWE 21 + +#define NPCX_ESPISTS_VWUPDW 17 +#define NPCX_ESPISTS_BMTXDONE 19 +#define NPCX_ESPISTS_PBMRX 20 +#define NPCX_ESPISTS_PMSGRX 21 +#define NPCX_ESPISTS_BMBURSTERR 22 +#define NPCX_ESPISTS_BMBURSTDONE 23 +#define NPCX_ESPISTS_ESPIRST_LVL 24 + +#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) +#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) +#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) +#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) +#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) + +#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) +#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_WK_EN(e) (((e)<<20) & 0x00100000) -#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) +#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000) +#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) /* eSPI max supported frequency */ enum { @@ -466,41 +463,41 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #endif /* UART registers */ -#define NPCX_UART_WK_GROUP MIWU_GROUP_8 -#define NPCX_UART_WK_BIT 7 +#define NPCX_UART_WK_GROUP MIWU_GROUP_8 +#define NPCX_UART_WK_BIT 7 #ifdef NPCX_SECOND_UART -#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 -#define NPCX_UART2_WK_BIT 6 +#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 +#define NPCX_UART2_WK_BIT 6 #endif /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0A + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0C + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1E + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKPND_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKPCL_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -508,64 +505,64 @@ enum { * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is * always 1 == MIWU_TABLE_1. */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 #endif /* NPCX_UART_MODULE2 */ /* ADC Registers */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n))) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n))) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n))) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* ADC register fields */ -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_THR_DCTL_THRD_EN 15 -#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH_CNT 3 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_THR_DCTL_THRD_EN 15 +#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH_CNT 3 -- cgit v1.2.1 From 7725784dbb6d6ab16873fc639d88d5c5d339d42a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:31 -0600 Subject: zephyr/projects/nissa/src/xivu/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf967e6ea2fe9e76f2e201e3631e8bac2b2ee4d1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730800 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/xivu/usbc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/nissa/src/xivu/usbc.c b/zephyr/projects/nissa/src/xivu/usbc.c index 32a390e502..dcf613bd4b 100644 --- a/zephyr/projects/nissa/src/xivu/usbc.c +++ b/zephyr/projects/nissa/src/xivu/usbc.c @@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port) usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); } -static inline void poll_usb_gpio(int port, - const struct gpio_dt_spec *gpio, +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, const struct deferred_data *ud) { if (!gpio_pin_get_dt(gpio)) { @@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port, } } -static void poll_c0_int (void) +static void poll_c0_int(void) { - poll_usb_gpio(0, - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), &poll_c0_int_data); } -static void poll_c1_int (void) +static void poll_c1_int(void) { - poll_usb_gpio(1, - GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), &poll_c1_int_data); } -- cgit v1.2.1 From 969d2637f36ef19aa2752e46de4b3fa49f5c6e6c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:47 -0600 Subject: chip/stm32/spi_controller.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15f508bc194f4b0a7454f1aa053c440db1a22d74 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729412 Reviewed-by: Jeremy Bettis --- chip/stm32/spi_controller.c | 80 +++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 47 deletions(-) diff --git a/chip/stm32/spi_controller.c b/chip/stm32/spi_controller.c index 8e5b01d621..7d8ddd7e5c 100644 --- a/chip/stm32/spi_controller.c +++ b/chip/stm32/spi_controller.c @@ -17,13 +17,11 @@ #include "timer.h" #include "util.h" -#if defined(CHIP_VARIANT_STM32F373) || \ - defined(CHIP_FAMILY_STM32L4) || \ - defined(CHIP_FAMILY_STM32L5) || \ - defined(CHIP_VARIANT_STM32F76X) +#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_FAMILY_STM32L5) || defined(CHIP_VARIANT_STM32F76X) #define HAS_SPI3 #else -#undef HAS_SPI3 +#undef HAS_SPI3 #endif /* The second (and third if available) SPI port are used as controller */ @@ -66,52 +64,40 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; /* Default DMA channel options */ #ifdef CHIP_FAMILY_STM32F4 -#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) +#define F4_CHANNEL(ch) STM32_DMA_CCR_CHANNEL(ch) #else -#define F4_CHANNEL(ch) 0 +#define F4_CHANNEL(ch) 0 #endif static const struct dma_option dma_tx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_TX_REQ_CH) - }, + { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI1_TX_REQ_CH) }, #endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_TX_REQ_CH) - }, + { STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI2_TX_REQ_CH) }, #ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_TX_REQ_CH) - }, + { STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI3_TX_REQ_CH) }, #endif }; static const struct dma_option dma_rx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI1_RX_REQ_CH) - }, + { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI1_RX_REQ_CH) }, #endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI2_RX_REQ_CH) - }, + { STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI2_RX_REQ_CH) }, #ifdef HAS_SPI3 - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - | F4_CHANNEL(STM32_SPI3_RX_REQ_CH) - }, + { STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | + F4_CHANNEL(STM32_SPI3_RX_REQ_CH) }, #endif }; @@ -134,7 +120,7 @@ static int spi_clear_rx_fifo(stm32_spi_regs_t *spi) uint32_t start = __hw_clock_source_read(), delta; while (!spi_rx_done(spi)) { - unused = spi->dr; /* Read one byte from FIFO */ + unused = spi->dr; /* Read one byte from FIFO */ delta = __hw_clock_source_read() - start; if (delta >= SPI_TRANSACTION_TIMEOUT_USEC) return EC_ERROR_TIMEOUT; @@ -232,7 +218,7 @@ static int spi_controller_initialize(const struct spi_device_t *spi_device) * https://www.st.com/resource/en/reference_manual/dm00031936.pdf#page=803 */ spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN | - STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); + STM32_SPI_CR2_FRXTH | STM32_SPI_CR2_DATASIZE(8); #ifdef CONFIG_SPI_HALFDUPLEX spi->cr1 |= STM32_SPI_CR1_BIDIMODE | STM32_SPI_CR1_BIDIOE; @@ -287,8 +273,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable) return spi_controller_shutdown(spi_device); } -static int spi_dma_start(int port, const uint8_t *txdata, - uint8_t *rxdata, int len) +static int spi_dma_start(int port, const uint8_t *txdata, uint8_t *rxdata, + int len) { dma_chan_t *txdma; @@ -350,8 +336,8 @@ static int spi_dma_wait(int port) static uint8_t spi_chip_select_already_asserted[ARRAY_SIZE(SPI_REGS)]; int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv = EC_SUCCESS; int port = spi_device->port; @@ -424,8 +410,8 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) { int rv = spi_dma_wait(spi_device->port); - if (!IS_ENABLED(CONFIG_USB_SPI) - || !spi_chip_select_already_asserted[spi_device->port]) { + if (!IS_ENABLED(CONFIG_USB_SPI) || + !spi_chip_select_already_asserted[spi_device->port]) { /* Drive SS high */ gpio_set_level(spi_device->gpio_cs, 1); } @@ -439,8 +425,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv; int port = spi_device->port; -- cgit v1.2.1 From 44eff719e34eb997b57bdd7b96e8526dca53046e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:57 -0600 Subject: board/sweetberry/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4264a3e54de707946ce5062fc167401f4cb57eba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728975 Reviewed-by: Jeremy Bettis --- board/sweetberry/board.c | 109 ++++++++++++++++++++++------------------------- 1 file changed, 52 insertions(+), 57 deletions(-) diff --git a/board/sweetberry/board.c b/board/sweetberry/board.c index bee8f91a22..64a70c52a3 100644 --- a/board/sweetberry/board.c +++ b/board/sweetberry/board.c @@ -28,14 +28,14 @@ * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Sweetberry"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Sweetberry EC Shell"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Sweetberry"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Sweetberry EC Shell"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -59,48 +59,43 @@ struct dwc_usb usb_ctl = { /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "i2c1", - .port = I2C_PORT_0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "i2c2", - .port = I2C_PORT_1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "i2c3", - .port = I2C_PORT_2, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "fmpi2c4", - .port = FMPI2C_PORT_3, - .kbps = 900, - .scl = GPIO_FMPI2C_SCL, - .sda = GPIO_FMPI2C_SDA - }, + { .name = "i2c1", + .port = I2C_PORT_0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "i2c2", + .port = I2C_PORT_1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "i2c3", + .port = I2C_PORT_2, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "fmpi2c4", + .port = FMPI2C_PORT_3, + .kbps = 900, + .scl = GPIO_FMPI2C_SCL, + .sda = GPIO_FMPI2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} -#define GPIO_SET_HS(bank, number) \ - (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2))) +#define GPIO_SET_HS(bank, number) \ + (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2))) void board_config_post_gpio_init(void) { /* We use MCO2 clock passthrough to provide a clock to USB HS */ gpio_config_module(MODULE_MCO, 1); /* GPIO PC9 to high speed */ - GPIO_SET_HS(C, 9); + GPIO_SET_HS(C, 9); if (usb_ctl.phy_type == USB_PHY_ULPI) gpio_set_level(GPIO_USB_MUX_SEL, 0); @@ -111,29 +106,29 @@ void board_config_post_gpio_init(void) GPIO_SET_HS(A, 11); GPIO_SET_HS(A, 12); - GPIO_SET_HS(C, 3); - GPIO_SET_HS(C, 2); - GPIO_SET_HS(C, 0); - GPIO_SET_HS(A, 5); + GPIO_SET_HS(C, 3); + GPIO_SET_HS(C, 2); + GPIO_SET_HS(C, 0); + GPIO_SET_HS(A, 5); - GPIO_SET_HS(B, 5); + GPIO_SET_HS(B, 5); GPIO_SET_HS(B, 13); GPIO_SET_HS(B, 12); - GPIO_SET_HS(B, 2); + GPIO_SET_HS(B, 2); GPIO_SET_HS(B, 10); - GPIO_SET_HS(B, 1); - GPIO_SET_HS(B, 0); - GPIO_SET_HS(A, 3); + GPIO_SET_HS(B, 1); + GPIO_SET_HS(B, 0); + GPIO_SET_HS(A, 3); /* Set I2C GPIO to HS */ - GPIO_SET_HS(B, 6); - GPIO_SET_HS(B, 7); - GPIO_SET_HS(F, 1); - GPIO_SET_HS(F, 0); - GPIO_SET_HS(A, 8); - GPIO_SET_HS(B, 4); - GPIO_SET_HS(C, 6); - GPIO_SET_HS(C, 7); + GPIO_SET_HS(B, 6); + GPIO_SET_HS(B, 7); + GPIO_SET_HS(F, 1); + GPIO_SET_HS(F, 0); + GPIO_SET_HS(A, 8); + GPIO_SET_HS(B, 4); + GPIO_SET_HS(C, 6); + GPIO_SET_HS(C, 7); } static void board_init(void) -- cgit v1.2.1 From 58e912236ec8ccd95a7d66b9cdb75206e1c5370a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:15 -0600 Subject: board/redrix/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife2769dd0d6c6c3a7ec0dae06fd54ec1c36efaa1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728881 Reviewed-by: Jeremy Bettis --- board/redrix/thermal.c | 113 ++++++++++++++++++++++++------------------------- 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/board/redrix/thermal.c b/board/redrix/thermal.c index 71902a5430..4dfbcf9c86 100644 --- a/board/redrix/thermal.c +++ b/board/redrix/thermal.c @@ -16,7 +16,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -40,97 +40,96 @@ static const struct fan_step *fan_step_table; static const struct fan_step fan_table_clamshell[] = { { /* level 0 */ - .on = {53, 53, 0, -1}, - .off = {99, 99, 99, -1}, - .rpm = {0, 0}, + .on = { 53, 53, 0, -1 }, + .off = { 99, 99, 99, -1 }, + .rpm = { 0, 0 }, }, { /* level 1 */ - .on = {54, 54, 0, -1}, - .off = {53, 53, 99, -1}, - .rpm = {3900, 4300}, + .on = { 54, 54, 0, -1 }, + .off = { 53, 53, 99, -1 }, + .rpm = { 3900, 4300 }, }, { /* level 2 */ - .on = {55, 55, 0, -1}, - .off = {54, 54, 99, -1}, - .rpm = {4800, 5200}, + .on = { 55, 55, 0, -1 }, + .off = { 54, 54, 99, -1 }, + .rpm = { 4800, 5200 }, }, { /* level 3 */ - .on = {56, 56, 0, -1}, - .off = {54, 55, 99, -1}, - .rpm = {5000, 5500}, + .on = { 56, 56, 0, -1 }, + .off = { 54, 55, 99, -1 }, + .rpm = { 5000, 5500 }, }, { /* level 4 */ - .on = {57, 57, 61, -1}, - .off = {56, 56, 59, -1}, - .rpm = {5200, 5700}, + .on = { 57, 57, 61, -1 }, + .off = { 56, 56, 59, -1 }, + .rpm = { 5200, 5700 }, }, { /* level 5 */ - .on = {58, 58, 63, -1}, - .off = {57, 57, 61, -1}, - .rpm = {5700, 6200}, + .on = { 58, 58, 63, -1 }, + .off = { 57, 57, 61, -1 }, + .rpm = { 5700, 6200 }, }, { /* level 6 */ - .on = {100, 100, 100, -1}, - .off = {58, 58, 63, -1}, - .rpm = {6200, 6400}, + .on = { 100, 100, 100, -1 }, + .off = { 58, 58, 63, -1 }, + .rpm = { 6200, 6400 }, }, }; static const struct fan_step fan_table_tablet[] = { { /* level 0 */ - .on = {52, 55, 0, -1}, - .off = {99, 99, 99, -1}, - .rpm = {0, 0}, + .on = { 52, 55, 0, -1 }, + .off = { 99, 99, 99, -1 }, + .rpm = { 0, 0 }, }, { /* level 1 */ - .on = {53, 56, 0, -1}, - .off = {52, 55, 99, -1}, - .rpm = {4100, 4200}, + .on = { 53, 56, 0, -1 }, + .off = { 52, 55, 99, -1 }, + .rpm = { 4100, 4200 }, }, { /* level 2 */ - .on = {54, 57, 0, -1}, - .off = {53, 56, 99, -1}, - .rpm = {4500, 4800}, + .on = { 54, 57, 0, -1 }, + .off = { 53, 56, 99, -1 }, + .rpm = { 4500, 4800 }, }, { /* level 3 */ - .on = {55, 58, 0, -1}, - .off = {54, 57, 99, -1}, - .rpm = {4800, 5200}, + .on = { 55, 58, 0, -1 }, + .off = { 54, 57, 99, -1 }, + .rpm = { 4800, 5200 }, }, { /* level 4 */ - .on = {56, 59, 61, -1}, - .off = {55, 58, 59, -1}, - .rpm = {5100, 5400}, + .on = { 56, 59, 61, -1 }, + .off = { 55, 58, 59, -1 }, + .rpm = { 5100, 5400 }, }, { /* level 5 */ - .on = {57, 60, 63, -1}, - .off = {56, 59, 61, -1}, - .rpm = {5500, 5800}, + .on = { 57, 60, 63, -1 }, + .off = { 56, 59, 61, -1 }, + .rpm = { 5500, 5800 }, }, { /* level 6 */ - .on = {100, 100, 100, -1}, - .off = {57, 60, 63, -1}, - .rpm = {6000, 6200}, + .on = { 100, 100, 100, -1 }, + .off = { 57, 60, 63, -1 }, + .rpm = { 6000, 6200 }, }, }; #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell) -BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == - ARRAY_SIZE(fan_table_tablet)); +BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet)); int fan_table_to_rpm(int fan, int *temp) { @@ -156,11 +155,12 @@ int fan_table_to_rpm(int fan, int *temp) temp[TEMP_SENSOR_3_CHARGER] < prev_tmp[TEMP_SENSOR_3_CHARGER]) { for (i = current_level; i > 0; i--) { if (temp[TEMP_SENSOR_1_DDR] < - fan_step_table[i].off[TEMP_SENSOR_1_DDR] && + fan_step_table[i].off[TEMP_SENSOR_1_DDR] && temp[TEMP_SENSOR_3_CHARGER] < - fan_step_table[i].off[TEMP_SENSOR_3_CHARGER] && + fan_step_table[i] + .off[TEMP_SENSOR_3_CHARGER] && temp[TEMP_SENSOR_2_SOC] < - fan_step_table[i].off[TEMP_SENSOR_2_SOC]) + fan_step_table[i].off[TEMP_SENSOR_2_SOC]) current_level = i - 1; else break; @@ -168,14 +168,15 @@ int fan_table_to_rpm(int fan, int *temp) } else if (temp[TEMP_SENSOR_1_DDR] > prev_tmp[TEMP_SENSOR_1_DDR] || temp[TEMP_SENSOR_2_SOC] > prev_tmp[TEMP_SENSOR_2_SOC] || temp[TEMP_SENSOR_3_CHARGER] > - prev_tmp[TEMP_SENSOR_3_CHARGER]) { + prev_tmp[TEMP_SENSOR_3_CHARGER]) { for (i = current_level; i < NUM_FAN_LEVELS; i++) { if ((temp[TEMP_SENSOR_1_DDR] > - fan_step_table[i].on[TEMP_SENSOR_1_DDR] && - temp[TEMP_SENSOR_3_CHARGER] > - fan_step_table[i].on[TEMP_SENSOR_3_CHARGER]) || + fan_step_table[i].on[TEMP_SENSOR_1_DDR] && + temp[TEMP_SENSOR_3_CHARGER] > + fan_step_table[i] + .on[TEMP_SENSOR_3_CHARGER]) || temp[TEMP_SENSOR_2_SOC] > - fan_step_table[i].on[TEMP_SENSOR_2_SOC]) + fan_step_table[i].on[TEMP_SENSOR_2_SOC]) current_level = i + 1; else break; @@ -206,10 +207,8 @@ int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } -- cgit v1.2.1 From 33ec91cfc8e247735624f368c71df13026001511 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:50 -0600 Subject: core/riscv-rv32i/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4dacb0ef9a14fe10ba30649f181f62cc3d58672b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729871 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/irq_handler.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/core/riscv-rv32i/irq_handler.h b/core/riscv-rv32i/irq_handler.h index 6fe7769684..30d3b787b8 100644 --- a/core/riscv-rv32i/irq_handler.h +++ b/core/riscv-rv32i/irq_handler.h @@ -20,12 +20,12 @@ * Macro to connect the interrupt handler "routine" to the irq number "irq" and * ensure it is enabled in the interrupt controller with the right priority. */ -#define DECLARE_IRQ(irq, routine, priority) \ - static void __keep routine(void); \ - void IRQ_HANDLER(CPU_INT(irq))(void) \ - __attribute__ ((alias(STRINGIFY(routine)))); \ - const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ - __attribute__((section(".rodata.irqprio"))) \ - = {CPU_INT(irq), priority} +#define DECLARE_IRQ(irq, routine, priority) \ + static void __keep routine(void); \ + void IRQ_HANDLER(CPU_INT(irq))(void) \ + __attribute__((alias(STRINGIFY(routine)))); \ + const struct irq_priority __keep IRQ_PRIORITY(CPU_INT(irq)) \ + __attribute__((section(".rodata.irqprio"))) = { CPU_INT(irq), \ + priority } -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From 94b7594e3ae289ff5ac9a3d969dd3e76da4e4cd3 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 30 Jun 2022 11:29:00 -0600 Subject: gitlab: Remove native_posix build The posix-ec project was renamed, and it was really only a sample, so just remove it from here. The target zephyr_boards_coverage will still build it, so we're not really losing anything by removing it. BUG=b:237431976 BRANCH=none TEST=None Signed-off-by: Jeremy Bettis Change-Id: If7d006885b38fec97bd234bcb4b250bf74e4c6c4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3736985 Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jack Rosenthal Auto-Submit: Jeremy Bettis --- .gitlab-ci.yml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 069ffca1f5..a3f8c4cfbc 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -191,12 +191,6 @@ lazor: PROJECT: "lazor" <<: *build_template -native_posix: - variables: - PROJECT: "posix-ec" - TOOLCHAIN: "host" - <<: *build_template - npcx7_evb: variables: PROJECT: "npcx7" -- cgit v1.2.1 From 72a8e1478021ec63c71c26c15a299bd558676916 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:13 -0600 Subject: chip/ish/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2cbc5863ff572bbdc1225a5422fe44f689b0b95a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729187 Reviewed-by: Jeremy Bettis --- chip/ish/registers.h | 666 +++++++++++++++++++++++++-------------------------- 1 file changed, 333 insertions(+), 333 deletions(-) diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 08f1ce6ea3..d50987b5c3 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -19,99 +19,99 @@ * ISH3.0 has 3 controllers. Locking must occur by-controller (not by-port). */ enum ish_i2c_port { - ISH_I2C0 = 0, /* Controller 0 */ - ISH_I2C1 = 1, /* Controller 1 */ - ISH_I2C2 = 2, /* Controller 2 */ + ISH_I2C0 = 0, /* Controller 0 */ + ISH_I2C1 = 1, /* Controller 1 */ + ISH_I2C2 = 2, /* Controller 2 */ I2C_PORT_COUNT, }; #endif -#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT +#define ISH_I2C_PORT_COUNT I2C_PORT_COUNT /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit * linear address space. */ #ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_BASE 0x00000000 -#define ISH_I2C1_BASE 0x00002000 -#define ISH_I2C2_BASE 0x00004000 -#define ISH_UART_BASE 0x08100000 -#define ISH_GPIO_BASE 0x00100000 -#define ISH_PMU_BASE 0x04200000 -#define ISH_OCP_BASE 0xFFFFFFFF -#define ISH_MISC_BASE 0x04400000 -#define ISH_DMA_BASE 0x10100000 -#define ISH_CCU_BASE 0x04300000 -#define ISH_IPC_BASE 0x04100000 -#define ISH_WDT_BASE 0x04900000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0x04700000 -#define ISH_LAPIC_BASE 0xFEE00000 +#define ISH_I2C0_BASE 0x00000000 +#define ISH_I2C1_BASE 0x00002000 +#define ISH_I2C2_BASE 0x00004000 +#define ISH_UART_BASE 0x08100000 +#define ISH_GPIO_BASE 0x00100000 +#define ISH_PMU_BASE 0x04200000 +#define ISH_OCP_BASE 0xFFFFFFFF +#define ISH_MISC_BASE 0x04400000 +#define ISH_DMA_BASE 0x10100000 +#define ISH_CCU_BASE 0x04300000 +#define ISH_IPC_BASE 0x04100000 +#define ISH_WDT_BASE 0x04900000 +#define ISH_IOAPIC_BASE 0xFEC00000 +#define ISH_HPET_BASE 0x04700000 +#define ISH_LAPIC_BASE 0xFEE00000 #else -#define ISH_I2C0_BASE 0x00100000 -#define ISH_I2C1_BASE 0x00102000 -#define ISH_I2C2_BASE 0x00105000 -#define ISH_UART_BASE 0x00103000 -#define ISH_GPIO_BASE 0x001F0000 -#define ISH_PMU_BASE 0x00800000 -#define ISH_OCP_BASE 0x00700000 -#define ISH_MISC_BASE 0x00C00000 -#define ISH_DMA_BASE 0x00400000 -#define ISH_CCU_BASE 0x00900000 -#define ISH_IPC_BASE 0x00B00000 -#define ISH_WDT_BASE 0xFDE00000 -#define ISH_IOAPIC_BASE 0xFEC00000 -#define ISH_HPET_BASE 0xFED00000 -#define ISH_LAPIC_BASE 0xFEE00000 +#define ISH_I2C0_BASE 0x00100000 +#define ISH_I2C1_BASE 0x00102000 +#define ISH_I2C2_BASE 0x00105000 +#define ISH_UART_BASE 0x00103000 +#define ISH_GPIO_BASE 0x001F0000 +#define ISH_PMU_BASE 0x00800000 +#define ISH_OCP_BASE 0x00700000 +#define ISH_MISC_BASE 0x00C00000 +#define ISH_DMA_BASE 0x00400000 +#define ISH_CCU_BASE 0x00900000 +#define ISH_IPC_BASE 0x00B00000 +#define ISH_WDT_BASE 0xFDE00000 +#define ISH_IOAPIC_BASE 0xFEC00000 +#define ISH_HPET_BASE 0xFED00000 +#define ISH_LAPIC_BASE 0xFEE00000 #endif /* HW interrupt pins mapped to IOAPIC, from I/O sources */ #ifdef CHIP_VARIANT_ISH5P4 -#define ISH_I2C0_IRQ 15 -#define ISH_I2C1_IRQ 16 -#define ISH_FABRIC_IRQ 12 -#define ISH_I2C2_IRQ 17 -#define ISH_WDT_IRQ 26 -#define ISH_GPIO_IRQ 13 -#define ISH_HPET_TIMER1_IRQ 14 -#define ISH_IPC_HOST2ISH_IRQ 0 -#define ISH_PMU_WAKEUP_IRQ 10 -#define ISH_D3_RISE_IRQ 9 -#define ISH_D3_FALL_IRQ 9 -#define ISH_BME_RISE_IRQ 9 -#define ISH_BME_FALL_IRQ 9 -#define ISH_IPC_ISH2HOST_CLR_IRQ 0 -#define ISH_UART0_IRQ 23 -#define ISH_UART1_IRQ 24 -#define ISH_RESET_PREP_IRQ 6 +#define ISH_I2C0_IRQ 15 +#define ISH_I2C1_IRQ 16 +#define ISH_FABRIC_IRQ 12 +#define ISH_I2C2_IRQ 17 +#define ISH_WDT_IRQ 26 +#define ISH_GPIO_IRQ 13 +#define ISH_HPET_TIMER1_IRQ 14 +#define ISH_IPC_HOST2ISH_IRQ 0 +#define ISH_PMU_WAKEUP_IRQ 10 +#define ISH_D3_RISE_IRQ 9 +#define ISH_D3_FALL_IRQ 9 +#define ISH_BME_RISE_IRQ 9 +#define ISH_BME_FALL_IRQ 9 +#define ISH_IPC_ISH2HOST_CLR_IRQ 0 +#define ISH_UART0_IRQ 23 +#define ISH_UART1_IRQ 24 +#define ISH_RESET_PREP_IRQ 6 #else -#define ISH_I2C0_IRQ 0 -#define ISH_I2C1_IRQ 1 -#define ISH_FABRIC_IRQ 5 -#define ISH_I2C2_IRQ 40 -#define ISH_WDT_IRQ 6 -#define ISH_GPIO_IRQ 7 -#define ISH_HPET_TIMER1_IRQ 8 -#define ISH_IPC_HOST2ISH_IRQ 12 -#define ISH_PMU_WAKEUP_IRQ 18 -#define ISH_D3_RISE_IRQ 19 -#define ISH_D3_FALL_IRQ 29 -#define ISH_BME_RISE_IRQ 50 -#define ISH_BME_FALL_IRQ 51 -#define ISH_IPC_ISH2HOST_CLR_IRQ 24 -#define ISH_UART0_IRQ 34 -#define ISH_UART1_IRQ 35 -#define ISH_RESET_PREP_IRQ 62 +#define ISH_I2C0_IRQ 0 +#define ISH_I2C1_IRQ 1 +#define ISH_FABRIC_IRQ 5 +#define ISH_I2C2_IRQ 40 +#define ISH_WDT_IRQ 6 +#define ISH_GPIO_IRQ 7 +#define ISH_HPET_TIMER1_IRQ 8 +#define ISH_IPC_HOST2ISH_IRQ 12 +#define ISH_PMU_WAKEUP_IRQ 18 +#define ISH_D3_RISE_IRQ 19 +#define ISH_D3_FALL_IRQ 29 +#define ISH_BME_RISE_IRQ 50 +#define ISH_BME_FALL_IRQ 51 +#define ISH_IPC_ISH2HOST_CLR_IRQ 24 +#define ISH_UART0_IRQ 34 +#define ISH_UART1_IRQ 35 +#define ISH_RESET_PREP_IRQ 62 #endif /* Interrupt vectors 0-31 are architecture reserved. * Vectors 32-255 are user-defined. */ -#define USER_VEC_START 32 +#define USER_VEC_START 32 /* Map IRQs to vectors after offset 10 for certain APIC interrupts */ -#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) -#define VEC_TO_IRQ(vec) ((vec) - USER_VEC_START - 10) +#define IRQ_TO_VEC(irq) ((irq) + USER_VEC_START + 10) +#define VEC_TO_IRQ(vec) ((vec)-USER_VEC_START - 10) /* ISH GPIO Registers */ #define ISH_GPIO_GCCR REG32(ISH_GPIO_BASE + 0x000) /* Direction lock */ @@ -129,322 +129,322 @@ enum ish_i2c_port { #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */ /* APIC interrupt vectors */ -#define ISH_TS_VECTOR 0x20 /* Task switch vector */ -#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ -#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */ -#define LAPIC_SPURIOUS_INT_VECTOR 0xff +#define ISH_TS_VECTOR 0x20 /* Task switch vector */ +#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ +#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */ +#define LAPIC_SPURIOUS_INT_VECTOR 0xff /* Interrupt to vector mapping. To be programmed into IOAPIC */ -#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ) -#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ) -#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ) -#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ) -#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ) -#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ) -#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ) -#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) -#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) -#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) -#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) -#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ) -#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ) -#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ) -#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ) -#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ) -#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ) - -#define ISH_DEBUG_UART UART_PORT_0 -#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ -#define ISH_DEBUG_UART_VEC ISH_UART0_VEC +#define ISH_I2C0_VEC IRQ_TO_VEC(ISH_I2C0_IRQ) +#define ISH_I2C1_VEC IRQ_TO_VEC(ISH_I2C1_IRQ) +#define ISH_I2C2_VEC IRQ_TO_VEC(ISH_I2C2_IRQ) +#define ISH_WDT_VEC IRQ_TO_VEC(ISH_WDT_IRQ) +#define ISH_GPIO_VEC IRQ_TO_VEC(ISH_GPIO_IRQ) +#define ISH_HPET_TIMER1_VEC IRQ_TO_VEC(ISH_HPET_TIMER1_IRQ) +#define ISH_IPC_ISH2HOST_CLR_VEC IRQ_TO_VEC(ISH_IPC_ISH2HOST_CLR_IRQ) +#define ISH_UART0_VEC IRQ_TO_VEC(ISH_UART0_IRQ) +#define ISH_UART1_VEC IRQ_TO_VEC(ISH_UART1_IRQ) +#define ISH_IPC_VEC IRQ_TO_VEC(ISH_IPC_HOST2ISH_IRQ) +#define ISH_RESET_PREP_VEC IRQ_TO_VEC(ISH_RESET_PREP_IRQ) +#define ISH_PMU_WAKEUP_VEC IRQ_TO_VEC(ISH_PMU_WAKEUP_IRQ) +#define ISH_D3_RISE_VEC IRQ_TO_VEC(ISH_D3_RISE_IRQ) +#define ISH_D3_FALL_VEC IRQ_TO_VEC(ISH_D3_FALL_IRQ) +#define ISH_BME_RISE_VEC IRQ_TO_VEC(ISH_BME_RISE_IRQ) +#define ISH_BME_FALL_VEC IRQ_TO_VEC(ISH_BME_FALL_IRQ) +#define ISH_FABRIC_VEC IRQ_TO_VEC(ISH_FABRIC_IRQ) + +#define ISH_DEBUG_UART UART_PORT_0 +#define ISH_DEBUG_UART_IRQ ISH_UART0_IRQ +#define ISH_DEBUG_UART_VEC ISH_UART0_VEC /* IPC_Registers */ -#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) -#define IPC_PISR_HOST2ISH_BIT BIT(0) - -#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) -#define IPC_PIMR_HOST2ISH_BIT BIT(0) -#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) -#define IPC_PIMR_CSME_CSR_BIT BIT(23) -#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) -#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) -#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) -#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) -#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) -#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) -#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) -#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) -#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) -#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) -#define DMA_ENABLED_MASK BIT(0) -#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) -#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) - -#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) -#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) -#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) -#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) +#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) +#define IPC_PISR_HOST2ISH_BIT BIT(0) + +#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) +#define IPC_PIMR_HOST2ISH_BIT BIT(0) +#define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) +#define IPC_PIMR_CSME_CSR_BIT BIT(23) +#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) +#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) +#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) +#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) +#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) +#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) +#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) +#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) +#define DMA_ENABLED_MASK BIT(0) +#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) +#define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) + +#define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) +#define IPC_UMA_RANGE_LOWER_1 REG32(ISH_IPC_BASE + 0x384) +#define IPC_UMA_RANGE_UPPER_0 REG32(ISH_IPC_BASE + 0x388) +#define IPC_UMA_RANGE_UPPER_1 REG32(ISH_IPC_BASE + 0x38C) /* PMU Registers */ -#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) +#define PMU_SRAM_PG_EN REG32(ISH_PMU_BASE + 0x0) #ifndef CHIP_VARIANT_ISH5P4 -#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) -#define PMU_D3_BIT_SET BIT(0) -#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) -#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2) -#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3) -#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4) -#define PMU_BME_BIT_SET BIT(5) -#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6) +#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x4) +#define PMU_D3_BIT_SET BIT(0) +#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(1) +#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(2) +#define PMU_D3_BIT_RISING_EDGE_MASK BIT(3) +#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(4) +#define PMU_BME_BIT_SET BIT(5) +#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(6) #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(7) -#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) -#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) +#define PMU_BME_BIT_RISING_EDGE_MASK BIT(8) +#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(9) #else -#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00) -#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04) -#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08) -#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10) -#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20) -#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14) -#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) -#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) -#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) -#define PMU_HOST_RST_B BIT(0) -#define PMU_PCE_SHADOW_MASK 0x1F -#define PMU_PCE_PG_ALLOWED BIT(4) -#define PMU_PCE_CHANGE_MASK BIT(9) -#define PMU_PCE_CHANGE_DETECTED BIT(8) -#define PMU_PCE_PMCRE BIT(0) -#define PMU_SW_PG_REQ_B_VAL BIT(0) -#define PMU_SW_PG_REQ_B_RISE BIT(1) -#define PMU_SW_PG_REQ_B_FALL BIT(2) -#define PMU_PMC_PG_WAKE_VAL BIT(0) -#define PMU_PMC_PG_WAKE_RISE BIT(1) -#define PMU_PMC_PG_WAKE_FALL BIT(2) -#define PMU_PCE_PG_ALLOWED BIT(4) -#define PMU_D0I3_ENABLE_MASK BIT(23) -#define PMU_D3_BIT_SET BIT(16) -#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17) -#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18) -#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19) -#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20) -#define PMU_BME_BIT_SET BIT(24) -#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25) -#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) -#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) -#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) +#define PMU_STATUS_REG_ADDR (ISH_PMU_BASE + 0xF00) +#define PMU_SCRATCHPAD0_REG_ADDR (ISH_PMU_BASE + 0xF04) +#define PMU_SCRATCHPAD1_REG_ADDR (ISH_PMU_BASE + 0xF08) +#define PMU_PG_EN_REG_ADDR (ISH_PMU_BASE + 0xF10) +#define PMU_PMC_HOST_RST_CTL REG32(ISH_PMU_BASE + 0xF20) +#define PMU_SW_PG_REQ REG32(ISH_PMU_BASE + 0xF14) +#define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) +#define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) +#define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) +#define PMU_HOST_RST_B BIT(0) +#define PMU_PCE_SHADOW_MASK 0x1F +#define PMU_PCE_PG_ALLOWED BIT(4) +#define PMU_PCE_CHANGE_MASK BIT(9) +#define PMU_PCE_CHANGE_DETECTED BIT(8) +#define PMU_PCE_PMCRE BIT(0) +#define PMU_SW_PG_REQ_B_VAL BIT(0) +#define PMU_SW_PG_REQ_B_RISE BIT(1) +#define PMU_SW_PG_REQ_B_FALL BIT(2) +#define PMU_PMC_PG_WAKE_VAL BIT(0) +#define PMU_PMC_PG_WAKE_RISE BIT(1) +#define PMU_PMC_PG_WAKE_FALL BIT(2) +#define PMU_PCE_PG_ALLOWED BIT(4) +#define PMU_D0I3_ENABLE_MASK BIT(23) +#define PMU_D3_BIT_SET BIT(16) +#define PMU_D3_BIT_RISING_EDGE_STATUS BIT(17) +#define PMU_D3_BIT_FALLING_EDGE_STATUS BIT(18) +#define PMU_D3_BIT_RISING_EDGE_MASK BIT(19) +#define PMU_D3_BIT_FALLING_EDGE_MASK BIT(20) +#define PMU_BME_BIT_SET BIT(24) +#define PMU_BME_BIT_RISING_EDGE_STATUS BIT(25) +#define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) +#define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) +#define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) #endif -#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) -#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254) +#define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) +#define PMU_GPIO_WAKE_MASK1 REG32(ISH_PMU_BASE + 0x254) -#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18) +#define PMU_ISH_FABRIC_CNT REG32(ISH_PMU_BASE + 0x18) -#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54) +#define PMU_PGCB_CLKGATE_CTRL REG32(ISH_PMU_BASE + 0x54) -#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) -#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ +#define PMU_VNN_REQ REG32(ISH_PMU_BASE + 0x3c) +#define VNN_REQ_IPC_HOST_WRITE BIT(3) /* Power for IPC host write */ -#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) -#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ +#define PMU_VNN_REQ_ACK REG32(ISH_PMU_BASE + 0x40) +#define PMU_VNN_REQ_ACK_STATUS BIT(0) /* VNN req and ack status */ -#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58) +#define PMU_VNNAON_RED REG32(ISH_PMU_BASE + 0x58) -#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) -#define PMU_RST_PREP_GET BIT(0) -#define PMU_RST_PREP_AVAIL BIT(1) -#define PMU_RST_PREP_INT_MASK BIT(31) +#define PMU_RST_PREP REG32(ISH_PMU_BASE + 0x5c) +#define PMU_RST_PREP_GET BIT(0) +#define PMU_RST_PREP_AVAIL BIT(1) +#define PMU_RST_PREP_INT_MASK BIT(31) -#define VNN_ID_DMA0 4 -#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) +#define VNN_ID_DMA0 4 +#define VNN_ID_DMA(chan) (VNN_ID_DMA0 + chan) /* OCP registers */ -#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) -#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20) -#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF +#define OCP_IOSF2OCP_BRIDGE (ISH_OCP_BASE + 0x9400) +#define OCP_AGENT_CONTROL REG32(OCP_IOSF2OCP_BRIDGE + 0x20) +#define OCP_RESPONSE_TO_DISABLE 0xFFFFF8FF /* MISC registers */ -#define MISC_REG_BASE ISH_MISC_BASE -#define DMA_REG_BASE ISH_DMA_BASE +#define MISC_REG_BASE ISH_MISC_BASE +#define DMA_REG_BASE ISH_DMA_BASE #ifndef CHIP_VARIANT_ISH5P4 -#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) -#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) -#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) -#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) -#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) +#define MISC_CHID_CFG_REG REG32(MISC_REG_BASE + 0x40) +#define MISC_DMA_CTL_REG(ch) REG32(MISC_REG_BASE + (4 * (ch))) +#define MISC_SRC_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x20 + (4 * (ch))) +#define MISC_DST_FILLIN_DMA(ch) REG32(MISC_REG_BASE + 0x80 + (4 * (ch))) +#define MISC_ISH_ECC_ERR_SRESP REG32(MISC_REG_BASE + 0x94) #else -#define DMA_MISC_OFFSET 0x1000 -#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET) -#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400) -#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch))) -#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch))) -#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch))) -#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404) +#define DMA_MISC_OFFSET 0x1000 +#define DMA_MISC_BASE (DMA_REG_BASE + DMA_MISC_OFFSET) +#define MISC_CHID_CFG_REG REG32(DMA_MISC_BASE + 0x400) +#define MISC_DMA_CTL_REG(ch) REG32(DMA_MISC_BASE + (4 * (ch))) +#define MISC_SRC_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x100 + (4 * (ch))) +#define MISC_DST_FILLIN_DMA(ch) REG32(DMA_MISC_BASE + 0x200 + (4 * (ch))) +#define MISC_ISH_ECC_ERR_SRESP REG32(DMA_MISC_BASE + 0x404) #endif -#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70) -#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74) +#define MISC_ISH_RTC_COUNTER0 REG32(ISH_MISC_BASE + 0x70) +#define MISC_ISH_RTC_COUNTER1 REG32(ISH_MISC_BASE + 0x74) /* DMA registers */ -#define DMA_CH_REGS_SIZE 0x58 -#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) -#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) -#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0) -#define DMA_EN_REG REG32(DMA_EN_REG_ADDR) -#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398) -#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400) -#define DMA_PSIZE_CHAN0_SIZE 512 -#define DMA_PSIZE_CHAN0_OFFSET 0 -#define DMA_PSIZE_CHAN1_SIZE 128 -#define DMA_PSIZE_CHAN1_OFFSET 13 -#define DMA_PSIZE_UPDATE BIT(26) -#define DMA_MAX_CHANNEL 4 -#define DMA_SAR(chan) REG32(chan + 0x000) -#define DMA_DAR(chan) REG32(chan + 0x008) -#define DMA_LLP(chan) REG32(chan + 0x010) -#define DMA_CTL_LOW(chan) REG32(chan + 0x018) -#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4) -#define DMA_CTL_INT_ENABLE BIT(0) -#define DMA_CTL_DST_TR_WIDTH_SHIFT 1 -#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4 -#define DMA_CTL_DINC_SHIFT 7 -#define DMA_CTL_SINC_SHIFT 9 -#define DMA_CTL_ADDR_INC 0 -#define DMA_CTL_DEST_MSIZE_SHIFT 11 -#define DMA_CTL_SRC_MSIZE_SHIFT 14 -#define DMA_CTL_TT_FC_SHIFT 20 -#define DMA_CTL_TT_FC_M2M_DMAC 0 -#define DMA_ENABLE BIT(0) -#define DMA_CH_EN_BIT(n) BIT(n) -#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n)) -#define DMA_MAX_BLOCK_SIZE (4096) -#define SRC_TR_WIDTH 2 -#define SRC_BURST_SIZE 3 -#define DEST_TR_WIDTH 2 -#define DEST_BURST_SIZE 3 - -#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) -#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) -#define PMU_MASK_EVENT_BIT_HPET BIT(16) -#define PMU_MASK_EVENT_BIT_IPC BIT(17) -#define PMU_MASK_EVENT_BIT_D3 BIT(18) -#define PMU_MASK_EVENT_BIT_DMA BIT(19) -#define PMU_MASK_EVENT_BIT_I2C0 BIT(20) -#define PMU_MASK_EVENT_BIT_I2C1 BIT(21) -#define PMU_MASK_EVENT_BIT_SPI BIT(22) -#define PMU_MASK_EVENT_BIT_UART BIT(23) -#define PMU_MASK_EVENT_BIT_ALL (0xffffffff) - -#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) - -#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44) -#define PMU_LDO_ENABLE_BIT BIT(0) -#define PMU_LDO_RETENTION_BIT BIT(1) -#define PMU_LDO_CALIBRATION_BIT BIT(2) -#define PMU_LDO_READY_BIT BIT(3) +#define DMA_CH_REGS_SIZE 0x58 +#define DMA_CLR_BLOCK_REG REG32(DMA_REG_BASE + 0x340) +#define DMA_CLR_ERR_REG REG32(DMA_REG_BASE + 0x358) +#define DMA_EN_REG_ADDR (DMA_REG_BASE + 0x3A0) +#define DMA_EN_REG REG32(DMA_EN_REG_ADDR) +#define DMA_CFG_REG REG32(DMA_REG_BASE + 0x398) +#define DMA_PSIZE_01 REG32(DMA_REG_BASE + 0x400) +#define DMA_PSIZE_CHAN0_SIZE 512 +#define DMA_PSIZE_CHAN0_OFFSET 0 +#define DMA_PSIZE_CHAN1_SIZE 128 +#define DMA_PSIZE_CHAN1_OFFSET 13 +#define DMA_PSIZE_UPDATE BIT(26) +#define DMA_MAX_CHANNEL 4 +#define DMA_SAR(chan) REG32(chan + 0x000) +#define DMA_DAR(chan) REG32(chan + 0x008) +#define DMA_LLP(chan) REG32(chan + 0x010) +#define DMA_CTL_LOW(chan) REG32(chan + 0x018) +#define DMA_CTL_HIGH(chan) REG32(chan + 0x018 + 0x4) +#define DMA_CTL_INT_ENABLE BIT(0) +#define DMA_CTL_DST_TR_WIDTH_SHIFT 1 +#define DMA_CTL_SRC_TR_WIDTH_SHIFT 4 +#define DMA_CTL_DINC_SHIFT 7 +#define DMA_CTL_SINC_SHIFT 9 +#define DMA_CTL_ADDR_INC 0 +#define DMA_CTL_DEST_MSIZE_SHIFT 11 +#define DMA_CTL_SRC_MSIZE_SHIFT 14 +#define DMA_CTL_TT_FC_SHIFT 20 +#define DMA_CTL_TT_FC_M2M_DMAC 0 +#define DMA_ENABLE BIT(0) +#define DMA_CH_EN_BIT(n) BIT(n) +#define DMA_CH_EN_WE_BIT(n) BIT(8 + (n)) +#define DMA_MAX_BLOCK_SIZE (4096) +#define SRC_TR_WIDTH 2 +#define SRC_BURST_SIZE 3 +#define DEST_TR_WIDTH 2 +#define DEST_BURST_SIZE 3 + +#define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) +#define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) +#define PMU_MASK_EVENT_BIT_HPET BIT(16) +#define PMU_MASK_EVENT_BIT_IPC BIT(17) +#define PMU_MASK_EVENT_BIT_D3 BIT(18) +#define PMU_MASK_EVENT_BIT_DMA BIT(19) +#define PMU_MASK_EVENT_BIT_I2C0 BIT(20) +#define PMU_MASK_EVENT_BIT_I2C1 BIT(21) +#define PMU_MASK_EVENT_BIT_SPI BIT(22) +#define PMU_MASK_EVENT_BIT_UART BIT(23) +#define PMU_MASK_EVENT_BIT_ALL (0xffffffff) + +#define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) + +#define PMU_LDO_CTRL REG32(ISH_PMU_BASE + 0x44) +#define PMU_LDO_ENABLE_BIT BIT(0) +#define PMU_LDO_RETENTION_BIT BIT(1) +#define PMU_LDO_CALIBRATION_BIT BIT(2) +#define PMU_LDO_READY_BIT BIT(3) /* CCU Registers */ -#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) -#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) +#define CCU_TCG_EN REG32(ISH_CCU_BASE + 0x0) +#define CCU_BCG_EN REG32(ISH_CCU_BASE + 0x4) #ifndef CHIP_VARIANT_ISH5P4 -#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) -#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ -#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) -#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) +#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x8) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x34) /* Reset history */ +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x38) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x3c) #else -#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c) -#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */ -#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40) -#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44) +#define CCU_WDT_CD REG32(ISH_CCU_BASE + 0x7c) +#define CCU_RST_HST REG32(ISH_CCU_BASE + 0x3c) /* Reset history */ +#define CCU_TCG_ENABLE REG32(ISH_CCU_BASE + 0x40) +#define CCU_BCG_ENABLE REG32(ISH_CCU_BASE + 0x44) #endif -#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4) -#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8) -#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc) -#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10) -#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14) -#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28) -#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc) -#define CCU_BCG_BIT_MIA BIT(0) -#define CCU_BCG_BIT_DMA BIT(1) -#define CCU_BCG_BIT_I2C0 BIT(2) -#define CCU_BCG_BIT_I2C1 BIT(3) -#define CCU_BCG_BIT_SPI BIT(4) -#define CCU_BCG_BIT_SRAM BIT(5) -#define CCU_BCG_BIT_HPET BIT(6) -#define CCU_BCG_BIT_UART BIT(7) -#define CCU_BCG_BIT_GPIO BIT(8) -#define CCU_BCG_BIT_I2C2 BIT(9) -#define CCU_BCG_BIT_SPI2 BIT(10) -#define CCU_BCG_BIT_ALL (0x7ff) +#define CCU_BCG_MIA REG32(ISH_CCU_BASE + 0x4) +#define CCU_BCG_UART REG32(ISH_CCU_BASE + 0x8) +#define CCU_BCG_I2C REG32(ISH_CCU_BASE + 0xc) +#define CCU_BCG_SPI REG32(ISH_CCU_BASE + 0x10) +#define CCU_BCG_GPIO REG32(ISH_CCU_BASE + 0x14) +#define CCU_BCG_DMA REG32(ISH_CCU_BASE + 0x28) +#define CCU_AONCG_EN REG32(ISH_CCU_BASE + 0xdc) +#define CCU_BCG_BIT_MIA BIT(0) +#define CCU_BCG_BIT_DMA BIT(1) +#define CCU_BCG_BIT_I2C0 BIT(2) +#define CCU_BCG_BIT_I2C1 BIT(3) +#define CCU_BCG_BIT_SPI BIT(4) +#define CCU_BCG_BIT_SRAM BIT(5) +#define CCU_BCG_BIT_HPET BIT(6) +#define CCU_BCG_BIT_UART BIT(7) +#define CCU_BCG_BIT_GPIO BIT(8) +#define CCU_BCG_BIT_I2C2 BIT(9) +#define CCU_BCG_BIT_SPI2 BIT(10) +#define CCU_BCG_BIT_ALL (0x7ff) /* Bitmasks for CCU_RST_HST */ -#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */ -#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */ -#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */ -#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ +#define CCU_SW_RST BIT(0) /* Used to indicate SW reset */ +#define CCU_WDT_RST BIT(1) /* Used to indicate WDT reset */ +#define CCU_MIASS_RST BIT(2) /* Used to indicate UIA shutdown reset */ +#define CCU_SRECC_RST BIT(3) /* Used to indicate SRAM ECC reset */ /* Fabric Agent Status register */ -#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) +#define FABRIC_AGENT_STATUS REG32(ISH_OCP_BASE + 0x7828) #define FABRIC_INBAND_ERR_SECONDARY_BIT BIT(29) -#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) -#define FABRIC_M_ERR_BIT BIT(24) -#define FABRIC_MIA_STATUS_BIT_ERR (FABRIC_INBAND_ERR_SECONDARY_BIT | \ - FABRIC_INBAND_ERR_PRIMARY_BIT | \ - FABRIC_M_ERR_BIT) +#define FABRIC_INBAND_ERR_PRIMARY_BIT BIT(28) +#define FABRIC_M_ERR_BIT BIT(24) +#define FABRIC_MIA_STATUS_BIT_ERR \ + (FABRIC_INBAND_ERR_SECONDARY_BIT | FABRIC_INBAND_ERR_PRIMARY_BIT | \ + FABRIC_M_ERR_BIT) /* CSME Registers */ #ifdef CHIP_VARIANT_ISH5P4 -#define SEC_OFFSET 0x10000 +#define SEC_OFFSET 0x10000 #else -#define SEC_OFFSET 0x0 +#define SEC_OFFSET 0x0 #endif -#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) -#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10) +#define ISH_RST_REG REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44) +#define IPC_PIMR_CIM_SEC (ISH_IPC_BASE + SEC_OFFSET + 0x10) /* IOAPIC registers */ -#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) -#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) +#define IOAPIC_IDX REG32(ISH_IOAPIC_BASE + 0x0) +#define IOAPIC_WDW REG32(ISH_IOAPIC_BASE + 0x10) /* Bare address needed for assembler (ISH_IOAPIC_BASE + 0x40) */ -#define IOAPIC_EOI_REG_ADDR 0xFEC00040 -#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) - -#define IOAPIC_VERSION (0x1) -#define IOAPIC_IOREDTBL (0x10) -#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) -#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) -#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) -#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) -#define IOAPIC_REDTBL_IRR (0x00004000) -#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) -#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) -#define IOAPIC_REDTBL_MASK (0x00010000) +#define IOAPIC_EOI_REG_ADDR 0xFEC00040 +#define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) + +#define IOAPIC_VERSION (0x1) +#define IOAPIC_IOREDTBL (0x10) +#define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) +#define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) +#define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) +#define IOAPIC_REDTBL_INTPOL_LOW (0x00002000) +#define IOAPIC_REDTBL_IRR (0x00004000) +#define IOAPIC_REDTBL_TRIGGER_EDGE (0x00000000) +#define IOAPIC_REDTBL_TRIGGER_LEVEL (0x00008000) +#define IOAPIC_REDTBL_MASK (0x00010000) /* WDT (Watchdog Timer) Registers */ -#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) -#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) -#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) -#define WDT_CONTROL_ENABLE_BIT BIT(17) +#define WDT_CONTROL REG32(ISH_WDT_BASE + 0x0) +#define WDT_RELOAD REG32(ISH_WDT_BASE + 0x4) +#define WDT_VALUES REG32(ISH_WDT_BASE + 0x8) +#define WDT_CONTROL_ENABLE_BIT BIT(17) /* LAPIC registers */ /* Bare address needed for assembler (ISH_LAPIC_BASE + 0xB0) */ -#define LAPIC_EOI_REG_ADDR 0xFEE000B0 -#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) -#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) -#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) -#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) -#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) -#define LAPIC_ERR_RECV_ILLEGAL BIT(6) -#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) +#define LAPIC_EOI_REG_ADDR 0xFEE000B0 +#define LAPIC_EOI_REG REG32(LAPIC_EOI_REG_ADDR) +#define LAPIC_ISR_REG REG32(ISH_LAPIC_BASE + 0x100) +#define LAPIC_ISR_LAST_REG REG32(ISH_LAPIC_BASE + 0x170) +#define LAPIC_IRR_REG REG32(ISH_LAPIC_BASE + 0x200) +#define LAPIC_ESR_REG REG32(ISH_LAPIC_BASE + 0x280) +#define LAPIC_ERR_RECV_ILLEGAL BIT(6) +#define LAPIC_ICR_REG REG32(ISH_LAPIC_BASE + 0x300) /* SRAM control registers */ #ifndef CHIP_VARIANT_ISH5P4 -#define ISH_SRAM_CTRL_BASE 0x00500000 +#define ISH_SRAM_CTRL_BASE 0x00500000 #else -#define ISH_SRAM_CTRL_BASE 0x10500000 +#define ISH_SRAM_CTRL_BASE 0x10500000 #endif -#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) -#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) -#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) -#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) -#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) -#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) +#define ISH_SRAM_CTRL_CSFGR REG32(ISH_SRAM_CTRL_BASE + 0x00) +#define ISH_SRAM_CTRL_INTR REG32(ISH_SRAM_CTRL_BASE + 0x04) +#define ISH_SRAM_CTRL_INTR_MASK REG32(ISH_SRAM_CTRL_BASE + 0x08) +#define ISH_SRAM_CTRL_ERASE_CTRL REG32(ISH_SRAM_CTRL_BASE + 0x0c) +#define ISH_SRAM_CTRL_ERASE_ADDR REG32(ISH_SRAM_CTRL_BASE + 0x10) +#define ISH_SRAM_CTRL_BANK_STATUS REG32(ISH_SRAM_CTRL_BASE + 0x2c) #endif /* __CROS_EC_REGISTERS_H */ -- cgit v1.2.1 From e77d42bf996b773b1976780a5c22f121382bd2a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:29 -0600 Subject: zephyr/emul/emul_syv682x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6d4eaded74753eec68a56589e9685e8dd2d906b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730698 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_syv682x.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/zephyr/emul/emul_syv682x.c b/zephyr/emul/emul_syv682x.c index 9f5ad865bb..870b51dd52 100644 --- a/zephyr/emul/emul_syv682x.c +++ b/zephyr/emul/emul_syv682x.c @@ -68,8 +68,8 @@ i2c_emul_to_syv682x_emul_data(const struct i2c_emul *emul) static void syv682x_emul_set_alert(struct syv682x_emul_data *data, bool alert) { int res = gpio_emul_input_set(data->alert_gpio_port, - /* The signal is inverted. */ - data->alert_gpio_pin, !alert); + /* The signal is inverted. */ + data->alert_gpio_pin, !alert); __ASSERT_NO_MSG(res == 0); } @@ -86,12 +86,12 @@ int syv682x_emul_set_reg(struct i2c_emul *emul, int reg, uint8_t val) } void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status, - uint8_t control_4) + uint8_t control_4) { uint8_t control_4_interrupt = control_4 & SYV682X_CONTROL_4_INT_MASK; struct syv682x_emul_data *data = i2c_emul_to_syv682x_emul_data(emul); int frs_en_gpio = gpio_emul_output_get(data->frs_en_gpio_port, - data->frs_en_gpio_pin); + data->frs_en_gpio_pin); __ASSERT_NO_MSG(frs_en_gpio >= 0); @@ -108,8 +108,8 @@ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status, data->reg[SYV682X_CONTROL_4_REG] |= control_4_interrupt; /* These conditions disable the power path. */ - if (status & (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP | - SYV682X_STATUS_OC_HV)) { + if (status & + (SYV682X_STATUS_TSD | SYV682X_STATUS_OVP | SYV682X_STATUS_OC_HV)) { data->reg[SYV682X_CONTROL_1_REG] |= SYV682X_CONTROL_1_PWR_ENB; } @@ -123,10 +123,9 @@ void syv682x_emul_set_condition(struct i2c_emul *emul, uint8_t status, /* VBAT_OVP disconnects CC and VCONN. */ if (control_4_interrupt & SYV682X_CONTROL_4_VBAT_OVP) { - data->reg[SYV682X_CONTROL_4_REG] &= ~(SYV682X_CONTROL_4_CC1_BPS - | SYV682X_CONTROL_4_CC2_BPS - | SYV682X_CONTROL_4_VCONN1 - | SYV682X_CONTROL_4_VCONN2); + data->reg[SYV682X_CONTROL_4_REG] &= ~( + SYV682X_CONTROL_4_CC1_BPS | SYV682X_CONTROL_4_CC2_BPS | + SYV682X_CONTROL_4_VCONN1 | SYV682X_CONTROL_4_VCONN2); } syv682x_emul_set_alert(data, status | control_4_interrupt); @@ -244,7 +243,7 @@ static void syv682x_emul_reset(struct syv682x_emul_data *data) * @return 0 on success or an error code on failure */ static int syv682x_emul_init(const struct emul *emul, - const struct device *parent) + const struct device *parent) { const struct syv682x_emul_cfg *cfg = emul->cfg; struct syv682x_emul_data *data = emul->data; @@ -263,7 +262,7 @@ static int syv682x_emul_init(const struct emul *emul, } /* Device instantiation */ -#define SYV682X_EMUL(n) \ +#define SYV682X_EMUL(n) \ static struct syv682x_emul_data syv682x_emul_data_##n = { \ .common = { \ .write_byte = syv682x_emul_write_byte, \ @@ -277,27 +276,27 @@ static int syv682x_emul_init(const struct emul *emul, DT_INST_PROP(n, alert_gpio), gpios)), \ .alert_gpio_pin = DT_GPIO_PIN( \ DT_INST_PROP(n, alert_gpio), gpios), \ - }; \ + }; \ static const struct syv682x_emul_cfg syv682x_emul_cfg_##n = { \ .common = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ - }; \ - EMUL_DEFINE(syv682x_emul_init, DT_DRV_INST(n), &syv682x_emul_cfg_##n, \ + }; \ + EMUL_DEFINE(syv682x_emul_init, DT_DRV_INST(n), &syv682x_emul_cfg_##n, \ &syv682x_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL) -#define SYV682X_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &syv682x_emul_data_##n.common.emul; - +#define SYV682X_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &syv682x_emul_data_##n.common.emul; struct i2c_emul *syv682x_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(SYV682X_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From 77b1f42afd7de3fb280f917cf994600b72a5dc2d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:37 -0600 Subject: board/primus/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d6e2918dc821e7ad4077d38352820e710fb04a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727762 Reviewed-by: Jeremy Bettis --- board/primus/led.c | 62 +++++++++++++++++++++++++++--------------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/board/primus/led.c b/board/primus/led.c index 3a8da5ac32..d2c839f5ee 100644 --- a/board/primus/led.c +++ b/board/primus/led.c @@ -24,32 +24,30 @@ #include "task.h" #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ## args) - -#define LED_ON_LVL 100 -#define LED_OFF_LVL 0 -#define LED_BAT_S3_OFF_TIME_MS 3000 -#define LED_BAT_S3_TICK_MS 50 -#define LED_BAT_S3_PWM_RESCALE 5 -#define LED_TOTAL_TICKS 6 -#define TICKS_STEP1_BRIGHTER 0 -#define TICKS_STEP2_DIMMER (1000 / LED_BAT_S3_TICK_MS) -#define TICKS_STEP3_OFF (2 * TICKS_STEP2_DIMMER) -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_LOGO_TICK_SEC (LED_ONE_SEC / 4) +#define CPRINTS(format, args...) cprints(CC_LOGOLED, format, ##args) + +#define LED_ON_LVL 100 +#define LED_OFF_LVL 0 +#define LED_BAT_S3_OFF_TIME_MS 3000 +#define LED_BAT_S3_TICK_MS 50 +#define LED_BAT_S3_PWM_RESCALE 5 +#define LED_TOTAL_TICKS 6 +#define TICKS_STEP1_BRIGHTER 0 +#define TICKS_STEP2_DIMMER (1000 / LED_BAT_S3_TICK_MS) +#define TICKS_STEP3_OFF (2 * TICKS_STEP2_DIMMER) +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_LOGO_TICK_SEC (LED_ONE_SEC / 4) /* Total on/off duration in a period */ -#define PERIOD (LED_LOGO_TICK_SEC * 2) -#define LED_ON 1 -#define LED_OFF EC_LED_COLOR_COUNT -#define LED_EVENT_SUSPEND TASK_EVENT_CUSTOM_BIT(0) -#define LED_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(1) +#define PERIOD (LED_LOGO_TICK_SEC * 2) +#define LED_ON 1 +#define LED_OFF EC_LED_COLOR_COUNT +#define LED_EVENT_SUSPEND TASK_EVENT_CUSTOM_BIT(0) +#define LED_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(1) static int tick; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); static void led_set_color_battery(enum ec_led_colors color) @@ -94,11 +92,11 @@ void led_set_color_power(int onoff_status) /* primus logo led and power led have same behavior. */ if (onoff_status == LED_ON) { pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_ON_LVL); - pwm_set_duty(PWM_CH_LED4, LED_ON_LVL); + pwm_set_duty(PWM_CH_LED4, LED_ON_LVL); } else { /* LED_OFF and unsupported colors */ pwm_set_duty(PWM_CH_TKP_A_LED_N, LED_OFF_LVL); - pwm_set_duty(PWM_CH_LED4, LED_OFF_LVL); + pwm_set_duty(PWM_CH_LED4, LED_OFF_LVL); } } @@ -176,7 +174,7 @@ static void suspend_led_update(void) * if we are not transitioning to suspend, we should break here. */ if (!chipset_in_or_transitioning_to_state( - CHIPSET_STATE_ANY_SUSPEND)) + CHIPSET_STATE_ANY_SUSPEND)) break; /* 1s gradual on, 1s gradual off, 3s off */ @@ -187,9 +185,9 @@ static void suspend_led_update(void) * behavior. */ pwm_set_duty(PWM_CH_TKP_A_LED_N, - tick * LED_BAT_S3_PWM_RESCALE); + tick * LED_BAT_S3_PWM_RESCALE); pwm_set_duty(PWM_CH_LED4, - tick * LED_BAT_S3_PWM_RESCALE); + tick * LED_BAT_S3_PWM_RESCALE); msleep(LED_BAT_S3_TICK_MS); } else if (tick <= TICKS_STEP3_OFF) { /* decrease 5 duty every 50ms until PWM=0 @@ -197,10 +195,12 @@ static void suspend_led_update(void) * A-cover and power button led are shared same * behavior. */ - pwm_set_duty(PWM_CH_TKP_A_LED_N, (TICKS_STEP3_OFF - - tick) * LED_BAT_S3_PWM_RESCALE); - pwm_set_duty(PWM_CH_LED4, (TICKS_STEP3_OFF - - tick) * LED_BAT_S3_PWM_RESCALE); + pwm_set_duty(PWM_CH_TKP_A_LED_N, + (TICKS_STEP3_OFF - tick) * + LED_BAT_S3_PWM_RESCALE); + pwm_set_duty(PWM_CH_LED4, + (TICKS_STEP3_OFF - tick) * + LED_BAT_S3_PWM_RESCALE); msleep(LED_BAT_S3_TICK_MS); } else { tick = TICKS_STEP1_BRIGHTER; -- cgit v1.2.1 From 04915dc49e22125eff042a73ef27d8e51944b13b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:58 -0600 Subject: chip/stm32/ucpd-stm32gx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I86b3b30b2f6dbcd9e351c620b9f3cb86a001bd99 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729538 Reviewed-by: Jeremy Bettis --- chip/stm32/ucpd-stm32gx.c | 268 +++++++++++++++++++--------------------------- 1 file changed, 113 insertions(+), 155 deletions(-) diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c index d8c41c8f28..7783721067 100644 --- a/chip/stm32/ucpd-stm32gx.c +++ b/chip/stm32/ucpd-stm32gx.c @@ -20,8 +20,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define USB_VID_STM32 0x0483 @@ -33,22 +33,19 @@ */ #define UCPD_BUF_LEN 30 -#define UCPD_IMR_RX_INT_MASK (STM32_UCPD_IMR_RXNEIE| \ - STM32_UCPD_IMR_RXORDDETIE | \ - STM32_UCPD_IMR_RXHRSTDETIE | \ - STM32_UCPD_IMR_RXOVRIE | \ - STM32_UCPD_IMR_RXMSGENDIE) +#define UCPD_IMR_RX_INT_MASK \ + (STM32_UCPD_IMR_RXNEIE | STM32_UCPD_IMR_RXORDDETIE | \ + STM32_UCPD_IMR_RXHRSTDETIE | STM32_UCPD_IMR_RXOVRIE | \ + STM32_UCPD_IMR_RXMSGENDIE) -#define UCPD_IMR_TX_INT_MASK (STM32_UCPD_IMR_TXISIE | \ - STM32_UCPD_IMR_TXMSGDISCIE | \ - STM32_UCPD_IMR_TXMSGSENTIE | \ - STM32_UCPD_IMR_TXMSGABTIE | \ - STM32_UCPD_IMR_TXUNDIE) +#define UCPD_IMR_TX_INT_MASK \ + (STM32_UCPD_IMR_TXISIE | STM32_UCPD_IMR_TXMSGDISCIE | \ + STM32_UCPD_IMR_TXMSGSENTIE | STM32_UCPD_IMR_TXMSGABTIE | \ + STM32_UCPD_IMR_TXUNDIE) -#define UCPD_ICR_TX_INT_MASK (STM32_UCPD_ICR_TXMSGDISCCF | \ - STM32_UCPD_ICR_TXMSGSENTCF | \ - STM32_UCPD_ICR_TXMSGABTCF | \ - STM32_UCPD_ICR_TXUNDCF) +#define UCPD_ICR_TX_INT_MASK \ + (STM32_UCPD_ICR_TXMSGDISCCF | STM32_UCPD_ICR_TXMSGSENTCF | \ + STM32_UCPD_ICR_TXMSGABTCF | STM32_UCPD_ICR_TXUNDCF) #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3) #define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3) @@ -69,16 +66,16 @@ enum ucpd_state { }; /* Events for pd_interrupt_handler_task */ -#define UCPD_EVT_GOOD_CRC_REQ BIT(0) -#define UCPD_EVT_TCPM_MSG_REQ BIT(1) -#define UCPD_EVT_HR_REQ BIT(2) -#define UCPD_EVT_TX_MSG_FAIL BIT(3) -#define UCPD_EVT_TX_MSG_DISC BIT(4) +#define UCPD_EVT_GOOD_CRC_REQ BIT(0) +#define UCPD_EVT_TCPM_MSG_REQ BIT(1) +#define UCPD_EVT_HR_REQ BIT(2) +#define UCPD_EVT_TX_MSG_FAIL BIT(3) +#define UCPD_EVT_TX_MSG_DISC BIT(4) #define UCPD_EVT_TX_MSG_SUCCESS BIT(5) -#define UCPD_EVT_HR_DONE BIT(6) -#define UCPD_EVT_HR_FAIL BIT(7) -#define UCPD_EVT_RX_GOOD_CRC BIT(8) -#define UCPD_EVT_RX_MSG BIT(9) +#define UCPD_EVT_HR_DONE BIT(6) +#define UCPD_EVT_HR_FAIL BIT(7) +#define UCPD_EVT_RX_GOOD_CRC BIT(8) +#define UCPD_EVT_RX_MSG BIT(9) #define UCPD_T_RECEIVE_US (1 * MSEC) @@ -161,11 +158,7 @@ int ucpd_tx_state_log_idx; int ucpd_tx_state_log_freeze; static char ucpd_names[][12] = { - "TX_IDLE", - "ACT_TCPM", - "ACT_CRC", - "HARD_RST", - "WAIT_CRC", + "TX_IDLE", "ACT_TCPM", "ACT_CRC", "HARD_RST", "WAIT_CRC", }; /* Defines and macros used for ucpd pd message logging */ #define MSG_LOG_LEN 64 @@ -218,8 +211,8 @@ static void ucpd_log_add_msg(uint16_t header, int dir) * crc -> GoodCrc received following tx message */ if (msg_log_cnt++ < MSG_LOG_LEN) { - int msg_bytes = MIN((PD_HEADER_CNT(header) << 2) + 2, - MSG_BUF_LEN); + int msg_bytes = + MIN((PD_HEADER_CNT(header) << 2) + 2, MSG_BUF_LEN); msg_log[idx].header = header; msg_log[idx].ts = ts; @@ -278,10 +271,10 @@ static void ucpd_cc_status(int port) * values of CC voltage detector, polarity, and PD enable status are * displayed. */ - rv = stm32gx_ucpd_get_cc(port,&v_cc1, &v_cc2); + rv = stm32gx_ucpd_get_cc(port, &v_cc1, &v_cc2); rp_name = rp_string[(rc >> 4) % 0x3]; - ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", - ccx[cc1_pull], ccx[cc2_pull], rp_name); + ccprintf("\tcc1\t = %s\n\tcc2\t = %s\n\tRp\t = %s\n", ccx[cc1_pull], + ccx[cc2_pull], rp_name); if (!rv) ccprintf("\tcc1_v\t = %d\n\tcc2_v\t = %d\n", v_cc1, v_cc2); } @@ -329,8 +322,8 @@ static void ucpd_cc_change_notify(void) ccprintf("vstate: cc1 = %x, cc2 = %x, Rp = %d\n", (sr >> STM32_UCPD_SR_VSTATE_CC1_SHIFT) & 0x3, (sr >> STM32_UCPD_SR_VSTATE_CC2_SHIFT) & 0x3, - (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) - & 0x3); + (ucpd_cc_set_save >> STM32_UCPD_CR_ANASUBMODE_SHIFT) & + 0x3); /* Display CC status on EC console */ ucpd_cc_status(0); } @@ -345,7 +338,9 @@ static int ucpd_msg_is_good_crc(uint16_t header) * type in the header. */ return ((PD_HEADER_CNT(header) == 0) && (PD_HEADER_EXT(header) == 0) && - (PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? 1 : 0; + (PD_HEADER_TYPE(header) == PD_CTRL_GOOD_CRC)) ? + 1 : + 0; } static void ucpd_hard_reset_rx_log(void) @@ -365,7 +360,7 @@ static void ucpd_port_enable(int port, int enable) static int ucpd_is_cc_pull_active(int port, enum usbpd_cc_pin cc_line) { int cc_enable = (STM32_UCPD_CR(port) & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; + STM32_UCPD_CR_CCENABLE_SHIFT; return ((cc_enable >> cc_line) & 0x1); } @@ -425,10 +420,10 @@ int stm32gx_ucpd_init(int port) task_disable_irq(STM32_IRQ_UCPD1); /* - * After exiting reset, stm32gx will have dead battery mode enabled by - * default which connects Rd to CC1/CC2. This should be disabled when EC - * is powered up. - */ + * After exiting reset, stm32gx will have dead battery mode enabled by + * default which connects Rd to CC1/CC2. This should be disabled when EC + * is powered up. + */ STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; /* Ensure that clock to UCPD is enabled */ @@ -446,9 +441,9 @@ int stm32gx_ucpd_init(int port) ucpd_port_enable(port, 0); cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); + STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | + STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | + STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); STM32_UCPD_CFGR1(port) = cfgr1_reg; /* @@ -463,9 +458,9 @@ int stm32gx_ucpd_init(int port) /* Configure CC change interrupts */ STM32_UCPD_IMR(port) = STM32_UCPD_IMR_TYPECEVT1IE | - STM32_UCPD_IMR_TYPECEVT2IE; + STM32_UCPD_IMR_TYPECEVT2IE; STM32_UCPD_ICR(port) = STM32_UCPD_ICR_TYPECEVT1CF | - STM32_UCPD_ICR_TYPECEVT2CF; + STM32_UCPD_ICR_TYPECEVT2CF; /* SOP'/SOP'' must be enabled via TCPCI call */ ucpd_rx_sop_prime_enabled = false; @@ -486,7 +481,7 @@ int stm32gx_ucpd_release(int port) } int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int vstate_cc1; int vstate_cc2; @@ -500,7 +495,7 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, * * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, * but needs to be modified slightly for case ANAMODE = 0. - * + * * If presenting Rp (source), then need to to a circular shift of * vstate_ccx value: * vstate_cc | cc_state @@ -515,9 +510,9 @@ int stm32gx_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, /* Get Rp or Rd active */ anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; + STM32_UCPD_SR_VSTATE_CC1_SHIFT; vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; + STM32_UCPD_SR_VSTATE_CC2_SHIFT; /* Do circular shift if port == source */ if (anamode) { @@ -544,8 +539,9 @@ int stm32gx_ucpd_get_role_control(int port) int cc1; int cc2; int anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); - int anasubmode = (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) - >> STM32_UCPD_CR_ANASUBMODE_SHIFT; + int anasubmode = + (STM32_UCPD_CR(port) & STM32_UCPD_CR_ANASUBMODE_MASK) >> + STM32_UCPD_CR_ANASUBMODE_SHIFT; /* * Role control register is defined as: @@ -575,9 +571,9 @@ int stm32gx_ucpd_get_role_control(int port) * Rp = (ANASUBMODE - 1) & 0x3 */ cc1 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_1) ? anamode + 1 : - TYPEC_CC_OPEN; + TYPEC_CC_OPEN; cc2 = ucpd_is_cc_pull_active(port, USBPD_CC_PIN_2) ? anamode + 1 : - TYPEC_CC_OPEN; + TYPEC_CC_OPEN; role_control = cc1 | (cc2 << 2); /* Circular shift anasubmode to convert to Rp range */ role_control |= (UCPD_ANASUB_TO_RP(anasubmode) << 4); @@ -633,7 +629,7 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp) /* Set ANAMODE if cc_pull is Rd */ if (cc_pull == TYPEC_CC_RD) { cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK; - /* Clear ANAMODE if cc_pull is Rp */ + /* Clear ANAMODE if cc_pull is Rp */ } else if (cc_pull == TYPEC_CC_RP) { cr &= ~(STM32_UCPD_CR_ANAMODE); cr |= ucpd_get_cc_enable_mask(port); @@ -650,7 +646,8 @@ int stm32gx_ucpd_set_cc(int port, int cc_pull, int rp) return EC_SUCCESS; } -int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) { +int stm32gx_ucpd_set_polarity(int port, enum tcpc_cc_polarity polarity) +{ /* * Polarity impacts the PHYCCSEL, CCENABLE, and CCxTCDIS fields. This * function is called when polarity is updated at TCPM layer. STM32Gx @@ -707,7 +704,7 @@ int stm32gx_ucpd_sop_prime_enable(int port, bool enable) } int stm32gx_ucpd_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) + struct ec_response_pd_chip_info_v1 *chip_info) { chip_info->vendor_id = USB_VID_STM32; chip_info->product_id = 0; @@ -726,7 +723,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) type = ucpd_tx_active_buffer->type; if (type == TCPCI_MSG_TX_HARD_RESET) { - /* + /* * From RM0440 45.4.4: * In order to facilitate generation of a Hard Reset, a special * code of TXMODE field is used. No other fields need to be @@ -745,9 +742,9 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) */ /* Enable interrupt for Hard Reset sent/discarded */ STM32_UCPD_ICR(port) = STM32_UCPD_ICR_HRSTDISCCF | - STM32_UCPD_ICR_HRSTSENTCF; + STM32_UCPD_ICR_HRSTSENTCF; STM32_UCPD_IMR(port) |= STM32_UCPD_IMR_HRSTDISCIE | - STM32_UCPD_IMR_HRSTSENTIE; + STM32_UCPD_IMR_HRSTSENTIE; /* Initiate Hard Reset */ STM32_UCPD_CR(port) |= STM32_UCPD_CR_TXHRST; } else if (type != TCPCI_MSG_INVALID) { @@ -794,7 +791,7 @@ static int stm32gx_ucpd_start_transmit(int port, enum ucpd_tx_msg msg_type) STM32_UCPD_TX_ORDSETR(port) = ucpd_txorderset[type]; /* Reset msg byte index */ - ucpd_tx_active_buffer-> msg_index = 0; + ucpd_tx_active_buffer->msg_index = 0; /* Enable interrupts */ ucpd_tx_interrupts_enable(port, 1); @@ -860,13 +857,11 @@ static void ucpd_task_log_dump(void) ccprintf("\n\t UCDP Task Log\n"); for (n = 0; n < TX_STATE_LOG_LEN; n++) { - ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", - n, + ccprintf("[%d]:\t\%8s\t%8s\t%02x\t%08x\t%09d\t%d\n", n, ucpd_names[ucpd_tx_statelog[idx].enter_state], ucpd_names[ucpd_tx_statelog[idx].exit_state], ucpd_tx_statelog[idx].tx_request, - ucpd_tx_statelog[idx].evt, - ucpd_tx_statelog[idx].ts, + ucpd_tx_statelog[idx].evt, ucpd_tx_statelog[idx].ts, ucpd_tx_statelog[idx].timeout_us); idx = (idx + 1) & TX_STATE_LOG_MASK; @@ -915,8 +910,8 @@ static void ucpd_manage_tx(int port, int evt) * not been sent yet, it needs to be discarded * based on the received message event. */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete( + port, TCPC_TX_COMPLETE_DISCARDED); ucpd_tx_request &= ~MSG_TCPM_MASK; } else if (!ucpd_rx_msg_active) { ucpd_set_tx_state(STATE_ACTIVE_TCPM); @@ -924,9 +919,10 @@ static void ucpd_manage_tx(int port, int evt) /* Save msgID required for GoodCRC check */ hdr = ucpd_tx_buffers[TX_MSG_TCPM].data.header; msg_id_match = PD_HEADER_ID(hdr); - tx_retry_max = PD_HEADER_REV(hdr) == PD_REV30 ? - UCPD_N_RETRY_COUNT_REV30 : - UCPD_N_RETRY_COUNT_REV20; + tx_retry_max = + PD_HEADER_REV(hdr) == PD_REV30 ? + UCPD_N_RETRY_COUNT_REV30 : + UCPD_N_RETRY_COUNT_REV20; } } @@ -962,8 +958,9 @@ static void ucpd_manage_tx(int port, int evt) * was just received. */ ucpd_set_tx_state(STATE_IDLE); - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete( + port, + TCPC_TX_COMPLETE_DISCARDED); ucpd_set_tx_state(STATE_IDLE); } else { /* @@ -977,8 +974,8 @@ static void ucpd_manage_tx(int port, int evt) enum tcpc_transmit_complete status; status = (evt & UCPD_EVT_TX_MSG_FAIL) ? - TCPC_TX_COMPLETE_FAILED : - TCPC_TX_COMPLETE_DISCARDED; + TCPC_TX_COMPLETE_FAILED : + TCPC_TX_COMPLETE_DISCARDED; ucpd_set_tx_state(STATE_IDLE); pd_transmit_complete(port, status); } @@ -997,11 +994,9 @@ static void ucpd_manage_tx(int port, int evt) break; case STATE_WAIT_CRC_ACK: - if (evt & UCPD_EVT_RX_GOOD_CRC && - ucpd_crc_id == msg_id_match) { + if (evt & UCPD_EVT_RX_GOOD_CRC && ucpd_crc_id == msg_id_match) { /* GoodCRC with matching ID was received */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_SUCCESS); + pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS); ucpd_set_tx_state(STATE_IDLE); #ifdef CONFIG_STM32G4_UCPD_DEBUG ucpd_log_mark_crc(); @@ -1026,8 +1021,7 @@ static void ucpd_manage_tx(int port, int evt) * in this state, then treat it as a discard from an * incoming message. */ - pd_transmit_complete(port, - TCPC_TX_COMPLETE_DISCARDED); + pd_transmit_complete(port, TCPC_TX_COMPLETE_DISCARDED); ucpd_set_tx_state(STATE_IDLE); } break; @@ -1064,7 +1058,7 @@ static void ucpd_manage_tx(int port, int evt) */ void ucpd_task(void *p) { - const int port = (int) ((intptr_t) p); + const int port = (int)((intptr_t)p); /* Init variables used to manage tx process */ stm32gx_ucpd_state_init(port); @@ -1117,8 +1111,8 @@ void ucpd_task(void *p) ucpd_manage_tx(port, evt); /* Look at task events only once. */ evt = 0; - } while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE - && !ucpd_rx_msg_active); + } while (ucpd_tx_request && ucpd_tx_state == STATE_IDLE && + !ucpd_rx_msg_active); } } @@ -1176,9 +1170,7 @@ static void ucpd_send_good_crc(int port, uint16_t rx_header) task_set_event(TASK_ID_UCPD, UCPD_EVT_GOOD_CRC_REQ); } -int stm32gx_ucpd_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, +int stm32gx_ucpd_transmit(int port, enum tcpci_msg_type type, uint16_t header, const uint32_t *data) { /* Length in bytes = (4 * object len) + 2 header byes */ @@ -1220,11 +1212,11 @@ int stm32gx_ucpd_get_message_raw(int port, uint32_t *payload, int *head) *head = *rx_header; #ifdef CONFIG_USB_PD_DECODE_SOP -/* - * The message header is a 16-bit value that's stored in a 32-bit data type. - * SOP* is encoded in bits 31 to 28 of the 32-bit data type. - * NOTE: The 4 byte header is not part of the PD spec. - */ + /* + * The message header is a 16-bit value that's stored in a 32-bit data + * type. SOP* is encoded in bits 31 to 28 of the 32-bit data type. NOTE: + * The 4 byte header is not part of the PD spec. + */ /* Get SOP value */ sop = STM32_UCPD_RX_ORDSETR(port) & STM32_UCPD_RXORDSETR_MASK; /* Put SOP in bits 31:28 of 32 bit header */ @@ -1253,9 +1245,10 @@ static void stm32gx_ucpd1_irq(void) /* STM32_IRQ_UCPD indicates this is from UCPD1, so port = 0 */ int port = 0; uint32_t sr = STM32_UCPD_SR(port); - uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | STM32_UCPD_SR_TXMSGABT - | STM32_UCPD_SR_TXMSGDISC | STM32_UCPD_SR_HRSTSENT | - STM32_UCPD_SR_HRSTDISC; + uint32_t tx_done_mask = STM32_UCPD_SR_TXMSGSENT | + STM32_UCPD_SR_TXMSGABT | + STM32_UCPD_SR_TXMSGDISC | + STM32_UCPD_SR_HRSTSENT | STM32_UCPD_SR_HRSTDISC; /* Check for CC events, set event to wake PD task */ if (sr & (STM32_UCPD_SR_TYPECEVT1 | STM32_UCPD_SR_TYPECEVT2)) { @@ -1279,8 +1272,8 @@ static void stm32gx_ucpd1_irq(void) #ifdef CONFIG_STM32G4_UCPD_DEBUG ucpd_log_mark_tx_comp(); #endif - } else if (sr & (STM32_UCPD_SR_TXMSGABT | - STM32_UCPD_SR_TXUND)) { + } else if (sr & + (STM32_UCPD_SR_TXMSGABT | STM32_UCPD_SR_TXUND)) { task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_FAIL); } else if (sr & STM32_UCPD_SR_TXMSGDISC) { task_set_event(TASK_ID_UCPD, UCPD_EVT_TX_MSG_DISC); @@ -1320,7 +1313,7 @@ static void stm32gx_ucpd1_irq(void) int good_crc = 0; type = STM32_UCPD_RX_ORDSETR(port) & - STM32_UCPD_RXORDSETR_MASK; + STM32_UCPD_RXORDSETR_MASK; good_crc = ucpd_msg_is_good_crc(*rx_header); @@ -1337,26 +1330,25 @@ static void stm32gx_ucpd1_irq(void) */ if (!good_crc && (ucpd_rx_sop_prime_enabled || type == TCPCI_MSG_SOP)) { - /* * If BIST test mode is active, then still need * to send GoodCRC reply, but there is no need * to send the message up to the tcpm layer. */ - if(!ucpd_rx_bist_mode) { + if (!ucpd_rx_bist_mode) { if (tcpm_enqueue_message(port)) - hook_call_deferred(&ucpd_rx_enque_error_data, - 0); + hook_call_deferred( + &ucpd_rx_enque_error_data, + 0); } - task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_MSG); + task_set_event(TASK_ID_UCPD, UCPD_EVT_RX_MSG); /* Send GoodCRC message (if required) */ ucpd_send_good_crc(port, *rx_header); } else if (good_crc) { task_set_event(TASK_ID_UCPD, - UCPD_EVT_RX_GOOD_CRC); + UCPD_EVT_RX_GOOD_CRC); ucpd_crc_id = PD_HEADER_ID(*rx_header); } } else { @@ -1379,44 +1371,16 @@ DECLARE_IRQ(STM32_IRQ_UCPD1, stm32gx_ucpd1_irq, 1); #ifdef CONFIG_STM32G4_UCPD_DEBUG static char ctrl_names[][12] = { - "rsvd", - "GoodCRC", - "Goto Min", - "Accept", - "Reject", - "Ping", - "PS_Rdy", - "Get_SRC", - "Get_SNK", - "DR_Swap", - "PR_Swap", - "VCONN_Swp", - "Wait", - "Soft_Rst", - "RSVD", - "RSVD", - "Not_Sup", - "Get_SRC_Ext", - "Get_Status", + "rsvd", "GoodCRC", "Goto Min", "Accept", "Reject", + "Ping", "PS_Rdy", "Get_SRC", "Get_SNK", "DR_Swap", + "PR_Swap", "VCONN_Swp", "Wait", "Soft_Rst", "RSVD", + "RSVD", "Not_Sup", "Get_SRC_Ext", "Get_Status", }; static char data_names[][10] = { - "RSVD", - "SRC_CAP", - "REQUEST", - "BIST", - "SINK_CAP", - "BATTERY", - "ALERT", - "GET_INFO", - "ENTER_USB", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "RSVD", - "VDM", + "RSVD", "SRC_CAP", "REQUEST", "BIST", "SINK_CAP", "BATTERY", + "ALERT", "GET_INFO", "ENTER_USB", "RSVD", "RSVD", "RSVD", + "RSVD", "RSVD", "RSVD", "VDM", }; static void ucpd_dump_msg_log(void) @@ -1428,7 +1392,6 @@ static void ucpd_dump_msg_log(void) uint16_t header; char *name; - ccprintf("ucpd: msg_total = %d\n", msg_log_cnt); ccprintf("Idx\t Delta(us)\tDir\t Type\t\tLen\t s1 s2 PR\t DR\n"); ccprintf("-----------------------------------------------------------" @@ -1446,18 +1409,13 @@ static void ucpd_dump_msg_log(void) name = len ? data_names[type] : ctrl_names[type]; dir = msg_log[i].dir; if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; + delta_ts = msg_log[i].ts - msg_log[i - 1].ts; } ccprintf("msg[%02d]: %08d\t %s\t %8s\t %02d\t %d %d\t" "%s\t %s", - i, - delta_ts, - dir ? "Rx" : "Tx", - name, - len, - msg_log[i].comp, - msg_log[i].crc, + i, delta_ts, dir ? "Rx" : "Tx", name, len, + msg_log[i].comp, msg_log[i].crc, PD_HEADER_PROLE(header) ? "SRC" : "SNK", PD_HEADER_DROLE(header) ? "DFP" : "UFP"); len = MIN((len * 4) + 2, MSG_BUF_LEN); @@ -1465,10 +1423,10 @@ static void ucpd_dump_msg_log(void) ccprintf(" %02x", msg_log[i].buf[j]); } else { if (i) { - delta_ts = msg_log[i].ts - msg_log[i-1].ts; + delta_ts = msg_log[i].ts - msg_log[i - 1].ts; } - ccprintf("msg[%02d]: %08d\t CC Voltage Change!", - i, delta_ts); + ccprintf("msg[%02d]: %08d\t CC Voltage Change!", i, + delta_ts); } ccprintf("\n"); msleep(5); @@ -1496,7 +1454,7 @@ static void stm32gx_ucpd_set_cc_debug(int port, int cc_mask, int pull, int rp) */ /* Get existing cc enable value */ cc_enable = (cr & STM32_UCPD_CR_CCENABLE_MASK) >> - STM32_UCPD_CR_CCENABLE_SHIFT; + STM32_UCPD_CR_CCENABLE_SHIFT; /* Apply cc_mask (enable CC line specified) */ cc_enable |= cc_mask; @@ -1527,7 +1485,7 @@ void ucpd_info(int port) /* Dump ucpd task state info */ ccprintf("ucpd: tx_state = %s, tx_req = %02x, timeout_us = %d\n", - ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us); + ucpd_names[ucpd_tx_state], ucpd_tx_request, ucpd_timeout_us); ucpd_task_log_dump(); } -- cgit v1.2.1 From d5d6f7cc9975a0bb6107ac332c48b47f52fd39fe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:35 -0600 Subject: board/waddledoo2/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0bbdb30156168b779606173dfaa6f04a6e0e2da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729104 Reviewed-by: Jeremy Bettis --- board/waddledoo2/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/waddledoo2/cbi_ssfc.h b/board/waddledoo2/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/waddledoo2/cbi_ssfc.h +++ b/board/waddledoo2/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 41c78ff985e304a694bab87d3a8d092a78349174 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:41 -0600 Subject: zephyr/test/drivers/src/stm_mems_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb6583dec4bf7c422a351f89b63fae0d741849ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730993 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/stm_mems_common.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/test/drivers/src/stm_mems_common.c b/zephyr/test/drivers/src/stm_mems_common.c index fef0766c7d..26c00feaef 100644 --- a/zephyr/test/drivers/src/stm_mems_common.c +++ b/zephyr/test/drivers/src/stm_mems_common.c @@ -317,14 +317,14 @@ ZTEST(stm_mems_common, test_st_normalize) st_normalize(&sensor, (int *)&actual_output, (uint8_t *)input_reading); zassert_within(actual_output[X], expected_output[X], 0.5f, - "X output is %d but expected %d", actual_output[X], - expected_output[X]); + "X output is %d but expected %d", actual_output[X], + expected_output[X]); zassert_within(actual_output[Y], expected_output[Y], 0.5f, - "Y output is %d but expected %d", actual_output[Y], - expected_output[Y]); + "Y output is %d but expected %d", actual_output[Y], + expected_output[Y]); zassert_within(actual_output[Z], expected_output[Z], 0.5f, - "Z output is %d but expected %d", actual_output[Z], - expected_output[Z]); + "Z output is %d but expected %d", actual_output[Z], + expected_output[Z]); } static void stm_mems_common_before(void *state) -- cgit v1.2.1 From 0326b0ba04c43cadc70d73e9279fbae43bba1aae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:01 -0600 Subject: board/blipper/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1163735b06fec68b419428df265e782ab80904c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728058 Reviewed-by: Jeremy Bettis --- board/blipper/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/blipper/cbi_ssfc.h b/board/blipper/cbi_ssfc.h index f4a51b8e91..7b29a1c585 100644 --- a/board/blipper/cbi_ssfc.h +++ b/board/blipper/cbi_ssfc.h @@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 49007151e25958afc2e3deb296b672a2d8a8f5e2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:20 -0600 Subject: board/agah/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I60a2b9212d40fb01a1b07109a1ef60ca53a6796b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727971 Reviewed-by: Jeremy Bettis --- board/agah/fans.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/agah/fans.c b/board/agah/fans.c index df6102b460..236c1021a5 100644 --- a/board/agah/fans.c +++ b/board/agah/fans.c @@ -30,14 +30,14 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; static const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_1, /* Use MFT id to control fan */ + .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From c383ffcb79b1f056c2750b5ebabb9d7f21e1629f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:11 -0600 Subject: board/nucleo-h743zi/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I808fb2934b3a454866d2911513b60782713eefb9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728783 Reviewed-by: Jeremy Bettis --- board/nucleo-h743zi/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/nucleo-h743zi/board.c b/board/nucleo-h743zi/board.c index c69a456425..0de182edcd 100644 --- a/board/nucleo-h743zi/board.c +++ b/board/nucleo-h743zi/board.c @@ -31,8 +31,8 @@ static void ap_deferred(void) * in S0: SLP_S3_L is 1 and SLP_S0_L is 1. * in S5/G3, the FP MCU should not be running. */ - int running = gpio_get_level(GPIO_PCH_SLP_S3_L) - && gpio_get_level(GPIO_PCH_SLP_S0_L); + int running = gpio_get_level(GPIO_PCH_SLP_S3_L) && + gpio_get_level(GPIO_PCH_SLP_S0_L); if (running) { /* S0 */ disable_sleep(SLEEP_MASK_AP_RUN); -- cgit v1.2.1 From b87a91cb41b5b3c9dcf21a82bea3067271fa5231 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:22 -0600 Subject: board/volteer/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a0003d2d6d36e7d66f2cdcd6ed74801f851e48e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729091 Reviewed-by: Jeremy Bettis --- board/volteer/board.h | 101 +++++++++++++++++++++++++------------------------- 1 file changed, 50 insertions(+), 51 deletions(-) diff --git a/board/volteer/board.h b/board/volteer/board.h index 10fd23486f..473b3ad2eb 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -54,49 +54,48 @@ /* TCS3400 ALS */ #define CONFIG_ALS -#define ALS_COUNT 1 +#define ALS_COUNT 1 #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL) | BIT(CLEAR_ALS)) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ #define CONFIG_USB_PD_FRS_PPC /* BC 1.2 */ @@ -106,8 +105,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -115,42 +114,42 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER #define CONFIG_DEBUG_ASSERT_BRIEF -- cgit v1.2.1 From bd7ced924743a782ee8ac16cd854250558ffc823 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:26 -0600 Subject: driver/tcpm/rt1718s.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If9d36d93b97bd3a34fbc2cca38370a5cd8e62cba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730098 Reviewed-by: Jeremy Bettis --- driver/tcpm/rt1718s.h | 349 +++++++++++++++++++++++++------------------------- 1 file changed, 173 insertions(+), 176 deletions(-) diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index a4f7545a06..0ac6ab4587 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -10,181 +10,179 @@ #include "usb_pd_tcpm.h" /* RT1718S Private RegMap */ -#define RT1718S_I2C_ADDR1_FLAGS 0x43 -#define RT1718S_I2C_ADDR2_FLAGS 0x40 - -#define RT1718S_VID 0x29CF -#define RT1718S_PID 0x1718 - -#define RT1718S_DEVICE_ID 0x04 -#define RT1718S_DEVICE_ID_ES1 0x4511 -#define RT1718S_DEVICE_ID_ES2 0x4513 - -#define RT1718S_PHYCTRL1 0x80 -#define RT1718S_PHYCTRL2 0x81 -#define RT1718S_PHYCTRL3 0x82 -#define RT1718S_PHYCTRL7 0x86 -#define RT1718S_VCON_CTRL1 0x8A -#define RT1718S_VCON_CTRL3 0x8C -#define RT1718S_VCON_LIMIT_MODE BIT(0) -#define RT1718S_SYS_CTRL1 0x8F -#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID BIT(6) -#define RT1718S_SYS_CTRL1_SHIPPING_OFF BIT(5) -#define RT1718S_SYS_CTRL2 0x90 -#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN BIT(0) -#define RT1718S_SYS_CTRL2_LPWR_EN BIT(3) - -#define RT1718S_VCONN_CONTROL_2 0x8B -#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7) -#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6) -#define RT1718S_VCONN_CONTROL_2_RVP_EN BIT(3) -#define RT1718S_VCONN_CONTROL_3 0x8C -#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5) -#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1) - -#define RT1718S_SYS_CTRL2 0x90 -#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN BIT(5) - -#define RT1718S_RT_MASK1 0x91 -#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW BIT(7) -#define RT1718S_RT_MASK1_M_RX_FRS BIT(6) -#define RT1718S_RT_MASK2 0x92 -#define RT1718S_RT_MASK3 0x93 -#define RT1718S_RT_MASK4 0x94 -#define RT1718S_RT_MASK5 0x95 -#define RT1718S_RT_MASK6 0x96 -#define RT1718S_RT_MASK6_M_BC12_SNK_DONE BIT(7) -#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE BIT(6) -#define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5) -#define RT1718S_RT_MASK7 0x97 - -#define RT1718S_RT_INT1 0x98 -#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW BIT(7) -#define RT1718S_RT_INT1_INT_RX_FRS BIT(6) -#define RT1718S_RT_INT2 0x99 -#define RT1718S_RT_INT6 0x9D -#define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7) -#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6) -#define RT1718S_RT_INT6_INT_BC12_TA_CHG BIT(5) -#define RT1718S_RT_INT6_INT_ADC_DONE BIT(0) - -#define RT1718S_RT_ST6 0xA4 -#define RT1718S_RT_ST6_BC12_SNK_DONE BIT(7) -#define RT1718S_RT_ST6_HVDCP_CHK_DONE BIT(6) -#define RT1718S_RT_ST6_BC12_TA_CHG BIT(5) - -#define RT1718S_PHYCTRL9 0xAC - -#define RT1718S_SYS_CTRL3 0xB0 -#define RT1718S_TCPC_CTRL1 0xB1 -#define RT1718S_TCPC_CTRL2 0xB2 -#define RT1718S_TCPC_CTRL3 0xB3 -#define RT1718S_SWRESET_MASK BIT(0) -#define RT1718S_TCPC_CTRL4 0xB4 -#define RT1718S_SYS_CTRL4 0xB8 -#define RT1718S_WATCHDOG_CTRL 0xBE -#define RT1718S_I2C_RST_CTRL 0xBF - -#define RT1718S_HILO_CTRL9 0xC8 -#define RT1718S_SHILED_CTRL1 0xCA -#define RT1718S_FRS_CTRL1 0xCB -#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK 0xF0 -#define RT1718S_FRS_CTRL2 0xCC -#define RT1718S_FRS_CTRL2_RX_FRS_EN BIT(6) -#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT BIT(4) -#define RT1718S_FRS_CTRL2_VBUS_FRS_EN BIT(3) -#define RT1718S_FRS_CTRL3 0xCE -#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 BIT(3) -#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1 BIT(2) - -#define RT1718S_DIS_SRC_VBUS_CTRL 0xE0 -#define RT1718S_ENA_SRC_VBUS_CTRL 0xE1 -#define RT1718S_FAULT_OC1_VBUS_CTRL 0xE3 -#define RT1718S_GPIO1_VBUS_CTRL 0xEA -#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS BIT(6) -#define RT1718S_GPIO2_VBUS_CTRL 0xEB -#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS BIT(6) -#define RT1718S_VBUS_CTRL_EN 0xEC -#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN BIT(7) -#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN BIT(6) - -#define RT1718S_GPIO_CTRL(n) (0xED + (n)) -#define RT1718S_GPIO_CTRL_PU BIT(5) -#define RT1718S_GPIO_CTRL_PD BIT(4) -#define RT1718S_GPIO_CTRL_OD_N BIT(3) -#define RT1718S_GPIO_CTRL_OE BIT(2) -#define RT1718S_GPIO_CTRL_O BIT(1) -#define RT1718S_GPIO_CTRL_I BIT(0) - -#define RT1718S_UNLOCK_PW_2 0xF0 -#define RT1718S_UNLOCK_PW_1 0xF1 - -#define RT1718S_RT2_SYS_CTRL5 0xF210 - -#define RT1718S_VBUS_VOL_TO_REG(_vol) (CLAMP(_vol, 5, 20) - 5) -#define RT1718S_VBUS_PCT_TO_REG(_pct) (CLAMP(_pct, 5, 20) \ - / 5 - 1) -#define RT1718S_RT2_VBUS_VOL_CTRL 0xF213 -#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL (BIT(5) | BIT(4)) -#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL 0x0F - -#define RT1718S_VCON_CTRL4 0xF211 -#define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5) -#define RT1718S_VCON_CTRL4_OCP_CP_EN BIT(4) - -#define RT1718S_RT2_VBUS_OCRC_EN 0xF214 -#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0) -#define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216 -#define RT1718S_RT2_VBUS_OCP_CTRL4 0xF219 - -#define RT1718S_RT2_SBU_CTRL_01 0xF23A -#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN BIT(7) -#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN BIT(6) -#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN BIT(3) -#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN BIT(2) -#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN BIT(1) -#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN BIT(0) - -#define RT1718S_RT2_BC12_SNK_FUNC 0xF260 -#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN BIT(7) -#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN BIT(6) -#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK 0x30 -#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE 0x00 -#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS 0x10 -#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS 0x20 -#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA 0x30 -#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT BIT(3) -#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL BIT(2) -#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS BIT(1) - -#define RT1718S_RT2_BC12_STAT 0xF261 -#define RT1718S_RT2_BC12_STAT_DCDT BIT(4) -#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK 0x0F -#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE 0x00 -#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP 0x0D -#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP 0x0E -#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP 0x0F - - -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET 0xF263 -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK 0x03 -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V 0x00 -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V 0x01 -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V 0x02 -#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V 0x03 - -#define RT1718S_RT2_BC12_SRC_FUNC 0xF26D -#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN BIT(7) -#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK 0x70 -#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP 0x00 -#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP 0x10 -#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP 0x20 -#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON BIT(0) - -#define RT1718S_ADC_CTRL_01 0xF2A0 -#define RT1718S_ADC_CTRL_02 0xF2A1 -#define RT1718S_ADC_CHX_VOL_L(ch) (0xF2A6 + (ch) * 2) -#define RT1718S_ADC_CHX_VOL_H(ch) (0xF2A7 + (ch) * 2) +#define RT1718S_I2C_ADDR1_FLAGS 0x43 +#define RT1718S_I2C_ADDR2_FLAGS 0x40 + +#define RT1718S_VID 0x29CF +#define RT1718S_PID 0x1718 + +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + +#define RT1718S_PHYCTRL1 0x80 +#define RT1718S_PHYCTRL2 0x81 +#define RT1718S_PHYCTRL3 0x82 +#define RT1718S_PHYCTRL7 0x86 +#define RT1718S_VCON_CTRL1 0x8A +#define RT1718S_VCON_CTRL3 0x8C +#define RT1718S_VCON_LIMIT_MODE BIT(0) +#define RT1718S_SYS_CTRL1 0x8F +#define RT1718S_SYS_CTRL1_TCPC_CONN_INVALID BIT(6) +#define RT1718S_SYS_CTRL1_SHIPPING_OFF BIT(5) +#define RT1718S_SYS_CTRL2 0x90 +#define RT1718S_SYS_CTRL2_BMCIO_OSC_EN BIT(0) +#define RT1718S_SYS_CTRL2_LPWR_EN BIT(3) + +#define RT1718S_VCONN_CONTROL_2 0x8B +#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 BIT(7) +#define RT1718S_VCONN_CONTROL_2_OVP_EN_CC2 BIT(6) +#define RT1718S_VCONN_CONTROL_2_RVP_EN BIT(3) +#define RT1718S_VCONN_CONTROL_3 0x8C +#define RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL GENMASK(7, 5) +#define RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG BIT(1) + +#define RT1718S_SYS_CTRL2 0x90 +#define RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN BIT(5) + +#define RT1718S_RT_MASK1 0x91 +#define RT1718S_RT_MASK1_M_VBUS_FRS_LOW BIT(7) +#define RT1718S_RT_MASK1_M_RX_FRS BIT(6) +#define RT1718S_RT_MASK2 0x92 +#define RT1718S_RT_MASK3 0x93 +#define RT1718S_RT_MASK4 0x94 +#define RT1718S_RT_MASK5 0x95 +#define RT1718S_RT_MASK6 0x96 +#define RT1718S_RT_MASK6_M_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_MASK6_M_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_MASK6_M_BC12_TA_CHG BIT(5) +#define RT1718S_RT_MASK7 0x97 + +#define RT1718S_RT_INT1 0x98 +#define RT1718S_RT_INT1_INT_VBUS_FRS_LOW BIT(7) +#define RT1718S_RT_INT1_INT_RX_FRS BIT(6) +#define RT1718S_RT_INT2 0x99 +#define RT1718S_RT_INT6 0x9D +#define RT1718S_RT_INT6_INT_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_INT6_INT_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_INT6_INT_BC12_TA_CHG BIT(5) +#define RT1718S_RT_INT6_INT_ADC_DONE BIT(0) + +#define RT1718S_RT_ST6 0xA4 +#define RT1718S_RT_ST6_BC12_SNK_DONE BIT(7) +#define RT1718S_RT_ST6_HVDCP_CHK_DONE BIT(6) +#define RT1718S_RT_ST6_BC12_TA_CHG BIT(5) + +#define RT1718S_PHYCTRL9 0xAC + +#define RT1718S_SYS_CTRL3 0xB0 +#define RT1718S_TCPC_CTRL1 0xB1 +#define RT1718S_TCPC_CTRL2 0xB2 +#define RT1718S_TCPC_CTRL3 0xB3 +#define RT1718S_SWRESET_MASK BIT(0) +#define RT1718S_TCPC_CTRL4 0xB4 +#define RT1718S_SYS_CTRL4 0xB8 +#define RT1718S_WATCHDOG_CTRL 0xBE +#define RT1718S_I2C_RST_CTRL 0xBF + +#define RT1718S_HILO_CTRL9 0xC8 +#define RT1718S_SHILED_CTRL1 0xCA +#define RT1718S_FRS_CTRL1 0xCB +#define RT1718S_FRS_CTRL1_FRSWAPRX_MASK 0xF0 +#define RT1718S_FRS_CTRL2 0xCC +#define RT1718S_FRS_CTRL2_RX_FRS_EN BIT(6) +#define RT1718S_FRS_CTRL2_FR_VBUS_SELECT BIT(4) +#define RT1718S_FRS_CTRL2_VBUS_FRS_EN BIT(3) +#define RT1718S_FRS_CTRL3 0xCE +#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO2 BIT(3) +#define RT1718S_FRS_CTRL3_FRS_RX_WAIT_GPIO1 BIT(2) + +#define RT1718S_DIS_SRC_VBUS_CTRL 0xE0 +#define RT1718S_ENA_SRC_VBUS_CTRL 0xE1 +#define RT1718S_FAULT_OC1_VBUS_CTRL 0xE3 +#define RT1718S_GPIO1_VBUS_CTRL 0xEA +#define RT1718S_GPIO1_VBUS_CTRL_FRS_RX_VBUS BIT(6) +#define RT1718S_GPIO2_VBUS_CTRL 0xEB +#define RT1718S_GPIO2_VBUS_CTRL_FRS_RX_VBUS BIT(6) +#define RT1718S_VBUS_CTRL_EN 0xEC +#define RT1718S_VBUS_CTRL_EN_GPIO2_VBUS_PATH_EN BIT(7) +#define RT1718S_VBUS_CTRL_EN_GPIO1_VBUS_PATH_EN BIT(6) + +#define RT1718S_GPIO_CTRL(n) (0xED + (n)) +#define RT1718S_GPIO_CTRL_PU BIT(5) +#define RT1718S_GPIO_CTRL_PD BIT(4) +#define RT1718S_GPIO_CTRL_OD_N BIT(3) +#define RT1718S_GPIO_CTRL_OE BIT(2) +#define RT1718S_GPIO_CTRL_O BIT(1) +#define RT1718S_GPIO_CTRL_I BIT(0) + +#define RT1718S_UNLOCK_PW_2 0xF0 +#define RT1718S_UNLOCK_PW_1 0xF1 + +#define RT1718S_RT2_SYS_CTRL5 0xF210 + +#define RT1718S_VBUS_VOL_TO_REG(_vol) (CLAMP(_vol, 5, 20) - 5) +#define RT1718S_VBUS_PCT_TO_REG(_pct) (CLAMP(_pct, 5, 20) / 5 - 1) +#define RT1718S_RT2_VBUS_VOL_CTRL 0xF213 +#define RT1718S_RT2_VBUS_VOL_CTRL_OVP_SEL (BIT(5) | BIT(4)) +#define RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL 0x0F + +#define RT1718S_VCON_CTRL4 0xF211 +#define RT1718S_VCON_CTRL4_UVP_CP_EN BIT(5) +#define RT1718S_VCON_CTRL4_OCP_CP_EN BIT(4) + +#define RT1718S_RT2_VBUS_OCRC_EN 0xF214 +#define RT1718S_RT2_VBUS_OCRC_EN_VBUS_OCP1_EN BIT(0) +#define RT1718S_RT2_VBUS_OCP_CTRL1 0xF216 +#define RT1718S_RT2_VBUS_OCP_CTRL4 0xF219 + +#define RT1718S_RT2_SBU_CTRL_01 0xF23A +#define RT1718S_RT2_SBU_CTRL_01_SBU_VIEN BIT(7) +#define RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN BIT(6) +#define RT1718S_RT2_SBU_CTRL_01_SBU2_SWEN BIT(3) +#define RT1718S_RT2_SBU_CTRL_01_SBU1_SWEN BIT(2) +#define RT1718S_RT2_SBU_CTRL_01_DM_SWEN BIT(1) +#define RT1718S_RT2_SBU_CTRL_01_DP_SWEN BIT(0) + +#define RT1718S_RT2_BC12_SNK_FUNC 0xF260 +#define RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN BIT(7) +#define RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN BIT(6) +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK 0x30 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_DISABLE 0x00 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_300MS 0x10 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS 0x20 +#define RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_WAIT_DATA 0x30 +#define RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT BIT(3) +#define RT1718S_RT2_BC12_SNK_FUNC_VPORT_SEL BIT(2) +#define RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS BIT(1) + +#define RT1718S_RT2_BC12_STAT 0xF261 +#define RT1718S_RT2_BC12_STAT_DCDT BIT(4) +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_MASK 0x0F +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_NONE 0x00 +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_SDP 0x0D +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_CDP 0x0E +#define RT1718S_RT2_BC12_STAT_PORT_STATUS_DCP 0x0F + +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET 0xF263 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK 0x03 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_55V 0x00 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_60V 0x01 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V 0x02 +#define RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_70V 0x03 + +#define RT1718S_RT2_BC12_SRC_FUNC 0xF26D +#define RT1718S_RT2_BC12_SRC_FUNC_BC12_SRC_EN BIT(7) +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_MASK 0x70 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_SDP 0x00 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_CDP 0x10 +#define RT1718S_RT2_BC12_SRC_FUNC_SRC_MODE_SEL_BC12_DCP 0x20 +#define RT1718S_RT2_BC12_SRC_FUNC_WAIT_VBUS_ON BIT(0) + +#define RT1718S_ADC_CTRL_01 0xF2A0 +#define RT1718S_ADC_CTRL_02 0xF2A1 +#define RT1718S_ADC_CHX_VOL_L(ch) (0xF2A6 + (ch)*2) +#define RT1718S_ADC_CHX_VOL_H(ch) (0xF2A7 + (ch)*2) extern const struct tcpm_drv rt1718s_tcpm_drv; extern const struct bc12_drv rt1718s_bc12_drv; @@ -256,7 +254,6 @@ int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal); */ int rt1718s_set_frs_enable(int port, int enable); - /** * Board override for fast role swap. * -- cgit v1.2.1 From d436ac69bce0107d371365878dc5b664796702d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:17 -0600 Subject: test/usb_pe_drp_old.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb22e757e84822a51859ece8eb12e098dd17c6ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730544 Reviewed-by: Jeremy Bettis --- test/usb_pe_drp_old.c | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/test/usb_pe_drp_old.c b/test/usb_pe_drp_old.c index 1954ae065b..c45c9b7033 100644 --- a/test/usb_pe_drp_old.c +++ b/test/usb_pe_drp_old.c @@ -21,9 +21,9 @@ #include "usb_tc_sm.h" #include "mock/usb_prl_mock.h" -#define pe_set_flag(_p, name) pe_set_fn((_p), (name ## _FN)) -#define pe_clr_flag(_p, name) pe_clr_fn((_p), (name ## _FN)) -#define pe_chk_flag(_p, name) pe_chk_fn((_p), (name ## _FN)) +#define pe_set_flag(_p, name) pe_set_fn((_p), (name##_FN)) +#define pe_clr_flag(_p, name) pe_clr_fn((_p), (name##_FN)) +#define pe_chk_flag(_p, name) pe_chk_fn((_p), (name##_FN)) /** * STUB Section @@ -77,12 +77,10 @@ bool pd_alt_mode_capable(int port) void pd_set_suspend(int port, int suspend) { - } void pd_set_error_recovery(int port) { - } test_static void setup_source(void) @@ -219,8 +217,8 @@ static int test_snk_give_source_cap(void) TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED)); TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE)); - TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0), - PD_DATA_SOURCE_CAP, "%d"); + TEST_EQ(mock_prl_get_last_sent_data_msg(PORT0), PD_DATA_SOURCE_CAP, + "%d"); TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d"); pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); @@ -249,9 +247,9 @@ test_static int test_extended_message_not_supported(void) * Receive an extended, non-chunked message; expect a Not Supported * response. */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -261,16 +259,16 @@ test_static int test_extended_message_not_supported(void) pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* * Receive an extended, chunked, single-chunk message; expect a Not * Supported response. */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -280,16 +278,16 @@ test_static int test_extended_message_not_supported(void) pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* * Receive an extended, chunked, multi-chunk message; expect a Not * Supported response after tChunkingNotSupported (not earlier). */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -301,13 +299,13 @@ test_static int test_extended_message_not_supported(void) */ task_wait_event(10 * MSEC); TEST_NE(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED); pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* @@ -408,8 +406,8 @@ static int test_send_caps_error(void) pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION); set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES); task_wait_event(10 * MSEC); - TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), - PD_CTRL_SOFT_RESET, "%d"); + TEST_EQ(mock_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET, + "%d"); TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d"); return EC_SUCCESS; -- cgit v1.2.1 From c97000ce0e82a0e4323fccba94eeed2770b61ade Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:17 -0600 Subject: board/volmar/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If38addf5747cbe07cc62e17fc540aab7e179b73e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729089 Reviewed-by: Jeremy Bettis --- board/volmar/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/volmar/usbc_config.h b/board/volmar/usbc_config.h index 69300a9354..73344d4f9e 100644 --- a/board/volmar/usbc_config.h +++ b/board/volmar/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From 47feaf9dba459c675931388fa496a69944a0eb0e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:55 -0600 Subject: chip/npcx/gpio-npcx7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie7cd0150e83d45d4e89675263b6ff8d7bd6463ff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729393 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio-npcx7.c | 201 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 200 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/npcx/gpio-npcx7.c diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c deleted file mode 120000 index 39b939f44c..0000000000 --- a/chip/npcx/gpio-npcx7.c +++ /dev/null @@ -1 +0,0 @@ -gpio-npcx5.c \ No newline at end of file diff --git a/chip/npcx/gpio-npcx7.c b/chip/npcx/gpio-npcx7.c new file mode 100644 index 0000000000..e2f3bb0b60 --- /dev/null +++ b/chip/npcx/gpio-npcx7.c @@ -0,0 +1,200 @@ +/* Copyright 2020 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* GPIO module for Chrome EC */ + +#include "clock.h" +#include "common.h" +#include "ec_commands.h" +#include "gpio_chip.h" +#include "hooks.h" +#include "host_command.h" +#include "lpc_chip.h" +#include "registers.h" +#include "task.h" + +/* + * List of GPIO IRQs to enable. Don't automatically enable interrupts for + * the keyboard input GPIO bank - that's handled separately. Of course the + * bank is different for different systems. + */ +static void gpio_init(void) +{ + /* Enable IRQs now that pins are set up */ + task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0); + task_enable_irq(NPCX_IRQ_WKINTEFGH_0); + task_enable_irq(NPCX_IRQ_WKINTC_0); + task_enable_irq(NPCX_IRQ_TWD_WKINTB_0); + task_enable_irq(NPCX_IRQ_WKINTA_1); + task_enable_irq(NPCX_IRQ_WKINTB_1); +#ifdef NPCX_SELECT_KSI_TO_GPIO + task_enable_irq(NPCX_IRQ_KSI_WKINTC_1); +#endif + task_enable_irq(NPCX_IRQ_WKINTD_1); + task_enable_irq(NPCX_IRQ_WKINTE_1); + task_enable_irq(NPCX_IRQ_WKINTF_1); + task_enable_irq(NPCX_IRQ_WKINTG_1); + task_enable_irq(NPCX_IRQ_WKINTH_1); +#if defined(CHIP_FAMILY_NPCX7) + task_enable_irq(NPCX_IRQ_WKINTFG_2); +#endif +} +DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); + +/** + * Handlers for each GPIO port. These read and clear the interrupt bits for + * the port, then call the master handler above. + */ + +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } + +/* If we need to handle the other type interrupts except GPIO, add code here */ +static void __gpio_wk0efgh_interrupt(void) +{ + if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { + /* Pending bit 7 or 6 or 5? */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + /* Disable host wake-up */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); + /* Clear pending bit of WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6); + return; + } + if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { + espi_espirst_handler(); + return; + } + } else { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { + lpc_lreset_pltrst_handler(); + return; + } + } + } + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_5)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_6)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_7)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_8)); +} + +#ifdef CONFIG_HOSTCMD_RTC +static void set_rtc_host_event(void) +{ + host_set_single_event(EC_HOST_EVENT_RTC); +} +DECLARE_DEFERRED(set_rtc_host_event); +#endif + +static void __gpio_rtc_interrupt(void) +{ + /* Check pending bit 7 */ +#ifdef CONFIG_HOSTCMD_RTC + if (NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_4) & 0x80) { + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_4), 7); + hook_call_deferred(&set_rtc_host_event_data, 0); + return; + } +#endif +#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \ + (CONFIG_CONSOLE_UART == 1) + /* Handle the interrupt from UART wakeup event */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_1), 6)) { + /* + * Disable WKEN bit to avoid the other unnecessary interrupts + * from the coming data bits after the start bit. (Pending bit + * of CR_SIN is set when a high-to-low transaction occurs.) + */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_1), 6); + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_1), 6); + /* Notify the clock module that the console is in use. */ + clock_refresh_console_in_use(); + return; + } +#endif + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1)); + gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4)); +} + +static void __gpio_wk1h_interrupt(void) +{ +#if defined(CHIP_FAMILY_NPCX7) && defined(CONFIG_LOW_POWER_IDLE) && \ + (CONFIG_CONSOLE_UART == 0) + /* Handle the interrupt from UART wakeup event */ + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_1, MIWU_GROUP_8), 7)) { + /* + * Disable WKEN bit to avoid the other unnecessary interrupts + * from the coming data bits after the start bit. (Pending bit + * of CR_SIN is set when a high-to-low transaction occurs.) + */ + CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Clear pending bit for WUI */ + SET_BIT(NPCX_WKPCL(MIWU_TABLE_1, MIWU_GROUP_8), 7); + /* Notify the clock module that the console is in use. */ + clock_refresh_console_in_use(); + } else +#endif + gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8)); +} + +GPIO_IRQ_FUNC(__gpio_wk0b_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_2)); +GPIO_IRQ_FUNC(__gpio_wk0c_interrupt, WUI_INT(MIWU_TABLE_0, MIWU_GROUP_3)); +GPIO_IRQ_FUNC(__gpio_wk1a_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_1)); +GPIO_IRQ_FUNC(__gpio_wk1b_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_2)); +#ifdef NPCX_SELECT_KSI_TO_GPIO +/* Declare GPIO irq functions for KSI pins if there's no keyboard scan task, */ +GPIO_IRQ_FUNC(__gpio_wk1c_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_3)); +#endif +GPIO_IRQ_FUNC(__gpio_wk1d_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_4)); +GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5)); +GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); +GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); +#if defined(CHIP_FAMILY_NPCX7) +GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); +#endif + +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +#ifdef NPCX_SELECT_KSI_TO_GPIO +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +#endif +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +#ifdef CONFIG_HOST_INTERFACE_SHI +/* + * HACK: Make CS GPIO P2 to improve SHI reliability. + * TODO: Increase CS-assertion-to-transaction-start delay on host to + * accommodate P3 CS interrupt. + */ +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +#else +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +#endif +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +#if defined(CHIP_FAMILY_NPCX7) +DECLARE_IRQ(NPCX_IRQ_WKINTFG_2, __gpio_wk2fg_interrupt, 3); +#endif + +#undef GPIO_IRQ_FUNC -- cgit v1.2.1 From 6101f1708733f674acb65c0b64b9f62710427053 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:55 -0600 Subject: board/coachz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff1a4de95219581c794868cd2f63d35252001d6a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728167 Reviewed-by: Jeremy Bettis --- board/coachz/board.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/coachz/board.h b/board/coachz/board.h index e1e2d94545..ff404855ed 100644 --- a/board/coachz/board.h +++ b/board/coachz/board.h @@ -12,7 +12,7 @@ /* On-body detection */ #define CONFIG_BODY_DETECTION -#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL +#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */ #define CONFIG_GESTURE_DETECTION #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR) @@ -21,7 +21,7 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Save some flash space */ #define CONFIG_LTO @@ -34,7 +34,7 @@ #undef CONFIG_CMD_TASK_RESET /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -101,10 +101,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 664700ea59a7b37744043621e49abf17cd65ccce Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Wed, 29 Jun 2022 10:08:52 +0800 Subject: osiris: Support second fan control Added second fan configuration BUG=b:234545460 BRANCH=none TEST=ectool pwmsetfanrpm <0|1> TEST=ectool pwmgetfanrpm <0|1> Signed-off-by: Yu-An Chen Change-Id: I0fa24371b757382b12ed401789326f2339f0a2ef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733931 Reviewed-by: Boris Mittelberg Commit-Queue: Boris Mittelberg --- board/osiris/board.h | 6 ++++-- board/osiris/fans.c | 22 ++++++++++++++++++++++ board/osiris/gpio.inc | 1 + board/osiris/pwm.c | 26 +++++--------------------- 4 files changed, 32 insertions(+), 23 deletions(-) diff --git a/board/osiris/board.h b/board/osiris/board.h index ffa8995389..aee05b025e 100644 --- a/board/osiris/board.h +++ b/board/osiris/board.h @@ -172,18 +172,20 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_FAN = 0, /* PWM5 */ + PWM_CH_FAN2, /* PWM3 */ PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, + FAN_CH_1, FAN_CH_COUNT }; enum mft_channel { MFT_CH_0 = 0, + MFT_CH_1, MFT_CH_COUNT }; diff --git a/board/osiris/fans.c b/board/osiris/fans.c index 44c70265b1..4b7ae45598 100644 --- a/board/osiris/fans.c +++ b/board/osiris/fans.c @@ -20,6 +20,11 @@ const struct mft_t mft_channels[] = { .clk_src = TCKC_LFCLK, .pwm_id = PWM_CH_FAN, }, + [MFT_CH_1] = { + .module = NPCX_MFT_MODULE_2, + .clk_src = TCKC_LFCLK, + .pwm_id = PWM_CH_FAN2, + }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -30,6 +35,13 @@ static const struct fan_conf fan_conf_0 = { .enable_gpio = GPIO_EN_PP5000_FAN, }; +static const struct fan_conf fan_conf_1 = { + .flags = FAN_USE_RPM_MODE, + .ch = MFT_CH_1, /* Use MFT id to control fan */ + .pgood_gpio = -1, + .enable_gpio = GPIO_EN_PP5000_FAN, +}; + /* * TODO(b/234545460): thermistor placement and calibration * @@ -43,9 +55,19 @@ static const struct fan_rpm fan_rpm_0 = { .rpm_max = 6000, }; +static const struct fan_rpm fan_rpm_1 = { + .rpm_min = 3000, + .rpm_start = 3000, + .rpm_max = 6000, +}; + const struct fan_t fans[FAN_CH_COUNT] = { [FAN_CH_0] = { .conf = &fan_conf_0, .rpm = &fan_rpm_0, }, + [FAN_CH_1] = { + .conf = &fan_conf_1, + .rpm = &fan_rpm_1, + }, }; diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc index ca22ddba08..32d75fa81b 100644 --- a/board/osiris/gpio.inc +++ b/board/osiris/gpio.inc @@ -92,6 +92,7 @@ ALTERNATE(PIN_MASK(F, 0x0c), 0, MODULE_I2C, 0) /* GPIOF3/I2C4_SCL1 /* PWM alternate functions */ ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0) /* GPIO40/TA1 */ +ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0) /* GPIO73/TA2 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* GPIO80/PWM3 */ ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* GPIOB7/PWM5 */ diff --git a/board/osiris/pwm.c b/board/osiris/pwm.c index 530a777a8f..803c8b0126 100644 --- a/board/osiris/pwm.c +++ b/board/osiris/pwm.c @@ -11,31 +11,15 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 3, - .flags = 0, - /* - * Set PWM frequency to multiple of 50 Hz and 60 Hz to prevent - * flicker. Higher frequencies consume similar average power to - * lower PWM frequencies, but higher frequencies record a much - * lower maximum power. - */ - .freq = 25000, - }, [PWM_CH_FAN] = { .channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, .freq = 25000 }, + [PWM_CH_FAN2] = { + .channel = 3, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 + }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); - -static void board_pwm_init(void) -{ - /* - * Turn on the fan at 50%. - */ - pwm_enable(PWM_CH_KBLIGHT, 1); - pwm_set_duty(PWM_CH_KBLIGHT, 50); -} -DECLARE_HOOK(HOOK_INIT, board_pwm_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 66bed46e6e3923bd6157349d979c00c0b94b9d52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:41 -0600 Subject: test/motion_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I65119c05789edad8c6fbae219dc074a2deaa8aa2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730528 Reviewed-by: Jeremy Bettis --- test/motion_common.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/test/motion_common.h b/test/motion_common.h index 45d856d9ef..313c95bfae 100644 --- a/test/motion_common.h +++ b/test/motion_common.h @@ -13,7 +13,7 @@ * The task will read the vectors at that interval */ #define TEST_LID_EC_RATE (1 * MSEC) -#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE) /* mHz */ +#define TEST_LID_FREQUENCY (1e9 / TEST_LID_EC_RATE) /* mHz */ /* * Time in ms to wait for the task to read the vectors. @@ -30,7 +30,8 @@ extern const unsigned int motion_sensor_count; void wait_for_valid_sample(void); void feed_accel_data(const float *array, int *idx, - int (filler)(const struct motion_sensor_t *s, const float f)); + int(filler)(const struct motion_sensor_t *s, + const float f)); /* * External data - from @@ -65,4 +66,4 @@ extern const float kAccelerometerVerticalHingeTestData[]; extern const size_t kAccelerometerVerticalHingeTestDataLength; extern const float kAccelerometerVerticalHingeUnstableTestData[]; extern const size_t kAccelerometerVerticalHingeUnstableTestDataLength; -#endif /* __CROS_EC_MOTION_COMMON_H */ +#endif /* __CROS_EC_MOTION_COMMON_H */ -- cgit v1.2.1 From a200ef3f964cc31fc44a9361c5b4c527b7021174 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:12 -0600 Subject: driver/retimer/anx7491.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib80da6708a5061803efc40e06d19ff20cf868d03 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730040 Reviewed-by: Jeremy Bettis --- driver/retimer/anx7491.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/driver/retimer/anx7491.h b/driver/retimer/anx7491.h index 045cf9f411..da2461564b 100644 --- a/driver/retimer/anx7491.h +++ b/driver/retimer/anx7491.h @@ -9,9 +9,9 @@ #define __CROS_EC_USB_RETIMER_ANX7491_H /* I2C interface addresses */ -#define ANX7491_I2C_ADDR0_FLAGS 0x10 -#define ANX7491_I2C_ADDR1_FLAGS 0x14 -#define ANX7491_I2C_ADDR2_FLAGS 0x16 -#define ANX7491_I2C_ADDR3_FLAGS 0x11 +#define ANX7491_I2C_ADDR0_FLAGS 0x10 +#define ANX7491_I2C_ADDR1_FLAGS 0x14 +#define ANX7491_I2C_ADDR2_FLAGS 0x16 +#define ANX7491_I2C_ADDR3_FLAGS 0x11 #endif /* __CROS_EC_USB_RETIMER_ANX7491_H */ -- cgit v1.2.1 From 008aabb956faa178acd0d75a465979c990d65e58 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:21 -0600 Subject: common/dps.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iebab9e7635dd66ad3af68be2dce5fd69fec6b7dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729604 Reviewed-by: Jeremy Bettis --- common/dps.c | 54 +++++++++++++++++++++++------------------------------- 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/common/dps.c b/common/dps.c index 3af25e6280..22934b56f8 100644 --- a/common/dps.c +++ b/common/dps.c @@ -25,7 +25,6 @@ #include "util.h" #include "usb_pe_sm.h" - #define K_MORE_PWR 96 #define K_LESS_PWR 93 #define K_SAMPLE 1 @@ -33,17 +32,16 @@ #define T_REQUEST_STABLE_TIME (10 * SECOND) #define T_NEXT_CHECK_TIME (5 * SECOND) -#define DPS_FLAG_DISABLED BIT(0) -#define DPS_FLAG_NO_SRCCAP BIT(1) -#define DPS_FLAG_WAITING BIT(2) -#define DPS_FLAG_SAMPLED BIT(3) -#define DPS_FLAG_NEED_MORE_PWR BIT(4) +#define DPS_FLAG_DISABLED BIT(0) +#define DPS_FLAG_NO_SRCCAP BIT(1) +#define DPS_FLAG_WAITING BIT(2) +#define DPS_FLAG_SAMPLED BIT(3) +#define DPS_FLAG_NEED_MORE_PWR BIT(4) -#define DPS_FLAG_STOP_EVENTS (DPS_FLAG_DISABLED | \ - DPS_FLAG_NO_SRCCAP) -#define DPS_FLAG_ALL GENMASK(31, 0) +#define DPS_FLAG_STOP_EVENTS (DPS_FLAG_DISABLED | DPS_FLAG_NO_SRCCAP) +#define DPS_FLAG_ALL GENMASK(31, 0) -#define MAX_MOVING_AVG_WINDOW 5 +#define MAX_MOVING_AVG_WINDOW 5 BUILD_ASSERT(K_MORE_PWR > K_LESS_PWR && 100 >= K_MORE_PWR && 100 >= K_LESS_PWR); @@ -135,8 +133,7 @@ static void dps_init(void) CPRINTS("ERR:WIN"); } - if (dps_config.k_less_pwr > 100 || - dps_config.k_more_pwr > 100 || + if (dps_config.k_less_pwr > 100 || dps_config.k_more_pwr > 100 || dps_config.k_more_pwr <= dps_config.k_less_pwr) { dps_config.k_less_pwr = K_LESS_PWR; dps_config.k_more_pwr = K_MORE_PWR; @@ -258,16 +255,16 @@ struct pdo_candidate { }; #define UPDATE_CANDIDATE(new_port, new_mv, new_mw) \ - do { \ - cand->port = new_port; \ - cand->mv = new_mv; \ - cand->mw = new_mw; \ + do { \ + cand->port = new_port; \ + cand->mv = new_mv; \ + cand->mw = new_mw; \ } while (0) -#define CLEAR_AND_RETURN() \ - do { \ +#define CLEAR_AND_RETURN() \ + do { \ moving_avg_count = 0; \ - return false; \ + return false; \ } while (0) /* @@ -360,7 +357,7 @@ static bool has_new_power_request(struct pdo_candidate *cand) input_curr, input_pwr_avg, input_curr_avg); for (int i = 0; i < board_get_usb_pd_port_count(); ++i) { - const uint32_t * const src_caps = pd_get_src_caps(i); + const uint32_t *const src_caps = pd_get_src_caps(i); /* If the port is not SNK, skip evaluating this port. */ if (pd_get_power_role(i) != PD_ROLE_SINK) @@ -419,7 +416,6 @@ static bool has_new_power_request(struct pdo_candidate *cand) } } - /* * if the candidate is the same as the current one, pick * the one at active charge port. @@ -454,14 +450,14 @@ void dps_update_stabilized_time(int port) void dps_task(void *u) { - struct pdo_candidate last_cand = {CHARGE_PORT_NONE, 0, 0}; + struct pdo_candidate last_cand = { CHARGE_PORT_NONE, 0, 0 }; int sample_count = 0; dps_init(); update_timeout(dps_config.t_check); while (1) { - struct pdo_candidate curr_cand = {CHARGE_PORT_NONE, 0, 0}; + struct pdo_candidate curr_cand = { CHARGE_PORT_NONE, 0, 0 }; timestamp_t now; now = get_time(); @@ -505,8 +501,7 @@ void dps_task(void *u) if (sample_count == dps_config.k_sample) { dynamic_mv = curr_cand.mv; dps_port = curr_cand.port; - pd_dpm_request(dps_port, - DPM_REQUEST_NEW_POWER_LEVEL); + pd_dpm_request(dps_port, DPM_REQUEST_NEW_POWER_LEVEL); sample_count = 0; flag &= ~(DPS_FLAG_SAMPLED | DPS_FLAG_NEED_MORE_PWR); } @@ -557,10 +552,8 @@ static int command_dps(int argc, char **argv) "Efficient: %dmV\n" "Batt: %dmv\n" "PDMaxMV: %dmV\n", - port, last_mv, last_ma, - vbus, input_curr, input_pwr, - get_efficient_voltage(), - batt_mv, + port, last_mv, last_ma, vbus, input_curr, input_pwr, + get_efficient_voltage(), batt_mv, pd_get_max_voltage()); return EC_SUCCESS; } @@ -657,6 +650,5 @@ static enum ec_status hc_usb_pd_dps_control(struct host_cmd_handler_args *args) dps_enable(p->enable); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DPS_CONTROL, - hc_usb_pd_dps_control, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_DPS_CONTROL, hc_usb_pd_dps_control, EC_VER_MASK(0)); -- cgit v1.2.1 From 09c0c08091103862bf5c5f9cce1a6840f5d5ab30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:13 -0600 Subject: chip/stm32/registers-stm32f3.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib36a226ce1f8e4e9cf3debc797c845f6c91caeac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729528 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f3.h | 1431 ++++++++++++++++++++-------------------- 1 file changed, 710 insertions(+), 721 deletions(-) diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h index b7e3cfc8af..30eefb7ce0 100644 --- a/chip/stm32/registers-stm32f3.h +++ b/chip/stm32/registers-stm32f3.h @@ -19,473 +19,467 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 #ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_USB_HP 74 -#define STM32_IRQ_USB_LP 75 +#define STM32_IRQ_USB_HP 74 +#define STM32_IRQ_USB_LP 75 #else -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 #endif -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ #ifdef CHIP_VARIANT_STM32F373 -#define STM32_IRQ_COMP 64 +#define STM32_IRQ_COMP 64 #else -#define STM32_IRQ_COMP 22 +#define STM32_IRQ_COMP 22 #endif -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_COMP_BASE 0x40010000 +#define STM32_COMP_BASE 0x40010000 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_DBGMCU_BASE 0xE0042000 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_FLASH_REGS_BASE 0x40022000 +#define STM32_FLASH_REGS_BASE 0x40022000 -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000C00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ +#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_OPTB_BASE 0x1FFFF800 +#define STM32_OPTB_BASE 0x1FFFF800 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RCC_BASE 0x40021000 +#define STM32_RCC_BASE 0x40021000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_PWR_CSR_EWUP1 BIT(8) +#define STM32_PWR_CSR_EWUP2 BIT(9) +#define STM32_PWR_CSR_EWUP3 BIT(10) +#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ + +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ +#define STM32_CRS_CR_SYNCOKIE BIT(0) +#define STM32_CRS_CR_SYNCWARNIE BIT(1) +#define STM32_CRS_CR_ERRIE BIT(2) +#define STM32_CRS_CR_ESYNCIE BIT(3) +#define STM32_CRS_CR_CEN BIT(5) +#define STM32_CRS_CR_AUTOTRIMEN BIT(6) +#define STM32_CRS_CR_SWSYNC BIT(7) +#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8) + +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ +#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0) +#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16) +#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24) +#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28) +#define STM32_CRS_CFGR_SYNCPOL BIT(31) + +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ +#define STM32_CRS_ISR_SYNCOKF BIT(0) +#define STM32_CRS_ISR_SYNCWARNF BIT(1) +#define STM32_CRS_ISR_ERRF BIT(2) +#define STM32_CRS_ISR_ESYNCF BIT(3) +#define STM32_CRS_ISR_SYNCERR BIT(8) +#define STM32_CRS_ISR_SYNCMISS BIT(9) +#define STM32_CRS_ISR_TRIMOVF BIT(10) +#define STM32_CRS_ISR_FEDIR BIT(15) +#define STM32_CRS_ISR_FECAP (0xffff << 16) + +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ +#define STM32_CRS_ICR_SYNCOKC BIT(0) +#define STM32_CRS_ICR_SYNCWARINC BIT(1) +#define STM32_CRS_ICR_ERRC BIT(2) +#define STM32_CRS_ICR_ESYNCC BIT(3) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ +#define STM32_RCC_APB2ENR_TIM16EN BIT(17) +#define STM32_RCC_APB2ENR_TIM17EN BIT(18) +#define STM32_RCC_DBGMCUEN BIT(22) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) /* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) +#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ +#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ -#define STM32_RCC_HB_DMA1 BIT(0) +#define STM32_RCC_HB_DMA1 BIT(0) /* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - +#define STM32_RCC_HB_DMA2 BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ +#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ +#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ +#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ +#define STM32_RCC_PB1_USB BIT(23) +#define STM32_RCC_PB1_CRS BIT(27) + +#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 64 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 64 /* --- SPI --- */ @@ -502,8 +496,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -513,125 +507,124 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(4) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB + +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 +#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_PGERR BIT(2) +#define FLASH_SR_WRPRTERR BIT(4) +#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) +#define FLASH_SR_EOP BIT(5) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_OPTPG BIT(4) +#define FLASH_CR_OPTER BIT(5) +#define FLASH_CR_STRT BIT(6) +#define FLASH_CR_LOCK BIT(7) +#define FLASH_CR_OPTWRE BIT(9) +#define FLASH_CR_OBL_LAUNCH BIT(13) +#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) +#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_OBR_RDP_MASK (3 << 1) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WRP01 0x08 +#define STM32_OPTB_WRP23 0x0c + +#define STM32_OPTB_COMPL_SHIFT 8 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ #ifdef CHIP_VARIANT_STM32F373 -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) #endif /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) +#define STM32_COMP_CMP2LOCK BIT(31) +#define STM32_COMP_CMP2OUT BIT(30) +#define STM32_COMP_CMP2HYST_HI (3 << 28) +#define STM32_COMP_CMP2HYST_MED (2 << 28) +#define STM32_COMP_CMP2HYST_LOW (1 << 28) +#define STM32_COMP_CMP2HYST_NO (0 << 28) +#define STM32_COMP_CMP2POL BIT(27) #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) @@ -646,32 +639,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) #endif -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) +#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) +#define STM32_COMP_WNDWEN BIT(23) + +#define STM32_COMP_CMP2INSEL_MASK (7 << 20) +#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ +#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) +#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) +#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) +#define STM32_COMP_CMP2INSEL_VREF (3 << 20) +#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) +#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) +#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) + +#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) +#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) +#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) +#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) +#define STM32_COMP_CMP2EN BIT(16) + +#define STM32_COMP_CMP1LOCK BIT(15) +#define STM32_COMP_CMP1OUT BIT(14) +#define STM32_COMP_CMP1HYST_HI (3 << 12) +#define STM32_COMP_CMP1HYST_MED (2 << 12) +#define STM32_COMP_CMP1HYST_LOW (1 << 12) +#define STM32_COMP_CMP1HYST_NO (0 << 12) +#define STM32_COMP_CMP1POL BIT(11) #ifdef CHIP_VARIANT_STM32F373 #define STM32_COMP_CMP1OUTSEL_TIM5_OCR (7 << 8) @@ -690,25 +683,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) #endif -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - +#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) + +#define STM32_COMP_CMP1INSEL_MASK (7 << 4) +#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ +#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) +#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) +#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) +#define STM32_COMP_CMP1INSEL_VREF (3 << 4) +#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) +#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) +#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) + +#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) +#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) +#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) +#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) +#define STM32_COMP_CMP1SW1 BIT(1) +#define STM32_COMP_CMP1EN BIT(0) /* --- DMA --- */ @@ -779,11 +771,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -794,8 +786,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -804,179 +796,177 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) +#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) + +#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) + +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) + +#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) + +#define STM32_USB_ISTR_EP_ID_MASK (0x000f) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) + +#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) + +#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) +#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) +#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) +#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) + +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -986,28 +976,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 62a0a0746bf9267286aa8634156e6933dcc1e19d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:56 -0600 Subject: board/spherion/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95b14e7d6a15a75fc612bd4177992148f3f431b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728944 Reviewed-by: Jeremy Bettis --- board/spherion/battery.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/spherion/battery.c b/board/spherion/battery.c index 3613a4750c..395acace08 100644 --- a/board/spherion/battery.c +++ b/board/spherion/battery.c @@ -88,11 +88,12 @@ int charger_profile_override(struct charge_state_data *curr) temp_sensor_read(TEMP_SENSOR_CHARGER, &charger_temp); charger_temp_c = K_TO_C(charger_temp); if (charger_temp_c > 52) - curr->requested_current = MIN(curr->requested_current, - 2200); + curr->requested_current = + MIN(curr->requested_current, 2200); else if (charger_temp_c > 48) - curr->requested_current = MIN(curr->requested_current, - CONFIG_CHARGER_MAX_INPUT_CURRENT); + curr->requested_current = + MIN(curr->requested_current, + CONFIG_CHARGER_MAX_INPUT_CURRENT); } return 0; -- cgit v1.2.1 From 192072ce23a0dfd31a2f596e10dbb5cecc9217c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:59 -0600 Subject: board/blipper/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie55cd45bfe53efa5acb34f76eed796bf1572a28e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728057 Reviewed-by: Jeremy Bettis --- board/blipper/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/blipper/cbi_ssfc.c b/board/blipper/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/blipper/cbi_ssfc.c +++ b/board/blipper/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 5d2460698acc3344bf5b1de75d526c2d425305a0 Mon Sep 17 00:00:00 2001 From: ridden_liu Date: Thu, 30 Jun 2022 17:22:28 +0800 Subject: Banshee: remove tuning MP2964 We don't need to tune MP2964 timing. These mp2964 tunings were needed for early brya boards. BUG=none BRANCH=none TEST=make BOARD=banshee Signed-off-by: ridden_liu Change-Id: Ia59ff87f63f10efef4686626559c7caf0e2aeaab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3737698 Reviewed-by: Boris Mittelberg Reviewed-by: Elthan Huang Commit-Queue: Boris Mittelberg --- board/banshee/build.mk | 1 - board/banshee/tune_mp2964.c | 42 ------------------------------------------ 2 files changed, 43 deletions(-) delete mode 100644 board/banshee/tune_mp2964.c diff --git a/board/banshee/build.mk b/board/banshee/build.mk index 88621dd44b..c4c9ce0a78 100644 --- a/board/banshee/build.mk +++ b/board/banshee/build.mk @@ -22,6 +22,5 @@ board-y+=keyboard.o board-y+=led.o board-y+=pwm.o board-y+=sensors.o -board-y+=tune_mp2964.o board-y+=usbc_config.o board-y+=keyboard_customization.o diff --git a/board/banshee/tune_mp2964.c b/board/banshee/tune_mp2964.c deleted file mode 100644 index ee4de6d3c4..0000000000 --- a/board/banshee/tune_mp2964.c +++ /dev/null @@ -1,42 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Tune the MP2964 IMVP9.1 parameters for brya */ - -#include "common.h" -#include "compile_time_macros.h" -#include "console.h" -#include "hooks.h" -#include "mp2964.h" - -const static struct mp2964_reg_val rail_a[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ -}; -const static struct mp2964_reg_val rail_b[] = { - { MP2964_MFR_ALT_SET, 0xe081 }, /* ALERT_DELAY = 200ns */ -}; - -static void mp2964_on_startup(void) -{ - static int chip_updated; - int status; - - if (get_board_id() != 1) - return; - - if (chip_updated) - return; - - chip_updated = 1; - - ccprintf("%s: attempting to tune PMIC\n", __func__); - - status = mp2964_tune(rail_a, ARRAY_SIZE(rail_a), rail_b, - ARRAY_SIZE(rail_b)); - if (status != EC_SUCCESS) - ccprintf("%s: could not update all settings\n", __func__); -} - -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, mp2964_on_startup, HOOK_PRIO_FIRST); -- cgit v1.2.1 From 52bf7a9ea43ea3542e25c781bc9e1a7e3f5b50d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:51 -0600 Subject: board/drawcia_riscv/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3340727bc8102928b7ad2310c1c0f33cfc43a244 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728242 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/led.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/drawcia_riscv/led.c b/board/drawcia_riscv/led.c index d13862cdcd..d45099e6c9 100644 --- a/board/drawcia_riscv/led.c +++ b/board/drawcia_riscv/led.c @@ -18,10 +18,8 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -29,7 +27,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -127,9 +125,9 @@ static void led_set_battery(void) */ if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } } @@ -158,8 +156,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); @@ -186,8 +184,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From caee006db1d7e7ed6b012063509bcdf4d63fd639 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:46:02 -0600 Subject: board/mchpevb1/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14d49c30f7e49f49ed2ff7f8e2c00374a0d355d2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728671 Reviewed-by: Jeremy Bettis --- board/mchpevb1/usb_pd_policy.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/mchpevb1/usb_pd_policy.c b/board/mchpevb1/usb_pd_policy.c index 690f8b8a3c..a1ac41854e 100644 --- a/board/mchpevb1/usb_pd_policy.c +++ b/board/mchpevb1/usb_pd_policy.c @@ -18,19 +18,16 @@ #include "usb_mux.h" #include "usb_pd.h" - -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L : - GPIO_USB_C0_CHARGE_EN_L, 1); + gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L : GPIO_USB_C0_CHARGE_EN_L, + 1); /* Provide VBUS */ - gpio_set_level(port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN, 1); + gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 1); /* notify host of power info change */ pd_send_host_event(PD_EVENT_POWER_CHANGE); @@ -41,8 +38,7 @@ int pd_set_power_supply_ready(int port) void pd_power_supply_reset(int port) { /* Disable VBUS */ - gpio_set_level(port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN, 0); + gpio_set_level(port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN, 0); /* notify host of power info change */ pd_send_host_event(PD_EVENT_POWER_CHANGE); -- cgit v1.2.1 From 34caba9182678ae4f304ae90271b8d11470c8c7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:32 -0600 Subject: cts/task/dut.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic54f142b71c5d8bd2295776f8b3f3e036965d30e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729763 Reviewed-by: Jeremy Bettis --- cts/task/dut.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/cts/task/dut.c b/cts/task/dut.c index 71fe4050ec..d895301d61 100644 --- a/cts/task/dut.c +++ b/cts/task/dut.c @@ -70,15 +70,15 @@ enum cts_rc test_task_switch(void) } if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) { - CPRINTS("Unexpected counter values: %d %d %d", - wake_count[0], wake_count[1], wake_count[2]); + CPRINTS("Unexpected counter values: %d %d %d", wake_count[0], + wake_count[1], wake_count[2]); return CTS_RC_FAILURE; } /* TODO: Verify no tasks are ready, no events are pending. */ - if (*task_get_event_bitmap(TASK_ID_A) - || *task_get_event_bitmap(TASK_ID_B) - || *task_get_event_bitmap(TASK_ID_C)) { + if (*task_get_event_bitmap(TASK_ID_A) || + *task_get_event_bitmap(TASK_ID_B) || + *task_get_event_bitmap(TASK_ID_C)) { CPRINTS("Events are pending"); return CTS_RC_FAILURE; } @@ -102,17 +102,17 @@ enum cts_rc test_task_priority(void) return CTS_RC_FAILURE; } - if (wake_count[0] != repeat_count - 1 - || wake_count[1] != repeat_count - 1) { - CPRINTS("Unexpected counter values: %d %d %d", - wake_count[0], wake_count[1], wake_count[2]); + if (wake_count[0] != repeat_count - 1 || + wake_count[1] != repeat_count - 1) { + CPRINTS("Unexpected counter values: %d %d %d", wake_count[0], + wake_count[1], wake_count[2]); return CTS_RC_FAILURE; } /* TODO: Verify no tasks are ready, no events are pending. */ - if (*task_get_event_bitmap(TASK_ID_A) - || *task_get_event_bitmap(TASK_ID_B) - || *task_get_event_bitmap(TASK_ID_C)) { + if (*task_get_event_bitmap(TASK_ID_A) || + *task_get_event_bitmap(TASK_ID_B) || + *task_get_event_bitmap(TASK_ID_C)) { CPRINTS("Events are pending"); return CTS_RC_FAILURE; } -- cgit v1.2.1 From 4565077c1850264815e3afd36b1a4971ff77f67a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:55 -0600 Subject: zephyr/shim/src/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68679356bb874a4c9a3af10c9e4889d31d6a2c0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730909 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/flash.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/zephyr/shim/src/flash.c b/zephyr/shim/src/flash.c index 9802b39c3a..90e6d1a724 100644 --- a/zephyr/shim/src/flash.c +++ b/zephyr/shim/src/flash.c @@ -167,8 +167,7 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) } #if IS_ENABLED(CONFIG_SHELL) -static int command_flashchip(const struct shell *shell, - size_t argc, +static int command_flashchip(const struct shell *shell, size_t argc, char **argv) { uint8_t manufacturer; @@ -177,23 +176,19 @@ static int command_flashchip(const struct shell *shell, uint8_t status2; int res; - res = cros_flash_physical_get_status(cros_flash_dev, - &status1, + res = cros_flash_physical_get_status(cros_flash_dev, &status1, &status2); if (!res) - shell_fprintf(shell, - SHELL_NORMAL, - "Status 1: 0x%02x, Status 2: 0x%02x\n", - status1, status2); + shell_fprintf(shell, SHELL_NORMAL, + "Status 1: 0x%02x, Status 2: 0x%02x\n", status1, + status2); - res = cros_flash_physical_get_jedec_id(cros_flash_dev, - &manufacturer, + res = cros_flash_physical_get_jedec_id(cros_flash_dev, &manufacturer, &device); if (!res) - shell_fprintf(shell, - SHELL_NORMAL, + shell_fprintf(shell, SHELL_NORMAL, "Manufacturer: 0x%02x, DID: 0x%04x\n", manufacturer, device); -- cgit v1.2.1 From a61b2cf394571d8657917e051c183225e4ede330 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:26 -0600 Subject: include/usb_pd_dp_ufp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idb40fefcb0afc4b7c16484c704866378c9cfe603 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730439 Reviewed-by: Jeremy Bettis --- include/usb_pd_dp_ufp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb_pd_dp_ufp.h b/include/usb_pd_dp_ufp.h index 64728d948e..d4b89e1951 100644 --- a/include/usb_pd_dp_ufp.h +++ b/include/usb_pd_dp_ufp.h @@ -32,4 +32,4 @@ void usb_pd_hpd_edge_event(int signal); */ void usb_pd_hpd_converter_enable(int enable); -#endif /* __CROS_EC_USB_PD_DP_UFP_H */ +#endif /* __CROS_EC_USB_PD_DP_UFP_H */ -- cgit v1.2.1 From 367a66c165af939b78e4e4bb2fbac9a5eee585cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:21 -0600 Subject: driver/nfc/ctn730.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55acdf21a01c389a8a8867a064fc2054922c1d18 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730032 Reviewed-by: Jeremy Bettis --- driver/nfc/ctn730.h | 148 ++++++++++++++++++++++++++-------------------------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/driver/nfc/ctn730.h b/driver/nfc/ctn730.h index 0195b36a6d..3ecb869129 100644 --- a/driver/nfc/ctn730.h +++ b/driver/nfc/ctn730.h @@ -6,109 +6,109 @@ #ifndef __CROS_EC_CTN730_H #define __CROS_EC_CTN730_H -#define CTN730_I2C_ADDR 0x28 +#define CTN730_I2C_ADDR 0x28 /* Size of flash address space in bytes */ -#define CTN730_FLASH_ADDR_SIZE 3 +#define CTN730_FLASH_ADDR_SIZE 3 /* All commands are guaranteed to finish within 1 second. */ -#define CTN730_COMMAND_TIME_OUT (1 * SECOND) +#define CTN730_COMMAND_TIME_OUT (1 * SECOND) /* Message Types */ -#define CTN730_MESSAGE_TYPE_COMMAND 0b00 -#define CTN730_MESSAGE_TYPE_RESPONSE 0b01 -#define CTN730_MESSAGE_TYPE_EVENT 0b10 +#define CTN730_MESSAGE_TYPE_COMMAND 0b00 +#define CTN730_MESSAGE_TYPE_RESPONSE 0b01 +#define CTN730_MESSAGE_TYPE_EVENT 0b10 /* Instruction Codes */ -#define WLC_HOST_CTRL_RESET 0b000000 -#define WLC_HOST_CTRL_DL_OPEN_SESSION 0b000011 -#define WLC_HOST_CTRL_DL_COMMIT_SESSION 0b000100 -#define WLC_HOST_CTRL_DL_WRITE_FLASH 0b000101 -#define WLC_HOST_CTRL_DUMP_STATUS 0b001100 -#define WLC_HOST_CTRL_GENERIC_ERROR 0b001111 -#define WLC_HOST_CTRL_BIST 0b000110 -#define WLC_CHG_CTRL_ENABLE 0b010000 -#define WLC_CHG_CTRL_DISABLE 0b010001 -#define WLC_CHG_CTRL_DEVICE_STATE 0b010010 -#define WLC_CHG_CTRL_CHARGING_STATE 0b010100 -#define WLC_CHG_CTRL_CHARGING_INFO 0b010101 +#define WLC_HOST_CTRL_RESET 0b000000 +#define WLC_HOST_CTRL_DL_OPEN_SESSION 0b000011 +#define WLC_HOST_CTRL_DL_COMMIT_SESSION 0b000100 +#define WLC_HOST_CTRL_DL_WRITE_FLASH 0b000101 +#define WLC_HOST_CTRL_DUMP_STATUS 0b001100 +#define WLC_HOST_CTRL_GENERIC_ERROR 0b001111 +#define WLC_HOST_CTRL_BIST 0b000110 +#define WLC_CHG_CTRL_ENABLE 0b010000 +#define WLC_CHG_CTRL_DISABLE 0b010001 +#define WLC_CHG_CTRL_DEVICE_STATE 0b010010 +#define WLC_CHG_CTRL_CHARGING_STATE 0b010100 +#define WLC_CHG_CTRL_CHARGING_INFO 0b010101 /* WLC_HOST_CTRL_RESET constants */ -#define WLC_HOST_CTRL_RESET_CMD_SIZE 1 -#define WLC_HOST_CTRL_RESET_RSP_SIZE 1 -#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE 0x00 -#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE 3 -#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE 0x01 -#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE 2 -#define WLC_HOST_CTRL_RESET_REASON_INTENDED 0x00 -#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED 0x01 -#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE 0x02 -#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL 0x00 -#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD 0x01 +#define WLC_HOST_CTRL_RESET_CMD_SIZE 1 +#define WLC_HOST_CTRL_RESET_RSP_SIZE 1 +#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE 0x00 +#define WLC_HOST_CTRL_RESET_EVT_NORMAL_MODE_SIZE 3 +#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE 0x01 +#define WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE 2 +#define WLC_HOST_CTRL_RESET_REASON_INTENDED 0x00 +#define WLC_HOST_CTRL_RESET_REASON_CORRUPTED 0x01 +#define WLC_HOST_CTRL_RESET_REASON_UNRECOVERABLE 0x02 +#define WLC_HOST_CTRL_RESET_CMD_MODE_NORMAL 0x00 +#define WLC_HOST_CTRL_RESET_CMD_MODE_DOWNLOAD 0x01 #define WLC_HOST_CTRL_RESET_EVT_MIN_SIZE \ WLC_HOST_CTRL_RESET_EVT_DOWNLOAD_MODE_SIZE /* WLC_HOST_CTRL_DL_* constants */ -#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE 2 -#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE 1 -#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE 128 -#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE \ +#define WLC_HOST_CTRL_DL_OPEN_SESSION_CMD_SIZE 2 +#define WLC_HOST_CTRL_DL_OPEN_SESSION_RSP_SIZE 1 +#define WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE 128 +#define WLC_HOST_CTRL_DL_WRITE_FLASH_CMD_SIZE \ (CTN730_FLASH_ADDR_SIZE + WLC_HOST_CTRL_DL_WRITE_FLASH_BLOCK_SIZE) -#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE 1 -#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE 4 -#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE 1 +#define WLC_HOST_CTRL_DL_WRITE_FLASH_RSP_SIZE 1 +#define WLC_HOST_CTRL_DL_COMMIT_SESSION_CMD_SIZE 4 +#define WLC_HOST_CTRL_DL_COMMIT_SESSION_RSP_SIZE 1 /* WLC_CHG_CTRL_ENABLE constants */ -#define WLC_CHG_CTRL_ENABLE_CMD_SIZE 2 -#define WLC_CHG_CTRL_ENABLE_RSP_SIZE 1 +#define WLC_CHG_CTRL_ENABLE_CMD_SIZE 2 +#define WLC_CHG_CTRL_ENABLE_RSP_SIZE 1 /* WLC_CHG_CTRL_DISABLE constants */ -#define WLC_CHG_CTRL_DISABLE_CMD_SIZE 0 -#define WLC_CHG_CTRL_DISABLE_RSP_SIZE 1 -#define WLC_CHG_CTRL_DISABLE_EVT_SIZE 1 +#define WLC_CHG_CTRL_DISABLE_CMD_SIZE 0 +#define WLC_CHG_CTRL_DISABLE_RSP_SIZE 1 +#define WLC_CHG_CTRL_DISABLE_EVT_SIZE 1 /* WLC_CHG_CTRL_DEVICE_STATE constants */ -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED 0x00 -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED 0x01 -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST 0x02 -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION 0x03 -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED 0x04 -#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED 0x05 -#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED 8 -#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE 1 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DETECTED 0x00 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEACTIVATED 0x01 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_LOST 0x02 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DEVICE_BAD_VERSION 0x03 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_DOCKED 0x04 +#define WLC_CHG_CTRL_DEVICE_STATE_DEVICE_UNDOCKED 0x05 +#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE_DETECTED 8 +#define WLC_CHG_CTRL_DEVICE_STATE_EVT_SIZE 1 /* WLC_CHG_CTRL_CHARGING_STATE constants */ -#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED 0x00 -#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED 0x01 -#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED 0x02 -#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE 1 +#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STARTED 0x00 +#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_ENDED 0x01 +#define WLC_CHG_CTRL_CHARGING_STATE_CHARGE_STOPPED 0x02 +#define WLC_CHG_CTRL_CHARGING_STATE_EVT_SIZE 1 /* WLC_HOST_CTRL_DUMP_STATUS constants */ -#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE 1 +#define WLC_HOST_CTRL_DUMP_STATUS_CMD_SIZE 1 /* WLC_CHG_CTRL_CHARGING_INFO constants */ -#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE 0 -#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE 2 -#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE 5 +#define WLC_CHG_CTRL_CHARGING_INFO_CMD_SIZE 0 +#define WLC_CHG_CTRL_CHARGING_INFO_RSP_SIZE 2 +#define WLC_CHG_CTRL_CHARGING_INFO_EVT_SIZE 5 /* Status Codes */ enum wlc_host_status { - WLC_HOST_STATUS_OK = 0x00, - WLC_HOST_STATUS_PARAMETER_ERROR = 0x01, - WLC_HOST_STATUS_STATE_ERROR = 0x02, - WLC_HOST_STATUS_VALUE_ERROR = 0x03, - WLC_HOST_STATUS_REJECTED = 0x04, - WLC_HOST_STATUS_RESOURCE_ERROR = 0x10, - WLC_HOST_STATUS_TXLDO_ERROR = 0x11, - WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR = 0x12, - WLC_HOST_STATUS_BIST_FAILED = 0x20, - WLC_HOST_STATUS_BIST_NO_WLC_CAP = 0x21, - WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW = 0x22, - WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW = 0x23, - WLC_HOST_STATUS_FW_VERSION_ERROR = 0x30, - WLC_HOST_STATUS_FW_VERIFICATION_ERROR = 0x31, - WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR = 0x32, - WLC_HOST_STATUS_NTAG_READ_ERROR = 0x33, + WLC_HOST_STATUS_OK = 0x00, + WLC_HOST_STATUS_PARAMETER_ERROR = 0x01, + WLC_HOST_STATUS_STATE_ERROR = 0x02, + WLC_HOST_STATUS_VALUE_ERROR = 0x03, + WLC_HOST_STATUS_REJECTED = 0x04, + WLC_HOST_STATUS_RESOURCE_ERROR = 0x10, + WLC_HOST_STATUS_TXLDO_ERROR = 0x11, + WLC_HOST_STATUS_ANTENNA_SELECTION_ERROR = 0x12, + WLC_HOST_STATUS_BIST_FAILED = 0x20, + WLC_HOST_STATUS_BIST_NO_WLC_CAP = 0x21, + WLC_HOST_STATUS_BIST_TXLDO_CURRENT_OVERFLOW = 0x22, + WLC_HOST_STATUS_BIST_TXLDO_CURRENT_UNDERFLOW = 0x23, + WLC_HOST_STATUS_FW_VERSION_ERROR = 0x30, + WLC_HOST_STATUS_FW_VERIFICATION_ERROR = 0x31, + WLC_HOST_STATUS_NTAG_BLOCK_PARAMETER_ERROR = 0x32, + WLC_HOST_STATUS_NTAG_READ_ERROR = 0x33, }; struct ctn730_msg { @@ -118,4 +118,4 @@ struct ctn730_msg { uint8_t payload[]; } __packed; -#endif /* __CROS_EC_CTN730_H */ +#endif /* __CROS_EC_CTN730_H */ -- cgit v1.2.1 From 031c893beb527072c6b3832b17992368c85cd273 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:49 -0600 Subject: common/usbc_ocp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01d8d97d77650ff36f4f98572015558173118994 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729801 Reviewed-by: Jeremy Bettis --- common/usbc_ocp.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/common/usbc_ocp.c b/common/usbc_ocp.c index 3694cfec7e..3f7be63039 100644 --- a/common/usbc_ocp.c +++ b/common/usbc_ocp.c @@ -16,8 +16,8 @@ #include "util.h" #ifndef TEST_BUILD -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(args...) #define CPRINTS(args...) @@ -102,7 +102,6 @@ static void re_enable_ports(void) } DECLARE_DEFERRED(re_enable_ports); - int usbc_ocp_add_event(int port) { int delay = 0; @@ -122,8 +121,8 @@ int usbc_ocp_add_event(int port) if (oc_event_cnt_tbl[port] >= OCP_MAX_CNT) { CPRINTS("C%d: OC event limit reached! " - "Source path disabled until physical disconnect.", - port); + "Source path disabled until physical disconnect.", + port); pd_power_supply_reset(port); } else if (oc_event_cnt_tbl[port] <= OCP_HR_CNT) { /* @@ -132,7 +131,7 @@ int usbc_ocp_add_event(int port) * contract. */ pd_send_hard_reset(port); - delay = PD_T_SRC_RECOVER + 100*MSEC; + delay = PD_T_SRC_RECOVER + 100 * MSEC; } else { /* * ErrorRecovery must be performed past the third OCP event, @@ -140,7 +139,7 @@ int usbc_ocp_add_event(int port) * contract is in place */ pd_set_error_recovery(port); - delay = PD_T_ERROR_RECOVERY + 100*MSEC; + delay = PD_T_ERROR_RECOVERY + 100 * MSEC; } if (delay) { @@ -148,11 +147,9 @@ int usbc_ocp_add_event(int port) hook_call_deferred(&re_enable_ports_data, delay); } - return EC_SUCCESS; } - int usbc_ocp_clear_event_counter(int port) { if ((port < 0) || (port >= board_get_usb_pd_port_count())) { @@ -168,8 +165,7 @@ int usbc_ocp_clear_event_counter(int port) * actually detect the physical disconnect. */ if (oc_event_cnt_tbl[port]) { - hook_call_deferred(&clear_oc_tbl_data, - OCP_COOLDOWN_DELAY_US); + hook_call_deferred(&clear_oc_tbl_data, OCP_COOLDOWN_DELAY_US); } return EC_SUCCESS; } -- cgit v1.2.1 From 4528f10f80c8ece53f7d08cca7988436b47df16e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:07 -0600 Subject: driver/tcpm/ps8xxx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ied16cfb6c772e948058284251917ba3f9b5b5983 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730082 Reviewed-by: Jeremy Bettis --- driver/tcpm/ps8xxx.c | 193 ++++++++++++++++++++++++--------------------------- 1 file changed, 89 insertions(+), 104 deletions(-) diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c index 212a7f10dd..0ffd69364a 100644 --- a/driver/tcpm/ps8xxx.c +++ b/driver/tcpm/ps8xxx.c @@ -23,7 +23,7 @@ #include "usb_mux.h" #include "usb_pd.h" -#if !defined(CONFIG_USB_PD_TCPM_PS8705) && \ +#if !defined(CONFIG_USB_PD_TCPM_PS8705) && \ !defined(CONFIG_USB_PD_TCPM_PS8751) && \ !defined(CONFIG_USB_PD_TCPM_PS8755) && \ !defined(CONFIG_USB_PD_TCPM_PS8805) && \ @@ -31,8 +31,7 @@ #error "Unsupported PS8xxx TCPC." #endif -#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || \ - !defined(CONFIG_USB_PD_TCPM_MUX) || \ +#if !defined(CONFIG_USB_PD_TCPM_TCPCI) || !defined(CONFIG_USB_PD_TCPM_MUX) || \ !defined(CONFIG_USBC_SS_MUX) #error "PS8XXX is using a standard TCPCI interface with integrated mux control" @@ -55,10 +54,10 @@ #endif /* CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define PS8XXX_I2C_RECOVERY_DELAY_MS 10 +#define PS8XXX_I2C_RECOVERY_DELAY_MS 10 /* * The product_id per ports here is expected to be set in callback function - @@ -94,7 +93,7 @@ static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT]; void ps8xxx_wake_from_standby(const struct usb_mux *me); -#if defined(CONFIG_USB_PD_TCPM_PS8705) || \ +#if defined(CONFIG_USB_PD_TCPM_PS8705) || \ defined(CONFIG_USB_PD_TCPM_PS8751) || \ defined(CONFIG_USB_PD_TCPM_PS8755) || \ defined(CONFIG_USB_PD_TCPM_PS8805) @@ -122,7 +121,7 @@ static int ps8xxx_addr_dci_disable(int port, int i2c_addr, int i2c_reg) } #endif /* CONFIG_USB_PD_TCPM_PS875[15] || CONFIG_USB_PD_TCPM_PS8[78]05 */ -#if defined(CONFIG_USB_PD_TCPM_PS8705) || \ +#if defined(CONFIG_USB_PD_TCPM_PS8705) || \ defined(CONFIG_USB_PD_TCPM_PS8755) || \ defined(CONFIG_USB_PD_TCPM_PS8805) static int ps8705_dci_disable(int port) @@ -191,8 +190,8 @@ int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level) return EC_ERROR_INVAL; rv = i2c_read8(tcpc_config[port].i2c_info.port, - PS8805_VENDOR_DEFINED_I2C_ADDR, - PS8805_REG_GPIO_CONTROL, ®val); + PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL, + ®val); if (rv) return rv; @@ -203,8 +202,8 @@ int ps8805_gpio_set_level(int port, enum ps8805_gpio signal, int level) regval &= ~mask; return i2c_write8(tcpc_config[port].i2c_info.port, - PS8805_VENDOR_DEFINED_I2C_ADDR, - PS8805_REG_GPIO_CONTROL, regval); + PS8805_VENDOR_DEFINED_I2C_ADDR, + PS8805_REG_GPIO_CONTROL, regval); } int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level) @@ -216,8 +215,8 @@ int ps8805_gpio_get_level(int port, enum ps8805_gpio signal, int *level) return EC_ERROR_INVAL; rv = i2c_read8(tcpc_config[port].i2c_info.port, - PS8805_VENDOR_DEFINED_I2C_ADDR, - PS8805_REG_GPIO_CONTROL, ®val); + PS8805_VENDOR_DEFINED_I2C_ADDR, PS8805_REG_GPIO_CONTROL, + ®val); if (rv) return rv; *level = !!(regval & ps8805_gpio_mask[signal]); @@ -245,49 +244,39 @@ struct ps8xxx_variant_map { */ static struct ps8xxx_variant_map variant_map[] = { #ifdef CONFIG_USB_PD_TCPM_PS8705 - { - PS8705_PRODUCT_ID, - ps8705_dci_disable, - { - [REG_FW_VER] = 0x82, - } - }, + { PS8705_PRODUCT_ID, + ps8705_dci_disable, + { + [REG_FW_VER] = 0x82, + } }, #endif #ifdef CONFIG_USB_PD_TCPM_PS8751 - { - PS8751_PRODUCT_ID, - ps8751_dci_disable, - { - [REG_FW_VER] = 0x90, - } - }, + { PS8751_PRODUCT_ID, + ps8751_dci_disable, + { + [REG_FW_VER] = 0x90, + } }, #endif #ifdef CONFIG_USB_PD_TCPM_PS8755 - { - PS8755_PRODUCT_ID, - ps8705_dci_disable, - { - [REG_FW_VER] = 0x82, - } - }, + { PS8755_PRODUCT_ID, + ps8705_dci_disable, + { + [REG_FW_VER] = 0x82, + } }, #endif #ifdef CONFIG_USB_PD_TCPM_PS8805 - { - PS8805_PRODUCT_ID, - ps8705_dci_disable, - { - [REG_FW_VER] = 0x82, - } - }, + { PS8805_PRODUCT_ID, + ps8705_dci_disable, + { + [REG_FW_VER] = 0x82, + } }, #endif #ifdef CONFIG_USB_PD_TCPM_PS8815 - { - PS8815_PRODUCT_ID, - ps8815_dci_disable, - { - [REG_FW_VER] = 0x82, - } - }, + { PS8815_PRODUCT_ID, + ps8815_dci_disable, + { + [REG_FW_VER] = 0x82, + } }, #endif }; @@ -300,8 +289,7 @@ static int get_reg_by_product(const int port, return INT32_MAX; for (i = 0; i < ARRAY_SIZE(variant_map); i++) { - if (product_id[port] == - variant_map[i].product_id) { + if (product_id[port] == variant_map[i].product_id) { return variant_map[i].reg_map[reg]; } } @@ -341,8 +329,7 @@ static int dp_set_irq(const struct usb_mux *me, int enable) } /* LCOV_EXCL_START */ -__overridable -uint16_t board_get_ps8xxx_product_id(int port) +__overridable uint16_t board_get_ps8xxx_product_id(int port) { /* Board supporting multiple chip sources in ps8xxx.c MUST override this * function to judge the real chip source for this board. For example, @@ -385,8 +372,7 @@ bool check_ps8755_chip(int port) } void ps8xxx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required) + mux_state_t mux_state, bool *ack_required) { int port = me->usb_port; int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; @@ -421,12 +407,12 @@ static int ps8xxx_tcpc_bist_mode_2(int port) int rv; /* Generate BIST for 50ms. */ - rv = tcpc_write(port, - PS8XXX_REG_BIST_CONT_MODE_BYTE0, PS8751_BIST_COUNTER_BYTE0); - rv |= tcpc_write(port, - PS8XXX_REG_BIST_CONT_MODE_BYTE1, PS8751_BIST_COUNTER_BYTE1); - rv |= tcpc_write(port, - PS8XXX_REG_BIST_CONT_MODE_BYTE2, PS8751_BIST_COUNTER_BYTE2); + rv = tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE0, + PS8751_BIST_COUNTER_BYTE0); + rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE1, + PS8751_BIST_COUNTER_BYTE1); + rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_BYTE2, + PS8751_BIST_COUNTER_BYTE2); /* Auto stop */ rv |= tcpc_write(port, PS8XXX_REG_BIST_CONT_MODE_CTR, 0); @@ -438,7 +424,7 @@ static int ps8xxx_tcpc_bist_mode_2(int port) } static int ps8xxx_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data) + uint16_t header, const uint32_t *data) { if (type == TCPCI_MSG_TX_BIST_MODE_2) return ps8xxx_tcpc_bist_mode_2(port); @@ -472,7 +458,7 @@ static void ps8xxx_role_control_delay(int port) #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE static int ps8xxx_set_role_ctrl(int port, enum tcpc_drp drp, - enum tcpc_rp_value rp, enum tcpc_cc_pull pull) + enum tcpc_rp_value rp, enum tcpc_cc_pull pull) { int rv; @@ -518,7 +504,7 @@ static int ps8xxx_tcpc_drp_toggle(int port) /* Set auto drp toggle, starting with the opposite pull */ rv |= ps8xxx_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, - opposite_pull); + opposite_pull); /* Set Look4Connection command */ rv |= tcpc_write(port, TCPC_REG_COMMAND, @@ -645,7 +631,7 @@ static int ps8xxx_lpm_recovery_delay(int port) } static int ps8xxx_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) + struct ec_response_pd_chip_info_v1 *chip_info) { int val; int reg; @@ -694,10 +680,10 @@ static int ps8xxx_get_chip_info(int port, int live, chip_info->fw_version_number = val; /* Treat unexpected values as error (FW not initiated from reset) */ - if (live && ( - chip_info->vendor_id != PS8XXX_VENDOR_ID || - chip_info->product_id != board_get_ps8xxx_product_id(port) || - chip_info->fw_version_number == 0)) + if (live && + (chip_info->vendor_id != PS8XXX_VENDOR_ID || + chip_info->product_id != board_get_ps8xxx_product_id(port) || + chip_info->fw_version_number == 0)) return EC_ERROR_UNKNOWN; #if defined(CONFIG_USB_PD_TCPM_PS8751) && \ @@ -721,7 +707,7 @@ static int ps8xxx_enter_low_power_mode(int port) * don't have it. Stub it out for PS8751/PS8815. */ if (product_id[port] == PS8751_PRODUCT_ID || - product_id[port] == PS8815_PRODUCT_ID) + product_id[port] == PS8815_PRODUCT_ID) return EC_SUCCESS; return tcpci_enter_low_power_mode(port); @@ -736,8 +722,7 @@ __maybe_unused static int ps8815_tcpc_fast_role_swap_enable(int port, if (!tcpm_tcpc_has_frs_control(port)) return EC_SUCCESS; - status = tcpc_update8(port, - PS8815_REG_RESERVED_F4, + status = tcpc_update8(port, PS8815_REG_RESERVED_F4, PS8815_REG_RESERVED_F4_FRS_EN, enable ? MASK_SET : MASK_CLR); if (status != EC_SUCCESS) @@ -816,7 +801,8 @@ __maybe_unused static int ps8815_disable_rp_detect_workaround_check(int port) } __overridable void board_ps8xxx_tcpc_init(int port) -{} +{ +} static int ps8xxx_tcpm_init(int port) { @@ -848,8 +834,7 @@ static int ps8xxx_tcpm_init(int port) * set reg 0xf4.FRS_EN (drive FRS GPIO to PPC) */ if (tcpm_tcpc_has_frs_control(port)) { - status = tcpc_update8(port, - PS8815_REG_RESERVED_D1, + status = tcpc_update8(port, PS8815_REG_RESERVED_D1, PS8815_REG_RESERVED_D1_FRS_EN, MASK_SET); if (status != EC_SUCCESS) @@ -884,7 +869,7 @@ static int ps8xxx_tcpm_init(int port) * delay will allow the transient to disappear. */ static int ps8751_get_gcc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int rv; int status; @@ -932,7 +917,7 @@ static int ps8xxx_tcpm_set_cc(int port, int pull) } static int ps8xxx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { #ifdef CONFIG_USB_PD_TCPM_PS8751 if (product_id[port] == PS8751_PRODUCT_ID) @@ -957,39 +942,39 @@ static int ps8xxx_tcpm_set_vconn(int port, int enable) } const struct tcpm_drv ps8xxx_tcpm_drv = { - .init = ps8xxx_tcpm_init, - .release = ps8xxx_tcpm_release, - .get_cc = ps8xxx_tcpm_get_cc, + .init = ps8xxx_tcpm_init, + .release = ps8xxx_tcpm_release, + .get_cc = ps8xxx_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = tcpci_tcpm_check_vbus_level, + .check_vbus_level = tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = tcpci_tcpm_select_rp_value, - .set_cc = ps8xxx_tcpm_set_cc, - .set_polarity = tcpci_tcpm_set_polarity, + .select_rp_value = tcpci_tcpm_select_rp_value, + .set_cc = ps8xxx_tcpm_set_cc, + .set_polarity = tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = ps8xxx_tcpm_set_vconn, - .set_msg_header = tcpci_tcpm_set_msg_header, - .set_rx_enable = tcpci_tcpm_set_rx_enable, - .get_message_raw = tcpci_tcpm_get_message_raw, - .transmit = ps8xxx_tcpm_transmit, - .tcpc_alert = tcpci_tcpc_alert, + .set_vconn = ps8xxx_tcpm_set_vconn, + .set_msg_header = tcpci_tcpm_set_msg_header, + .set_rx_enable = tcpci_tcpm_set_rx_enable, + .get_message_raw = tcpci_tcpm_get_message_raw, + .transmit = ps8xxx_tcpm_transmit, + .tcpc_alert = tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = tcpci_tcpc_discharge_vbus, #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = ps8xxx_tcpc_drp_toggle, + .drp_toggle = ps8xxx_tcpc_drp_toggle, #endif - .get_chip_info = ps8xxx_get_chip_info, - .set_snk_ctrl = tcpci_tcpm_set_snk_ctrl, - .set_src_ctrl = tcpci_tcpm_set_src_ctrl, + .get_chip_info = ps8xxx_get_chip_info, + .set_snk_ctrl = tcpci_tcpm_set_snk_ctrl, + .set_src_ctrl = tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = ps8xxx_enter_low_power_mode, + .enter_low_power_mode = ps8xxx_enter_low_power_mode, #endif - .set_bist_test_mode = tcpci_set_bist_test_mode, + .set_bist_test_mode = tcpci_set_bist_test_mode, #if defined(CONFIG_USB_PD_FRS) && defined(CONFIG_USB_PD_TCPM_PS8815) - .set_frs_enable = ps8815_tcpc_fast_role_swap_enable, + .set_frs_enable = ps8815_tcpc_fast_role_swap_enable, #endif }; @@ -1049,11 +1034,11 @@ static int ps8xxx_mux_set(const struct usb_mux *me, mux_state_t mux_state, * setting mux breaks SuperSpeed connection. */ if (mux_state != USB_PD_MUX_NONE) - RETURN_ERROR(mux_write(me, TCPC_REG_ROLE_CTRL, - TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, - TYPEC_RP_USB, - TYPEC_CC_RD, - TYPEC_CC_RD))); + RETURN_ERROR( + mux_write(me, TCPC_REG_ROLE_CTRL, + TCPC_REG_ROLE_CTRL_SET( + TYPEC_NO_DRP, TYPEC_RP_USB, + TYPEC_CC_RD, TYPEC_CC_RD))); } return tcpci_tcpm_mux_set(me, mux_state, ack_required); -- cgit v1.2.1 From a87b07108da1112da0be2d15f6f9af6ded1127dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:29 -0600 Subject: driver/temp_sensor/tmp112.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8f3c0a5c30fedba422dae16b2882939575fe294 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729880 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp112.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/driver/temp_sensor/tmp112.c b/driver/temp_sensor/tmp112.c index 6e726a27b9..a2e067fda4 100644 --- a/driver/temp_sensor/tmp112.c +++ b/driver/temp_sensor/tmp112.c @@ -21,7 +21,7 @@ #define TMP112_SHIFT1 (16 - TMP112_RESOLUTION) #define TMP112_SHIFT2 (TMP112_RESOLUTION - 8) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) static int temp_mk_local[TMP112_COUNT]; @@ -35,8 +35,8 @@ static int raw_read16(int sensor, const int offset, int *data_ptr) return EC_ERROR_NOT_POWERED; #endif return i2c_read16(tmp112_sensors[sensor].i2c_port, - tmp112_sensors[sensor].i2c_addr_flags, - offset, data_ptr); + tmp112_sensors[sensor].i2c_addr_flags, offset, + data_ptr); } static int raw_write16(int sensor, const int offset, int data) @@ -49,8 +49,7 @@ static int raw_write16(int sensor, const int offset, int data) return EC_ERROR_NOT_POWERED; #endif return i2c_write16(tmp112_sensors[sensor].i2c_port, - tmp112_sensors[sensor].i2c_addr_flags, - offset, data); + tmp112_sensors[sensor].i2c_addr_flags, offset, data); } static int get_reg_temp(int sensor, int *temp_ptr) -- cgit v1.2.1 From d42d801c1bc0d2bda99bef1fca3fef6f80a769b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:06 -0600 Subject: common/ctz.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73a582fc4ba30418041e6d93c29a928750de44db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729620 Reviewed-by: Jeremy Bettis --- common/ctz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/ctz.c b/common/ctz.c index bb6f69624e..a2b083baa7 100644 --- a/common/ctz.c +++ b/common/ctz.c @@ -20,8 +20,8 @@ int __keep __ctzsi2(int x) { static const uint8_t MulDeBruijnBitPos[32] = { - 0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8, - 31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9 + 0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8, + 31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9 }; return MulDeBruijnBitPos[((uint32_t)((x & -x) * 0x077CB531U)) >> 27]; } -- cgit v1.2.1 From 54155a58aa8902b2d7c0a31eed04f33dad5342e2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:03 -0600 Subject: board/dewatt/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2cc1e224672f708f0f6c46404b891db3dceeade9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728201 Reviewed-by: Jeremy Bettis --- board/dewatt/thermal.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/board/dewatt/thermal.c b/board/dewatt/thermal.c index 0d0d80095a..c35de5775b 100644 --- a/board/dewatt/thermal.c +++ b/board/dewatt/thermal.c @@ -12,7 +12,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, @@ -93,14 +93,14 @@ struct fan_step { }; static const struct fan_step fan_table[] = { - {.on = 0, .off = 1, .rpm = 0}, - {.on = 6, .off = 2, .rpm = 3000}, - {.on = 28, .off = 15, .rpm = 3300}, - {.on = 34, .off = 26, .rpm = 3700}, - {.on = 39, .off = 32, .rpm = 4000}, - {.on = 45, .off = 38, .rpm = 4300}, - {.on = 51, .off = 43, .rpm = 4700}, - {.on = 74, .off = 62, .rpm = 5400}, + { .on = 0, .off = 1, .rpm = 0 }, + { .on = 6, .off = 2, .rpm = 3000 }, + { .on = 28, .off = 15, .rpm = 3300 }, + { .on = 34, .off = 26, .rpm = 3700 }, + { .on = 39, .off = 32, .rpm = 4000 }, + { .on = 45, .off = 38, .rpm = 4300 }, + { .on = 51, .off = 43, .rpm = 4700 }, + { .on = 74, .off = 62, .rpm = 5400 }, }; #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table) @@ -137,10 +137,8 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) - CPRINTS("Setting fan RPM to %d", - fan_table[current_level].rpm); + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) + CPRINTS("Setting fan RPM to %d", fan_table[current_level].rpm); return fan_table[current_level].rpm; } -- cgit v1.2.1 From 8bf8871ccca55c1193d9a56bf9282b3c07c54244 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:51 -0600 Subject: board/scarlet/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb757af8ee37889062fd05fac04583e8daa502ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728916 Reviewed-by: Jeremy Bettis --- board/scarlet/board.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/board/scarlet/board.h b/board/scarlet/board.h index 19fda5382f..eb4432eba4 100644 --- a/board/scarlet/board.h +++ b/board/scarlet/board.h @@ -15,12 +15,12 @@ /* Optional modules */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_CHIPSET_RK3399 #define CONFIG_CMD_ACCELS #define CONFIG_CMD_RTC #define CONFIG_EMULATED_SYSRQ -#undef CONFIG_HIBERNATE +#undef CONFIG_HIBERNATE #define CONFIG_HOSTCMD_RTC #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -40,7 +40,7 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 #define CONFIG_UART_RX_DMA @@ -92,8 +92,7 @@ /* Camera VSYNC */ #define CONFIG_SYNC #define CONFIG_SYNC_COMMAND -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) /* To be able to indicate the device is in tablet mode. */ #define CONFIG_TABLET_MODE @@ -137,33 +136,33 @@ #endif /* Battery parameters for max17055 ModelGauge m5 algorithm. */ -#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ -#define BATTERY_DESIRED_CHARGING_CURRENT 4000 /* mA */ +#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ +#define BATTERY_DESIRED_CHARGING_CURRENT 4000 /* mA */ #define CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT -#define BAT_MAX_DISCHG_CURRENT 5000 /* mA */ +#define BAT_MAX_DISCHG_CURRENT 5000 /* mA */ #define CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE #define BAT_LOW_VOLTAGE_THRESH 3200 /* mV */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 12850 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 12850 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Timer selection */ -#define TIM_CLOCK32 2 +#define TIM_CLOCK32 2 #define TIM_WATCHDOG 7 /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 /* Optional for testing */ -#undef CONFIG_PECI -#undef CONFIG_PSTORE +#undef CONFIG_PECI +#undef CONFIG_PSTORE /* Modules we want to exclude */ #undef CONFIG_CMD_BATTFAKE @@ -176,24 +175,24 @@ #define CONFIG_TASK_PROFILING -#define I2C_PORT_CHARGER 0 -#define I2C_PORT_BATTERY 0 +#define I2C_PORT_CHARGER 0 +#define I2C_PORT_BATTERY 0 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_TCPC0 1 +#define I2C_PORT_TCPC0 1 /* Route sbs host requests to virtual battery driver */ #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_MKBP_INPUT_DEVICES #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO /* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 8be9e2df16b56392822438e5c9c4f70775eeacfd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:59 -0600 Subject: board/lalala/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I221141be248686f6346949854bbf7cb69237c73c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728612 Reviewed-by: Jeremy Bettis --- board/lalala/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/lalala/cbi_ssfc.h b/board/lalala/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/lalala/cbi_ssfc.h +++ b/board/lalala/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From fa5f83374ddedb02ea273038ad64dcfc9a3f3a7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:55 -0600 Subject: chip/mt_scp/rv32i_common/ipi_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4790b720538476983232f01963bcf2d85fb0f868 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729360 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/ipi_chip.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/mt_scp/rv32i_common/ipi_chip.h b/chip/mt_scp/rv32i_common/ipi_chip.h index 47a9434b09..80f70e5c3b 100644 --- a/chip/mt_scp/rv32i_common/ipi_chip.h +++ b/chip/mt_scp/rv32i_common/ipi_chip.h @@ -72,15 +72,15 @@ extern int *const ipi_wakeup_table[]; * handler: The IPI handler function * is_wakeup_src: Declare IPI ID as a wake-up source or not */ -#define DECLARE_IPI(_id, handler, is_wakeup_src) \ - struct ipi_num_check##_id { \ - int tmp1[_id < IPI_COUNT ? 1 : -1]; \ +#define DECLARE_IPI(_id, handler, is_wakeup_src) \ + struct ipi_num_check##_id { \ + int tmp1[_id < IPI_COUNT ? 1 : -1]; \ int tmp2[is_wakeup_src == 0 || is_wakeup_src == 1 ? 1 : -1]; \ - }; \ - void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ - { \ - handler(id, buf, len); \ - } \ + }; \ + void __keep IPI_HANDLER(_id)(int32_t id, void *buf, uint32_t len) \ + { \ + handler(id, buf, len); \ + } \ const int __keep IPI_WAKEUP(_id) = is_wakeup_src #endif /* __CROS_EC_IPI_CHIP_H */ -- cgit v1.2.1 From be008a9fa9222af83daf93f75ce1cf5137ab920b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:34 -0600 Subject: zephyr/emul/i2c_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19bca7fc7feb823028b0bcd56528b517b5fb7e55 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730700 Reviewed-by: Jeremy Bettis --- zephyr/emul/i2c_mock.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/emul/i2c_mock.c b/zephyr/emul/i2c_mock.c index e7750d5b72..ecacf95369 100644 --- a/zephyr/emul/i2c_mock.c +++ b/zephyr/emul/i2c_mock.c @@ -41,8 +41,7 @@ static const struct i2c_emul_api i2c_mock_api = { .transfer = i2c_common_emul_transfer, }; -static int i2c_mock_init(const struct emul *emul, - const struct device *parent) +static int i2c_mock_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = emul->data; -- cgit v1.2.1 From b4cbafa2e00644bd4b73487d78a2903cfc84e0df Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:55 -0600 Subject: board/mchpevb1/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I646032346cc85c3527b840ea67818b77a49bc5e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728655 Reviewed-by: Jeremy Bettis --- board/mchpevb1/board.c | 136 ++++++++++++++++++++----------------------------- 1 file changed, 55 insertions(+), 81 deletions(-) diff --git a/board/mchpevb1/board.c b/board/mchpevb1/board.c index 2991b59299..76982e58f5 100644 --- a/board/mchpevb1/board.c +++ b/board/mchpevb1/board.c @@ -58,26 +58,25 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* NOTE: MEC17xx EVB + SKL RVP3 does not use BD99992 PMIC. * RVP3 PMIC controlled by RVP3 logic. */ -#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_BD99992_FLAGS 0x30 /* * Maxim DS1624 I2C temperature sensor used for testing I2C. * DS1624 contains one internal temperature sensor * and EEPROM. It has no external temperature inputs. */ -#define DS1624_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN) -#define DS1624_IDX_LOCAL 0 -#define DS1624_READ_TEMP16 0xAA /* read 16-bit temperature */ -#define DS1624_ACCESS_CFG 0xAC /* read/write 8-bit config */ -#define DS1624_CMD_START 0xEE -#define DS1624_CMD_STOP 0x22 +#define DS1624_I2C_ADDR_FLAGS (0x48 | I2C_FLAG_BIG_ENDIAN) +#define DS1624_IDX_LOCAL 0 +#define DS1624_READ_TEMP16 0xAA /* read 16-bit temperature */ +#define DS1624_ACCESS_CFG 0xAC /* read/write 8-bit config */ +#define DS1624_CMD_START 0xEE +#define DS1624_CMD_STOP 0x22 /* * static global and routine to return smart battery @@ -116,7 +115,6 @@ void board_config_pre_init(void) } #endif /* #ifdef CONFIG_BOARD_PRE_INIT */ - /* * Use EC to handle ALL_SYS_PWRGD signal. * MEC17xx connected to SKL/KBL RVP3 reference board @@ -135,8 +133,8 @@ static void board_all_sys_pwrgd(void) CPRINTS("ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, allsys_out); - trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d", - allsys_in, allsys_out); + trace2(0, BRD, 0, "ALL_SYS_PWRGD=%d SYS_RESET_L=%d", allsys_in, + allsys_out); /* * Wait at least 10 ms between power signals going high @@ -161,14 +159,12 @@ void all_sys_pwrgd_interrupt(enum gpio_signal signal) } #endif /* #ifdef CONFIG_BOARD_HAS_ALL_SYS_PWRGD */ - #ifdef HAS_TASK_PDCMD /* Exchange status with PD MCU. */ static void pd_mcu_interrupt(enum gpio_signal signal) { /* Exchange status with PD MCU to determine interrupt cause */ host_command_pd_send_status(0); - } #endif @@ -217,33 +213,29 @@ void tablet_mode_interrupt(enum gpio_signal signal) */ const struct adc_t adc_channels[] = { /* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */ - [ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1}, + [ADC_VBUS] = { "VBUS", 30000, 1024, 0, 1 }, /* Adapter current output or battery discharging current */ - [ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3}, + [ADC_AMON_BMON] = { "AMON_BMON", 25000, 3072, 0, 3 }, /* System current consumption */ - [ADC_PSYS] = {"PSYS", 1, 1, 0, 4}, - [ADC_CASE] = {"CASE", 1, 1, 0, 7}, + [ADC_PSYS] = { "PSYS", 1, 1, 0, 4 }, + [ADC_CASE] = { "CASE", 1, 1, 0, 7 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* * MCHP EVB connected to KBL RVP3 */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "sensors", - .port = MCHP_I2C_PORT4, - .kbps = 100, - .scl = GPIO_SMB04_SCL, - .sda = GPIO_SMB04_SDA - }, - { - .name = "batt", - .port = MCHP_I2C_PORT5, - .kbps = 100, - .scl = GPIO_SMB05_SCL, - .sda = GPIO_SMB05_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "sensors", + .port = MCHP_I2C_PORT4, + .kbps = 100, + .scl = GPIO_SMB04_SCL, + .sda = GPIO_SMB04_SDA }, + { .name = "batt", + .port = MCHP_I2C_PORT5, + .kbps = 100, + .scl = GPIO_SMB05_SCL, + .sda = GPIO_SMB05_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -273,19 +265,15 @@ int board_i2c_p2c(int port) #ifdef CONFIG_USB_POWER_DELIVERY const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - {I2C_PORT_TCPC, - CONFIG_TCPC_I2C_BASE_ADDR_FLAGS, - &tcpci_tcpm_drv}, + { I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS, &tcpci_tcpm_drv }, - {I2C_PORT_TCPC, - CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1, - &tcpci_tcpm_drv}, + { I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1, &tcpci_tcpm_drv }, }; #endif /* SPI devices */ const struct spi_device_t spi_devices[] = { - { QMSPI0_PORT, 4, GPIO_QMSPI_CS0}, + { QMSPI0_PORT, 4, GPIO_QMSPI_CS0 }, #if defined(CONFIG_SPI_ACCEL_PORT) { GPSPI0_PORT, 2, GPIO_SPI0_CS0 }, #endif @@ -299,7 +287,6 @@ const enum gpio_signal hibernate_wake_pins[] = { }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - /* * Deep sleep support, called by chip level. */ @@ -429,9 +416,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); * a static global in this module. */ const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0}, - {"Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0}, - {"Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, sb_temp, 0 }, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, ds1624_get_val, 0 }, + { "Case", TEMP_SENSOR_TYPE_CASE, therm_get_val, (int)ADC_CASE }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); #endif @@ -440,16 +427,16 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); #ifdef CONFIG_ALS /* ALS instances. Must be in same order as enum als_id. */ struct als_t als[] = { - {"TI", opt3001_init, opt3001_read_lux, 5}, + { "TI", opt3001_init, opt3001_read_lux, 5 }, }; BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT); #endif const struct button_config buttons[CONFIG_BUTTON_COUNT] = { - {"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L, - 30 * MSEC, 0}, - {"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L, - 30 * MSEC, 0}, + { "Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L, + 30 * MSEC, 0 }, + { "Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L, 30 * MSEC, + 0 }, }; /* MCHP mec1701_evb connected to Intel SKL RVP3 with Kabylake @@ -490,8 +477,7 @@ static void board_pmic_init(void) cfg = 0x66; rv = i2c_read8(I2C_PORT_THERMAL, DS1624_I2C_ADDR_FLAGS, DS1624_ACCESS_CFG, &cfg); - trace2(0, BRD, 0, "Read DS1624 Config rv = %d cfg = 0x%02X", - rv, cfg); + trace2(0, BRD, 0, "Read DS1624 Config rv = %d cfg = 0x%02X", rv, cfg); if ((rv == EC_SUCCESS) && (cfg & (1u << 0))) { /* one-shot mode switch to continuous */ @@ -536,16 +522,13 @@ static void board_init(void) /* Provide AC status to the PCH */ gpio_set_level(GPIO_PCH_ACOK, extpower_is_present()); - if (system_jumped_late() && - chipset_in_state(CHIPSET_STATE_ON)) { + if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) { trace0(0, BRD, 0, "board_init: S0 call board_spi_enable"); board_spi_enable(); } - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - /** * Buffer the AC present GPIO to the PCH. */ @@ -577,8 +560,7 @@ int board_set_active_charge_port(int charge_port) if (is_real_port && source) { CPRINTS("MEC1701 Skip enable p%d", charge_port); - trace1(0, BOARD, 0, "Skip enable charge port %d", - charge_port); + trace1(0, BOARD, 0, "Skip enable charge port %d", charge_port); return EC_ERROR_INVAL; } @@ -592,10 +574,12 @@ int board_set_active_charge_port(int charge_port) } else { /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L : - GPIO_USB_C1_CHARGE_EN_L, 1); + GPIO_USB_C1_CHARGE_EN_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L : - GPIO_USB_C0_CHARGE_EN_L, 0); + GPIO_USB_C0_CHARGE_EN_L, + 0); } return EC_SUCCESS; @@ -609,11 +593,11 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } #else /* @@ -625,7 +609,6 @@ int charge_prevent_power_on(int power_button_pressed) return 0; } - #endif /* @@ -657,23 +640,18 @@ static void board_chipset_startup(void) gpio_set_level(GPIO_USB2_ENABLE, 1); hook_call_deferred(&enable_input_devices_data, 0); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); /* Called on AP S3 -> S5 transition */ static void board_chipset_shutdown(void) { CPRINTS("MEC1701 HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown"); - trace0(0, HOOK, 0, - "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown"); + trace0(0, HOOK, 0, "HOOK_CHIPSET_SHUTDOWN board_chipset_shutdown"); gpio_set_level(GPIO_USB1_ENABLE, 0); gpio_set_level(GPIO_USB2_ENABLE, 0); hook_call_deferred(&enable_input_devices_data, 0); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_chipset_shutdown, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) @@ -685,10 +663,9 @@ static void board_chipset_resume(void) gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1); gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 1); #endif - } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, - MOTION_SENSE_HOOK_PRIO-1); + MOTION_SENSE_HOOK_PRIO - 1); /* Called on AP S0 -> S3 transition */ static void board_chipset_suspend(void) @@ -701,9 +678,7 @@ static void board_chipset_suspend(void) gpio_set_level(GPIO_PP1800_DX_SENSOR_EN, 0); #endif } -DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, - board_chipset_suspend, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); void board_hibernate_late(void) { @@ -780,7 +755,6 @@ static void board_handle_reboot(void) } DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST); - static int sb_temp(int idx, int *temp_ptr) { if (idx != 0) @@ -817,8 +791,8 @@ static void sb_update(void) rv = sb_read(SB_TEMPERATURE, &smart_batt_temp); smart_batt_temp = smart_batt_temp / 10; - trace12(0, BRD, 0, "sb_read temperature rv=%d temp=%d K", - rv, smart_batt_temp); + trace12(0, BRD, 0, "sb_read temperature rv=%d temp=%d K", rv, + smart_batt_temp); } /* -- cgit v1.2.1 From f19210efe1a3897ff182d272466a5cade7175cc5 Mon Sep 17 00:00:00 2001 From: Peter Chi Date: Tue, 28 Jun 2022 09:24:29 +0000 Subject: Revert "crota: add power share support" This reverts commit aa949e591d8261a387315f211492062a4779cf4e. Reason for revert: Because firmware_ECUsbPorts test will FAILED when power share support, so we need revert this CL to make sure the test PASS. Original change's description: > crota: add power share support > > We need add feture for power share in S5/G3 state. > > BUG=b:230074336, b:230083233 > BRANCH=none > TEST=make -j BOARD=crota > > Signed-off-by: Peter Chi > Change-Id: Ic95887aeffea90b35159056af121f81513975ab2 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3602116 > Commit-Queue: Boris Mittelberg > Reviewed-by: Boris Mittelberg Bug: b:230074336, b:230083233 Change-Id: I55c95b1a352001589d94fd2f3f6b265cc48e63e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731770 Tested-by: Peter Chi Auto-Submit: Peter Chi Commit-Queue: Boris Mittelberg Reviewed-by: Boris Mittelberg --- board/crota/board.c | 21 --------------------- board/crota/board.h | 1 - 2 files changed, 22 deletions(-) diff --git a/board/crota/board.c b/board/crota/board.c index d74bdc29b6..a71549cdd7 100644 --- a/board/crota/board.c +++ b/board/crota/board.c @@ -10,7 +10,6 @@ #include "common.h" #include "compile_time_macros.h" #include "console.h" -#include "extpower.h" #include "gpio.h" #include "gpio_signal.h" #include "hooks.h" @@ -56,23 +55,3 @@ static void board_chipset_suspend(void) gpio_set_level(GPIO_EC_KB_BL_EN_L, 1); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); - -#ifdef CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK -static void usb_port_startup(void) -{ - gpio_set_level(GPIO_EN_PP5000_USBA_R, 1); -} -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, usb_port_startup, HOOK_PRIO_DEFAULT); - -static void usba_power(void) -{ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) { - if (extpower_is_present()) - gpio_set_level(GPIO_EN_PP5000_USBA_R, 1); - else - gpio_set_level(GPIO_EN_PP5000_USBA_R, 0); - } -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usba_power, HOOK_PRIO_DEFAULT); -DECLARE_HOOK(HOOK_AC_CHANGE, usba_power, HOOK_PRIO_DEFAULT); -#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */ diff --git a/board/crota/board.h b/board/crota/board.h index e972cf3425..9343e1b111 100644 --- a/board/crota/board.h +++ b/board/crota/board.h @@ -56,7 +56,6 @@ /* USB Type A Features */ #define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB -#define CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY -- cgit v1.2.1 From 2028551e8f5d22005df89ac5c84ddbdb9d09ef65 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:27 -0600 Subject: chip/mec1322/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I379c6716428192dbd3a695a73733d30c870a962f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729334 Reviewed-by: Jeremy Bettis --- chip/mec1322/uart.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c index 9118168dcd..d9f94b07f7 100644 --- a/chip/mec1322/uart.c +++ b/chip/mec1322/uart.c @@ -163,7 +163,7 @@ void uart_init(void) void uart_enter_dsleep(void) { /* Disable the UART interrupt. */ - task_disable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART=13 */ + task_disable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART=13 */ /* * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt @@ -175,13 +175,12 @@ void uart_enter_dsleep(void) MEC1322_UART_ACT &= ~BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ - MEC1322_INT_SOURCE(8) = (1<<18); + MEC1322_INT_SOURCE(8) = (1 << 18); /* Enable GPIO interrupts on the UART0 RX pin. */ gpio_enable_interrupt(GPIO_UART0_RX); } - void uart_exit_dsleep(void) { /* -- cgit v1.2.1 From 2ef111c88dbedb348422aefbc0229055ed94cdfc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:52 -0600 Subject: board/kano/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia14d8b7df1f38fe0488fc6bc1bbab62c021f24af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728522 Reviewed-by: Jeremy Bettis --- board/kano/fw_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/kano/fw_config.h b/board/kano/fw_config.h index 88573bdd33..56218a8f87 100644 --- a/board/kano/fw_config.h +++ b/board/kano/fw_config.h @@ -26,12 +26,12 @@ enum ec_cfg_thermal_solution_type { union kano_cbi_fw_config { struct { - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t ufc : 2; - uint32_t stylus : 1; - enum ec_cfg_thermal_solution_type thermal_solution : 1; - uint32_t reserved_1 : 24; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t ufc : 2; + uint32_t stylus : 1; + enum ec_cfg_thermal_solution_type thermal_solution : 1; + uint32_t reserved_1 : 24; }; uint32_t raw_value; }; -- cgit v1.2.1 From 5f935e67cffbdc406f04982cee7970b26dd1e0e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:12 -0600 Subject: board/woomax/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2243f585e03ef5e597bca0d5006f698a5094a9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729116 Reviewed-by: Jeremy Bettis --- board/woomax/board.h | 85 ++++++++++++++++++++-------------------------------- 1 file changed, 33 insertions(+), 52 deletions(-) diff --git a/board/woomax/board.h b/board/woomax/board.h index 2c249d7781..b1be1bcd1a 100644 --- a/board/woomax/board.h +++ b/board/woomax/board.h @@ -50,36 +50,32 @@ #define CONFIG_CUSTOM_FAN_CONTROL /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_C536, @@ -92,11 +88,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -105,10 +97,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -156,40 +145,32 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBC1_RETIMER_PS8802 \ - (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_USBC1_RETIMER_PS8802 (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_usbc1_retimer_ps8802(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8802); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8802); } -#define HAS_USBC1_RETIMER_PS8818 \ - (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI)) +#define HAS_USBC1_RETIMER_PS8818 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_usbc1_retimer_ps8818(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8818); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8818); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(WOOMAX_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } -#define HAS_MST_HUB_RTD2141B \ - (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_MST_HUB_RTD2141B (BIT(WOOMAX_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_mst_hub_rtd2141b(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_MST_HUB_RTD2141B); + return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B); } /** -- cgit v1.2.1 From 60502c2f9f78aa12d48c53a67b6dbc31f559b549 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:32 -0600 Subject: board/rainier/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3ba7ba2ef24335fcc82a19fdc1577bd7112796a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728874 Reviewed-by: Jeremy Bettis --- board/rainier/board.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/board/rainier/board.h b/board/rainier/board.h index e3d333e2f1..fab8e0c9fe 100644 --- a/board/rainier/board.h +++ b/board/rainier/board.h @@ -10,7 +10,7 @@ /* Optional modules */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_CHIPSET_RK3399 #define CONFIG_CMD_ACCELS #define CONFIG_CMD_RTC @@ -30,11 +30,11 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 /* Region sizes are no longer a power of 2 so we can't enable MPU */ -#undef CONFIG_MPU +#undef CONFIG_MPU /* Enable a different power-on sequence than the one on gru */ #undef CONFIG_CHIPSET_POWER_SEQ_VERSION @@ -104,38 +104,38 @@ #define CONFIG_USB_PD_COMM_LOCKED #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 12850 +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 12850 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Timer selection */ -#define TIM_CLOCK32 2 +#define TIM_CLOCK32 2 #define TIM_WATCHDOG 7 /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 /* Optional for testing */ -#undef CONFIG_PECI -#undef CONFIG_PSTORE +#undef CONFIG_PECI +#undef CONFIG_PSTORE #define CONFIG_TASK_PROFILING #define I2C_PORT_TCPC0 1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_MKBP_INPUT_DEVICES #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO /* Define the host events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_RTC)) #ifndef __ASSEMBLER__ -- cgit v1.2.1 From cceaa8969775fc7203ab4e065a4cf31de91660f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:33 -0600 Subject: chip/max32660/icc_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c41404e27162c9c55c1d19bd34af5fd2ba939a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729234 Reviewed-by: Jeremy Bettis --- chip/max32660/icc_regs.h | 110 +++++++++++++++++++++++------------------------ 1 file changed, 54 insertions(+), 56 deletions(-) diff --git a/chip/max32660/icc_regs.h b/chip/max32660/icc_regs.h index 5f40e4203d..ed62f74f3c 100644 --- a/chip/max32660/icc_regs.h +++ b/chip/max32660/icc_regs.h @@ -32,112 +32,110 @@ */ typedef struct { __I uint32_t cache_id; /**< \b 0x0000:<\tt> ICC CACHE_ID Register */ - __I uint32_t memcfg; /**< \b 0x0004:<\tt> ICC MEMCFG Register */ + __I uint32_t memcfg; /**< \b 0x0004:<\tt> ICC MEMCFG Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO uint32_t - cache_ctrl; /**< \b 0x0100:<\tt> ICC CACHE_CTRL Register */ + __IO uint32_t cache_ctrl; /**< \b 0x0100:<\tt> ICC CACHE_CTRL + Register */ __R uint32_t rsv_0x104_0x6ff[383]; - __IO uint32_t - invalidate; /**< \b 0x0700:<\tt> ICC INVALIDATE Register */ + __IO uint32_t invalidate; /**< \b 0x0700:<\tt> ICC INVALIDATE + Register */ } mxc_icc_regs_t; /** * ICC Peripheral Register Offsets from the ICC Base Peripheral * Address. */ -#define MXC_R_ICC_CACHE_ID \ - ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: \ +#define MXC_R_ICC_CACHE_ID \ + ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: \ 0x0x000 */ -#define MXC_R_ICC_MEMCFG \ - ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: \ +#define MXC_R_ICC_MEMCFG \ + ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: \ 0x0x004 */ -#define MXC_R_ICC_CACHE_CTRL \ - ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: \ +#define MXC_R_ICC_CACHE_CTRL \ + ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: \ 0x0x100 */ -#define MXC_R_ICC_INVALIDATE \ - ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: \ +#define MXC_R_ICC_INVALIDATE \ + ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: \ 0x0x700 */ /** * Cache ID Register. */ #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ -#define MXC_F_ICC_CACHE_ID_RELNUM \ - ((uint32_t)( \ - 0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \ - Mask */ +#define MXC_F_ICC_CACHE_ID_RELNUM \ + ((uint32_t)(0x3FUL \ + << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM \ + Mask */ #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ -#define MXC_F_ICC_CACHE_ID_PARTNUM \ - ((uint32_t)(0xFUL \ - << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \ +#define MXC_F_ICC_CACHE_ID_PARTNUM \ + ((uint32_t)(0xFUL \ + << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM \ Mask */ #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ #define MXC_F_ICC_CACHE_ID_CCHID \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ + ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< \ + CACHE_ID_CCHID \ + Mask */ /** * Memory Configuration Register. */ #define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ #define MXC_F_ICC_MEMCFG_CCHSZ \ - ((uint32_t)(0xFFFFUL \ - << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ + ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ \ + Mask */ #define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ #define MXC_F_ICC_MEMCFG_MEMSZ \ - ((uint32_t)(0xFFFFUL \ - << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ + ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ \ + Mask */ /** * Cache Control and Status Register. */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS \ - 0 /**< CACHE_CTRL_CACHE_EN Position \ +#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS \ + 0 /**< CACHE_CTRL_CACHE_EN Position \ */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< \ - CACHE_CTRL_CACHE_EN \ - Mask */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ +#define MXC_F_ICC_CACHE_CTRL_CACHE_EN \ + ((uint32_t)(0x1UL \ + << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< \ + CACHE_CTRL_CACHE_EN \ + Mask */ +#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS \ - (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \ +#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS \ + (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS \ + << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS \ Setting */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ +#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN \ - (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ - << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \ +#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN \ + (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN \ + << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN \ Setting */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \ +#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS \ 16 /**< CACHE_CTRL_CACHE_RDY Position */ -#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< \ - CACHE_CTRL_CACHE_RDY \ - Mask */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ +#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY \ + ((uint32_t)(0x1UL \ + << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< \ + CACHE_CTRL_CACHE_RDY \ + Mask */ +#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */ #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY \ << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \ CACHE_CTRL_CACHE_RDY_NOTREADY \ Setting */ -#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ +#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */ -#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY \ - (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ - << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \ - CACHE_CTRL_CACHE_RDY_READY \ +#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY \ + (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY \ + << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< \ + CACHE_CTRL_CACHE_RDY_READY \ Setting */ #endif /* _ICC_REGS_H_ */ -- cgit v1.2.1 From bbf87229f20e06b14e3ed3b98cfcd5bbc3652d82 Mon Sep 17 00:00:00 2001 From: Peter Chi Date: Tue, 28 Jun 2022 17:53:12 +0800 Subject: crota: remove set_board_legacy_i2c_speeds Because crota have not PS8815, so we remove it. BUG=b:237357634 BRANCH=none TEST=make -j BOARD=crota Signed-off-by: Peter Chi Change-Id: I652bd83907aea05cef3dc043ae9aa09524356f49 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731771 Reviewed-by: Boris Mittelberg Commit-Queue: Boris Mittelberg --- board/crota/i2c.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/board/crota/i2c.c b/board/crota/i2c.c index 1fc1126282..e7172ef22b 100644 --- a/board/crota/i2c.c +++ b/board/crota/i2c.c @@ -63,19 +63,3 @@ const struct i2c_port_t i2c_ports[] = { }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/* - * I2C controllers are initialized in main.c. This sets the speed much - * later, but before I2C peripherals are initialized. - */ -static void set_board_legacy_i2c_speeds(void) -{ - if (get_board_id() >= BOARD_ID_FAST_PLUS_CAPABLE) - return; - - ccprints("setting USB DB I2C buses to 400 kHz\n"); - - i2c_set_freq(I2C_PORT_USB_C0_C1_TCPC, I2C_FREQ_400KHZ); - i2c_set_freq(I2C_PORT_USB_C0_C1_PPC, I2C_FREQ_400KHZ); -} -DECLARE_HOOK(HOOK_INIT, set_board_legacy_i2c_speeds, HOOK_PRIO_INIT_I2C - 1); -- cgit v1.2.1 From e308fcdc8a17a3a515d6afffaf7f9bf88799499f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:27 -0600 Subject: board/chronicler/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8bb0dc8c56d43fcff8973a593b9fc994f86ec714 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728146 Reviewed-by: Jeremy Bettis --- board/chronicler/board.c | 90 ++++++++++++++++++++++++------------------------ 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/board/chronicler/board.c b/board/chronicler/board.c index 5f7f717bca..eca532a58a 100644 --- a/board/chronicler/board.c +++ b/board/chronicler/board.c @@ -36,22 +36,22 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; const struct fan_rpm fan_rpm_0 = { - .rpm_min = 3000, + .rpm_min = 3000, .rpm_start = 5000, - .rpm_max = 5100, + .rpm_max = 5100, }; const struct fan_t fans[FAN_CH_COUNT] = { @@ -73,23 +73,23 @@ const struct fan_t fans[FAN_CH_COUNT] = { * TODO(b/202062363): Remove when clang is fixed. */ #define THERMAL_CONFIG_WITHOUT_FAN \ - { \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(77), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ }, \ .temp_host_release = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ - }, \ + }, \ } -__maybe_unused static const struct ec_thermal_config - thermal_config_without_fan = THERMAL_CONFIG_WITHOUT_FAN; +__maybe_unused static const struct ec_thermal_config thermal_config_without_fan = + THERMAL_CONFIG_WITHOUT_FAN; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CONFIG_WITH_FAN \ - { \ +#define THERMAL_CONFIG_WITH_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(77), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -120,12 +120,12 @@ struct fan_step { /* Fan control table */ static const struct fan_step fan_table0[] = { - {.on = 30, .off = 0, .rpm = 3150 }, /* Fan level 0 */ - {.on = 47, .off = 43, .rpm = 3500 }, /* Fan level 1 */ - {.on = 50, .off = 47, .rpm = 3750 }, /* Fan level 2 */ - {.on = 53, .off = 50, .rpm = 4200 }, /* Fan level 3 */ - {.on = 56, .off = 53, .rpm = 4500 }, /* Fan level 4 */ - {.on = 59, .off = 56, .rpm = 5000 }, /* Fan level 5 */ + { .on = 30, .off = 0, .rpm = 3150 }, /* Fan level 0 */ + { .on = 47, .off = 43, .rpm = 3500 }, /* Fan level 1 */ + { .on = 50, .off = 47, .rpm = 3750 }, /* Fan level 2 */ + { .on = 53, .off = 50, .rpm = 4200 }, /* Fan level 3 */ + { .on = 56, .off = 53, .rpm = 4500 }, /* Fan level 4 */ + { .on = 59, .off = 56, .rpm = 5000 }, /* Fan level 5 */ }; /* All fan tables must have the same number of levels */ @@ -148,7 +148,7 @@ int fan_percent_to_rpm(int fan, int pct) if (++cnt != FAN_AVERAGE_TIME_SEC) return fan_table[previous_level].rpm; - avg_pct = (int) avg_pct / FAN_AVERAGE_TIME_SEC; + avg_pct = (int)avg_pct / FAN_AVERAGE_TIME_SEC; /* * Compare the pct and previous pct, we have the three paths : @@ -287,8 +287,8 @@ static const struct ec_response_keybd_config main_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &main_kb; } @@ -303,15 +303,15 @@ __override const struct ec_response_keybd_config */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif /******************************************************************************/ @@ -322,19 +322,19 @@ static int manual_run_time = -1; #endif struct drop_step { - int run_time; /* battery run time (day) */ - int drop_volt; /* drop voltage (mV) */ + int run_time; /* battery run time (day) */ + int drop_volt; /* drop voltage (mV) */ }; /* voltage drop table */ static const struct drop_step voltage_drop_table[] = { - {.run_time = 90, .drop_volt = 13200 }, /* drop level 0 */ - {.run_time = 198, .drop_volt = 13125 }, /* drop level 1 */ - {.run_time = 305, .drop_volt = 13050 }, /* drop level 2 */ - {.run_time = 412, .drop_volt = 12975 }, /* drop level 3 */ - {.run_time = 519, .drop_volt = 12900 }, /* drop level 4 */ - {.run_time = 626, .drop_volt = 12825 }, /* drop level 5 */ - {.run_time = __INT_MAX__, .drop_volt = 12750 },/* drop level 6 */ + { .run_time = 90, .drop_volt = 13200 }, /* drop level 0 */ + { .run_time = 198, .drop_volt = 13125 }, /* drop level 1 */ + { .run_time = 305, .drop_volt = 13050 }, /* drop level 2 */ + { .run_time = 412, .drop_volt = 12975 }, /* drop level 3 */ + { .run_time = 519, .drop_volt = 12900 }, /* drop level 4 */ + { .run_time = 626, .drop_volt = 12825 }, /* drop level 5 */ + { .run_time = __INT_MAX__, .drop_volt = 12750 }, /* drop level 6 */ }; #define NUM_DROP_LEVELS ARRAY_SIZE(voltage_drop_table) @@ -346,19 +346,19 @@ static int get_battery_run_time_day(uint32_t *battery_run_time) uint8_t data[6]; /* get battery run time */ - rv = sb_read_mfgacc(PARAM_FIRMWARE_RUNTIME, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_FIRMWARE_RUNTIME, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return EC_ERROR_UNKNOWN; /* * The response is 6 bytes; the runtime in seconds is the last 4 bytes. */ - run_time = *(int32_t *) (&data[2]); + run_time = *(int32_t *)(&data[2]); #ifdef BATTERY_RUNTIME_TEST - cprints(CC_CHARGER, "run_time : 0x%08x (%d day)", - run_time, (run_time / 86400)); + cprints(CC_CHARGER, "run_time : 0x%08x (%d day)", run_time, + (run_time / 86400)); /* manual battery run time fot test */ if (manual_run_time != -1) @@ -388,8 +388,8 @@ int charger_profile_override(struct charge_state_data *curr) break; } - curr->requested_voltage = MIN(curr->requested_voltage, - voltage_drop_table[i].drop_volt); + curr->requested_voltage = + MIN(curr->requested_voltage, voltage_drop_table[i].drop_volt); #ifdef BATTERY_RUNTIME_TEST cprints(CC_CHARGER, "Charger: run time(day): %d, drop level: %d, CV: %d", @@ -399,13 +399,13 @@ int charger_profile_override(struct charge_state_data *curr) } enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { return EC_RES_INVALID_PARAM; } @@ -445,10 +445,10 @@ static int command_manual_run_time(int argc, char **argv) return EC_ERROR_PARAM1; cprints(CC_CHARGER, "manual run time set to %d sec (%d day)", - manual_run_time, (manual_run_time/86400)); + manual_run_time, (manual_run_time / 86400)); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(rt, command_manual_run_time, "", - "Set manual run time for test"); + "Set manual run time for test"); #endif -- cgit v1.2.1 From 76df01dcd0d782181406c877108b5743d55a2c5f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:36 -0600 Subject: board/copano/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia7e936e4e5e8911ef74da245415b1dd852280465 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728175 Reviewed-by: Jeremy Bettis --- board/copano/board.h | 116 ++++++++++++++++++++++++--------------------------- 1 file changed, 54 insertions(+), 62 deletions(-) diff --git a/board/copano/board.h b/board/copano/board.h index 315d7bc8bb..ccddf8244f 100644 --- a/board/copano/board.h +++ b/board/copano/board.h @@ -28,11 +28,11 @@ #define CONFIG_POWER_PP5000_CONTROL #undef NPCX_PWM1_SEL -#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */ +#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1 */ /* LED defines */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* Keyboard features */ #define CONFIG_KEYBOARD_VIVALDI @@ -57,23 +57,23 @@ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 15000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 15000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY @@ -82,15 +82,15 @@ /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x40 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ #define CONFIG_USB_PD_FRS_PPC #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG @@ -104,8 +104,8 @@ #undef CONFIG_FANS /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -113,47 +113,46 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_0_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -164,10 +163,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -176,11 +172,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 7e43b1907455ecb0fb5326600bb4c9d8aa010fd0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:37 -0600 Subject: driver/ppc/ktu1125.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4d6cba10d538b79de30b88df6d4dae6aa17524b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730026 Reviewed-by: Jeremy Bettis --- driver/ppc/ktu1125.h | 168 +++++++++++++++++++++++++-------------------------- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/driver/ppc/ktu1125.h b/driver/ppc/ktu1125.h index 826c6a925e..ca57677984 100644 --- a/driver/ppc/ktu1125.h +++ b/driver/ppc/ktu1125.h @@ -12,114 +12,114 @@ #include "driver/ppc/ktu1125_public.h" -#define KTU1125_ID 0x0 -#define KTU1125_CTRL_SW_CFG 0x1 -#define KTU1125_SET_SW_CFG 0x2 -#define KTU1125_SET_SW2_CFG 0x3 -#define KTU1125_MONITOR_SNK 0x4 -#define KTU1125_MONITOR_SRC 0x5 -#define KTU1125_MONITOR_DATA 0x6 -#define KTU1125_INTMASK_SNK 0x7 -#define KTU1125_INTMASK_SRC 0x8 -#define KTU1125_INTMASK_DATA 0x9 -#define KTU1125_INT_SNK 0xA -#define KTU1125_INT_SRC 0xB -#define KTU1125_INT_DATA 0xC +#define KTU1125_ID 0x0 +#define KTU1125_CTRL_SW_CFG 0x1 +#define KTU1125_SET_SW_CFG 0x2 +#define KTU1125_SET_SW2_CFG 0x3 +#define KTU1125_MONITOR_SNK 0x4 +#define KTU1125_MONITOR_SRC 0x5 +#define KTU1125_MONITOR_DATA 0x6 +#define KTU1125_INTMASK_SNK 0x7 +#define KTU1125_INTMASK_SRC 0x8 +#define KTU1125_INTMASK_DATA 0x9 +#define KTU1125_INT_SNK 0xA +#define KTU1125_INT_SRC 0xB +#define KTU1125_INT_DATA 0xC /* KTU1125_ID default value */ #define KTU1125_VENDOR_DIE_IDS 0xA5 /* KTU1125_CTRL_SW_CFG bits */ -#define KTU1125_SBU_SHUT BIT(0) -#define KTU1125_VCONN_EN BIT(1) -#define KTU1125_CC2S_VCONN BIT(2) -#define KTU1125_CC1S_VCONN BIT(3) -#define KTU1125_POW_MODE BIT(4) -#define KTU1125_SW_AB_EN BIT(5) -#define KTU1125_FRS_EN BIT(6) -#define KTU1125_EN_L BIT(7) +#define KTU1125_SBU_SHUT BIT(0) +#define KTU1125_VCONN_EN BIT(1) +#define KTU1125_CC2S_VCONN BIT(2) +#define KTU1125_CC1S_VCONN BIT(3) +#define KTU1125_POW_MODE BIT(4) +#define KTU1125_SW_AB_EN BIT(5) +#define KTU1125_FRS_EN BIT(6) +#define KTU1125_EN_L BIT(7) /* KTU1125_SET_SW_CFG bits and fields */ -#define KTU1125_RDB_DIS BIT(0) -#define KTU1125_SS_CLP_SNK BIT(1) -#define KTU1125_TDON BIT(2) -#define KTU1125_VCONN_CLP_SHIFT 3 -#define KTU1125_VCONN_CLP_LEN 2 -#define KTU1125_SYSB_CLP_SHIFT 5 -#define KTU1125_SYSB_CLP_LEN 3 +#define KTU1125_RDB_DIS BIT(0) +#define KTU1125_SS_CLP_SNK BIT(1) +#define KTU1125_TDON BIT(2) +#define KTU1125_VCONN_CLP_SHIFT 3 +#define KTU1125_VCONN_CLP_LEN 2 +#define KTU1125_SYSB_CLP_SHIFT 5 +#define KTU1125_SYSB_CLP_LEN 3 /* VBUS Switch Current Limit Settings - SYSB_CLP */ -#define KTU1125_SYSB_ILIM_0_6 0 -#define KTU1125_SYSB_ILIM_1_05 1 -#define KTU1125_SYSB_ILIM_1_70 2 -#define KTU1125_SYSB_ILIM_3_30 3 -#define KTU1125_SYSB_ILIM_3_60 4 +#define KTU1125_SYSB_ILIM_0_6 0 +#define KTU1125_SYSB_ILIM_1_05 1 +#define KTU1125_SYSB_ILIM_1_70 2 +#define KTU1125_SYSB_ILIM_3_30 3 +#define KTU1125_SYSB_ILIM_3_60 4 /* VCONN Current Limit Settings - VCONN_CLP */ -#define KTU1125_VCONN_ILIM_0_40 0 -#define KTU1125_VCONN_ILIM_0_60 1 -#define KTU1125_VCONN_ILIM_1_00 2 -#define KTU1125_VCONN_ILIM_1_40 3 +#define KTU1125_VCONN_ILIM_0_40 0 +#define KTU1125_VCONN_ILIM_0_60 1 +#define KTU1125_VCONN_ILIM_1_00 2 +#define KTU1125_VCONN_ILIM_1_40 3 /* KTU1125_SET_SW2_CFG bits and fields */ -#define KTU1125_OVP_BUS_SHIFT 0 -#define KTU1125_OVP_BUS_LEN 3 -#define KTU1125_DIS_RES_SHIFT 3 -#define KTU1125_DIS_RES_LEN 2 -#define KTU1125_VBUS_DIS_EN BIT(5) -#define KTU1125_T_HIC_SHIFT 6 -#define KTU1125_T_HIC_LEN 2 +#define KTU1125_OVP_BUS_SHIFT 0 +#define KTU1125_OVP_BUS_LEN 3 +#define KTU1125_DIS_RES_SHIFT 3 +#define KTU1125_DIS_RES_LEN 2 +#define KTU1125_VBUS_DIS_EN BIT(5) +#define KTU1125_T_HIC_SHIFT 6 +#define KTU1125_T_HIC_LEN 2 /* VBUS Over Voltage Protection */ -#define KTU1125_SYSB_VLIM_25_00 0 -#define KTU1125_SYSB_VLIM_17_00 4 -#define KTU1125_SYSB_VLIM_13_75 5 -#define KTU1125_SYSB_VLIM_10_60 6 -#define KTU1125_SYSB_VLIM_6_00 7 +#define KTU1125_SYSB_VLIM_25_00 0 +#define KTU1125_SYSB_VLIM_17_00 4 +#define KTU1125_SYSB_VLIM_13_75 5 +#define KTU1125_SYSB_VLIM_10_60 6 +#define KTU1125_SYSB_VLIM_6_00 7 /* Discharge resistor [ohms] */ -#define KTU1125_DIS_RES_1400 0 -#define KTU1125_DIS_RES_730 1 -#define KTU1125_DIS_RES_570 2 -#define KTU1125_DIS_RES_205 3 +#define KTU1125_DIS_RES_1400 0 +#define KTU1125_DIS_RES_730 1 +#define KTU1125_DIS_RES_570 2 +#define KTU1125_DIS_RES_205 3 /* T _HIC values [ms] */ -#define KTU_T_HIC_MS_17 0 -#define KTU_T_HIC_MS_34 1 -#define KTU_T_HIC_MS_51 2 -#define KTU_T_HIC_MS_68 3 +#define KTU_T_HIC_MS_17 0 +#define KTU_T_HIC_MS_34 1 +#define KTU_T_HIC_MS_51 2 +#define KTU_T_HIC_MS_68 3 /* Bits for MONITOR/INTMASK/INT SNK */ -#define KTU1125_SS_FAIL BIT(0) -#define KTU1125_OTP BIT(1) -#define KTU1125_FR_SWAP BIT(2) -#define KTU1125_SYSA_SCP BIT(3) -#define KTU1125_SYSA_OCP BIT(4) -#define KTU1125_VBUS_OVP BIT(5) -#define KTU1125_VBUS_UVLO BIT(6) -#define KTU1125_SYSA_OK BIT(7) -#define KTU1125_SNK_MASK_ALL 0xFF +#define KTU1125_SS_FAIL BIT(0) +#define KTU1125_OTP BIT(1) +#define KTU1125_FR_SWAP BIT(2) +#define KTU1125_SYSA_SCP BIT(3) +#define KTU1125_SYSA_OCP BIT(4) +#define KTU1125_VBUS_OVP BIT(5) +#define KTU1125_VBUS_UVLO BIT(6) +#define KTU1125_SYSA_OK BIT(7) +#define KTU1125_SNK_MASK_ALL 0xFF /* Bits for MONITOR/INTMASK/INT SRC */ -#define KTU1125_VCONN_SCP BIT(0) -#define KTU1125_VCONN_CLP BIT(1) -#define KTU1125_VCONN_UVLO BIT(2) -#define KTU1125_SYSB_SCP BIT(3) -#define KTU1125_SYSB_OCP BIT(4) -#define KTU1125_SYSB_CLP BIT(5) -#define KTU1125_SYSB_UVLO BIT(6) -#define KTU1125_VBUS_OK BIT(7) -#define KTU1125_SRC_MASK_ALL 0xFF +#define KTU1125_VCONN_SCP BIT(0) +#define KTU1125_VCONN_CLP BIT(1) +#define KTU1125_VCONN_UVLO BIT(2) +#define KTU1125_SYSB_SCP BIT(3) +#define KTU1125_SYSB_OCP BIT(4) +#define KTU1125_SYSB_CLP BIT(5) +#define KTU1125_SYSB_UVLO BIT(6) +#define KTU1125_VBUS_OK BIT(7) +#define KTU1125_SRC_MASK_ALL 0xFF /* Bits for MONITOR/INTMASK/INT DATA */ -#define KTU1125_SBUB BIT(0) -#define KTU1125_SBUA BIT(1) -#define KTU1125_SBU2_OVP BIT(2) -#define KTU1125_SBU1_OVP BIT(3) -#define KTU1125_CC2_OVP BIT(4) -#define KTU1125_CC1_OVP BIT(5) -#define KTU1125_CC2S_CLAMP BIT(6) -#define KTU1125_CC1S_CLAMP BIT(7) -#define KTU1125_DATA_MASK_ALL 0xFC +#define KTU1125_SBUB BIT(0) +#define KTU1125_SBUA BIT(1) +#define KTU1125_SBU2_OVP BIT(2) +#define KTU1125_SBU1_OVP BIT(3) +#define KTU1125_CC2_OVP BIT(4) +#define KTU1125_CC1_OVP BIT(5) +#define KTU1125_CC2S_CLAMP BIT(6) +#define KTU1125_CC1S_CLAMP BIT(7) +#define KTU1125_DATA_MASK_ALL 0xFC #endif /* defined(__CROS_EC_KTU1125_H) */ -- cgit v1.2.1 From 7599215afe9691ac53d0d6dd30927ef16d3676d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:29 -0600 Subject: common/usbc/usb_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0d753380b61d9e81b640972e77b6be3383289145 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729794 Reviewed-by: Jeremy Bettis --- common/usbc/usb_sm.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/common/usbc/usb_sm.c b/common/usbc/usb_sm.c index 04b7193c0f..11b2e604af 100644 --- a/common/usbc/usb_sm.c +++ b/common/usbc/usb_sm.c @@ -12,8 +12,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -23,8 +23,8 @@ struct internal_ctx { usb_state_ptr last_entered; uint32_t running : 1; - uint32_t enter : 1; - uint32_t exit : 1; + uint32_t enter : 1; + uint32_t exit : 1; }; BUILD_ASSERT(sizeof(struct internal_ctx) == member_size(struct sm_ctx, internal)); @@ -65,9 +65,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b) * functions. */ static void call_entry_functions(const int port, - struct internal_ctx *const internal, - const usb_state_ptr stop, - const usb_state_ptr current) + struct internal_ctx *const internal, + const usb_state_ptr stop, + const usb_state_ptr current) { if (current == stop) return; @@ -92,7 +92,7 @@ static void call_entry_functions(const int port, * during an exit function. */ static void call_exit_functions(const int port, const usb_state_ptr stop, - const usb_state_ptr current) + const usb_state_ptr current) { if (current == stop) return; @@ -106,7 +106,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop, void set_state(const int port, struct sm_ctx *const ctx, const usb_state_ptr new_state) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; usb_state_ptr last_state; usb_state_ptr shared_parent; @@ -116,8 +116,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * intended state to transition into. */ if (internal->exit) { - CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", - port, new_state, ctx->current); + CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", port, + new_state, ctx->current); return; } @@ -176,8 +176,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * functions. */ static void call_run_functions(const int port, - const struct internal_ctx *const internal, - const usb_state_ptr current) + const struct internal_ctx *const internal, + const usb_state_ptr current) { if (!current) return; @@ -194,7 +194,7 @@ static void call_run_functions(const int port, void run_state(const int port, struct sm_ctx *const ctx) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; internal->running = true; call_run_functions(port, internal, ctx->current); -- cgit v1.2.1 From a48c0789f234ee03999abed8214c6d818db22921 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:34 -0600 Subject: include/gpio.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id923ced9c6df4ef4b27bdd22cb39ed6749ab0a0f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730292 Reviewed-by: Jeremy Bettis --- include/gpio.h | 96 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 47 insertions(+), 49 deletions(-) diff --git a/include/gpio.h b/include/gpio.h index 4d827eb3cc..2f22a1b4e7 100644 --- a/include/gpio.h +++ b/include/gpio.h @@ -57,14 +57,14 @@ * Map the legacy EC GPIO flags to the Zephyr equivalent. * Refer to the descriptions below. */ -#define GPIO_FLAG_NONE GPIO_DISCONNECTED +#define GPIO_FLAG_NONE GPIO_DISCONNECTED /* GPIO_ANALOG not supported by Zephyr */ /* GPIO_OPEN_DRAIN already defined by Zephyr */ /* GPIO_DEFAULT not supported by Zephyr */ /* GPIO_PULL_UP already defined by Zephyr */ /* GPIO_PULL_DOWN already defined by Zephyr */ -#define GPIO_LOW GPIO_OUTPUT_INIT_LOW -#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH +#define GPIO_LOW GPIO_OUTPUT_INIT_LOW +#define GPIO_HIGH GPIO_OUTPUT_INIT_HIGH /* GPIO_INPUT already defined by Zephyr */ /* GPIO_OUTPUT already defined by Zephyr */ @@ -72,14 +72,14 @@ * One to one mapping of interrupt flags isn't possible. So map these * flags to not conflict with any Zephyr flags. */ -#define GPIO_INT_F_RISING BIT(28) +#define GPIO_INT_F_RISING BIT(28) #define GPIO_INT_F_FALLING BIT(29) -#define GPIO_INT_F_LOW BIT(30) -#define GPIO_INT_F_HIGH BIT(31) +#define GPIO_INT_F_LOW BIT(30) +#define GPIO_INT_F_HIGH BIT(31) /* GPIO_INT_DSLEEP not supported by Zephyr */ /* GPIO_INT_SHARED not supported by Zephyr */ -#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8 +#define GPIO_SEL_1P8V GPIO_VOLTAGE_1P8 /* GPIO_ALTERNATE not supported by Zephyr */ /* GPIO_LOCKED not supported by Zephyr */ /* GPIO_HIB_WAKE_HIGH not supported by Zephyr */ @@ -98,51 +98,52 @@ * GPIO_PULL_DOWN * GPIO_PULL_ANALOG */ -#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */ -#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */ -#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain */ -#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */ -#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */ -#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */ -#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */ -#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */ -#define GPIO_INPUT BIT(8) /* Input */ -#define GPIO_OUTPUT BIT(9) /* Output */ -#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */ +#define GPIO_FLAG_NONE 0 /* No flag needed, default setting */ +#define GPIO_ANALOG BIT(0) /* Set pin to analog-mode */ +#define GPIO_OPEN_DRAIN (BIT(1) | BIT(2)) /* Output type is open-drain */ +#define GPIO_DEFAULT BIT(3) /* Don't set up on boot */ +#define GPIO_PULL_UP BIT(4) /* Enable on-chip pullup */ +#define GPIO_PULL_DOWN BIT(5) /* Enable on-chip pulldown */ +#define GPIO_LOW BIT(6) /* If GPIO_OUTPUT, set level low */ +#define GPIO_HIGH BIT(7) /* If GPIO_OUTPUT, set level high */ +#define GPIO_INPUT BIT(8) /* Input */ +#define GPIO_OUTPUT BIT(9) /* Output */ +#define GPIO_INT_F_RISING BIT(10) /* Interrupt on rising edge */ #define GPIO_INT_F_FALLING BIT(11) /* Interrupt on falling edge */ -#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */ -#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */ -#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */ -#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */ -#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ -#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ -#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ -#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ -#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ -#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ +#define GPIO_INT_F_LOW BIT(12) /* Interrupt on low level */ +#define GPIO_INT_F_HIGH BIT(13) /* Interrupt on high level */ +#define GPIO_INT_DSLEEP BIT(14) /* Interrupt in deep sleep */ +#define GPIO_INT_SHARED BIT(15) /* Shared among multiple pins */ +#define GPIO_SEL_1P8V BIT(16) /* Support 1.8v */ +#define GPIO_ALTERNATE BIT(17) /* GPIO used for alternate function. */ +#define GPIO_LOCKED BIT(18) /* Lock GPIO output and configuration */ +#define GPIO_HIB_WAKE_HIGH BIT(19) /* Hibernate wake on high level */ +#define GPIO_HIB_WAKE_LOW BIT(20) /* Hibernate wake on low level */ +#define GPIO_HIB_WAKE_RISING BIT(21) /* Hibernate wake on rising edge */ #define GPIO_HIB_WAKE_FALLING BIT(22) /* Hibernate wake on falling edge */ #ifdef CONFIG_GPIO_POWER_DOWN -#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */ +#define GPIO_POWER_DOWN BIT(23) /* Pin and pad is powered off */ #endif #endif /* CONFIG_ZEPHYR */ /* Common flag combinations */ -#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) -#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH) -#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) -#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) -#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING) -#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING) +#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW) +#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH) +#define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) +#define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) +#define GPIO_INT_RISING (GPIO_INPUT | GPIO_INT_F_RISING) +#define GPIO_INT_FALLING (GPIO_INPUT | GPIO_INT_F_FALLING) /* TODO(crosbug.com/p/24204): "EDGE" would have been clearer than "BOTH". */ -#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING) -#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW) -#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH) -#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) -#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL) +#define GPIO_INT_BOTH (GPIO_INT_RISING | GPIO_INT_FALLING) +#define GPIO_INT_LOW (GPIO_INPUT | GPIO_INT_F_LOW) +#define GPIO_INT_HIGH (GPIO_INPUT | GPIO_INT_F_HIGH) +#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH) +#define GPIO_INT_ANY (GPIO_INT_BOTH | GPIO_INT_LEVEL) #define GPIO_INT_BOTH_DSLEEP (GPIO_INT_BOTH | GPIO_INT_DSLEEP) -#define GPIO_HIB_WAKE_MASK (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | \ - GPIO_HIB_WAKE_RISING|GPIO_HIB_WAKE_FALLING) +#define GPIO_HIB_WAKE_MASK \ + (GPIO_HIB_WAKE_HIGH | GPIO_HIB_WAKE_LOW | GPIO_HIB_WAKE_RISING | \ + GPIO_HIB_WAKE_FALLING) /* Convert GPIO mask to GPIO number / index. */ #define GPIO_MASK_TO_NUM(mask) (__fls(mask)) @@ -151,9 +152,7 @@ * some boards and unit tests don't have a gpio_signal enum defined, so we * define an emtpy one here.*/ #ifndef __CROS_EC_GPIO_SIGNAL_H -enum gpio_signal { - GPIO_COUNT -}; +enum gpio_signal { GPIO_COUNT }; #endif /* __CROS_EC_GPIO_SIGNAL_H */ /* Alternate functions for GPIOs */ @@ -207,7 +206,7 @@ extern const int unused_pin_count; * If the signal's interrupt is enabled, this will be called in the * context of the GPIO interrupt handler. */ -extern void (* const gpio_irq_handlers[])(enum gpio_signal signal); +extern void (*const gpio_irq_handlers[])(enum gpio_signal signal); extern const int gpio_ih_count; #define GPIO_IH_COUNT gpio_ih_count @@ -440,7 +439,6 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal); */ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags); - /** * Set alternate function for GPIO(s). * @@ -454,7 +452,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags); * the specified GPIOs for normal GPIO operation. */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func); + enum gpio_alternate_func func); #ifdef CONFIG_GPIO_POWER_DOWN /** @@ -486,4 +484,4 @@ int signal_is_gpio(int signal); */ void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags); -#endif /* __CROS_EC_GPIO_H */ +#endif /* __CROS_EC_GPIO_H */ -- cgit v1.2.1 From f84c09f0d9be09bbf0682931ce2922bd254802a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:13 -0600 Subject: board/taeko/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib91f546978434e0c0a52c6cb1112993652d98ca2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728980 Reviewed-by: Jeremy Bettis --- board/taeko/charger.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/taeko/charger.c diff --git a/board/taeko/charger.c b/board/taeko/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/taeko/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/taeko/charger.c b/board/taeko/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/taeko/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From e9749ed13be95b93105cb41cb202614b826494fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:02 -0600 Subject: test/vpd_api.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2fb342e3f47f19b2dd570c4cb127d1a2d18554ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730318 Reviewed-by: Jeremy Bettis --- test/vpd_api.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/vpd_api.c b/test/vpd_api.c index 65e86adb96..5eb61cd5d2 100644 --- a/test/vpd_api.c +++ b/test/vpd_api.c @@ -33,11 +33,11 @@ #endif #ifndef CC_RA -#define CC_RA(port, cc, sel) (cc < pd_src_rd_threshold[ct_cc_rp_value]) +#define CC_RA(port, cc, sel) (cc < pd_src_rd_threshold[ct_cc_rp_value]) #endif #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC)) #ifndef CC_NC -#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC) +#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC) #endif /* @@ -54,7 +54,7 @@ #define PD_SNK_VA PD_SNK_VA_MV #endif -#define CC_RP(cc) (cc >= PD_SNK_VA) +#define CC_RP(cc) (cc >= PD_SNK_VA) /* Mock Board State */ static enum vpd_pwr mock_vconn_pwr_sel_odl; @@ -266,7 +266,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull) return TYPEC_CC_VOLT_RA; else return TYPEC_CC_VOLT_RD; - /* If we have a pull-down, then we are sink, check for Rp. */ + /* If we have a pull-down, then we are sink, check for Rp. */ } else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) { if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD) return TYPEC_CC_VOLT_RP_3_0; -- cgit v1.2.1 From afe55ff147ea8f36bf781c88c3fd791e1f77ae50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:11 -0600 Subject: util/stm32mon.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2c6ac14bfd2aff4d9a35e6d7806e820cc394ed8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730655 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- util/stm32mon.c | 230 ++++++++++++++++++++++++++------------------------------ 1 file changed, 106 insertions(+), 124 deletions(-) diff --git a/util/stm32mon.c b/util/stm32mon.c index 129e602439..bda5e919e1 100644 --- a/util/stm32mon.c +++ b/util/stm32mon.c @@ -17,7 +17,7 @@ /* use cfmakeraw() */ #define _DEFAULT_SOURCE /* Newer glibc */ -#define _BSD_SOURCE /* Older glibc */ +#define _BSD_SOURCE /* Older glibc */ #include #include @@ -39,52 +39,48 @@ #include "ec_version.h" -#define KBYTES_TO_BYTES 1024 +#define KBYTES_TO_BYTES 1024 /* * Some Ubuntu versions do not export SPI_IOC_WR_MODE32 even though * the kernel shipped on those supports it. */ #ifndef SPI_IOC_WR_MODE32 -#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32) +#define SPI_IOC_WR_MODE32 _IOW(SPI_IOC_MAGIC, 5, __u32) #endif /* Monitor command set */ -#define CMD_INIT 0x7f /* Starts the monitor */ +#define CMD_INIT 0x7f /* Starts the monitor */ -#define CMD_GETCMD 0x00 /* Gets the allowed commands */ -#define CMD_GETVER 0x01 /* Gets the bootloader version */ -#define CMD_GETID 0x02 /* Gets the Chip ID */ -#define CMD_READMEM 0x11 /* Reads memory */ -#define CMD_GO 0x21 /* Jumps to user code */ +#define CMD_GETCMD 0x00 /* Gets the allowed commands */ +#define CMD_GETVER 0x01 /* Gets the bootloader version */ +#define CMD_GETID 0x02 /* Gets the Chip ID */ +#define CMD_READMEM 0x11 /* Reads memory */ +#define CMD_GO 0x21 /* Jumps to user code */ #define CMD_WRITEMEM 0x31 /* Writes memory (SRAM or Flash) */ -#define CMD_ERASE 0x43 /* Erases n pages of Flash memory */ +#define CMD_ERASE 0x43 /* Erases n pages of Flash memory */ #define CMD_EXTERASE 0x44 /* Erases n pages of Flash memory */ #define CMD_NO_STRETCH_ERASE 0x45 /* Erases while sending busy frame */ -#define CMD_WP 0x63 /* Enables write protect */ -#define CMD_WU 0x73 /* Disables write protect */ -#define CMD_RP 0x82 /* Enables the read protection */ -#define CMD_RU 0x92 /* Disables the read protection */ - -#define CMD_LOOKUP_ENTRY(COMMAND) {CMD_##COMMAND, #COMMAND} +#define CMD_WP 0x63 /* Enables write protect */ +#define CMD_WU 0x73 /* Disables write protect */ +#define CMD_RP 0x82 /* Enables the read protection */ +#define CMD_RU 0x92 /* Disables the read protection */ + +#define CMD_LOOKUP_ENTRY(COMMAND) \ + { \ + CMD_##COMMAND, #COMMAND \ + } const struct { const uint8_t cmd; const char *name; } cmd_lookup_table[] = { - CMD_LOOKUP_ENTRY(INIT), - CMD_LOOKUP_ENTRY(GETCMD), - CMD_LOOKUP_ENTRY(GETVER), - CMD_LOOKUP_ENTRY(GETID), - CMD_LOOKUP_ENTRY(READMEM), - CMD_LOOKUP_ENTRY(GO), - CMD_LOOKUP_ENTRY(WRITEMEM), - CMD_LOOKUP_ENTRY(ERASE), - CMD_LOOKUP_ENTRY(EXTERASE), - CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE), - CMD_LOOKUP_ENTRY(WP), - CMD_LOOKUP_ENTRY(WU), - CMD_LOOKUP_ENTRY(RP), - CMD_LOOKUP_ENTRY(RU), + CMD_LOOKUP_ENTRY(INIT), CMD_LOOKUP_ENTRY(GETCMD), + CMD_LOOKUP_ENTRY(GETVER), CMD_LOOKUP_ENTRY(GETID), + CMD_LOOKUP_ENTRY(READMEM), CMD_LOOKUP_ENTRY(GO), + CMD_LOOKUP_ENTRY(WRITEMEM), CMD_LOOKUP_ENTRY(ERASE), + CMD_LOOKUP_ENTRY(EXTERASE), CMD_LOOKUP_ENTRY(NO_STRETCH_ERASE), + CMD_LOOKUP_ENTRY(WP), CMD_LOOKUP_ENTRY(WU), + CMD_LOOKUP_ENTRY(RP), CMD_LOOKUP_ENTRY(RU), }; const char *cmd_lookup_name(uint8_t cmd) @@ -98,27 +94,27 @@ const char *cmd_lookup_name(uint8_t cmd) return NULL; } -#define RESP_NACK 0x1f -#define RESP_ACK 0x79 /* 0b 0111 1001 */ -#define RESP_BUSY 0x76 +#define RESP_NACK 0x1f +#define RESP_ACK 0x79 /* 0b 0111 1001 */ +#define RESP_BUSY 0x76 #define RESP_DAMAGED_ACK 0xBC /* 0b 1011 1100, 1 bit shifted REST_ACK */ /* SPI Start of Frame */ -#define SOF 0x5A +#define SOF 0x5A /* Extended erase special parameters */ -#define ERASE_ALL 0xffff -#define ERASE_BANK1 0xfffe -#define ERASE_BANK2 0xfffd +#define ERASE_ALL 0xffff +#define ERASE_BANK1 0xfffe +#define ERASE_BANK2 0xfffd /* Upper bound of rebooting the monitor */ #define MAX_DELAY_REBOOT 100000 /* us */ /* Standard addresses common across various ST chips */ -#define STM32_MAIN_MEMORY_ADDR 0x08000000 -#define STM32_SYSTEM_MEMORY_ADDR 0x1FFF0000 +#define STM32_MAIN_MEMORY_ADDR 0x08000000 +#define STM32_SYSTEM_MEMORY_ADDR 0x1FFF0000 -#define STM32_UNIQUE_ID_SIZE_BYTES 12 +#define STM32_UNIQUE_ID_SIZE_BYTES 12 /* * Device electronic signature contains factory-programmed identification @@ -166,7 +162,7 @@ struct memory_layout { /* known STM32 SoC parameters */ struct stm32_def { - uint16_t id; + uint16_t id; const char *name; uint32_t flash_size; uint32_t page_size; @@ -285,8 +281,8 @@ struct stm32_def { #define DEFAULT_BAUDRATE B38400 #define PAGE_SIZE 256 #define INVALID_I2C_ADAPTER -1 -#define MAX_ACK_RETRY_COUNT (EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT) -#define MAX_RETRY_COUNT 3 +#define MAX_ACK_RETRY_COUNT (EXT_ERASE_TIMEOUT / DEFAULT_TIMEOUT) +#define MAX_RETRY_COUNT 3 enum interface_mode { MODE_SERIAL, @@ -315,24 +311,24 @@ int retry_on_damaged_ack; /* STM32MON function return values */ enum { - STM32_SUCCESS = 0, - STM32_EIO = -1, /* IO error */ - STM32_EINVAL = -2, /* Got a faulty response from device */ - STM32_ETIMEDOUT = -3, /* Device didn't respond in a time window. */ - STM32_ENOMEM = -4, /* Failed to allocate memory. */ - STM32_ENACK = -5, /* Got NACK. */ - STM32_EDACK = -6, /* Got a damanged ACK. */ + STM32_SUCCESS = 0, + STM32_EIO = -1, /* IO error */ + STM32_EINVAL = -2, /* Got a faulty response from device */ + STM32_ETIMEDOUT = -3, /* Device didn't respond in a time window. */ + STM32_ENOMEM = -4, /* Failed to allocate memory. */ + STM32_ENACK = -5, /* Got NACK. */ + STM32_EDACK = -6, /* Got a damanged ACK. */ }; BUILD_ASSERT(STM32_SUCCESS == 0); -#define IS_STM32_ERROR(res) ((res) < STM32_SUCCESS) +#define IS_STM32_ERROR(res) ((res) < STM32_SUCCESS) /* optional command flags */ enum { - FLAG_UNPROTECT = 0x01, - FLAG_ERASE = 0x02, - FLAG_GO = 0x04, + FLAG_UNPROTECT = 0x01, + FLAG_ERASE = 0x02, + FLAG_GO = 0x04, FLAG_READ_UNPROTECT = 0x08, - FLAG_CR50_MODE = 0x10, + FLAG_CR50_MODE = 0x10, }; typedef struct { @@ -357,14 +353,11 @@ static FILE *log_file; /* Statistic data structure for response kind. */ struct { - const char * const event_name; + const char *const event_name; uint32_t event_count; } stat_resp[] = { - { "RESP_ACK", 0 }, - { "RESP_NACK", 0 }, - { "RESP_BUSY", 0 }, - { "RESP_DAMAGED_ACK", 0 }, - { "JUNK", 0 }, + { "RESP_ACK", 0 }, { "RESP_NACK", 0 }, { "RESP_BUSY", 0 }, + { "RESP_DAMAGED_ACK", 0 }, { "JUNK", 0 }, }; enum { @@ -389,7 +382,7 @@ static void dump_log(const char *prefix, const void *data, size_t count) fprintf(log_file, "%s: ", prefix); for (i = 0; i < count; i++) { - if (i && !(i % 16)) + if (i && !(i % 16)) fprintf(log_file, "\n "); fprintf(log_file, " %02x", ((uint8_t *)data)[i]); } @@ -560,7 +553,6 @@ static void discard_input(int fd) do { res = read_wrapper(fd, buffer, sizeof(buffer)); if (res > 0) { - /* Discard zeros in the beginning of the buffer. */ for (i = 0; i < res; i++) if (buffer[i]) @@ -652,8 +644,8 @@ int wait_for_ack(int fd) return STM32_ETIMEDOUT; } -int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, - uint8_t *resp, int resp_size, int ack_requested) +int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, uint8_t *resp, + int resp_size, int ack_requested) { int res, i, c; payload_t *p; @@ -755,7 +747,8 @@ int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, } else if (IS_STM32_ERROR(res)) { fprintf(stderr, "Failed to get response to command" - " 0x%02x ACK\n", cmd); + " 0x%02x ACK\n", + cmd); return res; } } @@ -767,8 +760,8 @@ int send_command(int fd, uint8_t cmd, payload_t *loads, int cnt, return readcnt; } -int send_command_retry(int fd, uint8_t cmd, payload_t *loads, - int cnt, uint8_t *resp, int resp_size, int ack_requested) +int send_command_retry(int fd, uint8_t cmd, payload_t *loads, int cnt, + uint8_t *resp, int resp_size, int ack_requested) { int res; int retries = MAX_RETRY_COUNT; @@ -777,7 +770,7 @@ int send_command_retry(int fd, uint8_t cmd, payload_t *loads, int ack_tries = MAX_ACK_RETRY_COUNT; res = send_command(fd, cmd, loads, cnt, resp, resp_size, - ack_requested); + ack_requested); while (res == STM32_ETIMEDOUT && ack_tries--) { if (cmd == CMD_WRITEMEM) { @@ -807,8 +800,8 @@ struct stm32_def *command_get_id(int fd) res = send_command(fd, CMD_GETID, NULL, 0, id, sizeof(id), 1); if (res > 0) { if (id[0] != 1) { - fprintf(stderr, "unknown ID : %02x %02x %02x\n", - id[0], id[1], id[2]); + fprintf(stderr, "unknown ID : %02x %02x %02x\n", id[0], + id[1], id[2]); return NULL; } chipid = (id[1] << 8) | id[2]; @@ -891,8 +884,8 @@ int command_get_commands(int fd, struct stm32_def *chip) cmds[0]); return STM32_EINVAL; } - printf("Bootloader v%d.%d, commands : ", - cmds[1] >> 4, cmds[1] & 0xf); + printf("Bootloader v%d.%d, commands : ", cmds[1] >> 4, + cmds[1] & 0xf); boot_loader_version = cmds[1]; erase = command_erase; @@ -920,10 +913,10 @@ int command_get_commands(int fd, struct stm32_def *chip) static int use_progressbar; static int windex; -static const char wheel[] = {'|', '/', '-', '\\' }; +static const char wheel[] = { '|', '/', '-', '\\' }; static void draw_spinner(uint32_t remaining, uint32_t size) { - int percent = (size - remaining)*100/size; + int percent = (size - remaining) * 100 / size; if (use_progressbar) { int dots = percent / 4; @@ -944,15 +937,12 @@ int command_read_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer) uint32_t remaining = size; uint32_t addr_be; uint8_t cnt; - payload_t loads[2] = { - {4, (uint8_t *)&addr_be}, - {1, &cnt} - }; + payload_t loads[2] = { { 4, (uint8_t *)&addr_be }, { 1, &cnt } }; while (remaining) { uint32_t bytes = MIN(remaining, PAGE_SIZE); - cnt = (uint8_t) (bytes - 1); + cnt = (uint8_t)(bytes - 1); addr_be = htonl(address); draw_spinner(remaining, size); @@ -978,10 +968,8 @@ int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer) uint32_t addr_be; uint32_t cnt; uint8_t outbuf[257]; - payload_t loads[2] = { - {4, (uint8_t *)&addr_be}, - {sizeof(outbuf), outbuf} - }; + payload_t loads[2] = { { 4, (uint8_t *)&addr_be }, + { sizeof(outbuf), outbuf } }; while (remaining) { cnt = MIN(remaining, PAGE_SIZE); @@ -997,7 +985,7 @@ int command_write_mem(int fd, uint32_t address, uint32_t size, uint8_t *buffer) draw_spinner(remaining, size); res = send_command_retry(fd, CMD_WRITEMEM, loads, 2, - NULL, 0, 1); + NULL, 0, 1); if (IS_STM32_ERROR(res)) return STM32_EIO; } @@ -1026,7 +1014,7 @@ int command_ext_erase(int fd, uint16_t count, uint16_t start) load.data = (uint8_t *)pages; pages[0] = htons(count - 1); for (i = 0; i < count; i++) - pages[i+1] = htons(start + i); + pages[i + 1] = htons(start + i); } printf("Erasing...\n"); @@ -1045,8 +1033,8 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start) uint8_t erase_cmd; uint16_t count_be = htons(count); payload_t load[2] = { - { 2, (uint8_t *)&count_be}, - { 0, NULL}, + { 2, (uint8_t *)&count_be }, + { 0, NULL }, }; int load_cnt = 1; uint16_t *pages = NULL; @@ -1071,7 +1059,7 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start) } erase_cmd = (boot_loader_version == 0x10) ? CMD_EXTERASE : - CMD_NO_STRETCH_ERASE; + CMD_NO_STRETCH_ERASE; printf("Erasing...\n"); res = send_command(fd, erase_cmd, load, load_cnt, NULL, 0, 1); @@ -1083,7 +1071,6 @@ int command_erase_i2c(int fd, uint16_t count, uint16_t start) return res; } - int command_erase(int fd, uint16_t count, uint16_t start) { int res; @@ -1101,7 +1088,7 @@ int command_erase(int fd, uint16_t count, uint16_t start) load.data = (uint8_t *)pages; pages[0] = count - 1; for (i = 0; i < count; i++) - pages[i+1] = start + i; + pages[i + 1] = start + i; } printf("Erasing...\n"); @@ -1241,8 +1228,10 @@ int read_device_signature_register(int fd, const struct stm32_def *chip, } if (addr <= otp_end_addr) { - fprintf(stderr, "Attempting to read from invalid address: " - "%08X\n", addr); + fprintf(stderr, + "Attempting to read from invalid address: " + "%08X\n", + addr); return STM32_EINVAL; } @@ -1290,9 +1279,9 @@ int read_flash_size_register(int fd, struct stm32_def *chip, if (!flash_size_addr) return STM32_EINVAL; - res = read_device_signature_register(fd, chip, - flash_size_addr, sizeof(*flash_size_kbytes), - (uint8_t *)flash_size_kbytes); + res = read_device_signature_register(fd, chip, flash_size_addr, + sizeof(*flash_size_kbytes), + (uint8_t *)flash_size_kbytes); if (!IS_STM32_ERROR(res)) printf("Flash size: %" PRIu16 " KB\n", *flash_size_kbytes); @@ -1306,7 +1295,7 @@ int read_flash_size_register(int fd, struct stm32_def *chip, /* Return zero on success, a negative error value on failures. */ int read_unique_device_id_register(int fd, struct stm32_def *chip, - uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES]) + uint8_t device_id[STM32_UNIQUE_ID_SIZE_BYTES]) { int i; int res; @@ -1317,7 +1306,8 @@ int read_unique_device_id_register(int fd, struct stm32_def *chip, return STM32_EINVAL; res = read_device_signature_register(fd, chip, unique_device_id_addr, - STM32_UNIQUE_ID_SIZE_BYTES, device_id); + STM32_UNIQUE_ID_SIZE_BYTES, + device_id); if (!IS_STM32_ERROR(res)) { printf("Unique Device ID: 0x"); @@ -1353,7 +1343,8 @@ int read_package_data_register(int fd, struct stm32_def *chip, else fprintf(stderr, "Failed to read package data register (0x%08X). " - "Ignoring non-critical failure.\n", package_data_addr); + "Ignoring non-critical failure.\n", + package_data_addr); return res; } @@ -1445,25 +1436,16 @@ int write_flash(int fd, struct stm32_def *chip, const char *filename, } static const struct option longopts[] = { - {"adapter", 1, 0, 'a'}, - {"baudrate", 1, 0, 'b'}, - {"cr50", 0, 0, 'c'}, - {"device", 1, 0, 'd'}, - {"erase", 0, 0, 'e'}, - {"go", 0, 0, 'g'}, - {"help", 0, 0, 'h'}, - {"length", 1, 0, 'n'}, - {"location", 1, 0, 'l'}, - {"logfile", 1, 0, 'L'}, - {"offset", 1, 0, 'o'}, - {"progressbar", 0, 0, 'p'}, - {"read", 1, 0, 'r'}, - {"retries", 1, 0, 'R'}, - {"spi", 1, 0, 's'}, - {"unprotect", 0, 0, 'u'}, - {"version", 0, 0, 'v'}, - {"write", 1, 0, 'w'}, - {NULL, 0, 0, 0} + { "adapter", 1, 0, 'a' }, { "baudrate", 1, 0, 'b' }, + { "cr50", 0, 0, 'c' }, { "device", 1, 0, 'd' }, + { "erase", 0, 0, 'e' }, { "go", 0, 0, 'g' }, + { "help", 0, 0, 'h' }, { "length", 1, 0, 'n' }, + { "location", 1, 0, 'l' }, { "logfile", 1, 0, 'L' }, + { "offset", 1, 0, 'o' }, { "progressbar", 0, 0, 'p' }, + { "read", 1, 0, 'r' }, { "retries", 1, 0, 'R' }, + { "spi", 1, 0, 's' }, { "unprotect", 0, 0, 'u' }, + { "version", 0, 0, 'v' }, { "write", 1, 0, 'w' }, + { NULL, 0, 0, 0 } }; void display_usage(char *program) @@ -1498,9 +1480,9 @@ void display_usage(char *program) "the spinner\n"); fprintf(stderr, "--R[etries] : limit connect retries to num\n"); fprintf(stderr, "-L[ogfile] : save all communications exchange " - "in a log file\n"); + "in a log file\n"); fprintf(stderr, "-c[r50_mode] : consider device to be a Cr50 interface," - " no need to set UART port attributes\n"); + " no need to set UART port attributes\n"); fprintf(stderr, "--v[ersion] : print version and exit\n"); exit(2); @@ -1509,7 +1491,7 @@ void display_usage(char *program) void display_version(const char *exe_name) { printf("%s version: %s %s %s\n", exe_name, CROS_STM32MON_VERSION, DATE, - BUILDER); + BUILDER); } speed_t parse_baudrate(const char *value) @@ -1528,8 +1510,8 @@ speed_t parse_baudrate(const char *value) case 115200: return B115200; default: - fprintf(stderr, "Invalid baudrate %s, using %d\n", - value, DEFAULT_BAUDRATE); + fprintf(stderr, "Invalid baudrate %s, using %d\n", value, + DEFAULT_BAUDRATE); return DEFAULT_BAUDRATE; } } @@ -1626,7 +1608,7 @@ static void display_stat_response(void) printf("--\n"); for (idx = 0; idx < total_events; ++idx) { printf("%-18s %d\n", stat_resp[idx].event_name, - stat_resp[idx].event_count); + stat_resp[idx].event_count); } printf("--\n"); } -- cgit v1.2.1 From d5260b48d08ba5026e4c98470c79c37015715545 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:47 -0600 Subject: board/rammus/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b854a3f15f9f631f803081d29a71d90e4b7d8c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728855 Reviewed-by: Jeremy Bettis --- board/rammus/led.c | 39 +++++++++++++++++---------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/board/rammus/led.c b/board/rammus/led.c index e6187ce4b5..add243d9d8 100644 --- a/board/rammus/led.c +++ b/board/rammus/led.c @@ -23,9 +23,8 @@ #define LED_CHARGE_PULSE 10 #define LED_POWER_PULSE 15 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -47,24 +46,20 @@ enum led_power_state { }; static const struct { - uint8_t led1:1; - uint8_t led2:1; -} led_chg_state_table[] = { - [LED_STATE_DISCHARGE] = {LED_OFF, LED_OFF}, - [LED_STATE_CHARGE] = {LED_OFF, LED_ON}, - [LED_STATE_FULL] = {LED_ON, LED_OFF}, - [LED_STATE_ERROR_PHASE0] = {LED_OFF, LED_OFF}, - [LED_STATE_ERROR_PHASE1] = {LED_OFF, LED_ON} -}; + uint8_t led1 : 1; + uint8_t led2 : 1; +} led_chg_state_table[] = { [LED_STATE_DISCHARGE] = { LED_OFF, LED_OFF }, + [LED_STATE_CHARGE] = { LED_OFF, LED_ON }, + [LED_STATE_FULL] = { LED_ON, LED_OFF }, + [LED_STATE_ERROR_PHASE0] = { LED_OFF, LED_OFF }, + [LED_STATE_ERROR_PHASE1] = { LED_OFF, LED_ON } }; static const struct { - uint8_t led:1; -} led_pwr_state_table[] = { - [LED_STATE_S0] = {LED_ON}, - [LED_STATE_S3_PHASE0] = {LED_OFF}, - [LED_STATE_S3_PHASE1] = {LED_ON}, - [LED_STATE_S5] = {LED_OFF} -}; + uint8_t led : 1; +} led_pwr_state_table[] = { [LED_STATE_S0] = { LED_ON }, + [LED_STATE_S3_PHASE0] = { LED_OFF }, + [LED_STATE_S3_PHASE1] = { LED_ON }, + [LED_STATE_S5] = { LED_OFF } }; void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { @@ -100,7 +95,7 @@ static void rammus_led_set_power(void) chipset_state = chipset_in_state(CHIPSET_STATE_HARD_OFF) | (chipset_in_state(CHIPSET_STATE_SOFT_OFF) << 1) | - (chipset_in_state(CHIPSET_STATE_SUSPEND) << 2) | + (chipset_in_state(CHIPSET_STATE_SUSPEND) << 2) | (chipset_in_state(CHIPSET_STATE_ON) << 3) | (chipset_in_state(CHIPSET_STATE_STANDBY) << 4); @@ -136,7 +131,7 @@ static void rammus_led_set_battery(void) switch (chg_state) { case PWR_STATE_DISCHARGE: if ((charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) && - charge_percent >= BATTERY_LEVEL_NEAR_FULL) + charge_percent >= BATTERY_LEVEL_NEAR_FULL) config_battery_led(LED_STATE_FULL); else config_battery_led(LED_STATE_DISCHARGE); @@ -154,7 +149,7 @@ static void rammus_led_set_battery(void) break; case PWR_STATE_CHARGE_NEAR_FULL: case PWR_STATE_IDLE: - if(charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) + if (charge_get_flags() & CHARGE_FLAG_EXTERNAL_POWER) config_battery_led(LED_STATE_FULL); else config_battery_led(LED_STATE_DISCHARGE); -- cgit v1.2.1 From dd43c278bcb6cc2f631a471f815ad3fbaeb70e3c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:32 -0600 Subject: board/corori2/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ff75c22beb6a8a4b1cd4ddee6725933bf50f63a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728185 Reviewed-by: Jeremy Bettis --- board/corori2/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/corori2/usb_pd_policy.c b/board/corori2/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/corori2/usb_pd_policy.c +++ b/board/corori2/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 5e6bd7fa7245a3ea81511d5df84e1d75659a1b1d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:45 -0600 Subject: board/volmar/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I58d81fa8a14fa9ce2c6f61fcae32083921e5801c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729074 Reviewed-by: Jeremy Bettis --- board/volmar/board.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/board/volmar/board.c b/board/volmar/board.c index 8875d49caf..c1a4daf040 100644 --- a/board/volmar/board.c +++ b/board/volmar/board.c @@ -27,8 +27,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) __override void board_cbi_init(void) { @@ -53,7 +53,6 @@ static void board_chipset_suspend(void) } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); - /* keyboard factory test */ #ifdef CONFIG_KEYBOARD_FACTORY_TEST /* @@ -62,15 +61,14 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 6ed3315f0d00401e3d8f640278db0b606479906d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:58 -0600 Subject: common/typec_control.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I71f248224d0055fe7af4cae3bae68aaea15b4874 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729521 Reviewed-by: Jeremy Bettis --- common/typec_control.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/typec_control.c b/common/typec_control.c index 1fea258389..ff323b632b 100644 --- a/common/typec_control.c +++ b/common/typec_control.c @@ -28,7 +28,7 @@ void typec_set_sbu(int port, bool enable) } __overridable void typec_set_source_current_limit(int port, - enum tcpc_rp_value rp) + enum tcpc_rp_value rp) { if (IS_ENABLED(CONFIG_USBC_PPC)) ppc_set_vbus_source_current_limit(port, rp); @@ -45,8 +45,8 @@ void typec_set_vconn(int port, bool enable) * the PD state machine detects a disconnection on the CC lines, we will * reset our OC event counter. */ - if (IS_ENABLED(CONFIG_USBC_OCP) && - enable && usbc_ocp_is_port_latched_off(port)) + if (IS_ENABLED(CONFIG_USBC_OCP) && enable && + usbc_ocp_is_port_latched_off(port)) return; /* -- cgit v1.2.1 From 53ad5301be22ea949bdda2856f469d25c80336bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:10 -0600 Subject: core/minute-ia/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e322ce702445cb43355d6409907c8f5c9939e47 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729854 Reviewed-by: Jeremy Bettis --- core/minute-ia/irq_handler.h | 46 +++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/core/minute-ia/irq_handler.h b/core/minute-ia/irq_handler.h index 30106603d6..5640f8dbb4 100644 --- a/core/minute-ia/irq_handler.h +++ b/core/minute-ia/irq_handler.h @@ -12,7 +12,7 @@ #include "task.h" #include "task_defs.h" -asm (".include \"core/minute-ia/irq_handler_common.S\""); +asm(".include \"core/minute-ia/irq_handler_common.S\""); /* Helper macros to build the IRQ handler and priority struct names */ #define IRQ_HANDLER(irqname) CONCAT3(_irq_, irqname, _handler) @@ -30,26 +30,24 @@ asm (".include \"core/minute-ia/irq_handler_common.S\""); * Each irq has a irq_data structure placed in .rodata.irqs section, * to be used for dynamically setting up interrupt gates */ -#define DECLARE_IRQ_(irq_, routine_, vector) \ - static void __keep routine_(void); \ - void IRQ_HANDLER(irq_)(void); \ - __asm__ (".section .rodata.irqs\n"); \ - const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_) \ - __attribute__((section(".rodata.irqs"))) = { \ - .irq = irq_, \ - .routine = routine_, \ - .handler = IRQ_HANDLER(irq_) \ - }; \ - __asm__ ( \ - ".section .text._irq_" #irq_ "_handler\n" \ - "_irq_" #irq_ "_handler:\n" \ - "pusha\n" \ - ASM_LOCK_PREFIX "addl $1, __in_isr\n" \ - "irq_handler_common $0 $0 $" #irq_ "\n" \ - "movl $"#vector ", " STRINGIFY(IOAPIC_EOI_REG_ADDR) "\n" \ - "movl $0x00, " STRINGIFY(LAPIC_EOI_REG_ADDR) "\n" \ - ASM_LOCK_PREFIX "subl $1, __in_isr\n" \ - "popa\n" \ - "iret\n" \ - ) -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#define DECLARE_IRQ_(irq_, routine_, vector) \ + static void __keep routine_(void); \ + void IRQ_HANDLER(irq_)(void); \ + __asm__(".section .rodata.irqs\n"); \ + const struct irq_def __keep CONCAT4(__irq_, irq_, _, routine_) \ + __attribute__((section( \ + ".rodata.irqs"))) = { .irq = irq_, \ + .routine = routine_, \ + .handler = IRQ_HANDLER(irq_) }; \ + __asm__(".section .text._irq_" #irq_ "_handler\n" \ + "_irq_" #irq_ "_handler:\n" \ + "pusha\n" ASM_LOCK_PREFIX "addl $1, __in_isr\n" \ + "irq_handler_common $0 $0 $" #irq_ "\n" \ + "movl $" #vector ", " STRINGIFY( \ + IOAPIC_EOI_REG_ADDR) "\n" \ + "movl $0x00, " STRINGIFY( \ + LAPIC_EOI_REG_ADDR) "\n" ASM_LOCK_PREFIX \ + "subl $1, __in_isr\n" \ + "popa\n" \ + "iret\n") +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From e849888cebcff71a9594977463d547458fbba4d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:24 -0600 Subject: chip/mt_scp/mt8195/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I828f93e5a25ea81b2611234a655270d1083de5fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729355 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8195/clock.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/chip/mt_scp/mt8195/clock.c b/chip/mt_scp/mt8195/clock.c index f3b32ab52e..7a97a437cc 100644 --- a/chip/mt_scp/mt8195/clock.c +++ b/chip/mt_scp/mt8195/clock.c @@ -106,8 +106,8 @@ static void clock_ulposc_config_default(struct opp_ulposc_cfg *opp) AP_ULPOSC_CON1(opp->osc) = val; /* set settle time */ - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(2); + SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | + CLK_HIGH_VAL_VAL(2); } static void clock_ulposc_config_cali(struct opp_ulposc_cfg *opp, @@ -137,13 +137,12 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc) AP_CLK26CALI_1 = CFG_CKGEN_LOAD_CNT; /* before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; + AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK; /* select monclk_ext2fqmtr_sel: AP_CLK_DBG_CFG[14:8] */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); + AP_CLK_DBG_CFG = + (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | + (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2); /* set meter divisor to 1, bit[31:24] = b00000000 */ AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | @@ -176,7 +175,7 @@ static uint32_t clock_ulposc_measure_freq(uint32_t osc) return result; } -#define CAL_MIS_RATE 40 +#define CAL_MIS_RATE 40 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) { uint32_t curr, target; @@ -185,8 +184,8 @@ static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) target = opp->target_mhz * 512 / 26; #ifdef DEBUG - CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n", - opp->osc, opp->target_mhz, (curr * 26) / 512, opp->cali); + CPRINTF("osc:%u, target=%uMHz, curr=%uMHz, cali:%u\n", opp->osc, + opp->target_mhz, (curr * 26) / 512, opp->cali); #endif /* check if calibrated value is in the range of target value +- 4% */ @@ -401,7 +400,7 @@ void sr_task(void *u) uint32_t event; uint32_t prev, now; - while(1) { + while (1) { switch (state) { case SR_S0: event = task_wait_event(-1); @@ -463,12 +462,12 @@ void clock_init(void) SCP_SYS_CTRL |= AUTO_DDREN; /* set settle time */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL_VAL(1); - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL_VAL(1); - SCP_SLEEP_CTRL = - (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | VREQ_COUNT_VAL(1); + SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | + CLK_SYS_VAL_VAL(1); + SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | + CLK_HIGH_VAL_VAL(1); + SCP_SLEEP_CTRL = (SCP_SLEEP_CTRL & ~VREQ_COUNT_MASK) | + VREQ_COUNT_VAL(1); /* turn off ULPOSC2 */ SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; -- cgit v1.2.1 From 511f4848a39d274cb38e46d944e8aa3ae255b19e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:21 -0600 Subject: chip/mt_scp/mt8192/video.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idab5cef6fc93844316e31ba4a40335ea496c3c87 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729354 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8192/video.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/chip/mt_scp/mt8192/video.c b/chip/mt_scp/mt8192/video.c index 2f9b9a7808..626a4da1fd 100644 --- a/chip/mt_scp/mt8192/video.c +++ b/chip/mt_scp/mt8192/video.c @@ -13,7 +13,6 @@ uint32_t video_get_enc_capability(void) uint32_t video_get_dec_capability(void) { - return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 | - VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME | - VDEC_CAP_VP9_FRAME; + return VDEC_CAP_4K_DISABLED | VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE | + VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME; } -- cgit v1.2.1 From 8edc4b6aead5ebdf33eb93e8a0f971a26af527e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:59 -0600 Subject: board/puff/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40df14ea7e3e30107e39a7c51894984086fa715d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728847 Reviewed-by: Jeremy Bettis --- board/puff/board.c | 182 +++++++++++++++++++++++------------------------------ 1 file changed, 80 insertions(+), 102 deletions(-) diff --git a/board/puff/board.c b/board/puff/board.c index a893de33c3..be7371f521 100644 --- a/board/puff/board.c +++ b/board/puff/board.c @@ -45,8 +45,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -88,8 +88,8 @@ uint16_t tcpc_get_alert_status(void) } /* Called when the charge manager has switched to a new port. */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = @@ -105,14 +105,14 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1603) -#define PWR_FRONT_LOW (5*963) -#define PWR_REAR (5*1075) -#define PWR_HDMI (5*562) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1603) +#define PWR_FRONT_LOW (5 * 963) +#define PWR_REAR (5 * 1075) +#define PWR_HDMI (5 * 562) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -185,16 +185,14 @@ static const struct { int current; } bj_power[] = { { /* 0 - 65W (also default) */ - .voltage = 19000, - .current = 3420 - }, + .voltage = 19000, + .current = 3420 }, { /* 1 - 90W */ - .voltage = 19000, - .current = 4740 - }, + .voltage = 19000, + .current = 4740 }, }; -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -239,29 +237,26 @@ static void adp_state_init(void) } DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); - #include "gpio_list.h" /* Must come after other header files. */ /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_GREEN] = { .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | - PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_GREEN] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ @@ -288,41 +283,31 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -378,15 +363,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -405,7 +389,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -414,8 +398,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(68), \ @@ -434,8 +418,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ @@ -537,16 +521,13 @@ static void board_chipset_startup(void) if (ppc_is_sourcing_vbus(0)) ppc_vbus_source_enable(0, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -579,14 +560,12 @@ static void board_tcpc_init(void) /* * By default configured as output low. */ - gpio_set_flags(GPIO_USB_A4_OC_ODL, - GPIO_INPUT | GPIO_INT_BOTH); + gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH); gpio_enable_interrupt(GPIO_USB_A4_OC_ODL); } else { /* Ensure no interrupts from pin */ gpio_disable_interrupt(GPIO_USB_A4_OC_ODL); } - } /* Make sure this is called after fw_config is initialised */ DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2); @@ -705,8 +684,8 @@ void board_enable_s0_rails(int enable) unsigned int ec_config_get_bj_power(void) { - unsigned int bj = - (fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L; + unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >> + EC_CFG_BJ_POWER_L; /* Out of range value defaults to 0 */ if (bj >= ARRAY_SIZE(bj_power)) bj = 0; @@ -781,23 +760,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1); * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -812,8 +791,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -841,7 +819,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -868,8 +846,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -961,8 +938,9 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); -- cgit v1.2.1 From 7093ec07c40dd75da5efd0643f9a5bc818b6e6f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:50 -0600 Subject: include/libsharedobjs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I458a7e9ae4c645d1ed1b315091c3aa93492f92e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730300 Reviewed-by: Jeremy Bettis --- include/libsharedobjs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/libsharedobjs.h b/include/libsharedobjs.h index 3801ccaca0..c0017e5171 100644 --- a/include/libsharedobjs.h +++ b/include/libsharedobjs.h @@ -17,7 +17,7 @@ * NOTE: I know that this doesn't cover all possible cases, but it will catch * an obvious case. */ -#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF) +#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF) #error "The shared library is NOT compatible with this EC." #endif @@ -28,12 +28,12 @@ */ #undef SHAREDLIB #ifdef SHAREDLIB_IMAGE -#define SHAREDLIB(...) __attribute__ ((section(".roshared"))) __VA_ARGS__ +#define SHAREDLIB(...) __attribute__((section(".roshared"))) __VA_ARGS__ #else /* !defined(SHAREDLIB_IMAGE) */ #define SHAREDLIB(...) #endif /* defined(SHAREDLIB_IMAGE) */ #define SHAREDLIB_FUNC(...) \ - extern __VA_ARGS__ __attribute__ ((section(".roshared.text"))) + extern __VA_ARGS__ __attribute__((section(".roshared.text"))) #else /* !defined(CONFIG_SHAREDLIB) */ -- cgit v1.2.1 From b56e6d4d8e918a7b83b6d1c0016f033047a93612 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:08 -0600 Subject: chip/stm32/usb_spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I35d22d933175a0e356fe8725db3aff0de42379a7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729580 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_spi.c | 150 +++++++++++++++++++++++++-------------------------- 1 file changed, 72 insertions(+), 78 deletions(-) diff --git a/chip/stm32/usb_spi.c b/chip/stm32/usb_spi.c index e80d15b6cd..d5ea71f2ba 100644 --- a/chip/stm32/usb_spi.c +++ b/chip/stm32/usb_spi.c @@ -17,9 +17,9 @@ static bool usb_spi_received_packet(struct usb_spi_config const *config); static bool usb_spi_transmitted_packet(struct usb_spi_config const *config); static void usb_spi_read_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); + struct usb_spi_packet_ctx *packet); static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet); + struct usb_spi_packet_ctx *packet); /* * Map EC error codes to USB_SPI error codes. @@ -31,10 +31,14 @@ static void usb_spi_write_packet(struct usb_spi_config const *config, static int16_t usb_spi_map_error(int error) { switch (error) { - case EC_SUCCESS: return USB_SPI_SUCCESS; - case EC_ERROR_TIMEOUT: return USB_SPI_TIMEOUT; - case EC_ERROR_BUSY: return USB_SPI_BUSY; - default: return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); + case EC_SUCCESS: + return USB_SPI_SUCCESS; + case EC_ERROR_TIMEOUT: + return USB_SPI_TIMEOUT; + case EC_ERROR_BUSY: + return USB_SPI_BUSY; + default: + return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff); } } @@ -47,7 +51,7 @@ static int16_t usb_spi_map_error(int error) * @returns USB_SPI_RX_DATA_OVERFLOW if the source packet is too large */ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, - const struct usb_spi_packet_ctx *src) + const struct usb_spi_packet_ctx *src) { size_t max_read_length = dst->transfer_size - dst->transfer_index; size_t bytes_in_buffer = src->packet_size - src->header_size; @@ -61,7 +65,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, return USB_SPI_RX_DATA_OVERFLOW; } memcpy(dst->buffer + dst->transfer_index, packet_buffer, - bytes_in_buffer); + bytes_in_buffer); dst->transfer_index += bytes_in_buffer; return USB_SPI_SUCCESS; @@ -74,7 +78,7 @@ static int usb_spi_read_usb_packet(struct usb_spi_transfer_ctx *dst, * @param src Source transmit context we are reading data from. */ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst, - struct usb_spi_transfer_ctx *src) + struct usb_spi_transfer_ctx *src) { size_t transfer_size = src->transfer_size - src->transfer_index; size_t max_buffer_size = USB_MAX_PACKET_SIZE - dst->header_size; @@ -97,7 +101,7 @@ static void usb_spi_fill_usb_packet(struct usb_spi_packet_ctx *dst, * @param read_count Number of bytes to read in the SPI transfer */ static void usb_spi_setup_transfer(struct usb_spi_config const *config, - size_t write_count, size_t read_count) + size_t write_count, size_t read_count) { /* Reset any status code. */ config->state->status_code = USB_SPI_SUCCESS; @@ -145,7 +149,7 @@ static bool usb_spi_response_in_progress(struct usb_spi_config const *config) * @param status_code status code to set for the response. */ static void setup_transfer_response(struct usb_spi_config const *config, - uint16_t status_code) + uint16_t status_code) { config->state->status_code = status_code; config->state->spi_read_ctx.transfer_index = 0; @@ -163,7 +167,7 @@ static void setup_transfer_response(struct usb_spi_config const *config, * @param packet Packet buffer we will be transmitting. */ static void create_spi_config_response(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { /* Construct the response packet. */ packet->rsp_config.packet_id = USB_SPI_PKT_ID_RSP_USB_SPI_CONFIG; @@ -175,8 +179,7 @@ static void create_spi_config_response(struct usb_spi_config const *config, packet->rsp_config.feature_bitmap |= USB_SPI_FEATURE_FULL_DUPLEX_SUPPORTED; #endif - packet->packet_size = - sizeof(struct usb_spi_response_configuration_v2); + packet->packet_size = sizeof(struct usb_spi_response_configuration_v2); } static void create_spi_chip_select_response(struct usb_spi_config const *config, @@ -196,16 +199,14 @@ static void create_spi_chip_select_response(struct usb_spi_config const *config, * @param config USB SPI config * @param packet Packet buffer we will be transmitting. */ -static void usb_spi_create_spi_transfer_response( - struct usb_spi_config const *config, - struct usb_spi_packet_ctx *transmit_packet) +static void +usb_spi_create_spi_transfer_response(struct usb_spi_config const *config, + struct usb_spi_packet_ctx *transmit_packet) { - if (!usb_spi_response_in_progress(config)) return; if (config->state->spi_read_ctx.transfer_index == 0) { - /* Transmit the first packet with the status code. */ transmit_packet->header_size = offsetof(struct usb_spi_response_v2, data); @@ -215,10 +216,9 @@ static void usb_spi_create_spi_transfer_response( config->state->status_code; usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); + &config->state->spi_read_ctx); } else if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { - + config->state->spi_read_ctx.transfer_size) { /* Transmit the continue packets. */ transmit_packet->header_size = offsetof(struct usb_spi_continue_v2, data); @@ -228,10 +228,10 @@ static void usb_spi_create_spi_transfer_response( config->state->spi_read_ctx.transfer_index; usb_spi_fill_usb_packet(transmit_packet, - &config->state->spi_read_ctx); + &config->state->spi_read_ctx); } if (config->state->spi_read_ctx.transfer_index < - config->state->spi_read_ctx.transfer_size) { + config->state->spi_read_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_CONTINUE_RESPONSE; } else { config->state->mode = USB_SPI_MODE_IDLE; @@ -245,7 +245,7 @@ static void usb_spi_create_spi_transfer_response( * @param packet Received packet to process. */ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { if (packet->packet_size < USB_SPI_MIN_PACKET_SIZE) { /* No valid packet exists smaller than the packet id. */ @@ -256,14 +256,12 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, config->state->mode = USB_SPI_MODE_IDLE; switch (packet->packet_id) { - case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: - { + case USB_SPI_PKT_ID_CMD_GET_USB_SPI_CONFIG: { /* The host requires the SPI configuration. */ config->state->mode = USB_SPI_MODE_SEND_CONFIGURATION; break; } - case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: - { + case USB_SPI_PKT_ID_CMD_RESTART_RESPONSE: { /* * The host has requested the device restart the last response. * This is used to recover from lost USB packets without @@ -272,8 +270,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, setup_transfer_response(config, config->state->status_code); break; } - case USB_SPI_PKT_ID_CMD_TRANSFER_START: - { + case USB_SPI_PKT_ID_CMD_TRANSFER_START: { /* The host started a new USB SPI transfer */ size_t write_count = packet->cmd_start.write_count; size_t read_count = packet->cmd_start.read_count; @@ -282,42 +279,41 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, setup_transfer_response(config, USB_SPI_DISABLED); } else if (write_count > USB_SPI_MAX_WRITE_COUNT) { setup_transfer_response(config, - USB_SPI_WRITE_COUNT_INVALID); + USB_SPI_WRITE_COUNT_INVALID); #ifdef CONFIG_SPI_HALFDUPLEX } else if (read_count == USB_SPI_FULL_DUPLEX_ENABLED) { /* Full duplex mode is not supported on this device. */ - setup_transfer_response(config, - USB_SPI_UNSUPPORTED_FULL_DUPLEX); + setup_transfer_response( + config, USB_SPI_UNSUPPORTED_FULL_DUPLEX); #endif } else if (read_count > USB_SPI_MAX_READ_COUNT && - read_count != USB_SPI_FULL_DUPLEX_ENABLED) { + read_count != USB_SPI_FULL_DUPLEX_ENABLED) { setup_transfer_response(config, - USB_SPI_READ_COUNT_INVALID); + USB_SPI_READ_COUNT_INVALID); } else { - usb_spi_setup_transfer(config, write_count, read_count); - packet->header_size = - offsetof(struct usb_spi_command_v2, data); - config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); + usb_spi_setup_transfer(config, write_count, read_count); + packet->header_size = + offsetof(struct usb_spi_command_v2, data); + config->state->status_code = usb_spi_read_usb_packet( + &config->state->spi_write_ctx, packet); } /* Send responses if we encountered an error. */ if (config->state->status_code != USB_SPI_SUCCESS) { setup_transfer_response(config, - config->state->status_code); + config->state->status_code); break; } /* Start the SPI transfer when we've read all data. */ if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { + config->state->spi_write_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_START_SPI; } break; } - case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: - { + case USB_SPI_PKT_ID_CMD_TRANSFER_CONTINUE: { /* * The host has sent a continue packet for the SPI transfer * which contains additional data payload. @@ -326,26 +322,25 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, offsetof(struct usb_spi_continue_v2, data); if (config->state->status_code == USB_SPI_SUCCESS) { config->state->status_code = usb_spi_read_usb_packet( - &config->state->spi_write_ctx, packet); + &config->state->spi_write_ctx, packet); } /* Send responses if we encountered an error. */ if (config->state->status_code != USB_SPI_SUCCESS) { setup_transfer_response(config, - config->state->status_code); + config->state->status_code); break; } /* Start the SPI transfer when we've read all data. */ if (config->state->spi_write_ctx.transfer_index == - config->state->spi_write_ctx.transfer_size) { + config->state->spi_write_ctx.transfer_size) { config->state->mode = USB_SPI_MODE_START_SPI; } break; } - case USB_SPI_PKT_ID_CMD_CHIP_SELECT: - { + case USB_SPI_PKT_ID_CMD_CHIP_SELECT: { /* * The host is requesting the chip select line be * asserted or deasserted. @@ -362,8 +357,7 @@ static void usb_spi_process_rx_packet(struct usb_spi_config const *config, config->state->mode = USB_SPI_MODE_SEND_CHIP_SELECT_RESPONSE; break; } - default: - { + default: { /* An unknown USB packet was delivered. */ setup_transfer_response(config, USB_SPI_RX_UNEXPECTED_PACKET); break; @@ -396,8 +390,10 @@ void usb_spi_deferred(struct usb_spi_config const *config) * enable or disable routines and save our new state. */ if (enabled != config->state->enabled) { - if (enabled) usb_spi_board_enable(config); - else usb_spi_board_disable(config); + if (enabled) + usb_spi_board_enable(config); + else + usb_spi_board_disable(config); config->state->enabled = enabled; } @@ -439,11 +435,10 @@ void usb_spi_deferred(struct usb_spi_config const *config) read_count = SPI_READBACK_ALL; } #endif - status_code = spi_transaction(SPI_FLASH_DEVICE, - config->state->spi_write_ctx.buffer, + status_code = spi_transaction( + SPI_FLASH_DEVICE, config->state->spi_write_ctx.buffer, config->state->spi_write_ctx.transfer_size, - config->state->spi_read_ctx.buffer, - read_count); + config->state->spi_read_ctx.buffer, read_count); /* Cast the EC status code to USB SPI and start the response. */ status_code = usb_spi_map_error(status_code); @@ -451,7 +446,7 @@ void usb_spi_deferred(struct usb_spi_config const *config) } if (usb_spi_response_in_progress(config) && - usb_spi_transmitted_packet(config)) { + usb_spi_transmitted_packet(config)) { usb_spi_create_spi_transfer_response(config, transmit_packet); usb_spi_write_packet(config, transmit_packet); } @@ -491,7 +486,8 @@ static void usb_spi_read_packet(struct usb_spi_config const *config, /* Copy bytes from endpoint memory. */ packet_size = btable_ep[config->endpoint].rx_count & RX_COUNT_MASK; memcpy_from_usbram(packet->bytes, - (void *)usb_sram_addr(config->ep_rx_ram), packet_size); + (void *)usb_sram_addr(config->ep_rx_ram), + packet_size); packet->packet_size = packet_size; /* Set endpoint as valid for accepting new packet. */ STM32_TOGGLE_EP(config->endpoint, EP_RX_MASK, EP_RX_VALID, 0); @@ -505,14 +501,14 @@ static void usb_spi_read_packet(struct usb_spi_config const *config, * @param packet Source packet we will write to the endpoint data. */ static void usb_spi_write_packet(struct usb_spi_config const *config, - struct usb_spi_packet_ctx *packet) + struct usb_spi_packet_ctx *packet) { if (packet->packet_size == 0) return; /* Copy bytes to endpoint memory. */ memcpy_to_usbram((void *)usb_sram_addr(config->ep_tx_ram), - packet->bytes, packet->packet_size); + packet->bytes, packet->packet_size); btable_ep[config->endpoint].tx_count = packet->packet_size; /* Mark the packet as having no data. */ @@ -597,17 +593,17 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) usb_spi_reset_interface(config); - btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram); + btable_ep[endpoint].tx_addr = usb_sram_addr(config->ep_tx_ram); btable_ep[endpoint].tx_count = 0; - btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram); - btable_ep[endpoint].rx_count = - 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); + btable_ep[endpoint].rx_addr = usb_sram_addr(config->ep_rx_ram); + btable_ep[endpoint].rx_count = 0x8000 | + ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (3 << 12)); /* RX Valid */ + STM32_USB_EP(endpoint) = ((endpoint << 0) | /* Endpoint Addr*/ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ + (3 << 12)); /* RX Valid */ } /* @@ -617,21 +613,18 @@ void usb_spi_event(struct usb_spi_config const *config, enum usb_ep_event evt) * @param rx_buf Contains setup packet * @param tx_buf unused */ -int usb_spi_interface(struct usb_spi_config const *config, - usb_uint *rx_buf, +int usb_spi_interface(struct usb_spi_config const *config, usb_uint *rx_buf, usb_uint *tx_buf) { struct usb_setup_packet setup; usb_read_setup_packet(rx_buf, &setup); - if (setup.bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) + if (setup.bmRequestType != + (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE)) return 1; - if (setup.wValue != 0 || - setup.wIndex != config->interface || + if (setup.wValue != 0 || setup.wIndex != config->interface || setup.wLength != 0) return 1; @@ -644,7 +637,8 @@ int usb_spi_interface(struct usb_spi_config const *config, config->state->enabled_host = 0; break; - default: return 1; + default: + return 1; } /* -- cgit v1.2.1 From 73fca4c4e3d0599da9e2f52ae77acfa3af15a643 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:55 -0600 Subject: chip/npcx/lpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If47b3fd090b386b329c94afb77c0c758a58a7a13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727020 Reviewed-by: Jeremy Bettis --- chip/npcx/lpc.c | 65 ++++++++++++++++++++++++++------------------------------- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index ec99df9eb3..28126a22d2 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -33,30 +33,30 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #endif /* PM channel definitions */ -#define PMC_ACPI PM_CHAN_1 +#define PMC_ACPI PM_CHAN_1 #define PMC_HOST_CMD PM_CHAN_2 /* Microseconds to wait for eSPI VW changes to propagate */ -#define ESPI_DIRTY_WAIT_TIME_US 150 +#define ESPI_DIRTY_WAIT_TIME_US 150 -#define PORT80_MAX_BUF_SIZE 16 +#define PORT80_MAX_BUF_SIZE 16 static uint16_t port80_buf[PORT80_MAX_BUF_SIZE]; -static struct host_packet lpc_packet; -static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ -static uint8_t shm_mem_host_cmd[256] __aligned(8); -static uint8_t shm_memmap[256] __aligned(8); +static struct host_packet lpc_packet; +static struct host_cmd_handler_args host_cmd_args; +static uint8_t host_cmd_flags; /* Flags from host command */ +static uint8_t shm_mem_host_cmd[256] __aligned(8); +static uint8_t shm_memmap[256] __aligned(8); /* Params must be 32-bit aligned */ static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; -static struct ec_lpc_host_args * const lpc_host_args = - (struct ec_lpc_host_args *)shm_mem_host_cmd; +static struct ec_lpc_host_args *const lpc_host_args = + (struct ec_lpc_host_args *)shm_mem_host_cmd; /*****************************************************************************/ /* IC specific low-level driver */ @@ -260,15 +260,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args) } /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; + lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | + EC_HOST_ARGS_FLAG_TO_HOST; lpc_host_args->data_size = size; csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; + lpc_host_args->command_version + lpc_host_args->data_size; for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) csum += *out; @@ -300,13 +298,13 @@ static void lpc_send_response_packet(struct host_packet *pkt) int lpc_keyboard_has_char(void) { /* if OBF bit is '1', that mean still have a data in DBBOUT */ - return (NPCX_HIKMST&0x01) ? 1 : 0; + return (NPCX_HIKMST & 0x01) ? 1 : 0; } int lpc_keyboard_input_pending(void) { /* if IBF bit is '1', that mean still have a data in DBBIN */ - return (NPCX_HIKMST&0x02) ? 1 : 0; + return (NPCX_HIKMST & 0x02) ? 1 : 0; } /* Put a char to host buffer by HIKDO and send IRQ if specified. */ @@ -407,7 +405,7 @@ void lpc_update_host_event_status(void) /* Copy host events to mapped memory */ *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); + lpc_get_host_events(); lpc_task_enable_irq(); @@ -571,9 +569,9 @@ static void lpc_pmc_ibf_interrupt(void) /* Channel-2 for Host Command usage , so the argument data had been * put on the share memory firstly*/ if (NPCX_HIPMST(PMC_ACPI) & 0x02) - handle_acpi_write((NPCX_HIPMST(PMC_ACPI)&0x08) ? 1 : 0); + handle_acpi_write((NPCX_HIPMST(PMC_ACPI) & 0x08) ? 1 : 0); else if (NPCX_HIPMST(PMC_HOST_CMD) & 0x02) - handle_host_write((NPCX_HIPMST(PMC_HOST_CMD)&0x08) ? 1 : 0); + handle_host_write((NPCX_HIPMST(PMC_HOST_CMD) & 0x08) ? 1 : 0); } DECLARE_IRQ(NPCX_IRQ_PM_CHAN_IBF, lpc_pmc_ibf_interrupt, 4); @@ -591,7 +589,7 @@ static void lpc_port80_interrupt(void) /* buffer Port80 data to the local buffer if FIFO is not empty */ while (IS_BIT_SET(NPCX_DP80STS, NPCX_DP80STS_FNE) && - (count < ARRAY_SIZE(port80_buf))) + (count < ARRAY_SIZE(port80_buf))) port80_buf[count++] = NPCX_DP80BUF; for (i = 0; i < count; i++) { @@ -690,8 +688,7 @@ void host_register_init(void) /* LDN register = 0x0F(SHM) */ sib_write_reg(SIO_OFFSET, 0x07, 0x0F); /* WIN1&2 mapping to IO */ - sib_write_reg(SIO_OFFSET, 0xF1, - sib_read_reg(SIO_OFFSET, 0xF1) | 0x30); + sib_write_reg(SIO_OFFSET, 0xF1, sib_read_reg(SIO_OFFSET, 0xF1) | 0x30); /* WIN1 as Host Command on the IO:0x0800 */ sib_write_reg(SIO_OFFSET, 0xF5, 0x08); sib_write_reg(SIO_OFFSET, 0xF4, 0x00); @@ -711,7 +708,6 @@ void host_register_init(void) sib_write_reg(SIO_OFFSET, 0x30, 0x01); CPRINTS("Host settings are done!"); - } #ifdef CONFIG_CHIPSET_RESET_HOOK @@ -735,7 +731,7 @@ void lpc_lreset_pltrst_handler(void) int pltrst_asserted; /* Clear pending bit of WUI */ - SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 7); + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 7); /* Ignore PLTRST# from SOC if it is not valid */ if (chipset_pltrst_is_valid && !chipset_pltrst_is_valid()) @@ -770,7 +766,7 @@ static void lpc_init(void) { /* Enable clock for LPC peripheral */ clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT * register) is updated by booter after VCC1 Power-Up reset according to @@ -839,8 +835,8 @@ static void lpc_init(void) /* We support LPC args and version 3 protocol */ *(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) = - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | - EC_HOST_CMD_FLAG_VERSION_3; + EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED | + EC_HOST_CMD_FLAG_VERSION_3; /* * Clear processing flag before enabling lpc's interrupts in case @@ -854,7 +850,7 @@ static void lpc_init(void) /* * Set required control value (avoid setting HOSTWAIT bit at this stage) */ - NPCX_SMC_CTL = NPCX_SMC_CTL&~0x7F; + NPCX_SMC_CTL = NPCX_SMC_CTL & ~0x7F; /* Clear status */ NPCX_SMC_STS = NPCX_SMC_STS; @@ -903,8 +899,8 @@ static void lpc_init(void) CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL); CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL); /* Set SMIB/SCIB to make sure SMI/SCI are high at init */ - NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) - | BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB); + NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) | BIT(NPCX_HIPMIC_SMIB) | + BIT(NPCX_HIPMIC_SCIB); #ifndef CONFIG_SCI_GPIO /* * Allow SMI/SCI generated from PM module. @@ -973,9 +969,8 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, + EC_VER_MASK(0)); #if DEBUG_LPC static int command_lpc(int argc, char **argv) -- cgit v1.2.1 From 848a1c43eaceb9387b7e1a65acf4ec0498328515 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 30 Jun 2022 15:04:37 -0600 Subject: ec: Don't use grep to get cross compile value Instead of extracting the host's cross compile value from HOSTCC, just get it from HOST_CROSS_COMPILE, which is where HOSTCC gets it from in the first place. This allows overriding CCACHE to something other than ccache. BRANCH=None BUG=b:214323409 TEST=make clobber ; make -j8 test-coverage TEST=make clobber ; make -j1024 CCACHE=/mnt/host/depot_tools/.cipd_bin/gomacc test-coverage Signed-off-by: Jeremy Bettis Change-Id: I390d9dd15b5bd070030ecd8396bb8e07d23c9efd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739304 Commit-Queue: Jeremy Bettis Reviewed-by: Jack Rosenthal Tested-by: Jeremy Bettis Commit-Queue: Jack Rosenthal Auto-Submit: Jeremy Bettis --- Makefile.rules | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile.rules b/Makefile.rules index 3ea1d08df7..7af36a3afe 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -368,8 +368,7 @@ run-fuzz-test-targets=$(foreach t,$(fuzz-test-list-host),run-$(t)) $(fuzz-test-targets): TEST_FLAG=TEST_FUZZ=y TEST_ASAN=$(TEST_ASAN) \ TEST_MSAN=$(TEST_MSAN) TEST_UBSAN=$(TEST_UBSAN) \ - CROSS_COMPILE=$(shell echo $(HOSTCC) | grep -v ccache | \ - sed -e 's/[^-]*$$//') + CROSS_COMPILE=$(HOST_CROSS_COMPILE) $(fuzz-test-targets): host-%: | $(FAILED_BOARDS_DIR) @touch $(FAILED_BOARDS_DIR)/test-$* +$(call quiet,host_test,BUILD ) -- cgit v1.2.1 From 73cdab923fbfa58d6280df53e7dea881905febf4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:34 -0600 Subject: chip/npcx/config_chip-npcx7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I622d5f5a801ad8aafe0d5d34ffd00f584114362d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729389 Reviewed-by: Jeremy Bettis --- chip/npcx/config_chip-npcx7.h | 123 +++++++++++++++++++++--------------------- 1 file changed, 62 insertions(+), 61 deletions(-) diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 8404f16635..3acbd35135 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -16,26 +16,27 @@ */ /* Chip ID for all variants */ -#define NPCX787G_CHIP_ID 0x1F -#define NPCX796F_A_B_CHIP_ID 0x21 -#define NPCX796F_C_CHIP_ID 0x29 -#define NPCX797F_C_CHIP_ID 0x20 -#define NPCX797W_B_CHIP_ID 0x24 -#define NPCX797W_C_CHIP_ID 0x2C +#define NPCX787G_CHIP_ID 0x1F +#define NPCX796F_A_B_CHIP_ID 0x21 +#define NPCX796F_C_CHIP_ID 0x29 +#define NPCX797F_C_CHIP_ID 0x20 +#define NPCX797W_B_CHIP_ID 0x24 +#define NPCX797W_C_CHIP_ID 0x2C /*****************************************************************************/ /* Hardware features */ /* The optional hardware features depend on chip variant */ -#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ +#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \ defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ -#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \ + */ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #endif -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ defined(CHIP_VARIANT_NPCX7M7WC) #define NPCX_UART_FIFO_SUPPORT @@ -90,68 +91,68 @@ /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) - /* 192KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) - /* program memory base address for Code RAM (0x100C0000 - 192KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* 62 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for Code RAM (0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* 62 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 #elif defined(CHIP_VARIANT_NPCX7M7WB) - /* 256KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024) - /* program memory base address for Code RAM (0x100B0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 -# define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ - /* 126 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00020000 +/* 256KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024) +/* program memory base address for Code RAM (0x100B0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 +#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ +/* 126 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00020000 #elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC) - /* - * Code RAM is normally assumed to be same as image size, but since - * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we - * need to explicitly configure it. This is the actual size of code - * RAM on-chip. - */ -# define CONFIG_CODE_RAM_SIZE (256 * 1024) - /* - * In npcx797wc and npcx797fc, the code RAM size is limited by the - * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to - * re-organize the memory to: - * 1. the overall memory (RAM) layout is re-organized against the - * datasheet: - * In datasheet: 320 KB code RAM + 64 KB data RAM - * After re-organization: 256 KB code RAM + 128 KB data RAM. - * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the - * -WB). After the boot header is added, a 256K image would be - * too large to fit in either RO or RW sections of Flash (each - * of which is half of it). Because other code assumes that - * image size is a multiple of Flash erase granularity, we - * sacrifice a whole sector. - */ -# define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000) - /* program memory base address for Code RAM (0x100B0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 -# define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ - /* 126 KB data RAM + 2 KB BT RAM size */ -# define CONFIG_DATA_RAM_SIZE 0x00020000 - - /* - * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE - * is not the actual size of code RAM. - */ -# undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE) +/* + * Code RAM is normally assumed to be same as image size, but since + * we exclude 4k from the image (see NPCX_PROGRAM_MEMORY_SIZE) we + * need to explicitly configure it. This is the actual size of code + * RAM on-chip. + */ +#define CONFIG_CODE_RAM_SIZE (256 * 1024) +/* + * In npcx797wc and npcx797fc, the code RAM size is limited by the + * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to + * re-organize the memory to: + * 1. the overall memory (RAM) layout is re-organized against the + * datasheet: + * In datasheet: 320 KB code RAM + 64 KB data RAM + * After re-organization: 256 KB code RAM + 128 KB data RAM. + * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the + * -WB). After the boot header is added, a 256K image would be + * too large to fit in either RO or RW sections of Flash (each + * of which is half of it). Because other code assumes that + * image size is a multiple of Flash erase granularity, we + * sacrifice a whole sector. + */ +#define NPCX_PROGRAM_MEMORY_SIZE (CONFIG_CODE_RAM_SIZE - 0x1000) +/* program memory base address for Code RAM (0x100B0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 +#define CONFIG_RAM_BASE 0x200B0000 /* memory address of data ram */ +/* 126 KB data RAM + 2 KB BT RAM size */ +#define CONFIG_DATA_RAM_SIZE 0x00020000 + +/* + * Override default NPCX_RAM_SIZE because NPCX_PROGRAM_MEMORY_SIZE + * is not the actual size of code RAM. + */ +#undef NPCX_RAM_SIZE +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + CONFIG_CODE_RAM_SIZE) #else -# error "Unsupported chip variant" +#error "Unsupported chip variant" #endif -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) /* no low power ram in npcx7 series */ #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */ -- cgit v1.2.1 From 17abcce4e714155d343224b967bd3aa6deafda5b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:02 -0600 Subject: include/btle_hci_int.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icde1fc893d08c8e32a693303d910c5075b1d80c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730216 Reviewed-by: Jeremy Bettis --- include/btle_hci_int.h | 1676 +++++++++++++++++++++++++----------------------- 1 file changed, 864 insertions(+), 812 deletions(-) diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h index 83fffee69f..286afb3b37 100644 --- a/include/btle_hci_int.h +++ b/include/btle_hci_int.h @@ -8,377 +8,463 @@ * original author. */ - #ifndef _HCI_INT_H_ #define _HCI_INT_H_ #include "util.h" -#define HCI_DEV_NAME_LEN 248 - -#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */ -#define HCI_INQUIRY_LENGTH_MAX 48 /* units */ - -#define HCI_LAP_Unlimited_Inquiry 0x9E8B33 -#define HCI_LAP_Limited_Inquiry 0x9E8B00 - -#define HCI_CLOCK_OFST_VALID 0x8000 - -#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */ -#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */ -#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */ -#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */ -#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */ -#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */ -#define HCI_PKT_TYP_DEFAULT 0xCC18 - -#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */ -#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */ -#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */ -#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */ - -#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000 -#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001 -#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002 -#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004 -#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008 - -#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */ -#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */ -#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */ -#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class) */ -#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */ -#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS 0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 - yes w/ roleswitch */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are compared to wanted_class), auto_accept flag same as above */ -#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR 0x02 /* uint8_t mac[6], auto_accept flag same as above */ - -#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */ -#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */ - -#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01 -#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02 -#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04 - -#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01 -#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02 - -#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */ -#define HCI_INQ_MODE_RSSI 1 /* with RSSI @ BT 1.2+ */ -#define HCI_INQ_MODE_EIR 2 /* with EIR @ BT 2.1+ */ - -#define HCI_SSP_KEY_ENTRY_STARTED 0 -#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1 -#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2 -#define HCI_SSP_KEY_ENTRY_CLEARED 3 -#define HCI_SSP_KEY_ENTRY_COMPLETED 4 - -#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */ -#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */ -#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */ -#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */ - -#define HCI_PERIOD_TYPE_DOWNLINK 0x00 -#define HCI_PERIOD_TYPE_UPLINK 0x01 -#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02 -#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03 - -#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00 -#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01 -#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02 -#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03 -#define HCI_MWS_INTERVAL_TYPE_FRAME 0x04 /* type defined by Set External Frame Configuration command */ - -#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */ -#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */ -#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */ -#define HCI_CONNLESS_FRAG_TYPE_COMPLETE 0x03 /* complete fragment - no fragmentation */ - -#define HCI_CUR_MODE_ACTIVE 0x00 -#define HCI_CUR_MODE_HOLD 0x01 -#define HCI_CUR_MODE_SNIFF 0x02 -#define HCI_CUR_MODE_PARK 0x03 - -#define HCI_SCO_LINK_TYPE_SCO 0x00 -#define HCI_SCO_LINK_TYPE_ESCO 0x02 - -#define HCI_SCO_AIR_MODE_MULAW 0x00 -#define HCI_SCO_AIR_MODE_ALAW 0x01 -#define HCI_SCO_AIR_MODE_CVSD 0x02 -#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03 - -#define HCI_MCA_500_PPM 0x00 -#define HCI_MCA_250_PPM 0x01 -#define HCI_MCA_150_PPM 0x02 -#define HCI_MCA_100_PPM 0x03 -#define HCI_MCA_75_PPM 0x04 -#define HCI_MCA_50_PPM 0x05 -#define HCI_MCA_30_PPM 0x06 -#define HCI_MCA_20_PPM 0x07 - -#define HCI_EDR_LINK_KEY_COMBO 0x00 -#define HCI_EDR_LINK_KEY_LOCAL 0x01 -#define HCI_EDR_LINK_KEY_REMOTE 0x02 -#define HCI_EDR_LINK_KEY_DEBUG 0x03 -#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04 -#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05 -#define HCI_EDR_LINK_KEY_CHANGED 0x06 - -#define HCI_VERSION_1_0_B 0 /* BT 1.0b */ -#define HCI_VERSION_1_1 1 /* BT 1.1 */ -#define HCI_VERSION_1_2 2 /* BT 1.2 */ -#define HCI_VERSION_2_0 4 /* BT 2.0 */ -#define HCI_VERSION_2_1 3 /* BT 2.1 */ -#define HCI_VERSION_3_0 4 /* BT 3.0 */ -#define HCI_VERSION_4_0 6 /* BT 4.0 */ -#define HCI_VERSION_4_1 7 /* BT 4.1 */ - -#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */ -#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN 0x0000000000000100ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN 0x0000000000000200ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN 0x0000000000000400ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN 0x0000000000000800ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN 0x0000000000001000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN 0x0000000000002000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN 0x0000000000004000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN 0x0000000000008000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_INITIATING 0x0000000000010000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING 0x0000000000020000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER 0x0000000000080000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING 0x0000000000400000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING 0x0000000000800000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000020000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000040000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV 0x0000000080000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING 0x0000000100000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING 0x0000000200000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING 0x0000000400000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER 0x0000000800000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER 0x0000002000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE 0x0000004000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE 0x0000010000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */ - -#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE 0x0000000000000400ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */ -#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */ -#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN 0x0000000010000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS 0x0000000040000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_SCO_LINK 0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */ -#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE 0x0000001000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */ -#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER 0x0000004000000000ULL /* BT 4.0+ */ -#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER 0x0000100000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE 0x0001000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING 0x0020000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG 0x0040000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT 0x0100000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL 0x0200000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */ -#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER 0x0002000000000000ULL /* BT 4.0+ */ - -#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT 0x0000000000000001ULL /* BT 2.1+ */ -#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT 0x0000000000000008ULL /* BT 4.1+ */ - -#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER 0x0000000000000001ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE 0x0000000000000002ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN 0x0000000000000004ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN 0x0000000000000008ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT 0x0000000000000010ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN 0x0000000000000020ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT 0x0000000000000040ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER 0x0000000000000100ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */ -#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */ - -#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */ -#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */ -#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */ -#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */ -#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE 0x0000000000000040ULL /* BT 1.1+ */ -#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */ -#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE 0x0000000000000100ULL /* BT 1.1+ */ -#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE 0x0000000000000400ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE 0x0000000000000800ULL /* BT 1.1+ */ -#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */ -#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */ -#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */ -#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */ -#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */ -#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */ -#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */ -#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */ -#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */ -#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */ -#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */ -#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x0000000008000000ULL /* BT 1.1+ */ -#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */ -#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */ -#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE 0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */ -#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE 0x0000000080000000ULL /* BT 1.1+ */ -#define HCI_EVENT_ALL_BT_1_1 0x00000000FFFFFFFFULL /* also the default for BT 1.1 */ -#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */ -#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */ -#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE 0x0000000400000000ULL /* BT 1.2+ */ -#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */ -#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */ -#define HCI_EVENT_ALL_BT_1_2 0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */ -#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE 0x0000800000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY 0x0002000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_CONFIRMATION_REQUEST 0x0004000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED 0x0080000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_PASSKEY_NOTIFICATION 0x0400000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES 0x1000000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL -#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL -#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */ -#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL -#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL - -#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK 0x0000000000000004ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING 0x0000000000000008ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY 0x0000000000000010ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE 0x0000000000000040ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE 0x0000000000000080ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS 0x0000000000000100ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE 0x0000000000001000ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL -#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL -#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE 0x0000000000004000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED 0x0000000000020000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT 0x0000000000040000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE 0x0000000000080000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT 0x0000000000100000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE 0x0000000000200000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION 0x0000000000400000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED 0x0000000000800000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL - -#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE 0x0000000000000008ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */ -#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST 0x0000000000000020ULL /* BT 4.1+ */ - -#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */ -#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST 0x0000000000000002ULL /* BT 4.1+ */ -#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION 0x0000000000000004ULL /* BT 4.1+ */ -#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE 0x0000000000000008ULL /* BT 4.1+ */ -#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */ - - - - - -#define HCI_OGF_Link_Control 1 - +#define HCI_DEV_NAME_LEN 248 + +#define HCI_INQUIRY_LENGTH_UNIT 1280 /* msec */ +#define HCI_INQUIRY_LENGTH_MAX 48 /* units */ + +#define HCI_LAP_Unlimited_Inquiry 0x9E8B33 +#define HCI_LAP_Limited_Inquiry 0x9E8B00 + +#define HCI_CLOCK_OFST_VALID 0x8000 + +#define HCI_PKT_TYP_NO_2_DH1 0x0002 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH1 0x0004 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM1 0x0008 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH1 0x0010 /* BT 1.1+ */ +#define HCI_PKT_TYP_NO_2_DH3 0x0100 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH3 0x0200 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM3 0x0400 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH3 0x0800 /* BT 1.1+ */ +#define HCI_PKT_TYP_NO_2_DH5 0x1000 /* BT 2.1+ */ +#define HCI_PKT_TYP_NO_3_DH5 0x1000 /* BT 2.1+ */ +#define HCI_PKT_TYP_DM5 0x4000 /* BT 1.1+ */ +#define HCI_PKT_TYP_DH5 0x8000 /* BT 1.1+ */ +#define HCI_PKT_TYP_DEFAULT 0xCC18 + +#define HCI_PKT_TYP_SCO_HV1 0x0001 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_HV2 0x0002 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_HV3 0x0004 /* BT 1.1+ */ +#define HCI_PKT_TYP_SCO_EV3 0x0008 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_EV4 0x0010 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_EV5 0x0020 /* BT 1.2+ */ +#define HCI_PKT_TYP_SCO_NO_2_EV3 0x0040 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_3_EV3 0x0080 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_2_EV5 0x0100 /* BT 2.1+ */ +#define HCI_PKT_TYP_SCO_NO_3_EV5 0x0200 /* BT 2.1+ */ + +#define HCI_LINK_POLICY_DISABLE_ALL_LM_MODES 0x0000 +#define HCI_LINK_POLICY_ENABLE_ROLESWITCH 0x0001 +#define HCI_LINK_POLICY_ENABLE_HOLD_MODE 0x0002 +#define HCI_LINK_POLICY_ENABLE_SNIFF_MODE 0x0004 +#define HCI_LINK_POLICY_ENABLE_PARK_MODE 0x0008 + +#define HCI_FILTER_TYPE_CLEAR_ALL 0x00 /* no subtypes, no data */ +#define HCI_FILTER_INQUIRY_RESULT 0x01 /* below subtypes */ +#define HCI_FILTER_COND_TYPE_RETURN_ALL_DEVS 0x00 /* no data */ +#define HCI_FILTER_COND_TYPE_SPECIFIC_DEV_CLS \ + 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \ + compared to wanted_class) */ +#define HCI_FILTER_COND_TYPE_SPECIFIC_ADDR 0x02 /* uint8_t mac[6] */ +#define HCI_FILTER_CONNECTION_SETUP 0x02 /* below subtypes */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_ALL_DEVS \ + 0x00 /* uint8_t auto_accept_type: 1 - no, 2 - yes w/ no roleswitch, 3 \ + - yes w/ roleswitch */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_DEV_CLS \ + 0x01 /* uint24_t wanted_class, uint24_t wanted_mask (only set bits are \ + compared to wanted_class), auto_accept flag same as above */ +#define HCI_FILTER_COND_TYPE_ALLOW_CONNS_FROM_SPECIFIC_ADDR \ + 0x02 /* uint8_t mac[6], auto_accept flag same as above */ + +#define HCI_SCAN_ENABLE_INQUIRY 0x01 /* discoverable */ +#define HCI_SCAN_ENABLE_PAGE 0x02 /* connectable */ + +#define HCI_HOLD_MODE_SUSPEND_PAGE_SCAN 0x01 +#define HCI_HOLD_MODE_SUSPEND_INQUIRY_SCAN 0x02 +#define HCI_HOLD_MODE_SUSPEND_PERIODIC_INQUIRIES 0x04 + +#define HCI_TO_HOST_FLOW_CTRL_ACL 0x01 +#define HCI_TO_HOST_FLOW_CTRL_SCO 0x02 + +#define HCI_INQ_MODE_STD 0 /* normal mode @ BT 1.1+ */ +#define HCI_INQ_MODE_RSSI 1 /* with RSSI @ BT 1.2+ */ +#define HCI_INQ_MODE_EIR 2 /* with EIR @ BT 2.1+ */ + +#define HCI_SSP_KEY_ENTRY_STARTED 0 +#define HCI_SSP_KEY_ENTRY_DIGIT_ENTERED 1 +#define HCI_SSP_KEY_ENTRY_DIGIT_ERASED 2 +#define HCI_SSP_KEY_ENTRY_CLEARED 3 +#define HCI_SSP_KEY_ENTRY_COMPLETED 4 + +#define HCI_LOCATION_DOMAIN_OPTION_NONE 0x20 /* ' ' */ +#define HCI_LOCATION_DOMAIN_OPTION_OUTDOORS_ONLY 0x4F /* 'O' */ +#define HCI_LOCATION_DOMAIN_OPTION_INDOORS_ONLY 0x49 /* 'I' */ +#define HCI_LOCATION_DOMAIN_OPTION_NON_COUNTRY_ENTITY 0x58 /* 'X' */ + +#define HCI_PERIOD_TYPE_DOWNLINK 0x00 +#define HCI_PERIOD_TYPE_UPLINK 0x01 +#define HCI_PERIOD_TYPE_BIDIRECTIONAL 0x02 +#define HCI_PERIOD_TYPE_GUARD_PERIOD 0x03 + +#define HCI_MWS_INTERVAL_TYPE_NO_RX_NO_TX 0x00 +#define HCI_MWS_INTERVAL_TYPE_TX_ALLOWED 0x01 +#define HCI_MWS_INTERVAL_TYPE_RX_ALLOWED 0x02 +#define HCI_MWS_INTERVAL_TYPE_TX_RX_ALLOWED 0x03 +#define HCI_MWS_INTERVAL_TYPE_FRAME \ + 0x04 /* type defined by Set External Frame Configuration command */ + +#define HCI_CONNLESS_FRAG_TYPE_CONT 0x00 /* continuation fragment */ +#define HCI_CONNLESS_FRAG_TYPE_START 0x01 /* first fragment */ +#define HCI_CONNLESS_FRAG_TYPE_END 0x02 /* last fragment */ +#define HCI_CONNLESS_FRAG_TYPE_COMPLETE \ + 0x03 /* complete fragment - no fragmentation */ + +#define HCI_CUR_MODE_ACTIVE 0x00 +#define HCI_CUR_MODE_HOLD 0x01 +#define HCI_CUR_MODE_SNIFF 0x02 +#define HCI_CUR_MODE_PARK 0x03 + +#define HCI_SCO_LINK_TYPE_SCO 0x00 +#define HCI_SCO_LINK_TYPE_ESCO 0x02 + +#define HCI_SCO_AIR_MODE_MULAW 0x00 +#define HCI_SCO_AIR_MODE_ALAW 0x01 +#define HCI_SCO_AIR_MODE_CVSD 0x02 +#define HCI_SCO_AIR_MODE_TRANSPARENT 0x03 + +#define HCI_MCA_500_PPM 0x00 +#define HCI_MCA_250_PPM 0x01 +#define HCI_MCA_150_PPM 0x02 +#define HCI_MCA_100_PPM 0x03 +#define HCI_MCA_75_PPM 0x04 +#define HCI_MCA_50_PPM 0x05 +#define HCI_MCA_30_PPM 0x06 +#define HCI_MCA_20_PPM 0x07 + +#define HCI_EDR_LINK_KEY_COMBO 0x00 +#define HCI_EDR_LINK_KEY_LOCAL 0x01 +#define HCI_EDR_LINK_KEY_REMOTE 0x02 +#define HCI_EDR_LINK_KEY_DEBUG 0x03 +#define HCI_EDR_LINK_KEY_UNAUTH_COMBO 0x04 +#define HCI_EDR_LINK_KEY_AUTH_COMBO 0x05 +#define HCI_EDR_LINK_KEY_CHANGED 0x06 + +#define HCI_VERSION_1_0_B 0 /* BT 1.0b */ +#define HCI_VERSION_1_1 1 /* BT 1.1 */ +#define HCI_VERSION_1_2 2 /* BT 1.2 */ +#define HCI_VERSION_2_0 4 /* BT 2.0 */ +#define HCI_VERSION_2_1 3 /* BT 2.1 */ +#define HCI_VERSION_3_0 4 /* BT 3.0 */ +#define HCI_VERSION_4_0 6 /* BT 4.0 */ +#define HCI_VERSION_4_1 7 /* BT 4.1 */ + +#define HCI_LE_STATE_NONCON_ADV 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV 0x0000000000000008ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN 0x0000000000000010ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN 0x0000000000000020ULL /* BT 4.0+ */ +#define HCI_LE_STATE_INITIATE 0x0000000000000040ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SLAVE 0x0000000000000080ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_PASSIVE_SCAN \ + 0x0000000000000100ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_PASSIVE_SCAN \ + 0x0000000000000200ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_PASSIVE_SCAN \ + 0x0000000000000400ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_PASSIVE_SCAN \ + 0x0000000000000800ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_ACTIVE_SCAN \ + 0x0000000000001000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_ACTIVE_SCAN \ + 0x0000000000002000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_ACTIVE_SCAN \ + 0x0000000000004000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN \ + 0x0000000000008000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_INITIATING 0x0000000000010000ULL /* BT 4.0+ \ + */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING \ + 0x0000000000020000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER 0x0000000000080000ULL /* BT 4.0+ \ + */ +#define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING \ + 0x0000000000400000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_INITIATING \ + 0x0000000000800000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_MASTER 0x0000000001000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_MASTER 0x0000000002000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_SLAVE 0x0000000004000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_SLAVE 0x0000000008000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_INTIATING_w_MASTER 0x0000000010000000ULL /* BT 4.0+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000020000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_PASSIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000040000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_ACTIVE_SCAN_w_LOW_DUTY_CYCLE_DIRECT_ADV \ + 0x0000000080000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING \ + 0x0000000100000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING 0x0000000200000000ULL /* BT 4.1+ \ + */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING \ + 0x0000000400000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER \ + 0x0000000800000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER \ + 0x0000002000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE 0x0000004000000000ULL /* BT 4.1+ \ + */ +#define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE \ + 0x0000010000000000ULL /* BT 4.1+ */ +#define HCI_LE_STATE_INITIATING_w_SLAVE 0x0000020000000000ULL /* BT 4.1+ */ + +#define HCI_LMP_FTR_3_SLOT_PACKETS 0x0000000000000001ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_5_SLOT_PACKETS 0x0000000000000002ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_ENCRYPTION 0x0000000000000004ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SLOT_OFFSET 0x0000000000000008ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_TIMING_ACCURACY 0x0000000000000010ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SWITCH 0x0000000000000020ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HOLD_MODE 0x0000000000000040ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SNIFF_MODE 0x0000000000000080ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_PARK_MODE 0x0000000000000100ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_RSSI 0x0000000000000200ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_CHANNEL_QUALITY_DRIVEN_DATA_RATE \ + 0x0000000000000400ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_SCO_LINKS 0x0000000000000800ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HV2_PACKETS 0x0000000000001000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_HV3_PACKETS 0x0000000000002000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_MU_LAW 0x0000000000004000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_A_LAW 0x0000000000008000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_CVSD 0x0000000000010000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_PAGING_SCHEME 0x0000000000020000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_POWER_CONTROL 0x0000000000040000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_TRANSPARENT_SCO_DATA 0x0000000000080000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B0 0x0000000000100000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B1 0x0000000000200000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_FLOW_CONTROL_LAG_B2 0x0000000000400000ULL /* BT 1.1+ */ +#define HCI_LMP_FTR_BROADCAST_ENCRYPTION 0x0000000000800000ULL /* BT 1.2+ */ +#define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN 0x0000000010000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS \ + 0x0000000040000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_SCO_LINK \ + 0x0000000080000000ULL /* BT 2.1+ */ /* EV3 packets */ +#define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE 0x0000001000000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */ +#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER 0x0000004000000000ULL /* BT 4.0+ \ + */ +#define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_PAUSE_ENCRYPTION 0x0000040000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CAPABLE_MASTER 0x0000080000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_AFH_CLASSIFICATION_MASTER \ + 0x0000100000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ESCO_2MBPS 0x0000200000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ESCO_3MBPS 0x0000400000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_3_SLOT_ESCO 0x0000800000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_INQUIRY_RESPONSE \ + 0x0001000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING 0x0020000000000000ULL /* BT 2.1+ \ + */ +#define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG \ + 0x0040000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT \ + 0x0100000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_INQUIRY_RESPONSE_TX_POWER_LEVEL \ + 0x0200000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_EXTENDED_FEATURES 0x8000000000000000ULL /* BT 2.1+ */ +#define HCI_LMP_FTR_ENHANCED_POWER_CONTROL 0x0400000000000000ULL /* BT 3.0+ */ +#define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER \ + 0x0002000000000000ULL /* BT 4.0+ */ + +#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT 0x0000000000000001ULL /* BT 2.1+ \ + */ +#define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT \ + 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LMP_EXT_FTR_P1_SECURE_CONNECTIONS_HOST_SUPPORT \ + 0x0000000000000008ULL /* BT 4.1+ */ + +#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_MASTER \ + 0x0000000000000001ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_CONNLESS_SLAVE_BROADCAST_SLAVE \ + 0x0000000000000002ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_TRAIN \ + 0x0000000000000004ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SYNCHRONIZATION_SCAN \ + 0x0000000000000008ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_INQUIRY_RESPONSE_NOTIFICATION_EVT \ + 0x0000000000000010ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_GENERALIZED_INTERLACED_SCAN \ + 0x0000000000000020ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_COARSE_CLOCK_ADJUSTMENT \ + 0x0000000000000040ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_SECURE_CONNECTIONS_CAPABLE_CONTROLLER \ + 0x0000000000000100ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_PING 0x0000000000000200ULL /* BT 4.1+ */ +#define HCI_LMP_EXT_FTR_P2_TRAIN_NUDGING 0x0000000000000800ULL /* BT 4.1+ */ + +#define HCI_EVENT_INQUIRY_COMPLETE 0x0000000000000001ULL /* BT 1.1+ */ +#define HCI_EVENT_INQUIRY_RESULT 0x0000000000000002ULL /* BT 1.1+ */ +#define HCI_EVENT_CONN_COMPLETE 0x0000000000000004ULL /* BT 1.1+ */ +#define HCI_EVENT_CONN_REQUEST 0x0000000000000008ULL /* BT 1.1+ */ +#define HCI_EVENT_DISCONNECTION_COMPLETE 0x0000000000000010ULL /* BT 1.1+ */ +#define HCI_EVENT_AUTH_COMPLETE 0x0000000000000020ULL /* BT 1.1+ */ +#define HCI_EVENT_REMOTE_NAME_REQUEST_COMPLETE \ + 0x0000000000000040ULL /* BT 1.1+ */ +#define HCI_EVENT_ENCR_CHANGE 0x0000000000000080ULL /* BT 1.1+ */ +#define HCI_EVENT_CHANGE_CONN_LINK_KEY_COMPLETE \ + 0x0000000000000100ULL /* BT 1.1+ */ +#define HCI_EVENT_MASTER_LINK_KEY_COMPLETE 0x0000000000000200ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE \ + 0x0000000000000400ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_REMOTE_VERSION_INFO_COMPLETE \ + 0x0000000000000800ULL /* BT 1.1+ */ +#define HCI_EVENT_QOS_SETUP_COMPLETE 0x0000000000001000ULL /* BT 1.1+ */ +#define HCI_EVENT_HARDWARE_ERROR 0x0000000000008000ULL /* BT 1.1+ */ +#define HCI_EVENT_FLUSH_OCCURRED 0x0000000000010000ULL /* BT 1.1+ */ +#define HCI_EVENT_ROLE_CHANGE 0x0000000000020000ULL /* BT 1.1+ */ +#define HCI_EVENT_MODE_CHANGE 0x0000000000080000ULL /* BT 1.1+ */ +#define HCI_EVENT_RETURN_LINK_KEYS 0x0000000000100000ULL /* BT 1.1+ */ +#define HCI_EVENT_PIN_CODE_REQUEST 0x0000000000200000ULL /* BT 1.1+ */ +#define HCI_EVENT_LINK_KEY_REQUEST 0x0000000000400000ULL /* BT 1.1+ */ +#define HCI_EVENT_LINK_KEY_NOTIFICATION 0x0000000000800000ULL /* BT 1.1+ */ +#define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */ +#define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */ +#define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */ +#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x0000000008000000ULL /* BT 1.1+ \ + */ +#define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */ +#define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */ +#define HCI_EVENT_PAGE_SCAN_MODE_CHANGE \ + 0x0000000040000000ULL /* BT 1.1+, obsolete @ BT1.2+ */ +#define HCI_EVENT_PAGE_SCAN_REPETITION_MODE_CHANGE \ + 0x0000000080000000ULL /* BT 1.1+ */ +#define HCI_EVENT_ALL_BT_1_1 \ + 0x00000000FFFFFFFFULL /* also the default for BT 1.1 */ +#define HCI_EVENT_FLOW_SPEC_COMPLETE 0x0000000100000000ULL /* BT 1.2+ */ +#define HCI_EVENT_INQUIRY_RESULT_WITH_RSSI 0x0000000200000000ULL /* BT 1.2+ */ +#define HCI_EVENT_READ_REMOTE_EXTENDED_FEATURES_COMPLETE \ + 0x0000000400000000ULL /* BT 1.2+ */ +#define HCI_EVENT_SYNC_CONN_COMPLETE 0x0000080000000000ULL /* BT 1.2+ */ +#define HCI_EVENT_SYNC_CONN_CHANGED 0x0000100000000000ULL /* BT 1.2+ */ +#define HCI_EVENT_ALL_BT_1_2 \ + 0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */ +#define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE 0x0000800000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY \ + 0x0002000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_USER_CONFIRMATION_REQUEST 0x0004000000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED \ + 0x0080000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_USER_PASSKEY_NOTIFICATION 0x0400000000000000ULL /* BT 2.1+ \ + */ +#define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES \ + 0x1000000000000000ULL /* BT 2.1+ */ +#define HCI_EVENT_ALL_BT_2_1 0x1DBFFFFFFFFFFFFFULL +#define HCI_EVENT_ALL_BT_3_0 0x1DBFFFFFFFFFFFFFULL +#define HCI_EVENT_LE_META 0x2000000000000000ULL /* BT 4.0+ */ +#define HCI_EVENT_ALL_BT_4_0 0x3DBFFFFFFFFFFFFFULL +#define HCI_EVENT_ALL_BT_4_1 0x3DBFFFFFFFFFFFFFULL + +#define HCI_EVENT_P2_PHYS_LINK_COMPLETE 0x0000000000000001ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_CHANNEL_SELECTED 0x0000000000000002ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_DISCONNECTION_PHYSICAL_LINK \ + 0x0000000000000004ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING \ + 0x0000000000000008ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY 0x0000000000000010ULL /* BT 3.0+ \ + */ +#define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE \ + 0x0000000000000040ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_FLOW_SPEC_MODIFY_COMPLETE \ + 0x0000000000000080ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_NUMBER_OF_COMPLETED_DATA_BLOCKS \ + 0x0000000000000100ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_START_TEST 0x0000000000000200ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_TEST_END 0x0000000000000400ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_RECEIVER_REPORT 0x0000000000000800ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_SHORT_RANGE_MODE_CHANGE_COMPLETE \ + 0x0000000000001000ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */ +#define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL +#define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL +#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE 0x0000000000004000ULL /* BT 4.1+ \ + */ +#define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED \ + 0x0000000000020000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT \ + 0x0000000000040000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE 0x0000000000080000ULL /* BT 4.1+ \ + */ +#define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT \ + 0x0000000000100000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE \ + 0x0000000000200000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_INQUIRY_RESPONSE_NOTIFICATION \ + 0x0000000000400000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_AUTHENTICATED_PAYLOAD_TIMEOUT_EXPIRED \ + 0x0000000000800000ULL /* BT 4.1+ */ +#define HCI_EVENT_P2_ALL_BT_4_1 0x0000000000FFFFFFULL + +#define HCI_LE_EVENT_CONN_COMPLETE 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_ADV_REPORT 0x0000000000000002ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_CONN_UPDATE_COMPLETE 0x0000000000000004ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_READ_REMOTE_USED_FEATURES_CMPLETE \ + 0x0000000000000008ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_LTK_REQUEST 0x0000000000000010ULL /* BT 4.0+ */ +#define HCI_LE_EVENT_REMOTE_CONNECTION_PARAMETER_REQUEST \ + 0x0000000000000020ULL /* BT 4.1+ */ + +#define HCI_LE_FTR_ENCRYPTION 0x0000000000000001ULL /* BT 4.0+ */ +#define HCI_LE_FTR_CONNECTION_PARAMETERS_REQUEST \ + 0x0000000000000002ULL /* BT 4.1+ */ +#define HCI_LE_FTR_EXTENDED_REJECT_INDICATION \ + 0x0000000000000004ULL /* BT 4.1+ */ +#define HCI_LE_FTR_SLAVE_INITIATED_FEATURES_EXCHANGE \ + 0x0000000000000008ULL /* BT 4.1+ */ +#define HCI_LE_FTR_LE_PING 0x0000000000000010ULL /* BT 4.1+ */ + +#define HCI_OGF_Link_Control 1 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Inquiry 0x0001 /* status */ +#define HCI_CMD_Inquiry 0x0001 /* status */ struct hciInquiry { uint8_t lap[3]; uint8_t inqLen; uint8_t numResp; } __packed; -#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */ +#define HCI_CMD_Inquiry_Cancel 0x0002 /* complete */ struct hciCmplInquiryCancel { uint8_t status; } __packed; -#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */ +#define HCI_CMD_Periodic_Inquiry_Mode 0x0003 /* complete */ struct hciPeriodicInquiryMode { uint16_t maxPeriodLen; uint16_t minPeriodLen; @@ -390,10 +476,9 @@ struct hciCmplPeriodicInquiryMode { uint8_t status; } __packed; +#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */ -#define HCI_CMD_Exit_Periodic_Inquiry_Mode 0x0004 /* complete */ - -#define HCI_CMD_Create_Connection 0x0005 /* status */ +#define HCI_CMD_Create_Connection 0x0005 /* status */ struct hciCreateConnection { uint8_t mac[6]; uint16_t allowedPackets; /* HCI_PKT_TYP_* */ @@ -402,19 +487,20 @@ struct hciCreateConnection { uint8_t allowRoleSwitch; } __packed; -#define HCI_CMD_Disconnect 0x0006 /* status */ +#define HCI_CMD_Disconnect 0x0006 /* status */ struct hciDisconnect { uint16_t conn; uint8_t reason; } __packed; -#define HCI_CMD_Add_SCO_Connection 0x0007 /* status */ /* deprecated in BT 1.2+ */ +#define HCI_CMD_Add_SCO_Connection \ + 0x0007 /* status */ /* deprecated in BT 1.2+ */ struct hciAddScoConnection { uint16_t conn; uint16_t packetTypes; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */ +#define HCI_CMD_Create_Connection_Cancel 0x0008 /* complete */ struct hciCreateConnectionCancel { uint8_t mac[6]; } __packed; @@ -423,19 +509,19 @@ struct hciCmplCreateConnectionCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */ +#define HCI_CMD_Accept_Connection_Request 0x0009 /* status */ struct hciAcceptConnection { uint8_t mac[6]; uint8_t remainSlave; } __packed; -#define HCI_CMD_Reject_Connection_Request 0x000A /* status */ +#define HCI_CMD_Reject_Connection_Request 0x000A /* status */ struct hciRejectConnection { uint8_t mac[6]; uint8_t reason; } __packed; -#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */ +#define HCI_CMD_Link_Key_Request_Reply 0x000B /* complete */ struct hciLinkKeyRequestReply { uint8_t mac[6]; uint8_t key[16]; @@ -445,7 +531,7 @@ struct hciCmplLinkKeyRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */ +#define HCI_CMD_Link_Key_Request_Negative_Reply 0x000C /* complete */ struct hciLinkKeyRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -454,7 +540,7 @@ struct hciCmplLinkKeyRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */ +#define HCI_CMD_PIN_Code_Request_Reply 0x000D /* complete */ struct hciPinCodeRequestReply { uint8_t mac[6]; uint8_t pinCodeLen; @@ -465,7 +551,7 @@ struct hciCmplPinCodeRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */ +#define HCI_CMD_PIN_Code_Request_Negative_Reply 0x000E /* complete */ struct hciPinCodeRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -474,34 +560,34 @@ struct hciCmplPinCodeRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */ +#define HCI_CMD_Change_Connection_Packet_Type 0x000F /* status */ struct hciChangeConnectionPacketType { uint16_t conn; uint16_t allowedPackets; /* HCI_PKT_TYP_* */ } __packed; -#define HCI_CMD_Authentication_Requested 0x0011 /* status */ +#define HCI_CMD_Authentication_Requested 0x0011 /* status */ struct hciAuthRequested { uint16_t conn; } __packed; -#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */ +#define HCI_CMD_Set_Connection_Encryption 0x0013 /* status */ struct hciSetConnectionEncryption { uint16_t conn; uint8_t encrOn; } __packed; -#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */ +#define HCI_CMD_Change_Connection_Link_Key 0x0015 /* status */ struct hciChangeConnLinkKey { uint16_t conn; } __packed; -#define HCI_CMD_Master_Link_Key 0x0017 /* status */ +#define HCI_CMD_Master_Link_Key 0x0017 /* status */ struct hciMasterLinkKey { uint8_t useTempKey; } __packed; -#define HCI_CMD_Remote_Name_Request 0x0019 /* status */ +#define HCI_CMD_Remote_Name_Request 0x0019 /* status */ struct hciRemoteNameRequest { uint8_t mac[6]; uint8_t PSRM; @@ -509,7 +595,7 @@ struct hciRemoteNameRequest { uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */ } __packed; -#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */ +#define HCI_CMD_Remote_Name_Request_Cancel 0x001A /* complete */ struct hciRemoteNameRequestCancel { uint8_t mac[6]; } __packed; @@ -518,31 +604,30 @@ struct hciCmplRemoteNameRequestCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */ +#define HCI_CMD_Read_Remote_Supported_Features 0x001B /* status */ struct hciReadRemoteSupportedFeatures { uint16_t conn; } __packed; -#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */ +#define HCI_CMD_Read_Remote_Version_Information 0x001D /* status */ struct hciReadRemoteVersionInfo { uint16_t conn; } __packed; -#define HCI_CMD_Read_Clock_Offset 0x001F /* status */ +#define HCI_CMD_Read_Clock_Offset 0x001F /* status */ struct hciReadClockOffset { uint16_t conn; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */ +#define HCI_CMD_Read_Remote_Extended_Features 0x001C /* status */ struct hciReadRemoteExtendedFeatures { uint16_t conn; uint8_t page; /* BT1.2 max: 0 */ } __packed; -#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */ +#define HCI_CMD_Read_Lmp_Handle 0x0020 /* complete */ struct hciReadLmpHandle { uint16_t handle; } __packed; @@ -553,7 +638,7 @@ struct hciCmplReadLmpHandle { uint32_t reserved; } __packed; -#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */ +#define HCI_CMD_Setup_Synchronous_Connection 0x0028 /* status */ struct hciSetupSyncConn { uint16_t conn; uint32_t txBandwidth; @@ -564,7 +649,7 @@ struct hciSetupSyncConn { uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */ +#define HCI_CMD_Accept_Synchronous_Connection_Request 0x0029 /* status */ struct hciAcceptSyncConn { uint8_t mac[6]; uint32_t txBandwidth; @@ -575,16 +660,15 @@ struct hciAcceptSyncConn { uint16_t allowedPacketsSco; /* HCI_PKT_TYP_SCO_* */ } __packed; -#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */ +#define HCI_CMD_Reject_Synchronous_Connection_Request 0x002A /* status */ struct hciRejectSyncConn { uint8_t mac[6]; uint8_t reason; } __packed; - /* ==== BR 2.1 ==== */ -#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */ +#define HCI_CMD_IO_Capability_Request_Reply 0x002B /* complete */ struct hciIoCapabilityRequestReply { uint8_t mac[6]; uint8_t cap; /* HCI_DISPLAY_CAP_* */ @@ -596,7 +680,7 @@ struct hciCmplIoCapabilityRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */ +#define HCI_CMD_User_Confirmation_Request_Reply 0x002C /* complete */ struct hciUserConfRequestReply { uint8_t mac[6]; } __packed; @@ -605,7 +689,7 @@ struct hciCmplUserConfRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */ +#define HCI_CMD_User_Confirmation_Request_Negative_Reply 0x002D /* complete */ struct hciUserConfRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -614,7 +698,7 @@ struct hciCmplUserConfRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */ +#define HCI_CMD_User_Passkey_Request_Reply 0x002E /* complete */ struct hciUserPasskeyRequestReply { uint8_t mac[6]; uint32_t num; @@ -624,7 +708,7 @@ struct hciCmplUserPasskeyRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */ +#define HCI_CMD_User_Passkey_Request_Negative_Reply 0x002F /* complete */ struct hciUserPasskeyRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -633,7 +717,7 @@ struct hciCmplUserPasskeyRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */ +#define HCI_CMD_Remote_OOB_Data_Request_Reply 0x0030 /* complete */ struct hciRemoteOobDataRequestReply { uint8_t mac[6]; uint8_t C[16]; @@ -644,7 +728,7 @@ struct hciCmplRemoteOobDataRequestReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */ +#define HCI_CMD_Remote_OOB_Data_Request_Negative_Reply 0x0033 /* complete */ struct hciRemoteOobDataRequestNegativeReply { uint8_t mac[6]; } __packed; @@ -653,7 +737,7 @@ struct hciCmplRemoteOobDataRequestNegativeReply { uint8_t mac[6]; } __packed; -#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */ +#define HCI_CMD_IO_Capability_Request_Negative_Reply 0x0034 /* complete */ struct hciIoCapabilityRequestNegativeReply { uint8_t mac[6]; uint8_t reason; @@ -663,10 +747,9 @@ struct hciCmplIoCapabilityRequestNegativeReply { uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Create_Physical_link 0x0035 /* status */ +#define HCI_CMD_Create_Physical_link 0x0035 /* status */ struct hciCreatePhysicalLink { uint8_t physLinkHandle; uint8_t dedicatedAmpKeyLength; @@ -674,7 +757,7 @@ struct hciCreatePhysicalLink { uint8_t dedicatedAmpKey; } __packed; -#define HCI_CMD_Accept_Physical_link 0x0036 /* status */ +#define HCI_CMD_Accept_Physical_link 0x0036 /* status */ struct hciAcceptPhysicalLink { uint8_t physLinkHandle; uint8_t dedicatedAmpKeyLength; @@ -682,32 +765,32 @@ struct hciAcceptPhysicalLink { uint8_t dedicatedAmpKey; } __packed; -#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */ +#define HCI_CMD_Disconnect_Physical_link 0x0037 /* status */ struct hciDisconnectPhysicalLink { uint8_t physLinkHandle; uint8_t reason; } __packed; -#define HCI_CMD_Create_Logical_link 0x0038 /* status */ +#define HCI_CMD_Create_Logical_link 0x0038 /* status */ struct hciCreateLogicalLink { uint8_t physLinkHandle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; -#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */ +#define HCI_CMD_Accept_Logical_Link 0x0039 /* status */ struct hciAcceptLogicalLink { uint8_t physLinkHandle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; -#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */ +#define HCI_CMD_Disconnect_Logical_link 0x003A /* status */ struct hciDisconnectLogicalLink { uint8_t physLinkHandle; } __packed; -#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */ +#define HCI_CMD_Logical_Link_Cancel 0x003B /* complete */ struct hciLogicalLinkCancel { uint8_t physLinkHandle; uint8_t txFlowSpecID; @@ -718,17 +801,16 @@ struct hciCmplLogicalLinkCancel { uint8_t txFlowSpecID; } __packed; -#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */ +#define HCI_CMD_Flow_Spec_Modify 0x003C /* status */ struct hciFlowSpecModify { uint16_t handle; uint8_t txFlowSpec[16]; uint8_t rxFlowSpec[16]; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */ +#define HCI_CMD_Enhanced_Setup_Synchronous_Connection 0x003D /* status */ struct hciEnhSetupSyncConn { uint16_t conn; uint32_t txBandwidth; @@ -756,7 +838,7 @@ struct hciEnhSetupSyncConn { uint8_t retransmissionEffort; } __packed; -#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */ +#define HCI_CMD_Enhanced_Accept_Synchronous_Connection 0x003E /* status */ struct hciEnhAcceptSyncConn { uint8_t mac[6]; uint32_t txBandwidth; @@ -784,14 +866,14 @@ struct hciEnhAcceptSyncConn { uint8_t retransmissionEffort; } __packed; -#define HCI_CMD_Truncated_Page 0x003F /* status */ +#define HCI_CMD_Truncated_Page 0x003F /* status */ struct hciTruncatedPage { uint8_t mac[6]; uint8_t PSRM; uint16_t clockOffset; /* possibly | HCI_CLOCK_OFST_VALID */ } __packed; -#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */ +#define HCI_CMD_Truncated_Page_Cancel 0x0040 /* complete */ struct hciTruncatedPageCancel { uint8_t mac[6]; } __packed; @@ -800,7 +882,7 @@ struct hciCmplTruncatedPageCancel { uint8_t mac[6]; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast 0x0041 /* complete */ struct hciSetConnectionlessSlaveBroadcast { uint8_t enabled; uint8_t ltAddr; /* 1..7 */ @@ -816,7 +898,8 @@ struct hciCmplSetConnectionlessSlaveBroadcast { uint16_t interval; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive 0x0042 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive 0x0042 /* complete \ + */ struct hciSetConnectionlessSlaveBroadcastReceive { uint8_t enabled; uint8_t mac[6]; /* add rof tranmitter */ @@ -836,9 +919,9 @@ struct hciCmplSetConnectionlessSlaveBroadcastReceive { uint8_t ltAddr; /* 1..7 */ } __packed; -#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */ +#define HCI_CMD_Start_Synchronisation_Train 0x0043 /* status */ -#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */ +#define HCI_CMD_Receive_Synchronisation_Train 0x0044 /* status */ struct hciReceiveSyncTrain { uint8_t mac[6]; uint16_t syncScanTimeout; @@ -846,7 +929,7 @@ struct hciReceiveSyncTrain { uint16_t syncScanInterval; } __packed; -#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */ +#define HCI_CMD_Remote_OOB_Extended_Data_Request_Reply 0x0045 /* complete */ struct hciRemoteOobExtendedDataRequestReply { uint8_t mac[6]; uint8_t C_192[16]; @@ -859,23 +942,18 @@ struct hciCmplRemoteOobExtendedDataRequestReply { uint8_t mac[6]; } __packed; - - - - -#define HCI_OGF_Link_Policy 2 - +#define HCI_OGF_Link_Policy 2 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Hold_Mode 0x0001 /* status */ +#define HCI_CMD_Hold_Mode 0x0001 /* status */ struct hciHoldMode { uint16_t conn; uint16_t holdModeMaxInt; uint16_t holdModeMinInt; } __packed; -#define HCI_CMD_Sniff_Mode 0x0003 /* status */ +#define HCI_CMD_Sniff_Mode 0x0003 /* status */ struct hciSniffMode { uint16_t conn; uint16_t sniffMaxInt; @@ -884,24 +962,24 @@ struct hciSniffMode { uint16_t sniffTimeout; } __packed; -#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */ +#define HCI_CMD_Exit_Sniff_Mode 0x0004 /* status */ struct hciExitSniffMode { uint16_t conn; } __packed; -#define HCI_CMD_Park_State 0x0005 /* status */ +#define HCI_CMD_Park_State 0x0005 /* status */ struct hciParkState { uint16_t conn; uint16_t beaconMaxInt; uint16_t beaconMinInt; } __packed; -#define HCI_CMD_Exit_Park_State 0x0006 /* status */ +#define HCI_CMD_Exit_Park_State 0x0006 /* status */ struct hciExitParkState { uint16_t conn; } __packed; -#define HCI_CMD_QoS_Setup 0x0007 /* status */ +#define HCI_CMD_QoS_Setup 0x0007 /* status */ struct hisQosSetup { uint16_t conn; uint8_t flags; @@ -912,7 +990,7 @@ struct hisQosSetup { uint32_t delayVariation; } __packed; -#define HCI_CMD_Role_Discovery 0x0009 /* complete */ +#define HCI_CMD_Role_Discovery 0x0009 /* complete */ struct hciRoleDiscovery { uint16_t conn; } __packed; @@ -920,13 +998,13 @@ struct hciCmplRoleDiscovery { uint8_t status; } __packed; -#define HCI_CMD_Switch_Role 0x000B /* status */ +#define HCI_CMD_Switch_Role 0x000B /* status */ struct hciSwitchRole { uint8_t mac[6]; uint8_t becomeSlave; } __packed; -#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */ +#define HCI_CMD_Read_Link_Policy_Settings 0x000C /* complete */ struct hciReadLinkPolicySettings { uint16_t conn; } __packed; @@ -936,7 +1014,7 @@ struct hciCmplReadLinkPolicySettings { uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; -#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */ +#define HCI_CMD_Write_Link_Policy_Settings 0x000D /* complete */ struct hciWriteLinkPolicySettings { uint16_t conn; uint16_t policy; /* HCI_LINK_POLICY_* */ @@ -946,16 +1024,15 @@ struct hciCmplWriteLinkPolicySettings { uint16_t conn; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */ +#define HCI_CMD_Read_Default_Link_Policy_Settings 0x000E /* complete */ struct hciCmplReadDefaultLinkPolicySettings { uint8_t status; uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; -#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */ +#define HCI_CMD_Write_Default_Link_Policy_Settings 0x000F /* complete */ struct hciWriteDefaultLinkPolicySettings { uint16_t policy; /* HCI_LINK_POLICY_* */ } __packed; @@ -963,7 +1040,7 @@ struct hciCmplWriteDefaultLinkPolicySettings { uint8_t status; } __packed; -#define HCI_CMD_Flow_Specification 0x0010 /* status */ +#define HCI_CMD_Flow_Specification 0x0010 /* status */ struct hisFlowSpecification { uint16_t conn; uint8_t flags; @@ -975,10 +1052,9 @@ struct hisFlowSpecification { uint32_t accessLatency; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */ +#define HCI_CMD_Sniff_Subrating 0x0011 /* complete */ struct hciSniffSubrating { uint16_t conn; uint16_t maxLatency; @@ -990,16 +1066,11 @@ struct hciCmplSniffSubrating { uint16_t conn; } __packed; - - - - -#define HCI_OGF_Controller_and_Baseband 3 - +#define HCI_OGF_Controller_and_Baseband 3 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */ +#define HCI_CMD_Set_Event_Mask 0x0001 /* complete */ struct hciSetEventMask { uint64_t mask; /* bitmask of HCI_EVENT_* */ } __packed; @@ -1007,12 +1078,12 @@ struct hciCmplSetEventMask { uint8_t status; } __packed; -#define HCI_CMD_Reset 0x0003 /* complete */ +#define HCI_CMD_Reset 0x0003 /* complete */ struct hciCmplReset { uint8_t status; } __packed; -#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */ +#define HCI_CMD_Set_Event_Filter 0x0005 /* complete */ struct hciSetEventFilter { uint8_t filterType; /* HCI_FILTER_TYPE_* */ /* more things are optional here */ @@ -1021,7 +1092,7 @@ struct hciCmplSetEventFiler { uint8_t status; } __packed; -#define HCI_CMD_Flush 0x0008 /* complete */ +#define HCI_CMD_Flush 0x0008 /* complete */ struct hciFlush { uint16_t conn; } __packed; @@ -1030,13 +1101,13 @@ struct hciCmplFlush { uint16_t conn; } __packed; -#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */ +#define HCI_CMD_Read_PIN_Type 0x0009 /* complete */ struct hciCmplReadPinType { uint8_t status; uint8_t isFixed; } __packed; -#define HCI_CMD_Write_PIN_Type 0x000A /* complete */ +#define HCI_CMD_Write_PIN_Type 0x000A /* complete */ struct hciWritePinType { uint8_t isFixed; } __packed; @@ -1044,12 +1115,12 @@ struct hciCmplWritePinType { uint8_t status; } __packed; -#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */ +#define HCI_CMD_Create_New_Unit_Key 0x000B /* complete */ struct hciCmplCreateNewUnitKey { uint8_t status; } __packed; -#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */ +#define HCI_CMD_Read_Stored_Link_Key 0x000D /* complete */ struct hciReadStoredLinkKey { uint8_t mac[6]; uint8_t readAll; @@ -1060,7 +1131,7 @@ struct hciCmplReadStoredLinkKey { uint16_t numKeysRead; } __packed; -#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */ +#define HCI_CMD_Write_Stored_Link_Key 0x0011 /* complete */ struct hciWriteStoredLinkKeyItem { uint8_t mac[6]; uint8_t key[16]; @@ -1074,7 +1145,7 @@ struct hciCmplWriteStoredLinkKey { uint8_t numKeysWritten; } __packed; -#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */ +#define HCI_CMD_Delete_Stored_Link_Key 0x0012 /* complete */ struct hciDeleteStoredLinkKey { uint8_t mac[6]; uint8_t deleteAll; @@ -1084,7 +1155,7 @@ struct hciCmplDeleteStoredLinkKey { uint8_t numKeysDeleted; } __packed; -#define HCI_CMD_Write_Local_Name 0x0013 /* complete */ +#define HCI_CMD_Write_Local_Name 0x0013 /* complete */ struct hciWriteLocalName { char name[HCI_DEV_NAME_LEN]; } __packed; @@ -1092,19 +1163,19 @@ struct hciCmplWriteLocalName { uint8_t status; } __packed; -#define HCI_CMD_Read_Local_Name 0x0014 /* complete */ +#define HCI_CMD_Read_Local_Name 0x0014 /* complete */ struct hciCmplReadLocalName { uint8_t status; char name[HCI_DEV_NAME_LEN]; } __packed; -#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */ +#define HCI_CMD_Read_Connection_Accept_Timeout 0x0015 /* complete */ struct hciCmplReadConnAcceptTimeout { uint8_t status; uint16_t timeout; /* in units of 0.625ms 1..0xB540 */ } __packed; -#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */ +#define HCI_CMD_Write_Connection_Accept_Timeout 0x0016 /* complete */ struct hciWriteConnAcceptTimeout { uint16_t timeout; /* in units of 0.625ms 1..0xB540 */ } __packed; @@ -1112,13 +1183,13 @@ struct hciCmplWriteConnAcceptTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */ +#define HCI_CMD_Read_Page_Timeout 0x0017 /* complete */ struct hciCmplReadPageTimeout { uint8_t status; uint16_t timeout; } __packed; -#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */ +#define HCI_CMD_Write_Page_Timeout 0x0018 /* complete */ struct hciWritePageTimeout { uint16_t timeout; } __packed; @@ -1126,13 +1197,13 @@ struct hciCmplWritePageTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */ +#define HCI_CMD_Read_Scan_Enable 0x0019 /* complete */ struct hciCmplReadScanEnable { uint8_t status; uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */ } __packed; -#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */ +#define HCI_CMD_Write_Scan_Enable 0x001A /* complete */ struct hciWriteScanEnable { uint8_t state; /* bitmask of HCI_SCAN_ENABLE_* */ } __packed; @@ -1140,14 +1211,14 @@ struct hciCmplWriteScanEnable { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */ +#define HCI_CMD_Read_Page_Scan_Activity 0x001B /* complete */ struct hciCmplReadPageScanActivity { uint8_t status; uint16_t scanInterval; uint16_t scanWindow; } __packed; -#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */ +#define HCI_CMD_Write_Page_Scan_Activity 0x001C /* complete */ struct hciWritePageScanActivity { uint16_t scanInterval; uint16_t scanWindow; @@ -1156,14 +1227,14 @@ struct hciCmplWritePageScanActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */ +#define HCI_CMD_Read_Inquiry_Scan_Activity 0x001D /* complete */ struct hciCmplReadInquiryScanActivity { uint8_t status; uint16_t scanInterval; uint16_t scanWindow; } __packed; -#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */ +#define HCI_CMD_Write_Inquiry_Scan_Activity 0x001E /* complete */ struct hciWriteInquiryScanActivity { uint16_t scanInterval; uint16_t scanWindow; @@ -1172,13 +1243,13 @@ struct hciCmplWriteInquiryScanActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */ +#define HCI_CMD_Read_Authentication_Enable 0x001F /* complete */ struct hciCmplReadAuthEnable { uint8_t status; uint8_t authRequired; } __packed; -#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */ +#define HCI_CMD_Write_Authentication_Enable 0x0020 /* complete */ struct hciWriteAuthEnable { uint8_t authRequired; } __packed; @@ -1186,13 +1257,15 @@ struct hciCmplWriteAuthEnable { uint8_t status; } __packed; -#define HCI_CMD_Read_Encryption_Mode 0x0021 /* complete *//* deprecated in BT 2.1+ */ +#define HCI_CMD_Read_Encryption_Mode \ + 0x0021 /* complete */ /* deprecated in BT 2.1+ */ struct hciCmplReadEncryptionMode { uint8_t status; uint8_t encrRequired; } __packed; -#define HCI_CMD_Write_Encryption_Mode 0x0022 /* complete *//* deprecated in BT 2.1+ */ +#define HCI_CMD_Write_Encryption_Mode \ + 0x0022 /* complete */ /* deprecated in BT 2.1+ */ struct hciWriteEncryptionMode { uint8_t encrRequired; } __packed; @@ -1200,13 +1273,13 @@ struct hciCmplWriteEncryptionMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */ +#define HCI_CMD_Read_Class_Of_Device 0x0023 /* complete */ struct hciCmplReadClassOfDevice { uint8_t status; uint8_t cls[3]; } __packed; -#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */ +#define HCI_CMD_Write_Class_Of_Device 0x0024 /* complete */ struct hciWriteClassOfDevice { uint8_t cls[3]; } __packed; @@ -1214,13 +1287,13 @@ struct hciCmplWriteClassOfDevice { uint8_t status; } __packed; -#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */ +#define HCI_CMD_Read_Voice_Setting 0x0025 /* complete */ struct hciCmplReadVoiceSetting { uint8_t status; uint16_t voiceSetting; } __packed; -#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */ +#define HCI_CMD_Write_Voice_Setting 0x0026 /* complete */ struct hciWriteVoiceSetting { uint16_t voiceSetting; } __packed; @@ -1228,7 +1301,7 @@ struct hciCmplWriteVoiceSetting { uint8_t status; } __packed; -#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */ +#define HCI_CMD_Read_Automatic_Flush_Timeout 0x0027 /* complete */ struct hciReadAutoFlushTimeout { uint16_t conn; } __packed; @@ -1238,7 +1311,7 @@ struct hciCmplReadAutoFlushTimeout { uint16_t timeout; } __packed; -#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */ +#define HCI_CMD_Write_Automatic_Flush_Timeout 0x0028 /* complete */ struct hciWriteAutoFlushTimeout { uint16_t conn; uint16_t timeout; @@ -1248,13 +1321,13 @@ struct hciCmplWriteAutoFlushTimeout { uint16_t conn; } __packed; -#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */ +#define HCI_CMD_Read_Num_Broadcast_Retransmissions 0x0029 /* complete */ struct hciCmplReadNumBroadcastRetransmissions { uint8_t status; uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */ } __packed; -#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */ +#define HCI_CMD_Write_Num_Broadcast_Retransmissions 0x002A /* complete */ struct hciWriteNumBroadcastRetransmissions { uint8_t numRetransmissions; /* 0 .. 0xFE => 1 .. 255 TXes */ } __packed; @@ -1262,13 +1335,13 @@ struct hciCmplWriteNumBroadcastRetransmissions { uint8_t status; } __packed; -#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */ +#define HCI_CMD_Read_Hold_Mode_Activity 0x002B /* complete */ struct hciCmplReadHoldModeActivity { uint8_t status; uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */ } __packed; -#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */ +#define HCI_CMD_Write_Hold_Mode_Activity 0x002C /* complete */ struct hciWriteHoldModeActivity { uint8_t holdModeActivity; /* bitfield if HCI_HOLD_MODE_SUSPEND_* */ } __packed; @@ -1276,7 +1349,7 @@ struct hciCmplWriteHoldModeActivity { uint8_t status; } __packed; -#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */ +#define HCI_CMD_Read_Transmit_Power_Level 0x002D /* complete */ struct hciReadTransmitPowerLevel { uint16_t conn; uint8_t max; /* else current */ @@ -1287,13 +1360,13 @@ struct hciCmplReadTransmitPowerLevel { uint8_t txPower; /* actually an int8_t */ } __packed; -#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */ +#define HCI_CMD_Read_SCO_Flow_Control_Enable 0x002E /* complete */ struct hciCmplReadSyncFlowCtrl { uint8_t status; uint8_t syncFlowCtrlOn; } __packed; -#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */ +#define HCI_CMD_Write_SCO_Flow_Control_Enable 0x002F /* complete */ struct hciWriteSyncFlowCtrlEnable { uint8_t syncFlowCtrlOn; } __packed; @@ -1301,7 +1374,7 @@ struct hciCmplWriteSyncFlowCtrlEnable { uint8_t status; } __packed; -#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */ +#define HCI_CMD_Set_Controller_To_Host_Flow_Control 0x0031 /* complete */ struct hciSetControllerToHostFlowControl { uint8_t chipToHostFlowCtrl; /* bitmask of HCI_TO_HOST_FLOW_CTRL_* */ } __packed; @@ -1309,7 +1382,7 @@ struct hciCmplSetControllerToHostFlowControl { uint8_t status; } __packed; -#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */ +#define HCI_CMD_Host_Buffer_Size 0x0033 /* complete */ struct hciHostBufferSize { uint16_t maxAclPacket; uint8_t maxScoPacket; @@ -1320,7 +1393,9 @@ struct hciCmplHostBufferSize { uint8_t status; } __packed; -#define HCI_CMD_Host_Number_Of_Completed_Packets 0x0035 /* special: can be sent anytime (not subj to cmd flow control), does not generate events unless error */ +#define HCI_CMD_Host_Number_Of_Completed_Packets \ + 0x0035 /* special: can be sent anytime (not subj to cmd flow control), \ + does not generate events unless error */ struct hciHostNumberOfCompletedPacketsItem { uint16_t conn; uint16_t numCompletedPackets; @@ -1330,33 +1405,35 @@ struct hciHostNumberOfCompletedPackets { struct hciHostNumberOfCompletedPacketsItem items[]; } __packed; -#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */ +#define HCI_CMD_Read_Link_Supervision_Timeout 0x0036 /* complete */ struct hciReadLinkSupervisionTimeout { uint16_t conn; } __packed; struct hciCmplReadLinkSupervisionTimeout { uint8_t status; uint16_t conn; - uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */ + uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required + support 0x0190 - 0xffff */ } __packed; -#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */ +#define HCI_CMD_Write_Link_Supervision_Timeout 0x0037 /* complete */ struct hciWriteLinkSupervisionTimeout { uint16_t conn; - uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required support 0x0190 - 0xffff */ + uint16_t timeout; /* in units of 0.625ms allowed: 1..0xffff, required + support 0x0190 - 0xffff */ } __packed; struct hciCmplWriteLinkSupervisionTimeout { uint8_t status; uint16_t conn; } __packed; -#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */ +#define HCI_CMD_Read_Number_Of_Supported_IAC 0x0038 /* complete */ struct hciCmplReadNumberOfSupportedIac { uint8_t status; uint8_t numSupportedIac; } __packed; -#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */ +#define HCI_CMD_Read_Current_IAC_LAP 0x0039 /* complete */ struct hciCmplReadCurrentIacItem { uint8_t iac_lap[3]; } __packed; @@ -1366,7 +1443,7 @@ struct hciCmplReadCurrentIac { struct hciCmplReadCurrentIacItem items[]; } __packed; -#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */ +#define HCI_CMD_Write_Current_IAC_LAP 0x003A /* complete */ struct hciWriteCurrentIacLapItem { uint8_t iacLap[3]; } __packed; @@ -1378,13 +1455,13 @@ struct hciCmplWriteCurrentIacLap { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */ +#define HCI_CMD_Read_Page_Scan_Period_Mode 0x003B /* complete */ struct hciCmplReadPageScanPeriodMode { uint8_t status; uint8_t mode; } __packed; -#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */ +#define HCI_CMD_Write_Page_Scan_Period_Mode 0x003C /* complete */ struct hciWritePageScanPeriodMode { uint8_t mode; } __packed; @@ -1392,13 +1469,15 @@ struct hciCmplWritePageScanPeriodMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Mode 0x003D /* complete *//* deprecated in BT 1.2+ */ +#define HCI_CMD_Read_Page_Scan_Mode \ + 0x003D /* complete */ /* deprecated in BT 1.2+ */ struct hciCmplReadPageScanMode { uint8_t status; uint8_t pageScanMode; /* nonzero modes are optional */ } __packed; -#define HCI_CMD_Write_Page_Scan_Mode 0x003E /* complete *//* deprecated in BT 1.2+ */ +#define HCI_CMD_Write_Page_Scan_Mode \ + 0x003E /* complete */ /* deprecated in BT 1.2+ */ struct hciWritePageScanMode { uint8_t pageScanMode; /* nonzero modes are optional */ } __packed; @@ -1406,10 +1485,9 @@ struct hciCmplWritePageScanMode { uint8_t status; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */ +#define HCI_CMD_Set_AFH_Host_Channel_Classification 0x003F /* complete */ struct hciSetAfhHostChannelClassification { uint8_t channels[10]; } __packed; @@ -1417,13 +1495,13 @@ struct hciCmplSetAfhHostChannelClassification { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */ +#define HCI_CMD_Read_Inquiry_Scan_Type 0x0042 /* complete */ struct hciCmplReadInquiryScanType { uint8_t status; uint8_t interlaced; /* optional */ } __packed; -#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */ +#define HCI_CMD_Write_Inquiry_Scan_Type 0x0043 /* complete */ struct hciWriteInquiryScanType { uint8_t interlaced; /* optional */ } __packed; @@ -1431,13 +1509,13 @@ struct hciCmplWriteInquiryScanType { uint8_t status; } __packed; -#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */ +#define HCI_CMD_Read_Inquiry_Mode 0x0044 /* complete */ struct hciCmplReadInquryMode { uint8_t status; uint8_t inqMode; /* HCI_INQ_MODE_* */ } __packed; -#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */ +#define HCI_CMD_Write_Inquiry_Mode 0x0045 /* complete */ struct hciWriteInquiryMode { uint8_t inqMode; /* HCI_INQ_MODE_* */ } __packed; @@ -1445,13 +1523,13 @@ struct hciCmplWriteInquiryMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */ +#define HCI_CMD_Read_Page_Scan_Type 0x0046 /* complete */ struct hciCmplReadPageScanType { uint8_t status; uint8_t interlaced; /* optional */ } __packed; -#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */ +#define HCI_CMD_Write_Page_Scan_Type 0x0047 /* complete */ struct hciWritePageScanType { uint8_t interlaced; /* optional */ } __packed; @@ -1459,13 +1537,13 @@ struct hciCmplWritePageScanType { uint8_t status; } __packed; -#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */ +#define HCI_CMD_Read_AFH_Channel_Assessment_Mode 0x0048 /* complete */ struct hciCmplReadAfhChannelAssessment { uint8_t status; uint8_t channelAssessmentEnabled; } __packed; -#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */ +#define HCI_CMD_Write_AFH_Channel_Assessment_Mode 0x0049 /* complete */ struct hciWriteAfhChannelAssessment { uint8_t channelAssessmentEnabled; } __packed; @@ -1473,17 +1551,16 @@ struct hciCmplWriteAfhChannelAssessment { uint8_t status; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */ +#define HCI_CMD_Read_Extended_Inquiry_Response 0x0051 /* complete */ struct hciCmplReadEIR { uint8_t status; uint8_t useFec; uint8_t data[240]; } __packed; -#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */ +#define HCI_CMD_Write_Extended_Inquiry_Response 0x0052 /* complete */ struct hciWriteEIR { uint8_t useFec; uint8_t data[240]; @@ -1492,18 +1569,18 @@ struct hciCmplWriteEIR { uint8_t status; } __packed; -#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */ +#define HCI_CMD_Refresh_Encryption_Key 0x0052 /* status */ struct hciRefreshEncryptionKey { uint16_t conn; } __packed; -#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */ +#define HCI_CMD_Read_Simple_Pairing_Mode 0x0055 /* complete */ struct hciCmplReadSimplePairingMore { uint8_t status; uint8_t useSsp; } __packed; -#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */ +#define HCI_CMD_Write_Simple_Pairing_Mode 0x0056 /* complete */ struct hciWriteSimplePairingMode { uint8_t useSsp; } __packed; @@ -1511,20 +1588,21 @@ struct hciCmplWriteSimplePairingMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */ +#define HCI_CMD_Read_Local_OOB_Data 0x0057 /* complete */ struct hciCmplReadLocalOobData { uint8_t status; uint8_t C[16]; uint8_t R[16]; } __packed; -#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level 0x0058 /* complete */ +#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level 0x0058 /* complete \ + */ struct hciCmplReadInquiryTransmitPowerLevel { uint8_t status; uint8_t power; /* actually an int8_t */ } __packed; -#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */ +#define HCI_CMD_Write_Inquiry_Transmit_Power_Level 0x0059 /* complete */ struct hciWriteInquiryTransmitPowerLevel { uint8_t power; /* actually an int8_t */ } __packed; @@ -1532,13 +1610,13 @@ struct hciCmplWriteInquiryTransmitPowerLevel { uint8_t status; } __packed; -#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */ +#define HCI_CMD_Read_Default_Erroneous_Data_Reporting 0x005A /* complete */ struct hciCmplReadErroneousDataReporting { uint8_t status; uint8_t reportingEnabled; } __packed; -#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */ +#define HCI_CMD_Write_Default_Erroneous_Data_Reporting 0x005B /* complete */ struct hciWriteErroneousDataReporting { uint8_t reportingEnabled; } __packed; @@ -1546,13 +1624,14 @@ struct hciCmplWriteErroneousDataReporting { uint8_t status; } __packed; -#define HCI_CMD_Enhanced_Flush 0x005F /* status */ +#define HCI_CMD_Enhanced_Flush 0x005F /* status */ struct hciEnhancedFlush { uint16_t conn; - uint8_t which; /* 0 is the only value - flush auto-flushable packets only */ + uint8_t which; /* 0 is the only value - flush auto-flushable packets + only */ } __packed; -#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */ +#define HCI_CMD_Send_Keypress_Notification 0x0060 /* complete */ struct hciSendKeypressNotification { uint8_t mac[6]; uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */ @@ -1562,24 +1641,25 @@ struct hciCmplSendKeypressNotification { uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */ +#define HCI_CMD_Read_Logical_Link_Accept_Timeout 0x0061 /* complete */ struct hciCmplReadLogicalLinkTimeout { uint8_t status; - uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */ + uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support + 0x00A0..0xB540 */ } __packed; -#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */ +#define HCI_CMD_Write_Logical_Link_Accept_Timeout 0x0062 /* complete */ struct hciWriteLogicalLinkTimeout { - uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support 0x00A0..0xB540 */ + uint16_t timeout; /* in units of 0.625ms 1..0xB540. Required support + 0x00A0..0xB540 */ } __packed; struct hciCmplWriteLogicalLinkTimeout { uint8_t status; } __packed; -#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */ +#define HCI_CMD_Set_Event_Mask_Page_2 0x0063 /* complete */ struct hciSetEventMaskPage2 { uint64_t mask; /* bitmask of HCI_EVENT_P2_* */ } __packed; @@ -1587,7 +1667,7 @@ struct hciCmplSetEventMaskPage2 { uint8_t status; } __packed; -#define HCI_CMD_Read_Location_Data 0x0064 /* complete */ +#define HCI_CMD_Read_Location_Data 0x0064 /* complete */ struct hciCmplReadLocationData { uint8_t status; uint8_t regulatoryDomainKnown; @@ -1596,7 +1676,7 @@ struct hciCmplReadLocationData { uint8_t mainsPowered; } __packed; -#define HCI_CMD_Write_Location_Data 0x0065 /* complete */ +#define HCI_CMD_Write_Location_Data 0x0065 /* complete */ struct hciWriteLocationData { uint8_t regulatoryDomainKnown; uint16_t domain; /* ISO3166-1 code if known, else 0x5858 'XX' */ @@ -1607,21 +1687,23 @@ struct hciCmplWriteLocationData { uint8_t status; } __packed; -#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */ +#define HCI_CMD_Read_Flow_Control_Mode 0x0066 /* complete */ struct hciCmplReadFlowControlMode { uint8_t status; - uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */ + uint8_t blockBased; /* block based is for amp, packed-based is for + BR/EDR */ } __packed; -#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */ +#define HCI_CMD_Write_Flow_Control_mode 0x0067 /* complete */ struct hciWriteFlowControlMode { - uint8_t blockBased; /* block based is for amp, packed-based is for BR/EDR */ + uint8_t blockBased; /* block based is for amp, packed-based is for + BR/EDR */ } __packed; struct hciCmplWriteFlowcontrolMode { uint8_t status; } __packed; -#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */ +#define HCI_CMD_Read_Enhanced_Transmit_Power_Level 0x0068 /* complete */ struct hciReadEnhancedTransmitPowerLevel { uint16_t conn; uint8_t max; /* else currurent is read */ @@ -1634,7 +1716,7 @@ struct hciCmplReadEnhancedTransmitPowerLevel { uint8_t txLevel8DPSK; /* actually an int8_t */ } __packed; -#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */ +#define HCI_CMD_Read_Best_Effort_Flush_Timeout 0x0069 /* complete */ struct hciReadBestEffortFlushTimeout { uint16_t logicalLinkHandle; } __packed; @@ -1643,7 +1725,7 @@ struct hciCmplReadBestEffortFlushTimeout { uint32_t bestEffortFlushTimeout; /* in microseconds */ } __packed; -#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */ +#define HCI_CMD_Write_Best_Effort_Flush_Timeout 0x006A /* complete */ struct hciWriteBestEffortFlushTimeout { uint16_t logicalLinkHandle; uint32_t bestEffortFlushTimeout; /* in microseconds */ @@ -1652,23 +1734,22 @@ struct hciCmplWriteBestEffortFlushTimeout { uint8_t status; } __packed; -#define HCI_CMD_Short_Range_Mode 0x006B /* status */ +#define HCI_CMD_Short_Range_Mode 0x006B /* status */ struct hciShortRangeMode { uint8_t physicalLinkHandle; uint8_t shortRangeModeEnabled; } __packed; - /* ==== BT 4.0 ==== */ -#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */ +#define HCI_CMD_Read_LE_Host_Supported 0x006C /* complete */ struct hciCmplReadLeHostSupported { uint8_t status; uint8_t leSupportedHost; uint8_t simultaneousLeHost; } __packed; -#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */ +#define HCI_CMD_Write_LE_Host_Supported 0x006D /* complete */ struct hciWriteLeHostSupported { uint8_t leSupportedHost; uint8_t simultaneousLeHost; @@ -1677,10 +1758,9 @@ struct hciCmplWriteLeHostSupported { uint8_t status; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */ +#define HCI_CMD_Set_MWS_Channel_Parameters 0x006E /* complete */ struct hciSetMwsChannelParams { uint8_t mwsEnabled; uint16_t mwsChannelRxCenterFreq; /* in MHz */ @@ -1693,7 +1773,7 @@ struct hciCmplSetMwsChannelParams { uint8_t status; } __packed; -#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */ +#define HCI_CMD_Set_External_Frame_Configuration 0x006F /* complete */ struct hciSetExternalFrameConfigItem { uint16_t periodDuration; /* in microseconds */ uint8_t periodType; /* HCI_PERIOD_TYPE_* */ @@ -1709,7 +1789,7 @@ struct hciCmplSetExternalFrameConfig { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */ +#define HCI_CMD_Set_MWS_Signalling 0x0070 /* complete */ struct hciSetMwsSignalling { uint16_t mwsRxAssertOffset; /* all of these are in microseconds */ uint16_t mwsRxAssertJitter; @@ -1747,7 +1827,7 @@ struct hciCmplSetMwsSignalling { uint16_t _802TxOnDeassertJitter; } __packed; -#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */ +#define HCI_CMD_Set_MWS_Transport_Layer 0x0071 /* complete */ struct hciSetMwsTransportLayer { uint8_t transportLayer; uint32_t toMwsBaudRate; /* in byte/sec */ @@ -1757,7 +1837,7 @@ struct hciCmplSetMwsTransportLayer { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */ +#define HCI_CMD_Set_MWS_Scan_Frequency_Table 0x0072 /* complete */ struct hciSetMwsScanFrequencyTableItem { uint16_t scanFreqLow; /*in MHz */ uint16_t scanFreqHigh; /*in MHz */ @@ -1770,7 +1850,7 @@ struct hciCmplSetMwsScanFrequencyTable { uint8_t status; } __packed; -#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */ +#define HCI_CMD_Set_MWS_PATTERN_Configuration 0x0073 /* complete */ struct hciSetMwsPatternConfigItem { uint16_t intervalDuration; /* in microseconds */ uint8_t intervalType; /* HCI_MWS_INTERVAL_TYPE_* */ @@ -1784,7 +1864,7 @@ struct hciCmplSetMwsPatternConfig { uint8_t status; } __packed; -#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */ +#define HCI_CMD_Set_Reserved_LT_ADDR 0x0074 /* complete */ struct hciSetReservedLtAddr { uint8_t ltAddr; } __packed; @@ -1793,7 +1873,7 @@ struct hciCmplSetReservedLtAddr { uint8_t ltAddr; } __packed; -#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */ +#define HCI_CMD_Delete_Reserved_LT_ADDR 0x0075 /* complete */ struct hciDeleteReservedLtAddr { uint8_t ltAddr; } __packed; @@ -1802,7 +1882,7 @@ struct hciCmplDeleteReservedLtAddr { uint8_t ltAddr; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Data 0x0076 /* complete */ struct hciSetConnlessSlaveBroadcastData { uint8_t ltAddr; uint8_t fragment; /* HCI_CONNLESS_FRAG_TYPE_* */ @@ -1814,7 +1894,7 @@ struct hciCmplSetConnlessSlaveBroadcastData { uint8_t ltAddr; } __packed; -#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */ +#define HCI_CMD_Read_Synchronisation_Train_Parameters 0x0077 /* complete */ struct hciCmplReadSyncTrainParams { uint8_t status; uint16_t interval; @@ -1822,7 +1902,7 @@ struct hciCmplReadSyncTrainParams { uint8_t serviceData; } __packed; -#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */ +#define HCI_CMD_Write_Synchronisation_Train_Parameters 0x0078 /* complete */ struct hciWriteSyncTrainParams { uint16_t intMin; uint16_t intMax; @@ -1834,13 +1914,13 @@ struct hciCmplWriteSyncTrainParams { uint16_t interval; } __packed; -#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */ +#define HCI_CMD_Read_Secure_Connections_Host_Support 0x0079 /* complete */ struct hciCmplReadSecureConnectionsHostSupport { uint8_t status; uint8_t secureConnectionsSupported; } __packed; -#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */ +#define HCI_CMD_Write_Secure_Connections_Host_Support 0x007A /* complete */ struct hciWriteSecureConnectionsHostSupport { uint8_t secureConnectionsSupported; } __packed; @@ -1848,7 +1928,7 @@ struct hciCmplWriteSecureConnectionsHostSupport { uint8_t status; } __packed; -#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */ +#define HCI_CMD_Read_Authenticated_Payload_Timeout 0x007B /* complete */ struct hciReadAuthedPayloadTimeout { uint16_t conn; } __packed; @@ -1858,7 +1938,7 @@ struct hciCmplReadAuthedPayloadTimeout { uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */ } __packed; -#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */ +#define HCI_CMD_Write_Authenticated_Payload_Timeout 0x007C /* complete */ struct hciWriteAuthedPayloadTimeout { uint16_t conn; uint16_t timeout; /* in units of 10ms, 1 .. 0xffff */ @@ -1868,7 +1948,7 @@ struct hciCmplWriteAuthedPayloadTimeout { uint16_t conn; } __packed; -#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */ +#define HCI_CMD_Read_Local_OOB_Extended_Data 0x007D /* complete */ struct hciCmplReadLocalOobExtendedData { uint8_t status; uint8_t C_192[16]; @@ -1877,13 +1957,13 @@ struct hciCmplReadLocalOobExtendedData { uint8_t R_256[16]; } __packed; -#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */ +#define HCI_CMD_Read_Extended_Page_Timeout 0x007E /* complete */ struct hciCmplReadExtendedPageTimeout { uint8_t status; uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */ +#define HCI_CMD_Write_Extended_Page_Timeout 0x007F /* complete */ struct hciWriteExtendedPageTimeout { uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; @@ -1891,13 +1971,13 @@ struct hciCmplWriteExtendedPageTimeout { uint8_t status; } __packed; -#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */ +#define HCI_CMD_Read_Extended_Inquiry_Length 0x0080 /* complete */ struct hciCmplReadExtendedInquiryLength { uint8_t status; uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */ +#define HCI_CMD_Write_Extended_Inquiry_Length 0x0081 /* complete */ struct hciWriteExtendedInquiryLength { uint16_t timeout; /* in units of 0.625ms 0..0xffff */ } __packed; @@ -1905,16 +1985,11 @@ struct hciCmplWriteExtendedInquiryLength { uint8_t status; } __packed; - - - - -#define HCI_OGF_Informational 4 - +#define HCI_OGF_Informational 4 /* ==== BT 1.1 ==== */ -#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */ +#define HCI_CMD_Read_Local_Version_Information 0x0001 /* complete */ struct hciCmplReadLocalVersion { uint8_t status; uint8_t hciVersion; /* HCI_VERSION_* */ @@ -1924,19 +1999,19 @@ struct hciCmplReadLocalVersion { uint16_t lmpSubversion; } __packed; -#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */ +#define HCI_CMD_Read_Local_Supported_Commands 0x0002 /* complete */ struct hciCmplReadLocalSupportedCommands { uint8_t status; uint64_t bitfield; } __packed; -#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */ +#define HCI_CMD_Read_Local_Supported_Features 0x0003 /* complete */ struct hciCmplReadLocalSupportedFeatures { uint8_t status; - uint64_t features; /* bitmask of HCI_LMP_FTR_* */ + uint64_t features; /* bitmask of HCI_LMP_FTR_* */ } __packed; -#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */ +#define HCI_CMD_Read_Local_Extended_Features 0x0004 /* complete */ struct hciReadLocalExtendedFeatures { uint8_t page; } __packed; @@ -1947,7 +2022,7 @@ struct hciCmplReadLocalExtendedFeatures { uint64_t features; /* bitmask of HCI_LMP_EXT_FTR_P* */ } __packed; -#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */ +#define HCI_CMD_Read_Buffer_Size 0x0005 /* complete */ struct hciCmplReadBufferSize { uint8_t status; uint16_t aclBufferLen; @@ -1956,16 +2031,15 @@ struct hciCmplReadBufferSize { uint16_t numScoBuffers; } __packed; -#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */ +#define HCI_CMD_Read_BD_ADDR 0x0009 /* complete */ struct hciCmplReadBdAddr { uint8_t status; uint8_t mac[6]; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */ +#define HCI_CMD_Read_Data_Block_Size 0x000A /* complete */ struct hciCmplReadDataBlockSize { uint8_t status; uint16_t maxAclDataPacketLen; @@ -1973,30 +2047,24 @@ struct hciCmplReadDataBlockSize { uint16_t totalNumDataBlocks; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */ +#define HCI_CMD_Read_Local_Supported_Codecs 0x000B /* complete */ struct hciCmplReadLocalSupportedCodecs { uint8_t status; uint8_t numSupportedCodecs; uint8_t codecs[]; -/* these follow, but due to var array cannot be declared here: - uint8_t numVendorCodecs; - uint32_t vendorCodecs[]; -*/ + /* these follow, but due to var array cannot be declared here: + uint8_t numVendorCodecs; + uint32_t vendorCodecs[]; + */ } __packed; - - - - -#define HCI_OGF_Status 5 - +#define HCI_OGF_Status 5 /* == BT 1.1 == */ -#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */ +#define HCI_CMD_Read_Failed_Contact_Counter 0x0001 /* complete */ struct hciReadFailedContactCounter { uint16_t conn; } __packed; @@ -2006,7 +2074,7 @@ struct hciCmplReadFailedContactCounter { uint16_t counter; } __packed; -#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */ +#define HCI_CMD_Reset_Failed_Contact_Counter 0x0002 /* complete */ struct hciResetFailedContactCounter { uint16_t conn; } __packed; @@ -2015,7 +2083,7 @@ struct hciCmplResetFailedContactCounter { uint16_t conn; } __packed; -#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */ +#define HCI_CMD_Read_Link_Quality 0x0003 /* complete */ struct hciReadLinkQuality { uint16_t conn; } __packed; @@ -2025,7 +2093,7 @@ struct hciCmplReadLinkQuality { uint8_t quality; } __packed; -#define HCI_CMD_Read_RSSI 0x0005 /* complete */ +#define HCI_CMD_Read_RSSI 0x0005 /* complete */ struct hciReadRssi { uint16_t conn; } __packed; @@ -2035,10 +2103,9 @@ struct hciCmplReadRssi { uint8_t RSSI; /* actually an int8_t */ } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */ +#define HCI_CMD_Read_AFH_Channel_Map 0x0006 /* complete */ struct hciReadAfhChannelMap { uint16_t conn; } __packed; @@ -2048,7 +2115,7 @@ struct hciCmplReadAfhChannelMap { uint8_t map[10]; } __packed; -#define HCI_CMD_Read_Clock 0x0007 /* complete */ +#define HCI_CMD_Read_Clock 0x0007 /* complete */ struct hciReadClock { uint16_t conn; uint8_t readRemote; /* else reads local and ignores conn */ @@ -2060,10 +2127,9 @@ struct hciCmplReadClock { uint16_t accuracy; } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */ +#define HCI_CMD_Read_Encryption_Key_Size 0x0008 /* complete */ struct hciReadEncrKeySize { uint16_t conn; } __packed; @@ -2073,7 +2139,7 @@ struct hciCmplReadEncrKeySize { uint8_t keySize; } __packed; -#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */ +#define HCI_CMD_Read_Local_AMP_Info 0x0009 /* complete */ struct hciCmplReadLocalAmpInfo { uint8_t status; uint8_t ampStatus; @@ -2088,7 +2154,7 @@ struct hciCmplReadLocalAmpInfo { uint32_t bestEffortFlushTimeout; } __packed; -#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */ +#define HCI_CMD_Read_Local_AMP_ASSOC 0x000A /* complete */ struct hciReadLocalAmpAssoc { uint8_t physicalLinkHandle; uint16_t lengthSoFar; @@ -2101,7 +2167,7 @@ struct hciCmplReadLocalAmpAssoc { uint8_t ampAssocFragment[]; /* 1.. 248 byutes */ } __packed; -#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */ +#define HCI_CMD_Write_Remote_AMP_ASSOC 0x000B /* complete */ struct hciWriteRemoteAmpAssoc { uint8_t physicalLinkHandle; uint16_t lengthSoFar; @@ -2115,7 +2181,7 @@ struct hciCmplWriteRemoteAmpAssoc { /* ==== BT 4.1 ==== */ -#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */ +#define HCI_CMD_Get_MWS_Transport_Layer_Configuration 0x000C /* complete */ struct hciCmplGetMwsTransportLayerConfigItem { uint8_t transportLayer; uint8_t numBaudRates; @@ -2127,13 +2193,15 @@ struct hciCmplGetMwsTransportLayerConfigBandwidthItem { struct hciCmplGetMwsTransportLayerConfig { uint8_t status; uint8_t numTransports; - struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports items */ -/* this follows: - struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // sum(items[].numbaudRates) items -*/ + struct hciCmplGetMwsTransportLayerConfigItem items[]; /* numTransports + items */ + /* this follows: + struct hciCmplGetMwsTransportLayerConfigBandwidthItem items[] // + sum(items[].numbaudRates) items + */ } __packed; -#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */ +#define HCI_CMD_Set_Triggered_Clock_Capture 0x000D /* complete */ struct hciSetTriggeredClockCapture { uint16_t conn; uint8_t enable; @@ -2145,16 +2213,11 @@ struct hciCmplSetTriggeredClockCapture { uint8_t status; } __packed; - - - - -#define HCI_OGF_LE 8 - +#define HCI_OGF_LE 8 /* ==== BT 4.0 ==== */ -#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */ +#define HCI_CMD_LE_Set_Event_Mask 0x0001 /* complete */ struct hciLeSetEventMask { uint64_t events; /* bitmask of HCI_LE_EVENT_* */ } __packed; @@ -2162,28 +2225,28 @@ struct hciCmplLeSetEventMask { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */ +#define HCI_CMD_LE_Read_Buffer_Size 0x0002 /* complete */ struct hciCmplLeReadBufferSize { uint8_t status; uint16_t leBufferSize; uint8_t leNumBuffers; } __packed; -#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */ +#define HCI_CMD_LE_Read_Local_Supported_Features 0x0003 /* complete */ struct hciCmplLeReadLocalSupportedFeatures { uint8_t status; uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */ } __packed; -#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */ -struct hciLeSetRandomAddress{ +#define HCI_CMD_LE_Set_Random_Address 0x0005 /* complete */ +struct hciLeSetRandomAddress { uint8_t mac[6]; } __packed; -struct hciCmplLeSetRandomAddress{ +struct hciCmplLeSetRandomAddress { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */ +#define HCI_CMD_LE_Set_Adv_Params 0x0006 /* complete */ struct hciLeSetAdvParams { uint16_t advIntervalMin; uint16_t advIntervalMax; @@ -2198,13 +2261,13 @@ struct hciCmplLeSetAdvParams { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */ +#define HCI_CMD_LE_Read_Adv_Channel_TX_Power 0x0007 /* complete */ struct hciCmplLeReadAdvChannelTxPower { uint8_t status; uint8_t txPower; /* actually an int8_t */ } __packed; -#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */ +#define HCI_CMD_LE_Set_Advertising_Data 0x0008 /* complete */ struct hciLeSetAdvData { uint8_t advDataLen; uint8_t advData[31]; @@ -2213,7 +2276,7 @@ struct hciCmplLeSetAdvData { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */ +#define HCI_CMD_LE_Set_Scan_Response_Data 0x0009 /* complete */ struct hciSetScanResponseData { uint8_t scanRspDataLen; uint8_t scanRspData[31]; @@ -2222,7 +2285,7 @@ struct hciCmplSetScanResponseData { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */ +#define HCI_CMD_LE_Set_Advertise_Enable 0x000A /* complete */ struct hciLeSetAdvEnable { uint8_t advOn; } __packed; @@ -2230,7 +2293,7 @@ struct hciCmplLeSetAdvEnable { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */ +#define HCI_CMD_LE_Set_Scan_Parameters 0x000B /* complete */ struct hciLeSetScanParams { uint8_t activeScan; uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */ @@ -2242,7 +2305,7 @@ struct hciCmplLeSetScanParams { uint8_t status; } __packed; -#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */ +#define HCI_CMD_LE_Set_Scan_Enable 0x000C /* complete */ struct hciLeSetScanEnable { uint8_t scanOn; uint8_t filterDuplicates; @@ -2251,7 +2314,7 @@ struct hciCmplLeSetScanEnable { uint8_t status; } __packed; -#define HCI_CMD_LE_Create_Connection 0x000D /* status */ +#define HCI_CMD_LE_Create_Connection 0x000D /* status */ struct hciLeCreateConnection { uint16_t scanInterval; /* in units of 0.625ms, 4..0x4000 */ uint16_t scanWindow; /* in units of 0.625ms, 4..0x4000 */ @@ -2263,27 +2326,29 @@ struct hciLeCreateConnection { uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; -#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */ +#define HCI_CMD_LE_Create_Connection_Cancel 0x000E /* complete */ struct hciCmplLeCreateConnectionCancel { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */ +#define HCI_CMD_LE_Read_Allow_List_Size 0x000F /* complete */ struct hciCmplLeReadAllowListSize { uint8_t status; uint8_t allowlistSize; } __packed; -#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */ +#define HCI_CMD_LE_Clear_Allow_List 0x0010 /* complete */ struct hciCmplLeClearAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */ +#define HCI_CMD_LE_Add_Device_To_Allow_List 0x0011 /* complete */ struct hciLeAddDeviceToAllowList { uint8_t randomAddr; uint8_t mac[6]; @@ -2292,7 +2357,7 @@ struct hciCmplLeAddDeviceToAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */ +#define HCI_CMD_LE_Remove_Device_From_Allow_List 0x0012 /* complete */ struct hciLeRemoveDeviceFromAllowList { uint8_t randomAddr; uint8_t mac[6]; @@ -2301,18 +2366,20 @@ struct hciCmplLeRemoveDeviceFromAllowList { uint8_t status; } __packed; -#define HCI_CMD_LE_Connection_Update 0x0013 /* status */ +#define HCI_CMD_LE_Connection_Update 0x0013 /* status */ struct hciLeConnectionUpdate { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; -#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */ +#define HCI_CMD_LE_Set_Host_Channel_Classification 0x0014 /* complete */ struct hciLeSetHostChannelClassification { uint8_t chMap[5]; } __packed; @@ -2320,7 +2387,7 @@ struct hciCmplLeSetHostChannelClassification { uint8_t status; } __packed; -#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */ +#define HCI_CMD_LE_Read_Channel_Map 0x0015 /* complete */ struct hciLeReadChannelMap { uint16_t conn; } __packed; @@ -2330,12 +2397,12 @@ struct hciCmplLeReadChannelMap { uint8_t chMap[5]; } __packed; -#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */ +#define HCI_CMD_LE_Read_Remote_Used_Features 0x0016 /* status */ struct hciLeReadRemoteUsedFeatures { uint16_t conn; } __packed; -#define HCI_CMD_LE_Encrypt 0x0017 /* complete */ +#define HCI_CMD_LE_Encrypt 0x0017 /* complete */ struct hciLeEncrypt { uint8_t key[16]; uint8_t plaintext[16]; @@ -2345,13 +2412,13 @@ struct hciCmplLeEncrypt { uint8_t encryptedData[16]; } __packed; -#define HCI_CMD_LE_Rand 0x0018 /* complete */ +#define HCI_CMD_LE_Rand 0x0018 /* complete */ struct hciCmplLeRand { uint8_t status; uint64_t rand; } __packed; -#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */ +#define HCI_CMD_LE_Start_Encryption 0x0019 /* status */ struct hciLeStartEncryption { uint16_t conn; uint64_t rand; @@ -2359,7 +2426,7 @@ struct hciLeStartEncryption { uint8_t LTK[16]; } __packed; -#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */ +#define HCI_CMD_LE_LTK_Request_Reply 0x001A /* complete */ struct hciLeLtkRequestReply { uint16_t conn; uint8_t LTK[16]; @@ -2369,7 +2436,7 @@ struct hciCmplLeLtkRequestReply { uint16_t conn; } __packed; -#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */ +#define HCI_CMD_LE_LTK_Request_Negative_Reply 0x001B /* complete */ struct hciLeLtkRequestNegativeReply { uint16_t conn; } __packed; @@ -2378,13 +2445,13 @@ struct hciCmplLeLtkRequestNegativeReply { uint16_t conn; } __packed; -#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */ +#define HCI_CMD_LE_Read_Supported_States 0x001C /* complete */ struct hciCmplLeReadSupportedStates { uint8_t status; uint64_t states; /* bitmask of HCI_LE_STATE_* */ } __packed; -#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */ +#define HCI_CMD_LE_Receiver_Test 0x001D /* complete */ struct hciLeReceiverTest { uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */ } __packed; @@ -2392,7 +2459,7 @@ struct hciCmplLeReceiverTest { uint8_t status; } __packed; -#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */ +#define HCI_CMD_LE_Transmitter_Test 0x001E /* complete */ struct hciLeTransmitterTest { uint8_t radioChannelNum; /* 2402 + radioChannelNum * 2 MHz */ uint8_t lengthOfTestData; @@ -2402,31 +2469,33 @@ struct hciCmplLeTransmitterTest { uint8_t status; } __packed; -#define HCI_CMD_LE_Test_End 0x001F /* complete */ +#define HCI_CMD_LE_Test_End 0x001F /* complete */ struct hciCmplLeTestEnd { uint8_t status; uint16_t numPackets; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */ +#define HCI_CMD_LE_Remote_Conn_Param_Request_Reply 0x0020 /* complete */ struct hciLeRemoteConnParamRequestReply { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connIntervalMax; /* in units of 1.25ms, 6..0x0C80 */ uint16_t connLatency; /* 0..0x1F4 */ uint16_t supervisionTimeout; /* in units of 10ms, 0xA...0x0C80 */ - uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ - uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms 0..0xfff */ + uint16_t minConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ + uint16_t maxConnLen; /* minimum conn len needed in units of 0.625ms + 0..0xfff */ } __packed; struct hciCmplLeRemoteConnParamRequestReply { uint8_t status; uint16_t conn; } __packed; -#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply 0x0021 /* complete */ +#define HCI_CMD_LE_Remote_Conn_Param_Request_Negative_Reply \ + 0x0021 /* complete */ struct hciRemoteConnParamRequestNegativeReply { uint16_t conn; uint8_t reason; @@ -2436,19 +2505,16 @@ struct hciCmplLeRemoteConnParamRequestNegativeReply { uint16_t conn; } __packed; - - /* EVENTS */ - /* ==== BT 1.1 ==== */ -#define HCI_EVT_Inquiry_Complete 0x01 +#define HCI_EVT_Inquiry_Complete 0x01 struct hciEvtInquiryComplete { uint8_t status; } __packed; -#define HCI_EVT_Inquiry_Result 0x02 +#define HCI_EVT_Inquiry_Result 0x02 struct hciEvtInquiryResultItem { uint8_t mac[6]; uint8_t PSRM; @@ -2462,7 +2528,7 @@ struct hciEvtInquiryResult { struct hciEvtInquiryResultItem items[]; } __packed; -#define HCI_EVT_Connection_Complete 0x03 +#define HCI_EVT_Connection_Complete 0x03 struct hciEvtConnComplete { uint8_t status; uint16_t conn; @@ -2471,61 +2537,61 @@ struct hciEvtConnComplete { uint8_t encrypted; } __packed; -#define HCI_EVT_Connection_Request 0x04 +#define HCI_EVT_Connection_Request 0x04 struct hciEvtConnRequest { uint8_t mac[6]; uint8_t deviceClass[3]; uint8_t isAclLink; } __packed; -#define HCI_EVT_Disconnection_Complete 0x05 +#define HCI_EVT_Disconnection_Complete 0x05 struct hciEvtDiscComplete { uint8_t status; uint16_t conn; uint8_t reason; } __packed; -#define HCI_EVT_Authentication_Complete 0x06 +#define HCI_EVT_Authentication_Complete 0x06 struct hciEvtAuthComplete { uint8_t status; uint16_t handle; } __packed; -#define HCI_EVT_Remote_Name_Request_Complete 0x07 +#define HCI_EVT_Remote_Name_Request_Complete 0x07 struct hciEvtRemoteNameReqComplete { uint8_t status; uint8_t mac[6]; char name[HCI_DEV_NAME_LEN]; } __packed; -#define HCI_EVT_Encryption_Change 0x08 +#define HCI_EVT_Encryption_Change 0x08 struct hciEvtEncrChange { uint8_t status; uint16_t conn; uint8_t encrOn; } __packed; -#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09 +#define HCI_EVT_Change_Connection_Link_Key_Complete 0x09 struct hciEvtChangeConnLinkKeyComplete { uint8_t status; uint16_t handle; } __packed; -#define HCI_EVT_Master_Link_Key_Complete 0x0A +#define HCI_EVT_Master_Link_Key_Complete 0x0A struct hciEvtMasterLinkKeyComplete { uint8_t status; uint16_t conn; uint8_t usingTempKey; /* else using semi-permanent key */ } __packed; -#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B +#define HCI_EVT_Read_Remote_Supported_Features_Complete 0x0B struct hciEvtReadRemoteSupportedFeaturesComplete { uint8_t status; uint16_t conn; uint64_t lmpFeatures; /* bitmask of HCI_LMP_FTR_* */ } __packed; -#define HCI_EVT_Read_Remote_Version_Complete 0x0C +#define HCI_EVT_Read_Remote_Version_Complete 0x0C struct hciEvtReadRemoteVersionComplete { uint8_t status; uint16_t conn; @@ -2534,7 +2600,7 @@ struct hciEvtReadRemoteVersionComplete { uint16_t lmpSubversion; } __packed; -#define HCI_EVT_QOS_Setup_Complete 0x0D +#define HCI_EVT_QOS_Setup_Complete 0x0D struct hciEvtQosSetupComplete { uint8_t status; uint16_t conn; @@ -2546,37 +2612,37 @@ struct hciEvtQosSetupComplete { uint32_t delayVariation; } __packed; -#define HCI_EVT_Command_Complete 0x0E +#define HCI_EVT_Command_Complete 0x0E struct hciEvtCmdComplete { uint8_t numCmdCredits; uint16_t opcode; } __packed; -#define HCI_EVT_Command_Status 0x0F +#define HCI_EVT_Command_Status 0x0F struct hciEvtCmdStatus { uint8_t status; uint8_t numCmdCredits; uint16_t opcode; } __packed; -#define HCI_EVT_Hardware_Error 0x10 +#define HCI_EVT_Hardware_Error 0x10 struct hciEvtHwError { uint8_t errCode; } __packed; -#define HCI_EVT_Flush_Occurred 0x11 +#define HCI_EVT_Flush_Occurred 0x11 struct hciEvtFlushOccurred { uint16_t conn; } __packed; -#define HCI_EVT_Role_Change 0x12 +#define HCI_EVT_Role_Change 0x12 struct hciEvtRoleChange { uint8_t status; uint8_t mac[6]; uint8_t amSlave; } __packed; -#define HCI_EVT_Number_Of_Completed_Packets 0x13 +#define HCI_EVT_Number_Of_Completed_Packets 0x13 struct hciEvtNumCompletedPacketsItem { uint16_t conn; uint16_t numPackets; @@ -2586,7 +2652,7 @@ struct hciEvtNumCompletedPackets { struct hciEvtNumCompletedPacketsItem items[]; } __packed; -#define HCI_EVT_Mode_Change 0x14 +#define HCI_EVT_Mode_Change 0x14 struct hciEvtModeChange { uint8_t status; uint16_t conn; @@ -2594,7 +2660,7 @@ struct hciEvtModeChange { uint16_t interval; /* in units of 0.625ms 0..0xffff */ } __packed; -#define HCI_EVT_Return_Link_Keys 0x15 +#define HCI_EVT_Return_Link_Keys 0x15 struct hciEvtReturnLinkKeysItem { uint8_t mac[6]; uint8_t key[16]; @@ -2604,72 +2670,71 @@ struct hciEvtReturnLinkKeys { struct hciEvtReturnLinkKeysItem items[]; } __packed; -#define HCI_EVT_PIN_Code_Request 0x16 +#define HCI_EVT_PIN_Code_Request 0x16 struct hciEvtPinCodeReq { uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Key_Request 0x17 +#define HCI_EVT_Link_Key_Request 0x17 struct hciEvtLinkKeyReq { uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Key_Notification 0x18 +#define HCI_EVT_Link_Key_Notification 0x18 struct hciEvtLinkKeyNotif { uint8_t mac[6]; uint8_t key[16]; uint8_t keyType; /* HCI_KEY_TYPE_ */ } __packed; -#define HCI_EVT_Loopback_Command 0x19 +#define HCI_EVT_Loopback_Command 0x19 /* data is the sent command, up to 252 bytes of it */ -#define HCI_EVT_Data_Buffer_Overflow 0x1A +#define HCI_EVT_Data_Buffer_Overflow 0x1A struct hciEvtDataBufferOverflow { uint8_t aclLink; } __packed; -#define HCI_EVT_Max_Slots_Change 0x1B +#define HCI_EVT_Max_Slots_Change 0x1B struct hciEvtMaxSlotsChange { uint16_t conn; uint8_t lmpMaxSlots; } __packed; -#define HCI_EVT_Read_Clock_Offset_Complete 0x1C +#define HCI_EVT_Read_Clock_Offset_Complete 0x1C struct hciEvtReadClockOffsetComplete { uint8_t status; uint16_t conn; uint16_t clockOffset; } __packed; -#define HCI_EVT_Connection_Packet_Type_Changed 0x1D +#define HCI_EVT_Connection_Packet_Type_Changed 0x1D struct hciEvtConnPacketTypeChanged { uint8_t status; uint16_t conn; uint16_t packetsAllowed; /* HCI_PKT_TYP_* */ } __packed; -#define HCI_EVT_QoS_Violation 0x1E +#define HCI_EVT_QoS_Violation 0x1E struct hciEvtQosViolation { uint16_t conn; } __packed; -#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */ +#define HCI_EVT_Page_Scan_Mode_Change 0x1F /* deprecated in BT 1.2+ */ struct hciEvtPsmChange { uint8_t mac[6]; uint8_t PSM; } __packed; -#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20 +#define HCI_EVT_Page_Scan_Repetition_Mode_Change 0x20 struct hciEvtPrsmChange { uint8_t mac[6]; uint8_t PSRM; } __packed; - /* ==== BT 1.2 ==== */ -#define HCI_EVT_Flow_Specification_Complete 0x21 +#define HCI_EVT_Flow_Specification_Complete 0x21 struct hciEvtFlowSpecComplete { uint8_t status; uint16_t conn; @@ -2681,7 +2746,7 @@ struct hciEvtFlowSpecComplete { uint32_t latency; } __packed; -#define HCI_EVT_Inquiry_Result_With_RSSI 0x22 +#define HCI_EVT_Inquiry_Result_With_RSSI 0x22 struct hciEvtInquiryResultWithRssiItem { uint8_t mac[6]; uint8_t PSRM; @@ -2695,7 +2760,7 @@ struct hciEvtInquiryResultWithRssi { struct hciEvtInquiryResultWithRssiItem items[]; } __packed; -#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23 +#define HCI_EVT_Read_Remote_Extended_Features_Complete 0x23 struct hciEvtReadRemoteExtFeturesComplete { uint8_t status; uint16_t conn; @@ -2704,7 +2769,7 @@ struct hciEvtReadRemoteExtFeturesComplete { uint64_t extLmpFeatures; /* HCI_LMP_EXT_FTR_P* & HCI_LMP_FTR_* */ } __packed; -#define HCI_EVT_Synchronous_Connection_Complete 0x2C +#define HCI_EVT_Synchronous_Connection_Complete 0x2C struct hciEvtSyncConnComplete { uint8_t status; uint16_t conn; @@ -2717,7 +2782,7 @@ struct hciEvtSyncConnComplete { uint8_t airMode; /* HCI_SCO_AIR_MODE_* */ } __packed; -#define HCI_EVT_Synchronous_Connection_Changed 0x2D +#define HCI_EVT_Synchronous_Connection_Changed 0x2D struct hciEvtSyncConnChanged { uint8_t status; uint16_t conn; @@ -2727,10 +2792,9 @@ struct hciEvtSyncConnChanged { uint16_t txPacketLen; } __packed; - /* ==== BT 2.1 ==== */ -#define HCI_EVT_Sniff_Subrating 0x2E +#define HCI_EVT_Sniff_Subrating 0x2E struct hciEvtSniffSubrating { uint8_t status; uint16_t conn; @@ -2740,7 +2804,7 @@ struct hciEvtSniffSubrating { uint16_t minLocalTimeout; } __packed; -#define HCI_EVT_Extended_Inquiry_Result 0x2F +#define HCI_EVT_Extended_Inquiry_Result 0x2F struct hciEvtExtendedInquiryResult { uint8_t numResponses; /* must be 1 */ uint8_t mac[6]; @@ -2752,18 +2816,18 @@ struct hciEvtExtendedInquiryResult { uint8_t EIR[240]; } __packed; -#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30 +#define HCI_EVT_Encryption_Key_Refresh_Complete 0x30 struct hciEvtEncrKeyRefreshComplete { uint8_t status; uint16_t conn; } __packed; -#define HCI_EVT_IO_Capability_Request 0x31 +#define HCI_EVT_IO_Capability_Request 0x31 struct hciEvtIoCapRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_IO_Capability_Response 0x32 +#define HCI_EVT_IO_Capability_Response 0x32 struct hciEvtIoCapResponse { uint8_t mac[6]; uint8_t ioCapability; /* HCI_DISPLAY_CAP_* */ @@ -2771,90 +2835,89 @@ struct hciEvtIoCapResponse { uint8_t authReqments; /* HCI_AUTH_REQMENT_ */ } __packed; -#define HCI_EVT_User_Confirmation_Request 0x33 +#define HCI_EVT_User_Confirmation_Request 0x33 struct hciEvtUserConfRequest { uint8_t mac[6]; uint32_t numericValue; } __packed; -#define HCI_EVT_User_Passkey_Request 0x34 +#define HCI_EVT_User_Passkey_Request 0x34 struct hciEvtUserPasskeyRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_Remote_OOB_Data_Request 0x35 +#define HCI_EVT_Remote_OOB_Data_Request 0x35 struct hciEvtRemoteOobRequest { uint8_t mac[6]; } __packed; -#define HCI_EVT_Simple_Pairing_Complete 0x36 +#define HCI_EVT_Simple_Pairing_Complete 0x36 struct hciEvtSimplePairingComplete { uint8_t status; uint8_t mac[6]; } __packed; -#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38 +#define HCI_EVT_Link_Supervision_Timeout_Changed 0x38 struct hciEvtLinkSupervisionTimeoutChanged { uint16_t conn; uint16_t timeout; /* in units of 0.625 ms 1..0xffff */ } __packed; -#define HCI_EVT_Enhanced_Flush_Complete 0x39 +#define HCI_EVT_Enhanced_Flush_Complete 0x39 struct hciEvtEnahncedFlushComplete { uint16_t conn; } __packed; -#define HCI_EVT_User_Passkey_Notification 0x3B +#define HCI_EVT_User_Passkey_Notification 0x3B struct hciEvtUserPasskeyNotif { uint8_t mac[6]; uint32_t passkey; } __packed; -#define HCI_EVT_Keypress_Notification 0x3C +#define HCI_EVT_Keypress_Notification 0x3C struct hciEvtKeypressNotification { uint8_t mac[6]; uint8_t notifType; /* HCI_SSP_KEY_ENTRY_* */ } __packed; -#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D +#define HCI_EVT_Remote_Host_Supported_Features_Notification 0x3D struct hciEvtRemoteHostSupportedFeatures { uint8_t mac[6]; uint64_t hostSupportedFeatures; /* HCI_LMP_FTR_* */ } __packed; - /* ==== BT 3.0 ==== */ -#define HCI_EVT_Physical_Link_Complete 0x40 +#define HCI_EVT_Physical_Link_Complete 0x40 struct hciEvtPhysLinkComplete { uint8_t status; uint8_t physLinkHandle; } __packed; -#define HIC_EVT_Channel_Selected 0x41 +#define HIC_EVT_Channel_Selected 0x41 struct hciEvtChannelSelected { uint8_t physLinkHandle; } __packed; -#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42 +#define HCI_EVT_Disconnection_Physical_Link_Complete 0x42 struct hciEvtDiscPhysLinkComplete { uint8_t status; uint8_t physLinkHandle; uint8_t reason; } __packed; -#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43 +#define HCI_EVT_Physical_Link_Loss_Early_Warning 0x43 struct hciEvtDiscPhysLinkLossEralyWarning { uint8_t physLinkHandle; uint8_t lossReason; } __packed; -#define HCI_EVT_Physical_Link_Recovery 0x44 +#define HCI_EVT_Physical_Link_Recovery 0x44 struct hciEvtDiscPhysLinkRecovery { uint8_t physLinkHandle; } __packed; -#define HCI_EVT_Logical_Link_Complete 0x45 +#define HCI_EVT_Logical_Link_Complete 0x45 struct hciEvtLogicalLinkComplete { uint8_t status; uint16_t logicalLinkHandle; @@ -2862,20 +2925,20 @@ struct hciEvtLogicalLinkComplete { uint8_t txFlowSpecID; } __packed; -#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46 +#define HCI_EVT_Disconnection_Logical_Link_Complete 0x46 struct hciEvtDiscLogicalLinkComplete { uint8_t status; uint16_t logicalLinkHandle; uint8_t reason; } __packed; -#define HCI_EVT_Flow_Spec_Modify_Complete 0x47 +#define HCI_EVT_Flow_Spec_Modify_Complete 0x47 struct hciEvtFlowSpecModifyComplete { uint8_t status; uint16_t conn; } __packed; -#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48 +#define HCI_EVT_Number_Of_Completed_Data_Blocks 0x48 struct hciEvtNumCompletedDataBlocksItem { uint16_t conn; uint16_t numPackets; @@ -2886,19 +2949,19 @@ struct hciEvtNumCompletedDataBlocks { struct hciEvtNumCompletedDataBlocksItem items[]; } __packed; -#define HCI_EVT_AMP_Start_Test 0x49 +#define HCI_EVT_AMP_Start_Test 0x49 struct hciEvtAmpStartTest { uint8_t status; uint8_t scenario; } __packed; -#define HCI_EVT_AMP_Test_End 0x4A +#define HCI_EVT_AMP_Test_End 0x4A struct hciEvtAmpTestEnd { uint8_t status; uint8_t scenario; } __packed; -#define HCI_EVT_AMP_Receiver_Report 0x4B +#define HCI_EVT_AMP_Receiver_Report 0x4B struct hciEvtampReceiverReport { uint8_t controllerType; uint8_t reason; @@ -2909,28 +2972,27 @@ struct hciEvtampReceiverReport { uint32_t numberOfErrorBits; } __packed; -#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C +#define HCI_EVT_Short_Range_Mode_Change_Complete 0x4C struct hciEvtshortRangeModeChangeComplete { uint8_t status; uint8_t physLinkHandle; uint8_t shortRangeModeOn; } __packed; -#define HCI_EVT_AMP_Status_Change 0x4D +#define HCI_EVT_AMP_Status_Change 0x4D struct hciEvtAmpStatusChange { uint8_t status; uint8_t ampStatus; } __packed; - /* ==== BT 4.0 ==== */ -#define HCI_EVT_LE_Meta 0x3E +#define HCI_EVT_LE_Meta 0x3E struct hciEvtLeMeta { uint8_t subevent; } __packed; -#define HCI_EVTLE_Connection_Complete 0x01 +#define HCI_EVTLE_Connection_Complete 0x01 struct hciEvtLeConnectionComplete { uint8_t status; uint16_t conn; @@ -2943,21 +3005,23 @@ struct hciEvtLeConnectionComplete { uint8_t masterClockAccuracy; /* HCI_MCA_* */ } __packed; -#define HCI_EVTLE_Advertising_Report 0x02 +#define HCI_EVTLE_Advertising_Report 0x02 struct hciEvtLeAdvReportItem { uint8_t advType; /* HCI_ADV_TYPE_* */ uint8_t randomAddr; uint8_t mac[6]; uint8_t dataLen; uint8_t data[]; -/* int8_t RSSI <-- this cannot be here due to variable data len, but in reality it is there */ + /* int8_t RSSI <-- this cannot be here due to variable data len, but in + * reality it is there */ } __packed; struct hciEvtLeAdvReport { uint8_t numReports; - /* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since data length is variable */ + /* struct hciEvtLeAdvReportItem items[]; <- this cannot be here since + * data length is variable */ } __packed; -#define HCI_EVTLE_Connection_Update_Complete 0x03 +#define HCI_EVTLE_Connection_Update_Complete 0x03 struct hciEvtLeConnectionUpdateComplete { uint8_t status; uint16_t conn; @@ -2966,24 +3030,23 @@ struct hciEvtLeConnectionUpdateComplete { uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */ } __packed; -#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04 +#define HCI_EVTLE_Read_Remote_Used_Features_Complete 0x04 struct hciEvtLeReadRemoteFeaturesComplete { uint8_t status; uint16_t conn; uint64_t leFeatures; /* bitmask of HCI_LE_FTR_* */ } __packed; -#define HCI_EVTLE_LTK_Request 0x05 +#define HCI_EVTLE_LTK_Request 0x05 struct hciEvtLeLtkRequest { uint16_t conn; uint64_t randomNum; uint16_t diversifier; } __packed; - /* ==== BT 4.1 ==== */ -#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06 +#define HCI_EVTLE_Read_Remote_Connection_Parameter_Request 0x06 struct hciEvtLeReadRemoteConnParamRequest { uint16_t conn; uint16_t connIntervalMin; /* in units of 1.25 ms 6..0x0C80 */ @@ -2992,7 +3055,7 @@ struct hciEvtLeReadRemoteConnParamRequest { uint16_t supervisionTimeout; /* inunit sof 10ms, 0xA..0x0C80 */ } __packed; -#define HCI_EVT_Triggered_Clock_Capture 0x4E +#define HCI_EVT_Triggered_Clock_Capture 0x4E struct hciEvtTriggeredClockCapture { uint16_t conn; uint8_t piconetClock; @@ -3000,12 +3063,12 @@ struct hciEvtTriggeredClockCapture { uint16_t slotOffset; } __packed; -#define HCI_EVT_Synchronization_Train_Complete 0x4F +#define HCI_EVT_Synchronization_Train_Complete 0x4F struct hciEvtSyncTrainComplete { uint8_t status; } __packed; -#define HCI_EVT_Synchronization_Train_Received 0x50 +#define HCI_EVT_Synchronization_Train_Received 0x50 struct hciEvtSyncTrainReceived { uint8_t status; uint8_t mac[6]; @@ -3017,7 +3080,7 @@ struct hciEvtSyncTrainReceived { uint8_t serviceData; } __packed; -#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51 +#define HCI_EVT_Connectionless_Slave_Broadcast_Receive 0x51 struct hciEvtConnectionlessSlaveBroadcastReceive { uint8_t mac[6]; uint8_t ltAddr; @@ -3029,127 +3092,116 @@ struct hciEvtConnectionlessSlaveBroadcastReceive { /* data */ } __packed; -#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52 +#define HCI_EVT_Connectionless_Slave_Broadcast_Timeout 0x52 struct hciEvtConnectionlessSlaveBroadcastTimeout { uint8_t mac[6]; uint8_t ltAddr; } __packed; -#define HCI_EVT_Truncated_Page_Complete 0x53 +#define HCI_EVT_Truncated_Page_Complete 0x53 struct hciEvtTruncatedPageComplete { uint8_t status; uint8_t mac[6]; } __packed; -#define HCI_EVT_Slave_Page_Response_Timeout 0x54 +#define HCI_EVT_Slave_Page_Response_Timeout 0x54 -#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55 +#define HCI_EVT_Connless_Slave_Broadcast_Channel_Map_Change 0x55 struct hciEvtConnlessSlaveBroadcastChannelMapChange { uint8_t map[10]; } __packed; -#define HCI_EVT_Inquiry_Response_Notification 0x56 +#define HCI_EVT_Inquiry_Response_Notification 0x56 struct hciEvtInquiryResponseNotif { uint8_t lap[3]; uint8_t RSSI; /* actually an int8_t */ } __packed; -#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57 +#define HCI_EVT_Authenticated_Payload_Timeout_Expired 0x57 struct hciEvtAuthedPayloadTimeoutExpired { uint16_t conn; } __packed; - - - - /* ERROR CODES */ /* ==== BT 1.1 ==== */ -#define HCI_SUCCESS 0x00 -#define HCI_ERR_Unknown_HCI_Command 0x01 -#define HCI_ERR_No_Connection 0x02 -#define HCI_ERR_Hardware_Failure 0x03 -#define HCI_ERR_Page_Timeout 0x04 -#define HCI_ERR_Authentication_Failure 0x05 -#define HCI_ERR_Key_Missing 0x06 -#define HCI_ERR_Memory_Full 0x07 -#define HCI_ERR_Connection_Timeout 0x08 -#define HCI_ERR_Max_Number_Of_Connections 0x09 -#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A -#define HCI_ERR_ACL_Connection_Already_Exists 0x0B -#define HCI_ERR_Command_Disallowed 0x0C -#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D -#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E -#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F -#define HCI_ERR_Host_Timeout 0x10 -#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11 -#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12 -#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13 -#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14 -#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15 -#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16 -#define HCI_ERR_Repeated_Attempts 0x17 -#define HCI_ERR_Pairing_Not_Allowed 0x18 -#define HCI_ERR_Unknown_LMP_PDU 0x19 -#define HCI_ERR_Unsupported_Remote_Feature 0x1A -#define HCI_ERR_SCO_Offset_Rejected 0x1B -#define HCI_ERR_SCO_Interval_Rejected 0x1C -#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D -#define HCI_ERR_Invalid_LMP_Parameters 0x1E -#define HCI_ERR_Unspecified_Error 0x1F -#define HCI_ERR_Unsupported_LMP_Parameter 0x20 -#define HCI_ERR_Role_Change_Not_Allowed 0x21 -#define HCI_ERR_LMP_Response_Timeout 0x22 -#define HCI_ERR_LMP_Error_Transaction_Collision 0x23 -#define HCI_ERR_LMP_PDU_Not_Allowed 0x24 -#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25 -#define HCI_ERR_Unit_Key_Used 0x26 -#define HCI_ERR_QoS_Not_Supported 0x27 -#define HCI_ERR_Instant_Passed 0x28 -#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29 - +#define HCI_SUCCESS 0x00 +#define HCI_ERR_Unknown_HCI_Command 0x01 +#define HCI_ERR_No_Connection 0x02 +#define HCI_ERR_Hardware_Failure 0x03 +#define HCI_ERR_Page_Timeout 0x04 +#define HCI_ERR_Authentication_Failure 0x05 +#define HCI_ERR_Key_Missing 0x06 +#define HCI_ERR_Memory_Full 0x07 +#define HCI_ERR_Connection_Timeout 0x08 +#define HCI_ERR_Max_Number_Of_Connections 0x09 +#define HCI_ERR_Max_Number_Of_SCO_Connections_To_A_Device 0x0A +#define HCI_ERR_ACL_Connection_Already_Exists 0x0B +#define HCI_ERR_Command_Disallowed 0x0C +#define HCI_ERR_Host_Rejected_Due_To_Limited_Resources 0x0D +#define HCI_ERR_Host_Rejected_Due_To_Security_Reasons 0x0E +#define HCI_ERR_Host_Rejected_Remote_Device_Personal_Device 0x0F +#define HCI_ERR_Host_Timeout 0x10 +#define HCI_ERR_Unsupported_Feature_Or_Parameter_Value 0x11 +#define HCI_ERR_Invalid_HCI_Command_Parameters 0x12 +#define HCI_ERR_Other_End_Terminated_Connection_User_Requested 0x13 +#define HCI_ERR_Other_End_Terminated_Connection_Low_Resources 0x14 +#define HCI_ERR_Other_End_Terminated_Connection_Soon_Power_Off 0x15 +#define HCI_ERR_Connection_Terminated_By_Local_Host 0x16 +#define HCI_ERR_Repeated_Attempts 0x17 +#define HCI_ERR_Pairing_Not_Allowed 0x18 +#define HCI_ERR_Unknown_LMP_PDU 0x19 +#define HCI_ERR_Unsupported_Remote_Feature 0x1A +#define HCI_ERR_SCO_Offset_Rejected 0x1B +#define HCI_ERR_SCO_Interval_Rejected 0x1C +#define HCI_ERR_SCO_Air_Mode_Rejected 0x1D +#define HCI_ERR_Invalid_LMP_Parameters 0x1E +#define HCI_ERR_Unspecified_Error 0x1F +#define HCI_ERR_Unsupported_LMP_Parameter 0x20 +#define HCI_ERR_Role_Change_Not_Allowed 0x21 +#define HCI_ERR_LMP_Response_Timeout 0x22 +#define HCI_ERR_LMP_Error_Transaction_Collision 0x23 +#define HCI_ERR_LMP_PDU_Not_Allowed 0x24 +#define HCI_ERR_Encryption_Mode_Not_Acceptable 0x25 +#define HCI_ERR_Unit_Key_Used 0x26 +#define HCI_ERR_QoS_Not_Supported 0x27 +#define HCI_ERR_Instant_Passed 0x28 +#define HCI_ERR_Pairing_With_Unit_Key_Not_Supported 0x29 /* ==== BT 1.2 ==== */ -#define HCI_ERR_Different_Transaction_Collision 0x2A -#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C -#define HCI_ERR_QoS_Rejected 0x2D -#define HCI_ERR_Channel_Classification_Not_Supported 0x2E -#define HCI_ERR_Insufficient_Security 0x2F -#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30 -#define HCI_ERR_Role_Switch_Pending 0x33 -#define HCI_ERR_Reserved_Slot_Violation 0x34 -#define HIC_ERR_Role_Switch_Failed 0x35 - +#define HCI_ERR_Different_Transaction_Collision 0x2A +#define HCI_ERR_QoS_Unacceptable_Parameter 0x2C +#define HCI_ERR_QoS_Rejected 0x2D +#define HCI_ERR_Channel_Classification_Not_Supported 0x2E +#define HCI_ERR_Insufficient_Security 0x2F +#define HCI_ERR_Parameter_Out_Of_Mandatory_Range 0x30 +#define HCI_ERR_Role_Switch_Pending 0x33 +#define HCI_ERR_Reserved_Slot_Violation 0x34 +#define HIC_ERR_Role_Switch_Failed 0x35 /* ==== BT 2.1 ==== */ -#define HCI_ERR_EIR_Too_Large 0x36 -#define HCI_ERR_SSP_Not_Supported_By_Host 0x37 -#define HCI_ERR_Host_Busy_Pairing 0x38 - +#define HCI_ERR_EIR_Too_Large 0x36 +#define HCI_ERR_SSP_Not_Supported_By_Host 0x37 +#define HCI_ERR_Host_Busy_Pairing 0x38 /* ==== BT 3.0 ==== */ -#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39 -#define HCI_ERR_Controller_Busy 0x3A - +#define HCI_ERR_Connection_Rejected_No_Suitable_Channel_Found 0x39 +#define HCI_ERR_Controller_Busy 0x3A /* ==== BT 4.0 ==== */ -#define HCI_ERR_Unacceptable_Connection_Interval 0x3B -#define HCI_ERR_Directed_Advertising_Timeout 0x3C -#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D -#define HCI_ERR_Connection_Failed_To_To_Established 0x3E -#define HCI_ERR_MAC_Connection_Failed 0x3F - +#define HCI_ERR_Unacceptable_Connection_Interval 0x3B +#define HCI_ERR_Directed_Advertising_Timeout 0x3C +#define HCI_ERR_Connection_Terminated_Due_To_MIC_Failure 0x3D +#define HCI_ERR_Connection_Failed_To_To_Established 0x3E +#define HCI_ERR_MAC_Connection_Failed 0x3F /* ==== BT 4.1 ==== */ -#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40 - - +#define HCI_ERR_CoarseClock_AdjFailed_Will_Try_clock_Dragging 0x40 #endif -- cgit v1.2.1 From 5a7b83bd024a7b1be4508e4caaa55e92a7dd4b19 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:30 -0600 Subject: test/battery_get_params_smart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7652e4c2639709a2e9ac85f304839704b9cdd9da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730489 Reviewed-by: Jeremy Bettis --- test/battery_get_params_smart.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/test/battery_get_params_smart.c b/test/battery_get_params_smart.c index 3163fb587e..d60be9a5bc 100644 --- a/test/battery_get_params_smart.c +++ b/test/battery_get_params_smart.c @@ -19,7 +19,6 @@ static int fail_on_first, fail_on_last; static int read_count, write_count; struct batt_params batt; - void battery_compensate_params(struct batt_params *batt) { } @@ -44,17 +43,14 @@ int sb_read(int cmd, int *param) if (read_count >= fail_on_first && read_count <= fail_on_last) return EC_ERROR_UNKNOWN; - return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - cmd, param); + return i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param); } int sb_write(int cmd, int param) { write_count++; - return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - cmd, param); + return i2c_write16(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, cmd, param); } - /* Tests */ static int test_param_failures(void) { -- cgit v1.2.1 From 45e84fed8b6c3e5c2c714d7436ca20b9142fbf53 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:30 -0600 Subject: board/lazor/switchcap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I346500d5edaba085674d4cbcab2ae148edf59782 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728631 Reviewed-by: Jeremy Bettis --- board/lazor/switchcap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lazor/switchcap.c b/board/lazor/switchcap.c index 16f4a54c79..d5c7a0b764 100644 --- a/board/lazor/switchcap.c +++ b/board/lazor/switchcap.c @@ -14,8 +14,8 @@ #include "system.h" #include "sku.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /* LN9310 switchcap */ const struct ln9310_config_t ln9310_config = { -- cgit v1.2.1 From 94531a13837b4258fe767fae80a94fbf56cd3c17 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:04 -0600 Subject: include/eeprom.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e4acbb965a7dc8604cd72d36ccb8a6285765c30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730262 Reviewed-by: Jeremy Bettis --- include/eeprom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/eeprom.h b/include/eeprom.h index 368491c959..384530559f 100644 --- a/include/eeprom.h +++ b/include/eeprom.h @@ -52,4 +52,4 @@ int eeprom_write(int block, int offset, int size, const char *data); */ int eeprom_hide(int block); -#endif /* __CROS_EC_EEPROM_H */ +#endif /* __CROS_EC_EEPROM_H */ -- cgit v1.2.1 From c063c01d244c16d778d69ad7f0121f6adac8f3c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:47 -0600 Subject: test/cec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic648693e14d346ae37cca6f0eb1341a592e96a54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730493 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/cec.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/test/cec.c b/test/cec.c index 9377e4fcd3..28464dfab0 100644 --- a/test/cec.c +++ b/test/cec.c @@ -18,7 +18,6 @@ struct overflow_msg { BUILD_ASSERT(offsetof(struct overflow_msg, overflow_detector) == offsetof(struct cec_msg_transfer, buf) + MAX_CEC_MSG_LEN); - struct overflow_queue { struct cec_rx_queue queue; uint8_t overflow_detector[CEC_RX_BUFFER_SIZE]; @@ -35,7 +34,7 @@ static int test_msg_overflow(void) int i; /* Overwrite the buffer by 1 byte */ - for (i = 0; i < (MAX_CEC_MSG_LEN+1)*8; i++) { + for (i = 0; i < (MAX_CEC_MSG_LEN + 1) * 8; i++) { cec_transfer_set_bit(&overflow_msg.transfer, 1); cec_transfer_inc_bit(&overflow_msg.transfer); } @@ -60,8 +59,6 @@ static int test_msg_overflow(void) return EC_SUCCESS; } - - static int verify_no_queue_overflow(void) { int i; @@ -73,11 +70,9 @@ static int verify_no_queue_overflow(void) return EC_SUCCESS; } - static void clear_queue(void) { memset(queue, 0, sizeof(struct cec_rx_queue)); - } static int fill_queue(uint8_t *msg, int msg_size) @@ -92,12 +87,12 @@ static int fill_queue(uint8_t *msg, int msg_size) */ clear_queue(); - for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1)/(msg_size + 1); i++) + for (i = 0; i < (CEC_RX_BUFFER_SIZE - 1) / (msg_size + 1); i++) TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) == 0); /* Now the queue should be full */ TEST_ASSERT(cec_rx_queue_push(queue, msg, msg_size) == - EC_ERROR_OVERFLOW); + EC_ERROR_OVERFLOW); /* Verify nothing was written outside of the queue */ TEST_ASSERT(verify_no_queue_overflow() == EC_SUCCESS); -- cgit v1.2.1 From 3f32f1b98f4de432fdacc752fbb2383505b0f173 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:09 -0600 Subject: driver/wpc/cps8100.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b2e94589913ae4c98be1861defbce7d1e993849 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730175 Reviewed-by: Jeremy Bettis --- driver/wpc/cps8100.c | 99 ++++++++++++++++++++++++---------------------------- 1 file changed, 45 insertions(+), 54 deletions(-) diff --git a/driver/wpc/cps8100.c b/driver/wpc/cps8100.c index 78aa73fbfd..ffb81e3a91 100644 --- a/driver/wpc/cps8100.c +++ b/driver/wpc/cps8100.c @@ -18,49 +18,49 @@ /* Print additional data */ #define CPS8100_DEBUG -#define CPUTS(outstr) cputs(CC_PCHG, outstr) -#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CPS8100: " fmt, ##args) -#define CPRINTFP(fmt, args...) cprintf(CC_PCHG, "CPS8100: " fmt, ##args) -#define CPRINTF(fmt, args...) cprintf(CC_PCHG, fmt, ##args) +#define CPUTS(outstr) cputs(CC_PCHG, outstr) +#define CPRINTS(fmt, args...) cprints(CC_PCHG, "CPS8100: " fmt, ##args) +#define CPRINTFP(fmt, args...) cprintf(CC_PCHG, "CPS8100: " fmt, ##args) +#define CPRINTF(fmt, args...) cprintf(CC_PCHG, fmt, ##args) /* * Configuration */ -#define CPS8100_I2C_ADDR_H 0x31 -#define CPS8100_I2C_ADDR_L 0x30 +#define CPS8100_I2C_ADDR_H 0x31 +#define CPS8100_I2C_ADDR_L 0x30 /* High address registers (commands?) */ -#define CPS8100_REGH_PASSWORD 0xf500 -#define CPS8100_REGH_ACCESS_MODE 0xf505 -#define CPS8100_REGH_ADDRESS 0xf503 +#define CPS8100_REGH_PASSWORD 0xf500 +#define CPS8100_REGH_ACCESS_MODE 0xf505 +#define CPS8100_REGH_ADDRESS 0xf503 -#define CPS8100_ACCESS_MODE_8 0x00 -#define CPS8100_ACCESS_MODE_16 0x01 -#define CPS8100_ACCESS_MODE_32 0x02 +#define CPS8100_ACCESS_MODE_8 0x00 +#define CPS8100_ACCESS_MODE_16 0x01 +#define CPS8100_ACCESS_MODE_32 0x02 /* Registers */ -#define CPS8100_REG_IC_INFO 0x20000000 -#define CPS8100_REG_FW_INFO 0x20000004 -#define CPS8100_REG_FUNC_EN 0x2000003c -#define CPS8100_REG_ALERT_INFO 0x20000158 -#define CPS8100_REG_INT_ENABLE 0x20000160 -#define CPS8100_REG_INT_FLAG 0x20000164 - -#define CPS8100_STATUS_PROFILE(r) (((r) & GENMASK(5, 4)) >> 4) -#define CPS8100_STATUS_CHARGE(r) ((r) & BIT(6)) -#define CPS8100_STATUS_DEVICE(r) ((r) & BIT(7)) -#define CPS8100_STATUS_BATTERY(r) (((r) & GENMASK(15, 8)) >> 8) -#define CPS8100_IRQ_TYPE(r) (((r) & GENMASK(23, 20)) >> 20) +#define CPS8100_REG_IC_INFO 0x20000000 +#define CPS8100_REG_FW_INFO 0x20000004 +#define CPS8100_REG_FUNC_EN 0x2000003c +#define CPS8100_REG_ALERT_INFO 0x20000158 +#define CPS8100_REG_INT_ENABLE 0x20000160 +#define CPS8100_REG_INT_FLAG 0x20000164 + +#define CPS8100_STATUS_PROFILE(r) (((r)&GENMASK(5, 4)) >> 4) +#define CPS8100_STATUS_CHARGE(r) ((r)&BIT(6)) +#define CPS8100_STATUS_DEVICE(r) ((r)&BIT(7)) +#define CPS8100_STATUS_BATTERY(r) (((r)&GENMASK(15, 8)) >> 8) +#define CPS8100_IRQ_TYPE(r) (((r)&GENMASK(23, 20)) >> 20) /* Status flags in ALERT_INFO register */ -#define CPS8100_STATUS_FOD BIT(0) -#define CPS8100_STATUS_OCP BIT(1) -#define CPS8100_STATUS_OVP BIT(2) -#define CPS8100_STATUS_OTP BIT(3) -#define CPS8100_STATUS_UVP BIT(16) +#define CPS8100_STATUS_FOD BIT(0) +#define CPS8100_STATUS_OCP BIT(1) +#define CPS8100_STATUS_OVP BIT(2) +#define CPS8100_STATUS_OTP BIT(3) +#define CPS8100_STATUS_UVP BIT(16) /* Buffer size for i2c read & write */ -#define CPS8100_MESSAGE_BUFFER_SIZE 0x20 +#define CPS8100_MESSAGE_BUFFER_SIZE 0x20 /* TODO: Check datasheet how to wake up and how long it takes to wake up. */ static const int cps8100_wake_up_delay_ms = 10; @@ -82,21 +82,12 @@ struct cps8100_msg { } __packed; /* This driver isn't compatible with big endian. */ -BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__); - -static const char * const cps8100_func_names[] = { - [0] = "DPL", - [1] = "OPP", - [2] = "OTP", - [3] = "OVPK", - [4] = "OCP", - [5] = "UVP", - [6] = "OVP", - [7] = "FOD", - [8] = "SAMSUNG", - [9] = "APPLE", - [10] = "EPP", - [11] = "HUAWEI", +BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__); + +static const char *const cps8100_func_names[] = { + [0] = "DPL", [1] = "OPP", [2] = "OTP", [3] = "OVPK", + [4] = "OCP", [5] = "UVP", [6] = "OVP", [7] = "FOD", + [8] = "SAMSUNG", [9] = "APPLE", [10] = "EPP", [11] = "HUAWEI", [12] = "CPS", }; @@ -114,7 +105,7 @@ enum cps8100_irq_type { CPS8100_IRQ_TYPE_COUNT }; -static const char * const cps8100_irq_type_names[] = { +static const char *const cps8100_irq_type_names[] = { [CPS8100_IRQ_TYPE_FOD] = "FOD", [CPS8100_IRQ_TYPE_OCP] = "OCP", [CPS8100_IRQ_TYPE_OVP] = "OVP", @@ -127,7 +118,7 @@ static const char * const cps8100_irq_type_names[] = { [CPS8100_IRQ_TYPE_RESET] = "RESET", }; -static const char * const cps8100_profile_names[] = { +static const char *const cps8100_profile_names[] = { [0] = "NONE", [1] = "BPP", [2] = "EPP", @@ -214,9 +205,9 @@ static int cps8100_set_unlock(int port) uint8_t buf[4]; buf[0] = 0xf5; - buf[1] = 0x00; /* Password register address */ + buf[1] = 0x00; /* Password register address */ buf[2] = 0xe5; - buf[3] = 0x19; /* Password */ + buf[3] = 0x19; /* Password */ return cps8100_i2c_write(port, CPS8100_I2C_ADDR_H, buf, 4); } @@ -258,8 +249,8 @@ static int cps8100_read32(int port, uint32_t reg, uint32_t *val) buf[0] = (reg >> 8) & 0xff; buf[1] = (reg >> 0) & 0xff; - return i2c_xfer(port, CPS8100_I2C_ADDR_L, buf, 2, - (void *)val, sizeof(*val)); + return i2c_xfer(port, CPS8100_I2C_ADDR_L, buf, 2, (void *)val, + sizeof(*val)); } static int cps8100_reset(struct pchg *ctx) @@ -315,7 +306,8 @@ static void cps8100_print_alert_info(uint32_t reg) CPRINTFP("Profile: %s\n", cps8100_profile_names[CPS8100_STATUS_PROFILE(reg)]); CPRINTFP("%sCharging\n", CPS8100_STATUS_CHARGE(reg) ? "" : "Not "); - CPRINTFP("Device %sPresent\n", CPS8100_STATUS_DEVICE(reg) ? "":"Not "); + CPRINTFP("Device %sPresent\n", + CPS8100_STATUS_DEVICE(reg) ? "" : "Not "); CPRINTFP("Battery: %d%%\n", CPS8100_STATUS_BATTERY(reg)); } @@ -436,6 +428,5 @@ static int cc_cps8100(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(cps8100, cc_cps8100, - " [reset]", +DECLARE_CONSOLE_COMMAND(cps8100, cc_cps8100, " [reset]", "Print status of or reset CPS8100"); -- cgit v1.2.1 From 6eb343c1506296938ab41bd20f4b84e105299a3b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:24 -0600 Subject: board/beetley/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f2faaab68be035036d8d4532c53b823ef93f578 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728047 Reviewed-by: Jeremy Bettis --- board/beetley/board.c | 99 +++++++++++++++++++++------------------------------ 1 file changed, 41 insertions(+), 58 deletions(-) diff --git a/board/beetley/board.c b/board/beetley/board.c index 0e6c88b24b..2cf45faf93 100644 --- a/board/beetley/board.c +++ b/board/beetley/board.c @@ -43,7 +43,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 __override struct keyboard_scan_config keyscan_config = { @@ -100,7 +100,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -114,34 +113,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -203,27 +194,23 @@ static const struct ec_response_keybd_config beetley_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &beetley_keybd; } /* USB-A charging control */ -const int usb_port_enable[USB_PORT_COUNT] = { - GPIO_EN_USB_A0_VBUS -}; +const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_VBUS }; /* Sensors */ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t base_lsm6dsm_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_lsm6dsm_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; @@ -331,7 +318,6 @@ void board_init(void) keyscan_config.actual_key_mask[12] = 0xff; keyscan_config.actual_key_mask[13] = 0xff; keyscan_config.actual_key_mask[14] = 0xff; - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -422,7 +408,6 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) @@ -434,8 +419,7 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); raa489000_enable_asgate(0, false); return EC_SUCCESS; } @@ -448,8 +432,7 @@ int board_set_active_charge_port(int port) /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { CPRINTUSB("p%d: sink path enable failed.", port); return EC_ERROR_UNKNOWN; } @@ -481,18 +464,18 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charge", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "5V_Inductor", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charge", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "5V_Inductor", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 3f5f9632cbcc8f1352a6e74dfd8b160b01bc2c8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:06 -0600 Subject: board/lantis/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I66d969a9fe3dc8bba93afe4385bb17cfca64b40f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728614 Reviewed-by: Jeremy Bettis --- board/lantis/board.c | 183 +++++++++++++++++++++++---------------------------- 1 file changed, 83 insertions(+), 100 deletions(-) diff --git a/board/lantis/board.c b/board/lantis/board.c index f8c8b2e477..b7e670d11d 100644 --- a/board/lantis/board.c +++ b/board/lantis/board.c @@ -46,7 +46,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -183,48 +183,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -299,17 +287,13 @@ static struct accelgyro_saved_data_t g_bma422_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -497,8 +481,8 @@ static const struct ec_response_keybd_config landrid_keybd = { /* No function keys and no screenlock key */ }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_cbi_fw_config_numeric_pad()) { if (get_cbi_fw_config_kblight()) @@ -513,8 +497,7 @@ __override const struct ec_response_keybd_config } } -__override -uint8_t board_keyboard_row_refresh(void) +__override uint8_t board_keyboard_row_refresh(void) { if (gpio_get_level(GPIO_EC_VIVALDIKEYBOARD_ID)) return 3; @@ -674,8 +657,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -683,11 +666,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -698,11 +681,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -804,33 +787,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -860,9 +841,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -881,14 +861,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 140dac75cbd85a619e340cb22c46d7c73abe0276 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:39 -0600 Subject: common/audio_codec_i2s_rx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idec6acf070da46307065dae3d873cc0675f59c06 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729586 Reviewed-by: Jeremy Bettis --- common/audio_codec_i2s_rx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/audio_codec_i2s_rx.c b/common/audio_codec_i2s_rx.c index aeae19bdca..9c5b3ba03a 100644 --- a/common/audio_codec_i2s_rx.c +++ b/common/audio_codec_i2s_rx.c @@ -8,7 +8,7 @@ #include "console.h" #include "host_command.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) static uint8_t i2s_rx_enabled; @@ -128,5 +128,5 @@ static enum ec_status i2s_rx_host_command(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; } -DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX, - i2s_rx_host_command, EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_EC_CODEC_I2S_RX, i2s_rx_host_command, + EC_VER_MASK(0)); -- cgit v1.2.1 From 39b8f62babca576fad412bbe6a22e8220f59f064 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:59 -0600 Subject: board/moli/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c459f4a86c69ffc27395c3adb55edad24a08c9e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728690 Reviewed-by: Jeremy Bettis --- board/moli/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/moli/fans.c b/board/moli/fans.c index f2a70636d0..62492fe063 100644 --- a/board/moli/fans.c +++ b/board/moli/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 2847a87a3d6c875b2d3f1ade5ba6509c4c46e484 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:05 -0600 Subject: chip/mchp/registers-mec152x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3d66df7899d168ac9be75494b4d661b86657e541 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729298 Reviewed-by: Jeremy Bettis --- chip/mchp/registers-mec152x.h | 1697 ++++++++++++++++++++--------------------- 1 file changed, 838 insertions(+), 859 deletions(-) diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h index 10021ede8b..ee8e7043d1 100644 --- a/chip/mchp/registers-mec152x.h +++ b/chip/mchp/registers-mec152x.h @@ -14,196 +14,196 @@ * NOTE: GIRQ22 aggregated output and its sources are not connected to * the NVIC. */ -#define MCHP_IRQ_GIRQ8 0 -#define MCHP_IRQ_GIRQ9 1 -#define MCHP_IRQ_GIRQ10 2 -#define MCHP_IRQ_GIRQ11 3 -#define MCHP_IRQ_GIRQ12 4 -#define MCHP_IRQ_GIRQ13 5 -#define MCHP_IRQ_GIRQ14 6 -#define MCHP_IRQ_GIRQ15 7 -#define MCHP_IRQ_GIRQ16 8 -#define MCHP_IRQ_GIRQ17 9 -#define MCHP_IRQ_GIRQ18 10 -#define MCHP_IRQ_GIRQ19 11 -#define MCHP_IRQ_GIRQ20 12 -#define MCHP_IRQ_GIRQ21 13 -#define MCHP_IRQ_GIRQ23 14 -#define MCHP_IRQ_GIRQ24 15 -#define MCHP_IRQ_GIRQ25 16 -#define MCHP_IRQ_GIRQ26 17 +#define MCHP_IRQ_GIRQ8 0 +#define MCHP_IRQ_GIRQ9 1 +#define MCHP_IRQ_GIRQ10 2 +#define MCHP_IRQ_GIRQ11 3 +#define MCHP_IRQ_GIRQ12 4 +#define MCHP_IRQ_GIRQ13 5 +#define MCHP_IRQ_GIRQ14 6 +#define MCHP_IRQ_GIRQ15 7 +#define MCHP_IRQ_GIRQ16 8 +#define MCHP_IRQ_GIRQ17 9 +#define MCHP_IRQ_GIRQ18 10 +#define MCHP_IRQ_GIRQ19 11 +#define MCHP_IRQ_GIRQ20 12 +#define MCHP_IRQ_GIRQ21 13 +#define MCHP_IRQ_GIRQ23 14 +#define MCHP_IRQ_GIRQ24 15 +#define MCHP_IRQ_GIRQ25 16 +#define MCHP_IRQ_GIRQ26 17 /* GIRQ13 direct sources */ -#define MCHP_IRQ_I2C_0 20 -#define MCHP_IRQ_I2C_1 21 -#define MCHP_IRQ_I2C_2 22 -#define MCHP_IRQ_I2C_3 23 -#define MCHP_IRQ_I2C_4 158 -#define MCHP_IRQ_I2C_5 168 -#define MCHP_IRQ_I2C_6 169 -#define MCHP_IRQ_I2C_7 170 +#define MCHP_IRQ_I2C_0 20 +#define MCHP_IRQ_I2C_1 21 +#define MCHP_IRQ_I2C_2 22 +#define MCHP_IRQ_I2C_3 23 +#define MCHP_IRQ_I2C_4 158 +#define MCHP_IRQ_I2C_5 168 +#define MCHP_IRQ_I2C_6 169 +#define MCHP_IRQ_I2C_7 170 /* GIRQ14 direct sources */ -#define MCHP_IRQ_DMA_0 24 -#define MCHP_IRQ_DMA_1 25 -#define MCHP_IRQ_DMA_2 26 -#define MCHP_IRQ_DMA_3 27 -#define MCHP_IRQ_DMA_4 28 -#define MCHP_IRQ_DMA_5 29 -#define MCHP_IRQ_DMA_6 30 -#define MCHP_IRQ_DMA_7 31 -#define MCHP_IRQ_DMA_8 32 -#define MCHP_IRQ_DMA_9 33 -#define MCHP_IRQ_DMA_10 34 -#define MCHP_IRQ_DMA_11 35 +#define MCHP_IRQ_DMA_0 24 +#define MCHP_IRQ_DMA_1 25 +#define MCHP_IRQ_DMA_2 26 +#define MCHP_IRQ_DMA_3 27 +#define MCHP_IRQ_DMA_4 28 +#define MCHP_IRQ_DMA_5 29 +#define MCHP_IRQ_DMA_6 30 +#define MCHP_IRQ_DMA_7 31 +#define MCHP_IRQ_DMA_8 32 +#define MCHP_IRQ_DMA_9 33 +#define MCHP_IRQ_DMA_10 34 +#define MCHP_IRQ_DMA_11 35 /* GIRQ15 direct sources */ -#define MCHP_IRQ_UART0 40 -#define MCHP_IRQ_UART1 41 -#define MCHP_IRQ_EMI0 42 -#define MCHP_IRQ_EMI1 43 -#define MCHP_IRQ_UART2 44 -#define MCHP_IRQ_ACPIEC0_IBF 45 -#define MCHP_IRQ_ACPIEC0_OBE 46 -#define MCHP_IRQ_ACPIEC1_IBF 47 -#define MCHP_IRQ_ACPIEC1_OBE 48 -#define MCHP_IRQ_ACPIEC2_IBF 49 -#define MCHP_IRQ_ACPIEC2_OBE 50 -#define MCHP_IRQ_ACPIEC3_IBF 51 -#define MCHP_IRQ_ACPIEC3_OBE 52 -#define MCHP_IRQ_ACPIPM1_CTL 55 -#define MCHP_IRQ_ACPIPM1_EN 56 -#define MCHP_IRQ_ACPIPM1_STS 57 -#define MCHP_IRQ_8042EM_OBE 58 -#define MCHP_IRQ_8042EM_IBF 59 -#define MCHP_IRQ_MAILBOX_DATA 60 -#define MCHP_IRQ_PORT80DBG0 62 -#define MCHP_IRQ_PORT80DBG1 63 -#define MCHP_IRQ_LASIC 64 +#define MCHP_IRQ_UART0 40 +#define MCHP_IRQ_UART1 41 +#define MCHP_IRQ_EMI0 42 +#define MCHP_IRQ_EMI1 43 +#define MCHP_IRQ_UART2 44 +#define MCHP_IRQ_ACPIEC0_IBF 45 +#define MCHP_IRQ_ACPIEC0_OBE 46 +#define MCHP_IRQ_ACPIEC1_IBF 47 +#define MCHP_IRQ_ACPIEC1_OBE 48 +#define MCHP_IRQ_ACPIEC2_IBF 49 +#define MCHP_IRQ_ACPIEC2_OBE 50 +#define MCHP_IRQ_ACPIEC3_IBF 51 +#define MCHP_IRQ_ACPIEC3_OBE 52 +#define MCHP_IRQ_ACPIPM1_CTL 55 +#define MCHP_IRQ_ACPIPM1_EN 56 +#define MCHP_IRQ_ACPIPM1_STS 57 +#define MCHP_IRQ_8042EM_OBE 58 +#define MCHP_IRQ_8042EM_IBF 59 +#define MCHP_IRQ_MAILBOX_DATA 60 +#define MCHP_IRQ_PORT80DBG0 62 +#define MCHP_IRQ_PORT80DBG1 63 +#define MCHP_IRQ_LASIC 64 /* GIRQ16 direct sources */ -#define MCHP_IRQ_PKE_ERR 65 -#define MCHP_IRQ_PKE_END 66 -#define MCHP_IRQ_NDRNG 67 -#define MCHP_IRQ_AES 68 -#define MCHP_IRQ_HASH 69 +#define MCHP_IRQ_PKE_ERR 65 +#define MCHP_IRQ_PKE_END 66 +#define MCHP_IRQ_NDRNG 67 +#define MCHP_IRQ_AES 68 +#define MCHP_IRQ_HASH 69 /* GIRQ17 direct sources */ -#define MCHP_IRQ_PECI_HOST 70 -#define MCHP_IRQ_TACH_0 71 -#define MCHP_IRQ_TACH_1 72 -#define MCHP_IRQ_TACH_2 73 -#define MCHP_IRQ_TACH_3 159 -#define MCHP_IRQ_HDMI_CEC 160 -#define MCHP_IRQ_ADC_SNGL 78 -#define MCHP_IRQ_ADC_RPT 79 -#define MCHP_IRQ_LED0_WDT 83 -#define MCHP_IRQ_LED1_WDT 84 -#define MCHP_IRQ_LED2_WDT 85 -#define MCHP_IRQ_PROCHOT 87 +#define MCHP_IRQ_PECI_HOST 70 +#define MCHP_IRQ_TACH_0 71 +#define MCHP_IRQ_TACH_1 72 +#define MCHP_IRQ_TACH_2 73 +#define MCHP_IRQ_TACH_3 159 +#define MCHP_IRQ_HDMI_CEC 160 +#define MCHP_IRQ_ADC_SNGL 78 +#define MCHP_IRQ_ADC_RPT 79 +#define MCHP_IRQ_LED0_WDT 83 +#define MCHP_IRQ_LED1_WDT 84 +#define MCHP_IRQ_LED2_WDT 85 +#define MCHP_IRQ_PROCHOT 87 /* GIRQ18 direct sources */ -#define MCHP_IRQ_SLAVE_SPI 90 -#define MCHP_IRQ_QMSPI0 91 -#define MCHP_IRQ_PS2_0 100 -#define MCHP_IRQ_PS2_1 101 -#define MCHP_IRQ_PSPI 155 -#define MCHP_IRQ_SGPIO_0 161 -#define MCHP_IRQ_SGPIO_1 162 -#define MCHP_IRQ_SGPIO_2 163 -#define MCHP_IRQ_SGPIO_3 164 -#define MCHP_IRQ_CCT_TMR 146 -#define MCHP_IRQ_CCT_CAP0 147 -#define MCHP_IRQ_CCT_CAP1 148 -#define MCHP_IRQ_CCT_CAP2 149 -#define MCHP_IRQ_CCT_CAP3 150 -#define MCHP_IRQ_CCT_CAP4 151 -#define MCHP_IRQ_CCT_CAP5 152 -#define MCHP_IRQ_CCT_CMP0 153 -#define MCHP_IRQ_CCT_CMP1 154 +#define MCHP_IRQ_SLAVE_SPI 90 +#define MCHP_IRQ_QMSPI0 91 +#define MCHP_IRQ_PS2_0 100 +#define MCHP_IRQ_PS2_1 101 +#define MCHP_IRQ_PSPI 155 +#define MCHP_IRQ_SGPIO_0 161 +#define MCHP_IRQ_SGPIO_1 162 +#define MCHP_IRQ_SGPIO_2 163 +#define MCHP_IRQ_SGPIO_3 164 +#define MCHP_IRQ_CCT_TMR 146 +#define MCHP_IRQ_CCT_CAP0 147 +#define MCHP_IRQ_CCT_CAP1 148 +#define MCHP_IRQ_CCT_CAP2 149 +#define MCHP_IRQ_CCT_CAP3 150 +#define MCHP_IRQ_CCT_CAP4 151 +#define MCHP_IRQ_CCT_CAP5 152 +#define MCHP_IRQ_CCT_CMP0 153 +#define MCHP_IRQ_CCT_CMP1 154 /* GIRQ19 direct sources */ -#define MCHP_IRQ_ESPI_PC 103 -#define MCHP_IRQ_ESPI_BM1 104 -#define MCHP_IRQ_ESPI_BM2 105 -#define MCHP_IRQ_ESPI_LTR 106 -#define MCHP_IRQ_ESPI_OOB_UP 107 -#define MCHP_IRQ_ESPI_OOB_DN 108 -#define MCHP_IRQ_ESPI_FC 109 -#define MCHP_IRQ_ESPI_RESET 110 -#define MCHP_IRQ_ESPI_VW_EN 156 +#define MCHP_IRQ_ESPI_PC 103 +#define MCHP_IRQ_ESPI_BM1 104 +#define MCHP_IRQ_ESPI_BM2 105 +#define MCHP_IRQ_ESPI_LTR 106 +#define MCHP_IRQ_ESPI_OOB_UP 107 +#define MCHP_IRQ_ESPI_OOB_DN 108 +#define MCHP_IRQ_ESPI_FC 109 +#define MCHP_IRQ_ESPI_RESET 110 +#define MCHP_IRQ_ESPI_VW_EN 156 /* GIRQ20 direct sources */ -#define MCHP_IRQ_OTP 173 +#define MCHP_IRQ_OTP 173 /* GIRQ21 direct sources */ -#define MCHP_IRQ_WDG 171 -#define MCHP_IRQ_WEEK_ALARM 114 -#define MCHP_IRQ_SUBWEEK 115 -#define MCHP_IRQ_WEEK_SEC 116 -#define MCHP_IRQ_WEEK_SUBSEC 117 -#define MCHP_IRQ_WEEK_SYSPWR 118 -#define MCHP_IRQ_RTC 119 -#define MCHP_IRQ_RTC_ALARM 120 -#define MCHP_IRQ_VCI_OVRD_IN 121 -#define MCHP_IRQ_VCI_IN0 122 -#define MCHP_IRQ_VCI_IN1 123 -#define MCHP_IRQ_VCI_IN2 124 -#define MCHP_IRQ_VCI_IN3 125 -#define MCHP_IRQ_PS20A_WAKE 129 -#define MCHP_IRQ_PS20B_WAKE 130 -#define MCHP_IRQ_PS21B_WAKE 132 -#define MCHP_IRQ_KSC_INT 135 +#define MCHP_IRQ_WDG 171 +#define MCHP_IRQ_WEEK_ALARM 114 +#define MCHP_IRQ_SUBWEEK 115 +#define MCHP_IRQ_WEEK_SEC 116 +#define MCHP_IRQ_WEEK_SUBSEC 117 +#define MCHP_IRQ_WEEK_SYSPWR 118 +#define MCHP_IRQ_RTC 119 +#define MCHP_IRQ_RTC_ALARM 120 +#define MCHP_IRQ_VCI_OVRD_IN 121 +#define MCHP_IRQ_VCI_IN0 122 +#define MCHP_IRQ_VCI_IN1 123 +#define MCHP_IRQ_VCI_IN2 124 +#define MCHP_IRQ_VCI_IN3 125 +#define MCHP_IRQ_PS20A_WAKE 129 +#define MCHP_IRQ_PS20B_WAKE 130 +#define MCHP_IRQ_PS21B_WAKE 132 +#define MCHP_IRQ_KSC_INT 135 /* GIRQ23 direct sources */ -#define MCHP_IRQ_TIMER16_0 136 -#define MCHP_IRQ_TIMER16_1 137 -#define MCHP_IRQ_TIMER32_0 140 -#define MCHP_IRQ_TIMER32_1 141 -#define MCHP_IRQ_RTOS_TIMER 111 -#define MCHP_IRQ_HTIMER0 112 -#define MCHP_IRQ_HTIMER1 113 +#define MCHP_IRQ_TIMER16_0 136 +#define MCHP_IRQ_TIMER16_1 137 +#define MCHP_IRQ_TIMER32_0 140 +#define MCHP_IRQ_TIMER32_1 141 +#define MCHP_IRQ_RTOS_TIMER 111 +#define MCHP_IRQ_HTIMER0 112 +#define MCHP_IRQ_HTIMER1 113 /* Must match CONFIG_IRQ_COUNT in config_chip.h */ -#define MCHP_IRQ_MAX 174 +#define MCHP_IRQ_MAX 174 /* Block base addresses */ -#define MCHP_WDG_BASE 0x40000400 -#define MCHP_TMR16_0_BASE 0x40000c00 -#define MCHP_TMR32_0_BASE 0x40000c80 -#define MCHP_DMA_BASE 0x40002400 -#define MCHP_PROCHOT_BASE 0x40003400 -#define MCHP_I2C0_BASE 0x40004000 -#define MCHP_I2C1_BASE 0x40004400 -#define MCHP_I2C2_BASE 0x40004800 -#define MCHP_I2C3_BASE 0x40004C00 -#define MCHP_I2C4_BASE 0x40005000 -#define MCHP_I2C5_BASE 0x40005100 -#define MCHP_I2C6_BASE 0x40005200 -#define MCHP_I2C7_BASE 0x40005300 -#define MCHP_QMSPI0_BASE 0x40070000 -#define MCHP_PWM_0_BASE 0x40005800 -#define MCHP_TACH_0_BASE 0x40006000 -#define MCHP_PECI_BASE 0x40006400 -#define MCHP_RTMR_BASE 0x40007400 -#define MCHP_ADC_BASE 0x40007c00 -#define MCHP_TFDP_BASE 0x40008c00 -#define MCHP_HTIMER_BASE 0x40009800 -#define MCHP_KEYSCAN_BASE 0x40009c00 -#define MCHP_VBAT_BASE 0x4000a400 -#define MCHP_VBAT_RAM_BASE 0x4000a800 -#define MCHP_WKTIMER_BASE 0x4000ac80 -#define MCHP_BBLED_0_BASE 0x4000B800 -#define MCHP_INT_BASE 0x4000e000 -#define MCHP_EC_BASE 0x4000fc00 - -#define MCHP_PCR_BASE 0x40080100 -#define MCHP_GPIO_BASE 0x40081000 - -#define MCHP_MBOX_BASE 0x400f0000 -#define MCHP_8042_BASE 0x400f0400 -#define MCHP_ACPI_EC_0_BASE 0x400f0800 -#define MCHP_ACPI_PM1_BASE 0x400f1c00 -#define MCHP_UART0_BASE 0x400f2400 -#define MCHP_UART1_BASE 0x400f2800 -#define MCHP_UART2_BASE 0x400f2c00 -#define MCHP_ESPI_IO_BASE 0x400f3400 -#define MCHP_ESPI_MEM_BASE 0x400f3800 -#define MCHP_EMI_0_BASE 0x400f4000 -#define MCHP_EMI_1_BASE 0x400f4400 -#define MCHP_P80CAP0_BASE 0x400f8000 -#define MCHP_P80CAP1_BASE 0x400f8400 -#define MCHP_ESPI_VW_BASE 0x400f9c00 -#define MCHP_CHIP_BASE 0x400fff00 +#define MCHP_WDG_BASE 0x40000400 +#define MCHP_TMR16_0_BASE 0x40000c00 +#define MCHP_TMR32_0_BASE 0x40000c80 +#define MCHP_DMA_BASE 0x40002400 +#define MCHP_PROCHOT_BASE 0x40003400 +#define MCHP_I2C0_BASE 0x40004000 +#define MCHP_I2C1_BASE 0x40004400 +#define MCHP_I2C2_BASE 0x40004800 +#define MCHP_I2C3_BASE 0x40004C00 +#define MCHP_I2C4_BASE 0x40005000 +#define MCHP_I2C5_BASE 0x40005100 +#define MCHP_I2C6_BASE 0x40005200 +#define MCHP_I2C7_BASE 0x40005300 +#define MCHP_QMSPI0_BASE 0x40070000 +#define MCHP_PWM_0_BASE 0x40005800 +#define MCHP_TACH_0_BASE 0x40006000 +#define MCHP_PECI_BASE 0x40006400 +#define MCHP_RTMR_BASE 0x40007400 +#define MCHP_ADC_BASE 0x40007c00 +#define MCHP_TFDP_BASE 0x40008c00 +#define MCHP_HTIMER_BASE 0x40009800 +#define MCHP_KEYSCAN_BASE 0x40009c00 +#define MCHP_VBAT_BASE 0x4000a400 +#define MCHP_VBAT_RAM_BASE 0x4000a800 +#define MCHP_WKTIMER_BASE 0x4000ac80 +#define MCHP_BBLED_0_BASE 0x4000B800 +#define MCHP_INT_BASE 0x4000e000 +#define MCHP_EC_BASE 0x4000fc00 + +#define MCHP_PCR_BASE 0x40080100 +#define MCHP_GPIO_BASE 0x40081000 + +#define MCHP_MBOX_BASE 0x400f0000 +#define MCHP_8042_BASE 0x400f0400 +#define MCHP_ACPI_EC_0_BASE 0x400f0800 +#define MCHP_ACPI_PM1_BASE 0x400f1c00 +#define MCHP_UART0_BASE 0x400f2400 +#define MCHP_UART1_BASE 0x400f2800 +#define MCHP_UART2_BASE 0x400f2c00 +#define MCHP_ESPI_IO_BASE 0x400f3400 +#define MCHP_ESPI_MEM_BASE 0x400f3800 +#define MCHP_EMI_0_BASE 0x400f4000 +#define MCHP_EMI_1_BASE 0x400f4400 +#define MCHP_P80CAP0_BASE 0x400f8000 +#define MCHP_P80CAP1_BASE 0x400f8400 +#define MCHP_ESPI_VW_BASE 0x400f9c00 +#define MCHP_CHIP_BASE 0x400fff00 #ifndef __ASSEMBLER__ @@ -213,35 +213,34 @@ * Cortex-M4 bit-banding does require aliasing of the * DATA SRAM region. */ -#define MCHP_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) +#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x)) /* EC Chip Configuration */ /* 16-bit Device ID */ -#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E) +#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E) /* 8-bit Device Sub ID */ -#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D) +#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D) /* 8-bit Device Revision */ -#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C) +#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C) /* All in one */ -#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C) -#define MCHP_CHIP_DEVID_POS 16 -#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS) -#define MCHP_CHIP_SUBID_POS 8 -#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS) -#define MCHP_CHIP_REV_POS 0 -#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS) +#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C) +#define MCHP_CHIP_DEVID_POS 16 +#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS) +#define MCHP_CHIP_SUBID_POS 8 +#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS) +#define MCHP_CHIP_REV_POS 0 +#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS) #define MCHP_CHIP_EXTRACT_DEVID(d) \ - (((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS) + (((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS) #define MCHP_CHIP_EXTRACT_SUBID(d) \ - (((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS) + (((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS) #define MCHP_CHIP_EXTRACT_REV(d) \ - (((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS) + (((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS) /* PCR clock control dividers */ -#define MCHP_PCR_CLK_CTL_FASTEST 1U -#define MCHP_PCR_CLK_CTL_48MHZ 1U -#define MCHP_PCR_CLK_CTL_12MHZ 4U +#define MCHP_PCR_CLK_CTL_FASTEST 1U +#define MCHP_PCR_CLK_CTL_48MHZ 1U +#define MCHP_PCR_CLK_CTL_12MHZ 4U /* * PCR Peripheral Reset Lock register @@ -251,296 +250,295 @@ * register, write to PCR reset enable register(s), and * write a lock value. */ -#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84) -#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d -#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c +#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84) +#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d +#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c /* Number of PCR Sleep Enable, Clock Required, and Reset registers */ -#define MCHP_PCR_SLP_RST_REG_MAX 5 +#define MCHP_PCR_SLP_RST_REG_MAX 5 /* MC152x new bit allow sleep entry when PLL is not locked */ -#define MCHP_PCR_SYS_SLP_NO_PLL BIT(8) +#define MCHP_PCR_SYS_SLP_NO_PLL BIT(8) /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ -#define MCHP_PCR_OTP BIT(1) +#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ +#define MCHP_PCR_OTP BIT(1) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_JTAG BIT(0) -#define MCHP_PCR_SLP_EN0_OTP BIT(1) -#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN0_JTAG BIT(0) +#define MCHP_PCR_SLP_EN0_OTP BIT(1) +#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff /* * Encode register number and bit position * b[4:0] = bit number * b[10:8] = zero based register number */ -#define MCHP_PCR_ERB(rnum, bnum) \ - ((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f)) +#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f)) /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) -#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) -#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) -#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) -#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) -#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) -#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) -#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) -#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) -#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) -#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) -#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13) -#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) -#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) -#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) -#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) -#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) -#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) -#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) -#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) -#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) -#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) -#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) -#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) +#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) +#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) +#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) +#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) +#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) +#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) +#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) +#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) +#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) +#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) +#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) +#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13) +#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) +#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) +#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) +#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) +#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) +#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) +#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) +#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) +#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) +#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) +#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) +#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) -#define MCHP_PCR_SLP_EN1_ECS BIT(29) -#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) -#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) -#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) -#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) -#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) -#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) -#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) -#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) -#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) -#define MCHP_PCR_SLP_EN1_TACH3 BIT(13) -#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) -#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) -#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) -#define MCHP_PCR_SLP_EN1_WDT BIT(9) -#define MCHP_PCR_SLP_EN1_CPU BIT(8) -#define MCHP_PCR_SLP_EN1_TFDP BIT(7) -#define MCHP_PCR_SLP_EN1_DMA BIT(6) -#define MCHP_PCR_SLP_EN1_PMC BIT(5) -#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) -#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) -#define MCHP_PCR_SLP_EN1_PECI BIT(1) -#define MCHP_PCR_SLP_EN1_ECIA BIT(0) +#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) +#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) +#define MCHP_PCR_SLP_EN1_ECS BIT(29) +#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) +#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) +#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) +#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) +#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) +#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) +#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) +#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) +#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) +#define MCHP_PCR_SLP_EN1_TACH3 BIT(13) +#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) +#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) +#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) +#define MCHP_PCR_SLP_EN1_WDT BIT(9) +#define MCHP_PCR_SLP_EN1_CPU BIT(8) +#define MCHP_PCR_SLP_EN1_TFDP BIT(7) +#define MCHP_PCR_SLP_EN1_DMA BIT(6) +#define MCHP_PCR_SLP_EN1_PMC BIT(5) +#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) +#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) +#define MCHP_PCR_SLP_EN1_PECI BIT(1) +#define MCHP_PCR_SLP_EN1_ECIA BIT(0) /* all sleep enable 1 bits */ -#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff /* * block not used by default * Do not sleep ECIA, PMC, CPU and ECS */ -#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede +#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */ -#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29) -#define MCHP_PCR_UART2 MCHP_PCR_ERB(2, 28) -#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27) -#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26) -#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25) -#define MCHP_PCR_ASIF MCHP_PCR_ERB(2, 24) -#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) -#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) -#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20) -#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) -#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) -#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) -#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26) -#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) -#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) -#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) -#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) -#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) -#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) -#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0) +#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29) +#define MCHP_PCR_UART2 MCHP_PCR_ERB(2, 28) +#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27) +#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26) +#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25) +#define MCHP_PCR_ASIF MCHP_PCR_ERB(2, 24) +#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) +#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) +#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20) +#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) +#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) +#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) +#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26) +#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) +#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) +#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) +#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) +#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) +#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) +#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN2_GLUE BIT(29) -#define MCHP_PCR_SLP_EN2_UART2 BIT(28) -#define MCHP_PCR_SLP_EN2_SAF BIT(27) -#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) -#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) -#define MCHP_PCR_SLP_EN2_ASIF BIT(24) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) -#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) -#define MCHP_PCR_SLP_EN2_ESPI BIT(19) -#define MCHP_PCR_SLP_EN2_RTC BIT(18) -#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) -#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) -#define MCHP_PCR_SLP_EN2_GCFG BIT(12) -#define MCHP_PCR_SLP_EN2_UART1 BIT(2) -#define MCHP_PCR_SLP_EN2_UART0 BIT(1) -#define MCHP_PCR_SLP_EN2_EMI0 BIT(0) +#define MCHP_PCR_SLP_EN2_GLUE BIT(29) +#define MCHP_PCR_SLP_EN2_UART2 BIT(28) +#define MCHP_PCR_SLP_EN2_SAF BIT(27) +#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) +#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) +#define MCHP_PCR_SLP_EN2_ASIF BIT(24) +#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) +#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) +#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) +#define MCHP_PCR_SLP_EN2_ESPI BIT(19) +#define MCHP_PCR_SLP_EN2_RTC BIT(18) +#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) +#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) +#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) +#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) +#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) +#define MCHP_PCR_SLP_EN2_GCFG BIT(12) +#define MCHP_PCR_SLP_EN2_UART1 BIT(2) +#define MCHP_PCR_SLP_EN2_UART0 BIT(1) +#define MCHP_PCR_SLP_EN2_EMI0 BIT(0) /* all sleep enable 2 bits */ -#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */ -#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) -#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) -#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28) -#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27) -#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26) -#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) -#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) -#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20) -#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) -#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) -#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) -#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) -#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) -#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) -#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) -#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) -#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6) -#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) -#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) -#define MCHP_PCR_HDMI_CEC MCHP_PCR_ERB(3, 1) +#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) +#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) +#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28) +#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27) +#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26) +#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) +#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) +#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20) +#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) +#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) +#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) +#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) +#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) +#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) +#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) +#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) +#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6) +#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) +#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) +#define MCHP_PCR_HDMI_CEC MCHP_PCR_ERB(3, 1) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) -#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) -#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) -#define MCHP_PCR_SLP_EN3_RNG BIT(27) -#define MCHP_PCR_SLP_EN3_PKE BIT(26) -#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) -#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) -#define MCHP_PCR_SLP_EN3_LED2 BIT(18) -#define MCHP_PCR_SLP_EN3_LED1 BIT(17) -#define MCHP_PCR_SLP_EN3_LED0 BIT(16) -#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) -#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) -#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) -#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) -#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) -#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) -#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) -#define MCHP_PCR_SLP_EN3_ADC BIT(3) -#define MCHP_PCR_SLP_EN3_HDMI_CEC BIT(1) -#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26) +#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) +#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) +#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) +#define MCHP_PCR_SLP_EN3_RNG BIT(27) +#define MCHP_PCR_SLP_EN3_PKE BIT(26) +#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) +#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) +#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) +#define MCHP_PCR_SLP_EN3_LED2 BIT(18) +#define MCHP_PCR_SLP_EN3_LED1 BIT(17) +#define MCHP_PCR_SLP_EN3_LED0 BIT(16) +#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) +#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) +#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) +#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) +#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) +#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) +#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) +#define MCHP_PCR_SLP_EN3_ADC BIT(3) +#define MCHP_PCR_SLP_EN3_HDMI_CEC BIT(1) +#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26) /* all sleep enable 3 bits */ -#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffffd -#define MCHP_PCR_SLP_EN3_PWM_ALL 0 +#define MCHP_PCR_SLP_EN3_SLEEP 0xfffffffd +#define MCHP_PCR_SLP_EN3_PWM_ALL 0 /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */ -#define MCHP_PCR_SGPIO3 MCHP_PCR_ERB(4, 20) -#define MCHP_PCR_SGPIO2 MCHP_PCR_ERB(4, 19) -#define MCHP_PCR_SGPIO1 MCHP_PCR_ERB(4, 18) -#define MCHP_PCR_SGPIO0 MCHP_PCR_ERB(4, 17) -#define MCHP_PCR_SLV_SPI MCHP_PCR_ERB(4, 16) -#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) -#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) -#define MCHP_PCR_I2C7 MCHP_PCR_ERB(4, 12) -#define MCHP_PCR_I2C6 MCHP_PCR_ERB(4, 11) -#define MCHP_PCR_I2C5 MCHP_PCR_ERB(4, 10) -#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) -#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) +#define MCHP_PCR_SGPIO3 MCHP_PCR_ERB(4, 20) +#define MCHP_PCR_SGPIO2 MCHP_PCR_ERB(4, 19) +#define MCHP_PCR_SGPIO1 MCHP_PCR_ERB(4, 18) +#define MCHP_PCR_SGPIO0 MCHP_PCR_ERB(4, 17) +#define MCHP_PCR_SLV_SPI MCHP_PCR_ERB(4, 16) +#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) +#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) +#define MCHP_PCR_I2C7 MCHP_PCR_ERB(4, 12) +#define MCHP_PCR_I2C6 MCHP_PCR_ERB(4, 11) +#define MCHP_PCR_I2C5 MCHP_PCR_ERB(4, 10) +#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) +#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN4_SGPIO3 BIT(20) -#define MCHP_PCR_SLP_EN4_SGPIO2 BIT(19) -#define MCHP_PCR_SLP_EN4_SGPIO1 BIT(18) -#define MCHP_PCR_SLP_EN4_SGPIO0 BIT(17) -#define MCHP_PCR_SLP_EN4_SLV_SPI BIT(16) -#define MCHP_PCR_SLP_EN4_PSPI BIT(14) -#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) -#define MCHP_PCR_SLP_EN4_I2C7 BIT(12) -#define MCHP_PCR_SLP_EN4_I2C6 BIT(11) -#define MCHP_PCR_SLP_EN4_I2C5 BIT(10) -#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) -#define MCHP_PCR_SLP_EN4_RTMR BIT(6) +#define MCHP_PCR_SLP_EN4_SGPIO3 BIT(20) +#define MCHP_PCR_SLP_EN4_SGPIO2 BIT(19) +#define MCHP_PCR_SLP_EN4_SGPIO1 BIT(18) +#define MCHP_PCR_SLP_EN4_SGPIO0 BIT(17) +#define MCHP_PCR_SLP_EN4_SLV_SPI BIT(16) +#define MCHP_PCR_SLP_EN4_PSPI BIT(14) +#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) +#define MCHP_PCR_SLP_EN4_I2C7 BIT(12) +#define MCHP_PCR_SLP_EN4_I2C6 BIT(11) +#define MCHP_PCR_SLP_EN4_I2C5 BIT(10) +#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) +#define MCHP_PCR_SLP_EN4_RTMR BIT(6) /* all sleep enable 4 bits */ -#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff -#define MCHP_PCR_SLP_EN4_PWM_ALL 0 +#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN4_PWM_ALL 0 /* Allow all blocks to request clocks */ -#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP)) -#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP)) -#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP)) -#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP)) -#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP)) +#define MCHP_PCR_SLP_EN0_WAKE (~(MCHP_PCR_SLP_EN0_SLEEP)) +#define MCHP_PCR_SLP_EN1_WAKE (~(MCHP_PCR_SLP_EN1_SLEEP)) +#define MCHP_PCR_SLP_EN2_WAKE (~(MCHP_PCR_SLP_EN2_SLEEP)) +#define MCHP_PCR_SLP_EN3_WAKE (~(MCHP_PCR_SLP_EN3_SLEEP)) +#define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP)) /* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_MASK_RO 0xc8c -#define MCHP_PWR_RST_STS_MASK_RWC 0x170 +#define MCHP_PWR_RST_STS_MASK_RO 0xc8c +#define MCHP_PWR_RST_STS_MASK_RWC 0x170 #define MCHP_PWR_RST_STS_MASK \ ((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC)) -#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ -#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ -#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ -#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ -#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ -#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ -#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */ -#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ -#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ +#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ +#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ +#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ +#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ +#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ +#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ +#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */ +#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ +#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ /* Bit defines for MCHP_PCR_PWR_RST_CTL */ -#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 -#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) -#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8) -#define MCHP_PCR_PWR_OK_INV_BITPOS 0 +#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 +#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) +#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8) +#define MCHP_PCR_PWR_OK_INV_BITPOS 0 /* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET BIT(8) +#define MCHP_PCR_SYS_SOFT_RESET BIT(8) /* EC Subsystem */ -#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) -#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) -#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) -#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) -#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) -#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) -#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) -#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c) -#define MCHP_EC_VCI_FW_OVRD REG8(MCHP_EC_BASE + 0x50) -#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c) -#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64) -#define MCHP_EC_SLP_STS_MIRROR REG8(MCHP_EC_BASE + 0x114) +#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) +#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) +#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) +#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) +#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) +#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) +#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) +#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c) +#define MCHP_EC_VCI_FW_OVRD REG8(MCHP_EC_BASE + 0x50) +#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c) +#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64) +#define MCHP_EC_SLP_STS_MIRROR REG8(MCHP_EC_BASE + 0x114) /* AHB ERR Enable bit[0]=0(enable), 1(disable) */ -#define MCHP_EC_AHB_ERROR_ENABLE 0 -#define MCHP_EC_AHB_ERROR_DISABLE 1 +#define MCHP_EC_AHB_ERROR_ENABLE 0 +#define MCHP_EC_AHB_ERROR_DISABLE 1 /* MCHP_EC_JTAG_EN bit definitions */ -#define MCHP_JTAG_ENABLE 0x01 +#define MCHP_JTAG_ENABLE 0x01 /* bits [2:1] */ -#define MCHP_JTAG_MODE_4PIN 0x00 +#define MCHP_JTAG_MODE_4PIN 0x00 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */ -#define MCHP_JTAG_MODE_SWD_SWV 0x02 +#define MCHP_JTAG_MODE_SWD_SWV 0x02 /* ARM 2-pin SWD with no SWV */ -#define MCHP_JTAG_MODE_SWD 0x04 +#define MCHP_JTAG_MODE_SWD 0x04 /* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */ -#define MCHP_CRYPTO_NDRNG_SRST 0x01 -#define MCHP_CRYPTO_PKE_SRST 0x02 -#define MCHP_CRYPTO_AES_SHA_SRST 0x04 -#define MCHP_CRYPTO_ALL_SRST 0x07 +#define MCHP_CRYPTO_NDRNG_SRST 0x01 +#define MCHP_CRYPTO_PKE_SRST 0x02 +#define MCHP_CRYPTO_AES_SHA_SRST 0x04 +#define MCHP_CRYPTO_ALL_SRST 0x07 /* MCHP_GPIO_BANK_PWR bit definitions */ -#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86 -#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02 -#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04 -#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80 +#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86 +#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02 +#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04 +#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80 /* EC Interrupt aggregator (ECIA) */ -#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ -#define MCHP_INT_GIRQ_FIRST 8 -#define MCHP_INT_GIRQ_LAST 26 -#define MCHP_INT_GIRQ_NUM (26-8+1) +#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ +#define MCHP_INT_GIRQ_FIRST 8 +#define MCHP_INT_GIRQ_LAST 26 +#define MCHP_INT_GIRQ_NUM (26 - 8 + 1) /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */ -#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN)) +#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN)) /* * GPIO GIRQ's are not direct capable @@ -554,8 +552,8 @@ * GIRQ22 wake peripheral clock only * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires */ -#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U -#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U +#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U +#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U /* GIRQ13 I2C controllers. Direct capable */ #define MCHP_INT13_I2C(x) (1ul << (x)) @@ -564,120 +562,120 @@ #define MCHP_INT14_DMA(x) (1ul << (x)) /* GIQ15 interrupt sources. Direct capable */ -#define MCHP_INT15_UART_0 BIT(0) -#define MCHP_INT15_UART_1 BIT(1) -#define MCHP_INT15_UART_2 BIT(4) -#define MCHP_INT15_EMI_0 BIT(2) -#define MCHP_INT15_EMI_1 BIT(3) -#define MCHP_INT15_ACPI_EC0_IBF BIT(5) -#define MCHP_INT15_ACPI_EC0_OBE BIT(6) -#define MCHP_INT15_ACPI_EC1_IBF BIT(7) -#define MCHP_INT15_ACPI_EC1_OBE BIT(8) -#define MCHP_INT15_ACPI_EC2_IBF BIT(9) -#define MCHP_INT15_ACPI_EC2_OBE BIT(10) -#define MCHP_INT15_ACPI_EC3_IBF BIT(11) -#define MCHP_INT15_ACPI_EC3_OBE BIT(12) -#define MCHP_INT15_ACPI_PM1_CTL BIT(15) -#define MCHP_INT15_ACPI_PM1_EN BIT(16) -#define MCHP_INT15_ACPI_PM1_STS BIT(17) -#define MCHP_INT15_8042_OBE BIT(18) -#define MCHP_INT15_8042_IBF BIT(19) -#define MCHP_INT15_MAILBOX BIT(20) -#define MCHP_INT15_P80_0 BIT(22) -#define MCHP_INT15_P80_1 BIT(23) -#define MCHP_INT15_P80(x) BIT(22 + ((x) & 0x01U)) +#define MCHP_INT15_UART_0 BIT(0) +#define MCHP_INT15_UART_1 BIT(1) +#define MCHP_INT15_UART_2 BIT(4) +#define MCHP_INT15_EMI_0 BIT(2) +#define MCHP_INT15_EMI_1 BIT(3) +#define MCHP_INT15_ACPI_EC0_IBF BIT(5) +#define MCHP_INT15_ACPI_EC0_OBE BIT(6) +#define MCHP_INT15_ACPI_EC1_IBF BIT(7) +#define MCHP_INT15_ACPI_EC1_OBE BIT(8) +#define MCHP_INT15_ACPI_EC2_IBF BIT(9) +#define MCHP_INT15_ACPI_EC2_OBE BIT(10) +#define MCHP_INT15_ACPI_EC3_IBF BIT(11) +#define MCHP_INT15_ACPI_EC3_OBE BIT(12) +#define MCHP_INT15_ACPI_PM1_CTL BIT(15) +#define MCHP_INT15_ACPI_PM1_EN BIT(16) +#define MCHP_INT15_ACPI_PM1_STS BIT(17) +#define MCHP_INT15_8042_OBE BIT(18) +#define MCHP_INT15_8042_IBF BIT(19) +#define MCHP_INT15_MAILBOX BIT(20) +#define MCHP_INT15_P80_0 BIT(22) +#define MCHP_INT15_P80_1 BIT(23) +#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U)) /* GIRQ16 interrupt sources. Direct capable */ -#define MCHP_INT16_PKE_ERR BIT(0) -#define MCHP_INT16_PKE_DONE BIT(1) -#define MCHP_INT16_RNG_DONE BIT(2) -#define MCHP_INT16_AES_DONE BIT(3) -#define MCHP_INT16_HASH_DONE BIT(4) +#define MCHP_INT16_PKE_ERR BIT(0) +#define MCHP_INT16_PKE_DONE BIT(1) +#define MCHP_INT16_RNG_DONE BIT(2) +#define MCHP_INT16_AES_DONE BIT(3) +#define MCHP_INT16_HASH_DONE BIT(4) /* GIR17 interrupt sources. Direct capable */ -#define MCHP_INT17_PECI BIT(0) -#define MCHP_INT17_TACH_0 BIT(1) -#define MCHP_INT17_TACH_1 BIT(2) -#define MCHP_INT17_TACH_2 BIT(3) -#define MCHP_INT17_TACH_3 BIT(4) -#define MCHP_INT17_HDMI_CEC BIT(5) -#define MCHP_INT17_ADC_SINGLE BIT(8) -#define MCHP_INT17_ADC_REPEAT BIT(9) -#define MCHP_INT17_LED_WDT_0 BIT(13) -#define MCHP_INT17_LED_WDT_1 BIT(14) -#define MCHP_INT17_LED_WDT_2 BIT(15) -#define MCHP_INT17_PROCHOT BIT(17) +#define MCHP_INT17_PECI BIT(0) +#define MCHP_INT17_TACH_0 BIT(1) +#define MCHP_INT17_TACH_1 BIT(2) +#define MCHP_INT17_TACH_2 BIT(3) +#define MCHP_INT17_TACH_3 BIT(4) +#define MCHP_INT17_HDMI_CEC BIT(5) +#define MCHP_INT17_ADC_SINGLE BIT(8) +#define MCHP_INT17_ADC_REPEAT BIT(9) +#define MCHP_INT17_LED_WDT_0 BIT(13) +#define MCHP_INT17_LED_WDT_1 BIT(14) +#define MCHP_INT17_LED_WDT_2 BIT(15) +#define MCHP_INT17_PROCHOT BIT(17) /* GIRQ18 interrupt sources. Direct capable */ -#define MCHP_INT18_SLV_SPI BIT(0) -#define MCHP_INT18_QMSPI BIT(1) -#define MCHP_INT18_PS2_0 BIT(10) -#define MCHP_INT18_PS2_1 BIT(11) -#define MCHP_INT18_CCT BIT(20) -#define MCHP_INT18_CCT_CAP0 BIT(21) -#define MCHP_INT18_CCT_CAP1 BIT(22) -#define MCHP_INT18_CCT_CAP2 BIT(23) -#define MCHP_INT18_CCT_CAP3 BIT(24) -#define MCHP_INT18_CCT_CAP4 BIT(25) -#define MCHP_INT18_CCT_CAP6 BIT(26) -#define MCHP_INT18_CCT_CMP0 BIT(27) -#define MCHP_INT18_CCT_CMP1 BIT(28) +#define MCHP_INT18_SLV_SPI BIT(0) +#define MCHP_INT18_QMSPI BIT(1) +#define MCHP_INT18_PS2_0 BIT(10) +#define MCHP_INT18_PS2_1 BIT(11) +#define MCHP_INT18_CCT BIT(20) +#define MCHP_INT18_CCT_CAP0 BIT(21) +#define MCHP_INT18_CCT_CAP1 BIT(22) +#define MCHP_INT18_CCT_CAP2 BIT(23) +#define MCHP_INT18_CCT_CAP3 BIT(24) +#define MCHP_INT18_CCT_CAP4 BIT(25) +#define MCHP_INT18_CCT_CAP6 BIT(26) +#define MCHP_INT18_CCT_CMP0 BIT(27) +#define MCHP_INT18_CCT_CMP1 BIT(28) /* GIRQ19 interrupt sources. Direct capable */ -#define MCHP_INT19_ESPI_PC BIT(0) -#define MCHP_INT19_ESPI_BM1 BIT(1) -#define MCHP_INT19_ESPI_BM2 BIT(2) -#define MCHP_INT19_ESPI_LTR BIT(3) -#define MCHP_INT19_ESPI_OOB_TX BIT(4) -#define MCHP_INT19_ESPI_OOB_RX BIT(5) -#define MCHP_INT19_ESPI_FC BIT(6) -#define MCHP_INT19_ESPI_RESET BIT(7) -#define MCHP_INT19_ESPI_VW_EN BIT(8) -#define MCHP_INT19_ESPI_SAF BIT(9) -#define MCHP_INT19_ESPI_SAF_ERR BIT(10) +#define MCHP_INT19_ESPI_PC BIT(0) +#define MCHP_INT19_ESPI_BM1 BIT(1) +#define MCHP_INT19_ESPI_BM2 BIT(2) +#define MCHP_INT19_ESPI_LTR BIT(3) +#define MCHP_INT19_ESPI_OOB_TX BIT(4) +#define MCHP_INT19_ESPI_OOB_RX BIT(5) +#define MCHP_INT19_ESPI_FC BIT(6) +#define MCHP_INT19_ESPI_RESET BIT(7) +#define MCHP_INT19_ESPI_VW_EN BIT(8) +#define MCHP_INT19_ESPI_SAF BIT(9) +#define MCHP_INT19_ESPI_SAF_ERR BIT(10) /* GIRQ20 interrupt sources. Direct capable */ -#define MCHP_INT20_OPT BIT(3) +#define MCHP_INT20_OPT BIT(3) /* GIRQ21 interrupt sources. Direct capable */ -#define MCHP_INT21_WDT BIT(2) -#define MCHP_INT21_WEEK_ALARM BIT(3) -#define MCHP_INT21_WEEK_SUB BIT(4) -#define MCHP_INT21_WEEK_1SEC BIT(5) -#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) -#define MCHP_INT21_WEEK_PWR_PRES BIT(7) -#define MCHP_INT21_RTC BIT(8) -#define MCHP_INT21_RTC_ALARM BIT(9) -#define MCHP_INT21_VCI_OVRD BIT(10) -#define MCHP_INT21_VCI_IN0 BIT(11) -#define MCHP_INT21_VCI_IN1 BIT(12) -#define MCHP_INT21_VCI_IN2 BIT(13) -#define MCHP_INT21_VCI_IN3 BIT(14) -#define MCHP_INT21_PS2_0A_WAKE BIT(18) -#define MCHP_INT21_PS2_0B_WAKE BIT(19) -#define MCHP_INT21_PS2_1B_WAKE BIT(21) -#define MCHP_INT21_KEYSCAN BIT(25) +#define MCHP_INT21_WDT BIT(2) +#define MCHP_INT21_WEEK_ALARM BIT(3) +#define MCHP_INT21_WEEK_SUB BIT(4) +#define MCHP_INT21_WEEK_1SEC BIT(5) +#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) +#define MCHP_INT21_WEEK_PWR_PRES BIT(7) +#define MCHP_INT21_RTC BIT(8) +#define MCHP_INT21_RTC_ALARM BIT(9) +#define MCHP_INT21_VCI_OVRD BIT(10) +#define MCHP_INT21_VCI_IN0 BIT(11) +#define MCHP_INT21_VCI_IN1 BIT(12) +#define MCHP_INT21_VCI_IN2 BIT(13) +#define MCHP_INT21_VCI_IN3 BIT(14) +#define MCHP_INT21_PS2_0A_WAKE BIT(18) +#define MCHP_INT21_PS2_0B_WAKE BIT(19) +#define MCHP_INT21_PS2_1B_WAKE BIT(21) +#define MCHP_INT21_KEYSCAN BIT(25) /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */ -#define MCHP_INT22_WAKE_ONLY_SLV_SPI BIT(0) -#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) -#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) -#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) -#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) -#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5) -#define MCHP_INT22_WAKE_ONLY_I2C5 BIT(6) -#define MCHP_INT22_WAKE_ONLY_I2C6 BIT(7) -#define MCHP_INT22_WAKE_ONLY_I2C7 BIT(8) -#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) +#define MCHP_INT22_WAKE_ONLY_SLV_SPI BIT(0) +#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) +#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) +#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) +#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) +#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5) +#define MCHP_INT22_WAKE_ONLY_I2C5 BIT(6) +#define MCHP_INT22_WAKE_ONLY_I2C6 BIT(7) +#define MCHP_INT22_WAKE_ONLY_I2C7 BIT(8) +#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) /* GIRQ23 sources. Direct capable */ -#define MCHP_INT23_BTMR16_0 BIT(0) -#define MCHP_INT23_BTMR16_1 BIT(1) -#define MCHP_INT23_BTMR32_0 BIT(4) -#define MCHP_INT23_BTMR32_1 BIT(5) -#define MCHP_INT23_RTMR BIT(10) -#define MCHP_INT23_HTMR_0 BIT(16) -#define MCHP_INT23_HTMR_1 BIT(17) +#define MCHP_INT23_BTMR16_0 BIT(0) +#define MCHP_INT23_BTMR16_1 BIT(1) +#define MCHP_INT23_BTMR32_0 BIT(4) +#define MCHP_INT23_BTMR32_1 BIT(5) +#define MCHP_INT23_RTMR BIT(10) +#define MCHP_INT23_HTMR_0 BIT(16) +#define MCHP_INT23_HTMR_1 BIT(17) /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */ #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s))) @@ -686,20 +684,19 @@ #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s))) /* UART Peripheral 0 <= x <= 2 */ -#define MCHP_UART_INSTANCES 3 -#define MCHP_UART_SPACING 0x400 -#define MCHP_UART_CFG_OFS 0x300 +#define MCHP_UART_INSTANCES 3 +#define MCHP_UART_SPACING 0x400 +#define MCHP_UART_CFG_OFS 0x300 #define MCHP_UART_CONFIG_BASE(x) \ - (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_RUNTIME_BASE(x) \ - (MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_GIRQ 15 -#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) -#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) -#define MCHP_UART2_GIRQ_BIT (MCHP_INT15_UART_2) -#define MCHP_UART_GIRQ_BIT(x) BIT(x) + (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_GIRQ 15 +#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) +#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) +#define MCHP_UART2_GIRQ_BIT (MCHP_INT15_UART_2) +#define MCHP_UART_GIRQ_BIT(x) BIT(x) /* BIT defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY BIT(5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* * GPIO @@ -729,8 +726,8 @@ * id = 0x9d & 0x1f = 0x1d * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274 */ -#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \ - (((port << 5) + id) << 2)) +#define MCHP_GPIO_CTL(port, id) \ + REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2)) /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT 6 @@ -740,272 +737,257 @@ * In MECxxxx documentation GPIO numbers are octal, each control * register is located on a 32-bit boundary. */ -#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \ - ((gpio_num) << 2)) +#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2)) /* * GPIO control register bit fields */ -#define MCHP_GPIO_CTRL_PUD_BITPOS 0 -#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 -#define MCHP_GPIO_CTRL_PUD_MASK 0x03 -#define MCHP_GPIO_CTRL_PUD_NONE 0x00 -#define MCHP_GPIO_CTRL_PUD_PU 0x01 -#define MCHP_GPIO_CTRL_PUD_PD 0x02 -#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 -#define MCHP_GPIO_CTRL_PWR_BITPOS 2 -#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 -#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2) -#define MCHP_GPIO_CTRL_PWR_VTR (0x00 << 2) -#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2) -#define MCHP_GPIO_INTDET_MASK 0xF0 -#define MCHP_GPIO_INTDET_LVL_LO 0x00 -#define MCHP_GPIO_INTDET_LVL_HI 0x10 -#define MCHP_GPIO_INTDET_DISABLED 0x40 -#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0 -#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0 -#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0 -#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) -#define MCHP_GPIO_PUSH_PULL 0u -#define MCHP_GPIO_OPEN_DRAIN BIT(8) -#define MCHP_GPIO_INPUT 0u -#define MCHP_GPIO_OUTPUT BIT(9) -#define MCHP_GPIO_OUTSET_CTRL 0u -#define MCHP_GPIO_OUTSEL_PAR BIT(10) -#define MCHP_GPIO_POLARITY_NINV 0u -#define MCHP_GPIO_POLARITY_INV BIT(11) -#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12) -#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12) -#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) -#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) -#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) -#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) +#define MCHP_GPIO_CTRL_PUD_BITPOS 0 +#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 +#define MCHP_GPIO_CTRL_PUD_MASK 0x03 +#define MCHP_GPIO_CTRL_PUD_NONE 0x00 +#define MCHP_GPIO_CTRL_PUD_PU 0x01 +#define MCHP_GPIO_CTRL_PUD_PD 0x02 +#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 +#define MCHP_GPIO_CTRL_PWR_BITPOS 2 +#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 +#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2) +#define MCHP_GPIO_CTRL_PWR_VTR (0x00 << 2) +#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2) +#define MCHP_GPIO_INTDET_MASK 0xF0 +#define MCHP_GPIO_INTDET_LVL_LO 0x00 +#define MCHP_GPIO_INTDET_LVL_HI 0x10 +#define MCHP_GPIO_INTDET_DISABLED 0x40 +#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0 +#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0 +#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0 +#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) +#define MCHP_GPIO_PUSH_PULL 0u +#define MCHP_GPIO_OPEN_DRAIN BIT(8) +#define MCHP_GPIO_INPUT 0u +#define MCHP_GPIO_OUTPUT BIT(9) +#define MCHP_GPIO_OUTSET_CTRL 0u +#define MCHP_GPIO_OUTSEL_PAR BIT(10) +#define MCHP_GPIO_POLARITY_NINV 0u +#define MCHP_GPIO_POLARITY_INV BIT(11) +#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12) +#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12) +#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) +#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) +#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) +#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) /* MEC15xx only */ -#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 -#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15) +#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 +#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15) /* * GPIO Parallel Input and Output registers. * gpio_bank in [0, 5] */ -#define MCHP_GPIO_PARIN(bank) \ - REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) -#define MCHP_GPIO_PAROUT(bank) \ - REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) +#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) +#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) /* Basic timers */ -#define MCHP_TMR_SPACING 0x20 -#define MCHP_TMR16_INSTANCES 2 -#define MCHP_TMR32_INSTANCES 2 -#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) -#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) -#define MCHP_TMR16_BASE(n) \ - (MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR32_BASE(n) \ - (MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR16_GIRQ 23 -#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) -#define MCHP_TMR32_GIRQ 23 -#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) +#define MCHP_TMR_SPACING 0x20 +#define MCHP_TMR16_INSTANCES 2 +#define MCHP_TMR32_INSTANCES 2 +#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) +#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) +#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR16_GIRQ 23 +#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) +#define MCHP_TMR32_GIRQ 23 +#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) /* RTimer */ -#define MCHP_RTMR_GIRQ 23 -#define MCHP_RTMR_GIRQ_BIT(x) BIT(10) +#define MCHP_RTMR_GIRQ 23 +#define MCHP_RTMR_GIRQ_BIT(x) BIT(10) /* Watchdog */ /* MEC152x specific registers */ -#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10) -#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14) +#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10) +#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14) /* Status */ -#define MCHP_WDG_STS_IRQ BIT(0) +#define MCHP_WDG_STS_IRQ BIT(0) /* Interrupt enable */ -#define MCHP_WDG_IEN_IRQ_EN BIT(0) -#define MCHP_WDG_GIRQ 21 -#define MCHP_WDG_GIRQ_BIT BIT(2) +#define MCHP_WDG_IEN_IRQ_EN BIT(0) +#define MCHP_WDG_GIRQ 21 +#define MCHP_WDG_GIRQ_BIT BIT(2) /* Control register has a bit to enable IRQ generation */ -#define MCHP_WDG_RESET_IRQ_EN BIT(9) +#define MCHP_WDG_RESET_IRQ_EN BIT(9) /* VBAT */ -#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) -#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8) -#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC) -#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) -#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) +#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) +#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8) +#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC) +#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) +#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) /* read 32-bit word at 32-bit offset x where 0 <= x <= 16 */ -#define MCHP_VBAT_RAM_SIZE 64 -#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4)) -#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum)) -#define MCHP_VBAT_VWIRE_BACKUP 14 +#define MCHP_VBAT_RAM_SIZE 64 +#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4)) +#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum)) +#define MCHP_VBAT_VWIRE_BACKUP 14 /* * Miscellaneous firmware control fields * scratch pad index cannot be more than 32 as * MEC152x has 64 bytes = 16 words of scratch pad RAM */ -#define MCHP_IMAGETYPE_IDX 15 +#define MCHP_IMAGETYPE_IDX 15 /* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET BIT(2) -#define MCHP_VBAT_STS_RESETI BIT(4) -#define MCHP_VBAT_STS_WDT BIT(5) -#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) -#define MCHP_VBAT_STS_VBAT_RST BIT(7) -#define MCHP_VBAT_STS_ANY_RST 0xF4u +#define MCHP_VBAT_STS_SOFTRESET BIT(2) +#define MCHP_VBAT_STS_RESETI BIT(4) +#define MCHP_VBAT_STS_WDT BIT(5) +#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) +#define MCHP_VBAT_STS_VBAT_RST BIT(7) +#define MCHP_VBAT_STS_ANY_RST 0xF4u /* Bit definitions for MCHP_VBAT_CE */ -#define MCHP_VBAT_CE_XOSEL_BITPOS 3 -#define MCHP_VBAT_CE_XOSEL_MASK BIT(3) -#define MCHP_VBAT_CE_XOSEL_PAR 0 -#define MCHP_VBAT_CE_XOSEL_SE BIT(3) +#define MCHP_VBAT_CE_XOSEL_BITPOS 3 +#define MCHP_VBAT_CE_XOSEL_MASK BIT(3) +#define MCHP_VBAT_CE_XOSEL_PAR 0 +#define MCHP_VBAT_CE_XOSEL_SE BIT(3) -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2 -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2) -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0 -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2) +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2 +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2) +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0 +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2) -#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1 -#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1) -#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0 -#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1) +#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1 +#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1) +#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0 +#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1) /* Blinking-Breathing LED 0 <= n <= 2 */ -#define MCHP_BBLEB_INSTANCES 3 -#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n) & 0x03) * 256)) +#define MCHP_BBLEB_INSTANCES 3 +#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256)) /* EMI */ -#define MCHP_EMI_INSTANCES 2 -#define MCHP_EMI_SPACING 0x400 -#define MCHP_EMI_ECREG_OFS 0x100 +#define MCHP_EMI_INSTANCES 2 +#define MCHP_EMI_SPACING 0x400 +#define MCHP_EMI_ECREG_OFS 0x100 /* base of EMI registers only accessible by EC */ #define MCHP_EMI_BASE(n) \ - (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING)) + (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING)) /* base of EMI registers accessible by EC and Host */ -#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING)) -#define MCHP_EMI_GIRQ 15 -#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) +#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING)) +#define MCHP_EMI_GIRQ 15 +#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) /* Mailbox */ -#define MCHP_MBX_ECREGS_OFS 0x100 -#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE -#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) -#define MCHP_MBX_GIRQ 15 -#define MCHP_MBX_GIRQ_BIT BIT(20) +#define MCHP_MBX_ECREGS_OFS 0x100 +#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE +#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) +#define MCHP_MBX_GIRQ 15 +#define MCHP_MBX_GIRQ_BIT BIT(20) /* Port 80 Capture */ -#define MCHP_P80_SPACING 0x400 -#define MCHP_P80_BASE(n) \ - (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING))) -#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n)) +#define MCHP_P80_SPACING 0x400 +#define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING))) +#define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n)) /* Data capture with time stamp register */ -#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100) -#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104) -#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108) -#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c) -#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8) -#define MCHP_P80_CNT_SET(n, c) \ - (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8)) -#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330) -#define MCHP_P80_GIRQ 15 -#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n)) +#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100) +#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104) +#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108) +#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c) +#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8) +#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8)) +#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330) +#define MCHP_P80_GIRQ 15 +#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n)) /* * Port 80 Data register bits * bits[7:0] = data captured on Host write * bits[31:8] = optional time stamp */ -#define MCHP_P80_CAP_DATA_MASK 0xFFul -#define MCHP_P80_CAP_TS_BITPOS 8 -#define MCHP_P80_CAP_TS_MASK0 0xfffffful -#define MCHP_P80_CAP_TS_MASK \ +#define MCHP_P80_CAP_DATA_MASK 0xFFul +#define MCHP_P80_CAP_TS_BITPOS 8 +#define MCHP_P80_CAP_TS_MASK0 0xfffffful +#define MCHP_P80_CAP_TS_MASK \ ((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS)) /* Port 80 Configuration register bits */ -#define MCHP_P80_FLUSH_FIFO_WO BIT(1) -#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2) -#define MCHP_P80_TIMEBASE_BITPOS 3 -#define MCHP_P80_TIMEBASE_MASK0 0x03 -#define MCHP_P80_TIMEBASE_MASK \ +#define MCHP_P80_FLUSH_FIFO_WO BIT(1) +#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2) +#define MCHP_P80_TIMEBASE_BITPOS 3 +#define MCHP_P80_TIMEBASE_MASK0 0x03 +#define MCHP_P80_TIMEBASE_MASK \ ((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_750KHZ \ - (0x03 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_1500KHZ \ - (0x02 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_3MHZ \ - (0x01 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_6MHZ \ - (0x00 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMER_ENABLE BIT(5) -#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6) -#define MCHP_P80_FIFO_THRHOLD_1 0u -#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6) -#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6) -#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6) -#define MCHP_P80_FIFO_LEN 16 +#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMER_ENABLE BIT(5) +#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6) +#define MCHP_P80_FIFO_THRHOLD_1 0u +#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6) +#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6) +#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6) +#define MCHP_P80_FIFO_LEN 16 /* Port 80 Status register bits, read-only */ -#define MCHP_P80_STS_NOT_EMPTY BIT(0) -#define MCHP_P80_STS_OVERRUN BIT(1) +#define MCHP_P80_STS_NOT_EMPTY BIT(0) +#define MCHP_P80_STS_OVERRUN BIT(1) /* Port 80 Count register bits */ -#define MCHP_P80_CNT_BITPOS 8 -#define MCHP_P80_CNT_MASK0 0xfffffful -#define MCHP_P80_CNT_MASK \ - ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS)) +#define MCHP_P80_CNT_BITPOS 8 +#define MCHP_P80_CNT_MASK0 0xfffffful +#define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS)) /* PWM */ -#define MCHP_PWM_INSTANCES 9 -#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) -#define MCHP_PWM_SPACING 16 -#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING)) +#define MCHP_PWM_INSTANCES 9 +#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) +#define MCHP_PWM_SPACING 16 +#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING)) /* TACH */ -#define MCHP_TACH_INSTANCES 4 -#define MCHP_TACH_SPACING 16 -#define MCHP_TACH_BASE(x) \ - (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING)) -#define MCHP_TACH_GIRQ 17 -#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) +#define MCHP_TACH_INSTANCES 4 +#define MCHP_TACH_SPACING 16 +#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING)) +#define MCHP_TACH_GIRQ 17 +#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) /* ACPI EC */ -#define MCHP_ACPI_EC_INSTANCES 4 -#define MCHP_ACPI_EC_MAX (ACPI_EC_INSTANCES) -#define MCHP_ACPI_EC_SPACING 0x400 -#define MCHP_ACPI_EC_BASE(x) \ - (MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING)) -#define MCHP_ACPI_EC_GIRQ 15 -#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x) * 2)) -#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x) * 2)) +#define MCHP_ACPI_EC_INSTANCES 4 +#define MCHP_ACPI_EC_MAX (ACPI_EC_INSTANCES) +#define MCHP_ACPI_EC_SPACING 0x400 +#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING)) +#define MCHP_ACPI_EC_GIRQ 15 +#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2)) +#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2)) /* ACPI PM1 */ -#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 -#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE -#define MCHP_ACPI_PM_EC_BASE \ - (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) -#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) -#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) -#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) +#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 +#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE +#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) +#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) +#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) +#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) /* 8042 */ -#define MCHP_8042_ECREGS_OFS 0x100 -#define MCHP_8042_GIRQ 15 -#define MCHP_8042_OBE_GIRQ_BIT BIT(18) -#define MCHP_8042_IBF_GIRQ_BIT BIT(19) +#define MCHP_8042_ECREGS_OFS 0x100 +#define MCHP_8042_GIRQ 15 +#define MCHP_8042_OBE_GIRQ_BIT BIT(18) +#define MCHP_8042_IBF_GIRQ_BIT BIT(19) /* * I2C controllers 0 - 4 include SMBus network layer functionality. * I2C controllers 5 - 7 are I2C only and include slave mode * promiscuous functionality. */ -#define MCHP_I2C_CTRL0 0 -#define MCHP_I2C_CTRL1 1 -#define MCHP_I2C_CTRL2 2 -#define MCHP_I2C_CTRL3 3 -#define MCHP_I2C_CTRL4 4 -#define MCHP_I2C_CTRL5 5 -#define MCHP_I2C_CTRL6 6 -#define MCHP_I2C_CTRL7 7 -#define MCHP_I2C_CTRL_MAX 8 - -#define MCHP_I2C_SEP0 0x400 -#define MCHP_I2C_SEP1 0x100 +#define MCHP_I2C_CTRL0 0 +#define MCHP_I2C_CTRL1 1 +#define MCHP_I2C_CTRL2 2 +#define MCHP_I2C_CTRL3 3 +#define MCHP_I2C_CTRL4 4 +#define MCHP_I2C_CTRL5 5 +#define MCHP_I2C_CTRL6 6 +#define MCHP_I2C_CTRL7 7 +#define MCHP_I2C_CTRL_MAX 8 + +#define MCHP_I2C_SEP0 0x400 +#define MCHP_I2C_SEP1 0x100 /* * MEC152xH 144-pin package has eight I2C controllers and sixteen ports. @@ -1038,10 +1020,10 @@ * I2C15_SCL/SDA on GPIO0150 F1, GPIO0147 F1 */ -#define MCHP_MEC1521SZ_I2C_PORT_MASK 0xFEFFul -#define MCHP_MEC1523SZ_I2C_PORT_MASK 0xFFFFul +#define MCHP_MEC1521SZ_I2C_PORT_MASK 0xFEFFul +#define MCHP_MEC1523SZ_I2C_PORT_MASK 0xFFFFul -#define MCHP_I2C_PORT_MASK MCHP_MEC1521SZ_I2C_PORT_MASK +#define MCHP_I2C_PORT_MASK MCHP_MEC1521SZ_I2C_PORT_MASK enum MCHP_i2c_port { MCHP_I2C_PORT0 = 0, @@ -1064,8 +1046,8 @@ enum MCHP_i2c_port { }; /* I2C ports & Configs */ -#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX -#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT +#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX +#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT /* * I2C controllers 0-4 implement network layer hardware. @@ -1073,167 +1055,164 @@ enum MCHP_i2c_port { * MEC152x has I2C promiscuous mode feature in the following * additional registers. */ -#define MCHP_I2C_SLAVE_ADDR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x6c)) -#define MCHP_I2C_PROM_INTR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x70)) -#define MCHP_I2C_PROM_INTR_EN(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x74)) -#define MCHP_I2C_PROM_CTRL(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x78)) +#define MCHP_I2C_SLAVE_ADDR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x6c)) +#define MCHP_I2C_PROM_INTR(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x70)) +#define MCHP_I2C_PROM_INTR_EN(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x74)) +#define MCHP_I2C_PROM_CTRL(ctrl) REG32(MCHP_I2C_ADDR(ctrl, 0x78)) /* All I2C controllers connected to GIRQ13 */ -#define MCHP_I2C_GIRQ 13 +#define MCHP_I2C_GIRQ 13 /* I2C[0:7] -> GIRQ13 bits[0:7] */ -#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) +#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) /* Keyboard scan matrix */ -#define MCHP_KS_GIRQ 21 -#define MCHP_KS_GIRQ_BIT BIT(25) -#define MCHP_KS_DIRECT_NVIC 135 +#define MCHP_KS_GIRQ 21 +#define MCHP_KS_GIRQ_BIT BIT(25) +#define MCHP_KS_DIRECT_NVIC 135 /* ADC */ -#define MCHP_ADC_GIRQ 17 -#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) -#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) -#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 -#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 +#define MCHP_ADC_GIRQ 17 +#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) +#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) +#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 +#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 /* Hibernation timer */ -#define MCHP_HTIMER_SPACING 0x20 -#define MCHP_HTIMER_ADDR(n) \ - (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING)) -#define MCHP_HTIMER_GIRQ 23 +#define MCHP_HTIMER_SPACING 0x20 +#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING)) +#define MCHP_HTIMER_GIRQ 23 /* HTIMER[0:1] -> GIRQ23 bits[16:17] */ -#define MCHP_HTIMER_GIRQ_BIT(n) BIT(16 + (n)) -#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) +#define MCHP_HTIMER_GIRQ_BIT(n) BIT(16 + (n)) +#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) /* * Quad Master SPI (QMSPI) * MEC152x implements 16 descriptors, support for two chip selects, * and additional SPI signal timing registers. */ -#define MCHP_QMSPI_MAX_DESCR 16 +#define MCHP_QMSPI_MAX_DESCR 16 /* * Chip select implemented in bit[13:12] of the Mode register. * These bits are reserved in earlier chips. */ -#define MCHP_QMSPI_M_CS_POS 12 -#define MCHP_QMSPI_M_CS_MASK0 0x03 -#define MCHP_QMSPI_M_CS_MASK (0x03 << MCHP_QMSPI_M_CS_POS) -#define MCHP_QMSPI_M_CS0 (0x00 << MCHP_QMSPI_M_CS_POS) -#define MCHP_QMSPI_M_CS1 (0x01 << MCHP_QMSPI_M_CS_POS) +#define MCHP_QMSPI_M_CS_POS 12 +#define MCHP_QMSPI_M_CS_MASK0 0x03 +#define MCHP_QMSPI_M_CS_MASK (0x03 << MCHP_QMSPI_M_CS_POS) +#define MCHP_QMSPI_M_CS0 (0x00 << MCHP_QMSPI_M_CS_POS) +#define MCHP_QMSPI_M_CS1 (0x01 << MCHP_QMSPI_M_CS_POS) /* New QMSPI chip select timing register */ -#define MCHP_QMSPI_CS_TIMING \ - REG32(MCHP_QMSPI0_BASE + 0x28) -#define MCHP_QMSPI_CST_DFLT_VAL 0x06060406 -#define MCHP_QMSPI_CST_ON2CLK_MASK 0x0f -#define MCHP_QMSPI_CST_ON2CLK_DFLT 0x06 -#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS 8 -#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0 0x0f -#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK 0x0f00 -#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT 0x0400 -#define MCHP_QMSPI_CST_DLY_LDH_POS 16 -#define MCHP_QMSPI_CST_DLY_LDH_MASK0 0x0f -#define MCHP_QMSPI_CST_DLY_LDH_MASK 0xf0000 -#define MCHP_QMSPI_CST_DLY_LDH_DFLT 0x60000 -#define MCHP_QMSPI_CST_DLY_OFF2ON_POS 24 -#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT 0x06000000 -#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0 0xff -#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK 0xff000000 - -#define MCHP_QMSPI_GIRQ 18 -#define MCHP_QMSPI_GIRQ_BIT BIT(1) -#define MCHP_QMSPI_DIRECT_NVIC 91 +#define MCHP_QMSPI_CS_TIMING REG32(MCHP_QMSPI0_BASE + 0x28) +#define MCHP_QMSPI_CST_DFLT_VAL 0x06060406 +#define MCHP_QMSPI_CST_ON2CLK_MASK 0x0f +#define MCHP_QMSPI_CST_ON2CLK_DFLT 0x06 +#define MCHP_QMSPI_CST_DLY_CLK2OFF_POS 8 +#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK0 0x0f +#define MCHP_QMSPI_CST_DLY_CLK2OFF_MASK 0x0f00 +#define MCHP_QMSPI_CST_DLY_CLK2OFF_DFLT 0x0400 +#define MCHP_QMSPI_CST_DLY_LDH_POS 16 +#define MCHP_QMSPI_CST_DLY_LDH_MASK0 0x0f +#define MCHP_QMSPI_CST_DLY_LDH_MASK 0xf0000 +#define MCHP_QMSPI_CST_DLY_LDH_DFLT 0x60000 +#define MCHP_QMSPI_CST_DLY_OFF2ON_POS 24 +#define MCHP_QMSPI_CST_DLY_OFF2ON_DFLT 0x06000000 +#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK0 0xff +#define MCHP_QMSPI_CST_DLY_OFF2ON_MASK 0xff000000 + +#define MCHP_QMSPI_GIRQ 18 +#define MCHP_QMSPI_GIRQ_BIT BIT(1) +#define MCHP_QMSPI_DIRECT_NVIC 91 /* eSPI */ /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */ -#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 -#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 -#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 -#define MCHP_ESPI_IO_BAR_ID_8042 3 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 -#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 -#define MCHP_ESPI_IO_BAR_ID_P92 0xA -#define MCHP_ESPI_IO_BAR_ID_UART0 0xB -#define MCHP_ESPI_IO_BAR_ID_UART1 0xC -#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD -#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE -#define MCHP_ESPI_IO_BAR_P80_0 0x10 -#define MCHP_ESPI_IO_BAR_P80_1 0x11 -#define MCHP_ESPI_IO_BAR_RTC 0x12 -#define MCHP_ESPI_IO_BAR_ID_UART2 0x15 +#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 +#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 +#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 +#define MCHP_ESPI_IO_BAR_ID_8042 3 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 +#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 +#define MCHP_ESPI_IO_BAR_ID_P92 0xA +#define MCHP_ESPI_IO_BAR_ID_UART0 0xB +#define MCHP_ESPI_IO_BAR_ID_UART1 0xC +#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD +#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE +#define MCHP_ESPI_IO_BAR_P80_0 0x10 +#define MCHP_ESPI_IO_BAR_P80_1 0x11 +#define MCHP_ESPI_IO_BAR_RTC 0x12 +#define MCHP_ESPI_IO_BAR_ID_UART2 0x15 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */ -#define MCHP_ESPI_MBAR_ID_MBOX 0 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 -#define MCHP_ESPI_MBAR_ID_EMI_0 6 -#define MCHP_ESPI_MBAR_ID_EMI_1 7 +#define MCHP_ESPI_MBAR_ID_MBOX 0 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 +#define MCHP_ESPI_MBAR_ID_EMI_0 6 +#define MCHP_ESPI_MBAR_ID_EMI_1 7 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */ -#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ -#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ -#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ -#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ -#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 -#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 -#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 -#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 -#define MCHP_ESPI_SIRQ_UART0 9 -#define MCHP_ESPI_SIRQ_UART1 10 -#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ -#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ -#define MCHP_ESPI_SIRQ_EMI1_HEV 13 -#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 -#define MCHP_ESPI_SIRQ_RTC 17 -#define MCHP_ESPI_SIRQ_EC 18 -#define MCHP_ESPI_SIRQ_UART2 19 - -#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE) -#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul) +#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ +#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ +#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ +#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ +#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 +#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 +#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 +#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 +#define MCHP_ESPI_SIRQ_UART0 9 +#define MCHP_ESPI_SIRQ_UART1 10 +#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ +#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ +#define MCHP_ESPI_SIRQ_EMI1_HEV 13 +#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 +#define MCHP_ESPI_SIRQ_RTC 17 +#define MCHP_ESPI_SIRQ_EC 18 +#define MCHP_ESPI_SIRQ_UART2 19 + +#define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE) +#define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul) /* * eSPI RESET, channel enables and operations except Master-to-Slave * WWires are all on GIRQ19 */ -#define MCHP_ESPI_GIRQ 19 -#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) -#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) -#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) -#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) -#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) -#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) -#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) -#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) -#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) -#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) -#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) +#define MCHP_ESPI_GIRQ 19 +#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) +#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) +#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) +#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) +#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) +#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) +#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) +#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) +#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) +#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) +#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) /* * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */ -#define MCHP_ESPI_MSVW_0_6_GIRQ 24 -#define MCHP_ESPI_MSVW_7_10_GIRQ 25 +#define MCHP_ESPI_MSVW_0_6_GIRQ 24 +#define MCHP_ESPI_MSVW_7_10_GIRQ 25 /* * Four source bits, SRC[0:3] per Master-to-Slave register * v = MSVW [0:10] * n = VWire SRC bit = [0:3] */ -#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0)) +#define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0)) #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \ - (((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n)))) - + (((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n)))) /* DMA */ -#define MCHP_DMA_MAX_CHAN 12 -#define MCHP_DMA_CH_OFS 0x40 -#define MCHP_DMA_CH_OFS_BITPOS 6 -#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS) +#define MCHP_DMA_MAX_CHAN 12 +#define MCHP_DMA_CH_OFS 0x40 +#define MCHP_DMA_CH_OFS_BITPOS 6 +#define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS) /* * Available DMA channels. @@ -1263,18 +1242,18 @@ enum dma_channel { * Peripheral device DMA Device ID's for bits [15:9] * in DMA channel control register. */ -#define MCHP_DMA_I2C0_SLV_REQ_ID 0 -#define MCHP_DMA_I2C0_MTR_REQ_ID 1 -#define MCHP_DMA_I2C1_SLV_REQ_ID 2 -#define MCHP_DMA_I2C1_MTR_REQ_ID 3 -#define MCHP_DMA_I2C2_SLV_REQ_ID 4 -#define MCHP_DMA_I2C2_MTR_REQ_ID 5 -#define MCHP_DMA_I2C3_SLV_REQ_ID 6 -#define MCHP_DMA_I2C3_MTR_REQ_ID 7 -#define MCHP_DMA_I2C4_SLV_REQ_ID 8 -#define MCHP_DMA_I2C4_MTR_REQ_ID 9 -#define MCHP_DMA_QMSPI0_TX_REQ_ID 10 -#define MCHP_DMA_QMSPI0_RX_REQ_ID 11 +#define MCHP_DMA_I2C0_SLV_REQ_ID 0 +#define MCHP_DMA_I2C0_MTR_REQ_ID 1 +#define MCHP_DMA_I2C1_SLV_REQ_ID 2 +#define MCHP_DMA_I2C1_MTR_REQ_ID 3 +#define MCHP_DMA_I2C2_SLV_REQ_ID 4 +#define MCHP_DMA_I2C2_MTR_REQ_ID 5 +#define MCHP_DMA_I2C3_SLV_REQ_ID 6 +#define MCHP_DMA_I2C3_MTR_REQ_ID 7 +#define MCHP_DMA_I2C4_SLV_REQ_ID 8 +#define MCHP_DMA_I2C4_MTR_REQ_ID 9 +#define MCHP_DMA_QMSPI0_TX_REQ_ID 10 +#define MCHP_DMA_QMSPI0_RX_REQ_ID 11 /* * Hardware delay register. @@ -1283,7 +1262,7 @@ enum dma_channel { * serviced during the delay period. Reads have * no effect. */ -#define MCHP_USEC_DELAY_REG_ADDR 0x10000000 -#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x)) +#define MCHP_USEC_DELAY_REG_ADDR 0x10000000 +#define MCHP_USEC_DELAY(x) (REG8(MCHP_USEC_DELAY_REG_ADDR) = (x)) #endif /* #ifndef __ASSEMBLER__ */ -- cgit v1.2.1 From e667020f519ce5c1ecf53f536863adf7675cea4f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:43 -0600 Subject: power/falconlite.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic12e46ce9ef5964c0c72a22abe8067249cab1ee2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727059 Reviewed-by: Jeremy Bettis --- power/falconlite.c | 142 ++++++++++++++++++++--------------------------------- 1 file changed, 54 insertions(+), 88 deletions(-) diff --git a/power/falconlite.c b/power/falconlite.c index b418edfd84..ce03fbbf31 100644 --- a/power/falconlite.c +++ b/power/falconlite.c @@ -29,7 +29,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Long power key press to force shutdown in S0. go/crosdebug */ #define FORCED_SHUTDOWN_DELAY (8 * SECOND) @@ -39,61 +39,35 @@ #define SYS_RST_PULSE_LENGTH (30 * MSEC) /* Masks for power signals */ -#define IN_PG_S5 POWER_SIGNAL_MASK(FCL_PG_S5) -#define IN_PGOOD (POWER_SIGNAL_MASK(FCL_PG_VDD1_VDD2) | \ - POWER_SIGNAL_MASK(FCL_PG_VDD_MEDIA_ML) | \ - POWER_SIGNAL_MASK(FCL_PG_VDD_SOC) | \ - POWER_SIGNAL_MASK(FCL_PG_VDD_DDR_OD) | \ - POWER_SIGNAL_MASK(FCL_PG_S5)) +#define IN_PG_S5 POWER_SIGNAL_MASK(FCL_PG_S5) +#define IN_PGOOD \ + (POWER_SIGNAL_MASK(FCL_PG_VDD1_VDD2) | \ + POWER_SIGNAL_MASK(FCL_PG_VDD_MEDIA_ML) | \ + POWER_SIGNAL_MASK(FCL_PG_VDD_SOC) | \ + POWER_SIGNAL_MASK(FCL_PG_VDD_DDR_OD) | POWER_SIGNAL_MASK(FCL_PG_S5)) -#define IN_ALL_S0 IN_PGOOD -#define IN_ALL_S3 IN_PGOOD +#define IN_ALL_S0 IN_PGOOD +#define IN_ALL_S3 IN_PGOOD /* Power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - [FCL_AP_WARM_RST_REQ] = { - GPIO_AP_EC_WARM_RST_REQ, - POWER_SIGNAL_ACTIVE_HIGH, - "AP_WARM_RST_REQ" - }, - [FCL_AP_SHUTDOWN_REQ] = { - GPIO_AP_EC_SHUTDOWN_REQ_L, - POWER_SIGNAL_ACTIVE_LOW, - "AP_SHUTDOWN_REQ" - }, - [FCL_AP_WATCHDOG] = { - GPIO_AP_EC_WATCHDOG_L, - POWER_SIGNAL_ACTIVE_LOW, - "AP_WDT" - }, - [FCL_PG_S5] = { - GPIO_PG_S5_PWR_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PG_S5" - }, - [FCL_PG_VDD1_VDD2] = { - GPIO_PG_VDD1_VDD2_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PG_VDD1_VDD2" - }, - [FCL_PG_VDD_MEDIA_ML] = { - GPIO_PG_VDD_MEDIA_ML_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PG_VDD_MEDIA_ML" - }, - [FCL_PG_VDD_SOC] = { - GPIO_PG_VDD_SOC_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PG_VDD_SOC" - }, - [FCL_PG_VDD_DDR_OD] = { - GPIO_PG_VDD_DDR_OD, - POWER_SIGNAL_ACTIVE_HIGH, - "PG_VDD_DDR" - }, + [FCL_AP_WARM_RST_REQ] = { GPIO_AP_EC_WARM_RST_REQ, + POWER_SIGNAL_ACTIVE_HIGH, "AP_WARM_RST_REQ" }, + [FCL_AP_SHUTDOWN_REQ] = { GPIO_AP_EC_SHUTDOWN_REQ_L, + POWER_SIGNAL_ACTIVE_LOW, "AP_SHUTDOWN_REQ" }, + [FCL_AP_WATCHDOG] = { GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, + "AP_WDT" }, + [FCL_PG_S5] = { GPIO_PG_S5_PWR_OD, POWER_SIGNAL_ACTIVE_HIGH, "PG_S5" }, + [FCL_PG_VDD1_VDD2] = { GPIO_PG_VDD1_VDD2_OD, POWER_SIGNAL_ACTIVE_HIGH, + "PG_VDD1_VDD2" }, + [FCL_PG_VDD_MEDIA_ML] = { GPIO_PG_VDD_MEDIA_ML_OD, + POWER_SIGNAL_ACTIVE_HIGH, "PG_VDD_MEDIA_ML" }, + [FCL_PG_VDD_SOC] = { GPIO_PG_VDD_SOC_OD, POWER_SIGNAL_ACTIVE_HIGH, + "PG_VDD_SOC" }, + [FCL_PG_VDD_DDR_OD] = { GPIO_PG_VDD_DDR_OD, POWER_SIGNAL_ACTIVE_HIGH, + "PG_VDD_DDR" }, }; - /* Data structure for a GPIO operation for power sequencing */ struct power_seq_op { enum gpio_signal signal; @@ -109,70 +83,63 @@ struct power_seq_op { /* The power sequence for POWER_S3S5 */ static const struct power_seq_op s3s5_power_seq[] = { - {GPIO_EN_VDD_CPU, 0, 0}, - {GPIO_EN_VDD_GPU, 0, 0}, - {GPIO_EN_VDD_MEDIA_ML, 0, 4}, + { GPIO_EN_VDD_CPU, 0, 0 }, { GPIO_EN_VDD_GPU, 0, 0 }, + { GPIO_EN_VDD_MEDIA_ML, 0, 4 }, - {GPIO_EN_VDDQ_VR_D, 0, 4}, /* LPDDR */ + { GPIO_EN_VDDQ_VR_D, 0, 4 }, /* LPDDR */ - {GPIO_EN_VDD1_VDD2_VR, 0, 4}, /* LPDDR */ + { GPIO_EN_VDD1_VDD2_VR, 0, 4 }, /* LPDDR */ - {GPIO_EN_VDD_DDR, 0, 4}, + { GPIO_EN_VDD_DDR, 0, 4 }, - {GPIO_EN_PP3300A_IO_X, 0, 0}, - {GPIO_EN_PP3300_S3, 0, 4}, + { GPIO_EN_PP3300A_IO_X, 0, 0 }, { GPIO_EN_PP3300_S3, 0, 4 }, - {GPIO_EN_PP1820A_IO_X, 0, 0}, - {GPIO_EN_PP1800_S3, 0, 0}, + { GPIO_EN_PP1820A_IO_X, 0, 0 }, { GPIO_EN_PP1800_S3, 0, 0 }, }; /* The power sequence for POWER_G3S5 */ static const struct power_seq_op g3s5_power_seq[] = { /* delay 10ms as PP1800_S5 uses PP1800_S5 as alaternative supply */ - {GPIO_EN_PP5000_S5, 1, 10}, + { GPIO_EN_PP5000_S5, 1, 10 }, - {GPIO_EN_PP1800_S5, 1, 0}, + { GPIO_EN_PP1800_S5, 1, 0 }, - {GPIO_EN_PP1800_VDDIO_PMC_X, 1, 4}, + { GPIO_EN_PP1800_VDDIO_PMC_X, 1, 4 }, - {GPIO_EN_PP0800_VDD_PMC_X, 1, 0}, - {GPIO_EN_VDD_SOC, 1, 4}, + { GPIO_EN_PP0800_VDD_PMC_X, 1, 0 }, { GPIO_EN_VDD_SOC, 1, 4 }, - {GPIO_EN_PP1800_VDD33_PMC_X, 1, 0}, + { GPIO_EN_PP1800_VDD33_PMC_X, 1, 0 }, }; /* This is the power sequence for POWER_S5S3. */ static const struct power_seq_op s5s3_power_seq[] = { - {GPIO_EN_PP1800_S3, 1, 0}, - {GPIO_EN_PP1820A_IO_X, 1, 4}, + { GPIO_EN_PP1800_S3, 1, 0 }, { GPIO_EN_PP1820A_IO_X, 1, 4 }, - {GPIO_EN_PP3300_S3, 1, 0}, - {GPIO_EN_PP3300A_IO_X, 1, 4}, + { GPIO_EN_PP3300_S3, 1, 0 }, { GPIO_EN_PP3300A_IO_X, 1, 4 }, - {GPIO_EN_VDD_DDR, 1, 4}, + { GPIO_EN_VDD_DDR, 1, 4 }, - {GPIO_EN_VDD1_VDD2_VR, 1, 4}, /* LPDDR */ + { GPIO_EN_VDD1_VDD2_VR, 1, 4 }, /* LPDDR */ - {GPIO_EN_VDDQ_VR_D, 1, 4}, /* LPDDR */ + { GPIO_EN_VDDQ_VR_D, 1, 4 }, /* LPDDR */ - {GPIO_EN_VDD_MEDIA_ML, 1, 0}, - {GPIO_EN_VDD_GPU, 1, 0}, - {GPIO_EN_VDD_CPU, 1, 0}, + { GPIO_EN_VDD_MEDIA_ML, 1, 0 }, { GPIO_EN_VDD_GPU, 1, 0 }, + { GPIO_EN_VDD_CPU, 1, 0 }, }; /* The power sequence for POWER_S5G3 */ static const struct power_seq_op s5g3_power_seq[] = { - {GPIO_EN_PP1800_VDD33_PMC_X, 0, 4}, + { GPIO_EN_PP1800_VDD33_PMC_X, 0, 4 }, - {GPIO_EN_VDD_SOC, 0, 0}, + { GPIO_EN_VDD_SOC, 0, 0 }, - {GPIO_EN_PP0800_VDD_PMC_X, 0, 4}, + { GPIO_EN_PP0800_VDD_PMC_X, 0, 4 }, - {GPIO_EN_PP1800_VDDIO_PMC_X, 0, 4}, + { GPIO_EN_PP1800_VDDIO_PMC_X, 0, 4 }, - {GPIO_EN_PP1800_S5, 0, 4}, + { GPIO_EN_PP1800_S5, 0, 4 }, - {GPIO_EN_PP5000_S5, 0, 4}, + { GPIO_EN_PP5000_S5, 0, 4 }, }; /* most recently received sleep event */ @@ -265,7 +232,7 @@ enum power_state power_chipset_init(void) } else if (reset_flags & EC_RESET_FLAG_AP_OFF) { exit_hard_off = 0; } else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) && - gpio_get_level(GPIO_AC_PRESENT)) { + gpio_get_level(GPIO_AC_PRESENT)) { /* * If AC present, assume this is a wake-up by AC insert. * Boot EC only. @@ -324,8 +291,7 @@ static void power_seq_run(const struct power_seq_op *power_seq_ops, int i; for (i = 0; i < op_count; i++) { - GPIO_SET_LEVEL(power_seq_ops[i].signal, - power_seq_ops[i].level); + GPIO_SET_LEVEL(power_seq_ops[i].signal, power_seq_ops[i].level); if (!power_seq_ops[i].delay) continue; msleep(power_seq_ops[i].delay); @@ -491,9 +457,9 @@ static void power_button_changed(void) DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT); #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { CPRINTS("Handle sleep: %d", state); -- cgit v1.2.1 From 648bf92676ef3074efa437d6583be8d77c76f4e1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:48 -0600 Subject: board/fizz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id346678eb05b369b5f60a1d68db95ff1a32674c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728368 Reviewed-by: Jeremy Bettis --- board/fizz/led.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/fizz/led.c b/board/fizz/led.c index 9b6942d241..3b67ce894e 100644 --- a/board/fizz/led.c +++ b/board/fizz/led.c @@ -15,7 +15,7 @@ #include "timer.h" #include "util.h" -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -76,9 +76,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From 437e24ec02fa278bc5847ae98b66f6fd14881b4a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:51 -0600 Subject: board/stryke/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6296d6d806834a20677f23e5bc938ca11a21f168 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728973 Reviewed-by: Jeremy Bettis --- board/stryke/board.h | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/board/stryke/board.h b/board/stryke/board.h index 205c3bbd4a..ee49ade1f8 100644 --- a/board/stryke/board.h +++ b/board/stryke/board.h @@ -100,16 +100,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -121,8 +121,8 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ ADC_CH_COUNT }; @@ -133,11 +133,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, @@ -151,11 +147,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From c15a6d491698a0408d41ed39a1642d67b5fa5d52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:45 -0600 Subject: board/hammer/variants.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0497ff84acdafd2b54827dc51b5adf9c4e713df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728317 Reviewed-by: Jeremy Bettis --- board/hammer/variants.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/board/hammer/variants.h b/board/hammer/variants.h index 71e70f5758..3f0993d645 100644 --- a/board/hammer/variants.h +++ b/board/hammer/variants.h @@ -55,7 +55,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 566 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (48 * 1024) #elif defined(BOARD_BLAND) #define CONFIG_USB_HID_KEYBOARD_VIVALDI #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10 @@ -65,7 +65,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_DON) #define HAS_I2C_TOUCHPAD #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925 @@ -73,7 +73,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024) #elif defined(BOARD_DUCK) #define CONFIG_USB_HID_KEYBOARD_VIVALDI #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10 @@ -83,7 +83,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_EEL) #define CONFIG_USB_HID_KEYBOARD_VIVALDI #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10 @@ -93,7 +93,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_GELATIN) #define CONFIG_USB_HID_KEYBOARD_VIVALDI #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10 @@ -104,7 +104,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_MAGNEMITE) #define HAS_NO_TOUCHPAD #elif defined(BOARD_MASTERBALL) @@ -114,7 +114,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 839 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_MOONBALL) #define HAS_I2C_TOUCHPAD #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 2925 @@ -122,7 +122,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 929 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 457 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024) #elif defined(BOARD_STAFF) #define HAS_I2C_TOUCHPAD #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X 3206 @@ -130,7 +130,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1018 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 582 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (56 * 1024) #elif defined(BOARD_STAR) #define CONFIG_USB_HID_KEYBOARD_VIVALDI #define CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS 10 @@ -140,7 +140,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1042 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 569 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #elif defined(BOARD_WHISKERS) #define HAS_SPI_TOUCHPAD #define HAS_EN_PP3300_TP_ACTIVE_HIGH @@ -149,7 +149,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 255 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1031 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 751 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (CONFIG_UPDATE_PDU_SIZE + 128 * 1024) /* Enable to send heatmap to AP */ #define CONFIG_USB_ISOCHRONOUS #elif defined(BOARD_ZED) @@ -163,7 +163,7 @@ #define CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE 511 #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X 1060 /* tenth of mm */ #define CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y 575 /* tenth of mm */ -#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64*1024) +#define CONFIG_TOUCHPAD_VIRTUAL_SIZE (64 * 1024) #else #error "No touchpad information for board." #endif @@ -175,8 +175,8 @@ #endif /* Backlight */ -#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || \ - defined(BOARD_WAND) || defined(BOARD_WHISKERS) +#if defined(BOARD_HAMMER) || defined(BOARD_STAFF) || defined(BOARD_WAND) || \ + defined(BOARD_WHISKERS) /* * Even with this option, we detect the backlight presence using a PU/PD on the * PWM pin. Not defining this totally disables support. @@ -196,9 +196,9 @@ #endif /* BOARD_HAMMER/WAND/WHISKERS */ /* GMR sensor for tablet mode detection */ -#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) || \ - defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \ - defined(BOARD_EEL) +#if defined(BOARD_DON) || defined(BOARD_MASTERBALL) || \ + defined(BOARD_MOONBALL) || defined(BOARD_WHISKERS) || \ + defined(BOARD_EEL) #define CONFIG_GMR_TABLET_MODE #endif -- cgit v1.2.1 From 830e98929c02f06b461983491e7d2e3d662557f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:51 -0600 Subject: board/brask/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I348d00d42e86092008169ebdcb2f9155da12b5ac Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728040 Reviewed-by: Jeremy Bettis --- board/brask/board.c | 75 +++++++++++++++++++++++++++-------------------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/board/brask/board.c b/board/brask/board.c index 7b22e37e29..ee0db446c4 100644 --- a/board/brask/board.c +++ b/board/brask/board.c @@ -27,8 +27,8 @@ #include "fw_config.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -140,21 +140,21 @@ static int32_t base_5v_power_z1; */ /* PP5000_S5 loads */ -#define PWR_S5_BASE_LOAD (5*1431) -#define PWR_S5_FRONT_HIGH (5*1737) -#define PWR_S5_FRONT_LOW (5*1055) -#define PWR_S5_REAR_HIGH (5*1737) -#define PWR_S5_REAR_LOW (5*1055) -#define PWR_S5_HDMI (5*580) -#define PWR_S5_MAX (5*10000) -#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW) -#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW) +#define PWR_S5_BASE_LOAD (5 * 1431) +#define PWR_S5_FRONT_HIGH (5 * 1737) +#define PWR_S5_FRONT_LOW (5 * 1055) +#define PWR_S5_REAR_HIGH (5 * 1737) +#define PWR_S5_REAR_LOW (5 * 1055) +#define PWR_S5_HDMI (5 * 580) +#define PWR_S5_MAX (5 * 10000) +#define FRONT_DELTA (PWR_S5_FRONT_HIGH - PWR_S5_FRONT_LOW) +#define REAR_DELTA (PWR_S5_REAR_HIGH - PWR_S5_REAR_LOW) /* PP5000_Z1 loads */ -#define PWR_Z1_BASE_LOAD (5*5) -#define PWR_Z1_C_HIGH (5*3600) -#define PWR_Z1_C_LOW (5*2000) -#define PWR_Z1_MAX (5*9000) +#define PWR_Z1_BASE_LOAD (5 * 5) +#define PWR_Z1_C_HIGH (5 * 3600) +#define PWR_Z1_C_LOW (5 * 2000) +#define PWR_Z1_MAX (5 * 9000) /* * Update the 5V power usage, assuming no throttling, * and invoke the power monitoring. @@ -228,7 +228,7 @@ static void port_ocp_interrupt(enum gpio_signal signal) * only do that if the system is off since it might still brown out. */ -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -328,26 +328,26 @@ void board_overcurrent_event(int port, int is_overcurrented) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A_FRONT BIT(0) -#define THROT_TYPE_A_REAR BIT(1) -#define THROT_TYPE_C0 BIT(2) -#define THROT_TYPE_C1 BIT(3) -#define THROT_TYPE_C2 BIT(4) -#define THROT_PROCHOT BIT(5) +#define THROT_TYPE_A_FRONT BIT(0) +#define THROT_TYPE_A_REAR BIT(1) +#define THROT_TYPE_C0 BIT(2) +#define THROT_TYPE_C1 BIT(3) +#define THROT_TYPE_C2 BIT(4) +#define THROT_PROCHOT BIT(5) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -363,8 +363,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -392,7 +391,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -419,8 +418,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -551,24 +549,27 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C0) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); pd_update_contract(0); } if (diff & THROT_TYPE_C1) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(1, rp); tcpm_select_rp_value(1, rp); pd_update_contract(1); } if (diff & THROT_TYPE_C2) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C2) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(2, rp); tcpm_select_rp_value(2, rp); -- cgit v1.2.1 From 0ab99496aac96603af1213be7fbea1be6ce4ae2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:42 -0600 Subject: include/driver/tcpm/tcpm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8164ca4e4dc817882b2ad48cc9d9bbceb689e54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730254 Reviewed-by: Jeremy Bettis --- include/driver/tcpm/tcpm.h | 99 ++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 52 deletions(-) diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h index ef47a3b1e2..52ddba9e7e 100644 --- a/include/driver/tcpm/tcpm.h +++ b/include/driver/tcpm/tcpm.h @@ -26,26 +26,22 @@ #ifndef CONFIG_USB_PD_TCPC_LOW_POWER static inline int tcpc_addr_write(int port, int i2c_addr, int reg, int val) { - return i2c_write8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_write16(int port, int i2c_addr, int reg, int val) { - return i2c_write16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read(int port, int i2c_addr, int reg, int *val) { - return i2c_read8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) { - return i2c_read16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + return i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); } /* @@ -65,8 +61,8 @@ static inline int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val) * need an explicit by the caller. */ -static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, - int reg, int *val) +static inline int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, + int *val) { return tcpc_addr_read16(port, i2c_addr, reg, val); } @@ -75,49 +71,47 @@ static inline int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, int in_size) { return i2c_xfer(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size); + tcpc_config[port].i2c_info.addr_flags, out, out_size, + in, in_size); } static inline int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) + uint8_t *in, int in_size, int flags) { return i2c_xfer_unlocked(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size, flags); + tcpc_config[port].i2c_info.addr_flags, out, + out_size, in, in_size, flags); } static inline int tcpc_read_block(int port, int reg, uint8_t *in, int size) { return i2c_read_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, in, size); + tcpc_config[port].i2c_info.addr_flags, reg, in, + size); } -static inline int tcpc_write_block(int port, int reg, - const uint8_t *out, int size) +static inline int tcpc_write_block(int port, int reg, const uint8_t *out, + int size) { return i2c_write_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, out, size); + tcpc_config[port].i2c_info.addr_flags, reg, out, + size); } -static inline int tcpc_update8(int port, int reg, - uint8_t mask, +static inline int tcpc_update8(int port, int reg, uint8_t mask, enum mask_update_action action) { return i2c_update8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } -static inline int tcpc_update16(int port, int reg, - uint16_t mask, +static inline int tcpc_update16(int port, int reg, uint16_t mask, enum mask_update_action action) { return i2c_update16(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, mask, action); + tcpc_config[port].i2c_info.addr_flags, reg, mask, + action); } #else /* !CONFIG_USB_PD_TCPC_LOW_POWER */ @@ -128,40 +122,40 @@ int tcpc_addr_read16(int port, int i2c_addr, int reg, int *val); int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val); int tcpc_read_block(int port, int reg, uint8_t *in, int size); int tcpc_write_block(int port, int reg, const uint8_t *out, int size); -int tcpc_xfer(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size); -int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size); +int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags); -int tcpc_update8(int port, int reg, - uint8_t mask, enum mask_update_action action); -int tcpc_update16(int port, int reg, - uint16_t mask, enum mask_update_action action); +int tcpc_update8(int port, int reg, uint8_t mask, + enum mask_update_action action); +int tcpc_update16(int port, int reg, uint16_t mask, + enum mask_update_action action); #endif /* CONFIG_USB_PD_TCPC_LOW_POWER */ static inline int tcpc_write(int port, int reg, int val) { - return tcpc_addr_write(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_write16(int port, int reg, int val) { - return tcpc_addr_write16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_write16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline int tcpc_read(int port, int reg, int *val) { - return tcpc_addr_read(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read(port, tcpc_config[port].i2c_info.addr_flags, reg, + val); } static inline int tcpc_read16(int port, int reg, int *val) { - return tcpc_addr_read16(port, - tcpc_config[port].i2c_info.addr_flags, reg, val); + return tcpc_addr_read16(port, tcpc_config[port].i2c_info.addr_flags, + reg, val); } static inline void tcpc_lock(int port, int lock) @@ -191,7 +185,7 @@ static inline int tcpm_release(int port) } static inline int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { return tcpc_config[port].drv->get_cc(port, cc1, cc2); } @@ -281,7 +275,8 @@ static inline int tcpm_transmit(int port, enum tcpci_msg_type type, static inline bool tcpm_get_snk_ctrl(int port) { return tcpc_config[port].drv->get_snk_ctrl ? - tcpc_config[port].drv->get_snk_ctrl(port) : false; + tcpc_config[port].drv->get_snk_ctrl(port) : + false; } static inline int tcpm_set_snk_ctrl(int port, int enable) { @@ -293,9 +288,9 @@ static inline int tcpm_set_snk_ctrl(int port, int enable) static inline bool tcpm_get_src_ctrl(int port) { - return tcpc_config[port].drv->get_src_ctrl ? - tcpc_config[port].drv->get_src_ctrl(port) : false; + tcpc_config[port].drv->get_src_ctrl(port) : + false; } static inline int tcpm_set_src_ctrl(int port, int enable) { @@ -444,8 +439,8 @@ static inline int tcpm_set_frs_enable(int port, int enable) static inline int tcpc_set_sbu(int port, bool enable) { return tcpc_config[port].drv->set_sbu ? - tcpc_config[port].drv->set_sbu(port, enable) : - EC_SUCCESS; + tcpc_config[port].drv->set_sbu(port, enable) : + EC_SUCCESS; } #endif /* CONFIG_USB_PD_TCPM_SBU */ @@ -470,7 +465,7 @@ int tcpm_init(int port); * @return EC_SUCCESS or error */ int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); /** * Check VBUS level -- cgit v1.2.1 From 80c18857fb16973531739beb29c0b17e0fca1216 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:21 -0600 Subject: board/twinkie/injector.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c3d01abb5a0e9343adb6d69d77cef7e28fdb835 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729039 Reviewed-by: Jeremy Bettis --- board/twinkie/injector.c | 58 +++++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/board/twinkie/injector.c b/board/twinkie/injector.c index ef5bfb3e32..fc55d0d5ef 100644 --- a/board/twinkie/injector.c +++ b/board/twinkie/injector.c @@ -48,20 +48,25 @@ static const struct res_cfg { uint32_t flags; } cfgs[2]; } res_cfg[] = { - [INJ_RES_NONE] = {"NONE"}, - [INJ_RES_RA] = {"RA", {{GPIO_CC1_RA, GPIO_ODR_LOW}, - {GPIO_CC2_RA, GPIO_ODR_LOW} } }, - [INJ_RES_RD] = {"RD", {{GPIO_CC1_RD, GPIO_ODR_LOW}, - {GPIO_CC2_RD, GPIO_ODR_LOW} } }, - [INJ_RES_RPUSB] = {"RPUSB", {{GPIO_CC1_RPUSB, GPIO_OUT_HIGH}, - {GPIO_CC2_RPUSB, GPIO_OUT_HIGH} } }, - [INJ_RES_RP1A5] = {"RP1A5", {{GPIO_CC1_RP1A5, GPIO_OUT_HIGH}, - {GPIO_CC2_RP1A5, GPIO_OUT_HIGH} } }, - [INJ_RES_RP3A0] = {"RP3A0", {{GPIO_CC1_RP3A0, GPIO_OUT_HIGH}, - {GPIO_CC2_RP3A0, GPIO_OUT_HIGH} } }, + [INJ_RES_NONE] = { "NONE" }, + [INJ_RES_RA] = { "RA", + { { GPIO_CC1_RA, GPIO_ODR_LOW }, + { GPIO_CC2_RA, GPIO_ODR_LOW } } }, + [INJ_RES_RD] = { "RD", + { { GPIO_CC1_RD, GPIO_ODR_LOW }, + { GPIO_CC2_RD, GPIO_ODR_LOW } } }, + [INJ_RES_RPUSB] = { "RPUSB", + { { GPIO_CC1_RPUSB, GPIO_OUT_HIGH }, + { GPIO_CC2_RPUSB, GPIO_OUT_HIGH } } }, + [INJ_RES_RP1A5] = { "RP1A5", + { { GPIO_CC1_RP1A5, GPIO_OUT_HIGH }, + { GPIO_CC2_RP1A5, GPIO_OUT_HIGH } } }, + [INJ_RES_RP3A0] = { "RP3A0", + { { GPIO_CC1_RP3A0, GPIO_OUT_HIGH }, + { GPIO_CC2_RP3A0, GPIO_OUT_HIGH } } }, }; -#define CC_RA(cc) (cc < PD_SRC_RD_THRESHOLD) +#define CC_RA(cc) (cc < PD_SRC_RD_THRESHOLD) #define CC_RD(cc) ((cc > PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC)) #define GET_POLARITY(cc1, cc2) (CC_RD(cc2) || CC_RA(cc1)) @@ -103,8 +108,8 @@ static inline void enable_tracing_ifneeded(int flag) pd_rx_enable_monitoring(0); } -static int send_message(int polarity, uint16_t header, - uint8_t cnt, const uint32_t *data) +static int send_message(int polarity, uint16_t header, uint8_t cnt, + const uint32_t *data) { int bit_len; @@ -215,7 +220,7 @@ static void fsm_wait(uint32_t w) uint32_t timeout_ms = INJ_ARG0(w); uint32_t min_edges = INJ_ARG12(w); - wait_packet(inj_polarity, min_edges, timeout_ms * 1000); + wait_packet(inj_polarity, min_edges, timeout_ms * 1000); #endif } @@ -224,7 +229,7 @@ static void fsm_expect(uint32_t w) uint32_t timeout_ms = INJ_ARG0(w); uint8_t cmd = INJ_ARG2(w); - expect_packet(inj_polarity, cmd, timeout_ms * 1000); + expect_packet(inj_polarity, cmd, timeout_ms * 1000); } static void fsm_get(uint32_t w) { @@ -242,11 +247,11 @@ static void fsm_get(uint32_t w) break; case INJ_GET_VBUS: *store_ptr = (ina2xx_get_voltage(0) & 0xffff) | - ((ina2xx_get_current(0) & 0xffff) << 16); + ((ina2xx_get_current(0) & 0xffff) << 16); break; case INJ_GET_VCONN: *store_ptr = (ina2xx_get_voltage(1) & 0xffff) | - ((ina2xx_get_current(1) & 0xffff) << 16); + ((ina2xx_get_current(1) & 0xffff) << 16); break; case INJ_GET_POLARITY: *store_ptr = inj_polarity; @@ -375,7 +380,6 @@ static int cmd_fsm(int argc, char **argv) return EC_SUCCESS; } - static int cmd_send(int argc, char **argv) { int pol, cnt, i; @@ -396,7 +400,7 @@ static int cmd_send(int argc, char **argv) return EC_ERROR_PARAM3; for (i = 0; i < cnt; i++) - if (hex8tou32(argv[i+2], data + i)) + if (hex8tou32(argv[i + 2], data + i)) return EC_ERROR_INVAL; bit_len = send_message(pol, header, cnt, data); @@ -407,8 +411,8 @@ static int cmd_send(int argc, char **argv) static int cmd_cc_level(int argc, char **argv) { - ccprintf("CC1 = %d mV ; CC2 = %d mV\n", - pd_adc_read(0, 0), pd_adc_read(0, 1)); + ccprintf("CC1 = %d mV ; CC2 = %d mV\n", pd_adc_read(0, 0), + pd_adc_read(0, 1)); return EC_SUCCESS; } @@ -483,7 +487,7 @@ static int cmd_ina_dump(int argc, char **argv, int index) } ccprintf("%s = %d mV ; %d mA\n", index == 0 ? "VBUS" : "VCONN", - ina2xx_get_voltage(index), ina2xx_get_current(index)); + ina2xx_get_voltage(index), ina2xx_get_current(index)); if (index == 1) /* power off VCONN INA */ ina2xx_write(index, INA2XX_REG_CONFIG, 0); @@ -505,7 +509,7 @@ static int cmd_bufwr(int argc, char **argv) return EC_ERROR_PARAM2; for (i = 0; i < cnt; i++) - if (hex8tou32(argv[i+1], inj_cmds + idx + i)) + if (hex8tou32(argv[i + 1], inj_cmds + idx + i)) return EC_ERROR_INVAL; return EC_SUCCESS; @@ -553,13 +557,11 @@ static int cmd_trace(int argc, char **argv) if (argc < 1) return EC_ERROR_PARAM_COUNT; - if (!strcasecmp(argv[0], "on") || - !strcasecmp(argv[0], "1")) + if (!strcasecmp(argv[0], "on") || !strcasecmp(argv[0], "1")) set_trace_mode(TRACE_MODE_ON); else if (!strcasecmp(argv[0], "raw")) set_trace_mode(TRACE_MODE_RAW); - else if (!strcasecmp(argv[0], "off") || - !strcasecmp(argv[0], "0")) + else if (!strcasecmp(argv[0], "off") || !strcasecmp(argv[0], "0")) set_trace_mode(TRACE_MODE_OFF); else return EC_ERROR_PARAM2; -- cgit v1.2.1 From 2aff5617ff80063a83d471b0ad47d3563a003205 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:02 -0600 Subject: chip/npcx/ps2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70c934216276edf9aeaec287077e0fa160b888e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727022 Reviewed-by: Jeremy Bettis --- chip/npcx/ps2.c | 61 +++++++++++++++++++++++++-------------------------------- 1 file changed, 27 insertions(+), 34 deletions(-) diff --git a/chip/npcx/ps2.c b/chip/npcx/ps2.c index 13a1ff6d57..02c1190980 100644 --- a/chip/npcx/ps2.c +++ b/chip/npcx/ps2.c @@ -16,25 +16,25 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_PS2, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_PS2, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PS2, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_PS2, format, ##args) #if !(DEBUG_PS2) #define DEBUG_CPRINTS(...) #define DEBUG_CPRINTF(...) #else -#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ## args) -#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ## args) +#define DEBUG_CPRINTS(format, args...) cprints(CC_PS2, format, ##args) +#define DEBUG_CPRINTF(format, args...) cprintf(CC_PS2, format, ##args) #endif /* * Set WDAT3-0 and clear CLK3-0 in the PSOSIG register to * reset the shift mechanism. */ -#define PS2_SHIFT_MECH_RESET 0x47 +#define PS2_SHIFT_MECH_RESET 0x47 -#define PS2_TRANSACTION_TIMEOUT (20 * MSEC) -#define PS2_BUSY_RETRY 10 +#define PS2_TRANSACTION_TIMEOUT (20 * MSEC) +#define PS2_BUSY_RETRY 10 enum ps2_input_debounce_cycle { PS2_IDB_1_CYCLE, @@ -60,7 +60,7 @@ struct ps2_data { void (*rx_handler_cb)(uint8_t data); }; static struct ps2_data ps2_ch_data[NPCX_PS2_CH_COUNT] = { - [0 ... (NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL } + [0 ...(NPCX_PS2_CH_COUNT - 1)] = { PS2_RX_MODE, NULL } }; /* @@ -76,7 +76,7 @@ static void ps2_init(void) { /* Disable the power down bit of PS/2 */ clock_enable_peripheral(CGC_OFFSET_PS2, CGC_PS2_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Disable shift mechanism and configure PS/2 to received mode. */ NPCX_PS2_PSCON = 0x0; @@ -90,10 +90,9 @@ static void ps2_init(void) * [4] - : WUE = 1: Wake-Up Enable * [7] - : CLK_SEL = 1: Select Free-Run clock as the basic clock */ - NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | - BIT(NPCX_PS2_PSIEN_EOTIE) | - BIT(NPCX_PS2_PSIEN_PS2_WUE) | - BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL); + NPCX_PS2_PSIEN = BIT(NPCX_PS2_PSIEN_SOTIE) | BIT(NPCX_PS2_PSIEN_EOTIE) | + BIT(NPCX_PS2_PSIEN_PS2_WUE) | + BIT(NPCX_PS2_PSIEN_PS2_CLK_SEL); /* Enable weak internal pull-up */ SET_BIT(NPCX_PS2_PSCON, NPCX_PS2_PSCON_WPUED); @@ -106,8 +105,7 @@ static void ps2_init(void) } DECLARE_HOOK(HOOK_INIT, ps2_init, HOOK_PRIO_DEFAULT); -void ps2_enable_channel(int channel, int enable, - void (*callback)(uint8_t data)) +void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data)) { if (channel >= NPCX_PS2_CH_COUNT) { CPRINTS("Err:PS/2 CH exceed %d", NPCX_PS2_CH_COUNT); @@ -125,7 +123,7 @@ void ps2_enable_channel(int channel, int enable, /* Enable the relevant channel clock */ SET_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel)); } else { - channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel)); + channel_enabled_mask &= ~BIT(NPCX_PS2_PSOSIG_CLK(channel)); /* Disable the relevant channel clock */ CLEAR_BIT(NPCX_PS2_PSOSIG, NPCX_PS2_PSOSIG_CLK(channel)); ps2_ch_data[channel].rx_handler_cb = NULL; @@ -144,7 +142,9 @@ static int ps2_is_busy(void) * (due to Shift Mechanism is reset) */ return (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) | - IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? 1 : 0; + IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) ? + 1 : + 0; } int ps2_transmit_byte(int channel, uint8_t data) @@ -194,7 +194,7 @@ int ps2_transmit_byte(int channel, uint8_t data) /* Wait for interrupt */ event = task_wait_event_mask(TASK_EVENT_PS2_DONE, - PS2_TRANSACTION_TIMEOUT); + PS2_TRANSACTION_TIMEOUT); task_waiting = TASK_ID_INVALID; if (event == TASK_EVENT_TIMER) { @@ -216,7 +216,6 @@ int ps2_transmit_byte(int channel, uint8_t data) DEBUG_CPRINTF("Evt:0x%08x\n", event); return (event == TASK_EVENT_PS2_DONE) ? EC_SUCCESS : EC_ERROR_TIMEOUT; - } static void ps2_stop_inactive_ch_clk(uint8_t active_ch) @@ -224,20 +223,17 @@ static void ps2_stop_inactive_ch_clk(uint8_t active_ch) uint8_t mask; mask = ~NPCX_PS2_PSOSIG_CLK_MASK_ALL | - BIT(NPCX_PS2_PSOSIG_CLK(active_ch)); + BIT(NPCX_PS2_PSOSIG_CLK(active_ch)); NPCX_PS2_PSOSIG &= mask; - } static int ps2_is_rx_error(uint8_t ch) { - uint8_t status; + uint8_t status; status = NPCX_PS2_PSTAT & - (BIT(NPCX_PS2_PSTAT_PERR) | - BIT(NPCX_PS2_PSTAT_RFERR)); + (BIT(NPCX_PS2_PSTAT_PERR) | BIT(NPCX_PS2_PSTAT_RFERR)); if (status) { - if (status & BIT(NPCX_PS2_PSTAT_PERR)) CPRINTF("PS2 CH %d RX parity error\n", ch); if (status & BIT(NPCX_PS2_PSTAT_RFERR)) @@ -270,7 +266,7 @@ static void ps2_int_handler(void) /* PS/2 Start of Transaction */ if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_SOT) && - IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) { + IS_BIT_SET(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE)) { DEBUG_CPRINTF("SOT-"); /* * Once set, SOT is not cleared until the shift mechanism @@ -278,7 +274,7 @@ static void ps2_int_handler(void) * first occurrence of an SOT interrupt. */ CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_SOTIE); - /* PS/2 End of Transaction */ + /* PS/2 End of Transaction */ } else if (IS_BIT_SET(NPCX_PS2_PSTAT, NPCX_PS2_PSTAT_EOT)) { DEBUG_CPRINTF("EOT-"); CLEAR_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE); @@ -298,7 +294,7 @@ static void ps2_int_handler(void) if (!ps2_is_rx_error(active_ch)) { uint8_t data_read = NPCX_PS2_PSDAT; struct ps2_data *ps2_ptr = - &ps2_ch_data[active_ch]; + &ps2_ch_data[active_ch]; DEBUG_CPRINTF("Recv:0x%02x", data_read); if (ps2_ptr->rx_handler_cb) @@ -316,7 +312,6 @@ static void ps2_int_handler(void) SET_BIT(NPCX_PS2_PSIEN, NPCX_PS2_PSIEN_EOTIE); } DEBUG_CPRINTF("\n"); - } DECLARE_IRQ(NPCX_IRQ_PS2, ps2_int_handler, 5); @@ -341,8 +336,7 @@ static int command_ps2ench(int argc, char **argv) return 0; } -DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, - "ps2_ench channel 1|0", +DECLARE_CONSOLE_COMMAND(ps2ench, command_ps2ench, "ps2_ench channel 1|0", "Enable/Disable PS/2 channel"); static int command_ps2write(int argc, char **argv) @@ -360,7 +354,6 @@ static int command_ps2write(int argc, char **argv) ps2_transmit_byte(ch, data); return 0; } -DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, - "ps2_write channel data", - "Write data byte to PS/2 channel "); +DECLARE_CONSOLE_COMMAND(ps2write, command_ps2write, "ps2_write channel data", + "Write data byte to PS/2 channel "); #endif -- cgit v1.2.1 From b73e930d6eb7b46e44189329dfd2be856f8f2f52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:16 -0600 Subject: include/cros_board_info.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I90be72f81b330591623ff433bb534564ff29f805 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730235 Reviewed-by: Jeremy Bettis --- include/cros_board_info.h | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/include/cros_board_info.h b/include/cros_board_info.h index 9ed5e1777b..aed845393f 100644 --- a/include/cros_board_info.h +++ b/include/cros_board_info.h @@ -10,21 +10,22 @@ #include "common.h" #include "ec_commands.h" -#define CBI_VERSION_MAJOR 0 -#define CBI_VERSION_MINOR 0 +#define CBI_VERSION_MAJOR 0 +#define CBI_VERSION_MINOR 0 #ifdef CONFIG_CBI_GPIO /* * if CBI is sourced from GPIO, the CBI cache only needs to accomondate * BOARD_VERSION and SKU_ID */ -#define CBI_IMAGE_SIZE (sizeof(struct cbi_header) + (2 * \ - (sizeof(struct cbi_data) + sizeof(uint32_t)))) +#define CBI_IMAGE_SIZE \ + (sizeof(struct cbi_header) + \ + (2 * (sizeof(struct cbi_data) + sizeof(uint32_t)))) #else -#define CBI_IMAGE_SIZE 256 +#define CBI_IMAGE_SIZE 256 #endif -static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */ +static const uint8_t cbi_magic[] = { 0x43, 0x42, 0x49 }; /* 'C' 'B' 'I' */ struct cbi_header { uint8_t magic[3]; @@ -47,9 +48,9 @@ struct cbi_header { } __attribute__((packed)); struct cbi_data { - uint8_t tag; /* enum cbi_data_tag */ - uint8_t size; /* size of value[] */ - uint8_t value[]; /* data value */ + uint8_t tag; /* enum cbi_data_tag */ + uint8_t size; /* size of value[] */ + uint8_t value[]; /* data value */ } __attribute__((packed)); enum cbi_cache_status { @@ -143,8 +144,8 @@ uint8_t cbi_crc8(const struct cbi_header *h); * @return Address of the byte following the stored data in the * destination buffer */ -uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, - const void *buf, int size); +uint8_t *cbi_set_data(uint8_t *p, enum cbi_data_tag tag, const void *buf, + int size); /** * Store string data in memory in CBI data format. -- cgit v1.2.1 From 365c092210856c1b2199da8b10ae4828cb99e654 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:14 -0600 Subject: zephyr/shim/include/usbc/bb_retimer_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2595e322e1d1bd52e759df4591c8b4a7f7ddab97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730832 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/bb_retimer_usb_mux.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/include/usbc/bb_retimer_usb_mux.h b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h index 611c52e081..fb3f4ee68d 100644 --- a/zephyr/shim/include/usbc/bb_retimer_usb_mux.h +++ b/zephyr/shim/include/usbc/bb_retimer_usb_mux.h @@ -10,13 +10,13 @@ #define BB_RETIMER_USB_MUX_COMPAT intel_jhl8040r -#define USB_MUX_CONFIG_BB_RETIMER(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &bb_usb_retimer, \ - .hpd_update = bb_retimer_hpd_update, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_BB_RETIMER(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &bb_usb_retimer, \ + .hpd_update = bb_retimer_hpd_update, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = DT_PROP(mux_id, i2c_addr_flags), \ } #define BB_RETIMER_CONTROLS_CONFIG(mux_id, port_id, idx) \ -- cgit v1.2.1 From 4d2e3ee910972044cd1c37c966ed02ecaa281472 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:55 -0600 Subject: zephyr/projects/trogdor/lazor/src/switchcap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8f4d074e96ea12f3027ff70b42c03ba69adb7b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730809 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/switchcap.c | 43 +++++++++++---------------- 1 file changed, 17 insertions(+), 26 deletions(-) diff --git a/zephyr/projects/trogdor/lazor/src/switchcap.c b/zephyr/projects/trogdor/lazor/src/switchcap.c index 6dc7c3fbab..38616a21b8 100644 --- a/zephyr/projects/trogdor/lazor/src/switchcap.c +++ b/zephyr/projects/trogdor/lazor/src/switchcap.c @@ -16,8 +16,8 @@ #include "system.h" #include "sku.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /* LN9310 switchcap */ const struct ln9310_config_t ln9310_config = { @@ -34,18 +34,16 @@ static void switchcap_init(void) * When the chip in power down mode, it outputs high-Z. * Set pull-down to avoid floating. */ - gpio_pin_configure_dt( - GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0), - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0), + GPIO_INPUT | GPIO_PULL_DOWN); /* * Configure DA9313 enable, push-pull output. Don't set the * level here; otherwise, it will override its value and * shutdown the switchcap when sysjump to RW. */ - gpio_pin_configure_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), - GPIO_OUTPUT); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + GPIO_OUTPUT); } else if (board_has_ln9310()) { CPRINTS("Use switchcap: LN9310"); @@ -71,9 +69,8 @@ static void switchcap_init(void) * (6) GPIO init according to gpio.inc -> push-pull LOW * (7) This function configures it -> open-drain LOW */ - gpio_pin_configure_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), - GPIO_OUTPUT | GPIO_OPEN_DRAIN); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + GPIO_OUTPUT | GPIO_OPEN_DRAIN); /* Only configure the switchcap if not sysjump */ if (!system_jumped_late()) { @@ -83,8 +80,7 @@ static void switchcap_init(void) * configured from standby mode to switching mode. */ gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), - 0); + GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), 0); ln9310_init(); } } else if (board_has_buck_ic()) { @@ -98,18 +94,14 @@ DECLARE_HOOK(HOOK_INIT, switchcap_init, HOOK_PRIO_DEFAULT); void board_set_switchcap_power(int enable) { if (board_has_da9313()) { - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), - enable); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + enable); } else if (board_has_ln9310()) { - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), - enable); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_switchcap_on), + enable); ln9310_software_enable(enable); } else if (board_has_buck_ic()) { - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_vbob_en), - enable); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en), enable); } } @@ -117,18 +109,17 @@ int board_is_switchcap_enabled(void) { if (board_has_da9313() || board_has_ln9310()) return gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_switchcap_on)); + GPIO_DT_FROM_NODELABEL(gpio_switchcap_on)); /* Board has buck ic*/ - return gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_vbob_en)); + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_vbob_en)); } int board_is_switchcap_power_good(void) { if (board_has_da9313()) return gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0)); + GPIO_DT_FROM_NODELABEL(gpio_da9313_gpio0)); else if (board_has_ln9310()) return ln9310_power_good(); -- cgit v1.2.1 From 80550e6e6c03b23d821765202ae618d017808469 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:11 -0600 Subject: zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1093c90191167eeaa523ad35a741dbb0d98dbe88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730772 Reviewed-by: Jeremy Bettis --- .../intelrvp/adlrvp/include/adlrvp_zephyr.h | 28 ++++++++++------------ 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h index 0061b11110..2b0b3993ce 100644 --- a/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h +++ b/zephyr/projects/intelrvp/adlrvp/include/adlrvp_zephyr.h @@ -10,27 +10,25 @@ #include "config.h" +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 - -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 - +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) #define CONFIG_BATTERY_TYPE_NO_AUTO_DETECT -- cgit v1.2.1 From 6da96aee1432d49246d3be4f0127a38bc024a545 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:38 -0600 Subject: common/pd_log.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1e79d5cc2b97f01fc57bff6ec5a7c7756cdc1d4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729682 Reviewed-by: Jeremy Bettis --- common/pd_log.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/common/pd_log.c b/common/pd_log.c index 3708aad72e..9a9e21f420 100644 --- a/common/pd_log.c +++ b/common/pd_log.c @@ -21,8 +21,7 @@ BUILD_ASSERT(PD_LOG_SIZE_MASK == EVENT_LOG_SIZE_MASK); BUILD_ASSERT(PD_LOG_TIMESTAMP_SHIFT == EVENT_LOG_TIMESTAMP_SHIFT); BUILD_ASSERT(PD_EVENT_NO_ENTRY == EVENT_LOG_NO_ENTRY); -void pd_log_event(uint8_t type, uint8_t size_port, - uint16_t data, void *payload) +void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, void *payload) { uint32_t timestamp = get_time().val >> PD_LOG_TIMESTAMP_SHIFT; @@ -48,8 +47,8 @@ void pd_log_recv_vdm(int port, int cnt, uint32_t *payload) return; if (r->type != PD_EVENT_NO_ENTRY) { - timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT) - - r->timestamp; + timestamp = (get_time().val >> PD_LOG_TIMESTAMP_SHIFT) - + r->timestamp; log_add_event(r->type, size_port, r->data, r->payload, timestamp); /* record that we have enqueued new content */ @@ -84,8 +83,7 @@ dequeue_retry: return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY, - hc_pd_get_log_entry, +DECLARE_HOST_COMMAND(EC_CMD_PD_GET_LOG_ENTRY, hc_pd_get_log_entry, EC_VER_MASK(0)); static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args) @@ -117,8 +115,7 @@ static enum ec_status hc_pd_write_log_entry(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY, - hc_pd_write_log_entry, +DECLARE_HOST_COMMAND(EC_CMD_PD_WRITE_LOG_ENTRY, hc_pd_write_log_entry, EC_VER_MASK(0)); #else /* !HAS_TASK_HOSTCMD */ /* we are a PD accessory, send back the events as a VDM (VDO_CMD_GET_LOG) */ -- cgit v1.2.1 From 65adf2b05b8a7f5ac57309b6537190ab884416ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:30 -0600 Subject: test/motion_angle_tablet.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idbd2c8d4c833ae9996f8a40026bd8172cab871c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730527 Reviewed-by: Jeremy Bettis --- test/motion_angle_tablet.c | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/test/motion_angle_tablet.c b/test/motion_angle_tablet.c index 8eea053405..1265a973f7 100644 --- a/test/motion_angle_tablet.c +++ b/test/motion_angle_tablet.c @@ -19,25 +19,24 @@ #include "test_util.h" #include "util.h" - /*****************************************************************************/ /* Test utilities */ /* convert array value from g to m.s^2. */ int filler(const struct motion_sensor_t *s, const float v) { - return FP_TO_INT( fp_div( - FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR, - fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G))); + return FP_TO_INT( + fp_div(FLOAT_TO_FP(v) * MOTION_SCALING_FACTOR, + fp_mul(INT_TO_FP(s->current_range), MOTION_ONE_G))); } static int test_lid_angle_less180(void) { int index = 0, lid_angle; - struct motion_sensor_t *lid = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_LID]; - struct motion_sensor_t *base = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_BASE]; + struct motion_sensor_t *lid = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID]; + struct motion_sensor_t *base = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE]; /* We don't have TASK_CHIP so simulate init ourselves */ hook_notify(HOOK_CHIPSET_SHUTDOWN); @@ -61,18 +60,17 @@ static int test_lid_angle_less180(void) /* Check we stay in tablet mode, even when hinge is vertical. */ while (index < kAccelerometerVerticalHingeTestDataLength) { - feed_accel_data(kAccelerometerVerticalHingeTestData, - &index, filler); + feed_accel_data(kAccelerometerVerticalHingeTestData, &index, + filler); wait_for_valid_sample(); lid_angle = motion_lid_get_angle(); cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d", - index / TEST_LID_SAMPLE_SIZE, - lid->xyz[X], lid->xyz[Y], lid->xyz[Z], - base->xyz[X], base->xyz[Y], base->xyz[Z], - lid_angle); + index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y], + lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z], + lid_angle); /* We need few sample to debounce and enter laptop mode. */ - TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE * \ - (TABLET_MODE_DEBOUNCE_COUNT + 2) || + TEST_ASSERT(index < 2 * TEST_LID_SAMPLE_SIZE * + (TABLET_MODE_DEBOUNCE_COUNT + 2) || tablet_get_mode()); } /* @@ -86,19 +84,17 @@ static int test_lid_angle_less180(void) wait_for_valid_sample(); lid_angle = motion_lid_get_angle(); cprints(CC_ACCEL, "%d : LID(%d, %d, %d)/BASE(%d, %d, %d): %d", - index / TEST_LID_SAMPLE_SIZE, - lid->xyz[X], lid->xyz[Y], lid->xyz[Z], - base->xyz[X], base->xyz[Y], base->xyz[Z], - lid_angle); + index / TEST_LID_SAMPLE_SIZE, lid->xyz[X], lid->xyz[Y], + lid->xyz[Z], base->xyz[X], base->xyz[Y], base->xyz[Z], + lid_angle); /* We need few sample to debounce and enter laptop mode. */ TEST_ASSERT(index < TEST_LID_SAMPLE_SIZE * - (TABLET_MODE_DEBOUNCE_COUNT + 2) || + (TABLET_MODE_DEBOUNCE_COUNT + 2) || tablet_get_mode()); } return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 75162933e83d6624a6e15b3b79ee8b739e50f604 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:41 -0600 Subject: board/mrbland/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3428ee2c015ae1ca7f71f03d656e9f01f3f5476f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728705 Reviewed-by: Jeremy Bettis --- board/mrbland/board.c | 137 ++++++++++++++++++-------------------------------- 1 file changed, 49 insertions(+), 88 deletions(-) diff --git a/board/mrbland/board.c b/board/mrbland/board.c index dd56bcd0cc..6b2ec41a7b 100644 --- a/board/mrbland/board.c +++ b/board/mrbland/board.c @@ -39,10 +39,10 @@ #include "task.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -107,34 +107,26 @@ static void switchcap_interrupt(enum gpio_signal signal) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -142,45 +134,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, /* Base detection */ - [ADC_BASE_DET] = { - "BASE_DET", - NPCX_ADC_CH5, - ADC_MAX_VOLT, - ADC_READ_MAX + 1, - 0 - }, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -198,11 +170,9 @@ const struct ln9310_config_t ln9310_config = { /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -256,17 +226,13 @@ enum lid_accelgyro_type { static enum lid_accelgyro_type lid_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t lid_standard_ref_icm42607 = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_lid_accel = { .name = "Lid Accel", @@ -458,9 +424,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); void board_hibernate(void) { @@ -470,8 +436,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -566,8 +531,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -595,7 +559,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -619,24 +582,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From 7d0368e462971c7a376ecf893dfb5be88a35f229 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:03 -0600 Subject: chip/mchp/clock_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95ab17e58dc488a848bc1b0661bb2fc0ffba4028 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729225 Reviewed-by: Jeremy Bettis --- chip/mchp/clock_chip.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/chip/mchp/clock_chip.h b/chip/mchp/clock_chip.h index 2e7de60358..25f05928ee 100644 --- a/chip/mchp/clock_chip.h +++ b/chip/mchp/clock_chip.h @@ -11,7 +11,6 @@ #include void htimer_init(void); -void system_set_htimer_alarm(uint32_t seconds, - uint32_t microseconds); +void system_set_htimer_alarm(uint32_t seconds, uint32_t microseconds); #endif /* __CROS_EC_I2C_CLOCK_H */ -- cgit v1.2.1 From 4a616aca6bac556f29af2f3b5876a4ee56fe2955 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:08 -0600 Subject: baseboard/kukui/emmc_ite.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a5d98f9ca6aee4c37d3e0ebe1913f36c151c9f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727923 Reviewed-by: Jeremy Bettis --- baseboard/kukui/emmc_ite.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/baseboard/kukui/emmc_ite.c b/baseboard/kukui/emmc_ite.c index b0e1f6b3de..d7441e27cb 100644 --- a/baseboard/kukui/emmc_ite.c +++ b/baseboard/kukui/emmc_ite.c @@ -17,7 +17,7 @@ #include "bootblock_data.h" -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) enum emmc_cmd { EMMC_ERROR = -1, @@ -129,7 +129,7 @@ static void emmc_bootblock_transfer(void) /* Wait for FIFO1 or FIFO2 have been transmitted */ start = __hw_clock_source_read(); while (!(IT83XX_SPI_TXFSR & BIT(0)) && - (__hw_clock_source_read() - start < timeout_us)) + (__hw_clock_source_read() - start < timeout_us)) ; /* Abort an ongoing transfer due to a command is received. */ if (IT83XX_SPI_ISR & IT83XX_SPI_RX_FIFO_FULL) @@ -147,16 +147,16 @@ static enum emmc_cmd emmc_parse_command(int index, uint32_t *cmd0) uint32_t data[3]; data[0] = htobe32(cmd0[index]); - data[1] = htobe32(cmd0[index+1]); - data[2] = htobe32(cmd0[index+2]); + data[1] = htobe32(cmd0[index + 1]); + data[2] = htobe32(cmd0[index + 2]); if ((data[0] & 0xff000000) != 0x40000000) { /* Figure out alignment (cmd starts with 01) */ /* Number of leading ones. */ shift0 = __builtin_clz(~data[0]); - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); + data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0)); + data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0)); } if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { -- cgit v1.2.1 From a790706d9867578d5f6f75b72b01eef1920f58d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:22 -0600 Subject: zephyr/subsys/ap_pwrseq/ap_events.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03106bdb310f962777dae36c7dcf49914221ed0c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730947 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/ap_events.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/zephyr/subsys/ap_pwrseq/ap_events.c b/zephyr/subsys/ap_pwrseq/ap_events.c index d5b78c2c33..8072bae1e7 100644 --- a/zephyr/subsys/ap_pwrseq/ap_events.c +++ b/zephyr/subsys/ap_pwrseq/ap_events.c @@ -71,7 +71,8 @@ void ap_power_ev_send_callbacks(enum ap_power_events event) return; } data.event = event; - SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&callbacks, cb, tmp, node) { + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&callbacks, cb, tmp, node) + { if (cb->events & event) { cb->handler(cb, data); } -- cgit v1.2.1 From e5e5cb167a1783748bb28c9d385fe2c1cedb867e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:57 -0600 Subject: board/vell/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I942c758dd9368fc2c356366db8ca51bd9fa0dfaa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729054 Reviewed-by: Jeremy Bettis --- board/vell/led.c | 67 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/board/vell/led.c b/board/vell/led.c index 4387d1a6d7..611a2ef820 100644 --- a/board/vell/led.c +++ b/board/vell/led.c @@ -22,15 +22,13 @@ #define BATT_LOW_BCT 10 #define LED_TICK_INTERVAL_MS (500 * MSEC) -#define LED_CYCLE_TIME_MS (2000 * MSEC) -#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) -#define LED_ON_TIME_MS (1000 * MSEC) -#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED -}; +#define LED_CYCLE_TIME_MS (2000 * MSEC) +#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1000 * MSEC) +#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -38,13 +36,10 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - RIGHT_PORT = 0, - LEFT_PORT -}; +enum led_port { RIGHT_PORT = 0, LEFT_PORT }; uint8_t bat_led_on; uint8_t bat_led_off; @@ -66,9 +61,9 @@ static void led_set_color_battery(int port, enum led_color color) enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_AMBER_L : - GPIO_LEFT_LED_AMBER_L); + GPIO_LEFT_LED_AMBER_L); white_led = (port == RIGHT_PORT ? GPIO_RIGHT_LED_WHITE_L : - GPIO_LEFT_LED_WHITE_L); + GPIO_LEFT_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -148,10 +143,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -173,31 +168,39 @@ static void led_set_battery(void) */ if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < BATT_LOW_BCT) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { if (charge_get_percent() < BATT_LOW_BCT) - led_set_color_battery(LEFT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + LEFT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(LEFT_PORT, LED_OFF); } break; case PWR_STATE_ERROR: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - led_set_color_battery(RIGHT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { - led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) - ? LED_AMBER : LED_OFF); + led_set_color_battery(LEFT_PORT, (battery_ticks & 0x1) ? + LED_AMBER : + LED_OFF); } break; case PWR_STATE_CHARGE_NEAR_FULL: @@ -205,9 +208,11 @@ static void led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 0d8dc051b49bb6e965537e594ffd7d0939c6137e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:43 -0600 Subject: chip/it83xx/spi_controller.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe7bff3eac1797c8740655d36a64364ff04dc021 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729206 Reviewed-by: Jeremy Bettis --- chip/it83xx/spi_controller.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/it83xx/spi_controller.c b/chip/it83xx/spi_controller.c index d3898deef6..73fa2777e1 100644 --- a/chip/it83xx/spi_controller.c +++ b/chip/it83xx/spi_controller.c @@ -17,7 +17,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) enum sspi_clk_sel { sspi_clk_24mhz = 0, @@ -106,8 +106,8 @@ int spi_enable(const struct spi_device_t *spi_device, int enable) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int idx; uint8_t port = spi_device->port; -- cgit v1.2.1 From 873909eda139f01903f8f5da0bb00f57d9f040c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:22 -0600 Subject: cts/i2c/cts_i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fb83ff8ab75c8f646525b358be195801f702dd8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729760 Reviewed-by: Jeremy Bettis --- cts/i2c/cts_i2c.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/cts/i2c/cts_i2c.h b/cts/i2c/cts_i2c.h index 2914d92a99..c2d5bb707c 100644 --- a/cts/i2c/cts_i2c.h +++ b/cts/i2c/cts_i2c.h @@ -12,9 +12,9 @@ enum cts_i2c_packets { READ32_OFF, }; -#define WRITE8_DATA 0x42 -#define WRITE16_DATA 0x1234 -#define WRITE32_DATA 0xDEADBEEF -#define READ8_DATA 0x23 -#define READ16_DATA 0xACED -#define READ32_DATA 0x01ABCDEF +#define WRITE8_DATA 0x42 +#define WRITE16_DATA 0x1234 +#define WRITE32_DATA 0xDEADBEEF +#define READ8_DATA 0x23 +#define READ16_DATA 0xACED +#define READ32_DATA 0x01ABCDEF -- cgit v1.2.1 From 1e8ff87c557b19ae148eaf18e99741770da32e15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:29 -0600 Subject: common/onewire.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib19fec3db8d9e8488ab4fccf14d683b8cd75db3d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729698 Reviewed-by: Jeremy Bettis --- common/onewire.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/common/onewire.c b/common/onewire.c index cdb5837255..254abffcaa 100644 --- a/common/onewire.c +++ b/common/onewire.c @@ -16,16 +16,18 @@ * Note that these timing are actually _longer_ than legacy 1-wire standard * speed because we're running the 1-wire bus at 3.3V instead of 5V. */ -#define T_RSTL 602 /* Reset low pulse; 600-960 us */ -#define T_MSP 72 /* Presence detect sample time; 70-75 us */ -#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin */ -#define T_SLOT 70 /* Timeslot; >67 us */ -#define T_W0L 63 /* Write 0 low; 62-120 us */ -#define T_W1L 7 /* Write 1 low; 5-15 us */ -#define T_RL 7 /* Read low; 5-15 us */ -#define T_MSR 9 /* Read sample time; <15 us. Must be at least 200 ns after - * T_RL since that's how long the signal takes to be pulled - * up on our board. */ +#define T_RSTL 602 /* Reset low pulse; 600-960 us */ +#define T_MSP 72 /* Presence detect sample time; 70-75 us */ +#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin \ + */ +#define T_SLOT 70 /* Timeslot; >67 us */ +#define T_W0L 63 /* Write 0 low; 62-120 us */ +#define T_W1L 7 /* Write 1 low; 5-15 us */ +#define T_RL 7 /* Read low; 5-15 us */ +#define T_MSR \ + 9 /* Read sample time; <15 us. Must be at least 200 ns after \ + * T_RL since that's how long the signal takes to be pulled \ + * up on our board. */ /** * Output low on the bus for us, then switch back to open-drain input. @@ -98,7 +100,6 @@ static void writebit(int bit) interrupt_enable(); udelay(T_SLOT - T_W0L); } - } int onewire_reset(void) @@ -133,7 +134,7 @@ int onewire_read(void) int i; for (i = 0; i < 8; i++) - data |= readbit() << i; /* LSB first */ + data |= readbit() << i; /* LSB first */ return data; } @@ -143,5 +144,5 @@ void onewire_write(int data) int i; for (i = 0; i < 8; i++) - writebit((data >> i) & 0x01); /* LSB first */ + writebit((data >> i) & 0x01); /* LSB first */ } -- cgit v1.2.1 From bd74a35bbddf680e348e8f58a72716b1adb03806 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:57 -0600 Subject: zephyr/shim/chip/npcx/system_external_storage.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I654e8378e836c78ce520fc0a2464fb352f8dbb43 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730580 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/system_external_storage.c | 67 +++++++++++++------------ 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index 96d13fd94e..f871ad310b 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -26,13 +26,13 @@ static const struct device *mdc_dev = DEVICE_DT_GET(DT_NODELABEL(mdc)); static uint32_t fwctrl_cached = 0xFFFFFFFF; #ifdef CONFIG_SOC_SERIES_NPCX7 -#define NPCX_FWCTRL 0x007 -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 +#define NPCX_FWCTRL 0x007 +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 #elif defined(CONFIG_SOC_SERIES_NPCX9) -#define NPCX_FWCTRL 0x009 -#define NPCX_FWCTRL_RO_REGION 6 -#define NPCX_FWCTRL_FW_SLOT 7 +#define NPCX_FWCTRL 0x009 +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 #else #error "Unsupported NPCX SoC series." #endif @@ -66,28 +66,28 @@ void system_jump_to_booter(void) */ switch (system_get_shrspi_image_copy()) { case EC_IMAGE_RW: - flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF; + flash_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #ifdef CONFIG_RW_B case EC_IMAGE_RW_B: flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF; + CONFIG_RW_B_STORAGE_OFF; flash_used = CONFIG_RW_SIZE; break; #endif case EC_IMAGE_RO: default: /* Jump to RO by default */ - flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_STORAGE_OFF; + flash_offset = + CONFIG_EC_PROTECTED_STORAGE_OFF + CONFIG_RO_STORAGE_OFF; flash_used = CONFIG_RO_SIZE; break; } /* Make sure the reset vector is inside the destination image */ - addr_entry = *(uintptr_t *)(flash_offset + - CONFIG_MAPPED_STORAGE_BASE + 4); + addr_entry = + *(uintptr_t *)(flash_offset + CONFIG_MAPPED_STORAGE_BASE + 4); /* * Speed up FW download time by increasing clock freq of EC. It will @@ -95,29 +95,34 @@ void system_jump_to_booter(void) */ clock_turbo(); -/* - * npcx9 Rev.1 has the problem for download_from_flash API. - * Workwaroud it by executing the system_download_from_flash function - * in the suspend RAM like npcx5. - * TODO: Removing npcx9 when Rev.2 is available. - */ + /* + * npcx9 Rev.1 has the problem for download_from_flash API. + * Workwaroud it by executing the system_download_from_flash function + * in the suspend RAM like npcx5. + * TODO: Removing npcx9 when Rev.2 is available. + */ /* Bypass for GMDA issue of ROM api utilities */ #if defined(CONFIG_SOC_SERIES_NPCX5) || \ defined(CONFIG_PLATFORM_EC_WORKAROUND_FLASH_DOWNLOAD_API) - system_download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - addr_entry /* jump to this address after download */ + system_download_from_flash(flash_offset, /* The offset of the data in + spi flash */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded + data */ + flash_used, /* Number of bytes to download */ + addr_entry /* jump to this address after + download */ ); #else - download_from_flash( - flash_offset, /* The offset of the data in spi flash */ - CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of downloaded data */ - flash_used, /* Number of bytes to download */ - SIGN_NO_CHECK, /* Need CRC check or not */ - addr_entry, /* jump to this address after download */ - &status /* Status fo download */ + download_from_flash(flash_offset, /* The offset of the data in spi flash + */ + CONFIG_PROGRAM_MEMORY_BASE, /* RAM Addr of + downloaded data */ + flash_used, /* Number of bytes to download */ + SIGN_NO_CHECK, /* Need CRC check or not */ + addr_entry, /* jump to this address after download + */ + &status /* Status fo download */ ); #endif } -- cgit v1.2.1 From 53f056b78e75e13d3252186e26e144e735e06412 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:58 -0600 Subject: zephyr/shim/include/power/power.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a0e85d0cfc015e0b33c0481c1e7ad76d4cf324b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730586 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/power/power.h | 84 +++++++++++++-------------------------- 1 file changed, 27 insertions(+), 57 deletions(-) diff --git a/zephyr/shim/include/power/power.h b/zephyr/shim/include/power/power.h index 6ea2444705..c9a7437d4c 100644 --- a/zephyr/shim/include/power/power.h +++ b/zephyr/shim/include/power/power.h @@ -9,75 +9,45 @@ #include #include -#define POWER_SIGNAL_LIST_NODE \ - DT_NODELABEL(power_signal_list) +#define POWER_SIGNAL_LIST_NODE DT_NODELABEL(power_signal_list) -#define SYSTEM_DT_POWER_SIGNAL_CONFIG \ - DT_NODE_EXISTS(POWER_SIGNAL_LIST_NODE) +#define SYSTEM_DT_POWER_SIGNAL_CONFIG DT_NODE_EXISTS(POWER_SIGNAL_LIST_NODE) #if (SYSTEM_DT_POWER_SIGNAL_CONFIG) -#define GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid) \ - DT_STRING_UPPER_TOKEN( \ - DT_PROP( \ - cid, \ - power_gpio_pin \ - ), \ - enum_name \ - ) -#define GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid) \ -( \ - DT_GPIO_FLAGS( \ - DT_PROP( \ - cid, \ - power_gpio_pin \ - ), \ - gpios \ - ) & GPIO_ACTIVE_LOW \ - ? POWER_SIGNAL_ACTIVE_LOW \ - : POWER_SIGNAL_ACTIVE_HIGH \ -) -#define GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) \ - DT_PROP( \ - cid, \ - power_enum_name \ - ) - -#define GEN_POWER_SIGNAL_STRUCT_ENTRY(cid) \ -{ \ - .gpio = GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid), \ - .flags = GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid), \ - .name = GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) \ -} -#define GEN_POWER_SIGNAL_STRUCT(cid) \ - [GEN_POWER_SIGNAL_ENUM_ENTRY(cid)] = \ - GEN_POWER_SIGNAL_STRUCT_ENTRY(cid), - - -#define GEN_POWER_SIGNAL_ENUM_ENTRY(cid) \ - DT_STRING_UPPER_TOKEN( \ - cid, \ - power_enum_name \ - ) -#define GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA(cid) \ - GEN_POWER_SIGNAL_ENUM_ENTRY(cid), +#define GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid) \ + DT_STRING_UPPER_TOKEN(DT_PROP(cid, power_gpio_pin), enum_name) +#define GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid) \ + (DT_GPIO_FLAGS(DT_PROP(cid, power_gpio_pin), gpios) & \ + GPIO_ACTIVE_LOW ? \ + POWER_SIGNAL_ACTIVE_LOW : \ + POWER_SIGNAL_ACTIVE_HIGH) +#define GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) DT_PROP(cid, power_enum_name) + +#define GEN_POWER_SIGNAL_STRUCT_ENTRY(cid) \ + { \ + .gpio = GEN_POWER_SIGNAL_STRUCT_ENTRY_GPIO(cid), \ + .flags = GEN_POWER_SIGNAL_STRUCT_ENTRY_FLAGS(cid), \ + .name = GEN_POWER_SIGNAL_STRUCT_ENTRY_NAME(cid) \ + } +#define GEN_POWER_SIGNAL_STRUCT(cid) \ + [GEN_POWER_SIGNAL_ENUM_ENTRY(cid)] = GEN_POWER_SIGNAL_STRUCT_ENTRY(cid), + +#define GEN_POWER_SIGNAL_ENUM_ENTRY(cid) \ + DT_STRING_UPPER_TOKEN(cid, power_enum_name) +#define GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA(cid) GEN_POWER_SIGNAL_ENUM_ENTRY(cid), enum power_signal { - DT_FOREACH_CHILD( - POWER_SIGNAL_LIST_NODE, - GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA) - POWER_SIGNAL_COUNT + DT_FOREACH_CHILD(POWER_SIGNAL_LIST_NODE, + GEN_POWER_SIGNAL_ENUM_ENTRY_COMMA) POWER_SIGNAL_COUNT }; /* * Verify the number of required power-signals are specified in * the DeviceTree */ -#define POWER_SIGNALS_REQUIRED \ - DT_PROP( \ - POWER_SIGNAL_LIST_NODE, \ - power_signals_required \ - ) +#define POWER_SIGNALS_REQUIRED \ + DT_PROP(POWER_SIGNAL_LIST_NODE, power_signals_required) BUILD_ASSERT(POWER_SIGNALS_REQUIRED == POWER_SIGNAL_COUNT); #endif /* SYSTEM_DT_POWER_SIGNAL_CONFIG */ -- cgit v1.2.1 From 116c09ce6214408256a7efa456484de40473b1b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:15 -0600 Subject: cts/gpio/th.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38c54fc4354490571d83285445cdba5c9c5d890f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729758 Reviewed-by: Jeremy Bettis --- cts/gpio/th.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cts/gpio/th.c b/cts/gpio/th.c index 30f33b21bf..d553ae9df9 100644 --- a/cts/gpio/th.c +++ b/cts/gpio/th.c @@ -47,7 +47,7 @@ enum cts_rc read_high_test(void) { gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW); gpio_set_level(GPIO_OUTPUT_TEST, 1); - msleep(READ_WAIT_TIME_MS*2); + msleep(READ_WAIT_TIME_MS * 2); return CTS_RC_SUCCESS; } @@ -55,14 +55,14 @@ enum cts_rc read_low_test(void) { gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW); gpio_set_level(GPIO_OUTPUT_TEST, 0); - msleep(READ_WAIT_TIME_MS*2); + msleep(READ_WAIT_TIME_MS * 2); return CTS_RC_SUCCESS; } enum cts_rc od_read_high_test(void) { gpio_set_flags(GPIO_INPUT_TEST, GPIO_OUTPUT | GPIO_ODR_LOW); - msleep(READ_WAIT_TIME_MS*2); + msleep(READ_WAIT_TIME_MS * 2); return CTS_RC_SUCCESS; } -- cgit v1.2.1 From b32b9890cc513966e8ab7443a62d2fba82c7c323 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:29 -0600 Subject: driver/ppc/aoz1380.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I071b8eb20a10fac2373de6a286cb8c1b011b6ad3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730024 Reviewed-by: Jeremy Bettis --- driver/ppc/aoz1380.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/driver/ppc/aoz1380.c b/driver/ppc/aoz1380.c index 726f626caf..f207ebbddf 100644 --- a/driver/ppc/aoz1380.c +++ b/driver/ppc/aoz1380.c @@ -22,13 +22,13 @@ #include "usb_pd_tcpc.h" #include "usbc_ppc.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ -#define AOZ1380_FLAGS_SOURCE_ENABLED BIT(0) -#define AOZ1380_FLAGS_SINK_ENABLED BIT(1) +#define AOZ1380_FLAGS_SOURCE_ENABLED BIT(0) +#define AOZ1380_FLAGS_SINK_ENABLED BIT(1) #define AOZ1380_FLAGS_INT_ON_DISCONNECT BIT(2) static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -157,7 +157,6 @@ const struct ppc_drv aoz1380_drv = { .is_sourcing_vbus = &aoz1380_is_sourcing_vbus, .vbus_sink_enable = &aoz1380_vbus_sink_enable, .vbus_source_enable = &aoz1380_vbus_source_enable, - .set_vbus_source_current_limit = - &aoz1380_set_vbus_source_current_limit, + .set_vbus_source_current_limit = &aoz1380_set_vbus_source_current_limit, .interrupt = &aoz1380_interrupt, }; -- cgit v1.2.1 From 7a0cbb54fe880ce48b2be18aee8f619551080893 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:49 -0600 Subject: board/boten/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09774d037bbe47cf4150710cab208153a2a0ca9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728090 Reviewed-by: Jeremy Bettis --- board/boten/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/boten/usb_pd_policy.c b/board/boten/usb_pd_policy.c index 65ee678263..d5aa77fe93 100644 --- a/board/boten/usb_pd_policy.c +++ b/board/boten/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 433e813f2338bc439de9b5c88658e5331296c18e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:48 -0600 Subject: chip/host/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I16617431558488152ac6ec9f9aa92bebd6db8c89 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729153 Reviewed-by: Jeremy Bettis --- chip/host/system.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/chip/host/system.c b/chip/host/system.c index bf63af8bf0..0a362a0ffd 100644 --- a/chip/host/system.c +++ b/chip/host/system.c @@ -44,8 +44,7 @@ static void ramdata_get_persistent(void) FILE *f = get_persistent_storage("ramdata", "rb"); if ((f == NULL) || (fread(__ram_data, RAM_DATA_SIZE, 1, f) != 1)) { - fprintf(stderr, - "No RAM data found. Initializing to 0x00.\n"); + fprintf(stderr, "No RAM data found. Initializing to 0x00.\n"); memset(__ram_data, 0, RAM_DATA_SIZE); return; } @@ -129,14 +128,14 @@ static int load_time(timestamp_t *t) test_mockable struct panic_data *panic_get_data(void) { - return (struct panic_data *) - (__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data)); + return (struct panic_data *)(__ram_data + RAM_DATA_SIZE - + sizeof(struct panic_data)); } test_mockable uintptr_t get_panic_data_start(void) { - return (uintptr_t) - (__ram_data + RAM_DATA_SIZE - sizeof(struct panic_data)); + return (uintptr_t)(__ram_data + RAM_DATA_SIZE - + sizeof(struct panic_data)); } test_mockable void system_reset(int flags) -- cgit v1.2.1 From a173bfb89d67c8841c591e185c6ae5eb847a4189 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:54 -0600 Subject: board/brask/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida954ff325324a159cf4b8cdef3b685b3bec2734 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728041 Reviewed-by: Jeremy Bettis --- board/brask/board.h | 120 ++++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 65 deletions(-) diff --git a/board/brask/board.h b/board/brask/board.h index 1599749a07..ff6cb31878 100644 --- a/board/brask/board.h +++ b/board/brask/board.h @@ -21,11 +21,11 @@ /* HDMI CEC */ #define CONFIG_CEC #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT -#define CEC_GPIO_IN GPIO_HDMI_CEC_IN +#define CEC_GPIO_IN GPIO_HDMI_CEC_IN #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP /* USB Type A Features */ -#define USB_PORT_COUNT 4 +#define USB_PORT_COUNT 4 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -33,7 +33,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_PPC #define CONFIG_USB_PD_TCPM_RT1715 @@ -46,18 +46,18 @@ #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* The design should support up to 100W. */ /* TODO(b/197702356): Set the max PD to 60W now and change it * to 100W after we verify it. */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -65,58 +65,58 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD -#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD +#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD /* I2C Bus Configuration */ -#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 +#define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_QI NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_QI NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x59 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -140,7 +140,7 @@ * TODO(b/197478860): Enable the fan control. We need * to check the sensor value and adjust the fan speed. */ - #define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL @@ -153,7 +153,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -171,7 +171,7 @@ enum adc_channel { ADC_TEMP_SENSOR_3_WIFI, ADC_TEMP_SENSOR_4_DIMM, ADC_VBUS, - ADC_PPVAR_IMON, /* ADC3 */ + ADC_PPVAR_IMON, /* ADC3 */ ADC_CH_COUNT }; @@ -183,28 +183,18 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C2_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT }; enum pwm_channel { - PWM_CH_LED_GREEN, /* PWM0 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED_RED, /* PWM2 */ + PWM_CH_LED_GREEN, /* PWM0 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED_RED, /* PWM2 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; extern void adp_connect_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 773670cbd6129f08b314ce089a61f9b3fe854fdb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:44 -0600 Subject: board/kano/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia779184a32e4cfd8b8d8a396fb020d2ec2a735b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728481 Reviewed-by: Jeremy Bettis --- board/kano/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kano/fans.c b/board/kano/fans.c index b652ec90da..8453dd48bc 100644 --- a/board/kano/fans.c +++ b/board/kano/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 5a4678a38bcbd517f7a3f9ec07c74ea2ba82fc6f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:17 -0600 Subject: chip/npcx/uartn.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic06dde5c6f8798f5e228ba06fa29e5f915ec0fd2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729446 Reviewed-by: Jeremy Bettis --- chip/npcx/uartn.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/npcx/uartn.h b/chip/npcx/uartn.h index e5326f72b8..a0868a3a78 100644 --- a/chip/npcx/uartn.h +++ b/chip/npcx/uartn.h @@ -22,7 +22,7 @@ void uartn_init(uint8_t uart_num); */ void uartn_tx_start(uint8_t uart_num); - /* Disable the UART transmit interrupt. */ +/* Disable the UART transmit interrupt. */ void uartn_tx_stop(uint8_t uart_num, uint8_t sleep_ena); /* Flush the transmit FIFO. */ @@ -62,4 +62,4 @@ void uartn_rx_int_en(uint8_t uart_num); void uartn_wui_en(uint8_t uart_num); /* Enable/disable Tx NXMIP (No Transmit In Progress) interrupt */ void uartn_enable_tx_complete_int(uint8_t uart_num, uint8_t enable); -#endif /* __CROS_EC_UARTN_H */ +#endif /* __CROS_EC_UARTN_H */ -- cgit v1.2.1 From 009ff5ee4ec6d09875be38749e8269e3635b03e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:04 -0600 Subject: fuzz/usb_pd_fuzz.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I874ce723b01c447c44c71ff5dbe6f80ccf851ddd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730196 Reviewed-by: Jeremy Bettis --- fuzz/usb_pd_fuzz.c | 97 ++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 36 deletions(-) diff --git a/fuzz/usb_pd_fuzz.c b/fuzz/usb_pd_fuzz.c index 64eb0913a6..f92c7905ba 100644 --- a/fuzz/usb_pd_fuzz.c +++ b/fuzz/usb_pd_fuzz.c @@ -20,17 +20,26 @@ #define TASK_EVENT_FUZZ TASK_EVENT_CUSTOM_BIT(0) -#define PORT0 0 +#define PORT0 0 -static int mock_tcpm_init(int port) { return EC_SUCCESS; } -static int mock_tcpm_release(int port) { return EC_SUCCESS; } +static int mock_tcpm_init(int port) +{ + return EC_SUCCESS; +} +static int mock_tcpm_release(int port) +{ + return EC_SUCCESS; +} static int mock_tcpm_select_rp_value(int port, int rp) { return EC_SUCCESS; } -static int mock_tcpm_set_cc(int port, int pull) { return EC_SUCCESS; } +static int mock_tcpm_set_cc(int port, int pull) +{ + return EC_SUCCESS; +} static int mock_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) { return EC_SUCCESS; @@ -41,16 +50,28 @@ static __maybe_unused int mock_tcpm_sop_prime_enable(int port, bool enable) return EC_SUCCESS; } -static int mock_tcpm_set_vconn(int port, int enable) { return EC_SUCCESS; } -static int mock_tcpm_set_msg_header(int port, - int power_role, int data_role) { return EC_SUCCESS; } -static int mock_tcpm_set_rx_enable(int port, int enable) { return EC_SUCCESS; } +static int mock_tcpm_set_vconn(int port, int enable) +{ + return EC_SUCCESS; +} +static int mock_tcpm_set_msg_header(int port, int power_role, int data_role) +{ + return EC_SUCCESS; +} +static int mock_tcpm_set_rx_enable(int port, int enable) +{ + return EC_SUCCESS; +} static int mock_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data) -{ return EC_SUCCESS; } -static void mock_tcpc_alert(int port) {} + uint16_t header, const uint32_t *data) +{ + return EC_SUCCESS; +} +static void mock_tcpc_alert(int port) +{ +} static int mock_tcpci_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *info) + struct ec_response_pd_chip_info_v1 *info) { return EC_ERROR_UNIMPLEMENTED; } @@ -76,7 +97,7 @@ struct tcpc_state { static struct tcpc_state mock_tcpc_state[CONFIG_USB_PD_PORT_MAX_COUNT]; static int mock_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { *cc1 = mock_tcpc_state[port].cc1; *cc2 = mock_tcpc_state[port].cc2; @@ -125,31 +146,33 @@ int tcpm_enqueue_message(const int port) return EC_SUCCESS; } -void tcpm_clear_pending_messages(int port) {} +void tcpm_clear_pending_messages(int port) +{ +} static const struct tcpm_drv mock_tcpm_drv = { - .init = &mock_tcpm_init, - .release = &mock_tcpm_release, - .get_cc = &mock_tcpm_get_cc, + .init = &mock_tcpm_init, + .release = &mock_tcpm_release, + .get_cc = &mock_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &mock_tcpm_check_vbus_level, + .check_vbus_level = &mock_tcpm_check_vbus_level, #endif - .select_rp_value = &mock_tcpm_select_rp_value, - .set_cc = &mock_tcpm_set_cc, - .set_polarity = &mock_tcpm_set_polarity, + .select_rp_value = &mock_tcpm_select_rp_value, + .set_cc = &mock_tcpm_set_cc, + .set_polarity = &mock_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &mock_tcpm_sop_prime_enable, + .sop_prime_enable = &mock_tcpm_sop_prime_enable, #endif - .set_vconn = &mock_tcpm_set_vconn, - .set_msg_header = &mock_tcpm_set_msg_header, - .set_rx_enable = &mock_tcpm_set_rx_enable, + .set_vconn = &mock_tcpm_set_vconn, + .set_msg_header = &mock_tcpm_set_msg_header, + .set_rx_enable = &mock_tcpm_set_rx_enable, /* The core calls tcpm_dequeue_message. */ - .get_message_raw = NULL, - .transmit = &mock_tcpm_transmit, - .tcpc_alert = &mock_tcpc_alert, - .get_chip_info = &mock_tcpci_get_chip_info, + .get_message_raw = NULL, + .transmit = &mock_tcpm_transmit, + .tcpc_alert = &mock_tcpc_alert, + .get_chip_info = &mock_tcpci_get_chip_info, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &mock_enter_low_power_mode, + .enter_low_power_mode = &mock_enter_low_power_mode, #endif }; @@ -181,8 +204,8 @@ void run_test(int argc, char **argv) while (1) { task_wait_event_mask(TASK_EVENT_FUZZ, -1); - memset(&mock_tcpc_state[port], - 0, sizeof(mock_tcpc_state[port])); + memset(&mock_tcpc_state[port], 0, + sizeof(mock_tcpc_state[port])); task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_TCPC_RESET); task_wait_event(250 * MSEC); @@ -196,7 +219,7 @@ void run_test(int argc, char **argv) /* Fake RX messages, one by one. */ for (i = 0; i < MAX_MESSAGES && messages[i].cnt; i++) { memcpy(&mock_tcpc_state[port].message, &messages[i], - sizeof(messages[i])); + sizeof(messages[i])); tcpm_enqueue_message(port); task_wait_event(50 * MSEC); @@ -220,21 +243,23 @@ int test_fuzz_one_input(const uint8_t *data, unsigned int size) next_cc1 = data[0] & 0x0f; next_cc2 = (data[0] & 0xf0) >> 4; - data++; size--; + data++; + size--; memset(messages, 0, sizeof(messages)); for (i = 0; i < MAX_MESSAGES && size > 0; i++) { int cnt = data[0]; - if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD+3 || cnt > size) { + if (cnt < 3 || cnt > MAX_TCPC_PAYLOAD + 3 || cnt > size) { /* Invalid count, or out of bounds. */ return 0; } memcpy(&messages[i], data, cnt); - data += cnt; size -= cnt; + data += cnt; + size -= cnt; } if (size != 0) { -- cgit v1.2.1 From 2032b3615204d5991dc68ee420e42bc2b3e00cf3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:48 -0600 Subject: board/hatch/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic611ddd8504aff1219c426a4d857646e0f91b9bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728318 Reviewed-by: Jeremy Bettis --- board/hatch/board.c | 64 ++++++++++++++++++++++++----------------------------- 1 file changed, 29 insertions(+), 35 deletions(-) diff --git a/board/hatch/board.c b/board/hatch/board.c index 1cb3282299..e33a522225 100644 --- a/board/hatch/board.c +++ b/board/hatch/board.c @@ -42,8 +42,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPIO to enable/disable the USB Type-A port. */ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { @@ -109,16 +109,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -220,22 +220,18 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* * TODO(b/124337208): P0 boards don't have this sensor mounted so the rotation * matrix can't be tested properly. This needs to be revisited after EVT to make * sure the rotaiton matrix for the lid sensor is correct. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -359,7 +355,7 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -378,32 +374,31 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Hatch Temperature sensors */ /* * TODO(b/124316213): These setting need to be reviewed and set appropriately @@ -413,8 +408,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -469,7 +464,6 @@ static void board_gpio_set_pp5000(void) } else if (board_id >= 1) { reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW); } - } static void board_init(void) -- cgit v1.2.1 From ac83633c26d1a63e7a8f8c5c6b14b26098025161 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:04 -0600 Subject: board/asurada/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c947329b9498fd48e9b02ff96d13aa0c9d6833a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728012 Reviewed-by: Jeremy Bettis --- board/asurada/led.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/board/asurada/led.c b/board/asurada/led.c index 166ece92e9..6dcf401441 100644 --- a/board/asurada/led.c +++ b/board/asurada/led.c @@ -15,18 +15,16 @@ #include "stdbool.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #define LED_OFF EC_LED_COLOR_COUNT const enum ec_led_id supported_led_ids[] = { /* Main LED */ - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, + EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED, /* Not used, give them some random name for testing */ - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED + EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -85,8 +83,7 @@ static void led_set_color_battery(enum ec_led_colors color, int duty) } static enum ec_error_list set_color(enum ec_led_id led_id, - enum ec_led_colors color, - int duty) + enum ec_led_colors color, int duty) { switch (led_id) { case EC_LED_ID_LEFT_LED: @@ -174,13 +171,11 @@ static void update_led(enum ec_led_id led_id, bool is_active_charge_port, if (chipset_in_state(CHIPSET_STATE_ON)) set_color(led_id, EC_LED_COLOR_WHITE, duty); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - set_color( - led_id, - (tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF, - duty); + set_color(led_id, + (tick % 8 < 6) ? EC_LED_COLOR_AMBER : LED_OFF, + duty); else set_color(led_id, LED_OFF, 0); - } } -- cgit v1.2.1 From 4a1317fa35cf3a301a7c01d1623c1b8bded633fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:23 -0600 Subject: include/mat44.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b817da68876a459a14f9ae7922ce396f2c151be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730350 Reviewed-by: Jeremy Bettis --- include/mat44.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mat44.h b/include/mat44.h index 2faa093c8e..37df6ba2a1 100644 --- a/include/mat44.h +++ b/include/mat44.h @@ -22,4 +22,4 @@ void mat44_fp_swap_rows(mat44_fp_t A, const size_t i, const size_t j); void mat44_fp_solve(mat44_fp_t A, fpv4_t x, const fpv4_t b, const sizev4_t pivot); -#endif /* __CROS_EC_MAT_44_H */ +#endif /* __CROS_EC_MAT_44_H */ -- cgit v1.2.1 From 0fb02aee60c94d4cd8f335f2f37bb2c32d0031da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:19 -0600 Subject: test/usb_pe_drp_old_noextended.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c772a798c2339a80372898663ca14ddb590ca5c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730545 Reviewed-by: Jeremy Bettis --- test/usb_pe_drp_old_noextended.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/test/usb_pe_drp_old_noextended.c b/test/usb_pe_drp_old_noextended.c index cefd77b7d2..ddf6fda897 100644 --- a/test/usb_pe_drp_old_noextended.c +++ b/test/usb_pe_drp_old_noextended.c @@ -62,12 +62,10 @@ bool pd_alt_mode_capable(int port) void pd_set_suspend(int port, int suspend) { - } void pd_set_error_recovery(int port) { - } test_static void setup_source(void) @@ -198,8 +196,8 @@ static int test_snk_give_source_cap(void) TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_MSG_RECEIVED)); TEST_ASSERT(!pe_chk_flag(PORT0, PE_FLAGS_TX_COMPLETE)); - TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0), - PD_DATA_SOURCE_CAP, "%d"); + TEST_EQ(fake_prl_get_last_sent_data_msg_type(PORT0), PD_DATA_SOURCE_CAP, + "%d"); TEST_EQ(get_state_pe(PORT0), PE_DR_SNK_GIVE_SOURCE_CAP, "%d"); pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); @@ -228,9 +226,9 @@ test_static int test_extended_message_not_supported(void) * Receive an extended, non-chunked message; expect a Not Supported * response. */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)) & ~BIT(15); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -240,16 +238,16 @@ test_static int test_extended_message_not_supported(void) pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* * Receive an extended, chunked, single-chunk message; expect a Not * Supported response. */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, PD_MAX_EXTENDED_MSG_CHUNK_LEN); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -259,16 +257,16 @@ test_static int test_extended_message_not_supported(void) pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* * Receive an extended, chunked, multi-chunk message; expect a Not * Supported response after tChunkingNotSupported (not earlier). */ - rx_emsg[PORT0].header = PD_HEADER( - PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, PD_ROLE_UFP, 0, - PDO_MAX_OBJECTS, PD_REV30, 1); + rx_emsg[PORT0].header = PD_HEADER(PD_DATA_BATTERY_STATUS, PD_ROLE_SINK, + PD_ROLE_UFP, 0, PDO_MAX_OBJECTS, + PD_REV30, 1); *(uint16_t *)rx_emsg[PORT0].buf = PD_EXT_HEADER(0, 0, ARRAY_SIZE(rx_emsg[PORT0].buf)); pe_set_flag(PORT0, PE_FLAGS_MSG_RECEIVED); @@ -280,13 +278,13 @@ test_static int test_extended_message_not_supported(void) */ task_wait_event(10 * MSEC); TEST_NE(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); task_wait_event(PD_T_CHUNKING_NOT_SUPPORTED); pe_set_flag(PORT0, PE_FLAGS_TX_COMPLETE); task_wait_event(10 * MSEC); TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_NOT_SUPPORTED, - "%d"); + "%d"); /* At this point, the PE should again be running in PE_SRC_Ready. */ /* @@ -337,8 +335,8 @@ static int test_send_caps_error(void) pe_set_flag(PORT0, PE_FLAGS_PD_CONNECTION); set_state_pe(PORT0, PE_SRC_SEND_CAPABILITIES); task_wait_event(10 * MSEC); - TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), - PD_CTRL_SOFT_RESET, "%d"); + TEST_EQ(fake_prl_get_last_sent_ctrl_msg(PORT0), PD_CTRL_SOFT_RESET, + "%d"); TEST_EQ(get_state_pe(PORT0), PE_SEND_SOFT_RESET, "%d"); return EC_SUCCESS; -- cgit v1.2.1 From 09d6310cb382c5a3803caa55aa541009469d6bce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:58 -0600 Subject: chip/mt_scp/mt818x/memmap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7009e5141c1e52f50ffd927b50d024395328b768 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729341 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/memmap.c | 72 +++++++++++++++++++-------------------------- 1 file changed, 31 insertions(+), 41 deletions(-) diff --git a/chip/mt_scp/mt818x/memmap.c b/chip/mt_scp/mt818x/memmap.c index 6d8f2b0c87..e3b6eed192 100644 --- a/chip/mt_scp/mt818x/memmap.c +++ b/chip/mt_scp/mt818x/memmap.c @@ -34,13 +34,13 @@ #define MAP_INVALID 0xff static const uint8_t addr_map[16] = { - MAP_INVALID, /* 0x0: SRAM */ - MAP_INVALID, /* 0x1: Cached access (see below) */ - 0x4, 0x5, /* 0x2-0x3 */ - MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */ - 0x6, 0x7, 0x8, /* 0x6-0x8 */ - 0x0, 0x1, 0x2, 0x3, /* 0x9-0xc */ - 0x1, 0xa, 0x9 /* 0xd-0xf */ + MAP_INVALID, /* 0x0: SRAM */ + MAP_INVALID, /* 0x1: Cached access (see below) */ + 0x4, 0x5, /* 0x2-0x3 */ + MAP_INVALID, MAP_INVALID, /* 0x4-0x5 (unmapped: registers) */ + 0x6, 0x7, 0x8, /* 0x6-0x8 */ + 0x0, 0x1, 0x2, 0x3, /* 0x9-0xc */ + 0x1, 0xa, 0x9 /* 0xd-0xf */ }; /* @@ -60,16 +60,14 @@ BUILD_ASSERT(CONFIG_DRAM_BASE == CACHE_TRANS_SCP_CACHE_ADDR); static void cpu_invalidate_icache(void) { SCP_CACHE_OP(CACHE_ICACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_ICACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; + SCP_CACHE_OP(CACHE_ICACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; asm volatile("dsb; isb"); } void cpu_invalidate_dcache(void) { SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; + SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; /* Read is necessary to confirm the invalidation finish. */ REG32(CACHE_TRANS_SCP_CACHE_ADDR); asm volatile("dsb;"); @@ -94,11 +92,10 @@ void cpu_invalidate_dcache_range(uintptr_t base, unsigned int length) void cpu_clean_invalidate_dcache(void) { SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_CACHE_FLUSH_ALL_LINES | SCP_CACHE_OP_EN; + SCP_CACHE_OP(CACHE_DCACHE) |= OP_CACHE_FLUSH_ALL_LINES | + SCP_CACHE_OP_EN; SCP_CACHE_OP(CACHE_DCACHE) &= ~SCP_CACHE_OP_OP_MASK; - SCP_CACHE_OP(CACHE_DCACHE) |= - OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; + SCP_CACHE_OP(CACHE_DCACHE) |= OP_INVALIDATE_ALL_LINES | SCP_CACHE_OP_EN; /* Read necessary to confirm the invalidation finish. */ REG32(CACHE_TRANS_SCP_CACHE_ADDR); asm volatile("dsb;"); @@ -137,8 +134,8 @@ static void scp_cache_init(void) * should only be be configured in kernel driver before * laoding the firmware. b/137920815#comment18 */ - SCP_CACHE_CON(c) &= (SCP_CACHE_CON_CACHESIZE_MASK | - SCP_CACHE_CON_WAYEN); + SCP_CACHE_CON(c) &= + (SCP_CACHE_CON_CACHESIZE_MASK | SCP_CACHE_CON_WAYEN); SCP_CACHE_REGION_EN(c) = 0; SCP_CACHE_ENTRY(c, region) = 0; SCP_CACHE_END_ENTRY(c, region) = 0; @@ -164,7 +161,7 @@ static void scp_cache_init(void) /* Disable sleep protect */ SCP_SLP_PROTECT_CFG = SCP_SLP_PROTECT_CFG & - ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN); + ~(P_CACHE_SLP_PROT_EN | D_CACHE_SLP_PROT_EN); /* Enable region 0 for both I-cache and D-cache. */ for (c = 0; c < CACHE_COUNT; c++) { @@ -188,14 +185,14 @@ static void scp_cache_init(void) static int command_cacheinfo(int argc, char **argv) { - const char cache_name[] = {'I', 'D'}; + const char cache_name[] = { 'I', 'D' }; int c; for (c = 0; c < 2; c++) { uint64_t hit = ((uint64_t)SCP_CACHE_HCNT0U(c) << 32) | - SCP_CACHE_HCNT0L(c); + SCP_CACHE_HCNT0L(c); uint64_t access = ((uint64_t)SCP_CACHE_CCNT0U(c) << 32) | - SCP_CACHE_CCNT0L(c); + SCP_CACHE_CCNT0L(c); ccprintf("%ccache hit count: %llu\n", cache_name[c], hit); ccprintf("%ccache access count: %llu\n", cache_name[c], access); @@ -203,8 +200,7 @@ static int command_cacheinfo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(cacheinfo, command_cacheinfo, NULL, "Dump cache info"); void scp_memmap_init(void) @@ -221,11 +217,9 @@ void scp_memmap_init(void) * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 */ - SCP_REMAP_CFG1 = - (uint32_t)addr_map[0x7] << 24 | - (uint32_t)addr_map[0x6] << 16 | - (uint32_t)addr_map[0x3] << 8 | - (uint32_t)addr_map[0x2]; + SCP_REMAP_CFG1 = (uint32_t)addr_map[0x7] << 24 | + (uint32_t)addr_map[0x6] << 16 | + (uint32_t)addr_map[0x3] << 8 | (uint32_t)addr_map[0x2]; /* * SCP_REMAP_CFG2 @@ -234,11 +228,9 @@ void scp_memmap_init(void) * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 */ - SCP_REMAP_CFG2 = - (uint32_t)addr_map[0xb] << 24 | - (uint32_t)addr_map[0xa] << 16 | - (uint32_t)addr_map[0x9] << 8 | - (uint32_t)addr_map[0x8]; + SCP_REMAP_CFG2 = (uint32_t)addr_map[0xb] << 24 | + (uint32_t)addr_map[0xa] << 16 | + (uint32_t)addr_map[0x9] << 8 | (uint32_t)addr_map[0x8]; /* * SCP_REMAP_CFG3 * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd @@ -246,11 +238,9 @@ void scp_memmap_init(void) * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc */ - SCP_REMAP_CFG3 = - (uint32_t)addr_map[0xd] << 28 | - (uint32_t)addr_map[0xf] << 16 | - (uint32_t)addr_map[0xe] << 8 | - (uint32_t)addr_map[0xc]; + SCP_REMAP_CFG3 = (uint32_t)addr_map[0xd] << 28 | + (uint32_t)addr_map[0xf] << 16 | + (uint32_t)addr_map[0xe] << 8 | (uint32_t)addr_map[0xc]; /* Initialize cache remapping. */ scp_cache_init(); @@ -266,7 +256,7 @@ int memmap_ap_to_scp(uintptr_t ap_addr, uintptr_t *scp_addr) continue; *scp_addr = (ap_addr & SCP_REMAP_ADDR_LSB_MASK) | - (i << SCP_REMAP_ADDR_SHIFT); + (i << SCP_REMAP_ADDR_SHIFT); return EC_SUCCESS; } @@ -281,7 +271,7 @@ int memmap_scp_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) return EC_ERROR_INVAL; *ap_addr = (scp_addr & SCP_REMAP_ADDR_LSB_MASK) | - (addr_map[i] << SCP_REMAP_ADDR_SHIFT); + (addr_map[i] << SCP_REMAP_ADDR_SHIFT); return EC_SUCCESS; } @@ -310,7 +300,7 @@ int memmap_scp_cache_to_ap(uintptr_t scp_addr, uintptr_t *ap_addr) uintptr_t lsb; if ((scp_addr & SCP_L1_EXT_ADDR_OTHER_MSB_MASK) != - CACHE_TRANS_SCP_CACHE_ADDR) + CACHE_TRANS_SCP_CACHE_ADDR) return EC_ERROR_INVAL; lsb = scp_addr & SCP_L1_EXT_ADDR_OTHER_LSB_MASK; -- cgit v1.2.1 From 8d98f148c634b891b800586f65fa922d01f3d841 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:35 -0600 Subject: board/cret/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19f1df7315bfb40281479ebf88aa8b3a45dfe0db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728186 Reviewed-by: Jeremy Bettis --- board/cret/battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cret/battery.c b/board/cret/battery.c index ee5def4183..a78ec43836 100644 --- a/board/cret/battery.c +++ b/board/cret/battery.c @@ -638,8 +638,8 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H; int charger_profile_override(struct charge_state_data *curr) { if (chipset_in_state(CHIPSET_STATE_ON)) { - curr->requested_current = MIN(curr->requested_current, - CHARGING_CURRENT_1100MA); + curr->requested_current = + MIN(curr->requested_current, CHARGING_CURRENT_1100MA); } return 0; -- cgit v1.2.1 From 4b06c63451a2d16e8b5d2ee35d81a454ab6b2edc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:05 -0600 Subject: include/button.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I511decfc46f01e326b55f2da8518762c492675d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730217 Reviewed-by: Jeremy Bettis --- include/button.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/button.h b/include/button.h index 30d2969e8c..105dcff12a 100644 --- a/include/button.h +++ b/include/button.h @@ -13,9 +13,8 @@ #include "gpio_signal.h" #include "ec_commands.h" -#define BUTTON_FLAG_ACTIVE_HIGH BIT(0) -#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */ - +#define BUTTON_FLAG_ACTIVE_HIGH BIT(0) +#define BUTTON_FLAG_DISABLED BIT(1) /* Button disabled */ #define BUTTON_DEBOUNCE_US (30 * MSEC) @@ -103,4 +102,4 @@ int button_is_adc_detected(enum gpio_signal gpio); */ int adc_to_physical_value(enum gpio_signal gpio); -#endif /* __CROS_EC_BUTTON_H */ +#endif /* __CROS_EC_BUTTON_H */ -- cgit v1.2.1 From 96f5c6810a35e99e73776c566be2555c06190bf1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:54 -0600 Subject: board/scarlet/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I449527c32a8105cf3c59603acd4f16329b90b30e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728901 Reviewed-by: Jeremy Bettis --- board/scarlet/led.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/board/scarlet/led.c b/board/scarlet/led.c index d327ee46d6..9c1d00ac7b 100644 --- a/board/scarlet/led.c +++ b/board/scarlet/led.c @@ -28,7 +28,7 @@ enum led_color { LED_RED, LED_AMBER, LED_GREEN, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int bat_led_set_color(enum led_color color) @@ -69,13 +69,13 @@ static void scarlet_led_set_battery(void) break; case PWR_STATE_DISCHARGE: if (charge_get_percent() < 3) - bat_led_set_color((battery_second & 1) - ? LED_OFF : LED_AMBER); + bat_led_set_color((battery_second & 1) ? LED_OFF : + LED_AMBER); else if (charge_get_percent() < 10) - bat_led_set_color((battery_second & 3) - ? LED_OFF : LED_AMBER); + bat_led_set_color((battery_second & 3) ? LED_OFF : + LED_AMBER); else if (charge_get_percent() >= BATTERY_LEVEL_NEAR_FULL && - (chflags & CHARGE_FLAG_EXTERNAL_POWER)) + (chflags & CHARGE_FLAG_EXTERNAL_POWER)) bat_led_set_color(LED_GREEN); else bat_led_set_color(LED_OFF); @@ -88,8 +88,8 @@ static void scarlet_led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE. */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - bat_led_set_color( - (battery_second & 0x2) ? LED_GREEN : LED_AMBER); + bat_led_set_color((battery_second & 0x2) ? LED_GREEN : + LED_AMBER); else bat_led_set_color(LED_GREEN); break; @@ -112,10 +112,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_BAT_LED_RED, (brightness[EC_LED_COLOR_RED] != 0) ? - BAT_LED_ON : BAT_LED_OFF); + BAT_LED_ON : + BAT_LED_OFF); gpio_set_level(GPIO_BAT_LED_GREEN, (brightness[EC_LED_COLOR_GREEN] != 0) ? - BAT_LED_ON : BAT_LED_OFF); + BAT_LED_ON : + BAT_LED_OFF); return EC_SUCCESS; } return EC_ERROR_UNKNOWN; -- cgit v1.2.1 From 00876329de30fa370b6a92a3417340717ec54858 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:49 -0600 Subject: driver/battery/bq27541.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1372ed33eb509682cec59af9663642edf6e8dd10 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729929 Reviewed-by: Jeremy Bettis --- driver/battery/bq27541.c | 95 +++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 49 deletions(-) diff --git a/driver/battery/bq27541.c b/driver/battery/bq27541.c index b59bfc0b18..b063d220bf 100644 --- a/driver/battery/bq27541.c +++ b/driver/battery/bq27541.c @@ -13,52 +13,52 @@ #include "i2c.h" #include "util.h" -#define BQ27541_ADDR_FLAGS 0x55 -#define BQ27541_TYPE_ID 0x0541 -#define BQ27542_TYPE_ID 0x0542 -#define BQ27741_TYPE_ID 0x0741 -#define BQ27742_TYPE_ID 0x0742 - -#define REG_CTRL 0x00 -#define REG_AT_RATE 0x02 -#define REG_AT_RATE_TIME_TO_EMPTY 0x04 -#define REG_TEMPERATURE 0x06 -#define REG_VOLTAGE 0x08 -#define REG_FLAGS 0x0a -#define REG_NOMINAL_CAPACITY 0x0c +#define BQ27541_ADDR_FLAGS 0x55 +#define BQ27541_TYPE_ID 0x0541 +#define BQ27542_TYPE_ID 0x0542 +#define BQ27741_TYPE_ID 0x0741 +#define BQ27742_TYPE_ID 0x0742 + +#define REG_CTRL 0x00 +#define REG_AT_RATE 0x02 +#define REG_AT_RATE_TIME_TO_EMPTY 0x04 +#define REG_TEMPERATURE 0x06 +#define REG_VOLTAGE 0x08 +#define REG_FLAGS 0x0a +#define REG_NOMINAL_CAPACITY 0x0c #define REG_FULL_AVAILABLE_CAPACITY 0x0e -#define REG_REMAINING_CAPACITY 0x10 -#define REG_FULL_CHARGE_CAPACITY 0x12 -#define REG_AVERAGE_CURRENT 0x14 -#define REG_TIME_TO_EMPTY 0x16 -#define REG_TIME_TO_FULL 0x18 -#define REG_STANDBY_CURRENT 0x1a -#define REG_STANDBY_TIME_TO_EMPTY 0x1c -#define REG_MAX_LOAD_CURRENT 0x1e -#define REG_MAX_LOAD_TIME_TO_EMPTY 0x20 -#define REG_AVAILABLE_ENERGY 0x22 -#define REG_AVERAGE_POEWR 0x24 -#define REG_TT_EAT_CONSTANT_POWER 0x26 -#define REG_CYCLE_COUNT 0x2a -#define REG_STATE_OF_CHARGE 0x2c -#define REG_DATA_FLASH_BLOCK 0x3f -#define REG_DESIGN_CAPACITY 0x3c -#define REG_MANUFACTURER_INFO 0x52 -#define REG_DEVICE_NAME_LENGTH 0x62 -#define MAX_DEVICE_NAME_LENGTH 7 -#define REG_DEVICE_NAME 0x63 -#define REG_PROTECTOR 0x6d +#define REG_REMAINING_CAPACITY 0x10 +#define REG_FULL_CHARGE_CAPACITY 0x12 +#define REG_AVERAGE_CURRENT 0x14 +#define REG_TIME_TO_EMPTY 0x16 +#define REG_TIME_TO_FULL 0x18 +#define REG_STANDBY_CURRENT 0x1a +#define REG_STANDBY_TIME_TO_EMPTY 0x1c +#define REG_MAX_LOAD_CURRENT 0x1e +#define REG_MAX_LOAD_TIME_TO_EMPTY 0x20 +#define REG_AVAILABLE_ENERGY 0x22 +#define REG_AVERAGE_POEWR 0x24 +#define REG_TT_EAT_CONSTANT_POWER 0x26 +#define REG_CYCLE_COUNT 0x2a +#define REG_STATE_OF_CHARGE 0x2c +#define REG_DATA_FLASH_BLOCK 0x3f +#define REG_DESIGN_CAPACITY 0x3c +#define REG_MANUFACTURER_INFO 0x52 +#define REG_DEVICE_NAME_LENGTH 0x62 +#define MAX_DEVICE_NAME_LENGTH 7 +#define REG_DEVICE_NAME 0x63 +#define REG_PROTECTOR 0x6d /* Over-charge */ -#define BQ27542_FLAG_BATHI BIT(13) +#define BQ27542_FLAG_BATHI BIT(13) /* Over Temperature in discharge */ -#define BQ27542_FLAG_OTD BIT(11) +#define BQ27542_FLAG_OTD BIT(11) /* Over Temperature in charge */ -#define BQ27542_FLAG_OTC BIT(7) +#define BQ27542_FLAG_OTC BIT(7) /* Charge allowed */ -#define BQ27542_FLAG_CHG BIT(3) +#define BQ27542_FLAG_CHG BIT(3) /* Discharge */ -#define BQ27542_FLAG_DSG BIT(0) +#define BQ27542_FLAG_DSG BIT(0) static int battery_type_id; static int fake_state_of_charge = -1; @@ -273,10 +273,9 @@ enum battery_present battery_is_present(void) void battery_get_params(struct batt_params *batt) { int v; - const uint32_t flags_to_check = BATT_FLAG_BAD_TEMPERATURE | - BATT_FLAG_BAD_STATE_OF_CHARGE | - BATT_FLAG_BAD_VOLTAGE | - BATT_FLAG_BAD_CURRENT; + const uint32_t flags_to_check = + BATT_FLAG_BAD_TEMPERATURE | BATT_FLAG_BAD_STATE_OF_CHARGE | + BATT_FLAG_BAD_VOLTAGE | BATT_FLAG_BAD_CURRENT; /* Reset flags */ batt->flags = 0; @@ -287,8 +286,8 @@ void battery_get_params(struct batt_params *batt) if (bq27541_read8(REG_STATE_OF_CHARGE, &v) && fake_state_of_charge < 0) batt->flags |= BATT_FLAG_BAD_STATE_OF_CHARGE; - batt->state_of_charge = fake_state_of_charge >= 0 ? - fake_state_of_charge : v; + batt->state_of_charge = + fake_state_of_charge >= 0 ? fake_state_of_charge : v; if (bq27541_read(REG_VOLTAGE, &batt->voltage)) batt->flags |= BATT_FLAG_BAD_VOLTAGE; @@ -312,8 +311,7 @@ void battery_get_params(struct batt_params *batt) batt->flags |= BATT_FLAG_RESPONSIVE; batt->is_present = BP_YES; } else { - - /* If all of those reads error, the battery is not present */ + /* If all of those reads error, the battery is not present */ batt->is_present = BP_NO; } @@ -405,8 +403,7 @@ static int command_battfake(int argc, char **argv) } if (fake_state_of_charge >= 0) - ccprintf("Fake batt %d%%\n", - fake_state_of_charge); + ccprintf("Fake batt %d%%\n", fake_state_of_charge); return EC_SUCCESS; } -- cgit v1.2.1 From b95001cd8de062d6ab8c8b5b9076ff1fe4df01bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:16 -0600 Subject: zephyr/emul/emul_ln9310.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf1f6e40945584d1fe65e3a249a0a1288816d23d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730694 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_ln9310.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/zephyr/emul/emul_ln9310.c b/zephyr/emul/emul_ln9310.c index f2f92154f4..ae213ddebf 100644 --- a/zephyr/emul/emul_ln9310.c +++ b/zephyr/emul/emul_ln9310.c @@ -30,10 +30,8 @@ enum functional_mode { /* TODO shutdown_mode, */ /* TODO bypass, */ FUNCTIONAL_MODE_STANDBY = LN9310_SYS_STANDBY, - FUNCTIONAL_MODE_SWITCHING_21 = - LN9310_SYS_SWITCHING21_ACTIVE, - FUNCTIONAL_MODE_SWITCHING_31 = - LN9310_SYS_SWITCHING31_ACTIVE + FUNCTIONAL_MODE_SWITCHING_21 = LN9310_SYS_SWITCHING21_ACTIVE, + FUNCTIONAL_MODE_SWITCHING_31 = LN9310_SYS_SWITCHING31_ACTIVE }; struct ln9310_emul_data { @@ -489,11 +487,11 @@ static int emul_ln9310_init(const struct emul *emul, #define LN9310_GET_GPIO_INT_PIN(n) \ DT_GPIO_PIN(DT_INST_PROP(n, pg_int_pin), gpios) -#define INIT_LN9310(n) \ - const struct ln9310_config_t ln9310_config = { \ - .i2c_port = NAMED_I2C(power), \ - .i2c_addr_flags = DT_INST_REG_ADDR(n), \ - }; \ +#define INIT_LN9310(n) \ + const struct ln9310_config_t ln9310_config = { \ + .i2c_port = NAMED_I2C(power), \ + .i2c_addr_flags = DT_INST_REG_ADDR(n), \ + }; \ static struct ln9310_emul_data ln9310_emul_data_##n = { \ .common = { \ .start_write = ln9310_emul_start_write, \ @@ -506,13 +504,13 @@ static int emul_ln9310_init(const struct emul *emul, }, \ .gpio_int_port = LN9310_GET_GPIO_INT_PORT(n), \ .gpio_int_pin = LN9310_GET_GPIO_INT_PIN(n), \ - }; \ - static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(emul_ln9310_init, DT_DRV_INST(n), &ln9310_emul_cfg_##n, \ + }; \ + static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(emul_ln9310_init, DT_DRV_INST(n), &ln9310_emul_cfg_##n, \ &ln9310_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(INIT_LN9310) -- cgit v1.2.1 From 94eff5a061a5a3fee4cdfd6dc595a0748a604c17 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:59 -0600 Subject: test/console_edit.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibeedbc4978200981cfbd98291bfed195b3340210 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730495 Reviewed-by: Jeremy Bettis --- test/console_edit.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/test/console_edit.c b/test/console_edit.c index 8d0721c14e..e949073f16 100644 --- a/test/console_edit.c +++ b/test/console_edit.c @@ -40,7 +40,7 @@ enum arrow_key_t { static void arrow_key(enum arrow_key_t k, int repeat) { - static char seq[4] = {0x1B, '[', 0, 0}; + static char seq[4] = { 0x1B, '[', 0, 0 }; seq[2] = 'A' + k; while (repeat--) UART_INJECT(seq); @@ -63,7 +63,7 @@ static void end_key(void) static void ctrl_key(char c) { - static char seq[2] = {0, 0}; + static char seq[2] = { 0, 0 }; seq[0] = c - '@'; UART_INJECT(seq); } @@ -225,7 +225,7 @@ static int test_history_stash(void) static int test_history_list(void) { const char *exp_output = "history\n" /* Input command */ - "test3\n" /* Output 4 last commands */ + "test3\n" /* Output 4 last commands */ "test4\n" "test5\n" "history\n" @@ -258,8 +258,8 @@ static int test_output_channel(void) cputs(CC_TASK, "shouldn't see this either\n"); cflush(); test_capture_console(0); - TEST_ASSERT(compare_multiline_string(test_get_captured_console(), - "") == 0); + TEST_ASSERT(compare_multiline_string(test_get_captured_console(), "") == + 0); UART_INJECT("chan restore\n"); msleep(30); test_capture_console(1); -- cgit v1.2.1 From cd2d24ef67fde253f2affe8c9a9fab950b021293 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:08 -0600 Subject: chip/mchp/registers-mec1701.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I829a95ad84cd3b212ed62b52125a4830efc03b5c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729311 Reviewed-by: Jeremy Bettis --- chip/mchp/registers-mec1701.h | 1884 ++++++++++++++++++++--------------------- 1 file changed, 934 insertions(+), 950 deletions(-) diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h index bfe012a0d8..a44b210a34 100644 --- a/chip/mchp/registers-mec1701.h +++ b/chip/mchp/registers-mec1701.h @@ -14,219 +14,219 @@ * NOTE: GIRQ22 aggregated output and its sources are not connected to * the NVIC. */ -#define MCHP_IRQ_GIRQ8 0 -#define MCHP_IRQ_GIRQ9 1 -#define MCHP_IRQ_GIRQ10 2 -#define MCHP_IRQ_GIRQ11 3 -#define MCHP_IRQ_GIRQ12 4 -#define MCHP_IRQ_GIRQ13 5 -#define MCHP_IRQ_GIRQ14 6 -#define MCHP_IRQ_GIRQ15 7 -#define MCHP_IRQ_GIRQ16 8 -#define MCHP_IRQ_GIRQ17 9 -#define MCHP_IRQ_GIRQ18 10 -#define MCHP_IRQ_GIRQ19 11 -#define MCHP_IRQ_GIRQ20 12 -#define MCHP_IRQ_GIRQ21 13 -#define MCHP_IRQ_GIRQ23 14 -#define MCHP_IRQ_GIRQ24 15 -#define MCHP_IRQ_GIRQ25 16 -#define MCHP_IRQ_GIRQ26 17 +#define MCHP_IRQ_GIRQ8 0 +#define MCHP_IRQ_GIRQ9 1 +#define MCHP_IRQ_GIRQ10 2 +#define MCHP_IRQ_GIRQ11 3 +#define MCHP_IRQ_GIRQ12 4 +#define MCHP_IRQ_GIRQ13 5 +#define MCHP_IRQ_GIRQ14 6 +#define MCHP_IRQ_GIRQ15 7 +#define MCHP_IRQ_GIRQ16 8 +#define MCHP_IRQ_GIRQ17 9 +#define MCHP_IRQ_GIRQ18 10 +#define MCHP_IRQ_GIRQ19 11 +#define MCHP_IRQ_GIRQ20 12 +#define MCHP_IRQ_GIRQ21 13 +#define MCHP_IRQ_GIRQ23 14 +#define MCHP_IRQ_GIRQ24 15 +#define MCHP_IRQ_GIRQ25 16 +#define MCHP_IRQ_GIRQ26 17 /* GIRQ13 direct sources */ -#define MCHP_IRQ_I2C_0 20 -#define MCHP_IRQ_I2C_1 21 -#define MCHP_IRQ_I2C_2 22 -#define MCHP_IRQ_I2C_3 23 +#define MCHP_IRQ_I2C_0 20 +#define MCHP_IRQ_I2C_1 21 +#define MCHP_IRQ_I2C_2 22 +#define MCHP_IRQ_I2C_3 23 /* GIRQ14 direct sources */ -#define MCHP_IRQ_DMA_0 24 -#define MCHP_IRQ_DMA_1 25 -#define MCHP_IRQ_DMA_2 26 -#define MCHP_IRQ_DMA_3 27 -#define MCHP_IRQ_DMA_4 28 -#define MCHP_IRQ_DMA_5 29 -#define MCHP_IRQ_DMA_6 30 -#define MCHP_IRQ_DMA_7 31 -#define MCHP_IRQ_DMA_8 32 -#define MCHP_IRQ_DMA_9 33 -#define MCHP_IRQ_DMA_10 34 -#define MCHP_IRQ_DMA_11 35 -#define MCHP_IRQ_DMA_12 36 -#define MCHP_IRQ_DMA_13 37 +#define MCHP_IRQ_DMA_0 24 +#define MCHP_IRQ_DMA_1 25 +#define MCHP_IRQ_DMA_2 26 +#define MCHP_IRQ_DMA_3 27 +#define MCHP_IRQ_DMA_4 28 +#define MCHP_IRQ_DMA_5 29 +#define MCHP_IRQ_DMA_6 30 +#define MCHP_IRQ_DMA_7 31 +#define MCHP_IRQ_DMA_8 32 +#define MCHP_IRQ_DMA_9 33 +#define MCHP_IRQ_DMA_10 34 +#define MCHP_IRQ_DMA_11 35 +#define MCHP_IRQ_DMA_12 36 +#define MCHP_IRQ_DMA_13 37 /* GIRQ15 direct sources */ -#define MCHP_IRQ_UART0 40 -#define MCHP_IRQ_UART1 41 -#define MCHP_IRQ_EMI0 42 -#define MCHP_IRQ_EMI1 43 -#define MCHP_IRQ_EMI2 44 -#define MCHP_IRQ_ACPIEC0_IBF 45 -#define MCHP_IRQ_ACPIEC0_OBE 46 -#define MCHP_IRQ_ACPIEC1_IBF 47 -#define MCHP_IRQ_ACPIEC1_OBE 48 -#define MCHP_IRQ_ACPIEC2_IBF 49 -#define MCHP_IRQ_ACPIEC2_OBE 50 -#define MCHP_IRQ_ACPIEC3_IBF 51 -#define MCHP_IRQ_ACPIEC3_OBE 52 -#define MCHP_IRQ_ACPIEC4_IBF 53 -#define MCHP_IRQ_ACPIEC4_OBE 54 -#define MCHP_IRQ_ACPIPM1_CTL 55 -#define MCHP_IRQ_ACPIPM1_EN 56 -#define MCHP_IRQ_ACPIPM1_STS 57 -#define MCHP_IRQ_8042EM_OBE 58 -#define MCHP_IRQ_8042EM_IBF 59 -#define MCHP_IRQ_MAILBOX_DATA 60 -#define MCHP_IRQ_PORT80DBG0 62 -#define MCHP_IRQ_PORT80DBG1 63 +#define MCHP_IRQ_UART0 40 +#define MCHP_IRQ_UART1 41 +#define MCHP_IRQ_EMI0 42 +#define MCHP_IRQ_EMI1 43 +#define MCHP_IRQ_EMI2 44 +#define MCHP_IRQ_ACPIEC0_IBF 45 +#define MCHP_IRQ_ACPIEC0_OBE 46 +#define MCHP_IRQ_ACPIEC1_IBF 47 +#define MCHP_IRQ_ACPIEC1_OBE 48 +#define MCHP_IRQ_ACPIEC2_IBF 49 +#define MCHP_IRQ_ACPIEC2_OBE 50 +#define MCHP_IRQ_ACPIEC3_IBF 51 +#define MCHP_IRQ_ACPIEC3_OBE 52 +#define MCHP_IRQ_ACPIEC4_IBF 53 +#define MCHP_IRQ_ACPIEC4_OBE 54 +#define MCHP_IRQ_ACPIPM1_CTL 55 +#define MCHP_IRQ_ACPIPM1_EN 56 +#define MCHP_IRQ_ACPIPM1_STS 57 +#define MCHP_IRQ_8042EM_OBE 58 +#define MCHP_IRQ_8042EM_IBF 59 +#define MCHP_IRQ_MAILBOX_DATA 60 +#define MCHP_IRQ_PORT80DBG0 62 +#define MCHP_IRQ_PORT80DBG1 63 /* GIRQ16 direct sources */ -#define MCHP_IRQ_PKE_ERR 65 -#define MCHP_IRQ_PKE_END 66 -#define MCHP_IRQ_NDRNG 67 -#define MCHP_IRQ_AES 68 -#define MCHP_IRQ_HASH 69 +#define MCHP_IRQ_PKE_ERR 65 +#define MCHP_IRQ_PKE_END 66 +#define MCHP_IRQ_NDRNG 67 +#define MCHP_IRQ_AES 68 +#define MCHP_IRQ_HASH 69 /* GIRQ17 direct sources */ -#define MCHP_IRQ_PECI_HOST 70 -#define MCHP_IRQ_TACH_0 71 -#define MCHP_IRQ_TACH_1 72 -#define MCHP_IRQ_TACH_2 73 -#define MCHP_IRQ_FAN0_FAIL 74 -#define MCHP_IRQ_FAN0_STALL 75 -#define MCHP_IRQ_FAN1_FAIL 76 -#define MCHP_IRQ_FAN1_STALL 77 -#define MCHP_IRQ_ADC_SNGL 78 -#define MCHP_IRQ_ADC_RPT 79 -#define MCHP_IRQ_RCID0 80 -#define MCHP_IRQ_RCID1 81 -#define MCHP_IRQ_RCID2 82 -#define MCHP_IRQ_LED0_WDT 83 -#define MCHP_IRQ_LED1_WDT 84 -#define MCHP_IRQ_LED2_WDT 85 -#define MCHP_IRQ_LED3_WDT 86 -#define MCHP_IRQ_PHOT 87 -#define MCHP_IRQ_PWRGRD0 88 -#define MCHP_IRQ_PWRGRD1 89 +#define MCHP_IRQ_PECI_HOST 70 +#define MCHP_IRQ_TACH_0 71 +#define MCHP_IRQ_TACH_1 72 +#define MCHP_IRQ_TACH_2 73 +#define MCHP_IRQ_FAN0_FAIL 74 +#define MCHP_IRQ_FAN0_STALL 75 +#define MCHP_IRQ_FAN1_FAIL 76 +#define MCHP_IRQ_FAN1_STALL 77 +#define MCHP_IRQ_ADC_SNGL 78 +#define MCHP_IRQ_ADC_RPT 79 +#define MCHP_IRQ_RCID0 80 +#define MCHP_IRQ_RCID1 81 +#define MCHP_IRQ_RCID2 82 +#define MCHP_IRQ_LED0_WDT 83 +#define MCHP_IRQ_LED1_WDT 84 +#define MCHP_IRQ_LED2_WDT 85 +#define MCHP_IRQ_LED3_WDT 86 +#define MCHP_IRQ_PHOT 87 +#define MCHP_IRQ_PWRGRD0 88 +#define MCHP_IRQ_PWRGRD1 89 /* GIRQ18 direct sources */ -#define MCHP_IRQ_LPC 90 -#define MCHP_IRQ_QMSPI0 91 -#define MCHP_IRQ_SPI0_TX 92 -#define MCHP_IRQ_SPI0_RX 93 -#define MCHP_IRQ_SPI1_TX 94 -#define MCHP_IRQ_SPI1_RX 95 -#define MCHP_IRQ_BCM0_ERR 96 -#define MCHP_IRQ_BCM0_BUSY 97 -#define MCHP_IRQ_BCM1_ERR 98 -#define MCHP_IRQ_BCM1_BUSY 99 -#define MCHP_IRQ_PS2_0 100 -#define MCHP_IRQ_PS2_1 101 -#define MCHP_IRQ_PS2_2 102 -#define MCHP_IRQ_EEPROM 155 +#define MCHP_IRQ_LPC 90 +#define MCHP_IRQ_QMSPI0 91 +#define MCHP_IRQ_SPI0_TX 92 +#define MCHP_IRQ_SPI0_RX 93 +#define MCHP_IRQ_SPI1_TX 94 +#define MCHP_IRQ_SPI1_RX 95 +#define MCHP_IRQ_BCM0_ERR 96 +#define MCHP_IRQ_BCM0_BUSY 97 +#define MCHP_IRQ_BCM1_ERR 98 +#define MCHP_IRQ_BCM1_BUSY 99 +#define MCHP_IRQ_PS2_0 100 +#define MCHP_IRQ_PS2_1 101 +#define MCHP_IRQ_PS2_2 102 +#define MCHP_IRQ_EEPROM 155 /* GIRQ19 direct sources */ -#define MCHP_IRQ_ESPI_PC 103 -#define MCHP_IRQ_ESPI_BM1 104 -#define MCHP_IRQ_ESPI_BM2 105 -#define MCHP_IRQ_ESPI_LTR 106 -#define MCHP_IRQ_ESPI_OOB_UP 107 -#define MCHP_IRQ_ESPI_OOB_DN 108 -#define MCHP_IRQ_ESPI_FC 109 -#define MCHP_IRQ_ESPI_RESET 110 -#define MCHP_IRQ_ESPI_VW_EN 156 +#define MCHP_IRQ_ESPI_PC 103 +#define MCHP_IRQ_ESPI_BM1 104 +#define MCHP_IRQ_ESPI_BM2 105 +#define MCHP_IRQ_ESPI_LTR 106 +#define MCHP_IRQ_ESPI_OOB_UP 107 +#define MCHP_IRQ_ESPI_OOB_DN 108 +#define MCHP_IRQ_ESPI_FC 109 +#define MCHP_IRQ_ESPI_RESET 110 +#define MCHP_IRQ_ESPI_VW_EN 156 /* GIRQ21 direct sources */ -#define MCHP_IRQ_RTOS_TIMER 111 -#define MCHP_IRQ_HTIMER0 112 -#define MCHP_IRQ_HTIMER1 113 -#define MCHP_IRQ_WEEK_ALARM 114 -#define MCHP_IRQ_SUBWEEK 115 -#define MCHP_IRQ_WEEK_SEC 116 -#define MCHP_IRQ_WEEK_SUBSEC 117 -#define MCHP_IRQ_WEEK_SYSPWR 118 -#define MCHP_IRQ_RTC 119 -#define MCHP_IRQ_RTC_ALARM 120 -#define MCHP_IRQ_VCI_OVRD_IN 121 -#define MCHP_IRQ_VCI_IN0 122 -#define MCHP_IRQ_VCI_IN1 123 -#define MCHP_IRQ_VCI_IN2 124 -#define MCHP_IRQ_VCI_IN3 125 -#define MCHP_IRQ_VCI_IN4 126 -#define MCHP_IRQ_VCI_IN5 127 -#define MCHP_IRQ_VCI_IN6 128 -#define MCHP_IRQ_PS20A_WAKE 129 -#define MCHP_IRQ_PS20B_WAKE 130 -#define MCHP_IRQ_PS21A_WAKE 131 -#define MCHP_IRQ_PS21B_WAKE 132 -#define MCHP_IRQ_PS2_2_WAKE 133 -#define MCHP_IRQ_ENVMON 134 -#define MCHP_IRQ_KSC_INT 135 +#define MCHP_IRQ_RTOS_TIMER 111 +#define MCHP_IRQ_HTIMER0 112 +#define MCHP_IRQ_HTIMER1 113 +#define MCHP_IRQ_WEEK_ALARM 114 +#define MCHP_IRQ_SUBWEEK 115 +#define MCHP_IRQ_WEEK_SEC 116 +#define MCHP_IRQ_WEEK_SUBSEC 117 +#define MCHP_IRQ_WEEK_SYSPWR 118 +#define MCHP_IRQ_RTC 119 +#define MCHP_IRQ_RTC_ALARM 120 +#define MCHP_IRQ_VCI_OVRD_IN 121 +#define MCHP_IRQ_VCI_IN0 122 +#define MCHP_IRQ_VCI_IN1 123 +#define MCHP_IRQ_VCI_IN2 124 +#define MCHP_IRQ_VCI_IN3 125 +#define MCHP_IRQ_VCI_IN4 126 +#define MCHP_IRQ_VCI_IN5 127 +#define MCHP_IRQ_VCI_IN6 128 +#define MCHP_IRQ_PS20A_WAKE 129 +#define MCHP_IRQ_PS20B_WAKE 130 +#define MCHP_IRQ_PS21A_WAKE 131 +#define MCHP_IRQ_PS21B_WAKE 132 +#define MCHP_IRQ_PS2_2_WAKE 133 +#define MCHP_IRQ_ENVMON 134 +#define MCHP_IRQ_KSC_INT 135 /* GIRQ23 direct sources */ -#define MCHP_IRQ_TIMER16_0 136 -#define MCHP_IRQ_TIMER16_1 137 -#define MCHP_IRQ_TIMER16_2 138 -#define MCHP_IRQ_TIMER16_3 139 -#define MCHP_IRQ_TIMER32_0 140 -#define MCHP_IRQ_TIMER32_1 141 -#define MCHP_IRQ_CNTR_TM0 142 -#define MCHP_IRQ_CNTR_TM1 143 -#define MCHP_IRQ_CNTR_TM2 144 -#define MCHP_IRQ_CNTR_TM3 145 -#define MCHP_IRQ_CCT_TMR 146 -#define MCHP_IRQ_CCT_CAP0 147 -#define MCHP_IRQ_CCT_CAP1 148 -#define MCHP_IRQ_CCT_CAP2 149 -#define MCHP_IRQ_CCT_CAP3 150 -#define MCHP_IRQ_CCT_CAP4 151 -#define MCHP_IRQ_CCT_CAP5 152 -#define MCHP_IRQ_CCT_CMP0 153 -#define MCHP_IRQ_CCT_CMP1 154 +#define MCHP_IRQ_TIMER16_0 136 +#define MCHP_IRQ_TIMER16_1 137 +#define MCHP_IRQ_TIMER16_2 138 +#define MCHP_IRQ_TIMER16_3 139 +#define MCHP_IRQ_TIMER32_0 140 +#define MCHP_IRQ_TIMER32_1 141 +#define MCHP_IRQ_CNTR_TM0 142 +#define MCHP_IRQ_CNTR_TM1 143 +#define MCHP_IRQ_CNTR_TM2 144 +#define MCHP_IRQ_CNTR_TM3 145 +#define MCHP_IRQ_CCT_TMR 146 +#define MCHP_IRQ_CCT_CAP0 147 +#define MCHP_IRQ_CCT_CAP1 148 +#define MCHP_IRQ_CCT_CAP2 149 +#define MCHP_IRQ_CCT_CAP3 150 +#define MCHP_IRQ_CCT_CAP4 151 +#define MCHP_IRQ_CCT_CAP5 152 +#define MCHP_IRQ_CCT_CMP0 153 +#define MCHP_IRQ_CCT_CMP1 154 /* Must match CONFIG_IRQ_COUNT in config_chip.h */ #define MCHP_IRQ_MAX 157 /* Block base addresses */ -#define MCHP_WDG_BASE 0x40000000 -#define MCHP_TMR16_0_BASE 0x40000c00 -#define MCHP_TMR32_0_BASE 0x40000c80 -#define MCHP_CNT16_0_BASE 0x40000d00 -#define MCHP_DMA_BASE 0x40002400 -#define MCHP_PROCHOT_BASE 0x40003400 -#define MCHP_I2C0_BASE 0x40004000 -#define MCHP_I2C1_BASE 0x40004400 -#define MCHP_I2C2_BASE 0x40004800 -#define MCHP_I2C3_BASE 0x40004C00 -#define MCHP_QMSPI0_BASE 0x40005400 -#define MCHP_PWM_0_BASE 0x40005800 -#define MCHP_TACH_0_BASE 0x40006000 -#define MCHP_PECI_BASE 0x40006400 -#define MCHP_RTMR_BASE 0x40007400 -#define MCHP_ADC_BASE 0x40007c00 -#define MCHP_TFDP_BASE 0x40008c00 -#define MCHP_GPSPI0_BASE 0x40009400 -#define MCHP_GPSPI1_BASE 0x40009480 -#define MCHP_HTIMER_BASE 0x40009800 -#define MCHP_KEYSCAN_BASE 0x40009c00 -#define MCHP_RPM2PWM0_BASE 0x4000a000 -#define MCHP_RPM2PWM1_BASE 0x4000a080 -#define MCHP_VBAT_BASE 0x4000a400 -#define MCHP_VBAT_RAM_BASE 0x4000a800 -#define MCHP_WKTIMER_BASE 0x4000ac80 -#define MCHP_BBLED_0_BASE 0x4000B800 -#define MCHP_INT_BASE 0x4000e000 -#define MCHP_EC_BASE 0x4000fc00 - -#define MCHP_PCR_BASE 0x40080100 -#define MCHP_GPIO_BASE 0x40081000 - -#define MCHP_MBOX_BASE 0x400f0000 -#define MCHP_8042_BASE 0x400f0400 -#define MCHP_ACPI_EC_0_BASE 0x400f0800 -#define MCHP_ACPI_PM1_BASE 0x400f1c00 -#define MCHP_UART0_BASE 0x400f2400 -#define MCHP_UART1_BASE 0x400f2800 -#define MCHP_LPC_BASE 0x400f3000 -#define MCHP_ESPI_IO_BASE 0x400f3400 -#define MCHP_ESPI_MEM_BASE 0x400f3800 -#define MCHP_EMI_0_BASE 0x400f4000 -#define MCHP_EMI_1_BASE 0x400f4400 -#define MCHP_EMI_2_BASE 0x400f4800 -#define MCHP_P80CAP0_BASE 0x400f8000 -#define MCHP_P80CAP1_BASE 0x400f8400 -#define MCHP_ESPI_VW_BASE 0x400f9c00 -#define MCHP_CHIP_BASE 0x400fff00 +#define MCHP_WDG_BASE 0x40000000 +#define MCHP_TMR16_0_BASE 0x40000c00 +#define MCHP_TMR32_0_BASE 0x40000c80 +#define MCHP_CNT16_0_BASE 0x40000d00 +#define MCHP_DMA_BASE 0x40002400 +#define MCHP_PROCHOT_BASE 0x40003400 +#define MCHP_I2C0_BASE 0x40004000 +#define MCHP_I2C1_BASE 0x40004400 +#define MCHP_I2C2_BASE 0x40004800 +#define MCHP_I2C3_BASE 0x40004C00 +#define MCHP_QMSPI0_BASE 0x40005400 +#define MCHP_PWM_0_BASE 0x40005800 +#define MCHP_TACH_0_BASE 0x40006000 +#define MCHP_PECI_BASE 0x40006400 +#define MCHP_RTMR_BASE 0x40007400 +#define MCHP_ADC_BASE 0x40007c00 +#define MCHP_TFDP_BASE 0x40008c00 +#define MCHP_GPSPI0_BASE 0x40009400 +#define MCHP_GPSPI1_BASE 0x40009480 +#define MCHP_HTIMER_BASE 0x40009800 +#define MCHP_KEYSCAN_BASE 0x40009c00 +#define MCHP_RPM2PWM0_BASE 0x4000a000 +#define MCHP_RPM2PWM1_BASE 0x4000a080 +#define MCHP_VBAT_BASE 0x4000a400 +#define MCHP_VBAT_RAM_BASE 0x4000a800 +#define MCHP_WKTIMER_BASE 0x4000ac80 +#define MCHP_BBLED_0_BASE 0x4000B800 +#define MCHP_INT_BASE 0x4000e000 +#define MCHP_EC_BASE 0x4000fc00 + +#define MCHP_PCR_BASE 0x40080100 +#define MCHP_GPIO_BASE 0x40081000 + +#define MCHP_MBOX_BASE 0x400f0000 +#define MCHP_8042_BASE 0x400f0400 +#define MCHP_ACPI_EC_0_BASE 0x400f0800 +#define MCHP_ACPI_PM1_BASE 0x400f1c00 +#define MCHP_UART0_BASE 0x400f2400 +#define MCHP_UART1_BASE 0x400f2800 +#define MCHP_LPC_BASE 0x400f3000 +#define MCHP_ESPI_IO_BASE 0x400f3400 +#define MCHP_ESPI_MEM_BASE 0x400f3800 +#define MCHP_EMI_0_BASE 0x400f4000 +#define MCHP_EMI_1_BASE 0x400f4400 +#define MCHP_EMI_2_BASE 0x400f4800 +#define MCHP_P80CAP0_BASE 0x400f8000 +#define MCHP_P80CAP1_BASE 0x400f8400 +#define MCHP_ESPI_VW_BASE 0x400f9c00 +#define MCHP_CHIP_BASE 0x400fff00 #ifndef __ASSEMBLER__ @@ -236,238 +236,236 @@ * Cortex-M4 bit-banding does require aliasing of the * DATA SRAM region. */ -#define MCHP_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) +#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x)) /* EC Chip Configuration */ /* 8-bit Device ID */ -#define MCHP_CHIP_DEV_ID REG8(MCHP_CHIP_BASE + 0x20) +#define MCHP_CHIP_DEV_ID REG8(MCHP_CHIP_BASE + 0x20) /* 8-bit Device Revision */ -#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x21) +#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x21) /* PCR clock control dividers */ -#define MCHP_PCR_CLK_CTL_FASTEST 1U -#define MCHP_PCR_CLK_CTL_48MHZ 1U -#define MCHP_PCR_CLK_CTL_12MHZ 4U +#define MCHP_PCR_CLK_CTL_FASTEST 1U +#define MCHP_PCR_CLK_CTL_48MHZ 1U +#define MCHP_PCR_CLK_CTL_12MHZ 4U /* Number of PCR Sleep Enable, Clock Required, and Reset registers */ #define MCHP_PCR_SLP_RST_REG_MAX 5 /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ -#define MCHP_PCR_OTP BIT(1) -#define MCHP_PCR_ISPI BIT(2) +#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ +#define MCHP_PCR_OTP BIT(1) +#define MCHP_PCR_ISPI BIT(2) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_JTAG BIT(0) -#define MCHP_PCR_SLP_EN0_OTP BIT(1) -#define MCHP_PCR_SLP_EN0_ISPI BIT(2) -#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN0_JTAG BIT(0) +#define MCHP_PCR_SLP_EN0_OTP BIT(1) +#define MCHP_PCR_SLP_EN0_ISPI BIT(2) +#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff /* * Encode register number and bit position * b[4:0] = bit number * b[10:8] = zero based register number */ -#define MCHP_PCR_ERB(rnum, bnum) \ - ((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f)) +#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f)) /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) -#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) -#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) -#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) -#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) -#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) -#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) -#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) -#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) -#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) -#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) -#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) -#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) -#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) -#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) -#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) -#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) -#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) -#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) -#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) -#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) -#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) -#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) +#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) +#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) +#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) +#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) +#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) +#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) +#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) +#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) +#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) +#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) +#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) +#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) +#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) +#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) +#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) +#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) +#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) +#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) +#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) +#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) +#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) +#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) +#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) -#define MCHP_PCR_SLP_EN1_ECS BIT(29) -#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) -#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) -#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) -#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) -#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) -#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) -#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) -#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) -#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) -#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) -#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) -#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) -#define MCHP_PCR_SLP_EN1_WDT BIT(9) -#define MCHP_PCR_SLP_EN1_CPU BIT(8) -#define MCHP_PCR_SLP_EN1_TFDP BIT(7) -#define MCHP_PCR_SLP_EN1_DMA BIT(6) -#define MCHP_PCR_SLP_EN1_PMC BIT(5) -#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) -#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) -#define MCHP_PCR_SLP_EN1_PECI BIT(1) -#define MCHP_PCR_SLP_EN1_ECIA BIT(0) +#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) +#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) +#define MCHP_PCR_SLP_EN1_ECS BIT(29) +#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) + (0xff << 20)) +#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) +#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) +#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) +#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) +#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) +#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) +#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) +#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) +#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) +#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) +#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) +#define MCHP_PCR_SLP_EN1_WDT BIT(9) +#define MCHP_PCR_SLP_EN1_CPU BIT(8) +#define MCHP_PCR_SLP_EN1_TFDP BIT(7) +#define MCHP_PCR_SLP_EN1_DMA BIT(6) +#define MCHP_PCR_SLP_EN1_PMC BIT(5) +#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) +#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) +#define MCHP_PCR_SLP_EN1_PECI BIT(1) +#define MCHP_PCR_SLP_EN1_ECIA BIT(0) /* all sleep enable 1 bits */ -#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff /* * block not used by default * Do not sleep ECIA, PMC, CPU and ECS */ -#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede +#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */ -#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26) -#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25) -#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23) -#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) -#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) -#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) -#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) -#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) -#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26) -#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) -#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) -#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) -#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) -#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) -#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) -#define MCHP_PCR_LPC MCHP_PCR_ERB(2, 0) +#define MCHP_PCR_P80CAP1 MCHP_PCR_ERB(2, 26) +#define MCHP_PCR_P80CAP0 MCHP_PCR_ERB(2, 25) +#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23) +#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) +#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) +#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) +#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) +#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) +#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 26) +#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) +#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) +#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) +#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) +#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) +#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) +#define MCHP_PCR_LPC MCHP_PCR_ERB(2, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) -#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) -#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) -#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) -#define MCHP_PCR_SLP_EN2_ESPI BIT(19) -#define MCHP_PCR_SLP_EN2_RTC BIT(18) -#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) -#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) -#define MCHP_PCR_SLP_EN2_GCFG BIT(12) -#define MCHP_PCR_SLP_EN2_UART1 BIT(2) -#define MCHP_PCR_SLP_EN2_UART0 BIT(1) -#define MCHP_PCR_SLP_EN2_LPC BIT(0) +#define MCHP_PCR_SLP_EN2_P80CAP1 BIT(26) +#define MCHP_PCR_SLP_EN2_P80CAP0 BIT(25) +#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) +#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) +#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) +#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) +#define MCHP_PCR_SLP_EN2_ESPI BIT(19) +#define MCHP_PCR_SLP_EN2_RTC BIT(18) +#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) +#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) +#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) +#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) +#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) +#define MCHP_PCR_SLP_EN2_GCFG BIT(12) +#define MCHP_PCR_SLP_EN2_UART1 BIT(2) +#define MCHP_PCR_SLP_EN2_UART0 BIT(1) +#define MCHP_PCR_SLP_EN2_LPC BIT(0) /* all sleep enable 2 bits */ -#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */ -#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31) -#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) -#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) -#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28) -#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27) -#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26) -#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25) -#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) -#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) -#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22) -#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21) -#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(3, 20) -#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19) -#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) -#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) -#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) -#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) -#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) -#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) -#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12) -#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) -#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) -#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9) -#define MCHP_PCR_PS2_2 MCHP_PCR_ERB(3, 7) -#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6) -#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) -#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) +#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31) +#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) +#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) +#define MCHP_PCR_AESHASH MCHP_PCR_ERB(3, 28) +#define MCHP_PCR_RNG MCHP_PCR_ERB(3, 27) +#define MCHP_PCR_PKE MCHP_PCR_ERB(3, 26) +#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25) +#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) +#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) +#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22) +#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21) +#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(3, 20) +#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19) +#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) +#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) +#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) +#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) +#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) +#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) +#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12) +#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) +#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) +#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9) +#define MCHP_PCR_PS2_2 MCHP_PCR_ERB(3, 7) +#define MCHP_PCR_PS2_1 MCHP_PCR_ERB(3, 6) +#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) +#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) -#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) -#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) -#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) -#define MCHP_PCR_SLP_EN3_RNG BIT(27) -#define MCHP_PCR_SLP_EN3_PKE BIT(26) -#define MCHP_PCR_SLP_EN3_LED3 BIT(25) -#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) -#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) -#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) -#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) -#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) -#define MCHP_PCR_SLP_EN3_LED2 BIT(18) -#define MCHP_PCR_SLP_EN3_LED1 BIT(17) -#define MCHP_PCR_SLP_EN3_LED0 BIT(16) -#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) -#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) -#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) -#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12) -#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) -#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) -#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) -#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7) -#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) -#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) -#define MCHP_PCR_SLP_EN3_ADC BIT(3) -#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26) +#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) +#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) +#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) +#define MCHP_PCR_SLP_EN3_AESHASH BIT(28) +#define MCHP_PCR_SLP_EN3_RNG BIT(27) +#define MCHP_PCR_SLP_EN3_PKE BIT(26) +#define MCHP_PCR_SLP_EN3_LED3 BIT(25) +#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) +#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) +#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) +#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) +#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) +#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) +#define MCHP_PCR_SLP_EN3_LED2 BIT(18) +#define MCHP_PCR_SLP_EN3_LED1 BIT(17) +#define MCHP_PCR_SLP_EN3_LED0 BIT(16) +#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) +#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) +#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) +#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12) +#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) +#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) +#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) +#define MCHP_PCR_SLP_EN3_PS2_2 BIT(7) +#define MCHP_PCR_SLP_EN3_PS2_1 BIT(6) +#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) +#define MCHP_PCR_SLP_EN3_ADC BIT(3) +#define MCHP_PCR_SLP_EN3_ALL_CRYPTO (0x07 << 26) /* all sleep enable 3 bits */ -#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff -#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9) +#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9) /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */ -#define MCHP_PCR_FJCL MCHP_PCR_ERB(4, 15) -#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) -#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) -#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12) -#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11) -#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10) -#define MCHP_PCR_BCM1 MCHP_PCR_ERB(4, 9) -#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) -#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7) -#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) -#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5) -#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4) -#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3) -#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2) -#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1) -#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0) +#define MCHP_PCR_FJCL MCHP_PCR_ERB(4, 15) +#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) +#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) +#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12) +#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11) +#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10) +#define MCHP_PCR_BCM1 MCHP_PCR_ERB(4, 9) +#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) +#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7) +#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) +#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5) +#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4) +#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3) +#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2) +#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1) +#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN4_FJCL BIT(15) -#define MCHP_PCR_SLP_EN4_PSPI BIT(14) -#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) -#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) -#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) -#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) -#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) -#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) -#define MCHP_PCR_SLP_EN4_RTMR BIT(6) -#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) -#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) -#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) -#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) -#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) -#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) +#define MCHP_PCR_SLP_EN4_FJCL BIT(15) +#define MCHP_PCR_SLP_EN4_PSPI BIT(14) +#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) +#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) +#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) +#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) +#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) +#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) +#define MCHP_PCR_SLP_EN4_RTMR BIT(6) +#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) +#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) +#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) +#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) +#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) +#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) /* all sleep enable 4 bits */ -#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff #define MCHP_PCR_SLP_EN4_PWM_ALL \ (MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11) @@ -479,75 +477,75 @@ #define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP)) /* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_MASK_RO 0xc8c -#define MCHP_PWR_RST_STS_MASK_RWC 0x060 +#define MCHP_PWR_RST_STS_MASK_RO 0xc8c +#define MCHP_PWR_RST_STS_MASK_RWC 0x060 #define MCHP_PWR_RST_STS_MASK \ ((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC)) -#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ -#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ -#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ -#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ +#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ +#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ +#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ +#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ /* same function, old bit name */ -#define MCHP_PWR_RST_STS_VTR BIT(6) -#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ -#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ -#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ +#define MCHP_PWR_RST_STS_VTR BIT(6) +#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ +#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ +#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ /* Bit defines for MCHP_PCR_PWR_RST_CTL */ -#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 -#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) -#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8) -#define MCHP_PCR_PWR_OK_INV_BITPOS 0 +#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 +#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) +#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST (0 << 8) +#define MCHP_PCR_PWR_OK_INV_BITPOS 0 /* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET BIT(8) +#define MCHP_PCR_SYS_SOFT_RESET BIT(8) /* EC Subsystem */ -#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) -#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) -#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) -#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) -#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) -#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) -#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) -#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c) -#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40) -#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c) -#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64) +#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) +#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) +#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) +#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) +#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) +#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) +#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) +#define MCHP_EC_AES_SHA_SWAP_CTRL REG8(MCHP_EC_BASE + 0x2c) +#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40) +#define MCHP_EC_CRYPTO_SRESET REG8(MCHP_EC_BASE + 0x5c) +#define MCHP_EC_GPIO_BANK_PWR REG8(MCHP_EC_BASE + 0x64) /* AHB ERR Enable bit[0]=0(enable), 1(disable) */ -#define MCHP_EC_AHB_ERROR_ENABLE 0 -#define MCHP_EC_AHB_ERROR_DISABLE 1 +#define MCHP_EC_AHB_ERROR_ENABLE 0 +#define MCHP_EC_AHB_ERROR_DISABLE 1 /* MCHP_EC_JTAG_EN bit definitions */ -#define MCHP_JTAG_ENABLE 0x01 +#define MCHP_JTAG_ENABLE 0x01 /* bits [2:1] */ -#define MCHP_JTAG_MODE_4PIN 0x00 +#define MCHP_JTAG_MODE_4PIN 0x00 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */ -#define MCHP_JTAG_MODE_SWD_SWV 0x02 +#define MCHP_JTAG_MODE_SWD_SWV 0x02 /* ARM 2-pin SWD with no SWV */ -#define MCHP_JTAG_MODE_SWD 0x04 +#define MCHP_JTAG_MODE_SWD 0x04 /* MCHP_EC_CRYPTO_SRESET bit definitions. Bits cleared by HW */ -#define MCHP_CRYPTO_NDRNG_SRST 0x01 -#define MCHP_CRYPTO_PKE_SRST 0x02 -#define MCHP_CRYPTO_AES_SHA_SRST 0x04 -#define MCHP_CRYPTO_ALL_SRST 0x07 +#define MCHP_CRYPTO_NDRNG_SRST 0x01 +#define MCHP_CRYPTO_PKE_SRST 0x02 +#define MCHP_CRYPTO_AES_SHA_SRST 0x04 +#define MCHP_CRYPTO_ALL_SRST 0x07 /* MCHP_GPIO_BANK_PWR bit definitions */ -#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86 -#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02 -#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04 -#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80 +#define MCHP_EC_GPIO_BANK_PWR_MASK 0x86 +#define MCHP_EC_GPIO_BANK_PWR_VTR2_18 0x02 +#define MCHP_EC_GPIO_BANK_PWR_VTR3_18 0x04 +#define MCHP_EC_GPIO_BANK_PWR_LOCK 0x80 /* EC Interrupt aggregator (ECIA) */ -#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ -#define MCHP_INT_GIRQ_FIRST 8 -#define MCHP_INT_GIRQ_LAST 26 -#define MCHP_INT_GIRQ_NUM (26-8+1) +#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ +#define MCHP_INT_GIRQ_FIRST 8 +#define MCHP_INT_GIRQ_LAST 26 +#define MCHP_INT_GIRQ_NUM (26 - 8 + 1) /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */ -#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN)) +#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN)) /* * GPIO GIRQ's are not direct capable @@ -561,8 +559,8 @@ * GIRQ22 wake peripheral clock only * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires */ -#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U -#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U +#define MCHP_INT_AGGR_ONLY_BITMAP 0x07401F00U +#define MCHP_INT_DIRECT_CAPABLE_BITMAP 0x00BFE000U /* GIRQ13 I2C controllers. Direct capable */ #define MCHP_INT13_I2C(x) (1ul << (x)) @@ -571,148 +569,148 @@ #define MCHP_INT14_DMA(x) (1ul << (x)) /* GIQ15 interrupt sources. Direct capable */ -#define MCHP_INT15_UART_0 BIT(0) -#define MCHP_INT15_UART_1 BIT(1) -#define MCHP_INT15_EMI_0 BIT(2) -#define MCHP_INT15_EMI_1 BIT(3) -#define MCHP_INT15_EMI_2 BIT(4) -#define MCHP_INT15_ACPI_EC0_IBF BIT(5) -#define MCHP_INT15_ACPI_EC0_OBE BIT(6) -#define MCHP_INT15_ACPI_EC1_IBF BIT(7) -#define MCHP_INT15_ACPI_EC1_OBE BIT(8) -#define MCHP_INT15_ACPI_EC2_IBF BIT(9) -#define MCHP_INT15_ACPI_EC2_OBE BIT(10) -#define MCHP_INT15_ACPI_EC3_IBF BIT(11) -#define MCHP_INT15_ACPI_EC3_OBE BIT(12) -#define MCHP_INT15_ACPI_EC4_IBF BIT(13) -#define MCHP_INT15_ACPI_EC4_OBE BIT(14) -#define MCHP_INT15_ACPI_PM1_CTL BIT(15) -#define MCHP_INT15_ACPI_PM1_EN BIT(16) -#define MCHP_INT15_ACPI_PM1_STS BIT(17) -#define MCHP_INT15_8042_OBE BIT(18) -#define MCHP_INT15_8042_IBF BIT(19) -#define MCHP_INT15_MAILBOX BIT(20) -#define MCHP_INT15_P80_0 BIT(22) -#define MCHP_INT15_P80_1 BIT(23) -#define MCHP_INT15_P80(x) BIT(22 + ((x) & 0x01U)) +#define MCHP_INT15_UART_0 BIT(0) +#define MCHP_INT15_UART_1 BIT(1) +#define MCHP_INT15_EMI_0 BIT(2) +#define MCHP_INT15_EMI_1 BIT(3) +#define MCHP_INT15_EMI_2 BIT(4) +#define MCHP_INT15_ACPI_EC0_IBF BIT(5) +#define MCHP_INT15_ACPI_EC0_OBE BIT(6) +#define MCHP_INT15_ACPI_EC1_IBF BIT(7) +#define MCHP_INT15_ACPI_EC1_OBE BIT(8) +#define MCHP_INT15_ACPI_EC2_IBF BIT(9) +#define MCHP_INT15_ACPI_EC2_OBE BIT(10) +#define MCHP_INT15_ACPI_EC3_IBF BIT(11) +#define MCHP_INT15_ACPI_EC3_OBE BIT(12) +#define MCHP_INT15_ACPI_EC4_IBF BIT(13) +#define MCHP_INT15_ACPI_EC4_OBE BIT(14) +#define MCHP_INT15_ACPI_PM1_CTL BIT(15) +#define MCHP_INT15_ACPI_PM1_EN BIT(16) +#define MCHP_INT15_ACPI_PM1_STS BIT(17) +#define MCHP_INT15_8042_OBE BIT(18) +#define MCHP_INT15_8042_IBF BIT(19) +#define MCHP_INT15_MAILBOX BIT(20) +#define MCHP_INT15_P80_0 BIT(22) +#define MCHP_INT15_P80_1 BIT(23) +#define MCHP_INT15_P80(x) BIT(22 + ((x)&0x01U)) /* GIRQ16 interrupt sources. Direct capable */ -#define MCHP_INT16_PKE_ERR BIT(0) -#define MCHP_INT16_PKE_DONE BIT(1) -#define MCHP_INT16_RNG_DONE BIT(2) -#define MCHP_INT16_AES_DONE BIT(3) -#define MCHP_INT16_HASH_DONE BIT(4) +#define MCHP_INT16_PKE_ERR BIT(0) +#define MCHP_INT16_PKE_DONE BIT(1) +#define MCHP_INT16_RNG_DONE BIT(2) +#define MCHP_INT16_AES_DONE BIT(3) +#define MCHP_INT16_HASH_DONE BIT(4) /* GIR17 interrupt sources. Direct capable */ -#define MCHP_INT17_PECI BIT(0) -#define MCHP_INT17_TACH_0 BIT(1) -#define MCHP_INT17_TACH_1 BIT(2) -#define MCHP_INT17_TACH_2 BIT(3) -#define MCHP_INT17_RPM2PWM0_FAIL BIT(4) -#define MCHP_INT17_RPM2PWM0_STALL BIT(5) -#define MCHP_INT17_RPM2PWM1_FAIL BIT(6) -#define MCHP_INT17_RPM2PWM1_STALL BIT(7) -#define MCHP_INT17_ADC_SINGLE BIT(8) -#define MCHP_INT17_ADC_REPEAT BIT(9) -#define MCHP_INT17_RCID_0 BIT(10) -#define MCHP_INT17_RCID_1 BIT(11) -#define MCHP_INT17_RCID_2 BIT(12) -#define MCHP_INT17_LED_WDT_0 BIT(13) -#define MCHP_INT17_LED_WDT_1 BIT(14) -#define MCHP_INT17_LED_WDT_2 BIT(15) -#define MCHP_INT17_LED_WDT_3 BIT(16) -#define MCHP_INT17_PROCHOT BIT(17) -#define MCHP_INT17_PWRGRD0 BIT(18) -#define MCHP_INT17_PWRGRD1 BIT(19) +#define MCHP_INT17_PECI BIT(0) +#define MCHP_INT17_TACH_0 BIT(1) +#define MCHP_INT17_TACH_1 BIT(2) +#define MCHP_INT17_TACH_2 BIT(3) +#define MCHP_INT17_RPM2PWM0_FAIL BIT(4) +#define MCHP_INT17_RPM2PWM0_STALL BIT(5) +#define MCHP_INT17_RPM2PWM1_FAIL BIT(6) +#define MCHP_INT17_RPM2PWM1_STALL BIT(7) +#define MCHP_INT17_ADC_SINGLE BIT(8) +#define MCHP_INT17_ADC_REPEAT BIT(9) +#define MCHP_INT17_RCID_0 BIT(10) +#define MCHP_INT17_RCID_1 BIT(11) +#define MCHP_INT17_RCID_2 BIT(12) +#define MCHP_INT17_LED_WDT_0 BIT(13) +#define MCHP_INT17_LED_WDT_1 BIT(14) +#define MCHP_INT17_LED_WDT_2 BIT(15) +#define MCHP_INT17_LED_WDT_3 BIT(16) +#define MCHP_INT17_PROCHOT BIT(17) +#define MCHP_INT17_PWRGRD0 BIT(18) +#define MCHP_INT17_PWRGRD1 BIT(19) /* GIRQ18 interrupt sources. Direct capable */ -#define MCHP_INT18_LPC_ERR BIT(0) -#define MCHP_INT18_QMSPI BIT(1) -#define MCHP_INT18_GPSPI0_TXBE BIT(2) -#define MCHP_INT18_GPSPI0_RXBF BIT(3) -#define MCHP_INT18_GPSPI1_TXBE BIT(4) -#define MCHP_INT18_GPSPI1_RXBF BIT(5) -#define MCHP_INT18_BCM0_BUSY BIT(6) -#define MCHP_INT18_BCM0_ERR BIT(7) -#define MCHP_INT18_BCM1_BUSY BIT(8) -#define MCHP_INT18_BCM1_ERR BIT(9) -#define MCHP_INT18_PS2_0 BIT(10) -#define MCHP_INT18_PS2_1 BIT(11) -#define MCHP_INT18_PS2_2 BIT(12) -#define MCHP_INT18_PSPI BIT(13) +#define MCHP_INT18_LPC_ERR BIT(0) +#define MCHP_INT18_QMSPI BIT(1) +#define MCHP_INT18_GPSPI0_TXBE BIT(2) +#define MCHP_INT18_GPSPI0_RXBF BIT(3) +#define MCHP_INT18_GPSPI1_TXBE BIT(4) +#define MCHP_INT18_GPSPI1_RXBF BIT(5) +#define MCHP_INT18_BCM0_BUSY BIT(6) +#define MCHP_INT18_BCM0_ERR BIT(7) +#define MCHP_INT18_BCM1_BUSY BIT(8) +#define MCHP_INT18_BCM1_ERR BIT(9) +#define MCHP_INT18_PS2_0 BIT(10) +#define MCHP_INT18_PS2_1 BIT(11) +#define MCHP_INT18_PS2_2 BIT(12) +#define MCHP_INT18_PSPI BIT(13) /* GIRQ19 interrupt sources. Direct capable */ -#define MCHP_INT19_ESPI_PC BIT(0) -#define MCHP_INT19_ESPI_BM1 BIT(1) -#define MCHP_INT19_ESPI_BM2 BIT(2) -#define MCHP_INT19_ESPI_LTR BIT(3) -#define MCHP_INT19_ESPI_OOB_TX BIT(4) -#define MCHP_INT19_ESPI_OOB_RX BIT(5) -#define MCHP_INT19_ESPI_FC BIT(6) -#define MCHP_INT19_ESPI_RESET BIT(7) -#define MCHP_INT19_ESPI_VW_EN BIT(8) +#define MCHP_INT19_ESPI_PC BIT(0) +#define MCHP_INT19_ESPI_BM1 BIT(1) +#define MCHP_INT19_ESPI_BM2 BIT(2) +#define MCHP_INT19_ESPI_LTR BIT(3) +#define MCHP_INT19_ESPI_OOB_TX BIT(4) +#define MCHP_INT19_ESPI_OOB_RX BIT(5) +#define MCHP_INT19_ESPI_FC BIT(6) +#define MCHP_INT19_ESPI_RESET BIT(7) +#define MCHP_INT19_ESPI_VW_EN BIT(8) /* GIRQ20 interrupt sources. Direct capable */ -#define MCHP_INT20_STAP_OBF BIT(0) -#define MCHP_INT20_STAP_IBF BIT(1) -#define MCHP_INT20_STAP_WAKE BIT(2) -#define MCHP_INT20_ISPI BIT(8) +#define MCHP_INT20_STAP_OBF BIT(0) +#define MCHP_INT20_STAP_IBF BIT(1) +#define MCHP_INT20_STAP_WAKE BIT(2) +#define MCHP_INT20_ISPI BIT(8) /* GIRQ21 interrupt sources. Direct capable */ -#define MCHP_INT21_RTMR BIT(0) -#define MCHP_INT21_HTMR_0 BIT(1) -#define MCHP_INT21_HTMR_1 BIT(2) -#define MCHP_INT21_WEEK_ALARM BIT(3) -#define MCHP_INT21_WEEK_SUB BIT(4) -#define MCHP_INT21_WEEK_1SEC BIT(5) -#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) -#define MCHP_INT21_WEEK_PWR_PRES BIT(7) -#define MCHP_INT21_RTC BIT(8) -#define MCHP_INT21_RTC_ALARM BIT(9) -#define MCHP_INT21_VCI_OVRD BIT(10) -#define MCHP_INT21_VCI_IN0 BIT(11) -#define MCHP_INT21_VCI_IN1 BIT(12) -#define MCHP_INT21_VCI_IN2 BIT(13) -#define MCHP_INT21_VCI_IN3 BIT(14) -#define MCHP_INT21_VCI_IN4 BIT(15) -#define MCHP_INT21_VCI_IN5 BIT(16) -#define MCHP_INT21_VCI_IN6 BIT(17) -#define MCHP_INT21_PS2_0A_WAKE BIT(18) -#define MCHP_INT21_PS2_0B_WAKE BIT(19) -#define MCHP_INT21_PS2_1A_WAKE BIT(20) -#define MCHP_INT21_PS2_1B_WAKE BIT(21) -#define MCHP_INT21_PS2_2_WAKE BIT(22) -#define MCHP_INT21_ENVMON BIT(24) -#define MCHP_INT21_KEYSCAN BIT(25) +#define MCHP_INT21_RTMR BIT(0) +#define MCHP_INT21_HTMR_0 BIT(1) +#define MCHP_INT21_HTMR_1 BIT(2) +#define MCHP_INT21_WEEK_ALARM BIT(3) +#define MCHP_INT21_WEEK_SUB BIT(4) +#define MCHP_INT21_WEEK_1SEC BIT(5) +#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) +#define MCHP_INT21_WEEK_PWR_PRES BIT(7) +#define MCHP_INT21_RTC BIT(8) +#define MCHP_INT21_RTC_ALARM BIT(9) +#define MCHP_INT21_VCI_OVRD BIT(10) +#define MCHP_INT21_VCI_IN0 BIT(11) +#define MCHP_INT21_VCI_IN1 BIT(12) +#define MCHP_INT21_VCI_IN2 BIT(13) +#define MCHP_INT21_VCI_IN3 BIT(14) +#define MCHP_INT21_VCI_IN4 BIT(15) +#define MCHP_INT21_VCI_IN5 BIT(16) +#define MCHP_INT21_VCI_IN6 BIT(17) +#define MCHP_INT21_PS2_0A_WAKE BIT(18) +#define MCHP_INT21_PS2_0B_WAKE BIT(19) +#define MCHP_INT21_PS2_1A_WAKE BIT(20) +#define MCHP_INT21_PS2_1B_WAKE BIT(21) +#define MCHP_INT21_PS2_2_WAKE BIT(22) +#define MCHP_INT21_ENVMON BIT(24) +#define MCHP_INT21_KEYSCAN BIT(25) /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */ -#define MCHP_INT22_WAKE_ONLY_LPC BIT(0) -#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) -#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) -#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) -#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) -#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) +#define MCHP_INT22_WAKE_ONLY_LPC BIT(0) +#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) +#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) +#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) +#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) +#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) /* GIRQ23 sources. Direct capable */ -#define MCHP_INT23_BTMR16_0 BIT(0) -#define MCHP_INT23_BTMR16_1 BIT(1) -#define MCHP_INT23_BTMR16_2 BIT(2) -#define MCHP_INT23_BTMR16_3 BIT(3) -#define MCHP_INT23_BTMR32_0 BIT(4) -#define MCHP_INT23_BTMR32_1 BIT(5) -#define MCHP_INT23_CNT16_0 BIT(6) -#define MCHP_INT23_CNT16_1 BIT(7) -#define MCHP_INT23_CNT16_2 BIT(8) -#define MCHP_INT23_CNT16_3 BIT(9) -#define MCHP_INT23_CCT BIT(10) -#define MCHP_INT23_CCT_CAP0 BIT(11) -#define MCHP_INT23_CCT_CAP1 BIT(12) -#define MCHP_INT23_CCT_CAP2 BIT(13) -#define MCHP_INT23_CCT_CAP3 BIT(14) -#define MCHP_INT23_CCT_CAP4 BIT(15) -#define MCHP_INT23_CCT_CAP6 BIT(16) -#define MCHP_INT23_CCT_CMP0 BIT(17) -#define MCHP_INT23_CCT_CMP1 BIT(18) +#define MCHP_INT23_BTMR16_0 BIT(0) +#define MCHP_INT23_BTMR16_1 BIT(1) +#define MCHP_INT23_BTMR16_2 BIT(2) +#define MCHP_INT23_BTMR16_3 BIT(3) +#define MCHP_INT23_BTMR32_0 BIT(4) +#define MCHP_INT23_BTMR32_1 BIT(5) +#define MCHP_INT23_CNT16_0 BIT(6) +#define MCHP_INT23_CNT16_1 BIT(7) +#define MCHP_INT23_CNT16_2 BIT(8) +#define MCHP_INT23_CNT16_3 BIT(9) +#define MCHP_INT23_CCT BIT(10) +#define MCHP_INT23_CCT_CAP0 BIT(11) +#define MCHP_INT23_CCT_CAP1 BIT(12) +#define MCHP_INT23_CCT_CAP2 BIT(13) +#define MCHP_INT23_CCT_CAP3 BIT(14) +#define MCHP_INT23_CCT_CAP4 BIT(15) +#define MCHP_INT23_CCT_CAP6 BIT(16) +#define MCHP_INT23_CCT_CMP0 BIT(17) +#define MCHP_INT23_CCT_CMP1 BIT(18) /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */ #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s))) @@ -721,19 +719,18 @@ #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s))) /* UART Peripheral 0 <= x <= 1 */ -#define MCHP_UART_INSTANCES 2 -#define MCHP_UART_SPACING 0x400 -#define MCHP_UART_CFG_OFS 0x300 +#define MCHP_UART_INSTANCES 2 +#define MCHP_UART_SPACING 0x400 +#define MCHP_UART_CFG_OFS 0x300 #define MCHP_UART_CONFIG_BASE(x) \ - (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_RUNTIME_BASE(x) \ - (MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_GIRQ 15 -#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) -#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) -#define MCHP_UART_GIRQ_BIT(x) BIT(x) + (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_GIRQ 15 +#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) +#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) +#define MCHP_UART_GIRQ_BIT(x) BIT(x) /* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY BIT(5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* * GPIO @@ -764,284 +761,271 @@ * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274 * */ -#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \ - (((port << 5) + id) << 2)) +#define MCHP_GPIO_CTL(port, id) \ + REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2)) /* MCHP implements 6 GPIO ports */ -#define MCHP_GPIO_MAX_PORT 6 -#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT +#define MCHP_GPIO_MAX_PORT 6 +#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT /* * In MECxxxx documentation GPIO numbers are octal, each control * register is located on a 32-bit boundary. */ -#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \ - ((gpio_num) << 2)) +#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2)) /* * GPIO control register bit fields */ -#define MCHP_GPIO_CTRL_PUD_BITPOS 0 -#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 -#define MCHP_GPIO_CTRL_PUD_MASK 0x03 -#define MCHP_GPIO_CTRL_PUD_NONE 0x00 -#define MCHP_GPIO_CTRL_PUD_PU 0x01 -#define MCHP_GPIO_CTRL_PUD_PD 0x02 -#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 -#define MCHP_GPIO_CTRL_PWR_BITPOS 2 -#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 -#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2) -#define MCHP_GPIO_CTRL_PWR_VTR 0 -#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2) -#define MCHP_GPIO_INTDET_MASK 0xF0 -#define MCHP_GPIO_INTDET_LVL_LO 0x00 -#define MCHP_GPIO_INTDET_LVL_HI 0x10 -#define MCHP_GPIO_INTDET_DISABLED 0x40 -#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0 -#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0 -#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0 -#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) -#define MCHP_GPIO_PUSH_PULL 0u -#define MCHP_GPIO_OPEN_DRAIN BIT(8) -#define MCHP_GPIO_INPUT 0u -#define MCHP_GPIO_OUTPUT BIT(9) -#define MCHP_GPIO_OUTSET_CTRL 0u -#define MCHP_GPIO_OUTSEL_PAR BIT(10) -#define MCHP_GPIO_POLARITY_NINV 0u -#define MCHP_GPIO_POLARITY_INV BIT(11) -#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12) -#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12) -#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) -#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) -#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) -#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) +#define MCHP_GPIO_CTRL_PUD_BITPOS 0 +#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 +#define MCHP_GPIO_CTRL_PUD_MASK 0x03 +#define MCHP_GPIO_CTRL_PUD_NONE 0x00 +#define MCHP_GPIO_CTRL_PUD_PU 0x01 +#define MCHP_GPIO_CTRL_PUD_PD 0x02 +#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 +#define MCHP_GPIO_CTRL_PWR_BITPOS 2 +#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 +#define MCHP_GPIO_CTRL_PWR_MASK (0x03 << 2) +#define MCHP_GPIO_CTRL_PWR_VTR 0 +#define MCHP_GPIO_CTRL_PWR_OFF (0x02 << 2) +#define MCHP_GPIO_INTDET_MASK 0xF0 +#define MCHP_GPIO_INTDET_LVL_LO 0x00 +#define MCHP_GPIO_INTDET_LVL_HI 0x10 +#define MCHP_GPIO_INTDET_DISABLED 0x40 +#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0 +#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0 +#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0 +#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) +#define MCHP_GPIO_PUSH_PULL 0u +#define MCHP_GPIO_OPEN_DRAIN BIT(8) +#define MCHP_GPIO_INPUT 0u +#define MCHP_GPIO_OUTPUT BIT(9) +#define MCHP_GPIO_OUTSET_CTRL 0u +#define MCHP_GPIO_OUTSEL_PAR BIT(10) +#define MCHP_GPIO_POLARITY_NINV 0u +#define MCHP_GPIO_POLARITY_INV BIT(11) +#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x0F +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x0F << 12) +#define MCHP_GPIO_CTRL_FUNC_GPIO (0 << 12) +#define MCHP_GPIO_CTRL_FUNC_1 (1 << 12) +#define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) +#define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) +#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) /* MEC170x reserved read-only 0 bit. Value set to 0 */ -#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 -#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0 +#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 +#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0 /* * GPIO Parallel Input and Output registers. * gpio_bank in [0, 5] */ -#define MCHP_GPIO_PARIN(bank) \ - REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) -#define MCHP_GPIO_PAROUT(bank) \ - REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) +#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) +#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) /* Basic timers */ -#define MCHP_TMR_SPACING 0x20 -#define MCHP_TMR16_INSTANCES 4 -#define MCHP_TMR32_INSTANCES 2 -#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) -#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) -#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR16_GIRQ 23 -#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) -#define MCHP_TMR32_GIRQ 23 -#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) +#define MCHP_TMR_SPACING 0x20 +#define MCHP_TMR16_INSTANCES 4 +#define MCHP_TMR32_INSTANCES 2 +#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) +#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) +#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR16_GIRQ 23 +#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) +#define MCHP_TMR32_GIRQ 23 +#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) /* 16-bit Counter/timer */ -#define MCHP_CNT16_SPACING 0x20 -#define MCHP_CNT16_INSTANCES 4 -#define MCHP_CNT16_BASE(n) \ - (MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING) -#define MCHP_CNT16_GIRQ 23 -#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x)) +#define MCHP_CNT16_SPACING 0x20 +#define MCHP_CNT16_INSTANCES 4 +#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING) +#define MCHP_CNT16_GIRQ 23 +#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x)) /* RTimer */ -#define MCHP_RTMR_GIRQ 21 -#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR +#define MCHP_RTMR_GIRQ 21 +#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR /* VBAT */ -#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) -#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8) -#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC) -#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) -#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) +#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) +#define MCHP_VBAT_CE REG32(MCHP_VBAT_BASE + 0x8) +#define MCHP_VBAT_SHDN_DIS REG32(MCHP_VBAT_BASE + 0xC) +#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) +#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) /* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */ -#define MCHP_VBAT_RAM_SIZE 128 -#define MCHP_VBAT_RAM(wnum) \ - REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4)) -#define MCHP_VBAT_RAM8(bnum) \ - REG8(MCHP_VBAT_RAM_BASE + (bnum)) -#define MCHP_VBAT_VWIRE_BACKUP 30 +#define MCHP_VBAT_RAM_SIZE 128 +#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4)) +#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum)) +#define MCHP_VBAT_VWIRE_BACKUP 30 /* * Miscellaneous firmware control fields * scratch pad index cannot be more than 32 as * MEC152x has 64 bytes = 16 words of scratch RAM */ -#define MCHP_IMAGETYPE_IDX 31 +#define MCHP_IMAGETYPE_IDX 31 /* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET BIT(2) -#define MCHP_VBAT_STS_RESETI BIT(4) -#define MCHP_VBAT_STS_WDT BIT(5) -#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) -#define MCHP_VBAT_STS_VBAT_RST BIT(7) -#define MCHP_VBAT_STS_ANY_RST 0xF4u +#define MCHP_VBAT_STS_SOFTRESET BIT(2) +#define MCHP_VBAT_STS_RESETI BIT(4) +#define MCHP_VBAT_STS_WDT BIT(5) +#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) +#define MCHP_VBAT_STS_VBAT_RST BIT(7) +#define MCHP_VBAT_STS_ANY_RST 0xF4u /* Bit definitions for MCHP_VBAT_CE */ -#define MCHP_VBAT_CE_XOSEL_BITPOS 3 -#define MCHP_VBAT_CE_XOSEL_MASK BIT(3) -#define MCHP_VBAT_CE_XOSEL_PAR 0 -#define MCHP_VBAT_CE_XOSEL_SE BIT(3) +#define MCHP_VBAT_CE_XOSEL_BITPOS 3 +#define MCHP_VBAT_CE_XOSEL_MASK BIT(3) +#define MCHP_VBAT_CE_XOSEL_PAR 0 +#define MCHP_VBAT_CE_XOSEL_SE BIT(3) -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2 -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2) -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0 -#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2) +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_BITPOS 2 +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_MASK BIT(2) +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_INT 0 +#define MCHP_VBAT_CE_ALWAYS_ON_32K_SRC_CRYSTAL BIT(2) -#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1 -#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1) -#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0 -#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1) +#define MCHP_VBAT_CE_32K_DOMAIN_SRC_BITPOS 1 +#define MCHP_VBAT_CE_32K_DOMAIN_SRC_MASK BIT(1) +#define MCHP_VBAT_CE_32K_DOMAIN_ALWAYS_ON 0 +#define MCHP_VBAT_CE_32K_DOMAIN_32KHZ_IN_PIN BIT(1) /* Blinking-Breathing LED 0 <= n <= 2 */ -#define MCHP_BBLEB_INSTANCES 4 -#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n) & 0x03) * 256)) +#define MCHP_BBLEB_INSTANCES 4 +#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256)) /* EMI */ -#define MCHP_EMI_INSTANCES 3 -#define MCHP_EMI_SPACING 0x400 -#define MCHP_EMI_ECREG_OFS 0x100 +#define MCHP_EMI_INSTANCES 3 +#define MCHP_EMI_SPACING 0x400 +#define MCHP_EMI_ECREG_OFS 0x100 /* base of EMI registers only accessible by EC */ #define MCHP_EMI_BASE(n) \ - (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING)) + (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING)) /* base of EMI registers accessible by EC and Host */ -#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING)) -#define MCHP_EMI_GIRQ 15 -#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) +#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING)) +#define MCHP_EMI_GIRQ 15 +#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) /* Mailbox */ -#define MCHP_MBX_ECREGS_OFS 0x100 -#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE -#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) -#define MCHP_MBX_GIRQ 15 -#define MCHP_MBX_GIRQ_BIT BIT(20) +#define MCHP_MBX_ECREGS_OFS 0x100 +#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE +#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) +#define MCHP_MBX_GIRQ 15 +#define MCHP_MBX_GIRQ_BIT BIT(20) /* Port 80 Capture */ -#define MCHP_P80_SPACING 0x400 +#define MCHP_P80_SPACING 0x400 #define MCHP_P80_BASE(n) (MCHP_P80CAP0_BASE + ((n) * (MCHP_P80_SPACING))) #define MCHP_P80_HOST_DATA(n) REG8(MCHP_P80_BASE(n)) /* Data capture with time stamp register */ -#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100) -#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104) -#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108) -#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c) -#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8) -#define MCHP_P80_CNT_SET(n, c) \ - (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8)) -#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330) -#define MCHP_P80_GIRQ 15 -#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n)) +#define MCHP_P80_CAP(n) REG32(MCHP_P80_BASE(n) + 0x100) +#define MCHP_P80_CFG(n) REG8(MCHP_P80_BASE(n) + 0x104) +#define MCHP_P80_STS(n) REG8(MCHP_P80_BASE(n) + 0x108) +#define MCHP_P80_CNT(n) REG32(MCHP_P80_BASE(n) + 0x10c) +#define MCHP_P80_CNT_GET(n) (REG32(MCHP_P80_BASE(n) + 0x10c) >> 8) +#define MCHP_P80_CNT_SET(n, c) (REG32(MCHP_P80_BASE(n) + 0x10c) = ((c) << 8)) +#define MCHP_P80_ACTIVATE(n) REG8(MCHP_P80_BASE(n) + 0x330) +#define MCHP_P80_GIRQ 15 +#define MCHP_P80_GIRQ_BIT(n) BIT(22 + (n)) /* * Port 80 Data register bits * bits[7:0] = data captured on Host write * bits[31:8] = optional time stamp */ -#define MCHP_P80_CAP_DATA_MASK 0xFFul -#define MCHP_P80_CAP_TS_BITPOS 8 -#define MCHP_P80_CAP_TS_MASK0 0xfffffful -#define MCHP_P80_CAP_TS_MASK \ +#define MCHP_P80_CAP_DATA_MASK 0xFFul +#define MCHP_P80_CAP_TS_BITPOS 8 +#define MCHP_P80_CAP_TS_MASK0 0xfffffful +#define MCHP_P80_CAP_TS_MASK \ ((MCHP_P80_CAP_TS_MASK0) << (MCHP_P80_CAP_TS_BITPOS)) /* Port 80 Configuration register bits */ -#define MCHP_P80_FLUSH_FIFO_WO BIT(1) -#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2) -#define MCHP_P80_TIMEBASE_BITPOS 3 -#define MCHP_P80_TIMEBASE_MASK0 0x03 -#define MCHP_P80_TIMEBASE_MASK \ +#define MCHP_P80_FLUSH_FIFO_WO BIT(1) +#define MCHP_P80_RESET_TIMESTAMP_WO BIT(2) +#define MCHP_P80_TIMEBASE_BITPOS 3 +#define MCHP_P80_TIMEBASE_MASK0 0x03 +#define MCHP_P80_TIMEBASE_MASK \ ((MCHP_P80_TIMEBASE_MASK0) << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_750KHZ \ - (0x03 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_1500KHZ \ - (0x02 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_3MHZ \ - (0x01 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMEBASE_6MHZ \ - (0x00 << (MCHP_P80_TIMEBASE_BITPOS)) -#define MCHP_P80_TIMER_ENABLE BIT(5) -#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6) -#define MCHP_P80_FIFO_THRHOLD_1 0u -#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6) -#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6) -#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6) -#define MCHP_P80_FIFO_LEN 16 +#define MCHP_P80_TIMEBASE_750KHZ (0x03 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_1500KHZ (0x02 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_3MHZ (0x01 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMEBASE_6MHZ (0x00 << (MCHP_P80_TIMEBASE_BITPOS)) +#define MCHP_P80_TIMER_ENABLE BIT(5) +#define MCHP_P80_FIFO_THRHOLD_MASK (3u << 6) +#define MCHP_P80_FIFO_THRHOLD_1 0u +#define MCHP_P80_FIFO_THRHOLD_4 (1u << 6) +#define MCHP_P80_FIFO_THRHOLD_8 (2u << 6) +#define MCHP_P80_FIFO_THRHOLD_14 (3u << 6) +#define MCHP_P80_FIFO_LEN 16 /* Port 80 Status register bits, read-only */ -#define MCHP_P80_STS_NOT_EMPTY BIT(0) -#define MCHP_P80_STS_OVERRUN BIT(1) +#define MCHP_P80_STS_NOT_EMPTY BIT(0) +#define MCHP_P80_STS_OVERRUN BIT(1) /* Port 80 Count register bits */ -#define MCHP_P80_CNT_BITPOS 8 -#define MCHP_P80_CNT_MASK0 0xfffffful +#define MCHP_P80_CNT_BITPOS 8 +#define MCHP_P80_CNT_MASK0 0xfffffful #define MCHP_P80_CNT_MASK ((MCHP_P80_CNT_MASK0) << (MCHP_P80_CNT_BITPOS)) /* PWM SZ 144 pin package has 9 PWM's */ -#define MCHP_PWM_INSTANCES 9 -#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) -#define MCHP_PWM_SPACING 16 -#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING)) +#define MCHP_PWM_INSTANCES 9 +#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) +#define MCHP_PWM_SPACING 16 +#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING)) /* TACH */ -#define MCHP_TACH_INSTANCES 3 -#define MCHP_TACH_SPACING 16 -#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING)) -#define MCHP_TACH_GIRQ 17 -#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) +#define MCHP_TACH_INSTANCES 3 +#define MCHP_TACH_SPACING 16 +#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING)) +#define MCHP_TACH_GIRQ 17 +#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) /* FAN */ -#define MCHP_FAN_INSTANCES 2 -#define MCHP_FAN_SPACING 0x80U -#define MCHP_FAN_BASE(x) \ - (MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING)) -#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0) -#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2) -#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3) -#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4) -#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5) -#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6) -#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7) -#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8) -#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9) -#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa) -#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc) -#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe) -#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10) -#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11) +#define MCHP_FAN_INSTANCES 2 +#define MCHP_FAN_SPACING 0x80U +#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING)) +#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0) +#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2) +#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3) +#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4) +#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5) +#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6) +#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7) +#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8) +#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9) +#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa) +#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc) +#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe) +#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10) +#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11) /* ACPI EC */ -#define MCHP_ACPI_EC_INSTANCES 5 -#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES) -#define MCHP_ACPI_EC_SPACING 0x400 -#define MCHP_ACPI_EC_BASE(x) \ - (MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING)) -#define MCHP_ACPI_EC_GIRQ 15 -#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x) * 2)) -#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x) * 2)) +#define MCHP_ACPI_EC_INSTANCES 5 +#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES) +#define MCHP_ACPI_EC_SPACING 0x400 +#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING)) +#define MCHP_ACPI_EC_GIRQ 15 +#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2)) +#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2)) /* ACPI PM1 */ -#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 -#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE -#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) -#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) -#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) -#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) +#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 +#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE +#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) +#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) +#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) +#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) /* 8042 */ -#define MCHP_8042_ECREGS_OFS 0x100 -#define MCHP_8042_GIRQ 15 -#define MCHP_8042_OBE_GIRQ_BIT BIT(18) -#define MCHP_8042_IBF_GIRQ_BIT BIT(19) +#define MCHP_8042_ECREGS_OFS 0x100 +#define MCHP_8042_GIRQ 15 +#define MCHP_8042_OBE_GIRQ_BIT BIT(18) +#define MCHP_8042_IBF_GIRQ_BIT BIT(19) /* I2C controllers 0 - 4 include SMBus network layer functionality. */ -#define MCHP_I2C_CTRL0 0 -#define MCHP_I2C_CTRL1 1 -#define MCHP_I2C_CTRL2 2 -#define MCHP_I2C_CTRL3 3 -#define MCHP_I2C_CTRL_MAX 4 +#define MCHP_I2C_CTRL0 0 +#define MCHP_I2C_CTRL1 1 +#define MCHP_I2C_CTRL2 2 +#define MCHP_I2C_CTRL3 3 +#define MCHP_I2C_CTRL_MAX 4 -#define MCHP_I2C_SEP0 0x400 +#define MCHP_I2C_SEP0 0x400 /* * MEC1701H 144-pin package has four I2C controllers and eleven ports. @@ -1059,7 +1043,7 @@ #define MCHP_I2C_PORT_MASK 0x07FDul enum MCHP_i2c_port { MCHP_I2C_PORT0 = 0, - MCHP_I2C_PORT1, /* port 1, do not use. pins not present */ + MCHP_I2C_PORT1, /* port 1, do not use. pins not present */ MCHP_I2C_PORT2, MCHP_I2C_PORT3, MCHP_I2C_PORT4, @@ -1073,184 +1057,184 @@ enum MCHP_i2c_port { }; /* All I2C controllers connected to GIRQ13 */ -#define MCHP_I2C_GIRQ 13 +#define MCHP_I2C_GIRQ 13 /* I2C[0:7] -> GIRQ13 bits[0:7] */ -#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) +#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) /* Keyboard scan matrix */ -#define MCHP_KS_GIRQ 21 -#define MCHP_KS_GIRQ_BIT BIT(25) -#define MCHP_KS_DIRECT_NVIC 135 +#define MCHP_KS_GIRQ 21 +#define MCHP_KS_GIRQ_BIT BIT(25) +#define MCHP_KS_DIRECT_NVIC 135 /* ADC */ -#define MCHP_ADC_GIRQ 17 -#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) -#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) -#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 -#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 +#define MCHP_ADC_GIRQ 17 +#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) +#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) +#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 +#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 /* Hibernation timer */ -#define MCHP_HTIMER_SPACING 0x20 -#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING)) -#define MCHP_HTIMER_GIRQ 21 +#define MCHP_HTIMER_SPACING 0x20 +#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING)) +#define MCHP_HTIMER_GIRQ 21 /* HTIMER[0:1] -> GIRQ21 bits[1:2] */ -#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n)) -#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) +#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n)) +#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) /* General Purpose SPI (GP-SPI) */ -#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80)) -#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00) -#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04) -#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08) -#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c) -#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10) -#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14) -#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18) +#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80)) +#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00) +#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04) +#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08) +#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c) +#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10) +#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14) +#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18) /* Addresses of TX/RX register used in tables */ -#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c) -#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10) +#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c) +#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10) /* All GP-SPI controllers connected to GIRQ18 */ -#define MCHP_SPI_GIRQ 18 -#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x) * 2)) -#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x) * 2)) -#define MCHP_GPSPI0_ID 0 -#define MCHP_GPSPI1_ID 1 +#define MCHP_SPI_GIRQ 18 +#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2)) +#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2)) +#define MCHP_GPSPI0_ID 0 +#define MCHP_GPSPI1_ID 1 /* * Quad Master SPI (QMSPI) * MEC1701 implements 5 descriptors and a single chip select. */ -#define MCHP_QMSPI_MAX_DESCR 5 -#define MCHP_QMSPI_GIRQ 18 -#define MCHP_QMSPI_GIRQ_BIT BIT(1) -#define MCHP_QMSPI_DIRECT_NVIC 91 +#define MCHP_QMSPI_MAX_DESCR 5 +#define MCHP_QMSPI_GIRQ 18 +#define MCHP_QMSPI_GIRQ_BIT BIT(1) +#define MCHP_QMSPI_DIRECT_NVIC 91 /* LPC */ -#define MCHP_LPC_RT_BASE (MCHP_LPC_BASE + 0x100) -#define MCHP_LPC_CFG_BASE (MCHP_LPC_BASE + 0x300) -#define MCHP_LPC_ACT REG8(MCHP_LPC_CFG_BASE + 0x30) -#define MCHP_LPC_SIRQ(x) REG8(MCHP_LPC_CFG_BASE + 0x40 + (x)) -#define MCHP_LPC_CFG_BAR REG32(MCHP_LPC_CFG_BASE + 0x60) -#define MCHP_LPC_MAILBOX_BAR REG32(MCHP_LPC_CFG_BASE + 0x64) -#define MCHP_LPC_8042_BAR REG32(MCHP_LPC_CFG_BASE + 0x68) -#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C) -#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70) -#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74) -#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78) -#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C) -#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80) -#define MCHP_LPC_PORT92_BAR REG32(MCHP_LPC_CFG_BASE + 0x84) -#define MCHP_LPC_UART0_BAR REG32(MCHP_LPC_CFG_BASE + 0x88) -#define MCHP_LPC_UART1_BAR REG32(MCHP_LPC_CFG_BASE + 0x8C) -#define MCHP_LPC_EMI0_BAR REG32(MCHP_LPC_CFG_BASE + 0x90) -#define MCHP_LPC_EMI1_BAR REG32(MCHP_LPC_CFG_BASE + 0x94) -#define MCHP_LPC_EMI2_BAR REG32(MCHP_LPC_CFG_BASE + 0x98) -#define MCHP_LPC_P80DBG0_BAR REG32(MCHP_LPC_CFG_BASE + 0x9C) -#define MCHP_LPC_P80DBG1_BAR REG32(MCHP_LPC_CFG_BASE + 0xA0) -#define MCHP_LPC_RTC_BAR REG32(MCHP_LPC_CFG_BASE + 0xA4) -#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x)<<2)) +#define MCHP_LPC_RT_BASE (MCHP_LPC_BASE + 0x100) +#define MCHP_LPC_CFG_BASE (MCHP_LPC_BASE + 0x300) +#define MCHP_LPC_ACT REG8(MCHP_LPC_CFG_BASE + 0x30) +#define MCHP_LPC_SIRQ(x) REG8(MCHP_LPC_CFG_BASE + 0x40 + (x)) +#define MCHP_LPC_CFG_BAR REG32(MCHP_LPC_CFG_BASE + 0x60) +#define MCHP_LPC_MAILBOX_BAR REG32(MCHP_LPC_CFG_BASE + 0x64) +#define MCHP_LPC_8042_BAR REG32(MCHP_LPC_CFG_BASE + 0x68) +#define MCHP_LPC_ACPI_EC0_BAR REG32(MCHP_LPC_CFG_BASE + 0x6C) +#define MCHP_LPC_ACPI_EC1_BAR REG32(MCHP_LPC_CFG_BASE + 0x70) +#define MCHP_LPC_ACPI_EC2_BAR REG32(MCHP_LPC_CFG_BASE + 0x74) +#define MCHP_LPC_ACPI_EC3_BAR REG32(MCHP_LPC_CFG_BASE + 0x78) +#define MCHP_LPC_ACPI_EC4_BAR REG32(MCHP_LPC_CFG_BASE + 0x7C) +#define MCHP_LPC_ACPI_PM1_BAR REG32(MCHP_LPC_CFG_BASE + 0x80) +#define MCHP_LPC_PORT92_BAR REG32(MCHP_LPC_CFG_BASE + 0x84) +#define MCHP_LPC_UART0_BAR REG32(MCHP_LPC_CFG_BASE + 0x88) +#define MCHP_LPC_UART1_BAR REG32(MCHP_LPC_CFG_BASE + 0x8C) +#define MCHP_LPC_EMI0_BAR REG32(MCHP_LPC_CFG_BASE + 0x90) +#define MCHP_LPC_EMI1_BAR REG32(MCHP_LPC_CFG_BASE + 0x94) +#define MCHP_LPC_EMI2_BAR REG32(MCHP_LPC_CFG_BASE + 0x98) +#define MCHP_LPC_P80DBG0_BAR REG32(MCHP_LPC_CFG_BASE + 0x9C) +#define MCHP_LPC_P80DBG1_BAR REG32(MCHP_LPC_CFG_BASE + 0xA0) +#define MCHP_LPC_RTC_BAR REG32(MCHP_LPC_CFG_BASE + 0xA4) +#define MCHP_LPC_ACPI_EC_BAR(x) REG32(MCHP_LPC_CFG_BASE + 0x6C + ((x) << 2)) /* LPC BAR bits */ -#define MCHP_LPC_IO_BAR_ADDR_BITPOS (16) -#define MCHP_LPC_IO_BAR_EN (1ul << 15) +#define MCHP_LPC_IO_BAR_ADDR_BITPOS (16) +#define MCHP_LPC_IO_BAR_EN (1ul << 15) /* LPC Generic Memory BAR's, 64-bit registers */ -#define MCHP_LPC_SRAM0_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB0) -#define MCHP_LPC_SRAM0_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xB4) -#define MCHP_LPC_SRAM1_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB8) -#define MCHP_LPC_SRAM1_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xBC) +#define MCHP_LPC_SRAM0_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB0) +#define MCHP_LPC_SRAM0_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xB4) +#define MCHP_LPC_SRAM1_BAR_LO REG32(MCHP_LPC_CFG_BASE + 0xB8) +#define MCHP_LPC_SRAM1_BAR_HI REG32(MCHP_LPC_CFG_BASE + 0xBC) /* * LPC Logical Device Memory BAR's, 48-bit registers * Use 16-bit aligned access */ -#define MCHP_LPC_MAILBOX_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC0) -#define MCHP_LPC_MAILBOX_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC2) -#define MCHP_LPC_MAILBOX_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xC4) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8) -#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE) -#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4) -#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA) -#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0) -#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6) -#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC) -#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2) -#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4) - -#define MCHP_LPC_BUS_MONITOR REG32(MCHP_LPC_RT_BASE + 0x4) -#define MCHP_LPC_HOST_ERROR REG32(MCHP_LPC_RT_BASE + 0x8) -#define MCHP_LPC_EC_SERIRQ REG32(MCHP_LPC_RT_BASE + 0xC) -#define MCHP_LPC_EC_CLK_CTRL REG32(MCHP_LPC_RT_BASE + 0x10) -#define MCHP_LPC_BAR_INHIBIT REG32(MCHP_LPC_RT_BASE + 0x20) -#define MCHP_LPC_BAR_INIT REG32(MCHP_LPC_RT_BASE + 0x30) -#define MCHP_LPC_SRAM0_BAR REG32(MCHP_LPC_RT_BASE + 0xf8) -#define MCHP_LPC_SRAM1_BAR REG32(MCHP_LPC_RT_BASE + 0xfc) +#define MCHP_LPC_MAILBOX_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC0) +#define MCHP_LPC_MAILBOX_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC2) +#define MCHP_LPC_MAILBOX_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xC4) +#define MCHP_LPC_ACPI_EC0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xC6) +#define MCHP_LPC_ACPI_EC0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xC8) +#define MCHP_LPC_ACPI_EC0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xCA) +#define MCHP_LPC_ACPI_EC1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xCC) +#define MCHP_LPC_ACPI_EC1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xCE) +#define MCHP_LPC_ACPI_EC1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD0) +#define MCHP_LPC_ACPI_EC2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD2) +#define MCHP_LPC_ACPI_EC2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xD4) +#define MCHP_LPC_ACPI_EC2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xD6) +#define MCHP_LPC_ACPI_EC3_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xD8) +#define MCHP_LPC_ACPI_EC3_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xDA) +#define MCHP_LPC_ACPI_EC3_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xDC) +#define MCHP_LPC_ACPI_EC4_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xDE) +#define MCHP_LPC_ACPI_EC4_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE0) +#define MCHP_LPC_ACPI_EC4_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE2) +#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xE4) +#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xE6) +#define MCHP_LPC_ACPI_EMI0_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xE8) +#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xEA) +#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xEC) +#define MCHP_LPC_ACPI_EMI1_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xEE) +#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H0 REG32(MCHP_LPC_CFG_BASE + 0xF0) +#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H1 REG32(MCHP_LPC_CFG_BASE + 0xF2) +#define MCHP_LPC_ACPI_EMI2_MEM_BAR_H2 REG32(MCHP_LPC_CFG_BASE + 0xF4) + +#define MCHP_LPC_BUS_MONITOR REG32(MCHP_LPC_RT_BASE + 0x4) +#define MCHP_LPC_HOST_ERROR REG32(MCHP_LPC_RT_BASE + 0x8) +#define MCHP_LPC_EC_SERIRQ REG32(MCHP_LPC_RT_BASE + 0xC) +#define MCHP_LPC_EC_CLK_CTRL REG32(MCHP_LPC_RT_BASE + 0x10) +#define MCHP_LPC_BAR_INHIBIT REG32(MCHP_LPC_RT_BASE + 0x20) +#define MCHP_LPC_BAR_INIT REG32(MCHP_LPC_RT_BASE + 0x30) +#define MCHP_LPC_SRAM0_BAR REG32(MCHP_LPC_RT_BASE + 0xf8) +#define MCHP_LPC_SRAM1_BAR REG32(MCHP_LPC_RT_BASE + 0xfc) /* eSPI */ /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */ -#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 -#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 -#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 -#define MCHP_ESPI_IO_BAR_ID_8042 3 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8 -#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 -#define MCHP_ESPI_IO_BAR_ID_P92 0xA -#define MCHP_ESPI_IO_BAR_ID_UART0 0xB -#define MCHP_ESPI_IO_BAR_ID_UART1 0xC -#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD -#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE -#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF -#define MCHP_ESPI_IO_BAR_P80_0 0x10 -#define MCHP_ESPI_IO_BAR_P80_1 0x11 -#define MCHP_ESPI_IO_BAR_RTC 0x12 +#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 +#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 +#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 +#define MCHP_ESPI_IO_BAR_ID_8042 3 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8 +#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 +#define MCHP_ESPI_IO_BAR_ID_P92 0xA +#define MCHP_ESPI_IO_BAR_ID_UART0 0xB +#define MCHP_ESPI_IO_BAR_ID_UART1 0xC +#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD +#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE +#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF +#define MCHP_ESPI_IO_BAR_P80_0 0x10 +#define MCHP_ESPI_IO_BAR_P80_1 0x11 +#define MCHP_ESPI_IO_BAR_RTC 0x12 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */ -#define MCHP_ESPI_MBAR_ID_MBOX 0 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5 -#define MCHP_ESPI_MBAR_ID_EMI_0 6 -#define MCHP_ESPI_MBAR_ID_EMI_1 7 -#define MCHP_ESPI_MBAR_ID_EMI_2 8 +#define MCHP_ESPI_MBAR_ID_MBOX 0 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5 +#define MCHP_ESPI_MBAR_ID_EMI_0 6 +#define MCHP_ESPI_MBAR_ID_EMI_1 7 +#define MCHP_ESPI_MBAR_ID_EMI_2 8 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */ -#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ -#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ -#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ -#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ -#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 -#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 -#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 -#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 -#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8 -#define MCHP_ESPI_SIRQ_UART0 9 -#define MCHP_ESPI_SIRQ_UART1 10 -#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ -#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ -#define MCHP_ESPI_SIRQ_EMI1_HEV 13 -#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 -#define MCHP_ESPI_SIRQ_EMI2_HEV 15 -#define MCHP_ESPI_SIRQ_EMI2_EC2H 16 -#define MCHP_ESPI_SIRQ_RTC 17 -#define MCHP_ESPI_SIRQ_EC 18 +#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ +#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ +#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ +#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ +#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 +#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 +#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 +#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 +#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8 +#define MCHP_ESPI_SIRQ_UART0 9 +#define MCHP_ESPI_SIRQ_UART1 10 +#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ +#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ +#define MCHP_ESPI_SIRQ_EMI1_HEV 13 +#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 +#define MCHP_ESPI_SIRQ_EMI2_HEV 15 +#define MCHP_ESPI_SIRQ_EMI2_EC2H 16 +#define MCHP_ESPI_SIRQ_RTC 17 +#define MCHP_ESPI_SIRQ_EC 18 #define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE) #define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul) @@ -1259,22 +1243,22 @@ enum MCHP_i2c_port { * eSPI RESET, channel enables and operations except Master-to-Slave * WWires are all on GIRQ19 */ -#define MCHP_ESPI_GIRQ 19 -#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) -#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) -#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) -#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) -#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) -#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) -#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) -#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) -#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) +#define MCHP_ESPI_GIRQ 19 +#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) +#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) +#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) +#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) +#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) +#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) +#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) +#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) +#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) /* * eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */ -#define MCHP_ESPI_MSVW_0_6_GIRQ 24 -#define MCHP_ESPI_MSVW_7_10_GIRQ 25 +#define MCHP_ESPI_MSVW_0_6_GIRQ 24 +#define MCHP_ESPI_MSVW_7_10_GIRQ 25 /* * Four source bits, SRC[0:3] per Master-to-Slave register * v = MSVW [0:10] @@ -1283,12 +1267,12 @@ enum MCHP_i2c_port { #define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0)) #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \ - (((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n)))) + (((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n)))) /* DMA */ -#define MCHP_DMA_MAX_CHAN 14 -#define MCHP_DMA_CH_OFS 0x40 -#define MCHP_DMA_CH_OFS_BITPOS 6 +#define MCHP_DMA_MAX_CHAN 14 +#define MCHP_DMA_CH_OFS 0x40 +#define MCHP_DMA_CH_OFS_BITPOS 6 #define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS) /* @@ -1322,20 +1306,20 @@ enum dma_channel { * Peripheral device DMA Device ID's for bits [15:9] * in DMA channel control register. */ -#define MCHP_DMA_I2C0_SLV_REQ_ID 0 -#define MCHP_DMA_I2C0_MTR_REQ_ID 1 -#define MCHP_DMA_I2C1_SLV_REQ_ID 2 -#define MCHP_DMA_I2C1_MTR_REQ_ID 3 -#define MCHP_DMA_I2C2_SLV_REQ_ID 4 -#define MCHP_DMA_I2C2_MTR_REQ_ID 5 -#define MCHP_DMA_I2C3_SLV_REQ_ID 6 -#define MCHP_DMA_I2C3_MTR_REQ_ID 7 -#define MCHP_DMA_SPI0_TX_REQ_ID 8 -#define MCHP_DMA_SPI0_RX_REQ_ID 9 -#define MCHP_DMA_SPI1_TX_REQ_ID 10 -#define MCHP_DMA_SPI1_RX_REQ_ID 11 -#define MCHP_DMA_QMSPI0_TX_REQ_ID 12 -#define MCHP_DMA_QMSPI0_RX_REQ_ID 13 +#define MCHP_DMA_I2C0_SLV_REQ_ID 0 +#define MCHP_DMA_I2C0_MTR_REQ_ID 1 +#define MCHP_DMA_I2C1_SLV_REQ_ID 2 +#define MCHP_DMA_I2C1_MTR_REQ_ID 3 +#define MCHP_DMA_I2C2_SLV_REQ_ID 4 +#define MCHP_DMA_I2C2_MTR_REQ_ID 5 +#define MCHP_DMA_I2C3_SLV_REQ_ID 6 +#define MCHP_DMA_I2C3_MTR_REQ_ID 7 +#define MCHP_DMA_SPI0_TX_REQ_ID 8 +#define MCHP_DMA_SPI0_RX_REQ_ID 9 +#define MCHP_DMA_SPI1_TX_REQ_ID 10 +#define MCHP_DMA_SPI1_RX_REQ_ID 11 +#define MCHP_DMA_QMSPI0_TX_REQ_ID 12 +#define MCHP_DMA_QMSPI0_RX_REQ_ID 13 /* * Hardware delay register. -- cgit v1.2.1 From 432a229f9cd1ab8b7e6efea5a6d3487f90b9f8eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:00 -0600 Subject: baseboard/octopus/variant_usbc_standalone_tcpcs.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If213fb3f2e412e33953ac810dba7b47dce81b085 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727942 Reviewed-by: Jeremy Bettis --- baseboard/octopus/variant_usbc_standalone_tcpcs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c index d26e234c4b..9ab2b8f9e2 100644 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c @@ -21,8 +21,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) /******************************************************************************/ /* USB-C TPCP Configuration */ -- cgit v1.2.1 From 338b93d7a425817f2fb9f5358410c7c4ba782a1c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:46 -0600 Subject: baseboard/honeybuns/usbc_support.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iae5d633fdaffe1b33fc5088b21b7fb03d9aa9c24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727891 Reviewed-by: Jeremy Bettis --- baseboard/honeybuns/usbc_support.c | 50 +++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 28 deletions(-) diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c index c03e94f076..6082ff0715 100644 --- a/baseboard/honeybuns/usbc_support.c +++ b/baseboard/honeybuns/usbc_support.c @@ -23,8 +23,8 @@ #include "registers.h" #include "ucpd-stm32gx.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) enum usbc_states { UNATTACHED_SNK, @@ -39,7 +39,7 @@ static int usbc_vbus; static enum tcpc_cc_voltage_status cc1_v; static enum tcpc_cc_voltage_status cc2_v; -__maybe_unused static __const_data const char * const usbc_state_names[] = { +__maybe_unused static __const_data const char *const usbc_state_names[] = { [UNATTACHED_SNK] = "Unattached.SNK", [ATTACH_WAIT_SNK] = "AttachWait.SNK", [ATTACHED_SNK] = "Attached.SNK", @@ -48,17 +48,13 @@ __maybe_unused static __const_data const char * const usbc_state_names[] = { static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int baseboard_ppc_enable_sink_path(int port) @@ -126,9 +122,9 @@ static void baseboard_ucpd_apply_rd(int port) */ cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) | - STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | - STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | - STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); + STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) | + STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) | + STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1); STM32_UCPD_CFGR1(port) = cfgr1_reg; /* Enable ucpd */ @@ -147,9 +143,8 @@ static void baseboard_ucpd_apply_rd(int port) STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS; } - static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int vstate_cc1; int vstate_cc2; @@ -163,7 +158,7 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, * * vstate_cc maps directly to cc_state from tcpci spec when ANAMODE = 1, * but needs to be modified slightly for case ANAMODE = 0. - * + * * If presenting Rp (source), then need to to a circular shift of * vstate_ccx value: * vstate_cc | cc_state @@ -178,9 +173,9 @@ static void baseboard_ucpd_get_cc(int port, enum tcpc_cc_voltage_status *cc1, /* Get Rp or Rd active */ anamode = !!(STM32_UCPD_CR(port) & STM32_UCPD_CR_ANAMODE); vstate_cc1 = (sr & STM32_UCPD_SR_VSTATE_CC1_MASK) >> - STM32_UCPD_SR_VSTATE_CC1_SHIFT; + STM32_UCPD_SR_VSTATE_CC1_SHIFT; vstate_cc2 = (sr & STM32_UCPD_SR_VSTATE_CC2_MASK) >> - STM32_UCPD_SR_VSTATE_CC2_SHIFT; + STM32_UCPD_SR_VSTATE_CC2_SHIFT; /* Do circular shift if port == source */ if (anamode) { @@ -325,10 +320,8 @@ int c1_ps8805_is_sourcing_vbus(int port) return level; } - int c1_ps8805_vbus_source_enable(int port, int enable) { - return ps8805_gpio_set_level(port, PS8805_GPIO_1, enable); } @@ -358,12 +351,13 @@ static void baseboard_usb3_manage_vbus(void) ppc_ocp_count = 0; #ifdef GPIO_USB_HUB_OCP_NOTIFY - /* - * In the case of an OCP event on this port, the usb hub should be - * notified via a GPIO signal. Following, an OCP, the attached.src state - * for the usb3 only port is checked again. If it's attached, then make - * sure the OCP notify signal is reset. - */ + /* + * In the case of an OCP event on this port, the usb hub should + * be notified via a GPIO signal. Following, an OCP, the + * attached.src state for the usb3 only port is checked again. + * If it's attached, then make sure the OCP notify signal is + * reset. + */ gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 1); #endif } @@ -436,8 +430,9 @@ static void baseboard_usbc_usb3_handle_interrupt(void) CPRINTS("usb3_ppc: VBUS OC!"); gpio_set_level(GPIO_USB_HUB_OCP_NOTIFY, 0); if (++ppc_ocp_count < 5) - hook_call_deferred(&baseboard_usb3_manage_vbus_data, - USB_HUB_OCP_RESET_MSEC); + hook_call_deferred( + &baseboard_usb3_manage_vbus_data, + USB_HUB_OCP_RESET_MSEC); else CPRINTS("usb3_ppc: VBUS OC limit reached!"); } @@ -466,7 +461,6 @@ static void baseboard_usbc_usb3_handle_interrupt(void) /* Clear the interrupt sources. */ write_reg(port, SN5S330_INT_TRIP_RISE_REG2, rise); write_reg(port, SN5S330_INT_TRIP_FALL_REG2, fall); - } } DECLARE_DEFERRED(baseboard_usbc_usb3_handle_interrupt); -- cgit v1.2.1 From b80f0923ce0cf74387c6ff4329030d4893dbd750 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:38 -0600 Subject: board/fusb307bgevb/lcd.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6dfb071c1d5c39fd57a1c9a51ae627178b4da212 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728382 Reviewed-by: Jeremy Bettis --- board/fusb307bgevb/lcd.h | 66 ++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/board/fusb307bgevb/lcd.h b/board/fusb307bgevb/lcd.h index 21b0ee9ce9..f25e6852e6 100644 --- a/board/fusb307bgevb/lcd.h +++ b/board/fusb307bgevb/lcd.h @@ -11,50 +11,50 @@ #include "common.h" /* commands */ -#define LCD_CLEAR_DISPLAY BIT(0) -#define LCD_RETURN_HOME BIT(1) -#define LCD_ENTRYMODE_SET BIT(2) -#define LCD_DISPLAY_CONTROL BIT(3) -#define LCD_CURSOR_SHIFT BIT(4) -#define LCD_FUNCTION_SET BIT(5) -#define LCD_SET_CGRAMADDR BIT(6) -#define LCD_SET_DDRAMADDR BIT(7) +#define LCD_CLEAR_DISPLAY BIT(0) +#define LCD_RETURN_HOME BIT(1) +#define LCD_ENTRYMODE_SET BIT(2) +#define LCD_DISPLAY_CONTROL BIT(3) +#define LCD_CURSOR_SHIFT BIT(4) +#define LCD_FUNCTION_SET BIT(5) +#define LCD_SET_CGRAMADDR BIT(6) +#define LCD_SET_DDRAMADDR BIT(7) /* flags for display entry mode */ -#define LCD_ENTRY_RIGHT 0x00 -#define LCD_ENTRY_LEFT BIT(1) -#define LCD_ENTRY_SHIFT_INCREMENT BIT(0) -#define LCD_ENTRY_SHIFT_DECREMENT 0x00 +#define LCD_ENTRY_RIGHT 0x00 +#define LCD_ENTRY_LEFT BIT(1) +#define LCD_ENTRY_SHIFT_INCREMENT BIT(0) +#define LCD_ENTRY_SHIFT_DECREMENT 0x00 /* flags for display on/off control */ -#define LCD_DISPLAY_ON BIT(2) -#define LCD_DISPLAY_OFF 0x00 -#define LCD_CURSOR_ON BIT(1) -#define LCD_CURSOR_OFF 0x00 -#define LCD_BLINK_ON BIT(0) -#define LCD_BLINK_OFF 0x00 +#define LCD_DISPLAY_ON BIT(2) +#define LCD_DISPLAY_OFF 0x00 +#define LCD_CURSOR_ON BIT(1) +#define LCD_CURSOR_OFF 0x00 +#define LCD_BLINK_ON BIT(0) +#define LCD_BLINK_OFF 0x00 /* flags for display/cursor shift */ -#define LCD_DISPLAY_MOVE BIT(3) -#define LCD_CURSOR_MOVE 0x00 -#define LCD_MOVE_RIGHT BIT(2) -#define LCD_MOVE_LEFT 0x00 +#define LCD_DISPLAY_MOVE BIT(3) +#define LCD_CURSOR_MOVE 0x00 +#define LCD_MOVE_RIGHT BIT(2) +#define LCD_MOVE_LEFT 0x00 /* flags for function set */ -#define LCD_8BITMODE BIT(4) -#define LCD_4BITMODE 0x00 -#define LCD_2LINE BIT(3) -#define LCD_1LINE 0x00 -#define LCD_5X10DOTS BIT(2) -#define LCD_5X8DOTS 0x00 +#define LCD_8BITMODE BIT(4) +#define LCD_4BITMODE 0x00 +#define LCD_2LINE BIT(3) +#define LCD_1LINE 0x00 +#define LCD_5X10DOTS BIT(2) +#define LCD_5X8DOTS 0x00 /* flags for backlight control */ -#define LCD_BACKLIGHT BIT(3) -#define LCD_NO_BACKLIGHT 0x00 +#define LCD_BACKLIGHT BIT(3) +#define LCD_NO_BACKLIGHT 0x00 -#define LCD_EN BIT(2) /* Enable bit */ -#define LCD_RW BIT(1) /* Read/Write bit */ -#define LCD_RS BIT(0) /* Register select bit */ +#define LCD_EN BIT(2) /* Enable bit */ +#define LCD_RW BIT(1) /* Read/Write bit */ +#define LCD_RS BIT(0) /* Register select bit */ void lcd_init(uint8_t cols, uint8_t rows, uint8_t dotsize); void lcd_set_cursor(uint8_t col, uint8_t row); -- cgit v1.2.1 From 272998287bd031bbd17a587d198e0a20cbbcda77 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:45 -0600 Subject: driver/ioexpander/pca9675.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icc4adece0636103205da07ecf0ddf1b7ebf8bba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729992 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pca9675.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/ioexpander/pca9675.c b/driver/ioexpander/pca9675.c index f9e83b48c5..a2a13110b9 100644 --- a/driver/ioexpander/pca9675.c +++ b/driver/ioexpander/pca9675.c @@ -21,8 +21,8 @@ static struct pca9675_ioexpander pca9675_iox[CONFIG_IO_EXPANDER_PORT_COUNT]; static int pca9675_read16(int ioex, uint16_t *data) { return i2c_xfer(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, - NULL, 0, (uint8_t *)data, 2); + ioex_config[ioex].i2c_addr_flags, NULL, 0, + (uint8_t *)data, 2); } static int pca9675_write16(int ioex, uint16_t data) @@ -35,22 +35,21 @@ static int pca9675_write16(int ioex, uint16_t data) data |= pca9675_iox[ioex].io_direction; return i2c_xfer(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, - (uint8_t *)&data, 2, NULL, 0); + ioex_config[ioex].i2c_addr_flags, (uint8_t *)&data, 2, + NULL, 0); } static int pca9675_reset(int ioex) { uint8_t reset = PCA9675_RESET_SEQ_DATA; - return i2c_xfer(ioex_config[ioex].i2c_host_port, - 0, &reset, 1, NULL, 0); + return i2c_xfer(ioex_config[ioex].i2c_host_port, 0, &reset, 1, NULL, 0); } static int pca9675_get_flags_by_mask(int ioex, int port, int mask, int *flags) { - *flags = mask & pca9675_iox[ioex].io_direction ? - GPIO_INPUT : GPIO_OUTPUT; + *flags = mask & pca9675_iox[ioex].io_direction ? GPIO_INPUT : + GPIO_OUTPUT; return EC_SUCCESS; } @@ -129,13 +128,13 @@ static int pca9675_get_port(int ioex, int port, int *val) #endif const struct ioexpander_drv pca9675_ioexpander_drv = { - .init = &pca9675_init, - .get_level = &pca9675_get_level, - .set_level = &pca9675_set_level, - .get_flags_by_mask = &pca9675_get_flags_by_mask, - .set_flags_by_mask = &pca9675_set_flags_by_mask, - .enable_interrupt = &pca9675_enable_interrupt, + .init = &pca9675_init, + .get_level = &pca9675_get_level, + .set_level = &pca9675_set_level, + .get_flags_by_mask = &pca9675_get_flags_by_mask, + .set_flags_by_mask = &pca9675_set_flags_by_mask, + .enable_interrupt = &pca9675_enable_interrupt, #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT - .get_port = &pca9675_get_port, + .get_port = &pca9675_get_port, #endif }; -- cgit v1.2.1 From b18c1f11c44e43a82e2fa5187bd8eceecda4fd98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:36 -0600 Subject: power/cometlake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I990f675f2f65aa8456dd907083854131eda195df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727057 Reviewed-by: Jeremy Bettis --- power/cometlake.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/power/cometlake.c b/power/cometlake.c index 3c127b0c03..481e7dc51a 100644 --- a/power/cometlake.c +++ b/power/cometlake.c @@ -15,7 +15,7 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Power signals list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -53,12 +53,12 @@ const struct power_signal_info power_signal_list[] = { }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); -static int forcing_shutdown; /* Forced shutdown in progress? */ +static int forcing_shutdown; /* Forced shutdown in progress? */ /* Default no action, overwrite it in board.c if necessary*/ __overridable void board_chipset_forced_shutdown(void) { - return; + return; } void chipset_force_shutdown(enum chipset_shutdown_reason reason) @@ -84,7 +84,7 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) /* For b:143440730, stop checking GPIO_ALL_SYS_PGOOD if system is * already force to G3. - */ + */ board_chipset_forced_shutdown(); /* Need to wait a min of 10 msec before check for power good */ @@ -92,7 +92,8 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) /* Now wait for PP5000_A and RSMRST_L to go low */ while ((gpio_get_level(GPIO_PP5000_A_PG_OD) || - power_has_signals(IN_PGOOD_ALL_CORE)) && (timeout_ms > 0)) { + power_has_signals(IN_PGOOD_ALL_CORE)) && + (timeout_ms > 0)) { msleep(1); timeout_ms--; }; @@ -155,7 +156,6 @@ void chipset_pre_init_callback(void) enum power_state power_handle_state(enum power_state state) { - int all_sys_pwrgd_in; int all_sys_pwrgd_out; @@ -176,7 +176,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_S5: if (forcing_shutdown) { power_button_pch_release(); -- cgit v1.2.1 From 26efc313c368ccac2483acf62dd57c73190f29ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:51 -0600 Subject: chip/host/trng.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic32b80e3807336a9d293824bfa7977680e181423 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729169 Reviewed-by: Jeremy Bettis --- chip/host/trng.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/host/trng.c b/chip/host/trng.c index 8407aa6ea1..d54983f3a1 100644 --- a/chip/host/trng.c +++ b/chip/host/trng.c @@ -35,6 +35,6 @@ test_mockable void rand_bytes(void *buffer, size_t len) { uint8_t *b, *end; - for (b = buffer, end = b+len; b != end; b++) + for (b = buffer, end = b + len; b != end; b++) *b = (uint8_t)rand_r(&seed); } -- cgit v1.2.1 From f244bc291264d682980d20c58b6020794745266b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:59 -0600 Subject: board/ambassador/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I419c32bdb7c718371ca542cbb2a65691dfb2f0fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727980 Reviewed-by: Jeremy Bettis --- board/ambassador/board.c | 179 +++++++++++++++++++++-------------------------- 1 file changed, 79 insertions(+), 100 deletions(-) diff --git a/board/ambassador/board.c b/board/ambassador/board.c index 5cf319bc79..360dab72e4 100644 --- a/board/ambassador/board.c +++ b/board/ambassador/board.c @@ -45,8 +45,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -88,8 +88,8 @@ uint16_t tcpc_get_alert_status(void) } /* Called when the charge manager has switched to a new port. */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = @@ -105,14 +105,14 @@ static int32_t base_5v_power; * Power usage for each port as measured or estimated. * Units are milliwatts (5v x ma current) */ -#define PWR_BASE_LOAD (5*1335) -#define PWR_FRONT_HIGH (5*1603) -#define PWR_FRONT_LOW (5*963) -#define PWR_REAR (5*1075) -#define PWR_HDMI (5*562) -#define PWR_C_HIGH (5*3740) -#define PWR_C_LOW (5*2090) -#define PWR_MAX (5*10000) +#define PWR_BASE_LOAD (5 * 1335) +#define PWR_FRONT_HIGH (5 * 1603) +#define PWR_FRONT_LOW (5 * 963) +#define PWR_REAR (5 * 1075) +#define PWR_HDMI (5 * 562) +#define PWR_C_HIGH (5 * 3740) +#define PWR_C_LOW (5 * 2090) +#define PWR_MAX (5 * 10000) /* * Update the 5V power usage, assuming no throttling, @@ -185,16 +185,14 @@ static const struct { int current; } bj_power[] = { { /* 0 - 65W (also default) */ - .voltage = 19000, - .current = 3420 - }, + .voltage = 19000, + .current = 3420 }, { /* 1 - 90W */ - .voltage = 19000, - .current = 4740 - }, + .voltage = 19000, + .current = 4740 }, }; -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -239,27 +237,25 @@ static void adp_state_init(void) } DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); - #include "gpio_list.h" /* Must come after other header files. */ /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, - [PWM_CH_LED_RED] = { .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, - [PWM_CH_LED_WHITE] = { .channel = 2, - .flags = PWM_CONFIG_DSLEEP, - .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_LED_WHITE] = { .channel = 2, + .flags = PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; /******************************************************************************/ @@ -286,41 +282,31 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "ina", - .port = I2C_PORT_INA, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "ppc0", - .port = I2C_PORT_PPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 400, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "ina", + .port = I2C_PORT_INA, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "ppc0", + .port = I2C_PORT_PPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 400, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -376,15 +362,14 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /******************************************************************************/ /* Wake up pins */ -const enum gpio_signal hibernate_wake_pins[] = { -}; +const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -403,7 +388,7 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -412,8 +397,8 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ @@ -432,8 +417,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B \ - { \ +#define THERMAL_B \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(78), \ @@ -535,16 +520,13 @@ static void board_chipset_startup(void) if (ppc_is_sourcing_vbus(0)) ppc_vbus_source_enable(0, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); /******************************************************************************/ /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_TCPC_0] = { - .i2c_port = I2C_PORT_PPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_TCPC_0] = { .i2c_port = I2C_PORT_PPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -577,14 +559,12 @@ static void board_tcpc_init(void) /* * By default configured as output low. */ - gpio_set_flags(GPIO_USB_A4_OC_ODL, - GPIO_INPUT | GPIO_INT_BOTH); + gpio_set_flags(GPIO_USB_A4_OC_ODL, GPIO_INPUT | GPIO_INT_BOTH); gpio_enable_interrupt(GPIO_USB_A4_OC_ODL); } else { /* Ensure no interrupts from pin */ gpio_disable_interrupt(GPIO_USB_A4_OC_ODL); } - } /* Make sure this is called after fw_config is initialised */ DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2); @@ -703,8 +683,8 @@ void board_enable_s0_rails(int enable) unsigned int ec_config_get_bj_power(void) { - unsigned int bj = - (fw_config & EC_CFG_BJ_POWER_MASK) >> EC_CFG_BJ_POWER_L; + unsigned int bj = (fw_config & EC_CFG_BJ_POWER_MASK) >> + EC_CFG_BJ_POWER_L; /* Out of range value defaults to 0 */ if (bj >= ARRAY_SIZE(bj_power)) bj = 0; @@ -779,23 +759,23 @@ DECLARE_HOOK(HOOK_INIT, setup_thermal, HOOK_PRIO_DEFAULT - 1); * * All measurements are in milliwatts. */ -#define THROT_TYPE_A BIT(0) -#define THROT_TYPE_C BIT(1) -#define THROT_PROCHOT BIT(2) +#define THROT_TYPE_A BIT(0) +#define THROT_TYPE_C BIT(1) +#define THROT_PROCHOT BIT(2) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) static void power_monitor(void) { @@ -810,8 +790,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -839,7 +818,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -866,8 +845,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -959,8 +937,9 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); -- cgit v1.2.1 From 3bdfeba224ba2f64a77d13fd0079d2f185f9cc87 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:34 -0600 Subject: board/gingerbread/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icdba7c742504ee0dd0a35bc4e560301a9faaab9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728422 Reviewed-by: Jeremy Bettis --- board/gingerbread/board.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/gingerbread/board.h b/board/gingerbread/board.h index cfc5bbf0a0..9951271372 100644 --- a/board/gingerbread/board.h +++ b/board/gingerbread/board.h @@ -20,7 +20,6 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ #undef CONFIG_FLASH_PSTATE_LOCKED - #define CONFIG_WP_ACTIVE_HIGH /* Console */ @@ -29,8 +28,8 @@ #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX /* USB Type C and USB PD defines */ -#define USB_PD_PORT_HOST 0 -#define USB_PD_PORT_DP 1 +#define USB_PD_PORT_HOST 0 +#define USB_PD_PORT_DP 1 #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_MUX_TUSB1064 @@ -44,13 +43,13 @@ #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 /* I2C port names */ -#define I2C_PORT_I2C1 0 -#define I2C_PORT_I2C2 1 -#define I2C_PORT_I2C3 2 +#define I2C_PORT_I2C1 0 +#define I2C_PORT_I2C2 1 +#define I2C_PORT_I2C3 2 /* Required symbolic I2C port names */ #define I2C_PORT_MP4245 I2C_PORT_I2C3 #define I2C_PORT_EEPROM I2C_PORT_I2C1 -#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS +#define MP4245_I2C_ADDR_FLAGS MP4245_I2C_ADDR_0_FLAGS /* * Macros for GPIO signals used in common code that don't match the @@ -58,9 +57,9 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_WP GPIO_EC_WP_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_WP GPIO_EC_WP_L /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL @@ -80,7 +79,7 @@ #define GPIO_TRIGGER_1 GPIO_USB3_A1_CDP_EN #define GPIO_TRIGGER_2 GPIO_USB3_A2_CDP_EN -enum debug_gpio { +enum debug_gpio { TRIGGER_1 = 0, TRIGGER_2, }; -- cgit v1.2.1 From b325538a3dedb7b89680e0d9385899638afd529e Mon Sep 17 00:00:00 2001 From: Bobby Casey Date: Mon, 22 Feb 2021 10:42:20 -0800 Subject: cortex-m: Don't execute WFI instruction if debugging Allowing the processor to sleep causes the debugger to stop working. BRANCH=none BUG=b:180144572 TEST=Monitor power per go/cros-fpmcu-source-code-docs#dragonclaw-v0_2 TEST=Icetower (pp3300_dx_mcu_mw) with no debugger connected Idle: ~44 mW Low Power Mode: ~5.5 mW TEST=Icetower (pp3300_dx_mcu_mw) with debugger connected Idle: ~75 mW Low Power Mode: ~70 mW TEST=Dragonclaw (pp3300_dx_mcu_mw) with no debugger connected Idle: ~22 mW Low Power Mode: ~1.5 mW TEST=Dragonclaw (pp3300_dx_mcu_mw) with debugger connected Idle: ~64 mW Low Power Mode: ~19 mW Signed-off-by: Bobby Casey Change-Id: I48d58395b168dc3bb0932348cd8f5ce088fc0ac9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713754 Commit-Queue: Tom Hughes Tested-by: Tom Hughes Reviewed-by: Tom Hughes --- chip/mchp/clock.c | 4 ++-- chip/mchp/system.c | 2 +- chip/mec1322/clock.c | 6 ++---- chip/mec1322/system.c | 2 +- chip/stm32/clock-stm32f0.c | 6 +++--- chip/stm32/clock-stm32f4.c | 4 ++-- chip/stm32/clock-stm32h7.c | 4 ++-- chip/stm32/clock-stm32l4.c | 4 ++-- core/cortex-m/cpu.h | 9 +++++++++ core/cortex-m/task.c | 3 ++- core/cortex-m0/cpu.h | 9 +++++++++ core/cortex-m0/task.c | 2 +- 12 files changed, 36 insertions(+), 19 deletions(-) diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index 0a9a8f219c..3b3cd2d6af 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -630,7 +630,7 @@ void __idle(void) /* Wait for interrupt: goes into deep sleep. */ asm("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); asm("isb"); asm("nop"); @@ -671,7 +671,7 @@ void __idle(void) idle_sleep_cnt++; - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); diff --git a/chip/mchp/system.c b/chip/mchp/system.c index 72c96bef8f..1a9b3f6bc7 100644 --- a/chip/mchp/system.c +++ b/chip/mchp/system.c @@ -549,7 +549,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) MCHP_PCR_SYS_SLP_CTL = MCHP_PCR_SYS_SLP_ALL; asm("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); asm("isb"); asm("nop"); diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index 1fcf8fd199..04ee90ee98 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -362,7 +362,7 @@ void __idle(void) } /* Wait for interrupt: goes into deep sleep. */ - asm("wfi"); + cpu_enter_suspend_mode(); if (uart_ready_for_deepsleep) { resume_from_deep_sleep(); @@ -397,10 +397,8 @@ void __idle(void) } } else { /* CPU 'Sleep' mode */ - idle_sleep_cnt++; - - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index acf47eb371..3045cd6cff 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -353,7 +353,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) } } - asm("wfi"); + cpu_enter_suspend_mode(); /* Use 48MHz clock to speed through wake-up */ MEC1322_PCR_PROC_CLK_CTL = 1; diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 5a57e289fa..9896696227 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -267,7 +267,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) STM32_PWR_CR |= 0xe; CPU_SCB_SYSCTRL |= 0x4; /* go to Standby mode */ - asm("wfi"); + cpu_enter_suspend_mode(); /* we should never reach that point */ while (1) @@ -332,7 +332,7 @@ void __idle(void) set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0, 0); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -370,7 +370,7 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } #ifdef CONFIG_LOW_POWER_IDLE_LIMITED en_int: diff --git a/chip/stm32/clock-stm32f4.c b/chip/stm32/clock-stm32f4.c index bc403f8b69..6d8461afc1 100644 --- a/chip/stm32/clock-stm32f4.c +++ b/chip/stm32/clock-stm32f4.c @@ -543,7 +543,7 @@ void __idle(void) /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -576,7 +576,7 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 57dc170dd9..6c4c42d59b 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -544,7 +544,7 @@ void __idle(void) /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -579,7 +579,7 @@ void __idle(void) idle_sleep_cnt++; /* normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 730f5d6bb9..5a4de3a581 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -1063,7 +1063,7 @@ void __idle(void) /* ensure outstanding memory transactions complete */ asm volatile("dsb"); - asm("wfi"); + cpu_enter_suspend_mode(); CPU_SCB_SYSCTRL &= ~0x4; @@ -1101,7 +1101,7 @@ void __idle(void) idle_sleep_cnt++; /* Normal idle : only CPU clock stopped */ - asm("wfi"); + cpu_enter_suspend_mode(); } interrupt_enable(); } diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index c7645ac20d..dd6c11d4f6 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -10,6 +10,7 @@ #include #include "compile_time_macros.h" +#include "debug.h" /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t *)(addr)) @@ -137,4 +138,12 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) (priority << prio_shift); } +static inline void cpu_enter_suspend_mode(void) +{ + /* Preserve debug sessions by not suspending when connected */ + if (!debugger_is_connected()) { + asm("wfi"); + } +} + #endif /* __CROS_EC_CPU_H */ diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 2ec1ec1dc2..0747978f7e 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -9,6 +9,7 @@ #include "common.h" #include "console.h" #include "cpu.h" +#include "debug.h" #include "link_defs.h" #include "panic.h" #include "task.h" @@ -105,7 +106,7 @@ void __idle(void) * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). */ - asm("wfi"); + cpu_enter_suspend_mode(); #endif } } diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 48abf916d6..0fc2e655d4 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -10,6 +10,7 @@ #include #include "compile_time_macros.h" +#include "debug.h" /* Macro to access 32-bit registers */ #define CPUREG(addr) (*(volatile uint32_t *)(addr)) @@ -61,4 +62,12 @@ static inline void cpu_set_interrupt_priority(uint8_t irq, uint8_t priority) (priority << prio_shift); } +static inline void cpu_enter_suspend_mode(void) +{ + /* Preserve debug sessions by not suspending when connected */ + if (!debugger_is_connected()) { + asm("wfi"); + } +} + #endif /* __CROS_EC_CPU_H */ diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index 5eb67c7346..4837c2dfbd 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -72,7 +72,7 @@ void __idle(void) * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). */ - asm("wfi"); + cpu_enter_suspend_mode(); } } #endif /* !CONFIG_LOW_POWER_IDLE */ -- cgit v1.2.1 From 926949a4f57e7c32bc4f112afad893a6a51c10a8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:02 -0600 Subject: chip/npcx/gpio-npcx9.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4fc78ae49f438a1a0dacfc1867a49400eb38c408 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729394 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio-npcx9.c | 61 +++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index b567f1d1c8..795cf3b147 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -51,11 +51,11 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); * the port, then call the master handler above. */ -#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ -static void _irq_func(void) \ -{ \ - gpio_interrupt(wui_int); \ -} +#define GPIO_IRQ_FUNC(_irq_func, wui_int) \ + static void _irq_func(void) \ + { \ + gpio_interrupt(wui_int); \ + } /* If we need to handle the other type interrupts except GPIO, add code here */ static void __gpio_host_interrupt(void) @@ -63,7 +63,7 @@ static void __gpio_host_interrupt(void) if (IS_ENABLED(CONFIG_HOSTCMD_X86)) { /* Pending bit 7 or 6 or 5? */ if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6) && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 6)) { /* Disable host wake-up */ CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); /* Clear pending bit of WUI */ @@ -71,16 +71,18 @@ static void __gpio_host_interrupt(void) return; } if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 5)) { espi_espirst_handler(); return; } } else { - if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) - && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) { + if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), + 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), + 7)) { lpc_lreset_pltrst_handler(); return; } @@ -130,7 +132,6 @@ static void __gpio_cr_sin2_interrupt(void) } #endif gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_1)); - } static void __gpio_wk1h_interrupt(void) @@ -181,32 +182,32 @@ GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); #ifdef NPCX_SELECT_KSI_TO_GPIO -DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); #ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to * accommodate P3 CS interrupt. */ -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #else -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3); #undef GPIO_IRQ_FUNC -- cgit v1.2.1 From 9067cd82daafc2c733d93cb1ebd582e8b9360074 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:50 -0600 Subject: driver/tcpm/it8xxx2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a256c665807b330f3aa3078c4a61b0925a64c59 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730093 Reviewed-by: Jeremy Bettis --- driver/tcpm/it8xxx2.c | 189 ++++++++++++++++++++++++++------------------------ 1 file changed, 97 insertions(+), 92 deletions(-) diff --git a/driver/tcpm/it8xxx2.c b/driver/tcpm/it8xxx2.c index e1d4ad5d5c..3e634c8430 100644 --- a/driver/tcpm/it8xxx2.c +++ b/driver/tcpm/it8xxx2.c @@ -22,8 +22,8 @@ #ifdef CONFIG_USB_PD_TCPMV1 #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \ - defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \ - defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ + defined(CONFIG_USB_PD_VBUS_DETECT_TCPC) || \ + defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) #error "Unsupported config options of IT8xxx2 PD driver" #endif @@ -36,17 +36,17 @@ #endif #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) bool rx_en[IT83XX_USBPD_PHY_PORT_COUNT]; STATIC_IF(CONFIG_USB_PD_DECODE_SOP) - bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT]; -static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = {0}; +bool sop_prime_en[IT83XX_USBPD_PHY_PORT_COUNT]; +static uint8_t tx_error_status[IT83XX_USBPD_PHY_PORT_COUNT] = { 0 }; const struct usbpd_ctrl_t usbpd_ctrl_regs[] = { - {&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0}, - {&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1}, - {&IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2}, + { &IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0 }, + { &IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1 }, + { &IT83XX_GPIO_GPCRP0, &IT83XX_GPIO_GPCRP1, IT83XX_IRQ_USBPD2 }, }; BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT); @@ -58,8 +58,8 @@ BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) >= IT83XX_USBPD_PHY_PORT_COUNT); void it83xx_Rd_5_1K_only_for_hibernate(int port) { uint8_t cc_config = (port == USBPD_PORT_C ? - IT83XX_USBPD_CC_PIN_CONFIG2 : - IT83XX_USBPD_CC_PIN_CONFIG); + IT83XX_USBPD_CC_PIN_CONFIG2 : + IT83XX_USBPD_CC_PIN_CONFIG); /* This only apply to active PD port */ if (*usbpd_ctrl_regs[port].cc1 == cc_config && @@ -130,7 +130,7 @@ static enum tcpc_cc_voltage_status it8xxx2_get_cc(enum usbpd_port port, cc_state = TYPEC_CC_VOLT_OPEN; break; } - /* Source */ + /* Source */ } else { if (cc_pin == USBPD_CC_PIN_1) dfp_volt = USBPD_GET_SRC_COMPARE_CC1_VOLT(port); @@ -214,12 +214,12 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port, * Bit[2:0] Tx message type * 000b=SOP, 001b=SOP', 010b=SOP", 011b=Debug SOP', 100b=Debug SOP''. */ - IT83XX_USBPD_MTSR0(port) = - (IT83XX_USBPD_MTSR0(port) & ~0x7) | (type & 0x7); + IT83XX_USBPD_MTSR0(port) = (IT83XX_USBPD_MTSR0(port) & ~0x7) | + (type & 0x7); /* According PD version set HW auto retry count */ IT83XX_USBPD_PDCSR0(port) = (IT83XX_USBPD_PDCSR0(port) & ~0xC0) | - (retry_count << 6); + (retry_count << 6); /* Limited by PD_HEADER_CNT() */ ASSERT(length <= 0x7); @@ -244,7 +244,7 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port, */ if (tx_error_status[port] || (evt & TASK_EVENT_TIMER)) { if (tx_error_status[port] & - USBPD_REG_MASK_TX_NOT_EN_STAT) { + USBPD_REG_MASK_TX_NOT_EN_STAT) { CPRINTS("p%d TxErr: Tx EN and resend", port); tx_error_status[port] &= ~USBPD_REG_MASK_TX_NOT_EN_STAT; @@ -252,13 +252,13 @@ static enum tcpc_transmit_complete it8xxx2_tx_data(enum usbpd_port port, USBPD_REG_MASK_TX_MESSAGE_ENABLE; continue; } else if (tx_error_status[port] & - USBPD_REG_MASK_TX_DISCARD_STAT) { + USBPD_REG_MASK_TX_DISCARD_STAT) { CPRINTS("p%d TxErr: Discard and resend", port); tx_error_status[port] &= ~USBPD_REG_MASK_TX_DISCARD_STAT; continue; } else if (tx_error_status[port] & - USBPD_REG_MASK_TX_NO_RESPONSE_STAT) { + USBPD_REG_MASK_TX_NO_RESPONSE_STAT) { /* HW had automatically resent message twice */ tx_error_status[port] &= ~USBPD_REG_MASK_TX_NO_RESPONSE_STAT; @@ -290,8 +290,8 @@ static enum tcpc_transmit_complete it8xxx2_send_hw_reset(enum usbpd_port port) return TCPC_TX_COMPLETE_SUCCESS; } -static enum tcpc_transmit_complete it8xxx2_send_cable_reset( - enum usbpd_port port) +static enum tcpc_transmit_complete +it8xxx2_send_cable_reset(enum usbpd_port port) { /* Send cable reset */ USBPD_SEND_CABLE_RESET(port); @@ -324,14 +324,16 @@ static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled) /* Disable unused CC to become VCONN */ if (cc_pin == USBPD_CC_PIN_1) { IT83XX_USBPD_CCCSR(port) = USBPD_CC2_DISCONNECTED(port); - IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port) - & ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) - | USBPD_REG_MASK_DISCONNECT_POWER_CC1; + IT83XX_USBPD_CCPSR(port) = + (IT83XX_USBPD_CCPSR(port) & + ~USBPD_REG_MASK_DISCONNECT_POWER_CC2) | + USBPD_REG_MASK_DISCONNECT_POWER_CC1; } else { IT83XX_USBPD_CCCSR(port) = USBPD_CC1_DISCONNECTED(port); - IT83XX_USBPD_CCPSR(port) = (IT83XX_USBPD_CCPSR(port) - & ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) - | USBPD_REG_MASK_DISCONNECT_POWER_CC2; + IT83XX_USBPD_CCPSR(port) = + (IT83XX_USBPD_CCPSR(port) & + ~USBPD_REG_MASK_DISCONNECT_POWER_CC1) | + USBPD_REG_MASK_DISCONNECT_POWER_CC2; } } else { /* Connect cc analog module (ex.UP/RD/DET/TX/RX) */ @@ -340,7 +342,7 @@ static void it8xxx2_enable_vconn(enum usbpd_port port, int enabled) /* Disable cc 5v tolerant */ IT83XX_USBPD_CCPSR(port) |= (USBPD_REG_MASK_DISCONNECT_POWER_CC1 | - USBPD_REG_MASK_DISCONNECT_POWER_CC2); + USBPD_REG_MASK_DISCONNECT_POWER_CC2); } } @@ -440,8 +442,7 @@ static int it8xxx2_tcpm_release(int port) return EC_ERROR_UNIMPLEMENTED; } -static int it8xxx2_tcpm_get_cc(int port, - enum tcpc_cc_voltage_status *cc1, +static int it8xxx2_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, enum tcpc_cc_voltage_status *cc2) { *cc2 = it8xxx2_get_cc(port, USBPD_CC_PIN_2); @@ -487,7 +488,8 @@ static int it8xxx2_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) { enum usbpd_cc_pin cc_pin = (polarity == POLARITY_CC1 || polarity == POLARITY_CC1_DTS) ? - USBPD_CC_PIN_1 : USBPD_CC_PIN_2; + USBPD_CC_PIN_1 : + USBPD_CC_PIN_2; it8xxx2_select_polarity(port, cc_pin); @@ -504,13 +506,11 @@ __maybe_unused static int it8xxx2_tcpm_decode_sop_prime_enable(int port, return EC_SUCCESS; if (enable) - IT83XX_USBPD_PDCSR1(port) |= - (USBPD_REG_MASK_SOPP_RX_ENABLE | - USBPD_REG_MASK_SOPPP_RX_ENABLE); + IT83XX_USBPD_PDCSR1(port) |= (USBPD_REG_MASK_SOPP_RX_ENABLE | + USBPD_REG_MASK_SOPPP_RX_ENABLE); else - IT83XX_USBPD_PDCSR1(port) &= - ~(USBPD_REG_MASK_SOPP_RX_ENABLE | - USBPD_REG_MASK_SOPPP_RX_ENABLE); + IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOPP_RX_ENABLE | + USBPD_REG_MASK_SOPPP_RX_ENABLE); return EC_SUCCESS; } @@ -535,7 +535,8 @@ static int it8xxx2_tcpm_set_vconn(int port, int enable) /* Turn on Vconn power switch. */ board_pd_vconn_ctrl(port, USBPD_GET_PULL_CC_SELECTION(port) ? - USBPD_CC_PIN_2 : USBPD_CC_PIN_1, + USBPD_CC_PIN_2 : + USBPD_CC_PIN_1, enable); } else { /* @@ -592,26 +593,25 @@ static int it8xxx2_tcpm_set_rx_enable(int port, int enable) if (enable) { IT83XX_USBPD_IMR(port) &= ~USBPD_REG_MASK_MSG_RX_DONE; IT83XX_USBPD_PDCSR1(port) |= - (USBPD_REG_MASK_SOP_RX_ENABLE | - USBPD_REG_MASK_HARD_RESET_RX_ENABLE); + (USBPD_REG_MASK_SOP_RX_ENABLE | + USBPD_REG_MASK_HARD_RESET_RX_ENABLE); if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP)) - it8xxx2_tcpm_decode_sop_prime_enable(port, - sop_prime_en[port]); + it8xxx2_tcpm_decode_sop_prime_enable( + port, sop_prime_en[port]); } else { IT83XX_USBPD_IMR(port) |= USBPD_REG_MASK_MSG_RX_DONE; - IT83XX_USBPD_PDCSR1(port) &= ~(USBPD_REG_MASK_SOP_RX_ENABLE | - USBPD_REG_MASK_SOPP_RX_ENABLE | - USBPD_REG_MASK_SOPPP_RX_ENABLE | - USBPD_REG_MASK_HARD_RESET_RX_ENABLE); + IT83XX_USBPD_PDCSR1(port) &= + ~(USBPD_REG_MASK_SOP_RX_ENABLE | + USBPD_REG_MASK_SOPP_RX_ENABLE | + USBPD_REG_MASK_SOPPP_RX_ENABLE | + USBPD_REG_MASK_HARD_RESET_RX_ENABLE); } return EC_SUCCESS; } -static int it8xxx2_tcpm_transmit(int port, - enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data) +static int it8xxx2_tcpm_transmit(int port, enum tcpci_msg_type type, + uint16_t header, const uint32_t *data) { int status = TCPC_TX_COMPLETE_FAILED; @@ -621,10 +621,7 @@ static int it8xxx2_tcpm_transmit(int port, case TCPCI_MSG_SOP_PRIME_PRIME: case TCPCI_MSG_SOP_DEBUG_PRIME: case TCPCI_MSG_SOP_DEBUG_PRIME_PRIME: - status = it8xxx2_tx_data(port, - type, - header, - data); + status = it8xxx2_tx_data(port, type, header, data); break; case TCPCI_MSG_TX_BIST_MODE_2: it8xxx2_send_bist_mode2_pattern(port); @@ -645,12 +642,13 @@ static int it8xxx2_tcpm_transmit(int port, return EC_SUCCESS; } -static int it8xxx2_tcpm_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) +static int +it8xxx2_tcpm_get_chip_info(int port, int live, + struct ec_response_pd_chip_info_v1 *chip_info) { chip_info->vendor_id = USB_VID_ITE; - chip_info->product_id = ((IT83XX_GCTRL_CHIPID1 << 8) | - IT83XX_GCTRL_CHIPID2); + chip_info->product_id = + ((IT83XX_GCTRL_CHIPID1 << 8) | IT83XX_GCTRL_CHIPID2); chip_info->device_id = IT83XX_GCTRL_CHIPVER & 0xf; chip_info->fw_version_number = 0xEC; @@ -687,11 +685,13 @@ static int it8xxx2_tcpm_set_frs_enable(int port, int enable) /* W/C status */ IT83XX_USBPD_IFS(port) = 0x33; /* Enable FRS detection (cc to GND) interrupt */ - IT83XX_USBPD_MIFS(port) &= ~(USBPD_REG_MASK_FAST_SWAP_ISR | - USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); + IT83XX_USBPD_MIFS(port) &= + ~(USBPD_REG_MASK_FAST_SWAP_ISR | + USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); /* Enable FRS detection (cc to GND) */ - IT83XX_USBPD_PDFSCR(port) = (IT83XX_USBPD_PDFSCR(port) & ~mask) - | USBPD_REG_FAST_SWAP_DETECT_ENABLE; + IT83XX_USBPD_PDFSCR(port) = + (IT83XX_USBPD_PDFSCR(port) & ~mask) | + USBPD_REG_FAST_SWAP_DETECT_ENABLE; /* * TODO(b/160210457): Enable HW auto trigger * GPH3(port0)/GPH4(port1) output H/L after we detect FRS cc @@ -699,8 +699,9 @@ static int it8xxx2_tcpm_set_frs_enable(int port, int enable) */ } else { /* Disable FRS detection (cc to GND) interrupt */ - IT83XX_USBPD_MIFS(port) |= (USBPD_REG_MASK_FAST_SWAP_ISR | - USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); + IT83XX_USBPD_MIFS(port) |= + (USBPD_REG_MASK_FAST_SWAP_ISR | + USBPD_REG_MASK_FAST_SWAP_DETECT_ISR); /* Disable FRS detection and requestion */ IT83XX_USBPD_PDFSCR(port) &= ~mask; /* @@ -724,16 +725,18 @@ static void it8xxx2_tcpm_switch_plug_out_type(int port) if ((cc1 == TYPEC_CC_VOLT_RD && cc2 == TYPEC_CC_VOLT_RD) || (cc1 == TYPEC_CC_VOLT_RA && cc2 == TYPEC_CC_VOLT_RA)) /* We're source, switch to detect audio/debug plug out. */ - IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) & - ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) | - USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT | - USBPD_REG_PLUG_OUT_SELECT; + IT83XX_USBPD_TCDCR(port) = + (IT83XX_USBPD_TCDCR(port) & + ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE) | + USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT | + USBPD_REG_PLUG_OUT_SELECT; else if (cc1 == TYPEC_CC_VOLT_RD || cc2 == TYPEC_CC_VOLT_RD) /* We're source, switch to detect sink plug out. */ - IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) & - ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE & - ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) | - USBPD_REG_PLUG_OUT_SELECT; + IT83XX_USBPD_TCDCR(port) = + (IT83XX_USBPD_TCDCR(port) & + ~USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE & + ~USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT) | + USBPD_REG_PLUG_OUT_SELECT; else if (cc1 >= TYPEC_CC_VOLT_RP_DEF || cc2 >= TYPEC_CC_VOLT_RP_DEF) /* * We're sink, disable detect interrupt, so messages on cc line @@ -756,8 +759,8 @@ void switch_plug_out_type(enum usbpd_port port) static void it8xxx2_init(enum usbpd_port port, int role) { uint8_t cc_config = (port == USBPD_PORT_C ? - IT83XX_USBPD_CC_PIN_CONFIG2 : - IT83XX_USBPD_CC_PIN_CONFIG); + IT83XX_USBPD_CC_PIN_CONFIG2 : + IT83XX_USBPD_CC_PIN_CONFIG); if (IS_ENABLED(CONFIG_IT83XX_TUNE_CC_PHY)) { /* Tune cc Tx pre-driving time */ @@ -817,7 +820,7 @@ static void it8xxx2_init(enum usbpd_port port, int role) IT83XX_USBPD_TCDCR(port) = (IT83XX_USBPD_TCDCR(port) & ~(USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE | USBPD_REG_PLUG_OUT_SELECT)) | - USBPD_REG_PLUG_IN_OUT_DETECT_STAT; + USBPD_REG_PLUG_IN_OUT_DETECT_STAT; #endif /* Set cc1/cc2 pins alternate mode */ *usbpd_ctrl_regs[port].cc1 = cc_config; @@ -825,7 +828,8 @@ static void it8xxx2_init(enum usbpd_port port, int role) task_clear_pending_irq(usbpd_ctrl_regs[port].irq); #ifdef CONFIG_ZEPHYR irq_connect_dynamic(usbpd_ctrl_regs[port].irq, 0, - (void (*)(const void *))chip_pd_irq, (void *)port, 0); + (void (*)(const void *))chip_pd_irq, (void *)port, + 0); #endif task_enable_irq(usbpd_ctrl_regs[port].irq); USBPD_START(port); @@ -951,8 +955,9 @@ static void it8xxx2_tcpm_hook_disconnect(void) * Switch to detect plug in and enable detect plug in interrupt, * since pd task has detected a type-c physical disconnected. */ - IT83XX_USBPD_TCDCR(port) &= ~(USBPD_REG_PLUG_OUT_SELECT | - USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE); + IT83XX_USBPD_TCDCR(port) &= + ~(USBPD_REG_PLUG_OUT_SELECT | + USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE); /* Exit BIST test data mode */ USBPD_SW_RESET(port); @@ -976,28 +981,28 @@ DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, it8xxx2_tcpm_hook_disconnect, HOOK_PRIO_DEFAULT); const struct tcpm_drv it8xxx2_tcpm_drv = { - .init = &it8xxx2_tcpm_init, - .release = &it8xxx2_tcpm_release, - .get_cc = &it8xxx2_tcpm_get_cc, - .select_rp_value = &it8xxx2_tcpm_select_rp_value, - .set_cc = &it8xxx2_tcpm_set_cc, - .set_polarity = &it8xxx2_tcpm_set_polarity, + .init = &it8xxx2_tcpm_init, + .release = &it8xxx2_tcpm_release, + .get_cc = &it8xxx2_tcpm_get_cc, + .select_rp_value = &it8xxx2_tcpm_select_rp_value, + .set_cc = &it8xxx2_tcpm_set_cc, + .set_polarity = &it8xxx2_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &it8xxx2_tcpm_decode_sop_prime_enable, + .sop_prime_enable = &it8xxx2_tcpm_decode_sop_prime_enable, #endif - .set_vconn = &it8xxx2_tcpm_set_vconn, - .set_msg_header = &it8xxx2_tcpm_set_msg_header, - .set_rx_enable = &it8xxx2_tcpm_set_rx_enable, - .get_message_raw = &it8xxx2_tcpm_get_message_raw, - .transmit = &it8xxx2_tcpm_transmit, + .set_vconn = &it8xxx2_tcpm_set_vconn, + .set_msg_header = &it8xxx2_tcpm_set_msg_header, + .set_rx_enable = &it8xxx2_tcpm_set_rx_enable, + .get_message_raw = &it8xxx2_tcpm_get_message_raw, + .transmit = &it8xxx2_tcpm_transmit, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = NULL, + .drp_toggle = NULL, #endif - .get_chip_info = &it8xxx2_tcpm_get_chip_info, + .get_chip_info = &it8xxx2_tcpm_get_chip_info, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &it8xxx2_tcpm_enter_low_power_mode, + .enter_low_power_mode = &it8xxx2_tcpm_enter_low_power_mode, #endif #ifdef CONFIG_USB_PD_FRS_TCPC - .set_frs_enable = &it8xxx2_tcpm_set_frs_enable, + .set_frs_enable = &it8xxx2_tcpm_set_frs_enable, #endif }; -- cgit v1.2.1 From cf7fb12c5bbfa63e5428250116b95d476a7bd61f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:10 -0600 Subject: board/kinox/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie6197397bace8177b40a7ef8d474f5f32927331a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728537 Reviewed-by: Jeremy Bettis --- board/kinox/usbc_config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/kinox/usbc_config.h b/board/kinox/usbc_config.h index b294eb69c8..439d36e19a 100644 --- a/board/kinox/usbc_config.h +++ b/board/kinox/usbc_config.h @@ -8,11 +8,8 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 +#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT }; #endif /* __CROS_EC_USBC_CONFIG_H */ -- cgit v1.2.1 From 0bea4d2b1077135f26eecc2807f5bdcf3bac4f7f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:16 -0600 Subject: board/taniks/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2c6442c996c777c1f9bef7767dafb9a03830db2d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729029 Reviewed-by: Jeremy Bettis --- board/taniks/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/taniks/usbc_config.h b/board/taniks/usbc_config.h index 8bcf365e8d..09fd179aa1 100644 --- a/board/taniks/usbc_config.h +++ b/board/taniks/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From b4a490046e08853374b79413aab499292967b324 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:51 -0600 Subject: common/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia8647587dd08049325ceaad65365c795a678d918 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729754 Reviewed-by: Jeremy Bettis --- common/thermal.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/common/thermal.c b/common/thermal.c index 50bf3e27f1..7230ae2e73 100644 --- a/common/thermal.c +++ b/common/thermal.c @@ -25,7 +25,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) /*****************************************************************************/ /* EC-specific thermal controls */ @@ -93,7 +93,6 @@ static void thermal_control(void) /* go through all the sensors */ for (i = 0; i < TEMP_SENSOR_COUNT; ++i) { - /* read one */ rv = temp_sensor_read(i, &t); @@ -249,22 +248,18 @@ static int command_thermalget(int argc, char **argv) ccprintf("sensor warn high halt fan_off fan_max name\n"); for (i = 0; i < TEMP_SENSOR_COUNT; i++) { ccprintf(" %2d %3d %3d %3d %3d %3d %s\n", - i, - thermal_params[i].temp_host[EC_TEMP_THRESH_WARN], + i, thermal_params[i].temp_host[EC_TEMP_THRESH_WARN], thermal_params[i].temp_host[EC_TEMP_THRESH_HIGH], thermal_params[i].temp_host[EC_TEMP_THRESH_HALT], thermal_params[i].temp_fan_off, - thermal_params[i].temp_fan_max, - temp_sensors[i].name); + thermal_params[i].temp_fan_max, temp_sensors[i].name); } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget, - NULL, +DECLARE_CONSOLE_COMMAND(thermalget, command_thermalget, NULL, "Print thermal parameters (degrees Kelvin)"); - static int command_thermalset(int argc, char **argv) { unsigned int n; @@ -329,8 +324,7 @@ thermal_command_set_threshold(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_THERMAL_SET_THRESHOLD, - thermal_command_set_threshold, - EC_VER_MASK(1)); + thermal_command_set_threshold, EC_VER_MASK(1)); static enum ec_status thermal_command_get_threshold(struct host_cmd_handler_args *args) @@ -346,5 +340,4 @@ thermal_command_get_threshold(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_THERMAL_GET_THRESHOLD, - thermal_command_get_threshold, - EC_VER_MASK(1)); + thermal_command_get_threshold, EC_VER_MASK(1)); -- cgit v1.2.1 From 7c223aa530a80f457248614358f3667bfaed2aee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:15 -0600 Subject: include/pwm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7f38d79940af0d9676f88ec813b9fb5bf82f868a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730393 Reviewed-by: Jeremy Bettis --- include/pwm.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/include/pwm.h b/include/pwm.h index 401d3dc0ec..cda2b19014 100644 --- a/include/pwm.h +++ b/include/pwm.h @@ -39,34 +39,33 @@ void pwm_set_duty(enum pwm_channel ch, int percent); */ int pwm_get_duty(enum pwm_channel ch); - /* Flags for PWM config table */ /** * PWM output signal is inverted, so 100% duty means always low */ -#define PWM_CONFIG_ACTIVE_LOW BIT(0) +#define PWM_CONFIG_ACTIVE_LOW BIT(0) /** * PWM channel has a fan controller with a tach input and can auto-adjust * its duty cycle to produce a given fan RPM. */ -#define PWM_CONFIG_HAS_RPM_MODE BIT(1) +#define PWM_CONFIG_HAS_RPM_MODE BIT(1) /** * PWM clock select alternate source. The actual clock and alternate * source are chip dependent. */ -#define PWM_CONFIG_ALT_CLOCK BIT(2) +#define PWM_CONFIG_ALT_CLOCK BIT(2) /** * PWM channel has a complementary output signal which should be enabled in * addition to the primary output. */ -#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3) +#define PWM_CONFIG_COMPLEMENTARY_OUTPUT BIT(3) /** * PWM channel must stay active in low-power idle, if enabled. */ -#define PWM_CONFIG_DSLEEP BIT(4) +#define PWM_CONFIG_DSLEEP BIT(4) /** * PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.) */ -#define PWM_CONFIG_OPEN_DRAIN BIT(5) -#endif /* __CROS_EC_PWM_H */ +#define PWM_CONFIG_OPEN_DRAIN BIT(5) +#endif /* __CROS_EC_PWM_H */ -- cgit v1.2.1 From 324712cbac410c55557d286f5b090914e875cf54 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:21 -0600 Subject: board/vilboz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5659dd02db160de2884f08724f415d284367c331 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729070 Reviewed-by: Jeremy Bettis --- board/vilboz/led.c | 57 +++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/board/vilboz/led.c b/board/vilboz/led.c index 4e9697ddbb..0d7b77da3e 100644 --- a/board/vilboz/led.c +++ b/board/vilboz/led.c @@ -8,44 +8,49 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES); -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 12fcf228c6c6010f235f6ac3fdf4307fdea93c80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:40 -0600 Subject: board/kuldax/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee258e22b31e59a3940cad2ce2606d5c3afb533b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728603 Reviewed-by: Jeremy Bettis --- board/kuldax/pwm.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/board/kuldax/pwm.c b/board/kuldax/pwm.c index 125d507a82..6d66ad7c31 100644 --- a/board/kuldax/pwm.c +++ b/board/kuldax/pwm.c @@ -11,21 +11,16 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_GREEN] = { - .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, - .freq = 1000 - }, - [PWM_CH_LED_RED] = { - .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, + [PWM_CH_LED_GREEN] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP, + .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, + .freq = 1000 }, + [PWM_CH_LED_RED] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From 2e9830f4266a3172600955a51715e4e8d19317cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:50 -0600 Subject: common/fmap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3fc18f6afe775cfc763262af56dc5fc0cf1807b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729648 Reviewed-by: Jeremy Bettis --- common/fmap.c | 110 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 58 insertions(+), 52 deletions(-) diff --git a/common/fmap.c b/common/fmap.c index 6bae9c7f85..56918c827a 100644 --- a/common/fmap.c +++ b/common/fmap.c @@ -13,7 +13,8 @@ /* * FMAP structs. - * See https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/HEAD/lib/fmap.h + * See + * https://chromium.googlesource.com/chromiumos/third_party/flashmap/+/HEAD/lib/fmap.h */ #define FMAP_NAMELEN 32 #define FMAP_SIGNATURE "__FMAP__" @@ -25,8 +26,8 @@ * For address containing CONFIG_PROGRAM_MEMORY_BASE (symbols in *.RO.lds.S and * variable), this computes the offset to the start of the image on flash. */ -#define RELATIVE_RO(addr) ((addr) - CONFIG_PROGRAM_MEMORY_BASE - \ - CONFIG_RO_MEM_OFF) +#define RELATIVE_RO(addr) \ + ((addr)-CONFIG_PROGRAM_MEMORY_BASE - CONFIG_RO_MEM_OFF) /* * All internal EC code assumes that offsets are provided relative to @@ -45,23 +46,23 @@ #endif struct fmap_header { - char fmap_signature[FMAP_SIGNATURE_SIZE]; - uint8_t fmap_ver_major; - uint8_t fmap_ver_minor; - uint64_t fmap_base; - uint32_t fmap_size; - char fmap_name[FMAP_NAMELEN]; - uint16_t fmap_nareas; + char fmap_signature[FMAP_SIGNATURE_SIZE]; + uint8_t fmap_ver_major; + uint8_t fmap_ver_minor; + uint64_t fmap_base; + uint32_t fmap_size; + char fmap_name[FMAP_NAMELEN]; + uint16_t fmap_nareas; } __packed; -#define FMAP_AREA_STATIC BIT(0) /* can be checksummed */ -#define FMAP_AREA_COMPRESSED BIT(1) /* may be compressed */ -#define FMAP_AREA_RO BIT(2) /* writes may fail */ +#define FMAP_AREA_STATIC BIT(0) /* can be checksummed */ +#define FMAP_AREA_COMPRESSED BIT(1) /* may be compressed */ +#define FMAP_AREA_RO BIT(2) /* writes may fail */ struct fmap_area_header { uint32_t area_offset; uint32_t area_size; - char area_name[FMAP_NAMELEN]; + char area_name[FMAP_NAMELEN]; uint16_t area_flags; } __packed; @@ -77,19 +78,18 @@ struct fmap_area_header { #define NUM_EC_FMAP_AREAS_ROLLBACK 0 #endif #ifdef CONFIG_RW_B -# ifdef CONFIG_RWSIG_TYPE_RWSIG -# define NUM_EC_FMAP_AREAS_RW_B 2 -# else -# define NUM_EC_FMAP_AREAS_RW_B 1 -# endif +#ifdef CONFIG_RWSIG_TYPE_RWSIG +#define NUM_EC_FMAP_AREAS_RW_B 2 +#else +#define NUM_EC_FMAP_AREAS_RW_B 1 +#endif #else -#define NUM_EC_FMAP_AREAS_RW_B 0 +#define NUM_EC_FMAP_AREAS_RW_B 0 #endif -#define NUM_EC_FMAP_AREAS (7 + \ - NUM_EC_FMAP_AREAS_RWSIG + \ - NUM_EC_FMAP_AREAS_ROLLBACK + \ - NUM_EC_FMAP_AREAS_RW_B) +#define NUM_EC_FMAP_AREAS \ + (7 + NUM_EC_FMAP_AREAS_RWSIG + NUM_EC_FMAP_AREAS_ROLLBACK + \ + NUM_EC_FMAP_AREAS_RW_B) const struct _ec_fmap { struct fmap_header header; @@ -97,7 +97,7 @@ const struct _ec_fmap { } ec_fmap __keep __attribute__((section(".google"))) = { /* Header */ { - .fmap_signature = {'_', '_', 'F', 'M', 'A', 'P', '_', '_'}, + .fmap_signature = { '_', '_', 'F', 'M', 'A', 'P', '_', '_' }, .fmap_ver_major = FMAP_VER_MAJOR, .fmap_ver_minor = FMAP_VER_MINOR, .fmap_base = CONFIG_PROGRAM_MEMORY_BASE, @@ -108,7 +108,7 @@ const struct _ec_fmap { }, { - /* RO Firmware */ + /* RO Firmware */ { /* * Range of RO firmware to be updated. EC_RO @@ -120,7 +120,7 @@ const struct _ec_fmap { */ .area_name = "EC_RO", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START, + FMAP_REGION_START, .area_size = CONFIG_RO_SIZE + CONFIG_RO_STORAGE_OFF, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -128,7 +128,8 @@ const struct _ec_fmap { /* (Optional) RO firmware code. */ .area_name = "FR_MAIN", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RO_STORAGE_OFF, + FMAP_REGION_START + + CONFIG_RO_STORAGE_OFF, .area_size = CONFIG_RO_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -138,10 +139,11 @@ const struct _ec_fmap { * ASCII, and padded with \0. */ .area_name = "RO_FRID", - .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - + .area_offset = + CONFIG_EC_PROTECTED_STORAGE_OFF - FMAP_REGION_START + CONFIG_RO_STORAGE_OFF + RELATIVE_RO((uint32_t)__image_data_offset) + - offsetof(struct image_data, version), + offsetof(struct image_data, version), .area_size = sizeof(current_image_data.version), .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -150,8 +152,9 @@ const struct _ec_fmap { { .area_name = "FMAP", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RO_STORAGE_OFF + - RELATIVE_RO((uint32_t)&ec_fmap), + FMAP_REGION_START + + CONFIG_RO_STORAGE_OFF + + RELATIVE_RO((uint32_t)&ec_fmap), .area_size = sizeof(ec_fmap), .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -162,8 +165,7 @@ const struct _ec_fmap { * EC_RO and aligned to hardware specification. */ .area_name = "WP_RO", - .area_offset = CONFIG_WP_STORAGE_OFF - - FMAP_REGION_START, + .area_offset = CONFIG_WP_STORAGE_OFF - FMAP_REGION_START, .area_size = CONFIG_WP_STORAGE_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -172,8 +174,9 @@ const struct _ec_fmap { /* RO public key address, for RW verification */ .area_name = "KEY_RO", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RO_PUBKEY_ADDR - - CONFIG_PROGRAM_MEMORY_BASE, + FMAP_REGION_START + + CONFIG_RO_PUBKEY_ADDR - + CONFIG_PROGRAM_MEMORY_BASE, .area_size = CONFIG_RO_PUBKEY_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -181,10 +184,11 @@ const struct _ec_fmap { /* RW Firmware */ { - /* The range of RW firmware to be auto-updated. */ + /* The range of RW firmware to be auto-updated. */ .area_name = "EC_RW", .area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RW_STORAGE_OFF, + FMAP_REGION_START + + CONFIG_RW_STORAGE_OFF, .area_size = CONFIG_RW_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -197,10 +201,11 @@ const struct _ec_fmap { * accommodate image asymmetry. */ .area_name = "RW_FWID", - .area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF - + .area_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF - FMAP_REGION_START + CONFIG_RW_STORAGE_OFF + RELATIVE_RO((uint32_t)__image_data_offset) + - offsetof(struct image_data, version), + offsetof(struct image_data, version), .area_size = sizeof(current_image_data.version), .area_flags = FMAP_AREA_STATIC, }, @@ -213,22 +218,22 @@ const struct _ec_fmap { * accommodate image asymmetry. */ .area_name = "RW_RBVER", - .area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF - + .area_offset = + CONFIG_EC_WRITABLE_STORAGE_OFF - FMAP_REGION_START + CONFIG_RW_STORAGE_OFF + RELATIVE_RO((uint32_t)__image_data_offset) + offsetof(struct image_data, rollback_version), - .area_size = sizeof( - current_image_data.rollback_version), + .area_size = sizeof(current_image_data.rollback_version), .area_flags = FMAP_AREA_STATIC, }, #endif #ifdef CONFIG_RWSIG_TYPE_RWSIG { - /* RW image signature */ + /* RW image signature */ .area_name = "SIG_RW", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RW_SIG_ADDR - - CONFIG_PROGRAM_MEMORY_BASE, + FMAP_REGION_START + CONFIG_RW_SIG_ADDR - + CONFIG_PROGRAM_MEMORY_BASE, .area_size = CONFIG_RW_SIG_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, @@ -236,21 +241,22 @@ const struct _ec_fmap { #ifdef CONFIG_RW_B /* RW Firmware */ { - /* The range of RW firmware to be auto-updated. */ + /* The range of RW firmware to be auto-updated. */ .area_name = "EC_RW_B", .area_offset = CONFIG_EC_WRITABLE_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RW_STORAGE_OFF + - CONFIG_RW_SIZE, + FMAP_REGION_START + + CONFIG_RW_STORAGE_OFF + CONFIG_RW_SIZE, .area_size = CONFIG_RW_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, #ifdef CONFIG_RWSIG_TYPE_RWSIG { - /* RW_B image signature */ + /* RW_B image signature */ .area_name = "SIG_RW_B", .area_offset = CONFIG_EC_PROTECTED_STORAGE_OFF - - FMAP_REGION_START + CONFIG_RW_B_SIG_ADDR - - CONFIG_PROGRAM_MEMORY_BASE, + FMAP_REGION_START + + CONFIG_RW_B_SIG_ADDR - + CONFIG_PROGRAM_MEMORY_BASE, .area_size = CONFIG_RW_SIG_SIZE, .area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO, }, -- cgit v1.2.1 From ee90cfcf4d644e72d96de77d4df7445da337b9c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:47 -0600 Subject: board/dewatt/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I152ef6898ce1ba8a4b816d13a92c9a27e1b82b23 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728223 Reviewed-by: Jeremy Bettis --- board/dewatt/board.c | 94 +++++++++++++++++++++++----------------------------- 1 file changed, 41 insertions(+), 53 deletions(-) diff --git a/board/dewatt/board.c b/board/dewatt/board.c index 8d37cd076d..bcb61ca0fc 100644 --- a/board/dewatt/board.c +++ b/board/dewatt/board.c @@ -47,17 +47,13 @@ static struct bmi_drv_data_t g_bmi_data; static struct accelgyro_saved_data_t g_bma422_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* * We have total 30 pins for keyboard connecter {-1, -1} mean @@ -65,16 +61,15 @@ const mat33_fp_t lid_standard_ref = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); struct motion_sensor_t motion_sensors[] = { [BASE_ACCEL] = { @@ -178,51 +173,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me) } __override int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - PS8818_RX_INPUT_TERM_112_OHM); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + PS8818_RX_INPUT_TERM_112_OHM); if (rv) return rv; } @@ -230,11 +220,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -302,8 +291,7 @@ static void board_chipset_startup(void) if (get_board_version() > 1) pct2075_init(); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); int board_get_soc_temp_k(int idx, int *temp_k) { @@ -437,8 +425,8 @@ static const struct ec_response_keybd_config main_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &main_kb; } -- cgit v1.2.1 From d93fb09076afb00103b59dec87c9f0036fd75f07 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:52 -0600 Subject: zephyr/projects/trogdor/lazor/src/sku.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1fe47293f6f9a027993185401f6c3d80486e0548 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730808 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/sku.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/trogdor/lazor/src/sku.c b/zephyr/projects/trogdor/lazor/src/sku.c index dde0549805..cfc55fcdf3 100644 --- a/zephyr/projects/trogdor/lazor/src/sku.c +++ b/zephyr/projects/trogdor/lazor/src/sku.c @@ -13,8 +13,8 @@ #include "system.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint8_t sku_id; -- cgit v1.2.1 From 7155926298b2f18699d3bf082a3d543ecab1506f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:04 -0600 Subject: chip/stm32/usb_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1c42518bda4e4617c9f82390869f09eda7c05ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729567 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_console.c | 67 ++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/chip/stm32/usb_console.c b/chip/stm32/usb_console.c index b5666c8fbf..12b9c9a79d 100644 --- a/chip/stm32/usb_console.c +++ b/chip/stm32/usb_console.c @@ -18,11 +18,11 @@ #include "usb_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) -static struct queue const tx_q = QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, - uint8_t); +static struct queue const tx_q = + QUEUE_NULL(CONFIG_USB_CONSOLE_TX_BUF_SIZE, uint8_t); static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t); static int last_tx_ok = 1; @@ -33,31 +33,31 @@ static int is_readonly; /* USB-Serial descriptors */ const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_CONSOLE, - .bAlternateSetting = 0, - .bNumEndpoints = 2, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_CONSOLE, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL, .bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL, - .iInterface = USB_STR_CONSOLE_NAME, + .iInterface = USB_STR_CONSOLE_NAME, }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0x80 | USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk IN */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 10 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x80 | USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk IN */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 10 }; const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_EP_CONSOLE, - .bmAttributes = 0x02 /* Bulk OUT */, - .wMaxPacketSize = USB_MAX_PACKET_SIZE, - .bInterval = 0 + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_EP_CONSOLE, + .bmAttributes = 0x02 /* Bulk OUT */, + .wMaxPacketSize = USB_MAX_PACKET_SIZE, + .bInterval = 0 }; static usb_uint ep_buf_tx[USB_MAX_PACKET_SIZE / 2] __usb_ram; @@ -81,9 +81,8 @@ static void con_ep_rx(void) for (i = 0; i < (btable_ep[USB_EP_CONSOLE].rx_count & RX_COUNT_MASK); i++) { - int val = ((i & 1) ? - (ep_buf_rx[i >> 1] >> 8) : - (ep_buf_rx[i >> 1] & 0xff)); + int val = ((i & 1) ? (ep_buf_rx[i >> 1] >> 8) : + (ep_buf_rx[i >> 1] & 0xff)); QUEUE_ADD_UNITS(&rx_q, &val, 1); } @@ -100,18 +99,18 @@ static void ep_event(enum usb_ep_event evt) if (evt != USB_EVENT_RESET) return; - btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); + btable_ep[USB_EP_CONSOLE].tx_addr = usb_sram_addr(ep_buf_tx); btable_ep[USB_EP_CONSOLE].tx_count = 0; - btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); + btable_ep[USB_EP_CONSOLE].rx_addr = usb_sram_addr(ep_buf_rx); btable_ep[USB_EP_CONSOLE].rx_count = 0x8000 | ((USB_MAX_PACKET_SIZE / 32 - 1) << 10); - STM32_USB_EP(USB_EP_CONSOLE) = (USB_EP_CONSOLE | /* Endpoint Addr */ - (2 << 4) | /* TX NAK */ - (0 << 9) | /* Bulk EP */ - (is_readonly ? EP_RX_NAK - : EP_RX_VALID)); + STM32_USB_EP(USB_EP_CONSOLE) = + (USB_EP_CONSOLE | /* Endpoint Addr */ + (2 << 4) | /* TX NAK */ + (0 << 9) | /* Bulk EP */ + (is_readonly ? EP_RX_NAK : EP_RX_VALID)); is_reset = 1; } @@ -201,9 +200,9 @@ static void tx_fifo_handler(void) break; if (!(count & 1)) - buf[count/2] = val; + buf[count / 2] = val; else - buf[count/2] |= val << 8; + buf[count / 2] |= val << 8; count++; } -- cgit v1.2.1 From 366c13efcedee5153d1d76eb013857604015537d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:59 -0600 Subject: board/fleex/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If287cb8694061627ff356892b1b6a3edf3a1dd0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728371 Reviewed-by: Jeremy Bettis --- board/fleex/board.c | 77 +++++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 40 deletions(-) diff --git a/board/fleex/board.c b/board/fleex/board.c index 4464d45730..605d6c6182 100644 --- a/board/fleex/board.c +++ b/board/fleex/board.c @@ -42,11 +42,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; static int is_support_syv_ppc; @@ -74,11 +74,9 @@ static void board_update_ppc_config_from_board(void) if (!is_support_syv_ppc) return; - memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], - &ppc_syv682x_port0, + memcpy(&ppc_chips[USB_PD_PORT_TCPC_0], &ppc_syv682x_port0, sizeof(struct ppc_config_t)); - memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], - &ppc_syv682x_port1, + memcpy(&ppc_chips[USB_PD_PORT_TCPC_1], &ppc_syv682x_port1, sizeof(struct ppc_config_t)); gpio_set_flags(GPIO_USB_PD_C0_INT_ODL, GPIO_INT_BOTH); @@ -112,28 +110,30 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C0] = {"VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = {"VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -143,17 +143,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; - const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} - }; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct stprivate_data g_lis2dh_data; @@ -242,8 +238,8 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); static int board_is_convertible(void) { - return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23 - || sku_id == 0xff; + return sku_id == 0x21 || sku_id == 0x22 || sku_id == 0x23 || + sku_id == 0xff; } static void board_update_sensor_config_from_sku(void) @@ -300,9 +296,10 @@ void board_overcurrent_event(int port, int is_overcurrented) static void charger_set_buck_boost_mode(void) { int reg; - /* Reduce Buck-boost mode switching frequency to improve power efficiency. */ + /* Reduce Buck-boost mode switching frequency to improve power + * efficiency. */ if (i2c_read16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS, - ISL9238_REG_CONTROL3, ®) == EC_SUCCESS) { + ISL9238_REG_CONTROL3, ®) == EC_SUCCESS) { reg |= ISL9238_C3_BB_SWITCHING_PERIOD; if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS, ISL9238_REG_CONTROL3, reg)) -- cgit v1.2.1 From b8706f4a24b515f872a5b15bf3c59714cc5a2ba2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:13 -0600 Subject: chip/stm32/usart-stm32l5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I91652186bd21e30111a8228365c94005cc064635 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729417 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32l5.c | 58 +++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 4753370560..3a8db09202 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -23,7 +23,7 @@ static struct usart_config const *configs[STM32_USARTS_MAX]; struct usart_configs usart_get_configs(void) { - return (struct usart_configs) {configs, ARRAY_SIZE(configs)}; + return (struct usart_configs){ configs, ARRAY_SIZE(configs) }; } static void usart_variant_enable(struct usart_config const *config) @@ -52,18 +52,18 @@ static void usart_variant_disable(struct usart_config const *config) } static struct usart_hw_ops const usart_variant_hw_ops = { - .enable = usart_variant_enable, + .enable = usart_variant_enable, .disable = usart_variant_disable, }; static void freq_change(void) { - size_t i; + size_t i; for (i = 0; i < ARRAY_SIZE(configs); ++i) if (configs[i]) usart_set_baud_f0_l(configs[i], configs[i]->baud, - clock_get_freq()); + clock_get_freq()); } DECLARE_HOOK(HOOK_FREQ_CHANGE, freq_change, HOOK_PRIO_DEFAULT); @@ -79,12 +79,12 @@ void usart_clear_tc(struct usart_config const *config) */ #if defined(CONFIG_STREAM_USART1) struct usart_hw_config const usart1_hw = { - .index = 0, - .base = STM32_USART1_BASE, - .irq = STM32_IRQ_USART1, + .index = 0, + .base = STM32_USART1_BASE, + .irq = STM32_IRQ_USART1, .clock_register = &STM32_RCC_APB2ENR, - .clock_enable = STM32_RCC_PB2_USART1, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB2_USART1, + .ops = &usart_variant_hw_ops, }; static void usart1_interrupt(void) @@ -97,12 +97,12 @@ DECLARE_IRQ(STM32_IRQ_USART1, usart1_interrupt, 2); #if defined(CONFIG_STREAM_USART2) struct usart_hw_config const usart2_hw = { - .index = 1, - .base = STM32_USART2_BASE, - .irq = STM32_IRQ_USART2, + .index = 1, + .base = STM32_USART2_BASE, + .irq = STM32_IRQ_USART2, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART2, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART2, + .ops = &usart_variant_hw_ops, }; static void usart2_interrupt(void) @@ -115,12 +115,12 @@ DECLARE_IRQ(STM32_IRQ_USART2, usart2_interrupt, 2); #if defined(CONFIG_STREAM_USART3) struct usart_hw_config const usart3_hw = { - .index = 2, - .base = STM32_USART3_BASE, - .irq = STM32_IRQ_USART3, + .index = 2, + .base = STM32_USART3_BASE, + .irq = STM32_IRQ_USART3, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART3, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART3, + .ops = &usart_variant_hw_ops, }; static void usart3_interrupt(void) @@ -133,12 +133,12 @@ DECLARE_IRQ(STM32_IRQ_USART3, usart3_interrupt, 2); #if defined(CONFIG_STREAM_USART4) struct usart_hw_config const usart4_hw = { - .index = 3, - .base = STM32_USART4_BASE, - .irq = STM32_IRQ_USART4, + .index = 3, + .base = STM32_USART4_BASE, + .irq = STM32_IRQ_USART4, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART4, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART4, + .ops = &usart_variant_hw_ops, }; static void usart4_interrupt(void) @@ -151,12 +151,12 @@ DECLARE_IRQ(STM32_IRQ_USART4, usart4_interrupt, 2); #if defined(CONFIG_STREAM_USART5) struct usart_hw_config const usart5_hw = { - .index = 4, - .base = STM32_USART5_BASE, - .irq = STM32_IRQ_USART5, + .index = 4, + .base = STM32_USART5_BASE, + .irq = STM32_IRQ_USART5, .clock_register = &STM32_RCC_APB1ENR, - .clock_enable = STM32_RCC_PB1_USART5, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_PB1_USART5, + .ops = &usart_variant_hw_ops, }; static void usart5_interrupt(void) -- cgit v1.2.1 From f6b0ec15acd0603e7a19b383a34aa4ac705de623 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:53 -0600 Subject: chip/stm32/usart_tx_interrupt.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e0098aaef6590d663a2d8a8e5d2b9ec3c2e7a86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729547 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_tx_interrupt.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/chip/stm32/usart_tx_interrupt.c b/chip/stm32/usart_tx_interrupt.c index d8d441ba1b..32bf69b0c5 100644 --- a/chip/stm32/usart_tx_interrupt.c +++ b/chip/stm32/usart_tx_interrupt.c @@ -37,12 +37,11 @@ static void usart_written(struct consumer const *consumer, size_t count) STM32_USART_CR1(config->hw->base) |= STM32_USART_CR1_TXEIE; } -static void usart_tx_interrupt_handler_common( - struct usart_config const *config, - remove_data_t remove_data) +static void usart_tx_interrupt_handler_common(struct usart_config const *config, + remove_data_t remove_data) { intptr_t base = config->hw->base; - uint8_t byte; + uint8_t byte; if (!(STM32_USART_SR(base) & STM32_USART_SR_TXE)) return; @@ -73,7 +72,7 @@ static void usart_tx_interrupt_handler_common( static size_t queue_remove(struct usart_config const *config, uint8_t *dest) { - return queue_remove_unit(config->consumer.queue, (void *) dest); + return queue_remove_unit(config->consumer.queue, (void *)dest); } static void usart_tx_interrupt_handler(struct usart_config const *config) @@ -107,11 +106,11 @@ struct usart_tx const usart_tx_interrupt = { #if defined(CONFIG_USART_HOST_COMMAND) -static void usart_host_command_tx_interrupt_handler( - struct usart_config const *config) +static void +usart_host_command_tx_interrupt_handler(struct usart_config const *config) { usart_tx_interrupt_handler_common(config, - &usart_host_command_tx_remove_data); + &usart_host_command_tx_remove_data); } struct usart_tx const usart_host_command_tx_interrupt = { -- cgit v1.2.1 From cdd4fa4d2c85f707b56a707b0a5b23169677141f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:28 -0600 Subject: zephyr/projects/corsola/src/kingler/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie1795ec282678c3ea428551227ad49c377e6edcf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730737 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/kingler/led.c | 33 ++++++++++++++++++------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/led.c b/zephyr/projects/corsola/src/kingler/led.c index 045ddb5be1..340028e92f 100644 --- a/zephyr/projects/corsola/src/kingler/led.c +++ b/zephyr/projects/corsola/src/kingler/led.c @@ -13,20 +13,25 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From 9b6dad5468da1b00f1a5e5ec2dcec71af61f07ca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:19 -0600 Subject: baseboard/intelrvp/npcx_ec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If7e356f5762152df5cb6928a4015fd09446a75af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727904 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/npcx_ec.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h index 52bcb2dae6..98f227e594 100644 --- a/baseboard/intelrvp/npcx_ec.h +++ b/baseboard/intelrvp/npcx_ec.h @@ -19,20 +19,20 @@ enum mft_channel { #endif /* __ASSEMBLER__ */ /* ADC channels */ -#define ADC_MAX_MVOLT ADC_MAX_VOLT -#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 -#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 -#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 -#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 +#define ADC_MAX_MVOLT ADC_MAX_VOLT +#define ADC_TEMP_SNS_AMBIENT_CHANNEL NPCX_ADC_CH3 +#define ADC_TEMP_SNS_DDR_CHANNEL NPCX_ADC_CH4 +#define ADC_TEMP_SNS_SKIN_CHANNEL NPCX_ADC_CH2 +#define ADC_TEMP_SNS_VR_CHANNEL NPCX_ADC_CH1 /* KSO2 is inverted */ -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV /* Fan */ #define CONFIG_PWM -#define PWN_FAN_CHANNEL 3 +#define PWN_FAN_CHANNEL 3 /* GPIO64/65 are used as UART pins. */ -#define NPCX_UART_MODULE2 1 +#define NPCX_UART_MODULE2 1 #endif /* __CROS_EC_NPCX_EC_H */ -- cgit v1.2.1 From 90f9401491c4a2ed27ed379c8440b8b2709fffb0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:45 -0600 Subject: baseboard/octopus/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I815803e194ea1bd9b875a3ecec56b432780fc4dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727936 Reviewed-by: Jeremy Bettis --- baseboard/octopus/baseboard.h | 220 +++++++++++++++++++++--------------------- 1 file changed, 110 insertions(+), 110 deletions(-) diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index da564f5056..d29ae38170 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -16,7 +16,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) /* * Variant EC defines. Pick one: @@ -24,59 +24,59 @@ * VARIANT_OCTOPUS_EC_ITE8320 */ #if defined(VARIANT_OCTOPUS_EC_NPCX796FB) - /* NPCX7 config */ - #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ - #define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ - #define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ - - /* Internal SPI flash on NPCX7 */ - /* Flash is 1MB but reserve half for future use. */ - #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) - - #define CONFIG_SPI_FLASH_REGS - #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ - - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 - #define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 - #define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 - #define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 - #define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 - #define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 - #define I2C_ADDR_EEPROM_FLAGS 0x50 - - /* Enable PSL hibernate mode. */ - #define CONFIG_HIBERNATE_PSL - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - - /* Allow the EC to enter deep sleep in S0 */ - #define CONFIG_LOW_POWER_S0 +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* [0:GPIO40/73, 1:GPIO93/A6] as TACH */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +/* Flash is 1MB but reserve half for future use. */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) + +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* I2C Bus Configuration */ +#define I2C_PORT_BATTERY NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT3_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT4_1 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 + +/* Enable PSL hibernate mode. */ +#define CONFIG_HIBERNATE_PSL + +/* EC variant determines USB-C variant */ +#define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS + +/* Allow the EC to enter deep sleep in S0 */ +#define CONFIG_LOW_POWER_S0 #elif defined(VARIANT_OCTOPUS_EC_ITE8320) - /* IT83XX config */ - #define CONFIG_IT83XX_VCC_1P8V - /* I2C Bus Configuration */ - #define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ - #define I2C_PORT_SENSOR IT83XX_I2C_CH_B - #define I2C_PORT_USBC0 IT83XX_I2C_CH_C - #define I2C_PORT_USBC1 IT83XX_I2C_CH_E - #define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ - #define I2C_PORT_EEPROM IT83XX_I2C_CH_F - #define I2C_ADDR_EEPROM_FLAGS 0x50 - #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 - - /* EC variant determines USB-C variant */ - #define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS - - /* - * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at - * 48MHz core cpu clock. - */ - #define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 +/* IT83XX config */ +#define CONFIG_IT83XX_VCC_1P8V +/* I2C Bus Configuration */ +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A /* Shared bus */ +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A /* Shared bus */ +#define I2C_PORT_SENSOR IT83XX_I2C_CH_B +#define I2C_PORT_USBC0 IT83XX_I2C_CH_C +#define I2C_PORT_USBC1 IT83XX_I2C_CH_E +#define I2C_PORT_USB_MUX I2C_PORT_USBC0 /* For MUX driver */ +#define I2C_PORT_EEPROM IT83XX_I2C_CH_F +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 + +/* EC variant determines USB-C variant */ +#define VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS + +/* + * Limit maximal ODR to 125Hz, the EC is using ~5ms per sample at + * 48MHz core cpu clock. + */ +#define CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ 125000 #else - #error Must define a VARIANT_OCTOPUS_EC +#error Must define a VARIANT_OCTOPUS_EC #endif /* VARIANT_OCTOPUS_EC */ /* Common EC defines */ @@ -115,33 +115,33 @@ * VARIANT_OCTOPUS_CHARGER_BQ25703 */ #if defined(VARIANT_OCTOPUS_CHARGER_ISL9238) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 - /* - * ISL923x driver sets "Adapter insertion to Switching Debounce" - * CONTROL2 REG 0x3DH to 1 which is 150 ms - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +/* + * ISL923x driver sets "Adapter insertion to Switching Debounce" + * CONTROL2 REG 0x3DH to 1 which is 150 ms + */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #elif defined(VARIANT_OCTOPUS_CHARGER_BQ25703) - #define CONFIG_CHARGER_BQ25703 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 - /* - * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. - */ - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 50 +#define CONFIG_CHARGER_BQ25703 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +/* + * From BQ25703: CHRG_OK is HIGH after 50ms deglitch time. + */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 50 #elif defined(CONFIG_CHARGER_RUNTIME_CONFIG) - #define CONFIG_CHARGER_ISL9238 - #define CONFIG_CHARGER_BQ25710 - #define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 - #define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 - #define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 - - #undef CONFIG_EXTPOWER_DEBOUNCE_MS - #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_BQ25710 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC_ISL9238 20 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 + +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #else - #error Must define a VARIANT_OCTOPUS_CHARGER +#error Must define a VARIANT_OCTOPUS_CHARGER #endif /* VARIANT_OCTOPUS_CHARGER */ /* Common charger defines */ @@ -155,7 +155,7 @@ /* Common battery defines */ #define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L #define CONFIG_BATTERY_REVIVE_DISCONNECT @@ -166,38 +166,38 @@ * Automatically defined by VARIANT_OCTOPUS_EC_ variant. */ - /* - * Variant USBC defines. Pick one: - * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS - * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) - */ +/* + * Variant USBC defines. Pick one: + * VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS + * VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS (requires) + */ #if defined(VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS) - #define CONFIG_USB_PD_TCPC_LOW_POWER - #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #if !defined(VARIANT_OCTOPUS_TCPC_0_PS8751) - #define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ +#define CONFIG_USB_PD_TCPM_ANX7447 /* C0 TCPC: ANX7447QN */ #endif - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ - #define CONFIG_USB_PD_VBUS_DETECT_TCPC - #define CONFIG_USBC_PPC_NX20P3483 +#define CONFIG_USB_PD_TCPM_PS8751 /* C1 TCPC: PS8751 */ +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USBC_PPC_NX20P3483 #elif defined(VARIANT_OCTOPUS_USBC_ITE_EC_TCPCS) - #undef CONFIG_USB_PD_TCPC_LOW_POWER - #undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - #define CONFIG_USB_PD_VBUS_DETECT_PPC - #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ - #define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ - #define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ - #define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER - #define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ - #define CONFIG_USBC_PPC_VCONN - #define CONFIG_USBC_PPC_DEDICATED_INT +#undef CONFIG_USB_PD_TCPC_LOW_POWER +#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0 & C1 TCPC: ITE EC */ +#define CONFIG_USB_MUX_IT5205 /* C0 MUX: IT5205 */ +#define CONFIG_USB_PD_TCPM_PS8751 /* C1 Mux: PS8751 */ +#define CONFIG_USB_PD_TCPM_PS8751_CUSTOM_MUX_DRIVER +#define CONFIG_USBC_PPC_SN5S330 /* C0 & C1 PPC: each SN5S330 */ +#define CONFIG_USBC_PPC_VCONN +#define CONFIG_USBC_PPC_DEDICATED_INT #else - #error Must define a VARIANT_OCTOPUS_USBC +#error Must define a VARIANT_OCTOPUS_USBC #endif /* VARIANT_OCTOPUS_USBC */ /* Common USB-C defines */ -#define USB_PD_PORT_TCPC_0 0 -#define USB_PD_PORT_TCPC_1 1 +#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_1 1 #define CONFIG_USB_PID 0x5046 #define CONFIG_USB_DRP_ACC_TRYSRC @@ -226,14 +226,14 @@ #define CONFIG_CMD_PPC_DUMP /* TODO(b/76218141): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* TODO(b/76218141): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /******************************************************************************* * USB-A Configs @@ -252,7 +252,7 @@ * SoC / PCH Config */ - /* Common SoC / PCH defines */ +/* Common SoC / PCH defines */ #define CONFIG_CHIPSET_GEMINILAKE #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI @@ -275,7 +275,7 @@ #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2 -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI /******************************************************************************* * Sensor Config @@ -287,7 +287,7 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) #ifndef VARIANT_OCTOPUS_NO_SENSORS -- cgit v1.2.1 From e8055665e111b0789a51be18875bc1a341ba5370 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:57 -0600 Subject: chip/mchp/pwm_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7942777e176aafc70f1e700c3954d068ddaf7699 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729308 Reviewed-by: Jeremy Bettis --- chip/mchp/pwm_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/mchp/pwm_chip.h b/chip/mchp/pwm_chip.h index f828a234a7..e17e8e52e9 100644 --- a/chip/mchp/pwm_chip.h +++ b/chip/mchp/pwm_chip.h @@ -48,4 +48,4 @@ extern const struct pwm_t pwm_channels[]; void pwm_keep_awake(void); -#endif /* __CROS_EC_PWM_CHIP_H */ +#endif /* __CROS_EC_PWM_CHIP_H */ -- cgit v1.2.1 From 7fd42ca773cfccd4f7931f13812b5603f7ee965f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:56 -0600 Subject: baseboard/intelrvp/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8cf524faa2d3581733511d18c0d12d353dacfbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727894 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/baseboard.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/baseboard/intelrvp/baseboard.c b/baseboard/intelrvp/baseboard.c index 87b43f2297..a39903f084 100644 --- a/baseboard/intelrvp/baseboard.c +++ b/baseboard/intelrvp/baseboard.c @@ -86,14 +86,12 @@ const static struct ec_thermal_config thermal_a = { }; struct ec_thermal_config thermal_params[] = { - [TEMP_SNS_AMBIENT] = thermal_a, - [TEMP_SNS_BATTERY] = thermal_a, + [TEMP_SNS_AMBIENT] = thermal_a, [TEMP_SNS_BATTERY] = thermal_a, [TEMP_SNS_DDR] = thermal_a, #ifdef CONFIG_PECI [TEMP_SNS_PECI] = thermal_a, #endif - [TEMP_SNS_SKIN] = thermal_a, - [TEMP_SNS_VR] = thermal_a, + [TEMP_SNS_SKIN] = thermal_a, [TEMP_SNS_VR] = thermal_a, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); #endif /* CONFIG_TEMP_SENSOR */ @@ -144,12 +142,12 @@ int ioexpander_read_intelrvp_version(int *port0, int *port1) for (i = 0; i < RVP_VERSION_READ_RETRY_CNT; i++) { rv = pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_0, port0); + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_0, port0); if (!rv && !pca9555_read(I2C_PORT_PCA9555_BOARD_ID_GPIO, - I2C_ADDR_PCA9555_BOARD_ID_GPIO, - PCA9555_CMD_INPUT_PORT_1, port1)) + I2C_ADDR_PCA9555_BOARD_ID_GPIO, + PCA9555_CMD_INPUT_PORT_1, port1)) return 0; msleep(1); -- cgit v1.2.1 From aaaa3c770ea55617728f48bbe73245cae425327a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:59 -0600 Subject: board/crota/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If8b5a256a68915d26032841349572eebc7d45884 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728191 Reviewed-by: Jeremy Bettis --- board/crota/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/crota/charger.c b/board/crota/charger.c index e6a5c446d7..25423c0927 100644 --- a/board/crota/charger.c +++ b/board/crota/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From c0b1794196d606b846b60d6a7db48e97a644bb3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:34 -0600 Subject: core/host/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3a1f9146cfae34e64236839461b1586efab0595a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729841 Reviewed-by: Jeremy Bettis --- core/host/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/host/main.c b/core/host/main.c index ed7032eb63..8fdcde11c0 100644 --- a/core/host/main.c +++ b/core/host/main.c @@ -19,7 +19,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) const char *__prog_name; @@ -85,7 +85,7 @@ int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size) * We lose the program name as LLVM fuzzer takes over main function: * make up one. */ - static const char *name = STRINGIFY(PROJECT)".exe"; + static const char *name = STRINGIFY(PROJECT) ".exe"; if (!initialized) { __prog_name = name; -- cgit v1.2.1 From 6025be0a356f5a71c7e6062702e0a2f262d4f78e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:36 -0600 Subject: zephyr/shim/include/usbc/tcpc_ccgxxf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If62c5b123a65cf279ad20ccf03a2d8cffaab7eaa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730837 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_ccgxxf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h index 566fed03d6..0825007100 100644 --- a/zephyr/shim/include/usbc/tcpc_ccgxxf.h +++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h @@ -8,7 +8,7 @@ #define CCGXXF_TCPC_COMPAT cypress_ccgxxf -#define TCPC_CONFIG_CCGXXF(id) \ +#define TCPC_CONFIG_CCGXXF(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ -- cgit v1.2.1 From 63016e92f90c8335fa90b87e0bfa2b8d44b2662c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:48 -0600 Subject: core/cortex-m/mpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia2f95d269b42a5dac2639c3a25606808843a50f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729823 Reviewed-by: Jeremy Bettis --- core/cortex-m/mpu.c | 61 +++++++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 35 deletions(-) diff --git a/core/cortex-m/mpu.c b/core/cortex-m/mpu.c index 29da931a28..ec9ceca201 100644 --- a/core/cortex-m/mpu.c +++ b/core/cortex-m/mpu.c @@ -37,7 +37,6 @@ bool mpu_is_unified(void) return (mpu_get_type() & MPU_TYPE_UNIFIED_MASK) == 0; } - /** * Update a memory region. * @@ -74,7 +73,7 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit, asm volatile("isb; dsb;"); MPU_NUMBER = region; - MPU_SIZE &= ~1; /* Disable */ + MPU_SIZE &= ~1; /* Disable */ if (enable) { MPU_BASE = addr; /* @@ -85,8 +84,8 @@ int mpu_update_region(uint8_t region, uint32_t addr, uint8_t size_bit, * according to the doc, but they don't ..., do a single 32-bit * one. */ - REG32(&MPU_SIZE) = ((uint32_t)attr << 16) - | (srd << 8) | ((size_bit - 1) << 1) | 1; + REG32(&MPU_SIZE) = ((uint32_t)attr << 16) | (srd << 8) | + ((size_bit - 1) << 1) | 1; } asm volatile("isb; dsb;"); @@ -117,7 +116,7 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr, * regions must be naturally aligned to their size. */ uint8_t natural_alignment = MIN(addr == 0 ? 32 : alignment_log2(addr), - alignment_log2(size)); + alignment_log2(size)); uint8_t subregion_disable = 0; if (natural_alignment >= 5) { @@ -159,10 +158,9 @@ static int mpu_config_region_greedy(uint8_t region, uint32_t addr, *consumed = 1 << natural_alignment; } - return mpu_update_region(region, - addr & ~((1 << natural_alignment) - 1), - natural_alignment, - attr, enable, subregion_disable); + return mpu_update_region(region, addr & ~((1 << natural_alignment) - 1), + natural_alignment, attr, enable, + subregion_disable); } /** @@ -188,8 +186,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, if (size == 0) return EC_SUCCESS; - rv = mpu_config_region_greedy(region, addr, size, - attr, enable, &consumed); + rv = mpu_config_region_greedy(region, addr, size, attr, enable, + &consumed); if (rv != EC_SUCCESS) return rv; ASSERT(consumed <= size); @@ -198,8 +196,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, /* Regions other than DATA_RAM_TEXT may use two MPU regions */ if (size > 0 && region != REGION_DATA_RAM_TEXT) { - rv = mpu_config_region_greedy(region + 1, addr, size, - attr, enable, &consumed); + rv = mpu_config_region_greedy(region + 1, addr, size, attr, + enable, &consumed); if (rv != EC_SUCCESS) return rv; ASSERT(consumed <= size); @@ -223,8 +221,8 @@ int mpu_config_region(uint8_t region, uint32_t addr, uint32_t size, static int mpu_unlock_region(uint8_t region, uint32_t addr, uint32_t size, uint8_t texscb) { - return mpu_config_region(region, addr, size, - MPU_ATTR_RW_RW | texscb, 1); + return mpu_config_region(region, addr, size, MPU_ATTR_RW_RW | texscb, + 1); } void mpu_enable(void) @@ -247,13 +245,9 @@ int mpu_protect_data_ram(void) int ret; /* Prevent code execution from data RAM */ - ret = mpu_config_region(REGION_DATA_RAM, - CONFIG_RAM_BASE, - CONFIG_DATA_RAM_SIZE, - MPU_ATTR_XN | - MPU_ATTR_RW_RW | - MPU_ATTR_INTERNAL_SRAM, - 1); + ret = mpu_config_region( + REGION_DATA_RAM, CONFIG_RAM_BASE, CONFIG_DATA_RAM_SIZE, + MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_INTERNAL_SRAM, 1); if (ret != EC_SUCCESS) return ret; @@ -271,18 +265,16 @@ int mpu_protect_code_ram(void) return mpu_config_region(REGION_STORAGE, CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF, CONFIG_CODE_RAM_SIZE, - MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, - 1); + MPU_ATTR_RO_NO | MPU_ATTR_INTERNAL_SRAM, 1); } #else int mpu_lock_ro_flash(void) { /* Prevent execution from internal mapped RO flash */ - return mpu_config_region(REGION_STORAGE, - CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF, - CONFIG_RO_SIZE, - MPU_ATTR_XN | MPU_ATTR_RW_RW | - MPU_ATTR_FLASH_MEMORY, 1); + return mpu_config_region( + REGION_STORAGE, CONFIG_MAPPED_STORAGE_BASE + CONFIG_RO_MEM_OFF, + CONFIG_RO_SIZE, + MPU_ATTR_XN | MPU_ATTR_RW_RW | MPU_ATTR_FLASH_MEMORY, 1); } /* Represent RW with at most 2 MPU regions. */ @@ -298,8 +290,7 @@ struct mpu_rw_regions mpu_get_rw_regions(void) * the region because on the Cortex-M3, Cortex-M4 and Cortex-M7, the * address used for an MPU region must be aligned to the size. */ - aligned_size_bit = - __fls(regions.addr[0] & -regions.addr[0]); + aligned_size_bit = __fls(regions.addr[0] & -regions.addr[0]); regions.size[0] = MIN(BIT(aligned_size_bit), CONFIG_RW_SIZE); regions.addr[1] = regions.addr[0] + regions.size[0]; regions.size[1] = CONFIG_RW_SIZE - regions.size[0]; @@ -386,10 +377,10 @@ int mpu_lock_rollback(int lock) #ifdef CONFIG_CHIP_UNCACHED_REGION /* Store temporarily the regions ranges to use them for the MPU configuration */ -#define REGION(_name, _flag, _start, _size) \ - static const uint32_t CONCAT2(_region_start_, _name) \ +#define REGION(_name, _flag, _start, _size) \ + static const uint32_t CONCAT2(_region_start_, _name) \ __attribute__((unused, section(".unused"))) = _start; \ - static const uint32_t CONCAT2(_region_size_, _name) \ + static const uint32_t CONCAT2(_region_size_, _name) \ __attribute__((unused, section(".unused"))) = _size; #include "memory_regions.inc" #undef REGION @@ -424,7 +415,7 @@ int mpu_pre_init(void) * to the region size. */ rv = mpu_update_region(i, CORTEX_M_SRAM_BASE, MPU_SIZE_BITS_MIN, - 0, 0, 0); + 0, 0, 0); if (rv != EC_SUCCESS) return rv; } -- cgit v1.2.1 From 094a161870bd03c56f8c2f9d70cd6dd5713658b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:00 -0600 Subject: include/lightbar.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icd8875ffc68219e1474c3acecce525650cb06af2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730303 Reviewed-by: Jeremy Bettis --- include/lightbar.h | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/include/lightbar.h b/include/lightbar.h index 2c8c143922..84700eaf2a 100644 --- a/include/lightbar.h +++ b/include/lightbar.h @@ -13,26 +13,13 @@ /* Define the types of sequences */ #define LBMSG(state) LIGHTBAR_##state #include "lightbar_msg_list.h" -enum lightbar_sequence { - LIGHTBAR_MSG_LIST - LIGHTBAR_NUM_SEQUENCES -}; +enum lightbar_sequence { LIGHTBAR_MSG_LIST LIGHTBAR_NUM_SEQUENCES }; #undef LBMSG /* Bytecode field constants */ -enum lb_color { - LB_COL_RED, - LB_COL_GREEN, - LB_COL_BLUE, - LB_COL_ALL -}; +enum lb_color { LB_COL_RED, LB_COL_GREEN, LB_COL_BLUE, LB_COL_ALL }; -enum lb_control { - LB_CONT_COLOR0, - LB_CONT_COLOR1, - LB_CONT_PHASE, - LB_CONT_MAX -}; +enum lb_control { LB_CONT_COLOR0, LB_CONT_COLOR1, LB_CONT_PHASE, LB_CONT_MAX }; #ifdef CONFIG_ALS_LIGHTBAR_DIMMING /* @@ -67,4 +54,4 @@ extern void demo_battery_level(int inc); extern void demo_is_charging(int ischarge); extern void demo_brightness(int inc); extern void demo_tap(void); -#endif /* __CROS_EC_LIGHTBAR_H */ +#endif /* __CROS_EC_LIGHTBAR_H */ -- cgit v1.2.1 From 434afb9735448b237911c460c632d09f6c23e52f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:25 -0600 Subject: board/dirinboz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If8f5e8ecec6de50d88f8892a4b1d602487036ef3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728226 Reviewed-by: Jeremy Bettis --- board/dirinboz/board.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/board/dirinboz/board.c b/board/dirinboz/board.c index d49f82773b..be519fb8c6 100644 --- a/board/dirinboz/board.c +++ b/board/dirinboz/board.c @@ -35,8 +35,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* This I2C moved. Temporarily detect and support the V0 HW. */ int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1; @@ -167,8 +167,7 @@ void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -189,7 +188,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -291,7 +289,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -362,11 +359,9 @@ int board_pd_set_frs_enable(int port, int enable) /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -434,14 +429,13 @@ int usb_port_enable[USBA_PORT_COUNT] = { * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, - {1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1}, - {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, - {2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2}, - {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, { 1, 4 }, + { 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, + { 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, + { 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif #define CHARGING_CURRENT_500mA 500 @@ -501,13 +495,13 @@ int charger_profile_override(struct charge_state_data *curr) } enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { return EC_RES_INVALID_PARAM; } -- cgit v1.2.1 From 77346cc4c6b5f34eecae4b666602f07afedc66be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:40 -0600 Subject: driver/amd_stt.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e1eff155bcdfb85bfb462944d4c9246022dd6b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729906 Reviewed-by: Jeremy Bettis --- driver/amd_stt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/driver/amd_stt.c b/driver/amd_stt.c index 90fd82523b..a93992784c 100644 --- a/driver/amd_stt.c +++ b/driver/amd_stt.c @@ -18,9 +18,9 @@ static bool amd_stt_debug; /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) -static const char * const amd_stt_sensor_name[] = { +static const char *const amd_stt_sensor_name[] = { [AMD_STT_PCB_SENSOR_APU] = "APU", [AMD_STT_PCB_SENSOR_REMOTE] = "Ambient", [AMD_STT_PCB_SENSOR_GPU] = "GPU", @@ -108,7 +108,7 @@ static void amd_stt_handler(void) return; } } -DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR+1); +DECLARE_HOOK(HOOK_SECOND, amd_stt_handler, HOOK_PRIO_TEMP_SENSOR + 1); static int command_stt(int argc, char **argv) { -- cgit v1.2.1 From bedb7bdc89f088f0cb26a1fb4a7b283251950dec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:12 -0600 Subject: test/rollback.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ffcda91a8949282f33d071a102229719ab974ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730533 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/rollback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/rollback.c b/test/rollback.c index 2038333311..1300e8105b 100644 --- a/test/rollback.c +++ b/test/rollback.c @@ -47,7 +47,7 @@ test_static int read_rollback_region(const struct rollback_info *info, for (i = 0; i < info->region_size_bytes; i++) { if (crec_flash_read(offset + i, sizeof(data), &data) == - EC_SUCCESS) + EC_SUCCESS) bytes_read++; } -- cgit v1.2.1 From 62466d58f86d2e5a27f0a0ae9ca8e181e2184ced Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:39 -0600 Subject: common/event_log.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia8f2b3b8907a7857490a71ad199af1c5eca59b14 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729625 Reviewed-by: Jeremy Bettis --- common/event_log.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/common/event_log.c b/common/event_log.c index dc2c4ec2d7..cdf9f4dd90 100644 --- a/common/event_log.c +++ b/common/event_log.c @@ -13,8 +13,8 @@ /* Event log FIFO */ #define UNIT_SIZE sizeof(struct event_log_entry) -#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE/UNIT_SIZE) -#define UNIT_COUNT_MASK (UNIT_COUNT - 1) +#define UNIT_COUNT (CONFIG_EVENT_LOG_SIZE / UNIT_SIZE) +#define UNIT_COUNT_MASK (UNIT_COUNT - 1) static struct event_log_entry log_events[UNIT_COUNT]; BUILD_ASSERT(POWER_OF_TWO(UNIT_COUNT)); @@ -42,10 +42,10 @@ static size_t log_tail; static size_t log_tail_next; /* Size of one FIFO entry */ -#define ENTRY_SIZE(payload_sz) (1+DIV_ROUND_UP((payload_sz), UNIT_SIZE)) +#define ENTRY_SIZE(payload_sz) (1 + DIV_ROUND_UP((payload_sz), UNIT_SIZE)) -void log_add_event(uint8_t type, uint8_t size, uint16_t data, - void *payload, uint32_t timestamp) +void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload, + uint32_t timestamp) { struct event_log_entry *r; size_t payload_size = EVENT_LOG_SIZE(size); @@ -78,13 +78,13 @@ void log_add_event(uint8_t type, uint8_t size, uint16_t data, r->size = size; r->data = data; /* copy the payload into the FIFO */ - first = MIN(total_size - 1, (UNIT_COUNT - - (current_tail & UNIT_COUNT_MASK)) - 1); + first = MIN(total_size - 1, + (UNIT_COUNT - (current_tail & UNIT_COUNT_MASK)) - 1); if (first) memcpy(r->payload, payload, first * UNIT_SIZE); if (first < total_size - 1) memcpy(log_events, ((uint8_t *)payload) + first * UNIT_SIZE, - (total_size - first) * UNIT_SIZE); + (total_size - first) * UNIT_SIZE); /* mark the entry available in the queue if nobody is behind us */ if (current_tail == log_tail) log_tail = log_tail_next; @@ -112,7 +112,7 @@ retry: first = MIN(total_size, UNIT_COUNT - (current_head & UNIT_COUNT_MASK)); memcpy(r, entry, first * UNIT_SIZE); if (first < total_size) - memcpy(r + first, log_events, (total_size-first) * UNIT_SIZE); + memcpy(r + first, log_events, (total_size - first) * UNIT_SIZE); /* --- critical section : remove the entry from the queue --- */ lock_key = irq_lock(); @@ -137,7 +137,7 @@ retry: static int command_dlog(int argc, char **argv) { size_t log_cur; - const uint8_t * const log_events_end = + const uint8_t *const log_events_end = (uint8_t *)&log_events[UNIT_COUNT]; if (argc > 1) { @@ -164,7 +164,7 @@ static int command_dlog(int argc, char **argv) log_cur += ENTRY_SIZE(payload_bytes); ccprintf("%10d %4d 0x%04X %4d ", r->timestamp, r->type, - r->data, payload_bytes); + r->data, payload_bytes); /* display payload if exists */ payload = r->payload; @@ -179,8 +179,6 @@ static int command_dlog(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dlog, - command_dlog, - "[clear]", +DECLARE_CONSOLE_COMMAND(dlog, command_dlog, "[clear]", "Display/clear TPM event logs"); #endif -- cgit v1.2.1 From fb37354eb666d0939746e4a44607cc2bdb998bd6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:58 -0600 Subject: board/kinox/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf873a4c34ea16430b5eeb116b312fbb4298a10d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728555 Reviewed-by: Jeremy Bettis --- board/kinox/led.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/kinox/led.c b/board/kinox/led.c index 00381fa7f4..dbcbf32859 100644 --- a/board/kinox/led.c +++ b/board/kinox/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* * When pulsing is enabled, brightness is incremented by every @@ -242,8 +242,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|green|off|alert|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From 67be01bdc62de45dbbec549ae042ff8ae1c7edd6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:10 -0600 Subject: board/cherry_scp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39b5069308f65cf2d67b1ab34871ec1d186491ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728121 Reviewed-by: Jeremy Bettis --- board/cherry_scp/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cherry_scp/board.h b/board/cherry_scp/board.h index dcf7f09a6f..576b412c40 100644 --- a/board/cherry_scp/board.h +++ b/board/cherry_scp/board.h @@ -25,8 +25,8 @@ #define CONFIG_ROM_BASE 0x0 #define CONFIG_RAM_BASE 0x68000 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) -#define CONFIG_RAM_SIZE ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - \ - CONFIG_RAM_BASE) +#define CONFIG_RAM_SIZE \ + ((CONFIG_IPC_SHARED_OBJ_ADDR & (~(0x400 - 1))) - CONFIG_RAM_BASE) #define SCP_FW_END 0xc0000 -- cgit v1.2.1 From e6b60ded25135a8ad6162f55e235cd59b56e9a5f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:40 -0600 Subject: board/pazquel/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie37b549b54fd00c4d55b95b68164b4da3b8a4601 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728816 Reviewed-by: Jeremy Bettis --- board/pazquel/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/pazquel/usbc_config.c b/board/pazquel/usbc_config.c index aac136415d..73666d087c 100644 --- a/board/pazquel/usbc_config.c +++ b/board/pazquel/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 0f1a23461f4376faa797670ced4fe45f52fd5c86 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:53 -0600 Subject: driver/mag_bmm150.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0096b715b15812c23171c82e7c19b4a612eec33 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730006 Reviewed-by: Jeremy Bettis --- driver/mag_bmm150.c | 168 ++++++++++++++++++++++++---------------------------- 1 file changed, 76 insertions(+), 92 deletions(-) diff --git a/driver/mag_bmm150.c b/driver/mag_bmm150.c index ad1eba7ad0..47a89f3246 100644 --- a/driver/mag_bmm150.c +++ b/driver/mag_bmm150.c @@ -25,75 +25,74 @@ #error "Not implemented" #endif - #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) - +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) /**************************************************************************** -* Copyright (C) 2011 - 2014 Bosch Sensortec GmbH -* -****************************************************************************/ + * Copyright (C) 2011 - 2014 Bosch Sensortec GmbH + * + ****************************************************************************/ /*************************************************************************** -* License: -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of the copyright holder nor the names of the -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE -* -* The information provided is believed to be accurate and reliable. -* The copyright holder assumes no responsibility for the consequences of use -* of such information nor for any infringement of patents or -* other rights of third parties which may result from its use. -* No license is granted by implication or otherwise under any patent or -* patent rights of the copyright holder. -*/ - -#define BMI150_READ_16BIT_COM_REG(store_, addr_) do { \ - int val; \ - raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \ - store_ = val; \ - raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1, &val); \ - store_ |= (val << 8); \ -} while (0) + * License: + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of the copyright holder nor the names of the + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE + * + * The information provided is believed to be accurate and reliable. + * The copyright holder assumes no responsibility for the consequences of use + * of such information nor for any infringement of patents or + * other rights of third parties which may result from its use. + * No license is granted by implication or otherwise under any patent or + * patent rights of the copyright holder. + */ +#define BMI150_READ_16BIT_COM_REG(store_, addr_) \ + do { \ + int val; \ + raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_), &val); \ + store_ = val; \ + raw_mag_read8(s->port, s->i2c_spi_addr_flags, (addr_) + 1, \ + &val); \ + store_ |= (val << 8); \ + } while (0) int bmm150_init(struct motion_sensor_t *s) { int ret; int val; struct bmm150_comp_registers *regs = BMM150_COMP_REG(s); - struct mag_cal_t *moc = BMM150_CAL(s); + struct mag_cal_t *moc = BMM150_CAL(s); /* Set the compass from Suspend to Sleep */ - ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, - BMM150_PWR_CTRL, BMM150_PWR_ON); + ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_PWR_CTRL, + BMM150_PWR_ON); msleep(4); /* Now we can read the device id */ - ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_CHIP_ID, &val); + ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_CHIP_ID, + &val); if (ret) return EC_ERROR_UNKNOWN; @@ -101,27 +100,24 @@ int bmm150_init(struct motion_sensor_t *s) return EC_ERROR_ACCESS_DENIED; /* Read the private registers for compensation */ - ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_X1, &val); + ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X1, + &val); if (ret) return EC_ERROR_UNKNOWN; regs->dig1[X] = val; - raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_Y1, &val); + raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y1, &val); regs->dig1[Y] = val; - raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_X2, &val); + raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_X2, &val); regs->dig2[X] = val; - raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_Y2, &val); + raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_Y2, &val); regs->dig2[Y] = val; - raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_XY1, &val); + raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY1, + &val); regs->dig_xy1 = val; - raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REGA_DIG_XY2, &val); + raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REGA_DIG_XY2, + &val); regs->dig_xy2 = val; BMI150_READ_16BIT_COM_REG(regs->dig_z1, BMM150_REGA_DIG_Z1_LSB); @@ -130,21 +126,17 @@ int bmm150_init(struct motion_sensor_t *s) BMI150_READ_16BIT_COM_REG(regs->dig_z4, BMM150_REGA_DIG_Z4_LSB); BMI150_READ_16BIT_COM_REG(regs->dig_xyz1, BMM150_REGA_DIG_XYZ1_LSB); - /* Set the repetition in "Regular Preset" */ - raw_mag_write8(s->port, s->i2c_spi_addr_flags, - BMM150_REPXY, BMM150_REP(SPECIAL, XY)); - raw_mag_write8(s->port, s->i2c_spi_addr_flags, - BMM150_REPZ, BMM150_REP(SPECIAL, Z)); - ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REPXY, &val); - ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, - BMM150_REPZ, &val); + raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY, + BMM150_REP(SPECIAL, XY)); + raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ, + BMM150_REP(SPECIAL, Z)); + ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPXY, &val); + ret = raw_mag_read8(s->port, s->i2c_spi_addr_flags, BMM150_REPZ, &val); /* * Set the compass forced mode, to sleep after each measure. */ - ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, - BMM150_OP_CTRL, + ret = raw_mag_write8(s->port, s->i2c_spi_addr_flags, BMM150_OP_CTRL, BMM150_OP_MODE_FORCED << BMM150_OP_MODE_OFFSET); init_mag_cal(moc); @@ -152,10 +144,8 @@ int bmm150_init(struct motion_sensor_t *s) return ret; } -void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, - intv3_t raw, - intv3_t comp, - int r) +void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, intv3_t raw, + intv3_t comp, int r) { int inter, axis; struct bmm150_comp_registers *regs = BMM150_COMP_REG(s); @@ -191,10 +181,8 @@ void bmm150_temp_compensate_xy(const struct motion_sensor_t *s, } } -void bmm150_temp_compensate_z(const struct motion_sensor_t *s, - intv3_t raw, - intv3_t comp, - int r) +void bmm150_temp_compensate_z(const struct motion_sensor_t *s, intv3_t raw, + intv3_t comp, int r) { int dividend, divisor; struct bmm150_comp_registers *regs = BMM150_COMP_REG(s); @@ -221,9 +209,7 @@ void bmm150_temp_compensate_z(const struct motion_sensor_t *s, comp[Z] = BMM150_OVERFLOW_OUTPUT; } -void bmm150_normalize(const struct motion_sensor_t *s, - intv3_t v, - uint8_t *data) +void bmm150_normalize(const struct motion_sensor_t *s, intv3_t v, uint8_t *data) { uint16_t r; intv3_t raw; @@ -247,8 +233,7 @@ void bmm150_normalize(const struct motion_sensor_t *s, v[Z] += cal->bias[Z]; } -int bmm150_set_offset(const struct motion_sensor_t *s, - const intv3_t offset) +int bmm150_set_offset(const struct motion_sensor_t *s, const intv3_t offset) { struct mag_cal_t *cal = BMM150_CAL(s); cal->bias[X] = offset[X]; @@ -257,8 +242,7 @@ int bmm150_set_offset(const struct motion_sensor_t *s, return EC_SUCCESS; } -int bmm150_get_offset(const struct motion_sensor_t *s, - intv3_t offset) +int bmm150_get_offset(const struct motion_sensor_t *s, intv3_t offset) { struct mag_cal_t *cal = BMM150_CAL(s); offset[X] = cal->bias[X]; -- cgit v1.2.1 From 547b996eee96f4f19187793f696411d0ee26036f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:29 -0600 Subject: common/als.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98ab966b11b6fe45b27a96e3cd6936a77c317e1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729563 Reviewed-by: Jeremy Bettis --- common/als.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/common/als.c b/common/als.c index 2e9c7ba96c..b4d5ae1e5e 100644 --- a/common/als.c +++ b/common/als.c @@ -19,9 +19,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ALS, outstr) -#define CPRINTS(format, args...) cprints(CC_ALS, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_ALS, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_ALS, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_ALS, format, ##args) #define ALS_POLL_PERIOD SECOND @@ -90,8 +89,7 @@ static void als_task_init(void) * Enable ALS task in S0 only and may need to re-enable * when sysjumped. */ - if (system_jumped_late() && - chipset_in_state(CHIPSET_STATE_ON)) + if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) als_task_enable(); } @@ -121,7 +119,5 @@ static int command_als(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(als, command_als, - NULL, - "Print ALS values"); +DECLARE_CONSOLE_COMMAND(als, command_als, NULL, "Print ALS values"); #endif -- cgit v1.2.1 From 8e11028f46bcafdcfee0e1c29863b2cfb259282c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:07 -0600 Subject: baseboard/grunt/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie424c697776212a85b57b9127cc68c92cff08fd1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727517 Reviewed-by: Jeremy Bettis --- baseboard/grunt/usb_pd_policy.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/baseboard/grunt/usb_pd_policy.c b/baseboard/grunt/usb_pd_policy.c index 7c4fff953c..77966f346e 100644 --- a/baseboard/grunt/usb_pd_policy.c +++ b/baseboard/grunt/usb_pd_policy.c @@ -17,11 +17,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) int pd_check_vconn_swap(int port) { @@ -118,11 +118,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -142,8 +142,8 @@ __override void svdm_dp_post_config(int port) /* set the minimum time delay (2ms) for the next HPD IRQ */ svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, + USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED); } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ -- cgit v1.2.1 From 300fb09cb45d9f4aabaa9051e13610edfefacc62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:51 -0600 Subject: chip/stm32/config-stm32l100.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I957e80d3da7c4cc465beb24b37fd89437927e469 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729479 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l100.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h index 2132fab4dd..5ed085f225 100644 --- a/chip/stm32/config-stm32l100.h +++ b/chip/stm32/config-stm32l100.h @@ -5,8 +5,8 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ /* * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at @@ -21,8 +21,8 @@ /* Ideal write size in page-mode */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00002800 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00002800 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 @@ -37,10 +37,10 @@ #define CONFIG_STM32L_FAKE_HIBERNATE /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 -- cgit v1.2.1 From 16de98da2cc15bd80d5fd76aa26c388dc6a2f005 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:25 -0600 Subject: zephyr/drivers/cros_shi/cros_shi_it8xxx2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2ce1bd8bbcc620beec303cbeceb1a6cb0488acca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730679 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_shi/cros_shi_it8xxx2.c | 35 ++++++++++++++---------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c index 3d0db3bc89..ba7419640c 100644 --- a/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c +++ b/zephyr/drivers/cros_shi/cros_shi_it8xxx2.c @@ -21,12 +21,12 @@ #include "host_command.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) LOG_MODULE_REGISTER(cros_shi, LOG_LEVEL_ERR); -#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg * const)(dev)->config) +#define DRV_CONFIG(dev) ((struct cros_shi_it8xxx2_cfg *const)(dev)->config) /* * Strcture cros_shi_it8xxx2_cfg is about the setting of SHI, @@ -45,8 +45,8 @@ struct cros_shi_it8xxx2_cfg { /* Max data size for a version 3 request/response packet. */ #define SPI_MAX_REQUEST_SIZE SPI_RX_MAX_FIFO_SIZE -#define SPI_MAX_RESPONSE_SIZE (SPI_TX_MAX_FIFO_SIZE - \ - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH) +#define SPI_MAX_RESPONSE_SIZE \ + (SPI_TX_MAX_FIFO_SIZE - EC_SPI_PREAMBLE_LENGTH - EC_SPI_PAST_END_LENGTH) static const uint8_t out_preamble[EC_SPI_PREAMBLE_LENGTH] = { EC_SPI_PROCESSING, @@ -80,9 +80,9 @@ static enum shi_state_machine shi_state; static const int spi_response_state[] = { [SPI_STATE_READY_TO_RECV] = EC_SPI_RX_READY, - [SPI_STATE_RECEIVING] = EC_SPI_RECEIVING, - [SPI_STATE_PROCESSING] = EC_SPI_PROCESSING, - [SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA, + [SPI_STATE_RECEIVING] = EC_SPI_RECEIVING, + [SPI_STATE_PROCESSING] = EC_SPI_PROCESSING, + [SPI_STATE_RX_BAD] = EC_SPI_RX_BAD_DATA, }; BUILD_ASSERT(ARRAY_SIZE(spi_response_state) == SPI_STATE_COUNT); @@ -169,12 +169,12 @@ static void spi_send_response_packet(struct host_packet *pkt) /* Append our past-end byte, which we reserved space for. */ for (int i = 0; i < EC_SPI_PAST_END_LENGTH; i++) { - ((uint8_t *)pkt->response)[pkt->response_size + i] - = EC_SPI_PAST_END; + ((uint8_t *)pkt->response)[pkt->response_size + i] = + EC_SPI_PAST_END; } tx_size = pkt->response_size + EC_SPI_PREAMBLE_LENGTH + - EC_SPI_PAST_END_LENGTH; + EC_SPI_PAST_END_LENGTH; /* Transmit the reply */ spi_response_host_data(out_msg, tx_size); @@ -340,8 +340,8 @@ static int cros_shi_ite_init(const struct device *dev) * bit3 : Rx FIFO1 will not be overwrited once it's full. * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high. */ - IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC - | IT83XX_SPI_RXFAR; + IT83XX_SPI_GCR2 = IT83XX_SPI_RXF2OC | IT83XX_SPI_RXF1OC | + IT83XX_SPI_RXFAR; /* * Interrupt mask register (0b:Enable, 1b:Mask) * bit5 : Rx byte reach interrupt mask @@ -384,10 +384,8 @@ static const struct cros_shi_it8xxx2_cfg cros_shi_cfg = { CONFIG_PLATFORM_EC_GPIO_INIT_PRIORITY #error "CROS_SHI must initialize after the GPIOs initialization" #endif -DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL, - NULL, &cros_shi_cfg, POST_KERNEL, - CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY, - NULL); +DEVICE_DT_INST_DEFINE(0, cros_shi_ite_init, NULL, NULL, &cros_shi_cfg, + POST_KERNEL, CONFIG_CROS_SHI_IT8XXX2_INIT_PRIORITY, NULL); /* Get protocol information */ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) @@ -404,6 +402,5 @@ enum ec_status spi_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - spi_get_protocol_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, spi_get_protocol_info, EC_VER_MASK(0)); -- cgit v1.2.1 From 261690239a7ff910fbf3e186ec35af82d937e93b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:05 -0600 Subject: include/power_button.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I338d444d770880ed4d44f1a7b91450364b340f2c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730390 Reviewed-by: Jeremy Bettis --- include/power_button.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/power_button.h b/include/power_button.h index 167ca21e2b..a4264ab557 100644 --- a/include/power_button.h +++ b/include/power_button.h @@ -69,4 +69,4 @@ int64_t get_time_dsw_pwrok(void); */ void board_pwrbtn_to_pch(int level); -#endif /* __CROS_EC_POWER_BUTTON_H */ +#endif /* __CROS_EC_POWER_BUTTON_H */ -- cgit v1.2.1 From 3cac37c66f3a0494f206226f0f8b9667944d6789 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:35 -0600 Subject: baseboard/dedede/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide01dc860d08993f2a22145d29b4e46319df0ff7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727870 Reviewed-by: Jeremy Bettis --- baseboard/dedede/baseboard.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c index 60b3949e93..5e3d5baf8a 100644 --- a/baseboard/dedede/baseboard.c +++ b/baseboard/dedede/baseboard.c @@ -23,8 +23,8 @@ #include "usb_pd.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /******************************************************************************/ /* @@ -81,7 +81,6 @@ const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = { }; const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list); - /* * Dedede does not use hibernate wake pins, but the super low power "Z-state" * instead in which the EC is powered off entirely. Power will be restored to @@ -149,8 +148,8 @@ __override int intel_x86_get_pg_ec_dsw_pwrok(void) } /* Store away PP300_A good status before sysjumps */ -#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ -#define BASEBOARD_HOOK_VERSION 1 +#define BASEBOARD_SYSJUMP_TAG 0x4242 /* BB */ +#define BASEBOARD_HOOK_VERSION 1 static void pp3300_a_pgood_preserve(void) { @@ -167,13 +166,13 @@ static void baseboard_prepare_power_signals(void) stored = (const int *)system_get_jump_tag(BASEBOARD_SYSJUMP_TAG, &version, &size); if (stored && (version == BASEBOARD_HOOK_VERSION) && - (size == sizeof(pp3300_a_pgood))) + (size == sizeof(pp3300_a_pgood))) /* Valid PP3300 status found, restore before CHIPSET init */ pp3300_a_pgood = *stored; /* Restore pull-up on PG_PP1050_ST_OD */ if (system_jumped_to_this_image() && - gpio_get_level(GPIO_PG_EC_RSMRST_ODL)) + gpio_get_level(GPIO_PG_EC_RSMRST_ODL)) board_after_rsmrst(1); } DECLARE_HOOK(HOOK_INIT, baseboard_prepare_power_signals, HOOK_PRIO_FIRST); @@ -191,8 +190,8 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void) * PGOOD. */ return gpio_get_level(GPIO_PG_PP1050_ST_OD) && - gpio_get_level(GPIO_PG_DRAM_OD) && - gpio_get_level(GPIO_PG_VCCIO_EXT_OD); + gpio_get_level(GPIO_PG_DRAM_OD) && + gpio_get_level(GPIO_PG_VCCIO_EXT_OD); } __override int power_signal_get_level(enum gpio_signal signal) @@ -209,7 +208,6 @@ __override int power_signal_get_level(enum gpio_signal signal) return espi_vw_get_wire((enum espi_vw_signal)signal); } return gpio_get_level(signal); - } void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) @@ -220,8 +218,8 @@ void baseboard_all_sys_pgood_interrupt(enum gpio_signal signal) * driver to. * Early protos do not pull VCCST_PWRGD below Vil in hardware logic, * so we need to do the same for this signal. - * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW during - * SLP_S3_L assertion. + * Pull EN_VCCIO_EXT to LOW, which ensures VCCST_PWRGD remains LOW + * during SLP_S3_L assertion. */ if (!gpio_get_level(GPIO_SLP_S3_L)) { gpio_set_level(GPIO_ALL_SYS_PWRGD, 0); @@ -259,9 +257,9 @@ void board_hibernate_late(void) /* Disable any pull-ups on C0 and C1 interrupt lines */ gpio_set_flags(GPIO_USB_C0_INT_ODL, GPIO_INPUT); - #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 - gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); - #endif +#if CONFIG_USB_PD_PORT_MAX_COUNT > 1 + gpio_set_flags(GPIO_USB_C1_INT_ODL, GPIO_INPUT); +#endif /* * Turn on the Z state. This will not return as it will cut power to * the EC. -- cgit v1.2.1 From 4ed2881f1817354270bcdec32f130575372be5ee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:53 -0600 Subject: board/servo_v4p1/fusb302b.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e927f0e0705e8307297c87cef0a6def43c8aa59 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728931 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/fusb302b.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/servo_v4p1/fusb302b.c b/board/servo_v4p1/fusb302b.c index 4e144dec05..79a92b4930 100644 --- a/board/servo_v4p1/fusb302b.c +++ b/board/servo_v4p1/fusb302b.c @@ -72,7 +72,6 @@ int init_fusb302b(int p) if (ret) return ret; - ret = tcpc_read(TCPC_REG_INTERRUPTA, &interrupta); if (ret) return ret; @@ -159,7 +158,6 @@ int get_cc(int *cc1, int *cc2) else orig_meas_cc2 = 0; - /* Disable CC2 measurement switch, enable CC1 measurement switch */ reg &= ~TCPC_REG_SWITCHES0_MEAS_CC2; reg |= TCPC_REG_SWITCHES0_MEAS_CC1; -- cgit v1.2.1 From 5a497c26b6ab543d83cc350835a0e72a3af05afe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:22 -0600 Subject: chip/mchp/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia87775e167582b4ba57d3bed32f3a2fb7a175a8b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729302 Reviewed-by: Jeremy Bettis --- chip/mchp/system.c | 52 +++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/chip/mchp/system.c b/chip/mchp/system.c index 1a9b3f6bc7..4528eeea06 100644 --- a/chip/mchp/system.c +++ b/chip/mchp/system.c @@ -26,15 +26,15 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) /* Index values for hibernate data registers (RAM backed by VBAT) */ enum hibdata_index { - HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratch pad */ + HIBDATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratch pad */ HIBDATA_INDEX_SAVED_RESET_FLAGS, /* Saved reset flags */ - HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ - HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ - HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ + HIBDATA_INDEX_PD0, /* USB-PD0 saved port state */ + HIBDATA_INDEX_PD1, /* USB-PD1 saved port state */ + HIBDATA_INDEX_PD2, /* USB-PD2 saved port state */ }; /* @@ -47,7 +47,7 @@ enum hibdata_index { #ifdef CHIP_FAMILY_MEC172X static void vtr3_voltage_select(int use18v) { - (void) use18v; + (void)use18v; } #else static void vtr3_voltage_select(int use18v) @@ -59,7 +59,6 @@ static void vtr3_voltage_select(int use18v) } #endif - /* * The current logic will set EC_RESET_FLAG_RESET_PIN flag * even if the reset was caused by WDT. MEC170x/MEC152x HW RESET_SYS @@ -76,8 +75,7 @@ static void check_reset_cause(void) uint32_t status = MCHP_VBAT_STS; uint32_t flags = 0; uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & - (MCHP_PWR_RST_STS_SYS | - MCHP_PWR_RST_STS_VBAT); + (MCHP_PWR_RST_STS_SYS | MCHP_PWR_RST_STS_VBAT); /* Clear the reset causes now that we've read them */ MCHP_VBAT_STS |= status; @@ -92,13 +90,12 @@ static void check_reset_cause(void) if (rst_sts & MCHP_PWR_RST_STS_SYS) flags |= EC_RESET_FLAG_RESET_PIN; - flags |= chip_read_reset_flags(); chip_save_reset_flags(0); - if ((status & MCHP_VBAT_STS_WDT) && !(flags & (EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_HIBERNATE))) + if ((status & MCHP_VBAT_STS_WDT) && + !(flags & (EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD | + EC_RESET_FLAG_HIBERNATE))) flags |= EC_RESET_FLAG_WATCHDOG; system_set_reset_flags(flags); @@ -115,10 +112,10 @@ int system_is_reboot_warm(void) reset_flags = system_get_reset_flags(); if ((reset_flags & EC_RESET_FLAG_RESET_PIN) || - (reset_flags & EC_RESET_FLAG_POWER_ON) || - (reset_flags & EC_RESET_FLAG_WATCHDOG) || - (reset_flags & EC_RESET_FLAG_HARD) || - (reset_flags & EC_RESET_FLAG_SOFT)) + (reset_flags & EC_RESET_FLAG_POWER_ON) || + (reset_flags & EC_RESET_FLAG_WATCHDOG) || + (reset_flags & EC_RESET_FLAG_HARD) || + (reset_flags & EC_RESET_FLAG_SOFT)) return 0; else return 1; @@ -174,7 +171,7 @@ void system_pre_init(void) * Signals bus fault to Cortex-M4 core if an address presented * to AHB is not claimed by any HW block. */ - MCHP_EC_AHB_ERR = 0; /* write any value to clear */ + MCHP_EC_AHB_ERR = 0; /* write any value to clear */ MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */ /* Manual voltage selection only required for MEC170x and MEC152x */ @@ -435,13 +432,12 @@ static void disable_host_ifc_clocks(void) #else static void disable_host_ifc_clocks(void) { - #ifdef CHIP_FAMILY_MEC170X +#ifdef CHIP_FAMILY_MEC170X MCHP_LPC_ACT &= ~0x1; - #endif +#endif } #endif - /* * Called when hibernation timer is not used in deep sleep. * Switch 32 KHz clock logic from external 32KHz input to @@ -450,7 +446,9 @@ static void disable_host_ifc_clocks(void) * oscillator. */ #ifdef CHIP_FAMILY_MEC172X -static void switch_32k_pin2sil(void) {} +static void switch_32k_pin2sil(void) +{ +} #else static void switch_32k_pin2sil(void) { @@ -483,7 +481,7 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) for (i = MCHP_INT_GIRQ_FIRST; i <= MCHP_INT_GIRQ_LAST; ++i) { MCHP_INT_DISABLE(i) = 0xffffffff; - MCHP_INT_SOURCE(i) = 0xffffffff; + MCHP_INT_SOURCE(i) = 0xffffffff; } /* Disable UART */ @@ -577,14 +575,14 @@ enum ec_image system_get_shrspi_image_copy(void) uint32_t system_get_lfw_address(void) { - uint32_t * const lfw_vector = - (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE; + uint32_t *const lfw_vector = + (uint32_t *const)CONFIG_PROGRAM_MEMORY_BASE; return *(lfw_vector + 1); } void system_set_image_copy(enum ec_image copy) { - MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = (copy == EC_IMAGE_RW) ? - EC_IMAGE_RW : EC_IMAGE_RO; + MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = + (copy == EC_IMAGE_RW) ? EC_IMAGE_RW : EC_IMAGE_RO; } -- cgit v1.2.1 From 93116d385b90995e0683723bbb90abc15c3ed015 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:07 -0600 Subject: board/waddledee/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I64f8b3187ff898422f087e5bca98ec90c3cf91ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729099 Reviewed-by: Jeremy Bettis --- board/waddledee/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledee/usb_pd_policy.c b/board/waddledee/usb_pd_policy.c index 7046e25d6c..042adc0a86 100644 --- a/board/waddledee/usb_pd_policy.c +++ b/board/waddledee/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 61d27b88e3ce4c9ca51d9eb97a51165318c9bc09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:15 -0600 Subject: test/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I45e6f21c676ef5ebec8285c099af90fde908dec8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730500 Reviewed-by: Jeremy Bettis --- test/fan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/fan.c b/test/fan.c index d03aa0213c..683610fd31 100644 --- a/test/fan.c +++ b/test/fan.c @@ -17,7 +17,7 @@ #include "timer.h" #include "util.h" -#define FAN_RPM(fan) fans[fan].rpm +#define FAN_RPM(fan) fans[fan].rpm /*****************************************************************************/ /* Tests */ -- cgit v1.2.1 From b3118643228513aa817584a5ddcef0cbc1005483 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:44 -0600 Subject: zephyr/test/drivers/src/bmi260.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I551f379bc0f45a20404ee747ecdbcc6aed8f1623 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730940 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bmi260.c | 125 +++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 64 deletions(-) diff --git a/zephyr/test/drivers/src/bmi260.c b/zephyr/test/drivers/src/bmi260.c index abcab72898..f4e62535a1 100644 --- a/zephyr/test/drivers/src/bmi260.c +++ b/zephyr/test/drivers/src/bmi260.c @@ -18,28 +18,27 @@ #include "test/drivers/test_mocks.h" #include "test/drivers/test_state.h" -#define BMI_ORD DT_DEP_ORD(DT_NODELABEL(accel_bmi260)) -#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_accel)) -#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro)) -#define BMI_INT_EVENT \ +#define BMI_ORD DT_DEP_ORD(DT_NODELABEL(accel_bmi260)) +#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_accel)) +#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi260_gyro)) +#define BMI_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int))) /** How accurate comparision of vectors should be */ -#define V_EPS 8 +#define V_EPS 8 /** Convert from one type of vector to another */ -#define convert_int3v_int16(v, r) do { \ - r[0] = v[0]; \ - r[1] = v[1]; \ - r[2] = v[2]; \ +#define convert_int3v_int16(v, r) \ + do { \ + r[0] = v[0]; \ + r[1] = v[1]; \ + r[2] = v[2]; \ } while (0) /** Rotation used in some tests */ -static const mat33_fp_t test_rotation = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /** Rotate given vector by test rotation */ static void rotate_int3v_by_test_rotation(intv3_t v) { @@ -126,7 +125,8 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line) int i; for (i = 0; i < 3; i++) { - zassert_within(exp_v[i], v[i], eps, + zassert_within( + exp_v[i], v[i], eps, "Expected [%d; %d; %d], got [%d; %d; %d]; line: %d", exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line); } @@ -208,8 +208,7 @@ ZTEST_USER(bmi260, test_bmi_acc_get_offset) ms->rot_standard_ref = NULL; /* Test get offset without rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v(exp_v, ret_v); @@ -219,8 +218,7 @@ ZTEST_USER(bmi260, test_bmi_acc_get_offset) rotate_int3v_by_test_rotation(exp_v); /* Test get offset with rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v(exp_v, ret_v); @@ -271,8 +269,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_get_offset) ms->rot_standard_ref = NULL; /* Test get offset without rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v_eps(exp_v, ret_v, 64); @@ -282,8 +279,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_get_offset) rotate_int3v_by_test_rotation(exp_v); /* Test get offset with rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v_eps(exp_v, ret_v, 64); @@ -352,8 +348,8 @@ ZTEST_USER(bmi260, test_bmi_acc_set_offset) nv_c = bmi_emul_get_reg(emul, BMI260_NV_CONF); /* Only ACC_OFFSET_EN bit should be changed */ zassert_equal(0x7 | BMI260_ACC_OFFSET_EN, nv_c, - "Expected 0x%x, got 0x%x", - 0x7 | BMI260_ACC_OFFSET_EN, nv_c); + "Expected 0x%x, got 0x%x", 0x7 | BMI260_ACC_OFFSET_EN, + nv_c); /* Setup NV_CONF register value */ bmi_emul_set_reg(emul, BMI260_NV_CONF, 0); @@ -432,7 +428,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_offset) compare_int3v_eps(exp_v, ret_v, 32); /* Gyroscope offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) & - BMI260_OFFSET_GYRO_EN, NULL); + BMI260_OFFSET_GYRO_EN, + NULL); /* Setup rotation and rotate input for set_offset function */ ms->rot_standard_ref = &test_rotation; @@ -445,7 +442,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_set_offset) get_emul_gyr_offset(emul, ret_v); compare_int3v_eps(exp_v, ret_v, 32); zassert_true(bmi_emul_get_reg(emul, BMI260_OFFSET_EN_GYR98) & - BMI260_OFFSET_GYRO_EN, NULL); + BMI260_OFFSET_GYRO_EN, + NULL); } /** @@ -462,8 +460,8 @@ static void check_set_acc_range_f(struct i2c_emul *emul, zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd), "set_range failed; line: %d", line); zassert_equal(exp_range, ms->current_range, - "Expected range %d, got %d; line %d", - exp_range, ms->current_range, line); + "Expected range %d, got %d; line %d", exp_range, + ms->current_range, line); range_reg = bmi_emul_get_reg(emul, BMI260_ACC_RANGE); switch (exp_range) { @@ -491,7 +489,7 @@ static void check_set_acc_range_f(struct i2c_emul *emul, "Expected range reg 0x%x, got 0x%x; line %d", exp_range_reg, range_reg, line); } -#define check_set_acc_range(emul, ms, range, rnd, exp_range) \ +#define check_set_acc_range(emul, ms, range, rnd, exp_range) \ check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__) /** Test set accelerometer range with and without I2C errors */ @@ -514,12 +512,12 @@ ZTEST_USER(bmi260, test_bmi_acc_set_range) /* Test fail on write */ zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL); zassert_equal(start_range, ms->current_range, NULL); - zassert_equal(BMI260_GSEL_2G, - bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL); + zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE), + NULL); zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL); zassert_equal(start_range, ms->current_range, NULL); - zassert_equal(BMI260_GSEL_2G, - bmi_emul_get_reg(emul, BMI260_ACC_RANGE), NULL); + zassert_equal(BMI260_GSEL_2G, bmi_emul_get_reg(emul, BMI260_ACC_RANGE), + NULL); /* Do not fail on write */ i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -567,8 +565,8 @@ static void check_set_gyr_range_f(struct i2c_emul *emul, zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd), "set_range failed; line: %d", line); zassert_equal(exp_range, ms->current_range, - "Expected range %d, got %d; line %d", - exp_range, ms->current_range, line); + "Expected range %d, got %d; line %d", exp_range, + ms->current_range, line); range_reg = bmi_emul_get_reg(emul, BMI260_GYR_RANGE); switch (exp_range) { @@ -599,7 +597,7 @@ static void check_set_gyr_range_f(struct i2c_emul *emul, "Expected range reg 0x%x, got 0x%x; line %d", exp_range_reg, range_reg, line); } -#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \ +#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \ check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__) /** Test set gyroscope range with and without I2C errors */ @@ -741,10 +739,10 @@ static void check_set_acc_rate_f(struct i2c_emul *emul, } zassert_equal(exp_rate_reg, rate_reg, - "Expected rate reg 0x%x, got 0x%x; line %d", - exp_rate_reg, rate_reg, line); + "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg, + rate_reg, line); } -#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \ +#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \ check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__) /** Test set and get accelerometer rate with and without I2C errors */ @@ -798,8 +796,8 @@ ZTEST_USER(bmi260, test_bmi_acc_rate) check_set_acc_rate(emul, ms, 200000, 1, 200000); /* Test out of range rate with rounding down */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 0), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 12499, 0), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -808,10 +806,10 @@ ZTEST_USER(bmi260, test_bmi_acc_rate) ms->drv->set_data_rate(ms, 2000000, 0), NULL); /* Test out of range rate with rounding up */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 1), NULL); - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 6250, 1), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1), + NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 200001, 1), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -945,10 +943,10 @@ static void check_set_gyr_rate_f(struct i2c_emul *emul, } zassert_equal(exp_rate_reg, rate_reg, - "Expected rate reg 0x%x, got 0x%x; line %d", - exp_rate_reg, rate_reg, line); + "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg, + rate_reg, line); } -#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \ +#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \ check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__) /** Test set and get gyroscope rate with and without I2C errors */ @@ -996,8 +994,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate) check_set_gyr_rate(emul, ms, 200000, 1, 200000); /* Test out of range rate with rounding down */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 0), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 24999, 0), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -1006,8 +1004,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_rate) ms->drv->set_data_rate(ms, 4000000, 0), NULL); /* Test out of range rate with rounding up */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 1), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 12499, 1), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -1086,7 +1084,7 @@ ZTEST_USER(bmi260, test_bmi_scale) { struct motion_sensor_t *ms; int16_t ret_scale[3]; - int16_t exp_scale[3] = {100, 231, 421}; + int16_t exp_scale[3] = { 100, 231, 421 }; int16_t t; /* Test accelerometer */ @@ -1198,9 +1196,9 @@ ZTEST_USER(bmi260, test_bmi_acc_read) struct i2c_emul *emul; intv3_t ret_v; intv3_t exp_v; - int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE}; + int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE }; emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_ACC_SENSOR_ID]; @@ -1306,9 +1304,9 @@ ZTEST_USER(bmi260, test_bmi_gyr_read) struct i2c_emul *emul; intv3_t ret_v; intv3_t exp_v; - int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE}; + int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE }; emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_GYR_SENSOR_ID]; @@ -1658,9 +1656,8 @@ static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val, */ static void check_fifo_f(struct motion_sensor_t *ms_acc, struct motion_sensor_t *ms_gyr, - struct bmi_emul_frame *frame, - int acc_range, int gyr_range, - int line) + struct bmi_emul_frame *frame, int acc_range, + int gyr_range, int line) { struct ec_response_motion_sensor_data vector; struct bmi_emul_frame *f_acc, *f_gyr; @@ -1741,7 +1738,7 @@ static void check_fifo_f(struct motion_sensor_t *ms_acc, zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d", line); } -#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \ +#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \ check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__) /** Test irq handler of accelerometer sensor */ -- cgit v1.2.1 From 4a9b467ced3aaa42fb430b2c15f76151ab5d9c2e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:34 -0600 Subject: board/eldrid/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I99fba6ef7ff062b6ea1a5b605ede4225611bf147 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728287 Reviewed-by: Jeremy Bettis --- board/eldrid/board.c | 44 +++++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/board/eldrid/board.c b/board/eldrid/board.c index b3d1bb8293..25ec4ea376 100644 --- a/board/eldrid/board.c +++ b/board/eldrid/board.c @@ -48,7 +48,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -94,7 +94,7 @@ static void board_charger_config(void) ISL9241_REG_CONTROL1, ®) == EC_SUCCESS) { reg |= ISL9241_CONTROL1_PSYS; if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, - ISL9241_REG_CONTROL1, reg)) + ISL9241_REG_CONTROL1, reg)) CPRINTS("Failed to set isl9241"); } @@ -105,7 +105,7 @@ static void board_charger_config(void) ISL9241_REG_CONTROL2, ®) == EC_SUCCESS) { reg &= ~ISL9241_CONTROL2_PROCHOT_DEBOUNCE_MASK; if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, - ISL9241_REG_CONTROL2, reg)) + ISL9241_REG_CONTROL2, reg)) CPRINTS("Failed to set isl9241"); } @@ -116,7 +116,7 @@ static void board_charger_config(void) ISL9241_REG_CONTROL4, ®) == EC_SUCCESS) { reg |= ISL9241_CONTROL4_PSYS_RSENSE_RATIO; if (i2c_write16(I2C_PORT_CHARGER, ISL9241_ADDR_FLAGS, - ISL9241_REG_CONTROL4, reg)) + ISL9241_REG_CONTROL4, reg)) CPRINTS("Failed to set isl9241"); } } @@ -166,12 +166,12 @@ __override bool board_is_tbt_usb4_port(int port) * TODO (b/147732807): All the USB-C ports need to support same * features. Need to fix once USB-C feature set is known for Volteer. */ - return ((port == USBC_PORT_C1) - && ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3))); + return ((port == USBC_PORT_C1) && + ((usb_db == DB_USB4_GEN2) || (usb_db == DB_USB4_GEN3))); } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * b/166728543 @@ -188,9 +188,8 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 90 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /******************************************************************************/ @@ -198,7 +197,7 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -360,8 +359,7 @@ static void ps8815_reset(void) int val; gpio_set_level(ps8xxx_rst_odl, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(ps8xxx_rst_odl, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -372,16 +370,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -393,8 +391,9 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ if (usb_db == DB_USB3_ACTIVE) { ps8815_reset(); - usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(USBC_PORT_C1, + USB_PD_MUX_HPD_LVL_DEASSERTED | + USB_PD_MUX_HPD_IRQ_DEASSERTED); } } @@ -433,8 +432,7 @@ static void config_port_discrete_tcpc(int port) */ if (get_board_id() >= 1) { CPRINTS("C%d: RT1715", port); - tcpc_config[port].i2c_info.addr_flags = - RT1715_I2C_ADDR_FLAGS; + tcpc_config[port].i2c_info.addr_flags = RT1715_I2C_ADDR_FLAGS; tcpc_config[port].drv = &rt1715_tcpm_drv; return; } -- cgit v1.2.1 From ee333088ee95d2bb6d7c72e1030583265df982d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:48 -0600 Subject: board/berknip/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie6ff4a475567dfdb0e0f0646641811ad12bc37c0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728054 Reviewed-by: Jeremy Bettis --- board/berknip/board.h | 84 ++++++++++++++++++++------------------------------- 1 file changed, 33 insertions(+), 51 deletions(-) diff --git a/board/berknip/board.h b/board/berknip/board.h index 5ef9e33f0c..9235acc56f 100644 --- a/board/berknip/board.h +++ b/board/berknip/board.h @@ -30,27 +30,27 @@ #define CONFIG_POWER_SIGNAL_RUNTIME_CONFIG /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ @@ -76,11 +76,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_FAN, PWM_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -90,11 +86,7 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration @@ -147,49 +139,39 @@ enum ec_cfg_usb_db_type { #include "cbi_ec_fw_config.h" -#define HAS_USBC1_RETIMER_PS8743 \ - (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_USBC1_RETIMER_PS8743 (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_usbc1_retimer_ps8743(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_PS8743); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_PS8743); } -#define HAS_USBC1_RETIMER_TUSB544 \ - (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) +#define HAS_USBC1_RETIMER_TUSB544 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_usbc1_retimer_tusb544(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_USBC1_RETIMER_TUSB544); + return !!(BIT(ec_config_get_usb_db()) & HAS_USBC1_RETIMER_TUSB544); } -#define HAS_HDMI_RETIMER_PI3HDX1204 \ - (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) +#define HAS_HDMI_RETIMER_PI3HDX1204 (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_hdmi_retimer_pi3hdx1204(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_RETIMER_PI3HDX1204); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_RETIMER_PI3HDX1204); } -#define HAS_MST_HUB_RTD2141B \ - (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB)) +#define HAS_MST_HUB_RTD2141B (BIT(BERKNIP_DB_T_OPT3_USBAC_HDMI_MSTHUB)) static inline bool ec_config_has_mst_hub_rtd2141b(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_MST_HUB_RTD2141B); + return !!(BIT(ec_config_get_usb_db()) & HAS_MST_HUB_RTD2141B); } -#define HAS_HDMI_CONN_HPD \ - (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) +#define HAS_HDMI_CONN_HPD (BIT(BERKNIP_DB_T_OPT1_USBAC_HMDI)) static inline bool ec_config_has_hdmi_conn_hpd(void) { - return !!(BIT(ec_config_get_usb_db()) & - HAS_HDMI_CONN_HPD); + return !!(BIT(ec_config_get_usb_db()) & HAS_HDMI_CONN_HPD); } enum gpio_signal board_usbc_port_to_hpd_gpio(int port); -- cgit v1.2.1 From 9dd4d261dda0c116a02a76c73b77f7024595a1da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:17 -0600 Subject: board/foob/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70182ef482ac203b34367c72c953b82896401c1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728376 Reviewed-by: Jeremy Bettis --- board/foob/board.c | 62 ++++++++++++++++++++++++++---------------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/board/foob/board.c b/board/foob/board.c index 91d66d88d7..31299597e1 100644 --- a/board/foob/board.c +++ b/board/foob/board.c @@ -31,11 +31,11 @@ #include "util.h" #include "battery_smart.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -60,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -94,11 +94,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate lid and base sensor into standard reference frame */ -const mat33_fp_t standard_rot_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct stprivate_data g_lis2dh_data; @@ -238,11 +236,11 @@ int board_is_lid_angle_tablet_mode(void) } /* Battery functions */ -#define SB_OPTIONALMFG_FUNCTION2 0x3e +#define SB_OPTIONALMFG_FUNCTION2 0x3e /* Optional mfg function2 */ -#define SMART_QUICK_CHARGE (1<<12) +#define SMART_QUICK_CHARGE (1 << 12) /* Quick charge support */ -#define MODE_QUICK_CHARGE_SUPPORT (1<<4) +#define MODE_QUICK_CHARGE_SUPPORT (1 << 4) static void sb_quick_charge_mode(int enable) { -- cgit v1.2.1 From 3ddbabeb2101a219f041699d97272d5f301c6480 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:48 -0600 Subject: driver/ppc/rt1739.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I02cf7267914a280d88416096bf268393a12f83bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730049 Reviewed-by: Jeremy Bettis --- driver/ppc/rt1739.c | 103 +++++++++++++++++++++------------------------------- 1 file changed, 42 insertions(+), 61 deletions(-) diff --git a/driver/ppc/rt1739.c b/driver/ppc/rt1739.c index 7b08faac83..4c8effa483 100644 --- a/driver/ppc/rt1739.c +++ b/driver/ppc/rt1739.c @@ -15,7 +15,6 @@ #include "usbc_ppc.h" #include "util.h" - #if defined(CONFIG_USBC_PPC_VCONN) && !defined(CONFIG_USBC_PPC_POLARITY) #error "Can't use set_vconn without set_polarity" #endif @@ -24,35 +23,28 @@ #define RT1739_FLAGS_FRS_ENABLED BIT(1) static atomic_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) static int read_reg(uint8_t port, int reg, int *val) { - return i2c_read8( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val); + return i2c_read8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, val); } static int write_reg(uint8_t port, int reg, int val) { - return i2c_write8( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, val); + return i2c_write8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, val); } static int update_reg(int port, int reg, int mask, enum mask_update_action action) { - return i2c_update8( - ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, mask, action); + return i2c_update8(ppc_chips[port].i2c_port, + ppc_chips[port].i2c_addr_flags, reg, mask, action); } - static int rt1739_is_sourcing_vbus(int port) { return flags[port] & RT1739_FLAGS_SOURCE_ENABLED; @@ -63,11 +55,11 @@ static int rt1739_vbus_source_enable(int port, int enable) atomic_t prev_flag; if (enable) - prev_flag = atomic_or(&flags[port], - RT1739_FLAGS_SOURCE_ENABLED); + prev_flag = + atomic_or(&flags[port], RT1739_FLAGS_SOURCE_ENABLED); else prev_flag = atomic_clear_bits(&flags[port], - RT1739_FLAGS_SOURCE_ENABLED); + RT1739_FLAGS_SOURCE_ENABLED); /* Return if status doesn't change */ if (!!(prev_flag & RT1739_FLAGS_SOURCE_ENABLED) == !!enable) @@ -90,10 +82,8 @@ static int rt1739_vbus_source_enable(int port, int enable) static int rt1739_vbus_sink_enable(int port, int enable) { - return update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, - RT1739_HV_SNK_EN, + return update_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, RT1739_HV_SNK_EN, enable ? MASK_SET : MASK_CLR); - } #ifdef CONFIG_CMD_PPC_DUMP @@ -145,8 +135,7 @@ static int rt1739_is_vbus_present(int port) #ifdef CONFIG_USBC_PPC_POLARITY static int rt1739_set_polarity(int port, int polarity) { - return update_reg(port, RT1739_REG_VCONN_CTRL1, - RT1739_VCONN_ORIENT, + return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_ORIENT, polarity ? RT1739_VCONN_ORIENT_CC1 : RT1739_VCONN_ORIENT_CC2); } @@ -155,9 +144,8 @@ static int rt1739_set_polarity(int port, int polarity) #ifdef CONFIG_USBC_PPC_VCONN static int rt1739_set_vconn(int port, int enable) { - return update_reg(port, RT1739_REG_VCONN_CTRL1, - RT1739_VCONN_EN, - enable ? MASK_SET : MASK_CLR); + return update_reg(port, RT1739_REG_VCONN_CTRL1, RT1739_VCONN_EN, + enable ? MASK_SET : MASK_CLR); } #endif @@ -176,14 +164,13 @@ static int rt1739_workaround(int port) case RT1739_DEVICE_ID_ES1: CPRINTS("RT1739 ES1"); RETURN_ERROR(update_reg(port, RT1739_REG_SYS_CTRL1, - RT1739_OSC640K_FORCE_EN, - MASK_SET)); + RT1739_OSC640K_FORCE_EN, MASK_SET)); RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS, RT1739_OVP_DISVBUS_EN | - RT1739_UVLO_DISVBUS_EN | - RT1739_SCP_DISVBUS_EN | - RT1739_OCPS_DISVBUS_EN)); + RT1739_UVLO_DISVBUS_EN | + RT1739_SCP_DISVBUS_EN | + RT1739_OCPS_DISVBUS_EN)); break; case RT1739_DEVICE_ID_ES2: @@ -208,14 +195,13 @@ static int rt1739_workaround(int port) msleep(5); RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_SWITCH_CTRL, 0)); msleep(5); - RETURN_ERROR(write_reg(port, RT1739_VBUS_FAULT_DIS, - RT1739_OVP_DISVBUS_EN | - RT1739_UVLO_DISVBUS_EN | - RT1739_RCP_DISVBUS_EN | - RT1739_SCP_DISVBUS_EN)); - RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_CTRL1, - RT1739_HVLV_SCP_EN | - RT1739_HVLV_OCRC_EN)); + RETURN_ERROR(write_reg( + port, RT1739_VBUS_FAULT_DIS, + RT1739_OVP_DISVBUS_EN | RT1739_UVLO_DISVBUS_EN | + RT1739_RCP_DISVBUS_EN | RT1739_SCP_DISVBUS_EN)); + RETURN_ERROR( + write_reg(port, RT1739_REG_VBUS_CTRL1, + RT1739_HVLV_SCP_EN | RT1739_HVLV_OCRC_EN)); break; default: @@ -229,8 +215,7 @@ static int rt1739_workaround(int port) static int rt1739_set_frs_enable(int port, int enable) { /* Enable FRS RX detect */ - RETURN_ERROR(update_reg(port, RT1739_REG_CC_FRS_CTRL1, - RT1739_FRS_RX_EN, + RETURN_ERROR(update_reg(port, RT1739_REG_CC_FRS_CTRL1, RT1739_FRS_RX_EN, enable ? MASK_SET : MASK_CLR)); /* @@ -243,8 +228,7 @@ static int rt1739_set_frs_enable(int port, int enable) RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK5, RT1739_BC12_SNK_DONE_MASK, enable ? MASK_CLR : MASK_SET)); - RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK4, - RT1739_FRS_RX_MASK, + RETURN_ERROR(update_reg(port, RT1739_REG_INT_MASK4, RT1739_FRS_RX_MASK, enable ? MASK_SET : MASK_CLR)); if (enable) atomic_or(&flags[port], RT1739_FLAGS_FRS_ENABLED); @@ -268,22 +252,19 @@ static int rt1739_init(int port) RETURN_ERROR(rt1739_workaround(port)); RETURN_ERROR(rt1739_set_frs_enable(port, false)); RETURN_ERROR(update_reg(port, RT1739_REG_VBUS_DET_EN, - RT1739_VBUS_PRESENT_EN, - MASK_SET)); + RT1739_VBUS_PRESENT_EN, MASK_SET)); RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01, - RT1739_DM_SWEN | RT1739_DP_SWEN, - MASK_SET)); + RT1739_DM_SWEN | RT1739_DP_SWEN, MASK_SET)); RETURN_ERROR(update_reg(port, RT1739_REG_SBU_CTRL_01, - RT1739_SBUSW_MUX_SEL, - MASK_CLR)); + RT1739_SBUSW_MUX_SEL, MASK_CLR)); RETURN_ERROR(update_reg(port, RT1739_REG_VCONN_CTRL3, - RT1739_VCONN_CLIMIT_EN, - MASK_SET)); + RT1739_VCONN_CLIMIT_EN, MASK_SET)); /* VBUS OVP -> 23V */ - RETURN_ERROR(write_reg(port, RT1739_REG_VBUS_OV_SETTING, + RETURN_ERROR(write_reg( + port, RT1739_REG_VBUS_OV_SETTING, (RT1739_OVP_SEL_23_0V << RT1739_VBUS_OVP_SEL_SHIFT) | - (RT1739_OVP_SEL_23_0V << RT1739_VIN_HV_OVP_SEL_SHIFT))); + (RT1739_OVP_SEL_23_0V << RT1739_VIN_HV_OVP_SEL_SHIFT))); /* VBUS OCP -> 3.3A (or 5.5A for ES2 HV Sink) */ RETURN_ERROR(rt1739_get_device_id(port, &device_id)); if (device_id == RT1739_DEVICE_ID_ES2) @@ -317,7 +298,7 @@ static void rt1739_update_charge_manager(int port, if (new_bc12_type != current_bc12_type) { if (current_bc12_type != CHARGE_SUPPLIER_NONE) charge_manager_update_charge(current_bc12_type, port, - NULL); + NULL); if (new_bc12_type != CHARGE_SUPPLIER_NONE) { struct charge_port_info chg = { @@ -334,8 +315,8 @@ static void rt1739_update_charge_manager(int port, static void rt1739_enable_bc12_detection(int port, bool enable) { - update_reg(port, RT1739_REG_BC12_SNK_FUNC, - RT1739_BC12_SNK_EN, enable ? MASK_SET : MASK_CLR); + update_reg(port, RT1739_REG_BC12_SNK_FUNC, RT1739_BC12_SNK_EN, + enable ? MASK_SET : MASK_CLR); } static enum charge_supplier rt1739_bc12_get_device_type(int port) @@ -370,16 +351,16 @@ static void rt1739_usb_charger_task_init(const int port) static void rt1739_usb_charger_task_event(const int port, uint32_t evt) { bool is_non_pd_sink = !pd_capable(port) && - !usb_charger_port_is_sourcing_vbus(port) && - pd_check_vbus_level(port, VBUS_PRESENT); + !usb_charger_port_is_sourcing_vbus(port) && + pd_check_vbus_level(port, VBUS_PRESENT); /* vbus change, start bc12 detection */ if (evt & USB_CHG_EVENT_VBUS) { if (is_non_pd_sink) rt1739_enable_bc12_detection(port, true); else - rt1739_update_charge_manager( - port, CHARGE_SUPPLIER_NONE); + rt1739_update_charge_manager(port, + CHARGE_SUPPLIER_NONE); } /* detection done, update charge_manager and stop detection */ -- cgit v1.2.1 From 1f01679d576add340563ec910d49b1e3b3b25ede Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:11 -0600 Subject: board/kappa/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If442dafa2a1a885b8b992f2f0d949eb96e7a7509 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728527 Reviewed-by: Jeremy Bettis --- board/kappa/led.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/kappa/led.c b/board/kappa/led.c index 5b65d7b948..7caac3dfef 100644 --- a/board/kappa/led.c +++ b/board/kappa/led.c @@ -14,7 +14,7 @@ #define BAT_LED_ON 0 #define BAT_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -22,7 +22,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -87,11 +87,10 @@ static void led_set_battery(void) battery_ticks++; /* override battery led for system suspend */ - if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) && charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } @@ -119,8 +118,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); -- cgit v1.2.1 From be03adcb07a49f504f36c1bf534b634c48b432db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:19 -0600 Subject: common/acpi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieaccdef443aea8a3c5709aa3fb5287b6afcc24cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729582 Reviewed-by: Jeremy Bettis --- common/acpi.c | 55 ++++++++++++++++++++++++++----------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/common/acpi.c b/common/acpi.c index c234347019..ffb6acbc22 100644 --- a/common/acpi.c +++ b/common/acpi.c @@ -24,8 +24,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) /* Last received ACPI command */ static uint8_t acpi_cmd; @@ -37,8 +37,8 @@ static int acpi_data_count; static uint8_t acpi_mem_test; #ifdef CONFIG_DPTF -static int dptf_temp_sensor_id; /* last sensor ID written */ -static int dptf_temp_threshold; /* last threshold written */ +static int dptf_temp_sensor_id; /* last sensor ID written */ +static int dptf_temp_threshold; /* last threshold written */ /* * Current DPTF profile number. @@ -62,9 +62,9 @@ static int current_dptf_profile = DPTF_PROFILE_DEFAULT; #define ACPI_READ_CACHE_FLUSHED (EC_ACPI_MEM_MAPPED_BEGIN - 1) /* Calculate size of valid cache based upon end of memmap data. */ -#define ACPI_VALID_CACHE_SIZE(addr) (MIN( \ - EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \ - ACPI_READ_CACHE_SIZE)) +#define ACPI_VALID_CACHE_SIZE(addr) \ + (MIN(EC_ACPI_MEM_MAPPED_SIZE + EC_ACPI_MEM_MAPPED_BEGIN - (addr), \ + ACPI_READ_CACHE_SIZE)) /* * In burst mode, read the requested memmap data and the data immediately @@ -140,24 +140,20 @@ static int acpi_read(uint8_t addr) /* Check for out-of-range read. */ if (addr < EC_ACPI_MEM_MAPPED_BEGIN || addr >= EC_ACPI_MEM_MAPPED_BEGIN + EC_ACPI_MEM_MAPPED_SIZE) { - CPRINTS("ACPI read 0x%02x (ignored)", - acpi_addr); + CPRINTS("ACPI read 0x%02x (ignored)", acpi_addr); return 0xff; } #ifdef __clang__ #pragma clang diagnostic pop #endif /* __clang__ */ - /* Read from cache if enabled (burst mode). */ if (acpi_read_cache.enabled) { /* Fetch to cache on miss. */ if (acpi_read_cache.start_addr == ACPI_READ_CACHE_FLUSHED || acpi_read_cache.start_addr > addr || - addr - acpi_read_cache.start_addr >= - ACPI_READ_CACHE_SIZE) { - memcpy(acpi_read_cache.data, - memmap_addr, + addr - acpi_read_cache.start_addr >= ACPI_READ_CACHE_SIZE) { + memcpy(acpi_read_cache.data, memmap_addr, ACPI_VALID_CACHE_SIZE(addr)); acpi_read_cache.start_addr = addr; } @@ -177,7 +173,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) { int data = 0; int retval = 0; - int result = 0xff; /* value for bogus read */ + int result = 0xff; /* value for bogus read */ /* Read command/data; this clears the FRMH status bit. */ if (is_cmd) { @@ -241,7 +237,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) #ifdef CONFIG_DPTF result |= (acpi_dptf_get_profile_num() & EC_ACPI_MEM_DDPN_MASK) - << EC_ACPI_MEM_DDPN_SHIFT; + << EC_ACPI_MEM_DDPN_SHIFT; #endif break; @@ -260,7 +256,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) result = val >> (8 * off); break; - } + } case EC_ACPI_MEM_DEVICE_FEATURES4: case EC_ACPI_MEM_DEVICE_FEATURES5: case EC_ACPI_MEM_DEVICE_FEATURES6: @@ -270,7 +266,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) result = val >> (8 * off); break; - } + } #ifdef CONFIG_USB_PORT_POWER_DUMB case EC_ACPI_MEM_USB_PORT_POWER: { @@ -289,7 +285,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) result |= 1 << i; } break; - } + } #endif #ifdef CONFIG_USBC_RETIMER_FW_UPDATE case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE: @@ -324,8 +320,8 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) * does a lot of keyboard backlights and it scrolls the * debug console. */ - CPRINTF("\r[%pT ACPI kblight %d]", - PRINTF_TIMESTAMP_NOW, data); + CPRINTF("\r[%pT ACPI kblight %d]", PRINTF_TIMESTAMP_NOW, + data); kblight_set(data); kblight_enable(data > 0); break; @@ -342,13 +338,12 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) case EC_ACPI_MEM_TEMP_THRESHOLD: dptf_temp_threshold = data + EC_TEMP_SENSOR_OFFSET; break; - case EC_ACPI_MEM_TEMP_COMMIT: - { + case EC_ACPI_MEM_TEMP_COMMIT: { int idx = data & EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK; int enable = data & EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK; dptf_set_temp_threshold(dptf_temp_sensor_id, - dptf_temp_threshold, - idx, enable); + dptf_temp_threshold, idx, + enable); break; } #endif @@ -380,8 +375,9 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) if (mode_field & 1) mode = USB_CHARGE_MODE_ENABLED; - if (usb_charge_set_mode(i, mode, - USB_ALLOW_SUSPEND_CHARGE)) { + if (usb_charge_set_mode( + i, mode, + USB_ALLOW_SUSPEND_CHARGE)) { CPRINTS("ERROR: could not set charge " "mode of USB port p%d to %d", i, mode); @@ -389,7 +385,7 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) mode_field >>= 1; } break; - } + } #endif #ifdef CONFIG_USBC_RETIMER_FW_UPDATE case EC_ACPI_MEM_USB_RETIMER_FW_UPDATE: @@ -427,7 +423,8 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) * Disable from deferred function in case burst mode is enabled * for an extremely long time (ex. kernel bug / crash). */ - hook_call_deferred(&acpi_disable_burst_deferred_data, 1*SECOND); + hook_call_deferred(&acpi_disable_burst_deferred_data, + 1 * SECOND); /* ACPI 5.0-12.3.3: Burst ACK */ *resultptr = 0x90; -- cgit v1.2.1 From 6e8525503af343408364ea45fa069baa99b0c5e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:16 -0600 Subject: baseboard/volteer/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1a471b85c18aeeaaf3dccddf989755095bcf761 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727949 Reviewed-by: Jeremy Bettis --- baseboard/volteer/cbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/volteer/cbi.c b/baseboard/volteer/cbi.c index ea446acc4e..8a3dcef5ed 100644 --- a/baseboard/volteer/cbi.c +++ b/baseboard/volteer/cbi.c @@ -11,8 +11,8 @@ #include "hooks.h" #include "system.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ##args) static uint8_t board_id; -- cgit v1.2.1 From c589c04595af36d077b25816954486b25d607a79 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:42 -0600 Subject: chip/mt_scp/rv32i_common/csr.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8548d39099366f682d8b64e7301037200dd0daf1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729368 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/csr.h | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/chip/mt_scp/rv32i_common/csr.h b/chip/mt_scp/rv32i_common/csr.h index 7c767d0592..4b9834f6d6 100644 --- a/chip/mt_scp/rv32i_common/csr.h +++ b/chip/mt_scp/rv32i_common/csr.h @@ -22,14 +22,14 @@ static inline uint32_t read_csr(uint32_t reg) static inline void write_csr(uint32_t reg, uint32_t val) { - asm volatile ("csrw %0, %1" :: "i"(reg), "r"(val)); + asm volatile("csrw %0, %1" ::"i"(reg), "r"(val)); } static inline uint32_t set_csr(uint32_t reg, uint32_t bit) { uint32_t val; - asm volatile ("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); + asm volatile("csrrs %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); return val; } @@ -37,75 +37,75 @@ static inline uint32_t clear_csr(uint32_t reg, uint32_t bit) { uint32_t val; - asm volatile ("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); + asm volatile("csrrc %0, %1, %2" : "=r"(val) : "i"(reg), "r"(bit)); return val; } /* VIC */ -#define CSR_VIC_MICAUSE (0x5c0) -#define CSR_VIC_MIEMS (0x5c2) -#define CSR_VIC_MIPEND_G0 (0x5d0) -#define CSR_VIC_MIMASK_G0 (0x5d8) -#define CSR_VIC_MIWAKEUP_G0 (0x5e0) -#define CSR_VIC_MILSEL_G0 (0x5e8) -#define CSR_VIC_MIEMASK_G0 (0x5f0) +#define CSR_VIC_MICAUSE (0x5c0) +#define CSR_VIC_MIEMS (0x5c2) +#define CSR_VIC_MIPEND_G0 (0x5d0) +#define CSR_VIC_MIMASK_G0 (0x5d8) +#define CSR_VIC_MIWAKEUP_G0 (0x5e0) +#define CSR_VIC_MILSEL_G0 (0x5e8) +#define CSR_VIC_MIEMASK_G0 (0x5f0) /* centralized control enable */ -#define CSR_MCTREN (0x7c0) +#define CSR_MCTREN (0x7c0) /* I$, D$, ITCM, DTCM, BTB, RAS, VIC, CG, mpu */ -#define CSR_MCTREN_ICACHE BIT(0) -#define CSR_MCTREN_DCACHE BIT(1) -#define CSR_MCTREN_ITCM BIT(2) -#define CSR_MCTREN_DTCM BIT(3) -#define CSR_MCTREN_BTB BIT(4) -#define CSR_MCTREN_RAS BIT(5) -#define CSR_MCTREN_VIC BIT(6) -#define CSR_MCTREN_CG BIT(7) -#define CSR_MCTREN_MPU BIT(8) +#define CSR_MCTREN_ICACHE BIT(0) +#define CSR_MCTREN_DCACHE BIT(1) +#define CSR_MCTREN_ITCM BIT(2) +#define CSR_MCTREN_DTCM BIT(3) +#define CSR_MCTREN_BTB BIT(4) +#define CSR_MCTREN_RAS BIT(5) +#define CSR_MCTREN_VIC BIT(6) +#define CSR_MCTREN_CG BIT(7) +#define CSR_MCTREN_MPU BIT(8) /* MPU */ -#define CSR_MPU_ENTRY_EN (0x9c0) -#define CSR_MPU_LITCM (0x9dc) -#define CSR_MPU_LDTCM (0x9dd) -#define CSR_MPU_HITCM (0x9de) -#define CSR_MPU_HDTCM (0x9df) -#define CSR_MPU_L(n) (0x9e0 + (n)) -#define CSR_MPU_H(n) (0x9f0 + (n)) +#define CSR_MPU_ENTRY_EN (0x9c0) +#define CSR_MPU_LITCM (0x9dc) +#define CSR_MPU_LDTCM (0x9dd) +#define CSR_MPU_HITCM (0x9de) +#define CSR_MPU_HDTCM (0x9df) +#define CSR_MPU_L(n) (0x9e0 + (n)) +#define CSR_MPU_H(n) (0x9f0 + (n)) /* MPU attributes: set if permitted */ /* Privilege, machine mode in RISC-V. We don't use the flag because * we don't separate user / machine mode in EC OS. */ -#define MPU_ATTR_P BIT(5) +#define MPU_ATTR_P BIT(5) /* Readable */ -#define MPU_ATTR_R BIT(6) +#define MPU_ATTR_R BIT(6) /* Writable */ -#define MPU_ATTR_W BIT(7) +#define MPU_ATTR_W BIT(7) /* Cacheable */ -#define MPU_ATTR_C BIT(8) +#define MPU_ATTR_C BIT(8) /* Bufferable */ -#define MPU_ATTR_B BIT(9) +#define MPU_ATTR_B BIT(9) /* PMU */ -#define CSR_PMU_MPMUCTR (0xbc0) -#define CSR_PMU_MPMUCTR_C BIT(0) -#define CSR_PMU_MPMUCTR_I BIT(1) -#define CSR_PMU_MPMUCTR_H3 BIT(2) -#define CSR_PMU_MPMUCTR_H4 BIT(3) -#define CSR_PMU_MPMUCTR_H5 BIT(4) - -#define CSR_PMU_MCYCLE (0xb00) -#define CSR_PMU_MINSTRET (0xb02) -#define CSR_PMU_MHPMCOUNTER3 (0xb03) -#define CSR_PMU_MHPMCOUNTER4 (0xb04) -#define CSR_PMU_MHPMCOUNTER5 (0xb05) - -#define CSR_PMU_MCYCLEH (0xb80) -#define CSR_PMU_MINSTRETH (0xb82) -#define CSR_PMU_MHPMCOUNTER3H (0xb83) -#define CSR_PMU_MHPMCOUNTER4H (0xb84) -#define CSR_PMU_MHPMCOUNTER5H (0xb85) - -#define CSR_PMU_MHPMEVENT3 (0x323) -#define CSR_PMU_MHPMEVENT4 (0x324) -#define CSR_PMU_MHPMEVENT5 (0x325) +#define CSR_PMU_MPMUCTR (0xbc0) +#define CSR_PMU_MPMUCTR_C BIT(0) +#define CSR_PMU_MPMUCTR_I BIT(1) +#define CSR_PMU_MPMUCTR_H3 BIT(2) +#define CSR_PMU_MPMUCTR_H4 BIT(3) +#define CSR_PMU_MPMUCTR_H5 BIT(4) + +#define CSR_PMU_MCYCLE (0xb00) +#define CSR_PMU_MINSTRET (0xb02) +#define CSR_PMU_MHPMCOUNTER3 (0xb03) +#define CSR_PMU_MHPMCOUNTER4 (0xb04) +#define CSR_PMU_MHPMCOUNTER5 (0xb05) + +#define CSR_PMU_MCYCLEH (0xb80) +#define CSR_PMU_MINSTRETH (0xb82) +#define CSR_PMU_MHPMCOUNTER3H (0xb83) +#define CSR_PMU_MHPMCOUNTER4H (0xb84) +#define CSR_PMU_MHPMCOUNTER5H (0xb85) + +#define CSR_PMU_MHPMEVENT3 (0x323) +#define CSR_PMU_MHPMEVENT4 (0x324) +#define CSR_PMU_MHPMEVENT5 (0x325) #endif /* __CROS_EC_CSR_H */ -- cgit v1.2.1 From ca1f48f2fe6fefe1b7e8b22d8fe6a4f2f1d555aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:00 -0600 Subject: board/willow/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If44aabda3c33ad7d81e78a99e4e064c9241a4e50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729130 Reviewed-by: Jeremy Bettis --- board/willow/board.c | 75 ++++++++++++++++++++++------------------------------ 1 file changed, 32 insertions(+), 43 deletions(-) diff --git a/board/willow/board.c b/board/willow/board.c index fcf679f108..9cb384f05c 100644 --- a/board/willow/board.c +++ b/board/willow/board.c @@ -43,8 +43,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -56,40 +56,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -97,8 +91,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -154,8 +148,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -237,12 +230,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -299,8 +292,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -314,8 +306,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -354,11 +345,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; -- cgit v1.2.1 From e830eaa75e103032ae3819bc697819fcdbcd856c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:59 -0600 Subject: board/felwinter/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I646ecd893599e2cc808c631d909ceb51a5a86f88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728353 Reviewed-by: Jeremy Bettis --- board/felwinter/board.h | 149 +++++++++++++++++++++--------------------------- 1 file changed, 65 insertions(+), 84 deletions(-) diff --git a/board/felwinter/board.h b/board/felwinter/board.h index 26feb8de3c..8cd431fb99 100644 --- a/board/felwinter/board.h +++ b/board/felwinter/board.h @@ -24,12 +24,12 @@ /* LED */ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 -#define GPIO_PWR_LED_WHITE_L GPIO_LED_1_L -#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L -#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L +#define GPIO_PWR_LED_WHITE_L GPIO_LED_1_L +#define GPIO_BAT_LED_AMBER_L GPIO_LED_3_L +#define GPIO_BAT_LED_WHITE_L GPIO_LED_4_L /* Sensors */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -43,19 +43,18 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_LIS2DWL #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) - /* Sensor console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -63,7 +62,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_TCPM_PS8815 #define CONFIG_USBC_RETIMER_INTEL_BB @@ -78,17 +77,17 @@ #define CONFIG_USBC_PPC_NX20P3483 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -96,67 +95,67 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* * */ -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x58 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -173,19 +172,19 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_KEYBOARD_REFRESH_ROW3 #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -203,39 +202,21 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C2_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C2_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; -enum battery_type { - BATTERY_C536, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_C536, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; void pen_detect_interrupt(enum gpio_signal s); -- cgit v1.2.1 From 6acc3e8aef0afd8b9969acbeb4db9d1f7dfa45e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:15 -0600 Subject: zephyr/test/i2c/src/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4a65fbaf7e6caedfcdb37ccc1693627298229324 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730962 Reviewed-by: Jeremy Bettis --- zephyr/test/i2c/src/main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/test/i2c/src/main.c b/zephyr/test/i2c/src/main.c index dbe9878da5..8f068b238f 100644 --- a/zephyr/test/i2c/src/main.c +++ b/zephyr/test/i2c/src/main.c @@ -27,7 +27,6 @@ static void test_i2c_port_count(void) /* Test case main entry. */ void test_main(void) { - ztest_test_suite(test_i2c, - ztest_user_unit_test(test_i2c_port_count)); + ztest_test_suite(test_i2c, ztest_user_unit_test(test_i2c_port_count)); ztest_run_test_suite(test_i2c); } -- cgit v1.2.1 From 83668232ab63f5ff80fb01a050675c948f89e460 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:28 -0600 Subject: chip/mchp/tfdp_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03bc7d4f4c7ad080ed34583bbd8158f418a463f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729304 Reviewed-by: Jeremy Bettis --- chip/mchp/tfdp_chip.h | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/chip/mchp/tfdp_chip.h b/chip/mchp/tfdp_chip.h index 64d4d0b77e..e7ee42853e 100644 --- a/chip/mchp/tfdp_chip.h +++ b/chip/mchp/tfdp_chip.h @@ -13,7 +13,6 @@ #include - #ifdef CONFIG_MCHP_TFDP #undef TRACE0 @@ -35,19 +34,19 @@ #undef trace13 #undef trace14 -#define MCHP_TFDP_BASE_ADDR (0x40008c00ul) +#define MCHP_TFDP_BASE_ADDR (0x40008c00ul) -#define TFDP_FRAME_START (0xFD) +#define TFDP_FRAME_START (0xFD) -#define TFDP_POWER_ON (1u) -#define TFDP_POWER_OFF (0u) +#define TFDP_POWER_ON (1u) +#define TFDP_POWER_OFF (0u) -#define TFDP_ENABLE (1u) -#define TFDP_DISABLE (0u) -#define TFDP_CFG_PINS (1u) -#define TFDP_NO_CFG_PINS (0u) +#define TFDP_ENABLE (1u) +#define TFDP_DISABLE (0u) +#define TFDP_CFG_PINS (1u) +#define TFDP_NO_CFG_PINS (0u) -#define MCHP_TRACE_MASK_IRQ +#define MCHP_TRACE_MASK_IRQ #define TFDP_DELAY() @@ -59,18 +58,15 @@ void tfdp_power(uint8_t pwr_on); void tfdp_enable(uint8_t en, uint8_t pin_cfg); void TFDPTrace0(uint16_t nbr); void TFDPTrace1(uint16_t nbr, uint32_t p1); -void TFDPTrace2(uint16_t nbr, uint32_t p1, - uint32_t p2); -void TFDPTrace3(uint16_t nbr, uint32_t p1, - uint32_t p2, uint32_t p3); -void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4); +void TFDPTrace2(uint16_t nbr, uint32_t p1, uint32_t p2); +void TFDPTrace3(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3); +void TFDPTrace4(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3, + uint32_t p4); void TFDPTrace11(uint16_t nbr, uint32_t p1); void TFDPTrace12(uint16_t nbr, uint32_t p1, uint32_t p2); -void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3); -void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, - uint32_t p3, uint32_t p4); +void TFDPTrace13(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3); +void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, uint32_t p3, + uint32_t p4); #ifdef __cplusplus } @@ -80,15 +76,13 @@ void TFDPTrace14(uint16_t nbr, uint32_t p1, uint32_t p2, #define TRACE1(nbr, cat, b, str, p1) TFDPTrace1(nbr, p1) #define TRACE2(nbr, cat, b, str, p1, p2) TFDPTrace2(nbr, p1, p2) #define TRACE3(nbr, cat, b, str, p1, p2, p3) TFDPTrace3(nbr, p1, p2, p3) -#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, \ - p3, p4) +#define TRACE4(nbr, cat, b, str, p1, p2, p3, p4) TFDPTrace4(nbr, p1, p2, p3, p4) #define TRACE11(nbr, cat, b, str, p1) TFDPTrace11(nbr, p1) #define TRACE12(nbr, cat, b, str, p1, p2) TFDPTrace12(nbr, p1, p2) #define TRACE13(nbr, cat, b, str, p1, p2, p3) TFDPTrace13(nbr, p1, p2, p3) #define TRACE14(nbr, cat, b, str, p1, p2, p3, p4) \ TFDPTrace14(nbr, p1, p2, p3, p4) - #else /* #ifdef MCHP_TRACE */ /* !!! To prevent compiler warnings of unused parameters, -- cgit v1.2.1 From 14e4d88e424d17ff2deefbd08853f5b4f041f9e3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:13 -0600 Subject: core/minute-ia/mia_panic_internal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e73535092a5c253c8e035d8492439e8b8d84adc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729855 Reviewed-by: Jeremy Bettis --- core/minute-ia/mia_panic_internal.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/core/minute-ia/mia_panic_internal.h b/core/minute-ia/mia_panic_internal.h index 748ccbf2dd..a1c593ec05 100644 --- a/core/minute-ia/mia_panic_internal.h +++ b/core/minute-ia/mia_panic_internal.h @@ -8,10 +8,5 @@ * convenientely in the same order as pushed by hardwared during a * processor exception. */ -noreturn -void exception_panic( - uint32_t vector, - uint32_t errorcode, - uint32_t eip, - uint32_t cs, - uint32_t eflags); +noreturn void exception_panic(uint32_t vector, uint32_t errorcode, uint32_t eip, + uint32_t cs, uint32_t eflags); -- cgit v1.2.1 From 59e8930347118a1ae0abed6a886f67a3f47dbb34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:20 -0600 Subject: chip/stm32/debug_printf.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id099b0bf20beeec0685ae8d9b024b623ba7e63fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729488 Reviewed-by: Jeremy Bettis --- chip/stm32/debug_printf.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/chip/stm32/debug_printf.c b/chip/stm32/debug_printf.c index c4e151692c..bdf548e9e1 100644 --- a/chip/stm32/debug_printf.c +++ b/chip/stm32/debug_printf.c @@ -27,8 +27,6 @@ static int debug_txchar(void *context, int c) return 0; } - - void debug_printf(const char *format, ...) { va_list args; @@ -102,8 +100,8 @@ void uart_init(void) STM32_USART_BRR(UARTN_BASE) = DIV_ROUND_NEAREST(CPU_CLOCK, CONFIG_UART_BAUD_RATE); /* UART enabled, 8 Data bits, oversampling x16, no parity */ - STM32_USART_CR1(UARTN_BASE) = - STM32_USART_CR1_UE | STM32_USART_CR1_TE | STM32_USART_CR1_RE; + STM32_USART_CR1(UARTN_BASE) = STM32_USART_CR1_UE | STM32_USART_CR1_TE | + STM32_USART_CR1_RE; /* 1 stop bit, no fancy stuff */ STM32_USART_CR2(UARTN_BASE) = 0x0000; /* DMA disabled, special modes disabled, error interrupt disabled */ -- cgit v1.2.1 From a98881ee7759ff2e9b5c96c95fc2b7f29cf57b6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:41 -0600 Subject: test/usb_tcpmv2_td_pd_vndi3_e3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61f6891a77e700468ce4e69dede5fe26542b99ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730578 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_vndi3_e3.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_vndi3_e3.c b/test/usb_tcpmv2_td_pd_vndi3_e3.c index cbfc0d75e3..acea194963 100644 --- a/test/usb_tcpmv2_td_pd_vndi3_e3.c +++ b/test/usb_tcpmv2_td_pd_vndi3_e3.c @@ -11,10 +11,8 @@ #include "usb_tcpmv2_compliance.h" #include "usb_tc_sm.h" -uint32_t vdo = VDO(USB_SID_PD, 1, - VDO_SVDM_VERS(VDM_VER20) | - CMD_DISCOVER_IDENT); - +uint32_t vdo = + VDO(USB_SID_PD, 1, VDO_SVDM_VERS(VDM_VER20) | CMD_DISCOVER_IDENT); /***************************************************************************** * TD.PD.VNDI3.E3.VDM Identity @@ -32,8 +30,8 @@ static int td_pd_vndi3_e3(enum pd_data_role data_role) /* * a) Run PROC.PD.E1 Bring-up according to the UUT role. */ - TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), - EC_SUCCESS, "%d"); + TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS, + "%d"); /* * Make sure we are idle. Reject everything that is pending @@ -43,8 +41,7 @@ static int td_pd_vndi3_e3(enum pd_data_role data_role) /* * b) Tester executes a Discover Identity exchange */ - partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF, - 1, 0, &vdo); + partner_send_msg(TCPCI_MSG_SOP, PD_DATA_VENDOR_DEF, 1, 0, &vdo); /* * c) If the UUT is not a cable and if Responds_To_Discov_SOP is set to -- cgit v1.2.1 From 7937d7ba677c000ec369cfb5fb164b3bd6595b31 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:58 -0600 Subject: board/brask/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4dfd80f3be46f1cf7529657d7b66f3da4bdcf6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728092 Reviewed-by: Jeremy Bettis --- board/brask/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brask/fw_config.c b/board/brask/fw_config.c index a5857ef48f..5b987f7ebc 100644 --- a/board/brask/fw_config.c +++ b/board/brask/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union brask_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 84b39ce62ceb2c596b229daa271cad3966da38ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:17 -0600 Subject: board/coffeecake/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If7d8c1dbb06b576e07a70c51e15175d4b4859ee6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728172 Reviewed-by: Jeremy Bettis --- board/coffeecake/usb_pd_pdo.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/board/coffeecake/usb_pd_pdo.c b/board/coffeecake/usb_pd_pdo.c index a766d7dbe5..6dcc48e7ba 100644 --- a/board/coffeecake/usb_pd_pdo.c +++ b/board/coffeecake/usb_pd_pdo.c @@ -7,15 +7,16 @@ #include "usb_pd.h" #include "usb_pd_pdo.h" -#define PDO_FIXED_FLAGS_EXT (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED) +#define PDO_FIXED_FLAGS_EXT \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \ + PDO_FIXED_UNCONSTRAINED) -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) const uint32_t pd_src_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS_EXT), - [PDO_IDX_9V] = PDO_FIXED(9000, 2500, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS_EXT), + [PDO_IDX_9V] = PDO_FIXED(9000, 2500, PDO_FIXED_FLAGS), }; const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); BUILD_ASSERT(ARRAY_SIZE(pd_src_pdo) == PDO_IDX_COUNT); -- cgit v1.2.1 From bbef9f4f551083a003d241dc6fffaf0f3477b0de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:56 -0600 Subject: board/trembyle/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e6eaaec86d33a45ce1655388620665a18b1e810 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729024 Reviewed-by: Jeremy Bettis --- board/trembyle/led.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/board/trembyle/led.c b/board/trembyle/led.c index 3e2d195a06..f639ba2b99 100644 --- a/board/trembyle/led.c +++ b/board/trembyle/led.c @@ -8,26 +8,34 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_RED, 2 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_RED, 2 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_RED, + 2 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_RED, + 2 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From cc7f87c3c324ce9e9c526141b78d6185f1947ab6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:09 -0600 Subject: board/waddledoo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7bf9182c6d6fab9b79df569e51b0340d0e7fc976 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729100 Reviewed-by: Jeremy Bettis --- board/waddledoo/board.c | 60 +++++++++++++++++++++---------------------------- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/board/waddledoo/board.c b/board/waddledoo/board.c index 3dcfc29bdc..4436c43be3 100644 --- a/board/waddledoo/board.c +++ b/board/waddledoo/board.c @@ -42,8 +42,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -83,7 +83,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -118,7 +117,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -173,16 +171,17 @@ void board_init(void) if (get_cbi_fw_config_db() == DB_1A_HDMI) { /* Disable i2c on HDMI pins */ - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0); - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, + 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, + 0); /* Set HDMI and sub-rail enables to output */ gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, chipset_in_state(CHIPSET_STATE_ON) ? - GPIO_ODR_LOW : GPIO_ODR_HIGH); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + GPIO_ODR_LOW : + GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -191,8 +190,7 @@ void board_init(void) gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL); } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT); /* Enable C1 interrupt and check if it needs processing */ gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL); @@ -256,7 +254,7 @@ static void reconfigure_5v_gpio(void) gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW); } } -DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1); #endif /* BOARD_WADDLEDOO */ static void set_5v_gpio(int level) @@ -297,10 +295,9 @@ __override void board_power_5v_enable(int enable) gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } else { if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", + enable ? "en" : "dis"); } - } __override uint8_t board_get_usb_pd_port_count(void) @@ -325,13 +322,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -395,8 +390,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -421,17 +416,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; @@ -507,9 +498,8 @@ struct motion_sensor_t motion_sensors[] = { const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -640,7 +630,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { + !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) -- cgit v1.2.1 From 1f5c4d1919a869d5ae09aba0b6c603f4479e7ae5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:48 -0600 Subject: driver/charger/bq257x0_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I920bd45f048b2372ddb4e36a7cd757ca648bd251 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729937 Reviewed-by: Jeremy Bettis --- driver/charger/bq257x0_regs.h | 322 +++++++++++++++++++++--------------------- 1 file changed, 160 insertions(+), 162 deletions(-) diff --git a/driver/charger/bq257x0_regs.h b/driver/charger/bq257x0_regs.h index fcec8f7469..d02a303653 100644 --- a/driver/charger/bq257x0_regs.h +++ b/driver/charger/bq257x0_regs.h @@ -21,221 +21,221 @@ /* * ChargerStatus Register (0x20) */ -#define BQ257X0_CHARGER_STATUS_ICO_DONE_SHIFT 14 -#define BQ257X0_CHARGER_STATUS_ICO_DONE_BITS 1 +#define BQ257X0_CHARGER_STATUS_ICO_DONE_SHIFT 14 +#define BQ257X0_CHARGER_STATUS_ICO_DONE_BITS 1 /* * ChargeOption0 Register (0x12) */ -#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_SHIFT 15 -#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_BITS 1 -#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_SHIFT 5 -#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_BITS 1 -#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_SHIFT 4 -#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_BITS 1 -#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_SHIFT 1 -#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_BITS 1 -#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_SHIFT 0 -#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_BITS 1 +#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_SHIFT 15 +#define BQ257X0_CHARGE_OPTION_0_EN_LWPWR_BITS 1 +#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_SHIFT 5 +#define BQ257X0_CHARGE_OPTION_0_EN_LEARN_BITS 1 +#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_SHIFT 4 +#define BQ257X0_CHARGE_OPTION_0_IADP_GAIN_BITS 1 +#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_SHIFT 1 +#define BQ257X0_CHARGE_OPTION_0_EN_IDPM_BITS 1 +#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_SHIFT 0 +#define BQ257X0_CHARGE_OPTION_0_CHRG_INHIBIT_BITS 1 /* * ChargeOption1 Register (0x30) */ -#define BQ25710_CHARGE_OPTION_1_EN_PSYS_SHIFT 12 -#define BQ25710_CHARGE_OPTION_1_EN_PSYS_BITS 1 +#define BQ25710_CHARGE_OPTION_1_EN_PSYS_SHIFT 12 +#define BQ25710_CHARGE_OPTION_1_EN_PSYS_BITS 1 -#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_SHIFT 12 -#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_BITS 2 -#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__PBUS_PBAT 0 -#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__OFF 3 +#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_SHIFT 12 +#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG_BITS 2 +#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__PBUS_PBAT 0 +#define BQ25720_CHARGE_OPTION_1_PSYS_CONFIG__OFF 3 -#define BQ257X0_CHARGE_OPTION_1_CMP_REF_SHIFT 7 -#define BQ257X0_CHARGE_OPTION_1_CMP_REF_BITS 1 -#define BQ257X0_CHARGE_OPTION_1_CMP_REF__2P3 0 -#define BQ257X0_CHARGE_OPTION_1_CMP_REF__1P2 1 +#define BQ257X0_CHARGE_OPTION_1_CMP_REF_SHIFT 7 +#define BQ257X0_CHARGE_OPTION_1_CMP_REF_BITS 1 +#define BQ257X0_CHARGE_OPTION_1_CMP_REF__2P3 0 +#define BQ257X0_CHARGE_OPTION_1_CMP_REF__1P2 1 -#define BQ257X0_CHARGE_OPTION_1_CMP_POL_SHIFT 6 -#define BQ257X0_CHARGE_OPTION_1_CMP_POL_BITS 1 -#define BQ257X0_CHARGE_OPTION_1_CMP_POL__INTERNAL 0 -#define BQ257X0_CHARGE_OPTION_1_CMP_POL__EXTERNAL 1 +#define BQ257X0_CHARGE_OPTION_1_CMP_POL_SHIFT 6 +#define BQ257X0_CHARGE_OPTION_1_CMP_POL_BITS 1 +#define BQ257X0_CHARGE_OPTION_1_CMP_POL__INTERNAL 0 +#define BQ257X0_CHARGE_OPTION_1_CMP_POL__EXTERNAL 1 /* * ChargeOption2 Register (0x31) */ -#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_SHIFT 14 -#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_BITS 2 -#define BQ25720_CHARGE_OPTION_2_PKPWR_TOVLD_DEG__10MS 3 +#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_SHIFT 14 +#define BQ257X0_CHARGE_OPTION_2_PKPWR_TOVLD_DEG_BITS 2 +#define BQ25720_CHARGE_OPTION_2_PKPWR_TOVLD_DEG__10MS 3 -#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_SHIFT 8 -#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_BITS 2 +#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_SHIFT 8 +#define BQ257X0_CHARGE_OPTION_2_PKPWR_TMAX_BITS 2 -#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_SHIFT 7 -#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_BITS 1 +#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_SHIFT 7 +#define BQ257X0_CHARGE_OPTION_2_EN_EXTILIM_BITS 1 -#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_SHIFT 3 -#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_BITS 1 -#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__DISABLE 0 -#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__ENABLE 1 +#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_SHIFT 3 +#define BQ257X0_CHARGE_OPTION_2_EN_ACOC_BITS 1 +#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__DISABLE 0 +#define BQ257X0_CHARGE_OPTION_2_EN_ACOC__ENABLE 1 -#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_SHIFT 2 -#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_BITS 1 -#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__1P33 0 -#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__2P00 1 +#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_SHIFT 2 +#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH_BITS 1 +#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__1P33 0 +#define BQ257X0_CHARGE_OPTION_2_ACOC_VTH__2P00 1 -#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_SHIFT 0 -#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_BITS 1 -#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__1P33 0 -#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__2P00 1 +#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_SHIFT 0 +#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH_BITS 1 +#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__1P33 0 +#define BQ257X0_CHARGE_OPTION_2_BATOC_VTH__2P00 1 /* * ChargeOption3 Register (0x32) */ -#define BQ257X0_CHARGE_OPTION_3_RESET_REG_SHIFT 14 -#define BQ257X0_CHARGE_OPTION_3_RESET_REG_BITS 1 +#define BQ257X0_CHARGE_OPTION_3_RESET_REG_SHIFT 14 +#define BQ257X0_CHARGE_OPTION_3_RESET_REG_BITS 1 -#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_SHIFT 11 -#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_BITS 1 +#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_SHIFT 11 +#define BQ257X0_CHARGE_OPTION_3_EN_ICO_MODE_BITS 1 -#define BQ257X0_CHARGE_OPTION_3_IL_AVG_SHIFT 3 -#define BQ257X0_CHARGE_OPTION_3_IL_AVG_BITS 2 -#define BQ257X0_CHARGE_OPTION_3_IL_AVG__10A 1 +#define BQ257X0_CHARGE_OPTION_3_IL_AVG_SHIFT 3 +#define BQ257X0_CHARGE_OPTION_3_IL_AVG_BITS 2 +#define BQ257X0_CHARGE_OPTION_3_IL_AVG__10A 1 /* * ChargeOption4 Register (0x36) */ -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_SHIFT 13 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_BITS 3 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__2P4 0 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__3P2 1 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P0 2 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P8 3 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 4 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__6P4 5 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__7P2 6 -#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__8P0 7 - -#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_SHIFT 6 -#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_BITS 2 -#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__1P6MS 1 -#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__12MS 3 - -#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_SHIFT 3 -#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_BITS 3 -#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P25 0 -#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P5 1 - -#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_SHIFT 2 -#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_BITS 1 -#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__DISABLE 0 -#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__ENABLE 1 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_SHIFT 13 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP_BITS 3 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__2P4 0 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__3P2 1 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P0 2 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__4P8 3 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__5P6 4 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__6P4 5 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__7P2 6 +#define BQ25720_CHARGE_OPTION_4_VSYS_UVP__8P0 7 + +#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_SHIFT 6 +#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2_BITS 2 +#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__1P6MS 1 +#define BQ25720_CHARGE_OPTION_4_IDCHG_DEG2__12MS 3 + +#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_SHIFT 3 +#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2_BITS 3 +#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P25 0 +#define BQ25720_CHARGE_OPTION_4_IDCHG_TH2__1P5 1 + +#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_SHIFT 2 +#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2_BITS 1 +#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__DISABLE 0 +#define BQ25720_CHARGE_OPTION_4_PP_IDCHG2__ENABLE 1 /* * Vmin Active Protection Register (0x37) */ -#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT 2 -#define BQ25720_VMIN_AP_VSYS_TH2_BITS 6 +#define BQ25720_VMIN_AP_VSYS_TH2_SHIFT 2 +#define BQ25720_VMIN_AP_VSYS_TH2_BITS 6 /* * ProchotOption0 Register (0x33) */ -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_SHIFT 11 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_BITS 5 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10 1 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40 7 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P50 9 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P30 25 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P50 26 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__4P50 30 -#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__NA 31 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_SHIFT 11 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH_BITS 5 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P10 1 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P40 7 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__1P50 9 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P30 25 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__2P50 26 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__4P50 30 +#define BQ257X0_PROCHOT_OPTION_0_ILIM2_VTH__NA 31 /* * ProchotOption1 Register (0x34) */ -#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_SHIFT 10 -#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_BITS 6 - -#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_SHIFT 6 -#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_SHIFT 4 -#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_SHIFT 3 -#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_SHIFT 7 -#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_SHIFT 2 -#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_SHIFT 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__ENABLE 1 - -#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_SHIFT 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_BITS 1 -#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__DISABLE 0 -#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__ENABLE 1 +#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_SHIFT 10 +#define BQ257X0_PROCHOT_OPTION_1_IDCHG_VTH_BITS 6 + +#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_SHIFT 6 +#define BQ257X0_PROCHOT_OPTION_1_PP_COMP_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_COMP__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_SHIFT 4 +#define BQ257X0_PROCHOT_OPTION_1_PP_INOM_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_INOM__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_SHIFT 3 +#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_IDCHG__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_SHIFT 7 +#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_VDPM__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_SHIFT 2 +#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_VSYS__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_SHIFT 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_BATPRES__ENABLE 1 + +#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_SHIFT 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK_BITS 1 +#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__DISABLE 0 +#define BQ257X0_PROCHOT_OPTION_1_PP_ACOK__ENABLE 1 /* * ChargeCurrent Register (0x14) */ -#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_SHIFT 6 -#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_BITS 7 +#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_SHIFT 6 +#define BQ257X0_CHARGE_CURRENT_CHARGE_CURRENT_BITS 7 /* * IIN_DPM Register (0x22) */ -#define BQ257X0_IIN_DPM_CURRENT_SHIFT 8 -#define BQ257X0_IIN_DPM_CURRENT_BITS 7 -#define BQ257X0_IIN_DPM_CURRENT_STEP_MA 50 +#define BQ257X0_IIN_DPM_CURRENT_SHIFT 8 +#define BQ257X0_IIN_DPM_CURRENT_BITS 7 +#define BQ257X0_IIN_DPM_CURRENT_STEP_MA 50 /* * IIN_HOST Register (0x3f) */ -#define BQ257X0_IIN_HOST_CURRENT_SHIFT 8 -#define BQ257X0_IIN_HOST_CURRENT_BITS 7 -#define BQ257X0_IIN_HOST_CURRENT_STEP_MA 50 +#define BQ257X0_IIN_HOST_CURRENT_SHIFT 8 +#define BQ257X0_IIN_HOST_CURRENT_BITS 7 +#define BQ257X0_IIN_HOST_CURRENT_STEP_MA 50 /* * ADCOption Register (0x35) */ -#define BQ257X0_ADC_OPTION_ADC_START_SHIFT 14 -#define BQ257X0_ADC_OPTION_ADC_START_BITS 1 -#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_SHIFT 13 -#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_BITS 1 +#define BQ257X0_ADC_OPTION_ADC_START_SHIFT 14 +#define BQ257X0_ADC_OPTION_ADC_START_BITS 1 +#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_SHIFT 13 +#define BQ257X0_ADC_OPTION_ADC_FULLSCALE_BITS 1 -#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_SHIFT 6 -#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_BITS 1 -#define BQ257X0_ADC_OPTION_EN_ADC_ALL GENMASK(7, 0) +#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_SHIFT 6 +#define BQ257X0_ADC_OPTION_EN_ADC_VBUS_BITS 1 +#define BQ257X0_ADC_OPTION_EN_ADC_ALL GENMASK(7, 0) /* * ADCVBUS/PSYS Register (0x23) */ -#define BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT 8 -#define BQ257X0_ADC_VBUS_PSYS_VBUS_BITS 8 -#define BQ257X0_ADC_VBUS_PSYS_PSYS_SHIFT 0 -#define BQ257X0_ADC_VBUS_PSYS_PSYS_BITS 8 +#define BQ257X0_ADC_VBUS_PSYS_VBUS_SHIFT 8 +#define BQ257X0_ADC_VBUS_PSYS_VBUS_BITS 8 +#define BQ257X0_ADC_VBUS_PSYS_PSYS_SHIFT 0 +#define BQ257X0_ADC_VBUS_PSYS_PSYS_BITS 8 /* * VSYS_MIN Register (0x3e) */ -#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT 8 -#define BQ25710_MIN_SYSTEM_VOLTAGE_BITS 6 -#define BQ25720_VSYS_MIN_VOLTAGE_SHIFT 8 -#define BQ25720_VSYS_MIN_VOLTAGE_BITS 8 +#define BQ25710_MIN_SYSTEM_VOLTAGE_SHIFT 8 +#define BQ25710_MIN_SYSTEM_VOLTAGE_BITS 6 +#define BQ25720_VSYS_MIN_VOLTAGE_SHIFT 8 +#define BQ25720_VSYS_MIN_VOLTAGE_BITS 8 /* * BQ257x0 register field accessor macros. @@ -249,10 +249,9 @@ * _field register field name */ -#define BQ_FIELD_MASK(_chip, _reg, _field) \ - GENMASK( \ - (_chip##_##_reg##_##_field##_SHIFT + \ - _chip##_##_reg##_##_field##_BITS - 1), \ +#define BQ_FIELD_MASK(_chip, _reg, _field) \ + GENMASK((_chip##_##_reg##_##_field##_SHIFT + \ + _chip##_##_reg##_##_field##_BITS - 1), \ _chip##_##_reg##_##_field##_SHIFT) /* @@ -264,8 +263,8 @@ * _x the value of the register to be examined */ -#define GET_BQ_FIELD(_chip, _reg, _field, _x) \ - (((_x) >> _chip##_##_reg##_##_field##_SHIFT) & \ +#define GET_BQ_FIELD(_chip, _reg, _field, _x) \ + (((_x) >> _chip##_##_reg##_##_field##_SHIFT) & \ GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) /* @@ -279,11 +278,10 @@ * _x the initial value of the register */ -#define SET_BQ_FIELD(_chip, _reg, _field, _v, _x) \ - (((_x) & ~BQ_FIELD_MASK(_chip, _reg, _field)) | \ - (((_v) & \ - GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) << \ - _chip##_##_reg##_##_field##_SHIFT)) +#define SET_BQ_FIELD(_chip, _reg, _field, _v, _x) \ + (((_x) & ~BQ_FIELD_MASK(_chip, _reg, _field)) | \ + (((_v)&GENMASK(_chip##_##_reg##_##_field##_BITS - 1, 0)) \ + << _chip##_##_reg##_##_field##_SHIFT)) /* * Given a register value, sets the specified field to the predefined @@ -296,8 +294,8 @@ * _x the initial value of the register */ -#define SET_BQ_FIELD_BY_NAME(_chip, _reg, _field, _c, _x) \ - SET_BQ_FIELD(_chip, _reg, _field, \ - _chip##_##_reg##_##_field##__##_c, (_x)) +#define SET_BQ_FIELD_BY_NAME(_chip, _reg, _field, _c, _x) \ + SET_BQ_FIELD(_chip, _reg, _field, _chip##_##_reg##_##_field##__##_c, \ + (_x)) #endif /* __CROS_EC_BQ257X0_REGS_H */ -- cgit v1.2.1 From e8a5ca6aac80ec5bc1b75a165ff4cb87a218fbf6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:07 -0600 Subject: board/taeko/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8ab66cb1e86981de2c919f4089d4b1b84017bc67 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728978 Reviewed-by: Jeremy Bettis --- board/taeko/board.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/taeko/board.c b/board/taeko/board.c index f4f29e1199..2e4627c3bf 100644 --- a/board/taeko/board.c +++ b/board/taeko/board.c @@ -35,8 +35,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -121,8 +121,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -138,7 +138,7 @@ enum battery_present battery_hw_present(void) } __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Follow OEM request to limit the input current to @@ -146,7 +146,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From fb1ffa3fa07f429aa4e7d4976e9b4b261bb0866e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:37 -0600 Subject: chip/stm32/dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a20562243ebda1fcf5d5792283fbe8b060bf56a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729493 Reviewed-by: Jeremy Bettis --- chip/stm32/dma.c | 63 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 31 insertions(+), 32 deletions(-) diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index 940d950dff..e2804ed41d 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -15,15 +15,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args) /* Callback data to use when IRQ fires */ static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ + void (*cb)(void *); /* Callback function to call */ + void *cb_data; /* Callback data for callback function */ } dma_irq[STM32_DMAC_COUNT]; - /** * Return the IRQ for the DMA channel * @@ -36,9 +35,8 @@ static int dma_get_irq(enum dma_channel channel) if (channel == STM32_DMAC_CH1) return STM32_IRQ_DMA_CHANNEL_1; - return channel > STM32_DMAC_CH3 ? - STM32_IRQ_DMA_CHANNEL_4_7 : - STM32_IRQ_DMA_CHANNEL_2_3; + return channel > STM32_DMAC_CH3 ? STM32_IRQ_DMA_CHANNEL_4_7 : + STM32_IRQ_DMA_CHANNEL_2_3; #elif defined(CHIP_FAMILY_STM32L4) if (channel < STM32_DMAC_PER_CTLR) return STM32_IRQ_DMA_CHANNEL_1 + channel; @@ -55,7 +53,7 @@ static int dma_get_irq(enum dma_channel channel) return STM32_IRQ_DMA_CHANNEL_1 + channel; else return STM32_IRQ_DMA2_CHANNEL1 + - (channel - STM32_DMAC_PER_CTLR); + (channel - STM32_DMAC_PER_CTLR); #endif } @@ -127,7 +125,7 @@ void dma_disable_all(void) * 0 for rx */ static void prepare_channel(enum dma_channel channel, unsigned int count, - void *periph, void *memory, unsigned int flags) + void *periph, void *memory, unsigned int flags) { stm32_dma_chan_t *chan = dma_get_channel(channel); uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; @@ -161,8 +159,7 @@ void dma_prepare_tx(const struct dma_option *option, unsigned int count, * we're preparing the channel for transmit. */ prepare_channel(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR | option->flags); } void dma_start_rx(const struct dma_option *option, unsigned int count, @@ -191,10 +188,9 @@ void dma_dump(enum dma_channel channel) stm32_dma_regs_t *dma = STM32_DMA_REGS(channel); stm32_dma_chan_t *chan = dma_get_channel(channel); - CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, - chan->cndtr, chan->cpar, chan->cmar); - CPRINTF("chan %d, isr=%x, ifcr=%x\n", - channel, + CPRINTF("ccr=%x, cndtr=%x, cpar=%x, cmar=%x\n", chan->ccr, chan->cndtr, + chan->cpar, chan->cmar); + CPRINTF("chan %d, isr=%x, ifcr=%x\n", channel, (dma->isr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf, (dma->ifcr >> ((channel % STM32_DMAC_PER_CTLR) * 4)) & 0xf); } @@ -238,11 +234,12 @@ void dma_test(enum dma_channel channel) ctrl = STM32_DMA_CCR_PL_MEDIUM; chan->ccr = ctrl; - ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */; + ctrl |= STM32_DMA_CCR_MINC; /* | STM32_DMA_CCR_DIR */ + ; ctrl |= STM32_DMA_CCR_MEM2MEM; ctrl |= STM32_DMA_CCR_PINC; -/* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ -/* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ + /* ctrl |= STM32_DMA_CCR_MSIZE_32_BIT; */ + /* ctrl |= STM32_DMA_CCR_PSIZE_32_BIT; */ chan->ccr = ctrl; chan->ccr = ctrl | STM32_DMA_CCR_EN; @@ -255,10 +252,12 @@ void dma_test(enum dma_channel channel) void dma_init(void) { #if defined(CHIP_FAMILY_STM32L4) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN; + STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN | + STM32_RCC_AHB1ENR_DMA2EN; #elif defined(CHIP_FAMILY_STM32G4) || defined(CHIP_FAMILY_STM32L5) - STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN|STM32_RCC_AHB1ENR_DMA2EN | - STM32_RCC_AHB1ENR_DMAMUXEN; + STM32_RCC_AHB1ENR |= STM32_RCC_AHB1ENR_DMA1EN | + STM32_RCC_AHB1ENR_DMA2EN | + STM32_RCC_AHB1ENR_DMAMUXEN; #else STM32_RCC_AHBENR |= STM32_RCC_HB_DMA1; #endif @@ -337,8 +336,8 @@ static void dma_event_interrupt_channel_1(void) if (STM32_DMA1_REGS->isr & STM32_DMA_ISR_TCIF(STM32_DMAC_CH1)) { dma_clear_isr(STM32_DMAC_CH1); if (dma_irq[STM32_DMAC_CH1].cb != NULL) - (*dma_irq[STM32_DMAC_CH1].cb) - (dma_irq[STM32_DMAC_CH1].cb_data); + (*dma_irq[STM32_DMAC_CH1].cb)( + dma_irq[STM32_DMAC_CH1].cb_data); } } DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_1, dma_event_interrupt_channel_1, 1); @@ -374,15 +373,15 @@ DECLARE_IRQ(STM32_IRQ_DMA_CHANNEL_4_7, dma_event_interrupt_channel_4_7, 1); #else /* !CHIP_FAMILY_STM32F0 */ -#define DECLARE_DMA_IRQ(x) \ - static void CONCAT2(dma_event_interrupt_channel_, x)(void) \ - { \ - dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ - if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ - (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb) \ - (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ +#define DECLARE_DMA_IRQ(x) \ + static void CONCAT2(dma_event_interrupt_channel_, x)(void) \ + { \ + dma_clear_isr(CONCAT2(STM32_DMAC_CH, x)); \ + if (dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb != NULL) \ + (*dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb)( \ + dma_irq[CONCAT2(STM32_DMAC_CH, x)].cb_data); \ + } \ + DECLARE_IRQ(CONCAT2(STM32_IRQ_DMA_CHANNEL_, x), \ CONCAT2(dma_event_interrupt_channel_, x), 1) DECLARE_DMA_IRQ(1); -- cgit v1.2.1 From e5e78b3361605d1cc556cbba2b5807c46149a787 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:07 -0600 Subject: board/nucleo-g431rb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61d9ade06b3a967beef7094abb4c8f0616a72a1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728782 Reviewed-by: Jeremy Bettis --- board/nucleo-g431rb/board.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/board/nucleo-g431rb/board.h b/board/nucleo-g431rb/board.h index a65daa4364..908c1c49d6 100644 --- a/board/nucleo-g431rb/board.h +++ b/board/nucleo-g431rb/board.h @@ -14,14 +14,13 @@ #define CPU_CLOCK 48000000 #define CONFIG_STM_HWTIMER32 #define TIM_CLOCK32 2 -#define TIM_CLOCK_MSB 3 +#define TIM_CLOCK_MSB 3 #define TIM_CLOCK_LSB 15 #define TIM_WATCHDOG 7 /* Nucelo platform does not have a lid switch */ #undef CONFIG_LID_SWITCH - /* Setup UART console */ /* * The STM32G431 Nucleo-64 has two UARTs which can be connected to the virtual @@ -49,24 +48,20 @@ #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART1_TX #endif - /* * Macros for GPIO signals used in common code that don't match the * schematic names. Signal names in gpio.inc match the schematic and are * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_WP_L GPIO_EC_WP_L - - +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_WP_L #ifndef __ASSEMBLER__ #include "gpio_signal.h" #include "registers.h" - #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From f21b984b349e1e54f410b17e29dd2970edd99969 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:53 -0600 Subject: core/riscv-rv32i/math.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4868de12dfd49a068733451d00143c6b6f8f7616 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729872 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/math.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c index 591a67eb8f..6630f36ba2 100644 --- a/core/riscv-rv32i/math.c +++ b/core/riscv-rv32i/math.c @@ -9,10 +9,7 @@ /* Single precision floating point square root. */ float sqrtf(float x) { - asm volatile ( - "fsqrt.s %0, %1" - : "=f" (x) - : "f" (x)); + asm volatile("fsqrt.s %0, %1" : "=f"(x) : "f"(x)); return x; } -- cgit v1.2.1 From a7defa46c84d943619e162492000e0d1d6f2dd8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:30 -0600 Subject: common/i2c_controller.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If5e06173f4ecf16976b55f604b237223ebcbe1c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729635 Reviewed-by: Jeremy Bettis --- common/i2c_controller.c | 448 ++++++++++++++++++++---------------------------- 1 file changed, 186 insertions(+), 262 deletions(-) diff --git a/common/i2c_controller.c b/common/i2c_controller.c index 7a0550a93e..ea85f80a14 100644 --- a/common/i2c_controller.c +++ b/common/i2c_controller.c @@ -29,15 +29,15 @@ #endif /* CONFIG_ZEPHYR */ /* Delay for bitbanging i2c corresponds roughly to 100kHz. */ -#define I2C_BITBANG_DELAY_US 5 +#define I2C_BITBANG_DELAY_US 5 /* Number of attempts to unwedge each pin. */ -#define UNWEDGE_SCL_ATTEMPTS 10 -#define UNWEDGE_SDA_ATTEMPTS 3 +#define UNWEDGE_SCL_ATTEMPTS 10 +#define UNWEDGE_SDA_ATTEMPTS 3 #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /* Only chips with multi-port controllers will define I2C_CONTROLLER_COUNT */ #ifndef I2C_CONTROLLER_COUNT @@ -134,10 +134,11 @@ const struct i2c_port_t *get_i2c_port(const int port) return NULL; } -__maybe_unused static int chip_i2c_xfer_with_notify( - const int port, const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +__maybe_unused static int chip_i2c_xfer_with_notify(const int port, + const uint16_t addr_flags, + const uint8_t *out, + int out_size, uint8_t *in, + int in_size, int flags) { int ret; uint16_t no_pec_af = addr_flags; @@ -157,18 +158,18 @@ __maybe_unused static int chip_i2c_xfer_with_notify( no_pec_af &= ~I2C_FLAG_PEC; if (i2c_port->drv) - ret = i2c_port->drv->xfer(i2c_port, no_pec_af, - out, out_size, in, in_size, flags); + ret = i2c_port->drv->xfer(i2c_port, no_pec_af, out, out_size, + in, in_size, flags); else - ret = chip_i2c_xfer(port, no_pec_af, - out, out_size, in, in_size, flags); + ret = chip_i2c_xfer(port, no_pec_af, out, out_size, in, in_size, + flags); if (IS_ENABLED(CONFIG_I2C_XFER_BOARD_CALLBACK)) i2c_end_xfer_notify(port, addr_flags); if (IS_ENABLED(CONFIG_I2C_DEBUG)) { - i2c_trace_notify(port, addr_flags, out, out_size, - in, in_size, ret); + i2c_trace_notify(port, addr_flags, out, out_size, in, in_size, + ret); } return ret; @@ -179,16 +180,15 @@ __maybe_unused static int chip_i2c_xfer_with_notify( * Internal function that splits transfer into multiple chip_i2c_xfer() calls * if in_size or out_size exceeds CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE. */ -static int i2c_xfer_no_retry(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +static int i2c_xfer_no_retry(const int port, const uint16_t addr_flags, + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags) { int offset; - for (offset = 0; offset < out_size; ) { + for (offset = 0; offset < out_size;) { int chunk_size = MIN(out_size - offset, - CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE); + CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE); int out_flags = 0; if (offset == 0) @@ -197,13 +197,13 @@ static int i2c_xfer_no_retry(const int port, out_flags |= flags & I2C_XFER_STOP; RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags, - out + offset, chunk_size, NULL, 0, - out_flags)); + out + offset, chunk_size, + NULL, 0, out_flags)); offset += chunk_size; } - for (offset = 0; offset < in_size; ) { + for (offset = 0; offset < in_size;) { int chunk_size = MIN(in_size - offset, - CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE); + CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE); int in_flags = 0; if (offset == 0) @@ -211,18 +211,18 @@ static int i2c_xfer_no_retry(const int port, if (offset + chunk_size == in_size) in_flags |= flags & I2C_XFER_STOP; - RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags, - NULL, 0, in + offset, chunk_size, in_flags)); + RETURN_ERROR(chip_i2c_xfer_with_notify(port, addr_flags, NULL, + 0, in + offset, + chunk_size, in_flags)); offset += chunk_size; } return EC_SUCCESS; } #endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */ -int i2c_xfer_unlocked(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int i2c_xfer_unlocked(const int port, const uint16_t addr_flags, + const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags) { int i; int ret = EC_SUCCESS; @@ -275,14 +275,14 @@ int i2c_xfer_unlocked(const int port, /* Big endian flag is used in wrappers for this call */ if (no_pec_af & ~(I2C_ADDR_MASK | I2C_FLAG_BIG_ENDIAN)) ccprintf("Ignoring flags from i2c addr_flags: %04x", - no_pec_af); + no_pec_af); - ret = i2c_transfer(i2c_get_device_for_port(port), msg, - num_msgs, I2C_STRIP_FLAGS(no_pec_af)); + ret = i2c_transfer(i2c_get_device_for_port(port), msg, num_msgs, + I2C_STRIP_FLAGS(no_pec_af)); if (IS_ENABLED(CONFIG_I2C_DEBUG)) { - i2c_trace_notify(port, addr_flags, out, out_size, - in, in_size, ret); + i2c_trace_notify(port, addr_flags, out, out_size, in, + in_size, ret); } switch (ret) { @@ -294,13 +294,11 @@ int i2c_xfer_unlocked(const int port, return EC_ERROR_UNKNOWN; } #elif defined(CONFIG_I2C_XFER_LARGE_TRANSFER) - ret = i2c_xfer_no_retry(port, no_pec_af, - out, out_size, in, - in_size, flags); + ret = i2c_xfer_no_retry(port, no_pec_af, out, out_size, in, + in_size, flags); #else - ret = chip_i2c_xfer_with_notify(port, no_pec_af, - out, out_size, - in, in_size, flags); + ret = chip_i2c_xfer_with_notify(port, no_pec_af, out, out_size, + in, in_size, flags); #endif /* CONFIG_I2C_XFER_LARGE_TRANSFER */ if (ret != EC_ERROR_BUSY) break; @@ -308,16 +306,13 @@ int i2c_xfer_unlocked(const int port, return ret; } -int i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size) +int i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size) { int rv; i2c_lock(port, 1); - rv = i2c_xfer_unlocked(port, addr_flags, - out, out_size, in, in_size, + rv = i2c_xfer_unlocked(port, addr_flags, out, out_size, in, in_size, I2C_XFER_SINGLE); i2c_lock(port, 0); @@ -390,13 +385,13 @@ static int platform_ec_i2c_read(const int port, const uint16_t addr_flags, int i, rv; /* addr_8bit = 7 bit addr_flags + 1 bit r/w */ uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; - uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1}; + uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 }; uint8_t pec_local = 0, pec_remote; i2c_lock(port, 1); for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) { - rv = i2c_xfer_unlocked(port, addr_flags, ®, 1, - in, in_size, I2C_XFER_START); + rv = i2c_xfer_unlocked(port, addr_flags, ®, 1, in, + in_size, I2C_XFER_START); if (rv) continue; @@ -421,8 +416,7 @@ static int platform_ec_i2c_read(const int port, const uint16_t addr_flags, } /* i2c_writeN with optional error checking */ -static int platform_ec_i2c_write(const int port, - const uint16_t addr_flags, +static int platform_ec_i2c_write(const int port, const uint16_t addr_flags, const uint8_t *out, int out_size) { if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) @@ -438,15 +432,13 @@ static int platform_ec_i2c_write(const int port, i2c_lock(port, 1); for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) { - rv = i2c_xfer_unlocked(port, addr_flags, - out, out_size, NULL, 0, - I2C_XFER_START); + rv = i2c_xfer_unlocked(port, addr_flags, out, out_size, + NULL, 0, I2C_XFER_START); if (rv) continue; - rv = i2c_xfer_unlocked(port, addr_flags, - &pec, 1, NULL, 0, - I2C_XFER_STOP); + rv = i2c_xfer_unlocked(port, addr_flags, &pec, 1, NULL, + 0, I2C_XFER_STOP); if (!rv) break; } @@ -458,17 +450,14 @@ static int platform_ec_i2c_write(const int port, return i2c_xfer(port, addr_flags, out, out_size, NULL, 0); } -int i2c_read32(const int port, - const uint16_t addr_flags, - int offset, int *data) +int i2c_read32(const int port, const uint16_t addr_flags, int offset, int *data) { int rv; uint8_t reg, buf[sizeof(uint32_t)]; reg = offset & 0xff; /* I2C read 32-bit word: transmit 8-bit offset, and read 32bits */ - rv = platform_ec_i2c_read(port, addr_flags, reg, buf, - sizeof(uint32_t)); + rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint32_t)); if (rv) return rv; @@ -483,9 +472,7 @@ int i2c_read32(const int port, return EC_SUCCESS; } -int i2c_write32(const int port, - const uint16_t addr_flags, - int offset, int data) +int i2c_write32(const int port, const uint16_t addr_flags, int offset, int data) { uint8_t buf[1 + sizeof(uint32_t)]; @@ -507,17 +494,14 @@ int i2c_write32(const int port, sizeof(uint32_t) + 1); } -int i2c_read16(const int port, - const uint16_t addr_flags, - int offset, int *data) +int i2c_read16(const int port, const uint16_t addr_flags, int offset, int *data) { int rv; uint8_t reg, buf[sizeof(uint16_t)]; reg = offset & 0xff; /* I2C read 16-bit word: transmit 8-bit offset, and read 16bits */ - rv = platform_ec_i2c_read(port, addr_flags, reg, buf, - sizeof(uint16_t)); + rv = platform_ec_i2c_read(port, addr_flags, reg, buf, sizeof(uint16_t)); if (rv) return rv; @@ -530,9 +514,7 @@ int i2c_read16(const int port, return EC_SUCCESS; } -int i2c_write16(const int port, - const uint16_t addr_flags, - int offset, int data) +int i2c_write16(const int port, const uint16_t addr_flags, int offset, int data) { uint8_t buf[1 + sizeof(uint16_t)]; @@ -550,9 +532,7 @@ int i2c_write16(const int port, 1 + sizeof(uint16_t)); } -int i2c_read8(const int port, - const uint16_t addr_flags, - int offset, int *data) +int i2c_read8(const int port, const uint16_t addr_flags, int offset, int *data) { int rv; uint8_t reg = offset; @@ -560,17 +540,14 @@ int i2c_read8(const int port, reg = offset; - rv = platform_ec_i2c_read(port, addr_flags, reg, &buf, - sizeof(uint8_t)); + rv = platform_ec_i2c_read(port, addr_flags, reg, &buf, sizeof(uint8_t)); if (!rv) *data = buf; return rv; } -int i2c_write8(const int port, - const uint16_t addr_flags, - int offset, int data) +int i2c_write8(const int port, const uint16_t addr_flags, int offset, int data) { uint8_t buf[2]; @@ -580,11 +557,8 @@ int i2c_write8(const int port, return platform_ec_i2c_write(port, addr_flags, buf, sizeof(buf)); } -int i2c_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t mask, - const enum mask_update_action action) +int i2c_update8(const int port, const uint16_t addr_flags, const int offset, + const uint8_t mask, const enum mask_update_action action) { int rv; int read_val; @@ -594,8 +568,8 @@ int i2c_update8(const int port, if (rv) return rv; - write_val = (action == MASK_SET) ? (read_val | mask) - : (read_val & ~mask); + write_val = (action == MASK_SET) ? (read_val | mask) : + (read_val & ~mask); if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val) return EC_SUCCESS; @@ -603,11 +577,8 @@ int i2c_update8(const int port, return i2c_write8(port, addr_flags, offset, write_val); } -int i2c_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t mask, - const enum mask_update_action action) +int i2c_update16(const int port, const uint16_t addr_flags, const int offset, + const uint16_t mask, const enum mask_update_action action) { int rv; int read_val; @@ -617,8 +588,8 @@ int i2c_update16(const int port, if (rv) return rv; - write_val = (action == MASK_SET) ? (read_val | mask) - : (read_val & ~mask); + write_val = (action == MASK_SET) ? (read_val | mask) : + (read_val & ~mask); if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val) return EC_SUCCESS; @@ -626,10 +597,8 @@ int i2c_update16(const int port, return i2c_write16(port, addr_flags, offset, write_val); } -int i2c_field_update8(const int port, - const uint16_t addr_flags, - const int offset, - const uint8_t field_mask, +int i2c_field_update8(const int port, const uint16_t addr_flags, + const int offset, const uint8_t field_mask, const uint8_t set_value) { int rv; @@ -648,10 +617,8 @@ int i2c_field_update8(const int port, return i2c_write8(port, addr_flags, offset, write_val); } -int i2c_field_update16(const int port, - const uint16_t addr_flags, - const int offset, - const uint16_t field_mask, +int i2c_field_update16(const int port, const uint16_t addr_flags, + const int offset, const uint16_t field_mask, const uint16_t set_value) { int rv; @@ -670,8 +637,7 @@ int i2c_field_update16(const int port, return i2c_write16(port, addr_flags, offset, write_val); } -int i2c_read_offset16(const int port, - const uint16_t addr_flags, +int i2c_read_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int *data, int len) { int rv; @@ -701,8 +667,7 @@ int i2c_read_offset16(const int port, return EC_SUCCESS; } -int i2c_write_offset16(const int port, - const uint16_t addr_flags, +int i2c_write_offset16(const int port, const uint16_t addr_flags, uint16_t offset, int data, int len) { uint8_t buf[2 + sizeof(uint16_t)]; @@ -728,8 +693,7 @@ int i2c_write_offset16(const int port, return i2c_xfer(port, addr_flags, buf, 2 + len, NULL, 0); } -int i2c_read_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_read_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, uint8_t *data, int len) { uint8_t addr[sizeof(uint16_t)]; @@ -740,8 +704,7 @@ int i2c_read_offset16_block(const int port, return i2c_xfer(port, addr_flags, addr, 2, data, len); } -int i2c_write_offset16_block(const int port, - const uint16_t addr_flags, +int i2c_write_offset16_block(const int port, const uint16_t addr_flags, uint16_t offset, const uint8_t *data, int len) { int rv; @@ -758,16 +721,15 @@ int i2c_write_offset16_block(const int port, rv = i2c_xfer_unlocked(port, addr_flags, addr, 2, NULL, 0, I2C_XFER_START); if (!rv) - rv = i2c_xfer_unlocked(port, addr_flags, - data, len, NULL, 0, I2C_XFER_STOP); + rv = i2c_xfer_unlocked(port, addr_flags, data, len, NULL, 0, + I2C_XFER_STOP); i2c_lock(port, 0); return rv; } -int i2c_read_sized_block(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int max_len, int *read_len) +int i2c_read_sized_block(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int max_len, int *read_len) { int i, rv; uint8_t reg, block_length; @@ -788,9 +750,8 @@ int i2c_read_sized_block(const int port, * Send device reg space offset, and read back block length. * Keep this session open without a stop. */ - rv = i2c_xfer_unlocked(port, addr_flags, - ®, 1, &block_length, 1, - I2C_XFER_START); + rv = i2c_xfer_unlocked(port, addr_flags, ®, 1, &block_length, + 1, I2C_XFER_START); if (rv) continue; @@ -799,15 +760,13 @@ int i2c_read_sized_block(const int port, else data_length = block_length; - if (IS_ENABLED(CONFIG_SMBUS_PEC) && - I2C_USE_PEC(addr_flags)) { - uint8_t addr_8bit = - I2C_STRIP_FLAGS(addr_flags) << 1; - uint8_t out[3] = {addr_8bit, reg, addr_8bit | 1}; + if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(addr_flags)) { + uint8_t addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; + uint8_t out[3] = { addr_8bit, reg, addr_8bit | 1 }; uint8_t pec, pec_remote; - rv = i2c_xfer_unlocked(port, addr_flags, - 0, 0, data, data_length, 0); + rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data, + data_length, 0); if (rv) continue; @@ -820,8 +779,8 @@ int i2c_read_sized_block(const int port, while (block_length) { uint8_t byte; - rv = i2c_xfer_unlocked(port, addr_flags, - NULL, 0, &byte, 1, 0); + rv = i2c_xfer_unlocked(port, addr_flags, NULL, + 0, &byte, 1, 0); if (rv) break; pec = cros_crc8_arg(&byte, 1, pec); @@ -838,9 +797,8 @@ int i2c_read_sized_block(const int port, if (pec != pec_remote) rv = EC_ERROR_CRC; } else { - rv = i2c_xfer_unlocked(port, addr_flags, - 0, 0, data, data_length, - I2C_XFER_STOP); + rv = i2c_xfer_unlocked(port, addr_flags, 0, 0, data, + data_length, I2C_XFER_STOP); if (rv) continue; } @@ -854,9 +812,8 @@ int i2c_read_sized_block(const int port, return rv; } -int i2c_read_string(const int port, - const uint16_t addr_flags, - int offset, uint8_t *data, int len) +int i2c_read_string(const int port, const uint16_t addr_flags, int offset, + uint8_t *data, int len) { int read_len = 0; int rv = 0; @@ -865,7 +822,7 @@ int i2c_read_string(const int port, return EC_ERROR_INVAL; rv = i2c_read_sized_block(port, addr_flags, offset, data, len - 1, - &read_len); + &read_len); data[read_len] = 0; return rv; } @@ -880,9 +837,8 @@ int i2c_read_block(const int port, const uint16_t addr_flags, int offset, return rv; } -int i2c_write_block(const int port, - const uint16_t addr_flags, - int offset, const uint8_t *data, int len) +int i2c_write_block(const int port, const uint16_t addr_flags, int offset, + const uint8_t *data, int len) { int i, rv; uint8_t reg_address = offset, pec = 0; @@ -903,27 +859,25 @@ int i2c_write_block(const int port, */ i2c_lock(port, 1); for (i = 0; i <= CONFIG_I2C_NACK_RETRY_COUNT; i++) { - rv = i2c_xfer_unlocked(port, addr_flags, - ®_address, 1, NULL, 0, - I2C_XFER_START); + rv = i2c_xfer_unlocked(port, addr_flags, ®_address, 1, NULL, + 0, I2C_XFER_START); if (rv) continue; if (I2C_USE_PEC(addr_flags)) { - rv = i2c_xfer_unlocked(port, addr_flags, - data, len, NULL, 0, 0); + rv = i2c_xfer_unlocked(port, addr_flags, data, len, + NULL, 0, 0); if (rv) continue; - rv = i2c_xfer_unlocked(port, addr_flags, - &pec, sizeof(uint8_t), NULL, 0, + rv = i2c_xfer_unlocked(port, addr_flags, &pec, + sizeof(uint8_t), NULL, 0, I2C_XFER_STOP); if (rv) continue; } else { - rv = i2c_xfer_unlocked(port, addr_flags, - data, len, NULL, 0, - I2C_XFER_STOP); + rv = i2c_xfer_unlocked(port, addr_flags, data, len, + NULL, 0, I2C_XFER_STOP); if (rv) continue; } @@ -1022,7 +976,6 @@ int i2c_raw_mode(int port, int enable) return ret_sda == EC_SUCCESS ? ret_scl : ret_sda; } - /* * Unwedge the i2c bus for the given port. * @@ -1083,7 +1036,8 @@ int i2c_unwedge(int port) * clock low and there is nothing we can do. */ CPRINTS("I2C%d unwedge failed, " - "SCL is held low", port); + "SCL is held low", + port); ret = EC_ERROR_UNKNOWN; goto unwedge_done; } @@ -1202,8 +1156,8 @@ enum i2c_freq i2c_get_freq(int port) /* Host commands */ #ifdef CONFIG_I2C_DEBUG_PASSTHRU -#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ## args) -#define PTHRUPRINTF(format, args...) CPRINTF(format, ## args) +#define PTHRUPRINTS(format, args...) CPRINTS("I2C_PTHRU " format, ##args) +#define PTHRUPRINTF(format, args...) CPRINTF(format, ##args) #else #define PTHRUPRINTS(format, args...) #define PTHRUPRINTF(format, args...) @@ -1241,7 +1195,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args) } #ifdef CONFIG_I2C_PASSTHRU_RESTRICTED - out = (uint8_t *) args->params + size; + out = (uint8_t *)args->params + size; #endif /* Loop and process messages */; @@ -1252,8 +1206,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args) PTHRUPRINTS("port=%d, %s, addr=0x%x(7-bit), len=%d", params->port, addr_flags & EC_I2C_FLAG_READ ? "read" : "write", - addr_flags & EC_I2C_ADDR_MASK, - msg->len); + addr_flags & EC_I2C_ADDR_MASK, msg->len); if (addr_flags & EC_I2C_FLAG_READ) { read_len += msg->len; @@ -1270,8 +1223,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args) .addr_flags = addr_flags, .cmd = cmd_id, }; - if (!board_allow_i2c_passthru( - &cmd_desc)) + if (!board_allow_i2c_passthru(&cmd_desc)) return EC_RES_ACCESS_DENIED; } #endif @@ -1279,7 +1231,7 @@ static int check_i2c_params(const struct host_cmd_handler_args *args) /* Check there is room for the data */ if (args->response_max < - sizeof(struct ec_response_i2c_passthru) + read_len) { + sizeof(struct ec_response_i2c_passthru) + read_len) { PTHRUPRINTS("overflow1"); return EC_RES_INVALID_PARAM; } @@ -1316,8 +1268,7 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) */ ((struct ec_params_i2c_passthru *)(args->params))->port = i2c_get_port_from_remote_port( - ((struct ec_params_i2c_passthru *)(args->params)) - ->port); + ((struct ec_params_i2c_passthru *)(args->params))->port); #endif const struct ec_params_i2c_passthru *params = args->params; const struct ec_params_i2c_passthru_msg *msg; @@ -1349,8 +1300,8 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) return EC_RES_ACCESS_DENIED; for (i = 0; i < params->num_msgs; i++) { - if (!i2c_port->passthru_allowed(i2c_port, - params->msg[i].addr_flags)) + if (!i2c_port->passthru_allowed( + i2c_port, params->msg[i].addr_flags)) return EC_RES_ACCESS_DENIED; } } @@ -1358,12 +1309,11 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) /* Loop and process messages */ resp->i2c_status = 0; out = (uint8_t *)args->params + sizeof(*params) + - params->num_msgs * sizeof(*msg); + params->num_msgs * sizeof(*msg); in_len = 0; for (resp->num_msgs = 0, msg = params->msg; - resp->num_msgs < params->num_msgs; - resp->num_msgs++, msg++) { + resp->num_msgs < params->num_msgs; resp->num_msgs++, msg++) { int xferflags = I2C_XFER_START; int read_len = 0, write_len = 0; int rv = 1; @@ -1371,7 +1321,6 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) /* Have to remove the EC flags from the address flags */ uint16_t addr_flags = msg->addr_flags & EC_I2C_ADDR_MASK; - if (msg->addr_flags & EC_I2C_FLAG_READ) read_len = msg->len; else @@ -1385,15 +1334,14 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) if (is_i2c_port_virtual_battery(params->port) && addr_flags == VIRTUAL_BATTERY_ADDR_FLAGS) { if (virtual_battery_handler(resp, in_len, &rv, - xferflags, read_len, - write_len, out)) + xferflags, read_len, + write_len, out)) break; } #endif /* Transfer next message */ PTHRUPRINTS("xfer port=%x addr=0x%x rlen=%d flags=0x%x", - params->port, addr_flags, - read_len, xferflags); + params->port, addr_flags, read_len, xferflags); if (write_len) { PTHRUPRINTF(" out:"); for (i = 0; i < write_len; i++) @@ -1403,11 +1351,9 @@ static enum ec_status i2c_command_passthru(struct host_cmd_handler_args *args) if (rv) { if (!port_is_locked) i2c_lock(params->port, (port_is_locked = 1)); - rv = i2c_xfer_unlocked(params->port, - addr_flags, - out, write_len, - &resp->data[in_len], read_len, - xferflags); + rv = i2c_xfer_unlocked(params->port, addr_flags, out, + write_len, &resp->data[in_len], + read_len, xferflags); } if (rv) { @@ -1476,8 +1422,7 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args) */ ((struct ec_params_i2c_passthru_protect *)(args->params)) ->port = i2c_get_port_from_remote_port( - ((struct ec_params_i2c_passthru_protect *)(args->params)) - ->port); + ((struct ec_params_i2c_passthru_protect *)(args->params))->port); #endif const struct ec_params_i2c_passthru_protect *params = args->params; struct ec_response_i2c_passthru_protect *resp = args->response; @@ -1495,7 +1440,7 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args) */ if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE_TCPCS) { if (IS_ENABLED(CONFIG_USB_POWER_DELIVERY) && - !IS_ENABLED(CONFIG_USB_PD_TCPM_STUB)) + !IS_ENABLED(CONFIG_USB_PD_TCPM_STUB)) i2c_passthru_protect_tcpc_ports(); return EC_RES_SUCCESS; } @@ -1508,8 +1453,8 @@ i2c_command_passthru_protect(struct host_cmd_handler_args *args) if (params->subcmd == EC_CMD_I2C_PASSTHRU_PROTECT_STATUS) { if (args->response_max < sizeof(*resp)) { PTHRUPRINTS("protect no response, " - "response_max=%d, need at least %d", - args->response_max, sizeof(*resp)); + "response_max=%d, need at least %d", + args->response_max, sizeof(*resp)); return EC_RES_INVALID_PARAM; } @@ -1528,8 +1473,7 @@ DECLARE_HOST_COMMAND(EC_CMD_I2C_PASSTHRU_PROTECT, i2c_command_passthru_protect, #ifdef CONFIG_HOSTCMD_I2C_CONTROL -static enum ec_status -i2c_command_control(struct host_cmd_handler_args *args) +static enum ec_status i2c_command_control(struct host_cmd_handler_args *args) { #ifdef CONFIG_ZEPHYR /* For Zephyr, convert the received remote port number to a port number @@ -1537,8 +1481,7 @@ i2c_command_control(struct host_cmd_handler_args *args) */ ((struct ec_params_i2c_control *)(args->params))->port = i2c_get_port_from_remote_port( - ((struct ec_params_i2c_control *)(args->params)) - ->port); + ((struct ec_params_i2c_control *)(args->params))->port); #endif const struct ec_params_i2c_control *params = args->params; struct ec_response_i2c_control *resp = args->response; @@ -1559,7 +1502,7 @@ i2c_command_control(struct host_cmd_handler_args *args) old_i2c_freq = i2c_get_freq(cfg->port); khz = i2c_freq_to_khz(old_i2c_freq); old_i2c_speed_khz = (khz != 0) ? khz : - EC_I2C_CONTROL_SPEED_UNKNOWN; + EC_I2C_CONTROL_SPEED_UNKNOWN; break; case EC_I2C_CONTROL_SET_SPEED: @@ -1576,9 +1519,7 @@ i2c_command_control(struct host_cmd_handler_args *args) return EC_RES_ERROR; CPRINTS("I2C%d speed changed from %d kHz to %d kHz", - params->port, - old_i2c_speed_khz, - new_i2c_speed_khz); + params->port, old_i2c_speed_khz, new_i2c_speed_khz); break; default: @@ -1591,8 +1532,7 @@ i2c_command_control(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_I2C_CONTROL, i2c_command_control, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_I2C_CONTROL */ @@ -1608,7 +1548,8 @@ static int command_i2cprotect(int argc, char **argv) for (i = 0; i < i2c_ports_used; i++) { port = i2c_ports[i].port; ccprintf("Port %d: %s\n", port, - port_protected[port] ? "Protected" : "Unprotected"); + port_protected[port] ? "Protected" : + "Unprotected"); } } else if (argc == 2) { int port; @@ -1620,7 +1561,7 @@ static int command_i2cprotect(int argc, char **argv) if (!get_i2c_port(port)) { ccprintf("i2c passthru protect invalid port %d\n", - port); + port); return EC_RES_INVALID_PARAM; } @@ -1631,8 +1572,7 @@ static int command_i2cprotect(int argc, char **argv) return EC_RES_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect, - "[port]", +DECLARE_CONSOLE_COMMAND(i2cprotect, command_i2cprotect, "[port]", "Protect I2C bus"); #endif @@ -1662,12 +1602,12 @@ static void scan_bus(int port, const char *desc) */ for (addr_flags = I2C_FIRST_VALID_ADDR; addr_flags <= I2C_LAST_VALID_ADDR; ++addr_flags) { - watchdog_reload(); /* Otherwise a full scan trips watchdog */ + watchdog_reload(); /* Otherwise a full scan trips watchdog */ ccputs("."); /* Do a single read */ - if (!i2c_xfer_unlocked(port, addr_flags, - NULL, 0, &tmp, 1, I2C_XFER_SINGLE)) + if (!i2c_xfer_unlocked(port, addr_flags, NULL, 0, &tmp, 1, + I2C_XFER_SINGLE)) ccprintf("\n 0x%02x", addr_flags); } @@ -1694,7 +1634,6 @@ static int command_scan(int argc, char **argv) return EC_SUCCESS; } - port = strtoi(argv[1], &e, 0); if (*e) return EC_ERROR_PARAM2; @@ -1707,8 +1646,7 @@ static int command_scan(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cscan, command_scan, - "i2cscan [port]", +DECLARE_CONSOLE_COMMAND(i2cscan, command_scan, "i2cscan [port]", "Scan I2C ports for devices"); #endif @@ -1750,22 +1688,18 @@ static int command_i2cxfer(int argc, char **argv) if (strcasecmp(argv[1], "r") == 0) { /* 8-bit read */ if (offset_size == 2) - rv = i2c_read_offset16(port, addr_flags, - offset, &v, 1); + rv = i2c_read_offset16(port, addr_flags, offset, &v, 1); else - rv = i2c_read8(port, addr_flags, - offset, &v); + rv = i2c_read8(port, addr_flags, offset, &v); if (!rv) ccprintf("0x%02x [%d]\n", v, v); } else if (strcasecmp(argv[1], "r16") == 0) { /* 16-bit read */ if (offset_size == 2) - rv = i2c_read_offset16(port, addr_flags, - offset, &v, 2); + rv = i2c_read_offset16(port, addr_flags, offset, &v, 2); else - rv = i2c_read16(port, addr_flags, - offset, &v); + rv = i2c_read16(port, addr_flags, offset, &v); if (!rv) ccprintf("0x%04x [%d]\n", v, v); @@ -1774,8 +1708,7 @@ static int command_i2cxfer(int argc, char **argv) if (argc < 6 || v < 0 || v > sizeof(data)) return EC_ERROR_PARAM5; - rv = i2c_xfer(port, addr_flags, - (uint8_t *)&offset, 1, data, v); + rv = i2c_xfer(port, addr_flags, (uint8_t *)&offset, 1, data, v); if (!rv) ccprintf("Data: %ph\n", HEX_BUF(data, v)); @@ -1785,22 +1718,18 @@ static int command_i2cxfer(int argc, char **argv) if (argc < 6) return EC_ERROR_PARAM5; if (offset_size == 2) - rv = i2c_write_offset16(port, addr_flags, - offset, v, 1); + rv = i2c_write_offset16(port, addr_flags, offset, v, 1); else - rv = i2c_write8(port, addr_flags, - offset, v); + rv = i2c_write8(port, addr_flags, offset, v); } else if (strcasecmp(argv[1], "w16") == 0) { /* 16-bit write */ if (argc < 6) return EC_ERROR_PARAM5; if (offset_size == 2) - rv = i2c_write_offset16(port, addr_flags, - offset, v, 2); + rv = i2c_write_offset16(port, addr_flags, offset, v, 2); else - rv = i2c_write16(port, addr_flags, - offset, v); + rv = i2c_write16(port, addr_flags, offset, v); #ifdef CONFIG_CMD_I2C_XFER_RAW } else if (strcasecmp(argv[1], "raw") == 0) { /* [write_bytes..] */ @@ -1836,11 +1765,8 @@ static int command_i2cxfer(int argc, char **argv) xferflags |= I2C_XFER_STOP; ccprintf("Writing %d bytes\n", write_count); i2c_lock(port, 1); - rv = i2c_xfer_unlocked(port, - addr_flags, - data, write_count, - NULL, 0, - xferflags); + rv = i2c_xfer_unlocked(port, addr_flags, data, + write_count, NULL, 0, xferflags); if (rv || read_count == 0) { i2c_lock(port, 0); return rv; @@ -1850,10 +1776,8 @@ static int command_i2cxfer(int argc, char **argv) ccprintf("Reading %d bytes\n", read_count); if (write_count == 0) i2c_lock(port, 1); - rv = i2c_xfer_unlocked(port, - addr_flags, - NULL, 0, - data, read_count, + rv = i2c_xfer_unlocked(port, addr_flags, NULL, 0, data, + read_count, I2C_XFER_START | I2C_XFER_STOP); i2c_lock(port, 0); if (!rv) @@ -1878,7 +1802,7 @@ DECLARE_CONSOLE_COMMAND(i2cxfer, command_i2cxfer, #ifdef CONFIG_CMD_I2C_SPEED -static const char * const i2c_freq_str[] = { +static const char *const i2c_freq_str[] = { [I2C_FREQ_1000KHZ] = "1000 kHz", [I2C_FREQ_400KHZ] = "400 kHz", [I2C_FREQ_100KHZ] = "100 kHz", @@ -1936,16 +1860,14 @@ static int command_i2c_speed(int argc, char **argv) if (new_freq != I2C_FREQ_COUNT) ccprintf("Port %d speed changed from %s to %s\n", port, - i2c_freq_str[freq], - i2c_freq_str[new_freq]); + i2c_freq_str[freq], i2c_freq_str[new_freq]); else ccprintf("Port %d speed is %s\n", port, i2c_freq_str[freq]); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cspeed, command_i2c_speed, - "port [speed in kHz]", +DECLARE_CONSOLE_COMMAND(i2cspeed, command_i2c_speed, "port [speed in kHz]", "Get or set I2C port speed"); #endif /* CONFIG_CMD_I2C_SPEED */ @@ -1955,19 +1877,16 @@ static void i2c_test_status(struct i2c_test_results *i2c_test, int test_dev) { ccprintf("test_dev=%2d, ", test_dev); ccprintf("r=%5d, rs=%5d, rf=%5d, ", - i2c_test->read_success + i2c_test->read_fail, - i2c_test->read_success, - i2c_test->read_fail); + i2c_test->read_success + i2c_test->read_fail, + i2c_test->read_success, i2c_test->read_fail); ccprintf("w=%5d, ws=%5d, wf=%5d\n", - i2c_test->write_success + i2c_test->write_fail, - i2c_test->write_success, - i2c_test->write_fail); + i2c_test->write_success + i2c_test->write_fail, + i2c_test->write_success, i2c_test->write_fail); i2c_test->read_success = 0; i2c_test->read_fail = 0; - i2c_test->write_success = 0, - i2c_test->write_fail = 0; + i2c_test->write_success = 0, i2c_test->write_fail = 0; } #define I2C_STRESS_TEST_DATA_VERIFY_RETRY_COUNT 3 @@ -2025,10 +1944,11 @@ static int command_i2ctest(int argc, char **argv) if (rand & 0x1) { /* read */ rv = i2c_s_test->i2c_read ? - i2c_s_test->i2c_read(port, addr_flags, - reg_s_info->read_reg, &data) : - i2c_s_test->i2c_read_dev( - reg_s_info->read_reg, &data); + i2c_s_test->i2c_read(port, addr_flags, + reg_s_info->read_reg, + &data) : + i2c_s_test->i2c_read_dev( + reg_s_info->read_reg, &data); if (rv || data != reg_s_info->read_val) test_s_results->read_fail++; else @@ -2042,10 +1962,11 @@ static int command_i2ctest(int argc, char **argv) /* Read the write register */ rv = i2c_s_test->i2c_read ? - i2c_s_test->i2c_read(port, addr_flags, - reg_s_info->read_reg, &data) : - i2c_s_test->i2c_read_dev( - reg_s_info->read_reg, &data); + i2c_s_test->i2c_read(port, addr_flags, + reg_s_info->read_reg, + &data) : + i2c_s_test->i2c_read_dev( + reg_s_info->read_reg, &data); if (rv) { /* Skip writing invalid data */ test_s_results->read_fail++; @@ -2057,11 +1978,13 @@ static int command_i2ctest(int argc, char **argv) do { /* Write same value back */ rv = i2c_s_test->i2c_write ? - i2c_s_test->i2c_write(port, - addr_flags, - reg_s_info->write_reg, data) : - i2c_s_test->i2c_write_dev( - reg_s_info->write_reg, data); + i2c_s_test->i2c_write( + port, addr_flags, + reg_s_info->write_reg, + data) : + i2c_s_test->i2c_write_dev( + reg_s_info->write_reg, + data); i++; if (rv) { /* Skip reading as write failed */ @@ -2072,11 +1995,13 @@ static int command_i2ctest(int argc, char **argv) /* Read back to verify the data */ rv = i2c_s_test->i2c_read ? - i2c_s_test->i2c_read(port, - addr_flags, - reg_s_info->read_reg, &data_verify) : - i2c_s_test->i2c_read_dev( - reg_s_info->read_reg, &data_verify); + i2c_s_test->i2c_read( + port, addr_flags, + reg_s_info->read_reg, + &data_verify) : + i2c_s_test->i2c_read_dev( + reg_s_info->read_reg, + &data_verify); i++; if (rv) { /* Read failed try next time */ @@ -2111,7 +2036,6 @@ static int command_i2ctest(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest, - "i2ctest count|udelay|dev", +DECLARE_CONSOLE_COMMAND(i2ctest, command_i2ctest, "i2ctest count|udelay|dev", "I2C stress test"); #endif /* CONFIG_CMD_I2C_STRESS_TEST */ -- cgit v1.2.1 From f86bcae0e82eb26f60b2f0322bef3f80c562d88f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:55 -0600 Subject: chip/host/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94c737eb405a437e884826076daeeac9adf1d5fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729170 Reviewed-by: Jeremy Bettis --- chip/host/uart.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/chip/host/uart.c b/chip/host/uart.c index 578924612f..4c8474bcaa 100644 --- a/chip/host/uart.c +++ b/chip/host/uart.c @@ -55,7 +55,6 @@ static void test_capture_char(char c) capture_buf[capture_size++] = c; } - const char *test_get_captured_console(void) { return (const char *)capture_buf; @@ -190,6 +189,6 @@ void uart_init(void) pthread_mutex_unlock(&mutex); #endif - stopped = 1; /* Not transmitting yet */ + stopped = 1; /* Not transmitting yet */ init_done = 1; } -- cgit v1.2.1 From fa5582d6982ab873b6ca8b59cf9a3e2b381030f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:11 -0600 Subject: driver/als_al3010.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd65383bb6179a00deb782b2c3b2cece9f212bfa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729898 Reviewed-by: Jeremy Bettis --- driver/als_al3010.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/driver/als_al3010.h b/driver/als_al3010.h index 288e255990..f129f8a532 100644 --- a/driver/als_al3010.h +++ b/driver/als_al3010.h @@ -9,32 +9,32 @@ #define __CROS_EC_ALS_AL3010_H /* I2C interface */ -#define AL3010_I2C_ADDR1_FLAGS 0x1C -#define AL3010_I2C_ADDR2_FLAGS 0x1D -#define AL3010_I2C_ADDR3_FLAGS 0x1E +#define AL3010_I2C_ADDR1_FLAGS 0x1C +#define AL3010_I2C_ADDR2_FLAGS 0x1D +#define AL3010_I2C_ADDR3_FLAGS 0x1E /* AL3010 registers */ -#define AL3010_REG_SYSTEM 0x00 -#define AL3010_REG_INT_STATUS 0x01 -#define AL3010_REG_CONFIG 0x10 -#define AL3010_REG_DATA_LOW 0x0C +#define AL3010_REG_SYSTEM 0x00 +#define AL3010_REG_INT_STATUS 0x01 +#define AL3010_REG_CONFIG 0x10 +#define AL3010_REG_DATA_LOW 0x0C -#define AL3010_ENABLE 0x01 +#define AL3010_ENABLE 0x01 #define AL3010_GAIN_SELECT 3 -#define AL3010_GAIN_1 0 /* 77806 lx */ -#define AL3010_GAIN_2 1 /* 19452 lx */ -#define AL3010_GAIN_3 2 /* 4863 lx */ -#define AL3010_GAIN_4 3 /* 1216 lx */ -#define AL3010_GAIN CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT) +#define AL3010_GAIN_1 0 /* 77806 lx */ +#define AL3010_GAIN_2 1 /* 19452 lx */ +#define AL3010_GAIN_3 2 /* 4863 lx */ +#define AL3010_GAIN_4 3 /* 1216 lx */ +#define AL3010_GAIN CONCAT2(AL3010_GAIN_, AL3010_GAIN_SELECT) -#define AL3010_GAIN_SCALE_1 11872 /* 1.1872 lux/count */ -#define AL3010_GAIN_SCALE_2 2968 /* 0.2968 lux/count */ -#define AL3010_GAIN_SCALE_3 742 /* 0.0742 lux/count */ -#define AL3010_GAIN_SCALE_4 186 /* 0.0186 lux/count */ +#define AL3010_GAIN_SCALE_1 11872 /* 1.1872 lux/count */ +#define AL3010_GAIN_SCALE_2 2968 /* 0.2968 lux/count */ +#define AL3010_GAIN_SCALE_3 742 /* 0.0742 lux/count */ +#define AL3010_GAIN_SCALE_4 186 /* 0.0186 lux/count */ #define AL3010_GAIN_SCALE CONCAT2(AL3010_GAIN_SCALE_, AL3010_GAIN_SELECT) int al3010_init(void); int al3010_read_lux(int *lux, int af); -#endif /* __CROS_EC_ALS_AL3010_H */ +#endif /* __CROS_EC_ALS_AL3010_H */ -- cgit v1.2.1 From 829ed8a6c0e2556c228c1c2ec1ec1c88ae527af5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:24 -0600 Subject: driver/ioexpander/ioexpander_nct38xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I993c1809bc6e9f888cdd251f73643ccf8b13d0b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729983 Reviewed-by: Jeremy Bettis --- driver/ioexpander/ioexpander_nct38xx.c | 84 ++++++++++++++++------------------ 1 file changed, 40 insertions(+), 44 deletions(-) diff --git a/driver/ioexpander/ioexpander_nct38xx.c b/driver/ioexpander/ioexpander_nct38xx.c index 6d30e4ecc3..e691f62c83 100644 --- a/driver/ioexpander/ioexpander_nct38xx.c +++ b/driver/ioexpander/ioexpander_nct38xx.c @@ -13,8 +13,8 @@ #include "nct38xx.h" #include "tcpm/tcpci.h" -#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT #error "This driver doesn't support get_port function" @@ -30,7 +30,7 @@ struct nct38xx_chip_data { }; static struct nct38xx_chip_data chip_data[CONFIG_IO_EXPANDER_PORT_COUNT] = { - [0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = { {0, 0}, -1 } + [0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = { { 0, 0 }, -1 } }; static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask) @@ -41,9 +41,8 @@ static int nct38xx_ioex_check_is_valid(int ioex, int port, int mask) return EC_ERROR_INVAL; } if (mask & ~NCT38XXX_3808_VALID_GPIO_MASK) { - CPRINTF("GPIO%02d is not support in NCT3808\n", - __fls(mask)); + __fls(mask)); return EC_ERROR_INVAL; } } @@ -62,11 +61,11 @@ static int nct38xx_ioex_init(int ioex) * 010: NCT3808 */ rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - TCPC_REG_BCD_DEV, &val); + TCPC_REG_BCD_DEV, &val); if (rv != EC_SUCCESS) { CPRINTF("Failed to read NCT38XX DEV ID for IOexpander %d\n", - ioex); + ioex); return rv; } @@ -81,9 +80,9 @@ static int nct38xx_ioex_init(int ioex) * function of IOEX when the NCT38XX TCPCI driver is not included. */ if (!IS_ENABLED(CONFIG_USB_PD_TCPM_NCT38XX)) { - rv = i2c_write16(ioex_p->i2c_host_port, - ioex_p->i2c_addr_flags, TCPC_REG_ALERT_MASK, - TCPC_REG_ALERT_VENDOR_DEF); + rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, + TCPC_REG_ALERT_MASK, + TCPC_REG_ALERT_VENDOR_DEF); if (rv != EC_SUCCESS) return rv; } @@ -100,7 +99,7 @@ static int nct38xx_ioex_get_level(int ioex, int port, int mask, int *val) reg = NCT38XX_REG_GPIO_DATA_IN(port); rv = i2c_read8(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, val); + ioex_config[ioex].i2c_addr_flags, reg, val); if (rv != EC_SUCCESS) return rv; @@ -120,7 +119,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value) reg = NCT38XX_REG_GPIO_DATA_OUT(port); rv = i2c_read8(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, &val); + ioex_config[ioex].i2c_addr_flags, reg, &val); if (rv != EC_SUCCESS) return rv; @@ -130,7 +129,7 @@ static int nct38xx_ioex_set_level(int ioex, int port, int mask, int value) val &= ~mask; return i2c_write8(ioex_config[ioex].i2c_host_port, - ioex_config[ioex].i2c_addr_flags, reg, val); + ioex_config[ioex].i2c_addr_flags, reg, val); } static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags) @@ -177,7 +176,7 @@ static int nct38xx_ioex_get_flags(int ioex, int port, int mask, int *flags) } static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port, - int mask, int flags) + int mask, int flags) { int rv; int reg_rising, reg_falling; @@ -222,7 +221,7 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port, if (rv != EC_SUCCESS) return rv; } else if ((flags & GPIO_INT_F_RISING) || - (flags & GPIO_INT_F_FALLING)) { + (flags & GPIO_INT_F_FALLING)) { if (flags & GPIO_INT_F_RISING) rising |= mask; else @@ -242,7 +241,7 @@ static int nct38xx_ioex_sel_int_type(int i2c_port, int i2c_addr, int port, } static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask, - int flags) + int flags) { int rv, reg, val, i2c_port, i2c_addr; struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; @@ -260,8 +259,8 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask, */ if (port == 0) { /* GPIO03 in NCT3807 is not muxed with other function. */ - if (!(chip_data[ioex].chip_id == - NCT38XX_VARIANT_3807 && mask & 0x08)) { + if (!(chip_data[ioex].chip_id == NCT38XX_VARIANT_3807 && + mask & 0x08)) { reg = NCT38XX_REG_MUX_CONTROL; rv = i2c_read8(i2c_port, i2c_addr, reg, &val); if (rv != EC_SUCCESS) @@ -320,7 +319,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask, else val &= ~mask; - return i2c_write8(i2c_port, i2c_addr, reg, val); + return i2c_write8(i2c_port, i2c_addr, reg, val); } /* @@ -341,7 +340,7 @@ static int nct38xx_ioex_set_flags_by_mask(int ioex, int port, int mask, * TCPC. */ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask, - int enable) + int enable) { int rv, reg, val; struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; @@ -352,14 +351,14 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask, /* Clear the pending bit */ reg = NCT38XX_REG_GPIO_ALERT_STAT(port); - rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, &val); + rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + &val); if (rv != EC_SUCCESS) return rv; val |= mask; - rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, val); + rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + val); if (rv != EC_SUCCESS) return rv; @@ -374,8 +373,8 @@ static int nct38xx_ioex_enable_interrupt(int ioex, int port, int mask, val = chip_data[ioex].int_mask[port]; } - return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, val); + return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + val); } int nct38xx_ioex_event_handler(int ioex) @@ -386,15 +385,15 @@ int nct38xx_ioex_event_handler(int ioex) struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; int rv = 0; - int_mask = chip_data[ioex].int_mask[0] | ( - chip_data[ioex].int_mask[1] << 8); + int_mask = chip_data[ioex].int_mask[0] | + (chip_data[ioex].int_mask[1] << 8); reg = NCT38XX_REG_GPIO_ALERT_STAT(0); /* * Read ALERT_STAT_0 and ALERT_STAT_1 register in a single I2C * transaction to increase efficiency */ - rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, &int_status); + rv = i2c_read16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + &int_status); if (rv != EC_SUCCESS) return rv; @@ -403,15 +402,15 @@ int nct38xx_ioex_event_handler(int ioex) * Clear the changed status bits in ALERT_STAT_0 and ALERT_STAT_1 * register in a single I2C transaction to increase efficiency */ - rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, int_status); + rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + int_status); if (rv != EC_SUCCESS) return rv; /* For NCT3808, only check one port */ total_port = (chip_data[ioex].chip_id == NCT38XX_VARIANT_3808) ? - NCT38XX_NCT3808_MAX_IO_PORT : - NCT38XX_NCT3807_MAX_IO_PORT; + NCT38XX_NCT3808_MAX_IO_PORT : + NCT38XX_NCT3807_MAX_IO_PORT; for (i = 0; i < total_port; i++) { uint8_t pending; @@ -421,15 +420,13 @@ int nct38xx_ioex_event_handler(int ioex) continue; for (j = 0, g = ioex_list; j < ioex_ih_count; j++, g++) { - if (ioex == g->ioex && i == g->port && - (pending & g->mask)) { + (pending & g->mask)) { ioex_irq_handlers[j](j + IOEX_SIGNAL_START); pending &= ~g->mask; if (!pending) break; } - } } @@ -453,9 +450,8 @@ void nct38xx_ioex_handle_alert(int ioex) CPRINTF("fail to read ALERT register\n"); if (status & TCPC_REG_ALERT_VENDOR_DEF) { - rv = i2c_write16(ioex_p->i2c_host_port, - ioex_p->i2c_addr_flags, TCPC_REG_ALERT, - TCPC_REG_ALERT_VENDOR_DEF); + rv = i2c_write16(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, + TCPC_REG_ALERT, TCPC_REG_ALERT_VENDOR_DEF); if (rv != EC_SUCCESS) { CPRINTF("Fail to clear Vendor Define mask\n"); return; @@ -465,10 +461,10 @@ void nct38xx_ioex_handle_alert(int ioex) } const struct ioexpander_drv nct38xx_ioexpander_drv = { - .init = &nct38xx_ioex_init, - .get_level = &nct38xx_ioex_get_level, - .set_level = &nct38xx_ioex_set_level, + .init = &nct38xx_ioex_init, + .get_level = &nct38xx_ioex_get_level, + .set_level = &nct38xx_ioex_set_level, .get_flags_by_mask = &nct38xx_ioex_get_flags, .set_flags_by_mask = &nct38xx_ioex_set_flags_by_mask, - .enable_interrupt = &nct38xx_ioex_enable_interrupt, + .enable_interrupt = &nct38xx_ioex_enable_interrupt, }; -- cgit v1.2.1 From fd881f28f5593188c4bf71c99d881711dfef665b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:26 -0600 Subject: chip/it83xx/lpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5052428fed3384cb90abdaef899e44e9aa5ca893 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729203 Reviewed-by: Jeremy Bettis --- chip/it83xx/lpc.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 29f92e9b94..d9b869d571 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -30,7 +30,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) /* LPC PM channels */ enum lpc_pm_ch { @@ -48,25 +48,25 @@ enum pm_ctrl_mask { PM_CTRL_OBEIE = 0x02, }; -#define LPC_ACPI_CMD LPC_PM1 /* ACPI commands 62h/66h port */ -#define LPC_HOST_CMD LPC_PM2 /* Host commands 200h/204h port */ -#define LPC_HOST_PORT_80H LPC_PM3 /* Host 80h port */ +#define LPC_ACPI_CMD LPC_PM1 /* ACPI commands 62h/66h port */ +#define LPC_HOST_CMD LPC_PM2 /* Host commands 200h/204h port */ +#define LPC_HOST_PORT_80H LPC_PM3 /* Host 80h port */ static uint8_t acpi_ec_memmap[EC_MEMMAP_SIZE] - __attribute__((section(".h2ram.pool.acpiec"))); + __attribute__((section(".h2ram.pool.acpiec"))); static uint8_t host_cmd_memmap[256] - __attribute__((section(".h2ram.pool.hostcmd"))); + __attribute__((section(".h2ram.pool.hostcmd"))); static struct host_packet lpc_packet; static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ +static uint8_t host_cmd_flags; /* Flags from host command */ /* Params must be 32-bit aligned */ static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; static int p80l_index; -static struct ec_lpc_host_args * const lpc_host_args = +static struct ec_lpc_host_args *const lpc_host_args = (struct ec_lpc_host_args *)host_cmd_memmap; static void pm_set_ctrl(enum lpc_pm_ch ch, enum pm_ctrl_mask ctrl, int set) @@ -195,15 +195,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args) } /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; + lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | + EC_HOST_ARGS_FLAG_TO_HOST; lpc_host_args->data_size = size; csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; + lpc_host_args->command_version + lpc_host_args->data_size; for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) csum += *out; @@ -251,7 +249,7 @@ void lpc_update_host_event_status(void) /* Copy host events to mapped memory */ *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); + lpc_get_host_events(); task_enable_irq(IT83XX_IRQ_PMC_IN); @@ -390,7 +388,7 @@ void lpc_kbc_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) { keyboard_host_write(IT83XX_KBC_KBHIDIR, - (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); + (IT83XX_KBC_KBHISR & 0x08) ? 1 : 0); /* bit7, write-1 clear IBF */ IT83XX_KBC_KBHICR |= BIT(7); IT83XX_KBC_KBHICR &= ~BIT(7); @@ -733,8 +731,7 @@ void lpcrst_interrupt(enum gpio_signal signal) /* Store port 80 reset event */ port_80_write(PORT_80_EVENT_RESET); - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); + CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de"); } #endif @@ -765,6 +762,5 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, + EC_VER_MASK(0)); -- cgit v1.2.1 From 65f0a418dd424448bef9fffc90fe25f2f7da1f19 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:39 -0600 Subject: common/usbc/usbc_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d3a7f7021df57f7216ff5bb34a83c820323696d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729798 Reviewed-by: Jeremy Bettis --- common/usbc/usbc_pd_policy.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/usbc/usbc_pd_policy.c b/common/usbc/usbc_pd_policy.c index 6a06d4014f..907447c029 100644 --- a/common/usbc/usbc_pd_policy.c +++ b/common/usbc/usbc_pd_policy.c @@ -19,8 +19,8 @@ * 1) If dr_swap_to_dfp_flag == true and port data role is UFP, * transition to pe_drs_send_swap */ -__overridable bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag) +__overridable bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr, + bool dr_swap_flag) { if (dr_swap_flag && dr == PD_ROLE_UFP) return true; @@ -37,10 +37,10 @@ __overridable bool port_discovery_dr_swap_policy(int port, * then transition to pe_vcs_send_swap */ __overridable bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag) + bool vconn_swap_flag) { if (IS_ENABLED(CONFIG_USBC_VCONN) && vconn_swap_flag && - !tc_is_vconn_src(port) && tc_check_vconn_swap(port)) + !tc_is_vconn_src(port) && tc_check_vconn_swap(port)) return true; /* Do not perform a VCONN swap */ -- cgit v1.2.1 From 138e9f8649258cbcade1b1871416d332ac1fa756 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:13 -0600 Subject: chip/npcx/registers-npcx5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I667818f789af6fbb0aad57c2437a4ec8f354a71d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727025 Reviewed-by: Jeremy Bettis --- chip/npcx/registers-npcx5.h | 380 ++++++++++++++++++++++---------------------- 1 file changed, 189 insertions(+), 191 deletions(-) diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h index c441c1c926..bdd72c1716 100644 --- a/chip/npcx/registers-npcx5.h +++ b/chip/npcx/registers-npcx5.h @@ -19,87 +19,87 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 -#define NPCX_IRQ_PECI NPCX_IRQ_4 -#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 -#define NPCX_IRQ8_NOUSED NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ16_NOUSED NPCX_IRQ_16 -#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ19_NOUSED NPCX_IRQ_19 -#define NPCX_IRQ20_NOUSED NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 -#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ32_NOUSED NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 -#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 -#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 -#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 -#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 -#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTAD_0 +#define NPCX_IRQ8_NOUSED NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ16_NOUSED NPCX_IRQ_16 +#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ19_NOUSED NPCX_IRQ_19 +#define NPCX_IRQ20_NOUSED NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 +#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ32_NOUSED NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 +#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 +#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 +#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 +#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 -#define NPCX_ITIM32_BASE_ADDR 0x400BC000 -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - (0x400C0000 + (((mdl) - 2) * 0x2000L))) +#define NPCX_ITIM32_BASE_ADDR 0x400BC000 +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl)*0x2000L)) +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + (0x400C0000 + (((mdl)-2) * 0x2000L))) enum { NPCX_UART_PORT0 = 0, /* UART port 0 */ @@ -129,39 +129,39 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) /* pin-mux for JTAG */ -#define NPCX_DEVALT5_NJEN1_EN 1 -#define NPCX_DEVALT5_NJEN0_EN 2 +#define NPCX_DEVALT5_NJEN1_EN 1 +#define NPCX_DEVALT5_NJEN0_EN 2 /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C0_1_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C0_1_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C3_0_SL 6 /* pin-mux for UART */ -#define NPCX_DEVALTA_UART_SL1 7 -#define NPCX_DEVALTC_UART_SL2 0 +#define NPCX_DEVALTA_UART_SL1 7 +#define NPCX_DEVALTC_UART_SL2 0 /* pin-mux for Misc. */ /* External 32KHz crytal osc. input support */ -#define NPCX_DEVALTA_32KCLKIN_SL 3 +#define NPCX_DEVALTA_32KCLKIN_SL 3 /* SMBus register fields */ -#define NPCX_SMBSEL_SMB0SEL 0 +#define NPCX_SMBSEL_SMB0SEL 0 /* SMB enumeration: I2C port definitions. */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */ - NPCX_I2C_PORT1, /* I2C port 1 */ - NPCX_I2C_PORT2, /* I2C port 2 */ - NPCX_I2C_PORT3, /* I2C port 3 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */ + NPCX_I2C_PORT1, /* I2C port 1 */ + NPCX_I2C_PORT2, /* I2C port 2 */ + NPCX_I2C_PORT3, /* I2C port 3 */ NPCX_I2C_COUNT, }; @@ -195,32 +195,31 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD)) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD)) /* BBRAM register fields */ #define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) -#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ +#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ /* ITIM registers */ -#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) -#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) +#define NPCX_ITCNT8(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x000) +#define NPCX_ITCNT16(n) REG16(NPCX_ITIM_BASE_ADDR(n) + 0x002) /* ITIM32 registers */ -#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) +#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32 /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT16 +#define NPCX_ITCNT NPCX_ITCNT16 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM16_1 +#define ITIM_EVENT_NO ITIM16_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM16_5 +#define ITIM_WDG_NO ITIM16_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32 +#define ITIM_SYSTEM_NO ITIM32 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -235,11 +234,11 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers */ -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n)) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n)) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_INTWK_EN VWEVMS_INT_EN +#define VWEVMS_INTWK_EN VWEVMS_INT_EN /* eSPI max supported frequency */ enum { @@ -253,35 +252,35 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #elif (FMCLK <= 48000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 #endif /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0A + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0C + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1E + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*2L) + ((n) < 5 ? 0 : 0x1E)) +#define NPCX_WKPND_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0A + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKPCL_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x0C + ((n)*4L) + ((n) < 5 ? 0 : 0x10)) +#define NPCX_WKEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1E + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x1F + ((n)*2L) + ((n) < 5 ? 0 : 0x12)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -289,22 +288,22 @@ enum { * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is * always 1 == MIWU_TABLE_1. */ -#define NPCX_UART_WK_GROUP 6 -#define NPCX_UART_WK_BIT 4 -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_WK_GROUP 6 +#define NPCX_UART_WK_BIT 4 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_WK_GROUP 1 -#define NPCX_UART_WK_BIT 0 -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 +#define NPCX_UART_WK_GROUP 1 +#define NPCX_UART_WK_BIT 0 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) +#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) +#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 #endif /* NPCX_UART_MODULE2 */ /* This routine checks pending bit of GPIO wake-up functionality */ @@ -328,8 +327,7 @@ static inline void uart_clear_pending_wakeup(void) /* This routine enables wake-up functionality from GPIO on UART rx pin */ static inline void uart_enable_wakeup(int enable) { - UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, - enable); + UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, enable); } /* This routine checks functionality is UART rx or not */ @@ -339,50 +337,50 @@ static inline int npcx_is_uart(void) } /* ADC Registers */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n))) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L * (n))) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L * (n))) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* ADC register fields */ -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_THR_DCTL_THRD_EN 15 -#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH_CNT 3 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_THR_DCTL_THRD_EN 15 +#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH_CNT 3 -- cgit v1.2.1 From 61ae9f7ad560e01c3bd1d0c30f77cd6e0a9a2ea3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:39 -0600 Subject: common/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibba79223b2fd065b98d8d50d68aa5e3542c16cba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729775 Reviewed-by: Jeremy Bettis --- common/usb_pd_policy.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c index 30aa936f28..29460d083c 100644 --- a/common/usb_pd_policy.c +++ b/common/usb_pd_policy.c @@ -90,7 +90,7 @@ DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_DP_ALT_MODE_ENTERED, static uint32_t pd_src_caps[CONFIG_USB_PD_PORT_MAX_COUNT][PDO_MAX_OBJECTS]; static uint8_t pd_src_cap_cnt[CONFIG_USB_PD_PORT_MAX_COUNT]; -const uint32_t * const pd_get_src_caps(int port) +const uint32_t *const pd_get_src_caps(int port) { return pd_src_caps[port]; } @@ -373,14 +373,14 @@ static int dfp_discover_svids(uint32_t *payload) return 1; } -struct pd_discovery *pd_get_am_discovery_and_notify_access( - int port, enum tcpci_msg_type type) +struct pd_discovery * +pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type) { return (struct pd_discovery *)pd_get_am_discovery(port, type); } const struct pd_discovery *pd_get_am_discovery(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { return &discovery[port][type]; } @@ -407,7 +407,7 @@ void pd_set_dfp_enter_mode_flag(int port, bool set) static int dfp_discover_modes(int port, uint32_t *payload) { const struct pd_discovery *disc = - pd_get_am_discovery(port, TCPCI_MSG_SOP); + pd_get_am_discovery(port, TCPCI_MSG_SOP); uint16_t svid = disc->svids[disc->svid_idx].svid; if (disc->svid_idx >= disc->svid_cnt) @@ -553,8 +553,7 @@ static int process_am_discover_svids(int port, int cnt, uint32_t *payload, return dfp_discover_modes(port, payload); } -static int process_tbt_compat_discover_modes(int port, - enum tcpci_msg_type sop, +static int process_tbt_compat_discover_modes(int port, enum tcpci_msg_type sop, uint32_t *payload, enum tcpci_msg_type *rtype) { @@ -776,7 +775,7 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload, } else { if (!modep->opos) pd_dfp_enter_mode(port, TCPCI_MSG_SOP, - 0, 0); + 0, 0); if (modep->opos) { rsize = modep->fx->status(port, @@ -805,7 +804,7 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload, * config ack). */ if (svdm_dp_get_mux_mode(port) == - USB_PD_MUX_DP_ENABLED) + USB_PD_MUX_DP_ENABLED) usb_mux_set_safe_mode(port); rsize = modep->fx->config(port, payload); } else { @@ -952,7 +951,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload) flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF; crec_flash_physical_erase(CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_STORAGE_OFF, + CONFIG_RW_STORAGE_OFF, CONFIG_RW_SIZE); rw_flash_changed = 1; break; @@ -963,7 +962,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload) CONFIG_EC_WRITABLE_STORAGE_OFF + CONFIG_RW_STORAGE_OFF)) break; crec_flash_physical_write(flash_offset, 4 * (cnt - 1), - (const char *)(payload + 1)); + (const char *)(payload + 1)); flash_offset += 4 * (cnt - 1); rw_flash_changed = 1; break; @@ -976,7 +975,7 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload) for (offset = FW_RW_END - RSANUMBYTES; offset < FW_RW_END; offset += 4) crec_flash_physical_write(offset, 4, - (const char *)&zero); + (const char *)&zero); } break; default: -- cgit v1.2.1 From 118952d16fcb35bf6c88dd2062b8768e54317d0c Mon Sep 17 00:00:00 2001 From: ben chen Date: Tue, 14 Jun 2022 11:00:39 +0800 Subject: kuldax: modify gpio setting and remove USB C1/C2 modify gpio setting for new layout. BUG=b:231667209 BRANCH=None TEST=make BOARD=kuldax Change-Id: I0f62a7f1f4d1c010d6fefd8bd7e47cd02144726e Signed-off-by: Ben Chen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707073 Reviewed-by: caveh jalali Reviewed-by: Zhuohao Lee --- board/kuldax/board.c | 23 ------ board/kuldax/board.h | 16 +--- board/kuldax/ec.tasklist | 5 +- board/kuldax/gpio.inc | 65 ++++++---------- board/kuldax/i2c.c | 8 -- board/kuldax/usbc_config.c | 188 +++------------------------------------------ board/kuldax/usbc_config.h | 4 +- 7 files changed, 38 insertions(+), 271 deletions(-) diff --git a/board/kuldax/board.c b/board/kuldax/board.c index dff60f4986..cd3ed8e58b 100644 --- a/board/kuldax/board.c +++ b/board/kuldax/board.c @@ -113,8 +113,6 @@ int board_set_active_charge_port(int port) switch (port) { case CHARGE_PORT_TYPEC0: - case CHARGE_PORT_TYPEC1: - case CHARGE_PORT_TYPEC2: gpio_set_level(GPIO_EN_PPVAR_BJ_ADP_L, 1); break; case CHARGE_PORT_BARRELJACK: @@ -456,26 +454,6 @@ static void power_monitor(void) if (!(current_state & THROT_TYPE_C0)) gap += POWER_GAIN_TYPE_C; } - /* - * If the type-C port is sourcing power, - * check whether it should be throttled. - */ - if (ppc_is_sourcing_vbus(1) && gap <= 0) { - new_state |= THROT_TYPE_C1; - headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW; - if (!(current_state & THROT_TYPE_C1)) - gap += POWER_GAIN_TYPE_C; - } - /* - * If the type-C port is sourcing power, - * check whether it should be throttled. - */ - if (ppc_is_sourcing_vbus(2) && gap <= 0) { - new_state |= THROT_TYPE_C2; - headroom_5v_z1 += PWR_Z1_C_HIGH - PWR_Z1_C_LOW; - if (!(current_state & THROT_TYPE_C2)) - gap += POWER_GAIN_TYPE_C; - } /* * As a last resort, turn on PROCHOT to * throttle the CPU. @@ -585,7 +563,6 @@ static void power_monitor(void) int typea_bc = (new_state & THROT_TYPE_A_FRONT) ? 1 : 0; gpio_set_level(GPIO_USB_A_LOW_PWR2_OD, typea_bc); - gpio_set_level(GPIO_USB_A_LOW_PWR3_OD, typea_bc); } hook_call_deferred(&power_monitor_data, delay); } diff --git a/board/kuldax/board.h b/board/kuldax/board.h index bb339a080e..0e0c248cf9 100644 --- a/board/kuldax/board.h +++ b/board/kuldax/board.h @@ -16,7 +16,7 @@ #define CONFIG_MP2964 /* Barrel Jack */ -#define DEDICATED_CHARGE_PORT 3 +#define DEDICATED_CHARGE_PORT 1 /* HDMI CEC */ #define CONFIG_CEC @@ -31,16 +31,10 @@ /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY -#define CONFIG_IO_EXPANDER -#define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 - #define CONFIG_USB_PD_PPC #define CONFIG_USB_PD_TCPM_RT1715 #define CONFIG_USBC_RETIMER_INTEL_BB -#define CONFIG_USBC_RETIMER_KB800X -#define CONFIG_KB800X_CUSTOM_XBAR #define CONFIG_USBC_PPC_SYV682X #undef CONFIG_SYV682X_HV_ILIM #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 @@ -94,9 +88,7 @@ /* I2C Bus Configuration */ #define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 - -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 #define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 #define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 @@ -159,8 +151,6 @@ enum charge_port { CHARGE_PORT_TYPEC0, - CHARGE_PORT_TYPEC1, - CHARGE_PORT_TYPEC2, CHARGE_PORT_BARRELJACK, CHARGE_PORT_ENUM_COUNT }; @@ -183,8 +173,6 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT }; - enum pwm_channel { PWM_CH_LED_GREEN, /* PWM0 */ PWM_CH_FAN, /* PWM5 */ diff --git a/board/kuldax/ec.tasklist b/board/kuldax/ec.tasklist index 0688607266..13d51d7bd6 100644 --- a/board/kuldax/ec.tasklist +++ b/board/kuldax/ec.tasklist @@ -22,8 +22,5 @@ TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ - TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ - TASK_ALWAYS(PD_C2, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ - TASK_ALWAYS(PD_INT_C0, pd_shared_alert_task, (BIT(2) | BIT(0)), LARGER_TASK_STACK_SIZE) \ - TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(CEC, cec_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/kuldax/gpio.inc b/board/kuldax/gpio.inc index 617463b7f6..0c43d7734f 100644 --- a/board/kuldax/gpio.inc +++ b/board/kuldax/gpio.inc @@ -21,12 +21,6 @@ GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt GPIO_INT(USB_C0_C2_TCPC_INT_ODL, PIN(E, 0), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C0_PPC_INT_ODL, PIN(6, 2), GPIO_INT_FALLING, ppc_interrupt) GPIO_INT(USB_C0_RT_INT_ODL, PIN(B, 1), GPIO_INT_FALLING, retimer_interrupt) -GPIO_INT(USB_C1_BC12_INT_ODL, PIN(5, 0), GPIO_INT_FALLING, bc12_interrupt) -GPIO_INT(USB_C1_PPC_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C1_TCPC_INT_ODL, PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event) -GPIO_INT(USB_C2_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_interrupt) -GPIO_INT(USB_C2_PPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt) -GPIO_INT(USB_C2_RT_INT_ODL, PIN(4, 1), GPIO_INT_FALLING, retimer_interrupt) GPIO_INT(BJ_ADP_PRESENT_ODL, PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt) GPIO_INT(EC_RECOVERY_BTN_OD, PIN(2, 3), GPIO_INT_BOTH, button_interrupt) GPIO_INT(HDMI_CONN_OC_ODL, PIN(2, 4), GPIO_INPUT | GPIO_INT_BOTH, port_ocp_interrupt) @@ -79,13 +73,6 @@ GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) GPIO(GSC_EC_RECOVERY_BTN_OD, PIN(2, 2), GPIO_INPUT) -/* NFC */ -/* TODO(b/194068530): Enable NFC */ -GPIO(NFC_COIL_ACT_L, PIN(D, 4), GPIO_INPUT) -GPIO(NFC_LOW_POWER_MODE, PIN(9, 5), GPIO_OUT_HIGH) -GPIO(NFC_CARD_DET_L, PIN(A, 3), GPIO_INPUT) -GPIO(EN_NFC_BUZZER, PIN(0, 5), GPIO_OUT_LOW) - /* Wireless Charger */ GPIO(EC_QI_PWR, PIN(D, 2), GPIO_OUT_LOW) GPIO(QI_RESET_L, PIN(9, 3), GPIO_OUT_HIGH) @@ -111,19 +98,14 @@ GPIO(EC_I2C_USB_C0_C2_TCPC_SCL, PIN(9, 0), GPIO_INPUT) GPIO(EC_I2C_USB_C0_C2_TCPC_SDA, PIN(8, 7), GPIO_INPUT) GPIO(EC_I2C_USB_C1_MIX_SCL, PIN(E, 4), GPIO_INPUT) GPIO(EC_I2C_USB_C1_MIX_SDA, PIN(E, 3), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_TCPC_SCL, PIN(F, 3), GPIO_INPUT) -GPIO(EC_I2C_USB_C1_TCPC_SDA, PIN(F, 2), GPIO_INPUT) /* USBA */ GPIO(EN_PP5000_USBA, PIN(D, 7), GPIO_OUT_LOW) GPIO(USB_A0_STATUS_L, PIN(2, 1), GPIO_INPUT) GPIO(USB_A1_STATUS_L, PIN(2, 0), GPIO_INPUT) -GPIO(USB_A2_STATUS_L, PIN(1, 7), GPIO_INPUT) -GPIO(USB_A3_STATUS_L, PIN(1, 6), GPIO_INPUT) GPIO(USB_A_LOW_PWR0_OD, PIN(1, 5), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(USB_A_LOW_PWR1_OD, PIN(1, 4), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(USB_A_LOW_PWR2_OD, PIN(1, 1), GPIO_INPUT | GPIO_PULL_DOWN) -GPIO(USB_A_LOW_PWR3_OD, PIN(1, 0), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(USB_A_OC_SOC_L, PIN(8, 0), GPIO_OUT_HIGH) /* LED */ @@ -132,22 +114,9 @@ GPIO(LED_GREEN_L, PIN(C, 3), GPIO_OUT_LOW) GPIO(LED_RED_L, PIN(C, 4), GPIO_OUT_LOW) /* USBC */ -GPIO(USB_C0_C2_TCPC_RST_ODL, PIN(A, 7), GPIO_ODR_LOW) -GPIO(USB_C1_FRS_EN, PIN(9, 4), GPIO_OUT_LOW) +GPIO(USB_C0_FRS_EN, PIN(A, 3), GPIO_OUT_LOW) GPIO(USB_C1_RT_INT_ODL, PIN(A, 0), GPIO_INPUT) -GPIO(USB_C1_RT_RST_R_L, PIN(0, 2), GPIO_OUT_LOW) - -/* GPIO02_P2 to PU */ -/* GPIO03_P2 to PU */ -IOEX(USB_C0_OC_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C0_FRS_EN, EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW) -IOEX(USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW) - -IOEX(USB_C2_RT_RST_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW) -IOEX(USB_C1_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH) -IOEX(USB_C2_OC_ODL, EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH) -IOEX(USB_C2_FRS_EN, EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW) -/* GPIO07_P2 to PU */ +GPIO(USB_C0_RT_RST_ODL, PIN(9, 5), GPIO_ODR_LOW) /* UART alternate functions */ ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* GPIO64/CR_SIN1, GPO65/CR_SOUT1/FLPRG1_L */ @@ -173,15 +142,31 @@ ALTERNATE(PIN_MASK(4, 0x38), 0, MODULE_ADC, 0) /* GPIO45/ADC0, GPI ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0) /* GPIOE1/ADC7 */ /* Unused Pins */ -UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ +UNUSED(PIN(0, 2)) /* GPIO02/PSL_IN4 */ +UNUSED(PIN(0, 4)) /* KSO13/GPIO04 */ +UNUSED(PIN(0, 5)) /* KSO13/GPIO05 */ +UNUSED(PIN(0, 6)) /* KSO11/GPIO06/P80_CLK */ +UNUSED(PIN(1, 0)) /* KSO9/GPIO10/CR_SIN1 */ +UNUSED(PIN(1, 2)) /* KSO07/GPO12/JEN# */ +UNUSED(PIN(1, 3)) /* KSO06/GPO13/GP_SEL# */ +UNUSED(PIN(1, 6)) /* KSO3/GPIO16 */ +UNUSED(PIN(1, 7)) /* KSO2/GPIO17/JTAG_TDI */ UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */ UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ +UNUSED(PIN(4, 1)) /* GPIO41/ADC4 */ +UNUSED(PIN(5, 0)) /* GPIO50 */ +UNUSED(PIN(5, 6)) /* GPIO56/CLKRUN# */ UNUSED(PIN(6, 6)) /* GPIO66 */ +UNUSED(PIN(7, 0)) /* GPIO70/PS2_DAT0*/ UNUSED(PIN(8, 1)) /* GPIO81/PECI_DATA */ -UNUSED(PIN(5, 6)) /* GPIO56/CLKRUN# */ -UNUSED(PIN(9, 7)) /* GPIO97 */ +UNUSED(PIN(8, 3)) /* KSO15/GPIO83 */ UNUSED(PIN(8, 6)) /* GPIO86/TXD/CR_SOUT2 */ -UNUSED(PIN(1, 3)) /* KSO06/GPO13/GP_SEL# */ -UNUSED(PIN(1, 2)) /* KSO07/GPO12/JEN# */ -UNUSED(PIN(0, 6)) /* KSO11/GPIO06/P80_CLK */ -UNUSED(PIN(0, 4)) /* KSO13/GPIO04 */ +UNUSED(PIN(9, 7)) /* GPIO97 */ +UNUSED(PIN(9, 4)) /* GPIO94*/ +UNUSED(PIN(A, 2)) /* F_SCLK/GPIOA2 */ +UNUSED(PIN(A, 7)) /* GPIOA7 */ +UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ +UNUSED(PIN(D, 4)) /* GPIOD4/CR_SIN3 */ +UNUSED(PIN(F, 2)) /* GPIOF2/I2C4_SDA1*/ +UNUSED(PIN(F, 3)) /* GPIOF3/I2C4_SCL1*/ +UNUSED(PIN(F, 5)) /* GPIOF5/I2C5_SCL1*/ diff --git a/board/kuldax/i2c.c b/board/kuldax/i2c.c index 9c92852461..b114cfe64d 100644 --- a/board/kuldax/i2c.c +++ b/board/kuldax/i2c.c @@ -42,14 +42,6 @@ const struct i2c_port_t i2c_ports[] = { .scl = GPIO_EC_I2C_USB_C0_C2_RT_SCL, .sda = GPIO_EC_I2C_USB_C0_C2_RT_SDA, }, - { - /* I2C4 C1 TCPC */ - .name = "tcpc1", - .port = I2C_PORT_USB_C1_TCPC, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C1_TCPC_SCL, - .sda = GPIO_EC_I2C_USB_C1_TCPC_SDA, - }, { /* I2C5 */ .name = "wireless_charger", diff --git a/board/kuldax/usbc_config.c b/board/kuldax/usbc_config.c index 020a4696a5..437dc437c1 100644 --- a/board/kuldax/usbc_config.c +++ b/board/kuldax/usbc_config.c @@ -13,14 +13,12 @@ #include "driver/ppc/syv682x_public.h" #include "driver/retimer/bb_retimer_public.h" #include "driver/retimer/kb800x.h" -#include "driver/tcpm/nct38xx.h" #include "driver/tcpm/rt1715.h" #include "driver/tcpm/tcpci.h" #include "ec_commands.h" #include "gpio.h" #include "gpio_signal.h" #include "hooks.h" -#include "ioexpander.h" #include "system.h" #include "task.h" #include "task_id.h" @@ -36,57 +34,25 @@ #define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ -const struct tcpc_config_t tcpc_config[] = { +const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { .port = I2C_PORT_USB_C0_C2_TCPC, - .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_NO_DEBUG_ACC_CONTROL, - }, - [USBC_PORT_C1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1_TCPC, .addr_flags = RT1715_I2C_ADDR_FLAGS, }, .drv = &rt1715_tcpm_drv, }, - [USBC_PORT_C2] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0_C2_TCPC, - .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, - }, - .drv = &nct38xx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0, - }, }; -BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); -BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); /* USBC PPC configuration */ -struct ppc_config_t ppc_chips[] = { +struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0_C2_PPC, .i2c_addr_flags = SYV682X_ADDR0_FLAGS, .drv = &syv682x_drv, }, - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_USB_C1_PPC, - .i2c_addr_flags = SYV682X_ADDR0_FLAGS, - .drv = &syv682x_drv, - }, - [USBC_PORT_C2] = { - .i2c_port = I2C_PORT_USB_C0_C2_PPC, - .i2c_addr_flags = SYV682X_ADDR2_FLAGS, - .drv = &syv682x_drv, - }, }; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -96,35 +62,8 @@ static const struct usb_mux usbc0_tcss_usb_mux = { .driver = &virtual_usb_mux_driver, .hpd_update = &virtual_hpd_update, }; -static const struct usb_mux usbc1_tcss_usb_mux = { - .usb_port = USBC_PORT_C1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; -static const struct usb_mux usbc2_tcss_usb_mux = { - .usb_port = USBC_PORT_C2, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -struct kb800x_control_t kb800x_control[] = { - [USBC_PORT_C0] = { - }, - [USBC_PORT_C1] = { - .retimer_rst_gpio = GPIO_USB_C1_RT_RST_R_L, - .ss_lanes = { - [KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0, - [KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1, - [KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0, - [KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1, - } - }, - [USBC_PORT_C2] = { - }, -}; -BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT); -const struct usb_mux usb_muxes[] = { +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { .usb_port = USBC_PORT_C0, .driver = &bb_usb_retimer, @@ -133,74 +72,23 @@ const struct usb_mux usb_muxes[] = { .i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR, .next_mux = &usbc0_tcss_usb_mux, }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .driver = &kb800x_usb_mux_driver, - .i2c_port = I2C_PORT_USB_C1_MUX, - .i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS, - .next_mux = &usbc1_tcss_usb_mux, - }, - [USBC_PORT_C2] = { - .usb_port = USBC_PORT_C2, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C0_C2_MUX, - .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, - .next_mux = &usbc2_tcss_usb_mux, - }, }; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); /* BC1.2 charger detect configuration */ -const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { +const struct pi3usb9201_config_t + pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0_C2_BC12, .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, }, - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_USB_C1_BC12, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, - [USBC_PORT_C2] = { - .i2c_port = I2C_PORT_USB_C0_C2_BC12, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS, - }, -}; -BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); - -/* - * USB C0 and C2 uses burnside bridge chips and have their reset - * controlled by their respective TCPC chips acting as GPIO expanders. - * - * ioex_init() is normally called before we take the TCPCs out of - * reset, so we need to start in disabled mode, then explicitly - * call ioex_init(). - */ - -struct ioexpander_config_t ioex_config[] = { - [IOEX_C0_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, - }, - [IOEX_C2_NCT38XX] = { - .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, - .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, - .drv = &nct38xx_ioexpander_drv, - .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, - }, }; -BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) { - enum ioex_signal rst_signal; + enum gpio_signal rst_signal; if (me->usb_port == USBC_PORT_C0) { - rst_signal = IOEX_USB_C0_RT_RST_ODL; - } else if (me->usb_port == USBC_PORT_C2) { - rst_signal = IOEX_USB_C2_RT_RST_ODL; + rst_signal = GPIO_USB_C0_RT_RST_ODL; } else { return EC_ERROR_INVAL; } @@ -217,14 +105,14 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) * retimer_init() function ensures power is up before calling * this function. */ - ioex_set_level(rst_signal, 1); + gpio_set_level(rst_signal, 1); /* * Allow 1ms time for the retimer to power up lc_domain * which powers I2C controller within retimer */ msleep(1); } else { - ioex_set_level(rst_signal, 0); + gpio_set_level(rst_signal, 0); msleep(1); } return EC_SUCCESS; @@ -246,34 +134,9 @@ __override int bb_retimer_reset(const struct usb_mux *me) void board_reset_pd_mcu(void) { - enum gpio_signal tcpc_rst; - - tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; - /* * TODO(b/179648104): figure out correct timing */ - - gpio_set_level(tcpc_rst, 0); - gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 0); - - /* - * delay for power-on to reset-off and min. assertion time - */ - - msleep(20); - - gpio_set_level(tcpc_rst, 1); - gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1); - - /* wait for chips to come up */ - - msleep(50); -} - -static void enable_ioex(int ioex) -{ - ioex_init(ioex); } static void board_tcpc_init(void) @@ -282,24 +145,13 @@ static void board_tcpc_init(void) if (!system_jumped_late()) { board_reset_pd_mcu(); - /* - * These IO expander pins are implemented using the - * C0/C2 TCPC, so they must be set up after the TCPC has - * been taken out of reset. - */ - enable_ioex(IOEX_C0_NCT38XX); - enable_ioex(IOEX_C2_NCT38XX); } /* Enable PPC interrupts. */ gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL); /* Enable TCPC interrupts. */ gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL); - - gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); @@ -310,9 +162,6 @@ uint16_t tcpc_get_alert_status(void) if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0) status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2; - if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0) - status |= PD_STATUS_TCPC_ALERT_1; - return status; } @@ -320,10 +169,6 @@ int ppc_get_alert_status(int port) { if (port == USBC_PORT_C0) return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; - else if (port == USBC_PORT_C1) - return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; - else if (port == USBC_PORT_C2) - return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0; return 0; } @@ -333,9 +178,6 @@ void tcpc_alert_event(enum gpio_signal signal) case GPIO_USB_C0_C2_TCPC_INT_ODL: schedule_deferred_pd_interrupt(USBC_PORT_C0); break; - case GPIO_USB_C1_TCPC_INT_ODL: - schedule_deferred_pd_interrupt(USBC_PORT_C1); - break; default: break; } @@ -347,12 +189,6 @@ void bc12_interrupt(enum gpio_signal signal) case GPIO_USB_C0_BC12_INT_ODL: usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); break; - case GPIO_USB_C1_BC12_INT_ODL: - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - break; - case GPIO_USB_C2_BC12_INT_ODL: - usb_charger_task_set_event(2, USB_CHG_EVENT_BC12); - break; default: break; } @@ -364,12 +200,6 @@ void ppc_interrupt(enum gpio_signal signal) case GPIO_USB_C0_PPC_INT_ODL: syv682x_interrupt(USBC_PORT_C0); break; - case GPIO_USB_C1_PPC_INT_ODL: - syv682x_interrupt(USBC_PORT_C1); - break; - case GPIO_USB_C2_PPC_INT_ODL: - syv682x_interrupt(USBC_PORT_C2); - break; default: break; } diff --git a/board/kuldax/usbc_config.h b/board/kuldax/usbc_config.h index 1ccb5f0a71..b294eb69c8 100644 --- a/board/kuldax/usbc_config.h +++ b/board/kuldax/usbc_config.h @@ -8,12 +8,10 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 3 +#define CONFIG_USB_PD_PORT_MAX_COUNT 1 enum usbc_port { USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_C2, USBC_PORT_COUNT }; -- cgit v1.2.1 From c2f268959ce50567f1f1238c0756dd936bd7eb14 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:58 -0600 Subject: chip/mt_scp/rv32i_common/ipi_table.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I834fc70868c18230aa2ef011cee5da6be07865ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729361 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/ipi_table.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/chip/mt_scp/rv32i_common/ipi_table.c b/chip/mt_scp/rv32i_common/ipi_table.c index 8fe3f1e598..b27f51c801 100644 --- a/chip/mt_scp/rv32i_common/ipi_table.c +++ b/chip/mt_scp/rv32i_common/ipi_table.c @@ -17,21 +17,24 @@ typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); #define ipi_arguments int32_t id, void *data, uint32_t len #if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } +void ipi_handler_undefined(ipi_arguments) +{ +} const int ipi_wakeup_undefined; #define table(type, name, x) x -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ +#define ipi_x_func(suffix, args, number) \ + extern void \ + __attribute__((used, weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ ipi_##number##_##suffix(args); #define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; + extern int __attribute__((weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ + ipi_##number##_##suffix; #endif /* PASS == 1 */ @@ -41,11 +44,11 @@ const int ipi_wakeup_undefined; #undef ipi_x_func #undef ipi_x_var -#define table(type, name, x) \ - type const name[] \ - __attribute__((aligned(4), used, section(".rodata.ipi"))) = {x} +#define table(type, name, x) \ + type const name[] __attribute__((aligned(4), used, \ + section(".rodata.ipi"))) = { x } -#define ipi_x_var(suffix, number) \ +#define ipi_x_var(suffix, number) \ [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, #define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) -- cgit v1.2.1 From a0a743b35f77332526cd4dd5561243345037b3b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:05 -0600 Subject: board/poppy/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibdb33de83c8e820746e75ae3674a5883e8806df7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727752 Reviewed-by: Jeremy Bettis --- board/poppy/battery.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/board/poppy/battery.c b/board/poppy/battery.c index 4085651cc2..923acd900f 100644 --- a/board/poppy/battery.c +++ b/board/poppy/battery.c @@ -14,14 +14,14 @@ #include "gpio.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static enum battery_present batt_pres_prev = BP_NOT_SURE; /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS -#define SB_SHUTDOWN_DATA 0x0010 -#define SB_REVIVE_DATA 0x23a7 +#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS +#define SB_SHUTDOWN_DATA 0x0010 +#define SB_REVIVE_DATA 0x23a7 #if defined(BOARD_SORAKA) || defined(BOARD_LUX) static const struct battery_info info = { @@ -86,8 +86,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* @@ -108,13 +109,13 @@ static int battery_check_disconnect(void) uint8_t data[6]; /* Check if battery charging + discharging is disabled. */ - rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return BATTERY_DISCONNECT_ERROR; - if ((data[3] & (BATTERY_DISCHARGING_DISABLED | - BATTERY_CHARGING_DISABLED)) == + if ((data[3] & + (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) == (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) return BATTERY_DISCONNECTED; -- cgit v1.2.1 From fc95b149aa62fe19101736413fd5c9acff265ac1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:07 -0600 Subject: include/vboot_hash.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1518fc42a81a9259e2285e4d3e2d9a526706f2c0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730454 Reviewed-by: Jeremy Bettis --- include/vboot_hash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/vboot_hash.h b/include/vboot_hash.h index 126872393e..46ef3b3e9d 100644 --- a/include/vboot_hash.h +++ b/include/vboot_hash.h @@ -49,4 +49,4 @@ int vboot_hash_in_progress(void); */ void vboot_hash_abort(void); -#endif /* __CROS_EC_VBOOT_HASH_H */ +#endif /* __CROS_EC_VBOOT_HASH_H */ -- cgit v1.2.1 From 17efecc6451b0cf47bd8842bac78bd10cd8ac900 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:06 -0600 Subject: test/vpd_api.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaadee91a2338f08af38af627235c56878a157181 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730319 Reviewed-by: Jeremy Bettis --- test/vpd_api.h | 31 +++++++------------------------ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/test/vpd_api.h b/test/vpd_api.h index f848138172..83675bd242 100644 --- a/test/vpd_api.h +++ b/test/vpd_api.h @@ -16,39 +16,22 @@ * voltage (set by selecting the proper Rd resistor). Any voltage below * TYPE_C_SRC_DEFAULT_THRESHOLD will not be identified as a type C charger. */ -#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */ -#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ -#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ +#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */ +#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ +#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ +enum vpd_pin { PIN_ADC, PIN_CMP, PIN_GPO }; -enum vpd_pin { - PIN_ADC, - PIN_CMP, - PIN_GPO -}; - -enum vpd_gpo { - GPO_HZ, - GPO_HIGH, - GPO_LOW -}; +enum vpd_gpo { GPO_HZ, GPO_HIGH, GPO_LOW }; enum vpd_pwr { PWR_VCONN, PWR_VBUS, }; -enum vpd_cc { - CT_OPEN, - CT_CC1, - CT_CC2 -}; +enum vpd_cc { CT_OPEN, CT_CC1, CT_CC2 }; -enum vpd_billboard { - BB_NONE, - BB_SRC, - BB_SNK -}; +enum vpd_billboard { BB_NONE, BB_SRC, BB_SNK }; struct mock_pin { enum vpd_pin cfg; -- cgit v1.2.1 From 9a1d80651f49c75ebc80dff46341a2a37168f41c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:28 -0600 Subject: test/sbs_charging_v2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3ddccec1a96b50149f77a0d0ef7985b4a013de42 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730520 Reviewed-by: Jeremy Bettis --- test/sbs_charging_v2.c | 107 ++++++++++++++++++++++--------------------------- 1 file changed, 49 insertions(+), 58 deletions(-) diff --git a/test/sbs_charging_v2.c b/test/sbs_charging_v2.c index 2f9ddee57c..cf55ca3081 100644 --- a/test/sbs_charging_v2.c +++ b/test/sbs_charging_v2.c @@ -386,7 +386,7 @@ static int test_deep_charge_battery(void) state_v2 = charge_get_state_v2(); TEST_ASSERT(state_v2 == ST_IDLE); - /* recovery from a low voltage. */ + /* recovery from a low voltage. */ sb_write(SB_VOLTAGE, (bat_info->voltage_normal)); wait_charging_state(); state_v2 = charge_get_state_v2(); @@ -533,9 +533,8 @@ static int test_hc_charge_state(void) /* Get the state */ memset(&resp, 0, sizeof(resp)); params.cmd = CHARGE_STATE_CMD_GET_STATE; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(resp.get_state.ac); TEST_ASSERT(resp.get_state.chg_voltage); @@ -545,14 +544,13 @@ static int test_hc_charge_state(void) /* Check all the params */ for (i = 0; i < CS_NUM_BASE_PARAMS; i++) { - /* Read it */ memset(&resp, 0, sizeof(resp)); params.cmd = CHARGE_STATE_CMD_GET_PARAM; params.get_param.param = i; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, + sizeof(resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); if (i != CS_PARAM_LIMIT_POWER) TEST_ASSERT(resp.get_param.value); @@ -565,7 +563,7 @@ static int test_hc_charge_state(void) case CS_PARAM_CHG_VOLTAGE: case CS_PARAM_CHG_CURRENT: case CS_PARAM_CHG_INPUT_CURRENT: - tmp -= 128; /* Should be valid delta */ + tmp -= 128; /* Should be valid delta */ break; case CS_PARAM_CHG_STATUS: case CS_PARAM_LIMIT_POWER: @@ -578,9 +576,9 @@ static int test_hc_charge_state(void) params.cmd = CHARGE_STATE_CMD_SET_PARAM; params.set_param.param = i; params.set_param.value = tmp; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, + sizeof(resp)); if (i == CS_PARAM_CHG_STATUS || i == CS_PARAM_LIMIT_POWER) TEST_ASSERT(rv == EC_RES_ACCESS_DENIED); else @@ -593,9 +591,9 @@ static int test_hc_charge_state(void) memset(&resp, 0, sizeof(resp)); params.cmd = CHARGE_STATE_CMD_GET_PARAM; params.get_param.param = i; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, + sizeof(resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(resp.get_param.value == tmp); } @@ -605,17 +603,15 @@ static int test_hc_charge_state(void) memset(&resp, 0, sizeof(resp)); params.cmd = CHARGE_STATE_CMD_GET_PARAM; params.get_param.param = CS_PARAM_CUSTOM_PROFILE_MIN; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(resp.get_param.value == meh); params.cmd = CHARGE_STATE_CMD_SET_PARAM; params.set_param.param = CS_PARAM_CUSTOM_PROFILE_MIN; params.set_param.value = 0xc0def00d; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); /* Allow the change to take effect */ state = wait_charging_state(); @@ -624,23 +620,20 @@ static int test_hc_charge_state(void) /* param out of range */ params.cmd = CHARGE_STATE_CMD_GET_PARAM; params.get_param.param = CS_NUM_BASE_PARAMS; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_INVALID_PARAM); params.cmd = CHARGE_STATE_CMD_SET_PARAM; params.set_param.param = CS_NUM_BASE_PARAMS; - params.set_param.value = 0x1000; /* random value */ - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + params.set_param.value = 0x1000; /* random value */ + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_INVALID_PARAM); /* command out of range */ params.cmd = CHARGE_STATE_NUM_CMDS; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); TEST_ASSERT(rv == EC_RES_INVALID_PARAM); /* @@ -665,40 +658,38 @@ static int test_hc_current_limit(void) /* See what current the charger is delivering */ cs_params.cmd = CHARGE_STATE_CMD_GET_STATE; - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - &cs_params, sizeof(cs_params), - &cs_resp, sizeof(cs_resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params, + sizeof(cs_params), &cs_resp, + sizeof(cs_resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); norm_current = cs_resp.get_state.chg_current; /* Lower it a bit */ lower_current = norm_current - 256; cl_params.limit = lower_current; - rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, - &cl_params, sizeof(cl_params), - 0, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params, + sizeof(cl_params), 0, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); wait_charging_state(); /* See that it's changed */ - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - &cs_params, sizeof(cs_params), - &cs_resp, sizeof(cs_resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params, + sizeof(cs_params), &cs_resp, + sizeof(cs_resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(lower_current == cs_resp.get_state.chg_current); /* Remove the limit */ cl_params.limit = -1U; - rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, - &cl_params, sizeof(cl_params), - 0, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CURRENT_LIMIT, 0, &cl_params, + sizeof(cl_params), 0, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); wait_charging_state(); /* See that it's back */ - rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, - &cs_params, sizeof(cs_params), - &cs_resp, sizeof(cs_resp)); + rv = test_send_host_command(EC_CMD_CHARGE_STATE, 0, &cs_params, + sizeof(cs_params), &cs_resp, + sizeof(cs_resp)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(norm_current == cs_resp.get_state.chg_current); @@ -789,13 +780,13 @@ static int test_battery_sustainer(void) p.mode = CHARGE_CONTROL_NORMAL; p.sustain_soc.lower = 79; p.sustain_soc.upper = 80; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), NULL, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), + NULL, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); p.cmd = EC_CHARGE_CONTROL_CMD_GET; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), &r, sizeof(r)); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), &r, + sizeof(r)); TEST_ASSERT(rv == EC_RES_SUCCESS); TEST_ASSERT(r.sustain_soc.lower == 79); TEST_ASSERT(r.sustain_soc.upper == 80); @@ -854,8 +845,8 @@ static int test_battery_sustainer(void) p.mode = CHARGE_CONTROL_NORMAL; p.sustain_soc.lower = 79; p.sustain_soc.upper = 80; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), NULL, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), + NULL, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); wait_charging_state(); TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE); @@ -876,8 +867,8 @@ static int test_battery_sustainer(void) p.mode = CHARGE_CONTROL_NORMAL; p.sustain_soc.lower = 79; p.sustain_soc.upper = 80; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), NULL, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), + NULL, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); wait_charging_state(); TEST_ASSERT(get_chg_ctrl_mode() == CHARGE_CONTROL_DISCHARGE); @@ -898,8 +889,8 @@ static int test_battery_sustainer_discharge_idle(void) p.mode = CHARGE_CONTROL_NORMAL; p.sustain_soc.lower = 80; p.sustain_soc.upper = 80; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), NULL, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), + NULL, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); /* Check mode transition as the SoC changes. */ @@ -939,8 +930,8 @@ static int test_battery_sustainer_discharge_idle(void) p.mode = CHARGE_CONTROL_NORMAL; p.sustain_soc.lower = -1; p.sustain_soc.upper = -1; - rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, - &p, sizeof(p), NULL, 0); + rv = test_send_host_command(EC_CMD_CHARGE_CONTROL, 2, &p, sizeof(p), + NULL, 0); TEST_ASSERT(rv == EC_RES_SUCCESS); /* This time, mode will stay in NORMAL even when upper < SoC. */ -- cgit v1.2.1 From bcd4c3e6c6002321debd0ea9ed65a096da077d29 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:50 -0600 Subject: chip/mt_scp/rv32i_common/intc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec8ef6e074f3796f09b63d88c16d63756b0dfb7e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729370 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/intc.c | 406 ++++++++++++++++++++-------------------- 1 file changed, 203 insertions(+), 203 deletions(-) diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c index 606f487ed5..06b0b4ca1c 100644 --- a/chip/mt_scp/rv32i_common/intc.c +++ b/chip/mt_scp/rv32i_common/intc.c @@ -39,114 +39,114 @@ static struct { uint8_t group; } irqs[SCP_INTC_IRQ_COUNT] = { /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, + [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, + [SCP_IRQ_SPM] = { INTC_GRP_0 }, + [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_EINT] = { INTC_GRP_0 }, + [SCP_IRQ_PMIC] = { INTC_GRP_0 }, /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, + [SCP_IRQ_I2C0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, + [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, + [SCP_IRQ_VOW] = { INTC_GRP_0 }, + [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, + [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, + [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_GDMA] = { INTC_GRP_0 }, + [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, + [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, + [SCP_IRQ_ADSP] = { INTC_GRP_0 }, /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, + [SCP_IRQ_SPI0] = { INTC_GRP_0 }, + [SCP_IRQ_SPI1] = { INTC_GRP_0 }, + [SCP_IRQ_SPI2] = { INTC_GRP_0 }, /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF0] = { INTC_GRP_0 }, - [SCP_IRQ_CCIF1] = { INTC_GRP_0 }, + [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_DBG] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF0] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF1] = { INTC_GRP_0 }, /* 36 */ - [SCP_IRQ_CCIF2] = { INTC_GRP_0 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_USB0] = { INTC_GRP_0 }, - [SCP_IRQ_USB1] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF2] = { INTC_GRP_0 }, + [SCP_IRQ_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_USB0] = { INTC_GRP_0 }, + [SCP_IRQ_USB1] = { INTC_GRP_0 }, /* 40 */ - [SCP_IRQ_DPMAIF] = { INTC_GRP_0 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_DPMAIF] = { INTC_GRP_0 }, + [SCP_IRQ_INFRA] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, + [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, + [SCP_IRQ_MET0] = { INTC_GRP_0 }, + [SCP_IRQ_MET1] = { INTC_GRP_0 }, + [SCP_IRQ_MET2] = { INTC_GRP_0 }, + [SCP_IRQ_MET3] = { INTC_GRP_0 }, /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 }, - [SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 }, + [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK1] = { INTC_GRP_0 }, + [SCP_IRQ_MAD_DATAIN] = { INTC_GRP_0 }, /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, /* 72 */ /* 76 */ - [SCP_IRQ_I2C1_2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C2] = { INTC_GRP_0 }, /* 80 */ - [SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 }, - [SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 }, - [SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 }, + [SCP_IRQ_AUD2AUDIODSP] = { INTC_GRP_0 }, + [SCP_IRQ_AUD2AUDIODSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_A2DPOL] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_BTCVSD] = { INTC_GRP_0 }, /* 84 */ - [SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 }, - [SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 }, - [SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_CONN2ADSP_BLEISO] = { INTC_GRP_0 }, + [SCP_IRQ_PCIE2ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_APU2ADSP_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_APU2ADSP_MBOX] = { INTC_GRP_0 }, /* 88 */ - [SCP_IRQ_CCIF3] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 }, - [SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 }, + [SCP_IRQ_CCIF3] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA1] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA2] = { INTC_GRP_0 }, /* 92 */ - [SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 }, + [SCP_IRQ_I2C_DMA3] = { INTC_GRP_0 }, }; BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); #endif @@ -156,153 +156,153 @@ static struct { uint8_t group; } irqs[SCP_INTC_IRQ_COUNT] = { /* 0 */ - [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, - [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN0] = { INTC_GRP_7 }, + [SCP_IRQ_GIPC_IN1] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN3] = { INTC_GRP_0 }, /* 4 */ - [SCP_IRQ_SPM] = { INTC_GRP_0 }, - [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_EINT] = { INTC_GRP_0 }, - [SCP_IRQ_PMIC] = { INTC_GRP_0 }, + [SCP_IRQ_SPM] = { INTC_GRP_0 }, + [SCP_IRQ_AP_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_EINT] = { INTC_GRP_0 }, + [SCP_IRQ_PMIC] = { INTC_GRP_0 }, /* 8 */ - [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, - [SCP_IRQ_I2C0] = { INTC_GRP_0 }, - [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_TX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_TX] = { INTC_GRP_12 }, + [SCP_IRQ_I2C0] = { INTC_GRP_0 }, + [SCP_IRQ_I2C1_0] = { INTC_GRP_0 }, /* 12 */ - [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, - [SCP_IRQ_VOW] = { INTC_GRP_0 }, - [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, + [SCP_IRQ_BUS_DBG_TRACKER] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL] = { INTC_GRP_0 }, + [SCP_IRQ_VOW] = { INTC_GRP_0 }, + [SCP_IRQ_TIMER0] = { INTC_GRP_6 }, /* 16 */ - [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, - [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER1] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER2] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER3] = { INTC_GRP_6 }, + [SCP_IRQ_TIMER4] = { INTC_GRP_6 }, /* 20 */ - [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, - [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, - [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, - [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, + [SCP_IRQ_TIMER5] = { INTC_GRP_6 }, + [SCP_IRQ_OS_TIMER] = { INTC_GRP_0 }, + [SCP_IRQ_UART0_RX] = { INTC_GRP_12 }, + [SCP_IRQ_UART1_RX] = { INTC_GRP_12 }, /* 24 */ - [SCP_IRQ_GDMA] = { INTC_GRP_0 }, - [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, - [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, - [SCP_IRQ_ADSP] = { INTC_GRP_0 }, + [SCP_IRQ_GDMA] = { INTC_GRP_0 }, + [SCP_IRQ_AUDIO] = { INTC_GRP_0 }, + [SCP_IRQ_MD_DSP] = { INTC_GRP_0 }, + [SCP_IRQ_ADSP] = { INTC_GRP_0 }, /* 28 */ - [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, - [SCP_IRQ_SPI0] = { INTC_GRP_0 }, - [SCP_IRQ_SPI1] = { INTC_GRP_0 }, - [SCP_IRQ_SPI2] = { INTC_GRP_0 }, + [SCP_IRQ_CPU_TICK] = { INTC_GRP_0 }, + [SCP_IRQ_SPI0] = { INTC_GRP_0 }, + [SCP_IRQ_SPI1] = { INTC_GRP_0 }, + [SCP_IRQ_SPI2] = { INTC_GRP_0 }, /* 32 */ - [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, - [SCP_IRQ_DBG] = { INTC_GRP_0 }, - [SCP_IRQ_GCE] = { INTC_GRP_0 }, - [SCP_IRQ_MDP_GCE] = { INTC_GRP_0 }, + [SCP_IRQ_NEW_INFRA_SYS_CIRQ] = { INTC_GRP_0 }, + [SCP_IRQ_DBG] = { INTC_GRP_0 }, + [SCP_IRQ_GCE] = { INTC_GRP_0 }, + [SCP_IRQ_MDP_GCE] = { INTC_GRP_0 }, /* 36 */ - [SCP_IRQ_VDEC] = { INTC_GRP_8 }, - [SCP_IRQ_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_VDEC1] = { INTC_GRP_8 }, + [SCP_IRQ_VDEC] = { INTC_GRP_8 }, + [SCP_IRQ_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC_LAT] = { INTC_GRP_8 }, + [SCP_IRQ_VDEC1] = { INTC_GRP_8 }, /* 40 */ - [SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 }, - [SCP_IRQ_INFRA] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, - [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC1_LAT] = { INTC_GRP_8 }, + [SCP_IRQ_INFRA] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL_CORE] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2_CORE] = { INTC_GRP_0 }, /* 44 */ - [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, - [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, - [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, - [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_CLK_CTRL2] = { INTC_GRP_0 }, + [SCP_IRQ_GIPC_IN4] = { INTC_GRP_0 }, + [SCP_IRQ_PERIBUS_TIMEOUT] = { INTC_GRP_0 }, + [SCP_IRQ_INFRABUS_TIMEOUT] = { INTC_GRP_0 }, /* 48 */ - [SCP_IRQ_MET0] = { INTC_GRP_0 }, - [SCP_IRQ_MET1] = { INTC_GRP_0 }, - [SCP_IRQ_MET2] = { INTC_GRP_0 }, - [SCP_IRQ_MET3] = { INTC_GRP_0 }, + [SCP_IRQ_MET0] = { INTC_GRP_0 }, + [SCP_IRQ_MET1] = { INTC_GRP_0 }, + [SCP_IRQ_MET2] = { INTC_GRP_0 }, + [SCP_IRQ_MET3] = { INTC_GRP_0 }, /* 52 */ - [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, - [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 }, - [SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 }, + [SCP_IRQ_AP_WDT] = { INTC_GRP_0 }, + [SCP_IRQ_L2TCM_SEC_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_VDEC_INT_LINE_CNT] = { INTC_GRP_0 }, + [SCP_IRQ_VOW_DATAIN] = { INTC_GRP_0 }, /* 56 */ - [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_VENC] = { INTC_GRP_8 }, - [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C0_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C1_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_VENC] = { INTC_GRP_8 }, + [SCP_IRQ_APU_ENGINE] = { INTC_GRP_0 }, /* 60 */ - [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, - [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX0] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX1] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX2] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX3] = { INTC_GRP_0 }, /* 64 */ - [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, - [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_MBOX4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_CLK_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_BUS_REQ] = { INTC_GRP_0 }, + [SCP_IRQ_APSRC_REQ] = { INTC_GRP_0 }, /* 68 */ - [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, - [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, + [SCP_IRQ_APU_MBOX] = { INTC_GRP_0 }, + [SCP_IRQ_DEVAPC_SECURE_VIO] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA0] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA1] = { INTC_GRP_0 }, /* 72 */ - [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, - [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA2] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA3] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA4] = { INTC_GRP_0 }, + [SCP_IRQ_APDMA5] = { INTC_GRP_0 }, /* 76 */ - [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, - [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA0_1] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_PM_DVI_SQH] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_RESERVED] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_0] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_1] = { INTC_GRP_0 }, /* 80 */ - [SCP_IRQ_NNA0_2] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_0] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_1] = { INTC_GRP_0 }, - [SCP_IRQ_NNA1_2] = { INTC_GRP_0 }, + [SCP_IRQ_NNA0_2] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_0] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_1] = { INTC_GRP_0 }, + [SCP_IRQ_NNA1_2] = { INTC_GRP_0 }, /* 84 */ - [SCP_IRQ_JPEGENC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 }, - [SCP_IRQ_VENC_C1] = { INTC_GRP_8 }, + [SCP_IRQ_JPEGENC] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC_C2] = { INTC_GRP_0 }, + [SCP_IRQ_VENC_C1] = { INTC_GRP_8 }, /* 88 */ - [SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 }, - [SCP_IRQ_HDMITX] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGENC_C1] = { INTC_GRP_0 }, + [SCP_IRQ_JPEGDEC_C1] = { INTC_GRP_0 }, + [SCP_IRQ_HDMITX] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI2] = { INTC_GRP_0 }, /* 92 */ - [SCP_IRQ_EARC] = { INTC_GRP_0 }, - [SCP_IRQ_CEC] = { INTC_GRP_0 }, - [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, - [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, + [SCP_IRQ_EARC] = { INTC_GRP_0 }, + [SCP_IRQ_CEC] = { INTC_GRP_0 }, + [SCP_IRQ_HDMI_DEV_DET] = { INTC_GRP_0 }, + [SCP_IRQ_HDMIRX_OUT_ARM_PHY] = { INTC_GRP_0 }, /* 96 */ - [SCP_IRQ_I2C2] = { INTC_GRP_0 }, - [SCP_IRQ_I2C3] = { INTC_GRP_0 }, - [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, - [SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I2C2] = { INTC_GRP_0 }, + [SCP_IRQ_I2C3] = { INTC_GRP_0 }, + [SCP_IRQ_I3C2_IBI_WAKE] = { INTC_GRP_0 }, + [SCP_IRQ_I3C3_IBI_WAKE] = { INTC_GRP_0 }, /* 100 */ - [SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_0] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_1] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_2] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_3] = { INTC_GRP_0 }, /* 104 */ - [SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 }, - [SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_4] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_5] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_6] = { INTC_GRP_0 }, + [SCP_IRQ_SYS_I2C_7] = { INTC_GRP_0 }, /* 108 */ - [SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 }, - [SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_0] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_1] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_3] = { INTC_GRP_0 }, /* 112 */ - [SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 }, - [SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 }, + [SCP_IRQ_DISP2ADSP_4] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_0] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_1] = { INTC_GRP_0 }, + [SCP_IRQ_VDO1_DISP_MON2ADSP_2] = { INTC_GRP_0 }, /* 116 */ - [SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 }, - [SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 }, + [SCP_IRQ_GCE1_SECURE] = { INTC_GRP_0 }, + [SCP_IRQ_GCE_SECURE] = { INTC_GRP_0 }, }; BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT); #endif -- cgit v1.2.1 From 1dae7dc59772946293d02e794ba356ce8385eaf0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:14 -0600 Subject: board/bloog/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic632a49ab994d32aecf648680f0f3d636501d6c9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728060 Reviewed-by: Jeremy Bettis --- board/bloog/board.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/board/bloog/board.h b/board/bloog/board.h index d32fb43578..f9b6b2a2e2 100644 --- a/board/bloog/board.h +++ b/board/bloog/board.h @@ -27,8 +27,8 @@ #define CONFIG_LED_COMMON /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) @@ -59,10 +59,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -73,18 +73,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum battery_type { BATTERY_DYNAPACK_COS, -- cgit v1.2.1 From c40e5146424bcc10bf9076918b48f34f7ee3970f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:07 -0600 Subject: common/bluetooth_le.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I524c89ffe01be4be1100219cac195920fc8ba659 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729609 Reviewed-by: Jeremy Bettis --- common/bluetooth_le.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/common/bluetooth_le.c b/common/bluetooth_le.c index c148ef8285..4dc1aade45 100644 --- a/common/bluetooth_le.c +++ b/common/bluetooth_le.c @@ -7,7 +7,7 @@ #include "util.h" #include "console.h" -#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LE, format, ##args) /* * Convert from BLE Channel to frequency @@ -15,11 +15,11 @@ * Bluetooth 4.1 Vol 6 pg 36 4.1 Table 1.1 */ -#define CHAN_0_MHZ 2404 -#define CHAN_11_MHZ 2428 -#define CHAN_37_MHZ 2402 -#define CHAN_38_MHZ 2426 -#define CHAN_39_MHZ 2480 +#define CHAN_0_MHZ 2404 +#define CHAN_11_MHZ 2428 +#define CHAN_37_MHZ 2402 +#define CHAN_38_MHZ 2426 +#define CHAN_39_MHZ 2480 int chan2freq(int channel) { @@ -72,11 +72,11 @@ uint8_t get_next_data_channel(struct remapping_table *rt) /* Check if the channel is mapped */ if (rt->map[rt->last_unmapped_channel / 8] & - (1 << (rt->last_unmapped_channel % 8))) + (1 << (rt->last_unmapped_channel % 8))) return rt->last_unmapped_channel; else - return rt->remapping_index - [rt->last_unmapped_channel % rt->num_used_channels]; + return rt->remapping_index[rt->last_unmapped_channel % + rt->num_used_channels]; } /* BLE 4.1 Vol 3 Part C 11 */ @@ -85,27 +85,27 @@ uint8_t get_next_data_channel(struct remapping_table *rt) uint8_t *pack_adv(uint8_t *dest, int length, int type, const uint8_t *data) { /* Add the structure length */ - dest[0] = (uint8_t)length+1; + dest[0] = (uint8_t)length + 1; /* Add the structure type */ dest[1] = (uint8_t)type; /* Add the data */ memcpy(&dest[2], data, length); /* Return a pointer to the next structure */ - return &dest[2+length]; + return &dest[2 + length]; } uint8_t *pack_adv_int(uint8_t *dest, int length, int type, int data) { /* Add the structure length */ - dest[0] = (uint8_t)length+1; + dest[0] = (uint8_t)length + 1; /* Add the structure type */ dest[1] = (uint8_t)type; /* Add the data */ memcpy(&dest[2], &data, length); /* Return a pointer to the next structure */ - return &dest[2+length]; + return &dest[2 + length]; } uint8_t *pack_adv_addr(uint8_t *dest, uint64_t addr) @@ -160,19 +160,19 @@ void dump_ble_packet(struct ble_pdu *ble_p) int curr_offs; if (ble_p->header_type_adv) { - CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n", - ble_p, ble_p->header.adv.type, ble_p->header.adv.length, + CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n", ble_p, + ble_p->header.adv.type, ble_p->header.adv.length, (ble_p->header.adv.txaddr ? " TXADDR" : ""), (ble_p->header.adv.rxaddr ? " RXADDR" : "")); curr_offs = 0; if (ble_p->header.adv.type == - BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) { + BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ) { dump_ble_addr(ble_p->payload, "ScanA"); curr_offs += BLUETOOTH_ADDR_OCTETS; } else if (ble_p->header.adv.type == - BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) { + BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ) { dump_ble_addr(ble_p->payload, "InitA"); curr_offs += BLUETOOTH_ADDR_OCTETS; } -- cgit v1.2.1 From 8477bbe1a6af9967bfbc97ecc37bf079984cbc72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:41 -0600 Subject: chip/stm32/flash-f.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id329e3b395df3c8eb1a3c76d8faea61fba61aa36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729494 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-f.c | 60 +++++++++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index 9e35a2c689..edbb1fd0db 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -20,8 +20,8 @@ #include "util.h" #include "watchdog.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* * Approximate number of CPU cycles per iteration of the loop when polling @@ -49,14 +49,15 @@ /* Forward declarations */ #if defined(CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE) -static enum flash_rdp_level flash_physical_get_rdp_level(void); + static enum flash_rdp_level + flash_physical_get_rdp_level(void); static int flash_physical_set_rdp_level(enum flash_rdp_level level); #endif /* CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE */ static inline int calculate_flash_timeout(void) { - return (FLASH_WRITE_TIMEOUT_US * - (clock_get_freq() / SECOND) / CYCLE_PER_FLASH_LOOP); + return (FLASH_WRITE_TIMEOUT_US * (clock_get_freq() / SECOND) / + CYCLE_PER_FLASH_LOOP); } static int wait_busy(void) @@ -67,7 +68,6 @@ static int wait_busy(void) return (timeout > 0) ? EC_SUCCESS : EC_ERROR_TIMEOUT; } - void unlock_flash_control_register(void) { STM32_FLASH_KEYR = FLASH_KEYR_KEY1; @@ -134,7 +134,7 @@ bool flash_control_register_locked(void) * We at least unlock the control register lock. * We may also unlock other locks. */ -enum extra_lock_type { +enum extra_lock_type { NO_EXTRA_LOCK = 0, OPT_LOCK = 1, }; @@ -382,9 +382,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) watchdog_reload(); /* wait to be ready */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); + for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); i++) ; @@ -392,9 +390,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) *address++ = quantum; /* Wait for writes to complete */ - for (i = 0; - (STM32_FLASH_SR & FLASH_SR_BUSY) && - (i < timeout); + for (i = 0; (STM32_FLASH_SR & FLASH_SR_BUSY) && (i < timeout); i++) ; @@ -429,7 +425,7 @@ int crec_flash_physical_erase(int offset, int size) int sector = crec_flash_bank_index(offset); /* we take advantage of sector_size == erase_size */ if ((sector < 0) || (crec_flash_bank_index(offset + size) < 0)) - return EC_ERROR_INVAL; /* Invalid range */ + return EC_ERROR_INVAL; /* Invalid range */ #endif if (unlock(NO_EXTRA_LOCK) != EC_SUCCESS) @@ -459,7 +455,7 @@ int crec_flash_physical_erase(int offset, int size) #ifdef CHIP_FAMILY_STM32F4 /* select page to erase */ STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_SNB_MASK) | - (sector << STM32_FLASH_CR_SNB_OFFSET); + (sector << STM32_FLASH_CR_SNB_OFFSET); #else /* select page to erase */ STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; @@ -472,7 +468,7 @@ int crec_flash_physical_erase(int offset, int size) watchdog_reload(); while ((STM32_FLASH_SR & FLASH_SR_BUSY) && (get_time().val < deadline.val)) { - usleep(timeout_us/100); + usleep(timeout_us / 100); } if (STM32_FLASH_SR & FLASH_SR_BUSY) { res = EC_ERROR_TIMEOUT; @@ -487,7 +483,7 @@ int crec_flash_physical_erase(int offset, int size) res = EC_ERROR_UNKNOWN; goto exit_er; } -next_sector: + next_sector: size -= sector_size; offset += sector_size; #ifdef CHIP_FAMILY_STM32F4 @@ -540,8 +536,7 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) original_val = val = STM32_OPTB_WP & STM32_OPTB_nWRP_ALL; - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; + for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS; block++) { int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; @@ -573,10 +568,10 @@ static void unprotect_all_blocks(void) write_optb(STM32_FLASH_nWRP_ALL, STM32_FLASH_nWRP_ALL); } -#else /* CHIP_FAMILY_STM32F4 */ +#else /* CHIP_FAMILY_STM32F4 */ static int flash_physical_get_protect_at_boot(int block) { - uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8)); + uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block / 8)); return (!(val & (1 << (block % 8)))) ? 1 : 0; } @@ -589,11 +584,10 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) for (i = 0; i < 4; ++i) original_val[i] = val[i] = read_optb(i * 2 + 8); - for (block = WP_BANK_OFFSET; - block < WP_BANK_OFFSET + PHYSICAL_BANKS; + for (block = WP_BANK_OFFSET; block < WP_BANK_OFFSET + PHYSICAL_BANKS; block++) { int protect = new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT; - int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4; + int byte_off = STM32_OPTB_WRP_OFF(block / 8) / 2 - 4; if (block >= WP_BANK_OFFSET && block < WP_BANK_OFFSET + WP_BANK_COUNT) @@ -601,7 +595,8 @@ int crec_flash_physical_protect_at_boot(uint32_t new_flags) #ifdef CONFIG_ROLLBACK else if (block >= ROLLBACK_BANK_OFFSET && block < ROLLBACK_BANK_OFFSET + ROLLBACK_BANK_COUNT) - protect |= new_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; + protect |= new_flags & + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT; #endif #ifdef CONFIG_FLASH_PROTECT_RW else @@ -729,13 +724,12 @@ int crec_flash_pre_init(void) uint32_t prot_flags = crec_flash_get_protect(); int need_reset = 0; - #ifdef CHIP_FAMILY_STM32F4 unlock(NO_EXTRA_LOCK); /* Set the proper write size */ STM32_FLASH_CR = (STM32_FLASH_CR & ~STM32_FLASH_CR_PSIZE_MASK) | - (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) << - STM32_FLASH_CR_PSIZE_OFFSET; + (31 - __builtin_clz(CONFIG_FLASH_WRITE_SIZE)) + << STM32_FLASH_CR_PSIZE_OFFSET; lock(); #endif if (crec_flash_physical_restore_state()) @@ -776,8 +770,8 @@ int crec_flash_pre_init(void) * to the check above. One of them should be able to * go away. */ - crec_flash_protect_at_boot( - prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT); + crec_flash_protect_at_boot(prot_flags & + EC_FLASH_PROTECT_RO_AT_BOOT); need_reset = 1; } } else { @@ -792,7 +786,7 @@ int crec_flash_pre_init(void) } if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ALL_AT_BOOT) && + EC_FLASH_PROTECT_ALL_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ALL_NOW))) { /* @@ -808,7 +802,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_FLASH_PROTECT_RW if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_RW_AT_BOOT) && + EC_FLASH_PROTECT_RW_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_RW_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_RW_NOW))) { /* RW_AT_BOOT and RW_NOW do not match. */ @@ -818,7 +812,7 @@ int crec_flash_pre_init(void) #ifdef CONFIG_ROLLBACK if ((crec_flash_physical_get_valid_flags() & - EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) && (!!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_AT_BOOT) != !!(prot_flags & EC_FLASH_PROTECT_ROLLBACK_NOW))) { /* ROLLBACK_AT_BOOT and ROLLBACK_NOW do not match. */ -- cgit v1.2.1 From 6f90db19d8c085e40a8a798d788365c7d60477e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:42 -0600 Subject: baseboard/dedede/cbi_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ef76b0f31f5fe9561fa35ac8701fdaece0ab5cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727873 Reviewed-by: Jeremy Bettis --- baseboard/dedede/cbi_fw_config.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/baseboard/dedede/cbi_fw_config.h b/baseboard/dedede/cbi_fw_config.h index 90cc5e5fbe..5205be7b2d 100644 --- a/baseboard/dedede/cbi_fw_config.h +++ b/baseboard/dedede/cbi_fw_config.h @@ -24,8 +24,8 @@ enum fw_config_db { DB_1C, DB_1A_HDMI_LTE, }; -#define FW_CONFIG_DB_OFFSET 0 -#define FW_CONFIG_DB_MASK GENMASK(3, 0) +#define FW_CONFIG_DB_OFFSET 0 +#define FW_CONFIG_DB_MASK GENMASK(3, 0) /* * Stylus (1 bit) @@ -34,8 +34,8 @@ enum fw_config_stylus { STYLUS_ABSENT = 0, STYLUS_PRESENT = 1, }; -#define FW_CONFIG_STYLUS_OFFSET 4 -#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4) +#define FW_CONFIG_STYLUS_OFFSET 4 +#define FW_CONFIG_STYLUS_MASK GENMASK(4, 4) /* * Keyboard backlight (1 bit) @@ -44,8 +44,8 @@ enum fw_config_kblight_type { KB_BL_ABSENT = 0, KB_BL_PRESENT = 1, }; -#define FW_CONFIG_KB_BL_OFFSET 8 -#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) +#define FW_CONFIG_KB_BL_OFFSET 8 +#define FW_CONFIG_KB_BL_MASK GENMASK(8, 8) /* * Keyboard numeric pad (1 bit) @@ -54,8 +54,8 @@ enum fw_config_numeric_pad_type { NUMERIC_PAD_ABSENT = 0, NUMERIC_PAD_PRESENT = 1, }; -#define FW_CONFIG_KB_NUMPAD_OFFSET 9 -#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) +#define FW_CONFIG_KB_NUMPAD_OFFSET 9 +#define FW_CONFIG_KB_NUMPAD_MASK GENMASK(9, 9) /* * Tablet Mode (1 bit) @@ -64,11 +64,11 @@ enum fw_config_tablet_mode_type { TABLET_MODE_ABSENT = 0, TABLET_MODE_PRESENT = 1, }; -#define FW_CONFIG_TABLET_MODE_OFFSET 10 -#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) +#define FW_CONFIG_TABLET_MODE_OFFSET 10 +#define FW_CONFIG_TABLET_MODE_MASK GENMASK(10, 10) -#define FW_CONFIG_KB_LAYOUT_OFFSET 12 -#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) +#define FW_CONFIG_KB_LAYOUT_OFFSET 12 +#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(13, 12) /* * Hdmi (1 bit) @@ -77,8 +77,8 @@ enum fw_config_hdmi_type { HDMI_ABSENT = 0, HDMI_PRESENT = 1, }; -#define FW_CONFIG_HDMI_OFFSET 17 -#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) +#define FW_CONFIG_HDMI_OFFSET 17 +#define FW_CONFIG_HDMI_MASK GENMASK(17, 17) enum fw_config_db get_cbi_fw_config_db(void); enum fw_config_stylus get_cbi_fw_config_stylus(void); -- cgit v1.2.1 From ce3d37dd9c9e6059e9f3e89a54c97e2a2172aabe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:19 -0600 Subject: common/usb_console_stream.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id2df1387cf6537590c4eda195d3bfb1052c87a88 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729767 Reviewed-by: Jeremy Bettis --- common/usb_console_stream.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/common/usb_console_stream.c b/common/usb_console_stream.c index 13dd7f8264..3a743fbdb2 100644 --- a/common/usb_console_stream.c +++ b/common/usb_console_stream.c @@ -25,13 +25,12 @@ /* Console output macro */ #define USB_CONSOLE_TIMEOUT_US (30 * MSEC) -#define QUEUE_SIZE_USB_TX CONFIG_USB_CONSOLE_TX_BUF_SIZE -#define QUEUE_SIZE_USB_RX USB_MAX_PACKET_SIZE +#define QUEUE_SIZE_USB_TX CONFIG_USB_CONSOLE_TX_BUF_SIZE +#define QUEUE_SIZE_USB_RX USB_MAX_PACKET_SIZE static void usb_console_wr(struct queue_policy const *policy, size_t count); static void uart_console_rd(struct queue_policy const *policy, size_t count); - static int last_tx_ok = 1; /* @@ -52,24 +51,19 @@ static int is_readonly = 1; * usb-stream.c. */ static struct queue_policy const usb_console_policy = { - .add = usb_console_wr, + .add = usb_console_wr, .remove = uart_console_rd, }; static struct queue const tx_q = QUEUE_NULL(QUEUE_SIZE_USB_TX, uint8_t); -static struct queue const rx_q = QUEUE(QUEUE_SIZE_USB_RX, uint8_t, - usb_console_policy); +static struct queue const rx_q = + QUEUE(QUEUE_SIZE_USB_RX, uint8_t, usb_console_policy); struct usb_stream_config const usb_console; -USB_STREAM_CONFIG(usb_console, - USB_IFACE_CONSOLE, - USB_STR_CONSOLE_NAME, - USB_EP_CONSOLE, - USB_MAX_PACKET_SIZE, - USB_MAX_PACKET_SIZE, - rx_q, - tx_q) +USB_STREAM_CONFIG(usb_console, USB_IFACE_CONSOLE, USB_STR_CONSOLE_NAME, + USB_EP_CONSOLE, USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE, + rx_q, tx_q) static void usb_console_wr(struct queue_policy const *policy, size_t count) { @@ -185,7 +179,7 @@ int usb_puts(const char *outstr) if (!is_enabled) return EC_SUCCESS; - ret = usb_wait_console(); + ret = usb_wait_console(); if (ret) return ret; -- cgit v1.2.1 From fed26470a689b8466e03f1166067554a731fe06d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:40 -0600 Subject: power/ec_driven.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa04881d5e62fb9c9f9b09dea752b2da5a1ea7eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730463 Reviewed-by: Jeremy Bettis --- power/ec_driven.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/power/ec_driven.c b/power/ec_driven.c index 282941b941..ea0c4420ae 100644 --- a/power/ec_driven.c +++ b/power/ec_driven.c @@ -11,7 +11,7 @@ * */ -#include "chipset.h" /* This module implements chipset functions too */ +#include "chipset.h" /* This module implements chipset functions too */ #include "common.h" #include "console.h" #include "gpio.h" @@ -22,7 +22,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #define IN_SUSPEND POWER_SIGNAL_MASK(ECDRIVEN_SUSPEND_ASSERTED) -- cgit v1.2.1 From cf8ba71227172071885dcdbb177aec70667626ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:18 -0600 Subject: test/mag_cal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2d57214d937c2a945e07bd63dd60eaadfd318e3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730483 Reviewed-by: Jeremy Bettis --- test/mag_cal.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/test/mag_cal.c b/test/mag_cal.c index 8ee3b41480..40b71a2d34 100644 --- a/test/mag_cal.c +++ b/test/mag_cal.c @@ -17,35 +17,17 @@ * the high values and [-5,5] (+- 1.53 uT) for the low values. */ static intv3_t samples[] = { - { -522, 5, -5 }, - { -528, -3, 1 }, - { -531, -2, 0 }, - { -525, -1, 3 }, + { -522, 5, -5 }, { -528, -3, 1 }, { -531, -2, 0 }, { -525, -1, 3 }, - { 527, 3, -2 }, - { 523, -5, 1 }, - { 520, -3, 2 }, - { 522, 0, -4 }, + { 527, 3, -2 }, { 523, -5, 1 }, { 520, -3, 2 }, { 522, 0, -4 }, - { -3, -519, -2 }, - { 1, -521, 5 }, - { 2, -526, 4 }, - { 0, -532, -5 }, + { -3, -519, -2 }, { 1, -521, 5 }, { 2, -526, 4 }, { 0, -532, -5 }, - { -5, 528, 4 }, - { -2, 531, -4 }, - { 1, 522, 2 }, - { 5, 532, 3 }, + { -5, 528, 4 }, { -2, 531, -4 }, { 1, 522, 2 }, { 5, 532, 3 }, - { -5, 0, -524 }, - { -1, -2, -527 }, - { -3, 4, -532 }, - { 5, 3, -531 }, + { -5, 0, -524 }, { -1, -2, -527 }, { -3, 4, -532 }, { 5, 3, -531 }, - { 4, -2, 524 }, - { 1, 3, 520 }, - { 5, -5, 528 }, - { 0, 2, 521 }, + { 4, -2, 524 }, { 1, 3, 520 }, { 5, -5, 528 }, { 0, 2, 521 }, }; static int test_mag_cal_computes_bias(void) -- cgit v1.2.1 From 6474fb289097b416f34937521c098672dd74145e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:39 -0600 Subject: test/button.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I673164efb1422061eb0ed57142c0a72ba65e27e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730472 Reviewed-by: Jeremy Bettis --- test/button.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/button.c b/test/button.c index e457eaa786..9e06246d7f 100644 --- a/test/button.c +++ b/test/button.c @@ -3,7 +3,7 @@ * found in the LICENSE file. * * Test non-keyboard buttons. -* + * * Using GPIOS and buttons[] defined in board/host/board.c * Volume down is active low with a debounce time of 30 mSec. * Volume up is active high with a debounce time of 60 mSec. -- cgit v1.2.1 From ce2cf92034ad8ff8ba0cbdca03213ff626175c38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:19 -0600 Subject: test/rsa2048-3.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fb62300cf68bdebe4c424a3da2b48203a81b193 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730535 Reviewed-by: Jeremy Bettis --- test/rsa2048-3.h | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/test/rsa2048-3.h b/test/rsa2048-3.h index d1b15c15a4..a09f94ab87 100644 --- a/test/rsa2048-3.h +++ b/test/rsa2048-3.h @@ -13,7 +13,7 @@ * # dumpRSAPublicKey -pub key.pub | xxd -i */ const uint8_t rsa_data[] = { - 0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c, 0x11, 0x17, 0x38, 0xfd, + 0x40, 0x00, 0x00, 0x00, 0x0f, 0x46, 0xe8, 0x2c, 0x11, 0x17, 0x38, 0xfd, 0xef, 0xa2, 0xb5, 0x2d, 0x6d, 0x76, 0xe1, 0x70, 0x7d, 0x67, 0xb1, 0x9a, 0x18, 0x78, 0x90, 0xe2, 0xce, 0xa6, 0x81, 0xa0, 0x13, 0x37, 0xf2, 0x71, 0xf0, 0x44, 0x96, 0xaf, 0x52, 0x53, 0xd4, 0x23, 0x51, 0x19, 0xe5, 0xb0, @@ -65,18 +65,16 @@ BUILD_ASSERT(sizeof(*rsa_key) == sizeof(rsa_data)); /* SHA-256 sum to verify: * # sha256sum README | sed -e 's/\(..\)/0x\1, /mg' */ -const uint8_t hash[] = { - 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, 0x6c, 0xae, 0x8b, 0x2a, - 0x4e, 0xde, 0xc5, 0xeb, 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52, - 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 -}; +const uint8_t hash[] = { 0x6c, 0x5f, 0xef, 0x7f, 0x63, 0x1d, 0xb4, 0x35, + 0x6c, 0xae, 0x8b, 0x2a, 0x4e, 0xde, 0xc5, 0xeb, + 0x11, 0xba, 0x1f, 0x44, 0x40, 0xb6, 0x3a, 0x52, + 0xf2, 0x70, 0xef, 0xee, 0x44, 0x4b, 0x57, 0x62 }; /* Incorrect hash to test the negative case */ -const uint8_t hash_wrong[] = { - 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, 0x0f, 0x2d, 0x3d, 0x0f, - 0xe3, 0xb3, 0xc5, 0xe4, 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad, - 0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 -}; +const uint8_t hash_wrong[] = { 0x61, 0x1b, 0xd2, 0x44, 0xc7, 0x18, 0xa7, 0x2d, + 0x0f, 0x2d, 0x3d, 0x0f, 0xe3, 0xb3, 0xc5, 0xe4, + 0x12, 0xc2, 0x7b, 0x1e, 0x05, 0x2c, 0x6f, 0xad, + 0xc4, 0xac, 0x71, 0x55, 0xe8, 0x80, 0x5c, 0x38 }; /* Generate signature using futility: * # futility create key.pem -- cgit v1.2.1 From a2099a29d001af59f284efc90ebe6a875f0e19f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:55 -0600 Subject: zephyr/projects/nissa/src/joxer/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If9d2680c0ba5ea709a42331cdddbc8b9b8b6d35b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730787 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/joxer/usbc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/nissa/src/joxer/usbc.c b/zephyr/projects/nissa/src/joxer/usbc.c index eeab449c32..9e12f05188 100644 --- a/zephyr/projects/nissa/src/joxer/usbc.c +++ b/zephyr/projects/nissa/src/joxer/usbc.c @@ -103,8 +103,8 @@ static void board_chargers_suspend(struct ap_power_ev_callback *const cb, fn = sm5803_disable_low_power_mode; break; default: - LOG_WRN("%s: power event %d is not recognized", - __func__, data.event); + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); return; } @@ -281,7 +281,7 @@ void board_reset_pd_mcu(void) */ } -#define INT_RECHECK_US 5000 +#define INT_RECHECK_US 5000 /* C0 interrupt line shared by BC 1.2 and charger */ -- cgit v1.2.1 From 673aabf72d7b3d46103c3f1a8750c5e836500464 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:08 -0600 Subject: board/driblee/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iead6d063629f6e2f137c6578cab344faaa809cf4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728260 Reviewed-by: Jeremy Bettis --- board/driblee/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/driblee/cbi_ssfc.c b/board/driblee/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/driblee/cbi_ssfc.c +++ b/board/driblee/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From a80f9958b97c4bc502ae4a7a3bac512fc14f9515 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:22 -0600 Subject: include/driver/charger/isl9241_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iab45abf98e097b508ac53eabf0565fc502f34287 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730274 Reviewed-by: Jeremy Bettis --- include/driver/charger/isl9241_public.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/driver/charger/isl9241_public.h b/include/driver/charger/isl9241_public.h index 342f627bd3..3815826172 100644 --- a/include/driver/charger/isl9241_public.h +++ b/include/driver/charger/isl9241_public.h @@ -8,10 +8,10 @@ #ifndef __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H #define __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H -#define ISL9241_ADDR_FLAGS 0x09 +#define ISL9241_ADDR_FLAGS 0x09 /* Default minimum VIN voltage controlled by ISL9241_REG_VIN_VOLTAGE */ -#define ISL9241_BC12_MIN_VOLTAGE 4096 +#define ISL9241_BC12_MIN_VOLTAGE 4096 extern const struct charger_drv isl9241_drv; @@ -33,9 +33,9 @@ int isl9241_set_ac_prochot(int chgnum, int ma); */ int isl9241_set_dc_prochot(int chgnum, int ma); -#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ -#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ -#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MIN 128 /* mA */ +#define ISL9241_AC_PROCHOT_CURRENT_MAX 6400 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MIN 256 /* mA */ +#define ISL9241_DC_PROCHOT_CURRENT_MAX 12800 /* mA */ #endif /* __CROS_EC_DRIVER_CHARGER_ISL9241_PUBLIC_H */ -- cgit v1.2.1 From e4e12e57b2da06f1ba6c2a323c5eba2b2ae5972b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:26 -0600 Subject: include/fpsensor_crypto.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic058dacf90f8ca65f082db924f0871fa2a614285 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730290 Reviewed-by: Jeremy Bettis --- include/fpsensor_crypto.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/include/fpsensor_crypto.h b/include/fpsensor_crypto.h index b6252b3fd2..4744d6e4aa 100644 --- a/include/fpsensor_crypto.h +++ b/include/fpsensor_crypto.h @@ -67,11 +67,9 @@ int derive_positive_match_secret(uint8_t *output, * @param tag_size the size of |tag|. * @return EC_SUCCESS on success and error code otherwise. */ -int aes_gcm_encrypt(const uint8_t *key, int key_size, - const uint8_t *plaintext, - uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - uint8_t *tag, int tag_size); +int aes_gcm_encrypt(const uint8_t *key, int key_size, const uint8_t *plaintext, + uint8_t *ciphertext, int text_size, const uint8_t *nonce, + int nonce_size, uint8_t *tag, int tag_size); /** * Decrypt |plaintext| using AES-GCM128. @@ -89,7 +87,7 @@ int aes_gcm_encrypt(const uint8_t *key, int key_size, */ int aes_gcm_decrypt(const uint8_t *key, int key_size, uint8_t *plaintext, const uint8_t *ciphertext, int text_size, - const uint8_t *nonce, int nonce_size, - const uint8_t *tag, int tag_size); + const uint8_t *nonce, int nonce_size, const uint8_t *tag, + int tag_size); #endif /* __CROS_EC_FPSENSOR_CRYPTO_H */ -- cgit v1.2.1 From 2195bea04dfff5233bdda8727340aef5834cde5e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:39 -0600 Subject: board/volteer_ish/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73f5affbcf4fcfb90b9d5ad4a100bdc0c40a5975 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729083 Reviewed-by: Jeremy Bettis --- board/volteer_ish/board.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/volteer_ish/board.h b/board/volteer_ish/board.h index 2e2b7e7276..c5f8d161d0 100644 --- a/board/volteer_ish/board.h +++ b/board/volteer_ish/board.h @@ -22,7 +22,7 @@ #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* ISH specific */ -#undef CONFIG_DEBUG_ASSERT +#undef CONFIG_DEBUG_ASSERT #define CONFIG_CLOCK_CRYSTAL #define CONFIG_ISH_UART_0 /* EC */ @@ -40,7 +40,6 @@ #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_HECI - /* Enable sensor fifo, must also define the _SIZE and _THRES */ #define CONFIG_ACCEL_FIFO /* FIFO size is in power of 2. */ @@ -87,10 +86,7 @@ #include "registers.h" /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, SENSOR_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 996c076a263922a3e53e749e0eb81dc6ab87dc12 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:18 -0600 Subject: zephyr/shim/include/cros_cbi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a5300586efbdfe3e74f40348525ffab9ff0a68d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730583 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/cros_cbi.h | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/zephyr/shim/include/cros_cbi.h b/zephyr/shim/include/cros_cbi.h index 40a2b9d8ec..0969c673d5 100644 --- a/zephyr/shim/include/cros_cbi.h +++ b/zephyr/shim/include/cros_cbi.h @@ -14,18 +14,17 @@ * Macros are _INST_ types, so require DT_DRV_COMPAT to be defined. */ #define DT_DRV_COMPAT named_cbi_ssfc_value -#define CROS_CBI_LABEL "cros_cbi" +#define CROS_CBI_LABEL "cros_cbi" -#define CBI_SSFC_VALUE_COMPAT named_cbi_ssfc_value -#define CBI_SSFC_VALUE_ID(id) DT_CAT(CBI_SSFC_VALUE_, id) -#define CBI_SSFC_VALUE_ID_WITH_COMMA(id) CBI_SSFC_VALUE_ID(id), +#define CBI_SSFC_VALUE_COMPAT named_cbi_ssfc_value +#define CBI_SSFC_VALUE_ID(id) DT_CAT(CBI_SSFC_VALUE_, id) +#define CBI_SSFC_VALUE_ID_WITH_COMMA(id) CBI_SSFC_VALUE_ID(id), #define CBI_SSFC_VALUE_INST_ENUM(inst, _) \ CBI_SSFC_VALUE_ID_WITH_COMMA(DT_INST(inst, CBI_SSFC_VALUE_COMPAT)) enum cbi_ssfc_value_id { LISTIFY(DT_NUM_INST_STATUS_OKAY(CBI_SSFC_VALUE_COMPAT), - CBI_SSFC_VALUE_INST_ENUM, ()) - CBI_SSFC_VALUE_COUNT + CBI_SSFC_VALUE_INST_ENUM, ()) CBI_SSFC_VALUE_COUNT }; #undef DT_DRV_COMPAT @@ -34,19 +33,18 @@ enum cbi_ssfc_value_id { * Macros to help generate the enum list of field and value names * for the FW_CONFIG CBI data. */ -#define CBI_FW_CONFIG_COMPAT cros_ec_cbi_fw_config -#define CBI_FW_CONFIG_VALUE_COMPAT cros_ec_cbi_fw_config_value +#define CBI_FW_CONFIG_COMPAT cros_ec_cbi_fw_config +#define CBI_FW_CONFIG_VALUE_COMPAT cros_ec_cbi_fw_config_value /* * Retrieve the enum-name property for this node. */ -#define CBI_FW_CONFIG_ENUM(node) DT_STRING_TOKEN(node, enum_name) +#define CBI_FW_CONFIG_ENUM(node) DT_STRING_TOKEN(node, enum_name) /* * Create an enum entry without a value (an enum with a following comma). */ -#define CBI_FW_CONFIG_ENUM_WITH_COMMA(node) \ - CBI_FW_CONFIG_ENUM(node), +#define CBI_FW_CONFIG_ENUM_WITH_COMMA(node) CBI_FW_CONFIG_ENUM(node), /* * Create a single enum entry with assignment to the node's value, @@ -67,7 +65,7 @@ enum cbi_ssfc_value_id { enum cbi_fw_config_field_id { DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_COMPAT, CBI_FW_CONFIG_CHILD_ENUM_LIST) - CBI_FW_CONFIG_FIELDS_COUNT + CBI_FW_CONFIG_FIELDS_COUNT }; /* @@ -76,7 +74,8 @@ enum cbi_fw_config_field_id { enum cbi_fw_config_value_id { DT_FOREACH_STATUS_OKAY(CBI_FW_CONFIG_VALUE_COMPAT, CBI_FW_CONFIG_ENUM_WITH_VALUE) - CBI_FW_CONFIG_VALUES_LAST /* added to ensure at least one entry */ + CBI_FW_CONFIG_VALUES_LAST /* added to ensure at least one entry + */ }; /** -- cgit v1.2.1 From 15ae6b579593645c666ac1dc5a53b104223c3b7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:07 -0600 Subject: common/regulator.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9abc9c87259d183f21cc0965b4d3b89c7a968a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729704 Reviewed-by: Jeremy Bettis --- common/regulator.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/common/regulator.c b/common/regulator.c index 54d9e87521..dd7c30a29a 100644 --- a/common/regulator.c +++ b/common/regulator.c @@ -11,8 +11,7 @@ #include "host_command.h" #include "regulator.h" -static enum ec_status -hc_regulator_get_info(struct host_cmd_handler_args *args) +static enum ec_status hc_regulator_get_info(struct host_cmd_handler_args *args) { const struct ec_params_regulator_get_info *p = args->params; struct ec_response_regulator_get_info *r = args->response; @@ -33,8 +32,7 @@ hc_regulator_get_info(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_REGULATOR_GET_INFO, hc_regulator_get_info, EC_VER_MASK(0)); -static enum ec_status -hc_regulator_enable(struct host_cmd_handler_args *args) +static enum ec_status hc_regulator_enable(struct host_cmd_handler_args *args) { const struct ec_params_regulator_enable *p = args->params; int rv; -- cgit v1.2.1 From 4206e1d26873c5c2f0ec11c3cb0be44dbb63c924 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:30 -0600 Subject: board/eve/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If94c2e8d80e12a0fb0ea2bbbc674750f0554b277 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728296 Reviewed-by: Jeremy Bettis --- board/eve/board.c | 160 ++++++++++++++++++++++++------------------------------ 1 file changed, 72 insertions(+), 88 deletions(-) diff --git a/board/eve/board.c b/board/eve/board.c index fb0fc4b87a..ed8be66c85 100644 --- a/board/eve/board.c +++ b/board/eve/board.c @@ -57,8 +57,8 @@ #include "util.h" #include "espi.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -171,13 +171,13 @@ __override struct keyboard_scan_config keyscan_config = { /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { 5, 0, 10000 }, - [PWM_CH_LED_L_RED] = { 2, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_KBLIGHT] = { 5, 0, 10000 }, + [PWM_CH_LED_L_RED] = { 2, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_L_GREEN] = { 3, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_LED_L_BLUE] = { 4, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_LED_R_RED] = { 1, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_L_BLUE] = { 4, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_R_RED] = { 1, PWM_CONFIG_DSLEEP, 100 }, [PWM_CH_LED_R_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_LED_R_BLUE] = { 6, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_R_BLUE] = { 6, PWM_CONFIG_DSLEEP, 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -190,42 +190,32 @@ const enum gpio_signal hibernate_wake_pins[] = { const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "accelgyro", - .port = I2C_PORT_GYRO, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "sensors", - .port = I2C_PORT_LID_ACCEL, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "batt", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "accelgyro", + .port = I2C_PORT_GYRO, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "sensors", + .port = I2C_PORT_LID_ACCEL, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "batt", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -360,7 +350,7 @@ void board_tcpc_init(void) */ for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } uint16_t tcpc_get_alert_status(void) @@ -381,18 +371,18 @@ uint16_t tcpc_get_alert_status(void) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* These BD99992GW temp sensors are only readable in S0 */ - {"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, - {"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM3}, - {"Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO}, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, + { "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM3 }, + { "Gyro", TEMP_SENSOR_TYPE_BOARD, bmi160_get_sensor_temp, BASE_GYRO }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -408,8 +398,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) != + EC_SUCCESS) return; if (!(vrfault & BIT(4))) @@ -636,8 +626,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Enable charging trigger by BC1.2 detection */ int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP || @@ -649,8 +639,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, return; charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -719,7 +709,7 @@ __override void lid_angle_peripheral_enable(int enable) * which might be faulty. Disable keyboard and trackpad wake. */ if (chipset_in_state(CHIPSET_STATE_ANY_OFF) || - (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND))) + (tablet_get_mode() && chipset_in_state(CHIPSET_STATE_SUSPEND))) enable = 0; keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE); @@ -851,36 +841,30 @@ static struct mutex g_lid_mutex; static struct kionix_accel_data g_kxcj9_data; static struct bmi_drv_data_t g_bmi160_data; -static struct si114x_drv_data_t g_si114x_data = { - .state = SI114X_NOT_READY, - .covered = 0, - .type_data = { - /* Proximity - unused */ - { - }, - /* light */ - { - .base_data_reg = SI114X_ALS_VIS_DATA0, - .irq_flags = SI114X_IRQ_ENABLE_ALS_IE_INT0 | - SI114X_IRQ_ENABLE_ALS_IE_INT1, - .scale = 1, - .offset = -256, - } - } -}; +static struct si114x_drv_data_t + g_si114x_data = { .state = SI114X_NOT_READY, + .covered = 0, + .type_data = { + /* Proximity - unused */ + {}, + /* light */ + { + .base_data_reg = SI114X_ALS_VIS_DATA0, + .irq_flags = + SI114X_IRQ_ENABLE_ALS_IE_INT0 | + SI114X_IRQ_ENABLE_ALS_IE_INT1, + .scale = 1, + .offset = -256, + } } }; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t mag_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 1484211d3c802fcd54f61afea5adac89a0551bc2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:40 -0600 Subject: board/waddledoo2/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I067e6595e063bdf32f0e662c04ba263a154ab849 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729105 Reviewed-by: Jeremy Bettis --- board/waddledoo2/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledoo2/usb_pd_policy.c b/board/waddledoo2/usb_pd_policy.c index fd9018a3f0..98b770be8f 100644 --- a/board/waddledoo2/usb_pd_policy.c +++ b/board/waddledoo2/usb_pd_policy.c @@ -10,8 +10,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From caba90b048a2c78524562323984b39d8c64d1fd0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:40 -0600 Subject: include/driver/tcpm/tcpci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b6ee32b6c386768e51f63c0d093b61b63d9edde Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730253 Reviewed-by: Jeremy Bettis --- include/driver/tcpm/tcpci.h | 447 +++++++++++++++++++++----------------------- 1 file changed, 218 insertions(+), 229 deletions(-) diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h index 559b75a14f..50fcb6ed64 100644 --- a/include/driver/tcpm/tcpci.h +++ b/include/driver/tcpm/tcpci.h @@ -14,259 +14,250 @@ #include "usb_mux.h" #include "usb_pd_tcpm.h" -#define TCPC_REG_VENDOR_ID 0x0 -#define TCPC_REG_PRODUCT_ID 0x2 -#define TCPC_REG_BCD_DEV 0x4 -#define TCPC_REG_TC_REV 0x6 -#define TCPC_REG_PD_REV 0x8 -#define TCPC_REG_PD_INT_REV 0xa - -#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 -#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 -#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 -#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff -#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 -#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 -#define TCPC_REG_PD_INT_REV_REV(reg) \ - ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) -#define TCPC_REG_PD_INT_REV_VER(reg) \ - (reg & TCOC_REG_PD_INT_REV_VER_MASK) - -#define TCPC_REG_ALERT 0x10 -#define TCPC_REG_ALERT_NONE 0x0000 -#define TCPC_REG_ALERT_MASK_ALL 0xffff -#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) -#define TCPC_REG_ALERT_ALERT_EXT BIT(14) -#define TCPC_REG_ALERT_EXT_STATUS BIT(13) +#define TCPC_REG_VENDOR_ID 0x0 +#define TCPC_REG_PRODUCT_ID 0x2 +#define TCPC_REG_BCD_DEV 0x4 +#define TCPC_REG_TC_REV 0x6 +#define TCPC_REG_PD_REV 0x8 +#define TCPC_REG_PD_INT_REV 0xa + +#define TCPC_REG_PD_INT_REV_REV_MASK 0xff00 +#define TCPC_REG_PD_INT_REV_REV_1_0 0x10 +#define TCPC_REG_PD_INT_REV_REV_2_0 0x20 +#define TCPC_REG_PD_INT_REV_VER_MASK 0x00ff +#define TCPC_REG_PD_INT_REV_VER_1_0 0x10 +#define TCPC_REG_PD_INT_REV_VER_1_1 0x11 +#define TCPC_REG_PD_INT_REV_REV(reg) ((reg & TCOC_REG_PD_INT_REV_REV_MASK) >> 8) +#define TCPC_REG_PD_INT_REV_VER(reg) (reg & TCOC_REG_PD_INT_REV_VER_MASK) + +#define TCPC_REG_ALERT 0x10 +#define TCPC_REG_ALERT_NONE 0x0000 +#define TCPC_REG_ALERT_MASK_ALL 0xffff +#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_ALERT_EXT BIT(14) +#define TCPC_REG_ALERT_EXT_STATUS BIT(13) #define TCPC_REG_ALERT_RX_BEGINNING BIT(12) #define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11) -#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) -#define TCPC_REG_ALERT_FAULT BIT(9) -#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) -#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) -#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) +#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_REG_ALERT_FAULT BIT(9) +#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) +#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) +#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) #define TCPC_REG_ALERT_TX_DISCARDED BIT(5) -#define TCPC_REG_ALERT_TX_FAILED BIT(4) -#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) -#define TCPC_REG_ALERT_RX_STATUS BIT(2) +#define TCPC_REG_ALERT_TX_FAILED BIT(4) +#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) +#define TCPC_REG_ALERT_RX_STATUS BIT(2) #define TCPC_REG_ALERT_POWER_STATUS BIT(1) -#define TCPC_REG_ALERT_CC_STATUS BIT(0) -#define TCPC_REG_ALERT_TX_COMPLETE (TCPC_REG_ALERT_TX_SUCCESS | \ - TCPC_REG_ALERT_TX_DISCARDED | \ - TCPC_REG_ALERT_TX_FAILED) +#define TCPC_REG_ALERT_CC_STATUS BIT(0) +#define TCPC_REG_ALERT_TX_COMPLETE \ + (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | \ + TCPC_REG_ALERT_TX_FAILED) -#define TCPC_REG_ALERT_MASK 0x12 -#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) +#define TCPC_REG_ALERT_MASK 0x12 +#define TCPC_REG_ALERT_MASK_VENDOR_DEF BIT(15) #define TCPC_REG_POWER_STATUS_MASK 0x14 #define TCPC_REG_FAULT_STATUS_MASK 0x15 -#define TCPC_REG_EXT_STATUS_MASK 0x16 +#define TCPC_REG_EXT_STATUS_MASK 0x16 #define TCPC_REG_ALERT_EXTENDED_MASK 0x17 #define TCPC_REG_CONFIG_STD_OUTPUT 0x18 -#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) -#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) -#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB BIT(2) +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) #define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) -#define TCPC_REG_TCPC_CTRL 0x19 +#define TCPC_REG_TCPC_CTRL 0x19 #define TCPC_REG_TCPC_CTRL_SET(polarity) (polarity) -#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg) & 0x1) +#define TCPC_REG_TCPC_CTRL_POLARITY(reg) ((reg)&0x1) /* * In TCPCI Rev 2.0, this bit must be set this to generate CC status alerts when * a connection is found. */ -#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) -#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) -#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) - -#define TCPC_REG_ROLE_CTRL 0x1a -#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) -#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5)|BIT(4)) -#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1)|BIT(0)) -#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ - ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ - (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ - (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ - ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK)) -#define TCPC_REG_ROLE_CTRL_DRP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) -#define TCPC_REG_ROLE_CTRL_RP(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) -#define TCPC_REG_ROLE_CTRL_CC2(reg) \ - (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) -#define TCPC_REG_ROLE_CTRL_CC1(reg) \ - ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK) - -#define TCPC_REG_FAULT_CTRL 0x1b -#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) -#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) - -#define TCPC_REG_POWER_CTRL 0x1c -#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) -#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) -#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) -#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) -#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) +#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) +#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) +#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) + +#define TCPC_REG_ROLE_CTRL 0x1a +#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) +#define TCPC_REG_ROLE_CTRL_RP_MASK (BIT(5) | BIT(4)) +#define TCPC_REG_ROLE_CTRL_CC2_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_ROLE_CTRL_CC1_MASK (BIT(1) | BIT(0)) +#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ + ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ + (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ + (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | \ + ((cc1)&TCPC_REG_ROLE_CTRL_CC1_MASK)) +#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg)&TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) +#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg)&TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) +#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg)&TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) +#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg)&TCPC_REG_ROLE_CTRL_CC1_MASK) + +#define TCPC_REG_FAULT_CTRL 0x1b +#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) +#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(0) + +#define TCPC_REG_POWER_CTRL 0x1c +#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) +#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) +#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) #define TCPC_REG_POWER_CTRL_SET(vconn) (vconn) -#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg) & 0x1) +#define TCPC_REG_POWER_CTRL_VCONN(reg) ((reg)&0x1) -#define TCPC_REG_CC_STATUS 0x1d -#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) -#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) -#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3)|BIT(2)) -#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1)|BIT(0)) +#define TCPC_REG_CC_STATUS 0x1d +#define TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK BIT(5) +#define TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK BIT(4) +#define TCPC_REG_CC_STATUS_CC2_STATE_MASK (BIT(3) | BIT(2)) +#define TCPC_REG_CC_STATUS_CC1_STATE_MASK (BIT(1) | BIT(0)) #define TCPC_REG_CC_STATUS_SET(term, cc1, cc2) \ - ((term) << 4 | ((cc2) & 0x3) << 2 | ((cc1) & 0x3)) + ((term) << 4 | ((cc2)&0x3) << 2 | ((cc1)&0x3)) #define TCPC_REG_CC_STATUS_LOOK4CONNECTION(reg) \ - ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) + ((reg & TCPC_REG_CC_STATUS_LOOK4CONNECTION_MASK) >> 5) #define TCPC_REG_CC_STATUS_TERM(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) + (((reg)&TCPC_REG_CC_STATUS_CONNECT_RESULT_MASK) >> 4) #define TCPC_REG_CC_STATUS_CC2(reg) \ - (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) -#define TCPC_REG_CC_STATUS_CC1(reg) \ - ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK) + (((reg)&TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) +#define TCPC_REG_CC_STATUS_CC1(reg) ((reg)&TCPC_REG_CC_STATUS_CC1_STATE_MASK) -#define TCPC_REG_POWER_STATUS 0x1e -#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff +#define TCPC_REG_POWER_STATUS 0x1e +#define TCPC_REG_POWER_STATUS_MASK_ALL 0xff #define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7) -#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) +#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) #define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4) -#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) #define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0) -#define TCPC_REG_FAULT_STATUS 0x1f -#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) -#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) -#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) -#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) -#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) -#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) -#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) - -#define TCPC_REG_EXT_STATUS 0x20 -#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) - -#define TCPC_REG_ALERT_EXT 0x21 -#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) -#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) -#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) - -#define TCPC_REG_COMMAND 0x23 -#define TCPC_REG_COMMAND_WAKE_I2C 0x11 -#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 -#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 -#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 -#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 -#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 -#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 -#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD -#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE -#define TCPC_REG_COMMAND_I2CIDLE 0xFF - -#define TCPC_REG_DEV_CAP_1 0x24 -#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) -#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) -#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) -#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) -#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) -#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8)|BIT(9)) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) -#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) -#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) -#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) -#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) -#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) -#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) -#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) -#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) - -#define TCPC_REG_DEV_CAP_2 0x26 -#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) -#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) - -#define TCPC_REG_STD_INPUT_CAP 0x28 -#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4)|BIT(3)) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) -#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) -#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) - -#define TCPC_REG_STD_OUTPUT_CAP 0x29 -#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) -#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) -#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) -#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) -#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) -#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) -#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) - -#define TCPC_REG_CONFIG_EXT_1 0x2A -#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) - -#define TCPC_REG_GENERIC_TIMER 0x2c - -#define TCPC_REG_MSG_HDR_INFO 0x2e +#define TCPC_REG_FAULT_STATUS 0x1f +#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) +#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) +#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) +#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) +#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) +#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) + +#define TCPC_REG_EXT_STATUS 0x20 +#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) + +#define TCPC_REG_ALERT_EXT 0x21 +#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) +#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) +#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) + +#define TCPC_REG_COMMAND 0x23 +#define TCPC_REG_COMMAND_WAKE_I2C 0x11 +#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 +#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 +#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 +#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 +#define TCPC_REG_COMMAND_SRC_CTRL_HIGH 0x77 +#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 +#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD +#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE +#define TCPC_REG_COMMAND_I2CIDLE 0xFF + +#define TCPC_REG_DEV_CAP_1 0x24 +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK (BIT(8) | BIT(9)) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF (0 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF (1 << 8) +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF (2 << 8) +#define TCPC_REG_DEV_CAP_1_PWRROLE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK (0 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC (1 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK (2 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC (3 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_DRP (4 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL (5 << 5) +#define TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP (6 << 5) +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +#define TCPC_REG_DEV_CAP_1_SOURCE_NONDEFAULT_VBUS BIT(1) +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) + +#define TCPC_REG_DEV_CAP_2 0x26 +#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) +#define TCPC_REG_DEV_CAP_2_SNK_FR_SWAP BIT(9) + +#define TCPC_REG_STD_INPUT_CAP 0x28 +#define TCPC_REG_STD_INPUT_CAP_SRC_FR_SWAP (BIT(4) | BIT(3)) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_V_F BIT(2) +#define TCPC_REG_STD_INPUT_CAP_EXT_OVR_C_F BIT(1) +#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) + +#define TCPC_REG_STD_OUTPUT_CAP 0x29 +#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) +#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) +#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) +#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) +#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) +#define TCPC_REG_STD_OUTPUT_CAP_MUX_CONF_CTRL BIT(2) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) +#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) + +#define TCPC_REG_CONFIG_EXT_1 0x2A +#define TCPC_REG_CONFIG_EXT_1_FR_SWAP_SNK_DIR BIT(1) + +#define TCPC_REG_GENERIC_TIMER 0x2c + +#define TCPC_REG_MSG_HDR_INFO 0x2e #define TCPC_REG_MSG_HDR_INFO_SET(drole, prole) \ - ((drole) << 3 | (PD_REV20 << 1) | (prole)) -#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg) & 0x8) >> 3) -#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg) & 0x1) - -#define TCPC_REG_RX_DETECT 0x2f -#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) -#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) -#define TCPC_REG_RX_DETECT_HRST BIT(5) -#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) -#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) -#define TCPC_REG_RX_DETECT_SOPPP BIT(2) -#define TCPC_REG_RX_DETECT_SOPP BIT(1) -#define TCPC_REG_RX_DETECT_SOP BIT(0) -#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_HRST) -#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ - (TCPC_REG_RX_DETECT_SOP | \ - TCPC_REG_RX_DETECT_SOPP | \ - TCPC_REG_RX_DETECT_SOPPP | \ - TCPC_REG_RX_DETECT_HRST) + ((drole) << 3 | (PD_REV20 << 1) | (prole)) +#define TCPC_REG_MSG_HDR_INFO_DROLE(reg) (((reg)&0x8) >> 3) +#define TCPC_REG_MSG_HDR_INFO_PROLE(reg) ((reg)&0x1) + +#define TCPC_REG_RX_DETECT 0x2f +#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) +#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) +#define TCPC_REG_RX_DETECT_HRST BIT(5) +#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) +#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) +#define TCPC_REG_RX_DETECT_SOPPP BIT(2) +#define TCPC_REG_RX_DETECT_SOPP BIT(1) +#define TCPC_REG_RX_DETECT_SOP BIT(0) +#define TCPC_REG_RX_DETECT_SOP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST) +#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | \ + TCPC_REG_RX_DETECT_SOPPP | TCPC_REG_RX_DETECT_HRST) /* TCPCI Rev 1.0 receive registers */ -#define TCPC_REG_RX_BYTE_CNT 0x30 +#define TCPC_REG_RX_BYTE_CNT 0x30 #define TCPC_REG_RX_BUF_FRAME_TYPE 0x31 -#define TCPC_REG_RX_HDR 0x32 -#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ +#define TCPC_REG_RX_HDR 0x32 +#define TCPC_REG_RX_DATA 0x34 /* through 0x4f */ /* * In TCPCI Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can * only be accessed by reading at a common register address 30h. */ -#define TCPC_REG_RX_BUFFER 0x30 +#define TCPC_REG_RX_BUFFER 0x30 -#define TCPC_REG_TRANSMIT 0x50 +#define TCPC_REG_TRANSMIT 0x50 #define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) \ - ((retries) << 4 | (type)) + ((retries) << 4 | (type)) #define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type) -#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg) & 0x30) >> 4) -#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg) & 0x7) +#define TCPC_REG_TRANSMIT_RETRY(reg) (((reg)&0x30) >> 4) +#define TCPC_REG_TRANSMIT_TYPE(reg) ((reg)&0x7) /* TCPCI Rev 1.0 transmit registers */ -#define TCPC_REG_TX_BYTE_CNT 0x51 -#define TCPC_REG_TX_HDR 0x52 -#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ +#define TCPC_REG_TX_BYTE_CNT 0x51 +#define TCPC_REG_TX_HDR 0x52 +#define TCPC_REG_TX_DATA 0x54 /* through 0x6f */ /* * In TCPCI Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the @@ -274,12 +265,12 @@ * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x * is “hidden” and can only be accessed by writing to register address 51h */ -#define TCPC_REG_TX_BUFFER 0x51 +#define TCPC_REG_TX_BUFFER 0x51 -#define TCPC_REG_VBUS_VOLTAGE 0x70 -#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) -#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) -#define TCPC_REG_VBUS_VOLTAGE_LSB 25 +#define TCPC_REG_VBUS_VOLTAGE 0x70 +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT GENMASK(9, 0) +#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR GENMASK(11, 10) +#define TCPC_REG_VBUS_VOLTAGE_LSB 25 /* * 00: the measurement is not scaled @@ -287,22 +278,21 @@ * 10: the measurement is divided by 4 * 11: reserved */ -#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ - (1 << (((x) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) -#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) \ - ((x) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) -#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ - (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ +#define TCPC_REG_VBUS_VOLTAGE_SCALE(x) \ + (1 << (((x)&TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR) >> 9)) +#define TCPC_REG_VBUS_VOLTAGE_MEASURE(x) ((x)&TCPC_REG_VBUS_VOLTAGE_MEASUREMENT) +#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ + (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASURE(x) * \ TCPC_REG_VBUS_VOLTAGE_LSB) #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72 #define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */ -#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 -#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 -#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a +#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a extern const struct tcpm_drv tcpci_tcpm_drv; extern const struct usb_mux_driver tcpci_tcpm_usb_mux_driver; @@ -315,7 +305,7 @@ enum tcpc_cc_pull tcpci_get_cached_pull(int port); void tcpci_tcpc_alert(int port); int tcpci_tcpm_init(int port); int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); bool tcpci_tcpm_check_vbus_level(int port, enum vbus_level level); int tcpci_tcpm_select_rp_value(int port, int rp); int tcpci_tcpm_set_cc(int port, int pull); @@ -325,20 +315,19 @@ int tcpci_tcpm_set_vconn(int port, int enable); int tcpci_tcpm_set_msg_header(int port, int power_role, int data_role); int tcpci_tcpm_set_rx_enable(int port, int enable); int tcpci_tcpm_get_message_raw(int port, uint32_t *payload, int *head); -int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data); +int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data); int tcpci_tcpm_release(int port); #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull pull); + enum tcpc_cc_pull pull); int tcpci_tcpc_drp_toggle(int port); #endif #ifdef CONFIG_USB_PD_TCPC_LOW_POWER int tcpci_enter_low_power_mode(int port); void tcpci_wake_low_power_mode(int port); #endif -enum ec_error_list tcpci_set_bist_test_mode(const int port, - const bool enable); +enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable); void tcpci_tcpc_discharge_vbus(int port, int enable); void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable); int tcpci_tcpc_debug_accessory(int port, bool enable); -- cgit v1.2.1 From 16a22390d6fd519b27c9c3f819ff0657d1923c5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:16 -0600 Subject: chip/mec1322/pwm_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib7438c9a0ba5a125ddf123b1684c9eecdefd8bbd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729321 Reviewed-by: Jeremy Bettis --- chip/mec1322/pwm_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/mec1322/pwm_chip.h b/chip/mec1322/pwm_chip.h index 9c441aaecd..61a17379e0 100644 --- a/chip/mec1322/pwm_chip.h +++ b/chip/mec1322/pwm_chip.h @@ -23,4 +23,4 @@ extern const struct pwm_t pwm_channels[]; * MEC1322_PCR_EC_SLP_EN bit mask. */ uint32_t pwm_get_keep_awake_mask(void); -#endif /* __CROS_EC_PWM_CHIP_H */ +#endif /* __CROS_EC_PWM_CHIP_H */ -- cgit v1.2.1 From 7c0b6e48f867a092c5ebf58311f346b033fec760 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:19 -0600 Subject: board/metaknight/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea58d4d6b8a9a450a3a1c9ca06ed3862b546e19d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728454 Reviewed-by: Jeremy Bettis --- board/metaknight/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/metaknight/usb_pd_policy.c b/board/metaknight/usb_pd_policy.c index 3190595596..9edc5a181d 100644 --- a/board/metaknight/usb_pd_policy.c +++ b/board/metaknight/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From b5c574353419ed888682df21ad09c50a6b15461c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:42 -0600 Subject: board/primus/ps2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic56befd87b1a2158e41ed78e65d688e94aabc664 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728843 Reviewed-by: Jeremy Bettis --- board/primus/ps2.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/primus/ps2.h b/board/primus/ps2.h index 0943d5ba4b..abdec687b6 100644 --- a/board/primus/ps2.h +++ b/board/primus/ps2.h @@ -12,20 +12,20 @@ * 0x01 was the original IBM trackpoint, others implement very limited * subset of trackpoint features. */ -#define TP_READ_ID 0xE1 /* Sent for device identification */ +#define TP_READ_ID 0xE1 /* Sent for device identification */ -#define TP_COMMAND 0xE2 /* Commands start with this */ +#define TP_COMMAND 0xE2 /* Commands start with this */ /* * Toggling Flag bits */ -#define TP_TOGGLE 0x47 /* Toggle command */ +#define TP_TOGGLE 0x47 /* Toggle command */ -#define TP_VARIANT_ELAN 0x03 -#define TP_VARIANT_SYNAPTICS 0x06 -#define TP_TOGGLE_SOURCE_TAG 0x20 -#define TP_TOGGLE_BURST 0x28 -#define TP_TOGGLE_SNAPTICS_SLEEP 0x10 -#define TP_TOGGLE_ELAN_SLEEP 0x8 +#define TP_VARIANT_ELAN 0x03 +#define TP_VARIANT_SYNAPTICS 0x06 +#define TP_TOGGLE_SOURCE_TAG 0x20 +#define TP_TOGGLE_BURST 0x28 +#define TP_TOGGLE_SNAPTICS_SLEEP 0x10 +#define TP_TOGGLE_ELAN_SLEEP 0x8 #endif /* __CROS_EC_PRIMUS_PS2_H */ -- cgit v1.2.1 From 8293c2fec921d9cd67a179c0565246c8e29d69b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:24 -0600 Subject: board/sasukette/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5ff30e9e3b3be00ed9eb89b6f64b6086d129e480 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728909 Reviewed-by: Jeremy Bettis --- board/sasukette/battery.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/sasukette/battery.c b/board/sasukette/battery.c index 652c04a651..b81b8c8212 100644 --- a/board/sasukette/battery.c +++ b/board/sasukette/battery.c @@ -12,8 +12,8 @@ #include "common.h" #include "util.h" -#define CHARGING_VOLTAGE_MV_SAFE 8400 -#define CHARGING_CURRENT_MA_SAFE 1500 +#define CHARGING_VOLTAGE_MV_SAFE 8400 +#define CHARGING_CURRENT_MA_SAFE 1500 /* * Battery info for all sasukette battery types. Note that the fields @@ -165,13 +165,13 @@ int charger_profile_override(struct charge_state_data *curr) } enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { return EC_RES_INVALID_PARAM; } -- cgit v1.2.1 From 5a4d7b929b87d4c82dae6d5fd56782ea71d06b9e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:16 -0600 Subject: board/twinkie/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd172bb832cead022fab83b59f74f28452eccd65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729037 Reviewed-by: Jeremy Bettis --- board/twinkie/board.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/board/twinkie/board.c b/board/twinkie/board.c index f3f8460c8d..6b33d5ea20 100644 --- a/board/twinkie/board.c +++ b/board/twinkie/board.c @@ -36,7 +36,7 @@ void board_config_pre_init(void) STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver and TIM2 DMA */ STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10) /* Remap USART1 RX/TX DMA */ - | BIT(29);/* Remap TIM2 DMA */ + | BIT(29); /* Remap TIM2 DMA */ /* 40 MHz pin speed on UART PA9/PA10 */ STM32_GPIO_OSPEEDR(GPIO_A) |= 0x003C0000; /* 40 MHz pin speed on TX clock out PB9 */ @@ -59,24 +59,22 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(1)}, - [ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(3)}, + [ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(1) }, + [ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(3) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_I2C_SCL, - .sda = GPIO_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_I2C_SCL, + .sda = GPIO_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -const void * const usb_strings[] = { +const void *const usb_strings[] = { [USB_STR_DESC] = usb_string_desc, [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), [USB_STR_PRODUCT] = USB_STRING_DESC("Twinkie"), -- cgit v1.2.1 From bb5170bf59d2d69ff48f837d6ee0a84e265262a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:33 -0600 Subject: power/cometlake-discrete.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e4a741dd37981bb58123d0f67bcde81e925c55a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730462 Reviewed-by: Jeremy Bettis --- power/cometlake-discrete.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/power/cometlake-discrete.c b/power/cometlake-discrete.c index a22e32a69f..b731f56bda 100644 --- a/power/cometlake-discrete.c +++ b/power/cometlake-discrete.c @@ -217,7 +217,9 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) shutdown_s5_rails(); } -void chipset_handle_espi_reset_assert(void) {} +void chipset_handle_espi_reset_assert(void) +{ +} enum power_state chipset_force_g3(void) { @@ -303,7 +305,7 @@ enum power_state power_handle_state(enum power_state state) if (power_wait_signals(POWER_SIGNAL_MASK(PP1800_A_PGOOD) | POWER_SIGNAL_MASK(PP1050_A_PGOOD))) return pgood_timeout(POWER_S5G3); - msleep(10); /* tPCH03: VCCPRIM good -> RSMRST >10ms */ + msleep(10); /* tPCH03: VCCPRIM good -> RSMRST >10ms */ gpio_set_level(GPIO_PCH_RSMRST_L, 1); break; @@ -383,7 +385,9 @@ enum power_state power_handle_state(enum power_state state) * implies power sequencing is all-off and we don't have any external * PMIC to synchronize state with. */ -void chipset_handle_reboot(void) {} +void chipset_handle_reboot(void) +{ +} #endif /* CONFIG_VBOOT_EFS */ void c10_gate_interrupt(enum gpio_signal signal) @@ -406,8 +410,8 @@ void c10_gate_interrupt(enum gpio_signal signal) void slp_s3_interrupt(enum gpio_signal signal) { - if (!gpio_get_level(GPIO_SLP_S3_L) - && chipset_in_state(CHIPSET_STATE_ON)) { + if (!gpio_get_level(GPIO_SLP_S3_L) && + chipset_in_state(CHIPSET_STATE_ON)) { /* Falling edge on SLP_S3_L means dropping to S3 from S0 */ shutdown_s0_rails(); } -- cgit v1.2.1 From ecd3fac45187f795a6816248224c1618964a265e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:59 -0600 Subject: core/riscv-rv32i/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I509b44ee511e472d3952d0a5b31c838a57f9908b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729738 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/task.c | 107 ++++++++++++++++++++++-------------------------- 1 file changed, 48 insertions(+), 59 deletions(-) diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index edc31a872e..88d888b185 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -19,10 +19,10 @@ typedef struct { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ } task_; /* Value to store in unused stack */ @@ -36,11 +36,9 @@ CONFIG_TEST_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { - "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { + "<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK @@ -48,12 +46,12 @@ static const char * const task_names[] = { static int task_will_switch; static uint32_t exc_sub_time; static uint64_t task_start_time; /* Time task scheduling started */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern int __task_start(void); @@ -96,41 +94,36 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .a0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .a0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t a0; uint32_t pc; uint16_t stack_size; -} tasks_init[] = { - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -}; +} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK /* Contexts for all tasks */ -static task_ tasks[TASK_ID_COUNT] __attribute__ ((section(".bss.tasks"))); +static task_ tasks[TASK_ID_COUNT] __attribute__((section(".bss.tasks"))); /* Validity checks about static task invariants */ BUILD_ASSERT(TASK_ID_COUNT <= (sizeof(unsigned) * 8)); BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8); #undef TASK /* Reserve space to discard context on first context switch. */ -uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__ - ((section(".bss.task_scratchpad"))); +uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] + __attribute__((section(".bss.task_scratchpad"))); task_ *current_task = (task_ *)scratchpad; @@ -162,7 +155,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -int start_called; /* Has task swapping started */ +int start_called; /* Has task swapping started */ /* in interrupt context */ volatile bool in_interrupt; @@ -188,22 +181,22 @@ static inline task_ *__task_id_to_ptr(task_id_t id) void __ram_code interrupt_disable(void) { /* bit11: disable MEIE */ - asm volatile ("li t0, 0x800"); - asm volatile ("csrc mie, t0"); + asm volatile("li t0, 0x800"); + asm volatile("csrc mie, t0"); } void __ram_code interrupt_enable(void) { /* bit11: enable MEIE */ - asm volatile ("li t0, 0x800"); - asm volatile ("csrs mie, t0"); + asm volatile("li t0, 0x800"); + asm volatile("csrs mie, t0"); } inline bool is_interrupt_enabled(void) { int mie = 0; - asm volatile ("csrr %0, mie" : "=r"(mie)); + asm volatile("csrr %0, mie" : "=r"(mie)); /* Check if MEIE bit is set in MIE register */ return mie & 0x800; @@ -229,7 +222,7 @@ task_id_t __ram_code task_get_current(void) return current_task - tasks; } -atomic_t * __ram_code task_get_event_bitmap(task_id_t tskid) +atomic_t *__ram_code task_get_event_bitmap(task_id_t tskid) { task_ *tsk = __task_id_to_ptr(tskid); @@ -247,7 +240,7 @@ int task_start_called(void) * Also includes emulation of software triggering interrupt vector */ void __ram_code __keep syscall_handler(int desched, task_id_t resched, - int swirq) + int swirq) { /* are we emulating an interrupt ? */ if (swirq) { @@ -279,14 +272,14 @@ void __ram_code __keep syscall_handler(int desched, task_id_t resched, set_mepc(get_mepc() + 4); } -task_ * __ram_code next_sched_task(void) +task_ *__ram_code next_sched_task(void) { task_ *new_task = __task_id_to_ptr(__fls(tasks_ready & tasks_enabled)); #ifdef CONFIG_TASK_PROFILING if (current_task != new_task) { current_task->runtime += - (exc_start_time - exc_end_time - exc_sub_time); + (exc_start_time - exc_end_time - exc_sub_time); task_will_switch = 1; } #endif @@ -466,14 +459,14 @@ uint32_t __ram_code read_clear_int_mask(void) uint32_t mie, meie = BIT(11); /* Read and clear MEIE bit of MIE register. */ - asm volatile ("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie)); + asm volatile("csrrc %0, mie, %1" : "=r"(mie) : "r"(meie)); return mie; } void __ram_code set_int_mask(uint32_t val) { - asm volatile ("csrw mie, %0" : : "r"(val)); + asm volatile("csrw mie, %0" : : "r"(val)); } void task_enable_all_tasks(void) @@ -553,12 +546,12 @@ void __ram_code mutex_lock(struct mutex *mtx) atomic_or(&mtx->waiters, id); while (1) { - asm volatile ( + asm volatile( /* set lock value */ "li %0, 2\n\t" /* attempt to acquire lock */ "amoswap.w.aq %0, %0, %1\n\t" - : "=&r" (locked), "+A" (mtx->lock)); + : "=&r"(locked), "+A"(mtx->lock)); /* we got it ! */ if (!locked) break; @@ -576,9 +569,7 @@ void __ram_code mutex_unlock(struct mutex *mtx) task_ *tsk = current_task; /* give back the lock */ - asm volatile ( - "amoswap.w.aqrl zero, zero, %0\n\t" - : "+A" (mtx->lock)); + asm volatile("amoswap.w.aqrl zero, zero, %0\n\t" : "+A"(mtx->lock)); waiters = mtx->waiters; while (waiters) { @@ -648,9 +639,7 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, - "Print task info"); +DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); static int command_task_ready(int argc, char **argv) { @@ -664,8 +653,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); void task_pre_init(void) @@ -688,9 +676,10 @@ void task_pre_init(void) tasks[i].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[TASK_SCRATCHPAD_SIZE-2] = tasks_init[i].a0; /* a0 */ - sp[TASK_SCRATCHPAD_SIZE-1] = (uint32_t)task_exit_trap; /* ra */ - sp[0] = tasks_init[i].pc; /* pc/mepc */ + sp[TASK_SCRATCHPAD_SIZE - 2] = tasks_init[i].a0; /* a0 */ + sp[TASK_SCRATCHPAD_SIZE - 1] = (uint32_t)task_exit_trap; /* ra + */ + sp[0] = tasks_init[i].pc; /* pc/mepc */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++) -- cgit v1.2.1 From 501e4829a62127f1adcf70e70ac23a87fbcd2880 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:10 -0600 Subject: driver/temp_sensor/g753.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b6b7ef619cc4f404d663c38e3545e71c93f9ba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730103 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/g753.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/driver/temp_sensor/g753.c b/driver/temp_sensor/g753.c index e3946e4f43..c98c54bd3d 100644 --- a/driver/temp_sensor/g753.c +++ b/driver/temp_sensor/g753.c @@ -31,15 +31,14 @@ static int has_power(void) static int raw_read8(const int offset, int *data_ptr) { - return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset, + data_ptr); } #ifdef CONFIG_CMD_TEMP_SENSOR static int raw_write8(const int offset, int data) { - return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, - offset, data); + return i2c_write8(I2C_PORT_THERMAL, G753_I2C_ADDR_FLAGS, offset, data); } #endif @@ -93,8 +92,7 @@ static void temp_sensor_poll(void) DECLARE_HOOK(HOOK_SECOND, temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR); #ifdef CONFIG_CMD_TEMP_SENSOR -static void print_temps(const char *name, - const int temp_reg, +static void print_temps(const char *name, const int temp_reg, const int high_limit_reg) { int value; @@ -106,7 +104,6 @@ static void print_temps(const char *name, if (get_temp(high_limit_reg, &value) == EC_SUCCESS) ccprintf(" High Alarm: %3dC\n", value); - } static int print_status(void) @@ -118,8 +115,7 @@ static int print_status(void) return EC_ERROR_NOT_POWERED; } - print_temps("Local", G753_TEMP_LOCAL, - G753_LOCAL_TEMP_HIGH_LIMIT_R); + print_temps("Local", G753_TEMP_LOCAL, G753_LOCAL_TEMP_HIGH_LIMIT_R); ccprintf("\n"); @@ -161,8 +157,8 @@ static int command_g753(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", - offset, BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is %pb\n", offset, + BINARY_VALUE(data, 8)); return rv; } @@ -185,7 +181,8 @@ static int command_g753(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(g753, command_g753, +DECLARE_CONSOLE_COMMAND( + g753, command_g753, "[settemp|setbyte ] or [getbyte ]. " "Temps in Celsius.", "Print g753 temp sensor status or set parameters."); -- cgit v1.2.1 From 9415d7d60033a090ea34c08c29284563bc861f69 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Tue, 28 Jun 2022 00:39:22 -0700 Subject: TCPMv2: Use helper functions in cable check This is no-op refactor. There are quite a few places to check if SOP'/SOP" are needed when enter or exit TBT Alt mode. Group this checking in common functions to reduce code duplication. Also add helper function to check a special cable type which is passive in ID VDO but active in TBT3 VDO (for example, LRD cable). BUG=none BRANCH=none TEST=On Voxel, LRD cable can enter USB4 mode with Gatkex Creek; can enter TBT mode with TBT dock. Same tests with CBR, Apple TBT3 cable, Apple TBT4 cable, all pass. Signed-off-by: Li Feng Change-Id: I7652bb6ab7e669104ae34414fbfc6f725e0a8ac3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731282 Reviewed-by: Abe Levkoy --- common/usbc/tbt_alt_mode.c | 202 ++++++++++++++++++++++++++------------------- 1 file changed, 119 insertions(+), 83 deletions(-) diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index 479d83644a..2d4f8bf9fa 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -57,8 +57,8 @@ */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -70,8 +70,8 @@ * with a partner. It may be fixed in b/159495742, in which case this * logic is unneeded. */ -#define TBT_FLAG_RETRY_DONE BIT(0) -#define TBT_FLAG_EXIT_DONE BIT(1) +#define TBT_FLAG_RETRY_DONE BIT(0) +#define TBT_FLAG_EXIT_DONE BIT(1) #define TBT_FLAG_CABLE_ENTRY_DONE BIT(2) static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -123,12 +123,14 @@ void tbt_init(int port) bool tbt_is_active(int port) { - return tbt_state[port] != TBT_INACTIVE && tbt_state[port] != TBT_START; + return tbt_state[port] != TBT_INACTIVE && + tbt_state[port] != TBT_START; } bool tbt_entry_is_done(int port) { - return tbt_state[port] == TBT_ACTIVE || tbt_state[port] == TBT_INACTIVE; + return tbt_state[port] == TBT_ACTIVE || + tbt_state[port] == TBT_INACTIVE; } bool tbt_cable_entry_is_done(int port) @@ -138,15 +140,13 @@ bool tbt_cable_entry_is_done(int port) static void tbt_exit_done(int port) { - /* - * If the EC exits an alt mode autonomously, don't try to enter it - * again. If the AP commands the EC to exit DP mode, it might command - * the EC to enter again later, so leave the state machine ready for - * that possibility. - */ - tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? - TBT_START : - TBT_INACTIVE; + /* + * If the EC exits an alt mode autonomously, don't try to enter it again. If + * the AP commands the EC to exit DP mode, it might command the EC to enter + * again later, so leave the state machine ready for that possibility. + */ + tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) + ? TBT_START : TBT_INACTIVE; TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE); TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE); @@ -159,10 +159,50 @@ static void tbt_exit_done(int port) tbt_prints("alt mode protocol failed!", port); } -void tbt_exit_mode_request(int port) +static bool tbt_is_lrd_active_cable(int port) { union tbt_mode_resp_cable cable_mode_resp; + cable_mode_resp.raw_value = + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + /* TODO(b:233402434 b:233429913) + * Need to add the checking that cable is passive in Discover ID + * Header VDO. + */ + if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) + return true; + + return false; +} + +/* Check if this port requires SOP' mode entry and exit */ +static bool tbt_sop_prime_needed(int port) +{ + /* + * We require SOP' entry if cable is + * active cable, or + * an LRD cable (passive in DiscoverIdentity, active in TBT mode) + */ + if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE || + tbt_is_lrd_active_cable(port)) + return true; + return false; +} + +/* Check if this port requires SOP'' mode entry and exit */ +static bool tbt_sop_prime_prime_needed(int port) +{ + const struct pd_discovery *disc; + + disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); + if (disc->identity.product_t1.a_rev20.sop_p_p && + !tbt_is_lrd_active_cable(port)) + return true; + return false; +} + +void tbt_exit_mode_request(int port) +{ TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE); TBT_CLR_FLAG(port, TBT_FLAG_EXIT_DONE); /* @@ -172,28 +212,24 @@ void tbt_exit_mode_request(int port) * TODO (b/156749387): Remove once data reset feature is in place. */ if (tbt_state[port] == TBT_ENTER_SOP) { - cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - /* * For Linear re-driver cables, the port enters USB4 mode * with Thunderbolt mode for SOP prime. Hence, on request to * exit, only exit Thunderbolt mode SOP prime */ - tbt_state[port] = cable_mode_resp.tbt_active_passive == - TBT_CABLE_ACTIVE ? - TBT_EXIT_SOP_PRIME : - TBT_EXIT_SOP_PRIME_PRIME; + tbt_state[port] = + /* TODO: replace with tbt_sop_prime_prime_needed */ + tbt_is_lrd_active_cable(port) ? + TBT_EXIT_SOP_PRIME : TBT_EXIT_SOP_PRIME_PRIME; } } -static bool tbt_response_valid(int port, enum tcpci_msg_type type, char *cmdt, - int vdm_cmd) +static bool tbt_response_valid(int port, enum tcpci_msg_type type, + char *cmdt, int vdm_cmd) { enum tbt_states st = tbt_state[port]; union tbt_mode_resp_cable cable_mode_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) - }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; /* * Check for an unexpected response. @@ -234,55 +270,47 @@ static void tbt_active_cable_exit_mode(int port) bool tbt_cable_entry_required_for_usb4(int port) { const struct pd_discovery *disc_sop_prime; - union tbt_mode_resp_cable cable_mode_resp; - /* Request to enter Thunderbolt mode for the cable prior to entering - * USB4 mode if - - * 1. Thunderbolt Mode SOP' VDO active/passive bit (B25) is - * TBT_CABLE_ACTIVE or - * 2. It's an active cable with VDM version < 2.0 or - * VDO version < 1.3 - */ if (tbt_cable_entry_is_done(port)) return false; - cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - - if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) + /* + * For some cables, the TCPM may need to enter TBT mode with the + * cable to support USB4 mode with the partner. Request to enter + * Thunderbolt mode for the cable prior to entering USB4 for + * the port partner if + * 1. The cable advertises itself as passive in its Identity VDO + * but active in its TBT mode VDO, or + * 2. The cable advertises itself as active, but its PD support + * is not new enough to support Enter_USB. + */ + if (tbt_is_lrd_active_cable(port)) return true; if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) { disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 || disc_sop_prime->identity.product_t1.a_rev30.vdo_ver < - VDO_VERSION_1_3) + VDO_VERSION_1_3) return true; } return false; } void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { - const struct pd_discovery *disc; const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]); int opos_sop, opos_sop_prime; - union tbt_mode_resp_cable cable_mode_resp; if (!tbt_response_valid(port, type, "ACK", vdm_cmd)) return; - disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); - switch (tbt_state[port]) { case TBT_ENTER_SOP_PRIME: tbt_prints("enter mode SOP'", port); - cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); /* For LRD cables, Enter mode SOP' -> Enter mode SOP */ - if (disc->identity.product_t1.a_rev20.sop_p_p && - cable_mode_resp.tbt_active_passive != TBT_CABLE_ACTIVE) { + if (tbt_sop_prime_prime_needed(port)) { tbt_state[port] = TBT_ENTER_SOP_PRIME_PRIME; } else { TBT_SET_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE); @@ -310,6 +338,11 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, if (opos_sop > 0) pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL, opos_sop); + /* + * TODO: + * Replace with tbt_sop_prime_prime_needed() and + * tbt_sop_prime_prime_needed(). + */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) { tbt_active_cable_exit_mode(port); } else { @@ -332,12 +365,13 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, * Exit mode process is complete; go to inactive state. */ tbt_exit_done(port); - opos_sop_prime = pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL); + opos_sop_prime = + pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); /* Clear Thunderbolt related signals */ pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL, opos_sop_prime); + USB_VID_INTEL, opos_sop_prime); set_usb_mux_with_current_data_role(port); } else { tbt_retry_enter_mode(port); @@ -352,8 +386,8 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, break; default: /* Invalid or unexpected negotiation state */ - CPRINTF("%s called with invalid state %d\n", __func__, - tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", + __func__, tbt_state[port]); tbt_exit_done(port); break; } @@ -407,8 +441,8 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) } break; default: - CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd, - tbt_state[port]); + CPRINTS("C%d: NAK for cmd %d in state %d", port, + vdm_cmd, tbt_state[port]); tbt_exit_done(port); break; } @@ -417,7 +451,7 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) static bool tbt_mode_is_supported(int port, int vdo_count) { const struct pd_discovery *disc = - pd_get_am_discovery(port, TCPCI_MSG_SOP); + pd_get_am_discovery(port, TCPCI_MSG_SOP); if (!disc->identity.idh.modal_support) return false; @@ -431,8 +465,8 @@ static bool tbt_mode_is_supported(int port, int vdo_count) * SVID USB_VID_INTEL to enter Thunderbolt alt mode */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE && - !pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL)) + !pd_is_mode_discovered_for_svid( + port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL)) return false; return true; @@ -444,7 +478,6 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, { struct svdm_amode_data *modep; int vdo_count_ret = 0; - union tbt_mode_resp_cable cable_mode_resp; *tx_type = TCPCI_MSG_SOP; @@ -468,12 +501,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, */ usb_mux_set_safe_mode(port); - cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - /* Active cable and LRD cables send Enter Mode SOP' first */ - if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE || - cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) { + if (tbt_sop_prime_needed(port)) { tbt_state[port] = TBT_ENTER_SOP_PRIME; } else { /* Passive cable send Enter Mode SOP */ @@ -487,12 +516,14 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, *tx_type = TCPCI_MSG_SOP_PRIME; break; case TBT_ENTER_SOP_PRIME_PRIME: - vdo_count_ret = enter_tbt_compat_mode( - port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); + vdo_count_ret = + enter_tbt_compat_mode( + port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_ENTER_SOP: - vdo_count_ret = enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); + vdo_count_ret = + enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); break; case TBT_ACTIVE: /* @@ -514,38 +545,43 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, return MSG_SETUP_MUX_WAIT; case TBT_EXIT_SOP: /* DPM will only call this after safe state set is done */ - modep = pd_get_amode_data(port, TCPCI_MSG_SOP, USB_VID_INTEL); + modep = pd_get_amode_data(port, + TCPCI_MSG_SOP, USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)); + VDO_OPOS(modep->opos) | + VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS( + pd_get_vdo_ver(port, TCPCI_MSG_SOP)); vdo_count_ret = 1; break; case TBT_EXIT_SOP_PRIME_PRIME: - modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL); + modep = pd_get_amode_data(port, + TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver( - port, TCPCI_MSG_SOP_PRIME_PRIME)); + VDO_OPOS(modep->opos) | + VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver(port, + TCPCI_MSG_SOP_PRIME_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_EXIT_SOP_PRIME: - modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL); + modep = pd_get_amode_data(port, + TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS( - pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME)); + VDO_OPOS(modep->opos) | + VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver(port, + TCPCI_MSG_SOP_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME; break; @@ -553,8 +589,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, /* Thunderbolt mode is inactive */ return MSG_SETUP_UNSUPPORTED; default: - CPRINTF("%s called with invalid state %d\n", __func__, - tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", + __func__, tbt_state[port]); return MSG_SETUP_ERROR; } -- cgit v1.2.1 From 88222aad8fc04497f54da56063208d298659234f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:26 -0600 Subject: board/magolor/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I892a72fcc03ef42ba66f343a8a7b9cfe15117304 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728642 Reviewed-by: Jeremy Bettis --- board/magolor/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/magolor/led.c b/board/magolor/led.c index 5206244073..fd8f9d6c83 100644 --- a/board/magolor/led.c +++ b/board/magolor/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 726886de2cc44c22ff9453d1e1cdcfbe6b7e6ccd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:36 -0600 Subject: board/kingoftown/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie684fe948cf0320f91c65338aec641e74165bb6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728549 Reviewed-by: Jeremy Bettis --- board/kingoftown/board.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/board/kingoftown/board.h b/board/kingoftown/board.h index e71fdd6741..2bee2621ba 100644 --- a/board/kingoftown/board.h +++ b/board/kingoftown/board.h @@ -11,7 +11,7 @@ #include "baseboard.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -20,7 +20,7 @@ #define CONFIG_PWM_KBLIGHT /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -68,12 +68,7 @@ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -83,11 +78,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From d366a1b25c7fcb4a52b568e489834c73c6382d3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:34 -0600 Subject: zephyr/projects/skyrim/include/gpio_map.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieba1bcf29e1a07ee22db44d548cf0ba666c3dd0e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730801 Reviewed-by: Jeremy Bettis --- zephyr/projects/skyrim/include/gpio_map.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index ca1272a9ed..9d88da8056 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -21,8 +21,8 @@ enum power_signal { POWER_SIGNAL_COUNT, }; -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L #endif /* __ZEPHYR_GPIO_MAP_H */ -- cgit v1.2.1 From 05bc69753dd355d5c0a273a8557ae9fd7f77a496 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:23 -0600 Subject: board/taeko/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie62669d3d47134e766ff07f6348ea5b5cf7ca5b4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728983 Reviewed-by: Jeremy Bettis --- board/taeko/fw_config.h | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/board/taeko/fw_config.h b/board/taeko/fw_config.h index 4062946868..a858598f04 100644 --- a/board/taeko/fw_config.h +++ b/board/taeko/fw_config.h @@ -14,20 +14,14 @@ * Source of truth is the project/taeko/taeko/config.star configuration file. */ -enum ec_cfg_usb_db_type { - DB_USB_ABSENT = 0, - DB_USB3_PS8815 = 1 -}; +enum ec_cfg_usb_db_type { DB_USB_ABSENT = 0, DB_USB3_PS8815 = 1 }; enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_DISABLED = 0, KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_tabletmode_type { - TABLETMODE_DISABLED = 0, - TABLETMODE_ENABLED = 1 -}; +enum ec_cfg_tabletmode_type { TABLETMODE_DISABLED = 0, TABLETMODE_ENABLED = 1 }; enum ec_cfg_kbnumpad { KEYBOARD_NUMBER_PAD_ABSENT = 0, @@ -46,11 +40,11 @@ enum ec_cfg_emmc_status { union taeko_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 2; - uint32_t sd_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 4; + enum ec_cfg_usb_db_type usb_db : 2; + uint32_t sd_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 4; /* b/194515356 - Fw config structure * b/203630618 - Move tablet mode to bit14 * bit8-9: kb_layout @@ -58,11 +52,11 @@ union taeko_cbi_fw_config { * bit12: nvme * bit13: emmc */ - enum ec_cfg_nvme_status nvme_status : 1; - enum ec_cfg_emmc_status emmc_status : 1; - enum ec_cfg_tabletmode_type tabletmode : 1; - enum ec_cfg_kbnumpad kbnumpad : 1; - uint32_t reserved_2 : 16; + enum ec_cfg_nvme_status nvme_status : 1; + enum ec_cfg_emmc_status emmc_status : 1; + enum ec_cfg_tabletmode_type tabletmode : 1; + enum ec_cfg_kbnumpad kbnumpad : 1; + uint32_t reserved_2 : 16; }; uint32_t raw_value; }; -- cgit v1.2.1 From 54f3c1f5f72da4085d6c7cd7e8b8e6266940952c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:51 -0600 Subject: board/volmar/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib61803da9280fb819cef5275f77e95850780a522 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729064 Reviewed-by: Jeremy Bettis --- board/volmar/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/volmar/charger.c b/board/volmar/charger.c index 85e0de90fe..32dd2ddddb 100644 --- a/board/volmar/charger.c +++ b/board/volmar/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 1a1e93881f4231d4af28879bd5c879b9d03b9467 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:29 -0600 Subject: zephyr/projects/nissa/src/xivu/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If924920179b37aad11d845842361bcb44ace46ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730799 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/xivu/led.c | 37 ++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/zephyr/projects/nissa/src/xivu/led.c b/zephyr/projects/nissa/src/xivu/led.c index a0c0447419..fbe5c88218 100644 --- a/zephyr/projects/nissa/src/xivu/led.c +++ b/zephyr/projects/nissa/src/xivu/led.c @@ -13,20 +13,29 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC } }, + }; __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From 0ee4960a2e1ccd856627ca1aa60eae665fdbbe4e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:51 -0600 Subject: common/usbc_ppc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4032451d819a73589631cd22f0a5f5846e0f909a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729802 Reviewed-by: Jeremy Bettis --- common/usbc_ppc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/usbc_ppc.c b/common/usbc_ppc.c index f6c7f6876d..aa462e3743 100644 --- a/common/usbc_ppc.c +++ b/common/usbc_ppc.c @@ -15,8 +15,8 @@ #include "util.h" #ifndef TEST_BUILD -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(args...) #define CPRINTS(args...) @@ -277,7 +277,7 @@ int ppc_set_frs_enable(int port, int enable) ppc = &ppc_chips[port]; if (ppc->drv->set_frs_enable) - rv = ppc->drv->set_frs_enable(port,enable); + rv = ppc->drv->set_frs_enable(port, enable); return rv; } -- cgit v1.2.1 From 44b5bfd71dc34701aad87dad631343a31f307148 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:46 -0600 Subject: chip/mchp/lpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3337050b8f82d37f59f69188377e576d19b4b13d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729296 Reviewed-by: Jeremy Bettis --- chip/mchp/lpc.c | 129 +++++++++++++++++++++----------------------------------- 1 file changed, 48 insertions(+), 81 deletions(-) diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index 86cc67fb51..e44c40a7bd 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -27,23 +27,22 @@ /* Console output macros */ #ifdef CONFIG_MCHP_DEBUG_LPC #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #else #define CPUTS(...) #define CPRINTS(...) #endif -static uint8_t -mem_mapped[0x200] __attribute__((section(".bss.big_align"))); +static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align"))); static struct host_packet lpc_packet; static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ +static uint8_t host_cmd_flags; /* Flags from host command */ static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; -static struct ec_lpc_host_args * const lpc_host_args = +static struct ec_lpc_host_args *const lpc_host_args = (struct ec_lpc_host_args *)mem_mapped; #ifdef CONFIG_BOARD_ID_CMD_ACPI_EC1 @@ -52,7 +51,6 @@ static uint8_t custom_acpi_ec2os_cnt; static uint8_t custom_apci_ec2os[4]; #endif - static void keyboard_irq_assert(void) { #ifdef CONFIG_KEYBOARD_IRQ_GPIO @@ -142,7 +140,6 @@ static uint8_t *lpc_get_hostcmd_data_range(void) return mem_mapped; } - /** * Update the host event status. * @@ -182,7 +179,7 @@ void lpc_update_host_event_status(void) /* Copy host events to mapped memory */ *(uint32_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); + lpc_get_host_events(); task_enable_irq(MCHP_IRQ_ACPIEC0_IBF); @@ -216,15 +213,13 @@ static void lpc_send_response(struct host_cmd_handler_args *args) } /* New-style response */ - lpc_host_args->flags = - (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | - EC_HOST_ARGS_FLAG_TO_HOST; + lpc_host_args->flags = (host_cmd_flags & ~EC_HOST_ARGS_FLAG_FROM_HOST) | + EC_HOST_ARGS_FLAG_TO_HOST; lpc_host_args->data_size = size; csum = args->command + lpc_host_args->flags + - lpc_host_args->command_version + - lpc_host_args->data_size; + lpc_host_args->command_version + lpc_host_args->data_size; for (i = 0, out = (uint8_t *)args->response; i < size; i++, out++) csum += *out; @@ -243,9 +238,7 @@ static void lpc_send_response(struct host_cmd_handler_args *args) * sticky status in interrupt aggregator. */ MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(1); - + MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1); } static void lpc_send_response_packet(struct host_packet *pkt) @@ -265,8 +258,7 @@ static void lpc_send_response_packet(struct host_packet *pkt) /* Clear the busy bit, so the host knows the EC is done. */ MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(1); + MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(1); } uint8_t *lpc_get_memmap_range(void) @@ -283,10 +275,8 @@ void lpc_mem_mapped_init(void) } const int acpi_ec_pcr_slp[] = { - MCHP_PCR_ACPI_EC0, - MCHP_PCR_ACPI_EC1, - MCHP_PCR_ACPI_EC2, - MCHP_PCR_ACPI_EC3, + MCHP_PCR_ACPI_EC0, MCHP_PCR_ACPI_EC1, + MCHP_PCR_ACPI_EC2, MCHP_PCR_ACPI_EC3, #ifndef CHIP_FAMILY_MEC152X MCHP_PCR_ACPI_EC4, #endif @@ -294,10 +284,8 @@ const int acpi_ec_pcr_slp[] = { BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES); const int acpi_ec_nvic_ibf[] = { - MCHP_IRQ_ACPIEC0_IBF, - MCHP_IRQ_ACPIEC1_IBF, - MCHP_IRQ_ACPIEC2_IBF, - MCHP_IRQ_ACPIEC3_IBF, + MCHP_IRQ_ACPIEC0_IBF, MCHP_IRQ_ACPIEC1_IBF, + MCHP_IRQ_ACPIEC2_IBF, MCHP_IRQ_ACPIEC3_IBF, #ifndef CHIP_FAMILY_MEC152X MCHP_IRQ_ACPIEC4_IBF, #endif @@ -306,10 +294,8 @@ BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES); #ifdef CONFIG_HOST_INTERFACE_ESPI const int acpi_ec_espi_bar_id[] = { - MCHP_ESPI_IO_BAR_ID_ACPI_EC0, - MCHP_ESPI_IO_BAR_ID_ACPI_EC1, - MCHP_ESPI_IO_BAR_ID_ACPI_EC2, - MCHP_ESPI_IO_BAR_ID_ACPI_EC3, + MCHP_ESPI_IO_BAR_ID_ACPI_EC0, MCHP_ESPI_IO_BAR_ID_ACPI_EC1, + MCHP_ESPI_IO_BAR_ID_ACPI_EC2, MCHP_ESPI_IO_BAR_ID_ACPI_EC3, #ifndef CHIP_FAMILY_MEC152X MCHP_ESPI_IO_BAR_ID_ACPI_EC4, #endif @@ -327,17 +313,15 @@ void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask) MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]); #ifdef CONFIG_HOST_INTERFACE_ESPI - MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = - mask; + MCHP_ESPI_IO_BAR_CTL_MASK(acpi_ec_espi_bar_id[instance]) = mask; MCHP_ESPI_IO_BAR(acpi_ec_espi_bar_id[instance]) = - (io_base << 16) + 0x01ul; + (io_base << 16) + 0x01ul; #else - MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) + - (1ul << 15) + mask; + MCHP_LPC_ACPI_EC_BAR(instance) = (io_base << 16) + (1ul << 15) + mask; #endif MCHP_ACPI_EC_STATUS(instance) &= ~EC_LPC_STATUS_PROCESSING; MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(instance); + MCHP_ACPI_EC_IBF_GIRQ_BIT(instance); task_enable_irq(acpi_ec_nvic_ibf[instance]); } @@ -352,8 +336,7 @@ void chip_8042_config(uint32_t io_base) #ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_8042) = 0x04; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = - (io_base << 16) + 0x01ul; + MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_8042) = (io_base << 16) + 0x01ul; #else /* Set up 8042 interface at 0x60/0x64 */ MCHP_LPC_8042_BAR = (io_base << 16) + (1ul << 15); @@ -363,8 +346,8 @@ void chip_8042_config(uint32_t io_base) MCHP_8042_ACT |= 1; - MCHP_INT_ENABLE(MCHP_8042_GIRQ) = MCHP_8042_OBE_GIRQ_BIT + - MCHP_8042_IBF_GIRQ_BIT; + MCHP_INT_ENABLE(MCHP_8042_GIRQ) = + MCHP_8042_OBE_GIRQ_BIT + MCHP_8042_IBF_GIRQ_BIT; task_enable_irq(MCHP_IRQ_8042EM_IBF); task_enable_irq(MCHP_IRQ_8042EM_OBE); @@ -394,8 +377,7 @@ void chip_emi0_config(uint32_t io_base) { #ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_ID_EMI0) = 0x0F; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = - (io_base << 16) + 0x01ul; + MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_ID_EMI0) = (io_base << 16) + 0x01ul; #else MCHP_LPC_EMI0_BAR = (io_base << 16) + (1ul << 15); #endif @@ -431,27 +413,23 @@ void chip_port80_config(uint32_t io_base) /* Last: Enable Host access via eSPI IO BAR */ MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_BDP0) = 0x00; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) = - (io_base << 16) + 0x01ul; + MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_BDP0) = (io_base << 16) + 0x01ul; } #else void chip_port80_config(uint32_t io_base) { MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0); - MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + - MCHP_P80_RESET_TIMESTAMP_WO; + MCHP_P80_CFG(0) = MCHP_P80_FLUSH_FIFO_WO + MCHP_P80_RESET_TIMESTAMP_WO; #ifdef CONFIG_HOST_INTERFACE_ESPI MCHP_ESPI_IO_BAR_CTL_MASK(MCHP_ESPI_IO_BAR_P80_0) = 0x00; - MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = - (io_base << 16) + 0x01ul; + MCHP_ESPI_IO_BAR(MCHP_ESPI_IO_BAR_P80_0) = (io_base << 16) + 0x01ul; #else MCHP_LPC_P80DBG0_BAR = (io_base << 16) + (1ul << 15); #endif - MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 + - MCHP_P80_TIMEBASE_1500KHZ + - MCHP_P80_TIMER_ENABLE; + MCHP_P80_CFG(0) = MCHP_P80_FIFO_THRHOLD_14 + MCHP_P80_TIMEBASE_1500KHZ + + MCHP_P80_TIMER_ENABLE; MCHP_P80_ACTIVATE(0) = 1; @@ -541,9 +519,9 @@ static void lpc_init(void) * NOTE: EMI doesn't have a sleep enable. */ MCHP_PCR_SLP_DIS_DEV_MASK(2, MCHP_PCR_SLP_EN2_GCFG + - MCHP_PCR_SLP_EN2_ACPI_EC0 + - MCHP_PCR_SLP_EN2_ACPI_EC0 + - MCHP_PCR_SLP_EN2_MIF8042); + MCHP_PCR_SLP_EN2_ACPI_EC0 + + MCHP_PCR_SLP_EN2_ACPI_EC0 + + MCHP_PCR_SLP_EN2_MIF8042); #ifdef CONFIG_HOST_INTERFACE_ESPI @@ -574,8 +552,7 @@ static void lpc_init(void) * clock stop and there are no pending SERIRQ * or LPC DMA. */ - MCHP_LPC_EC_CLK_CTRL = - (MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul; + MCHP_LPC_EC_CLK_CTRL = (MCHP_LPC_EC_CLK_CTRL & ~(0x03ul)) | 0x01ul; setup_lpc(); #endif @@ -635,8 +612,7 @@ void lpcrst_interrupt(enum gpio_signal signal) #endif } #ifdef CONFIG_MCHP_DEBUG_LPC - CPRINTS("LPC RESET# %sasserted", - lpc_get_pltrst_asserted() ? "" : "de"); + CPRINTS("LPC RESET# %sasserted", lpc_get_pltrst_asserted() ? "" : "de"); #endif #endif } @@ -688,8 +664,7 @@ int port_80_read(void) * Some chipset CoreBoot will send read board ID command expecting * a two byte response. */ -static int acpi_ec0_custom(int is_cmd, uint8_t value, - uint8_t *resultptr) +static int acpi_ec0_custom(int is_cmd, uint8_t value, uint8_t *resultptr) { int rval; @@ -699,7 +674,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value, if (is_cmd && (value == 0x0d)) { MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); + MCHP_ACPI_EC_OBE_GIRQ_BIT(0); /* Write two bytes sequence 0xC2, 0x04 to Host */ if (MCHP_ACPI_EC_BYTE_CTL(0) & 0x01) { /* Host enabled 4-byte mode */ @@ -715,7 +690,7 @@ static int acpi_ec0_custom(int is_cmd, uint8_t value, custom_apci_ec2os[0] = 0x04; MCHP_ACPI_EC_EC2OS(0, 0) = 0x02; MCHP_INT_ENABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); + MCHP_ACPI_EC_OBE_GIRQ_BIT(0); task_enable_irq(MCHP_IRQ_ACPIEC0_OBE); } custom_acpi_cmd = 0; @@ -754,8 +729,7 @@ static void acpi_0_interrupt(void) MCHP_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; /* Clear R/W1C status bit in Aggregator */ - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_IBF_GIRQ_BIT(0); + MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_IBF_GIRQ_BIT(0); /* * ACPI 5.0-12.6.1: Generate SCI for Input Buffer Empty / @@ -775,8 +749,7 @@ static void acpi_0_obe_isr(void) { uint8_t sts, data; - MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); + MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) = MCHP_ACPI_EC_OBE_GIRQ_BIT(0); sts = MCHP_ACPI_EC_STATUS(0); data = MCHP_ACPI_EC_BYTE_CTL(0); @@ -788,7 +761,7 @@ static void acpi_0_obe_isr(void) if (custom_acpi_ec2os_cnt == 0) { /* was last byte? */ MCHP_INT_DISABLE(MCHP_ACPI_EC_GIRQ) = - MCHP_ACPI_EC_OBE_GIRQ_BIT(0); + MCHP_ACPI_EC_OBE_GIRQ_BIT(0); } lpc_generate_sci(); @@ -800,8 +773,7 @@ static void acpi_1_interrupt(void) { uint8_t st = MCHP_ACPI_EC_STATUS(1); - if (!(st & EC_LPC_STATUS_FROM_HOST) || - !(st & EC_LPC_STATUS_LAST_CMD)) + if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD)) return; /* Set the busy bit */ @@ -821,8 +793,7 @@ static void acpi_1_interrupt(void) if (host_cmd_args.command == EC_COMMAND_PROTOCOL_3) { lpc_packet.send_response = lpc_send_response_packet; - lpc_packet.request = - (const void *)lpc_get_hostcmd_data_range(); + lpc_packet.request = (const void *)lpc_get_hostcmd_data_range(); lpc_packet.request_temp = params_copy; lpc_packet.request_max = sizeof(params_copy); /* Don't know the request size so @@ -830,8 +801,7 @@ static void acpi_1_interrupt(void) */ lpc_packet.request_size = EC_LPC_HOST_PACKET_SIZE; - lpc_packet.response = - (void *)lpc_get_hostcmd_data_range(); + lpc_packet.response = (void *)lpc_get_hostcmd_data_range(); lpc_packet.response_max = EC_LPC_HOST_PACKET_SIZE; lpc_packet.response_size = 0; @@ -857,8 +827,7 @@ DECLARE_IRQ(MCHP_IRQ_ACPIEC1_IBF, acpi_1_interrupt, 1); static void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) - keyboard_host_write(MCHP_8042_H2E, - MCHP_8042_STS & BIT(3)); + keyboard_host_write(MCHP_8042_H2E, MCHP_8042_STS & BIT(3)); MCHP_INT_SOURCE(MCHP_8042_GIRQ) = MCHP_8042_IBF_GIRQ_BIT; task_wake(TASK_ID_KEYPROTO); @@ -954,7 +923,7 @@ int lpc_get_pltrst_asserted(void) return !gpio_get_level(GPIO_PCH_PLTRST_L); #else /* assumes LPC clock is running when host changes LRESET# */ - return (MCHP_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0; + return (MCHP_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0; #endif #endif } @@ -996,9 +965,8 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, + EC_VER_MASK(0)); #ifdef CONFIG_MCHP_DEBUG_LPC static int command_lpc(int argc, char **argv) @@ -1016,6 +984,5 @@ static int command_lpc(int argc, char **argv) return EC_ERROR_PARAM1; return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", - "Trigger SCI/SMI"); +DECLARE_CONSOLE_COMMAND(lpc, command_lpc, "[sci|smi|wake]", "Trigger SCI/SMI"); #endif -- cgit v1.2.1 From 8eeb9f59861523842c7025aed8d0003ed04b9c16 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:27 -0600 Subject: board/shotzo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fb26cefe9f3cfe660e50d46b0985fe662d31ab7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728949 Reviewed-by: Jeremy Bettis --- board/shotzo/board.c | 176 +++++++++++++++++++++++---------------------------- 1 file changed, 80 insertions(+), 96 deletions(-) diff --git a/board/shotzo/board.c b/board/shotzo/board.c index a7cd45c7c6..be3926a014 100644 --- a/board/shotzo/board.c +++ b/board/shotzo/board.c @@ -43,7 +43,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -182,48 +182,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -298,17 +286,13 @@ static struct accelgyro_saved_data_t g_bma422_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -564,8 +548,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -573,11 +557,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -588,11 +572,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -697,33 +681,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -753,9 +735,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -774,14 +755,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 7c87e2085459ebd20e8c13248fdfaee6f255ef23 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:38 -0600 Subject: include/mock/charge_manager_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf6fc171dcbe92952584c6c40d7635393e5d80f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730356 Reviewed-by: Jeremy Bettis --- include/mock/charge_manager_mock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mock/charge_manager_mock.h b/include/mock/charge_manager_mock.h index 8a791f6121..23377f6716 100644 --- a/include/mock/charge_manager_mock.h +++ b/include/mock/charge_manager_mock.h @@ -16,7 +16,7 @@ struct mock_ctrl_charge_manager { }; #define MOCK_CTRL_DEFAULT_CHARGE_MANAGER \ - ((struct mock_ctrl_charge_manager) { \ + ((struct mock_ctrl_charge_manager){ \ .vbus_voltage_mv = 0, \ }) -- cgit v1.2.1 From c11401f3104664f32c37a4a03979a897d1db5468 Mon Sep 17 00:00:00 2001 From: Jacky_Wang Date: Thu, 23 Jun 2022 18:26:38 +0800 Subject: throttle_ap: Add option to gate PROCHOT based on suspend The PROCHOT signal is not valid while system is on power off process. Add an option to gate if PROCHOT is asserted in the S3 state. BUG=b:237362268 BRANCH=firmware-volteer-13672.B TEST=make BOARD=drobit 1. Check fan will not full run while system power off. Signed-off-by: Jacky_Wang Change-Id: I0ec6c6b9fc1961a9b555bdf2ded98620fa7ba017 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3720838 Commit-Queue: caveh jalali Reviewed-by: Daisuke Nojiri Reviewed-by: caveh jalali --- common/throttle_ap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/throttle_ap.c b/common/throttle_ap.c index c47f509c6d..1f50cdb597 100644 --- a/common/throttle_ap.c +++ b/common/throttle_ap.c @@ -126,7 +126,7 @@ static void prochot_input_deferred(void) * asserting low is normal behavior and not a concern * for PROCHOT# event. Ignore all PROCHOT changes while the AP is off */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_ANY_SUSPEND)) return; /* -- cgit v1.2.1 From a63f8770111bbef567d05f7b292cc6a167ce752f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:29 -0600 Subject: include/usb_pd_dpm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ef3d75bcfb276888e25714dffd033061b609c9b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730440 Reviewed-by: Jeremy Bettis --- include/usb_pd_dpm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h index 391e7ed246..d977bdfdca 100644 --- a/include/usb_pd_dpm.h +++ b/include/usb_pd_dpm.h @@ -51,7 +51,7 @@ void dpm_data_reset_complete(int port); * @param vdm The VDM payload of the ACK */ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Informs the DPM that a VDM NAK was received. Also applies when a VDM request @@ -63,7 +63,7 @@ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, * @param vdm_cmd The VDM command of the request */ void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, - uint8_t vdm_cmd); + uint8_t vdm_cmd); /* * Drives the Policy Engine through entry/exit mode process @@ -147,4 +147,4 @@ enum dpm_msg_setup_status { MSG_SETUP_MUX_WAIT, }; -#endif /* __CROS_EC_USB_DPM_H */ +#endif /* __CROS_EC_USB_DPM_H */ -- cgit v1.2.1 From 8bd096d41cade17b2980d2bd04424cf0cedc3677 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:28 -0600 Subject: include/overflow.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I769915801ed391ef951a4737c4744d35f559c88e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730375 Reviewed-by: Jeremy Bettis --- include/overflow.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/overflow.h b/include/overflow.h index 42eab6a094..b2202121ee 100644 --- a/include/overflow.h +++ b/include/overflow.h @@ -26,7 +26,7 @@ __has_builtin(__builtin_mul_overflow) #define COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW 1 #endif -#endif /* __clang__ */ +#endif /* __clang__ */ #include "third_party/linux/overflow.h" -- cgit v1.2.1 From e15ee4d7a9a33e0d829f7eddef92e90e2791a955 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:05 -0600 Subject: chip/mt_scp/rv32i_common/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia0da077c2ee18fe91ed4665c0fbb4fc625a80e79 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729372 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/uart.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/mt_scp/rv32i_common/uart.c b/chip/mt_scp/rv32i_common/uart.c index 35b4003c9f..07c56e3bc3 100644 --- a/chip/mt_scp/rv32i_common/uart.c +++ b/chip/mt_scp/rv32i_common/uart.c @@ -31,9 +31,8 @@ void uart_init(void) uart_init_pinmux(); /* Clear FIFO */ - UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO - | UART_FCR_CLEAR_RCVR - | UART_FCR_CLEAR_XMIT; + UART_FCR(UARTN) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT; /* Line control: parity none, 8 bit, 1 stop bit */ UART_LCR(UARTN) = UART_LCR_WLEN8; /* For baud rate <= 115200 */ @@ -137,7 +136,7 @@ static void uart_irq_handler(void) case UART_RX_IRQ(UARTN): uart_process(); SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0); - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); break; } -- cgit v1.2.1 From 890b1bf862029bce52f4bac151a6c51e384b264e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:13 -0600 Subject: baseboard/brya/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c573b92eb0a59c1660f591a3bd097347b832980 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727861 Reviewed-by: Jeremy Bettis --- baseboard/brya/baseboard.h | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index bc44a9d642..96404c4fe4 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -12,18 +12,18 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX9 config */ -#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* * This defines which pads (GPIO10/11 or GPIO64/65) are connected to * the "UART1" (NPCX_UART_PORT0) controller when used for * CONSOLE_UART. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 for UART1 */ /* EC Defines */ #define CONFIG_LTO @@ -68,7 +68,7 @@ #define CONFIG_CHARGE_MANAGER #define CONFIG_CHARGER #define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CMD_CHARGER_DUMP @@ -79,8 +79,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Common battery defines */ #define CONFIG_BATTERY_SMART @@ -181,7 +181,7 @@ #define CONFIG_USB_PD_TCPM_NCT38XX #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -189,7 +189,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD @@ -230,13 +230,13 @@ * bytes. Task stack sizes not listed here use more generic values (see * ec.tasklist). */ -#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088 -#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088 -#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152 -#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800 -#define BASEBOARD_PD_TASK_STACK_SIZE 1216 -#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088 -#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048 +#define BASEBOARD_CHARGER_TASK_STACK_SIZE 1088 +#define BASEBOARD_CHG_RAMP_TASK_STACK_SIZE 1088 +#define BASEBOARD_CHIPSET_TASK_STACK_SIZE 1152 +#define BASEBOARD_PD_INT_TASK_STACK_SIZE 800 +#define BASEBOARD_PD_TASK_STACK_SIZE 1216 +#define BASEBOARD_POWERBTN_TASK_STACK_SIZE 1088 +#define BASEBOARD_RGBKBD_TASK_STACK_SIZE 2048 #ifndef __ASSEMBLER__ @@ -248,7 +248,6 @@ #include "baseboard_usbc_config.h" #include "extpower.h" - /* * Check battery disconnect state. * This function will return if battery is initialized or not. -- cgit v1.2.1 From eee1338ad27f0490f1ea838a4495ca16a4e82fba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:09 -0600 Subject: chip/ish/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a9ef1f349696b26cfb4c3027c5b69d383da3c6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729173 Reviewed-by: Jeremy Bettis --- chip/ish/clock.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/chip/ish/clock.c b/chip/ish/clock.c index ac818f5733..f442da7370 100644 --- a/chip/ish/clock.c +++ b/chip/ish/clock.c @@ -12,8 +12,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) void clock_init(void) { -- cgit v1.2.1 From 7cdebf07e2cd45e3247900f6d48b2754af72fc99 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:42 -0600 Subject: board/agah/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I043c4ef9779d3ecf086b046cbb59d2a292507fc1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727976 Reviewed-by: Jeremy Bettis --- board/agah/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/agah/usbc_config.h b/board/agah/usbc_config.h index e5b7576d72..43e7b20411 100644 --- a/board/agah/usbc_config.h +++ b/board/agah/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C2, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C2, USBC_PORT_COUNT }; struct ps8818_reg_val { uint8_t reg; -- cgit v1.2.1 From f2981c33dbf651247232e38123336e59c9c14ff0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:26 -0600 Subject: include/temp_sensor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d2830b1897f25fe0388e70b5639399eb4a91734 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730419 Reviewed-by: Jeremy Bettis --- include/temp_sensor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/temp_sensor.h b/include/temp_sensor.h index f8b6f64508..dc2ac17f35 100644 --- a/include/temp_sensor.h +++ b/include/temp_sensor.h @@ -72,4 +72,4 @@ int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr); */ int print_temps(void); -#endif /* __CROS_EC_TEMP_SENSOR_H */ +#endif /* __CROS_EC_TEMP_SENSOR_H */ -- cgit v1.2.1 From 7141d422c1512c5eb7922dd9d0a9d43c16c7fc56 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:29 -0600 Subject: core/cortex-m/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f16b4098e165a09f17e2fe2041eb4282ba56108 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729815 Reviewed-by: Jeremy Bettis --- core/cortex-m/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m/atomic.h b/core/cortex-m/atomic.h index a09f5cc8be..d6aac70626 100644 --- a/core/cortex-m/atomic.h +++ b/core/cortex-m/atomic.h @@ -41,4 +41,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 0acd44f8621153da0aa697c9d55721bd64fbab3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:27 -0600 Subject: util/uut/l_com_port.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I674d540094d99d22aeb47605013e1d355d4a85e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730661 Reviewed-by: Jeremy Bettis --- util/uut/l_com_port.c | 56 ++++++++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/util/uut/l_com_port.c b/util/uut/l_com_port.c index 018dec9950..448ffc1ac7 100644 --- a/util/uut/l_com_port.c +++ b/util/uut/l_com_port.c @@ -100,7 +100,8 @@ void set_read_blocking(int dev_drv, bool block) memset(&tty, 0, sizeof(tty)); if (tcgetattr(dev_drv, &tty) != 0) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "set_read_blocking Error: %d Fail to get attribute " "from Device number %d.\n", errno, dev_drv); @@ -111,7 +112,8 @@ void set_read_blocking(int dev_drv, bool block) tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */ if (tcsetattr(dev_drv, TCSANOW, &tty) != 0) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "set_read_blocking Error: %d Fail to set attribute to " "Device number %d.\n", errno, dev_drv); @@ -145,7 +147,8 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields) memset(&tty, 0, sizeof(tty)); if (tcgetattr(h_dev_drv, &tty) != 0) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_config_uart Error: Fail to get attribute from " "Device number %d.\n", h_dev_drv); @@ -171,12 +174,12 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields) tty.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); tty.c_oflag = ~OPOST; - tty.c_cc[VMIN] = 0; /* read doesn't block */ + tty.c_cc[VMIN] = 0; /* read doesn't block */ tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */ - tty.c_iflag |= (com_port_fields.flow_control == 0x01) - ? (IXON | IXOFF) - : 0x00; /* xon/xoff ctrl */ + tty.c_iflag |= (com_port_fields.flow_control == 0x01) ? (IXON | IXOFF) : + 0x00; /* xon/xoff + ctrl */ tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */ /* enable reading */ @@ -191,7 +194,8 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields) tcflush(h_dev_drv, TCIFLUSH); if (tcsetattr(h_dev_drv, TCSANOW, &tty) != 0) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_config_uart Error: %d setting port handle %d: %s.\n", errno, h_dev_drv, strerror(errno)); return false; @@ -221,7 +225,6 @@ static void discard_input(int fd) do { res = read(fd, buffer, sizeof(buffer)); if (res > 0) { - /* Discard zeros in the beginning of the buffer. */ for (i = 0; i < res; i++) if (buffer[i]) @@ -250,7 +253,6 @@ static void discard_input(int fd) printf("%d zeros ignored\n", count_of_zeros); } - /****************************************************************************** * Function: int com_port_open() * @@ -268,7 +270,7 @@ static void discard_input(int fd) ***************************************************************************** */ int com_port_open(const char *com_port_dev_name, - struct comport_fields com_port_fields) + struct comport_fields com_port_fields) { int port_handler; @@ -276,15 +278,16 @@ int com_port_open(const char *com_port_dev_name, if (port_handler < 0) { display_color_msg(FAIL, - "com_port_open Error %d opening %s: %s\n", - errno, com_port_dev_name, strerror(errno)); + "com_port_open Error %d opening %s: %s\n", + errno, com_port_dev_name, strerror(errno)); return INVALID_HANDLE_VALUE; } tcgetattr(port_handler, &savetty); if (!com_config_uart(port_handler, com_port_fields)) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_port_open() Error %d, Failed on com_config_uart() %s, " "%s\n", errno, com_port_dev_name, strerror(errno)); @@ -318,7 +321,8 @@ bool com_port_close(int device_id) tcsetattr(device_id, TCSANOW, &savetty); if (close(device_id) == INVALID_HANDLE_VALUE) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_port_close() Error: %d Device com%u was not opened, " "%s.\n", errno, (uint32_t)device_id, strerror(errno)); @@ -345,14 +349,14 @@ bool com_port_close(int device_id) * ***************************************************************************** */ -bool com_port_write_bin(int device_id, const uint8_t *buffer, - uint32_t buf_size) +bool com_port_write_bin(int device_id, const uint8_t *buffer, uint32_t buf_size) { uint32_t bytes_written; bytes_written = write(device_id, buffer, buf_size); if (bytes_written != buf_size) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_port_write_bin() Error: %d Failed to write data to " "Uart Port %d, %s.\n", errno, (uint32_t)device_id, strerror(errno)); @@ -389,9 +393,10 @@ uint32_t com_port_read_bin(int device_id, uint8_t *buffer, uint32_t buf_size) if (read_bytes == -1) { display_color_msg(FAIL, - "%s() Error: %d Device number %u was not " - "opened, %s.\n", - __func__, errno, (uint32_t)device_id, strerror(errno)); + "%s() Error: %d Device number %u was not " + "opened, %s.\n", + __func__, errno, (uint32_t)device_id, + strerror(errno)); } return read_bytes; @@ -422,9 +427,9 @@ uint32_t com_port_wait_read(int device_id) fds.events = POLLIN; ret_val = poll(&fds, 1, COMMAND_TIMEOUT); if (ret_val < 0) { - display_color_msg(FAIL, - "%s() Error: %d Device number %u %s\n", - __func__, errno, (uint32_t)device_id, strerror(errno)); + display_color_msg(FAIL, "%s() Error: %d Device number %u %s\n", + __func__, errno, (uint32_t)device_id, + strerror(errno)); return 0; } @@ -434,7 +439,8 @@ uint32_t com_port_wait_read(int device_id) if (ret_val > 0) { /* Get number of bytes that are ready to be read. */ if (ioctl(device_id, FIONREAD, &bytes) < 0) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "com_port_wait_for_read() Error: %d Device number " "%u %s\n", errno, (uint32_t)device_id, strerror(errno)); -- cgit v1.2.1 From 949911763c0635b3caa49bd083f61ebaefdf0c56 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:46 -0600 Subject: board/voxel/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62114632a7b3716905d9baf2e595b7361ac63ef7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729095 Reviewed-by: Jeremy Bettis --- board/voxel/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/voxel/led.c b/board/voxel/led.c index 4be69689f7..c57a3bc1c1 100644 --- a/board/voxel/led.c +++ b/board/voxel/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From ed8ca0e4c16e4b019499d7a5f12fe95994f831d0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:09 -0600 Subject: test/usb_tcpmv2_td_pd_other.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaefc6db81b9727b3c3255964ad272e44d6e8e7c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730555 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_other.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/usb_tcpmv2_td_pd_other.c b/test/usb_tcpmv2_td_pd_other.c index 1882480150..24eca5fccb 100644 --- a/test/usb_tcpmv2_td_pd_other.c +++ b/test/usb_tcpmv2_td_pd_other.c @@ -57,7 +57,7 @@ int test_retry_count_sop(void) * The retry count for PD3 should be 2. */ TEST_EQ(verify_tcpci_tx_retry_count(TCPCI_MSG_SOP, 0, - PD_DATA_SOURCE_CAP, 2), + PD_DATA_SOURCE_CAP, 2), EC_SUCCESS, "%d"); return EC_SUCCESS; } -- cgit v1.2.1 From ebc159533f48ca49a2b30a378e21a2afe2c770a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:30 -0600 Subject: zephyr/test/drivers/isl923x/src/charge_ramp_hw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I025a81fdea08efc0c5ad73d2da04108f31b799c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730971 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/isl923x/src/charge_ramp_hw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c index c1ae9ce240..fcb1b73018 100644 --- a/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c +++ b/zephyr/test/drivers/isl923x/src/charge_ramp_hw.c @@ -3,7 +3,6 @@ * found in the LICENSE file. */ - #include #include "driver/charger/isl923x.h" @@ -16,8 +15,8 @@ #define CHARGER_NUM get_charger_num(&isl923x_drv) #define ISL923X_EMUL emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))) -ZTEST_SUITE(charge_ramp_hw, drivers_predicate_post_main, NULL, NULL, - NULL, NULL); +ZTEST_SUITE(charge_ramp_hw, drivers_predicate_post_main, NULL, NULL, NULL, + NULL); ZTEST(charge_ramp_hw, test_charge_ramp_hw_ramp) { -- cgit v1.2.1 From a1e1edfa934113bbe1b1c9daecb92a957f9fd67d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:43 -0600 Subject: board/wheelie/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50eb1e81877b91833853ea69ef1933c03169fa7a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729106 Reviewed-by: Jeremy Bettis --- board/wheelie/board.c | 66 ++++++++++++++++++++++----------------------------- 1 file changed, 29 insertions(+), 37 deletions(-) diff --git a/board/wheelie/board.c b/board/wheelie/board.c index 0ad7590a31..bd738ad14b 100644 --- a/board/wheelie/board.c +++ b/board/wheelie/board.c @@ -40,7 +40,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) /* C0 interrupt line shared by BC 1.2 and charger */ static void usb_c0_interrupt(enum gpio_signal s) @@ -68,34 +68,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -445,14 +437,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 21f0440d7664c4a17bf575c0a445ba22cc6aae6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:56 -0600 Subject: driver/tcpm/mt6370.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1ed179d2b1bf21d40574f7c7b5b701f312da151 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730095 Reviewed-by: Jeremy Bettis --- driver/tcpm/mt6370.c | 49 ++++++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/driver/tcpm/mt6370.c b/driver/tcpm/mt6370.c index 7f4cb5b3d3..15aa05bee2 100644 --- a/driver/tcpm/mt6370.c +++ b/driver/tcpm/mt6370.c @@ -16,8 +16,8 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static int mt6370_polarity; @@ -36,7 +36,6 @@ static int mt6370_init(int port) /* Only do soft-reset in shipping mode. (b:122017882) */ if (!(val & MT6370_REG_SHIPPING_OFF)) { - /* Software reset. */ rv = tcpc_write(port, MT6370_REG_SWRESET, 1); if (rv) @@ -91,7 +90,7 @@ static inline int mt6370_init_cc_params(int port, int cc_res) } static int mt6370_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int status; int rv; @@ -186,35 +185,35 @@ int mt6370_vconn_discharge(int port) /* MT6370 is a TCPCI compatible port controller */ const struct tcpm_drv mt6370_tcpm_drv = { - .init = &mt6370_init, - .release = &tcpci_tcpm_release, - .get_cc = &mt6370_get_cc, + .init = &mt6370_init, + .release = &tcpci_tcpm_release, + .get_cc = &mt6370_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &mt6370_set_cc, - .set_polarity = &mt6370_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &mt6370_set_cc, + .set_polarity = &mt6370_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tcpci_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, - .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &tcpci_get_chip_info, + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &mt6370_enter_low_power_mode, + .enter_low_power_mode = &mt6370_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; -- cgit v1.2.1 From 8626b6f857659dc246ac5beb1586bf46c02c5e72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:32 -0600 Subject: board/kracko/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6feee5aaa18c27c05fb5cd329c9f35f7432f06b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728538 Reviewed-by: Jeremy Bettis --- board/kracko/board.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/board/kracko/board.h b/board/kracko/board.h index 57f7927b86..79205a2933 100644 --- a/board/kracko/board.h +++ b/board/kracko/board.h @@ -23,13 +23,14 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM @@ -38,9 +39,9 @@ #define CONFIG_LED_ONOFF_STATES /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -73,8 +74,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -85,8 +86,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -109,21 +110,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; -- cgit v1.2.1 From ab3b2be1f73ff018ccf17cc1c922a5e6077399b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:04 -0600 Subject: board/banshee/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I00eca3532f4cf5e48c2630322b59762b55e88d6a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728003 Reviewed-by: Jeremy Bettis --- board/banshee/usbc_config.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/banshee/usbc_config.c b/board/banshee/usbc_config.c index 93292873bc..20c8983979 100644 --- a/board/banshee/usbc_config.c +++ b/board/banshee/usbc_config.c @@ -36,8 +36,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -252,8 +252,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -294,7 +294,7 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) * which powers I2C controller within retimer */ msleep(1); - } else{ + } else { ioex_set_level(rst_signal, 0); msleep(1); } -- cgit v1.2.1 From 2af74fb002f137bf25da2d2724c267573f7ed435 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:58 -0600 Subject: include/power/intel_x86.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic15a2e06f57089f9140347fa44de147190c7c298 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730387 Reviewed-by: Jeremy Bettis --- include/power/intel_x86.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/power/intel_x86.h b/include/power/intel_x86.h index 45f4a67786..4091e18a0a 100644 --- a/include/power/intel_x86.h +++ b/include/power/intel_x86.h @@ -5,7 +5,6 @@ /* Intel X86 chipset power control module for Chrome EC */ - #ifndef __CROS_EC_INTEL_X86_H #define __CROS_EC_INTEL_X86_H -- cgit v1.2.1 From 43eb12ad456c343b1fc5c481e1127659f8ca1bbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:33 -0600 Subject: driver/als_si114x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia41c09e879b0215d1dd5167b48d0deb3af67ef0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729927 Reviewed-by: Jeremy Bettis --- driver/als_si114x.c | 95 +++++++++++++++++++++-------------------------------- 1 file changed, 38 insertions(+), 57 deletions(-) diff --git a/driver/als_si114x.c b/driver/als_si114x.c index 28b8364609..1804dfb536 100644 --- a/driver/als_si114x.c +++ b/driver/als_si114x.c @@ -24,8 +24,8 @@ #endif #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) static int init(struct motion_sensor_t *s); @@ -57,10 +57,8 @@ static inline int raw_read16(const int port, const uint16_t i2c_addr_flags, } /* helper function to operate on parameter values: op can be query/set/or/and */ -static int si114x_param_op(const struct motion_sensor_t *s, - uint8_t op, - uint8_t param, - int *value) +static int si114x_param_op(const struct motion_sensor_t *s, uint8_t op, + uint8_t param, int *value) { int ret; @@ -73,13 +71,12 @@ static int si114x_param_op(const struct motion_sensor_t *s, goto error; } - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_COMMAND, op | (param & 0x1F)); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND, + op | (param & 0x1F)); if (ret != EC_SUCCESS) goto error; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - SI114X_PARAM_RD, value); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_PARAM_RD, value); if (ret != EC_SUCCESS) goto error; @@ -101,8 +98,7 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb) /* Read ALX result */ for (i = 0; i < nb; i++) { ret = raw_read16(s->port, s->i2c_spi_addr_flags, - type_data->base_data_reg + i * 2, - &val); + type_data->base_data_reg + i * 2, &val); if (ret) break; if (val == SI114X_OVERFLOW) { @@ -122,8 +118,7 @@ static int si114x_read_results(struct motion_sensor_t *s, int nb) */ if (s->type == MOTIONSENSE_TYPE_PROX) val = BIT(16) / val; - val = val * type_data->scale + - val * type_data->uscale / 10000; + val = val * type_data->scale + val * type_data->uscale / 10000; s->raw_xyz[i] = val; } @@ -184,8 +179,8 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) if (!(*event & CONFIG_ALS_SI114X_INT_EVENT)) return EC_ERROR_NOT_HANDLED; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - SI114X_IRQ_STATUS, &val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS, + &val); if (ret) return ret; @@ -193,8 +188,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) return EC_ERROR_INVAL; /* clearing IRQ */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_IRQ_STATUS, + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_STATUS, val & type_data->irq_flags); if (ret != EC_SUCCESS) CPRINTS("clearing irq failed"); @@ -274,8 +268,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v) CPRINTS("Invalid sensor type"); return EC_ERROR_INVAL; } - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_COMMAND, cmd); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND, + cmd); #ifdef CONFIG_ALS_SI114X_POLLING hook_call_deferred(&si114x_read_deferred_data, SI114x_POLLING_DELAY); @@ -330,8 +324,8 @@ static int si114x_set_chlist(const struct motion_sensor_t *s) break; } - return si114x_param_op(s, SI114X_COMMAND_PARAM_SET, - SI114X_PARAM_CHLIST, ®); + return si114x_param_op(s, SI114X_COMMAND_PARAM_SET, SI114X_PARAM_CHLIST, + ®); } #ifdef CONFIG_ALS_SI114X_CHECK_REVISION @@ -363,58 +357,53 @@ static int si114x_initialize(const struct motion_sensor_t *s) int ret, val; /* send reset command */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_COMMAND, SI114X_COMMAND_RESET); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_COMMAND, + SI114X_COMMAND_RESET); if (ret != EC_SUCCESS) return ret; msleep(20); /* hardware key, magic value */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_HW_KEY, SI114X_HW_KEY_VALUE); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_HW_KEY, + SI114X_HW_KEY_VALUE); if (ret != EC_SUCCESS) return ret; msleep(20); /* interrupt configuration, interrupt output enable */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_INT_CFG, SI114X_INT_CFG_INT_OE); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_INT_CFG, + SI114X_INT_CFG_INT_OE); if (ret != EC_SUCCESS) return ret; /* enable interrupt for certain activities */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_IRQ_ENABLE, - SI114X_IRQ_ENABLE_PS3_IE | - SI114X_IRQ_ENABLE_PS2_IE | - SI114X_IRQ_ENABLE_PS1_IE | - SI114X_IRQ_ENABLE_ALS_IE_INT0); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_IRQ_ENABLE, + SI114X_IRQ_ENABLE_PS3_IE | SI114X_IRQ_ENABLE_PS2_IE | + SI114X_IRQ_ENABLE_PS1_IE | + SI114X_IRQ_ENABLE_ALS_IE_INT0); if (ret != EC_SUCCESS) return ret; /* Only forced mode */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_MEAS_RATE, 0); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_MEAS_RATE, 0); if (ret != EC_SUCCESS) return ret; /* measure ALS every time device wakes up */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_ALS_RATE, 0); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_ALS_RATE, 0); if (ret != EC_SUCCESS) return ret; /* measure proximity every time device wakes up */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_PS_RATE, 0); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_RATE, 0); if (ret != EC_SUCCESS) return ret; /* set LED currents to maximum */ switch (SI114X_NUM_LEDS) { case 3: - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - SI114X_PS_LED3, 0x0f); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, SI114X_PS_LED3, + 0x0f); if (ret != EC_SUCCESS) return ret; ret = raw_write8(s->port, s->i2c_spi_addr_flags, @@ -444,9 +433,7 @@ static int si114x_initialize(const struct motion_sensor_t *s) return ret; } -static int set_resolution(const struct motion_sensor_t *s, - int res, - int rnd) +static int set_resolution(const struct motion_sensor_t *s, int res, int rnd) { int ret, reg1, reg2, val; /* override on resolution: set the gain. between 0 to 7 */ @@ -489,9 +476,7 @@ static int get_resolution(const struct motion_sensor_t *s) return val & 0x07; } -static int set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int set_range(struct motion_sensor_t *s, int range, int rnd) { struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s); data->scale = range >> 16; @@ -507,27 +492,23 @@ static int get_data_rate(const struct motion_sensor_t *s) return data->rate; } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, - int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s); data->rate = rate; return EC_SUCCESS; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s); data->offset = offset[X]; return EC_SUCCESS; } -static int get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) +static int get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct si114x_typed_data_t *data = SI114X_GET_TYPED_DATA(s); offset[X] = data->offset; -- cgit v1.2.1 From 131f6abf8ff17eb823f9af37bebe9611fb1db7b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:49 -0600 Subject: chip/it83xx/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6f8398975a9ed7f1bd4dc6ef014bb32c6c6726b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729217 Reviewed-by: Jeremy Bettis --- chip/it83xx/uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c index d0b645e68c..661e0724b3 100644 --- a/chip/it83xx/uart.c +++ b/chip/it83xx/uart.c @@ -17,7 +17,7 @@ #include "util.h" /* Traces on UART1 */ -#define UART_PORT 0 +#define UART_PORT 0 #define UART_PORT_HOST 1 static int init_done; -- cgit v1.2.1 From 27c21a9334062be67d2324bb2f48960fc062b258 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:48 -0600 Subject: power/icelake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09857f63ba764922c21747394fbb74e6ab45e1da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730464 Reviewed-by: Jeremy Bettis --- power/icelake.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/power/icelake.c b/power/icelake.c index 00248061e9..b06c5c51a7 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -17,20 +17,19 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(signal, value) \ gpio_set_level_verbose(CC_CHIPSET, signal, value) #else -#define GPIO_SET_LEVEL(signal, value) \ - gpio_set_level(signal, value) +#define GPIO_SET_LEVEL(signal, value) gpio_set_level(signal, value) #endif /* The wait time is ~150 msec, allow for safety margin. */ -#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) +#define IN_PCH_SLP_SUS_WAIT_TIME_USEC (250 * MSEC) -static int forcing_shutdown; /* Forced shutdown in progress? */ +static int forcing_shutdown; /* Forced shutdown in progress? */ /* Power signals list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { @@ -152,7 +151,7 @@ void chipset_handle_espi_reset_assert(void) * power button. If yes, release power button. */ if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) && - forcing_shutdown) { + forcing_shutdown) { power_button_pch_release(); forcing_shutdown = 0; } @@ -171,7 +170,6 @@ static void enable_pp5000_rail(void) power_5v_enable(task_get_current(), 1); else GPIO_SET_LEVEL(GPIO_EN_PP5000, 1); - } static void dsw_pwrok_pass_thru(void) @@ -180,8 +178,8 @@ static void dsw_pwrok_pass_thru(void) /* Pass-through DSW_PWROK to ICL. */ if (dswpwrok_in != gpio_get_level(GPIO_PCH_DSW_PWROK)) { - if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE) - && dswpwrok_in) { + if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE) && + dswpwrok_in) { /* * Once DSW_PWROK is high, reconfigure SLP_S3_L back to * an input after a short delay. @@ -208,7 +206,7 @@ static void dsw_pwrok_pass_thru(void) * ¶m level 0 deasserts the signal, other values assert the signal */ static void pwrok_signal_set(const struct intel_x86_pwrok_signal *signal, - int level) + int level) { GPIO_SET_LEVEL(signal->gpio, signal->active_low ? !level : level); } @@ -257,7 +255,6 @@ enum power_state power_handle_state(enum power_state state) common_intel_x86_handle_rsmrst(state); switch (state) { - case POWER_G3S5: if (IS_ENABLED(CONFIG_CHIPSET_SLP_S3_L_OVERRIDE)) { /* @@ -297,7 +294,8 @@ enum power_state power_handle_state(enum power_state state) * signal doesn't go high within 250 msec then go back to G3. */ if (power_wait_signals_timeout(IN_PCH_SLP_SUS_DEASSERTED, - IN_PCH_SLP_SUS_WAIT_TIME_USEC) != EC_SUCCESS) { + IN_PCH_SLP_SUS_WAIT_TIME_USEC) != + EC_SUCCESS) { CPRINTS("SLP_SUS_L didn't go high! Going back to G3."); return POWER_S5G3; } @@ -318,7 +316,7 @@ enum power_state power_handle_state(enum power_state state) GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1); /* Now wait for ALL_SYS_PWRGD. */ while (!intel_x86_get_pg_ec_all_sys_pwrgd() && - (timeout_ms > 0)) { + (timeout_ms > 0)) { msleep(1); timeout_ms--; }; -- cgit v1.2.1 From ee3a23d209e9801d38f438dc7d01d62c9de8cb5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:51 -0600 Subject: board/ghost/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e648a401402309659f9ffa31edaa692f500b732 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728407 Reviewed-by: Jeremy Bettis --- board/ghost/usbc_config.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/board/ghost/usbc_config.c b/board/ghost/usbc_config.c index f8b1df5ade..15ce0daf7e 100644 --- a/board/ghost/usbc_config.c +++ b/board/ghost/usbc_config.c @@ -25,15 +25,11 @@ #include "usb_pd_tbt.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #ifdef CONFIG_ZEPHYR -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; #endif /* CONFIG_ZEPHYR */ /* USBC TCPC configuration */ -- cgit v1.2.1 From ce6adb64c1ddb92be09fbf9b2339f4c0315fafe7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:53 -0600 Subject: baseboard/asurada/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I22d31b6a1de35d5f3fe4582bf6e5f47388c09acf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727854 Reviewed-by: Jeremy Bettis --- baseboard/asurada/usb_pd_policy.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/baseboard/asurada/usb_pd_policy.c b/baseboard/asurada/usb_pd_policy.c index 03993fcbbe..4fce60548c 100644 --- a/baseboard/asurada/usb_pd_policy.c +++ b/baseboard/asurada/usb_pd_policy.c @@ -19,8 +19,8 @@ #error Asurada reference must have at least one 3.0 A port #endif -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) int svdm_get_hpd_gpio(int port) { @@ -79,8 +79,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) if (lvl) gpio_set_level_verbose(CC_USBPD, GPIO_DP_AUX_PATH_SEL, port); - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -147,7 +146,7 @@ __override void svdm_exit_dp_mode(int port) svdm_set_hpd_gpio(port, 0); #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) -- cgit v1.2.1 From 830bd7d7406a23cdcd62905e18aff9f79866e617 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:59 -0600 Subject: zephyr/test/drivers/src/host_cmd/host_event_commands.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id967c4f553ecf7c44fc496c1104b895d03815a3b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730972 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/host_cmd/host_event_commands.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/zephyr/test/drivers/src/host_cmd/host_event_commands.c b/zephyr/test/drivers/src/host_cmd/host_event_commands.c index fec550e3c1..cbcc3dd2e8 100644 --- a/zephyr/test/drivers/src/host_cmd/host_event_commands.c +++ b/zephyr/test/drivers/src/host_cmd/host_event_commands.c @@ -48,8 +48,8 @@ ZTEST_SUITE(host_cmd_host_event_commands, drivers_predicate_post_main, host_cmd_host_event_commands_after, NULL); static enum ec_status host_event_cmd_helper(enum ec_host_event_action action, - uint8_t mask, - struct ec_response_host_event *r) + uint8_t mask, + struct ec_response_host_event *r) { enum ec_status ret_val; @@ -73,11 +73,9 @@ ZTEST_USER(host_cmd_host_event_commands, test_host_event_invalid_cmd) enum ec_status ret_val; struct ec_response_host_event result = { 0 }; - ret_val = host_event_cmd_helper(0xFF, 0, - &result); + ret_val = host_event_cmd_helper(0xFF, 0, &result); - zassert_equal(ret_val, EC_RES_INVALID_PARAM, - "Expected=%d, returned=%d", + zassert_equal(ret_val, EC_RES_INVALID_PARAM, "Expected=%d, returned=%d", EC_RES_INVALID_PARAM, ret_val); } -- cgit v1.2.1 From a434679bdb6d2992d471f795879cb6f0825e310a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:30 -0600 Subject: board/sasukette/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If6a3a1c80e6f3a14cba2a5f82a2437556e4af3af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728899 Reviewed-by: Jeremy Bettis --- board/sasukette/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/sasukette/board.h b/board/sasukette/board.h index a1d987aaf3..fce9cd3978 100644 --- a/board/sasukette/board.h +++ b/board/sasukette/board.h @@ -60,8 +60,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ #ifndef __ASSEMBLER__ @@ -70,10 +70,10 @@ /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_TEMP_SENSOR_3, /* ADC15*/ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15*/ ADC_CH_COUNT }; -- cgit v1.2.1 From 1c43c9ed86e15957472914550da4f6c9d32b92f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:26 -0600 Subject: board/voema/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I963413080257e5864c055150bf5b1045fa0dd426 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729072 Reviewed-by: Jeremy Bettis --- board/voema/board.h | 106 ++++++++++++++++++++++++---------------------------- 1 file changed, 49 insertions(+), 57 deletions(-) diff --git a/board/voema/board.h b/board/voema/board.h index b5f8dc4ec8..15233edbe0 100644 --- a/board/voema/board.h +++ b/board/voema/board.h @@ -45,7 +45,7 @@ /* TCS3400 ALS */ #define CONFIG_ALS -#define ALS_COUNT 1 +#define ALS_COUNT 1 #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) @@ -55,36 +55,36 @@ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 65000 -#define PD_MAX_CURRENT_MA 3250 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 65000 +#define PD_MAX_CURRENT_MA 3250 +#define PD_MAX_VOLTAGE_MV 20000 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ #undef CONFIG_SYV682X_HV_ILIM #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 -#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C0/C1 */ #define CONFIG_USB_PD_FRS_PPC #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #undef CONFIG_USB_PD_TCPM_TUSB422 @@ -98,8 +98,8 @@ #undef CONFIG_FANS /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -111,45 +111,44 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -161,10 +160,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -175,11 +171,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 44d9369d103aed561da0f651320243d02cfcc3ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:37 -0600 Subject: board/shotzo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e4bd03a7d10aa06051d1d8e1056478b65d145a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728940 Reviewed-by: Jeremy Bettis --- board/shotzo/led.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/shotzo/led.c b/board/shotzo/led.c index 761b4b4047..abbcc3e57d 100644 --- a/board/shotzo/led.c +++ b/board/shotzo/led.c @@ -18,10 +18,8 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -29,7 +27,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -127,9 +125,9 @@ static void led_set_battery(void) */ if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } } @@ -158,8 +156,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); @@ -186,8 +184,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From d50c3e2d4503aa93e1cb400cdd1e7b49b5c4f5e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:54 -0600 Subject: driver/retimer/tdp142.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4fc3716f55d6bde3bc51d13d01be330bfd36a14a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730069 Reviewed-by: Jeremy Bettis --- driver/retimer/tdp142.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/retimer/tdp142.h b/driver/retimer/tdp142.h index 8346a233a5..ba4031b7e3 100644 --- a/driver/retimer/tdp142.h +++ b/driver/retimer/tdp142.h @@ -20,11 +20,11 @@ #define TDP142_I2C_ADDR3 0x0F /* Registers */ -#define TDP142_REG_GENERAL 0x0A -#define TDP142_GENERAL_CTLSEL GENMASK(1, 0) -#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3) -#define TDP142_GENERAL_EQ_OVERRIDE BIT(4) -#define TDP142_GENERAL_SWAP_HPDIN BIT(5) +#define TDP142_REG_GENERAL 0x0A +#define TDP142_GENERAL_CTLSEL GENMASK(1, 0) +#define TDP142_GENERAL_HPDIN_OVRRIDE BIT(3) +#define TDP142_GENERAL_EQ_OVERRIDE BIT(4) +#define TDP142_GENERAL_SWAP_HPDIN BIT(5) enum tdp142_ctlsel { TDP142_CTLSEL_SHUTDOWN, -- cgit v1.2.1 From 13af2f2b1f3d08851f5282c275f08228b445aaf9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:03 -0600 Subject: chip/ish/aontaskfw/ish_aon_share.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a42aa0ee8fad5eee06eed11d8410de65a032cbd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729171 Reviewed-by: Jeremy Bettis --- chip/ish/aontaskfw/ish_aon_share.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/ish/aontaskfw/ish_aon_share.h b/chip/ish/aontaskfw/ish_aon_share.h index 20b36ec2b2..9fa4239128 100644 --- a/chip/ish/aontaskfw/ish_aon_share.h +++ b/chip/ish/aontaskfw/ish_aon_share.h @@ -11,13 +11,12 @@ #include "power_mgt.h" /* magic ID for valid aontask image check */ -#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ +#define AON_MAGIC_ID 0x544E4F41 /*"AONT"*/ /* aontask error code */ -#define AON_SUCCESS 0 -#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 -#define AON_ERROR_DMA_FAILED 2 - +#define AON_SUCCESS 0 +#define AON_ERROR_NOT_SUPPORT_POWER_MODE 1 +#define AON_ERROR_DMA_FAILED 2 /* shared data structure between main FW and aontask */ struct ish_aon_share { -- cgit v1.2.1 From c3e865d40a226203847dfa29f8bd4b67e978c291 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:32 -0600 Subject: board/fennel/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55368c9d1a91d4afbc020ce86bed0e2965207ef7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728363 Reviewed-by: Jeremy Bettis --- board/fennel/board.c | 145 +++++++++++++++++++++++---------------------------- 1 file changed, 65 insertions(+), 80 deletions(-) diff --git a/board/fennel/board.c b/board/fennel/board.c index b9adcad237..74b3e4e720 100644 --- a/board/fennel/board.c +++ b/board/fennel/board.c @@ -47,8 +47,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -60,40 +60,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -101,8 +95,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -158,8 +152,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -240,12 +233,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -302,8 +295,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -320,8 +312,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -360,17 +351,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ /* Lid accel private data */ @@ -417,20 +404,20 @@ struct motion_sensor_t icm42607_base_accel = { }; struct motion_sensor_t icm42607_base_gyro = { - .name = "Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm42607_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm42607_data, - .port = CONFIG_SPI_ACCEL_PORT, - .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT), - .default_range = 1000, /* dps */ - .rot_standard_ref = NULL, - .min_frequency = ICM42607_GYRO_MIN_FREQ, - .max_frequency = ICM42607_GYRO_MAX_FREQ, + .name = "Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM42607, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm42607_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm42607_data, + .port = CONFIG_SPI_ACCEL_PORT, + .i2c_spi_addr_flags = ACCEL_MK_SPI_ADDR_FLAGS(CONFIG_SPI_ACCEL_PORT), + .default_range = 1000, /* dps */ + .rot_standard_ref = NULL, + .min_frequency = ICM42607_GYRO_MIN_FREQ, + .max_frequency = ICM42607_GYRO_MAX_FREQ, }; struct motion_sensor_t motion_sensors[] = { @@ -522,18 +509,18 @@ static void board_detect_motionsensor(void) if (base_accelgyro_config != BASE_GYRO_NONE) return; /* Check base accelgyro chip */ - ret = icm_read8(&icm42607_base_accel, - ICM42607_REG_WHO_AM_I, &val); + ret = icm_read8(&icm42607_base_accel, ICM42607_REG_WHO_AM_I, &val); if (ret) ccprints("Get ICM fail."); if (val == ICM42607_CHIP_ICM42607P) { motion_sensors[BASE_ACCEL] = icm42607_base_accel; motion_sensors[BASE_GYRO] = icm42607_base_gyro; } - base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) - ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160; - ccprints("BASE Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P) - ? "ICM42607" : "BMI160"); + base_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ? + BASE_GYRO_ICM426XX : + BASE_GYRO_BMI160; + ccprints("BASE Accelgyro: %s", + (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160"); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, HOOK_PRIO_DEFAULT); @@ -559,7 +546,7 @@ void motion_interrupt(enum gpio_signal signal) } const struct it8801_pwm_t it8801_pwm_channels[] = { - [IT8801_PWM_CH_KBLIGHT] = {.index = 4}, + [IT8801_PWM_CH_KBLIGHT] = { .index = 4 }, }; void board_kblight_init(void) @@ -575,11 +562,11 @@ bool board_has_kb_backlight(void) #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* Battery functions */ -#define SB_SMARTCHARGE 0x26 +#define SB_SMARTCHARGE 0x26 /* Quick charge enable bit */ -#define SMART_QUICK_CHARGE 0x02 +#define SMART_QUICK_CHARGE 0x02 /* Quick charge support bit */ -#define MODE_QUICK_CHARGE_SUPPORT 0x01 +#define MODE_QUICK_CHARGE_SUPPORT 0x01 static void sb_quick_charge_mode(int enable) { @@ -650,8 +637,8 @@ int board_get_battery_i2c(void) } #ifdef SECTION_IS_RW -static int it8801_get_target_channel(enum pwm_channel *channel, - int type, int index) +static int it8801_get_target_channel(enum pwm_channel *channel, int type, + int index) { switch (type) { case EC_PWM_TYPE_GENERIC: @@ -674,14 +661,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - duty = (uint32_t) p->duty * 255 / 65535; + duty = (uint32_t)p->duty * 255 / 65535; it8801_pwm_set_raw_duty(channel, duty); it8801_pwm_enable(channel, p->duty > 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); static enum ec_status @@ -695,12 +681,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255; + r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255; args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); #endif -- cgit v1.2.1 From 23211768f6ef822ae0bd20cdb7b25143ef1d7fca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:02 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd9d6f57f6470981af7f8bad9fbe41ff67607742 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730955 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/integration/usbc/usb.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb.c b/zephyr/test/drivers/src/integration/usbc/usb.c index 93a37a356f..4b8cd2fe11 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb.c +++ b/zephyr/test/drivers/src/integration/usbc/usb.c @@ -122,14 +122,12 @@ ZTEST(integration_usb, test_attach_drp) /* Attach emulated sink */ tcpci_partner_init(&my_drp, PD_REV20); - my_drp.extensions = - tcpci_drp_emul_init( - &drp_ext, &my_drp, PD_ROLE_SINK, - tcpci_src_emul_init(&src_ext, &my_drp, NULL), - tcpci_snk_emul_init(&snk_ext, &my_drp, NULL)); - - zassert_ok(tcpci_partner_connect_to_tcpci(&my_drp, tcpci_emul), - NULL); + my_drp.extensions = tcpci_drp_emul_init( + &drp_ext, &my_drp, PD_ROLE_SINK, + tcpci_src_emul_init(&src_ext, &my_drp, NULL), + tcpci_snk_emul_init(&snk_ext, &my_drp, NULL)); + + zassert_ok(tcpci_partner_connect_to_tcpci(&my_drp, tcpci_emul), NULL); /* Wait for PD negotiation */ k_sleep(K_SECONDS(10)); -- cgit v1.2.1 From 08d61e3e32222e83f9533c0bef383dced030b18c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:58 -0600 Subject: core/cortex-m/vecttable.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d27a14ec3d01581df669496af767c9e5d654fde Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729827 Reviewed-by: Jeremy Bettis --- core/cortex-m/vecttable.c | 355 +++++++++------------------------------------- 1 file changed, 69 insertions(+), 286 deletions(-) diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c index 4897376c1b..e89eca17c0 100644 --- a/core/cortex-m/vecttable.c +++ b/core/cortex-m/vecttable.c @@ -22,18 +22,16 @@ typedef void (*func)(void); void __attribute__((used, naked)) default_handler(void); void default_handler() { - asm( - ".thumb_func\n" - " b exception_panic" - ); + asm(".thumb_func\n" + " b exception_panic"); } #define table(x) x -#define weak_with_default __attribute__((used,weak,alias("default_handler"))) +#define weak_with_default __attribute__((used, weak, alias("default_handler"))) -#define vec(name) extern void weak_with_default name ## _handler(void); -#define irq(num) vec(irq_ ## num) +#define vec(name) extern void weak_with_default name##_handler(void); +#define irq(num) vec(irq_##num) #define item(name) extern void name(void); #define null @@ -59,21 +57,19 @@ void weak_with_default svc_handler(int desched, task_id_t resched); * This approach differs slightly from the one in the document, * it only loads r0 (desched) and r1 (resched) for svc_handler. */ -void __attribute__((used,naked)) svc_helper_handler(void); +void __attribute__((used, naked)) svc_helper_handler(void); void svc_helper_handler() { - asm( - ".thumb_func\n" - " tst lr, #4 /* see if called from supervisor mode */\n" - " mrs r2, msp /* get the correct stack pointer into r2 */\n" - " it ne\n" - " mrsne r2, psp\n" - " ldr r1, [r2, #4] /* get regs from stack frame */\n" - " ldr r0, [r2]\n" - " b %0 /* call svc_handler */\n" - : - : "i"(svc_handler) - ); + asm(".thumb_func\n" + " tst lr, #4 /* see if called from supervisor mode */\n" + " mrs r2, msp /* get the correct stack pointer into r2 */\n" + " it ne\n" + " mrsne r2, psp\n" + " ldr r1, [r2, #4] /* get regs from stack frame */\n" + " ldr r0, [r2]\n" + " b %0 /* call svc_handler */\n" + : + : "i"(svc_handler)); } #endif /* PASS 1 */ @@ -100,277 +96,64 @@ void svc_helper_handler() #pragma clang diagnostic ignored "-Winitializer-overrides" #endif /* __clang__ */ -#define table(x) \ - const func vectors[] __attribute__((section(".text.vecttable"))) = { \ - x \ - [IRQ_UNUSED_OFFSET] = null \ - }; +#define table(x) \ + const func vectors[] __attribute__((section( \ + ".text.vecttable"))) = { x[IRQ_UNUSED_OFFSET] = null }; -#define vec(name) name ## _handler, -#define irq(num) [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = vec(irq_ ## num) +#define vec(name) name##_handler, +#define irq(num) \ + [num < CONFIG_IRQ_COUNT ? num + IRQ_OFFSET : IRQ_UNUSED_OFFSET] = \ + vec(irq_##num) #define item(name) name, -#define null (void*)0, +#define null (void *)0, #endif /* PASS 2 */ -table( - item(stack_end) - item(reset) - vec(nmi) - vec(hard_fault) - vec(mpu_fault) - vec(bus_fault) - vec(usage_fault) - null - null - null - null - item(svc_helper_handler) - vec(debug) - null - vec(pendsv) - vec(sys_tick) - irq(0) - irq(1) - irq(2) - irq(3) - irq(4) - irq(5) - irq(6) - irq(7) - irq(8) - irq(9) - irq(10) - irq(11) - irq(12) - irq(13) - irq(14) - irq(15) - irq(16) - irq(17) - irq(18) - irq(19) - irq(20) - irq(21) - irq(22) - irq(23) - irq(24) - irq(25) - irq(26) - irq(27) - irq(28) - irq(29) - irq(30) - irq(31) - irq(32) - irq(33) - irq(34) - irq(35) - irq(36) - irq(37) - irq(38) - irq(39) - irq(40) - irq(41) - irq(42) - irq(43) - irq(44) - irq(45) - irq(46) - irq(47) - irq(48) - irq(49) - irq(50) - irq(51) - irq(52) - irq(53) - irq(54) - irq(55) - irq(56) - irq(57) - irq(58) - irq(59) - irq(60) - irq(61) - irq(62) - irq(63) - irq(64) - irq(65) - irq(66) - irq(67) - irq(68) - irq(69) - irq(70) - irq(71) - irq(72) - irq(73) - irq(74) - irq(75) - irq(76) - irq(77) - irq(78) - irq(79) - irq(80) - irq(81) - irq(82) - irq(83) - irq(84) - irq(85) - irq(86) - irq(87) - irq(88) - irq(89) - irq(90) - irq(91) - irq(92) - irq(93) - irq(94) - irq(95) - irq(96) - irq(97) - irq(98) - irq(99) - irq(100) - irq(101) - irq(102) - irq(103) - irq(104) - irq(105) - irq(106) - irq(107) - irq(108) - irq(109) - irq(110) - irq(111) - irq(112) - irq(113) - irq(114) - irq(115) - irq(116) - irq(117) - irq(118) - irq(119) - irq(120) - irq(121) - irq(122) - irq(123) - irq(124) - irq(125) - irq(126) - irq(127) - irq(128) - irq(129) - irq(130) - irq(131) - irq(132) - irq(133) - irq(134) - irq(135) - irq(136) - irq(137) - irq(138) - irq(139) - irq(140) - irq(141) - irq(142) - irq(143) - irq(144) - irq(145) - irq(146) - irq(147) - irq(148) - irq(149) - irq(150) - irq(151) - irq(152) - irq(153) - irq(154) - irq(155) - irq(156) - irq(157) - irq(158) - irq(159) - irq(160) - irq(161) - irq(162) - irq(163) - irq(164) - irq(165) - irq(166) - irq(167) - irq(168) - irq(169) - irq(170) - irq(171) - irq(172) - irq(173) - irq(174) - irq(175) - irq(176) - irq(177) - irq(178) - irq(179) - irq(180) - irq(181) - irq(182) - irq(183) - irq(184) - irq(185) - irq(186) - irq(187) - irq(188) - irq(189) - irq(190) - irq(191) - irq(192) - irq(193) - irq(194) - irq(195) - irq(196) - irq(197) - irq(198) - irq(199) - irq(200) - irq(201) - irq(202) - irq(203) - irq(204) - irq(205) - irq(206) - irq(207) - irq(208) - irq(209) - irq(210) - irq(211) - irq(212) - irq(213) - irq(214) - irq(215) - irq(216) - irq(217) - irq(218) - irq(219) - irq(220) - irq(221) - irq(222) - irq(223) - irq(224) - irq(225) - irq(226) - irq(227) - irq(228) - irq(229) - irq(230) - irq(231) - irq(232) - irq(233) - irq(234) - irq(235) - irq(236) - irq(237) - irq(238) - irq(239) -) +table(item(stack_end) item(reset) vec(nmi) vec(hard_fault) vec(mpu_fault) vec( + bus_fault) vec(usage_fault) null null null null item(svc_helper_handler) vec(debug) + null vec(pendsv) vec(sys_tick) irq(0) irq(1) irq(2) irq(3) irq(4) irq( + 5) irq(6) irq(7) irq(8) irq(9) irq(10) irq(11) irq(12) irq(13) + irq(14) irq(15) irq(16) irq(17) irq(18) irq(19) irq(20) irq( + 21) irq(22) irq(23) irq(24) irq(25) irq(26) irq(27) + irq(28) irq(29) irq(30) irq(31) irq(32) irq(33) irq( + 34) irq(35) irq(36) irq(37) irq(38) irq(39) + irq(40) irq(41) irq(42) irq(43) irq(44) irq( + 45) irq(46) irq(47) irq(48) irq(49) + irq(50) irq(51) irq(52) irq(53) irq( + 54) irq(55) irq(56) irq(57) + irq(58) irq(59) irq(60) irq( + 61) irq(62) irq(63) + irq(64) irq(65) irq( + 66) irq(67) + irq(68) irq( + 69) irq(70) + irq(71) irq(72) irq(73) irq(74) irq(75) irq(76) irq(77) irq(78) irq(79) irq(80) irq(81) irq(82) irq(83) irq(84) irq(85) irq(86) irq(87) irq(88) irq(89) irq(90) irq(91) irq(92) irq(93) irq(94) irq(95) irq(96) irq(97) irq( + 98) irq(99) + irq(100) irq(101) irq(102) irq(103) irq(104) irq(105) irq(106) irq( + 107) irq(108) irq(109) irq(110) irq(111) irq(112) irq(113) irq(114) irq(115) + irq(116) irq(117) irq(118) irq(119) irq(120) irq(121) irq(122) irq( + 123) irq(124) irq(125) irq(126) irq(127) irq(128) irq(129) irq(130) irq(131) + irq(132) irq(133) irq(134) irq(135) irq(136) irq(137) irq(138) irq( + 139) irq(140) irq(141) irq(142) irq(143) irq(144) irq(145) irq(146) irq(147) + irq(148) irq(149) irq(150) irq(151) irq(152) irq(153) irq(154) irq( + 155) irq(156) irq(157) irq(158) irq(159) irq(160) irq(161) irq(162) irq(163) + irq(164) irq(165) irq(166) irq(167) irq(168) irq(169) irq(170) irq( + 171) irq(172) irq(173) irq(174) irq(175) irq(176) irq(177) irq(178) + irq(179) irq(180) irq(181) irq(182) irq(183) irq(184) irq(185) irq( + 186) irq(187) irq(188) irq(189) irq(190) irq(191) irq(192) + irq(193) irq(194) irq(195) irq(196) irq(197) irq(198) irq( + 199) irq(200) irq(201) irq(202) irq(203) irq(204) + irq(205) irq(206) irq(207) irq(208) irq(209) irq( + 210) irq(211) irq(212) irq(213) irq(214) + irq(215) irq(216) irq(217) irq(218) irq( + 219) irq(220) irq(221) irq(222) + irq(223) irq(224) irq(225) irq( + 226) irq(227) irq(228) + irq(229) irq(230) irq(231) irq( + 232) irq(233) irq(234) + irq(235) irq(236) irq( + 237) irq(238) + irq(239)) #if PASS == 2 #ifdef __clang__ -- cgit v1.2.1 From 460b0ac3bd7a7163da882d9971c7f95179bf4c3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:17 -0600 Subject: common/rtc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d0e84810967dc1e3b45b7756724e29c5c7ce49b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729706 Reviewed-by: Jeremy Bettis --- common/rtc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/common/rtc.c b/common/rtc.c index 670e86d707..4c1e554f10 100644 --- a/common/rtc.c +++ b/common/rtc.c @@ -8,9 +8,8 @@ #include "rtc.h" -static uint16_t days_since_year_start[12] = { - 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 -}; +static uint16_t days_since_year_start[12] = { 0, 31, 59, 90, 120, 151, + 181, 212, 243, 273, 304, 334 }; /* Conversion between calendar date and seconds eclapsed since 1970-01-01 */ uint32_t date_to_sec(struct calendar_date time) @@ -25,8 +24,8 @@ uint32_t date_to_sec(struct calendar_date time) } sec += (days_since_year_start[time.month - 1] + - (IS_LEAP_YEAR(time.year) && time.month > 2) + - (time.day - 1)) * SECS_PER_DAY; + (IS_LEAP_YEAR(time.year) && time.month > 2) + (time.day - 1)) * + SECS_PER_DAY; /* add the accumulated time in seconds from 1970 to 2000 */ return sec + SECS_TILL_YEAR_2K; @@ -55,7 +54,8 @@ struct calendar_date sec_to_date(uint32_t sec) } for (i = 1; i < 12; i++) { if (days_since_year_start[i] + - (IS_LEAP_YEAR(time.year) && (i >= 2)) >= day_tmp) + (IS_LEAP_YEAR(time.year) && (i >= 2)) >= + day_tmp) break; } time.month = i; -- cgit v1.2.1 From d88f309af75cb53a89858d16c5271ae2e518f7cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:47 -0600 Subject: zephyr/emul/emul_bmi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I816fe1fb147d7471af58e7ff9861ce29f4eab27f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730686 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_bmi.c | 81 +++++++++++++++++++++++++------------------------- 1 file changed, 41 insertions(+), 40 deletions(-) diff --git a/zephyr/emul/emul_bmi.c b/zephyr/emul/emul_bmi.c index 37dba43e6d..bdc440a36f 100644 --- a/zephyr/emul/emul_bmi.c +++ b/zephyr/emul/emul_bmi.c @@ -21,7 +21,7 @@ LOG_MODULE_REGISTER(emul_bmi); #include "driver/accelgyro_bmi260.h" #include "driver/accelgyro_bmi_common.h" -#define BMI_DATA_FROM_I2C_EMUL(_emul) \ +#define BMI_DATA_FROM_I2C_EMUL(_emul) \ CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ struct bmi_emul_data, common) @@ -296,17 +296,17 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis, case BMI_EMUL_ACC_X: data->off_acc_x = val; data->reg[data->type_data->acc_off_reg] = - bmi_emul_acc_off_to_nvm(data->off_acc_x); + bmi_emul_acc_off_to_nvm(data->off_acc_x); break; case BMI_EMUL_ACC_Y: data->off_acc_y = val; data->reg[data->type_data->acc_off_reg + 1] = - bmi_emul_acc_off_to_nvm(data->off_acc_y); + bmi_emul_acc_off_to_nvm(data->off_acc_y); break; case BMI_EMUL_ACC_Z: data->off_acc_z = val; data->reg[data->type_data->acc_off_reg + 2] = - bmi_emul_acc_off_to_nvm(data->off_acc_z); + bmi_emul_acc_off_to_nvm(data->off_acc_z); break; case BMI_EMUL_GYR_X: data->off_gyr_x = val; @@ -314,9 +314,9 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis, data->reg[data->type_data->gyr_off_reg] = gyr_off & 0xff; gyr98_shift = 0; data->reg[data->type_data->gyr98_off_reg] &= - ~(0x3 << gyr98_shift); + ~(0x3 << gyr98_shift); data->reg[data->type_data->gyr98_off_reg] |= - (gyr_off & 0x300) >> (8 - gyr98_shift); + (gyr_off & 0x300) >> (8 - gyr98_shift); break; case BMI_EMUL_GYR_Y: data->off_gyr_y = val; @@ -324,9 +324,9 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis, data->reg[data->type_data->gyr_off_reg + 1] = gyr_off & 0xff; gyr98_shift = 2; data->reg[data->type_data->gyr98_off_reg] &= - ~(0x3 << gyr98_shift); + ~(0x3 << gyr98_shift); data->reg[data->type_data->gyr98_off_reg] |= - (gyr_off & 0x300) >> (8 - gyr98_shift); + (gyr_off & 0x300) >> (8 - gyr98_shift); break; case BMI_EMUL_GYR_Z: data->off_gyr_z = val; @@ -334,9 +334,9 @@ void bmi_emul_set_off(struct i2c_emul *emul, enum bmi_emul_axis axis, data->reg[data->type_data->gyr_off_reg + 2] = gyr_off & 0xff; gyr98_shift = 4; data->reg[data->type_data->gyr98_off_reg] &= - ~(0x3 << gyr98_shift); + ~(0x3 << gyr98_shift); data->reg[data->type_data->gyr98_off_reg] |= - (gyr_off & 0x300) >> (8 - gyr98_shift); + (gyr_off & 0x300) >> (8 - gyr98_shift); break; } } @@ -595,8 +595,8 @@ static void bmi_emul_set_current_frame(struct i2c_emul *emul, data = BMI_DATA_FROM_I2C_EMUL(emul); data->fifo_frame_byte = 0; - data->fifo_frame_len = bmi_emul_get_frame_len(emul, frame, tag_time, - header); + data->fifo_frame_len = + bmi_emul_get_frame_len(emul, frame, tag_time, header); /* Empty FIFO frame */ if (frame == NULL) { if (tag_time && header) { @@ -628,11 +628,14 @@ static void bmi_emul_set_current_frame(struct i2c_emul *emul, if (header) { data->fifo[0] = BMI_EMUL_FIFO_HEAD_DATA; data->fifo[0] |= frame->type & BMI_EMUL_FRAME_MAG ? - BMI_EMUL_FIFO_HEAD_DATA_MAG : 0; + BMI_EMUL_FIFO_HEAD_DATA_MAG : + 0; data->fifo[0] |= frame->type & BMI_EMUL_FRAME_GYR ? - BMI_EMUL_FIFO_HEAD_DATA_GYR : 0; + BMI_EMUL_FIFO_HEAD_DATA_GYR : + 0; data->fifo[0] |= frame->type & BMI_EMUL_FRAME_ACC ? - BMI_EMUL_FIFO_HEAD_DATA_ACC : 0; + BMI_EMUL_FIFO_HEAD_DATA_ACC : + 0; data->fifo[0] |= frame->tag & BMI_EMUL_FIFO_HEAD_DATA_TAG_MASK; i = 1; } @@ -688,11 +691,11 @@ static void bmi_emul_updata_int_off(struct i2c_emul *emul) data = BMI_DATA_FROM_I2C_EMUL(emul); data->off_acc_x = bmi_emul_acc_nvm_to_off( - data->reg[data->type_data->acc_off_reg]); + data->reg[data->type_data->acc_off_reg]); data->off_acc_y = bmi_emul_acc_nvm_to_off( - data->reg[data->type_data->acc_off_reg + 1]); + data->reg[data->type_data->acc_off_reg + 1]); data->off_acc_z = bmi_emul_acc_nvm_to_off( - data->reg[data->type_data->acc_off_reg + 2]); + data->reg[data->type_data->acc_off_reg + 2]); gyr98 = data->reg[data->type_data->gyr98_off_reg]; @@ -855,10 +858,9 @@ static int bmi_emul_handle_write(struct i2c_emul *emul, int reg, uint8_t val, } /** Check description in emul_bmi.h */ -void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift, - int gyr_shift, int acc_reg, int gyr_reg, - int sensortime_reg, bool acc_off_en, - bool gyr_off_en) +void bmi_emul_state_to_reg(struct i2c_emul *emul, int acc_shift, int gyr_shift, + int acc_reg, int gyr_reg, int sensortime_reg, + bool acc_off_en, bool gyr_off_en) { struct bmi_emul_data *data; int32_t val[3]; @@ -945,9 +947,8 @@ uint16_t bmi_emul_fifo_len(struct i2c_emul *emul, bool tag_time, bool header) } /** Check description in emul_bmi.h */ -uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte, - bool tag_time, bool header, int acc_shift, - int gyr_shift) +uint8_t bmi_emul_get_fifo_data(struct i2c_emul *emul, int byte, bool tag_time, + bool header, int acc_shift, int gyr_shift) { struct bmi_emul_data *data; int ret; @@ -1031,8 +1032,7 @@ static int bmi_emul_handle_read(struct i2c_emul *emul, int reg, uint8_t *buf, * * @return 0 indicating success (always) */ -static int bmi_emul_init(const struct emul *emul, - const struct device *parent) +static int bmi_emul_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = cfg->data; @@ -1066,7 +1066,7 @@ static int bmi_emul_init(const struct emul *emul, return ret; } -#define BMI_EMUL(n) \ +#define BMI_EMUL(n) \ static struct bmi_emul_data bmi_emul_data_##n = { \ .error_on_ro_write = DT_INST_PROP(n, error_on_ro_write),\ .error_on_wo_read = DT_INST_PROP(n, error_on_wo_read), \ @@ -1084,27 +1084,28 @@ static int bmi_emul_init(const struct emul *emul, .finish_read = NULL, \ .access_reg = NULL, \ }, \ - }; \ - \ - static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .data = &bmi_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(bmi_emul_init, DT_DRV_INST(n), &bmi_emul_cfg_##n, \ + }; \ + \ + static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .data = &bmi_emul_data_##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(bmi_emul_init, DT_DRV_INST(n), &bmi_emul_cfg_##n, \ &bmi_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL) -#define BMI_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &bmi_emul_data_##n.common.emul; +#define BMI_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &bmi_emul_data_##n.common.emul; /** Check description in emul_bmi.h */ struct i2c_emul *bmi_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(BMI_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From de06417b0d7c8114e6d8bd3ed3784cb78b19d941 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:20 -0600 Subject: board/quackingstick/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2f8250911dedcee5767a95ea9ed9f9c34c8f1b3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728871 Reviewed-by: Jeremy Bettis --- board/quackingstick/usbc_config.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/board/quackingstick/usbc_config.c b/board/quackingstick/usbc_config.c index 1873e916ad..c4853a2041 100644 --- a/board/quackingstick/usbc_config.c +++ b/board/quackingstick/usbc_config.c @@ -13,8 +13,8 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -25,16 +25,16 @@ const struct charger_config_t chg_chips[] = { }; struct temp_chg_step { - int low; /* temp thershold ('C) to lower level*/ - int high; /* temp thershold ('C) to higher level */ - int current; /* charging limitation (mA) */ + int low; /* temp thershold ('C) to lower level*/ + int high; /* temp thershold ('C) to higher level */ + int current; /* charging limitation (mA) */ }; static const struct temp_chg_step temp_chg_table[] = { - {.low = 0, .high = 50, .current = 3000}, /* Lv0: normal charge */ - {.low = 48, .high = 53, .current = 1500}, - {.low = 51, .high = 56, .current = 1000}, - {.low = 54, .high = 100, .current = 800}, + { .low = 0, .high = 50, .current = 3000 }, /* Lv0: normal charge */ + { .low = 48, .high = 53, .current = 1500 }, + { .low = 51, .high = 56, .current = 1000 }, + { .low = 54, .high = 100, .current = 800 }, }; #define NUM_TEMP_CHG_LEVELS ARRAY_SIZE(temp_chg_table) @@ -64,8 +64,9 @@ int charger_profile_override(struct charge_state_data *curr) if (current_level >= NUM_TEMP_CHG_LEVELS) current_level = NUM_TEMP_CHG_LEVELS - 1; - curr->requested_current = MIN(curr->requested_current, - temp_chg_table[current_level].current); + curr->requested_current = + MIN(curr->requested_current, + temp_chg_table[current_level].current); } /* Lower the max requested voltage to 5V when battery is full. */ -- cgit v1.2.1 From e31e367cab9b626d379d05232278b589bdb9777d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:15 -0600 Subject: board/vilboz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I34f36446894da02ed28f22848cd582f8c9ceb373 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729057 Reviewed-by: Jeremy Bettis --- board/vilboz/board.c | 35 +++++++++++++---------------------- 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/board/vilboz/board.c b/board/vilboz/board.c index 4e0461469d..b183d74f27 100644 --- a/board/vilboz/board.c +++ b/board/vilboz/board.c @@ -33,8 +33,8 @@ #include "usb_mux.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* This I2C moved. Temporarily detect and support the V0 HW. */ int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1; @@ -55,17 +55,13 @@ static struct stprivate_data g_lis2dwl_data; static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ struct motion_sensor_t motion_sensors[] = { @@ -219,8 +215,7 @@ void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -241,7 +236,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -323,7 +317,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -367,8 +360,7 @@ int board_pd_set_frs_enable(int port, int enable) /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -509,7 +501,7 @@ const int usb_port_enable[USBA_PORT_COUNT] = { }; __override void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) + int max_ma, int charge_mv) { /* * Limit the input current to 95% negotiated limit, @@ -517,7 +509,6 @@ __override void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 276e0ec5657658df282d6e3db218c99ab15e7aa1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:41 -0600 Subject: board/gooey/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1182d97115b6edb15965d2aeb0f8c3f127f531af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728425 Reviewed-by: Jeremy Bettis --- board/gooey/led.c | 57 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/board/gooey/led.c b/board/gooey/led.c index 6d55ce2932..3c8db4d897 100644 --- a/board/gooey/led.c +++ b/board/gooey/led.c @@ -11,41 +11,46 @@ #include "gpio.h" #include "pwm.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, + 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From cc14c5111cd1f224b189d7469780e813a0e66e2e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:11 -0600 Subject: baseboard/volteer/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I410d2ea926366f69addf4b7aed28c14a6a9bc14f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727947 Reviewed-by: Jeremy Bettis --- baseboard/volteer/baseboard.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/baseboard/volteer/baseboard.h b/baseboard/volteer/baseboard.h index c7f7c0d047..e3ebee7c38 100644 --- a/baseboard/volteer/baseboard.h +++ b/baseboard/volteer/baseboard.h @@ -13,11 +13,11 @@ /* * By default, enable all console messages excepted HC */ -#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) +#define CC_DEFAULT (CC_ALL & ~(BIT(CC_HOSTCMD))) /* NPCX7 config */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS @@ -94,10 +94,10 @@ #define CONFIG_CMD_ACCEL_INFO /* Thermal features */ -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_POWER -#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK +#define GPIO_TEMP_SENSOR_POWER GPIO_PG_EC_DSW_PWROK #define CONFIG_THERMISTOR #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B #define CONFIG_THROTTLE_AP @@ -107,7 +107,7 @@ #define CONFIG_CHARGE_MANAGER #define CONFIG_CHARGER #define CONFIG_CHARGER_DISCHARGE_ON_AC -#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_INPUT_CURRENT 512 /* * Hardware based charge ramp is broken in the ISL9241 (b/169350714). @@ -115,7 +115,7 @@ #define CONFIG_CHARGE_RAMP_SW #define CONFIG_CHARGER_ISL9241 /* Setting ISL9241 Register Control1 switching frequency to 724kHz. */ -#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ +#define CONFIG_ISL9241_SWITCHING_FREQ ISL9241_CONTROL1_SWITCHING_FREQ_724KHZ #define CONFIG_USB_CHARGER #define CONFIG_BC12_DETECT_PI3USB9201 @@ -124,8 +124,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Common battery defines */ #define CONFIG_BATTERY_SMART @@ -140,7 +140,7 @@ /* EDP back-light control defines */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EDP_BL_EN /* USB Type C and USB PD defines */ /* Enable the new USB-C PD stack */ @@ -169,11 +169,11 @@ #define CONFIG_USB_PD_TCPC_LOW_POWER #define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_USB_PD_TCPM_RT1715 -#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ -#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ +#define CONFIG_USB_PD_TCPM_TUSB422 /* USBC port C0 */ +#define CONFIG_USB_PD_TCPM_PS8815 /* USBC port USB3 DB */ #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID #define CONFIG_USB_PD_TCPM_MUX -#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ +#define CONFIG_HOSTCMD_PD_CONTROL /* Needed for TCPC FW update */ #define CONFIG_CMD_USB_PD_PE /* @@ -190,7 +190,7 @@ * with non-PD chargers. Override the default low-power mode exit delay. */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50*MSEC) +#define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (50 * MSEC) /* Enable USB3.2 DRD */ #define CONFIG_USB_PD_USB32_DRD -- cgit v1.2.1 From f9669d961b4992c7dfd4875330f4a9617a8689cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:22 -0600 Subject: board/hoho/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4465665cdebbd339338d6a46c60e932bce91354c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728323 Reviewed-by: Jeremy Bettis --- board/hoho/usb_pd_config.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h index 2f01c275a8..e783ff874c 100644 --- a/board/hoho/usb_pd_config.h +++ b/board/hoho/usb_pd_config.h @@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* output low on SPI TX (PB4) to disable the FET */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*4))) - | (1 << (2*4)); + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4)); /* put the low level reference in Hi-Z */ gpio_set_level(GPIO_PD_CC1_TX_EN, 0); } @@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity) * use the right comparator : CC1 -> PA1 (COMP1 INP) * use VrefInt / 2 as INM (about 600mV) */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; } /* Initialize pins used for TX and put them in Hi-Z */ @@ -111,7 +110,9 @@ static inline void pd_tx_init(void) gpio_config_module(MODULE_USB_PD, 1); } -static inline void pd_set_host_mode(int port, int enable) {} +static inline void pd_set_host_mode(int port, int enable) +{ +} static inline void pd_config_init(int port, uint8_t power_role) { -- cgit v1.2.1 From be7b78fec57dea9a34c15f6dcbf83cf748d6fb30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:53 -0600 Subject: board/shuboz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I769840defd1ae455f99042d868cb663e4ac42600 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728952 Reviewed-by: Jeremy Bettis --- board/shuboz/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/shuboz/led.c b/board/shuboz/led.c index af91f32ec6..b007009cba 100644 --- a/board/shuboz/led.c +++ b/board/shuboz/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {LED_OFF, 2 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { LED_OFF, 2 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); -- cgit v1.2.1 From 0fd21cedcd830e9527be8b86718b41204f4f8815 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:59 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifd5974b5750798aec413debc47c22cc74160a639 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730728 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h index fcc8d6a85a..dd98c5131f 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_drp.h @@ -55,12 +55,12 @@ struct tcpci_drp_emul_data { * * @return Pointer to USB-C DRP extension */ -struct tcpci_partner_extension *tcpci_drp_emul_init( - struct tcpci_drp_emul_data *data, - struct tcpci_partner_data *common_data, - enum pd_power_role power_role, - struct tcpci_partner_extension *src_ext, - struct tcpci_partner_extension *snk_ext); +struct tcpci_partner_extension * +tcpci_drp_emul_init(struct tcpci_drp_emul_data *data, + struct tcpci_partner_data *common_data, + enum pd_power_role power_role, + struct tcpci_partner_extension *src_ext, + struct tcpci_partner_extension *snk_ext); /** * @brief Set correct flags for first capabilities PDO to indicate that this -- cgit v1.2.1 From 29cde0798a94e294f779053a670221a966550bc1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:58 -0600 Subject: zephyr/projects/trogdor/lazor/src/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I052b7aeb9e3491b7de2583efec3532b9a6ca3b0a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730810 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/usb_pd_policy.c | 43 +++++++++++------------ 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c index b94a65005a..a0549976cb 100644 --- a/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c +++ b/zephyr/projects/trogdor/lazor/src/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -24,10 +24,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -108,11 +108,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -175,8 +175,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * TODO(waihong): Better to move switching DP mux to * the usb_mux abstraction. */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), port == 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_sel), + port == 1); gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_mux_oe_l), 0); /* Connect the SBU lines in PPC chip. */ @@ -190,8 +190,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -203,13 +202,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -234,8 +231,8 @@ __override int svdm_dp_attention(int port, uint32_t *payload) gpio_pin_set_dt(hpd, 1); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; @@ -256,9 +253,9 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det), 0); + USB_PD_MUX_HPD_IRQ_DEASSERTED); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_dp_hot_plug_det), + 0); } } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ -- cgit v1.2.1 From 66d15cbf0eb798f1e4aaab91544b314516f33133 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:31 -0600 Subject: board/kakadu/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie6bdf5b9cadcd2c01bd8e8d86d8b1ce28b35acdc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728520 Reviewed-by: Jeremy Bettis --- board/kakadu/board.c | 123 ++++++++++++++++++++++----------------------------- 1 file changed, 54 insertions(+), 69 deletions(-) diff --git a/board/kakadu/board.c b/board/kakadu/board.c index 89905aa4a3..9a65319efe 100644 --- a/board/kakadu/board.c +++ b/board/kakadu/board.c @@ -43,8 +43,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -61,45 +61,40 @@ static void gauge_interrupt(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, - [ADC_BATT_ID] = {"BATT_ID", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_POGO_ADC_INT_L] = {"POGO_ADC_INT_L", 3300, 4096, 0, STM32_AIN(6)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, + [ADC_BATT_ID] = { "BATT_ID", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_POGO_ADC_INT_L] = { "POGO_ADC_INT_L", 3300, 4096, 0, + STM32_AIN(6) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ @@ -119,8 +114,7 @@ struct mt6370_thermal_bound thermal_bound = { .err = 4, }; -static void board_hpd_update(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -244,9 +238,8 @@ int extpower_is_present(void) if (board_vbus_source_enabled(CHARGE_PORT_USB_C)) usb_c_extpower_present = 0; else - usb_c_extpower_present = tcpm_check_vbus_level( - CHARGE_PORT_USB_C, - VBUS_PRESENT); + usb_c_extpower_present = + tcpm_check_vbus_level(CHARGE_PORT_USB_C, VBUS_PRESENT); return usb_c_extpower_present; } @@ -334,17 +327,13 @@ enum lid_accelgyro_type { static enum lid_accelgyro_type lid_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t lid_standard_ref_icm42607 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_lid_accel = { .name = "Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -370,20 +359,20 @@ struct motion_sensor_t icm42607_lid_accel = { }; struct motion_sensor_t icm42607_lid_gyro = { - .name = "Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_LID, - .drv = &icm42607_drv, - .mutex = &g_lid_mutex, - .drv_data = &g_icm42607_data, - .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &lid_standard_ref_icm42607, - .min_frequency = ICM42607_GYRO_MIN_FREQ, - .max_frequency = ICM42607_GYRO_MAX_FREQ, + .name = "Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM42607, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_LID, + .drv = &icm42607_drv, + .mutex = &g_lid_mutex, + .drv_data = &g_icm42607_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &lid_standard_ref_icm42607, + .min_frequency = ICM42607_GYRO_MIN_FREQ, + .max_frequency = ICM42607_GYRO_MAX_FREQ, }; struct motion_sensor_t motion_sensors[] = { @@ -460,18 +449,18 @@ static void board_detect_motionsensor(void) if (lid_accelgyro_config != LID_GYRO_NONE) return; /* Check base accelgyro chip */ - ret = icm_read8(&icm42607_lid_accel, - ICM42607_REG_WHO_AM_I, &val); + ret = icm_read8(&icm42607_lid_accel, ICM42607_REG_WHO_AM_I, &val); if (ret) ccprints("Get ICM fail."); if (val == ICM42607_CHIP_ICM42607P) { motion_sensors[LID_ACCEL] = icm42607_lid_accel; motion_sensors[LID_GYRO] = icm42607_lid_gyro; } - lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) - ? LID_GYRO_ICM426XX : LID_GYRO_BMI160; - ccprints("LID Accelgyro: %s", (val == ICM42607_CHIP_ICM42607P) - ? "ICM42607" : "BMI160"); + lid_accelgyro_config = (val == ICM42607_CHIP_ICM42607P) ? + LID_GYRO_ICM426XX : + LID_GYRO_BMI160; + ccprints("LID Accelgyro: %s", + (val == ICM42607_CHIP_ICM42607P) ? "ICM42607" : "BMI160"); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, HOOK_PRIO_DEFAULT); @@ -525,9 +514,8 @@ __override int board_charge_port_is_connected(int port) return gpio_get_level(GPIO_POGO_VBUS_PRESENT); } -__override -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r) +__override void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r) { r->meas.voltage_now = 3300; r->meas.voltage_max = 3300; @@ -540,13 +528,10 @@ void board_fill_source_power_info(int port, static void mt6370_reg_fix(void) { i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT946X_REG_CHGCTRL1, + chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL1, BIT(3) | BIT(5), MASK_CLR); i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT946X_REG_CHGCTRL2, - BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), - MASK_CLR); + chg_chips[CHARGER_SOLO].i2c_addr_flags, RT946X_REG_CHGCTRL2, + BIT(5) | BIT(RT946X_SHIFT_BATDET_DIS_DLY), MASK_CLR); } DECLARE_HOOK(HOOK_INIT, mt6370_reg_fix, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 1d66ab8a46b221091b3aa08cbe26dad00b31a187 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:49 -0600 Subject: include/driver/temp_sensor/sb_tsi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If9f64b38886c24399fd2cfdb64b4dbefe1cad01e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730256 Reviewed-by: Jeremy Bettis --- include/driver/temp_sensor/sb_tsi.h | 40 ++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/include/driver/temp_sensor/sb_tsi.h b/include/driver/temp_sensor/sb_tsi.h index b7113dbc70..ba045affa9 100644 --- a/include/driver/temp_sensor/sb_tsi.h +++ b/include/driver/temp_sensor/sb_tsi.h @@ -11,27 +11,27 @@ #ifndef __CROS_EC_SB_TSI_H #define __CROS_EC_SB_TSI_H -#define SB_TSI_I2C_ADDR_FLAGS 0x4C +#define SB_TSI_I2C_ADDR_FLAGS 0x4C /* G781 register */ -#define SB_TSI_TEMP_H 0x01 -#define SB_TSI_STATUS 0x02 -#define SB_TSI_CONFIG_1 0x03 -#define SB_TSI_UPDATE_RATE 0x04 -#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 -#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 -#define SB_TSI_CONFIG_2 0x09 -#define SB_TSI_TEMP_L 0x10 -#define SB_TSI_TEMP_OFFSET_H 0x11 -#define SB_TSI_TEMP_OFFSET_L 0x12 -#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 -#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 -#define SB_TSI_TIMEOUT_CONFIG 0x22 -#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F -#define SB_TSI_ALERT_THRESHOLD 0x32 -#define SB_TSI_ALERT_CONFIG 0xBF -#define SB_TSI_MANUFACTURE_ID 0xFE -#define SB_TSI_REVISION 0xFF +#define SB_TSI_TEMP_H 0x01 +#define SB_TSI_STATUS 0x02 +#define SB_TSI_CONFIG_1 0x03 +#define SB_TSI_UPDATE_RATE 0x04 +#define SB_TSI_HIGH_TEMP_THRESHOLD_H 0x07 +#define SB_TSI_LOW_TEMP_THRESHOLD_H 0x08 +#define SB_TSI_CONFIG_2 0x09 +#define SB_TSI_TEMP_L 0x10 +#define SB_TSI_TEMP_OFFSET_H 0x11 +#define SB_TSI_TEMP_OFFSET_L 0x12 +#define SB_TSI_HIGH_TEMP_THRESHOLD_L 0x13 +#define SB_TSI_LOW_TEMP_THRESHOLD_L 0x14 +#define SB_TSI_TIMEOUT_CONFIG 0x22 +#define SB_TSI_PSTATE_LIMIT_CONFIG 0x2F +#define SB_TSI_ALERT_THRESHOLD 0x32 +#define SB_TSI_ALERT_CONFIG 0xBF +#define SB_TSI_MANUFACTURE_ID 0xFE +#define SB_TSI_REVISION 0xFF /** * Get the value of a sensor in K. @@ -43,4 +43,4 @@ */ int sb_tsi_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_SB_TSI_H */ +#endif /* __CROS_EC_SB_TSI_H */ -- cgit v1.2.1 From 294dfa9ca48d4044c0c137a129a7584c70223d39 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:28 -0600 Subject: chip/stm32/config-stm32f07x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e34b4f14f42539a7e15a52c0ce83f011d46127b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729471 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f07x.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h index 2aa8f6d37d..05896cb9f9 100644 --- a/chip/stm32/config-stm32f07x.h +++ b/chip/stm32/config-stm32f07x.h @@ -5,15 +5,15 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES (128 * 1024) -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00004000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 @@ -23,10 +23,10 @@ #define CONFIG_CONSOLE_HISTORY 3 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 1024 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 1024 #define CONFIG_USB_RAM_ACCESS_TYPE uint16_t #define CONFIG_USB_RAM_ACCESS_SIZE 2 /* DFU Address */ -#define STM32_DFU_BASE 0x1fffC800 +#define STM32_DFU_BASE 0x1fffC800 -- cgit v1.2.1 From 8986745e3dd19e23774ee6636611a9a788c84abf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:24 -0600 Subject: baseboard/mtscp-rv32i/vdec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idb73d77ef2fc69ab9192e04483645371837c50bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727929 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/vdec.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/baseboard/mtscp-rv32i/vdec.c b/baseboard/mtscp-rv32i/vdec.c index c3f5f5a9cf..68681f63e8 100644 --- a/baseboard/mtscp-rv32i/vdec.c +++ b/baseboard/mtscp-rv32i/vdec.c @@ -21,11 +21,11 @@ static void event_vdec_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_VDEC_SERVICE); } static struct consumer const event_vdec_consumer; -static struct queue const event_vdec_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_consumer); +static struct queue const event_vdec_queue = + QUEUE_DIRECT(8, struct vdec_msg, null_producer, event_vdec_consumer); static struct consumer const event_vdec_consumer = { .queue = &event_vdec_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_vdec_written, }), }; @@ -36,19 +36,23 @@ static void event_vdec_core_written(struct consumer const *consumer, task_wake(TASK_ID_VDEC_CORE_SERVICE); } static struct consumer const event_vdec_core_consumer; -static struct queue const event_vdec_core_queue = QUEUE_DIRECT(8, - struct vdec_msg, null_producer, event_vdec_core_consumer); +static struct queue const event_vdec_core_queue = QUEUE_DIRECT( + 8, struct vdec_msg, null_producer, event_vdec_core_consumer); static struct consumer const event_vdec_core_consumer = { .queue = &event_vdec_core_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_vdec_core_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void vdec_msg_handler(void *data) {} -void vdec_core_msg_handler(void *data) {} +void vdec_msg_handler(void *data) +{ +} +void vdec_core_msg_handler(void *data) +{ +} #endif static void vdec_h264_ipi_handler(int id, void *data, uint32_t len) -- cgit v1.2.1 From 2280b382145753c5daf84d07dab0259220a9a39b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:44 -0600 Subject: chip/stm32/spi_controller-stm32h7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50c48fbb4226f7d78ec743990d74496049014793 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729411 Reviewed-by: Jeremy Bettis --- chip/stm32/spi_controller-stm32h7.c | 56 +++++++++++++------------------------ 1 file changed, 20 insertions(+), 36 deletions(-) diff --git a/chip/stm32/spi_controller-stm32h7.c b/chip/stm32/spi_controller-stm32h7.c index 7792204a85..a1e7804217 100644 --- a/chip/stm32/spi_controller-stm32h7.c +++ b/chip/stm32/spi_controller-stm32h7.c @@ -50,44 +50,28 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; static const struct dma_option dma_tx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, #endif - { - STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI2_TX, (void *)&STM32_SPI2_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI4_TX, (void *)&STM32_SPI4_REGS->txdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, }; static const struct dma_option dma_rx_option[] = { #ifdef CONFIG_STM32_SPI1_CONTROLLER - { - STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, #endif - { - STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, - { - STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT - }, + { STM32_DMAC_SPI2_RX, (void *)&STM32_SPI2_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, + { STM32_DMAC_SPI4_RX, (void *)&STM32_SPI4_REGS->rxdr, + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }, }; static uint8_t spi_enabled[ARRAY_SIZE(SPI_REGS)]; @@ -252,8 +236,8 @@ static int spi_dma_wait(int port) } int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv = EC_SUCCESS; int port = spi_device->port; @@ -314,8 +298,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rv; int port = spi_device->port; -- cgit v1.2.1 From 8819b5dc653c514dceb9b107128f02dfc29601d5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:28 -0600 Subject: board/cappy2/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I195b65b5db7c5838d0fe9399c4c3b1e318e6cbec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728136 Reviewed-by: Jeremy Bettis --- board/cappy2/led.c | 63 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/board/cappy2/led.c b/board/cappy2/led.c index fb6faae482..e556ab9ef5 100644 --- a/board/cappy2/led.c +++ b/board/cappy2/led.c @@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100; /* cappy2 : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -55,7 +58,7 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -73,7 +76,7 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } @@ -117,12 +120,12 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, - !brightness[EC_LED_COLOR_GREEN]); + !brightness[EC_LED_COLOR_GREEN]); gpio_set_level(GPIO_BAT_LED_RED_L, - !brightness[EC_LED_COLOR_RED]); + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, - !brightness[EC_LED_COLOR_BLUE]); + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 25f8008c8ccb97e017f8d87db471fe195b0815d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:15 -0600 Subject: include/tablet_mode.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I921f40901ebb127e436c2e4f96abfed8f69ccb54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730415 Reviewed-by: Jeremy Bettis --- include/tablet_mode.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/tablet_mode.h b/include/tablet_mode.h index 6ad565628c..ca8dfa2386 100644 --- a/include/tablet_mode.h +++ b/include/tablet_mode.h @@ -14,8 +14,8 @@ int tablet_get_mode(void); /* Bit mask of tablet mode trigger */ -#define TABLET_TRIGGER_LID BIT(0) -#define TABLET_TRIGGER_BASE BIT(1) +#define TABLET_TRIGGER_LID BIT(0) +#define TABLET_TRIGGER_BASE BIT(1) /** * Set tablet mode state @@ -56,4 +56,4 @@ void gmr_tablet_switch_disable(void); */ int board_sensor_at_360(void); -#endif /* __CROS_EC_TABLET_MODE_H */ +#endif /* __CROS_EC_TABLET_MODE_H */ -- cgit v1.2.1 From 282392a94fda321f549f2df296335e7d5548b27c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:37 -0600 Subject: chip/mt_scp/rv32i_common/cache.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I72d95c9e4eac271d62f7f6540faef2ea420c97a2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729346 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/cache.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/chip/mt_scp/rv32i_common/cache.h b/chip/mt_scp/rv32i_common/cache.h index 13e5ad1a42..2bb95e64de 100644 --- a/chip/mt_scp/rv32i_common/cache.h +++ b/chip/mt_scp/rv32i_common/cache.h @@ -14,23 +14,23 @@ /* rs1 0~31 register X0~X31 */ #define COP(rs1) (((rs1) << 15) | 0x400f) -#define COP_OP_BARRIER_ICACHE 0x0 -#define COP_OP_INVALIDATE_ICACHE 0x8 -#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9 - -#define COP_OP_BARRIER_DCACHE 0x10 -#define COP_OP_WRITEBACK_DCACHE 0x14 -#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15 -#define COP_OP_INVALIDATE_DCACHE 0x18 -#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19 +#define COP_OP_BARRIER_ICACHE 0x0 +#define COP_OP_INVALIDATE_ICACHE 0x8 +#define COP_OP_INVALIDATE_ICACHE_ADDR 0x9 + +#define COP_OP_BARRIER_DCACHE 0x10 +#define COP_OP_WRITEBACK_DCACHE 0x14 +#define COP_OP_WRITEBACK_DCACHE_ADDR 0x15 +#define COP_OP_INVALIDATE_DCACHE 0x18 +#define COP_OP_INVALIDATE_DCACHE_ADDR 0x19 /* FLUSH = WRITEBACK + INVALIDATE */ -#define COP_OP_FLUSH_DCACHE 0x1C -#define COP_OP_FLUSH_DCACHE_ADDR 0x1D +#define COP_OP_FLUSH_DCACHE 0x1C +#define COP_OP_FLUSH_DCACHE_ADDR 0x1D static inline void cache_op_all(uint32_t op) { register int t0 asm("t0") = op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); + asm volatile(".word " STRINGIFY(COP(5))::"r"(t0)); } static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op) @@ -44,7 +44,7 @@ static inline int cache_op_addr(uintptr_t addr, uint32_t length, uint32_t op) for (offset = 0; offset < length; offset += 4) { t0 = addr + offset + op; - asm volatile (".word "STRINGIFY(COP(5)) :: "r"(t0)); + asm volatile(".word " STRINGIFY(COP(5))::"r"(t0)); } return EC_SUCCESS; -- cgit v1.2.1 From 99a0efda69f6d4987859796d6302194bbf8216dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:06 -0600 Subject: driver/temp_sensor/f75303.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a4c60ff4afb3c89f2b4f36529736beea5bb1118 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730117 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/f75303.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/driver/temp_sensor/f75303.c b/driver/temp_sensor/f75303.c index 6b8895a252..0a944f2d8d 100644 --- a/driver/temp_sensor/f75303.c +++ b/driver/temp_sensor/f75303.c @@ -13,15 +13,14 @@ #include "console.h" static int temps[F75303_IDX_COUNT]; -static int8_t fake_temp[F75303_IDX_COUNT] = {-1, -1, -1}; +static int8_t fake_temp[F75303_IDX_COUNT] = { -1, -1, -1 }; /** * Read 8 bits register from temp sensor. */ static int raw_read8(const int offset, int *data) { - return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS, - offset, data); + return i2c_read8(I2C_PORT_THERMAL, F75303_I2C_ADDR_FLAGS, offset, data); } static int get_temp(const int offset, int *temp) @@ -88,6 +87,5 @@ static int f75303_set_fake_temp(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp, - " |off", - "Set fake temperature of sensor f75303."); +DECLARE_CONSOLE_COMMAND(f75303, f75303_set_fake_temp, " |off", + "Set fake temperature of sensor f75303."); -- cgit v1.2.1 From d8db20186baa24a6d8ad01920e5e80f6f718b098 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:36 -0600 Subject: chip/npcx/shi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b7c77be9e9b18e2da1c88e1ceb6fe89c6eed993 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729432 Reviewed-by: Jeremy Bettis --- chip/npcx/shi.c | 134 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 66 insertions(+), 68 deletions(-) diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 48b56d18ef..4e7553a8f9 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -24,8 +24,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #if !(DEBUG_SHI) #define DEBUG_CPUTS(...) @@ -33,39 +33,42 @@ #define DEBUG_CPRINTF(...) #else #define DEBUG_CPUTS(outstr) cputs(CC_SPI, outstr) -#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define DEBUG_CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define DEBUG_CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #endif /* SHI Bus definition */ #ifdef NPCX_SHI_V2 -#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */ -#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size */ +#define SHI_OBUF_FULL_SIZE 128 /* Full output buffer size */ +#define SHI_IBUF_FULL_SIZE 128 /* Full input buffer size */ /* Configure the IBUFLVL2 = the size of V3 protocol header */ #define SHI_IBUFLVL2_THRESHOLD (sizeof(struct ec_host_request)) #else -#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */ -#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size */ +#define SHI_OBUF_FULL_SIZE 64 /* Full output buffer size */ +#define SHI_IBUF_FULL_SIZE 64 /* Full input buffer size */ #endif -#define SHI_OBUF_HALF_SIZE (SHI_OBUF_FULL_SIZE/2) /* Half output buffer size */ -#define SHI_IBUF_HALF_SIZE (SHI_IBUF_FULL_SIZE/2) /* Half input buffer size */ +#define SHI_OBUF_HALF_SIZE \ + (SHI_OBUF_FULL_SIZE / 2) /* Half output buffer size */ +#define SHI_IBUF_HALF_SIZE \ + (SHI_IBUF_FULL_SIZE / 2) /* Half input buffer size */ /* Start address of SHI output buffer */ -#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020) +#define SHI_OBUF_START_ADDR (volatile uint8_t *)(NPCX_SHI_BASE_ADDR + 0x020) /* Middle address of SHI output buffer */ -#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) +#define SHI_OBUF_HALF_ADDR (SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) /* Top address of SHI output buffer */ -#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE) +#define SHI_OBUF_FULL_ADDR (SHI_OBUF_START_ADDR + SHI_IBUF_FULL_SIZE) /* * Valid offset of SHI output buffer to write. * When SIMUL bit is set, IBUFPTR can be used instead of OBUFPTR */ -#define SHI_OBUF_VALID_OFFSET ((shi_read_buf_pointer() + \ - SHI_OUT_PREAMBLE_LENGTH) % SHI_OBUF_FULL_SIZE) +#define SHI_OBUF_VALID_OFFSET \ + ((shi_read_buf_pointer() + SHI_OUT_PREAMBLE_LENGTH) % \ + SHI_OBUF_FULL_SIZE) /* Start address of SHI input buffer */ -#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0)) +#define SHI_IBUF_START_ADDR (&NPCX_IBUF(0)) /* Current address of SHI input buffer */ -#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer()) +#define SHI_IBUF_CUR_ADDR (SHI_IBUF_START_ADDR + shi_read_buf_pointer()) /* * Timeout to wait for SHI request packet @@ -106,12 +109,11 @@ */ #define SHI_PROTO3_OVERHEAD (EC_SPI_PAST_END_LENGTH + EC_SPI_FRAME_START_LENGTH) - #ifdef NPCX_SHI_BYPASS_OVER_256B /* The boundary which SHI will output invalid data on MISO. */ #define SHI_BYPASS_BOUNDARY 256 /* Increase FRAME_START_LENGTH in case shi outputs invalid FRAME_START byte */ -#undef EC_SPI_FRAME_START_LENGTH +#undef EC_SPI_FRAME_START_LENGTH #define EC_SPI_FRAME_START_LENGTH 2 #endif @@ -141,10 +143,9 @@ BUILD_ASSERT(SHI_MAX_RESPONSE_SIZE <= SHI_BYPASS_BOUNDARY); */ #define SHI_OUT_START_PAD (4 * (EC_SPI_FRAME_START_LENGTH / 4 + 1)) #define SHI_OUT_END_PAD (4 * (EC_SPI_PAST_END_LENGTH / 4 + 1)) -static uint8_t out_msg_padded[SHI_OUT_START_PAD + - SHI_MAX_RESPONSE_SIZE + +static uint8_t out_msg_padded[SHI_OUT_START_PAD + SHI_MAX_RESPONSE_SIZE + SHI_OUT_END_PAD] __aligned(4); -static uint8_t * const out_msg = +static uint8_t *const out_msg = out_msg_padded + SHI_OUT_START_PAD - EC_SPI_FRAME_START_LENGTH; static uint8_t in_msg[SHI_MAX_REQUEST_SIZE] __aligned(4); @@ -176,18 +177,18 @@ volatile enum shi_state state; /* SHI bus parameters */ struct shi_bus_parameters { - uint8_t *rx_msg; /* Entry pointer of msg rx buffer */ - uint8_t *tx_msg; /* Entry pointer of msg tx buffer */ + uint8_t *rx_msg; /* Entry pointer of msg rx buffer */ + uint8_t *tx_msg; /* Entry pointer of msg tx buffer */ volatile uint8_t *rx_buf; /* Entry pointer of receive buffer */ volatile uint8_t *tx_buf; /* Entry pointer of transmit buffer */ - uint16_t sz_received; /* Size of received data in bytes */ - uint16_t sz_sending; /* Size of sending data in bytes */ - uint16_t sz_request; /* request bytes need to receive */ - uint16_t sz_response; /* response bytes need to receive */ - timestamp_t rx_deadline; /* deadline of receiving */ - uint8_t pre_ibufstat; /* Previous IBUFSTAT value */ + uint16_t sz_received; /* Size of received data in bytes */ + uint16_t sz_sending; /* Size of sending data in bytes */ + uint16_t sz_request; /* request bytes need to receive */ + uint16_t sz_response; /* response bytes need to receive */ + timestamp_t rx_deadline; /* deadline of receiving */ + uint8_t pre_ibufstat; /* Previous IBUFSTAT value */ #ifdef NPCX_SHI_BYPASS_OVER_256B - uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */ + uint16_t bytes_in_256b; /* Sent bytes in 256 bytes boundary */ #endif } shi_params; @@ -222,7 +223,7 @@ static void shi_send_response_packet(struct host_packet *pkt) interrupt_disable(); if (state == SHI_STATE_PROCESSING) { /* Append our past-end byte, which we reserved space for. */ - ((uint8_t *) pkt->response)[pkt->response_size + 0] = + ((uint8_t *)pkt->response)[pkt->response_size + 0] = EC_SPI_PAST_END; /* Computing sending bytes of response */ @@ -266,8 +267,8 @@ void shi_handle_host_package(void) /* Need to receive data from buffer */ return; else { - uint16_t remain_bytes = shi_params.sz_request - - shi_params.sz_received; + uint16_t remain_bytes = + shi_params.sz_request - shi_params.sz_received; /* Read remaining bytes from input buffer directly */ if (!shi_read_inbuf_wait(remain_bytes)) @@ -287,7 +288,6 @@ void shi_handle_host_package(void) shi_packet.request_max = sizeof(in_msg); shi_packet.request_size = shi_params.sz_request; - #ifdef NPCX_SHI_BYPASS_OVER_256B /* Move FRAME_START to second byte */ out_msg[0] = EC_SPI_PROCESSING; @@ -324,7 +324,7 @@ static void shi_parse_header(void) if (in_msg[0] == EC_HOST_REQUEST_VERSION) { /* Protocol version 3 */ - struct ec_host_request *r = (struct ec_host_request *) in_msg; + struct ec_host_request *r = (struct ec_host_request *)in_msg; int pkt_size; /* * If request is over 32 bytes, @@ -371,8 +371,8 @@ static void shi_fill_out_status(uint8_t status) * be done within this gap. No racing happens. */ start = SHI_OBUF_VALID_OFFSET; - end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) - % SHI_OBUF_FULL_SIZE); + end = ((start + SHI_OBUF_FULL_SIZE - SHI_OUT_PREAMBLE_LENGTH) % + SHI_OBUF_FULL_SIZE); fill_ptr = (uint8_t *)SHI_OBUF_START_ADDR + start; fill_end = (uint8_t *)SHI_OBUF_START_ADDR + end; @@ -388,17 +388,17 @@ static void shi_fill_out_status(uint8_t status) } #ifdef NPCX_SHI_V2 - /* - * This routine configures at which level the Input Buffer Half Full 2(IBHF2)) - * event triggers an interrupt to core. - */ +/* + * This routine configures at which level the Input Buffer Half Full 2(IBHF2)) + * event triggers an interrupt to core. + */ static void shi_sec_ibf_int_enable(int enable) { if (enable) { /* Setup IBUFLVL2 threshold and enable it */ SET_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS); SET_FIELD(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2, - SHI_IBUFLVL2_THRESHOLD); + SHI_IBUFLVL2_THRESHOLD); CLEAR_BIT(NPCX_SHICFG5, NPCX_SHICFG5_IBUFLVL2DIS); /* Enable IBHF2 event */ SET_BIT(NPCX_EVENABLE2, NPCX_EVENABLE2_IBHF2EN); @@ -436,9 +436,9 @@ static int shi_is_cs_glitch(void) */ static void shi_write_half_outbuf(void) { - const uint8_t size = MIN(SHI_OBUF_HALF_SIZE, - shi_params.sz_response - - shi_params.sz_sending); + const uint8_t size = + MIN(SHI_OBUF_HALF_SIZE, + shi_params.sz_response - shi_params.sz_sending); uint8_t *obuf_ptr = (uint8_t *)shi_params.tx_buf; const uint8_t *obuf_end = obuf_ptr + size; uint8_t *msg_ptr = shi_params.tx_msg; @@ -468,8 +468,8 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes) * If response package is across 256 bytes boundary, * bypass needs to extend PROCESSING bytes after reaching the boundary. */ - if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes - > SHI_BYPASS_BOUNDARY) { + if (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE + szbytes > + SHI_BYPASS_BOUNDARY) { state = SHI_STATE_WAIT_ALIGNMENT; /* Set pointer of output buffer to the start address */ shi_params.tx_buf = SHI_OBUF_START_ADDR; @@ -485,7 +485,7 @@ static void shi_write_first_pkg_outbuf(uint16_t szbytes) /* Fill up to OBUF mid point, or OBUF end */ size = MIN(SHI_OBUF_HALF_SIZE - (offset % SHI_OBUF_HALF_SIZE), - szbytes - shi_params.sz_sending); + szbytes - shi_params.sz_sending); obuf_end = obuf_ptr + size; while (obuf_ptr != obuf_end) *(obuf_ptr++) = *(msg_ptr++); @@ -520,8 +520,8 @@ static void shi_read_half_inbuf(void) /* Restore data to msg buffer */ *(shi_params.rx_msg++) = *(shi_params.rx_buf++); shi_params.sz_received++; - } while (shi_params.sz_received % SHI_IBUF_HALF_SIZE - && shi_params.sz_received != shi_params.sz_request); + } while (shi_params.sz_received % SHI_IBUF_HALF_SIZE && + shi_params.sz_received != shi_params.sz_request); } /* @@ -601,7 +601,7 @@ static void shi_handle_cs_assert(void) if (state == SHI_STATE_DISABLED) return; - /* SHI V2 module filters cs glitch by hardware automatically */ + /* SHI V2 module filters cs glitch by hardware automatically */ #ifndef NPCX_SHI_V2 /* * IBUFSTAT resets on the 7th clock cycle after CS assertion, which @@ -725,7 +725,7 @@ static void shi_int_handler(void) DEBUG_CPRINTF("CNL-"); return; - /* Next transaction but we're not ready */ + /* Next transaction but we're not ready */ } else if (state == SHI_STATE_CNL_RESP_NOT_RDY) return; @@ -754,8 +754,8 @@ static void shi_int_handler(void) return shi_handle_host_package(); } else if (state == SHI_STATE_SENDING) { /* Write data from msg buffer to output buffer */ - if (shi_params.tx_buf == SHI_OBUF_START_ADDR + - SHI_OBUF_FULL_SIZE) { + if (shi_params.tx_buf == + SHI_OBUF_START_ADDR + SHI_OBUF_FULL_SIZE) { /* Write data from bottom address again */ shi_params.tx_buf = SHI_OBUF_START_ADDR; return shi_write_half_outbuf(); @@ -770,8 +770,8 @@ static void shi_int_handler(void) * If pointer of output buffer will reach 256 bytes * boundary soon, start to fill response data. */ - if (shi_params.bytes_in_256b == SHI_BYPASS_BOUNDARY - - SHI_OBUF_FULL_SIZE) { + if (shi_params.bytes_in_256b == + SHI_BYPASS_BOUNDARY - SHI_OBUF_FULL_SIZE) { state = SHI_STATE_SENDING; DEBUG_CPRINTF("SND-"); return shi_write_half_outbuf(); @@ -805,8 +805,9 @@ static void shi_int_handler(void) if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_IBF)) { #ifdef NPCX_SHI_BYPASS_OVER_256B /* Record the sent bytes within 256B boundary */ - shi_params.bytes_in_256b = (shi_params.bytes_in_256b + - SHI_OBUF_FULL_SIZE) % SHI_BYPASS_BOUNDARY; + shi_params.bytes_in_256b = + (shi_params.bytes_in_256b + SHI_OBUF_FULL_SIZE) % + SHI_BYPASS_BOUNDARY; #endif if (state == SHI_STATE_RECEIVING) { /* read data from input to msg buffer */ @@ -816,16 +817,16 @@ static void shi_int_handler(void) return shi_handle_host_package(); } else if (state == SHI_STATE_SENDING) /* Write data from msg buffer to output buffer */ - if (shi_params.tx_buf == SHI_OBUF_START_ADDR + - SHI_OBUF_HALF_SIZE) + if (shi_params.tx_buf == + SHI_OBUF_START_ADDR + SHI_OBUF_HALF_SIZE) return shi_write_half_outbuf(); else /* ignore it */ return; else if (state == SHI_STATE_PROCESSING #ifdef NPCX_SHI_BYPASS_OVER_256B - || state == SHI_STATE_WAIT_ALIGNMENT + || state == SHI_STATE_WAIT_ALIGNMENT #endif - ) + ) /* Wait for host handles request */ return; else @@ -850,7 +851,6 @@ void shi_cs_event(enum gpio_signal signal) #else shi_handle_cs_assert(); #endif - } /*****************************************************************************/ @@ -960,9 +960,7 @@ static void shi_reenable_on_sysjump(void) shi_enable(); } /* Call hook after chipset sets initial power state */ -DECLARE_HOOK(HOOK_INIT, - shi_reenable_on_sysjump, - HOOK_PRIO_POST_CHIPSET); +DECLARE_HOOK(HOOK_INIT, shi_reenable_on_sysjump, HOOK_PRIO_POST_CHIPSET); /* Disable SHI bus */ static void shi_disable(void) @@ -1079,4 +1077,4 @@ static enum ec_status shi_get_protocol_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, shi_get_protocol_info, -EC_VER_MASK(0)); + EC_VER_MASK(0)); -- cgit v1.2.1 From bc31583be4ba924ce89e4ed9a1b20d4e14d68e37 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:07 -0600 Subject: chip/it83xx/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I86977f5db8dd4c1f36f867cf17f0bfa44c22d233 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729212 Reviewed-by: Jeremy Bettis --- chip/it83xx/hwtimer.c | 47 +++++++++++++++++++++-------------------------- 1 file changed, 21 insertions(+), 26 deletions(-) diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c index 291751a1cb..8a49943559 100644 --- a/chip/it83xx/hwtimer.c +++ b/chip/it83xx/hwtimer.c @@ -55,18 +55,18 @@ #define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000) const struct ext_timer_ctrl_t et_ctrl_regs[] = { - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08, - IT83XX_IRQ_EXT_TIMER3}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10, - IT83XX_IRQ_EXT_TIMER4}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20, - IT83XX_IRQ_EXT_TIMER5}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40, - IT83XX_IRQ_EXT_TIMER6}, - {&IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80, - IT83XX_IRQ_EXT_TIMER7}, - {&IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01, - IT83XX_IRQ_EXT_TMR8}, + { &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x08, + IT83XX_IRQ_EXT_TIMER3 }, + { &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x10, + IT83XX_IRQ_EXT_TIMER4 }, + { &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x20, + IT83XX_IRQ_EXT_TIMER5 }, + { &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x40, + IT83XX_IRQ_EXT_TIMER6 }, + { &IT83XX_INTC_IELMR19, &IT83XX_INTC_IPOLR19, &IT83XX_INTC_ISR19, 0x80, + IT83XX_IRQ_EXT_TIMER7 }, + { &IT83XX_INTC_IELMR10, &IT83XX_INTC_IPOLR10, &IT83XX_INTC_ISR10, 0x01, + IT83XX_IRQ_EXT_TMR8 }, }; BUILD_ASSERT(ARRAY_SIZE(et_ctrl_regs) == EXT_TIMER_COUNT); @@ -128,7 +128,8 @@ void __hw_clock_event_set(uint32_t deadline) wait = deadline - __hw_clock_source_read(); IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = wait < EVENT_TIMER_COUNT_TO_US(0xffffffff) ? - EVENT_TIMER_US_TO_COUNT(wait) : 0xffffffff; + EVENT_TIMER_US_TO_COUNT(wait) : + 0xffffffff; /* enable and re-start timer */ IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x03; task_enable_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq); @@ -225,7 +226,7 @@ DECLARE_IRQ(CPU_INT_GROUP_3, __hw_clock_source_irq, 1); #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES /* Number of CPU cycles in 125 us */ -#define CYCLES_125NS (125*(PLL_CLOCK/SECOND) / 1000) +#define CYCLES_125NS (125 * (PLL_CLOCK / SECOND) / 1000) uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer) { uint32_t prev_mask = read_clear_int_mask(); @@ -245,8 +246,8 @@ uint32_t __ram_code ext_observation_reg_read(enum ext_timer_sel ext_timer) /* read for the second time */ "lwi %0,[%1]\n\t" : "=&r"(val) - : "r"((uintptr_t) &IT83XX_ETWD_ETXCNTOR(ext_timer)), - "i"(CYCLES_125NS)); + : "r"((uintptr_t)&IT83XX_ETWD_ETXCNTOR(ext_timer)), + "i"(CYCLES_125NS)); /* restore interrupts */ set_int_mask(prev_mask); @@ -275,10 +276,8 @@ void ext_timer_stop(enum ext_timer_sel ext_timer, int dis_irq) } static void ext_timer_ctrl(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int with_int, - int32_t count) + enum ext_timer_clock_source ext_timer_clock, + int start, int with_int, int32_t count) { uint8_t intc_mask; @@ -307,12 +306,8 @@ static void ext_timer_ctrl(enum ext_timer_sel ext_timer, } int ext_timer_ms(enum ext_timer_sel ext_timer, - enum ext_timer_clock_source ext_timer_clock, - int start, - int with_int, - int32_t ms, - int first_time_enable, - int raw) + enum ext_timer_clock_source ext_timer_clock, int start, + int with_int, int32_t ms, int first_time_enable, int raw) { uint32_t count; -- cgit v1.2.1 From f3d9ac9ada7ecc01becc28c846f52ccfd143ae3f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:30 -0600 Subject: include/driver/ppc/syv682x_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8701aeb65e931b2567353c4aec627f82bbf21ba2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730250 Reviewed-by: Jeremy Bettis --- include/driver/ppc/syv682x_public.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/driver/ppc/syv682x_public.h b/include/driver/ppc/syv682x_public.h index 92c841f811..63ad89be8b 100644 --- a/include/driver/ppc/syv682x_public.h +++ b/include/driver/ppc/syv682x_public.h @@ -9,10 +9,10 @@ #define __CROS_EC_DRIVER_PPC_SYV682X_PUBLIC_H /* I2C addresses */ -#define SYV682X_ADDR0_FLAGS 0x40 -#define SYV682X_ADDR1_FLAGS 0x41 -#define SYV682X_ADDR2_FLAGS 0x42 -#define SYV682X_ADDR3_FLAGS 0x43 +#define SYV682X_ADDR0_FLAGS 0x40 +#define SYV682X_ADDR1_FLAGS 0x41 +#define SYV682X_ADDR2_FLAGS 0x42 +#define SYV682X_ADDR3_FLAGS 0x43 extern const struct ppc_drv syv682x_drv; -- cgit v1.2.1 From 0bfd27e502eb8533a02b57c5409a48bf3fbf04af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:31 -0600 Subject: board/voema/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie270f348687efbe9e60038b140205a4a91219e40 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729060 Reviewed-by: Jeremy Bettis --- board/voema/sensors.c | 52 +++++++++++++++++++++++---------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/board/voema/sensors.c b/board/voema/sensors.c index b55890b074..b55afcc9c2 100644 --- a/board/voema/sensors.c +++ b/board/voema/sensors.c @@ -90,23 +90,17 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t kx022_lid_accel = { .name = "Lid Accel", @@ -256,20 +250,20 @@ struct motion_sensor_t icm_base_accel = { }; struct motion_sensor_t icm_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm426xx_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &base_icm_ref, - .min_frequency = ICM426XX_GYRO_MIN_FREQ, - .max_frequency = ICM426XX_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM426XX, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm426xx_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm426xx_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &base_icm_ref, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; /* ALS instances when LPC mapping is needed. Each entry directs to a sensor. */ -- cgit v1.2.1 From 2ed4ae389e38d1cd335cd7be546e54100ea47047 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:22 -0600 Subject: include/als.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa7210593ff0b20c480c7329ddf5d14669c16bd9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730203 Reviewed-by: Jeremy Bettis --- include/als.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/als.h b/include/als.h index 4ff3fcdb4f..dedc1a12f9 100644 --- a/include/als.h +++ b/include/als.h @@ -34,4 +34,4 @@ extern struct als_t als[]; */ int als_read(enum als_id id, int *lux); -#endif /* __CROS_EC_ALS_H */ +#endif /* __CROS_EC_ALS_H */ -- cgit v1.2.1 From 4b7e8b728dac87d3f174f38abfc8fe930214bfb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:11 -0600 Subject: board/agah/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib624221254b77f7ccc7aa45928c64202c7bb6ec3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727969 Reviewed-by: Jeremy Bettis --- board/agah/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/agah/board.c b/board/agah/board.c index 47f2628fbb..e4d48507ee 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -31,8 +31,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static int block_sequence; @@ -68,7 +68,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); static void board_init(void) { if ((system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) || - (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) { + (keyboard_scan_get_boot_keys() & BOOT_KEY_DOWN_ARROW)) { CPRINTS("PG_PP3300_S5_OD block is enabled"); block_sequence = 1; } -- cgit v1.2.1 From 464210e264e9d8b27aba2b4ea173f85dc80130b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:58 -0600 Subject: common/keyboard_scan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0ce1a97977659490e8d56fc0a2b5838e6bcb135 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729659 Reviewed-by: Jeremy Bettis --- common/keyboard_scan.c | 89 +++++++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 49 deletions(-) diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c index 0edeca5867..f445efc33f 100644 --- a/common/keyboard_scan.c +++ b/common/keyboard_scan.c @@ -33,21 +33,21 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_KEYSCAN, outstr) -#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args) -#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ##args) +#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args) #ifdef CONFIG_KEYBOARD_DEBUG #define CPUTS5(outstr) cputs(CC_KEYSCAN, outstr) -#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args) #else #define CPUTS5(outstr) #define CPRINTS5(format, args...) #endif -#define SCAN_TIME_COUNT 32 /* Number of last scan times to track */ +#define SCAN_TIME_COUNT 32 /* Number of last scan times to track */ /* If we're waiting for a scan to happen, we'll give it this long */ -#define SCAN_TASK_TIMEOUT_US (100 * MSEC) +#define SCAN_TASK_TIMEOUT_US (100 * MSEC) #ifndef CONFIG_KEYBOARD_POST_SCAN_CLOCKS /* @@ -85,9 +85,9 @@ __overridable struct keyboard_scan_config keyscan_config = { #ifdef CONFIG_KEYBOARD_BOOT_KEYS #ifndef CONFIG_KEYBOARD_MULTIPLE static const struct boot_key_entry boot_key_list[] = { - {KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC}, /* Esc */ - {KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN}, /* Down-arrow */ - {KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT}, /* Left-Shift */ + { KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */ + { KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */ + { KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */ }; #else struct boot_key_entry boot_key_list[] = { @@ -214,7 +214,7 @@ static int keyboard_read_adc_rows(void) /* Read each adc channel to build row byte */ for (int i = 0; i < KEYBOARD_ROWS; i++) { if (adc_read_channel(ADC_KSI_00 + i) > - keyscan_config.ksi_threshold_mv) + keyscan_config.ksi_threshold_mv) kb_row |= (1 << i); } @@ -246,7 +246,6 @@ static void keyboard_read_refresh_key(uint8_t *state) } #endif - /** * Simulate a keypress. * @@ -259,7 +258,7 @@ static void simulate_key(int row, int col, int pressed) int old_polls; if ((simulated_key[col] & BIT(row)) == ((pressed ? 1 : 0) << row)) - return; /* No change */ + return; /* No change */ simulated_key[col] ^= BIT(row); @@ -279,8 +278,8 @@ static void simulate_key(int row, int col, int pressed) * That means it needs to have run and for enough time. */ ensure_keyboard_scanned(old_polls); - usleep(pressed ? - keyscan_config.debounce_down_us : keyscan_config.debounce_up_us); + usleep(pressed ? keyscan_config.debounce_down_us : + keyscan_config.debounce_up_us); ensure_keyboard_scanned(kbd_polls); } @@ -378,7 +377,6 @@ static int read_matrix(uint8_t *state) /* Mask off keys that don't exist on the actual keyboard */ state[c] &= keyscan_config.actual_key_mask[c]; - } keyboard_raw_drive_column(KEYBOARD_COLUMN_NONE); @@ -594,7 +592,7 @@ static int check_keys_changed(uint8_t *state) if (tnow - scan_time[scan_edge_index[c][i]] < (state[c] ? keyscan_config.debounce_down_us : keyscan_config.debounce_up_us)) - continue; /* Not done debouncing */ + continue; /* Not done debouncing */ debouncing[c] &= ~BIT(i); if (!IS_ENABLED(CONFIG_KEYBOARD_STRICT_DEBOUNCE)) @@ -639,7 +637,6 @@ static int check_keys_changed(uint8_t *state) } if (any_change) { - #ifdef CONFIG_KEYBOARD_SUPPRESS_NOISE /* Suppress keyboard noise */ keyboard_suppress_noise(); @@ -652,9 +649,9 @@ static int check_keys_changed(uint8_t *state) /* Print delta times from now back to each previous scan */ CPRINTF("[%pT kb deltaT", PRINTF_TIMESTAMP_NOW); for (i = 0; i < SCAN_TIME_COUNT; i++) { - int tnew = scan_time[ - (SCAN_TIME_COUNT + scan_time_index - i) % - SCAN_TIME_COUNT]; + int tnew = scan_time[(SCAN_TIME_COUNT + + scan_time_index - i) % + SCAN_TIME_COUNT]; CPRINTF(" %d", tnow - tnew); } CPRINTF("]\n"); @@ -706,8 +703,9 @@ static uint32_t check_key_list(const uint8_t *state) * button hold, and ignore it if so. */ for (c = 0; c < keyboard_cols; c++) - if ((keyscan_config.actual_key_mask[c] & KEYBOARD_MASK_PWRBTN) - && !(curr_state[c] & KEYBOARD_MASK_PWRBTN)) + if ((keyscan_config.actual_key_mask[c] & + KEYBOARD_MASK_PWRBTN) && + !(curr_state[c] & KEYBOARD_MASK_PWRBTN)) break; if (c == keyboard_cols) @@ -754,7 +752,7 @@ static void read_adc_boot_keys(uint8_t *state) udelay(keyscan_config.output_settle_us); if (adc_read_channel(ADC_KSI_00 + r) > - keyscan_config.ksi_threshold_mv) + keyscan_config.ksi_threshold_mv) state[c] |= BIT(r); } @@ -802,7 +800,7 @@ static uint32_t check_boot_key(const uint8_t *state) static void keyboard_freq_change(void) { post_scan_clock_us = (CONFIG_KEYBOARD_POST_SCAN_CLOCKS * 1000) / - (clock_get_freq() / 1000); + (clock_get_freq() / 1000); } DECLARE_HOOK(HOOK_FREQ_CHANGE, keyboard_freq_change, HOOK_PRIO_DEFAULT); @@ -838,8 +836,8 @@ void keyboard_scan_init(void) } /* Configure refresh key matrix */ - keyboard_mask_refresh = KEYBOARD_ROW_TO_MASK( - board_keyboard_row_refresh()); + keyboard_mask_refresh = + KEYBOARD_ROW_TO_MASK(board_keyboard_row_refresh()); if (!IS_ENABLED(CONFIG_KEYBOARD_SCAN_ADC)) /* Configure GPIO */ @@ -920,7 +918,8 @@ void keyboard_scan_task(void *u) if (local_disable_scanning != new_disable_scanning) CPRINTS("KB disable_scanning_mask changed: " - "0x%08x", new_disable_scanning); + "0x%08x", + new_disable_scanning); if (!new_disable_scanning) { /* Enabled now */ @@ -955,7 +954,7 @@ void keyboard_scan_task(void *u) #else if (!local_disable_scanning && (keyboard_read_adc_rows() || force_poll || - !gpio_get_level(GPIO_RFR_KEY_L))) + !gpio_get_level(GPIO_RFR_KEY_L))) break; #endif else @@ -976,15 +975,16 @@ void keyboard_scan_task(void *u) /* Check for keys down */ if (check_keys_changed(debounced_state)) { - poll_deadline.val = start.val - + keyscan_config.poll_timeout_us; + poll_deadline.val = + start.val + + keyscan_config.poll_timeout_us; } else if (timestamp_expired(poll_deadline, &start)) { break; } /* Delay between scans */ wait_time = keyscan_config.scan_period_us - - (get_time().val - start.val); + (get_time().val - start.val); if (wait_time < keyscan_config.min_post_scan_delay_us) wait_time = @@ -1046,8 +1046,7 @@ mkbp_command_simulate_key(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY, - mkbp_command_simulate_key, +DECLARE_HOST_COMMAND(EC_CMD_MKBP_SIMULATE_KEY, mkbp_command_simulate_key, EC_VER_MASK(0)); #ifdef CONFIG_KEYBOARD_FACTORY_TEST @@ -1065,17 +1064,15 @@ int keyboard_factory_test_scan(void) /* Set all of KSO/KSI pins to internal pull-up and input */ for (i = 0; i < keyboard_factory_scan_pins_used; i++) { - if (keyboard_factory_scan_pins[i][0] < 0) continue; port = keyboard_factory_scan_pins[i][0]; id = keyboard_factory_scan_pins[i][1]; - gpio_set_alternate_function(port, 1 << id, - GPIO_ALT_FUNC_NONE); + gpio_set_alternate_function(port, 1 << id, GPIO_ALT_FUNC_NONE); gpio_set_flags_by_mask(port, 1 << id, - GPIO_INPUT | GPIO_PULL_UP); + GPIO_INPUT | GPIO_PULL_UP); } /* @@ -1083,7 +1080,6 @@ int keyboard_factory_test_scan(void) * going to low level, it indicate the two pins are shorted. */ for (i = 0; i < keyboard_factory_scan_pins_used; i++) { - if (keyboard_factory_scan_pins[i][0] < 0) continue; @@ -1093,19 +1089,18 @@ int keyboard_factory_test_scan(void) gpio_set_flags_by_mask(port, 1 << id, GPIO_OUT_LOW); for (j = 0; j < keyboard_factory_scan_pins_used; j++) { - if (keyboard_factory_scan_pins[j][0] < 0 || i == j) continue; if (keyboard_raw_is_input_low( - keyboard_factory_scan_pins[j][0], - keyboard_factory_scan_pins[j][1])) { + keyboard_factory_scan_pins[j][0], + keyboard_factory_scan_pins[j][1])) { shorted = i << 8 | j; goto done; } } gpio_set_flags_by_mask(port, 1 << id, - GPIO_INPUT | GPIO_PULL_UP); + GPIO_INPUT | GPIO_PULL_UP); } done: gpio_config_module(MODULE_KEYBOARD_SCAN, 1); @@ -1133,8 +1128,7 @@ static enum ec_status keyboard_factory_test(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST, - keyboard_factory_test, +DECLARE_HOST_COMMAND(EC_CMD_KEYBOARD_FACTORY_TEST, keyboard_factory_test, EC_VER_MASK(0)); #endif @@ -1175,14 +1169,12 @@ static int command_ksstate(int argc, char **argv) print_state(debounced_state, "debounced "); print_state(debouncing, "debouncing"); - ccprintf("Keyboard scan disable mask: 0x%08x\n", - disable_scanning_mask); + ccprintf("Keyboard scan disable mask: 0x%08x\n", disable_scanning_mask); ccprintf("Keyboard scan state printing %s\n", print_state_changes ? "on" : "off"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate, - "ksstate [on | off | force]", +DECLARE_CONSOLE_COMMAND(ksstate, command_ksstate, "ksstate [on | off | force]", "Show or toggle printing keyboard scan state"); static int command_keyboard_press(int argc, char **argv) @@ -1226,7 +1218,6 @@ static int command_keyboard_press(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press, - "[col row [0 | 1]]", +DECLARE_CONSOLE_COMMAND(kbpress, command_keyboard_press, "[col row [0 | 1]]", "Simulate keypress"); #endif -- cgit v1.2.1 From 2227df479d712ddd4fb0693b3b50f3d0ddbb2127 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:20 -0600 Subject: chip/stm32/clock-stm32l4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I981abbad9b726c069c6416e8cad58db05f5424af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729468 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32l4.c | 96 +++++++++++++++++++++------------------------- 1 file changed, 44 insertions(+), 52 deletions(-) diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 5a4de3a581..a4227cbc9f 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -21,7 +21,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) /* High-speed oscillator is 16 MHz */ #define STM32_HSI_CLOCK 16000000 @@ -45,13 +45,13 @@ #define SCALING 1000 enum clock_osc { - OSC_INIT = 0, /* Uninitialized */ - OSC_HSI, /* High-speed internal oscillator */ - OSC_MSI, /* Multi-speed internal oscillator */ -#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ - OSC_HSE, /* High-speed external oscillator */ + OSC_INIT = 0, /* Uninitialized */ + OSC_HSI, /* High-speed internal oscillator */ + OSC_MSI, /* Multi-speed internal oscillator */ +#ifdef STM32_HSE_CLOCK /* Allows us to catch absence of HSE at comiple time */ + OSC_HSE, /* High-speed external oscillator */ #endif - OSC_PLL, /* PLL */ + OSC_PLL, /* PLL */ }; static int freq = STM32_MSI_CLOCK; @@ -162,8 +162,8 @@ static void clock_switch_osc(enum clock_osc osc) * 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN * in RCC_PLLCFGR. */ -static int stm32_configure_pll(enum clock_osc osc, - uint8_t m, uint8_t n, uint8_t r) +static int stm32_configure_pll(enum clock_osc osc, uint8_t m, uint8_t n, + uint8_t r) { uint32_t val; bool pll_unchanged; @@ -323,9 +323,8 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) case OSC_MSI: /* Switch to MSI @ 1MHz */ - STM32_RCC_CR = - (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | - STM32_RCC_ICSCR_MSIRANGE_1MHZ; + STM32_RCC_CR = (STM32_RCC_CR & ~STM32_RCC_ICSCR_MSIRANGE_MASK) | + STM32_RCC_ICSCR_MSIRANGE_1MHZ; /* Ensure that MSI is ON */ clock_enable_osc(osc); @@ -353,7 +352,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) /* Disable other clock sources */ STM32_RCC_CR &= ~(STM32_RCC_CR_MSION | STM32_RCC_CR_HSION | - STM32_RCC_CR_PLLON); + STM32_RCC_CR_PLLON); freq = STM32_HSE_CLOCK; @@ -396,22 +395,22 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) */ val = STM32_FLASH_ACR; val &= ~STM32_FLASH_ACR_LATENCY_MASK; - if (freq <= 16000000U) { + if (freq <= 16000000U) { val = val; - } else if (freq <= 32000000U) { + } else if (freq <= 32000000U) { val |= 1; - } else if (freq <= 48000000U) { + } else if (freq <= 48000000U) { val |= 2; - } else if (freq <= 64000000U) { + } else if (freq <= 64000000U) { val |= 3; - } else if (freq <= 80000000U) { + } else if (freq <= 80000000U) { val |= 4; - } else { + } else { val |= 4; CPUTS("Incorrect Frequency setting in VOS1!\n"); } STM32_FLASH_ACR = val; - } else { + } else { val = STM32_FLASH_ACR; val &= ~STM32_FLASH_ACR_LATENCY_MASK; @@ -423,7 +422,7 @@ static void clock_set_osc(enum clock_osc osc, enum clock_osc pll_osc) val |= 2; } else if (freq <= 26000000U) { val |= 3; - } else { + } else { val |= 4; CPUTS("Incorrect Frequency setting in VOS2!\n"); } @@ -472,8 +471,8 @@ void clock_enable_module(enum module_id module, int enable) /* ADC select bit 28/29 */ STM32_RCC_CCIPR &= ~STM32_RCC_CCIPR_ADCSEL_MSK; - STM32_RCC_CCIPR |= (STM32_RCC_CCIPR_ADCSEL_0 | - STM32_RCC_CCIPR_ADCSEL_1); + STM32_RCC_CCIPR |= + (STM32_RCC_CCIPR_ADCSEL_0 | STM32_RCC_CCIPR_ADCSEL_1); /* ADC clock enable */ if (enable) STM32_RCC_AHB2ENR |= STM32_RCC_HB2_ADC1; @@ -484,12 +483,11 @@ void clock_enable_module(enum module_id module, int enable) STM32_RCC_APB1ENR1 |= STM32_RCC_PB1_SPI2; else STM32_RCC_APB1ENR1 &= ~STM32_RCC_PB1_SPI2; - } else if (module == MODULE_SPI || - module == MODULE_SPI_CONTROLLER) { + } else if (module == MODULE_SPI || module == MODULE_SPI_CONTROLLER) { if (enable) STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_SPI1EN; - else if ((new_mask & (BIT(MODULE_SPI) | - BIT(MODULE_SPI_CONTROLLER))) == 0) + else if ((new_mask & + (BIT(MODULE_SPI) | BIT(MODULE_SPI_CONTROLLER))) == 0) STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_SPI1EN; } else if (module == MODULE_USB) { #ifdef CHIP_FAMILY_STM32L5 @@ -588,7 +586,6 @@ void rtc_set(uint32_t sec) } #endif - void clock_init(void) { #ifdef STM32_HSE_CLOCK @@ -666,7 +663,6 @@ uint32_t us_to_rtcss(uint32_t us) (us * (RTC_FREQ / SCALING) / (SECOND / SCALING))); } - /* Convert decimal to BCD */ static uint8_t u8_to_bcd(uint8_t val) { @@ -684,12 +680,14 @@ static uint32_t rtc_tr_to_sec(uint32_t rtc_tr) /* convert the hours field */ sec = (((rtc_tr & RTC_TR_HT) >> RTC_TR_HT_POS) * 10 + - ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * 3600; + ((rtc_tr & RTC_TR_HU) >> RTC_TR_HU_POS)) * + 3600; /* convert the minutes field */ sec += (((rtc_tr & RTC_TR_MNT) >> RTC_TR_MNT_POS) * 10 + - ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * 60; + ((rtc_tr & RTC_TR_MNU) >> RTC_TR_MNU_POS)) * + 60; /* convert the seconds field */ - sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + + sec += ((rtc_tr & RTC_TR_ST) >> RTC_TR_ST_POS) * 10 + (rtc_tr & RTC_TR_SU); return sec; } @@ -766,10 +764,9 @@ static uint32_t rtc_dr_to_sec(uint32_t rtc_dr) struct calendar_date time; uint32_t sec; - time.year = (((rtc_dr & 0xf00000) >> 20) * 10 + - ((rtc_dr & 0xf0000) >> 16)); - time.month = (((rtc_dr & 0x1000) >> 12) * 10 + - ((rtc_dr & 0xf00) >> 8)); + time.year = + (((rtc_dr & 0xf00000) >> 20) * 10 + ((rtc_dr & 0xf0000) >> 16)); + time.month = (((rtc_dr & 0x1000) >> 12) * 10 + ((rtc_dr & 0xf00) >> 8)); time.day = ((rtc_dr & 0x30) >> 4) * 10 + (rtc_dr & 0xf); sec = date_to_sec(time); @@ -905,8 +902,8 @@ void set_rtc_alarm(uint32_t delay_s, uint32_t delay_us, * If the caller doesn't specify subsecond delay (e.g. host command), * just align the alarm time to second. */ - STM32_RTC_ALRMASSR = delay_us ? - (us_to_rtcss(alarm_us) | 0x0f000000) : 0; + STM32_RTC_ALRMASSR = delay_us ? (us_to_rtcss(alarm_us) | 0x0f000000) : + 0; #ifdef CONFIG_HOSTCMD_RTC /* @@ -968,8 +965,7 @@ static void set_rtc_host_event(void) DECLARE_DEFERRED(set_rtc_host_event); #endif -test_mockable_static -void __rtc_alarm_irq(void) +test_mockable_static void __rtc_alarm_irq(void) { struct rtc_time_reg rtc; @@ -985,7 +981,6 @@ void __rtc_alarm_irq(void) } DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); - void print_system_rtc(enum console_channel ch) { uint32_t sec; @@ -997,7 +992,6 @@ void print_system_rtc(enum console_channel ch) cprintf(ch, "RTC: 0x%08x (%d.00 s)\n", sec, sec); } - #ifdef CONFIG_LOW_POWER_IDLE /* Low power idle statistics */ static int idle_sleep_cnt; @@ -1015,7 +1009,6 @@ static int dsleep_recovery_margin_us = 1000000; */ #define SET_RTC_MATCH_DELAY 120 /* us */ - void low_power_init(void) { /* Enter stop1 mode */ @@ -1055,11 +1048,11 @@ void __idle(void) /* Set deep sleep bit */ CPU_SCB_SYSCTRL |= 0x4; - set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY - - PLL_LOCK_LATENCY, + set_rtc_alarm(0, + next_delay - STOP_MODE_LATENCY - + PLL_LOCK_LATENCY, &rtc0, 0); - /* ensure outstanding memory transactions complete */ asm volatile("dsb"); @@ -1071,8 +1064,8 @@ void __idle(void) STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN; clock_wait_bus_cycles(BUS_APB, 2); - stm32_configure_pll(OSC_HSI, STM32_PLLM, - STM32_PLLN, STM32_PLLR); + stm32_configure_pll(OSC_HSI, STM32_PLLM, STM32_PLLN, + STM32_PLLR); /* Switch to PLL */ clock_switch_osc(OSC_PLL); @@ -1117,14 +1110,13 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llus\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llus\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_LOW_POWER_IDLE */ -- cgit v1.2.1 From de53654287a0657d90620a04ef3378175afcb99c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:04 -0600 Subject: board/driblee/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac8727a0ff1284ca36e807d4913a96ead0eee352 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728259 Reviewed-by: Jeremy Bettis --- board/driblee/board.h | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/board/driblee/board.h b/board/driblee/board.h index e1bd9d1dca..0280b0fc79 100644 --- a/board/driblee/board.h +++ b/board/driblee/board.h @@ -49,7 +49,7 @@ #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* PWM */ -#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ +#define NPCX7_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ /* Temp sensor */ #define CONFIG_TEMP_SENSOR @@ -86,16 +86,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -111,17 +111,13 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 60a63d26c163daea5d776245755ed9245d321bed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:16 -0600 Subject: chip/mt_scp/mt8192/clock_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If70a491949779595a94de083300ba054d76df6f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729352 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8192/clock_regs.h | 83 ++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 43 deletions(-) diff --git a/chip/mt_scp/mt8192/clock_regs.h b/chip/mt_scp/mt8192/clock_regs.h index 5928ca0473..02210d5e0f 100644 --- a/chip/mt_scp/mt8192/clock_regs.h +++ b/chip/mt_scp/mt8192/clock_regs.h @@ -9,48 +9,45 @@ #define __CROS_EC_CLOCK_REGS_H /* clock source select */ -#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) -#define CLK_SW_SEL_26M 0 -#define CLK_SW_SEL_32K 1 -#define CLK_SW_SEL_ULPOSC2 2 -#define CLK_SW_SEL_ULPOSC1 3 -#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) -#define CLK_HIGH_EN BIT(1) /* ULPOSC */ -#define CLK_HIGH_CG BIT(2) +#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) +#define CLK_SW_SEL_26M 0 +#define CLK_SW_SEL_32K 1 +#define CLK_SW_SEL_ULPOSC2 2 +#define CLK_SW_SEL_ULPOSC1 3 +#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) +#define CLK_HIGH_EN BIT(1) /* ULPOSC */ +#define CLK_HIGH_CG BIT(2) /* clock general control */ -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) -#define VREQ_PMIC_WRAP_SEL (0x2) +#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) +#define VREQ_PMIC_WRAP_SEL (0x2) /* TOPCK clk */ -#define TOPCK_BASE AP_REG_BASE -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 +#define TOPCK_BASE AP_REG_BASE +#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) +#define MISC_METER_DIVISOR_MASK 0xff000000 +#define MISC_METER_DIV_1 0 /* OSC meter */ -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) -#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16) -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN BIT(4) -#define CFG_FREQ_METER_ENABLE BIT(12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) +#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) +#define DBG_MODE_MASK 3 +#define DBG_MODE_SET_CLOCK 0 +#define DBG_BIST_SOURCE_MASK (0x3f << 16) +#define DBG_BIST_SOURCE_ULPOSC1 (0x25 << 16) +#define DBG_BIST_SOURCE_ULPOSC2 (0x24 << 16) +#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) +#define CFG_FREQ_METER_RUN BIT(4) +#define CFG_FREQ_METER_ENABLE BIT(12) +#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) +#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF) /* * ULPOSC * osc: 0 for ULPOSC1, 1 for ULPOSC2. */ -#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) -#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) -#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8) -#define AP_ULPOSC_CON0(osc) \ - REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON1(osc) \ - REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON2(osc) \ - REG32(AP_ULPOSC_CON2_BASE + (osc) * 0x10) +#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) +#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) +#define AP_ULPOSC_CON2_BASE (AP_REG_BASE + 0xC2B8) +#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10) +#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10) +#define AP_ULPOSC_CON2(osc) REG32(AP_ULPOSC_CON2_BASE + (osc)*0x10) /* * AP_ULPOSC_CON0 * bit0-6: calibration @@ -60,11 +57,11 @@ * bit24: cp_en * bit25-31: reserved */ -#define OSC_CALI_MASK 0x7f -#define OSC_IBAND_SHIFT 7 -#define OSC_FBAND_SHIFT 14 -#define OSC_DIV_SHIFT 18 -#define OSC_CP_EN BIT(24) +#define OSC_CALI_MASK 0x7f +#define OSC_IBAND_SHIFT 7 +#define OSC_FBAND_SHIFT 14 +#define OSC_DIV_SHIFT 18 +#define OSC_CP_EN BIT(24) /* AP_ULPOSC_CON1 * bit0-7: 32K calibration * bit 8-15: rsv1 @@ -73,10 +70,10 @@ * bit26: div2_en * bit27-31: reserved */ -#define OSC_RSV1_SHIFT 8 -#define OSC_RSV2_SHIFT 16 -#define OSC_MOD_SHIFT 24 -#define OSC_DIV2_EN BIT(26) +#define OSC_RSV1_SHIFT 8 +#define OSC_RSV2_SHIFT 16 +#define OSC_MOD_SHIFT 24 +#define OSC_DIV2_EN BIT(26) /* AP_ULPOSC_CON2 * bit0-7: bias * bit8-31: reserved -- cgit v1.2.1 From 5f16105406ba409bf0c27ec35221d4bc679b6b7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:59 -0600 Subject: zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb96970bc0645cc6735650ff1e5d3b59d3e81a08 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730671 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c index 49c80b2211..9e2df93c74 100644 --- a/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c +++ b/zephyr/drivers/cros_kb_raw/cros_kb_raw_ite.c @@ -120,7 +120,7 @@ static int cros_kb_raw_ite_drive_column(const struct device *dev, int col) * we are using). */ inst->KBS_KSOH1 = ((inst->KBS_KSOH1) & ~KSOH_PIN_MASK) | - ((mask >> 8) & KSOH_PIN_MASK); + ((mask >> 8) & KSOH_PIN_MASK); /* restore interrupts */ irq_unlock(key); @@ -208,7 +208,7 @@ static int cros_kb_raw_ite_init(const struct device *dev) */ if (IS_ENABLED(CONFIG_LOG)) { if (config->wuc_map_list[i].wucs != - config->wuc_map_list[0].wucs) { + config->wuc_map_list[0].wucs) { LOG_ERR("KSI%d isn't in the same wuc node!", i); } } -- cgit v1.2.1 From 5636337247a487333c3374bfbdfdf951663eb787 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:21 -0600 Subject: board/nami/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9159849527348e007506d7ec6505b6f717ce9b52 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728720 Reviewed-by: Jeremy Bettis --- board/nami/usb_pd_policy.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/board/nami/usb_pd_policy.c b/board/nami/usb_pd_policy.c index c1d5591d7c..3f0098f5e1 100644 --- a/board/nami/usb_pd_policy.c +++ b/board/nami/usb_pd_policy.c @@ -22,12 +22,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { return vbus_en[port]; @@ -52,8 +52,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 1); + gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1); /* Ensure we advertise the proper available current quota */ charge_manager_source_port(port, 1); @@ -103,8 +102,7 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_PMIC_SLP_SUS_L); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) -- cgit v1.2.1 From ec5a9f96d744dc7dfb9ac570320c9749edd14214 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:46 -0600 Subject: include/shared_mem.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If378a1ea7efc2a9b502ff99e8d11be7ee1d82ef9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730405 Reviewed-by: Jeremy Bettis --- include/shared_mem.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/shared_mem.h b/include/shared_mem.h index eadac22a48..e896f64e04 100644 --- a/include/shared_mem.h +++ b/include/shared_mem.h @@ -46,10 +46,10 @@ int shared_mem_size(void); */ int shared_mem_acquire(int size, char **dest_ptr); -#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \ - ({ \ - SHARED_MEM_CHECK_SIZE(size); \ - shared_mem_acquire((size), (dest_ptr)); \ +#define SHARED_MEM_ACQUIRE_CHECK(size, dest_ptr) \ + ({ \ + SHARED_MEM_CHECK_SIZE(size); \ + shared_mem_acquire((size), (dest_ptr)); \ }) /** @@ -85,4 +85,4 @@ extern struct shm_buffer *free_buf_chain; extern struct shm_buffer *allocced_buf_chain; #endif -#endif /* __CROS_EC_SHARED_MEM_H */ +#endif /* __CROS_EC_SHARED_MEM_H */ -- cgit v1.2.1 From 9bd8ce6570c1c1ff47a93a6f759e5deb86df9bc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:16 -0600 Subject: board/bloog/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iddcd41a35547f093aa32faf445f08e228f5f769c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728036 Reviewed-by: Jeremy Bettis --- board/bloog/led.c | 55 +++++++++++++++++++++++++++++-------------------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/board/bloog/led.c b/board/bloog/led.c index 609b330a56..7b623ef4f8 100644 --- a/board/bloog/led.c +++ b/board/bloog/led.c @@ -24,11 +24,9 @@ #define LED_TICKS_PER_CYCLE 10 #define LED_ON_TICKS 5 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -36,15 +34,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color_battery(int port, enum led_color color) { gpio_set_level(port ? GPIO_LED_AMBER_C1_L : GPIO_LED_AMBER_C0_L, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(port ? GPIO_LED_WHITE_C1_L : GPIO_LED_WHITE_C0_L, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_set_color_power(enum led_color color) @@ -141,15 +139,14 @@ static void led_set_battery(void) */ if (!board_is_convertible()) { if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && - charge_get_state() != PWR_STATE_CHARGE) { - + CHIPSET_STATE_STANDBY) && + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; - led_set_color_battery(0, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); - led_set_color_battery(1, power_ticks & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery(0, power_ticks & 0x4 ? LED_WHITE : + LED_OFF); + led_set_color_battery(1, power_ticks & 0x4 ? LED_WHITE : + LED_OFF); return; } } @@ -164,9 +161,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(1, (battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_battery( + 1, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(1, LED_OFF); } @@ -175,17 +175,19 @@ static void led_set_battery(void) led_set_color_battery(0, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; @@ -205,9 +207,10 @@ static void led_set_power(void) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY)) - led_set_color_power((power_tick % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_power( + (power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 98777afa97ee48dfc19725cc45a757e3c052edf7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:58 -0600 Subject: test/kb_8042.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ice5b264d59ce0f586811b643751ed48ddf00afaf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730480 Reviewed-by: Jeremy Bettis --- test/kb_8042.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/test/kb_8042.c b/test/kb_8042.c index 9705b506fe..0bd0c273c4 100644 --- a/test/kb_8042.c +++ b/test/kb_8042.c @@ -20,7 +20,7 @@ #include "timer.h" #include "util.h" -static const char *action[2] = {"release", "press"}; +static const char *action[2] = { "release", "press" }; #define BUF_SIZE 16 static char lpc_char_buf[BUF_SIZE]; @@ -274,8 +274,8 @@ static const struct ec_response_keybd_config keybd_config = { }, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &keybd_config; } @@ -285,8 +285,8 @@ static int test_ec_cmd_get_keybd_config(void) struct ec_response_keybd_config resp; int rv; - rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0, - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_GET_KEYBD_CONFIG, 0, NULL, 0, &resp, + sizeof(resp)); if (rv != EC_RES_SUCCESS) { ccprintf("Error: EC_CMD_GET_KEYBD_CONFIG cmd returns %d\n", rv); return EC_ERROR_INVAL; @@ -307,18 +307,18 @@ static int test_vivaldi_top_keys(void) /* Test REFRESH key */ write_cmd_byte(read_cmd_byte() | I8042_XLATE); - press_key(2, 3, 1); /* Press T2 */ - VERIFY_LPC_CHAR("\xe0\x67"); /* Check REFRESH scancode in set-1 */ + press_key(2, 3, 1); /* Press T2 */ + VERIFY_LPC_CHAR("\xe0\x67"); /* Check REFRESH scancode in set-1 */ /* Test SNAPSHOT key */ write_cmd_byte(read_cmd_byte() | I8042_XLATE); - press_key(4, 3, 1); /* Press T2 */ - VERIFY_LPC_CHAR("\xe0\x13"); /* Check SNAPSHOT scancode in set-1 */ + press_key(4, 3, 1); /* Press T2 */ + VERIFY_LPC_CHAR("\xe0\x13"); /* Check SNAPSHOT scancode in set-1 */ /* Test VOL_UP key */ write_cmd_byte(read_cmd_byte() | I8042_XLATE); - press_key(5, 3, 1); /* Press T2 */ - VERIFY_LPC_CHAR("\xe0\x30"); /* Check VOL_UP scancode in set-1 */ + press_key(5, 3, 1); /* Press T2 */ + VERIFY_LPC_CHAR("\xe0\x30"); /* Check VOL_UP scancode in set-1 */ return EC_SUCCESS; } -- cgit v1.2.1 From 3de1522f1dfc5f1b742e1a56178a2d585aeed072 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:20 -0600 Subject: common/lid_switch.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac0c96d49ba40431e7cb8705349a8b36a334cb66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729662 Reviewed-by: Jeremy Bettis --- common/lid_switch.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/common/lid_switch.c b/common/lid_switch.c index 050bbd9512..dd82544b2f 100644 --- a/common/lid_switch.c +++ b/common/lid_switch.c @@ -16,15 +16,15 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SWITCH, outstr) -#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args) /* if no X-macro is defined for LID switch GPIO, use GPIO_LID_OPEN as default */ #ifndef CONFIG_LID_SWITCH_GPIO_LIST #define CONFIG_LID_SWITCH_GPIO_LIST LID_GPIO(GPIO_LID_OPEN) #endif -static int debounced_lid_open; /* Debounced lid state */ -static int forced_lid_open; /* Forced lid open */ +static int debounced_lid_open; /* Debounced lid state */ +static int forced_lid_open; /* Forced lid open */ /** * Get raw lid switch state. @@ -87,7 +87,7 @@ static void lid_init(void) if (raw_lid_open()) debounced_lid_open = 1; - /* Enable interrupts, now that we've initialized */ + /* Enable interrupts, now that we've initialized */ #define LID_GPIO(gpio) gpio_enable_interrupt(gpio); CONFIG_LID_SWITCH_GPIO_LIST #undef LID_GPIO @@ -138,18 +138,14 @@ static int command_lidopen(int argc, char **argv) lid_switch_open(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen, - NULL, - "Simulate lid open"); +DECLARE_CONSOLE_COMMAND(lidopen, command_lidopen, NULL, "Simulate lid open"); static int command_lidclose(int argc, char **argv) { lid_switch_close(); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose, - NULL, - "Simulate lid close"); +DECLARE_CONSOLE_COMMAND(lidclose, command_lidclose, NULL, "Simulate lid close"); static int command_lidstate(int argc, char **argv) { @@ -157,9 +153,7 @@ static int command_lidstate(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate, - NULL, - "Get state of lid"); +DECLARE_CONSOLE_COMMAND(lidstate, command_lidstate, NULL, "Get state of lid"); /** * Host command to enable/disable lid opened. @@ -176,5 +170,4 @@ static enum ec_status hc_force_lid_open(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_FORCE_LID_OPEN, hc_force_lid_open, EC_VER_MASK(0)); -- cgit v1.2.1 From deaa451f946bb025ccbf7fdb4c6775873a2efdc0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:50 -0600 Subject: common/keyboard_8042_sharedlib.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e6ed4be10a35d3f5e846f4438cea79abdb30580 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729640 Reviewed-by: Jeremy Bettis --- common/keyboard_8042_sharedlib.c | 163 ++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 88 deletions(-) diff --git a/common/keyboard_8042_sharedlib.c b/common/keyboard_8042_sharedlib.c index a2ed5c4445..5a3c0e12d8 100644 --- a/common/keyboard_8042_sharedlib.c +++ b/common/keyboard_8042_sharedlib.c @@ -17,25 +17,25 @@ #ifndef CONFIG_KEYBOARD_CUSTOMIZATION /* The standard Chrome OS keyboard matrix table in scan code set 2. */ static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000}, - {0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015}, - {0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024}, - {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d}, - {0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d}, - {0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043}, - {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c}, - {0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059}, - {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d}, - {0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044}, - {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 }, + { 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 }, + { 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d }, + { 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d }, + { 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c }, + { 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d }, + { 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, #ifndef CONFIG_KEYBOARD_KEYPAD - {0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, - {0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b}, + { 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 }, + { 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b }, #else - {0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, - {0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b}, - {0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070}, - {0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a}, + { 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 }, + { 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b }, + { 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 }, + { 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a }, #endif }; @@ -68,37 +68,32 @@ void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val) * see scancode_translate_set2_to_1 below). */ SHAREDLIB(const uint8_t scancode_translate_table[128] = { - 0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, - 0x64, 0x44, 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, - 0x65, 0x38, 0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, - 0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, - 0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, - 0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, - 0x69, 0x31, 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, - 0x6a, 0x72, 0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, - 0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, - 0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, - 0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, - 0x3a, 0x36, 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, - 0x55, 0x56, 0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, - 0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, - 0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, - 0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, -}); - + 0xff, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44, + 0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38, 0x2a, 0x70, + 0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71, 0x2c, 0x1f, 0x1e, 0x11, + 0x03, 0x5b, 0x67, 0x2e, 0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, + 0x68, 0x39, 0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31, + 0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72, 0x32, 0x24, + 0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33, 0x25, 0x17, 0x18, 0x0b, + 0x0a, 0x60, 0x6c, 0x34, 0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, + 0x6d, 0x73, 0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36, + 0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56, 0x77, 0x78, + 0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f, 0x7d, 0x4b, 0x47, 0x7e, + 0x7f, 0x6f, 0x52, 0x53, 0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, + 0x57, 0x4e, 0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, + }); #ifdef CONFIG_KEYBOARD_DEBUG -SHAREDLIB(const -static char * const keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = { - "UNKNOWN", "F1", "F2", "F3", - "F4", "F5", "F6", "F7", - "F8", "F9", "F10", "F11", - "F12", "F13", "F14", "F15", - "L-ALT", "R-ALT", "L-CTR", "R-CTR", - "L-SHT", "R-SHT", "ENTER", "SPACE", - "B-SPC", "TAB", "SEARC", "LEFT", - "RIGHT", "DOWN", "UP", "ESC", -}); +SHAREDLIB( + const static char *const + keycap_long_label[KLLI_MAX & KEYCAP_LONG_LABEL_INDEX_BITMASK] = { + "UNKNOWN", "F1", "F2", "F3", "F4", "F5", + "F6", "F7", "F8", "F9", "F10", "F11", + "F12", "F13", "F14", "F15", "L-ALT", "R-ALT", + "L-CTR", "R-CTR", "L-SHT", "R-SHT", "ENTER", "SPACE", + "B-SPC", "TAB", "SEARC", "LEFT", "RIGHT", "DOWN", + "UP", "ESC", + }); const char *get_keycap_long_label(uint8_t idx) { @@ -109,38 +104,30 @@ const char *get_keycap_long_label(uint8_t idx) #ifndef CONFIG_KEYBOARD_CUSTOMIZATION static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC, - KLLI_R_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_F11, KLLI_ESC, KLLI_TAB, '~', - 'a', 'z', '1', 'q'}, - {KLLI_F1, KLLI_F4, KLLI_F3, KLLI_F2, - 'd', 'c', '3', 'e'}, - {'b', 'g', 't', '5', - 'f', 'v', '4', 'r'}, - {KLLI_F10, KLLI_F7, KLLI_F6, KLLI_F5, - 's', 'x', '2', 'w'}, - {KLLI_UNKNO, KLLI_F12, ']', KLLI_F13, - 'k', ',', '8', 'i'}, - {'n', 'h', 'y', '6', - 'j', 'm', '7', 'u'}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT}, - {'=', '\'', '[', '-', - ';', '/', '0', 'p'}, - {KLLI_F14, KLLI_F9, KLLI_F8, KLLI_UNKNO, - '|', '.', '9', 'o'}, - {KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO}, - {KLLI_F15, KLLI_B_SPC, KLLI_UNKNO, '\\', - KLLI_ENTER, KLLI_SPACE, KLLI_DOWN, KLLI_UP}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT}, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_L_CTR, KLLI_SEARC, KLLI_R_CTR, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_F11, KLLI_ESC, KLLI_TAB, '~', 'a', 'z', '1', 'q' }, + { KLLI_F1, KLLI_F4, KLLI_F3, KLLI_F2, 'd', 'c', '3', 'e' }, + { 'b', 'g', 't', '5', 'f', 'v', '4', 'r' }, + { KLLI_F10, KLLI_F7, KLLI_F6, KLLI_F5, 's', 'x', '2', 'w' }, + { KLLI_UNKNO, KLLI_F12, ']', KLLI_F13, 'k', ',', '8', 'i' }, + { 'n', 'h', 'y', '6', 'j', 'm', '7', 'u' }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_L_SHT, KLLI_UNKNO, KLLI_R_SHT }, + { '=', '\'', '[', '-', ';', '/', '0', 'p' }, + { KLLI_F14, KLLI_F9, KLLI_F8, KLLI_UNKNO, '|', '.', '9', 'o' }, + { KLLI_R_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_L_ALT, KLLI_UNKNO }, + { KLLI_F15, KLLI_B_SPC, KLLI_UNKNO, '\\', KLLI_ENTER, KLLI_SPACE, + KLLI_DOWN, KLLI_UP }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_RIGHT, KLLI_LEFT }, #ifdef CONFIG_KEYBOARD_KEYPAD /* TODO: Populate these */ - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, #endif }; @@ -174,16 +161,16 @@ uint8_t scancode_translate_set2_to_1(uint8_t code) * Must be in the same order as defined in keyboard_button_type. */ SHAREDLIB(const struct button_8042_t buttons_8042[] = { - {SCANCODE_POWER, 0}, - {SCANCODE_VOLUME_DOWN, 1}, - {SCANCODE_VOLUME_UP, 1}, - {SCANCODE_1, 1}, - {SCANCODE_2, 1}, - {SCANCODE_3, 1}, - {SCANCODE_4, 1}, - {SCANCODE_5, 1}, - {SCANCODE_6, 1}, - {SCANCODE_7, 1}, - {SCANCODE_8, 1}, -}); + { SCANCODE_POWER, 0 }, + { SCANCODE_VOLUME_DOWN, 1 }, + { SCANCODE_VOLUME_UP, 1 }, + { SCANCODE_1, 1 }, + { SCANCODE_2, 1 }, + { SCANCODE_3, 1 }, + { SCANCODE_4, 1 }, + { SCANCODE_5, 1 }, + { SCANCODE_6, 1 }, + { SCANCODE_7, 1 }, + { SCANCODE_8, 1 }, + }); BUILD_ASSERT(ARRAY_SIZE(buttons_8042) == KEYBOARD_BUTTON_COUNT); -- cgit v1.2.1 From dc8fba548e437ab6bcfc47f4f11b13ef4c497b33 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:51 -0600 Subject: board/pompom/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49ab4fd64e4063e96e129d7496baa4118ee226ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728839 Reviewed-by: Jeremy Bettis --- board/pompom/board.h | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/board/pompom/board.h b/board/pompom/board.h index 110774cb97..1b9557d4e3 100644 --- a/board/pompom/board.h +++ b/board/pompom/board.h @@ -12,7 +12,7 @@ #include "board_revs.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -72,12 +72,7 @@ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -87,11 +82,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; enum battery_type { BATTERY_BYD, -- cgit v1.2.1 From e1f4fc01221952a266e4a4b2da96fdc68f1fc359 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:27 -0600 Subject: board/taeko/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ab37f008f9a0669c1bfb9a04d3691afb9d7b0ce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728984 Reviewed-by: Jeremy Bettis --- board/taeko/led.c | 61 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/board/taeko/led.c b/board/taeko/led.c index 35d4fe4146..be1bdde30a 100644 --- a/board/taeko/led.c +++ b/board/taeko/led.c @@ -14,44 +14,49 @@ #include "led_common.h" #include "gpio.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 048ecc19d2d7b5343ac6dc252aa02d60b0c55a52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:43 -0600 Subject: board/lick/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id330d474d96ac32537ebe96bc6971d6d9f603ab8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728623 Reviewed-by: Jeremy Bettis --- board/lick/board.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/board/lick/board.h b/board/lick/board.h index 5c75a38c84..7f84f31aae 100644 --- a/board/lick/board.h +++ b/board/lick/board.h @@ -30,8 +30,8 @@ #define CONFIG_CMD_ACCEL_INFO /* Sensors */ -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -50,10 +50,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT, }; @@ -64,18 +64,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From e6f275bb2f98c6f661efef825acd9e96cba34b84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:32 -0600 Subject: common/math_util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idf891d7c3bceabe6ed337221ff1557ec506a6bc1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729665 Reviewed-by: Jeremy Bettis --- common/math_util.c | 108 +++++++++++++++++++++++++---------------------------- 1 file changed, 51 insertions(+), 57 deletions(-) diff --git a/common/math_util.c b/common/math_util.c index ff305438eb..3640f15ed9 100644 --- a/common/math_util.c +++ b/common/math_util.c @@ -11,18 +11,18 @@ #include "util.h" /* For cosine lookup table, define the increment and the size of the table. */ -#define COSINE_LUT_INCR_DEG 5 -#define COSINE_LUT_SIZE ((180 / COSINE_LUT_INCR_DEG) + 1) +#define COSINE_LUT_INCR_DEG 5 +#define COSINE_LUT_SIZE ((180 / COSINE_LUT_INCR_DEG) + 1) /* Lookup table for the value of cosine from 0 degrees to 180 degrees. */ static const fp_t cos_lut[] = { - FLOAT_TO_FP( 1.00000), FLOAT_TO_FP( 0.99619), FLOAT_TO_FP( 0.98481), - FLOAT_TO_FP( 0.96593), FLOAT_TO_FP( 0.93969), FLOAT_TO_FP( 0.90631), - FLOAT_TO_FP( 0.86603), FLOAT_TO_FP( 0.81915), FLOAT_TO_FP( 0.76604), - FLOAT_TO_FP( 0.70711), FLOAT_TO_FP( 0.64279), FLOAT_TO_FP( 0.57358), - FLOAT_TO_FP( 0.50000), FLOAT_TO_FP( 0.42262), FLOAT_TO_FP( 0.34202), - FLOAT_TO_FP( 0.25882), FLOAT_TO_FP( 0.17365), FLOAT_TO_FP( 0.08716), - FLOAT_TO_FP( 0.00000), FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365), + FLOAT_TO_FP(1.00000), FLOAT_TO_FP(0.99619), FLOAT_TO_FP(0.98481), + FLOAT_TO_FP(0.96593), FLOAT_TO_FP(0.93969), FLOAT_TO_FP(0.90631), + FLOAT_TO_FP(0.86603), FLOAT_TO_FP(0.81915), FLOAT_TO_FP(0.76604), + FLOAT_TO_FP(0.70711), FLOAT_TO_FP(0.64279), FLOAT_TO_FP(0.57358), + FLOAT_TO_FP(0.50000), FLOAT_TO_FP(0.42262), FLOAT_TO_FP(0.34202), + FLOAT_TO_FP(0.25882), FLOAT_TO_FP(0.17365), FLOAT_TO_FP(0.08716), + FLOAT_TO_FP(0.00000), FLOAT_TO_FP(-0.08716), FLOAT_TO_FP(-0.17365), FLOAT_TO_FP(-0.25882), FLOAT_TO_FP(-0.34202), FLOAT_TO_FP(-0.42262), FLOAT_TO_FP(-0.50000), FLOAT_TO_FP(-0.57358), FLOAT_TO_FP(-0.64279), FLOAT_TO_FP(-0.70711), FLOAT_TO_FP(-0.76604), FLOAT_TO_FP(-0.81915), @@ -32,7 +32,6 @@ static const fp_t cos_lut[] = { }; BUILD_ASSERT(ARRAY_SIZE(cos_lut) == COSINE_LUT_SIZE); - fp_t arc_cos(fp_t x) { int i; @@ -48,8 +47,8 @@ fp_t arc_cos(fp_t x) * interpolate for precision. */ /* TODO(crosbug.com/p/25600): Optimize with binary search. */ - for (i = 0; i < COSINE_LUT_SIZE-1; i++) { - if (x >= cos_lut[i+1]) { + for (i = 0; i < COSINE_LUT_SIZE - 1; i++) { + if (x >= cos_lut[i + 1]) { const fp_t interp = fp_div(cos_lut[i] - x, cos_lut[i] - cos_lut[i + 1]); @@ -104,7 +103,7 @@ int int_sqrtf(fp_inter_t x) * infrequently enough it doesn't matter. */ if (x <= 0) - return 0; /* Yeah, for imaginary numbers too */ + return 0; /* Yeah, for imaginary numbers too */ else if (x >= (fp_inter_t)rmax * rmax) return rmax; @@ -138,9 +137,8 @@ fp_t fp_sqrtf(fp_t x) int vector_magnitude(const intv3_t v) { - fp_inter_t sum = (fp_inter_t)v[0] * v[0] + - (fp_inter_t)v[1] * v[1] + - (fp_inter_t)v[2] * v[2]; + fp_inter_t sum = (fp_inter_t)v[0] * v[0] + (fp_inter_t)v[1] * v[1] + + (fp_inter_t)v[2] * v[2]; return int_sqrtf(sum); } @@ -155,8 +153,7 @@ void cross_product(const intv3_t v1, const intv3_t v2, intv3_t v) fp_inter_t dot_product(const intv3_t v1, const intv3_t v2) { - return (fp_inter_t)v1[X] * v2[X] + - (fp_inter_t)v1[Y] * v2[Y] + + return (fp_inter_t)v1[X] * v2[X] + (fp_inter_t)v1[Y] * v2[Y] + (fp_inter_t)v1[Z] * v2[Z]; } @@ -215,17 +212,13 @@ void rotate(const intv3_t v, const mat33_fp_t R, intv3_t res) return; } - /* Rotate */ - t[0] = (fp_inter_t)v[0] * R[0][0] + - (fp_inter_t)v[1] * R[1][0] + - (fp_inter_t)v[2] * R[2][0]; - t[1] = (fp_inter_t)v[0] * R[0][1] + - (fp_inter_t)v[1] * R[1][1] + - (fp_inter_t)v[2] * R[2][1]; - t[2] = (fp_inter_t)v[0] * R[0][2] + - (fp_inter_t)v[1] * R[1][2] + - (fp_inter_t)v[2] * R[2][2]; + t[0] = (fp_inter_t)v[0] * R[0][0] + (fp_inter_t)v[1] * R[1][0] + + (fp_inter_t)v[2] * R[2][0]; + t[1] = (fp_inter_t)v[0] * R[0][1] + (fp_inter_t)v[1] * R[1][1] + + (fp_inter_t)v[2] * R[2][1]; + t[2] = (fp_inter_t)v[0] * R[0][2] + (fp_inter_t)v[1] * R[1][2] + + (fp_inter_t)v[2] * R[2][2]; /* Scale by fixed point shift when writing back to result */ res[0] = FP_TO_INT(t[0]); @@ -244,38 +237,39 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res) return; } - deter = fp_mul(R[0][0], (fp_mul(R[1][1], R[2][2]) - - fp_mul(R[2][1], R[1][2]))) - - fp_mul(R[0][1], (fp_mul(R[1][0], R[2][2]) - - fp_mul(R[1][2], R[2][0]))) + - fp_mul(R[0][2], (fp_mul(R[1][0], R[2][1]) - - fp_mul(R[1][1], R[2][0]))); + deter = fp_mul(R[0][0], + (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2]))) - + fp_mul(R[0][1], + (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0]))) + + fp_mul(R[0][2], + (fp_mul(R[1][0], R[2][1]) - fp_mul(R[1][1], R[2][0]))); /* * invert the matrix: from * http://stackoverflow.com/questions/983999/ * simple-3x3-matrix-inverse-code-c */ - t[0] = (fp_inter_t)v[0] * (fp_mul(R[1][1], R[2][2]) - - fp_mul(R[2][1], R[1][2])) - - (fp_inter_t)v[1] * (fp_mul(R[1][0], R[2][2]) - - fp_mul(R[1][2], R[2][0])) + - (fp_inter_t)v[2] * (fp_mul(R[1][0], R[2][1]) - - fp_mul(R[2][0], R[1][1])); - - t[1] = (fp_inter_t)v[0] * (fp_mul(R[0][1], R[2][2]) - - fp_mul(R[0][2], R[2][1])) * -1 + - (fp_inter_t)v[1] * (fp_mul(R[0][0], R[2][2]) - - fp_mul(R[0][2], R[2][0])) - - (fp_inter_t)v[2] * (fp_mul(R[0][0], R[2][1]) - - fp_mul(R[2][0], R[0][1])); - - t[2] = (fp_inter_t)v[0] * (fp_mul(R[0][1], R[1][2]) - - fp_mul(R[0][2], R[1][1])) - - (fp_inter_t)v[1] * (fp_mul(R[0][0], R[1][2]) - - fp_mul(R[1][0], R[0][2])) + - (fp_inter_t)v[2] * (fp_mul(R[0][0], R[1][1]) - - fp_mul(R[1][0], R[0][1])); + t[0] = (fp_inter_t)v[0] * + (fp_mul(R[1][1], R[2][2]) - fp_mul(R[2][1], R[1][2])) - + (fp_inter_t)v[1] * + (fp_mul(R[1][0], R[2][2]) - fp_mul(R[1][2], R[2][0])) + + (fp_inter_t)v[2] * + (fp_mul(R[1][0], R[2][1]) - fp_mul(R[2][0], R[1][1])); + + t[1] = (fp_inter_t)v[0] * + (fp_mul(R[0][1], R[2][2]) - fp_mul(R[0][2], R[2][1])) * + -1 + + (fp_inter_t)v[1] * + (fp_mul(R[0][0], R[2][2]) - fp_mul(R[0][2], R[2][0])) - + (fp_inter_t)v[2] * + (fp_mul(R[0][0], R[2][1]) - fp_mul(R[2][0], R[0][1])); + + t[2] = (fp_inter_t)v[0] * + (fp_mul(R[0][1], R[1][2]) - fp_mul(R[0][2], R[1][1])) - + (fp_inter_t)v[1] * + (fp_mul(R[0][0], R[1][2]) - fp_mul(R[1][0], R[0][2])) + + (fp_inter_t)v[2] * + (fp_mul(R[0][0], R[1][1]) - fp_mul(R[1][0], R[0][1])); /* Scale by fixed point shift when writing back to result */ res[0] = FP_TO_INT(fp_div(t[0], deter)); @@ -287,8 +281,8 @@ void rotate_inv(const intv3_t v, const mat33_fp_t R, intv3_t res) int round_divide(int64_t dividend, int divisor) { return (dividend > 0) ^ (divisor > 0) ? - (dividend - divisor / 2) / divisor : - (dividend + divisor / 2) / divisor; + (dividend - divisor / 2) / divisor : + (dividend + divisor / 2) / divisor; } #if ULONG_MAX == 0xFFFFFFFFUL @@ -303,7 +297,7 @@ uint64_t bitmask_uint64(int offset) { union mask64_t { struct { -#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) +#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) uint32_t lo; uint32_t hi; #elif (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) -- cgit v1.2.1 From 6da5aaab43a163981fda7b26ca24c567e53e313e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:42 -0600 Subject: board/eldrid/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe806f3e0e149276a43f266d1a43dfd8a0985c92 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728307 Reviewed-by: Jeremy Bettis --- board/eldrid/sensors.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/eldrid/sensors.c b/board/eldrid/sensors.c index a9248938a3..986606fe6b 100644 --- a/board/eldrid/sensors.c +++ b/board/eldrid/sensors.c @@ -30,17 +30,13 @@ static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From 01545d06bd3a9da5257690d08309eeecb766d6bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:55 -0600 Subject: board/kinox/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14e4a68b945c97b0f8a2c00601b867f01ba6cc86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728535 Reviewed-by: Jeremy Bettis --- board/kinox/fw_config.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/kinox/fw_config.h b/board/kinox/fw_config.h index 0d79d55376..8e30af576a 100644 --- a/board/kinox/fw_config.h +++ b/board/kinox/fw_config.h @@ -14,11 +14,7 @@ * Source of truth is the project/brask/kinox/config.star configuration file. */ -enum ec_cfg_dp_display { - ABSENT = 0, - DB_HDMI = 1, - DB_DP = 2 -}; +enum ec_cfg_dp_display { ABSENT = 0, DB_HDMI = 1, DB_DP = 2 }; union kinox_cbi_fw_config { struct { -- cgit v1.2.1 From 2a3840fac94a9d376cdbf7e0431a927303cdc161 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:30 -0600 Subject: driver/charger/bd9995x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If80d574afeccdc792f13c59e1dba7febbde72322 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729956 Reviewed-by: Jeremy Bettis --- driver/charger/bd9995x.h | 500 +++++++++++++++++++++++------------------------ 1 file changed, 249 insertions(+), 251 deletions(-) diff --git a/driver/charger/bd9995x.h b/driver/charger/bd9995x.h index a1f1bdb64f..1b7e4b9ec7 100644 --- a/driver/charger/bd9995x.h +++ b/driver/charger/bd9995x.h @@ -8,11 +8,11 @@ #ifndef __CROS_EC_BD9995X_H #define __CROS_EC_BD9995X_H -#define BD9995X_ADDR_FLAGS 0x09 +#define BD9995X_ADDR_FLAGS 0x09 -#define BD9995X_CHARGER_NAME "bd9995x" -#define BD99955_CHIP_ID 0x221 -#define BD99956_CHIP_ID 0x331 +#define BD9995X_CHARGER_NAME "bd9995x" +#define BD99955_CHIP_ID 0x221 +#define BD99956_CHIP_ID 0x331 /* BD9995X commands to change the command code map */ enum bd9995x_command { @@ -35,7 +35,7 @@ enum bd9995x_charge_port { }; /* Min. charge current w/ no battery to prevent collapse */ -#define BD9995X_NO_BATTERY_CHARGE_I_MIN 512 +#define BD9995X_NO_BATTERY_CHARGE_I_MIN 512 /* * BC1.2 minimum voltage threshold. @@ -43,285 +43,283 @@ enum bd9995x_charge_port { * BD9995X Anti-Collapse Threshold Voltage Accuracy is -100mV to +100mV, * and Delta of 50mV. */ -#define BD9995X_BC12_MIN_VOLTAGE 4600 +#define BD9995X_BC12_MIN_VOLTAGE 4600 /* Battery Charger Commands */ -#define BD9995X_CMD_CHG_CURRENT 0x14 -#define BD9995X_CMD_CHG_VOLTAGE 0x15 -#define BD9995X_CMD_IBUS_LIM_SET 0x3C -#define BD9995X_CMD_ICC_LIM_SET 0x3D -#define BD9995X_CMD_PROTECT_SET 0x3E -#define BD9995X_CMD_MAP_SET 0x3F +#define BD9995X_CMD_CHG_CURRENT 0x14 +#define BD9995X_CMD_CHG_VOLTAGE 0x15 +#define BD9995X_CMD_IBUS_LIM_SET 0x3C +#define BD9995X_CMD_ICC_LIM_SET 0x3D +#define BD9995X_CMD_PROTECT_SET 0x3E +#define BD9995X_CMD_MAP_SET 0x3F /* Extended commands */ -#define BD9995X_CMD_CHGSTM_STATUS 0x00 -#define BD9995X_CMD_VBAT_VSYS_STATUS 0x01 -#define BD9995X_CMD_VBUS_VCC_STATUS 0x02 -#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8) +#define BD9995X_CMD_CHGSTM_STATUS 0x00 +#define BD9995X_CMD_VBAT_VSYS_STATUS 0x01 +#define BD9995X_CMD_VBUS_VCC_STATUS 0x02 +#define BD9995X_CMD_VBUS_VCC_STATUS_VCC_DETECT BIT(8) #define BD9995X_CMD_VBUS_VCC_STATUS_VBUS_DETECT BIT(0) -#define BD9995X_CMD_CHGOP_STATUS 0x03 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9) -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8) -#define BD9995X_BATTTEMP_MASK 0x700 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2 2 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3 3 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1 4 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6 -#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7 -#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1) - -#define BD9995X_CMD_WDT_STATUS 0x04 -#define BD9995X_CMD_CUR_ILIM_VAL 0x05 -#define BD9995X_CMD_SEL_ILIM_VAL 0x06 -#define BD9995X_CMD_EXT_IBUS_LIM_SET 0x07 -#define BD9995X_CMD_EXT_ICC_LIM_SET 0x08 -#define BD9995X_CMD_IOTG_LIM_SET 0x09 -#define BD9995X_CMD_VIN_CTRL_SET 0x0A -#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4) - -#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11) +#define BD9995X_CMD_CHGOP_STATUS 0x03 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP2 BIT(10) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP1 BIT(9) +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP0 BIT(8) +#define BD9995X_BATTTEMP_MASK 0x700 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_ROOMTEMP 0 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT1 1 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT2 2 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_HOT3 3 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD1 4 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_COLD2 5 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_DISABLE 6 +#define BD9995X_CMD_CHGOP_STATUS_BATTEMP_BATOPEN 7 +#define BD9995X_CMD_CHGOP_STATUS_RBOOST_UV BIT(1) + +#define BD9995X_CMD_WDT_STATUS 0x04 +#define BD9995X_CMD_CUR_ILIM_VAL 0x05 +#define BD9995X_CMD_SEL_ILIM_VAL 0x06 +#define BD9995X_CMD_EXT_IBUS_LIM_SET 0x07 +#define BD9995X_CMD_EXT_ICC_LIM_SET 0x08 +#define BD9995X_CMD_IOTG_LIM_SET 0x09 +#define BD9995X_CMD_VIN_CTRL_SET 0x0A +#define BD9995X_CMD_VIN_CTRL_SET_VSYS_PRIORITY BIT(4) + +#define BD9995X_CMD_VIN_CTRL_SET_PP_BOTH_THRU BIT(11) #define BD9995X_CMD_VIN_CTRL_SET_VBUS_PRIORITY BIT(7) -#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6) -#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5) +#define BD9995X_CMD_VIN_CTRL_SET_VBUS_EN BIT(6) +#define BD9995X_CMD_VIN_CTRL_SET_VCC_EN BIT(5) -#define BD9995X_CMD_CHGOP_SET1 0x0B -#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15) -#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14) +#define BD9995X_CMD_CHGOP_SET1 0x0B +#define BD9995X_CMD_CHGOP_SET1_DCP_2500_SEL BIT(15) +#define BD9995X_CMD_CHGOP_SET1_SDP_500_SEL BIT(14) #define BD9995X_CMD_CHGOP_SET1_ILIM_AUTO_DISEN BIT(13) -#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11) -#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10) +#define BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN BIT(11) +#define BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN BIT(10) #define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN BIT(9) -#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8) - -#define BD9995X_CMD_CHGOP_SET2 0x0C -#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8) -#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7) -#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6) -#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2) -#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2) -#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2) +#define BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG BIT(8) + +#define BD9995X_CMD_CHGOP_SET2 0x0C +#define BD9995X_CMD_CHGOP_SET2_BATT_LEARN BIT(8) +#define BD9995X_CMD_CHGOP_SET2_CHG_EN BIT(7) +#define BD9995X_CMD_CHGOP_SET2_USB_SUS BIT(6) +#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL (3 << 2) +#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_600 (0 << 2) +#define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_857 BIT(2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1000 (2 << 2) #define BD9995X_CMD_CHGOP_SET2_DCDC_CLK_SEL_1200 (3 << 2) -#define BD9995X_CMD_VBUSCLPS_TH_SET 0x0D -#define BD9995X_CMD_VCCCLPS_TH_SET 0x0E -#define BD9995X_CMD_CHGWDT_SET 0x0F -#define BD9995X_CMD_BATTWDT_SET 0x10 -#define BD9995X_CMD_VSYSREG_SET 0x11 -#define BD9995X_CMD_VSYSVAL_THH_SET 0x12 -#define BD9995X_CMD_VSYSVAL_THL_SET 0x13 -#define BD9995X_CMD_ITRICH_SET 0x14 - -#define BD9995X_CMD_IPRECH_SET 0x15 -#define BD9995X_IPRECH_MAX 1024 - -#define BD9995X_CMD_ICHG_SET 0x16 -#define BD9995X_CMD_ITERM_SET 0x17 -#define BD9995X_CMD_VPRECHG_TH_SET 0x18 -#define BD9995X_CMD_VRBOOST_SET 0x19 -#define BD9995X_CMD_VFASTCHG_REG_SET1 0x1A -#define BD9995X_CMD_VFASTCHG_REG_SET2 0x1B -#define BD9995X_CMD_VFASTCHG_REG_SET3 0x1C -#define BD9995X_CMD_VRECHG_SET 0x1D -#define BD9995X_CMD_VBATOVP_SET 0x1E -#define BD9995X_CMD_IBATSHORT_SET 0x1F -#define BD9995X_CMD_PROCHOT_CTRL_SET 0x20 -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1) -#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0) - -#define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21 -#define BD9995X_CMD_PROCHOT_INORM_SET 0x22 -#define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23 -#define BD9995X_CMD_PROCHOT_VSYS_SET 0x24 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3) -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW 0x04 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW 0x03 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW 0x02 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW 0x01 -#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW 0x00 -#define BD9995X_PMON_IOUT_ADC_READ_COUNT 128 - -#define BD9995X_CMD_PMON_DACIN_VAL 0x26 -#define BD9995X_CMD_IOUT_DACIN_VAL 0x27 -#define BD9995X_CMD_VCC_UCD_SET 0x28 +#define BD9995X_CMD_VBUSCLPS_TH_SET 0x0D +#define BD9995X_CMD_VCCCLPS_TH_SET 0x0E +#define BD9995X_CMD_CHGWDT_SET 0x0F +#define BD9995X_CMD_BATTWDT_SET 0x10 +#define BD9995X_CMD_VSYSREG_SET 0x11 +#define BD9995X_CMD_VSYSVAL_THH_SET 0x12 +#define BD9995X_CMD_VSYSVAL_THL_SET 0x13 +#define BD9995X_CMD_ITRICH_SET 0x14 + +#define BD9995X_CMD_IPRECH_SET 0x15 +#define BD9995X_IPRECH_MAX 1024 + +#define BD9995X_CMD_ICHG_SET 0x16 +#define BD9995X_CMD_ITERM_SET 0x17 +#define BD9995X_CMD_VPRECHG_TH_SET 0x18 +#define BD9995X_CMD_VRBOOST_SET 0x19 +#define BD9995X_CMD_VFASTCHG_REG_SET1 0x1A +#define BD9995X_CMD_VFASTCHG_REG_SET2 0x1B +#define BD9995X_CMD_VFASTCHG_REG_SET3 0x1C +#define BD9995X_CMD_VRECHG_SET 0x1D +#define BD9995X_CMD_VBATOVP_SET 0x1E +#define BD9995X_CMD_IBATSHORT_SET 0x1F +#define BD9995X_CMD_PROCHOT_CTRL_SET 0x20 +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 BIT(4) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 BIT(3) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 BIT(2) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 BIT(1) +#define BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0 BIT(0) + +#define BD9995X_CMD_PROCHOT_ICRIT_SET 0x21 +#define BD9995X_CMD_PROCHOT_INORM_SET 0x22 +#define BD9995X_CMD_PROCHOT_IDCHG_SET 0x23 +#define BD9995X_CMD_PROCHOT_VSYS_SET 0x24 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET 0x25 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IMON_INSEL BIT(9) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_INSEL BIT(8) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_OUT_EN BIT(7) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_SOURCE_SEL BIT(6) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_MASK 0x30 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_40V 0x03 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V 0x02 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_10V 0x01 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_05V 0x00 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_OUT_EN BIT(3) +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_MASK 0x07 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_64UAW 0x06 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_32UAW 0x05 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_16UAW 0x04 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_08UAW 0x03 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_04UAW 0x02 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW 0x01 +#define BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_01UAW 0x00 +#define BD9995X_PMON_IOUT_ADC_READ_COUNT 128 + +#define BD9995X_CMD_PMON_DACIN_VAL 0x26 +#define BD9995X_CMD_IOUT_DACIN_VAL 0x27 +#define BD9995X_CMD_VCC_UCD_SET 0x28 /* Bits for both VCC_UCD_SET and VBUS_UCD_SET regs */ /* Retry BC1.2 detection on set */ -#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12) +#define BD9995X_CMD_UCD_SET_BCSRETRY BIT(12) /* Enable BC1.2 detection, will automatically occur on VBUS detect */ -#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7) +#define BD9995X_CMD_UCD_SET_USBDETEN BIT(7) /* USB switch state auto-control */ -#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1) +#define BD9995X_CMD_UCD_SET_USB_SW_EN BIT(1) /* USB switch state, 1 = ON, only meaningful when USB_SW_EN = 0 */ -#define BD9995X_CMD_UCD_SET_USB_SW BIT(0) +#define BD9995X_CMD_UCD_SET_USB_SW BIT(0) -#define BD9995X_CMD_VCC_UCD_STATUS 0x29 +#define BD9995X_CMD_VCC_UCD_STATUS 0x29 /* Bits for both VCC_UCD_STATUS and VBUS_UCD_STATUS regs */ -#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15) -#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13) -#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12) -#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11) -#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6) -#define BD9995X_TYPE_MASK (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ - BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ - BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ - BD9995X_CMD_UCD_STATUS_PUPDET | \ - BD9995X_CMD_UCD_STATUS_CHGDET) +#define BD9995X_CMD_UCD_STATUS_DCDFAIL BIT(15) +#define BD9995X_CMD_UCD_STATUS_CHGPORT1 BIT(13) +#define BD9995X_CMD_UCD_STATUS_CHGPORT0 BIT(12) +#define BD9995X_CMD_UCD_STATUS_PUPDET BIT(11) +#define BD9995X_CMD_UCD_STATUS_CHGDET BIT(6) +#define BD9995X_TYPE_MASK \ + (BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ + BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_PUPDET | \ + BD9995X_CMD_UCD_STATUS_CHGDET) /* BC1.2 chargers */ -#define BD9995X_TYPE_CDP (BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ - BD9995X_CMD_UCD_STATUS_CHGDET) -#define BD9995X_TYPE_DCP (BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ - BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ - BD9995X_CMD_UCD_STATUS_CHGDET) -#define BD9995X_TYPE_SDP (BD9995X_CMD_UCD_STATUS_CHGPORT0) +#define BD9995X_TYPE_CDP \ + (BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGDET) +#define BD9995X_TYPE_DCP \ + (BD9995X_CMD_UCD_STATUS_CHGPORT1 | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ + BD9995X_CMD_UCD_STATUS_CHGDET) +#define BD9995X_TYPE_SDP (BD9995X_CMD_UCD_STATUS_CHGPORT0) /* non-standard BC1.2 chargers */ -#define BD9995X_TYPE_OTHER (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ - BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ - BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ - BD9995X_CMD_UCD_STATUS_CHGDET) -#define BD9995X_TYPE_PUP_PORT (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ - BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ - BD9995X_CMD_UCD_STATUS_PUPDET) +#define BD9995X_TYPE_OTHER \ + (BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT1 | \ + BD9995X_CMD_UCD_STATUS_CHGPORT0 | BD9995X_CMD_UCD_STATUS_CHGDET) +#define BD9995X_TYPE_PUP_PORT \ + (BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0 | \ + BD9995X_CMD_UCD_STATUS_PUPDET) /* Open ports */ -#define BD9995X_TYPE_OPEN_PORT (BD9995X_CMD_UCD_STATUS_DCDFAIL | \ - BD9995X_CMD_UCD_STATUS_CHGPORT0) -#define BD9995X_TYPE_VBUS_OPEN 0 - -#define BD9995X_CMD_VCC_IDD_STATUS 0x2A -#define BD9995X_CMD_VCC_UCD_FCTRL_SET 0x2B -#define BD9995X_CMD_VCC_UCD_FCTRL_EN 0x2C -#define BD9995X_CMD_VBUS_UCD_SET 0x30 -#define BD9995X_CMD_VBUS_UCD_STATUS 0x31 -#define BD9995X_CMD_VBUS_IDD_STATUS 0x32 -#define BD9995X_CMD_VBUS_UCD_FCTRL_SET 0x33 -#define BD9995X_CMD_VBUS_UCD_FCTRL_EN 0x34 -#define BD9995X_CMD_CHIP_ID 0x38 -#define BD9995X_CMD_CHIP_REV 0x39 -#define BD9995X_CMD_IC_SET1 0x3A -#define BD9995X_CMD_IC_SET2 0x3B -#define BD9995X_CMD_SYSTEM_STATUS 0x3C -#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1) -#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0) - -#define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D -#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1) -#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0) - -#define BD9995X_CMD_EXT_PROTECT_SET 0x3E -#define BD9995X_CMD_EXT_MAP_SET 0x3F -#define BD9995X_CMD_VM_CTRL_SET 0x40 -#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9) -#define BD9995X_CMD_THERM_WINDOW_SET1 0x41 -#define BD9995X_CMD_THERM_WINDOW_SET2 0x42 -#define BD9995X_CMD_THERM_WINDOW_SET3 0x43 -#define BD9995X_CMD_THERM_WINDOW_SET4 0x44 -#define BD9995X_CMD_THERM_WINDOW_SET5 0x45 -#define BD9995X_CMD_IBATP_TH_SET 0x46 -#define BD9995X_CMD_IBATM_TH_SET 0x47 -#define BD9995X_CMD_VBAT_TH_SET 0x48 -#define BD9995X_CMD_THERM_TH_SET 0x49 -#define BD9995X_CMD_IACP_TH_SET 0x4A -#define BD9995X_CMD_VACP_TH_SET 0x4B +#define BD9995X_TYPE_OPEN_PORT \ + (BD9995X_CMD_UCD_STATUS_DCDFAIL | BD9995X_CMD_UCD_STATUS_CHGPORT0) +#define BD9995X_TYPE_VBUS_OPEN 0 + +#define BD9995X_CMD_VCC_IDD_STATUS 0x2A +#define BD9995X_CMD_VCC_UCD_FCTRL_SET 0x2B +#define BD9995X_CMD_VCC_UCD_FCTRL_EN 0x2C +#define BD9995X_CMD_VBUS_UCD_SET 0x30 +#define BD9995X_CMD_VBUS_UCD_STATUS 0x31 +#define BD9995X_CMD_VBUS_IDD_STATUS 0x32 +#define BD9995X_CMD_VBUS_UCD_FCTRL_SET 0x33 +#define BD9995X_CMD_VBUS_UCD_FCTRL_EN 0x34 +#define BD9995X_CMD_CHIP_ID 0x38 +#define BD9995X_CMD_CHIP_REV 0x39 +#define BD9995X_CMD_IC_SET1 0x3A +#define BD9995X_CMD_IC_SET2 0x3B +#define BD9995X_CMD_SYSTEM_STATUS 0x3C +#define BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE BIT(1) +#define BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE BIT(0) + +#define BD9995X_CMD_SYSTEM_CTRL_SET 0x3D +#define BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD BIT(1) +#define BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST BIT(0) + +#define BD9995X_CMD_EXT_PROTECT_SET 0x3E +#define BD9995X_CMD_EXT_MAP_SET 0x3F +#define BD9995X_CMD_VM_CTRL_SET 0x40 +#define BD9995X_CMD_VM_CTRL_SET_EXTIADPEN BIT(9) +#define BD9995X_CMD_THERM_WINDOW_SET1 0x41 +#define BD9995X_CMD_THERM_WINDOW_SET2 0x42 +#define BD9995X_CMD_THERM_WINDOW_SET3 0x43 +#define BD9995X_CMD_THERM_WINDOW_SET4 0x44 +#define BD9995X_CMD_THERM_WINDOW_SET5 0x45 +#define BD9995X_CMD_IBATP_TH_SET 0x46 +#define BD9995X_CMD_IBATM_TH_SET 0x47 +#define BD9995X_CMD_VBAT_TH_SET 0x48 +#define BD9995X_CMD_THERM_TH_SET 0x49 +#define BD9995X_CMD_IACP_TH_SET 0x4A +#define BD9995X_CMD_VACP_TH_SET 0x4B /* Enable discharge when VBUS falls below BD9995X_VBUS_DISCHARGE_TH */ -#define BD9995X_VBUS_DISCHARGE_TH 3900 -#define BD9995X_CMD_VBUS_TH_SET 0x4C -#define BD9995X_CMD_VCC_TH_SET 0x4D - -#define BD9995X_CMD_VSYS_TH_SET 0x4E -#define BD9995X_CMD_EXTIADP_TH_SET 0x4F -#define BD9995X_CMD_IBATP_VAL 0x50 -#define BD9995X_CMD_IBATP_AVE_VAL 0x51 -#define BD9995X_CMD_IBATM_VAL 0x52 -#define BD9995X_CMD_IBATM_AVE_VAL 0x53 -#define BD9995X_CMD_VBAT_VAL 0x54 -#define BD9995X_CMD_VBAT_AVE_VAL 0x55 -#define BD9995X_CMD_THERM_VAL 0x56 -#define BD9995X_CMD_VTH_VAL 0x57 -#define BD9995X_CMD_IACP_VAL 0x58 -#define BD9995X_CMD_IACP_AVE_VAL 0x59 -#define BD9995X_CMD_VACP_VAL 0x5A -#define BD9995X_CMD_VACP_AVE_VAL 0x5B -#define BD9995X_CMD_VBUS_VAL 0x5C -#define BD9995X_CMD_VBUS_AVE_VAL 0x5D -#define BD9995X_CMD_VCC_VAL 0x5E -#define BD9995X_CMD_VCC_AVE_VAL 0x5F -#define BD9995X_CMD_VSYS_VAL 0x60 -#define BD9995X_CMD_VSYS_AVE_VAL 0x61 -#define BD9995X_CMD_EXTIADP_VAL 0x62 -#define BD9995X_CMD_EXTIADP_AVE_VAL 0x63 -#define BD9995X_CMD_VACPCLPS_TH_SET 0x64 -#define BD9995X_CMD_INT0_SET 0x68 -#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2) -#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1) -#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0) - -#define BD9995X_CMD_INT1_SET 0x69 +#define BD9995X_VBUS_DISCHARGE_TH 3900 +#define BD9995X_CMD_VBUS_TH_SET 0x4C +#define BD9995X_CMD_VCC_TH_SET 0x4D + +#define BD9995X_CMD_VSYS_TH_SET 0x4E +#define BD9995X_CMD_EXTIADP_TH_SET 0x4F +#define BD9995X_CMD_IBATP_VAL 0x50 +#define BD9995X_CMD_IBATP_AVE_VAL 0x51 +#define BD9995X_CMD_IBATM_VAL 0x52 +#define BD9995X_CMD_IBATM_AVE_VAL 0x53 +#define BD9995X_CMD_VBAT_VAL 0x54 +#define BD9995X_CMD_VBAT_AVE_VAL 0x55 +#define BD9995X_CMD_THERM_VAL 0x56 +#define BD9995X_CMD_VTH_VAL 0x57 +#define BD9995X_CMD_IACP_VAL 0x58 +#define BD9995X_CMD_IACP_AVE_VAL 0x59 +#define BD9995X_CMD_VACP_VAL 0x5A +#define BD9995X_CMD_VACP_AVE_VAL 0x5B +#define BD9995X_CMD_VBUS_VAL 0x5C +#define BD9995X_CMD_VBUS_AVE_VAL 0x5D +#define BD9995X_CMD_VCC_VAL 0x5E +#define BD9995X_CMD_VCC_AVE_VAL 0x5F +#define BD9995X_CMD_VSYS_VAL 0x60 +#define BD9995X_CMD_VSYS_AVE_VAL 0x61 +#define BD9995X_CMD_EXTIADP_VAL 0x62 +#define BD9995X_CMD_EXTIADP_AVE_VAL 0x63 +#define BD9995X_CMD_VACPCLPS_TH_SET 0x64 +#define BD9995X_CMD_INT0_SET 0x68 +#define BD9995X_CMD_INT0_SET_INT2_EN BIT(2) +#define BD9995X_CMD_INT0_SET_INT1_EN BIT(1) +#define BD9995X_CMD_INT0_SET_INT0_EN BIT(0) + +#define BD9995X_CMD_INT1_SET 0x69 /* Bits for both INT1 & INT2 reg */ -#define BD9995X_CMD_INT_SET_TH_DET BIT(9) -#define BD9995X_CMD_INT_SET_TH_RES BIT(8) -#define BD9995X_CMD_INT_SET_DET BIT(1) -#define BD9995X_CMD_INT_SET_RES BIT(0) -#define BD9995X_CMD_INT_VBUS_DET (BD9995X_CMD_INT_SET_RES | \ - BD9995X_CMD_INT_SET_DET) -#define BD9995X_CMD_INT_VBUS_TH (BD9995X_CMD_INT_SET_TH_RES | \ - BD9995X_CMD_INT_SET_TH_DET) - -#define BD9995X_CMD_INT2_SET 0x6A -#define BD9995X_CMD_INT3_SET 0x6B -#define BD9995X_CMD_INT4_SET 0x6C -#define BD9995X_CMD_INT5_SET 0x6D -#define BD9995X_CMD_INT6_SET 0x6E -#define BD9995X_CMD_INT7_SET 0x6F -#define BD9995X_CMD_INT0_STATUS 0x70 -#define BD9995X_CMD_INT1_STATUS 0x71 +#define BD9995X_CMD_INT_SET_TH_DET BIT(9) +#define BD9995X_CMD_INT_SET_TH_RES BIT(8) +#define BD9995X_CMD_INT_SET_DET BIT(1) +#define BD9995X_CMD_INT_SET_RES BIT(0) +#define BD9995X_CMD_INT_VBUS_DET \ + (BD9995X_CMD_INT_SET_RES | BD9995X_CMD_INT_SET_DET) +#define BD9995X_CMD_INT_VBUS_TH \ + (BD9995X_CMD_INT_SET_TH_RES | BD9995X_CMD_INT_SET_TH_DET) + +#define BD9995X_CMD_INT2_SET 0x6A +#define BD9995X_CMD_INT3_SET 0x6B +#define BD9995X_CMD_INT4_SET 0x6C +#define BD9995X_CMD_INT5_SET 0x6D +#define BD9995X_CMD_INT6_SET 0x6E +#define BD9995X_CMD_INT7_SET 0x6F +#define BD9995X_CMD_INT0_STATUS 0x70 +#define BD9995X_CMD_INT1_STATUS 0x71 /* Bits for both INT1_STATUS & INT2_STATUS reg */ -#define BD9995X_CMD_INT_STATUS_DET BIT(1) -#define BD9995X_CMD_INT_STATUS_RES BIT(0) - -#define BD9995X_CMD_INT2_STATUS 0x72 -#define BD9995X_CMD_INT3_STATUS 0x73 -#define BD9995X_CMD_INT4_STATUS 0x74 -#define BD9995X_CMD_INT5_STATUS 0x75 -#define BD9995X_CMD_INT6_STATUS 0x76 -#define BD9995X_CMD_INT7_STATUS 0x77 -#define BD9995X_CMD_REG0 0x78 -#define BD9995X_CMD_REG1 0x79 -#define BD9995X_CMD_OTPREG0 0x7A -#define BD9995X_CMD_OTPREG1 0x7B -#define BD9995X_CMD_SMBREG 0x7C +#define BD9995X_CMD_INT_STATUS_DET BIT(1) +#define BD9995X_CMD_INT_STATUS_RES BIT(0) + +#define BD9995X_CMD_INT2_STATUS 0x72 +#define BD9995X_CMD_INT3_STATUS 0x73 +#define BD9995X_CMD_INT4_STATUS 0x74 +#define BD9995X_CMD_INT5_STATUS 0x75 +#define BD9995X_CMD_INT6_STATUS 0x76 +#define BD9995X_CMD_INT7_STATUS 0x77 +#define BD9995X_CMD_REG0 0x78 +#define BD9995X_CMD_REG1 0x79 +#define BD9995X_CMD_OTPREG0 0x7A +#define BD9995X_CMD_OTPREG1 0x7B +#define BD9995X_CMD_SMBREG 0x7C /* Normal functionality - power save mode disabled. */ -#define BD9995X_PWR_SAVE_OFF 0 +#define BD9995X_PWR_SAVE_OFF 0 /* BGATE ON w/ PROCHOT# monitored only system voltage. */ -#define BD9995X_PWR_SAVE_LOW 0x1 +#define BD9995X_PWR_SAVE_LOW 0x1 /* BGATE ON w/ PROCHOT# monitored only system voltage every 1ms. */ -#define BD9995X_PWR_SAVE_MED 0x2 +#define BD9995X_PWR_SAVE_MED 0x2 /* BGATE ON w/o PROCHOT# monitoring. */ -#define BD9995X_PWR_SAVE_HIGH 0x5 +#define BD9995X_PWR_SAVE_HIGH 0x5 /* BGATE OFF */ -#define BD9995X_PWR_SAVE_MAX 0x6 -#define BD9995X_CMD_DEBUG_MODE_SET 0x7F +#define BD9995X_PWR_SAVE_MAX 0x6 +#define BD9995X_CMD_DEBUG_MODE_SET 0x7F /* * Non-standard interface functions - bd9995x integrates additional -- cgit v1.2.1 From 69153c9b86fe347255e853a0af468a5badba9bda Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:30 -0600 Subject: board/plankton/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idfa249403f5877961a3059787fdb53af58d2f09b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728834 Reviewed-by: Jeremy Bettis --- board/plankton/usb_pd_config.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/board/plankton/usb_pd_config.h b/board/plankton/usb_pd_config.h index fca6484069..17a2dcd456 100644 --- a/board/plankton/usb_pd_config.h +++ b/board/plankton/usb_pd_config.h @@ -50,7 +50,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -92,9 +92,8 @@ static inline void pd_tx_disable(int port, int polarity) { /* output low on SPI TX to disable the FET */ /* PA6 is SPI1_MISO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*6))) - | (1 << (2*6)); + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 6))) | (1 << (2 * 6)); /* put the low level reference in Hi-Z */ gpio_set_level(GPIO_USBC_CC1_TX_EN, 0); gpio_set_level(GPIO_USBC_CC2_TX_EN, 0); @@ -104,11 +103,10 @@ static inline void pd_tx_disable(int port, int polarity) static inline void pd_select_polarity(int port, int polarity) { /* use the right comparator non inverted input for COMP1 */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN - | (polarity ? - STM32_COMP_CMP1INSEL_INM4 : - STM32_COMP_CMP1INSEL_INM6); + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | + (polarity ? STM32_COMP_CMP1INSEL_INM4 : + STM32_COMP_CMP1INSEL_INM6); gpio_set_level(GPIO_USBC_POLARITY, polarity); } -- cgit v1.2.1 From 2e57ad3b830d4e866d4309e19da560a8887bacc0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:58 -0600 Subject: board/osiris/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e40aafb0e449e74c24d25a6a8a35a2111948ae1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728800 Reviewed-by: Jeremy Bettis --- board/osiris/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/osiris/i2c.c b/board/osiris/i2c.c index 7c88d306a7..23eac76a21 100644 --- a/board/osiris/i2c.c +++ b/board/osiris/i2c.c @@ -9,7 +9,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From 812268c6c255a5d0f245d2f3d8ea00878cbf47cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:20 -0600 Subject: test/math_util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8116da45d63948083783a93e4f1412696a912105 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730484 Reviewed-by: Jeremy Bettis --- test/math_util.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/test/math_util.c b/test/math_util.c index 6482888e55..0188384b2a 100644 --- a/test/math_util.c +++ b/test/math_util.c @@ -25,7 +25,7 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Test utilities */ /* Macro to compare two floats and check if they are equal within diff. */ -#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b) - diff) && (a) <= ((b) + diff)) +#define IS_FLOAT_EQUAL(a, b, diff) ((a) >= ((b)-diff) && (a) <= ((b) + diff)) #define ACOS_TOLERANCE_DEG 0.5f #define RAD_TO_DEG (180.0f / 3.1415926f) @@ -45,21 +45,19 @@ static int test_acos(void) return EC_SUCCESS; } - const mat33_fp_t test_matrices[] = { - {{ 0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} }, - {{ FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5)}, - { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6)}, - { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0} } + { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }, + { { FLOAT_TO_FP(1), 0, FLOAT_TO_FP(5) }, + { FLOAT_TO_FP(2), FLOAT_TO_FP(1), FLOAT_TO_FP(6) }, + { FLOAT_TO_FP(3), FLOAT_TO_FP(4), 0 } } }; - static int test_rotate(void) { int i, j, k; - intv3_t v = {1, 2, 3}; + intv3_t v = { 1, 2, 3 }; intv3_t w; for (i = 0; i < ARRAY_SIZE(test_matrices); i++) { -- cgit v1.2.1 From b738b60b75b108c5b1aa97b540c95997e1c7bbfd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:40 -0600 Subject: include/sha1.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I091ce4c5ae2deea1adfa584ed356101367ff34c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730403 Reviewed-by: Jeremy Bettis --- include/sha1.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/sha1.h b/include/sha1.h index 42c0f2612f..89fbbf0cd8 100644 --- a/include/sha1.h +++ b/include/sha1.h @@ -11,7 +11,7 @@ #include "common.h" #ifdef HOST_TOOLS_BUILD #include -#define DIV_ROUND_UP(x, y) (((x) + ((y) - 1)) / (y)) +#define DIV_ROUND_UP(x, y) (((x) + ((y)-1)) / (y)) #else #include "util.h" #endif @@ -33,4 +33,4 @@ void sha1_init(struct sha1_ctx *ctx); void sha1_update(struct sha1_ctx *ctx, const uint8_t *data, uint32_t len); uint8_t *sha1_final(struct sha1_ctx *ctx); -#endif /* __CROS_EC_SHA1_H */ +#endif /* __CROS_EC_SHA1_H */ -- cgit v1.2.1 From 26d05e43830ccfe6bdf0c33e4b639f40fba1c54a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:14 -0600 Subject: board/ampton/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I419db6ad79c852b3ffc2a04e16f0dcb05ec80934 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727984 Reviewed-by: Jeremy Bettis --- board/ampton/board.h | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/board/ampton/board.h b/board/ampton/board.h index d0a3cf5bc0..52ee8fa464 100644 --- a/board/ampton/board.h +++ b/board/ampton/board.h @@ -16,7 +16,7 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* I2C bus configuraiton */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* EC console commands */ #define CONFIG_CMD_ACCELS @@ -28,7 +28,7 @@ #define CONFIG_LED_COMMON -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 5000 /* Sensors */ #define CONFIG_TEMP_SENSOR @@ -38,11 +38,11 @@ #define CONFIG_TEMP_SENSOR_POWER #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300 -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_ICM42607 /* Base accel */ -#define CONFIG_SYNC /* Camera VSYNC */ +#define CONFIG_SYNC /* Camera VSYNC */ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Sensors without hardware FIFO are in forced mode */ @@ -57,8 +57,7 @@ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) /* Keyboard backlight is unimplemented in hardware */ #undef CONFIG_PWM @@ -90,13 +89,7 @@ enum temp_sensor_id { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - VSYNC, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, VSYNC, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From a9bb007f364fd25979d164cd3636fa7e77eae59a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:17 -0600 Subject: board/hoho/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide779e54af0322831ed91d3ff515adc762ae705c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728321 Reviewed-by: Jeremy Bettis --- board/hoho/board.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/hoho/board.c b/board/hoho/board.c index 07b772c826..e36f89a1b9 100644 --- a/board/hoho/board.c +++ b/board/hoho/board.c @@ -98,7 +98,7 @@ void board_config_pre_init(void) /* enable SYSCFG clock */ STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */ } #ifdef CONFIG_SPI_FLASH @@ -142,11 +142,10 @@ static void factory_validation_deferred(void) /* test mcdp via serial to validate function */ if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) && - (MCDP_CHIPID(info.chipid) == 0x2850)) { + (MCDP_CHIPID(info.chipid) == 0x2850)) { gpio_set_level(GPIO_MCDP_READY, 1); pd_log_event(PD_EVENT_VIDEO_CODEC, - PD_LOG_PORT_SIZE(0, sizeof(info)), - 0, &info); + PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info); } mcdp_disable(); @@ -167,7 +166,7 @@ static void board_init(void) gpio_set_level(GPIO_STM_READY, 1); /* factory test only */ /* Delay needed to allow HDMI MCU to boot. */ - hook_call_deferred(&factory_validation_deferred_data, 200*MSEC); + hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -175,11 +174,11 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)}, + [ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -const void * const usb_strings[] = { +const void *const usb_strings[] = { [USB_STR_DESC] = usb_string_desc, [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), [USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"), -- cgit v1.2.1 From 1c08a2a81f3dda04a8c8f0f9ef5746829290dd54 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:16 -0600 Subject: zephyr/projects/nissa/src/nivviks/usbc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I052a1d6313564d50b12fb24f84f4eef8de740f70 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730794 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nivviks/usbc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/nissa/src/nivviks/usbc.c b/zephyr/projects/nissa/src/nivviks/usbc.c index c068eba6f4..651a18c21c 100644 --- a/zephyr/projects/nissa/src/nivviks/usbc.c +++ b/zephyr/projects/nissa/src/nivviks/usbc.c @@ -54,8 +54,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -233,8 +232,7 @@ static void usbc_interrupt_trigger(int port) usb_charger_task_set_event(port, USB_CHG_EVENT_BC12); } -static inline void poll_usb_gpio(int port, - const struct gpio_dt_spec *gpio, +static inline void poll_usb_gpio(int port, const struct gpio_dt_spec *gpio, const struct deferred_data *ud) { if (!gpio_pin_get_dt(gpio)) { @@ -243,17 +241,15 @@ static inline void poll_usb_gpio(int port, } } -static void poll_c0_int (void) +static void poll_c0_int(void) { - poll_usb_gpio(0, - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), + poll_usb_gpio(0, GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl), &poll_c0_int_data); } -static void poll_c1_int (void) +static void poll_c1_int(void) { - poll_usb_gpio(1, - GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + poll_usb_gpio(1, GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), &poll_c1_int_data); } -- cgit v1.2.1 From 99511274de8f1fcd50b76e576a7b47fed2f79ce1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:12 -0600 Subject: board/jacuzzi/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7267a683de78a94e76fe121f15acc83aa9fa706b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728474 Reviewed-by: Jeremy Bettis --- board/jacuzzi/battery.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/jacuzzi/battery.c b/board/jacuzzi/battery.c index 443bf1e98a..d4a33f2cee 100644 --- a/board/jacuzzi/battery.c +++ b/board/jacuzzi/battery.c @@ -120,7 +120,8 @@ const struct board_batt_params board_battery_info[] = { }; BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); -const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC_AC16L5J_KT00205009; +const enum battery_type DEFAULT_BATTERY_TYPE = + BATTERY_PANASONIC_AC16L5J_KT00205009; enum battery_present battery_hw_present(void) { -- cgit v1.2.1 From ca2c12f6510319aded1661c029caf1bfd8bac30a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:59 -0600 Subject: board/redrix/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3c207841d3d9861e4d54e8a11bb5d752a02f22a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728858 Reviewed-by: Jeremy Bettis --- board/redrix/fans.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/redrix/fans.c b/board/redrix/fans.c index d464eeab67..1d736dff4d 100644 --- a/board/redrix/fans.c +++ b/board/redrix/fans.c @@ -30,14 +30,14 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; static const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_1, /* Use MFT id to control fan */ + .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN2, }; -- cgit v1.2.1 From d0091747750716c730bed37148e05910dba566f9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:37 -0600 Subject: board/npcx_evb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I689aa3856fcfd2d8a9316ba66d67bb6452f6d3fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728770 Reviewed-by: Jeremy Bettis --- board/npcx_evb/board.h | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/board/npcx_evb/board.h b/board/npcx_evb/board.h index 5a22435396..6c26d347eb 100644 --- a/board/npcx_evb/board.h +++ b/board/npcx_evb/board.h @@ -19,7 +19,7 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ #define CONFIG_SPI_FLASH_PORT 0 #define CONFIG_SPI_FLASH -#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ +#define CONFIG_FLASH_SIZE_BYTES 0x00800000 /* 8MB spi flash */ #define CONFIG_SPI_FLASH_REGS #define CONFIG_SPI_FLASH_W25Q64 #define CONFIG_I2C @@ -41,29 +41,24 @@ #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_I2CWEDGE -#define CONFIG_FANS 1 +#define CONFIG_FANS 1 /* Optional feature - used by nuvoton */ -#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 0 /* 0:GPIO10/11 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* Optional for testing */ -#undef CONFIG_PSTORE -#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#undef CONFIG_PSTORE +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ /* Single I2C port, where the EC is the master. */ -#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 -#define I2C_PORT_HOST 0 +#define I2C_PORT_MASTER NPCX_I2C_PORT0_0 +#define I2C_PORT_HOST 0 #ifndef __ASSEMBLER__ -enum adc_channel { - ADC_CH_0 = 0, - ADC_CH_1, - ADC_CH_2, - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_0 = 0, ADC_CH_1, ADC_CH_2, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_FAN, -- cgit v1.2.1 From 0662fa9dfd965670aea486ad141d8b8fa75bb0dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:56 -0600 Subject: board/nipperkin/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5fc0a2fe1989123f284a87430abedd3ee224609 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728754 Reviewed-by: Jeremy Bettis --- board/nipperkin/led.c | 72 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 42 insertions(+), 30 deletions(-) diff --git a/board/nipperkin/led.c b/board/nipperkin/led.c index 93131400d2..a61a710579 100644 --- a/board/nipperkin/led.c +++ b/board/nipperkin/led.c @@ -35,22 +35,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LED_LEFT_PORT = 0, - LED_RIGHT_PORT -}; +enum led_port { LED_LEFT_PORT = 0, LED_RIGHT_PORT }; static void led_set_color_battery(enum led_port port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_AMBER_L : - GPIO_C1_CHARGE_LED_AMBER_L); + GPIO_C1_CHARGE_LED_AMBER_L); white_led = (port == LED_LEFT_PORT ? GPIO_C0_CHARGE_LED_WHITE_L : - GPIO_C1_CHARGE_LED_WHITE_L); + GPIO_C1_CHARGE_LED_WHITE_L); switch (color) { case LED_WHITE: @@ -121,11 +118,13 @@ static void set_active_port_color(enum led_color color) int port = charge_manager_get_active_charge_port(); if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) - led_set_color_battery(LED_RIGHT_PORT, - (port == LED_RIGHT_PORT) ? color : LED_OFF); + led_set_color_battery(LED_RIGHT_PORT, (port == LED_RIGHT_PORT) ? + color : + LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) - led_set_color_battery(LED_LEFT_PORT, - (port == LED_LEFT_PORT) ? color : LED_OFF); + led_set_color_battery(LED_LEFT_PORT, (port == LED_LEFT_PORT) ? + color : + LED_OFF); } static void led_set_battery(void) @@ -142,16 +141,19 @@ static void led_set_battery(void) * system suspend with non-charging state. */ if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; - led_set_color_battery(LED_RIGHT_PORT, power_ticks - % LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS - ? LED_WHITE : LED_OFF); - led_set_color_battery(LED_LEFT_PORT, power_ticks - % LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS - ? LED_WHITE : LED_OFF); + led_set_color_battery(LED_RIGHT_PORT, + power_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); + led_set_color_battery(LED_LEFT_PORT, + power_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); return; } @@ -165,30 +167,38 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(LED_RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + LED_RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(LED_RIGHT_PORT, LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(LED_LEFT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery( + LED_LEFT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else led_set_color_battery(LED_LEFT_PORT, LED_OFF); } break; case PWR_STATE_ERROR: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { - led_set_color_battery(LED_RIGHT_PORT, + led_set_color_battery( + LED_RIGHT_PORT, (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); } if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { - led_set_color_battery(LED_LEFT_PORT, + led_set_color_battery( + LED_LEFT_PORT, (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); } break; @@ -198,9 +208,11 @@ static void led_set_battery(void) break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From 171376679b63536b1748816cbcf6ca9a11f200c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:27 -0600 Subject: chip/ish/uart_defs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie73dff77c3803f1b7dae800b8629557d94822815 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729164 Reviewed-by: Jeremy Bettis --- chip/ish/uart_defs.h | 391 +++++++++++++++++++++++++-------------------------- 1 file changed, 189 insertions(+), 202 deletions(-) diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index 5bfc7b9a6b..2953f80b09 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -12,344 +12,331 @@ #include #include "atomic.h" -#define UART_ERROR -1 -#define UART_BUSY -2 +#define UART_ERROR -1 +#define UART_BUSY -2 #ifdef CHIP_VARIANT_ISH5P4 -#define UART0_OFFS (0x00) -#define UART1_OFFS (0x2000) -#define UART2_OFFS (0x4000) +#define UART0_OFFS (0x00) +#define UART1_OFFS (0x2000) +#define UART2_OFFS (0x4000) #else -#define UART0_OFFS (0x80) -#define UART1_OFFS (0x100) -#define UART2_OFFS (0x180) +#define UART0_OFFS (0x80) +#define UART1_OFFS (0x100) +#define UART2_OFFS (0x180) #endif -#define HSU_BASE ISH_UART_BASE -#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) -#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) -#define UART2_BASE (ISH_UART_BASE + UART2_OFFS) +#define HSU_BASE ISH_UART_BASE +#define UART0_BASE (ISH_UART_BASE + UART0_OFFS) +#define UART1_BASE (ISH_UART_BASE + UART1_OFFS) +#define UART2_BASE (ISH_UART_BASE + UART2_OFFS) -#define UART_REG(size, name, n) \ - REG##size(uart_ctx[n].base + \ +#define UART_REG(size, name, n) \ + REG##size(uart_ctx[n].base + \ UART_OFFSET_##name * uart_ctx[n].addr_interval) /* Register accesses */ -#define LSR(n) UART_REG(8, LSR, n) -#define THR(n) UART_REG(8, THR, n) -#define RBR(n) UART_REG(8, RBR, n) -#define DLL(n) UART_REG(8, DLL, n) -#define DLH(n) UART_REG(8, DLH, n) -#define IER(n) UART_REG(8, IER, n) -#define IIR(n) UART_REG(8, IIR, n) -#define FCR(n) UART_REG(8, FCR, n) -#define LCR(n) UART_REG(8, LCR, n) -#define MCR(n) UART_REG(8, MCR, n) -#define MSR(n) UART_REG(8, MSR, n) -#define DLF(n) UART_REG(8, DLF, n) -#define FOR(n) UART_REG(32, FOR, n) -#define ABR(n) UART_REG(32, ABR, n) -#define PS(n) UART_REG(32, PS, n) -#define MUL(n) UART_REG(32, MUL, n) -#define DIV(n) UART_REG(32, DIV, n) +#define LSR(n) UART_REG(8, LSR, n) +#define THR(n) UART_REG(8, THR, n) +#define RBR(n) UART_REG(8, RBR, n) +#define DLL(n) UART_REG(8, DLL, n) +#define DLH(n) UART_REG(8, DLH, n) +#define IER(n) UART_REG(8, IER, n) +#define IIR(n) UART_REG(8, IIR, n) +#define FCR(n) UART_REG(8, FCR, n) +#define LCR(n) UART_REG(8, LCR, n) +#define MCR(n) UART_REG(8, MCR, n) +#define MSR(n) UART_REG(8, MSR, n) +#define DLF(n) UART_REG(8, DLF, n) +#define FOR(n) UART_REG(32, FOR, n) +#define ABR(n) UART_REG(32, ABR, n) +#define PS(n) UART_REG(32, PS, n) +#define MUL(n) UART_REG(32, MUL, n) +#define DIV(n) UART_REG(32, DIV, n) #ifdef CONFIG_ISH_DW_UART /* * RBR: Receive Buffer register (BLAB bit = 0) */ -#define UART_OFFSET_RBR (0x00) +#define UART_OFFSET_RBR (0x00) /* * THR: Transmit Holding register (BLAB bit = 0) */ -#define UART_OFFSET_THR (0x00) +#define UART_OFFSET_THR (0x00) /* * DLL: Divisor Latch Reg. low byte (BLAB bit = 1) * baud rate = (serial clock freq) / (16 * divisor) */ -#define UART_OFFSET_DLL (0x00) +#define UART_OFFSET_DLL (0x00) /* * DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ -#define UART_OFFSET_DLH (0x04) +#define UART_OFFSET_DLH (0x04) /* * IER: Interrupt Enable register (BLAB bit = 0) */ -#define UART_OFFSET_IER (0x04) +#define UART_OFFSET_IER (0x04) -#define IER_RECV (0x01) /* Receive Data Available */ -#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ -#define IER_LINE_STAT (0x04) /* Receiver Line Status */ -#define IER_MODEM (0x08) /* Modem Status */ -#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ +#define IER_RECV (0x01) /* Receive Data Available */ +#define IER_TDRQ (0x02) /* Transmit Holding Register Empty */ +#define IER_LINE_STAT (0x04) /* Receiver Line Status */ +#define IER_MODEM (0x08) /* Modem Status */ +#define IER_PTIME (0x80) /* Programmable THRE Interrupt Mode Enable */ /* * IIR: Interrupt ID register */ -#define UART_OFFSET_IIR (0x08) - -#define IIR_MODEM (0x00) /* Prio: 4 */ -#define IIR_NO_INTR (0x01) -#define IIR_THRE (0x02) /* Prio: 3 */ -#define IIR_RECV_DATA (0x04) /* Prio: 2 */ -#define IIR_LINE_STAT (0x06) /* Prio: 1 */ -#define IIR_BUSY (0x07) /* Prio: 5 */ -#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ -#define IIR_SOURCE (0x0F) +#define UART_OFFSET_IIR (0x08) +#define IIR_MODEM (0x00) /* Prio: 4 */ +#define IIR_NO_INTR (0x01) +#define IIR_THRE (0x02) /* Prio: 3 */ +#define IIR_RECV_DATA (0x04) /* Prio: 2 */ +#define IIR_LINE_STAT (0x06) /* Prio: 1 */ +#define IIR_BUSY (0x07) /* Prio: 5 */ +#define IIR_TIME_OUT (0x0C) /* Prio: 2 */ +#define IIR_SOURCE (0x0F) /* * FCR: FIFO Control register (FIFO_MODE != NONE) */ -#define UART_OFFSET_FCR (0x08) +#define UART_OFFSET_FCR (0x08) -#define FIFO_SIZE 64 -#define FCR_FIFO_ENABLE (0x01) -#define FCR_RESET_RX (0x02) -#define FCR_RESET_TX (0x04) -#define FCR_DMA_MODE (0x08) +#define FIFO_SIZE 64 +#define FCR_FIFO_ENABLE (0x01) +#define FCR_RESET_RX (0x02) +#define FCR_RESET_TX (0x04) +#define FCR_DMA_MODE (0x08) /* * LCR: Line Control register */ -#define UART_OFFSET_LCR (0x0c) +#define UART_OFFSET_LCR (0x0c) -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) +#define LCR_5BIT_CHR (0x00) +#define LCR_6BIT_CHR (0x01) +#define LCR_7BIT_CHR (0x02) +#define LCR_8BIT_CHR (0x03) +#define LCR_BIT_CHR_MASK (0x03) -#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ -#define LCR_PEN BIT(3) /* Parity Enable */ -#define LCR_EPS BIT(4) /* Even Parity Select */ -#define LCR_SP BIT(5) /* Stick Parity */ -#define LCR_BC BIT(6) /* Break Control */ -#define LCR_DLAB BIT(7) /* Divisor Latch Access */ +#define LCR_STOP BIT(2) /* 0: 1 stop bit, 1: 1.5/2 */ +#define LCR_PEN BIT(3) /* Parity Enable */ +#define LCR_EPS BIT(4) /* Even Parity Select */ +#define LCR_SP BIT(5) /* Stick Parity */ +#define LCR_BC BIT(6) /* Break Control */ +#define LCR_DLAB BIT(7) /* Divisor Latch Access */ /* * MCR: Modem Control register */ -#define UART_OFFSET_MCR (0x10) -#define MCR_DTR (0x1) /* Data terminal ready */ -#define MCR_RTS (0x2) /* Request to send */ -#define MCR_LOOP (0x10) /* LoopBack bit*/ +#define UART_OFFSET_MCR (0x10) +#define MCR_DTR (0x1) /* Data terminal ready */ +#define MCR_RTS (0x2) /* Request to send */ +#define MCR_LOOP (0x10) /* LoopBack bit*/ -#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ -#define MCR_AUTO_FLOW_EN (0x20) +#define MCR_INTR_ENABLE (0x08) /* User-designated OUT2 */ +#define MCR_AUTO_FLOW_EN (0x20) /* * LSR: Line Status register */ -#define UART_OFFSET_LSR (0x14) +#define UART_OFFSET_LSR (0x14) -#define LSR_DR (0x01) /* Data Ready */ -#define LSR_OE (0x02) /* Overrun error */ -#define LSR_PE (0x04) /* Parity error */ -#define LSR_FE (0x08) /* Framing error */ -#define LSR_BI (0x10) /* Breaking interrupt */ -#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ -#define LSR_TEMT (0x40) /* Transmitter empty */ +#define LSR_DR (0x01) /* Data Ready */ +#define LSR_OE (0x02) /* Overrun error */ +#define LSR_PE (0x04) /* Parity error */ +#define LSR_FE (0x08) /* Framing error */ +#define LSR_BI (0x10) /* Breaking interrupt */ +#define LSR_TDRQ (0x20) /* Transmit Holding Register Empty */ +#define LSR_TEMT (0x40) /* Transmitter empty */ /* * MSR: Modem Status register */ -#define UART_OFFSET_MSR (0x18) +#define UART_OFFSET_MSR (0x18) -#define MSR_CTS BIT(4) /* Clear To Send signal */ +#define MSR_CTS BIT(4) /* Clear To Send signal */ /* * TFL: Transmit FIFO Level */ -#define UART_OFFSET_TFL (0x80) +#define UART_OFFSET_TFL (0x80) /* * RFL: Receive FIFO Level */ -#define UART_OFFSET_RFL (0x84) +#define UART_OFFSET_RFL (0x84) #else /* RBR: Receive Buffer register (BLAB bit = 0) */ -#define UART_OFFSET_RBR (0) +#define UART_OFFSET_RBR (0) /* THR: Transmit Holding register (BLAB bit = 0) */ -#define UART_OFFSET_THR (0) +#define UART_OFFSET_THR (0) /* IER: Interrupt Enable register (BLAB bit = 0) */ -#define UART_OFFSET_IER (1) +#define UART_OFFSET_IER (1) /* FCR: FIFO Control register */ -#define UART_OFFSET_FCR (2) -#define FCR_FIFO_ENABLE BIT(0) -#define FCR_RESET_RX BIT(1) -#define FCR_RESET_TX BIT(2) +#define UART_OFFSET_FCR (2) +#define FCR_FIFO_ENABLE BIT(0) +#define FCR_RESET_RX BIT(1) +#define FCR_RESET_TX BIT(2) /* LCR: Line Control register */ -#define UART_OFFSET_LCR (3) -#define LCR_DLAB (0x80) -#define LCR_5BIT_CHR (0x00) -#define LCR_6BIT_CHR (0x01) -#define LCR_7BIT_CHR (0x02) -#define LCR_8BIT_CHR (0x03) -#define LCR_BIT_CHR_MASK (0x03) -#define LCR_SB (0x40) /* Set Break */ +#define UART_OFFSET_LCR (3) +#define LCR_DLAB (0x80) +#define LCR_5BIT_CHR (0x00) +#define LCR_6BIT_CHR (0x01) +#define LCR_7BIT_CHR (0x02) +#define LCR_8BIT_CHR (0x03) +#define LCR_BIT_CHR_MASK (0x03) +#define LCR_SB (0x40) /* Set Break */ /* MCR: Modem Control register */ -#define UART_OFFSET_MCR (4) -#define MCR_DTR BIT(0) -#define MCR_RTS BIT(1) -#define MCR_LOO BIT(4) -#define MCR_INTR_ENABLE BIT(3) -#define MCR_AUTO_FLOW_EN BIT(5) +#define UART_OFFSET_MCR (4) +#define MCR_DTR BIT(0) +#define MCR_RTS BIT(1) +#define MCR_LOO BIT(4) +#define MCR_INTR_ENABLE BIT(3) +#define MCR_AUTO_FLOW_EN BIT(5) /* LSR: Line Status register */ -#define UART_OFFSET_LSR (5) -#define LSR_DR BIT(0) /* Data Ready */ -#define LSR_OE BIT(1) /* Overrun error */ -#define LSR_PE BIT(2) /* Parity error */ -#define LSR_FE BIT(3) /* Framing error */ -#define LSR_BI BIT(4) /* Breaking interrupt */ -#define LSR_THR_EMPTY BIT(5) /* Non FIFO mode: Transmit holding - * register empty - */ -#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */ -#define LSR_TEMT BIT(6) /* Transmitter empty */ +#define UART_OFFSET_LSR (5) +#define LSR_DR BIT(0) /* Data Ready */ +#define LSR_OE BIT(1) /* Overrun error */ +#define LSR_PE BIT(2) /* Parity error */ +#define LSR_FE BIT(3) /* Framing error */ +#define LSR_BI BIT(4) /* Breaking interrupt */ +#define LSR_THR_EMPTY \ + BIT(5) /* Non FIFO mode: Transmit holding \ + * register empty \ + */ +#define LSR_TDRQ BIT(5) /* FIFO mode: Transmit Data request */ +#define LSR_TEMT BIT(6) /* Transmitter empty */ #define FCR_ITL_FIFO_64_BYTES_56 (BIT(6) | BIT(7)) -#define IER_RECV BIT(0) -#define IER_TDRQ BIT(1) -#define IER_LINE_STAT BIT(2) +#define IER_RECV BIT(0) +#define IER_TDRQ BIT(1) +#define IER_LINE_STAT BIT(2) -#define UART_OFFSET_IIR (2) +#define UART_OFFSET_IIR (2) /* MSR: Modem Status register */ -#define UART_OFFSET_MSR (6) +#define UART_OFFSET_MSR (6) /* DLL: Divisor Latch Reg. low byte (BLAB bit = 1) */ -#define UART_OFFSET_DLL (0) +#define UART_OFFSET_DLL (0) /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */ -#define UART_OFFSET_DLH (1) +#define UART_OFFSET_DLH (1) #endif /* * DLF: Divisor Latch Fraction Register */ -#define UART_OFFSET_DLF (0xC0) +#define UART_OFFSET_DLF (0xC0) /* FOR: Fifo O Register (ISH only) */ -#define UART_OFFSET_FOR (0x20) -#define FOR_OCCUPANCY_OFFS 0 -#define FOR_OCCUPANCY_MASK 0x7F +#define UART_OFFSET_FOR (0x20) +#define FOR_OCCUPANCY_OFFS 0 +#define FOR_OCCUPANCY_MASK 0x7F /* ABR: Auto-Baud Control Register (ISH only) */ -#define UART_OFFSET_ABR (0x24) -#define ABR_UUE BIT(4) +#define UART_OFFSET_ABR (0x24) +#define ABR_UUE BIT(4) /* Pre-Scalar Register (ISH only) */ -#define UART_OFFSET_PS (0x30) +#define UART_OFFSET_PS (0x30) /* DDS registers (ISH only) */ -#define UART_OFFSET_MUL (0x34) -#define UART_OFFSET_DIV (0x38) +#define UART_OFFSET_MUL (0x34) +#define UART_OFFSET_DIV (0x38) -#define FCR_FIFO_SIZE_16 (0x00) -#define FCR_FIFO_SIZE_64 (0x20) -#define FCR_ITL_FIFO_64_BYTES_1 (0x00) +#define FCR_FIFO_SIZE_16 (0x00) +#define FCR_FIFO_SIZE_64 (0x20) +#define FCR_ITL_FIFO_64_BYTES_1 (0x00) /* tx empty trigger(TET) */ -#define FCR_TET_EMPTY (0x00) -#define FCR_TET_2CHAR (0x10) -#define FCR_TET_QTR_FULL (0x20) -#define FCR_TET_HALF_FULL (0x30) +#define FCR_TET_EMPTY (0x00) +#define FCR_TET_2CHAR (0x10) +#define FCR_TET_QTR_FULL (0x20) +#define FCR_TET_HALF_FULL (0x30) /* receive trigger(RT) */ -#define FCR_RT_1CHAR (0x00) -#define FCR_RT_QTR_FULL (0x40) -#define FCR_RT_HALF_FULL (0x80) -#define FCR_RT_2LESS_FULL (0xc0) +#define FCR_RT_1CHAR (0x00) +#define FCR_RT_QTR_FULL (0x40) +#define FCR_RT_HALF_FULL (0x80) +#define FCR_RT_2LESS_FULL (0xc0) /* G_IEN: Global Interrupt Enable (ISH only) */ -#define HSU_REG_GIEN REG32(HSU_BASE + 0x0) -#define HSU_REG_GIST REG32(HSU_BASE + 0x4) - -#define GIEN_PWR_MGMT BIT(24) -#define GIEN_DMA_EN BIT(5) -#define GIEN_UART2_EN BIT(2) -#define GIEN_UART1_EN BIT(1) -#define GIEN_UART0_EN BIT(0) -#define GIST_DMA_EN BIT(5) -#define GIST_UART2_EN BIT(2) -#define GIST_UART1_EN BIT(1) -#define GIST_UART0_EN BIT(0) -#define GIST_UARTx_EN (GIST_UART0_EN|GIST_UART1_EN|GIST_UART2_EN) +#define HSU_REG_GIEN REG32(HSU_BASE + 0x0) +#define HSU_REG_GIST REG32(HSU_BASE + 0x4) + +#define GIEN_PWR_MGMT BIT(24) +#define GIEN_DMA_EN BIT(5) +#define GIEN_UART2_EN BIT(2) +#define GIEN_UART1_EN BIT(1) +#define GIEN_UART0_EN BIT(0) +#define GIST_DMA_EN BIT(5) +#define GIST_UART2_EN BIT(2) +#define GIST_UART1_EN BIT(1) +#define GIST_UART0_EN BIT(0) +#define GIST_UARTx_EN (GIST_UART0_EN | GIST_UART1_EN | GIST_UART2_EN) /* UART config flag, send to sc_io_control if the current UART line has HW * flow control lines connected. */ -#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) +#define UART_CONFIG_HW_FLOW_CONTROL BIT(0) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_msg is * raised only when the rx buffer is completely full. Otherwise, the event * is raised after a timeout is received on the UART line, * and all data received until now is provided. */ -#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) +#define UART_CONFIG_DELIVER_FULL_RX_BUF BIT(1) /* UART config flag for sc_io_control. If defined a sc_io_event_rx_buf_depleted * is raised when all rx buffers that were added are full. Otherwise, no * event is raised. */ -#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) - -#define UART_INT_DEVICES 3 -#define UART_EXT_DEVICES 8 -#define UART_DEVICES UART_INT_DEVICES -#define UART_ISH_ADDR_INTERVAL 1 - -#define B9600 0x0000d -#define B57600 0x00000018 -#define B115200 0x00000011 -#define B921600 0x00000012 -#define B2000000 0x00000013 -#define B3000000 0x00000014 -#define B3250000 0x00000015 -#define B3500000 0x00000016 -#define B4000000 0x00000017 -#define B19200 0x0000e -#define B38400 0x0000f +#define UART_CONFIG_ANNOUNCE_DEPLETED_BUF BIT(2) + +#define UART_INT_DEVICES 3 +#define UART_EXT_DEVICES 8 +#define UART_DEVICES UART_INT_DEVICES +#define UART_ISH_ADDR_INTERVAL 1 + +#define B9600 0x0000d +#define B57600 0x00000018 +#define B115200 0x00000011 +#define B921600 0x00000012 +#define B2000000 0x00000013 +#define B3000000 0x00000014 +#define B3250000 0x00000015 +#define B3500000 0x00000016 +#define B4000000 0x00000017 +#define B19200 0x0000e +#define B38400 0x0000f /* KHZ, MHZ */ -#define KHZ(x) ((x) * 1000) -#define MHZ(x) (KHZ(x) * 1000) +#define KHZ(x) ((x)*1000) +#define MHZ(x) (KHZ(x) * 1000) #if defined(CHIP_VARIANT_ISH5P4) /* Change to 100MHZ in real silicon platform */ -#define UART_ISH_INPUT_FREQ MHZ(100) +#define UART_ISH_INPUT_FREQ MHZ(100) #elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5) -#define UART_ISH_INPUT_FREQ MHZ(120) +#define UART_ISH_INPUT_FREQ MHZ(120) #elif defined(CHIP_FAMILY_ISH4) -#define UART_ISH_INPUT_FREQ MHZ(100) +#define UART_ISH_INPUT_FREQ MHZ(100) #endif -#define UART_DEFAULT_BAUD_RATE 115200 -#define UART_STATE_CG BIT(UART_OP_CG) +#define UART_DEFAULT_BAUD_RATE 115200 +#define UART_STATE_CG BIT(UART_OP_CG) -enum UART_PORT { - UART_PORT_0, - UART_PORT_1, - UART_PORT_MAX -}; +enum UART_PORT { UART_PORT_0, UART_PORT_1, UART_PORT_MAX }; -enum UART_OP { - UART_OP_READ, - UART_OP_WRITE, - UART_OP_CG, - UART_OP_MAX -}; +enum UART_OP { UART_OP_READ, UART_OP_WRITE, UART_OP_CG, UART_OP_MAX }; -enum { - BAUD_IDX, - BAUD_SPEED, - BAUD_TABLE_MAX -}; +enum { BAUD_IDX, BAUD_SPEED, BAUD_TABLE_MAX }; struct uart_ctx { uint32_t id; -- cgit v1.2.1 From 30cb66770972be44c635f8b78e1a3a9d18ad629e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:51 -0600 Subject: util/ec_panicinfo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I74f1ff82c03b0df19e45c4b4b7b5deddd6f5b39b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730612 Reviewed-by: Jeremy Bettis --- util/ec_panicinfo.c | 78 +++++++++++++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/util/ec_panicinfo.c b/util/ec_panicinfo.c index 0294ac90de..4ad24ff0f3 100644 --- a/util/ec_panicinfo.c +++ b/util/ec_panicinfo.c @@ -12,11 +12,10 @@ static void print_panic_reg(int regnum, const uint32_t *regs, int index) { - static const char * const regname[] = { - "r0 ", "r1 ", "r2 ", "r3 ", "r4 ", - "r5 ", "r6 ", "r7 ", "r8 ", "r9 ", - "r10", "r11", "r12", "sp ", "lr ", - "pc "}; + static const char *const regname[] = { "r0 ", "r1 ", "r2 ", "r3 ", + "r4 ", "r5 ", "r6 ", "r7 ", + "r8 ", "r9 ", "r10", "r11", + "r12", "sp ", "lr ", "pc " }; printf("%s:", regname[regnum]); if (regs) @@ -56,14 +55,15 @@ static int parse_panic_info_cm(const struct panic_data *pdata) ORIG_HANDLER } origin = ORIG_UNKNOWN; int i; - const char *panic_origins[3] = {"", "PROCESS", "HANDLER"}; + const char *panic_origins[3] = { "", "PROCESS", "HANDLER" }; printf("Saved panic data:%s\n", (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)")); if (pdata->struct_version == 2) origin = ((lregs[11] & 0xf) == 1 || (lregs[11] & 0xf) == 9) ? - ORIG_HANDLER : ORIG_PROCESS; + ORIG_HANDLER : + ORIG_PROCESS; /* * In pdata struct, 'regs', which is allocated before 'frame', has @@ -75,8 +75,7 @@ static int parse_panic_info_cm(const struct panic_data *pdata) sregs = pdata->cm.frame - (pdata->struct_version == 1 ? 1 : 0); printf("=== %s EXCEPTION: %02x ====== xPSR: %08x ===\n", - panic_origins[origin], - lregs[1] & 0xff, sregs ? sregs[7] : -1); + panic_origins[origin], lregs[1] & 0xff, sregs ? sregs[7] : -1); for (i = 0; i < 4; ++i) print_panic_reg(i, sregs, i); for (i = 4; i < 10; ++i) @@ -104,14 +103,14 @@ static int parse_panic_info_nds32(const struct panic_data *pdata) (pdata->flags & PANIC_DATA_FLAG_OLD_HOSTCMD ? "" : " (NEW)")); printf("=== EXCEP: ITYPE=%x ===\n", itype); - printf("R0 %08x R1 %08x R2 %08x R3 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - printf("R4 %08x R5 %08x R6 %08x R7 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - printf("R8 %08x R9 %08x R10 %08x R15 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - printf("FP %08x GP %08x LP %08x SP %08x\n", - regs[12], regs[13], regs[14], regs[15]); + printf("R0 %08x R1 %08x R2 %08x R3 %08x\n", regs[0], regs[1], + regs[2], regs[3]); + printf("R4 %08x R5 %08x R6 %08x R7 %08x\n", regs[4], regs[5], + regs[6], regs[7]); + printf("R8 %08x R9 %08x R10 %08x R15 %08x\n", regs[8], regs[9], + regs[10], regs[11]); + printf("FP %08x GP %08x LP %08x SP %08x\n", regs[12], regs[13], + regs[14], regs[15]); printf("IPC %08x IPSW %05x\n", ipc, ipsw); printf("SWID of ITYPE: %x\n", ((itype >> 16) & 0x7fff)); @@ -127,22 +126,22 @@ static int parse_panic_info_rv32i(const struct panic_data *pdata) mepc = pdata->riscv.mepc; printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause); - printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", - regs[12], regs[13], regs[14], regs[15]); - printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", - regs[16], regs[17], regs[18], regs[19]); - printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", - regs[20], regs[21], regs[22], regs[23]); - printf("A2 %08x A1 %08x A0 %08x TP %08x\n", - regs[24], regs[25], regs[26], regs[27]); - printf("GP %08x RA %08x SP %08x MEPC %08x\n", - regs[28], regs[29], regs[30], mepc); + printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", regs[0], regs[1], + regs[2], regs[3]); + printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", regs[4], regs[5], + regs[6], regs[7]); + printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", regs[8], regs[9], + regs[10], regs[11]); + printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", regs[12], regs[13], + regs[14], regs[15]); + printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", regs[16], regs[17], + regs[18], regs[19]); + printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", regs[20], regs[21], + regs[22], regs[23]); + printf("A2 %08x A1 %08x A0 %08x TP %08x\n", regs[24], regs[25], + regs[26], regs[27]); + printf("GP %08x RA %08x SP %08x MEPC %08x\n", regs[28], regs[29], + regs[30], mepc); return 0; } @@ -153,7 +152,7 @@ int parse_panic_info(const char *data, size_t size) const size_t header_size = 4; /* Size of the panic information "trailer" (struct_size and magic). */ const size_t trailer_size = sizeof(struct panic_data) - - offsetof(struct panic_data, struct_size); + offsetof(struct panic_data, struct_size); struct panic_data pdata = { 0 }; size_t copy_size; @@ -164,7 +163,8 @@ int parse_panic_info(const char *data, size_t size) } if (size > sizeof(pdata)) { - fprintf(stderr, "WARNING: Panic data too large (%zd > %zd). " + fprintf(stderr, + "WARNING: Panic data too large (%zd > %zd). " "Following data may be incorrect!\n", size, sizeof(pdata)); copy_size = sizeof(pdata); @@ -175,20 +175,22 @@ int parse_panic_info(const char *data, size_t size) memcpy(&pdata, data, copy_size); /* Then copy the trailer in position. */ memcpy((char *)&pdata + (sizeof(struct panic_data) - trailer_size), - data + (size - trailer_size), trailer_size); + data + (size - trailer_size), trailer_size); /* * We only understand panic data with version <= 2. Warn the user * of higher versions. */ if (pdata.struct_version > 2) - fprintf(stderr, "WARNING: Unknown panic data version (%d). " + fprintf(stderr, + "WARNING: Unknown panic data version (%d). " "Following data may be incorrect!\n", pdata.struct_version); /* Validate magic number */ if (pdata.magic != PANIC_DATA_MAGIC) - fprintf(stderr, "WARNING: Incorrect panic magic (%d). " + fprintf(stderr, + "WARNING: Incorrect panic magic (%d). " "Following data may be incorrect!\n", pdata.magic); -- cgit v1.2.1 From 2478f4ca182573080611a2ef6ba7b6064c75d0b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:11 -0600 Subject: include/acpi.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I817e0588747ddc78a286cfa0fd1caf648a21448a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730199 Reviewed-by: Jeremy Bettis --- include/acpi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/acpi.h b/include/acpi.h index 56930c4b2d..d51abd4ed6 100644 --- a/include/acpi.h +++ b/include/acpi.h @@ -74,4 +74,4 @@ int acpi_dptf_set_profile_num(int n); */ int acpi_dptf_get_profile_num(void); -#endif /* __CROS_EC_ACPI_H */ +#endif /* __CROS_EC_ACPI_H */ -- cgit v1.2.1 From d4a508a198a26a5664f58c974da9e4a9a7fa2a05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:59 -0600 Subject: board/volmar/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e80cfa459c543534ab05287e3a5010fa5cdf41a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729076 Reviewed-by: Jeremy Bettis --- board/volmar/fw_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/volmar/fw_config.h b/board/volmar/fw_config.h index ba8c807a66..c5a3ed3d9b 100644 --- a/board/volmar/fw_config.h +++ b/board/volmar/fw_config.h @@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type { union volmar_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t boot_nvme_mask : 1; - uint32_t boot_emmc_mask : 1; - uint32_t reserved_1 : 22; + enum ec_cfg_usb_db_type usb_db : 4; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t boot_nvme_mask : 1; + uint32_t boot_emmc_mask : 1; + uint32_t reserved_1 : 22; }; uint32_t raw_value; }; -- cgit v1.2.1 From d934af2e4bc2e3cac8e8728b9d8340f733fd48af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:13 -0600 Subject: board/nami/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic15d40c5f3d63e40c0f9d79c34c65f4c0dd672a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728717 Reviewed-by: Jeremy Bettis --- board/nami/board.c | 215 ++++++++++++++++++++++++----------------------------- 1 file changed, 97 insertions(+), 118 deletions(-) diff --git a/board/nami/board.c b/board/nami/board.c index 20882cff13..29e9913ada 100644 --- a/board/nami/board.c +++ b/board/nami/board.c @@ -65,11 +65,11 @@ #include "fan.h" #include "fan_chip.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_PS8751 0 -#define USB_PD_PORT_ANX7447 1 +#define USB_PD_PORT_PS8751 0 +#define USB_PD_PORT_ANX7447 1 uint16_t board_version; uint8_t oem = PROJECT_NAMI; @@ -82,17 +82,16 @@ uint8_t model; * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); static void tcpc_alert_event(enum gpio_signal signal) { @@ -151,13 +150,14 @@ void usb1_evt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { /* Vbus sensing (10x voltage divider). PPVAR_BOOSTIN_SENSE */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18, - ADC_READ_MAX+1, 0}, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -166,7 +166,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -212,54 +212,42 @@ struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "tcpc1", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "battery", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "charger", - .port = NPCX_I2C_PORT2, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "pmic", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "accelgyro", - .port = NPCX_I2C_PORT3, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "tcpc1", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "battery", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "charger", + .port = NPCX_I2C_PORT2, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "pmic", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "accelgyro", + .port = NPCX_I2C_PORT3, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -333,7 +321,6 @@ void board_reset_pd_mcu(void) if (oem == PROJECT_AKALI && board_version < 0x0200) { if (anx7447_flash_erase(USB_PD_PORT_ANX7447)) CPRINTS("Failed to erase OCM flash"); - } /* Assert reset */ @@ -366,7 +353,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 2); @@ -391,12 +378,12 @@ uint16_t tcpc_get_alert_status(void) * F75303_Remote1 is near CPU, and F75303_Remote2 is near 5V power IC. */ const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = { - {"F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val, - F75303_IDX_LOCAL}, - {"F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val, - F75303_IDX_REMOTE1}, - {"F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val, - F75303_IDX_REMOTE2}, + { "F75303_Local", TEMP_SENSOR_TYPE_BOARD, f75303_get_val, + F75303_IDX_LOCAL }, + { "F75303_Remote1", TEMP_SENSOR_TYPE_CPU, f75303_get_val, + F75303_IDX_REMOTE1 }, + { "F75303_Remote2", TEMP_SENSOR_TYPE_BOARD, f75303_get_val, + F75303_IDX_REMOTE2 }, }; struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT]; @@ -405,8 +392,8 @@ struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT]; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ @@ -426,8 +413,8 @@ __maybe_unused static const struct ec_thermal_config thermal_a = THERMAL_A; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B1 \ - { \ +#define THERMAL_B1 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(82), \ @@ -447,8 +434,8 @@ __maybe_unused static const struct ec_thermal_config thermal_b1 = THERMAL_B1; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_B2 \ - { \ +#define THERMAL_B2 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(84), \ @@ -468,8 +455,8 @@ __maybe_unused static const struct ec_thermal_config thermal_b2 = THERMAL_B2; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_C1 \ - { \ +#define THERMAL_C1 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(66), \ @@ -489,8 +476,8 @@ __maybe_unused static const struct ec_thermal_config thermal_c1 = THERMAL_C1; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_C2 \ - { \ +#define THERMAL_C2 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(74), \ @@ -510,8 +497,8 @@ __maybe_unused static const struct ec_thermal_config thermal_c2 = THERMAL_C2; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_D0 \ - { \ +#define THERMAL_D0 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(79), \ [EC_TEMP_THRESH_HIGH] = 0, \ @@ -531,8 +518,8 @@ __maybe_unused static const struct ec_thermal_config thermal_d0 = THERMAL_D0; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_D1 \ - { \ +#define THERMAL_D1 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(59), \ [EC_TEMP_THRESH_HIGH] = 0, \ @@ -552,8 +539,8 @@ __maybe_unused static const struct ec_thermal_config thermal_d1 = THERMAL_D1; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_D2 \ - { \ +#define THERMAL_D2 \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = C_TO_K(59), \ [EC_TEMP_THRESH_HIGH] = 0, \ @@ -570,11 +557,9 @@ __maybe_unused static const struct ec_thermal_config thermal_d1 = THERMAL_D1; __maybe_unused static const struct ec_thermal_config thermal_d2 = THERMAL_D2; #define I2C_PMIC_READ(reg, data) \ - i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\ - (reg), (data)) + i2c_read8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data)) #define I2C_PMIC_WRITE(reg, data) \ - i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS,\ - (reg), (data)) + i2c_write8(I2C_PORT_PMIC, TPS650X30_I2C_ADDR1_FLAGS, (reg), (data)) static void board_pmic_init(void) { @@ -726,8 +711,8 @@ int board_set_active_charge_port(int charge_port) charge_port < CONFIG_USB_PD_PORT_MAX_COUNT); /* check if we are sourcing VBUS on the port */ /* dnojiri: revisit */ - int is_source = gpio_get_level(charge_port == 0 ? - GPIO_USB_C0_5V_EN : GPIO_USB_C1_5V_EN); + int is_source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN : + GPIO_USB_C1_5V_EN); if (is_real_port && is_source) { CPRINTF("No charging on source port p%d is ", charge_port); @@ -745,17 +730,19 @@ int board_set_active_charge_port(int charge_port) /* dnojiri: revisit. there is always this assumption that * battery is present. If not, this may cause brownout. */ gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L : - GPIO_USB_C1_CHARGE_L, 1); + GPIO_USB_C1_CHARGE_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 0); + GPIO_USB_C0_CHARGE_L, + 0); } return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 96% negotiated limit, @@ -764,12 +751,11 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, int factor = 96; if (oem == PROJECT_AKALI && - (model == MODEL_EKKO || model == MODEL_BARD)) + (model == MODEL_EKKO || model == MODEL_BARD)) factor = 95; charge_ma = charge_ma * factor / 100; charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void board_hibernate(void) @@ -782,9 +768,9 @@ void board_hibernate(void) } const struct pwm_t pwm_channels[] = { - [PWM_CH_LED1] = { 3, PWM_CONFIG_DSLEEP, 1200 }, + [PWM_CH_LED1] = { 3, PWM_CONFIG_DSLEEP, 1200 }, [PWM_CH_LED2] = { 5, PWM_CONFIG_DSLEEP, 1200 }, - [PWM_CH_FAN] = {4, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 4, PWM_CONFIG_OPEN_DRAIN, 25000 }, /* * 1.2kHz is a multiple of both 50 and 60. So a video recorder * (generally designed to ignore either 50 or 60 Hz flicker) will not @@ -806,23 +792,17 @@ static struct kionix_accel_data g_kx022_data; static struct accelgyro_saved_data_t g_bma255_data; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t rotation_x180_z90 = { - { 0, FLOAT_TO_FP(-1), 0 }, - { FLOAT_TO_FP(-1), 0, 0 }, - { 0, 0, FLOAT_TO_FP(-1) } -}; +const mat33_fp_t rotation_x180_z90 = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; const struct motion_sensor_t lid_accel_1 = { .name = "Lid Accel", @@ -1096,7 +1076,7 @@ static void board_init(void) ISL9238_REG_CONTROL3, ®) == EC_SUCCESS) { reg |= ISL9238_C3_BB_SWITCHING_PERIOD; if (i2c_write16(I2C_PORT_CHARGER, I2C_ADDR_CHARGER_FLAGS, - ISL9238_REG_CONTROL3, reg)) + ISL9238_REG_CONTROL3, reg)) CPRINTF("Failed to set isl9238\n"); } @@ -1188,14 +1168,13 @@ void board_kblight_init(void) } } -enum critical_shutdown board_critical_shutdown_check( - struct charge_state_data *curr) +enum critical_shutdown +board_critical_shutdown_check(struct charge_state_data *curr) { if (oem == PROJECT_VAYNE) return CRITICAL_SHUTDOWN_CUTOFF; else return CRITICAL_SHUTDOWN_HIBERNATE; - } uint8_t board_set_battery_level_shutdown(void) -- cgit v1.2.1 From a0993a78320b1b4c41f97c5d45c72e9a75130192 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:57 -0600 Subject: zephyr/shim/include/usbc/usb_muxes.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iae7b874cd9e95234080eb669783e2d4479dd81fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730854 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/usb_muxes.h | 124 +++++++++++++++++------------------ 1 file changed, 61 insertions(+), 63 deletions(-) diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h index 9422d4008d..1986114a2a 100644 --- a/zephyr/shim/include/usbc/usb_muxes.h +++ b/zephyr/shim/include/usbc/usb_muxes.h @@ -20,35 +20,35 @@ * @brief List of USB mux drivers compatibles and their configurations. Each * element of list has to have (compatible, config) format. */ -#define USB_MUX_DRIVERS \ - (ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483), \ - (BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \ - (IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205), \ - (PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ - (TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ - (TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064), \ - (VIRTUAL_USB_MUX_COMPAT, USB_MUX_CONFIG_VIRTUAL) +#define USB_MUX_DRIVERS \ + (ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483), \ + (BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \ + (IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205), \ + (PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ + (TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ + (TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064), \ + (VIRTUAL_USB_MUX_COMPAT, USB_MUX_CONFIG_VIRTUAL) /** * @brief Get compatible from @p driver * * @param driver USB mux driver description in format (compatible, config) */ -#define USB_MUX_DRIVER_GET_COMPAT(driver) GET_ARG_N(1, __DEBRACKET driver) +#define USB_MUX_DRIVER_GET_COMPAT(driver) GET_ARG_N(1, __DEBRACKET driver) /** * @brief Get configuration from @p driver * * @param driver USB mux driver description in format (compatible, config) */ -#define USB_MUX_DRIVER_GET_CONFIG(driver) GET_ARG_N(2, __DEBRACKET driver) +#define USB_MUX_DRIVER_GET_CONFIG(driver) GET_ARG_N(2, __DEBRACKET driver) /** * @brief USB mux port number based on parent node in DTS * * @param port_id USBC node ID */ -#define USB_MUX_PORT(port_id) DT_REG_ADDR(port_id) +#define USB_MUX_PORT(port_id) DT_REG_ADDR(port_id) /** * @brief Name of USB mux structure if node is not EMPTY. Note, that root of @@ -56,22 +56,22 @@ * * @param mux_id USB mux node ID */ -#define USB_MUX_STRUCT_NAME(mux_id) \ +#define USB_MUX_STRUCT_NAME(mux_id) \ COND_CODE_0(IS_EMPTY(mux_id), (DT_CAT(USB_MUX_NODE_, mux_id)), (EMPTY)) /** * @brief USB muxes in chain should be constant only if configuration * cannot change in runtime */ -#define MAYBE_CONST COND_CODE_1(CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG, \ - (), (const)) +#define MAYBE_CONST \ + COND_CODE_1(CONFIG_PLATFORM_EC_USB_MUX_RUNTIME_CONFIG, (), (const)) /** * @brief Declaration of USB mux structure * * @param mux_id USB mux node ID */ -#define USB_MUX_STRUCT_DECLARE(mux_id) \ +#define USB_MUX_STRUCT_DECLARE(mux_id) \ MAYBE_CONST struct usb_mux USB_MUX_STRUCT_NAME(mux_id) /** @@ -79,7 +79,7 @@ * * @param name Identifier to reference */ -#define USB_MUX_POINTER_OR_NULL(name) \ +#define USB_MUX_POINTER_OR_NULL(name) \ COND_CODE_0(IS_EMPTY(name), (&name), (NULL)) /** @@ -88,7 +88,7 @@ * @param idx Position of USB mux in chain * @param port_id USBC node ID */ -#define USB_MUX_GET_CHAIN_N(idx, port_id) \ +#define USB_MUX_GET_CHAIN_N(idx, port_id) \ DT_PHANDLE_BY_IDX(port_id, usb_muxes, idx) /** @@ -97,10 +97,11 @@ * @param port_id USBC node ID * @param idx Position of USB mux in chain */ -#define USB_MUX_NEXT(port_id, idx) \ - GET_ARG_N(2, GET_ARGS_LESS_N(idx, \ - LISTIFY(DT_PROP_LEN(port_id, usb_muxes), \ - USB_MUX_GET_CHAIN_N, (,), port_id)), \ +#define USB_MUX_NEXT(port_id, idx) \ + GET_ARG_N(2, \ + GET_ARGS_LESS_N( \ + idx, LISTIFY(DT_PROP_LEN(port_id, usb_muxes), \ + USB_MUX_GET_CHAIN_N, (, ), port_id)), \ EMPTY) /** @@ -109,7 +110,7 @@ * @param port_id USBC node ID * @param idx Position of USB mux in chain */ -#define USB_MUX_NEXT_POINTER(port_id, idx) \ +#define USB_MUX_NEXT_POINTER(port_id, idx) \ USB_MUX_POINTER_OR_NULL(USB_MUX_STRUCT_NAME(USB_MUX_NEXT(port_id, idx))) /** @@ -119,7 +120,7 @@ * @param mux_id USB mux node ID * @param cb_name Name of property with callback function */ -#define USB_MUX_CALLBACK_OR_NULL(mux_id, cb_name) \ +#define USB_MUX_CALLBACK_OR_NULL(mux_id, cb_name) \ USB_MUX_POINTER_OR_NULL(DT_STRING_TOKEN_OR(mux_id, cb_name, EMPTY)) /** @@ -131,12 +132,12 @@ * @param flags_mask Mask for bits that should be igonred in flags property * @param flags_val Value that should be used instead for masked bits */ -#define USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, \ - flags_mask, flags_val) \ - .usb_port = USB_MUX_PORT(port_id), \ - .next_mux = USB_MUX_NEXT_POINTER(port_id, idx), \ - .board_init = USB_MUX_CALLBACK_OR_NULL(mux_id, board_init), \ - .board_set = USB_MUX_CALLBACK_OR_NULL(mux_id, board_set), \ +#define USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, flags_mask, \ + flags_val) \ + .usb_port = USB_MUX_PORT(port_id), \ + .next_mux = USB_MUX_NEXT_POINTER(port_id, idx), \ + .board_init = USB_MUX_CALLBACK_OR_NULL(mux_id, board_init), \ + .board_set = USB_MUX_CALLBACK_OR_NULL(mux_id, board_set), \ .flags = (DT_PROP(mux_id, flags) & ~(flags_mask)) | (flags_val) /** @@ -146,7 +147,7 @@ * @param port_id USBC node ID * @param idx Position of USB mux in chain */ -#define USB_MUX_COMMON_FIELDS(mux_id, port_id, idx) \ +#define USB_MUX_COMMON_FIELDS(mux_id, port_id, idx) \ USB_MUX_COMMON_FIELDS_WITH_FLAGS(mux_id, port_id, idx, 0, 0) /** @@ -156,8 +157,7 @@ * @param mux_id USB mux node ID * @param compat USB mux driver compatible */ -#define USB_MUX_IS_COMPATIBLE(mux_id, compat) \ - DT_NODE_HAS_COMPAT(mux_id, compat) +#define USB_MUX_IS_COMPATIBLE(mux_id, compat) DT_NODE_HAS_COMPAT(mux_id, compat) /** * @brief Expands to @p driver config if @p mux_id is compatible with @p driver @@ -165,18 +165,18 @@ * @param driver USB mux driver description in format (compatible, config) * @param mux_id USB mux node ID */ -#define USB_MUX_DRIVER_CONFIG_IF_COMPAT(driver, mux_id) \ - COND_CODE_1(USB_MUX_IS_COMPATIBLE( \ - mux_id, USB_MUX_DRIVER_GET_COMPAT(driver)), \ - (USB_MUX_DRIVER_GET_CONFIG(driver)), ()) +#define USB_MUX_DRIVER_CONFIG_IF_COMPAT(driver, mux_id) \ + COND_CODE_1(USB_MUX_IS_COMPATIBLE(mux_id, \ + USB_MUX_DRIVER_GET_COMPAT(driver)), \ + (USB_MUX_DRIVER_GET_CONFIG(driver)), ()) /** * @brief Find driver from USB_MUX_DRIVERS that is compatible with @p mux_id * * @param mux_id USB mux node ID */ -#define USB_MUX_FIND_DRIVER_CONFIG(mux_id) \ - FOR_EACH_FIXED_ARG(USB_MUX_DRIVER_CONFIG_IF_COMPAT, (), mux_id, \ +#define USB_MUX_FIND_DRIVER_CONFIG(mux_id) \ + FOR_EACH_FIXED_ARG(USB_MUX_DRIVER_CONFIG_IF_COMPAT, (), mux_id, \ USB_MUX_DRIVERS) /** @@ -187,7 +187,7 @@ * @param idx Position of USB mux in chain * @param op Operation to perform on USB muxes */ -#define USB_MUX_CALL_OP(mux_id, port_id, idx, op) \ +#define USB_MUX_CALL_OP(mux_id, port_id, idx, op) \ op(mux_id, port_id, idx, USB_MUX_FIND_DRIVER_CONFIG(mux_id)) /** @@ -197,7 +197,7 @@ * @param idx Position of USB mux in chain * @param op Operation to perform on USB muxes */ -#define USB_MUX_DO(port_id, idx, op) \ +#define USB_MUX_DO(port_id, idx, op) \ USB_MUX_CALL_OP(USB_MUX_GET_CHAIN_N(idx, port_id), port_id, idx, op) /** @@ -208,7 +208,7 @@ * @param idx Position of USB mux in chain * @param conf Driver configuration function */ -#define USB_MUX_DECLARE(mux_id, port_id, idx, conf) \ +#define USB_MUX_DECLARE(mux_id, port_id, idx, conf) \ extern USB_MUX_STRUCT_DECLARE(mux_id); /** @@ -219,7 +219,7 @@ * @param idx Position of USB mux in chain * @param conf Driver configuration function */ -#define USB_MUX_DEFINE(mux_id, port_id, idx, conf) \ +#define USB_MUX_DEFINE(mux_id, port_id, idx, conf) \ USB_MUX_STRUCT_DECLARE(mux_id) = conf(mux_id, port_id, idx); /** @@ -230,7 +230,7 @@ * @param idx Position of USB mux in chain * @param conf Driver configuration function */ -#define USB_MUX_ARRAY(mux_id, port_id, idx, conf) \ +#define USB_MUX_ARRAY(mux_id, port_id, idx, conf) \ [USB_MUX_PORT(port_id)] = conf(mux_id, port_id, idx), /** @@ -241,8 +241,7 @@ * USB mux node ID, USBC port node ID, position in chain, and driver * config as arguments. */ -#define USB_MUX_FIRST(port_id, op) \ - USB_MUX_DO(port_id, 0, op) +#define USB_MUX_FIRST(port_id, op) USB_MUX_DO(port_id, 0, op) /** * @brief Call USB_MUX_DO if @p idx is not 0 (is not first mux in chain) @@ -252,7 +251,7 @@ * @param idx Position of USB mux in chain * @param op Operation to perform on USB muxes */ -#define USB_MUX_DO_SKIP_FIRST(port_id, unused2, idx, op) \ +#define USB_MUX_DO_SKIP_FIRST(port_id, unused2, idx, op) \ COND_CODE_1(UTIL_BOOL(idx), (USB_MUX_DO(port_id, idx, op)), ()) /** @@ -263,9 +262,9 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_NO_FIRST(port_id, op) \ - DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, \ - USB_MUX_DO_SKIP_FIRST, op) +#define USB_MUX_NO_FIRST(port_id, op) \ + DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, USB_MUX_DO_SKIP_FIRST, \ + op) /** * @brief Call @p op if @p idx mux in chain has BB retimer compatible @@ -275,12 +274,12 @@ * @param idx Position of USB mux in chain * @param op Operation to perform on BB retimer */ -#define USB_MUX_ONLY_BB_RETIMER(port_id, unused2, idx, op) \ - COND_CODE_1(USB_MUX_IS_COMPATIBLE( \ - USB_MUX_GET_CHAIN_N(idx, port_id), \ - BB_RETIMER_USB_MUX_COMPAT), \ - (op(USB_MUX_GET_CHAIN_N(idx, port_id), port_id, \ - idx, BB_RETIMER_CONTROLS_CONFIG)), ()) +#define USB_MUX_ONLY_BB_RETIMER(port_id, unused2, idx, op) \ + COND_CODE_1(USB_MUX_IS_COMPATIBLE(USB_MUX_GET_CHAIN_N(idx, port_id), \ + BB_RETIMER_USB_MUX_COMPAT), \ + (op(USB_MUX_GET_CHAIN_N(idx, port_id), port_id, idx, \ + BB_RETIMER_CONTROLS_CONFIG)), \ + ()) /** * @brief Call @p op with every BB retimer in chain @@ -290,8 +289,8 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_BB_RETIMERS(port_id, op) \ - DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, \ +#define USB_MUX_BB_RETIMERS(port_id, op) \ + DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, \ USB_MUX_ONLY_BB_RETIMER, op) /** @@ -306,8 +305,8 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_USBC_PORT_HAS_MUXES(port_id, filter, op) \ - COND_CODE_1(DT_NODE_HAS_PROP(port_id, usb_muxes), \ +#define USB_MUX_USBC_PORT_HAS_MUXES(port_id, filter, op) \ + COND_CODE_1(DT_NODE_HAS_PROP(port_id, usb_muxes), \ (filter(port_id, op)), ()) /** @@ -321,10 +320,9 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_FOREACH_USBC_PORT(filter, op) \ - DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port, \ - USB_MUX_USBC_PORT_HAS_MUXES, \ - filter, op) +#define USB_MUX_FOREACH_USBC_PORT(filter, op) \ + DT_FOREACH_STATUS_OKAY_VARGS(named_usbc_port, \ + USB_MUX_USBC_PORT_HAS_MUXES, filter, op) /** * Forward declare all usb_mux structures e.g. -- cgit v1.2.1 From c9e102b9a23bc58ca8ae26e53e17c8635a41fe46 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:45 -0600 Subject: board/fizz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8289c7c44cbe4cea5614115d6a69b078c897c7d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728367 Reviewed-by: Jeremy Bettis --- board/fizz/board.h | 80 ++++++++++++++++++++++++++---------------------------- 1 file changed, 38 insertions(+), 42 deletions(-) diff --git a/board/fizz/board.h b/board/fizz/board.h index ad1ca85cac..a40b7d04b2 100644 --- a/board/fizz/board.h +++ b/board/fizz/board.h @@ -12,7 +12,7 @@ * Allow dangerous commands. * TODO: Remove this config before production. */ -#undef CONFIG_SYSTEM_UNLOCKED +#undef CONFIG_SYSTEM_UNLOCKED #define CONFIG_USB_PD_COMM_LOCKED /* EC */ @@ -32,7 +32,7 @@ #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_POWER_BUTTON_IGNORE_LID #define CONFIG_PWM #define CONFIG_LTO @@ -47,7 +47,7 @@ #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE #define CEC_GPIO_OUT GPIO_CEC_OUT -#define CEC_GPIO_IN GPIO_CEC_IN +#define CEC_GPIO_IN GPIO_CEC_IN #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP #define CONFIG_FANS 1 #undef CONFIG_FAN_INIT_SPEED @@ -63,7 +63,7 @@ #undef CONFIG_CMD_ADC /* Reduce flash space usage */ -#undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CONSOLE_CMDHELP /* SOC */ #define CONFIG_CHIPSET_SKYLAKE @@ -82,7 +82,7 @@ #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 @@ -96,7 +96,7 @@ #define CONFIG_TEMP_SENSOR_TMP432 /* USB */ -#undef CONFIG_USB_CHARGER /* dnojiri: verify */ +#undef CONFIG_USB_CHARGER /* dnojiri: verify */ #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_CUSTOM_PDO @@ -119,7 +119,7 @@ #define CONFIG_USBC_VCONN_SWAP /* Charge ports */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT 1 @@ -128,21 +128,21 @@ #define USB_PORT_COUNT 5 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 +#define I2C_PORT_BATTERY NPCX_I2C_PORT1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_TCPC0_FLAGS 0x0b -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_TCPC0_FLAGS 0x0b +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Verify and jump to RW image on boot */ #define CONFIG_VBOOT_EFS @@ -159,18 +159,17 @@ * end of RW_A and RW_B, respectively. */ #define CONFIG_RW_B -#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF -#undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) -#undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE) -#define CONFIG_RW_A_SIGN_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define CONFIG_RW_B_SIGN_STORAGE_OFF (CONFIG_RW_B_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#undef CONFIG_RW_SIZE +#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF +#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE) +#define CONFIG_RW_A_SIGN_STORAGE_OFF \ + (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_SIGN_STORAGE_OFF \ + (CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) #define CONFIG_RWSIG #define CONFIG_RWSIG_TYPE_RWSIG @@ -196,15 +195,12 @@ enum charge_port { }; enum temp_sensor_id { - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ TEMP_SENSOR_COUNT }; -enum adc_channel { - ADC_VBUS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_LED_RED, @@ -245,17 +241,17 @@ enum OEM_ID { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power. Since Fizz doesn't have a battery to charge, * we're not interested in any power lower than the AP power-on threshold. */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From aebb0491044d62edcfc2ef059311b0af34cd84d2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:43 -0600 Subject: zephyr/shim/src/ppc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic15e7be58335f6617b900d907201c9b7474261d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730928 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/ppc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c index c1bf3cb0fd..936367ca78 100644 --- a/zephyr/shim/src/ppc.c +++ b/zephyr/shim/src/ppc.c @@ -10,7 +10,7 @@ #include "usbc/ppc_syv682x.h" #include "usbc/ppc.h" -#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \ +#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(SN5S330_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(SYV682X_COMPAT) @@ -30,10 +30,10 @@ struct ppc_config_t ppc_chips[] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_PRIM, - PPC_CHIP_SYV682X) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS( + SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X) }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -41,10 +41,10 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); struct ppc_config_t ppc_chips_alt[] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT, PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_ALT, - PPC_CHIP_SYV682X) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS( + SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 243b4e82b65cbdfa5bcb618e6d61bd08358f6c92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:23 -0600 Subject: common/capsense.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9d0586d59fc2cb741aa700e12304b2d613dabc8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729611 Reviewed-by: Jeremy Bettis --- common/capsense.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/common/capsense.c b/common/capsense.c index b2413ac61f..e5c3880e2a 100644 --- a/common/capsense.c +++ b/common/capsense.c @@ -12,8 +12,8 @@ #include "timer.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) #define CAPSENSE_I2C_ADDR 0x08 #define CAPSENSE_MASK_BITS 8 @@ -24,8 +24,7 @@ static int capsense_read_bitmask(void) int rv; uint8_t val = 0; - rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR, - 0, 0, &val, 1); + rv = i2c_xfer(I2C_PORT_CAPSENSE, CAPSENSE_I2C_ADDR, 0, 0, &val, 1); if (rv) CPRINTS("%s failed: error %d", __func__, rv); @@ -52,8 +51,8 @@ static void capsense_change_deferred(void) new_val = capsense_read_bitmask(); if (new_val != cur_val) { - CPRINTF("[%pT capsense 0x%02x: ", - PRINTF_TIMESTAMP_NOW, new_val); + CPRINTF("[%pT capsense 0x%02x: ", PRINTF_TIMESTAMP_NOW, + new_val); for (i = 0; i < CAPSENSE_MASK_BITS; i++) { /* See what changed */ n = (new_val >> i) & 0x01; -- cgit v1.2.1 From 37a326a95019946819a6222770f0ec152cfdc079 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:32 -0600 Subject: common/online_calibration.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03a5789212e04bcdb4cf5d139f19c46cfbdedb74 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729699 Reviewed-by: Jeremy Bettis --- common/online_calibration.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/online_calibration.c b/common/online_calibration.c index 6ff46f4714..fec20030ca 100644 --- a/common/online_calibration.c +++ b/common/online_calibration.c @@ -202,8 +202,7 @@ void online_calibration_init(void) void *type_specific_data = NULL; s->online_calib_data->last_temperature = -1; - type_specific_data = - s->online_calib_data->type_specific_data; + type_specific_data = s->online_calib_data->type_specific_data; if (!type_specific_data) continue; -- cgit v1.2.1 From 0cd6d00d668b03d339cb750a552435df8217a1e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:17 -0600 Subject: board/waddledoo/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95fa87a32021e821c9e73cd856b50acc38c8d6af Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729108 Reviewed-by: Jeremy Bettis --- board/waddledoo/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/waddledoo/cbi_ssfc.h b/board/waddledoo/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/waddledoo/cbi_ssfc.h +++ b/board/waddledoo/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From fca117e89f337e81d81180daef5b7136c60c2e5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:30 -0600 Subject: common/usb_pd_console_cmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I77c1e87ab00b7f7201fd06d85c214cd82817d35f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729771 Reviewed-by: Jeremy Bettis --- common/usb_pd_console_cmd.c | 75 +++++++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/common/usb_pd_console_cmd.c b/common/usb_pd_console_cmd.c index 3ad1944494..a04ef785f9 100644 --- a/common/usb_pd_console_cmd.c +++ b/common/usb_pd_console_cmd.c @@ -23,24 +23,24 @@ static void dump_pe(int port) const struct pd_discovery *disc = pd_get_am_discovery(port, TCPCI_MSG_SOP); - static const char * const idh_ptype_names[] = { - "UNDEF", "Hub", "Periph", "PCable", "ACable", "AMA", - "RSV6", "RSV7"}; - static const char * const tx_names[] = {"SOP", "SOP'", "SOP''"}; + static const char *const idh_ptype_names[] = { "UNDEF", "Hub", + "Periph", "PCable", + "ACable", "AMA", + "RSV6", "RSV7" }; + static const char *const tx_names[] = { "SOP", "SOP'", "SOP''" }; for (type = TCPCI_MSG_SOP; type < DISCOVERY_TYPE_COUNT; type++) { resp = pd_get_identity_response(port, type); if (pd_get_identity_discovery(port, type) != PD_DISC_COMPLETE) { ccprintf("No %s identity discovered yet.\n", - tx_names[type]); + tx_names[type]); continue; } idh_ptype = resp->idh.product_type; ccprintf("IDENT %s:\n", tx_names[type]); ccprintf("\t[ID Header] %08x :: %s, VID:%04x\n", - resp->raw_value[0], - idh_ptype_names[idh_ptype], + resp->raw_value[0], idh_ptype_names[idh_ptype], resp->idh.usb_vendor_id); ccprintf("\t[Cert Stat] %08x\n", resp->cert.xid); @@ -62,11 +62,11 @@ static void dump_pe(int port) ccprintf("SVID[%d]: %04x MODES:", i, disc->svids[i].svid); for (j = 0; j < disc->svids[j].mode_cnt; j++) ccprintf(" [%d] %08x", j + 1, - disc->svids[i].mode_vdo[j]); + disc->svids[i].mode_vdo[j]); ccprintf("\n"); modep = pd_get_amode_data(port, TCPCI_MSG_SOP, - disc->svids[i].svid); + disc->svids[i].svid); if (modep) { mode_caps = modep->data->mode_vdo[modep->opos - 1]; ccprintf("MODE[%d]: svid:%04x caps:%08x\n", modep->opos, @@ -92,18 +92,16 @@ static int command_pe(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pe, command_pe, - " dump", - "USB PE"); +DECLARE_CONSOLE_COMMAND(pe, command_pe, " dump", "USB PE"); #endif /* CONFIG_CMD_USB_PD_PE */ #ifdef CONFIG_CMD_USB_PD_CABLE -static const char * const cable_type[] = { +static const char *const cable_type[] = { [IDH_PTYPE_PCABLE] = "Passive", [IDH_PTYPE_ACABLE] = "Active", }; -static const char * const cable_curr[] = { +static const char *const cable_curr[] = { [USB_VBUS_CUR_3A] = "3A", [USB_VBUS_CUR_5A] = "5A", }; @@ -127,8 +125,7 @@ static int command_cable(int argc, char **argv) ptype = get_usb_pd_cable_type(port); ccprintf("Cable Type: "); - if (ptype != IDH_PTYPE_PCABLE && - ptype != IDH_PTYPE_ACABLE) { + if (ptype != IDH_PTYPE_PCABLE && ptype != IDH_PTYPE_ACABLE) { ccprintf("Not Emark Cable\n"); return EC_SUCCESS; } @@ -139,7 +136,6 @@ static int command_cable(int argc, char **argv) cable_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - /* Cable revision */ ccprintf("Cable Rev: %d.0\n", cable_rev + 1); @@ -148,13 +144,15 @@ static int command_cable(int argc, char **argv) * connector type (Bit 19:18) and current handling capability bit 6:5 */ ccprintf("Connector Type: %d\n", - disc->identity.product_t1.p_rev20.connector); + disc->identity.product_t1.p_rev20.connector); if (disc->identity.product_t1.p_rev20.vbus_cur) { ccprintf("Cable Current: %s\n", - disc->identity.product_t1.p_rev20.vbus_cur > - ARRAY_SIZE(cable_curr) ? "Invalid" : - cable_curr[disc->identity.product_t1.p_rev20.vbus_cur]); + disc->identity.product_t1.p_rev20.vbus_cur > + ARRAY_SIZE(cable_curr) ? + "Invalid" : + cable_curr[disc->identity.product_t1.p_rev20 + .vbus_cur]); } else ccprintf("Cable Current: Invalid\n"); @@ -164,7 +162,7 @@ static int command_cable(int argc, char **argv) */ if (ptype == IDH_PTYPE_PCABLE) ccprintf("USB Superspeed Signaling support: %d\n", - disc->identity.product_t1.p_rev20.ss); + disc->identity.product_t1.p_rev20.ss); /* * For Rev 3.0 active cables and Rev 2.0 active and passive cables, @@ -172,7 +170,8 @@ static int command_cable(int argc, char **argv) */ if (ptype == IDH_PTYPE_ACABLE) ccprintf("SOP'' Controller: %s present\n", - disc->identity.product_t1.a_rev20.sop_p_p ? "" : "Not"); + disc->identity.product_t1.a_rev20.sop_p_p ? "" : + "Not"); if (cable_rev == PD_REV30) { /* @@ -180,15 +179,16 @@ static int command_cable(int argc, char **argv) * same bits 10:9. */ ccprintf("Max vbus voltage: %d\n", - 20 + 10 * disc->identity.product_t1.p_rev30.vbus_max); + 20 + 10 * disc->identity.product_t1.p_rev30.vbus_max); /* For Rev 3.0 Active cables */ if (ptype == IDH_PTYPE_ACABLE) { ccprintf("SS signaling: USB_SS_GEN%u\n", - disc->identity.product_t2.a2_rev30.usb_gen ? - 2 : 1); + disc->identity.product_t2.a2_rev30.usb_gen ? + 2 : + 1); ccprintf("Number of SS lanes supported: %u\n", - disc->identity.product_t2.a2_rev30.usb_lanes); + disc->identity.product_t2.a2_rev30.usb_lanes); } } @@ -196,28 +196,29 @@ static int command_cable(int argc, char **argv) return EC_SUCCESS; ccprintf("Rounded support: %s\n", - cable_mode_resp.tbt_rounded == - TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ? "Yes" : "No"); + cable_mode_resp.tbt_rounded == + TBT_GEN3_GEN4_ROUNDED_NON_ROUNDED ? + "Yes" : + "No"); ccprintf("Optical cable: %s\n", - cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No"); + cable_mode_resp.tbt_cable == TBT_CABLE_OPTICAL ? "Yes" : "No"); ccprintf("Retimer support: %s\n", - cable_mode_resp.retimer_type == USB_RETIMER ? - "Yes" : "No"); + cable_mode_resp.retimer_type == USB_RETIMER ? "Yes" : "No"); ccprintf("Link training: %s-directional\n", - cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni"); + cable_mode_resp.lsrx_comm == BIDIR_LSRX_COMM ? "Bi" : "Uni"); ccprintf("Thunderbolt cable type: %s\n", - cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ? - "Active" : "Passive"); + cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ? + "Active" : + "Passive"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pdcable, command_cable, - "", +DECLARE_CONSOLE_COMMAND(pdcable, command_cable, "", "Cable Characteristics"); #endif /* CONFIG_CMD_USB_PD_CABLE */ -- cgit v1.2.1 From 401f570a9e04fd12af522e084f0845d446b57c79 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:58 -0600 Subject: driver/gl3590.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I363f6247ed42c801225b6b7f57e05a580e4ffe6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729978 Reviewed-by: Jeremy Bettis --- driver/gl3590.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/driver/gl3590.c b/driver/gl3590.c index cb8d914d8c..201228c368 100644 --- a/driver/gl3590.c +++ b/driver/gl3590.c @@ -12,8 +12,8 @@ #include "gl3590.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /* GL3590 is unique in terms of i2c_read, since it doesn't support repeated * start sequence. One need to issue two separate transactions - first is write @@ -25,11 +25,8 @@ int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count) struct uhub_i2c_iface_t *uhub_p = &uhub_config[hub]; i2c_lock(uhub_p->i2c_host_port, 1); - rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, - uhub_p->i2c_addr, - ®, 1, - NULL, 0, - I2C_XFER_SINGLE); + rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, ®, 1, + NULL, 0, I2C_XFER_SINGLE); i2c_lock(uhub_p->i2c_host_port, 0); if (rv) @@ -39,11 +36,8 @@ int gl3590_read(int hub, uint8_t reg, uint8_t *data, int count) udelay(MSEC); i2c_lock(uhub_p->i2c_host_port, 1); - rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, - uhub_p->i2c_addr, - NULL, 0, - data, count, - I2C_XFER_SINGLE); + rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, NULL, 0, + data, count, I2C_XFER_SINGLE); i2c_lock(uhub_p->i2c_host_port, 0); /* @@ -71,11 +65,8 @@ int gl3590_write(int hub, uint8_t reg, uint8_t *data, int count) memcpy(&buf[1], data, count); i2c_lock(uhub_p->i2c_host_port, 1); - rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, - uhub_p->i2c_addr, - buf, count + 1, - NULL, 0, - I2C_XFER_SINGLE); + rv = i2c_xfer_unlocked(uhub_p->i2c_host_port, uhub_p->i2c_addr, buf, + count + 1, NULL, 0, I2C_XFER_SINGLE); i2c_lock(uhub_p->i2c_host_port, 0); /* @@ -164,7 +155,7 @@ void gl3590_irq_handler(int hub) else ccprintf("Host hub event! "); - switch(res_reg[0]) { + switch (res_reg[0]) { case 0x0: ccprintf("No response"); break; @@ -247,7 +238,7 @@ enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr) return EC_SUCCESS; } else { CPRINTF("GL3590: Neither USB3 nor USB2 hubs " - "configured\n"); + "configured\n"); return EC_ERROR_HW_INTERNAL; } case GL3590_1_5_A_HOST_PWR_SRC: @@ -262,11 +253,11 @@ enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr) } } -#define GL3590_EN_PORT_MAX_RETRY_COUNT 10 +#define GL3590_EN_PORT_MAX_RETRY_COUNT 10 int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable) { - uint8_t buf[4] = {0}; + uint8_t buf[4] = { 0 }; uint8_t en_mask = 0; uint8_t tmp; int rv, i; @@ -306,8 +297,9 @@ int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable) } CPRINTF("GL3590: Port %s retrying.. %d/%d\n" - "Port status is 0x%x\n", enable ? "enable" : "disable", - i, GL3590_EN_PORT_MAX_RETRY_COUNT, tmp); + "Port status is 0x%x\n", + enable ? "enable" : "disable", i, + GL3590_EN_PORT_MAX_RETRY_COUNT, tmp); } return EC_SUCCESS; -- cgit v1.2.1 From 79fde1cf39d4e4c2f6f4049eb877782bc60632c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:25 -0600 Subject: test/rtc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5efb394a3c8566f73095b9f1562a96b22a0b1a7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730537 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/rtc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/test/rtc.c b/test/rtc.c index 3e53f85611..d7f20f831f 100644 --- a/test/rtc.c +++ b/test/rtc.c @@ -16,15 +16,14 @@ static struct { struct calendar_date time; uint32_t sec; } test_case[] = { - {{8, 3, 1}, 1204329600}, - {{17, 10, 1}, 1506816000}, + { { 8, 3, 1 }, 1204329600 }, + { { 17, 10, 1 }, 1506816000 }, }; static int calendar_time_comp(struct calendar_date time_1, - struct calendar_date time_2) + struct calendar_date time_2) { - return (time_1.year == time_2.year && - time_1.month == time_2.month && + return (time_1.year == time_2.year && time_1.month == time_2.month && time_1.day == time_2.day); } -- cgit v1.2.1 From 1119032aa0c2c7c0ac3e36fe9e13a16a2df12ce6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:53 -0600 Subject: include/usb_tbt_alt_mode.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I015a8fe973704ecb6bcad6a58f8e2e01c0e9ccb1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730449 Reviewed-by: Jeremy Bettis --- include/usb_tbt_alt_mode.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb_tbt_alt_mode.h b/include/usb_tbt_alt_mode.h index a187c1b42b..c445c013fb 100644 --- a/include/usb_tbt_alt_mode.h +++ b/include/usb_tbt_alt_mode.h @@ -78,7 +78,7 @@ bool tbt_is_active(int port); * @param vdm VDM from ACK */ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm); + uint32_t *vdm); /* * Handles NAKed (or Not Supported or timed out) Thunderbolt VDM requests. -- cgit v1.2.1 From 888b2e989bdd7bb3b7735fee042de2b3d48db9b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:00 -0600 Subject: common/vboot/common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic4e898b710e9843ebae7ba08f668b8bafb6eb215 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729805 Reviewed-by: Jeremy Bettis --- common/vboot/common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/vboot/common.c b/common/vboot/common.c index 39f8c193c7..1e45d7389c 100644 --- a/common/vboot/common.c +++ b/common/vboot/common.c @@ -10,8 +10,8 @@ #include "shared_mem.h" #include "vboot.h" -#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ## args) +#define CPRINTS(format, args...) cprints(CC_VBOOT, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_VBOOT, format, ##args) int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end) { @@ -32,8 +32,8 @@ int vboot_is_padding_valid(const uint8_t *data, uint32_t start, uint32_t end) return EC_SUCCESS; } -int vboot_verify(const uint8_t *data, int len, - const struct rsa_public_key *key, const uint8_t *sig) +int vboot_verify(const uint8_t *data, int len, const struct rsa_public_key *key, + const uint8_t *sig) { struct sha256_ctx ctx; uint8_t *hash; -- cgit v1.2.1 From b42238fe687f8bdc0bcda65c12f93fdb89fa381a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:47 -0600 Subject: include/host_command.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie90e2fb5163feba32e1c934773f934e5d26711f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730280 Reviewed-by: Jeremy Bettis --- include/host_command.h | 93 +++++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/include/host_command.h b/include/host_command.h index 3ab3d54351..9ebb5989a3 100644 --- a/include/host_command.h +++ b/include/host_command.h @@ -20,11 +20,11 @@ struct host_cmd_handler_args { * send the response back to the host. */ void (*send_response)(struct host_cmd_handler_args *args); - uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */ - uint8_t version; /* Version of command (0-31) */ + uint16_t command; /* Command (e.g., EC_CMD_FLASH_GET_INFO) */ + uint8_t version; /* Version of command (0-31) */ const void *params; /* Input parameters */ - uint16_t params_size; /* Size of input parameters in bytes */ + uint16_t params_size; /* Size of input parameters in bytes */ /* * Pointer to output response data buffer. On input to the handler, @@ -130,14 +130,13 @@ struct host_command { #ifdef CONFIG_HOST_EVENT64 typedef uint64_t host_event_t; -#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e) -#define HOST_EVENT_CCPRINTF(str, e) \ - ccprintf("%s 0x%016" PRIx64 "\n", str, e) +#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%016" PRIx64, str, e) +#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%016" PRIx64 "\n", str, e) #else typedef uint32_t host_event_t; -#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%08x", str, e) -#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%08x\n", str, e) +#define HOST_EVENT_CPRINTS(str, e) CPRINTS("%s 0x%08x", str, e) +#define HOST_EVENT_CCPRINTF(str, e) ccprintf("%s 0x%08x\n", str, e) #endif /** @@ -256,44 +255,46 @@ void host_packet_receive(struct host_packet *pkt); #ifndef CONFIG_ZEPHYR __error("This function should only be called from Zephyr OS code") #endif -struct host_command *zephyr_find_host_command(int command); + struct host_command *zephyr_find_host_command(int command); #if defined(CONFIG_ZEPHYR) #include "zephyr_host_command.h" #elif defined(HAS_TASK_HOSTCMD) #define EXPAND(off, cmd) __host_cmd_(off, cmd) #define __host_cmd_(off, cmd) __host_cmd_##off##cmd -#define EXPANDSTR(off, cmd) "__host_cmd_"#off#cmd +#define EXPANDSTR(off, cmd) "__host_cmd_" #off #cmd /* * Register a host command handler with * commands starting at offset 0x0000 */ -#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status(routine)(struct host_cmd_handler_args *args); \ - const struct host_command __keep __no_sanitize_address \ - EXPAND(0x0000, command) \ - __attribute__((section(".rodata.hcmds." EXPANDSTR(0x0000, command)))) \ - = {routine, command, version_mask} +#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args); \ + const struct host_command __keep __no_sanitize_address EXPAND(0x0000, \ + command) \ + __attribute__((section(".rodata.hcmds." EXPANDSTR( \ + 0x0000, command)))) = { routine, command, \ + version_mask } /* * Register a private host command handler with * commands starting at offset EC_CMD_BOARD_SPECIFIC_BASE, */ -#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status(routine)(struct host_cmd_handler_args *args); \ - const struct host_command __keep __no_sanitize_address \ - EXPAND(EC_CMD_BOARD_SPECIFIC_BASE, command) \ - __attribute__((section(".rodata.hcmds."\ - EXPANDSTR(EC_CMD_BOARD_SPECIFIC_BASE, command)))) \ - = {routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \ - version_mask} +#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args); \ + const struct host_command __keep __no_sanitize_address EXPAND( \ + EC_CMD_BOARD_SPECIFIC_BASE, command) \ + __attribute__((section(".rodata.hcmds." EXPANDSTR( \ + EC_CMD_BOARD_SPECIFIC_BASE, command)))) = { \ + routine, EC_PRIVATE_HOST_COMMAND_VALUE(command), \ + version_mask \ + } #else /* !CONFIG_ZEPHYR && !HAS_TASK_HOSTCMD */ -#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ - static enum ec_status (routine)(struct host_cmd_handler_args *args) \ +#define DECLARE_HOST_COMMAND(command, routine, version_mask) \ + static enum ec_status(routine)(struct host_cmd_handler_args * args) \ __attribute__((unused)) -#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ +#define DECLARE_PRIVATE_HOST_COMMAND(command, routine, version_mask) \ DECLARE_HOST_COMMAND(command, routine, version_mask) #endif /* CONFIG_ZEPHYR */ @@ -304,7 +305,6 @@ struct host_command *zephyr_find_host_command(int command); */ void host_throttle_cpu(int throttle); - /** * Signal host command task to send status to PD MCU. * @@ -335,8 +335,7 @@ int pd_get_active_charge_port(void); * @param indata Pointer to buffer to store response * @param insize Size of buffer to store response */ -int pd_host_command(int command, int version, - const void *outdata, int outsize, +int pd_host_command(int command, int version, const void *outdata, int outsize, void *indata, int insize); /* @@ -358,29 +357,29 @@ stub_send_response_callback(struct host_cmd_handler_args *args) ARG_UNUSED(args); } -#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS) \ - { \ - .command = (CMD), .version = (VERSION), \ - .send_response = stub_send_response_callback, \ - .response_size = 0, \ - COND_CODE_0(IS_EMPTY(RESPONSE), \ - (.response = &(RESPONSE), \ - .response_max = sizeof(RESPONSE)), \ - (.response = NULL, .response_max = 0)), \ - COND_CODE_0(IS_EMPTY(PARAMS), \ - (.params = &(PARAMS), \ - .params_size = sizeof(PARAMS)), \ - (.params = NULL, .params_size = 0)) \ +#define BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, PARAMS) \ + { \ + .command = (CMD), .version = (VERSION), \ + .send_response = stub_send_response_callback, \ + .response_size = 0, \ + COND_CODE_0(IS_EMPTY(RESPONSE), \ + (.response = &(RESPONSE), \ + .response_max = sizeof(RESPONSE)), \ + (.response = NULL, .response_max = 0)), \ + COND_CODE_0(IS_EMPTY(PARAMS), \ + (.params = &(PARAMS), \ + .params_size = sizeof(PARAMS)), \ + (.params = NULL, .params_size = 0)) \ } -#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \ +#define BUILD_HOST_COMMAND_RESPONSE(CMD, VERSION, RESPONSE) \ BUILD_HOST_COMMAND(CMD, VERSION, RESPONSE, EMPTY) -#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \ +#define BUILD_HOST_COMMAND_PARAMS(CMD, VERSION, PARAMS) \ BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, PARAMS) -#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \ +#define BUILD_HOST_COMMAND_SIMPLE(CMD, VERSION) \ BUILD_HOST_COMMAND(CMD, VERSION, EMPTY, EMPTY) #endif /* CONFIG_ZTEST */ -#endif /* __CROS_EC_HOST_COMMAND_H */ +#endif /* __CROS_EC_HOST_COMMAND_H */ -- cgit v1.2.1 From 243e242e4945ceb0971574e74cc1842371bb0f5c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:05 -0600 Subject: chip/ish/ish_persistent_data.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I82632e4110b8d4571ea5b98176a06c19760269b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729186 Reviewed-by: Jeremy Bettis --- chip/ish/ish_persistent_data.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/chip/ish/ish_persistent_data.c b/chip/ish/ish_persistent_data.c index 003f781d5f..be74960cb0 100644 --- a/chip/ish/ish_persistent_data.c +++ b/chip/ish/ish_persistent_data.c @@ -16,7 +16,7 @@ struct ish_persistent_data ish_persistent_data = { .magic = PERSISTENT_DATA_MAGIC, .reset_flags = EC_RESET_FLAG_POWER_ON, .watchdog_counter = 0, - .panic_data = {0}, + .panic_data = { 0 }, }; /* @@ -40,8 +40,7 @@ void ish_persistent_data_init(void) { if (ish_persistent_data_aon.magic == PERSISTENT_DATA_MAGIC) { /* Stored data is valid, load a copy */ - memcpy(&ish_persistent_data, - &ish_persistent_data_aon, + memcpy(&ish_persistent_data, &ish_persistent_data_aon, sizeof(struct ish_persistent_data)); /* Invalidate stored data, in case commit fails to happen */ @@ -54,7 +53,6 @@ void ish_persistent_data_init(void) void ish_persistent_data_commit(void) { - memcpy(&ish_persistent_data_aon, - &ish_persistent_data, + memcpy(&ish_persistent_data_aon, &ish_persistent_data, sizeof(struct ish_persistent_data)); } -- cgit v1.2.1 From 5aa417fb82a26c153a6f6097fbb85202b64dc1af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:49 -0600 Subject: board/anahera/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9e7b9c5de85116e27abf4665563b118bc55c358 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727991 Reviewed-by: Jeremy Bettis --- board/anahera/usbc_config.h | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/board/anahera/usbc_config.h b/board/anahera/usbc_config.h index b42c0f59fe..785cfdb082 100644 --- a/board/anahera/usbc_config.h +++ b/board/anahera/usbc_config.h @@ -8,21 +8,13 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; struct ps8811_reg_val { uint8_t reg; -- cgit v1.2.1 From c8db23656825fe4c42412d963b8c2368bbd23371 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:18 -0600 Subject: chip/max32660/gpio_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I63ce147fc4a7f68cbdde79690d5cbe78e52c556d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729231 Reviewed-by: Jeremy Bettis --- chip/max32660/gpio_regs.h | 703 +++++++++++++++++++++++----------------------- 1 file changed, 358 insertions(+), 345 deletions(-) diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h index 1c6fcf7a71..172d8f14c9 100644 --- a/chip/max32660/gpio_regs.h +++ b/chip/max32660/gpio_regs.h @@ -40,65 +40,65 @@ * Structure type to access the GPIO Registers. */ typedef struct { - __IO uint32_t en; /**< \b 0x00:<\tt> GPIO EN Register */ + __IO uint32_t en; /**< \b 0x00:<\tt> GPIO EN Register */ __IO uint32_t en_set; /**< \b 0x04:<\tt> GPIO EN_SET Register */ __IO uint32_t en_clr; /**< \b 0x08:<\tt> GPIO EN_CLR Register */ __IO uint32_t out_en; /**< \b 0x0C:<\tt> GPIO OUT_EN Register */ - __IO uint32_t - out_en_set; /**< \b 0x10:<\tt> GPIO OUT_EN_SET Register */ - __IO uint32_t - out_en_clr; /**< \b 0x14:<\tt> GPIO OUT_EN_CLR Register */ - __IO uint32_t out; /**< \b 0x18:<\tt> GPIO OUT Register */ + __IO uint32_t out_en_set; /**< \b 0x10:<\tt> GPIO OUT_EN_SET + Register */ + __IO uint32_t out_en_clr; /**< \b 0x14:<\tt> GPIO OUT_EN_CLR + Register */ + __IO uint32_t out; /**< \b 0x18:<\tt> GPIO OUT Register */ __O uint32_t out_set; /**< \b 0x1C:<\tt> GPIO OUT_SET Register */ __O uint32_t out_clr; /**< \b 0x20:<\tt> GPIO OUT_CLR Register */ - __I uint32_t in; /**< \b 0x24:<\tt> GPIO IN Register */ + __I uint32_t in; /**< \b 0x24:<\tt> GPIO IN Register */ __IO uint32_t int_mod; /**< \b 0x28:<\tt> GPIO INT_MOD Register */ __IO uint32_t int_pol; /**< \b 0x2C:<\tt> GPIO INT_POL Register */ __R uint32_t rsv_0x30; __IO uint32_t int_en; /**< \b 0x34:<\tt> GPIO INT_EN Register */ - __IO uint32_t - int_en_set; /**< \b 0x38:<\tt> GPIO INT_EN_SET Register */ - __IO uint32_t - int_en_clr; /**< \b 0x3C:<\tt> GPIO INT_EN_CLR Register */ + __IO uint32_t int_en_set; /**< \b 0x38:<\tt> GPIO INT_EN_SET + Register */ + __IO uint32_t int_en_clr; /**< \b 0x3C:<\tt> GPIO INT_EN_CLR + Register */ __I uint32_t int_stat; /**< \b 0x40:<\tt> GPIO INT_STAT Register */ __R uint32_t rsv_0x44; __IO uint32_t int_clr; /**< \b 0x48:<\tt> GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< \b 0x4C:<\tt> GPIO WAKE_EN Register */ - __IO uint32_t - wake_en_set; /**< \b 0x50:<\tt> GPIO WAKE_EN_SET Register */ - __IO uint32_t - wake_en_clr; /**< \b 0x54:<\tt> GPIO WAKE_EN_CLR Register */ + __IO uint32_t wake_en_set; /**< \b 0x50:<\tt> GPIO WAKE_EN_SET + Register */ + __IO uint32_t wake_en_clr; /**< \b 0x54:<\tt> GPIO WAKE_EN_CLR + Register */ __R uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< \b 0x5C:<\tt> GPIO INT_DUAL_EDGE Register */ __IO uint32_t pad_cfg1; /**< \b 0x60:<\tt> GPIO PAD_CFG1 Register */ __IO uint32_t pad_cfg2; /**< \b 0x64:<\tt> GPIO PAD_CFG2 Register */ - __IO uint32_t en1; /**< \b 0x68:<\tt> GPIO EN1 Register */ - __IO uint32_t en1_set; /**< \b 0x6C:<\tt> GPIO EN1_SET Register */ - __IO uint32_t en1_clr; /**< \b 0x70:<\tt> GPIO EN1_CLR Register */ - __IO uint32_t en2; /**< \b 0x74:<\tt> GPIO EN2 Register */ - __IO uint32_t en2_set; /**< \b 0x78:<\tt> GPIO EN2_SET Register */ - __IO uint32_t en2_clr; /**< \b 0x7C:<\tt> GPIO EN2_CLR Register */ + __IO uint32_t en1; /**< \b 0x68:<\tt> GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C:<\tt> GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70:<\tt> GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74:<\tt> GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78:<\tt> GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C:<\tt> GPIO EN2_CLR Register */ __R uint32_t rsv_0x80_0xa7[10]; - __IO uint32_t is; /**< \b 0xA8:<\tt> GPIO IS Register */ - __IO uint32_t sr; /**< \b 0xAC:<\tt> GPIO SR Register */ - __IO uint32_t ds; /**< \b 0xB0:<\tt> GPIO DS Register */ + __IO uint32_t is; /**< \b 0xA8:<\tt> GPIO IS Register */ + __IO uint32_t sr; /**< \b 0xAC:<\tt> GPIO SR Register */ + __IO uint32_t ds; /**< \b 0xB0:<\tt> GPIO DS Register */ __IO uint32_t ds1; /**< \b 0xB4:<\tt> GPIO DS1 Register */ - __IO uint32_t ps; /**< \b 0xB8:<\tt> GPIO PS Register */ + __IO uint32_t ps; /**< \b 0xB8:<\tt> GPIO PS Register */ __R uint32_t rsv_0xbc; __IO uint32_t vssel; /**< \b 0xC0:<\tt> GPIO VSSEL Register */ } mxc_gpio_regs_t; -#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ -#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ -#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ -#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ -#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ -#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ -#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ -#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ -#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ -#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ +#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ +#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ +#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ +#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ +#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ +#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ +#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ +#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ +#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ +#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ #define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ #define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ #define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ @@ -126,8 +126,8 @@ typedef struct { * Enumeration type for the GPIO Function Type */ typedef enum { - GPIO_FUNC_IN, /**< GPIO Input */ - GPIO_FUNC_OUT, /**< GPIO Output */ + GPIO_FUNC_IN, /**< GPIO Input */ + GPIO_FUNC_OUT, /**< GPIO Output */ GPIO_FUNC_ALT1, /**< Alternate Function Selection */ GPIO_FUNC_ALT2, /**< Alternate Function Selection */ GPIO_FUNC_ALT3, /**< Alternate Function Selection */ @@ -138,8 +138,8 @@ typedef enum { * Enumeration type for the type of GPIO pad on a given pin. */ typedef enum { - GPIO_PAD_NONE, /**< No pull-up or pull-down */ - GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ + GPIO_PAD_NONE, /**< No pull-up or pull-down */ + GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */ } gpio_pad_t; @@ -147,10 +147,10 @@ typedef enum { * Structure type for configuring a GPIO port. */ typedef struct { - uint32_t port; /**< Index of GPIO port */ - uint32_t mask; /**< Pin mask (multiple pins may be set) */ + uint32_t port; /**< Index of GPIO port */ + uint32_t mask; /**< Pin mask (multiple pins may be set) */ gpio_func_t func; /**< Function type */ - gpio_pad_t pad; /**< Pad type */ + gpio_pad_t pad; /**< Pad type */ } gpio_cfg_t; typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t; @@ -166,110 +166,110 @@ typedef enum { } gpio_int_pol_t; /* Register offsets for module GPIO */ -#define MXC_R_GPIO_EN \ - ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN \ + ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: \ 0x0x000 */ -#define MXC_R_GPIO_EN_SET \ - ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN_SET \ + ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: \ 0x0x004 */ -#define MXC_R_GPIO_EN_CLR \ - ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN_CLR \ + ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: \ 0x0x008 */ -#define MXC_R_GPIO_OUT_EN \ - ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT_EN \ + ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: \ 0x0x00C */ -#define MXC_R_GPIO_OUT_EN_SET \ - ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT_EN_SET \ + ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: \ 0x0x010 */ -#define MXC_R_GPIO_OUT_EN_CLR \ - ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT_EN_CLR \ + ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: \ 0x0x014 */ -#define MXC_R_GPIO_OUT \ - ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT \ + ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: \ 0x0x018 */ -#define MXC_R_GPIO_OUT_SET \ - ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT_SET \ + ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: \ 0x0x01C */ -#define MXC_R_GPIO_OUT_CLR \ - ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_OUT_CLR \ + ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: \ 0x0x020 */ -#define MXC_R_GPIO_IN \ - ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_IN \ + ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: \ 0x0x024 */ -#define MXC_R_GPIO_INT_MOD \ - ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_MOD \ + ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: \ 0x0x028 */ -#define MXC_R_GPIO_INT_POL \ - ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_POL \ + ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: \ 0x0x02C */ -#define MXC_R_GPIO_INT_EN \ - ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_EN \ + ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: \ 0x0x034 */ -#define MXC_R_GPIO_INT_EN_SET \ - ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_EN_SET \ + ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: \ 0x0x038 */ -#define MXC_R_GPIO_INT_EN_CLR \ - ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_EN_CLR \ + ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: \ 0x0x03C */ -#define MXC_R_GPIO_INT_STAT \ - ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_STAT \ + ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: \ 0x0x040 */ -#define MXC_R_GPIO_INT_CLR \ - ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_CLR \ + ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: \ 0x0x048 */ -#define MXC_R_GPIO_WAKE_EN \ - ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_WAKE_EN \ + ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: \ 0x0x04C */ -#define MXC_R_GPIO_WAKE_EN_SET \ - ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_WAKE_EN_SET \ + ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: \ 0x0x050 */ -#define MXC_R_GPIO_WAKE_EN_CLR \ - ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_WAKE_EN_CLR \ + ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: \ 0x0x054 */ -#define MXC_R_GPIO_INT_DUAL_EDGE \ - ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_INT_DUAL_EDGE \ + ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: \ 0x0x05C */ -#define MXC_R_GPIO_PAD_CFG1 \ - ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_PAD_CFG1 \ + ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: \ 0x0x060 */ -#define MXC_R_GPIO_PAD_CFG2 \ - ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_PAD_CFG2 \ + ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: \ 0x0x064 */ -#define MXC_R_GPIO_EN1 \ - ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN1 \ + ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: \ 0x0x068 */ -#define MXC_R_GPIO_EN1_SET \ - ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN1_SET \ + ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: \ 0x0x06C */ -#define MXC_R_GPIO_EN1_CLR \ - ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN1_CLR \ + ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: \ 0x0x070 */ -#define MXC_R_GPIO_EN2 \ - ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN2 \ + ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: \ 0x0x074 */ -#define MXC_R_GPIO_EN2_SET \ - ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN2_SET \ + ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: \ 0x0x078 */ -#define MXC_R_GPIO_EN2_CLR \ - ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_EN2_CLR \ + ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: \ 0x0x07C */ -#define MXC_R_GPIO_IS \ - ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_IS \ + ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: \ 0x0x0A8 */ -#define MXC_R_GPIO_SR \ - ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_SR \ + ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: \ 0x0x0AC */ -#define MXC_R_GPIO_DS \ - ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_DS \ + ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: \ 0x0x0B0 */ -#define MXC_R_GPIO_DS1 \ - ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_DS1 \ + ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: \ 0x0x0B4 */ -#define MXC_R_GPIO_PS \ - ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_PS \ + ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: \ 0x0x0B8 */ -#define MXC_R_GPIO_VSSEL \ - ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: \ +#define MXC_R_GPIO_VSSEL \ + ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: \ 0x0x0C0 */ /** @@ -277,19 +277,24 @@ typedef enum { * setting for one GPIO pin on the associated port. */ #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ -#define MXC_F_GPIO_EN_GPIO_EN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ -#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ +#define MXC_F_GPIO_EN_GPIO_EN \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< \ + EN_GPIO_EN \ + Mask */ +#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ -#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ - (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ -#define MXC_V_GPIO_EN_GPIO_EN_GPIO \ +#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ + (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_ALTERNATE \ + Setting \ + */ +#define MXC_V_GPIO_EN_GPIO_EN_GPIO \ ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ -#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ - (MXC_V_GPIO_EN_GPIO_EN_GPIO \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ +#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ + (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_GPIO \ + Setting \ + */ /** * GPIO Set Function Enable Register. Writing a 1 to one or more bits @@ -297,9 +302,10 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ -#define MXC_F_GPIO_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ +#define MXC_F_GPIO_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< \ + EN_SET_ALL \ + Mask */ /** * GPIO Clear Function Enable Register. Writing a 1 to one or more @@ -307,33 +313,34 @@ typedef enum { * without affecting other bits in that register. */ #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ -#define MXC_F_GPIO_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ +#define MXC_F_GPIO_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< \ + EN_CLR_ALL \ + Mask */ /** * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN * setting for one GPIO pin in the associated port. */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS \ - 0 /**< OUT_EN_GPIO_OUT_EN Position \ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS \ + 0 /**< OUT_EN_GPIO_OUT_EN Position \ */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \ - Mask */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< \ + OUT_EN_GPIO_OUT_EN \ + Mask */ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ + (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \ Setting */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN \ + (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \ Setting */ /** @@ -342,10 +349,10 @@ typedef enum { * GPIO_OUT_EN to 1, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ -#define MXC_F_GPIO_OUT_EN_SET_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< \ + OUT_EN_SET_ALL \ + Mask */ /** * GPIO Output Enable Clear Function Enable Register. Writing a 1 to @@ -353,10 +360,10 @@ typedef enum { * GPIO_OUT_EN to 0, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ -#define MXC_F_GPIO_OUT_EN_CLR_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< \ + OUT_EN_CLR_ALL \ + Mask */ /** * GPIO Output Register. Each bit controls the GPIO_OUT setting for @@ -364,40 +371,44 @@ typedef enum { * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. */ #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ -#define MXC_F_GPIO_OUT_GPIO_OUT \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ -#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ +#define MXC_F_GPIO_OUT_GPIO_OUT \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< \ + OUT_GPIO_OUT \ + Mask */ +#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ - (MXC_V_GPIO_OUT_GPIO_OUT_LOW \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ -#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ + (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_LOW \ + Setting \ + */ +#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ - (MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ + (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_HIGH \ + Setting \ + */ /** * GPIO Output Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_OUT to 1, without affecting other * bits in that register. */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \ 0 /**< OUT_SET_GPIO_OUT_SET Position */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< \ - OUT_SET_GPIO_OUT_SET \ - Mask */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< \ + OUT_SET_GPIO_OUT_SET \ + Mask */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ -#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO \ + (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ + << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \ Setting */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET \ (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ @@ -408,49 +419,48 @@ typedef enum { * clears the bits in the same positions in GPIO_OUT to 0, without affecting * other bits in that register. */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \ 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< \ - OUT_CLR_GPIO_OUT_CLR \ - Mask */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< \ + OUT_CLR_GPIO_OUT_CLR \ + Mask */ /** * GPIO Input Register. Read-only register to read from the logic * states of the GPIO pins on this port. */ #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ -#define MXC_F_GPIO_IN_GPIO_IN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_IN_GPIO_IN \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< \ + IN_GPIO_IN \ + Mask */ /** * GPIO Interrupt Mode Register. Each bit in this register controls * the interrupt mode setting for the associated GPIO pin on this port. */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \ 0 /**< INT_MOD_GPIO_INT_MOD Position */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< \ - INT_MOD_GPIO_INT_MOD \ - Mask */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< \ + INT_MOD_GPIO_INT_MOD \ + Mask */ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ INT_MOD_GPIO_INT_MOD_LEVEL \ Setting */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ -#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ - INT_MOD_GPIO_INT_MOD_EDGE \ +#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ + (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ + << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ + INT_MOD_GPIO_INT_MOD_EDGE \ Setting */ /** @@ -458,22 +468,21 @@ typedef enum { * controls the interrupt polarity setting for one GPIO pin in the associated * port. */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \ 0 /**< INT_POL_GPIO_INT_POL Position */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< \ - INT_POL_GPIO_INT_POL \ - Mask */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< \ + INT_POL_GPIO_INT_POL \ + Mask */ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING \ (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< \ INT_POL_GPIO_INT_POL_FALLING \ Setting */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING \ (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ @@ -485,25 +494,25 @@ typedef enum { * GPIO Interrupt Enable Register. Each bit in this register controls * the GPIO interrupt enable for the associated pin on the GPIO port. */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS \ - 0 /**< INT_EN_GPIO_INT_EN Position \ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS \ + 0 /**< INT_EN_GPIO_INT_EN Position \ */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \ - Mask */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< \ + INT_EN_GPIO_INT_EN \ + Mask */ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS \ + (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \ Setting */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN \ + (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \ Setting */ /** @@ -511,22 +520,21 @@ typedef enum { * register sets the bits in the same positions in GPIO_INT_EN to 1, without * affecting other bits in that register. */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \ 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< \ - INT_EN_SET_GPIO_INT_EN_SET \ - Mask */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< \ + INT_EN_SET_GPIO_INT_EN_SET \ + Mask */ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< \ INT_EN_SET_GPIO_INT_EN_SET_NO \ Setting */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ @@ -538,22 +546,21 @@ typedef enum { * this register clears the bits in the same positions in GPIO_INT_EN to 0, * without affecting other bits in that register. */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \ 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< \ - INT_EN_CLR_GPIO_INT_EN_CLR \ - Mask */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< \ + INT_EN_CLR_GPIO_INT_EN_CLR \ + Mask */ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< \ INT_EN_CLR_GPIO_INT_EN_CLR_NO \ Setting */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ @@ -564,22 +571,21 @@ typedef enum { * GPIO Interrupt Status Register. Each bit in this register contains * the pending interrupt status for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \ 0 /**< INT_STAT_GPIO_INT_STAT Position */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< \ - INT_STAT_GPIO_INT_STAT \ - Mask */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< \ + INT_STAT_GPIO_INT_STAT \ + Mask */ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO \ (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< \ INT_STAT_GPIO_INT_STAT_NO \ Setting */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ @@ -593,33 +599,33 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ -#define MXC_F_GPIO_INT_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ +#define MXC_F_GPIO_INT_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< \ + INT_CLR_ALL \ + Mask */ /** * GPIO Wake Enable Register. Each bit in this register controls the * PMU wakeup enable for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \ 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< \ - WAKE_EN_GPIO_WAKE_EN \ - Mask */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< \ + WAKE_EN_GPIO_WAKE_EN \ + Mask */ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \ Setting */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ -#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \ +#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ + (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ + << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \ Setting */ /** @@ -628,9 +634,9 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \ +#define MXC_F_GPIO_WAKE_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \ Mask */ /** @@ -639,32 +645,31 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \ +#define MXC_F_GPIO_WAKE_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \ Mask */ /** * GPIO Interrupt Dual Edge Mode Register. Each bit in this register * selects dual edge mode for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \ 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< \ - INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - Mask \ - */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< \ + INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ + Mask \ + */ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< \ INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ Setting */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ @@ -676,29 +681,28 @@ typedef enum { * GPIO Input Mode Config 1. Each bit in this register enables the * weak pull-up for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \ 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< \ - PAD_CFG1_GPIO_PAD_CFG1 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< \ + PAD_CFG1_GPIO_PAD_CFG1 \ + Mask */ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ PAD_CFG1_GPIO_PAD_CFG1_PU \ Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ @@ -710,29 +714,28 @@ typedef enum { * GPIO Input Mode Config 2. Each bit in this register enables the * weak pull-up for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \ 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< \ - PAD_CFG2_GPIO_PAD_CFG2 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< \ + PAD_CFG2_GPIO_PAD_CFG2 \ + Mask */ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ PAD_CFG2_GPIO_PAD_CFG2_PU \ Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ @@ -746,19 +749,22 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ -#define MXC_F_GPIO_EN1_GPIO_EN1 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ -#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ +#define MXC_F_GPIO_EN1_GPIO_EN1 \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< \ + EN1_GPIO_EN1 \ + Mask */ +#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ -#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ + (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< \ + EN1_GPIO_EN1_PRIMARY \ + Setting \ + */ +#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \ +#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ + (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \ */ /** @@ -767,9 +773,10 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ -#define MXC_F_GPIO_EN1_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_EN1_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< \ + EN1_SET_ALL \ + Mask */ /** * GPIO Alternate Function Clear. Writing a 1 to one or more bits in @@ -777,9 +784,10 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ -#define MXC_F_GPIO_EN1_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_EN1_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< \ + EN1_CLR_ALL \ + Mask */ /** * GPIO Alternate Function Enable Register. Each bit in this register @@ -787,19 +795,22 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ -#define MXC_F_GPIO_EN2_GPIO_EN2 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ -#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ +#define MXC_F_GPIO_EN2_GPIO_EN2 \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< \ + EN2_GPIO_EN2 \ + Mask */ +#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ -#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ + (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< \ + EN2_GPIO_EN2_PRIMARY \ + Setting \ + */ +#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \ +#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ + (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \ */ /** @@ -808,9 +819,10 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ -#define MXC_F_GPIO_EN2_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_EN2_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< \ + EN2_SET_ALL \ + Mask */ /** * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits @@ -818,9 +830,10 @@ typedef enum { * without affecting other bits in that register. */ #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ -#define MXC_F_GPIO_EN2_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_EN2_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< \ + EN2_CLR_ALL \ + Mask */ /** * GPIO Drive Strength Register. Each bit in this register selects @@ -828,13 +841,13 @@ typedef enum { * Datasheet for sink/source current of GPIO pins in each mode. */ #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ -#define MXC_F_GPIO_DS_DS \ +#define MXC_F_GPIO_DS_DS \ ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ -#define MXC_S_GPIO_DS_DS_LD \ +#define MXC_S_GPIO_DS_DS_LD \ (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ -#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ -#define MXC_S_GPIO_DS_DS_HD \ +#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ +#define MXC_S_GPIO_DS_DS_HD \ (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ /** @@ -844,23 +857,23 @@ typedef enum { */ #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ #define MXC_F_GPIO_DS1_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask \ + */ /** * GPIO Pull Select Mode. */ #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ -#define MXC_F_GPIO_PS_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \ +#define MXC_F_GPIO_PS_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \ */ /** * GPIO Voltage Select. */ #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ -#define MXC_F_GPIO_VSSEL_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ +#define MXC_F_GPIO_VSSEL_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL \ + Mask */ #endif /* _GPIO_REGS_H_ */ -- cgit v1.2.1 From a8d6d30b2aed577cdce063075f3ee75314d878d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:29 -0600 Subject: chip/it83xx/peci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I983048cd3d71bb541806724209452ace9ff43385 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729214 Reviewed-by: Jeremy Bettis --- chip/it83xx/peci.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/chip/it83xx/peci.c b/chip/it83xx/peci.c index 07336eaaf6..d485b3fccf 100644 --- a/chip/it83xx/peci.c +++ b/chip/it83xx/peci.c @@ -14,22 +14,20 @@ #include "task.h" enum peci_status { - PECI_STATUS_NO_ERR = 0x00, - PECI_STATUS_HOBY = 0x01, - PECI_STATUS_FINISH = 0x02, - PECI_STATUS_RD_FCS_ERR = 0x04, - PECI_STATUS_WR_FCS_ERR = 0x08, - PECI_STATUS_EXTERR = 0x20, - PECI_STATUS_BUSERR = 0x40, - PECI_STATUS_RCV_ERRCODE = 0x80, - PECI_STATUS_ERR_NEED_RST = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR), - PECI_STATUS_ANY_ERR = (PECI_STATUS_RCV_ERRCODE | - PECI_STATUS_BUSERR | - PECI_STATUS_EXTERR | - PECI_STATUS_WR_FCS_ERR | - PECI_STATUS_RD_FCS_ERR), - PECI_STATUS_ANY_BIT = 0xFE, - PECI_STATUS_TIMEOUT = 0xFF, + PECI_STATUS_NO_ERR = 0x00, + PECI_STATUS_HOBY = 0x01, + PECI_STATUS_FINISH = 0x02, + PECI_STATUS_RD_FCS_ERR = 0x04, + PECI_STATUS_WR_FCS_ERR = 0x08, + PECI_STATUS_EXTERR = 0x20, + PECI_STATUS_BUSERR = 0x40, + PECI_STATUS_RCV_ERRCODE = 0x80, + PECI_STATUS_ERR_NEED_RST = (PECI_STATUS_BUSERR | PECI_STATUS_EXTERR), + PECI_STATUS_ANY_ERR = (PECI_STATUS_RCV_ERRCODE | PECI_STATUS_BUSERR | + PECI_STATUS_EXTERR | PECI_STATUS_WR_FCS_ERR | + PECI_STATUS_RD_FCS_ERR), + PECI_STATUS_ANY_BIT = 0xFE, + PECI_STATUS_TIMEOUT = 0xFF, }; static task_id_t peci_current_task; @@ -106,10 +104,9 @@ int peci_transaction(struct peci_data *peci) IT83XX_PECI_HOWRLR = 0x00; } else { if ((peci->cmd_code == PECI_CMD_WR_PKG_CFG) || - (peci->cmd_code == PECI_CMD_WR_IAMSR) || - (peci->cmd_code == PECI_CMD_WR_PCI_CFG) || - (peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) { - + (peci->cmd_code == PECI_CMD_WR_IAMSR) || + (peci->cmd_code == PECI_CMD_WR_PCI_CFG) || + (peci->cmd_code == PECI_CMD_WR_PCI_CFG_LOCAL)) { /* write length include Cmd Code + AW FCS */ IT83XX_PECI_HOWRLR = peci->w_len + 2; @@ -157,17 +154,14 @@ int peci_transaction(struct peci_data *peci) peci_current_task = TASK_ID_INVALID; if (index < peci->timeout_us) { - status = IT83XX_PECI_HOSTAR; /* any error */ if (IT83XX_PECI_HOSTAR & PECI_STATUS_ANY_ERR) { - if (IT83XX_PECI_HOSTAR & PECI_STATUS_ERR_NEED_RST) peci_reset(); } else if (IT83XX_PECI_HOSTAR & PECI_STATUS_FINISH) { - /* The read data field of the PECI protocol. */ for (index = 0x00; index < peci->r_len; index++) peci->r_buf[index] = IT83XX_PECI_HORDDR; -- cgit v1.2.1 From a6932d6bf062086f296b024a89a16459c89d9f41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:14 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e1.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4870c2d0a8c6ec93bc6ab2e4cabc584f740131a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730556 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e1.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e1.c b/test/usb_tcpmv2_td_pd_src3_e1.c index 751e354b11..41c839fa87 100644 --- a/test/usb_tcpmv2_td_pd_src3_e1.c +++ b/test/usb_tcpmv2_td_pd_src3_e1.c @@ -69,21 +69,17 @@ int test_td_pd_src3_e1(void) * 5. Message Type field = 00001b (Source Capabilities) * 6. Extended field = 0b */ - TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, - PD_DATA_SOURCE_CAP, - data, - sizeof(data), - &msg_len, - 0), + TEST_EQ(verify_tcpci_tx_with_data(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, + data, sizeof(data), &msg_len, 0), EC_SUCCESS, "%d"); TEST_GE(msg_len, HEADER_BYTE_CNT, "%d"); header = UINT16_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET); pd_cnt = PD_HEADER_CNT(header); TEST_NE(pd_cnt, 0, "%d"); - TEST_EQ(msg_len, HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT + - (pd_cnt * PDO_BYTE_CNT), "%d"); + TEST_EQ(msg_len, + HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + (pd_cnt * PDO_BYTE_CNT), + "%d"); TEST_EQ(PD_HEADER_PROLE(header), PD_ROLE_SOURCE, "%d"); TEST_EQ(PD_HEADER_REV(header), REVISION_3, "%d"); TEST_EQ(PD_HEADER_DROLE(header), PD_ROLE_DFP, "%d"); @@ -96,8 +92,8 @@ int test_td_pd_src3_e1(void) * 2. Voltage field = 100 (5 V) * 3. Bits 23..22 = 000b (Reserved) */ - pdo = UINT32_FROM_BYTE_ARRAY_LE(data, HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT); + pdo = UINT32_FROM_BYTE_ARRAY_LE(data, + HEADER_BYTE_OFFSET + HEADER_BYTE_CNT); type = pdo & PDO_TYPE_MASK; TEST_EQ(type, PDO_TYPE_FIXED, "%d"); @@ -135,15 +131,14 @@ int test_td_pd_src3_e1(void) int offset; uint32_t voltage; - offset = HEADER_BYTE_OFFSET + - HEADER_BYTE_CNT + + offset = HEADER_BYTE_OFFSET + HEADER_BYTE_CNT + (i * PDO_BYTE_CNT); pdo = UINT32_FROM_BYTE_ARRAY_LE(data, offset); type = pdo & PDO_TYPE_MASK; if (type == PDO_TYPE_FIXED) { - TEST_EQ(pdo & (GENMASK(28, 26)|GENMASK(24, 22)), - 0, "%d"); + TEST_EQ(pdo & (GENMASK(28, 26) | GENMASK(24, 22)), 0, + "%d"); TEST_EQ(last_battery_voltage, 0, "%d"); TEST_EQ(last_variable_voltage, 0, "%d"); TEST_EQ(last_programmable_voltage, 0, "%d"); -- cgit v1.2.1 From 1566c1aaea78f122794b13c4df4e31441ae88423 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:42 -0600 Subject: board/rammus/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23f19acfba9febeaa20652d361cf313fbb838baa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728876 Reviewed-by: Jeremy Bettis --- board/rammus/board.h | 104 +++++++++++++++++++++++++-------------------------- 1 file changed, 50 insertions(+), 54 deletions(-) diff --git a/board/rammus/board.h b/board/rammus/board.h index e044148401..a3cbfa6122 100644 --- a/board/rammus/board.h +++ b/board/rammus/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -29,7 +29,7 @@ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER #define CONFIG_KEYBOARD_COL2_INVERTED -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_LED_COMMON #define CONFIG_LID_SWITCH @@ -92,8 +92,8 @@ #define CONFIG_CMD_CHARGER_ADC_AMON_BMON #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON @@ -140,7 +140,7 @@ /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 1024 #define CONFIG_TABLET_MODE @@ -181,45 +181,45 @@ #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_MP2949 NPCX_I2C_PORT2 -#define I2C_PORT_GYRO NPCX_I2C_PORT3 -#define I2C_PORT_ACCEL I2C_PORT_GYRO -#define I2C_PORT_THERMAL I2C_PORT_PMIC +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT1 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_MP2949 NPCX_I2C_PORT2 +#define I2C_PORT_GYRO NPCX_I2C_PORT3 +#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_THERMAL I2C_PORT_PMIC /* I2C addresses */ -#define I2C_ADDR_BD99992_FLAGS 0x30 -#define I2C_ADDR_MP2949_FLAGS 0x20 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Rename GPIOs */ -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH -#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L -#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_PWR_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN -#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK -#define GPIO_ENABLE_BACKLIGHT GPIO_BL_DISABLE_L -#define GPIO_CPU_PROCHOT GPIO_PCH_PROCHOT -#define GPIO_PCH_PWRBTN_L GPIO_PCH_PWR_BTN_L -#define GPIO_EC_PLATFORM_RST GPIO_PLATFORM_RST -#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC -#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT -#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_SUS_L GPIO_SLP_SUS_L_PCH +#define GPIO_PG_EC_RSMRST_ODL GPIO_ROP_EC_RSMRST_L +#define GPIO_PMIC_DPWROK GPIO_ROP_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_PWR_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN +#define GPIO_AC_PRESENT GPIO_ROP_EC_ACOK +#define GPIO_ENABLE_BACKLIGHT GPIO_BL_DISABLE_L +#define GPIO_CPU_PROCHOT GPIO_PCH_PROCHOT +#define GPIO_PCH_PWRBTN_L GPIO_PCH_PWR_BTN_L +#define GPIO_EC_PLATFORM_RST GPIO_PLATFORM_RST +#define GPIO_PMIC_SLP_SUS_L GPIO_SLP_SUS_L_PMIC +#define GPIO_USB_C0_5V_EN GPIO_EN_USB_C0_5V_OUT +#define GPIO_USB_C1_5V_EN GPIO_EN_USB_C1_5V_OUT #ifndef __ASSEMBLER__ @@ -227,11 +227,11 @@ #include "registers.h" enum temp_sensor_id { - TEMP_SENSOR_BATTERY, /* Smart Battery Temperature */ - TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ - TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ + TEMP_SENSOR_BATTERY, /* Smart Battery Temperature */ + TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ TEMP_SENSOR_COUNT }; @@ -248,11 +248,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, @@ -265,16 +261,16 @@ enum pwm_channel { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From 453a24c378af98d3d69e4183dae94c62c401524b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:06 -0600 Subject: board/sasuke/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib44ff2f9267bc1def4214ac07fc2e71497237963 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728886 Reviewed-by: Jeremy Bettis --- board/sasuke/board.c | 323 ++++++++++++++++++++++++--------------------------- 1 file changed, 152 insertions(+), 171 deletions(-) diff --git a/board/sasuke/board.c b/board/sasuke/board.c index 830c92eb47..415e92effc 100644 --- a/board/sasuke/board.c +++ b/board/sasuke/board.c @@ -42,8 +42,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -83,7 +83,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -118,7 +117,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) { @@ -164,18 +162,17 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - static int board_id = -1; static int mux_c1 = SSFC_USB_SS_MUX_DEFAULT; @@ -191,16 +188,17 @@ void board_init(void) if (get_cbi_fw_config_db() == DB_1A_HDMI) { /* Disable i2c on HDMI pins */ - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0); - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, + 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, + 0); /* Set HDMI and sub-rail enables to output */ gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, chipset_in_state(CHIPSET_STATE_ON) ? - GPIO_ODR_LOW : GPIO_ODR_HIGH); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + GPIO_ODR_LOW : + GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -209,8 +207,7 @@ void board_init(void) gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL); } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT); /* Enable C1 interrupts */ gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL); @@ -229,8 +226,9 @@ void board_init(void) board_id = val; if (board_id == 2) { nb7v904m_lpm_disable = 1; - nb7v904m_set_aux_ch_switch(&usbc0_retimer, - NB7V904M_AUX_CH_FLIPPED); + nb7v904m_set_aux_ch_switch( + &usbc0_retimer, + NB7V904M_AUX_CH_FLIPPED); } } } @@ -238,9 +236,7 @@ void board_init(void) mux_c1 = get_cbi_ssfc_usb_ss_mux(); if (mux_c1 == SSFC_USB_SS_MUX_PS8743) - memcpy(&usb_muxes[1], - &usbmux_ps8743, - sizeof(struct usb_mux)); + memcpy(&usb_muxes[1], &usbmux_ps8743, sizeof(struct usb_mux)); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -302,10 +298,9 @@ __override void board_power_5v_enable(int enable) gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } else { if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", + enable ? "en" : "dis"); } - } __override uint8_t board_get_usb_pd_port_count(void) @@ -330,13 +325,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -400,8 +393,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -421,9 +414,8 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) raa489000_set_output_current(port, rp); } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -489,9 +481,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; static int board_nb7v904m_mux_set_c0(const struct usb_mux *me, - mux_state_t mux_state); + mux_state_t mux_state); static int board_nb7v904m_mux_set(const struct usb_mux *me, - mux_state_t mux_state); + mux_state_t mux_state); static int ps8743_tune_mux(const struct usb_mux *me); const struct usb_mux usbc0_retimer = { @@ -536,16 +528,15 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB Mux C1 : board_init of PS8743 */ static int ps8743_tune_mux(const struct usb_mux *me) { - ps8743_tune_usb_eq(me, - PS8743_USB_EQ_TX_3_6_DB, - PS8743_USB_EQ_RX_16_0_DB); + ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, + PS8743_USB_EQ_RX_16_0_DB); return EC_SUCCESS; } /* USB Mux C0 */ static int board_nb7v904m_mux_set_c0(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED); @@ -563,79 +554,74 @@ static int board_nb7v904m_mux_set_c0(const struct usb_mux *me, if (mux_state & USB_PD_MUX_DP_ENABLED) { /* USB with DP */ if (flipped) { - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_10_DB, - NB7V904M_CH_B_EQ_0_DB, - NB7V904M_CH_C_EQ_2_DB, - NB7V904M_CH_D_EQ_2_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_1P5_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_C); - } - else { - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_2_DB, - NB7V904M_CH_B_EQ_2_DB, - NB7V904M_CH_C_EQ_0_DB, - NB7V904M_CH_D_EQ_10_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_1P5_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A); + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_10_DB, + NB7V904M_CH_B_EQ_0_DB, + NB7V904M_CH_C_EQ_2_DB, + NB7V904M_CH_D_EQ_2_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_1P5_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_C, + NB7V904M_LOSS_PROFILE_C); + } else { + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_2_DB, + NB7V904M_CH_B_EQ_2_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_10_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_1P5_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_C, + NB7V904M_LOSS_PROFILE_C, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); } } else { /* USB only */ if (board_id == 2) - rv |= nb7v904m_set_aux_ch_switch(me, - NB7V904M_AUX_CH_FLIPPED); + rv |= nb7v904m_set_aux_ch_switch( + me, NB7V904M_AUX_CH_FLIPPED); rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_10_DB, - NB7V904M_CH_B_EQ_0_DB, - NB7V904M_CH_C_EQ_0_DB, - NB7V904M_CH_D_EQ_10_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_1P5_DB, - NB7V904M_CH_C_GAIN_1P5_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A); + NB7V904M_CH_A_EQ_10_DB, + NB7V904M_CH_B_EQ_0_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_10_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_1P5_DB, + NB7V904M_CH_C_GAIN_1P5_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); } } else if (mux_state & USB_PD_MUX_DP_ENABLED) { /* 4 lanes DP */ - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_2_DB, - NB7V904M_CH_B_EQ_2_DB, - NB7V904M_CH_C_EQ_2_DB, - NB7V904M_CH_D_EQ_2_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_C, - NB7V904M_LOSS_PROFILE_C); + rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_2_DB, + NB7V904M_CH_B_EQ_2_DB, + NB7V904M_CH_C_EQ_2_DB, + NB7V904M_CH_D_EQ_2_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C, + NB7V904M_LOSS_PROFILE_C, NB7V904M_LOSS_PROFILE_C); } return rv; @@ -643,7 +629,7 @@ static int board_nb7v904m_mux_set_c0(const struct usb_mux *me, /* USB Mux */ static int board_nb7v904m_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED); @@ -652,75 +638,70 @@ static int board_nb7v904m_mux_set(const struct usb_mux *me, /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { if (flipped) { - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_10_DB, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_D_EQ_4_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_ALL_SKIP_GAIN, - NB7V904M_CH_B_GAIN_3P5_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_ALL_SKIP_GAIN); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D); - } - else { - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_4_DB, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_D_EQ_10_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_ALL_SKIP_GAIN, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_3P5_DB, - NB7V904M_CH_ALL_SKIP_GAIN); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A); + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_10_DB, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_D_EQ_4_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_ALL_SKIP_GAIN, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_ALL_SKIP_GAIN); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D); + } else { + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_4_DB, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_D_EQ_10_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_ALL_SKIP_GAIN, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_3P5_DB, + NB7V904M_CH_ALL_SKIP_GAIN); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); } } else { /* USB only */ rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_10_DB, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_D_EQ_10_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_ALL_SKIP_GAIN, - NB7V904M_CH_B_GAIN_3P5_DB, - NB7V904M_CH_C_GAIN_3P5_DB, - NB7V904M_CH_ALL_SKIP_GAIN); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A); + NB7V904M_CH_A_EQ_10_DB, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_D_EQ_10_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_ALL_SKIP_GAIN, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_3P5_DB, + NB7V904M_CH_ALL_SKIP_GAIN); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); } } else if (mux_state & USB_PD_MUX_DP_ENABLED) { /* 4 lanes DP */ - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_4_DB, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_ALL_SKIP_EQ, - NB7V904M_CH_D_EQ_4_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_ALL_SKIP_GAIN, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_ALL_SKIP_GAIN); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D); + rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_4_DB, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_ALL_SKIP_EQ, + NB7V904M_CH_D_EQ_4_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_ALL_SKIP_GAIN, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_ALL_SKIP_GAIN); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D); } return rv; @@ -748,7 +729,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { + !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) @@ -778,8 +759,8 @@ static const struct ec_response_keybd_config keybd1 = { }, /* No function keys, no numeric keypad and no screenlock key */ }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { /* * Future boards should use fw_config if needed. -- cgit v1.2.1 From 635b0fa594a13d37d3d8be58852eb24d1db2f746 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:15 -0600 Subject: driver/temp_sensor/thermistor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6fbbc2eae65af9be19eb1402d746c606f86d2e46 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729876 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/thermistor.c | 138 ++++++++++++++++++++-------------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/driver/temp_sensor/thermistor.c b/driver/temp_sensor/thermistor.c index bef10416b6..4363167aa1 100644 --- a/driver/temp_sensor/thermistor.c +++ b/driver/temp_sensor/thermistor.c @@ -15,7 +15,7 @@ #include "util.h" int thermistor_linear_interpolate(uint16_t mv, - const struct thermistor_info *info) + const struct thermistor_info *info) { const struct thermistor_data_pair *data = info->data; int v_high = 0, v_low = 0, t_low, t_high, num_steps; @@ -66,7 +66,7 @@ int thermistor_linear_interpolate(uint16_t mv, return t_low + num_steps; } -#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) || \ +#if defined(CONFIG_STEINHART_HART_3V3_51K1_47K_4050B) || \ defined(CONFIG_STEINHART_HART_3V3_13K7_47K_4050B) || \ defined(CONFIG_STEINHART_HART_6V0_51K1_47K_4050B) || \ defined(CONFIG_STEINHART_HART_3V0_22K6_47K_4050B) || \ @@ -103,19 +103,19 @@ int thermistor_get_temperature(int idx_adc, int *temp_ptr, */ #define THERMISTOR_SCALING_FACTOR_51_47 11 static const struct thermistor_data_pair thermistor_data_51_47[] = { - { 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0 }, - { 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10 }, - { 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20 }, - { 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30 }, - { 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40 }, - { 802 / THERMISTOR_SCALING_FACTOR_51_47, 50 }, - { 593 / THERMISTOR_SCALING_FACTOR_51_47, 60 }, - { 436 / THERMISTOR_SCALING_FACTOR_51_47, 70 }, - { 321 / THERMISTOR_SCALING_FACTOR_51_47, 80 }, - { 276 / THERMISTOR_SCALING_FACTOR_51_47, 85 }, - { 237 / THERMISTOR_SCALING_FACTOR_51_47, 90 }, - { 204 / THERMISTOR_SCALING_FACTOR_51_47, 95 }, - { 177 / THERMISTOR_SCALING_FACTOR_51_47, 100 }, + { 2484 / THERMISTOR_SCALING_FACTOR_51_47, 0 }, + { 2142 / THERMISTOR_SCALING_FACTOR_51_47, 10 }, + { 1767 / THERMISTOR_SCALING_FACTOR_51_47, 20 }, + { 1400 / THERMISTOR_SCALING_FACTOR_51_47, 30 }, + { 1072 / THERMISTOR_SCALING_FACTOR_51_47, 40 }, + { 802 / THERMISTOR_SCALING_FACTOR_51_47, 50 }, + { 593 / THERMISTOR_SCALING_FACTOR_51_47, 60 }, + { 436 / THERMISTOR_SCALING_FACTOR_51_47, 70 }, + { 321 / THERMISTOR_SCALING_FACTOR_51_47, 80 }, + { 276 / THERMISTOR_SCALING_FACTOR_51_47, 85 }, + { 237 / THERMISTOR_SCALING_FACTOR_51_47, 90 }, + { 204 / THERMISTOR_SCALING_FACTOR_51_47, 95 }, + { 177 / THERMISTOR_SCALING_FACTOR_51_47, 100 }, }; static const struct thermistor_info thermistor_info_51_47 = { @@ -127,7 +127,7 @@ static const struct thermistor_info thermistor_info_51_47 = { int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr) { return thermistor_get_temperature(idx_adc, temp_ptr, - &thermistor_info_51_47); + &thermistor_info_51_47); } #endif /* CONFIG_STEINHART_HART_3V3_51K1_47K_4050B */ @@ -139,19 +139,19 @@ int get_temp_3v3_51k1_47k_4050b(int idx_adc, int *temp_ptr) */ #define THERMISTOR_SCALING_FACTOR_13_47 13 static const struct thermistor_data_pair thermistor_data_13_47[] = { - { 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0 }, - { 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10 }, - { 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20 }, - { 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30 }, - { 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40 }, - { 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50 }, - { 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60 }, - { 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70 }, - { 947 / THERMISTOR_SCALING_FACTOR_13_47, 80 }, - { 839 / THERMISTOR_SCALING_FACTOR_13_47, 85 }, - { 741 / THERMISTOR_SCALING_FACTOR_13_47, 90 }, - { 653 / THERMISTOR_SCALING_FACTOR_13_47, 95 }, - { 576 / THERMISTOR_SCALING_FACTOR_13_47, 100 }, + { 3033 / THERMISTOR_SCALING_FACTOR_13_47, 0 }, + { 2882 / THERMISTOR_SCALING_FACTOR_13_47, 10 }, + { 2677 / THERMISTOR_SCALING_FACTOR_13_47, 20 }, + { 2420 / THERMISTOR_SCALING_FACTOR_13_47, 30 }, + { 2119 / THERMISTOR_SCALING_FACTOR_13_47, 40 }, + { 1799 / THERMISTOR_SCALING_FACTOR_13_47, 50 }, + { 1485 / THERMISTOR_SCALING_FACTOR_13_47, 60 }, + { 1197 / THERMISTOR_SCALING_FACTOR_13_47, 70 }, + { 947 / THERMISTOR_SCALING_FACTOR_13_47, 80 }, + { 839 / THERMISTOR_SCALING_FACTOR_13_47, 85 }, + { 741 / THERMISTOR_SCALING_FACTOR_13_47, 90 }, + { 653 / THERMISTOR_SCALING_FACTOR_13_47, 95 }, + { 576 / THERMISTOR_SCALING_FACTOR_13_47, 100 }, }; static const struct thermistor_info thermistor_info_13_47 = { @@ -163,7 +163,7 @@ static const struct thermistor_info thermistor_info_13_47 = { int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr) { return thermistor_get_temperature(idx_adc, temp_ptr, - &thermistor_info_13_47); + &thermistor_info_13_47); } #endif /* CONFIG_STEINHART_HART_3V3_13K7_47K_4050B */ @@ -175,19 +175,19 @@ int get_temp_3v3_13k7_47k_4050b(int idx_adc, int *temp_ptr) */ #define THERMISTOR_SCALING_FACTOR_6V0_51_47 18 static const struct thermistor_data_pair thermistor_data_6v0_51_47[] = { - { 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0 }, - { 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10 }, - { 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20 }, - { 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30 }, - { 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40 }, - { 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50 }, - { 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60 }, - { 794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70 }, - { 584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80 }, - { 502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85 }, - { 432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90 }, - { 372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95 }, - { 322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 }, + { 4517 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 0 }, + { 3895 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 10 }, + { 3214 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 20 }, + { 2546 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 30 }, + { 1950 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 40 }, + { 1459 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 50 }, + { 1079 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 60 }, + { 794 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 70 }, + { 584 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 80 }, + { 502 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 85 }, + { 432 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 90 }, + { 372 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 95 }, + { 322 / THERMISTOR_SCALING_FACTOR_6V0_51_47, 100 }, }; static const struct thermistor_info thermistor_info_6v0_51_47 = { @@ -199,7 +199,7 @@ static const struct thermistor_info thermistor_info_6v0_51_47 = { int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr) { return thermistor_get_temperature(idx_adc, temp_ptr, - &thermistor_info_6v0_51_47); + &thermistor_info_6v0_51_47); } #endif /* CONFIG_STEINHART_HART_6V0_51K1_47K_4050B */ @@ -211,19 +211,19 @@ int get_temp_6v0_51k1_47k_4050b(int idx_adc, int *temp_ptr) */ #define THERMISTOR_SCALING_FACTOR_22_47 11 static const struct thermistor_data_pair thermistor_data_22_47[] = { - { 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0 }, - { 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10 }, - { 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20 }, - { 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30 }, - { 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40 }, - { 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50 }, - { 994 / THERMISTOR_SCALING_FACTOR_22_47, 60 }, - { 769 / THERMISTOR_SCALING_FACTOR_22_47, 70 }, - { 588 / THERMISTOR_SCALING_FACTOR_22_47, 80 }, - { 513 / THERMISTOR_SCALING_FACTOR_22_47, 85 }, - { 448 / THERMISTOR_SCALING_FACTOR_22_47, 90 }, - { 390 / THERMISTOR_SCALING_FACTOR_22_47, 95 }, - { 340 / THERMISTOR_SCALING_FACTOR_22_47, 100 }, + { 2619 / THERMISTOR_SCALING_FACTOR_22_47, 0 }, + { 2421 / THERMISTOR_SCALING_FACTOR_22_47, 10 }, + { 2168 / THERMISTOR_SCALING_FACTOR_22_47, 20 }, + { 1875 / THERMISTOR_SCALING_FACTOR_22_47, 30 }, + { 1563 / THERMISTOR_SCALING_FACTOR_22_47, 40 }, + { 1262 / THERMISTOR_SCALING_FACTOR_22_47, 50 }, + { 994 / THERMISTOR_SCALING_FACTOR_22_47, 60 }, + { 769 / THERMISTOR_SCALING_FACTOR_22_47, 70 }, + { 588 / THERMISTOR_SCALING_FACTOR_22_47, 80 }, + { 513 / THERMISTOR_SCALING_FACTOR_22_47, 85 }, + { 448 / THERMISTOR_SCALING_FACTOR_22_47, 90 }, + { 390 / THERMISTOR_SCALING_FACTOR_22_47, 95 }, + { 340 / THERMISTOR_SCALING_FACTOR_22_47, 100 }, }; static const struct thermistor_info thermistor_info_22_47 = { @@ -235,7 +235,7 @@ static const struct thermistor_info thermistor_info_22_47 = { int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr) { return thermistor_get_temperature(idx_adc, temp_ptr, - &thermistor_info_22_47); + &thermistor_info_22_47); } #endif /* CONFIG_STEINHART_HART_3V0_22K6_47K_4050B */ @@ -247,16 +247,16 @@ int get_temp_3v0_22k6_47k_4050b(int idx_adc, int *temp_ptr) */ #define THERMISTOR_SCALING_FACTOR_31_47 11 static const struct thermistor_data_pair thermistor_data_31_47[] = { - { 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0 }, - { 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10 }, - { 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20 }, - { 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30 }, - { 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50 }, - { 878 / THERMISTOR_SCALING_FACTOR_31_47, 60 }, - { 665 / THERMISTOR_SCALING_FACTOR_31_47, 70 }, - { 500 / THERMISTOR_SCALING_FACTOR_31_47, 80 }, - { 375 / THERMISTOR_SCALING_FACTOR_31_47, 90 }, - { 282 / THERMISTOR_SCALING_FACTOR_31_47, 100 }, + { 2753 / THERMISTOR_SCALING_FACTOR_31_47, 0 }, + { 2487 / THERMISTOR_SCALING_FACTOR_31_47, 10 }, + { 2165 / THERMISTOR_SCALING_FACTOR_31_47, 20 }, + { 1813 / THERMISTOR_SCALING_FACTOR_31_47, 30 }, + { 1145 / THERMISTOR_SCALING_FACTOR_31_47, 50 }, + { 878 / THERMISTOR_SCALING_FACTOR_31_47, 60 }, + { 665 / THERMISTOR_SCALING_FACTOR_31_47, 70 }, + { 500 / THERMISTOR_SCALING_FACTOR_31_47, 80 }, + { 375 / THERMISTOR_SCALING_FACTOR_31_47, 90 }, + { 282 / THERMISTOR_SCALING_FACTOR_31_47, 100 }, }; static const struct thermistor_info thermistor_info_31_47 = { @@ -268,6 +268,6 @@ static const struct thermistor_info thermistor_info_31_47 = { int get_temp_3v3_30k9_47k_4050b(int idx_adc, int *temp_ptr) { return thermistor_get_temperature(idx_adc, temp_ptr, - &thermistor_info_31_47); + &thermistor_info_31_47); } #endif /* CONFIG_STEINHART_HART_3V3_30K9_47K_4050B */ -- cgit v1.2.1 From 7f366e63e05202cfba1ec6349bad76289de770b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:50 -0600 Subject: common/base_state.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8ec4aa62820459e62ad88ee404865af6809bad15 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729588 Reviewed-by: Jeremy Bettis --- common/base_state.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/base_state.c b/common/base_state.c index 543329fe29..6d0704e0ba 100644 --- a/common/base_state.c +++ b/common/base_state.c @@ -8,7 +8,7 @@ #include "host_command.h" #include "hooks.h" -#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args) #ifdef CONFIG_BASE_ATTACHED_SWITCH /* 1: base attached, 0: otherwise */ @@ -47,10 +47,9 @@ static int command_setbasestate(int argc, char **argv) return EC_ERROR_PARAM1; return EC_SUCCESS; - } -DECLARE_CONSOLE_COMMAND(basestate, command_setbasestate, - "[attach | detach | reset]", +DECLARE_CONSOLE_COMMAND( + basestate, command_setbasestate, "[attach | detach | reset]", "Manually force base state to attached, detached or reset."); static enum ec_status hostcmd_setbasestate(struct host_cmd_handler_args *args) -- cgit v1.2.1 From 8e736c8bf871740e36fbdb76cc93e2dadbc40d0a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:22 -0600 Subject: board/beadrix/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I149071e6ed3fddca61111cf4c3f6d519d4ca3ccd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728026 Reviewed-by: Jeremy Bettis --- board/beadrix/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/beadrix/usb_pd_policy.c b/board/beadrix/usb_pd_policy.c index a50ef8cfa9..fb0f60802f 100644 --- a/board/beadrix/usb_pd_policy.c +++ b/board/beadrix/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 9463d00ee62f6f4643fe34af1ff4d1ed8eb78597 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:03 -0600 Subject: board/brask/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idbabce59cc931401a61686c4fb4331d37f2bfbd9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728094 Reviewed-by: Jeremy Bettis --- board/brask/led.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/brask/led.c b/board/brask/led.c index 68dffb67a7..c6264ee906 100644 --- a/board/brask/led.c +++ b/board/brask/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* * When pulsing is enabled, brightness is incremented by every @@ -231,8 +231,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|green|off|alert|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|green|off|alert|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -250,10 +249,10 @@ int led_set_brightness(enum ec_led_id id, const uint8_t *brightness) else return set_color(id, LED_OFF, 0); } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - /* Blink alert if insufficient power per system_can_boot_ap(). */ + /* Blink alert if insufficient power per system_can_boot_ap(). */ int insufficient_power = (charge_ma * charge_mv) < (CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON * 1000); -- cgit v1.2.1 From 6306a201e933e42c7816da5c85256450bb33aae7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:32 -0600 Subject: board/mithrax/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idceb6e293ab19acdc28367a269c52184de450ed6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728459 Reviewed-by: Jeremy Bettis --- board/mithrax/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/mithrax/fw_config.c b/board/mithrax/fw_config.c index 6985059d50..d0f7d084ee 100644 --- a/board/mithrax/fw_config.c +++ b/board/mithrax/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union mithrax_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From c7b0bca6e1f50f7f14beda9b10ab854ebcf74bcc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:59 -0600 Subject: zephyr/subsys/ap_pwrseq/signal_vw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icdde12cc19ff4546962a418ba7048d771e044f5e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730933 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/signal_vw.c | 54 +++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/signal_vw.c b/zephyr/subsys/ap_pwrseq/signal_vw.c index 53719a9c4f..d2c3c0a8d1 100644 --- a/zephyr/subsys/ap_pwrseq/signal_vw.c +++ b/zephyr/subsys/ap_pwrseq/signal_vw.c @@ -9,31 +9,30 @@ #include "signal_vw.h" -#define MY_COMPAT intel_ap_pwrseq_vw +#define MY_COMPAT intel_ap_pwrseq_vw #if HAS_VW_SIGNALS LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); -#define INIT_ESPI_SIGNAL(id) \ -{ \ - .espi_signal = DT_STRING_UPPER_TOKEN(id, virtual_wire), \ - .signal = PWR_SIGNAL_ENUM(id), \ - .invert = DT_PROP(id, vw_invert), \ -}, +#define INIT_ESPI_SIGNAL(id) \ + { \ + .espi_signal = DT_STRING_UPPER_TOKEN(id, virtual_wire), \ + .signal = PWR_SIGNAL_ENUM(id), \ + .invert = DT_PROP(id, vw_invert), \ + }, /* * Struct containing the eSPI virtual wire config. */ struct vw_config { - uint8_t espi_signal; /* associated VW signal */ - uint8_t signal; /* power signal */ - bool invert; /* Invert the signal value */ + uint8_t espi_signal; /* associated VW signal */ + uint8_t signal; /* power signal */ + bool invert; /* Invert the signal value */ }; -const static struct vw_config vw_config[] = { -DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_ESPI_SIGNAL) -}; +const static struct vw_config vw_config[] = { DT_FOREACH_STATUS_OKAY( + MY_COMPAT, INIT_ESPI_SIGNAL) }; /* * Current signal value. @@ -49,16 +48,14 @@ static atomic_t signal_valid; BUILD_ASSERT(ARRAY_SIZE(vw_config) <= (sizeof(atomic_t) * 8)); -static void espi_handler(const struct device *dev, - struct espi_callback *cb, +static void espi_handler(const struct device *dev, struct espi_callback *cb, struct espi_event event) { - LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type, - event.evt_details, event.evt_data); + LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type, event.evt_details, + event.evt_data); switch (event.evt_type) { default: - __ASSERT(0, "ESPI unknown event type: %d", - event.evt_type); + __ASSERT(0, "ESPI unknown event type: %d", event.evt_type); break; case ESPI_BUS_EVENT_CHANNEL_READY: @@ -72,9 +69,9 @@ static void espi_handler(const struct device *dev, case ESPI_BUS_EVENT_VWIRE_RECEIVED: for (int i = 0; i < ARRAY_SIZE(vw_config); i++) { if (event.evt_details == vw_config[i].espi_signal) { - bool value = vw_config[i].invert - ? !event.evt_data - : !!event.evt_data; + bool value = vw_config[i].invert ? + !event.evt_data : + !!event.evt_data; atomic_set_bit_to(&signal_data, i, value); atomic_set_bit(&signal_valid, i); @@ -104,7 +101,7 @@ void power_signal_vw_init(void) /* Configure handler for eSPI events */ espi_init_callback(&espi_cb, espi_handler, ESPI_BUS_EVENT_CHANNEL_READY | - ESPI_BUS_EVENT_VWIRE_RECEIVED); + ESPI_BUS_EVENT_VWIRE_RECEIVED); espi_add_callback(espi_dev, &espi_cb); /* * Check whether the bus is ready, and if so, @@ -115,14 +112,13 @@ void power_signal_vw_init(void) uint8_t vw_value; if (espi_receive_vwire(espi_dev, - vw_config[i].espi_signal, - &vw_value) == 0) { + vw_config[i].espi_signal, + &vw_value) == 0) { atomic_set_bit_to(&signal_data, i, - vw_config[i].invert - ? !vw_value - : !!vw_value); + vw_config[i].invert ? + !vw_value : + !!vw_value); atomic_set_bit(&signal_valid, i); - } } } -- cgit v1.2.1 From 2826384cf8484d2c19d6489e0da03e9585a0bc80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:27 -0600 Subject: board/baklava/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic939cdfa6a9034f97dea8a6921ce271305422626 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728017 Reviewed-by: Jeremy Bettis --- board/baklava/board.c | 82 +++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 45 deletions(-) diff --git a/board/baklava/board.c b/board/baklava/board.c index 12365e0ff6..c1972fc928 100644 --- a/board/baklava/board.c +++ b/board/baklava/board.c @@ -28,8 +28,8 @@ #include "usb_tc_sm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define QUICHE_PD_DEBUG_LVL 1 @@ -84,25 +84,25 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal) * signals is driven by USB/MST hub power sequencing requirements. */ const struct power_seq board_power_seq[] = { - {GPIO_EN_AC_JACK, 1, 20}, - {GPIO_EC_DFU_MUX_CTRL, 0, 0}, - {GPIO_EN_PP5000_A, 1, 31}, - {GPIO_MST_LP_CTL_L, 1, 0}, - {GPIO_EN_PP3300_B, 1, 1}, - {GPIO_EN_PP1100_A, 1, 100+30}, - {GPIO_EN_BB, 1, 30}, - {GPIO_EN_PP1050_A, 1, 30}, - {GPIO_EN_PP1200_A, 1, 20}, - {GPIO_EN_PP5000_C, 1, 20}, - {GPIO_EN_PP5000_HSPORT, 1, 31}, - {GPIO_EN_DP_SINK, 1, 80}, - {GPIO_MST_RST_L, 1, 61}, - {GPIO_EC_HUB2_RESET_L, 1, 41}, - {GPIO_EC_HUB3_RESET_L, 1, 33}, - {GPIO_DP_SINK_RESET, 1, 100}, - {GPIO_USBC_UF_RESET_L, 1, 33}, - {GPIO_DEMUX_DP_HDMI_PD_N, 1, 10}, - {GPIO_DEMUX_DP_HDMI_MODE, 1, 5}, + { GPIO_EN_AC_JACK, 1, 20 }, + { GPIO_EC_DFU_MUX_CTRL, 0, 0 }, + { GPIO_EN_PP5000_A, 1, 31 }, + { GPIO_MST_LP_CTL_L, 1, 0 }, + { GPIO_EN_PP3300_B, 1, 1 }, + { GPIO_EN_PP1100_A, 1, 100 + 30 }, + { GPIO_EN_BB, 1, 30 }, + { GPIO_EN_PP1050_A, 1, 30 }, + { GPIO_EN_PP1200_A, 1, 20 }, + { GPIO_EN_PP5000_C, 1, 20 }, + { GPIO_EN_PP5000_HSPORT, 1, 31 }, + { GPIO_EN_DP_SINK, 1, 80 }, + { GPIO_MST_RST_L, 1, 61 }, + { GPIO_EC_HUB2_RESET_L, 1, 41 }, + { GPIO_EC_HUB3_RESET_L, 1, 33 }, + { GPIO_DP_SINK_RESET, 1, 100 }, + { GPIO_USBC_UF_RESET_L, 1, 33 }, + { GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 }, + { GPIO_DEMUX_DP_HDMI_MODE, 1, 5 }, }; const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); @@ -110,13 +110,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Acer"), - [USB_STR_PRODUCT] = USB_STRING_DESC("D501"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Acer"), + [USB_STR_PRODUCT] = USB_STRING_DESC("D501"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -135,8 +135,7 @@ struct ppc_config_t ppc_chips[] = { * PS8802 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8822_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; @@ -167,16 +166,12 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_HOST] = { - .i2c_port = I2C_PORT_I2C1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_USB3] = { - .i2c_port = I2C_PORT_I2C3, - .i2c_addr_flags = SN5S330_ADDR1_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3, + .i2c_addr_flags = SN5S330_ADDR1_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -284,14 +279,13 @@ static void board_usb_tc_disconnect(void) if (port == USB_PD_PORT_HOST) gpio_set_level(GPIO_UFP_PLUG_DET, 1); } -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \ +DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, HOOK_PRIO_DEFAULT); #endif /* SECTION_IS_RW */ static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -356,6 +350,4 @@ static int command_dplane(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dplane, command_dplane, - "<2 | 4>", - "MST lane control."); +DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control."); -- cgit v1.2.1 From 0ed2fb872382b22ddfad186f0d0b495481bad55a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:39 -0600 Subject: core/host/stack_trace.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icc0bf3336285f2af5db00d254c68f732ac46eecc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729843 Reviewed-by: Jeremy Bettis --- core/host/stack_trace.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c index adef66dd44..54163c66ad 100644 --- a/core/host/stack_trace.c +++ b/core/host/stack_trace.c @@ -45,8 +45,8 @@ static void __attribute__((noinline)) _task_dump_trace_impl(int offset) for (i = 0; i < sz - offset; ++i) { fprintf(stderr, "#%-2d %s\n", i, messages[i]); /* %p is correct (as opposed to %pP) since this is the host */ - sprintf(buf, "addr2line %p -e %s", - trace[i + offset], __get_prog_name()); + sprintf(buf, "addr2line %p -e %s", trace[i + offset], + __get_prog_name()); file = popen(buf, "r"); if (file) { nb = fread(buf, 1, sizeof(buf) - 1, file); @@ -77,8 +77,8 @@ static void __attribute__((noinline)) _task_dump_trace_dispatch(int sig) } else if (in_interrupt_context()) { fprintf(stderr, "Stack trace of ISR:\n"); } else { - fprintf(stderr, "Stack trace of task %d (%s):\n", - running, task_get_name(running)); + fprintf(stderr, "Stack trace of task %d (%s):\n", running, + task_get_name(running)); } if (need_dispatch) { -- cgit v1.2.1 From b2310e14393c849db96332927580b78e45e5f8f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:32 -0600 Subject: chip/mt_scp/mt8195/video.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd1f55b0337c895680d6d9c06b623845baf7c854 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729357 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8195/video.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/mt_scp/mt8195/video.c b/chip/mt_scp/mt8195/video.c index cc62f051df..132df73fce 100644 --- a/chip/mt_scp/mt8195/video.c +++ b/chip/mt_scp/mt8195/video.c @@ -13,6 +13,6 @@ uint32_t video_get_enc_capability(void) uint32_t video_get_dec_capability(void) { - return VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE | - VDEC_CAP_VP8_FRAME | VDEC_CAP_VP9_FRAME; + return VDEC_CAP_MM21 | VDEC_CAP_H264_SLICE | VDEC_CAP_VP8_FRAME | + VDEC_CAP_VP9_FRAME; } -- cgit v1.2.1 From 2b5c6aacbac9c257e33d30b508eed19ff75f0c0d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:17 -0600 Subject: chip/npcx/registers-npcx9.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I924e94d9e6756b3a668d34f66981c99cd6091286 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729427 Reviewed-by: Jeremy Bettis --- chip/npcx/registers-npcx9.h | 723 ++++++++++++++++++++++---------------------- 1 file changed, 357 insertions(+), 366 deletions(-) diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h index 2f2a22405a..ac4609d40e 100644 --- a/chip/npcx/registers-npcx9.h +++ b/chip/npcx/registers-npcx9.h @@ -19,157 +19,155 @@ #endif /* NPCX-IRQ numbers */ -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 -#define NPCX_IRQ_PECI NPCX_IRQ_4 -#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5 -#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7 -#define NPCX_IRQ_SMB8 NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11 -#define NPCX_IRQ_GDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ_SMB7 NPCX_IRQ_16 -#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ_SMB5 NPCX_IRQ_19 -#define NPCX_IRQ_SMB6 NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 -#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28 -#define NPCX_I3C_MDMA5 NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ_UART2 NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ_UART3 NPCX_IRQ_38 -#define NPCX_IRQ_UART4 NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42 -#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45 -#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_WKINTG_2 NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 -#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 -#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 +#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 +#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 +#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 +#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 +#define NPCX_IRQ_PECI NPCX_IRQ_4 +#define NPCX_IRQ_MTC_WKINTD_0 NPCX_IRQ_5 +#define NPCX_IRQ_MTC NPCX_IRQ_MTC_WKINTD_0 +#define NPCX_IRQ_PORT80 NPCX_IRQ_6 +#define NPCX_IRQ_CR_SIN2_WKINTA_0 NPCX_IRQ_7 +#define NPCX_IRQ_SMB8 NPCX_IRQ_8 +#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 +#define NPCX_IRQ_ADC NPCX_IRQ_10 +#define NPCX_IRQ_WKINTE_0 NPCX_IRQ_11 +#define NPCX_IRQ_GDMA NPCX_IRQ_12 +#define NPCX_IRQ_SMB1 NPCX_IRQ_13 +#define NPCX_IRQ_SMB2 NPCX_IRQ_14 +#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 +#define NPCX_IRQ_SMB7 NPCX_IRQ_16 +#define NPCX_IRQ_ITIM32_3 NPCX_IRQ_17 +#define NPCX_IRQ_SHI NPCX_IRQ_18 +#define NPCX_IRQ_ESPI NPCX_IRQ_18 +#define NPCX_IRQ_SMB5 NPCX_IRQ_19 +#define NPCX_IRQ_SMB6 NPCX_IRQ_20 +#define NPCX_IRQ_PS2 NPCX_IRQ_21 +#define NPCX_IRQ22_NOUSED NPCX_IRQ_22 +#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 +#define NPCX_IRQ_SHM NPCX_IRQ_24 +#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 +#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 +#define NPCX_IRQ_ITIM32_2 NPCX_IRQ_27 +#define NPCX_IRQ_ITIM32_1 NPCX_IRQ_28 +#define NPCX_I3C_MDMA5 NPCX_IRQ_29 +#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 +#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 +#define NPCX_IRQ_UART2 NPCX_IRQ_32 +#define NPCX_IRQ_UART NPCX_IRQ_33 +#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 +#define NPCX_IRQ_WKINTF_0 NPCX_IRQ_35 +#define NPCX_IRQ_SMB3 NPCX_IRQ_36 +#define NPCX_IRQ_SMB4 NPCX_IRQ_37 +#define NPCX_IRQ_UART3 NPCX_IRQ_38 +#define NPCX_IRQ_UART4 NPCX_IRQ_39 +#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 +#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 +#define NPCX_IRQ_WKINTG_0 NPCX_IRQ_42 +#define NPCX_IRQ_ITIM32_4 NPCX_IRQ_43 +#define NPCX_IRQ_ITIM32_5 NPCX_IRQ_44 +#define NPCX_IRQ_ITIM32_6 NPCX_IRQ_45 +#define NPCX_IRQ_WKINTH_0 NPCX_IRQ_46 +#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 +#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 +#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 +#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 +#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 +#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 +#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 +#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 +#define NPCX_WKINTG_2 NPCX_IRQ_55 +#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 +#define NPCX_IRQ_SPI NPCX_IRQ_57 +#define NPCX_IRQ_ITIM64 NPCX_IRQ_58 +#define NPCX_IRQ_LCT_WKINTF_2 NPCX_IRQ_59 +#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 +#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 +#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 +#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* MIWU definition */ -#define LCT_WUI_GROUP MIWU_GROUP_6 -#define LCT_WUI_MASK MASK_PIN7 +#define LCT_WUI_GROUP MIWU_GROUP_6 +#define LCT_WUI_MASK MASK_PIN7 /* Modules Map */ /* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009) +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x009) /* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 6 -#define NPCX_FWCTRL_FW_SLOT 7 - -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl) * 0x2000L)) -#define NPCX_LCT_BASE_ADDR 0x400D7000 -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - ((mdl) < 4) ? \ - (0x400C0000 + (((mdl) - 2) * 0x2000L)) : \ - ((mdl) == 4) ? \ - (0x40008000) : \ - (0x40017000 + (((mdl) - 5) * 0x1000L))) - -#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) -#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) +#define NPCX_FWCTRL_RO_REGION 6 +#define NPCX_FWCTRL_FW_SLOT 7 + +#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl)*0x2000L)) +#define NPCX_LCT_BASE_ADDR 0x400D7000 +#define NPCX_SMB_BASE_ADDR(mdl) \ + (((mdl) < 2) ? (0x40009000 + ((mdl)*0x2000L)) : \ + ((mdl) < 4) ? (0x400C0000 + (((mdl)-2) * 0x2000L)) : \ + ((mdl) == 4) ? (0x40008000) : \ + (0x40017000 + (((mdl)-5) * 0x1000L))) + +#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) +#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) enum { - NPCX_UART_PORT0 = 0, /* UART port 0 */ - NPCX_UART_PORT1 = 1, /* UART port 1 */ - NPCX_UART_PORT2 = 2, /* UART port 2 */ - NPCX_UART_PORT3 = 3, /* UART port 3 */ + NPCX_UART_PORT0 = 0, /* UART port 0 */ + NPCX_UART_PORT1 = 1, /* UART port 1 */ + NPCX_UART_PORT2 = 2, /* UART port 2 */ + NPCX_UART_PORT3 = 3, /* UART port 3 */ NPCX_UART_COUNT }; - /* UART registers only used for FIFO mode */ -#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) -#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) -#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) -#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) +/* UART registers only used for FIFO mode */ +#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) +#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) +#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) +#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) /* UART FIFO register fields */ -#define NPCX_UMDSL_FIFO_MD 0 +#define NPCX_UMDSL_FIFO_MD 0 -#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) -#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 -#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 -#define NPCX_UFTSTS_NXMIP 7 +#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) +#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 +#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 +#define NPCX_UFTSTS_NXMIP 7 -#define NPCX_UFRSTS_RFULL_LVL_STS 5 -#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 -#define NPCX_UFRSTS_ERR 7 +#define NPCX_UFRSTS_RFULL_LVL_STS 5 +#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 +#define NPCX_UFRSTS_ERR 7 -#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) -#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 -#define NPCX_UFTCTL_TEMPTY_EN 6 -#define NPCX_UFTCTL_NXMIPEN 7 +#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) +#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 +#define NPCX_UFTCTL_TEMPTY_EN 6 +#define NPCX_UFTCTL_NXMIPEN 7 -#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) -#define NPCX_UFRCTL_RFULL_LVL_EN 5 -#define NPCX_UFRCTL_RNEMPTY_EN 6 -#define NPCX_UFRCTL_ERR_EN 7 +#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) +#define NPCX_UFRCTL_RFULL_LVL_EN 5 +#define NPCX_UFRCTL_RNEMPTY_EN 6 +#define NPCX_UFRCTL_ERR_EN 7 /* KBSCAN register fields */ -#define NPCX_KBHDRV_FIELD FIELD(6, 2) +#define NPCX_KBHDRV_FIELD FIELD(6, 2) /* GLUE registers */ -#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) -#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034) -#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038) +#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) +#define NPCX_GLUE_PSL_MCTL1 REG8(NPCX_GLUE_REGS_BASE + 0x034) +#define NPCX_GLUE_PSL_MCTL2 REG8(NPCX_GLUE_REGS_BASE + 0x038) /* PSL register fields */ -#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7 -#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6 -#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4 -#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3 -#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1 -#define NPCX_GLUE_PSL_MCTL1_OD_EN 0 - -#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7 -#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6 -#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3 -#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1) +#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_PSL 7 +#define NPCX_GLUE_PSL_MCTL1_PSL_GPO_CTL 6 +#define NPCX_GLUE_PSL_MCTL1_LCT_EV 4 +#define NPCX_GLUE_PSL_MCTL1_VCC1_RST_EV 3 +#define NPCX_GLUE_PSL_MCTL1_PLS_EN 1 +#define NPCX_GLUE_PSL_MCTL1_OD_EN 0 + +#define NPCX_GLUE_PSL_MCTL2_VCC1_RST_PSL_LK 7 +#define NPCX_GLUE_PSL_MCTL2_PSL_GP_EN 6 +#define NPCX_GLUE_PSL_MCTL2_AC_IN_BLOCK_EN 3 +#define NPCX_GLUE_PSL_MCTL2_AC_IN_SEL FIELD(0, 1) /* GPIO registers */ -#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) +#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) /* System Configuration (SCFG) Registers */ @@ -197,105 +195,105 @@ enum { ALT_GROUP_COUNT }; -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) -#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ - (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ - (NPCX_SCFG_BASE_ADDR + 0x026)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) +#define NPCX_LV_GPIO_CTL_ADDR(n) \ + (((n) < 5) ? (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) : \ + (NPCX_SCFG_BASE_ADDR + 0x026)) +#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) /* Device Alternate Function Lock */ -#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n)) +#define NPCX_DEVALT_LK(n) REG8(NPCX_SCFG_BASE_ADDR + 0x210 + (n)) /* pin-mux for I2C */ -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C7_0_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C6_0_SL 3 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C5_0_SL 5 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#define NPCX_DEVALT6_I2C6_1_SL 5 -#define NPCX_DEVALT6_I2C5_1_SL 6 -#define NPCX_DEVALT6_I2C4_1_SL 7 +#define NPCX_DEVALT2_I2C0_0_SL 0 +#define NPCX_DEVALT2_I2C7_0_SL 1 +#define NPCX_DEVALT2_I2C1_0_SL 2 +#define NPCX_DEVALT2_I2C6_0_SL 3 +#define NPCX_DEVALT2_I2C2_0_SL 4 +#define NPCX_DEVALT2_I2C5_0_SL 5 +#define NPCX_DEVALT2_I2C3_0_SL 6 +#define NPCX_DEVALT6_I2C6_1_SL 5 +#define NPCX_DEVALT6_I2C5_1_SL 6 +#define NPCX_DEVALT6_I2C4_1_SL 7 /* pin-mux for ADC */ -#define NPCX_DEVALTF_ADC5_SL 0 -#define NPCX_DEVALTF_ADC6_SL 1 -#define NPCX_DEVALTF_ADC7_SL 2 -#define NPCX_DEVALTF_ADC8_SL 3 -#define NPCX_DEVALTF_ADC9_SL 4 -#define NPCX_DEVALTF_ADC10_SL 5 -#define NPCX_DEVALTF_ADC11_SL 6 +#define NPCX_DEVALTF_ADC5_SL 0 +#define NPCX_DEVALTF_ADC6_SL 1 +#define NPCX_DEVALTF_ADC7_SL 2 +#define NPCX_DEVALTF_ADC8_SL 3 +#define NPCX_DEVALTF_ADC9_SL 4 +#define NPCX_DEVALTF_ADC10_SL 5 +#define NPCX_DEVALTF_ADC11_SL 6 /* pin-mux for PSL */ -#define NPCX_DEVALTD_PSL_IN1_AHI 0 -#define NPCX_DEVALTD_NPSL_IN1_SL 1 -#define NPCX_DEVALTD_PSL_IN2_AHI 2 -#define NPCX_DEVALTD_NPSL_IN2_SL 3 -#define NPCX_DEVALTD_PSL_IN3_AHI 4 -#define NPCX_DEVALTD_PSL_IN3_SL 5 -#define NPCX_DEVALTD_PSL_IN4_AHI 6 -#define NPCX_DEVALTD_PSL_IN4_SL 7 +#define NPCX_DEVALTD_PSL_IN1_AHI 0 +#define NPCX_DEVALTD_NPSL_IN1_SL 1 +#define NPCX_DEVALTD_PSL_IN2_AHI 2 +#define NPCX_DEVALTD_NPSL_IN2_SL 3 +#define NPCX_DEVALTD_PSL_IN3_AHI 4 +#define NPCX_DEVALTD_PSL_IN3_SL 5 +#define NPCX_DEVALTD_PSL_IN4_AHI 6 +#define NPCX_DEVALTD_PSL_IN4_SL 7 /* pin-mux for Misc. */ /* pin-mux for UART */ -#define NPCX_DEVALTJ_CR_SIN1_SL1 0 -#define NPCX_DEVALTJ_CR_SOUT1_SL1 1 -#define NPCX_DEVALTJ_CR_SIN1_SL2 2 -#define NPCX_DEVALTJ_CR_SOUT1_SL2 3 -#define NPCX_DEVALTJ_CR_SIN2_SL 4 -#define NPCX_DEVALTJ_CR_SOUT2_SL 5 -#define NPCX_DEVALTJ_CR_SIN3_SL 6 -#define NPCX_DEVALTJ_CR_SOUT3_SL 7 -#define NPCX_DEVALTE_CR_SIN4_SL 6 -#define NPCX_DEVALTE_CR_SOUT4_SL 7 +#define NPCX_DEVALTJ_CR_SIN1_SL1 0 +#define NPCX_DEVALTJ_CR_SOUT1_SL1 1 +#define NPCX_DEVALTJ_CR_SIN1_SL2 2 +#define NPCX_DEVALTJ_CR_SOUT1_SL2 3 +#define NPCX_DEVALTJ_CR_SIN2_SL 4 +#define NPCX_DEVALTJ_CR_SOUT2_SL 5 +#define NPCX_DEVALTJ_CR_SIN3_SL 6 +#define NPCX_DEVALTJ_CR_SOUT3_SL 7 +#define NPCX_DEVALTE_CR_SIN4_SL 6 +#define NPCX_DEVALTE_CR_SOUT4_SL 7 /* SHI module version 2 enable bit */ -#define NPCX_DEVALTF_SHI_NEW 7 +#define NPCX_DEVALTF_SHI_NEW 7 /* VCC_RST Pull-Up Disable */ -#define NPCX_DEVALTG_VCC1_RST_PUD 5 -#define NPCX_DEVALTG_PSL_OUT_SL 6 -#define NPCX_DEVALTG_PSL_GPO_SL 7 +#define NPCX_DEVALTG_VCC1_RST_PUD 5 +#define NPCX_DEVALTG_PSL_OUT_SL 6 +#define NPCX_DEVALTG_PSL_GPO_SL 7 /* SMBus register fields */ -#define NPCX_SMBSEL_SMB4SEL 4 -#define NPCX_SMBSEL_SMB5SEL 5 -#define NPCX_SMBSEL_SMB6SEL 6 +#define NPCX_SMBSEL_SMB4SEL 4 +#define NPCX_SMBSEL_SMB5SEL 5 +#define NPCX_SMBSEL_SMB6SEL 6 /* pin-mux for JTAG */ -#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120) -#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4) -#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06 -#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09 +#define NPCX_JEN_CTL1 REG8(NPCX_SCFG_BASE_ADDR + 0x120) +#define NPCX_JEN_CTL1_JEN_EN_FIELD FIELD(0, 4) +#define NPCX_JEN_CTL1_JEN_EN_DIS 0x06 +#define NPCX_JEN_CTL1_JEN_EN_ENA 0x09 /* SMB enumeration: I2C port definitions. */ enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ - NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ - NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ - NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ - NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ - NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ - NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ - NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ - NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ + NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ + NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ + NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ + NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ + NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ + NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ + NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ + NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ + NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ + NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ NPCX_I2C_COUNT, }; /* Power Management Controller (PMC) Registers */ -#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) -#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) +#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + (offset)) /* PMC register fields */ -#define NPCX_PWDWN_CTL3_SMB4_PD 4 -#define NPCX_PWDWN_CTL7_SMB5_PD 0 -#define NPCX_PWDWN_CTL7_SMB6_PD 1 -#define NPCX_PWDWN_CTL7_SMB7_PD 2 -#define NPCX_PWDWN_CTL7_ITIM64_PD 5 -#define NPCX_PWDWN_CTL7_UART2_PD 6 +#define NPCX_PWDWN_CTL3_SMB4_PD 4 +#define NPCX_PWDWN_CTL7_SMB5_PD 0 +#define NPCX_PWDWN_CTL7_SMB6_PD 1 +#define NPCX_PWDWN_CTL7_SMB7_PD 2 +#define NPCX_PWDWN_CTL7_ITIM64_PD 5 +#define NPCX_PWDWN_CTL7_UART2_PD 6 /* * PMC enumeration: @@ -331,38 +329,37 @@ enum NPCX_PMC_PWDWN_CTL_T { NPCX_PMC_PWDWN_CNT, }; -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB7_PD)) -#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) +#define CGC_I2C_MASK \ + (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB4_PD)) +#define CGC_I2C_MASK2 \ + (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB7_PD)) +#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) /* BBRAM register fields */ -#define NPCX_BKUP_STS_VSBY_STS 1 -#define NPCX_BKUP_STS_VCC1_STS 0 -#define NPCX_BKUP_STS_ALL_MASK \ +#define NPCX_BKUP_STS_VSBY_STS 1 +#define NPCX_BKUP_STS_VCC1_STS 0 +#define NPCX_BKUP_STS_ALL_MASK \ (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ - BIT(NPCX_BKUP_STS_VCC1_STS)) -#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ + BIT(NPCX_BKUP_STS_VCC1_STS)) +#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ /* ITIM registers */ -#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008) +#define NPCX_ITCNT32(n) REG32(NPCX_ITIM_BASE_ADDR(n) + 0x008) /* Timer counter register used for 1 micro-second system tick */ -#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6) +#define NPCX_ITCNT_SYSTEM NPCX_ITCNT32(ITIM32_6) /* Timer counter register used for others */ -#define NPCX_ITCNT NPCX_ITCNT32 +#define NPCX_ITCNT NPCX_ITCNT32 /* ITIM module No. used for event */ -#define ITIM_EVENT_NO ITIM32_1 +#define ITIM_EVENT_NO ITIM32_1 /* ITIM module No. used for watchdog */ -#define ITIM_WDG_NO ITIM32_5 +#define ITIM_WDG_NO ITIM32_5 /* ITIM module No. used for 1 micro-second system tick */ -#define ITIM_SYSTEM_NO ITIM32_6 +#define ITIM_SYSTEM_NO ITIM32_6 /* ITIM enumeration */ enum ITIM_MODULE_T { @@ -376,56 +373,56 @@ enum ITIM_MODULE_T { }; /* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */ -#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) -#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) -#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) -#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) -#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) +#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) +#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) +#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) +#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) +#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) +#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) +#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) /* SHI register fields */ -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 /* eSPI register fields */ -#define NPCX_ESPIIE_BMTXDONEIE 19 -#define NPCX_ESPIIE_PBMRXIE 20 -#define NPCX_ESPIIE_PMSGRXIE 21 -#define NPCX_ESPIIE_BMBURSTERRIE 22 -#define NPCX_ESPIIE_BMBURSTDONEIE 23 - -#define NPCX_ESPIWE_PBMRXWE 20 -#define NPCX_ESPIWE_PMSGRXWE 21 - -#define NPCX_ESPISTS_VWUPDW 17 -#define NPCX_ESPISTS_BMTXDONE 19 -#define NPCX_ESPISTS_PBMRX 20 -#define NPCX_ESPISTS_PMSGRX 21 -#define NPCX_ESPISTS_BMBURSTERR 22 -#define NPCX_ESPISTS_BMBURSTDONE 23 -#define NPCX_ESPISTS_ESPIRST_LVL 24 - -#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) - -#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) +#define NPCX_ESPIIE_BMTXDONEIE 19 +#define NPCX_ESPIIE_PBMRXIE 20 +#define NPCX_ESPIIE_PMSGRXIE 21 +#define NPCX_ESPIIE_BMBURSTERRIE 22 +#define NPCX_ESPIIE_BMBURSTDONEIE 23 + +#define NPCX_ESPIWE_PBMRXWE 20 +#define NPCX_ESPIWE_PMSGRXWE 21 + +#define NPCX_ESPISTS_VWUPDW 17 +#define NPCX_ESPISTS_BMTXDONE 19 +#define NPCX_ESPISTS_PBMRX 20 +#define NPCX_ESPISTS_PMSGRX 21 +#define NPCX_ESPISTS_BMBURSTERR 22 +#define NPCX_ESPISTS_BMBURSTDONE 23 +#define NPCX_ESPISTS_ESPIRST_LVL 24 + +#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) +#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) +#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) +#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) +#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) + +#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) +#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_WK_EN(e) (((e)<<20) & 0x00100000) -#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) +#define VWEVMS_WK_EN(e) (((e) << 20) & 0x00100000) +#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) /* eSPI max supported frequency */ enum { @@ -449,61 +446,55 @@ enum { /* eSPI max frequency support per FMCLK */ #if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 #else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 #endif /* UART registers */ -#define NPCX_UART_WK_GROUP MIWU_GROUP_8 -#define NPCX_UART_WK_BIT 7 -#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 -#define NPCX_UART2_WK_BIT 6 +#define NPCX_UART_WK_GROUP MIWU_GROUP_8 +#define NPCX_UART_WK_BIT 7 +#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 +#define NPCX_UART2_WK_BIT 6 /* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 0x10)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 0x10)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + \ - ((n) * 0x10)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + \ - ((n) * 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + \ - ((n) * 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + \ - ((n) * 0x10)) -#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + \ - ((n) * 0x10)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x07 + \ - ((n) * 0x10)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) +#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + ((n)*0x10)) +#define NPCX_WKAEDG_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x01 + ((n)*0x10)) +#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x02 + ((n)*0x10)) +#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x03 + ((n)*0x10)) +#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x04 + ((n)*0x10)) +#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x05 + ((n)*0x10)) +#define NPCX_WKST_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x06 + ((n)*0x10)) +#define NPCX_WKINEN_ADDR(port, n) \ + (NPCX_MIWU_BASE_ADDR(port) + 0x07 + ((n)*0x10)) + +#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) +#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) +#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) +#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) +#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) +#define NPCX_WKST(port, n) REG8(NPCX_WKST_ADDR(port, n)) +#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) +#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* LCT register */ -#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002) -#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004) -#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005) -#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006) -#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008) -#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A) -#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C) +#define NPCX_LCTCONT REG8(NPCX_LCT_BASE_ADDR + 0x002) +#define NPCX_LCTSTAT REG8(NPCX_LCT_BASE_ADDR + 0x004) +#define NPCX_LCTSECOND REG8(NPCX_LCT_BASE_ADDR + 0x005) +#define NPCX_LCTMINUTE REG8(NPCX_LCT_BASE_ADDR + 0x006) +#define NPCX_LCTHOUR REG8(NPCX_LCT_BASE_ADDR + 0x008) +#define NPCX_LCTDAY REG8(NPCX_LCT_BASE_ADDR + 0x00A) +#define NPCX_LCTWEEK REG8(NPCX_LCT_BASE_ADDR + 0x00C) /* LCTCONT fields */ -#define NPCX_LCTCONT_EN 0 -#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1) -#define NPCX_LCTCONT_EVEN 1 -#define NPCX_LCTCONT_PSL_EN 2 -#define NPCX_LCTCONT_CLK_EN 6 -#define NPCX_LCTCONT_VSBY_PWR 7 +#define NPCX_LCTCONT_EN 0 +#define NPCX_LCTCONT_EN_FIELD FIELD(0, 1) +#define NPCX_LCTCONT_EVEN 1 +#define NPCX_LCTCONT_PSL_EN 2 +#define NPCX_LCTCONT_CLK_EN 6 +#define NPCX_LCTCONT_VSBY_PWR 7 /* LCTSTAT fields */ -#define NPCX_LCTSTAT_EVST 0 +#define NPCX_LCTSTAT_EVST 0 /* UART registers and functions */ #if NPCX_UART_MODULE2 @@ -512,73 +503,73 @@ enum { * always 1 == MIWU_TABLE_1. */ #define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 -#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 -#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 +#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 +#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 +#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 #else /* !NPCX_UART_MODULE2 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 -#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) -#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 -#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 +#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 +#define NPCX_UART_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL1 +#define NPCX_UART_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL1 +#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(ALT_GROUP_J) +#define NPCX_UART_ALT_DEVALT_SIN_SL NPCX_DEVALTJ_CR_SIN1_SL2 +#define NPCX_UART_ALT_DEVALT_SOUT_SL NPCX_DEVALTJ_CR_SOUT1_SL2 #endif /* NPCX_UART_MODULE2 */ /* ADC register */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) +#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) +#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) +#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) +#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) +#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) +#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) +#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) +#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) +#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) /* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) +#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L * (n))) /* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L*(n))) +#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x05E + (2L * (n))) /* ADC register fields */ -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR6_IEN 13 -#define NPCX_THRCTS_THR5_IEN 12 -#define NPCX_THRCTS_THR4_IEN 11 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR6_STS 5 -#define NPCX_THRCTS_THR5_STS 4 -#define NPCX_THRCTS_THR4_STS 3 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH4 4 -#define NPCX_ADC_THRESH5 5 -#define NPCX_ADC_THRESH6 6 -#define NPCX_ADC_THRESH_CNT 6 +#define NPCX_ADCSTS_EOCEV 0 +#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) +#define NPCX_ADCCNF_ADCRPTC 3 +#define NPCX_ADCCNF_INTECEN 6 +#define NPCX_ADCCNF_START 4 +#define NPCX_ADCCNF_ADCEN 0 +#define NPCX_ADCCNF_STOP 11 +#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) +#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) +#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) +#define NPCX_THRCTS_ADC_WKEN 15 +#define NPCX_THRCTS_THR6_IEN 13 +#define NPCX_THRCTS_THR5_IEN 12 +#define NPCX_THRCTS_THR4_IEN 11 +#define NPCX_THRCTS_THR3_IEN 10 +#define NPCX_THRCTS_THR2_IEN 9 +#define NPCX_THRCTS_THR1_IEN 8 +#define NPCX_THRCTS_ADC_EVENT 7 +#define NPCX_THRCTS_THR6_STS 5 +#define NPCX_THRCTS_THR5_STS 4 +#define NPCX_THRCTS_THR4_STS 3 +#define NPCX_THRCTS_THR3_STS 2 +#define NPCX_THRCTS_THR2_STS 1 +#define NPCX_THRCTS_THR1_STS 0 +#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) +#define NPCX_CHNDAT_NEW 15 +#define NPCX_THRCTL_THEN 15 +#define NPCX_THRCTL_L_H 14 +#define NPCX_THRCTL_CHNSEL FIELD(10, 4) +#define NPCX_THRCTL_THRVAL FIELD(0, 10) + +#define NPCX_ADC_THRESH1 1 +#define NPCX_ADC_THRESH2 2 +#define NPCX_ADC_THRESH3 3 +#define NPCX_ADC_THRESH4 4 +#define NPCX_ADC_THRESH5 5 +#define NPCX_ADC_THRESH6 6 +#define NPCX_ADC_THRESH_CNT 6 -- cgit v1.2.1 From 445caf679c1c5c692e066d027d16427c5aedafdf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:21 -0600 Subject: chip/mec1322/spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I99f12b4e7958bf3cb164a66e7d7bb0df5b82f238 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729323 Reviewed-by: Jeremy Bettis --- chip/mec1322/spi.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c index 5cc25b8089..9ca43dbf69 100644 --- a/chip/mec1322/spi.c +++ b/chip/mec1322/spi.c @@ -17,12 +17,12 @@ #include "task.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) #define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 -#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port) * 2) +#define SPI_DMA_CHANNEL(port) (MEC1322_DMAC_SPI0_RX + (port)*2) /* only regular image needs mutex, LFW does not have scheduling */ /* TODO: Move SPI locking to common code */ @@ -31,16 +31,10 @@ static struct mutex spi_mutex; #endif static const struct dma_option spi_rx_option[] = { - { - SPI_DMA_CHANNEL(0), - (void *)&MEC1322_SPI_RD(0), - MEC1322_DMA_XFER_SIZE(1) - }, - { - SPI_DMA_CHANNEL(1), - (void *)&MEC1322_SPI_RD(1), - MEC1322_DMA_XFER_SIZE(1) - }, + { SPI_DMA_CHANNEL(0), (void *)&MEC1322_SPI_RD(0), + MEC1322_DMA_XFER_SIZE(1) }, + { SPI_DMA_CHANNEL(1), (void *)&MEC1322_SPI_RD(1), + MEC1322_DMA_XFER_SIZE(1) }, }; static int wait_byte(const int port) @@ -74,8 +68,8 @@ static int spi_tx(const int port, const uint8_t *txdata, int txlen) } int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int port = spi_device->port; int ret = EC_SUCCESS; @@ -129,8 +123,8 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) } int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int ret; -- cgit v1.2.1 From 313ca1a4abee2cd06ca63fbd5a1559efc61bf89b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:55 -0600 Subject: driver/accelgyro_lsm6ds0.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17648794f75a50c17a41901310218deb6a4aadc0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729894 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6ds0.h | 170 ++++++++++++++++++++++----------------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/driver/accelgyro_lsm6ds0.h b/driver/accelgyro_lsm6ds0.h index c6b0789c08..425740421f 100644 --- a/driver/accelgyro_lsm6ds0.h +++ b/driver/accelgyro_lsm6ds0.h @@ -15,95 +15,95 @@ * 7-bit address is 110101Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define LSM6DS0_ADDR0_FLAGS 0x6a -#define LSM6DS0_ADDR1_FLAGS 0x6b +#define LSM6DS0_ADDR0_FLAGS 0x6a +#define LSM6DS0_ADDR1_FLAGS 0x6b /* who am I */ -#define LSM6DS0_WHO_AM_I 0x68 +#define LSM6DS0_WHO_AM_I 0x68 /* Chip specific registers. */ -#define LSM6DS0_ACT_THS 0x04 -#define LSM6DS0_ACT_DUR 0x05 -#define LSM6DS0_INT_GEN_CFG_XL 0x06 -#define LSM6DS0_INT_GEN_THS_X_XL 0x07 -#define LSM6DS0_INT_GEN_THS_Y_XL 0x08 -#define LSM6DS0_INT_GEN_THS_Z_XL 0x09 -#define LSM6DS0_INT_GEN_DUR_XL 0x0a -#define LSM6DS0_REFERENCE_G 0x0b -#define LSM6DS0_INT_CTRL 0x0c -#define LSM6DS0_WHO_AM_I_REG 0x0f -#define LSM6DS0_CTRL_REG1_G 0x10 -#define LSM6DS0_CTRL_REG2_G 0x11 -#define LSM6DS0_CTRL_REG3_G 0x12 -#define LSM6DS0_ORIENT_CFG_G 0x13 -#define LSM6DS0_INT_GEN_SRC_G 0x14 -#define LSM6DS0_OUT_TEMP_L 0x15 -#define LSM6DS0_OUT_TEMP_H 0x16 -#define LSM6DS0_OUT_X_L_G 0x18 -#define LSM6DS0_OUT_X_H_G 0x19 -#define LSM6DS0_OUT_Y_L_G 0x1a -#define LSM6DS0_OUT_Y_H_G 0x1b -#define LSM6DS0_OUT_Z_L_G 0x1c -#define LSM6DS0_OUT_Z_H_G 0x1d -#define LSM6DS0_CTRL_REG4 0x1e -#define LSM6DS0_CTRL_REG5_XL 0x1f -#define LSM6DS0_CTRL_REG6_XL 0x20 -#define LSM6DS0_CTRL_REG7_XL 0x21 -#define LSM6DS0_CTRL_REG8 0x22 -#define LSM6DS0_CTRL_REG9 0x23 -#define LSM6DS0_CTRL_REG10 0x24 -#define LSM6DS0_INT_GEN_SRC_XL 0x26 -#define LSM6DS0_STATUS_REG 0x27 -#define LSM6DS0_OUT_X_L_XL 0x28 -#define LSM6DS0_OUT_X_H_XL 0x29 -#define LSM6DS0_OUT_Y_L_XL 0x2a -#define LSM6DS0_OUT_Y_H_XL 0x2b -#define LSM6DS0_OUT_Z_L_XL 0x2c -#define LSM6DS0_OUT_Z_H_XL 0x2d -#define LSM6DS0_FIFO_CTRL 0x2e -#define LSM6DS0_FIFO_SRC 0x2f -#define LSM6DS0_INT_GEN_CFG_G 0x30 -#define LSM6DS0_INT_GEN_THS_XH_G 0x31 -#define LSM6DS0_INT_GEN_THS_XL_G 0x32 -#define LSM6DS0_INT_GEN_THS_YH_G 0x33 -#define LSM6DS0_INT_GEN_THS_YL_G 0x34 -#define LSM6DS0_INT_GEN_THS_ZH_G 0x35 -#define LSM6DS0_INT_GEN_THS_ZL_G 0x36 -#define LSM6DS0_INT_GEN_DUR_G 0x37 - -#define LSM6DS0_DPS_SEL_245 (0 << 3) -#define LSM6DS0_DPS_SEL_500 BIT(3) -#define LSM6DS0_DPS_SEL_1000 (2 << 3) -#define LSM6DS0_DPS_SEL_2000 (3 << 3) -#define LSM6DS0_GSEL_2G (0 << 3) -#define LSM6DS0_GSEL_4G (2 << 3) -#define LSM6DS0_GSEL_8G (3 << 3) - -#define LSM6DS0_RANGE_MASK (3 << 3) - -#define LSM6DS0_ODR_PD (0 << 5) -#define LSM6DS0_ODR_10HZ BIT(5) -#define LSM6DS0_ODR_15HZ BIT(5) -#define LSM6DS0_ODR_50HZ (2 << 5) -#define LSM6DS0_ODR_59HZ (2 << 5) -#define LSM6DS0_ODR_119HZ (3 << 5) -#define LSM6DS0_ODR_238HZ (4 << 5) -#define LSM6DS0_ODR_476HZ (5 << 5) -#define LSM6DS0_ODR_952HZ (6 << 5) - -#define LSM6DS0_ODR_MASK (7 << 5) +#define LSM6DS0_ACT_THS 0x04 +#define LSM6DS0_ACT_DUR 0x05 +#define LSM6DS0_INT_GEN_CFG_XL 0x06 +#define LSM6DS0_INT_GEN_THS_X_XL 0x07 +#define LSM6DS0_INT_GEN_THS_Y_XL 0x08 +#define LSM6DS0_INT_GEN_THS_Z_XL 0x09 +#define LSM6DS0_INT_GEN_DUR_XL 0x0a +#define LSM6DS0_REFERENCE_G 0x0b +#define LSM6DS0_INT_CTRL 0x0c +#define LSM6DS0_WHO_AM_I_REG 0x0f +#define LSM6DS0_CTRL_REG1_G 0x10 +#define LSM6DS0_CTRL_REG2_G 0x11 +#define LSM6DS0_CTRL_REG3_G 0x12 +#define LSM6DS0_ORIENT_CFG_G 0x13 +#define LSM6DS0_INT_GEN_SRC_G 0x14 +#define LSM6DS0_OUT_TEMP_L 0x15 +#define LSM6DS0_OUT_TEMP_H 0x16 +#define LSM6DS0_OUT_X_L_G 0x18 +#define LSM6DS0_OUT_X_H_G 0x19 +#define LSM6DS0_OUT_Y_L_G 0x1a +#define LSM6DS0_OUT_Y_H_G 0x1b +#define LSM6DS0_OUT_Z_L_G 0x1c +#define LSM6DS0_OUT_Z_H_G 0x1d +#define LSM6DS0_CTRL_REG4 0x1e +#define LSM6DS0_CTRL_REG5_XL 0x1f +#define LSM6DS0_CTRL_REG6_XL 0x20 +#define LSM6DS0_CTRL_REG7_XL 0x21 +#define LSM6DS0_CTRL_REG8 0x22 +#define LSM6DS0_CTRL_REG9 0x23 +#define LSM6DS0_CTRL_REG10 0x24 +#define LSM6DS0_INT_GEN_SRC_XL 0x26 +#define LSM6DS0_STATUS_REG 0x27 +#define LSM6DS0_OUT_X_L_XL 0x28 +#define LSM6DS0_OUT_X_H_XL 0x29 +#define LSM6DS0_OUT_Y_L_XL 0x2a +#define LSM6DS0_OUT_Y_H_XL 0x2b +#define LSM6DS0_OUT_Z_L_XL 0x2c +#define LSM6DS0_OUT_Z_H_XL 0x2d +#define LSM6DS0_FIFO_CTRL 0x2e +#define LSM6DS0_FIFO_SRC 0x2f +#define LSM6DS0_INT_GEN_CFG_G 0x30 +#define LSM6DS0_INT_GEN_THS_XH_G 0x31 +#define LSM6DS0_INT_GEN_THS_XL_G 0x32 +#define LSM6DS0_INT_GEN_THS_YH_G 0x33 +#define LSM6DS0_INT_GEN_THS_YL_G 0x34 +#define LSM6DS0_INT_GEN_THS_ZH_G 0x35 +#define LSM6DS0_INT_GEN_THS_ZL_G 0x36 +#define LSM6DS0_INT_GEN_DUR_G 0x37 + +#define LSM6DS0_DPS_SEL_245 (0 << 3) +#define LSM6DS0_DPS_SEL_500 BIT(3) +#define LSM6DS0_DPS_SEL_1000 (2 << 3) +#define LSM6DS0_DPS_SEL_2000 (3 << 3) +#define LSM6DS0_GSEL_2G (0 << 3) +#define LSM6DS0_GSEL_4G (2 << 3) +#define LSM6DS0_GSEL_8G (3 << 3) + +#define LSM6DS0_RANGE_MASK (3 << 3) + +#define LSM6DS0_ODR_PD (0 << 5) +#define LSM6DS0_ODR_10HZ BIT(5) +#define LSM6DS0_ODR_15HZ BIT(5) +#define LSM6DS0_ODR_50HZ (2 << 5) +#define LSM6DS0_ODR_59HZ (2 << 5) +#define LSM6DS0_ODR_119HZ (3 << 5) +#define LSM6DS0_ODR_238HZ (4 << 5) +#define LSM6DS0_ODR_476HZ (5 << 5) +#define LSM6DS0_ODR_952HZ (6 << 5) + +#define LSM6DS0_ODR_MASK (7 << 5) /* * Register : STATUS_REG * Address : 0X27 */ enum lsm6ds0_status { - LSM6DS0_STS_DOWN = 0x00, - LSM6DS0_STS_XLDA_UP = 0x01, - LSM6DS0_STS_GDA_UP = 0x02, + LSM6DS0_STS_DOWN = 0x00, + LSM6DS0_STS_XLDA_UP = 0x01, + LSM6DS0_STS_GDA_UP = 0x02, }; -#define LSM6DS0_STS_XLDA_MASK 0x01 -#define LSM6DS0_STS_GDA_MASK 0x02 +#define LSM6DS0_STS_XLDA_MASK 0x01 +#define LSM6DS0_STS_GDA_MASK 0x02 /* * Register : CTRL_REG8 @@ -111,18 +111,18 @@ enum lsm6ds0_status { * Bit Group Name: BDU */ enum lsm6ds0_bdu { - LSM6DS0_BDU_DISABLE = 0x00, - LSM6DS0_BDU_ENABLE = 0x40, + LSM6DS0_BDU_DISABLE = 0x00, + LSM6DS0_BDU_ENABLE = 0x40, }; /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define LSM6DS0_RESOLUTION 16 +#define LSM6DS0_RESOLUTION 16 /* Min and Max sampling frequency in mHz */ -#define LSM6DS0_ACCEL_MIN_FREQ 14900 -#define LSM6DS0_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000) +#define LSM6DS0_ACCEL_MIN_FREQ 14900 +#define LSM6DS0_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000) -#define LSM6DS0_GYRO_MIN_FREQ 14900 -#define LSM6DS0_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000) +#define LSM6DS0_GYRO_MIN_FREQ 14900 +#define LSM6DS0_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(952000, 119000) extern const struct accelgyro_drv lsm6ds0_drv; struct lsm6ds0_data { -- cgit v1.2.1 From 2c52da77ae22908d0cc8606e3bebea0327477f9a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:37 -0600 Subject: include/gpio_list.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17fafdef029bd5d972085709dbc084bb881476c8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730277 Reviewed-by: Jeremy Bettis --- include/gpio_list.h | 49 +++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/include/gpio_list.h b/include/gpio_list.h index 6bd43187d9..7ff6c09617 100644 --- a/include/gpio_list.h +++ b/include/gpio_list.h @@ -8,35 +8,35 @@ #include "gpio_signal.h" #ifdef CONFIG_COMMON_GPIO_SHORTNAMES -#define GPIO(name, pin, flags) {GPIO_NAME_BY_##pin, GPIO_##pin, flags}, +#define GPIO(name, pin, flags) { GPIO_NAME_BY_##pin, GPIO_##pin, flags }, #define GPIO_INT(name, pin, flags, signal) \ - {GPIO_NAME_BY_##pin, GPIO_##pin, flags}, + { GPIO_NAME_BY_##pin, GPIO_##pin, flags }, #else -#define GPIO(name, pin, flags) {#name, GPIO_##pin, flags}, -#define GPIO_INT(name, pin, flags, signal) {#name, GPIO_##pin, flags}, +#define GPIO(name, pin, flags) { #name, GPIO_##pin, flags }, +#define GPIO_INT(name, pin, flags, signal) { #name, GPIO_##pin, flags }, #endif -#define UNIMPLEMENTED(name) {#name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT}, +#define UNIMPLEMENTED(name) { #name, UNIMPLEMENTED_GPIO_BANK, 0, GPIO_DEFAULT }, /* GPIO signal list. */ __const_data const struct gpio_info gpio_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT); -#define UNUSED(pin) {GPIO_##pin}, +#define UNUSED(pin) { GPIO_##pin }, /* Unconnected pin list. */ __const_data const struct unused_pin_info unused_pin_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; const int unused_pin_count = ARRAY_SIZE(unused_pin_list); /* GPIO Interrupt Handlers */ #define GPIO_INT(name, pin, flags, signal) signal, -void (* const gpio_irq_handlers[])(enum gpio_signal signal) = { - #include "gpio.wrap" +void (*const gpio_irq_handlers[])(enum gpio_signal signal) = { +#include "gpio.wrap" }; const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); @@ -47,7 +47,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * * This constraint is handled within gpio.wrap. */ -#define GPIO_INT(name, pin, flags, signal) \ +#define GPIO_INT(name, pin, flags, signal) \ BUILD_ASSERT(GPIO_##name < ARRAY_SIZE(gpio_irq_handlers)); #include "gpio.wrap" @@ -64,8 +64,9 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * The compiler will complain if we use the same name twice. The linker ignores * anything that gets by. */ -#define PIN(a, b...) static const int _pin_ ## a ## _ ## b \ - __attribute__((unused, section(".unused"))) = __LINE__; +#define PIN(a, b...) \ + static const int _pin_##a##_##b \ + __attribute__((unused, section(".unused"))) = __LINE__; #include "gpio.wrap" #include "ioexpander.h" @@ -83,7 +84,7 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * - flags: the same as the flags of GPIO. * */ -#define IOEX(name, expin, flags) {#name, IOEX_##expin, flags}, +#define IOEX(name, expin, flags) { #name, IOEX_##expin, flags }, /* * Define the IO expander IO which supports interrupt in gpio.inc by * the format: @@ -97,18 +98,18 @@ const int gpio_ih_count = ARRAY_SIZE(gpio_irq_handlers); * - flags: the same as the flags of GPIO. * - handler: the IOEX IO's interrupt handler. */ -#define IOEX_INT(name, expin, flags, handler) {#name, IOEX_##expin, flags}, +#define IOEX_INT(name, expin, flags, handler) { #name, IOEX_##expin, flags }, /* IO expander signal list. */ const struct ioex_info ioex_list[] = { - #include "gpio.wrap" +#include "gpio.wrap" }; BUILD_ASSERT(ARRAY_SIZE(ioex_list) == IOEX_COUNT); /* IO Expander Interrupt Handlers */ #define IOEX_INT(name, expin, flags, handler) handler, -void (* const ioex_irq_handlers[])(enum ioex_signal signal) = { - #include "gpio.wrap" +void (*const ioex_irq_handlers[])(enum ioex_signal signal) = { +#include "gpio.wrap" }; const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); /* @@ -116,9 +117,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); * IOEX's declaration in the gpio.inc * file. */ -#define IOEX_INT(name, expin, flags, handler) \ - BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START \ - < ARRAY_SIZE(ioex_irq_handlers)); +#define IOEX_INT(name, expin, flags, handler) \ + BUILD_ASSERT(IOEX_##name - IOEX_SIGNAL_START < \ + ARRAY_SIZE(ioex_irq_handlers)); #include "gpio.wrap" #define IOEX(name, expin, flags) expin @@ -128,9 +129,9 @@ const int ioex_ih_count = ARRAY_SIZE(ioex_irq_handlers); * number declared is greater or equal to CONFIG_IO_EXPANDER_PORT_COUNT. * The linker ignores anything that gets by. */ -#define EXPIN(a, b, c...) \ - static const int _expin_ ## a ## _ ## b ## _ ## c \ - __attribute__((unused, section(".unused"))) = __LINE__; \ +#define EXPIN(a, b, c...) \ + static const int _expin_##a##_##b##_##c \ + __attribute__((unused, section(".unused"))) = __LINE__; \ BUILD_ASSERT(a < CONFIG_IO_EXPANDER_PORT_COUNT); #include "gpio.wrap" -- cgit v1.2.1 From 4f052806c9c76b589ac2ce270a3985ab0069a1ae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:32 -0600 Subject: zephyr/shim/chip/npcx/include/flash_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3832b01526560a7dd717bd1120779f78b8877a7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728329 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/include/flash_chip.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/shim/chip/npcx/include/flash_chip.h b/zephyr/shim/chip/npcx/include/flash_chip.h index 1d7a76f1da..3b9375348b 100644 --- a/zephyr/shim/chip/npcx/include/flash_chip.h +++ b/zephyr/shim/chip/npcx/include/flash_chip.h @@ -8,17 +8,17 @@ #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x10000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x10000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at start of protected region, right after header */ -#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE +#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE #define CONFIG_RW_STORAGE_OFF 0 /* Use 4k sector erase for NPCX monitor flash erase operations. */ -#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 +#define NPCX_MONITOR_FLASH_ERASE_SIZE 0x1000 #endif /* __CROS_EC_FLASH_CHIP_H */ -- cgit v1.2.1 From fb983396158842626671d2dc52377bb8c4340325 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:29 -0600 Subject: test/usb_prl_noextended.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0629c5f76202781b4795f240f880e3d40963e517 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730567 Reviewed-by: Jeremy Bettis --- test/usb_prl_noextended.c | 1348 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1347 insertions(+), 1 deletion(-) mode change 120000 => 100644 test/usb_prl_noextended.c diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c deleted file mode 120000 index a47c01a13e..0000000000 --- a/test/usb_prl_noextended.c +++ /dev/null @@ -1 +0,0 @@ -usb_prl_old.c \ No newline at end of file diff --git a/test/usb_prl_noextended.c b/test/usb_prl_noextended.c new file mode 100644 index 0000000000..c0b5d8696d --- /dev/null +++ b/test/usb_prl_noextended.c @@ -0,0 +1,1347 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Test USB Protocol Layer module. + */ +#include "common.h" +#include "crc.h" +#include "task.h" +#include "tcpm/tcpm.h" +#include "test_util.h" +#include "timer.h" +#include "usb_emsg.h" +#include "usb_pd_test_util.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" +#include "usb_pe_sm.h" +#include "usb_prl_sm.h" +#include "usb_sm_checks.h" +#include "usb_tc_sm.h" +#include "util.h" + +#define PORT0 0 + +/* + * These enum definitions are declared in usb_prl_sm and are private to that + * file. If those definitions are re-ordered, then we need to update these + * definitions (should be very rare). + */ +enum usb_prl_tx_state { + PRL_TX_PHY_LAYER_RESET, + PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + PRL_TX_LAYER_RESET_FOR_TRANSMIT, + PRL_TX_WAIT_FOR_PHY_RESPONSE, + PRL_TX_SRC_SOURCE_TX, + PRL_TX_SNK_START_AMS, + PRL_TX_SRC_PENDING, + PRL_TX_SNK_PENDING, + PRL_TX_DISCARD_MESSAGE, +}; + +enum usb_prl_hr_state { + PRL_HR_WAIT_FOR_REQUEST, + PRL_HR_RESET_LAYER, + PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, + PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, +}; + +enum usb_rch_state { + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + RCH_PASS_UP_MESSAGE, + RCH_PROCESSING_EXTENDED_MESSAGE, + RCH_REQUESTING_CHUNK, + RCH_WAITING_CHUNK, + RCH_REPORT_ERROR, +}; + +enum usb_tch_state { + TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, + TCH_WAIT_FOR_TRANSMISSION_COMPLETE, + TCH_CONSTRUCT_CHUNKED_MESSAGE, + TCH_SENDING_CHUNKED_MESSAGE, + TCH_WAIT_CHUNK_REQUEST, + TCH_MESSAGE_RECEIVED, + TCH_MESSAGE_SENT, + TCH_REPORT_ERROR, +}; + +/* Defined in implementation */ +enum usb_prl_tx_state prl_tx_get_state(const int port); +enum usb_prl_hr_state prl_hr_get_state(const int port); +enum usb_rch_state rch_get_state(const int port); +enum usb_tch_state tch_get_state(const int port); + +#ifndef CONFIG_USB_PD_EXTENDED_MESSAGES +enum usb_rch_state rch_get_state(const int port) +{ + return RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER; +} +#endif + +static uint32_t test_data[] = { + 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, + 0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, + 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647, + 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, + 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, + 0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, + 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7, + 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, + 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, + 0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, + 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344 +}; + +void pd_set_suspend(int port, int suspend) +{ +} + +void pd_set_error_recovery(int port) +{ +} + +static enum pd_power_role get_partner_power_role(int port); +static enum pd_data_role get_partner_data_role(int port); + +static struct pd_prl { + int rev; + int pd_enable; + enum pd_power_role power_role; + enum pd_data_role data_role; + int msg_tx_id; + int msg_rx_id; + enum tcpci_msg_type sop; + + int mock_pe_message_sent; + int mock_pe_error; + int mock_pe_hard_reset_sent; + int mock_pe_got_hard_reset; + int mock_pe_message_received; + int mock_got_soft_reset; + int mock_message_discard; +} pd_port[CONFIG_USB_PD_PORT_MAX_COUNT]; + +static void init_port(int port, int rev) +{ + pd_port[port].rev = rev; + pd_port[port].pd_enable = 0; + pd_port[port].power_role = PD_ROLE_SINK; + pd_port[port].data_role = PD_ROLE_UFP; + pd_port[port].msg_tx_id = 0; + pd_port[port].msg_rx_id = 0; + + tcpm_init(port); + tcpm_set_polarity(port, 0); + tcpm_set_rx_enable(port, 0); +} + +static inline uint32_t pending_pd_task_events(int port) +{ + return *task_get_event_bitmap(PD_PORT_TO_TASK_ID(port)); +} + +void inc_tx_id(int port) +{ + pd_port[port].msg_tx_id = (pd_port[port].msg_tx_id + 1) & 7; +} + +void inc_rx_id(int port) +{ + pd_port[port].msg_rx_id = (pd_port[port].msg_rx_id + 1) % 7; +} + +static int verify_goodcrc(int port, int role, int id) +{ + return pd_test_tx_msg_verify_sop(port) && + pd_test_tx_msg_verify_short(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, + role, id, 0, 0, 0)) && + pd_test_tx_msg_verify_crc(port) && + pd_test_tx_msg_verify_eop(port); +} + +static void simulate_rx_msg(int port, uint16_t header, int cnt, + const uint32_t *data) +{ + int i; + + pd_test_rx_set_preamble(port, 1); + pd_test_rx_msg_append_sop(port); + pd_test_rx_msg_append_short(port, header); + + crc32_init(); + crc32_hash16(header); + + for (i = 0; i < cnt; ++i) { + pd_test_rx_msg_append_word(port, data[i]); + crc32_hash32(data[i]); + } + + pd_test_rx_msg_append_word(port, crc32_result()); + + pd_test_rx_msg_append_eop(port); + pd_test_rx_msg_append_last_edge(port); + + pd_simulate_rx(port); +} + +static void simulate_goodcrc(int port, int role, int id) +{ + simulate_rx_msg(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, + pd_port[port].rev, 0), + 0, NULL); +} + +static void cycle_through_state_machine(int port, uint32_t num, uint32_t time) +{ + int i; + + for (i = 0; i < num; i++) { + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(time); + } +} + +static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type, + int chunk_num, int len) +{ + uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), + get_partner_data_role(port), + pd_port[port].msg_rx_id, 1, + pd_port[port].rev, 1); + uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len); + + simulate_rx_msg(port, header, 1, (const uint32_t *)&msg); + task_wait_event(30 * MSEC); + + if (!verify_goodcrc(port, pd_port[port].data_role, + pd_port[port].msg_rx_id)) + return 0; + + return 1; +} + +static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type) +{ + uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), + get_partner_data_role(port), + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); + + simulate_rx_msg(port, header, 0, NULL); + task_wait_event(30 * MSEC); + + if (!verify_goodcrc(port, pd_port[port].data_role, + pd_port[port].msg_rx_id)) + return 0; + + return 1; +} + +static int verify_data_reception(int port, uint16_t header, int len) +{ + int i; + int cnt = (len + 3) & ~3; + + cycle_through_state_machine(port, 3, 10 * MSEC); + + if (pd_port[port].mock_pe_error >= 0) + return 0; + + if (!pd_port[port].mock_pe_message_received) + return 0; + + if (rx_emsg[port].header != header) + return 0; + + if (rx_emsg[port].len != cnt) + return 0; + + for (i = 0; i < cnt; i++) { + if (i < len) { + if (rx_emsg[port].buf[i] != + *((unsigned char *)test_data + i)) + return 0; + } else { + if (rx_emsg[port].buf[i] != 0) + return 0; + } + } + + return 1; +} + +static int verify_chunk_data_reception(int port, uint16_t header, int len) +{ + int i; + uint8_t *td = (uint8_t *)test_data; + + if (pd_port[port].mock_got_soft_reset) { + ccprintf("Got mock soft reset\n"); + return 0; + } + + if (!pd_port[port].mock_pe_message_received) { + ccprintf("No mock pe msg received\n"); + return 0; + } + + if (pd_port[port].mock_pe_error >= 0) { + ccprintf("Mock pe error (%d)\n", pd_port[port].mock_pe_error); + return 0; + } + + if (rx_emsg[port].len != len) { + ccprintf("emsg len (%d) != 0\n", rx_emsg[port].len); + return 0; + } + + for (i = 0; i < len; i++) { + if (rx_emsg[port].buf[i] != td[i]) { + ccprintf("emsg buf[%d] != td\n", i); + return 0; + } + } + + return 1; +} + +static int simulate_receive_data(int port, enum pd_data_msg_type msg_type, + int len) +{ + int i; + int nw = (len + 3) >> 2; + uint8_t td[28]; + uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), + get_partner_data_role(port), + pd_port[port].msg_rx_id, nw, + pd_port[port].rev, 0); + + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_received = 0; + rx_emsg[port].header = 0; + rx_emsg[port].len = 0; + memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf)); + + for (i = 0; i < 28; i++) { + if (i < len) + td[i] = *((uint8_t *)test_data + i); + else + td[i] = 0; + } + + simulate_rx_msg(port, header, nw, (uint32_t *)td); + task_wait_event(30 * MSEC); + + if (!verify_goodcrc(port, pd_port[port].data_role, + pd_port[port].msg_rx_id)) + return 0; + + inc_rx_id(port); + + return verify_data_reception(port, header, len); +} + +static int simulate_receive_extended_data(int port, + enum pd_data_msg_type msg_type, + int len) +{ + int i; + int j; + int byte_len; + int nw; + int dsize; + uint8_t td[28]; + int chunk_num = 0; + int data_offset = 0; + uint8_t *expected_data = (uint8_t *)test_data; + uint16_t header; + + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_received = 0; + rx_emsg[port].header = 0; + rx_emsg[port].len = 0; + memset(rx_emsg[port].buf, 0, ARRAY_SIZE(rx_emsg[port].buf)); + + dsize = len; + for (j = 0; j < 10; j++) { + /* Let state machine settle before starting another round */ + cycle_through_state_machine(port, 10, MSEC); + + byte_len = len; + if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN) + byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN; + + len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN; + + memset(td, 0, 28); + *(uint16_t *)td = PD_EXT_HEADER(chunk_num, 0, dsize); + + for (i = 0; i < byte_len; i++) + td[i + 2] = *(expected_data + data_offset++); + + nw = (byte_len + 2 + 3) >> 2; + header = PD_HEADER(msg_type, get_partner_power_role(port), + get_partner_data_role(port), + pd_port[port].msg_rx_id, nw, + pd_port[port].rev, 1); + + if (pd_port[port].mock_pe_error >= 0) { + ccprintf("Mock pe error (%d) iteration (%d)\n", + pd_port[port].mock_pe_error, j); + return 0; + } + + if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && + pd_port[port].mock_pe_message_received) { + ccprintf("Mock pe msg received iteration (%d)\n", j); + return 0; + } + + if (rx_emsg[port].len != 0) { + ccprintf("emsg len (%d) != 0 iteration (%d)\n", + rx_emsg[port].len, j); + return 0; + } + + simulate_rx_msg(port, header, nw, (uint32_t *)td); + cycle_through_state_machine(port, 1, MSEC); + + if (!verify_goodcrc(port, pd_port[port].data_role, + pd_port[port].msg_rx_id)) { + ccprintf("Verify goodcrc bad iteration (%d)\n", j); + return 0; + } + + cycle_through_state_machine(port, 1, MSEC); + inc_rx_id(port); + + if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) { + if (pd_port[port].mock_pe_message_received) + return 1; + return 0; + } + + /* + * If no more data, do expected to get a chunk request + */ + if (len <= 0) + break; + + /* + * We need to ensure that the TX event has been set, which may + * require an extra cycle through the state machine + */ + if (!(PD_EVENT_TX & pending_pd_task_events(port))) + cycle_through_state_machine(port, 1, MSEC); + + chunk_num++; + + /* Test Request next chunk packet */ + if (!pd_test_tx_msg_verify_sop(port)) { + ccprintf("Verify sop bad iteration (%d)\n", j); + return 0; + } + + if (!pd_test_tx_msg_verify_short( + port, PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, + pd_port[port].msg_tx_id, 1, + pd_port[port].rev, 1))) { + ccprintf("Verify msg short bad iteration (%d)\n", j); + return 0; + } + + if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num, + 1, 0))) { + ccprintf("Verify msg word bad iteration (%d)\n", j); + return 0; + } + + if (!pd_test_tx_msg_verify_crc(port)) { + ccprintf("Verify msg crc bad iteration (%d)\n", j); + return 0; + } + + if (!pd_test_tx_msg_verify_eop(port)) { + ccprintf("Verify msg eop bad iteration (%d)\n", j); + return 0; + } + + cycle_through_state_machine(port, 1, MSEC); + + /* Request next chunk packet was good. Send GoodCRC */ + simulate_goodcrc(port, get_partner_power_role(port), + pd_port[port].msg_tx_id); + + cycle_through_state_machine(port, 1, MSEC); + + inc_tx_id(port); + } + + cycle_through_state_machine(port, 1, MSEC); + + return verify_chunk_data_reception(port, header, dsize); +} + +static int verify_ctrl_msg_transmission(int port, + enum pd_ctrl_msg_type msg_type) +{ + if (!pd_test_tx_msg_verify_sop(port)) + return 0; + + if (!pd_test_tx_msg_verify_short( + port, + PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, pd_port[port].msg_tx_id, + 0, pd_port[port].rev, 0))) + return 0; + + if (!pd_test_tx_msg_verify_crc(port)) + return 0; + + if (!pd_test_tx_msg_verify_eop(port)) + return 0; + + return 1; +} + +static int +simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type, + enum pd_ctrl_msg_type msg_type) +{ + pd_port[port].mock_got_soft_reset = 0; + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_sent = 0; + prl_send_ctrl_msg(port, type, msg_type); + cycle_through_state_machine(port, 1, MSEC); + + return verify_ctrl_msg_transmission(port, msg_type); +} + +static int verify_data_msg_transmission(int port, + enum pd_data_msg_type msg_type, int len) +{ + int i; + int num_words = (len + 3) >> 2; + int data_obj_in_bytes; + uint32_t td; + + if (!pd_test_tx_msg_verify_sop(port)) + return 0; + + if (!pd_test_tx_msg_verify_short( + port, + PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, pd_port[port].msg_tx_id, + num_words, pd_port[port].rev, 0))) + return 0; + + for (i = 0; i < num_words; i++) { + td = test_data[i]; + data_obj_in_bytes = (i + 1) * 4; + if (data_obj_in_bytes > len) { + switch (data_obj_in_bytes - len) { + case 1: + td &= 0x00ffffff; + break; + case 2: + td &= 0x0000ffff; + break; + case 3: + td &= 0x000000ff; + break; + } + } + + if (!pd_test_tx_msg_verify_word(port, td)) + return 0; + } + + if (!pd_test_tx_msg_verify_crc(port)) + return 0; + + if (!pd_test_tx_msg_verify_eop(port)) + return 0; + + return 1; +} + +static int +simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type, + enum pd_data_msg_type msg_type, int len) +{ + int i; + uint8_t *buf = tx_emsg[port].buf; + uint8_t *td = (uint8_t *)test_data; + + pd_port[port].mock_got_soft_reset = 0; + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_sent = 0; + + for (i = 0; i < len; i++) + buf[i] = td[i]; + + tx_emsg[port].len = len; + + prl_send_data_msg(port, type, msg_type); + cycle_through_state_machine(port, 1, MSEC); + + return verify_data_msg_transmission(port, msg_type, len); +} + +static int verify_extended_data_msg_transmission(int port, + enum pd_ext_msg_type msg_type, + int len) +{ + int i; + int j; + int nw; + int byte_len; + int dsize; + uint32_t td; + uint8_t *expected_data = (uint8_t *)&test_data; + int data_offset = 0; + int chunk_number_to_send = 0; + + dsize = len; + + for (j = 0; j < 10; j++) { + byte_len = len; + if (byte_len > PD_MAX_EXTENDED_MSG_CHUNK_LEN) + byte_len = PD_MAX_EXTENDED_MSG_CHUNK_LEN; + + nw = (byte_len + 2 + 3) >> 2; + + if (!pd_test_tx_msg_verify_sop(port)) { + ccprintf("failed tx sop; iteration (%d)\n", j); + return 0; + } + + if (!pd_test_tx_msg_verify_short( + port, PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, + pd_port[port].msg_tx_id, nw, + pd_port[port].rev, 1))) { + ccprintf("failed tx short\n"); + return 0; + } + td = PD_EXT_HEADER(chunk_number_to_send, 0, dsize); + td |= *(expected_data + data_offset++) << 16; + td |= *(expected_data + data_offset++) << 24; + + if (byte_len == 1) + td &= 0x00ffffff; + + if (!pd_test_tx_msg_verify_word(port, td)) { + ccprintf("failed tx word\n"); + return 0; + } + + byte_len -= 2; + + if (byte_len > 0) { + nw = (byte_len + 3) >> 2; + for (i = 0; i < nw; i++) { + td = *(expected_data + data_offset++) << 0; + td |= *(expected_data + data_offset++) << 8; + td |= *(expected_data + data_offset++) << 16; + td |= *(expected_data + data_offset++) << 24; + + switch (byte_len) { + case 3: + td &= 0x00ffffff; + break; + case 2: + td &= 0x0000ffff; + break; + case 1: + td &= 0x000000ff; + break; + } + + if (!pd_test_tx_msg_verify_word(port, td)) + return 0; + byte_len -= 4; + } + } + + if (!pd_test_tx_msg_verify_crc(port)) { + ccprintf("failed tx crc\n"); + return 0; + } + + if (!pd_test_tx_msg_verify_eop(port)) { + ccprintf("failed tx eop\n"); + return 0; + } + + cycle_through_state_machine(port, 1, MSEC); + + /* Send GoodCRC */ + simulate_goodcrc(port, get_partner_power_role(port), + pd_port[port].msg_tx_id); + cycle_through_state_machine(port, 1, MSEC); + inc_tx_id(port); + + len -= PD_MAX_EXTENDED_MSG_CHUNK_LEN; + if (len <= 0) + break; + + chunk_number_to_send++; + /* Let state machine settle */ + cycle_through_state_machine(port, 10, MSEC); + if (!simulate_request_chunk(port, msg_type, + chunk_number_to_send, dsize)) { + ccprintf("failed request chunk\n"); + return 0; + } + + cycle_through_state_machine(port, 1, MSEC); + inc_rx_id(port); + } + + return 1; +} + +static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type, + enum pd_ext_msg_type msg_type, + int len) +{ + int i; + uint8_t *buf = tx_emsg[port].buf; + uint8_t *td = (uint8_t *)test_data; + + memset(buf, 0, ARRAY_SIZE(tx_emsg[port].buf)); + tx_emsg[port].len = len; + + /* don't overflow buffer */ + if (len > ARRAY_SIZE(tx_emsg[port].buf)) + len = ARRAY_SIZE(tx_emsg[port].buf); + + for (i = 0; i < len; i++) + buf[i] = td[i]; + + prl_send_ext_data_msg(port, type, msg_type); + cycle_through_state_machine(port, 1, MSEC); + + return verify_extended_data_msg_transmission(port, msg_type, len); +} + +uint8_t tc_get_pd_enabled(int port) +{ + return pd_port[port].pd_enable; +} + +static void enable_prl(int port, int en) +{ + tcpm_set_rx_enable(port, en); + + pd_port[port].pd_enable = en; + pd_port[port].msg_tx_id = 0; + pd_port[port].msg_rx_id = 0; + + /* Init PRL */ + cycle_through_state_machine(port, 10, MSEC); + + prl_set_rev(port, TCPCI_MSG_SOP, pd_port[port].rev); +} + +enum pd_power_role pd_get_power_role(int port) +{ + return pd_port[port].power_role; +} + +static enum pd_power_role get_partner_power_role(int port) +{ + return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE : + PD_ROLE_SINK; +} + +enum pd_data_role pd_get_data_role(int port) +{ + return pd_port[port].data_role; +} + +static enum pd_data_role get_partner_data_role(int port) +{ + return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP : + PD_ROLE_UFP; +} + +enum pd_cable_plug tc_get_cable_plug(int port) +{ + return PD_PLUG_FROM_DFP_UFP; +} + +void pe_report_error(int port, enum pe_error e, enum tcpci_msg_type type) +{ + pd_port[port].mock_pe_error = e; + pd_port[port].sop = type; +} + +void pe_report_discard(int port) +{ + pd_port[port].mock_message_discard = 1; +} + +void pe_got_hard_reset(int port) +{ + pd_port[port].mock_pe_got_hard_reset = 1; +} + +void pe_message_received(int port) +{ + pd_port[port].mock_pe_message_received = 1; +} + +void pe_message_sent(int port) +{ + pd_port[port].mock_pe_message_sent = 1; +} + +void pe_hard_reset_sent(int port) +{ + pd_port[port].mock_pe_hard_reset_sent = 1; +} + +void pe_got_soft_reset(int port) +{ + pd_port[port].mock_got_soft_reset = 1; +} + +bool pe_in_frs_mode(int port) +{ + return false; +} + +bool pe_in_local_ams(int port) +{ + /* We will probably want to change this in the future */ + return false; +} + +static int test_prl_reset(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + prl_reset_soft(port); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); + TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, + "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_send_ctrl_msg(void) +{ + int i; + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Control message transmission and tx_id increment + */ + for (i = 0; i < 10; i++) { + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%u"); + + TEST_NE(simulate_send_ctrl_msg_request_from_pe( + port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT), + 0, "%d"); + + cycle_through_state_machine(port, 1, MSEC); + + simulate_goodcrc(port, get_partner_power_role(port), + pd_port[port].msg_tx_id); + inc_tx_id(port); + + /* Let statemachine settle */ + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + } + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_send_data_msg(void) +{ + int i; + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Sending data message with 1 to 28 bytes + */ + for (i = 1; i <= 28; i++) { + cycle_through_state_machine(port, 1, MSEC); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%u"); + + TEST_NE(simulate_send_data_msg_request_from_pe( + port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i), + 0, "%d"); + + cycle_through_state_machine(port, 1, MSEC); + + simulate_goodcrc(port, get_partner_power_role(port), + pd_port[port].msg_tx_id); + inc_tx_id(port); + + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + } + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_send_data_msg_to_much_data(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Send data message with more than 28-bytes, should fail + */ + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + + /* Try to send 29-bytes */ + TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP, + PD_DATA_SOURCE_CAP, 29), + 0, "%d"); + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(30 * MSEC); + + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_EQ(pd_port[port].mock_pe_message_sent, 0, "%d"); + TEST_EQ(pd_port[port].mock_pe_error, ERR_TCH_XMIT, "%d"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_send_extended_data_msg(void) +{ + int i; + int port = PORT0; + + if (!IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) { + ccprints("CONFIG_USB_PD_EXTENDED_MESSAGES disabled; skipping"); + return EC_SUCCESS; + } + + enable_prl(port, 1); + + /* + * TEST: Sending extended data message with 29 to 260 bytes + */ + + pd_port[port].mock_got_soft_reset = 0; + pd_port[port].mock_pe_error = -1; + + ccprintf("Iteration "); + for (i = 29; i <= PD_MAX_EXTENDED_MSG_LEN; i++) { + ccprintf(".%d", i); + pd_port[port].mock_pe_message_sent = 0; + + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%d"); + + TEST_NE(simulate_send_extended_data_msg( + port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO, + i), + 0, "%d"); + + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + } + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_receive_soft_reset_msg(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Receiving Soft Reset + */ + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); + + pd_port[port].mock_got_soft_reset = 0; + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_received = 0; + + TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_SOFT_RESET), 0, "%d"); + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(30 * MSEC); + + cycle_through_state_machine(port, 10, MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 1, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + /* + * We don't want to get pe_got_soft_reset and pe_message_received, just + * pe_got_soft_reset. + */ + TEST_EQ(pd_port[port].mock_pe_message_received, 0, "%d"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_receive_control_msg(void) +{ + int port = PORT0; + int expected_header = + PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port), + get_partner_data_role(port), pd_port[port].msg_rx_id, + 0, pd_port[port].rev, 0); + + enable_prl(port, 1); + + /* + * TEST: Receiving a control message + */ + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); + + pd_port[port].mock_got_soft_reset = 0; + pd_port[port].mock_pe_error = -1; + pd_port[port].mock_pe_message_received = 0; + + TEST_NE(simulate_receive_ctrl_msg(port, PD_CTRL_DR_SWAP), 0, "%d"); + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(30 * MSEC); + + cycle_through_state_machine(port, 3, 10 * MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + TEST_NE(pd_port[port].mock_pe_message_received, 0, "%d"); + TEST_EQ(expected_header, rx_emsg[port].header, "%d"); + TEST_EQ(rx_emsg[port].len, 0, "%d"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_receive_data_msg(void) +{ + int port = PORT0; + int i; + + enable_prl(port, 1); + + /* + * TEST: Receiving data message with 1 to 28 bytes + */ + + for (i = 1; i <= 28; i++) { + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(rch_get_state(port), + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i), + 0, "%d"); + } + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_receive_extended_data_msg(void) +{ + int len; + int port = PORT0; + + enable_prl(port, 1); + + if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) { + /* + * TEST: Receiving extended data message with 29 to 260 bytes + */ + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(rch_get_state(port), + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + + for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) { + TEST_NE(simulate_receive_extended_data( + port, PD_DATA_BATTERY_STATUS, len), + 0, "%d"); + } + } else { + /* + * TEST: Receiving unsupported extended data message and then + * subsequently receiving a support non-extended data message. + */ + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + TEST_NE(simulate_receive_extended_data( + port, PD_DATA_BATTERY_STATUS, 29), + 0, "%d"); + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28), + 0, "%d"); + } + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_send_soft_reset_msg(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Send soft reset + */ + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + + TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP, + PD_CTRL_SOFT_RESET), + 0, "%d"); + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(30 * MSEC); + + simulate_goodcrc(port, get_partner_power_role(port), + pd_port[port].msg_tx_id); + inc_tx_id(port); + + TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u"); + + cycle_through_state_machine(port, 3, 10 * MSEC); + + TEST_EQ(pd_port[port].mock_got_soft_reset, 0, "%d"); + TEST_NE(pd_port[port].mock_pe_message_sent, 0, "%d"); + TEST_LE(pd_port[port].mock_pe_error, 0, "%d"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_pe_execute_hard_reset_msg(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + pd_port[port].mock_pe_hard_reset_sent = 0; + + /* + * TEST: Policy Engine initiated hard reset + */ + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); + + /* Simulate receiving hard reset from policy engine */ + prl_execute_hard_reset(port); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + + cycle_through_state_machine(port, 1, 10 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, + "%u"); + + cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET); + TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d"); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); + + /* Simulate policy engine indicating that it is done hard reset */ + prl_hard_reset_complete(port); + + cycle_through_state_machine(port, 1, 10 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +static int test_phy_execute_hard_reset_msg(void) +{ + int port = PORT0; + + enable_prl(port, 1); + + /* + * TEST: Port partner initiated hard reset + */ + + pd_port[port].mock_pe_got_hard_reset = 0; + + task_wake(PD_PORT_TO_TASK_ID(port)); + task_wait_event(40 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); + + /* Simulate receiving hard reset from port partner */ + pd_execute_hard_reset(port); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + + cycle_through_state_machine(port, 1, 10 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); + + cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET); + TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d"); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); + + /* Simulate policy engine indicating that it is done hard reset */ + prl_hard_reset_complete(port); + + cycle_through_state_machine(port, 1, 10 * MSEC); + + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); + + enable_prl(port, 0); + + return EC_SUCCESS; +} + +/* Reset the state machine between each test */ +void before_test(void) +{ + /* This test relies on explicitly cycling through events manually */ + tc_pause_event_loop(PORT0); + + pd_port[PORT0].mock_pe_message_sent = 0; + pd_port[PORT0].mock_pe_error = -1; + pd_port[PORT0].mock_message_discard = 0; + pd_port[PORT0].mock_pe_hard_reset_sent = 0; + pd_port[PORT0].mock_pe_got_hard_reset = 0; + pd_port[PORT0].mock_pe_message_received = 0; + pd_port[PORT0].mock_got_soft_reset = 0; + pd_port[PORT0].pd_enable = false; + cycle_through_state_machine(PORT0, 10, MSEC); + pd_port[PORT0].pd_enable = true; + cycle_through_state_machine(PORT0, 10, MSEC); +} + +void run_test(int argc, char **argv) +{ + test_reset(); + + /* Test PD 2.0 Protocol */ + init_port(PORT0, PD_REV20); + RUN_TEST(test_prl_reset); + RUN_TEST(test_send_ctrl_msg); + RUN_TEST(test_send_data_msg); + RUN_TEST(test_send_data_msg_to_much_data); + RUN_TEST(test_receive_control_msg); + RUN_TEST(test_receive_data_msg); + RUN_TEST(test_receive_soft_reset_msg); + RUN_TEST(test_send_soft_reset_msg); + RUN_TEST(test_pe_execute_hard_reset_msg); + RUN_TEST(test_phy_execute_hard_reset_msg); + + /* TODO(shurst): More PD 2.0 Tests */ + + ccprints("Starting PD 3.0 tests"); + + /* Test PD 3.0 Protocol */ + init_port(PORT0, PD_REV30); + RUN_TEST(test_prl_reset); + RUN_TEST(test_send_ctrl_msg); + RUN_TEST(test_send_data_msg); + RUN_TEST(test_send_data_msg_to_much_data); + RUN_TEST(test_send_extended_data_msg); + RUN_TEST(test_receive_control_msg); + RUN_TEST(test_receive_data_msg); + RUN_TEST(test_receive_extended_data_msg); + RUN_TEST(test_receive_soft_reset_msg); + RUN_TEST(test_send_soft_reset_msg); + RUN_TEST(test_pe_execute_hard_reset_msg); + RUN_TEST(test_phy_execute_hard_reset_msg); + + /* TODO(shurst): More PD 3.0 Tests */ + + /* Do basic state machine validity checks last. */ + RUN_TEST(test_prl_no_parent_cycles); + RUN_TEST(test_prl_all_states_named); + + test_print_result(); +} -- cgit v1.2.1 From edbb7b984f1e7d884c2434667199d46e56e92e0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:26 -0600 Subject: core/nds32/cpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie43a8786c085943913e74526a16fefa35d648c81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729860 Reviewed-by: Jeremy Bettis --- core/nds32/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c index 6a3f3b5bc4..d94a90cf07 100644 --- a/core/nds32/cpu.c +++ b/core/nds32/cpu.c @@ -12,5 +12,5 @@ void cpu_init(void) { /* DLM initialization is done in init.S */ /* Global interrupt enable */ - asm volatile ("setgie.e"); + asm volatile("setgie.e"); } -- cgit v1.2.1 From a193d76e48112e71facf5c1ba9b09d925ea43266 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:57 -0600 Subject: board/driblee/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0bdc962a1877a540cf87bbbad1837c0c6c16d3a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728257 Reviewed-by: Jeremy Bettis --- board/driblee/battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/driblee/battery.c b/board/driblee/battery.c index 19f0312305..cc1661b7e2 100644 --- a/board/driblee/battery.c +++ b/board/driblee/battery.c @@ -638,8 +638,8 @@ const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_BYD_1VX1H; int charger_profile_override(struct charge_state_data *curr) { if (chipset_in_state(CHIPSET_STATE_ON)) { - curr->requested_current = MIN(curr->requested_current, - CHARGING_CURRENT_1100MA); + curr->requested_current = + MIN(curr->requested_current, CHARGING_CURRENT_1100MA); } return 0; -- cgit v1.2.1 From 8e8f98ddd947ab41c2c9fb7c49f33eba5dc1ddc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:58 -0600 Subject: board/waddledee/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0808c0086a9104e9f6ea51d02cedc1d2f7d28111 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729098 Reviewed-by: Jeremy Bettis --- board/waddledee/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/waddledee/cbi_ssfc.c b/board/waddledee/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/waddledee/cbi_ssfc.c +++ b/board/waddledee/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 522cd466f9164d6def9f6c3180a71dcf560c870b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:38 -0600 Subject: board/vell/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5d15dcb471043d5c2620f9425b3f8332c40260ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729043 Reviewed-by: Jeremy Bettis --- board/vell/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/vell/board.c b/board/vell/board.c index 47774afec5..ba60c65373 100644 --- a/board/vell/board.c +++ b/board/vell/board.c @@ -27,8 +27,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static void board_chipset_startup(void) { -- cgit v1.2.1 From 59658ba500e854de82db02928cde5beb9de081cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:59 -0600 Subject: chip/npcx/system-npcx7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf301253a6a81e7883d0405fa1057175f20a23dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729440 Reviewed-by: Jeremy Bettis --- chip/npcx/system-npcx7.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index abbb6755c3..b3a8aec6fd 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -21,13 +21,13 @@ #include "system_chip.h" #include "rom_chip.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Macros for last 32K ram block */ #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) /* Higher bits are reserved and need to be masked */ -#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) +#define RAM_PD_MASK (~BIT(LAST_RAM_BLK)) /*****************************************************************************/ /* IC specific low-level driver depends on chip series */ @@ -83,11 +83,11 @@ void system_enter_psl_mode(void) NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PSL; #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 - /* - * If pulse mode is enabled, the VCC power is turned off by the - * external component (Ex: PMIC) but PSL_OUT. So we can just return - * here. - */ + /* + * If pulse mode is enabled, the VCC power is turned off by the + * external component (Ex: PMIC) but PSL_OUT. So we can just return + * here. + */ if (IS_BIT_SET(NPCX_GLUE_PSL_MCTL1, NPCX_GLUE_PSL_MCTL1_PLS_EN)) return; #endif @@ -113,8 +113,7 @@ static void system_psl_type_sel(enum psl_pin_t psl_pin, uint32_t flags) /* Set PSL input events' type as level or edge trigger */ if ((flags & GPIO_INT_F_HIGH) || (flags & GPIO_INT_F_LOW)) CLEAR_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); - else if ((flags & GPIO_INT_F_RISING) || - (flags & GPIO_INT_F_FALLING)) + else if ((flags & GPIO_INT_F_RISING) || (flags & GPIO_INT_F_FALLING)) SET_BIT(NPCX_GLUE_PSL_CTS, psl_pin + 4); /* @@ -145,7 +144,7 @@ int system_config_psl_mode(enum gpio_signal signal) * Hibernate function in last 32K ram block for npcx7 series. * Do not use global variable since we also turn off data ram. */ -noreturn void __keep __attribute__ ((section(".after_init"))) +noreturn void __keep __attribute__((section(".after_init"))) __enter_hibernate_in_last_block(void) { /* @@ -164,7 +163,7 @@ __enter_hibernate_in_last_block(void) NPCX_PMCSR = 0x6; /* Enter deep idle, wake-up by GPIOs or RTC */ - asm volatile ("wfi"); + asm volatile("wfi"); /* RTC wake-up */ if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO)) @@ -208,8 +207,8 @@ void __hibernate_npcx_series(void) __enter_hibernate_in_psl(); #else /* Make sure this is located in the last 32K code RAM block */ - ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE - < (32*1024)); + ASSERT((uint32_t)(&__after_init_end) - CONFIG_PROGRAM_MEMORY_BASE < + (32 * 1024)); /* Execute hibernate func in last 32K block */ __enter_hibernate_in_last_block(); -- cgit v1.2.1 From 9f9c8ababf27e95fb5c0fa45bd054585a9fb4247 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:24 -0600 Subject: include/task_id.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9563e00926310e888f7c33185231436f10a944a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730418 Reviewed-by: Jeremy Bettis --- include/task_id.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/include/task_id.h b/include/task_id.h index 2ea10c9595..2cb57b59b3 100644 --- a/include/task_id.h +++ b/include/task_id.h @@ -17,8 +17,8 @@ #include "task_filter.h" /* define the name of the header containing the list of tasks */ -#define STRINGIFY0(name) #name -#define STRINGIFY(name) STRINGIFY0(name) +#define STRINGIFY0(name) #name +#define STRINGIFY(name) STRINGIFY0(name) #define CTS_TASK_LIST STRINGIFY(CTS_TASKFILE) #define TEST_TASK_LIST STRINGIFY(TEST_TASKFILE) #define BOARD_TASK_LIST STRINGIFY(BOARD_TASKFILE) @@ -46,16 +46,17 @@ enum { TASK_ID_IDLE, /* CONFIG_TASK_LIST is a macro coming from the BOARD_TASK_LIST file */ CONFIG_TASK_LIST - /* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file */ - CONFIG_TEST_TASK_LIST - /* For CTS tasks */ - CONFIG_CTS_TASK_LIST + /* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file + */ + CONFIG_TEST_TASK_LIST + /* For CTS tasks */ + CONFIG_CTS_TASK_LIST #ifdef EMU_BUILD - TASK_ID_TEST_RUNNER, + TASK_ID_TEST_RUNNER, #endif /* Number of tasks */ TASK_ID_COUNT, - /* Special task identifiers */ +/* Special task identifiers */ #ifdef EMU_BUILD TASK_ID_INT_GEN = 0xfe, /* interrupt generator */ #endif -- cgit v1.2.1 From 67e0b8bb5690346d2468d031ff8dd73ee47af92d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:11 -0600 Subject: zephyr/shim/src/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf25e9cf26b24ace2187555e32247b917e2af739 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730903 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/thermal.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/src/thermal.c b/zephyr/shim/src/thermal.c index c31e2bfcc6..e986f6a27c 100644 --- a/zephyr/shim/src/thermal.c +++ b/zephyr/shim/src/thermal.c @@ -7,7 +7,7 @@ #include "temp_sensor/temp_sensor.h" #include "ec_commands.h" -#define THERMAL_CONFIG(node_id) \ +#define THERMAL_CONFIG(node_id) \ [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = \ -- cgit v1.2.1 From 348a00f50b52b6c305ee29fa078e3751a3b8c172 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:53 -0600 Subject: include/driver/accelgyro_bmi160_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c54eb98398e2673a785af028f1665c37bfb44ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730248 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi160_public.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/driver/accelgyro_bmi160_public.h b/include/driver/accelgyro_bmi160_public.h index 6a6890eb84..57d1bc56cc 100644 --- a/include/driver/accelgyro_bmi160_public.h +++ b/include/driver/accelgyro_bmi160_public.h @@ -18,7 +18,7 @@ */ /* I2C addresses */ -#define BMI160_ADDR0_FLAGS 0x68 +#define BMI160_ADDR0_FLAGS 0x68 extern const struct accelgyro_drv bmi160_drv; -- cgit v1.2.1 From d29c8a6ce0aa9f6d7d3c4396685e0bb780a1da0f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:34 -0600 Subject: test/usb_tcpmv2_td_pd_src_e1.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95b716904b00b45695c8b03d98ffe45092126d49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730560 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src_e1.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src_e1.c b/test/usb_tcpmv2_td_pd_src_e1.c index a617f90ca2..3e1f56e33c 100644 --- a/test/usb_tcpmv2_td_pd_src_e1.c +++ b/test/usb_tcpmv2_td_pd_src_e1.c @@ -38,8 +38,7 @@ int test_td_pd_src_e1(void) * is not received from the Provider within 250 ms (tFirstSourceCap * max) after VBus present. */ - TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0, - PD_DATA_SOURCE_CAP, + TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, 0, PD_DATA_SOURCE_CAP, 250 * MSEC), EC_SUCCESS, "%d"); -- cgit v1.2.1 From 38d01e10c60d5991c535466fc5435ff3ab397601 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:21 -0600 Subject: chip/npcx/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7063e3b6c6c9845b685ef4ca7b32aef89601a807 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729428 Reviewed-by: Jeremy Bettis --- chip/npcx/registers.h | 2552 ++++++++++++++++++++++++------------------------- 1 file changed, 1270 insertions(+), 1282 deletions(-) diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 8f0c7431a6..5942ea46d0 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -17,28 +17,32 @@ * Macro Functions */ /* Bit functions */ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) -#define UPDATE_BIT(reg, bit, cond) { if (cond) \ - SET_BIT(reg, bit); \ - else \ - CLEAR_BIT(reg, bit); } +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define UPDATE_BIT(reg, bit, cond) \ + { \ + if (cond) \ + SET_BIT(reg, bit); \ + else \ + CLEAR_BIT(reg, bit); \ + } /* Field functions */ -#define GET_POS_FIELD(pos, size) pos -#define GET_SIZE_FIELD(pos, size) size -#define FIELD_POS(field) GET_POS_##field -#define FIELD_SIZE(field) GET_SIZE_##field +#define GET_POS_FIELD(pos, size) pos +#define GET_SIZE_FIELD(pos, size) size +#define FIELD_POS(field) GET_POS_##field +#define FIELD_SIZE(field) GET_SIZE_##field /* Read field functions */ #define GET_FIELD(reg, field) \ _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) -#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) +#define _GET_FIELD_(reg, f_pos, f_size) \ + (((reg) >> (f_pos)) & ((1 << (f_size)) - 1)) /* Write field functions */ #define SET_FIELD(reg, field, value) \ _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) -#define _SET_FIELD_(reg, f_pos, f_size, value) \ - ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ - | ((value) << (f_pos))) +#define _SET_FIELD_(reg, f_pos, f_size, value) \ + ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \ + ((value) << (f_pos))) /******************************************************************************/ /* @@ -46,216 +50,212 @@ */ /* Global Definition */ -#define I2C_7BITS_ADDR 0 +#define I2C_7BITS_ADDR 0 /* Switcher of features */ -#define SUPPORT_LCT 1 -#define SUPPORT_WDG 1 -#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ +#define SUPPORT_LCT 1 +#define SUPPORT_WDG 1 +#define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ /* Switcher of debugging */ -#define DEBUG_GPIO 0 -#define DEBUG_I2C 0 -#define DEBUG_TMR 0 -#define DEBUG_WDG 0 -#define DEBUG_FAN 0 -#define DEBUG_PWM 0 -#define DEBUG_SPI 0 -#define DEBUG_FLH 0 -#define DEBUG_PECI 0 -#define DEBUG_SHI 0 -#define DEBUG_CLK 0 -#define DEBUG_LPC 0 -#define DEBUG_ESPI 0 -#define DEBUG_CEC 0 -#define DEBUG_SIB 0 -#define DEBUG_PS2 0 +#define DEBUG_GPIO 0 +#define DEBUG_I2C 0 +#define DEBUG_TMR 0 +#define DEBUG_WDG 0 +#define DEBUG_FAN 0 +#define DEBUG_PWM 0 +#define DEBUG_SPI 0 +#define DEBUG_FLH 0 +#define DEBUG_PECI 0 +#define DEBUG_SHI 0 +#define DEBUG_CLK 0 +#define DEBUG_LPC 0 +#define DEBUG_ESPI 0 +#define DEBUG_CEC 0 +#define DEBUG_SIB 0 +#define DEBUG_PS2 0 /* Modules Map */ -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 -#define NPCX_SHM_BASE_ADDR 0x40010000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 -#define NPCX_FIU_BASE_ADDR 0x40020000 -#define NPCX_KBSCAN_REGS_BASE 0x400A3000 -#define NPCX_WOV_BASE_ADDR 0x400A4000 -#define NPCX_APM_BASE_ADDR 0x400A4800 -#define NPCX_GLUE_REGS_BASE 0x400A5000 -#define NPCX_BBRAM_BASE_ADDR 0x400AF000 -#define NPCX_PS2_BASE_ADDR 0x400B1000 -#define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_LFCG_BASE_ADDR 0x400B5100 -#define NPCX_FMUL2_BASE_ADDR 0x400B5200 -#define NPCX_MTC_BASE_ADDR 0x400B7000 -#define NPCX_MSWC_BASE_ADDR 0x400C1000 -#define NPCX_SCFG_BASE_ADDR 0x400C3000 -#define NPCX_KBC_BASE_ADDR 0x400C7000 -#define NPCX_ADC_BASE_ADDR 0x400D1000 -#define NPCX_SPI_BASE_ADDR 0x400D2000 -#define NPCX_PECI_BASE_ADDR 0x400D4000 -#define NPCX_TWD_BASE_ADDR 0x400D8000 +#define NPCX_ESPI_BASE_ADDR 0x4000A000 +#define NPCX_MDC_BASE_ADDR 0x4000C000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_SIB_BASE_ADDR 0x4000E000 +#define NPCX_SHI_BASE_ADDR 0x4000F000 +#define NPCX_SHM_BASE_ADDR 0x40010000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_FIU_BASE_ADDR 0x40020000 +#define NPCX_KBSCAN_REGS_BASE 0x400A3000 +#define NPCX_WOV_BASE_ADDR 0x400A4000 +#define NPCX_APM_BASE_ADDR 0x400A4800 +#define NPCX_GLUE_REGS_BASE 0x400A5000 +#define NPCX_BBRAM_BASE_ADDR 0x400AF000 +#define NPCX_PS2_BASE_ADDR 0x400B1000 +#define NPCX_HFCG_BASE_ADDR 0x400B5000 +#define NPCX_LFCG_BASE_ADDR 0x400B5100 +#define NPCX_FMUL2_BASE_ADDR 0x400B5200 +#define NPCX_MTC_BASE_ADDR 0x400B7000 +#define NPCX_MSWC_BASE_ADDR 0x400C1000 +#define NPCX_SCFG_BASE_ADDR 0x400C3000 +#define NPCX_KBC_BASE_ADDR 0x400C7000 +#define NPCX_ADC_BASE_ADDR 0x400D1000 +#define NPCX_SPI_BASE_ADDR 0x400D2000 +#define NPCX_PECI_BASE_ADDR 0x400D4000 +#define NPCX_TWD_BASE_ADDR 0x400D8000 /* Multi-Modules Map */ -#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) -#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) -#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) +#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L)) +#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L)) +#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L)) +#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L)) +#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L)) +#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L)) /* * NPCX-IRQ numbers */ -#define NPCX_IRQ_0 0 -#define NPCX_IRQ_1 1 -#define NPCX_IRQ_2 2 -#define NPCX_IRQ_3 3 -#define NPCX_IRQ_4 4 -#define NPCX_IRQ_5 5 -#define NPCX_IRQ_6 6 -#define NPCX_IRQ_7 7 -#define NPCX_IRQ_8 8 -#define NPCX_IRQ_9 9 -#define NPCX_IRQ_10 10 -#define NPCX_IRQ_11 11 -#define NPCX_IRQ_12 12 -#define NPCX_IRQ_13 13 -#define NPCX_IRQ_14 14 -#define NPCX_IRQ_15 15 -#define NPCX_IRQ_16 16 -#define NPCX_IRQ_17 17 -#define NPCX_IRQ_18 18 -#define NPCX_IRQ_19 19 -#define NPCX_IRQ_20 20 -#define NPCX_IRQ_21 21 -#define NPCX_IRQ_22 22 -#define NPCX_IRQ_23 23 -#define NPCX_IRQ_24 24 -#define NPCX_IRQ_25 25 -#define NPCX_IRQ_26 26 -#define NPCX_IRQ_27 27 -#define NPCX_IRQ_28 28 -#define NPCX_IRQ_29 29 -#define NPCX_IRQ_30 30 -#define NPCX_IRQ_31 31 -#define NPCX_IRQ_32 32 -#define NPCX_IRQ_33 33 -#define NPCX_IRQ_34 34 -#define NPCX_IRQ_35 35 -#define NPCX_IRQ_36 36 -#define NPCX_IRQ_37 37 -#define NPCX_IRQ_38 38 -#define NPCX_IRQ_39 39 -#define NPCX_IRQ_40 40 -#define NPCX_IRQ_41 41 -#define NPCX_IRQ_42 42 -#define NPCX_IRQ_43 43 -#define NPCX_IRQ_44 44 -#define NPCX_IRQ_45 45 -#define NPCX_IRQ_46 46 -#define NPCX_IRQ_47 47 -#define NPCX_IRQ_48 48 -#define NPCX_IRQ_49 49 -#define NPCX_IRQ_50 50 -#define NPCX_IRQ_51 51 -#define NPCX_IRQ_52 52 -#define NPCX_IRQ_53 53 -#define NPCX_IRQ_54 54 -#define NPCX_IRQ_55 55 -#define NPCX_IRQ_56 56 -#define NPCX_IRQ_57 57 -#define NPCX_IRQ_58 58 -#define NPCX_IRQ_59 59 -#define NPCX_IRQ_60 60 -#define NPCX_IRQ_61 61 -#define NPCX_IRQ_62 62 -#define NPCX_IRQ_63 63 - -#define NPCX_IRQ_COUNT 64 +#define NPCX_IRQ_0 0 +#define NPCX_IRQ_1 1 +#define NPCX_IRQ_2 2 +#define NPCX_IRQ_3 3 +#define NPCX_IRQ_4 4 +#define NPCX_IRQ_5 5 +#define NPCX_IRQ_6 6 +#define NPCX_IRQ_7 7 +#define NPCX_IRQ_8 8 +#define NPCX_IRQ_9 9 +#define NPCX_IRQ_10 10 +#define NPCX_IRQ_11 11 +#define NPCX_IRQ_12 12 +#define NPCX_IRQ_13 13 +#define NPCX_IRQ_14 14 +#define NPCX_IRQ_15 15 +#define NPCX_IRQ_16 16 +#define NPCX_IRQ_17 17 +#define NPCX_IRQ_18 18 +#define NPCX_IRQ_19 19 +#define NPCX_IRQ_20 20 +#define NPCX_IRQ_21 21 +#define NPCX_IRQ_22 22 +#define NPCX_IRQ_23 23 +#define NPCX_IRQ_24 24 +#define NPCX_IRQ_25 25 +#define NPCX_IRQ_26 26 +#define NPCX_IRQ_27 27 +#define NPCX_IRQ_28 28 +#define NPCX_IRQ_29 29 +#define NPCX_IRQ_30 30 +#define NPCX_IRQ_31 31 +#define NPCX_IRQ_32 32 +#define NPCX_IRQ_33 33 +#define NPCX_IRQ_34 34 +#define NPCX_IRQ_35 35 +#define NPCX_IRQ_36 36 +#define NPCX_IRQ_37 37 +#define NPCX_IRQ_38 38 +#define NPCX_IRQ_39 39 +#define NPCX_IRQ_40 40 +#define NPCX_IRQ_41 41 +#define NPCX_IRQ_42 42 +#define NPCX_IRQ_43 43 +#define NPCX_IRQ_44 44 +#define NPCX_IRQ_45 45 +#define NPCX_IRQ_46 46 +#define NPCX_IRQ_47 47 +#define NPCX_IRQ_48 48 +#define NPCX_IRQ_49 49 +#define NPCX_IRQ_50 50 +#define NPCX_IRQ_51 51 +#define NPCX_IRQ_52 52 +#define NPCX_IRQ_53 53 +#define NPCX_IRQ_54 54 +#define NPCX_IRQ_55 55 +#define NPCX_IRQ_56 56 +#define NPCX_IRQ_57 57 +#define NPCX_IRQ_58 58 +#define NPCX_IRQ_59 59 +#define NPCX_IRQ_60 60 +#define NPCX_IRQ_61 61 +#define NPCX_IRQ_62 62 +#define NPCX_IRQ_63 63 + +#define NPCX_IRQ_COUNT 64 /******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ -#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) -#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) -#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004) -#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) -#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) -#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) +#define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) +#define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) +#define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004) +#define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) +#define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) +#define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) /* HFCG register fields */ -#define NPCX_HFCGCTRL_LOAD 0 -#define NPCX_HFCGCTRL_LOCK 2 -#define NPCX_HFCGCTRL_CLK_CHNG 7 +#define NPCX_HFCGCTRL_LOAD 0 +#define NPCX_HFCGCTRL_LOCK 2 +#define NPCX_HFCGCTRL_CLK_CHNG 7 /******************************************************************************/ /* Low Frequency Clock Generator (LFCG) registers */ -#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) -#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) -#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) -#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) -#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) -#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) -#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) +#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) +#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) +#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) +#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) +#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) +#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) +#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) /* LFCG register fields */ -#define NPCX_LFCGCTL_XTCLK_VAL 7 -#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 +#define NPCX_LFCGCTL_XTCLK_VAL 7 +#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 /******************************************************************************/ /* CR UART Register */ -#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000) -#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002) -#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004) -#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006) -#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008) -#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) -#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) -#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) +#define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000) +#define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002) +#define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004) +#define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006) +#define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008) +#define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) +#define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) +#define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) /******************************************************************************/ /* KBSCAN registers */ -#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04) -#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05) -#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06) -#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08) -#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A) -#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B) -#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C) -#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D) -#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E) -#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F) +#define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04) +#define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05) +#define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06) +#define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08) +#define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A) +#define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B) +#define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C) +#define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D) +#define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E) +#define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F) /* KBSCAN register fields */ -#define NPCX_KBSBUFINDX 0 -#define NPCX_KBSDONE 0 -#define NPCX_KBSERR 1 -#define NPCX_KBSSTART 0 -#define NPCX_KBSMODE 1 -#define NPCX_KBSIEN 2 -#define NPCX_KBSINC 3 -#define NPCX_KBSCFGINDX 0 +#define NPCX_KBSBUFINDX 0 +#define NPCX_KBSDONE 0 +#define NPCX_KBSERR 1 +#define NPCX_KBSSTART 0 +#define NPCX_KBSMODE 1 +#define NPCX_KBSIEN 2 +#define NPCX_KBSINC 3 +#define NPCX_KBSCFGINDX 0 /* KBSCAN definitions */ -#define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */ -#define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */ -#define KB_ROW_MASK ((1<= 0 && i <= 1) ? ESPI_VW_TYPE_INT_EV : \ - (i >= 2 && i <= 7) ? ESPI_VW_TYPE_SYS_EV : \ - (i >= 64 && i <= 127) ? ESPI_VW_TYPE_PLT : \ - (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ - ESPI_VW_TYPE_NONE) +#define VM_TYPE(i) \ + ((i >= 0 && i <= 1) ? ESPI_VW_TYPE_INT_EV : \ + (i >= 2 && i <= 7) ? ESPI_VW_TYPE_SYS_EV : \ + (i >= 64 && i <= 127) ? ESPI_VW_TYPE_PLT : \ + (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ + ESPI_VW_TYPE_NONE) /* Bit field manipulation for VWEVMS Value */ -#define VWEVMS_INX(i) ((i<<8) & 0x00007F00) -#define VWEVMS_INX_EN(n) ((n<<15) & 0x00008000) -#define VWEVMS_PLTRST_EN(p) ((p<<17) & 0x00020000) -#define VWEVMS_INT_EN(e) ((e<<18) & 0x00040000) -#define VWEVMS_ESPIRST_EN(r) ((r<<19) & 0x00080000) -#define VWEVMS_FIELD(i, n, p, e, r) (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \ - VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \ - VWEVMS_ESPIRST_EN(r)) -#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00)>>8)) +#define VWEVMS_INX(i) ((i << 8) & 0x00007F00) +#define VWEVMS_INX_EN(n) ((n << 15) & 0x00008000) +#define VWEVMS_PLTRST_EN(p) ((p << 17) & 0x00020000) +#define VWEVMS_INT_EN(e) ((e << 18) & 0x00040000) +#define VWEVMS_ESPIRST_EN(r) ((r << 19) & 0x00080000) +#define VWEVMS_FIELD(i, n, p, e, r) \ + (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | VWEVMS_PLTRST_EN(p) | \ + VWEVMS_INTWK_EN(e) | VWEVMS_ESPIRST_EN(r)) +#define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00) >> 8)) /* Bit field manipulation for VWEVSM Value */ -#define VWEVSM_VALID_N(v) ((v<<4) & 0x000000F0) -#define VWEVSM_INX(i) ((i<<8) & 0x00007F00) -#define VWEVSM_INX_EN(n) ((n<<15) & 0x00008000) -#define VWEVSM_DIRTY(d) ((d<<16) & 0x00010000) -#define VWEVSM_PLTRST_EN(p) ((p<<17) & 0x00020000) -#define VWEVSM_CDRST_EN(c) ((c<<19) & 0x00080000) -#define VWEVSM_FIELD(i, n, v, p, c) (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \ - VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\ - VWEVSM_CDRST_EN(c)) -#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00)>>8)) +#define VWEVSM_VALID_N(v) ((v << 4) & 0x000000F0) +#define VWEVSM_INX(i) ((i << 8) & 0x00007F00) +#define VWEVSM_INX_EN(n) ((n << 15) & 0x00008000) +#define VWEVSM_DIRTY(d) ((d << 16) & 0x00010000) +#define VWEVSM_PLTRST_EN(p) ((p << 17) & 0x00020000) +#define VWEVSM_CDRST_EN(c) ((c << 19) & 0x00080000) +#define VWEVSM_FIELD(i, n, v, p, c) \ + (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | VWEVSM_VALID_N(v) | \ + VWEVSM_PLTRST_EN(p) | VWEVSM_CDRST_EN(c)) +#define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00) >> 8)) /* define macro to handle SMI/SCI Virtual Wire */ /* Read SMI VWire status from VWEVSM(offset 2) register. */ -#define SMI_STATUS_MASK ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002)) +#define SMI_STATUS_MASK ((uint8_t)(NPCX_VWEVSM(2) & 0x00000002)) /* * Read SCI VWire status from VWEVSM(offset 2) register. * Left shift 2 to meet the SCIB field in HIPMIC register. */ -#define SCI_STATUS_MASK (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2) -#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) -#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB) -#define NPCX_VW_SCI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ - SMI_STATUS_MASK | SCIB_MASK(level)) -#define NPCX_VW_SMI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ - SCI_STATUS_MASK | SMIB_MASK(level)) +#define SCI_STATUS_MASK (((uint8_t)(NPCX_VWEVSM(2) & 0x00000001)) << 2) +#define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) +#define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB) +#define NPCX_VW_SCI(level) \ + ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SMI_STATUS_MASK | SCIB_MASK(level)) +#define NPCX_VW_SMI(level) \ + ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | SCI_STATUS_MASK | SMIB_MASK(level)) /* eSPI enumeration */ /* eSPI channels */ @@ -1306,374 +1301,367 @@ enum { /* eSPI IO modes */ enum { NPCX_ESPI_IO_MODE_SINGLE = 0, - NPCX_ESPI_IO_MODE_DUAL = 1, - NPCX_ESPI_IO_MODE_QUAD = 2, - NPCX_ESPI_IO_MODE_ALL = 3, - NPCX_ESPI_IO_MODE_NONE = 0xFF + NPCX_ESPI_IO_MODE_DUAL = 1, + NPCX_ESPI_IO_MODE_QUAD = 2, + NPCX_ESPI_IO_MODE_ALL = 3, + NPCX_ESPI_IO_MODE_NONE = 0xFF }; /* eSPI IO mode selected */ enum { NPCX_ESPI_IO_MODE_SEL_SINGLE = 0, - NPCX_ESPI_IO_MODE_SEL_DUAL = 1, - NPCX_ESPI_IO_MODE_SEL_QUARD = 2, - NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF + NPCX_ESPI_IO_MODE_SEL_DUAL = 1, + NPCX_ESPI_IO_MODE_SEL_QUARD = 2, + NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF }; /* VW types */ enum { - ESPI_VW_TYPE_INT_EV, /* Interrupt event */ - ESPI_VW_TYPE_SYS_EV, /* System Event */ - ESPI_VW_TYPE_PLT, /* Platform specific */ - ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */ + ESPI_VW_TYPE_INT_EV, /* Interrupt event */ + ESPI_VW_TYPE_SYS_EV, /* System Event */ + ESPI_VW_TYPE_PLT, /* Platform specific */ + ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */ ESPI_VW_TYPE_NUM, ESPI_VW_TYPE_NONE = 0xFF }; /******************************************************************************/ /* GDMA (General DMA) Registers */ -#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) -#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) -#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) -#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) -#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010) -#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014) -#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018) - +#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) +#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) +#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) +#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) +#define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010) +#define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014) +#define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018) /******************************************************************************/ /* GDMA register fields */ -#define NPCX_GDMA_CTL_GDMAEN 0 -#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) -#define NPCX_GDMA_CTL_DADIR 4 -#define NPCX_GDMA_CTL_SADIR 5 -#define NPCX_GDMA_CTL_SAFIX 7 -#define NPCX_GDMA_CTL_SIEN 8 -#define NPCX_GDMA_CTL_BME 9 -#define NPCX_GDMA_CTL_SBMS 11 -#define NPCX_GDMA_CTL_TWS FIELD(12, 2) -#define NPCX_GDMA_CTL_DM 15 -#define NPCX_GDMA_CTL_SOFTREQ 16 -#define NPCX_GDMA_CTL_TC 18 -#define NPCX_GDMA_CTL_GDMAERR 20 -#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 +#define NPCX_GDMA_CTL_GDMAEN 0 +#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) +#define NPCX_GDMA_CTL_DADIR 4 +#define NPCX_GDMA_CTL_SADIR 5 +#define NPCX_GDMA_CTL_SAFIX 7 +#define NPCX_GDMA_CTL_SIEN 8 +#define NPCX_GDMA_CTL_BME 9 +#define NPCX_GDMA_CTL_SBMS 11 +#define NPCX_GDMA_CTL_TWS FIELD(12, 2) +#define NPCX_GDMA_CTL_DM 15 +#define NPCX_GDMA_CTL_SOFTREQ 16 +#define NPCX_GDMA_CTL_TC 18 +#define NPCX_GDMA_CTL_GDMAERR 20 +#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 /******************************************************************************/ /* Nuvoton internal used only registers */ -#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000) -#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000) -#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000) +#define NPCX_INTERNAL_CTRL1 REG8(0x400DB000) +#define NPCX_INTERNAL_CTRL2 REG8(0x400DD000) +#define NPCX_INTERNAL_CTRL3 REG8(0x400DF000) /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_DHCSR REG32(0xE000EDF0) -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) - +#define CPU_DHCSR REG32(0xE000EDF0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) /******************************************************************************/ /* Flash Utiltiy definition */ /* * Flash commands for the W25Q16CV SPI flash */ -#define CMD_READ_ID 0x9F -#define CMD_READ_MAN_DEV_ID 0x90 -#define CMD_WRITE_EN 0x06 -#define CMD_WRITE_STATUS 0x50 -#define CMD_READ_STATUS_REG 0x05 -#define CMD_READ_STATUS_REG2 0x35 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_FLASH_PROGRAM 0x02 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_BLOCK_32K_ERASE 0x52 -#define CMD_BLOCK_64K_ERASE 0xd8 -#define CMD_PROGRAM_UINT_SIZE 0x08 -#define CMD_PAGE_SIZE 0x00 -#define CMD_READ_ID_TYPE 0x47 -#define CMD_FAST_READ 0x0B +#define CMD_READ_ID 0x9F +#define CMD_READ_MAN_DEV_ID 0x90 +#define CMD_WRITE_EN 0x06 +#define CMD_WRITE_STATUS 0x50 +#define CMD_READ_STATUS_REG 0x05 +#define CMD_READ_STATUS_REG2 0x35 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_FLASH_PROGRAM 0x02 +#define CMD_SECTOR_ERASE 0x20 +#define CMD_BLOCK_32K_ERASE 0x52 +#define CMD_BLOCK_64K_ERASE 0xd8 +#define CMD_PROGRAM_UINT_SIZE 0x08 +#define CMD_PAGE_SIZE 0x00 +#define CMD_READ_ID_TYPE 0x47 +#define CMD_FAST_READ 0x0B /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ -#define FIU_CHIP_SELECT 0 +#define FIU_CHIP_SELECT 0 /* Create UMA control mask */ -#define MASK(bit) (0x1 << (bit)) -#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ -#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ -#define RD_WR 0x05 /* 0: Read 1: Write */ -#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ -#define EXEC_DONE 0x07 -#define D_SIZE_1 0x01 -#define D_SIZE_2 0x02 -#define D_SIZE_3 0x03 -#define D_SIZE_4 0x04 -#define FLASH_SEL MASK(DEV_NUM) - -#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) -#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) -#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - |MASK(A_SIZE) | D_SIZE_1) -#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) -#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) -#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) -#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) -#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) -#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) -#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) -#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) -#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) -#define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_1) -#define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_2) -#define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(A_SIZE)) +#define MASK(bit) (0x1 << (bit)) +#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ +#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ +#define RD_WR 0x05 /* 0: Read 1: Write */ +#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ +#define EXEC_DONE 0x07 +#define D_SIZE_1 0x01 +#define D_SIZE_2 0x02 +#define D_SIZE_3 0x03 +#define D_SIZE_4 0x04 +#define FLASH_SEL MASK(DEV_NUM) + +#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) +#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) +#define MASK_CMD_ADR_WR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1) +#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) +#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) +#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) +#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) +#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) +#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) +#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) +#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) +#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) +#define MASK_CMD_WR_1BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1) +#define MASK_CMD_WR_2BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2) +#define MASK_CMD_WR_ADR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE)) /******************************************************************************/ /* APM (Audio Processing Module) Registers */ -#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000) -#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004) -#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008) -#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C) -#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010) -#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014) -#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018) -#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C) -#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020) -#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C) -#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030) -#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034) -#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038) -#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C) -#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040) -#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044) -#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048) -#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C) -#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050) -#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054) -#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058) -#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C) -#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060) -#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064) -#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068) -#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C) -#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070) -#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074) +#define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000) +#define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004) +#define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008) +#define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C) +#define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010) +#define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014) +#define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018) +#define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C) +#define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020) +#define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C) +#define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030) +#define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034) +#define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038) +#define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C) +#define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040) +#define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044) +#define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048) +#define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C) +#define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050) +#define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054) +#define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058) +#define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C) +#define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060) +#define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064) +#define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068) +#define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C) +#define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070) +#define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074) /******************************************************************************/ /* APM register fields */ -#define NPCX_APM_SR_IRQ_PEND 6 -#define NPCX_APM_SR2_SMUTEIP 6 -#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2) -#define NPCX_APM_IMR_VAD_DTC_MASK 6 -#define NPCX_APM_IFR_VAD_DTC 6 -#define NPCX_APM_CR_APM_PD 0 -#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2) -#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2) -#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2) -#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4 -#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2) -#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4) -#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2) -#define NPCX_APM_FCR_ADC_ADC_HPF 6 -#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2) -#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2) -#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3) -#define NPCX_APM_CR_DMIC_PD_DMIC 7 -#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7 -#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6) -#define NPCX_APM_CR_MIX_MIX_LOAD 6 -#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8) -#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2) -#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2) -#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6) -#define NPCX_APM_GCR_ADCL_LRGID 7 -#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6) -#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6) -#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6) -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6) -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6 -#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7 -#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8) -#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4) -#define NPCX_ADC_AGC_0_AGC_STEREO 6 -#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4) -#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3) -#define NPCX_ADC_AGC_1_NG_EN 7 -#define NPCX_ADC_AGC_2_DCY FIELD(0, 4) -#define NPCX_ADC_AGC_2_ATK FIELD(4, 4) -#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5) -#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5) -#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6) -#define NPCX_APM_CR_VAD_VAD_LOAD 6 -#define NPCX_APM_CR_VAD_VAD_EN 7 -#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8) -#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0 -#define NPCX_APM_CR_TR_FAST_ON 7 -#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2) -#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3) -#define NPCX_VAD_0_VAD_ADC_WAKEUP 5 -#define NPCX_VAD_0_ZCD_EN 6 -#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5) -#define NPCX_APM_CONTROL_ADD FIELD(0, 6) -#define NPCX_APM_CONTROL_LOAD 6 +#define NPCX_APM_SR_IRQ_PEND 6 +#define NPCX_APM_SR2_SMUTEIP 6 +#define NPCX_APM_ICR_INTR_MODE FIELD(6, 2) +#define NPCX_APM_IMR_VAD_DTC_MASK 6 +#define NPCX_APM_IFR_VAD_DTC 6 +#define NPCX_APM_CR_APM_PD 0 +#define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2) +#define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2) +#define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2) +#define NPCX_APM_AICR_ADC_PD_AICR_ADC 4 +#define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2) +#define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4) +#define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2) +#define NPCX_APM_FCR_ADC_ADC_HPF 6 +#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2) +#define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2) +#define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3) +#define NPCX_APM_CR_DMIC_PD_DMIC 7 +#define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7 +#define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6) +#define NPCX_APM_CR_MIX_MIX_LOAD 6 +#define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8) +#define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2) +#define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2) +#define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6) +#define NPCX_APM_GCR_ADCL_LRGID 7 +#define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6) +#define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6) +#define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6) +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6) +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6 +#define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7 +#define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8) +#define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4) +#define NPCX_ADC_AGC_0_AGC_STEREO 6 +#define NPCX_ADC_AGC_1_HOLD FIELD(0, 4) +#define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3) +#define NPCX_ADC_AGC_1_NG_EN 7 +#define NPCX_ADC_AGC_2_DCY FIELD(0, 4) +#define NPCX_ADC_AGC_2_ATK FIELD(4, 4) +#define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5) +#define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5) +#define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6) +#define NPCX_APM_CR_VAD_VAD_LOAD 6 +#define NPCX_APM_CR_VAD_VAD_EN 7 +#define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8) +#define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0 +#define NPCX_APM_CR_TR_FAST_ON 7 +#define NPCX_VAD_0_VAD_INSEL FIELD(0, 2) +#define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3) +#define NPCX_VAD_0_VAD_ADC_WAKEUP 5 +#define NPCX_VAD_0_ZCD_EN 6 +#define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5) +#define NPCX_APM_CONTROL_ADD FIELD(0, 6) +#define NPCX_APM_CONTROL_LOAD 6 /******************************************************************************/ /* FMUL2 (Frequency Multiplier Module 2) Registers */ -#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000) -#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002) -#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004) -#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006) -#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008) -#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A) +#define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000) +#define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002) +#define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004) +#define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006) +#define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008) +#define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A) /******************************************************************************/ /* FMUL2 register fields */ -#define NPCX_FMUL2_FM2CTRL_LOAD2 0 -#define NPCX_FMUL2_FM2CTRL_LOCK2 2 -#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5 -#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6 -#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7 -#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6) -#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4) +#define NPCX_FMUL2_FM2CTRL_LOAD2 0 +#define NPCX_FMUL2_FM2CTRL_LOCK2 2 +#define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5 +#define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6 +#define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7 +#define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6) +#define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4) /******************************************************************************/ /* WOV (Wake-on-Voice) Registers */ -#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000) -#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004) -#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008) -#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C) -#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010) -#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014) -#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018) -#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C) -#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n)) -#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030) +#define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000) +#define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004) +#define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008) +#define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C) +#define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010) +#define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014) +#define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018) +#define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C) +#define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4 * n)) +#define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030) /******************************************************************************/ /* WOV register fields */ -#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0 -#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3 -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7 -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7) -#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7) -#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24 -#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25 -#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6) -#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6) -#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13 -#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14 -#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3) -#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8) -#define NPCX_WOV_STATUS_CFIFO_NE 8 -#define NPCX_WOV_STATUS_CFIFO_OIT 9 -#define NPCX_WOV_STATUS_CFIFO_OWT 10 -#define NPCX_WOV_STATUS_CFIFO_OVRN 11 -#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12 -#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13 -#define NPCX_WOV_STATUS_BITS FIELD(9, 6) -#define NPCX_WOV_INTEN_VAD_INTEN 0 -#define NPCX_WOV_INTEN_VAD_WKEN 1 -#define NPCX_WOV_INTEN_CFIFO_NE_IE 8 -#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9 -#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10 -#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11 -#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12 -#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13 -#define NPCX_WOV_APM_CTRL_APM_RST 0 -#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0 -#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4) -#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4) -#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15 -#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12) -#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4) -#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5) -#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5 -#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6 -#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9) -#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16) -#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16 -#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17 -#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18 -#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19 -#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20 -#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21 -#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22 -#define NPCX_WOV_I2S_CNTL0_I2S_TST 23 -#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 +#define NPCX_WOV_CLOCK_CNT_CLK_SEL 0 +#define NPCX_WOV_CLOCK_CNT_DMIC_EN 3 +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7 +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7) +#define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7) +#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24 +#define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25 +#define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6) +#define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6) +#define NPCX_WOV_FIFO_CNT_I2S_FFRST 13 +#define NPCX_WOV_FIFO_CNT_CORE_FFRST 14 +#define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3) +#define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8) +#define NPCX_WOV_STATUS_CFIFO_NE 8 +#define NPCX_WOV_STATUS_CFIFO_OIT 9 +#define NPCX_WOV_STATUS_CFIFO_OWT 10 +#define NPCX_WOV_STATUS_CFIFO_OVRN 11 +#define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12 +#define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13 +#define NPCX_WOV_STATUS_BITS FIELD(9, 6) +#define NPCX_WOV_INTEN_VAD_INTEN 0 +#define NPCX_WOV_INTEN_VAD_WKEN 1 +#define NPCX_WOV_INTEN_CFIFO_NE_IE 8 +#define NPCX_WOV_INTEN_CFIFO_OIT_IE 9 +#define NPCX_WOV_INTEN_CFIFO_OWT_WE 10 +#define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11 +#define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12 +#define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13 +#define NPCX_WOV_APM_CTRL_APM_RST 0 +#define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0 +#define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4) +#define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4) +#define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15 +#define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12) +#define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4) +#define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5) +#define NPCX_WOV_I2S_CNTL_I2S_TRIG 5 +#define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6 +#define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9) +#define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16) +#define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16 +#define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17 +#define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18 +#define NPCX_WOV_I2S_CNTL0_I2S_OPS 19 +#define NPCX_WOV_I2S_CNTL0_I2S_OPE 20 +#define NPCX_WOV_I2S_CNTL0_I2S_IPS 21 +#define NPCX_WOV_I2S_CNTL0_I2S_IPE 22 +#define NPCX_WOV_I2S_CNTL0_I2S_TST 23 +#define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 /******************************************************************************/ /* PS/2 registers */ -#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) -#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) -#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004) -#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006) -#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008) -#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A) +#define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) +#define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) +#define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004) +#define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006) +#define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008) +#define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A) /* PS/2 register field */ -#define NPCX_PS2_PSTAT_SOT 0 -#define NPCX_PS2_PSTAT_EOT 1 -#define NPCX_PS2_PSTAT_PERR 2 -#define NPCX_PS2_PSTAT_ACH FIELD(3, 3) -#define NPCX_PS2_PSTAT_RFERR 6 - -#define NPCX_PS2_PSCON_EN 0 -#define NPCX_PS2_PSCON_XMT 1 -#define NPCX_PS2_PSCON_HDRV FIELD(2, 2) -#define NPCX_PS2_PSCON_IDB FIELD(4, 3) -#define NPCX_PS2_PSCON_WPUED 7 - -#define NPCX_PS2_PSOSIG_WDAT0 0 -#define NPCX_PS2_PSOSIG_WDAT1 1 -#define NPCX_PS2_PSOSIG_WDAT2 2 -#define NPCX_PS2_PSOSIG_CLK0 3 -#define NPCX_PS2_PSOSIG_CLK1 4 -#define NPCX_PS2_PSOSIG_CLK2 5 -#define NPCX_PS2_PSOSIG_WDAT3 6 -#define NPCX_PS2_PSOSIG_CLK3 7 -#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? \ - ((n) + 3) : 7) -#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? \ - ((n) + 0) : 6) -#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \ - (BIT(NPCX_PS2_PSOSIG_CLK0) | \ - BIT(NPCX_PS2_PSOSIG_CLK1) | \ - BIT(NPCX_PS2_PSOSIG_CLK2) | \ - BIT(NPCX_PS2_PSOSIG_CLK3)) - -#define NPCX_PS2_PSISIG_RDAT0 0 -#define NPCX_PS2_PSISIG_RDAT1 1 -#define NPCX_PS2_PSISIG_RDAT2 2 -#define NPCX_PS2_PSISIG_RCLK0 3 -#define NPCX_PS2_PSISIG_RCLK1 4 -#define NPCX_PS2_PSISIG_RCLK2 5 -#define NPCX_PS2_PSISIG_RDAT3 6 -#define NPCX_PS2_PSISIG_RCLK3 7 -#define NPCX_PS2_PSIEN_SOTIE 0 -#define NPCX_PS2_PSIEN_EOTIE 1 -#define NPCX_PS2_PSIEN_PS2_WUE 4 -#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7 +#define NPCX_PS2_PSTAT_SOT 0 +#define NPCX_PS2_PSTAT_EOT 1 +#define NPCX_PS2_PSTAT_PERR 2 +#define NPCX_PS2_PSTAT_ACH FIELD(3, 3) +#define NPCX_PS2_PSTAT_RFERR 6 + +#define NPCX_PS2_PSCON_EN 0 +#define NPCX_PS2_PSCON_XMT 1 +#define NPCX_PS2_PSCON_HDRV FIELD(2, 2) +#define NPCX_PS2_PSCON_IDB FIELD(4, 3) +#define NPCX_PS2_PSCON_WPUED 7 + +#define NPCX_PS2_PSOSIG_WDAT0 0 +#define NPCX_PS2_PSOSIG_WDAT1 1 +#define NPCX_PS2_PSOSIG_WDAT2 2 +#define NPCX_PS2_PSOSIG_CLK0 3 +#define NPCX_PS2_PSOSIG_CLK1 4 +#define NPCX_PS2_PSOSIG_CLK2 5 +#define NPCX_PS2_PSOSIG_WDAT3 6 +#define NPCX_PS2_PSOSIG_CLK3 7 +#define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? ((n) + 3) : 7) +#define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? ((n) + 0) : 6) +#define NPCX_PS2_PSOSIG_CLK_MASK_ALL \ + (BIT(NPCX_PS2_PSOSIG_CLK0) | BIT(NPCX_PS2_PSOSIG_CLK1) | \ + BIT(NPCX_PS2_PSOSIG_CLK2) | BIT(NPCX_PS2_PSOSIG_CLK3)) + +#define NPCX_PS2_PSISIG_RDAT0 0 +#define NPCX_PS2_PSISIG_RDAT1 1 +#define NPCX_PS2_PSISIG_RDAT2 2 +#define NPCX_PS2_PSISIG_RCLK0 3 +#define NPCX_PS2_PSISIG_RCLK1 4 +#define NPCX_PS2_PSISIG_RCLK2 5 +#define NPCX_PS2_PSISIG_RDAT3 6 +#define NPCX_PS2_PSISIG_RCLK3 7 +#define NPCX_PS2_PSIEN_SOTIE 0 +#define NPCX_PS2_PSIEN_EOTIE 1 +#define NPCX_PS2_PSIEN_PS2_WUE 4 +#define NPCX_PS2_PSIEN_PS2_CLK_SEL 7 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC extern const enum gpio_signal hibernate_wake_pins[]; -- cgit v1.2.1 From 85313ff68589758e10b0011e431b1ac01ad5221f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:17 -0600 Subject: zephyr/include/dt-bindings/charger/intersil_isl9241.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I99bd391528cd4da9ea8f6c66af02a97969f63de4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730713 Reviewed-by: Jeremy Bettis --- zephyr/include/dt-bindings/charger/intersil_isl9241.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/include/dt-bindings/charger/intersil_isl9241.h b/zephyr/include/dt-bindings/charger/intersil_isl9241.h index 5a2742570e..c383fe8ce1 100644 --- a/zephyr/include/dt-bindings/charger/intersil_isl9241.h +++ b/zephyr/include/dt-bindings/charger/intersil_isl9241.h @@ -9,10 +9,10 @@ #define SWITCHING_FREQ_1420KHZ 0 #define SWITCHING_FREQ_1180KHZ 1 #define SWITCHING_FREQ_1020KHZ 2 -#define SWITCHING_FREQ_890KHZ 3 -#define SWITCHING_FREQ_808KHZ 4 -#define SWITCHING_FREQ_724KHZ 5 -#define SWITCHING_FREQ_656KHZ 6 -#define SWITCHING_FREQ_600KHZ 7 +#define SWITCHING_FREQ_890KHZ 3 +#define SWITCHING_FREQ_808KHZ 4 +#define SWITCHING_FREQ_724KHZ 5 +#define SWITCHING_FREQ_656KHZ 6 +#define SWITCHING_FREQ_600KHZ 7 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CHARGER_INTERSIL_ISL9241_H_ */ -- cgit v1.2.1 From 3431dc660b4048dd7d2372c20c1bf42de5bc8c93 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:19 -0600 Subject: board/terrador/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia7ea620c4e76cfa3595357f352d5fc841da91acb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729016 Reviewed-by: Jeremy Bettis --- board/terrador/board.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/board/terrador/board.c b/board/terrador/board.c index d6378d6aaa..eb5941f0e5 100644 --- a/board/terrador/board.c +++ b/board/terrador/board.c @@ -43,7 +43,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -71,7 +71,6 @@ union volteer_cbi_fw_config fw_config_defaults = { static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -173,8 +172,8 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -201,8 +200,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -270,7 +269,6 @@ __override void board_cbi_init(void) /* Reassign USB_C0_RT_RST_ODL */ bb_controls[USBC_PORT_C0].usb_ls_en_gpio = GPIO_USB_C0_LS_EN; bb_controls[USBC_PORT_C0].retimer_rst_gpio = GPIO_USB_C0_RT_RST_ODL; - } /******************************************************************************/ -- cgit v1.2.1 From 56c59a5824c760fee5219aa93ed2e0a6fa11314e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:29 -0600 Subject: baseboard/mtscp-rv32i/venc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49da266274f97029577256339dfcc5259ad251c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727931 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/venc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/baseboard/mtscp-rv32i/venc.c b/baseboard/mtscp-rv32i/venc.c index 09bb0cbd39..b2a6a89801 100644 --- a/baseboard/mtscp-rv32i/venc.c +++ b/baseboard/mtscp-rv32i/venc.c @@ -21,18 +21,20 @@ static void event_venc_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_VENC_SERVICE); } static struct consumer const event_venc_consumer; -static struct queue const event_venc_queue = QUEUE_DIRECT(8, - struct venc_msg, null_producer, event_venc_consumer); +static struct queue const event_venc_queue = + QUEUE_DIRECT(8, struct venc_msg, null_producer, event_venc_consumer); static struct consumer const event_venc_consumer = { .queue = &event_venc_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_venc_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void venc_h264_msg_handler(void *data) {} +void venc_h264_msg_handler(void *data) +{ +} #endif static void venc_h264_ipi_handler(int id, void *data, uint32_t len) -- cgit v1.2.1 From 5e7ae81dd60bc653d1f38375ad1c19cf78541fad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:19 -0600 Subject: zephyr/shim/src/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7219b41045cec95f7c53faed6df41e6b3ace2131 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730904 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/watchdog.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/src/watchdog.c b/zephyr/shim/src/watchdog.c index 00cd5c4c30..2f3c7b39a0 100644 --- a/zephyr/shim/src/watchdog.c +++ b/zephyr/shim/src/watchdog.c @@ -24,12 +24,12 @@ static void wdt_warning_handler(const struct device *wdt_dev, int channel_id) { /* TODO(b/176523207): watchdog warning message */ printk("Watchdog deadline is close!\n"); - #ifdef TEST_BUILD +#ifdef TEST_BUILD wdt_warning_triggered = true; - #endif +#endif #ifdef CONFIG_SOC_SERIES_MEC172X extern void cros_chip_wdt_handler(const struct device *wdt_dev, - int channel_id); + int channel_id); cros_chip_wdt_handler(wdt_dev, channel_id); #endif } -- cgit v1.2.1 From 2b37c4a2b1b349a0de546bbc83eea18b0fd205a5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:06 -0600 Subject: test/usb_tcpmv2_td_pd_ll_e5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I76b317fbb275163cddfc790a6b6fba06005d79a5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730554 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_ll_e5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_ll_e5.c b/test/usb_tcpmv2_td_pd_ll_e5.c index ae6409eb20..5796f91ce0 100644 --- a/test/usb_tcpmv2_td_pd_ll_e5.c +++ b/test/usb_tcpmv2_td_pd_ll_e5.c @@ -26,8 +26,8 @@ static int td_pd_ll_e5(enum pd_data_role data_role) /* * a) Run PROC.PD.E1 Bring-up according to the UUT role. */ - TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), - EC_SUCCESS, "%d"); + TEST_EQ(proc_pd_e1(data_role, INITIAL_AND_ALREADY_ATTACHED), EC_SUCCESS, + "%d"); /* * Make sure we are idle. Reject everything that is pending -- cgit v1.2.1 From 168bcb1dfd59b846b2508666fb2317b70452943c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:42 -0600 Subject: board/polyberry/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5af3ae614224879c343edcdfb3de2916674691d4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727748 Reviewed-by: Jeremy Bettis --- board/polyberry/board.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/polyberry/board.h b/board/polyberry/board.h index 8e55967bf5..5fab50286d 100644 --- a/board/polyberry/board.h +++ b/board/polyberry/board.h @@ -44,15 +44,15 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_UPDATE 1 -#define USB_IFACE_COUNT 2 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_UPDATE 1 +#define USB_IFACE_COUNT 2 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_UPDATE 2 -#define USB_EP_COUNT 3 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_UPDATE 2 +#define USB_EP_COUNT 3 /* This is not actually a Chromium EC so disable some features. */ #undef CONFIG_WATCHDOG_HELP -- cgit v1.2.1 From aa3ee976f725de3eb3efa7ebbf1d1ff7f34dc411 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:03 -0600 Subject: common/vboot/efs2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e633deb0503ceedda35dcbca9e99f38a619acdd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729806 Reviewed-by: Jeremy Bettis --- common/vboot/efs2.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/common/vboot/efs2.c b/common/vboot/efs2.c index a410c274f5..750be4c824 100644 --- a/common/vboot/efs2.c +++ b/common/vboot/efs2.c @@ -26,14 +26,14 @@ #include "vboot.h" #include "vboot_hash.h" -#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args) -#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args) +#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args) +#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args) static const char *boot_mode_to_string(uint8_t mode) { static const char *boot_mode_str[] = { - [BOOT_MODE_NORMAL] = "NORMAL", - [BOOT_MODE_NO_BOOT] = "NO_BOOT", + [BOOT_MODE_NORMAL] = "NORMAL", + [BOOT_MODE_NO_BOOT] = "NO_BOOT", }; if (mode < ARRAY_SIZE(boot_mode_str)) return boot_mode_str[mode]; @@ -46,8 +46,8 @@ static const char *boot_mode_to_string(uint8_t mode) */ static bool is_valid_cr50_response(enum cr50_comm_err code) { - return code != CR50_COMM_ERR_TIMEOUT - && (code >> 8) == CR50_COMM_ERR_PREFIX; + return code != CR50_COMM_ERR_TIMEOUT && + (code >> 8) == CR50_COMM_ERR_PREFIX; } __overridable void board_enable_packet_mode(bool enable) @@ -108,7 +108,7 @@ static enum cr50_comm_err send_to_cr50(const uint8_t *data, size_t size) while (!timeout) { int c = uart_getc(); if (c != -1) { - res.error = res.error | c << (i*8); + res.error = res.error | c << (i * 8); break; } msleep(1); @@ -159,7 +159,7 @@ static enum cr50_comm_err cmd_to_cr50(enum cr50_comm_cmd cmd, p->size = size; memcpy(p->data, data, size); p->crc = cros_crc8((uint8_t *)&p->type, - sizeof(p->type) + sizeof(p->size) + size); + sizeof(p->type) + sizeof(p->size) + size); do { rv = send_to_cr50((uint8_t *)&s, @@ -196,8 +196,8 @@ static enum cr50_comm_err set_boot_mode(uint8_t mode) enum cr50_comm_err rv; CPRINTS("Setting boot mode to %s(%d)", boot_mode_to_string(mode), mode); - rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE, - &mode, sizeof(enum boot_mode)); + rv = cmd_to_cr50(CR50_COMM_CMD_SET_BOOT_MODE, &mode, + sizeof(enum boot_mode)); if (rv != CR50_COMM_SUCCESS) CPRINTS("Failed to set boot mode"); return rv; @@ -274,8 +274,8 @@ void vboot_main(void) (system_get_reset_flags() & EC_RESET_FLAG_STAY_IN_RO)) { if (system_is_manual_recovery()) CPRINTS("In recovery mode"); - if (!IS_ENABLED(CONFIG_BATTERY) - && !IS_ENABLED(HAS_TASK_KEYSCAN)) { + if (!IS_ENABLED(CONFIG_BATTERY) && + !IS_ENABLED(HAS_TASK_KEYSCAN)) { /* * For Chromeboxes, we relax security by allowing PD in * RO. Attackers don't gain meaningful advantage on @@ -296,7 +296,7 @@ void vboot_main(void) if (!is_battery_ready()) { CPRINTS("Battery not ready or bad"); if (set_boot_mode(BOOT_MODE_NO_BOOT) == - CR50_COMM_SUCCESS) + CR50_COMM_SUCCESS) enable_pd(); } -- cgit v1.2.1 From 414a196dae0590a42781a03c298fa5081bb48f1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:12 -0600 Subject: builtin/stdarg.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7884b63a2dac266c8aff5a52d1f67f4162bb102e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729124 Reviewed-by: Jeremy Bettis --- builtin/stdarg.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/builtin/stdarg.h b/builtin/stdarg.h index 66ab940b16..babd96887a 100644 --- a/builtin/stdarg.h +++ b/builtin/stdarg.h @@ -13,10 +13,10 @@ */ #ifdef __GNUC__ -#define va_start(v, l) __builtin_va_start(v, l) -#define va_end(v) __builtin_va_end(v) -#define va_arg(v, l) __builtin_va_arg(v, l) -typedef __builtin_va_list va_list; +#define va_start(v, l) __builtin_va_start(v, l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v, l) __builtin_va_arg(v, l) +typedef __builtin_va_list va_list; #else #include_next #endif -- cgit v1.2.1 From 424362bebfb02b3ef98fdbb4298373556fea1971 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:42 -0600 Subject: driver/accelgyro_icm426xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iceda6f118c2d99bc51dbdf02fb2dd8fdad5d77eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729918 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm426xx.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/driver/accelgyro_icm426xx.c b/driver/accelgyro_icm426xx.c index 1c88d4b305..3dfcb8a071 100644 --- a/driver/accelgyro_icm426xx.c +++ b/driver/accelgyro_icm426xx.c @@ -27,11 +27,11 @@ #endif #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCELGYRO_ICM426XX_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v, const uint8_t *raw) @@ -45,8 +45,7 @@ static int icm426xx_normalize(const struct motion_sensor_t *s, intv3_t v, v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4); /* check if data is valid */ - if (v[X] == ICM426XX_INVALID_DATA && - v[Y] == ICM426XX_INVALID_DATA && + if (v[X] == ICM426XX_INVALID_DATA && v[Y] == ICM426XX_INVALID_DATA && v[Z] == ICM426XX_INVALID_DATA) { return EC_ERROR_INVAL; } @@ -76,8 +75,8 @@ static int icm426xx_check_sensor_stabilized(const struct motion_sensor_t *s, } /* use FIFO threshold interrupt on INT1 */ -#define ICM426XX_FIFO_INT_EN ICM426XX_FIFO_THS_INT1_EN -#define ICM426XX_FIFO_INT_STATUS ICM426XX_FIFO_THS_INT +#define ICM426XX_FIFO_INT_EN ICM426XX_FIFO_THS_INT1_EN +#define ICM426XX_FIFO_INT_STATUS ICM426XX_FIFO_THS_INT static int __maybe_unused icm426xx_enable_fifo(const struct motion_sensor_t *s, int enable) @@ -184,7 +183,8 @@ out_unlock: } static void __maybe_unused icm426xx_push_fifo_data(struct motion_sensor_t *s, - const uint8_t *raw, uint32_t ts) + const uint8_t *raw, + uint32_t ts) { intv3_t v; struct ec_response_motion_sensor_data vect; @@ -232,8 +232,8 @@ static int __maybe_unused icm426xx_load_fifo(struct motion_sensor_t *s, return ret; for (i = 0; i < count; i += size) { - size = icm_fifo_decode_packet(&st->fifo_buffer[i], - &accel, &gyro); + size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel, + &gyro); /* exit if error or FIFO is empty */ if (size <= 0) return -size; @@ -310,7 +310,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s) /* deassert async reset for proper INT pin operation */ ret = icm_field_update8(s, ICM426XX_REG_INT_CONFIG1, - ICM426XX_INT_ASYNC_RESET, 0); + ICM426XX_INT_ASYNC_RESET, 0); if (ret != EC_SUCCESS) return ret; @@ -322,8 +322,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s) */ val = ICM426XX_FIFO_PARTIAL_READ | ICM426XX_FIFO_WM_GT_TH; ret = icm_field_update8(s, ICM426XX_REG_FIFO_CONFIG1, - GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK, - val); + GENMASK(6, 5) | ICM426XX_FIFO_EN_MASK, val); if (ret != EC_SUCCESS) return ret; @@ -337,7 +336,7 @@ static int icm426xx_config_interrupt(const struct motion_sensor_t *s) return ret; } -#endif /* ACCELGYRO_ICM426XX_INT_ENABLE */ +#endif /* ACCELGYRO_ICM426XX_INT_ENABLE */ static int icm426xx_enable_sensor(const struct motion_sensor_t *s, int enable) { @@ -431,7 +430,7 @@ static int icm426xx_set_data_rate(const struct motion_sensor_t *s, int rate, if (rate > 0) { if ((normalized_rate < min_rate) || - (normalized_rate > max_rate)) + (normalized_rate > max_rate)) return EC_RES_INVALID_PARAM; } @@ -470,8 +469,7 @@ out_unlock: return ret; } -static int icm426xx_set_range(struct motion_sensor_t *s, int range, - int rnd) +static int icm426xx_set_range(struct motion_sensor_t *s, int range, int rnd) { int reg, ret, reg_val; int newrange; @@ -536,8 +534,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s, switch (s->type) { case MOTIONSENSE_TYPE_ACCEL: mutex_lock(s->mutex); - ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4, - raw, sizeof(raw)); + ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER4, raw, + sizeof(raw)); mutex_unlock(s->mutex); if (ret != EC_SUCCESS) return ret; @@ -554,8 +552,8 @@ static int icm426xx_get_hw_offset(const struct motion_sensor_t *s, break; case MOTIONSENSE_TYPE_GYRO: mutex_lock(s->mutex); - ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0, - raw, sizeof(raw)); + ret = icm_read_n(s, ICM426XX_REG_OFFSET_USER0, raw, + sizeof(raw)); mutex_unlock(s->mutex); if (ret != EC_SUCCESS) return ret; -- cgit v1.2.1 From cd5a6fa2ca48f8222076babb43f40867c0093ca7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:33 -0600 Subject: include/driver/retimer/anx7483_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c401c552f6e599bd97b4ca6b3509da1bf65310f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730276 Reviewed-by: Jeremy Bettis --- include/driver/retimer/anx7483_public.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index 8c3b9eaf60..c578bdf618 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -13,10 +13,10 @@ #include "usb_mux.h" /* I2C interface addresses */ -#define ANX7483_I2C_ADDR0_FLAGS 0x3E -#define ANX7483_I2C_ADDR1_FLAGS 0x38 -#define ANX7483_I2C_ADDR2_FLAGS 0x40 -#define ANX7483_I2C_ADDR3_FLAGS 0x44 +#define ANX7483_I2C_ADDR0_FLAGS 0x3E +#define ANX7483_I2C_ADDR1_FLAGS 0x38 +#define ANX7483_I2C_ADDR2_FLAGS 0x40 +#define ANX7483_I2C_ADDR3_FLAGS 0x44 /* Equalization tuning */ enum anx7483_eq_setting { -- cgit v1.2.1 From 3287c0a7216ff1d315954277602d7338787ae263 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:45 -0600 Subject: common/peripheral_charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46572fe5440a99775589f5a68f97b3b33ed3c538 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729685 Reviewed-by: Jeremy Bettis --- common/peripheral_charger.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/common/peripheral_charger.c b/common/peripheral_charger.c index 024379fe58..657c634e3a 100644 --- a/common/peripheral_charger.c +++ b/common/peripheral_charger.c @@ -23,7 +23,7 @@ /* Host event queue. Shared by all ports. */ static struct queue const host_events = - QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, uint32_t); + QUEUE_NULL(PCHG_EVENT_QUEUE_SIZE, uint32_t); struct mutex host_event_mtx; static void pchg_queue_event(struct pchg *ctx, enum pchg_event event) @@ -59,7 +59,7 @@ static void pchg_queue_host_event(struct pchg *ctx, uint32_t event) static const char *_text_state(enum pchg_state state) { /* TODO: Use "S%d" for normal build. */ - static const char * const state_names[] = EC_PCHG_STATE_TEXT; + static const char *const state_names[] = EC_PCHG_STATE_TEXT; BUILD_ASSERT(ARRAY_SIZE(state_names) == PCHG_STATE_COUNT); if (state >= sizeof(state_names)) @@ -71,7 +71,7 @@ static const char *_text_state(enum pchg_state state) static const char *_text_event(enum pchg_event event) { /* TODO: Use "S%d" for normal build. */ - static const char * const event_names[] = { + static const char *const event_names[] = { [PCHG_EVENT_NONE] = "NONE", [PCHG_EVENT_IRQ] = "IRQ", [PCHG_EVENT_RESET] = "RESET", @@ -118,7 +118,8 @@ static void _clear_port(struct pchg *ctx) } __overridable void board_pchg_power_on(int port, bool on) -{} +{ +} static enum pchg_state pchg_reset(struct pchg *ctx) { @@ -504,7 +505,7 @@ static int pchg_run(struct pchg *ctx) /* Don't wake up if the lid is closed. */ return 0; return (ctx->event == PCHG_EVENT_DEVICE_DETECTED || - ctx->event == PCHG_EVENT_DEVICE_LOST); + ctx->event == PCHG_EVENT_DEVICE_LOST); } if (ctx->event == PCHG_EVENT_CHARGE_UPDATE) @@ -538,7 +539,6 @@ void pchg_irq(enum gpio_signal signal) } } - static void pchg_startup(void) { struct pchg *ctx; @@ -630,8 +630,8 @@ static enum ec_status hc_pchg(struct host_cmd_handler_args *args) ctx = &pchgs[port]; - if (ctx->state == PCHG_STATE_CONNECTED - && ctx->battery_percent >= ctx->cfg->full_percent) + if (ctx->state == PCHG_STATE_CONNECTED && + ctx->battery_percent >= ctx->cfg->full_percent) r->state = PCHG_STATE_FULL; else r->state = ctx->state; @@ -643,7 +643,8 @@ static enum ec_status hc_pchg(struct host_cmd_handler_args *args) r->dropped_host_event_count = ctx->dropped_host_event_count; args->response_size = args->version == 1 ? - sizeof(struct ec_response_pchg) : sizeof(*r); + sizeof(struct ec_response_pchg) : + sizeof(*r); return EC_RES_SUCCESS; } @@ -758,11 +759,11 @@ static int cc_pchg(int argc, char **argv) ctx = &pchgs[port]; if (argc == 2) { - ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n", - port, _text_state(ctx->state), _text_event(ctx->event), + ccprintf("P%d STATE_%s EVENT_%s SOC=%d%%\n", port, + _text_state(ctx->state), _text_event(ctx->event), ctx->battery_percent); - ccprintf("error=0x%x dropped=%u fw_version=0x%x\n", - ctx->error, ctx->dropped_event_count, ctx->fw_version); + ccprintf("error=0x%x dropped=%u fw_version=0x%x\n", ctx->error, + ctx->dropped_event_count, ctx->fw_version); return EC_SUCCESS; } -- cgit v1.2.1 From f2f753867081a481c778778fb9ed22d3053dbad3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:49 -0600 Subject: chip/stm32/i2c-stm32l.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I78d96618a5eabe1f146a3dc49e7cd6a6e11331b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729518 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32l.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/chip/stm32/i2c-stm32l.c b/chip/stm32/i2c-stm32l.c index 74ecff192d..582266b14d 100644 --- a/chip/stm32/i2c-stm32l.c +++ b/chip/stm32/i2c-stm32l.c @@ -19,7 +19,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST @@ -35,23 +35,20 @@ * flips out. The battery may flip out and hold lines low for up to * 25ms. If we just wait it will eventually let them go. */ -#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (30 * MSEC) /* * Delay 5us in bitbang mode. That gives us roughly 5us low and 5us high or * a frequency of 100kHz. */ -#define I2C_BITBANG_HALF_CYCLE_US 5 +#define I2C_BITBANG_HALF_CYCLE_US 5 #ifdef CONFIG_I2C_DEBUG static void dump_i2c_reg(int port, const char *what) { CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s", - STM32_I2C_CR1(port), - STM32_I2C_CR2(port), - STM32_I2C_SR1(port), - STM32_I2C_SR2(port), - what); + STM32_I2C_CR1(port), STM32_I2C_CR2(port), STM32_I2C_SR1(port), + STM32_I2C_SR2(port), what); } #else static inline void dump_i2c_reg(int port, const char *what) @@ -164,10 +161,8 @@ static void i2c_init_port(const struct i2c_port_t *p) /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int started = (flags & I2C_XFER_START) ? 0 : 1; @@ -188,10 +183,8 @@ int chip_i2c_xfer(const int port, STM32_I2C_SR1(port) = 0; /* Clear start, stop, POS, ACK bits to get us in a known state */ - STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | - STM32_I2C_CR1_STOP | - STM32_I2C_CR1_POS | - STM32_I2C_CR1_ACK); + STM32_I2C_CR1(port) &= ~(STM32_I2C_CR1_START | STM32_I2C_CR1_STOP | + STM32_I2C_CR1_POS | STM32_I2C_CR1_ACK); /* No out bytes and no in bytes means just check for active */ if (out_bytes || !in_bytes) { @@ -291,7 +284,7 @@ int chip_i2c_xfer(const int port, } } - xfer_exit: +xfer_exit: /* On error, queue a stop condition */ if (rv) { flags |= I2C_XFER_STOP; @@ -305,7 +298,8 @@ int chip_i2c_xfer(const int port, if (rv == I2C_ERROR_FAILED_START) { const struct i2c_port_t *p = i2c_ports; CPRINTS("chip_i2c_xfer start error; " - "unwedging and resetting i2c %d", port); + "unwedging and resetting i2c %d", + port); i2c_unwedge(port); @@ -363,7 +357,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ @@ -419,6 +413,4 @@ static int command_i2cdump(int argc, char **argv) dump_i2c_reg(I2C_PORT_MASTER, "dump"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, - NULL, - "Dump I2C regs"); +DECLARE_CONSOLE_COMMAND(i2cdump, command_i2cdump, NULL, "Dump I2C regs"); -- cgit v1.2.1 From b8f88a38057ce7ef27feb8c0760d42eded6b0b03 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:51 -0600 Subject: board/berknip/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If979379a48297d0957715fcb4042f69cb78e543e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728055 Reviewed-by: Jeremy Bettis --- board/berknip/led.c | 58 ++++++++++++++++++++++++++++------------------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/board/berknip/led.c b/board/berknip/led.c index 79d691ffac..72e6e2c017 100644 --- a/board/berknip/led.c +++ b/board/berknip/led.c @@ -35,22 +35,19 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - RIGHT_PORT = 0, - LEFT_PORT -}; +enum led_port { RIGHT_PORT = 0, LEFT_PORT }; static void led_set_color_battery(int port, enum led_color color) { enum gpio_signal amber_led, white_led; amber_led = (port == RIGHT_PORT ? GPIO_LED_CHRG_L : - GPIO_C1_CHARGE_LED_AMBER_DB_L); + GPIO_C1_CHARGE_LED_AMBER_DB_L); white_led = (port == RIGHT_PORT ? GPIO_LED_FULL_L : - GPIO_C1_CHARGE_LED_WHITE_DB_L); + GPIO_C1_CHARGE_LED_WHITE_DB_L); switch (color) { case LED_WHITE: @@ -122,10 +119,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -141,18 +138,20 @@ static void led_set_battery(void) * design, blinking both two side battery white LEDs to indicate * system suspend with non-charging state. */ - if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && - charge_get_state() != PWR_STATE_CHARGE) { - + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) && + charge_get_state() != PWR_STATE_CHARGE) { power_ticks++; - led_set_color_battery(RIGHT_PORT, power_ticks - % LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS - ? LED_WHITE : LED_OFF); - led_set_color_battery(LEFT_PORT, power_ticks - % LED_TICKS_PER_CYCLE_S3 < POWER_LED_ON_S3_TICKS - ? LED_WHITE : LED_OFF); + led_set_color_battery(RIGHT_PORT, + power_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); + led_set_color_battery(LEFT_PORT, + power_ticks % LED_TICKS_PER_CYCLE_S3 < + POWER_LED_ON_S3_TICKS ? + LED_WHITE : + LED_OFF); return; } @@ -166,9 +165,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } @@ -177,17 +179,19 @@ static void led_set_battery(void) led_set_color_battery(LEFT_PORT, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From c9a0f940b1b5ab408be1b1ef5a4725323d393f44 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:33 -0600 Subject: zephyr/projects/it8xxx2_evb/include/gpio_map.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I00ee80ec1f268ae66143bdd20ac70db4a7b2a520 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730780 Reviewed-by: Jeremy Bettis --- zephyr/projects/it8xxx2_evb/include/gpio_map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/it8xxx2_evb/include/gpio_map.h b/zephyr/projects/it8xxx2_evb/include/gpio_map.h index b9d9026892..4ebfbe31b6 100644 --- a/zephyr/projects/it8xxx2_evb/include/gpio_map.h +++ b/zephyr/projects/it8xxx2_evb/include/gpio_map.h @@ -9,6 +9,6 @@ #include #include -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #endif /* __ZEPHYR_GPIO_MAP_H */ -- cgit v1.2.1 From 988c2bc3aff939934d57f29f1916e87c307fd186 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:46 -0600 Subject: board/nipperkin/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I210ba473253f14444081f574f9743640b71fe1d2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728750 Reviewed-by: Jeremy Bettis --- board/nipperkin/board.c | 89 ++++++++++++++++++++++--------------------------- 1 file changed, 39 insertions(+), 50 deletions(-) diff --git a/board/nipperkin/board.c b/board/nipperkin/board.c index 93db38b7ec..1b109187b6 100644 --- a/board/nipperkin/board.c +++ b/board/nipperkin/board.c @@ -45,16 +45,15 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal); * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); __override enum ec_error_list board_a1_ps8811_retimer_init(const struct usb_mux *me) @@ -63,51 +62,46 @@ board_a1_ps8811_retimer_init(const struct usb_mux *me) } __override int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_10G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_10G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX1EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX1EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_APTX2EQ_5G_LEVEL, - PS8818_EQ_LEVEL_UP_MASK, - PS8818_EQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_APTX2EQ_5G_LEVEL, + PS8818_EQ_LEVEL_UP_MASK, + PS8818_EQ_LEVEL_UP_19DB); if (rv) return rv; /* Set the RX input termination */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_RX_PHY, - PS8818_RX_INPUT_TERM_MASK, - PS8818_RX_INPUT_TERM_112_OHM); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_RX_PHY, + PS8818_RX_INPUT_TERM_MASK, + PS8818_RX_INPUT_TERM_112_OHM); if (rv) return rv; } @@ -115,11 +109,10 @@ __override int board_c1_ps8818_mux_set(const struct usb_mux *me, /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - rv = ps8818_i2c_field_update8(me, - PS8818_REG_PAGE1, - PS8818_REG1_DPEQ_LEVEL, - PS8818_DPEQ_LEVEL_UP_MASK, - PS8818_DPEQ_LEVEL_UP_19DB); + rv = ps8818_i2c_field_update8(me, PS8818_REG_PAGE1, + PS8818_REG1_DPEQ_LEVEL, + PS8818_DPEQ_LEVEL_UP_MASK, + PS8818_DPEQ_LEVEL_UP_19DB); if (rv) return rv; @@ -145,8 +138,7 @@ static void board_chipset_startup(void) if (get_board_version() > 1) pct2075_init(); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); int board_get_soc_temp_k(int idx, int *temp_k) { @@ -336,17 +328,15 @@ static void board_chipset_resume(void) ioex_set_level(IOEX_EN_PWR_HDMI, 1); ioex_set_level(IOEX_HDMI_DATA_EN, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - check_hdmi_hpd_status()); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + check_hdmi_hpd_status()); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); /* Called on AP suspend */ static void board_chipset_suspend(void) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); ioex_set_level(IOEX_HDMI_DATA_EN, 0); ioex_set_level(IOEX_EN_PWR_HDMI, 0); ioex_set_level(IOEX_USB_A1_PD_R_L, 0); @@ -499,10 +489,9 @@ static void hdmi_hpd_handler(void) int hpd = check_hdmi_hpd_status(); ccprints("HDMI HPD %d", hpd); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && hpd); + pi3hdx1204_enable( + I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd); } DECLARE_DEFERRED(hdmi_hpd_handler); -- cgit v1.2.1 From 8e8756c9a21db5e1f93a75a197b4bfe761ec8448 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:39 -0600 Subject: chip/mt_scp/mt818x/clock_mt8186.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I613390529d13ce159af4ef295cbe8f4332592fa2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729337 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/clock_mt8186.c | 59 ++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 26 deletions(-) diff --git a/chip/mt_scp/mt818x/clock_mt8186.c b/chip/mt_scp/mt818x/clock_mt8186.c index f5f25c773f..f7a4954232 100644 --- a/chip/mt_scp/mt818x/clock_mt8186.c +++ b/chip/mt_scp/mt818x/clock_mt8186.c @@ -14,11 +14,12 @@ #include "timer.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) -#define ULPOSC_CAL_MIN_VALUE 3 -#define ULPOSC_CAL_MAX_VALUE 60 -#define ULPOSC_CAL_START_VALUE ((ULPOSC_CAL_MIN_VALUE + ULPOSC_CAL_MAX_VALUE)/2) +#define ULPOSC_CAL_MIN_VALUE 3 +#define ULPOSC_CAL_MAX_VALUE 60 +#define ULPOSC_CAL_START_VALUE \ + ((ULPOSC_CAL_MIN_VALUE + ULPOSC_CAL_MAX_VALUE) / 2) static struct opp_ulposc_cfg { uint32_t osc; @@ -29,11 +30,19 @@ static struct opp_ulposc_cfg { uint32_t target_mhz; } opp[] = { { - .osc = 1, .target_mhz = ULPOSC2_CLOCK_MHZ, .div = 16, .iband = 4, .mod = 1, + .osc = 1, + .target_mhz = ULPOSC2_CLOCK_MHZ, + .div = 16, + .iband = 4, + .mod = 1, .cali = ULPOSC_CAL_START_VALUE, }, { - .osc = 0, .target_mhz = ULPOSC1_CLOCK_MHZ, .div = 12, .iband = 4, .mod = 1, + .osc = 0, + .target_mhz = ULPOSC1_CLOCK_MHZ, + .div = 12, + .iband = 4, + .mod = 1, .cali = ULPOSC_CAL_START_VALUE, }, }; @@ -94,13 +103,12 @@ static unsigned int clock_ulposc_measure_freq(int osc) int cnt; /* Before select meter clock input, bit[1:0] = b00 */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | - DBG_MODE_SET_CLOCK; + AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_MODE_MASK) | DBG_MODE_SET_CLOCK; /* Select source, bit[21:16] = clk_src */ - AP_CLK_DBG_CFG = (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | - (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : - DBG_BIST_SOURCE_ULPOSC2); + AP_CLK_DBG_CFG = + (AP_CLK_DBG_CFG & ~DBG_BIST_SOURCE_MASK) | + (osc == 0 ? DBG_BIST_SOURCE_ULPOSC1 : DBG_BIST_SOURCE_ULPOSC2); /* Set meter divisor to 1, bit[31:24] = b00000000 */ AP_CLK_MISC_CFG_0 = (AP_CLK_MISC_CFG_0 & ~MISC_METER_DIVISOR_MASK) | @@ -132,7 +140,7 @@ static unsigned int clock_ulposc_measure_freq(int osc) return result; } -#define CAL_MIS_RATE 40 +#define CAL_MIS_RATE 40 static int clock_ulposc_is_calibrated(struct opp_ulposc_cfg *opp) { uint32_t curr, target; @@ -231,13 +239,12 @@ static void clock_calibrate_ulposc(struct opp_ulposc_cfg *opp) clock_ulposc_config_default(opp); clock_high_enable(opp->osc); - /* Calibrate only if it is not accurate enough. */ if (!clock_ulposc_is_calibrated(opp)) opp->cali = clock_ulposc_process_cali(opp); - CPRINTF("osc:%u, target=%uMHz, cal:%u\n", - opp->osc, opp->target_mhz, opp->cali); + CPRINTF("osc:%u, target=%uMHz, cal:%u\n", opp->osc, opp->target_mhz, + opp->cali); } void scp_use_clock(enum scp_clock_source src) @@ -271,17 +278,18 @@ void clock_init(void) SCP_SYS_CTRL |= AUTO_DDREN; /* Set settle time */ - SCP_CLK_SYS_VAL = - (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | CLK_SYS_VAL(1); - SCP_CLK_HIGH_VAL = - (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | CLK_HIGH_VAL(1); - SCP_CLK_SLEEP_CTRL = - (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | VREQ_COUNTER_VAL(1); + SCP_CLK_SYS_VAL = (SCP_CLK_SYS_VAL & ~CLK_SYS_VAL_MASK) | + CLK_SYS_VAL(1); + SCP_CLK_HIGH_VAL = (SCP_CLK_HIGH_VAL & ~CLK_HIGH_VAL_MASK) | + CLK_HIGH_VAL(1); + SCP_CLK_SLEEP_CTRL = (SCP_CLK_SLEEP_CTRL & ~VREQ_COUNTER_MASK) | + VREQ_COUNTER_VAL(1); /* Set RG MUX to SW mode */ - AP_PLL_CON0 = LTECLKSQ_EN | LTECLKSQ_LPF_EN | LTECLKSQ_HYS_EN | LTECLKSQ_VOD_EN | - LTECLKSQ_HYS_SEL | CLKSQ_RESERVE | SSUSB26M_CK2_EN | SSUSB26M_CK_EN| - XTAL26M_CK_EN | ULPOSC_CTRL_SEL; + AP_PLL_CON0 = LTECLKSQ_EN | LTECLKSQ_LPF_EN | LTECLKSQ_HYS_EN | + LTECLKSQ_VOD_EN | LTECLKSQ_HYS_SEL | CLKSQ_RESERVE | + SSUSB26M_CK2_EN | SSUSB26M_CK_EN | XTAL26M_CK_EN | + ULPOSC_CTRL_SEL; /* Turn off ULPOSC2 */ SCP_CLK_ON_CTRL |= HIGH_CORE_DIS_SUB; @@ -323,8 +331,7 @@ static int command_ulposc(int argc, char *argv[]) int i; for (i = 0; i <= 1; ++i) - ccprintf("ULPOSC%u frequency: %u kHz\n", - i + 1, + ccprintf("ULPOSC%u frequency: %u kHz\n", i + 1, clock_ulposc_measure_freq(i) * 26 * 1000 / 1024); return EC_SUCCESS; } -- cgit v1.2.1 From c67eef2443c03e371eff79a89a402dd573647ab3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:51 -0600 Subject: zephyr/projects/corsola/src/krabby/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1524bba0c36b3c54602bd4f28c049669cf1274a6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730745 Reviewed-by: Jeremy Bettis --- zephyr/projects/corsola/src/krabby/usbc_config.c | 40 +++++++++++++----------- 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/usbc_config.c b/zephyr/projects/corsola/src/krabby/usbc_config.c index 73ecd2f7bd..45c0e71451 100644 --- a/zephyr/projects/corsola/src/krabby/usbc_config.c +++ b/zephyr/projects/corsola/src/krabby/usbc_config.c @@ -23,9 +23,9 @@ #include "variant_db_detection.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) void c0_bc12_interrupt(enum gpio_signal signal) { @@ -58,12 +58,12 @@ void ppc_interrupt(enum gpio_signal signal) int ppc_get_alert_status(int port) { if (port == 0) { - return gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(usb_c0_ppc_bc12_int_odl)) == 0; + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + usb_c0_ppc_bc12_int_odl)) == 0; } if (port == 1 && corsola_get_db_type() == CORSOLA_DB_TYPEC) { - return gpio_pin_get_dt( - GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl)) == 0; + return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS( + gpio_usb_c1_ppc_int_odl)) == 0; } return 0; @@ -73,15 +73,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } @@ -169,10 +173,10 @@ int board_set_active_charge_port(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) { - return ADC_VBUS_C0; + return ADC_VBUS_C0; } if (port == 1) { - return ADC_VBUS_C1; + return ADC_VBUS_C1; } CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; -- cgit v1.2.1 From db9740a65f52e055348aa2234c183ddc07cd443f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:33 -0600 Subject: board/sasukette/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id88b30e7efa2d2921824a1def5ef0a22b5ab515e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728911 Reviewed-by: Jeremy Bettis --- board/sasukette/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/sasukette/cbi_ssfc.c b/board/sasukette/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/sasukette/cbi_ssfc.c +++ b/board/sasukette/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 473173a86e38189cee59f5bfd4c17286af5eb064 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:25 -0600 Subject: baseboard/ite_evb/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea016239e78c9bfe8445a88b6d41a8977f3f5e7b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727906 Reviewed-by: Jeremy Bettis --- baseboard/ite_evb/baseboard.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/baseboard/ite_evb/baseboard.c b/baseboard/ite_evb/baseboard.c index 00459b12bc..c76204d35c 100644 --- a/baseboard/ite_evb/baseboard.c +++ b/baseboard/ite_evb/baseboard.c @@ -42,8 +42,10 @@ const struct fan_rpm fan_rpm_0 = { }; const struct fan_t fans[] = { - { .conf = &fan_conf_0, - .rpm = &fan_rpm_0, }, + { + .conf = &fan_conf_0, + .rpm = &fan_rpm_0, + }, }; BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS); @@ -123,11 +125,9 @@ __override struct keyboard_scan_config keyscan_config = { #if defined(CONFIG_SPI_FLASH_PORT) /* SPI devices */ const struct spi_device_t spi_devices[] = { - [CONFIG_SPI_FLASH_PORT] = { - .port = CONFIG_SPI_FLASH_PORT, - .div = 0, - .gpio_cs = -1 - }, + [CONFIG_SPI_FLASH_PORT] = { .port = CONFIG_SPI_FLASH_PORT, + .div = 0, + .gpio_cs = -1 }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); #endif @@ -139,9 +139,8 @@ static void board_init(void) DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_POWER_BUTTON_L, GPIO_LID_OPEN -}; +const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, + GPIO_LID_OPEN }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* -- cgit v1.2.1 From b4daf26acab0253fd1a0563e1e6e31f4c70a8ce5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:23 -0600 Subject: board/oak/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e3be02ae6661503a2613fb2cb0c5cfc5a7f23c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728788 Reviewed-by: Jeremy Bettis --- board/oak/battery.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/oak/battery.c b/board/oak/battery.c index fffd2f7763..3ff104bb07 100644 --- a/board/oak/battery.c +++ b/board/oak/battery.c @@ -11,7 +11,7 @@ #include "util.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define PARAM_CUT_OFF_LOW 0x10 +#define PARAM_CUT_OFF_LOW 0x10 #define PARAM_CUT_OFF_HIGH 0x00 static const struct battery_info info = { @@ -21,7 +21,7 @@ static const struct battery_info info = { /* * TODO(crosbug.com/p/44428): * In order to compatible with 2S battery, set min voltage as 6V rather - * than 9V. Should set voltage_min to 9V, when 2S battery + * than 9V. Should set voltage_min to 9V, when 2S battery * phased out. */ .voltage_min = 6000, @@ -57,10 +57,10 @@ static int cutoff(void) buf[2] = PARAM_CUT_OFF_HIGH; i2c_lock(I2C_PORT_BATTERY, 1); - rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - buf, 3, NULL, 0, I2C_XFER_SINGLE); - rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - buf, 3, NULL, 0, I2C_XFER_SINGLE); + rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3, + NULL, 0, I2C_XFER_SINGLE); + rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3, + NULL, 0, I2C_XFER_SINGLE); i2c_lock(I2C_PORT_BATTERY, 0); return rv; -- cgit v1.2.1 From 3814eb0c1d370b75850e2bb80786b0646bfbe13f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:02 -0600 Subject: board/ambassador/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62b06742f0e981a866f23a5d223878e140b9ea61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727102 Reviewed-by: Jeremy Bettis --- board/ambassador/board.h | 106 +++++++++++++++++++++++------------------------ 1 file changed, 51 insertions(+), 55 deletions(-) diff --git a/board/ambassador/board.h b/board/ambassador/board.h index c6aac262c5..135133a40d 100644 --- a/board/ambassador/board.h +++ b/board/ambassador/board.h @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -85,7 +85,7 @@ #define CONFIG_CPU_PROCHOT_ACTIVE_LOW /* Dedicated barreljack charger port */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT 1 @@ -104,15 +104,15 @@ #define CONFIG_INA3221 /* b/143501304 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Fan and temp. */ #define CONFIG_FANS 1 @@ -136,7 +136,7 @@ #define CONFIG_USB_PD_DECODE_SOP #undef CONFIG_USB_CHARGER #define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PID 0x5040 +#define CONFIG_USB_PID 0x5040 #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DISCHARGE_PPC @@ -156,7 +156,7 @@ #define CONFIG_USBC_VCONN #define CONFIG_USBC_VCONN_SWAP -#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_0 0 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS @@ -168,12 +168,12 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -191,11 +191,11 @@ enum charge_port { }; enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -220,11 +220,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_COUNT -}; - +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT }; /* Board specific handlers */ void board_reset_pd_mcu(void); @@ -238,20 +234,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) unsigned int ec_config_get_bj_power(void); @@ -261,30 +257,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 13b8788b76e52b868e83744d81c17aa61d5f9b43 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:55 -0600 Subject: include/mock/tcpm_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iea7180cdd3cef11f42db53bfa5b1e42580145e76 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730363 Reviewed-by: Jeremy Bettis --- include/mock/tcpm_mock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mock/tcpm_mock.h b/include/mock/tcpm_mock.h index 7fd89919f5..e5b67f2249 100644 --- a/include/mock/tcpm_mock.h +++ b/include/mock/tcpm_mock.h @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ - /* Mock for the TCPM interface */ +/* Mock for the TCPM interface */ #include "common.h" #include "tcpm/tcpm.h" -- cgit v1.2.1 From de13a628a95602c2275f30f8ae29eb1976f8c2c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:50 -0600 Subject: common/power_button.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If09d71beff891b1a4e5912dbe0cd1eaabc7db19b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729686 Reviewed-by: Jeremy Bettis --- common/power_button.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/common/power_button.c b/common/power_button.c index 20c468301c..0f84fbb3f1 100644 --- a/common/power_button.c +++ b/common/power_button.c @@ -21,14 +21,14 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SWITCH, outstr) -#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args) /* By default the power button is active low */ #ifndef CONFIG_POWER_BUTTON_FLAGS #define CONFIG_POWER_BUTTON_FLAGS 0 #endif -static int debounced_power_pressed; /* Debounced power button state */ +static int debounced_power_pressed; /* Debounced power button state */ static int simulate_power_pressed; static volatile int power_button_is_stable = 1; @@ -41,8 +41,11 @@ static const struct button_config power_button = { int power_button_signal_asserted(void) { - return !!(gpio_get_level(power_button.gpio) - == (power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ? 1 : 0); + return !!( + gpio_get_level(power_button.gpio) == + (power_button.flags & BUTTON_FLAG_ACTIVE_HIGH) ? + 1 : + 0); } /** @@ -93,8 +96,8 @@ int power_button_wait_for_release(int timeout_us) * the power button is debounced but not changed, or the power * button has not been debounced. */ - task_wait_event(MIN(power_button.debounce_us, - deadline.val - now.val)); + task_wait_event( + MIN(power_button.debounce_us, deadline.val - now.val)); } CPRINTS("%s released in time", power_button.name); @@ -164,8 +167,8 @@ static void power_button_change_deferred(void) debounced_power_pressed = new_pressed; power_button_is_stable = 1; - CPRINTS("%s %s", - power_button.name, new_pressed ? "pressed" : "released"); + CPRINTS("%s %s", power_button.name, + new_pressed ? "pressed" : "released"); /* Call hooks */ hook_notify(HOOK_POWER_BUTTON_CHANGE); @@ -197,7 +200,7 @@ void power_button_interrupt(enum gpio_signal signal) static int command_powerbtn(int argc, char **argv) { - int ms = 200; /* Press duration in ms */ + int ms = 200; /* Press duration in ms */ char *e; if (argc > 1) { @@ -221,6 +224,5 @@ static int command_powerbtn(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn, - "[msec]", +DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn, "[msec]", "Simulate power button press"); -- cgit v1.2.1 From 3b3af5df4d1ce4e8b768eb7e7ea9e379cca3726e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:57 -0600 Subject: board/dewatt/board_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9839e0025c0a80f6b9399cb1ebf36a00a1fa7cde Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728224 Reviewed-by: Jeremy Bettis --- board/dewatt/board_fw_config.h | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/board/dewatt/board_fw_config.h b/board/dewatt/board_fw_config.h index 1de417d77a..b51eddaa08 100644 --- a/board/dewatt/board_fw_config.h +++ b/board/dewatt/board_fw_config.h @@ -13,26 +13,25 @@ /* * USB Daughter Board (2 bits) */ -#define FW_CONFIG_USB_DB_OFFSET 0 -#define FW_CONFIG_USB_DB_WIDTH 2 -#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0 -#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1 +#define FW_CONFIG_USB_DB_OFFSET 0 +#define FW_CONFIG_USB_DB_WIDTH 2 +#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0 +#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1 /* * Form Factor (1 bits) */ -#define FW_CONFIG_FORM_FACTOR_OFFSET 2 -#define FW_CONFIG_FORM_FACTOR_WIDTH 1 -#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0 -#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1 +#define FW_CONFIG_FORM_FACTOR_OFFSET 2 +#define FW_CONFIG_FORM_FACTOR_WIDTH 1 +#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0 +#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1 /* * Keyboard Backlight (1 bit) */ -#define FW_CONFIG_KBLIGHT_OFFSET 3 -#define FW_CONFIG_KBLIGHT_WIDTH 1 -#define FW_CONFIG_KBLIGHT_NO 0 -#define FW_CONFIG_KBLIGHT_YES 1 - +#define FW_CONFIG_KBLIGHT_OFFSET 3 +#define FW_CONFIG_KBLIGHT_WIDTH 1 +#define FW_CONFIG_KBLIGHT_NO 0 +#define FW_CONFIG_KBLIGHT_YES 1 #endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */ -- cgit v1.2.1 From fc4484f9157989e0a355cd0dfdab1643fb3f93f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:47 -0600 Subject: test/mpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b45ec44c8d6f4e8edf260737baa7e666957de07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730529 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/mpu.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/test/mpu.c b/test/mpu.c index 25b2c58903..0ace4ee710 100644 --- a/test/mpu.c +++ b/test/mpu.c @@ -17,22 +17,18 @@ struct mpu_info { }; #if defined(CHIP_VARIANT_STM32F412) -struct mpu_info mpu_info = { - .has_mpu = true, - .num_mpu_regions = 8, - .mpu_is_unified = true -}; +struct mpu_info mpu_info = { .has_mpu = true, + .num_mpu_regions = 8, + .mpu_is_unified = true }; struct mpu_rw_regions expected_rw_regions = { .num_regions = 2, .addr = { 0x08060000, 0x08080000 }, .size = { 0x20000, 0x80000 } }; #elif defined(CHIP_VARIANT_STM32H7X3) -struct mpu_info mpu_info = { - .has_mpu = true, - .num_mpu_regions = 16, - .mpu_is_unified = true -}; +struct mpu_info mpu_info = { .has_mpu = true, + .num_mpu_regions = 16, + .mpu_is_unified = true }; struct mpu_rw_regions expected_rw_regions = { .num_regions = 1, .addr = { 0x08100000, @@ -75,7 +71,7 @@ test_static int test_mpu_update_region_valid_region(void) { volatile char data __maybe_unused; - char * const ram_base = (char * const)CONFIG_RAM_BASE; + char *const ram_base = (char *const)CONFIG_RAM_BASE; const uint8_t size_bit = 5; uint16_t mpu_attr = MPU_ATTR_NO_NO; -- cgit v1.2.1 From 4f8ea3f50e91232e3585fb3c3b981295498dc4c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:33 -0600 Subject: chip/stm32/dma-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I72732c67cd7820ec90869e277910ecf821418694 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729492 Reviewed-by: Jeremy Bettis --- chip/stm32/dma-stm32f4.c | 51 +++++++++++++++++++++++------------------------- 1 file changed, 24 insertions(+), 27 deletions(-) diff --git a/chip/stm32/dma-stm32f4.c b/chip/stm32/dma-stm32f4.c index 3374cff7fc..e817d6ad95 100644 --- a/chip/stm32/dma-stm32f4.c +++ b/chip/stm32/dma-stm32f4.c @@ -14,15 +14,15 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_DMA, outstr) -#define CPRINTF(format, args...) cprintf(CC_DMA, format, ## args) -#define CPRINTS(format, args...) cprints(CC_DMA, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_DMA, format, ##args) +#define CPRINTS(format, args...) cprints(CC_DMA, format, ##args) stm32_dma_regs_t *STM32_DMA_REGS[] = { STM32_DMA1_REGS, STM32_DMA2_REGS }; /* Callback data to use when IRQ fires */ static struct { - void (*cb)(void *); /* Callback function to call */ - void *cb_data; /* Callback data for callback function */ + void (*cb)(void *); /* Callback function to call */ + void *cb_data; /* Callback data for callback function */ } dma_irq[STM32_DMAS_TOTAL_COUNT]; /** @@ -91,7 +91,7 @@ void dma_disable_all(void) * @param flags DMA flags for the control register. */ static void prepare_stream(enum dma_channel stream, unsigned count, - void *periph, void *memory, unsigned flags) + void *periph, void *memory, unsigned flags) { stm32_dma_stream_t *dma_stream = dma_get_channel(stream); uint32_t ccr = STM32_DMA_CCR_PL_VERY_HIGH; @@ -128,18 +128,17 @@ void dma_prepare_tx(const struct dma_option *option, unsigned count, * we're preparing the stream for transmit. */ prepare_stream(option->channel, count, option->periph, (void *)memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_M2P | + option->flags); } -void dma_start_rx(const struct dma_option *option, unsigned count, - void *memory) +void dma_start_rx(const struct dma_option *option, unsigned count, void *memory) { stm32_dma_stream_t *stream = dma_get_channel(option->channel); prepare_stream(option->channel, count, option->periph, memory, - STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | - option->flags); + STM32_DMA_CCR_MINC | STM32_DMA_CCR_DIR_P2M | + option->flags); dma_go(stream); } @@ -176,10 +175,8 @@ void dma_dump(enum dma_channel stream) CPRINTF("scr=%x, sndtr=%x, spar=%x, sm0ar=%x, sfcr=%x\n", dma_stream->scr, dma_stream->sndtr, dma_stream->spar, dma_stream->sm0ar, dma_stream->sfcr); - CPRINTF("stream %d, isr=%x, ifcr=%x\n", - stream, - STM32_DMA_GET_ISR(stream), - STM32_DMA_GET_IFCR(stream)); + CPRINTF("stream %d, isr=%x, ifcr=%x\n", stream, + STM32_DMA_GET_ISR(stream), STM32_DMA_GET_IFCR(stream)); } void dma_check(enum dma_channel stream, char *buf) @@ -218,7 +215,7 @@ void dma_test(enum dma_channel stream) dma_stream->spar = (uint32_t)periph; dma_stream->sm0ar = (uint32_t)memory; dma_stream->sndtr = count; - dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; + dma_stream->sfcr &= ~STM32_DMA_SFCR_DMDIS; ctrl = STM32_DMA_CCR_PL_MEDIUM; dma_stream->scr = ctrl; @@ -300,17 +297,17 @@ void dma_clear_isr(enum dma_channel stream) } #ifdef CONFIG_DMA_DEFAULT_HANDLERS -#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) -#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) -#define DECLARE_DMA_IRQ(dma, x) \ - static void STM32_DMA_FCT(dma, x)(void) \ - { \ - dma_clear_isr(STM32_DMA_IDX(dma, x)); \ - if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ - (*dma_irq[STM32_DMA_IDX(dma, x)].cb) \ - (dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ - } \ - DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ +#define STM32_DMA_IDX(dma, x) CONCAT4(STM32_DMA, dma, _STREAM, x) +#define STM32_DMA_FCT(dma, x) CONCAT4(dma_, dma, _event_interrupt_stream_, x) +#define DECLARE_DMA_IRQ(dma, x) \ + static void STM32_DMA_FCT(dma, x)(void) \ + { \ + dma_clear_isr(STM32_DMA_IDX(dma, x)); \ + if (dma_irq[STM32_DMA_IDX(dma, x)].cb != NULL) \ + (*dma_irq[STM32_DMA_IDX(dma, x)].cb)( \ + dma_irq[STM32_DMA_IDX(dma, x)].cb_data); \ + } \ + DECLARE_IRQ(CONCAT4(STM32_IRQ_DMA, dma, _STREAM, x), \ STM32_DMA_FCT(dma, x), 1); DECLARE_DMA_IRQ(1, 0); -- cgit v1.2.1 From 72cff918fd753f6d44da94fe27b158f036f849ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:29 -0600 Subject: chip/mt_scp/mt8195/intc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I35fd024ab96b958d10afb810e7d68f0d4dda8560 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729356 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8195/intc.h | 248 +++++++++++++++++++++++----------------------- 1 file changed, 124 insertions(+), 124 deletions(-) diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h index ba77f069f2..ea4ca5c9a8 100644 --- a/chip/mt_scp/mt8195/intc.h +++ b/chip/mt_scp/mt8195/intc.h @@ -7,160 +7,160 @@ #define __CROS_EC_INTC_H /* INTC */ -#define SCP_INTC_IRQ_POL0 0xef001f20 -#define SCP_INTC_IRQ_POL1 0x044001dd -#define SCP_INTC_IRQ_POL2 0xffffdfe0 -#define SCP_INTC_IRQ_POL3 0xfffffff3 -#define SCP_INTC_GRP_LEN 4 -#define SCP_INTC_IRQ_COUNT 127 +#define SCP_INTC_IRQ_POL0 0xef001f20 +#define SCP_INTC_IRQ_POL1 0x044001dd +#define SCP_INTC_IRQ_POL2 0xffffdfe0 +#define SCP_INTC_IRQ_POL3 0xfffffff3 +#define SCP_INTC_GRP_LEN 4 +#define SCP_INTC_IRQ_COUNT 127 /* IRQ numbers */ -#define SCP_IRQ_GIPC_IN0 0 -#define SCP_IRQ_GIPC_IN1 1 -#define SCP_IRQ_GIPC_IN2 2 -#define SCP_IRQ_GIPC_IN3 3 +#define SCP_IRQ_GIPC_IN0 0 +#define SCP_IRQ_GIPC_IN1 1 +#define SCP_IRQ_GIPC_IN2 2 +#define SCP_IRQ_GIPC_IN3 3 /* 4 */ -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_AP_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 +#define SCP_IRQ_SPM 4 +#define SCP_IRQ_AP_CIRQ 5 +#define SCP_IRQ_EINT 6 +#define SCP_IRQ_PMIC 7 /* 8 */ -#define SCP_IRQ_UART0_TX 8 -#define SCP_IRQ_UART1_TX 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1_0 11 +#define SCP_IRQ_UART0_TX 8 +#define SCP_IRQ_UART1_TX 9 +#define SCP_IRQ_I2C0 10 +#define SCP_IRQ_I2C1_0 11 /* 12 */ -#define SCP_IRQ_BUS_DBG_TRACKER 12 -#define SCP_IRQ_CLK_CTRL 13 -#define SCP_IRQ_VOW 14 -#define SCP_IRQ_TIMER0 15 +#define SCP_IRQ_BUS_DBG_TRACKER 12 +#define SCP_IRQ_CLK_CTRL 13 +#define SCP_IRQ_VOW 14 +#define SCP_IRQ_TIMER0 15 /* 16 */ -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 +#define SCP_IRQ_TIMER1 16 +#define SCP_IRQ_TIMER2 17 +#define SCP_IRQ_TIMER3 18 +#define SCP_IRQ_TIMER4 19 /* 20 */ -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_OS_TIMER 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 +#define SCP_IRQ_TIMER5 20 +#define SCP_IRQ_OS_TIMER 21 +#define SCP_IRQ_UART0_RX 22 +#define SCP_IRQ_UART1_RX 23 /* 24 */ -#define SCP_IRQ_GDMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD_DSP 26 -#define SCP_IRQ_ADSP 27 +#define SCP_IRQ_GDMA 24 +#define SCP_IRQ_AUDIO 25 +#define SCP_IRQ_MD_DSP 26 +#define SCP_IRQ_ADSP 27 /* 28 */ -#define SCP_IRQ_CPU_TICK 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 +#define SCP_IRQ_CPU_TICK 28 +#define SCP_IRQ_SPI0 29 +#define SCP_IRQ_SPI1 30 +#define SCP_IRQ_SPI2 31 /* 32 */ -#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 -#define SCP_IRQ_DBG 33 -#define SCP_IRQ_GCE 34 -#define SCP_IRQ_MDP_GCE 35 +#define SCP_IRQ_NEW_INFRA_SYS_CIRQ 32 +#define SCP_IRQ_DBG 33 +#define SCP_IRQ_GCE 34 +#define SCP_IRQ_MDP_GCE 35 /* 36 */ -#define SCP_IRQ_VDEC 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_VDEC_LAT 38 -#define SCP_IRQ_VDEC1 39 +#define SCP_IRQ_VDEC 36 +#define SCP_IRQ_WDT 37 +#define SCP_IRQ_VDEC_LAT 38 +#define SCP_IRQ_VDEC1 39 /* 40 */ -#define SCP_IRQ_VDEC1_LAT 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_CLK_CTRL_CORE 42 -#define SCP_IRQ_CLK_CTRL2_CORE 43 +#define SCP_IRQ_VDEC1_LAT 40 +#define SCP_IRQ_INFRA 41 +#define SCP_IRQ_CLK_CTRL_CORE 42 +#define SCP_IRQ_CLK_CTRL2_CORE 43 /* 44 */ -#define SCP_IRQ_CLK_CTRL2 44 -#define SCP_IRQ_GIPC_IN4 45 /* HALT */ -#define SCP_IRQ_PERIBUS_TIMEOUT 46 -#define SCP_IRQ_INFRABUS_TIMEOUT 47 +#define SCP_IRQ_CLK_CTRL2 44 +#define SCP_IRQ_GIPC_IN4 45 /* HALT */ +#define SCP_IRQ_PERIBUS_TIMEOUT 46 +#define SCP_IRQ_INFRABUS_TIMEOUT 47 /* 48 */ -#define SCP_IRQ_MET0 48 -#define SCP_IRQ_MET1 49 -#define SCP_IRQ_MET2 50 -#define SCP_IRQ_MET3 51 +#define SCP_IRQ_MET0 48 +#define SCP_IRQ_MET1 49 +#define SCP_IRQ_MET2 50 +#define SCP_IRQ_MET3 51 /* 52 */ -#define SCP_IRQ_AP_WDT 52 -#define SCP_IRQ_L2TCM_SEC_VIO 53 -#define SCP_IRQ_VDEC_INT_LINE_CNT 54 -#define SCP_IRQ_VOW_DATAIN 55 +#define SCP_IRQ_AP_WDT 52 +#define SCP_IRQ_L2TCM_SEC_VIO 53 +#define SCP_IRQ_VDEC_INT_LINE_CNT 54 +#define SCP_IRQ_VOW_DATAIN 55 /* 56 */ -#define SCP_IRQ_I3C0_IBI_WAKE 56 -#define SCP_IRQ_I3C1_IBI_WAKE 57 -#define SCP_IRQ_VENC 58 -#define SCP_IRQ_APU_ENGINE 59 +#define SCP_IRQ_I3C0_IBI_WAKE 56 +#define SCP_IRQ_I3C1_IBI_WAKE 57 +#define SCP_IRQ_VENC 58 +#define SCP_IRQ_APU_ENGINE 59 /* 60 */ -#define SCP_IRQ_MBOX0 60 -#define SCP_IRQ_MBOX1 61 -#define SCP_IRQ_MBOX2 62 -#define SCP_IRQ_MBOX3 63 +#define SCP_IRQ_MBOX0 60 +#define SCP_IRQ_MBOX1 61 +#define SCP_IRQ_MBOX2 62 +#define SCP_IRQ_MBOX3 63 /* 64 */ -#define SCP_IRQ_MBOX4 64 -#define SCP_IRQ_SYS_CLK_REQ 65 -#define SCP_IRQ_BUS_REQ 66 -#define SCP_IRQ_APSRC_REQ 67 +#define SCP_IRQ_MBOX4 64 +#define SCP_IRQ_SYS_CLK_REQ 65 +#define SCP_IRQ_BUS_REQ 66 +#define SCP_IRQ_APSRC_REQ 67 /* 68 */ -#define SCP_IRQ_APU_MBOX 68 -#define SCP_IRQ_DEVAPC_SECURE_VIO 69 -#define SCP_IRQ_APDMA0 70 -#define SCP_IRQ_APDMA1 71 +#define SCP_IRQ_APU_MBOX 68 +#define SCP_IRQ_DEVAPC_SECURE_VIO 69 +#define SCP_IRQ_APDMA0 70 +#define SCP_IRQ_APDMA1 71 /* 72 */ -#define SCP_IRQ_APDMA2 72 -#define SCP_IRQ_APDMA3 73 -#define SCP_IRQ_APDMA4 74 -#define SCP_IRQ_APDMA5 75 +#define SCP_IRQ_APDMA2 72 +#define SCP_IRQ_APDMA3 73 +#define SCP_IRQ_APDMA4 74 +#define SCP_IRQ_APDMA5 75 /* 76 */ -#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76 -#define SCP_IRQ_HDMIRX_RESERVED 77 -#define SCP_IRQ_NNA0_0 78 -#define SCP_IRQ_NNA0_1 79 +#define SCP_IRQ_HDMIRX_PM_DVI_SQH 76 +#define SCP_IRQ_HDMIRX_RESERVED 77 +#define SCP_IRQ_NNA0_0 78 +#define SCP_IRQ_NNA0_1 79 /* 80 */ -#define SCP_IRQ_NNA0_2 80 -#define SCP_IRQ_NNA1_0 81 -#define SCP_IRQ_NNA1_1 82 -#define SCP_IRQ_NNA1_2 83 +#define SCP_IRQ_NNA0_2 80 +#define SCP_IRQ_NNA1_0 81 +#define SCP_IRQ_NNA1_1 82 +#define SCP_IRQ_NNA1_2 83 /* 84 */ -#define SCP_IRQ_JPEGENC 84 -#define SCP_IRQ_JPEGDEC 85 -#define SCP_IRQ_JPEGDEC_C2 86 -#define SCP_IRQ_VENC_C1 87 +#define SCP_IRQ_JPEGENC 84 +#define SCP_IRQ_JPEGDEC 85 +#define SCP_IRQ_JPEGDEC_C2 86 +#define SCP_IRQ_VENC_C1 87 /* 88 */ -#define SCP_IRQ_JPEGENC_C1 88 -#define SCP_IRQ_JPEGDEC_C1 89 -#define SCP_IRQ_HDMITX 90 -#define SCP_IRQ_HDMI2 91 +#define SCP_IRQ_JPEGENC_C1 88 +#define SCP_IRQ_JPEGDEC_C1 89 +#define SCP_IRQ_HDMITX 90 +#define SCP_IRQ_HDMI2 91 /* 92 */ -#define SCP_IRQ_EARC 92 -#define SCP_IRQ_CEC 93 -#define SCP_IRQ_HDMI_DEV_DET 94 -#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95 +#define SCP_IRQ_EARC 92 +#define SCP_IRQ_CEC 93 +#define SCP_IRQ_HDMI_DEV_DET 94 +#define SCP_IRQ_HDMIRX_OUT_ARM_PHY 95 /* 96 */ -#define SCP_IRQ_I2C2 96 -#define SCP_IRQ_I2C3 97 -#define SCP_IRQ_I3C2_IBI_WAKE 98 -#define SCP_IRQ_I3C3_IBI_WAKE 99 +#define SCP_IRQ_I2C2 96 +#define SCP_IRQ_I2C3 97 +#define SCP_IRQ_I3C2_IBI_WAKE 98 +#define SCP_IRQ_I3C3_IBI_WAKE 99 /* 100 */ -#define SCP_IRQ_SYS_I2C_0 100 -#define SCP_IRQ_SYS_I2C_1 101 -#define SCP_IRQ_SYS_I2C_2 102 -#define SCP_IRQ_SYS_I2C_3 103 +#define SCP_IRQ_SYS_I2C_0 100 +#define SCP_IRQ_SYS_I2C_1 101 +#define SCP_IRQ_SYS_I2C_2 102 +#define SCP_IRQ_SYS_I2C_3 103 /* 104 */ -#define SCP_IRQ_SYS_I2C_4 104 -#define SCP_IRQ_SYS_I2C_5 105 -#define SCP_IRQ_SYS_I2C_6 106 -#define SCP_IRQ_SYS_I2C_7 107 +#define SCP_IRQ_SYS_I2C_4 104 +#define SCP_IRQ_SYS_I2C_5 105 +#define SCP_IRQ_SYS_I2C_6 106 +#define SCP_IRQ_SYS_I2C_7 107 /* 108 */ -#define SCP_IRQ_DISP2ADSP_0 108 -#define SCP_IRQ_DISP2ADSP_1 109 -#define SCP_IRQ_DISP2ADSP_2 110 -#define SCP_IRQ_DISP2ADSP_3 111 +#define SCP_IRQ_DISP2ADSP_0 108 +#define SCP_IRQ_DISP2ADSP_1 109 +#define SCP_IRQ_DISP2ADSP_2 110 +#define SCP_IRQ_DISP2ADSP_3 111 /* 112 */ -#define SCP_IRQ_DISP2ADSP_4 112 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114 -#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115 +#define SCP_IRQ_DISP2ADSP_4 112 +#define SCP_IRQ_VDO1_DISP_MON2ADSP_0 113 +#define SCP_IRQ_VDO1_DISP_MON2ADSP_1 114 +#define SCP_IRQ_VDO1_DISP_MON2ADSP_2 115 /* 116 */ -#define SCP_IRQ_GCE1_SECURE 116 -#define SCP_IRQ_GCE_SECURE 117 +#define SCP_IRQ_GCE1_SECURE 116 +#define SCP_IRQ_GCE_SECURE 117 #endif /* __CROS_EC_INTC_H */ -- cgit v1.2.1 From ba0ee0629a9ef6ba2c567b3e1d2908e9c9f62d13 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:47 -0600 Subject: include/mock/rollback_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39b3b0bd0c33021e440a8b4df1cf8387a469d26d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730360 Reviewed-by: Jeremy Bettis --- include/mock/rollback_mock.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/include/mock/rollback_mock.h b/include/mock/rollback_mock.h index 576f87e6b9..e712881eb7 100644 --- a/include/mock/rollback_mock.h +++ b/include/mock/rollback_mock.h @@ -17,11 +17,12 @@ struct mock_ctrl_rollback { bool get_secret_fail; }; -#define MOCK_CTRL_DEFAULT_ROLLBACK \ -(struct mock_ctrl_rollback) { \ - .get_secret_fail = false, \ -} +#define MOCK_CTRL_DEFAULT_ROLLBACK \ + (struct mock_ctrl_rollback) \ + { \ + .get_secret_fail = false, \ + } extern struct mock_ctrl_rollback mock_ctrl_rollback; -#endif /* __MOCK_ROLLBACK_MOCK_H */ +#endif /* __MOCK_ROLLBACK_MOCK_H */ -- cgit v1.2.1 From ee9c1023da45d72b8b3bd1f827f1da7035b85d51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:32 -0600 Subject: board/homestar/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2d756b026667c81f8eaba3198f4cb32e760a48ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728468 Reviewed-by: Jeremy Bettis --- board/homestar/board.c | 157 ++++++++++++++++++------------------------------- 1 file changed, 57 insertions(+), 100 deletions(-) diff --git a/board/homestar/board.c b/board/homestar/board.c index 05c9759355..458ed8d1c4 100644 --- a/board/homestar/board.c +++ b/board/homestar/board.c @@ -39,10 +39,10 @@ #include "task.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -119,41 +119,31 @@ static void switchcap_interrupt(enum gpio_signal signal) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -161,45 +151,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, /* Base detection */ - [ADC_BASE_DET] = { - "BASE_DET", - NPCX_ADC_CH5, - ADC_MAX_VOLT, - ADC_READ_MAX + 1, - 0 - }, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -217,16 +187,12 @@ const struct ln9310_config_t ln9310_config = { /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -297,17 +263,13 @@ enum lid_accelgyro_type { static enum lid_accelgyro_type lid_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t lid_standard_ref_icm42607 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_lid_accel = { .name = "Lid Accel", @@ -502,9 +464,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); void board_hibernate(void) { @@ -514,8 +476,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -612,8 +573,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -641,7 +601,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -665,24 +624,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From 734367ada420f5a1f93adb93f25f0661a3dc95de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:18 -0600 Subject: driver/tcpm/rt1715.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icad273490e9837fa624b81e8dab66046566ab20e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730085 Reviewed-by: Jeremy Bettis --- driver/tcpm/rt1715.c | 39 +++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/driver/tcpm/rt1715.c b/driver/tcpm/rt1715.c index 7985ee95a3..f9d6cfa6cb 100644 --- a/driver/tcpm/rt1715.c +++ b/driver/tcpm/rt1715.c @@ -20,12 +20,11 @@ static int rt1715_polarity[CONFIG_USB_PD_PORT_MAX_COUNT]; static bool rt1715_initialized[CONFIG_USB_PD_PORT_MAX_COUNT]; - static int rt1715_enable_ext_messages(int port, int enable) { return tcpc_update8(port, RT1715_REG_VENDOR_5, - RT1715_REG_VENDOR_5_ENEXTMSG, - enable ? MASK_SET : MASK_CLR); + RT1715_REG_VENDOR_5_ENEXTMSG, + enable ? MASK_SET : MASK_CLR); } static int rt1715_tcpci_tcpm_init(int port) @@ -40,7 +39,7 @@ static int rt1715_tcpci_tcpm_init(int port) if (!(rt1715_initialized[port])) { /* RT1715 has a vendor-defined register reset */ rv = tcpc_update8(port, RT1715_REG_VENDOR_7, - RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET); + RT1715_REG_VENDOR_7_SOFT_RESET, MASK_SET); if (rv) return rv; rt1715_initialized[port] = true; @@ -48,7 +47,7 @@ static int rt1715_tcpci_tcpm_init(int port) } rv = tcpc_update8(port, RT1715_REG_VENDOR_5, - RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET); + RT1715_REG_VENDOR_5_SHUTDOWN_OFF, MASK_SET); if (rv) return rv; @@ -56,8 +55,8 @@ static int rt1715_tcpci_tcpm_init(int port) rt1715_enable_ext_messages(port, 1); rv = tcpc_write(port, RT1715_REG_I2CRST_CTRL, - (RT1715_REG_I2CRST_CTRL_EN | - RT1715_REG_I2CRST_CTRL_TOUT_200MS)); + (RT1715_REG_I2CRST_CTRL_EN | + RT1715_REG_I2CRST_CTRL_TOUT_200MS)); if (rv) return rv; @@ -71,27 +70,27 @@ static int rt1715_tcpci_tcpm_init(int port) * (min 250 us, max 500 us). */ rv = tcpc_write(port, RT1715_REG_TTCPC_FILTER, - RT1715_REG_TTCPC_FILTER_400US); + RT1715_REG_TTCPC_FILTER_400US); if (rv) return rv; rv = tcpc_write(port, RT1715_REG_DRP_TOGGLE_CYCLE, - RT1715_REG_DRP_TOGGLE_CYCLE_76MS); + RT1715_REG_DRP_TOGGLE_CYCLE_76MS); if (rv) return rv; /* PHY control */ /* Set PHY control registers to Richtek recommended values */ rv = tcpc_write(port, RT1715_REG_PHY_CTRL1, - (RT1715_REG_PHY_CTRL1_ENRETRY | - RT1715_REG_PHY_CTRL1_TRANSCNT_7 | - RT1715_REG_PHY_CTRL1_TRXFILTER_125NS)); + (RT1715_REG_PHY_CTRL1_ENRETRY | + RT1715_REG_PHY_CTRL1_TRANSCNT_7 | + RT1715_REG_PHY_CTRL1_TRXFILTER_125NS)); if (rv) return rv; /* Set PHY control registers to Richtek recommended values */ rv = tcpc_write(port, RT1715_REG_PHY_CTRL2, - RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US); + RT1715_REG_PHY_CTRL2_CDRTHRESH_2_58US); if (rv) return rv; @@ -113,14 +112,14 @@ static inline int rt1715_init_cc_params(int port, int cc_level) /* RXCC threshold : 0.55V */ en = RT1715_REG_BMCIO_RXDZEN_DISABLE; - sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA - | RT1715_REG_BMCIO_RXDZSEL_SEL; + sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA | + RT1715_REG_BMCIO_RXDZSEL_SEL; } else { /* RD threshold : 0.35V & RP threshold : 0.75V */ en = RT1715_REG_BMCIO_RXDZEN_ENABLE; - sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA - | RT1715_REG_BMCIO_RXDZSEL_SEL; + sel = RT1715_REG_BMCIO_RXDZSEL_OCCTRL_600MA | + RT1715_REG_BMCIO_RXDZSEL_SEL; } rv = tcpc_write(port, RT1715_REG_BMCIO_RXDZEN, en); @@ -131,7 +130,7 @@ static inline int rt1715_init_cc_params(int port, int cc_level) } static int rt1715_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int rv; @@ -235,7 +234,7 @@ const struct tcpm_drv rt1715_tcpm_drv = { .set_cc = &tcpci_tcpm_set_cc, .set_polarity = &rt1715_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif .set_vconn = &rt1715_set_vconn, .set_msg_header = &tcpci_tcpm_set_msg_header, @@ -257,5 +256,5 @@ const struct tcpm_drv rt1715_tcpm_drv = { #ifdef CONFIG_USB_PD_TCPC_LOW_POWER .enter_low_power_mode = &rt1715_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; -- cgit v1.2.1 From 997b67741174b90db38b1e5cd4bd8a5886383a6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:33 -0600 Subject: common/ec_features.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba14941da00feb7aed8a5fdfabf30e3d62b9ea7e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729624 Reviewed-by: Jeremy Bettis --- common/ec_features.c | 63 ++++++++++++++++++++++++++-------------------------- 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/common/ec_features.c b/common/ec_features.c index 6b84f6d2df..34e0c35c7c 100644 --- a/common/ec_features.c +++ b/common/ec_features.c @@ -15,97 +15,97 @@ uint32_t get_feature_flags0(void) { uint32_t result = 0 #ifdef CONFIG_FW_LIMITED_IMAGE - | EC_FEATURE_MASK_0(EC_FEATURE_LIMITED) + | EC_FEATURE_MASK_0(EC_FEATURE_LIMITED) #endif #ifdef CONFIG_FLASH_CROS - | EC_FEATURE_MASK_0(EC_FEATURE_FLASH) + | EC_FEATURE_MASK_0(EC_FEATURE_FLASH) #endif #ifdef CONFIG_FANS - | EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN) + | EC_FEATURE_MASK_0(EC_FEATURE_PWM_FAN) #endif #ifdef CONFIG_KEYBOARD_BACKLIGHT - | EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB) + | EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB) #endif #ifdef HAS_TASK_LIGHTBAR - | EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR) + | EC_FEATURE_MASK_0(EC_FEATURE_LIGHTBAR) #endif #ifdef CONFIG_LED_COMMON - | EC_FEATURE_MASK_0(EC_FEATURE_LED) + | EC_FEATURE_MASK_0(EC_FEATURE_LED) #endif #ifdef HAS_TASK_MOTIONSENSE - | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE) + | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE) #endif #ifdef HAS_TASK_KEYSCAN - | EC_FEATURE_MASK_0(EC_FEATURE_KEYB) + | EC_FEATURE_MASK_0(EC_FEATURE_KEYB) #endif #ifdef CONFIG_PSTORE - | EC_FEATURE_MASK_0(EC_FEATURE_PSTORE) + | EC_FEATURE_MASK_0(EC_FEATURE_PSTORE) #endif #ifdef CONFIG_HOSTCMD_X86 - | EC_FEATURE_MASK_0(EC_FEATURE_PORT80) + | EC_FEATURE_MASK_0(EC_FEATURE_PORT80) #endif #ifdef CONFIG_TEMP_SENSOR - | EC_FEATURE_MASK_0(EC_FEATURE_THERMAL) + | EC_FEATURE_MASK_0(EC_FEATURE_THERMAL) #endif #if (defined CONFIG_BACKLIGHT_LID) || (defined CONFIG_BACKLIGHT_REQ_GPIO) - | EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH) + | EC_FEATURE_MASK_0(EC_FEATURE_BKLIGHT_SWITCH) #endif #ifdef CONFIG_WIRELESS - | EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH) + | EC_FEATURE_MASK_0(EC_FEATURE_WIFI_SWITCH) #endif #ifdef CONFIG_HOSTCMD_EVENTS - | EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS) + | EC_FEATURE_MASK_0(EC_FEATURE_HOST_EVENTS) #endif #ifdef CONFIG_COMMON_GPIO - | EC_FEATURE_MASK_0(EC_FEATURE_GPIO) + | EC_FEATURE_MASK_0(EC_FEATURE_GPIO) #endif #ifdef CONFIG_I2C_CONTROLLER - | EC_FEATURE_MASK_0(EC_FEATURE_I2C) + | EC_FEATURE_MASK_0(EC_FEATURE_I2C) #endif #ifdef CONFIG_CHARGER - | EC_FEATURE_MASK_0(EC_FEATURE_CHARGER) + | EC_FEATURE_MASK_0(EC_FEATURE_CHARGER) #endif #if (defined CONFIG_BATTERY) - | EC_FEATURE_MASK_0(EC_FEATURE_BATTERY) + | EC_FEATURE_MASK_0(EC_FEATURE_BATTERY) #endif #ifdef CONFIG_BATTERY_SMART - | EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY) + | EC_FEATURE_MASK_0(EC_FEATURE_SMART_BATTERY) #endif #ifdef CONFIG_AP_HANG_DETECT - | EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT) + | EC_FEATURE_MASK_0(EC_FEATURE_HANG_DETECT) #endif #if 0 | EC_FEATURE_MASK_0(EC_FEATURE_PMU) /* Obsolete */ #endif #ifdef CONFIG_HOSTCMD_PD - | EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU) + | EC_FEATURE_MASK_0(EC_FEATURE_SUB_MCU) #endif #ifdef CONFIG_CHARGE_MANAGER - | EC_FEATURE_MASK_0(EC_FEATURE_USB_PD) + | EC_FEATURE_MASK_0(EC_FEATURE_USB_PD) #endif #ifdef CONFIG_ACCEL_FIFO - | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO) + | EC_FEATURE_MASK_0(EC_FEATURE_MOTION_SENSE_FIFO) #endif #ifdef CONFIG_VSTORE - | EC_FEATURE_MASK_0(EC_FEATURE_VSTORE) + | EC_FEATURE_MASK_0(EC_FEATURE_VSTORE) #endif #ifdef CONFIG_USB_MUX_VIRTUAL - | EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL) + | EC_FEATURE_MASK_0(EC_FEATURE_USBC_SS_MUX_VIRTUAL) #endif #ifdef CONFIG_HOSTCMD_RTC - | EC_FEATURE_MASK_0(EC_FEATURE_RTC) + | EC_FEATURE_MASK_0(EC_FEATURE_RTC) #endif #ifdef CONFIG_SPI_FP_PORT - | EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT) + | EC_FEATURE_MASK_0(EC_FEATURE_FINGERPRINT) #endif #ifdef HAS_TASK_CENTROIDING - | EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD) + | EC_FEATURE_MASK_0(EC_FEATURE_TOUCHPAD) #endif #if defined(HAS_TASK_RWSIG) || defined(HAS_TASK_RWSIG_RO) - | EC_FEATURE_MASK_0(EC_FEATURE_RWSIG) + | EC_FEATURE_MASK_0(EC_FEATURE_RWSIG) #endif #ifdef CONFIG_DEVICE_EVENT - | EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT) + | EC_FEATURE_MASK_0(EC_FEATURE_DEVICE_EVENT) #endif ; return board_override_feature_flags0(result); @@ -113,7 +113,8 @@ uint32_t get_feature_flags0(void) uint32_t get_feature_flags1(void) { - uint32_t result = EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS) + uint32_t result = + EC_FEATURE_MASK_1(EC_FEATURE_UNIFIED_WAKE_MASKS) #ifdef CONFIG_HOST_EVENT64 | EC_FEATURE_MASK_1(EC_FEATURE_HOST_EVENT64) #endif -- cgit v1.2.1 From e533761f6e3b6c8dcd8e7f1c2b55e2b0e14b407e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:53 -0600 Subject: common/mock/fp_sensor_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia7eb6d5270fa47569c5cac32abeb2e37dbf4d8b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729689 Reviewed-by: Jeremy Bettis --- common/mock/fp_sensor_mock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/common/mock/fp_sensor_mock.c b/common/mock/fp_sensor_mock.c index 363f092ff1..ef25e62afa 100644 --- a/common/mock/fp_sensor_mock.c +++ b/common/mock/fp_sensor_mock.c @@ -59,9 +59,8 @@ int fp_sensor_acquire_image_with_mode(uint8_t *image_data, int mode) return mock_ctrl_fp_sensor.fp_sensor_acquire_image_with_mode_return; } -int fp_finger_match(void *templ, uint32_t templ_count, - uint8_t *image, int32_t *match_index, - uint32_t *update_bitmap) +int fp_finger_match(void *templ, uint32_t templ_count, uint8_t *image, + int32_t *match_index, uint32_t *update_bitmap) { return mock_ctrl_fp_sensor.fp_finger_match_return; } -- cgit v1.2.1 From bde8a752142d613f74e98ed6b675c05ed6643c99 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:31 -0600 Subject: driver/temp_sensor/tmp411.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4608034f02abd47b0535ac1831193dd5109f3d8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729881 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp411.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/driver/temp_sensor/tmp411.c b/driver/temp_sensor/tmp411.c index 8db3f9a8d8..482f31a9c6 100644 --- a/driver/temp_sensor/tmp411.c +++ b/driver/temp_sensor/tmp411.c @@ -139,7 +139,7 @@ int tmp411_set_therm_limit(int channel, int limit_c, int hysteresis) return EC_ERROR_INVAL; if (hysteresis > TMP411_HYSTERESIS_HIGH_LIMIT || - hysteresis < TMP411_HYSTERESIS_LOW_LIMIT) + hysteresis < TMP411_HYSTERESIS_LOW_LIMIT) return EC_ERROR_INVAL; /* hysteresis must be less than high limit */ @@ -181,17 +181,14 @@ static void tmp411_temp_sensor_poll(void) if (get_temp(TMP411_REMOTE1, &temp_c) == EC_SUCCESS) temp_val_remote1 = C_TO_K(temp_c); - } DECLARE_HOOK(HOOK_SECOND, tmp411_temp_sensor_poll, HOOK_PRIO_TEMP_SENSOR); #ifdef CONFIG_CMD_TEMP_SENSOR -static void print_temps( - const char *name, - const int tmp411_temp_reg, - const int tmp411_therm_limit_reg, - const int tmp411_high_limit_reg, - const int tmp411_low_limit_reg) +static void print_temps(const char *name, const int tmp411_temp_reg, + const int tmp411_therm_limit_reg, + const int tmp411_high_limit_reg, + const int tmp411_low_limit_reg) { int value; @@ -219,15 +216,11 @@ static int print_status(void) { int value; - print_temps("Local", TMP411_LOCAL, - TMP411_LOCAL_THERM_LIMIT, - TMP411_LOCAL_HIGH_LIMIT_R, - TMP411_LOCAL_LOW_LIMIT_R); + print_temps("Local", TMP411_LOCAL, TMP411_LOCAL_THERM_LIMIT, + TMP411_LOCAL_HIGH_LIMIT_R, TMP411_LOCAL_LOW_LIMIT_R); - print_temps("Remote1", TMP411_REMOTE1, - TMP411_REMOTE1_THERM_LIMIT, - TMP411_REMOTE1_HIGH_LIMIT_R, - TMP411_REMOTE1_LOW_LIMIT_R); + print_temps("Remote1", TMP411_REMOTE1, TMP411_REMOTE1_THERM_LIMIT, + TMP411_REMOTE1_HIGH_LIMIT_R, TMP411_REMOTE1_LOW_LIMIT_R); ccprintf("\n"); @@ -285,8 +278,8 @@ static int command_tmp411(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", - offset, BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is %pb\n", offset, + BINARY_VALUE(data, 8)); return rv; } @@ -309,7 +302,8 @@ static int command_tmp411(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(tmp411, command_tmp411, +DECLARE_CONSOLE_COMMAND( + tmp411, command_tmp411, "[settemp|setbyte ] or [getbyte ] or" "[power ]. " "Temps in Celsius.", -- cgit v1.2.1 From 57862d65c0c5602249e554c846090e5db6fdec50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:22 -0600 Subject: zephyr/test/drivers/src/keyboard_scan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3d36cae0cffc63fda8742665df154c4fc22c68b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730990 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/keyboard_scan.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/test/drivers/src/keyboard_scan.c b/zephyr/test/drivers/src/keyboard_scan.c index 209c5320e0..7f1c860ad5 100644 --- a/zephyr/test/drivers/src/keyboard_scan.c +++ b/zephyr/test/drivers/src/keyboard_scan.c @@ -12,8 +12,7 @@ int emulate_keystate(int row, int col, int pressed) { - const struct device *dev = - DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw)); + const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(cros_kb_raw)); return emul_kb_raw_set_kbstate(dev, row, col, pressed); } -- cgit v1.2.1 From 0817ab7d0ea7018d0b9f8f3d3881145de4c9f65a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:02 -0600 Subject: board/pico/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6eb12c96ed37ee6eb37d0895f4af4f26b08dbda Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728824 Reviewed-by: Jeremy Bettis --- board/pico/board.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/board/pico/board.h b/board/pico/board.h index 6e1fe1d964..422a7d6814 100644 --- a/board/pico/board.h +++ b/board/pico/board.h @@ -50,7 +50,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -68,14 +68,14 @@ #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 IT83XX_I2C_CH_C -#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C -#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_SENSORS IT83XX_I2C_CH_B -#define I2C_PORT_ACCEL I2C_PORT_SENSORS -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 IT83XX_I2C_CH_C +#define I2C_PORT_TCPC0 IT83XX_I2C_CH_C +#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A +#define I2C_PORT_SENSORS IT83XX_I2C_CH_B +#define I2C_PORT_ACCEL I2C_PORT_SENSORS +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT @@ -129,7 +129,7 @@ enum battery_type { /* support factory keyboard test */ #define CONFIG_KEYBOARD_FACTORY_TEST -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV extern const int keyboard_factory_scan_pins[][2]; extern const int keyboard_factory_scan_pins_used; -- cgit v1.2.1 From bf2404054cf046933292a51ff5df500d9871a3a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:08 -0600 Subject: include/power_led.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d9123dbf223f90f96528c30802d95049d6ccbf8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730391 Reviewed-by: Jeremy Bettis --- include/power_led.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/power_led.h b/include/power_led.h index 05ea7ead3c..2966dbfe27 100644 --- a/include/power_led.h +++ b/include/power_led.h @@ -28,7 +28,9 @@ void powerled_set_state(enum powerled_state state); #else -static inline void powerled_set_state(enum powerled_state state) {} +static inline void powerled_set_state(enum powerled_state state) +{ +} #endif -- cgit v1.2.1 From 170052ec49fae4c8a8f78915c7346e3e8e49fd69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:41 -0600 Subject: driver/charger/bq24773.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie19bacf2ea920b7e01b720e61f53dfddab725b01 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729960 Reviewed-by: Jeremy Bettis --- driver/charger/bq24773.h | 116 +++++++++++++++++++++++------------------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/driver/charger/bq24773.h b/driver/charger/bq24773.h index 46f8939036..d0bc0e0953 100644 --- a/driver/charger/bq24773.h +++ b/driver/charger/bq24773.h @@ -12,78 +12,78 @@ #include "i2c.h" /* I2C address */ -#define BQ24770_ADDR_FLAGS 0x09 -#define BQ24773_ADDR_FLAGS 0x6a +#define BQ24770_ADDR_FLAGS 0x09 +#define BQ24773_ADDR_FLAGS 0x6a /* Chip specific commands */ -#define BQ24770_CHARGE_OPTION0 0x12 -#define BQ24770_CHARGE_OPTION1 0x3B -#define BQ24770_CHARGE_OPTION2 0x38 -#define BQ24770_PROCHOT_OPTION0 0x3C -#define BQ24770_PROCHOT_OPTION1 0x3D -#define BQ24770_CHARGE_CURRENT 0x14 -#define BQ24770_MAX_CHARGE_VOLTAGE 0x15 -#define BQ24770_MIN_SYSTEM_VOLTAGE 0x3E -#define BQ24770_INPUT_CURRENT 0x3F -#define BQ24770_MANUFACTURE_ID 0xFE -#define BQ24770_DEVICE_ADDRESS 0xFF +#define BQ24770_CHARGE_OPTION0 0x12 +#define BQ24770_CHARGE_OPTION1 0x3B +#define BQ24770_CHARGE_OPTION2 0x38 +#define BQ24770_PROCHOT_OPTION0 0x3C +#define BQ24770_PROCHOT_OPTION1 0x3D +#define BQ24770_CHARGE_CURRENT 0x14 +#define BQ24770_MAX_CHARGE_VOLTAGE 0x15 +#define BQ24770_MIN_SYSTEM_VOLTAGE 0x3E +#define BQ24770_INPUT_CURRENT 0x3F +#define BQ24770_MANUFACTURE_ID 0xFE +#define BQ24770_DEVICE_ADDRESS 0xFF -#define BQ24773_CHARGE_OPTION0 0x00 -#define BQ24773_CHARGE_OPTION1 0x02 -#define BQ24773_PROCHOT_OPTION0 0x04 -#define BQ24773_PROCHOT_OPTION1 0x06 -#define BQ24773_PROCHOT_STATUS 0x08 -#define BQ24773_DEVICE_ADDRESS 0x09 -#define BQ24773_CHARGE_CURRENT 0x0A -#define BQ24773_MAX_CHARGE_VOLTAGE 0x0C -#define BQ24773_MIN_SYSTEM_VOLTAGE 0x0E -#define BQ24773_INPUT_CURRENT 0x0F -#define BQ24773_CHARGE_OPTION2 0x10 +#define BQ24773_CHARGE_OPTION0 0x00 +#define BQ24773_CHARGE_OPTION1 0x02 +#define BQ24773_PROCHOT_OPTION0 0x04 +#define BQ24773_PROCHOT_OPTION1 0x06 +#define BQ24773_PROCHOT_STATUS 0x08 +#define BQ24773_DEVICE_ADDRESS 0x09 +#define BQ24773_CHARGE_CURRENT 0x0A +#define BQ24773_MAX_CHARGE_VOLTAGE 0x0C +#define BQ24773_MIN_SYSTEM_VOLTAGE 0x0E +#define BQ24773_INPUT_CURRENT 0x0F +#define BQ24773_CHARGE_OPTION2 0x10 /* Option bits */ -#define OPTION0_CHARGE_INHIBIT BIT(0) -#define OPTION0_LEARN_ENABLE BIT(5) -#define OPTION0_SWITCHING_FREQ_MASK (3 << 8) -#define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8) -#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8) -#define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8) -#define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8) +#define OPTION0_CHARGE_INHIBIT BIT(0) +#define OPTION0_LEARN_ENABLE BIT(5) +#define OPTION0_SWITCHING_FREQ_MASK (3 << 8) +#define OPTION0_SWITCHING_FREQ_600KHZ (0 << 8) +#define OPTION0_SWITCHING_FREQ_800KHZ BIT(8) +#define OPTION0_SWITCHING_FREQ_1000KHZ (2 << 8) +#define OPTION0_SWITCHING_FREQ_1200KHZ (3 << 8) -#define OPTION2_EN_EXTILIM BIT(7) +#define OPTION2_EN_EXTILIM BIT(7) /* Prochot Option bits */ -#define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */ +#define PROCHOT_OPTION1_SELECTOR_MASK 0x7f /* [6:0] PROCHOT SELECTOR */ #ifdef CONFIG_CHARGER_BQ24770 - #define CHARGER_NAME "bq24770" - #define I2C_ADDR_CHARGER_FLAGS BQ24770_ADDR_FLAGS +#define CHARGER_NAME "bq24770" +#define I2C_ADDR_CHARGER_FLAGS BQ24770_ADDR_FLAGS - #define REG_CHARGE_OPTION0 BQ24770_CHARGE_OPTION0 - #define REG_CHARGE_OPTION1 BQ24770_CHARGE_OPTION1 - #define REG_CHARGE_OPTION2 BQ24770_CHARGE_OPTION2 - #define REG_PROCHOT_OPTION0 BQ24770_PROCHOT_OPTION0 - #define REG_PROCHOT_OPTION1 BQ24770_PROCHOT_OPTION1 - #define REG_CHARGE_CURRENT BQ24770_CHARGE_CURRENT - #define REG_MAX_CHARGE_VOLTAGE BQ24770_MAX_CHARGE_VOLTAGE - #define REG_MIN_SYSTEM_VOLTAGE BQ24770_MIN_SYSTEM_VOLTAGE - #define REG_INPUT_CURRENT BQ24770_INPUT_CURRENT - #define REG_MANUFACTURE_ID BQ24770_MANUFACTURE_ID - #define REG_DEVICE_ADDRESS BQ24770_DEVICE_ADDRESS +#define REG_CHARGE_OPTION0 BQ24770_CHARGE_OPTION0 +#define REG_CHARGE_OPTION1 BQ24770_CHARGE_OPTION1 +#define REG_CHARGE_OPTION2 BQ24770_CHARGE_OPTION2 +#define REG_PROCHOT_OPTION0 BQ24770_PROCHOT_OPTION0 +#define REG_PROCHOT_OPTION1 BQ24770_PROCHOT_OPTION1 +#define REG_CHARGE_CURRENT BQ24770_CHARGE_CURRENT +#define REG_MAX_CHARGE_VOLTAGE BQ24770_MAX_CHARGE_VOLTAGE +#define REG_MIN_SYSTEM_VOLTAGE BQ24770_MIN_SYSTEM_VOLTAGE +#define REG_INPUT_CURRENT BQ24770_INPUT_CURRENT +#define REG_MANUFACTURE_ID BQ24770_MANUFACTURE_ID +#define REG_DEVICE_ADDRESS BQ24770_DEVICE_ADDRESS #elif defined(CONFIG_CHARGER_BQ24773) - #define CHARGER_NAME "bq24773" - #define I2C_ADDR_CHARGER_FLAGS BQ24773_ADDR_FLAGS +#define CHARGER_NAME "bq24773" +#define I2C_ADDR_CHARGER_FLAGS BQ24773_ADDR_FLAGS - #define REG_CHARGE_OPTION0 BQ24773_CHARGE_OPTION0 - #define REG_CHARGE_OPTION1 BQ24773_CHARGE_OPTION1 - #define REG_CHARGE_OPTION2 BQ24773_CHARGE_OPTION2 - #define REG_PROCHOT_OPTION0 BQ24773_PROCHOT_OPTION0 - #define REG_PROCHOT_OPTION1 BQ24773_PROCHOT_OPTION1 - #define REG_CHARGE_CURRENT BQ24773_CHARGE_CURRENT - #define REG_MAX_CHARGE_VOLTAGE BQ24773_MAX_CHARGE_VOLTAGE - #define REG_MIN_SYSTEM_VOLTAGE BQ24773_MIN_SYSTEM_VOLTAGE - #define REG_INPUT_CURRENT BQ24773_INPUT_CURRENT - #define REG_DEVICE_ADDRESS BQ24773_DEVICE_ADDRESS +#define REG_CHARGE_OPTION0 BQ24773_CHARGE_OPTION0 +#define REG_CHARGE_OPTION1 BQ24773_CHARGE_OPTION1 +#define REG_CHARGE_OPTION2 BQ24773_CHARGE_OPTION2 +#define REG_PROCHOT_OPTION0 BQ24773_PROCHOT_OPTION0 +#define REG_PROCHOT_OPTION1 BQ24773_PROCHOT_OPTION1 +#define REG_CHARGE_CURRENT BQ24773_CHARGE_CURRENT +#define REG_MAX_CHARGE_VOLTAGE BQ24773_MAX_CHARGE_VOLTAGE +#define REG_MIN_SYSTEM_VOLTAGE BQ24773_MIN_SYSTEM_VOLTAGE +#define REG_INPUT_CURRENT BQ24773_INPUT_CURRENT +#define REG_DEVICE_ADDRESS BQ24773_DEVICE_ADDRESS #endif extern const struct charger_drv bq2477x_drv; -- cgit v1.2.1 From 60e28279fa8ab47cac9ef9b882db2b5a25139a83 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:28 -0600 Subject: board/corori2/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fe9f971d806555c2097fb92600304d7c956cd04 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728164 Reviewed-by: Jeremy Bettis --- board/corori2/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/corori2/cbi_ssfc.h b/board/corori2/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/corori2/cbi_ssfc.h +++ b/board/corori2/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 23cb5c539ddad52fc2092c1398d0f4ad92199cba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:13 -0600 Subject: zephyr/emul/emul_lis2dw12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4438723ba42412f522a60bc1a8c1557b038ec1c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730693 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_lis2dw12.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/emul/emul_lis2dw12.c b/zephyr/emul/emul_lis2dw12.c index 38bf6572b1..0d99585b8e 100644 --- a/zephyr/emul/emul_lis2dw12.c +++ b/zephyr/emul/emul_lis2dw12.c @@ -295,21 +295,21 @@ void lis2dw12_emul_clear_accel_reading(const struct emul *emul) data->status_reg &= ~LIS2DW12_STS_DRDY_UP; } -#define INIT_LIS2DW12(n) \ +#define INIT_LIS2DW12(n) \ static struct lis2dw12_emul_data lis2dw12_emul_data_##n = { \ .common = { \ .write_byte = lis2dw12_emul_write_byte, \ .read_byte = lis2dw12_emul_read_byte, \ }, \ - }; \ + }; \ static const struct lis2dw12_emul_cfg lis2dw12_emul_cfg_##n = { \ .common = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ - }; \ - EMUL_DEFINE(emul_lis2dw12_init, DT_DRV_INST(n), \ + }; \ + EMUL_DEFINE(emul_lis2dw12_init, DT_DRV_INST(n), \ &lis2dw12_emul_cfg_##n, &lis2dw12_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(INIT_LIS2DW12) -- cgit v1.2.1 From 4fdb92426654f22c0b620603bab85701a6fb9c34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:03 -0600 Subject: chip/mt_scp/rv32i_common/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I400e070c61808ecbab98522d355cdb4394c2263e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729362 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/registers.h | 320 ++++++++++++++++++----------------- 1 file changed, 161 insertions(+), 159 deletions(-) diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index afe706948e..86cec4b887 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -14,200 +14,202 @@ #define UNIMPLEMENTED_GPIO_BANK 0 -#define SCP_REG_BASE 0x70000000 +#define SCP_REG_BASE 0x70000000 /* clock control */ -#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) +#define SCP_CLK_CTRL_BASE (SCP_REG_BASE + 0x21000) /* system clock counter value */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) -#define CLK_SYS_VAL_MASK (0x3ff << 0) -#define CLK_SYS_VAL_VAL(v) ((v) & CLK_SYS_VAL_MASK) +#define SCP_CLK_SYS_VAL REG32(SCP_CLK_CTRL_BASE + 0x0014) +#define CLK_SYS_VAL_MASK (0x3ff << 0) +#define CLK_SYS_VAL_VAL(v) ((v)&CLK_SYS_VAL_MASK) /* ULPOSC clock counter value */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018) -#define CLK_HIGH_VAL_MASK (0x1f << 0) -#define CLK_HIGH_VAL_VAL(v) ((v) & CLK_HIGH_VAL_MASK) +#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_CTRL_BASE + 0x0018) +#define CLK_HIGH_VAL_MASK (0x1f << 0) +#define CLK_HIGH_VAL_VAL(v) ((v)&CLK_HIGH_VAL_MASK) /* sleep mode control */ -#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020) -#define SLP_CTRL_EN BIT(0) -#define VREQ_COUNT_MASK (0x7F << 1) -#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK) -#define SPM_SLP_MODE BIT(8) +#define SCP_SLEEP_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0020) +#define SLP_CTRL_EN BIT(0) +#define VREQ_COUNT_MASK (0x7F << 1) +#define VREQ_COUNT_VAL(v) (((v) << 1) & VREQ_COUNT_MASK) +#define SPM_SLP_MODE BIT(8) /* clock divider select */ -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024) -#define CLK_DIV_SEL1 0 -#define CLK_DIV_SEL2 1 -#define CLK_DIV_SEL4 2 -#define CLK_DIV_SEL3 3 +#define SCP_CLK_DIV_SEL REG32(SCP_CLK_CTRL_BASE + 0x0024) +#define CLK_DIV_SEL1 0 +#define CLK_DIV_SEL2 1 +#define CLK_DIV_SEL4 2 +#define CLK_DIV_SEL3 3 /* clock gate */ -#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030) -#define CG_TIMER_MCLK BIT(0) -#define CG_TIMER_BCLK BIT(1) -#define CG_MAD_MCLK BIT(2) -#define CG_I2C_MCLK BIT(3) -#define CG_I2C_BCLK BIT(4) -#define CG_GPIO_MCLK BIT(5) -#define CG_AP2P_MCLK BIT(6) -#define CG_UART0_MCLK BIT(7) -#define CG_UART0_BCLK BIT(8) -#define CG_UART0_RST BIT(9) -#define CG_UART1_MCLK BIT(10) -#define CG_UART1_BCLK BIT(11) -#define CG_UART1_RST BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_I3C0 BIT(21) -#define CG_I3C1 BIT(22) -#define CG_DMA2_CH0 BIT(23) -#define CG_DMA2_CH1 BIT(24) -#define CG_DMA2_CH2 BIT(25) -#define CG_DMA2_CH3 BIT(26) +#define SCP_SET_CLK_CG REG32(SCP_CLK_CTRL_BASE + 0x0030) +#define CG_TIMER_MCLK BIT(0) +#define CG_TIMER_BCLK BIT(1) +#define CG_MAD_MCLK BIT(2) +#define CG_I2C_MCLK BIT(3) +#define CG_I2C_BCLK BIT(4) +#define CG_GPIO_MCLK BIT(5) +#define CG_AP2P_MCLK BIT(6) +#define CG_UART0_MCLK BIT(7) +#define CG_UART0_BCLK BIT(8) +#define CG_UART0_RST BIT(9) +#define CG_UART1_MCLK BIT(10) +#define CG_UART1_BCLK BIT(11) +#define CG_UART1_RST BIT(12) +#define CG_SPI0 BIT(13) +#define CG_SPI1 BIT(14) +#define CG_SPI2 BIT(15) +#define CG_DMA_CH0 BIT(16) +#define CG_DMA_CH1 BIT(17) +#define CG_DMA_CH2 BIT(18) +#define CG_DMA_CH3 BIT(19) +#define CG_I3C0 BIT(21) +#define CG_I3C1 BIT(22) +#define CG_DMA2_CH0 BIT(23) +#define CG_DMA2_CH1 BIT(24) +#define CG_DMA2_CH2 BIT(25) +#define CG_DMA2_CH3 BIT(26) /* UART clock select */ -#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044) -#define UART0_CK_SEL_SHIFT 0 -#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT) -#define UART0_CK_SEL_VAL(v) ((v) & UART0_CK_SEL_MASK) -#define UART0_CK_SW_STATUS_MASK (0xf << 8) -#define UART0_CK_SW_STATUS_VAL(v) ((v) & UART0_CK_SW_STATUS_MASK) -#define UART1_CK_SEL_SHIFT 16 -#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT) -#define UART1_CK_SEL_VAL(v) ((v) & UART1_CK_SEL_MASK) -#define UART1_CK_SW_STATUS_MASK (0xf << 24) -#define UART1_CK_SW_STATUS_VAL(v) ((v) & UART1_CK_SW_STATUS_MASK) -#define UART_CK_SEL_26M 0 -#define UART_CK_SEL_32K 1 -#define UART_CK_SEL_ULPOSC 2 -#define UART_CK_SW_STATUS_26M BIT(0) -#define UART_CK_SW_STATUS_32K BIT(1) -#define UART_CK_SW_STATUS_ULPOS BIT(2) +#define SCP_UART_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0044) +#define UART0_CK_SEL_SHIFT 0 +#define UART0_CK_SEL_MASK (0x3 << UART0_CK_SEL_SHIFT) +#define UART0_CK_SEL_VAL(v) ((v)&UART0_CK_SEL_MASK) +#define UART0_CK_SW_STATUS_MASK (0xf << 8) +#define UART0_CK_SW_STATUS_VAL(v) ((v)&UART0_CK_SW_STATUS_MASK) +#define UART1_CK_SEL_SHIFT 16 +#define UART1_CK_SEL_MASK (0x3 << UART1_CK_SEL_SHIFT) +#define UART1_CK_SEL_VAL(v) ((v)&UART1_CK_SEL_MASK) +#define UART1_CK_SW_STATUS_MASK (0xf << 24) +#define UART1_CK_SW_STATUS_VAL(v) ((v)&UART1_CK_SW_STATUS_MASK) +#define UART_CK_SEL_26M 0 +#define UART_CK_SEL_32K 1 +#define UART_CK_SEL_ULPOSC 2 +#define UART_CK_SW_STATUS_26M BIT(0) +#define UART_CK_SW_STATUS_32K BIT(1) +#define UART_CK_SW_STATUS_ULPOS BIT(2) /* BCLK clock select */ -#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) -#define BCLK_CK_SEL_SYS_DIV8 0 -#define BCLK_CK_SEL_32K 1 -#define BCLK_CK_SEL_ULPOSC_DIV8 2 +#define SCP_BCLK_CK_SEL REG32(SCP_CLK_CTRL_BASE + 0x0048) +#define BCLK_CK_SEL_SYS_DIV8 0 +#define BCLK_CK_SEL_32K 1 +#define BCLK_CK_SEL_ULPOSC_DIV8 2 /* VREQ control */ -#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) -#define VREQ_SEL BIT(0) -#define VREQ_VALUE BIT(4) -#define VREQ_EXT_SEL BIT(8) -#define VREQ_DVFS_SEL BIT(16) -#define VREQ_DVFS_VALUE BIT(20) -#define VREQ_DVFS_EXT_SEL BIT(24) -#define VREQ_SRCLKEN_SEL BIT(27) -#define VREQ_SRCLKEN_VALUE BIT(28) +#define SCP_CPU_VREQ_CTRL REG32(SCP_CLK_CTRL_BASE + 0x0054) +#define VREQ_SEL BIT(0) +#define VREQ_VALUE BIT(4) +#define VREQ_EXT_SEL BIT(8) +#define VREQ_DVFS_SEL BIT(16) +#define VREQ_DVFS_VALUE BIT(20) +#define VREQ_DVFS_EXT_SEL BIT(24) +#define VREQ_SRCLKEN_SEL BIT(27) +#define VREQ_SRCLKEN_VALUE BIT(28) /* clock on control */ -#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C) -#define HIGH_CORE_CG BIT(1) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C) -#define HIGH_AO BIT(0) -#define HIGH_DIS_SUB BIT(1) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) +#define SCP_CLK_HIGH_CORE_CG REG32(SCP_CLK_CTRL_BASE + 0x005C) +#define HIGH_CORE_CG BIT(1) +#define SCP_CLK_ON_CTRL REG32(SCP_CLK_CTRL_BASE + 0x006C) +#define HIGH_AO BIT(0) +#define HIGH_DIS_SUB BIT(1) +#define HIGH_CG_AO BIT(2) +#define HIGH_CORE_AO BIT(4) +#define HIGH_CORE_DIS_SUB BIT(5) +#define HIGH_CORE_CG_AO BIT(6) /* system control */ -#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) -#define AUTO_DDREN BIT(9) +#define SCP_SYS_CTRL REG32(SCP_REG_BASE + 0x24000) +#define AUTO_DDREN BIT(9) /* IPC */ -#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080) -#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090) -#define IPC_SCP2HOST BIT(0) -#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098) -#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C) -#define GIPC_IN(n) BIT(n) +#define SCP_SCP2APMCU_IPC_SET REG32(SCP_REG_BASE + 0x24080) +#define SCP_SCP2SPM_IPC_SET REG32(SCP_REG_BASE + 0x24090) +#define IPC_SCP2HOST BIT(0) +#define SCP_GIPC_IN_SET REG32(SCP_REG_BASE + 0x24098) +#define SCP_GIPC_IN_CLR REG32(SCP_REG_BASE + 0x2409C) +#define GIPC_IN(n) BIT(n) /* UART */ -#define SCP_UART_COUNT 2 -#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) -#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000) -#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000) -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] +#define SCP_UART_COUNT 2 +#define UART_TX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _TX) +#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) +#define SCP_UART0_BASE (SCP_REG_BASE + 0x26000) +#define SCP_UART1_BASE (SCP_REG_BASE + 0x27000) +#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) +#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] /* WDT */ -#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030) -#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034) -#define WDT_FREQ 33825 /* 0xFFFFF / 31 */ -#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000) -#define WDT_EN BIT(31) -#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) -#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) -#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0) -#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4) -#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8) +#define SCP_CORE0_WDT_IRQ REG32(SCP_REG_BASE + 0x30030) +#define SCP_CORE0_WDT_CFG REG32(SCP_REG_BASE + 0x30034) +#define WDT_FREQ 33825 /* 0xFFFFF / 31 */ +#define WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ +#define WDT_PERIOD(ms) (WDT_FREQ * (ms) / 1000) +#define WDT_EN BIT(31) +#define SCP_CORE0_WDT_KICK REG32(SCP_REG_BASE + 0x30038) +#define SCP_CORE0_WDT_CUR_VAL REG32(SCP_REG_BASE + 0x3003C) +#define SCP_CORE0_MON_PC_LATCH REG32(SCP_REG_BASE + 0x300D0) +#define SCP_CORE0_MON_LR_LATCH REG32(SCP_REG_BASE + 0x300D4) +#define SCP_CORE0_MON_SP_LATCH REG32(SCP_REG_BASE + 0x300D8) /* INTC */ -#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ -#define SCP_INTC_BIT(irq) ((irq) & 0x1F) /* bit shift =LSB[0:4] */ -#define SCP_INTC_GRP_COUNT 15 -#define SCP_INTC_GRP_GAP 4 +#define SCP_INTC_WORD(irq) ((irq) >> 5) /* word length = 2^5 */ +#define SCP_INTC_BIT(irq) ((irq)&0x1F) /* bit shift =LSB[0:4] */ +#define SCP_INTC_GRP_COUNT 15 +#define SCP_INTC_GRP_GAP 4 -#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000) +#define SCP_CORE0_INTC_IRQ_BASE (SCP_REG_BASE + 0x32000) #define SCP_CORE0_INTC_IRQ_STA(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)] #define SCP_CORE0_INTC_IRQ_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0020)[(w)] #define SCP_CORE0_INTC_IRQ_POL(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)] -#define SCP_CORE0_INTC_IRQ_GRP(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] -#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \ - ((g) << SCP_INTC_GRP_GAP))[(w)] + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0040)[(w)] +#define SCP_CORE0_INTC_IRQ_GRP(g, w) \ + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0050 + \ + ((g) << SCP_INTC_GRP_GAP)) \ + [(w)] +#define SCP_CORE0_INTC_IRQ_GRP_STA(g, w) \ + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0150 + \ + ((g) << SCP_INTC_GRP_GAP)) \ + [(w)] #define SCP_CORE0_INTC_SLP_WAKE_EN(w) \ - REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)] -#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250) + REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0240)[(w)] +#define SCP_CORE0_INTC_IRQ_OUT REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0250) /* UART */ -#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258) -#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C) -#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ) +#define SCP_CORE0_INTC_UART0_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x0258) +#define SCP_CORE0_INTC_UART1_RX_IRQ REG32(SCP_CORE0_INTC_IRQ_BASE + 0x025C) +#define SCP_CORE0_INTC_UART_RX_IRQ(n) CONCAT3(SCP_CORE0_INTC_UART, n, _RX_IRQ) /* XGPT (general purpose timer) */ -#define NUM_TIMERS 6 -#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n))) -#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000) -#define TIMER_EN BIT(0) -#define TIMER_CLK_SRC_32K (0 << 4) -#define TIMER_CLK_SRC_26M (1 << 4) -#define TIMER_CLK_SRC_BCLK (2 << 4) -#define TIMER_CLK_SRC_MCLK (3 << 4) -#define TIMER_CLK_SRC_MASK (3 << 4) -#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004) -#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008) -#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C) -#define TIMER_IRQ_EN BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLR BIT(5) -#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) +#define NUM_TIMERS 6 +#define SCP_CORE0_TIMER_BASE(n) (SCP_REG_BASE + 0x33000 + (0x10 * (n))) +#define SCP_CORE0_TIMER_EN(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0000) +#define TIMER_EN BIT(0) +#define TIMER_CLK_SRC_32K (0 << 4) +#define TIMER_CLK_SRC_26M (1 << 4) +#define TIMER_CLK_SRC_BCLK (2 << 4) +#define TIMER_CLK_SRC_MCLK (3 << 4) +#define TIMER_CLK_SRC_MASK (3 << 4) +#define SCP_CORE0_TIMER_RST_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0004) +#define SCP_CORE0_TIMER_CUR_VAL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x0008) +#define SCP_CORE0_TIMER_IRQ_CTRL(n) REG32(SCP_CORE0_TIMER_BASE(n) + 0x000C) +#define TIMER_IRQ_EN BIT(0) +#define TIMER_IRQ_STATUS BIT(4) +#define TIMER_IRQ_CLR BIT(5) +#define SCP_IRQ_TIMER(n) CONCAT2(SCP_IRQ_TIMER, n) /* secure control */ -#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000) -#define VREQ_SECURE_DIS BIT(4) +#define SCP_SEC_CTRL REG32(SCP_REG_BASE + 0xA5000) +#define VREQ_SECURE_DIS BIT(4) /* memory remap */ -#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060) -#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064) -#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068) -#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C) +#define SCP_R_REMAP_0X0123 REG32(SCP_REG_BASE + 0xA5060) +#define SCP_R_REMAP_0X4567 REG32(SCP_REG_BASE + 0xA5064) +#define SCP_R_REMAP_0X89AB REG32(SCP_REG_BASE + 0xA5068) +#define SCP_R_REMAP_0XCDEF REG32(SCP_REG_BASE + 0xA506C) /* external address: AP */ -#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ +#define AP_REG_BASE 0x60000000 /* 0x10000000 remap to 0x6 */ /* AP GPIO */ -#define AP_GPIO_BASE (AP_REG_BASE + 0x5000) -#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) -#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) -#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) -#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) -#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) -#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) +#define AP_GPIO_BASE (AP_REG_BASE + 0x5000) +#define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) +#define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) +#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) +#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) +#define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) +#define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) #include "clock_regs.h" -- cgit v1.2.1 From a0791b65adebf27b99f27143105bc59ef519da72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:31 -0600 Subject: chip/mchp/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia20b7a6ef05ce8324b6bdd4fb7f2377cf4e31b97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729313 Reviewed-by: Jeremy Bettis --- chip/mchp/uart.c | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c index c274519b94..4f40886e24 100644 --- a/chip/mchp/uart.c +++ b/chip/mchp/uart.c @@ -17,40 +17,40 @@ #include "util.h" #include "tfdp_chip.h" -#define TX_FIFO_SIZE 16 +#define TX_FIFO_SIZE 16 BUILD_ASSERT((CONFIG_UART_CONSOLE >= 0) && (CONFIG_UART_CONSOLE < MCHP_UART_INSTANCES)); #if CONFIG_UART_CONSOLE == 2 -#define UART_IRQ MCHP_IRQ_UART2 -#define UART_IRQ_BIT MCHP_UART2_GIRQ_BIT -#define UART_PCR MCHP_PCR_UART2 -#define GPIO_UART_RX GPIO_UART2_RX +#define UART_IRQ MCHP_IRQ_UART2 +#define UART_IRQ_BIT MCHP_UART2_GIRQ_BIT +#define UART_PCR MCHP_PCR_UART2 +#define GPIO_UART_RX GPIO_UART2_RX /* MEC152x only. UART2 RX Pin = GPIO 0145 GIRQ08 bit[5] */ -#define UART_RX_PIN_GIRQ 8 -#define UART_RX_PIN_BIT BIT(5) +#define UART_RX_PIN_GIRQ 8 +#define UART_RX_PIN_BIT BIT(5) #elif CONFIG_UART_CONSOLE == 1 -#define UART_IRQ MCHP_IRQ_UART1 -#define UART_IRQ_BIT MCHP_UART1_GIRQ_BIT -#define UART_PCR MCHP_PCR_UART1 -#define GPIO_UART_RX GPIO_UART1_RX +#define UART_IRQ MCHP_IRQ_UART1 +#define UART_IRQ_BIT MCHP_UART1_GIRQ_BIT +#define UART_PCR MCHP_PCR_UART1 +#define GPIO_UART_RX GPIO_UART1_RX /* MEC152x and MEC170x UART1 RX Pin = GPIO 0171. GIRQ08 bit[25] */ -#define UART_RX_PIN_GIRQ 8 -#define UART_RX_PIN_BIT BIT(25) +#define UART_RX_PIN_GIRQ 8 +#define UART_RX_PIN_BIT BIT(25) #else -#define UART_IRQ MCHP_IRQ_UART0 -#define UART_IRQ_BIT MCHP_UART0_GIRQ_BIT -#define UART_PCR MCHP_PCR_UART0 -#define GPIO_UART_RX GPIO_UART0_RX +#define UART_IRQ MCHP_IRQ_UART0 +#define UART_IRQ_BIT MCHP_UART0_GIRQ_BIT +#define UART_PCR MCHP_PCR_UART0 +#define GPIO_UART_RX GPIO_UART0_RX /* MEC152x and MEC170x UART0 RX Pin = GPIO 0105. GIRQ09 bit[5] */ -#define UART_RX_PIN_GIRQ 9 -#define UART_RX_PIN_BIT BIT(5) +#define UART_RX_PIN_GIRQ 9 +#define UART_RX_PIN_BIT BIT(5) #endif /* CONFIG_UART_CONSOLE == 2 */ @@ -103,7 +103,7 @@ int uart_tx_ready(void) * this, we check transmit FIFO empty bit every 16 characters written. */ return tx_fifo_used != 0 || - (MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY); + (MCHP_UART_LSR(CONFIG_UART_CONSOLE) & MCHP_LSR_TX_EMPTY); } int uart_tx_in_progress(void) @@ -212,7 +212,7 @@ void uart_init(void) void uart_enter_dsleep(void) { /* Disable the UART interrupt. */ - task_disable_irq(UART_IRQ); /* NVIC interrupt for UART=13 */ + task_disable_irq(UART_IRQ); /* NVIC interrupt for UART=13 */ /* * Set the UART0 RX pin to be a GPIO-162(fixed pin) interrupt @@ -233,7 +233,6 @@ void uart_enter_dsleep(void) gpio_enable_interrupt(GPIO_UART_RX); } - void uart_exit_dsleep(void) { /* -- cgit v1.2.1 From bebbe4997c487063ddf3b2ce8b33126c1d643ef9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:38 -0600 Subject: board/storo/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5aa83b6223b05923075e8ceab573eec8a411fbd3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728959 Reviewed-by: Jeremy Bettis --- board/storo/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/storo/cbi_ssfc.h b/board/storo/cbi_ssfc.h index f4a51b8e91..7b29a1c585 100644 --- a/board/storo/cbi_ssfc.h +++ b/board/storo/cbi_ssfc.h @@ -57,5 +57,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From c4b2cd755b22912cabfa072af89af1e409bb3ec0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:57 -0600 Subject: board/nucleo-f411re/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5f526f98a0d9ad3dd161cae4470f916ff0d101de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728778 Reviewed-by: Jeremy Bettis --- board/nucleo-f411re/board.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/nucleo-f411re/board.h b/board/nucleo-f411re/board.h index 56d2ad41d0..ebadcac182 100644 --- a/board/nucleo-f411re/board.h +++ b/board/nucleo-f411re/board.h @@ -12,7 +12,6 @@ #define CPU_CLOCK 84000000 #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 - /* the UART console is on USART2 (PA2/PA3) */ #undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 2 @@ -43,7 +42,7 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_DEBUG #define I2C_PORT_MASTER 1 -#define I2C_PORT_SLAVE 0 /* needed for DMAC macros (ugh) */ +#define I2C_PORT_SLAVE 0 /* needed for DMAC macros (ugh) */ #define I2C_PORT_ACCEL I2C_PORT_MASTER #ifndef __ASSEMBLER__ -- cgit v1.2.1 From d4213c0b6676ff80c4e3a8b396f716421cabc007 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:00 -0600 Subject: chip/host/usb_pd_phy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia45063178baa5f75d18de9392fa95194b6e20237 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729154 Reviewed-by: Jeremy Bettis --- chip/host/usb_pd_phy.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c index ba81b986ad..eb77c1eecd 100644 --- a/chip/host/usb_pd_phy.c +++ b/chip/host/usb_pd_phy.c @@ -37,9 +37,9 @@ static struct pd_physical { int verified_idx; } pd_phy[CONFIG_USB_PD_PORT_MAX_COUNT]; -static const uint16_t enc4b5b[] = { - 0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, 0x0E, 0x0F, 0x12, 0x13, 0x16, - 0x17, 0x1A, 0x1B, 0x1C, 0x1D}; +static const uint16_t enc4b5b[] = { 0x1E, 0x09, 0x14, 0x15, 0x0A, 0x0B, + 0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17, + 0x1A, 0x1B, 0x1C, 0x1D }; /* Test utilities */ static void pd_test_reset_phy(int port) @@ -216,7 +216,6 @@ int pd_test_tx_msg_verify_crc(int port) return pd_test_tx_msg_verify_word(port, crc32_result()); } - /* Mock functions */ void pd_init_dequeue(int port) -- cgit v1.2.1 From c5f62064116ea847c0964e196aee545dcdbcb35f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:00 -0600 Subject: board/coral/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I134c33a2526ce1a9927437c65b0750c99ea2e45d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728178 Reviewed-by: Jeremy Bettis --- board/coral/usb_pd_policy.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/board/coral/usb_pd_policy.c b/board/coral/usb_pd_policy.c index e071f6ae2a..b3a1edc1b6 100644 --- a/board/coral/usb_pd_policy.c +++ b/board/coral/usb_pd_policy.c @@ -23,12 +23,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -39,7 +39,8 @@ static void board_vbus_update_source_current(int port) { enum gpio_signal gpio = port ? GPIO_USB_C1_5V_EN : GPIO_USB_C0_5V_EN; int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); /* * Driving USB_Cx_5V_EN high, actually put a 16.5k resistance -- cgit v1.2.1 From af78dc683ff8a4a23d07be13c04a733e12d98ca0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:21 -0600 Subject: board/corori2/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a8090bff7311b85a0af6599d8ec5fe5b93b7d3c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728183 Reviewed-by: Jeremy Bettis --- board/corori2/board.c | 84 +++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 47 deletions(-) diff --git a/board/corori2/board.c b/board/corori2/board.c index 0ccd3c3ebc..29885dc0a8 100644 --- a/board/corori2/board.c +++ b/board/corori2/board.c @@ -44,8 +44,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -85,7 +85,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } /* C1 interrupt line shared by BC 1.2, TCPC, and charger */ @@ -120,7 +119,6 @@ static void sub_usb_c1_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c1_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -167,22 +165,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [ADC_TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [ADC_TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [ADC_TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [ADC_TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_MEMORY \ - { \ +#define THERMAL_MEMORY \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ @@ -200,8 +198,8 @@ __maybe_unused static const struct ec_thermal_config thermal_memory = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ @@ -234,16 +232,17 @@ void board_init(void) if (get_cbi_fw_config_db() == DB_1A_HDMI) { /* Disable i2c on HDMI pins */ - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, 0); - gpio_config_pin(MODULE_I2C, - GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, + 0); + gpio_config_pin(MODULE_I2C, GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, + 0); /* Set HDMI and sub-rail enables to output */ gpio_set_flags(GPIO_EC_I2C_SUB_C1_SCL_HDMI_EN_ODL, chipset_in_state(CHIPSET_STATE_ON) ? - GPIO_ODR_LOW : GPIO_ODR_HIGH); - gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); + GPIO_ODR_LOW : + GPIO_ODR_HIGH); + gpio_set_flags(GPIO_SUB_C1_INT_EN_RAILS_ODL, GPIO_ODR_HIGH); /* Select HDMI option */ gpio_set_level(GPIO_HDMI_SEL_L, 0); @@ -252,8 +251,7 @@ void board_init(void) gpio_enable_interrupt(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL); } else { /* Set SDA as an input */ - gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, - GPIO_INPUT); + gpio_set_flags(GPIO_EC_I2C_SUB_C1_SDA_HDMI_HPD_ODL, GPIO_INPUT); /* Enable C1 interrupt and check if it needs processing */ gpio_enable_interrupt(GPIO_SUB_C1_INT_EN_RAILS_ODL); @@ -320,7 +318,7 @@ static void reconfigure_5v_gpio(void) gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW); } } -DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1); #endif /* BOARD_WADDLEDOO */ static void set_5v_gpio(int level) @@ -361,10 +359,9 @@ __override void board_power_5v_enable(int enable) gpio_set_level(GPIO_SUB_C1_INT_EN_RAILS_ODL, !enable); } else { if (isl923x_set_comparator_inversion(1, !!enable)) - CPRINTS("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTS("Failed to %sable sub rails!", + enable ? "en" : "dis"); } - } __override uint8_t board_get_usb_pd_port_count(void) @@ -389,13 +386,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -459,8 +454,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -485,17 +480,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; @@ -571,9 +562,8 @@ struct motion_sensor_t motion_sensors[] = { const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -704,7 +694,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { + !gpio_get_level(GPIO_SUB_C1_INT_EN_RAILS_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) -- cgit v1.2.1 From 03435f98f4d0635fb3357f10b6e87111a912a6b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:50 -0600 Subject: util/lbplay.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I47e423b89cdcb5f25ba89fcc0d610ddf3abae916 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730649 Reviewed-by: Jeremy Bettis --- util/lbplay.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/util/lbplay.c b/util/lbplay.c index 9ab0564b74..8739c8b040 100644 --- a/util/lbplay.c +++ b/util/lbplay.c @@ -126,11 +126,8 @@ int main(int argc, char **argv) * to see what the limit is. The default is 50msec (20Hz). */ for (i = 0; i < 256; i += 4) { - sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d", - i, 0, 0, - 0, 0, i, - 255-i, 255, 0, - 0, 255, 255-i); + sprintf(buf, "0 %d %d %d 1 %d %d %d 2 %d %d %d 3 %d %d %d", i, + 0, 0, 0, 0, i, 255 - i, 255, 0, 0, 255, 255 - i); lseek(fd_l, 0, SEEK_SET); if (write(fd_l, buf, strlen(buf) + 1) < 0) perror("write to led control"); -- cgit v1.2.1 From a31e693a72b1a06efb299697b42ac853620f4544 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:16 -0600 Subject: include/virtual_battery.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If609f6a1e4a92a5f4ad3db31312f513e33188c1e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730457 Reviewed-by: Jeremy Bettis --- include/virtual_battery.h | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/include/virtual_battery.h b/include/virtual_battery.h index a5cac1140c..689f54365b 100644 --- a/include/virtual_battery.h +++ b/include/virtual_battery.h @@ -6,8 +6,8 @@ #ifndef __CROS_EC_VIRTUAL_BATTERY_H #define __CROS_EC_VIRTUAL_BATTERY_H -#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) \ - && !defined(VIRTUAL_BATTERY_ADDR_FLAGS) +#if defined(CONFIG_I2C_VIRTUAL_BATTERY) && defined(CONFIG_BATTERY_SMART) && \ + !defined(VIRTUAL_BATTERY_ADDR_FLAGS) #define VIRTUAL_BATTERY_ADDR_FLAGS BATTERY_ADDR_FLAGS #endif @@ -21,10 +21,8 @@ * @return EC_SUCCESS if successful, non-zero if error. * */ -int virtual_battery_operation(const uint8_t *batt_cmd_head, - uint8_t *dest, - int read_len, - int write_len); +int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest, + int read_len, int write_len); /** * Parse a command for virtual battery function. @@ -39,10 +37,9 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head, * @param out Data to send * @return EC_SUCCESS if successful, non-zero if error. */ -int virtual_battery_handler(struct ec_response_i2c_passthru *resp, - int in_len, int *err_code, int xferflags, - int read_len, int write_len, - const uint8_t *out); +int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len, + int *err_code, int xferflags, int read_len, + int write_len, const uint8_t *out); /* Reset the state machine and static variables. */ void reset_parse_state(void); -- cgit v1.2.1 From 3b489044b804021f19816762f4a43e2f9ae5f558 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:13 -0600 Subject: chip/npcx/adc_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I750313d2ffbe458702a7f359b66f59794d760ef7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729364 Reviewed-by: Jeremy Bettis --- chip/npcx/adc_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/npcx/adc_chip.h b/chip/npcx/adc_chip.h index 300447df16..61423394b7 100644 --- a/chip/npcx/adc_chip.h +++ b/chip/npcx/adc_chip.h @@ -32,7 +32,7 @@ enum npcx_adc_input_channel { #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 NPCX_ADC_CH10, NPCX_ADC_CH11, - #endif +#endif NPCX_ADC_CH_COUNT }; -- cgit v1.2.1 From 30426fbed062beb219614358e302fb17ca42b0e5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:23 -0600 Subject: include/usb_pd.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40817da308d2106a53b9df74f8304f534683d6fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730438 Reviewed-by: Jeremy Bettis --- include/usb_pd.h | 952 +++++++++++++++++++++++++++---------------------------- 1 file changed, 464 insertions(+), 488 deletions(-) diff --git a/include/usb_pd.h b/include/usb_pd.h index 2ce7bca177..aaf365d389 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -26,58 +26,56 @@ */ #if defined(HAS_TASK_PD_C0) && defined(CONFIG_USB_PD_PORT_MAX_COUNT) #define PD_PORT_TO_TASK_ID(port) (TASK_ID_PD_C0 + (port)) -#define TASK_ID_TO_PD_PORT(id) ((id) - TASK_ID_PD_C0) +#define TASK_ID_TO_PD_PORT(id) ((id)-TASK_ID_PD_C0) #else #define PD_PORT_TO_TASK_ID(port) -1 /* stub task ID */ #define TASK_ID_TO_PD_PORT(id) 0 #endif /* CONFIG_USB_PD_PORT_MAX_COUNT && HAS_TASK_PD_C0 */ enum pd_rx_errors { - PD_RX_ERR_INVAL = -1, /* Invalid packet */ - PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */ - PD_RX_ERR_CRC = -3, /* CRC mismatch */ - PD_RX_ERR_ID = -4, /* Invalid ID number */ + PD_RX_ERR_INVAL = -1, /* Invalid packet */ + PD_RX_ERR_HARD_RESET = -2, /* Got a Hard-Reset packet */ + PD_RX_ERR_CRC = -3, /* CRC mismatch */ + PD_RX_ERR_ID = -4, /* Invalid ID number */ PD_RX_ERR_UNSUPPORTED_SOP = -5, /* Unsupported SOP */ - PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */ + PD_RX_ERR_CABLE_RESET = -6 /* Got a Cable-Reset packet */ }; /* Events for USB PD task */ /* Outgoing packet event */ -#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3) +#define PD_EVENT_TX TASK_EVENT_CUSTOM_BIT(3) /* CC line change event */ -#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4) +#define PD_EVENT_CC TASK_EVENT_CUSTOM_BIT(4) /* TCPC has reset */ -#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5) +#define PD_EVENT_TCPC_RESET TASK_EVENT_CUSTOM_BIT(5) /* DRP state has changed */ -#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6) +#define PD_EVENT_UPDATE_DUAL_ROLE TASK_EVENT_CUSTOM_BIT(6) /* * A task, other than the task owning the PD port, accessed the TCPC. The task * that owns the port does not send itself this event. */ -#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7) +#define PD_EVENT_DEVICE_ACCESSED TASK_EVENT_CUSTOM_BIT(7) /* Chipset power state changed */ -#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8) +#define PD_EVENT_POWER_STATE_CHANGE TASK_EVENT_CUSTOM_BIT(8) /* Issue a Hard Reset. */ -#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9) +#define PD_EVENT_SEND_HARD_RESET TASK_EVENT_CUSTOM_BIT(9) /* Prepare for sysjump */ -#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10) +#define PD_EVENT_SYSJUMP TASK_EVENT_CUSTOM_BIT(10) /* Receive a Hard Reset. */ -#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11) +#define PD_EVENT_RX_HARD_RESET TASK_EVENT_CUSTOM_BIT(11) /* MUX configured notification event */ -#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12) +#define PD_EVENT_AP_MUX_DONE TASK_EVENT_CUSTOM_BIT(12) /* First free event on PD task */ -#define PD_EVENT_FIRST_FREE_BIT 13 +#define PD_EVENT_FIRST_FREE_BIT 13 /* Ensure TCPC is out of low power mode before handling these events. */ -#define PD_EXIT_LOW_POWER_EVENT_MASK \ - (PD_EVENT_CC | \ - PD_EVENT_UPDATE_DUAL_ROLE | \ - PD_EVENT_POWER_STATE_CHANGE | \ - PD_EVENT_TCPC_RESET) +#define PD_EXIT_LOW_POWER_EVENT_MASK \ + (PD_EVENT_CC | PD_EVENT_UPDATE_DUAL_ROLE | \ + PD_EVENT_POWER_STATE_CHANGE | PD_EVENT_TCPC_RESET) /* --- PD data message helpers --- */ -#define PDO_MAX_OBJECTS 7 +#define PDO_MAX_OBJECTS 7 #define PDO_MODES (PDO_MAX_OBJECTS - 1) /* PDO : Power Data Object */ @@ -94,65 +92,58 @@ enum pd_rx_errors { * * Note: Some bits and decode macros are defined in ec_commands.h */ -#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported */ /* Higher capability in vSafe5V sink PDO */ -#define PDO_FIXED_SNK_HIGHER_CAP BIT(28) -#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23) +#define PDO_FIXED_SNK_HIGHER_CAP BIT(28) +#define PDO_FIXED_FRS_CURR_NOT_SUPPORTED (0 << 23) #define PDO_FIXED_FRS_CURR_DFLT_USB_POWER (1 << 23) -#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23) -#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23) +#define PDO_FIXED_FRS_CURR_1A5_AT_5V (2 << 23) +#define PDO_FIXED_FRS_CURR_3A0_AT_5V (3 << 23) #define PDO_FIXED_PEAK_CURR () /* [21..20] Peak current */ -#define PDO_FIXED_VOLT(mv) (((mv)/50) << 10) /* Voltage in 50mV units */ -#define PDO_FIXED_CURR(ma) (((ma)/10) << 0) /* Max current in 10mA units */ +#define PDO_FIXED_VOLT(mv) (((mv) / 50) << 10) /* Voltage in 50mV units */ +#define PDO_FIXED_CURR(ma) (((ma) / 10) << 0) /* Max current in 10mA units */ #define PDO_FIXED_GET_VOLT(pdo) (((pdo >> 10) & 0x3FF) * 50) #define PDO_FIXED_GET_CURR(pdo) ((pdo & 0x3FF) * 10) -#define PDO_FIXED(mv, ma, flags) (PDO_FIXED_VOLT(mv) |\ - PDO_FIXED_CURR(ma) | (flags)) +#define PDO_FIXED(mv, ma, flags) \ + (PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma) | (flags)) #define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20) #define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10) -#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) +#define PDO_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) -#define PDO_VAR(min_mv, max_mv, op_ma) \ - (PDO_VAR_MIN_VOLT(min_mv) | \ - PDO_VAR_MAX_VOLT(max_mv) | \ - PDO_VAR_OP_CURR(op_ma) | \ - PDO_TYPE_VARIABLE) +#define PDO_VAR(min_mv, max_mv, op_ma) \ + (PDO_VAR_MIN_VOLT(min_mv) | PDO_VAR_MAX_VOLT(max_mv) | \ + PDO_VAR_OP_CURR(op_ma) | PDO_TYPE_VARIABLE) #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & 0x3FF) << 20) #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & 0x3FF) << 10) #define PDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) -#define PDO_BATT(min_mv, max_mv, op_mw) \ - (PDO_BATT_MIN_VOLT(min_mv) | \ - PDO_BATT_MAX_VOLT(max_mv) | \ - PDO_BATT_OP_POWER(op_mw) | \ - PDO_TYPE_BATTERY) +#define PDO_BATT(min_mv, max_mv, op_mw) \ + (PDO_BATT_MIN_VOLT(min_mv) | PDO_BATT_MAX_VOLT(max_mv) | \ + PDO_BATT_OP_POWER(op_mw) | PDO_TYPE_BATTERY) /* RDO : Request Data Object */ -#define RDO_OBJ_POS(n) (((n) & 0x7) << 28) -#define RDO_POS(rdo) (((rdo) >> 28) & 0x7) -#define RDO_GIVE_BACK BIT(27) -#define RDO_CAP_MISMATCH BIT(26) -#define RDO_COMM_CAP BIT(25) -#define RDO_NO_SUSPEND BIT(24) -#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10) +#define RDO_OBJ_POS(n) (((n)&0x7) << 28) +#define RDO_POS(rdo) (((rdo) >> 28) & 0x7) +#define RDO_GIVE_BACK BIT(27) +#define RDO_CAP_MISMATCH BIT(26) +#define RDO_COMM_CAP BIT(25) +#define RDO_NO_SUSPEND BIT(24) +#define RDO_FIXED_VAR_OP_CURR(ma) ((((ma) / 10) & 0x3FF) << 10) #define RDO_FIXED_VAR_MAX_CURR(ma) ((((ma) / 10) & 0x3FF) << 0) -#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10) -#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) +#define RDO_BATT_OP_POWER(mw) ((((mw) / 250) & 0x3FF) << 10) +#define RDO_BATT_MAX_POWER(mw) ((((mw) / 250) & 0x3FF) << 0) -#define RDO_FIXED(n, op_ma, max_ma, flags) \ - (RDO_OBJ_POS(n) | (flags) | \ - RDO_FIXED_VAR_OP_CURR(op_ma) | \ - RDO_FIXED_VAR_MAX_CURR(max_ma)) +#define RDO_FIXED(n, op_ma, max_ma, flags) \ + (RDO_OBJ_POS(n) | (flags) | RDO_FIXED_VAR_OP_CURR(op_ma) | \ + RDO_FIXED_VAR_MAX_CURR(max_ma)) - -#define RDO_BATT(n, op_mw, max_mw, flags) \ - (RDO_OBJ_POS(n) | (flags) | \ - RDO_BATT_OP_POWER(op_mw) | \ - RDO_BATT_MAX_POWER(max_mw)) +#define RDO_BATT(n, op_mw, max_mw, flags) \ + (RDO_OBJ_POS(n) | (flags) | RDO_BATT_OP_POWER(op_mw) | \ + RDO_BATT_MAX_POWER(max_mw)) /* BDO : BIST Data Object * 31:28 BIST Mode @@ -161,41 +152,41 @@ enum pd_rx_errors { * 27:16 Reserved * 15:0 Returned error counters (reserved in PD 3.0) */ -#define BDO_MODE_RECV (0 << 28) -#define BDO_MODE_TRANSMIT BIT(28) -#define BDO_MODE_COUNTERS (2 << 28) -#define BDO_MODE_CARRIER0 (3 << 28) -#define BDO_MODE_CARRIER1 (4 << 28) -#define BDO_MODE_CARRIER2 (5 << 28) -#define BDO_MODE_CARRIER3 (6 << 28) -#define BDO_MODE_EYE (7 << 28) -#define BDO_MODE_TEST_DATA (8 << 28) - -#define BDO(mode, cnt) ((mode) | ((cnt) & 0xFFFF)) - -#define BIST_MODE(n) ((n) >> 28) -#define BIST_ERROR_COUNTER(n) ((n) & 0xffff) -#define BIST_RECEIVER_MODE 0 -#define BIST_TRANSMIT_MODE 1 +#define BDO_MODE_RECV (0 << 28) +#define BDO_MODE_TRANSMIT BIT(28) +#define BDO_MODE_COUNTERS (2 << 28) +#define BDO_MODE_CARRIER0 (3 << 28) +#define BDO_MODE_CARRIER1 (4 << 28) +#define BDO_MODE_CARRIER2 (5 << 28) +#define BDO_MODE_CARRIER3 (6 << 28) +#define BDO_MODE_EYE (7 << 28) +#define BDO_MODE_TEST_DATA (8 << 28) + +#define BDO(mode, cnt) ((mode) | ((cnt)&0xFFFF)) + +#define BIST_MODE(n) ((n) >> 28) +#define BIST_ERROR_COUNTER(n) ((n)&0xffff) +#define BIST_RECEIVER_MODE 0 +#define BIST_TRANSMIT_MODE 1 #define BIST_RETURNED_COUNTER 2 -#define BIST_CARRIER_MODE_0 3 -#define BIST_CARRIER_MODE_1 4 -#define BIST_CARRIER_MODE_2 5 -#define BIST_CARRIER_MODE_3 6 -#define BIST_EYE_PATTERN 7 -#define BIST_TEST_DATA 8 +#define BIST_CARRIER_MODE_0 3 +#define BIST_CARRIER_MODE_1 4 +#define BIST_CARRIER_MODE_2 5 +#define BIST_CARRIER_MODE_3 6 +#define BIST_EYE_PATTERN 7 +#define BIST_TEST_DATA 8 #define SVID_DISCOVERY_MAX 16 /* Timers */ -#define PD_T_SINK_TX (18*MSEC) /* between 16ms and 20 */ -#define PD_T_CHUNKING_NOT_SUPPORTED (45*MSEC) /* between 40ms and 50ms */ -#define PD_T_HARD_RESET_COMPLETE (5*MSEC) /* between 4ms and 5ms*/ -#define PD_T_HARD_RESET_RETRY (1*MSEC) /* 1ms */ -#define PD_T_SEND_SOURCE_CAP (100*MSEC) /* between 100ms and 200ms */ -#define PD_T_SINK_WAIT_CAP (575*MSEC) /* between 310ms and 620ms */ -#define PD_T_SINK_TRANSITION (35*MSEC) /* between 20ms and 35ms */ -#define PD_T_SOURCE_ACTIVITY (45*MSEC) /* between 40ms and 50ms */ +#define PD_T_SINK_TX (18 * MSEC) /* between 16ms and 20 */ +#define PD_T_CHUNKING_NOT_SUPPORTED (45 * MSEC) /* between 40ms and 50ms */ +#define PD_T_HARD_RESET_COMPLETE (5 * MSEC) /* between 4ms and 5ms*/ +#define PD_T_HARD_RESET_RETRY (1 * MSEC) /* 1ms */ +#define PD_T_SEND_SOURCE_CAP (100 * MSEC) /* between 100ms and 200ms */ +#define PD_T_SINK_WAIT_CAP (575 * MSEC) /* between 310ms and 620ms */ +#define PD_T_SINK_TRANSITION (35 * MSEC) /* between 20ms and 35ms */ +#define PD_T_SOURCE_ACTIVITY (45 * MSEC) /* between 40ms and 50ms */ /* * Adjusting for TCPMv2 PD2 Compliance. In tests like TD.PD.SRC.E5 this * value is the duration before the Hard Reset can be sent. Setting the @@ -207,92 +198,92 @@ enum pd_rx_errors { * usb_pd unit test. */ #ifndef CONFIG_USB_PD_TCPMV2 -#define PD_T_SENDER_RESPONSE (30*MSEC) /* between 24ms and 30ms */ +#define PD_T_SENDER_RESPONSE (30 * MSEC) /* between 24ms and 30ms */ #else -#define PD_T_SENDER_RESPONSE (24*MSEC) /* between 24ms and 30ms */ +#define PD_T_SENDER_RESPONSE (24 * MSEC) /* between 24ms and 30ms */ #endif -#define PD_T_PS_TRANSITION (500*MSEC) /* between 450ms and 550ms */ -#define PD_T_PS_SOURCE_ON (480*MSEC) /* between 390ms and 480ms */ -#define PD_T_PS_SOURCE_OFF (835*MSEC) /* between 750ms and 920ms */ -#define PD_T_PS_HARD_RESET (25*MSEC) /* between 25ms and 35ms */ -#define PD_T_ERROR_RECOVERY (240*MSEC) /* min 240ms if sourcing VConn */ -#define PD_T_CC_DEBOUNCE (100*MSEC) /* between 100ms and 200ms */ +#define PD_T_PS_TRANSITION (500 * MSEC) /* between 450ms and 550ms */ +#define PD_T_PS_SOURCE_ON (480 * MSEC) /* between 390ms and 480ms */ +#define PD_T_PS_SOURCE_OFF (835 * MSEC) /* between 750ms and 920ms */ +#define PD_T_PS_HARD_RESET (25 * MSEC) /* between 25ms and 35ms */ +#define PD_T_ERROR_RECOVERY (240 * MSEC) /* min 240ms if sourcing VConn */ +#define PD_T_CC_DEBOUNCE (100 * MSEC) /* between 100ms and 200ms */ /* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */ -#define PD_T_DRP_SNK (40*MSEC) /* toggle time for sink DRP */ -#define PD_T_DRP_SRC (30*MSEC) /* toggle time for source DRP */ -#define PD_T_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_TRY_CC_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_SINK_ADJ (55*MSEC) /* between tPDDebounce and 60ms */ -#define PD_T_SRC_RECOVER (760*MSEC) /* between 660ms and 1000ms */ -#define PD_T_SRC_RECOVER_MAX (1000*MSEC) /* 1000ms */ -#define PD_T_SRC_TURN_ON (275*MSEC) /* 275ms */ -#define PD_T_SAFE_0V (650*MSEC) /* 650ms */ -#define PD_T_NO_RESPONSE (5500*MSEC) /* between 4.5s and 5.5s */ -#define PD_T_BIST_TRANSMIT (50*MSEC) /* 50ms (for task_wait arg) */ -#define PD_T_BIST_RECEIVE (60*MSEC) /* 60ms (time to process bist) */ -#define PD_T_BIST_CONT_MODE (55*MSEC) /* 30ms to 60ms */ -#define PD_T_VCONN_SOURCE_ON (100*MSEC) /* 100ms */ -#define PD_T_DRP_TRY (125*MSEC) /* between 75ms and 150ms */ -#define PD_T_TRY_TIMEOUT (550*MSEC) /* between 550ms and 1100ms */ -#define PD_T_TRY_WAIT (600*MSEC) /* Wait time for TryWait.SNK */ -#define PD_T_SINK_REQUEST (100*MSEC) /* 100ms before next request */ -#define PD_T_PD_DEBOUNCE (15*MSEC) /* between 10ms and 20ms */ -#define PD_T_CHUNK_SENDER_RESPONSE (25*MSEC) /* 25ms */ -#define PD_T_CHUNK_SENDER_REQUEST (25*MSEC) /* 25ms */ -#define PD_T_SWAP_SOURCE_START (25*MSEC) /* Min of 20ms */ -#define PD_T_RP_VALUE_CHANGE (20*MSEC) /* 20ms */ -#define PD_T_SRC_DISCONNECT (15*MSEC) /* 15ms */ -#define PD_T_SRC_TRANSITION (25*MSEC) /* 25ms to 35 ms */ -#define PD_T_VCONN_STABLE (50*MSEC) /* 50ms */ -#define PD_T_DISCOVER_IDENTITY (45*MSEC) /* between 40ms and 50ms */ -#define PD_T_SYSJUMP (1000*MSEC) /* 1s */ -#define PD_T_PR_SWAP_WAIT (100*MSEC) /* tPRSwapWait 100ms */ -#define PD_T_DATA_RESET (225*MSEC) /* between 200ms and 250ms */ -#define PD_T_DATA_RESET_FAIL (300*MSEC) /* 300ms */ -#define PD_T_VCONN_REAPPLIED (10*MSEC) /* between 10ms and 20ms */ -#define PD_T_VCONN_DISCHARGE (240*MSEC) /* between 160ms and 240ms */ +#define PD_T_DRP_SNK (40 * MSEC) /* toggle time for sink DRP */ +#define PD_T_DRP_SRC (30 * MSEC) /* toggle time for source DRP */ +#define PD_T_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_TRY_CC_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_SINK_ADJ (55 * MSEC) /* between tPDDebounce and 60ms */ +#define PD_T_SRC_RECOVER (760 * MSEC) /* between 660ms and 1000ms */ +#define PD_T_SRC_RECOVER_MAX (1000 * MSEC) /* 1000ms */ +#define PD_T_SRC_TURN_ON (275 * MSEC) /* 275ms */ +#define PD_T_SAFE_0V (650 * MSEC) /* 650ms */ +#define PD_T_NO_RESPONSE (5500 * MSEC) /* between 4.5s and 5.5s */ +#define PD_T_BIST_TRANSMIT (50 * MSEC) /* 50ms (for task_wait arg) */ +#define PD_T_BIST_RECEIVE (60 * MSEC) /* 60ms (time to process bist) */ +#define PD_T_BIST_CONT_MODE (55 * MSEC) /* 30ms to 60ms */ +#define PD_T_VCONN_SOURCE_ON (100 * MSEC) /* 100ms */ +#define PD_T_DRP_TRY (125 * MSEC) /* between 75ms and 150ms */ +#define PD_T_TRY_TIMEOUT (550 * MSEC) /* between 550ms and 1100ms */ +#define PD_T_TRY_WAIT (600 * MSEC) /* Wait time for TryWait.SNK */ +#define PD_T_SINK_REQUEST (100 * MSEC) /* 100ms before next request */ +#define PD_T_PD_DEBOUNCE (15 * MSEC) /* between 10ms and 20ms */ +#define PD_T_CHUNK_SENDER_RESPONSE (25 * MSEC) /* 25ms */ +#define PD_T_CHUNK_SENDER_REQUEST (25 * MSEC) /* 25ms */ +#define PD_T_SWAP_SOURCE_START (25 * MSEC) /* Min of 20ms */ +#define PD_T_RP_VALUE_CHANGE (20 * MSEC) /* 20ms */ +#define PD_T_SRC_DISCONNECT (15 * MSEC) /* 15ms */ +#define PD_T_SRC_TRANSITION (25 * MSEC) /* 25ms to 35 ms */ +#define PD_T_VCONN_STABLE (50 * MSEC) /* 50ms */ +#define PD_T_DISCOVER_IDENTITY (45 * MSEC) /* between 40ms and 50ms */ +#define PD_T_SYSJUMP (1000 * MSEC) /* 1s */ +#define PD_T_PR_SWAP_WAIT (100 * MSEC) /* tPRSwapWait 100ms */ +#define PD_T_DATA_RESET (225 * MSEC) /* between 200ms and 250ms */ +#define PD_T_DATA_RESET_FAIL (300 * MSEC) /* 300ms */ +#define PD_T_VCONN_REAPPLIED (10 * MSEC) /* between 10ms and 20ms */ +#define PD_T_VCONN_DISCHARGE (240 * MSEC) /* between 160ms and 240ms */ /* * Non-spec timer to prevent going Unattached if Vbus drops before a partner FRS * signal comes through. This timer should be shorter than tSinkDisconnect * (40ms) to ensure we still transition out of Attached.SNK in time. */ -#define PD_T_FRS_VBUS_DEBOUNCE (5*MSEC) +#define PD_T_FRS_VBUS_DEBOUNCE (5 * MSEC) /* number of edges and time window to detect CC line is not idle */ -#define PD_RX_TRANSITION_COUNT 3 +#define PD_RX_TRANSITION_COUNT 3 #define PD_RX_TRANSITION_WINDOW 20 /* between 12us and 20us */ /* from USB Type-C Specification Table 5-1 */ -#define PD_T_AME (1*SECOND) /* timeout from UFP attach to Alt Mode Entry */ +#define PD_T_AME (1 * SECOND) /* timeout from UFP attach to Alt Mode Entry */ /* VDM Timers ( USB PD Spec Rev2.0 Table 6-30 )*/ -#define PD_T_VDM_BUSY (50*MSEC) /* at least 50ms */ -#define PD_T_VDM_E_MODE (25*MSEC) /* enter/exit the same max */ -#define PD_T_VDM_RCVR_RSP (15*MSEC) /* max of 15ms */ -#define PD_T_VDM_SNDR_RSP (30*MSEC) /* max of 30ms */ -#define PD_T_VDM_WAIT_MODE_E (100*MSEC) /* enter/exit the same max */ +#define PD_T_VDM_BUSY (50 * MSEC) /* at least 50ms */ +#define PD_T_VDM_E_MODE (25 * MSEC) /* enter/exit the same max */ +#define PD_T_VDM_RCVR_RSP (15 * MSEC) /* max of 15ms */ +#define PD_T_VDM_SNDR_RSP (30 * MSEC) /* max of 30ms */ +#define PD_T_VDM_WAIT_MODE_E (100 * MSEC) /* enter/exit the same max */ /* CTVPD Timers ( USB Type-C ECN Table 4-27 ) */ -#define PD_T_VPDDETACH (20*MSEC) /* max of 20*MSEC */ -#define PD_T_VPDCTDD (4*MSEC) /* max of 4ms */ -#define PD_T_VPDDISABLE (25*MSEC) /* min of 25ms */ +#define PD_T_VPDDETACH (20 * MSEC) /* max of 20*MSEC */ +#define PD_T_VPDCTDD (4 * MSEC) /* max of 4ms */ +#define PD_T_VPDDISABLE (25 * MSEC) /* min of 25ms */ /* Voltage thresholds in mV (Table 7-24, PD 3.0 Version 2.0 Spec) */ -#define PD_V_SAFE0V_MAX 800 -#define PD_V_SAFE5V_MIN 4750 -#define PD_V_SAFE5V_NOM 5000 -#define PD_V_SAFE5V_MAX 5500 +#define PD_V_SAFE0V_MAX 800 +#define PD_V_SAFE5V_MIN 4750 +#define PD_V_SAFE5V_NOM 5000 +#define PD_V_SAFE5V_MAX 5500 /* USB Type-C voltages in mV (Table 4-3, USB Type-C Release 2.0 Spec) */ #define PD_V_SINK_DISCONNECT_MAX 3670 /* TODO(b/149530538): Add equation for vSinkDisconnectPD */ /* Maximum voltage in mV offered by PD 3.0 Version 2.0 Spec */ -#define PD_REV3_MAX_VOLTAGE 20000 +#define PD_REV3_MAX_VOLTAGE 20000 /* Power in mW at which we will automatically charge from a DRP partner */ -#define PD_DRP_CHARGE_POWER_MIN 27000 +#define PD_DRP_CHARGE_POWER_MIN 27000 /* function table for entered mode */ struct amode_fx { @@ -325,9 +316,9 @@ struct svdm_response { * value after resetting connection information via memset. */ enum pd_discovery_state { - PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */ - PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */ - PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */ + PD_DISC_NEEDED = 0, /* Cable or partner still needs to be probed */ + PD_DISC_COMPLETE, /* Successfully probed, valid to read VDO */ + PD_DISC_FAIL, /* Cable did not respond, or Discover* NAK */ }; /* Mode discovery state for a particular SVID with a particular transmit type */ @@ -391,8 +382,8 @@ enum hpd_event { }; /* DisplayPort flags */ -#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */ -#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */ +#define DP_FLAGS_DP_ON BIT(0) /* Display port mode is on */ +#define DP_FLAGS_HPD_HI_PENDING BIT(1) /* Pending HPD_HI */ /* Discover Identity ACK contents after headers */ union disc_ident_ack { @@ -408,7 +399,7 @@ union disc_ident_ack { uint32_t raw_value[PDO_MAX_OBJECTS - 1]; }; BUILD_ASSERT(sizeof(union disc_ident_ack) == - sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1)); + sizeof(uint32_t) * (PDO_MAX_OBJECTS - 1)); /* Discover Identity data - ACK plus discovery state */ struct identity_data { @@ -428,10 +419,10 @@ enum pd_alternate_modes { /* Discover and possibly enter modes for all SOP* communications when enabled */ #ifdef CONFIG_USB_PD_DECODE_SOP #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP_PRIME + 1) -#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1) +#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP_PRIME_PRIME + 1) #else #define DISCOVERY_TYPE_COUNT (TCPCI_MSG_SOP + 1) -#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1) +#define AMODE_TYPE_COUNT (TCPCI_MSG_SOP + 1) #endif /* Discovery results for a port partner (SOP) or cable plug (SOP') */ @@ -485,56 +476,53 @@ struct partner_active_modes { * <4:0> :: command */ #define VDO(vid, type, custom) \ - (((vid) << 16) | \ - ((type) << 15) | \ - ((custom) & 0x7FFF)) - -#define VDO_SVDM_TYPE BIT(15) -#define VDO_SVDM_VERS(x) (x << 13) -#define VDO_OPOS(x) (x << 8) -#define VDO_CMDT(x) (x << 6) -#define VDO_OPOS_MASK VDO_OPOS(0x7) -#define VDO_CMDT_MASK VDO_CMDT(0x3) - -#define CMDT_INIT 0 -#define CMDT_RSP_ACK 1 -#define CMDT_RSP_NAK 2 + (((vid) << 16) | ((type) << 15) | ((custom)&0x7FFF)) + +#define VDO_SVDM_TYPE BIT(15) +#define VDO_SVDM_VERS(x) (x << 13) +#define VDO_OPOS(x) (x << 8) +#define VDO_CMDT(x) (x << 6) +#define VDO_OPOS_MASK VDO_OPOS(0x7) +#define VDO_CMDT_MASK VDO_CMDT(0x3) + +#define CMDT_INIT 0 +#define CMDT_RSP_ACK 1 +#define CMDT_RSP_NAK 2 #define CMDT_RSP_BUSY 3 - /* reserved for SVDM ... for Google UVDM */ #define VDO_SRC_INITIATOR (0 << 5) #define VDO_SRC_RESPONDER BIT(5) -#define CMD_DISCOVER_IDENT 1 -#define CMD_DISCOVER_SVID 2 -#define CMD_DISCOVER_MODES 3 -#define CMD_ENTER_MODE 4 -#define CMD_EXIT_MODE 5 -#define CMD_ATTENTION 6 -#define CMD_DP_STATUS 16 -#define CMD_DP_CONFIG 17 +#define CMD_DISCOVER_IDENT 1 +#define CMD_DISCOVER_SVID 2 +#define CMD_DISCOVER_MODES 3 +#define CMD_ENTER_MODE 4 +#define CMD_EXIT_MODE 5 +#define CMD_ATTENTION 6 +#define CMD_DP_STATUS 16 +#define CMD_DP_CONFIG 17 -#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f)) +#define VDO_CMD_VENDOR(x) (((10 + (x)) & 0x1f)) /* ChromeOS specific commands */ -#define VDO_CMD_VERSION VDO_CMD_VENDOR(0) -#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1) -#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2) -#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5) -#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6) -#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7) -#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8) -#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10) -#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11) -#define VDO_CMD_FLIP VDO_CMD_VENDOR(12) -#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13) -#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14) - -#define PD_VDO_VID(vdo) ((vdo) >> 16) +#define VDO_CMD_VERSION VDO_CMD_VENDOR(0) +#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1) +#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2) +#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5) +#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6) +#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7) +#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8) +#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10) +#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11) +#define VDO_CMD_FLIP VDO_CMD_VENDOR(12) +#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13) +#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14) + +#define PD_VDO_VID(vdo) ((vdo) >> 16) #define PD_VDO_SVDM(vdo) (((vdo) >> 15) & 1) #define PD_VDO_OPOS(vdo) (((vdo) >> 8) & 0x7) -#define PD_VDO_CMD(vdo) ((vdo) & 0x1f) +#define PD_VDO_CMD(vdo) ((vdo)&0x1f) #define PD_VDO_CMDT(vdo) (((vdo) >> 6) & 0x3) /* @@ -556,37 +544,37 @@ struct partner_active_modes { * [6] :: Product type DFP VDO * */ -#define VDO_INDEX_HDR 0 -#define VDO_INDEX_IDH 1 -#define VDO_INDEX_CSTAT 2 -#define VDO_INDEX_CABLE 3 -#define VDO_INDEX_PRODUCT 3 -#define VDO_INDEX_AMA 4 +#define VDO_INDEX_HDR 0 +#define VDO_INDEX_IDH 1 +#define VDO_INDEX_CSTAT 2 +#define VDO_INDEX_CABLE 3 +#define VDO_INDEX_PRODUCT 3 +#define VDO_INDEX_AMA 4 #define VDO_INDEX_PTYPE_UFP1_VDO 4 -#define VDO_INDEX_PTYPE_CABLE1 4 +#define VDO_INDEX_PTYPE_CABLE1 4 #define VDO_INDEX_PTYPE_UFP2_VDO 5 -#define VDO_INDEX_PTYPE_CABLE2 5 -#define VDO_INDEX_PTYPE_DFP_VDO 6 +#define VDO_INDEX_PTYPE_CABLE2 5 +#define VDO_INDEX_PTYPE_DFP_VDO 6 #define VDO_I(name) VDO_INDEX_##name /* PD Rev 2.0 ID Header VDO */ -#define VDO_IDH(usbh, usbd, ptype, is_modal, vid) \ - ((usbh) << 31 | (usbd) << 30 | ((ptype) & 0x7) << 27 \ - | (is_modal) << 26 | ((vid) & 0xffff)) +#define VDO_IDH(usbh, usbd, ptype, is_modal, vid) \ + ((usbh) << 31 | (usbd) << 30 | ((ptype)&0x7) << 27 | \ + (is_modal) << 26 | ((vid)&0xffff)) /* PD Rev 3.0 ID Header VDO */ -#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid) \ - (VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) \ - | ((ptype_d) & 0x7) << 23 | ((ctype) & 0x3) << 21) +#define VDO_IDH_REV30(usbh, usbd, ptype_u, is_modal, ptype_d, ctype, vid) \ + (VDO_IDH(usbh, usbd, ptype_u, is_modal, vid) | ((ptype_d)&0x7) << 23 | \ + ((ctype)&0x3) << 21) -#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7) +#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7) #define PD_IDH_IS_MODAL(vdo) (((vdo) >> 26) & 0x1) -#define PD_IDH_VID(vdo) ((vdo) & 0xffff) +#define PD_IDH_VID(vdo) ((vdo)&0xffff) -#define VDO_CSTAT(tid) ((tid) & 0xfffff) -#define PD_CSTAT_TID(vdo) ((vdo) & 0xfffff) +#define VDO_CSTAT(tid) ((tid)&0xfffff) +#define PD_CSTAT_TID(vdo) ((vdo)&0xfffff) -#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff)) +#define VDO_PRODUCT(pid, bcd) (((pid)&0xffff) << 16 | ((bcd)&0xffff)) #define PD_PRODUCT_PID(vdo) (((vdo) >> 16) & 0xffff) /* @@ -622,9 +610,9 @@ enum pd_rev_type { }; #ifdef CONFIG_USB_PD_REV30 -#define PD_REVISION PD_REV30 +#define PD_REVISION PD_REV30 #else -#define PD_REVISION PD_REV20 +#define PD_REVISION PD_REV20 #endif #if defined(CONFIG_USB_PD_TCPMV1) @@ -649,18 +637,17 @@ struct pd_cable { /* Cable revision */ enum pd_rev_type rev; - }; /* Note: These flags are only used for TCPMv1 */ /* Check if Thunderbolt-compatible mode enabled */ -#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0) +#define CABLE_FLAGS_TBT_COMPAT_ENABLE BIT(0) /* Flag to limit speed to TBT Gen 2 passive cable */ #define CABLE_FLAGS_TBT_COMPAT_LIMIT_SPEED BIT(1) /* Flag for checking if device is USB4.0 capable */ -#define CABLE_FLAGS_USB4_CAPABLE BIT(2) +#define CABLE_FLAGS_USB4_CAPABLE BIT(2) /* Flag for entering ENTER_USB mode */ -#define CABLE_FLAGS_ENTER_USB_MODE BIT(3) +#define CABLE_FLAGS_ENTER_USB_MODE BIT(3) /* * SVDM Discover SVIDs request -> response @@ -670,9 +657,9 @@ struct pd_cable { * mark the end of SVIDs. If more than 12 SVIDs are supported command SHOULD be * repeated. */ -#define VDO_SVID(svid0, svid1) (((svid0) & 0xffff) << 16 | ((svid1) & 0xffff)) +#define VDO_SVID(svid0, svid1) (((svid0)&0xffff) << 16 | ((svid1)&0xffff)) #define PD_VDO_SVID_SVID0(vdo) ((vdo) >> 16) -#define PD_VDO_SVID_SVID1(vdo) ((vdo) & 0xffff) +#define PD_VDO_SVID_SVID1(vdo) ((vdo)&0xffff) /* * Google modes capabilities @@ -702,10 +689,9 @@ struct pd_cable { * Other bits are reserved. * <1:0> : signal direction ( 00b=rsv, 01b=sink, 10b=src 11b=both ) */ -#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir) \ - (((snkp) & 0xff) << 16 | ((srcp) & 0xff) << 8 \ - | ((usb) & 1) << 7 | ((gdr) & 1) << 6 | ((sign) & 0xF) << 2 \ - | ((sdir) & 0x3)) +#define VDO_MODE_DP(snkp, srcp, usb, gdr, sign, sdir) \ + (((snkp)&0xff) << 16 | ((srcp)&0xff) << 8 | ((usb)&1) << 7 | \ + ((gdr)&1) << 6 | ((sign)&0xF) << 2 | ((sdir)&0x3)) #define MODE_DP_DFP_PIN_SHIFT 8 #define MODE_DP_UFP_PIN_SHIFT 16 @@ -719,11 +705,11 @@ struct pd_cable { /* Pin configs A/B/C/D/E/F */ #define MODE_DP_PIN_CAPS_MASK 0x3f -#define MODE_DP_V13 0x1 +#define MODE_DP_V13 0x1 #define MODE_DP_GEN2 0x2 -#define MODE_DP_SNK 0x1 -#define MODE_DP_SRC 0x2 +#define MODE_DP_SNK 0x1 +#define MODE_DP_SRC 0x2 #define MODE_DP_BOTH 0x3 #define MODE_DP_CABLE_SHIFT 6 @@ -740,9 +726,10 @@ struct pd_cable { * or UFP_D (if receptacle==1) * Also refer to DisplayPort Alt Mode Capabilities Clarification (4/30/2015) */ -#define PD_DP_PIN_CAPS(x) ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) \ - ? (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) \ - : (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK)) +#define PD_DP_PIN_CAPS(x) \ + ((((x) >> MODE_DP_CABLE_SHIFT) & 0x1) ? \ + (((x) >> MODE_DP_UFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK) : \ + (((x) >> MODE_DP_DFP_PIN_SHIFT) & MODE_DP_PIN_CAPS_MASK)) /* * DisplayPort Status VDO @@ -758,10 +745,10 @@ struct pd_cable { * <1:0> : connect status : 00b == no (DFP|UFP)_D is connected or disabled. * 01b == DFP_D connected, 10b == UFP_D connected, 11b == both. */ -#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn) \ - (((irq) & 1) << 8 | ((lvl) & 1) << 7 | ((amode) & 1) << 6 \ - | ((usbc) & 1) << 5 | ((mf) & 1) << 4 | ((en) & 1) << 3 \ - | ((lp) & 1) << 2 | ((conn & 0x3) << 0)) +#define VDO_DP_STATUS(irq, lvl, amode, usbc, mf, en, lp, conn) \ + (((irq)&1) << 8 | ((lvl)&1) << 7 | ((amode)&1) << 6 | \ + ((usbc)&1) << 5 | ((mf)&1) << 4 | ((en)&1) << 3 | ((lp)&1) << 2 | \ + ((conn & 0x3) << 0)) #define PD_VDO_DPSTS_MF_MASK BIT(4) @@ -770,9 +757,9 @@ struct pd_cable { #define PD_VDO_DPSTS_MF_PREF(x) (((x) >> 4) & 1) /* Per DisplayPort Spec v1.3 Section 3.3 */ -#define HPD_USTREAM_DEBOUNCE_LVL (2*MSEC) +#define HPD_USTREAM_DEBOUNCE_LVL (2 * MSEC) #define HPD_USTREAM_DEBOUNCE_IRQ (250) -#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */ +#define HPD_DSTREAM_DEBOUNCE_IRQ (500) /* between 500-1000us */ /* * DisplayPort Configure VDO @@ -786,7 +773,7 @@ struct pd_cable { * <1:0> : cfg : 00 == USB, 01 == DFP_D, 10 == UFP_D, 11 == reserved */ #define VDO_DP_CFG(pin, sig, cfg) \ - (((pin) & 0xff) << 8 | ((sig) & 0xf) << 2 | ((cfg) & 0x3)) + (((pin)&0xff) << 8 | ((sig)&0xf) << 2 | ((cfg)&0x3)) #define PD_DP_CFG_DPON(x) (((x & 0x3) == 1) || ((x & 0x3) == 2)) /* @@ -794,18 +781,18 @@ struct pd_cable { * for backward compatibility, if it is null, * get the former sink pin assignment we used to be in <23:16>. */ -#define PD_DP_CFG_PIN(x) ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) \ - : (((x) >> 16) & 0xff)) +#define PD_DP_CFG_PIN(x) \ + ((((x) >> 8) & 0xff) ? (((x) >> 8) & 0xff) : (((x) >> 16) & 0xff)) /* * ChromeOS specific PD device Hardware IDs. Used to identify unique * products and used in VDO_INFO. Note this field is 10 bits. */ -#define USB_PD_HW_DEV_ID_RESERVED 0 -#define USB_PD_HW_DEV_ID_ZINGER 1 -#define USB_PD_HW_DEV_ID_MINIMUFFIN 2 -#define USB_PD_HW_DEV_ID_DINGDONG 3 -#define USB_PD_HW_DEV_ID_HOHO 4 -#define USB_PD_HW_DEV_ID_HONEYBUNS 5 +#define USB_PD_HW_DEV_ID_RESERVED 0 +#define USB_PD_HW_DEV_ID_ZINGER 1 +#define USB_PD_HW_DEV_ID_MINIMUFFIN 2 +#define USB_PD_HW_DEV_ID_DINGDONG 3 +#define USB_PD_HW_DEV_ID_HOHO 4 +#define USB_PD_HW_DEV_ID_HONEYBUNS 5 /* * ChromeOS specific VDO_CMD_READ_INFO responds with device info including: @@ -815,19 +802,18 @@ struct pd_cable { * SW Debug Version: Software version useful for debugging (15 bits) * IS RW: True if currently in RW, False otherwise (1 bit) */ -#define VDO_INFO(id, id_minor, ver, is_rw) ((id_minor) << 26 \ - | ((id) & 0x3ff) << 16 \ - | ((ver) & 0x7fff) << 1 \ - | ((is_rw) & 1)) -#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16) -#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff) -#define VDO_INFO_IS_RW(x) ((x) & 1) +#define VDO_INFO(id, id_minor, ver, is_rw) \ + ((id_minor) << 26 | ((id)&0x3ff) << 16 | ((ver)&0x7fff) << 1 | \ + ((is_rw)&1)) +#define VDO_INFO_HW_DEV_ID(x) ((x) >> 16) +#define VDO_INFO_SW_DBG_VER(x) (((x) >> 1) & 0x7fff) +#define VDO_INFO_IS_RW(x) ((x)&1) #define HW_DEV_ID_MAJ(x) (x & 0x3ff) #define HW_DEV_ID_MIN(x) ((x) >> 10) /* USB-IF SIDs */ -#define USB_SID_PD 0xff00 /* power delivery */ +#define USB_SID_PD 0xff00 /* power delivery */ #define USB_SID_DISPLAYPORT 0xff01 #define USB_GOOGLE_TYPEC_URL "http://www.google.com/chrome/devices/typec" @@ -835,19 +821,19 @@ struct pd_cable { #define USB_VID_GOOGLE 0x18d1 /* Other Vendor IDs */ -#define USB_VID_APPLE 0x05ac +#define USB_VID_APPLE 0x05ac #define USB_PID1_APPLE 0x1012 #define USB_PID2_APPLE 0x1013 -#define USB_VID_HP 0x03F0 -#define USB_PID_HP_USB_C_DOCK_G5 0x036B -#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B -#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467 -#define USB_PID_HP_ELITE_E233_MONITOR 0x1747 -#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D -#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E +#define USB_VID_HP 0x03F0 +#define USB_PID_HP_USB_C_DOCK_G5 0x036B +#define USB_PID_HP_USB_C_A_UNIV_DOCK_G2 0x096B +#define USB_PID_HP_E24D_DOCK_MONITOR 0x0467 +#define USB_PID_HP_ELITE_E233_MONITOR 0x1747 +#define USB_PID_HP_E244D_DOCK_MONITOR 0x056D +#define USB_PID_HP_E274D_DOCK_MONITOR 0x016E -#define USB_VID_INTEL 0x8087 +#define USB_VID_INTEL 0x8087 /* Timeout for message receive in microseconds */ #define USB_PD_RX_TMOUT_US 1800 @@ -855,46 +841,46 @@ struct pd_cable { /* --- Protocol layer functions --- */ enum pd_states { - PD_STATE_DISABLED, /* C0 */ - PD_STATE_SUSPENDED, /* C1 */ - PD_STATE_SNK_DISCONNECTED, /* C2 */ - PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3 */ - PD_STATE_SNK_HARD_RESET_RECOVER, /* C4 */ - PD_STATE_SNK_DISCOVERY, /* C5 */ - PD_STATE_SNK_REQUESTED, /* C6 */ - PD_STATE_SNK_TRANSITION, /* C7 */ - PD_STATE_SNK_READY, /* C8 */ - PD_STATE_SNK_SWAP_INIT, /* C9 */ - PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */ - PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */ - PD_STATE_SNK_SWAP_STANDBY, /* C12 */ - PD_STATE_SNK_SWAP_COMPLETE, /* C13 */ - PD_STATE_SRC_DISCONNECTED, /* C14 */ - PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */ - PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */ - PD_STATE_SRC_STARTUP, /* C17 */ - PD_STATE_SRC_DISCOVERY, /* C18 */ - PD_STATE_SRC_NEGOCIATE, /* C19 */ - PD_STATE_SRC_ACCEPTED, /* C20 */ - PD_STATE_SRC_POWERED, /* C21 */ - PD_STATE_SRC_TRANSITION, /* C22 */ - PD_STATE_SRC_READY, /* C23 */ - PD_STATE_SRC_GET_SINK_CAP, /* C24 */ - PD_STATE_DR_SWAP, /* C25 */ - PD_STATE_SRC_SWAP_INIT, /* C26 */ - PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */ - PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */ - PD_STATE_SRC_SWAP_STANDBY, /* C29 */ - PD_STATE_VCONN_SWAP_SEND, /* C30 */ - PD_STATE_VCONN_SWAP_INIT, /* C31 */ - PD_STATE_VCONN_SWAP_READY, /* C32 */ - PD_STATE_SOFT_RESET, /* C33 */ - PD_STATE_HARD_RESET_SEND, /* C34 */ - PD_STATE_HARD_RESET_EXECUTE, /* C35 */ - PD_STATE_BIST_RX, /* C36 */ - PD_STATE_BIST_TX, /* C37 */ - PD_STATE_DRP_AUTO_TOGGLE, /* C38 */ - PD_STATE_ENTER_USB, /* C39 */ + PD_STATE_DISABLED, /* C0 */ + PD_STATE_SUSPENDED, /* C1 */ + PD_STATE_SNK_DISCONNECTED, /* C2 */ + PD_STATE_SNK_DISCONNECTED_DEBOUNCE, /* C3 */ + PD_STATE_SNK_HARD_RESET_RECOVER, /* C4 */ + PD_STATE_SNK_DISCOVERY, /* C5 */ + PD_STATE_SNK_REQUESTED, /* C6 */ + PD_STATE_SNK_TRANSITION, /* C7 */ + PD_STATE_SNK_READY, /* C8 */ + PD_STATE_SNK_SWAP_INIT, /* C9 */ + PD_STATE_SNK_SWAP_SNK_DISABLE, /* C10 */ + PD_STATE_SNK_SWAP_SRC_DISABLE, /* C11 */ + PD_STATE_SNK_SWAP_STANDBY, /* C12 */ + PD_STATE_SNK_SWAP_COMPLETE, /* C13 */ + PD_STATE_SRC_DISCONNECTED, /* C14 */ + PD_STATE_SRC_DISCONNECTED_DEBOUNCE, /* C15 */ + PD_STATE_SRC_HARD_RESET_RECOVER, /* C16 */ + PD_STATE_SRC_STARTUP, /* C17 */ + PD_STATE_SRC_DISCOVERY, /* C18 */ + PD_STATE_SRC_NEGOCIATE, /* C19 */ + PD_STATE_SRC_ACCEPTED, /* C20 */ + PD_STATE_SRC_POWERED, /* C21 */ + PD_STATE_SRC_TRANSITION, /* C22 */ + PD_STATE_SRC_READY, /* C23 */ + PD_STATE_SRC_GET_SINK_CAP, /* C24 */ + PD_STATE_DR_SWAP, /* C25 */ + PD_STATE_SRC_SWAP_INIT, /* C26 */ + PD_STATE_SRC_SWAP_SNK_DISABLE, /* C27 */ + PD_STATE_SRC_SWAP_SRC_DISABLE, /* C28 */ + PD_STATE_SRC_SWAP_STANDBY, /* C29 */ + PD_STATE_VCONN_SWAP_SEND, /* C30 */ + PD_STATE_VCONN_SWAP_INIT, /* C31 */ + PD_STATE_VCONN_SWAP_READY, /* C32 */ + PD_STATE_SOFT_RESET, /* C33 */ + PD_STATE_HARD_RESET_SEND, /* C34 */ + PD_STATE_HARD_RESET_EXECUTE, /* C35 */ + PD_STATE_BIST_RX, /* C36 */ + PD_STATE_BIST_TX, /* C37 */ + PD_STATE_DRP_AUTO_TOGGLE, /* C38 */ + PD_STATE_ENTER_USB, /* C39 */ /* Number of states. Not an actual state. */ PD_STATE_COUNT, }; @@ -939,23 +925,23 @@ enum pd_states { #ifdef CONFIG_USB_PD_TCPMV1 /* Flags used for TCPMv1 */ -#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */ -#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */ -#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */ -#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */ -#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */ -#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */ +#define PD_FLAGS_PING_ENABLED BIT(0) /* SRC_READY pings enabled */ +#define PD_FLAGS_PARTNER_DR_POWER BIT(1) /* port partner is dualrole power */ +#define PD_FLAGS_PARTNER_DR_DATA BIT(2) /* port partner is dualrole data */ +#define PD_FLAGS_CHECK_IDENTITY BIT(3) /* discover identity in READY */ +#define PD_FLAGS_SNK_CAP_RECVD BIT(4) /* sink capabilities received */ +#define PD_FLAGS_TCPC_DRP_TOGGLE BIT(5) /* TCPC-controlled DRP toggling */ #define PD_FLAGS_EXPLICIT_CONTRACT BIT(6) /* explicit pwr contract in place */ -#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */ -#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */ -#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */ -#define PD_FLAGS_CHECK_DR_ROLE BIT(10)/* check data role in READY */ -#define PD_FLAGS_PARTNER_UNCONSTR BIT(11)/* port partner unconstrained pwr */ -#define PD_FLAGS_VCONN_ON BIT(12)/* vconn is being sourced */ -#define PD_FLAGS_TRY_SRC BIT(13)/* Try.SRC states are active */ -#define PD_FLAGS_PARTNER_USB_COMM BIT(14)/* port partner is USB comms */ -#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15)/* send new source capabilities */ -#define PD_FLAGS_TS_DTS_PARTNER BIT(16)/* partner has rp/rp or rd/rd */ +#define PD_FLAGS_VBUS_NEVER_LOW BIT(7) /* VBUS input has never been low */ +#define PD_FLAGS_PREVIOUS_PD_CONN BIT(8) /* previously PD connected */ +#define PD_FLAGS_CHECK_PR_ROLE BIT(9) /* check power role in READY */ +#define PD_FLAGS_CHECK_DR_ROLE BIT(10) /* check data role in READY */ +#define PD_FLAGS_PARTNER_UNCONSTR BIT(11) /* port partner unconstrained pwr */ +#define PD_FLAGS_VCONN_ON BIT(12) /* vconn is being sourced */ +#define PD_FLAGS_TRY_SRC BIT(13) /* Try.SRC states are active */ +#define PD_FLAGS_PARTNER_USB_COMM BIT(14) /* port partner is USB comms */ +#define PD_FLAGS_UPDATE_SRC_CAPS BIT(15) /* send new source capabilities */ +#define PD_FLAGS_TS_DTS_PARTNER BIT(16) /* partner has rp/rp or rd/rd */ /* * These PD_FLAGS_LPM* flags track the software state (PD_LPM_FLAGS_REQUESTED) * and hardware state (PD_LPM_FLAGS_ENGAGED) of the TCPC low power mode. @@ -963,26 +949,26 @@ enum pd_states { * low power (when PD_LPM_FLAGS_ENGAGED is changing). */ #ifdef CONFIG_USB_PD_TCPC_LOW_POWER -#define PD_FLAGS_LPM_REQUESTED BIT(17)/* Tracks SW LPM state */ -#define PD_FLAGS_LPM_ENGAGED BIT(18)/* Tracks HW LPM state */ -#define PD_FLAGS_LPM_TRANSITION BIT(19)/* Tracks HW LPM transition */ -#define PD_FLAGS_LPM_EXIT BIT(19)/* Tracks HW LPM exit */ +#define PD_FLAGS_LPM_REQUESTED BIT(17) /* Tracks SW LPM state */ +#define PD_FLAGS_LPM_ENGAGED BIT(18) /* Tracks HW LPM state */ +#define PD_FLAGS_LPM_TRANSITION BIT(19) /* Tracks HW LPM transition */ +#define PD_FLAGS_LPM_EXIT BIT(19) /* Tracks HW LPM exit */ #endif /* * Tracks whether port negotiation may have stalled due to not starting reset * timers in SNK_DISCOVERY */ -#define PD_FLAGS_SNK_WAITING_BATT BIT(21) +#define PD_FLAGS_SNK_WAITING_BATT BIT(21) /* Check vconn state in READY */ #define PD_FLAGS_CHECK_VCONN_STATE BIT(22) #endif /* CONFIG_USB_PD_TCPMV1 */ /* Per-port battery backed RAM flags */ #define PD_BBRMFLG_EXPLICIT_CONTRACT BIT(0) -#define PD_BBRMFLG_POWER_ROLE BIT(1) -#define PD_BBRMFLG_DATA_ROLE BIT(2) -#define PD_BBRMFLG_VCONN_ROLE BIT(3) -#define PD_BBRMFLG_DBGACC_ROLE BIT(4) +#define PD_BBRMFLG_POWER_ROLE BIT(1) +#define PD_BBRMFLG_DATA_ROLE BIT(2) +#define PD_BBRMFLG_VCONN_ROLE BIT(3) +#define PD_BBRMFLG_DBGACC_ROLE BIT(4) /* Initial value for CC debounce variable */ #define PD_CC_UNSET -1 @@ -1005,31 +991,31 @@ enum pd_dual_role_states { * NOTE: These are usually set by host commands from the AP. */ enum pd_dpm_request { - DPM_REQUEST_DR_SWAP = BIT(0), - DPM_REQUEST_PR_SWAP = BIT(1), - DPM_REQUEST_VCONN_SWAP = BIT(2), - DPM_REQUEST_GOTO_MIN = BIT(3), - DPM_REQUEST_SRC_CAP_CHANGE = BIT(4), - DPM_REQUEST_GET_SNK_CAPS = BIT(5), - DPM_REQUEST_SEND_PING = BIT(6), - DPM_REQUEST_SOURCE_CAP = BIT(7), - DPM_REQUEST_NEW_POWER_LEVEL = BIT(8), - DPM_REQUEST_VDM = BIT(9), - DPM_REQUEST_BIST_TX = BIT(10), - DPM_REQUEST_SNK_STARTUP = BIT(11), - DPM_REQUEST_SRC_STARTUP = BIT(12), - DPM_REQUEST_HARD_RESET_SEND = BIT(13), - DPM_REQUEST_SOFT_RESET_SEND = BIT(14), - DPM_REQUEST_PORT_DISCOVERY = BIT(15), - DPM_REQUEST_SEND_ALERT = BIT(16), - DPM_REQUEST_ENTER_USB = BIT(17), - DPM_REQUEST_GET_SRC_CAPS = BIT(18), - DPM_REQUEST_EXIT_MODES = BIT(19), - DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20), - DPM_REQUEST_FRS_DET_ENABLE = BIT(21), - DPM_REQUEST_FRS_DET_DISABLE = BIT(22), - DPM_REQUEST_DATA_RESET = BIT(23), - DPM_REQUEST_GET_REVISION = BIT(24), + DPM_REQUEST_DR_SWAP = BIT(0), + DPM_REQUEST_PR_SWAP = BIT(1), + DPM_REQUEST_VCONN_SWAP = BIT(2), + DPM_REQUEST_GOTO_MIN = BIT(3), + DPM_REQUEST_SRC_CAP_CHANGE = BIT(4), + DPM_REQUEST_GET_SNK_CAPS = BIT(5), + DPM_REQUEST_SEND_PING = BIT(6), + DPM_REQUEST_SOURCE_CAP = BIT(7), + DPM_REQUEST_NEW_POWER_LEVEL = BIT(8), + DPM_REQUEST_VDM = BIT(9), + DPM_REQUEST_BIST_TX = BIT(10), + DPM_REQUEST_SNK_STARTUP = BIT(11), + DPM_REQUEST_SRC_STARTUP = BIT(12), + DPM_REQUEST_HARD_RESET_SEND = BIT(13), + DPM_REQUEST_SOFT_RESET_SEND = BIT(14), + DPM_REQUEST_PORT_DISCOVERY = BIT(15), + DPM_REQUEST_SEND_ALERT = BIT(16), + DPM_REQUEST_ENTER_USB = BIT(17), + DPM_REQUEST_GET_SRC_CAPS = BIT(18), + DPM_REQUEST_EXIT_MODES = BIT(19), + DPM_REQUEST_SOP_PRIME_SOFT_RESET_SEND = BIT(20), + DPM_REQUEST_FRS_DET_ENABLE = BIT(21), + DPM_REQUEST_FRS_DET_DISABLE = BIT(22), + DPM_REQUEST_DATA_RESET = BIT(23), + DPM_REQUEST_GET_REVISION = BIT(24), }; /** @@ -1142,7 +1128,7 @@ void pd_resume_check_pr_swap_needed(int port); /* Control Message type - USB-PD Spec Rev 3.0, Ver 1.1, Table 6-5 */ enum pd_ctrl_msg_type { - PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */ + PD_CTRL_INVALID = 0, /* 0 Reserved - DO NOT PUT IN MESSAGES */ PD_CTRL_GOOD_CRC = 1, PD_CTRL_GOTO_MIN = 2, PD_CTRL_ACCEPT = 3, @@ -1173,33 +1159,28 @@ enum pd_ctrl_msg_type { }; /* Control message types which always mark the start of an AMS */ -#define PD_CTRL_AMS_START_MASK ((1 << PD_CTRL_GOTO_MIN) | \ - (1 << PD_CTRL_GET_SOURCE_CAP) | \ - (1 << PD_CTRL_GET_SINK_CAP) | \ - (1 << PD_CTRL_DR_SWAP) | \ - (1 << PD_CTRL_PR_SWAP) | \ - (1 << PD_CTRL_VCONN_SWAP) | \ - (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | \ - (1 << PD_CTRL_GET_STATUS) | \ - (1 << PD_CTRL_FR_SWAP) | \ - (1 << PD_CTRL_GET_PPS_STATUS) | \ - (1 << PD_CTRL_GET_COUNTRY_CODES)) - +#define PD_CTRL_AMS_START_MASK \ + ((1 << PD_CTRL_GOTO_MIN) | (1 << PD_CTRL_GET_SOURCE_CAP) | \ + (1 << PD_CTRL_GET_SINK_CAP) | (1 << PD_CTRL_DR_SWAP) | \ + (1 << PD_CTRL_PR_SWAP) | (1 << PD_CTRL_VCONN_SWAP) | \ + (1 << PD_CTRL_GET_SOURCE_CAP_EXT) | (1 << PD_CTRL_GET_STATUS) | \ + (1 << PD_CTRL_FR_SWAP) | (1 << PD_CTRL_GET_PPS_STATUS) | \ + (1 << PD_CTRL_GET_COUNTRY_CODES)) /* Battery Status Data Object fields for REV 3.0 */ #define BSDO_CAP_UNKNOWN 0xffff -#define BSDO_CAP(n) (((n) & 0xffff) << 16) -#define BSDO_INVALID BIT(8) -#define BSDO_PRESENT BIT(9) +#define BSDO_CAP(n) (((n)&0xffff) << 16) +#define BSDO_INVALID BIT(8) +#define BSDO_PRESENT BIT(9) #define BSDO_DISCHARGING BIT(10) -#define BSDO_IDLE BIT(11) +#define BSDO_IDLE BIT(11) /* Battery Capability offsets for 16-bit array indexes */ -#define BCDB_VID 0 -#define BCDB_PID 1 -#define BCDB_DESIGN_CAP 2 -#define BCDB_FULL_CAP 3 -#define BCDB_BATT_TYPE 4 +#define BCDB_VID 0 +#define BCDB_PID 1 +#define BCDB_DESIGN_CAP 2 +#define BCDB_FULL_CAP 3 +#define BCDB_BATT_TYPE 4 /* Battery Capability Data Block (BCDB) in struct format. * See USB-PD spec Rev 3.1, V 1.3 section 6.5.5 @@ -1233,13 +1214,13 @@ struct pd_bcdb { * Get Battery Cap Message fields for REV 3.0 (assumes extended header is * present in first two bytes) */ -#define BATT_CAP_REF(n) (((n) >> 16) & 0xff) +#define BATT_CAP_REF(n) (((n) >> 16) & 0xff) /* SOP SDB fields for PD Rev 3.0 Section 6.5.2.1 */ enum pd_sdb_temperature_status { - PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0, - PD_SDB_TEMPERATURE_STATUS_NORMAL = 2, - PD_SDB_TEMPERATURE_STATUS_WARNING = 4, + PD_SDB_TEMPERATURE_STATUS_NOT_SUPPORTED = 0, + PD_SDB_TEMPERATURE_STATUS_NORMAL = 2, + PD_SDB_TEMPERATURE_STATUS_WARNING = 4, PD_SDB_TEMPERATURE_STATUS_OVER_TEMPERATURE = 6, } __packed; BUILD_ASSERT(sizeof(enum pd_sdb_temperature_status) == 1); @@ -1301,16 +1282,16 @@ enum pd_ext_msg_type { }; /* Alert Data Object fields for REV 3.1 */ -#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7) +#define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7) /* Alert Data Object fields for REV 3.0 */ -#define ADO_OVP_EVENT (BIT(24) << 6) -#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5) -#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4) -#define ADO_OTP_EVENT (BIT(24) << 3) -#define ADO_OCP_EVENT (BIT(24) << 2) -#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1) -#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20) -#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16) +#define ADO_OVP_EVENT (BIT(24) << 6) +#define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5) +#define ADO_OPERATING_CONDITION_CHANGE (BIT(24) << 4) +#define ADO_OTP_EVENT (BIT(24) << 3) +#define ADO_OCP_EVENT (BIT(24) << 2) +#define ADO_BATTERY_STATUS_CHANGE (BIT(24) << 1) +#define ADO_FIXED_BATTERIES(n) ((n & 0xf) << 20) +#define ADO_HOT_SWAPPABLE_BATTERIES(n) ((n & 0xf) << 16) /* Extended alert event types for REV 3.1 */ enum ado_extended_alert_event_type { @@ -1342,15 +1323,11 @@ enum pd_data_msg_type { /* 16-31 Reserved */ }; - /* * Cable plug. See 6.2.1.1.7 Cable Plug. Only applies to SOP' and SOP". * Replaced by pd_power_role for SOP packets. */ -enum pd_cable_plug { - PD_PLUG_FROM_DFP_UFP = 0, - PD_PLUG_FROM_CABLE = 1 -}; +enum pd_cable_plug { PD_PLUG_FROM_DFP_UFP = 0, PD_PLUG_FROM_CABLE = 1 }; enum cable_outlet { CABLE_PLUG = 0, @@ -1359,11 +1336,11 @@ enum cable_outlet { /* Vconn role */ #define PD_ROLE_VCONN_OFF 0 -#define PD_ROLE_VCONN_ON 1 +#define PD_ROLE_VCONN_ON 1 /* chunk is a request or response in REV 3.0 */ #define CHUNK_RESPONSE 0 -#define CHUNK_REQUEST 1 +#define CHUNK_REQUEST 1 /* collision avoidance Rp values in REV 3.0 */ #define SINK_TX_OK TYPEC_RP_3A0 @@ -1380,38 +1357,37 @@ enum cable_outlet { /* Port default state at startup */ #ifdef CONFIG_USB_PD_DUAL_ROLE -#define PD_DEFAULT_STATE(port) ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \ - PD_STATE_SRC_DISCONNECTED : \ - PD_STATE_SNK_DISCONNECTED) +#define PD_DEFAULT_STATE(port) \ + ((PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE) ? \ + PD_STATE_SRC_DISCONNECTED : \ + PD_STATE_SNK_DISCONNECTED) #else #define PD_DEFAULT_STATE(port) PD_STATE_SRC_DISCONNECTED #endif /* Build extended message header with chunking */ #define PD_EXT_HEADER(cnum, rchk, dsize) \ - (BIT(15) | ((cnum) << 11) | \ - ((rchk) << 10) | (dsize)) + (BIT(15) | ((cnum) << 11) | ((rchk) << 10) | (dsize)) /* Build extended message header without chunking */ #define PD_EXT_HEADER_UNCHUNKED(dsize) (dsize) /* build message header */ -#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \ - ((type) | ((rev) << 6) | \ - ((drole) << 5) | ((prole) << 8) | \ - ((id) << 9) | ((cnt) << 12) | ((ext) << 15)) +#define PD_HEADER(type, prole, drole, id, cnt, rev, ext) \ + ((type) | ((rev) << 6) | ((drole) << 5) | ((prole) << 8) | \ + ((id) << 9) | ((cnt) << 12) | ((ext) << 15)) /* Used for processing pd header */ -#define PD_HEADER_EXT(header) (((header) >> 15) & 1) -#define PD_HEADER_CNT(header) (((header) >> 12) & 7) +#define PD_HEADER_EXT(header) (((header) >> 15) & 1) +#define PD_HEADER_CNT(header) (((header) >> 12) & 7) /* * NOTE: bit 4 was added in PD 3.0, and should be reserved and set to 0 in PD * 2.0 messages */ -#define PD_HEADER_TYPE(header) ((header) & 0x1F) -#define PD_HEADER_ID(header) (((header) >> 9) & 7) +#define PD_HEADER_TYPE(header) ((header)&0x1F) +#define PD_HEADER_ID(header) (((header) >> 9) & 7) #define PD_HEADER_PROLE(header) (((header) >> 8) & 1) -#define PD_HEADER_REV(header) (((header) >> 6) & 3) +#define PD_HEADER_REV(header) (((header) >> 6) & 3) #define PD_HEADER_DROLE(header) (((header) >> 5) & 1) /* @@ -1420,47 +1396,47 @@ enum cable_outlet { * NOTE: This is not part of the PD spec. */ #define PD_HEADER_GET_SOP(header) (((header) >> 28) & 0xf) -#define PD_HEADER_SOP(sop) (((sop) & 0xf) << 28) +#define PD_HEADER_SOP(sop) (((sop)&0xf) << 28) /* Used for processing pd extended header */ -#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1) +#define PD_EXT_HEADER_CHUNKED(header) (((header) >> 15) & 1) #define PD_EXT_HEADER_CHUNK_NUM(header) (((header) >> 11) & 0xf) #define PD_EXT_HEADER_REQ_CHUNK(header) (((header) >> 10) & 1) -#define PD_EXT_HEADER_DATA_SIZE(header) ((header) & 0x1ff) +#define PD_EXT_HEADER_DATA_SIZE(header) ((header)&0x1ff) /* Used to get extended header from the first 32-bit word of the message */ #define GET_EXT_HEADER(msg) (msg & 0xffff) /* Extended message constants (PD 3.0, Rev. 2.0, section 6.13) */ -#define PD_MAX_EXTENDED_MSG_LEN 260 -#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26 +#define PD_MAX_EXTENDED_MSG_LEN 260 +#define PD_MAX_EXTENDED_MSG_CHUNK_LEN 26 /* K-codes for special symbols */ #define PD_SYNC1 0x18 #define PD_SYNC2 0x11 #define PD_SYNC3 0x06 -#define PD_RST1 0x07 -#define PD_RST2 0x19 -#define PD_EOP 0x0D +#define PD_RST1 0x07 +#define PD_RST2 0x19 +#define PD_EOP 0x0D /* Minimum PD supply current (mA) */ -#define PD_MIN_MA 500 +#define PD_MIN_MA 500 /* Minimum PD voltage (mV) */ -#define PD_MIN_MV 5000 +#define PD_MIN_MV 5000 /* No connect voltage threshold for sources based on Rp */ -#define PD_SRC_DEF_VNC_MV 1600 -#define PD_SRC_1_5_VNC_MV 1600 -#define PD_SRC_3_0_VNC_MV 2600 +#define PD_SRC_DEF_VNC_MV 1600 +#define PD_SRC_1_5_VNC_MV 1600 +#define PD_SRC_3_0_VNC_MV 2600 /* Rd voltage threshold for sources based on Rp */ -#define PD_SRC_DEF_RD_THRESH_MV 200 -#define PD_SRC_1_5_RD_THRESH_MV 400 -#define PD_SRC_3_0_RD_THRESH_MV 800 +#define PD_SRC_DEF_RD_THRESH_MV 200 +#define PD_SRC_1_5_RD_THRESH_MV 400 +#define PD_SRC_3_0_RD_THRESH_MV 800 /* Voltage threshold to detect connection when presenting Rd */ -#define PD_SNK_VA_MV 250 +#define PD_SNK_VA_MV 250 /* --- Policy layer functions --- */ @@ -1553,7 +1529,7 @@ void pd_process_source_cap(int port, int cnt, uint32_t *src_caps); * @param ma reduce current to minimum value. * @param mv reduce voltage to minimum value. */ -void pd_snk_give_back(int port, uint32_t * const ma, uint32_t * const mv); +void pd_snk_give_back(int port, uint32_t *const ma, uint32_t *const mv); /** * Put a cap on the max voltage requested as a sink. @@ -1661,7 +1637,6 @@ void pd_set_external_voltage_limit(int port, int mv); void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage); - /** * Update the power contract if it exists. * @@ -1733,8 +1708,7 @@ __override_proto bool pd_can_charge_from_device(int port, const int pdo_cnt, * @param data_role current data role * @return True if data swap is allowed, False otherwise */ -__override_proto int pd_check_data_swap(int port, - enum pd_data_role data_role); +__override_proto int pd_check_data_swap(int port, enum pd_data_role data_role); /** * Check if vconn swap is allowed. @@ -1752,9 +1726,8 @@ int pd_check_vconn_swap(int port); * @param pr_role Our power role * @param flags PD flags */ -__override_proto void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags); +__override_proto void pd_check_pr_role(int port, enum pd_power_role pr_role, + int flags); /** * Check current data role for potential data swap @@ -1763,9 +1736,8 @@ __override_proto void pd_check_pr_role(int port, * @param dr_role Our data role * @param flags PD flags */ -__override_proto void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags); +__override_proto void pd_check_dr_role(int port, enum pd_data_role dr_role, + int flags); /** * Check for a potential Vconn swap if the port isn't @@ -1783,7 +1755,7 @@ __override_proto void pd_try_execute_vconn_swap(int port, int flags); * @param data_role new data role */ __override_proto void pd_execute_data_swap(int port, - enum pd_data_role data_role); + enum pd_data_role data_role); /** * Get desired dual role state when chipset is suspended. @@ -1832,7 +1804,7 @@ __override_proto int pd_custom_vdm(int port, int cnt, uint32_t *payload, * @return if >0, number of VDOs to send back. */ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload, - uint32_t head, enum tcpci_msg_type *rtype); + uint32_t head, enum tcpci_msg_type *rtype); /** * Handle Custom VDMs for flashing. @@ -1853,8 +1825,8 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload); * @param opos object position of mode to exit. * @return vdm for UFP to be sent to enter mode or zero if not. */ -uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, - uint16_t svid, int opos); +uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid, + int opos); /** * Save the Enter mode command data received from the port partner for setting @@ -1892,7 +1864,7 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status); * @return 1 if UFP should be sent exit mode VDM. */ int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid, - int opos); + int opos); /** * Consume the SVDM attention data @@ -1911,7 +1883,7 @@ void dfp_consume_attention(int port, uint32_t *payload); * @param payload payload data. */ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Consume the SVIDs @@ -1922,7 +1894,7 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, * @param payload payload data. */ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Consume the alternate modes @@ -1933,7 +1905,7 @@ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, * @param payload payload data. */ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload); + uint32_t *payload); /** * Returns true if connected VPD supports Charge Through @@ -2037,7 +2009,7 @@ void pd_set_identity_discovery(int port, enum tcpci_msg_type type, * @return Current discovery state (failed or complete) */ enum pd_discovery_state pd_get_identity_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Set SVID discovery state for this type and port. @@ -2047,7 +2019,7 @@ enum pd_discovery_state pd_get_identity_discovery(int port, * @param disc Discovery state to set (failed or complete) */ void pd_set_svids_discovery(int port, enum tcpci_msg_type type, - enum pd_discovery_state disc); + enum pd_discovery_state disc); /** * Get SVID discovery state for this type and port @@ -2057,7 +2029,7 @@ void pd_set_svids_discovery(int port, enum tcpci_msg_type type, * @return Current discovery state (failed or complete) */ enum pd_discovery_state pd_get_svids_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Set Modes discovery state for this port, SOP* type, and SVID. @@ -2067,8 +2039,8 @@ enum pd_discovery_state pd_get_svids_discovery(int port, * @param svid SVID to set mode discovery state for * @param disc Discovery state to set (failed or complete) */ -void pd_set_modes_discovery(int port, enum tcpci_msg_type type, - uint16_t svid, enum pd_discovery_state disc); +void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid, + enum pd_discovery_state disc); /** * Get Modes discovery state for this port and SOP* type. Modes discover is @@ -2084,7 +2056,7 @@ void pd_set_modes_discovery(int port, enum tcpci_msg_type type, * PD_DISC_FAIL) */ enum pd_discovery_state pd_get_modes_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Returns the mode vdo count of the specified SVID and sets @@ -2098,8 +2070,8 @@ enum pd_discovery_state pd_get_modes_discovery(int port, * @return Mode VDO cnt of specified SVID if is discovered, * 0 otherwise */ -int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid, uint32_t *vdo_out); +int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid, + uint32_t *vdo_out); /** * Get a pointer to mode data for the next SVID that needs to be discovered. @@ -2115,7 +2087,7 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, * NULL, otherwise */ const struct svid_mode_data *pd_get_next_mode(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Return a pointer to the discover identity response structure for this SOP* @@ -2126,7 +2098,7 @@ const struct svid_mode_data *pd_get_next_mode(int port, * @return pointer to response structure, which the caller may not alter */ const union disc_ident_ack *pd_get_identity_response(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /** * Return the VID of the USB PD accessory connected to a specified port @@ -2182,7 +2154,7 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type); * @return Pointer to modes of VDO */ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /* * Looks for a discovered mode VDO for the specified SVID. @@ -2193,7 +2165,7 @@ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, * @return Whether a mode was discovered for the SVID */ bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid); + uint16_t svid); /** * Return the alternate mode entry and exit data @@ -2203,8 +2175,8 @@ bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type, * @param svid SVID * @return pointer to SVDM mode data */ -struct svdm_amode_data *pd_get_amode_data(int port, - enum tcpci_msg_type type, uint16_t svid); +struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type, + uint16_t svid); /* * Returns cable revision @@ -2272,8 +2244,8 @@ bool pd_discovery_access_validate(int port, enum tcpci_msg_type type); * @param type Transmit type (SOP, SOP') for discovered information * @return pointer to PD alternate mode discovery results */ -struct pd_discovery *pd_get_am_discovery_and_notify_access(int port, - enum tcpci_msg_type type); +struct pd_discovery * +pd_get_am_discovery_and_notify_access(int port, enum tcpci_msg_type type); /* * Returns the constant pointer to PD alternate mode discovery results @@ -2284,7 +2256,7 @@ struct pd_discovery *pd_get_am_discovery_and_notify_access(int port, * @return pointer to PD alternate mode discovery results */ const struct pd_discovery *pd_get_am_discovery(int port, - enum tcpci_msg_type type); + enum tcpci_msg_type type); /* * Returns the pointer to PD active alternate modes. @@ -2294,8 +2266,8 @@ const struct pd_discovery *pd_get_am_discovery(int port, * @param type Transmit type (SOP, SOP', SOP'') for active modes * @return Pointer to PD active alternate modes. */ -struct partner_active_modes *pd_get_partner_active_modes(int port, - enum tcpci_msg_type type); +struct partner_active_modes * +pd_get_partner_active_modes(int port, enum tcpci_msg_type type); /* * Sets the current object position for DP alt-mode @@ -2470,8 +2442,7 @@ enum tbt_compat_cable_speed get_tbt_cable_speed(int port); * @param payload payload data * @return Number of object filled */ -int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, - uint32_t *payload); +int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload); /** * Return maximum speed supported by the port to enter into Thunderbolt mode @@ -2506,8 +2477,7 @@ __override_proto enum tbt_compat_cable_speed board_get_max_tbt_speed(int port); * EC_RES_UNAVAILABLE if board does not support this feature */ __override_proto enum ec_status - board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply); +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply); /** * Return true if the board's port supports TBT or USB4 @@ -2614,8 +2584,8 @@ void pd_dpm_request(int port, enum pd_dpm_request req); * must be 1 - 7 inclusive. * @return True if the setup was successful */ -bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, - uint32_t *vdm, uint32_t vdo_cnt); +bool pd_setup_vdm_request(int port, enum tcpci_msg_type tx_type, uint32_t *vdm, + uint32_t vdo_cnt); /* Power Data Objects for the source and the sink */ __override_proto extern const uint32_t pd_src_pdo[]; @@ -2637,7 +2607,9 @@ extern const int pd_snk_pdo_cnt; #if defined(HAS_TASK_HOSTCMD) && !defined(TEST_BUILD) void pd_send_host_event(int mask); #else -static inline void pd_send_host_event(int mask) { } +static inline void pd_send_host_event(int mask) +{ +} #endif /** @@ -2712,7 +2684,6 @@ int pd_write_preamble(int port); */ int pd_write_sym(int port, int bit_off, uint32_t val10); - /** * Ensure that we have an edge after EOP and we end up at level 0, * also fill the last byte. @@ -2973,7 +2944,7 @@ void pd_clear_events(int port, uint32_t clear_mask); * @return EC_RES_SUCCESS if a VDM message is scheduled. */ enum ec_status pd_request_vdm_attention(int port, const uint32_t *data, - int vdo_count); + int vdo_count); /* * Requests that the port enter the specified mode. A successful result just @@ -3088,7 +3059,7 @@ bool pd_waiting_on_partner_src_caps(int port); * * @param port USB-C port number */ -const uint32_t * const pd_get_src_caps(int port); +const uint32_t *const pd_get_src_caps(int port); /** * Returns the number of source caps @@ -3112,7 +3083,7 @@ void pd_set_src_caps(int port, int cnt, uint32_t *src_caps); * * @param port USB-C port number */ -const uint32_t * const pd_get_snk_caps(int port); +const uint32_t *const pd_get_snk_caps(int port); /** * Returns the number of sink caps @@ -3261,8 +3232,8 @@ __override_proto void pd_notify_dp_alt_mode_entry(int port); * Determines the PD state of the port partner according to Table 4-10 in USB PD * specification. */ -enum pd_cc_states pd_get_cc_state( - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2); +enum pd_cc_states pd_get_cc_state(enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2); /* * Optional, get the board-specific SRC DTS polarity. @@ -3285,8 +3256,8 @@ __override_proto uint8_t board_get_src_dts_polarity(int port); * @param data type-defined information * @param payload pointer to the optional payload (0..16 bytes) */ -void pd_log_event(uint8_t type, uint8_t size_port, - uint16_t data, void *payload); +void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, + void *payload); /** * Retrieve one logged event and prepare a VDM with it. @@ -3297,10 +3268,15 @@ void pd_log_event(uint8_t type, uint8_t size_port, * @return number of 32-bit words in the VDM payload. */ int pd_vdm_get_log_entry(uint32_t *payload); -#else /* CONFIG_USB_PD_LOGGING */ -static inline void pd_log_event(uint8_t type, uint8_t size_port, - uint16_t data, void *payload) {} -static inline int pd_vdm_get_log_entry(uint32_t *payload) { return 0; } +#else /* CONFIG_USB_PD_LOGGING */ +static inline void pd_log_event(uint8_t type, uint8_t size_port, uint16_t data, + void *payload) +{ +} +static inline int pd_vdm_get_log_entry(uint32_t *payload) +{ + return 0; +} #endif /* CONFIG_USB_PD_LOGGING */ /** @@ -3557,9 +3533,9 @@ int typec_update_cc(int port); * @param pd_sdb_power_state enum defining the New Power State field of the SDB * @return pd_sdb_power_indicator enum for the SDB */ -__override_proto enum pd_sdb_power_indicator board_get_pd_sdb_power_indicator( -enum pd_sdb_power_state power_state); +__override_proto enum pd_sdb_power_indicator +board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state); /****************************************************************************/ -#endif /* __CROS_EC_USB_PD_H */ +#endif /* __CROS_EC_USB_PD_H */ -- cgit v1.2.1 From 61972b68466324287ee7fca416a48e38bacfe4c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:07 -0600 Subject: chip/mec1322/lpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia802a552139bc4fe7a2d13b556cf04a698902c66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729319 Reviewed-by: Jeremy Bettis --- chip/mec1322/lpc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index be3b36cfef..58dc65461c 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -22,18 +22,18 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) static uint8_t mem_mapped[0x200] __attribute__((section(".bss.big_align"))); static struct host_packet lpc_packet; static struct host_cmd_handler_args host_cmd_args; -static uint8_t host_cmd_flags; /* Flags from host command */ +static uint8_t host_cmd_flags; /* Flags from host command */ static uint8_t params_copy[EC_LPC_HOST_PACKET_SIZE] __aligned(4); static int init_done; -static struct ec_lpc_host_args * const lpc_host_args = +static struct ec_lpc_host_args *const lpc_host_args = (struct ec_lpc_host_args *)mem_mapped; static void keyboard_irq_assert(void) @@ -152,7 +152,7 @@ void lpc_update_host_event_status(void) /* Copy host events to mapped memory */ *(host_event_t *)host_get_memmap(EC_MEMMAP_HOST_EVENTS) = - lpc_get_host_events(); + lpc_get_host_events(); task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); @@ -267,9 +267,9 @@ static void lpc_init(void) MEC1322_LPC_ACT |= 1; /* - * Ring Oscillator not permitted to shut down - * until LPC activate bit is cleared - */ + * Ring Oscillator not permitted to shut down + * until LPC activate bit is cleared + */ MEC1322_LPC_CLK_CTRL |= 3; /* Initialize host args and memory map to all zero */ @@ -375,8 +375,7 @@ DECLARE_IRQ(MEC1322_IRQ_ACPIEC0_IBF, acpi_0_interrupt, 1); void acpi_1_interrupt(void) { uint8_t st = MEC1322_ACPI_EC_STATUS(1); - if (!(st & EC_LPC_STATUS_FROM_HOST) || - !(st & EC_LPC_STATUS_LAST_CMD)) + if (!(st & EC_LPC_STATUS_FROM_HOST) || !(st & EC_LPC_STATUS_LAST_CMD)) return; /* Set the busy bit */ @@ -477,7 +476,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) int lpc_get_pltrst_asserted(void) { - return (MEC1322_LPC_BUS_MONITOR & (1<<1)) ? 1 : 0; + return (MEC1322_LPC_BUS_MONITOR & (1 << 1)) ? 1 : 0; } /* Enable LPC ACPI-EC0 interrupts */ @@ -515,6 +514,5 @@ static enum ec_status lpc_get_protocol_info(struct host_cmd_handler_args *args) return EC_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - lpc_get_protocol_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, + EC_VER_MASK(0)); -- cgit v1.2.1 From d8bb5625bf007f9009102c5910ab0e62323300a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:09 -0600 Subject: board/volmar/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I65c2ab42ce19bbe00b7e9745dfeca8a83f9710eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729079 Reviewed-by: Jeremy Bettis --- board/volmar/sensors.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/volmar/sensors.c b/board/volmar/sensors.c index 720771c360..8b5dbb987c 100644 --- a/board/volmar/sensors.c +++ b/board/volmar/sensors.c @@ -70,8 +70,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -100,8 +100,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -128,8 +128,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -141,12 +141,12 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; .temp_fan_max = C_TO_K(50), \ } __maybe_unused static const struct ec_thermal_config thermal_charger = - THERMAL_CHARGER; + THERMAL_CHARGER; /* this should really be "const" */ struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, [TEMP_SENSOR_2_FAN] = THERMAL_FAN, - [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, + [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From c4e6881c99685c576b17c199ea3ac7962d69418b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:01 -0600 Subject: driver/mcdp28x0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4930e2acef5b6ee615a482e9d4dab0a4ab696a77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730027 Reviewed-by: Jeremy Bettis --- driver/mcdp28x0.c | 50 +++++++++++++++++++++----------------------------- 1 file changed, 21 insertions(+), 29 deletions(-) diff --git a/driver/mcdp28x0.c b/driver/mcdp28x0.c index bf44a6eaf8..4502d00eca 100644 --- a/driver/mcdp28x0.c +++ b/driver/mcdp28x0.c @@ -16,7 +16,7 @@ #include "usart-stm32f0.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) static uint8_t mcdp_inbuf[MCDP_INBUF_MAX]; @@ -35,27 +35,21 @@ static inline void print_buffer(uint8_t *buf, int cnt) CPRINTF("\n"); } #else -static inline void print_buffer(uint8_t *buf, int cnt) {} +static inline void print_buffer(uint8_t *buf, int cnt) +{ +} #endif static struct usart_config const usart_mcdp; -struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT(MCDP_INBUF_MAX, - uint8_t, - usart_mcdp.producer, - null_consumer); -struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT(MCDP_OUTBUF_MAX, - uint8_t, - null_producer, - usart_mcdp.consumer); - -static struct usart_config const usart_mcdp = USART_CONFIG(CONFIG_MCDP28X0, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart_mcdp_rx_queue, - usart_mcdp_tx_queue); +struct queue const usart_mcdp_rx_queue = QUEUE_DIRECT( + MCDP_INBUF_MAX, uint8_t, usart_mcdp.producer, null_consumer); +struct queue const usart_mcdp_tx_queue = QUEUE_DIRECT( + MCDP_OUTBUF_MAX, uint8_t, null_producer, usart_mcdp.consumer); + +static struct usart_config const usart_mcdp = + USART_CONFIG(CONFIG_MCDP28X0, usart_rx_interrupt, usart_tx_interrupt, + 115200, 0, usart_mcdp_rx_queue, usart_mcdp_tx_queue); /** * Compute checksum. @@ -131,7 +125,7 @@ static int rx_serial(uint8_t *msg, int cnt) read = queue_remove_units(&usart_mcdp_rx_queue, msg, cnt); while ((read < cnt) && retry) { - usleep(100*MSEC); + usleep(100 * MSEC); read += queue_remove_units(&usart_mcdp_rx_queue, msg + read, cnt - read); retry--; @@ -143,7 +137,7 @@ static int rx_serial(uint8_t *msg, int cnt) if (cnt > msg[0]) cnt = msg[0]; - if (msg[cnt-1] != compute_checksum(0, msg, cnt-1)) + if (msg[cnt - 1] != compute_checksum(0, msg, cnt - 1)) return MCDP_ERROR_CHKSUM; if (read != cnt) { @@ -176,9 +170,9 @@ void mcdp_disable(void) usart_shutdown(&usart_mcdp); } -int mcdp_get_info(struct mcdp_info *info) +int mcdp_get_info(struct mcdp_info *info) { - const uint8_t msg[2] = {MCDP_CMD_APPSTEST, 0x28}; + const uint8_t msg[2] = { MCDP_CMD_APPSTEST, 0x28 }; int rv = tx_serial(msg, sizeof(msg)); if (rv) @@ -233,8 +227,8 @@ static int mcdp_appstest(uint8_t cmd, int paramc, char **paramv) msg[1] = i + 1; msg[2] = (param >> 24) & 0xff; msg[3] = (param >> 16) & 0xff; - msg[4] = (param >> 8) & 0xff; - msg[5] = (param >> 0) & 0xff; + msg[4] = (param >> 8) & 0xff; + msg[5] = (param >> 0) & 0xff; rv = tx_serial(msg, sizeof(msg)); if (rv) return rv; @@ -277,9 +271,8 @@ int command_mcdp(int argc, char **argv) ccprintf("family:%04x chipid:%04x irom:%d.%d.%d " "fw:%d.%d.%d\n", MCDP_FAMILY(info.family), - MCDP_CHIPID(info.chipid), - info.irom.major, info.irom.minor, - info.irom.build, + MCDP_CHIPID(info.chipid), info.irom.major, + info.irom.minor, info.irom.build, info.fw.major, info.fw.minor, info.fw.build); } else if (!strncasecmp(argv[1], "devid", 4)) { uint8_t dev_id = strtoi(argv[2], &e, 10); @@ -309,6 +302,5 @@ int command_mcdp(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(mcdp, command_mcdp, - "info|devid |appstest []", - "USB PD"); + "info|devid |appstest []", "USB PD"); #endif /* CONFIG_CMD_MCDP */ -- cgit v1.2.1 From 63710ad38955e657c97d1c554be1d5cc0cb2e8c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:32 -0600 Subject: board/wormdingler/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I51014017882c27964d11b89837889a5f952d46b8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729136 Reviewed-by: Jeremy Bettis --- board/wormdingler/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/wormdingler/usbc_config.c b/board/wormdingler/usbc_config.c index aac136415d..73666d087c 100644 --- a/board/wormdingler/usbc_config.c +++ b/board/wormdingler/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From a81d1b9cf2bfb062963ba088b32be3f838297a38 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:02 -0600 Subject: include/vb21_struct.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c35541f9ec090327f0907a20163d2ba5dbf6383 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730452 Reviewed-by: Jeremy Bettis --- include/vb21_struct.h | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/include/vb21_struct.h b/include/vb21_struct.h index 74d0ea3ad2..b1e6bedd7f 100644 --- a/include/vb21_struct.h +++ b/include/vb21_struct.h @@ -28,25 +28,24 @@ */ enum vb21_struct_common_magic { /* "Vb2B" = vb21_keyblock.c.magic */ - VB21_MAGIC_KEYBLOCK = 0x42326256, + VB21_MAGIC_KEYBLOCK = 0x42326256, /* "Vb2F" = vb21_fw_preamble.c.magic */ - VB21_MAGIC_FW_PREAMBLE = 0x46326256, + VB21_MAGIC_FW_PREAMBLE = 0x46326256, /* "Vb2I" = vb21_packed_private_key.c.magic */ - VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256, + VB21_MAGIC_PACKED_PRIVATE_KEY = 0x49326256, /* "Vb2K" = vb2_kernel_preamble.c.magic */ - VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256, + VB21_MAGIC_KERNEL_PREAMBLE = 0x4b326256, /* "Vb2P" = vb21_packed_key.c.magic */ - VB21_MAGIC_PACKED_KEY = 0x50326256, + VB21_MAGIC_PACKED_KEY = 0x50326256, /* "Vb2S" = vb21_signature.c.magic */ - VB21_MAGIC_SIGNATURE = 0x53326256, + VB21_MAGIC_SIGNATURE = 0x53326256, }; - /* * Generic struct header for all vboot2.1 structs. This makes it easy to * automatically parse and identify vboot structs (e.g., in futility). This @@ -145,7 +144,7 @@ struct vb21_packed_key { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_PACKED_KEY_SIZE \ +#define EXPECTED_VB21_PACKED_KEY_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE) /* Current version of vb21_packed_private_key struct */ @@ -184,7 +183,7 @@ struct vb21_packed_private_key { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \ +#define EXPECTED_VB21_PACKED_PRIVATE_KEY_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 12 + EXPECTED_ID_SIZE) /* Current version of vb21_signature struct */ @@ -232,10 +231,9 @@ struct vb21_signature { struct vb2_id id; } __attribute__((packed)); -#define EXPECTED_VB21_SIGNATURE_SIZE \ +#define EXPECTED_VB21_SIGNATURE_SIZE \ (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16 + EXPECTED_ID_SIZE) - /* Current version of vb21_keyblock struct */ #define VB21_KEYBLOCK_VERSION_MAJOR 3 #define VB21_KEYBLOCK_VERSION_MINOR 0 @@ -290,7 +288,6 @@ struct vb21_keyblock { #define EXPECTED_VB21_KEYBLOCK_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 16) - /* Current version of vb21_fw_preamble struct */ #define VB21_FW_PREAMBLE_VERSION_MAJOR 3 #define VB21_FW_PREAMBLE_VERSION_MINOR 0 @@ -343,4 +340,4 @@ struct vb21_fw_preamble { #define EXPECTED_VB21_FW_PREAMBLE_SIZE (EXPECTED_VB21_STRUCT_COMMON_SIZE + 20) -#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */ +#endif /* VBOOT_REFERENCE_VB21_STRUCT_H_ */ -- cgit v1.2.1 From 04358f0052ffdfac9e9c38f380ec2fc679080fcb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:27 -0600 Subject: cts/mutex/dut.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1257af36ec4b96f99c60ddd58f079d929a02ecb0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729743 Reviewed-by: Jeremy Bettis --- cts/mutex/dut.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cts/mutex/dut.c b/cts/mutex/dut.c index 9cbbd8badb..3e9a8ca7c2 100644 --- a/cts/mutex/dut.c +++ b/cts/mutex/dut.c @@ -23,7 +23,7 @@ static struct mutex mtx; int mutex_random_task(void *unused) { - char letter = 'A'+(TASK_ID_MTX3A - task_get_current()); + char letter = 'A' + (TASK_ID_MTX3A - task_get_current()); /* wait to be activated */ while (1) { -- cgit v1.2.1 From b97c95a8a8398f4756698954ae46c07b630ece42 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:59 -0600 Subject: include/mock/usb_prl_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f3edbbbfeaa9b4a4724f15ae4ebacf7eb79423c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730365 Reviewed-by: Jeremy Bettis --- include/mock/usb_prl_mock.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/mock/usb_prl_mock.h b/include/mock/usb_prl_mock.h index ee37d6e6e2..40cd95543f 100644 --- a/include/mock/usb_prl_mock.h +++ b/include/mock/usb_prl_mock.h @@ -13,17 +13,14 @@ void mock_prl_reset(void); -int mock_prl_wait_for_tx_msg(int port, - enum tcpci_msg_type tx_type, +int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout); + enum pd_data_msg_type data_msg, int timeout); enum pd_ctrl_msg_type mock_prl_get_last_sent_ctrl_msg(int port); enum pd_data_msg_type mock_prl_get_last_sent_data_msg(int port); - void mock_prl_clear_last_sent_msg(int port); void mock_prl_message_sent(int port); -- cgit v1.2.1 From 79eb0a6ac239260cd783ac95cca252b451bc52b9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:14 -0600 Subject: board/madoo/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf82d2658ec713068a4fdb28930e28250a561ae7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728641 Reviewed-by: Jeremy Bettis --- board/madoo/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/madoo/usb_pd_policy.c b/board/madoo/usb_pd_policy.c index 02bb449f60..f2e62044b5 100644 --- a/board/madoo/usb_pd_policy.c +++ b/board/madoo/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 17ff9c09cec37f694f96dded327567a28d0bb2ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:26 -0600 Subject: board/plankton/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9bfabb5c9f494548c40b6bd142fb9180169eb140 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728832 Reviewed-by: Jeremy Bettis --- board/plankton/board.c | 96 +++++++++++++++++++++----------------------------- 1 file changed, 41 insertions(+), 55 deletions(-) diff --git a/board/plankton/board.c b/board/plankton/board.c index 5a62f63c86..165e7dfb80 100644 --- a/board/plankton/board.c +++ b/board/plankton/board.c @@ -78,14 +78,12 @@ void hpd_lvl_deferred(void) /* Configure redriver's back side */ if (level) sn75dp130_dpcd_init(); - } /* Send queued IRQ if the cable is attached */ if (hpd_possible_irq && level && dp_mode) pd_send_hpd(0, hpd_irq); hpd_possible_irq = 0; - } DECLARE_DEFERRED(hpd_lvl_deferred); @@ -103,8 +101,7 @@ void hpd_event(enum gpio_signal signal) hpd_prev_ts = now.val; /* All previous hpd level events need to be re-triggered */ - hook_call_deferred(&hpd_lvl_deferred_data, - HPD_USTREAM_DEBOUNCE_LVL); + hook_call_deferred(&hpd_lvl_deferred_data, HPD_USTREAM_DEBOUNCE_LVL); } /* Debounce time for voltage buttons */ @@ -134,8 +131,7 @@ enum usbc_action { USBC_ACT_COUNT }; -enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] = -{ +enum board_src_cap src_cap_mapping[USBC_ACT_COUNT] = { [USBC_ACT_5V_TO_DUT] = SRC_CAP_5V, [USBC_ACT_12V_TO_DUT] = SRC_CAP_12V, [USBC_ACT_20V_TO_DUT] = SRC_CAP_20V, @@ -155,21 +151,21 @@ static void set_active_cc(int cc) * disabled then only set the active CC line. */ /* Pull-up on CC2 */ - gpio_set_flags(GPIO_USBC_CC2_HOST, - ((cc || drp_enable) && host_mode) ? - GPIO_OUT_HIGH : GPIO_INPUT); + gpio_set_flags(GPIO_USBC_CC2_HOST, ((cc || drp_enable) && host_mode) ? + GPIO_OUT_HIGH : + GPIO_INPUT); /* Pull-down on CC2 */ gpio_set_flags(GPIO_USBC_CC2_DEVICE_ODL, - ((cc || drp_enable) && !host_mode) ? - GPIO_OUT_LOW : GPIO_INPUT); + ((cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW : + GPIO_INPUT); /* Pull-up on CC1 */ - gpio_set_flags(GPIO_USBC_CC1_HOST, - ((!cc || drp_enable) && host_mode) ? - GPIO_OUT_HIGH : GPIO_INPUT); + gpio_set_flags(GPIO_USBC_CC1_HOST, ((!cc || drp_enable) && host_mode) ? + GPIO_OUT_HIGH : + GPIO_INPUT); /* Pull-down on CC1 */ gpio_set_flags(GPIO_USBC_CC1_DEVICE_ODL, - ((!cc || drp_enable) && !host_mode) ? - GPIO_OUT_LOW : GPIO_INPUT); + ((!cc || drp_enable) && !host_mode) ? GPIO_OUT_LOW : + GPIO_INPUT); } /** @@ -221,7 +217,7 @@ static void fake_disconnect_end(void) board_pd_set_host_mode(fake_pd_host_mode); /* Restart CC cable detection */ - hook_call_deferred(&detect_cc_cable_data, 500*MSEC); + hook_call_deferred(&detect_cc_cable_data, 500 * MSEC); } DECLARE_DEFERRED(fake_disconnect_end); @@ -361,10 +357,10 @@ static void set_usbc_action(enum usbc_action act) gpio_set_level(GPIO_CASE_CLOSE_EN, 1); gpio_set_level(GPIO_CASE_CLOSE_DFU_L, 1); break; - case USBC_ACT_DRP_TOGGLE: + case USBC_ACT_DRP_TOGGLE: /* Toggle dualrole mode setting. */ - update_usbc_dual_role(drp_enable ? - PD_DRP_TOGGLE_OFF : PD_DRP_TOGGLE_ON); + update_usbc_dual_role(drp_enable ? PD_DRP_TOGGLE_OFF : + PD_DRP_TOGGLE_ON); break; default: break; @@ -424,8 +420,8 @@ static void button_deferred(void) break; } - ccprintf("Button %d = %d\n", - button_pressed, gpio_get_level(button_pressed)); + ccprintf("Button %d = %d\n", button_pressed, + gpio_get_level(button_pressed)); } DECLARE_DEFERRED(button_deferred); @@ -453,20 +449,18 @@ void vbus_event(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, - [ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, + [ADC_CH_CC1_PD] = { "CC1_PD", 3300, 4096, 0, STM32_AIN(0) }, + [ADC_CH_CC2_PD] = { "CC2_PD", 3300, 4096, 0, STM32_AIN(4) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -476,12 +470,12 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); * Pin number for active-high reset from PCA9534 to CMOS pull-down to * SN75DP130's RSTN (active-low) */ -#define REDRIVER_RST_PIN 0x1 +#define REDRIVER_RST_PIN 0x1 static int sn75dp130_i2c_write(uint8_t index, uint8_t value) { - return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS, - index, value); + return i2c_write8(I2C_PORT_MASTER, SN75DP130_I2C_ADDR_FLAGS, index, + value); } /** @@ -494,17 +488,15 @@ static int sn75dp130_reset(void) { int rv; - rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20, - REDRIVER_RST_PIN, PCA9534_OUTPUT); + rv = pca9534_config_pin(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, + PCA9534_OUTPUT); /* Assert (its active high) */ - rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, - REDRIVER_RST_PIN, 1); + rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 1); /* datasheet recommends > 100usec */ usleep(200); /* De-assert */ - rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, - REDRIVER_RST_PIN, 0); + rv |= pca9534_set_level(I2C_PORT_MASTER, 0x20, REDRIVER_RST_PIN, 0); /* datasheet recommends > 400msec */ usleep(450 * MSEC); return rv; @@ -600,12 +592,10 @@ int board_in_hub_mode(void) int ret; int level; - ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, - 6, PCA9534_INPUT); + ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 6, PCA9534_INPUT); if (ret) return -1; - ret = pca9534_get_level(I2C_PORT_MASTER, 0x20, - 6, &level); + ret = pca9534_get_level(I2C_PORT_MASTER, 0x20, 6, &level); if (ret) return -1; return level; @@ -615,17 +605,14 @@ static int board_usb_hub_reset(void) { int ret; - ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, - 7, PCA9534_OUTPUT); + ret = pca9534_config_pin(I2C_PORT_MASTER, 0x20, 7, PCA9534_OUTPUT); if (ret) return ret; - ret = pca9534_set_level(I2C_PORT_MASTER, 0x20, - 7, 0); + ret = pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 0); if (ret) return ret; usleep(100 * MSEC); - return pca9534_set_level(I2C_PORT_MASTER, 0x20, - 7, 1); + return pca9534_set_level(I2C_PORT_MASTER, 0x20, 7, 1); } void board_maybe_reset_usb_hub(void) @@ -638,8 +625,7 @@ static int cmd_usb_hub_reset(int argc, char *argv[]) { return board_usb_hub_reset(); } -DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset, - NULL, "Reset USB hub"); +DECLARE_CONSOLE_COMMAND(hub_reset, cmd_usb_hub_reset, NULL, "Reset USB hub"); static void board_usb_hub_reset_no_return(void) { @@ -668,7 +654,7 @@ int board_fake_pd_adc_read(int cc) * on other CC line. */ if (active_cc == cc) return adc_read_channel(cc ? ADC_CH_CC2_PD : - ADC_CH_CC1_PD); + ADC_CH_CC1_PD); else return host_mode ? 3000 : 0; } @@ -776,8 +762,8 @@ static int cmd_fake_disconnect(int argc, char *argv[]) fake_pd_disconnect_duration_us = duration_ms * MSEC; hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC); - ccprintf("Fake disconnect for %d ms starting in %d ms.\n", - duration_ms, delay_ms); + ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms, + delay_ms); return EC_SUCCESS; } -- cgit v1.2.1 From d0fa5ece23954391ccdd2fa16b0d4590182d46ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:08 -0600 Subject: include/driver/accelgyro_lsm6dso_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib3119c7b9bd3c961919bc772fdbd855ad27b8d8e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730270 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_lsm6dso_public.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/driver/accelgyro_lsm6dso_public.h b/include/driver/accelgyro_lsm6dso_public.h index 65e98bccec..6b5f54e74b 100644 --- a/include/driver/accelgyro_lsm6dso_public.h +++ b/include/driver/accelgyro_lsm6dso_public.h @@ -14,12 +14,11 @@ * 7-bit address is 110101xb. Where 'x' is determined * by the voltage on the ADDR pin */ -#define LSM6DSO_ADDR0_FLAGS 0x6a -#define LSM6DSO_ADDR1_FLAGS 0x6b +#define LSM6DSO_ADDR0_FLAGS 0x6a +#define LSM6DSO_ADDR1_FLAGS 0x6b /* Absolute maximum rate for Acc and Gyro sensors */ -#define LSM6DSO_ODR_MIN_VAL 13000 -#define LSM6DSO_ODR_MAX_VAL \ - MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) +#define LSM6DSO_ODR_MIN_VAL 13000 +#define LSM6DSO_ODR_MAX_VAL MOTION_MAX_SENSOR_FREQUENCY(416000, 13000) #endif /* __CROS_EC_ACCELGYRO_LSM6DSO_PUBLIC_H */ -- cgit v1.2.1 From 6b72a56c7f3bc1453ce39c0989318caf926965bb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:33 -0600 Subject: chip/mchp/gpspi_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2c836ae2a2ff2b97ff61914a9a1bae72dffbaab1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729294 Reviewed-by: Jeremy Bettis --- chip/mchp/gpspi_chip.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/mchp/gpspi_chip.h b/chip/mchp/gpspi_chip.h index b48aec0976..a231bac806 100644 --- a/chip/mchp/gpspi_chip.h +++ b/chip/mchp/gpspi_chip.h @@ -24,8 +24,8 @@ int gpspi_transaction_flush(const struct spi_device_t *spi_device); int gpspi_transaction_wait(const struct spi_device_t *spi_device); int gpspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen); + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen); int gpspi_enable(int port, int enable); -- cgit v1.2.1 From 413011c28fda61f8479ab7b5d1d25332e94d43f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:59 -0600 Subject: board/zinger/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2aa7a97d606ba19fd9f960ce4b64aab00837354b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729122 Reviewed-by: Jeremy Bettis --- board/zinger/usb_pd_config.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h index d0797b3d80..2bbc720108 100644 --- a/board/zinger/usb_pd_config.h +++ b/board/zinger/usb_pd_config.h @@ -10,7 +10,7 @@ /* Timer selection for baseband PD communication */ #define TIM_CLOCK_PD_TX_C0 14 -#define TIM_CLOCK_PD_RX_C0 3 +#define TIM_CLOCK_PD_RX_C0 3 #define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 #define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 @@ -46,7 +46,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 /* connect TIM3 CH1 to TIM3_CH2 input */ -#define TIM_CCR_CS 2 +#define TIM_CCR_CS 2 #define EXTI_COMP_MASK(p) BIT(7) #define IRQ_COMP STM32_IRQ_EXTI4_15 /* the RX is inverted, triggers on rising edge */ @@ -72,7 +72,7 @@ static inline void pd_tx_spi_reset(int port) static inline void pd_tx_enable(int port, int polarity) { /* Drive SPI MISO on PA6 by putting it in AF mode */ - STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2*6); + STM32_GPIO_MODER(GPIO_A) |= 0x2 << (2 * 6); /* Drive TX GND on PA4 */ STM32_GPIO_BSRR(GPIO_A) = 1 << (4 + 16 /* Reset */); } @@ -83,7 +83,7 @@ static inline void pd_tx_disable(int port, int polarity) /* Put TX GND (PA4) in Hi-Z state */ STM32_GPIO_BSRR(GPIO_A) = BIT(4) /* Set */; /* Put SPI MISO (PA6) in Hi-Z by putting it in input mode */ - STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6)); + STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2 * 6)); } /* we know the plug polarity, do the right configuration */ @@ -98,7 +98,9 @@ static inline void pd_tx_init(void) /* Already done in hardware_init() */ } -static inline void pd_config_init(int port, uint8_t power_role) {} +static inline void pd_config_init(int port, uint8_t power_role) +{ +} static inline int pd_adc_read(int port, int cc) { -- cgit v1.2.1 From d0cd0bd6bd26a86c2eebea12f678a6044d18c558 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:18 -0600 Subject: board/vilboz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I72c6679803d33e5830da36e808790f65e964ea92 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729058 Reviewed-by: Jeremy Bettis --- board/vilboz/board.h | 75 ++++++++++++++++++++-------------------------------- 1 file changed, 28 insertions(+), 47 deletions(-) diff --git a/board/vilboz/board.h b/board/vilboz/board.h index 91a7d6e868..3fb52d008b 100644 --- a/board/vilboz/board.h +++ b/board/vilboz/board.h @@ -42,39 +42,35 @@ #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 4 /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ /* This I2C moved. Temporarily detect and support the V0 HW. */ extern int I2C_PORT_BATTERY; -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_SMP, @@ -91,19 +87,11 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; -enum ioex_port { - IOEX_C0_NCT3807 = 0, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_PORT_COUNT }; -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB3_C0_DP2_HPD \ - : GPIO_DP1_HPD) +#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD) enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -112,16 +100,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration -- cgit v1.2.1 From d2fa05782918ce24260a335c184cc9883bb8e6eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:04 -0600 Subject: chip/stm32/power_led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27fbcd4fa62353687920df5b9e5af47153b33bd2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729406 Reviewed-by: Jeremy Bettis --- chip/stm32/power_led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c index 508745199f..ab5f2dcd34 100644 --- a/chip/stm32/power_led.c +++ b/chip/stm32/power_led.c @@ -28,9 +28,9 @@ #include "timer.h" #include "util.h" -#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ -#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ -#define LED_STEP_PERCENT 4 /* Incremental value of each step */ +#define LED_STATE_TIMEOUT_MIN (15 * MSEC) /* Minimum of 15ms per step */ +#define LED_HOLD_TIME (330 * MSEC) /* Hold for 330ms at min/max */ +#define LED_STEP_PERCENT 4 /* Incremental value of each step */ static enum powerled_state led_state = POWERLED_STATE_ON; static int power_led_percent = 100; @@ -86,7 +86,8 @@ static int power_led_step(void) * Decreases timeout as duty cycle percentage approaches * 0%, increase as it approaches 100%. */ - state_timeout = LED_STATE_TIMEOUT_MIN + + state_timeout = + LED_STATE_TIMEOUT_MIN + LED_STATE_TIMEOUT_MIN * (power_led_percent / 33); } @@ -156,7 +157,6 @@ static int command_powerled(int argc, char **argv) powerled_set_state(state); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(powerled, command_powerled, - "[off | on | suspend]", - "Change power LED state"); +DECLARE_CONSOLE_COMMAND(powerled, command_powerled, "[off | on | suspend]", + "Change power LED state"); #endif -- cgit v1.2.1 From 3beb81da4d8e08221bb8910ebdf94c67a75b1e2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:07 -0600 Subject: driver/stm_mems_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3070653d6edb3f3a5f537ef1f2e4df167421abf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730071 Reviewed-by: Jeremy Bettis --- driver/stm_mems_common.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/driver/stm_mems_common.c b/driver/stm_mems_common.c index d3088521d9..61de0dd92a 100644 --- a/driver/stm_mems_common.c +++ b/driver/stm_mems_common.c @@ -11,28 +11,24 @@ /** * st_raw_read_n - Read n bytes for read */ -int st_raw_read_n(const int port, - const uint16_t i2c_addr_flags, +int st_raw_read_n(const int port, const uint16_t i2c_addr_flags, const uint8_t reg, uint8_t *data_ptr, const int len) { /* TODO: Implement SPI interface support */ - return i2c_read_block(port, i2c_addr_flags, - reg | 0x80, data_ptr, len); + return i2c_read_block(port, i2c_addr_flags, reg | 0x80, data_ptr, len); } /** * st_raw_read_n_noinc - Read n bytes for read (no auto inc address) */ -int st_raw_read_n_noinc(const int port, - const uint16_t i2c_addr_flags, +int st_raw_read_n_noinc(const int port, const uint16_t i2c_addr_flags, const uint8_t reg, uint8_t *data_ptr, const int len) { /* TODO: Implement SPI interface support */ - return i2c_read_block(port, i2c_addr_flags, - reg, data_ptr, len); + return i2c_read_block(port, i2c_addr_flags, reg, data_ptr, len); } - /** +/** * st_write_data_with_mask - Write register with mask * @s: Motion sensor pointer * @reg: Device register @@ -40,24 +36,22 @@ int st_raw_read_n_noinc(const int port, * @data: Data pointer */ int st_write_data_with_mask(const struct motion_sensor_t *s, int reg, - uint8_t mask, uint8_t data) + uint8_t mask, uint8_t data) { int err; int new_data = 0x00, old_data = 0x00; - err = st_raw_read8(s->port, s->i2c_spi_addr_flags, - reg, &old_data); + err = st_raw_read8(s->port, s->i2c_spi_addr_flags, reg, &old_data); if (err != EC_SUCCESS) return err; - new_data = ((old_data & (~mask)) | - ((data << __builtin_ctz(mask)) & mask)); + new_data = + ((old_data & (~mask)) | ((data << __builtin_ctz(mask)) & mask)); if (new_data == old_data) return EC_SUCCESS; - return st_raw_write8(s->port, s->i2c_spi_addr_flags, - reg, new_data); + return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, new_data); } /** @@ -77,8 +71,8 @@ int st_get_resolution(const struct motion_sensor_t *s) * @offset: offset vector * @temp: Temp */ -int st_set_offset(const struct motion_sensor_t *s, - const int16_t *offset, int16_t temp) +int st_set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { struct stprivate_data *data = s->drv_data; @@ -94,8 +88,8 @@ int st_set_offset(const struct motion_sensor_t *s, * @offset: offset vector * @temp: Temp */ -int st_get_offset(const struct motion_sensor_t *s, - int16_t *offset, int16_t *temp) +int st_get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct stprivate_data *data = s->drv_data; -- cgit v1.2.1 From 1d7e24ba4a710f9f6f9feba6babde122690be71a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:35 -0600 Subject: zephyr/shim/src/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0e3afae8c633fd3f5e410015570c1a44e818c4d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727426 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/panic.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/src/panic.c b/zephyr/shim/src/panic.c index 0685f52ede..8b73d03400 100644 --- a/zephyr/shim/src/panic.c +++ b/zephyr/shim/src/panic.c @@ -48,13 +48,13 @@ */ #define PANIC_ARCH PANIC_ARCH_RISCV_RV32I #define PANIC_REG_LIST(M) \ - M(ra, riscv.regs[29], ra) \ - M(a0, riscv.regs[26], a0) \ - M(a1, riscv.regs[25], a1) \ - M(a2, riscv.regs[24], a2) \ - M(a3, riscv.regs[23], a3) \ - M(a4, riscv.regs[22], a4) \ - M(a5, riscv.regs[21], a5) \ + M(ra, riscv.regs[29], ra) \ + M(a0, riscv.regs[26], a0) \ + M(a1, riscv.regs[25], a1) \ + M(a2, riscv.regs[24], a2) \ + M(a3, riscv.regs[23], a3) \ + M(a4, riscv.regs[22], a4) \ + M(a5, riscv.regs[21], a5) \ M(a6, riscv.regs[20], a6) \ M(a7, riscv.regs[19], a7) \ M(t0, riscv.regs[18], t0) \ @@ -99,8 +99,9 @@ static void copy_esf_to_panic_data(const z_arch_esf_t *esf, { pdata->arch = PANIC_ARCH; pdata->struct_version = 2; - pdata->flags = (PANIC_ARCH == PANIC_ARCH_CORTEX_M) - ? PANIC_DATA_FLAG_FRAME_VALID : 0; + pdata->flags = (PANIC_ARCH == PANIC_ARCH_CORTEX_M) ? + PANIC_DATA_FLAG_FRAME_VALID : + 0; pdata->reserved = 0; pdata->struct_size = sizeof(*pdata); pdata->magic = PANIC_DATA_MAGIC; @@ -137,7 +138,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *esf) #ifdef CONFIG_PLATFORM_EC_SOFTWARE_PANIC void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); /* Setup panic data structure */ memset(pdata, 0, CONFIG_PANIC_DATA_SIZE); @@ -157,7 +158,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); if (pdata && pdata->struct_version == 2) { *exception = PANIC_REG_EXCEPTION(pdata); -- cgit v1.2.1 From dab1dbe355fab1918c618d4a6a9111e1a0a443bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:55 -0600 Subject: chip/mec1322/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieac393c703fb142ab58ae7eeb217d5a4e358cf09 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729328 Reviewed-by: Jeremy Bettis --- chip/mec1322/gpio.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index 6435f4fe9d..ea68549ad1 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -21,16 +21,14 @@ struct gpio_int_mapping { /* Mapping from GPIO port to GIRQ info */ static const struct gpio_int_mapping int_map[22] = { - {11, 0}, {11, 0}, {11, 0}, {11, 0}, - {10, 4}, {10, 4}, {10, 4}, {-1, -1}, - {-1, -1}, {-1, -1}, {9, 10}, {9, 10}, - {9, 10}, {9, 10}, {8, 14}, {8, 14}, - {8, 14}, {-1, -1}, {-1, -1}, {-1, -1}, - {20, 20}, {20, 20} + { 11, 0 }, { 11, 0 }, { 11, 0 }, { 11, 0 }, { 10, 4 }, { 10, 4 }, + { 10, 4 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { 9, 10 }, { 9, 10 }, + { 9, 10 }, { 9, 10 }, { 8, 14 }, { 8, 14 }, { 8, 14 }, { -1, -1 }, + { -1, -1 }, { -1, -1 }, { 20, 20 }, { 20, 20 } }; void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { int i; uint32_t val; @@ -199,7 +197,6 @@ void gpio_pre_init(void) int is_warm = system_is_reboot_warm(); const struct gpio_info *g = gpio_list; - for (i = 0; i < GPIO_COUNT; i++, g++) { flags = g->flags; @@ -217,15 +214,15 @@ void gpio_pre_init(void) /* Use as GPIO, not alternate function */ gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); + GPIO_ALT_FUNC_NONE); } } /* Clear any interrupt flags before enabling GPIO interrupt */ -#define ENABLE_GPIO_GIRQ(x) \ - do { \ +#define ENABLE_GPIO_GIRQ(x) \ + do { \ MEC1322_INT_SOURCE(x) |= MEC1322_INT_RESULT(x); \ - task_enable_irq(MEC1322_IRQ_GIRQ ## x); \ + task_enable_irq(MEC1322_IRQ_GIRQ##x); \ } while (0) static void gpio_init(void) @@ -241,7 +238,6 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); /*****************************************************************************/ /* Interrupt handlers */ - /** * Handler for each GIRQ interrupt. This reads and clears the interrupt bits for * the GIRQ interrupt, then finds and calls the corresponding GPIO interrupt -- cgit v1.2.1 From cd74707ba872abae2fcbea741d7586ff5971a797 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:23 -0600 Subject: driver/als_isl29035.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9cb14ee48534130d5f36850983e6230af85837d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729925 Reviewed-by: Jeremy Bettis --- driver/als_isl29035.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/als_isl29035.c b/driver/als_isl29035.c index db77a19f09..be35389602 100644 --- a/driver/als_isl29035.c +++ b/driver/als_isl29035.c @@ -9,16 +9,16 @@ #include "i2c.h" /* I2C interface */ -#define ILS29035_I2C_ADDR_FLAGS 0x44 -#define ILS29035_REG_COMMAND_I 0 +#define ILS29035_I2C_ADDR_FLAGS 0x44 +#define ILS29035_REG_COMMAND_I 0 #define ILS29035_REG_COMMAND_II 1 -#define ILS29035_REG_DATA_LSB 2 -#define ILS29035_REG_DATA_MSB 3 +#define ILS29035_REG_DATA_LSB 2 +#define ILS29035_REG_DATA_MSB 3 #define ILS29035_REG_INT_LT_LSB 4 #define ILS29035_REG_INT_LT_MSB 5 #define ILS29035_REG_INT_HT_LSB 6 #define ILS29035_REG_INT_HT_MSB 7 -#define ILS29035_REG_ID 15 +#define ILS29035_REG_ID 15 int isl29035_init(void) { -- cgit v1.2.1 From dc165d8f185f78399499bcd6554a7ac33f68e541 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:49 -0600 Subject: board/taniks/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4641cb619a915b0b4a2121ed8fc14caa10841311 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728965 Reviewed-by: Jeremy Bettis --- board/taniks/charger.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/taniks/charger.c diff --git a/board/taniks/charger.c b/board/taniks/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/taniks/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/taniks/charger.c b/board/taniks/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/taniks/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From 51bf98eb981160757fb1b01a0192539983c82b51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:39 -0600 Subject: board/mithrax/keyboard_customization.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I643a678c6ac7ea0f8a91dd83e6eeb065101586c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728462 Reviewed-by: Jeremy Bettis --- board/mithrax/keyboard_customization.c | 87 +++++++++++++++------------------- 1 file changed, 39 insertions(+), 48 deletions(-) diff --git a/board/mithrax/keyboard_customization.c b/board/mithrax/keyboard_customization.c index 4e45de34be..b6830f17a3 100644 --- a/board/mithrax/keyboard_customization.c +++ b/board/mithrax/keyboard_customization.c @@ -12,24 +12,23 @@ #include "keyboard_raw.h" static uint16_t scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000}, - {0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016}, - {0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a}, - {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d}, - {0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d}, - {0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043}, - {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c}, - {0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059}, - {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d}, - {0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a}, - {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, - {0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066}, - {0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d}, - {0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021}, - {0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069}, + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 }, + { 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 }, + { 0x006c, 0xe024, 0xe01d, 0xe020, 0xe038, 0xe071, 0x0026, 0x002a }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d }, + { 0x0078, 0xe032, 0xe035, 0xe02c, 0xe02d, 0x0041, 0x001e, 0x001d }, + { 0x0051, 0x0007, 0x005b, 0x000f, 0x0042, 0x0022, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c }, + { 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d }, + { 0x0045, 0xe021, 0xe023, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, + { 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 }, + { 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d }, + { 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 }, + { 0x0023, 0xe05a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007d, 0x0069 }, }; - uint16_t get_scancode_set2(uint8_t row, uint8_t col) { if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) @@ -64,38 +63,30 @@ void board_keyboard_drive_col(int col) #ifdef CONFIG_KEYBOARD_DEBUG static char keycap_label[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', - '1', KLLI_UNKNO, 'a'}, - {KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, - KLLI_SEARC, '3', KLLI_F3, KLLI_UNKNO}, - {'x', 'z', KLLI_F2, KLLI_F1, - 's', '2', 'w', KLLI_ESC}, - {'v', 'b', 'g', 't', - '5', '4', 'r', 'f'}, - {'m', 'n', 'h', 'y', - '6', '7', 'u', 'j'}, - {'.', KLLI_DOWN, '\\', 'o', - KLLI_F10, '9', KLLI_UNKNO, 'l'}, - {KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {',', KLLI_UNKNO, KLLI_F7, KLLI_F6, - KLLI_F5, '8', 'i', 'k'}, - {KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, - KLLI_UNKNO, KLLI_UNKNO, KLLI_LEFT, KLLI_UNKNO}, - {KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, - {'/', KLLI_UP, '-', KLLI_UNKNO, - '0', 'p', '[', ';'}, - {'\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, - '=', KLLI_B_SPC, ']', 'd'}, - {KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, - KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO}, + { 'c', KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { 'q', KLLI_UNKNO, KLLI_UNKNO, KLLI_TAB, '`', '1', KLLI_UNKNO, 'a' }, + { KLLI_R_ALT, KLLI_L_ALT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { KLLI_UNKNO, KLLI_SPACE, 'e', KLLI_F4, KLLI_SEARC, '3', KLLI_F3, + KLLI_UNKNO }, + { 'x', 'z', KLLI_F2, KLLI_F1, 's', '2', 'w', KLLI_ESC }, + { 'v', 'b', 'g', 't', '5', '4', 'r', 'f' }, + { 'm', 'n', 'h', 'y', '6', '7', 'u', 'j' }, + { '.', KLLI_DOWN, '\\', 'o', KLLI_F10, '9', KLLI_UNKNO, 'l' }, + { KLLI_R_SHT, KLLI_L_SHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { ',', KLLI_UNKNO, KLLI_F7, KLLI_F6, KLLI_F5, '8', 'i', 'k' }, + { KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, KLLI_F9, KLLI_UNKNO, KLLI_UNKNO, + KLLI_LEFT, KLLI_UNKNO }, + { KLLI_R_CTR, KLLI_L_CTR, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO }, + { '/', KLLI_UP, '-', KLLI_UNKNO, '0', 'p', '[', ';' }, + { '\'', KLLI_ENTER, KLLI_UNKNO, KLLI_UNKNO, '=', KLLI_B_SPC, ']', 'd' }, + { KLLI_UNKNO, KLLI_F8, KLLI_RIGHT, KLLI_UNKNO, KLLI_UNKNO, KLLI_UNKNO, + KLLI_UNKNO, KLLI_UNKNO }, }; char get_keycap_label(uint8_t row, uint8_t col) -- cgit v1.2.1 From f25c69169f060607cb29e93474da0b0512781569 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:37 -0600 Subject: chip/stm32/config-stm32f4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2056ce6f07c39be61b739eed33369c717b1682a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729474 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f4.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/chip/stm32/config-stm32f4.h b/chip/stm32/config-stm32f4.h index ee1d594116..fbb53717a9 100644 --- a/chip/stm32/config-stm32f4.h +++ b/chip/stm32/config-stm32f4.h @@ -5,9 +5,9 @@ /* Memory mapping */ #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (1 * 1024 * 1024) #else -# define CONFIG_FLASH_SIZE_BYTES (512 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #endif /* 3 regions type: 16K, 64K and 128K */ @@ -31,33 +31,32 @@ #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE #ifdef CHIP_VARIANT_STM32F412 -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00040000 /* 256 KB */ #else -# define CONFIG_RAM_BASE 0x20000000 -# define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00020000 /* 128 KB */ #endif -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (256 * 1024) -#define CONFIG_RW_MEM_OFF (256 * 1024) -#define CONFIG_RW_SIZE (256 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (256 * 1024) +#define CONFIG_RW_MEM_OFF (256 * 1024) +#define CONFIG_RW_SIZE (256 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) - -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Use PSTATE embedded in the RO image, not in its own erase block */ #define CONFIG_FLASH_PSTATE @@ -67,12 +66,12 @@ #define CONFIG_OTP /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 97 +#define CONFIG_IRQ_COUNT 97 #undef CONFIG_CMD_CHARGEN /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 /* * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm -- cgit v1.2.1 From aa651f32559fef0d414cad41a1f7abe313863d31 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:02 -0600 Subject: driver/accelgyro_lsm6dso.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I016da5fc9bc530832a7d33ecdfebc1b6874a049a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729897 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6dso.c | 48 +++++++++++++++++++++------------------------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/driver/accelgyro_lsm6dso.c b/driver/accelgyro_lsm6dso.c index 74731fad27..609583723b 100644 --- a/driver/accelgyro_lsm6dso.c +++ b/driver/accelgyro_lsm6dso.c @@ -23,10 +23,10 @@ #define ACCEL_LSM6DSO_INT_ENABLE #endif -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCEL_LSM6DSO_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; /* * When ODR change, the sensor filters need settling time; @@ -75,7 +75,7 @@ static int config_interrupt(const struct motion_sensor_t *s) return ret; int1_ctrl_val |= LSM6DSO_INT_FIFO_TH | LSM6DSO_INT_FIFO_OVR | - LSM6DSO_INT_FIFO_FULL; + LSM6DSO_INT_FIFO_FULL; ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSO_INT1_CTRL, int1_ctrl_val); @@ -171,10 +171,9 @@ static inline int load_fifo(struct motion_sensor_t *main_s, int i; for (i = 0; i < fifo_len; i++) { - RETURN_ERROR(st_raw_read_n_noinc(main_s->port, - main_s->i2c_spi_addr_flags, - LSM6DSO_FIFO_DATA_ADDR_TAG, - fifo, sizeof(fifo))); + RETURN_ERROR(st_raw_read_n_noinc( + main_s->port, main_s->i2c_spi_addr_flags, + LSM6DSO_FIFO_DATA_ADDR_TAG, fifo, sizeof(fifo))); push_fifo_data(main_s, fifo, last_interrupt_timestamp); } @@ -205,8 +204,8 @@ static int accelgyro_config_fifo(const struct motion_sensor_t *s) fifo_odr_mask = LSM6DSO_FIFO_ODR_MASK(s); reg_val = LSM6DSO_ODR_TO_REG(data->base.odr); - err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR, - fifo_odr_mask, reg_val); + err = st_write_data_with_mask(s, LSM6DSO_FIFO_CTRL3_ADDR, fifo_odr_mask, + reg_val); if (err != EC_SUCCESS) return err; @@ -238,9 +237,9 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) do { /* Read how many data patterns on FIFO to read. */ - RETURN_ERROR(st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, - LSM6DSO_FIFO_STS1_ADDR, - (uint8_t *)&fsts, sizeof(fsts))); + RETURN_ERROR(st_raw_read_n_noinc( + s->port, s->i2c_spi_addr_flags, LSM6DSO_FIFO_STS1_ADDR, + (uint8_t *)&fsts, sizeof(fsts))); if (fsts.len & (LSM6DSO_FIFO_DATA_OVR | LSM6DSO_FIFO_FULL)) CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len); @@ -294,8 +293,7 @@ static int set_range(struct motion_sensor_t *s, int range, int rnd) } mutex_lock(s->mutex); - err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK, - reg_val); + err = st_write_data_with_mask(s, ctrl_reg, LSM6DSO_RANGE_MASK, reg_val); if (err == EC_SUCCESS) s->current_range = newrange; @@ -348,8 +346,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DSO_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RS Error", s->name, s->type); @@ -394,8 +392,8 @@ static int read(const struct motion_sensor_t *s, intv3_t v) xyz_reg = get_xyz_reg(s->type); /* Read data bytes starting at xyz_reg. */ - ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, - xyz_reg, raw, OUT_XYZ_SIZE); + ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, xyz_reg, raw, + OUT_XYZ_SIZE); if (ret != EC_SUCCESS) return ret; @@ -410,8 +408,8 @@ static int init(struct motion_sensor_t *s) int ret = 0, tmp; struct stprivate_data *data = LSM6DSO_GET_DATA(s); - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DSO_WHO_AM_I_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSO_WHO_AM_I_REG, + &tmp); if (ret != EC_SUCCESS) return EC_ERROR_UNKNOWN; @@ -438,10 +436,9 @@ static int init(struct motion_sensor_t *s) * Output data not updated until have been read. * Require interrupt to be active low. */ - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSO_CTRL3_ADDR, - LSM6DSO_BDU | LSM6DSO_IF_INC - | LSM6DSO_H_L_ACTIVE); + ret = st_raw_write8( + s->port, s->i2c_spi_addr_flags, LSM6DSO_CTRL3_ADDR, + LSM6DSO_BDU | LSM6DSO_IF_INC | LSM6DSO_H_L_ACTIVE); if (ret != EC_SUCCESS) goto err_unlock; @@ -482,8 +479,7 @@ int get_rms_noise(const struct motion_sensor_t *s) #endif #ifdef CONFIG_GESTURE_HOST_DETECTION -int lsm_list_activities(const struct motion_sensor_t *s, - uint32_t *enabled, +int lsm_list_activities(const struct motion_sensor_t *s, uint32_t *enabled, uint32_t *disabled) { struct stprivate_data *data = LSM6DSO_GET_DATA(s); -- cgit v1.2.1 From 8c1746c38879b2db38f8df2c465a536a56e00d10 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:54 -0600 Subject: zephyr/shim/src/switchcap_ln9310.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7bdbad65592346ddf6d19b2c9b3ebbad2d7aa427 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730915 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/switchcap_ln9310.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/zephyr/shim/src/switchcap_ln9310.c b/zephyr/shim/src/switchcap_ln9310.c index bd8612fb2e..95d608c9ba 100644 --- a/zephyr/shim/src/switchcap_ln9310.c +++ b/zephyr/shim/src/switchcap_ln9310.c @@ -18,11 +18,9 @@ #define SC_PIN_ENABLE_PHANDLE \ DT_PHANDLE_BY_IDX(DT_PATH(switchcap), enable_pin, 0) -#define SC_PIN_ENABLE \ - GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE) +#define SC_PIN_ENABLE GPIO_DT_FROM_NODE(SC_PIN_ENABLE_PHANDLE) -#define SC_PORT_PHANDLE \ - DT_PHANDLE(DT_PATH(switchcap), port) +#define SC_PORT_PHANDLE DT_PHANDLE(DT_PATH(switchcap), port) #define SC_PORT DT_STRING_UPPER_TOKEN(SC_PORT_PHANDLE, enum_name) #define SC_ADDR_FLAGS DT_STRING_UPPER_TOKEN(DT_PATH(switchcap), addr_flags) -- cgit v1.2.1 From 2546846c3ff4263b4d70ef5c0f2179fcfa0a9dd8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:07 -0600 Subject: zephyr/shim/src/temp_sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie6711266b9c95c77c9d1a0369a4b971c9ab86073 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730917 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/temp_sensors.c | 124 ++++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 65 deletions(-) diff --git a/zephyr/shim/src/temp_sensors.c b/zephyr/shim/src/temp_sensors.c index 4d8ff28945..e8332c16e5 100644 --- a/zephyr/shim/src/temp_sensors.c +++ b/zephyr/shim/src/temp_sensors.c @@ -15,20 +15,18 @@ #define GET_POWER_GOOD_PROP(node_id) DT_PROP(node_id, power_good_pin) -#define GET_POWER_GOOD_DEV(node_id) \ - DEVICE_DT_GET(DT_GPIO_CTLR(GET_POWER_GOOD_PROP(node_id), \ - gpios)) +#define GET_POWER_GOOD_DEV(node_id) \ + DEVICE_DT_GET(DT_GPIO_CTLR(GET_POWER_GOOD_PROP(node_id), gpios)) -#define GET_POWER_GOOD_PIN(node_id) DT_GPIO_PIN(GET_POWER_GOOD_PROP(node_id), \ - gpios) +#define GET_POWER_GOOD_PIN(node_id) \ + DT_GPIO_PIN(GET_POWER_GOOD_PROP(node_id), gpios) #if ANY_INST_HAS_POWER_GOOD_PIN -#define FILL_POWER_GOOD(node_id) \ -COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_good_pin), \ - (.power_good_dev = GET_POWER_GOOD_DEV(node_id), \ - .power_good_pin = GET_POWER_GOOD_PIN(node_id), ), \ - (.power_good_dev = NULL, \ - .power_good_pin = 0, )) +#define FILL_POWER_GOOD(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, power_good_pin), \ + (.power_good_dev = GET_POWER_GOOD_DEV(node_id), \ + .power_good_pin = GET_POWER_GOOD_PIN(node_id), ), \ + (.power_good_dev = NULL, .power_good_pin = 0, )) #else #define FILL_POWER_GOOD(node_id) #endif /* ANY_INST_HAS_POWER_GOOD_PIN */ @@ -58,20 +56,19 @@ static int thermistor_get_temp(const struct temp_sensor_t *sensor, .data = DT_CAT(node_id, _thermistor_data), \ }) -#define GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id) \ - (&(struct zephyr_temp_sensor){ \ - .read = &thermistor_get_temp, \ +#define GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id) \ + (&(struct zephyr_temp_sensor){ \ + .read = &thermistor_get_temp, \ .thermistor = \ GET_THERMISTOR_INFO(DT_PHANDLE(node_id, thermistor)), \ - FILL_POWER_GOOD(node_id) \ - }) - -#define TEMP_THERMISTOR(node_id) \ - [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ - .idx = ZSHIM_ADC_ID(DT_PHANDLE(node_id, adc)), \ - .type = TEMP_SENSOR_TYPE_BOARD, \ - .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id), \ + FILL_POWER_GOOD(node_id) }) + +#define TEMP_THERMISTOR(node_id) \ + [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ + .name = DT_LABEL(node_id), \ + .idx = ZSHIM_ADC_ID(DT_PHANDLE(node_id, adc)), \ + .type = TEMP_SENSOR_TYPE_BOARD, \ + .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id), \ }, DT_FOREACH_STATUS_OKAY(cros_ec_thermistor, DEFINE_THERMISTOR_DATA) @@ -89,19 +86,17 @@ static int pct2075_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) .i2c_addr_flags = DT_STRING_TOKEN(node_id, i2c_addr_flags), \ }, -#define GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id) \ - (&(struct zephyr_temp_sensor){ \ - .read = &pct2075_get_temp, \ - .thermistor = NULL, \ - FILL_POWER_GOOD(node_id) \ - }) - -#define TEMP_PCT2075(node_id) \ - [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ - .idx = ZSHIM_PCT2075_SENSOR_ID(node_id), \ - .type = TEMP_SENSOR_TYPE_BOARD, \ - .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id), \ +#define GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id) \ + (&(struct zephyr_temp_sensor){ .read = &pct2075_get_temp, \ + .thermistor = NULL, \ + FILL_POWER_GOOD(node_id) }) + +#define TEMP_PCT2075(node_id) \ + [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ + .name = DT_LABEL(node_id), \ + .idx = ZSHIM_PCT2075_SENSOR_ID(node_id), \ + .type = TEMP_SENSOR_TYPE_BOARD, \ + .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id), \ }, const struct pct2075_sensor_t pct2075_sensors[PCT2075_COUNT] = { @@ -121,19 +116,17 @@ static int sb_tsi_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) #endif /* cros_ec_temp_sensor_sb_tsi */ -#define GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id) \ - (&(struct zephyr_temp_sensor){ \ - .read = &sb_tsi_get_temp, \ - .thermistor = NULL, \ - FILL_POWER_GOOD(node_id) \ - }) - -#define TEMP_SB_TSI(node_id) \ - [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ - .idx = 0, \ - .type = TEMP_SENSOR_TYPE_CPU, \ - .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id), \ +#define GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id) \ + (&(struct zephyr_temp_sensor){ .read = &sb_tsi_get_temp, \ + .thermistor = NULL, \ + FILL_POWER_GOOD(node_id) }) + +#define TEMP_SB_TSI(node_id) \ + [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ + .name = DT_LABEL(node_id), \ + .idx = 0, \ + .type = TEMP_SENSOR_TYPE_CPU, \ + .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id), \ }, #if DT_HAS_COMPAT_STATUS_OKAY(cros_ec_temp_sensor_tmp112) @@ -149,19 +142,17 @@ static int tmp112_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) .i2c_addr_flags = DT_STRING_TOKEN(node_id, i2c_addr_flags), \ }, -#define GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id) \ - (&(struct zephyr_temp_sensor){ \ - .read = &tmp112_get_temp, \ - .thermistor = NULL, \ - FILL_POWER_GOOD(node_id) \ - }) - -#define TEMP_TMP112(node_id) \ - [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ - .idx = ZSHIM_TMP112_SENSOR_ID(node_id), \ - .type = TEMP_SENSOR_TYPE_BOARD, \ - .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id), \ +#define GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id) \ + (&(struct zephyr_temp_sensor){ .read = &tmp112_get_temp, \ + .thermistor = NULL, \ + FILL_POWER_GOOD(node_id) }) + +#define TEMP_TMP112(node_id) \ + [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ + .name = DT_LABEL(node_id), \ + .idx = ZSHIM_TMP112_SENSOR_ID(node_id), \ + .type = TEMP_SENSOR_TYPE_BOARD, \ + .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id), \ }, const struct tmp112_sensor_t tmp112_sensors[TMP112_COUNT] = { @@ -170,9 +161,12 @@ const struct tmp112_sensor_t tmp112_sensors[TMP112_COUNT] = { const struct temp_sensor_t temp_sensors[] = { DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_thermistor, TEMP_THERMISTOR) - DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075, TEMP_PCT2075) - DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_sb_tsi, TEMP_SB_TSI) - DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_tmp112, TEMP_TMP112) + DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_pct2075, + TEMP_PCT2075) + DT_FOREACH_STATUS_OKAY(cros_ec_temp_sensor_sb_tsi, + TEMP_SB_TSI) + DT_FOREACH_STATUS_OKAY( + cros_ec_temp_sensor_tmp112, TEMP_TMP112) }; int temp_sensor_read(enum temp_sensor_id id, int *temp_ptr) -- cgit v1.2.1 From 18d9d3259610e85617ea2c384d8e8dd2d7119e0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:31 -0600 Subject: zephyr/drivers/cros_system/cros_system_it8xxx2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idb94578e0a6142a4b2aba3ed7ecad04edc5e9bc8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730681 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_system/cros_system_it8xxx2.c | 48 ++++++++++++------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c index 693b981e83..39fde98175 100644 --- a/zephyr/drivers/cros_system/cros_system_it8xxx2.c +++ b/zephyr/drivers/cros_system/cros_system_it8xxx2.c @@ -36,8 +36,7 @@ static uint32_t system_get_chip_id(void) struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE; return (gctrl_base->GCTRL_ECHIPID1 << 16) | - (gctrl_base->GCTRL_ECHIPID2 << 8) | - gctrl_base->GCTRL_ECHIPID3; + (gctrl_base->GCTRL_ECHIPID2 << 8) | gctrl_base->GCTRL_ECHIPID3; } static uint8_t system_get_chip_version(void) @@ -52,26 +51,26 @@ static const char *cros_system_it8xxx2_get_chip_name(const struct device *dev) { ARG_UNUSED(dev); - static char buf[8] = {'i', 't'}; + static char buf[8] = { 'i', 't' }; uint32_t chip_id = system_get_chip_id(); int num = 4; for (int n = 2; num >= 0; n++, num--) - snprintf(buf+n, (sizeof(buf)-n), "%x", + snprintf(buf + n, (sizeof(buf) - n), "%x", chip_id >> (num * 4) & 0xF); return buf; } -static const char *cros_system_it8xxx2_get_chip_revision(const struct device - *dev) +static const char * +cros_system_it8xxx2_get_chip_revision(const struct device *dev) { ARG_UNUSED(dev); static char buf[3]; uint8_t rev = system_get_chip_version(); - snprintf(buf, sizeof(buf), "%1xx", rev+0xa); + snprintf(buf, sizeof(buf), "%1xx", rev + 0xa); return buf; } @@ -81,9 +80,10 @@ static int cros_system_it8xxx2_get_reset_cause(const struct device *dev) ARG_UNUSED(dev); struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE; uint8_t last_reset_source = gctrl_base->GCTRL_RSTS & IT8XXX2_GCTRL_LRS; - uint8_t raw_reset_cause2 = gctrl_base->GCTRL_SPCTRL4 & + uint8_t raw_reset_cause2 = + gctrl_base->GCTRL_SPCTRL4 & (IT8XXX2_GCTRL_LRSIWR | IT8XXX2_GCTRL_LRSIPWRSWTR | - IT8XXX2_GCTRL_LRSIPGWR); + IT8XXX2_GCTRL_LRSIPGWR); /* Clear reset cause. */ gctrl_base->GCTRL_RSTS |= IT8XXX2_GCTRL_LRS; @@ -185,8 +185,8 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev, * Convert milliseconds(or at least 1 ms) to 32 Hz * free run timer count for hibernate. */ - uint32_t c = (seconds * 1000 + microseconds / 1000 + 1) * - 32 / 1000; + uint32_t c = + (seconds * 1000 + microseconds / 1000 + 1) * 32 / 1000; /* Enable a 32-bit timer and clock source is 32 Hz */ /* Disable external timer x */ @@ -205,7 +205,7 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev, /* * Get the interrupt DTS node for this wakeup pin */ -#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx) +#define WAKEUP_INT(id, prop, idx) DT_PHANDLE_BY_IDX(id, prop, idx) /* * Get the named-gpio node for this wakeup pin by reading the @@ -217,19 +217,19 @@ static int cros_system_it8xxx2_hibernate(const struct device *dev, /* * Reset and re-enable interrupts on this wake pin. */ -#define WAKEUP_SETUP(id, prop, idx) \ -do { \ - gpio_pin_configure_dt(GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \ - GPIO_INPUT); \ - gpio_enable_dt_interrupt( \ - GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \ +#define WAKEUP_SETUP(id, prop, idx) \ + do { \ + gpio_pin_configure_dt( \ + GPIO_DT_FROM_NODE(WAKEUP_NGPIO(id, prop, idx)), \ + GPIO_INPUT); \ + gpio_enable_dt_interrupt( \ + GPIO_INT_FROM_NODE(WAKEUP_INT(id, prop, idx))); \ } while (0); -/* - * For all the wake-pins, re-init the GPIO and re-enable the interrupt. - */ - DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, - wakeup_irqs, + /* + * For all the wake-pins, re-init the GPIO and re-enable the interrupt. + */ + DT_FOREACH_PROP_ELEM(SYSTEM_DT_NODE_HIBERNATE_CONFIG, wakeup_irqs, WAKEUP_SETUP); #undef WAKEUP_INT @@ -242,7 +242,7 @@ do { \ chip_pll_ctrl(CHIP_PLL_SLEEP); /* Chip sleep and wait timer wake it up */ - __asm__ volatile ("wfi"); + __asm__ volatile("wfi"); /* Reset EC when wake up from sleep mode (system hibernate) */ system_reset(SYSTEM_RESET_HIBERNATE); -- cgit v1.2.1 From 18fc5f2005ce4d9bd0ef0e4d95dbd5b1e2829dcc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:53 -0600 Subject: board/reef_mchp/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9afa8ca32261df9c3ba54673ae2287f6a87b21ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728885 Reviewed-by: Jeremy Bettis --- board/reef_mchp/board.c | 147 ++++++++++++++++++++---------------------------- 1 file changed, 62 insertions(+), 85 deletions(-) diff --git a/board/reef_mchp/board.c b/board/reef_mchp/board.c index c9293ad080..8fe85f70f7 100644 --- a/board/reef_mchp/board.c +++ b/board/reef_mchp/board.c @@ -57,17 +57,16 @@ #include "usb_pd_tcpm.h" #include "util.h" - #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) -#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) +#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 #ifdef CONFIG_BOARD_PRE_INIT /* @@ -161,7 +160,7 @@ void tablet_mode_interrupt(enum gpio_signal signal) /* SPI devices */ const struct spi_device_t spi_devices[] = { - { QMSPI0_PORT, 4, GPIO_QMSPI_CS0}, + { QMSPI0_PORT, 4, GPIO_QMSPI_CS0 }, #if defined(CONFIG_SPI_ACCEL_PORT) { GPSPI0_PORT, 2, GPIO_SPI0_CS0 }, #endif @@ -175,15 +174,9 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); */ const struct adc_t adc_channels[] = { /* Vref = 3.000V, 10-bit unsigned reading */ - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", 3000, 1024, 0, 0 - }, - [ADC_TEMP_SENSOR_AMB] = { - "AMBIENT", 3000, 1024, 0, 1 - }, - [ADC_BOARD_ID] = { - "BRD_ID", 3000, 1024, 0, 2 - }, + [ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", 3000, 1024, 0, 0 }, + [ADC_TEMP_SENSOR_AMB] = { "AMBIENT", 3000, 1024, 0, 1 }, + [ADC_BOARD_ID] = { "BRD_ID", 3000, 1024, 0, 2 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -192,7 +185,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct pwm_t pwm_channels[] = { /* channel, flags */ [PWM_CH_LED_GREEN] = { 4, PWM_CONFIG_DSLEEP }, - [PWM_CH_LED_RED] = { 5, PWM_CONFIG_DSLEEP }, + [PWM_CH_LED_RED] = { 5, PWM_CONFIG_DSLEEP }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); #endif /* #ifdef CONFIG_PWM */ @@ -203,42 +196,32 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); * Due to added RC of interposer board temporarily reduce * 400 to 100 kHz. */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = MCHP_I2C_PORT0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = MCHP_I2C_PORT2, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "accelgyro", - .port = I2C_PORT_GYRO, - .kbps = 400, - .scl = GPIO_EC_I2C_GYRO_SCL, - .sda = GPIO_EC_I2C_GYRO_SDA - }, - { - .name = "sensors", - .port = MCHP_I2C_PORT7, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, - { - .name = "batt", - .port = MCHP_I2C_PORT3, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = MCHP_I2C_PORT0, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = MCHP_I2C_PORT2, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "accelgyro", + .port = I2C_PORT_GYRO, + .kbps = 400, + .scl = GPIO_EC_I2C_GYRO_SCL, + .sda = GPIO_EC_I2C_GYRO_SDA }, + { .name = "sensors", + .port = MCHP_I2C_PORT7, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, + { .name = "batt", + .port = MCHP_I2C_PORT3, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -534,9 +517,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); /* * Data derived from Seinhart-Hart equation in a resistor divider circuit with @@ -573,8 +556,7 @@ int board_get_charger_temp(int idx, int *temp_ptr) if (mv < 0) return -1; - *temp_ptr = thermistor_linear_interpolate(mv, - &charger_thermistor_info); + *temp_ptr = thermistor_linear_interpolate(mv, &charger_thermistor_info); *temp_ptr = C_TO_K(*temp_ptr); return 0; } @@ -614,8 +596,7 @@ int board_get_ambient_temp(int idx, int *temp_ptr) if (mv < 0) return -1; - *temp_ptr = thermistor_linear_interpolate(mv, - &amb_thermistor_info); + *temp_ptr = thermistor_linear_interpolate(mv, &amb_thermistor_info); *temp_ptr = C_TO_K(*temp_ptr); return 0; } @@ -626,9 +607,9 @@ int board_get_ambient_temp(int idx, int *temp_ptr) * delay from read to taking action */ const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, - {"Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, board_get_ambient_temp, 0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_charger_temp, 1 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -750,8 +731,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Enable charging trigger by BC1.2 detection */ int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP || @@ -763,8 +744,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, return; charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -890,17 +871,17 @@ void board_hibernate_late(void) int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs in hibernate */ - {GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN}, + { GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN }, /* * BD99956 handles charge input automatically. We'll disable * charge output in hibernate. Charger will assert ACOK_OD * when VBUS or VCC are plugged in. */ - {GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, - {GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + { GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, + { GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, }; /* Change GPIOs' state in hibernate for better power consumption */ @@ -927,17 +908,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t mag_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -1113,8 +1090,8 @@ struct { int thresh_mv; } const reef_board_versions[] = { /* Vin = 3.3V, R1 = 46.4K, R2 values listed below */ - { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ - { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ + { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ + { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ { BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */ { BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */ { BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */ -- cgit v1.2.1 From fe7c249d0a05779cf90673f1c3fd6f7727b49c1d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:13 -0600 Subject: board/metaknight/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I036d351ba2ebe603a2b05cef880f4283bc1bdfe1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728452 Reviewed-by: Jeremy Bettis --- board/metaknight/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/metaknight/cbi_ssfc.h b/board/metaknight/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/metaknight/cbi_ssfc.h +++ b/board/metaknight/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 22ef41d4e34bb6044e0b3c5c9af607cd0476d539 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:19 -0600 Subject: zephyr/test/ap_power/src/signals.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I921b3be922e4f62d42f0bb4e40208bf39b56dcaa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730969 Reviewed-by: Jeremy Bettis --- zephyr/test/ap_power/src/signals.c | 104 ++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 54 deletions(-) diff --git a/zephyr/test/ap_power/src/signals.c b/zephyr/test/ap_power/src/signals.c index c2ccffb8c9..e50c8dd09b 100644 --- a/zephyr/test/ap_power/src/signals.c +++ b/zephyr/test/ap_power/src/signals.c @@ -37,19 +37,13 @@ static struct { enum power_signal signal; int pin; } signal_to_pin_table[] = { -{ PWR_EN_PP5000_A, 10}, -{ PWR_EN_PP3300_A, 11}, -{ PWR_RSMRST, 12}, -{ PWR_EC_PCH_RSMRST, 13}, -{ PWR_SLP_S0, 14}, -{ PWR_SLP_S3, 15}, -{ PWR_SLP_SUS, 16}, -{ PWR_EC_SOC_DSW_PWROK, 17}, -{ PWR_VCCST_PWRGD, 18}, -{ PWR_IMVP9_VRRDY, 19}, -{ PWR_PCH_PWROK, 20}, -{ PWR_EC_PCH_SYS_PWROK, 21}, -{ PWR_SYS_RST, 22}, + { PWR_EN_PP5000_A, 10 }, { PWR_EN_PP3300_A, 11 }, + { PWR_RSMRST, 12 }, { PWR_EC_PCH_RSMRST, 13 }, + { PWR_SLP_S0, 14 }, { PWR_SLP_S3, 15 }, + { PWR_SLP_SUS, 16 }, { PWR_EC_SOC_DSW_PWROK, 17 }, + { PWR_VCCST_PWRGD, 18 }, { PWR_IMVP9_VRRDY, 19 }, + { PWR_PCH_PWROK, 20 }, { PWR_EC_PCH_SYS_PWROK, 21 }, + { PWR_SYS_RST, 22 }, }; /* @@ -106,9 +100,9 @@ ZTEST(signals, test_validate_request) zassert_equal(-EINVAL, power_signal_enable(PWR_IMVP9_VRRDY), "enable interrupt on input pin without interrupt config"); /* Can't disable interrupt on input with no interrupt flags */ - zassert_equal(-EINVAL, - power_signal_disable(PWR_IMVP9_VRRDY), - "disable interrupt on input pin without interrupt config"); + zassert_equal( + -EINVAL, power_signal_disable(PWR_IMVP9_VRRDY), + "disable interrupt on input pin without interrupt config"); /* Invalid signal - should be rejectde */ zassert_equal(-EINVAL, power_signal_get(-1), "power_signal_get with -1 signal should fail"); @@ -135,7 +129,7 @@ ZTEST(signals, test_board_signals) * Check that the board level signals get correctly invoked. */ zassert_ok(power_signal_set(PWR_ALL_SYS_PWRGD, 1), - "power_signal_set on board signal failed"); + "power_signal_set on board signal failed"); zassert_equal(1, power_signal_get(PWR_ALL_SYS_PWRGD), "power_signal_get on board signal should return 1"); } @@ -153,12 +147,13 @@ ZTEST(signals, test_signal_name) { for (int signal = 0; signal < POWER_SIGNAL_COUNT; signal++) { zassert_not_null(power_signal_name(signal), - "Signal name for %d should be not null", signal); + "Signal name for %d should be not null", + signal); } zassert_is_null(power_signal_name(-1), - "Out of bounds signal name should be null"); + "Out of bounds signal name should be null"); zassert_is_null(power_signal_name(POWER_SIGNAL_COUNT), - "Out of bounds signal name should be null"); + "Out of bounds signal name should be null"); } /** @@ -180,18 +175,19 @@ ZTEST(signals, test_init_outputs) static const enum power_signal active_high[] = { PWR_EN_PP5000_A, PWR_EN_PP3300_A, PWR_EC_PCH_RSMRST, PWR_EC_SOC_DSW_PWROK, PWR_PCH_PWROK - }; + }; static const enum power_signal active_low[] = { PWR_SYS_RST }; for (int i = 0; i < ARRAY_SIZE(active_high); i++) { zassert_equal(0, emul_get(active_high[i]), - "Signal %d (%s) init to de-asserted state failed", - active_high[i], power_signal_name(active_high[i])); + "Signal %d (%s) init to de-asserted state failed", + active_high[i], + power_signal_name(active_high[i])); } for (int i = 0; i < ARRAY_SIZE(active_low); i++) { zassert_equal(1, emul_get(active_low[i]), - "Signal %d (%s) init to de-asserted state failed", - active_low[i], power_signal_name(active_low[i])); + "Signal %d (%s) init to de-asserted state failed", + active_low[i], power_signal_name(active_low[i])); } } @@ -212,14 +208,15 @@ ZTEST(signals, test_gpio_input) "power_signal_get of PWR_RSMRST should be 1"); emul_set(PWR_RSMRST, 0); zassert_equal(0, power_signal_get(PWR_RSMRST), - "power_signal_get of PWR_RSMRST should be 0"); + "power_signal_get of PWR_RSMRST should be 0"); /* ACTIVE_LOW input */ emul_set(PWR_SLP_S0, 0); - zassert_equal(1, power_signal_get(PWR_SLP_S0), - "power_signal_get of active-low signal PWR_SLP_S0 should be 1"); + zassert_equal( + 1, power_signal_get(PWR_SLP_S0), + "power_signal_get of active-low signal PWR_SLP_S0 should be 1"); emul_set(PWR_SLP_S0, 1); zassert_equal(0, power_signal_get(PWR_SLP_S0), - "power_signal_get of active-low PWR_SLP_S0 should be 0"); + "power_signal_get of active-low PWR_SLP_S0 should be 0"); } /** @@ -235,17 +232,17 @@ ZTEST(signals, test_gpio_output) { power_signal_set(PWR_PCH_PWROK, 1); zassert_equal(1, emul_get(PWR_PCH_PWROK), - "power_signal_set of PWR_PCH_PWROK should be 1"); + "power_signal_set of PWR_PCH_PWROK should be 1"); power_signal_set(PWR_PCH_PWROK, 0); zassert_equal(0, emul_get(PWR_PCH_PWROK), - "power_signal_set of PWR_PCH_PWROK should be 0"); + "power_signal_set of PWR_PCH_PWROK should be 0"); /* ACTIVE_LOW output */ power_signal_set(PWR_SYS_RST, 0); zassert_equal(1, emul_get(PWR_SYS_RST), - "power_signal_set of PWR_SYS_RST should be 1"); + "power_signal_set of PWR_SYS_RST should be 1"); power_signal_set(PWR_SYS_RST, 1); zassert_equal(0, emul_get(PWR_SYS_RST), - "power_signal_set of PWR_SYS_RST should be 0"); + "power_signal_set of PWR_SYS_RST should be 0"); } /** @@ -269,7 +266,8 @@ ZTEST(signals, test_signal_mask) * Set board level (polled) signal. */ power_signal_set(PWR_ALL_SYS_PWRGD, 1); - zassert_equal(bm, (power_get_signals() & bm), + zassert_equal( + bm, (power_get_signals() & bm), "Expected PWR_ALL_SYS_PWRGD signal to be present in mask"); /* * Use GPIO that does not interrupt to confirm that a pin change @@ -281,11 +279,11 @@ ZTEST(signals, test_signal_mask) emul_set(PWR_IMVP9_VRRDY, 1); zassert_equal(0, (power_get_signals() & vm), "Expected mask to be 0"); zassert_equal(true, power_signals_match(bm, bm), - "Expected match of mask to signal match"); + "Expected match of mask to signal match"); zassert_equal(-ETIMEDOUT, power_wait_mask_signals_timeout(bm, 0, 5), - "Expected timeout waiting for mask to be 0"); + "Expected timeout waiting for mask to be 0"); zassert_ok(power_wait_mask_signals_timeout(0, vm, 5), - "expected match with a 0 mask (always true)"); + "expected match with a 0 mask (always true)"); } /** @@ -305,7 +303,7 @@ ZTEST(signals, test_debug_mask) old = power_get_debug(); power_set_debug(dm); zassert_equal(dm, power_get_debug(), - "Debug mask does not match set value"); + "Debug mask does not match set value"); /* * Reset back to default. */ @@ -332,10 +330,10 @@ ZTEST(signals, test_gpio_interrupts) /* Check that GPIO pin changes update the signal mask. */ emul_set(PWR_RSMRST, 1); zassert_equal(true, power_signals_on(rsm), - "PWR_RSMRST not updated in mask"); + "PWR_RSMRST not updated in mask"); emul_set(PWR_RSMRST, 0); zassert_equal(true, power_signals_off(rsm), - "PWR_RSMRST not updated in mask"); + "PWR_RSMRST not updated in mask"); /* * Check that an ACTIVE_LOW signal gets asserted in @@ -343,10 +341,10 @@ ZTEST(signals, test_gpio_interrupts) */ emul_set(PWR_SLP_S3, 0); zassert_equal(true, power_signals_on(s3), - "SLP_S3 signal should be on in mask"); + "SLP_S3 signal should be on in mask"); emul_set(PWR_SLP_S3, 1); zassert_equal(true, power_signals_off(s3), - "SLP_S3 should be off in mask"); + "SLP_S3 should be off in mask"); /* * Check that disabled interrupt on the GPIO does not trigger @@ -354,18 +352,18 @@ ZTEST(signals, test_gpio_interrupts) */ emul_set(PWR_SLP_S0, 0); zassert_equal(false, power_signals_on(s0), - "SLP_S0 should not have updated"); + "SLP_S0 should not have updated"); emul_set(PWR_SLP_S0, 1); zassert_equal(false, power_signals_on(s0), - "SLP_S0 should not have updated"); + "SLP_S0 should not have updated"); power_signal_enable(PWR_SLP_S0); emul_set(PWR_SLP_S0, 0); zassert_equal(true, power_signals_on(s0), - "SLP_S0 should have updated the mask"); + "SLP_S0 should have updated the mask"); emul_set(PWR_SLP_S0, 1); zassert_equal(true, power_signals_off(s0), - "SLP_S0 should have updated the mask"); + "SLP_S0 should have updated the mask"); /* * Disable the GPIO interrupt again. @@ -373,10 +371,10 @@ ZTEST(signals, test_gpio_interrupts) power_signal_disable(PWR_SLP_S0); emul_set(PWR_SLP_S0, 0); zassert_equal(false, power_signals_on(s0), - "SLP_S0 should not have updated the mask"); + "SLP_S0 should not have updated the mask"); emul_set(PWR_SLP_S0, 1); zassert_equal(true, power_signals_off(s0), - "SLP_S0 should not have updated the mask"); + "SLP_S0 should not have updated the mask"); } /** @@ -400,11 +398,9 @@ ZTEST(signals, test_espi_vw) * so sending a 0 value should be received as a signal. */ emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 0); - zassert_equal(1, power_signal_get(PWR_SLP_S5), - "VW SLP_S5 should be 1"); + zassert_equal(1, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 1"); emul_espi_host_send_vw(espi, ESPI_VWIRE_SIGNAL_SLP_S5, 1); - zassert_equal(0, power_signal_get(PWR_SLP_S5), - "VW SLP_S5 should be 0"); + zassert_equal(0, power_signal_get(PWR_SLP_S5), "VW SLP_S5 should be 0"); } static void *init_dev(void) @@ -422,5 +418,5 @@ static void init_signals(void *data) /** * @brief Test Suite: Verifies power signal functionality. */ -ZTEST_SUITE(signals, ap_power_predicate_post_main, - init_dev, init_signals, NULL, NULL); +ZTEST_SUITE(signals, ap_power_predicate_post_main, init_dev, init_signals, NULL, + NULL); -- cgit v1.2.1 From 922d51a6dbde3d4e7eb3f8359df11fecf3f7489e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:03 -0600 Subject: chip/max32660/flash_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief6b204e4fb74f5528cf5b1ff57a561af49436ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729229 Reviewed-by: Jeremy Bettis --- chip/max32660/flash_chip.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/chip/max32660/flash_chip.c b/chip/max32660/flash_chip.c index 747d7dcc58..29d2f35489 100644 --- a/chip/max32660/flash_chip.c +++ b/chip/max32660/flash_chip.c @@ -25,7 +25,7 @@ #define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) /// Calculate the address of a page in flash from the page number -#define MXC_FLASH_PAGE_ADDR(page) \ +#define MXC_FLASH_PAGE_ADDR(page) \ (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) void flash_operation(void) @@ -123,7 +123,6 @@ int crec_flash_physical_write(int offset, int size, const char *data) // Align the address and read/write if we have to if (offset & 0x3) { - // Figure out how many bytes we have to write to round up the // address bytes_written = 4 - (offset & 0x3); @@ -163,7 +162,6 @@ int crec_flash_physical_write(int offset, int size, const char *data) } if (size >= 16) { - // write in 128-bit bursts while we can MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH; @@ -330,8 +328,8 @@ static int command_flash_test1(int argc, char **argv) /* * erase page */ - error_status = crec_flash_physical_erase(flash_address, - CONFIG_FLASH_ERASE_SIZE); + error_status = crec_flash_physical_erase( + flash_address, CONFIG_FLASH_ERASE_SIZE); if (error_status != EC_SUCCESS) { CPRINTS("Error with crec_flash_physical_erase\n"); return EC_ERROR_UNKNOWN; @@ -389,8 +387,8 @@ static int command_flash_test1(int argc, char **argv) */ for (page = PAGE_START; page <= PAGE_END; page++) { flash_address = page * CONFIG_FLASH_ERASE_SIZE; - error_status = crec_flash_physical_erase(flash_address, - CONFIG_FLASH_ERASE_SIZE); + error_status = crec_flash_physical_erase( + flash_address, CONFIG_FLASH_ERASE_SIZE); if (error_status != EC_SUCCESS) { CPRINTS("Error with crec_flash_physical_erase\n"); return EC_ERROR_UNKNOWN; -- cgit v1.2.1 From 0dcae4667028e27fcc0361b27a3c6659efe04d6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:35 -0600 Subject: chip/stm32/adc-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0dea982a55d8fd967023c81bea3e9f28a790443 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729452 Reviewed-by: Jeremy Bettis --- chip/stm32/adc-stm32f4.c | 261 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 260 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/adc-stm32f4.c diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c deleted file mode 120000 index 5e375b9dbf..0000000000 --- a/chip/stm32/adc-stm32f4.c +++ /dev/null @@ -1 +0,0 @@ -adc-stm32f3.c \ No newline at end of file diff --git a/chip/stm32/adc-stm32f4.c b/chip/stm32/adc-stm32f4.c new file mode 100644 index 0000000000..66a41a5965 --- /dev/null +++ b/chip/stm32/adc-stm32f4.c @@ -0,0 +1,260 @@ +/* Copyright 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "clock.h" +#include "common.h" +#include "console.h" +#include "dma.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "timer.h" +#include "util.h" + +#define ADC_SINGLE_READ_TIMEOUT 3000 /* 3 ms */ + +#define SMPR1_EXPAND(v) \ + ((v) | ((v) << 3) | ((v) << 6) | ((v) << 9) | ((v) << 12) | \ + ((v) << 15) | ((v) << 18) | ((v) << 21)) +#define SMPR2_EXPAND(v) (SMPR1_EXPAND(v) | ((v) << 24) | ((v) << 27)) + +/* Default ADC sample time = 13.5 cycles */ +#ifndef CONFIG_ADC_SAMPLE_TIME +#define CONFIG_ADC_SAMPLE_TIME 2 +#endif + +struct mutex adc_lock; + +static int watchdog_ain_id; + +static inline void adc_set_channel(int sample_id, int channel) +{ + uint32_t mask, val; + volatile uint32_t *sqr_reg; + + if (sample_id < 6) { + mask = 0x1f << (sample_id * 5); + val = channel << (sample_id * 5); + sqr_reg = &STM32_ADC_SQR3; + } else if (sample_id < 12) { + mask = 0x1f << ((sample_id - 6) * 5); + val = channel << ((sample_id - 6) * 5); + sqr_reg = &STM32_ADC_SQR2; + } else { + mask = 0x1f << ((sample_id - 12) * 5); + val = channel << ((sample_id - 12) * 5); + sqr_reg = &STM32_ADC_SQR1; + } + + *sqr_reg = (*sqr_reg & ~mask) | val; +} + +static void adc_configure(int ain_id) +{ + /* Set ADC channel */ + adc_set_channel(0, ain_id); + + /* Disable DMA */ + STM32_ADC_CR2 &= ~BIT(8); + + /* Disable scan mode */ + STM32_ADC_CR1 &= ~BIT(8); +} + +static void __attribute__((unused)) adc_configure_all(void) +{ + int i; + + /* Set ADC channels */ + STM32_ADC_SQR1 = (ADC_CH_COUNT - 1) << 20; + for (i = 0; i < ADC_CH_COUNT; ++i) + adc_set_channel(i, adc_channels[i].channel); + + /* Enable DMA */ + STM32_ADC_CR2 |= BIT(8); + + /* Enable scan mode */ + STM32_ADC_CR1 |= BIT(8); +} + +static inline int adc_powered(void) +{ + return STM32_ADC_CR2 & BIT(0); +} + +static inline int adc_conversion_ended(void) +{ + return STM32_ADC_SR & BIT(1); +} + +static int adc_watchdog_enabled(void) +{ + return STM32_ADC_CR1 & BIT(23); +} + +static int adc_enable_watchdog_no_lock(void) +{ + /* Fail if watchdog already enabled */ + if (adc_watchdog_enabled()) + return EC_ERROR_UNKNOWN; + + /* Set channel */ + STM32_ADC_SQR3 = watchdog_ain_id; + STM32_ADC_SQR1 = 0; + STM32_ADC_CR1 = (STM32_ADC_CR1 & ~0x1f) | watchdog_ain_id; + + /* Clear interrupt bit */ + STM32_ADC_SR &= ~0x1; + + /* AWDSGL=1, SCAN=1, AWDIE=1, AWDEN=1 */ + STM32_ADC_CR1 |= BIT(9) | BIT(8) | BIT(6) | BIT(23); + + /* Disable DMA */ + STM32_ADC_CR2 &= ~BIT(8); + + /* CONT=1 */ + STM32_ADC_CR2 |= BIT(1); + + /* Start conversion */ + STM32_ADC_CR2 |= BIT(0); + + return EC_SUCCESS; +} + +int adc_enable_watchdog(int ain_id, int high, int low) +{ + int ret; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + + watchdog_ain_id = ain_id; + + /* Set thresholds */ + STM32_ADC_HTR = high & 0xfff; + STM32_ADC_LTR = low & 0xfff; + + ret = adc_enable_watchdog_no_lock(); + mutex_unlock(&adc_lock); + return ret; +} + +static int adc_disable_watchdog_no_lock(void) +{ + /* Fail if watchdog not running */ + if (!adc_watchdog_enabled()) + return EC_ERROR_UNKNOWN; + + /* AWDEN=0, AWDIE=0 */ + STM32_ADC_CR1 &= ~BIT(23) & ~BIT(6); + + /* CONT=0 */ + STM32_ADC_CR2 &= ~BIT(1); + + return EC_SUCCESS; +} + +int adc_disable_watchdog(void) +{ + int ret; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + ret = adc_disable_watchdog_no_lock(); + mutex_unlock(&adc_lock); + return ret; +} + +int adc_read_channel(enum adc_channel ch) +{ + const struct adc_t *adc = adc_channels + ch; + int value; + int restore_watchdog = 0; + timestamp_t deadline; + + if (!adc_powered()) + return EC_ERROR_UNKNOWN; + + mutex_lock(&adc_lock); + + if (adc_watchdog_enabled()) { + restore_watchdog = 1; + adc_disable_watchdog_no_lock(); + } + + adc_configure(adc->channel); + + /* Clear EOC bit */ + STM32_ADC_SR &= ~BIT(1); + + /* Start conversion (Note: For now only confirmed on F4) */ +#if defined(CHIP_FAMILY_STM32F4) + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; +#else + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; +#endif + + /* Wait for EOC bit set */ + deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; + value = ADC_READ_ERROR; + do { + if (adc_conversion_ended()) { + value = STM32_ADC_DR & ADC_READ_MAX; + break; + } + } while (!timestamp_expired(deadline, NULL)); + + if (restore_watchdog) + adc_enable_watchdog_no_lock(); + + mutex_unlock(&adc_lock); + return (value == ADC_READ_ERROR) ? + ADC_READ_ERROR : + value * adc->factor_mul / adc->factor_div + adc->shift; +} + +static void adc_init(void) +{ + /* + * Enable ADC clock. + * APB2 clock is 16MHz. ADC clock prescaler is /2. + * So the ADC clock is 8MHz. + */ + clock_enable_module(MODULE_ADC, 1); + + /* + * ADC clock is divided with respect to AHB, so no delay needed + * here. If ADC clock is the same as AHB, a read on ADC + * register is needed here. + */ + + if (!adc_powered()) { + /* Power on ADC module */ + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; + + /* Reset calibration */ + STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) + ; + + /* A/D Calibrate */ + STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) + ; + } + + /* Set right alignment */ + STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; + + /* Set sample time of all channels */ + STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); + STM32_ADC_SMPR2 = SMPR2_EXPAND(CONFIG_ADC_SAMPLE_TIME); +} +DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); -- cgit v1.2.1 From c25e1ae6b128eb9cc2b0d73de3f4a005a4086172 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:28 -0600 Subject: chip/stm32/gpio_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib7c451a1ae29880bad2efb0656389f27c0c7eff5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729510 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/gpio_chip.h b/chip/stm32/gpio_chip.h index b440cf5041..c15b3dfe42 100644 --- a/chip/stm32/gpio_chip.h +++ b/chip/stm32/gpio_chip.h @@ -20,4 +20,4 @@ void gpio_enable_clocks(void); int gpio_required_clocks(void); void __keep gpio_interrupt(void); -#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ +#endif /* __CROS_EC_CHIP_STM32_GPIO_CHIP_H */ -- cgit v1.2.1 From 9a4edfa2caf0356d2a84b07371015f89c52db41f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:05 -0600 Subject: common/lb_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fdaa337d73b0307f6d1c26b8542b3c0f78b1afd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729660 Reviewed-by: Jeremy Bettis --- common/lb_common.c | 68 +++++++++++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/common/lb_common.c b/common/lb_common.c index 019e0e254f..7cdd0067dd 100644 --- a/common/lb_common.c +++ b/common/lb_common.c @@ -101,8 +101,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr) -#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ## args) -#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_LIGHTBAR, format, ##args) +#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args) /******************************************************************************/ /* How to talk to the controller */ @@ -120,9 +120,8 @@ static inline void controller_write(int ctrl_num, uint8_t reg, uint8_t val) buf[0] = reg; buf[1] = val; ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags); - i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num], - buf, 2, 0, 0, - I2C_XFER_SINGLE); + i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num], buf, 2, + 0, 0, I2C_XFER_SINGLE); } static inline uint8_t controller_read(int ctrl_num, uint8_t reg) @@ -132,7 +131,7 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg) ctrl_num = ctrl_num % ARRAY_SIZE(i2c_addr_flags); rv = i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, i2c_addr_flags[ctrl_num], - ®, 1, buf, 1, I2C_XFER_SINGLE); + ®, 1, buf, 1, I2C_XFER_SINGLE); return rv ? 0 : buf[0]; } @@ -149,15 +148,15 @@ static inline uint8_t controller_read(int ctrl_num, uint8_t reg) * I've lowered the other colors until they all appear approximately equal * brightness when full on. That's still pretty bright and a lot of current * drain on the battery, so we'll probably rarely go that high. */ -#define MAX_RED 0x5c +#define MAX_RED 0x5c #define MAX_GREEN 0x30 -#define MAX_BLUE 0x67 +#define MAX_BLUE 0x67 #endif #ifdef BOARD_HOST /* For testing only */ -#define MAX_RED 0xff +#define MAX_RED 0xff #define MAX_GREEN 0xff -#define MAX_BLUE 0xff +#define MAX_BLUE 0xff #endif /* How we'd like to see the driver chips initialized. The controllers have some @@ -169,20 +168,20 @@ struct initdata_s { }; static const struct initdata_s init_vals[] = { - {0x04, 0x00}, /* no backlight function */ - {0x05, 0x3f}, /* xRGBRGB per chip */ - {0x0f, 0x01}, /* square law looks better */ - {0x10, 0x3f}, /* enable independent LEDs */ - {0x11, 0x00}, /* no auto cycling */ - {0x12, 0x00}, /* no auto cycling */ - {0x13, 0x00}, /* instant fade in/out */ - {0x14, 0x00}, /* not using LED 7 */ - {0x15, 0x00}, /* current for LED 6 (blue) */ - {0x16, 0x00}, /* current for LED 5 (red) */ - {0x17, 0x00}, /* current for LED 4 (green) */ - {0x18, 0x00}, /* current for LED 3 (blue) */ - {0x19, 0x00}, /* current for LED 2 (red) */ - {0x1a, 0x00}, /* current for LED 1 (green) */ + { 0x04, 0x00 }, /* no backlight function */ + { 0x05, 0x3f }, /* xRGBRGB per chip */ + { 0x0f, 0x01 }, /* square law looks better */ + { 0x10, 0x3f }, /* enable independent LEDs */ + { 0x11, 0x00 }, /* no auto cycling */ + { 0x12, 0x00 }, /* no auto cycling */ + { 0x13, 0x00 }, /* instant fade in/out */ + { 0x14, 0x00 }, /* not using LED 7 */ + { 0x15, 0x00 }, /* current for LED 6 (blue) */ + { 0x16, 0x00 }, /* current for LED 5 (red) */ + { 0x17, 0x00 }, /* current for LED 4 (green) */ + { 0x18, 0x00 }, /* current for LED 3 (blue) */ + { 0x19, 0x00 }, /* current for LED 2 (red) */ + { 0x1a, 0x00 }, /* current for LED 1 (green) */ }; /* Controller register lookup tables. */ @@ -198,7 +197,7 @@ static const uint8_t led_to_isc[] = { 0x15, 0x18, 0x15, 0x18 }; /* Scale 0-255 into max value */ static inline uint8_t scale_abs(int val, int max) { - return (val * max)/255; + return (val * max) / 255; } /* This is the overall brightness control. */ @@ -211,7 +210,7 @@ static uint8_t current[NUM_LEDS][3]; /* Scale 0-255 by brightness */ static inline uint8_t scale(int val, int max) { - return scale_abs((val * brightness)/255, max); + return scale_abs((val * brightness) / 255, max); } /* Helper function to set one LED color and remember it for later */ @@ -225,8 +224,8 @@ static void setrgb(int led, int red, int green, int blue) bank = led_to_isc[led]; i2c_lock(I2C_PORT_LIGHTBAR, 1); controller_write(ctrl, bank, scale(blue, MAX_BLUE)); - controller_write(ctrl, bank+1, scale(red, MAX_RED)); - controller_write(ctrl, bank+2, scale(green, MAX_GREEN)); + controller_write(ctrl, bank + 1, scale(red, MAX_RED)); + controller_write(ctrl, bank + 2, scale(green, MAX_GREEN)); i2c_lock(I2C_PORT_LIGHTBAR, 0); } @@ -310,12 +309,10 @@ void lb_on(void) i2c_lock(I2C_PORT_LIGHTBAR, 0); } -static const uint8_t dump_reglist[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0a, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, - 0x18, 0x19, 0x1a -}; +static const uint8_t dump_reglist[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, + 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, + 0x16, 0x17, 0x18, 0x19, 0x1a }; /* Helper for host command to dump controller registers */ void lb_hc_cmd_dump(struct ec_response_lightbar *out) @@ -323,8 +320,7 @@ void lb_hc_cmd_dump(struct ec_response_lightbar *out) int i; uint8_t reg; - BUILD_ASSERT(ARRAY_SIZE(dump_reglist) == - ARRAY_SIZE(out->dump.vals)); + BUILD_ASSERT(ARRAY_SIZE(dump_reglist) == ARRAY_SIZE(out->dump.vals)); for (i = 0; i < ARRAY_SIZE(dump_reglist); i++) { reg = dump_reglist[i]; -- cgit v1.2.1 From 373f3daa4e5e44c3350393b4b4995e7cc10f2312 Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Thu, 30 Jun 2022 16:07:46 +0800 Subject: power/mt8192: Do not exit hard off when ap idle To prevent system power on from POWER_G3 when ap idle (such as power off the system in recovery mode), set exit_hard_off to 0 for this condition. BUG=b:237230874 BRANCH=cherry TEST=make sure that system will not power on when power off in recovery mode. Signed-off-by: Tommy Chung Change-Id: I27697a030f3fdb128ea87b559add0a4a05399c56 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3737702 Reviewed-by: Ting Shen --- power/mt8192.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/power/mt8192.c b/power/mt8192.c index fc99bce5e0..c977d6f617 100644 --- a/power/mt8192.c +++ b/power/mt8192.c @@ -204,6 +204,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST); enum power_state power_chipset_init(void) { int exit_hard_off = 1; + uint32_t reset_flags = system_get_reset_flags(); /* Enable reboot / sleep control inputs from AP */ gpio_enable_interrupt(GPIO_AP_EC_WARM_RST_REQ); @@ -216,9 +217,10 @@ enum power_state power_chipset_init(void) CPRINTS("already in S0"); return POWER_S0; } - } else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) { + } else if ((reset_flags & EC_RESET_FLAG_AP_OFF) || + (reset_flags & EC_RESET_FLAG_AP_IDLE)) { exit_hard_off = 0; - } else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) && + } else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) && gpio_get_level(GPIO_AC_PRESENT)) { /* * If AC present, assume this is a wake-up by AC insert. -- cgit v1.2.1 From bb3a72287ff9b6a3cbbc69ea52f18fe92a26b720 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:52 -0600 Subject: chip/mec1322/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4547b506a73048e4b8e4affb04ca3fcf79460a0a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729318 Reviewed-by: Jeremy Bettis --- chip/mec1322/flash.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c index fac5b08d8f..d1f28baca2 100644 --- a/chip/mec1322/flash.c +++ b/chip/mec1322/flash.c @@ -51,7 +51,7 @@ int crec_flash_physical_read(int offset, int size, char *data) int crec_flash_physical_write(int offset, int size, const char *data) { int ret = EC_SUCCESS; - int i, write_size; + int i, write_size; if (entire_flash_locked) return EC_ERROR_ACCESS_DENIED; @@ -62,8 +62,7 @@ int crec_flash_physical_write(int offset, int size, const char *data) for (i = 0; i < size; i += write_size) { write_size = MIN((size - i), SPI_FLASH_MAX_WRITE_SIZE); - ret = spi_flash_write(offset + i, - write_size, + ret = spi_flash_write(offset + i, write_size, (uint8_t *)data + i); if (ret != EC_SUCCESS) break; @@ -99,7 +98,7 @@ int crec_flash_physical_erase(int offset, int size) int crec_flash_physical_get_protect(int bank) { return spi_flash_check_protect(bank * CONFIG_FLASH_BANK_SIZE, - CONFIG_FLASH_BANK_SIZE); + CONFIG_FLASH_BANK_SIZE); } /** @@ -153,8 +152,7 @@ uint32_t crec_flash_physical_get_protect_flags(void) */ uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -171,8 +169,9 @@ uint32_t crec_flash_physical_get_writable_flags(uint32_t cur_flags) wp_status = spi_flash_check_wp(); - if (wp_status == SPI_WP_NONE || (wp_status == SPI_WP_HARDWARE && - !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) + if (wp_status == SPI_WP_NONE || + (wp_status == SPI_WP_HARDWARE && + !(cur_flags & EC_FLASH_PROTECT_GPIO_ASSERTED))) ret = EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW; if (!entire_flash_locked) @@ -243,7 +242,7 @@ int crec_flash_physical_restore_state(void) */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) entire_flash_locked = prev->entire_flash_locked; -- cgit v1.2.1 From 8e49c60b085a77da0fbf4d61e0e817bcdfcd3303 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:49 -0600 Subject: zephyr/emul/tcpc/emul_tcpci_partner_drp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1773982d45519b94b640910b8e0854f4833aacc6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730705 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci_partner_drp.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_drp.c b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c index 6c3abdac78..da12a08b26 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_drp.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_drp.c @@ -28,10 +28,10 @@ LOG_MODULE_REGISTER(tcpci_drp_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); * @return TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled * @return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled */ -static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data, - const struct tcpci_emul_msg *msg) +static enum tcpci_partner_handler_res +tcpci_drp_emul_handle_sop_msg(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data, + const struct tcpci_emul_msg *msg) { struct tcpci_drp_emul_data *data = CONTAINER_OF(ext, struct tcpci_drp_emul_data, ext); @@ -46,9 +46,8 @@ static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg( case PD_DATA_REQUEST: if (common_data->power_role == PD_ROLE_SINK) { /* As sink we shouldn't accept request */ - tcpci_partner_send_control_msg(common_data, - PD_CTRL_REJECT, - 0); + tcpci_partner_send_control_msg( + common_data, PD_CTRL_REJECT, 0); return TCPCI_PARTNER_COMMON_MSG_HANDLED; } /* As source, let source handler to handle this */ @@ -66,8 +65,7 @@ static enum tcpci_partner_handler_res tcpci_drp_emul_handle_sop_msg( switch (PD_HEADER_TYPE(header)) { case PD_CTRL_PR_SWAP: tcpci_partner_send_control_msg(common_data, - PD_CTRL_ACCEPT, - 0); + PD_CTRL_ACCEPT, 0); data->in_pwr_swap = true; return TCPCI_PARTNER_COMMON_MSG_HANDLED; case PD_CTRL_PS_RDY: @@ -140,12 +138,12 @@ struct tcpci_partner_extension_ops tcpci_drp_emul_ops = { .connect = NULL, }; -struct tcpci_partner_extension *tcpci_drp_emul_init( - struct tcpci_drp_emul_data *data, - struct tcpci_partner_data *common_data, - enum pd_power_role power_role, - struct tcpci_partner_extension *src_ext, - struct tcpci_partner_extension *snk_ext) +struct tcpci_partner_extension * +tcpci_drp_emul_init(struct tcpci_drp_emul_data *data, + struct tcpci_partner_data *common_data, + enum pd_power_role power_role, + struct tcpci_partner_extension *src_ext, + struct tcpci_partner_extension *snk_ext) { struct tcpci_partner_extension *drp_ext = &data->ext; struct tcpci_src_emul_data *src_data = -- cgit v1.2.1 From 9647c36e323cfa845988a21f7696417286636b90 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:40 -0600 Subject: chip/host/persistence.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id230a7e4d784a504ade9ed8b84409e2cd5ceee67 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729151 Reviewed-by: Jeremy Bettis --- chip/host/persistence.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/chip/host/persistence.c b/chip/host/persistence.c index 44d60f1bb8..b2ab19f97e 100644 --- a/chip/host/persistence.c +++ b/chip/host/persistence.c @@ -60,9 +60,8 @@ static void get_storage_path(char *out) current = strchr(current, '/'); } - - sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s", - max_len, buf); + sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s", max_len, + buf); out[PATH_MAX - 1] = '\0'; ASSERT(sz <= max_len + max_prefix_len); @@ -81,8 +80,8 @@ FILE *get_persistent_storage(const char *tag, const char *mode) * be named 'bar_persist_foo' */ get_storage_path(buf); - snprintf(path, PATH_MAX - 1, "%.*s_%32s", - max_len + max_prefix_len, buf, tag); + snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, buf, + tag); path[PATH_MAX - 1] = '\0'; return fopen(path, mode); @@ -102,8 +101,8 @@ void remove_persistent_storage(const char *tag) ASSERT(strlen(tag) < 32); get_storage_path(buf); - snprintf(path, PATH_MAX - 1, "%.*s_%32s", - max_len + max_prefix_len, buf, tag); + snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, buf, + tag); path[PATH_MAX - 1] = '\0'; unlink(path); -- cgit v1.2.1 From 6cb2564a2a0584c666f67ba3a945dac17772fcbc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:22 -0600 Subject: driver/tcpm/anx74xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ided2361c208c09b5cb6bcb1ac2c6553d7834b062 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730074 Reviewed-by: Jeremy Bettis --- driver/tcpm/anx74xx.c | 154 ++++++++++++++++++++++++-------------------------- 1 file changed, 73 insertions(+), 81 deletions(-) diff --git a/driver/tcpm/anx74xx.c b/driver/tcpm/anx74xx.c index 1fc813c448..e9fd9f0ba6 100644 --- a/driver/tcpm/anx74xx.c +++ b/driver/tcpm/anx74xx.c @@ -30,23 +30,24 @@ #error "Please undefine PD 3.0. See b/159253723 for details" #endif -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) struct anx_state { - int polarity; - int vconn_en; - int mux_state; + int polarity; + int vconn_en; + int mux_state; #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - int prev_mode; + int prev_mode; #endif }; -#define clear_recvd_msg_int(port) do {\ - int reg, rv; \ +#define clear_recvd_msg_int(port) \ + do { \ + int reg, rv; \ rv = tcpc_read(port, ANX74XX_REG_RECVD_MSG_INT, ®); \ - if (!rv) \ - tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, \ - reg | 0x01); \ + if (!rv) \ + tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, \ + reg | 0x01); \ } while (0) static struct anx_state anx[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -233,8 +234,7 @@ static void anx74xx_tcpc_discharge_vbus(int port, int enable) static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT]; void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required) + mux_state_t mux_state, bool *ack_required) { int reg; int port = me->usb_port; @@ -296,11 +296,10 @@ static int anx74xx_tcpm_mux_enter_safe_mode(int port) if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, ®)) return EC_ERROR_UNKNOWN; - if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg | - ANX74XX_REG_MODE_TRANS)) + if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, + reg | ANX74XX_REG_MODE_TRANS)) return EC_ERROR_UNKNOWN; - return EC_SUCCESS; } @@ -311,11 +310,10 @@ static int anx74xx_tcpm_mux_exit_safe_mode(int port) if (mux_read(me, ANX74XX_REG_ANALOG_CTRL_2, ®)) return EC_ERROR_UNKNOWN; - if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, reg & - ~ANX74XX_REG_MODE_TRANS)) + if (mux_write(me, ANX74XX_REG_ANALOG_CTRL_2, + reg & ~ANX74XX_REG_MODE_TRANS)) return EC_ERROR_UNKNOWN; - return EC_SUCCESS; } @@ -357,12 +355,11 @@ static int anx74xx_tcpm_mux_exit(int port) return EC_SUCCESS; } - static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled) { int reg; const int aux_mask = ANX74XX_REG_AUX_SWAP_SET_CC2 | - ANX74XX_REG_AUX_SWAP_SET_CC1; + ANX74XX_REG_AUX_SWAP_SET_CC1; const struct usb_mux *me = &usb_muxes[port]; /* @@ -391,8 +388,7 @@ static int anx74xx_mux_aux_to_sbu(int port, int polarity, int enabled) return EC_SUCCESS; } -static int anx74xx_tcpm_mux_set(const struct usb_mux *me, - mux_state_t mux_state, +static int anx74xx_tcpm_mux_set(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { int ctrl5; @@ -448,7 +444,7 @@ static int anx74xx_tcpm_mux_set(const struct usb_mux *me, } else if (!mux_state) { return anx74xx_tcpm_mux_exit(port); } else { - return EC_ERROR_UNIMPLEMENTED; + return EC_ERROR_UNIMPLEMENTED; } /* @@ -504,8 +500,7 @@ static int anx74xx_init_analog(int port) /* Analog settings for chip */ rv |= tcpc_write(port, ANX74XX_REG_HPD_CONTROL, ANX74XX_REG_HPD_OP_MODE); - rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, - ANX74XX_REG_HPD_DEFAULT); + rv |= tcpc_write(port, ANX74XX_REG_HPD_CTRL_0, ANX74XX_REG_HPD_DEFAULT); if (rv) return rv; rv = tcpc_read(port, ANX74XX_REG_GPIO_CTRL_4_5, ®); @@ -526,9 +521,7 @@ static int anx74xx_init_analog(int port) } static int anx74xx_send_message(int port, uint16_t header, - const uint32_t *payload, - int type, - uint8_t len) + const uint32_t *payload, int type, uint8_t len) { int reg, rv = EC_SUCCESS; uint8_t *buf = NULL; @@ -537,12 +530,12 @@ static int anx74xx_send_message(int port, uint16_t header, /* Soft Reset Message type = 1101 and Number of Data Object = 0 */ if ((header & 0x700f) == 0x000d) { /* - * When sending soft reset, - * the Rx buffer of ANX3429 shall be clear - */ + * When sending soft reset, + * the Rx buffer of ANX3429 shall be clear + */ rv = tcpc_read(port, ANX74XX_REG_CTRL_FW, ®); - rv |= tcpc_write( - port, ANX74XX_REG_CTRL_FW, reg | CLEAR_RX_BUFFER); + rv |= tcpc_write(port, ANX74XX_REG_CTRL_FW, + reg | CLEAR_RX_BUFFER); if (rv) return EC_ERROR_UNKNOWN; tcpc_write(port, ANX74XX_REG_RECVD_MSG_INT, 0xFF); @@ -574,7 +567,8 @@ static int anx74xx_send_message(int port, uint16_t header, *buf); else rv = tcpc_write(port, - ANX74XX_REG_TX_START_ADDR_1 + i - 18, + ANX74XX_REG_TX_START_ADDR_1 + + i - 18, *buf); if (rv) { num_retry++; @@ -607,15 +601,13 @@ static int anx74xx_send_message(int port, uint16_t header, return rv; } -static int anx74xx_read_pd_obj(int port, - uint8_t *buf, - int plen) +static int anx74xx_read_pd_obj(int port, uint8_t *buf, int plen) { int rv = EC_SUCCESS, i; int reg, addr = ANX74XX_REG_PD_RX_DATA_OBJ; /* Read PD data objects from ANX */ - for (i = 0; i < plen ; i++) { + for (i = 0; i < plen; i++) { /* Register sequence changes for last two bytes, if * plen is greater than 26 */ @@ -664,7 +656,7 @@ static int anx74xx_check_cc_type(int cc_reg) } static int anx74xx_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int rv = EC_SUCCESS; int reg = 0; @@ -729,7 +721,6 @@ static int anx74xx_tcpm_select_rp_value(int port, int rp) return EC_SUCCESS; } - static int anx74xx_cc_software_ctrl(int port, int enable) { int rv; @@ -760,7 +751,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull) switch (pull) { case TYPEC_CC_RP: - /* Enable Rp */ + /* Enable Rp */ rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, ®); if (rv) return EC_ERROR_UNKNOWN; @@ -768,7 +759,7 @@ static int anx74xx_tcpm_set_cc(int port, int pull) rv |= tcpc_write(port, ANX74XX_REG_ANALOG_STATUS, reg); break; case TYPEC_CC_RD: - /* Enable Rd */ + /* Enable Rd */ rv |= tcpc_read(port, ANX74XX_REG_ANALOG_STATUS, ®); if (rv) return EC_ERROR_UNKNOWN; @@ -835,7 +826,7 @@ static int anx74xx_tcpm_set_vconn(int port, int enable) if (reg & ANX74XX_REG_REPLY_SOP_EN) { if (enable) { reg |= ANX74XX_REG_REPLY_SOP_1_EN | - ANX74XX_REG_REPLY_SOP_2_EN; + ANX74XX_REG_REPLY_SOP_2_EN; } else { reg &= ~(ANX74XX_REG_REPLY_SOP_1_EN | ANX74XX_REG_REPLY_SOP_2_EN); @@ -850,7 +841,8 @@ static int anx74xx_tcpm_set_vconn(int port, int enable) static int anx74xx_tcpm_set_msg_header(int port, int power_role, int data_role) { return tcpc_write(port, ANX74XX_REG_TX_AUTO_GOODCRC_1, - ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role, !!power_role)); + ANX74XX_REG_AUTO_GOODCRC_SET(!!data_role, + !!power_role)); } static int anx74xx_tcpm_set_rx_enable(int port, int enable) @@ -917,8 +909,7 @@ static int anx74xx_tcpm_get_message_raw(int port, uint32_t *payload, int *head) } static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, - const uint32_t *data) + uint16_t header, const uint32_t *data) { uint8_t len = 0; int ret = 0, reg = 0; @@ -929,37 +920,36 @@ static int anx74xx_tcpm_transmit(int port, enum tcpci_msg_type type, case TCPCI_MSG_SOP_PRIME: case TCPCI_MSG_SOP_PRIME_PRIME: len = PD_HEADER_CNT(header) * 4 + 2; - ret = anx74xx_send_message(port, header, - data, type, len); + ret = anx74xx_send_message(port, header, data, type, len); break; case TCPCI_MSG_TX_HARD_RESET: - /* Request HARD RESET */ + /* Request HARD RESET */ tcpc_read(port, ANX74XX_REG_TX_CTRL_1, ®); reg |= ANX74XX_REG_TX_HARD_RESET_REQ; ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg); - /*After Hard Reset, TCPM shall disable goodCRC*/ + /*After Hard Reset, TCPM shall disable goodCRC*/ anx74xx_tcpm_set_auto_good_crc(port, 0); break; case TCPCI_MSG_CABLE_RESET: - /* Request CABLE RESET */ + /* Request CABLE RESET */ tcpc_read(port, ANX74XX_REG_TX_CTRL_1, ®); reg |= ANX74XX_REG_TX_CABLE_RESET_REQ; ret = tcpc_write(port, ANX74XX_REG_TX_CTRL_1, reg); break; case TCPCI_MSG_TX_BIST_MODE_2: - /* Request BIST MODE 2 */ - reg = ANX74XX_REG_TX_BIST_START - | ANX74XX_REG_TX_BIXT_FOREVER | (0x02 << 4); + /* Request BIST MODE 2 */ + reg = ANX74XX_REG_TX_BIST_START | ANX74XX_REG_TX_BIXT_FOREVER | + (0x02 << 4); ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, reg); msleep(1); ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, - reg | ANX74XX_REG_TX_BIST_ENABLE); + reg | ANX74XX_REG_TX_BIST_ENABLE); msleep(30); tcpc_read(port, ANX74XX_REG_TX_BIST_CTRL, ®); ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, - reg | ANX74XX_REG_TX_BIST_STOP); + reg | ANX74XX_REG_TX_BIST_STOP); ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, - reg & (~ANX74XX_REG_TX_BIST_STOP)); + reg & (~ANX74XX_REG_TX_BIST_STOP)); ret = tcpc_write(port, ANX74XX_REG_TX_BIST_CTRL, 0); break; default: @@ -1006,7 +996,8 @@ void anx74xx_tcpc_alert(int port) /* Ensure we don't loop endlessly */ if (failed_attempts >= MAX_ALLOW_FAILED_RX_READS) { CPRINTF("C%d Cannot consume RX buffer after %d failed " - "attempts!", port, failed_attempts); + "attempts!", + port, failed_attempts); /* * The port is in a bad state, we don't want to consume * all EC resources so suspend the port for a little @@ -1084,7 +1075,8 @@ static int anx74xx_tcpm_init(int port) /* Initialize interrupt polarity */ reg = tcpc_config[port].flags & TCPC_FLAGS_ALERT_ACTIVE_HIGH ? - ANX74XX_REG_IRQ_POL_HIGH : ANX74XX_REG_IRQ_POL_LOW; + ANX74XX_REG_IRQ_POL_HIGH : + ANX74XX_REG_IRQ_POL_LOW; rv |= tcpc_write(port, ANX74XX_REG_IRQ_STATUS, reg); /* unmask interrupts */ @@ -1131,7 +1123,7 @@ static int anx74xx_tcpm_init(int port) } static int anx74xx_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) + struct ec_response_pd_chip_info_v1 *chip_info) { int rv = tcpci_get_chip_info(port, live, chip_info); int val; @@ -1171,34 +1163,34 @@ static int anx74xx_tcpm_release(int port) } const struct tcpm_drv anx74xx_tcpm_drv = { - .init = &anx74xx_tcpm_init, - .release = &anx74xx_tcpm_release, - .get_cc = &anx74xx_tcpm_get_cc, + .init = &anx74xx_tcpm_init, + .release = &anx74xx_tcpm_release, + .get_cc = &anx74xx_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &anx74xx_tcpm_check_vbus_level, + .check_vbus_level = &anx74xx_tcpm_check_vbus_level, #endif - .select_rp_value = &anx74xx_tcpm_select_rp_value, - .set_cc = &anx74xx_tcpm_set_cc, - .set_polarity = &anx74xx_tcpm_set_polarity, + .select_rp_value = &anx74xx_tcpm_select_rp_value, + .set_cc = &anx74xx_tcpm_set_cc, + .set_polarity = &anx74xx_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &anx74xx_tcpm_set_vconn, - .set_msg_header = &anx74xx_tcpm_set_msg_header, - .set_rx_enable = &anx74xx_tcpm_set_rx_enable, - .get_message_raw = &anx74xx_tcpm_get_message_raw, - .transmit = &anx74xx_tcpm_transmit, - .tcpc_alert = &anx74xx_tcpc_alert, + .set_vconn = &anx74xx_tcpm_set_vconn, + .set_msg_header = &anx74xx_tcpm_set_msg_header, + .set_rx_enable = &anx74xx_tcpm_set_rx_enable, + .get_message_raw = &anx74xx_tcpm_get_message_raw, + .transmit = &anx74xx_tcpm_transmit, + .tcpc_alert = &anx74xx_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &anx74xx_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &anx74xx_tcpc_discharge_vbus, #endif - .get_chip_info = &anx74xx_get_chip_info, + .get_chip_info = &anx74xx_get_chip_info, #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) && \ - defined(CONFIG_USB_PD_TCPC_LOW_POWER) - .drp_toggle = &anx74xx_tcpc_drp_toggle, - .enter_low_power_mode = &anx74xx_enter_low_power_mode, + defined(CONFIG_USB_PD_TCPC_LOW_POWER) + .drp_toggle = &anx74xx_tcpc_drp_toggle, + .enter_low_power_mode = &anx74xx_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC -- cgit v1.2.1 From 06960cd92867158b7024262a499e9f3e34e765ad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:08 -0600 Subject: board/vell/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ca9ec2366e89f318ad56bee9cf670077e841abe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729056 Reviewed-by: Jeremy Bettis --- board/vell/usbc_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/vell/usbc_config.h b/board/vell/usbc_config.h index 447c03efb3..cd539741cb 100644 --- a/board/vell/usbc_config.h +++ b/board/vell/usbc_config.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 4 +#define CONFIG_USB_PD_PORT_MAX_COUNT 4 enum usbc_port { USBC_PORT_C0 = 0, -- cgit v1.2.1 From 46d1b38dc567dd326e7acef745e262eb80f26ce4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:13 -0600 Subject: board/fluffy/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd32b96dfc3d8669667f716d839b0935ac14e538 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728375 Reviewed-by: Jeremy Bettis --- board/fluffy/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/fluffy/board.h b/board/fluffy/board.h index 75e9843b83..76faf9f7c5 100644 --- a/board/fluffy/board.h +++ b/board/fluffy/board.h @@ -29,13 +29,13 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_COUNT 1 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_COUNT 1 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_COUNT 2 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_COUNT 2 /* Optional features */ #define CONFIG_STM_HWTIMER32 @@ -48,7 +48,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" -- cgit v1.2.1 From 408056cbb5381ca90c90ca70d7f623d418124dc0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:24 -0600 Subject: common/usbc/usb_prl_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I550fc6b0a2dd74fcd57ac507f9ab756d2b449d2f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729792 Reviewed-by: Jeremy Bettis --- common/usbc/usb_prl_sm.c | 251 +++++++++++++++++++++-------------------------- 1 file changed, 114 insertions(+), 137 deletions(-) diff --git a/common/usbc/usb_prl_sm.c b/common/usbc/usb_prl_sm.c index 805e6dfcd8..cf8c0a9e07 100644 --- a/common/usbc/usb_prl_sm.c +++ b/common/usbc/usb_prl_sm.c @@ -33,8 +33,8 @@ #include "vpd_api.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -46,27 +46,25 @@ #undef DEBUG_PRINT_FLAG_NAMES #ifdef DEBUG_PRINT_FLAG_NAMES -__maybe_unused static void print_flag(const char *group, - int set_or_clear, +__maybe_unused static void print_flag(const char *group, int set_or_clear, int flag); -#define SET_FLAG(group, flags, flag) \ - do { \ - print_flag(group, 1, flag); \ - atomic_or(flags, (flag)); \ +#define SET_FLAG(group, flags, flag) \ + do { \ + print_flag(group, 1, flag); \ + atomic_or(flags, (flag)); \ } while (0) -#define CLR_FLAG(group, flags, flag) \ - do { \ - int before = *flags; \ - atomic_clear_bits(flags, (flag)); \ - if (*flags != before) \ - print_flag(group, 0, flag); \ +#define CLR_FLAG(group, flags, flag) \ + do { \ + int before = *flags; \ + atomic_clear_bits(flags, (flag)); \ + if (*flags != before) \ + print_flag(group, 0, flag); \ } while (0) #else #define SET_FLAG(group, flags, flag) atomic_or(flags, (flag)) #define CLR_FLAG(group, flags, flag) atomic_clear_bits(flags, (flag)) #endif - #define RCH_SET_FLAG(port, flag) SET_FLAG("RCH", &rch[port].flags, (flag)) #define RCH_CLR_FLAG(port, flag) CLR_FLAG("RCH", &rch[port].flags, (flag)) #define RCH_CHK_FLAG(port, flag) (rch[port].flags & (flag)) @@ -98,34 +96,34 @@ __maybe_unused static void print_flag(const char *group, * different meanings in each state machine. */ /* Flag to note message transmission completed */ -#define PRL_FLAGS_TX_COMPLETE BIT(0) +#define PRL_FLAGS_TX_COMPLETE BIT(0) /* Flag to note that PRL requested to set SINK_NG CC state */ -#define PRL_FLAGS_SINK_NG BIT(1) +#define PRL_FLAGS_SINK_NG BIT(1) /* Flag to note PRL waited for SINK_OK CC state before transmitting */ -#define PRL_FLAGS_WAIT_SINK_OK BIT(2) +#define PRL_FLAGS_WAIT_SINK_OK BIT(2) /* Flag to note transmission error occurred */ -#define PRL_FLAGS_TX_ERROR BIT(3) +#define PRL_FLAGS_TX_ERROR BIT(3) /* Flag to note PE triggered a hard reset */ -#define PRL_FLAGS_PE_HARD_RESET BIT(4) +#define PRL_FLAGS_PE_HARD_RESET BIT(4) /* Flag to note hard reset has completed */ -#define PRL_FLAGS_HARD_RESET_COMPLETE BIT(5) +#define PRL_FLAGS_HARD_RESET_COMPLETE BIT(5) /* Flag to note port partner sent a hard reset */ #define PRL_FLAGS_PORT_PARTNER_HARD_RESET BIT(6) /* * Flag to note a message transmission has been requested. It is only cleared * when we send the message to the TCPC layer. */ -#define PRL_FLAGS_MSG_XMIT BIT(7) +#define PRL_FLAGS_MSG_XMIT BIT(7) /* Flag to note a message was received */ -#define PRL_FLAGS_MSG_RECEIVED BIT(8) +#define PRL_FLAGS_MSG_RECEIVED BIT(8) /* Flag to note aborting current TX message, not currently set */ -#define PRL_FLAGS_ABORT BIT(9) +#define PRL_FLAGS_ABORT BIT(9) /* Flag to note current TX message uses chunking */ -#define PRL_FLAGS_CHUNKING BIT(10) +#define PRL_FLAGS_CHUNKING BIT(10) struct bit_name { - int value; - const char *name; + int value; + const char *name; }; static __const_data const struct bit_name flag_bit_names[] = { @@ -136,17 +134,15 @@ static __const_data const struct bit_name flag_bit_names[] = { { PRL_FLAGS_PE_HARD_RESET, "PRL_FLAGS_PE_HARD_RESET" }, { PRL_FLAGS_HARD_RESET_COMPLETE, "PRL_FLAGS_HARD_RESET_COMPLETE" }, { PRL_FLAGS_PORT_PARTNER_HARD_RESET, - "PRL_FLAGS_PORT_PARTNER_HARD_RESET" }, + "PRL_FLAGS_PORT_PARTNER_HARD_RESET" }, { PRL_FLAGS_MSG_XMIT, "PRL_FLAGS_MSG_XMIT" }, { PRL_FLAGS_MSG_RECEIVED, "PRL_FLAGS_MSG_RECEIVED" }, { PRL_FLAGS_ABORT, "PRL_FLAGS_ABORT" }, { PRL_FLAGS_CHUNKING, "PRL_FLAGS_CHUNKING" }, }; -__maybe_unused static void print_bits(const char *group, - const char *desc, - int value, - const struct bit_name *names, +__maybe_unused static void print_bits(const char *group, const char *desc, + int value, const struct bit_name *names, int names_size) { int i; @@ -162,8 +158,7 @@ __maybe_unused static void print_bits(const char *group, CPRINTF("\n"); } -__maybe_unused static void print_flag(const char *group, - int set_or_clear, +__maybe_unused static void print_flag(const char *group, int set_or_clear, int flag) { print_bits(group, set_or_clear ? "Set" : "Clr", flag, flag_bit_names, @@ -238,7 +233,7 @@ enum usb_tch_state { TCH_REPORT_ERROR, }; -static const char * const prl_tx_state_names[] = { +static const char *const prl_tx_state_names[] = { [PRL_TX_PHY_LAYER_RESET] = "PRL_TX_PHY_LAYER_RESET", [PRL_TX_WAIT_FOR_MESSAGE_REQUEST] = "PRL_TX_WAIT_FOR_MESSAGE_REQUEST", [PRL_TX_LAYER_RESET_FOR_TRANSMIT] = "PRL_TX_LAYER_RESET_FOR_TRANSMIT", @@ -250,18 +245,18 @@ static const char * const prl_tx_state_names[] = { [PRL_TX_DISCARD_MESSAGE] = "PRL_TX_DISCARD_MESSAGE", }; -static const char * const prl_hr_state_names[] = { +static const char *const prl_hr_state_names[] = { [PRL_HR_WAIT_FOR_REQUEST] = "PRL_HR_WAIT_FOR_REQUEST", [PRL_HR_RESET_LAYER] = "PRL_HR_RESET_LAYER", - [PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] - = "PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE", - [PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] - = "PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE", + [PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE] = + "PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE", + [PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE] = + "PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE", }; -__maybe_unused static const char * const rch_state_names[] = { - [RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] - = "RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER", +__maybe_unused static const char *const rch_state_names[] = { + [RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER] = + "RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER", [RCH_PASS_UP_MESSAGE] = "RCH_PASS_UP_MESSAGE", [RCH_PROCESSING_EXTENDED_MESSAGE] = "RCH_PROCESSING_EXTENDED_MESSAGE", [RCH_REQUESTING_CHUNK] = "RCH_REQUESTING_CHUNK", @@ -269,11 +264,11 @@ __maybe_unused static const char * const rch_state_names[] = { [RCH_REPORT_ERROR] = "RCH_REPORT_ERROR", }; -__maybe_unused static const char * const tch_state_names[] = { - [TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] - = "TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE", - [TCH_WAIT_FOR_TRANSMISSION_COMPLETE] - = "TCH_WAIT_FOR_TRANSMISSION_COMPLETE", +__maybe_unused static const char *const tch_state_names[] = { + [TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE] = + "TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE", + [TCH_WAIT_FOR_TRANSMISSION_COMPLETE] = + "TCH_WAIT_FOR_TRANSMISSION_COMPLETE", [TCH_CONSTRUCT_CHUNKED_MESSAGE] = "TCH_CONSTRUCT_CHUNKED_MESSAGE", [TCH_SENDING_CHUNKED_MESSAGE] = "TCH_SENDING_CHUNKED_MESSAGE", [TCH_WAIT_CHUNK_REQUEST] = "TCH_WAIT_CHUNK_REQUEST", @@ -380,12 +375,12 @@ GEN_NOT_SUPPORTED(PRL_TX_SNK_START_AMS); GEN_NOT_SUPPORTED(RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER); #define RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER \ - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER_NOT_SUPPORTED GEN_NOT_SUPPORTED(RCH_PASS_UP_MESSAGE); #define RCH_PASS_UP_MESSAGE RCH_PASS_UP_MESSAGE_NOT_SUPPORTED GEN_NOT_SUPPORTED(RCH_PROCESSING_EXTENDED_MESSAGE); #define RCH_PROCESSING_EXTENDED_MESSAGE \ - RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED + RCH_PROCESSING_EXTENDED_MESSAGE_NOT_SUPPORTED GEN_NOT_SUPPORTED(RCH_REQUESTING_CHUNK); #define RCH_REQUESTING_CHUNK RCH_REQUESTING_CHUNK_NOT_SUPPORTED GEN_NOT_SUPPORTED(RCH_WAITING_CHUNK); @@ -395,13 +390,13 @@ GEN_NOT_SUPPORTED(RCH_REPORT_ERROR); GEN_NOT_SUPPORTED(TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE); #define TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE \ - TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED + TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE_NOT_SUPPORTED GEN_NOT_SUPPORTED(TCH_WAIT_FOR_TRANSMISSION_COMPLETE); #define TCH_WAIT_FOR_TRANSMISSION_COMPLETE \ - TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED + TCH_WAIT_FOR_TRANSMISSION_COMPLETE_NOT_SUPPORTED GEN_NOT_SUPPORTED(TCH_CONSTRUCT_CHUNKED_MESSAGE); #define TCH_CONSTRUCT_CHUNKED_MESSAGE \ - TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED + TCH_CONSTRUCT_CHUNKED_MESSAGE_NOT_SUPPORTED GEN_NOT_SUPPORTED(TCH_SENDING_CHUNKED_MESSAGE); #define TCH_SENDING_CHUNKED_MESSAGE TCH_SENDING_CHUNKED_MESSAGE_NOT_SUPPORTED GEN_NOT_SUPPORTED(TCH_WAIT_CHUNK_REQUEST); @@ -435,7 +430,7 @@ static void print_current_prl_tx_state(const int port) { if (prl_debug_level >= DEBUG_LEVEL_3) CPRINTS("C%d: %s", port, - prl_tx_state_names[prl_tx_get_state(port)]); + prl_tx_state_names[prl_tx_get_state(port)]); } /* Set the hard reset statemachine to a new state. */ @@ -456,7 +451,7 @@ static void print_current_prl_hr_state(const int port) { if (prl_debug_level >= DEBUG_LEVEL_3) CPRINTS("C%d: %s", port, - prl_hr_state_names[prl_hr_get_state(port)]); + prl_hr_state_names[prl_hr_get_state(port)]); } /* Set the chunked Rx statemachine to a new state. */ @@ -477,8 +472,7 @@ test_export_static enum usb_rch_state rch_get_state(const int port) static void print_current_rch_state(const int port) { if (prl_debug_level >= DEBUG_LEVEL_3) - CPRINTS("C%d: %s", port, - rch_state_names[rch_get_state(port)]); + CPRINTS("C%d: %s", port, rch_state_names[rch_get_state(port)]); } #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ @@ -503,12 +497,10 @@ test_export_static enum usb_tch_state tch_get_state(const int port) static void print_current_tch_state(const int port) { if (prl_debug_level >= DEBUG_LEVEL_3) - CPRINTS("C%d: %s", port, - tch_state_names[tch_get_state(port)]); + CPRINTS("C%d: %s", port, tch_state_names[tch_get_state(port)]); } #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ - timestamp_t prl_get_tcpc_tx_success_ts(int port) { return tcpc_tx_success_ts[port]; @@ -605,9 +597,8 @@ bool prl_is_busy(int port) { #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES return rch_get_state(port) != - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER || - tch_get_state(port) != - TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE; + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER || + tch_get_state(port) != TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE; #else return false; #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ @@ -626,9 +617,8 @@ void prl_hard_reset_complete(int port) task_wake(PD_PORT_TO_TASK_ID(port)); } -void prl_send_ctrl_msg(int port, - enum tcpci_msg_type type, - enum pd_ctrl_msg_type msg) +void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, + enum pd_ctrl_msg_type msg) { pdmsg[port].xmit_type = type; pdmsg[port].msg_type = msg; @@ -646,9 +636,8 @@ void prl_send_ctrl_msg(int port, task_wake(PD_PORT_TO_TASK_ID(port)); } -void prl_send_data_msg(int port, - enum tcpci_msg_type type, - enum pd_data_msg_type msg) +void prl_send_data_msg(int port, enum tcpci_msg_type type, + enum pd_data_msg_type msg) { pdmsg[port].xmit_type = type; pdmsg[port].msg_type = msg; @@ -666,9 +655,8 @@ void prl_send_data_msg(int port, } #ifdef CONFIG_USB_PD_EXTENDED_MESSAGES -void prl_send_ext_data_msg(int port, - enum tcpci_msg_type type, - enum pd_ext_msg_type msg) +void prl_send_ext_data_msg(int port, enum tcpci_msg_type type, + enum pd_ext_msg_type msg) { pdmsg[port].xmit_type = type; pdmsg[port].msg_type = msg; @@ -736,11 +724,9 @@ void prl_run(int port, int evt, int en) * reset. */ if (prl_hr_get_state(port) == PRL_HR_WAIT_FOR_REQUEST) { - /* Run Protocol Layer Message Reception */ prl_rx_wait_for_phy_message(port, evt); - if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) { /* * Run RX Chunked state machine after prl_rx. @@ -772,8 +758,7 @@ void prl_run(int port, int evt, int en) } } -void prl_set_rev(int port, enum tcpci_msg_type type, - enum pd_rev_type rev) +void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev) { /* We only store revisions for SOP* types. */ ASSERT(type < NUM_SOP_STAR_TYPES); @@ -814,7 +799,7 @@ static void prl_copy_msg_to_buffer(int port) /* Copy message to chunked buffer */ memset((uint8_t *)pdmsg[port].tx_chk_buf, 0, CHK_BUF_SIZE_BYTES); memcpy((uint8_t *)pdmsg[port].tx_chk_buf, (uint8_t *)tx_emsg[port].buf, - tx_emsg[port].len); + tx_emsg[port].len); /* * Pad length to 4-byte boundary and * convert to number of 32-bit objects. @@ -828,8 +813,8 @@ static void prl_copy_msg_to_buffer(int port) static __maybe_unused int pdmsg_xmit_type_is_rev30(const int port) { if (IS_ENABLED(CONFIG_USB_PD_REV30)) - return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) - && (prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30)); + return ((pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES) && + (prl_get_rev(port, pdmsg[port].xmit_type) == PD_REV30)); else return 0; } @@ -846,8 +831,7 @@ static void prl_tx_phy_layer_reset_entry(const int port) { print_current_prl_tx_state(port); - if (IS_ENABLED(CONFIG_USB_CTVPD) - || IS_ENABLED(CONFIG_USB_VPD)) { + if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD)) { vpd_rx_enable(pd_is_connected(port)); } else { /* Note: can't clear PHY messages due to TCPC architecture */ @@ -884,7 +868,7 @@ static void prl_tx_wait_for_message_request_run(const int port) if (IS_ENABLED(CONFIG_USB_PD_REV30) && is_sop_rev30(port) && pe_in_local_ams(port)) { if (PRL_TX_CHK_FLAG(port, PRL_FLAGS_SINK_NG | - PRL_FLAGS_WAIT_SINK_OK)) { + PRL_FLAGS_WAIT_SINK_OK)) { /* * If we are already in an AMS then allow the * multi-message AMS to continue, even if we @@ -915,7 +899,7 @@ static void prl_tx_wait_for_message_request_run(const int port) * Soft Reset Message Message pending */ if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) && - (tx_emsg[port].len == 0)) { + (tx_emsg[port].len == 0)) { set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT); } /* @@ -1063,23 +1047,21 @@ static uint32_t get_sop_star_header(const int port) #endif /* SOP vs SOP'/SOP" headers are different. Replace fields as needed */ - return PD_HEADER( - pdmsg[port].msg_type, - is_sop_packet ? - pd_get_power_role(port) : tc_get_cable_plug(port), - is_sop_packet ? - pd_get_data_role(port) : 0, - prl_tx[port].msg_id_counter[pdmsg[port].xmit_type], - pdmsg[port].data_objs, - pdmsg[port].rev[pdmsg[port].xmit_type], - ext); + return PD_HEADER(pdmsg[port].msg_type, + is_sop_packet ? pd_get_power_role(port) : + tc_get_cable_plug(port), + is_sop_packet ? pd_get_data_role(port) : 0, + prl_tx[port].msg_id_counter[pdmsg[port].xmit_type], + pdmsg[port].data_objs, + pdmsg[port].rev[pdmsg[port].xmit_type], ext); } static void prl_tx_construct_message(const int port) { /* The header is unused for hard reset, etc. */ const uint32_t header = pdmsg[port].xmit_type < NUM_SOP_STAR_TYPES ? - get_sop_star_header(port) : 0; + get_sop_star_header(port) : + 0; /* Save SOP* so the correct msg_id_counter can be incremented */ prl_tx[port].last_xmit_type = pdmsg[port].xmit_type; @@ -1199,7 +1181,7 @@ static void prl_tx_src_pending_run(const int port) * SinkTxTimer timeout */ if ((tx_emsg[port].len == 0) && - (pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) { + (pdmsg[port].msg_type == PD_CTRL_SOFT_RESET)) { set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT); } /* Message pending (except Soft Reset) & @@ -1259,7 +1241,7 @@ static void prl_tx_snk_pending_run(const int port) * Rp = SinkTxOk */ if ((pdmsg[port].msg_type == PD_CTRL_SOFT_RESET) && - (tx_emsg[port].len == 0)) { + (tx_emsg[port].len == 0)) { set_state_prl_tx(port, PRL_TX_LAYER_RESET_FOR_TRANSMIT); } /* @@ -1305,7 +1287,7 @@ static void prl_hr_wait_for_request_entry(const int port) static void prl_hr_wait_for_request_run(const int port) { if (PRL_HR_CHK_FLAG(port, PRL_FLAGS_PE_HARD_RESET | - PRL_FLAGS_PORT_PARTNER_HARD_RESET)) + PRL_FLAGS_PORT_PARTNER_HARD_RESET)) set_state_prl_hr(port, PRL_HR_RESET_LAYER); } @@ -1332,8 +1314,7 @@ static void prl_hr_reset_layer_entry(const int port) } /* Disable RX */ - if (IS_ENABLED(CONFIG_USB_CTVPD) || - IS_ENABLED(CONFIG_USB_VPD)) + if (IS_ENABLED(CONFIG_USB_CTVPD) || IS_ENABLED(CONFIG_USB_VPD)) vpd_rx_enable(0); else tcpm_set_rx_enable(port, 0); @@ -1396,8 +1377,7 @@ static void prl_hr_wait_for_phy_hard_reset_complete_entry(const int port) print_current_prl_hr_state(port); /* Start HardResetCompleteTimer */ - pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE, - PD_T_PS_HARD_RESET); + pd_timer_enable(port, PR_TIMER_HARD_RESET_COMPLETE, PD_T_PS_HARD_RESET); } static void prl_hr_wait_for_phy_hard_reset_complete_run(const int port) @@ -1455,11 +1435,11 @@ static void copy_chunk_to_ext(int port) { /* Calculate number of bytes */ pdmsg[port].num_bytes_received = - (PD_HEADER_CNT(rx_emsg[port].header) * 4); + (PD_HEADER_CNT(rx_emsg[port].header) * 4); /* Copy chunk into extended message */ memcpy((uint8_t *)rx_emsg[port].buf, (uint8_t *)pdmsg[port].rx_chk_buf, - pdmsg[port].num_bytes_received); + pdmsg[port].num_bytes_received); /* Set extended message length */ rx_emsg[port].len = pdmsg[port].num_bytes_received; @@ -1491,10 +1471,10 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port) * Are we communicating with a PD3.0 device and is * this an extended message? */ - if (pdmsg_xmit_type_is_rev30(port) - && PD_HEADER_EXT(rx_emsg[port].header)) { + if (pdmsg_xmit_type_is_rev30(port) && + PD_HEADER_EXT(rx_emsg[port].header)) { uint16_t exhdr = - GET_EXT_HEADER(*pdmsg[port].rx_chk_buf); + GET_EXT_HEADER(*pdmsg[port].rx_chk_buf); uint8_t chunked = PD_EXT_HEADER_CHUNKED(exhdr); /* @@ -1502,7 +1482,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port) * (Chunking = 1 & Chunked = 1) */ if ((RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) && - chunked) { + chunked) { /* * RCH_Processing_Extended_Message first chunk * entry processing embedded here @@ -1524,7 +1504,7 @@ static void rch_wait_for_message_from_protocol_layer_run(const int port) * (Chunking = 0 & Chunked = 0)) */ else if (!RCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING) && - !chunked) { + !chunked) { /* Copy chunk to extended buffer */ copy_chunk_to_ext(port); set_state_rch(port, RCH_PASS_UP_MESSAGE); @@ -1602,8 +1582,8 @@ static void rch_processing_extended_message_run(const int port) byte_num = PD_MAX_EXTENDED_MSG_CHUNK_LEN; /* Make sure extended message buffer does not overflow */ - if (pdmsg[port].num_bytes_received + - byte_num > EXTENDED_BUFFER_SIZE) { + if (pdmsg[port].num_bytes_received + byte_num > + EXTENDED_BUFFER_SIZE) { rch[port].error = ERR_RCH_CHUNKED; set_state_rch(port, RCH_REPORT_ERROR); return; @@ -1612,9 +1592,8 @@ static void rch_processing_extended_message_run(const int port) /* Append data */ /* Add 2 to chk_buf to skip over extended message header */ memcpy(((uint8_t *)rx_emsg[port].buf + - pdmsg[port].num_bytes_received), - (uint8_t *)pdmsg[port].rx_chk_buf + 2, - byte_num); + pdmsg[port].num_bytes_received), + (uint8_t *)pdmsg[port].rx_chk_buf + 2, byte_num); /* increment chunk number expected */ pdmsg[port].chunk_number_expected++; /* adjust num bytes received */ @@ -1623,7 +1602,7 @@ static void rch_processing_extended_message_run(const int port) /* Was that the last chunk? */ if (pdmsg[port].num_bytes_received >= data_size) { rx_emsg[port].len = pdmsg[port].num_bytes_received; - /* Pass Message to Policy Engine */ + /* Pass Message to Policy Engine */ set_state_rch(port, RCH_PASS_UP_MESSAGE); } /* @@ -1652,11 +1631,11 @@ static void rch_requesting_chunk_entry(const int port) * Send Chunk Request to Protocol Layer * with chunk number = Chunk_Number_Expected */ - pdmsg[port].tx_chk_buf[0] = PD_EXT_HEADER( - pdmsg[port].chunk_number_expected, - 1, /* Request Chunk */ - 0 /* Data Size */ - ); + pdmsg[port].tx_chk_buf[0] = + PD_EXT_HEADER(pdmsg[port].chunk_number_expected, 1, /* Request + Chunk */ + 0 /* Data Size */ + ); pdmsg[port].data_objs = 1; pdmsg[port].ext = 1; @@ -1827,16 +1806,15 @@ static void tch_wait_for_message_request_from_pe_run(const int port) * Discard the Message */ if (rch_get_state(port) != - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) { + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER) { tch[port].error = ERR_TCH_XMIT; set_state_tch(port, TCH_REPORT_ERROR); } else { /* * Extended Message Request & Chunking */ - if (pdmsg_xmit_type_is_rev30(port) - && pdmsg[port].ext - && TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) { + if (pdmsg_xmit_type_is_rev30(port) && pdmsg[port].ext && + TCH_CHK_FLAG(port, PRL_FLAGS_CHUNKING)) { /* * NOTE: TCH_Prepare_To_Send_Chunked_Message * embedded here. @@ -1855,7 +1833,8 @@ static void tch_wait_for_message_request_from_pe_run(const int port) /* Pass Message to Protocol Layer */ PRL_TX_SET_FLAG(port, PRL_FLAGS_MSG_XMIT); - set_state_tch(port, + set_state_tch( + port, TCH_WAIT_FOR_TRANSMISSION_COMPLETE); } } @@ -1900,7 +1879,7 @@ static void tch_wait_for_transmission_complete_run(const int port) * the tx message was sent successfully. */ if (TCH_CHK_FLAG(port, PRL_FLAGS_MSG_RECEIVED) && - prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) { + prl_tx[port].xmit_status != TCPC_TX_COMPLETE_SUCCESS) { TCH_CLR_FLAG(port, PRL_FLAGS_MSG_RECEIVED); set_state_tch(port, TCH_MESSAGE_RECEIVED); return; @@ -1937,8 +1916,9 @@ static void tch_construct_chunked_message_entry(const int port) num = PD_MAX_EXTENDED_MSG_CHUNK_LEN; /* Set the chunks extended header */ - *ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send, - 0, /* Chunk Request */ + *ext_hdr = PD_EXT_HEADER(pdmsg[port].chunk_number_to_send, 0, /* Chunk + Request + */ tx_emsg[port].len); /* Copy the message chunk into chk_buf */ @@ -2036,7 +2016,8 @@ static void tch_wait_chunk_request_run(const int port) */ if (PD_EXT_HEADER_CHUNK_NUM(exthdr) == pdmsg[port].chunk_number_to_send) { - set_state_tch(port, + set_state_tch( + port, TCH_CONSTRUCT_CHUNKED_MESSAGE); } /* @@ -2111,8 +2092,6 @@ static void tch_message_sent_entry(const int port) return; } - - set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE); } @@ -2136,7 +2115,6 @@ static void tch_report_error_entry(const int port) return; } - set_state_tch(port, TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE); } #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ @@ -2176,7 +2154,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt) /* dump received packet content (only dump ping at debug level MAX) */ if ((prl_debug_level >= DEBUG_LEVEL_2 && type != PD_CTRL_PING) || - prl_debug_level >= DEBUG_LEVEL_3) { + prl_debug_level >= DEBUG_LEVEL_3) { int p; ccprintf("C%d: RECV %04x/%d ", port, header, cnt); @@ -2189,8 +2167,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt) * Ignore messages sent to the cable from our * port partner if we aren't Vconn powered device. */ - if (!IS_ENABLED(CONFIG_USB_CTVPD) && - !IS_ENABLED(CONFIG_USB_VPD) && + if (!IS_ENABLED(CONFIG_USB_CTVPD) && !IS_ENABLED(CONFIG_USB_VPD) && PD_HEADER_GET_SOP(header) != TCPCI_MSG_SOP && PD_HEADER_PROLE(header) == PD_PLUG_FROM_DFP_UFP) return; @@ -2224,9 +2201,9 @@ static void prl_rx_wait_for_phy_message(const int port, int evt) if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES)) { set_state_rch(port, - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER); + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER); set_state_tch(port, - TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE); + TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE); } /* @@ -2286,7 +2263,7 @@ static void prl_rx_wait_for_phy_message(const int port, int evt) * tch_wait_for_message_request_from_pe has been run */ else if (tch_get_state(port) != - TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE || + TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE || TCH_CHK_FLAG(port, PRL_FLAGS_MSG_XMIT)) { /* NOTE: RTR_TX_CHUNKS State embedded here. */ /* -- cgit v1.2.1 From 5a23e14e7c2cb0561e24a1108fa09019cd64a164 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:03 -0600 Subject: zephyr/shim/include/battery_enum.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I60f02c4fa9b35d7bd64a9a5f577814a6e341b3bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730565 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/battery_enum.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/include/battery_enum.h b/zephyr/shim/include/battery_enum.h index 7497edea0b..0ee36a8aa8 100644 --- a/zephyr/shim/include/battery_enum.h +++ b/zephyr/shim/include/battery_enum.h @@ -8,16 +8,16 @@ "included in all zephyr builds automatically" #endif -#define BATTERY_ENUM(val) DT_CAT(BATTERY_, val) +#define BATTERY_ENUM(val) DT_CAT(BATTERY_, val) #define BATTERY_TYPE(id) BATTERY_ENUM(DT_STRING_UPPER_TOKEN(id, enum_name)) -#define BATTERY_TYPE_WITH_COMMA(id) BATTERY_TYPE(id), +#define BATTERY_TYPE_WITH_COMMA(id) BATTERY_TYPE(id), /* This produces a list of BATTERY_ identifiers */ enum battery_type { #if DT_HAS_COMPAT_STATUS_OKAY(battery_smart) DT_FOREACH_STATUS_OKAY(battery_smart, BATTERY_TYPE_WITH_COMMA) #endif - BATTERY_TYPE_COUNT, + BATTERY_TYPE_COUNT, }; #undef BATTERY_TYPE_WITH_COMMA -- cgit v1.2.1 From c11084fd61e0100c64cc00199f725a6c21ed80b4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:18 -0600 Subject: driver/temp_sensor/thermistor_ncp15wb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e84444da701af11f80643654dfcf3ee1fe57aef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729877 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/thermistor_ncp15wb.c | 44 +++++++++++++++++---------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/driver/temp_sensor/thermistor_ncp15wb.c b/driver/temp_sensor/thermistor_ncp15wb.c index dba06ee326..3cc05790d9 100644 --- a/driver/temp_sensor/thermistor_ncp15wb.c +++ b/driver/temp_sensor/thermistor_ncp15wb.c @@ -15,30 +15,30 @@ * For 50C through 100C, use linear interpolation from discreet points * in table below. For temps < 50C, use a simplified linear function. */ -#define ADC_DISCREET_RANGE_START_TEMP 50 +#define ADC_DISCREET_RANGE_START_TEMP 50 /* 10 bit ADC result corresponding to START_TEMP */ -#define ADC_DISCREET_RANGE_START_RESULT 407 +#define ADC_DISCREET_RANGE_START_RESULT 407 -#define ADC_DISCREET_RANGE_LIMIT_TEMP 100 +#define ADC_DISCREET_RANGE_LIMIT_TEMP 100 /* 10 bit ADC result corresponding to LIMIT_TEMP */ -#define ADC_DISCREET_RANGE_LIMIT_RESULT 107 +#define ADC_DISCREET_RANGE_LIMIT_RESULT 107 /* Table entries in steppings of 5C */ -#define ADC_DISCREET_RANGE_STEP 5 +#define ADC_DISCREET_RANGE_STEP 5 /* Discreet range ADC results (9 bit) per temperature, in 5 degree steps */ static const uint8_t adc_result[] = { - 203, /* 50 C */ - 178, /* 55 C */ - 157, /* 60 C */ - 138, /* 65 C */ - 121, /* 70 C */ - 106, /* 75 C */ - 93, /* 80 C */ - 81, /* 85 C */ - 70, /* 90 C */ - 61, /* 95 C */ - 53, /* 100 C */ + 203, /* 50 C */ + 178, /* 55 C */ + 157, /* 60 C */ + 138, /* 65 C */ + 121, /* 70 C */ + 106, /* 75 C */ + 93, /* 80 C */ + 81, /* 85 C */ + 70, /* 90 C */ + 61, /* 95 C */ + 53, /* 100 C */ }; /* @@ -46,8 +46,9 @@ static const uint8_t adc_result[] = { * to 50C, the temperature curve is roughly linear, so we don't need to include * data points in our table. */ -#define adc_to_temp(result) (ADC_DISCREET_RANGE_START_TEMP - \ - (((result) - ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32) +#define adc_to_temp(result) \ + (ADC_DISCREET_RANGE_START_TEMP - \ + (((result)-ADC_DISCREET_RANGE_START_RESULT) * 3 + 16) / 32) /* Convert ADC result (10 bit) to temperature in celsius */ int ncp15wb_calculate_temp(uint16_t adc) @@ -72,8 +73,7 @@ int ncp15wb_calculate_temp(uint16_t adc) tail = ARRAY_SIZE(adc_result) - 1; while (head != tail) { mid = (head + tail) / 2; - if (adc_result[mid] >= adc && - adc_result[mid+1] < adc) + if (adc_result[mid] >= adc && adc_result[mid + 1] < adc) break; if (adc_result[mid] > adc) head = mid + 1; @@ -85,7 +85,9 @@ int ncp15wb_calculate_temp(uint16_t adc) if (head != tail) { delta = adc_result[mid] - adc_result[mid + 1]; step = ((adc_result[mid] - adc) * - ADC_DISCREET_RANGE_STEP + delta / 2) / delta; + ADC_DISCREET_RANGE_STEP + + delta / 2) / + delta; } else { /* Edge case where adc = max */ mid = head; -- cgit v1.2.1 From 922ffdae159d99736aff49ea8a5eef5e39df124e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:40 -0600 Subject: driver/led/mp3385.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59a10352b491bd2ca1069c26c009b5dc3a625eeb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730001 Reviewed-by: Jeremy Bettis --- driver/led/mp3385.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/led/mp3385.h b/driver/led/mp3385.h index bdb5dac0ae..68d408217a 100644 --- a/driver/led/mp3385.h +++ b/driver/led/mp3385.h @@ -27,7 +27,7 @@ void mp3385_board_init(void); int mp3385_set_config(int offset, int data); #ifndef MP3385_POWER_BACKLIGHT_DELAY -#define MP3385_POWER_BACKLIGHT_DELAY (15*MSEC) +#define MP3385_POWER_BACKLIGHT_DELAY (15 * MSEC) #endif void mp3385_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From fd47cc2771a7367d3988a7468fb82e8434f91141 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:44 -0600 Subject: board/nightfury/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d17a01ce92f5700c569b9d94daa99d9b356e7e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728749 Reviewed-by: Jeremy Bettis --- board/nightfury/led.c | 76 +++++++++++++++++++++++++++------------------------ 1 file changed, 40 insertions(+), 36 deletions(-) diff --git a/board/nightfury/led.c b/board/nightfury/led.c index dce39acfd6..603f69195f 100644 --- a/board/nightfury/led.c +++ b/board/nightfury/led.c @@ -12,8 +12,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 1; @@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100; /* Nightfury : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -55,12 +58,11 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } - if (color == EC_LED_COLOR_BLUE) - { + if (color == EC_LED_COLOR_BLUE) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL); @@ -74,15 +76,14 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; } /* Battery leds must be turn off when blue led is on * because Nightfury has 3-in-1 led. */ - if(!gpio_get_level(GPIO_PWR_LED_BLUE_L)) - { + if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); return; @@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]); - gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]); + gpio_set_level(GPIO_BAT_LED_GREEN_L, + !brightness[EC_LED_COLOR_GREEN]); + gpio_set_level(GPIO_BAT_LED_RED_L, + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { - gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]); + gpio_set_level(GPIO_PWR_LED_BLUE_L, + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 00636484a43b468382cc14b6926c30d63e2cf433 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:48 -0600 Subject: board/coachz/base_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1929d7fddc93f67296c2cc120c10814d8ac358a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728150 Reviewed-by: Jeremy Bettis --- board/coachz/base_detect.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/coachz/base_detect.c b/board/coachz/base_detect.c index 0068b37d8d..6465bd7a1d 100644 --- a/board/coachz/base_detect.c +++ b/board/coachz/base_detect.c @@ -19,8 +19,8 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Base detection and debouncing */ #define BASE_DETECT_EN_DEBOUNCE_US (350 * MSEC) @@ -93,8 +93,8 @@ static uint32_t pulse_width; static void print_base_detect_value(int v, int tmp_pulse_width) { - CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, - v, tmp_pulse_width); + CPRINTS("%s = %d (pulse %d)", adc_channels[ADC_BASE_DET].name, v, + tmp_pulse_width); } static void base_detect_deferred(void) @@ -144,12 +144,12 @@ void base_detect_interrupt(enum gpio_signal signal) { uint64_t time_now = get_time().val; int debounce_us; - + if (detect_pin_connected(signal)) debounce_us = BASE_DETECT_EN_DEBOUNCE_US; - else + else debounce_us = BASE_DETECT_DIS_DEBOUNCE_US; - + if (base_detect_debounce_time <= time_now) { /* * Detect and measure detection pin pulse, when base is @@ -211,7 +211,7 @@ static void base_init(void) if (system_jumped_late() && chipset_in_state(CHIPSET_STATE_ON)) base_enable(); } -DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, base_init, HOOK_PRIO_DEFAULT + 1); void base_force_state(enum ec_set_base_state_cmd state) { -- cgit v1.2.1 From c720085f617381f13bada0f77bcaccb2a1a03340 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:53 -0600 Subject: zephyr/test/drivers/src/temp_sensor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98e09afbdc2ba9788dc949e77915ebbd15129935 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730994 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/temp_sensor.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/zephyr/test/drivers/src/temp_sensor.c b/zephyr/test/drivers/src/temp_sensor.c index 1a49dba8ca..4b63c6ab8a 100644 --- a/zephyr/test/drivers/src/temp_sensor.c +++ b/zephyr/test/drivers/src/temp_sensor.c @@ -20,17 +20,16 @@ #define GPIO_PG_EC_DSW_PWROK_PATH DT_PATH(named_gpios, pg_ec_dsw_pwrok) #define GPIO_PG_EC_DSW_PWROK_PORT DT_GPIO_PIN(GPIO_PG_EC_DSW_PWROK_PATH, gpios) -#define ADC_DEVICE_NODE DT_NODELABEL(adc0) -#define ADC_CHANNELS_NUM DT_PROP(DT_NODELABEL(adc0), nchannels) +#define ADC_DEVICE_NODE DT_NODELABEL(adc0) +#define ADC_CHANNELS_NUM DT_PROP(DT_NODELABEL(adc0), nchannels) /** Test error code when invalid sensor is passed to temp_sensor_read() */ ZTEST_USER(temp_sensor, test_temp_sensor_wrong_id) { int temp; - zassert_equal(EC_ERROR_INVAL, temp_sensor_read(TEMP_SENSOR_COUNT, - &temp), - NULL); + zassert_equal(EC_ERROR_INVAL, + temp_sensor_read(TEMP_SENSOR_COUNT, &temp), NULL); } /** Test error code when temp_sensor_read() is called with powered off ADC */ @@ -85,9 +84,10 @@ static void check_valid_temperature(const struct device *adc_dev, int sensor) 1000), "adc_emul_const_value_set() failed (sensor %d)", sensor); zassert_equal(EC_SUCCESS, temp_sensor_read(sensor, &temp), NULL); - zassert_within(temp, 273 + 50, 51, - "Expected temperature in 0*C-100*C, got %d*C (sensor %d)", - temp - 273, sensor); + zassert_within( + temp, 273 + 50, 51, + "Expected temperature in 0*C-100*C, got %d*C (sensor %d)", + temp - 273, sensor); /* Return error on ADC channel of tested sensor */ zassert_ok(adc_emul_value_func_set(adc_dev, temp_sensors[sensor].idx, adc_error_func, NULL), @@ -105,7 +105,7 @@ ZTEST_USER(temp_sensor, test_temp_sensor_read) /* Return error on all ADC channels */ for (chan = 0; chan < ADC_CHANNELS_NUM; chan++) { zassert_ok(adc_emul_value_func_set(adc_dev, chan, - adc_error_func, NULL), + adc_error_func, NULL), "channel %d adc_emul_value_func_set() failed", chan); } -- cgit v1.2.1 From 0f67eea3d5f7502d668c473f9de8f0b73efa2c28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:45 -0600 Subject: common/usb_pd_tcpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id4160318c43dd8f5c7ebc68b7ef0178ae04026e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729777 Reviewed-by: Jeremy Bettis --- common/usb_pd_tcpc.c | 276 +++++++++++++++++++++++++-------------------------- 1 file changed, 137 insertions(+), 139 deletions(-) diff --git a/common/usb_pd_tcpc.c b/common/usb_pd_tcpc.c index 1aaee29abc..7c7690adec 100644 --- a/common/usb_pd_tcpc.c +++ b/common/usb_pd_tcpc.c @@ -24,8 +24,8 @@ #include "usb_pd_tcpm.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* * Debug log level - higher number == more log @@ -45,93 +45,93 @@ static const int debug_level; #endif /* Encode 5 bits using Biphase Mark Coding */ -#define BMC(x) ((x & 1 ? 0x001 : 0x3FF) \ - ^ (x & 2 ? 0x004 : 0x3FC) \ - ^ (x & 4 ? 0x010 : 0x3F0) \ - ^ (x & 8 ? 0x040 : 0x3C0) \ - ^ (x & 16 ? 0x100 : 0x300)) +#define BMC(x) \ + ((x & 1 ? 0x001 : 0x3FF) ^ (x & 2 ? 0x004 : 0x3FC) ^ \ + (x & 4 ? 0x010 : 0x3F0) ^ (x & 8 ? 0x040 : 0x3C0) ^ \ + (x & 16 ? 0x100 : 0x300)) /* 4b/5b + Bimark Phase encoding */ static const uint16_t bmc4b5b[] = { -/* 0 = 0000 */ BMC(0x1E) /* 11110 */, -/* 1 = 0001 */ BMC(0x09) /* 01001 */, -/* 2 = 0010 */ BMC(0x14) /* 10100 */, -/* 3 = 0011 */ BMC(0x15) /* 10101 */, -/* 4 = 0100 */ BMC(0x0A) /* 01010 */, -/* 5 = 0101 */ BMC(0x0B) /* 01011 */, -/* 6 = 0110 */ BMC(0x0E) /* 01110 */, -/* 7 = 0111 */ BMC(0x0F) /* 01111 */, -/* 8 = 1000 */ BMC(0x12) /* 10010 */, -/* 9 = 1001 */ BMC(0x13) /* 10011 */, -/* A = 1010 */ BMC(0x16) /* 10110 */, -/* B = 1011 */ BMC(0x17) /* 10111 */, -/* C = 1100 */ BMC(0x1A) /* 11010 */, -/* D = 1101 */ BMC(0x1B) /* 11011 */, -/* E = 1110 */ BMC(0x1C) /* 11100 */, -/* F = 1111 */ BMC(0x1D) /* 11101 */, -/* Sync-1 K-code 11000 Startsynch #1 */ -/* Sync-2 K-code 10001 Startsynch #2 */ -/* RST-1 K-code 00111 Hard Reset #1 */ -/* RST-2 K-code 11001 Hard Reset #2 */ -/* EOP K-code 01101 EOP End Of Packet */ -/* Reserved Error 00000 */ -/* Reserved Error 00001 */ -/* Reserved Error 00010 */ -/* Reserved Error 00011 */ -/* Reserved Error 00100 */ -/* Reserved Error 00101 */ -/* Reserved Error 00110 */ -/* Reserved Error 01000 */ -/* Reserved Error 01100 */ -/* Reserved Error 10000 */ -/* Reserved Error 11111 */ + /* 0 = 0000 */ BMC(0x1E) /* 11110 */, + /* 1 = 0001 */ BMC(0x09) /* 01001 */, + /* 2 = 0010 */ BMC(0x14) /* 10100 */, + /* 3 = 0011 */ BMC(0x15) /* 10101 */, + /* 4 = 0100 */ BMC(0x0A) /* 01010 */, + /* 5 = 0101 */ BMC(0x0B) /* 01011 */, + /* 6 = 0110 */ BMC(0x0E) /* 01110 */, + /* 7 = 0111 */ BMC(0x0F) /* 01111 */, + /* 8 = 1000 */ BMC(0x12) /* 10010 */, + /* 9 = 1001 */ BMC(0x13) /* 10011 */, + /* A = 1010 */ BMC(0x16) /* 10110 */, + /* B = 1011 */ BMC(0x17) /* 10111 */, + /* C = 1100 */ BMC(0x1A) /* 11010 */, + /* D = 1101 */ BMC(0x1B) /* 11011 */, + /* E = 1110 */ BMC(0x1C) /* 11100 */, + /* F = 1111 */ BMC(0x1D) /* 11101 */, + /* Sync-1 K-code 11000 Startsynch #1 */ + /* Sync-2 K-code 10001 Startsynch #2 */ + /* RST-1 K-code 00111 Hard Reset #1 */ + /* RST-2 K-code 11001 Hard Reset #2 */ + /* EOP K-code 01101 EOP End Of Packet */ + /* Reserved Error 00000 */ + /* Reserved Error 00001 */ + /* Reserved Error 00010 */ + /* Reserved Error 00011 */ + /* Reserved Error 00100 */ + /* Reserved Error 00101 */ + /* Reserved Error 00110 */ + /* Reserved Error 01000 */ + /* Reserved Error 01100 */ + /* Reserved Error 10000 */ + /* Reserved Error 11111 */ }; static const uint8_t dec4b5b[] = { -/* Error */ 0x10 /* 00000 */, -/* Error */ 0x10 /* 00001 */, -/* Error */ 0x10 /* 00010 */, -/* Error */ 0x10 /* 00011 */, -/* Error */ 0x10 /* 00100 */, -/* Error */ 0x10 /* 00101 */, -/* Error */ 0x10 /* 00110 */, -/* RST-1 */ 0x13 /* 00111 K-code: Hard Reset #1 */, -/* Error */ 0x10 /* 01000 */, -/* 1 = 0001 */ 0x01 /* 01001 */, -/* 4 = 0100 */ 0x04 /* 01010 */, -/* 5 = 0101 */ 0x05 /* 01011 */, -/* Error */ 0x10 /* 01100 */, -/* EOP */ 0x15 /* 01101 K-code: EOP End Of Packet */, -/* 6 = 0110 */ 0x06 /* 01110 */, -/* 7 = 0111 */ 0x07 /* 01111 */, -/* Error */ 0x10 /* 10000 */, -/* Sync-2 */ 0x12 /* 10001 K-code: Startsynch #2 */, -/* 8 = 1000 */ 0x08 /* 10010 */, -/* 9 = 1001 */ 0x09 /* 10011 */, -/* 2 = 0010 */ 0x02 /* 10100 */, -/* 3 = 0011 */ 0x03 /* 10101 */, -/* A = 1010 */ 0x0A /* 10110 */, -/* B = 1011 */ 0x0B /* 10111 */, -/* Sync-1 */ 0x11 /* 11000 K-code: Startsynch #1 */, -/* RST-2 */ 0x14 /* 11001 K-code: Hard Reset #2 */, -/* C = 1100 */ 0x0C /* 11010 */, -/* D = 1101 */ 0x0D /* 11011 */, -/* E = 1110 */ 0x0E /* 11100 */, -/* F = 1111 */ 0x0F /* 11101 */, -/* 0 = 0000 */ 0x00 /* 11110 */, -/* Error */ 0x10 /* 11111 */, + /* Error */ 0x10 /* 00000 */, + /* Error */ 0x10 /* 00001 */, + /* Error */ 0x10 /* 00010 */, + /* Error */ 0x10 /* 00011 */, + /* Error */ 0x10 /* 00100 */, + /* Error */ 0x10 /* 00101 */, + /* Error */ 0x10 /* 00110 */, + /* RST-1 */ 0x13 /* 00111 K-code: Hard Reset #1 */, + /* Error */ 0x10 /* 01000 */, + /* 1 = 0001 */ 0x01 /* 01001 */, + /* 4 = 0100 */ 0x04 /* 01010 */, + /* 5 = 0101 */ 0x05 /* 01011 */, + /* Error */ 0x10 /* 01100 */, + /* EOP */ 0x15 /* 01101 K-code: EOP End Of Packet */, + /* 6 = 0110 */ 0x06 /* 01110 */, + /* 7 = 0111 */ 0x07 /* 01111 */, + /* Error */ 0x10 /* 10000 */, + /* Sync-2 */ 0x12 /* 10001 K-code: Startsynch #2 */, + /* 8 = 1000 */ 0x08 /* 10010 */, + /* 9 = 1001 */ 0x09 /* 10011 */, + /* 2 = 0010 */ 0x02 /* 10100 */, + /* 3 = 0011 */ 0x03 /* 10101 */, + /* A = 1010 */ 0x0A /* 10110 */, + /* B = 1011 */ 0x0B /* 10111 */, + /* Sync-1 */ 0x11 /* 11000 K-code: Startsynch #1 */, + /* RST-2 */ 0x14 /* 11001 K-code: Hard Reset #2 */, + /* C = 1100 */ 0x0C /* 11010 */, + /* D = 1101 */ 0x0D /* 11011 */, + /* E = 1110 */ 0x0E /* 11100 */, + /* F = 1111 */ 0x0F /* 11101 */, + /* 0 = 0000 */ 0x00 /* 11110 */, + /* Error */ 0x10 /* 11111 */, }; /* Start of Packet sequence : three Sync-1 K-codes, then one Sync-2 K-code */ -#define PD_SOP (PD_SYNC1 | (PD_SYNC1<<5) | (PD_SYNC1<<10) | (PD_SYNC2<<15)) -#define PD_SOP_PRIME (PD_SYNC1 | (PD_SYNC1<<5) | \ - (PD_SYNC3<<10) | (PD_SYNC3<<15)) -#define PD_SOP_PRIME_PRIME (PD_SYNC1 | (PD_SYNC3<<5) | \ - (PD_SYNC1<<10) | (PD_SYNC3<<15)) +#define PD_SOP \ + (PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC1 << 10) | (PD_SYNC2 << 15)) +#define PD_SOP_PRIME \ + (PD_SYNC1 | (PD_SYNC1 << 5) | (PD_SYNC3 << 10) | (PD_SYNC3 << 15)) +#define PD_SOP_PRIME_PRIME \ + (PD_SYNC1 | (PD_SYNC3 << 5) | (PD_SYNC1 << 10) | (PD_SYNC3 << 15)) /* Hard Reset sequence : three RST-1 K-codes, then one RST-2 K-code */ -#define PD_HARD_RESET (PD_RST1 | (PD_RST1 << 5) |\ - (PD_RST1 << 10) | (PD_RST2 << 15)) +#define PD_HARD_RESET \ + (PD_RST1 | (PD_RST1 << 5) | (PD_RST1 << 10) | (PD_RST2 << 15)) /* * Polarity based on 'DFP Perspective' (see table USB Type-C Cable and Connector @@ -159,11 +159,11 @@ static const uint8_t dec4b5b[] = { #endif #ifndef CC_RA -#define CC_RA(port, cc, sel) (cc < PD_SRC_RD_THRESHOLD) +#define CC_RA(port, cc, sel) (cc < PD_SRC_RD_THRESHOLD) #endif #define CC_RD(cc) ((cc >= PD_SRC_RD_THRESHOLD) && (cc < PD_SRC_VNC)) #ifndef CC_NC -#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC) +#define CC_NC(port, cc, sel) (cc >= PD_SRC_VNC) #endif /* @@ -180,16 +180,16 @@ static const uint8_t dec4b5b[] = { #define PD_SNK_VA PD_SNK_VA_MV #endif -#define CC_RP(cc) (cc >= PD_SNK_VA) +#define CC_RP(cc) (cc >= PD_SNK_VA) /* * Type C power source charge current limits are identified by their cc * voltage (set by selecting the proper Rd resistor). Any voltage below * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger. */ -#define TYPE_C_SRC_500_THRESHOLD PD_SRC_RD_THRESHOLD -#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ -#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ +#define TYPE_C_SRC_500_THRESHOLD PD_SRC_RD_THRESHOLD +#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ +#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ /* Convert TCPC Alert register to index into pd.alert[] */ #define ALERT_REG_TO_INDEX(reg) (reg - TCPC_REG_ALERT) @@ -254,8 +254,8 @@ static struct pd_port_controller { #endif /* Last received */ - int rx_head[RX_BUFFER_SIZE+1]; - uint32_t rx_payload[RX_BUFFER_SIZE+1][7]; + int rx_head[RX_BUFFER_SIZE + 1]; + uint32_t rx_payload[RX_BUFFER_SIZE + 1][7]; int rx_buf_head, rx_buf_tail; /* Next transmit */ @@ -309,7 +309,7 @@ int encode_word(int port, int off, uint32_t val32) /* prepare a 4b/5b-encoded PD message to send */ int prepare_message(int port, uint16_t header, uint8_t cnt, - const uint32_t *data) + const uint32_t *data) { int off, i; /* 64-bit preamble */ @@ -387,8 +387,8 @@ static int send_validate_message(int port, uint16_t header, uint8_t expected_msg_id = PD_HEADER_ID(header); uint8_t cnt = PD_HEADER_CNT(header); int retries = PD_HEADER_TYPE(header) == PD_DATA_SOURCE_CAP ? - 0 : - CONFIG_PD_RETRY_COUNT; + 0 : + CONFIG_PD_RETRY_COUNT; /* retry 3 times if we are not getting a valid answer */ for (r = 0; r <= retries; r++) { @@ -464,7 +464,7 @@ static int send_validate_message(int port, uint16_t header, static void send_goodcrc(int port, int id) { uint16_t header = PD_HEADER(PD_CTRL_GOOD_CRC, pd[port].power_role, - pd[port].data_role, id, 0, 0, 0); + pd[port].data_role, id, 0, 0, 0); int bit_len = prepare_message(port, header, 0, NULL); if (pd_start_tx(port, pd[port].polarity, bit_len) < 0) @@ -536,7 +536,7 @@ static void bist_mode_2_tx(int port) * build context buffer with 5 bytes, where the data is * alternating 1's and 0's. */ - bit = pd_write_sym(port, 0, BMC(0x15)); + bit = pd_write_sym(port, 0, BMC(0x15)); bit = pd_write_sym(port, bit, BMC(0x0a)); bit = pd_write_sym(port, bit, BMC(0x15)); bit = pd_write_sym(port, bit, BMC(0x0a)); @@ -566,10 +566,9 @@ static inline int decode_short(int port, int off, uint16_t *val16) dec4b5b[(w >> 15) & 0x1f], dec4b5b[(w >> 10) & 0x1f], dec4b5b[(w >> 5) & 0x1f], dec4b5b[(w >> 0) & 0x1f]); #endif - *val16 = dec4b5b[w & 0x1f] | - (dec4b5b[(w >> 5) & 0x1f] << 4) | - (dec4b5b[(w >> 10) & 0x1f] << 8) | - (dec4b5b[(w >> 15) & 0x1f] << 12); + *val16 = dec4b5b[w & 0x1f] | (dec4b5b[(w >> 5) & 0x1f] << 4) | + (dec4b5b[(w >> 10) & 0x1f] << 8) | + (dec4b5b[(w >> 15) & 0x1f] << 12); return end; } @@ -674,7 +673,7 @@ int pd_analyze_rx(int port, uint32_t *payload) #else /* CONFIG_USB_VPD || CONFIG_USB_CTVPD */ #ifdef CONFIG_USB_PD_DECODE_SOP if (val == PD_SOP || val == PD_SOP_PRIME || - val == PD_SOP_PRIME_PRIME) + val == PD_SOP_PRIME_PRIME) break; #else if (val == PD_SOP) { @@ -734,7 +733,7 @@ int pd_analyze_rx(int port, uint32_t *payload) /* read payload data */ for (p = 0; p < cnt && bit > 0; p++) { - bit = decode_word(port, bit, payload+p); + bit = decode_word(port, bit, payload + p); crc32_hash32(payload[p]); } ccrc = crc32_result(); @@ -801,7 +800,7 @@ static int cc_voltage_to_status(int port, int cc_volt, int cc_sel) return TYPEC_CC_VOLT_RA; else return TYPEC_CC_VOLT_RD; - /* If we have a pull-down, then we are sink, check for Rp. */ + /* If we have a pull-down, then we are sink, check for Rp. */ } #ifdef CONFIG_USB_PD_DUAL_ROLE else if (pd[port].cc_pull == TYPEC_CC_RD) { @@ -843,9 +842,8 @@ int tcpc_run(int port, int evt) /* incoming packet ? */ if (pd_rx_started(port) && pd[port].rx_enabled) { /* Get message and place at RX buffer head */ - res = pd[port].rx_head[pd[port].rx_buf_head] = - pd_analyze_rx(port, - pd[port].rx_payload[pd[port].rx_buf_head]); + res = pd[port].rx_head[pd[port].rx_buf_head] = pd_analyze_rx( + port, pd[port].rx_payload[pd[port].rx_buf_head]); pd_rx_complete(port); /* @@ -872,9 +870,8 @@ int tcpc_run(int port, int evt) #else case TCPCI_MSG_SOP: #endif - res = send_validate_message(port, - pd[port].tx_head, - pd[port].tx_data); + res = send_validate_message(port, pd[port].tx_head, + pd[port].tx_data); break; case TCPCI_MSG_TX_BIST_MODE_2: bist_mode_2_tx(port); @@ -929,11 +926,11 @@ int tcpc_run(int port, int evt) */ return (get_time().val >= pd[port].low_power_ts.val && pd[port].cc_pull == TYPEC_CC_RD && - cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1])) - ? 200 * MSEC - : 10 * MSEC; + cc_is_open(pd[port].cc_status[0], pd[port].cc_status[1])) ? + 200 * MSEC : + 10 * MSEC; #else - return 10*MSEC; + return 10 * MSEC; #endif } @@ -941,7 +938,7 @@ int tcpc_run(int port, int evt) void pd_task(void *u) { int port = TASK_ID_TO_PD_PORT(task_get_current()); - int timeout = 10*MSEC; + int timeout = 10 * MSEC; int evt; /* initialize phy task */ @@ -1024,8 +1021,8 @@ int tcpc_set_cc(int port, int pull) * because we only want to go into low power mode when we are not * dual-role toggling. */ - pd[port].low_power_ts.val = get_time().val + - 2*(PD_T_DRP_SRC + PD_T_DRP_SNK); + pd[port].low_power_ts.val = + get_time().val + 2 * (PD_T_DRP_SRC + PD_T_DRP_SNK); #endif /* @@ -1047,7 +1044,7 @@ int tcpc_set_cc(int port, int pull) } int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { *cc2 = pd[port].cc_status[1]; *cc1 = pd[port].cc_status[0]; @@ -1184,8 +1181,9 @@ void tcpc_init(int port) /* Initialize physical layer */ pd_hw_init(port, PD_ROLE_DEFAULT(port)); - pd[port].cc_pull = PD_ROLE_DEFAULT(port) == - PD_ROLE_SOURCE ? TYPEC_CC_RP : TYPEC_CC_RD; + pd[port].cc_pull = PD_ROLE_DEFAULT(port) == PD_ROLE_SOURCE ? + TYPEC_CC_RP : + TYPEC_CC_RD; #ifdef TCPC_LOW_POWER /* Don't use low power immediately after boot */ pd[port].low_power_ts.val = get_time().val + SECOND; @@ -1196,16 +1194,15 @@ void tcpc_init(int port) /* make initial readings of CC voltages */ for (i = 0; i < 2; i++) { - pd[port].cc_status[i] = cc_voltage_to_status(port, - pd_adc_read(port, i), - i); + pd[port].cc_status[i] = + cc_voltage_to_status(port, pd_adc_read(port, i), i); } #ifdef CONFIG_USB_PD_TCPC_TRACK_VBUS #if CONFIG_USB_PD_PORT_MAX_COUNT >= 2 - tcpc_set_power_status(port, !gpio_get_level(port ? - GPIO_USB_C1_VBUS_WAKE_L : - GPIO_USB_C0_VBUS_WAKE_L)); + tcpc_set_power_status(port, + !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L : + GPIO_USB_C0_VBUS_WAKE_L)); #else tcpc_set_power_status(port, !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); #endif /* CONFIG_USB_PD_PORT_MAX_COUNT >= 2 */ @@ -1223,7 +1220,7 @@ void tcpc_init(int port) void pd_vbus_evt_p0(enum gpio_signal signal) { tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C0), - !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); + !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); task_wake(TASK_ID_PD_C0); } @@ -1234,7 +1231,7 @@ void pd_vbus_evt_p1(enum gpio_signal signal) return; tcpc_set_power_status(TASK_ID_TO_PD_PORT(TASK_ID_PD_C1), - !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); + !gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); task_wake(TASK_ID_PD_C1); } #endif /* PD_PORT_COUNT >= 2 */ @@ -1277,8 +1274,8 @@ static void tcpc_i2c_write(int port, int reg, int len, uint8_t *payload) tcpc_alert_mask_set(port, alert); break; case TCPC_REG_RX_DETECT: - tcpc_set_rx_enable(port, payload[1] & - TCPC_REG_RX_DETECT_SOP_HRST_MASK); + tcpc_set_rx_enable( + port, payload[1] & TCPC_REG_RX_DETECT_SOP_HRST_MASK); break; case TCPC_REG_POWER_STATUS_MASK: tcpc_set_power_status_mask(port, payload[1]); @@ -1308,12 +1305,11 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload) case TCPC_REG_CC_STATUS: tcpc_get_cc(port, &cc1, &cc2); payload[0] = TCPC_REG_CC_STATUS_SET( - pd[port].cc_pull == TYPEC_CC_RD, - pd[port].cc_status[0], pd[port].cc_status[1]); + pd[port].cc_pull == TYPEC_CC_RD, pd[port].cc_status[0], + pd[port].cc_status[1]); return 1; case TCPC_REG_ROLE_CTRL: - payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0, - pd[port].cc_pull, + payload[0] = TCPC_REG_ROLE_CTRL_SET(0, 0, pd[port].cc_pull, pd[port].cc_pull); return 1; case TCPC_REG_TCPC_CTRL: @@ -1325,7 +1321,8 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload) return 1; case TCPC_REG_RX_DETECT: payload[0] = pd[port].rx_enabled ? - TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0; + TCPC_REG_RX_DETECT_SOP_HRST_MASK : + 0; return 1; case TCPC_REG_ALERT: tcpc_alert_status(port, &alert); @@ -1337,13 +1334,14 @@ static int tcpc_i2c_read(int port, int reg, uint8_t *payload) payload[1] = (pd[port].alert_mask >> 8) & 0xff; return 2; case TCPC_REG_RX_BYTE_CNT: - payload[0] = 3 + 4 * - PD_HEADER_CNT(pd[port].rx_head[pd[port].rx_buf_tail]); + payload[0] = + 3 + 4 * PD_HEADER_CNT( + pd[port].rx_head[pd[port].rx_buf_tail]); return 1; case TCPC_REG_RX_HDR: payload[0] = pd[port].rx_head[pd[port].rx_buf_tail] & 0xff; - payload[1] = - (pd[port].rx_head[pd[port].rx_buf_tail] >> 8) & 0xff; + payload[1] = (pd[port].rx_head[pd[port].rx_buf_tail] >> 8) & + 0xff; return 2; case TCPC_REG_RX_DATA: memcpy(payload, pd[port].rx_payload[pd[port].rx_buf_tail], @@ -1452,12 +1450,12 @@ static int command_tcpc(int argc, char **argv) } else if (!strncasecmp(argv[2], "state", 5)) { ccprintf("Port C%d, %s - CC:%d, CC0:%d, CC1:%d\n" "Alert: 0x%02x Mask: 0x%04x\n" - "Power Status: 0x%02x Mask: 0x%02x\n", port, - pd[port].rx_enabled ? "Ena" : "Dis", - pd[port].cc_pull, - pd[port].cc_status[0], pd[port].cc_status[1], - pd[port].alert, pd[port].alert_mask, - pd[port].power_status, pd[port].power_status_mask); + "Power Status: 0x%02x Mask: 0x%02x\n", + port, pd[port].rx_enabled ? "Ena" : "Dis", + pd[port].cc_pull, pd[port].cc_status[0], + pd[port].cc_status[1], pd[port].alert, + pd[port].alert_mask, pd[port].power_status, + pd[port].power_status_mask); } return EC_SUCCESS; -- cgit v1.2.1 From 3169ff2553bb9422132efc11b40f9f71889590b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:19 -0600 Subject: common/rwsig.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I78717f34ba60e3d82903fe394bc71c7f7c7d52bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729747 Reviewed-by: Jeremy Bettis --- common/rwsig.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/common/rwsig.c b/common/rwsig.c index 676c66d79b..b13a87e49c 100644 --- a/common/rwsig.c +++ b/common/rwsig.c @@ -25,18 +25,17 @@ #include "vboot.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) #if !defined(CONFIG_MAPPED_STORAGE) #error rwsig implementation assumes mem-mapped storage. #endif /* RW firmware reset vector */ -static uint32_t * const rw_rst = +static uint32_t *const rw_rst = (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4); - void rwsig_jump_now(void) { /* Protect all flash before jumping to RW. */ @@ -74,8 +73,8 @@ void rwsig_jump_now(void) * Check that memory between rwdata[start] and rwdata[len-1] is filled * with ones. data, start and len must be aligned on 4-byte boundary. */ -static int check_padding(const uint8_t *data, - unsigned int start, unsigned int len) +static int check_padding(const uint8_t *data, unsigned int start, + unsigned int len) { unsigned int i; const uint32_t *data32 = (const uint32_t *)data; @@ -83,7 +82,7 @@ static int check_padding(const uint8_t *data, if ((start % 4) != 0 || (len % 4) != 0) return 0; - for (i = start/4; i < len/4; i++) { + for (i = start / 4; i < len / 4; i++) { if (data32[i] != 0xffffffff) return 0; } @@ -99,8 +98,8 @@ int rwsig_check_signature(void) const uint8_t *sig; uint8_t *hash; uint32_t *rsa_workbuf = NULL; - const uint8_t *rwdata = (uint8_t *)CONFIG_PROGRAM_MEMORY_BASE - + CONFIG_RW_MEM_OFF; + const uint8_t *rwdata = + (uint8_t *)CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF; int good = 0; unsigned int rwlen; @@ -125,8 +124,8 @@ int rwsig_check_signature(void) if (rw_rollback_version < 0 || min_rollback_version < 0 || rw_rollback_version < min_rollback_version) { - CPRINTS("Rollback error (%d < %d)", - rw_rollback_version, min_rollback_version); + CPRINTS("Rollback error (%d < %d)", rw_rollback_version, + min_rollback_version); goto out; } #endif @@ -152,8 +151,8 @@ int rwsig_check_signature(void) goto out; } - key = (const struct rsa_public_key *) - ((const uint8_t *)vb21_key + vb21_key->key_offset); + key = (const struct rsa_public_key *)((const uint8_t *)vb21_key + + vb21_key->key_offset); /* * TODO(crbug.com/690773): We could verify other parameters such @@ -179,7 +178,7 @@ int rwsig_check_signature(void) * Check that unverified RW region is actually filled with ones. */ good = check_padding(rwdata, rwlen, - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE); + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE); if (!good) { CPRINTS("Invalid padding."); goto out; @@ -207,11 +206,10 @@ int rwsig_check_signature(void) */ if (rw_rollback_version != min_rollback_version #ifdef CONFIG_FLASH_PROTECT_RW - && ((!system_is_locked() || - crec_flash_get_protect() & - EC_FLASH_PROTECT_RW_NOW)) + && ((!system_is_locked() || + crec_flash_get_protect() & EC_FLASH_PROTECT_RW_NOW)) #endif - ) { + ) { /* * This will fail if the rollback block is protected (RW image * will unprotect that block later on). @@ -219,8 +217,7 @@ int rwsig_check_signature(void) int ret = rollback_update_version(rw_rollback_version); if (ret == 0) { - CPRINTS("Rollback updated to %d", - rw_rollback_version); + CPRINTS("Rollback updated to %d", rw_rollback_version); } else if (ret != EC_ERROR_ACCESS_DENIED) { CPRINTS("Rollback update error %d", ret); good = 0; @@ -315,9 +312,7 @@ static enum ec_status rwsig_cmd_action(struct host_cmd_handler_args *args) args->response_size = 0; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION, - rwsig_cmd_action, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_RWSIG_ACTION, rwsig_cmd_action, EC_VER_MASK(0)); #else /* !HAS_TASK_RWSIG */ static enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args) @@ -330,7 +325,6 @@ static enum ec_status rwsig_cmd_check_status(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS, - rwsig_cmd_check_status, +DECLARE_HOST_COMMAND(EC_CMD_RWSIG_CHECK_STATUS, rwsig_cmd_check_status, EC_VER_MASK(0)); #endif -- cgit v1.2.1 From ee49f602dfb6ab2cf16af56a888bb3a05e6ae996 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:49 -0600 Subject: chip/it83xx/dac.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idc78adc2e1d3e7e25cc7409ef2ba60392b2df818 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729195 Reviewed-by: Jeremy Bettis --- chip/it83xx/dac.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/chip/it83xx/dac.c b/chip/it83xx/dac.c index 695d1cbc68..bcb7d25024 100644 --- a/chip/it83xx/dac.c +++ b/chip/it83xx/dac.c @@ -85,6 +85,5 @@ static int command_dac(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dac, command_dac, - "[ch2-5] [0-3300mV]", +DECLARE_CONSOLE_COMMAND(dac, command_dac, "[ch2-5] [0-3300mV]", "Enable or disable(0mV) DAC output voltage."); -- cgit v1.2.1 From 7e723f211a48e7e78a0fa3fd615c6f1b91f61971 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:23 -0600 Subject: test/usb_ppc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I77e7c5bba65a883580ab03ff0ca0a1ad8753c949 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730551 Reviewed-by: Jeremy Bettis --- test/usb_ppc.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/test/usb_ppc.c b/test/usb_ppc.c index 0cf6f69bf3..4d37992348 100644 --- a/test/usb_ppc.c +++ b/test/usb_ppc.c @@ -28,15 +28,12 @@ const struct ppc_drv null_drv = { }; struct ppc_config_t ppc_chips[] = { - [0] = { - .drv = &null_drv - }, + [0] = { .drv = &null_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); const struct tcpc_config_t tcpc_config[] = { - [0] = { - }, + [0] = {}, }; static int test_ppc_init(void) @@ -171,8 +168,6 @@ static int test_ppc_is_vbus_present(void) return EC_SUCCESS; } - - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 17348d9d2f8f28b96b650f32b13a4bc3b05a7eef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:29 -0600 Subject: core/host/host_task.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib12135303310a2c4f291ff7e3130cacd77030974 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729839 Reviewed-by: Jeremy Bettis --- core/host/host_task.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/host/host_task.h b/core/host/host_task.h index 30cd2ff594..c0e2534347 100644 --- a/core/host/host_task.h +++ b/core/host/host_task.h @@ -34,4 +34,4 @@ void task_register_interrupt(void); */ pid_t getpid(void); -#endif /* __CROS_EC_HOST_TASK_H */ +#endif /* __CROS_EC_HOST_TASK_H */ -- cgit v1.2.1 From 91f115b7b2951521ec44d5fb721ac6f370ade1f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:17 -0600 Subject: cts/hook/dut.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibe525534d790b42fe3e5b7251a856735747c1e22 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729742 Reviewed-by: Jeremy Bettis --- cts/hook/dut.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/cts/hook/dut.c b/cts/hook/dut.c index f3a52ddaf4..1d6b1e145e 100644 --- a/cts/hook/dut.c +++ b/cts/hook/dut.c @@ -88,8 +88,7 @@ static enum cts_rc test_ticks(void) msleep(1300); interval = tick_time[1].val - tick_time[0].val; - error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / - HOOK_TICK_INTERVAL; + error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL; if (error_pct < -10 || 10 < error_pct) { CPRINTS("tick error=%d%% interval=%lld", error_pct, interval); return CTS_RC_FAILURE; @@ -142,8 +141,8 @@ static enum cts_rc test_deferred(void) /* Invalid deferred function */ deferred_call_count = 0; - if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) - == EC_SUCCESS) { + if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) == + EC_SUCCESS) { CPRINTL("non_deferred_func_data"); return CTS_RC_FAILURE; } -- cgit v1.2.1 From dd7c77f63e0510c4701a9a2e232757a4d48e527d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:27 -0600 Subject: driver/charger/bd9995x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idfe3c40be177ba6baefd2ce36329222e432c570c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729936 Reviewed-by: Jeremy Bettis --- driver/charger/bd9995x.c | 379 ++++++++++++++++++++++++----------------------- 1 file changed, 193 insertions(+), 186 deletions(-) diff --git a/driver/charger/bd9995x.c b/driver/charger/bd9995x.c index 8fee94ad7b..80479523b4 100644 --- a/driver/charger/bd9995x.c +++ b/driver/charger/bd9995x.c @@ -21,7 +21,7 @@ #include "usb_charge.h" #include "usb_pd.h" -#define OTPROM_LOAD_WAIT_RETRY 3 +#define OTPROM_LOAD_WAIT_RETRY 3 #define BD9995X_CHARGE_PORT_COUNT 2 @@ -29,11 +29,11 @@ * BC1.2 detection starts 100ms after VBUS/VCC attach and typically * completes 312ms after VBUS/VCC attach. */ -#define BC12_DETECT_US (312*MSEC) +#define BC12_DETECT_US (312 * MSEC) #define BD9995X_VSYS_PRECHARGE_OFFSET_MV 200 /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT /* @@ -44,18 +44,18 @@ #define VBUS_DELTA 1000 /* VBUS is debounced if it's stable for this length of time */ -#define VBUS_MSEC (100*MSEC) +#define VBUS_MSEC (100 * MSEC) /* VBUS debouncing sample interval */ -#define VBUS_CHECK_MSEC (10*MSEC) +#define VBUS_CHECK_MSEC (10 * MSEC) /* Time to wait before VBUS debouncing begins */ -#define STABLE_TIMEOUT (500*MSEC) +#define STABLE_TIMEOUT (500 * MSEC) /* Maximum time to wait until VBUS is debounced */ -#define DEBOUNCE_TIMEOUT (500*MSEC) +#define DEBOUNCE_TIMEOUT (500 * MSEC) -enum vstate {START, STABLE, DEBOUNCE}; +enum vstate { START, STABLE, DEBOUNCE }; static enum vstate vbus_state; static int vbus_voltage; @@ -67,29 +67,29 @@ static int select_input_port_update; #endif /* Charger parameters */ -#define CHARGER_NAME BD9995X_CHARGER_NAME -#define CHARGE_V_MAX 19200 -#define CHARGE_V_MIN 3072 -#define CHARGE_V_STEP 16 -#define CHARGE_I_MAX 16320 -#define CHARGE_I_MIN 128 -#define CHARGE_I_OFF 0 -#define CHARGE_I_STEP 64 -#define INPUT_I_MAX 16352 -#define INPUT_I_MIN 512 -#define INPUT_I_STEP 32 +#define CHARGER_NAME BD9995X_CHARGER_NAME +#define CHARGE_V_MAX 19200 +#define CHARGE_V_MIN 3072 +#define CHARGE_V_STEP 16 +#define CHARGE_I_MAX 16320 +#define CHARGE_I_MIN 128 +#define CHARGE_I_OFF 0 +#define CHARGE_I_STEP 64 +#define INPUT_I_MAX 16352 +#define INPUT_I_MIN 512 +#define INPUT_I_STEP 32 /* Charger parameters */ static const struct charger_info bd9995x_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = CHARGE_I_MAX, - .current_min = CHARGE_I_MIN, + .current_max = CHARGE_I_MAX, + .current_min = CHARGE_I_MIN, .current_step = CHARGE_I_STEP, - .input_current_max = INPUT_I_MAX, - .input_current_min = INPUT_I_MIN, + .input_current_max = INPUT_I_MAX, + .input_current_min = INPUT_I_MIN, .input_current_step = INPUT_I_STEP, }; @@ -164,8 +164,7 @@ static inline enum ec_error_list ch_raw_read16(int chgnum, int cmd, int *param, } rv = i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - cmd, param); + chg_chips[chgnum].i2c_addr_flags, cmd, param); bd9995x_read_cleanup: mutex_unlock(&bd9995x_map_mutex); @@ -193,8 +192,7 @@ static inline enum ec_error_list ch_raw_write16(int chgnum, int cmd, int param, } rv = i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - cmd, param); + chg_chips[chgnum].i2c_addr_flags, cmd, param); bd9995x_write_cleanup: mutex_unlock(&bd9995x_map_mutex); @@ -206,12 +204,11 @@ bd9995x_write_cleanup: static int bd9995x_set_vfastchg(int chgnum, int voltage) { - int rv; /* Fast Charge Voltage Regulation Settings for fast charging. */ rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET1, - voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); + voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -221,12 +218,12 @@ static int bd9995x_set_vfastchg(int chgnum, int voltage) * to same voltage. */ rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET2, - voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); + voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); if (rv) return rv; rv = ch_raw_write16(chgnum, BD9995X_CMD_VFASTCHG_REG_SET3, - voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); + voltage & 0x7FF0, BD9995X_EXTENDED_COMMAND); #endif return rv; @@ -246,7 +243,7 @@ static int bd9995x_is_discharging_on_ac(int chgnum) int reg; if (ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, ®, - BD9995X_EXTENDED_COMMAND)) + BD9995X_EXTENDED_COMMAND)) return 0; return !!(reg & BD9995X_CMD_CHGOP_SET2_BATT_LEARN); @@ -292,8 +289,9 @@ static int bd9995x_charger_enable(int chgnum, int enable) * Set VSYSREG_SET > VBAT so that the charger is in Pre-Charge * state when not charging or discharging. */ - rv = bd9995x_set_vsysreg(chgnum, bi->voltage_max + - BD9995X_VSYS_PRECHARGE_OFFSET_MV); + rv = bd9995x_set_vsysreg( + chgnum, + bi->voltage_max + BD9995X_VSYS_PRECHARGE_OFFSET_MV); /* * Allow charger in pre-charge state for 50ms before disabling @@ -306,7 +304,7 @@ static int bd9995x_charger_enable(int chgnum, int enable) return rv; rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -316,7 +314,7 @@ static int bd9995x_charger_enable(int chgnum, int enable) reg &= ~BD9995X_CMD_CHGOP_SET2_CHG_EN; return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } static int bd9995x_por_reset(int chgnum) @@ -326,9 +324,9 @@ static int bd9995x_por_reset(int chgnum) int i; rv = ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET, - BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD | - BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST, - BD9995X_EXTENDED_COMMAND); + BD9995X_CMD_SYSTEM_CTRL_SET_OTPLD | + BD9995X_CMD_SYSTEM_CTRL_SET_ALLRST, + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -336,10 +334,10 @@ static int bd9995x_por_reset(int chgnum) for (i = 0; i < OTPROM_LOAD_WAIT_RETRY; i++) { msleep(10); rv = ch_raw_read16(chgnum, BD9995X_CMD_SYSTEM_STATUS, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (!rv && (reg & BD9995X_CMD_SYSTEM_STATUS_OTPLD_STATE) && - (reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE)) + (reg & BD9995X_CMD_SYSTEM_STATUS_ALLRST_STATE)) break; } @@ -349,7 +347,7 @@ static int bd9995x_por_reset(int chgnum) return EC_ERROR_TIMEOUT; return ch_raw_write16(chgnum, BD9995X_CMD_SYSTEM_CTRL_SET, 0, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } static int bd9995x_reset_to_zero(int chgnum) @@ -366,7 +364,7 @@ static int bd9995x_reset_to_zero(int chgnum) static int bd9995x_get_charger_op_status(int chgnum, int *status) { return ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_STATUS, status, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } #ifdef HAS_TASK_USB_CHG @@ -379,10 +377,11 @@ static int bd9995x_get_bc12_device_type(int chgnum, int port) int rv; int reg; - rv = ch_raw_read16(chgnum, (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_VBUS_UCD_STATUS : - BD9995X_CMD_VCC_UCD_STATUS, - ®, BD9995X_EXTENDED_COMMAND); + rv = ch_raw_read16(chgnum, + (port == BD9995X_CHARGE_PORT_VBUS) ? + BD9995X_CMD_VBUS_UCD_STATUS : + BD9995X_CMD_VCC_UCD_STATUS, + ®, BD9995X_EXTENDED_COMMAND); if (rv) return CHARGE_SUPPLIER_NONE; @@ -415,7 +414,8 @@ static int bd9995x_update_ucd_set_reg(int chgnum, int port, uint16_t mask, int rv; int reg; int port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_VBUS_UCD_SET : BD9995X_CMD_VCC_UCD_SET; + BD9995X_CMD_VBUS_UCD_SET : + BD9995X_CMD_VCC_UCD_SET; mutex_lock(&ucd_set_mutex[port]); rv = ch_raw_read16(chgnum, port_reg, ®, BD9995X_EXTENDED_COMMAND); @@ -484,32 +484,33 @@ static int bd9995x_enable_vbus_detect_interrupts(int chgnum, int port, /* 1st Level Interrupt Setting */ rv = ch_raw_read16(chgnum, BD9995X_CMD_INT0_SET, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; mask_val = ((port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_INT0_SET_INT1_EN : - BD9995X_CMD_INT0_SET_INT2_EN) | - BD9995X_CMD_INT0_SET_INT0_EN; + BD9995X_CMD_INT0_SET_INT1_EN : + BD9995X_CMD_INT0_SET_INT2_EN) | + BD9995X_CMD_INT0_SET_INT0_EN; if (enable) reg |= mask_val; else reg &= ~mask_val; rv = ch_raw_write16(chgnum, BD9995X_CMD_INT0_SET, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; /* 2nd Level Interrupt Setting */ - port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_INT1_SET : BD9995X_CMD_INT2_SET; + port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_INT1_SET : + BD9995X_CMD_INT2_SET; rv = ch_raw_read16(chgnum, port_reg, ®, BD9995X_EXTENDED_COMMAND); if (rv) return rv; - /* Enable threshold interrupts if we need to control discharge */ + /* Enable threshold interrupts if we need to control discharge + */ #ifdef CONFIG_USB_PD_DISCHARGE mask_val = BD9995X_CMD_INT_VBUS_DET | BD9995X_CMD_INT_VBUS_TH; #else @@ -531,7 +532,8 @@ static int bd9995x_get_interrupts(int chgnum, int port) int port_reg; port_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_INT1_STATUS : BD9995X_CMD_INT2_STATUS; + BD9995X_CMD_INT1_STATUS : + BD9995X_CMD_INT2_STATUS; rv = ch_raw_read16(chgnum, port_reg, ®, BD9995X_EXTENDED_COMMAND); @@ -553,8 +555,8 @@ static int bd9995x_bc12_detect(int chgnum, int port, int enable) { return bd9995x_update_ucd_set_reg(chgnum, port, BD9995X_CMD_UCD_SET_BCSRETRY | - BD9995X_CMD_UCD_SET_USBDETEN | - BD9995X_CMD_UCD_SET_USB_SW_EN, + BD9995X_CMD_UCD_SET_USBDETEN | + BD9995X_CMD_UCD_SET_USB_SW_EN, enable); } @@ -626,12 +628,12 @@ static enum ec_error_list bd9995x_set_input_current_limit(int chgnum, input_current = bd9995x_charger_info.input_current_min; rv = ch_raw_write16(chgnum, BD9995X_CMD_IBUS_LIM_SET, input_current, - BD9995X_BAT_CHG_COMMAND); + BD9995X_BAT_CHG_COMMAND); if (rv) return rv; return ch_raw_write16(chgnum, BD9995X_CMD_ICC_LIM_SET, input_current, - BD9995X_BAT_CHG_COMMAND); + BD9995X_BAT_CHG_COMMAND); } static enum ec_error_list bd9995x_get_input_current_limit(int chgnum, @@ -658,12 +660,12 @@ static enum ec_error_list bd9995x_get_option(int chgnum, int *option) int reg; rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET1, option, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -677,7 +679,7 @@ static enum ec_error_list bd9995x_set_option(int chgnum, int option) int rv; rv = ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET1, option & 0xFFFF, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -704,7 +706,7 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status) /* charger enable/inhibit */ rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -713,15 +715,15 @@ static enum ec_error_list bd9995x_get_status(int chgnum, int *status) /* charger alarm enable/inhibit */ rv = ch_raw_read16(chgnum, BD9995X_CMD_PROCHOT_CTRL_SET, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; if (!(reg & (BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN4 | - BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 | - BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 | - BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 | - BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0))) + BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN3 | + BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN2 | + BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN1 | + BD9995X_CMD_PROCHOT_CTRL_SET_PROCHOT_EN0))) *status |= CHARGER_ALARM_INHIBITED; rv = bd9995x_get_charger_op_status(chgnum, ®); @@ -788,7 +790,7 @@ static enum ec_error_list bd9995x_set_mode(int chgnum, int mode) static enum ec_error_list bd9995x_get_current(int chgnum, int *current) { return ch_raw_read16(chgnum, BD9995X_CMD_CHG_CURRENT, current, - BD9995X_BAT_CHG_COMMAND); + BD9995X_BAT_CHG_COMMAND); } static enum ec_error_list bd9995x_set_current(int chgnum, int current) @@ -824,7 +826,7 @@ static enum ec_error_list bd9995x_set_current(int chgnum, int current) return rv; rv = ch_raw_write16(chgnum, BD9995X_CMD_CHG_CURRENT, current, - BD9995X_BAT_CHG_COMMAND); + BD9995X_BAT_CHG_COMMAND); if (rv) return rv; @@ -869,7 +871,7 @@ static enum ec_error_list bd9995x_get_voltage(int chgnum, int *voltage) } return ch_raw_read16(chgnum, BD9995X_CMD_CHG_VOLTAGE, voltage, - BD9995X_BAT_CHG_COMMAND); + BD9995X_BAT_CHG_COMMAND); } static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage) @@ -880,11 +882,9 @@ static enum ec_error_list bd9995x_set_voltage(int chgnum, int voltage) * Regulate the system voltage to battery max if the battery * is not present or the battery is discharging on AC. */ - if (voltage == 0 || - bd9995x_is_discharging_on_ac(chgnum) || - battery_is_present() != BP_YES || - battery_is_cut_off() || - voltage > battery_voltage_max) + if (voltage == 0 || bd9995x_is_discharging_on_ac(chgnum) || + battery_is_present() != BP_YES || battery_is_cut_off() || + voltage > battery_voltage_max) voltage = battery_voltage_max; /* Charge voltage step 16 mV */ @@ -921,8 +921,7 @@ static void bd9995x_battery_charging_profile_settings(int chgnum) BD9995X_EXTENDED_COMMAND); /* Re-charge Battery Voltage Setting */ - ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET, - bi->voltage_max & 0x7FF0, + ch_raw_write16(chgnum, BD9995X_CMD_VRECHG_SET, bi->voltage_max & 0x7FF0, BD9995X_EXTENDED_COMMAND); /* Set battery OVP to 500 + maximum battery voltage */ @@ -972,8 +971,9 @@ static void bd9995x_init(void) * that the charger is in Pre-Charge state and that the input current * disable setting below will be active. */ - bd9995x_set_vsysreg(CHARGER_SOLO, battery_get_info()->voltage_max + - BD9995X_VSYS_PRECHARGE_OFFSET_MV); + bd9995x_set_vsysreg(CHARGER_SOLO, + battery_get_info()->voltage_max + + BD9995X_VSYS_PRECHARGE_OFFSET_MV); /* Enable BC1.2 USB charging and DC/DC converter @ 1200KHz */ if (ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET2, ®, @@ -1060,7 +1060,7 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable) int reg; rv = ch_raw_read16(chgnum, BD9995X_CMD_CHGOP_SET2, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -1072,13 +1072,13 @@ static enum ec_error_list bd9995x_discharge_on_ac(int chgnum, int enable) */ if (enable) reg |= BD9995X_CMD_CHGOP_SET2_BATT_LEARN | - BD9995X_CMD_CHGOP_SET2_USB_SUS; + BD9995X_CMD_CHGOP_SET2_USB_SUS; else reg &= ~(BD9995X_CMD_CHGOP_SET2_BATT_LEARN | - BD9995X_CMD_CHGOP_SET2_USB_SUS); + BD9995X_CMD_CHGOP_SET2_USB_SUS); return ch_raw_write16(chgnum, BD9995X_CMD_CHGOP_SET2, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } static enum ec_error_list bd9995x_get_vbus_voltage(int chgnum, int port, @@ -1143,7 +1143,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select) } else if (port == BD9995X_CHARGE_PORT_BOTH) { /* Enable both the ports for PG3 */ reg |= BD9995X_CMD_VIN_CTRL_SET_VBUS_EN | - BD9995X_CMD_VIN_CTRL_SET_VCC_EN; + BD9995X_CMD_VIN_CTRL_SET_VCC_EN; } else { /* Invalid charge port */ panic("Invalid charge port"); @@ -1161,7 +1161,7 @@ int bd9995x_select_input_port(enum bd9995x_charge_port port, int select) } rv = ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_VIN_CTRL_SET, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); select_input_port_exit: mutex_unlock(&bd9995x_vin_mutex); return rv; @@ -1192,8 +1192,8 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port) int vbus_reg; int voltage; - vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_VBUS_VAL : BD9995X_CMD_VCC_VAL; + vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? BD9995X_CMD_VBUS_VAL : + BD9995X_CMD_VCC_VAL; if (ch_raw_read16(chgnum, vbus_reg, &voltage, BD9995X_EXTENDED_COMMAND)) voltage = 0; @@ -1209,14 +1209,13 @@ static int bd9995x_vbus_debounce(int chgnum, enum bd9995x_charge_port port) } #endif - #ifdef CONFIG_CHARGER_BATTERY_TSENSE int bd9995x_get_battery_temp(int *temp_ptr) { int rv; rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_THERM_VAL, temp_ptr, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -1237,7 +1236,7 @@ int bd9995x_get_battery_voltage(void) int vbat_val, rv; rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_VBAT_VAL, &vbat_val, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); return rv ? 0 : vbat_val; } @@ -1255,15 +1254,15 @@ int bd9995x_bc12_enable_charging(int port, int enable) * for USB-C. */ rv = ch_raw_read16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; mask_val = (BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG_EN | - BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG | - ((port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN : - BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN)); + BD9995X_CMD_CHGOP_SET1_SDP_CHG_TRIG | + ((port == BD9995X_CHARGE_PORT_VBUS) ? + BD9995X_CMD_CHGOP_SET1_VBUS_BC_DISEN : + BD9995X_CMD_CHGOP_SET1_VCC_BC_DISEN)); if (enable) reg &= ~mask_val; @@ -1271,7 +1270,7 @@ int bd9995x_bc12_enable_charging(int port, int enable) reg |= mask_val; return ch_raw_write16(CHARGER_SOLO, BD9995X_CMD_CHGOP_SET1, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } static void bd9995x_set_switches(int port, enum usb_switch setting) @@ -1283,17 +1282,18 @@ static void bd9995x_set_switches(int port, enum usb_switch setting) if (setting != USB_SWITCH_RESTORE) usb_switch_state[port] = setting; - /* ensure we disable power saving when we are using DP/DN */ + /* ensure we disable power saving when we are using DP/DN */ #ifdef CONFIG_BD9995X_POWER_SAVE_MODE bd9995x_set_power_save_mode( (usb_switch_state[0] == USB_SWITCH_DISCONNECT && - usb_switch_state[1] == USB_SWITCH_DISCONNECT) - ? CONFIG_BD9995X_POWER_SAVE_MODE : BD9995X_PWR_SAVE_OFF); + usb_switch_state[1] == USB_SWITCH_DISCONNECT) ? + CONFIG_BD9995X_POWER_SAVE_MODE : + BD9995X_PWR_SAVE_OFF); #endif - bd9995x_update_ucd_set_reg(CHARGER_SOLO, port, - BD9995X_CMD_UCD_SET_USB_SW, - usb_switch_state[port] == USB_SWITCH_CONNECT); + bd9995x_update_ucd_set_reg( + CHARGER_SOLO, port, BD9995X_CMD_UCD_SET_USB_SW, + usb_switch_state[port] == USB_SWITCH_CONNECT); } void bd9995x_vbus_interrupt(enum gpio_signal signal) @@ -1337,8 +1337,11 @@ static void bd9995x_usb_charger_task_init(const int unused) * provided, then disable wait for this port. */ bc12_det_mark[port] = - usb_charger_process(CHARGER_SOLO, port) - ? get_time().val + BC12_DETECT_US : 0; + usb_charger_process(CHARGER_SOLO, + port) ? + get_time().val + + BC12_DETECT_US : + 0; changed = 1; } #ifdef CONFIG_USB_PD_DISCHARGE @@ -1346,21 +1349,22 @@ static void bd9995x_usb_charger_task_init(const int unused) !initialized) { /* Get VBUS voltage */ vbus_reg = (port == BD9995X_CHARGE_PORT_VBUS) ? - BD9995X_CMD_VBUS_VAL : - BD9995X_CMD_VCC_VAL; + BD9995X_CMD_VBUS_VAL : + BD9995X_CMD_VCC_VAL; if (ch_raw_read16(CHARGER_SOLO, vbus_reg, &voltage, BD9995X_EXTENDED_COMMAND)) voltage = 0; /* Set discharge accordingly */ - pd_set_vbus_discharge(port, + pd_set_vbus_discharge( + port, voltage < BD9995X_VBUS_DISCHARGE_TH); changed = 1; } #endif - if (bc12_det_mark[port] && (get_time().val > - bc12_det_mark[port])) { + if (bc12_det_mark[port] && + (get_time().val > bc12_det_mark[port])) { /* * bc12_type result should be available. If not * available still, then function will return @@ -1371,7 +1375,8 @@ static void bd9995x_usb_charger_task_init(const int unused) bc12_det_mark[port] = bd9995x_bc12_check_type(CHARGER_SOLO, port) ? - get_time().val + 100 * MSEC : 0; + get_time().val + 100 * MSEC : + 0; /* Reset BC1.2 regs to skip auto-detection. */ bd9995x_bc12_detect(CHARGER_SOLO, port, 0); } @@ -1386,8 +1391,8 @@ static void bd9995x_usb_charger_task_init(const int unused) if (bc12_det_mark[port]) { int bc12_wait_usec; - bc12_wait_usec = bc12_det_mark[port] - - get_time().val; + bc12_wait_usec = + bc12_det_mark[port] - get_time().val; if ((sleep_usec < 0) || (sleep_usec > bc12_wait_usec)) sleep_usec = bc12_wait_usec; @@ -1396,40 +1401,43 @@ static void bd9995x_usb_charger_task_init(const int unused) initialized = 1; #ifdef CONFIG_BD9995X_DELAY_INPUT_PORT_SELECT -/* - * When a charge port is selected and VBUS is 5V, the inrush current on some - * devices causes VBUS to droop, which could signal a sink disconnection. - * - * To mitigate the problem, charge port selection is delayed until VBUS - * is stable or one second has passed. Hopefully PD has negotiated a VBUS - * voltage of at least 9V before the one second timeout. - */ - if (select_input_port_update) { - sleep_usec = VBUS_CHECK_MSEC; - changed = 0; - - switch (vbus_state) { - case START: - vbus_timeout = get_time().val + STABLE_TIMEOUT; - vbus_state = STABLE; - break; - case STABLE: - if (get_time().val > vbus_timeout) { - vbus_state = DEBOUNCE; - vbus_timeout = get_time().val + - DEBOUNCE_TIMEOUT; - } - break; - case DEBOUNCE: - if (bd9995x_vbus_debounce(CHARGER_SOLO, port_update) || - get_time().val > vbus_timeout) { - select_input_port_update = 0; - bd9995x_select_input_port_private( + /* + * When a charge port is selected and VBUS is 5V, the inrush + * current on some devices causes VBUS to droop, which could + * signal a sink disconnection. + * + * To mitigate the problem, charge port selection is delayed + * until VBUS is stable or one second has passed. Hopefully PD + * has negotiated a VBUS voltage of at least 9V before the one + * second timeout. + */ + if (select_input_port_update) { + sleep_usec = VBUS_CHECK_MSEC; + changed = 0; + + switch (vbus_state) { + case START: + vbus_timeout = get_time().val + STABLE_TIMEOUT; + vbus_state = STABLE; + break; + case STABLE: + if (get_time().val > vbus_timeout) { + vbus_state = DEBOUNCE; + vbus_timeout = get_time().val + + DEBOUNCE_TIMEOUT; + } + break; + case DEBOUNCE: + if (bd9995x_vbus_debounce(CHARGER_SOLO, + port_update) || + get_time().val > vbus_timeout) { + select_input_port_update = 0; + bd9995x_select_input_port_private( port_update, select_update); + } + break; } - break; } - } #endif /* @@ -1445,7 +1453,6 @@ static void bd9995x_usb_charger_task_init(const int unused) } #endif /* HAS_TASK_USB_CHG */ - /*** Console commands ***/ #ifdef CONFIG_CMD_CHARGER_DUMP static int read_bat(int chgnum, uint8_t cmd) @@ -1472,8 +1479,8 @@ static void console_bd9995x_dump_regs(int chgnum) /* Battery group registers */ for (i = 0; i < ARRAY_SIZE(regs); ++i) - ccprintf("BAT REG %4x: %4x\n", regs[i], read_bat(CHARGER_SOLO, - regs[i])); + ccprintf("BAT REG %4x: %4x\n", regs[i], + read_bat(CHARGER_SOLO, regs[i])); /* Extended group registers */ for (i = 0; i < 0x7f; ++i) { @@ -1538,7 +1545,7 @@ static int bd9995x_psys_charger_adc(int chgnum) for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) { if (ch_raw_read16(chgnum, BD9995X_CMD_PMON_DACIN_VAL, ®, - BD9995X_EXTENDED_COMMAND)) + BD9995X_EXTENDED_COMMAND)) return 0; /* Conversion Interval is 200us */ @@ -1550,8 +1557,8 @@ static int bd9995x_psys_charger_adc(int chgnum) * Calculate power in mW * PSYS = VACP×IACP+VBAT×IBAT = IPMON / GPMON */ - return (int) ((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) * - BD9995X_PMON_IOUT_ADC_READ_COUNT)); + return (int)((ipmon * 1000) / (BIT(BD9995X_PSYS_GAIN_SELECT) * + BD9995X_PMON_IOUT_ADC_READ_COUNT)); } static int bd9995x_enable_psys(int chgnum) @@ -1560,7 +1567,7 @@ static int bd9995x_enable_psys(int chgnum) int reg; rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -1571,7 +1578,7 @@ static int bd9995x_enable_psys(int chgnum) BD9995X_PSYS_GAIN_SELECT); return ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); } /** @@ -1591,12 +1598,11 @@ static int console_command_psys(int argc, char **argv) return rv; CPRINTS("PSYS from chg_adc: %d mW", - bd9995x_psys_charger_adc(CHARGER_SOLO)); + bd9995x_psys_charger_adc(CHARGER_SOLO)); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(psys, console_command_psys, - NULL, +DECLARE_CONSOLE_COMMAND(psys, console_command_psys, NULL, "Get the system power in mW"); #endif /* CONFIG_CHARGER_PSYS_READ */ @@ -1609,7 +1615,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum) for (i = 0; i < BD9995X_PMON_IOUT_ADC_READ_COUNT; i++) { ch_raw_read16(chgnum, BD9995X_CMD_IOUT_DACIN_VAL, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); iout += reg; /* Conversion Interval is 200us */ @@ -1625,7 +1631,7 @@ static int bd9995x_amon_bmon_chg_adc(int chgnum) * VIADP = GIADP * (VACP- VACN) = GIADP * IADP / IADP_RES */ return (iout * (5 << BD9995X_IOUT_GAIN_SELECT)) / - (10 * BD9995X_PMON_IOUT_ADC_READ_COUNT); + (10 * BD9995X_PMON_IOUT_ADC_READ_COUNT); } static int bd9995x_amon_bmon(int chgnum, int amon_bmon) @@ -1636,7 +1642,7 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon) int sns_res; rv = ch_raw_read16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, ®, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; @@ -1655,16 +1661,14 @@ static int bd9995x_amon_bmon(int chgnum, int amon_bmon) } rv = ch_raw_write16(chgnum, BD9995X_CMD_PMON_IOUT_CTRL_SET, reg, - BD9995X_EXTENDED_COMMAND); + BD9995X_EXTENDED_COMMAND); if (rv) return rv; imon = bd9995x_amon_bmon_chg_adc(chgnum); - CPRINTS("%cMON from chg_adc: %d uV, %d mA]", - amon_bmon ? 'A' : 'B', - imon * sns_res, - imon); + CPRINTS("%cMON from chg_adc: %d uV, %d mA]", amon_bmon ? 'A' : 'B', + imon * sns_res, imon); return EC_SUCCESS; } @@ -1686,8 +1690,7 @@ static int console_command_amon_bmon(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon, - "amonbmon [a|b]", +DECLARE_CONSOLE_COMMAND(amonbmon, console_command_amon_bmon, "amonbmon [a|b]", "Get charger AMON/BMON voltage diff, current"); #endif /* CONFIG_CMD_CHARGER_ADC_AMON_BMON */ @@ -1741,28 +1744,32 @@ const struct charger_drv bd9995x_drv = { /* provide a default bc12_ports[] for backward compatibility */ struct bc12_config bc12_ports[BD9995X_CHARGE_PORT_COUNT] = { { - .drv = &(const struct bc12_drv) { - .usb_charger_task_init = bd9995x_usb_charger_task_init, - /* events handled in init */ - .usb_charger_task_event = NULL, - .set_switches = bd9995x_set_switches, + .drv = + &(const struct bc12_drv){ + .usb_charger_task_init = + bd9995x_usb_charger_task_init, + /* events handled in init */ + .usb_charger_task_event = NULL, + .set_switches = bd9995x_set_switches, #if defined(CONFIG_CHARGE_RAMP_SW) - .ramp_allowed = bd9995x_ramp_allowed, - .ramp_max = bd9995x_ramp_max, + .ramp_allowed = bd9995x_ramp_allowed, + .ramp_max = bd9995x_ramp_max, #endif /* CONFIG_CHARGE_RAMP_SW */ - }, + }, }, { - .drv = &(const struct bc12_drv) { - /* bd9995x uses a single task thread for both ports */ - .usb_charger_task_init = NULL, - .usb_charger_task_event = NULL, - .set_switches = bd9995x_set_switches, + .drv = + &(const struct bc12_drv){ + /* bd9995x uses a single task thread for both + ports */ + .usb_charger_task_init = NULL, + .usb_charger_task_event = NULL, + .set_switches = bd9995x_set_switches, #if defined(CONFIG_CHARGE_RAMP_SW) - .ramp_allowed = bd9995x_ramp_allowed, - .ramp_max = bd9995x_ramp_max, + .ramp_allowed = bd9995x_ramp_allowed, + .ramp_max = bd9995x_ramp_max, #endif /* CONFIG_CHARGE_RAMP_SW */ - }, + }, }, }; BUILD_ASSERT(ARRAY_SIZE(bc12_ports) == CHARGE_PORT_COUNT); -- cgit v1.2.1 From 7bc7da0de49be5e3b138cfe54548419538aef794 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:34 -0600 Subject: cts/task/th.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idd6eefc97ba588574e19928e6dd25ab21c67db53 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729744 Reviewed-by: Jeremy Bettis --- cts/task/th.c | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 144 insertions(+), 1 deletion(-) mode change 120000 => 100644 cts/task/th.c diff --git a/cts/task/th.c b/cts/task/th.c deleted file mode 120000 index 41eab28462..0000000000 --- a/cts/task/th.c +++ /dev/null @@ -1 +0,0 @@ -dut.c \ No newline at end of file diff --git a/cts/task/th.c b/cts/task/th.c new file mode 100644 index 0000000000..d895301d61 --- /dev/null +++ b/cts/task/th.c @@ -0,0 +1,144 @@ +/* Copyright 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Tasks for scheduling test. + */ + +#include "common.h" +#include "cts_common.h" +#include "task.h" +#include "timer.h" + +static int repeat_count; +static int wake_count[3]; + +void clean_state(void) +{ + wake_count[0] = wake_count[1] = wake_count[2] = 0; +} + +void task_abc(void *data) +{ + int task_id = task_get_current(); + int id = task_id - TASK_ID_A; + task_id_t next = task_id + 1; + + if (next > TASK_ID_C) + next = TASK_ID_A; + + task_wait_event(-1); + + CPRINTS("%c Starting", 'A' + id); + cflush(); + + while (1) { + wake_count[id]++; + if (id == 2 && wake_count[id] == repeat_count) { + task_set_event(TASK_ID_CTS, TASK_EVENT_WAKE); + task_wait_event(0); + } else { + task_set_event(next, TASK_EVENT_WAKE); + task_wait_event(0); + } + } +} + +void task_tick(void *data) +{ + task_wait_event(-1); + ccprintf("\n[starting Task T]\n"); + + /* Wake up every tick */ + while (1) + /* Wait for timer interrupt message */ + usleep(3000); +} + +enum cts_rc test_task_switch(void) +{ + uint32_t event; + + repeat_count = 3000; + + task_wake(TASK_ID_A); + event = task_wait_event(5 * SECOND); + + if (event != TASK_EVENT_WAKE) { + CPRINTS("Woken up by unexpected event: 0x%08x", event); + return CTS_RC_FAILURE; + } + + if (wake_count[0] != repeat_count || wake_count[1] != repeat_count) { + CPRINTS("Unexpected counter values: %d %d %d", wake_count[0], + wake_count[1], wake_count[2]); + return CTS_RC_FAILURE; + } + + /* TODO: Verify no tasks are ready, no events are pending. */ + if (*task_get_event_bitmap(TASK_ID_A) || + *task_get_event_bitmap(TASK_ID_B) || + *task_get_event_bitmap(TASK_ID_C)) { + CPRINTS("Events are pending"); + return CTS_RC_FAILURE; + } + + return CTS_RC_SUCCESS; +} + +enum cts_rc test_task_priority(void) +{ + uint32_t event; + + repeat_count = 2; + + task_wake(TASK_ID_A); + task_wake(TASK_ID_C); + + event = task_wait_event(5 * SECOND); + + if (event != TASK_EVENT_WAKE) { + CPRINTS("Woken up by unexpected event: 0x%08x", event); + return CTS_RC_FAILURE; + } + + if (wake_count[0] != repeat_count - 1 || + wake_count[1] != repeat_count - 1) { + CPRINTS("Unexpected counter values: %d %d %d", wake_count[0], + wake_count[1], wake_count[2]); + return CTS_RC_FAILURE; + } + + /* TODO: Verify no tasks are ready, no events are pending. */ + if (*task_get_event_bitmap(TASK_ID_A) || + *task_get_event_bitmap(TASK_ID_B) || + *task_get_event_bitmap(TASK_ID_C)) { + CPRINTS("Events are pending"); + return CTS_RC_FAILURE; + } + + return CTS_RC_SUCCESS; +} + +static void recurse(int x) +{ + CPRINTS("+%d", x); + msleep(1); + recurse(x + 1); + CPRINTS("-%d", x); +} + +enum cts_rc test_stack_overflow(void) +{ + recurse(0); + return CTS_RC_FAILURE; +} + +#include "cts_testlist.h" + +void cts_task(void) +{ + task_wake(TASK_ID_TICK); + cts_main_loop(tests, "Task"); + task_wait_event(-1); +} -- cgit v1.2.1 From 3d3a9845ab0b5e91790762c9cdfa5d96c2159403 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:13 -0600 Subject: zephyr/shim/include/zephyr_hooks_shim.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iab0cb2581bed09e61b3d05b03828510ff24c8df8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730858 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_hooks_shim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/zephyr_hooks_shim.h b/zephyr/shim/include/zephyr_hooks_shim.h index 1798a42aeb..3f9819b43a 100644 --- a/zephyr/shim/include/zephyr_hooks_shim.h +++ b/zephyr/shim/include/zephyr_hooks_shim.h @@ -31,7 +31,7 @@ int hook_call_deferred(const struct deferred_data *data, int us); K_WORK_DELAYABLE_DEFINE(routine##_work_data, \ (void (*)(struct k_work *))routine); \ __maybe_unused const struct deferred_data routine##_data = { \ - .work = &routine##_work_data, \ + .work = &routine##_work_data, \ } /** -- cgit v1.2.1 From 41bcb5137905b045ad4273be4a7b3a47b419a4c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:36 -0600 Subject: test/body_detection_data_literals.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8913f0d69df2192cf1dfafda65cf7f100cb088c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730471 Reviewed-by: Jeremy Bettis --- test/body_detection_data_literals.c | 12380 +++++++++++++++++----------------- 1 file changed, 6190 insertions(+), 6190 deletions(-) diff --git a/test/body_detection_data_literals.c b/test/body_detection_data_literals.c index 96a0cc2f8f..c24430bdb0 100644 --- a/test/body_detection_data_literals.c +++ b/test/body_detection_data_literals.c @@ -6,6208 +6,6208 @@ const struct body_detect_test_data kBodyDetectOnBodyTestData[] = { /* x, y, z, action*/ - {3.233367f, 1.968032f, 8.875299f, 0}, - {3.190272f, 2.127247f, 9.054865f, 0}, - {3.361457f, 2.057815f, 9.054865f, 0}, - {3.377019f, 1.917754f, 9.093172f, 0}, - {3.460816f, 1.817198f, 9.058456f, 0}, - {3.500320f, 1.726218f, 8.900438f, 0}, - {3.715799f, 1.363497f, 8.836992f, 0}, - {3.883393f, 0.884657f, 8.832204f, 0}, - {3.948036f, 0.577002f, 9.016558f, 0}, - {3.600877f, 0.717063f, 9.200911f, 0}, - {3.318361f, 0.854729f, 9.166195f, 0}, - {3.272871f, 0.731428f, 9.149436f, 0}, - {3.452436f, 0.250194f, 9.297876f, 0}, - {3.817552f, -0.353144f, 9.424768f, 0}, - {3.828326f, -0.495599f, 9.284708f, 0}, - {3.312376f, -0.040701f, 9.204502f, 0}, - {3.049014f, 0.515950f, 9.223656f, 0}, - {3.099292f, 0.980425f, 8.882483f, 0}, - {3.153162f, 1.443703f, 8.154645f, 0}, - {3.501518f, 1.487995f, 8.054089f, 0}, - {4.235340f, 1.292868f, 8.480257f, 0}, - {4.284421f, 1.511937f, 8.848964f, 0}, - {3.988737f, 1.928528f, 9.149436f, 0}, - {3.825932f, 2.076969f, 9.576800f, 0}, - {3.903743f, 1.991974f, 10.133451f, 0}, - {3.841494f, 2.000354f, 10.165773f, 0}, - {3.706222f, 1.930922f, 9.649823f, 0}, - {3.949233f, 1.614888f, 9.054865f, 0}, - {4.237734f, 1.272517f, 8.625106f, 0}, - {4.188653f, 1.134851f, 8.268370f, 0}, - {4.242523f, 0.991199f, 8.091199f, 0}, - {4.157528f, 0.970848f, 8.135491f, 0}, - {3.951627f, 0.967257f, 8.353364f, 0}, - {4.073731f, 0.994790f, 8.854949f, 0}, - {3.840297f, 1.124077f, 9.249992f, 0}, - {3.736149f, 1.142033f, 9.491806f, 0}, - {3.809172f, 1.126471f, 9.651020f, 0}, - {3.987540f, 1.173158f, 9.633064f, 0}, - {4.237734f, 1.005564f, 9.467864f, 0}, - {4.308363f, 0.939724f, 9.190137f, 0}, - {4.367021f, 0.986410f, 9.021346f, 0}, - {4.406525f, 1.033097f, 9.074018f, 0}, - {4.185062f, 1.276109f, 9.235627f, 0}, - {3.971978f, 1.363497f, 9.525325f, 0}, - {4.031833f, 1.318007f, 10.833755f, 0}, - {4.214989f, 1.144428f, 10.241191f, 0}, - {4.808751f, 0.590170f, 9.690525f, 0}, - {4.697421f, 0.372298f, 10.245979f, 0}, - {4.490322f, 0.207098f, 9.682145f, 0}, - {4.353853f, 0.494402f, 8.651442f, 0}, - {3.981555f, 1.094149f, 8.230062f, 0}, - {3.933671f, 1.310825f, 8.426387f, 0}, - {4.107250f, 1.189917f, 9.068033f, 0}, - {4.529827f, 0.888248f, 9.501383f, 0}, - {4.699815f, 0.720654f, 9.765942f, 0}, - {4.661508f, 0.647631f, 9.916777f, 0}, - {4.627989f, 0.587776f, 9.925157f, 0}, - {4.413708f, 0.587776f, 9.791081f, 0}, - {4.369415f, 0.466869f, 9.840162f, 0}, - {4.412511f, 0.335188f, 9.932339f, 0}, - {4.234143f, 0.452504f, 9.502580f, 0}, - {3.817552f, 1.055842f, 8.638274f, 0}, - {3.130417f, 1.842337f, 7.748828f, 0}, - {2.511516f, 2.430113f, 7.059299f, 0}, - {2.267308f, 2.840718f, 6.742067f, 0}, - {2.082954f, 3.129220f, 6.706154f, 0}, - {1.653195f, 3.483561f, 6.813893f, 0}, - {1.053448f, 3.797201f, 7.132322f, 0}, - {0.333991f, 4.125207f, 7.364560f, 0}, - {-0.039504f, 4.228158f, 8.018176f, 0}, - {0.403423f, 3.726573f, 8.789108f, 0}, - {1.179144f, 3.120840f, 9.289496f, 0}, - {1.683123f, 2.905362f, 9.911988f, 0}, - {1.442506f, 3.038240f, 10.551240f, 0}, - {1.403001f, 2.936486f, 12.229574f, 0}, - {1.601720f, 2.541443f, 14.815310f, 0}, - {2.233789f, 2.037464f, 14.715951f, 0}, - {2.664745f, 1.736992f, 12.216406f, 0}, - {3.331529f, 1.385045f, 10.475822f, 0}, - {3.337515f, 1.235407f, 9.133873f, 0}, - {3.173512f, 1.292868f, 8.406036f, 0}, - {3.201046f, 1.462856f, 8.306677f, 0}, - {3.157950f, 1.595734f, 9.011769f, 0}, - {2.759315f, 1.777694f, 10.049655f, 0}, - {2.315192f, 2.105699f, 10.682920f, 0}, - {2.063801f, 2.375046f, 10.832559f, 0}, - {2.310403f, 2.485180f, 10.688907f, 0}, - {2.553414f, 2.606087f, 10.153803f, 0}, - {2.475603f, 2.731782f, 9.356534f, 0}, - {2.710234f, 2.529472f, 9.297876f, 0}, - {2.777272f, 2.193087f, 9.394841f, 0}, - {2.938881f, 1.920148f, 9.531310f, 0}, - {3.108869f, 1.635239f, 10.534480f, 0}, - {3.187877f, 1.425746f, 10.899596f, 0}, - {3.448845f, 1.331175f, 10.508144f, 0}, - {3.606862f, 1.470039f, 9.440331f, 0}, - {3.700236f, 1.162384f, 8.781926f, 0}, - {3.713404f, 0.864306f, 8.845372f, 0}, - {3.575738f, 0.404620f, 9.610319f, 0}, - {3.495532f, -0.130484f, 9.526522f, 0}, - {3.403355f, -0.411802f, 8.833401f, 0}, - {3.203440f, -0.380678f, 8.850161f, 0}, - {2.822762f, -0.191536f, 9.560040f, 0}, - {2.488771f, -0.459686f, 9.883258f, 0}, - {3.065773f, -0.764947f, 10.110707f, 0}, - {1.993172f, 1.004367f, 9.798264f, 0}, - {2.426522f, 1.732204f, 10.036487f, 0}, - {3.213017f, 1.238999f, 10.182533f, 0}, - {2.779666f, 2.394200f, 9.916777f, 0}, - {3.187877f, 2.622846f, 9.593559f, 0}, - {4.195836f, 1.867476f, 9.876076f, 0}, - {3.720587f, 2.114079f, 9.998179f, 0}, - {2.948457f, 2.766498f, 9.500186f, 0}, - {3.869027f, 2.822762f, 9.572012f, 0}, - {4.205412f, 2.656365f, 9.753971f, 0}, - {4.151543f, 2.828747f, 9.751576f, 0}, - {4.046198f, 2.905362f, 9.131479f, 0}, - {3.915714f, 3.032254f, 8.237246f, 0}, - {3.864239f, 3.126825f, 8.008599f, 0}, - {3.466802f, 2.999933f, 8.634683f, 0}, - {2.876631f, 2.902968f, 9.473849f, 0}, - {2.329557f, 2.899376f, 10.187322f, 0}, - {2.197876f, 3.608059f, 10.637431f, 0}, - {2.357090f, 4.205412f, 10.235206f, 0}, - {2.716220f, 4.076126f, 9.261963f, 0}, - {3.520671f, 3.847480f, 8.461103f, 0}, - {4.180274f, 3.879801f, 7.758405f, 0}, - {4.691435f, 4.034227f, 7.019794f, 0}, - {4.918884f, 3.915714f, 6.659468f, 0}, - {4.722559f, 4.205412f, 6.113590f, 0}, - {5.349840f, 4.169499f, 5.413286f, 0}, - {6.423639f, 3.742135f, 5.009864f, 0}, - {6.799528f, 3.581723f, 4.843467f, 0}, - {6.915647f, 3.337515f, 4.921278f, 0}, - {7.358574f, 3.173512f, 5.214568f, 0}, - {7.584826f, 2.861069f, 5.182246f, 0}, - {7.077255f, 2.771286f, 5.073310f, 0}, - {7.192177f, 2.306812f, 5.501872f, 0}, - {7.241258f, 2.145203f, 5.888535f, 0}, - {7.599191f, 1.898601f, 6.099225f, 0}, - {7.576446f, 2.138021f, 6.144714f, 0}, - {7.465116f, 1.962047f, 6.021413f, 0}, - {7.677002f, 1.740583f, 5.643129f, 0}, - {7.966701f, 1.648407f, 4.964374f, 0}, - {8.038527f, 1.636436f, 4.419693f, 0}, - {8.176193f, 1.582566f, 4.183865f, 0}, - {8.489834f, 1.460462f, 4.319137f, 0}, - {8.804670f, 1.314416f, 4.444832f, 0}, - {8.803473f, 1.308430f, 4.492716f, 0}, - {8.580813f, 1.392227f, 4.501096f, 0}, - {8.056483f, 1.595734f, 4.428073f, 0}, - {8.418008f, 1.316810f, 4.600455f, 0}, - {8.826219f, 1.170764f, 4.411314f, 0}, - {8.652639f, 1.201888f, 3.910926f, 0}, - {8.285130f, 0.927753f, 3.752909f, 0}, - {8.475469f, 1.027112f, 3.569752f, 0}, - {9.009375f, 0.708683f, 3.605665f, 0}, - {8.797488f, 0.600944f, 3.107672f, 0}, - {8.864526f, 0.620098f, 2.863463f, 0}, - {8.833401f, 0.214281f, 2.640803f, 0}, - {9.212882f, 0.150835f, 2.487574f, 0}, - {9.308650f, 0.226252f, 2.375046f, 0}, - {8.869314f, 0.094571f, 2.142809f, 0}, - {9.208094f, 0.002394f, 2.132035f, 0}, - {9.100354f, 0.015562f, 2.367864f, 0}, - {8.973462f, -0.011971f, 2.602495f, 0}, - {8.872906f, 0.000000f, 2.564188f, 0}, - {8.883679f, 0.092177f, 2.452858f, 0}, - {8.857343f, 0.241814f, 2.480391f, 0}, - {8.919592f, 0.371101f, 2.612072f, 0}, - {9.002192f, 0.483628f, 2.536655f, 0}, - {9.056062f, 0.521936f, 2.335542f, 0}, - {9.023740f, 0.572214f, 2.012325f, 0}, - {9.085989f, 0.592565f, 1.854308f, 0}, - {9.127888f, 0.505176f, 1.783679f, 0}, - {8.968674f, 0.653617f, 1.787270f, 0}, - {8.872906f, 0.650025f, 1.867476f, 0}, - {8.798685f, 0.628478f, 2.148795f, 0}, - {8.841781f, 0.530315f, 2.687490f, 0}, - {8.541308f, 0.642843f, 2.780863f, 0}, - {8.499411f, 0.402226f, 2.566582f, 0}, - {8.734042f, -0.217872f, 2.597707f, 0}, - {8.689749f, -0.295684f, 3.051408f, 0}, - {8.298298f, -0.123301f, 3.968387f, 0}, - {7.545321f, -0.111330f, 4.738122f, 0}, - {6.827062f, -0.112527f, 5.501872f, 0}, - {6.604401f, 0.435744f, 6.827062f, 0}, - {6.572079f, 0.610521f, 7.642287f, 0}, - {6.546940f, 0.383072f, 7.778756f, 0}, - {6.274001f, 0.530315f, 7.600388f, 0}, - {5.847834f, 1.544259f, 7.811078f, 0}, - {5.374979f, 1.781285f, 7.654258f, 0}, - {5.163093f, 1.493981f, 7.372939f, 0}, - {5.104434f, 1.314416f, 7.807487f, 0}, - {5.424060f, 0.847547f, 8.513776f, 0}, - {5.471944f, 0.817619f, 8.461103f, 0}, - {4.618412f, 1.319204f, 8.107959f, 0}, - {4.265267f, 1.634042f, 7.587220f, 0}, - {5.191823f, 1.347935f, 7.196965f, 0}, - {4.748896f, 1.868673f, 7.097606f, 0}, - {4.595667f, 1.187523f, 7.428006f, 0}, - {3.948036f, 1.272517f, 8.262384f, 0}, - {2.280476f, 1.892615f, 8.998601f, 0}, - {2.828747f, 1.725021f, 8.937549f, 0}, - {3.256112f, 1.863885f, 9.101552f, 0}, - {3.264492f, 1.679531f, 8.540112f, 0}, - {3.616439f, 1.237801f, 8.178588f, 0}, - {3.713404f, 1.492784f, 9.411600f, 0}, - {3.654746f, 1.428140f, 10.740381f, 0}, - {3.139993f, 1.246181f, 10.362098f, 0}, - {2.381032f, 1.161187f, 9.357731f, 0}, - {2.602495f, 1.027112f, 11.311399f, 0}, - {2.964020f, 1.120486f, 12.570747f, 0}, - {2.501939f, 1.344343f, 10.244782f, 0}, - {2.152386f, 1.455674f, 9.786293f, 0}, - {1.878250f, 1.450885f, 10.216052f, 0}, - {1.844731f, 1.434126f, 12.245136f, 0}, - {2.011128f, 1.198297f, 13.654123f, 0}, - {1.562216f, 1.192312f, 10.202884f, 0}, - {1.046265f, 1.596931f, 8.796291f, 0}, - {1.344343f, 1.769314f, 9.710876f, 0}, - {1.857899f, 1.845928f, 10.510538f, 0}, - {2.217029f, 1.814804f, 11.314989f, 0}, - {2.341528f, 1.612494f, 11.218024f, 0}, - {2.144006f, 1.527500f, 10.122678f, 0}, - {2.220621f, 1.271320f, 10.222037f, 0}, - {2.487574f, 0.978031f, 10.830164f, 0}, - {2.782060f, 0.950497f, 11.261120f, 0}, - {3.031057f, 0.894234f, 10.802630f, 0}, - {2.880223f, 0.992396f, 9.764745f, 0}, - {2.115276f, 1.447294f, 8.930367f, 0}, - {1.849520f, 1.715444f, 8.956702f, 0}, - {2.313994f, 1.569398f, 9.429557f, 0}, - {2.365470f, 1.504755f, 9.142253f, 0}, - {2.184708f, 1.528697f, 8.570039f, 0}, - {2.346316f, 1.491587f, 8.657428f, 0}, - {2.662350f, 1.338358f, 8.938745f, 0}, - {2.619255f, 1.200691f, 8.894453f, 0}, - {2.372652f, 1.073799f, 8.850161f, 0}, - {2.363075f, 1.012747f, 9.173378f, 0}, - {2.529472f, 1.101332f, 9.485821f, 0}, - {2.730585f, 1.132457f, 9.469061f, 0}, - {2.913742f, 1.120486f, 9.311044f, 0}, - {3.093307f, 1.151610f, 9.610319f, 0}, - {3.087321f, 1.296459f, 10.226826f, 0}, - {2.811988f, 1.377862f, 10.601518f, 0}, - {2.683898f, 1.231816f, 10.516523f, 0}, - {2.584539f, 1.250970f, 10.043670f, 0}, - {2.732979f, 1.283291f, 9.721649f, 0}, - {2.949655f, 1.004367f, 9.597151f, 0}, - {2.908953f, 0.938526f, 9.525325f, 0}, - {2.630029f, 1.124077f, 9.534902f, 0}, - {2.710234f, 0.859518f, 9.769533f, 0}, - {2.574962f, 0.883460f, 9.832980f, 0}, - {2.279279f, 1.092952f, 9.628276f, 0}, - {2.272096f, 1.016338f, 9.598348f, 0}, - {2.448070f, 0.889445f, 9.724044f, 0}, - {2.395397f, 0.984016f, 9.685737f, 0}, - {2.266110f, 1.094149f, 9.788687f, 0}, - {2.366667f, 1.074996f, 9.836571f, 0}, - {2.486377f, 1.023521f, 9.856922f, 0}, - {2.391806f, 1.103726f, 9.935930f, 0}, - {2.179919f, 1.174355f, 9.900018f, 0}, - {2.024296f, 1.203086f, 9.925157f, 0}, - {2.039858f, 1.156399f, 9.900018f, 0}, - {2.087743f, 1.066616f, 9.976632f, 0}, - {2.084151f, 0.975637f, 9.853331f, 0}, - {2.179919f, 0.985213f, 9.618699f, 0}, - {2.300826f, 1.031900f, 9.533705f, 0}, - {2.246957f, 1.083376f, 9.599545f, 0}, - {2.124853f, 0.970848f, 9.703692f, 0}, - {2.005142f, 1.036689f, 9.664188f, 0}, - {2.142809f, 1.047463f, 9.641443f, 0}, - {2.340331f, 0.885854f, 9.666583f, 0}, - {2.238577f, 0.888248f, 9.624684f, 0}, - {2.110487f, 0.960074f, 9.634261f, 0}, - {2.123656f, 1.030703f, 9.668977f, 0}, - {2.196679f, 1.061828f, 9.731226f, 0}, - {2.325965f, 0.931344f, 9.607924f, 0}, - {2.492362f, 0.841561f, 9.391250f, 0}, - {2.663548f, 0.991199f, 9.607924f, 0}, - {2.663548f, 0.933738f, 9.994588f, 0}, - {2.318783f, 0.817619f, 9.791081f, 0}, - {1.841140f, 0.946906f, 9.582786f, 0}, - {1.580172f, 1.162384f, 9.424768f, 0}, - {1.405395f, 1.210268f, 9.209291f, 0}, - {1.625662f, 1.034294f, 9.338577f, 0}, - {1.824380f, 1.120486f, 9.599545f, 0}, - {1.843534f, 1.120486f, 10.004165f, 0}, - {2.057815f, 0.648828f, 10.226826f, 0}, - {2.493559f, 0.673967f, 9.695313f, 0}, - {2.706643f, 0.766144f, 9.198517f, 0}, - {2.315192f, 0.678756f, 8.605952f, 0}, - {1.771708f, 0.752976f, 8.489834f, 0}, - {1.243787f, 0.969651f, 9.085989f, 0}, - {1.102529f, 0.957680f, 9.589969f, 0}, - {0.967257f, 0.730231f, 9.928748f, 0}, - {0.428562f, 0.812831f, 10.267527f, 0}, - {0.254982f, 1.097741f, 10.530889f, 0}, - {0.830787f, 1.238999f, 10.898398f, 0}, - {1.181538f, 1.061828f, 11.079161f, 0}, - {1.320401f, 1.142033f, 11.312595f, 0}, - {1.430535f, 0.967257f, 11.358085f, 0}, - {1.130062f, 0.909796f, 11.218024f, 0}, - {0.805648f, 0.810437f, 11.358085f, 0}, - {0.553060f, 0.751779f, 11.392801f, 0}, - {0.617704f, 0.609324f, 11.170140f, 0}, - {0.879869f, 0.511162f, 11.275485f, 0}, - {0.829590f, 0.587776f, 11.293442f, 0}, - {0.312443f, 0.672770f, 11.064795f, 0}, - {0.293290f, 0.867898f, 10.777492f, 0}, - {0.509965f, 0.920570f, 10.351324f, 0}, - {0.536301f, 1.023521f, 10.133451f, 0}, - {0.774524f, 1.107318f, 10.016136f, 0}, - {1.381453f, 0.903811f, 9.916777f, 0}, - {1.589749f, 0.810437f, 9.695313f, 0}, - {1.593340f, 0.811634f, 9.537296f, 0}, - {1.824380f, 0.887051f, 9.521733f, 0}, - {1.902192f, 0.964863f, 9.576800f, 0}, - {1.674743f, 1.398213f, 9.964661f, 0}, - {1.234210f, 1.440111f, 9.610319f, 0}, - {1.334767f, 1.115697f, 9.568420f, 0}, - {1.393424f, 1.659181f, 9.431952f, 0}, - {1.001973f, 2.656365f, 9.647429f, 0}, - {0.780509f, 3.013101f, 9.451105f, 0}, - {1.270123f, 3.008312f, 9.417586f, 0}, - {1.909375f, 3.031057f, 9.946704f, 0}, - {1.747766f, 3.309982f, 9.271540f, 0}, - {1.356314f, 3.300405f, 8.287523f, 0}, - {0.751779f, 3.156753f, 7.970292f, 0}, - {0.063446f, 3.359063f, 8.893256f, 0}, - {0.136469f, 3.002327f, 8.529338f, 0}, - {0.253785f, 3.015495f, 8.072045f, 0}, - {-0.045490f, 3.882195f, 8.609544f, 0}, - {0.149638f, 4.250902f, 9.435542f, 0}, - {1.071405f, 3.465605f, 9.838965f, 0}, - {1.856702f, 3.051408f, 11.276682f, 0}, - {2.770089f, 2.961626f, 10.789463f, 0}, - {3.514686f, 2.636014f, 7.386107f, 0}, - {3.545810f, 2.828747f, 7.304704f, 0}, - {3.815158f, 3.108869f, 6.725308f, 0}, - {3.323150f, 3.184286f, 4.733334f, 0}, - {2.572568f, 3.155556f, 6.907267f, 0}, - {3.299208f, 2.012325f, 9.501383f, 0}, - {3.531445f, 2.621649f, 8.761575f, 0}, - {4.510673f, 3.228579f, 12.022475f, 0}, - {6.127955f, 1.776496f, 13.516457f, 0}, - {5.631158f, 1.547850f, 11.772282f, 0}, - {5.889732f, -0.058658f, 7.119154f, 0}, - {4.481943f, 1.406592f, 6.591233f, 0}, - {4.230552f, 1.640027f, 9.447514f, 0}, - {4.007891f, 0.654814f, 11.417940f, 0}, - {4.525038f, 0.415394f, 11.757916f, 0}, - {4.125207f, 0.555454f, 10.915158f, 0}, - {3.624819f, 0.526724f, 9.951492f, 0}, - {3.210622f, 0.480037f, 10.086765f, 0}, - {3.298011f, 1.221042f, 9.670174f, 0}, - {3.142388f, 1.479616f, 9.212882f, 0}, - {2.955640f, 1.448491f, 8.816642f, 0}, - {3.101686f, 2.088940f, 9.536098f, 0}, - {3.215411f, 2.460041f, 9.319424f, 0}, - {3.247732f, 2.573765f, 8.180982f, 0}, - {3.251324f, 2.348710f, 8.084017f, 0}, - {3.372231f, 2.255337f, 9.076412f, 0}, - {3.545810f, 2.310403f, 9.700102f, 0}, - {3.739741f, 2.173934f, 9.156618f, 0}, - {3.809172f, 1.825577f, 9.087187f, 0}, - {3.727770f, 1.434126f, 9.709679f, 0}, - {3.596088f, 1.175552f, 10.115496f, 0}, - {3.452436f, 1.128865f, 9.888046f, 0}, - {3.217805f, 1.009155f, 9.366111f, 0}, - {3.197454f, 1.152807f, 9.042893f, 0}, - {3.360260f, 1.312022f, 8.710100f, 0}, - {3.630804f, 1.417366f, 8.561660f, 0}, - {3.858253f, 1.345540f, 8.723268f, 0}, - {4.018665f, 1.070207f, 9.018951f, 0}, - {4.181470f, 0.847547f, 9.135071f, 0}, - {4.359838f, 0.720654f, 9.123099f, 0}, - {4.487928f, 0.720654f, 9.082398f, 0}, - {4.380189f, 0.676362f, 9.085989f, 0}, - {4.357444f, 0.766144f, 9.149436f, 0}, - {4.260479f, 0.820014f, 8.944732f, 0}, - {4.271253f, 0.809240f, 9.156618f, 0}, - {4.315546f, 0.563834f, 9.089581f, 0}, - {4.484337f, 0.366313f, 8.816642f, 1}, - {4.460395f, 0.489614f, 8.925578f, 0}, - {4.448424f, 0.270545f, 9.436740f, 0}, - {4.559754f, 0.149638f, 9.291890f, 0}, - {4.551374f, 0.318429f, 8.737633f, 0}, - {4.523841f, 0.301669f, 8.877694f, 0}, - {4.411314f, 0.075417f, 9.094369f, 0}, - {4.203018f, -0.062249f, 9.162603f, 0}, - {4.171894f, -0.029928f, 8.957899f, 0}, - {4.235340f, -0.195127f, 9.186545f, 0}, - {4.386175f, -0.499191f, 9.753971f, 0}, - {4.505885f, -0.679953f, 10.381251f, 0}, - {4.586090f, -0.547075f, 10.471034f, 0}, - {4.892548f, -0.622492f, 9.931142f, 0}, - {5.498281f, -0.993593f, 9.714467f, 0}, - {5.907689f, -1.383848f, 9.782701f, 0}, - {6.193796f, -1.279700f, 9.963464f, 0}, - {6.526589f, -1.408987f, 8.862131f, 0}, - {6.619963f, -2.099714f, 7.775165f, 0}, - {6.324279f, -2.311600f, 7.964306f, 0}, - {5.984303f, -2.063801f, 9.196122f, 0}, - {5.639538f, -1.571792f, 8.735239f, 0}, - {5.276817f, -1.029506f, 7.680594f, 0}, - {5.011061f, -0.629675f, 7.769179f, 0}, - {4.618412f, -0.131681f, 8.444344f, 0}, - {4.189850f, 0.440533f, 8.780728f, 0}, - {4.214989f, 1.012747f, 8.608346f, 0}, - {4.211398f, 1.684320f, 8.520958f, 0}, - {4.193441f, 2.132035f, 9.264358f, 0}, - {4.256888f, 2.742556f, 9.690525f, 0}, - {4.542994f, 3.782836f, 9.542085f, 0}, - {5.335475f, 4.732136f, 8.649048f, 0}, - {5.679042f, 5.600034f, 7.328646f, 0}, - {5.938813f, 6.015428f, 5.878958f, 0}, - {5.702984f, 5.841848f, 3.946839f, 0}, - {5.978318f, 4.942826f, 2.680307f, 0}, - {6.204569f, 4.444832f, 3.429692f, 0}, - {6.102816f, 4.230552f, 4.288013f, 0}, - {6.244074f, 4.173091f, 4.954797f, 0}, - {6.355404f, 3.830720f, 5.212173f, 0}, - {7.004232f, 3.655943f, 4.850649f, 0}, - {7.965504f, 2.867055f, 4.497505f, 0}, - {8.603558f, 3.070562f, 4.267662f, 0}, - {9.105143f, 4.338291f, 4.809948f, 0}, - {8.657428f, 4.848255f, 3.834311f, 0}, - {7.819458f, 5.075704f, 0.330400f, 0}, - {7.815866f, 5.650312f, -3.190272f, 0}, - {7.144293f, 6.502647f, -10.860091f, 0}, - {7.374136f, 4.941629f, -7.758405f, 0}, - {8.832204f, 3.672703f, 0.448913f, 0}, - {9.153027f, 3.536233f, 0.270545f, 0}, - {8.880088f, 4.343079f, 0.025139f, 0}, - {8.923183f, 4.811145f, -0.472855f, 0}, - {9.080004f, 4.722559f, -0.604536f, 0}, - {9.029726f, 4.490322f, -0.079009f, 0}, - {9.149436f, 4.181470f, -0.168791f, 0}, - {9.192532f, 4.162317f, -0.488417f, 0}, - {9.105143f, 4.446030f, -0.647631f, 0}, - {9.289496f, 4.550177f, -0.691924f, 0}, - {9.198517f, 4.359838f, -0.305261f, 0}, - {8.995009f, 4.213792f, 0.192733f, 0}, - {8.955505f, 4.545389f, -0.177171f, 0}, - {8.451527f, 5.149924f, -1.136048f, 0}, - {7.418429f, 5.443214f, 0.033519f, 0}, - {6.846215f, 5.254072f, 2.087743f, 0}, - {7.192177f, 4.586090f, 3.452436f, 0}, - {7.727281f, 3.658338f, 3.614045f, 0}, - {8.420402f, 3.105278f, 2.424128f, 0}, - {9.446317f, 2.968808f, 1.719036f, 0}, - {9.706087f, 2.862266f, 2.051830f, 0}, - {9.520536f, 2.778469f, 2.466026f, 0}, - {9.439134f, 2.862266f, 3.065773f, 0}, - {8.769955f, 3.287237f, 3.415326f, 0}, - {8.048103f, 3.784033f, 2.977188f, 0}, - {7.817063f, 3.926488f, 1.849520f, 0}, - {8.365335f, 3.857056f, 0.901416f, 0}, - {8.749604f, 3.778048f, 0.855927f, 0}, - {7.741646f, 4.425679f, 1.212662f, 0}, - {6.775586f, 5.135559f, 1.638830f, 0}, - {7.811078f, 4.550177f, 3.052605f, 0}, - {8.285130f, 4.247311f, 3.077744f, 0}, - {8.590390f, 4.511870f, 2.555809f, 0}, - {8.787911f, 4.813539f, 2.319980f, 0}, - {8.252808f, 4.928461f, 1.952470f, 0}, - {7.679397f, 4.880577f, 1.568201f, 0}, - {7.946350f, 4.525038f, 1.531091f, 0}, - {8.236049f, 4.353853f, 1.537076f, 0}, - {8.593981f, 4.235340f, 1.843534f, 0}, - {8.511381f, 4.062957f, 1.691502f, 0}, - {8.268370f, 4.389766f, 1.649604f, 0}, - {8.129506f, 5.080492f, 1.691502f, 0}, - {8.280341f, 5.632356f, 1.444900f, 0}, - {8.936352f, 5.948390f, 1.972821f, 0}, - {10.184927f, 5.974726f, 3.705025f, 0}, - {11.186900f, 5.440820f, 3.477576f, 0}, - {11.239573f, 4.985922f, 1.543062f, 0}, - {11.077964f, 4.748896f, 1.107318f, 0}, - {10.912764f, 4.514264f, 1.528697f, 0}, - {10.890019f, 3.810369f, 1.624465f, 0}, - {9.329000f, 2.948457f, 1.057039f, 0}, - {7.509408f, 2.424128f, 1.201888f, 0}, - {7.207739f, 1.965638f, 1.035492f, 0}, - {7.030569f, 1.936908f, 0.076614f, 0}, - {6.907267f, 2.347513f, -0.646434f, 0}, - {7.483072f, 2.871843f, -0.088585f, 0}, - {8.190558f, 3.590103f, 1.675940f, 0}, - {8.498213f, 3.961204f, 1.974018f, 0}, - {8.552083f, 3.774457f, 1.284488f, 0}, - {8.402445f, 3.895364f, 2.099714f, 0}, - {8.273158f, 4.100068f, 2.432507f, 0}, - {8.030147f, 4.141966f, 1.668757f, 0}, - {7.900860f, 4.010285f, 1.027112f, 0}, - {7.912831f, 3.936065f, 0.803254f, 0}, - {7.878115f, 4.007891f, 0.687135f, 0}, - {7.789530f, 4.050986f, 0.326808f, 0}, - {8.213304f, 3.869027f, 0.050278f, 0}, - {8.558068f, 3.667914f, 0.016759f, 0}, - {8.617923f, 3.523065f, 0.405817f, 0}, - {8.524549f, 3.506306f, 0.683544f, 0}, - {8.438358f, 3.640381f, 0.433350f, 0}, - {8.262384f, 3.952824f, 0.190339f, 0}, - {8.115141f, 4.276042f, 0.306458f, 0}, - {8.386883f, 4.367021f, 0.554257f, 0}, - {8.827415f, 4.244917f, 0.985213f, 0}, - {9.200911f, 4.337093f, 0.806845f, 0}, - {10.524903f, 4.668690f, -0.792480f, 0}, - {11.640601f, 4.612426f, -1.328781f, 0}, - {11.060007f, 4.495111f, -0.488417f, 0}, - {9.582786f, 5.093661f, 0.833182f, 0}, - {9.582786f, 5.696999f, 1.917754f, 0}, - {10.176547f, 5.428849f, 1.911769f, 0}, - {10.186124f, 5.148727f, 2.031479f, 0}, - {9.921565f, 4.803962f, 2.525881f, 0}, - {9.082398f, 3.547007f, 2.503136f, 0}, - {8.127112f, 2.201467f, 3.013101f, 0}, - {8.121126f, 2.080560f, 3.895364f, 0}, - {7.538139f, 3.345895f, 3.219002f, 0}, - {7.010218f, 3.763683f, 2.015916f, 0}, - {7.691368f, 3.278857f, 1.988383f, 0}, - {9.029726f, 2.555809f, 2.470814f, 0}, - {9.815023f, 2.255337f, 1.878250f, 0}, - {9.594757f, 2.603693f, 0.724246f, 0}, - {8.785517f, 3.135205f, 0.660799f, 0}, - {8.186967f, 3.447648f, 1.098938f, 0}, - {7.940364f, 3.257309f, 1.605311f, 0}, - {7.721295f, 2.911347f, 1.705868f, 0}, - {7.763194f, 2.804805f, 1.307233f, 0}, - {8.137886f, 2.965217f, 1.130062f, 0}, - {8.329422f, 3.266886f, 1.200691f, 0}, - {8.224077f, 3.472787f, 1.547850f, 0}, - {7.841005f, 3.687068f, 1.614888f, 0}, - {7.527365f, 4.015073f, 1.435323f, 0}, - {7.979869f, 4.304772f, 1.449688f, 0}, - {6.466734f, 4.948812f, 0.798466f, 0}, - {5.912477f, 5.204991f, 0.487220f, 0}, - {8.413219f, 5.108026f, 3.270477f, 0}, - {9.945507f, 5.396527f, 3.342303f, 0}, - {10.691300f, 5.128376f, 2.308009f, 0}, - {10.842135f, 4.801568f, 1.601720f, 0}, - {9.938325f, 4.821919f, 1.177946f, 0}, - {8.507790f, 4.671084f, 1.237801f, 0}, - {8.838189f, 4.602849f, 2.097319f, 0}, - {10.510538f, 4.817131f, 2.170342f, 0}, - {12.216406f, 4.753684f, 1.561018f, 0}, - {12.654545f, 3.897758f, 0.378284f, 0}, - {11.204856f, 1.860294f, -0.105345f, 0}, - {8.844175f, 0.367510f, 1.064222f, 0}, - {7.511803f, 0.355539f, 1.830366f, 0}, - {7.447159f, 0.761356f, 1.376665f, 0}, - {7.492649f, 1.477221f, 1.074996f, 0}, - {7.439977f, 1.969230f, 1.636436f, 0}, - {8.178588f, 2.361878f, 2.212241f, 0}, - {9.138661f, 2.566582f, 3.772062f, 0}, - {8.628697f, 3.113657f, 5.457579f, 0}, - {7.310690f, 3.958810f, 4.115630f, 0}, - {6.605598f, 3.852268f, -0.732625f, 0}, - {7.333435f, 2.907756f, -0.568623f, 0}, - {7.597994f, 2.693475f, 1.482010f, 0}, - {7.583629f, 2.049435f, 0.691924f, 0}, - {9.470259f, 0.593762f, -0.951695f, 0}, - {10.658978f, 0.784101f, -0.517147f, 0}, - {10.287878f, 1.835154f, 0.626083f, 0}, - {9.807840f, 2.612072f, 1.288080f, 0}, - {8.984236f, 2.947260f, 0.714669f, 0}, - {8.761575f, 2.649182f, -0.256179f, 0}, - {8.923183f, 2.196679f, -0.543483f, 0}, - {8.926775f, 1.908177f, -0.259771f, 0}, - {8.783123f, 2.282870f, 0.343568f, 0}, - {8.637076f, 2.968808f, 0.847547f, 0}, - {9.196122f, 2.409762f, 1.001973f, 0}, - {10.965436f, 2.219424f, -0.040701f, 0}, - {12.228376f, 2.415748f, -2.486377f, 0}, - {11.583140f, 2.370258f, -2.585736f, 0}, - {10.394420f, 2.659956f, -0.113724f, 0}, - {9.483426f, 3.004721f, 1.859096f, 0}, - {9.071624f, 3.149570f, 2.835930f, 0}, - {9.080004f, 3.254915f, 3.105278f, 0}, - {9.205699f, 3.192666f, 3.260900f, 0}, - {9.168590f, 2.627635f, 3.888181f, 0}, - {8.310268f, 1.988383f, 3.989934f, 0}, - {6.813893f, 1.753752f, 3.471590f, 0}, - {6.712140f, 1.843534f, 3.975569f, 0}, - {7.686579f, 1.092952f, 4.849452f, 0}, - {8.225274f, -0.057461f, 5.044580f, 0}, - {9.645035f, -1.168370f, 5.014652f, 0}, - {10.184927f, -1.946485f, 5.219356f, 0}, - {9.691722f, -2.285264f, 4.790794f, 0}, - {9.776716f, -2.582145f, 4.147952f, 0}, - {9.946704f, -2.756921f, 3.651155f, 0}, - {9.209291f, -2.138021f, 3.199848f, 0}, - {8.215697f, -1.181538f, 2.749739f, 0}, - {7.557292f, -0.480037f, 2.457646f, 0}, - {7.584826f, -0.227449f, 2.263716f, 0}, - {8.142674f, 0.092177f, 1.337161f, 0}, - {8.587996f, 0.541089f, -0.260968f, 0}, - {9.088384f, 0.393846f, -1.416169f, 0}, - {9.514551f, 0.010774f, -0.566228f, 0}, - {9.374491f, 0.046687f, 0.678756f, 0}, - {9.302665f, 0.275333f, 0.553060f, 0}, - {9.515748f, 0.501585f, 0.005986f, 0}, - {9.652218f, 0.667982f, -0.077812f, 0}, - {9.983814f, 0.775721f, 0.123301f, 0}, - {10.466246f, 0.855927f, 0.921767f, 0}, - {11.034868f, 0.636857f, 1.392227f, 0}, - {11.848896f, -0.166397f, 0.960074f, 0}, - {12.391183f, -1.085770f, 0.053870f, 0}, - {12.482162f, -1.602917f, -0.912190f, 0}, - {12.077542f, -1.947682f, -1.058236f, 0}, - {11.311399f, -1.833957f, -0.653617f, 0}, - {10.664965f, -1.778891f, 0.350750f, 0}, - {9.764745f, -2.568977f, 2.135627f, 0}, - {8.580813f, -3.081336f, 2.833536f, 0}, - {7.436386f, -2.665942f, 2.202664f, 0}, - {6.769601f, -1.289277f, 2.110487f, 0}, - {7.038948f, 0.441730f, 3.216608f, 0}, - {8.155843f, 1.883038f, 4.080914f, 0}, - {9.284708f, 1.380256f, 3.860648f, 0}, - {9.452302f, -0.167594f, 2.287658f, 0}, - {9.560040f, -0.761356f, 0.659602f, 0}, - {9.497791f, -0.784101f, -0.830787f, 0}, - {9.290693f, -0.700303f, -1.665166f, 0}, - {8.920790f, -0.146046f, -1.515529f, 0}, - {8.766363f, 0.034716f, -0.599747f, 0}, - {8.348576f, -0.287304f, -0.076614f, 0}, - {8.081622f, -0.591367f, 0.045490f, 0}, - {7.095212f, -1.157596f, 1.143231f, 0}, - {6.483494f, -1.507149f, 0.781706f, 0}, - {6.980290f, -1.605311f, 0.519541f, 0}, - {8.282735f, -1.045068f, 1.046265f, 0}, - {7.284354f, -1.468842f, 0.658405f, 0}, - {8.409628f, -2.402580f, -0.105345f, 0}, - {10.058035f, -2.456449f, 2.020705f, 0}, - {11.830939f, -2.476800f, 2.808397f, 0}, - {12.722779f, -1.401804f, 0.846350f, 0}, - {11.550818f, -0.071826f, -3.417721f, 0}, - {10.788265f, -0.575805f, -7.012612f, 0}, - {10.037683f, -1.229422f, -8.307875f, 0}, - {9.273934f, -0.415394f, -6.815091f, 0}, - {9.394841f, 0.909796f, -5.343854f, 0}, - {8.586799f, 1.194706f, -2.789243f, 0}, - {8.435964f, 0.617704f, -0.373495f, 0}, - {8.913607f, -0.415394f, 0.533907f, 0}, - {8.986629f, -1.616085f, 0.727837f, 0}, - {8.663413f, -2.105699f, 1.237801f, 0}, - {8.337802f, -2.239774f, 1.921346f, 0}, - {8.827415f, -2.661153f, 2.705446f, 0}, - {9.233232f, -3.117249f, 3.457225f, 0}, - {9.272737f, -2.991553f, 3.994723f, 0}, - {8.706509f, -2.610875f, 4.343079f, 0}, - {7.984657f, -2.519896f, 4.351459f, 0}, - {8.218092f, -3.441663f, 4.805160f, 0}, - {9.825797f, -4.513067f, 4.161120f, 0}, - {10.711651f, -6.089648f, 4.596864f, 0}, - {11.142607f, -7.103591f, 3.855859f, 0}, - {10.658978f, -6.648694f, 3.931277f, 0}, - {10.046063f, -5.696999f, 4.780020f, 0}, - {9.539690f, -4.680661f, 5.057748f, 0}, - {7.566869f, -3.590103f, 4.860226f, 0}, - {6.440398f, -3.344697f, 4.193441f, 0}, - {6.586444f, -3.541022f, 3.108869f, 0}, - {7.125139f, -3.699039f, 0.994790f, 0}, - {8.431175f, -4.952403f, -2.618058f, 0}, - {9.090777f, -5.112814f, -7.767982f, 0}, - {8.908818f, -3.330332f, -9.904806f, 0}, - {8.309072f, -1.798044f, -7.811078f, 0}, - {8.213304f, -1.308430f, -7.665031f, 0}, - {8.283933f, -1.283291f, -4.946417f, 0}, - {8.704114f, -1.482010f, -1.357511f, 0}, - {8.904030f, -1.138442f, -0.214281f, 0}, - {9.314635f, -1.148019f, -0.150835f, 0}, - {9.588771f, -0.961271f, -1.286883f, 0}, - {9.983814f, -0.888248f, -3.894166f, 0}, - {10.663767f, -0.937329f, -6.470325f, 0}, - {11.098314f, -0.972045f, -6.862975f, 0}, - {10.899596f, -1.125274f, -5.509054f, 0}, - {10.278301f, -1.490390f, -3.240550f, 0}, - {9.907200f, -1.777694f, -0.620098f, 0}, - {8.779531f, -2.339134f, 1.922543f, 0}, - {7.435188f, -2.651577f, 4.188653f, 0}, - {6.859383f, -2.463632f, 5.175064f, 0}, - {6.631934f, -2.347513f, 5.786782f, 0}, - {6.870157f, -2.407368f, 6.654679f, 0}, - {7.872130f, -2.549823f, 6.404485f, 0}, - {9.375688f, -3.722981f, 3.958810f, 0}, - {11.268303f, -5.311533f, -0.108936f, 0}, - {12.009308f, -6.212949f, -5.847834f, 0}, - {10.462654f, -5.131968f, -11.382027f, 0}, - {7.885298f, -2.762907f, -11.698062f, 0}, - {7.011415f, -1.878250f, -9.295482f, 0}, - {6.627146f, -1.376665f, -6.520604f, 0}, - {7.509408f, -1.753752f, -3.491941f, 0}, - {8.297100f, -1.997960f, -0.979228f, 0}, - {8.939943f, -1.666363f, -0.052672f, 0}, - {8.857343f, -0.831985f, 0.451307f, 0}, - {8.007402f, -0.197522f, 1.444900f, 0}, - {7.693762f, 0.035913f, 3.700236f, 0}, - {7.378925f, -0.505176f, 3.415326f, 0}, - {5.979515f, -1.707065f, -0.325611f, 0}, - {7.726084f, -3.241747f, -5.707773f, 0}, - {8.884876f, -3.162738f, -12.425899f, 0}, - {9.512156f, 0.045490f, -13.029237f, 0}, - {8.766363f, 1.078587f, -6.048946f, 0}, - {8.428782f, -0.650025f, -1.023521f, 0}, - {8.790305f, -0.999579f, 1.993172f, 0}, - {9.354139f, -0.804451f, 2.904165f, 0}, - {10.168168f, -1.060631f, -0.969651f, 0}, - {11.595111f, -1.048660f, -4.067746f, 0}, - {13.030434f, -0.831985f, -6.460749f, 0}, - {11.122256f, 0.191536f, -7.928393f, 0}, - {9.040500f, 0.798466f, -6.001062f, 0}, - {8.956702f, 0.328005f, -1.649604f, 0}, - {9.064442f, 0.119710f, 0.561440f, 0}, - {9.356534f, 0.306458f, 0.186748f, 0}, - {10.399208f, -0.664391f, -0.585382f, 0}, - {11.281470f, -1.975215f, -2.223015f, 0}, - {10.011348f, -1.996763f, -4.955994f, 0}, - {9.003389f, -2.169145f, -6.757630f, 0}, - {8.583207f, -2.082954f, -5.573698f, 0}, - {8.798685f, -1.921346f, -2.810791f, 0}, - {8.974659f, -1.520317f, -1.250970f, 0}, - {8.078031f, -0.515950f, 0.366313f, 0}, - {6.692986f, 0.751779f, 2.220621f, 0}, - {6.210555f, 1.480813f, 1.197100f, 0}, - {7.131125f, 0.602141f, -2.041055f, 0}, - {8.007402f, 0.234632f, -4.835087f, 0}, - {8.462300f, 0.919373f, -5.451593f, 0}, - {7.928393f, 1.326387f, -4.395751f, 0}, - {6.871354f, 1.467645f, -2.835930f, 0}, - {6.029793f, 1.558624f, -0.976834f, 0}, - {5.135559f, 1.978806f, 0.028730f, 0}, - {7.839808f, 1.517923f, 0.440533f, 0}, - {11.483781f, 0.501585f, -0.684741f, 0}, - {9.314635f, 0.493205f, -3.245338f, 0}, - {8.585602f, 0.633266f, -4.395751f, 0}, - {9.229641f, 0.914584f, -4.349064f, 0}, - {9.064442f, 0.970848f, -3.658338f, 0}, - {9.977829f, 0.555454f, -2.989159f, 0}, - {9.810235f, 0.744596f, -3.434480f, 0}, - {9.325409f, 1.397016f, -3.568555f, 0}, - {9.496594f, 1.741781f, -3.239353f, 0}, - {10.398011f, 1.367088f, -3.130417f, 0}, - {10.730804f, 0.985213f, -2.704249f, 0}, - {10.894808f, 1.125274f, -1.823183f, 0}, - {11.997336f, 0.918176f, -2.120064f, 0}, - {12.749115f, 0.508767f, -3.248930f, 0}, - {12.022475f, 0.416591f, -3.471590f, 0}, - {10.839741f, 0.440533f, -5.136756f, 0}, - {10.629051f, 0.883460f, -8.376109f, 0}, - {11.104300f, 1.051054f, -8.720874f, 0}, - {10.903187f, 0.842758f, -5.995077f, 0}, - {11.470613f, 0.239420f, -2.959231f, 0}, - {11.871641f, -0.373495f, -0.988805f, 0}, - {9.727634f, -0.487220f, 1.842337f, 0}, - {6.479902f, -0.034716f, 3.007115f, 0}, - {4.198230f, 0.515950f, 3.420115f, 0}, - {2.959231f, 1.742978f, 3.507503f, 0}, - {3.488349f, 2.468420f, 2.369061f, 0}, - {5.433637f, 2.197876f, -2.054224f, 0}, - {6.564897f, 2.667139f, -4.945220f, 0}, - {7.331040f, 3.190272f, -2.327163f, 0}, - {10.497370f, 3.070562f, 0.073023f, 0}, - {10.967831f, 1.744175f, -2.159569f, 0}, - {10.575182f, 0.481234f, -3.937262f, 0}, - {10.111904f, 0.632069f, -2.493559f, 0}, - {9.317030f, 1.003170f, -0.973242f, 0}, - {8.687355f, 1.310825f, -0.208295f, 0}, - {8.713691f, 1.209071f, -0.918176f, 0}, - {8.810657f, 1.183932f, -2.063801f, 0}, - {8.763969f, 1.406592f, -2.553414f, 0}, - {8.019373f, 1.916557f, -2.993947f, 0}, - {7.505817f, 2.184708f, -3.209425f, 0}, - {7.550110f, 2.245760f, -2.833536f, 0}, - {7.843400f, 2.250548f, -2.468420f, 0}, - {8.210909f, 2.315192f, -2.410959f, 0}, - {8.468286f, 2.409762f, -3.126825f, 0}, - {8.376109f, 2.358287f, -3.925291f, 0}, - {8.769955f, 2.191890f, -3.524262f, 0}, - {9.360126f, 2.389412f, -3.094504f, 0}, - {10.235206f, 2.645591f, -4.356247f, 0}, - {10.369281f, 3.308784f, -5.960361f, 0}, - {9.583982f, 3.739741f, -6.137532f, 0}, - {9.226050f, 3.244141f, -4.029438f, 0}, - {9.249992f, 3.345895f, -1.376665f, 0}, - {9.409206f, 3.989934f, 0.690727f, 0}, - {9.866499f, 4.723757f, 1.246181f, 0}, - {11.179717f, 3.829523f, -0.788889f, 0}, - {12.655742f, 2.403777f, -3.202243f, 0}, - {12.897555f, 0.988805f, -4.781218f, 0}, - {11.311399f, 0.092177f, -4.595667f, 0}, - {8.464694f, 0.628478f, -2.196679f, 0}, - {6.581656f, 1.258152f, -0.107739f, 0}, - {6.366178f, 1.856702f, 0.781706f, 0}, - {6.930012f, 1.881841f, 0.209493f, 0}, - {7.776362f, 0.798466f, -0.858321f, 0}, - {8.432373f, -0.011971f, -1.729810f, 0}, - {8.836992f, -0.251391f, -2.906559f, 0}, - {8.950717f, -0.007183f, -3.992329f, 0}, - {8.702917f, 0.239420f, -3.590103f, 0}, - {8.307875f, 0.493205f, -2.304418f, 0}, - {7.890086f, 1.065419f, -1.701079f, 0}, - {7.886495f, 1.557427f, -1.941696f, 0}, - {8.344984f, 1.771708f, -2.163160f, 0}, - {8.882483f, 2.037464f, -2.286461f, 0}, - {8.996207f, 2.401383f, -2.816776f, 0}, - {9.011769f, 2.549823f, -3.086124f, 0}, - {9.118311f, 2.431310f, -3.043028f, 0}, - {9.022543f, 2.371455f, -3.132811f, 0}, - {8.949520f, 2.278081f, -3.059788f, 0}, - {9.159013f, 2.190693f, -2.688687f, 0}, - {9.372096f, 2.074574f, -2.284067f, 0}, - {9.406812f, 2.118867f, -1.695094f, 0}, - {9.403221f, 2.088940f, -1.282094f, 0}, - {9.539690f, 2.345119f, -1.448491f, 0}, - {9.548070f, 2.826353f, -2.069786f, 0}, - {9.326607f, 3.178301f, -2.748542f, 0}, - {9.295482f, 3.290828f, -2.521093f, 0}, - {10.214854f, 3.190272f, -2.946063f, 0}, - {11.439487f, 3.104080f, -4.429270f, 0}, - {12.179296f, 2.619255f, -5.501872f, 0}, - {12.650953f, 1.750160f, -4.109644f, 0}, - {11.921919f, 0.913387f, -1.047463f, 0}, - {10.370478f, 0.256179f, 0.997184f, 0}, - {9.369702f, -0.351947f, 2.355893f, 0}, - {7.855371f, -0.039504f, 2.788046f, 0}, - {6.522998f, 0.343568f, 1.185129f, 0}, - {6.356601f, 0.954089f, -0.673967f, 0}, - {6.839033f, 1.606508f, -1.197100f, 0}, - {8.453920f, 1.814804f, -0.993593f, 0}, - {9.556450f, 1.889024f, -0.434547f, 0}, - {9.387658f, 2.385820f, -0.804451f, 0}, - {9.039303f, 2.761710f, -1.951273f, 0}, - {8.828612f, 2.579751f, -2.316389f, 0}, - {8.649048f, 2.282870f, -2.097319f, 0}, - {8.495819f, 2.323571f, -1.842337f, 0}, - {8.274356f, 2.814382f, -1.483207f, 0}, - {8.022964f, 3.214214f, -1.207874f, 0}, - {7.991840f, 3.224988f, -1.155202f, 0}, - {8.200135f, 3.023875f, -1.380256f, 0}, - {8.465892f, 2.995144f, -1.857899f, 0}, - {8.471877f, 3.099292f, -2.273293f, 0}, - {8.388080f, 3.125628f, -2.305615f, 0}, - {8.433570f, 3.105278f, -2.064998f, 0}, - {8.494622f, 3.213017f, -1.946485f, 0}, - {8.669398f, 3.210622f, -2.211044f, 0}, - {8.773546f, 3.099292f, -2.907756f, 0}, - {8.705312f, 3.130417f, -3.394976f, 0}, - {8.570039f, 3.405750f, -1.821986f, 0}, - {8.820233f, 3.371034f, -1.948879f, 0}, - {9.376884f, 3.290828f, -4.145557f, 0}, - {9.933537f, 3.511094f, -5.504266f, 0}, - {10.266330f, 3.343500f, -4.606441f, 0}, - {10.199292f, 3.286040f, -2.880223f, 0}, - {10.279498f, 3.457225f, -2.645591f, 0}, - {10.939100f, 3.313573f, -3.344697f, 0}, - {11.617856f, 1.872265f, -3.330332f, 0}, - {11.283865f, 0.302866f, -2.816776f, 0}, - {8.844175f, 0.647631f, -0.970848f, 0}, - {6.621161f, 1.608902f, 0.426168f, 0}, - {6.217738f, 2.564188f, 0.738611f, 0}, - {6.973108f, 3.286040f, -0.644040f, 0}, - {8.750801f, 2.173934f, -1.210268f, 0}, - {10.366886f, 0.428562f, -1.189917f, 0}, - {10.743973f, 0.110133f, -1.969230f, 0}, - {10.110707f, 0.746990f, -2.530669f, 0}, - {8.839387f, 1.630450f, -2.548626f, 0}, - {7.795516f, 2.329557f, -2.692278f, 0}, - {7.451948f, 2.700658f, -2.602495f, 0}, - {7.606374f, 2.907756f, -2.309206f, 0}, - {8.056483f, 3.023875f, -2.039858f, 0}, - {8.440752f, 3.139993f, -1.945288f, 0}, - {8.403643f, 3.387793f, -1.736992f, 0}, - {8.280341f, 3.640381f, -1.544259f, 0}, - {8.359349f, 3.767274f, -1.551442f, 0}, - {8.535323f, 3.780442f, -1.817198f, 0}, - {8.860934f, 3.679886f, -2.035070f, 0}, - {9.190137f, 3.599680f, -2.019508f, 0}, - {9.193728f, 3.535036f, -2.249351f, 0}, - {8.997404f, 3.507503f, -2.041055f, 0}, - {8.646653f, 3.554190f, -1.903389f, 0}, - {8.368926f, 3.604468f, -1.539471f, 0}, - {8.249216f, 3.761288f, -1.181538f, 0}, - {8.482651f, 3.960007f, -1.823183f, 0}, - {8.767561f, 3.967190f, -2.565385f, 0}, - {8.783123f, 3.831917f, -3.102883f, 0}, - {8.614332f, 3.810369f, -3.654746f, 0}, - {8.664610f, 3.786427f, -4.390963f, 0}, - {8.987827f, 4.016271f, -5.419272f, 0}, - {9.724044f, 4.271253f, -6.058523f, 0}, - {10.873260f, 3.715799f, -6.293155f, 0}, - {12.078739f, 3.123234f, -5.191823f, 0}, - {12.312174f, 2.310403f, -2.348710f, 0}, - {11.079161f, 1.405395f, 1.435323f, 0}, - {9.323015f, 1.150413f, 2.363075f, 0}, - {7.666229f, 0.990002f, 1.956061f, 0}, - {6.414062f, 1.784876f, 2.576159f, 0}, - {5.781993f, 3.196257f, 2.535458f, 0}, - {6.141123f, 3.886984f, 0.312443f, 0}, - {7.559687f, 3.445254f, -1.547850f, 0}, - {9.400826f, 2.853886f, -1.867476f, 0}, - {9.509763f, 3.022678f, -3.046620f, 0}, - {8.577222f, 3.954021f, -4.252100f, 0}, - {8.172602f, 3.744529f, -3.657140f, 0}, - {8.269567f, 3.207031f, -2.509122f, 0}, - {8.135491f, 3.442860f, -1.326387f, 0}, - {7.990643f, 3.718193f, -0.969651f, 0}, - {8.020570f, 3.763683f, -1.307233f, 0}, - {8.246822f, 3.590103f, -1.707065f, 0}, - {8.331817f, 3.252521f, -1.964441f, 0}, - {8.212107f, 2.896982f, -2.375046f, 0}, - {8.174996f, 2.774878f, -2.712629f, 0}, - {8.511381f, 2.673124f, -2.576159f, 0}, - {8.957899f, 2.570174f, -2.475603f, 0}, - {9.176969f, 2.637211f, -2.371455f, 0}, - {9.011769f, 2.729388f, -2.279279f, 0}, - {8.756786f, 2.636014f, -2.651577f, 0}, - {8.678975f, 2.534261f, -3.602074f, 0}, - {8.603558f, 2.598904f, -3.883393f, 0}, - {8.331817f, 2.859872f, -3.414129f, 0}, - {8.225274f, 3.234564f, -3.913320f, 0}, - {8.254004f, 3.434480f, -4.692632f, 0}, - {7.493846f, 3.796004f, -4.635171f, 0}, - {7.006627f, 4.036621f, -3.604468f, 0}, - {6.774389f, 4.210201f, -2.053027f, 0}, - {7.364560f, 4.368218f, -1.525105f, 0}, - {9.597151f, 3.620030f, -1.552639f, 0}, - {11.402378f, 1.831563f, -2.977188f, 0}, - {12.288232f, 0.525527f, -4.697421f, 0}, - {11.234784f, 0.181959f, -4.031833f, 0}, - {9.607924f, 0.386663f, -1.760934f, 0}, - {9.303862f, 0.387860f, -0.899022f, 0}, - {9.464272f, 0.622492f, -1.006761f, 0}, - {9.558844f, 1.036689f, -1.015141f, 0}, - {9.920368f, 0.829590f, -1.874659f, 0}, - {10.107116f, 0.355539f, -3.119643f, 0}, - {9.897623f, -0.099359f, -4.199427f, 0}, - {9.185349f, -0.276530f, -4.827904f, 0}, - {8.003811f, 0.396240f, -4.807554f, 0}, - {7.156264f, 0.701501f, -5.153516f, 0}, - {7.101197f, 0.053870f, -4.508279f, 0}, - {7.503423f, -0.792480f, -3.005918f, 0}, - {8.105564f, -1.297656f, -1.985989f, 0}, - {8.426387f, -1.464053f, -1.731007f, 0}, - {8.543703f, -1.358709f, -1.970427f, 0}, - {8.645456f, -1.344343f, -2.333148f, 0}, - {8.863329f, -1.558624f, -2.579751f, 0}, - {8.951914f, -1.918951f, -3.125628f, 0}, - {8.690947f, -1.860294f, -3.743332f, 0}, - {8.432373f, -1.956061f, -4.167105f, 0}, - {8.066060f, -2.053027f, -4.120419f, 0}, - {7.721295f, -2.195482f, -3.816355f, 0}, - {8.643063f, -2.871843f, -3.706222f, 0}, - {9.257174f, -3.336318f, -3.749317f, 0}, - {8.542506f, -3.499123f, -4.060563f, 0}, - {7.796712f, -4.046198f, -3.117249f, 0}, - {9.125494f, -4.362233f, -1.403001f, 0}, - {10.022121f, -4.328714f, 0.181959f, 0}, - {9.467864f, -4.274844f, 0.749385f, 0}, - {8.961491f, -3.708616f, -0.160411f, 0}, - {9.466667f, -3.045423f, -1.674743f, 0}, - {10.119086f, -2.406171f, -2.686292f, 0}, - {10.562014f, -1.898601f, -3.098095f, 0}, - {10.864880f, -1.751357f, -2.885011f, 0}, - {11.161760f, -1.505952f, -2.561794f, 0}, - {11.179717f, -1.201888f, -3.112460f, 0}, - {10.089159f, -1.221042f, -4.156332f, 0}, - {7.001838f, -0.794874f, -3.333924f, 0}, - {5.855016f, -0.556652f, -2.070983f, 0}, - {5.731715f, -0.816422f, -1.926134f, 0}, - {5.664677f, -0.999579f, -2.529472f, 0}, - {5.078098f, -0.949300f, -3.558978f, 0}, - {4.414905f, -0.963666f, -4.428073f, 0}, - {4.523841f, -1.501163f, -5.098449f, 0}, - {4.826707f, -2.104502f, -5.495886f, 0}, - {5.408498f, -2.646788f, -4.911702f, 0}, - {7.024583f, -3.204637f, -3.964795f, 0}, - {8.048103f, -3.580526f, -2.898179f, 0}, - {8.647851f, -4.011482f, -2.421733f, 0}, - {8.653836f, -3.981555f, -2.619255f, 0}, - {8.593981f, -3.761288f, -2.304418f, 0}, - {9.291890f, -3.605665f, -1.768117f, 0}, - {10.421953f, -3.653549f, -2.403777f, 0}, - {10.747564f, -4.040213f, -3.653549f, 0}, - {11.080358f, -4.187456f, -3.568555f, 0}, - {11.591519f, -4.479548f, -3.045423f, 0}, - {12.521667f, -4.991907f, -3.197454f, 0}, - {12.606661f, -5.301956f, -3.508700f, 0}, - {12.215209f, -5.559332f, -3.132811f, 0}, - {11.514905f, -5.664677f, -2.713826f, 0}, - {10.378858f, -5.208582f, -2.182313f, 0}, - {9.202108f, -4.546586f, -1.216254f, 0}, - {8.280341f, -4.206610f, -0.418985f, 0}, - {7.450751f, -4.313151f, 0.014365f, 0}, - {7.369348f, -4.450818f, 0.191536f, 0}, - {7.760799f, -4.636368f, 0.500388f, 0}, - {8.317451f, -4.886562f, 0.723048f, 0}, - {9.074018f, -4.566936f, 1.207874f, 0}, - {9.854527f, -4.408919f, 1.930922f, 0}, - {9.587574f, -3.520671f, 2.163160f, 0}, - {7.569263f, -1.774102f, 2.106896f, 0}, - {6.695381f, -1.079784f, 3.076547f, 0}, - {6.536166f, -1.090558f, 2.916136f, 0}, - {7.067678f, -1.138442f, 1.533485f, 0}, - {8.107959f, -0.973242f, -2.732979f, 0}, - {9.166195f, -1.021126f, -7.004232f, 0}, - {9.587574f, -1.686714f, -7.388502f, 0}, - {9.416389f, -1.589749f, -5.742489f, 0}, - {8.761575f, -1.954864f, -2.201467f, 0}, - {8.656230f, -2.102108f, -0.766144f, 0}, - {8.858541f, -2.230197f, -0.316034f, 0}, - {9.175772f, -2.531867f, 0.506373f, 0}, - {9.725241f, -2.759315f, 1.114500f, 0}, - {10.110707f, -2.782060f, 0.573411f, 0}, - {9.934733f, -2.370258f, 0.377087f, 0}, - {9.617501f, -2.214635f, -0.361524f, 0}, - {9.494201f, -2.189496f, -1.580172f, 0}, - {9.704890f, -2.115276f, -2.446872f, 0}, - {9.459484f, -2.057815f, -2.561794f, 0}, - {9.435542f, -2.030282f, -2.092531f, 0}, - {9.346957f, -1.996763f, -1.692699f, 0}, - {9.319424f, -2.132035f, -1.470039f, 0}, - {9.446317f, -2.430113f, -1.489192f, 0}, - {9.703692f, -2.687490f, -1.851914f, 0}, - {9.847345f, -2.719811f, -2.027887f, 0}, - {9.732423f, -2.558203f, -2.355893f, 0}, - {9.549267f, -2.409762f, -2.292447f, 0}, - {9.601939f, -2.473209f, -1.733401f, 0}, - {9.971844f, -2.697066f, -1.748963f, 0}, - {10.626657f, -3.017889f, -1.353920f, 0}, - {11.123453f, -3.641578f, -1.219845f, 0}, - {11.133030f, -4.373006f, -1.596931f, 0}, - {10.457866f, -4.733334f, -2.841915f, 0}, - {9.214079f, -4.768049f, -3.096898f, 0}, - {7.812275f, -4.437650f, -1.672349f, 0}, - {6.750447f, -4.045001f, 0.490811f, 0}, - {6.290761f, -3.907335f, 1.800438f, 0}, - {6.235694f, -4.234143f, 1.041477f, 0}, - {7.199359f, -4.850649f, -2.310403f, 0}, - {8.538915f, -4.039015f, -3.203440f, 0}, - {9.186545f, -2.800017f, -4.298786f, 0}, - {9.197320f, -2.372652f, -4.565740f, 0}, - {9.024938f, -1.969230f, -4.732136f, 0}, - {8.607149f, -1.534682f, -4.993104f, 0}, - {7.957124f, -1.502361f, -4.132390f, 0}, - {7.705733f, -1.678334f, -2.855083f, 0}, - {7.752420f, -1.753752f, -1.508346f, 0}, - {8.034935f, -1.557427f, -0.313640f, 0}, - {7.546519f, -1.106120f, 0.447715f, 0}, - {6.752841f, -0.906205f, 1.265335f, 0}, - {6.906070f, -1.195903f, 1.750160f, 0}, - {7.101197f, -1.496375f, 1.381453f, 0}, - {7.223301f, -1.824380f, 0.837970f, 0}, - {7.374136f, -2.153583f, 0.274136f, 0}, - {7.323858f, -2.404974f, -0.490811f, 0}, - {7.491452f, -2.598904f, -1.482010f, 0}, - {7.899663f, -2.819170f, -2.953246f, 0}, - {8.497016f, -3.117249f, -4.119221f, 0}, - {9.168590f, -3.533839f, -6.064509f, 0}, - {9.417586f, -3.632001f, -6.847412f, 0}, - {9.738409f, -3.272871f, -6.969516f, 0}, - {9.919171f, -2.809594f, -6.331462f, 0}, - {9.987406f, -2.677913f, -4.316743f, 0}, - {9.593559f, -2.616861f, -3.142388f, 0}, - {9.325409f, -2.674321f, -3.335121f, 0}, - {9.167392f, -2.829944f, -3.014298f, 0}, - {9.194925f, -3.105278f, -2.008734f, 0}, - {9.613911f, -3.459619f, -2.535458f, 0}, - {10.720031f, -4.271253f, -3.035846f, 0}, - {11.372450f, -5.182246f, -2.151189f, 0}, - {10.842135f, -5.142742f, -0.895431f, 0}, - {9.220064f, -4.575316f, 0.703895f, 0}, - {7.491452f, -4.206610f, 1.714247f, 0}, - {6.665453f, -4.437650f, 2.238577f, 0}, - {7.479481f, -4.993104f, 3.179498f, 0}, - {8.750801f, -5.791570f, 2.965217f, 0}, - {9.563632f, -6.527786f, 1.649604f, 0}, - {9.215276f, -6.408076f, 0.693121f, 0}, - {8.240837f, -5.831074f, -0.050278f, 0}, - {7.832625f, -5.178655f, -0.134075f, 0}, - {6.849806f, -4.006694f, 0.402226f, 0}, - {6.220132f, -3.184286f, -0.293290f, 0}, - {6.138729f, -3.074153f, 0.524330f, 0}, - {7.079649f, -3.414129f, -1.236604f, 0}, - {7.497437f, -3.640381f, -2.803608f, 0}, - {7.586023f, -3.466802f, -3.118446f, 0}, - {7.608768f, -3.038240f, -3.612848f, 0}, - {7.706930f, -2.804805f, -3.219002f, 0}, - {7.848188f, -2.905362f, -3.991132f, 0}, - {8.244428f, -3.093307f, -4.150346f, 0}, - {8.699326f, -2.829944f, -4.168303f, 0}, - {8.613134f, -2.391806f, -3.326741f, 0}, - {8.754393f, -2.479194f, -2.382229f, 0}, - {9.027331f, -2.700658f, -2.299629f, 0}, - {9.117114f, -2.700658f, -2.309206f, 0}, - {9.198517f, -2.815579f, -1.631647f, 0}, - {9.265554f, -2.861069f, -0.093374f, 0}, - {9.057259f, -2.791637f, 0.238223f, 0}, - {9.398433f, -2.922121f, 0.565031f, 0}, - {9.453499f, -2.892194f, 0.474052f, 0}, - {9.267948f, -2.750936f, 0.118513f, 0}, - {9.593559f, -2.905362f, 0.064643f, 0}, - {9.916777f, -3.290828f, 0.547075f, 0}, - {9.968252f, -3.573344f, 0.733822f, 0}, - {10.299849f, -4.295195f, -2.195482f, 0}, - {10.365689f, -5.293576f, -3.512291f, 0}, - {10.035290f, -6.093239f, -3.232170f, 0}, - {9.386461f, -5.595245f, -0.808043f, 0}, - {7.836217f, -5.037397f, -1.355117f, 0}, - {7.586023f, -4.918884f, -0.707486f, 0}, - {8.003811f, -5.001484f, -1.582566f, 0}, - {8.651442f, -5.248086f, -3.233367f, 0}, - {8.804670f, -4.791991f, -2.944866f, 0}, - {7.832625f, -3.906137f, -2.813185f, 0}, - {6.901282f, -3.084927f, -2.161963f, 0}, - {6.792346f, -2.578553f, -1.455674f, 0}, - {7.048525f, -2.341528f, -1.499966f, 0}, - {7.358574f, -2.551020f, -1.587355f, 0}, - {7.480678f, -2.724600f, -2.063801f, 0}, - {7.368151f, -2.518698f, -1.176749f, 0}, - {7.399275f, -2.738965f, -1.344343f, 0}, - {7.823049f, -2.987962f, -1.318007f, 0}, - {7.832625f, -2.798820f, -1.460462f, 0}, - {7.547716f, -2.303221f, -1.837548f, 0}, - {7.366954f, -2.001551f, -2.175131f, 0}, - {7.653060f, -2.163160f, -2.703052f, 0}, - {7.995431f, -2.481588f, -3.134008f, 0}, - {8.619121f, -2.681504f, -3.325544f, 0}, - {8.935155f, -2.726994f, -4.122813f, 0}, - {9.391250f, -2.748542f, -4.546586f, 0}, - {9.763548f, -2.730585f, -4.378992f, 0}, - {10.044867f, -2.233789f, -5.177458f, 0}, - {10.336959f, -2.200270f, -5.360614f, 0}, - {10.339353f, -2.786849f, -4.867409f, 0}, - {10.545254f, -3.339909f, -4.352656f, 0}, - {10.761930f, -3.875013f, -3.894166f, 0}, - {10.625460f, -4.471169f, -3.217805f, 0}, - {9.902411f, -4.558557f, -2.613269f, 0}, - {8.913607f, -3.739741f, -1.416169f, 0}, - {8.100776f, -3.011904f, 1.066616f, 0}, - {7.064087f, -3.003524f, 3.325544f, 0}, - {6.754038f, -3.834311f, 5.176260f, 0}, - {7.175417f, -4.786006f, 7.241258f, 0}, - {7.382516f, -5.288788f, 6.618766f, 0}, - {8.252808f, -5.669466f, 4.605244f, 0}, - {9.193728f, -6.020216f, 2.553414f, 0}, - {9.549267f, -5.853819f, 0.247800f, 0}, - {8.914804f, -5.385753f, -0.512359f, 0}, - {8.572433f, -4.914096f, -1.824380f, 0}, - {8.161828f, -3.992329f, -3.460816f, 0}, - {7.699748f, -2.631226f, -3.369837f, 0}, - {7.472299f, -2.184708f, -1.789665f, 0}, - {7.617147f, -2.147598f, -1.602917f, 0}, - {7.779953f, -1.984792f, -1.983595f, 0}, - {8.039723f, -1.725021f, -2.574962f, 0}, - {8.286326f, -1.487995f, -2.779666f, 0}, - {8.273158f, -1.437717f, -2.838324f, 0}, - {8.219289f, -1.659181f, -2.960428f, 0}, - {8.444344f, -1.786073f, -2.853886f, 0}, - {8.597572f, -1.544259f, -2.703052f, 0}, - {8.681370f, -1.361103f, -2.530669f, 0}, - {8.962687f, -1.437717f, -2.333148f, 0}, - {9.131479f, -1.589749f, -1.939302f, 0}, - {9.050076f, -1.765723f, -1.616085f, 0}, - {9.041697f, -1.929725f, -1.650801f, 0}, - {9.260766f, -2.108093f, -1.804030f, 0}, - {9.653415f, -2.413354f, -2.396594f, 0}, - {9.742000f, -2.288855f, -1.392227f, 0}, - {9.372096f, -1.877053f, -0.934935f, 0}, - {9.860513f, -2.138021f, -1.429337f, 0}, - {10.694892f, -2.595313f, -1.260546f, 0}, - {11.317384f, -2.925713f, -0.727837f, 0}, - {11.739960f, -3.251324f, -0.887051f, 0}, - {11.595111f, -3.508700f, -2.597707f, 0}, - {10.346536f, -4.009088f, -4.683055f, 0}, - {9.039303f, -4.310757f, -4.425679f, 0}, - {8.474271f, -4.114433f, -2.164357f, 0}, - {8.452724f, -3.538628f, -0.290895f, 0}, - {8.659822f, -3.467999f, 0.682347f, 0}, - {8.937549f, -3.530248f, 0.061052f, 0}, - {8.566448f, -2.431310f, -0.852335f, 0}, - {8.067257f, -1.312022f, -1.903389f, 0}, - {8.377306f, -1.103726f, -1.419761f, 0}, - {8.070848f, -1.212662f, -2.258928f, 0}, - {8.067257f, -1.584960f, -2.608481f, 0}, - {7.800304f, -1.910572f, -3.106475f, 0}, - {7.347800f, -2.184708f, -3.384202f, 0}, - {7.348997f, -2.264913f, -2.862266f, 0}, - {7.765588f, -2.091334f, -1.757343f, 0}, - {7.970292f, -1.810015f, -1.043871f, 0}, - {8.240837f, -1.757343f, -0.768538f, 0}, - {8.485045f, -1.801636f, -0.395043f, 0}, - {8.564054f, -1.716641f, -0.083797f, 0}, - {8.844175f, -1.758540f, -0.086191f, 0}, - {9.075215f, -1.959653f, -0.597353f, 0}, - {9.182955f, -2.019508f, -1.362300f, 0}, - {9.318227f, -2.041055f, -1.719036f, 0}, - {9.363716f, -2.062603f, -2.341528f, 0}, - {9.173378f, -1.891418f, -2.298432f, 0}, - {9.066835f, -1.715444f, -2.759315f, 0}, - {9.272737f, -1.723824f, -2.409762f, 0}, - {9.367308f, -1.574187f, -1.908177f, 0}, - {9.205699f, -1.302445f, -1.863885f, 0}, - {9.190137f, -1.492784f, -1.729810f, 0}, - {9.236824f, -1.769314f, -1.782482f, 0}, - {9.534902f, -2.070983f, -2.035070f, 0}, - {10.097539f, -2.543838f, -1.827972f, 0}, - {10.522510f, -2.759315f, -2.231395f, 0}, - {10.928327f, -2.730585f, -2.249351f, 0}, - {11.123453f, -2.719811f, -1.364694f, 0}, - {10.806222f, -2.395397f, -0.016759f, 0}, - {9.789884f, -1.911769f, 0.586579f, 0}, - {8.809459f, -2.251745f, 0.070629f, 0}, - {8.212107f, -3.077744f, 0.161609f, 0}, - {8.462300f, -3.548204f, 1.023521f, 0}, - {8.960294f, -3.872619f, 1.528697f, 0}, - {9.425965f, -4.192245f, 1.470039f, 0}, - {9.999376f, -4.453212f, 1.244984f, 0}, - {9.986209f, -4.420890f, 0.696712f, 0}, - {9.368505f, -4.025847f, 0.286107f, 0}, - {8.735239f, -3.618833f, 0.021548f, 0}, - {8.062469f, -3.245338f, -0.644040f, 0}, - {7.747632f, -2.964020f, -1.055842f, 0}, - {7.532154f, -2.788046f, -0.582988f, 0}, - {7.694959f, -2.956837f, -0.339976f, 0}, - {8.044512f, -3.439268f, -0.831985f, 0}, - {8.398854f, -3.869027f, -1.472433f, 0}, - {8.674187f, -3.954021f, -1.877053f, 0}, - {8.778335f, -3.669111f, -1.696291f, 0}, - {8.744816f, -3.325544f, -2.801214f, 0}, - {9.170983f, -3.161541f, -2.974794f, 0}, - {8.848964f, -2.875434f, -3.779245f, 0}, - {8.207318f, -2.503136f, -4.129995f, 0}, - {8.026556f, -2.263716f, -4.618412f, 0}, - {8.368926f, -2.215832f, -4.732136f, 0}, - {8.961491f, -2.413354f, -3.232170f, 0}, - {9.333789f, -2.713826f, -1.446097f, 0}, - {9.246401f, -2.952049f, -0.226252f, 0}, - {8.790305f, -2.959231f, 0.460884f, 0}, - {8.155843f, -2.730585f, 0.590170f, 0}, - {7.708127f, -2.560597f, 0.263362f, 0}, - {7.612359f, -2.658759f, 0.471657f, 0}, - {8.567645f, -3.356668f, 0.718260f, 0}, - {10.579970f, -4.683055f, 1.223436f, 0}, - {12.627011f, -5.783190f, 2.347513f, 0}, - {11.851291f, -5.154713f, 2.021902f, 0}, - {8.839387f, -3.144782f, -3.478773f, 0}, - {8.154645f, -3.208228f, -8.307875f, 0}, - {9.410403f, -4.708194f, -0.691924f, 0}, - {9.804249f, -4.711786f, 1.703473f, 0}, - {9.985011f, -4.288013f, -2.111685f, 0}, - {9.917974f, -3.863042f, -0.809240f, 0}, - {9.002192f, -3.196257f, -0.214281f, 0}, - {8.477862f, -2.410959f, -0.794874f, 0}, - {8.450329f, -1.956061f, -0.992396f, 0}, - {8.361744f, -1.842337f, -1.545456f, 0}, - {8.178588f, -1.766920f, -1.849520f, 0}, - {8.061272f, -1.640027f, -2.190693f, 0}, - {7.553701f, -1.369482f, -2.219424f, 0}, - {7.180206f, -1.359906f, -2.621649f, 0}, - {7.414838f, -1.776496f, -3.306390f, 0}, - {7.927197f, -1.954864f, -3.851071f, 0}, - {8.195347f, -1.989580f, -4.341882f, 0}, - {8.341393f, -2.115276f, -4.428073f, 0}, - {8.359349f, -2.343922f, -4.118024f, 0}, - {8.401248f, -2.454055f, -3.053802f, 0}, - {8.487439f, -2.311600f, -2.007537f, 0}, - {8.573630f, -2.114079f, -1.933317f, 0}, - {8.593981f, -2.120064f, -2.171540f, 0}, - {8.409628f, -2.209847f, -2.895785f, 0}, - {8.107959f, -2.146400f, -2.240971f, 0}, - {8.183376f, -1.910572f, -1.847125f, 0}, - {8.455117f, -1.956061f, -1.793256f, 0}, - {8.859737f, -2.144006f, -2.002748f, 0}, - {9.208094f, -2.382229f, -2.218226f, 0}, - {9.277525f, -2.410959f, -2.454055f, 0}, - {9.018951f, -2.202664f, -2.607284f, 0}, - {8.807065f, -1.917754f, -3.163935f, 0}, - {8.732844f, -1.766920f, -3.756500f, 0}, - {8.488636f, -1.750160f, -3.998314f, 0}, - {8.299495f, -1.744175f, -3.921700f, 0}, - {8.184573f, -1.738189f, -3.780442f, 0}, - {8.080425f, -1.723824f, -3.687068f, 0}, - {7.970292f, -1.810015f, -3.618833f, 0}, - {7.970292f, -1.811212f, -3.657140f, 0}, - {7.902057f, -1.886630f, -3.809172f, 0}, - {8.113944f, -2.105699f, -4.045001f, 0}, - {8.355759f, -2.325965f, -3.809172f, 0}, - {8.410825f, -2.215832f, -3.554190f, 0}, - {8.657428f, -2.017113f, -3.271674f, 0}, - {8.823824f, -2.086545f, -2.360681f, 0}, - {8.422796f, -2.122458f, -1.601720f, 0}, - {8.717282f, -1.810015f, -1.653195f, 0}, - {9.615108f, -1.516726f, -1.790862f, 0}, - {9.629473f, -1.593340f, -3.891772f, 0}, - {10.530889f, -2.082954f, -6.175839f, 0}, - {10.994166f, -2.302023f, -4.498702f, 0}, - {9.297876f, -1.614888f, -3.004721f, 0}, - {7.264003f, -0.905008f, -0.735019f, 0}, - {7.615951f, -1.219845f, 0.140061f, 0}, - {8.942337f, -1.484404f, -0.383072f, 0}, - {10.296257f, -2.246957f, -0.167594f, 0}, - {11.376041f, -2.970005f, 0.173579f, 0}, - {10.957057f, -2.890997f, -0.011971f, 0}, - {10.125072f, -2.902968f, -0.169988f, 0}, - {9.543282f, -2.770089f, -0.092177f, 0}, - {9.082398f, -2.452858f, 0.432153f, 0}, - {8.699326f, -1.927331f, 0.356736f, 0}, - {8.416810f, -1.535879f, 0.282516f, 0}, - {7.886495f, -0.933738f, -0.872686f, 0}, - {8.098382f, -0.636857f, 1.728612f, 0}, - {8.451527f, -0.509965f, 1.399410f, 0}, - {9.103946f, -0.675164f, 0.752976f, 0}, - {9.591166f, -0.895431f, 0.257377f, 0}, - {9.684539f, -0.997184f, -0.475249f, 0}, - {9.461879f, -0.949300f, -0.150835f, 0}, - {9.260766f, -0.992396f, -0.387860f, 0}, - {9.248795f, -1.278503f, -0.785298f, 0}, - {9.558844f, -1.503558f, -0.909796f, 0}, - {10.126269f, -1.493981f, -0.755370f, 0}, - {10.194504f, -1.428140f, -0.456095f, 0}, - {10.286680f, -1.380256f, -0.415394f, 0}, - {10.317805f, -1.411381f, -0.383072f, 0}, - {10.150211f, -1.398213f, -0.389058f, 0}, - {9.968252f, -1.315613f, -0.265756f, 0}, - {9.878469f, -1.361103f, -0.398634f, 0}, - {9.900018f, -1.498769f, -0.544681f, 0}, - {9.877273f, -1.466448f, -1.072602f, 0}, - {9.799460f, -1.371877f, -1.558624f, 0}, - {9.544478f, -1.285685f, -1.635239f, 0}, - {9.278723f, -1.120486f, -1.229422f, 0}, - {9.204502f, -1.103726f, -0.731428f, 0}, - {9.202108f, -1.182735f, -0.477643f, 0}, - {9.107537f, -1.255758f, 0.050278f, 0}, - {8.898045f, -1.216254f, 0.428562f, 0}, - {8.766363f, -1.130062f, 0.016759f, 0}, - {8.706509f, -1.060631f, -0.681150f, 0}, - {8.720874f, -1.039083f, -1.149216f, 0}, - {9.220064f, -1.296459f, -1.238999f, 0}, - {10.467443f, -1.696291f, -0.963666f, 0}, - {11.536453f, -1.877053f, -1.309627f, 0}, - {11.785450f, -1.964441f, -2.002748f, 0}, - {11.763902f, -2.772484f, -3.430889f, 0}, - {11.314989f, -3.549402f, -5.012258f, 0}, - {9.746788f, -3.913320f, -4.704603f, 0}, - {8.693340f, -4.775232f, -3.177104f, 0}, - {8.215697f, -5.501872f, -1.019929f, 0}, - {7.824246f, -5.450397f, 0.652420f, 0}, - {7.545321f, -4.419693f, 0.913387f, 0}, - {7.720098f, -3.350683f, -0.903811f, 0}, - {7.936773f, -2.221818f, -3.144782f, 0}, - {8.151054f, -1.693897f, -4.214989f, 0}, - {7.918817f, -1.904586f, -3.973175f, 0}, - {7.843400f, -2.130838f, -3.676294f, 0}, - {7.507014f, -2.142809f, -2.937684f, 0}, - {7.426809f, -2.203861f, -2.422930f, 0}, - {7.520183f, -2.273293f, -2.515107f, 0}, - {7.607571f, -2.073377f, -2.264913f, 0}, - {7.933182f, -1.736992f, -2.202664f, 0}, - {8.366532f, -1.519120f, -2.388215f, 0}, - {8.694537f, -1.306036f, -2.293644f, 0}, - {8.757984f, -1.061828f, -1.953667f, 0}, - {8.790305f, -1.007958f, -1.453279f, 0}, - {8.921987f, -1.209071f, -0.818816f, 0}, - {8.914804f, -1.312022f, -0.050278f, 0}, - {8.711297f, -1.246181f, 0.578199f, 0}, - {8.656230f, -1.249772f, 0.275333f, 0}, - {8.939943f, -1.387439f, -0.482431f, 0}, - {9.241612f, -1.586158f, -0.899022f, 0}, - {9.497791f, -1.592143f, -1.055842f, 0}, - {9.671371f, -1.361103f, -1.174355f, 0}, - {9.715664f, -1.000776f, -1.108515f, 0}, - {9.829389f, -0.665588f, -1.197100f, 0}, - {9.860513f, -0.462081f, -1.599326f, 0}, - {9.821009f, -0.490811f, -2.014719f, 0}, - {9.856922f, -0.694318f, -2.319980f, 0}, - {10.049655f, -1.024718f, -2.524684f, 0}, - {10.514130f, -1.493981f, -1.921346f, 0}, - {10.843332f, -1.666363f, -1.532288f, 0}, - {11.147395f, -1.837548f, -1.659181f, 0}, - {11.727989f, -2.455252f, -1.991974f, 0}, - {12.029658f, -3.106475f, -0.149638f, 0}, - {10.973816f, -3.138796f, 2.298432f, 0}, - {9.229641f, -2.894588f, 2.509122f, 0}, - {8.149857f, -2.712629f, 1.924937f, 0}, - {7.643484f, -3.005918f, 1.844731f, 0}, - {7.934379f, -3.333924f, 1.647210f, 0}, - {8.604755f, -3.669111f, 1.010352f, 0}, - {9.069230f, -3.952824f, 0.132878f, 0}, - {9.255978f, -3.986343f, -0.216675f, 0}, - {9.123099f, -3.824735f, 0.580594f, 0}, - {8.698129f, -3.511094f, 0.641646f, 0}, - {8.346182f, -3.187877f, 1.156399f, 0}, - {8.060075f, -2.959231f, 1.389833f, 0}, - {7.915226f, -2.890997f, 1.458068f, 0}, - {8.005008f, -3.084927f, 1.079784f, 0}, - {7.953533f, -3.286040f, -0.043096f, 0}, - {8.371321f, -3.442860f, -2.762907f, 0}, - {8.309072f, -3.312376f, -4.205412f, 0}, - {8.149857f, -2.729388f, -3.705025f, 0}, - {7.922408f, -2.109290f, -3.027466f, 0}, - {7.881707f, -1.766920f, -3.349486f, 0}, - {7.872130f, -1.252167f, -4.329911f, 0}, - {8.201332f, -0.677559f, -3.967190f, 0}, - {8.599967f, -0.760159f, -3.022678f, 0}, - {8.785517f, -1.183932f, -2.488771f, 0}, - {9.235627f, -1.813607f, -1.701079f, 0}, - {9.714467f, -2.225409f, -0.598550f, 0}, - {9.683342f, -2.312797f, 0.444124f, 0}, - {9.585180f, -2.341528f, 0.554257f, 0}, - {9.459484f, -2.260125f, 0.377087f, 0}, - {9.476244f, -2.183511f, 0.265756f, 0}, - {9.752774f, -2.238577f, 0.000000f, 0}, - {10.631446f, -2.571371f, 0.381875f, 0}, - {11.678908f, -2.847901f, 1.048660f, 0}, - {11.956635f, -2.754527f, 1.926134f, 0}, - {11.179717f, -2.287658f, 1.643618f, 0}, - {9.974237f, -1.684320f, -0.531512f, 0}, - {9.130282f, -1.295262f, 0.968454f, 0}, - {8.774743f, -0.958877f, 1.218648f, 0}, - {8.473074f, -0.690727f, 1.455674f, 0}, - {8.464694f, -0.987608f, 0.141258f, 0}, - {9.175772f, -1.808818f, -3.797201f, 0}, - {10.365689f, -2.500742f, -9.164998f, 0}, - {10.453077f, -1.736992f, -3.761288f, 0}, - {9.622290f, -0.969651f, 0.599747f, 0}, - {8.990221f, -0.987608f, -4.253296f, 0}, - {9.148238f, -1.395819f, -3.313573f, 0}, - {8.651442f, -1.607705f, -1.174355f, 0}, - {7.994234f, -1.643618f, -0.547075f, 0}, - {7.620739f, -1.555033f, -0.290895f, 0}, - {7.387304f, -1.526303f, -0.118513f, 0}, - {7.176615f, -1.487995f, -0.105345f, 0}, - {7.222105f, -1.329978f, -0.065841f, 0}, - {7.553701f, -1.047463f, -0.521936f, 0}, - {7.945153f, -0.768538f, -0.612915f, 0}, - {8.386883f, -0.518344f, -0.260968f, 0}, - {8.783123f, -0.316034f, -0.155623f, 0}, - {9.229641f, -0.201113f, -0.294487f, 0}, - {9.470259f, -0.234632f, -0.818816f, 0}, - {9.665385f, -0.349553f, -0.980425f, 0}, - {9.798264f, -0.347159f, -0.960074f, 0}, - {9.586377f, -0.480037f, -1.021126f, 0}, - {9.587574f, -0.565031f, -0.806845f, 0}, - {9.617501f, -0.590170f, -0.330400f, 0}, - {9.609122f, -0.484826f, 0.050278f, 0}, - {9.691722f, -0.368707f, 0.562637f, 0}, - {9.884455f, -0.318429f, 1.296459f, 0}, - {9.916777f, -0.286107f, 1.254561f, 0}, - {10.086765f, -0.414197f, 0.605733f, 0}, - {10.672147f, -0.663193f, -0.056264f, 0}, - {11.547227f, -0.732625f, -1.089361f, 0}, - {12.741933f, -0.981622f, -1.647210f, 0}, - {13.311752f, -1.082178f, -2.098516f, 0}, - {12.233165f, -1.091755f, -1.170764f, 0}, - {9.745591f, -1.782482f, -1.260546f, 0}, - {6.040567f, -2.230197f, -1.437717f, 0}, - {5.289985f, -2.487574f, 0.503979f, 0}, - {6.959939f, -3.001130f, 3.216608f, 0}, - {8.799882f, -4.107250f, 4.249705f, 0}, - {9.941916f, -4.839875f, 4.045001f, 0}, - {9.454696f, -5.104434f, 3.131614f, 0}, - {8.892059f, -5.509054f, 1.795650f, 0}, - {7.688973f, -5.981909f, 0.606930f, 0}, - {7.673411f, -6.725308f, 0.831985f, 0}, - {8.412022f, -7.346603f, 0.257377f, 0}, - {8.220486f, -6.330265f, -0.105345f, 0}, - {7.586023f, -4.578907f, 0.073023f, 0}, - {7.775165f, -3.556584f, -1.447294f, 0}, - {8.498213f, -3.017889f, -4.783612f, 0}, - {8.949520f, -2.546232f, -4.119221f, 0}, - {8.564054f, -2.585736f, -1.102529f, 0}, - {7.644681f, -3.087321f, -0.313640f, 0}, - {8.555674f, -2.998736f, -0.015562f, 0}, - {9.572012f, -2.636014f, -0.071826f, 0}, - {8.997404f, -2.252942f, 1.218648f, 0}, - {7.629118f, -1.496375f, 0.980425f, 0}, - {7.766785f, -1.379059f, 1.416169f, 0}, - {8.343787f, -1.787270f, 1.284488f, 0}, - {8.748407f, -1.811212f, 0.870292f, 0}, - {9.136268f, -2.027887f, 1.131260f, 0}, - {9.615108f, -2.226606f, 1.380256f, 0}, - {10.127466f, -2.141612f, 0.444124f, 0}, - {10.301045f, -1.841140f, -0.062249f, 0}, - {10.163380f, -1.441308f, -2.595313f, 0}, - {9.898820f, -1.045068f, 1.595734f, 0}, - {9.682145f, -1.219845f, 2.372652f, 0}, - {10.177745f, -1.084573f, 1.078587f, 0}, - {11.180914f, -0.885854f, 0.757764f, 0}, - {12.489345f, -1.234210f, 2.330754f, 0}, - {13.658912f, -2.050632f, 2.142809f, 0}, - {13.063952f, -2.145203f, -0.293290f, 0}, - {9.628276f, -1.520317f, -2.880223f, 0}, - {6.360192f, -1.479616f, -3.886984f, 0}, - {5.079296f, -1.917754f, -2.090137f, 0}, - {6.202175f, -3.551796f, -0.855927f, 0}, - {7.969095f, -4.886562f, -0.975637f, 0}, - {11.101906f, -4.876986f, 0.645237f, 0}, - {11.766296f, -4.067746f, 0.531512f, 0}, - {10.569196f, -3.503912f, -0.644040f, 0}, - {10.237599f, -3.076547f, -0.447715f, 0}, - {9.629473f, -2.752133f, -0.193930f, 0}, - {8.340196f, -1.911769f, -0.742202f, 0}, - {7.272383f, -1.003170f, -1.213859f, 0}, - {6.823470f, -0.739808f, -1.057039f, 0}, - {7.050919f, -0.673967f, -0.834379f, 0}, - {7.595600f, -0.442927f, -0.532710f, 0}, - {8.060075f, -0.168791f, -0.527921f, 0}, - {8.573630f, 0.094571f, -1.207874f, 0}, - {8.899241f, 0.466869f, -1.898601f, 0}, - {9.060850f, 0.805648f, -1.408987f, 0}, - {9.222459f, 0.831985f, -0.489614f, 0}, - {9.290693f, 0.647631f, 0.099359f, 0}, - {8.882483f, 0.517147f, -0.029928f, 0}, - {8.628697f, 0.389058f, -0.817619f, 0}, - {9.248795f, 0.234632f, -1.046265f, 0}, - {9.690525f, -0.081403f, -1.126471f, 0}, - {10.071202f, -0.231040f, -0.632069f, 0}, - {10.299849f, -0.039504f, 0.476446f, 0}, - {10.965436f, 0.278924f, 0.920570f, 0}, - {11.526876f, 0.132878f, -0.335188f, 0}, - {11.572366f, 0.118513f, -0.995987f, 0}, - {12.087119f, 0.074220f, 0.064643f, 0}, - {14.025224f, -0.268150f, 0.715866f, 0}, - {13.812140f, -0.075417f, 2.175131f, 0}, - {10.393223f, 0.955286f, 4.447227f, 0}, - {5.740095f, 2.165554f, 5.378571f, 0}, - {2.682701f, 2.470814f, 4.266465f, 0}, - {2.267308f, 1.452082f, 2.970005f, 0}, - {5.784388f, -0.737414f, 2.178722f, 0}, - {8.700523f, -2.176328f, 0.712274f, 0}, - {8.658625f, -2.545035f, -1.139639f, 0}, - {8.984236f, -3.094504f, -0.059855f, 0}, - {10.274710f, -4.108448f, 2.123656f, 0}, - {11.112679f, -5.146333f, 2.748542f, 0}, - {12.083528f, -5.299562f, -0.111330f, 0}, - {11.859670f, -3.488349f, -2.300826f, 0}, - {10.259148f, -1.679531f, -0.063446f, 0}, - {8.656230f, -1.307233f, 1.798044f, 0}, - {7.996628f, -1.447294f, 1.592143f, 0}, - {8.142674f, -1.909375f, 0.881066f, 0}, - {8.282735f, -2.118867f, 0.978031f, 0}, - {8.382094f, -1.970427f, 1.248575f, 0}, - {8.866920f, -1.735795f, 0.386663f, 0}, - {9.623487f, -1.595734f, -0.269348f, 0}, - {9.806643f, -1.525105f, -0.345962f, 0}, - {9.609122f, -1.367088f, 0.299275f, 0}, - {9.714467f, -1.388636f, 1.693897f, 0}, - {9.576800f, -1.092952f, 2.396594f, 0}, - {9.296679f, -1.480813f, 2.565385f, 0}, - {9.323015f, -0.742202f, 2.341528f, 0}, - {9.384068f, -1.109712f, 1.960850f, 0}, - {9.868893f, -1.590946f, 2.421733f, 0}, - {10.109509f, -1.939302f, 2.955640f, 0}, - {9.973041f, -2.006340f, 3.324347f, 0}, - {9.859316f, -1.581369f, 3.942050f, 0}, - {9.793475f, -0.999579f, 3.818749f, 0}, - {8.820233f, -0.578199f, 2.885011f, 0}, - {7.404064f, -0.547075f, 1.671152f, 0}, - {6.730096f, -0.906205f, 0.976834f, 0}, - {8.153448f, -2.236183f, 0.503979f, 0}, - {9.867696f, -4.234143f, -0.254982f, 0}, - {7.984657f, -2.888602f, -1.261743f, 0}, - {9.093172f, -3.695448f, -2.171540f, 0}, - {9.166195f, -3.958810f, -1.365891f, 0}, - {9.483426f, -4.307166f, -1.432929f, 0}, - {9.564829f, -4.777626f, -2.000354f, 0}, - {9.548070f, -5.154713f, -2.106896f, 0}, - {9.175772f, -5.427651f, -1.608902f, 0}, - {8.127112f, -6.010639f, -1.829169f, 0}, - {8.129506f, -6.432018f, -1.207874f, 0}, - {7.790727f, -5.821497f, 0.189142f, 0}, - {7.073664f, -4.104856f, 2.110487f, 0}, - {7.091620f, -3.636790f, 1.745372f, 0}, - {7.758405f, -3.837903f, 0.458489f, 0}, - {8.832204f, -3.739741f, 0.357933f, 0}, - {9.786293f, -3.177104f, 0.160411f, 0}, - {9.618699f, -2.337936f, -0.683544f, 0}, - {9.124296f, -1.669955f, -0.986410f, 0}, - {8.815445f, -1.297656f, 0.074220f, 0}, - {8.663413f, -1.192312f, 0.752976f, 0}, - {8.526943f, -1.224633f, 0.095768f, 0}, - {8.671793f, -1.508346f, -0.044293f, 0}, - {9.041697f, -1.966835f, -1.302445f, 0}, - {9.320621f, -2.434901f, -0.640449f, 0}, - {9.319424f, -2.719811f, -0.933738f, 0}, - {9.598348f, -2.252942f, 0.096965f, 0}, - {9.272737f, -2.086545f, -0.335188f, 0}, - {9.397235f, -1.977609f, -0.829590f, 0}, - {9.585180f, -1.861491f, -0.963666f, 0}, - {9.563632f, -1.543062f, -1.194706f, 0}, - {9.265554f, -1.262941f, -1.276109f, 0}, - {8.941140f, -0.998381f, -1.148019f, 0}, - {8.711297f, -0.948103f, -1.108515f, 0}, - {8.803473f, -1.259349f, -1.027112f, 0}, - {9.475047f, -2.545035f, -0.591367f, 0}, - {10.941494f, -4.028242f, -0.374692f, 0}, - {11.295835f, -3.961204f, 0.489614f, 0}, - {9.697707f, -2.606087f, 1.587355f, 0}, - {8.414416f, -2.354696f, 1.309627f, 0}, - {8.408431f, -3.039437f, 0.598550f, 0}, - {8.759181f, -3.227382f, 0.460884f, 0}, - {9.191334f, -3.215411f, 0.717063f, 0}, - {9.106340f, -3.286040f, -1.228225f, 0}, - {9.215276f, -3.016692f, -0.532710f, 0}, - {9.226050f, -2.573765f, 1.215057f, 0}, - {9.278723f, -2.743753f, 0.444124f, 0}, - {9.779110f, -3.204637f, 1.349132f, 0}, - {9.914383f, -3.223790f, 1.940499f, 0}, - {9.907200f, -2.806002f, 1.668757f, 0}, - {10.375266f, -2.416945f, 2.098516f, 0}, - {11.027685f, -2.161963f, 2.414551f, 0}, - {11.603491f, -1.948879f, 2.486377f, 0}, - {11.531665f, -1.472433f, 2.813185f, 0}, - {10.983393f, -0.723048f, 2.525881f, 0}, - {9.938325f, 0.086191f, 2.130838f, 0}, - {8.816642f, 0.365116f, 2.731782f, 0}, - {10.491385f, 0.019154f, 3.318361f, 0}, - {10.913961f, -0.289698f, 4.115630f, 0}, - {9.964661f, 0.154426f, 4.765655f, 0}, - {7.896072f, 1.101332f, 4.291604f, 0}, - {7.783545f, 1.666363f, 4.158726f, 0}, - {8.256399f, 1.159990f, 4.963177f, 0}, - {8.441950f, 0.727837f, 5.633553f, 0}, - {7.973883f, 0.981622f, 5.418075f, 0}, - {7.131125f, 1.492784f, 4.759670f, 0}, - {7.067678f, 1.640027f, 4.987119f, 0}, - {7.246047f, 1.323993f, 5.380965f, 0}, - {7.788333f, 1.154004f, 5.783190f, 0}, - {8.256399f, 1.544259f, 6.980290f, 0}, - {8.076834f, 2.169145f, 7.654258f, 0}, - {7.649469f, 2.182313f, 7.368151f, 0}, - {7.462722f, 2.094925f, 6.817485f, 0}, - {6.956348f, 1.817198f, 6.009442f, 0}, - {6.156685f, 1.295262f, 5.595245f, 0}, - {5.171472f, 1.101332f, 5.043383f, 0}, - {4.614820f, 1.007958f, 4.921278f, 0}, - {4.693829f, 0.915781f, 5.402513f, 0}, - {4.863817f, 1.090558f, 5.463564f, 0}, - {4.620806f, 1.468842f, 5.919660f, 0}, - {4.741713f, 1.361103f, 6.609190f, 0}, - {4.047395f, 1.677137f, 6.482296f, 0}, - {4.094082f, 1.859096f, 6.527786f, 0}, - {4.349064f, 1.829169f, 6.309914f, 0}, - {4.477154f, 1.816001f, 6.591233f, 0}, - {4.513067f, 1.195903f, 7.651864f, 0}, - {5.130771f, 0.706289f, 8.787911f, 0}, - {5.143939f, 0.804451f, 8.456315f, 0}, - {4.619609f, 0.244208f, 7.931985f, 0}, - {3.963598f, -0.852335f, 8.146266f, 0}, - {4.163514f, -1.314416f, 8.972264f, 0}, - {4.601653f, -1.395819f, 9.185349f, 0}, - {4.854240f, -1.686714f, 8.943534f, 0}, - {4.542994f, -2.023099f, 8.414416f, 0}, - {3.835509f, -2.602495f, 8.085214f, 0}, - {2.978385f, -2.853886f, 8.039723f, 0}, - {2.686292f, -2.522290f, 7.716507f, 0}, - {2.425325f, -2.989159f, 10.263936f, 0}, - {1.680728f, -3.276463f, 12.568354f, 0}, - {1.449688f, -2.462435f, 9.834177f, 0}, - {1.904586f, -2.296038f, 8.819036f, 0}, - {2.072180f, -2.254139f, 9.337380f, 0}, - {2.197876f, -2.144006f, 9.494201f, 0}, - {2.105699f, -1.899798f, 9.169786f, 0}, - {1.717839f, -1.751357f, 9.096764f, 0}, - {1.574187f, -1.813607f, 9.458287f, 0}, - {1.502361f, -1.717839f, 9.576800f, 0}, - {1.379059f, -1.528697f, 9.473849f, 0}, - {1.168370f, -1.182735f, 9.206897f, 0}, - {1.060631f, -1.138442f, 9.701299f, 0}, - {0.893037f, -1.142033f, 10.007756f, 0}, - {0.729034f, -1.097741f, 10.362098f, 0}, - {0.847547f, -1.270123f, 11.415545f, 0}, - {0.700303f, -1.437717f, 11.802209f, 0}, - {0.657208f, -0.940921f, 10.297455f, 0}, - {0.820014f, -0.262165f, 8.865723f, 0}, - {1.120486f, -0.100556f, 9.303862f, 0}, - {1.000776f, -0.172382f, 10.194504f, 0}, - {0.691924f, 0.026336f, 8.984236f, 0}, - {0.712274f, 0.058658f, 8.265976f, 0}, - {0.530315f, -0.462081f, 10.773900f, 0}, - {0.463278f, -0.685938f, 10.289075f, 0}, - {0.442927f, -0.518344f, 7.893678f, 0}, - {0.445321f, -0.438139f, 7.972686f, 0}, - {0.378284f, -0.450110f, 8.655033f, 0}, - {0.043096f, 0.015562f, 8.980644f, 0}, - {0.220266f, 0.984016f, 9.639050f, 0}, - {0.154426f, 1.146822f, 9.488214f, 0}, - {-0.119710f, 1.325190f, 9.168590f, 0}, - {-0.130484f, 1.334767f, 9.746788f, 0}, - {-0.025139f, 1.310825f, 10.338156f, 0}, - {0.028730f, 1.616085f, 9.712072f, 0}, - {0.044293f, 1.892615f, 8.583207f, 0}, - {0.069432f, 1.480813f, 8.564054f, 0}, - {0.033519f, 1.243787f, 8.768758f, 0}, - {0.373495f, 1.514332f, 8.633486f, 0}, - {0.353144f, 1.561018f, 8.446738f, 0}, - {0.129287f, 1.313219f, 8.616726f, 0}, - {-0.028730f, 0.976834f, 9.123099f, 0}, - {-0.076614f, 0.966060f, 9.351746f, 0}, - {-0.161609f, 1.165975f, 8.965082f, 0}, - {-0.343568f, 1.641224f, 8.194150f, 0}, - {-0.442927f, 1.661575f, 8.437161f, 0}, - {-0.363918f, 1.365891f, 9.854527f, 0}, - {-0.282516f, 1.326387f, 10.666162f, 0}, - {-0.314837f, 1.443703f, 10.433924f, 0}, - {-0.644040f, 1.332372f, 9.327804f, 0}, - {-0.999579f, 1.479616f, 8.036133f, 0}, - {-0.799663f, 1.452082f, 8.346182f, 0}, - {-0.858321f, 1.567004f, 9.868893f, 0}, - {-0.938526f, 1.495178f, 11.599899f, 0}, - {-1.193509f, 1.498769f, 11.905160f, 0}, - {-1.556230f, 1.338358f, 10.947480f, 0}, - {-1.557427f, 1.256955f, 11.003743f, 0}, - {-1.413775f, 1.060631f, 11.848896f, 0}, - {-1.280897f, 0.922964f, 12.215209f, 0}, - {-1.132457f, 0.927753f, 11.399983f, 0}, - {-1.037886f, 0.881066f, 10.413573f, 0}, - {-0.605733f, 0.897825f, 10.074794f, 0}, - {-0.149638f, 0.872686f, 10.181335f, 0}, - {0.278924f, 0.933738f, 10.765521f, 0}, - {0.741005f, 1.137245f, 10.898398f, 0}, - {1.114500f, 1.398213f, 10.672147f, 0}, - {1.337161f, 1.841140f, 11.609476f, 0}, - {1.916557f, 1.922543f, 13.679262f, 0}, - {2.594116f, 1.768117f, 13.814534f, 0}, - {3.088518f, 2.280476f, 12.144580f, 0}, - {3.426100f, 2.173934f, 11.726792f, 0}, - {3.564964f, 1.717839f, 11.662148f, 0}, - {3.779245f, 1.653195f, 11.219221f, 0}, - {3.823538f, 1.709459f, 10.377660f, 0}, + { 3.233367f, 1.968032f, 8.875299f, 0 }, + { 3.190272f, 2.127247f, 9.054865f, 0 }, + { 3.361457f, 2.057815f, 9.054865f, 0 }, + { 3.377019f, 1.917754f, 9.093172f, 0 }, + { 3.460816f, 1.817198f, 9.058456f, 0 }, + { 3.500320f, 1.726218f, 8.900438f, 0 }, + { 3.715799f, 1.363497f, 8.836992f, 0 }, + { 3.883393f, 0.884657f, 8.832204f, 0 }, + { 3.948036f, 0.577002f, 9.016558f, 0 }, + { 3.600877f, 0.717063f, 9.200911f, 0 }, + { 3.318361f, 0.854729f, 9.166195f, 0 }, + { 3.272871f, 0.731428f, 9.149436f, 0 }, + { 3.452436f, 0.250194f, 9.297876f, 0 }, + { 3.817552f, -0.353144f, 9.424768f, 0 }, + { 3.828326f, -0.495599f, 9.284708f, 0 }, + { 3.312376f, -0.040701f, 9.204502f, 0 }, + { 3.049014f, 0.515950f, 9.223656f, 0 }, + { 3.099292f, 0.980425f, 8.882483f, 0 }, + { 3.153162f, 1.443703f, 8.154645f, 0 }, + { 3.501518f, 1.487995f, 8.054089f, 0 }, + { 4.235340f, 1.292868f, 8.480257f, 0 }, + { 4.284421f, 1.511937f, 8.848964f, 0 }, + { 3.988737f, 1.928528f, 9.149436f, 0 }, + { 3.825932f, 2.076969f, 9.576800f, 0 }, + { 3.903743f, 1.991974f, 10.133451f, 0 }, + { 3.841494f, 2.000354f, 10.165773f, 0 }, + { 3.706222f, 1.930922f, 9.649823f, 0 }, + { 3.949233f, 1.614888f, 9.054865f, 0 }, + { 4.237734f, 1.272517f, 8.625106f, 0 }, + { 4.188653f, 1.134851f, 8.268370f, 0 }, + { 4.242523f, 0.991199f, 8.091199f, 0 }, + { 4.157528f, 0.970848f, 8.135491f, 0 }, + { 3.951627f, 0.967257f, 8.353364f, 0 }, + { 4.073731f, 0.994790f, 8.854949f, 0 }, + { 3.840297f, 1.124077f, 9.249992f, 0 }, + { 3.736149f, 1.142033f, 9.491806f, 0 }, + { 3.809172f, 1.126471f, 9.651020f, 0 }, + { 3.987540f, 1.173158f, 9.633064f, 0 }, + { 4.237734f, 1.005564f, 9.467864f, 0 }, + { 4.308363f, 0.939724f, 9.190137f, 0 }, + { 4.367021f, 0.986410f, 9.021346f, 0 }, + { 4.406525f, 1.033097f, 9.074018f, 0 }, + { 4.185062f, 1.276109f, 9.235627f, 0 }, + { 3.971978f, 1.363497f, 9.525325f, 0 }, + { 4.031833f, 1.318007f, 10.833755f, 0 }, + { 4.214989f, 1.144428f, 10.241191f, 0 }, + { 4.808751f, 0.590170f, 9.690525f, 0 }, + { 4.697421f, 0.372298f, 10.245979f, 0 }, + { 4.490322f, 0.207098f, 9.682145f, 0 }, + { 4.353853f, 0.494402f, 8.651442f, 0 }, + { 3.981555f, 1.094149f, 8.230062f, 0 }, + { 3.933671f, 1.310825f, 8.426387f, 0 }, + { 4.107250f, 1.189917f, 9.068033f, 0 }, + { 4.529827f, 0.888248f, 9.501383f, 0 }, + { 4.699815f, 0.720654f, 9.765942f, 0 }, + { 4.661508f, 0.647631f, 9.916777f, 0 }, + { 4.627989f, 0.587776f, 9.925157f, 0 }, + { 4.413708f, 0.587776f, 9.791081f, 0 }, + { 4.369415f, 0.466869f, 9.840162f, 0 }, + { 4.412511f, 0.335188f, 9.932339f, 0 }, + { 4.234143f, 0.452504f, 9.502580f, 0 }, + { 3.817552f, 1.055842f, 8.638274f, 0 }, + { 3.130417f, 1.842337f, 7.748828f, 0 }, + { 2.511516f, 2.430113f, 7.059299f, 0 }, + { 2.267308f, 2.840718f, 6.742067f, 0 }, + { 2.082954f, 3.129220f, 6.706154f, 0 }, + { 1.653195f, 3.483561f, 6.813893f, 0 }, + { 1.053448f, 3.797201f, 7.132322f, 0 }, + { 0.333991f, 4.125207f, 7.364560f, 0 }, + { -0.039504f, 4.228158f, 8.018176f, 0 }, + { 0.403423f, 3.726573f, 8.789108f, 0 }, + { 1.179144f, 3.120840f, 9.289496f, 0 }, + { 1.683123f, 2.905362f, 9.911988f, 0 }, + { 1.442506f, 3.038240f, 10.551240f, 0 }, + { 1.403001f, 2.936486f, 12.229574f, 0 }, + { 1.601720f, 2.541443f, 14.815310f, 0 }, + { 2.233789f, 2.037464f, 14.715951f, 0 }, + { 2.664745f, 1.736992f, 12.216406f, 0 }, + { 3.331529f, 1.385045f, 10.475822f, 0 }, + { 3.337515f, 1.235407f, 9.133873f, 0 }, + { 3.173512f, 1.292868f, 8.406036f, 0 }, + { 3.201046f, 1.462856f, 8.306677f, 0 }, + { 3.157950f, 1.595734f, 9.011769f, 0 }, + { 2.759315f, 1.777694f, 10.049655f, 0 }, + { 2.315192f, 2.105699f, 10.682920f, 0 }, + { 2.063801f, 2.375046f, 10.832559f, 0 }, + { 2.310403f, 2.485180f, 10.688907f, 0 }, + { 2.553414f, 2.606087f, 10.153803f, 0 }, + { 2.475603f, 2.731782f, 9.356534f, 0 }, + { 2.710234f, 2.529472f, 9.297876f, 0 }, + { 2.777272f, 2.193087f, 9.394841f, 0 }, + { 2.938881f, 1.920148f, 9.531310f, 0 }, + { 3.108869f, 1.635239f, 10.534480f, 0 }, + { 3.187877f, 1.425746f, 10.899596f, 0 }, + { 3.448845f, 1.331175f, 10.508144f, 0 }, + { 3.606862f, 1.470039f, 9.440331f, 0 }, + { 3.700236f, 1.162384f, 8.781926f, 0 }, + { 3.713404f, 0.864306f, 8.845372f, 0 }, + { 3.575738f, 0.404620f, 9.610319f, 0 }, + { 3.495532f, -0.130484f, 9.526522f, 0 }, + { 3.403355f, -0.411802f, 8.833401f, 0 }, + { 3.203440f, -0.380678f, 8.850161f, 0 }, + { 2.822762f, -0.191536f, 9.560040f, 0 }, + { 2.488771f, -0.459686f, 9.883258f, 0 }, + { 3.065773f, -0.764947f, 10.110707f, 0 }, + { 1.993172f, 1.004367f, 9.798264f, 0 }, + { 2.426522f, 1.732204f, 10.036487f, 0 }, + { 3.213017f, 1.238999f, 10.182533f, 0 }, + { 2.779666f, 2.394200f, 9.916777f, 0 }, + { 3.187877f, 2.622846f, 9.593559f, 0 }, + { 4.195836f, 1.867476f, 9.876076f, 0 }, + { 3.720587f, 2.114079f, 9.998179f, 0 }, + { 2.948457f, 2.766498f, 9.500186f, 0 }, + { 3.869027f, 2.822762f, 9.572012f, 0 }, + { 4.205412f, 2.656365f, 9.753971f, 0 }, + { 4.151543f, 2.828747f, 9.751576f, 0 }, + { 4.046198f, 2.905362f, 9.131479f, 0 }, + { 3.915714f, 3.032254f, 8.237246f, 0 }, + { 3.864239f, 3.126825f, 8.008599f, 0 }, + { 3.466802f, 2.999933f, 8.634683f, 0 }, + { 2.876631f, 2.902968f, 9.473849f, 0 }, + { 2.329557f, 2.899376f, 10.187322f, 0 }, + { 2.197876f, 3.608059f, 10.637431f, 0 }, + { 2.357090f, 4.205412f, 10.235206f, 0 }, + { 2.716220f, 4.076126f, 9.261963f, 0 }, + { 3.520671f, 3.847480f, 8.461103f, 0 }, + { 4.180274f, 3.879801f, 7.758405f, 0 }, + { 4.691435f, 4.034227f, 7.019794f, 0 }, + { 4.918884f, 3.915714f, 6.659468f, 0 }, + { 4.722559f, 4.205412f, 6.113590f, 0 }, + { 5.349840f, 4.169499f, 5.413286f, 0 }, + { 6.423639f, 3.742135f, 5.009864f, 0 }, + { 6.799528f, 3.581723f, 4.843467f, 0 }, + { 6.915647f, 3.337515f, 4.921278f, 0 }, + { 7.358574f, 3.173512f, 5.214568f, 0 }, + { 7.584826f, 2.861069f, 5.182246f, 0 }, + { 7.077255f, 2.771286f, 5.073310f, 0 }, + { 7.192177f, 2.306812f, 5.501872f, 0 }, + { 7.241258f, 2.145203f, 5.888535f, 0 }, + { 7.599191f, 1.898601f, 6.099225f, 0 }, + { 7.576446f, 2.138021f, 6.144714f, 0 }, + { 7.465116f, 1.962047f, 6.021413f, 0 }, + { 7.677002f, 1.740583f, 5.643129f, 0 }, + { 7.966701f, 1.648407f, 4.964374f, 0 }, + { 8.038527f, 1.636436f, 4.419693f, 0 }, + { 8.176193f, 1.582566f, 4.183865f, 0 }, + { 8.489834f, 1.460462f, 4.319137f, 0 }, + { 8.804670f, 1.314416f, 4.444832f, 0 }, + { 8.803473f, 1.308430f, 4.492716f, 0 }, + { 8.580813f, 1.392227f, 4.501096f, 0 }, + { 8.056483f, 1.595734f, 4.428073f, 0 }, + { 8.418008f, 1.316810f, 4.600455f, 0 }, + { 8.826219f, 1.170764f, 4.411314f, 0 }, + { 8.652639f, 1.201888f, 3.910926f, 0 }, + { 8.285130f, 0.927753f, 3.752909f, 0 }, + { 8.475469f, 1.027112f, 3.569752f, 0 }, + { 9.009375f, 0.708683f, 3.605665f, 0 }, + { 8.797488f, 0.600944f, 3.107672f, 0 }, + { 8.864526f, 0.620098f, 2.863463f, 0 }, + { 8.833401f, 0.214281f, 2.640803f, 0 }, + { 9.212882f, 0.150835f, 2.487574f, 0 }, + { 9.308650f, 0.226252f, 2.375046f, 0 }, + { 8.869314f, 0.094571f, 2.142809f, 0 }, + { 9.208094f, 0.002394f, 2.132035f, 0 }, + { 9.100354f, 0.015562f, 2.367864f, 0 }, + { 8.973462f, -0.011971f, 2.602495f, 0 }, + { 8.872906f, 0.000000f, 2.564188f, 0 }, + { 8.883679f, 0.092177f, 2.452858f, 0 }, + { 8.857343f, 0.241814f, 2.480391f, 0 }, + { 8.919592f, 0.371101f, 2.612072f, 0 }, + { 9.002192f, 0.483628f, 2.536655f, 0 }, + { 9.056062f, 0.521936f, 2.335542f, 0 }, + { 9.023740f, 0.572214f, 2.012325f, 0 }, + { 9.085989f, 0.592565f, 1.854308f, 0 }, + { 9.127888f, 0.505176f, 1.783679f, 0 }, + { 8.968674f, 0.653617f, 1.787270f, 0 }, + { 8.872906f, 0.650025f, 1.867476f, 0 }, + { 8.798685f, 0.628478f, 2.148795f, 0 }, + { 8.841781f, 0.530315f, 2.687490f, 0 }, + { 8.541308f, 0.642843f, 2.780863f, 0 }, + { 8.499411f, 0.402226f, 2.566582f, 0 }, + { 8.734042f, -0.217872f, 2.597707f, 0 }, + { 8.689749f, -0.295684f, 3.051408f, 0 }, + { 8.298298f, -0.123301f, 3.968387f, 0 }, + { 7.545321f, -0.111330f, 4.738122f, 0 }, + { 6.827062f, -0.112527f, 5.501872f, 0 }, + { 6.604401f, 0.435744f, 6.827062f, 0 }, + { 6.572079f, 0.610521f, 7.642287f, 0 }, + { 6.546940f, 0.383072f, 7.778756f, 0 }, + { 6.274001f, 0.530315f, 7.600388f, 0 }, + { 5.847834f, 1.544259f, 7.811078f, 0 }, + { 5.374979f, 1.781285f, 7.654258f, 0 }, + { 5.163093f, 1.493981f, 7.372939f, 0 }, + { 5.104434f, 1.314416f, 7.807487f, 0 }, + { 5.424060f, 0.847547f, 8.513776f, 0 }, + { 5.471944f, 0.817619f, 8.461103f, 0 }, + { 4.618412f, 1.319204f, 8.107959f, 0 }, + { 4.265267f, 1.634042f, 7.587220f, 0 }, + { 5.191823f, 1.347935f, 7.196965f, 0 }, + { 4.748896f, 1.868673f, 7.097606f, 0 }, + { 4.595667f, 1.187523f, 7.428006f, 0 }, + { 3.948036f, 1.272517f, 8.262384f, 0 }, + { 2.280476f, 1.892615f, 8.998601f, 0 }, + { 2.828747f, 1.725021f, 8.937549f, 0 }, + { 3.256112f, 1.863885f, 9.101552f, 0 }, + { 3.264492f, 1.679531f, 8.540112f, 0 }, + { 3.616439f, 1.237801f, 8.178588f, 0 }, + { 3.713404f, 1.492784f, 9.411600f, 0 }, + { 3.654746f, 1.428140f, 10.740381f, 0 }, + { 3.139993f, 1.246181f, 10.362098f, 0 }, + { 2.381032f, 1.161187f, 9.357731f, 0 }, + { 2.602495f, 1.027112f, 11.311399f, 0 }, + { 2.964020f, 1.120486f, 12.570747f, 0 }, + { 2.501939f, 1.344343f, 10.244782f, 0 }, + { 2.152386f, 1.455674f, 9.786293f, 0 }, + { 1.878250f, 1.450885f, 10.216052f, 0 }, + { 1.844731f, 1.434126f, 12.245136f, 0 }, + { 2.011128f, 1.198297f, 13.654123f, 0 }, + { 1.562216f, 1.192312f, 10.202884f, 0 }, + { 1.046265f, 1.596931f, 8.796291f, 0 }, + { 1.344343f, 1.769314f, 9.710876f, 0 }, + { 1.857899f, 1.845928f, 10.510538f, 0 }, + { 2.217029f, 1.814804f, 11.314989f, 0 }, + { 2.341528f, 1.612494f, 11.218024f, 0 }, + { 2.144006f, 1.527500f, 10.122678f, 0 }, + { 2.220621f, 1.271320f, 10.222037f, 0 }, + { 2.487574f, 0.978031f, 10.830164f, 0 }, + { 2.782060f, 0.950497f, 11.261120f, 0 }, + { 3.031057f, 0.894234f, 10.802630f, 0 }, + { 2.880223f, 0.992396f, 9.764745f, 0 }, + { 2.115276f, 1.447294f, 8.930367f, 0 }, + { 1.849520f, 1.715444f, 8.956702f, 0 }, + { 2.313994f, 1.569398f, 9.429557f, 0 }, + { 2.365470f, 1.504755f, 9.142253f, 0 }, + { 2.184708f, 1.528697f, 8.570039f, 0 }, + { 2.346316f, 1.491587f, 8.657428f, 0 }, + { 2.662350f, 1.338358f, 8.938745f, 0 }, + { 2.619255f, 1.200691f, 8.894453f, 0 }, + { 2.372652f, 1.073799f, 8.850161f, 0 }, + { 2.363075f, 1.012747f, 9.173378f, 0 }, + { 2.529472f, 1.101332f, 9.485821f, 0 }, + { 2.730585f, 1.132457f, 9.469061f, 0 }, + { 2.913742f, 1.120486f, 9.311044f, 0 }, + { 3.093307f, 1.151610f, 9.610319f, 0 }, + { 3.087321f, 1.296459f, 10.226826f, 0 }, + { 2.811988f, 1.377862f, 10.601518f, 0 }, + { 2.683898f, 1.231816f, 10.516523f, 0 }, + { 2.584539f, 1.250970f, 10.043670f, 0 }, + { 2.732979f, 1.283291f, 9.721649f, 0 }, + { 2.949655f, 1.004367f, 9.597151f, 0 }, + { 2.908953f, 0.938526f, 9.525325f, 0 }, + { 2.630029f, 1.124077f, 9.534902f, 0 }, + { 2.710234f, 0.859518f, 9.769533f, 0 }, + { 2.574962f, 0.883460f, 9.832980f, 0 }, + { 2.279279f, 1.092952f, 9.628276f, 0 }, + { 2.272096f, 1.016338f, 9.598348f, 0 }, + { 2.448070f, 0.889445f, 9.724044f, 0 }, + { 2.395397f, 0.984016f, 9.685737f, 0 }, + { 2.266110f, 1.094149f, 9.788687f, 0 }, + { 2.366667f, 1.074996f, 9.836571f, 0 }, + { 2.486377f, 1.023521f, 9.856922f, 0 }, + { 2.391806f, 1.103726f, 9.935930f, 0 }, + { 2.179919f, 1.174355f, 9.900018f, 0 }, + { 2.024296f, 1.203086f, 9.925157f, 0 }, + { 2.039858f, 1.156399f, 9.900018f, 0 }, + { 2.087743f, 1.066616f, 9.976632f, 0 }, + { 2.084151f, 0.975637f, 9.853331f, 0 }, + { 2.179919f, 0.985213f, 9.618699f, 0 }, + { 2.300826f, 1.031900f, 9.533705f, 0 }, + { 2.246957f, 1.083376f, 9.599545f, 0 }, + { 2.124853f, 0.970848f, 9.703692f, 0 }, + { 2.005142f, 1.036689f, 9.664188f, 0 }, + { 2.142809f, 1.047463f, 9.641443f, 0 }, + { 2.340331f, 0.885854f, 9.666583f, 0 }, + { 2.238577f, 0.888248f, 9.624684f, 0 }, + { 2.110487f, 0.960074f, 9.634261f, 0 }, + { 2.123656f, 1.030703f, 9.668977f, 0 }, + { 2.196679f, 1.061828f, 9.731226f, 0 }, + { 2.325965f, 0.931344f, 9.607924f, 0 }, + { 2.492362f, 0.841561f, 9.391250f, 0 }, + { 2.663548f, 0.991199f, 9.607924f, 0 }, + { 2.663548f, 0.933738f, 9.994588f, 0 }, + { 2.318783f, 0.817619f, 9.791081f, 0 }, + { 1.841140f, 0.946906f, 9.582786f, 0 }, + { 1.580172f, 1.162384f, 9.424768f, 0 }, + { 1.405395f, 1.210268f, 9.209291f, 0 }, + { 1.625662f, 1.034294f, 9.338577f, 0 }, + { 1.824380f, 1.120486f, 9.599545f, 0 }, + { 1.843534f, 1.120486f, 10.004165f, 0 }, + { 2.057815f, 0.648828f, 10.226826f, 0 }, + { 2.493559f, 0.673967f, 9.695313f, 0 }, + { 2.706643f, 0.766144f, 9.198517f, 0 }, + { 2.315192f, 0.678756f, 8.605952f, 0 }, + { 1.771708f, 0.752976f, 8.489834f, 0 }, + { 1.243787f, 0.969651f, 9.085989f, 0 }, + { 1.102529f, 0.957680f, 9.589969f, 0 }, + { 0.967257f, 0.730231f, 9.928748f, 0 }, + { 0.428562f, 0.812831f, 10.267527f, 0 }, + { 0.254982f, 1.097741f, 10.530889f, 0 }, + { 0.830787f, 1.238999f, 10.898398f, 0 }, + { 1.181538f, 1.061828f, 11.079161f, 0 }, + { 1.320401f, 1.142033f, 11.312595f, 0 }, + { 1.430535f, 0.967257f, 11.358085f, 0 }, + { 1.130062f, 0.909796f, 11.218024f, 0 }, + { 0.805648f, 0.810437f, 11.358085f, 0 }, + { 0.553060f, 0.751779f, 11.392801f, 0 }, + { 0.617704f, 0.609324f, 11.170140f, 0 }, + { 0.879869f, 0.511162f, 11.275485f, 0 }, + { 0.829590f, 0.587776f, 11.293442f, 0 }, + { 0.312443f, 0.672770f, 11.064795f, 0 }, + { 0.293290f, 0.867898f, 10.777492f, 0 }, + { 0.509965f, 0.920570f, 10.351324f, 0 }, + { 0.536301f, 1.023521f, 10.133451f, 0 }, + { 0.774524f, 1.107318f, 10.016136f, 0 }, + { 1.381453f, 0.903811f, 9.916777f, 0 }, + { 1.589749f, 0.810437f, 9.695313f, 0 }, + { 1.593340f, 0.811634f, 9.537296f, 0 }, + { 1.824380f, 0.887051f, 9.521733f, 0 }, + { 1.902192f, 0.964863f, 9.576800f, 0 }, + { 1.674743f, 1.398213f, 9.964661f, 0 }, + { 1.234210f, 1.440111f, 9.610319f, 0 }, + { 1.334767f, 1.115697f, 9.568420f, 0 }, + { 1.393424f, 1.659181f, 9.431952f, 0 }, + { 1.001973f, 2.656365f, 9.647429f, 0 }, + { 0.780509f, 3.013101f, 9.451105f, 0 }, + { 1.270123f, 3.008312f, 9.417586f, 0 }, + { 1.909375f, 3.031057f, 9.946704f, 0 }, + { 1.747766f, 3.309982f, 9.271540f, 0 }, + { 1.356314f, 3.300405f, 8.287523f, 0 }, + { 0.751779f, 3.156753f, 7.970292f, 0 }, + { 0.063446f, 3.359063f, 8.893256f, 0 }, + { 0.136469f, 3.002327f, 8.529338f, 0 }, + { 0.253785f, 3.015495f, 8.072045f, 0 }, + { -0.045490f, 3.882195f, 8.609544f, 0 }, + { 0.149638f, 4.250902f, 9.435542f, 0 }, + { 1.071405f, 3.465605f, 9.838965f, 0 }, + { 1.856702f, 3.051408f, 11.276682f, 0 }, + { 2.770089f, 2.961626f, 10.789463f, 0 }, + { 3.514686f, 2.636014f, 7.386107f, 0 }, + { 3.545810f, 2.828747f, 7.304704f, 0 }, + { 3.815158f, 3.108869f, 6.725308f, 0 }, + { 3.323150f, 3.184286f, 4.733334f, 0 }, + { 2.572568f, 3.155556f, 6.907267f, 0 }, + { 3.299208f, 2.012325f, 9.501383f, 0 }, + { 3.531445f, 2.621649f, 8.761575f, 0 }, + { 4.510673f, 3.228579f, 12.022475f, 0 }, + { 6.127955f, 1.776496f, 13.516457f, 0 }, + { 5.631158f, 1.547850f, 11.772282f, 0 }, + { 5.889732f, -0.058658f, 7.119154f, 0 }, + { 4.481943f, 1.406592f, 6.591233f, 0 }, + { 4.230552f, 1.640027f, 9.447514f, 0 }, + { 4.007891f, 0.654814f, 11.417940f, 0 }, + { 4.525038f, 0.415394f, 11.757916f, 0 }, + { 4.125207f, 0.555454f, 10.915158f, 0 }, + { 3.624819f, 0.526724f, 9.951492f, 0 }, + { 3.210622f, 0.480037f, 10.086765f, 0 }, + { 3.298011f, 1.221042f, 9.670174f, 0 }, + { 3.142388f, 1.479616f, 9.212882f, 0 }, + { 2.955640f, 1.448491f, 8.816642f, 0 }, + { 3.101686f, 2.088940f, 9.536098f, 0 }, + { 3.215411f, 2.460041f, 9.319424f, 0 }, + { 3.247732f, 2.573765f, 8.180982f, 0 }, + { 3.251324f, 2.348710f, 8.084017f, 0 }, + { 3.372231f, 2.255337f, 9.076412f, 0 }, + { 3.545810f, 2.310403f, 9.700102f, 0 }, + { 3.739741f, 2.173934f, 9.156618f, 0 }, + { 3.809172f, 1.825577f, 9.087187f, 0 }, + { 3.727770f, 1.434126f, 9.709679f, 0 }, + { 3.596088f, 1.175552f, 10.115496f, 0 }, + { 3.452436f, 1.128865f, 9.888046f, 0 }, + { 3.217805f, 1.009155f, 9.366111f, 0 }, + { 3.197454f, 1.152807f, 9.042893f, 0 }, + { 3.360260f, 1.312022f, 8.710100f, 0 }, + { 3.630804f, 1.417366f, 8.561660f, 0 }, + { 3.858253f, 1.345540f, 8.723268f, 0 }, + { 4.018665f, 1.070207f, 9.018951f, 0 }, + { 4.181470f, 0.847547f, 9.135071f, 0 }, + { 4.359838f, 0.720654f, 9.123099f, 0 }, + { 4.487928f, 0.720654f, 9.082398f, 0 }, + { 4.380189f, 0.676362f, 9.085989f, 0 }, + { 4.357444f, 0.766144f, 9.149436f, 0 }, + { 4.260479f, 0.820014f, 8.944732f, 0 }, + { 4.271253f, 0.809240f, 9.156618f, 0 }, + { 4.315546f, 0.563834f, 9.089581f, 0 }, + { 4.484337f, 0.366313f, 8.816642f, 1 }, + { 4.460395f, 0.489614f, 8.925578f, 0 }, + { 4.448424f, 0.270545f, 9.436740f, 0 }, + { 4.559754f, 0.149638f, 9.291890f, 0 }, + { 4.551374f, 0.318429f, 8.737633f, 0 }, + { 4.523841f, 0.301669f, 8.877694f, 0 }, + { 4.411314f, 0.075417f, 9.094369f, 0 }, + { 4.203018f, -0.062249f, 9.162603f, 0 }, + { 4.171894f, -0.029928f, 8.957899f, 0 }, + { 4.235340f, -0.195127f, 9.186545f, 0 }, + { 4.386175f, -0.499191f, 9.753971f, 0 }, + { 4.505885f, -0.679953f, 10.381251f, 0 }, + { 4.586090f, -0.547075f, 10.471034f, 0 }, + { 4.892548f, -0.622492f, 9.931142f, 0 }, + { 5.498281f, -0.993593f, 9.714467f, 0 }, + { 5.907689f, -1.383848f, 9.782701f, 0 }, + { 6.193796f, -1.279700f, 9.963464f, 0 }, + { 6.526589f, -1.408987f, 8.862131f, 0 }, + { 6.619963f, -2.099714f, 7.775165f, 0 }, + { 6.324279f, -2.311600f, 7.964306f, 0 }, + { 5.984303f, -2.063801f, 9.196122f, 0 }, + { 5.639538f, -1.571792f, 8.735239f, 0 }, + { 5.276817f, -1.029506f, 7.680594f, 0 }, + { 5.011061f, -0.629675f, 7.769179f, 0 }, + { 4.618412f, -0.131681f, 8.444344f, 0 }, + { 4.189850f, 0.440533f, 8.780728f, 0 }, + { 4.214989f, 1.012747f, 8.608346f, 0 }, + { 4.211398f, 1.684320f, 8.520958f, 0 }, + { 4.193441f, 2.132035f, 9.264358f, 0 }, + { 4.256888f, 2.742556f, 9.690525f, 0 }, + { 4.542994f, 3.782836f, 9.542085f, 0 }, + { 5.335475f, 4.732136f, 8.649048f, 0 }, + { 5.679042f, 5.600034f, 7.328646f, 0 }, + { 5.938813f, 6.015428f, 5.878958f, 0 }, + { 5.702984f, 5.841848f, 3.946839f, 0 }, + { 5.978318f, 4.942826f, 2.680307f, 0 }, + { 6.204569f, 4.444832f, 3.429692f, 0 }, + { 6.102816f, 4.230552f, 4.288013f, 0 }, + { 6.244074f, 4.173091f, 4.954797f, 0 }, + { 6.355404f, 3.830720f, 5.212173f, 0 }, + { 7.004232f, 3.655943f, 4.850649f, 0 }, + { 7.965504f, 2.867055f, 4.497505f, 0 }, + { 8.603558f, 3.070562f, 4.267662f, 0 }, + { 9.105143f, 4.338291f, 4.809948f, 0 }, + { 8.657428f, 4.848255f, 3.834311f, 0 }, + { 7.819458f, 5.075704f, 0.330400f, 0 }, + { 7.815866f, 5.650312f, -3.190272f, 0 }, + { 7.144293f, 6.502647f, -10.860091f, 0 }, + { 7.374136f, 4.941629f, -7.758405f, 0 }, + { 8.832204f, 3.672703f, 0.448913f, 0 }, + { 9.153027f, 3.536233f, 0.270545f, 0 }, + { 8.880088f, 4.343079f, 0.025139f, 0 }, + { 8.923183f, 4.811145f, -0.472855f, 0 }, + { 9.080004f, 4.722559f, -0.604536f, 0 }, + { 9.029726f, 4.490322f, -0.079009f, 0 }, + { 9.149436f, 4.181470f, -0.168791f, 0 }, + { 9.192532f, 4.162317f, -0.488417f, 0 }, + { 9.105143f, 4.446030f, -0.647631f, 0 }, + { 9.289496f, 4.550177f, -0.691924f, 0 }, + { 9.198517f, 4.359838f, -0.305261f, 0 }, + { 8.995009f, 4.213792f, 0.192733f, 0 }, + { 8.955505f, 4.545389f, -0.177171f, 0 }, + { 8.451527f, 5.149924f, -1.136048f, 0 }, + { 7.418429f, 5.443214f, 0.033519f, 0 }, + { 6.846215f, 5.254072f, 2.087743f, 0 }, + { 7.192177f, 4.586090f, 3.452436f, 0 }, + { 7.727281f, 3.658338f, 3.614045f, 0 }, + { 8.420402f, 3.105278f, 2.424128f, 0 }, + { 9.446317f, 2.968808f, 1.719036f, 0 }, + { 9.706087f, 2.862266f, 2.051830f, 0 }, + { 9.520536f, 2.778469f, 2.466026f, 0 }, + { 9.439134f, 2.862266f, 3.065773f, 0 }, + { 8.769955f, 3.287237f, 3.415326f, 0 }, + { 8.048103f, 3.784033f, 2.977188f, 0 }, + { 7.817063f, 3.926488f, 1.849520f, 0 }, + { 8.365335f, 3.857056f, 0.901416f, 0 }, + { 8.749604f, 3.778048f, 0.855927f, 0 }, + { 7.741646f, 4.425679f, 1.212662f, 0 }, + { 6.775586f, 5.135559f, 1.638830f, 0 }, + { 7.811078f, 4.550177f, 3.052605f, 0 }, + { 8.285130f, 4.247311f, 3.077744f, 0 }, + { 8.590390f, 4.511870f, 2.555809f, 0 }, + { 8.787911f, 4.813539f, 2.319980f, 0 }, + { 8.252808f, 4.928461f, 1.952470f, 0 }, + { 7.679397f, 4.880577f, 1.568201f, 0 }, + { 7.946350f, 4.525038f, 1.531091f, 0 }, + { 8.236049f, 4.353853f, 1.537076f, 0 }, + { 8.593981f, 4.235340f, 1.843534f, 0 }, + { 8.511381f, 4.062957f, 1.691502f, 0 }, + { 8.268370f, 4.389766f, 1.649604f, 0 }, + { 8.129506f, 5.080492f, 1.691502f, 0 }, + { 8.280341f, 5.632356f, 1.444900f, 0 }, + { 8.936352f, 5.948390f, 1.972821f, 0 }, + { 10.184927f, 5.974726f, 3.705025f, 0 }, + { 11.186900f, 5.440820f, 3.477576f, 0 }, + { 11.239573f, 4.985922f, 1.543062f, 0 }, + { 11.077964f, 4.748896f, 1.107318f, 0 }, + { 10.912764f, 4.514264f, 1.528697f, 0 }, + { 10.890019f, 3.810369f, 1.624465f, 0 }, + { 9.329000f, 2.948457f, 1.057039f, 0 }, + { 7.509408f, 2.424128f, 1.201888f, 0 }, + { 7.207739f, 1.965638f, 1.035492f, 0 }, + { 7.030569f, 1.936908f, 0.076614f, 0 }, + { 6.907267f, 2.347513f, -0.646434f, 0 }, + { 7.483072f, 2.871843f, -0.088585f, 0 }, + { 8.190558f, 3.590103f, 1.675940f, 0 }, + { 8.498213f, 3.961204f, 1.974018f, 0 }, + { 8.552083f, 3.774457f, 1.284488f, 0 }, + { 8.402445f, 3.895364f, 2.099714f, 0 }, + { 8.273158f, 4.100068f, 2.432507f, 0 }, + { 8.030147f, 4.141966f, 1.668757f, 0 }, + { 7.900860f, 4.010285f, 1.027112f, 0 }, + { 7.912831f, 3.936065f, 0.803254f, 0 }, + { 7.878115f, 4.007891f, 0.687135f, 0 }, + { 7.789530f, 4.050986f, 0.326808f, 0 }, + { 8.213304f, 3.869027f, 0.050278f, 0 }, + { 8.558068f, 3.667914f, 0.016759f, 0 }, + { 8.617923f, 3.523065f, 0.405817f, 0 }, + { 8.524549f, 3.506306f, 0.683544f, 0 }, + { 8.438358f, 3.640381f, 0.433350f, 0 }, + { 8.262384f, 3.952824f, 0.190339f, 0 }, + { 8.115141f, 4.276042f, 0.306458f, 0 }, + { 8.386883f, 4.367021f, 0.554257f, 0 }, + { 8.827415f, 4.244917f, 0.985213f, 0 }, + { 9.200911f, 4.337093f, 0.806845f, 0 }, + { 10.524903f, 4.668690f, -0.792480f, 0 }, + { 11.640601f, 4.612426f, -1.328781f, 0 }, + { 11.060007f, 4.495111f, -0.488417f, 0 }, + { 9.582786f, 5.093661f, 0.833182f, 0 }, + { 9.582786f, 5.696999f, 1.917754f, 0 }, + { 10.176547f, 5.428849f, 1.911769f, 0 }, + { 10.186124f, 5.148727f, 2.031479f, 0 }, + { 9.921565f, 4.803962f, 2.525881f, 0 }, + { 9.082398f, 3.547007f, 2.503136f, 0 }, + { 8.127112f, 2.201467f, 3.013101f, 0 }, + { 8.121126f, 2.080560f, 3.895364f, 0 }, + { 7.538139f, 3.345895f, 3.219002f, 0 }, + { 7.010218f, 3.763683f, 2.015916f, 0 }, + { 7.691368f, 3.278857f, 1.988383f, 0 }, + { 9.029726f, 2.555809f, 2.470814f, 0 }, + { 9.815023f, 2.255337f, 1.878250f, 0 }, + { 9.594757f, 2.603693f, 0.724246f, 0 }, + { 8.785517f, 3.135205f, 0.660799f, 0 }, + { 8.186967f, 3.447648f, 1.098938f, 0 }, + { 7.940364f, 3.257309f, 1.605311f, 0 }, + { 7.721295f, 2.911347f, 1.705868f, 0 }, + { 7.763194f, 2.804805f, 1.307233f, 0 }, + { 8.137886f, 2.965217f, 1.130062f, 0 }, + { 8.329422f, 3.266886f, 1.200691f, 0 }, + { 8.224077f, 3.472787f, 1.547850f, 0 }, + { 7.841005f, 3.687068f, 1.614888f, 0 }, + { 7.527365f, 4.015073f, 1.435323f, 0 }, + { 7.979869f, 4.304772f, 1.449688f, 0 }, + { 6.466734f, 4.948812f, 0.798466f, 0 }, + { 5.912477f, 5.204991f, 0.487220f, 0 }, + { 8.413219f, 5.108026f, 3.270477f, 0 }, + { 9.945507f, 5.396527f, 3.342303f, 0 }, + { 10.691300f, 5.128376f, 2.308009f, 0 }, + { 10.842135f, 4.801568f, 1.601720f, 0 }, + { 9.938325f, 4.821919f, 1.177946f, 0 }, + { 8.507790f, 4.671084f, 1.237801f, 0 }, + { 8.838189f, 4.602849f, 2.097319f, 0 }, + { 10.510538f, 4.817131f, 2.170342f, 0 }, + { 12.216406f, 4.753684f, 1.561018f, 0 }, + { 12.654545f, 3.897758f, 0.378284f, 0 }, + { 11.204856f, 1.860294f, -0.105345f, 0 }, + { 8.844175f, 0.367510f, 1.064222f, 0 }, + { 7.511803f, 0.355539f, 1.830366f, 0 }, + { 7.447159f, 0.761356f, 1.376665f, 0 }, + { 7.492649f, 1.477221f, 1.074996f, 0 }, + { 7.439977f, 1.969230f, 1.636436f, 0 }, + { 8.178588f, 2.361878f, 2.212241f, 0 }, + { 9.138661f, 2.566582f, 3.772062f, 0 }, + { 8.628697f, 3.113657f, 5.457579f, 0 }, + { 7.310690f, 3.958810f, 4.115630f, 0 }, + { 6.605598f, 3.852268f, -0.732625f, 0 }, + { 7.333435f, 2.907756f, -0.568623f, 0 }, + { 7.597994f, 2.693475f, 1.482010f, 0 }, + { 7.583629f, 2.049435f, 0.691924f, 0 }, + { 9.470259f, 0.593762f, -0.951695f, 0 }, + { 10.658978f, 0.784101f, -0.517147f, 0 }, + { 10.287878f, 1.835154f, 0.626083f, 0 }, + { 9.807840f, 2.612072f, 1.288080f, 0 }, + { 8.984236f, 2.947260f, 0.714669f, 0 }, + { 8.761575f, 2.649182f, -0.256179f, 0 }, + { 8.923183f, 2.196679f, -0.543483f, 0 }, + { 8.926775f, 1.908177f, -0.259771f, 0 }, + { 8.783123f, 2.282870f, 0.343568f, 0 }, + { 8.637076f, 2.968808f, 0.847547f, 0 }, + { 9.196122f, 2.409762f, 1.001973f, 0 }, + { 10.965436f, 2.219424f, -0.040701f, 0 }, + { 12.228376f, 2.415748f, -2.486377f, 0 }, + { 11.583140f, 2.370258f, -2.585736f, 0 }, + { 10.394420f, 2.659956f, -0.113724f, 0 }, + { 9.483426f, 3.004721f, 1.859096f, 0 }, + { 9.071624f, 3.149570f, 2.835930f, 0 }, + { 9.080004f, 3.254915f, 3.105278f, 0 }, + { 9.205699f, 3.192666f, 3.260900f, 0 }, + { 9.168590f, 2.627635f, 3.888181f, 0 }, + { 8.310268f, 1.988383f, 3.989934f, 0 }, + { 6.813893f, 1.753752f, 3.471590f, 0 }, + { 6.712140f, 1.843534f, 3.975569f, 0 }, + { 7.686579f, 1.092952f, 4.849452f, 0 }, + { 8.225274f, -0.057461f, 5.044580f, 0 }, + { 9.645035f, -1.168370f, 5.014652f, 0 }, + { 10.184927f, -1.946485f, 5.219356f, 0 }, + { 9.691722f, -2.285264f, 4.790794f, 0 }, + { 9.776716f, -2.582145f, 4.147952f, 0 }, + { 9.946704f, -2.756921f, 3.651155f, 0 }, + { 9.209291f, -2.138021f, 3.199848f, 0 }, + { 8.215697f, -1.181538f, 2.749739f, 0 }, + { 7.557292f, -0.480037f, 2.457646f, 0 }, + { 7.584826f, -0.227449f, 2.263716f, 0 }, + { 8.142674f, 0.092177f, 1.337161f, 0 }, + { 8.587996f, 0.541089f, -0.260968f, 0 }, + { 9.088384f, 0.393846f, -1.416169f, 0 }, + { 9.514551f, 0.010774f, -0.566228f, 0 }, + { 9.374491f, 0.046687f, 0.678756f, 0 }, + { 9.302665f, 0.275333f, 0.553060f, 0 }, + { 9.515748f, 0.501585f, 0.005986f, 0 }, + { 9.652218f, 0.667982f, -0.077812f, 0 }, + { 9.983814f, 0.775721f, 0.123301f, 0 }, + { 10.466246f, 0.855927f, 0.921767f, 0 }, + { 11.034868f, 0.636857f, 1.392227f, 0 }, + { 11.848896f, -0.166397f, 0.960074f, 0 }, + { 12.391183f, -1.085770f, 0.053870f, 0 }, + { 12.482162f, -1.602917f, -0.912190f, 0 }, + { 12.077542f, -1.947682f, -1.058236f, 0 }, + { 11.311399f, -1.833957f, -0.653617f, 0 }, + { 10.664965f, -1.778891f, 0.350750f, 0 }, + { 9.764745f, -2.568977f, 2.135627f, 0 }, + { 8.580813f, -3.081336f, 2.833536f, 0 }, + { 7.436386f, -2.665942f, 2.202664f, 0 }, + { 6.769601f, -1.289277f, 2.110487f, 0 }, + { 7.038948f, 0.441730f, 3.216608f, 0 }, + { 8.155843f, 1.883038f, 4.080914f, 0 }, + { 9.284708f, 1.380256f, 3.860648f, 0 }, + { 9.452302f, -0.167594f, 2.287658f, 0 }, + { 9.560040f, -0.761356f, 0.659602f, 0 }, + { 9.497791f, -0.784101f, -0.830787f, 0 }, + { 9.290693f, -0.700303f, -1.665166f, 0 }, + { 8.920790f, -0.146046f, -1.515529f, 0 }, + { 8.766363f, 0.034716f, -0.599747f, 0 }, + { 8.348576f, -0.287304f, -0.076614f, 0 }, + { 8.081622f, -0.591367f, 0.045490f, 0 }, + { 7.095212f, -1.157596f, 1.143231f, 0 }, + { 6.483494f, -1.507149f, 0.781706f, 0 }, + { 6.980290f, -1.605311f, 0.519541f, 0 }, + { 8.282735f, -1.045068f, 1.046265f, 0 }, + { 7.284354f, -1.468842f, 0.658405f, 0 }, + { 8.409628f, -2.402580f, -0.105345f, 0 }, + { 10.058035f, -2.456449f, 2.020705f, 0 }, + { 11.830939f, -2.476800f, 2.808397f, 0 }, + { 12.722779f, -1.401804f, 0.846350f, 0 }, + { 11.550818f, -0.071826f, -3.417721f, 0 }, + { 10.788265f, -0.575805f, -7.012612f, 0 }, + { 10.037683f, -1.229422f, -8.307875f, 0 }, + { 9.273934f, -0.415394f, -6.815091f, 0 }, + { 9.394841f, 0.909796f, -5.343854f, 0 }, + { 8.586799f, 1.194706f, -2.789243f, 0 }, + { 8.435964f, 0.617704f, -0.373495f, 0 }, + { 8.913607f, -0.415394f, 0.533907f, 0 }, + { 8.986629f, -1.616085f, 0.727837f, 0 }, + { 8.663413f, -2.105699f, 1.237801f, 0 }, + { 8.337802f, -2.239774f, 1.921346f, 0 }, + { 8.827415f, -2.661153f, 2.705446f, 0 }, + { 9.233232f, -3.117249f, 3.457225f, 0 }, + { 9.272737f, -2.991553f, 3.994723f, 0 }, + { 8.706509f, -2.610875f, 4.343079f, 0 }, + { 7.984657f, -2.519896f, 4.351459f, 0 }, + { 8.218092f, -3.441663f, 4.805160f, 0 }, + { 9.825797f, -4.513067f, 4.161120f, 0 }, + { 10.711651f, -6.089648f, 4.596864f, 0 }, + { 11.142607f, -7.103591f, 3.855859f, 0 }, + { 10.658978f, -6.648694f, 3.931277f, 0 }, + { 10.046063f, -5.696999f, 4.780020f, 0 }, + { 9.539690f, -4.680661f, 5.057748f, 0 }, + { 7.566869f, -3.590103f, 4.860226f, 0 }, + { 6.440398f, -3.344697f, 4.193441f, 0 }, + { 6.586444f, -3.541022f, 3.108869f, 0 }, + { 7.125139f, -3.699039f, 0.994790f, 0 }, + { 8.431175f, -4.952403f, -2.618058f, 0 }, + { 9.090777f, -5.112814f, -7.767982f, 0 }, + { 8.908818f, -3.330332f, -9.904806f, 0 }, + { 8.309072f, -1.798044f, -7.811078f, 0 }, + { 8.213304f, -1.308430f, -7.665031f, 0 }, + { 8.283933f, -1.283291f, -4.946417f, 0 }, + { 8.704114f, -1.482010f, -1.357511f, 0 }, + { 8.904030f, -1.138442f, -0.214281f, 0 }, + { 9.314635f, -1.148019f, -0.150835f, 0 }, + { 9.588771f, -0.961271f, -1.286883f, 0 }, + { 9.983814f, -0.888248f, -3.894166f, 0 }, + { 10.663767f, -0.937329f, -6.470325f, 0 }, + { 11.098314f, -0.972045f, -6.862975f, 0 }, + { 10.899596f, -1.125274f, -5.509054f, 0 }, + { 10.278301f, -1.490390f, -3.240550f, 0 }, + { 9.907200f, -1.777694f, -0.620098f, 0 }, + { 8.779531f, -2.339134f, 1.922543f, 0 }, + { 7.435188f, -2.651577f, 4.188653f, 0 }, + { 6.859383f, -2.463632f, 5.175064f, 0 }, + { 6.631934f, -2.347513f, 5.786782f, 0 }, + { 6.870157f, -2.407368f, 6.654679f, 0 }, + { 7.872130f, -2.549823f, 6.404485f, 0 }, + { 9.375688f, -3.722981f, 3.958810f, 0 }, + { 11.268303f, -5.311533f, -0.108936f, 0 }, + { 12.009308f, -6.212949f, -5.847834f, 0 }, + { 10.462654f, -5.131968f, -11.382027f, 0 }, + { 7.885298f, -2.762907f, -11.698062f, 0 }, + { 7.011415f, -1.878250f, -9.295482f, 0 }, + { 6.627146f, -1.376665f, -6.520604f, 0 }, + { 7.509408f, -1.753752f, -3.491941f, 0 }, + { 8.297100f, -1.997960f, -0.979228f, 0 }, + { 8.939943f, -1.666363f, -0.052672f, 0 }, + { 8.857343f, -0.831985f, 0.451307f, 0 }, + { 8.007402f, -0.197522f, 1.444900f, 0 }, + { 7.693762f, 0.035913f, 3.700236f, 0 }, + { 7.378925f, -0.505176f, 3.415326f, 0 }, + { 5.979515f, -1.707065f, -0.325611f, 0 }, + { 7.726084f, -3.241747f, -5.707773f, 0 }, + { 8.884876f, -3.162738f, -12.425899f, 0 }, + { 9.512156f, 0.045490f, -13.029237f, 0 }, + { 8.766363f, 1.078587f, -6.048946f, 0 }, + { 8.428782f, -0.650025f, -1.023521f, 0 }, + { 8.790305f, -0.999579f, 1.993172f, 0 }, + { 9.354139f, -0.804451f, 2.904165f, 0 }, + { 10.168168f, -1.060631f, -0.969651f, 0 }, + { 11.595111f, -1.048660f, -4.067746f, 0 }, + { 13.030434f, -0.831985f, -6.460749f, 0 }, + { 11.122256f, 0.191536f, -7.928393f, 0 }, + { 9.040500f, 0.798466f, -6.001062f, 0 }, + { 8.956702f, 0.328005f, -1.649604f, 0 }, + { 9.064442f, 0.119710f, 0.561440f, 0 }, + { 9.356534f, 0.306458f, 0.186748f, 0 }, + { 10.399208f, -0.664391f, -0.585382f, 0 }, + { 11.281470f, -1.975215f, -2.223015f, 0 }, + { 10.011348f, -1.996763f, -4.955994f, 0 }, + { 9.003389f, -2.169145f, -6.757630f, 0 }, + { 8.583207f, -2.082954f, -5.573698f, 0 }, + { 8.798685f, -1.921346f, -2.810791f, 0 }, + { 8.974659f, -1.520317f, -1.250970f, 0 }, + { 8.078031f, -0.515950f, 0.366313f, 0 }, + { 6.692986f, 0.751779f, 2.220621f, 0 }, + { 6.210555f, 1.480813f, 1.197100f, 0 }, + { 7.131125f, 0.602141f, -2.041055f, 0 }, + { 8.007402f, 0.234632f, -4.835087f, 0 }, + { 8.462300f, 0.919373f, -5.451593f, 0 }, + { 7.928393f, 1.326387f, -4.395751f, 0 }, + { 6.871354f, 1.467645f, -2.835930f, 0 }, + { 6.029793f, 1.558624f, -0.976834f, 0 }, + { 5.135559f, 1.978806f, 0.028730f, 0 }, + { 7.839808f, 1.517923f, 0.440533f, 0 }, + { 11.483781f, 0.501585f, -0.684741f, 0 }, + { 9.314635f, 0.493205f, -3.245338f, 0 }, + { 8.585602f, 0.633266f, -4.395751f, 0 }, + { 9.229641f, 0.914584f, -4.349064f, 0 }, + { 9.064442f, 0.970848f, -3.658338f, 0 }, + { 9.977829f, 0.555454f, -2.989159f, 0 }, + { 9.810235f, 0.744596f, -3.434480f, 0 }, + { 9.325409f, 1.397016f, -3.568555f, 0 }, + { 9.496594f, 1.741781f, -3.239353f, 0 }, + { 10.398011f, 1.367088f, -3.130417f, 0 }, + { 10.730804f, 0.985213f, -2.704249f, 0 }, + { 10.894808f, 1.125274f, -1.823183f, 0 }, + { 11.997336f, 0.918176f, -2.120064f, 0 }, + { 12.749115f, 0.508767f, -3.248930f, 0 }, + { 12.022475f, 0.416591f, -3.471590f, 0 }, + { 10.839741f, 0.440533f, -5.136756f, 0 }, + { 10.629051f, 0.883460f, -8.376109f, 0 }, + { 11.104300f, 1.051054f, -8.720874f, 0 }, + { 10.903187f, 0.842758f, -5.995077f, 0 }, + { 11.470613f, 0.239420f, -2.959231f, 0 }, + { 11.871641f, -0.373495f, -0.988805f, 0 }, + { 9.727634f, -0.487220f, 1.842337f, 0 }, + { 6.479902f, -0.034716f, 3.007115f, 0 }, + { 4.198230f, 0.515950f, 3.420115f, 0 }, + { 2.959231f, 1.742978f, 3.507503f, 0 }, + { 3.488349f, 2.468420f, 2.369061f, 0 }, + { 5.433637f, 2.197876f, -2.054224f, 0 }, + { 6.564897f, 2.667139f, -4.945220f, 0 }, + { 7.331040f, 3.190272f, -2.327163f, 0 }, + { 10.497370f, 3.070562f, 0.073023f, 0 }, + { 10.967831f, 1.744175f, -2.159569f, 0 }, + { 10.575182f, 0.481234f, -3.937262f, 0 }, + { 10.111904f, 0.632069f, -2.493559f, 0 }, + { 9.317030f, 1.003170f, -0.973242f, 0 }, + { 8.687355f, 1.310825f, -0.208295f, 0 }, + { 8.713691f, 1.209071f, -0.918176f, 0 }, + { 8.810657f, 1.183932f, -2.063801f, 0 }, + { 8.763969f, 1.406592f, -2.553414f, 0 }, + { 8.019373f, 1.916557f, -2.993947f, 0 }, + { 7.505817f, 2.184708f, -3.209425f, 0 }, + { 7.550110f, 2.245760f, -2.833536f, 0 }, + { 7.843400f, 2.250548f, -2.468420f, 0 }, + { 8.210909f, 2.315192f, -2.410959f, 0 }, + { 8.468286f, 2.409762f, -3.126825f, 0 }, + { 8.376109f, 2.358287f, -3.925291f, 0 }, + { 8.769955f, 2.191890f, -3.524262f, 0 }, + { 9.360126f, 2.389412f, -3.094504f, 0 }, + { 10.235206f, 2.645591f, -4.356247f, 0 }, + { 10.369281f, 3.308784f, -5.960361f, 0 }, + { 9.583982f, 3.739741f, -6.137532f, 0 }, + { 9.226050f, 3.244141f, -4.029438f, 0 }, + { 9.249992f, 3.345895f, -1.376665f, 0 }, + { 9.409206f, 3.989934f, 0.690727f, 0 }, + { 9.866499f, 4.723757f, 1.246181f, 0 }, + { 11.179717f, 3.829523f, -0.788889f, 0 }, + { 12.655742f, 2.403777f, -3.202243f, 0 }, + { 12.897555f, 0.988805f, -4.781218f, 0 }, + { 11.311399f, 0.092177f, -4.595667f, 0 }, + { 8.464694f, 0.628478f, -2.196679f, 0 }, + { 6.581656f, 1.258152f, -0.107739f, 0 }, + { 6.366178f, 1.856702f, 0.781706f, 0 }, + { 6.930012f, 1.881841f, 0.209493f, 0 }, + { 7.776362f, 0.798466f, -0.858321f, 0 }, + { 8.432373f, -0.011971f, -1.729810f, 0 }, + { 8.836992f, -0.251391f, -2.906559f, 0 }, + { 8.950717f, -0.007183f, -3.992329f, 0 }, + { 8.702917f, 0.239420f, -3.590103f, 0 }, + { 8.307875f, 0.493205f, -2.304418f, 0 }, + { 7.890086f, 1.065419f, -1.701079f, 0 }, + { 7.886495f, 1.557427f, -1.941696f, 0 }, + { 8.344984f, 1.771708f, -2.163160f, 0 }, + { 8.882483f, 2.037464f, -2.286461f, 0 }, + { 8.996207f, 2.401383f, -2.816776f, 0 }, + { 9.011769f, 2.549823f, -3.086124f, 0 }, + { 9.118311f, 2.431310f, -3.043028f, 0 }, + { 9.022543f, 2.371455f, -3.132811f, 0 }, + { 8.949520f, 2.278081f, -3.059788f, 0 }, + { 9.159013f, 2.190693f, -2.688687f, 0 }, + { 9.372096f, 2.074574f, -2.284067f, 0 }, + { 9.406812f, 2.118867f, -1.695094f, 0 }, + { 9.403221f, 2.088940f, -1.282094f, 0 }, + { 9.539690f, 2.345119f, -1.448491f, 0 }, + { 9.548070f, 2.826353f, -2.069786f, 0 }, + { 9.326607f, 3.178301f, -2.748542f, 0 }, + { 9.295482f, 3.290828f, -2.521093f, 0 }, + { 10.214854f, 3.190272f, -2.946063f, 0 }, + { 11.439487f, 3.104080f, -4.429270f, 0 }, + { 12.179296f, 2.619255f, -5.501872f, 0 }, + { 12.650953f, 1.750160f, -4.109644f, 0 }, + { 11.921919f, 0.913387f, -1.047463f, 0 }, + { 10.370478f, 0.256179f, 0.997184f, 0 }, + { 9.369702f, -0.351947f, 2.355893f, 0 }, + { 7.855371f, -0.039504f, 2.788046f, 0 }, + { 6.522998f, 0.343568f, 1.185129f, 0 }, + { 6.356601f, 0.954089f, -0.673967f, 0 }, + { 6.839033f, 1.606508f, -1.197100f, 0 }, + { 8.453920f, 1.814804f, -0.993593f, 0 }, + { 9.556450f, 1.889024f, -0.434547f, 0 }, + { 9.387658f, 2.385820f, -0.804451f, 0 }, + { 9.039303f, 2.761710f, -1.951273f, 0 }, + { 8.828612f, 2.579751f, -2.316389f, 0 }, + { 8.649048f, 2.282870f, -2.097319f, 0 }, + { 8.495819f, 2.323571f, -1.842337f, 0 }, + { 8.274356f, 2.814382f, -1.483207f, 0 }, + { 8.022964f, 3.214214f, -1.207874f, 0 }, + { 7.991840f, 3.224988f, -1.155202f, 0 }, + { 8.200135f, 3.023875f, -1.380256f, 0 }, + { 8.465892f, 2.995144f, -1.857899f, 0 }, + { 8.471877f, 3.099292f, -2.273293f, 0 }, + { 8.388080f, 3.125628f, -2.305615f, 0 }, + { 8.433570f, 3.105278f, -2.064998f, 0 }, + { 8.494622f, 3.213017f, -1.946485f, 0 }, + { 8.669398f, 3.210622f, -2.211044f, 0 }, + { 8.773546f, 3.099292f, -2.907756f, 0 }, + { 8.705312f, 3.130417f, -3.394976f, 0 }, + { 8.570039f, 3.405750f, -1.821986f, 0 }, + { 8.820233f, 3.371034f, -1.948879f, 0 }, + { 9.376884f, 3.290828f, -4.145557f, 0 }, + { 9.933537f, 3.511094f, -5.504266f, 0 }, + { 10.266330f, 3.343500f, -4.606441f, 0 }, + { 10.199292f, 3.286040f, -2.880223f, 0 }, + { 10.279498f, 3.457225f, -2.645591f, 0 }, + { 10.939100f, 3.313573f, -3.344697f, 0 }, + { 11.617856f, 1.872265f, -3.330332f, 0 }, + { 11.283865f, 0.302866f, -2.816776f, 0 }, + { 8.844175f, 0.647631f, -0.970848f, 0 }, + { 6.621161f, 1.608902f, 0.426168f, 0 }, + { 6.217738f, 2.564188f, 0.738611f, 0 }, + { 6.973108f, 3.286040f, -0.644040f, 0 }, + { 8.750801f, 2.173934f, -1.210268f, 0 }, + { 10.366886f, 0.428562f, -1.189917f, 0 }, + { 10.743973f, 0.110133f, -1.969230f, 0 }, + { 10.110707f, 0.746990f, -2.530669f, 0 }, + { 8.839387f, 1.630450f, -2.548626f, 0 }, + { 7.795516f, 2.329557f, -2.692278f, 0 }, + { 7.451948f, 2.700658f, -2.602495f, 0 }, + { 7.606374f, 2.907756f, -2.309206f, 0 }, + { 8.056483f, 3.023875f, -2.039858f, 0 }, + { 8.440752f, 3.139993f, -1.945288f, 0 }, + { 8.403643f, 3.387793f, -1.736992f, 0 }, + { 8.280341f, 3.640381f, -1.544259f, 0 }, + { 8.359349f, 3.767274f, -1.551442f, 0 }, + { 8.535323f, 3.780442f, -1.817198f, 0 }, + { 8.860934f, 3.679886f, -2.035070f, 0 }, + { 9.190137f, 3.599680f, -2.019508f, 0 }, + { 9.193728f, 3.535036f, -2.249351f, 0 }, + { 8.997404f, 3.507503f, -2.041055f, 0 }, + { 8.646653f, 3.554190f, -1.903389f, 0 }, + { 8.368926f, 3.604468f, -1.539471f, 0 }, + { 8.249216f, 3.761288f, -1.181538f, 0 }, + { 8.482651f, 3.960007f, -1.823183f, 0 }, + { 8.767561f, 3.967190f, -2.565385f, 0 }, + { 8.783123f, 3.831917f, -3.102883f, 0 }, + { 8.614332f, 3.810369f, -3.654746f, 0 }, + { 8.664610f, 3.786427f, -4.390963f, 0 }, + { 8.987827f, 4.016271f, -5.419272f, 0 }, + { 9.724044f, 4.271253f, -6.058523f, 0 }, + { 10.873260f, 3.715799f, -6.293155f, 0 }, + { 12.078739f, 3.123234f, -5.191823f, 0 }, + { 12.312174f, 2.310403f, -2.348710f, 0 }, + { 11.079161f, 1.405395f, 1.435323f, 0 }, + { 9.323015f, 1.150413f, 2.363075f, 0 }, + { 7.666229f, 0.990002f, 1.956061f, 0 }, + { 6.414062f, 1.784876f, 2.576159f, 0 }, + { 5.781993f, 3.196257f, 2.535458f, 0 }, + { 6.141123f, 3.886984f, 0.312443f, 0 }, + { 7.559687f, 3.445254f, -1.547850f, 0 }, + { 9.400826f, 2.853886f, -1.867476f, 0 }, + { 9.509763f, 3.022678f, -3.046620f, 0 }, + { 8.577222f, 3.954021f, -4.252100f, 0 }, + { 8.172602f, 3.744529f, -3.657140f, 0 }, + { 8.269567f, 3.207031f, -2.509122f, 0 }, + { 8.135491f, 3.442860f, -1.326387f, 0 }, + { 7.990643f, 3.718193f, -0.969651f, 0 }, + { 8.020570f, 3.763683f, -1.307233f, 0 }, + { 8.246822f, 3.590103f, -1.707065f, 0 }, + { 8.331817f, 3.252521f, -1.964441f, 0 }, + { 8.212107f, 2.896982f, -2.375046f, 0 }, + { 8.174996f, 2.774878f, -2.712629f, 0 }, + { 8.511381f, 2.673124f, -2.576159f, 0 }, + { 8.957899f, 2.570174f, -2.475603f, 0 }, + { 9.176969f, 2.637211f, -2.371455f, 0 }, + { 9.011769f, 2.729388f, -2.279279f, 0 }, + { 8.756786f, 2.636014f, -2.651577f, 0 }, + { 8.678975f, 2.534261f, -3.602074f, 0 }, + { 8.603558f, 2.598904f, -3.883393f, 0 }, + { 8.331817f, 2.859872f, -3.414129f, 0 }, + { 8.225274f, 3.234564f, -3.913320f, 0 }, + { 8.254004f, 3.434480f, -4.692632f, 0 }, + { 7.493846f, 3.796004f, -4.635171f, 0 }, + { 7.006627f, 4.036621f, -3.604468f, 0 }, + { 6.774389f, 4.210201f, -2.053027f, 0 }, + { 7.364560f, 4.368218f, -1.525105f, 0 }, + { 9.597151f, 3.620030f, -1.552639f, 0 }, + { 11.402378f, 1.831563f, -2.977188f, 0 }, + { 12.288232f, 0.525527f, -4.697421f, 0 }, + { 11.234784f, 0.181959f, -4.031833f, 0 }, + { 9.607924f, 0.386663f, -1.760934f, 0 }, + { 9.303862f, 0.387860f, -0.899022f, 0 }, + { 9.464272f, 0.622492f, -1.006761f, 0 }, + { 9.558844f, 1.036689f, -1.015141f, 0 }, + { 9.920368f, 0.829590f, -1.874659f, 0 }, + { 10.107116f, 0.355539f, -3.119643f, 0 }, + { 9.897623f, -0.099359f, -4.199427f, 0 }, + { 9.185349f, -0.276530f, -4.827904f, 0 }, + { 8.003811f, 0.396240f, -4.807554f, 0 }, + { 7.156264f, 0.701501f, -5.153516f, 0 }, + { 7.101197f, 0.053870f, -4.508279f, 0 }, + { 7.503423f, -0.792480f, -3.005918f, 0 }, + { 8.105564f, -1.297656f, -1.985989f, 0 }, + { 8.426387f, -1.464053f, -1.731007f, 0 }, + { 8.543703f, -1.358709f, -1.970427f, 0 }, + { 8.645456f, -1.344343f, -2.333148f, 0 }, + { 8.863329f, -1.558624f, -2.579751f, 0 }, + { 8.951914f, -1.918951f, -3.125628f, 0 }, + { 8.690947f, -1.860294f, -3.743332f, 0 }, + { 8.432373f, -1.956061f, -4.167105f, 0 }, + { 8.066060f, -2.053027f, -4.120419f, 0 }, + { 7.721295f, -2.195482f, -3.816355f, 0 }, + { 8.643063f, -2.871843f, -3.706222f, 0 }, + { 9.257174f, -3.336318f, -3.749317f, 0 }, + { 8.542506f, -3.499123f, -4.060563f, 0 }, + { 7.796712f, -4.046198f, -3.117249f, 0 }, + { 9.125494f, -4.362233f, -1.403001f, 0 }, + { 10.022121f, -4.328714f, 0.181959f, 0 }, + { 9.467864f, -4.274844f, 0.749385f, 0 }, + { 8.961491f, -3.708616f, -0.160411f, 0 }, + { 9.466667f, -3.045423f, -1.674743f, 0 }, + { 10.119086f, -2.406171f, -2.686292f, 0 }, + { 10.562014f, -1.898601f, -3.098095f, 0 }, + { 10.864880f, -1.751357f, -2.885011f, 0 }, + { 11.161760f, -1.505952f, -2.561794f, 0 }, + { 11.179717f, -1.201888f, -3.112460f, 0 }, + { 10.089159f, -1.221042f, -4.156332f, 0 }, + { 7.001838f, -0.794874f, -3.333924f, 0 }, + { 5.855016f, -0.556652f, -2.070983f, 0 }, + { 5.731715f, -0.816422f, -1.926134f, 0 }, + { 5.664677f, -0.999579f, -2.529472f, 0 }, + { 5.078098f, -0.949300f, -3.558978f, 0 }, + { 4.414905f, -0.963666f, -4.428073f, 0 }, + { 4.523841f, -1.501163f, -5.098449f, 0 }, + { 4.826707f, -2.104502f, -5.495886f, 0 }, + { 5.408498f, -2.646788f, -4.911702f, 0 }, + { 7.024583f, -3.204637f, -3.964795f, 0 }, + { 8.048103f, -3.580526f, -2.898179f, 0 }, + { 8.647851f, -4.011482f, -2.421733f, 0 }, + { 8.653836f, -3.981555f, -2.619255f, 0 }, + { 8.593981f, -3.761288f, -2.304418f, 0 }, + { 9.291890f, -3.605665f, -1.768117f, 0 }, + { 10.421953f, -3.653549f, -2.403777f, 0 }, + { 10.747564f, -4.040213f, -3.653549f, 0 }, + { 11.080358f, -4.187456f, -3.568555f, 0 }, + { 11.591519f, -4.479548f, -3.045423f, 0 }, + { 12.521667f, -4.991907f, -3.197454f, 0 }, + { 12.606661f, -5.301956f, -3.508700f, 0 }, + { 12.215209f, -5.559332f, -3.132811f, 0 }, + { 11.514905f, -5.664677f, -2.713826f, 0 }, + { 10.378858f, -5.208582f, -2.182313f, 0 }, + { 9.202108f, -4.546586f, -1.216254f, 0 }, + { 8.280341f, -4.206610f, -0.418985f, 0 }, + { 7.450751f, -4.313151f, 0.014365f, 0 }, + { 7.369348f, -4.450818f, 0.191536f, 0 }, + { 7.760799f, -4.636368f, 0.500388f, 0 }, + { 8.317451f, -4.886562f, 0.723048f, 0 }, + { 9.074018f, -4.566936f, 1.207874f, 0 }, + { 9.854527f, -4.408919f, 1.930922f, 0 }, + { 9.587574f, -3.520671f, 2.163160f, 0 }, + { 7.569263f, -1.774102f, 2.106896f, 0 }, + { 6.695381f, -1.079784f, 3.076547f, 0 }, + { 6.536166f, -1.090558f, 2.916136f, 0 }, + { 7.067678f, -1.138442f, 1.533485f, 0 }, + { 8.107959f, -0.973242f, -2.732979f, 0 }, + { 9.166195f, -1.021126f, -7.004232f, 0 }, + { 9.587574f, -1.686714f, -7.388502f, 0 }, + { 9.416389f, -1.589749f, -5.742489f, 0 }, + { 8.761575f, -1.954864f, -2.201467f, 0 }, + { 8.656230f, -2.102108f, -0.766144f, 0 }, + { 8.858541f, -2.230197f, -0.316034f, 0 }, + { 9.175772f, -2.531867f, 0.506373f, 0 }, + { 9.725241f, -2.759315f, 1.114500f, 0 }, + { 10.110707f, -2.782060f, 0.573411f, 0 }, + { 9.934733f, -2.370258f, 0.377087f, 0 }, + { 9.617501f, -2.214635f, -0.361524f, 0 }, + { 9.494201f, -2.189496f, -1.580172f, 0 }, + { 9.704890f, -2.115276f, -2.446872f, 0 }, + { 9.459484f, -2.057815f, -2.561794f, 0 }, + { 9.435542f, -2.030282f, -2.092531f, 0 }, + { 9.346957f, -1.996763f, -1.692699f, 0 }, + { 9.319424f, -2.132035f, -1.470039f, 0 }, + { 9.446317f, -2.430113f, -1.489192f, 0 }, + { 9.703692f, -2.687490f, -1.851914f, 0 }, + { 9.847345f, -2.719811f, -2.027887f, 0 }, + { 9.732423f, -2.558203f, -2.355893f, 0 }, + { 9.549267f, -2.409762f, -2.292447f, 0 }, + { 9.601939f, -2.473209f, -1.733401f, 0 }, + { 9.971844f, -2.697066f, -1.748963f, 0 }, + { 10.626657f, -3.017889f, -1.353920f, 0 }, + { 11.123453f, -3.641578f, -1.219845f, 0 }, + { 11.133030f, -4.373006f, -1.596931f, 0 }, + { 10.457866f, -4.733334f, -2.841915f, 0 }, + { 9.214079f, -4.768049f, -3.096898f, 0 }, + { 7.812275f, -4.437650f, -1.672349f, 0 }, + { 6.750447f, -4.045001f, 0.490811f, 0 }, + { 6.290761f, -3.907335f, 1.800438f, 0 }, + { 6.235694f, -4.234143f, 1.041477f, 0 }, + { 7.199359f, -4.850649f, -2.310403f, 0 }, + { 8.538915f, -4.039015f, -3.203440f, 0 }, + { 9.186545f, -2.800017f, -4.298786f, 0 }, + { 9.197320f, -2.372652f, -4.565740f, 0 }, + { 9.024938f, -1.969230f, -4.732136f, 0 }, + { 8.607149f, -1.534682f, -4.993104f, 0 }, + { 7.957124f, -1.502361f, -4.132390f, 0 }, + { 7.705733f, -1.678334f, -2.855083f, 0 }, + { 7.752420f, -1.753752f, -1.508346f, 0 }, + { 8.034935f, -1.557427f, -0.313640f, 0 }, + { 7.546519f, -1.106120f, 0.447715f, 0 }, + { 6.752841f, -0.906205f, 1.265335f, 0 }, + { 6.906070f, -1.195903f, 1.750160f, 0 }, + { 7.101197f, -1.496375f, 1.381453f, 0 }, + { 7.223301f, -1.824380f, 0.837970f, 0 }, + { 7.374136f, -2.153583f, 0.274136f, 0 }, + { 7.323858f, -2.404974f, -0.490811f, 0 }, + { 7.491452f, -2.598904f, -1.482010f, 0 }, + { 7.899663f, -2.819170f, -2.953246f, 0 }, + { 8.497016f, -3.117249f, -4.119221f, 0 }, + { 9.168590f, -3.533839f, -6.064509f, 0 }, + { 9.417586f, -3.632001f, -6.847412f, 0 }, + { 9.738409f, -3.272871f, -6.969516f, 0 }, + { 9.919171f, -2.809594f, -6.331462f, 0 }, + { 9.987406f, -2.677913f, -4.316743f, 0 }, + { 9.593559f, -2.616861f, -3.142388f, 0 }, + { 9.325409f, -2.674321f, -3.335121f, 0 }, + { 9.167392f, -2.829944f, -3.014298f, 0 }, + { 9.194925f, -3.105278f, -2.008734f, 0 }, + { 9.613911f, -3.459619f, -2.535458f, 0 }, + { 10.720031f, -4.271253f, -3.035846f, 0 }, + { 11.372450f, -5.182246f, -2.151189f, 0 }, + { 10.842135f, -5.142742f, -0.895431f, 0 }, + { 9.220064f, -4.575316f, 0.703895f, 0 }, + { 7.491452f, -4.206610f, 1.714247f, 0 }, + { 6.665453f, -4.437650f, 2.238577f, 0 }, + { 7.479481f, -4.993104f, 3.179498f, 0 }, + { 8.750801f, -5.791570f, 2.965217f, 0 }, + { 9.563632f, -6.527786f, 1.649604f, 0 }, + { 9.215276f, -6.408076f, 0.693121f, 0 }, + { 8.240837f, -5.831074f, -0.050278f, 0 }, + { 7.832625f, -5.178655f, -0.134075f, 0 }, + { 6.849806f, -4.006694f, 0.402226f, 0 }, + { 6.220132f, -3.184286f, -0.293290f, 0 }, + { 6.138729f, -3.074153f, 0.524330f, 0 }, + { 7.079649f, -3.414129f, -1.236604f, 0 }, + { 7.497437f, -3.640381f, -2.803608f, 0 }, + { 7.586023f, -3.466802f, -3.118446f, 0 }, + { 7.608768f, -3.038240f, -3.612848f, 0 }, + { 7.706930f, -2.804805f, -3.219002f, 0 }, + { 7.848188f, -2.905362f, -3.991132f, 0 }, + { 8.244428f, -3.093307f, -4.150346f, 0 }, + { 8.699326f, -2.829944f, -4.168303f, 0 }, + { 8.613134f, -2.391806f, -3.326741f, 0 }, + { 8.754393f, -2.479194f, -2.382229f, 0 }, + { 9.027331f, -2.700658f, -2.299629f, 0 }, + { 9.117114f, -2.700658f, -2.309206f, 0 }, + { 9.198517f, -2.815579f, -1.631647f, 0 }, + { 9.265554f, -2.861069f, -0.093374f, 0 }, + { 9.057259f, -2.791637f, 0.238223f, 0 }, + { 9.398433f, -2.922121f, 0.565031f, 0 }, + { 9.453499f, -2.892194f, 0.474052f, 0 }, + { 9.267948f, -2.750936f, 0.118513f, 0 }, + { 9.593559f, -2.905362f, 0.064643f, 0 }, + { 9.916777f, -3.290828f, 0.547075f, 0 }, + { 9.968252f, -3.573344f, 0.733822f, 0 }, + { 10.299849f, -4.295195f, -2.195482f, 0 }, + { 10.365689f, -5.293576f, -3.512291f, 0 }, + { 10.035290f, -6.093239f, -3.232170f, 0 }, + { 9.386461f, -5.595245f, -0.808043f, 0 }, + { 7.836217f, -5.037397f, -1.355117f, 0 }, + { 7.586023f, -4.918884f, -0.707486f, 0 }, + { 8.003811f, -5.001484f, -1.582566f, 0 }, + { 8.651442f, -5.248086f, -3.233367f, 0 }, + { 8.804670f, -4.791991f, -2.944866f, 0 }, + { 7.832625f, -3.906137f, -2.813185f, 0 }, + { 6.901282f, -3.084927f, -2.161963f, 0 }, + { 6.792346f, -2.578553f, -1.455674f, 0 }, + { 7.048525f, -2.341528f, -1.499966f, 0 }, + { 7.358574f, -2.551020f, -1.587355f, 0 }, + { 7.480678f, -2.724600f, -2.063801f, 0 }, + { 7.368151f, -2.518698f, -1.176749f, 0 }, + { 7.399275f, -2.738965f, -1.344343f, 0 }, + { 7.823049f, -2.987962f, -1.318007f, 0 }, + { 7.832625f, -2.798820f, -1.460462f, 0 }, + { 7.547716f, -2.303221f, -1.837548f, 0 }, + { 7.366954f, -2.001551f, -2.175131f, 0 }, + { 7.653060f, -2.163160f, -2.703052f, 0 }, + { 7.995431f, -2.481588f, -3.134008f, 0 }, + { 8.619121f, -2.681504f, -3.325544f, 0 }, + { 8.935155f, -2.726994f, -4.122813f, 0 }, + { 9.391250f, -2.748542f, -4.546586f, 0 }, + { 9.763548f, -2.730585f, -4.378992f, 0 }, + { 10.044867f, -2.233789f, -5.177458f, 0 }, + { 10.336959f, -2.200270f, -5.360614f, 0 }, + { 10.339353f, -2.786849f, -4.867409f, 0 }, + { 10.545254f, -3.339909f, -4.352656f, 0 }, + { 10.761930f, -3.875013f, -3.894166f, 0 }, + { 10.625460f, -4.471169f, -3.217805f, 0 }, + { 9.902411f, -4.558557f, -2.613269f, 0 }, + { 8.913607f, -3.739741f, -1.416169f, 0 }, + { 8.100776f, -3.011904f, 1.066616f, 0 }, + { 7.064087f, -3.003524f, 3.325544f, 0 }, + { 6.754038f, -3.834311f, 5.176260f, 0 }, + { 7.175417f, -4.786006f, 7.241258f, 0 }, + { 7.382516f, -5.288788f, 6.618766f, 0 }, + { 8.252808f, -5.669466f, 4.605244f, 0 }, + { 9.193728f, -6.020216f, 2.553414f, 0 }, + { 9.549267f, -5.853819f, 0.247800f, 0 }, + { 8.914804f, -5.385753f, -0.512359f, 0 }, + { 8.572433f, -4.914096f, -1.824380f, 0 }, + { 8.161828f, -3.992329f, -3.460816f, 0 }, + { 7.699748f, -2.631226f, -3.369837f, 0 }, + { 7.472299f, -2.184708f, -1.789665f, 0 }, + { 7.617147f, -2.147598f, -1.602917f, 0 }, + { 7.779953f, -1.984792f, -1.983595f, 0 }, + { 8.039723f, -1.725021f, -2.574962f, 0 }, + { 8.286326f, -1.487995f, -2.779666f, 0 }, + { 8.273158f, -1.437717f, -2.838324f, 0 }, + { 8.219289f, -1.659181f, -2.960428f, 0 }, + { 8.444344f, -1.786073f, -2.853886f, 0 }, + { 8.597572f, -1.544259f, -2.703052f, 0 }, + { 8.681370f, -1.361103f, -2.530669f, 0 }, + { 8.962687f, -1.437717f, -2.333148f, 0 }, + { 9.131479f, -1.589749f, -1.939302f, 0 }, + { 9.050076f, -1.765723f, -1.616085f, 0 }, + { 9.041697f, -1.929725f, -1.650801f, 0 }, + { 9.260766f, -2.108093f, -1.804030f, 0 }, + { 9.653415f, -2.413354f, -2.396594f, 0 }, + { 9.742000f, -2.288855f, -1.392227f, 0 }, + { 9.372096f, -1.877053f, -0.934935f, 0 }, + { 9.860513f, -2.138021f, -1.429337f, 0 }, + { 10.694892f, -2.595313f, -1.260546f, 0 }, + { 11.317384f, -2.925713f, -0.727837f, 0 }, + { 11.739960f, -3.251324f, -0.887051f, 0 }, + { 11.595111f, -3.508700f, -2.597707f, 0 }, + { 10.346536f, -4.009088f, -4.683055f, 0 }, + { 9.039303f, -4.310757f, -4.425679f, 0 }, + { 8.474271f, -4.114433f, -2.164357f, 0 }, + { 8.452724f, -3.538628f, -0.290895f, 0 }, + { 8.659822f, -3.467999f, 0.682347f, 0 }, + { 8.937549f, -3.530248f, 0.061052f, 0 }, + { 8.566448f, -2.431310f, -0.852335f, 0 }, + { 8.067257f, -1.312022f, -1.903389f, 0 }, + { 8.377306f, -1.103726f, -1.419761f, 0 }, + { 8.070848f, -1.212662f, -2.258928f, 0 }, + { 8.067257f, -1.584960f, -2.608481f, 0 }, + { 7.800304f, -1.910572f, -3.106475f, 0 }, + { 7.347800f, -2.184708f, -3.384202f, 0 }, + { 7.348997f, -2.264913f, -2.862266f, 0 }, + { 7.765588f, -2.091334f, -1.757343f, 0 }, + { 7.970292f, -1.810015f, -1.043871f, 0 }, + { 8.240837f, -1.757343f, -0.768538f, 0 }, + { 8.485045f, -1.801636f, -0.395043f, 0 }, + { 8.564054f, -1.716641f, -0.083797f, 0 }, + { 8.844175f, -1.758540f, -0.086191f, 0 }, + { 9.075215f, -1.959653f, -0.597353f, 0 }, + { 9.182955f, -2.019508f, -1.362300f, 0 }, + { 9.318227f, -2.041055f, -1.719036f, 0 }, + { 9.363716f, -2.062603f, -2.341528f, 0 }, + { 9.173378f, -1.891418f, -2.298432f, 0 }, + { 9.066835f, -1.715444f, -2.759315f, 0 }, + { 9.272737f, -1.723824f, -2.409762f, 0 }, + { 9.367308f, -1.574187f, -1.908177f, 0 }, + { 9.205699f, -1.302445f, -1.863885f, 0 }, + { 9.190137f, -1.492784f, -1.729810f, 0 }, + { 9.236824f, -1.769314f, -1.782482f, 0 }, + { 9.534902f, -2.070983f, -2.035070f, 0 }, + { 10.097539f, -2.543838f, -1.827972f, 0 }, + { 10.522510f, -2.759315f, -2.231395f, 0 }, + { 10.928327f, -2.730585f, -2.249351f, 0 }, + { 11.123453f, -2.719811f, -1.364694f, 0 }, + { 10.806222f, -2.395397f, -0.016759f, 0 }, + { 9.789884f, -1.911769f, 0.586579f, 0 }, + { 8.809459f, -2.251745f, 0.070629f, 0 }, + { 8.212107f, -3.077744f, 0.161609f, 0 }, + { 8.462300f, -3.548204f, 1.023521f, 0 }, + { 8.960294f, -3.872619f, 1.528697f, 0 }, + { 9.425965f, -4.192245f, 1.470039f, 0 }, + { 9.999376f, -4.453212f, 1.244984f, 0 }, + { 9.986209f, -4.420890f, 0.696712f, 0 }, + { 9.368505f, -4.025847f, 0.286107f, 0 }, + { 8.735239f, -3.618833f, 0.021548f, 0 }, + { 8.062469f, -3.245338f, -0.644040f, 0 }, + { 7.747632f, -2.964020f, -1.055842f, 0 }, + { 7.532154f, -2.788046f, -0.582988f, 0 }, + { 7.694959f, -2.956837f, -0.339976f, 0 }, + { 8.044512f, -3.439268f, -0.831985f, 0 }, + { 8.398854f, -3.869027f, -1.472433f, 0 }, + { 8.674187f, -3.954021f, -1.877053f, 0 }, + { 8.778335f, -3.669111f, -1.696291f, 0 }, + { 8.744816f, -3.325544f, -2.801214f, 0 }, + { 9.170983f, -3.161541f, -2.974794f, 0 }, + { 8.848964f, -2.875434f, -3.779245f, 0 }, + { 8.207318f, -2.503136f, -4.129995f, 0 }, + { 8.026556f, -2.263716f, -4.618412f, 0 }, + { 8.368926f, -2.215832f, -4.732136f, 0 }, + { 8.961491f, -2.413354f, -3.232170f, 0 }, + { 9.333789f, -2.713826f, -1.446097f, 0 }, + { 9.246401f, -2.952049f, -0.226252f, 0 }, + { 8.790305f, -2.959231f, 0.460884f, 0 }, + { 8.155843f, -2.730585f, 0.590170f, 0 }, + { 7.708127f, -2.560597f, 0.263362f, 0 }, + { 7.612359f, -2.658759f, 0.471657f, 0 }, + { 8.567645f, -3.356668f, 0.718260f, 0 }, + { 10.579970f, -4.683055f, 1.223436f, 0 }, + { 12.627011f, -5.783190f, 2.347513f, 0 }, + { 11.851291f, -5.154713f, 2.021902f, 0 }, + { 8.839387f, -3.144782f, -3.478773f, 0 }, + { 8.154645f, -3.208228f, -8.307875f, 0 }, + { 9.410403f, -4.708194f, -0.691924f, 0 }, + { 9.804249f, -4.711786f, 1.703473f, 0 }, + { 9.985011f, -4.288013f, -2.111685f, 0 }, + { 9.917974f, -3.863042f, -0.809240f, 0 }, + { 9.002192f, -3.196257f, -0.214281f, 0 }, + { 8.477862f, -2.410959f, -0.794874f, 0 }, + { 8.450329f, -1.956061f, -0.992396f, 0 }, + { 8.361744f, -1.842337f, -1.545456f, 0 }, + { 8.178588f, -1.766920f, -1.849520f, 0 }, + { 8.061272f, -1.640027f, -2.190693f, 0 }, + { 7.553701f, -1.369482f, -2.219424f, 0 }, + { 7.180206f, -1.359906f, -2.621649f, 0 }, + { 7.414838f, -1.776496f, -3.306390f, 0 }, + { 7.927197f, -1.954864f, -3.851071f, 0 }, + { 8.195347f, -1.989580f, -4.341882f, 0 }, + { 8.341393f, -2.115276f, -4.428073f, 0 }, + { 8.359349f, -2.343922f, -4.118024f, 0 }, + { 8.401248f, -2.454055f, -3.053802f, 0 }, + { 8.487439f, -2.311600f, -2.007537f, 0 }, + { 8.573630f, -2.114079f, -1.933317f, 0 }, + { 8.593981f, -2.120064f, -2.171540f, 0 }, + { 8.409628f, -2.209847f, -2.895785f, 0 }, + { 8.107959f, -2.146400f, -2.240971f, 0 }, + { 8.183376f, -1.910572f, -1.847125f, 0 }, + { 8.455117f, -1.956061f, -1.793256f, 0 }, + { 8.859737f, -2.144006f, -2.002748f, 0 }, + { 9.208094f, -2.382229f, -2.218226f, 0 }, + { 9.277525f, -2.410959f, -2.454055f, 0 }, + { 9.018951f, -2.202664f, -2.607284f, 0 }, + { 8.807065f, -1.917754f, -3.163935f, 0 }, + { 8.732844f, -1.766920f, -3.756500f, 0 }, + { 8.488636f, -1.750160f, -3.998314f, 0 }, + { 8.299495f, -1.744175f, -3.921700f, 0 }, + { 8.184573f, -1.738189f, -3.780442f, 0 }, + { 8.080425f, -1.723824f, -3.687068f, 0 }, + { 7.970292f, -1.810015f, -3.618833f, 0 }, + { 7.970292f, -1.811212f, -3.657140f, 0 }, + { 7.902057f, -1.886630f, -3.809172f, 0 }, + { 8.113944f, -2.105699f, -4.045001f, 0 }, + { 8.355759f, -2.325965f, -3.809172f, 0 }, + { 8.410825f, -2.215832f, -3.554190f, 0 }, + { 8.657428f, -2.017113f, -3.271674f, 0 }, + { 8.823824f, -2.086545f, -2.360681f, 0 }, + { 8.422796f, -2.122458f, -1.601720f, 0 }, + { 8.717282f, -1.810015f, -1.653195f, 0 }, + { 9.615108f, -1.516726f, -1.790862f, 0 }, + { 9.629473f, -1.593340f, -3.891772f, 0 }, + { 10.530889f, -2.082954f, -6.175839f, 0 }, + { 10.994166f, -2.302023f, -4.498702f, 0 }, + { 9.297876f, -1.614888f, -3.004721f, 0 }, + { 7.264003f, -0.905008f, -0.735019f, 0 }, + { 7.615951f, -1.219845f, 0.140061f, 0 }, + { 8.942337f, -1.484404f, -0.383072f, 0 }, + { 10.296257f, -2.246957f, -0.167594f, 0 }, + { 11.376041f, -2.970005f, 0.173579f, 0 }, + { 10.957057f, -2.890997f, -0.011971f, 0 }, + { 10.125072f, -2.902968f, -0.169988f, 0 }, + { 9.543282f, -2.770089f, -0.092177f, 0 }, + { 9.082398f, -2.452858f, 0.432153f, 0 }, + { 8.699326f, -1.927331f, 0.356736f, 0 }, + { 8.416810f, -1.535879f, 0.282516f, 0 }, + { 7.886495f, -0.933738f, -0.872686f, 0 }, + { 8.098382f, -0.636857f, 1.728612f, 0 }, + { 8.451527f, -0.509965f, 1.399410f, 0 }, + { 9.103946f, -0.675164f, 0.752976f, 0 }, + { 9.591166f, -0.895431f, 0.257377f, 0 }, + { 9.684539f, -0.997184f, -0.475249f, 0 }, + { 9.461879f, -0.949300f, -0.150835f, 0 }, + { 9.260766f, -0.992396f, -0.387860f, 0 }, + { 9.248795f, -1.278503f, -0.785298f, 0 }, + { 9.558844f, -1.503558f, -0.909796f, 0 }, + { 10.126269f, -1.493981f, -0.755370f, 0 }, + { 10.194504f, -1.428140f, -0.456095f, 0 }, + { 10.286680f, -1.380256f, -0.415394f, 0 }, + { 10.317805f, -1.411381f, -0.383072f, 0 }, + { 10.150211f, -1.398213f, -0.389058f, 0 }, + { 9.968252f, -1.315613f, -0.265756f, 0 }, + { 9.878469f, -1.361103f, -0.398634f, 0 }, + { 9.900018f, -1.498769f, -0.544681f, 0 }, + { 9.877273f, -1.466448f, -1.072602f, 0 }, + { 9.799460f, -1.371877f, -1.558624f, 0 }, + { 9.544478f, -1.285685f, -1.635239f, 0 }, + { 9.278723f, -1.120486f, -1.229422f, 0 }, + { 9.204502f, -1.103726f, -0.731428f, 0 }, + { 9.202108f, -1.182735f, -0.477643f, 0 }, + { 9.107537f, -1.255758f, 0.050278f, 0 }, + { 8.898045f, -1.216254f, 0.428562f, 0 }, + { 8.766363f, -1.130062f, 0.016759f, 0 }, + { 8.706509f, -1.060631f, -0.681150f, 0 }, + { 8.720874f, -1.039083f, -1.149216f, 0 }, + { 9.220064f, -1.296459f, -1.238999f, 0 }, + { 10.467443f, -1.696291f, -0.963666f, 0 }, + { 11.536453f, -1.877053f, -1.309627f, 0 }, + { 11.785450f, -1.964441f, -2.002748f, 0 }, + { 11.763902f, -2.772484f, -3.430889f, 0 }, + { 11.314989f, -3.549402f, -5.012258f, 0 }, + { 9.746788f, -3.913320f, -4.704603f, 0 }, + { 8.693340f, -4.775232f, -3.177104f, 0 }, + { 8.215697f, -5.501872f, -1.019929f, 0 }, + { 7.824246f, -5.450397f, 0.652420f, 0 }, + { 7.545321f, -4.419693f, 0.913387f, 0 }, + { 7.720098f, -3.350683f, -0.903811f, 0 }, + { 7.936773f, -2.221818f, -3.144782f, 0 }, + { 8.151054f, -1.693897f, -4.214989f, 0 }, + { 7.918817f, -1.904586f, -3.973175f, 0 }, + { 7.843400f, -2.130838f, -3.676294f, 0 }, + { 7.507014f, -2.142809f, -2.937684f, 0 }, + { 7.426809f, -2.203861f, -2.422930f, 0 }, + { 7.520183f, -2.273293f, -2.515107f, 0 }, + { 7.607571f, -2.073377f, -2.264913f, 0 }, + { 7.933182f, -1.736992f, -2.202664f, 0 }, + { 8.366532f, -1.519120f, -2.388215f, 0 }, + { 8.694537f, -1.306036f, -2.293644f, 0 }, + { 8.757984f, -1.061828f, -1.953667f, 0 }, + { 8.790305f, -1.007958f, -1.453279f, 0 }, + { 8.921987f, -1.209071f, -0.818816f, 0 }, + { 8.914804f, -1.312022f, -0.050278f, 0 }, + { 8.711297f, -1.246181f, 0.578199f, 0 }, + { 8.656230f, -1.249772f, 0.275333f, 0 }, + { 8.939943f, -1.387439f, -0.482431f, 0 }, + { 9.241612f, -1.586158f, -0.899022f, 0 }, + { 9.497791f, -1.592143f, -1.055842f, 0 }, + { 9.671371f, -1.361103f, -1.174355f, 0 }, + { 9.715664f, -1.000776f, -1.108515f, 0 }, + { 9.829389f, -0.665588f, -1.197100f, 0 }, + { 9.860513f, -0.462081f, -1.599326f, 0 }, + { 9.821009f, -0.490811f, -2.014719f, 0 }, + { 9.856922f, -0.694318f, -2.319980f, 0 }, + { 10.049655f, -1.024718f, -2.524684f, 0 }, + { 10.514130f, -1.493981f, -1.921346f, 0 }, + { 10.843332f, -1.666363f, -1.532288f, 0 }, + { 11.147395f, -1.837548f, -1.659181f, 0 }, + { 11.727989f, -2.455252f, -1.991974f, 0 }, + { 12.029658f, -3.106475f, -0.149638f, 0 }, + { 10.973816f, -3.138796f, 2.298432f, 0 }, + { 9.229641f, -2.894588f, 2.509122f, 0 }, + { 8.149857f, -2.712629f, 1.924937f, 0 }, + { 7.643484f, -3.005918f, 1.844731f, 0 }, + { 7.934379f, -3.333924f, 1.647210f, 0 }, + { 8.604755f, -3.669111f, 1.010352f, 0 }, + { 9.069230f, -3.952824f, 0.132878f, 0 }, + { 9.255978f, -3.986343f, -0.216675f, 0 }, + { 9.123099f, -3.824735f, 0.580594f, 0 }, + { 8.698129f, -3.511094f, 0.641646f, 0 }, + { 8.346182f, -3.187877f, 1.156399f, 0 }, + { 8.060075f, -2.959231f, 1.389833f, 0 }, + { 7.915226f, -2.890997f, 1.458068f, 0 }, + { 8.005008f, -3.084927f, 1.079784f, 0 }, + { 7.953533f, -3.286040f, -0.043096f, 0 }, + { 8.371321f, -3.442860f, -2.762907f, 0 }, + { 8.309072f, -3.312376f, -4.205412f, 0 }, + { 8.149857f, -2.729388f, -3.705025f, 0 }, + { 7.922408f, -2.109290f, -3.027466f, 0 }, + { 7.881707f, -1.766920f, -3.349486f, 0 }, + { 7.872130f, -1.252167f, -4.329911f, 0 }, + { 8.201332f, -0.677559f, -3.967190f, 0 }, + { 8.599967f, -0.760159f, -3.022678f, 0 }, + { 8.785517f, -1.183932f, -2.488771f, 0 }, + { 9.235627f, -1.813607f, -1.701079f, 0 }, + { 9.714467f, -2.225409f, -0.598550f, 0 }, + { 9.683342f, -2.312797f, 0.444124f, 0 }, + { 9.585180f, -2.341528f, 0.554257f, 0 }, + { 9.459484f, -2.260125f, 0.377087f, 0 }, + { 9.476244f, -2.183511f, 0.265756f, 0 }, + { 9.752774f, -2.238577f, 0.000000f, 0 }, + { 10.631446f, -2.571371f, 0.381875f, 0 }, + { 11.678908f, -2.847901f, 1.048660f, 0 }, + { 11.956635f, -2.754527f, 1.926134f, 0 }, + { 11.179717f, -2.287658f, 1.643618f, 0 }, + { 9.974237f, -1.684320f, -0.531512f, 0 }, + { 9.130282f, -1.295262f, 0.968454f, 0 }, + { 8.774743f, -0.958877f, 1.218648f, 0 }, + { 8.473074f, -0.690727f, 1.455674f, 0 }, + { 8.464694f, -0.987608f, 0.141258f, 0 }, + { 9.175772f, -1.808818f, -3.797201f, 0 }, + { 10.365689f, -2.500742f, -9.164998f, 0 }, + { 10.453077f, -1.736992f, -3.761288f, 0 }, + { 9.622290f, -0.969651f, 0.599747f, 0 }, + { 8.990221f, -0.987608f, -4.253296f, 0 }, + { 9.148238f, -1.395819f, -3.313573f, 0 }, + { 8.651442f, -1.607705f, -1.174355f, 0 }, + { 7.994234f, -1.643618f, -0.547075f, 0 }, + { 7.620739f, -1.555033f, -0.290895f, 0 }, + { 7.387304f, -1.526303f, -0.118513f, 0 }, + { 7.176615f, -1.487995f, -0.105345f, 0 }, + { 7.222105f, -1.329978f, -0.065841f, 0 }, + { 7.553701f, -1.047463f, -0.521936f, 0 }, + { 7.945153f, -0.768538f, -0.612915f, 0 }, + { 8.386883f, -0.518344f, -0.260968f, 0 }, + { 8.783123f, -0.316034f, -0.155623f, 0 }, + { 9.229641f, -0.201113f, -0.294487f, 0 }, + { 9.470259f, -0.234632f, -0.818816f, 0 }, + { 9.665385f, -0.349553f, -0.980425f, 0 }, + { 9.798264f, -0.347159f, -0.960074f, 0 }, + { 9.586377f, -0.480037f, -1.021126f, 0 }, + { 9.587574f, -0.565031f, -0.806845f, 0 }, + { 9.617501f, -0.590170f, -0.330400f, 0 }, + { 9.609122f, -0.484826f, 0.050278f, 0 }, + { 9.691722f, -0.368707f, 0.562637f, 0 }, + { 9.884455f, -0.318429f, 1.296459f, 0 }, + { 9.916777f, -0.286107f, 1.254561f, 0 }, + { 10.086765f, -0.414197f, 0.605733f, 0 }, + { 10.672147f, -0.663193f, -0.056264f, 0 }, + { 11.547227f, -0.732625f, -1.089361f, 0 }, + { 12.741933f, -0.981622f, -1.647210f, 0 }, + { 13.311752f, -1.082178f, -2.098516f, 0 }, + { 12.233165f, -1.091755f, -1.170764f, 0 }, + { 9.745591f, -1.782482f, -1.260546f, 0 }, + { 6.040567f, -2.230197f, -1.437717f, 0 }, + { 5.289985f, -2.487574f, 0.503979f, 0 }, + { 6.959939f, -3.001130f, 3.216608f, 0 }, + { 8.799882f, -4.107250f, 4.249705f, 0 }, + { 9.941916f, -4.839875f, 4.045001f, 0 }, + { 9.454696f, -5.104434f, 3.131614f, 0 }, + { 8.892059f, -5.509054f, 1.795650f, 0 }, + { 7.688973f, -5.981909f, 0.606930f, 0 }, + { 7.673411f, -6.725308f, 0.831985f, 0 }, + { 8.412022f, -7.346603f, 0.257377f, 0 }, + { 8.220486f, -6.330265f, -0.105345f, 0 }, + { 7.586023f, -4.578907f, 0.073023f, 0 }, + { 7.775165f, -3.556584f, -1.447294f, 0 }, + { 8.498213f, -3.017889f, -4.783612f, 0 }, + { 8.949520f, -2.546232f, -4.119221f, 0 }, + { 8.564054f, -2.585736f, -1.102529f, 0 }, + { 7.644681f, -3.087321f, -0.313640f, 0 }, + { 8.555674f, -2.998736f, -0.015562f, 0 }, + { 9.572012f, -2.636014f, -0.071826f, 0 }, + { 8.997404f, -2.252942f, 1.218648f, 0 }, + { 7.629118f, -1.496375f, 0.980425f, 0 }, + { 7.766785f, -1.379059f, 1.416169f, 0 }, + { 8.343787f, -1.787270f, 1.284488f, 0 }, + { 8.748407f, -1.811212f, 0.870292f, 0 }, + { 9.136268f, -2.027887f, 1.131260f, 0 }, + { 9.615108f, -2.226606f, 1.380256f, 0 }, + { 10.127466f, -2.141612f, 0.444124f, 0 }, + { 10.301045f, -1.841140f, -0.062249f, 0 }, + { 10.163380f, -1.441308f, -2.595313f, 0 }, + { 9.898820f, -1.045068f, 1.595734f, 0 }, + { 9.682145f, -1.219845f, 2.372652f, 0 }, + { 10.177745f, -1.084573f, 1.078587f, 0 }, + { 11.180914f, -0.885854f, 0.757764f, 0 }, + { 12.489345f, -1.234210f, 2.330754f, 0 }, + { 13.658912f, -2.050632f, 2.142809f, 0 }, + { 13.063952f, -2.145203f, -0.293290f, 0 }, + { 9.628276f, -1.520317f, -2.880223f, 0 }, + { 6.360192f, -1.479616f, -3.886984f, 0 }, + { 5.079296f, -1.917754f, -2.090137f, 0 }, + { 6.202175f, -3.551796f, -0.855927f, 0 }, + { 7.969095f, -4.886562f, -0.975637f, 0 }, + { 11.101906f, -4.876986f, 0.645237f, 0 }, + { 11.766296f, -4.067746f, 0.531512f, 0 }, + { 10.569196f, -3.503912f, -0.644040f, 0 }, + { 10.237599f, -3.076547f, -0.447715f, 0 }, + { 9.629473f, -2.752133f, -0.193930f, 0 }, + { 8.340196f, -1.911769f, -0.742202f, 0 }, + { 7.272383f, -1.003170f, -1.213859f, 0 }, + { 6.823470f, -0.739808f, -1.057039f, 0 }, + { 7.050919f, -0.673967f, -0.834379f, 0 }, + { 7.595600f, -0.442927f, -0.532710f, 0 }, + { 8.060075f, -0.168791f, -0.527921f, 0 }, + { 8.573630f, 0.094571f, -1.207874f, 0 }, + { 8.899241f, 0.466869f, -1.898601f, 0 }, + { 9.060850f, 0.805648f, -1.408987f, 0 }, + { 9.222459f, 0.831985f, -0.489614f, 0 }, + { 9.290693f, 0.647631f, 0.099359f, 0 }, + { 8.882483f, 0.517147f, -0.029928f, 0 }, + { 8.628697f, 0.389058f, -0.817619f, 0 }, + { 9.248795f, 0.234632f, -1.046265f, 0 }, + { 9.690525f, -0.081403f, -1.126471f, 0 }, + { 10.071202f, -0.231040f, -0.632069f, 0 }, + { 10.299849f, -0.039504f, 0.476446f, 0 }, + { 10.965436f, 0.278924f, 0.920570f, 0 }, + { 11.526876f, 0.132878f, -0.335188f, 0 }, + { 11.572366f, 0.118513f, -0.995987f, 0 }, + { 12.087119f, 0.074220f, 0.064643f, 0 }, + { 14.025224f, -0.268150f, 0.715866f, 0 }, + { 13.812140f, -0.075417f, 2.175131f, 0 }, + { 10.393223f, 0.955286f, 4.447227f, 0 }, + { 5.740095f, 2.165554f, 5.378571f, 0 }, + { 2.682701f, 2.470814f, 4.266465f, 0 }, + { 2.267308f, 1.452082f, 2.970005f, 0 }, + { 5.784388f, -0.737414f, 2.178722f, 0 }, + { 8.700523f, -2.176328f, 0.712274f, 0 }, + { 8.658625f, -2.545035f, -1.139639f, 0 }, + { 8.984236f, -3.094504f, -0.059855f, 0 }, + { 10.274710f, -4.108448f, 2.123656f, 0 }, + { 11.112679f, -5.146333f, 2.748542f, 0 }, + { 12.083528f, -5.299562f, -0.111330f, 0 }, + { 11.859670f, -3.488349f, -2.300826f, 0 }, + { 10.259148f, -1.679531f, -0.063446f, 0 }, + { 8.656230f, -1.307233f, 1.798044f, 0 }, + { 7.996628f, -1.447294f, 1.592143f, 0 }, + { 8.142674f, -1.909375f, 0.881066f, 0 }, + { 8.282735f, -2.118867f, 0.978031f, 0 }, + { 8.382094f, -1.970427f, 1.248575f, 0 }, + { 8.866920f, -1.735795f, 0.386663f, 0 }, + { 9.623487f, -1.595734f, -0.269348f, 0 }, + { 9.806643f, -1.525105f, -0.345962f, 0 }, + { 9.609122f, -1.367088f, 0.299275f, 0 }, + { 9.714467f, -1.388636f, 1.693897f, 0 }, + { 9.576800f, -1.092952f, 2.396594f, 0 }, + { 9.296679f, -1.480813f, 2.565385f, 0 }, + { 9.323015f, -0.742202f, 2.341528f, 0 }, + { 9.384068f, -1.109712f, 1.960850f, 0 }, + { 9.868893f, -1.590946f, 2.421733f, 0 }, + { 10.109509f, -1.939302f, 2.955640f, 0 }, + { 9.973041f, -2.006340f, 3.324347f, 0 }, + { 9.859316f, -1.581369f, 3.942050f, 0 }, + { 9.793475f, -0.999579f, 3.818749f, 0 }, + { 8.820233f, -0.578199f, 2.885011f, 0 }, + { 7.404064f, -0.547075f, 1.671152f, 0 }, + { 6.730096f, -0.906205f, 0.976834f, 0 }, + { 8.153448f, -2.236183f, 0.503979f, 0 }, + { 9.867696f, -4.234143f, -0.254982f, 0 }, + { 7.984657f, -2.888602f, -1.261743f, 0 }, + { 9.093172f, -3.695448f, -2.171540f, 0 }, + { 9.166195f, -3.958810f, -1.365891f, 0 }, + { 9.483426f, -4.307166f, -1.432929f, 0 }, + { 9.564829f, -4.777626f, -2.000354f, 0 }, + { 9.548070f, -5.154713f, -2.106896f, 0 }, + { 9.175772f, -5.427651f, -1.608902f, 0 }, + { 8.127112f, -6.010639f, -1.829169f, 0 }, + { 8.129506f, -6.432018f, -1.207874f, 0 }, + { 7.790727f, -5.821497f, 0.189142f, 0 }, + { 7.073664f, -4.104856f, 2.110487f, 0 }, + { 7.091620f, -3.636790f, 1.745372f, 0 }, + { 7.758405f, -3.837903f, 0.458489f, 0 }, + { 8.832204f, -3.739741f, 0.357933f, 0 }, + { 9.786293f, -3.177104f, 0.160411f, 0 }, + { 9.618699f, -2.337936f, -0.683544f, 0 }, + { 9.124296f, -1.669955f, -0.986410f, 0 }, + { 8.815445f, -1.297656f, 0.074220f, 0 }, + { 8.663413f, -1.192312f, 0.752976f, 0 }, + { 8.526943f, -1.224633f, 0.095768f, 0 }, + { 8.671793f, -1.508346f, -0.044293f, 0 }, + { 9.041697f, -1.966835f, -1.302445f, 0 }, + { 9.320621f, -2.434901f, -0.640449f, 0 }, + { 9.319424f, -2.719811f, -0.933738f, 0 }, + { 9.598348f, -2.252942f, 0.096965f, 0 }, + { 9.272737f, -2.086545f, -0.335188f, 0 }, + { 9.397235f, -1.977609f, -0.829590f, 0 }, + { 9.585180f, -1.861491f, -0.963666f, 0 }, + { 9.563632f, -1.543062f, -1.194706f, 0 }, + { 9.265554f, -1.262941f, -1.276109f, 0 }, + { 8.941140f, -0.998381f, -1.148019f, 0 }, + { 8.711297f, -0.948103f, -1.108515f, 0 }, + { 8.803473f, -1.259349f, -1.027112f, 0 }, + { 9.475047f, -2.545035f, -0.591367f, 0 }, + { 10.941494f, -4.028242f, -0.374692f, 0 }, + { 11.295835f, -3.961204f, 0.489614f, 0 }, + { 9.697707f, -2.606087f, 1.587355f, 0 }, + { 8.414416f, -2.354696f, 1.309627f, 0 }, + { 8.408431f, -3.039437f, 0.598550f, 0 }, + { 8.759181f, -3.227382f, 0.460884f, 0 }, + { 9.191334f, -3.215411f, 0.717063f, 0 }, + { 9.106340f, -3.286040f, -1.228225f, 0 }, + { 9.215276f, -3.016692f, -0.532710f, 0 }, + { 9.226050f, -2.573765f, 1.215057f, 0 }, + { 9.278723f, -2.743753f, 0.444124f, 0 }, + { 9.779110f, -3.204637f, 1.349132f, 0 }, + { 9.914383f, -3.223790f, 1.940499f, 0 }, + { 9.907200f, -2.806002f, 1.668757f, 0 }, + { 10.375266f, -2.416945f, 2.098516f, 0 }, + { 11.027685f, -2.161963f, 2.414551f, 0 }, + { 11.603491f, -1.948879f, 2.486377f, 0 }, + { 11.531665f, -1.472433f, 2.813185f, 0 }, + { 10.983393f, -0.723048f, 2.525881f, 0 }, + { 9.938325f, 0.086191f, 2.130838f, 0 }, + { 8.816642f, 0.365116f, 2.731782f, 0 }, + { 10.491385f, 0.019154f, 3.318361f, 0 }, + { 10.913961f, -0.289698f, 4.115630f, 0 }, + { 9.964661f, 0.154426f, 4.765655f, 0 }, + { 7.896072f, 1.101332f, 4.291604f, 0 }, + { 7.783545f, 1.666363f, 4.158726f, 0 }, + { 8.256399f, 1.159990f, 4.963177f, 0 }, + { 8.441950f, 0.727837f, 5.633553f, 0 }, + { 7.973883f, 0.981622f, 5.418075f, 0 }, + { 7.131125f, 1.492784f, 4.759670f, 0 }, + { 7.067678f, 1.640027f, 4.987119f, 0 }, + { 7.246047f, 1.323993f, 5.380965f, 0 }, + { 7.788333f, 1.154004f, 5.783190f, 0 }, + { 8.256399f, 1.544259f, 6.980290f, 0 }, + { 8.076834f, 2.169145f, 7.654258f, 0 }, + { 7.649469f, 2.182313f, 7.368151f, 0 }, + { 7.462722f, 2.094925f, 6.817485f, 0 }, + { 6.956348f, 1.817198f, 6.009442f, 0 }, + { 6.156685f, 1.295262f, 5.595245f, 0 }, + { 5.171472f, 1.101332f, 5.043383f, 0 }, + { 4.614820f, 1.007958f, 4.921278f, 0 }, + { 4.693829f, 0.915781f, 5.402513f, 0 }, + { 4.863817f, 1.090558f, 5.463564f, 0 }, + { 4.620806f, 1.468842f, 5.919660f, 0 }, + { 4.741713f, 1.361103f, 6.609190f, 0 }, + { 4.047395f, 1.677137f, 6.482296f, 0 }, + { 4.094082f, 1.859096f, 6.527786f, 0 }, + { 4.349064f, 1.829169f, 6.309914f, 0 }, + { 4.477154f, 1.816001f, 6.591233f, 0 }, + { 4.513067f, 1.195903f, 7.651864f, 0 }, + { 5.130771f, 0.706289f, 8.787911f, 0 }, + { 5.143939f, 0.804451f, 8.456315f, 0 }, + { 4.619609f, 0.244208f, 7.931985f, 0 }, + { 3.963598f, -0.852335f, 8.146266f, 0 }, + { 4.163514f, -1.314416f, 8.972264f, 0 }, + { 4.601653f, -1.395819f, 9.185349f, 0 }, + { 4.854240f, -1.686714f, 8.943534f, 0 }, + { 4.542994f, -2.023099f, 8.414416f, 0 }, + { 3.835509f, -2.602495f, 8.085214f, 0 }, + { 2.978385f, -2.853886f, 8.039723f, 0 }, + { 2.686292f, -2.522290f, 7.716507f, 0 }, + { 2.425325f, -2.989159f, 10.263936f, 0 }, + { 1.680728f, -3.276463f, 12.568354f, 0 }, + { 1.449688f, -2.462435f, 9.834177f, 0 }, + { 1.904586f, -2.296038f, 8.819036f, 0 }, + { 2.072180f, -2.254139f, 9.337380f, 0 }, + { 2.197876f, -2.144006f, 9.494201f, 0 }, + { 2.105699f, -1.899798f, 9.169786f, 0 }, + { 1.717839f, -1.751357f, 9.096764f, 0 }, + { 1.574187f, -1.813607f, 9.458287f, 0 }, + { 1.502361f, -1.717839f, 9.576800f, 0 }, + { 1.379059f, -1.528697f, 9.473849f, 0 }, + { 1.168370f, -1.182735f, 9.206897f, 0 }, + { 1.060631f, -1.138442f, 9.701299f, 0 }, + { 0.893037f, -1.142033f, 10.007756f, 0 }, + { 0.729034f, -1.097741f, 10.362098f, 0 }, + { 0.847547f, -1.270123f, 11.415545f, 0 }, + { 0.700303f, -1.437717f, 11.802209f, 0 }, + { 0.657208f, -0.940921f, 10.297455f, 0 }, + { 0.820014f, -0.262165f, 8.865723f, 0 }, + { 1.120486f, -0.100556f, 9.303862f, 0 }, + { 1.000776f, -0.172382f, 10.194504f, 0 }, + { 0.691924f, 0.026336f, 8.984236f, 0 }, + { 0.712274f, 0.058658f, 8.265976f, 0 }, + { 0.530315f, -0.462081f, 10.773900f, 0 }, + { 0.463278f, -0.685938f, 10.289075f, 0 }, + { 0.442927f, -0.518344f, 7.893678f, 0 }, + { 0.445321f, -0.438139f, 7.972686f, 0 }, + { 0.378284f, -0.450110f, 8.655033f, 0 }, + { 0.043096f, 0.015562f, 8.980644f, 0 }, + { 0.220266f, 0.984016f, 9.639050f, 0 }, + { 0.154426f, 1.146822f, 9.488214f, 0 }, + { -0.119710f, 1.325190f, 9.168590f, 0 }, + { -0.130484f, 1.334767f, 9.746788f, 0 }, + { -0.025139f, 1.310825f, 10.338156f, 0 }, + { 0.028730f, 1.616085f, 9.712072f, 0 }, + { 0.044293f, 1.892615f, 8.583207f, 0 }, + { 0.069432f, 1.480813f, 8.564054f, 0 }, + { 0.033519f, 1.243787f, 8.768758f, 0 }, + { 0.373495f, 1.514332f, 8.633486f, 0 }, + { 0.353144f, 1.561018f, 8.446738f, 0 }, + { 0.129287f, 1.313219f, 8.616726f, 0 }, + { -0.028730f, 0.976834f, 9.123099f, 0 }, + { -0.076614f, 0.966060f, 9.351746f, 0 }, + { -0.161609f, 1.165975f, 8.965082f, 0 }, + { -0.343568f, 1.641224f, 8.194150f, 0 }, + { -0.442927f, 1.661575f, 8.437161f, 0 }, + { -0.363918f, 1.365891f, 9.854527f, 0 }, + { -0.282516f, 1.326387f, 10.666162f, 0 }, + { -0.314837f, 1.443703f, 10.433924f, 0 }, + { -0.644040f, 1.332372f, 9.327804f, 0 }, + { -0.999579f, 1.479616f, 8.036133f, 0 }, + { -0.799663f, 1.452082f, 8.346182f, 0 }, + { -0.858321f, 1.567004f, 9.868893f, 0 }, + { -0.938526f, 1.495178f, 11.599899f, 0 }, + { -1.193509f, 1.498769f, 11.905160f, 0 }, + { -1.556230f, 1.338358f, 10.947480f, 0 }, + { -1.557427f, 1.256955f, 11.003743f, 0 }, + { -1.413775f, 1.060631f, 11.848896f, 0 }, + { -1.280897f, 0.922964f, 12.215209f, 0 }, + { -1.132457f, 0.927753f, 11.399983f, 0 }, + { -1.037886f, 0.881066f, 10.413573f, 0 }, + { -0.605733f, 0.897825f, 10.074794f, 0 }, + { -0.149638f, 0.872686f, 10.181335f, 0 }, + { 0.278924f, 0.933738f, 10.765521f, 0 }, + { 0.741005f, 1.137245f, 10.898398f, 0 }, + { 1.114500f, 1.398213f, 10.672147f, 0 }, + { 1.337161f, 1.841140f, 11.609476f, 0 }, + { 1.916557f, 1.922543f, 13.679262f, 0 }, + { 2.594116f, 1.768117f, 13.814534f, 0 }, + { 3.088518f, 2.280476f, 12.144580f, 0 }, + { 3.426100f, 2.173934f, 11.726792f, 0 }, + { 3.564964f, 1.717839f, 11.662148f, 0 }, + { 3.779245f, 1.653195f, 11.219221f, 0 }, + { 3.823538f, 1.709459f, 10.377660f, 0 }, }; const size_t kBodyDetectOnBodyTestDataLength = ARRAY_SIZE(kBodyDetectOnBodyTestData); const struct body_detect_test_data kBodyDetectOffOnTestData[] = { - {-0.269348, 0.220266, 10.030501, 0}, - {-0.259771, 0.216675, 10.113101, 0}, - {-0.253785, 0.213084, 10.096342, 0}, - {-0.262165, 0.201113, 10.098736, 0}, - {-0.257377, 0.210690, 10.093947, 0}, - {-0.253785, 0.202310, 10.096342, 0}, - {-0.257377, 0.213084, 10.113101, 0}, - {-0.257377, 0.221464, 10.096342, 0}, - {-0.262165, 0.217872, 10.115496, 0}, - {-0.258574, 0.219069, 10.102327, 0}, - {-0.275333, 0.205901, 10.123875, 0}, - {-0.262165, 0.209493, 10.085567, 0}, - {-0.271742, 0.209493, 10.110707, 0}, - {-0.275333, 0.220266, 10.096342, 0}, - {-0.251391, 0.210690, 10.097539, 0}, - {-0.262165, 0.210690, 10.090356, 0}, - {-0.268150, 0.208295, 10.108313, 0}, - {-0.258574, 0.210690, 10.098736, 0}, - {-0.270545, 0.219069, 10.097539, 0}, - {-0.263362, 0.211887, 10.102327, 0}, - {-0.264559, 0.211887, 10.097539, 0}, - {-0.262165, 0.204704, 10.090356, 0}, - {-0.246603, 0.203507, 10.089159, 0}, - {-0.250194, 0.215478, 10.099933, 0}, - {-0.270545, 0.225055, 10.109509, 0}, - {-0.256179, 0.213084, 10.097539, 0}, - {-0.248997, 0.207098, 10.086765, 0}, - {-0.248997, 0.210690, 10.087962, 0}, - {-0.256179, 0.201113, 10.089159, 0}, - {-0.258574, 0.203507, 10.104721, 0}, - {-0.262165, 0.208295, 10.093947, 0}, - {-0.246603, 0.204704, 10.086765, 0}, - {-0.247800, 0.208295, 10.108313, 0}, - {-0.252588, 0.220266, 10.099933, 0}, - {-0.264559, 0.210690, 10.098736, 0}, - {-0.266953, 0.185551, 10.084371, 0}, - {-0.253785, 0.213084, 10.109509, 0}, - {-0.256179, 0.231040, 10.099933, 0}, - {-0.252588, 0.205901, 10.091554, 0}, - {-0.259771, 0.207098, 10.095144, 0}, - {-0.260968, 0.203507, 10.096342, 0}, - {-0.253785, 0.205901, 10.095144, 0}, - {-0.256179, 0.217872, 10.093947, 0}, - {-0.265756, 0.209493, 10.083174, 0}, - {-0.263362, 0.204704, 10.103524, 0}, - {-0.253785, 0.198719, 10.095144, 0}, - {-0.252588, 0.209493, 10.103524, 0}, - {-0.260968, 0.205901, 10.098736, 0}, - {-0.259771, 0.205901, 10.083174, 0}, - {-0.266953, 0.216675, 10.090356, 0}, - {-0.265756, 0.207098, 10.101130, 0}, - {-0.262165, 0.204704, 10.111904, 0}, - {-0.248997, 0.199916, 10.101130, 0}, - {-0.263362, 0.207098, 10.096342, 0}, - {-0.281319, 0.227449, 10.108313, 0}, - {-0.259771, 0.219069, 10.087962, 0}, - {-0.258574, 0.214281, 10.079582, 0}, - {-0.268150, 0.204704, 10.108313, 0}, - {-0.277727, 0.204704, 10.114298, 0}, - {-0.257377, 0.208295, 10.115496, 0}, - {-0.260968, 0.222661, 10.104721, 0}, - {-0.265756, 0.213084, 10.102327, 0}, - {-0.256179, 0.210690, 10.099933, 0}, - {-0.253785, 0.203507, 10.109509, 0}, - {-0.270545, 0.201113, 10.103524, 0}, - {-0.259771, 0.209493, 10.115496, 0}, - {-0.264559, 0.207098, 10.103524, 0}, - {-0.263362, 0.202310, 10.105919, 0}, - {-0.260968, 0.220266, 10.110707, 0}, - {-0.257377, 0.216675, 10.110707, 0}, - {-0.259771, 0.195127, 10.093947, 0}, - {-0.271742, 0.209493, 10.104721, 0}, - {-0.257377, 0.223858, 10.108313, 0}, - {-0.265756, 0.205901, 10.101130, 0}, - {-0.270545, 0.196324, 10.101130, 0}, - {-0.254982, 0.202310, 10.115496, 0}, - {-0.248997, 0.214281, 10.116693, 0}, - {-0.268150, 0.207098, 10.111904, 0}, - {-0.263362, 0.204704, 10.091554, 0}, - {-0.270545, 0.210690, 10.091554, 0}, - {-0.268150, 0.215478, 10.102327, 0}, - {-0.264559, 0.223858, 10.096342, 0}, - {-0.262165, 0.203507, 10.099933, 0}, - {-0.259771, 0.203507, 10.103524, 0}, - {-0.269348, 0.204704, 10.119086, 0}, - {-0.265756, 0.202310, 10.091554, 0}, - {-0.260968, 0.201113, 10.092751, 0}, - {-0.260968, 0.210690, 10.092751, 0}, - {-0.266953, 0.205901, 10.109509, 0}, - {-0.269348, 0.203507, 10.105919, 0}, - {-0.264559, 0.193930, 10.114298, 0}, - {-0.263362, 0.216675, 10.093947, 0}, - {-0.256179, 0.208295, 10.095144, 0}, - {-0.271742, 0.203507, 10.103524, 0}, - {-0.259771, 0.208295, 10.089159, 0}, - {-0.257377, 0.220266, 10.108313, 0}, - {-0.266953, 0.207098, 10.101130, 0}, - {-0.268150, 0.198719, 10.117889, 0}, - {-0.258574, 0.204704, 10.091554, 0}, - {-0.266953, 0.201113, 10.104721, 0}, - {-0.265756, 0.205901, 10.091554, 0}, - {-0.277727, 0.203507, 10.102327, 0}, - {-0.266953, 0.204704, 10.093947, 0}, - {-0.265756, 0.215478, 10.107116, 0}, - {-0.254982, 0.215478, 10.110707, 0}, - {-0.269348, 0.217872, 10.095144, 0}, - {-0.265756, 0.229843, 10.109509, 0}, - {-0.260968, 0.226252, 10.098736, 0}, - {-0.253785, 0.208295, 10.095144, 0}, - {-0.253785, 0.211887, 10.085567, 0}, - {-0.268150, 0.214281, 10.109509, 0}, - {-0.258574, 0.201113, 10.107116, 0}, - {-0.265756, 0.211887, 10.103524, 0}, - {-0.256179, 0.215478, 10.093947, 0}, - {-0.263362, 0.204704, 10.107116, 0}, - {-0.260968, 0.214281, 10.098736, 0}, - {-0.259771, 0.213084, 10.110707, 0}, - {-0.276530, 0.215478, 10.095144, 0}, - {-0.263362, 0.211887, 10.084371, 0}, - {-0.245406, 0.217872, 10.110707, 0}, - {-0.251391, 0.209493, 10.105919, 0}, - {-0.269348, 0.205901, 10.093947, 0}, - {-0.271742, 0.201113, 10.099933, 0}, - {-0.270545, 0.228646, 10.099933, 0}, - {-0.262165, 0.217872, 10.096342, 0}, - {-0.259771, 0.209493, 10.099933, 0}, - {-0.260968, 0.210690, 10.105919, 0}, - {-0.252588, 0.203507, 10.099933, 0}, - {-0.263362, 0.197522, 10.095144, 0}, - {-0.271742, 0.213084, 10.101130, 0}, - {-0.268150, 0.196324, 10.110707, 0}, - {-0.248997, 0.213084, 10.108313, 0}, - {-0.254982, 0.215478, 10.095144, 0}, - {-0.260968, 0.208295, 10.107116, 0}, - {-0.259771, 0.219069, 10.108313, 0}, - {-0.266953, 0.214281, 10.098736, 0}, - {-0.269348, 0.202310, 10.090356, 0}, - {-0.258574, 0.204704, 10.113101, 0}, - {-0.263362, 0.226252, 10.086765, 0}, - {-0.264559, 0.204704, 10.096342, 0}, - {-0.271742, 0.219069, 10.096342, 0}, - {-0.252588, 0.210690, 10.104721, 0}, - {-0.258574, 0.211887, 10.113101, 0}, - {-0.264559, 0.210690, 10.104721, 0}, - {-0.269348, 0.214281, 10.103524, 0}, - {-0.253785, 0.211887, 10.093947, 0}, - {-0.256179, 0.223858, 10.110707, 0}, - {-0.274136, 0.207098, 10.098736, 0}, - {-0.274136, 0.207098, 10.092751, 0}, - {-0.254982, 0.210690, 10.091554, 0}, - {-0.257377, 0.204704, 10.098736, 0}, - {-0.257377, 0.209493, 10.108313, 0}, - {-0.257377, 0.211887, 10.095144, 0}, - {-0.259771, 0.199916, 10.095144, 0}, - {-0.257377, 0.214281, 10.101130, 0}, - {-0.270545, 0.217872, 10.103524, 0}, - {-0.281319, 0.204704, 10.104721, 0}, - {-0.271742, 0.208295, 10.103524, 0}, - {-0.258574, 0.211887, 10.104721, 0}, - {-0.264559, 0.204704, 10.126269, 0}, - {-0.262165, 0.201113, 10.101130, 0}, - {-0.258574, 0.219069, 10.096342, 0}, - {-0.263362, 0.211887, 10.107116, 0}, - {-0.265756, 0.203507, 10.091554, 0}, - {-0.264559, 0.205901, 10.107116, 0}, - {-0.256179, 0.214281, 10.095144, 0}, - {-0.263362, 0.202310, 10.097539, 0}, - {-0.271742, 0.207098, 10.104721, 0}, - {-0.272939, 0.210690, 10.101130, 0}, - {-0.262165, 0.205901, 10.096342, 0}, - {-0.260968, 0.209493, 10.107116, 0}, - {-0.269348, 0.217872, 10.093947, 0}, - {-0.256179, 0.220266, 10.087962, 0}, - {-0.264559, 0.208295, 10.092751, 0}, - {-0.265756, 0.208295, 10.095144, 0}, - {-0.262165, 0.199916, 10.098736, 0}, - {-0.259771, 0.215478, 10.101130, 0}, - {-0.263362, 0.217872, 10.097539, 0}, - {-0.263362, 0.204704, 10.095144, 0}, - {-0.248997, 0.202310, 10.096342, 0}, - {-0.260968, 0.226252, 10.097539, 0}, - {-0.259771, 0.216675, 10.103524, 0}, - {-0.270545, 0.205901, 10.090356, 0}, - {-0.250194, 0.219069, 10.089159, 0}, - {-0.254982, 0.213084, 10.098736, 0}, - {-0.268150, 0.204704, 10.102327, 0}, - {-0.258574, 0.215478, 10.104721, 0}, - {-0.250194, 0.217872, 10.102327, 0}, - {-0.250194, 0.215478, 10.097539, 0}, - {-0.251391, 0.213084, 10.086765, 0}, - {-0.266953, 0.204704, 10.108313, 0}, - {-0.270545, 0.199916, 10.099933, 0}, - {-0.271742, 0.208295, 10.092751, 0}, - {-0.268150, 0.222661, 10.098736, 0}, - {-0.252588, 0.213084, 10.096342, 0}, - {-0.266953, 0.213084, 10.092751, 0}, - {-0.265756, 0.205901, 10.105919, 0}, - {-0.258574, 0.209493, 10.103524, 0}, - {-0.263362, 0.203507, 10.103524, 0}, - {-0.265756, 0.213084, 10.092751, 0}, - {-0.266953, 0.209493, 10.097539, 0}, - {-0.272939, 0.193930, 10.110707, 0}, - {-0.258574, 0.209493, 10.109509, 0}, - {-0.259771, 0.213084, 10.101130, 0}, - {-0.274136, 0.215478, 10.101130, 0}, - {-0.259771, 0.207098, 10.091554, 0}, - {-0.265756, 0.208295, 10.101130, 0}, - {-0.263362, 0.210690, 10.109509, 0}, - {-0.264559, 0.216675, 10.110707, 0}, - {-0.266953, 0.211887, 10.099933, 0}, - {-0.268150, 0.199916, 10.093947, 0}, - {-0.265756, 0.216675, 10.105919, 0}, - {-0.262165, 0.204704, 10.081977, 0}, - {-0.263362, 0.214281, 10.086765, 0}, - {-0.263362, 0.210690, 10.084371, 0}, - {-0.257377, 0.201113, 10.104721, 0}, - {-0.262165, 0.203507, 10.109509, 0}, - {-0.266953, 0.217872, 10.113101, 0}, - {-0.252588, 0.209493, 10.102327, 0}, - {-0.257377, 0.213084, 10.096342, 0}, - {-0.260968, 0.211887, 10.101130, 0}, - {-0.263362, 0.197522, 10.114298, 0}, - {-0.272939, 0.192733, 10.103524, 0}, - {-0.250194, 0.207098, 10.079582, 0}, - {-0.253785, 0.214281, 10.107116, 0}, - {-0.254982, 0.205901, 10.095144, 0}, - {-0.256179, 0.209493, 10.103524, 0}, - {-0.265756, 0.222661, 10.111904, 0}, - {-0.259771, 0.211887, 10.101130, 0}, - {-0.256179, 0.202310, 10.115496, 0}, - {-0.260968, 0.209493, 10.109509, 0}, - {-0.243011, 0.203507, 10.101130, 0}, - {-0.252588, 0.205901, 10.096342, 0}, - {-0.253785, 0.225055, 10.095144, 0}, - {-0.258574, 0.225055, 10.096342, 0}, - {-0.264559, 0.215478, 10.092751, 0}, - {-0.265756, 0.205901, 10.114298, 0}, - {-0.266953, 0.220266, 10.108313, 0}, - {-0.268150, 0.208295, 10.109509, 0}, - {-0.259771, 0.210690, 10.103524, 0}, - {-0.253785, 0.210690, 10.109509, 0}, - {-0.268150, 0.213084, 10.097539, 0}, - {-0.268150, 0.215478, 10.102327, 0}, - {-0.269348, 0.201113, 10.103524, 0}, - {-0.262165, 0.199916, 10.107116, 0}, - {-0.260968, 0.205901, 10.120284, 0}, - {-0.257377, 0.193930, 10.102327, 0}, - {-0.264559, 0.203507, 10.104721, 0}, - {-0.265756, 0.210690, 10.093947, 0}, - {-0.256179, 0.209493, 10.097539, 0}, - {-0.257377, 0.204704, 10.107116, 0}, - {-0.260968, 0.208295, 10.093947, 0}, - {-0.258574, 0.204704, 10.102327, 0}, - {-0.263362, 0.211887, 10.107116, 0}, - {-0.263362, 0.191536, 10.097539, 0}, - {-0.253785, 0.209493, 10.107116, 0}, - {-0.254982, 0.217872, 10.105919, 0}, - {-0.259771, 0.207098, 10.096342, 0}, - {-0.265756, 0.204704, 10.114298, 0}, - {-0.270545, 0.208295, 10.099933, 0}, - {-0.262165, 0.214281, 10.104721, 0}, - {-0.257377, 0.205901, 10.095144, 0}, - {-0.266953, 0.214281, 10.096342, 0}, - {-0.274136, 0.225055, 10.093947, 0}, - {-0.266953, 0.216675, 10.099933, 0}, - {-0.269348, 0.208295, 10.099933, 0}, - {-0.266953, 0.222661, 10.105919, 0}, - {-0.246603, 0.204704, 10.090356, 0}, - {-0.257377, 0.202310, 10.102327, 0}, - {-0.258574, 0.217872, 10.114298, 0}, - {-0.268150, 0.225055, 10.099933, 0}, - {-0.278924, 0.210690, 10.097539, 0}, - {-0.263362, 0.203507, 10.104721, 0}, - {-0.252588, 0.221464, 10.089159, 0}, - {-0.252588, 0.208295, 10.073597, 0}, - {-0.252588, 0.213084, 10.091554, 0}, - {-0.256179, 0.210690, 10.087962, 0}, - {-0.272939, 0.214281, 10.097539, 0}, - {-0.259771, 0.203507, 10.097539, 0}, - {-0.271742, 0.208295, 10.102327, 0}, - {-0.262165, 0.216675, 10.095144, 0}, - {-0.264559, 0.215478, 10.095144, 0}, - {-0.265756, 0.214281, 10.103524, 0}, - {-0.268150, 0.217872, 10.096342, 0}, - {-0.262165, 0.221464, 10.104721, 0}, - {-0.274136, 0.219069, 10.101130, 0}, - {-0.264559, 0.208295, 10.097539, 0}, - {-0.265756, 0.203507, 10.089159, 0}, - {-0.269348, 0.204704, 10.110707, 0}, - {-0.268150, 0.214281, 10.116693, 0}, - {-0.250194, 0.199916, 10.102327, 0}, - {-0.266953, 0.197522, 10.105919, 0}, - {-0.268150, 0.199916, 10.108313, 0}, - {-0.259771, 0.195127, 10.093947, 0}, - {-0.262165, 0.215478, 10.085567, 0}, - {-0.263362, 0.216675, 10.101130, 0}, - {-0.252588, 0.227449, 10.037683, 0}, - {-0.276530, 0.208295, 10.177745, 0}, - {-0.254982, 0.205901, 10.175350, 0}, - {-0.257377, 0.204704, 10.041275, 0}, - {-0.258574, 0.210690, 10.117889, 1}, - {-0.243011, 0.209493, 10.085567, 0}, - {-0.254982, 0.196324, 10.109509, 0}, - {-0.248997, 0.193930, 10.097539, 0}, - {-0.269348, 0.207098, 10.098736, 0}, - {-0.262165, 0.213084, 10.098736, 0}, - {-0.262165, 0.201113, 10.066414, 0}, - {-0.264559, 0.208295, 10.103524, 0}, - {-0.264559, 0.208295, 10.101130, 0}, - {-0.257377, 0.210690, 10.119086, 0}, - {-0.256179, 0.198719, 10.093947, 0}, - {-0.253785, 0.198719, 10.113101, 0}, - {-0.254982, 0.215478, 10.081977, 0}, - {-0.259771, 0.210690, 10.092751, 0}, - {-0.264559, 0.214281, 10.090356, 0}, - {-0.260968, 0.187945, 10.144226, 0}, - {-0.268150, 0.245406, 10.073597, 0}, - {-0.408211, 0.396240, 10.056837, 0}, - {-2.020705, 2.340331, 10.170562, 0}, - {-0.186748, 1.916557, 10.966634, 0}, - {7.234076, -2.675519, 16.133318, 0}, - {7.775165, 0.863109, 11.798618, 0}, - {3.503912, -1.510740, 2.634817, 0}, - {-3.895364, -5.768825, 9.538493, 0}, - {-4.587287, -2.717417, 26.975452, 0}, - {-3.013101, 4.329911, 32.156502, 0}, - {-4.693829, -1.854308, 19.993965, 0}, - {-5.236115, -2.634817, 18.126490, 0}, - {-6.558911, 1.010352, 20.283663, 0}, - {-8.033738, 0.130484, 22.203812, 0}, - {-7.487861, -0.525527, 18.705885, 0}, - {-6.692986, 0.266953, 15.228310, 0}, - {-6.151897, 0.128090, 10.176547, 0}, - {-6.020216, 0.745793, 5.400118, 0}, - {-5.798753, 1.690305, 1.695094, 0}, - {-3.584117, 1.229422, -1.827972, 0}, - {-0.386663, 1.133654, -4.835087, 0}, - {0.955286, 1.742978, -4.969162, 0}, - {3.201046, 1.059434, -6.075283, 0}, - {7.366954, -0.312443, -7.837414, 0}, - {8.429978, -0.656011, -6.296746, 0}, - {6.950363, -0.164003, -3.179498, 0}, - {6.801922, -0.415394, -0.955286, 0}, - {7.827837, -0.814028, 1.152807, 0}, - {7.793121, -0.723048, 3.940853, 0}, - {7.422020, -0.292092, 6.720520, 0}, - {7.978672, -0.298078, 7.856567, 0}, - {8.202530, -0.122104, 7.301113, 0}, - {7.778756, 0.360327, 6.107605, 0}, - {7.892480, 0.318429, 5.987895, 0}, - {8.950717, 0.108936, 6.327871, 0}, - {8.798685, 0.319626, 7.009021, 0}, - {7.748828, 0.839167, 7.133519, 0}, - {7.795516, 0.958877, 6.597219, 0}, - {7.850582, 1.035492, 5.942405, 0}, - {7.547716, 1.152807, 5.074507, 0}, - {7.116760, 1.128865, 4.546586, 0}, - {7.422020, 0.805648, 4.566936, 0}, - {7.937970, 0.517147, 4.827904, 0}, - {8.088805, 0.418985, 5.172669, 0}, - {8.329422, 0.415394, 5.573698, 0}, - {8.099579, 0.739808, 5.117603, 0}, - {7.973883, 0.805648, 4.387372, 0}, - {7.833823, 1.048660, 3.857056, 0}, - {8.100776, 1.177946, 3.950430, 0}, - {8.722071, 1.122880, 4.909307, 0}, - {9.400826, 0.921767, 5.566515, 0}, - {9.440331, 0.920570, 5.175064, 0}, - {8.723268, 1.022323, 4.551374, 0}, - {8.115141, 1.175552, 4.096477, 0}, - {8.135491, 1.387439, 3.754106, 0}, - {8.602361, 1.533485, 3.762486, 0}, - {8.884876, 1.289277, 4.268859, 0}, - {8.775940, 0.867898, 4.517856, 0}, - {8.434767, 0.647631, 4.377795, 0}, - {8.220486, 0.623689, 4.394554, 0}, - {7.817063, 0.945709, 4.226960, 0}, - {8.021768, 1.249772, 3.598483, 0}, - {9.108734, 0.667982, 3.156753, 0}, - {9.658203, 0.177171, 2.748542, 0}, - {9.301467, 0.393846, 2.639606, 0}, - {9.026134, 0.736217, 3.105278, 0}, - {8.865723, 0.814028, 3.799596, 0}, - {8.759181, 0.849941, 4.060563, 0}, - {8.493424, 0.964863, 4.404131, 0}, - {8.276750, 1.033097, 4.540600, 0}, - {8.324634, 0.908599, 4.672281, 0}, - {8.778335, 0.644040, 4.946417, 0}, - {8.558068, 0.827196, 5.007470, 0}, - {8.507790, 0.703895, 4.434059, 0}, - {8.688552, 0.684741, 3.661929, 0}, - {8.784320, 0.820014, 3.207031, 0}, - {8.844175, 0.839167, 3.385399, 0}, - {8.908818, 0.858321, 3.974372, 0}, - {9.044091, 0.907402, 4.442438, 0}, - {8.989024, 0.899022, 4.399343, 0}, - {8.925578, 0.815225, 4.141966, 0}, - {9.033317, 0.615309, 3.840297, 0}, - {9.083595, 0.436942, 3.727770, 0}, - {9.020149, 0.338779, 3.928882, 0}, - {8.930367, 0.299275, 4.174288, 0}, - {8.963885, 0.246603, 4.288013, 0}, - {8.842978, 0.304063, 4.236537, 0}, - {8.641865, 0.396240, 4.152740, 0}, - {8.591587, 0.466869, 4.163514, 0}, - {8.656230, 0.460884, 4.255691, 0}, - {8.836992, 0.398634, 4.118024, 0}, - {8.957899, 0.453701, 3.754106, 0}, - {9.045288, 0.502782, 3.326741, 0}, - {9.083595, 0.586579, 3.045423, 0}, - {9.033317, 0.705092, 3.004721, 0}, - {8.968674, 0.715866, 3.072956, 0}, - {8.899241, 0.684741, 3.071759, 0}, - {8.809459, 0.632069, 3.072956, 0}, - {8.832204, 0.585382, 3.138796, 0}, - {8.825022, 0.575805, 3.143585, 0}, - {8.761575, 0.556652, 3.064576, 0}, - {8.750801, 0.594959, 3.092109, 0}, - {8.817839, 0.633266, 3.129220, 0}, - {8.913607, 0.640449, 3.046620, 0}, - {8.998601, 0.658405, 2.869449, 0}, - {9.095566, 0.684741, 2.670730, 0}, - {9.133873, 0.694318, 2.789243, 0}, - {9.126691, 0.676362, 3.256112, 0}, - {9.041697, 0.723048, 3.632001, 0}, - {8.827415, 0.763750, 3.794807, 0}, - {8.853752, 0.694318, 3.775654, 0}, - {9.000996, 0.618901, 3.673900, 0}, - {9.066835, 0.561440, 3.708616, 0}, - {9.075215, 0.497994, 3.767274, 0}, - {9.064442, 0.417788, 3.775654, 0}, - {9.003389, 0.444124, 3.676294, 0}, - {8.943534, 0.500388, 3.551796, 0}, - {8.961491, 0.505176, 3.343500, 0}, - {8.789108, 0.600944, 3.191469, 0}, - {8.816642, 0.596156, 3.118446, 0}, - {8.889665, 0.549469, 3.131614, 0}, - {8.881285, 0.533907, 3.242944, 0}, - {8.783123, 0.590170, 3.416523, 0}, - {8.716085, 0.642843, 3.600877, 0}, - {8.719677, 0.612915, 3.694251, 0}, - {8.792700, 0.532710, 3.641578, 0}, - {8.895650, 0.470460, 3.475181, 0}, - {8.902833, 0.453701, 3.179498, 0}, - {8.833401, 0.399831, 2.855083, 0}, - {8.759181, 0.278924, 2.383426, 0}, - {8.670595, 0.118513, 1.875856, 0}, - {8.531732, -0.013168, 1.414972, 0}, - {8.376109, -0.057461, 1.115697, 0}, - {8.304283, -0.015562, 1.341949, 0}, - {7.916422, 0.159214, 1.878250, 0}, - {7.595600, 0.270545, 3.086124, 0}, - {7.516591, 0.349553, 4.906913, 0}, - {7.881707, 0.061052, 6.694183, 0}, - {8.112747, -0.235829, 7.243652, 0}, - {8.034935, -0.387860, 7.001838, 0}, - {8.052892, -0.222661, 6.254848, 0}, - {7.948744, 0.203507, 5.623976, 0}, - {7.327449, 0.853532, 5.892127, 0}, - {6.556517, 1.406592, 6.268016, 0}, - {6.993458, 1.375468, 6.548137, 0}, - {7.503423, 1.138442, 6.823470, 0}, - {7.237667, 1.118091, 7.408852, 0}, - {7.144293, 1.031900, 8.170208, 0}, - {7.127533, 0.927753, 8.361744, 0}, - {6.883325, 0.820014, 8.204924, 0}, - {6.708549, 0.644040, 7.923605, 0}, - {6.877340, 0.410605, 7.595600, 0}, - {7.054511, 0.339976, 7.395684, 0}, - {7.176615, 0.295684, 7.271185, 0}, - {7.182600, 0.259771, 7.201754, 0}, - {6.823470, 0.384269, 7.207739, 0}, - {6.624752, 0.464475, 7.419626, 0}, - {6.767207, 0.436942, 7.730872, 0}, - {6.834244, 0.386663, 7.971489, 0}, - {6.795937, 0.344765, 7.827837, 0}, - {6.531378, 0.404620, 7.354982, 0}, - {6.513421, 0.317232, 7.140702, 0}, - {6.649891, 0.192733, 7.065284, 0}, - {6.544546, 0.299275, 6.846215, 0}, - {6.555320, 0.381875, 6.678621, 0}, - {6.630737, 0.332794, 6.690592, 0}, - {6.636723, 0.199916, 6.915647, 0}, - {6.590036, 0.169988, 7.594403, 0}, - {6.248862, 0.393846, 8.506593, 0}, - {6.199781, 0.445321, 8.953111, 0}, - {6.538560, 0.023942, 8.977053, 0}, - {6.251256, 0.074220, 8.766363, 0}, - {6.154291, 0.337582, 8.178588, 0}, - {6.550531, 0.281319, 7.522577, 0}, - {6.397303, 0.652420, 7.284354, 0}, - {6.174642, 0.914584, 7.181403, 0}, - {6.265622, 0.825999, 6.584050, 0}, - {6.449975, 0.812831, 6.244074, 0}, - {6.738476, 0.641646, 6.549335, 0}, - {6.904873, 0.591367, 6.961137, 0}, - {6.669044, 0.671573, 7.244849, 0}, - {6.514618, 0.677559, 7.499832, 0}, - {6.716928, 0.464475, 7.510606, 0}, - {6.792346, 0.463278, 7.596797, 0}, - {6.734885, 0.585382, 7.791924, 0}, - {6.658270, 0.447715, 7.554898, 0}, - {6.463143, 0.486023, 7.091620, 0}, - {6.501450, 0.563834, 6.517013, 0}, - {6.488282, 0.654814, 6.062115, 0}, - {6.436807, 0.670376, 6.069297, 0}, - {6.479902, 0.659602, 6.549335, 0}, - {6.368572, 0.628478, 7.060496, 0}, - {6.446383, 0.487220, 7.497437, 0}, - {6.628343, 0.423773, 7.789530, 0}, - {6.636723, 0.460884, 7.996628, 0}, - {6.369769, 0.560243, 8.149857, 0}, - {6.105210, 0.602141, 8.106761, 0}, - {6.810302, 0.294487, 8.166616, 0}, - {7.140702, 0.201113, 8.110353, 0}, - {6.691789, 0.211887, 7.706930, 0}, - {6.524195, 0.271742, 7.422020, 0}, - {6.406879, 0.363918, 7.422020, 0}, - {6.278790, 0.423773, 7.556096, 0}, - {6.175839, 0.460884, 7.661440, 0}, - {6.229709, 0.451307, 7.507014, 0}, - {6.511027, 0.403423, 6.991064, 0}, - {6.872551, 0.345962, 6.734885, 0}, - {6.777980, 0.488417, 6.701366, 0}, - {6.730096, 0.620098, 6.682212, 0}, - {6.818682, 0.694318, 6.673833, 0}, - {6.897690, 0.634463, 6.702563, 0}, - {6.824667, 0.557849, 6.743265, 0}, - {6.700169, 0.621295, 6.815091, 0}, - {6.441595, 0.687135, 6.744462, 0}, - {6.476311, 0.812831, 6.872551, 0}, - {7.070073, 0.621295, 7.327449, 0}, - {6.791149, 0.446518, 7.169432, 0}, - {6.742067, 0.513556, 7.479481, 0}, - {6.738476, 0.420182, 7.603980, 0}, - {6.797134, 0.195127, 7.705733, 0}, - {6.882128, 0.363918, 7.593205, 0}, - {6.769601, 0.568623, 7.325055, 0}, - {6.915647, 0.465672, 7.016203, 0}, - {7.165841, 0.305261, 6.475114, 0}, - {7.277171, 0.234632, 5.893323, 0}, - {7.274777, 0.275333, 5.352234, 0}, - {6.994656, 0.428562, 5.149924, 0}, - {6.801922, 0.456095, 5.353431, 0}, - {6.751644, 0.354342, 5.864593, 0}, - {6.592430, 0.339976, 6.321885, 0}, - {6.416456, 0.262165, 6.567291, 0}, - {6.847412, -0.142455, 7.101197, 0}, - {7.248441, -0.061052, 7.084438, 0}, - {6.556517, 0.310049, 7.459130, 0}, - {6.555320, 0.251391, 7.558490, 0}, - {6.552926, 0.347159, 7.578840, 0}, - {6.534969, 0.442927, 7.498635, 0}, - {6.439201, 0.484826, 7.303507, 0}, - {6.555320, 0.341173, 7.278368, 0}, - {6.587642, 0.209493, 7.347800, 0}, - {6.563700, 0.135272, 7.492649, 0}, - {6.603204, 0.100556, 7.559687, 0}, - {6.515815, 0.198719, 7.558490, 0}, - {6.441595, 0.270545, 7.536942, 0}, - {6.330265, 0.298078, 7.629118, 0}, - {6.339842, 0.277727, 7.694959, 0}, - {6.260833, 0.245406, 7.636301, 0}, - {6.145912, 0.185551, 7.546519, 0}, - {6.068100, 0.132878, 7.322661, 0}, - {5.987895, 0.122104, 7.220907, 0}, - {5.989091, 0.123301, 7.357377, 0}, - {5.981909, 0.122104, 7.590811, 0}, - {6.020216, 0.088585, 7.677002, 0}, - {6.030990, 0.148440, 7.593205, 0}, - {6.063312, 0.219069, 7.480678, 0}, - {6.089648, 0.265756, 7.527365, 0}, - {6.050144, 0.359130, 7.862553, 0}, - {6.011837, 0.365116, 8.170208, 0}, - {6.011837, 0.265756, 8.222880, 0}, - {5.893323, 0.202310, 8.207318, 0}, - {5.845439, 0.137667, 8.021768, 0}, - {5.822695, 0.196324, 8.021768, 0}, - {5.906492, 0.239420, 8.250414, 0}, - {5.809526, 0.296881, 8.378503, 0}, - {5.810724, 0.222661, 8.389277, 0}, - {5.754460, 0.226252, 8.317451, 0}, - {5.809526, 0.104148, 8.396460, 0}, - {5.810724, 0.187945, 8.570039, 0}, - {6.063312, 0.287304, 8.530535, 0}, - {6.098028, 0.141258, 8.274356, 0}, - {5.651509, 0.290895, 8.311465, 0}, - {5.661086, 0.392649, 8.327028, 0}, - {5.258861, 0.590170, 8.374912, 0}, - {6.062115, 0.117316, 7.928393, 0}, - {6.623555, -0.246603, 7.491452, 0}, - {6.019019, 0.135272, 7.080847, 0}, - {6.084859, 0.463278, 7.062890, 0}, - {5.912477, 0.451307, 7.258018, 0}, - {5.827483, 0.532710, 7.372939, 0}, - {5.821497, 0.537498, 7.540533, 0}, - {5.737700, 0.536301, 7.648272, 0}, - {5.851425, 0.383072, 7.718901, 0}, - {6.072888, 0.365116, 7.699748, 0}, - {5.929236, 0.392649, 7.878115, 0}, - {5.967544, 0.354342, 8.107959, 0}, - {6.045355, 0.253785, 8.421598, 0}, - {5.923251, 0.323217, 8.574827, 0}, - {5.803541, 0.372298, 8.486242, 0}, - {5.785584, 0.416591, 8.215697, 0}, - {5.768825, 0.496797, 7.946350, 0}, - {5.838257, 0.527921, 7.711719, 0}, - {5.963953, 0.471657, 7.472299, 0}, - {5.986697, 0.430956, 7.435188, 0}, - {5.928040, 0.436942, 7.484270, 0}, - {5.907689, 0.472855, 7.449553, 0}, - {5.935222, 0.456095, 7.354982, 0}, - {5.959164, 0.450110, 7.420823, 0}, - {5.960361, 0.391452, 7.717704, 0}, - {5.880156, 0.399831, 7.902057, 0}, - {5.771219, 0.411802, 7.936773, 0}, - {5.997471, 0.266953, 8.137886, 0}, - {5.945996, 0.380678, 8.301888, 0}, - {5.877761, 0.434547, 8.265976, 0}, - {5.904098, 0.408211, 7.947547, 0}, - {5.918463, 0.432153, 7.615951, 0}, - {5.869381, 0.438139, 7.486664, 0}, - {5.837060, 0.451307, 7.556096, 0}, - {5.900506, 0.465672, 7.654258, 0}, - {5.870579, 0.454898, 7.651864, 0}, - {5.875367, 0.454898, 7.615951, 0}, - {5.887338, 0.451307, 7.697353, 0}, - {5.850228, 0.456095, 7.779953, 0}, - {5.858608, 0.477643, 7.884101, 0}, - {5.749671, 0.506373, 7.787136, 0}, - {5.683831, 0.507570, 7.660243, 0}, - {5.740095, 0.469263, 7.811078, 0}, - {5.766431, 0.405817, 8.002614, 0}, - {5.714955, 0.442927, 8.042118, 0}, - {5.723335, 0.399831, 8.002614, 0}, - {5.712561, 0.343568, 7.995431, 0}, - {5.741292, 0.323217, 8.110353, 0}, - {5.766431, 0.349553, 8.237246, 0}, - {5.704182, 0.367510, 8.276750, 0}, - {5.651509, 0.348356, 8.161828, 0}, - {5.655100, 0.367510, 7.977475, 0}, - {5.770022, 0.269348, 8.037330, 0}, - {5.765234, 0.149638, 8.125915, 0}, - {5.671860, 0.073023, 7.973883, 0}, - {5.667071, 0.105345, 7.836217, 0}, - {5.662283, 0.092177, 7.824246, 0}, - {5.702984, 0.031125, 7.970292, 0}, - {5.731715, -0.005986, 8.169010, 0}, - {5.705379, -0.038307, 8.178588, 0}, - {5.635947, -0.082600, 8.060075, 0}, - {5.614399, -0.087388, 7.846991, 0}, - {5.607216, -0.051475, 7.807487, 0}, - {5.610808, -0.033519, 7.864947, 0}, - {5.594049, 0.014365, 7.959518, 0}, - {5.595245, 0.070629, 8.085214, 0}, - {5.577289, 0.046687, 8.267173, 0}, - {5.512646, -0.061052, 8.195347, 0}, - {5.414484, -0.068235, 7.988248, 0}, - {5.358220, 0.023942, 7.862553, 0}, - {5.412089, 0.094571, 7.925999, 0}, - {5.420469, 0.159214, 8.106761, 0}, - {5.276817, 0.208295, 8.341393, 0}, - {5.264846, 0.239420, 8.215697, 0}, - {5.281605, 0.105345, 8.564054, 0}, - {5.311533, -0.020351, 8.683764, 0}, - {5.209779, 0.087388, 8.489834, 0}, - {5.149924, 0.135272, 8.765166, 0}, - {5.169078, 0.017957, 9.282313, 0}, - {5.274423, -0.105345, 9.628276, 0}, - {5.270832, -0.059855, 9.247598, 0}, - {5.166684, 0.098162, 8.629894, 0}, - {5.128376, 0.126893, 8.294706, 0}, - {5.119997, 0.088585, 8.373714, 0}, - {5.146333, 0.090980, 8.540112, 0}, - {5.112814, 0.226252, 8.293509, 0}, - {5.086478, 0.238223, 8.079228, 0}, - {5.076901, 0.137667, 8.086411, 0}, - {5.064930, 0.064643, 8.396460, 0}, - {5.090069, 0.101754, 8.791503, 0}, - {5.090069, 0.272939, 9.018951, 0}, - {5.106829, 0.399831, 8.947125, 0}, - {5.129574, 0.401029, 8.738831, 0}, - {5.143939, 0.233435, 8.713691, 0}, - {5.165487, 0.124498, 8.570039, 0}, - {5.170275, 0.147243, 8.276750, 0}, - {5.114011, 0.207098, 7.818260, 0}, - {5.033806, 0.308852, 7.491452, 0}, - {5.043383, 0.314837, 7.789530, 0}, - {5.061339, 0.219069, 8.386883, 0}, - {5.069719, 0.137667, 8.644259, 0}, - {5.058945, 0.147243, 8.481454, 0}, - {5.007470, 0.186748, 8.107959, 0}, - {4.957191, 0.214281, 8.024161, 0}, - {5.048171, 0.130484, 8.451527, 0}, - {5.088872, 0.058658, 8.924380, 0}, - {5.104434, -0.016759, 9.154224, 0}, - {5.117603, -0.027533, 8.935155, 0}, - {5.018243, 0.071826, 8.637076, 0}, - {4.983528, 0.090980, 8.604755, 0}, - {5.019441, 0.026336, 8.650245, 0}, - {5.030214, -0.013168, 8.646653, 0}, - {4.939235, -0.026336, 8.565250, 0}, - {4.879380, -0.089783, 8.562857, 0}, - {4.832693, -0.186748, 8.906425, 0}, - {4.851846, -0.294487, 9.361322, 0}, - {4.910504, -0.284910, 9.572012, 0}, - {4.920081, -0.166397, 9.233232, 0}, - {4.865015, -0.051475, 8.621514, 0}, - {4.821919, -0.007183, 8.482651, 0}, - {4.851846, -0.021548, 8.792700, 0}, - {4.916490, -0.056264, 9.081201, 0}, - {4.939235, -0.034716, 8.680172, 0}, - {4.878182, 0.039504, 8.130703, 0}, - {4.825510, 0.070629, 8.079228, 0}, - {4.854240, 0.033519, 8.445540, 0}, - {4.932052, -0.016759, 8.767561, 0}, - {4.988316, -0.080206, 8.864526, 0}, - {5.024229, -0.152032, 8.710100, 0}, - {5.026623, -0.175974, 8.593981, 0}, - {5.011061, -0.119710, 8.465892, 0}, - {5.051762, -0.058658, 8.503001, 0}, - {5.104434, 0.028730, 8.389277, 0}, - {5.108026, 0.174777, 8.304283, 0}, - {5.121194, 0.207098, 8.368926, 0}, - {5.137953, 0.177171, 8.186967, 0}, - {5.123588, 0.141258, 8.036133, 0}, - {5.098449, 0.186748, 8.031344, 0}, - {5.036200, 0.240617, 8.049300, 0}, - {4.977542, 0.316034, 8.190558, 0}, - {4.978739, 0.294487, 8.428782, 0}, - {5.046974, 0.195127, 8.704114, 0}, - {5.042185, 0.211887, 8.719677, 0}, - {4.927264, 0.299275, 8.538915, 0}, - {4.918884, 0.241814, 8.495819, 0}, - {4.897336, 0.189142, 8.492228, 0}, - {4.878182, 0.237026, 8.601164, 0}, - {4.818327, 0.262165, 8.705312, 0}, - {4.871000, 0.172382, 8.791503, 0}, - {4.924870, 0.119710, 8.872906, 0}, - {4.873394, 0.243011, 8.825022, 0}, - {4.832693, 0.408211, 8.659822, 0}, - {4.838678, 0.367510, 8.619121, 0}, - {4.904519, 0.169988, 8.809459, 0}, - {4.926067, 0.071826, 9.058456, 0}, - {4.940432, 0.058658, 8.823824, 0}, - {4.930855, 0.167594, 8.331817, 0}, - {4.918884, 0.266953, 8.265976, 0}, - {4.941629, 0.207098, 8.900438, 0}, - {4.957191, 0.129287, 9.339774, 0}, - {4.915293, 0.180762, 9.089581, 0}, - {4.930855, 0.190339, 8.826219, 0}, - {5.080492, 0.038307, 8.766363, 0}, - {5.204991, -0.108936, 8.631091, 0}, - {5.202597, -0.047884, 8.157040, 0}, - {5.157107, 0.095768, 7.870933, 0}, - {5.164289, 0.168791, 8.019373, 0}, - {5.199006, 0.167594, 8.428782, 0}, - {5.215765, 0.180762, 8.804670, 0}, - {5.201400, 0.278924, 8.614332, 0}, - {5.171472, 0.433350, 8.225274, 0}, - {5.199006, 0.466869, 8.068454, 0}, - {5.245692, 0.434547, 8.081622, 0}, - {5.252875, 0.493205, 8.092396, 0}, - {5.194217, 0.633266, 8.359349, 0}, - {5.155910, 0.772130, 8.494622, 0}, - {5.196611, 0.809240, 8.324634, 0}, - {5.245692, 0.724246, 8.206120, 0}, - {5.252875, 0.677559, 8.295903, 0}, - {5.234919, 0.689530, 8.449132, 0}, - {5.256466, 0.666785, 8.635880, 0}, - {5.276817, 0.672770, 8.653836, 0}, - {5.300759, 0.682347, 8.694537, 0}, - {5.352234, 0.640449, 8.677778, 0}, - {5.373782, 0.659602, 8.445540, 0}, - {5.371388, 0.752976, 8.093594, 0}, - {5.348643, 0.889445, 7.916422, 0}, - {5.337869, 0.974439, 8.097184, 0}, - {5.346249, 0.991199, 8.227669, 0}, - {5.382162, 0.978031, 8.289918, 0}, - {5.436031, 0.922964, 8.264779, 0}, - {5.408498, 0.940921, 8.136689, 0}, - {5.376176, 0.939724, 8.165420, 0}, - {5.364205, 0.924161, 8.331817, 0}, - {5.351037, 0.873883, 8.446738, 0}, - {5.334278, 0.855927, 8.334210, 0}, - {5.292379, 0.861912, 8.178588, 0}, - {5.298365, 0.858321, 8.146266, 0}, - {5.319912, 0.841561, 8.136689, 0}, - {5.353431, 0.793677, 8.121126, 0}, - {5.378571, 0.736217, 8.218092, 0}, - {5.397724, 0.694318, 8.354561, 0}, - {5.367796, 0.709880, 8.420402, 0}, - {5.335475, 0.749385, 8.528141, 0}, - {5.313927, 0.818816, 8.493424, 0}, - {5.306745, 0.889445, 8.315057, 0}, - {5.333081, 0.893037, 8.216895, 0}, - {5.345052, 0.899022, 8.208515, 0}, - {5.348643, 0.920570, 8.322240, 0}, - {5.346249, 0.955286, 8.494622, 0}, - {5.325898, 0.984016, 8.801080, 0}, - {5.355825, 0.998381, 9.132676, 0}, - {5.388147, 0.967257, 9.349351, 0}, - {5.489901, 0.889445, 9.421177, 0}, - {5.553347, 0.900219, 9.010572, 0}, - {5.532996, 1.004367, 8.176193, 0}, - {5.509054, 1.109712, 7.471101, 0}, - {5.504266, 1.175552, 7.400473, 0}, - {5.482718, 1.159990, 7.684185, 0}, - {5.443214, 1.177946, 8.027753, 0}, - {5.426455, 1.201888, 8.292312, 0}, - {5.492295, 1.139639, 8.359349, 0}, - {5.532996, 1.092952, 8.263581, 0}, - {5.522223, 1.072602, 7.959518, 0}, - {5.504266, 1.033097, 7.606374, 0}, - {5.524617, 0.958877, 7.461524, 0}, - {5.505463, 0.876277, 7.580038, 0}, - {5.458776, 0.823605, 7.835020, 0}, - {5.432440, 0.756567, 8.016979, 0}, - {5.386950, 0.760159, 8.174996, 0}, - {5.400118, 0.748188, 8.362941, 0}, - {5.449199, 0.687135, 8.324634, 0}, - {5.426455, 0.701501, 7.993037, 0}, - {5.407301, 0.751779, 7.637498, 0}, - {5.455185, 0.737414, 7.868538, 0}, - {5.456382, 0.735019, 8.342590, 0}, - {5.409695, 0.805648, 8.420402, 0}, - {5.379767, 0.878671, 8.323437, 0}, - {5.433637, 0.877474, 8.230062, 0}, - {5.477930, 0.864306, 8.248019, 0}, - {5.511448, 0.831985, 8.370124, 0}, - {5.525814, 0.817619, 8.439555, 0}, - {5.498281, 0.797269, 8.486242, 0}, - {5.485112, 0.806845, 8.465892, 0}, - {5.480324, 0.830787, 8.364138, 0}, - {5.485112, 0.831985, 8.337802, 0}, - {5.487506, 0.854729, 8.340196, 0}, - {5.434834, 0.873883, 8.372518, 0}, - {5.397724, 0.854729, 8.346182, 0}, - {5.392936, 0.869095, 8.216895, 0}, - {5.373782, 0.891840, 8.018176, 0}, - {5.401315, 0.872686, 7.902057, 0}, - {5.448002, 0.833182, 7.929591, 0}, - {5.425257, 0.835576, 8.146266, 0}, - {5.413286, 0.849941, 8.409628, 0}, - {5.421666, 0.837970, 8.495819, 0}, - {5.434834, 0.802057, 8.402445, 0}, - {5.456382, 0.772130, 8.238442, 0}, - {5.482718, 0.749385, 8.231260, 0}, - {5.497083, 0.744596, 8.304283, 0}, - {5.479127, 0.781706, 8.298298, 0}, - {5.432440, 0.882263, 8.295903, 0}, - {5.404907, 0.958877, 8.201332, 0}, - {5.397724, 0.944512, 8.110353, 0}, - {5.394133, 0.920570, 8.216895, 0}, - {5.437228, 0.899022, 8.328225, 0}, - {5.474339, 0.902613, 8.413219, 0}, - {5.529405, 0.889445, 8.447935, 0}, - {5.590457, 0.873883, 8.355759, 0}, - {5.612005, 0.877474, 8.292312, 0}, - {5.613202, 0.870292, 8.209712, 0}, - {5.585669, 0.913387, 8.025358, 0}, - {5.511448, 0.933738, 7.991840, 0}, - {5.475535, 0.949300, 8.026556, 0}, - {5.463564, 0.999579, 8.031344, 0}, - {5.469550, 0.994790, 7.918817, 0}, - {5.504266, 0.974439, 7.881707, 0}, - {5.546165, 0.991199, 7.955927, 0}, - {5.553347, 0.997184, 8.128309, 0}, - {5.567712, 1.010352, 8.230062, 0}, - {5.553347, 1.048660, 8.279144, 0}, - {5.578486, 1.033097, 8.268370, 0}, - {5.571303, 1.016338, 8.101973, 0}, - {5.543770, 0.985213, 7.933182, 0}, - {5.550953, 0.909796, 7.971489, 0}, - {5.547361, 0.855927, 7.951138, 0}, - {5.540179, 0.840364, 7.978672, 0}, - {5.523419, 0.848744, 8.152251, 0}, - {5.491098, 0.853532, 8.298298, 0}, - {5.420469, 0.901416, 8.333014, 0}, - {5.403709, 0.937329, 8.419205, 0}, - {5.440820, 0.964863, 8.601164, 0}, - {5.465959, 0.991199, 8.426387, 0}, - {5.457579, 1.051054, 8.109156, 0}, - {5.437228, 1.104923, 7.977475, 0}, - {5.428849, 1.102529, 8.027753, 0}, - {5.433637, 1.090558, 8.195347, 0}, - {5.432440, 1.100135, 8.276750, 0}, - {5.461170, 1.134851, 8.309072, 0}, - {5.511448, 1.119289, 8.292312, 0}, - {5.540179, 1.089361, 8.316254, 0}, - {5.518631, 1.103726, 8.358152, 0}, - {5.528208, 1.112106, 8.343787, 0}, - {5.527011, 1.094149, 8.257596, 0}, - {5.495886, 1.116894, 8.154645, 0}, - {5.510252, 1.092952, 8.208515, 0}, - {5.538982, 1.058236, 8.158237, 0}, - {5.511448, 1.088164, 7.948744, 0}, - {5.515040, 1.084573, 7.852976, 0}, - {5.507857, 1.104923, 7.959518, 0}, - {5.468353, 1.138442, 8.188165, 0}, - {5.468353, 1.148019, 8.327028, 0}, - {5.481521, 1.133654, 8.289918, 0}, - {5.511448, 1.120486, 8.226472, 0}, - {5.530602, 1.086967, 8.198938, 0}, - {5.529405, 1.065419, 8.166616, 0}, - {5.469550, 1.060631, 8.221684, 0}, - {5.440820, 1.053448, 8.240837, 0}, - {5.396527, 1.053448, 8.213304, 0}, - {5.386950, 1.055842, 8.234851, 0}, - {5.421666, 1.046265, 8.246822, 0}, - {5.431243, 1.029506, 8.155843, 0}, - {5.298365, 1.292868, 5.756854, 0}, - {5.191823, 1.255758, 8.088805, 0}, - {5.204991, 1.169567, 10.260345, 0} + { -0.269348, 0.220266, 10.030501, 0 }, + { -0.259771, 0.216675, 10.113101, 0 }, + { -0.253785, 0.213084, 10.096342, 0 }, + { -0.262165, 0.201113, 10.098736, 0 }, + { -0.257377, 0.210690, 10.093947, 0 }, + { -0.253785, 0.202310, 10.096342, 0 }, + { -0.257377, 0.213084, 10.113101, 0 }, + { -0.257377, 0.221464, 10.096342, 0 }, + { -0.262165, 0.217872, 10.115496, 0 }, + { -0.258574, 0.219069, 10.102327, 0 }, + { -0.275333, 0.205901, 10.123875, 0 }, + { -0.262165, 0.209493, 10.085567, 0 }, + { -0.271742, 0.209493, 10.110707, 0 }, + { -0.275333, 0.220266, 10.096342, 0 }, + { -0.251391, 0.210690, 10.097539, 0 }, + { -0.262165, 0.210690, 10.090356, 0 }, + { -0.268150, 0.208295, 10.108313, 0 }, + { -0.258574, 0.210690, 10.098736, 0 }, + { -0.270545, 0.219069, 10.097539, 0 }, + { -0.263362, 0.211887, 10.102327, 0 }, + { -0.264559, 0.211887, 10.097539, 0 }, + { -0.262165, 0.204704, 10.090356, 0 }, + { -0.246603, 0.203507, 10.089159, 0 }, + { -0.250194, 0.215478, 10.099933, 0 }, + { -0.270545, 0.225055, 10.109509, 0 }, + { -0.256179, 0.213084, 10.097539, 0 }, + { -0.248997, 0.207098, 10.086765, 0 }, + { -0.248997, 0.210690, 10.087962, 0 }, + { -0.256179, 0.201113, 10.089159, 0 }, + { -0.258574, 0.203507, 10.104721, 0 }, + { -0.262165, 0.208295, 10.093947, 0 }, + { -0.246603, 0.204704, 10.086765, 0 }, + { -0.247800, 0.208295, 10.108313, 0 }, + { -0.252588, 0.220266, 10.099933, 0 }, + { -0.264559, 0.210690, 10.098736, 0 }, + { -0.266953, 0.185551, 10.084371, 0 }, + { -0.253785, 0.213084, 10.109509, 0 }, + { -0.256179, 0.231040, 10.099933, 0 }, + { -0.252588, 0.205901, 10.091554, 0 }, + { -0.259771, 0.207098, 10.095144, 0 }, + { -0.260968, 0.203507, 10.096342, 0 }, + { -0.253785, 0.205901, 10.095144, 0 }, + { -0.256179, 0.217872, 10.093947, 0 }, + { -0.265756, 0.209493, 10.083174, 0 }, + { -0.263362, 0.204704, 10.103524, 0 }, + { -0.253785, 0.198719, 10.095144, 0 }, + { -0.252588, 0.209493, 10.103524, 0 }, + { -0.260968, 0.205901, 10.098736, 0 }, + { -0.259771, 0.205901, 10.083174, 0 }, + { -0.266953, 0.216675, 10.090356, 0 }, + { -0.265756, 0.207098, 10.101130, 0 }, + { -0.262165, 0.204704, 10.111904, 0 }, + { -0.248997, 0.199916, 10.101130, 0 }, + { -0.263362, 0.207098, 10.096342, 0 }, + { -0.281319, 0.227449, 10.108313, 0 }, + { -0.259771, 0.219069, 10.087962, 0 }, + { -0.258574, 0.214281, 10.079582, 0 }, + { -0.268150, 0.204704, 10.108313, 0 }, + { -0.277727, 0.204704, 10.114298, 0 }, + { -0.257377, 0.208295, 10.115496, 0 }, + { -0.260968, 0.222661, 10.104721, 0 }, + { -0.265756, 0.213084, 10.102327, 0 }, + { -0.256179, 0.210690, 10.099933, 0 }, + { -0.253785, 0.203507, 10.109509, 0 }, + { -0.270545, 0.201113, 10.103524, 0 }, + { -0.259771, 0.209493, 10.115496, 0 }, + { -0.264559, 0.207098, 10.103524, 0 }, + { -0.263362, 0.202310, 10.105919, 0 }, + { -0.260968, 0.220266, 10.110707, 0 }, + { -0.257377, 0.216675, 10.110707, 0 }, + { -0.259771, 0.195127, 10.093947, 0 }, + { -0.271742, 0.209493, 10.104721, 0 }, + { -0.257377, 0.223858, 10.108313, 0 }, + { -0.265756, 0.205901, 10.101130, 0 }, + { -0.270545, 0.196324, 10.101130, 0 }, + { -0.254982, 0.202310, 10.115496, 0 }, + { -0.248997, 0.214281, 10.116693, 0 }, + { -0.268150, 0.207098, 10.111904, 0 }, + { -0.263362, 0.204704, 10.091554, 0 }, + { -0.270545, 0.210690, 10.091554, 0 }, + { -0.268150, 0.215478, 10.102327, 0 }, + { -0.264559, 0.223858, 10.096342, 0 }, + { -0.262165, 0.203507, 10.099933, 0 }, + { -0.259771, 0.203507, 10.103524, 0 }, + { -0.269348, 0.204704, 10.119086, 0 }, + { -0.265756, 0.202310, 10.091554, 0 }, + { -0.260968, 0.201113, 10.092751, 0 }, + { -0.260968, 0.210690, 10.092751, 0 }, + { -0.266953, 0.205901, 10.109509, 0 }, + { -0.269348, 0.203507, 10.105919, 0 }, + { -0.264559, 0.193930, 10.114298, 0 }, + { -0.263362, 0.216675, 10.093947, 0 }, + { -0.256179, 0.208295, 10.095144, 0 }, + { -0.271742, 0.203507, 10.103524, 0 }, + { -0.259771, 0.208295, 10.089159, 0 }, + { -0.257377, 0.220266, 10.108313, 0 }, + { -0.266953, 0.207098, 10.101130, 0 }, + { -0.268150, 0.198719, 10.117889, 0 }, + { -0.258574, 0.204704, 10.091554, 0 }, + { -0.266953, 0.201113, 10.104721, 0 }, + { -0.265756, 0.205901, 10.091554, 0 }, + { -0.277727, 0.203507, 10.102327, 0 }, + { -0.266953, 0.204704, 10.093947, 0 }, + { -0.265756, 0.215478, 10.107116, 0 }, + { -0.254982, 0.215478, 10.110707, 0 }, + { -0.269348, 0.217872, 10.095144, 0 }, + { -0.265756, 0.229843, 10.109509, 0 }, + { -0.260968, 0.226252, 10.098736, 0 }, + { -0.253785, 0.208295, 10.095144, 0 }, + { -0.253785, 0.211887, 10.085567, 0 }, + { -0.268150, 0.214281, 10.109509, 0 }, + { -0.258574, 0.201113, 10.107116, 0 }, + { -0.265756, 0.211887, 10.103524, 0 }, + { -0.256179, 0.215478, 10.093947, 0 }, + { -0.263362, 0.204704, 10.107116, 0 }, + { -0.260968, 0.214281, 10.098736, 0 }, + { -0.259771, 0.213084, 10.110707, 0 }, + { -0.276530, 0.215478, 10.095144, 0 }, + { -0.263362, 0.211887, 10.084371, 0 }, + { -0.245406, 0.217872, 10.110707, 0 }, + { -0.251391, 0.209493, 10.105919, 0 }, + { -0.269348, 0.205901, 10.093947, 0 }, + { -0.271742, 0.201113, 10.099933, 0 }, + { -0.270545, 0.228646, 10.099933, 0 }, + { -0.262165, 0.217872, 10.096342, 0 }, + { -0.259771, 0.209493, 10.099933, 0 }, + { -0.260968, 0.210690, 10.105919, 0 }, + { -0.252588, 0.203507, 10.099933, 0 }, + { -0.263362, 0.197522, 10.095144, 0 }, + { -0.271742, 0.213084, 10.101130, 0 }, + { -0.268150, 0.196324, 10.110707, 0 }, + { -0.248997, 0.213084, 10.108313, 0 }, + { -0.254982, 0.215478, 10.095144, 0 }, + { -0.260968, 0.208295, 10.107116, 0 }, + { -0.259771, 0.219069, 10.108313, 0 }, + { -0.266953, 0.214281, 10.098736, 0 }, + { -0.269348, 0.202310, 10.090356, 0 }, + { -0.258574, 0.204704, 10.113101, 0 }, + { -0.263362, 0.226252, 10.086765, 0 }, + { -0.264559, 0.204704, 10.096342, 0 }, + { -0.271742, 0.219069, 10.096342, 0 }, + { -0.252588, 0.210690, 10.104721, 0 }, + { -0.258574, 0.211887, 10.113101, 0 }, + { -0.264559, 0.210690, 10.104721, 0 }, + { -0.269348, 0.214281, 10.103524, 0 }, + { -0.253785, 0.211887, 10.093947, 0 }, + { -0.256179, 0.223858, 10.110707, 0 }, + { -0.274136, 0.207098, 10.098736, 0 }, + { -0.274136, 0.207098, 10.092751, 0 }, + { -0.254982, 0.210690, 10.091554, 0 }, + { -0.257377, 0.204704, 10.098736, 0 }, + { -0.257377, 0.209493, 10.108313, 0 }, + { -0.257377, 0.211887, 10.095144, 0 }, + { -0.259771, 0.199916, 10.095144, 0 }, + { -0.257377, 0.214281, 10.101130, 0 }, + { -0.270545, 0.217872, 10.103524, 0 }, + { -0.281319, 0.204704, 10.104721, 0 }, + { -0.271742, 0.208295, 10.103524, 0 }, + { -0.258574, 0.211887, 10.104721, 0 }, + { -0.264559, 0.204704, 10.126269, 0 }, + { -0.262165, 0.201113, 10.101130, 0 }, + { -0.258574, 0.219069, 10.096342, 0 }, + { -0.263362, 0.211887, 10.107116, 0 }, + { -0.265756, 0.203507, 10.091554, 0 }, + { -0.264559, 0.205901, 10.107116, 0 }, + { -0.256179, 0.214281, 10.095144, 0 }, + { -0.263362, 0.202310, 10.097539, 0 }, + { -0.271742, 0.207098, 10.104721, 0 }, + { -0.272939, 0.210690, 10.101130, 0 }, + { -0.262165, 0.205901, 10.096342, 0 }, + { -0.260968, 0.209493, 10.107116, 0 }, + { -0.269348, 0.217872, 10.093947, 0 }, + { -0.256179, 0.220266, 10.087962, 0 }, + { -0.264559, 0.208295, 10.092751, 0 }, + { -0.265756, 0.208295, 10.095144, 0 }, + { -0.262165, 0.199916, 10.098736, 0 }, + { -0.259771, 0.215478, 10.101130, 0 }, + { -0.263362, 0.217872, 10.097539, 0 }, + { -0.263362, 0.204704, 10.095144, 0 }, + { -0.248997, 0.202310, 10.096342, 0 }, + { -0.260968, 0.226252, 10.097539, 0 }, + { -0.259771, 0.216675, 10.103524, 0 }, + { -0.270545, 0.205901, 10.090356, 0 }, + { -0.250194, 0.219069, 10.089159, 0 }, + { -0.254982, 0.213084, 10.098736, 0 }, + { -0.268150, 0.204704, 10.102327, 0 }, + { -0.258574, 0.215478, 10.104721, 0 }, + { -0.250194, 0.217872, 10.102327, 0 }, + { -0.250194, 0.215478, 10.097539, 0 }, + { -0.251391, 0.213084, 10.086765, 0 }, + { -0.266953, 0.204704, 10.108313, 0 }, + { -0.270545, 0.199916, 10.099933, 0 }, + { -0.271742, 0.208295, 10.092751, 0 }, + { -0.268150, 0.222661, 10.098736, 0 }, + { -0.252588, 0.213084, 10.096342, 0 }, + { -0.266953, 0.213084, 10.092751, 0 }, + { -0.265756, 0.205901, 10.105919, 0 }, + { -0.258574, 0.209493, 10.103524, 0 }, + { -0.263362, 0.203507, 10.103524, 0 }, + { -0.265756, 0.213084, 10.092751, 0 }, + { -0.266953, 0.209493, 10.097539, 0 }, + { -0.272939, 0.193930, 10.110707, 0 }, + { -0.258574, 0.209493, 10.109509, 0 }, + { -0.259771, 0.213084, 10.101130, 0 }, + { -0.274136, 0.215478, 10.101130, 0 }, + { -0.259771, 0.207098, 10.091554, 0 }, + { -0.265756, 0.208295, 10.101130, 0 }, + { -0.263362, 0.210690, 10.109509, 0 }, + { -0.264559, 0.216675, 10.110707, 0 }, + { -0.266953, 0.211887, 10.099933, 0 }, + { -0.268150, 0.199916, 10.093947, 0 }, + { -0.265756, 0.216675, 10.105919, 0 }, + { -0.262165, 0.204704, 10.081977, 0 }, + { -0.263362, 0.214281, 10.086765, 0 }, + { -0.263362, 0.210690, 10.084371, 0 }, + { -0.257377, 0.201113, 10.104721, 0 }, + { -0.262165, 0.203507, 10.109509, 0 }, + { -0.266953, 0.217872, 10.113101, 0 }, + { -0.252588, 0.209493, 10.102327, 0 }, + { -0.257377, 0.213084, 10.096342, 0 }, + { -0.260968, 0.211887, 10.101130, 0 }, + { -0.263362, 0.197522, 10.114298, 0 }, + { -0.272939, 0.192733, 10.103524, 0 }, + { -0.250194, 0.207098, 10.079582, 0 }, + { -0.253785, 0.214281, 10.107116, 0 }, + { -0.254982, 0.205901, 10.095144, 0 }, + { -0.256179, 0.209493, 10.103524, 0 }, + { -0.265756, 0.222661, 10.111904, 0 }, + { -0.259771, 0.211887, 10.101130, 0 }, + { -0.256179, 0.202310, 10.115496, 0 }, + { -0.260968, 0.209493, 10.109509, 0 }, + { -0.243011, 0.203507, 10.101130, 0 }, + { -0.252588, 0.205901, 10.096342, 0 }, + { -0.253785, 0.225055, 10.095144, 0 }, + { -0.258574, 0.225055, 10.096342, 0 }, + { -0.264559, 0.215478, 10.092751, 0 }, + { -0.265756, 0.205901, 10.114298, 0 }, + { -0.266953, 0.220266, 10.108313, 0 }, + { -0.268150, 0.208295, 10.109509, 0 }, + { -0.259771, 0.210690, 10.103524, 0 }, + { -0.253785, 0.210690, 10.109509, 0 }, + { -0.268150, 0.213084, 10.097539, 0 }, + { -0.268150, 0.215478, 10.102327, 0 }, + { -0.269348, 0.201113, 10.103524, 0 }, + { -0.262165, 0.199916, 10.107116, 0 }, + { -0.260968, 0.205901, 10.120284, 0 }, + { -0.257377, 0.193930, 10.102327, 0 }, + { -0.264559, 0.203507, 10.104721, 0 }, + { -0.265756, 0.210690, 10.093947, 0 }, + { -0.256179, 0.209493, 10.097539, 0 }, + { -0.257377, 0.204704, 10.107116, 0 }, + { -0.260968, 0.208295, 10.093947, 0 }, + { -0.258574, 0.204704, 10.102327, 0 }, + { -0.263362, 0.211887, 10.107116, 0 }, + { -0.263362, 0.191536, 10.097539, 0 }, + { -0.253785, 0.209493, 10.107116, 0 }, + { -0.254982, 0.217872, 10.105919, 0 }, + { -0.259771, 0.207098, 10.096342, 0 }, + { -0.265756, 0.204704, 10.114298, 0 }, + { -0.270545, 0.208295, 10.099933, 0 }, + { -0.262165, 0.214281, 10.104721, 0 }, + { -0.257377, 0.205901, 10.095144, 0 }, + { -0.266953, 0.214281, 10.096342, 0 }, + { -0.274136, 0.225055, 10.093947, 0 }, + { -0.266953, 0.216675, 10.099933, 0 }, + { -0.269348, 0.208295, 10.099933, 0 }, + { -0.266953, 0.222661, 10.105919, 0 }, + { -0.246603, 0.204704, 10.090356, 0 }, + { -0.257377, 0.202310, 10.102327, 0 }, + { -0.258574, 0.217872, 10.114298, 0 }, + { -0.268150, 0.225055, 10.099933, 0 }, + { -0.278924, 0.210690, 10.097539, 0 }, + { -0.263362, 0.203507, 10.104721, 0 }, + { -0.252588, 0.221464, 10.089159, 0 }, + { -0.252588, 0.208295, 10.073597, 0 }, + { -0.252588, 0.213084, 10.091554, 0 }, + { -0.256179, 0.210690, 10.087962, 0 }, + { -0.272939, 0.214281, 10.097539, 0 }, + { -0.259771, 0.203507, 10.097539, 0 }, + { -0.271742, 0.208295, 10.102327, 0 }, + { -0.262165, 0.216675, 10.095144, 0 }, + { -0.264559, 0.215478, 10.095144, 0 }, + { -0.265756, 0.214281, 10.103524, 0 }, + { -0.268150, 0.217872, 10.096342, 0 }, + { -0.262165, 0.221464, 10.104721, 0 }, + { -0.274136, 0.219069, 10.101130, 0 }, + { -0.264559, 0.208295, 10.097539, 0 }, + { -0.265756, 0.203507, 10.089159, 0 }, + { -0.269348, 0.204704, 10.110707, 0 }, + { -0.268150, 0.214281, 10.116693, 0 }, + { -0.250194, 0.199916, 10.102327, 0 }, + { -0.266953, 0.197522, 10.105919, 0 }, + { -0.268150, 0.199916, 10.108313, 0 }, + { -0.259771, 0.195127, 10.093947, 0 }, + { -0.262165, 0.215478, 10.085567, 0 }, + { -0.263362, 0.216675, 10.101130, 0 }, + { -0.252588, 0.227449, 10.037683, 0 }, + { -0.276530, 0.208295, 10.177745, 0 }, + { -0.254982, 0.205901, 10.175350, 0 }, + { -0.257377, 0.204704, 10.041275, 0 }, + { -0.258574, 0.210690, 10.117889, 1 }, + { -0.243011, 0.209493, 10.085567, 0 }, + { -0.254982, 0.196324, 10.109509, 0 }, + { -0.248997, 0.193930, 10.097539, 0 }, + { -0.269348, 0.207098, 10.098736, 0 }, + { -0.262165, 0.213084, 10.098736, 0 }, + { -0.262165, 0.201113, 10.066414, 0 }, + { -0.264559, 0.208295, 10.103524, 0 }, + { -0.264559, 0.208295, 10.101130, 0 }, + { -0.257377, 0.210690, 10.119086, 0 }, + { -0.256179, 0.198719, 10.093947, 0 }, + { -0.253785, 0.198719, 10.113101, 0 }, + { -0.254982, 0.215478, 10.081977, 0 }, + { -0.259771, 0.210690, 10.092751, 0 }, + { -0.264559, 0.214281, 10.090356, 0 }, + { -0.260968, 0.187945, 10.144226, 0 }, + { -0.268150, 0.245406, 10.073597, 0 }, + { -0.408211, 0.396240, 10.056837, 0 }, + { -2.020705, 2.340331, 10.170562, 0 }, + { -0.186748, 1.916557, 10.966634, 0 }, + { 7.234076, -2.675519, 16.133318, 0 }, + { 7.775165, 0.863109, 11.798618, 0 }, + { 3.503912, -1.510740, 2.634817, 0 }, + { -3.895364, -5.768825, 9.538493, 0 }, + { -4.587287, -2.717417, 26.975452, 0 }, + { -3.013101, 4.329911, 32.156502, 0 }, + { -4.693829, -1.854308, 19.993965, 0 }, + { -5.236115, -2.634817, 18.126490, 0 }, + { -6.558911, 1.010352, 20.283663, 0 }, + { -8.033738, 0.130484, 22.203812, 0 }, + { -7.487861, -0.525527, 18.705885, 0 }, + { -6.692986, 0.266953, 15.228310, 0 }, + { -6.151897, 0.128090, 10.176547, 0 }, + { -6.020216, 0.745793, 5.400118, 0 }, + { -5.798753, 1.690305, 1.695094, 0 }, + { -3.584117, 1.229422, -1.827972, 0 }, + { -0.386663, 1.133654, -4.835087, 0 }, + { 0.955286, 1.742978, -4.969162, 0 }, + { 3.201046, 1.059434, -6.075283, 0 }, + { 7.366954, -0.312443, -7.837414, 0 }, + { 8.429978, -0.656011, -6.296746, 0 }, + { 6.950363, -0.164003, -3.179498, 0 }, + { 6.801922, -0.415394, -0.955286, 0 }, + { 7.827837, -0.814028, 1.152807, 0 }, + { 7.793121, -0.723048, 3.940853, 0 }, + { 7.422020, -0.292092, 6.720520, 0 }, + { 7.978672, -0.298078, 7.856567, 0 }, + { 8.202530, -0.122104, 7.301113, 0 }, + { 7.778756, 0.360327, 6.107605, 0 }, + { 7.892480, 0.318429, 5.987895, 0 }, + { 8.950717, 0.108936, 6.327871, 0 }, + { 8.798685, 0.319626, 7.009021, 0 }, + { 7.748828, 0.839167, 7.133519, 0 }, + { 7.795516, 0.958877, 6.597219, 0 }, + { 7.850582, 1.035492, 5.942405, 0 }, + { 7.547716, 1.152807, 5.074507, 0 }, + { 7.116760, 1.128865, 4.546586, 0 }, + { 7.422020, 0.805648, 4.566936, 0 }, + { 7.937970, 0.517147, 4.827904, 0 }, + { 8.088805, 0.418985, 5.172669, 0 }, + { 8.329422, 0.415394, 5.573698, 0 }, + { 8.099579, 0.739808, 5.117603, 0 }, + { 7.973883, 0.805648, 4.387372, 0 }, + { 7.833823, 1.048660, 3.857056, 0 }, + { 8.100776, 1.177946, 3.950430, 0 }, + { 8.722071, 1.122880, 4.909307, 0 }, + { 9.400826, 0.921767, 5.566515, 0 }, + { 9.440331, 0.920570, 5.175064, 0 }, + { 8.723268, 1.022323, 4.551374, 0 }, + { 8.115141, 1.175552, 4.096477, 0 }, + { 8.135491, 1.387439, 3.754106, 0 }, + { 8.602361, 1.533485, 3.762486, 0 }, + { 8.884876, 1.289277, 4.268859, 0 }, + { 8.775940, 0.867898, 4.517856, 0 }, + { 8.434767, 0.647631, 4.377795, 0 }, + { 8.220486, 0.623689, 4.394554, 0 }, + { 7.817063, 0.945709, 4.226960, 0 }, + { 8.021768, 1.249772, 3.598483, 0 }, + { 9.108734, 0.667982, 3.156753, 0 }, + { 9.658203, 0.177171, 2.748542, 0 }, + { 9.301467, 0.393846, 2.639606, 0 }, + { 9.026134, 0.736217, 3.105278, 0 }, + { 8.865723, 0.814028, 3.799596, 0 }, + { 8.759181, 0.849941, 4.060563, 0 }, + { 8.493424, 0.964863, 4.404131, 0 }, + { 8.276750, 1.033097, 4.540600, 0 }, + { 8.324634, 0.908599, 4.672281, 0 }, + { 8.778335, 0.644040, 4.946417, 0 }, + { 8.558068, 0.827196, 5.007470, 0 }, + { 8.507790, 0.703895, 4.434059, 0 }, + { 8.688552, 0.684741, 3.661929, 0 }, + { 8.784320, 0.820014, 3.207031, 0 }, + { 8.844175, 0.839167, 3.385399, 0 }, + { 8.908818, 0.858321, 3.974372, 0 }, + { 9.044091, 0.907402, 4.442438, 0 }, + { 8.989024, 0.899022, 4.399343, 0 }, + { 8.925578, 0.815225, 4.141966, 0 }, + { 9.033317, 0.615309, 3.840297, 0 }, + { 9.083595, 0.436942, 3.727770, 0 }, + { 9.020149, 0.338779, 3.928882, 0 }, + { 8.930367, 0.299275, 4.174288, 0 }, + { 8.963885, 0.246603, 4.288013, 0 }, + { 8.842978, 0.304063, 4.236537, 0 }, + { 8.641865, 0.396240, 4.152740, 0 }, + { 8.591587, 0.466869, 4.163514, 0 }, + { 8.656230, 0.460884, 4.255691, 0 }, + { 8.836992, 0.398634, 4.118024, 0 }, + { 8.957899, 0.453701, 3.754106, 0 }, + { 9.045288, 0.502782, 3.326741, 0 }, + { 9.083595, 0.586579, 3.045423, 0 }, + { 9.033317, 0.705092, 3.004721, 0 }, + { 8.968674, 0.715866, 3.072956, 0 }, + { 8.899241, 0.684741, 3.071759, 0 }, + { 8.809459, 0.632069, 3.072956, 0 }, + { 8.832204, 0.585382, 3.138796, 0 }, + { 8.825022, 0.575805, 3.143585, 0 }, + { 8.761575, 0.556652, 3.064576, 0 }, + { 8.750801, 0.594959, 3.092109, 0 }, + { 8.817839, 0.633266, 3.129220, 0 }, + { 8.913607, 0.640449, 3.046620, 0 }, + { 8.998601, 0.658405, 2.869449, 0 }, + { 9.095566, 0.684741, 2.670730, 0 }, + { 9.133873, 0.694318, 2.789243, 0 }, + { 9.126691, 0.676362, 3.256112, 0 }, + { 9.041697, 0.723048, 3.632001, 0 }, + { 8.827415, 0.763750, 3.794807, 0 }, + { 8.853752, 0.694318, 3.775654, 0 }, + { 9.000996, 0.618901, 3.673900, 0 }, + { 9.066835, 0.561440, 3.708616, 0 }, + { 9.075215, 0.497994, 3.767274, 0 }, + { 9.064442, 0.417788, 3.775654, 0 }, + { 9.003389, 0.444124, 3.676294, 0 }, + { 8.943534, 0.500388, 3.551796, 0 }, + { 8.961491, 0.505176, 3.343500, 0 }, + { 8.789108, 0.600944, 3.191469, 0 }, + { 8.816642, 0.596156, 3.118446, 0 }, + { 8.889665, 0.549469, 3.131614, 0 }, + { 8.881285, 0.533907, 3.242944, 0 }, + { 8.783123, 0.590170, 3.416523, 0 }, + { 8.716085, 0.642843, 3.600877, 0 }, + { 8.719677, 0.612915, 3.694251, 0 }, + { 8.792700, 0.532710, 3.641578, 0 }, + { 8.895650, 0.470460, 3.475181, 0 }, + { 8.902833, 0.453701, 3.179498, 0 }, + { 8.833401, 0.399831, 2.855083, 0 }, + { 8.759181, 0.278924, 2.383426, 0 }, + { 8.670595, 0.118513, 1.875856, 0 }, + { 8.531732, -0.013168, 1.414972, 0 }, + { 8.376109, -0.057461, 1.115697, 0 }, + { 8.304283, -0.015562, 1.341949, 0 }, + { 7.916422, 0.159214, 1.878250, 0 }, + { 7.595600, 0.270545, 3.086124, 0 }, + { 7.516591, 0.349553, 4.906913, 0 }, + { 7.881707, 0.061052, 6.694183, 0 }, + { 8.112747, -0.235829, 7.243652, 0 }, + { 8.034935, -0.387860, 7.001838, 0 }, + { 8.052892, -0.222661, 6.254848, 0 }, + { 7.948744, 0.203507, 5.623976, 0 }, + { 7.327449, 0.853532, 5.892127, 0 }, + { 6.556517, 1.406592, 6.268016, 0 }, + { 6.993458, 1.375468, 6.548137, 0 }, + { 7.503423, 1.138442, 6.823470, 0 }, + { 7.237667, 1.118091, 7.408852, 0 }, + { 7.144293, 1.031900, 8.170208, 0 }, + { 7.127533, 0.927753, 8.361744, 0 }, + { 6.883325, 0.820014, 8.204924, 0 }, + { 6.708549, 0.644040, 7.923605, 0 }, + { 6.877340, 0.410605, 7.595600, 0 }, + { 7.054511, 0.339976, 7.395684, 0 }, + { 7.176615, 0.295684, 7.271185, 0 }, + { 7.182600, 0.259771, 7.201754, 0 }, + { 6.823470, 0.384269, 7.207739, 0 }, + { 6.624752, 0.464475, 7.419626, 0 }, + { 6.767207, 0.436942, 7.730872, 0 }, + { 6.834244, 0.386663, 7.971489, 0 }, + { 6.795937, 0.344765, 7.827837, 0 }, + { 6.531378, 0.404620, 7.354982, 0 }, + { 6.513421, 0.317232, 7.140702, 0 }, + { 6.649891, 0.192733, 7.065284, 0 }, + { 6.544546, 0.299275, 6.846215, 0 }, + { 6.555320, 0.381875, 6.678621, 0 }, + { 6.630737, 0.332794, 6.690592, 0 }, + { 6.636723, 0.199916, 6.915647, 0 }, + { 6.590036, 0.169988, 7.594403, 0 }, + { 6.248862, 0.393846, 8.506593, 0 }, + { 6.199781, 0.445321, 8.953111, 0 }, + { 6.538560, 0.023942, 8.977053, 0 }, + { 6.251256, 0.074220, 8.766363, 0 }, + { 6.154291, 0.337582, 8.178588, 0 }, + { 6.550531, 0.281319, 7.522577, 0 }, + { 6.397303, 0.652420, 7.284354, 0 }, + { 6.174642, 0.914584, 7.181403, 0 }, + { 6.265622, 0.825999, 6.584050, 0 }, + { 6.449975, 0.812831, 6.244074, 0 }, + { 6.738476, 0.641646, 6.549335, 0 }, + { 6.904873, 0.591367, 6.961137, 0 }, + { 6.669044, 0.671573, 7.244849, 0 }, + { 6.514618, 0.677559, 7.499832, 0 }, + { 6.716928, 0.464475, 7.510606, 0 }, + { 6.792346, 0.463278, 7.596797, 0 }, + { 6.734885, 0.585382, 7.791924, 0 }, + { 6.658270, 0.447715, 7.554898, 0 }, + { 6.463143, 0.486023, 7.091620, 0 }, + { 6.501450, 0.563834, 6.517013, 0 }, + { 6.488282, 0.654814, 6.062115, 0 }, + { 6.436807, 0.670376, 6.069297, 0 }, + { 6.479902, 0.659602, 6.549335, 0 }, + { 6.368572, 0.628478, 7.060496, 0 }, + { 6.446383, 0.487220, 7.497437, 0 }, + { 6.628343, 0.423773, 7.789530, 0 }, + { 6.636723, 0.460884, 7.996628, 0 }, + { 6.369769, 0.560243, 8.149857, 0 }, + { 6.105210, 0.602141, 8.106761, 0 }, + { 6.810302, 0.294487, 8.166616, 0 }, + { 7.140702, 0.201113, 8.110353, 0 }, + { 6.691789, 0.211887, 7.706930, 0 }, + { 6.524195, 0.271742, 7.422020, 0 }, + { 6.406879, 0.363918, 7.422020, 0 }, + { 6.278790, 0.423773, 7.556096, 0 }, + { 6.175839, 0.460884, 7.661440, 0 }, + { 6.229709, 0.451307, 7.507014, 0 }, + { 6.511027, 0.403423, 6.991064, 0 }, + { 6.872551, 0.345962, 6.734885, 0 }, + { 6.777980, 0.488417, 6.701366, 0 }, + { 6.730096, 0.620098, 6.682212, 0 }, + { 6.818682, 0.694318, 6.673833, 0 }, + { 6.897690, 0.634463, 6.702563, 0 }, + { 6.824667, 0.557849, 6.743265, 0 }, + { 6.700169, 0.621295, 6.815091, 0 }, + { 6.441595, 0.687135, 6.744462, 0 }, + { 6.476311, 0.812831, 6.872551, 0 }, + { 7.070073, 0.621295, 7.327449, 0 }, + { 6.791149, 0.446518, 7.169432, 0 }, + { 6.742067, 0.513556, 7.479481, 0 }, + { 6.738476, 0.420182, 7.603980, 0 }, + { 6.797134, 0.195127, 7.705733, 0 }, + { 6.882128, 0.363918, 7.593205, 0 }, + { 6.769601, 0.568623, 7.325055, 0 }, + { 6.915647, 0.465672, 7.016203, 0 }, + { 7.165841, 0.305261, 6.475114, 0 }, + { 7.277171, 0.234632, 5.893323, 0 }, + { 7.274777, 0.275333, 5.352234, 0 }, + { 6.994656, 0.428562, 5.149924, 0 }, + { 6.801922, 0.456095, 5.353431, 0 }, + { 6.751644, 0.354342, 5.864593, 0 }, + { 6.592430, 0.339976, 6.321885, 0 }, + { 6.416456, 0.262165, 6.567291, 0 }, + { 6.847412, -0.142455, 7.101197, 0 }, + { 7.248441, -0.061052, 7.084438, 0 }, + { 6.556517, 0.310049, 7.459130, 0 }, + { 6.555320, 0.251391, 7.558490, 0 }, + { 6.552926, 0.347159, 7.578840, 0 }, + { 6.534969, 0.442927, 7.498635, 0 }, + { 6.439201, 0.484826, 7.303507, 0 }, + { 6.555320, 0.341173, 7.278368, 0 }, + { 6.587642, 0.209493, 7.347800, 0 }, + { 6.563700, 0.135272, 7.492649, 0 }, + { 6.603204, 0.100556, 7.559687, 0 }, + { 6.515815, 0.198719, 7.558490, 0 }, + { 6.441595, 0.270545, 7.536942, 0 }, + { 6.330265, 0.298078, 7.629118, 0 }, + { 6.339842, 0.277727, 7.694959, 0 }, + { 6.260833, 0.245406, 7.636301, 0 }, + { 6.145912, 0.185551, 7.546519, 0 }, + { 6.068100, 0.132878, 7.322661, 0 }, + { 5.987895, 0.122104, 7.220907, 0 }, + { 5.989091, 0.123301, 7.357377, 0 }, + { 5.981909, 0.122104, 7.590811, 0 }, + { 6.020216, 0.088585, 7.677002, 0 }, + { 6.030990, 0.148440, 7.593205, 0 }, + { 6.063312, 0.219069, 7.480678, 0 }, + { 6.089648, 0.265756, 7.527365, 0 }, + { 6.050144, 0.359130, 7.862553, 0 }, + { 6.011837, 0.365116, 8.170208, 0 }, + { 6.011837, 0.265756, 8.222880, 0 }, + { 5.893323, 0.202310, 8.207318, 0 }, + { 5.845439, 0.137667, 8.021768, 0 }, + { 5.822695, 0.196324, 8.021768, 0 }, + { 5.906492, 0.239420, 8.250414, 0 }, + { 5.809526, 0.296881, 8.378503, 0 }, + { 5.810724, 0.222661, 8.389277, 0 }, + { 5.754460, 0.226252, 8.317451, 0 }, + { 5.809526, 0.104148, 8.396460, 0 }, + { 5.810724, 0.187945, 8.570039, 0 }, + { 6.063312, 0.287304, 8.530535, 0 }, + { 6.098028, 0.141258, 8.274356, 0 }, + { 5.651509, 0.290895, 8.311465, 0 }, + { 5.661086, 0.392649, 8.327028, 0 }, + { 5.258861, 0.590170, 8.374912, 0 }, + { 6.062115, 0.117316, 7.928393, 0 }, + { 6.623555, -0.246603, 7.491452, 0 }, + { 6.019019, 0.135272, 7.080847, 0 }, + { 6.084859, 0.463278, 7.062890, 0 }, + { 5.912477, 0.451307, 7.258018, 0 }, + { 5.827483, 0.532710, 7.372939, 0 }, + { 5.821497, 0.537498, 7.540533, 0 }, + { 5.737700, 0.536301, 7.648272, 0 }, + { 5.851425, 0.383072, 7.718901, 0 }, + { 6.072888, 0.365116, 7.699748, 0 }, + { 5.929236, 0.392649, 7.878115, 0 }, + { 5.967544, 0.354342, 8.107959, 0 }, + { 6.045355, 0.253785, 8.421598, 0 }, + { 5.923251, 0.323217, 8.574827, 0 }, + { 5.803541, 0.372298, 8.486242, 0 }, + { 5.785584, 0.416591, 8.215697, 0 }, + { 5.768825, 0.496797, 7.946350, 0 }, + { 5.838257, 0.527921, 7.711719, 0 }, + { 5.963953, 0.471657, 7.472299, 0 }, + { 5.986697, 0.430956, 7.435188, 0 }, + { 5.928040, 0.436942, 7.484270, 0 }, + { 5.907689, 0.472855, 7.449553, 0 }, + { 5.935222, 0.456095, 7.354982, 0 }, + { 5.959164, 0.450110, 7.420823, 0 }, + { 5.960361, 0.391452, 7.717704, 0 }, + { 5.880156, 0.399831, 7.902057, 0 }, + { 5.771219, 0.411802, 7.936773, 0 }, + { 5.997471, 0.266953, 8.137886, 0 }, + { 5.945996, 0.380678, 8.301888, 0 }, + { 5.877761, 0.434547, 8.265976, 0 }, + { 5.904098, 0.408211, 7.947547, 0 }, + { 5.918463, 0.432153, 7.615951, 0 }, + { 5.869381, 0.438139, 7.486664, 0 }, + { 5.837060, 0.451307, 7.556096, 0 }, + { 5.900506, 0.465672, 7.654258, 0 }, + { 5.870579, 0.454898, 7.651864, 0 }, + { 5.875367, 0.454898, 7.615951, 0 }, + { 5.887338, 0.451307, 7.697353, 0 }, + { 5.850228, 0.456095, 7.779953, 0 }, + { 5.858608, 0.477643, 7.884101, 0 }, + { 5.749671, 0.506373, 7.787136, 0 }, + { 5.683831, 0.507570, 7.660243, 0 }, + { 5.740095, 0.469263, 7.811078, 0 }, + { 5.766431, 0.405817, 8.002614, 0 }, + { 5.714955, 0.442927, 8.042118, 0 }, + { 5.723335, 0.399831, 8.002614, 0 }, + { 5.712561, 0.343568, 7.995431, 0 }, + { 5.741292, 0.323217, 8.110353, 0 }, + { 5.766431, 0.349553, 8.237246, 0 }, + { 5.704182, 0.367510, 8.276750, 0 }, + { 5.651509, 0.348356, 8.161828, 0 }, + { 5.655100, 0.367510, 7.977475, 0 }, + { 5.770022, 0.269348, 8.037330, 0 }, + { 5.765234, 0.149638, 8.125915, 0 }, + { 5.671860, 0.073023, 7.973883, 0 }, + { 5.667071, 0.105345, 7.836217, 0 }, + { 5.662283, 0.092177, 7.824246, 0 }, + { 5.702984, 0.031125, 7.970292, 0 }, + { 5.731715, -0.005986, 8.169010, 0 }, + { 5.705379, -0.038307, 8.178588, 0 }, + { 5.635947, -0.082600, 8.060075, 0 }, + { 5.614399, -0.087388, 7.846991, 0 }, + { 5.607216, -0.051475, 7.807487, 0 }, + { 5.610808, -0.033519, 7.864947, 0 }, + { 5.594049, 0.014365, 7.959518, 0 }, + { 5.595245, 0.070629, 8.085214, 0 }, + { 5.577289, 0.046687, 8.267173, 0 }, + { 5.512646, -0.061052, 8.195347, 0 }, + { 5.414484, -0.068235, 7.988248, 0 }, + { 5.358220, 0.023942, 7.862553, 0 }, + { 5.412089, 0.094571, 7.925999, 0 }, + { 5.420469, 0.159214, 8.106761, 0 }, + { 5.276817, 0.208295, 8.341393, 0 }, + { 5.264846, 0.239420, 8.215697, 0 }, + { 5.281605, 0.105345, 8.564054, 0 }, + { 5.311533, -0.020351, 8.683764, 0 }, + { 5.209779, 0.087388, 8.489834, 0 }, + { 5.149924, 0.135272, 8.765166, 0 }, + { 5.169078, 0.017957, 9.282313, 0 }, + { 5.274423, -0.105345, 9.628276, 0 }, + { 5.270832, -0.059855, 9.247598, 0 }, + { 5.166684, 0.098162, 8.629894, 0 }, + { 5.128376, 0.126893, 8.294706, 0 }, + { 5.119997, 0.088585, 8.373714, 0 }, + { 5.146333, 0.090980, 8.540112, 0 }, + { 5.112814, 0.226252, 8.293509, 0 }, + { 5.086478, 0.238223, 8.079228, 0 }, + { 5.076901, 0.137667, 8.086411, 0 }, + { 5.064930, 0.064643, 8.396460, 0 }, + { 5.090069, 0.101754, 8.791503, 0 }, + { 5.090069, 0.272939, 9.018951, 0 }, + { 5.106829, 0.399831, 8.947125, 0 }, + { 5.129574, 0.401029, 8.738831, 0 }, + { 5.143939, 0.233435, 8.713691, 0 }, + { 5.165487, 0.124498, 8.570039, 0 }, + { 5.170275, 0.147243, 8.276750, 0 }, + { 5.114011, 0.207098, 7.818260, 0 }, + { 5.033806, 0.308852, 7.491452, 0 }, + { 5.043383, 0.314837, 7.789530, 0 }, + { 5.061339, 0.219069, 8.386883, 0 }, + { 5.069719, 0.137667, 8.644259, 0 }, + { 5.058945, 0.147243, 8.481454, 0 }, + { 5.007470, 0.186748, 8.107959, 0 }, + { 4.957191, 0.214281, 8.024161, 0 }, + { 5.048171, 0.130484, 8.451527, 0 }, + { 5.088872, 0.058658, 8.924380, 0 }, + { 5.104434, -0.016759, 9.154224, 0 }, + { 5.117603, -0.027533, 8.935155, 0 }, + { 5.018243, 0.071826, 8.637076, 0 }, + { 4.983528, 0.090980, 8.604755, 0 }, + { 5.019441, 0.026336, 8.650245, 0 }, + { 5.030214, -0.013168, 8.646653, 0 }, + { 4.939235, -0.026336, 8.565250, 0 }, + { 4.879380, -0.089783, 8.562857, 0 }, + { 4.832693, -0.186748, 8.906425, 0 }, + { 4.851846, -0.294487, 9.361322, 0 }, + { 4.910504, -0.284910, 9.572012, 0 }, + { 4.920081, -0.166397, 9.233232, 0 }, + { 4.865015, -0.051475, 8.621514, 0 }, + { 4.821919, -0.007183, 8.482651, 0 }, + { 4.851846, -0.021548, 8.792700, 0 }, + { 4.916490, -0.056264, 9.081201, 0 }, + { 4.939235, -0.034716, 8.680172, 0 }, + { 4.878182, 0.039504, 8.130703, 0 }, + { 4.825510, 0.070629, 8.079228, 0 }, + { 4.854240, 0.033519, 8.445540, 0 }, + { 4.932052, -0.016759, 8.767561, 0 }, + { 4.988316, -0.080206, 8.864526, 0 }, + { 5.024229, -0.152032, 8.710100, 0 }, + { 5.026623, -0.175974, 8.593981, 0 }, + { 5.011061, -0.119710, 8.465892, 0 }, + { 5.051762, -0.058658, 8.503001, 0 }, + { 5.104434, 0.028730, 8.389277, 0 }, + { 5.108026, 0.174777, 8.304283, 0 }, + { 5.121194, 0.207098, 8.368926, 0 }, + { 5.137953, 0.177171, 8.186967, 0 }, + { 5.123588, 0.141258, 8.036133, 0 }, + { 5.098449, 0.186748, 8.031344, 0 }, + { 5.036200, 0.240617, 8.049300, 0 }, + { 4.977542, 0.316034, 8.190558, 0 }, + { 4.978739, 0.294487, 8.428782, 0 }, + { 5.046974, 0.195127, 8.704114, 0 }, + { 5.042185, 0.211887, 8.719677, 0 }, + { 4.927264, 0.299275, 8.538915, 0 }, + { 4.918884, 0.241814, 8.495819, 0 }, + { 4.897336, 0.189142, 8.492228, 0 }, + { 4.878182, 0.237026, 8.601164, 0 }, + { 4.818327, 0.262165, 8.705312, 0 }, + { 4.871000, 0.172382, 8.791503, 0 }, + { 4.924870, 0.119710, 8.872906, 0 }, + { 4.873394, 0.243011, 8.825022, 0 }, + { 4.832693, 0.408211, 8.659822, 0 }, + { 4.838678, 0.367510, 8.619121, 0 }, + { 4.904519, 0.169988, 8.809459, 0 }, + { 4.926067, 0.071826, 9.058456, 0 }, + { 4.940432, 0.058658, 8.823824, 0 }, + { 4.930855, 0.167594, 8.331817, 0 }, + { 4.918884, 0.266953, 8.265976, 0 }, + { 4.941629, 0.207098, 8.900438, 0 }, + { 4.957191, 0.129287, 9.339774, 0 }, + { 4.915293, 0.180762, 9.089581, 0 }, + { 4.930855, 0.190339, 8.826219, 0 }, + { 5.080492, 0.038307, 8.766363, 0 }, + { 5.204991, -0.108936, 8.631091, 0 }, + { 5.202597, -0.047884, 8.157040, 0 }, + { 5.157107, 0.095768, 7.870933, 0 }, + { 5.164289, 0.168791, 8.019373, 0 }, + { 5.199006, 0.167594, 8.428782, 0 }, + { 5.215765, 0.180762, 8.804670, 0 }, + { 5.201400, 0.278924, 8.614332, 0 }, + { 5.171472, 0.433350, 8.225274, 0 }, + { 5.199006, 0.466869, 8.068454, 0 }, + { 5.245692, 0.434547, 8.081622, 0 }, + { 5.252875, 0.493205, 8.092396, 0 }, + { 5.194217, 0.633266, 8.359349, 0 }, + { 5.155910, 0.772130, 8.494622, 0 }, + { 5.196611, 0.809240, 8.324634, 0 }, + { 5.245692, 0.724246, 8.206120, 0 }, + { 5.252875, 0.677559, 8.295903, 0 }, + { 5.234919, 0.689530, 8.449132, 0 }, + { 5.256466, 0.666785, 8.635880, 0 }, + { 5.276817, 0.672770, 8.653836, 0 }, + { 5.300759, 0.682347, 8.694537, 0 }, + { 5.352234, 0.640449, 8.677778, 0 }, + { 5.373782, 0.659602, 8.445540, 0 }, + { 5.371388, 0.752976, 8.093594, 0 }, + { 5.348643, 0.889445, 7.916422, 0 }, + { 5.337869, 0.974439, 8.097184, 0 }, + { 5.346249, 0.991199, 8.227669, 0 }, + { 5.382162, 0.978031, 8.289918, 0 }, + { 5.436031, 0.922964, 8.264779, 0 }, + { 5.408498, 0.940921, 8.136689, 0 }, + { 5.376176, 0.939724, 8.165420, 0 }, + { 5.364205, 0.924161, 8.331817, 0 }, + { 5.351037, 0.873883, 8.446738, 0 }, + { 5.334278, 0.855927, 8.334210, 0 }, + { 5.292379, 0.861912, 8.178588, 0 }, + { 5.298365, 0.858321, 8.146266, 0 }, + { 5.319912, 0.841561, 8.136689, 0 }, + { 5.353431, 0.793677, 8.121126, 0 }, + { 5.378571, 0.736217, 8.218092, 0 }, + { 5.397724, 0.694318, 8.354561, 0 }, + { 5.367796, 0.709880, 8.420402, 0 }, + { 5.335475, 0.749385, 8.528141, 0 }, + { 5.313927, 0.818816, 8.493424, 0 }, + { 5.306745, 0.889445, 8.315057, 0 }, + { 5.333081, 0.893037, 8.216895, 0 }, + { 5.345052, 0.899022, 8.208515, 0 }, + { 5.348643, 0.920570, 8.322240, 0 }, + { 5.346249, 0.955286, 8.494622, 0 }, + { 5.325898, 0.984016, 8.801080, 0 }, + { 5.355825, 0.998381, 9.132676, 0 }, + { 5.388147, 0.967257, 9.349351, 0 }, + { 5.489901, 0.889445, 9.421177, 0 }, + { 5.553347, 0.900219, 9.010572, 0 }, + { 5.532996, 1.004367, 8.176193, 0 }, + { 5.509054, 1.109712, 7.471101, 0 }, + { 5.504266, 1.175552, 7.400473, 0 }, + { 5.482718, 1.159990, 7.684185, 0 }, + { 5.443214, 1.177946, 8.027753, 0 }, + { 5.426455, 1.201888, 8.292312, 0 }, + { 5.492295, 1.139639, 8.359349, 0 }, + { 5.532996, 1.092952, 8.263581, 0 }, + { 5.522223, 1.072602, 7.959518, 0 }, + { 5.504266, 1.033097, 7.606374, 0 }, + { 5.524617, 0.958877, 7.461524, 0 }, + { 5.505463, 0.876277, 7.580038, 0 }, + { 5.458776, 0.823605, 7.835020, 0 }, + { 5.432440, 0.756567, 8.016979, 0 }, + { 5.386950, 0.760159, 8.174996, 0 }, + { 5.400118, 0.748188, 8.362941, 0 }, + { 5.449199, 0.687135, 8.324634, 0 }, + { 5.426455, 0.701501, 7.993037, 0 }, + { 5.407301, 0.751779, 7.637498, 0 }, + { 5.455185, 0.737414, 7.868538, 0 }, + { 5.456382, 0.735019, 8.342590, 0 }, + { 5.409695, 0.805648, 8.420402, 0 }, + { 5.379767, 0.878671, 8.323437, 0 }, + { 5.433637, 0.877474, 8.230062, 0 }, + { 5.477930, 0.864306, 8.248019, 0 }, + { 5.511448, 0.831985, 8.370124, 0 }, + { 5.525814, 0.817619, 8.439555, 0 }, + { 5.498281, 0.797269, 8.486242, 0 }, + { 5.485112, 0.806845, 8.465892, 0 }, + { 5.480324, 0.830787, 8.364138, 0 }, + { 5.485112, 0.831985, 8.337802, 0 }, + { 5.487506, 0.854729, 8.340196, 0 }, + { 5.434834, 0.873883, 8.372518, 0 }, + { 5.397724, 0.854729, 8.346182, 0 }, + { 5.392936, 0.869095, 8.216895, 0 }, + { 5.373782, 0.891840, 8.018176, 0 }, + { 5.401315, 0.872686, 7.902057, 0 }, + { 5.448002, 0.833182, 7.929591, 0 }, + { 5.425257, 0.835576, 8.146266, 0 }, + { 5.413286, 0.849941, 8.409628, 0 }, + { 5.421666, 0.837970, 8.495819, 0 }, + { 5.434834, 0.802057, 8.402445, 0 }, + { 5.456382, 0.772130, 8.238442, 0 }, + { 5.482718, 0.749385, 8.231260, 0 }, + { 5.497083, 0.744596, 8.304283, 0 }, + { 5.479127, 0.781706, 8.298298, 0 }, + { 5.432440, 0.882263, 8.295903, 0 }, + { 5.404907, 0.958877, 8.201332, 0 }, + { 5.397724, 0.944512, 8.110353, 0 }, + { 5.394133, 0.920570, 8.216895, 0 }, + { 5.437228, 0.899022, 8.328225, 0 }, + { 5.474339, 0.902613, 8.413219, 0 }, + { 5.529405, 0.889445, 8.447935, 0 }, + { 5.590457, 0.873883, 8.355759, 0 }, + { 5.612005, 0.877474, 8.292312, 0 }, + { 5.613202, 0.870292, 8.209712, 0 }, + { 5.585669, 0.913387, 8.025358, 0 }, + { 5.511448, 0.933738, 7.991840, 0 }, + { 5.475535, 0.949300, 8.026556, 0 }, + { 5.463564, 0.999579, 8.031344, 0 }, + { 5.469550, 0.994790, 7.918817, 0 }, + { 5.504266, 0.974439, 7.881707, 0 }, + { 5.546165, 0.991199, 7.955927, 0 }, + { 5.553347, 0.997184, 8.128309, 0 }, + { 5.567712, 1.010352, 8.230062, 0 }, + { 5.553347, 1.048660, 8.279144, 0 }, + { 5.578486, 1.033097, 8.268370, 0 }, + { 5.571303, 1.016338, 8.101973, 0 }, + { 5.543770, 0.985213, 7.933182, 0 }, + { 5.550953, 0.909796, 7.971489, 0 }, + { 5.547361, 0.855927, 7.951138, 0 }, + { 5.540179, 0.840364, 7.978672, 0 }, + { 5.523419, 0.848744, 8.152251, 0 }, + { 5.491098, 0.853532, 8.298298, 0 }, + { 5.420469, 0.901416, 8.333014, 0 }, + { 5.403709, 0.937329, 8.419205, 0 }, + { 5.440820, 0.964863, 8.601164, 0 }, + { 5.465959, 0.991199, 8.426387, 0 }, + { 5.457579, 1.051054, 8.109156, 0 }, + { 5.437228, 1.104923, 7.977475, 0 }, + { 5.428849, 1.102529, 8.027753, 0 }, + { 5.433637, 1.090558, 8.195347, 0 }, + { 5.432440, 1.100135, 8.276750, 0 }, + { 5.461170, 1.134851, 8.309072, 0 }, + { 5.511448, 1.119289, 8.292312, 0 }, + { 5.540179, 1.089361, 8.316254, 0 }, + { 5.518631, 1.103726, 8.358152, 0 }, + { 5.528208, 1.112106, 8.343787, 0 }, + { 5.527011, 1.094149, 8.257596, 0 }, + { 5.495886, 1.116894, 8.154645, 0 }, + { 5.510252, 1.092952, 8.208515, 0 }, + { 5.538982, 1.058236, 8.158237, 0 }, + { 5.511448, 1.088164, 7.948744, 0 }, + { 5.515040, 1.084573, 7.852976, 0 }, + { 5.507857, 1.104923, 7.959518, 0 }, + { 5.468353, 1.138442, 8.188165, 0 }, + { 5.468353, 1.148019, 8.327028, 0 }, + { 5.481521, 1.133654, 8.289918, 0 }, + { 5.511448, 1.120486, 8.226472, 0 }, + { 5.530602, 1.086967, 8.198938, 0 }, + { 5.529405, 1.065419, 8.166616, 0 }, + { 5.469550, 1.060631, 8.221684, 0 }, + { 5.440820, 1.053448, 8.240837, 0 }, + { 5.396527, 1.053448, 8.213304, 0 }, + { 5.386950, 1.055842, 8.234851, 0 }, + { 5.421666, 1.046265, 8.246822, 0 }, + { 5.431243, 1.029506, 8.155843, 0 }, + { 5.298365, 1.292868, 5.756854, 0 }, + { 5.191823, 1.255758, 8.088805, 0 }, + { 5.204991, 1.169567, 10.260345, 0 } }; const size_t kBodyDetectOffOnTestDataLength = ARRAY_SIZE(kBodyDetectOffOnTestData); const struct body_detect_test_data kBodyDetectOnOffTestData[] = { - {-6.536166, 0.264559, 7.560884, 0}, - {-6.253651, 0.108936, 8.167813, 0}, - {-5.890929, -0.029928, 8.061272, 0}, - {-5.833468, -0.045490, 8.250414, 0}, - {-5.932828, 0.038307, 8.573630, 0}, - {-5.995077, 0.104148, 8.634683, 0}, - {-6.080071, 0.181959, 8.317451, 0}, - {-6.069297, 0.177171, 8.151054, 0}, - {-5.978318, 0.113724, 8.407233, 0}, - {-5.895718, 0.033519, 8.592784, 0}, - {-5.828680, -0.022745, 8.299495, 0}, - {-5.768825, -0.070629, 7.958321, 0}, - {-5.770022, -0.089783, 8.028950, 0}, - {-5.832272, -0.074220, 8.360547, 0}, - {-5.880156, -0.067038, 8.488636, 0}, - {-5.987895, -0.017957, 8.342590, 0}, - {-6.148306, 0.014365, 8.317451, 0}, - {-6.337448, 0.102951, 8.492228, 0}, - {-6.411668, 0.148440, 8.571237, 0}, - {-6.341039, 0.099359, 8.250414, 0}, - {-6.232103, 0.067038, 7.899663, 0}, - {-6.172248, 0.100556, 8.152251, 0}, - {-6.095634, 0.111330, 8.632288, 0}, - {-6.033384, 0.126893, 8.614332, 0}, - {-5.936419, 0.131681, 8.136689, 0}, - {-5.931631, 0.205901, 7.739252, 0}, - {-5.986697, 0.271742, 7.870933, 0}, - {-6.040567, 0.250194, 8.099579, 0}, - {-6.077677, 0.244208, 8.191755, 0}, - {-6.071692, 0.277727, 8.146266, 0}, - {-5.953178, 0.292092, 8.025358, 0}, - {-5.847834, 0.330400, 7.942759, 0}, - {-5.776008, 0.392649, 8.036133, 0}, - {-5.680240, 0.417788, 7.892480, 0}, - {-5.617990, 0.458489, 7.609965, 0}, - {-5.550953, 0.496797, 7.418429, 0}, - {-5.301956, 0.369904, 8.050498, 0}, - {-5.276817, 0.290895, 9.167392, 0}, - {-5.890929, 0.215478, 9.044091, 0}, - {-6.495465, 0.108936, 9.111129, 0}, - {-6.545743, -0.049081, 9.390053, 0}, - {-5.966347, -0.161609, 9.362519, 0}, - {-5.325898, -0.117316, 8.969871, 0}, - {-5.263649, 0.105345, 8.404840, 0}, - {-5.620385, 0.336385, 8.085214, 0}, - {-5.886141, 0.472855, 8.037330, 0}, - {-5.704182, 0.427365, 8.032541, 0}, - {-5.359417, 0.301669, 7.813472, 0}, - {-5.331883, 0.329203, 7.632710, 0}, - {-5.483915, 0.433350, 7.621936, 0}, - {-5.862199, 0.703895, 8.079228, 0}, - {-5.808330, 0.616507, 9.142253, 0}, - {-5.513843, 0.481234, 9.751576, 0}, - {-5.365402, 0.470460, 9.706087, 0}, - {-5.378571, 0.440533, 9.333789, 0}, - {-5.637144, 0.565031, 8.905227, 0}, - {-5.776008, 0.560243, 8.019373, 0}, - {-5.779599, 0.676362, 7.132322, 0}, - {-5.549756, 0.760159, 7.116760, 0}, - {-5.303153, 0.730231, 7.817063, 0}, - {-5.206188, 0.831985, 8.506593, 0}, - {-5.151122, 0.725443, 8.941140, 0}, - {-5.292379, 0.556652, 9.176969, 0}, - {-5.622779, 0.563834, 9.362519, 0}, - {-5.481521, 0.433350, 9.410403, 0}, - {-5.045777, -0.074220, 9.109931, 0}, - {-5.035003, -0.328005, 8.900438, 0}, - {-5.307941, -0.389058, 9.000996, 0}, - {-5.561727, -0.269348, 9.169786, 0}, - {-5.603625, 0.213084, 9.216474, 0}, - {-5.357023, 0.697909, 9.339774, 0}, - {-5.081690, 0.764947, 9.429557, 0}, - {-5.063733, 0.520739, 9.349351, 0}, - {-5.212173, 0.463278, 9.210487, 0}, - {-5.079296, 0.622492, 9.057259, 0}, - {-4.827904, 0.758961, 8.755589, 0}, - {-4.689041, 0.723048, 8.749604, 0}, - {-4.681858, 0.731428, 9.129085, 0}, - {-4.598061, 0.723048, 9.536098, 0}, - {-4.378992, 0.730231, 9.668977, 0}, - {-4.214989, 0.672770, 9.102749, 0}, - {-4.241325, 0.641646, 8.643063, 0}, - {-4.289209, 0.708683, 8.941140, 0}, - {-4.304772, 0.984016, 9.394841, 0}, - {-4.106053, 0.980425, 9.239218, 0}, - {-3.926488, 0.615309, 8.754393, 0}, - {-4.012679, 0.414197, 8.646653, 0}, - {-4.191047, 0.730231, 9.080004, 0}, - {-4.211398, 1.057039, 9.763548, 0}, - {-4.055775, 0.944512, 9.933537, 0}, - {-3.976766, 0.493205, 9.303862, 0}, - {-4.319137, 0.397437, 8.835795, 0}, - {-4.368218, 0.577002, 9.014163, 0}, - {-4.213792, 0.700303, 9.281116, 0}, - {-4.164711, 0.563834, 9.527719, 0}, - {-4.132390, 0.458489, 9.472652, 0}, - {-4.106053, 0.392649, 9.238021, 0}, - {-4.090491, 0.524330, 9.093172, 0}, - {-4.052184, 0.738611, 9.153027, 0}, - {-4.015073, 0.524330, 9.047682, 0}, - {-4.149149, 0.454898, 8.930367, 0}, - {-4.250902, 0.724246, 9.131479, 0}, - {-4.231749, 0.701501, 9.166195, 0}, - {-4.356247, 0.757764, 9.208094, 0}, - {-4.443635, 0.785298, 9.235627, 0}, - {-4.355050, 0.804451, 9.149436, 0}, - {-4.307166, 0.567425, 9.187743, 0}, - {-4.550177, 0.476446, 9.249992, 0}, - {-4.790794, 0.457292, 9.175772, 0}, - {-4.935644, 0.417788, 9.200911, 0}, - {-4.940432, 0.588973, 9.419980, 0}, - {-4.709392, 0.357933, 9.624684, 0}, - {-4.763261, 0.093374, 9.773125, 0}, - {-5.021835, 0.171185, 9.756365, 0}, - {-5.087675, 0.294487, 9.680948, 0}, - {-4.916490, 0.357933, 9.610319, 0}, - {-4.729742, 0.360327, 9.296679, 0}, - {-4.635171, 0.266953, 8.780728, 0}, - {-4.843467, 0.410605, 8.383291, 0}, - {-4.898533, 0.500388, 8.177390, 0}, - {-4.692632, 0.489614, 8.313860, 0}, - {-4.566936, 0.451307, 8.595179, 0}, - {-4.624397, 0.457292, 8.774743, 0}, - {-4.781218, 0.441730, 8.777138, 0}, - {-4.916490, 0.410605, 8.816642, 0}, - {-5.014652, 0.482431, 8.795094, 0}, - {-4.830298, 0.306458, 8.991419, 0}, - {-5.154713, 0.448913, 8.974659, 0}, - {-5.114011, 0.424971, 8.789108, 0}, - {-4.894942, 0.238223, 8.692143, 0}, - {-4.979936, 0.184353, 8.980644, 0}, - {-5.267240, 0.381875, 9.326607, 0}, - {-5.289985, 0.413000, 9.498989, 0}, - {-5.128376, 0.320823, 9.273934, 0}, - {-4.978739, 0.312443, 8.930367, 0}, - {-5.054156, 0.391452, 8.816642, 0}, - {-5.224144, 0.409408, 8.898045, 0}, - {-5.287591, 0.392649, 8.862131, 0}, - {-5.182246, 0.426168, 8.808262, 0}, - {-5.039791, 0.471657, 8.797488, 0}, - {-4.969162, 0.490811, 8.793897, 0}, - {-5.032609, 0.511162, 8.804670, 0}, - {-5.021835, 0.465672, 8.822627, 0}, - {-4.967965, 0.496797, 8.820233, 0}, - {-4.969162, 0.571017, 8.796291, 0}, - {-4.904519, 0.560243, 8.785517, 0}, - {-4.750093, 0.547075, 8.775940, 0}, - {-4.687844, 0.500388, 8.554477, 0}, - {-4.741713, 0.487220, 8.224077, 0}, - {-4.880577, 0.569820, 8.147463, 0}, - {-4.959586, 0.610521, 8.506593, 0}, - {-4.977542, 0.555454, 8.856146, 0}, - {-4.910504, 0.424971, 8.870511, 0}, - {-4.947615, 0.316034, 8.845372, 0}, - {-5.177458, 0.336385, 9.156618, 0}, - {-5.345052, 0.371101, 9.455894, 0}, - {-5.370191, 0.402226, 9.381673, 0}, - {-5.357023, 0.372298, 9.232036, 0}, - {-5.309139, 0.289698, 9.148238, 0}, - {-5.236115, 0.247800, 9.085989, 0}, - {-5.159501, 0.211887, 9.010572, 0}, - {-5.081690, 0.173579, 8.878891, 0}, - {-5.049368, 0.208295, 8.710100, 0}, - {-5.026623, 0.229843, 8.664610, 0}, - {-5.032609, 0.237026, 8.772349, 0}, - {-4.967965, 0.233435, 8.868117, 0}, - {-4.844664, 0.164003, 8.799882, 0}, - {-4.906913, 0.155623, 8.500607, 0}, - {-5.141545, 0.264559, 8.359349, 0}, - {-5.264846, 0.310049, 8.640668, 0}, - {-5.348643, 0.306458, 8.961491, 0}, - {-5.366600, 0.301669, 8.968674, 0}, - {-5.404907, 0.298078, 8.802277, 0}, - {-5.386950, 0.259771, 8.801080, 0}, - {-5.335475, 0.208295, 8.759181, 0}, - {-5.300759, 0.174777, 8.723268, 0}, - {-5.237313, 0.147243, 8.762773, 0}, - {-5.303153, 0.185551, 8.772349, 0}, - {-5.394133, 0.204704, 8.888468, 0}, - {-5.383359, 0.167594, 8.965082, 0}, - {-5.257663, 0.110133, 8.893256, 0}, - {-5.116405, 0.039504, 8.738831, 0}, - {-5.194217, 0.044293, 8.644259, 0}, - {-5.336672, 0.111330, 8.772349, 0}, - {-5.389344, 0.132878, 8.972264, 0}, - {-5.400118, 0.136469, 8.959097, 0}, - {-5.455185, 0.185551, 8.850161, 0}, - {-5.519828, 0.210690, 8.804670, 0}, - {-5.555741, 0.210690, 8.898045, 0}, - {-5.507857, 0.222661, 8.835795, 0}, - {-5.402513, 0.205901, 8.598769, 0}, - {-5.368994, 0.257377, 8.353364, 0}, - {-5.437228, 0.366313, 8.394066, 0}, - {-5.401315, 0.345962, 8.656230, 0}, - {-5.341460, 0.350750, 8.723268, 0}, - {-5.272028, 0.362721, 8.585602, 0}, - {-5.282803, 0.387860, 8.337802, 0}, - {-5.285197, 0.420182, 8.268370, 0}, - {-5.250481, 0.415394, 8.337802, 0}, - {-5.185837, 0.379481, 8.416810, 0}, - {-5.161895, 0.356736, 8.468286, 0}, - {-5.203794, 0.344765, 8.577222, 0}, - {-5.272028, 0.306458, 8.719677, 0}, - {-5.315124, 0.271742, 8.868117, 0}, - {-5.337869, 0.296881, 8.939943, 0}, - {-5.376176, 0.299275, 8.894453, 0}, - {-5.442017, 0.318429, 8.793897, 0}, - {-5.452791, 0.331597, 8.714889, 0}, - {-5.412089, 0.289698, 8.700523, 0}, - {-5.406104, 0.251391, 8.773546, 0}, - {-5.368994, 0.252588, 8.866920, 0}, - {-5.323504, 0.240617, 8.942337, 0}, - {-5.333081, 0.231040, 9.015361, 0}, - {-5.377373, 0.231040, 8.980644, 0}, - {-5.450397, 0.292092, 8.865723, 0}, - {-5.483915, 0.336385, 8.750801, 0}, - {-5.474339, 0.355539, 8.653836, 0}, - {-5.404907, 0.342371, 8.593981, 0}, - {-5.243298, 0.234632, 8.598769, 0}, - {-5.164289, 0.198719, 8.635880, 0}, - {-5.214568, 0.248997, 8.646653, 0}, - {-5.316321, 0.288501, 8.589192, 0}, - {-5.452791, 0.343568, 8.579616, 0}, - {-5.509054, 0.366313, 8.670595, 0}, - {-5.474339, 0.319626, 8.686158, 0}, - {-5.384556, 0.275333, 8.689749, 0}, - {-5.365402, 0.268150, 8.750801, 0}, - {-5.437228, 0.357933, 8.748407, 0}, - {-5.470747, 0.402226, 8.730451, 0}, - {-5.386950, 0.362721, 8.672990, 0}, - {-5.339066, 0.363918, 8.700523, 0}, - {-5.295970, 0.398634, 8.793897, 0}, - {-5.307941, 0.413000, 8.899241, 0}, - {-5.295970, 0.392649, 8.924380, 0}, - {-5.287591, 0.405817, 8.936352, 0}, - {-5.269634, 0.417788, 8.896848, 0}, - {-5.342658, 0.471657, 8.640668, 0}, - {-5.464762, 0.557849, 8.434767, 0}, - {-5.467156, 0.575805, 8.456315, 0}, - {-5.443214, 0.561440, 8.497016, 0}, - {-5.440820, 0.574608, 8.524549, 0}, - {-5.438426, 0.598550, 8.480257, 0}, - {-5.348643, 0.553060, 8.530535, 0}, - {-5.238510, 0.509965, 8.638274, 0}, - {-5.155910, 0.445321, 8.657428, 0}, - {-5.111617, 0.395043, 8.583207, 0}, - {-5.115209, 0.365116, 8.610741, 0}, - {-5.176260, 0.344765, 8.625106, 0}, - {-5.254072, 0.373495, 8.711297, 0}, - {-5.267240, 0.379481, 8.808262, 0}, - {-5.238510, 0.329203, 8.795094, 0}, - {-5.266043, 0.282516, 8.694537, 0}, - {-5.410892, 0.308852, 8.599967, 0}, - {-5.538982, 0.337582, 8.520958, 0}, - {-5.544967, 0.344765, 8.590390, 0}, - {-5.458776, 0.276530, 8.730451, 0}, - {-5.408498, 0.211887, 8.729254, 0}, - {-5.450397, 0.195127, 8.633486, 0}, - {-5.509054, 0.216675, 8.659822, 0}, - {-5.483915, 0.190339, 8.823824, 0}, - {-5.430046, 0.169988, 9.004586, 0}, - {-5.392936, 0.186748, 9.078807, 0}, - {-5.406104, 0.197522, 9.024938, 0}, - {-5.462368, 0.269348, 8.857343, 0}, - {-5.462368, 0.290895, 8.724465, 0}, - {-5.409695, 0.284910, 8.667005, 0}, - {-5.389344, 0.288501, 8.643063, 0}, - {-5.354629, 0.284910, 8.577222, 0}, - {-5.329489, 0.287304, 8.591587, 0}, - {-5.280408, 0.282516, 8.658625, 0}, - {-5.206188, 0.225055, 8.695735, 0}, - {-5.169078, 0.235829, 8.741224, 0}, - {-5.181049, 0.256179, 8.693340, 0}, - {-5.245692, 0.262165, 8.619121, 0}, - {-5.334278, 0.257377, 8.613134, 0}, - {-5.388147, 0.248997, 8.681370, 0}, - {-5.376176, 0.240617, 8.742421, 0}, - {-5.360614, 0.199916, 8.707705, 0}, - {-5.443214, 0.190339, 8.631091, 0}, - {-5.489901, 0.172382, 8.549688, 0}, - {-5.524617, 0.192733, 8.529338, 0}, - {-5.518631, 0.189142, 8.562857, 0}, - {-5.479127, 0.158017, 8.555674, 0}, - {-5.499477, 0.140061, 8.599967, 0}, - {-5.519828, 0.130484, 8.643063, 0}, - {-5.493492, 0.090980, 8.652639, 0}, - {-5.458776, 0.074220, 8.610741, 0}, - {-5.483915, 0.107739, 8.635880, 0}, - {-5.445608, 0.087388, 8.746013, 0}, - {-5.422863, 0.052672, 8.787911, 0}, - {-5.402513, 0.032322, 8.768758, 0}, - {-5.373782, -0.007183, 8.802277, 0}, - {-5.371388, -0.031125, 8.772349, 0}, - {-5.416878, -0.052672, 8.682567, 0}, - {-5.614399, -0.032322, 8.693340, 0}, - {-5.582078, 0.015562, 8.038527, 0}, - {-5.532996, -0.019154, 8.003811, 1}, - {-5.451593, -0.088585, 8.389277, 0}, - {-5.433637, -0.120907, 8.461103, 0}, - {-5.456382, -0.082600, 8.352167, 0}, - {-5.480324, -0.110133, 8.429978, 0}, - {-5.503069, -0.126893, 8.602361, 0}, - {-5.524617, -0.173579, 8.689749, 0}, - {-5.519828, -0.161609, 8.710100, 0}, - {-5.448002, -0.165200, 8.803473, 0}, - {-5.337869, -0.209493, 8.835795, 0}, - {-5.226539, -0.217872, 8.792700, 0}, - {-5.204991, -0.144849, 8.779531, 0}, - {-5.155910, -0.038307, 8.741224, 0}, - {-5.038594, 0.025139, 8.692143, 0}, - {-4.826707, 0.129287, 8.741224, 0}, - {-4.588484, 0.221464, 9.275131, 0}, - {-4.413708, 0.146046, 9.674962, 0}, - {-4.571725, 0.420182, 9.512156, 0}, - {-4.693829, 0.806845, 9.115917, 0}, - {-4.513067, 1.146822, 8.775940, 0}, - {-3.907335, 0.906205, 8.744816, 0}, - {-3.440465, 0.709880, 8.558068, 0}, - {-3.076547, 0.870292, 8.097184, 0}, - {-2.567780, 0.849941, 7.629118, 0}, - {-0.930147, -0.430956, 9.020149, 0}, - {0.472855, -1.265335, 13.321329, 0}, - {-0.475249, -0.396240, 11.602294, 0}, - {-2.302023, 0.135272, 10.661373, 0}, - {-2.796426, -0.083797, 11.195279, 0}, - {-2.404974, -0.368707, 10.447092, 0}, - {-1.205480, -0.381875, 9.781505, 0}, - {-0.250194, 0.064643, 9.928748, 0}, - {-0.004788, 0.374692, 9.695313, 0}, - {0.256179, -0.470460, 8.904030, 0}, - {0.268150, -0.964863, 8.276750, 0}, - {0.314837, -0.756567, 8.742421, 0}, - {0.496797, -0.694318, 9.910791, 0}, - {0.828393, -0.748188, 10.779886, 0}, - {0.738611, -0.306458, 11.670528, 0}, - {0.616507, -0.045490, 11.973394, 0}, - {0.690727, -0.164003, 11.194082, 0}, - {0.632069, -0.343568, 10.463851, 0}, - {0.422576, 0.026336, 10.319002, 0}, - {0.520739, 0.468066, 10.074794, 0}, - {0.845153, 0.277727, 9.525325, 0}, - {1.058236, -0.199916, 9.085989, 0}, - {1.198297, -0.499191, 9.630670, 0}, - {1.109712, -0.314837, 10.516523, 0}, - {1.086967, 0.258574, 10.805025, 0}, - {1.313219, 0.523133, 10.685315, 0}, - {1.334767, 0.202310, 10.316608, 0}, - {1.298854, -0.199916, 9.993391, 0}, - {1.471236, -0.282516, 10.037683, 0}, - {1.620873, 0.053870, 9.892835, 0}, - {1.553836, 0.363918, 9.296679, 0}, - {1.425746, 0.114922, 8.937549, 0}, - {1.545456, -0.174777, 9.566027, 0}, - {1.985989, 0.075417, 10.395617, 0}, - {2.272096, 0.312443, 10.295060, 0}, - {2.181116, 0.196324, 9.525325, 0}, - {1.965638, 0.197522, 9.500186, 0}, - {2.054224, -0.038307, 9.800658, 0}, - {1.924937, 0.196324, 9.728832, 0}, - {2.146400, 0.402226, 9.747986, 0}, - {2.321177, 0.282516, 9.983814, 0}, - {2.279279, 0.118513, 7.716507, 0}, - {2.229000, -0.113724, 9.612713, 0}, - {2.345119, 0.343568, 11.982971, 0}, - {2.196679, 0.189142, 9.917974, 0}, - {2.218226, -0.119710, 9.633064, 0}, - {2.020705, 0.239420, 9.703692, 0}, - {1.997960, 0.318429, 9.247598, 0}, - {1.975215, 0.132878, 8.886073, 0}, - {1.841140, 0.253785, 8.754393, 0}, - {1.507149, 0.458489, 8.775940, 0}, - {1.295262, 0.497994, 9.170983, 0}, - {1.291671, 0.102951, 9.712072, 0}, - {1.267729, 0.034716, 9.686934, 0}, - {1.474827, -0.047884, 9.932339, 0}, - {1.121683, -0.041899, 10.319002, 0}, - {0.475249, 0.349553, 11.362873, 0}, - {0.029928, 0.153229, 13.443434, 0}, - {1.442506, -0.270545, 12.089513, 0}, - {0.821211, 0.186748, 10.431530, 0}, - {0.302866, 0.573411, 9.538493, 0}, - {0.973242, -0.051475, 8.095987, 0}, - {1.428140, -1.648407, 7.060496, 0}, - {1.292868, -2.129641, 8.062469, 0}, - {0.068235, 0.414197, 8.157040, 0}, - {-1.018732, 1.418563, 9.985011, 0}, - {-1.479616, 1.746569, 18.444918, 0}, - {0.362721, 0.951695, 11.461036, 0}, - {0.283713, -0.120907, 8.001416, 0}, - {-0.320823, 0.131681, 11.031277, 0}, - {-0.141258, 0.141258, 9.783898, 0}, - {-0.098162, 0.118513, 10.248373, 0}, - {-0.278924, 0.311246, 9.223656, 0}, - {-0.034716, 0.162806, 9.734818, 0}, - {-0.282516, -0.306458, 12.023673, 0}, - {-0.219069, 0.069432, 9.692919, 0}, - {-0.235829, 0.088585, 10.111904, 0}, - {-0.243011, 0.071826, 10.181335, 0}, - {-0.237026, 0.084994, 10.177745, 0}, - {-0.246603, 0.079009, 10.078385, 0}, - {-0.222661, 0.083797, 10.192110, 0}, - {-0.252588, 0.067038, 10.103524, 0}, - {-0.226252, 0.084994, 10.156197, 0}, - {-0.265756, 0.071826, 10.116693, 0}, - {-0.235829, 0.083797, 10.168168, 0}, - {-0.251391, 0.083797, 10.108313, 0}, - {-0.248997, 0.083797, 10.155000, 0}, - {-0.228646, 0.083797, 10.122678, 0}, - {-0.266953, 0.067038, 10.104721, 0}, - {-0.233435, 0.074220, 10.141831, 0}, - {-0.259771, 0.080206, 10.107116, 0}, - {-0.245406, 0.080206, 10.166970, 0}, - {-0.256179, 0.075417, 10.099933, 0}, - {-0.243011, 0.070629, 10.153803, 0}, - {-0.256179, 0.073023, 10.090356, 0}, - {-0.258574, 0.077812, 10.200489, 0}, - {-0.253785, 0.063446, 10.095144, 0}, - {-0.245406, 0.073023, 10.135846, 0}, - {-0.251391, 0.082600, 10.134649, 0}, - {-0.251391, 0.068235, 10.116693, 0}, - {-0.247800, 0.079009, 10.164577, 0}, - {-0.244208, 0.075417, 10.115496, 0}, - {-0.238223, 0.073023, 10.137043, 0}, - {-0.251391, 0.077812, 10.078385, 0}, - {-0.235829, 0.077812, 10.131058, 0}, - {-0.250194, 0.087388, 10.123875, 0}, - {-0.250194, 0.079009, 10.147817, 0}, - {-0.254982, 0.064643, 10.110707, 0}, - {-0.256179, 0.083797, 10.151408, 0}, - {-0.237026, 0.079009, 10.103524, 0}, - {-0.256179, 0.079009, 10.137043, 0}, - {-0.246603, 0.081403, 10.139438, 0}, - {-0.243011, 0.077812, 10.115496, 0}, - {-0.254982, 0.063446, 10.159788, 0}, - {-0.248997, 0.089783, 10.092751, 0}, - {-0.251391, 0.074220, 10.164577, 0}, - {-0.246603, 0.079009, 10.117889, 0}, - {-0.247800, 0.086191, 10.145423, 0}, - {-0.247800, 0.088585, 10.123875, 0}, - {-0.254982, 0.075417, 10.122678, 0}, - {-0.250194, 0.080206, 10.147817, 0}, - {-0.251391, 0.068235, 10.113101, 0}, - {-0.246603, 0.074220, 10.147817, 0}, - {-0.243011, 0.068235, 10.104721, 0}, - {-0.245406, 0.063446, 10.143028, 0}, - {-0.250194, 0.075417, 10.121481, 0}, - {-0.252588, 0.079009, 10.141831, 0}, - {-0.245406, 0.071826, 10.129861, 0}, - {-0.240617, 0.079009, 10.135846, 0}, - {-0.240617, 0.069432, 10.141831, 0}, - {-0.245406, 0.079009, 10.121481, 0}, - {-0.252588, 0.069432, 10.160985, 0}, - {-0.258574, 0.067038, 10.121481, 0}, - {-0.260968, 0.067038, 10.140635, 0}, - {-0.250194, 0.068235, 10.127466, 0}, - {-0.239420, 0.074220, 10.129861, 0}, - {-0.250194, 0.065841, 10.131058, 0}, - {-0.245406, 0.074220, 10.128663, 0}, - {-0.247800, 0.088585, 10.133451, 0}, - {-0.245406, 0.082600, 10.105919, 0}, - {-0.251391, 0.067038, 10.133451, 0}, - {-0.241814, 0.075417, 10.121481, 0}, - {-0.247800, 0.075417, 10.140635, 0}, - {-0.254982, 0.080206, 10.132255, 0}, - {-0.237026, 0.074220, 10.137043, 0}, - {-0.251391, 0.082600, 10.135846, 0}, - {-0.247800, 0.095768, 10.135846, 0}, - {-0.244208, 0.075417, 10.115496, 0}, - {-0.245406, 0.074220, 10.138240, 0}, - {-0.239420, 0.080206, 10.137043, 0}, - {-0.257377, 0.073023, 10.128663, 0}, - {-0.253785, 0.081403, 10.134649, 0}, - {-0.256179, 0.061052, 10.137043, 0}, - {-0.243011, 0.082600, 10.129861, 0}, - {-0.246603, 0.080206, 10.116693, 0}, - {-0.240617, 0.080206, 10.120284, 0}, - {-0.251391, 0.069432, 10.109509, 0}, - {-0.247800, 0.073023, 10.144226, 0}, - {-0.248997, 0.077812, 10.110707, 0}, - {-0.256179, 0.065841, 10.134649, 0}, - {-0.246603, 0.071826, 10.111904, 0}, - {-0.265756, 0.075417, 10.123875, 0}, - {-0.245406, 0.084994, 10.131058, 0}, - {-0.251391, 0.073023, 10.114298, 0}, - {-0.247800, 0.090980, 10.145423, 0}, - {-0.263362, 0.088585, 10.121481, 0}, - {-0.258574, 0.074220, 10.149014, 0}, - {-0.252588, 0.069432, 10.114298, 0}, - {-0.259771, 0.074220, 10.121481, 0}, - {-0.251391, 0.068235, 10.137043, 0}, - {-0.245406, 0.074220, 10.131058, 0}, - {-0.244208, 0.074220, 10.121481, 0}, - {-0.253785, 0.070629, 10.108313, 0}, - {-0.256179, 0.077812, 10.144226, 0}, - {-0.241814, 0.058658, 10.104721, 0}, - {-0.244208, 0.069432, 10.133451, 0}, - {-0.241814, 0.081403, 10.113101, 0}, - {-0.253785, 0.080206, 10.110707, 0}, - {-0.257377, 0.086191, 10.121481, 0}, - {-0.252588, 0.080206, 10.129861, 0}, - {-0.246603, 0.081403, 10.121481, 0}, - {-0.245406, 0.086191, 10.123875, 0}, - {-0.251391, 0.076614, 10.153803, 0}, - {-0.246603, 0.068235, 10.120284, 0}, - {-0.234632, 0.090980, 10.134649, 0}, - {-0.253785, 0.080206, 10.098736, 0}, - {-0.256179, 0.093374, 10.135846, 0}, - {-0.259771, 0.076614, 10.126269, 0}, - {-0.240617, 0.074220, 10.147817, 0}, - {-0.256179, 0.068235, 10.119086, 0}, - {-0.254982, 0.073023, 10.120284, 0}, - {-0.250194, 0.082600, 10.143028, 0}, - {-0.250194, 0.076614, 10.115496, 0}, - {-0.247800, 0.068235, 10.145423, 0}, - {-0.241814, 0.077812, 10.122678, 0}, - {-0.245406, 0.079009, 10.138240, 0}, - {-0.266953, 0.083797, 10.111904, 0}, - {-0.254982, 0.074220, 10.116693, 0}, - {-0.248997, 0.090980, 10.138240, 0}, - {-0.262165, 0.083797, 10.123875, 0}, - {-0.245406, 0.081403, 10.128663, 0}, - {-0.252588, 0.065841, 10.103524, 0}, - {-0.248997, 0.089783, 10.128663, 0}, - {-0.250194, 0.070629, 10.108313, 0}, - {-0.248997, 0.068235, 10.147817, 0}, - {-0.251391, 0.083797, 10.125072, 0}, - {-0.258574, 0.070629, 10.125072, 0}, - {-0.259771, 0.058658, 10.125072, 0}, - {-0.246603, 0.070629, 10.120284, 0}, - {-0.243011, 0.064643, 10.128663, 0}, - {-0.263362, 0.073023, 10.134649, 0}, - {-0.246603, 0.076614, 10.140635, 0}, - {-0.246603, 0.084994, 10.122678, 0}, - {-0.241814, 0.068235, 10.131058, 0}, - {-0.243011, 0.073023, 10.115496, 0}, - {-0.252588, 0.074220, 10.157393, 0}, - {-0.264559, 0.076614, 10.105919, 0}, - {-0.254982, 0.069432, 10.135846, 0}, - {-0.234632, 0.075417, 10.126269, 0}, - {-0.239420, 0.080206, 10.120284, 0}, - {-0.251391, 0.087388, 10.146620, 0}, - {-0.238223, 0.069432, 10.126269, 0}, - {-0.247800, 0.065841, 10.127466, 0}, - {-0.253785, 0.069432, 10.113101, 0}, - {-0.252588, 0.079009, 10.144226, 0}, - {-0.254982, 0.074220, 10.123875, 0}, - {-0.247800, 0.061052, 10.134649, 0}, - {-0.248997, 0.067038, 10.119086, 0}, - {-0.247800, 0.077812, 10.123875, 0}, - {-0.253785, 0.079009, 10.134649, 0}, - {-0.246603, 0.084994, 10.111904, 0}, - {-0.253785, 0.087388, 10.139438, 0}, - {-0.256179, 0.082600, 10.097539, 0}, - {-0.240617, 0.087388, 10.149014, 0}, - {-0.252588, 0.059855, 10.108313, 0}, - {-0.235829, 0.082600, 10.129861, 0}, - {-0.247800, 0.094571, 10.127466, 0}, - {-0.248997, 0.082600, 10.122678, 0}, - {-0.240617, 0.084994, 10.131058, 0}, - {-0.253785, 0.077812, 10.116693, 0}, - {-0.258574, 0.086191, 10.133451, 0}, - {-0.247800, 0.071826, 10.128663, 0}, - {-0.247800, 0.074220, 10.132255, 0}, - {-0.254982, 0.071826, 10.120284, 0}, - {-0.253785, 0.080206, 10.140635, 0}, - {-0.269348, 0.076614, 10.132255, 0}, - {-0.253785, 0.082600, 10.131058, 0}, - {-0.244208, 0.089783, 10.140635, 0}, - {-0.247800, 0.073023, 10.110707, 0}, - {-0.252588, 0.070629, 10.129861, 0}, - {-0.257377, 0.071826, 10.125072, 0}, - {-0.252588, 0.074220, 10.117889, 0}, - {-0.254982, 0.068235, 10.128663, 0}, - {-0.259771, 0.058658, 10.134649, 0}, - {-0.252588, 0.070629, 10.119086, 0}, - {-0.243011, 0.089783, 10.146620, 0}, - {-0.240617, 0.075417, 10.128663, 0}, - {-0.254982, 0.063446, 10.145423, 0}, - {-0.272939, 0.081403, 10.127466, 0}, - {-0.241814, 0.075417, 10.127466, 0}, - {-0.233435, 0.073023, 10.125072, 0}, - {-0.248997, 0.080206, 10.132255, 0}, - {-0.241814, 0.074220, 10.134649, 0}, - {-0.266953, 0.068235, 10.133451, 0}, - {-0.245406, 0.069432, 10.127466, 0}, - {-0.247800, 0.087388, 10.131058, 0}, - {-0.247800, 0.082600, 10.129861, 0}, - {-0.257377, 0.070629, 10.137043, 0}, - {-0.247800, 0.074220, 10.131058, 0}, - {-0.252588, 0.086191, 10.114298, 0}, - {-0.247800, 0.089783, 10.135846, 0}, - {-0.256179, 0.073023, 10.131058, 0}, - {-0.257377, 0.080206, 10.133451, 0}, - {-0.245406, 0.069432, 10.125072, 0}, - {-0.250194, 0.061052, 10.126269, 0}, - {-0.252588, 0.079009, 10.135846, 0}, - {-0.250194, 0.073023, 10.128663, 0}, - {-0.237026, 0.075417, 10.155000, 0}, - {-0.247800, 0.079009, 10.140635, 0}, - {-0.251391, 0.069432, 10.151408, 0}, - {-0.244208, 0.075417, 10.127466, 0}, - {-0.252588, 0.071826, 10.111904, 0}, - {-0.257377, 0.077812, 10.138240, 0}, - {-0.241814, 0.069432, 10.122678, 0}, - {-0.253785, 0.071826, 10.139438, 0}, - {-0.256179, 0.077812, 10.119086, 0}, - {-0.262165, 0.077812, 10.133451, 0}, - {-0.252588, 0.061052, 10.132255, 0}, - {-0.250194, 0.077812, 10.119086, 0}, - {-0.253785, 0.081403, 10.132255, 0}, - {-0.253785, 0.079009, 10.117889, 0}, - {-0.252588, 0.064643, 10.129861, 0}, - {-0.247800, 0.073023, 10.117889, 0}, - {-0.253785, 0.065841, 10.126269, 0}, - {-0.256179, 0.069432, 10.128663, 0}, - {-0.250194, 0.080206, 10.128663, 0}, - {-0.257377, 0.084994, 10.107116, 0}, - {-0.254982, 0.080206, 10.137043, 0}, - {-0.259771, 0.076614, 10.137043, 0}, - {-0.265756, 0.063446, 10.132255, 0}, - {-0.251391, 0.056264, 10.120284, 0}, - {-0.247800, 0.067038, 10.132255, 0}, - {-0.247800, 0.074220, 10.126269, 0}, - {-0.247800, 0.070629, 10.127466, 0}, - {-0.239420, 0.081403, 10.143028, 0}, - {-0.254982, 0.081403, 10.129861, 0}, - {-0.259771, 0.088585, 10.138240, 0}, - {-0.246603, 0.080206, 10.108313, 0}, - {-0.252588, 0.086191, 10.125072, 0}, - {-0.247800, 0.071826, 10.132255, 0}, - {-0.240617, 0.073023, 10.126269, 0}, - {-0.256179, 0.075417, 10.134649, 0}, - {-0.254982, 0.081403, 10.117889, 0}, - {-0.250194, 0.070629, 10.133451, 0}, - {-0.254982, 0.064643, 10.137043, 0}, - {-0.254982, 0.075417, 10.147817, 0}, - {-0.240617, 0.077812, 10.122678, 0}, - {-0.239420, 0.083797, 10.153803, 0}, - {-0.258574, 0.070629, 10.131058, 0}, - {-0.256179, 0.077812, 10.133451, 0}, - {-0.265756, 0.080206, 10.143028, 0}, - {-0.256179, 0.070629, 10.138240, 0}, - {-0.250194, 0.067038, 10.129861, 0}, - {-0.245406, 0.071826, 10.126269, 0}, - {-0.259771, 0.073023, 10.135846, 0}, - {-0.251391, 0.061052, 10.121481, 0}, - {-0.254982, 0.075417, 10.150211, 0}, - {-0.247800, 0.081403, 10.137043, 0}, - {-0.248997, 0.084994, 10.126269, 0}, - {-0.257377, 0.082600, 10.135846, 0}, - {-0.257377, 0.073023, 10.110707, 0}, - {-0.251391, 0.077812, 10.138240, 0}, - {-0.238223, 0.064643, 10.116693, 0}, - {-0.239420, 0.075417, 10.138240, 0}, - {-0.260968, 0.071826, 10.132255, 0}, - {-0.253785, 0.094571, 10.132255, 0}, - {-0.248997, 0.081403, 10.127466, 0}, - {-0.245406, 0.073023, 10.150211, 0}, - {-0.252588, 0.080206, 10.120284, 0}, - {-0.247800, 0.075417, 10.122678, 0}, - {-0.246603, 0.069432, 10.122678, 0}, - {-0.246603, 0.090980, 10.119086, 0}, - {-0.253785, 0.076614, 10.139438, 0}, - {-0.253785, 0.063446, 10.127466, 0}, - {-0.248997, 0.094571, 10.146620, 0}, - {-0.257377, 0.079009, 10.115496, 0}, - {-0.247800, 0.068235, 10.122678, 0}, - {-0.244208, 0.080206, 10.117889, 0}, - {-0.257377, 0.099359, 10.134649, 0}, - {-0.257377, 0.089783, 10.111904, 0}, - {-0.247800, 0.073023, 10.133451, 0}, - {-0.238223, 0.070629, 10.120284, 0}, - {-0.256179, 0.073023, 10.125072, 0}, - {-0.257377, 0.063446, 10.144226, 0}, - {-0.259771, 0.081403, 10.122678, 0}, - {-0.251391, 0.079009, 10.123875, 0}, - {-0.256179, 0.068235, 10.122678, 0}, - {-0.252588, 0.065841, 10.128663, 0}, - {-0.239420, 0.074220, 10.122678, 0}, - {-0.247800, 0.073023, 10.138240, 0}, - {-0.245406, 0.076614, 10.111904, 0}, - {-0.252588, 0.076614, 10.125072, 0}, - {-0.259771, 0.059855, 10.122678, 0}, - {-0.262165, 0.067038, 10.137043, 0}, - {-0.248997, 0.073023, 10.127466, 0}, - {-0.248997, 0.076614, 10.132255, 0}, - {-0.244208, 0.080206, 10.115496, 0}, - {-0.245406, 0.055067, 10.140635, 0}, - {-0.251391, 0.059855, 10.135846, 0}, - {-0.246603, 0.073023, 10.111904, 0}, - {-0.248997, 0.081403, 10.123875, 0}, - {-0.248997, 0.070629, 10.126269, 0}, - {-0.251391, 0.075417, 10.129861, 0}, - {-0.239420, 0.071826, 10.139438, 0}, - {-0.244208, 0.076614, 10.109509, 0}, - {-0.263362, 0.082600, 10.135846, 0}, - {-0.252588, 0.071826, 10.127466, 0}, - {-0.241814, 0.067038, 10.122678, 0}, - {-0.252588, 0.079009, 10.125072, 0}, - {-0.260968, 0.084994, 10.125072, 0}, - {-0.245406, 0.080206, 10.119086, 0}, - {-0.241814, 0.071826, 10.126269, 0}, - {-0.251391, 0.075417, 10.135846, 0}, - {-0.254982, 0.068235, 10.127466, 0}, - {-0.260968, 0.074220, 10.127466, 0}, - {-0.247800, 0.076614, 10.122678, 0}, - {-0.258574, 0.067038, 10.114298, 0}, - {-0.258574, 0.073023, 10.122678, 0}, - {-0.257377, 0.058658, 10.145423, 0}, - {-0.254982, 0.063446, 10.127466, 0}, - {-0.245406, 0.068235, 10.135846, 0}, - {-0.247800, 0.071826, 10.135846, 0}, - {-0.256179, 0.068235, 10.138240, 0}, - {-0.257377, 0.074220, 10.113101, 0}, - {-0.244208, 0.081403, 10.139438, 0}, - {-0.241814, 0.061052, 10.131058, 0}, - {-0.257377, 0.073023, 10.116693, 0}, - {-0.256179, 0.083797, 10.129861, 0}, - {-0.240617, 0.084994, 10.121481, 0}, - {-0.239420, 0.073023, 10.135846, 0}, - {-0.252588, 0.074220, 10.132255, 0}, - {-0.252588, 0.077812, 10.127466, 0}, - {-0.251391, 0.082600, 10.140635, 0}, - {-0.256179, 0.077812, 10.129861, 0}, - {-0.254982, 0.064643, 10.117889, 0}, - {-0.263362, 0.065841, 10.122678, 0}, - {-0.252588, 0.079009, 10.135846, 0}, - {-0.248997, 0.075417, 10.127466, 0}, - {-0.238223, 0.079009, 10.133451, 0}, - {-0.244208, 0.080206, 10.133451, 0}, - {-0.254982, 0.076614, 10.150211, 0}, - {-0.264559, 0.068235, 10.141831, 0}, - {-0.246603, 0.077812, 10.132255, 0}, - {-0.262165, 0.070629, 10.134649, 0}, - {-0.258574, 0.062249, 10.129861, 0}, - {-0.259771, 0.071826, 10.133451, 0}, - {-0.243011, 0.086191, 10.125072, 0}, - {-0.250194, 0.074220, 10.125072, 0}, - {-0.260968, 0.059855, 10.101130, 0}, - {-0.252588, 0.063446, 10.129861, 0}, - {-0.251391, 0.079009, 10.128663, 0}, - {-0.252588, 0.069432, 10.138240, 0}, - {-0.246603, 0.074220, 10.141831, 0}, - {-0.250194, 0.080206, 10.117889, 0}, - {-0.256179, 0.068235, 10.131058, 0}, - {-0.258574, 0.058658, 10.110707, 0}, - {-0.244208, 0.073023, 10.137043, 0}, - {-0.260968, 0.076614, 10.117889, 0}, - {-0.245406, 0.081403, 10.119086, 0}, - {-0.243011, 0.077812, 10.135846, 0}, - {-0.256179, 0.069432, 10.131058, 0}, - {-0.245406, 0.079009, 10.121481, 0}, - {-0.250194, 0.086191, 10.129861, 0}, - {-0.245406, 0.089783, 10.132255, 0}, - {-0.241814, 0.077812, 10.147817, 0}, - {-0.244208, 0.076614, 10.133451, 0}, - {-0.263362, 0.075417, 10.096342, 0}, - {-0.250194, 0.058658, 10.134649, 0}, - {-0.231040, 0.068235, 10.117889, 0}, - {-0.250194, 0.069432, 10.144226, 0}, - {-0.263362, 0.073023, 10.117889, 0}, - {-0.241814, 0.071826, 10.133451, 0}, - {-0.240617, 0.073023, 10.131058, 0}, - {-0.237026, 0.082600, 10.116693, 0}, - {-0.239420, 0.080206, 10.138240, 0}, - {-0.259771, 0.079009, 10.139438, 0}, - {-0.266953, 0.071826, 10.140635, 0}, - {-0.251391, 0.071826, 10.107116, 0}, - {-0.258574, 0.073023, 10.132255, 0}, - {-0.243011, 0.090980, 10.132255, 0}, - {-0.234632, 0.064643, 10.129861, 0}, - {-0.250194, 0.059855, 10.134649, 0}, - {-0.238223, 0.081403, 10.140635, 0}, - {-0.243011, 0.077812, 10.131058, 0}, - {-0.247800, 0.069432, 10.143028, 0}, - {-0.247800, 0.067038, 10.135846, 0}, - {-0.243011, 0.065841, 10.128663, 0}, - {-0.253785, 0.077812, 10.129861, 0}, - {-0.244208, 0.080206, 10.107116, 0}, - {-0.244208, 0.074220, 10.143028, 0}, - {-0.253785, 0.080206, 10.119086, 0}, - {-0.247800, 0.070629, 10.139438, 0}, - {-0.243011, 0.082600, 10.125072, 0}, - {-0.257377, 0.075417, 10.150211, 0}, - {-0.263362, 0.077812, 10.152605, 0}, - {-0.263362, 0.081403, 10.135846, 0}, - {-0.250194, 0.075417, 10.139438, 0}, - {-0.248997, 0.077812, 10.131058, 0}, - {-0.247800, 0.074220, 10.127466, 0}, - {-0.243011, 0.069432, 10.122678, 0}, - {-0.251391, 0.079009, 10.133451, 0}, - {-0.252588, 0.061052, 10.126269, 0}, - {-0.265756, 0.081403, 10.128663, 0}, - {-0.244208, 0.064643, 10.122678, 0}, - {-0.256179, 0.065841, 10.123875, 0}, - {-0.263362, 0.076614, 10.125072, 0}, - {-0.252588, 0.079009, 10.126269, 0}, - {-0.252588, 0.070629, 10.115496, 0}, - {-0.254982, 0.073023, 10.115496, 0}, - {-0.234632, 0.070629, 10.123875, 0}, - {-0.237026, 0.076614, 10.121481, 0}, - {-0.256179, 0.070629, 10.134649, 0}, - {-0.268150, 0.073023, 10.129861, 0}, - {-0.244208, 0.075417, 10.121481, 0}, - {-0.253785, 0.080206, 10.126269, 0}, - {-0.259771, 0.075417, 10.120284, 0}, - {-0.263362, 0.070629, 10.115496, 0}, - {-0.247800, 0.075417, 10.126269, 0}, - {-0.243011, 0.068235, 10.152605, 0}, - {-0.247800, 0.069432, 10.125072, 0}, - {-0.257377, 0.083797, 10.129861, 0}, - {-0.247800, 0.075417, 10.129861, 0}, - {-0.247800, 0.076614, 10.115496, 0}, - {-0.247800, 0.071826, 10.131058, 0}, - {-0.258574, 0.083797, 10.125072, 0}, - {-0.250194, 0.095768, 10.132255, 0}, - {-0.266953, 0.076614, 10.123875, 0}, - {-0.256179, 0.079009, 10.152605, 0}, - {-0.251391, 0.073023, 10.126269, 0}, - {-0.248997, 0.068235, 10.128663, 0}, - {-0.243011, 0.073023, 10.134649, 0}, - {-0.258574, 0.071826, 10.137043, 0}, - {-0.253785, 0.061052, 10.119086, 0}, - {-0.250194, 0.073023, 10.138240, 0}, - {-0.241814, 0.070629, 10.113101, 0}, - {-0.250194, 0.079009, 10.141831, 0}, - {-0.237026, 0.070629, 10.128663, 0}, - {-0.240617, 0.083797, 10.120284, 0}, - {-0.259771, 0.073023, 10.144226, 0}, - {-0.232237, 0.068235, 10.122678, 0}, - {-0.246603, 0.065841, 10.133451, 0}, - {-0.258574, 0.079009, 10.109509, 0}, - {-0.245406, 0.075417, 10.131058, 0}, - {-0.240617, 0.076614, 10.127466, 0}, - {-0.246603, 0.074220, 10.115496, 0}, - {-0.247800, 0.068235, 10.129861, 0}, - {-0.252588, 0.073023, 10.145423, 0}, - {-0.252588, 0.069432, 10.132255, 0}, - {-0.248997, 0.062249, 10.110707, 0}, - {-0.257377, 0.073023, 10.146620, 0}, - {-0.247800, 0.077812, 10.133451, 0}, - {-0.233435, 0.075417, 10.123875, 0}, - {-0.259771, 0.080206, 10.117889, 0}, - {-0.252588, 0.071826, 10.131058, 0}, - {-0.257377, 0.077812, 10.128663, 0}, - {-0.244208, 0.065841, 10.138240, 0}, - {-0.245406, 0.076614, 10.132255, 0}, - {-0.259771, 0.074220, 10.134649, 0}, - {-0.251391, 0.073023, 10.133451, 0}, - {-0.238223, 0.063446, 10.127466, 0}, - {-0.246603, 0.052672, 10.128663, 0}, - {-0.260968, 0.069432, 10.125072, 0}, - {-0.251391, 0.087388, 10.104721, 0}, - {-0.243011, 0.074220, 10.120284, 0}, - {-0.259771, 0.069432, 10.149014, 0}, - {-0.252588, 0.083797, 10.139438, 0}, - {-0.252588, 0.070629, 10.134649, 0}, - {-0.244208, 0.071826, 10.134649, 0}, - {-0.244208, 0.080206, 10.122678, 0}, - {-0.263362, 0.076614, 10.126269, 0}, - {-0.243011, 0.076614, 10.113101, 0}, - {-0.250194, 0.084994, 10.133451, 0}, - {-0.247800, 0.081403, 10.151408, 0}, - {-0.247800, 0.082600, 10.123875, 0}, - {-0.240617, 0.080206, 10.133451, 0}, - {-0.254982, 0.074220, 10.135846, 0}, - {-0.260968, 0.076614, 10.123875, 0}, - {-0.251391, 0.069432, 10.127466, 0}, - {-0.251391, 0.080206, 10.140635, 0}, - {-0.248997, 0.065841, 10.129861, 0}, - {-0.245406, 0.081403, 10.137043, 0}, - {-0.248997, 0.096965, 10.128663, 0}, - {-0.264559, 0.069432, 10.149014, 0}, - {-0.254982, 0.071826, 10.114298, 0}, - {-0.257377, 0.071826, 10.140635, 0}, - {-0.254982, 0.077812, 10.128663, 0}, - {-0.256179, 0.083797, 10.126269, 0}, - {-0.254982, 0.063446, 10.143028, 0}, - {-0.247800, 0.058658, 10.133451, 0}, - {-0.251391, 0.068235, 10.137043, 0}, - {-0.245406, 0.080206, 10.102327, 0}, - {-0.243011, 0.070629, 10.129861, 0}, - {-0.253785, 0.073023, 10.111904, 0}, - {-0.251391, 0.076614, 10.145423, 0}, - {-0.247800, 0.075417, 10.133451, 0}, - {-0.248997, 0.065841, 10.139438, 0}, - {-0.248997, 0.063446, 10.125072, 0}, - {-0.252588, 0.070629, 10.102327, 0}, - {-0.246603, 0.083797, 10.113101, 0}, - {-0.237026, 0.074220, 10.116693, 0}, - {-0.240617, 0.073023, 10.138240, 0}, - {-0.235829, 0.076614, 10.116693, 0}, - {-0.247800, 0.073023, 10.141831, 0}, - {-0.258574, 0.075417, 10.134649, 0}, - {-0.253785, 0.081403, 10.126269, 0}, - {-0.250194, 0.082600, 10.121481, 0}, - {-0.250194, 0.088585, 10.149014, 0}, - {-0.253785, 0.069432, 10.126269, 0}, - {-0.252588, 0.083797, 10.128663, 0}, - {-0.245406, 0.058658, 10.133451, 0}, - {-0.258574, 0.087388, 10.119086, 0}, - {-0.253785, 0.064643, 10.131058, 0}, - {-0.248997, 0.067038, 10.128663, 0}, - {-0.248997, 0.075417, 10.155000, 0}, - {-0.251391, 0.079009, 10.132255, 0}, - {-0.253785, 0.087388, 10.131058, 0}, - {-0.240617, 0.088585, 10.113101, 0}, - {-0.247800, 0.077812, 10.134649, 0}, - {-0.247800, 0.077812, 10.122678, 0}, - {-0.263362, 0.086191, 10.131058, 0}, - {-0.243011, 0.084994, 10.129861, 0}, - {-0.243011, 0.077812, 10.113101, 0}, - {-0.252588, 0.077812, 10.125072, 0}, - {-0.248997, 0.076614, 10.096342, 0}, - {-0.241814, 0.070629, 10.158591, 0}, - {-0.257377, 0.075417, 10.117889, 0}, - {-0.250194, 0.076614, 10.131058, 0}, - {-0.250194, 0.071826, 10.135846, 0}, - {-0.253785, 0.069432, 10.115496, 0}, - {-0.248997, 0.069432, 10.144226, 0}, - {-0.246603, 0.068235, 10.110707, 0}, - {-0.260968, 0.075417, 10.151408, 0}, - {-0.246603, 0.074220, 10.113101, 0}, - {-0.254982, 0.076614, 10.122678, 0}, - {-0.250194, 0.063446, 10.116693, 0}, - {-0.233435, 0.077812, 10.134649, 0}, - {-0.245406, 0.079009, 10.135846, 0}, - {-0.250194, 0.079009, 10.119086, 0}, - {-0.264559, 0.086191, 10.109509, 0}, - {-0.252588, 0.090980, 10.126269, 0}, - {-0.250194, 0.082600, 10.147817, 0}, - {-0.238223, 0.070629, 10.125072, 0}, - {-0.245406, 0.082600, 10.139438, 0}, - {-0.239420, 0.082600, 10.131058, 0}, - {-0.251391, 0.087388, 10.147817, 0}, - {-0.257377, 0.073023, 10.128663, 0}, - {-0.251391, 0.081403, 10.144226, 0}, - {-0.254982, 0.086191, 10.120284, 0}, - {-0.253785, 0.080206, 10.146620, 0}, - {-0.256179, 0.077812, 10.149014, 0}, - {-0.248997, 0.083797, 10.128663, 0}, - {-0.251391, 0.071826, 10.125072, 0}, - {-0.244208, 0.068235, 10.113101, 0}, - {-0.252588, 0.070629, 10.132255, 0}, - {-0.258574, 0.064643, 10.116693, 0}, - {-0.246603, 0.074220, 10.135846, 0}, - {-0.247800, 0.070629, 10.123875, 0}, - {-0.239420, 0.081403, 10.144226, 0}, - {-0.247800, 0.075417, 10.121481, 0}, - {-0.259771, 0.073023, 10.103524, 0}, - {-0.248997, 0.073023, 10.129861, 0}, - {-0.241814, 0.071826, 10.134649, 0}, - {-0.235829, 0.079009, 10.127466, 0}, - {-0.244208, 0.095768, 10.122678, 0}, - {-0.227449, 0.065841, 10.147817, 0}, - {-0.251391, 0.074220, 10.135846, 0}, - {-0.251391, 0.074220, 10.137043, 0}, - {-0.253785, 0.077812, 10.125072, 0}, - {-0.259771, 0.071826, 10.135846, 0}, - {-0.227449, 0.067038, 10.122678, 0}, - {-0.235829, 0.065841, 10.127466, 0}, - {-0.251391, 0.076614, 10.128663, 0}, - {-0.238223, 0.058658, 10.128663, 0}, - {-0.238223, 0.074220, 10.126269, 0}, - {-0.246603, 0.084994, 10.140635, 0}, - {-0.258574, 0.071826, 10.132255, 0}, - {-0.252588, 0.074220, 10.122678, 0}, - {-0.245406, 0.076614, 10.121481, 0}, - {-0.244208, 0.074220, 10.134649, 0}, - {-0.248997, 0.069432, 10.122678, 0}, - {-0.246603, 0.077812, 10.127466, 0}, - {-0.256179, 0.083797, 10.133451, 0}, - {-0.247800, 0.086191, 10.135846, 0}, - {-0.248997, 0.076614, 10.144226, 0}, - {-0.253785, 0.073023, 10.120284, 0}, - {-0.256179, 0.071826, 10.140635, 0}, - {-0.254982, 0.083797, 10.123875, 0}, - {-0.247800, 0.076614, 10.131058, 0}, - {-0.259771, 0.077812, 10.117889, 0}, - {-0.243011, 0.069432, 10.132255, 0}, - {-0.250194, 0.075417, 10.120284, 0}, - {-0.247800, 0.086191, 10.128663, 0}, - {-0.241814, 0.065841, 10.150211, 0}, - {-0.250194, 0.075417, 10.128663, 0}, - {-0.234632, 0.079009, 10.103524, 0}, - {-0.266953, 0.073023, 10.127466, 0}, - {-0.237026, 0.080206, 10.119086, 0}, - {-0.254982, 0.075417, 10.151408, 0}, - {-0.248997, 0.063446, 10.129861, 0}, - {-0.254982, 0.071826, 10.135846, 0}, - {-0.246603, 0.075417, 10.125072, 0}, - {-0.237026, 0.069432, 10.126269, 0}, - {-0.243011, 0.070629, 10.146620, 0}, - {-0.244208, 0.082600, 10.137043, 0}, - {-0.263362, 0.071826, 10.138240, 0}, - {-0.250194, 0.074220, 10.149014, 0}, - {-0.250194, 0.070629, 10.137043, 0}, - {-0.253785, 0.080206, 10.122678, 0}, - {-0.247800, 0.080206, 10.131058, 0}, - {-0.237026, 0.082600, 10.134649, 0}, - {-0.243011, 0.079009, 10.129861, 0}, - {-0.246603, 0.071826, 10.117889, 0}, - {-0.256179, 0.074220, 10.135846, 0}, - {-0.250194, 0.075417, 10.128663, 0}, - {-0.247800, 0.074220, 10.120284, 0}, - {-0.251391, 0.065841, 10.141831, 0}, - {-0.248997, 0.062249, 10.115496, 0}, - {-0.260968, 0.068235, 10.141831, 0}, - {-0.248997, 0.079009, 10.141831, 0}, - {-0.247800, 0.075417, 10.156197, 0}, - {-0.246603, 0.070629, 10.132255, 0}, - {-0.252588, 0.082600, 10.116693, 0}, - {-0.252588, 0.074220, 10.122678, 0}, - {-0.262165, 0.071826, 10.123875, 0}, - {-0.251391, 0.067038, 10.121481, 0}, - {-0.239420, 0.081403, 10.113101, 0}, - {-0.247800, 0.084994, 10.132255, 0}, - {-0.252588, 0.075417, 10.138240, 0}, - {-0.246603, 0.075417, 10.125072, 0}, - {-0.246603, 0.076614, 10.109509, 0}, - {-0.253785, 0.074220, 10.125072, 0}, - {-0.251391, 0.081403, 10.139438, 0}, - {-0.243011, 0.073023, 10.114298, 0}, - {-0.253785, 0.065841, 10.107116, 0}, - {-0.243011, 0.080206, 10.121481, 0}, - {-0.253785, 0.069432, 10.129861, 0}, - {-0.256179, 0.068235, 10.121481, 0}, - {-0.246603, 0.068235, 10.121481, 0}, - {-0.254982, 0.075417, 10.121481, 0}, - {-0.241814, 0.074220, 10.120284, 0}, - {-0.258574, 0.073023, 10.127466, 0}, - {-0.235829, 0.074220, 10.128663, 0}, - {-0.247800, 0.071826, 10.120284, 0}, - {-0.258574, 0.073023, 10.119086, 0}, - {-0.256179, 0.082600, 10.125072, 0}, - {-0.243011, 0.081403, 10.128663, 0}, - {-0.241814, 0.069432, 10.132255, 0}, - {-0.252588, 0.074220, 10.135846, 0}, - {-0.235829, 0.076614, 10.138240, 0}, - {-0.252588, 0.069432, 10.133451, 0}, - {-0.257377, 0.087388, 10.129861, 0}, - {-0.252588, 0.079009, 10.120284, 0}, - {-0.245406, 0.077812, 10.132255, 0}, - {-0.244208, 0.077812, 10.105919, 0}, - {-0.252588, 0.064643, 10.128663, 0}, - {-0.257377, 0.080206, 10.122678, 0}, - {-0.227449, 0.075417, 10.122678, 0}, - {-0.256179, 0.076614, 10.139438, 0}, - {-0.250194, 0.068235, 10.134649, 0}, - {-0.244208, 0.080206, 10.145423, 0}, - {-0.244208, 0.075417, 10.117889, 0}, - {-0.245406, 0.071826, 10.137043, 0}, - {-0.251391, 0.069432, 10.132255, 0}, - {-0.252588, 0.065841, 10.127466, 0}, - {-0.252588, 0.087388, 10.135846, 0}, - {-0.250194, 0.083797, 10.140635, 0}, - {-0.265756, 0.083797, 10.127466, 0}, - {-0.251391, 0.081403, 10.116693, 0}, - {-0.243011, 0.073023, 10.131058, 0}, - {-0.256179, 0.079009, 10.132255, 0}, - {-0.256179, 0.079009, 10.135846, 0}, - {-0.259771, 0.080206, 10.139438, 0}, - {-0.248997, 0.069432, 10.134649, 0}, - {-0.247800, 0.076614, 10.109509, 0}, - {-0.251391, 0.069432, 10.140635, 0}, - {-0.248997, 0.065841, 10.129861, 0}, - {-0.256179, 0.084994, 10.119086, 0}, - {-0.253785, 0.082600, 10.111904, 0}, - {-0.251391, 0.079009, 10.134649, 0}, - {-0.258574, 0.077812, 10.125072, 0}, - {-0.254982, 0.062249, 10.108313, 0}, - {-0.272939, 0.080206, 10.151408, 0}, - {-0.260968, 0.082600, 10.113101, 0}, - {-0.244208, 0.086191, 10.123875, 0}, - {-0.247800, 0.079009, 10.116693, 0}, - {-0.247800, 0.075417, 10.141831, 0}, - {-0.259771, 0.076614, 10.120284, 0}, - {-0.239420, 0.081403, 10.134649, 0}, - {-0.253785, 0.080206, 10.121481, 0}, - {-0.262165, 0.074220, 10.119086, 0}, - {-0.253785, 0.069432, 10.127466, 0}, - {-0.262165, 0.069432, 10.104721, 0}, - {-0.252588, 0.084994, 10.120284, 0}, - {-0.251391, 0.063446, 10.113101, 0}, - {-0.263362, 0.074220, 10.121481, 0}, - {-0.259771, 0.068235, 10.135846, 0}, - {-0.250194, 0.070629, 10.138240, 0}, - {-0.258574, 0.077812, 10.132255, 0}, - {-0.252588, 0.067038, 10.135846, 0}, - {-0.251391, 0.064643, 10.128663, 0}, - {-0.243011, 0.082600, 10.134649, 0}, - {-0.238223, 0.084994, 10.144226, 0}, - {-0.260968, 0.084994, 10.123875, 0}, - {-0.254982, 0.075417, 10.137043, 0}, - {-0.259771, 0.075417, 10.111904, 0}, - {-0.251391, 0.084994, 10.143028, 0}, - {-0.245406, 0.079009, 10.117889, 0}, - {-0.252588, 0.074220, 10.149014, 0}, - {-0.254982, 0.062249, 10.132255, 0}, - {-0.241814, 0.062249, 10.116693, 0}, - {-0.247800, 0.074220, 10.151408, 0}, - {-0.240617, 0.081403, 10.115496, 0}, - {-0.247800, 0.067038, 10.139438, 0}, - {-0.250194, 0.079009, 10.126269, 0}, - {-0.237026, 0.087388, 10.150211, 0}, - {-0.238223, 0.073023, 10.134649, 0}, - {-0.241814, 0.080206, 10.140635, 0}, - {-0.248997, 0.075417, 10.122678, 0}, - {-0.254982, 0.081403, 10.123875, 0}, - {-0.257377, 0.067038, 10.138240, 0}, - {-0.247800, 0.076614, 10.128663, 0}, - {-0.256179, 0.076614, 10.145423, 0}, - {-0.241814, 0.080206, 10.132255, 0}, - {-0.238223, 0.067038, 10.137043, 0}, - {-0.257377, 0.064643, 10.119086, 0}, - {-0.243011, 0.081403, 10.129861, 0}, - {-0.248997, 0.081403, 10.115496, 0}, - {-0.258574, 0.062249, 10.133451, 0}, - {-0.247800, 0.070629, 10.119086, 0}, - {-0.252588, 0.074220, 10.129861, 0}, - {-0.246603, 0.070629, 10.133451, 0}, - {-0.245406, 0.073023, 10.102327, 0}, - {-0.252588, 0.080206, 10.139438, 0}, - {-0.247800, 0.068235, 10.113101, 0}, - {-0.254982, 0.074220, 10.126269, 0}, - {-0.251391, 0.079009, 10.120284, 0}, - {-0.251391, 0.089783, 10.137043, 0}, - {-0.252588, 0.065841, 10.127466, 0}, - {-0.251391, 0.068235, 10.120284, 0}, - {-0.257377, 0.067038, 10.127466, 0}, - {-0.241814, 0.081403, 10.128663, 0}, - {-0.241814, 0.081403, 10.135846, 0}, - {-0.247800, 0.071826, 10.135846, 0}, - {-0.250194, 0.070629, 10.138240, 0}, - {-0.252588, 0.084994, 10.131058, 0}, - {-0.245406, 0.083797, 10.139438, 0}, - {-0.244208, 0.075417, 10.123875, 0}, - {-0.259771, 0.077812, 10.137043, 0}, - {-0.248997, 0.071826, 10.123875, 0}, - {-0.246603, 0.086191, 10.152605, 0}, - {-0.241814, 0.069432, 10.132255, 0}, - {-0.243011, 0.064643, 10.129861, 0}, - {-0.245406, 0.073023, 10.129861, 0}, - {-0.251391, 0.076614, 10.116693, 0}, - {-0.264559, 0.068235, 10.139438, 0}, - {-0.247800, 0.073023, 10.105919, 0}, - {-0.244208, 0.077812, 10.145423, 0}, - {-0.250194, 0.077812, 10.137043, 0}, - {-0.252588, 0.064643, 10.126269, 0}, - {-0.252588, 0.079009, 10.125072, 0}, - {-0.239420, 0.084994, 10.126269, 0}, - {-0.246603, 0.067038, 10.137043, 0}, - {-0.252588, 0.077812, 10.114298, 0}, - {-0.266953, 0.062249, 10.131058, 0}, - {-0.264559, 0.076614, 10.114298, 0}, - {-0.250194, 0.071826, 10.135846, 0}, - {-0.250194, 0.087388, 10.134649, 0}, - {-0.246603, 0.082600, 10.147817, 0}, - {-0.245406, 0.065841, 10.131058, 0}, - {-0.258574, 0.070629, 10.139438, 0}, - {-0.251391, 0.081403, 10.111904, 0}, - {-0.246603, 0.080206, 10.132255, 0}, - {-0.235829, 0.074220, 10.117889, 0}, - {-0.243011, 0.075417, 10.123875, 0}, - {-0.241814, 0.065841, 10.139438, 0}, - {-0.241814, 0.077812, 10.119086, 0}, - {-0.247800, 0.084994, 10.153803, 0}, - {-0.266953, 0.081403, 10.116693, 0}, - {-0.243011, 0.083797, 10.137043, 0}, - {-0.257377, 0.074220, 10.109509, 0}, - {-0.252588, 0.074220, 10.126269, 0}, - {-0.247800, 0.076614, 10.127466, 0}, - {-0.243011, 0.068235, 10.111904, 0}, - {-0.259771, 0.077812, 10.132255, 0}, - {-0.253785, 0.092177, 10.103524, 0}, - {-0.243011, 0.086191, 10.123875, 0}, - {-0.232237, 0.069432, 10.134649, 0}, - {-0.233435, 0.076614, 10.129861, 0}, - {-0.257377, 0.068235, 10.114298, 0}, - {-0.250194, 0.074220, 10.127466, 0}, - {-0.245406, 0.077812, 10.131058, 0}, - {-0.251391, 0.077812, 10.123875, 0}, - {-0.245406, 0.074220, 10.123875, 0}, - {-0.245406, 0.069432, 10.122678, 0}, - {-0.254982, 0.071826, 10.119086, 0}, - {-0.257377, 0.064643, 10.116693, 0}, - {-0.256179, 0.079009, 10.128663, 0}, - {-0.241814, 0.062249, 10.098736, 0}, - {-0.248997, 0.067038, 10.144226, 0}, - {-0.237026, 0.083797, 10.145423, 0}, - {-0.253785, 0.076614, 10.120284, 0}, - {-0.251391, 0.065841, 10.113101, 0}, - {-0.248997, 0.067038, 10.104721, 0}, - {-0.244208, 0.073023, 10.134649, 0}, - {-0.259771, 0.069432, 10.134649, 0}, - {-0.244208, 0.084994, 10.141831, 0}, - {-0.257377, 0.076614, 10.126269, 0}, - {-0.246603, 0.073023, 10.137043, 0}, - {-0.247800, 0.073023, 10.111904, 0}, - {-0.243011, 0.073023, 10.144226, 0}, - {-0.251391, 0.080206, 10.129861, 0}, - {-0.244208, 0.076614, 10.126269, 0}, - {-0.246603, 0.069432, 10.135846, 0}, - {-0.250194, 0.073023, 10.131058, 0}, - {-0.250194, 0.069432, 10.122678, 0}, - {-0.238223, 0.073023, 10.133451, 0}, - {-0.229843, 0.063446, 10.121481, 0}, - {-0.235829, 0.084994, 10.115496, 0}, - {-0.243011, 0.077812, 10.122678, 0}, - {-0.238223, 0.067038, 10.116693, 0}, - {-0.245406, 0.069432, 10.137043, 0}, - {-0.258574, 0.081403, 10.122678, 0}, - {-0.239420, 0.083797, 10.149014, 0}, - {-0.240617, 0.075417, 10.123875, 0}, - {-0.251391, 0.067038, 10.153803, 0}, - {-0.240617, 0.075417, 10.145423, 0}, - {-0.231040, 0.083797, 10.129861, 0}, - {-0.247800, 0.090980, 10.155000, 0}, - {-0.247800, 0.077812, 10.125072, 0}, - {-0.253785, 0.084994, 10.131058, 0}, - {-0.257377, 0.073023, 10.108313, 0}, - {-0.248997, 0.080206, 10.123875, 0}, - {-0.244208, 0.073023, 10.113101, 0}, - {-0.237026, 0.080206, 10.121481, 0}, - {-0.248997, 0.055067, 10.127466, 0}, - {-0.256179, 0.073023, 10.137043, 0}, - {-0.260968, 0.081403, 10.131058, 0}, - {-0.251391, 0.069432, 10.125072, 0}, - {-0.252588, 0.074220, 10.115496, 0}, - {-0.250194, 0.086191, 10.122678, 0}, - {-0.235829, 0.076614, 10.119086, 0}, - {-0.258574, 0.079009, 10.127466, 0}, - {-0.247800, 0.076614, 10.139438, 0}, - {-0.247800, 0.079009, 10.126269, 0}, - {-0.237026, 0.088585, 10.134649, 0}, - {-0.240617, 0.073023, 10.120284, 0}, - {-0.244208, 0.073023, 10.125072, 0}, - {-0.243011, 0.076614, 10.115496, 0}, - {-0.238223, 0.080206, 10.122678, 0}, - {-0.239420, 0.067038, 10.122678, 0}, - {-0.253785, 0.081403, 10.119086, 0}, - {-0.246603, 0.080206, 10.125072, 0}, - {-0.251391, 0.082600, 10.126269, 0}, - {-0.238223, 0.073023, 10.132255, 0}, - {-0.252588, 0.075417, 10.133451, 0}, - {-0.254982, 0.061052, 10.140635, 0}, - {-0.253785, 0.065841, 10.117889, 0}, - {-0.235829, 0.071826, 10.143028, 0}, - {-0.245406, 0.083797, 10.122678, 0}, - {-0.256179, 0.088585, 10.129861, 0}, - {-0.259771, 0.077812, 10.121481, 0}, - {-0.238223, 0.067038, 10.125072, 0}, - {-0.247800, 0.073023, 10.140635, 0}, - {-0.248997, 0.073023, 10.111904, 0}, - {-0.245406, 0.075417, 10.145423, 0}, - {-0.268150, 0.075417, 10.102327, 0}, - {-0.246603, 0.080206, 10.129861, 0}, - {-0.251391, 0.080206, 10.126269, 0}, - {-0.251391, 0.071826, 10.134649, 0}, - {-0.262165, 0.076614, 10.143028, 0}, - {-0.247800, 0.070629, 10.121481, 0}, - {-0.238223, 0.083797, 10.135846, 0}, - {-0.251391, 0.069432, 10.111904, 0}, - {-0.256179, 0.082600, 10.139438, 0}, - {-0.262165, 0.083797, 10.128663, 0}, - {-0.251391, 0.079009, 10.122678, 0}, - {-0.245406, 0.077812, 10.125072, 0}, - {-0.239420, 0.074220, 10.125072, 0}, - {-0.258574, 0.076614, 10.127466, 0}, - {-0.256179, 0.088585, 10.126269, 0}, - {-0.246603, 0.080206, 10.111904, 0}, - {-0.241814, 0.084994, 10.133451, 0}, - {-0.235829, 0.079009, 10.141831, 0}, - {-0.263362, 0.073023, 10.138240, 0}, - {-0.251391, 0.069432, 10.134649, 0}, - {-0.245406, 0.069432, 10.127466, 0}, - {-0.250194, 0.074220, 10.133451, 0}, - {-0.251391, 0.068235, 10.131058, 0}, - {-0.254982, 0.070629, 10.128663, 0}, - {-0.240617, 0.083797, 10.111904, 0}, - {-0.245406, 0.075417, 10.122678, 0}, - {-0.245406, 0.084994, 10.119086, 0}, - {-0.248997, 0.079009, 10.098736, 0}, - {-0.240617, 0.070629, 10.127466, 0}, - {-0.244208, 0.079009, 10.145423, 0}, - {-0.264559, 0.079009, 10.120284, 0}, - {-0.244208, 0.077812, 10.119086, 0}, - {-0.237026, 0.080206, 10.107116, 0}, - {-0.235829, 0.086191, 10.128663, 0}, - {-0.245406, 0.081403, 10.133451, 0}, - {-0.247800, 0.077812, 10.138240, 0}, - {-0.251391, 0.080206, 10.125072, 0}, - {-0.257377, 0.068235, 10.147817, 0}, - {-0.263362, 0.076614, 10.121481, 0}, - {-0.268150, 0.073023, 10.116693, 0}, - {-0.247800, 0.071826, 10.122678, 0}, - {-0.260968, 0.073023, 10.134649, 0}, - {-0.254982, 0.074220, 10.116693, 0}, - {-0.246603, 0.086191, 10.131058, 0}, - {-0.248997, 0.079009, 10.125072, 0}, - {-0.252588, 0.067038, 10.132255, 0}, - {-0.254982, 0.063446, 10.123875, 0}, - {-0.256179, 0.067038, 10.116693, 0}, - {-0.259771, 0.083797, 10.125072, 0}, - {-0.264559, 0.069432, 10.131058, 0}, - {-0.243011, 0.074220, 10.143028, 0}, - {-0.254982, 0.081403, 10.128663, 0}, - {-0.253785, 0.065841, 10.143028, 0}, - {-0.260968, 0.075417, 10.131058, 0}, - {-0.265756, 0.090980, 10.128663, 0}, - {-0.244208, 0.088585, 10.146620, 0}, - {-0.246603, 0.082600, 10.114298, 0}, - {-0.256179, 0.077812, 10.133451, 0}, - {-0.250194, 0.064643, 10.117889, 0}, - {-0.254982, 0.075417, 10.117889, 0}, - {-0.266953, 0.065841, 10.113101, 0}, - {-0.253785, 0.073023, 10.128663, 0}, - {-0.259771, 0.082600, 10.138240, 0}, - {-0.247800, 0.071826, 10.145423, 0}, - {-0.243011, 0.074220, 10.122678, 0}, - {-0.257377, 0.083797, 10.140635, 0}, - {-0.232237, 0.087388, 10.117889, 0}, - {-0.244208, 0.076614, 10.125072, 0}, - {-0.248997, 0.067038, 10.128663, 0}, - {-0.256179, 0.062249, 10.115496, 0}, - {-0.263362, 0.071826, 10.141831, 0}, - {-0.246603, 0.075417, 10.107116, 0}, - {-0.244208, 0.081403, 10.137043, 0}, - {-0.254982, 0.083797, 10.123875, 0}, - {-0.243011, 0.092177, 10.132255, 0}, - {-0.260968, 0.077812, 10.131058, 0}, - {-0.256179, 0.073023, 10.119086, 0}, - {-0.239420, 0.082600, 10.132255, 0}, - {-0.251391, 0.073023, 10.117889, 0}, - {-0.254982, 0.071826, 10.134649, 0}, - {-0.259771, 0.080206, 10.120284, 0}, - {-0.246603, 0.069432, 10.133451, 0}, - {-0.250194, 0.061052, 10.126269, 0}, - {-0.256179, 0.063446, 10.109509, 0}, - {-0.251391, 0.087388, 10.120284, 0}, - {-0.246603, 0.069432, 10.132255, 0}, - {-0.244208, 0.077812, 10.133451, 0}, - {-0.257377, 0.069432, 10.126269, 0}, - {-0.247800, 0.075417, 10.133451, 0}, - {-0.246603, 0.071826, 10.117889, 0}, - {-0.245406, 0.093374, 10.135846, 0}, - {-0.254982, 0.082600, 10.105919, 0}, - {-0.247800, 0.076614, 10.143028, 0}, - {-0.246603, 0.076614, 10.126269, 0}, - {-0.243011, 0.067038, 10.127466, 0}, - {-0.253785, 0.064643, 10.119086, 0}, - {-0.248997, 0.079009, 10.127466, 0}, - {-0.248997, 0.080206, 10.141831, 0}, - {-0.244208, 0.074220, 10.133451, 0}, - {-0.240617, 0.079009, 10.135846, 0}, - {-0.232237, 0.075417, 10.115496, 0}, - {-0.254982, 0.082600, 10.139438, 0}, - {-0.258574, 0.077812, 10.119086, 0}, - {-0.246603, 0.076614, 10.109509, 0}, - {-0.248997, 0.080206, 10.125072, 0}, - {-0.256179, 0.077812, 10.128663, 0}, - {-0.235829, 0.076614, 10.126269, 0}, - {-0.253785, 0.076614, 10.128663, 0}, - {-0.254982, 0.075417, 10.147817, 0}, - {-0.246603, 0.079009, 10.145423, 0}, - {-0.243011, 0.081403, 10.146620, 0}, - {-0.237026, 0.075417, 10.134649, 0}, - {-0.258574, 0.077812, 10.149014, 0}, - {-0.262165, 0.079009, 10.141831, 0}, - {-0.245406, 0.069432, 10.140635, 0}, - {-0.240617, 0.074220, 10.120284, 0}, - {-0.252588, 0.080206, 10.143028, 0}, - {-0.254982, 0.084994, 10.135846, 0}, - {-0.248997, 0.067038, 10.131058, 0}, - {-0.234632, 0.070629, 10.133451, 0}, - {-0.246603, 0.067038, 10.132255, 0}, - {-0.246603, 0.070629, 10.143028, 0}, - {-0.245406, 0.079009, 10.135846, 0}, - {-0.253785, 0.077812, 10.144226, 0}, - {-0.248997, 0.076614, 10.127466, 0}, - {-0.227449, 0.093374, 10.119086, 0}, - {-0.257377, 0.073023, 10.125072, 0}, - {-0.254982, 0.057461, 10.133451, 0}, - {-0.247800, 0.069432, 10.122678, 0}, - {-0.252588, 0.075417, 10.125072, 0}, - {-0.262165, 0.088585, 10.125072, 0}, - {-0.253785, 0.080206, 10.127466, 0}, - {-0.252588, 0.070629, 10.137043, 0}, - {-0.254982, 0.068235, 10.113101, 0}, - {-0.244208, 0.076614, 10.132255, 0}, - {-0.244208, 0.074220, 10.129861, 0}, - {-0.244208, 0.073023, 10.141831, 0}, - {-0.239420, 0.080206, 10.108313, 0}, - {-0.241814, 0.087388, 10.122678, 0}, - {-0.253785, 0.093374, 10.122678, 0}, - {-0.252588, 0.070629, 10.133451, 0}, - {-0.244208, 0.073023, 10.147817, 0}, - {-0.245406, 0.076614, 10.122678, 0}, - {-0.254982, 0.087388, 10.132255, 0}, - {-0.241814, 0.065841, 10.125072, 0}, - {-0.231040, 0.068235, 10.123875, 0}, - {-0.238223, 0.081403, 10.117889, 0}, - {-0.241814, 0.083797, 10.139438, 0}, - {-0.240617, 0.045490, 10.119086, 0}, - {-0.262165, 0.069432, 10.125072, 0}, - {-0.259771, 0.081403, 10.126269, 0}, - {-0.248997, 0.068235, 10.129861, 0}, - {-0.238223, 0.071826, 10.131058, 0}, - {-0.237026, 0.087388, 10.117889, 0}, - {-0.253785, 0.076614, 10.123875, 0}, - {-0.260968, 0.077812, 10.120284, 0}, - {-0.246603, 0.073023, 10.126269, 0}, - {-0.256179, 0.082600, 10.119086, 0}, - {-0.252588, 0.067038, 10.139438, 0}, - {-0.260968, 0.073023, 10.127466, 0}, - {-0.235829, 0.086191, 10.121481, 0}, - {-0.244208, 0.088585, 10.131058, 0}, - {-0.245406, 0.073023, 10.143028, 0}, - {-0.243011, 0.079009, 10.139438, 0}, - {-0.253785, 0.077812, 10.120284, 0}, - {-0.252588, 0.068235, 10.123875, 0}, - {-0.246603, 0.069432, 10.132255, 0}, - {-0.237026, 0.070629, 10.139438, 0}, - {-0.244208, 0.068235, 10.120284, 0}, - {-0.247800, 0.079009, 10.134649, 0}, - {-0.256179, 0.084994, 10.150211, 0}, - {-0.246603, 0.070629, 10.126269, 0}, - {-0.246603, 0.065841, 10.131058, 0}, - {-0.262165, 0.068235, 10.126269, 0}, - {-0.244208, 0.069432, 10.125072, 0}, - {-0.245406, 0.081403, 10.114298, 0}, - {-0.257377, 0.070629, 10.133451, 0}, - {-0.247800, 0.079009, 10.109509, 0}, - {-0.245406, 0.071826, 10.125072, 0}, - {-0.237026, 0.069432, 10.139438, 0}, - {-0.244208, 0.081403, 10.145423, 0}, - {-0.246603, 0.075417, 10.129861, 0}, - {-0.262165, 0.082600, 10.128663, 0}, - {-0.246603, 0.083797, 10.147817, 0}, - {-0.243011, 0.079009, 10.128663, 0}, - {-0.251391, 0.069432, 10.133451, 0}, - {-0.253785, 0.070629, 10.122678, 0}, - {-0.248997, 0.075417, 10.139438, 0}, - {-0.256179, 0.080206, 10.104721, 0}, - {-0.263362, 0.081403, 10.127466, 0}, - {-0.247800, 0.068235, 10.140635, 0}, - {-0.251391, 0.062249, 10.138240, 0}, - {-0.245406, 0.087388, 10.133451, 0}, - {-0.254982, 0.075417, 10.122678, 0}, - {-0.240617, 0.071826, 10.135846, 0}, - {-0.258574, 0.068235, 10.114298, 0}, - {-0.250194, 0.077812, 10.137043, 0}, - {-0.238223, 0.070629, 10.121481, 0}, - {-0.244208, 0.080206, 10.126269, 0}, - {-0.246603, 0.071826, 10.119086, 0}, - {-0.258574, 0.068235, 10.147817, 0}, - {-0.252588, 0.058658, 10.121481, 0}, - {-0.258574, 0.073023, 10.122678, 0}, - {-0.244208, 0.075417, 10.144226, 0}, - {-0.241814, 0.075417, 10.120284, 0}, - {-0.257377, 0.063446, 10.129861, 0}, - {-0.260968, 0.075417, 10.091554, 0}, - {-0.260968, 0.086191, 10.149014, 0}, - {-0.243011, 0.084994, 10.095144, 0}, - {-0.246603, 0.081403, 10.141831, 0}, - {-0.243011, 0.068235, 10.138240, 0}, - {-0.252588, 0.084994, 10.131058, 0}, - {-0.257377, 0.077812, 10.141831, 0}, - {-0.247800, 0.071826, 10.113101, 0}, - {-0.258574, 0.073023, 10.151408, 0}, - {-0.256179, 0.067038, 10.119086, 0}, - {-0.264559, 0.070629, 10.131058, 0}, - {-0.266953, 0.079009, 10.107116, 0}, - {-0.245406, 0.077812, 10.137043, 0}, - {-0.256179, 0.076614, 10.128663, 0}, - {-0.252588, 0.068235, 10.135846, 0}, - {-0.257377, 0.069432, 10.133451, 0}, - {-0.258574, 0.062249, 10.133451, 0}, - {-0.268150, 0.092177, 10.128663, 0}, - {-0.257377, 0.076614, 10.139438, 0}, - {-0.240617, 0.076614, 10.115496, 0}, - {-0.248997, 0.075417, 10.129861, 0}, - {-0.251391, 0.075417, 10.135846, 0}, - {-0.263362, 0.062249, 10.092751, 0}, - {-0.245406, 0.079009, 10.135846, 0}, - {-0.248997, 0.077812, 10.114298, 0}, - {-0.245406, 0.090980, 10.143028, 0}, - {-0.246603, 0.081403, 10.125072, 0}, - {-0.243011, 0.059855, 10.127466, 0}, - {-0.248997, 0.068235, 10.145423, 0}, - {-0.245406, 0.070629, 10.132255, 0}, - {-0.240617, 0.068235, 10.139438, 0}, - {-0.241814, 0.069432, 10.115496, 0}, - {-0.250194, 0.082600, 10.137043, 0}, - {-0.250194, 0.073023, 10.128663, 0}, - {-0.241814, 0.086191, 10.144226, 0}, - {-0.254982, 0.070629, 10.121481, 0}, - {-0.244208, 0.082600, 10.131058, 0}, - {-0.244208, 0.086191, 10.126269, 0}, - {-0.251391, 0.086191, 10.138240, 0}, - {-0.256179, 0.073023, 10.123875, 0}, - {-0.247800, 0.080206, 10.127466, 0}, - {-0.239420, 0.087388, 10.145423, 0}, - {-0.247800, 0.056264, 10.145423, 0}, - {-0.239420, 0.063446, 10.143028, 0}, - {-0.259771, 0.067038, 10.111904, 0}, - {-0.245406, 0.079009, 10.135846, 0}, - {-0.254982, 0.074220, 10.121481, 0}, - {-0.257377, 0.070629, 10.141831, 0}, - {-0.243011, 0.068235, 10.141831, 0}, - {-0.254982, 0.071826, 10.140635, 0}, - {-0.231040, 0.068235, 10.126269, 0}, - {-0.240617, 0.074220, 10.119086, 0}, - {-0.244208, 0.070629, 10.123875, 0}, - {-0.248997, 0.067038, 10.132255, 0}, - {-0.252588, 0.071826, 10.135846, 0}, - {-0.250194, 0.074220, 10.108313, 0}, - {-0.252588, 0.071826, 10.137043, 0}, - {-0.253785, 0.074220, 10.117889, 0}, - {-0.246603, 0.069432, 10.123875, 0}, - {-0.250194, 0.065841, 10.132255, 0}, - {-0.240617, 0.062249, 10.153803, 0}, - {-0.250194, 0.069432, 10.122678, 0}, - {-0.248997, 0.073023, 10.114298, 0}, - {-0.251391, 0.075417, 10.131058, 0}, - {-0.239420, 0.065841, 10.134649, 0}, - {-0.244208, 0.077812, 10.146620, 0}, - {-0.253785, 0.089783, 10.102327, 0}, - {-0.248997, 0.073023, 10.123875, 0}, - {-0.252588, 0.074220, 10.109509, 0}, - {-0.248997, 0.086191, 10.144226, 0}, - {-0.240617, 0.073023, 10.135846, 0}, - {-0.245406, 0.063446, 10.111904, 0}, - {-0.253785, 0.057461, 10.120284, 0}, - {-0.257377, 0.074220, 10.120284, 0}, - {-0.262165, 0.070629, 10.153803, 0}, - {-0.260968, 0.071826, 10.128663, 0}, - {-0.251391, 0.070629, 10.138240, 0}, - {-0.246603, 0.075417, 10.119086, 0}, - {-0.247800, 0.069432, 10.120284, 0}, - {-0.268150, 0.074220, 10.134649, 0}, - {-0.241814, 0.082600, 10.143028, 0}, - {-0.245406, 0.082600, 10.143028, 0}, - {-0.259771, 0.074220, 10.125072, 0}, - {-0.263362, 0.069432, 10.132255, 0}, - {-0.248997, 0.076614, 10.111904, 0}, - {-0.254982, 0.071826, 10.128663, 0}, - {-0.238223, 0.079009, 10.101130, 0}, - {-0.246603, 0.075417, 10.149014, 0}, - {-0.262165, 0.061052, 10.116693, 0}, - {-0.245406, 0.071826, 10.135846, 0}, - {-0.241814, 0.090980, 10.120284, 0}, - {-0.247800, 0.082600, 10.133451, 0}, - {-0.260968, 0.064643, 10.149014, 0}, - {-0.241814, 0.069432, 10.127466, 0}, - {-0.246603, 0.073023, 10.128663, 0}, - {-0.259771, 0.068235, 10.083174, 0}, - {-0.254982, 0.086191, 10.129861, 0}, - {-0.251391, 0.070629, 10.111904, 0}, - {-0.250194, 0.064643, 10.128663, 0}, - {-0.244208, 0.080206, 10.114298, 0}, - {-0.234632, 0.075417, 10.128663, 0}, - {-0.247800, 0.080206, 10.132255, 0}, - {-0.247800, 0.071826, 10.135846, 0}, - {-0.240617, 0.063446, 10.133451, 0}, - {-0.253785, 0.070629, 10.128663, 0}, - {-0.251391, 0.075417, 10.131058, 0}, - {-0.252588, 0.074220, 10.116693, 0}, - {-0.248997, 0.071826, 10.129861, 0}, - {-0.251391, 0.087388, 10.108313, 0}, - {-0.248997, 0.083797, 10.137043, 0}, - {-0.257377, 0.068235, 10.132255, 0}, - {-0.256179, 0.065841, 10.141831, 0}, - {-0.239420, 0.076614, 10.132255, 0}, - {-0.251391, 0.073023, 10.127466, 0}, - {-0.252588, 0.073023, 10.138240, 0}, - {-0.253785, 0.070629, 10.119086, 0}, - {-0.247800, 0.069432, 10.119086, 0}, - {-0.246603, 0.067038, 10.123875, 0}, - {-0.246603, 0.077812, 10.146620, 0}, - {-0.246603, 0.083797, 10.123875, 0}, - {-0.246603, 0.083797, 10.143028, 0}, - {-0.241814, 0.071826, 10.110707, 0}, - {-0.248997, 0.077812, 10.134649, 0}, - {-0.251391, 0.074220, 10.143028, 0}, - {-0.243011, 0.082600, 10.133451, 0}, - {-0.251391, 0.079009, 10.111904, 0}, - {-0.251391, 0.081403, 10.122678, 0}, - {-0.247800, 0.080206, 10.144226, 0}, - {-0.247800, 0.092177, 10.114298, 0}, - {-0.244208, 0.073023, 10.134649, 0}, - {-0.245406, 0.081403, 10.126269, 0}, - {-0.250194, 0.073023, 10.144226, 0}, - {-0.243011, 0.079009, 10.133451, 0}, - {-0.260968, 0.077812, 10.122678, 0}, - {-0.252588, 0.090980, 10.122678, 0}, - {-0.268150, 0.073023, 10.128663, 0}, - {-0.256179, 0.075417, 10.123875, 0}, - {-0.248997, 0.063446, 10.104721, 0}, - {-0.245406, 0.090980, 10.128663, 0}, - {-0.253785, 0.087388, 10.115496, 0}, - {-0.239420, 0.073023, 10.138240, 0}, - {-0.238223, 0.059855, 10.119086, 0}, - {-0.248997, 0.070629, 10.125072, 0}, - {-0.250194, 0.081403, 10.131058, 0}, - {-0.248997, 0.093374, 10.132255, 0}, - {-0.253785, 0.092177, 10.128663, 0}, - {-0.251391, 0.071826, 10.134649, 0}, - {-0.233435, 0.074220, 10.129861, 0}, - {-0.241814, 0.079009, 10.103524, 0}, - {-0.253785, 0.070629, 10.153803, 0}, - {-0.260968, 0.069432, 10.144226, 0}, - {-0.250194, 0.065841, 10.123875, 0}, - {-0.262165, 0.092177, 10.125072, 0}, - {-0.252588, 0.088585, 10.151408, 0}, - {-0.253785, 0.087388, 10.132255, 0}, - {-0.244208, 0.062249, 10.137043, 0}, - {-0.256179, 0.065841, 10.110707, 0}, - {-0.244208, 0.075417, 10.117889, 0}, - {-0.240617, 0.082600, 10.132255, 0}, - {-0.248997, 0.074220, 10.115496, 0}, - {-0.250194, 0.079009, 10.141831, 0}, - {-0.246603, 0.077812, 10.119086, 0}, - {-0.252588, 0.074220, 10.117889, 0}, - {-0.257377, 0.075417, 10.120284, 0}, - {-0.250194, 0.077812, 10.117889, 0}, - {-0.239420, 0.081403, 10.143028, 0}, - {-0.237026, 0.076614, 10.137043, 0}, - {-0.240617, 0.077812, 10.149014, 0}, - {-0.270545, 0.071826, 10.131058, 0}, - {-0.262165, 0.068235, 10.122678, 0}, - {-0.259771, 0.067038, 10.114298, 0}, - {-0.246603, 0.082600, 10.121481, 0}, - {-0.254982, 0.076614, 10.127466, 0}, - {-0.244208, 0.063446, 10.122678, 0}, - {-0.246603, 0.074220, 10.121481, 0}, - {-0.253785, 0.086191, 10.127466, 0}, - {-0.253785, 0.079009, 10.131058, 0}, - {-0.245406, 0.071826, 10.132255, 0}, - {-0.248997, 0.074220, 10.132255, 0}, - {-0.260968, 0.055067, 10.121481, 0}, - {-0.243011, 0.070629, 10.122678, 0}, - {-0.252588, 0.070629, 10.132255, 0}, - {-0.243011, 0.077812, 10.143028, 0}, - {-0.246603, 0.077812, 10.132255, 0}, - {-0.253785, 0.082600, 10.131058, 0}, - {-0.256179, 0.068235, 10.137043, 0}, - {-0.243011, 0.088585, 10.121481, 0}, - {-0.239420, 0.065841, 10.133451, 0}, - {-0.252588, 0.063446, 10.122678, 0}, - {-0.252588, 0.082600, 10.141831, 0}, - {-0.238223, 0.083797, 10.122678, 0}, - {-0.251391, 0.076614, 10.140635, 0}, - {-0.265756, 0.081403, 10.135846, 0}, - {-0.252588, 0.076614, 10.141831, 0}, - {-0.246603, 0.079009, 10.131058, 0}, - {-0.250194, 0.077812, 10.126269, 0}, - {-0.240617, 0.079009, 10.146620, 0}, - {-0.247800, 0.089783, 10.132255, 0}, - {-0.259771, 0.089783, 10.111904, 0}, - {-0.266953, 0.084994, 10.141831, 0}, - {-0.244208, 0.087388, 10.147817, 0}, - {-0.235829, 0.067038, 10.127466, 0}, - {-0.245406, 0.069432, 10.129861, 0}, - {-0.250194, 0.083797, 10.108313, 0}, - {-0.240617, 0.084994, 10.146620, 0}, - {-0.256179, 0.077812, 10.121481, 0}, - {-0.250194, 0.076614, 10.151408, 0}, - {-0.248997, 0.073023, 10.128663, 0}, - {-0.252588, 0.068235, 10.140635, 0}, - {-0.252588, 0.074220, 10.147817, 0}, - {-0.253785, 0.083797, 10.139438, 0}, - {-0.243011, 0.069432, 10.114298, 0}, - {-0.235829, 0.059855, 10.122678, 0}, - {-0.253785, 0.076614, 10.145423, 0}, - {-0.245406, 0.077812, 10.115496, 0}, - {-0.252588, 0.065841, 10.139438, 0}, - {-0.248997, 0.092177, 10.132255, 0}, - {-0.256179, 0.088585, 10.150211, 0}, - {-0.250194, 0.082600, 10.134649, 0}, - {-0.244208, 0.069432, 10.137043, 0}, - {-0.254982, 0.076614, 10.127466, 0}, - {-0.253785, 0.063446, 10.135846, 0}, - {-0.258574, 0.080206, 10.145423, 0}, - {-0.232237, 0.074220, 10.126269, 0}, - {-0.241814, 0.080206, 10.131058, 0}, - {-0.240617, 0.075417, 10.116693, 0}, - {-0.253785, 0.068235, 10.132255, 0}, - {-0.241814, 0.083797, 10.139438, 0}, - {-0.245406, 0.084994, 10.129861, 0}, - {-0.245406, 0.079009, 10.165773, 0}, - {-0.238223, 0.079009, 10.101130, 0}, - {-0.247800, 0.081403, 10.138240, 0}, - {-0.244208, 0.070629, 10.126269, 0}, - {-0.253785, 0.082600, 10.149014, 0}, - {-0.235829, 0.079009, 10.115496, 0}, - {-0.239420, 0.070629, 10.114298, 0}, - {-0.251391, 0.086191, 10.128663, 0}, - {-0.241814, 0.075417, 10.119086, 0}, - {-0.241814, 0.074220, 10.165773, 0}, - {-0.233435, 0.075417, 10.101130, 0}, - {-0.254982, 0.087388, 10.135846, 0}, - {-0.232237, 0.074220, 10.129861, 0}, - {-0.233435, 0.076614, 10.123875, 0}, - {-0.258574, 0.093374, 10.137043, 0}, - {-0.243011, 0.074220, 10.137043, 0}, - {-0.244208, 0.083797, 10.145423, 0}, - {-0.252588, 0.087388, 10.137043, 0}, - {-0.251391, 0.077812, 10.120284, 0}, - {-0.235829, 0.067038, 10.117889, 0}, - {-0.240617, 0.075417, 10.125072, 0}, - {-0.253785, 0.086191, 10.127466, 0}, - {-0.256179, 0.080206, 10.126269, 0}, - {-0.254982, 0.071826, 10.132255, 0}, - {-0.235829, 0.074220, 10.128663, 0}, - {-0.252588, 0.079009, 10.117889, 0}, - {-0.245406, 0.081403, 10.123875, 0}, - {-0.246603, 0.073023, 10.127466, 0}, - {-0.252588, 0.063446, 10.159788, 0}, - {-0.247800, 0.079009, 10.147817, 0}, - {-0.258574, 0.079009, 10.131058, 0}, - {-0.269348, 0.075417, 10.134649, 0}, - {-0.248997, 0.083797, 10.107116, 0}, - {-0.244208, 0.081403, 10.139438, 0}, - {-0.259771, 0.070629, 10.133451, 0}, - {-0.257377, 0.063446, 10.128663, 0}, - {-0.254982, 0.071826, 10.121481, 0}, - {-0.252588, 0.088585, 10.137043, 0}, - {-0.251391, 0.083797, 10.135846, 0}, - {-0.253785, 0.086191, 10.134649, 0}, - {-0.252588, 0.073023, 10.115496, 0}, - {-0.254982, 0.075417, 10.145423, 0}, - {-0.250194, 0.076614, 10.137043, 0}, - {-0.248997, 0.070629, 10.135846, 0}, - {-0.259771, 0.073023, 10.137043, 0}, - {-0.245406, 0.088585, 10.120284, 0}, - {-0.254982, 0.074220, 10.151408, 0}, - {-0.252588, 0.074220, 10.103524, 0}, - {-0.258574, 0.070629, 10.146620, 0}, - {-0.251391, 0.080206, 10.121481, 0}, - {-0.241814, 0.070629, 10.131058, 0}, - {-0.246603, 0.071826, 10.116693, 0}, - {-0.248997, 0.067038, 10.135846, 0}, - {-0.251391, 0.070629, 10.132255, 0}, - {-0.250194, 0.081403, 10.132255, 0}, - {-0.254982, 0.074220, 10.134649, 0}, - {-0.243011, 0.081403, 10.131058, 0}, - {-0.237026, 0.089783, 10.128663, 0}, - {-0.243011, 0.077812, 10.125072, 0}, - {-0.244208, 0.074220, 10.131058, 0}, - {-0.243011, 0.086191, 10.121481, 0}, - {-0.250194, 0.079009, 10.135846, 0}, - {-0.247800, 0.061052, 10.132255, 0}, - {-0.258574, 0.063446, 10.122678, 0}, - {-0.245406, 0.076614, 10.114298, 0}, - {-0.238223, 0.082600, 10.101130, 0}, - {-0.264559, 0.057461, 10.119086, 0}, - {-0.248997, 0.077812, 10.126269, 0}, - {-0.237026, 0.094571, 10.127466, 0}, - {-0.256179, 0.071826, 10.116693, 0}, - {-0.248997, 0.080206, 10.135846, 0}, - {-0.259771, 0.067038, 10.128663, 0}, - {-0.246603, 0.074220, 10.134649, 0}, - {-0.244208, 0.083797, 10.131058, 0}, - {-0.233435, 0.075417, 10.129861, 0}, - {-0.241814, 0.074220, 10.128663, 0}, - {-0.238223, 0.080206, 10.105919, 0}, - {-0.241814, 0.084994, 10.131058, 0}, - {-0.254982, 0.076614, 10.129861, 0}, - {-0.258574, 0.079009, 10.117889, 0}, - {-0.251391, 0.069432, 10.135846, 0}, - {-0.243011, 0.082600, 10.135846, 0}, - {-0.243011, 0.073023, 10.121481, 0}, - {-0.250194, 0.074220, 10.140635, 0}, - {-0.251391, 0.069432, 10.119086, 0}, - {-0.258574, 0.074220, 10.117889, 0}, - {-0.260968, 0.069432, 10.138240, 0}, - {-0.260968, 0.080206, 10.133451, 0}, - {-0.238223, 0.080206, 10.140635, 0}, - {-0.248997, 0.075417, 10.103524, 0}, - {-0.259771, 0.069432, 10.144226, 0}, - {-0.252588, 0.076614, 10.095144, 0}, - {-0.254982, 0.068235, 10.146620, 0}, - {-0.256179, 0.079009, 10.143028, 0}, - {-0.246603, 0.090980, 10.139438, 0}, - {-0.251391, 0.079009, 10.131058, 0}, - {-0.253785, 0.077812, 10.119086, 0}, - {-0.256179, 0.076614, 10.157393, 0}, - {-0.246603, 0.067038, 10.121481, 0}, - {-0.237026, 0.081403, 10.159788, 0}, - {-0.250194, 0.082600, 10.125072, 0}, - {-0.248997, 0.077812, 10.117889, 0}, - {-0.237026, 0.074220, 10.121481, 0}, - {-0.237026, 0.062249, 10.138240, 0}, - {-0.247800, 0.070629, 10.126269, 0}, - {-0.245406, 0.073023, 10.138240, 0}, - {-0.245406, 0.065841, 10.134649, 0}, - {-0.240617, 0.083797, 10.137043, 0}, - {-0.244208, 0.063446, 10.137043, 0}, - {-0.260968, 0.080206, 10.123875, 0}, - {-0.245406, 0.083797, 10.137043, 0}, - {-0.237026, 0.068235, 10.122678, 0}, - {-0.250194, 0.070629, 10.137043, 0}, - {-0.248997, 0.073023, 10.128663, 0}, - {-0.239420, 0.073023, 10.127466, 0}, - {-0.256179, 0.069432, 10.123875, 0}, - {-0.244208, 0.064643, 10.141831, 0}, - {-0.246603, 0.062249, 10.114298, 0}, - {-0.260968, 0.076614, 10.108313, 0}, - {-0.257377, 0.069432, 10.135846, 0}, - {-0.265756, 0.074220, 10.123875, 0}, - {-0.254982, 0.065841, 10.145423, 0}, - {-0.248997, 0.070629, 10.123875, 0}, - {-0.241814, 0.079009, 10.137043, 0}, - {-0.251391, 0.095768, 10.141831, 0}, - {-0.244208, 0.071826, 10.111904, 0}, - {-0.243011, 0.075417, 10.132255, 0}, - {-0.246603, 0.090980, 10.131058, 0}, - {-0.252588, 0.071826, 10.135846, 0}, - {-0.248997, 0.065841, 10.120284, 0}, - {-0.248997, 0.082600, 10.116693, 0}, - {-0.263362, 0.075417, 10.138240, 0}, - {-0.247800, 0.061052, 10.129861, 0}, - {-0.250194, 0.059855, 10.132255, 0}, - {-0.251391, 0.069432, 10.152605, 0}, - {-0.247800, 0.068235, 10.129861, 0}, - {-0.240617, 0.062249, 10.138240, 0}, - {-0.264559, 0.070629, 10.120284, 0}, - {-0.253785, 0.071826, 10.151408, 0}, - {-0.246603, 0.074220, 10.125072, 0}, - {-0.256179, 0.070629, 10.160985, 0}, - {-0.247800, 0.061052, 10.131058, 0}, - {-0.246603, 0.070629, 10.125072, 0}, - {-0.258574, 0.086191, 10.135846, 0}, - {-0.253785, 0.077812, 10.120284, 0}, - {-0.235829, 0.074220, 10.133451, 0}, - {-0.239420, 0.083797, 10.122678, 0}, - {-0.258574, 0.071826, 10.139438, 0}, - {-0.259771, 0.084994, 10.110707, 0}, - {-0.243011, 0.077812, 10.131058, 0}, - {-0.240617, 0.077812, 10.134649, 0}, - {-0.244208, 0.059855, 10.128663, 0}, - {-0.239420, 0.068235, 10.122678, 0}, - {-0.258574, 0.076614, 10.119086, 0}, - {-0.258574, 0.075417, 10.147817, 0}, - {-0.248997, 0.062249, 10.117889, 0}, - {-0.248997, 0.076614, 10.135846, 0}, - {-0.241814, 0.076614, 10.109509, 0}, - {-0.257377, 0.068235, 10.144226, 0}, - {-0.264559, 0.064643, 10.096342, 0}, - {-0.241814, 0.068235, 10.139438, 0}, - {-0.250194, 0.088585, 10.114298, 0}, - {-0.259771, 0.079009, 10.159788, 0}, - {-0.247800, 0.071826, 10.138240, 0}, - {-0.245406, 0.073023, 10.117889, 0}, - {-0.246603, 0.070629, 10.137043, 0}, - {-0.248997, 0.069432, 10.108313, 0}, - {-0.254982, 0.077812, 10.144226, 0}, - {-0.254982, 0.088585, 10.108313, 0}, - {-0.245406, 0.082600, 10.135846, 0}, - {-0.245406, 0.095768, 10.125072, 0}, - {-0.232237, 0.083797, 10.133451, 0}, - {-0.243011, 0.069432, 10.089159, 0}, - {-0.237026, 0.082600, 10.152605, 0}, - {-0.241814, 0.065841, 10.116693, 0}, - {-0.262165, 0.067038, 10.138240, 0}, - {-0.262165, 0.081403, 10.150211, 0}, - {-0.257377, 0.079009, 10.109509, 0}, - {-0.257377, 0.084994, 10.131058, 0}, - {-0.238223, 0.090980, 10.107116, 0}, - {-0.231040, 0.093374, 10.151408, 0}, - {-0.250194, 0.069432, 10.108313, 0}, - {-0.244208, 0.067038, 10.166970, 0}, - {-0.244208, 0.074220, 10.105919, 0}, - {-0.247800, 0.076614, 10.145423, 0}, - {-0.237026, 0.071826, 10.122678, 0}, - {-0.244208, 0.070629, 10.127466, 0}, - {-0.243011, 0.074220, 10.119086, 0}, - {-0.246603, 0.073023, 10.121481, 0}, - {-0.245406, 0.084994, 10.129861, 0}, - {-0.237026, 0.082600, 10.128663, 0}, - {-0.229843, 0.074220, 10.127466, 0}, - {-0.250194, 0.076614, 10.116693, 0}, - {-0.240617, 0.074220, 10.138240, 0}, - {-0.240617, 0.074220, 10.117889, 0}, - {-0.245406, 0.075417, 10.126269, 0}, - {-0.241814, 0.077812, 10.129861, 0}, - {-0.251391, 0.081403, 10.139438, 0}, - {-0.227449, 0.075417, 10.127466, 0}, - {-0.239420, 0.079009, 10.119086, 0}, - {-0.238223, 0.087388, 10.120284, 0}, - {-0.243011, 0.057461, 10.122678, 0}, - {-0.250194, 0.056264, 10.145423, 0}, - {-0.233435, 0.075417, 10.119086, 0}, - {-0.237026, 0.061052, 10.137043, 0}, - {-0.240617, 0.084994, 10.123875, 0}, - {-0.245406, 0.088585, 10.151408, 0}, - {-0.234632, 0.081403, 10.128663, 0}, - {-0.240617, 0.086191, 10.123875, 0}, - {-0.237026, 0.080206, 10.119086, 0}, - {-0.234632, 0.067038, 10.134649, 0}, - {-0.241814, 0.070629, 10.138240, 0}, - {-0.248997, 0.065841, 10.134649, 0}, - {-0.238223, 0.081403, 10.143028, 0}, - {-0.243011, 0.079009, 10.121481, 0}, - {-0.240617, 0.079009, 10.128663, 0}, - {-0.251391, 0.069432, 10.131058, 0}, - {-0.244208, 0.063446, 10.138240, 0}, - {-0.240617, 0.058658, 10.117889, 0}, - {-0.239420, 0.081403, 10.145423, 0}, - {-0.245406, 0.080206, 10.114298, 0}, - {-0.240617, 0.075417, 10.127466, 0}, - {-0.243011, 0.077812, 10.127466, 0}, - {-0.250194, 0.065841, 10.119086, 0}, - {-0.232237, 0.064643, 10.120284, 0}, - {-0.239420, 0.065841, 10.131058, 0}, - {-0.251391, 0.071826, 10.143028, 0}, - {-0.246603, 0.080206, 10.125072, 0}, - {-0.238223, 0.075417, 10.123875, 0}, - {-0.245406, 0.081403, 10.132255, 0}, - {-0.241814, 0.083797, 10.117889, 0}, - {-0.251391, 0.070629, 10.135846, 0}, - {-0.262165, 0.075417, 10.120284, 0}, - {-0.251391, 0.086191, 10.145423, 0}, - {-0.239420, 0.087388, 10.131058, 0}, - {-0.246603, 0.077812, 10.126269, 0}, - {-0.246603, 0.073023, 10.135846, 0}, - {-0.264559, 0.079009, 10.120284, 0}, - {-0.264559, 0.074220, 10.125072, 0}, - {-0.229843, 0.067038, 10.127466, 0}, - {-0.231040, 0.077812, 10.131058, 0}, - {-0.245406, 0.075417, 10.128663, 0}, - {-0.240617, 0.071826, 10.116693, 0}, - {-0.234632, 0.081403, 10.128663, 0}, - {-0.228646, 0.063446, 10.132255, 0}, - {-0.227449, 0.057461, 10.139438, 0}, - {-0.251391, 0.075417, 10.120284, 0}, - {-0.231040, 0.092177, 10.122678, 0}, - {-0.240617, 0.077812, 10.137043, 0}, - {-0.252588, 0.075417, 10.132255, 0}, - {-0.248997, 0.077812, 10.120284, 0}, - {-0.248997, 0.080206, 10.117889, 0}, - {-0.252588, 0.063446, 10.113101, 0}, - {-0.247800, 0.069432, 10.133451, 0}, - {-0.246603, 0.092177, 10.108313, 0}, - {-0.240617, 0.088585, 10.134649, 0}, - {-0.239420, 0.076614, 10.125072, 0}, - {-0.248997, 0.070629, 10.128663, 0}, - {-0.243011, 0.073023, 10.128663, 0}, - {-0.243011, 0.084994, 10.115496, 0}, - {-0.243011, 0.087388, 10.141831, 0}, - {-0.237026, 0.070629, 10.144226, 0}, - {-0.247800, 0.081403, 10.113101, 0}, - {-0.234632, 0.096965, 10.133451, 0}, - {-0.258574, 0.069432, 10.132255, 0}, - {-0.258574, 0.077812, 10.116693, 0}, - {-0.243011, 0.079009, 10.135846, 0}, - {-0.253785, 0.082600, 10.102327, 0}, - {-0.240617, 0.075417, 10.144226, 0}, - {-0.247800, 0.074220, 10.123875, 0}, - {-0.256179, 0.079009, 10.120284, 0}, - {-0.254982, 0.077812, 10.141831, 0}, - {-0.257377, 0.076614, 10.143028, 0}, - {-0.250194, 0.086191, 10.137043, 0}, - {-0.238223, 0.081403, 10.116693, 0}, - {-0.238223, 0.084994, 10.139438, 0}, - {-0.247800, 0.080206, 10.126269, 0}, - {-0.263362, 0.074220, 10.131058, 0}, - {-0.260968, 0.077812, 10.123875, 0}, - {-0.238223, 0.059855, 10.128663, 0}, - {-0.245406, 0.062249, 10.134649, 0}, - {-0.257377, 0.080206, 10.131058, 0}, - {-0.244208, 0.083797, 10.131058, 0}, - {-0.232237, 0.080206, 10.134649, 0}, - {-0.244208, 0.076614, 10.119086, 0}, - {-0.241814, 0.073023, 10.141831, 0}, - {-0.257377, 0.067038, 10.138240, 0}, - {-0.241814, 0.086191, 10.133451, 0}, - {-0.246603, 0.079009, 10.133451, 0}, - {-0.248997, 0.067038, 10.125072, 0}, - {-0.239420, 0.082600, 10.122678, 0}, - {-0.244208, 0.084994, 10.129861, 0}, - {-0.233435, 0.073023, 10.147817, 0}, - {-0.250194, 0.069432, 10.133451, 0}, - {-0.254982, 0.070629, 10.146620, 0}, - {-0.231040, 0.083797, 10.117889, 0}, - {-0.245406, 0.081403, 10.119086, 0}, - {-0.256179, 0.093374, 10.131058, 0}, - {-0.241814, 0.084994, 10.138240, 0}, - {-0.252588, 0.073023, 10.137043, 0}, - {-0.251391, 0.081403, 10.126269, 0}, - {-0.235829, 0.069432, 10.137043, 0}, - {-0.247800, 0.080206, 10.132255, 0}, - {-0.238223, 0.064643, 10.144226, 0}, - {-0.234632, 0.076614, 10.127466, 0}, - {-0.245406, 0.069432, 10.137043, 0}, - {-0.241814, 0.082600, 10.116693, 0}, - {-0.233435, 0.101754, 10.132255, 0}, - {-0.240617, 0.086191, 10.132255, 0}, - {-0.235829, 0.081403, 10.120284, 0}, - {-0.239420, 0.076614, 10.128663, 0}, - {-0.251391, 0.079009, 10.117889, 0}, - {-0.256179, 0.081403, 10.149014, 0}, - {-0.238223, 0.079009, 10.105919, 0}, - {-0.234632, 0.079009, 10.125072, 0}, - {-0.254982, 0.071826, 10.115496, 0}, - {-0.263362, 0.082600, 10.151408, 0}, - {-0.243011, 0.075417, 10.109509, 0}, - {-0.222661, 0.073023, 10.129861, 0}, - {-0.246603, 0.074220, 10.133451, 0}, - {-0.248997, 0.086191, 10.129861, 0}, - {-0.252588, 0.086191, 10.149014, 0}, - {-0.238223, 0.071826, 10.104721, 0}, - {-0.237026, 0.071826, 10.135846, 0}, - {-0.243011, 0.086191, 10.111904, 0}, - {-0.244208, 0.093374, 10.141831, 0}, - {-0.253785, 0.063446, 10.123875, 0}, - {-0.244208, 0.083797, 10.134649, 0}, - {-0.244208, 0.090980, 10.128663, 0}, - {-0.258574, 0.065841, 10.134649, 0}, - {-0.256179, 0.070629, 10.128663, 0}, - {-0.243011, 0.071826, 10.137043, 0}, - {-0.225055, 0.074220, 10.134649, 0}, - {-0.245406, 0.069432, 10.116693, 0}, - {-0.237026, 0.077812, 10.133451, 0}, - {-0.245406, 0.073023, 10.104721, 0}, - {-0.253785, 0.081403, 10.159788, 0}, - {-0.245406, 0.086191, 10.113101, 0}, - {-0.243011, 0.081403, 10.126269, 0}, - {-0.241814, 0.065841, 10.108313, 0}, - {-0.240617, 0.057461, 10.131058, 0}, - {-0.241814, 0.065841, 10.144226, 0}, - {-0.237026, 0.073023, 10.128663, 0}, - {-0.250194, 0.090980, 10.145423, 0}, - {-0.254982, 0.070629, 10.119086, 0}, - {-0.244208, 0.063446, 10.131058, 0}, - {-0.235829, 0.077812, 10.121481, 0}, - {-0.248997, 0.076614, 10.137043, 0}, - {-0.262165, 0.076614, 10.123875, 0}, - {-0.250194, 0.064643, 10.119086, 0}, - {-0.239420, 0.077812, 10.116693, 0}, - {-0.245406, 0.080206, 10.128663, 0}, - {-0.243011, 0.084994, 10.123875, 0}, - {-0.244208, 0.077812, 10.125072, 0}, - {-0.237026, 0.089783, 10.122678, 0}, - {-0.235829, 0.065841, 10.137043, 0}, - {-0.245406, 0.065841, 10.150211, 0}, - {-0.252588, 0.074220, 10.111904, 0}, - {-0.241814, 0.068235, 10.146620, 0}, - {-0.229843, 0.069432, 10.120284, 0}, - {-0.240617, 0.079009, 10.131058, 0}, - {-0.240617, 0.084994, 10.095144, 0}, - {-0.239420, 0.067038, 10.133451, 0}, - {-0.247800, 0.083797, 10.128663, 0}, - {-0.252588, 0.075417, 10.135846, 0}, - {-0.252588, 0.068235, 10.131058, 0}, - {-0.243011, 0.087388, 10.102327, 0}, - {-0.247800, 0.088585, 10.132255, 0}, - {-0.243011, 0.086191, 10.127466, 0}, - {-0.229843, 0.080206, 10.123875, 0}, - {-0.245406, 0.073023, 10.134649, 0}, - {-0.233435, 0.081403, 10.132255, 0}, - {-0.245406, 0.082600, 10.126269, 0}, - {-0.233435, 0.073023, 10.137043, 0}, - {-0.235829, 0.070629, 10.140635, 0}, - {-0.241814, 0.076614, 10.121481, 0}, - {-0.244208, 0.069432, 10.123875, 0}, - {-0.252588, 0.075417, 10.140635, 0}, - {-0.253785, 0.080206, 10.133451, 0}, - {-0.237026, 0.075417, 10.121481, 0}, - {-0.227449, 0.065841, 10.129861, 0}, - {-0.245406, 0.077812, 10.131058, 0}, - {-0.229843, 0.094571, 10.129861, 0}, - {-0.237026, 0.068235, 10.105919, 0}, - {-0.260968, 0.073023, 10.120284, 0}, - {-0.241814, 0.076614, 10.131058, 0}, - {-0.250194, 0.077812, 10.126269, 0}, - {-0.254982, 0.068235, 10.135846, 0}, - {-0.240617, 0.071826, 10.108313, 0}, - {-0.258574, 0.083797, 10.125072, 0}, - {-0.254982, 0.081403, 10.132255, 0}, - {-0.251391, 0.079009, 10.135846, 0}, - {-0.245406, 0.069432, 10.121481, 0}, - {-0.232237, 0.069432, 10.122678, 0}, - {-0.234632, 0.083797, 10.131058, 0}, - {-0.234632, 0.089783, 10.129861, 0}, - {-0.238223, 0.079009, 10.127466, 0}, - {-0.246603, 0.083797, 10.121481, 0}, - {-0.247800, 0.074220, 10.121481, 0}, - {-0.247800, 0.075417, 10.117889, 0}, - {-0.235829, 0.065841, 10.129861, 0}, - {-0.241814, 0.075417, 10.111904, 0}, - {-0.239420, 0.081403, 10.129861, 0}, - {-0.247800, 0.087388, 10.128663, 0}, - {-0.243011, 0.079009, 10.126269, 0}, - {-0.245406, 0.067038, 10.137043, 0}, - {-0.257377, 0.059855, 10.122678, 0}, - {-0.250194, 0.068235, 10.147817, 0}, - {-0.243011, 0.074220, 10.129861, 0}, - {-0.237026, 0.086191, 10.129861, 0}, - {-0.246603, 0.107739, 10.131058, 0}, - {-0.241814, 0.082600, 10.141831, 0}, - {-0.245406, 0.064643, 10.119086, 0}, - {-0.258574, 0.075417, 10.129861, 0}, - {-0.237026, 0.071826, 10.123875, 0}, - {-0.243011, 0.075417, 10.101130, 0}, - {-0.253785, 0.083797, 10.125072, 0}, - {-0.241814, 0.081403, 10.119086, 0}, - {-0.234632, 0.089783, 10.137043, 0}, - {-0.245406, 0.070629, 10.132255, 0}, - {-0.251391, 0.067038, 10.131058, 0}, - {-0.250194, 0.069432, 10.139438, 0}, - {-0.237026, 0.086191, 10.123875, 0}, - {-0.235829, 0.086191, 10.147817, 0}, - {-0.248997, 0.074220, 10.123875, 0}, - {-0.251391, 0.079009, 10.114298, 0}, - {-0.246603, 0.081403, 10.122678, 0}, - {-0.235829, 0.079009, 10.119086, 0}, - {-0.240617, 0.087388, 10.127466, 0}, - {-0.239420, 0.077812, 10.133451, 0}, - {-0.247800, 0.087388, 10.108313, 0}, - {-0.245406, 0.087388, 10.111904, 0}, - {-0.237026, 0.073023, 10.147817, 0}, - {-0.241814, 0.079009, 10.135846, 0}, - {-0.241814, 0.074220, 10.121481, 0}, - {-0.258574, 0.063446, 10.146620, 0}, - {-0.243011, 0.079009, 10.123875, 0}, - {-0.225055, 0.073023, 10.122678, 0}, - {-0.234632, 0.075417, 10.119086, 0}, - {-0.246603, 0.068235, 10.134649, 0}, - {-0.235829, 0.071826, 10.141831, 0}, - {-0.234632, 0.069432, 10.137043, 0}, - {-0.244208, 0.064643, 10.126269, 0}, - {-0.239420, 0.068235, 10.125072, 0}, - {-0.246603, 0.087388, 10.131058, 0}, - {-0.241814, 0.071826, 10.128663, 0}, - {-0.241814, 0.083797, 10.140635, 0}, - {-0.252588, 0.070629, 10.119086, 0}, - {-0.243011, 0.070629, 10.117889, 0}, - {-0.265756, 0.077812, 10.125072, 0}, - {-0.248997, 0.083797, 10.129861, 0}, - {-0.248997, 0.082600, 10.122678, 0}, - {-0.247800, 0.083797, 10.133451, 0}, - {-0.260968, 0.086191, 10.141831, 0}, - {-0.244208, 0.075417, 10.132255, 0}, - {-0.232237, 0.080206, 10.135846, 0}, - {-0.244208, 0.077812, 10.131058, 0}, - {-0.239420, 0.077812, 10.143028, 0}, - {-0.238223, 0.077812, 10.127466, 0}, - {-0.235829, 0.089783, 10.140635, 0}, - {-0.239420, 0.070629, 10.111904, 0}, - {-0.253785, 0.064643, 10.129861, 0}, - {-0.250194, 0.065841, 10.127466, 0}, - {-0.251391, 0.073023, 10.110707, 0}, - {-0.240617, 0.069432, 10.098736, 0}, - {-0.246603, 0.074220, 10.122678, 0}, - {-0.243011, 0.077812, 10.141831, 0}, - {-0.243011, 0.074220, 10.131058, 0}, - {-0.247800, 0.081403, 10.125072, 0}, - {-0.256179, 0.057461, 10.134649, 0}, - {-0.243011, 0.068235, 10.144226, 0}, - {-0.228646, 0.095768, 10.125072, 0}, - {-0.250194, 0.083797, 10.135846, 0}, - {-0.246603, 0.062249, 10.122678, 0}, - {-0.245406, 0.073023, 10.119086, 0}, - {-0.246603, 0.081403, 10.122678, 0}, - {-0.246603, 0.080206, 10.129861, 0}, - {-0.231040, 0.067038, 10.116693, 0}, - {-0.228646, 0.074220, 10.129861, 0}, - {-0.235829, 0.073023, 10.134649, 0}, - {-0.246603, 0.093374, 10.123875, 0}, - {-0.252588, 0.080206, 10.127466, 0}, - {-0.233435, 0.061052, 10.133451, 0}, - {-0.243011, 0.070629, 10.137043, 0}, - {-0.250194, 0.077812, 10.108313, 0}, - {-0.235829, 0.083797, 10.121481, 0}, - {-0.247800, 0.081403, 10.141831, 0}, - {-0.252588, 0.081403, 10.131058, 0}, - {-0.243011, 0.080206, 10.126269, 0}, - {-0.235829, 0.070629, 10.109509, 0}, - {-0.237026, 0.073023, 10.135846, 0}, - {-0.237026, 0.074220, 10.123875, 0}, - {-0.253785, 0.089783, 10.117889, 0}, - {-0.248997, 0.087388, 10.123875, 0}, - {-0.228646, 0.073023, 10.128663, 0}, - {-0.233435, 0.073023, 10.137043, 0}, - {-0.247800, 0.080206, 10.123875, 0}, - {-0.254982, 0.074220, 10.132255, 0}, - {-0.234632, 0.081403, 10.113101, 0}, - {-0.241814, 0.074220, 10.149014, 0}, - {-0.244208, 0.064643, 10.119086, 0}, - {-0.235829, 0.069432, 10.121481, 0}, - {-0.237026, 0.071826, 10.123875, 0}, - {-0.241814, 0.065841, 10.134649, 0}, - {-0.237026, 0.065841, 10.153803, 0}, - {-0.239420, 0.077812, 10.135846, 0}, - {-0.244208, 0.073023, 10.125072, 0}, - {-0.246603, 0.065841, 10.117889, 0}, - {-0.237026, 0.073023, 10.129861, 0}, - {-0.254982, 0.080206, 10.111904, 0}, - {-0.241814, 0.076614, 10.140635, 0}, - {-0.243011, 0.057461, 10.123875, 0}, - {-0.241814, 0.081403, 10.139438, 0}, - {-0.246603, 0.070629, 10.131058, 0}, - {-0.251391, 0.075417, 10.147817, 0}, - {-0.251391, 0.070629, 10.120284, 0}, - {-0.234632, 0.086191, 10.137043, 0}, - {-0.235829, 0.079009, 10.119086, 0}, - {-0.235829, 0.086191, 10.119086, 0}, - {-0.234632, 0.069432, 10.121481, 0}, - {-0.246603, 0.069432, 10.126269, 0}, - {-0.245406, 0.083797, 10.145423, 0}, - {-0.245406, 0.077812, 10.116693, 0}, - {-0.240617, 0.079009, 10.144226, 0}, - {-0.237026, 0.073023, 10.134649, 0}, - {-0.238223, 0.077812, 10.140635, 0}, - {-0.227449, 0.082600, 10.127466, 0}, - {-0.233435, 0.092177, 10.122678, 0}, - {-0.246603, 0.083797, 10.140635, 0}, - {-0.229843, 0.065841, 10.134649, 0}, - {-0.227449, 0.080206, 10.138240, 0}, - {-0.243011, 0.077812, 10.138240, 0}, - {-0.240617, 0.076614, 10.119086, 0}, - {-0.241814, 0.073023, 10.125072, 0}, - {-0.240617, 0.071826, 10.123875, 0}, - {-0.250194, 0.079009, 10.117889, 0}, - {-0.243011, 0.080206, 10.145423, 0}, - {-0.252588, 0.081403, 10.119086, 0}, - {-0.240617, 0.068235, 10.132255, 0}, - {-0.244208, 0.065841, 10.114298, 0}, - {-0.235829, 0.073023, 10.125072, 0}, - {-0.248997, 0.076614, 10.117889, 0}, - {-0.250194, 0.059855, 10.121481, 0}, - {-0.239420, 0.095768, 10.147817, 0}, - {-0.262165, 0.081403, 10.116693, 0}, - {-0.253785, 0.065841, 10.149014, 0}, - {-0.244208, 0.067038, 10.115496, 0}, - {-0.238223, 0.074220, 10.122678, 0}, - {-0.235829, 0.075417, 10.149014, 0}, - {-0.243011, 0.062249, 10.144226, 0}, - {-0.244208, 0.073023, 10.123875, 0}, - {-0.239420, 0.084994, 10.132255, 0}, - {-0.238223, 0.074220, 10.120284, 0}, - {-0.256179, 0.063446, 10.137043, 0}, - {-0.243011, 0.061052, 10.117889, 0}, - {-0.235829, 0.064643, 10.119086, 0}, - {-0.235829, 0.079009, 10.133451, 0}, - {-0.237026, 0.082600, 10.119086, 0}, - {-0.238223, 0.079009, 10.139438, 0}, - {-0.247800, 0.065841, 10.117889, 0}, - {-0.243011, 0.069432, 10.158591, 0}, - {-0.246603, 0.080206, 10.122678, 0}, - {-0.256179, 0.083797, 10.141831, 0}, - {-0.235829, 0.092177, 10.108313, 0}, - {-0.237026, 0.061052, 10.132255, 0}, - {-0.237026, 0.058658, 10.156197, 0}, - {-0.244208, 0.059855, 10.117889, 0}, - {-0.237026, 0.087388, 10.144226, 0}, - {-0.257377, 0.094571, 10.110707, 0}, - {-0.256179, 0.080206, 10.132255, 0}, - {-0.243011, 0.089783, 10.133451, 0}, - {-0.238223, 0.080206, 10.133451, 0}, - {-0.240617, 0.067038, 10.114298, 0}, - {-0.246603, 0.064643, 10.133451, 0}, - {-0.245406, 0.075417, 10.128663, 0}, - {-0.240617, 0.071826, 10.122678, 0}, - {-0.229843, 0.068235, 10.126269, 0}, - {-0.240617, 0.081403, 10.123875, 0}, - {-0.244208, 0.079009, 10.138240, 0}, - {-0.237026, 0.065841, 10.145423, 0}, - {-0.239420, 0.069432, 10.133451, 0}, - {-0.253785, 0.076614, 10.127466, 0}, - {-0.256179, 0.082600, 10.125072, 0}, - {-0.232237, 0.081403, 10.113101, 0}, - {-0.239420, 0.065841, 10.139438, 0}, - {-0.241814, 0.084994, 10.128663, 0}, - {-0.252588, 0.071826, 10.122678, 0}, - {-0.243011, 0.067038, 10.157393, 0}, - {-0.251391, 0.081403, 10.134649, 0}, - {-0.251391, 0.083797, 10.127466, 0}, - {-0.265756, 0.074220, 10.115496, 0}, - {-0.245406, 0.062249, 10.150211, 0}, - {-0.241814, 0.070629, 10.117889, 0}, - {-0.257377, 0.083797, 10.120284, 0}, - {-0.239420, 0.081403, 10.121481, 0}, - {-0.247800, 0.068235, 10.135846, 0}, - {-0.243011, 0.071826, 10.129861, 0}, - {-0.235829, 0.082600, 10.128663, 0}, - {-0.247800, 0.073023, 10.145423, 0}, - {-0.258574, 0.065841, 10.123875, 0}, - {-0.233435, 0.069432, 10.122678, 0}, - {-0.245406, 0.076614, 10.120284, 0}, - {-0.247800, 0.089783, 10.131058, 0}, - {-0.244208, 0.090980, 10.114298, 0}, - {-0.247800, 0.089783, 10.143028, 0}, - {-0.229843, 0.073023, 10.119086, 0}, - {-0.240617, 0.082600, 10.134649, 0}, - {-0.244208, 0.095768, 10.125072, 0}, - {-0.241814, 0.083797, 10.145423, 0}, - {-0.250194, 0.068235, 10.139438, 0}, - {-0.248997, 0.075417, 10.113101, 0}, - {-0.250194, 0.076614, 10.128663, 0}, - {-0.247800, 0.081403, 10.114298, 0}, - {-0.247800, 0.075417, 10.123875, 0}, - {-0.248997, 0.095768, 10.145423, 0}, - {-0.245406, 0.088585, 10.143028, 0}, - {-0.238223, 0.084994, 10.113101, 0}, - {-0.240617, 0.071826, 10.126269, 0}, - {-0.240617, 0.067038, 10.140635, 0}, - {-0.245406, 0.071826, 10.138240, 0}, - {-0.254982, 0.073023, 10.128663, 0}, - {-0.245406, 0.077812, 10.145423, 0}, - {-0.250194, 0.070629, 10.127466, 0}, - {-0.243011, 0.073023, 10.137043, 0}, - {-0.245406, 0.067038, 10.117889, 0}, - {-0.243011, 0.071826, 10.151408, 0}, - {-0.252588, 0.081403, 10.128663, 0}, - {-0.233435, 0.074220, 10.110707, 0}, - {-0.243011, 0.074220, 10.126269, 0}, - {-0.239420, 0.089783, 10.143028, 0}, - {-0.237026, 0.086191, 10.123875, 0}, - {-0.243011, 0.064643, 10.129861, 0}, - {-0.234632, 0.077812, 10.133451, 0}, - {-0.250194, 0.086191, 10.133451, 0}, - {-0.241814, 0.074220, 10.125072, 0}, - {-0.243011, 0.086191, 10.122678, 0}, - {-0.234632, 0.076614, 10.121481, 0}, - {-0.251391, 0.082600, 10.135846, 0}, - {-0.251391, 0.084994, 10.133451, 0}, - {-0.245406, 0.063446, 10.117889, 0}, - {-0.253785, 0.079009, 10.122678, 0}, - {-0.243011, 0.074220, 10.129861, 0}, - {-0.233435, 0.069432, 10.127466, 0}, - {-0.251391, 0.077812, 10.126269, 0}, - {-0.245406, 0.079009, 10.120284, 0}, - {-0.247800, 0.068235, 10.128663, 0}, - {-0.244208, 0.069432, 10.133451, 0}, - {-0.238223, 0.074220, 10.146620, 0}, - {-0.241814, 0.080206, 10.120284, 0}, - {-0.248997, 0.071826, 10.107116, 0}, - {-0.240617, 0.073023, 10.123875, 0}, - {-0.239420, 0.063446, 10.135846, 0}, - {-0.245406, 0.068235, 10.117889, 0}, - {-0.248997, 0.088585, 10.105919, 0}, - {-0.248997, 0.067038, 10.138240, 0}, - {-0.247800, 0.074220, 10.128663, 0}, - {-0.237026, 0.079009, 10.138240, 0}, - {-0.243011, 0.092177, 10.140635, 0}, - {-0.235829, 0.082600, 10.128663, 0}, - {-0.240617, 0.079009, 10.116693, 0}, - {-0.248997, 0.087388, 10.114298, 0}, - {-0.238223, 0.079009, 10.120284, 0}, - {-0.241814, 0.087388, 10.128663, 0}, - {-0.250194, 0.063446, 10.129861, 0}, - {-0.245406, 0.071826, 10.128663, 0}, - {-0.251391, 0.073023, 10.123875, 0}, - {-0.258574, 0.084994, 10.137043, 0}, - {-0.246603, 0.077812, 10.140635, 0}, - {-0.244208, 0.070629, 10.111904, 0}, - {-0.252588, 0.075417, 10.143028, 0}, - {-0.248997, 0.069432, 10.117889, 0}, - {-0.243011, 0.073023, 10.129861, 0}, - {-0.238223, 0.079009, 10.143028, 0}, - {-0.238223, 0.080206, 10.114298, 0}, - {-0.241814, 0.074220, 10.132255, 0}, - {-0.240617, 0.065841, 10.132255, 0}, - {-0.247800, 0.069432, 10.134649, 0}, - {-0.251391, 0.075417, 10.132255, 0}, - {-0.238223, 0.086191, 10.115496, 0}, - {-0.245406, 0.076614, 10.139438, 0}, - {-0.240617, 0.073023, 10.123875, 0}, - {-0.238223, 0.071826, 10.137043, 0}, - {-0.245406, 0.076614, 10.135846, 0}, - {-0.251391, 0.081403, 10.133451, 0}, - {-0.251391, 0.086191, 10.134649, 0}, - {-0.248997, 0.079009, 10.115496, 0}, - {-0.256179, 0.067038, 10.133451, 0}, - {-0.246603, 0.068235, 10.121481, 0}, - {-0.244208, 0.082600, 10.135846, 0}, - {-0.250194, 0.079009, 10.122678, 0}, - {-0.252588, 0.079009, 10.120284, 0}, - {-0.243011, 0.083797, 10.127466, 0}, - {-0.243011, 0.071826, 10.119086, 0}, - {-0.251391, 0.081403, 10.128663, 0}, - {-0.252588, 0.065841, 10.122678, 0}, - {-0.240617, 0.079009, 10.131058, 0}, - {-0.253785, 0.082600, 10.121481, 0}, - {-0.256179, 0.071826, 10.140635, 0}, - {-0.263362, 0.070629, 10.123875, 0}, - {-0.248997, 0.074220, 10.123875, 0}, - {-0.235829, 0.064643, 10.125072, 0}, - {-0.238223, 0.082600, 10.125072, 0}, - {-0.238223, 0.077812, 10.108313, 0}, - {-0.231040, 0.071826, 10.117889, 0}, - {-0.250194, 0.093374, 10.122678, 0}, - {-0.241814, 0.080206, 10.123875, 0}, - {-0.258574, 0.073023, 10.117889, 0}, - {-0.248997, 0.071826, 10.127466, 0}, - {-0.246603, 0.067038, 10.146620, 0}, - {-0.248997, 0.074220, 10.126269, 0}, - {-0.248997, 0.071826, 10.133451, 0}, - {-0.247800, 0.080206, 10.133451, 0}, - {-0.239420, 0.076614, 10.138240, 0}, - {-0.248997, 0.081403, 10.127466, 0}, - {-0.248997, 0.076614, 10.137043, 0}, - {-0.248997, 0.080206, 10.123875, 0}, - {-0.239420, 0.067038, 10.141831, 0}, - {-0.235829, 0.083797, 10.119086, 0}, - {-0.247800, 0.069432, 10.134649, 0}, - {-0.237026, 0.087388, 10.137043, 0}, - {-0.246603, 0.073023, 10.131058, 0}, - {-0.251391, 0.083797, 10.135846, 0}, - {-0.247800, 0.071826, 10.121481, 0}, - {-0.246603, 0.076614, 10.128663, 0}, - {-0.251391, 0.082600, 10.114298, 0}, - {-0.254982, 0.082600, 10.134649, 0}, - {-0.237026, 0.084994, 10.117889, 0}, - {-0.229843, 0.077812, 10.119086, 0}, - {-0.246603, 0.070629, 10.125072, 0}, - {-0.235829, 0.076614, 10.140635, 0}, - {-0.245406, 0.061052, 10.122678, 0}, - {-0.240617, 0.076614, 10.119086, 0}, - {-0.259771, 0.088585, 10.126269, 0}, - {-0.241814, 0.077812, 10.139438, 0}, - {-0.244208, 0.075417, 10.116693, 0}, - {-0.239420, 0.067038, 10.109509, 0}, - {-0.241814, 0.083797, 10.134649, 0}, - {-0.244208, 0.067038, 10.125072, 0}, - {-0.244208, 0.073023, 10.149014, 0}, - {-0.243011, 0.084994, 10.116693, 0}, - {-0.231040, 0.076614, 10.123875, 0}, - {-0.247800, 0.089783, 10.120284, 0}, - {-0.246603, 0.077812, 10.122678, 0}, - {-0.262165, 0.077812, 10.120284, 0}, - {-0.231040, 0.070629, 10.115496, 0}, - {-0.243011, 0.077812, 10.149014, 0}, - {-0.248997, 0.090980, 10.119086, 0}, - {-0.250194, 0.090980, 10.132255, 0}, - {-0.238223, 0.074220, 10.120284, 0}, - {-0.228646, 0.080206, 10.140635, 0}, - {-0.245406, 0.075417, 10.113101, 0}, - {-0.233435, 0.089783, 10.131058, 0}, - {-0.244208, 0.081403, 10.117889, 0}, - {-0.246603, 0.063446, 10.141831, 0}, - {-0.235829, 0.090980, 10.143028, 0}, - {-0.233435, 0.081403, 10.125072, 0}, - {-0.251391, 0.077812, 10.127466, 0}, - {-0.238223, 0.081403, 10.125072, 0}, - {-0.235829, 0.074220, 10.132255, 0}, - {-0.244208, 0.064643, 10.119086, 0}, - {-0.256179, 0.071826, 10.143028, 0}, - {-0.240617, 0.082600, 10.110707, 0}, - {-0.248997, 0.071826, 10.137043, 0}, - {-0.251391, 0.076614, 10.125072, 0}, - {-0.228646, 0.082600, 10.134649, 0}, - {-0.233435, 0.082600, 10.111904, 0}, - {-0.246603, 0.068235, 10.119086, 0}, - {-0.235829, 0.067038, 10.143028, 0}, - {-0.241814, 0.079009, 10.126269, 0}, - {-0.238223, 0.095768, 10.125072, 0}, - {-0.243011, 0.065841, 10.105919, 0}, - {-0.256179, 0.081403, 10.132255, 0}, - {-0.256179, 0.073023, 10.110707, 0}, - {-0.246603, 0.079009, 10.145423, 0}, - {-0.231040, 0.069432, 10.122678, 0}, - {-0.234632, 0.065841, 10.139438, 0}, - {-0.232237, 0.094571, 10.126269, 0}, - {-0.243011, 0.081403, 10.149014, 0}, - {-0.256179, 0.083797, 10.132255, 0}, - {-0.246603, 0.073023, 10.127466, 0}, - {-0.244208, 0.067038, 10.131058, 0}, - {-0.244208, 0.082600, 10.133451, 0}, - {-0.239420, 0.088585, 10.137043, 0}, - {-0.234632, 0.069432, 10.123875, 0}, - {-0.241814, 0.069432, 10.137043, 0}, - {-0.241814, 0.083797, 10.120284, 0}, - {-0.243011, 0.075417, 10.134649, 0}, - {-0.250194, 0.075417, 10.132255, 0}, - {-0.240617, 0.076614, 10.126269, 0}, - {-0.265756, 0.083797, 10.137043, 0}, - {-0.258574, 0.079009, 10.116693, 0}, - {-0.237026, 0.069432, 10.122678, 0}, - {-0.248997, 0.073023, 10.121481, 0}, - {-0.256179, 0.080206, 10.123875, 0}, - {-0.248997, 0.067038, 10.122678, 0}, - {-0.237026, 0.083797, 10.143028, 0}, - {-0.238223, 0.080206, 10.114298, 0}, - {-0.253785, 0.074220, 10.129861, 0}, - {-0.250194, 0.075417, 10.129861, 0}, - {-0.254982, 0.081403, 10.151408, 0}, - {-0.250194, 0.070629, 10.135846, 0}, - {-0.247800, 0.075417, 10.120284, 0}, - {-0.241814, 0.064643, 10.139438, 0}, - {-0.246603, 0.071826, 10.138240, 0}, - {-0.243011, 0.079009, 10.152605, 0}, - {-0.241814, 0.080206, 10.127466, 0}, - {-0.251391, 0.070629, 10.129861, 0}, - {-0.243011, 0.081403, 10.139438, 0}, - {-0.251391, 0.070629, 10.129861, 0}, - {-0.251391, 0.076614, 10.122678, 0}, - {-0.252588, 0.079009, 10.133451, 0}, - {-0.254982, 0.073023, 10.128663, 0}, - {-0.232237, 0.067038, 10.113101, 0}, - {-0.239420, 0.088585, 10.120284, 0}, - {-0.245406, 0.080206, 10.113101, 0}, - {-0.238223, 0.075417, 10.131058, 0}, - {-0.244208, 0.065841, 10.109509, 0}, - {-0.235829, 0.068235, 10.141831, 0}, - {-0.251391, 0.081403, 10.121481, 0}, - {-0.250194, 0.077812, 10.119086, 0}, - {-0.241814, 0.071826, 10.126269, 0}, - {-0.233435, 0.069432, 10.135846, 0}, - {-0.239420, 0.076614, 10.131058, 0}, - {-0.239420, 0.088585, 10.107116, 0}, - {-0.234632, 0.084994, 10.126269, 0}, - {-0.247800, 0.077812, 10.128663, 0}, - {-0.246603, 0.083797, 10.137043, 0}, - {-0.240617, 0.087388, 10.127466, 0}, - {-0.256179, 0.070629, 10.117889, 0}, - {-0.243011, 0.077812, 10.121481, 0}, - {-0.243011, 0.083797, 10.133451, 0}, - {-0.252588, 0.087388, 10.125072, 0}, - {-0.256179, 0.073023, 10.127466, 0}, - {-0.239420, 0.057461, 10.128663, 0}, - {-0.243011, 0.070629, 10.117889, 0}, - {-0.252588, 0.074220, 10.138240, 0}, - {-0.243011, 0.073023, 10.127466, 0}, - {-0.238223, 0.082600, 10.133451, 0}, - {-0.235829, 0.074220, 10.143028, 0}, - {-0.248997, 0.065841, 10.153803, 0}, - {-0.240617, 0.081403, 10.107116, 0}, - {-0.241814, 0.087388, 10.123875, 0}, - {-0.241814, 0.070629, 10.141831, 0}, - {-0.238223, 0.074220, 10.113101, 0}, - {-0.251391, 0.079009, 10.129861, 0}, - {-0.253785, 0.082600, 10.108313, 0}, - {-0.254982, 0.075417, 10.121481, 0}, - {-0.247800, 0.057461, 10.133451, 0}, - {-0.243011, 0.058658, 10.128663, 0}, - {-0.244208, 0.080206, 10.120284, 0}, - {-0.231040, 0.079009, 10.109509, 0}, - {-0.256179, 0.070629, 10.120284, 0}, - {-0.251391, 0.082600, 10.143028, 0}, - {-0.233435, 0.068235, 10.128663, 0}, - {-0.241814, 0.068235, 10.129861, 0}, - {-0.235829, 0.083797, 10.111904, 0}, - {-0.238223, 0.067038, 10.139438, 0}, - {-0.260968, 0.063446, 10.128663, 0}, - {-0.231040, 0.084994, 10.140635, 0}, - {-0.237026, 0.082600, 10.134649, 0}, - {-0.246603, 0.070629, 10.144226, 0}, - {-0.246603, 0.080206, 10.125072, 0}, - {-0.244208, 0.087388, 10.122678, 0}, - {-0.234632, 0.069432, 10.111904, 0}, - {-0.252588, 0.065841, 10.121481, 0}, - {-0.245406, 0.071826, 10.128663, 0}, - {-0.243011, 0.075417, 10.129861, 0}, - {-0.238223, 0.068235, 10.139438, 0}, - {-0.256179, 0.076614, 10.126269, 0}, - {-0.246603, 0.083797, 10.131058, 0}, - {-0.248997, 0.080206, 10.116693, 0}, - {-0.241814, 0.082600, 10.123875, 0}, - {-0.262165, 0.075417, 10.113101, 0}, - {-0.240617, 0.079009, 10.134649, 0}, - {-0.244208, 0.077812, 10.121481, 0}, - {-0.246603, 0.068235, 10.141831, 0}, - {-0.252588, 0.075417, 10.120284, 0}, - {-0.247800, 0.084994, 10.104721, 0}, - {-0.241814, 0.086191, 10.126269, 0}, - {-0.237026, 0.082600, 10.117889, 0}, - {-0.243011, 0.070629, 10.117889, 0}, - {-0.239420, 0.070629, 10.135846, 0}, - {-0.237026, 0.065841, 10.120284, 0}, - {-0.237026, 0.061052, 10.125072, 0}, - {-0.235829, 0.061052, 10.114298, 0}, - {-0.252588, 0.074220, 10.137043, 0}, - {-0.253785, 0.086191, 10.119086, 0}, - {-0.252588, 0.089783, 10.129861, 0}, - {-0.245406, 0.084994, 10.126269, 0}, - {-0.232237, 0.076614, 10.120284, 0}, - {-0.252588, 0.082600, 10.119086, 0}, - {-0.251391, 0.064643, 10.132255, 0}, - {-0.227449, 0.076614, 10.149014, 0}, - {-0.259771, 0.083797, 10.131058, 0}, - {-0.248997, 0.075417, 10.127466, 0}, - {-0.244208, 0.071826, 10.133451, 0}, - {-0.243011, 0.070629, 10.132255, 0}, - {-0.228646, 0.076614, 10.128663, 0}, - {-0.241814, 0.089783, 10.138240, 0}, - {-0.252588, 0.086191, 10.122678, 0}, - {-0.254982, 0.068235, 10.133451, 0}, - {-0.250194, 0.071826, 10.150211, 0}, - {-0.235829, 0.084994, 10.140635, 0}, - {-0.234632, 0.087388, 10.139438, 0}, - {-0.245406, 0.077812, 10.105919, 0}, - {-0.250194, 0.080206, 10.107116, 0}, - {-0.240617, 0.092177, 10.132255, 0}, - {-0.243011, 0.077812, 10.133451, 0}, - {-0.248997, 0.062249, 10.128663, 0}, - {-0.245406, 0.068235, 10.125072, 0}, - {-0.250194, 0.064643, 10.129861, 0}, - {-0.248997, 0.082600, 10.126269, 0}, - {-0.252588, 0.073023, 10.141831, 0}, - {-0.250194, 0.076614, 10.127466, 0}, - {-0.251391, 0.077812, 10.121481, 0}, - {-0.250194, 0.069432, 10.134649, 0}, - {-0.232237, 0.065841, 10.131058, 0}, - {-0.233435, 0.081403, 10.131058, 0}, - {-0.241814, 0.074220, 10.111904, 0}, - {-0.248997, 0.064643, 10.135846, 0}, - {-0.239420, 0.081403, 10.143028, 0}, - {-0.239420, 0.077812, 10.138240, 0}, - {-0.237026, 0.074220, 10.110707, 0}, - {-0.235829, 0.081403, 10.121481, 0}, - {-0.247800, 0.063446, 10.129861, 0}, - {-0.235829, 0.068235, 10.121481, 0}, - {-0.238223, 0.064643, 10.123875, 0}, - {-0.246603, 0.070629, 10.132255, 0}, - {-0.264559, 0.073023, 10.145423, 0}, - {-0.247800, 0.065841, 10.116693, 0}, - {-0.247800, 0.084994, 10.125072, 0}, - {-0.225055, 0.080206, 10.115496, 0}, - {-0.233435, 0.064643, 10.135846, 0}, - {-0.247800, 0.069432, 10.131058, 0}, - {-0.234632, 0.081403, 10.125072, 0}, - {-0.246603, 0.081403, 10.128663, 0}, - {-0.235829, 0.086191, 10.117889, 0}, - {-0.233435, 0.077812, 10.122678, 0}, - {-0.256179, 0.049081, 10.128663, 0}, - {-0.243011, 0.083797, 10.138240, 0}, - {-0.239420, 0.087388, 10.129861, 0}, - {-0.238223, 0.068235, 10.131058, 0}, - {-0.234632, 0.068235, 10.129861, 0}, - {-0.250194, 0.080206, 10.135846, 0}, - {-0.246603, 0.062249, 10.131058, 0}, - {-0.243011, 0.076614, 10.134649, 0}, - {-0.246603, 0.093374, 10.128663, 0}, - {-0.251391, 0.065841, 10.126269, 0}, - {-0.235829, 0.069432, 10.135846, 0}, - {-0.243011, 0.081403, 10.120284, 0}, - {-0.245406, 0.086191, 10.129861, 0}, - {-0.234632, 0.073023, 10.110707, 0}, - {-0.244208, 0.083797, 10.140635, 0}, - {-0.247800, 0.069432, 10.141831, 0}, - {-0.240617, 0.076614, 10.149014, 0}, - {-0.243011, 0.081403, 10.122678, 0}, - {-0.237026, 0.071826, 10.120284, 0}, - {-0.234632, 0.073023, 10.120284, 0}, - {-0.237026, 0.077812, 10.131058, 0}, - {-0.244208, 0.080206, 10.152605, 0}, - {-0.250194, 0.076614, 10.135846, 0}, - {-0.253785, 0.069432, 10.131058, 0}, - {-0.260968, 0.073023, 10.141831, 0}, - {-0.247800, 0.070629, 10.134649, 0}, - {-0.257377, 0.068235, 10.125072, 0}, - {-0.243011, 0.073023, 10.121481, 0}, - {-0.235829, 0.082600, 10.127466, 0}, - {-0.237026, 0.070629, 10.139438, 0}, - {-0.227449, 0.081403, 10.127466, 0}, - {-0.239420, 0.080206, 10.141831, 0}, - {-0.251391, 0.069432, 10.129861, 0}, - {-0.238223, 0.069432, 10.121481, 0}, - {-0.237026, 0.069432, 10.126269, 0}, - {-0.250194, 0.077812, 10.114298, 0}, - {-0.237026, 0.094571, 10.116693, 0}, - {-0.253785, 0.084994, 10.143028, 0}, - {-0.263362, 0.071826, 10.123875, 0}, - {-0.246603, 0.064643, 10.126269, 0}, - {-0.240617, 0.059855, 10.131058, 0}, - {-0.247800, 0.070629, 10.139438, 0}, - {-0.240617, 0.082600, 10.132255, 0}, - {-0.234632, 0.073023, 10.111904, 0}, - {-0.240617, 0.062249, 10.131058, 0}, - {-0.238223, 0.080206, 10.129861, 0}, - {-0.243011, 0.076614, 10.123875, 0}, - {-0.246603, 0.080206, 10.125072, 0}, - {-0.235829, 0.079009, 10.127466, 0}, - {-0.243011, 0.076614, 10.110707, 0}, - {-0.246603, 0.065841, 10.128663, 0}, - {-0.246603, 0.076614, 10.133451, 0}, - {-0.253785, 0.080206, 10.123875, 0}, - {-0.241814, 0.073023, 10.119086, 0}, - {-0.250194, 0.075417, 10.120284, 0}, - {-0.235829, 0.079009, 10.143028, 0}, - {-0.241814, 0.071826, 10.135846, 0}, - {-0.254982, 0.077812, 10.125072, 0}, - {-0.238223, 0.077812, 10.122678, 0}, - {-0.235829, 0.071826, 10.132255, 0}, - {-0.238223, 0.084994, 10.120284, 0}, - {-0.253785, 0.075417, 10.146620, 0}, - {-0.254982, 0.069432, 10.141831, 0}, - {-0.240617, 0.087388, 10.126269, 0}, - {-0.251391, 0.088585, 10.115496, 0}, - {-0.256179, 0.065841, 10.129861, 0}, - {-0.243011, 0.069432, 10.127466, 0}, - {-0.246603, 0.063446, 10.134649, 0}, - {-0.246603, 0.073023, 10.128663, 0}, - {-0.240617, 0.068235, 10.119086, 0}, - {-0.257377, 0.069432, 10.143028, 0}, - {-0.245406, 0.081403, 10.128663, 0}, - {-0.252588, 0.075417, 10.120284, 0}, - {-0.241814, 0.068235, 10.111904, 0}, - {-0.238223, 0.075417, 10.141831, 0}, - {-0.240617, 0.071826, 10.111904, 0}, - {-0.247800, 0.067038, 10.126269, 0}, - {-0.247800, 0.068235, 10.134649, 0}, - {-0.238223, 0.084994, 10.139438, 0}, - {-0.237026, 0.090980, 10.141831, 0}, - {-0.245406, 0.068235, 10.109509, 0}, - {-0.256179, 0.076614, 10.143028, 0}, - {-0.237026, 0.080206, 10.116693, 0}, - {-0.228646, 0.079009, 10.134649, 0}, - {-0.247800, 0.071826, 10.121481, 0}, - {-0.241814, 0.075417, 10.129861, 0}, - {-0.228646, 0.076614, 10.152605, 0}, - {-0.238223, 0.087388, 10.125072, 0}, - {-0.239420, 0.075417, 10.128663, 0}, - {-0.247800, 0.074220, 10.114298, 0}, - {-0.219069, 0.080206, 10.126269, 0}, - {-0.234632, 0.082600, 10.109509, 0}, - {-0.244208, 0.063446, 10.127466, 0}, - {-0.247800, 0.068235, 10.134649, 0}, - {-0.245406, 0.069432, 10.139438, 0}, - {-0.251391, 0.086191, 10.128663, 0}, - {-0.244208, 0.065841, 10.127466, 0}, - {-0.246603, 0.070629, 10.125072, 0}, - {-0.240617, 0.081403, 10.125072, 0}, - {-0.232237, 0.063446, 10.141831, 0}, - {-0.247800, 0.065841, 10.126269, 0}, - {-0.235829, 0.086191, 10.133451, 0}, - {-0.245406, 0.096965, 10.121481, 0}, - {-0.239420, 0.090980, 10.121481, 0}, - {-0.248997, 0.077812, 10.125072, 0}, - {-0.231040, 0.067038, 10.126269, 0}, - {-0.245406, 0.081403, 10.125072, 0}, - {-0.231040, 0.074220, 10.145423, 0}, - {-0.253785, 0.067038, 10.115496, 0}, - {-0.246603, 0.065841, 10.110707, 0}, - {-0.245406, 0.069432, 10.131058, 0}, - {-0.232237, 0.076614, 10.113101, 0}, - {-0.243011, 0.075417, 10.121481, 0}, - {-0.243011, 0.079009, 10.132255, 0}, - {-0.238223, 0.079009, 10.123875, 0}, - {-0.245406, 0.069432, 10.122678, 0}, - {-0.247800, 0.075417, 10.126269, 0}, - {-0.239420, 0.079009, 10.139438, 0}, - {-0.244208, 0.083797, 10.105919, 0}, - {-0.245406, 0.071826, 10.109509, 0}, - {-0.233435, 0.076614, 10.128663, 0}, - {-0.243011, 0.088585, 10.131058, 0}, - {-0.252588, 0.069432, 10.117889, 0}, - {-0.248997, 0.090980, 10.119086, 0}, - {-0.241814, 0.074220, 10.129861, 0}, - {-0.253785, 0.068235, 10.135846, 0}, - {-0.240617, 0.074220, 10.125072, 0}, - {-0.246603, 0.076614, 10.131058, 0}, - {-0.238223, 0.081403, 10.117889, 0}, - {-0.246603, 0.074220, 10.127466, 0}, - {-0.250194, 0.070629, 10.133451, 0}, - {-0.248997, 0.073023, 10.132255, 0}, - {-0.250194, 0.077812, 10.122678, 0}, - {-0.259771, 0.077812, 10.123875, 0}, - {-0.234632, 0.079009, 10.123875, 0}, - {-0.241814, 0.073023, 10.120284, 0}, - {-0.251391, 0.063446, 10.146620, 0}, - {-0.250194, 0.074220, 10.113101, 0}, - {-0.256179, 0.082600, 10.119086, 0}, - {-0.257377, 0.080206, 10.132255, 0}, - {-0.245406, 0.090980, 10.127466, 0}, - {-0.243011, 0.075417, 10.133451, 0}, - {-0.239420, 0.088585, 10.125072, 0}, - {-0.241814, 0.079009, 10.127466, 0}, - {-0.251391, 0.070629, 10.137043, 0}, - {-0.235829, 0.081403, 10.110707, 0}, - {-0.248997, 0.075417, 10.141831, 0}, - {-0.231040, 0.087388, 10.125072, 0}, - {-0.247800, 0.068235, 10.127466, 0}, - {-0.252588, 0.086191, 10.119086, 0}, - {-0.240617, 0.071826, 10.127466, 0}, - {-0.243011, 0.081403, 10.144226, 0}, - {-0.243011, 0.083797, 10.126269, 0}, - {-0.251391, 0.074220, 10.127466, 0}, - {-0.239420, 0.084994, 10.125072, 0}, - {-0.231040, 0.069432, 10.113101, 0}, - {-0.246603, 0.069432, 10.138240, 0}, - {-0.243011, 0.075417, 10.132255, 0}, - {-0.243011, 0.084994, 10.113101, 0}, - {-0.253785, 0.082600, 10.120284, 0}, - {-0.247800, 0.070629, 10.125072, 0}, - {-0.244208, 0.079009, 10.113101, 0}, - {-0.260968, 0.073023, 10.127466, 0}, - {-0.239420, 0.063446, 10.128663, 0}, - {-0.234632, 0.082600, 10.122678, 0}, - {-0.240617, 0.079009, 10.132255, 0}, - {-0.251391, 0.069432, 10.133451, 0}, - {-0.252588, 0.073023, 10.131058, 0}, - {-0.239420, 0.059855, 10.121481, 0}, - {-0.238223, 0.079009, 10.122678, 0}, - {-0.229843, 0.070629, 10.115496, 0}, - {-0.246603, 0.074220, 10.128663, 0}, - {-0.235829, 0.079009, 10.121481, 0}, - {-0.237026, 0.076614, 10.146620, 0}, - {-0.244208, 0.077812, 10.117889, 0}, - {-0.258574, 0.070629, 10.133451, 0}, - {-0.259771, 0.077812, 10.119086, 0}, - {-0.246603, 0.083797, 10.133451, 0}, - {-0.241814, 0.076614, 10.127466, 0}, - {-0.253785, 0.077812, 10.116693, 0}, - {-0.256179, 0.075417, 10.123875, 0}, - {-0.254982, 0.074220, 10.120284, 0}, - {-0.252588, 0.070629, 10.114298, 0}, - {-0.256179, 0.074220, 10.128663, 0}, - {-0.237026, 0.071826, 10.139438, 0}, - {-0.235829, 0.069432, 10.108313, 0}, - {-0.250194, 0.074220, 10.116693, 0}, - {-0.241814, 0.073023, 10.131058, 0}, - {-0.234632, 0.075417, 10.147817, 0}, - {-0.238223, 0.067038, 10.111904, 0}, - {-0.251391, 0.071826, 10.128663, 0}, - {-0.239420, 0.087388, 10.134649, 0}, - {-0.237026, 0.082600, 10.128663, 0}, - {-0.240617, 0.089783, 10.133451, 0}, - {-0.245406, 0.081403, 10.119086, 0}, - {-0.241814, 0.080206, 10.128663, 0}, - {-0.235829, 0.062249, 10.140635, 0}, - {-0.235829, 0.065841, 10.128663, 0}, - {-0.237026, 0.092177, 10.128663, 0}, - {-0.244208, 0.082600, 10.122678, 0}, - {-0.247800, 0.065841, 10.127466, 0}, - {-0.243011, 0.070629, 10.113101, 0}, - {-0.238223, 0.068235, 10.123875, 0}, - {-0.241814, 0.077812, 10.107116, 0}, - {-0.238223, 0.088585, 10.132255, 0}, - {-0.234632, 0.067038, 10.127466, 0}, - {-0.243011, 0.075417, 10.117889, 0}, - {-0.240617, 0.077812, 10.132255, 0}, - {-0.240617, 0.079009, 10.120284, 0}, - {-0.239420, 0.074220, 10.125072, 0}, - {-0.233435, 0.071826, 10.132255, 0}, - {-0.241814, 0.083797, 10.126269, 0}, - {-0.258574, 0.089783, 10.127466, 0}, - {-0.234632, 0.081403, 10.131058, 0}, - {-0.252588, 0.071826, 10.137043, 0}, - {-0.240617, 0.064643, 10.127466, 0}, - {-0.248997, 0.070629, 10.133451, 0}, - {-0.246603, 0.087388, 10.132255, 0}, - {-0.250194, 0.075417, 10.132255, 0}, - {-0.244208, 0.073023, 10.126269, 0}, - {-0.241814, 0.079009, 10.120284, 0}, - {-0.251391, 0.083797, 10.128663, 0}, - {-0.234632, 0.080206, 10.145423, 0}, - {-0.250194, 0.074220, 10.140635, 0}, - {-0.247800, 0.062249, 10.116693, 0}, - {-0.243011, 0.077812, 10.125072, 0}, - {-0.247800, 0.064643, 10.126269, 0}, - {-0.244208, 0.071826, 10.145423, 0}, - {-0.253785, 0.070629, 10.123875, 0}, - {-0.237026, 0.077812, 10.133451, 0}, - {-0.246603, 0.082600, 10.117889, 0}, - {-0.245406, 0.086191, 10.121481, 0}, - {-0.235829, 0.073023, 10.117889, 0}, - {-0.243011, 0.075417, 10.134649, 0}, - {-0.239420, 0.087388, 10.139438, 0}, - {-0.227449, 0.084994, 10.135846, 0}, - {-0.240617, 0.083797, 10.133451, 0}, - {-0.243011, 0.073023, 10.117889, 0}, - {-0.228646, 0.082600, 10.144226, 0}, - {-0.240617, 0.068235, 10.104721, 0}, - {-0.241814, 0.059855, 10.127466, 0}, - {-0.243011, 0.081403, 10.116693, 0}, - {-0.238223, 0.080206, 10.147817, 0}, - {-0.244208, 0.076614, 10.119086, 0}, - {-0.241814, 0.073023, 10.119086, 0}, - {-0.251391, 0.075417, 10.131058, 0}, - {-0.244208, 0.071826, 10.127466, 0}, - {-0.233435, 0.082600, 10.146620, 0}, - {-0.250194, 0.070629, 10.120284, 0}, - {-0.248997, 0.067038, 10.135846, 0}, - {-0.233435, 0.077812, 10.109509, 0}, - {-0.243011, 0.083797, 10.133451, 0}, - {-0.251391, 0.069432, 10.111904, 0}, - {-0.234632, 0.076614, 10.138240, 0}, - {-0.241814, 0.086191, 10.120284, 0}, - {-0.239420, 0.068235, 10.128663, 0}, - {-0.229843, 0.071826, 10.140635, 0}, - {-0.245406, 0.082600, 10.115496, 0}, - {-0.234632, 0.076614, 10.143028, 0}, - {-0.246603, 0.068235, 10.119086, 0}, - {-0.250194, 0.064643, 10.132255, 0}, - {-0.237026, 0.082600, 10.129861, 0}, - {-0.256179, 0.089783, 10.138240, 0}, - {-0.239420, 0.076614, 10.121481, 0}, - {-0.238223, 0.069432, 10.133451, 0}, - {-0.247800, 0.067038, 10.135846, 0}, - {-0.250194, 0.070629, 10.131058, 0}, - {-0.243011, 0.080206, 10.141831, 0}, - {-0.244208, 0.064643, 10.122678, 0}, - {-0.238223, 0.070629, 10.134649, 0}, - {-0.229843, 0.070629, 10.113101, 0}, - {-0.254982, 0.087388, 10.137043, 0}, - {-0.259771, 0.081403, 10.128663, 0}, - {-0.241814, 0.074220, 10.129861, 0}, - {-0.247800, 0.065841, 10.126269, 0}, - {-0.253785, 0.063446, 10.122678, 0}, - {-0.256179, 0.076614, 10.129861, 0}, - {-0.250194, 0.083797, 10.123875, 0}, - {-0.239420, 0.073023, 10.129861, 0}, - {-0.253785, 0.084994, 10.109509, 0}, - {-0.238223, 0.071826, 10.151408, 0}, - {-0.245406, 0.068235, 10.110707, 0}, - {-0.246603, 0.064643, 10.127466, 0}, - {-0.232237, 0.077812, 10.113101, 0}, - {-0.247800, 0.064643, 10.132255, 0}, - {-0.254982, 0.080206, 10.137043, 0}, - {-0.248997, 0.080206, 10.138240, 0}, - {-0.243011, 0.081403, 10.123875, 0}, - {-0.237026, 0.087388, 10.127466, 0}, - {-0.234632, 0.070629, 10.129861, 0}, - {-0.235829, 0.073023, 10.121481, 0}, - {-0.244208, 0.073023, 10.127466, 0}, - {-0.237026, 0.067038, 10.138240, 0}, - {-0.248997, 0.067038, 10.119086, 0}, - {-0.253785, 0.079009, 10.129861, 0}, - {-0.239420, 0.068235, 10.129861, 0}, - {-0.252588, 0.071826, 10.122678, 0}, - {-0.243011, 0.076614, 10.134649, 0}, - {-0.234632, 0.075417, 10.117889, 0}, - {-0.235829, 0.070629, 10.115496, 0}, - {-0.247800, 0.083797, 10.123875, 0}, - {-0.241814, 0.089783, 10.123875, 0}, - {-0.234632, 0.087388, 10.133451, 0}, - {-0.239420, 0.073023, 10.116693, 0}, - {-0.241814, 0.087388, 10.122678, 0}, - {-0.243011, 0.077812, 10.126269, 0}, - {-0.247800, 0.076614, 10.129861, 0}, - {-0.244208, 0.082600, 10.140635, 0}, - {-0.241814, 0.079009, 10.150211, 0}, - {-0.237026, 0.065841, 10.144226, 0}, - {-0.234632, 0.081403, 10.133451, 0}, - {-0.231040, 0.081403, 10.121481, 0}, - {-0.248997, 0.071826, 10.143028, 0}, - {-0.257377, 0.063446, 10.119086, 0}, - {-0.245406, 0.087388, 10.141831, 0}, - {-0.246603, 0.082600, 10.137043, 0}, - {-0.227449, 0.080206, 10.128663, 0}, - {-0.244208, 0.082600, 10.120284, 0}, - {-0.245406, 0.087388, 10.139438, 0}, - {-0.237026, 0.061052, 10.137043, 0}, - {-0.240617, 0.061052, 10.132255, 0}, - {-0.239420, 0.076614, 10.132255, 0}, - {-0.244208, 0.083797, 10.131058, 0}, - {-0.227449, 0.077812, 10.137043, 0}, - {-0.240617, 0.089783, 10.144226, 0}, - {-0.238223, 0.083797, 10.121481, 0}, - {-0.260968, 0.068235, 10.119086, 0}, - {-0.243011, 0.070629, 10.155000, 0}, - {-0.248997, 0.079009, 10.117889, 0}, - {-0.252588, 0.076614, 10.111904, 0}, - {-0.237026, 0.084994, 10.134649, 0}, - {-0.248997, 0.069432, 10.128663, 0}, - {-0.235829, 0.082600, 10.126269, 0}, - {-0.245406, 0.069432, 10.150211, 0}, - {-0.253785, 0.090980, 10.125072, 0}, - {-0.247800, 0.077812, 10.119086, 0}, - {-0.248997, 0.074220, 10.117889, 0}, - {-0.239420, 0.080206, 10.122678, 0}, - {-0.239420, 0.087388, 10.127466, 0}, - {-0.244208, 0.074220, 10.128663, 0}, - {-0.229843, 0.068235, 10.123875, 0}, - {-0.247800, 0.080206, 10.127466, 0}, - {-0.241814, 0.071826, 10.119086, 0}, - {-0.235829, 0.086191, 10.121481, 0}, - {-0.234632, 0.084994, 10.127466, 0}, - {-0.237026, 0.073023, 10.131058, 0}, - {-0.243011, 0.074220, 10.123875, 0}, - {-0.259771, 0.084994, 10.146620, 0}, - {-0.241814, 0.071826, 10.122678, 0}, - {-0.232237, 0.077812, 10.132255, 0}, - {-0.239420, 0.076614, 10.133451, 0}, - {-0.244208, 0.076614, 10.128663, 0}, - {-0.241814, 0.081403, 10.153803, 0}, - {-0.246603, 0.069432, 10.114298, 0}, - {-0.247800, 0.067038, 10.128663, 0}, - {-0.239420, 0.077812, 10.132255, 0}, - {-0.248997, 0.064643, 10.133451, 0}, - {-0.231040, 0.075417, 10.120284, 0}, - {-0.235829, 0.070629, 10.109509, 0}, - {-0.248997, 0.079009, 10.121481, 0}, - {-0.239420, 0.094571, 10.128663, 0}, - {-0.254982, 0.083797, 10.134649, 0}, - {-0.240617, 0.079009, 10.117889, 0}, - {-0.244208, 0.065841, 10.122678, 0}, - {-0.238223, 0.070629, 10.116693, 0}, - {-0.244208, 0.081403, 10.131058, 0}, - {-0.239420, 0.071826, 10.135846, 0}, - {-0.231040, 0.070629, 10.139438, 0}, - {-0.240617, 0.070629, 10.125072, 0}, - {-0.235829, 0.079009, 10.127466, 0}, - {-0.235829, 0.077812, 10.126269, 0}, - {-0.241814, 0.071826, 10.127466, 0}, - {-0.243011, 0.068235, 10.131058, 0}, - {-0.240617, 0.076614, 10.129861, 0}, - {-0.231040, 0.070629, 10.127466, 0}, - {-0.229843, 0.076614, 10.129861, 0}, - {-0.235829, 0.071826, 10.128663, 0}, - {-0.235829, 0.068235, 10.131058, 0}, - {-0.246603, 0.074220, 10.122678, 0}, - {-0.232237, 0.075417, 10.126269, 0}, - {-0.233435, 0.075417, 10.116693, 0}, - {-0.227449, 0.069432, 10.131058, 0}, - {-0.233435, 0.069432, 10.133451, 0}, - {-0.243011, 0.076614, 10.125072, 0}, - {-0.243011, 0.079009, 10.111904, 0}, - {-0.245406, 0.080206, 10.137043, 0}, - {-0.244208, 0.083797, 10.133451, 0}, - {-0.247800, 0.071826, 10.131058, 0}, - {-0.239420, 0.063446, 10.114298, 0}, - {-0.234632, 0.070629, 10.119086, 0}, - {-0.238223, 0.070629, 10.151408, 0}, - {-0.247800, 0.075417, 10.134649, 0}, - {-0.241814, 0.075417, 10.137043, 0}, - {-0.240617, 0.067038, 10.121481, 0}, - {-0.243011, 0.063446, 10.137043, 0}, - {-0.229843, 0.068235, 10.132255, 0}, - {-0.241814, 0.075417, 10.122678, 0}, - {-0.246603, 0.086191, 10.119086, 0}, - {-0.235829, 0.081403, 10.126269, 0}, - {-0.229843, 0.081403, 10.138240, 0}, - {-0.234632, 0.075417, 10.120284, 0}, - {-0.237026, 0.080206, 10.133451, 0}, - {-0.232237, 0.074220, 10.114298, 0}, - {-0.245406, 0.069432, 10.128663, 0}, - {-0.241814, 0.064643, 10.134649, 0}, - {-0.239420, 0.086191, 10.133451, 0}, - {-0.238223, 0.086191, 10.144226, 0}, - {-0.248997, 0.063446, 10.131058, 0}, - {-0.229843, 0.065841, 10.137043, 0}, - {-0.239420, 0.084994, 10.110707, 0}, - {-0.231040, 0.083797, 10.141831, 0}, - {-0.245406, 0.073023, 10.128663, 0}, - {-0.245406, 0.071826, 10.129861, 0}, - {-0.238223, 0.071826, 10.120284, 0}, - {-0.247800, 0.081403, 10.137043, 0}, - {-0.264559, 0.069432, 10.135846, 0}, - {-0.247800, 0.070629, 10.131058, 0}, - {-0.240617, 0.082600, 10.134649, 0}, - {-0.246603, 0.075417, 10.126269, 0}, - {-0.238223, 0.071826, 10.152605, 0}, - {-0.235829, 0.063446, 10.132255, 0}, - {-0.251391, 0.065841, 10.120284, 0}, - {-0.243011, 0.068235, 10.131058, 0}, - {-0.222661, 0.067038, 10.134649, 0}, - {-0.239420, 0.081403, 10.128663, 0}, - {-0.240617, 0.083797, 10.138240, 0}, - {-0.223858, 0.068235, 10.122678, 0}, - {-0.238223, 0.065841, 10.140635, 0}, - {-0.237026, 0.081403, 10.134649, 0}, - {-0.240617, 0.079009, 10.123875, 0}, - {-0.238223, 0.073023, 10.133451, 0}, - {-0.246603, 0.067038, 10.117889, 0}, - {-0.243011, 0.061052, 10.135846, 0}, - {-0.239420, 0.075417, 10.116693, 0}, - {-0.260968, 0.065841, 10.123875, 0}, - {-0.247800, 0.064643, 10.117889, 0}, - {-0.248997, 0.093374, 10.140635, 0}, - {-0.244208, 0.080206, 10.144226, 0}, - {-0.258574, 0.077812, 10.113101, 0}, - {-0.250194, 0.069432, 10.126269, 0}, - {-0.238223, 0.073023, 10.102327, 0}, - {-0.240617, 0.070629, 10.135846, 0}, - {-0.247800, 0.063446, 10.121481, 0}, - {-0.268150, 0.088585, 10.135846, 0}, - {-0.246603, 0.075417, 10.119086, 0}, - {-0.233435, 0.071826, 10.131058, 0}, - {-0.245406, 0.071826, 10.128663, 0}, - {-0.244208, 0.094571, 10.128663, 0}, - {-0.234632, 0.080206, 10.123875, 0}, - {-0.240617, 0.081403, 10.109509, 0}, - {-0.240617, 0.069432, 10.128663, 0}, - {-0.237026, 0.069432, 10.122678, 0}, - {-0.234632, 0.071826, 10.137043, 0}, - {-0.239420, 0.076614, 10.139438, 0}, - {-0.244208, 0.088585, 10.117889, 0}, - {-0.259771, 0.087388, 10.134649, 0}, - {-0.252588, 0.077812, 10.134649, 0}, - {-0.241814, 0.073023, 10.117889, 0}, - {-0.243011, 0.080206, 10.128663, 0}, - {-0.241814, 0.086191, 10.119086, 0}, - {-0.244208, 0.073023, 10.115496, 0}, - {-0.239420, 0.080206, 10.123875, 0}, - {-0.248997, 0.070629, 10.137043, 0}, - {-0.240617, 0.076614, 10.119086, 0}, - {-0.233435, 0.070629, 10.128663, 0}, - {-0.235829, 0.075417, 10.121481, 0}, - {-0.240617, 0.090980, 10.127466, 0}, - {-0.252588, 0.067038, 10.114298, 0}, - {-0.229843, 0.077812, 10.123875, 0}, - {-0.248997, 0.084994, 10.137043, 0}, - {-0.245406, 0.070629, 10.110707, 0}, - {-0.239420, 0.061052, 10.131058, 0}, - {-0.241814, 0.077812, 10.132255, 0}, - {-0.239420, 0.081403, 10.126269, 0}, - {-0.235829, 0.069432, 10.127466, 0}, - {-0.243011, 0.076614, 10.134649, 0}, - {-0.252588, 0.077812, 10.132255, 0}, - {-0.237026, 0.077812, 10.138240, 0}, - {-0.246603, 0.073023, 10.127466, 0}, - {-0.241814, 0.063446, 10.129861, 0}, - {-0.234632, 0.071826, 10.126269, 0}, - {-0.248997, 0.081403, 10.113101, 0}, - {-0.244208, 0.084994, 10.114298, 0}, - {-0.232237, 0.077812, 10.132255, 0}, - {-0.234632, 0.084994, 10.128663, 0}, - {-0.244208, 0.088585, 10.108313, 0}, - {-0.253785, 0.070629, 10.141831, 0}, - {-0.247800, 0.071826, 10.121481, 0}, - {-0.244208, 0.070629, 10.128663, 0}, - {-0.244208, 0.079009, 10.116693, 0}, - {-0.239420, 0.074220, 10.113101, 0}, - {-0.239420, 0.079009, 10.127466, 0}, - {-0.251391, 0.071826, 10.133451, 0}, - {-0.247800, 0.076614, 10.133451, 0}, - {-0.254982, 0.088585, 10.137043, 0}, - {-0.250194, 0.081403, 10.137043, 0}, - {-0.257377, 0.077812, 10.117889, 0}, - {-0.237026, 0.079009, 10.123875, 0}, - {-0.235829, 0.073023, 10.121481, 0}, - {-0.262165, 0.082600, 10.123875, 0}, - {-0.248997, 0.073023, 10.113101, 0}, - {-0.241814, 0.076614, 10.114298, 0}, - {-0.251391, 0.073023, 10.131058, 0}, - {-0.248997, 0.075417, 10.141831, 0}, - {-0.237026, 0.074220, 10.132255, 0}, - {-0.253785, 0.084994, 10.122678, 0}, - {-0.247800, 0.079009, 10.133451, 0}, - {-0.246603, 0.082600, 10.109509, 0}, - {-0.252588, 0.094571, 10.122678, 0}, - {-0.246603, 0.073023, 10.125072, 0}, - {-0.250194, 0.057461, 10.115496, 0}, - {-0.250194, 0.071826, 10.122678, 0}, - {-0.251391, 0.076614, 10.127466, 0}, - {-0.240617, 0.079009, 10.126269, 0}, - {-0.259771, 0.073023, 10.115496, 0}, - {-0.246603, 0.074220, 10.135846, 0}, - {-0.253785, 0.077812, 10.119086, 0}, - {-0.244208, 0.077812, 10.128663, 0}, - {-0.241814, 0.069432, 10.128663, 0}, - {-0.244208, 0.081403, 10.126269, 0}, - {-0.246603, 0.086191, 10.128663, 0}, - {-0.252588, 0.084994, 10.132255, 0}, - {-0.247800, 0.076614, 10.128663, 0}, - {-0.240617, 0.063446, 10.126269, 0}, - {-0.235829, 0.069432, 10.127466, 0}, - {-0.240617, 0.087388, 10.129861, 0}, - {-0.251391, 0.063446, 10.128663, 0}, - {-0.252588, 0.077812, 10.135846, 0}, - {-0.254982, 0.082600, 10.138240, 0}, - {-0.244208, 0.081403, 10.128663, 0}, - {-0.241814, 0.086191, 10.117889, 0}, - {-0.254982, 0.069432, 10.149014, 0}, - {-0.248997, 0.068235, 10.131058, 0}, - {-0.252588, 0.063446, 10.122678, 0}, - {-0.240617, 0.079009, 10.152605, 0}, - {-0.240617, 0.088585, 10.107116, 0}, - {-0.248997, 0.076614, 10.138240, 0}, - {-0.251391, 0.075417, 10.119086, 0}, - {-0.225055, 0.079009, 10.138240, 0}, - {-0.239420, 0.077812, 10.150211, 0}, - {-0.250194, 0.055067, 10.137043, 0}, - {-0.257377, 0.082600, 10.125072, 0}, - {-0.243011, 0.075417, 10.119086, 0}, - {-0.244208, 0.064643, 10.119086, 0}, - {-0.246603, 0.080206, 10.117889, 0}, - {-0.232237, 0.079009, 10.158591, 0}, - {-0.247800, 0.071826, 10.120284, 0}, - {-0.245406, 0.075417, 10.137043, 0}, - {-0.240617, 0.069432, 10.117889, 0}, - {-0.246603, 0.080206, 10.134649, 0}, - {-0.248997, 0.087388, 10.109509, 0}, - {-0.252588, 0.081403, 10.132255, 0}, - {-0.250194, 0.069432, 10.123875, 0}, - {-0.257377, 0.073023, 10.131058, 0}, - {-0.241814, 0.068235, 10.109509, 0}, - {-0.243011, 0.080206, 10.108313, 0}, - {-0.238223, 0.074220, 10.139438, 0}, - {-0.245406, 0.075417, 10.122678, 0}, - {-0.250194, 0.069432, 10.137043, 0}, - {-0.245406, 0.069432, 10.116693, 0}, - {-0.235829, 0.070629, 10.158591, 0}, - {-0.247800, 0.082600, 10.117889, 0}, - {-0.247800, 0.077812, 10.137043, 0}, - {-0.243011, 0.080206, 10.134649, 0}, - {-0.263362, 0.081403, 10.110707, 0}, - {-0.247800, 0.079009, 10.127466, 0}, - {-0.248997, 0.071826, 10.131058, 0}, - {-0.248997, 0.075417, 10.144226, 0}, - {-0.239420, 0.077812, 10.117889, 0}, - {-0.248997, 0.071826, 10.139438, 0}, - {-0.254982, 0.083797, 10.120284, 0}, - {-0.238223, 0.075417, 10.131058, 0}, - {-0.235829, 0.084994, 10.105919, 0}, - {-0.245406, 0.080206, 10.133451, 0}, - {-0.247800, 0.075417, 10.131058, 0}, - {-0.235829, 0.079009, 10.120284, 0}, - {-0.247800, 0.070629, 10.133451, 0}, - {-0.253785, 0.064643, 10.110707, 0}, - {-0.240617, 0.071826, 10.120284, 0}, - {-0.248997, 0.079009, 10.101130, 0}, - {-0.243011, 0.079009, 10.141831, 0}, - {-0.244208, 0.077812, 10.134649, 0}, - {-0.245406, 0.081403, 10.140635, 0}, - {-0.253785, 0.070629, 10.110707, 0}, - {-0.254982, 0.058658, 10.129861, 0}, - {-0.239420, 0.083797, 10.137043, 0}, - {-0.232237, 0.081403, 10.125072, 0}, - {-0.243011, 0.068235, 10.139438, 0}, - {-0.243011, 0.063446, 10.123875, 0}, - {-0.232237, 0.074220, 10.140635, 0}, - {-0.241814, 0.077812, 10.116693, 0}, - {-0.247800, 0.074220, 10.139438, 0}, - {-0.245406, 0.077812, 10.127466, 0}, - {-0.233435, 0.073023, 10.132255, 0}, - {-0.243011, 0.074220, 10.121481, 0}, - {-0.246603, 0.059855, 10.125072, 0}, - {-0.246603, 0.070629, 10.120284, 0}, - {-0.241814, 0.087388, 10.133451, 0}, - {-0.245406, 0.061052, 10.128663, 0}, - {-0.248997, 0.079009, 10.111904, 0}, - {-0.237026, 0.077812, 10.135846, 0}, - {-0.240617, 0.083797, 10.108313, 0}, - {-0.237026, 0.075417, 10.141831, 0}, - {-0.243011, 0.061052, 10.132255, 0}, - {-0.234632, 0.073023, 10.133451, 0}, - {-0.251391, 0.073023, 10.137043, 0}, - {-0.237026, 0.083797, 10.135846, 0}, - {-0.231040, 0.077812, 10.117889, 0}, - {-0.237026, 0.061052, 10.140635, 0}, - {-0.243011, 0.071826, 10.127466, 0}, - {-0.235829, 0.081403, 10.131058, 0}, - {-0.241814, 0.076614, 10.123875, 0}, - {-0.258574, 0.081403, 10.127466, 0}, - {-0.241814, 0.063446, 10.127466, 0}, - {-0.254982, 0.071826, 10.139438, 0}, - {-0.244208, 0.077812, 10.117889, 0}, - {-0.240617, 0.077812, 10.134649, 0}, - {-0.258574, 0.075417, 10.128663, 0}, - {-0.245406, 0.069432, 10.131058, 0}, - {-0.245406, 0.074220, 10.126269, 0}, - {-0.248997, 0.075417, 10.137043, 0}, - {-0.248997, 0.082600, 10.137043, 0}, - {-0.245406, 0.084994, 10.115496, 0}, - {-0.244208, 0.073023, 10.126269, 0}, - {-0.234632, 0.067038, 10.126269, 0}, - {-0.238223, 0.064643, 10.127466, 0}, - {-0.263362, 0.065841, 10.123875, 0}, - {-0.257377, 0.081403, 10.126269, 0}, - {-0.237026, 0.082600, 10.105919, 0}, - {-0.253785, 0.083797, 10.119086, 0}, - {-0.234632, 0.073023, 10.125072, 0}, - {-0.243011, 0.062249, 10.122678, 0}, - {-0.251391, 0.076614, 10.119086, 0}, - {-0.258574, 0.071826, 10.139438, 0}, - {-0.250194, 0.071826, 10.140635, 0}, - {-0.251391, 0.086191, 10.140635, 0}, - {-0.248997, 0.077812, 10.121481, 0}, - {-0.244208, 0.083797, 10.126269, 0}, - {-0.241814, 0.083797, 10.133451, 0}, - {-0.246603, 0.070629, 10.119086, 0}, - {-0.241814, 0.067038, 10.146620, 0}, - {-0.247800, 0.079009, 10.109509, 0}, - {-0.256179, 0.069432, 10.146620, 0}, - {-0.247800, 0.073023, 10.126269, 0}, - {-0.245406, 0.070629, 10.113101, 0}, - {-0.234632, 0.084994, 10.126269, 0}, - {-0.228646, 0.068235, 10.129861, 0}, - {-0.246603, 0.062249, 10.143028, 0}, - {-0.245406, 0.084994, 10.122678, 0}, - {-0.244208, 0.067038, 10.143028, 0}, - {-0.241814, 0.080206, 10.138240, 0}, - {-0.243011, 0.083797, 10.135846, 0}, - {-0.238223, 0.069432, 10.139438, 0}, - {-0.235829, 0.081403, 10.121481, 0}, - {-0.241814, 0.081403, 10.119086, 0}, - {-0.241814, 0.068235, 10.146620, 0}, - {-0.246603, 0.093374, 10.107116, 0}, - {-0.247800, 0.088585, 10.135846, 0}, - {-0.258574, 0.069432, 10.101130, 0}, - {-0.252588, 0.074220, 10.135846, 0}, - {-0.240617, 0.058658, 10.127466, 0}, - {-0.263362, 0.073023, 10.138240, 0}, - {-0.244208, 0.081403, 10.135846, 0}, - {-0.248997, 0.086191, 10.127466, 0}, - {-0.251391, 0.074220, 10.133451, 0}, - {-0.241814, 0.068235, 10.129861, 0}, - {-0.247800, 0.075417, 10.144226, 0}, - {-0.248997, 0.086191, 10.113101, 0}, - {-0.239420, 0.080206, 10.153803, 0}, - {-0.239420, 0.059855, 10.117889, 0}, - {-0.244208, 0.073023, 10.139438, 0}, - {-0.245406, 0.082600, 10.120284, 0}, - {-0.238223, 0.086191, 10.133451, 0}, - {-0.246603, 0.079009, 10.123875, 0}, - {-0.247800, 0.074220, 10.131058, 0}, - {-0.252588, 0.084994, 10.120284, 0}, - {-0.245406, 0.075417, 10.125072, 0}, - {-0.240617, 0.069432, 10.135846, 0}, - {-0.245406, 0.076614, 10.121481, 0}, - {-0.231040, 0.068235, 10.132255, 0}, - {-0.233435, 0.076614, 10.134649, 0}, - {-0.239420, 0.082600, 10.127466, 0}, - {-0.253785, 0.076614, 10.104721, 0}, - {-0.247800, 0.089783, 10.133451, 0}, - {-0.238223, 0.076614, 10.134649, 0}, - {-0.240617, 0.073023, 10.105919, 0}, - {-0.243011, 0.067038, 10.146620, 0}, - {-0.246603, 0.067038, 10.135846, 0}, - {-0.250194, 0.080206, 10.146620, 0}, - {-0.252588, 0.062249, 10.125072, 0}, - {-0.234632, 0.074220, 10.127466, 0}, - {-0.239420, 0.069432, 10.149014, 0}, - {-0.243011, 0.069432, 10.126269, 0}, - {-0.240617, 0.071826, 10.109509, 0}, - {-0.258574, 0.067038, 10.121481, 0}, - {-0.258574, 0.079009, 10.137043, 0}, - {-0.248997, 0.083797, 10.114298, 0}, - {-0.228646, 0.077812, 10.123875, 0}, - {-0.248997, 0.061052, 10.128663, 0}, - {-0.253785, 0.080206, 10.140635, 0}, - {-0.250194, 0.077812, 10.119086, 0}, - {-0.250194, 0.080206, 10.134649, 0}, - {-0.254982, 0.079009, 10.104721, 0}, - {-0.251391, 0.076614, 10.125072, 0}, - {-0.244208, 0.069432, 10.109509, 0}, - {-0.251391, 0.075417, 10.131058, 0}, - {-0.246603, 0.074220, 10.135846, 0}, - {-0.247800, 0.077812, 10.133451, 0}, - {-0.243011, 0.095768, 10.119086, 0}, - {-0.252588, 0.079009, 10.103524, 0}, - {-0.248997, 0.080206, 10.119086, 0}, - {-0.250194, 0.087388, 10.122678, 0}, - {-0.244208, 0.071826, 10.143028, 0}, - {-0.228646, 0.079009, 10.104721, 0}, - {-0.235829, 0.087388, 10.125072, 0}, - {-0.241814, 0.070629, 10.105919, 0}, - {-0.251391, 0.081403, 10.140635, 0}, - {-0.235829, 0.074220, 10.117889, 0}, - {-0.244208, 0.076614, 10.134649, 0}, - {-0.248997, 0.074220, 10.108313, 0}, - {-0.240617, 0.089783, 10.123875, 0}, - {-0.254982, 0.074220, 10.146620, 0}, - {-0.252588, 0.079009, 10.120284, 0}, - {-0.246603, 0.087388, 10.133451, 0}, - {-0.246603, 0.074220, 10.116693, 0}, - {-0.235829, 0.074220, 10.138240, 0}, - {-0.239420, 0.076614, 10.111904, 0}, - {-0.253785, 0.065841, 10.132255, 0}, - {-0.246603, 0.074220, 10.117889, 0}, - {-0.251391, 0.084994, 10.121481, 0}, - {-0.260968, 0.087388, 10.131058, 0}, - {-0.246603, 0.084994, 10.123875, 0}, - {-0.247800, 0.087388, 10.119086, 0}, - {-0.238223, 0.070629, 10.125072, 0}, - {-0.248997, 0.075417, 10.137043, 0}, - {-0.240617, 0.081403, 10.126269, 0}, - {-0.225055, 0.075417, 10.117889, 0}, - {-0.245406, 0.061052, 10.099933, 0}, - {-0.229843, 0.071826, 10.133451, 0}, - {-0.239420, 0.088585, 10.158591, 0}, - {-0.251391, 0.079009, 10.111904, 0}, - {-0.234632, 0.070629, 10.151408, 0}, - {-0.232237, 0.068235, 10.127466, 0}, - {-0.238223, 0.083797, 10.125072, 0}, - {-0.240617, 0.083797, 10.104721, 0}, - {-0.234632, 0.084994, 10.127466, 0}, - {-0.243011, 0.068235, 10.098736, 0}, - {-0.251391, 0.075417, 10.146620, 0}, - {-0.257377, 0.082600, 10.117889, 0}, - {-0.234632, 0.076614, 10.119086, 0}, - {-0.244208, 0.080206, 10.132255, 0}, - {-0.232237, 0.080206, 10.139438, 0}, - {-0.235829, 0.083797, 10.134649, 0}, - {-0.240617, 0.083797, 10.107116, 0}, - {-0.239420, 0.087388, 10.134649, 0}, - {-0.248997, 0.074220, 10.125072, 0}, - {-0.247800, 0.064643, 10.150211, 0}, - {-0.243011, 0.076614, 10.111904, 0}, - {-0.247800, 0.069432, 10.139438, 0}, - {-0.240617, 0.076614, 10.132255, 0}, - {-0.240617, 0.076614, 10.129861, 0}, - {-0.235829, 0.065841, 10.105919, 0}, - {-0.252588, 0.080206, 10.113101, 0}, - {-0.251391, 0.077812, 10.149014, 0}, - {-0.241814, 0.082600, 10.056837, 0}, - {-0.243011, 0.084994, 10.199292, 0}, - {-0.253785, 0.077812, 10.098736, 0}, - {-0.229843, 0.063446, 10.103524, 0}, - {-0.250194, 0.069432, 10.183730, 0}, - {-0.240617, 0.086191, 10.067612, 0}, - {-0.246603, 0.070629, 10.201687, 0}, - {-0.263362, 0.067038, 10.071202, 0}, - {-0.245406, 0.059855, 10.166970, 0}, - {-0.239420, 0.065841, 10.092751, 0}, - {-0.238223, 0.068235, 10.139438, 0}, - {-0.243011, 0.074220, 10.116693, 0}, - {-0.240617, 0.081403, 10.122678, 0}, - {-0.251391, 0.067038, 10.119086, 0}, - {-0.240617, 0.075417, 10.113101, 0}, - {-0.250194, 0.059855, 10.137043, 0}, - {-0.244208, 0.062249, 10.129861, 0}, - {-0.229843, 0.083797, 10.117889, 0}, - {-0.246603, 0.076614, 10.123875, 0}, - {-0.234632, 0.087388, 10.140635, 0}, - {-0.254982, 0.079009, 10.119086, 0}, - {-0.237026, 0.074220, 10.157393, 0}, - {-0.247800, 0.088585, 10.115496, 0}, - {-0.251391, 0.087388, 10.144226, 0}, - {-0.238223, 0.071826, 10.116693, 0}, - {-0.233435, 0.069432, 10.137043, 0}, - {-0.231040, 0.081403, 10.119086, 0}, - {-0.244208, 0.079009, 10.116693, 0}, - {-0.245406, 0.073023, 10.147817, 0}, - {-0.250194, 0.071826, 10.113101, 0}, - {-0.238223, 0.077812, 10.135846, 0}, - {-0.240617, 0.077812, 10.105919, 0}, - {-0.239420, 0.076614, 10.145423, 0}, - {-0.232237, 0.070629, 10.102327, 0}, - {-0.241814, 0.080206, 10.119086, 0}, - {-0.237026, 0.068235, 10.111904, 0}, - {-0.260968, 0.082600, 10.137043, 0}, - {-0.240617, 0.089783, 10.139438, 0}, - {-0.238223, 0.077812, 10.128663, 0}, - {-0.240617, 0.075417, 10.138240, 0}, - {-0.247800, 0.075417, 10.129861, 0}, - {-0.251391, 0.075417, 10.143028, 0}, - {-0.254982, 0.076614, 10.128663, 0}, - {-0.251391, 0.070629, 10.157393, 0}, - {-0.253785, 0.086191, 10.134649, 0}, - {-0.248997, 0.079009, 10.126269, 0}, - {-0.244208, 0.087388, 10.117889, 0}, - {-0.254982, 0.080206, 10.125072, 0}, - {-0.244208, 0.071826, 10.122678, 0}, - {-0.248997, 0.087388, 10.111904, 0}, - {-0.246603, 0.075417, 10.133451, 0}, - {-0.252588, 0.071826, 10.099933, 0}, - {-0.245406, 0.082600, 10.132255, 0}, - {-0.246603, 0.086191, 10.129861, 0}, - {-0.227449, 0.067038, 10.151408, 0}, - {-0.235829, 0.079009, 10.109509, 0}, - {-0.239420, 0.080206, 10.137043, 0}, - {-0.241814, 0.084994, 10.121481, 0}, - {-0.251391, 0.081403, 10.116693, 0}, - {-0.260968, 0.073023, 10.141831, 0}, - {-0.245406, 0.073023, 10.122678, 0}, - {-0.252588, 0.083797, 10.139438, 0}, - {-0.243011, 0.080206, 10.122678, 0}, - {-0.239420, 0.077812, 10.138240, 0}, - {-0.241814, 0.068235, 10.113101, 0}, - {-0.244208, 0.074220, 10.133451, 0}, - {-0.257377, 0.079009, 10.128663, 0}, - {-0.253785, 0.074220, 10.125072, 0}, - {-0.238223, 0.062249, 10.132255, 0}, - {-0.243011, 0.068235, 10.119086, 0}, - {-0.240617, 0.074220, 10.132255, 0}, - {-0.272939, 0.076614, 10.116693, 0}, - {-0.234632, 0.075417, 10.138240, 0}, - {-0.241814, 0.073023, 10.085567, 0}, - {-0.246603, 0.075417, 10.163380, 0}, - {-0.248997, 0.058658, 10.093947, 0}, - {-0.243011, 0.070629, 10.146620, 0}, - {-0.238223, 0.074220, 10.110707, 0}, - {-0.252588, 0.065841, 10.141831, 0}, - {-0.229843, 0.074220, 10.137043, 0}, - {-0.248997, 0.076614, 10.099933, 0}, - {-0.229843, 0.081403, 10.157393, 0}, - {-0.243011, 0.082600, 10.074794, 0}, - {-0.250194, 0.071826, 10.164577, 0}, - {-0.263362, 0.076614, 10.103524, 0}, - {-0.260968, 0.094571, 10.138240, 0}, - {-0.240617, 0.077812, 10.116693, 0}, - {-0.239420, 0.081403, 10.109509, 0}, - {-0.253785, 0.086191, 10.135846, 0}, - {-0.247800, 0.076614, 10.093947, 0}, - {-0.256179, 0.068235, 10.158591, 0}, - {-0.253785, 0.079009, 10.090356, 0}, - {-0.239420, 0.076614, 10.151408, 0}, - {-0.244208, 0.082600, 10.115496, 0}, - {-0.244208, 0.081403, 10.134649, 0}, - {-0.254982, 0.088585, 10.122678, 0}, - {-0.252588, 0.069432, 10.120284, 0}, - {-0.247800, 0.077812, 10.137043, 0}, - {-0.250194, 0.076614, 10.117889, 0}, - {-0.238223, 0.077812, 10.121481, 0}, - {-0.245406, 0.065841, 10.186124, 0}, - {-0.233435, 0.065841, 10.046063, 0}, - {-0.237026, 0.094571, 10.243585, 0}, - {-0.231040, 0.093374, 10.014939, 0}, - {-0.243011, 0.084994, 10.223234, 0}, - {-0.256179, 0.064643, 9.987406, 0}, - {-0.250194, 0.098162, 10.247176, 0}, - {-0.229843, 0.073023, 9.891638, 0}, - {-0.268150, 0.062249, 10.406390, 0}, - {-0.247800, 0.073023, 9.883258, 0}, - {-0.237026, 0.076614, 10.360901, 0}, - {-0.247800, 0.081403, 9.975434, 0}, - {-0.225055, 0.080206, 10.178942, 0}, - {-0.263362, 0.071826, 10.163380, 0}, - {-0.237026, 0.076614, 10.062823, 0}, - {-0.265756, 0.075417, 10.214854, 0}, - {-0.234632, 0.083797, 10.053246, 0}, - {-0.254982, 0.071826, 10.210066, 0}, - {-0.241814, 0.076614, 10.001771, 0}, - {-0.221464, 0.117316, 10.239994, 0}, - {-0.269348, 0.076614, 10.064020, 0}, - {-0.220266, 0.092177, 10.166970, 0}, - {-0.252588, 0.075417, 10.111904, 0}, - {-0.232237, 0.068235, 10.122678, 0}, - {-0.259771, 0.075417, 10.110707, 0}, - {-0.246603, 0.095768, 10.137043, 0}, - {-0.235829, 0.076614, 10.138240, 0}, - {-0.256179, 0.071826, 10.102327, 0}, - {-0.229843, 0.089783, 10.175350, 0}, - {-0.260968, 0.082600, 10.089159, 0}, - {-0.225055, 0.086191, 10.169365, 0}, - {-0.262165, 0.087388, 10.103524, 0}, - {-0.234632, 0.077812, 10.149014, 0}, - {-0.241814, 0.070629, 10.079582, 0}, - {-0.256179, 0.077812, 10.163380, 0}, - {-0.226252, 0.068235, 10.096342, 0}, - {-0.253785, 0.080206, 10.117889, 0}, - {-0.244208, 0.077812, 10.163380, 0}, - {-0.269348, 0.076614, 10.097539, 0}, - {-0.238223, 0.069432, 10.169365, 0}, - {-0.254982, 0.068235, 10.096342, 0}, - {-0.231040, 0.061052, 10.159788, 0}, - {-0.248997, 0.075417, 10.079582, 0}, - {-0.258574, 0.071826, 10.162182, 0}, - {-0.232237, 0.079009, 10.102327, 0}, - {-0.256179, 0.100556, 10.138240, 0}, - {-0.232237, 0.084994, 10.116693, 0}, - {-0.235829, 0.080206, 10.110707, 0}, - {-0.225055, 0.065841, 10.129861, 0}, - {-0.217872, 0.082600, 10.090356, 0}, - {-0.244208, 0.081403, 10.157393, 0}, + { -6.536166, 0.264559, 7.560884, 0 }, + { -6.253651, 0.108936, 8.167813, 0 }, + { -5.890929, -0.029928, 8.061272, 0 }, + { -5.833468, -0.045490, 8.250414, 0 }, + { -5.932828, 0.038307, 8.573630, 0 }, + { -5.995077, 0.104148, 8.634683, 0 }, + { -6.080071, 0.181959, 8.317451, 0 }, + { -6.069297, 0.177171, 8.151054, 0 }, + { -5.978318, 0.113724, 8.407233, 0 }, + { -5.895718, 0.033519, 8.592784, 0 }, + { -5.828680, -0.022745, 8.299495, 0 }, + { -5.768825, -0.070629, 7.958321, 0 }, + { -5.770022, -0.089783, 8.028950, 0 }, + { -5.832272, -0.074220, 8.360547, 0 }, + { -5.880156, -0.067038, 8.488636, 0 }, + { -5.987895, -0.017957, 8.342590, 0 }, + { -6.148306, 0.014365, 8.317451, 0 }, + { -6.337448, 0.102951, 8.492228, 0 }, + { -6.411668, 0.148440, 8.571237, 0 }, + { -6.341039, 0.099359, 8.250414, 0 }, + { -6.232103, 0.067038, 7.899663, 0 }, + { -6.172248, 0.100556, 8.152251, 0 }, + { -6.095634, 0.111330, 8.632288, 0 }, + { -6.033384, 0.126893, 8.614332, 0 }, + { -5.936419, 0.131681, 8.136689, 0 }, + { -5.931631, 0.205901, 7.739252, 0 }, + { -5.986697, 0.271742, 7.870933, 0 }, + { -6.040567, 0.250194, 8.099579, 0 }, + { -6.077677, 0.244208, 8.191755, 0 }, + { -6.071692, 0.277727, 8.146266, 0 }, + { -5.953178, 0.292092, 8.025358, 0 }, + { -5.847834, 0.330400, 7.942759, 0 }, + { -5.776008, 0.392649, 8.036133, 0 }, + { -5.680240, 0.417788, 7.892480, 0 }, + { -5.617990, 0.458489, 7.609965, 0 }, + { -5.550953, 0.496797, 7.418429, 0 }, + { -5.301956, 0.369904, 8.050498, 0 }, + { -5.276817, 0.290895, 9.167392, 0 }, + { -5.890929, 0.215478, 9.044091, 0 }, + { -6.495465, 0.108936, 9.111129, 0 }, + { -6.545743, -0.049081, 9.390053, 0 }, + { -5.966347, -0.161609, 9.362519, 0 }, + { -5.325898, -0.117316, 8.969871, 0 }, + { -5.263649, 0.105345, 8.404840, 0 }, + { -5.620385, 0.336385, 8.085214, 0 }, + { -5.886141, 0.472855, 8.037330, 0 }, + { -5.704182, 0.427365, 8.032541, 0 }, + { -5.359417, 0.301669, 7.813472, 0 }, + { -5.331883, 0.329203, 7.632710, 0 }, + { -5.483915, 0.433350, 7.621936, 0 }, + { -5.862199, 0.703895, 8.079228, 0 }, + { -5.808330, 0.616507, 9.142253, 0 }, + { -5.513843, 0.481234, 9.751576, 0 }, + { -5.365402, 0.470460, 9.706087, 0 }, + { -5.378571, 0.440533, 9.333789, 0 }, + { -5.637144, 0.565031, 8.905227, 0 }, + { -5.776008, 0.560243, 8.019373, 0 }, + { -5.779599, 0.676362, 7.132322, 0 }, + { -5.549756, 0.760159, 7.116760, 0 }, + { -5.303153, 0.730231, 7.817063, 0 }, + { -5.206188, 0.831985, 8.506593, 0 }, + { -5.151122, 0.725443, 8.941140, 0 }, + { -5.292379, 0.556652, 9.176969, 0 }, + { -5.622779, 0.563834, 9.362519, 0 }, + { -5.481521, 0.433350, 9.410403, 0 }, + { -5.045777, -0.074220, 9.109931, 0 }, + { -5.035003, -0.328005, 8.900438, 0 }, + { -5.307941, -0.389058, 9.000996, 0 }, + { -5.561727, -0.269348, 9.169786, 0 }, + { -5.603625, 0.213084, 9.216474, 0 }, + { -5.357023, 0.697909, 9.339774, 0 }, + { -5.081690, 0.764947, 9.429557, 0 }, + { -5.063733, 0.520739, 9.349351, 0 }, + { -5.212173, 0.463278, 9.210487, 0 }, + { -5.079296, 0.622492, 9.057259, 0 }, + { -4.827904, 0.758961, 8.755589, 0 }, + { -4.689041, 0.723048, 8.749604, 0 }, + { -4.681858, 0.731428, 9.129085, 0 }, + { -4.598061, 0.723048, 9.536098, 0 }, + { -4.378992, 0.730231, 9.668977, 0 }, + { -4.214989, 0.672770, 9.102749, 0 }, + { -4.241325, 0.641646, 8.643063, 0 }, + { -4.289209, 0.708683, 8.941140, 0 }, + { -4.304772, 0.984016, 9.394841, 0 }, + { -4.106053, 0.980425, 9.239218, 0 }, + { -3.926488, 0.615309, 8.754393, 0 }, + { -4.012679, 0.414197, 8.646653, 0 }, + { -4.191047, 0.730231, 9.080004, 0 }, + { -4.211398, 1.057039, 9.763548, 0 }, + { -4.055775, 0.944512, 9.933537, 0 }, + { -3.976766, 0.493205, 9.303862, 0 }, + { -4.319137, 0.397437, 8.835795, 0 }, + { -4.368218, 0.577002, 9.014163, 0 }, + { -4.213792, 0.700303, 9.281116, 0 }, + { -4.164711, 0.563834, 9.527719, 0 }, + { -4.132390, 0.458489, 9.472652, 0 }, + { -4.106053, 0.392649, 9.238021, 0 }, + { -4.090491, 0.524330, 9.093172, 0 }, + { -4.052184, 0.738611, 9.153027, 0 }, + { -4.015073, 0.524330, 9.047682, 0 }, + { -4.149149, 0.454898, 8.930367, 0 }, + { -4.250902, 0.724246, 9.131479, 0 }, + { -4.231749, 0.701501, 9.166195, 0 }, + { -4.356247, 0.757764, 9.208094, 0 }, + { -4.443635, 0.785298, 9.235627, 0 }, + { -4.355050, 0.804451, 9.149436, 0 }, + { -4.307166, 0.567425, 9.187743, 0 }, + { -4.550177, 0.476446, 9.249992, 0 }, + { -4.790794, 0.457292, 9.175772, 0 }, + { -4.935644, 0.417788, 9.200911, 0 }, + { -4.940432, 0.588973, 9.419980, 0 }, + { -4.709392, 0.357933, 9.624684, 0 }, + { -4.763261, 0.093374, 9.773125, 0 }, + { -5.021835, 0.171185, 9.756365, 0 }, + { -5.087675, 0.294487, 9.680948, 0 }, + { -4.916490, 0.357933, 9.610319, 0 }, + { -4.729742, 0.360327, 9.296679, 0 }, + { -4.635171, 0.266953, 8.780728, 0 }, + { -4.843467, 0.410605, 8.383291, 0 }, + { -4.898533, 0.500388, 8.177390, 0 }, + { -4.692632, 0.489614, 8.313860, 0 }, + { -4.566936, 0.451307, 8.595179, 0 }, + { -4.624397, 0.457292, 8.774743, 0 }, + { -4.781218, 0.441730, 8.777138, 0 }, + { -4.916490, 0.410605, 8.816642, 0 }, + { -5.014652, 0.482431, 8.795094, 0 }, + { -4.830298, 0.306458, 8.991419, 0 }, + { -5.154713, 0.448913, 8.974659, 0 }, + { -5.114011, 0.424971, 8.789108, 0 }, + { -4.894942, 0.238223, 8.692143, 0 }, + { -4.979936, 0.184353, 8.980644, 0 }, + { -5.267240, 0.381875, 9.326607, 0 }, + { -5.289985, 0.413000, 9.498989, 0 }, + { -5.128376, 0.320823, 9.273934, 0 }, + { -4.978739, 0.312443, 8.930367, 0 }, + { -5.054156, 0.391452, 8.816642, 0 }, + { -5.224144, 0.409408, 8.898045, 0 }, + { -5.287591, 0.392649, 8.862131, 0 }, + { -5.182246, 0.426168, 8.808262, 0 }, + { -5.039791, 0.471657, 8.797488, 0 }, + { -4.969162, 0.490811, 8.793897, 0 }, + { -5.032609, 0.511162, 8.804670, 0 }, + { -5.021835, 0.465672, 8.822627, 0 }, + { -4.967965, 0.496797, 8.820233, 0 }, + { -4.969162, 0.571017, 8.796291, 0 }, + { -4.904519, 0.560243, 8.785517, 0 }, + { -4.750093, 0.547075, 8.775940, 0 }, + { -4.687844, 0.500388, 8.554477, 0 }, + { -4.741713, 0.487220, 8.224077, 0 }, + { -4.880577, 0.569820, 8.147463, 0 }, + { -4.959586, 0.610521, 8.506593, 0 }, + { -4.977542, 0.555454, 8.856146, 0 }, + { -4.910504, 0.424971, 8.870511, 0 }, + { -4.947615, 0.316034, 8.845372, 0 }, + { -5.177458, 0.336385, 9.156618, 0 }, + { -5.345052, 0.371101, 9.455894, 0 }, + { -5.370191, 0.402226, 9.381673, 0 }, + { -5.357023, 0.372298, 9.232036, 0 }, + { -5.309139, 0.289698, 9.148238, 0 }, + { -5.236115, 0.247800, 9.085989, 0 }, + { -5.159501, 0.211887, 9.010572, 0 }, + { -5.081690, 0.173579, 8.878891, 0 }, + { -5.049368, 0.208295, 8.710100, 0 }, + { -5.026623, 0.229843, 8.664610, 0 }, + { -5.032609, 0.237026, 8.772349, 0 }, + { -4.967965, 0.233435, 8.868117, 0 }, + { -4.844664, 0.164003, 8.799882, 0 }, + { -4.906913, 0.155623, 8.500607, 0 }, + { -5.141545, 0.264559, 8.359349, 0 }, + { -5.264846, 0.310049, 8.640668, 0 }, + { -5.348643, 0.306458, 8.961491, 0 }, + { -5.366600, 0.301669, 8.968674, 0 }, + { -5.404907, 0.298078, 8.802277, 0 }, + { -5.386950, 0.259771, 8.801080, 0 }, + { -5.335475, 0.208295, 8.759181, 0 }, + { -5.300759, 0.174777, 8.723268, 0 }, + { -5.237313, 0.147243, 8.762773, 0 }, + { -5.303153, 0.185551, 8.772349, 0 }, + { -5.394133, 0.204704, 8.888468, 0 }, + { -5.383359, 0.167594, 8.965082, 0 }, + { -5.257663, 0.110133, 8.893256, 0 }, + { -5.116405, 0.039504, 8.738831, 0 }, + { -5.194217, 0.044293, 8.644259, 0 }, + { -5.336672, 0.111330, 8.772349, 0 }, + { -5.389344, 0.132878, 8.972264, 0 }, + { -5.400118, 0.136469, 8.959097, 0 }, + { -5.455185, 0.185551, 8.850161, 0 }, + { -5.519828, 0.210690, 8.804670, 0 }, + { -5.555741, 0.210690, 8.898045, 0 }, + { -5.507857, 0.222661, 8.835795, 0 }, + { -5.402513, 0.205901, 8.598769, 0 }, + { -5.368994, 0.257377, 8.353364, 0 }, + { -5.437228, 0.366313, 8.394066, 0 }, + { -5.401315, 0.345962, 8.656230, 0 }, + { -5.341460, 0.350750, 8.723268, 0 }, + { -5.272028, 0.362721, 8.585602, 0 }, + { -5.282803, 0.387860, 8.337802, 0 }, + { -5.285197, 0.420182, 8.268370, 0 }, + { -5.250481, 0.415394, 8.337802, 0 }, + { -5.185837, 0.379481, 8.416810, 0 }, + { -5.161895, 0.356736, 8.468286, 0 }, + { -5.203794, 0.344765, 8.577222, 0 }, + { -5.272028, 0.306458, 8.719677, 0 }, + { -5.315124, 0.271742, 8.868117, 0 }, + { -5.337869, 0.296881, 8.939943, 0 }, + { -5.376176, 0.299275, 8.894453, 0 }, + { -5.442017, 0.318429, 8.793897, 0 }, + { -5.452791, 0.331597, 8.714889, 0 }, + { -5.412089, 0.289698, 8.700523, 0 }, + { -5.406104, 0.251391, 8.773546, 0 }, + { -5.368994, 0.252588, 8.866920, 0 }, + { -5.323504, 0.240617, 8.942337, 0 }, + { -5.333081, 0.231040, 9.015361, 0 }, + { -5.377373, 0.231040, 8.980644, 0 }, + { -5.450397, 0.292092, 8.865723, 0 }, + { -5.483915, 0.336385, 8.750801, 0 }, + { -5.474339, 0.355539, 8.653836, 0 }, + { -5.404907, 0.342371, 8.593981, 0 }, + { -5.243298, 0.234632, 8.598769, 0 }, + { -5.164289, 0.198719, 8.635880, 0 }, + { -5.214568, 0.248997, 8.646653, 0 }, + { -5.316321, 0.288501, 8.589192, 0 }, + { -5.452791, 0.343568, 8.579616, 0 }, + { -5.509054, 0.366313, 8.670595, 0 }, + { -5.474339, 0.319626, 8.686158, 0 }, + { -5.384556, 0.275333, 8.689749, 0 }, + { -5.365402, 0.268150, 8.750801, 0 }, + { -5.437228, 0.357933, 8.748407, 0 }, + { -5.470747, 0.402226, 8.730451, 0 }, + { -5.386950, 0.362721, 8.672990, 0 }, + { -5.339066, 0.363918, 8.700523, 0 }, + { -5.295970, 0.398634, 8.793897, 0 }, + { -5.307941, 0.413000, 8.899241, 0 }, + { -5.295970, 0.392649, 8.924380, 0 }, + { -5.287591, 0.405817, 8.936352, 0 }, + { -5.269634, 0.417788, 8.896848, 0 }, + { -5.342658, 0.471657, 8.640668, 0 }, + { -5.464762, 0.557849, 8.434767, 0 }, + { -5.467156, 0.575805, 8.456315, 0 }, + { -5.443214, 0.561440, 8.497016, 0 }, + { -5.440820, 0.574608, 8.524549, 0 }, + { -5.438426, 0.598550, 8.480257, 0 }, + { -5.348643, 0.553060, 8.530535, 0 }, + { -5.238510, 0.509965, 8.638274, 0 }, + { -5.155910, 0.445321, 8.657428, 0 }, + { -5.111617, 0.395043, 8.583207, 0 }, + { -5.115209, 0.365116, 8.610741, 0 }, + { -5.176260, 0.344765, 8.625106, 0 }, + { -5.254072, 0.373495, 8.711297, 0 }, + { -5.267240, 0.379481, 8.808262, 0 }, + { -5.238510, 0.329203, 8.795094, 0 }, + { -5.266043, 0.282516, 8.694537, 0 }, + { -5.410892, 0.308852, 8.599967, 0 }, + { -5.538982, 0.337582, 8.520958, 0 }, + { -5.544967, 0.344765, 8.590390, 0 }, + { -5.458776, 0.276530, 8.730451, 0 }, + { -5.408498, 0.211887, 8.729254, 0 }, + { -5.450397, 0.195127, 8.633486, 0 }, + { -5.509054, 0.216675, 8.659822, 0 }, + { -5.483915, 0.190339, 8.823824, 0 }, + { -5.430046, 0.169988, 9.004586, 0 }, + { -5.392936, 0.186748, 9.078807, 0 }, + { -5.406104, 0.197522, 9.024938, 0 }, + { -5.462368, 0.269348, 8.857343, 0 }, + { -5.462368, 0.290895, 8.724465, 0 }, + { -5.409695, 0.284910, 8.667005, 0 }, + { -5.389344, 0.288501, 8.643063, 0 }, + { -5.354629, 0.284910, 8.577222, 0 }, + { -5.329489, 0.287304, 8.591587, 0 }, + { -5.280408, 0.282516, 8.658625, 0 }, + { -5.206188, 0.225055, 8.695735, 0 }, + { -5.169078, 0.235829, 8.741224, 0 }, + { -5.181049, 0.256179, 8.693340, 0 }, + { -5.245692, 0.262165, 8.619121, 0 }, + { -5.334278, 0.257377, 8.613134, 0 }, + { -5.388147, 0.248997, 8.681370, 0 }, + { -5.376176, 0.240617, 8.742421, 0 }, + { -5.360614, 0.199916, 8.707705, 0 }, + { -5.443214, 0.190339, 8.631091, 0 }, + { -5.489901, 0.172382, 8.549688, 0 }, + { -5.524617, 0.192733, 8.529338, 0 }, + { -5.518631, 0.189142, 8.562857, 0 }, + { -5.479127, 0.158017, 8.555674, 0 }, + { -5.499477, 0.140061, 8.599967, 0 }, + { -5.519828, 0.130484, 8.643063, 0 }, + { -5.493492, 0.090980, 8.652639, 0 }, + { -5.458776, 0.074220, 8.610741, 0 }, + { -5.483915, 0.107739, 8.635880, 0 }, + { -5.445608, 0.087388, 8.746013, 0 }, + { -5.422863, 0.052672, 8.787911, 0 }, + { -5.402513, 0.032322, 8.768758, 0 }, + { -5.373782, -0.007183, 8.802277, 0 }, + { -5.371388, -0.031125, 8.772349, 0 }, + { -5.416878, -0.052672, 8.682567, 0 }, + { -5.614399, -0.032322, 8.693340, 0 }, + { -5.582078, 0.015562, 8.038527, 0 }, + { -5.532996, -0.019154, 8.003811, 1 }, + { -5.451593, -0.088585, 8.389277, 0 }, + { -5.433637, -0.120907, 8.461103, 0 }, + { -5.456382, -0.082600, 8.352167, 0 }, + { -5.480324, -0.110133, 8.429978, 0 }, + { -5.503069, -0.126893, 8.602361, 0 }, + { -5.524617, -0.173579, 8.689749, 0 }, + { -5.519828, -0.161609, 8.710100, 0 }, + { -5.448002, -0.165200, 8.803473, 0 }, + { -5.337869, -0.209493, 8.835795, 0 }, + { -5.226539, -0.217872, 8.792700, 0 }, + { -5.204991, -0.144849, 8.779531, 0 }, + { -5.155910, -0.038307, 8.741224, 0 }, + { -5.038594, 0.025139, 8.692143, 0 }, + { -4.826707, 0.129287, 8.741224, 0 }, + { -4.588484, 0.221464, 9.275131, 0 }, + { -4.413708, 0.146046, 9.674962, 0 }, + { -4.571725, 0.420182, 9.512156, 0 }, + { -4.693829, 0.806845, 9.115917, 0 }, + { -4.513067, 1.146822, 8.775940, 0 }, + { -3.907335, 0.906205, 8.744816, 0 }, + { -3.440465, 0.709880, 8.558068, 0 }, + { -3.076547, 0.870292, 8.097184, 0 }, + { -2.567780, 0.849941, 7.629118, 0 }, + { -0.930147, -0.430956, 9.020149, 0 }, + { 0.472855, -1.265335, 13.321329, 0 }, + { -0.475249, -0.396240, 11.602294, 0 }, + { -2.302023, 0.135272, 10.661373, 0 }, + { -2.796426, -0.083797, 11.195279, 0 }, + { -2.404974, -0.368707, 10.447092, 0 }, + { -1.205480, -0.381875, 9.781505, 0 }, + { -0.250194, 0.064643, 9.928748, 0 }, + { -0.004788, 0.374692, 9.695313, 0 }, + { 0.256179, -0.470460, 8.904030, 0 }, + { 0.268150, -0.964863, 8.276750, 0 }, + { 0.314837, -0.756567, 8.742421, 0 }, + { 0.496797, -0.694318, 9.910791, 0 }, + { 0.828393, -0.748188, 10.779886, 0 }, + { 0.738611, -0.306458, 11.670528, 0 }, + { 0.616507, -0.045490, 11.973394, 0 }, + { 0.690727, -0.164003, 11.194082, 0 }, + { 0.632069, -0.343568, 10.463851, 0 }, + { 0.422576, 0.026336, 10.319002, 0 }, + { 0.520739, 0.468066, 10.074794, 0 }, + { 0.845153, 0.277727, 9.525325, 0 }, + { 1.058236, -0.199916, 9.085989, 0 }, + { 1.198297, -0.499191, 9.630670, 0 }, + { 1.109712, -0.314837, 10.516523, 0 }, + { 1.086967, 0.258574, 10.805025, 0 }, + { 1.313219, 0.523133, 10.685315, 0 }, + { 1.334767, 0.202310, 10.316608, 0 }, + { 1.298854, -0.199916, 9.993391, 0 }, + { 1.471236, -0.282516, 10.037683, 0 }, + { 1.620873, 0.053870, 9.892835, 0 }, + { 1.553836, 0.363918, 9.296679, 0 }, + { 1.425746, 0.114922, 8.937549, 0 }, + { 1.545456, -0.174777, 9.566027, 0 }, + { 1.985989, 0.075417, 10.395617, 0 }, + { 2.272096, 0.312443, 10.295060, 0 }, + { 2.181116, 0.196324, 9.525325, 0 }, + { 1.965638, 0.197522, 9.500186, 0 }, + { 2.054224, -0.038307, 9.800658, 0 }, + { 1.924937, 0.196324, 9.728832, 0 }, + { 2.146400, 0.402226, 9.747986, 0 }, + { 2.321177, 0.282516, 9.983814, 0 }, + { 2.279279, 0.118513, 7.716507, 0 }, + { 2.229000, -0.113724, 9.612713, 0 }, + { 2.345119, 0.343568, 11.982971, 0 }, + { 2.196679, 0.189142, 9.917974, 0 }, + { 2.218226, -0.119710, 9.633064, 0 }, + { 2.020705, 0.239420, 9.703692, 0 }, + { 1.997960, 0.318429, 9.247598, 0 }, + { 1.975215, 0.132878, 8.886073, 0 }, + { 1.841140, 0.253785, 8.754393, 0 }, + { 1.507149, 0.458489, 8.775940, 0 }, + { 1.295262, 0.497994, 9.170983, 0 }, + { 1.291671, 0.102951, 9.712072, 0 }, + { 1.267729, 0.034716, 9.686934, 0 }, + { 1.474827, -0.047884, 9.932339, 0 }, + { 1.121683, -0.041899, 10.319002, 0 }, + { 0.475249, 0.349553, 11.362873, 0 }, + { 0.029928, 0.153229, 13.443434, 0 }, + { 1.442506, -0.270545, 12.089513, 0 }, + { 0.821211, 0.186748, 10.431530, 0 }, + { 0.302866, 0.573411, 9.538493, 0 }, + { 0.973242, -0.051475, 8.095987, 0 }, + { 1.428140, -1.648407, 7.060496, 0 }, + { 1.292868, -2.129641, 8.062469, 0 }, + { 0.068235, 0.414197, 8.157040, 0 }, + { -1.018732, 1.418563, 9.985011, 0 }, + { -1.479616, 1.746569, 18.444918, 0 }, + { 0.362721, 0.951695, 11.461036, 0 }, + { 0.283713, -0.120907, 8.001416, 0 }, + { -0.320823, 0.131681, 11.031277, 0 }, + { -0.141258, 0.141258, 9.783898, 0 }, + { -0.098162, 0.118513, 10.248373, 0 }, + { -0.278924, 0.311246, 9.223656, 0 }, + { -0.034716, 0.162806, 9.734818, 0 }, + { -0.282516, -0.306458, 12.023673, 0 }, + { -0.219069, 0.069432, 9.692919, 0 }, + { -0.235829, 0.088585, 10.111904, 0 }, + { -0.243011, 0.071826, 10.181335, 0 }, + { -0.237026, 0.084994, 10.177745, 0 }, + { -0.246603, 0.079009, 10.078385, 0 }, + { -0.222661, 0.083797, 10.192110, 0 }, + { -0.252588, 0.067038, 10.103524, 0 }, + { -0.226252, 0.084994, 10.156197, 0 }, + { -0.265756, 0.071826, 10.116693, 0 }, + { -0.235829, 0.083797, 10.168168, 0 }, + { -0.251391, 0.083797, 10.108313, 0 }, + { -0.248997, 0.083797, 10.155000, 0 }, + { -0.228646, 0.083797, 10.122678, 0 }, + { -0.266953, 0.067038, 10.104721, 0 }, + { -0.233435, 0.074220, 10.141831, 0 }, + { -0.259771, 0.080206, 10.107116, 0 }, + { -0.245406, 0.080206, 10.166970, 0 }, + { -0.256179, 0.075417, 10.099933, 0 }, + { -0.243011, 0.070629, 10.153803, 0 }, + { -0.256179, 0.073023, 10.090356, 0 }, + { -0.258574, 0.077812, 10.200489, 0 }, + { -0.253785, 0.063446, 10.095144, 0 }, + { -0.245406, 0.073023, 10.135846, 0 }, + { -0.251391, 0.082600, 10.134649, 0 }, + { -0.251391, 0.068235, 10.116693, 0 }, + { -0.247800, 0.079009, 10.164577, 0 }, + { -0.244208, 0.075417, 10.115496, 0 }, + { -0.238223, 0.073023, 10.137043, 0 }, + { -0.251391, 0.077812, 10.078385, 0 }, + { -0.235829, 0.077812, 10.131058, 0 }, + { -0.250194, 0.087388, 10.123875, 0 }, + { -0.250194, 0.079009, 10.147817, 0 }, + { -0.254982, 0.064643, 10.110707, 0 }, + { -0.256179, 0.083797, 10.151408, 0 }, + { -0.237026, 0.079009, 10.103524, 0 }, + { -0.256179, 0.079009, 10.137043, 0 }, + { -0.246603, 0.081403, 10.139438, 0 }, + { -0.243011, 0.077812, 10.115496, 0 }, + { -0.254982, 0.063446, 10.159788, 0 }, + { -0.248997, 0.089783, 10.092751, 0 }, + { -0.251391, 0.074220, 10.164577, 0 }, + { -0.246603, 0.079009, 10.117889, 0 }, + { -0.247800, 0.086191, 10.145423, 0 }, + { -0.247800, 0.088585, 10.123875, 0 }, + { -0.254982, 0.075417, 10.122678, 0 }, + { -0.250194, 0.080206, 10.147817, 0 }, + { -0.251391, 0.068235, 10.113101, 0 }, + { -0.246603, 0.074220, 10.147817, 0 }, + { -0.243011, 0.068235, 10.104721, 0 }, + { -0.245406, 0.063446, 10.143028, 0 }, + { -0.250194, 0.075417, 10.121481, 0 }, + { -0.252588, 0.079009, 10.141831, 0 }, + { -0.245406, 0.071826, 10.129861, 0 }, + { -0.240617, 0.079009, 10.135846, 0 }, + { -0.240617, 0.069432, 10.141831, 0 }, + { -0.245406, 0.079009, 10.121481, 0 }, + { -0.252588, 0.069432, 10.160985, 0 }, + { -0.258574, 0.067038, 10.121481, 0 }, + { -0.260968, 0.067038, 10.140635, 0 }, + { -0.250194, 0.068235, 10.127466, 0 }, + { -0.239420, 0.074220, 10.129861, 0 }, + { -0.250194, 0.065841, 10.131058, 0 }, + { -0.245406, 0.074220, 10.128663, 0 }, + { -0.247800, 0.088585, 10.133451, 0 }, + { -0.245406, 0.082600, 10.105919, 0 }, + { -0.251391, 0.067038, 10.133451, 0 }, + { -0.241814, 0.075417, 10.121481, 0 }, + { -0.247800, 0.075417, 10.140635, 0 }, + { -0.254982, 0.080206, 10.132255, 0 }, + { -0.237026, 0.074220, 10.137043, 0 }, + { -0.251391, 0.082600, 10.135846, 0 }, + { -0.247800, 0.095768, 10.135846, 0 }, + { -0.244208, 0.075417, 10.115496, 0 }, + { -0.245406, 0.074220, 10.138240, 0 }, + { -0.239420, 0.080206, 10.137043, 0 }, + { -0.257377, 0.073023, 10.128663, 0 }, + { -0.253785, 0.081403, 10.134649, 0 }, + { -0.256179, 0.061052, 10.137043, 0 }, + { -0.243011, 0.082600, 10.129861, 0 }, + { -0.246603, 0.080206, 10.116693, 0 }, + { -0.240617, 0.080206, 10.120284, 0 }, + { -0.251391, 0.069432, 10.109509, 0 }, + { -0.247800, 0.073023, 10.144226, 0 }, + { -0.248997, 0.077812, 10.110707, 0 }, + { -0.256179, 0.065841, 10.134649, 0 }, + { -0.246603, 0.071826, 10.111904, 0 }, + { -0.265756, 0.075417, 10.123875, 0 }, + { -0.245406, 0.084994, 10.131058, 0 }, + { -0.251391, 0.073023, 10.114298, 0 }, + { -0.247800, 0.090980, 10.145423, 0 }, + { -0.263362, 0.088585, 10.121481, 0 }, + { -0.258574, 0.074220, 10.149014, 0 }, + { -0.252588, 0.069432, 10.114298, 0 }, + { -0.259771, 0.074220, 10.121481, 0 }, + { -0.251391, 0.068235, 10.137043, 0 }, + { -0.245406, 0.074220, 10.131058, 0 }, + { -0.244208, 0.074220, 10.121481, 0 }, + { -0.253785, 0.070629, 10.108313, 0 }, + { -0.256179, 0.077812, 10.144226, 0 }, + { -0.241814, 0.058658, 10.104721, 0 }, + { -0.244208, 0.069432, 10.133451, 0 }, + { -0.241814, 0.081403, 10.113101, 0 }, + { -0.253785, 0.080206, 10.110707, 0 }, + { -0.257377, 0.086191, 10.121481, 0 }, + { -0.252588, 0.080206, 10.129861, 0 }, + { -0.246603, 0.081403, 10.121481, 0 }, + { -0.245406, 0.086191, 10.123875, 0 }, + { -0.251391, 0.076614, 10.153803, 0 }, + { -0.246603, 0.068235, 10.120284, 0 }, + { -0.234632, 0.090980, 10.134649, 0 }, + { -0.253785, 0.080206, 10.098736, 0 }, + { -0.256179, 0.093374, 10.135846, 0 }, + { -0.259771, 0.076614, 10.126269, 0 }, + { -0.240617, 0.074220, 10.147817, 0 }, + { -0.256179, 0.068235, 10.119086, 0 }, + { -0.254982, 0.073023, 10.120284, 0 }, + { -0.250194, 0.082600, 10.143028, 0 }, + { -0.250194, 0.076614, 10.115496, 0 }, + { -0.247800, 0.068235, 10.145423, 0 }, + { -0.241814, 0.077812, 10.122678, 0 }, + { -0.245406, 0.079009, 10.138240, 0 }, + { -0.266953, 0.083797, 10.111904, 0 }, + { -0.254982, 0.074220, 10.116693, 0 }, + { -0.248997, 0.090980, 10.138240, 0 }, + { -0.262165, 0.083797, 10.123875, 0 }, + { -0.245406, 0.081403, 10.128663, 0 }, + { -0.252588, 0.065841, 10.103524, 0 }, + { -0.248997, 0.089783, 10.128663, 0 }, + { -0.250194, 0.070629, 10.108313, 0 }, + { -0.248997, 0.068235, 10.147817, 0 }, + { -0.251391, 0.083797, 10.125072, 0 }, + { -0.258574, 0.070629, 10.125072, 0 }, + { -0.259771, 0.058658, 10.125072, 0 }, + { -0.246603, 0.070629, 10.120284, 0 }, + { -0.243011, 0.064643, 10.128663, 0 }, + { -0.263362, 0.073023, 10.134649, 0 }, + { -0.246603, 0.076614, 10.140635, 0 }, + { -0.246603, 0.084994, 10.122678, 0 }, + { -0.241814, 0.068235, 10.131058, 0 }, + { -0.243011, 0.073023, 10.115496, 0 }, + { -0.252588, 0.074220, 10.157393, 0 }, + { -0.264559, 0.076614, 10.105919, 0 }, + { -0.254982, 0.069432, 10.135846, 0 }, + { -0.234632, 0.075417, 10.126269, 0 }, + { -0.239420, 0.080206, 10.120284, 0 }, + { -0.251391, 0.087388, 10.146620, 0 }, + { -0.238223, 0.069432, 10.126269, 0 }, + { -0.247800, 0.065841, 10.127466, 0 }, + { -0.253785, 0.069432, 10.113101, 0 }, + { -0.252588, 0.079009, 10.144226, 0 }, + { -0.254982, 0.074220, 10.123875, 0 }, + { -0.247800, 0.061052, 10.134649, 0 }, + { -0.248997, 0.067038, 10.119086, 0 }, + { -0.247800, 0.077812, 10.123875, 0 }, + { -0.253785, 0.079009, 10.134649, 0 }, + { -0.246603, 0.084994, 10.111904, 0 }, + { -0.253785, 0.087388, 10.139438, 0 }, + { -0.256179, 0.082600, 10.097539, 0 }, + { -0.240617, 0.087388, 10.149014, 0 }, + { -0.252588, 0.059855, 10.108313, 0 }, + { -0.235829, 0.082600, 10.129861, 0 }, + { -0.247800, 0.094571, 10.127466, 0 }, + { -0.248997, 0.082600, 10.122678, 0 }, + { -0.240617, 0.084994, 10.131058, 0 }, + { -0.253785, 0.077812, 10.116693, 0 }, + { -0.258574, 0.086191, 10.133451, 0 }, + { -0.247800, 0.071826, 10.128663, 0 }, + { -0.247800, 0.074220, 10.132255, 0 }, + { -0.254982, 0.071826, 10.120284, 0 }, + { -0.253785, 0.080206, 10.140635, 0 }, + { -0.269348, 0.076614, 10.132255, 0 }, + { -0.253785, 0.082600, 10.131058, 0 }, + { -0.244208, 0.089783, 10.140635, 0 }, + { -0.247800, 0.073023, 10.110707, 0 }, + { -0.252588, 0.070629, 10.129861, 0 }, + { -0.257377, 0.071826, 10.125072, 0 }, + { -0.252588, 0.074220, 10.117889, 0 }, + { -0.254982, 0.068235, 10.128663, 0 }, + { -0.259771, 0.058658, 10.134649, 0 }, + { -0.252588, 0.070629, 10.119086, 0 }, + { -0.243011, 0.089783, 10.146620, 0 }, + { -0.240617, 0.075417, 10.128663, 0 }, + { -0.254982, 0.063446, 10.145423, 0 }, + { -0.272939, 0.081403, 10.127466, 0 }, + { -0.241814, 0.075417, 10.127466, 0 }, + { -0.233435, 0.073023, 10.125072, 0 }, + { -0.248997, 0.080206, 10.132255, 0 }, + { -0.241814, 0.074220, 10.134649, 0 }, + { -0.266953, 0.068235, 10.133451, 0 }, + { -0.245406, 0.069432, 10.127466, 0 }, + { -0.247800, 0.087388, 10.131058, 0 }, + { -0.247800, 0.082600, 10.129861, 0 }, + { -0.257377, 0.070629, 10.137043, 0 }, + { -0.247800, 0.074220, 10.131058, 0 }, + { -0.252588, 0.086191, 10.114298, 0 }, + { -0.247800, 0.089783, 10.135846, 0 }, + { -0.256179, 0.073023, 10.131058, 0 }, + { -0.257377, 0.080206, 10.133451, 0 }, + { -0.245406, 0.069432, 10.125072, 0 }, + { -0.250194, 0.061052, 10.126269, 0 }, + { -0.252588, 0.079009, 10.135846, 0 }, + { -0.250194, 0.073023, 10.128663, 0 }, + { -0.237026, 0.075417, 10.155000, 0 }, + { -0.247800, 0.079009, 10.140635, 0 }, + { -0.251391, 0.069432, 10.151408, 0 }, + { -0.244208, 0.075417, 10.127466, 0 }, + { -0.252588, 0.071826, 10.111904, 0 }, + { -0.257377, 0.077812, 10.138240, 0 }, + { -0.241814, 0.069432, 10.122678, 0 }, + { -0.253785, 0.071826, 10.139438, 0 }, + { -0.256179, 0.077812, 10.119086, 0 }, + { -0.262165, 0.077812, 10.133451, 0 }, + { -0.252588, 0.061052, 10.132255, 0 }, + { -0.250194, 0.077812, 10.119086, 0 }, + { -0.253785, 0.081403, 10.132255, 0 }, + { -0.253785, 0.079009, 10.117889, 0 }, + { -0.252588, 0.064643, 10.129861, 0 }, + { -0.247800, 0.073023, 10.117889, 0 }, + { -0.253785, 0.065841, 10.126269, 0 }, + { -0.256179, 0.069432, 10.128663, 0 }, + { -0.250194, 0.080206, 10.128663, 0 }, + { -0.257377, 0.084994, 10.107116, 0 }, + { -0.254982, 0.080206, 10.137043, 0 }, + { -0.259771, 0.076614, 10.137043, 0 }, + { -0.265756, 0.063446, 10.132255, 0 }, + { -0.251391, 0.056264, 10.120284, 0 }, + { -0.247800, 0.067038, 10.132255, 0 }, + { -0.247800, 0.074220, 10.126269, 0 }, + { -0.247800, 0.070629, 10.127466, 0 }, + { -0.239420, 0.081403, 10.143028, 0 }, + { -0.254982, 0.081403, 10.129861, 0 }, + { -0.259771, 0.088585, 10.138240, 0 }, + { -0.246603, 0.080206, 10.108313, 0 }, + { -0.252588, 0.086191, 10.125072, 0 }, + { -0.247800, 0.071826, 10.132255, 0 }, + { -0.240617, 0.073023, 10.126269, 0 }, + { -0.256179, 0.075417, 10.134649, 0 }, + { -0.254982, 0.081403, 10.117889, 0 }, + { -0.250194, 0.070629, 10.133451, 0 }, + { -0.254982, 0.064643, 10.137043, 0 }, + { -0.254982, 0.075417, 10.147817, 0 }, + { -0.240617, 0.077812, 10.122678, 0 }, + { -0.239420, 0.083797, 10.153803, 0 }, + { -0.258574, 0.070629, 10.131058, 0 }, + { -0.256179, 0.077812, 10.133451, 0 }, + { -0.265756, 0.080206, 10.143028, 0 }, + { -0.256179, 0.070629, 10.138240, 0 }, + { -0.250194, 0.067038, 10.129861, 0 }, + { -0.245406, 0.071826, 10.126269, 0 }, + { -0.259771, 0.073023, 10.135846, 0 }, + { -0.251391, 0.061052, 10.121481, 0 }, + { -0.254982, 0.075417, 10.150211, 0 }, + { -0.247800, 0.081403, 10.137043, 0 }, + { -0.248997, 0.084994, 10.126269, 0 }, + { -0.257377, 0.082600, 10.135846, 0 }, + { -0.257377, 0.073023, 10.110707, 0 }, + { -0.251391, 0.077812, 10.138240, 0 }, + { -0.238223, 0.064643, 10.116693, 0 }, + { -0.239420, 0.075417, 10.138240, 0 }, + { -0.260968, 0.071826, 10.132255, 0 }, + { -0.253785, 0.094571, 10.132255, 0 }, + { -0.248997, 0.081403, 10.127466, 0 }, + { -0.245406, 0.073023, 10.150211, 0 }, + { -0.252588, 0.080206, 10.120284, 0 }, + { -0.247800, 0.075417, 10.122678, 0 }, + { -0.246603, 0.069432, 10.122678, 0 }, + { -0.246603, 0.090980, 10.119086, 0 }, + { -0.253785, 0.076614, 10.139438, 0 }, + { -0.253785, 0.063446, 10.127466, 0 }, + { -0.248997, 0.094571, 10.146620, 0 }, + { -0.257377, 0.079009, 10.115496, 0 }, + { -0.247800, 0.068235, 10.122678, 0 }, + { -0.244208, 0.080206, 10.117889, 0 }, + { -0.257377, 0.099359, 10.134649, 0 }, + { -0.257377, 0.089783, 10.111904, 0 }, + { -0.247800, 0.073023, 10.133451, 0 }, + { -0.238223, 0.070629, 10.120284, 0 }, + { -0.256179, 0.073023, 10.125072, 0 }, + { -0.257377, 0.063446, 10.144226, 0 }, + { -0.259771, 0.081403, 10.122678, 0 }, + { -0.251391, 0.079009, 10.123875, 0 }, + { -0.256179, 0.068235, 10.122678, 0 }, + { -0.252588, 0.065841, 10.128663, 0 }, + { -0.239420, 0.074220, 10.122678, 0 }, + { -0.247800, 0.073023, 10.138240, 0 }, + { -0.245406, 0.076614, 10.111904, 0 }, + { -0.252588, 0.076614, 10.125072, 0 }, + { -0.259771, 0.059855, 10.122678, 0 }, + { -0.262165, 0.067038, 10.137043, 0 }, + { -0.248997, 0.073023, 10.127466, 0 }, + { -0.248997, 0.076614, 10.132255, 0 }, + { -0.244208, 0.080206, 10.115496, 0 }, + { -0.245406, 0.055067, 10.140635, 0 }, + { -0.251391, 0.059855, 10.135846, 0 }, + { -0.246603, 0.073023, 10.111904, 0 }, + { -0.248997, 0.081403, 10.123875, 0 }, + { -0.248997, 0.070629, 10.126269, 0 }, + { -0.251391, 0.075417, 10.129861, 0 }, + { -0.239420, 0.071826, 10.139438, 0 }, + { -0.244208, 0.076614, 10.109509, 0 }, + { -0.263362, 0.082600, 10.135846, 0 }, + { -0.252588, 0.071826, 10.127466, 0 }, + { -0.241814, 0.067038, 10.122678, 0 }, + { -0.252588, 0.079009, 10.125072, 0 }, + { -0.260968, 0.084994, 10.125072, 0 }, + { -0.245406, 0.080206, 10.119086, 0 }, + { -0.241814, 0.071826, 10.126269, 0 }, + { -0.251391, 0.075417, 10.135846, 0 }, + { -0.254982, 0.068235, 10.127466, 0 }, + { -0.260968, 0.074220, 10.127466, 0 }, + { -0.247800, 0.076614, 10.122678, 0 }, + { -0.258574, 0.067038, 10.114298, 0 }, + { -0.258574, 0.073023, 10.122678, 0 }, + { -0.257377, 0.058658, 10.145423, 0 }, + { -0.254982, 0.063446, 10.127466, 0 }, + { -0.245406, 0.068235, 10.135846, 0 }, + { -0.247800, 0.071826, 10.135846, 0 }, + { -0.256179, 0.068235, 10.138240, 0 }, + { -0.257377, 0.074220, 10.113101, 0 }, + { -0.244208, 0.081403, 10.139438, 0 }, + { -0.241814, 0.061052, 10.131058, 0 }, + { -0.257377, 0.073023, 10.116693, 0 }, + { -0.256179, 0.083797, 10.129861, 0 }, + { -0.240617, 0.084994, 10.121481, 0 }, + { -0.239420, 0.073023, 10.135846, 0 }, + { -0.252588, 0.074220, 10.132255, 0 }, + { -0.252588, 0.077812, 10.127466, 0 }, + { -0.251391, 0.082600, 10.140635, 0 }, + { -0.256179, 0.077812, 10.129861, 0 }, + { -0.254982, 0.064643, 10.117889, 0 }, + { -0.263362, 0.065841, 10.122678, 0 }, + { -0.252588, 0.079009, 10.135846, 0 }, + { -0.248997, 0.075417, 10.127466, 0 }, + { -0.238223, 0.079009, 10.133451, 0 }, + { -0.244208, 0.080206, 10.133451, 0 }, + { -0.254982, 0.076614, 10.150211, 0 }, + { -0.264559, 0.068235, 10.141831, 0 }, + { -0.246603, 0.077812, 10.132255, 0 }, + { -0.262165, 0.070629, 10.134649, 0 }, + { -0.258574, 0.062249, 10.129861, 0 }, + { -0.259771, 0.071826, 10.133451, 0 }, + { -0.243011, 0.086191, 10.125072, 0 }, + { -0.250194, 0.074220, 10.125072, 0 }, + { -0.260968, 0.059855, 10.101130, 0 }, + { -0.252588, 0.063446, 10.129861, 0 }, + { -0.251391, 0.079009, 10.128663, 0 }, + { -0.252588, 0.069432, 10.138240, 0 }, + { -0.246603, 0.074220, 10.141831, 0 }, + { -0.250194, 0.080206, 10.117889, 0 }, + { -0.256179, 0.068235, 10.131058, 0 }, + { -0.258574, 0.058658, 10.110707, 0 }, + { -0.244208, 0.073023, 10.137043, 0 }, + { -0.260968, 0.076614, 10.117889, 0 }, + { -0.245406, 0.081403, 10.119086, 0 }, + { -0.243011, 0.077812, 10.135846, 0 }, + { -0.256179, 0.069432, 10.131058, 0 }, + { -0.245406, 0.079009, 10.121481, 0 }, + { -0.250194, 0.086191, 10.129861, 0 }, + { -0.245406, 0.089783, 10.132255, 0 }, + { -0.241814, 0.077812, 10.147817, 0 }, + { -0.244208, 0.076614, 10.133451, 0 }, + { -0.263362, 0.075417, 10.096342, 0 }, + { -0.250194, 0.058658, 10.134649, 0 }, + { -0.231040, 0.068235, 10.117889, 0 }, + { -0.250194, 0.069432, 10.144226, 0 }, + { -0.263362, 0.073023, 10.117889, 0 }, + { -0.241814, 0.071826, 10.133451, 0 }, + { -0.240617, 0.073023, 10.131058, 0 }, + { -0.237026, 0.082600, 10.116693, 0 }, + { -0.239420, 0.080206, 10.138240, 0 }, + { -0.259771, 0.079009, 10.139438, 0 }, + { -0.266953, 0.071826, 10.140635, 0 }, + { -0.251391, 0.071826, 10.107116, 0 }, + { -0.258574, 0.073023, 10.132255, 0 }, + { -0.243011, 0.090980, 10.132255, 0 }, + { -0.234632, 0.064643, 10.129861, 0 }, + { -0.250194, 0.059855, 10.134649, 0 }, + { -0.238223, 0.081403, 10.140635, 0 }, + { -0.243011, 0.077812, 10.131058, 0 }, + { -0.247800, 0.069432, 10.143028, 0 }, + { -0.247800, 0.067038, 10.135846, 0 }, + { -0.243011, 0.065841, 10.128663, 0 }, + { -0.253785, 0.077812, 10.129861, 0 }, + { -0.244208, 0.080206, 10.107116, 0 }, + { -0.244208, 0.074220, 10.143028, 0 }, + { -0.253785, 0.080206, 10.119086, 0 }, + { -0.247800, 0.070629, 10.139438, 0 }, + { -0.243011, 0.082600, 10.125072, 0 }, + { -0.257377, 0.075417, 10.150211, 0 }, + { -0.263362, 0.077812, 10.152605, 0 }, + { -0.263362, 0.081403, 10.135846, 0 }, + { -0.250194, 0.075417, 10.139438, 0 }, + { -0.248997, 0.077812, 10.131058, 0 }, + { -0.247800, 0.074220, 10.127466, 0 }, + { -0.243011, 0.069432, 10.122678, 0 }, + { -0.251391, 0.079009, 10.133451, 0 }, + { -0.252588, 0.061052, 10.126269, 0 }, + { -0.265756, 0.081403, 10.128663, 0 }, + { -0.244208, 0.064643, 10.122678, 0 }, + { -0.256179, 0.065841, 10.123875, 0 }, + { -0.263362, 0.076614, 10.125072, 0 }, + { -0.252588, 0.079009, 10.126269, 0 }, + { -0.252588, 0.070629, 10.115496, 0 }, + { -0.254982, 0.073023, 10.115496, 0 }, + { -0.234632, 0.070629, 10.123875, 0 }, + { -0.237026, 0.076614, 10.121481, 0 }, + { -0.256179, 0.070629, 10.134649, 0 }, + { -0.268150, 0.073023, 10.129861, 0 }, + { -0.244208, 0.075417, 10.121481, 0 }, + { -0.253785, 0.080206, 10.126269, 0 }, + { -0.259771, 0.075417, 10.120284, 0 }, + { -0.263362, 0.070629, 10.115496, 0 }, + { -0.247800, 0.075417, 10.126269, 0 }, + { -0.243011, 0.068235, 10.152605, 0 }, + { -0.247800, 0.069432, 10.125072, 0 }, + { -0.257377, 0.083797, 10.129861, 0 }, + { -0.247800, 0.075417, 10.129861, 0 }, + { -0.247800, 0.076614, 10.115496, 0 }, + { -0.247800, 0.071826, 10.131058, 0 }, + { -0.258574, 0.083797, 10.125072, 0 }, + { -0.250194, 0.095768, 10.132255, 0 }, + { -0.266953, 0.076614, 10.123875, 0 }, + { -0.256179, 0.079009, 10.152605, 0 }, + { -0.251391, 0.073023, 10.126269, 0 }, + { -0.248997, 0.068235, 10.128663, 0 }, + { -0.243011, 0.073023, 10.134649, 0 }, + { -0.258574, 0.071826, 10.137043, 0 }, + { -0.253785, 0.061052, 10.119086, 0 }, + { -0.250194, 0.073023, 10.138240, 0 }, + { -0.241814, 0.070629, 10.113101, 0 }, + { -0.250194, 0.079009, 10.141831, 0 }, + { -0.237026, 0.070629, 10.128663, 0 }, + { -0.240617, 0.083797, 10.120284, 0 }, + { -0.259771, 0.073023, 10.144226, 0 }, + { -0.232237, 0.068235, 10.122678, 0 }, + { -0.246603, 0.065841, 10.133451, 0 }, + { -0.258574, 0.079009, 10.109509, 0 }, + { -0.245406, 0.075417, 10.131058, 0 }, + { -0.240617, 0.076614, 10.127466, 0 }, + { -0.246603, 0.074220, 10.115496, 0 }, + { -0.247800, 0.068235, 10.129861, 0 }, + { -0.252588, 0.073023, 10.145423, 0 }, + { -0.252588, 0.069432, 10.132255, 0 }, + { -0.248997, 0.062249, 10.110707, 0 }, + { -0.257377, 0.073023, 10.146620, 0 }, + { -0.247800, 0.077812, 10.133451, 0 }, + { -0.233435, 0.075417, 10.123875, 0 }, + { -0.259771, 0.080206, 10.117889, 0 }, + { -0.252588, 0.071826, 10.131058, 0 }, + { -0.257377, 0.077812, 10.128663, 0 }, + { -0.244208, 0.065841, 10.138240, 0 }, + { -0.245406, 0.076614, 10.132255, 0 }, + { -0.259771, 0.074220, 10.134649, 0 }, + { -0.251391, 0.073023, 10.133451, 0 }, + { -0.238223, 0.063446, 10.127466, 0 }, + { -0.246603, 0.052672, 10.128663, 0 }, + { -0.260968, 0.069432, 10.125072, 0 }, + { -0.251391, 0.087388, 10.104721, 0 }, + { -0.243011, 0.074220, 10.120284, 0 }, + { -0.259771, 0.069432, 10.149014, 0 }, + { -0.252588, 0.083797, 10.139438, 0 }, + { -0.252588, 0.070629, 10.134649, 0 }, + { -0.244208, 0.071826, 10.134649, 0 }, + { -0.244208, 0.080206, 10.122678, 0 }, + { -0.263362, 0.076614, 10.126269, 0 }, + { -0.243011, 0.076614, 10.113101, 0 }, + { -0.250194, 0.084994, 10.133451, 0 }, + { -0.247800, 0.081403, 10.151408, 0 }, + { -0.247800, 0.082600, 10.123875, 0 }, + { -0.240617, 0.080206, 10.133451, 0 }, + { -0.254982, 0.074220, 10.135846, 0 }, + { -0.260968, 0.076614, 10.123875, 0 }, + { -0.251391, 0.069432, 10.127466, 0 }, + { -0.251391, 0.080206, 10.140635, 0 }, + { -0.248997, 0.065841, 10.129861, 0 }, + { -0.245406, 0.081403, 10.137043, 0 }, + { -0.248997, 0.096965, 10.128663, 0 }, + { -0.264559, 0.069432, 10.149014, 0 }, + { -0.254982, 0.071826, 10.114298, 0 }, + { -0.257377, 0.071826, 10.140635, 0 }, + { -0.254982, 0.077812, 10.128663, 0 }, + { -0.256179, 0.083797, 10.126269, 0 }, + { -0.254982, 0.063446, 10.143028, 0 }, + { -0.247800, 0.058658, 10.133451, 0 }, + { -0.251391, 0.068235, 10.137043, 0 }, + { -0.245406, 0.080206, 10.102327, 0 }, + { -0.243011, 0.070629, 10.129861, 0 }, + { -0.253785, 0.073023, 10.111904, 0 }, + { -0.251391, 0.076614, 10.145423, 0 }, + { -0.247800, 0.075417, 10.133451, 0 }, + { -0.248997, 0.065841, 10.139438, 0 }, + { -0.248997, 0.063446, 10.125072, 0 }, + { -0.252588, 0.070629, 10.102327, 0 }, + { -0.246603, 0.083797, 10.113101, 0 }, + { -0.237026, 0.074220, 10.116693, 0 }, + { -0.240617, 0.073023, 10.138240, 0 }, + { -0.235829, 0.076614, 10.116693, 0 }, + { -0.247800, 0.073023, 10.141831, 0 }, + { -0.258574, 0.075417, 10.134649, 0 }, + { -0.253785, 0.081403, 10.126269, 0 }, + { -0.250194, 0.082600, 10.121481, 0 }, + { -0.250194, 0.088585, 10.149014, 0 }, + { -0.253785, 0.069432, 10.126269, 0 }, + { -0.252588, 0.083797, 10.128663, 0 }, + { -0.245406, 0.058658, 10.133451, 0 }, + { -0.258574, 0.087388, 10.119086, 0 }, + { -0.253785, 0.064643, 10.131058, 0 }, + { -0.248997, 0.067038, 10.128663, 0 }, + { -0.248997, 0.075417, 10.155000, 0 }, + { -0.251391, 0.079009, 10.132255, 0 }, + { -0.253785, 0.087388, 10.131058, 0 }, + { -0.240617, 0.088585, 10.113101, 0 }, + { -0.247800, 0.077812, 10.134649, 0 }, + { -0.247800, 0.077812, 10.122678, 0 }, + { -0.263362, 0.086191, 10.131058, 0 }, + { -0.243011, 0.084994, 10.129861, 0 }, + { -0.243011, 0.077812, 10.113101, 0 }, + { -0.252588, 0.077812, 10.125072, 0 }, + { -0.248997, 0.076614, 10.096342, 0 }, + { -0.241814, 0.070629, 10.158591, 0 }, + { -0.257377, 0.075417, 10.117889, 0 }, + { -0.250194, 0.076614, 10.131058, 0 }, + { -0.250194, 0.071826, 10.135846, 0 }, + { -0.253785, 0.069432, 10.115496, 0 }, + { -0.248997, 0.069432, 10.144226, 0 }, + { -0.246603, 0.068235, 10.110707, 0 }, + { -0.260968, 0.075417, 10.151408, 0 }, + { -0.246603, 0.074220, 10.113101, 0 }, + { -0.254982, 0.076614, 10.122678, 0 }, + { -0.250194, 0.063446, 10.116693, 0 }, + { -0.233435, 0.077812, 10.134649, 0 }, + { -0.245406, 0.079009, 10.135846, 0 }, + { -0.250194, 0.079009, 10.119086, 0 }, + { -0.264559, 0.086191, 10.109509, 0 }, + { -0.252588, 0.090980, 10.126269, 0 }, + { -0.250194, 0.082600, 10.147817, 0 }, + { -0.238223, 0.070629, 10.125072, 0 }, + { -0.245406, 0.082600, 10.139438, 0 }, + { -0.239420, 0.082600, 10.131058, 0 }, + { -0.251391, 0.087388, 10.147817, 0 }, + { -0.257377, 0.073023, 10.128663, 0 }, + { -0.251391, 0.081403, 10.144226, 0 }, + { -0.254982, 0.086191, 10.120284, 0 }, + { -0.253785, 0.080206, 10.146620, 0 }, + { -0.256179, 0.077812, 10.149014, 0 }, + { -0.248997, 0.083797, 10.128663, 0 }, + { -0.251391, 0.071826, 10.125072, 0 }, + { -0.244208, 0.068235, 10.113101, 0 }, + { -0.252588, 0.070629, 10.132255, 0 }, + { -0.258574, 0.064643, 10.116693, 0 }, + { -0.246603, 0.074220, 10.135846, 0 }, + { -0.247800, 0.070629, 10.123875, 0 }, + { -0.239420, 0.081403, 10.144226, 0 }, + { -0.247800, 0.075417, 10.121481, 0 }, + { -0.259771, 0.073023, 10.103524, 0 }, + { -0.248997, 0.073023, 10.129861, 0 }, + { -0.241814, 0.071826, 10.134649, 0 }, + { -0.235829, 0.079009, 10.127466, 0 }, + { -0.244208, 0.095768, 10.122678, 0 }, + { -0.227449, 0.065841, 10.147817, 0 }, + { -0.251391, 0.074220, 10.135846, 0 }, + { -0.251391, 0.074220, 10.137043, 0 }, + { -0.253785, 0.077812, 10.125072, 0 }, + { -0.259771, 0.071826, 10.135846, 0 }, + { -0.227449, 0.067038, 10.122678, 0 }, + { -0.235829, 0.065841, 10.127466, 0 }, + { -0.251391, 0.076614, 10.128663, 0 }, + { -0.238223, 0.058658, 10.128663, 0 }, + { -0.238223, 0.074220, 10.126269, 0 }, + { -0.246603, 0.084994, 10.140635, 0 }, + { -0.258574, 0.071826, 10.132255, 0 }, + { -0.252588, 0.074220, 10.122678, 0 }, + { -0.245406, 0.076614, 10.121481, 0 }, + { -0.244208, 0.074220, 10.134649, 0 }, + { -0.248997, 0.069432, 10.122678, 0 }, + { -0.246603, 0.077812, 10.127466, 0 }, + { -0.256179, 0.083797, 10.133451, 0 }, + { -0.247800, 0.086191, 10.135846, 0 }, + { -0.248997, 0.076614, 10.144226, 0 }, + { -0.253785, 0.073023, 10.120284, 0 }, + { -0.256179, 0.071826, 10.140635, 0 }, + { -0.254982, 0.083797, 10.123875, 0 }, + { -0.247800, 0.076614, 10.131058, 0 }, + { -0.259771, 0.077812, 10.117889, 0 }, + { -0.243011, 0.069432, 10.132255, 0 }, + { -0.250194, 0.075417, 10.120284, 0 }, + { -0.247800, 0.086191, 10.128663, 0 }, + { -0.241814, 0.065841, 10.150211, 0 }, + { -0.250194, 0.075417, 10.128663, 0 }, + { -0.234632, 0.079009, 10.103524, 0 }, + { -0.266953, 0.073023, 10.127466, 0 }, + { -0.237026, 0.080206, 10.119086, 0 }, + { -0.254982, 0.075417, 10.151408, 0 }, + { -0.248997, 0.063446, 10.129861, 0 }, + { -0.254982, 0.071826, 10.135846, 0 }, + { -0.246603, 0.075417, 10.125072, 0 }, + { -0.237026, 0.069432, 10.126269, 0 }, + { -0.243011, 0.070629, 10.146620, 0 }, + { -0.244208, 0.082600, 10.137043, 0 }, + { -0.263362, 0.071826, 10.138240, 0 }, + { -0.250194, 0.074220, 10.149014, 0 }, + { -0.250194, 0.070629, 10.137043, 0 }, + { -0.253785, 0.080206, 10.122678, 0 }, + { -0.247800, 0.080206, 10.131058, 0 }, + { -0.237026, 0.082600, 10.134649, 0 }, + { -0.243011, 0.079009, 10.129861, 0 }, + { -0.246603, 0.071826, 10.117889, 0 }, + { -0.256179, 0.074220, 10.135846, 0 }, + { -0.250194, 0.075417, 10.128663, 0 }, + { -0.247800, 0.074220, 10.120284, 0 }, + { -0.251391, 0.065841, 10.141831, 0 }, + { -0.248997, 0.062249, 10.115496, 0 }, + { -0.260968, 0.068235, 10.141831, 0 }, + { -0.248997, 0.079009, 10.141831, 0 }, + { -0.247800, 0.075417, 10.156197, 0 }, + { -0.246603, 0.070629, 10.132255, 0 }, + { -0.252588, 0.082600, 10.116693, 0 }, + { -0.252588, 0.074220, 10.122678, 0 }, + { -0.262165, 0.071826, 10.123875, 0 }, + { -0.251391, 0.067038, 10.121481, 0 }, + { -0.239420, 0.081403, 10.113101, 0 }, + { -0.247800, 0.084994, 10.132255, 0 }, + { -0.252588, 0.075417, 10.138240, 0 }, + { -0.246603, 0.075417, 10.125072, 0 }, + { -0.246603, 0.076614, 10.109509, 0 }, + { -0.253785, 0.074220, 10.125072, 0 }, + { -0.251391, 0.081403, 10.139438, 0 }, + { -0.243011, 0.073023, 10.114298, 0 }, + { -0.253785, 0.065841, 10.107116, 0 }, + { -0.243011, 0.080206, 10.121481, 0 }, + { -0.253785, 0.069432, 10.129861, 0 }, + { -0.256179, 0.068235, 10.121481, 0 }, + { -0.246603, 0.068235, 10.121481, 0 }, + { -0.254982, 0.075417, 10.121481, 0 }, + { -0.241814, 0.074220, 10.120284, 0 }, + { -0.258574, 0.073023, 10.127466, 0 }, + { -0.235829, 0.074220, 10.128663, 0 }, + { -0.247800, 0.071826, 10.120284, 0 }, + { -0.258574, 0.073023, 10.119086, 0 }, + { -0.256179, 0.082600, 10.125072, 0 }, + { -0.243011, 0.081403, 10.128663, 0 }, + { -0.241814, 0.069432, 10.132255, 0 }, + { -0.252588, 0.074220, 10.135846, 0 }, + { -0.235829, 0.076614, 10.138240, 0 }, + { -0.252588, 0.069432, 10.133451, 0 }, + { -0.257377, 0.087388, 10.129861, 0 }, + { -0.252588, 0.079009, 10.120284, 0 }, + { -0.245406, 0.077812, 10.132255, 0 }, + { -0.244208, 0.077812, 10.105919, 0 }, + { -0.252588, 0.064643, 10.128663, 0 }, + { -0.257377, 0.080206, 10.122678, 0 }, + { -0.227449, 0.075417, 10.122678, 0 }, + { -0.256179, 0.076614, 10.139438, 0 }, + { -0.250194, 0.068235, 10.134649, 0 }, + { -0.244208, 0.080206, 10.145423, 0 }, + { -0.244208, 0.075417, 10.117889, 0 }, + { -0.245406, 0.071826, 10.137043, 0 }, + { -0.251391, 0.069432, 10.132255, 0 }, + { -0.252588, 0.065841, 10.127466, 0 }, + { -0.252588, 0.087388, 10.135846, 0 }, + { -0.250194, 0.083797, 10.140635, 0 }, + { -0.265756, 0.083797, 10.127466, 0 }, + { -0.251391, 0.081403, 10.116693, 0 }, + { -0.243011, 0.073023, 10.131058, 0 }, + { -0.256179, 0.079009, 10.132255, 0 }, + { -0.256179, 0.079009, 10.135846, 0 }, + { -0.259771, 0.080206, 10.139438, 0 }, + { -0.248997, 0.069432, 10.134649, 0 }, + { -0.247800, 0.076614, 10.109509, 0 }, + { -0.251391, 0.069432, 10.140635, 0 }, + { -0.248997, 0.065841, 10.129861, 0 }, + { -0.256179, 0.084994, 10.119086, 0 }, + { -0.253785, 0.082600, 10.111904, 0 }, + { -0.251391, 0.079009, 10.134649, 0 }, + { -0.258574, 0.077812, 10.125072, 0 }, + { -0.254982, 0.062249, 10.108313, 0 }, + { -0.272939, 0.080206, 10.151408, 0 }, + { -0.260968, 0.082600, 10.113101, 0 }, + { -0.244208, 0.086191, 10.123875, 0 }, + { -0.247800, 0.079009, 10.116693, 0 }, + { -0.247800, 0.075417, 10.141831, 0 }, + { -0.259771, 0.076614, 10.120284, 0 }, + { -0.239420, 0.081403, 10.134649, 0 }, + { -0.253785, 0.080206, 10.121481, 0 }, + { -0.262165, 0.074220, 10.119086, 0 }, + { -0.253785, 0.069432, 10.127466, 0 }, + { -0.262165, 0.069432, 10.104721, 0 }, + { -0.252588, 0.084994, 10.120284, 0 }, + { -0.251391, 0.063446, 10.113101, 0 }, + { -0.263362, 0.074220, 10.121481, 0 }, + { -0.259771, 0.068235, 10.135846, 0 }, + { -0.250194, 0.070629, 10.138240, 0 }, + { -0.258574, 0.077812, 10.132255, 0 }, + { -0.252588, 0.067038, 10.135846, 0 }, + { -0.251391, 0.064643, 10.128663, 0 }, + { -0.243011, 0.082600, 10.134649, 0 }, + { -0.238223, 0.084994, 10.144226, 0 }, + { -0.260968, 0.084994, 10.123875, 0 }, + { -0.254982, 0.075417, 10.137043, 0 }, + { -0.259771, 0.075417, 10.111904, 0 }, + { -0.251391, 0.084994, 10.143028, 0 }, + { -0.245406, 0.079009, 10.117889, 0 }, + { -0.252588, 0.074220, 10.149014, 0 }, + { -0.254982, 0.062249, 10.132255, 0 }, + { -0.241814, 0.062249, 10.116693, 0 }, + { -0.247800, 0.074220, 10.151408, 0 }, + { -0.240617, 0.081403, 10.115496, 0 }, + { -0.247800, 0.067038, 10.139438, 0 }, + { -0.250194, 0.079009, 10.126269, 0 }, + { -0.237026, 0.087388, 10.150211, 0 }, + { -0.238223, 0.073023, 10.134649, 0 }, + { -0.241814, 0.080206, 10.140635, 0 }, + { -0.248997, 0.075417, 10.122678, 0 }, + { -0.254982, 0.081403, 10.123875, 0 }, + { -0.257377, 0.067038, 10.138240, 0 }, + { -0.247800, 0.076614, 10.128663, 0 }, + { -0.256179, 0.076614, 10.145423, 0 }, + { -0.241814, 0.080206, 10.132255, 0 }, + { -0.238223, 0.067038, 10.137043, 0 }, + { -0.257377, 0.064643, 10.119086, 0 }, + { -0.243011, 0.081403, 10.129861, 0 }, + { -0.248997, 0.081403, 10.115496, 0 }, + { -0.258574, 0.062249, 10.133451, 0 }, + { -0.247800, 0.070629, 10.119086, 0 }, + { -0.252588, 0.074220, 10.129861, 0 }, + { -0.246603, 0.070629, 10.133451, 0 }, + { -0.245406, 0.073023, 10.102327, 0 }, + { -0.252588, 0.080206, 10.139438, 0 }, + { -0.247800, 0.068235, 10.113101, 0 }, + { -0.254982, 0.074220, 10.126269, 0 }, + { -0.251391, 0.079009, 10.120284, 0 }, + { -0.251391, 0.089783, 10.137043, 0 }, + { -0.252588, 0.065841, 10.127466, 0 }, + { -0.251391, 0.068235, 10.120284, 0 }, + { -0.257377, 0.067038, 10.127466, 0 }, + { -0.241814, 0.081403, 10.128663, 0 }, + { -0.241814, 0.081403, 10.135846, 0 }, + { -0.247800, 0.071826, 10.135846, 0 }, + { -0.250194, 0.070629, 10.138240, 0 }, + { -0.252588, 0.084994, 10.131058, 0 }, + { -0.245406, 0.083797, 10.139438, 0 }, + { -0.244208, 0.075417, 10.123875, 0 }, + { -0.259771, 0.077812, 10.137043, 0 }, + { -0.248997, 0.071826, 10.123875, 0 }, + { -0.246603, 0.086191, 10.152605, 0 }, + { -0.241814, 0.069432, 10.132255, 0 }, + { -0.243011, 0.064643, 10.129861, 0 }, + { -0.245406, 0.073023, 10.129861, 0 }, + { -0.251391, 0.076614, 10.116693, 0 }, + { -0.264559, 0.068235, 10.139438, 0 }, + { -0.247800, 0.073023, 10.105919, 0 }, + { -0.244208, 0.077812, 10.145423, 0 }, + { -0.250194, 0.077812, 10.137043, 0 }, + { -0.252588, 0.064643, 10.126269, 0 }, + { -0.252588, 0.079009, 10.125072, 0 }, + { -0.239420, 0.084994, 10.126269, 0 }, + { -0.246603, 0.067038, 10.137043, 0 }, + { -0.252588, 0.077812, 10.114298, 0 }, + { -0.266953, 0.062249, 10.131058, 0 }, + { -0.264559, 0.076614, 10.114298, 0 }, + { -0.250194, 0.071826, 10.135846, 0 }, + { -0.250194, 0.087388, 10.134649, 0 }, + { -0.246603, 0.082600, 10.147817, 0 }, + { -0.245406, 0.065841, 10.131058, 0 }, + { -0.258574, 0.070629, 10.139438, 0 }, + { -0.251391, 0.081403, 10.111904, 0 }, + { -0.246603, 0.080206, 10.132255, 0 }, + { -0.235829, 0.074220, 10.117889, 0 }, + { -0.243011, 0.075417, 10.123875, 0 }, + { -0.241814, 0.065841, 10.139438, 0 }, + { -0.241814, 0.077812, 10.119086, 0 }, + { -0.247800, 0.084994, 10.153803, 0 }, + { -0.266953, 0.081403, 10.116693, 0 }, + { -0.243011, 0.083797, 10.137043, 0 }, + { -0.257377, 0.074220, 10.109509, 0 }, + { -0.252588, 0.074220, 10.126269, 0 }, + { -0.247800, 0.076614, 10.127466, 0 }, + { -0.243011, 0.068235, 10.111904, 0 }, + { -0.259771, 0.077812, 10.132255, 0 }, + { -0.253785, 0.092177, 10.103524, 0 }, + { -0.243011, 0.086191, 10.123875, 0 }, + { -0.232237, 0.069432, 10.134649, 0 }, + { -0.233435, 0.076614, 10.129861, 0 }, + { -0.257377, 0.068235, 10.114298, 0 }, + { -0.250194, 0.074220, 10.127466, 0 }, + { -0.245406, 0.077812, 10.131058, 0 }, + { -0.251391, 0.077812, 10.123875, 0 }, + { -0.245406, 0.074220, 10.123875, 0 }, + { -0.245406, 0.069432, 10.122678, 0 }, + { -0.254982, 0.071826, 10.119086, 0 }, + { -0.257377, 0.064643, 10.116693, 0 }, + { -0.256179, 0.079009, 10.128663, 0 }, + { -0.241814, 0.062249, 10.098736, 0 }, + { -0.248997, 0.067038, 10.144226, 0 }, + { -0.237026, 0.083797, 10.145423, 0 }, + { -0.253785, 0.076614, 10.120284, 0 }, + { -0.251391, 0.065841, 10.113101, 0 }, + { -0.248997, 0.067038, 10.104721, 0 }, + { -0.244208, 0.073023, 10.134649, 0 }, + { -0.259771, 0.069432, 10.134649, 0 }, + { -0.244208, 0.084994, 10.141831, 0 }, + { -0.257377, 0.076614, 10.126269, 0 }, + { -0.246603, 0.073023, 10.137043, 0 }, + { -0.247800, 0.073023, 10.111904, 0 }, + { -0.243011, 0.073023, 10.144226, 0 }, + { -0.251391, 0.080206, 10.129861, 0 }, + { -0.244208, 0.076614, 10.126269, 0 }, + { -0.246603, 0.069432, 10.135846, 0 }, + { -0.250194, 0.073023, 10.131058, 0 }, + { -0.250194, 0.069432, 10.122678, 0 }, + { -0.238223, 0.073023, 10.133451, 0 }, + { -0.229843, 0.063446, 10.121481, 0 }, + { -0.235829, 0.084994, 10.115496, 0 }, + { -0.243011, 0.077812, 10.122678, 0 }, + { -0.238223, 0.067038, 10.116693, 0 }, + { -0.245406, 0.069432, 10.137043, 0 }, + { -0.258574, 0.081403, 10.122678, 0 }, + { -0.239420, 0.083797, 10.149014, 0 }, + { -0.240617, 0.075417, 10.123875, 0 }, + { -0.251391, 0.067038, 10.153803, 0 }, + { -0.240617, 0.075417, 10.145423, 0 }, + { -0.231040, 0.083797, 10.129861, 0 }, + { -0.247800, 0.090980, 10.155000, 0 }, + { -0.247800, 0.077812, 10.125072, 0 }, + { -0.253785, 0.084994, 10.131058, 0 }, + { -0.257377, 0.073023, 10.108313, 0 }, + { -0.248997, 0.080206, 10.123875, 0 }, + { -0.244208, 0.073023, 10.113101, 0 }, + { -0.237026, 0.080206, 10.121481, 0 }, + { -0.248997, 0.055067, 10.127466, 0 }, + { -0.256179, 0.073023, 10.137043, 0 }, + { -0.260968, 0.081403, 10.131058, 0 }, + { -0.251391, 0.069432, 10.125072, 0 }, + { -0.252588, 0.074220, 10.115496, 0 }, + { -0.250194, 0.086191, 10.122678, 0 }, + { -0.235829, 0.076614, 10.119086, 0 }, + { -0.258574, 0.079009, 10.127466, 0 }, + { -0.247800, 0.076614, 10.139438, 0 }, + { -0.247800, 0.079009, 10.126269, 0 }, + { -0.237026, 0.088585, 10.134649, 0 }, + { -0.240617, 0.073023, 10.120284, 0 }, + { -0.244208, 0.073023, 10.125072, 0 }, + { -0.243011, 0.076614, 10.115496, 0 }, + { -0.238223, 0.080206, 10.122678, 0 }, + { -0.239420, 0.067038, 10.122678, 0 }, + { -0.253785, 0.081403, 10.119086, 0 }, + { -0.246603, 0.080206, 10.125072, 0 }, + { -0.251391, 0.082600, 10.126269, 0 }, + { -0.238223, 0.073023, 10.132255, 0 }, + { -0.252588, 0.075417, 10.133451, 0 }, + { -0.254982, 0.061052, 10.140635, 0 }, + { -0.253785, 0.065841, 10.117889, 0 }, + { -0.235829, 0.071826, 10.143028, 0 }, + { -0.245406, 0.083797, 10.122678, 0 }, + { -0.256179, 0.088585, 10.129861, 0 }, + { -0.259771, 0.077812, 10.121481, 0 }, + { -0.238223, 0.067038, 10.125072, 0 }, + { -0.247800, 0.073023, 10.140635, 0 }, + { -0.248997, 0.073023, 10.111904, 0 }, + { -0.245406, 0.075417, 10.145423, 0 }, + { -0.268150, 0.075417, 10.102327, 0 }, + { -0.246603, 0.080206, 10.129861, 0 }, + { -0.251391, 0.080206, 10.126269, 0 }, + { -0.251391, 0.071826, 10.134649, 0 }, + { -0.262165, 0.076614, 10.143028, 0 }, + { -0.247800, 0.070629, 10.121481, 0 }, + { -0.238223, 0.083797, 10.135846, 0 }, + { -0.251391, 0.069432, 10.111904, 0 }, + { -0.256179, 0.082600, 10.139438, 0 }, + { -0.262165, 0.083797, 10.128663, 0 }, + { -0.251391, 0.079009, 10.122678, 0 }, + { -0.245406, 0.077812, 10.125072, 0 }, + { -0.239420, 0.074220, 10.125072, 0 }, + { -0.258574, 0.076614, 10.127466, 0 }, + { -0.256179, 0.088585, 10.126269, 0 }, + { -0.246603, 0.080206, 10.111904, 0 }, + { -0.241814, 0.084994, 10.133451, 0 }, + { -0.235829, 0.079009, 10.141831, 0 }, + { -0.263362, 0.073023, 10.138240, 0 }, + { -0.251391, 0.069432, 10.134649, 0 }, + { -0.245406, 0.069432, 10.127466, 0 }, + { -0.250194, 0.074220, 10.133451, 0 }, + { -0.251391, 0.068235, 10.131058, 0 }, + { -0.254982, 0.070629, 10.128663, 0 }, + { -0.240617, 0.083797, 10.111904, 0 }, + { -0.245406, 0.075417, 10.122678, 0 }, + { -0.245406, 0.084994, 10.119086, 0 }, + { -0.248997, 0.079009, 10.098736, 0 }, + { -0.240617, 0.070629, 10.127466, 0 }, + { -0.244208, 0.079009, 10.145423, 0 }, + { -0.264559, 0.079009, 10.120284, 0 }, + { -0.244208, 0.077812, 10.119086, 0 }, + { -0.237026, 0.080206, 10.107116, 0 }, + { -0.235829, 0.086191, 10.128663, 0 }, + { -0.245406, 0.081403, 10.133451, 0 }, + { -0.247800, 0.077812, 10.138240, 0 }, + { -0.251391, 0.080206, 10.125072, 0 }, + { -0.257377, 0.068235, 10.147817, 0 }, + { -0.263362, 0.076614, 10.121481, 0 }, + { -0.268150, 0.073023, 10.116693, 0 }, + { -0.247800, 0.071826, 10.122678, 0 }, + { -0.260968, 0.073023, 10.134649, 0 }, + { -0.254982, 0.074220, 10.116693, 0 }, + { -0.246603, 0.086191, 10.131058, 0 }, + { -0.248997, 0.079009, 10.125072, 0 }, + { -0.252588, 0.067038, 10.132255, 0 }, + { -0.254982, 0.063446, 10.123875, 0 }, + { -0.256179, 0.067038, 10.116693, 0 }, + { -0.259771, 0.083797, 10.125072, 0 }, + { -0.264559, 0.069432, 10.131058, 0 }, + { -0.243011, 0.074220, 10.143028, 0 }, + { -0.254982, 0.081403, 10.128663, 0 }, + { -0.253785, 0.065841, 10.143028, 0 }, + { -0.260968, 0.075417, 10.131058, 0 }, + { -0.265756, 0.090980, 10.128663, 0 }, + { -0.244208, 0.088585, 10.146620, 0 }, + { -0.246603, 0.082600, 10.114298, 0 }, + { -0.256179, 0.077812, 10.133451, 0 }, + { -0.250194, 0.064643, 10.117889, 0 }, + { -0.254982, 0.075417, 10.117889, 0 }, + { -0.266953, 0.065841, 10.113101, 0 }, + { -0.253785, 0.073023, 10.128663, 0 }, + { -0.259771, 0.082600, 10.138240, 0 }, + { -0.247800, 0.071826, 10.145423, 0 }, + { -0.243011, 0.074220, 10.122678, 0 }, + { -0.257377, 0.083797, 10.140635, 0 }, + { -0.232237, 0.087388, 10.117889, 0 }, + { -0.244208, 0.076614, 10.125072, 0 }, + { -0.248997, 0.067038, 10.128663, 0 }, + { -0.256179, 0.062249, 10.115496, 0 }, + { -0.263362, 0.071826, 10.141831, 0 }, + { -0.246603, 0.075417, 10.107116, 0 }, + { -0.244208, 0.081403, 10.137043, 0 }, + { -0.254982, 0.083797, 10.123875, 0 }, + { -0.243011, 0.092177, 10.132255, 0 }, + { -0.260968, 0.077812, 10.131058, 0 }, + { -0.256179, 0.073023, 10.119086, 0 }, + { -0.239420, 0.082600, 10.132255, 0 }, + { -0.251391, 0.073023, 10.117889, 0 }, + { -0.254982, 0.071826, 10.134649, 0 }, + { -0.259771, 0.080206, 10.120284, 0 }, + { -0.246603, 0.069432, 10.133451, 0 }, + { -0.250194, 0.061052, 10.126269, 0 }, + { -0.256179, 0.063446, 10.109509, 0 }, + { -0.251391, 0.087388, 10.120284, 0 }, + { -0.246603, 0.069432, 10.132255, 0 }, + { -0.244208, 0.077812, 10.133451, 0 }, + { -0.257377, 0.069432, 10.126269, 0 }, + { -0.247800, 0.075417, 10.133451, 0 }, + { -0.246603, 0.071826, 10.117889, 0 }, + { -0.245406, 0.093374, 10.135846, 0 }, + { -0.254982, 0.082600, 10.105919, 0 }, + { -0.247800, 0.076614, 10.143028, 0 }, + { -0.246603, 0.076614, 10.126269, 0 }, + { -0.243011, 0.067038, 10.127466, 0 }, + { -0.253785, 0.064643, 10.119086, 0 }, + { -0.248997, 0.079009, 10.127466, 0 }, + { -0.248997, 0.080206, 10.141831, 0 }, + { -0.244208, 0.074220, 10.133451, 0 }, + { -0.240617, 0.079009, 10.135846, 0 }, + { -0.232237, 0.075417, 10.115496, 0 }, + { -0.254982, 0.082600, 10.139438, 0 }, + { -0.258574, 0.077812, 10.119086, 0 }, + { -0.246603, 0.076614, 10.109509, 0 }, + { -0.248997, 0.080206, 10.125072, 0 }, + { -0.256179, 0.077812, 10.128663, 0 }, + { -0.235829, 0.076614, 10.126269, 0 }, + { -0.253785, 0.076614, 10.128663, 0 }, + { -0.254982, 0.075417, 10.147817, 0 }, + { -0.246603, 0.079009, 10.145423, 0 }, + { -0.243011, 0.081403, 10.146620, 0 }, + { -0.237026, 0.075417, 10.134649, 0 }, + { -0.258574, 0.077812, 10.149014, 0 }, + { -0.262165, 0.079009, 10.141831, 0 }, + { -0.245406, 0.069432, 10.140635, 0 }, + { -0.240617, 0.074220, 10.120284, 0 }, + { -0.252588, 0.080206, 10.143028, 0 }, + { -0.254982, 0.084994, 10.135846, 0 }, + { -0.248997, 0.067038, 10.131058, 0 }, + { -0.234632, 0.070629, 10.133451, 0 }, + { -0.246603, 0.067038, 10.132255, 0 }, + { -0.246603, 0.070629, 10.143028, 0 }, + { -0.245406, 0.079009, 10.135846, 0 }, + { -0.253785, 0.077812, 10.144226, 0 }, + { -0.248997, 0.076614, 10.127466, 0 }, + { -0.227449, 0.093374, 10.119086, 0 }, + { -0.257377, 0.073023, 10.125072, 0 }, + { -0.254982, 0.057461, 10.133451, 0 }, + { -0.247800, 0.069432, 10.122678, 0 }, + { -0.252588, 0.075417, 10.125072, 0 }, + { -0.262165, 0.088585, 10.125072, 0 }, + { -0.253785, 0.080206, 10.127466, 0 }, + { -0.252588, 0.070629, 10.137043, 0 }, + { -0.254982, 0.068235, 10.113101, 0 }, + { -0.244208, 0.076614, 10.132255, 0 }, + { -0.244208, 0.074220, 10.129861, 0 }, + { -0.244208, 0.073023, 10.141831, 0 }, + { -0.239420, 0.080206, 10.108313, 0 }, + { -0.241814, 0.087388, 10.122678, 0 }, + { -0.253785, 0.093374, 10.122678, 0 }, + { -0.252588, 0.070629, 10.133451, 0 }, + { -0.244208, 0.073023, 10.147817, 0 }, + { -0.245406, 0.076614, 10.122678, 0 }, + { -0.254982, 0.087388, 10.132255, 0 }, + { -0.241814, 0.065841, 10.125072, 0 }, + { -0.231040, 0.068235, 10.123875, 0 }, + { -0.238223, 0.081403, 10.117889, 0 }, + { -0.241814, 0.083797, 10.139438, 0 }, + { -0.240617, 0.045490, 10.119086, 0 }, + { -0.262165, 0.069432, 10.125072, 0 }, + { -0.259771, 0.081403, 10.126269, 0 }, + { -0.248997, 0.068235, 10.129861, 0 }, + { -0.238223, 0.071826, 10.131058, 0 }, + { -0.237026, 0.087388, 10.117889, 0 }, + { -0.253785, 0.076614, 10.123875, 0 }, + { -0.260968, 0.077812, 10.120284, 0 }, + { -0.246603, 0.073023, 10.126269, 0 }, + { -0.256179, 0.082600, 10.119086, 0 }, + { -0.252588, 0.067038, 10.139438, 0 }, + { -0.260968, 0.073023, 10.127466, 0 }, + { -0.235829, 0.086191, 10.121481, 0 }, + { -0.244208, 0.088585, 10.131058, 0 }, + { -0.245406, 0.073023, 10.143028, 0 }, + { -0.243011, 0.079009, 10.139438, 0 }, + { -0.253785, 0.077812, 10.120284, 0 }, + { -0.252588, 0.068235, 10.123875, 0 }, + { -0.246603, 0.069432, 10.132255, 0 }, + { -0.237026, 0.070629, 10.139438, 0 }, + { -0.244208, 0.068235, 10.120284, 0 }, + { -0.247800, 0.079009, 10.134649, 0 }, + { -0.256179, 0.084994, 10.150211, 0 }, + { -0.246603, 0.070629, 10.126269, 0 }, + { -0.246603, 0.065841, 10.131058, 0 }, + { -0.262165, 0.068235, 10.126269, 0 }, + { -0.244208, 0.069432, 10.125072, 0 }, + { -0.245406, 0.081403, 10.114298, 0 }, + { -0.257377, 0.070629, 10.133451, 0 }, + { -0.247800, 0.079009, 10.109509, 0 }, + { -0.245406, 0.071826, 10.125072, 0 }, + { -0.237026, 0.069432, 10.139438, 0 }, + { -0.244208, 0.081403, 10.145423, 0 }, + { -0.246603, 0.075417, 10.129861, 0 }, + { -0.262165, 0.082600, 10.128663, 0 }, + { -0.246603, 0.083797, 10.147817, 0 }, + { -0.243011, 0.079009, 10.128663, 0 }, + { -0.251391, 0.069432, 10.133451, 0 }, + { -0.253785, 0.070629, 10.122678, 0 }, + { -0.248997, 0.075417, 10.139438, 0 }, + { -0.256179, 0.080206, 10.104721, 0 }, + { -0.263362, 0.081403, 10.127466, 0 }, + { -0.247800, 0.068235, 10.140635, 0 }, + { -0.251391, 0.062249, 10.138240, 0 }, + { -0.245406, 0.087388, 10.133451, 0 }, + { -0.254982, 0.075417, 10.122678, 0 }, + { -0.240617, 0.071826, 10.135846, 0 }, + { -0.258574, 0.068235, 10.114298, 0 }, + { -0.250194, 0.077812, 10.137043, 0 }, + { -0.238223, 0.070629, 10.121481, 0 }, + { -0.244208, 0.080206, 10.126269, 0 }, + { -0.246603, 0.071826, 10.119086, 0 }, + { -0.258574, 0.068235, 10.147817, 0 }, + { -0.252588, 0.058658, 10.121481, 0 }, + { -0.258574, 0.073023, 10.122678, 0 }, + { -0.244208, 0.075417, 10.144226, 0 }, + { -0.241814, 0.075417, 10.120284, 0 }, + { -0.257377, 0.063446, 10.129861, 0 }, + { -0.260968, 0.075417, 10.091554, 0 }, + { -0.260968, 0.086191, 10.149014, 0 }, + { -0.243011, 0.084994, 10.095144, 0 }, + { -0.246603, 0.081403, 10.141831, 0 }, + { -0.243011, 0.068235, 10.138240, 0 }, + { -0.252588, 0.084994, 10.131058, 0 }, + { -0.257377, 0.077812, 10.141831, 0 }, + { -0.247800, 0.071826, 10.113101, 0 }, + { -0.258574, 0.073023, 10.151408, 0 }, + { -0.256179, 0.067038, 10.119086, 0 }, + { -0.264559, 0.070629, 10.131058, 0 }, + { -0.266953, 0.079009, 10.107116, 0 }, + { -0.245406, 0.077812, 10.137043, 0 }, + { -0.256179, 0.076614, 10.128663, 0 }, + { -0.252588, 0.068235, 10.135846, 0 }, + { -0.257377, 0.069432, 10.133451, 0 }, + { -0.258574, 0.062249, 10.133451, 0 }, + { -0.268150, 0.092177, 10.128663, 0 }, + { -0.257377, 0.076614, 10.139438, 0 }, + { -0.240617, 0.076614, 10.115496, 0 }, + { -0.248997, 0.075417, 10.129861, 0 }, + { -0.251391, 0.075417, 10.135846, 0 }, + { -0.263362, 0.062249, 10.092751, 0 }, + { -0.245406, 0.079009, 10.135846, 0 }, + { -0.248997, 0.077812, 10.114298, 0 }, + { -0.245406, 0.090980, 10.143028, 0 }, + { -0.246603, 0.081403, 10.125072, 0 }, + { -0.243011, 0.059855, 10.127466, 0 }, + { -0.248997, 0.068235, 10.145423, 0 }, + { -0.245406, 0.070629, 10.132255, 0 }, + { -0.240617, 0.068235, 10.139438, 0 }, + { -0.241814, 0.069432, 10.115496, 0 }, + { -0.250194, 0.082600, 10.137043, 0 }, + { -0.250194, 0.073023, 10.128663, 0 }, + { -0.241814, 0.086191, 10.144226, 0 }, + { -0.254982, 0.070629, 10.121481, 0 }, + { -0.244208, 0.082600, 10.131058, 0 }, + { -0.244208, 0.086191, 10.126269, 0 }, + { -0.251391, 0.086191, 10.138240, 0 }, + { -0.256179, 0.073023, 10.123875, 0 }, + { -0.247800, 0.080206, 10.127466, 0 }, + { -0.239420, 0.087388, 10.145423, 0 }, + { -0.247800, 0.056264, 10.145423, 0 }, + { -0.239420, 0.063446, 10.143028, 0 }, + { -0.259771, 0.067038, 10.111904, 0 }, + { -0.245406, 0.079009, 10.135846, 0 }, + { -0.254982, 0.074220, 10.121481, 0 }, + { -0.257377, 0.070629, 10.141831, 0 }, + { -0.243011, 0.068235, 10.141831, 0 }, + { -0.254982, 0.071826, 10.140635, 0 }, + { -0.231040, 0.068235, 10.126269, 0 }, + { -0.240617, 0.074220, 10.119086, 0 }, + { -0.244208, 0.070629, 10.123875, 0 }, + { -0.248997, 0.067038, 10.132255, 0 }, + { -0.252588, 0.071826, 10.135846, 0 }, + { -0.250194, 0.074220, 10.108313, 0 }, + { -0.252588, 0.071826, 10.137043, 0 }, + { -0.253785, 0.074220, 10.117889, 0 }, + { -0.246603, 0.069432, 10.123875, 0 }, + { -0.250194, 0.065841, 10.132255, 0 }, + { -0.240617, 0.062249, 10.153803, 0 }, + { -0.250194, 0.069432, 10.122678, 0 }, + { -0.248997, 0.073023, 10.114298, 0 }, + { -0.251391, 0.075417, 10.131058, 0 }, + { -0.239420, 0.065841, 10.134649, 0 }, + { -0.244208, 0.077812, 10.146620, 0 }, + { -0.253785, 0.089783, 10.102327, 0 }, + { -0.248997, 0.073023, 10.123875, 0 }, + { -0.252588, 0.074220, 10.109509, 0 }, + { -0.248997, 0.086191, 10.144226, 0 }, + { -0.240617, 0.073023, 10.135846, 0 }, + { -0.245406, 0.063446, 10.111904, 0 }, + { -0.253785, 0.057461, 10.120284, 0 }, + { -0.257377, 0.074220, 10.120284, 0 }, + { -0.262165, 0.070629, 10.153803, 0 }, + { -0.260968, 0.071826, 10.128663, 0 }, + { -0.251391, 0.070629, 10.138240, 0 }, + { -0.246603, 0.075417, 10.119086, 0 }, + { -0.247800, 0.069432, 10.120284, 0 }, + { -0.268150, 0.074220, 10.134649, 0 }, + { -0.241814, 0.082600, 10.143028, 0 }, + { -0.245406, 0.082600, 10.143028, 0 }, + { -0.259771, 0.074220, 10.125072, 0 }, + { -0.263362, 0.069432, 10.132255, 0 }, + { -0.248997, 0.076614, 10.111904, 0 }, + { -0.254982, 0.071826, 10.128663, 0 }, + { -0.238223, 0.079009, 10.101130, 0 }, + { -0.246603, 0.075417, 10.149014, 0 }, + { -0.262165, 0.061052, 10.116693, 0 }, + { -0.245406, 0.071826, 10.135846, 0 }, + { -0.241814, 0.090980, 10.120284, 0 }, + { -0.247800, 0.082600, 10.133451, 0 }, + { -0.260968, 0.064643, 10.149014, 0 }, + { -0.241814, 0.069432, 10.127466, 0 }, + { -0.246603, 0.073023, 10.128663, 0 }, + { -0.259771, 0.068235, 10.083174, 0 }, + { -0.254982, 0.086191, 10.129861, 0 }, + { -0.251391, 0.070629, 10.111904, 0 }, + { -0.250194, 0.064643, 10.128663, 0 }, + { -0.244208, 0.080206, 10.114298, 0 }, + { -0.234632, 0.075417, 10.128663, 0 }, + { -0.247800, 0.080206, 10.132255, 0 }, + { -0.247800, 0.071826, 10.135846, 0 }, + { -0.240617, 0.063446, 10.133451, 0 }, + { -0.253785, 0.070629, 10.128663, 0 }, + { -0.251391, 0.075417, 10.131058, 0 }, + { -0.252588, 0.074220, 10.116693, 0 }, + { -0.248997, 0.071826, 10.129861, 0 }, + { -0.251391, 0.087388, 10.108313, 0 }, + { -0.248997, 0.083797, 10.137043, 0 }, + { -0.257377, 0.068235, 10.132255, 0 }, + { -0.256179, 0.065841, 10.141831, 0 }, + { -0.239420, 0.076614, 10.132255, 0 }, + { -0.251391, 0.073023, 10.127466, 0 }, + { -0.252588, 0.073023, 10.138240, 0 }, + { -0.253785, 0.070629, 10.119086, 0 }, + { -0.247800, 0.069432, 10.119086, 0 }, + { -0.246603, 0.067038, 10.123875, 0 }, + { -0.246603, 0.077812, 10.146620, 0 }, + { -0.246603, 0.083797, 10.123875, 0 }, + { -0.246603, 0.083797, 10.143028, 0 }, + { -0.241814, 0.071826, 10.110707, 0 }, + { -0.248997, 0.077812, 10.134649, 0 }, + { -0.251391, 0.074220, 10.143028, 0 }, + { -0.243011, 0.082600, 10.133451, 0 }, + { -0.251391, 0.079009, 10.111904, 0 }, + { -0.251391, 0.081403, 10.122678, 0 }, + { -0.247800, 0.080206, 10.144226, 0 }, + { -0.247800, 0.092177, 10.114298, 0 }, + { -0.244208, 0.073023, 10.134649, 0 }, + { -0.245406, 0.081403, 10.126269, 0 }, + { -0.250194, 0.073023, 10.144226, 0 }, + { -0.243011, 0.079009, 10.133451, 0 }, + { -0.260968, 0.077812, 10.122678, 0 }, + { -0.252588, 0.090980, 10.122678, 0 }, + { -0.268150, 0.073023, 10.128663, 0 }, + { -0.256179, 0.075417, 10.123875, 0 }, + { -0.248997, 0.063446, 10.104721, 0 }, + { -0.245406, 0.090980, 10.128663, 0 }, + { -0.253785, 0.087388, 10.115496, 0 }, + { -0.239420, 0.073023, 10.138240, 0 }, + { -0.238223, 0.059855, 10.119086, 0 }, + { -0.248997, 0.070629, 10.125072, 0 }, + { -0.250194, 0.081403, 10.131058, 0 }, + { -0.248997, 0.093374, 10.132255, 0 }, + { -0.253785, 0.092177, 10.128663, 0 }, + { -0.251391, 0.071826, 10.134649, 0 }, + { -0.233435, 0.074220, 10.129861, 0 }, + { -0.241814, 0.079009, 10.103524, 0 }, + { -0.253785, 0.070629, 10.153803, 0 }, + { -0.260968, 0.069432, 10.144226, 0 }, + { -0.250194, 0.065841, 10.123875, 0 }, + { -0.262165, 0.092177, 10.125072, 0 }, + { -0.252588, 0.088585, 10.151408, 0 }, + { -0.253785, 0.087388, 10.132255, 0 }, + { -0.244208, 0.062249, 10.137043, 0 }, + { -0.256179, 0.065841, 10.110707, 0 }, + { -0.244208, 0.075417, 10.117889, 0 }, + { -0.240617, 0.082600, 10.132255, 0 }, + { -0.248997, 0.074220, 10.115496, 0 }, + { -0.250194, 0.079009, 10.141831, 0 }, + { -0.246603, 0.077812, 10.119086, 0 }, + { -0.252588, 0.074220, 10.117889, 0 }, + { -0.257377, 0.075417, 10.120284, 0 }, + { -0.250194, 0.077812, 10.117889, 0 }, + { -0.239420, 0.081403, 10.143028, 0 }, + { -0.237026, 0.076614, 10.137043, 0 }, + { -0.240617, 0.077812, 10.149014, 0 }, + { -0.270545, 0.071826, 10.131058, 0 }, + { -0.262165, 0.068235, 10.122678, 0 }, + { -0.259771, 0.067038, 10.114298, 0 }, + { -0.246603, 0.082600, 10.121481, 0 }, + { -0.254982, 0.076614, 10.127466, 0 }, + { -0.244208, 0.063446, 10.122678, 0 }, + { -0.246603, 0.074220, 10.121481, 0 }, + { -0.253785, 0.086191, 10.127466, 0 }, + { -0.253785, 0.079009, 10.131058, 0 }, + { -0.245406, 0.071826, 10.132255, 0 }, + { -0.248997, 0.074220, 10.132255, 0 }, + { -0.260968, 0.055067, 10.121481, 0 }, + { -0.243011, 0.070629, 10.122678, 0 }, + { -0.252588, 0.070629, 10.132255, 0 }, + { -0.243011, 0.077812, 10.143028, 0 }, + { -0.246603, 0.077812, 10.132255, 0 }, + { -0.253785, 0.082600, 10.131058, 0 }, + { -0.256179, 0.068235, 10.137043, 0 }, + { -0.243011, 0.088585, 10.121481, 0 }, + { -0.239420, 0.065841, 10.133451, 0 }, + { -0.252588, 0.063446, 10.122678, 0 }, + { -0.252588, 0.082600, 10.141831, 0 }, + { -0.238223, 0.083797, 10.122678, 0 }, + { -0.251391, 0.076614, 10.140635, 0 }, + { -0.265756, 0.081403, 10.135846, 0 }, + { -0.252588, 0.076614, 10.141831, 0 }, + { -0.246603, 0.079009, 10.131058, 0 }, + { -0.250194, 0.077812, 10.126269, 0 }, + { -0.240617, 0.079009, 10.146620, 0 }, + { -0.247800, 0.089783, 10.132255, 0 }, + { -0.259771, 0.089783, 10.111904, 0 }, + { -0.266953, 0.084994, 10.141831, 0 }, + { -0.244208, 0.087388, 10.147817, 0 }, + { -0.235829, 0.067038, 10.127466, 0 }, + { -0.245406, 0.069432, 10.129861, 0 }, + { -0.250194, 0.083797, 10.108313, 0 }, + { -0.240617, 0.084994, 10.146620, 0 }, + { -0.256179, 0.077812, 10.121481, 0 }, + { -0.250194, 0.076614, 10.151408, 0 }, + { -0.248997, 0.073023, 10.128663, 0 }, + { -0.252588, 0.068235, 10.140635, 0 }, + { -0.252588, 0.074220, 10.147817, 0 }, + { -0.253785, 0.083797, 10.139438, 0 }, + { -0.243011, 0.069432, 10.114298, 0 }, + { -0.235829, 0.059855, 10.122678, 0 }, + { -0.253785, 0.076614, 10.145423, 0 }, + { -0.245406, 0.077812, 10.115496, 0 }, + { -0.252588, 0.065841, 10.139438, 0 }, + { -0.248997, 0.092177, 10.132255, 0 }, + { -0.256179, 0.088585, 10.150211, 0 }, + { -0.250194, 0.082600, 10.134649, 0 }, + { -0.244208, 0.069432, 10.137043, 0 }, + { -0.254982, 0.076614, 10.127466, 0 }, + { -0.253785, 0.063446, 10.135846, 0 }, + { -0.258574, 0.080206, 10.145423, 0 }, + { -0.232237, 0.074220, 10.126269, 0 }, + { -0.241814, 0.080206, 10.131058, 0 }, + { -0.240617, 0.075417, 10.116693, 0 }, + { -0.253785, 0.068235, 10.132255, 0 }, + { -0.241814, 0.083797, 10.139438, 0 }, + { -0.245406, 0.084994, 10.129861, 0 }, + { -0.245406, 0.079009, 10.165773, 0 }, + { -0.238223, 0.079009, 10.101130, 0 }, + { -0.247800, 0.081403, 10.138240, 0 }, + { -0.244208, 0.070629, 10.126269, 0 }, + { -0.253785, 0.082600, 10.149014, 0 }, + { -0.235829, 0.079009, 10.115496, 0 }, + { -0.239420, 0.070629, 10.114298, 0 }, + { -0.251391, 0.086191, 10.128663, 0 }, + { -0.241814, 0.075417, 10.119086, 0 }, + { -0.241814, 0.074220, 10.165773, 0 }, + { -0.233435, 0.075417, 10.101130, 0 }, + { -0.254982, 0.087388, 10.135846, 0 }, + { -0.232237, 0.074220, 10.129861, 0 }, + { -0.233435, 0.076614, 10.123875, 0 }, + { -0.258574, 0.093374, 10.137043, 0 }, + { -0.243011, 0.074220, 10.137043, 0 }, + { -0.244208, 0.083797, 10.145423, 0 }, + { -0.252588, 0.087388, 10.137043, 0 }, + { -0.251391, 0.077812, 10.120284, 0 }, + { -0.235829, 0.067038, 10.117889, 0 }, + { -0.240617, 0.075417, 10.125072, 0 }, + { -0.253785, 0.086191, 10.127466, 0 }, + { -0.256179, 0.080206, 10.126269, 0 }, + { -0.254982, 0.071826, 10.132255, 0 }, + { -0.235829, 0.074220, 10.128663, 0 }, + { -0.252588, 0.079009, 10.117889, 0 }, + { -0.245406, 0.081403, 10.123875, 0 }, + { -0.246603, 0.073023, 10.127466, 0 }, + { -0.252588, 0.063446, 10.159788, 0 }, + { -0.247800, 0.079009, 10.147817, 0 }, + { -0.258574, 0.079009, 10.131058, 0 }, + { -0.269348, 0.075417, 10.134649, 0 }, + { -0.248997, 0.083797, 10.107116, 0 }, + { -0.244208, 0.081403, 10.139438, 0 }, + { -0.259771, 0.070629, 10.133451, 0 }, + { -0.257377, 0.063446, 10.128663, 0 }, + { -0.254982, 0.071826, 10.121481, 0 }, + { -0.252588, 0.088585, 10.137043, 0 }, + { -0.251391, 0.083797, 10.135846, 0 }, + { -0.253785, 0.086191, 10.134649, 0 }, + { -0.252588, 0.073023, 10.115496, 0 }, + { -0.254982, 0.075417, 10.145423, 0 }, + { -0.250194, 0.076614, 10.137043, 0 }, + { -0.248997, 0.070629, 10.135846, 0 }, + { -0.259771, 0.073023, 10.137043, 0 }, + { -0.245406, 0.088585, 10.120284, 0 }, + { -0.254982, 0.074220, 10.151408, 0 }, + { -0.252588, 0.074220, 10.103524, 0 }, + { -0.258574, 0.070629, 10.146620, 0 }, + { -0.251391, 0.080206, 10.121481, 0 }, + { -0.241814, 0.070629, 10.131058, 0 }, + { -0.246603, 0.071826, 10.116693, 0 }, + { -0.248997, 0.067038, 10.135846, 0 }, + { -0.251391, 0.070629, 10.132255, 0 }, + { -0.250194, 0.081403, 10.132255, 0 }, + { -0.254982, 0.074220, 10.134649, 0 }, + { -0.243011, 0.081403, 10.131058, 0 }, + { -0.237026, 0.089783, 10.128663, 0 }, + { -0.243011, 0.077812, 10.125072, 0 }, + { -0.244208, 0.074220, 10.131058, 0 }, + { -0.243011, 0.086191, 10.121481, 0 }, + { -0.250194, 0.079009, 10.135846, 0 }, + { -0.247800, 0.061052, 10.132255, 0 }, + { -0.258574, 0.063446, 10.122678, 0 }, + { -0.245406, 0.076614, 10.114298, 0 }, + { -0.238223, 0.082600, 10.101130, 0 }, + { -0.264559, 0.057461, 10.119086, 0 }, + { -0.248997, 0.077812, 10.126269, 0 }, + { -0.237026, 0.094571, 10.127466, 0 }, + { -0.256179, 0.071826, 10.116693, 0 }, + { -0.248997, 0.080206, 10.135846, 0 }, + { -0.259771, 0.067038, 10.128663, 0 }, + { -0.246603, 0.074220, 10.134649, 0 }, + { -0.244208, 0.083797, 10.131058, 0 }, + { -0.233435, 0.075417, 10.129861, 0 }, + { -0.241814, 0.074220, 10.128663, 0 }, + { -0.238223, 0.080206, 10.105919, 0 }, + { -0.241814, 0.084994, 10.131058, 0 }, + { -0.254982, 0.076614, 10.129861, 0 }, + { -0.258574, 0.079009, 10.117889, 0 }, + { -0.251391, 0.069432, 10.135846, 0 }, + { -0.243011, 0.082600, 10.135846, 0 }, + { -0.243011, 0.073023, 10.121481, 0 }, + { -0.250194, 0.074220, 10.140635, 0 }, + { -0.251391, 0.069432, 10.119086, 0 }, + { -0.258574, 0.074220, 10.117889, 0 }, + { -0.260968, 0.069432, 10.138240, 0 }, + { -0.260968, 0.080206, 10.133451, 0 }, + { -0.238223, 0.080206, 10.140635, 0 }, + { -0.248997, 0.075417, 10.103524, 0 }, + { -0.259771, 0.069432, 10.144226, 0 }, + { -0.252588, 0.076614, 10.095144, 0 }, + { -0.254982, 0.068235, 10.146620, 0 }, + { -0.256179, 0.079009, 10.143028, 0 }, + { -0.246603, 0.090980, 10.139438, 0 }, + { -0.251391, 0.079009, 10.131058, 0 }, + { -0.253785, 0.077812, 10.119086, 0 }, + { -0.256179, 0.076614, 10.157393, 0 }, + { -0.246603, 0.067038, 10.121481, 0 }, + { -0.237026, 0.081403, 10.159788, 0 }, + { -0.250194, 0.082600, 10.125072, 0 }, + { -0.248997, 0.077812, 10.117889, 0 }, + { -0.237026, 0.074220, 10.121481, 0 }, + { -0.237026, 0.062249, 10.138240, 0 }, + { -0.247800, 0.070629, 10.126269, 0 }, + { -0.245406, 0.073023, 10.138240, 0 }, + { -0.245406, 0.065841, 10.134649, 0 }, + { -0.240617, 0.083797, 10.137043, 0 }, + { -0.244208, 0.063446, 10.137043, 0 }, + { -0.260968, 0.080206, 10.123875, 0 }, + { -0.245406, 0.083797, 10.137043, 0 }, + { -0.237026, 0.068235, 10.122678, 0 }, + { -0.250194, 0.070629, 10.137043, 0 }, + { -0.248997, 0.073023, 10.128663, 0 }, + { -0.239420, 0.073023, 10.127466, 0 }, + { -0.256179, 0.069432, 10.123875, 0 }, + { -0.244208, 0.064643, 10.141831, 0 }, + { -0.246603, 0.062249, 10.114298, 0 }, + { -0.260968, 0.076614, 10.108313, 0 }, + { -0.257377, 0.069432, 10.135846, 0 }, + { -0.265756, 0.074220, 10.123875, 0 }, + { -0.254982, 0.065841, 10.145423, 0 }, + { -0.248997, 0.070629, 10.123875, 0 }, + { -0.241814, 0.079009, 10.137043, 0 }, + { -0.251391, 0.095768, 10.141831, 0 }, + { -0.244208, 0.071826, 10.111904, 0 }, + { -0.243011, 0.075417, 10.132255, 0 }, + { -0.246603, 0.090980, 10.131058, 0 }, + { -0.252588, 0.071826, 10.135846, 0 }, + { -0.248997, 0.065841, 10.120284, 0 }, + { -0.248997, 0.082600, 10.116693, 0 }, + { -0.263362, 0.075417, 10.138240, 0 }, + { -0.247800, 0.061052, 10.129861, 0 }, + { -0.250194, 0.059855, 10.132255, 0 }, + { -0.251391, 0.069432, 10.152605, 0 }, + { -0.247800, 0.068235, 10.129861, 0 }, + { -0.240617, 0.062249, 10.138240, 0 }, + { -0.264559, 0.070629, 10.120284, 0 }, + { -0.253785, 0.071826, 10.151408, 0 }, + { -0.246603, 0.074220, 10.125072, 0 }, + { -0.256179, 0.070629, 10.160985, 0 }, + { -0.247800, 0.061052, 10.131058, 0 }, + { -0.246603, 0.070629, 10.125072, 0 }, + { -0.258574, 0.086191, 10.135846, 0 }, + { -0.253785, 0.077812, 10.120284, 0 }, + { -0.235829, 0.074220, 10.133451, 0 }, + { -0.239420, 0.083797, 10.122678, 0 }, + { -0.258574, 0.071826, 10.139438, 0 }, + { -0.259771, 0.084994, 10.110707, 0 }, + { -0.243011, 0.077812, 10.131058, 0 }, + { -0.240617, 0.077812, 10.134649, 0 }, + { -0.244208, 0.059855, 10.128663, 0 }, + { -0.239420, 0.068235, 10.122678, 0 }, + { -0.258574, 0.076614, 10.119086, 0 }, + { -0.258574, 0.075417, 10.147817, 0 }, + { -0.248997, 0.062249, 10.117889, 0 }, + { -0.248997, 0.076614, 10.135846, 0 }, + { -0.241814, 0.076614, 10.109509, 0 }, + { -0.257377, 0.068235, 10.144226, 0 }, + { -0.264559, 0.064643, 10.096342, 0 }, + { -0.241814, 0.068235, 10.139438, 0 }, + { -0.250194, 0.088585, 10.114298, 0 }, + { -0.259771, 0.079009, 10.159788, 0 }, + { -0.247800, 0.071826, 10.138240, 0 }, + { -0.245406, 0.073023, 10.117889, 0 }, + { -0.246603, 0.070629, 10.137043, 0 }, + { -0.248997, 0.069432, 10.108313, 0 }, + { -0.254982, 0.077812, 10.144226, 0 }, + { -0.254982, 0.088585, 10.108313, 0 }, + { -0.245406, 0.082600, 10.135846, 0 }, + { -0.245406, 0.095768, 10.125072, 0 }, + { -0.232237, 0.083797, 10.133451, 0 }, + { -0.243011, 0.069432, 10.089159, 0 }, + { -0.237026, 0.082600, 10.152605, 0 }, + { -0.241814, 0.065841, 10.116693, 0 }, + { -0.262165, 0.067038, 10.138240, 0 }, + { -0.262165, 0.081403, 10.150211, 0 }, + { -0.257377, 0.079009, 10.109509, 0 }, + { -0.257377, 0.084994, 10.131058, 0 }, + { -0.238223, 0.090980, 10.107116, 0 }, + { -0.231040, 0.093374, 10.151408, 0 }, + { -0.250194, 0.069432, 10.108313, 0 }, + { -0.244208, 0.067038, 10.166970, 0 }, + { -0.244208, 0.074220, 10.105919, 0 }, + { -0.247800, 0.076614, 10.145423, 0 }, + { -0.237026, 0.071826, 10.122678, 0 }, + { -0.244208, 0.070629, 10.127466, 0 }, + { -0.243011, 0.074220, 10.119086, 0 }, + { -0.246603, 0.073023, 10.121481, 0 }, + { -0.245406, 0.084994, 10.129861, 0 }, + { -0.237026, 0.082600, 10.128663, 0 }, + { -0.229843, 0.074220, 10.127466, 0 }, + { -0.250194, 0.076614, 10.116693, 0 }, + { -0.240617, 0.074220, 10.138240, 0 }, + { -0.240617, 0.074220, 10.117889, 0 }, + { -0.245406, 0.075417, 10.126269, 0 }, + { -0.241814, 0.077812, 10.129861, 0 }, + { -0.251391, 0.081403, 10.139438, 0 }, + { -0.227449, 0.075417, 10.127466, 0 }, + { -0.239420, 0.079009, 10.119086, 0 }, + { -0.238223, 0.087388, 10.120284, 0 }, + { -0.243011, 0.057461, 10.122678, 0 }, + { -0.250194, 0.056264, 10.145423, 0 }, + { -0.233435, 0.075417, 10.119086, 0 }, + { -0.237026, 0.061052, 10.137043, 0 }, + { -0.240617, 0.084994, 10.123875, 0 }, + { -0.245406, 0.088585, 10.151408, 0 }, + { -0.234632, 0.081403, 10.128663, 0 }, + { -0.240617, 0.086191, 10.123875, 0 }, + { -0.237026, 0.080206, 10.119086, 0 }, + { -0.234632, 0.067038, 10.134649, 0 }, + { -0.241814, 0.070629, 10.138240, 0 }, + { -0.248997, 0.065841, 10.134649, 0 }, + { -0.238223, 0.081403, 10.143028, 0 }, + { -0.243011, 0.079009, 10.121481, 0 }, + { -0.240617, 0.079009, 10.128663, 0 }, + { -0.251391, 0.069432, 10.131058, 0 }, + { -0.244208, 0.063446, 10.138240, 0 }, + { -0.240617, 0.058658, 10.117889, 0 }, + { -0.239420, 0.081403, 10.145423, 0 }, + { -0.245406, 0.080206, 10.114298, 0 }, + { -0.240617, 0.075417, 10.127466, 0 }, + { -0.243011, 0.077812, 10.127466, 0 }, + { -0.250194, 0.065841, 10.119086, 0 }, + { -0.232237, 0.064643, 10.120284, 0 }, + { -0.239420, 0.065841, 10.131058, 0 }, + { -0.251391, 0.071826, 10.143028, 0 }, + { -0.246603, 0.080206, 10.125072, 0 }, + { -0.238223, 0.075417, 10.123875, 0 }, + { -0.245406, 0.081403, 10.132255, 0 }, + { -0.241814, 0.083797, 10.117889, 0 }, + { -0.251391, 0.070629, 10.135846, 0 }, + { -0.262165, 0.075417, 10.120284, 0 }, + { -0.251391, 0.086191, 10.145423, 0 }, + { -0.239420, 0.087388, 10.131058, 0 }, + { -0.246603, 0.077812, 10.126269, 0 }, + { -0.246603, 0.073023, 10.135846, 0 }, + { -0.264559, 0.079009, 10.120284, 0 }, + { -0.264559, 0.074220, 10.125072, 0 }, + { -0.229843, 0.067038, 10.127466, 0 }, + { -0.231040, 0.077812, 10.131058, 0 }, + { -0.245406, 0.075417, 10.128663, 0 }, + { -0.240617, 0.071826, 10.116693, 0 }, + { -0.234632, 0.081403, 10.128663, 0 }, + { -0.228646, 0.063446, 10.132255, 0 }, + { -0.227449, 0.057461, 10.139438, 0 }, + { -0.251391, 0.075417, 10.120284, 0 }, + { -0.231040, 0.092177, 10.122678, 0 }, + { -0.240617, 0.077812, 10.137043, 0 }, + { -0.252588, 0.075417, 10.132255, 0 }, + { -0.248997, 0.077812, 10.120284, 0 }, + { -0.248997, 0.080206, 10.117889, 0 }, + { -0.252588, 0.063446, 10.113101, 0 }, + { -0.247800, 0.069432, 10.133451, 0 }, + { -0.246603, 0.092177, 10.108313, 0 }, + { -0.240617, 0.088585, 10.134649, 0 }, + { -0.239420, 0.076614, 10.125072, 0 }, + { -0.248997, 0.070629, 10.128663, 0 }, + { -0.243011, 0.073023, 10.128663, 0 }, + { -0.243011, 0.084994, 10.115496, 0 }, + { -0.243011, 0.087388, 10.141831, 0 }, + { -0.237026, 0.070629, 10.144226, 0 }, + { -0.247800, 0.081403, 10.113101, 0 }, + { -0.234632, 0.096965, 10.133451, 0 }, + { -0.258574, 0.069432, 10.132255, 0 }, + { -0.258574, 0.077812, 10.116693, 0 }, + { -0.243011, 0.079009, 10.135846, 0 }, + { -0.253785, 0.082600, 10.102327, 0 }, + { -0.240617, 0.075417, 10.144226, 0 }, + { -0.247800, 0.074220, 10.123875, 0 }, + { -0.256179, 0.079009, 10.120284, 0 }, + { -0.254982, 0.077812, 10.141831, 0 }, + { -0.257377, 0.076614, 10.143028, 0 }, + { -0.250194, 0.086191, 10.137043, 0 }, + { -0.238223, 0.081403, 10.116693, 0 }, + { -0.238223, 0.084994, 10.139438, 0 }, + { -0.247800, 0.080206, 10.126269, 0 }, + { -0.263362, 0.074220, 10.131058, 0 }, + { -0.260968, 0.077812, 10.123875, 0 }, + { -0.238223, 0.059855, 10.128663, 0 }, + { -0.245406, 0.062249, 10.134649, 0 }, + { -0.257377, 0.080206, 10.131058, 0 }, + { -0.244208, 0.083797, 10.131058, 0 }, + { -0.232237, 0.080206, 10.134649, 0 }, + { -0.244208, 0.076614, 10.119086, 0 }, + { -0.241814, 0.073023, 10.141831, 0 }, + { -0.257377, 0.067038, 10.138240, 0 }, + { -0.241814, 0.086191, 10.133451, 0 }, + { -0.246603, 0.079009, 10.133451, 0 }, + { -0.248997, 0.067038, 10.125072, 0 }, + { -0.239420, 0.082600, 10.122678, 0 }, + { -0.244208, 0.084994, 10.129861, 0 }, + { -0.233435, 0.073023, 10.147817, 0 }, + { -0.250194, 0.069432, 10.133451, 0 }, + { -0.254982, 0.070629, 10.146620, 0 }, + { -0.231040, 0.083797, 10.117889, 0 }, + { -0.245406, 0.081403, 10.119086, 0 }, + { -0.256179, 0.093374, 10.131058, 0 }, + { -0.241814, 0.084994, 10.138240, 0 }, + { -0.252588, 0.073023, 10.137043, 0 }, + { -0.251391, 0.081403, 10.126269, 0 }, + { -0.235829, 0.069432, 10.137043, 0 }, + { -0.247800, 0.080206, 10.132255, 0 }, + { -0.238223, 0.064643, 10.144226, 0 }, + { -0.234632, 0.076614, 10.127466, 0 }, + { -0.245406, 0.069432, 10.137043, 0 }, + { -0.241814, 0.082600, 10.116693, 0 }, + { -0.233435, 0.101754, 10.132255, 0 }, + { -0.240617, 0.086191, 10.132255, 0 }, + { -0.235829, 0.081403, 10.120284, 0 }, + { -0.239420, 0.076614, 10.128663, 0 }, + { -0.251391, 0.079009, 10.117889, 0 }, + { -0.256179, 0.081403, 10.149014, 0 }, + { -0.238223, 0.079009, 10.105919, 0 }, + { -0.234632, 0.079009, 10.125072, 0 }, + { -0.254982, 0.071826, 10.115496, 0 }, + { -0.263362, 0.082600, 10.151408, 0 }, + { -0.243011, 0.075417, 10.109509, 0 }, + { -0.222661, 0.073023, 10.129861, 0 }, + { -0.246603, 0.074220, 10.133451, 0 }, + { -0.248997, 0.086191, 10.129861, 0 }, + { -0.252588, 0.086191, 10.149014, 0 }, + { -0.238223, 0.071826, 10.104721, 0 }, + { -0.237026, 0.071826, 10.135846, 0 }, + { -0.243011, 0.086191, 10.111904, 0 }, + { -0.244208, 0.093374, 10.141831, 0 }, + { -0.253785, 0.063446, 10.123875, 0 }, + { -0.244208, 0.083797, 10.134649, 0 }, + { -0.244208, 0.090980, 10.128663, 0 }, + { -0.258574, 0.065841, 10.134649, 0 }, + { -0.256179, 0.070629, 10.128663, 0 }, + { -0.243011, 0.071826, 10.137043, 0 }, + { -0.225055, 0.074220, 10.134649, 0 }, + { -0.245406, 0.069432, 10.116693, 0 }, + { -0.237026, 0.077812, 10.133451, 0 }, + { -0.245406, 0.073023, 10.104721, 0 }, + { -0.253785, 0.081403, 10.159788, 0 }, + { -0.245406, 0.086191, 10.113101, 0 }, + { -0.243011, 0.081403, 10.126269, 0 }, + { -0.241814, 0.065841, 10.108313, 0 }, + { -0.240617, 0.057461, 10.131058, 0 }, + { -0.241814, 0.065841, 10.144226, 0 }, + { -0.237026, 0.073023, 10.128663, 0 }, + { -0.250194, 0.090980, 10.145423, 0 }, + { -0.254982, 0.070629, 10.119086, 0 }, + { -0.244208, 0.063446, 10.131058, 0 }, + { -0.235829, 0.077812, 10.121481, 0 }, + { -0.248997, 0.076614, 10.137043, 0 }, + { -0.262165, 0.076614, 10.123875, 0 }, + { -0.250194, 0.064643, 10.119086, 0 }, + { -0.239420, 0.077812, 10.116693, 0 }, + { -0.245406, 0.080206, 10.128663, 0 }, + { -0.243011, 0.084994, 10.123875, 0 }, + { -0.244208, 0.077812, 10.125072, 0 }, + { -0.237026, 0.089783, 10.122678, 0 }, + { -0.235829, 0.065841, 10.137043, 0 }, + { -0.245406, 0.065841, 10.150211, 0 }, + { -0.252588, 0.074220, 10.111904, 0 }, + { -0.241814, 0.068235, 10.146620, 0 }, + { -0.229843, 0.069432, 10.120284, 0 }, + { -0.240617, 0.079009, 10.131058, 0 }, + { -0.240617, 0.084994, 10.095144, 0 }, + { -0.239420, 0.067038, 10.133451, 0 }, + { -0.247800, 0.083797, 10.128663, 0 }, + { -0.252588, 0.075417, 10.135846, 0 }, + { -0.252588, 0.068235, 10.131058, 0 }, + { -0.243011, 0.087388, 10.102327, 0 }, + { -0.247800, 0.088585, 10.132255, 0 }, + { -0.243011, 0.086191, 10.127466, 0 }, + { -0.229843, 0.080206, 10.123875, 0 }, + { -0.245406, 0.073023, 10.134649, 0 }, + { -0.233435, 0.081403, 10.132255, 0 }, + { -0.245406, 0.082600, 10.126269, 0 }, + { -0.233435, 0.073023, 10.137043, 0 }, + { -0.235829, 0.070629, 10.140635, 0 }, + { -0.241814, 0.076614, 10.121481, 0 }, + { -0.244208, 0.069432, 10.123875, 0 }, + { -0.252588, 0.075417, 10.140635, 0 }, + { -0.253785, 0.080206, 10.133451, 0 }, + { -0.237026, 0.075417, 10.121481, 0 }, + { -0.227449, 0.065841, 10.129861, 0 }, + { -0.245406, 0.077812, 10.131058, 0 }, + { -0.229843, 0.094571, 10.129861, 0 }, + { -0.237026, 0.068235, 10.105919, 0 }, + { -0.260968, 0.073023, 10.120284, 0 }, + { -0.241814, 0.076614, 10.131058, 0 }, + { -0.250194, 0.077812, 10.126269, 0 }, + { -0.254982, 0.068235, 10.135846, 0 }, + { -0.240617, 0.071826, 10.108313, 0 }, + { -0.258574, 0.083797, 10.125072, 0 }, + { -0.254982, 0.081403, 10.132255, 0 }, + { -0.251391, 0.079009, 10.135846, 0 }, + { -0.245406, 0.069432, 10.121481, 0 }, + { -0.232237, 0.069432, 10.122678, 0 }, + { -0.234632, 0.083797, 10.131058, 0 }, + { -0.234632, 0.089783, 10.129861, 0 }, + { -0.238223, 0.079009, 10.127466, 0 }, + { -0.246603, 0.083797, 10.121481, 0 }, + { -0.247800, 0.074220, 10.121481, 0 }, + { -0.247800, 0.075417, 10.117889, 0 }, + { -0.235829, 0.065841, 10.129861, 0 }, + { -0.241814, 0.075417, 10.111904, 0 }, + { -0.239420, 0.081403, 10.129861, 0 }, + { -0.247800, 0.087388, 10.128663, 0 }, + { -0.243011, 0.079009, 10.126269, 0 }, + { -0.245406, 0.067038, 10.137043, 0 }, + { -0.257377, 0.059855, 10.122678, 0 }, + { -0.250194, 0.068235, 10.147817, 0 }, + { -0.243011, 0.074220, 10.129861, 0 }, + { -0.237026, 0.086191, 10.129861, 0 }, + { -0.246603, 0.107739, 10.131058, 0 }, + { -0.241814, 0.082600, 10.141831, 0 }, + { -0.245406, 0.064643, 10.119086, 0 }, + { -0.258574, 0.075417, 10.129861, 0 }, + { -0.237026, 0.071826, 10.123875, 0 }, + { -0.243011, 0.075417, 10.101130, 0 }, + { -0.253785, 0.083797, 10.125072, 0 }, + { -0.241814, 0.081403, 10.119086, 0 }, + { -0.234632, 0.089783, 10.137043, 0 }, + { -0.245406, 0.070629, 10.132255, 0 }, + { -0.251391, 0.067038, 10.131058, 0 }, + { -0.250194, 0.069432, 10.139438, 0 }, + { -0.237026, 0.086191, 10.123875, 0 }, + { -0.235829, 0.086191, 10.147817, 0 }, + { -0.248997, 0.074220, 10.123875, 0 }, + { -0.251391, 0.079009, 10.114298, 0 }, + { -0.246603, 0.081403, 10.122678, 0 }, + { -0.235829, 0.079009, 10.119086, 0 }, + { -0.240617, 0.087388, 10.127466, 0 }, + { -0.239420, 0.077812, 10.133451, 0 }, + { -0.247800, 0.087388, 10.108313, 0 }, + { -0.245406, 0.087388, 10.111904, 0 }, + { -0.237026, 0.073023, 10.147817, 0 }, + { -0.241814, 0.079009, 10.135846, 0 }, + { -0.241814, 0.074220, 10.121481, 0 }, + { -0.258574, 0.063446, 10.146620, 0 }, + { -0.243011, 0.079009, 10.123875, 0 }, + { -0.225055, 0.073023, 10.122678, 0 }, + { -0.234632, 0.075417, 10.119086, 0 }, + { -0.246603, 0.068235, 10.134649, 0 }, + { -0.235829, 0.071826, 10.141831, 0 }, + { -0.234632, 0.069432, 10.137043, 0 }, + { -0.244208, 0.064643, 10.126269, 0 }, + { -0.239420, 0.068235, 10.125072, 0 }, + { -0.246603, 0.087388, 10.131058, 0 }, + { -0.241814, 0.071826, 10.128663, 0 }, + { -0.241814, 0.083797, 10.140635, 0 }, + { -0.252588, 0.070629, 10.119086, 0 }, + { -0.243011, 0.070629, 10.117889, 0 }, + { -0.265756, 0.077812, 10.125072, 0 }, + { -0.248997, 0.083797, 10.129861, 0 }, + { -0.248997, 0.082600, 10.122678, 0 }, + { -0.247800, 0.083797, 10.133451, 0 }, + { -0.260968, 0.086191, 10.141831, 0 }, + { -0.244208, 0.075417, 10.132255, 0 }, + { -0.232237, 0.080206, 10.135846, 0 }, + { -0.244208, 0.077812, 10.131058, 0 }, + { -0.239420, 0.077812, 10.143028, 0 }, + { -0.238223, 0.077812, 10.127466, 0 }, + { -0.235829, 0.089783, 10.140635, 0 }, + { -0.239420, 0.070629, 10.111904, 0 }, + { -0.253785, 0.064643, 10.129861, 0 }, + { -0.250194, 0.065841, 10.127466, 0 }, + { -0.251391, 0.073023, 10.110707, 0 }, + { -0.240617, 0.069432, 10.098736, 0 }, + { -0.246603, 0.074220, 10.122678, 0 }, + { -0.243011, 0.077812, 10.141831, 0 }, + { -0.243011, 0.074220, 10.131058, 0 }, + { -0.247800, 0.081403, 10.125072, 0 }, + { -0.256179, 0.057461, 10.134649, 0 }, + { -0.243011, 0.068235, 10.144226, 0 }, + { -0.228646, 0.095768, 10.125072, 0 }, + { -0.250194, 0.083797, 10.135846, 0 }, + { -0.246603, 0.062249, 10.122678, 0 }, + { -0.245406, 0.073023, 10.119086, 0 }, + { -0.246603, 0.081403, 10.122678, 0 }, + { -0.246603, 0.080206, 10.129861, 0 }, + { -0.231040, 0.067038, 10.116693, 0 }, + { -0.228646, 0.074220, 10.129861, 0 }, + { -0.235829, 0.073023, 10.134649, 0 }, + { -0.246603, 0.093374, 10.123875, 0 }, + { -0.252588, 0.080206, 10.127466, 0 }, + { -0.233435, 0.061052, 10.133451, 0 }, + { -0.243011, 0.070629, 10.137043, 0 }, + { -0.250194, 0.077812, 10.108313, 0 }, + { -0.235829, 0.083797, 10.121481, 0 }, + { -0.247800, 0.081403, 10.141831, 0 }, + { -0.252588, 0.081403, 10.131058, 0 }, + { -0.243011, 0.080206, 10.126269, 0 }, + { -0.235829, 0.070629, 10.109509, 0 }, + { -0.237026, 0.073023, 10.135846, 0 }, + { -0.237026, 0.074220, 10.123875, 0 }, + { -0.253785, 0.089783, 10.117889, 0 }, + { -0.248997, 0.087388, 10.123875, 0 }, + { -0.228646, 0.073023, 10.128663, 0 }, + { -0.233435, 0.073023, 10.137043, 0 }, + { -0.247800, 0.080206, 10.123875, 0 }, + { -0.254982, 0.074220, 10.132255, 0 }, + { -0.234632, 0.081403, 10.113101, 0 }, + { -0.241814, 0.074220, 10.149014, 0 }, + { -0.244208, 0.064643, 10.119086, 0 }, + { -0.235829, 0.069432, 10.121481, 0 }, + { -0.237026, 0.071826, 10.123875, 0 }, + { -0.241814, 0.065841, 10.134649, 0 }, + { -0.237026, 0.065841, 10.153803, 0 }, + { -0.239420, 0.077812, 10.135846, 0 }, + { -0.244208, 0.073023, 10.125072, 0 }, + { -0.246603, 0.065841, 10.117889, 0 }, + { -0.237026, 0.073023, 10.129861, 0 }, + { -0.254982, 0.080206, 10.111904, 0 }, + { -0.241814, 0.076614, 10.140635, 0 }, + { -0.243011, 0.057461, 10.123875, 0 }, + { -0.241814, 0.081403, 10.139438, 0 }, + { -0.246603, 0.070629, 10.131058, 0 }, + { -0.251391, 0.075417, 10.147817, 0 }, + { -0.251391, 0.070629, 10.120284, 0 }, + { -0.234632, 0.086191, 10.137043, 0 }, + { -0.235829, 0.079009, 10.119086, 0 }, + { -0.235829, 0.086191, 10.119086, 0 }, + { -0.234632, 0.069432, 10.121481, 0 }, + { -0.246603, 0.069432, 10.126269, 0 }, + { -0.245406, 0.083797, 10.145423, 0 }, + { -0.245406, 0.077812, 10.116693, 0 }, + { -0.240617, 0.079009, 10.144226, 0 }, + { -0.237026, 0.073023, 10.134649, 0 }, + { -0.238223, 0.077812, 10.140635, 0 }, + { -0.227449, 0.082600, 10.127466, 0 }, + { -0.233435, 0.092177, 10.122678, 0 }, + { -0.246603, 0.083797, 10.140635, 0 }, + { -0.229843, 0.065841, 10.134649, 0 }, + { -0.227449, 0.080206, 10.138240, 0 }, + { -0.243011, 0.077812, 10.138240, 0 }, + { -0.240617, 0.076614, 10.119086, 0 }, + { -0.241814, 0.073023, 10.125072, 0 }, + { -0.240617, 0.071826, 10.123875, 0 }, + { -0.250194, 0.079009, 10.117889, 0 }, + { -0.243011, 0.080206, 10.145423, 0 }, + { -0.252588, 0.081403, 10.119086, 0 }, + { -0.240617, 0.068235, 10.132255, 0 }, + { -0.244208, 0.065841, 10.114298, 0 }, + { -0.235829, 0.073023, 10.125072, 0 }, + { -0.248997, 0.076614, 10.117889, 0 }, + { -0.250194, 0.059855, 10.121481, 0 }, + { -0.239420, 0.095768, 10.147817, 0 }, + { -0.262165, 0.081403, 10.116693, 0 }, + { -0.253785, 0.065841, 10.149014, 0 }, + { -0.244208, 0.067038, 10.115496, 0 }, + { -0.238223, 0.074220, 10.122678, 0 }, + { -0.235829, 0.075417, 10.149014, 0 }, + { -0.243011, 0.062249, 10.144226, 0 }, + { -0.244208, 0.073023, 10.123875, 0 }, + { -0.239420, 0.084994, 10.132255, 0 }, + { -0.238223, 0.074220, 10.120284, 0 }, + { -0.256179, 0.063446, 10.137043, 0 }, + { -0.243011, 0.061052, 10.117889, 0 }, + { -0.235829, 0.064643, 10.119086, 0 }, + { -0.235829, 0.079009, 10.133451, 0 }, + { -0.237026, 0.082600, 10.119086, 0 }, + { -0.238223, 0.079009, 10.139438, 0 }, + { -0.247800, 0.065841, 10.117889, 0 }, + { -0.243011, 0.069432, 10.158591, 0 }, + { -0.246603, 0.080206, 10.122678, 0 }, + { -0.256179, 0.083797, 10.141831, 0 }, + { -0.235829, 0.092177, 10.108313, 0 }, + { -0.237026, 0.061052, 10.132255, 0 }, + { -0.237026, 0.058658, 10.156197, 0 }, + { -0.244208, 0.059855, 10.117889, 0 }, + { -0.237026, 0.087388, 10.144226, 0 }, + { -0.257377, 0.094571, 10.110707, 0 }, + { -0.256179, 0.080206, 10.132255, 0 }, + { -0.243011, 0.089783, 10.133451, 0 }, + { -0.238223, 0.080206, 10.133451, 0 }, + { -0.240617, 0.067038, 10.114298, 0 }, + { -0.246603, 0.064643, 10.133451, 0 }, + { -0.245406, 0.075417, 10.128663, 0 }, + { -0.240617, 0.071826, 10.122678, 0 }, + { -0.229843, 0.068235, 10.126269, 0 }, + { -0.240617, 0.081403, 10.123875, 0 }, + { -0.244208, 0.079009, 10.138240, 0 }, + { -0.237026, 0.065841, 10.145423, 0 }, + { -0.239420, 0.069432, 10.133451, 0 }, + { -0.253785, 0.076614, 10.127466, 0 }, + { -0.256179, 0.082600, 10.125072, 0 }, + { -0.232237, 0.081403, 10.113101, 0 }, + { -0.239420, 0.065841, 10.139438, 0 }, + { -0.241814, 0.084994, 10.128663, 0 }, + { -0.252588, 0.071826, 10.122678, 0 }, + { -0.243011, 0.067038, 10.157393, 0 }, + { -0.251391, 0.081403, 10.134649, 0 }, + { -0.251391, 0.083797, 10.127466, 0 }, + { -0.265756, 0.074220, 10.115496, 0 }, + { -0.245406, 0.062249, 10.150211, 0 }, + { -0.241814, 0.070629, 10.117889, 0 }, + { -0.257377, 0.083797, 10.120284, 0 }, + { -0.239420, 0.081403, 10.121481, 0 }, + { -0.247800, 0.068235, 10.135846, 0 }, + { -0.243011, 0.071826, 10.129861, 0 }, + { -0.235829, 0.082600, 10.128663, 0 }, + { -0.247800, 0.073023, 10.145423, 0 }, + { -0.258574, 0.065841, 10.123875, 0 }, + { -0.233435, 0.069432, 10.122678, 0 }, + { -0.245406, 0.076614, 10.120284, 0 }, + { -0.247800, 0.089783, 10.131058, 0 }, + { -0.244208, 0.090980, 10.114298, 0 }, + { -0.247800, 0.089783, 10.143028, 0 }, + { -0.229843, 0.073023, 10.119086, 0 }, + { -0.240617, 0.082600, 10.134649, 0 }, + { -0.244208, 0.095768, 10.125072, 0 }, + { -0.241814, 0.083797, 10.145423, 0 }, + { -0.250194, 0.068235, 10.139438, 0 }, + { -0.248997, 0.075417, 10.113101, 0 }, + { -0.250194, 0.076614, 10.128663, 0 }, + { -0.247800, 0.081403, 10.114298, 0 }, + { -0.247800, 0.075417, 10.123875, 0 }, + { -0.248997, 0.095768, 10.145423, 0 }, + { -0.245406, 0.088585, 10.143028, 0 }, + { -0.238223, 0.084994, 10.113101, 0 }, + { -0.240617, 0.071826, 10.126269, 0 }, + { -0.240617, 0.067038, 10.140635, 0 }, + { -0.245406, 0.071826, 10.138240, 0 }, + { -0.254982, 0.073023, 10.128663, 0 }, + { -0.245406, 0.077812, 10.145423, 0 }, + { -0.250194, 0.070629, 10.127466, 0 }, + { -0.243011, 0.073023, 10.137043, 0 }, + { -0.245406, 0.067038, 10.117889, 0 }, + { -0.243011, 0.071826, 10.151408, 0 }, + { -0.252588, 0.081403, 10.128663, 0 }, + { -0.233435, 0.074220, 10.110707, 0 }, + { -0.243011, 0.074220, 10.126269, 0 }, + { -0.239420, 0.089783, 10.143028, 0 }, + { -0.237026, 0.086191, 10.123875, 0 }, + { -0.243011, 0.064643, 10.129861, 0 }, + { -0.234632, 0.077812, 10.133451, 0 }, + { -0.250194, 0.086191, 10.133451, 0 }, + { -0.241814, 0.074220, 10.125072, 0 }, + { -0.243011, 0.086191, 10.122678, 0 }, + { -0.234632, 0.076614, 10.121481, 0 }, + { -0.251391, 0.082600, 10.135846, 0 }, + { -0.251391, 0.084994, 10.133451, 0 }, + { -0.245406, 0.063446, 10.117889, 0 }, + { -0.253785, 0.079009, 10.122678, 0 }, + { -0.243011, 0.074220, 10.129861, 0 }, + { -0.233435, 0.069432, 10.127466, 0 }, + { -0.251391, 0.077812, 10.126269, 0 }, + { -0.245406, 0.079009, 10.120284, 0 }, + { -0.247800, 0.068235, 10.128663, 0 }, + { -0.244208, 0.069432, 10.133451, 0 }, + { -0.238223, 0.074220, 10.146620, 0 }, + { -0.241814, 0.080206, 10.120284, 0 }, + { -0.248997, 0.071826, 10.107116, 0 }, + { -0.240617, 0.073023, 10.123875, 0 }, + { -0.239420, 0.063446, 10.135846, 0 }, + { -0.245406, 0.068235, 10.117889, 0 }, + { -0.248997, 0.088585, 10.105919, 0 }, + { -0.248997, 0.067038, 10.138240, 0 }, + { -0.247800, 0.074220, 10.128663, 0 }, + { -0.237026, 0.079009, 10.138240, 0 }, + { -0.243011, 0.092177, 10.140635, 0 }, + { -0.235829, 0.082600, 10.128663, 0 }, + { -0.240617, 0.079009, 10.116693, 0 }, + { -0.248997, 0.087388, 10.114298, 0 }, + { -0.238223, 0.079009, 10.120284, 0 }, + { -0.241814, 0.087388, 10.128663, 0 }, + { -0.250194, 0.063446, 10.129861, 0 }, + { -0.245406, 0.071826, 10.128663, 0 }, + { -0.251391, 0.073023, 10.123875, 0 }, + { -0.258574, 0.084994, 10.137043, 0 }, + { -0.246603, 0.077812, 10.140635, 0 }, + { -0.244208, 0.070629, 10.111904, 0 }, + { -0.252588, 0.075417, 10.143028, 0 }, + { -0.248997, 0.069432, 10.117889, 0 }, + { -0.243011, 0.073023, 10.129861, 0 }, + { -0.238223, 0.079009, 10.143028, 0 }, + { -0.238223, 0.080206, 10.114298, 0 }, + { -0.241814, 0.074220, 10.132255, 0 }, + { -0.240617, 0.065841, 10.132255, 0 }, + { -0.247800, 0.069432, 10.134649, 0 }, + { -0.251391, 0.075417, 10.132255, 0 }, + { -0.238223, 0.086191, 10.115496, 0 }, + { -0.245406, 0.076614, 10.139438, 0 }, + { -0.240617, 0.073023, 10.123875, 0 }, + { -0.238223, 0.071826, 10.137043, 0 }, + { -0.245406, 0.076614, 10.135846, 0 }, + { -0.251391, 0.081403, 10.133451, 0 }, + { -0.251391, 0.086191, 10.134649, 0 }, + { -0.248997, 0.079009, 10.115496, 0 }, + { -0.256179, 0.067038, 10.133451, 0 }, + { -0.246603, 0.068235, 10.121481, 0 }, + { -0.244208, 0.082600, 10.135846, 0 }, + { -0.250194, 0.079009, 10.122678, 0 }, + { -0.252588, 0.079009, 10.120284, 0 }, + { -0.243011, 0.083797, 10.127466, 0 }, + { -0.243011, 0.071826, 10.119086, 0 }, + { -0.251391, 0.081403, 10.128663, 0 }, + { -0.252588, 0.065841, 10.122678, 0 }, + { -0.240617, 0.079009, 10.131058, 0 }, + { -0.253785, 0.082600, 10.121481, 0 }, + { -0.256179, 0.071826, 10.140635, 0 }, + { -0.263362, 0.070629, 10.123875, 0 }, + { -0.248997, 0.074220, 10.123875, 0 }, + { -0.235829, 0.064643, 10.125072, 0 }, + { -0.238223, 0.082600, 10.125072, 0 }, + { -0.238223, 0.077812, 10.108313, 0 }, + { -0.231040, 0.071826, 10.117889, 0 }, + { -0.250194, 0.093374, 10.122678, 0 }, + { -0.241814, 0.080206, 10.123875, 0 }, + { -0.258574, 0.073023, 10.117889, 0 }, + { -0.248997, 0.071826, 10.127466, 0 }, + { -0.246603, 0.067038, 10.146620, 0 }, + { -0.248997, 0.074220, 10.126269, 0 }, + { -0.248997, 0.071826, 10.133451, 0 }, + { -0.247800, 0.080206, 10.133451, 0 }, + { -0.239420, 0.076614, 10.138240, 0 }, + { -0.248997, 0.081403, 10.127466, 0 }, + { -0.248997, 0.076614, 10.137043, 0 }, + { -0.248997, 0.080206, 10.123875, 0 }, + { -0.239420, 0.067038, 10.141831, 0 }, + { -0.235829, 0.083797, 10.119086, 0 }, + { -0.247800, 0.069432, 10.134649, 0 }, + { -0.237026, 0.087388, 10.137043, 0 }, + { -0.246603, 0.073023, 10.131058, 0 }, + { -0.251391, 0.083797, 10.135846, 0 }, + { -0.247800, 0.071826, 10.121481, 0 }, + { -0.246603, 0.076614, 10.128663, 0 }, + { -0.251391, 0.082600, 10.114298, 0 }, + { -0.254982, 0.082600, 10.134649, 0 }, + { -0.237026, 0.084994, 10.117889, 0 }, + { -0.229843, 0.077812, 10.119086, 0 }, + { -0.246603, 0.070629, 10.125072, 0 }, + { -0.235829, 0.076614, 10.140635, 0 }, + { -0.245406, 0.061052, 10.122678, 0 }, + { -0.240617, 0.076614, 10.119086, 0 }, + { -0.259771, 0.088585, 10.126269, 0 }, + { -0.241814, 0.077812, 10.139438, 0 }, + { -0.244208, 0.075417, 10.116693, 0 }, + { -0.239420, 0.067038, 10.109509, 0 }, + { -0.241814, 0.083797, 10.134649, 0 }, + { -0.244208, 0.067038, 10.125072, 0 }, + { -0.244208, 0.073023, 10.149014, 0 }, + { -0.243011, 0.084994, 10.116693, 0 }, + { -0.231040, 0.076614, 10.123875, 0 }, + { -0.247800, 0.089783, 10.120284, 0 }, + { -0.246603, 0.077812, 10.122678, 0 }, + { -0.262165, 0.077812, 10.120284, 0 }, + { -0.231040, 0.070629, 10.115496, 0 }, + { -0.243011, 0.077812, 10.149014, 0 }, + { -0.248997, 0.090980, 10.119086, 0 }, + { -0.250194, 0.090980, 10.132255, 0 }, + { -0.238223, 0.074220, 10.120284, 0 }, + { -0.228646, 0.080206, 10.140635, 0 }, + { -0.245406, 0.075417, 10.113101, 0 }, + { -0.233435, 0.089783, 10.131058, 0 }, + { -0.244208, 0.081403, 10.117889, 0 }, + { -0.246603, 0.063446, 10.141831, 0 }, + { -0.235829, 0.090980, 10.143028, 0 }, + { -0.233435, 0.081403, 10.125072, 0 }, + { -0.251391, 0.077812, 10.127466, 0 }, + { -0.238223, 0.081403, 10.125072, 0 }, + { -0.235829, 0.074220, 10.132255, 0 }, + { -0.244208, 0.064643, 10.119086, 0 }, + { -0.256179, 0.071826, 10.143028, 0 }, + { -0.240617, 0.082600, 10.110707, 0 }, + { -0.248997, 0.071826, 10.137043, 0 }, + { -0.251391, 0.076614, 10.125072, 0 }, + { -0.228646, 0.082600, 10.134649, 0 }, + { -0.233435, 0.082600, 10.111904, 0 }, + { -0.246603, 0.068235, 10.119086, 0 }, + { -0.235829, 0.067038, 10.143028, 0 }, + { -0.241814, 0.079009, 10.126269, 0 }, + { -0.238223, 0.095768, 10.125072, 0 }, + { -0.243011, 0.065841, 10.105919, 0 }, + { -0.256179, 0.081403, 10.132255, 0 }, + { -0.256179, 0.073023, 10.110707, 0 }, + { -0.246603, 0.079009, 10.145423, 0 }, + { -0.231040, 0.069432, 10.122678, 0 }, + { -0.234632, 0.065841, 10.139438, 0 }, + { -0.232237, 0.094571, 10.126269, 0 }, + { -0.243011, 0.081403, 10.149014, 0 }, + { -0.256179, 0.083797, 10.132255, 0 }, + { -0.246603, 0.073023, 10.127466, 0 }, + { -0.244208, 0.067038, 10.131058, 0 }, + { -0.244208, 0.082600, 10.133451, 0 }, + { -0.239420, 0.088585, 10.137043, 0 }, + { -0.234632, 0.069432, 10.123875, 0 }, + { -0.241814, 0.069432, 10.137043, 0 }, + { -0.241814, 0.083797, 10.120284, 0 }, + { -0.243011, 0.075417, 10.134649, 0 }, + { -0.250194, 0.075417, 10.132255, 0 }, + { -0.240617, 0.076614, 10.126269, 0 }, + { -0.265756, 0.083797, 10.137043, 0 }, + { -0.258574, 0.079009, 10.116693, 0 }, + { -0.237026, 0.069432, 10.122678, 0 }, + { -0.248997, 0.073023, 10.121481, 0 }, + { -0.256179, 0.080206, 10.123875, 0 }, + { -0.248997, 0.067038, 10.122678, 0 }, + { -0.237026, 0.083797, 10.143028, 0 }, + { -0.238223, 0.080206, 10.114298, 0 }, + { -0.253785, 0.074220, 10.129861, 0 }, + { -0.250194, 0.075417, 10.129861, 0 }, + { -0.254982, 0.081403, 10.151408, 0 }, + { -0.250194, 0.070629, 10.135846, 0 }, + { -0.247800, 0.075417, 10.120284, 0 }, + { -0.241814, 0.064643, 10.139438, 0 }, + { -0.246603, 0.071826, 10.138240, 0 }, + { -0.243011, 0.079009, 10.152605, 0 }, + { -0.241814, 0.080206, 10.127466, 0 }, + { -0.251391, 0.070629, 10.129861, 0 }, + { -0.243011, 0.081403, 10.139438, 0 }, + { -0.251391, 0.070629, 10.129861, 0 }, + { -0.251391, 0.076614, 10.122678, 0 }, + { -0.252588, 0.079009, 10.133451, 0 }, + { -0.254982, 0.073023, 10.128663, 0 }, + { -0.232237, 0.067038, 10.113101, 0 }, + { -0.239420, 0.088585, 10.120284, 0 }, + { -0.245406, 0.080206, 10.113101, 0 }, + { -0.238223, 0.075417, 10.131058, 0 }, + { -0.244208, 0.065841, 10.109509, 0 }, + { -0.235829, 0.068235, 10.141831, 0 }, + { -0.251391, 0.081403, 10.121481, 0 }, + { -0.250194, 0.077812, 10.119086, 0 }, + { -0.241814, 0.071826, 10.126269, 0 }, + { -0.233435, 0.069432, 10.135846, 0 }, + { -0.239420, 0.076614, 10.131058, 0 }, + { -0.239420, 0.088585, 10.107116, 0 }, + { -0.234632, 0.084994, 10.126269, 0 }, + { -0.247800, 0.077812, 10.128663, 0 }, + { -0.246603, 0.083797, 10.137043, 0 }, + { -0.240617, 0.087388, 10.127466, 0 }, + { -0.256179, 0.070629, 10.117889, 0 }, + { -0.243011, 0.077812, 10.121481, 0 }, + { -0.243011, 0.083797, 10.133451, 0 }, + { -0.252588, 0.087388, 10.125072, 0 }, + { -0.256179, 0.073023, 10.127466, 0 }, + { -0.239420, 0.057461, 10.128663, 0 }, + { -0.243011, 0.070629, 10.117889, 0 }, + { -0.252588, 0.074220, 10.138240, 0 }, + { -0.243011, 0.073023, 10.127466, 0 }, + { -0.238223, 0.082600, 10.133451, 0 }, + { -0.235829, 0.074220, 10.143028, 0 }, + { -0.248997, 0.065841, 10.153803, 0 }, + { -0.240617, 0.081403, 10.107116, 0 }, + { -0.241814, 0.087388, 10.123875, 0 }, + { -0.241814, 0.070629, 10.141831, 0 }, + { -0.238223, 0.074220, 10.113101, 0 }, + { -0.251391, 0.079009, 10.129861, 0 }, + { -0.253785, 0.082600, 10.108313, 0 }, + { -0.254982, 0.075417, 10.121481, 0 }, + { -0.247800, 0.057461, 10.133451, 0 }, + { -0.243011, 0.058658, 10.128663, 0 }, + { -0.244208, 0.080206, 10.120284, 0 }, + { -0.231040, 0.079009, 10.109509, 0 }, + { -0.256179, 0.070629, 10.120284, 0 }, + { -0.251391, 0.082600, 10.143028, 0 }, + { -0.233435, 0.068235, 10.128663, 0 }, + { -0.241814, 0.068235, 10.129861, 0 }, + { -0.235829, 0.083797, 10.111904, 0 }, + { -0.238223, 0.067038, 10.139438, 0 }, + { -0.260968, 0.063446, 10.128663, 0 }, + { -0.231040, 0.084994, 10.140635, 0 }, + { -0.237026, 0.082600, 10.134649, 0 }, + { -0.246603, 0.070629, 10.144226, 0 }, + { -0.246603, 0.080206, 10.125072, 0 }, + { -0.244208, 0.087388, 10.122678, 0 }, + { -0.234632, 0.069432, 10.111904, 0 }, + { -0.252588, 0.065841, 10.121481, 0 }, + { -0.245406, 0.071826, 10.128663, 0 }, + { -0.243011, 0.075417, 10.129861, 0 }, + { -0.238223, 0.068235, 10.139438, 0 }, + { -0.256179, 0.076614, 10.126269, 0 }, + { -0.246603, 0.083797, 10.131058, 0 }, + { -0.248997, 0.080206, 10.116693, 0 }, + { -0.241814, 0.082600, 10.123875, 0 }, + { -0.262165, 0.075417, 10.113101, 0 }, + { -0.240617, 0.079009, 10.134649, 0 }, + { -0.244208, 0.077812, 10.121481, 0 }, + { -0.246603, 0.068235, 10.141831, 0 }, + { -0.252588, 0.075417, 10.120284, 0 }, + { -0.247800, 0.084994, 10.104721, 0 }, + { -0.241814, 0.086191, 10.126269, 0 }, + { -0.237026, 0.082600, 10.117889, 0 }, + { -0.243011, 0.070629, 10.117889, 0 }, + { -0.239420, 0.070629, 10.135846, 0 }, + { -0.237026, 0.065841, 10.120284, 0 }, + { -0.237026, 0.061052, 10.125072, 0 }, + { -0.235829, 0.061052, 10.114298, 0 }, + { -0.252588, 0.074220, 10.137043, 0 }, + { -0.253785, 0.086191, 10.119086, 0 }, + { -0.252588, 0.089783, 10.129861, 0 }, + { -0.245406, 0.084994, 10.126269, 0 }, + { -0.232237, 0.076614, 10.120284, 0 }, + { -0.252588, 0.082600, 10.119086, 0 }, + { -0.251391, 0.064643, 10.132255, 0 }, + { -0.227449, 0.076614, 10.149014, 0 }, + { -0.259771, 0.083797, 10.131058, 0 }, + { -0.248997, 0.075417, 10.127466, 0 }, + { -0.244208, 0.071826, 10.133451, 0 }, + { -0.243011, 0.070629, 10.132255, 0 }, + { -0.228646, 0.076614, 10.128663, 0 }, + { -0.241814, 0.089783, 10.138240, 0 }, + { -0.252588, 0.086191, 10.122678, 0 }, + { -0.254982, 0.068235, 10.133451, 0 }, + { -0.250194, 0.071826, 10.150211, 0 }, + { -0.235829, 0.084994, 10.140635, 0 }, + { -0.234632, 0.087388, 10.139438, 0 }, + { -0.245406, 0.077812, 10.105919, 0 }, + { -0.250194, 0.080206, 10.107116, 0 }, + { -0.240617, 0.092177, 10.132255, 0 }, + { -0.243011, 0.077812, 10.133451, 0 }, + { -0.248997, 0.062249, 10.128663, 0 }, + { -0.245406, 0.068235, 10.125072, 0 }, + { -0.250194, 0.064643, 10.129861, 0 }, + { -0.248997, 0.082600, 10.126269, 0 }, + { -0.252588, 0.073023, 10.141831, 0 }, + { -0.250194, 0.076614, 10.127466, 0 }, + { -0.251391, 0.077812, 10.121481, 0 }, + { -0.250194, 0.069432, 10.134649, 0 }, + { -0.232237, 0.065841, 10.131058, 0 }, + { -0.233435, 0.081403, 10.131058, 0 }, + { -0.241814, 0.074220, 10.111904, 0 }, + { -0.248997, 0.064643, 10.135846, 0 }, + { -0.239420, 0.081403, 10.143028, 0 }, + { -0.239420, 0.077812, 10.138240, 0 }, + { -0.237026, 0.074220, 10.110707, 0 }, + { -0.235829, 0.081403, 10.121481, 0 }, + { -0.247800, 0.063446, 10.129861, 0 }, + { -0.235829, 0.068235, 10.121481, 0 }, + { -0.238223, 0.064643, 10.123875, 0 }, + { -0.246603, 0.070629, 10.132255, 0 }, + { -0.264559, 0.073023, 10.145423, 0 }, + { -0.247800, 0.065841, 10.116693, 0 }, + { -0.247800, 0.084994, 10.125072, 0 }, + { -0.225055, 0.080206, 10.115496, 0 }, + { -0.233435, 0.064643, 10.135846, 0 }, + { -0.247800, 0.069432, 10.131058, 0 }, + { -0.234632, 0.081403, 10.125072, 0 }, + { -0.246603, 0.081403, 10.128663, 0 }, + { -0.235829, 0.086191, 10.117889, 0 }, + { -0.233435, 0.077812, 10.122678, 0 }, + { -0.256179, 0.049081, 10.128663, 0 }, + { -0.243011, 0.083797, 10.138240, 0 }, + { -0.239420, 0.087388, 10.129861, 0 }, + { -0.238223, 0.068235, 10.131058, 0 }, + { -0.234632, 0.068235, 10.129861, 0 }, + { -0.250194, 0.080206, 10.135846, 0 }, + { -0.246603, 0.062249, 10.131058, 0 }, + { -0.243011, 0.076614, 10.134649, 0 }, + { -0.246603, 0.093374, 10.128663, 0 }, + { -0.251391, 0.065841, 10.126269, 0 }, + { -0.235829, 0.069432, 10.135846, 0 }, + { -0.243011, 0.081403, 10.120284, 0 }, + { -0.245406, 0.086191, 10.129861, 0 }, + { -0.234632, 0.073023, 10.110707, 0 }, + { -0.244208, 0.083797, 10.140635, 0 }, + { -0.247800, 0.069432, 10.141831, 0 }, + { -0.240617, 0.076614, 10.149014, 0 }, + { -0.243011, 0.081403, 10.122678, 0 }, + { -0.237026, 0.071826, 10.120284, 0 }, + { -0.234632, 0.073023, 10.120284, 0 }, + { -0.237026, 0.077812, 10.131058, 0 }, + { -0.244208, 0.080206, 10.152605, 0 }, + { -0.250194, 0.076614, 10.135846, 0 }, + { -0.253785, 0.069432, 10.131058, 0 }, + { -0.260968, 0.073023, 10.141831, 0 }, + { -0.247800, 0.070629, 10.134649, 0 }, + { -0.257377, 0.068235, 10.125072, 0 }, + { -0.243011, 0.073023, 10.121481, 0 }, + { -0.235829, 0.082600, 10.127466, 0 }, + { -0.237026, 0.070629, 10.139438, 0 }, + { -0.227449, 0.081403, 10.127466, 0 }, + { -0.239420, 0.080206, 10.141831, 0 }, + { -0.251391, 0.069432, 10.129861, 0 }, + { -0.238223, 0.069432, 10.121481, 0 }, + { -0.237026, 0.069432, 10.126269, 0 }, + { -0.250194, 0.077812, 10.114298, 0 }, + { -0.237026, 0.094571, 10.116693, 0 }, + { -0.253785, 0.084994, 10.143028, 0 }, + { -0.263362, 0.071826, 10.123875, 0 }, + { -0.246603, 0.064643, 10.126269, 0 }, + { -0.240617, 0.059855, 10.131058, 0 }, + { -0.247800, 0.070629, 10.139438, 0 }, + { -0.240617, 0.082600, 10.132255, 0 }, + { -0.234632, 0.073023, 10.111904, 0 }, + { -0.240617, 0.062249, 10.131058, 0 }, + { -0.238223, 0.080206, 10.129861, 0 }, + { -0.243011, 0.076614, 10.123875, 0 }, + { -0.246603, 0.080206, 10.125072, 0 }, + { -0.235829, 0.079009, 10.127466, 0 }, + { -0.243011, 0.076614, 10.110707, 0 }, + { -0.246603, 0.065841, 10.128663, 0 }, + { -0.246603, 0.076614, 10.133451, 0 }, + { -0.253785, 0.080206, 10.123875, 0 }, + { -0.241814, 0.073023, 10.119086, 0 }, + { -0.250194, 0.075417, 10.120284, 0 }, + { -0.235829, 0.079009, 10.143028, 0 }, + { -0.241814, 0.071826, 10.135846, 0 }, + { -0.254982, 0.077812, 10.125072, 0 }, + { -0.238223, 0.077812, 10.122678, 0 }, + { -0.235829, 0.071826, 10.132255, 0 }, + { -0.238223, 0.084994, 10.120284, 0 }, + { -0.253785, 0.075417, 10.146620, 0 }, + { -0.254982, 0.069432, 10.141831, 0 }, + { -0.240617, 0.087388, 10.126269, 0 }, + { -0.251391, 0.088585, 10.115496, 0 }, + { -0.256179, 0.065841, 10.129861, 0 }, + { -0.243011, 0.069432, 10.127466, 0 }, + { -0.246603, 0.063446, 10.134649, 0 }, + { -0.246603, 0.073023, 10.128663, 0 }, + { -0.240617, 0.068235, 10.119086, 0 }, + { -0.257377, 0.069432, 10.143028, 0 }, + { -0.245406, 0.081403, 10.128663, 0 }, + { -0.252588, 0.075417, 10.120284, 0 }, + { -0.241814, 0.068235, 10.111904, 0 }, + { -0.238223, 0.075417, 10.141831, 0 }, + { -0.240617, 0.071826, 10.111904, 0 }, + { -0.247800, 0.067038, 10.126269, 0 }, + { -0.247800, 0.068235, 10.134649, 0 }, + { -0.238223, 0.084994, 10.139438, 0 }, + { -0.237026, 0.090980, 10.141831, 0 }, + { -0.245406, 0.068235, 10.109509, 0 }, + { -0.256179, 0.076614, 10.143028, 0 }, + { -0.237026, 0.080206, 10.116693, 0 }, + { -0.228646, 0.079009, 10.134649, 0 }, + { -0.247800, 0.071826, 10.121481, 0 }, + { -0.241814, 0.075417, 10.129861, 0 }, + { -0.228646, 0.076614, 10.152605, 0 }, + { -0.238223, 0.087388, 10.125072, 0 }, + { -0.239420, 0.075417, 10.128663, 0 }, + { -0.247800, 0.074220, 10.114298, 0 }, + { -0.219069, 0.080206, 10.126269, 0 }, + { -0.234632, 0.082600, 10.109509, 0 }, + { -0.244208, 0.063446, 10.127466, 0 }, + { -0.247800, 0.068235, 10.134649, 0 }, + { -0.245406, 0.069432, 10.139438, 0 }, + { -0.251391, 0.086191, 10.128663, 0 }, + { -0.244208, 0.065841, 10.127466, 0 }, + { -0.246603, 0.070629, 10.125072, 0 }, + { -0.240617, 0.081403, 10.125072, 0 }, + { -0.232237, 0.063446, 10.141831, 0 }, + { -0.247800, 0.065841, 10.126269, 0 }, + { -0.235829, 0.086191, 10.133451, 0 }, + { -0.245406, 0.096965, 10.121481, 0 }, + { -0.239420, 0.090980, 10.121481, 0 }, + { -0.248997, 0.077812, 10.125072, 0 }, + { -0.231040, 0.067038, 10.126269, 0 }, + { -0.245406, 0.081403, 10.125072, 0 }, + { -0.231040, 0.074220, 10.145423, 0 }, + { -0.253785, 0.067038, 10.115496, 0 }, + { -0.246603, 0.065841, 10.110707, 0 }, + { -0.245406, 0.069432, 10.131058, 0 }, + { -0.232237, 0.076614, 10.113101, 0 }, + { -0.243011, 0.075417, 10.121481, 0 }, + { -0.243011, 0.079009, 10.132255, 0 }, + { -0.238223, 0.079009, 10.123875, 0 }, + { -0.245406, 0.069432, 10.122678, 0 }, + { -0.247800, 0.075417, 10.126269, 0 }, + { -0.239420, 0.079009, 10.139438, 0 }, + { -0.244208, 0.083797, 10.105919, 0 }, + { -0.245406, 0.071826, 10.109509, 0 }, + { -0.233435, 0.076614, 10.128663, 0 }, + { -0.243011, 0.088585, 10.131058, 0 }, + { -0.252588, 0.069432, 10.117889, 0 }, + { -0.248997, 0.090980, 10.119086, 0 }, + { -0.241814, 0.074220, 10.129861, 0 }, + { -0.253785, 0.068235, 10.135846, 0 }, + { -0.240617, 0.074220, 10.125072, 0 }, + { -0.246603, 0.076614, 10.131058, 0 }, + { -0.238223, 0.081403, 10.117889, 0 }, + { -0.246603, 0.074220, 10.127466, 0 }, + { -0.250194, 0.070629, 10.133451, 0 }, + { -0.248997, 0.073023, 10.132255, 0 }, + { -0.250194, 0.077812, 10.122678, 0 }, + { -0.259771, 0.077812, 10.123875, 0 }, + { -0.234632, 0.079009, 10.123875, 0 }, + { -0.241814, 0.073023, 10.120284, 0 }, + { -0.251391, 0.063446, 10.146620, 0 }, + { -0.250194, 0.074220, 10.113101, 0 }, + { -0.256179, 0.082600, 10.119086, 0 }, + { -0.257377, 0.080206, 10.132255, 0 }, + { -0.245406, 0.090980, 10.127466, 0 }, + { -0.243011, 0.075417, 10.133451, 0 }, + { -0.239420, 0.088585, 10.125072, 0 }, + { -0.241814, 0.079009, 10.127466, 0 }, + { -0.251391, 0.070629, 10.137043, 0 }, + { -0.235829, 0.081403, 10.110707, 0 }, + { -0.248997, 0.075417, 10.141831, 0 }, + { -0.231040, 0.087388, 10.125072, 0 }, + { -0.247800, 0.068235, 10.127466, 0 }, + { -0.252588, 0.086191, 10.119086, 0 }, + { -0.240617, 0.071826, 10.127466, 0 }, + { -0.243011, 0.081403, 10.144226, 0 }, + { -0.243011, 0.083797, 10.126269, 0 }, + { -0.251391, 0.074220, 10.127466, 0 }, + { -0.239420, 0.084994, 10.125072, 0 }, + { -0.231040, 0.069432, 10.113101, 0 }, + { -0.246603, 0.069432, 10.138240, 0 }, + { -0.243011, 0.075417, 10.132255, 0 }, + { -0.243011, 0.084994, 10.113101, 0 }, + { -0.253785, 0.082600, 10.120284, 0 }, + { -0.247800, 0.070629, 10.125072, 0 }, + { -0.244208, 0.079009, 10.113101, 0 }, + { -0.260968, 0.073023, 10.127466, 0 }, + { -0.239420, 0.063446, 10.128663, 0 }, + { -0.234632, 0.082600, 10.122678, 0 }, + { -0.240617, 0.079009, 10.132255, 0 }, + { -0.251391, 0.069432, 10.133451, 0 }, + { -0.252588, 0.073023, 10.131058, 0 }, + { -0.239420, 0.059855, 10.121481, 0 }, + { -0.238223, 0.079009, 10.122678, 0 }, + { -0.229843, 0.070629, 10.115496, 0 }, + { -0.246603, 0.074220, 10.128663, 0 }, + { -0.235829, 0.079009, 10.121481, 0 }, + { -0.237026, 0.076614, 10.146620, 0 }, + { -0.244208, 0.077812, 10.117889, 0 }, + { -0.258574, 0.070629, 10.133451, 0 }, + { -0.259771, 0.077812, 10.119086, 0 }, + { -0.246603, 0.083797, 10.133451, 0 }, + { -0.241814, 0.076614, 10.127466, 0 }, + { -0.253785, 0.077812, 10.116693, 0 }, + { -0.256179, 0.075417, 10.123875, 0 }, + { -0.254982, 0.074220, 10.120284, 0 }, + { -0.252588, 0.070629, 10.114298, 0 }, + { -0.256179, 0.074220, 10.128663, 0 }, + { -0.237026, 0.071826, 10.139438, 0 }, + { -0.235829, 0.069432, 10.108313, 0 }, + { -0.250194, 0.074220, 10.116693, 0 }, + { -0.241814, 0.073023, 10.131058, 0 }, + { -0.234632, 0.075417, 10.147817, 0 }, + { -0.238223, 0.067038, 10.111904, 0 }, + { -0.251391, 0.071826, 10.128663, 0 }, + { -0.239420, 0.087388, 10.134649, 0 }, + { -0.237026, 0.082600, 10.128663, 0 }, + { -0.240617, 0.089783, 10.133451, 0 }, + { -0.245406, 0.081403, 10.119086, 0 }, + { -0.241814, 0.080206, 10.128663, 0 }, + { -0.235829, 0.062249, 10.140635, 0 }, + { -0.235829, 0.065841, 10.128663, 0 }, + { -0.237026, 0.092177, 10.128663, 0 }, + { -0.244208, 0.082600, 10.122678, 0 }, + { -0.247800, 0.065841, 10.127466, 0 }, + { -0.243011, 0.070629, 10.113101, 0 }, + { -0.238223, 0.068235, 10.123875, 0 }, + { -0.241814, 0.077812, 10.107116, 0 }, + { -0.238223, 0.088585, 10.132255, 0 }, + { -0.234632, 0.067038, 10.127466, 0 }, + { -0.243011, 0.075417, 10.117889, 0 }, + { -0.240617, 0.077812, 10.132255, 0 }, + { -0.240617, 0.079009, 10.120284, 0 }, + { -0.239420, 0.074220, 10.125072, 0 }, + { -0.233435, 0.071826, 10.132255, 0 }, + { -0.241814, 0.083797, 10.126269, 0 }, + { -0.258574, 0.089783, 10.127466, 0 }, + { -0.234632, 0.081403, 10.131058, 0 }, + { -0.252588, 0.071826, 10.137043, 0 }, + { -0.240617, 0.064643, 10.127466, 0 }, + { -0.248997, 0.070629, 10.133451, 0 }, + { -0.246603, 0.087388, 10.132255, 0 }, + { -0.250194, 0.075417, 10.132255, 0 }, + { -0.244208, 0.073023, 10.126269, 0 }, + { -0.241814, 0.079009, 10.120284, 0 }, + { -0.251391, 0.083797, 10.128663, 0 }, + { -0.234632, 0.080206, 10.145423, 0 }, + { -0.250194, 0.074220, 10.140635, 0 }, + { -0.247800, 0.062249, 10.116693, 0 }, + { -0.243011, 0.077812, 10.125072, 0 }, + { -0.247800, 0.064643, 10.126269, 0 }, + { -0.244208, 0.071826, 10.145423, 0 }, + { -0.253785, 0.070629, 10.123875, 0 }, + { -0.237026, 0.077812, 10.133451, 0 }, + { -0.246603, 0.082600, 10.117889, 0 }, + { -0.245406, 0.086191, 10.121481, 0 }, + { -0.235829, 0.073023, 10.117889, 0 }, + { -0.243011, 0.075417, 10.134649, 0 }, + { -0.239420, 0.087388, 10.139438, 0 }, + { -0.227449, 0.084994, 10.135846, 0 }, + { -0.240617, 0.083797, 10.133451, 0 }, + { -0.243011, 0.073023, 10.117889, 0 }, + { -0.228646, 0.082600, 10.144226, 0 }, + { -0.240617, 0.068235, 10.104721, 0 }, + { -0.241814, 0.059855, 10.127466, 0 }, + { -0.243011, 0.081403, 10.116693, 0 }, + { -0.238223, 0.080206, 10.147817, 0 }, + { -0.244208, 0.076614, 10.119086, 0 }, + { -0.241814, 0.073023, 10.119086, 0 }, + { -0.251391, 0.075417, 10.131058, 0 }, + { -0.244208, 0.071826, 10.127466, 0 }, + { -0.233435, 0.082600, 10.146620, 0 }, + { -0.250194, 0.070629, 10.120284, 0 }, + { -0.248997, 0.067038, 10.135846, 0 }, + { -0.233435, 0.077812, 10.109509, 0 }, + { -0.243011, 0.083797, 10.133451, 0 }, + { -0.251391, 0.069432, 10.111904, 0 }, + { -0.234632, 0.076614, 10.138240, 0 }, + { -0.241814, 0.086191, 10.120284, 0 }, + { -0.239420, 0.068235, 10.128663, 0 }, + { -0.229843, 0.071826, 10.140635, 0 }, + { -0.245406, 0.082600, 10.115496, 0 }, + { -0.234632, 0.076614, 10.143028, 0 }, + { -0.246603, 0.068235, 10.119086, 0 }, + { -0.250194, 0.064643, 10.132255, 0 }, + { -0.237026, 0.082600, 10.129861, 0 }, + { -0.256179, 0.089783, 10.138240, 0 }, + { -0.239420, 0.076614, 10.121481, 0 }, + { -0.238223, 0.069432, 10.133451, 0 }, + { -0.247800, 0.067038, 10.135846, 0 }, + { -0.250194, 0.070629, 10.131058, 0 }, + { -0.243011, 0.080206, 10.141831, 0 }, + { -0.244208, 0.064643, 10.122678, 0 }, + { -0.238223, 0.070629, 10.134649, 0 }, + { -0.229843, 0.070629, 10.113101, 0 }, + { -0.254982, 0.087388, 10.137043, 0 }, + { -0.259771, 0.081403, 10.128663, 0 }, + { -0.241814, 0.074220, 10.129861, 0 }, + { -0.247800, 0.065841, 10.126269, 0 }, + { -0.253785, 0.063446, 10.122678, 0 }, + { -0.256179, 0.076614, 10.129861, 0 }, + { -0.250194, 0.083797, 10.123875, 0 }, + { -0.239420, 0.073023, 10.129861, 0 }, + { -0.253785, 0.084994, 10.109509, 0 }, + { -0.238223, 0.071826, 10.151408, 0 }, + { -0.245406, 0.068235, 10.110707, 0 }, + { -0.246603, 0.064643, 10.127466, 0 }, + { -0.232237, 0.077812, 10.113101, 0 }, + { -0.247800, 0.064643, 10.132255, 0 }, + { -0.254982, 0.080206, 10.137043, 0 }, + { -0.248997, 0.080206, 10.138240, 0 }, + { -0.243011, 0.081403, 10.123875, 0 }, + { -0.237026, 0.087388, 10.127466, 0 }, + { -0.234632, 0.070629, 10.129861, 0 }, + { -0.235829, 0.073023, 10.121481, 0 }, + { -0.244208, 0.073023, 10.127466, 0 }, + { -0.237026, 0.067038, 10.138240, 0 }, + { -0.248997, 0.067038, 10.119086, 0 }, + { -0.253785, 0.079009, 10.129861, 0 }, + { -0.239420, 0.068235, 10.129861, 0 }, + { -0.252588, 0.071826, 10.122678, 0 }, + { -0.243011, 0.076614, 10.134649, 0 }, + { -0.234632, 0.075417, 10.117889, 0 }, + { -0.235829, 0.070629, 10.115496, 0 }, + { -0.247800, 0.083797, 10.123875, 0 }, + { -0.241814, 0.089783, 10.123875, 0 }, + { -0.234632, 0.087388, 10.133451, 0 }, + { -0.239420, 0.073023, 10.116693, 0 }, + { -0.241814, 0.087388, 10.122678, 0 }, + { -0.243011, 0.077812, 10.126269, 0 }, + { -0.247800, 0.076614, 10.129861, 0 }, + { -0.244208, 0.082600, 10.140635, 0 }, + { -0.241814, 0.079009, 10.150211, 0 }, + { -0.237026, 0.065841, 10.144226, 0 }, + { -0.234632, 0.081403, 10.133451, 0 }, + { -0.231040, 0.081403, 10.121481, 0 }, + { -0.248997, 0.071826, 10.143028, 0 }, + { -0.257377, 0.063446, 10.119086, 0 }, + { -0.245406, 0.087388, 10.141831, 0 }, + { -0.246603, 0.082600, 10.137043, 0 }, + { -0.227449, 0.080206, 10.128663, 0 }, + { -0.244208, 0.082600, 10.120284, 0 }, + { -0.245406, 0.087388, 10.139438, 0 }, + { -0.237026, 0.061052, 10.137043, 0 }, + { -0.240617, 0.061052, 10.132255, 0 }, + { -0.239420, 0.076614, 10.132255, 0 }, + { -0.244208, 0.083797, 10.131058, 0 }, + { -0.227449, 0.077812, 10.137043, 0 }, + { -0.240617, 0.089783, 10.144226, 0 }, + { -0.238223, 0.083797, 10.121481, 0 }, + { -0.260968, 0.068235, 10.119086, 0 }, + { -0.243011, 0.070629, 10.155000, 0 }, + { -0.248997, 0.079009, 10.117889, 0 }, + { -0.252588, 0.076614, 10.111904, 0 }, + { -0.237026, 0.084994, 10.134649, 0 }, + { -0.248997, 0.069432, 10.128663, 0 }, + { -0.235829, 0.082600, 10.126269, 0 }, + { -0.245406, 0.069432, 10.150211, 0 }, + { -0.253785, 0.090980, 10.125072, 0 }, + { -0.247800, 0.077812, 10.119086, 0 }, + { -0.248997, 0.074220, 10.117889, 0 }, + { -0.239420, 0.080206, 10.122678, 0 }, + { -0.239420, 0.087388, 10.127466, 0 }, + { -0.244208, 0.074220, 10.128663, 0 }, + { -0.229843, 0.068235, 10.123875, 0 }, + { -0.247800, 0.080206, 10.127466, 0 }, + { -0.241814, 0.071826, 10.119086, 0 }, + { -0.235829, 0.086191, 10.121481, 0 }, + { -0.234632, 0.084994, 10.127466, 0 }, + { -0.237026, 0.073023, 10.131058, 0 }, + { -0.243011, 0.074220, 10.123875, 0 }, + { -0.259771, 0.084994, 10.146620, 0 }, + { -0.241814, 0.071826, 10.122678, 0 }, + { -0.232237, 0.077812, 10.132255, 0 }, + { -0.239420, 0.076614, 10.133451, 0 }, + { -0.244208, 0.076614, 10.128663, 0 }, + { -0.241814, 0.081403, 10.153803, 0 }, + { -0.246603, 0.069432, 10.114298, 0 }, + { -0.247800, 0.067038, 10.128663, 0 }, + { -0.239420, 0.077812, 10.132255, 0 }, + { -0.248997, 0.064643, 10.133451, 0 }, + { -0.231040, 0.075417, 10.120284, 0 }, + { -0.235829, 0.070629, 10.109509, 0 }, + { -0.248997, 0.079009, 10.121481, 0 }, + { -0.239420, 0.094571, 10.128663, 0 }, + { -0.254982, 0.083797, 10.134649, 0 }, + { -0.240617, 0.079009, 10.117889, 0 }, + { -0.244208, 0.065841, 10.122678, 0 }, + { -0.238223, 0.070629, 10.116693, 0 }, + { -0.244208, 0.081403, 10.131058, 0 }, + { -0.239420, 0.071826, 10.135846, 0 }, + { -0.231040, 0.070629, 10.139438, 0 }, + { -0.240617, 0.070629, 10.125072, 0 }, + { -0.235829, 0.079009, 10.127466, 0 }, + { -0.235829, 0.077812, 10.126269, 0 }, + { -0.241814, 0.071826, 10.127466, 0 }, + { -0.243011, 0.068235, 10.131058, 0 }, + { -0.240617, 0.076614, 10.129861, 0 }, + { -0.231040, 0.070629, 10.127466, 0 }, + { -0.229843, 0.076614, 10.129861, 0 }, + { -0.235829, 0.071826, 10.128663, 0 }, + { -0.235829, 0.068235, 10.131058, 0 }, + { -0.246603, 0.074220, 10.122678, 0 }, + { -0.232237, 0.075417, 10.126269, 0 }, + { -0.233435, 0.075417, 10.116693, 0 }, + { -0.227449, 0.069432, 10.131058, 0 }, + { -0.233435, 0.069432, 10.133451, 0 }, + { -0.243011, 0.076614, 10.125072, 0 }, + { -0.243011, 0.079009, 10.111904, 0 }, + { -0.245406, 0.080206, 10.137043, 0 }, + { -0.244208, 0.083797, 10.133451, 0 }, + { -0.247800, 0.071826, 10.131058, 0 }, + { -0.239420, 0.063446, 10.114298, 0 }, + { -0.234632, 0.070629, 10.119086, 0 }, + { -0.238223, 0.070629, 10.151408, 0 }, + { -0.247800, 0.075417, 10.134649, 0 }, + { -0.241814, 0.075417, 10.137043, 0 }, + { -0.240617, 0.067038, 10.121481, 0 }, + { -0.243011, 0.063446, 10.137043, 0 }, + { -0.229843, 0.068235, 10.132255, 0 }, + { -0.241814, 0.075417, 10.122678, 0 }, + { -0.246603, 0.086191, 10.119086, 0 }, + { -0.235829, 0.081403, 10.126269, 0 }, + { -0.229843, 0.081403, 10.138240, 0 }, + { -0.234632, 0.075417, 10.120284, 0 }, + { -0.237026, 0.080206, 10.133451, 0 }, + { -0.232237, 0.074220, 10.114298, 0 }, + { -0.245406, 0.069432, 10.128663, 0 }, + { -0.241814, 0.064643, 10.134649, 0 }, + { -0.239420, 0.086191, 10.133451, 0 }, + { -0.238223, 0.086191, 10.144226, 0 }, + { -0.248997, 0.063446, 10.131058, 0 }, + { -0.229843, 0.065841, 10.137043, 0 }, + { -0.239420, 0.084994, 10.110707, 0 }, + { -0.231040, 0.083797, 10.141831, 0 }, + { -0.245406, 0.073023, 10.128663, 0 }, + { -0.245406, 0.071826, 10.129861, 0 }, + { -0.238223, 0.071826, 10.120284, 0 }, + { -0.247800, 0.081403, 10.137043, 0 }, + { -0.264559, 0.069432, 10.135846, 0 }, + { -0.247800, 0.070629, 10.131058, 0 }, + { -0.240617, 0.082600, 10.134649, 0 }, + { -0.246603, 0.075417, 10.126269, 0 }, + { -0.238223, 0.071826, 10.152605, 0 }, + { -0.235829, 0.063446, 10.132255, 0 }, + { -0.251391, 0.065841, 10.120284, 0 }, + { -0.243011, 0.068235, 10.131058, 0 }, + { -0.222661, 0.067038, 10.134649, 0 }, + { -0.239420, 0.081403, 10.128663, 0 }, + { -0.240617, 0.083797, 10.138240, 0 }, + { -0.223858, 0.068235, 10.122678, 0 }, + { -0.238223, 0.065841, 10.140635, 0 }, + { -0.237026, 0.081403, 10.134649, 0 }, + { -0.240617, 0.079009, 10.123875, 0 }, + { -0.238223, 0.073023, 10.133451, 0 }, + { -0.246603, 0.067038, 10.117889, 0 }, + { -0.243011, 0.061052, 10.135846, 0 }, + { -0.239420, 0.075417, 10.116693, 0 }, + { -0.260968, 0.065841, 10.123875, 0 }, + { -0.247800, 0.064643, 10.117889, 0 }, + { -0.248997, 0.093374, 10.140635, 0 }, + { -0.244208, 0.080206, 10.144226, 0 }, + { -0.258574, 0.077812, 10.113101, 0 }, + { -0.250194, 0.069432, 10.126269, 0 }, + { -0.238223, 0.073023, 10.102327, 0 }, + { -0.240617, 0.070629, 10.135846, 0 }, + { -0.247800, 0.063446, 10.121481, 0 }, + { -0.268150, 0.088585, 10.135846, 0 }, + { -0.246603, 0.075417, 10.119086, 0 }, + { -0.233435, 0.071826, 10.131058, 0 }, + { -0.245406, 0.071826, 10.128663, 0 }, + { -0.244208, 0.094571, 10.128663, 0 }, + { -0.234632, 0.080206, 10.123875, 0 }, + { -0.240617, 0.081403, 10.109509, 0 }, + { -0.240617, 0.069432, 10.128663, 0 }, + { -0.237026, 0.069432, 10.122678, 0 }, + { -0.234632, 0.071826, 10.137043, 0 }, + { -0.239420, 0.076614, 10.139438, 0 }, + { -0.244208, 0.088585, 10.117889, 0 }, + { -0.259771, 0.087388, 10.134649, 0 }, + { -0.252588, 0.077812, 10.134649, 0 }, + { -0.241814, 0.073023, 10.117889, 0 }, + { -0.243011, 0.080206, 10.128663, 0 }, + { -0.241814, 0.086191, 10.119086, 0 }, + { -0.244208, 0.073023, 10.115496, 0 }, + { -0.239420, 0.080206, 10.123875, 0 }, + { -0.248997, 0.070629, 10.137043, 0 }, + { -0.240617, 0.076614, 10.119086, 0 }, + { -0.233435, 0.070629, 10.128663, 0 }, + { -0.235829, 0.075417, 10.121481, 0 }, + { -0.240617, 0.090980, 10.127466, 0 }, + { -0.252588, 0.067038, 10.114298, 0 }, + { -0.229843, 0.077812, 10.123875, 0 }, + { -0.248997, 0.084994, 10.137043, 0 }, + { -0.245406, 0.070629, 10.110707, 0 }, + { -0.239420, 0.061052, 10.131058, 0 }, + { -0.241814, 0.077812, 10.132255, 0 }, + { -0.239420, 0.081403, 10.126269, 0 }, + { -0.235829, 0.069432, 10.127466, 0 }, + { -0.243011, 0.076614, 10.134649, 0 }, + { -0.252588, 0.077812, 10.132255, 0 }, + { -0.237026, 0.077812, 10.138240, 0 }, + { -0.246603, 0.073023, 10.127466, 0 }, + { -0.241814, 0.063446, 10.129861, 0 }, + { -0.234632, 0.071826, 10.126269, 0 }, + { -0.248997, 0.081403, 10.113101, 0 }, + { -0.244208, 0.084994, 10.114298, 0 }, + { -0.232237, 0.077812, 10.132255, 0 }, + { -0.234632, 0.084994, 10.128663, 0 }, + { -0.244208, 0.088585, 10.108313, 0 }, + { -0.253785, 0.070629, 10.141831, 0 }, + { -0.247800, 0.071826, 10.121481, 0 }, + { -0.244208, 0.070629, 10.128663, 0 }, + { -0.244208, 0.079009, 10.116693, 0 }, + { -0.239420, 0.074220, 10.113101, 0 }, + { -0.239420, 0.079009, 10.127466, 0 }, + { -0.251391, 0.071826, 10.133451, 0 }, + { -0.247800, 0.076614, 10.133451, 0 }, + { -0.254982, 0.088585, 10.137043, 0 }, + { -0.250194, 0.081403, 10.137043, 0 }, + { -0.257377, 0.077812, 10.117889, 0 }, + { -0.237026, 0.079009, 10.123875, 0 }, + { -0.235829, 0.073023, 10.121481, 0 }, + { -0.262165, 0.082600, 10.123875, 0 }, + { -0.248997, 0.073023, 10.113101, 0 }, + { -0.241814, 0.076614, 10.114298, 0 }, + { -0.251391, 0.073023, 10.131058, 0 }, + { -0.248997, 0.075417, 10.141831, 0 }, + { -0.237026, 0.074220, 10.132255, 0 }, + { -0.253785, 0.084994, 10.122678, 0 }, + { -0.247800, 0.079009, 10.133451, 0 }, + { -0.246603, 0.082600, 10.109509, 0 }, + { -0.252588, 0.094571, 10.122678, 0 }, + { -0.246603, 0.073023, 10.125072, 0 }, + { -0.250194, 0.057461, 10.115496, 0 }, + { -0.250194, 0.071826, 10.122678, 0 }, + { -0.251391, 0.076614, 10.127466, 0 }, + { -0.240617, 0.079009, 10.126269, 0 }, + { -0.259771, 0.073023, 10.115496, 0 }, + { -0.246603, 0.074220, 10.135846, 0 }, + { -0.253785, 0.077812, 10.119086, 0 }, + { -0.244208, 0.077812, 10.128663, 0 }, + { -0.241814, 0.069432, 10.128663, 0 }, + { -0.244208, 0.081403, 10.126269, 0 }, + { -0.246603, 0.086191, 10.128663, 0 }, + { -0.252588, 0.084994, 10.132255, 0 }, + { -0.247800, 0.076614, 10.128663, 0 }, + { -0.240617, 0.063446, 10.126269, 0 }, + { -0.235829, 0.069432, 10.127466, 0 }, + { -0.240617, 0.087388, 10.129861, 0 }, + { -0.251391, 0.063446, 10.128663, 0 }, + { -0.252588, 0.077812, 10.135846, 0 }, + { -0.254982, 0.082600, 10.138240, 0 }, + { -0.244208, 0.081403, 10.128663, 0 }, + { -0.241814, 0.086191, 10.117889, 0 }, + { -0.254982, 0.069432, 10.149014, 0 }, + { -0.248997, 0.068235, 10.131058, 0 }, + { -0.252588, 0.063446, 10.122678, 0 }, + { -0.240617, 0.079009, 10.152605, 0 }, + { -0.240617, 0.088585, 10.107116, 0 }, + { -0.248997, 0.076614, 10.138240, 0 }, + { -0.251391, 0.075417, 10.119086, 0 }, + { -0.225055, 0.079009, 10.138240, 0 }, + { -0.239420, 0.077812, 10.150211, 0 }, + { -0.250194, 0.055067, 10.137043, 0 }, + { -0.257377, 0.082600, 10.125072, 0 }, + { -0.243011, 0.075417, 10.119086, 0 }, + { -0.244208, 0.064643, 10.119086, 0 }, + { -0.246603, 0.080206, 10.117889, 0 }, + { -0.232237, 0.079009, 10.158591, 0 }, + { -0.247800, 0.071826, 10.120284, 0 }, + { -0.245406, 0.075417, 10.137043, 0 }, + { -0.240617, 0.069432, 10.117889, 0 }, + { -0.246603, 0.080206, 10.134649, 0 }, + { -0.248997, 0.087388, 10.109509, 0 }, + { -0.252588, 0.081403, 10.132255, 0 }, + { -0.250194, 0.069432, 10.123875, 0 }, + { -0.257377, 0.073023, 10.131058, 0 }, + { -0.241814, 0.068235, 10.109509, 0 }, + { -0.243011, 0.080206, 10.108313, 0 }, + { -0.238223, 0.074220, 10.139438, 0 }, + { -0.245406, 0.075417, 10.122678, 0 }, + { -0.250194, 0.069432, 10.137043, 0 }, + { -0.245406, 0.069432, 10.116693, 0 }, + { -0.235829, 0.070629, 10.158591, 0 }, + { -0.247800, 0.082600, 10.117889, 0 }, + { -0.247800, 0.077812, 10.137043, 0 }, + { -0.243011, 0.080206, 10.134649, 0 }, + { -0.263362, 0.081403, 10.110707, 0 }, + { -0.247800, 0.079009, 10.127466, 0 }, + { -0.248997, 0.071826, 10.131058, 0 }, + { -0.248997, 0.075417, 10.144226, 0 }, + { -0.239420, 0.077812, 10.117889, 0 }, + { -0.248997, 0.071826, 10.139438, 0 }, + { -0.254982, 0.083797, 10.120284, 0 }, + { -0.238223, 0.075417, 10.131058, 0 }, + { -0.235829, 0.084994, 10.105919, 0 }, + { -0.245406, 0.080206, 10.133451, 0 }, + { -0.247800, 0.075417, 10.131058, 0 }, + { -0.235829, 0.079009, 10.120284, 0 }, + { -0.247800, 0.070629, 10.133451, 0 }, + { -0.253785, 0.064643, 10.110707, 0 }, + { -0.240617, 0.071826, 10.120284, 0 }, + { -0.248997, 0.079009, 10.101130, 0 }, + { -0.243011, 0.079009, 10.141831, 0 }, + { -0.244208, 0.077812, 10.134649, 0 }, + { -0.245406, 0.081403, 10.140635, 0 }, + { -0.253785, 0.070629, 10.110707, 0 }, + { -0.254982, 0.058658, 10.129861, 0 }, + { -0.239420, 0.083797, 10.137043, 0 }, + { -0.232237, 0.081403, 10.125072, 0 }, + { -0.243011, 0.068235, 10.139438, 0 }, + { -0.243011, 0.063446, 10.123875, 0 }, + { -0.232237, 0.074220, 10.140635, 0 }, + { -0.241814, 0.077812, 10.116693, 0 }, + { -0.247800, 0.074220, 10.139438, 0 }, + { -0.245406, 0.077812, 10.127466, 0 }, + { -0.233435, 0.073023, 10.132255, 0 }, + { -0.243011, 0.074220, 10.121481, 0 }, + { -0.246603, 0.059855, 10.125072, 0 }, + { -0.246603, 0.070629, 10.120284, 0 }, + { -0.241814, 0.087388, 10.133451, 0 }, + { -0.245406, 0.061052, 10.128663, 0 }, + { -0.248997, 0.079009, 10.111904, 0 }, + { -0.237026, 0.077812, 10.135846, 0 }, + { -0.240617, 0.083797, 10.108313, 0 }, + { -0.237026, 0.075417, 10.141831, 0 }, + { -0.243011, 0.061052, 10.132255, 0 }, + { -0.234632, 0.073023, 10.133451, 0 }, + { -0.251391, 0.073023, 10.137043, 0 }, + { -0.237026, 0.083797, 10.135846, 0 }, + { -0.231040, 0.077812, 10.117889, 0 }, + { -0.237026, 0.061052, 10.140635, 0 }, + { -0.243011, 0.071826, 10.127466, 0 }, + { -0.235829, 0.081403, 10.131058, 0 }, + { -0.241814, 0.076614, 10.123875, 0 }, + { -0.258574, 0.081403, 10.127466, 0 }, + { -0.241814, 0.063446, 10.127466, 0 }, + { -0.254982, 0.071826, 10.139438, 0 }, + { -0.244208, 0.077812, 10.117889, 0 }, + { -0.240617, 0.077812, 10.134649, 0 }, + { -0.258574, 0.075417, 10.128663, 0 }, + { -0.245406, 0.069432, 10.131058, 0 }, + { -0.245406, 0.074220, 10.126269, 0 }, + { -0.248997, 0.075417, 10.137043, 0 }, + { -0.248997, 0.082600, 10.137043, 0 }, + { -0.245406, 0.084994, 10.115496, 0 }, + { -0.244208, 0.073023, 10.126269, 0 }, + { -0.234632, 0.067038, 10.126269, 0 }, + { -0.238223, 0.064643, 10.127466, 0 }, + { -0.263362, 0.065841, 10.123875, 0 }, + { -0.257377, 0.081403, 10.126269, 0 }, + { -0.237026, 0.082600, 10.105919, 0 }, + { -0.253785, 0.083797, 10.119086, 0 }, + { -0.234632, 0.073023, 10.125072, 0 }, + { -0.243011, 0.062249, 10.122678, 0 }, + { -0.251391, 0.076614, 10.119086, 0 }, + { -0.258574, 0.071826, 10.139438, 0 }, + { -0.250194, 0.071826, 10.140635, 0 }, + { -0.251391, 0.086191, 10.140635, 0 }, + { -0.248997, 0.077812, 10.121481, 0 }, + { -0.244208, 0.083797, 10.126269, 0 }, + { -0.241814, 0.083797, 10.133451, 0 }, + { -0.246603, 0.070629, 10.119086, 0 }, + { -0.241814, 0.067038, 10.146620, 0 }, + { -0.247800, 0.079009, 10.109509, 0 }, + { -0.256179, 0.069432, 10.146620, 0 }, + { -0.247800, 0.073023, 10.126269, 0 }, + { -0.245406, 0.070629, 10.113101, 0 }, + { -0.234632, 0.084994, 10.126269, 0 }, + { -0.228646, 0.068235, 10.129861, 0 }, + { -0.246603, 0.062249, 10.143028, 0 }, + { -0.245406, 0.084994, 10.122678, 0 }, + { -0.244208, 0.067038, 10.143028, 0 }, + { -0.241814, 0.080206, 10.138240, 0 }, + { -0.243011, 0.083797, 10.135846, 0 }, + { -0.238223, 0.069432, 10.139438, 0 }, + { -0.235829, 0.081403, 10.121481, 0 }, + { -0.241814, 0.081403, 10.119086, 0 }, + { -0.241814, 0.068235, 10.146620, 0 }, + { -0.246603, 0.093374, 10.107116, 0 }, + { -0.247800, 0.088585, 10.135846, 0 }, + { -0.258574, 0.069432, 10.101130, 0 }, + { -0.252588, 0.074220, 10.135846, 0 }, + { -0.240617, 0.058658, 10.127466, 0 }, + { -0.263362, 0.073023, 10.138240, 0 }, + { -0.244208, 0.081403, 10.135846, 0 }, + { -0.248997, 0.086191, 10.127466, 0 }, + { -0.251391, 0.074220, 10.133451, 0 }, + { -0.241814, 0.068235, 10.129861, 0 }, + { -0.247800, 0.075417, 10.144226, 0 }, + { -0.248997, 0.086191, 10.113101, 0 }, + { -0.239420, 0.080206, 10.153803, 0 }, + { -0.239420, 0.059855, 10.117889, 0 }, + { -0.244208, 0.073023, 10.139438, 0 }, + { -0.245406, 0.082600, 10.120284, 0 }, + { -0.238223, 0.086191, 10.133451, 0 }, + { -0.246603, 0.079009, 10.123875, 0 }, + { -0.247800, 0.074220, 10.131058, 0 }, + { -0.252588, 0.084994, 10.120284, 0 }, + { -0.245406, 0.075417, 10.125072, 0 }, + { -0.240617, 0.069432, 10.135846, 0 }, + { -0.245406, 0.076614, 10.121481, 0 }, + { -0.231040, 0.068235, 10.132255, 0 }, + { -0.233435, 0.076614, 10.134649, 0 }, + { -0.239420, 0.082600, 10.127466, 0 }, + { -0.253785, 0.076614, 10.104721, 0 }, + { -0.247800, 0.089783, 10.133451, 0 }, + { -0.238223, 0.076614, 10.134649, 0 }, + { -0.240617, 0.073023, 10.105919, 0 }, + { -0.243011, 0.067038, 10.146620, 0 }, + { -0.246603, 0.067038, 10.135846, 0 }, + { -0.250194, 0.080206, 10.146620, 0 }, + { -0.252588, 0.062249, 10.125072, 0 }, + { -0.234632, 0.074220, 10.127466, 0 }, + { -0.239420, 0.069432, 10.149014, 0 }, + { -0.243011, 0.069432, 10.126269, 0 }, + { -0.240617, 0.071826, 10.109509, 0 }, + { -0.258574, 0.067038, 10.121481, 0 }, + { -0.258574, 0.079009, 10.137043, 0 }, + { -0.248997, 0.083797, 10.114298, 0 }, + { -0.228646, 0.077812, 10.123875, 0 }, + { -0.248997, 0.061052, 10.128663, 0 }, + { -0.253785, 0.080206, 10.140635, 0 }, + { -0.250194, 0.077812, 10.119086, 0 }, + { -0.250194, 0.080206, 10.134649, 0 }, + { -0.254982, 0.079009, 10.104721, 0 }, + { -0.251391, 0.076614, 10.125072, 0 }, + { -0.244208, 0.069432, 10.109509, 0 }, + { -0.251391, 0.075417, 10.131058, 0 }, + { -0.246603, 0.074220, 10.135846, 0 }, + { -0.247800, 0.077812, 10.133451, 0 }, + { -0.243011, 0.095768, 10.119086, 0 }, + { -0.252588, 0.079009, 10.103524, 0 }, + { -0.248997, 0.080206, 10.119086, 0 }, + { -0.250194, 0.087388, 10.122678, 0 }, + { -0.244208, 0.071826, 10.143028, 0 }, + { -0.228646, 0.079009, 10.104721, 0 }, + { -0.235829, 0.087388, 10.125072, 0 }, + { -0.241814, 0.070629, 10.105919, 0 }, + { -0.251391, 0.081403, 10.140635, 0 }, + { -0.235829, 0.074220, 10.117889, 0 }, + { -0.244208, 0.076614, 10.134649, 0 }, + { -0.248997, 0.074220, 10.108313, 0 }, + { -0.240617, 0.089783, 10.123875, 0 }, + { -0.254982, 0.074220, 10.146620, 0 }, + { -0.252588, 0.079009, 10.120284, 0 }, + { -0.246603, 0.087388, 10.133451, 0 }, + { -0.246603, 0.074220, 10.116693, 0 }, + { -0.235829, 0.074220, 10.138240, 0 }, + { -0.239420, 0.076614, 10.111904, 0 }, + { -0.253785, 0.065841, 10.132255, 0 }, + { -0.246603, 0.074220, 10.117889, 0 }, + { -0.251391, 0.084994, 10.121481, 0 }, + { -0.260968, 0.087388, 10.131058, 0 }, + { -0.246603, 0.084994, 10.123875, 0 }, + { -0.247800, 0.087388, 10.119086, 0 }, + { -0.238223, 0.070629, 10.125072, 0 }, + { -0.248997, 0.075417, 10.137043, 0 }, + { -0.240617, 0.081403, 10.126269, 0 }, + { -0.225055, 0.075417, 10.117889, 0 }, + { -0.245406, 0.061052, 10.099933, 0 }, + { -0.229843, 0.071826, 10.133451, 0 }, + { -0.239420, 0.088585, 10.158591, 0 }, + { -0.251391, 0.079009, 10.111904, 0 }, + { -0.234632, 0.070629, 10.151408, 0 }, + { -0.232237, 0.068235, 10.127466, 0 }, + { -0.238223, 0.083797, 10.125072, 0 }, + { -0.240617, 0.083797, 10.104721, 0 }, + { -0.234632, 0.084994, 10.127466, 0 }, + { -0.243011, 0.068235, 10.098736, 0 }, + { -0.251391, 0.075417, 10.146620, 0 }, + { -0.257377, 0.082600, 10.117889, 0 }, + { -0.234632, 0.076614, 10.119086, 0 }, + { -0.244208, 0.080206, 10.132255, 0 }, + { -0.232237, 0.080206, 10.139438, 0 }, + { -0.235829, 0.083797, 10.134649, 0 }, + { -0.240617, 0.083797, 10.107116, 0 }, + { -0.239420, 0.087388, 10.134649, 0 }, + { -0.248997, 0.074220, 10.125072, 0 }, + { -0.247800, 0.064643, 10.150211, 0 }, + { -0.243011, 0.076614, 10.111904, 0 }, + { -0.247800, 0.069432, 10.139438, 0 }, + { -0.240617, 0.076614, 10.132255, 0 }, + { -0.240617, 0.076614, 10.129861, 0 }, + { -0.235829, 0.065841, 10.105919, 0 }, + { -0.252588, 0.080206, 10.113101, 0 }, + { -0.251391, 0.077812, 10.149014, 0 }, + { -0.241814, 0.082600, 10.056837, 0 }, + { -0.243011, 0.084994, 10.199292, 0 }, + { -0.253785, 0.077812, 10.098736, 0 }, + { -0.229843, 0.063446, 10.103524, 0 }, + { -0.250194, 0.069432, 10.183730, 0 }, + { -0.240617, 0.086191, 10.067612, 0 }, + { -0.246603, 0.070629, 10.201687, 0 }, + { -0.263362, 0.067038, 10.071202, 0 }, + { -0.245406, 0.059855, 10.166970, 0 }, + { -0.239420, 0.065841, 10.092751, 0 }, + { -0.238223, 0.068235, 10.139438, 0 }, + { -0.243011, 0.074220, 10.116693, 0 }, + { -0.240617, 0.081403, 10.122678, 0 }, + { -0.251391, 0.067038, 10.119086, 0 }, + { -0.240617, 0.075417, 10.113101, 0 }, + { -0.250194, 0.059855, 10.137043, 0 }, + { -0.244208, 0.062249, 10.129861, 0 }, + { -0.229843, 0.083797, 10.117889, 0 }, + { -0.246603, 0.076614, 10.123875, 0 }, + { -0.234632, 0.087388, 10.140635, 0 }, + { -0.254982, 0.079009, 10.119086, 0 }, + { -0.237026, 0.074220, 10.157393, 0 }, + { -0.247800, 0.088585, 10.115496, 0 }, + { -0.251391, 0.087388, 10.144226, 0 }, + { -0.238223, 0.071826, 10.116693, 0 }, + { -0.233435, 0.069432, 10.137043, 0 }, + { -0.231040, 0.081403, 10.119086, 0 }, + { -0.244208, 0.079009, 10.116693, 0 }, + { -0.245406, 0.073023, 10.147817, 0 }, + { -0.250194, 0.071826, 10.113101, 0 }, + { -0.238223, 0.077812, 10.135846, 0 }, + { -0.240617, 0.077812, 10.105919, 0 }, + { -0.239420, 0.076614, 10.145423, 0 }, + { -0.232237, 0.070629, 10.102327, 0 }, + { -0.241814, 0.080206, 10.119086, 0 }, + { -0.237026, 0.068235, 10.111904, 0 }, + { -0.260968, 0.082600, 10.137043, 0 }, + { -0.240617, 0.089783, 10.139438, 0 }, + { -0.238223, 0.077812, 10.128663, 0 }, + { -0.240617, 0.075417, 10.138240, 0 }, + { -0.247800, 0.075417, 10.129861, 0 }, + { -0.251391, 0.075417, 10.143028, 0 }, + { -0.254982, 0.076614, 10.128663, 0 }, + { -0.251391, 0.070629, 10.157393, 0 }, + { -0.253785, 0.086191, 10.134649, 0 }, + { -0.248997, 0.079009, 10.126269, 0 }, + { -0.244208, 0.087388, 10.117889, 0 }, + { -0.254982, 0.080206, 10.125072, 0 }, + { -0.244208, 0.071826, 10.122678, 0 }, + { -0.248997, 0.087388, 10.111904, 0 }, + { -0.246603, 0.075417, 10.133451, 0 }, + { -0.252588, 0.071826, 10.099933, 0 }, + { -0.245406, 0.082600, 10.132255, 0 }, + { -0.246603, 0.086191, 10.129861, 0 }, + { -0.227449, 0.067038, 10.151408, 0 }, + { -0.235829, 0.079009, 10.109509, 0 }, + { -0.239420, 0.080206, 10.137043, 0 }, + { -0.241814, 0.084994, 10.121481, 0 }, + { -0.251391, 0.081403, 10.116693, 0 }, + { -0.260968, 0.073023, 10.141831, 0 }, + { -0.245406, 0.073023, 10.122678, 0 }, + { -0.252588, 0.083797, 10.139438, 0 }, + { -0.243011, 0.080206, 10.122678, 0 }, + { -0.239420, 0.077812, 10.138240, 0 }, + { -0.241814, 0.068235, 10.113101, 0 }, + { -0.244208, 0.074220, 10.133451, 0 }, + { -0.257377, 0.079009, 10.128663, 0 }, + { -0.253785, 0.074220, 10.125072, 0 }, + { -0.238223, 0.062249, 10.132255, 0 }, + { -0.243011, 0.068235, 10.119086, 0 }, + { -0.240617, 0.074220, 10.132255, 0 }, + { -0.272939, 0.076614, 10.116693, 0 }, + { -0.234632, 0.075417, 10.138240, 0 }, + { -0.241814, 0.073023, 10.085567, 0 }, + { -0.246603, 0.075417, 10.163380, 0 }, + { -0.248997, 0.058658, 10.093947, 0 }, + { -0.243011, 0.070629, 10.146620, 0 }, + { -0.238223, 0.074220, 10.110707, 0 }, + { -0.252588, 0.065841, 10.141831, 0 }, + { -0.229843, 0.074220, 10.137043, 0 }, + { -0.248997, 0.076614, 10.099933, 0 }, + { -0.229843, 0.081403, 10.157393, 0 }, + { -0.243011, 0.082600, 10.074794, 0 }, + { -0.250194, 0.071826, 10.164577, 0 }, + { -0.263362, 0.076614, 10.103524, 0 }, + { -0.260968, 0.094571, 10.138240, 0 }, + { -0.240617, 0.077812, 10.116693, 0 }, + { -0.239420, 0.081403, 10.109509, 0 }, + { -0.253785, 0.086191, 10.135846, 0 }, + { -0.247800, 0.076614, 10.093947, 0 }, + { -0.256179, 0.068235, 10.158591, 0 }, + { -0.253785, 0.079009, 10.090356, 0 }, + { -0.239420, 0.076614, 10.151408, 0 }, + { -0.244208, 0.082600, 10.115496, 0 }, + { -0.244208, 0.081403, 10.134649, 0 }, + { -0.254982, 0.088585, 10.122678, 0 }, + { -0.252588, 0.069432, 10.120284, 0 }, + { -0.247800, 0.077812, 10.137043, 0 }, + { -0.250194, 0.076614, 10.117889, 0 }, + { -0.238223, 0.077812, 10.121481, 0 }, + { -0.245406, 0.065841, 10.186124, 0 }, + { -0.233435, 0.065841, 10.046063, 0 }, + { -0.237026, 0.094571, 10.243585, 0 }, + { -0.231040, 0.093374, 10.014939, 0 }, + { -0.243011, 0.084994, 10.223234, 0 }, + { -0.256179, 0.064643, 9.987406, 0 }, + { -0.250194, 0.098162, 10.247176, 0 }, + { -0.229843, 0.073023, 9.891638, 0 }, + { -0.268150, 0.062249, 10.406390, 0 }, + { -0.247800, 0.073023, 9.883258, 0 }, + { -0.237026, 0.076614, 10.360901, 0 }, + { -0.247800, 0.081403, 9.975434, 0 }, + { -0.225055, 0.080206, 10.178942, 0 }, + { -0.263362, 0.071826, 10.163380, 0 }, + { -0.237026, 0.076614, 10.062823, 0 }, + { -0.265756, 0.075417, 10.214854, 0 }, + { -0.234632, 0.083797, 10.053246, 0 }, + { -0.254982, 0.071826, 10.210066, 0 }, + { -0.241814, 0.076614, 10.001771, 0 }, + { -0.221464, 0.117316, 10.239994, 0 }, + { -0.269348, 0.076614, 10.064020, 0 }, + { -0.220266, 0.092177, 10.166970, 0 }, + { -0.252588, 0.075417, 10.111904, 0 }, + { -0.232237, 0.068235, 10.122678, 0 }, + { -0.259771, 0.075417, 10.110707, 0 }, + { -0.246603, 0.095768, 10.137043, 0 }, + { -0.235829, 0.076614, 10.138240, 0 }, + { -0.256179, 0.071826, 10.102327, 0 }, + { -0.229843, 0.089783, 10.175350, 0 }, + { -0.260968, 0.082600, 10.089159, 0 }, + { -0.225055, 0.086191, 10.169365, 0 }, + { -0.262165, 0.087388, 10.103524, 0 }, + { -0.234632, 0.077812, 10.149014, 0 }, + { -0.241814, 0.070629, 10.079582, 0 }, + { -0.256179, 0.077812, 10.163380, 0 }, + { -0.226252, 0.068235, 10.096342, 0 }, + { -0.253785, 0.080206, 10.117889, 0 }, + { -0.244208, 0.077812, 10.163380, 0 }, + { -0.269348, 0.076614, 10.097539, 0 }, + { -0.238223, 0.069432, 10.169365, 0 }, + { -0.254982, 0.068235, 10.096342, 0 }, + { -0.231040, 0.061052, 10.159788, 0 }, + { -0.248997, 0.075417, 10.079582, 0 }, + { -0.258574, 0.071826, 10.162182, 0 }, + { -0.232237, 0.079009, 10.102327, 0 }, + { -0.256179, 0.100556, 10.138240, 0 }, + { -0.232237, 0.084994, 10.116693, 0 }, + { -0.235829, 0.080206, 10.110707, 0 }, + { -0.225055, 0.065841, 10.129861, 0 }, + { -0.217872, 0.082600, 10.090356, 0 }, + { -0.244208, 0.081403, 10.157393, 0 }, }; const size_t kBodyDetectOnOffTestDataLength = -- cgit v1.2.1 From 5f417649d12342adb72fdcbd8a8d66c7887be529 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:11:27 -0600 Subject: board/volteer/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39342b13774eef74b797f19f71808a1e5e896cbe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729081 Reviewed-by: Jeremy Bettis --- board/volteer/sensors.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/volteer/sensors.c b/board/volteer/sensors.c index c3e42cbf05..92e510429d 100644 --- a/board/volteer/sensors.c +++ b/board/volteer/sensors.c @@ -84,17 +84,13 @@ static struct tcs3400_rgb_drv_data_t g_tcs3400_rgb_data = { }; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { -- cgit v1.2.1 From cd70e2e35c321f49d86600e4dd46cfa906f00b0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:20 -0600 Subject: chip/ish/system_state.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4ef4285ff28c9441bcbe8cbb1d1faf731ad3ace4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729163 Reviewed-by: Jeremy Bettis --- chip/ish/system_state.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/ish/system_state.h b/chip/ish/system_state.h index 20de1aaf4b..66ccd80b58 100644 --- a/chip/ish/system_state.h +++ b/chip/ish/system_state.h @@ -6,7 +6,7 @@ #ifndef __SYSTEM_STATE_H #define __SYSTEM_STATE_H -#define HECI_FIXED_SYSTEM_STATE_ADDR 13 +#define HECI_FIXED_SYSTEM_STATE_ADDR 13 struct ss_subsys_device; -- cgit v1.2.1 From 62618fd33368aae0fbcc316e77bc58ed37302be5 Mon Sep 17 00:00:00 2001 From: wen zhang Date: Fri, 1 Jul 2022 14:57:43 +0800 Subject: zephyr: Remove the unused enum for USB-A These enum-names are not used in the legacy code so remove them BUG=b:237738771 TEST=zmake testall BRANCH=none Change-Id: Ib5fbdc7432e300c44a091169d0d1aeaba6f96bf6 Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739989 Reviewed-by: Zhengqiao Xia Reviewed-by: Andrew McRae --- zephyr/dts/bindings/gpio/gpio-enum-name.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml index bdfb1fba1c..608a2c8236 100644 --- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml +++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml @@ -42,8 +42,6 @@ properties: - GPIO_EN_PP3300_A - GPIO_EN_PP5000 - GPIO_EN_PP5000_A - - GPIO_EN_PP5000_USB_A0_VBUS - - GPIO_EN_PP5000_USB_A1_VBUS - GPIO_EN_PP5000_USBA - GPIO_EN_PP5000_USBA_R - GPIO_EN_PPVAR_VCCIN -- cgit v1.2.1 From 5665479326deb26640c6f581d9eba6224beabf7c Mon Sep 17 00:00:00 2001 From: wen zhang Date: Fri, 1 Jul 2022 15:08:04 +0800 Subject: corsole: Remove unused gpio enum-name for USB-A These enum-names are not used in the legacy code so remove them BUG=b:237738771 TEST=zmake testall BRANCH=none Change-Id: I55e615b940942ab2778c453ff8966a138bff2dfa Signed-off-by: wen zhang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739990 Reviewed-by: Andrew McRae --- zephyr/projects/corsola/gpio_kingler.dts | 1 - zephyr/projects/corsola/gpio_krabby.dts | 1 - zephyr/projects/corsola/gpio_steelix.dts | 2 -- zephyr/projects/corsola/gpio_tentacruel.dts | 1 - 4 files changed, 5 deletions(-) diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts index ea78d94f48..f117140ea7 100644 --- a/zephyr/projects/corsola/gpio_kingler.dts +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -178,7 +178,6 @@ }; en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus_x { gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_EN_PP5000_USB_A0_VBUS"; }; gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { gpios = <&gpio3 7 GPIO_INPUT>; diff --git a/zephyr/projects/corsola/gpio_krabby.dts b/zephyr/projects/corsola/gpio_krabby.dts index 70ee4b8643..169e9061fd 100644 --- a/zephyr/projects/corsola/gpio_krabby.dts +++ b/zephyr/projects/corsola/gpio_krabby.dts @@ -115,7 +115,6 @@ }; en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_EN_PP5000_USB_A0_VBUS"; }; usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo { gpios = <&gpiof 0 GPIO_INPUT>; diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts index 8332cea379..4d7b9a507c 100644 --- a/zephyr/projects/corsola/gpio_steelix.dts +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -85,7 +85,6 @@ }; en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus_x { gpios = <&gpiof 5 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_EN_PP5000_USB_A1_VBUS"; }; usb_a1_fault_odl { gpios = <&gpiof 4 GPIO_INPUT>; @@ -185,7 +184,6 @@ }; en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus_x { gpios = <&gpio6 0 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_EN_PP5000_USB_A0_VBUS"; }; gpio_hdmi_prsnt_odl: hdmi_prsnt_odl { gpios = <&gpio3 7 GPIO_INPUT>; diff --git a/zephyr/projects/corsola/gpio_tentacruel.dts b/zephyr/projects/corsola/gpio_tentacruel.dts index 23d85bb59e..459ca33dd6 100644 --- a/zephyr/projects/corsola/gpio_tentacruel.dts +++ b/zephyr/projects/corsola/gpio_tentacruel.dts @@ -115,7 +115,6 @@ }; en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { gpios = <&gpiob 7 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_EN_PP5000_USB_A0_VBUS"; }; usb_c0_ppc_frsinfo: usb_c0_ppc_frsinfo { gpios = <&gpiof 0 GPIO_INPUT>; -- cgit v1.2.1 From 4909c647ebd02f914a9fda62853569a44e2032bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:54 -0600 Subject: board/banshee/keyboard_customization.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49c60cf12e3771fe82bb9bbf26b20ba7d4674249 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728023 Reviewed-by: Jeremy Bettis --- board/banshee/keyboard_customization.h | 75 +++++++++++++++++----------------- 1 file changed, 37 insertions(+), 38 deletions(-) diff --git a/board/banshee/keyboard_customization.h b/board/banshee/keyboard_customization.h index 18043d7453..59ac28745c 100644 --- a/board/banshee/keyboard_customization.h +++ b/board/banshee/keyboard_customization.h @@ -25,52 +25,51 @@ extern uint8_t keyboard_cols; #define KEYBOARD_ROW_TO_MASK(r) (1 << (r)) /* Columns and masks for keys we particularly care about */ -#define KEYBOARD_COL_DOWN 8 -#define KEYBOARD_ROW_DOWN 1 -#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) -#define KEYBOARD_COL_ESC 5 -#define KEYBOARD_ROW_ESC 7 -#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) -#define KEYBOARD_COL_KEY_H 7 -#define KEYBOARD_ROW_KEY_H 2 -#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) -#define KEYBOARD_COL_KEY_R 6 -#define KEYBOARD_ROW_KEY_R 6 -#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) -#define KEYBOARD_COL_LEFT_ALT 3 -#define KEYBOARD_ROW_LEFT_ALT 1 -#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) -#define KEYBOARD_COL_REFRESH 4 -#define KEYBOARD_ROW_REFRESH 6 -#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) -#define KEYBOARD_COL_RIGHT_ALT 3 -#define KEYBOARD_ROW_RIGHT_ALT 0 -#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) -#define KEYBOARD_DEFAULT_COL_VOL_UP 13 -#define KEYBOARD_DEFAULT_ROW_VOL_UP 3 -#define KEYBOARD_COL_LEFT_CTRL 12 -#define KEYBOARD_ROW_LEFT_CTRL 1 +#define KEYBOARD_COL_DOWN 8 +#define KEYBOARD_ROW_DOWN 1 +#define KEYBOARD_MASK_DOWN KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_DOWN) +#define KEYBOARD_COL_ESC 5 +#define KEYBOARD_ROW_ESC 7 +#define KEYBOARD_MASK_ESC KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_ESC) +#define KEYBOARD_COL_KEY_H 7 +#define KEYBOARD_ROW_KEY_H 2 +#define KEYBOARD_MASK_KEY_H KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_H) +#define KEYBOARD_COL_KEY_R 6 +#define KEYBOARD_ROW_KEY_R 6 +#define KEYBOARD_MASK_KEY_R KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_R) +#define KEYBOARD_COL_LEFT_ALT 3 +#define KEYBOARD_ROW_LEFT_ALT 1 +#define KEYBOARD_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_ALT) +#define KEYBOARD_COL_REFRESH 4 +#define KEYBOARD_ROW_REFRESH 6 +#define KEYBOARD_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_REFRESH) +#define KEYBOARD_COL_RIGHT_ALT 3 +#define KEYBOARD_ROW_RIGHT_ALT 0 +#define KEYBOARD_MASK_RIGHT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_ALT) +#define KEYBOARD_DEFAULT_COL_VOL_UP 13 +#define KEYBOARD_DEFAULT_ROW_VOL_UP 3 +#define KEYBOARD_COL_LEFT_CTRL 12 +#define KEYBOARD_ROW_LEFT_CTRL 1 #define KEYBOARD_MASK_LEFT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_CTRL) #define KEYBOARD_COL_RIGHT_CTRL 12 #define KEYBOARD_ROW_RIGHT_CTRL 0 #define KEYBOARD_MASK_RIGHT_CTRL KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_RIGHT_CTRL) -#define KEYBOARD_COL_SEARCH 4 -#define KEYBOARD_ROW_SEARCH 4 -#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) -#define KEYBOARD_COL_KEY_0 13 -#define KEYBOARD_ROW_KEY_0 4 -#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) -#define KEYBOARD_COL_KEY_1 2 -#define KEYBOARD_ROW_KEY_1 5 -#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) -#define KEYBOARD_COL_KEY_2 5 -#define KEYBOARD_ROW_KEY_2 5 -#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) +#define KEYBOARD_COL_SEARCH 4 +#define KEYBOARD_ROW_SEARCH 4 +#define KEYBOARD_MASK_SEARCH KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_SEARCH) +#define KEYBOARD_COL_KEY_0 13 +#define KEYBOARD_ROW_KEY_0 4 +#define KEYBOARD_MASK_KEY_0 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_0) +#define KEYBOARD_COL_KEY_1 2 +#define KEYBOARD_ROW_KEY_1 5 +#define KEYBOARD_MASK_KEY_1 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_1) +#define KEYBOARD_COL_KEY_2 5 +#define KEYBOARD_ROW_KEY_2 5 +#define KEYBOARD_MASK_KEY_2 KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_KEY_2) #define KEYBOARD_COL_LEFT_SHIFT 9 #define KEYBOARD_ROW_LEFT_SHIFT 1 #define KEYBOARD_MASK_LEFT_SHIFT KEYBOARD_ROW_TO_MASK(KEYBOARD_ROW_LEFT_SHIFT) void board_id_keyboard_col_inverted(int board_id); - #endif /* __KEYBOARD_CUSTOMIZATION_H */ -- cgit v1.2.1 From 0f5f2872bddbd3d20cf3b4744e5e01f7774440ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:37 -0600 Subject: baseboard/nucleo-f412zg/base-board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I634ff2dbbdce45e47146c94fe7928ac0b499cc61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727933 Reviewed-by: Jeremy Bettis --- baseboard/nucleo-f412zg/base-board.h | 72 ++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h index d41cdfd207..b104621ec7 100644 --- a/baseboard/nucleo-f412zg/base-board.h +++ b/baseboard/nucleo-f412zg/base-board.h @@ -50,28 +50,28 @@ #define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300 -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (128 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (128 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */ -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * We want to prevent flash readout, and use it as indicator of protection @@ -116,7 +116,7 @@ */ #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE #ifdef SECTION_IS_RW - #undef CONFIG_ROLLBACK_UPDATE +#undef CONFIG_ROLLBACK_UPDATE #endif /*-------------------------------------------------------------------------* @@ -124,9 +124,9 @@ *-------------------------------------------------------------------------*/ #ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ - #define CONFIG_RSA - #define CONFIG_RWSIG +/* RO verifies the RW partition signature */ +#define CONFIG_RSA +#define CONFIG_RWSIG #endif /* SECTION_IS_RO */ #define CONFIG_RSA_KEY_SIZE 3072 #define CONFIG_RSA_EXPONENT_3 @@ -172,27 +172,27 @@ #define CONFIG_WP_ACTIVE_HIGH #ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ - #define CONFIG_SPI +/* TODO(hesling): Fix the illogical dependency between spi.c + * and host_command.c + * + * Currently, the chip/stm32/spi.c depends on functions defined in + * common/host_command.c. When unit test builds use their own tasklist + * without the HOSTCMD task, host_command.c is excluded from the build, + * but chip/stm32/spi.c remains (because of CONFIG_SPI). + * This triggers an undefined reference linker error. + * The reproduce case: + * - Allow CONFIG_SPI in TEST_BUILDs + * - make BOARD=nucleo-h743zi tests + */ +#define CONFIG_SPI #endif #ifndef __ASSEMBLER__ - /* Timer selection */ - #define TIM_CLOCK32 2 - #define TIM_WATCHDOG 16 - #include "gpio_signal.h" - void button_event(enum gpio_signal signal); +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_WATCHDOG 16 +#include "gpio_signal.h" +void button_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASE_BOARD_H */ -- cgit v1.2.1 From 1c8445d3449c6e816ebc88c5ae924e8b432a6f60 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:52 -0600 Subject: board/primus/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4ea60bfa0ac9dfd1950adff67688033d9d8da496 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727764 Reviewed-by: Jeremy Bettis --- board/primus/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/primus/usbc_config.h b/board/primus/usbc_config.h index 8bc1918c02..a7eabddd4e 100644 --- a/board/primus/usbc_config.h +++ b/board/primus/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From 205c135ec45b1a40cb5268504967be14feb46f47 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:41 -0600 Subject: board/delbin/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf285adfd3fc9208628378b0c092bbce4dad23fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728220 Reviewed-by: Jeremy Bettis --- board/delbin/board.h | 106 +++++++++++++++++++++++---------------------------- 1 file changed, 48 insertions(+), 58 deletions(-) diff --git a/board/delbin/board.h b/board/delbin/board.h index 46b7a9b648..0fc3d84e94 100644 --- a/board/delbin/board.h +++ b/board/delbin/board.h @@ -18,7 +18,7 @@ #undef CONFIG_CHIP_INIT_ROM_REGION #undef NPCX_PWM1_SEL -#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* Optional features */ #undef CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ @@ -61,36 +61,35 @@ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W, the limitation of 45W is for the delbin * board. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #undef CONFIG_USB_MUX_RUNTIME_CONFIG /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ #define CONFIG_USBC_PPC_SYV682X - /* BC 1.2 */ /* Volume Button feature */ @@ -98,8 +97,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -111,45 +110,44 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_UART2_EC_RX -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_UART2_EC_RX +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PG_EC_DSW_PWROK GPIO_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 - -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM - -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM + +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -160,11 +158,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_FAN = 0, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -173,11 +167,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); void motion_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From 843b6f0249f0200bd826140c4be755e992228f6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:20 -0600 Subject: driver/usb_mux/anx7451.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7205fcf974ca803239f679abfb73c459a191688f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730159 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx7451.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/driver/usb_mux/anx7451.c b/driver/usb_mux/anx7451.c index db56457bb8..f72b2c93d2 100644 --- a/driver/usb_mux/anx7451.c +++ b/driver/usb_mux/anx7451.c @@ -22,17 +22,16 @@ #define ANX7451_I2C_WAKE_TIMEOUT_MS 20 #define ANX7451_I2C_WAKE_RETRY_DELAY_US 500 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -static inline int anx7451_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx7451_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx7451_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx7451_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } -- cgit v1.2.1 From ca6284c251d55bb8f40731346dcbd392647f95ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:53 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id293078358da998b172333cd054cb67453181fb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730726 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci.h | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h index 81fea3edeb..b1bc8be926 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci.h +++ b/zephyr/include/emul/tcpc/emul_tcpci.h @@ -133,10 +133,7 @@ enum tcpci_emul_ops_resp { }; /** Revisions supported by TCPCI emaluator */ -enum tcpci_emul_rev { - TCPCI_EMUL_REV1_0_VER1_0 = 0, - TCPCI_EMUL_REV2_0_VER1_1 -}; +enum tcpci_emul_rev { TCPCI_EMUL_REV1_0_VER1_0 = 0, TCPCI_EMUL_REV2_0_VER1_1 }; /** Status of TX message send to TCPCI emulator partner */ enum tcpci_emul_tx_status { @@ -166,9 +163,9 @@ struct tcpci_emul_dev_ops { * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ - enum tcpci_emul_ops_resp (*read_byte)(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, uint8_t *val, int bytes); + enum tcpci_emul_ops_resp (*read_byte)( + const struct emul *emul, const struct tcpci_emul_dev_ops *ops, + int reg, uint8_t *val, int bytes); /** * @brief Function called for each byte of write message @@ -183,9 +180,9 @@ struct tcpci_emul_dev_ops { * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ - enum tcpci_emul_ops_resp (*write_byte)(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, uint8_t val, int bytes); + enum tcpci_emul_ops_resp (*write_byte)( + const struct emul *emul, const struct tcpci_emul_dev_ops *ops, + int reg, uint8_t val, int bytes); /** * @brief Function called on the end of write message @@ -199,9 +196,9 @@ struct tcpci_emul_dev_ops { * @return TCPCI_EMUL_DONE to immedietly return success * @return TCPCI_EMUL_ERROR to immedietly return error */ - enum tcpci_emul_ops_resp (*handle_write)(const struct emul *emul, - const struct tcpci_emul_dev_ops *ops, - int reg, int msg_len); + enum tcpci_emul_ops_resp (*handle_write)( + const struct emul *emul, const struct tcpci_emul_dev_ops *ops, + int reg, int msg_len); /** * @brief Function called on reset @@ -227,8 +224,7 @@ struct tcpci_emul_partner_ops { void (*transmit)(const struct emul *emul, const struct tcpci_emul_partner_ops *ops, const struct tcpci_emul_msg *tx_msg, - enum tcpci_msg_type type, - int retry); + enum tcpci_msg_type type, int retry); /** * @brief Function called when control settings change to allow partner -- cgit v1.2.1 From dfa303df61bcf8f3ca552e924dec2e152967adc0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:59 -0600 Subject: board/garg/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic0a8607940a17f9e6c88731ab2a5c6ffa4621c98 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728389 Reviewed-by: Jeremy Bettis --- board/garg/board.c | 121 +++++++++++++++++++++++++---------------------------- 1 file changed, 56 insertions(+), 65 deletions(-) diff --git a/board/garg/board.c b/board/garg/board.c index de55f33c6a..b08b5a979c 100644 --- a/board/garg/board.c +++ b/board/garg/board.c @@ -44,11 +44,11 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -58,17 +58,16 @@ static uint8_t sku_id; * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); static void ppc_interrupt(enum gpio_signal signal) { @@ -91,31 +90,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -125,24 +124,17 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; - -const mat33_fp_t base_icm_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_bmi260_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_icm_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; +static const mat33_fp_t base_bmi260_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -256,20 +248,20 @@ struct motion_sensor_t icm426xx_base_accel = { }; struct motion_sensor_t icm426xx_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm426xx_data, - .port = I2C_PORT_SENSOR, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &base_icm_ref, - .min_frequency = ICM426XX_GYRO_MIN_FREQ, - .max_frequency = ICM426XX_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM426XX, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm426xx_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm426xx_data, + .port = I2C_PORT_SENSOR, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &base_icm_ref, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; struct motion_sensor_t bmi260_base_accel = { @@ -318,7 +310,6 @@ struct motion_sensor_t bmi260_base_gyro = { .max_frequency = BMI_GYRO_MAX_FREQ, }; - static int board_is_convertible(void) { /* @@ -389,8 +380,8 @@ void board_hibernate_late(void) const uint32_t hibernate_pins[][2] = { /* Turn off LEDs before going to hibernate */ - {GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP}, + { GPIO_BAT_LED_BLUE_L, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_ORANGE_L, GPIO_INPUT | GPIO_PULL_UP }, }; for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i) -- cgit v1.2.1 From c99f46b48ea7ce9e69253041833c266046626500 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:41 -0600 Subject: driver/retimer/ps8811.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I768a7c973ad8fd7e741a9f73fc8a0d4f06334f82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730067 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8811.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/driver/retimer/ps8811.c b/driver/retimer/ps8811.c index 6a66248d38..2485592d18 100644 --- a/driver/retimer/ps8811.c +++ b/driver/retimer/ps8811.c @@ -15,9 +15,7 @@ int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); return rv; } @@ -26,23 +24,18 @@ int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data) { int rv; - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); return rv; } int ps8811_i2c_field_update(const struct usb_mux *me, int page, int offset, - uint8_t field_mask, uint8_t set_value) + uint8_t field_mask, uint8_t set_value) { int rv; - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); return rv; } -- cgit v1.2.1 From 2e6d0e1f17267352e743ba9a886cca9a3c4482f0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:40 -0600 Subject: include/gpio_signal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I807d2d55eda4934201bbb7ec2bd2a6341c99a8a3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730278 Reviewed-by: Jeremy Bettis --- include/gpio_signal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/gpio_signal.h b/include/gpio_signal.h index 86fd5d7822..a1176906c2 100644 --- a/include/gpio_signal.h +++ b/include/gpio_signal.h @@ -27,7 +27,7 @@ #define GPIO_SIGNAL_START 0 /* The first valid GPIO signal is 0 */ enum gpio_signal { - #include "gpio.wrap" +#include "gpio.wrap" GPIO_COUNT, /* Ensure that sizeof gpio_signal is large enough for ioex_signal */ GPIO_LIMIT = 0x0FFF @@ -42,7 +42,7 @@ enum ioex_signal { IOEX_SIGNAL_START = GPIO_LIMIT + 1, /* Used to ensure that the first IOEX signal is same as start */ __IOEX_PLACEHOLDER = GPIO_LIMIT, - #include "gpio.wrap" +#include "gpio.wrap" IOEX_SIGNAL_END, IOEX_LIMIT = 0x1FFF }; -- cgit v1.2.1 From e02cb7b4161a63d29468f7d4dfbd310500cc918f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:44 -0600 Subject: chip/npcx/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia5b1ecd192def38ebfb0d9cc515e3de1e57dc610 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729378 Reviewed-by: Jeremy Bettis --- chip/npcx/espi.c | 176 +++++++++++++++++++++++++++---------------------------- 1 file changed, 86 insertions(+), 90 deletions(-) diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 7248c7711f..6479e85c62 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -24,114 +24,114 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) #endif /* Default eSPI configuration for VW events */ struct vwevms_config_t { - uint8_t idx; /* VW index */ - uint8_t idx_en; /* Index enable */ - uint8_t pltrst_en; /* Enable reset by PLTRST assert */ + uint8_t idx; /* VW index */ + uint8_t idx_en; /* Index enable */ + uint8_t pltrst_en; /* Enable reset by PLTRST assert */ uint8_t espirst_en; /* Enable reset by eSPI_RST assert */ - uint8_t int_en; /* Interrupt/Wake-up enable */ + uint8_t int_en; /* Interrupt/Wake-up enable */ }; struct vwevsm_config_t { - uint8_t idx; /* VW index */ - uint8_t idx_en; /* Index enable */ - uint8_t pltrst_en; /* Enable reset by PLTRST assert */ - uint8_t cdrst_en; /* Enable cold reset */ - uint8_t valid; /* Valid VW mask */ + uint8_t idx; /* VW index */ + uint8_t idx_en; /* Index enable */ + uint8_t pltrst_en; /* Enable reset by PLTRST assert */ + uint8_t cdrst_en; /* Enable cold reset */ + uint8_t valid; /* Valid VW mask */ }; /* Default MIWU configurations for VW events */ struct host_wui_item { uint16_t table : 2; /* MIWU table 0-2 */ uint16_t group : 3; /* MIWU group 0-7 */ - uint16_t num : 3; /* MIWU bit 0-7 */ - uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */ + uint16_t num : 3; /* MIWU bit 0-7 */ + uint16_t edge : 4; /* MIWU edge trigger type rising/falling/any */ }; /* Mapping item between VW signal, index and value */ struct vw_event_t { - uint16_t name; /* Name of signal */ - uint8_t evt_idx; /* VW index of signal */ - uint8_t evt_val; /* VW value of signal */ + uint16_t name; /* Name of signal */ + uint8_t evt_idx; /* VW index of signal */ + uint8_t evt_val; /* VW value of signal */ }; /* Default settings of VWEVMS registers (Please refer Table.43/44) */ static const struct vwevms_config_t espi_in_list[] = { - /* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ +/* IDX EN ENPL ENESP IE/WE VW Event Bit 0 - 3 (M->S) */ #ifdef CONFIG_HOSTCMD_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST - {0x02, 1, 0, 1, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ + { 0x02, 1, 0, 1, 1 }, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ #else - {0x02, 1, 0, 0, 1}, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ + { 0x02, 1, 0, 0, 1 }, /* SLP_S3#, SLP_S4#, SLP_S5#, Reserve */ #endif - {0x03, 1, 0, 1, 1}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ - {0x07, 1, 1, 1, 1}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ - {0x41, 1, 0, 1, 1}, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ - {0x42, 1, 0, 0, 1}, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ - {0x47, 1, 1, 1, 1}, /* HOST_C10, Reserve, Reserve, Reserve */ + { 0x03, 1, 0, 1, 1 }, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ + { 0x07, 1, 1, 1, 1 }, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ + { 0x41, 1, 0, 1, 1 }, /* SUS_WARN#, SPWRDN_ACK, Reserve, SLP_A# */ + { 0x42, 1, 0, 0, 1 }, /* SLP_LAN#, SLP_WAN#, Reserve, Reserve */ + { 0x47, 1, 1, 1, 1 }, /* HOST_C10, Reserve, Reserve, Reserve */ }; /* Default settings of VWEVSM registers (Please refer Table.43/44) */ static const struct vwevsm_config_t espi_out_list[] = { /* IDX EN ENPL ENCDR VDMASK VW Event Bit 0 - 3 (S->M) */ - {0x04, 1, 0, 0, 0x0D}, /* ORST_ACK, Reserve, WAKE#, PME# */ - {0x05, 1, 0, 0, 0x0F}, /* SLV_BL_DNE, ERR_F, ERR_NF, SLV_BL_STS */ + { 0x04, 1, 0, 0, 0x0D }, /* ORST_ACK, Reserve, WAKE#, PME# */ + { 0x05, 1, 0, 0, 0x0F }, /* SLV_BL_DNE, ERR_F, ERR_NF, SLV_BL_STS */ #ifdef CONFIG_SCI_GPIO - {0x06, 1, 1, 0, 0x0C}, /* SCI#, SMI#, RCIN#, HRST_ACK */ + { 0x06, 1, 1, 0, 0x0C }, /* SCI#, SMI#, RCIN#, HRST_ACK */ #else - {0x06, 1, 1, 0, 0x0F}, /* SCI#, SMI#, RCIN#, HRST_ACK */ + { 0x06, 1, 1, 0, 0x0F }, /* SCI#, SMI#, RCIN#, HRST_ACK */ #endif - {0x40, 1, 0, 0, 0x01}, /* SUS_ACK, Reserve, Reserve, Reserve */ + { 0x40, 1, 0, 0, 0x01 }, /* SUS_ACK, Reserve, Reserve, Reserve */ }; /* eSPI interrupts used in MIWU */ static const struct host_wui_item espi_vw_int_list[] = { /* ESPI_RESET */ - {MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING}, + { MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING }, /* SLP_S3 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING }, /* SLP_S4 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 1, MIWU_EDGE_ANYING }, /* SLP_S5 */ - {MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 2, MIWU_EDGE_ANYING }, /* VW_WIRE_PLTRST */ - {MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 5, MIWU_EDGE_ANYING }, /* VW_WIRE_OOB_RST_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_1, 6, MIWU_EDGE_ANYING }, /* VW_WIRE_HOST_RST_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_2, 0, MIWU_EDGE_ANYING }, /* VW_WIRE_SUS_WARN */ - {MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING}, + { MIWU_TABLE_2, MIWU_GROUP_2, 4, MIWU_EDGE_ANYING }, }; /* VW signals used in eSPI */ static const struct vw_event_t vw_events_list[] = { - {VW_SLP_S3_L, 0x02, 0x01}, /* index 02h (In) */ - {VW_SLP_S4_L, 0x02, 0x02}, - {VW_SLP_S5_L, 0x02, 0x04}, - {VW_SUS_STAT_L, 0x03, 0x01}, /* index 03h (In) */ - {VW_PLTRST_L, 0x03, 0x02}, - {VW_OOB_RST_WARN, 0x03, 0x04}, - {VW_OOB_RST_ACK, 0x04, 0x01}, /* index 04h (Out) */ - {VW_WAKE_L, 0x04, 0x04}, - {VW_PME_L, 0x04, 0x08}, - {VW_ERROR_FATAL, 0x05, 0x02}, /* index 05h (Out) */ - {VW_ERROR_NON_FATAL, 0x05, 0x04}, - {VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09}, - {VW_SCI_L, 0x06, 0x01}, /* index 06h (Out) */ - {VW_SMI_L, 0x06, 0x02}, - {VW_RCIN_L, 0x06, 0x04}, - {VW_HOST_RST_ACK, 0x06, 0x08}, - {VW_HOST_RST_WARN, 0x07, 0x01}, /* index 07h (In) */ - {VW_SUS_ACK, 0x40, 0x01}, /* index 40h (Out) */ - {VW_SUS_WARN_L, 0x41, 0x01}, /* index 41h (In) */ - {VW_SUS_PWRDN_ACK_L, 0x41, 0x02}, - {VW_SLP_A_L, 0x41, 0x08}, - {VW_SLP_LAN, 0x42, 0x01}, /* index 42h (In) */ - {VW_SLP_WLAN, 0x42, 0x02}, + { VW_SLP_S3_L, 0x02, 0x01 }, /* index 02h (In) */ + { VW_SLP_S4_L, 0x02, 0x02 }, + { VW_SLP_S5_L, 0x02, 0x04 }, + { VW_SUS_STAT_L, 0x03, 0x01 }, /* index 03h (In) */ + { VW_PLTRST_L, 0x03, 0x02 }, + { VW_OOB_RST_WARN, 0x03, 0x04 }, + { VW_OOB_RST_ACK, 0x04, 0x01 }, /* index 04h (Out) */ + { VW_WAKE_L, 0x04, 0x04 }, + { VW_PME_L, 0x04, 0x08 }, + { VW_ERROR_FATAL, 0x05, 0x02 }, /* index 05h (Out) */ + { VW_ERROR_NON_FATAL, 0x05, 0x04 }, + { VW_PERIPHERAL_BTLD_STATUS_DONE, 0x05, 0x09 }, + { VW_SCI_L, 0x06, 0x01 }, /* index 06h (Out) */ + { VW_SMI_L, 0x06, 0x02 }, + { VW_RCIN_L, 0x06, 0x04 }, + { VW_HOST_RST_ACK, 0x06, 0x08 }, + { VW_HOST_RST_WARN, 0x07, 0x01 }, /* index 07h (In) */ + { VW_SUS_ACK, 0x40, 0x01 }, /* index 40h (Out) */ + { VW_SUS_WARN_L, 0x41, 0x01 }, /* index 41h (In) */ + { VW_SUS_PWRDN_ACK_L, 0x41, 0x02 }, + { VW_SLP_A_L, 0x41, 0x08 }, + { VW_SLP_LAN, 0x42, 0x01 }, /* index 42h (In) */ + { VW_SLP_WLAN, 0x42, 0x02 }, }; /* Flag for boot load signals */ @@ -153,7 +153,7 @@ static void espi_reset_recovery(void) static void espi_vw_config_in(const struct vwevms_config_t *config) { uint32_t val; - uint8_t i, index; + uint8_t i, index; switch (VM_TYPE(config->idx)) { case ESPI_VW_TYPE_SYS_EV: @@ -164,11 +164,10 @@ static void espi_vw_config_in(const struct vwevms_config_t *config) if (index == config->idx) { /* Get Wire field */ val = NPCX_VWEVMS(i) & 0x0F; - val |= VWEVMS_FIELD(config->idx, - config->idx_en, - config->pltrst_en, - config->int_en, - config->espirst_en); + val |= VWEVMS_FIELD(config->idx, config->idx_en, + config->pltrst_en, + config->int_en, + config->espirst_en); NPCX_VWEVMS(i) = val; return; } @@ -196,11 +195,10 @@ static void espi_vw_config_out(const struct vwevsm_config_t *config) if (index == config->idx) { /* Preserve WIRE(3-0) and HW_WIRE (27-24). */ val = NPCX_VWEVSM(i) & 0x0F00000F; - val |= VWEVSM_FIELD(config->idx, - config->idx_en, - config->valid, - config->pltrst_en, - config->cdrst_en); + val |= VWEVSM_FIELD(config->idx, config->idx_en, + config->valid, + config->pltrst_en, + config->cdrst_en); NPCX_VWEVSM(i) = val; return; } @@ -218,8 +216,8 @@ static void espi_enable_vw_int(const struct host_wui_item *vwire_int) { uint8_t table = vwire_int->table; uint8_t group = vwire_int->group; - uint8_t num = vwire_int->num; - uint8_t edge = vwire_int->edge; + uint8_t num = vwire_int->num; + uint8_t edge = vwire_int->edge; /* Set detection mode to edge */ CLEAR_BIT(NPCX_WKMOD(table, group), num); @@ -266,7 +264,7 @@ void espi_vw_power_signal_interrupt(enum espi_vw_signal signal) { if (IS_ENABLED(CONFIG_HOST_ESPI_VW_POWER_SIGNAL)) /* TODO: Add VW handler in power/common.c */ - power_signal_interrupt((enum gpio_signal) signal); + power_signal_interrupt((enum gpio_signal)signal); } void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us) @@ -289,7 +287,7 @@ void espi_wait_vw_not_dirty(enum espi_vw_signal signal, unsigned int timeout_us) timeout = get_time().val + (uint64_t)timeout_us; while ((NPCX_VWEVSM(offset) & VWEVSM_DIRTY(1)) && - (get_time().val < timeout)) { + (get_time().val < timeout)) { udelay(10); } } @@ -609,12 +607,12 @@ static void espi_interrupt(void) * handled by PLTRST separately. */ for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; - chan++) { + chan++) { if (!IS_PERIPHERAL_CHAN_ENABLE(chan) && - IS_HOST_CHAN_EN(chan)) + IS_HOST_CHAN_EN(chan)) ENABLE_ESPI_CHAN(chan); else if (IS_PERIPHERAL_CHAN_ENABLE(chan) && - !IS_HOST_CHAN_EN(chan)) + !IS_HOST_CHAN_EN(chan)) DISABLE_ESPI_CHAN(chan); } @@ -625,9 +623,8 @@ static void espi_interrupt(void) */ if (boot_load_done == 0 && IS_PERIPHERAL_CHAN_ENABLE(NPCX_ESPI_CH_VW)) { - - espi_vw_set_wire( - VW_PERIPHERAL_BTLD_STATUS_DONE, 1); + espi_vw_set_wire(VW_PERIPHERAL_BTLD_STATUS_DONE, + 1); boot_load_done = 1; } } @@ -662,7 +659,7 @@ void espi_init(void) /* Support all I/O modes */ SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, - NPCX_ESPI_IO_MODE_ALL); + NPCX_ESPI_IO_MODE_ALL); /* Set eSPI speed to max supported */ SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, @@ -688,7 +685,7 @@ static int command_espi(int argc, char **argv) if (argc == 1) { return EC_ERROR_INVAL; - /* Get value of eSPI registers */ + /* Get value of eSPI registers */ } else if (argc == 2) { int i; @@ -697,23 +694,23 @@ static int command_espi(int argc, char **argv) } else if (strcasecmp(argv[1], "vsm") == 0) { for (i = 0; i < ESPI_VWEVSM_NUM; i++) { uint32_t val = NPCX_VWEVSM(i); - uint8_t idx = VWEVSM_IDX_GET(val); + uint8_t idx = VWEVSM_IDX_GET(val); ccprintf("VWEVSM%d: %02x [0x%08x]\n", i, idx, - val); + val); } } else if (strcasecmp(argv[1], "vms") == 0) { for (i = 0; i < ESPI_VWEVMS_NUM; i++) { uint32_t val = NPCX_VWEVMS(i); - uint8_t idx = VWEVMS_IDX_GET(val); + uint8_t idx = VWEVMS_IDX_GET(val); ccprintf("VWEVMS%d: %02x [0x%08x]\n", i, idx, - val); + val); } } - /* Enable/Disable the channels of eSPI */ + /* Enable/Disable the channels of eSPI */ } else if (argc == 3) { - uint32_t m = (uint32_t) strtoi(argv[2], &e, 0); + uint32_t m = (uint32_t)strtoi(argv[2], &e, 0); if (*e) return EC_ERROR_PARAM2; @@ -733,6 +730,5 @@ static int command_espi(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(espi, command_espi, - "cfg/vms/vsm/en/dis [channel]", +DECLARE_CONSOLE_COMMAND(espi, command_espi, "cfg/vms/vsm/en/dis [channel]", "eSPI configurations"); -- cgit v1.2.1 From e21ed3a3ab849ae097a7d62eff98d4433737ea88 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:45 -0600 Subject: board/marzipan/switchcap.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I950dd89e1f8b5bf98b36f8459379493522a8537f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728669 Reviewed-by: Jeremy Bettis --- board/marzipan/switchcap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/marzipan/switchcap.c b/board/marzipan/switchcap.c index 26009d55d8..03198485b2 100644 --- a/board/marzipan/switchcap.c +++ b/board/marzipan/switchcap.c @@ -12,8 +12,8 @@ #include "power/qcom.h" #include "system.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) void board_set_switchcap_power(int enable) { -- cgit v1.2.1 From b563e94e0a88a5c73a642a2c34bc12cb0e4966a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:49 -0600 Subject: board/mithrax/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f8fb58a9247a426972330ee41e9277d24756774 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728466 Reviewed-by: Jeremy Bettis --- board/mithrax/usbc_config.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/board/mithrax/usbc_config.c b/board/mithrax/usbc_config.c index b1b28ab7c2..a39bc22ee8 100644 --- a/board/mithrax/usbc_config.c +++ b/board/mithrax/usbc_config.c @@ -33,8 +33,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ struct tcpc_config_t tcpc_config[] = { @@ -139,24 +139,23 @@ struct usb_mux usb_muxes[] = { BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); static const struct usb_mux usb_muxes_c1 = { - .usb_port = USBC_PORT_C1, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C1_MUX, - .i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR, - .next_mux = &usbc1_tcss_usb_mux, + .usb_port = USBC_PORT_C1, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C1_MUX, + .i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc1_tcss_usb_mux, }; static const struct usb_mux usb_muxes_c2 = { - .usb_port = USBC_PORT_C2, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C2_MUX, - .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, - .next_mux = &usbc2_tcss_usb_mux, + .usb_port = USBC_PORT_C2, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C2_MUX, + .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc2_tcss_usb_mux, }; - /* BC1.2 charger detect configuration */ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { [USBC_PORT_C2] = { @@ -254,7 +253,6 @@ void board_reset_pd_mcu(void) if (ec_cfg_usb_db_type() == DB_USB4_NCT3807) gpio_set_level(GPIO_USB_C1_RST_ODL, 0); - /* * delay for power-on to reset-off and min. assertion time */ @@ -392,10 +390,9 @@ __override bool board_is_dts_port(int port) __override bool board_is_tbt_usb4_port(int port) { - if (((port == USBC_PORT_C2) && - (ec_cfg_usb_mb_type() == MB_USB4_TBT)) || - ((port == USBC_PORT_C1) && - (ec_cfg_usb_db_type() == DB_USB4_NCT3807))) + if (((port == USBC_PORT_C2) && (ec_cfg_usb_mb_type() == MB_USB4_TBT)) || + ((port == USBC_PORT_C1) && + (ec_cfg_usb_db_type() == DB_USB4_NCT3807))) return true; return false; -- cgit v1.2.1 From b53f1db93b3e1a454a19f56aa61d891fd77a521a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:54 -0600 Subject: board/munna/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6df9705bf9c74b75af04a5281983aecf74d9d62b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728710 Reviewed-by: Jeremy Bettis --- board/munna/board.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/board/munna/board.h b/board/munna/board.h index 322f145e33..f31d0809c1 100644 --- a/board/munna/board.h +++ b/board/munna/board.h @@ -27,13 +27,13 @@ #undef STM32_PLLM #undef STM32_PLLN #undef STM32_PLLR -#define STM32_PLLM 1 +#define STM32_PLLM 1 #ifdef STM32_HSE_CLOCK -#define STM32_PLLN 12 +#define STM32_PLLN 12 #else -#define STM32_PLLN 10 +#define STM32_PLLN 10 #endif -#define STM32_PLLR 2 +#define STM32_PLLR 2 #define STM32_USE_PLL @@ -65,13 +65,12 @@ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_POWER_LED -#undef CONFIG_WATCHDOG_PERIOD_MS +#undef CONFIG_WATCHDOG_PERIOD_MS #define CONFIG_WATCHDOG_PERIOD_MS 4000 - /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -93,34 +92,34 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER 2 -#define I2C_PORT_SENSORS 2 -#define I2C_PORT_KB_DISCRETE 2 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_BATTERY 3 -#define I2C_PORT_TCPC0 0 +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER 2 +#define I2C_PORT_SENSORS 2 +#define I2C_PORT_KB_DISCRETE 2 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BATTERY 3 +#define I2C_PORT_TCPC0 0 #undef I2C_CONTROLLER_COUNT #undef I2C_PORT_COUNT -#define I2C_CONTROLLER_COUNT 3 -#define I2C_PORT_COUNT 3 +#define I2C_CONTROLLER_COUNT 3 +#define I2C_PORT_COUNT 3 /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO /* Define the MKBP events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) #undef CONFIG_GMR_TABLET_MODE #undef GPIO_TABLET_MODE_L -- cgit v1.2.1 From ac835a340b517e461bd109fa6be7addedf106e88 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:04 -0600 Subject: include/i2c_peripheral.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic424f65d3fb20d41e97bb51016ffc39c16873ba9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730286 Reviewed-by: Jeremy Bettis --- include/i2c_peripheral.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/i2c_peripheral.h b/include/i2c_peripheral.h index 488e886b0e..2894a39a1a 100644 --- a/include/i2c_peripheral.h +++ b/include/i2c_peripheral.h @@ -10,9 +10,9 @@ /* Data structure to define I2C peripheral port configuration. */ struct i2c_periph_port_t { - const char *name; /* Port name */ - int port; /* Port */ - uint8_t addr; /* address(7-bit without R/W) */ + const char *name; /* Port name */ + int port; /* Port */ + uint8_t addr; /* address(7-bit without R/W) */ }; extern const struct i2c_periph_port_t i2c_periph_ports[]; -- cgit v1.2.1 From d888fb44d7bc6cacbbaab9143b03c7e435c464b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:32 -0600 Subject: chip/npcx/config_chip-npcx5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2471f91f8a1da611b262f1ebca8150e34d26caff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729376 Reviewed-by: Jeremy Bettis --- chip/npcx/config_chip-npcx5.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h index 434caba1d8..e82a13a256 100644 --- a/chip/npcx/config_chip-npcx5.h +++ b/chip/npcx/config_chip-npcx5.h @@ -14,10 +14,10 @@ */ /* Chip ID for all variants */ -#define NPCX585G_CHIP_ID 0x12 -#define NPCX575G_CHIP_ID 0x13 -#define NPCX586G_CHIP_ID 0x16 -#define NPCX576G_CHIP_ID 0x17 +#define NPCX585G_CHIP_ID 0x12 +#define NPCX575G_CHIP_ID 0x13 +#define NPCX586G_CHIP_ID 0x16 +#define NPCX576G_CHIP_ID 0x17 /*****************************************************************************/ /* Hardware features */ @@ -37,18 +37,18 @@ */ #define CONFIG_I2C_MULTI_PORT_CONTROLLER /* Number of I2C controllers */ -#define I2C_CONTROLLER_COUNT 4 +#define I2C_CONTROLLER_COUNT 4 /* Number of I2C ports */ -#define I2C_PORT_COUNT 5 +#define I2C_PORT_COUNT 5 /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /* Use chip variant to specify the size and start address of program memory */ #if defined(CHIP_VARIANT_NPCX5M5G) -- cgit v1.2.1 From 7e018b1c1d5681f3418d6aa549cf6dcd8dec8524 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:58 -0600 Subject: test/usb_tcpmv2_compliance_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I26d6171dda6258508a02e5121d11b60f72f1293f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730572 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_compliance_common.c | 153 +++++++++++++++--------------------- 1 file changed, 63 insertions(+), 90 deletions(-) diff --git a/test/usb_tcpmv2_compliance_common.c b/test/usb_tcpmv2_compliance_common.c index 6145f59388..8127172065 100644 --- a/test/usb_tcpmv2_compliance_common.c +++ b/test/usb_tcpmv2_compliance_common.c @@ -15,9 +15,8 @@ uint32_t rdo = RDO_FIXED(1, 500, 500, 0); uint32_t pdo = PDO_FIXED(5000, 3000, - PDO_FIXED_DUAL_ROLE | - PDO_FIXED_DATA_SWAP | - PDO_FIXED_COMM_CAP); + PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | + PDO_FIXED_COMM_CAP); const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { { @@ -31,25 +30,22 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .driver = &mock_usb_mux_driver, - } -}; - +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .driver = &mock_usb_mux_driver, +} }; -void mock_set_cc(enum mock_connect_result cr, - enum mock_cc_state cc1, enum mock_cc_state cc2) +void mock_set_cc(enum mock_connect_result cr, enum mock_cc_state cc1, + enum mock_cc_state cc2) { mock_tcpci_set_reg(TCPC_REG_CC_STATUS, - TCPC_REG_CC_STATUS_SET(cr, cc1, cc2)); + TCPC_REG_CC_STATUS_SET(cr, cc1, cc2)); } -void mock_set_role(int drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull cc1, enum tcpc_cc_pull cc2) +void mock_set_role(int drp, enum tcpc_rp_value rp, enum tcpc_cc_pull cc1, + enum tcpc_cc_pull cc2) { mock_tcpci_set_reg(TCPC_REG_ROLE_CTRL, - TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)); + TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2)); } static int mock_alert_count; @@ -80,7 +76,9 @@ int pd_check_vconn_swap(int port) return 1; } -void board_reset_pd_mcu(void) {} +void board_reset_pd_mcu(void) +{ +} /***************************************************************************** * Partner utility functions @@ -125,38 +123,31 @@ void partner_tx_msg_id_reset(int sop) partner_tx_id[sop] = 0; } -void partner_send_msg(enum tcpci_msg_type sop, - uint16_t type, - uint16_t cnt, - uint16_t ext, - uint32_t *payload) +void partner_send_msg(enum tcpci_msg_type sop, uint16_t type, uint16_t cnt, + uint16_t ext, uint32_t *payload) { uint16_t header; partner_tx_id[sop] &= 7; header = PD_HEADER(type, - sop == TCPCI_MSG_SOP ? partner_get_power_role() - : PD_PLUG_FROM_CABLE, - partner_get_data_role(), - partner_tx_id[sop], - cnt, - partner_get_pd_rev(), - ext); + sop == TCPCI_MSG_SOP ? partner_get_power_role() : + PD_PLUG_FROM_CABLE, + partner_get_data_role(), partner_tx_id[sop], cnt, + partner_get_pd_rev(), ext); mock_tcpci_receive(sop, header, payload); ++partner_tx_id[sop]; mock_set_alert(TCPC_REG_ALERT_RX_STATUS); } - /***************************************************************************** * TCPCI clean power up */ int tcpci_startup(void) { /* Should be in low power mode before AP boots. */ - TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), - TCPC_REG_COMMAND_I2CIDLE, "%d"); + TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE, + "%d"); task_wait_event(10 * SECOND); hook_notify(HOOK_CHIPSET_STARTUP); @@ -165,12 +156,12 @@ int tcpci_startup(void) task_wait_event(10 * SECOND); /* Should be in low power mode and DRP auto-toggling with AP in S0. */ - TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL) - & TCPC_REG_ROLE_CTRL_DRP_MASK), + TEST_EQ((mock_tcpci_get_reg(TCPC_REG_ROLE_CTRL) & + TCPC_REG_ROLE_CTRL_DRP_MASK), TCPC_REG_ROLE_CTRL_DRP_MASK, "%d"); /* TODO: check previous command was TCPC_REG_COMMAND_LOOK4CONNECTION */ - TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), - TCPC_REG_COMMAND_I2CIDLE, "%d"); + TEST_EQ(mock_tcpci_get_reg(TCPC_REG_COMMAND), TCPC_REG_COMMAND_I2CIDLE, + "%d"); /* TODO: this should be performed in TCPCI mock on startup but needs * more TCPCI functionality added before that can happen. So until @@ -198,13 +189,12 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC), PD_ROLE_DISCONNECTED, "%d"); - partner_set_data_role((data_role == PD_ROLE_UFP) - ? PD_ROLE_DFP - : PD_ROLE_UFP); + partner_set_data_role((data_role == PD_ROLE_UFP) ? PD_ROLE_DFP : + PD_ROLE_UFP); - partner_set_power_role((data_role == PD_ROLE_UFP) - ? PD_ROLE_SOURCE - : PD_ROLE_SINK); + partner_set_power_role((data_role == PD_ROLE_UFP) ? + PD_ROLE_SOURCE : + PD_ROLE_SINK); switch (partner_get_power_role()) { case PD_ROLE_SOURCE: @@ -212,11 +202,10 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) * b) The tester applies Rp (PD3=1.5A, PD2=3A) and * waits for the UUT attachment. */ - mock_set_cc(MOCK_CC_DUT_IS_SNK, - MOCK_CC_SNK_OPEN, - (partner_get_pd_rev() == PD_REV30 - ? MOCK_CC_SNK_RP_1_5 - : MOCK_CC_SNK_RP_3_0)); + mock_set_cc(MOCK_CC_DUT_IS_SNK, MOCK_CC_SNK_OPEN, + (partner_get_pd_rev() == PD_REV30 ? + MOCK_CC_SNK_RP_1_5 : + MOCK_CC_SNK_RP_3_0)); mock_set_alert(TCPC_REG_ALERT_CC_STATUS); task_wait_event(5 * MSEC); @@ -227,11 +216,12 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) /* * d) The tester applies Vbus and waits 50 ms. */ - mock_tcpci_set_reg_bits(TCPC_REG_POWER_STATUS, - TCPC_REG_POWER_STATUS_VBUS_PRES); + mock_tcpci_set_reg_bits( + TCPC_REG_POWER_STATUS, + TCPC_REG_POWER_STATUS_VBUS_PRES); mock_tcpci_clr_reg_bits(TCPC_REG_EXT_STATUS, - TCPC_REG_EXT_STATUS_SAFE0V); + TCPC_REG_EXT_STATUS_SAFE0V); mock_set_alert(TCPC_REG_ALERT_EXT_STATUS | TCPC_REG_ALERT_POWER_STATUS); task_wait_event(50 * MSEC); @@ -242,8 +232,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) * b) The tester applies Rd and waits for Vbus for * tNoResponse max (5.5 s). */ - mock_set_cc(MOCK_CC_DUT_IS_SRC, - MOCK_CC_SRC_OPEN, + mock_set_cc(MOCK_CC_DUT_IS_SRC, MOCK_CC_SRC_OPEN, MOCK_CC_SRC_RD); mock_set_alert(TCPC_REG_ALERT_CC_STATUS); break; @@ -260,7 +249,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) */ task_wait_event(1 * MSEC); partner_send_msg(TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 1, - 0, &pdo); + 0, &pdo); /* * f) The tester waits for the Request from the UUT for @@ -324,8 +313,7 @@ int proc_pd_e1(enum pd_data_role data_role, enum proc_pd_e1_attach attach) TEST_EQ(tc_is_attached_src(PORT0), true, "%d"); break; } - TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC), - data_role, "%d"); + TEST_EQ(pd_get_data_role(I2C_PORT_HOST_TCPC), data_role, "%d"); } return EC_SUCCESS; @@ -390,13 +378,8 @@ int handle_attach_expected_msgs(enum pd_data_role data_role) possible[4].data_msg = 0; do { - rv = verify_tcpci_possible_tx(possible, - 5, - &found_index, - NULL, - 0, - NULL, - -1); + rv = verify_tcpci_possible_tx(possible, 5, &found_index, + NULL, 0, NULL, -1); TEST_NE(rv, EC_ERROR_UNKNOWN, "%d"); if (rv == EC_ERROR_TIMEOUT) @@ -406,30 +389,29 @@ int handle_attach_expected_msgs(enum pd_data_role data_role) task_wait_event(10 * MSEC); switch (found_index) { - case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */ + case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SOURCE_CAP */ partner_send_msg(TCPCI_MSG_SOP, - PD_DATA_SOURCE_CAP, - 1, 0, &pdo); + PD_DATA_SOURCE_CAP, 1, 0, + &pdo); break; case 1: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */ partner_send_msg(TCPCI_MSG_SOP, - PD_DATA_SINK_CAP, - 1, 0, &pdo); + PD_DATA_SINK_CAP, 1, 0, &pdo); break; case 2: /* TCPCI_MSG_SOP_PRIME PD_DATA_VENDOR_DEF */ partner_send_msg(TCPCI_MSG_SOP_PRIME, - PD_CTRL_NOT_SUPPORTED, - 0, 0, NULL); + PD_CTRL_NOT_SUPPORTED, 0, 0, + NULL); break; case 3: /* TCPCI_MSG_SOP PD_DATA_VENDOR_DEF */ partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_NOT_SUPPORTED, - 0, 0, NULL); + PD_CTRL_NOT_SUPPORTED, 0, 0, + NULL); break; case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */ partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_NOT_SUPPORTED, - 0, 0, NULL); + PD_CTRL_NOT_SUPPORTED, 0, 0, + NULL); break; default: TEST_ASSERT(0); @@ -460,13 +442,8 @@ int handle_attach_expected_msgs(enum pd_data_role data_role) possible[4].data_msg = 0; do { - rv = verify_tcpci_possible_tx(possible, - 5, - &found_index, - NULL, - 0, - NULL, - -1); + rv = verify_tcpci_possible_tx(possible, 5, &found_index, + NULL, 0, NULL, -1); TEST_NE(rv, EC_ERROR_UNKNOWN, "%d"); if (rv == EC_ERROR_TIMEOUT) @@ -478,29 +455,25 @@ int handle_attach_expected_msgs(enum pd_data_role data_role) switch (found_index) { case 0: /* TCPCI_MSG_SOP PD_CTRL_GET_SINK_CAP */ partner_send_msg(TCPCI_MSG_SOP, - PD_DATA_SINK_CAP, - 1, 0, &pdo); + PD_DATA_SINK_CAP, 1, 0, &pdo); break; case 1: /* TCPCI_MSG_SOP PD_CTRL_DR_SWAP */ - partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_REJECT, + partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT, 0, 0, NULL); break; - case 2: /* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */ - partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_REJECT, + case 2: /* TCPCI_MSG_SOP PD_CTRL_PR_SWAP */ + partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT, 0, 0, NULL); break; case 3: /* TCPCI_MSG_SOP PD_CTRL_VCONN_SWAP */ TEST_LT(vcs++, 4, "%d"); - partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_REJECT, + partner_send_msg(TCPCI_MSG_SOP, PD_CTRL_REJECT, 0, 0, NULL); break; case 4: /* TCPCI_MSG_SOP PD_CTRL_GET_REVISION */ partner_send_msg(TCPCI_MSG_SOP, - PD_CTRL_NOT_SUPPORTED, - 0, 0, NULL); + PD_CTRL_NOT_SUPPORTED, 0, 0, + NULL); break; default: TEST_ASSERT(0); -- cgit v1.2.1 From 8b749fcf214fe9c7952dcf25c29b7412bf783942 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:58 -0600 Subject: common/chipset.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7ffd08ddb8ca73443b020e4509feda3984949400 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729601 Reviewed-by: Jeremy Bettis --- common/chipset.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/common/chipset.c b/common/chipset.c index 61478f184a..4a3582d5ae 100644 --- a/common/chipset.c +++ b/common/chipset.c @@ -18,7 +18,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /*****************************************************************************/ /* Console commands */ @@ -31,17 +31,14 @@ static int command_apreset(int argc, char **argv) chipset_reset(CHIPSET_RESET_CONSOLE_CMD); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(apreset, command_apreset, - NULL, - "Issue AP reset"); +DECLARE_CONSOLE_COMMAND(apreset, command_apreset, NULL, "Issue AP reset"); static int command_apshutdown(int argc, char **argv) { chipset_force_shutdown(CHIPSET_SHUTDOWN_CONSOLE_CMD); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown, - NULL, +DECLARE_CONSOLE_COMMAND(apshutdown, command_apshutdown, NULL, "Force AP shutdown"); #endif @@ -53,9 +50,7 @@ static enum ec_status host_command_apreset(struct host_cmd_handler_args *args) chipset_reset(CHIPSET_RESET_HOST_CMD); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_AP_RESET, - host_command_apreset, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_AP_RESET, host_command_apreset, EC_VER_MASK(0)); #endif @@ -64,8 +59,7 @@ K_MUTEX_DEFINE(reset_log_mutex); static int next_reset_log __preserved_logs(next_reset_log); static uint32_t ap_resets_since_ec_boot; /* keep reset_logs size a power of 2 */ -static struct ap_reset_log_entry - reset_logs[4] __preserved_logs(reset_logs); +static struct ap_reset_log_entry reset_logs[4] __preserved_logs(reset_logs); static int reset_log_checksum __preserved_logs(reset_log_checksum); /* Calculate reset log checksum */ @@ -113,11 +107,10 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, mutex_lock(&reset_log_mutex); *resets_since_ec_boot = ap_resets_since_ec_boot; - for (i = 0; - i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries; + for (i = 0; i != ARRAY_SIZE(reset_logs) && i != num_reset_log_entries; ++i) { log_address = (next_reset_log + i) & - (ARRAY_SIZE(reset_logs) - 1); + (ARRAY_SIZE(reset_logs) - 1); reset_log_entries[i] = reset_logs[log_address]; } mutex_unlock(&reset_log_mutex); @@ -125,4 +118,4 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, return EC_SUCCESS; } -#endif /* !CONFIG_AP_RESET_LOG */ +#endif /* !CONFIG_AP_RESET_LOG */ -- cgit v1.2.1 From 2310775ade189ed07b5ee08c89d21c78d76782e8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:55 -0600 Subject: include/driver/accelgyro_bmi260.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib53918b5910763a36b1f49d10db329b335e70fd6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730106 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi260.h | 544 +++++++++++++++++++------------------- 1 file changed, 272 insertions(+), 272 deletions(-) diff --git a/include/driver/accelgyro_bmi260.h b/include/driver/accelgyro_bmi260.h index fb5db82afb..a063539fb7 100644 --- a/include/driver/accelgyro_bmi260.h +++ b/include/driver/accelgyro_bmi260.h @@ -13,320 +13,320 @@ #include "mag_bmm150.h" #include "driver/accelgyro_bmi260_public.h" -#define BMI260_CHIP_ID 0x00 +#define BMI260_CHIP_ID 0x00 /* BMI260 chip identifier */ -#define BMI260_CHIP_ID_MAJOR 0x27 +#define BMI260_CHIP_ID_MAJOR 0x27 /* BMI220 chip identifier */ -#define BMI220_CHIP_ID_MAJOR 0x26 - -#define BMI260_ERR_REG 0x02 - -#define BMI260_STATUS 0x03 -#define BMI260_AUX_BUSY BIT(2) -#define BMI260_CMD_RDY BIT(4) -#define BMI260_DRDY_AUX BIT(5) -#define BMI260_DRDY_GYR BIT(6) -#define BMI260_DRDY_ACC BIT(7) -#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) -#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) - -#define BMI260_AUX_X_L_G 0x04 -#define BMI260_AUX_X_H_G 0x05 -#define BMI260_AUX_Y_L_G 0x06 -#define BMI260_AUX_Y_H_G 0x07 -#define BMI260_AUX_Z_L_G 0x08 -#define BMI260_AUX_Z_H_G 0x09 -#define BMI260_AUX_R_L_G 0x0a -#define BMI260_AUX_R_H_G 0x0b -#define BMI260_ACC_X_L_G 0x0c -#define BMI260_ACC_X_H_G 0x0d -#define BMI260_ACC_Y_L_G 0x0e -#define BMI260_ACC_Y_H_G 0x0f -#define BMI260_ACC_Z_L_G 0x10 -#define BMI260_ACC_Z_H_G 0x11 -#define BMI260_GYR_X_L_G 0x12 -#define BMI260_GYR_X_H_G 0x13 -#define BMI260_GYR_Y_L_G 0x14 -#define BMI260_GYR_Y_H_G 0x15 -#define BMI260_GYR_Z_L_G 0x16 -#define BMI260_GYR_Z_H_G 0x17 - -#define BMI260_SENSORTIME_0 0x18 -#define BMI260_SENSORTIME_1 0x19 -#define BMI260_SENSORTIME_2 0x1a - -#define BMI260_EVENT 0x1b +#define BMI220_CHIP_ID_MAJOR 0x26 + +#define BMI260_ERR_REG 0x02 + +#define BMI260_STATUS 0x03 +#define BMI260_AUX_BUSY BIT(2) +#define BMI260_CMD_RDY BIT(4) +#define BMI260_DRDY_AUX BIT(5) +#define BMI260_DRDY_GYR BIT(6) +#define BMI260_DRDY_ACC BIT(7) +#define BMI260_DRDY_OFF(_sensor) (7 - (_sensor)) +#define BMI260_DRDY_MASK(_sensor) (1 << BMI260_DRDY_OFF(_sensor)) + +#define BMI260_AUX_X_L_G 0x04 +#define BMI260_AUX_X_H_G 0x05 +#define BMI260_AUX_Y_L_G 0x06 +#define BMI260_AUX_Y_H_G 0x07 +#define BMI260_AUX_Z_L_G 0x08 +#define BMI260_AUX_Z_H_G 0x09 +#define BMI260_AUX_R_L_G 0x0a +#define BMI260_AUX_R_H_G 0x0b +#define BMI260_ACC_X_L_G 0x0c +#define BMI260_ACC_X_H_G 0x0d +#define BMI260_ACC_Y_L_G 0x0e +#define BMI260_ACC_Y_H_G 0x0f +#define BMI260_ACC_Z_L_G 0x10 +#define BMI260_ACC_Z_H_G 0x11 +#define BMI260_GYR_X_L_G 0x12 +#define BMI260_GYR_X_H_G 0x13 +#define BMI260_GYR_Y_L_G 0x14 +#define BMI260_GYR_Y_H_G 0x15 +#define BMI260_GYR_Z_L_G 0x16 +#define BMI260_GYR_Z_H_G 0x17 + +#define BMI260_SENSORTIME_0 0x18 +#define BMI260_SENSORTIME_1 0x19 +#define BMI260_SENSORTIME_2 0x1a + +#define BMI260_EVENT 0x1b /* 2 bytes interrupt reasons*/ -#define BMI260_INT_STATUS_0 0x1c -#define BMI260_SIG_MOTION_OUT BIT(0) -#define BMI260_STEP_COUNTER_OUT BIT(1) -#define BMI260_HIGH_LOW_G_OUT BIT(2) -#define BMI260_TAP_OUT BIT(3) -#define BMI260_FLAT_OUT BIT(4) -#define BMI260_NO_MOTION_OUT BIT(5) -#define BMI260_ANY_MOTION_OUT BIT(6) -#define BMI260_ORIENTATION_OUT BIT(7) - -#define BMI260_INT_STATUS_1 0x1d -#define BMI260_FFULL_INT BIT(0 + 8) -#define BMI260_FWM_INT BIT(1 + 8) -#define BMI260_ERR_INT BIT(2 + 8) -#define BMI260_AUX_DRDY_INT BIT(5 + 8) -#define BMI260_GYR_DRDY_INT BIT(6 + 8) -#define BMI260_ACC_DRDY_INT BIT(7 + 8) - -#define BMI260_INT_MASK 0xFFFF - -#define BMI260_SC_OUT_0 0x1e -#define BMI260_SC_OUT_1 0x1f - -#define BMI260_ORIENT_ACT 0x20 - -#define BMI260_INTERNAL_STATUS 0X21 -#define BMI260_MESSAGE_MASK 0xf -#define BMI260_NOT_INIT 0x00 -#define BMI260_INIT_OK 0x01 -#define BMI260_INIT_ERR 0x02 -#define BMI260_DRV_ERR 0x03 -#define BMI260_SNS_STOP 0x04 -#define BMI260_NVM_ERROR 0x05 -#define BMI260_START_UP_ERROR 0x06 -#define BMI260_COMPAT_ERROR 0x07 - -#define BMI260_TEMPERATURE_0 0x22 -#define BMI260_TEMPERATURE_1 0x23 - -#define BMI260_FIFO_LENGTH_0 0x24 -#define BMI260_FIFO_LENGTH_1 0x25 -#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) -#define BMI260_FIFO_DATA 0x26 - -#define BMI260_FEAT_PAGE 0x2f +#define BMI260_INT_STATUS_0 0x1c +#define BMI260_SIG_MOTION_OUT BIT(0) +#define BMI260_STEP_COUNTER_OUT BIT(1) +#define BMI260_HIGH_LOW_G_OUT BIT(2) +#define BMI260_TAP_OUT BIT(3) +#define BMI260_FLAT_OUT BIT(4) +#define BMI260_NO_MOTION_OUT BIT(5) +#define BMI260_ANY_MOTION_OUT BIT(6) +#define BMI260_ORIENTATION_OUT BIT(7) + +#define BMI260_INT_STATUS_1 0x1d +#define BMI260_FFULL_INT BIT(0 + 8) +#define BMI260_FWM_INT BIT(1 + 8) +#define BMI260_ERR_INT BIT(2 + 8) +#define BMI260_AUX_DRDY_INT BIT(5 + 8) +#define BMI260_GYR_DRDY_INT BIT(6 + 8) +#define BMI260_ACC_DRDY_INT BIT(7 + 8) + +#define BMI260_INT_MASK 0xFFFF + +#define BMI260_SC_OUT_0 0x1e +#define BMI260_SC_OUT_1 0x1f + +#define BMI260_ORIENT_ACT 0x20 + +#define BMI260_INTERNAL_STATUS 0X21 +#define BMI260_MESSAGE_MASK 0xf +#define BMI260_NOT_INIT 0x00 +#define BMI260_INIT_OK 0x01 +#define BMI260_INIT_ERR 0x02 +#define BMI260_DRV_ERR 0x03 +#define BMI260_SNS_STOP 0x04 +#define BMI260_NVM_ERROR 0x05 +#define BMI260_START_UP_ERROR 0x06 +#define BMI260_COMPAT_ERROR 0x07 + +#define BMI260_TEMPERATURE_0 0x22 +#define BMI260_TEMPERATURE_1 0x23 + +#define BMI260_FIFO_LENGTH_0 0x24 +#define BMI260_FIFO_LENGTH_1 0x25 +#define BMI260_FIFO_LENGTH_MASK (BIT(14) - 1) +#define BMI260_FIFO_DATA 0x26 + +#define BMI260_FEAT_PAGE 0x2f /* * The register of feature page should be read/write as 16-bit register * Otherwise, there can be invalid data */ /* Features page 0 */ -#define BMI260_ORIENT_OUT 0x36 -#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 -#define BMI260_ORIENT_PORTRAIT 0x0 -#define BMI260_ORIENT_LANDSCAPE 0x1 -#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 -#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 +#define BMI260_ORIENT_OUT 0x36 +#define BMI260_ORIENT_OUT_PORTRAIT_LANDSCAPE_MASK 3 +#define BMI260_ORIENT_PORTRAIT 0x0 +#define BMI260_ORIENT_LANDSCAPE 0x1 +#define BMI260_ORIENT_PORTRAIT_INVERT 0x2 +#define BMI260_ORIENT_LANDSCAPE_INVERT 0x3 /* Features page 1 */ -#define BMI260_GEN_SET_1 0x34 -#define BMI260_GYR_SELF_OFF BIT(9) +#define BMI260_GEN_SET_1 0x34 +#define BMI260_GYR_SELF_OFF BIT(9) -#define BMI260_TAP_1 0x3e -#define BMI260_TAP_1_EN BIT(0) -#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 -#define BMI260_TAP_1_SENSITIVITY_MASK \ - (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) +#define BMI260_TAP_1 0x3e +#define BMI260_TAP_1_EN BIT(0) +#define BMI260_TAP_1_SENSITIVITY_OFFSET 1 +#define BMI260_TAP_1_SENSITIVITY_MASK (0x7 << BMI260_TAP_1_SENSITIVITY_OFFSET) /* Features page 2 */ -#define BMI260_ORIENT_1 0x30 -#define BMI260_ORIENT_1_EN BIT(0) -#define BMI260_ORIENT_1_UD_EN BIT(1) +#define BMI260_ORIENT_1 0x30 +#define BMI260_ORIENT_1_EN BIT(0) +#define BMI260_ORIENT_1_UD_EN BIT(1) #define BMI260_ORIENT_1_MODE_OFFSET 2 -#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) -#define BMI260_ORIENT_1_BLOCK_OFFSET 4 -#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) -#define BMI260_ORIENT_1_THETA_OFFSET 6 -#define BMI260_ORIENT_1_THETA_MASK \ +#define BMI260_ORIENT_1_MODE_MASK (0x3 << BMI260_ORIENT_1_MODE_OFFSET) +#define BMI260_ORIENT_1_BLOCK_OFFSET 4 +#define BMI260_ORIENT_1_BLOCK_MASK (0x3 << BMI260_ORIENT_1_BLOCK_OFFSET) +#define BMI260_ORIENT_1_THETA_OFFSET 6 +#define BMI260_ORIENT_1_THETA_MASK \ ((BIT(6) - 1) << BMI260_ORIENT_1_THETA_OFFSET) -#define BMI260_ORIENT_2 0x32 +#define BMI260_ORIENT_2 0x32 /* hysteresis(10...0) range is 0~1g, default is 128 (0.0625g) */ -#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) +#define BMI260_ORIENT_2_HYSTERESIS_MASK (BIT(11) - 1) -#define BMI260_ACC_CONF 0x40 -#define BMI260_ACC_BW_OFFSET 4 -#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) -#define BMI260_FILTER_PERF BIT(7) -#define BMI260_ULP 0x0 -#define BMI260_HP 0x1 +#define BMI260_ACC_CONF 0x40 +#define BMI260_ACC_BW_OFFSET 4 +#define BMI260_ACC_BW_MASK (0x7 << BMI260_ACC_BW_OFFSET) +#define BMI260_FILTER_PERF BIT(7) +#define BMI260_ULP 0x0 +#define BMI260_HP 0x1 -#define BMI260_ACC_RANGE 0x41 -#define BMI260_GSEL_2G 0x00 -#define BMI260_GSEL_4G 0x01 -#define BMI260_GSEL_8G 0x02 -#define BMI260_GSEL_16G 0x03 +#define BMI260_ACC_RANGE 0x41 +#define BMI260_GSEL_2G 0x00 +#define BMI260_GSEL_4G 0x01 +#define BMI260_GSEL_8G 0x02 +#define BMI260_GSEL_16G 0x03 /* The max positvie value of accel data is 0x7FFF, equal to range(g) */ /* So, in order to get +1g, divide the 0x7FFF by range */ #define BMI260_ACC_DATA_PLUS_1G(range) (0x7FFF / (range)) #define BMI260_ACC_DATA_MINUS_1G(range) (-BMI260_ACC_DATA_PLUS_1G(range)) -#define BMI260_GYR_CONF 0x42 -#define BMI260_GYR_BW_OFFSET 4 -#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) -#define BMI260_GYR_NOISE_PERF BIT(6) - -#define BMI260_GYR_RANGE 0x43 -#define BMI260_DPS_SEL_2000 0x00 -#define BMI260_DPS_SEL_1000 0x01 -#define BMI260_DPS_SEL_500 0x02 -#define BMI260_DPS_SEL_250 0x03 -#define BMI260_DPS_SEL_125 0x04 - -#define BMI260_AUX_CONF 0x44 - -#define BMI260_FIFO_DOWNS 0x45 - -#define BMI260_FIFO_WTM_0 0x46 -#define BMI260_FIFO_WTM_1 0x47 - -#define BMI260_FIFO_CONFIG_0 0x48 -#define BMI260_FIFO_STOP_ON_FULL BIT(0) -#define BMI260_FIFO_TIME_EN BIT(1) - -#define BMI260_FIFO_CONFIG_1 0x49 -#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 -#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) -#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 -#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) -#define BMI260_FIFO_TAG_INT_EDGE 0x0 -#define BMI260_FIFO_TAG_INT_LEVEL 0x1 -#define BMI260_FIFO_TAG_ACC_SAT 0x2 -#define BMI260_FIFO_TAG_GYR_SAT 0x3 -#define BMI260_FIFO_HEADER_EN BIT(4) -#define BMI260_FIFO_AUX_EN BIT(5) -#define BMI260_FIFO_ACC_EN BIT(6) -#define BMI260_FIFO_GYR_EN BIT(7) -#define BMI260_FIFO_SENSOR_EN(_sensor) \ - ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? BMI260_FIFO_ACC_EN : \ - ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ - BMI260_FIFO_AUX_EN)) - -#define BMI260_SATURATION 0x4a - -#define BMI260_AUX_DEV_ID 0x4b -#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID - -#define BMI260_AUX_IF_CONF 0x4c -#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF -#define BMI260_AUX_READ_BURST_MASK 3 -#define BMI260_AUX_MAN_READ_BURST_OFF 2 -#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) -#define BMI260_AUX_READ_BURST_1 0 -#define BMI260_AUX_READ_BURST_2 1 -#define BMI260_AUX_READ_BURST_6 2 -#define BMI260_AUX_READ_BURST_8 3 -#define BMI260_AUX_FCU_WRITE_EN BIT(6) -#define BMI260_AUX_MANUAL_EN BIT(7) - -#define BMI260_AUX_RD_ADDR 0x4d -#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR -#define BMI260_AUX_WR_ADDR 0x4e -#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR -#define BMI260_AUX_WR_DATA 0x4f -#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA -#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G - -#define BMI260_ERR_REG_MSK 0x52 -#define BMI260_FATAL_ERR BIT(0) -#define BMI260_INTERNAL_ERR_OFF 1 -#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) -#define BMI260_FIFO_ERR BIT(6) -#define BMI260_AUX_ERR BIT(7) - -#define BMI260_INT1_IO_CTRL 0x53 -#define BMI260_INT1_LVL BIT(1) -#define BMI260_INT1_OD BIT(2) -#define BMI260_INT1_OUTPUT_EN BIT(3) -#define BMI260_INT1_INPUT_EN BIT(4) - -#define BMI260_INT2_IO_CTRL 0x54 -#define BMI260_INT2_LVL BIT(1) -#define BMI260_INT2_OD BIT(2) -#define BMI260_INT2_OUTPUT_EN BIT(3) -#define BMI260_INT2_INPUT_EN BIT(4) - -#define BMI260_INT_LATCH 0x55 -#define BMI260_INT_LATCH_EN BIT(0) - -#define BMI260_INT1_MAP_FEAT 0x56 -#define BMI260_INT2_MAP_FEAT 0x57 -#define BMI260_MAP_SIG_MOTION_OUT BIT(0) +#define BMI260_GYR_CONF 0x42 +#define BMI260_GYR_BW_OFFSET 4 +#define BMI260_GYR_BW_MASK (0x3 << BMI260_GYR_BW_OFFSET) +#define BMI260_GYR_NOISE_PERF BIT(6) + +#define BMI260_GYR_RANGE 0x43 +#define BMI260_DPS_SEL_2000 0x00 +#define BMI260_DPS_SEL_1000 0x01 +#define BMI260_DPS_SEL_500 0x02 +#define BMI260_DPS_SEL_250 0x03 +#define BMI260_DPS_SEL_125 0x04 + +#define BMI260_AUX_CONF 0x44 + +#define BMI260_FIFO_DOWNS 0x45 + +#define BMI260_FIFO_WTM_0 0x46 +#define BMI260_FIFO_WTM_1 0x47 + +#define BMI260_FIFO_CONFIG_0 0x48 +#define BMI260_FIFO_STOP_ON_FULL BIT(0) +#define BMI260_FIFO_TIME_EN BIT(1) + +#define BMI260_FIFO_CONFIG_1 0x49 +#define BMI260_FIFO_TAG_INT1_EN_OFFSET 0 +#define BMI260_FIFO_TAG_INT1_EN_MASK (0x3 << BMI260_FIFO_TAG_INT1_EN_OFFSET) +#define BMI260_FIFO_TAG_INT2_EN_OFFSET 2 +#define BMI260_FIFO_TAG_INT2_EN_MASK (0x3 << BMI260_FIFO_TAG_INT2_EN_OFFSET) +#define BMI260_FIFO_TAG_INT_EDGE 0x0 +#define BMI260_FIFO_TAG_INT_LEVEL 0x1 +#define BMI260_FIFO_TAG_ACC_SAT 0x2 +#define BMI260_FIFO_TAG_GYR_SAT 0x3 +#define BMI260_FIFO_HEADER_EN BIT(4) +#define BMI260_FIFO_AUX_EN BIT(5) +#define BMI260_FIFO_ACC_EN BIT(6) +#define BMI260_FIFO_GYR_EN BIT(7) +#define BMI260_FIFO_SENSOR_EN(_sensor) \ + ((_sensor) == MOTIONSENSE_TYPE_ACCEL ? \ + BMI260_FIFO_ACC_EN : \ + ((_sensor) == MOTIONSENSE_TYPE_GYRO ? BMI260_FIFO_GYR_EN : \ + BMI260_FIFO_AUX_EN)) + +#define BMI260_SATURATION 0x4a + +#define BMI260_AUX_DEV_ID 0x4b +#define BMI260_AUX_I2C_ADDRESS BMI260_AUX_DEV_ID + +#define BMI260_AUX_IF_CONF 0x4c +#define BMI260_AUX_I2C_CONTROL BMI260_AUX_IF_CONF +#define BMI260_AUX_READ_BURST_MASK 3 +#define BMI260_AUX_MAN_READ_BURST_OFF 2 +#define BMI260_AUX_MAN_READ_BURST_MASK (0x3 << BMI280_AUX_MAN_READ_BURST_OFF) +#define BMI260_AUX_READ_BURST_1 0 +#define BMI260_AUX_READ_BURST_2 1 +#define BMI260_AUX_READ_BURST_6 2 +#define BMI260_AUX_READ_BURST_8 3 +#define BMI260_AUX_FCU_WRITE_EN BIT(6) +#define BMI260_AUX_MANUAL_EN BIT(7) + +#define BMI260_AUX_RD_ADDR 0x4d +#define BMI260_AUX_I2C_READ_ADDR BMI260_AUX_RD_ADDR +#define BMI260_AUX_WR_ADDR 0x4e +#define BMI260_AUX_I2C_WRITE_ADDR BMI260_AUX_WR_ADDR +#define BMI260_AUX_WR_DATA 0x4f +#define BMI260_AUX_I2C_WRITE_DATA BMI260_AUX_WR_DATA +#define BMI260_AUX_I2C_READ_DATA BMI260_AUX_X_L_G + +#define BMI260_ERR_REG_MSK 0x52 +#define BMI260_FATAL_ERR BIT(0) +#define BMI260_INTERNAL_ERR_OFF 1 +#define BMI260_INTERNAL_ERR_MASK (0xf << BMI260_INTERNAL_ERR_OFF) +#define BMI260_FIFO_ERR BIT(6) +#define BMI260_AUX_ERR BIT(7) + +#define BMI260_INT1_IO_CTRL 0x53 +#define BMI260_INT1_LVL BIT(1) +#define BMI260_INT1_OD BIT(2) +#define BMI260_INT1_OUTPUT_EN BIT(3) +#define BMI260_INT1_INPUT_EN BIT(4) + +#define BMI260_INT2_IO_CTRL 0x54 +#define BMI260_INT2_LVL BIT(1) +#define BMI260_INT2_OD BIT(2) +#define BMI260_INT2_OUTPUT_EN BIT(3) +#define BMI260_INT2_INPUT_EN BIT(4) + +#define BMI260_INT_LATCH 0x55 +#define BMI260_INT_LATCH_EN BIT(0) + +#define BMI260_INT1_MAP_FEAT 0x56 +#define BMI260_INT2_MAP_FEAT 0x57 +#define BMI260_MAP_SIG_MOTION_OUT BIT(0) #define BMI260_MAP_STEP_COUNTER_OUT BIT(1) -#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) -#define BMI260_MAP_TAP_OUT BIT(3) -#define BMI260_MAP_FLAT_OUT BIT(4) -#define BMI260_MAP_NO_MOTION_OUT BIT(5) -#define BMI260_MAP_ANY_MOTION_OUT BIT(6) -#define BMI260_MAP_ORIENTAION_OUT BIT(7) - -#define BMI260_INT_MAP_DATA 0x58 -#define BMI260_MAP_FFULL_INT BIT(0) -#define BMI260_MAP_FWM_INT BIT(1) -#define BMI260_MAP_DRDY_INT BIT(2) -#define BMI260_MAP_ERR_INT BIT(3) -#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 -#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 +#define BMI260_MAP_HIGH_LOW_G_OUT BIT(2) +#define BMI260_MAP_TAP_OUT BIT(3) +#define BMI260_MAP_FLAT_OUT BIT(4) +#define BMI260_MAP_NO_MOTION_OUT BIT(5) +#define BMI260_MAP_ANY_MOTION_OUT BIT(6) +#define BMI260_MAP_ORIENTAION_OUT BIT(7) + +#define BMI260_INT_MAP_DATA 0x58 +#define BMI260_MAP_FFULL_INT BIT(0) +#define BMI260_MAP_FWM_INT BIT(1) +#define BMI260_MAP_DRDY_INT BIT(2) +#define BMI260_MAP_ERR_INT BIT(3) +#define BMI260_INT_MAP_DATA_INT1_OFFSET 0 +#define BMI260_INT_MAP_DATA_INT2_OFFSET 4 #define BMI260_INT_MAP_DATA_REG(_i, _bit) \ - (CONCAT3(BMI260_MAP_, _bit, _INT) << \ - CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) + (CONCAT3(BMI260_MAP_, _bit, _INT) \ + << CONCAT3(BMI260_INT_MAP_DATA_INT, _i, _OFFSET)) -#define BMI260_INIT_CTRL 0x59 -#define BMI260_INIT_ADDR_0 0x5b -#define BMI260_INIT_ADDR_1 0x5c -#define BMI260_INIT_DATA 0x5e -#define BMI260_INTERNAL_ERROR 0x5f -#define BMI260_INT_ERR_1 BIT(1) -#define BMI260_INT_ERR_2 BIT(2) -#define BMI260_FEAT_ENG_DISABLED BIT(4) +#define BMI260_INIT_CTRL 0x59 +#define BMI260_INIT_ADDR_0 0x5b +#define BMI260_INIT_ADDR_1 0x5c +#define BMI260_INIT_DATA 0x5e +#define BMI260_INTERNAL_ERROR 0x5f +#define BMI260_INT_ERR_1 BIT(1) +#define BMI260_INT_ERR_2 BIT(2) +#define BMI260_FEAT_ENG_DISABLED BIT(4) -#define BMI260_AUX_IF_TRIM 0x68 -#define BMI260_GYR_CRT_CONF 0x69 +#define BMI260_AUX_IF_TRIM 0x68 +#define BMI260_GYR_CRT_CONF 0x69 -#define BMI260_NVM_CONF 0x6a -#define BMI260_NVM_PROG_EN BIT(1) +#define BMI260_NVM_CONF 0x6a +#define BMI260_NVM_PROG_EN BIT(1) -#define BMI260_IF_CONF 0x6b -#define BMI260_IF_SPI3 BIT(0) -#define BMI260_IF_SPI3_OIS BIT(1) -#define BMI260_IF_OIS_EN BIT(4) -#define BMI260_IF_AUX_EN BIT(5) +#define BMI260_IF_CONF 0x6b +#define BMI260_IF_SPI3 BIT(0) +#define BMI260_IF_SPI3_OIS BIT(1) +#define BMI260_IF_OIS_EN BIT(4) +#define BMI260_IF_AUX_EN BIT(5) -#define BMI260_DRV 0x6c -#define BMI260_ACC_SELF_TEST 0x6d +#define BMI260_DRV 0x6c +#define BMI260_ACC_SELF_TEST 0x6d #define BMI260_GYR_SELF_TEST_AXES 0x6e -#define BMI260_NV_CONF 0x70 -#define BMI260_ACC_OFFSET_EN BIT(3) +#define BMI260_NV_CONF 0x70 +#define BMI260_ACC_OFFSET_EN BIT(3) -#define BMI260_OFFSET_ACC70 0x71 -#define BMI260_OFFSET_GYR70 0x74 -#define BMI260_OFFSET_EN_GYR98 0x77 -#define BMI260_OFFSET_GYRO_EN BIT(6) -#define BMI260_GYR_GAIN_EN BIT(7) +#define BMI260_OFFSET_ACC70 0x71 +#define BMI260_OFFSET_GYR70 0x74 +#define BMI260_OFFSET_EN_GYR98 0x77 +#define BMI260_OFFSET_GYRO_EN BIT(6) +#define BMI260_GYR_GAIN_EN BIT(7) -#define BMI260_PWR_CONF 0x7c -#define BMI260_ADV_POWER_SAVE BIT(0) -#define BMI260_FIFO_SELF_WAKE_UP BIT(1) -#define BMI260_FUP_EN BIT(2) +#define BMI260_PWR_CONF 0x7c +#define BMI260_ADV_POWER_SAVE BIT(0) +#define BMI260_FIFO_SELF_WAKE_UP BIT(1) +#define BMI260_FUP_EN BIT(2) -#define BMI260_PWR_CTRL 0x7d -#define BMI260_AUX_EN BIT(0) -#define BMI260_GYR_EN BIT(1) -#define BMI260_ACC_EN BIT(2) +#define BMI260_PWR_CTRL 0x7d +#define BMI260_AUX_EN BIT(0) +#define BMI260_GYR_EN BIT(1) +#define BMI260_ACC_EN BIT(2) #define BMI260_PWR_EN(_sensor_type) BIT(2 - _sensor_type) -#define BMI260_TEMP_EN BIT(3) +#define BMI260_TEMP_EN BIT(3) -#define BMI260_CMD_REG 0x7e -#define BMI260_CMD_FIFO_FLUSH 0xb0 -#define BMI260_CMD_SOFT_RESET 0xb6 +#define BMI260_CMD_REG 0x7e +#define BMI260_CMD_FIFO_FLUSH 0xb0 +#define BMI260_CMD_SOFT_RESET 0xb6 -#define BMI260_FF_FRAME_LEN_TS 4 -#define BMI260_FF_DATA_LEN_ACC 6 -#define BMI260_FF_DATA_LEN_GYR 6 -#define BMI260_FF_DATA_LEN_MAG 8 +#define BMI260_FF_FRAME_LEN_TS 4 +#define BMI260_FF_DATA_LEN_ACC 6 +#define BMI260_FF_DATA_LEN_GYR 6 +#define BMI260_FF_DATA_LEN_MAG 8 /* Root mean square noise of 100Hz accelerometer, units: ug */ -#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 +#define BMI260_ACCEL_RMS_NOISE_100HZ 1060 #if defined(CONFIG_ZEPHYR) #if DT_NODE_EXISTS(DT_ALIAS(bmi260_int)) @@ -343,9 +343,9 @@ * bmi260-int = &base_accel; * }; */ -#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ +#define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi260_int))) #endif -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ #endif /* __CROS_EC_ACCELGYRO_BMI260_H */ -- cgit v1.2.1 From 61313d3c94a8b80a66a5452630baae9b3e7a9bf7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:55 -0600 Subject: core/cortex-m/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib2186f2f662542398c1a48a6052f47e15792b6c8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729826 Reviewed-by: Jeremy Bettis --- core/cortex-m/task.c | 152 ++++++++++++++++++++++++--------------------------- 1 file changed, 70 insertions(+), 82 deletions(-) diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 0747978f7e..8c46bc0161 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -22,10 +22,10 @@ typedef union { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ }; } task_; @@ -41,12 +41,10 @@ CONFIG_CTS_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -56,12 +54,12 @@ static uint64_t task_start_time; /* Time task scheduling started */ * We only keep 32-bit values for exception start/end time, to avoid * accounting errors when we service interrupt when the timer wraps around. */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern void __switchto(task_ *from, task_ *to); @@ -92,14 +90,13 @@ void __idle(void) * shortly therefore, resumes execution on exiting idle mode. * Workaround: Replace the idle function with the followings */ - asm ( - "cpsid i\n" /* Disable interrupt */ - "push {r0-r5}\n" /* Save needed registers */ - "wfi\n" /* Wait for int to enter idle */ - "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ - "pop {r0-r5}\n" /* Restore regs before enabling ints */ - "isb\n" /* Flush the cpu pipeline */ - "cpsie i\n" :: "r" (0x100A8000) /* Enable interrupts */ + asm("cpsid i\n" /* Disable interrupt */ + "push {r0-r5}\n" /* Save needed registers */ + "wfi\n" /* Wait for int to enter idle */ + "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ + "pop {r0-r5}\n" /* Restore regs before enabling ints */ + "isb\n" /* Flush the cpu pipeline */ + "cpsie i\n" ::"r"(0x100A8000) /* Enable interrupts */ ); #else /* @@ -122,20 +119,19 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .r0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .r0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t r0; uint32_t pc; uint16_t stack_size; } tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST CONFIG_CTS_TASK_LIST }; #undef TASK @@ -143,17 +139,16 @@ static const struct { static task_ tasks[TASK_ID_COUNT]; /* Reset constants and state for all tasks */ -#define TASK_RESET_SUPPORTED BIT(31) -#define TASK_RESET_LOCK BIT(30) -#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) -#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK -#define TASK_RESET_UNSUPPORTED 0 -#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) -#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED +#define TASK_RESET_SUPPORTED BIT(31) +#define TASK_RESET_LOCK BIT(30) +#define TASK_RESET_STATE_MASK (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) +#define TASK_RESET_WAITERS_MASK ~TASK_RESET_STATE_MASK +#define TASK_RESET_UNSUPPORTED 0 +#define TASK_RESET_STATE_LOCKED (TASK_RESET_SUPPORTED | TASK_RESET_LOCK) +#define TASK_RESET_STATE_UNLOCKED TASK_RESET_SUPPORTED #ifdef CONFIG_TASK_RESET_LIST -#define ENABLE_RESET(n) \ - [TASK_ID_##n] = TASK_RESET_SUPPORTED, +#define ENABLE_RESET(n) [TASK_ID_##n] = TASK_RESET_SUPPORTED, static uint32_t task_reset_state[TASK_ID_COUNT] = { #ifdef CONFIG_TASK_RESET_LIST CONFIG_TASK_RESET_LIST @@ -168,13 +163,10 @@ BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); BUILD_ASSERT(BIT(TASK_ID_COUNT) < TASK_RESET_LOCK); /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST - CONFIG_CTS_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST + CONFIG_CTS_TASK_LIST] __aligned(8); #undef TASK @@ -211,7 +203,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -static int start_called; /* Has task swapping started */ +static int start_called; /* Has task swapping started */ static inline task_ *__task_id_to_ptr(task_id_t id) { @@ -233,7 +225,7 @@ inline bool is_interrupt_enabled(void) int primask; /* Interrupts are enabled when PRIMASK bit is 0 */ - asm("mrs %0, primask":"=r"(primask)); + asm("mrs %0, primask" : "=r"(primask)); return !(primask & 0x1); } @@ -241,8 +233,9 @@ inline bool is_interrupt_enabled(void) inline bool in_interrupt_context(void) { int ret; - asm("mrs %0, ipsr \n" /* read exception number */ - "lsl %0, #23 \n":"=r"(ret)); /* exception bits are the 9 LSB */ + asm("mrs %0, ipsr \n" /* read exception number */ + "lsl %0, #23 \n" + : "=r"(ret)); /* exception bits are the 9 LSB */ return ret; } @@ -250,8 +243,8 @@ inline bool in_interrupt_context(void) static inline int get_interrupt_context(void) { int ret; - asm("mrs %0, ipsr \n":"=r"(ret)); /* read exception number */ - return ret & 0x1ff; /* exception bits are the 9 LSB */ + asm("mrs %0, ipsr \n" : "=r"(ret)); /* read exception number */ + return ret & 0x1ff; /* exception bits are the 9 LSB */ } #endif @@ -352,7 +345,7 @@ void svc_handler(int desched, task_id_t resched) if (next == current) return; - /* Switch to new task */ + /* Switch to new task */ #ifdef CONFIG_TASK_PROFILING task_switches++; #endif @@ -365,7 +358,7 @@ void __schedule(int desched, int resched) register int p0 asm("r0") = desched; register int p1 asm("r1") = resched; - asm("svc 0"::"r"(p0),"r"(p1)); + asm("svc 0" ::"r"(p0), "r"(p1)); } #ifdef CONFIG_TASK_PROFILING @@ -390,9 +383,9 @@ void __keep task_start_irq_handler(void *excep_return) * and we are not called from another exception (this must match the * logic for when we chain to svc_handler() below). */ - if (!need_resched_or_profiling - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!need_resched_or_profiling || + (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; exc_start_time = t; @@ -405,9 +398,9 @@ void __keep task_resched_if_needed(void *excep_return) * Continue iff a rescheduling event happened or profiling is active, * and we are not called from another exception. */ - if (!need_resched_or_profiling - || (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) - == EXC_RETURN_MODE_HANDLER)) + if (!need_resched_or_profiling || + (((uint32_t)excep_return & EXC_RETURN_MODE_MASK) == + EXC_RETURN_MODE_HANDLER)) return; svc_handler(0, 0); @@ -571,10 +564,10 @@ static uint32_t init_task_context(task_id_t id) tasks[id].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[8] = tasks_init[id].r0; /* r0 */ - sp[13] = (uint32_t)task_exit_trap; /* lr */ - sp[14] = tasks_init[id].pc; /* pc */ - sp[15] = 0x01000000; /* psr */ + sp[8] = tasks_init[id].r0; /* r0 */ + sp[13] = (uint32_t)task_exit_trap; /* lr */ + sp[14] = tasks_init[id].pc; /* pc */ + sp[15] = 0x01000000; /* psr */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = tasks[id].stack; sp < (uint32_t *)tasks[id].sp; sp++) @@ -619,8 +612,7 @@ DECLARE_DEFERRED(deferred_task_reset); * and if it matches if_value, updates the state to new_value, and returns * TRUE. */ -static int update_reset_state(uint32_t *state, - uint32_t if_value, +static int update_reset_state(uint32_t *state, uint32_t if_value, uint32_t to_value) { int update; @@ -676,8 +668,7 @@ void task_enable_resets(void) uint32_t *state = &task_reset_state[id]; if (*state == TASK_RESET_UNSUPPORTED) { - cprints(CC_TASK, - "%s called from non-resettable task, id: %d", + cprints(CC_TASK, "%s called from non-resettable task, id: %d", __func__, id); return; } @@ -720,8 +711,7 @@ void task_disable_resets(void) uint32_t *state = &task_reset_state[id]; if (*state == TASK_RESET_UNSUPPORTED) { - cprints(CC_TASK, - "%s called from non-resettable task, id %d", + cprints(CC_TASK, "%s called from non-resettable task, id %d", __func__, id); return; } @@ -776,8 +766,8 @@ int task_reset_cleanup(void) if (cleanup_req) { while (!try_release_reset_lock(state)) { /* Find the first waiter to notify. */ - task_id_t notify_id = __fls( - *state & TASK_RESET_WAITERS_MASK); + task_id_t notify_id = + __fls(*state & TASK_RESET_WAITERS_MASK); /* * Remove the task from waiters first, so that * when it wakes after being notified, it is in @@ -913,8 +903,9 @@ void mutex_lock(struct mutex *mtx) " teq %0, #0\n" " it eq\n" " strexeq %0, %2, [%1]\n" - : "=&r" (value) - : "r" (&mtx->lock), "r" (2) : "cc"); + : "=&r"(value) + : "r"(&mtx->lock), "r"(2) + : "cc"); /* * "value" is equals to 1 if the store conditional failed, * 2 if somebody else owns the mutex, 0 else. @@ -1006,8 +997,7 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); #ifdef CONFIG_CMD_TASKREADY @@ -1023,8 +1013,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); #endif @@ -1094,7 +1083,6 @@ static int command_task_reset(int argc, char **argv) return EC_ERROR_PARAM_COUNT; } -DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, - "task_id", +DECLARE_CONSOLE_COMMAND(taskreset, command_task_reset, "task_id", "Reset a task"); -#endif /* CONFIG_CMD_TASK_RESET */ +#endif /* CONFIG_CMD_TASK_RESET */ -- cgit v1.2.1 From f905e631f398b7364e3c8f65797850df5321d3d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:21 -0600 Subject: board/mithrax/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0a247ebe9edd4fe25615aad8d92ab2fe1b9dec5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728455 Reviewed-by: Jeremy Bettis --- board/mithrax/board.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/board/mithrax/board.c b/board/mithrax/board.c index 3db87618f8..57d9039053 100644 --- a/board/mithrax/board.c +++ b/board/mithrax/board.c @@ -29,8 +29,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static void rgb_backlight_config(void); @@ -97,8 +97,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -130,7 +130,6 @@ static void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - /** * Deferred function to handle pen detect change */ @@ -153,8 +152,7 @@ DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT); void pen_detect_interrupt(enum gpio_signal s) { /* Trigger deferred notification of pen detect change */ - hook_call_deferred(&pendetect_deferred_data, - 500 * MSEC); + hook_call_deferred(&pendetect_deferred_data, 500 * MSEC); } void pen_config(void) -- cgit v1.2.1 From 84bc86f15504b3949712702c025428901a00bd3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:14 -0600 Subject: include/ioexpander.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie935903fff9cfa343eed449b9f78b222d90a1219 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730293 Reviewed-by: Jeremy Bettis --- include/ioexpander.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/ioexpander.h b/include/ioexpander.h index 21d7034303..323ba65330 100644 --- a/include/ioexpander.h +++ b/include/ioexpander.h @@ -11,7 +11,7 @@ #define ioex_signal gpio_signal #include "gpio.h" #else -enum ioex_signal; /* from gpio_signal.h */ +enum ioex_signal; /* from gpio_signal.h */ #endif /* IO expander signal definition structure */ @@ -34,11 +34,11 @@ struct ioex_info { /* Signal information from board.c. Must match order from enum ioex_signal. */ extern const struct ioex_info ioex_list[]; -extern void (* const ioex_irq_handlers[])(enum ioex_signal signal); +extern void (*const ioex_irq_handlers[])(enum ioex_signal signal); extern const int ioex_ih_count; /* Get ioex_info structure for specified signal */ -#define IOEX_GET_INFO(signal) (ioex_list + (signal) - IOEX_SIGNAL_START) +#define IOEX_GET_INFO(signal) (ioex_list + (signal)-IOEX_SIGNAL_START) struct ioexpander_drv { /* Initialize IO expander chip/driver */ @@ -60,9 +60,9 @@ struct ioexpander_drv { }; /* IO expander default init disabled. No I2C communication will be attempted. */ -#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0) +#define IOEX_FLAGS_DEFAULT_INIT_DISABLED BIT(0) /* IO Expander has been initialized */ -#define IOEX_FLAGS_INITIALIZED BIT(1) +#define IOEX_FLAGS_INITIALIZED BIT(1) /* * BITS 24 to 31 are used by io-expander drivers that need to control multiple -- cgit v1.2.1 From 73971d20353285b04a3dabb6ddb5f8d2f03fd563 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:47 -0600 Subject: test/usb_typec_ctvpd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib448c72f52f9a0007b3ccfc6a444f97373a8e112 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730314 Reviewed-by: Jeremy Bettis --- test/usb_typec_ctvpd.c | 160 ++++++++++++++++++++++--------------------------- 1 file changed, 73 insertions(+), 87 deletions(-) diff --git a/test/usb_typec_ctvpd.c b/test/usb_typec_ctvpd.c index 583c529fca..2c7404ec9b 100644 --- a/test/usb_typec_ctvpd.c +++ b/test/usb_typec_ctvpd.c @@ -18,12 +18,12 @@ #include "usb_sm_checks.h" #include "vpd_api.h" -#define PORT0 0 +#define PORT0 0 -enum cc_type {CC1, CC2}; -enum vbus_type {VBUS_0 = 0, VBUS_5 = 5000}; -enum vconn_type {VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000}; -enum snk_con_voltage_type {SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0}; +enum cc_type { CC1, CC2 }; +enum vbus_type { VBUS_0 = 0, VBUS_5 = 5000 }; +enum vconn_type { VCONN_0 = 0, VCONN_3 = 3000, VCONN_5 = 5000 }; +enum snk_con_voltage_type { SRC_CON_DEF, SRC_CON_1_5, SRC_CON_3_0 }; /* * These enum definitions are declared in usb_tc_*_sm and are private to that @@ -92,15 +92,15 @@ static int ct_connect_sink(enum cc_type cc, enum snk_con_voltage_type v) switch (v) { case SRC_CON_DEF: ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV) : - mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV); + mock_set_cc1_rp3a0_rd_l(PD_SRC_DEF_RD_THRESH_MV); break; case SRC_CON_1_5: ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV) : - mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV); + mock_set_cc1_rp3a0_rd_l(PD_SRC_1_5_RD_THRESH_MV); break; case SRC_CON_3_0: ret = (cc) ? mock_set_cc2_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV) : - mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV); + mock_set_cc1_rp3a0_rd_l(PD_SRC_3_0_RD_THRESH_MV); break; default: ret = 0; @@ -124,7 +124,7 @@ static int ct_connect_source(enum cc_type cc, enum vbus_type vbus) { mock_set_ct_vbus(vbus); return (cc) ? mock_set_cc2_rpusb_odh(PD_SNK_VA_MV) : - mock_set_cc1_rpusb_odh(PD_SNK_VA_MV); + mock_set_cc1_rpusb_odh(PD_SNK_VA_MV); } static int ct_disconnect_source(void) @@ -297,14 +297,15 @@ void inc_rx_id(int port) static int verify_goodcrc(int port, int role, int id) { return pd_test_tx_msg_verify_sop_prime(port) && - pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC, - role, role, id, 0, 0, 0)) && - pd_test_tx_msg_verify_crc(port) && - pd_test_tx_msg_verify_eop(port); + pd_test_tx_msg_verify_short(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, + role, id, 0, 0, 0)) && + pd_test_tx_msg_verify_crc(port) && + pd_test_tx_msg_verify_eop(port); } static void simulate_rx_msg(int port, uint16_t header, int cnt, - const uint32_t *data) + const uint32_t *data) { int i; @@ -330,20 +331,20 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt, static void simulate_goodcrc(int port, int role, int id) { - simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, - pd_port[port].rev, 0), 0, NULL); + simulate_rx_msg(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, + pd_port[port].rev, 0), + 0, NULL); } static void simulate_discovery_identity(int port) { - uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE, - 1, pd_port[port].msg_rx_id, - 1, pd_port[port].rev, 0); - uint32_t msg = VDO(USB_SID_PD, - 1, /* Structured VDM */ - VDO_SVDM_VERS(1) | - VDO_CMDT(CMDT_INIT) | - CMD_DISCOVER_IDENT); + uint16_t header = PD_HEADER(PD_DATA_VENDOR_DEF, PD_ROLE_SOURCE, 1, + pd_port[port].msg_rx_id, 1, + pd_port[port].rev, 0); + uint32_t msg = VDO(USB_SID_PD, 1, /* Structured VDM */ + VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_INIT) | + CMD_DISCOVER_IDENT); simulate_rx_msg(port, header, 1, (const uint32_t *)&msg); } @@ -538,35 +539,27 @@ static int test_vpd_host_src_detection_vconn(void) static int test_vpd_host_src_detection_message_reception(void) { int port = PORT0; - uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE, - 1, /* Structured VDM */ - VDO_SVDM_VERS(1) | - VDO_CMDT(CMDT_RSP_ACK) | - CMD_DISCOVER_IDENT); - uint32_t expected_vdo_id_header = VDO_IDH( - 0, /* Not a USB Host */ + uint32_t expected_vdm_header = VDO( + USB_VID_GOOGLE, 1, /* Structured VDM */ + VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT); + uint32_t expected_vdo_id_header = + VDO_IDH(0, /* Not a USB Host */ 1, /* Capable of being enumerated as USB Device */ - IDH_PTYPE_VPD, - 0, /* Modal Operation Not Supported */ + IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */ USB_VID_GOOGLE); uint32_t expected_vdo_cert = 0; - uint32_t expected_vdo_product = VDO_PRODUCT( - CONFIG_USB_PID, - USB_BCD_DEVICE); + uint32_t expected_vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE); uint32_t expected_vdo_vpd = VDO_VPD( - VPD_HW_VERSION, - VPD_FW_VERSION, - VPD_MAX_VBUS_20V, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP( - VPD_VBUS_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP( - VPD_GND_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED - : VPD_CTS_NOT_SUPPORTED); + VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? + VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED : + VPD_CTS_NOT_SUPPORTED); mock_set_vconn(VCONN_0); host_disconnect_source(); @@ -608,8 +601,8 @@ static int test_vpd_host_src_detection_message_reception(void) simulate_discovery_identity(port); task_wait_event(30 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(30 * MSEC); @@ -617,9 +610,10 @@ static int test_vpd_host_src_detection_message_reception(void) /* Test Discover Identity Ack */ TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0, - pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0, + pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header)); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header)); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert)); @@ -648,7 +642,6 @@ static int test_vpd_host_src_detection_message_reception(void) TEST_EQ(get_state_tc(port), TC_UNATTACHED_SNK, "%d"); - return EC_SUCCESS; } @@ -992,35 +985,27 @@ static int test_ctvpd_behavior_case3(void) static int test_ctvpd_behavior_case4(void) { int port = PORT0; - uint32_t expected_vdm_header = VDO(USB_VID_GOOGLE, - 1, /* Structured VDM */ - VDO_SVDM_VERS(1) | - VDO_CMDT(CMDT_RSP_ACK) | - CMD_DISCOVER_IDENT); - uint32_t expected_vdo_id_header = VDO_IDH( - 0, /* Not a USB Host */ + uint32_t expected_vdm_header = VDO( + USB_VID_GOOGLE, 1, /* Structured VDM */ + VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT); + uint32_t expected_vdo_id_header = + VDO_IDH(0, /* Not a USB Host */ 1, /* Capable of being enumerated as USB Device */ - IDH_PTYPE_VPD, - 0, /* Modal Operation Not Supported */ + IDH_PTYPE_VPD, 0, /* Modal Operation Not Supported */ USB_VID_GOOGLE); uint32_t expected_vdo_cert = 0; - uint32_t expected_vdo_product = VDO_PRODUCT( - CONFIG_USB_PID, - USB_BCD_DEVICE); + uint32_t expected_vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE); uint32_t expected_vdo_vpd = VDO_VPD( - VPD_HW_VERSION, - VPD_FW_VERSION, - VPD_MAX_VBUS_20V, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP( - VPD_VBUS_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP( - VPD_GND_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED - : VPD_CTS_NOT_SUPPORTED); + VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? + VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP(VPD_GND_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED : + VPD_CTS_NOT_SUPPORTED); init_port(port); mock_set_vconn(VCONN_0); @@ -1107,8 +1092,8 @@ static int test_ctvpd_behavior_case4(void) simulate_discovery_identity(port); task_wait_event(40 * MSEC); - TEST_ASSERT(verify_goodcrc(port, - PD_ROLE_SINK, pd_port[port].msg_rx_id)); + TEST_ASSERT( + verify_goodcrc(port, PD_ROLE_SINK, pd_port[port].msg_rx_id)); task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); @@ -1116,9 +1101,10 @@ static int test_ctvpd_behavior_case4(void) /* Test Discover Identity Ack */ TEST_ASSERT(pd_test_tx_msg_verify_sop_prime(port)); - TEST_ASSERT(pd_test_tx_msg_verify_short(port, - PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0, - pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0))); + TEST_ASSERT(pd_test_tx_msg_verify_short( + port, + PD_HEADER(PD_DATA_VENDOR_DEF, PD_PLUG_FROM_CABLE, 0, + pd_port[port].msg_tx_id, 5, pd_port[port].rev, 0))); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdm_header)); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_id_header)); TEST_ASSERT(pd_test_tx_msg_verify_word(port, expected_vdo_cert)); @@ -1268,8 +1254,8 @@ static int test_ctvpd_behavior_case5(void) * e. CTVPD connects VBUS from the Charge-Through side to the Host * side */ - wait_for_state_change(port, PD_T_TRY_CC_DEBOUNCE + - PD_T_DRP_TRY + 40 * MSEC); + wait_for_state_change(port, + PD_T_TRY_CC_DEBOUNCE + PD_T_DRP_TRY + 40 * MSEC); TEST_ASSERT(get_state_tc(port) == TC_TRY_WAIT_SRC); TEST_ASSERT(check_host_rpusb()); -- cgit v1.2.1 From b102c65882ab0c028437aef87c0b2d408920aa07 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:51 -0600 Subject: zephyr/shim/chip/npcx/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2890dbc19d95875e8e345134ba673e961b7ccfba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728335 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/system.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/chip/npcx/system.c b/zephyr/shim/chip/npcx/system.c index ae28749ec0..f6751ae46a 100644 --- a/zephyr/shim/chip/npcx/system.c +++ b/zephyr/shim/chip/npcx/system.c @@ -54,9 +54,9 @@ void system_mpu_config(void) CPU_MPU_CTRL = 0x7; /* Create a new MPU Region to allow execution from low-power ram */ - CPU_MPU_RNR = REGION_CHIP_RESERVED; + CPU_MPU_RNR = REGION_CHIP_RESERVED; CPU_MPU_RASR = CPU_MPU_RASR & 0xFFFFFFFE; /* Disable region */ - CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ + CPU_MPU_RBAR = CONFIG_LPRAM_BASE; /* Set region base address */ /* * Set region size & attribute and enable region * [31:29] - Reserved. -- cgit v1.2.1 From 137105e5800e9589776ef70307f3203b4298ac7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:35 -0600 Subject: chip/mt_scp/rv32i_common/cache.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I66e4fad61491a6ce7078230a6c7c46a893164358 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729345 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/cache.c | 52 ++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/chip/mt_scp/rv32i_common/cache.c b/chip/mt_scp/rv32i_common/cache.c index 62147590fe..f2f20dbd36 100644 --- a/chip/mt_scp/rv32i_common/cache.c +++ b/chip/mt_scp/rv32i_common/cache.c @@ -33,8 +33,9 @@ void cache_init(void) #pragma GCC unroll 16 for (i = 0; i < NR_MPU_ENTRIES; ++i) { if (mpu_entries[i].end_addr - mpu_entries[i].start_addr) { - write_csr(CSR_MPU_L(i), mpu_entries[i].start_addr | - mpu_entries[i].attribute); + write_csr(CSR_MPU_L(i), + mpu_entries[i].start_addr | + mpu_entries[i].attribute); write_csr(CSR_MPU_H(i), mpu_entries[i].end_addr); mpu_en |= BIT(i); } @@ -47,7 +48,7 @@ void cache_init(void) set_csr(CSR_MCTREN, CSR_MCTREN_MPU); /* fence */ - asm volatile ("fence.i" ::: "memory"); + asm volatile("fence.i" ::: "memory"); } #ifdef DEBUG @@ -56,15 +57,11 @@ void cache_init(void) * D for D-cache * C for control transfer instructions (branch, jump, ret, interrupt, ...) */ -static enum { - PMU_SELECT_I = 0, - PMU_SELECT_D, - PMU_SELECT_C -} pmu_select; +static enum { PMU_SELECT_I = 0, PMU_SELECT_D, PMU_SELECT_C } pmu_select; int command_enable_pmu(int argc, char **argv) { - static const char * const selectors[] = { + static const char *const selectors[] = { [PMU_SELECT_I] = "I", [PMU_SELECT_D] = "D", [PMU_SELECT_C] = "C", @@ -87,9 +84,8 @@ int command_enable_pmu(int argc, char **argv) /* disable all PMU */ clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); /* reset cycle count */ write_csr(CSR_PMU_MCYCLE, 0); @@ -138,25 +134,23 @@ int command_enable_pmu(int argc, char **argv) /* enable all PMU */ set_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, - "[I | D | C]", "Enable PMU"); +DECLARE_SAFE_CONSOLE_COMMAND(enable_pmu, command_enable_pmu, "[I | D | C]", + "Enable PMU"); int command_disable_pmu(int argc, char **argv) { clear_csr(CSR_PMU_MPMUCTR, - CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | - CSR_PMU_MPMUCTR_H3 | CSR_PMU_MPMUCTR_H4 | - CSR_PMU_MPMUCTR_H5); + CSR_PMU_MPMUCTR_C | CSR_PMU_MPMUCTR_I | CSR_PMU_MPMUCTR_H3 | + CSR_PMU_MPMUCTR_H4 | CSR_PMU_MPMUCTR_H5); return EC_SUCCESS; } -DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, - NULL, "Disable PMU"); +DECLARE_SAFE_CONSOLE_COMMAND(disable_pmu, command_disable_pmu, NULL, + "Disable PMU"); int command_show_pmu(int argc, char **argv) { @@ -164,19 +158,19 @@ int command_show_pmu(int argc, char **argv) uint32_t p; val3 = ((uint64_t)read_csr(CSR_PMU_MCYCLEH) << 32) | - read_csr(CSR_PMU_MCYCLE); + read_csr(CSR_PMU_MCYCLE); ccprintf("cycles: %lld\n", val3); val3 = ((uint64_t)read_csr(CSR_PMU_MINSTRETH) << 32) | - read_csr(CSR_PMU_MINSTRET); + read_csr(CSR_PMU_MINSTRET); ccprintf("retired instructions: %lld\n", val3); val3 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER3H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER3); + read_csr(CSR_PMU_MHPMCOUNTER3); val4 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER4H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER4); + read_csr(CSR_PMU_MHPMCOUNTER4); val5 = ((uint64_t)read_csr(CSR_PMU_MHPMCOUNTER5H) << 32) | - read_csr(CSR_PMU_MHPMCOUNTER5); + read_csr(CSR_PMU_MHPMCOUNTER5); if (val3) p = val4 * 10000 / val3; @@ -199,8 +193,8 @@ int command_show_pmu(int argc, char **argv) case PMU_SELECT_C: ccprintf("control transfer instruction:\n"); ccprintf(" total: %lld\n", val3); - ccprintf(" miss-predict: %lld (%d.%d%%)\n", - val4, p / 100, p % 100); + ccprintf(" miss-predict: %lld (%d.%d%%)\n", val4, p / 100, + p % 100); ccprintf("interrupts: %lld\n", val5); break; } -- cgit v1.2.1 From 38f80c2225a04c5b22272bff354565c72a4816c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:40 -0600 Subject: zephyr/shim/src/power_host_sleep_api.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cdcf98e2315e9bcb2efbe2bfea300fb7acdc8cf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730927 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/power_host_sleep_api.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/src/power_host_sleep_api.c b/zephyr/shim/src/power_host_sleep_api.c index 1d283e1c3c..87a91a54c5 100644 --- a/zephyr/shim/src/power_host_sleep_api.c +++ b/zephyr/shim/src/power_host_sleep_api.c @@ -7,8 +7,8 @@ #include #include -static enum power_state translate_ap_power_state( - enum power_states_ndsx ap_power_state) +static enum power_state +translate_ap_power_state(enum power_states_ndsx ap_power_state) { switch (ap_power_state) { case SYS_POWER_STATE_S5: @@ -24,8 +24,8 @@ static enum power_state translate_ap_power_state( } } -int ap_power_get_lazy_wake_mask( - enum power_states_ndsx state, host_event_t *mask) +int ap_power_get_lazy_wake_mask(enum power_states_ndsx state, + host_event_t *mask) { enum power_state st; @@ -36,9 +36,8 @@ int ap_power_get_lazy_wake_mask( } #if CONFIG_AP_PWRSEQ_HOST_SLEEP -void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +void power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { ap_power_chipset_handle_host_sleep_event(state, ctx); } -- cgit v1.2.1 From 010968a5b18ce1f48c1bbf1d86bbbf668de06c5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:48 -0600 Subject: zephyr/shim/include/usbc/tcpc_ps8xxx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e6f637e8b36d0b34c89070d29c0104924caac35 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730841 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_ps8xxx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h index d47f6cc9df..379b041e8e 100644 --- a/zephyr/shim/include/usbc/tcpc_ps8xxx.h +++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h @@ -8,7 +8,7 @@ #define PS8XXX_COMPAT parade_ps8xxx -#define TCPC_CONFIG_PS8XXX(id) \ +#define TCPC_CONFIG_PS8XXX(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ -- cgit v1.2.1 From e62cb6bb5608c4e26e72fb7d768c67e060b2e0ca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:08 -0600 Subject: board/dingdong/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa1b696c21db2c77873a3944c2be9db4cbca7cd2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728202 Reviewed-by: Jeremy Bettis --- board/dingdong/board.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/dingdong/board.c b/board/dingdong/board.c index ddaf6bb928..78bcbc82da 100644 --- a/board/dingdong/board.c +++ b/board/dingdong/board.c @@ -96,7 +96,7 @@ void board_config_pre_init(void) /* enable SYSCFG clock */ STM32_RCC_APB2ENR |= BIT(0); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */ } /* Initialize board. */ @@ -115,10 +115,10 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)}, + [ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -const void * const usb_strings[] = { +const void *const usb_strings[] = { [USB_STR_DESC] = usb_string_desc, [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), [USB_STR_PRODUCT] = USB_STRING_DESC("Dingdong"), -- cgit v1.2.1 From 29406b66f26f46562d63c2c4ce2d39e6f5302f57 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:14 -0600 Subject: util/usb_if.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2b4776eb6540c49eb9542203463cff643a6c9d44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730656 Reviewed-by: Jeremy Bettis --- util/usb_if.c | 44 ++++++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/util/usb_if.c b/util/usb_if.c index f8aa6bfd7e..034524e27f 100644 --- a/util/usb_if.c +++ b/util/usb_if.c @@ -12,16 +12,14 @@ /* Return 0 on error, since it's never gonna be EP 0 */ static int find_endpoint(const struct libusb_interface_descriptor *iface, - uint16_t subclass, - uint16_t protocol, + uint16_t subclass, uint16_t protocol, struct usb_endpoint *uep) { const struct libusb_endpoint_descriptor *ep; if (iface->bInterfaceClass == 255 && iface->bInterfaceSubClass == subclass && - iface->bInterfaceProtocol == protocol && - iface->bNumEndpoints) { + iface->bInterfaceProtocol == protocol && iface->bNumEndpoints) { ep = &iface->endpoint[0]; uep->ep_num = ep->bEndpointAddress & 0x7f; uep->chunk_len = ep->wMaxPacketSize; @@ -32,8 +30,7 @@ static int find_endpoint(const struct libusb_interface_descriptor *iface, } /* Return -1 on error */ -static int find_interface(uint16_t subclass, - uint16_t protocol, +static int find_interface(uint16_t subclass, uint16_t protocol, struct usb_endpoint *uep) { int iface_num = -1; @@ -66,8 +63,8 @@ out: return iface_num; } -static libusb_device_handle *check_device(libusb_device *dev, - uint16_t vid, uint16_t pid, const char *serial) +static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid, + uint16_t pid, const char *serial) { struct libusb_device_descriptor desc; libusb_device_handle *handle = NULL; @@ -81,18 +78,17 @@ static libusb_device_handle *check_device(libusb_device *dev, return NULL; if (desc.iSerialNumber && serial) { - sn_size = libusb_get_string_descriptor_ascii(handle, - desc.iSerialNumber, (unsigned char *)sn, - sizeof(sn)); + sn_size = libusb_get_string_descriptor_ascii( + handle, desc.iSerialNumber, (unsigned char *)sn, + sizeof(sn)); } /* * If the VID, PID, and serial number don't match, then it's not the * correct device. Close the handle and return NULL. */ - if ((vid && vid != desc.idVendor) || - (pid && pid != desc.idProduct) || - (serial && ((sn_size != strlen(serial)) || - memcmp(sn, serial, sn_size)))) { + if ((vid && vid != desc.idVendor) || (pid && pid != desc.idProduct) || + (serial && + ((sn_size != strlen(serial)) || memcmp(sn, serial, sn_size)))) { libusb_close(handle); return NULL; } @@ -156,8 +152,8 @@ int usb_findit(const char *serial, uint16_t vid, uint16_t pid, goto terminate_usb_findit; } - printf("found interface %d endpoint %d, chunk_len %d\n", - iface_num, uep->ep_num, uep->chunk_len); + printf("found interface %d endpoint %d, chunk_len %d\n", iface_num, + uep->ep_num, uep->chunk_len); libusb_set_auto_detach_kernel_driver(uep->devh, 1); r = libusb_claim_interface(uep->devh, iface_num); @@ -175,17 +171,15 @@ terminate_usb_findit: return -1; } -int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, - void *inbuf, int inlen, int allow_less, size_t *rxed_count) +int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, void *inbuf, + int inlen, int allow_less, size_t *rxed_count) { - int r, actual; /* Send data out */ if (outbuf && outlen) { actual = 0; - r = libusb_bulk_transfer(uep->devh, uep->ep_num, - outbuf, outlen, + r = libusb_bulk_transfer(uep->devh, uep->ep_num, outbuf, outlen, &actual, 1000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); @@ -200,11 +194,9 @@ int usb_trx(struct usb_endpoint *uep, void *outbuf, int outlen, /* Read reply back */ if (inbuf && inlen) { - actual = 0; - r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, - inbuf, inlen, - &actual, 1000); + r = libusb_bulk_transfer(uep->devh, uep->ep_num | 0x80, inbuf, + inlen, &actual, 1000); if (r < 0) { USB_ERROR("libusb_bulk_transfer", r); return -1; -- cgit v1.2.1 From d513952abecb991bf5bb13790a9afac376348379 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:11 -0600 Subject: zephyr/shim/src/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iccb6283d3951a3daade561c4eba80f517fc2d6e3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727463 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/i2c.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/src/i2c.c b/zephyr/shim/src/i2c.c index 8d55876629..93d7f846bd 100644 --- a/zephyr/shim/src/i2c.c +++ b/zephyr/shim/src/i2c.c @@ -24,8 +24,7 @@ #define INIT_DEV_BINDING(id) \ [I2C_PORT(id)] = DEVICE_DT_GET(DT_PHANDLE(id, i2c_port)), -#define INIT_REMOTE_PORTS(id) \ - [I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1), +#define INIT_REMOTE_PORTS(id) [I2C_PORT(id)] = DT_PROP_OR(id, remote_port, -1), #define I2C_PORT_FLAGS(id) \ COND_CODE_1(DT_PROP(id, dynamic_speed), (I2C_PORT_FLAG_DYNAMIC_SPEED), \ @@ -44,18 +43,15 @@ * Since all the ports will eventually be handled by device tree. This will * be removed at that point. */ -const struct i2c_port_t i2c_ports[] = { - DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_INIT) -}; +const struct i2c_port_t i2c_ports[] = { DT_FOREACH_CHILD( + DT_PATH(named_i2c_ports), I2C_PORT_INIT) }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -static const int i2c_remote_ports[I2C_PORT_COUNT] = { - DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_REMOTE_PORTS) -}; +static const int i2c_remote_ports[I2C_PORT_COUNT] = { DT_FOREACH_CHILD( + DT_PATH(named_i2c_ports), INIT_REMOTE_PORTS) }; static int i2c_physical_ports[I2C_PORT_COUNT]; -static const struct device *i2c_devices[I2C_PORT_COUNT] = { - DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), INIT_DEV_BINDING) -}; +static const struct device *i2c_devices[I2C_PORT_COUNT] = { DT_FOREACH_CHILD( + DT_PATH(named_i2c_ports), INIT_DEV_BINDING) }; static int init_device_bindings(const struct device *device) { -- cgit v1.2.1 From cca54a502fe5027028bd48b2fc2dba3a9007c0d5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:48 -0600 Subject: board/volmar/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8a3eff0293dcd095da8c56f42d52c9bfad0a39d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729075 Reviewed-by: Jeremy Bettis --- board/volmar/board.h | 112 ++++++++++++++++++++++++--------------------------- 1 file changed, 53 insertions(+), 59 deletions(-) diff --git a/board/volmar/board.h b/board/volmar/board.h index e8b355d4b5..dc4f5d2df4 100644 --- a/board/volmar/board.h +++ b/board/volmar/board.h @@ -25,7 +25,7 @@ #define CONFIG_LED_ONOFF_STATES /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -46,17 +46,17 @@ #define CONFIG_USBC_PPC_SYV682X /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -64,60 +64,60 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* Thermal features */ #define CONFIG_THERMISTOR @@ -125,15 +125,15 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT +#undef CONFIG_POWER_BUTTON_INIT_TIMEOUT #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 2 /* Keyboard */ @@ -142,7 +142,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -168,20 +168,14 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_KBLIGHT = 0, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #ifdef CONFIG_KEYBOARD_FACTORY_TEST extern const int keyboard_factory_scan_pins[][2]; -- cgit v1.2.1 From 8cfe18c3afa4d263884309c6d1a9b4ce737a4053 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:04 -0600 Subject: chip/npcx/ps2_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I552507f4f90d944f90e79237b70fe6aacf218314 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727023 Reviewed-by: Jeremy Bettis --- chip/npcx/ps2_chip.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/npcx/ps2_chip.h b/chip/npcx/ps2_chip.h index d88e6791ad..ebdbfca031 100644 --- a/chip/npcx/ps2_chip.h +++ b/chip/npcx/ps2_chip.h @@ -21,4 +21,4 @@ void ps2_enable_channel(int channel, int enable, void (*callback)(uint8_t data)); int ps2_transmit_byte(int channel, uint8_t data); -#endif /* __CROS_EC_PS2_CHIP_H */ +#endif /* __CROS_EC_PS2_CHIP_H */ -- cgit v1.2.1 From a716512690e808e79f42960a5072483c7b56eca1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:23 -0600 Subject: board/agah/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee4a404b2560ce62245c8126c67efa760e24ae22 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727096 Reviewed-by: Jeremy Bettis --- board/agah/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/agah/fw_config.c b/board/agah/fw_config.c index 7a08e187a6..b53950af97 100644 --- a/board/agah/fw_config.c +++ b/board/agah/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union agah_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 9326e7a9bb1dae17484f821e2d40ae3905714d32 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:37 -0600 Subject: board/banshee/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46bdb91691540093da713cea35d890e00e6c3c1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728020 Reviewed-by: Jeremy Bettis --- board/banshee/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/banshee/charger.c b/board/banshee/charger.c index 85e0de90fe..32dd2ddddb 100644 --- a/board/banshee/charger.c +++ b/board/banshee/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 778cf406f8547e7f6a7efad8d019bca59b1feb1f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:33 -0600 Subject: util/comm-servo-spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I539253b9549e6a5f93374a1668b51738af39ade6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730607 Reviewed-by: Jeremy Bettis --- util/comm-servo-spi.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/util/comm-servo-spi.c b/util/comm-servo-spi.c index ef6dc7880b..55bd2eb3fd 100644 --- a/util/comm-servo-spi.c +++ b/util/comm-servo-spi.c @@ -74,8 +74,8 @@ enum mpsse_pins { * propagates data on the falling edge * and reads data on the rising edge of the clock. */ -#define SPI_CMD_TX (MPSSE_DO_WRITE | MPSSE_WRITE_NEG) -#define SPI_CMD_RX (MPSSE_DO_READ) +#define SPI_CMD_TX (MPSSE_DO_WRITE | MPSSE_WRITE_NEG) +#define SPI_CMD_RX (MPSSE_DO_READ) #define SPI_CMD_TXRX (MPSSE_DO_WRITE | MPSSE_DO_READ | MPSSE_WRITE_NEG) static int raw_read(uint8_t *buf, int size) @@ -94,7 +94,7 @@ static int raw_read(uint8_t *buf, int size) static int mpsse_set_pins(uint8_t levels) { - uint8_t buf[MPSSE_CMD_SIZE] = {0}; + uint8_t buf[MPSSE_CMD_SIZE] = { 0 }; buf[0] = SET_BITS_LOW; buf[1] = levels; @@ -103,8 +103,8 @@ static int mpsse_set_pins(uint8_t levels) return ftdi_write_data(&ftdi, buf, sizeof(buf)) != sizeof(buf); } -static int send_request(int cmd, int version, - const uint8_t *outdata, size_t outsize) +static int send_request(int cmd, int version, const uint8_t *outdata, + size_t outsize) { uint8_t *txbuf; struct ec_host_request *request; @@ -133,8 +133,8 @@ static int send_request(int cmd, int version, request->data_len = outsize; /* copy the data to transmit after the command header */ - memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request), - outdata, outsize); + memcpy(txbuf + MPSSE_CMD_SIZE + sizeof(struct ec_host_request), outdata, + outsize); /* Compute the checksum */ for (i = MPSSE_CMD_SIZE; i < total_len; i++) @@ -212,13 +212,12 @@ static int get_response(uint8_t *bodydest, size_t bodylen) /* Check the header */ if (hdr.struct_version != EC_HOST_RESPONSE_VERSION) { fprintf(stderr, "response version %d (should be %d)\n", - hdr.struct_version, - EC_HOST_RESPONSE_VERSION); + hdr.struct_version, EC_HOST_RESPONSE_VERSION); return -EC_RES_ERROR; } if (hdr.data_len > bodylen) { - fprintf(stderr, "response data_len %d is > %zd\n", - hdr.data_len, bodylen); + fprintf(stderr, "response data_len %d is > %zd\n", hdr.data_len, + bodylen); return -EC_RES_ERROR; } @@ -243,9 +242,8 @@ read_error: return -EC_RES_ERROR; } -static int ec_command_servo_spi(int cmd, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_servo_spi(int cmd, int version, const void *outdata, + int outsize, void *indata, int insize) { int ret = -EC_RES_ERROR; @@ -275,7 +273,7 @@ static int mpsse_set_clock(uint32_t freq) { uint32_t system_clock = 0; uint16_t divisor = 0; - uint8_t buf[MPSSE_CMD_SIZE] = {0}; + uint8_t buf[MPSSE_CMD_SIZE] = { 0 }; if (freq > 6000000) { buf[0] = TCK_X5; @@ -307,10 +305,10 @@ static void servo_spi_close(void) int comm_init_servo_spi(const char *device_name) { int status; - uint8_t buf[MPSSE_CMD_SIZE] = {0}; + uint8_t buf[MPSSE_CMD_SIZE] = { 0 }; /* if the user mentioned a device name, use it as serial string */ - const char *serial = strcmp(CROS_EC_DEV_NAME, device_name) ? - device_name : NULL; + const char *serial = + strcmp(CROS_EC_DEV_NAME, device_name) ? device_name : NULL; if (ftdi_init(&ftdi)) return -EC_RES_ERROR; -- cgit v1.2.1 From f9dfe4e59f16025f1c3a2d22a910c9b026e211d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:04 -0600 Subject: baseboard/kukui/emmc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If592118257f725b989fef6fd7710f184315a1369 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727922 Reviewed-by: Jeremy Bettis --- baseboard/kukui/emmc.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/baseboard/kukui/emmc.c b/baseboard/kukui/emmc.c index 68953d8923..db165631f0 100644 --- a/baseboard/kukui/emmc.c +++ b/baseboard/kukui/emmc.c @@ -43,8 +43,8 @@ #include "bootblock_data.h" -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SPI, format, ##args) #if EMMC_SPI_PORT == 1 #define STM32_SPI_EMMC_REGS STM32_SPI1_REGS @@ -68,7 +68,7 @@ static timestamp_t boot_deadline; /* 1024 bytes circular buffer is enough for ~0.6ms @ 13Mhz. */ #define SPI_RX_BUF_BYTES 1024 -#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES/4) +#define SPI_RX_BUF_WORDS (SPI_RX_BUF_BYTES / 4) static uint32_t in_msg[SPI_RX_BUF_WORDS]; /* Macros to advance in the circular buffer. */ @@ -92,7 +92,7 @@ static const struct dma_option dma_tx_option = { static const struct dma_option dma_rx_option = { STM32_DMAC_SPI_EMMC_RX, (void *)&STM32_SPI_EMMC_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | - STM32_DMA_CCR_CIRC + STM32_DMA_CCR_CIRC }; /* Setup DMA to transfer bootblock. */ @@ -123,7 +123,7 @@ static void bootblock_stop(void) */ start = __hw_clock_source_read(); while (STM32_SPI_EMMC_REGS->sr & STM32_SPI_SR_FTLVL && - __hw_clock_source_read() - start < timeout) + __hw_clock_source_read() - start < timeout) ; /* Then flush SPI FIFO, and make sure DAT line stays idle (high). */ @@ -152,8 +152,8 @@ static enum emmc_cmd emmc_parse_command(int index) /* Number of leading ones. */ shift0 = __builtin_clz(~data[0]); - data[0] = (data[0] << shift0) | (data[1] >> (32-shift0)); - data[1] = (data[1] << shift0) | (data[2] >> (32-shift0)); + data[0] = (data[0] << shift0) | (data[1] >> (32 - shift0)); + data[1] = (data[1] << shift0) | (data[2] >> (32 - shift0)); if (data[0] == 0x40000000 && data[1] == 0x0095ffff) { /* 400000000095 GO_IDLE_STATE */ @@ -177,7 +177,6 @@ static enum emmc_cmd emmc_parse_command(int index) return EMMC_ERROR; } - /* * Wake the EMMC task when there is a falling edge on the CMD line, so that we * can capture the command. -- cgit v1.2.1 From 4cf9f223ac7af769370c623ec5c006d385801fe6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:01 -0600 Subject: core/minute-ia/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I983361bfb6f943967b312d5510106576482894bf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729851 Reviewed-by: Jeremy Bettis --- core/minute-ia/include/fpu.h | 123 +++++++++++++++++++------------------------ 1 file changed, 55 insertions(+), 68 deletions(-) diff --git a/core/minute-ia/include/fpu.h b/core/minute-ia/include/fpu.h index 553807352a..8b1915134d 100644 --- a/core/minute-ia/include/fpu.h +++ b/core/minute-ia/include/fpu.h @@ -12,19 +12,15 @@ #ifdef CONFIG_FPU -#define M_PI 3.14159265358979323846 -#define M_PI_2 1.57079632679489661923 +#define M_PI 3.14159265358979323846 +#define M_PI_2 1.57079632679489661923 static inline float sqrtf(float v) { float root; /* root = fsqart (v); */ - asm volatile( - "fsqrt" - : "=t" (root) - : "0" (v) - ); + asm volatile("fsqrt" : "=t"(root) : "0"(v)); return root; } @@ -34,11 +30,7 @@ static inline float fabsf(float v) float root; /* root = fabs (v); */ - asm volatile( - "fabs" - : "=t" (root) - : "0" (v) - ); + asm volatile("fabs" : "=t"(root) : "0"(v)); return root; } @@ -51,12 +43,11 @@ static inline float logf(float v) { float res; - asm volatile( - "fldln2\n" - "fxch\n" - "fyl2x\n" - : "=t" (res) - : "0" (v)); + asm volatile("fldln2\n" + "fxch\n" + "fyl2x\n" + : "=t"(res) + : "0"(v)); return res; } @@ -70,20 +61,19 @@ static inline float expf(float v) { float res; - asm volatile( - "fldl2e\n" - "fmulp\n" - "fld %%st(0)\n" - "frndint\n" - "fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */ - "fxch %%st(1)\n" - "f2xm1\n" - "fld1\n" - "faddp\n" - "fscale\n" - "fstp %%st(1)\n" - : "=t" (res) - : "0" (v)); + asm volatile("fldl2e\n" + "fmulp\n" + "fld %%st(0)\n" + "frndint\n" + "fsubr %%st(0),%%st(1)\n" /* bug-binutils/19054 */ + "fxch %%st(1)\n" + "f2xm1\n" + "fld1\n" + "faddp\n" + "fscale\n" + "fstp %%st(1)\n" + : "=t"(res) + : "0"(v)); return res; } @@ -97,24 +87,23 @@ static inline float powf(float x, float y) { float res; - asm volatile( - "fyl2x\n" - "fld %%st(0)\n" - "frndint\n" - "fsub %%st,%%st(1)\n" - "fxch\n" - "fchs\n" - "f2xm1\n" - "fld1\n" - "faddp\n" - "fxch\n" - "fld1\n" - "fscale\n" - "fstp %%st(1)\n" - "fmulp\n" - : "=t" (res) - : "0" (x), "u" (y) - : "st(1)"); + asm volatile("fyl2x\n" + "fld %%st(0)\n" + "frndint\n" + "fsub %%st,%%st(1)\n" + "fxch\n" + "fchs\n" + "f2xm1\n" + "fld1\n" + "faddp\n" + "fxch\n" + "fld1\n" + "fscale\n" + "fstp %%st(1)\n" + "fmulp\n" + : "=t"(res) + : "0"(x), "u"(y) + : "st(1)"); return res; } @@ -125,16 +114,15 @@ static inline float ceilf(float v) float res; unsigned short control_word, control_word_tmp; - asm volatile("fnstcw %0" : "=m" (control_word)); + asm volatile("fnstcw %0" : "=m"(control_word)); /* Set Rounding Mode to 10B, round up toward +infinity */ control_word_tmp = (control_word | 0x0800) & 0xfbff; - asm volatile( - "fld %3\n" - "fldcw %1\n" - "frndint\n" - "fldcw %2" - : "=t" (res) - : "m" (control_word_tmp), "m"(control_word), "m" (v)); + asm volatile("fld %3\n" + "fldcw %1\n" + "frndint\n" + "fldcw %2" + : "=t"(res) + : "m"(control_word_tmp), "m"(control_word), "m"(v)); return res; } @@ -144,7 +132,7 @@ static inline float atan2f(float y, float x) { float res; - asm volatile("fpatan" : "=t" (res) : "0" (x), "u" (y) : "st(1)"); + asm volatile("fpatan" : "=t"(res) : "0"(x), "u"(y) : "st(1)"); return res; } @@ -154,11 +142,10 @@ static inline float atanf(float v) { float res; - asm volatile( - "fld1\n" - "fpatan\n" - : "=t" (res) - : "0" (v)); + asm volatile("fld1\n" + "fpatan\n" + : "=t"(res) + : "0"(v)); return res; } @@ -168,7 +155,7 @@ static inline float sinf(float v) { float res; - asm volatile("fsin" : "=t" (res) : "0" (v)); + asm volatile("fsin" : "=t"(res) : "0"(v)); return res; } @@ -178,7 +165,7 @@ static inline float cosf(float v) { float res; - asm volatile("fcos" : "=t" (res) : "0" (v)); + asm volatile("fcos" : "=t"(res) : "0"(v)); return res; } @@ -189,5 +176,5 @@ static inline float acosf(float v) return atan2f(sqrtf(1.0 - v * v), v); } -#endif /* CONFIG_FPU */ -#endif /* __CROS_EC_FPU_H */ +#endif /* CONFIG_FPU */ +#endif /* __CROS_EC_FPU_H */ -- cgit v1.2.1 From 6f5c6adf7f779e090b3dcf61f299bbb0a0510f0c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:31 -0600 Subject: board/damu/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8159a08b39f88af5ff8ad1c98a7a6a3642fde5f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728195 Reviewed-by: Jeremy Bettis --- board/damu/board.c | 83 +++++++++++++++++++++++------------------------------- 1 file changed, 35 insertions(+), 48 deletions(-) diff --git a/board/damu/board.c b/board/damu/board.c index 8a97e53afb..0e44099f56 100644 --- a/board/damu/board.c +++ b/board/damu/board.c @@ -46,8 +46,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -59,40 +59,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -100,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -157,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -239,12 +232,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -301,8 +294,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -316,8 +308,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -356,17 +347,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ /* Lid accel private data */ -- cgit v1.2.1 From cea721382e7a6d821abb19e77904272f320a4392 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:47 -0600 Subject: board/servo_v4p1/chg_control.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8c643bc99281c70d89588ab1a294469acfa7399d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728924 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/chg_control.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/servo_v4p1/chg_control.h b/board/servo_v4p1/chg_control.h index 8b81708ccc..660dd0a204 100644 --- a/board/servo_v4p1/chg_control.h +++ b/board/servo_v4p1/chg_control.h @@ -8,11 +8,7 @@ #include -enum chg_cc_t { - CHG_OPEN, - CHG_CC1, - CHG_CC2 -}; +enum chg_cc_t { CHG_OPEN, CHG_CC1, CHG_CC2 }; enum chg_power_select_t { CHG_POWER_OFF, -- cgit v1.2.1 From d01f19d8883954d2b8e9b051c62b6ed992029a17 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:32 -0600 Subject: common/ap_hang_detect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd1590308bfa9d3c9022b0b6b9ec920b6d728f4b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729585 Reviewed-by: Jeremy Bettis --- common/ap_hang_detect.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/common/ap_hang_detect.c b/common/ap_hang_detect.c index 0c9e7a186d..ed80ca7632 100644 --- a/common/ap_hang_detect.c +++ b/common/ap_hang_detect.c @@ -18,12 +18,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static struct ec_params_hang_detect hdparams; -static int active; /* Is hang detect timer active / counting? */ -static int timeout_will_reboot; /* Will the deferred call reboot the AP? */ +static int active; /* Is hang detect timer active / counting? */ +static int timeout_will_reboot; /* Will the deferred call reboot the AP? */ /** * Handle the hang detect timer expiring. @@ -56,7 +56,8 @@ static void hang_detect_deferred(void) timeout_will_reboot = 1; hook_call_deferred(&hang_detect_deferred_data, (hdparams.warm_reboot_timeout_msec - - hdparams.host_event_timeout_msec) * MSEC); + hdparams.host_event_timeout_msec) * + MSEC); } else { /* Not rebooting, so go back to idle */ active = 0; @@ -196,13 +197,12 @@ hang_detect_host_command(struct host_cmd_handler_args *args) */ if (hdparams.warm_reboot_timeout_msec && hdparams.warm_reboot_timeout_msec <= - hdparams.host_event_timeout_msec) + hdparams.host_event_timeout_msec) hdparams.host_event_timeout_msec = 0; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT, - hang_detect_host_command, +DECLARE_HOST_COMMAND(EC_CMD_HANG_DETECT, hang_detect_host_command, EC_VER_MASK(0)); /*****************************************************************************/ @@ -233,6 +233,5 @@ static int command_hang_detect(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect, - NULL, +DECLARE_CONSOLE_COMMAND(hangdet, command_hang_detect, NULL, "Print hang detect state"); -- cgit v1.2.1 From f03931c3784f83306d2b56a223891d2c2a581dbe Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:23 -0600 Subject: board/twinkie/injector.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia51dc11cdc666de63919c23519d69250669a0f81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729040 Reviewed-by: Jeremy Bettis --- board/twinkie/injector.h | 58 ++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/board/twinkie/injector.h b/board/twinkie/injector.h index 4a33f8ecf0..9ff9dbd534 100644 --- a/board/twinkie/injector.h +++ b/board/twinkie/injector.h @@ -21,50 +21,50 @@ /* Macros to extract values from FSM command words */ #define INJ_CMD(w) ((w) >> 28) -#define INJ_ARG(w) ((w) & 0x0FFFFFFF) -#define INJ_ARG0(w) ((w) & 0x0000FFFF) +#define INJ_ARG(w) ((w)&0x0FFFFFFF) +#define INJ_ARG0(w) ((w)&0x0000FFFF) #define INJ_ARG1(w) (((w) >> 16) & 0xFF) #define INJ_ARG2(w) (((w) >> 24) & 0xF) #define INJ_ARG12(w) (((w) >> 16) & 0xFFF) enum inj_cmd { - INJ_CMD_END = 0x0, /* stop the FSM */ - INJ_CMD_SEND = 0x1, /* Send message on CCx */ - /* arg0: header arg1/2:payload index/count */ - INJ_CMD_WAVE = 0x2, /* Send arbitrary waveform */ - /* stored at index arg1 of len arg0 */ - INJ_CMD_HRST = 0x3, /* Send Hard Reset on CCx */ - INJ_CMD_WAIT = 0x4, /* Wait for arg12 edges if arg12 != 0 */ - /* and timeout after arg0 ms */ - INJ_CMD_GET = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */ - INJ_CMD_SET = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */ - INJ_CMD_JUMP = 0x8, /* Jump to index (as arg0) */ + INJ_CMD_END = 0x0, /* stop the FSM */ + INJ_CMD_SEND = 0x1, /* Send message on CCx */ + /* arg0: header arg1/2:payload index/count */ + INJ_CMD_WAVE = 0x2, /* Send arbitrary waveform */ + /* stored at index arg1 of len arg0 */ + INJ_CMD_HRST = 0x3, /* Send Hard Reset on CCx */ + INJ_CMD_WAIT = 0x4, /* Wait for arg12 edges if arg12 != 0 */ + /* and timeout after arg0 ms */ + INJ_CMD_GET = 0x5, /* Get parameter arg1 (INJ_GET_x) at index arg0 */ + INJ_CMD_SET = 0x6, /* Set parameter arg1 (INJ_SET_x) with arg0 */ + INJ_CMD_JUMP = 0x8, /* Jump to index (as arg0) */ INJ_CMD_EXPCT = 0xC, /* Expect a packet with command arg2 */ - /* and timeout after arg0 ms */ - INJ_CMD_NOP = 0xF, /* No-Operation */ + /* and timeout after arg0 ms */ + INJ_CMD_NOP = 0xF, /* No-Operation */ }; enum inj_set { - INJ_SET_RESISTOR1 = 0, /* CC1 resistor as arg0 (INJ_RES_x) */ - INJ_SET_RESISTOR2 = 1, /* CC2 resistor as arg0 (INJ_RES_x) */ - INJ_SET_RECORD = 2, /* Recording on/off */ - INJ_SET_TX_SPEED = 3, /* TX frequency is arg0 kHz */ - INJ_SET_RX_THRESH = 4, /* RX voltage threshold is arg0 mV */ - INJ_SET_POLARITY = 5, /* Polarity for other operations (INJ_POL_CC) */ - INJ_SET_TRACE = 6, /* Text packet trace on/raw/off */ + INJ_SET_RESISTOR1 = 0, /* CC1 resistor as arg0 (INJ_RES_x) */ + INJ_SET_RESISTOR2 = 1, /* CC2 resistor as arg0 (INJ_RES_x) */ + INJ_SET_RECORD = 2, /* Recording on/off */ + INJ_SET_TX_SPEED = 3, /* TX frequency is arg0 kHz */ + INJ_SET_RX_THRESH = 4, /* RX voltage threshold is arg0 mV */ + INJ_SET_POLARITY = 5, /* Polarity for other operations (INJ_POL_CC) */ + INJ_SET_TRACE = 6, /* Text packet trace on/raw/off */ }; enum inj_get { - INJ_GET_CC = 0, /* CC1/CC2 voltages in mV */ - INJ_GET_VBUS = 1, /* VBUS voltage in mV and current in mA */ - INJ_GET_VCONN = 2, /* VCONN voltage in mV and current in mA */ + INJ_GET_CC = 0, /* CC1/CC2 voltages in mV */ + INJ_GET_VBUS = 1, /* VBUS voltage in mV and current in mA */ + INJ_GET_VCONN = 2, /* VCONN voltage in mV and current in mA */ INJ_GET_POLARITY = 3, /* Current polarity (INJ_POL_CC) */ }; enum inj_res { - INJ_RES_NONE = 0, - INJ_RES_RA = 1, - INJ_RES_RD = 2, + INJ_RES_NONE = 0, + INJ_RES_RA = 1, + INJ_RES_RD = 2, INJ_RES_RPUSB = 3, INJ_RES_RP1A5 = 4, INJ_RES_RP3A0 = 5, @@ -79,7 +79,7 @@ enum inj_pol { enum trace_mode { TRACE_MODE_OFF = 0, TRACE_MODE_RAW = 1, - TRACE_MODE_ON = 2, + TRACE_MODE_ON = 2, }; /* Number of words in the FSM command/data buffer */ -- cgit v1.2.1 From f8391e0c26a23a7352c624996515f62193759702 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:39 -0600 Subject: chip/mt_scp/rv32i_common/config_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32866f9c2e6849a383cbd835fe2493c15cafb431 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729367 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/config_chip.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/mt_scp/rv32i_common/config_chip.h b/chip/mt_scp/rv32i_common/config_chip.h index ac53d51732..ea9dc3f61a 100644 --- a/chip/mt_scp/rv32i_common/config_chip.h +++ b/chip/mt_scp/rv32i_common/config_chip.h @@ -10,10 +10,10 @@ /* Interval between HOOK_TICK notifications */ #define HOOK_TICK_INTERVAL_MS 500 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* RW only, no flash */ -#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_FW_INCLUDE_RO #define CONFIG_RO_MEM_OFF 0 #define CONFIG_RO_SIZE 0 #define CONFIG_RW_MEM_OFF 0 -- cgit v1.2.1 From 34cc6fb4567f3f8526a2da4150be3023a3ca471c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:37 -0600 Subject: zephyr/test/drivers/src/bc12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d6e47efb39062d30f0f24d9a6b7e7d4ca14da37 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730938 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bc12.c | 75 +++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 38 deletions(-) diff --git a/zephyr/test/drivers/src/bc12.c b/zephyr/test/drivers/src/bc12.c index d1a96131c1..ac1c5692d1 100644 --- a/zephyr/test/drivers/src/bc12.c +++ b/zephyr/test/drivers/src/bc12.c @@ -27,8 +27,8 @@ LOG_MODULE_REGISTER(test_drivers_bc12, LOG_LEVEL_DBG); /* Control_1 register bit definitions */ #define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0) #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1 -#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \ - PI3USB9201_REG_CTRL_1_MODE_SHIFT) +#define PI3USB9201_REG_CTRL_1_MODE_MASK \ + (0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT) /* Control_2 register bit definitions */ #define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1) @@ -67,26 +67,26 @@ struct bc12_status { }; static const struct bc12_status bc12_chg_limits[] = { - [CHG_OTHER] = { .supplier = CHARGE_SUPPLIER_OTHER, - .current_limit = 500 }, - [CHG_2_4A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, - .current_limit = USB_CHARGER_MAX_CURR_MA }, - [CHG_2_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, - .current_limit = USB_CHARGER_MAX_CURR_MA }, - [CHG_1_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, - .current_limit = 1000 }, + [CHG_OTHER] = { .supplier = CHARGE_SUPPLIER_OTHER, + .current_limit = 500 }, + [CHG_2_4A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, + .current_limit = USB_CHARGER_MAX_CURR_MA }, + [CHG_2_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, + .current_limit = USB_CHARGER_MAX_CURR_MA }, + [CHG_1_0A] = { .supplier = CHARGE_SUPPLIER_PROPRIETARY, + .current_limit = 1000 }, [CHG_RESERVED] = { .supplier = CHARGE_SUPPLIER_NONE, .current_limit = 0 }, - [CHG_CDP] = { .supplier = CHARGE_SUPPLIER_BC12_CDP, - .current_limit = USB_CHARGER_MAX_CURR_MA }, - [CHG_SDP] = { .supplier = CHARGE_SUPPLIER_BC12_SDP, - .current_limit = 500 }, + [CHG_CDP] = { .supplier = CHARGE_SUPPLIER_BC12_CDP, + .current_limit = USB_CHARGER_MAX_CURR_MA }, + [CHG_SDP] = { .supplier = CHARGE_SUPPLIER_BC12_SDP, + .current_limit = 500 }, #if defined(CONFIG_CHARGE_RAMP_SW) || defined(CONFIG_CHARGE_RAMP_HW) - [CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP, - .current_limit = USB_CHARGER_MAX_CURR_MA }, + [CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP, + .current_limit = USB_CHARGER_MAX_CURR_MA }, #else - [CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP, - .current_limit = 500 }, + [CHG_DCP] = { .supplier = CHARGE_SUPPLIER_BC12_DCP, + .current_limit = 500 }, #endif }; @@ -140,9 +140,10 @@ static void test_bc12_pi3usb9201_host_mode(void) pi3usb9201_emul_set_reg(emul, PI3USB9201_REG_HOST_STS, 0); } -static void test_bc12_pi3usb9201_client_mode( - enum pi3usb9201_client_sts detect_result, - enum charge_supplier supplier, int current_limit) +static void +test_bc12_pi3usb9201_client_mode(enum pi3usb9201_client_sts detect_result, + enum charge_supplier supplier, + int current_limit) { struct i2c_emul *emul = pi3usb9201_emul_get(PI3USB9201_ORD); uint8_t a, b; @@ -188,14 +189,11 @@ static void test_bc12_pi3usb9201_client_mode( } /* Wait for the charge port to update. */ msleep(500); - zassert_equal(charge_manager_get_active_charge_port(), - port, NULL); - zassert_equal(charge_manager_get_supplier(), - supplier, NULL); - zassert_equal(charge_manager_get_charger_current(), - current_limit, NULL); - zassert_equal(charge_manager_get_charger_voltage(), - voltage, NULL); + zassert_equal(charge_manager_get_active_charge_port(), port, NULL); + zassert_equal(charge_manager_get_supplier(), supplier, NULL); + zassert_equal(charge_manager_get_charger_current(), current_limit, + NULL); + zassert_equal(charge_manager_get_charger_voltage(), voltage, NULL); /* * Pretend that the USB-C Port Manager (TCPMv2) has set the port data @@ -213,10 +211,10 @@ static void test_bc12_pi3usb9201_client_mode( b |= PI3USB9201_REG_CTRL_1_INT_MASK; zassert_equal(a, b, NULL); /* Expect the charge manager to have no active supplier. */ - zassert_equal(charge_manager_get_active_charge_port(), - CHARGE_PORT_NONE, NULL); - zassert_equal(charge_manager_get_supplier(), - CHARGE_SUPPLIER_NONE, NULL); + zassert_equal(charge_manager_get_active_charge_port(), CHARGE_PORT_NONE, + NULL); + zassert_equal(charge_manager_get_supplier(), CHARGE_SUPPLIER_NONE, + NULL); zassert_equal(charge_manager_get_charger_current(), 0, NULL); zassert_equal(charge_manager_get_charger_voltage(), 0, NULL); } @@ -240,8 +238,9 @@ ZTEST_USER(bc12, test_bc12_pi3usb9201) uint8_t a, b; /* Pretend we have battery and AC so charging works normally. */ - zassert_ok(gpio_emul_input_set(batt_pres_dev, - GPIO_BATT_PRES_ODL_PORT, 0), NULL); + zassert_ok(gpio_emul_input_set(batt_pres_dev, GPIO_BATT_PRES_ODL_PORT, + 0), + NULL); zassert_equal(BP_YES, battery_is_present(), NULL); zassert_ok(gpio_emul_input_set(acok_dev, GPIO_ACOK_OD_PORT, 1), NULL); msleep(CONFIG_EXTPOWER_DEBOUNCE_MS + 1); @@ -269,9 +268,9 @@ ZTEST_USER(bc12, test_bc12_pi3usb9201) test_bc12_pi3usb9201_host_mode(); for (int c = CHG_OTHER; c <= CHG_DCP; c++) { - test_bc12_pi3usb9201_client_mode(c, - bc12_chg_limits[c].supplier, - bc12_chg_limits[c].current_limit); + test_bc12_pi3usb9201_client_mode( + c, bc12_chg_limits[c].supplier, + bc12_chg_limits[c].current_limit); } } -- cgit v1.2.1 From f0a36198b44bc80cccaf4e8a0a696e8305c7448c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:27 -0600 Subject: util/comm-i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I43c66a95ccba02a9e012da41a979cf852c861a44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730325 Reviewed-by: Jeremy Bettis --- util/comm-i2c.c | 51 ++++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/util/comm-i2c.c b/util/comm-i2c.c index d76749fbe5..1f2bb24e83 100644 --- a/util/comm-i2c.c +++ b/util/comm-i2c.c @@ -27,7 +27,7 @@ #define I2C_ADAPTER_NODE "/sys/class/i2c-adapter/i2c-%d/%d-%04x/name" #define I2C_ADAPTER_NAME "cros-ec-i2c" -#define I2C_MAX_ADAPTER 32 +#define I2C_MAX_ADAPTER 32 #define I2C_NODE "/dev/i2c-%d" #ifdef DEBUG @@ -62,9 +62,8 @@ static void dump_buffer(const uint8_t *data, int length) * Sends a command to the EC (protocol v3). Returns the command status code * (>= 0), or a negative EC_RES_* value on error. */ -static int ec_command_i2c_3(int command, int version, - const void *outdata, int outsize, - void *indata, int insize) +static int ec_command_i2c_3(int command, int version, const void *outdata, + int outsize, void *indata, int insize) { int ret = -EC_RES_ERROR; int error; @@ -87,8 +86,8 @@ static int ec_command_i2c_3(int command, int version, insize, ec_max_insize); return -EC_RES_ERROR; } - req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request) - + outsize; + req_len = I2C_REQUEST_HEADER_SIZE + sizeof(struct ec_host_request) + + outsize; req_buf = (uint8_t *)(calloc(1, req_len)); if (!req_buf) goto done; @@ -102,8 +101,8 @@ static int ec_command_i2c_3(int command, int version, req->reserved = 0; req->data_len = outsize; - memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE - + sizeof(struct ec_host_request)], + memcpy(&req_buf[I2C_REQUEST_HEADER_SIZE + + sizeof(struct ec_host_request)], outdata, outsize); req->checksum = @@ -115,8 +114,8 @@ static int ec_command_i2c_3(int command, int version, i2c_msg.len = req_len; i2c_msg.buf = req_buf; - resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response) - + insize; + resp_len = I2C_RESPONSE_HEADER_SIZE + sizeof(struct ec_host_response) + + insize; resp_buf = (uint8_t *)(calloc(1, resp_len)); if (!resp_buf) goto done; @@ -135,8 +134,8 @@ static int ec_command_i2c_3(int command, int version, data.nmsgs = 1; error = ioctl(i2c_fd, I2C_RDWR, &data); if (error < 0) { - fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n", - error, errno, strerror(errno)); + fprintf(stderr, "I2C write failed: %d (err: %d, %s)\n", error, + errno, strerror(errno)); goto done; } @@ -146,8 +145,8 @@ static int ec_command_i2c_3(int command, int version, i2c_msg.buf = resp_buf; error = ioctl(i2c_fd, I2C_RDWR, &data); if (error < 0) { - fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n", - error, errno, strerror(errno)); + fprintf(stderr, "I2C read failed: %d (err: %d, %s)\n", error, + errno, strerror(errno)); goto done; } @@ -177,15 +176,16 @@ static int ec_command_i2c_3(int command, int version, goto done; } - if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE], resp_buf[1]) - != 0) { + if ((uint8_t)sum_bytes(&resp_buf[I2C_RESPONSE_HEADER_SIZE], + resp_buf[1]) != 0) { debug("Bad checksum on EC response.\n"); ret = -EC_RES_INVALID_CHECKSUM; goto done; } - memcpy(indata, &resp_buf[I2C_RESPONSE_HEADER_SIZE - + sizeof(struct ec_host_response)], + memcpy(indata, + &resp_buf[I2C_RESPONSE_HEADER_SIZE + + sizeof(struct ec_host_response)], insize); ret = resp->data_len; @@ -208,7 +208,8 @@ int comm_init_i2c(int i2c_bus) i = i2c_bus; if (i >= I2C_MAX_ADAPTER) { - fprintf(stderr, "Invalid I2C bus number %d. (The highest possible bus number is %d.)\n", + fprintf(stderr, + "Invalid I2C bus number %d. (The highest possible bus number is %d.)\n", i, I2C_MAX_ADAPTER); return -1; } @@ -217,8 +218,8 @@ int comm_init_i2c(int i2c_bus) for (i = 0; i < I2C_MAX_ADAPTER; i++) { FILE *f; - if (asprintf(&file_path, I2C_ADAPTER_NODE, - i, i, EC_I2C_ADDR) < 0) + if (asprintf(&file_path, I2C_ADAPTER_NODE, i, i, + EC_I2C_ADDR) < 0) return -1; f = fopen(file_path, "r"); if (f) { @@ -248,10 +249,10 @@ int comm_init_i2c(int i2c_bus) free(file_path); ec_command_proto = ec_command_i2c_3; - ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE - - sizeof(struct ec_host_request); - ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE - - sizeof(struct ec_host_response); + ec_max_outsize = I2C_MAX_HOST_PACKET_SIZE - I2C_REQUEST_HEADER_SIZE - + sizeof(struct ec_host_request); + ec_max_insize = I2C_MAX_HOST_PACKET_SIZE - I2C_RESPONSE_HEADER_SIZE - + sizeof(struct ec_host_response); return 0; } -- cgit v1.2.1 From 17e98427ad232aeadb15d2fdb281cb0fdd0f4354 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:39 -0600 Subject: chip/stm32/config-stm32f76x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I998a27da29e34903496a88071d9f4feb79c6ff65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729475 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f76x.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/chip/stm32/config-stm32f76x.h b/chip/stm32/config-stm32f76x.h index aa7f7ac5c0..627878f888 100644 --- a/chip/stm32/config-stm32f76x.h +++ b/chip/stm32/config-stm32f76x.h @@ -4,7 +4,7 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) +#define CONFIG_FLASH_SIZE_BYTES (2048 * 1024) /* 3 regions type: 32K, 128K and 256K */ #define SIZE_32KB (32 * 1024) @@ -29,35 +29,35 @@ /* DTCM-RAM: 128kB 0x20000000 - 0x2001FFFF*/ /* SRAM1: 368kB 0x20020000 - 0x2007BFFF */ /* SRAM2: 16kB 0x2007C000 - 0x2007FFFF */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00080000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00080000 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (1024 * 1024) -#define CONFIG_RW_MEM_OFF (1024 * 1024) -#define CONFIG_RW_SIZE (1024 * 1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE (1024 * 1024) +#define CONFIG_RW_MEM_OFF (1024 * 1024) +#define CONFIG_RW_SIZE (1024 * 1024) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ - (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE #undef I2C_PORT_COUNT -#define I2C_PORT_COUNT 4 +#define I2C_PORT_COUNT 4 /* Use PSTATE embedded in the RO image, not in its own erase block */ #define CONFIG_FLASH_PSTATE #undef CONFIG_FLASH_PSTATE_BANK /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 109 +#define CONFIG_IRQ_COUNT 109 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 -- cgit v1.2.1 From d7f21a9b8ea1beff82246d1dc28ce20aa1858ac4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:38 -0600 Subject: chip/npcx/i2c-npcx7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e2f9a0cda8c21632cef13099c662d1a1bc20da2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729385 Reviewed-by: Jeremy Bettis --- chip/npcx/i2c-npcx7.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/chip/npcx/i2c-npcx7.c b/chip/npcx/i2c-npcx7.c index 3f27aff49e..0193f124e8 100644 --- a/chip/npcx/i2c-npcx7.c +++ b/chip/npcx/i2c-npcx7.c @@ -37,13 +37,13 @@ void i2c_select_port(int port) /* Select I2C ports for the same controller */ else if (port <= NPCX_I2C_PORT4_1) { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB4SEL, - (port == NPCX_I2C_PORT4_1)); + (port == NPCX_I2C_PORT4_1)); } else if (port <= NPCX_I2C_PORT5_1) { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB5SEL, - (port == NPCX_I2C_PORT5_1)); + (port == NPCX_I2C_PORT5_1)); } else { UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB6SEL, - (port == NPCX_I2C_PORT6_1)); + (port == NPCX_I2C_PORT6_1)); } } @@ -52,7 +52,7 @@ int i2c_is_raw_mode(int port) int group, bit; if (port == NPCX_I2C_PORT4_1 || port == NPCX_I2C_PORT5_1 || - port == NPCX_I2C_PORT6_1) { + port == NPCX_I2C_PORT6_1) { group = 6; bit = 7 - (port - NPCX_I2C_PORT4_1) / 2; } else { -- cgit v1.2.1 From bce4cd1a5dacdb54a86a7db4b79dd1be3a40c2ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:56 -0600 Subject: common/battery_fuel_gauge.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id808f92dfae50f5097f2eeb2bf584009d0aaef48 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729608 Reviewed-by: Jeremy Bettis --- common/battery_fuel_gauge.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/common/battery_fuel_gauge.c b/common/battery_fuel_gauge.c index 900798a9fd..a89a6f22eb 100644 --- a/common/battery_fuel_gauge.c +++ b/common/battery_fuel_gauge.c @@ -12,7 +12,7 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* * Authenticate the battery connected. @@ -26,8 +26,8 @@ static bool authenticate_battery_type(int index, char *manuf_name) { char device_name[32]; - const struct fuel_gauge_info * const fuel_gauge = - &board_battery_info[index].fuel_gauge; + const struct fuel_gauge_info *const fuel_gauge = + &board_battery_info[index].fuel_gauge; int len = 0; /* check for valid index */ @@ -40,17 +40,14 @@ static bool authenticate_battery_type(int index, char *manuf_name) /* device name is specified in table */ if (fuel_gauge->device_name != NULL) { - /* Get the device name */ - if (battery_device_name(device_name, - sizeof(device_name))) + if (battery_device_name(device_name, sizeof(device_name))) return false; len = strlen(fuel_gauge->device_name); /* device name mismatch */ - if (strncasecmp(device_name, fuel_gauge->device_name, - len)) + if (strncasecmp(device_name, fuel_gauge->device_name, len)) return false; } @@ -70,7 +67,7 @@ static int battery_get_fixed_battery_type(void) { if (fixed_battery_type == BATTERY_TYPE_UNINITIALIZED) { CPRINTS("Warning: Battery type is not Initialized! " - "Setting to default battery type.\n"); + "Setting to default battery type.\n"); fixed_battery_type = DEFAULT_BATTERY_TYPE; } @@ -144,7 +141,8 @@ static inline const struct board_batt_params *get_batt_params(void) int type = get_battery_type(); return &board_battery_info[type == BATTERY_TYPE_COUNT ? - board_get_default_battery_type() : type]; + board_get_default_battery_type() : + type]; } const struct battery_info *battery_get_info(void) @@ -202,10 +200,10 @@ int board_cut_off_battery(void) if (board_battery_info[type].fuel_gauge.ship_mode.wb_support) rv = cut_off_battery_block_write( - &board_battery_info[type].fuel_gauge.ship_mode); + &board_battery_info[type].fuel_gauge.ship_mode); else rv = cut_off_battery_sb_write( - &board_battery_info[type].fuel_gauge.ship_mode); + &board_battery_info[type].fuel_gauge.ship_mode); return rv ? EC_RES_ERROR : EC_RES_SUCCESS; } @@ -308,8 +306,7 @@ enum battery_disconnect_state battery_get_disconnect_state(void) if ((reg & board_battery_info[type].fuel_gauge.fet.reg_mask) == board_battery_info[type].fuel_gauge.fet.disconnect_val) { CPRINTS("Batt disconnected: reg 0x%04x mask 0x%04x disc 0x%04x", - reg, - board_battery_info[type].fuel_gauge.fet.reg_mask, + reg, board_battery_info[type].fuel_gauge.fet.reg_mask, board_battery_info[type].fuel_gauge.fet.disconnect_val); return BATTERY_DISCONNECTED; } @@ -326,8 +323,9 @@ int battery_imbalance_mv(void) * If battery type is unknown, we cannot safely access non-standard * registers. */ - return (type == BATTERY_TYPE_COUNT) ? 0 : - board_battery_info[type].fuel_gauge.imbalance_mv(); + return (type == BATTERY_TYPE_COUNT) ? + 0 : + board_battery_info[type].fuel_gauge.imbalance_mv(); } int battery_default_imbalance_mv(void) -- cgit v1.2.1 From 1ab125e8b30327cfce0f73daa2d99a481c6380b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:02 -0600 Subject: zephyr/include/ap_power/ap_power.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia4de825febae1b839b04873d77e64e82609a2a2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730709 Reviewed-by: Jeremy Bettis --- zephyr/include/ap_power/ap_power.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/zephyr/include/ap_power/ap_power.h b/zephyr/include/ap_power/ap_power.h index 182e81ca4d..7959604ae0 100644 --- a/zephyr/include/ap_power/ap_power.h +++ b/zephyr/include/ap_power/ap_power.h @@ -116,9 +116,9 @@ typedef void (*ap_power_ev_callback_handler_t)(struct ap_power_ev_callback *cb, * ap_power_ev_init_callback can be used to initialise this structure. */ struct ap_power_ev_callback { - sys_snode_t node; /* Only usable by AP power event code */ + sys_snode_t node; /* Only usable by AP power event code */ ap_power_ev_callback_handler_t handler; - enum ap_power_events events; /* Events to listen for */ + enum ap_power_events events; /* Events to listen for */ }; /** @endcond */ @@ -129,9 +129,10 @@ struct ap_power_ev_callback { * @param handler The function pointer to call. * @param events The bitmask of events to be called for. */ -static inline void ap_power_ev_init_callback(struct ap_power_ev_callback *cb, - ap_power_ev_callback_handler_t handler, - enum ap_power_events events) +static inline void +ap_power_ev_init_callback(struct ap_power_ev_callback *cb, + ap_power_ev_callback_handler_t handler, + enum ap_power_events events) { __ASSERT(cb, "Callback pointer should not be NULL"); __ASSERT(handler, "Callback handler pointer should not be NULL"); -- cgit v1.2.1 From 571c6ac6e6bf44a756ec525992eb00c7a1d0034a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:30 -0600 Subject: util/uut/lib_crc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6fc98be960fba774cde605606e080316accda24c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730662 Reviewed-by: Jeremy Bettis --- util/uut/lib_crc.c | 61 ++++++++++++++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/util/uut/lib_crc.c b/util/uut/lib_crc.c index 176e91327c..61ce3c9420 100644 --- a/util/uut/lib_crc.c +++ b/util/uut/lib_crc.c @@ -54,38 +54,35 @@ /* CRC16 lookup table for polynom 0xA001 */ static const unsigned short crc16_tab[256] = { - 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, - 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, - 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, - 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, - 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, - 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, - 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, - 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, - 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, - 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, - 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, - 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, - 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, - 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, - 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, - 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, - 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, - 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, - 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, - 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, - 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, - 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, - 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, - 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, - 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, - 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, - 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, - 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, - 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, - 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, - 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, - 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, 0xC601, + 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, 0xCC01, 0x0CC0, + 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, 0x0A00, 0xCAC1, 0xCB81, + 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, 0xD801, 0x18C0, 0x1980, 0xD941, + 0x1B00, 0xDBC1, 0xDA81, 0x1A40, 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, + 0x1DC0, 0x1C80, 0xDC41, 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, + 0x1680, 0xD641, 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, + 0x1040, 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, 0x3C00, + 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, 0xFA01, 0x3AC0, + 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, 0x2800, 0xE8C1, 0xE981, + 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, 0xEE01, 0x2EC0, 0x2F80, 0xEF41, + 0x2D00, 0xEDC1, 0xEC81, 0x2C40, 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, + 0xE7C1, 0xE681, 0x2640, 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, + 0x2080, 0xE041, 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, + 0x6240, 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, 0xAA01, + 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, 0x7800, 0xB8C1, + 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, 0xBE01, 0x7EC0, 0x7F80, + 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, 0xB401, 0x74C0, 0x7580, 0xB541, + 0x7700, 0xB7C1, 0xB681, 0x7640, 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, + 0x71C0, 0x7080, 0xB041, 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, + 0x5280, 0x9241, 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, + 0x5440, 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, 0x8801, + 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, 0x4E00, 0x8EC1, + 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, 0x4400, 0x84C1, 0x8581, + 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, 0x8201, 0x42C0, 0x4380, 0x8341, + 0x4100, 0x81C1, 0x8081, 0x4040 }; /********************************************************************* -- cgit v1.2.1 From 422f892a20276a24935ca2ad11a3fdc6f8384028 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:40 -0600 Subject: board/polyberry/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I09e08ed76c30f3fba2cec1c52a8badc779b4ac14 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728837 Reviewed-by: Jeremy Bettis --- board/polyberry/board.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/board/polyberry/board.c b/board/polyberry/board.c index 5bb811f82c..f394d6b847 100644 --- a/board/polyberry/board.c +++ b/board/polyberry/board.c @@ -24,13 +24,13 @@ * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Polyberry"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Polyberry EC Shell"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Polyberry"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Polyberry EC Shell"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -47,15 +47,15 @@ struct dwc_usb usb_ctl = { .irq = STM32_IRQ_OTG_HS, }; -#define GPIO_SET_HS(bank, number) \ - (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number) * 2))) +#define GPIO_SET_HS(bank, number) \ + (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << ((number)*2))) void board_config_post_gpio_init(void) { /* We use MCO2 clock passthrough to provide a clock to USB HS */ gpio_config_module(MODULE_MCO, 1); /* GPIO PC9 to high speed */ - GPIO_SET_HS(C, 9); + GPIO_SET_HS(C, 9); if (usb_ctl.phy_type == USB_PHY_ULPI) gpio_set_level(GPIO_USB_MUX_SEL, 0); @@ -66,19 +66,19 @@ void board_config_post_gpio_init(void) GPIO_SET_HS(A, 11); GPIO_SET_HS(A, 12); - GPIO_SET_HS(C, 3); - GPIO_SET_HS(C, 2); - GPIO_SET_HS(C, 0); - GPIO_SET_HS(A, 5); + GPIO_SET_HS(C, 3); + GPIO_SET_HS(C, 2); + GPIO_SET_HS(C, 0); + GPIO_SET_HS(A, 5); - GPIO_SET_HS(B, 5); + GPIO_SET_HS(B, 5); GPIO_SET_HS(B, 13); GPIO_SET_HS(B, 12); - GPIO_SET_HS(B, 2); + GPIO_SET_HS(B, 2); GPIO_SET_HS(B, 10); - GPIO_SET_HS(B, 1); - GPIO_SET_HS(B, 0); - GPIO_SET_HS(A, 3); + GPIO_SET_HS(B, 1); + GPIO_SET_HS(B, 0); + GPIO_SET_HS(A, 3); } static void board_init(void) -- cgit v1.2.1 From 4a1479d8c0b5b1fe38e0178f2c189e185c0e91b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:13 -0600 Subject: board/drallion_ish/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a2756815e2aa5da485ea720539af3a1a0311017 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726420 Reviewed-by: Jeremy Bettis --- board/drallion_ish/board.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/board/drallion_ish/board.c b/board/drallion_ish/board.c index fba8a622a9..f42ebb6132 100644 --- a/board/drallion_ish/board.c +++ b/board/drallion_ish/board.c @@ -43,11 +43,9 @@ static struct stprivate_data g_lis2dh_data; static struct lis2mdl_private_data lis2mdl_a_data; /* Matrix to rotate base sensor into standard reference frame */ -const mat33_fp_t base_rot_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_rot_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { -- cgit v1.2.1 From c35b1335dbd849f7a3b25b090d1459d7bbba1e06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:57 -0600 Subject: board/kukui_scp/isp_p1_srv.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5a8b4ea0c2499a7ff3c9330d7776e45f22c07e5f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728540 Reviewed-by: Jeremy Bettis --- board/kukui_scp/isp_p1_srv.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/board/kukui_scp/isp_p1_srv.c b/board/kukui_scp/isp_p1_srv.c index 5c2ae7c2e9..39b2a41a07 100644 --- a/board/kukui_scp/isp_p1_srv.c +++ b/board/kukui_scp/isp_p1_srv.c @@ -20,19 +20,21 @@ static struct consumer const event_isp_consumer; static void event_isp_written(struct consumer const *consumer, size_t count); -static struct queue const event_isp_queue = QUEUE_DIRECT(8, - struct isp_msg, null_producer, event_isp_consumer); +static struct queue const event_isp_queue = + QUEUE_DIRECT(8, struct isp_msg, null_producer, event_isp_consumer); static struct consumer const event_isp_consumer = { .queue = &event_isp_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_isp_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT8183 -void isp_msg_handler(void *data) {} +void isp_msg_handler(void *data) +{ +} #endif static void event_isp_written(struct consumer const *consumer, size_t count) -- cgit v1.2.1 From 1b3169bd9247ec7ef6f92bad4d5f3d4af2eaa927 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:27 -0600 Subject: zephyr/shim/include/i2c/i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6042445a98fda2c8b3bd8a521cbf73f57d50260c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730584 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/i2c/i2c.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/include/i2c/i2c.h b/zephyr/shim/include/i2c/i2c.h index c7e29e79e5..36ad16812f 100644 --- a/zephyr/shim/include/i2c/i2c.h +++ b/zephyr/shim/include/i2c/i2c.h @@ -17,7 +17,7 @@ enum i2c_ports { DT_FOREACH_CHILD(DT_PATH(named_i2c_ports), I2C_PORT_WITH_COMMA) - I2C_PORT_COUNT + I2C_PORT_COUNT }; #define NAMED_I2C(name) I2C_PORT(DT_PATH(named_i2c_ports, name)) #endif /* named_i2c_ports */ @@ -36,8 +36,9 @@ enum i2c_ports { #endif #if defined(CONFIG_I2C_ITE_IT8XXX2) && defined(CONFIG_I2C_ITE_ENHANCE) -#define I2C_DEVICE_COUNT DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_i2c) + \ - DT_NUM_INST_STATUS_OKAY(ite_enhance_i2c) +#define I2C_DEVICE_COUNT \ + DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_i2c) + \ + DT_NUM_INST_STATUS_OKAY(ite_enhance_i2c) #else #define I2C_DEVICE_COUNT DT_NUM_INST_STATUS_OKAY(I2C_COMPAT) #endif -- cgit v1.2.1 From 11c4a92bcbd9b51f25c838d0f95b53f7718a6f31 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:58 -0600 Subject: include/lid_switch.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2b6893f145401c9d6b556273c5c3a45aee1616f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730302 Reviewed-by: Jeremy Bettis --- include/lid_switch.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/lid_switch.h b/include/lid_switch.h index 93d093a21f..d127e3feb1 100644 --- a/include/lid_switch.h +++ b/include/lid_switch.h @@ -14,7 +14,7 @@ /** * Debounce time for lid switch */ -#define LID_DEBOUNCE_US (30 * MSEC) +#define LID_DEBOUNCE_US (30 * MSEC) /** * Return non-zero if lid is open. @@ -37,4 +37,4 @@ void lid_interrupt(enum gpio_signal signal); */ void enable_lid_detect(bool enable); -#endif /* __CROS_EC_LID_SWITCH_H */ +#endif /* __CROS_EC_LID_SWITCH_H */ -- cgit v1.2.1 From ff6956c428b61dbee4c881e562f547b7e39a4943 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Fri, 1 Jul 2022 09:28:14 +0800 Subject: kinox: LED_PWR_L change to open drain According to the LED_PWR_L GPIO change to OD from push-pull. So modify the setting. BUG=b:237482098 BRANCH=none TEST=The LED can light up at S0, breath at suspend, off at shutdown. Signed-off-by: Matt Wang Change-Id: Ibbfe291adc4b2c2df1463e630c206f47534d1e78 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739981 Reviewed-by: Ricky Chang --- board/kinox/pwm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kinox/pwm.c b/board/kinox/pwm.c index 112ee62c8c..90db5670f7 100644 --- a/board/kinox/pwm.c +++ b/board/kinox/pwm.c @@ -13,7 +13,8 @@ const struct pwm_t pwm_channels[] = { [PWM_CH_LED_GREEN] = { .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP | + PWM_CONFIG_OPEN_DRAIN, .freq = 2000 }, [PWM_CH_FAN] = { -- cgit v1.2.1 From 0d2925ca52f02a005055aaf807a6b8eddd1fff1c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:23 -0600 Subject: board/wormdingler/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I731a2fcde590834f85c0d0f381862c4375a47ce8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729135 Reviewed-by: Jeremy Bettis --- board/wormdingler/board.c | 154 +++++++++++++++++----------------------------- 1 file changed, 56 insertions(+), 98 deletions(-) diff --git a/board/wormdingler/board.c b/board/wormdingler/board.c index 4ece983255..63e273b426 100644 --- a/board/wormdingler/board.c +++ b/board/wormdingler/board.c @@ -39,10 +39,10 @@ #include "task.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ +#define KS_DEBOUNCE_US (30 * MSEC) /* Debounce time for kickstand switch */ /* Forward declaration */ static void tcpc_alert_event(enum gpio_signal signal); @@ -119,41 +119,31 @@ static void switchcap_interrupt(enum gpio_signal signal) /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -161,45 +151,25 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, /* Base detection */ - [ADC_BASE_DET] = { - "BASE_DET", - NPCX_ADC_CH5, - ADC_MAX_VOLT, - ADC_READ_MAX + 1, - 0 - }, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH5, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -217,16 +187,12 @@ const struct ln9310_config_t ln9310_config = { /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -297,17 +263,13 @@ enum lid_accelgyro_type { static enum lid_accelgyro_type lid_accelgyro_config; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t lid_standard_ref_icm42607 = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref_icm42607 = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_lid_accel = { .name = "Lid Accel", @@ -501,7 +463,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -513,8 +475,7 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_GYRO_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); /* * Board rev 1+ has the hardware fix. Don't need the following @@ -611,8 +572,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -663,24 +623,22 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From 3e34f90310598019897bed411e78da62bdbd9c0a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:52 -0600 Subject: board/munna/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0d60ce0d5efa64d5a854ae26ecdcdc381662f03b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728709 Reviewed-by: Jeremy Bettis --- board/munna/board.c | 109 ++++++++++++++++++++++------------------------------ 1 file changed, 47 insertions(+), 62 deletions(-) diff --git a/board/munna/board.c b/board/munna/board.c index 8eca3f61f1..488848ce5f 100644 --- a/board/munna/board.c +++ b/board/munna/board.c @@ -44,8 +44,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -57,42 +57,36 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(5), - STM32_RANK(1)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15), - STM32_RANK(2)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(5), + STM32_RANK(1) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(15), + STM32_RANK(2) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 2, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 2, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 3, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 3, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -100,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -157,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -239,12 +232,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -314,8 +307,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -333,8 +325,7 @@ static void board_spi_disable(void) STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; #endif } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -373,17 +364,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ /* Lid accel private data */ @@ -471,7 +458,7 @@ struct motion_sensor_t motion_sensors[] = { const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct it8801_pwm_t it8801_pwm_channels[] = { - [IT8801_PWM_CH_KBLIGHT] = {.index = 4}, + [IT8801_PWM_CH_KBLIGHT] = { .index = 4 }, }; void board_kblight_init(void) @@ -487,11 +474,11 @@ bool board_has_kb_backlight(void) #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* Battery functions */ -#define SB_SMARTCHARGE 0x26 +#define SB_SMARTCHARGE 0x26 /* Quick charge enable bit */ -#define SMART_QUICK_CHARGE 0x02 +#define SMART_QUICK_CHARGE 0x02 /* Quick charge support bit */ -#define MODE_QUICK_CHARGE_SUPPORT 0x01 +#define MODE_QUICK_CHARGE_SUPPORT 0x01 static void sb_quick_charge_mode(int enable) { @@ -562,8 +549,8 @@ int board_get_battery_i2c(void) } #ifdef SECTION_IS_RW -static int it8801_get_target_channel(enum pwm_channel *channel, - int type, int index) +static int it8801_get_target_channel(enum pwm_channel *channel, int type, + int index) { switch (type) { case EC_PWM_TYPE_GENERIC: @@ -586,14 +573,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - duty = (uint32_t) p->duty * 255 / 65535; + duty = (uint32_t)p->duty * 255 / 65535; it8801_pwm_set_raw_duty(channel, duty); it8801_pwm_enable(channel, p->duty > 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); static enum ec_status @@ -607,12 +593,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255; + r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255; args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); #endif -- cgit v1.2.1 From c9af680f2a23109e9c0b5481d46ed3d3e1420977 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:54 -0600 Subject: zephyr/shim/chip/npcx/system_download_from_flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5e07a9758d4d81d144eeec97665b269169c80a98 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730562 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/system_download_from_flash.c | 54 +++++++++++----------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/zephyr/shim/chip/npcx/system_download_from_flash.c b/zephyr/shim/chip/npcx/system_download_from_flash.c index f616dc6603..556140bf21 100644 --- a/zephyr/shim/chip/npcx/system_download_from_flash.c +++ b/zephyr/shim/chip/npcx/system_download_from_flash.c @@ -11,40 +11,40 @@ #include "system_chip.h" /* Modules Map */ -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 /******************************************************************************/ /* GDMA (General DMA) Registers */ -#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) -#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) -#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) -#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) +#define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) +#define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) +#define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) +#define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) /******************************************************************************/ /* GDMA register fields */ -#define NPCX_GDMA_CTL_GDMAEN 0 -#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) -#define NPCX_GDMA_CTL_DADIR 4 -#define NPCX_GDMA_CTL_SADIR 5 -#define NPCX_GDMA_CTL_SAFIX 7 -#define NPCX_GDMA_CTL_SIEN 8 -#define NPCX_GDMA_CTL_BME 9 -#define NPCX_GDMA_CTL_SBMS 11 -#define NPCX_GDMA_CTL_TWS FIELD(12, 2) -#define NPCX_GDMA_CTL_DM 15 -#define NPCX_GDMA_CTL_SOFTREQ 16 -#define NPCX_GDMA_CTL_TC 18 -#define NPCX_GDMA_CTL_GDMAERR 20 -#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 +#define NPCX_GDMA_CTL_GDMAEN 0 +#define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) +#define NPCX_GDMA_CTL_DADIR 4 +#define NPCX_GDMA_CTL_SADIR 5 +#define NPCX_GDMA_CTL_SAFIX 7 +#define NPCX_GDMA_CTL_SIEN 8 +#define NPCX_GDMA_CTL_BME 9 +#define NPCX_GDMA_CTL_SBMS 11 +#define NPCX_GDMA_CTL_TWS FIELD(12, 2) +#define NPCX_GDMA_CTL_DM 15 +#define NPCX_GDMA_CTL_SOFTREQ 16 +#define NPCX_GDMA_CTL_TC 18 +#define NPCX_GDMA_CTL_GDMAERR 20 +#define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 /******************************************************************************/ /* Low Power RAM definitions */ -#define NPCX_LPRAM_CTRL REG32(0x40001044) +#define NPCX_LPRAM_CTRL REG32(0x40001044) /******************************************************************************/ /* Sysjump utilities in low power ram for npcx series. */ -noreturn void __keep __attribute__ ((section(".lowpower_ram2"))) +noreturn void __keep __attribute__((section(".lowpower_ram2"))) __start_gdma(uint32_t exeAddr) { /* Enable GDMA now */ @@ -55,7 +55,7 @@ __start_gdma(uint32_t exeAddr) /* Wait for transfer to complete/fail */ while (!IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_TC) && - !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) + !IS_BIT_SET(NPCX_GDMA_CTL, NPCX_GDMA_CTL_GDMAERR)) ; /* Disable GDMA now */ @@ -81,11 +81,11 @@ __start_gdma(uint32_t exeAddr) } /* Begin address of Suspend RAM for little FW (GDMA utilities). */ -#define LFW_OFFSET 0x160 +#define LFW_OFFSET 0x160 uintptr_t __lpram_lfw_start = CONFIG_LPRAM_BASE + LFW_OFFSET; void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr) + uint32_t size, uint32_t exeAddr) { int i; uint8_t chunkSize = 16; /* 4 data burst mode. ie.16 bytes */ @@ -94,7 +94,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, * it's a thumb branch for cortex-m series CPU. */ void (*__start_gdma_in_lpram)(uint32_t) = - (void(*)(uint32_t))(__lpram_lfw_start | 0x01); + (void (*)(uint32_t))(__lpram_lfw_start | 0x01); /* * Before enabling burst mode for better performance of GDMA, it's @@ -152,7 +152,7 @@ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, /* Copy the __start_gdma_in_lpram instructions to LPRAM */ for (i = 0; i < &__flash_lplfw_end - &__flash_lplfw_start; i++) *((uint32_t *)__lpram_lfw_start + i) = - *(&__flash_lplfw_start + i); + *(&__flash_lplfw_start + i); /* Start GDMA in Suspend RAM */ __start_gdma_in_lpram(exeAddr); -- cgit v1.2.1 From 558d72e0af6e8f9469daed624d3680d17f4a0574 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:09 -0600 Subject: driver/usb_mux/anx3443.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6cfc6d11e1192525e45dca56813944323de69ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730155 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx3443.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/driver/usb_mux/anx3443.c b/driver/usb_mux/anx3443.c index c7158b645c..1a350de54c 100644 --- a/driver/usb_mux/anx3443.c +++ b/driver/usb_mux/anx3443.c @@ -23,22 +23,21 @@ #define ANX3443_I2C_WAKE_TIMEOUT_MS 20 #define ANX3443_I2C_WAKE_RETRY_DELAY_US 500 -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static struct { mux_state_t mux_state; bool awake; } saved_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT]; -static inline int anx3443_read(const struct usb_mux *me, - uint8_t reg, int *val) +static inline int anx3443_read(const struct usb_mux *me, uint8_t reg, int *val) { return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } -static inline int anx3443_write(const struct usb_mux *me, - uint8_t reg, uint8_t val) +static inline int anx3443_write(const struct usb_mux *me, uint8_t reg, + uint8_t val) { return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } -- cgit v1.2.1 From 86e525e5a0ba6ff61dfc461e940d3a7d224cb0ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:03 -0600 Subject: chip/ish/ish_i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ice052bbef4e806443a78db0cc04a16f916f53a92 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729185 Reviewed-by: Jeremy Bettis --- chip/ish/ish_i2c.h | 60 ++++++++++++++++++++++-------------------------------- 1 file changed, 24 insertions(+), 36 deletions(-) diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h index 5b30de775c..1c797399d0 100644 --- a/chip/ish/ish_i2c.h +++ b/chip/ish/ish_i2c.h @@ -9,23 +9,22 @@ #include #include "task.h" -#define I2C_TSC_TIMEOUT 2000000 -#define I2C_CALIB_ADDRESS 0x3 -#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20) -#define NS_IN_SEC 1000 -#define DEFAULT_SDA_HOLD 240 -#define DEFAULT_SDA_HOLD_STD 2400 -#define DEFAULT_SDA_HOLD_FAST 600 -#define DEFAULT_SDA_HOLD_FAST_PLUS 300 -#define DEFAULT_SDA_HOLD_HIGH 140 -#define NS_2_COUNTERS(ns, clk) ((ns * clk)/NS_IN_SEC) -#define COUNTERS_2_NS(counters, clk) (counters * (NANOSECONDS_IN_SEC / \ - (clk * HZ_IN_MEGAHZ))) -#define I2C_TX_FLUSH_TIMEOUT_USEC 200 +#define I2C_TSC_TIMEOUT 2000000 +#define I2C_CALIB_ADDRESS 0x3 +#define I2C_INTERRUPT_TIMEOUT (TICKFREQ / 20) +#define NS_IN_SEC 1000 +#define DEFAULT_SDA_HOLD 240 +#define DEFAULT_SDA_HOLD_STD 2400 +#define DEFAULT_SDA_HOLD_FAST 600 +#define DEFAULT_SDA_HOLD_FAST_PLUS 300 +#define DEFAULT_SDA_HOLD_HIGH 140 +#define NS_2_COUNTERS(ns, clk) ((ns * clk) / NS_IN_SEC) +#define COUNTERS_2_NS(counters, clk) \ + (counters * (NANOSECONDS_IN_SEC / (clk * HZ_IN_MEGAHZ))) +#define I2C_TX_FLUSH_TIMEOUT_USEC 200 #define ISH_I2C_FIFO_SIZE 64 - enum { /* freq mode values */ I2C_FREQ_25 = 0, @@ -38,29 +37,18 @@ enum { }; const unsigned int clk_in[] = { - [I2C_FREQ_25] = 25, - [I2C_FREQ_50] = 50, - [I2C_FREQ_100] = 100, - [I2C_FREQ_120] = 120, - [I2C_FREQ_40] = 40, - [I2C_FREQ_20] = 20, + [I2C_FREQ_25] = 25, [I2C_FREQ_50] = 50, [I2C_FREQ_100] = 100, + [I2C_FREQ_120] = 120, [I2C_FREQ_40] = 40, [I2C_FREQ_20] = 20, [I2C_FREQ_37] = 37, }; const uint8_t spkln[] = { - [I2C_FREQ_25] = 2, - [I2C_FREQ_50] = 3, - [I2C_FREQ_100] = 5, - [I2C_FREQ_120] = 6, - [I2C_FREQ_40] = 2, - [I2C_FREQ_20] = 1, + [I2C_FREQ_25] = 2, [I2C_FREQ_50] = 3, [I2C_FREQ_100] = 5, + [I2C_FREQ_120] = 6, [I2C_FREQ_40] = 2, [I2C_FREQ_20] = 1, [I2C_FREQ_37] = 2, }; -enum { - I2C_READ, - I2C_WRITE -}; +enum { I2C_READ, I2C_WRITE }; enum { /* REGISTERS */ @@ -125,7 +113,7 @@ enum { IC_10BITADDR_MASTER = 0, /* IC_TAR WRITE VALUES */ IC_10BITADDR_MASTER_VAL = - (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET), + (IC_10BITADDR_MASTER << IC_10BITADDR_MASTER_OFFSET), TAR_SPECIAL_VAL = (TAR_SPECIAL << SPECIAL_OFFSET), /* IC_DATA_CMD OFFSETS */ DATA_CMD_DAT_OFFSET = 0, @@ -180,13 +168,13 @@ struct i2c_bus_info { struct i2c_bus_data fast_speed; struct i2c_bus_data fast_plus_speed; struct i2c_bus_data high_speed; -} __attribute__ ((__packed__)); +} __attribute__((__packed__)); enum i2c_speed { - I2C_SPEED_100KHZ, /* 100kHz */ - I2C_SPEED_400KHZ, /* 400kHz */ - I2C_SPEED_1MHZ, /* 1MHz */ - I2C_SPEED_3M4HZ, /* 3.4MHz */ + I2C_SPEED_100KHZ, /* 100kHz */ + I2C_SPEED_400KHZ, /* 400kHz */ + I2C_SPEED_1MHZ, /* 1MHz */ + I2C_SPEED_3M4HZ, /* 3.4MHz */ }; struct i2c_context { -- cgit v1.2.1 From ba3ed745058cd6b7c754c75f6662c00969df7ca4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:45 -0600 Subject: chip/max32660/uart_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I23f4138ad0af936a7b5b4d34300ed63c830fcb13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729223 Reviewed-by: Jeremy Bettis --- chip/max32660/uart_chip.c | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/chip/max32660/uart_chip.c b/chip/max32660/uart_chip.c index 7d323650ae..4be5936e0c 100644 --- a/chip/max32660/uart_chip.c +++ b/chip/max32660/uart_chip.c @@ -35,24 +35,24 @@ static int done_uart_init_yet; #define UART_BAUD 115200 -#define UART_ER_IF \ - (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \ +#define UART_ER_IF \ + (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \ MXC_F_UART_INT_FL_RX_PARITY_ERROR | MXC_F_UART_INT_FL_RX_OVERRUN) -#define UART_ER_IE \ - (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \ +#define UART_ER_IE \ + (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \ MXC_F_UART_INT_EN_RX_PARITY_ERROR | MXC_F_UART_INT_EN_RX_OVERRUN) #define UART_RX_IF (UART_ER_IF | MXC_F_UART_INT_FL_RX_FIFO_THRESH) #define UART_RX_IE (UART_ER_IE | MXC_F_UART_INT_EN_RX_FIFO_THRESH) -#define UART_TX_IF \ - (UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \ +#define UART_TX_IF \ + (UART_ER_IF | MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \ MXC_F_UART_INT_FL_TX_FIFO_THRESH) -#define UART_TX_IE \ - (UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \ +#define UART_TX_IE \ + (UART_ER_IE | MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \ MXC_F_UART_INT_EN_TX_FIFO_THRESH) #define UART_RX_THRESHOLD_LEVEL 1 @@ -242,19 +242,20 @@ void uart_init(void) gpio_config_module(MODULE_UART, 1); /* Drain FIFOs and enable UART and set configuration */ - MXC_UART->ctrl = (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1); + MXC_UART->ctrl = + (MXC_F_UART_CTRL_ENABLE | MXC_S_UART_CTRL_CHAR_SIZE_8 | 1); /* Set the baud rate */ - div = PeripheralClock / (UART_BAUD); // constant part of DIV (i.e. DIV - // * (Baudrate*factor_int)) + div = PeripheralClock / (UART_BAUD); // constant part of DIV (i.e. DIV + // * (Baudrate*factor_int)) do { factor += 1; - baud0 = div >> (7 - factor); // divide by 128,64,32,16 to - // extract integer part - baud1 = ((div << factor) - - (baud0 << 7)); // subtract factor corrected div - - // integer parts + baud0 = div >> (7 - factor); // divide by 128,64,32,16 to + // extract integer part + baud1 = ((div << factor) - (baud0 << 7)); // subtract factor + // corrected div - + // integer parts } while ((baud0 == 0) && (factor < 4)); @@ -262,7 +263,7 @@ void uart_init(void) MXC_UART->baud1 = baud1; MXC_UART->thresh_ctrl = UART_RX_THRESHOLD_LEVEL - << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS; + << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS; /* Clear Interrupt Flags */ flags = MXC_UART->int_fl; -- cgit v1.2.1 From 57d4f26f55b9ba624d8fb4526f18739b43919b92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:57 -0600 Subject: chip/stm32/config-stm32l15x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87e03f4cd23af14f7d46ba90dc7b34ac219ba6ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729481 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l15x.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h index 9f957d8981..b13c4dd140 100644 --- a/chip/stm32/config-stm32l15x.h +++ b/chip/stm32/config-stm32l15x.h @@ -5,8 +5,8 @@ /* Memory mapping */ #define CONFIG_FLASH_SIZE_BYTES 0x00020000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0100 /* erase bank size */ /* * TODO(crosbug.com/p/23805): Technically we can write in word-mode (4 bytes at @@ -21,8 +21,8 @@ /* Ideal write size in page-mode */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0080 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00004000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00004000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 45 @@ -38,10 +38,10 @@ #define CONFIG_FLASH_ERASED_VALUE32 0 /* USB packet ram config */ -#define CONFIG_USB_RAM_BASE 0x40006000 -#define CONFIG_USB_RAM_SIZE 512 +#define CONFIG_USB_RAM_BASE 0x40006000 +#define CONFIG_USB_RAM_SIZE 512 #define CONFIG_USB_RAM_ACCESS_TYPE uint32_t #define CONFIG_USB_RAM_ACCESS_SIZE 4 /* DFU Address */ -#define STM32_DFU_BASE 0x1ff00000 +#define STM32_DFU_BASE 0x1ff00000 -- cgit v1.2.1 From 7f9697d7bf50bfa4f73a3c1947caec94c7b5e70d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:50 -0600 Subject: board/cret/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I205fb6d6d50b68dd4da6976d38a436d6c8bd6fa7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728188 Reviewed-by: Jeremy Bettis --- board/cret/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cret/usb_pd_policy.c b/board/cret/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/cret/usb_pd_policy.c +++ b/board/cret/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 0ee20402041637146eabfaf147caacbd98abbc55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:35 -0600 Subject: include/dma.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I80a4006b8f8637f09ded56a1ae77b9395cb6ad0e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730242 Reviewed-by: Jeremy Bettis --- include/dma.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/dma.h b/include/dma.h index 1687b5f899..8b8da9dc76 100644 --- a/include/dma.h +++ b/include/dma.h @@ -17,14 +17,14 @@ /* DMA channel options */ struct dma_option { - enum dma_channel channel; /* DMA channel */ - void *periph; /* Pointer to peripheral data register */ - unsigned flags; /* DMA flags for the control register. Normally - used to select memory size. */ + enum dma_channel channel; /* DMA channel */ + void *periph; /* Pointer to peripheral data register */ + unsigned flags; /* DMA flags for the control register. Normally + used to select memory size. */ }; -#define DMA_POLLING_INTERVAL_US 100 /* us */ -#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */ +#define DMA_POLLING_INTERVAL_US 100 /* us */ +#define DMA_TRANSFER_TIMEOUT_US (100 * MSEC) /* us */ /** * Get a pointer to a DMA channel. @@ -117,7 +117,7 @@ void dma_dump(enum dma_channel channel); * Testing: Test that DMA works correctly for memory to memory transfers */ void dma_test(enum dma_channel channel); -#endif /* CONFIG_DMA_HELP */ +#endif /* CONFIG_DMA_HELP */ /** * Clear the DMA interrupt/event flags for a given channel -- cgit v1.2.1 From c688ab321564643d912b04dd5860d64f644fc0a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:17 -0600 Subject: test/usb_tcpmv2_td_pd_src3_e26.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iddded0a88750065180d38493281bb94493c10a94 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730557 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src3_e26.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src3_e26.c b/test/usb_tcpmv2_td_pd_src3_e26.c index f5f5bcd3c4..ba9bab464c 100644 --- a/test/usb_tcpmv2_td_pd_src3_e26.c +++ b/test/usb_tcpmv2_td_pd_src3_e26.c @@ -47,8 +47,8 @@ int test_td_pd_src3_e26(void) * d) The Tester verifies that a Soft_Reset message is sent by the UUT * within tReceive max (1.1 ms) + tSoftReset max (15 ms). */ - TEST_EQ(verify_tcpci_tx_timeout( - TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, 15 * MSEC), + TEST_EQ(verify_tcpci_tx_timeout(TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET, 0, + 15 * MSEC), EC_SUCCESS, "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS); -- cgit v1.2.1 From 7ea46d2ea95393a91770801871caf3a36cadaf64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:14 -0600 Subject: chip/max32660/gpio_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0697b4a1317c2501f8ce6a09b7df036479d228df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729230 Reviewed-by: Jeremy Bettis --- chip/max32660/gpio_chip.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/chip/max32660/gpio_chip.c b/chip/max32660/gpio_chip.c index 1ef73890ec..e88069a5a6 100644 --- a/chip/max32660/gpio_chip.c +++ b/chip/max32660/gpio_chip.c @@ -21,10 +21,10 @@ #define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* 0-terminated list of GPIO base addresses */ -static mxc_gpio_regs_t *gpio_bases[] = {MXC_GPIO0, 0}; +static mxc_gpio_regs_t *gpio_bases[] = { MXC_GPIO0, 0 }; void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); @@ -42,7 +42,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, gpio->en1_set = mask; break; default: - /* Default as input */ + /* Default as input */ gpio->out_en_clr = mask; gpio->en_set = mask; gpio->en1_clr = mask; @@ -184,7 +184,7 @@ void gpio_pre_init(void) /* Use as GPIO, not alternate function */ gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); + GPIO_ALT_FUNC_NONE); /* Set up GPIO based on flags */ gpio_set_flags_by_mask(g->port, g->mask, flags); @@ -194,8 +194,8 @@ void gpio_pre_init(void) static void gpio_init(void) { /* - * Enable global GPIO0 Port interrupt. Note that interrupts still need to be - * enabled at the per pin level. + * Enable global GPIO0 Port interrupt. Note that interrupts still need + * to be enabled at the per pin level. */ task_enable_irq(EC_GPIO0_IRQn); } @@ -227,13 +227,13 @@ static void gpio_interrupt(int port, uint32_t mis) * Handlers for each GPIO port. Read the interrupt status, call the common GPIO * interrupt handler and clear the GPIO hardware interrupt status. */ -#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \ - static void irqfunc(void) \ - { \ - mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase); \ - uint32_t mis = gpio->int_stat; \ - gpio_interrupt(gpiobase, mis); \ - gpio->int_clr = mis; \ +#define GPIO_IRQ_FUNC(irqfunc, gpiobase) \ + static void irqfunc(void) \ + { \ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(gpiobase); \ + uint32_t mis = gpio->int_stat; \ + gpio_interrupt(gpiobase, mis); \ + gpio->int_clr = mis; \ } GPIO_IRQ_FUNC(__gpio_0_interrupt, PORT_0); -- cgit v1.2.1 From 0889531b9029dbcba2107343150b029546a20630 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:36 -0600 Subject: board/morphius/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I169d236e9cdc38c206590357c71c4f73171834c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728703 Reviewed-by: Jeremy Bettis --- board/morphius/thermal.c | 325 +++++++++++++++++++++++------------------------ 1 file changed, 161 insertions(+), 164 deletions(-) diff --git a/board/morphius/thermal.c b/board/morphius/thermal.c index a51dee7c8b..fa54eabe5e 100644 --- a/board/morphius/thermal.c +++ b/board/morphius/thermal.c @@ -20,7 +20,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -44,316 +44,315 @@ static const struct fan_step *fan_step_table; static const struct fan_step fan1_table_clamshell[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 40, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {1900}, + .on = { -1, -1, 40, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 1900 }, }, { /* level 2 */ - .on = {-1, -1, 45, -1}, - .off = {-1, -1, 43, -1}, - .rpm = {2900}, + .on = { -1, -1, 45, -1 }, + .off = { -1, -1, 43, -1 }, + .rpm = { 2900 }, }, { /* level 3 */ - .on = {-1, -1, 48, -1}, - .off = {-1, -1, 46, -1}, - .rpm = {3200}, + .on = { -1, -1, 48, -1 }, + .off = { -1, -1, 46, -1 }, + .rpm = { 3200 }, }, { /* level 4 */ - .on = {-1, -1, 51, -1}, - .off = {-1, -1, 49, -1}, - .rpm = {3550}, + .on = { -1, -1, 51, -1 }, + .off = { -1, -1, 49, -1 }, + .rpm = { 3550 }, }, { /* level 5 */ - .on = {-1, -1, 54, -1}, - .off = {-1, -1, 52, -1}, - .rpm = {3950}, + .on = { -1, -1, 54, -1 }, + .off = { -1, -1, 52, -1 }, + .rpm = { 3950 }, }, { /* level 6 */ - .on = {-1, -1, 57, -1}, - .off = {-1, -1, 55, -1}, - .rpm = {4250}, + .on = { -1, -1, 57, -1 }, + .off = { -1, -1, 55, -1 }, + .rpm = { 4250 }, }, { /* level 7 */ - .on = {-1, -1, 60, -1}, - .off = {-1, -1, 58, -1}, - .rpm = {4650}, + .on = { -1, -1, 60, -1 }, + .off = { -1, -1, 58, -1 }, + .rpm = { 4650 }, }, }; static const struct fan_step fan1_table_tablet[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 41, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {2100}, + .on = { -1, -1, 41, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 2100 }, }, { /* level 2 */ - .on = {-1, -1, 50, -1}, - .off = {-1, -1, 48, -1}, - .rpm = {2600}, + .on = { -1, -1, 50, -1 }, + .off = { -1, -1, 48, -1 }, + .rpm = { 2600 }, }, { /* level 3 */ - .on = {-1, -1, 54, -1}, - .off = {-1, -1, 52, -1}, - .rpm = {2800}, + .on = { -1, -1, 54, -1 }, + .off = { -1, -1, 52, -1 }, + .rpm = { 2800 }, }, { /* level 4 */ - .on = {-1, -1, 57, -1}, - .off = {-1, -1, 55, -1}, - .rpm = {3300}, + .on = { -1, -1, 57, -1 }, + .off = { -1, -1, 55, -1 }, + .rpm = { 3300 }, }, { /* level 5 */ - .on = {-1, -1, 60, -1}, - .off = {-1, -1, 58, -1}, - .rpm = {3800}, + .on = { -1, -1, 60, -1 }, + .off = { -1, -1, 58, -1 }, + .rpm = { 3800 }, }, { /* level 6 */ - .on = {-1, -1, 72, -1}, - .off = {-1, -1, 69, -1}, - .rpm = {4000}, + .on = { -1, -1, 72, -1 }, + .off = { -1, -1, 69, -1 }, + .rpm = { 4000 }, }, { /* level 7 */ - .on = {-1, -1, 74, -1}, - .off = {-1, -1, 73, -1}, - .rpm = {4300}, + .on = { -1, -1, 74, -1 }, + .off = { -1, -1, 73, -1 }, + .rpm = { 4300 }, }, }; static const struct fan_step fan1_table_stand[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 34, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {1850}, + .on = { -1, -1, 34, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 1850 }, }, { /* level 2 */ - .on = {-1, -1, 42, -1}, - .off = {-1, -1, 39, -1}, - .rpm = {2550}, + .on = { -1, -1, 42, -1 }, + .off = { -1, -1, 39, -1 }, + .rpm = { 2550 }, }, { /* level 3 */ - .on = {-1, -1, 49, -1}, - .off = {-1, -1, 48, -1}, - .rpm = {2900}, + .on = { -1, -1, 49, -1 }, + .off = { -1, -1, 48, -1 }, + .rpm = { 2900 }, }, { /* level 4 */ - .on = {-1, -1, 51, -1}, - .off = {-1, -1, 50, -1}, - .rpm = {3350}, + .on = { -1, -1, 51, -1 }, + .off = { -1, -1, 50, -1 }, + .rpm = { 3350 }, }, { /* level 5 */ - .on = {-1, -1, 53, -1}, - .off = {-1, -1, 52, -1}, - .rpm = {3700}, + .on = { -1, -1, 53, -1 }, + .off = { -1, -1, 52, -1 }, + .rpm = { 3700 }, }, { /* level 6 */ - .on = {-1, -1, 55, -1}, - .off = {-1, -1, 54, -1}, - .rpm = {3900}, + .on = { -1, -1, 55, -1 }, + .off = { -1, -1, 54, -1 }, + .rpm = { 3900 }, }, { /* level 7 */ - .on = {-1, -1, 57, -1}, - .off = {-1, -1, 56, -1}, - .rpm = {4250}, + .on = { -1, -1, 57, -1 }, + .off = { -1, -1, 56, -1 }, + .rpm = { 4250 }, }, }; static const struct fan_step fan0_table_clamshell[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 41, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {2350}, + .on = { -1, -1, 41, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 2350 }, }, { /* level 2 */ - .on = {-1, -1, 44, -1}, - .off = {-1, -1, 42, -1}, - .rpm = {3300}, + .on = { -1, -1, 44, -1 }, + .off = { -1, -1, 42, -1 }, + .rpm = { 3300 }, }, { /* level 3 */ - .on = {-1, -1, 47, -1}, - .off = {-1, -1, 45, -1}, - .rpm = {3600}, + .on = { -1, -1, 47, -1 }, + .off = { -1, -1, 45, -1 }, + .rpm = { 3600 }, }, { /* level 4 */ - .on = {-1, -1, 50, -1}, - .off = {-1, -1, 48, -1}, - .rpm = {4050}, + .on = { -1, -1, 50, -1 }, + .off = { -1, -1, 48, -1 }, + .rpm = { 4050 }, }, { /* level 5 */ - .on = {-1, -1, 53, -1}, - .off = {-1, -1, 51, -1}, - .rpm = {4450}, + .on = { -1, -1, 53, -1 }, + .off = { -1, -1, 51, -1 }, + .rpm = { 4450 }, }, { /* level 6 */ - .on = {-1, -1, 56, -1}, - .off = {-1, -1, 54, -1}, - .rpm = {4750}, + .on = { -1, -1, 56, -1 }, + .off = { -1, -1, 54, -1 }, + .rpm = { 4750 }, }, { /* level 7 */ - .on = {-1, -1, 59, -1}, - .off = {-1, -1, 57, -1}, - .rpm = {5150}, + .on = { -1, -1, 59, -1 }, + .off = { -1, -1, 57, -1 }, + .rpm = { 5150 }, }, }; static const struct fan_step fan0_table_tablet[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 41, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {2250}, + .on = { -1, -1, 41, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 2250 }, }, { /* level 2 */ - .on = {-1, -1, 50, -1}, - .off = {-1, -1, 48, -1}, - .rpm = {2850}, + .on = { -1, -1, 50, -1 }, + .off = { -1, -1, 48, -1 }, + .rpm = { 2850 }, }, { /* level 3 */ - .on = {-1, -1, 54, -1}, - .off = {-1, -1, 51, -1}, - .rpm = {3100}, + .on = { -1, -1, 54, -1 }, + .off = { -1, -1, 51, -1 }, + .rpm = { 3100 }, }, { /* level 4 */ - .on = {-1, -1, 57, -1}, - .off = {-1, -1, 55, -1}, - .rpm = {3500}, + .on = { -1, -1, 57, -1 }, + .off = { -1, -1, 55, -1 }, + .rpm = { 3500 }, }, { /* level 5 */ - .on = {-1, -1, 60, -1}, - .off = {-1, -1, 58, -1}, - .rpm = {3900}, + .on = { -1, -1, 60, -1 }, + .off = { -1, -1, 58, -1 }, + .rpm = { 3900 }, }, { /* level 6 */ - .on = {-1, -1, 72, -1}, - .off = {-1, -1, 69, -1}, - .rpm = {4150}, + .on = { -1, -1, 72, -1 }, + .off = { -1, -1, 69, -1 }, + .rpm = { 4150 }, }, { /* level 7 */ - .on = {-1, -1, 74, -1}, - .off = {-1, -1, 73, -1}, - .rpm = {4400}, + .on = { -1, -1, 74, -1 }, + .off = { -1, -1, 73, -1 }, + .rpm = { 4400 }, }, }; static const struct fan_step fan0_table_stand[] = { { /* level 0 */ - .on = {-1, -1, -1, -1}, - .off = {-1, -1, -1, -1}, - .rpm = {0}, + .on = { -1, -1, -1, -1 }, + .off = { -1, -1, -1, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 34, -1}, - .off = {-1, -1, 31, -1}, - .rpm = {2250}, + .on = { -1, -1, 34, -1 }, + .off = { -1, -1, 31, -1 }, + .rpm = { 2250 }, }, { /* level 2 */ - .on = {-1, -1, 42, -1}, - .off = {-1, -1, 39, -1}, - .rpm = {2800}, + .on = { -1, -1, 42, -1 }, + .off = { -1, -1, 39, -1 }, + .rpm = { 2800 }, }, { /* level 3 */ - .on = {-1, -1, 49, -1}, - .off = {-1, -1, 48, -1}, - .rpm = {3150}, + .on = { -1, -1, 49, -1 }, + .off = { -1, -1, 48, -1 }, + .rpm = { 3150 }, }, { /* level 4 */ - .on = {-1, -1, 51, -1}, - .off = {-1, -1, 50, -1}, - .rpm = {3550}, + .on = { -1, -1, 51, -1 }, + .off = { -1, -1, 50, -1 }, + .rpm = { 3550 }, }, { /* level 5 */ - .on = {-1, -1, 53, -1}, - .off = {-1, -1, 52, -1}, - .rpm = {3900}, + .on = { -1, -1, 53, -1 }, + .off = { -1, -1, 52, -1 }, + .rpm = { 3900 }, }, { /* level 6 */ - .on = {-1, -1, 55, -1}, - .off = {-1, -1, 54, -1}, - .rpm = {4150}, + .on = { -1, -1, 55, -1 }, + .off = { -1, -1, 54, -1 }, + .rpm = { 4150 }, }, { /* level 7 */ - .on = {-1, -1, 57, -1}, - .off = {-1, -1, 56, -1}, - .rpm = {4400}, + .on = { -1, -1, 57, -1 }, + .off = { -1, -1, 56, -1 }, + .rpm = { 4400 }, }, }; #define NUM_FAN_LEVELS ARRAY_SIZE(fan1_table_clamshell) -#define lid_angle_tablet 340 +#define lid_angle_tablet 340 static int throttle_on; -BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) == - ARRAY_SIZE(fan1_table_tablet)); +BUILD_ASSERT(ARRAY_SIZE(fan1_table_clamshell) == ARRAY_SIZE(fan1_table_tablet)); #define average_time 60 int fan_table_to_rpm(int fan, int *temp) @@ -404,7 +403,7 @@ int fan_table_to_rpm(int fan, int *temp) for (j = 0; j < average_time; j++) avg_sum = avg_sum + avg_calc_tmp[TEMP_SENSOR_CPU][j]; - avg_tmp[TEMP_SENSOR_CPU] = avg_sum/average_time; + avg_tmp[TEMP_SENSOR_CPU] = avg_sum / average_time; /* * Compare the current and previous temperature, we have @@ -416,10 +415,10 @@ int fan_table_to_rpm(int fan, int *temp) if (avg_tmp[TEMP_SENSOR_CPU] < prev_tmp[TEMP_SENSOR_CPU]) { for (i = current_level; i >= 0; i--) { if (avg_tmp[TEMP_SENSOR_CPU] < - fan_step_table[i].off[TEMP_SENSOR_CPU]) { - /* - * fan step down debounce - */ + fan_step_table[i].off[TEMP_SENSOR_CPU]) { + /* + * fan step down debounce + */ if (fan_down_count < 10) { fan_down_count++; fan_up_count = 0; @@ -434,12 +433,12 @@ int fan_table_to_rpm(int fan, int *temp) break; } } else if (avg_tmp[TEMP_SENSOR_CPU] > prev_tmp[TEMP_SENSOR_CPU]) { - for (i = current_level+1; i < NUM_FAN_LEVELS; i++) { + for (i = current_level + 1; i < NUM_FAN_LEVELS; i++) { if ((avg_tmp[TEMP_SENSOR_CPU] > - fan_step_table[i].on[TEMP_SENSOR_CPU])) { - /* - * fan step up debounce - */ + fan_step_table[i].on[TEMP_SENSOR_CPU])) { + /* + * fan step up debounce + */ if (fan_up_count < 10) { fan_up_count++; fan_down_count = 0; @@ -499,10 +498,8 @@ void thermal_protect(void) int rv1, rv2; int thermal_sensor1, thermal_sensor2; - rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR, - &thermal_sensor1); - rv2 = temp_sensor_read(TEMP_SENSOR_CPU, - &thermal_sensor2); + rv1 = temp_sensor_read(TEMP_SENSOR_5V_REGULATOR, &thermal_sensor1); + rv2 = temp_sensor_read(TEMP_SENSOR_CPU, &thermal_sensor2); if (rv2 == EC_SUCCESS) { if ((!lid_is_open()) && (!extpower_is_present())) { @@ -523,8 +520,8 @@ void thermal_protect(void) } if (rv1 == EC_SUCCESS) { - if ((!lid_is_open()) && (!extpower_is_present()) - && thermal_sensor1 > C_TO_K(51)) + if ((!lid_is_open()) && (!extpower_is_present()) && + thermal_sensor1 > C_TO_K(51)) chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); } } -- cgit v1.2.1 From 65c480cf0bd3d6954532a47ad98fed95cb34f368 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:00 -0600 Subject: common/keyboard_test.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I860814833129ac0497bc65dac16f133226716a50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729643 Reviewed-by: Jeremy Bettis --- common/keyboard_test.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/common/keyboard_test.c b/common/keyboard_test.c index e7b1dfe501..79345a1b4c 100644 --- a/common/keyboard_test.c +++ b/common/keyboard_test.c @@ -13,8 +13,8 @@ #include enum { - KEYSCAN_MAX_LENGTH = 20, - KEYSCAN_SEQ_START_DELAY_US = 10000, + KEYSCAN_MAX_LENGTH = 20, + KEYSCAN_SEQ_START_DELAY_US = 10000, }; static uint8_t keyscan_seq_count; @@ -151,8 +151,8 @@ static int keyscan_seq_collect(struct ec_params_keyscan_seq_ctrl *req, resp->collect.num_items = end - start; for (i = start, ksi = keyscan_items; i < end; i++, ksi++) - resp->collect.item[i].flags = ksi->done ? - EC_KEYSCAN_SEQ_FLAG_DONE : 0; + resp->collect.item[i].flags = + ksi->done ? EC_KEYSCAN_SEQ_FLAG_DONE : 0; return sizeof(*resp) + resp->collect.num_items; } @@ -186,7 +186,8 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args) keyscan_seq_start(); break; case EC_KEYSCAN_SEQ_COLLECT: - args->response_size = keyscan_seq_collect(&req, + args->response_size = keyscan_seq_collect( + &req, (struct ec_result_keyscan_seq_ctrl *)args->response); break; default: @@ -196,6 +197,4 @@ static enum ec_status keyscan_seq_ctrl(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL, - keyscan_seq_ctrl, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_KEYSCAN_SEQ_CTRL, keyscan_seq_ctrl, EC_VER_MASK(0)); -- cgit v1.2.1 From 27c573587d9967b4d2710444e738cf4532973e50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:05 -0600 Subject: driver/charger/rt9490.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3fe4a2d4bb4871be32d4b20e6aaf1428dfc1f7d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729939 Reviewed-by: Jeremy Bettis --- driver/charger/rt9490.c | 107 ++++++++++++++++++++++-------------------------- 1 file changed, 50 insertions(+), 57 deletions(-) diff --git a/driver/charger/rt9490.c b/driver/charger/rt9490.c index 2d69e843e9..b87e6ccceb 100644 --- a/driver/charger/rt9490.c +++ b/driver/charger/rt9490.c @@ -22,33 +22,33 @@ #include "util.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #define CPRINTS(format, args...) \ - cprints(CC_CHARGER, "%s " format, "RT9490", ## args) + cprints(CC_CHARGER, "%s " format, "RT9490", ##args) /* Charger parameters */ -#define CHARGER_NAME "rt9490" -#define CHARGE_V_MAX 18800 -#define CHARGE_V_MIN 3000 -#define CHARGE_V_STEP 10 -#define CHARGE_I_MAX 5000 -#define CHARGE_I_MIN 50 -#define CHARGE_I_STEP 10 -#define INPUT_I_MAX 3300 -#define INPUT_I_MIN 100 -#define INPUT_I_STEP 10 +#define CHARGER_NAME "rt9490" +#define CHARGE_V_MAX 18800 +#define CHARGE_V_MIN 3000 +#define CHARGE_V_STEP 10 +#define CHARGE_I_MAX 5000 +#define CHARGE_I_MIN 50 +#define CHARGE_I_STEP 10 +#define INPUT_I_MAX 3300 +#define INPUT_I_MIN 100 +#define INPUT_I_STEP 10 /* Charger parameters */ static const struct charger_info rt9490_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = CHARGE_I_MAX, - .current_min = CHARGE_I_MIN, + .current_max = CHARGE_I_MAX, + .current_min = CHARGE_I_MIN, .current_step = CHARGE_I_STEP, - .input_current_max = INPUT_I_MAX, - .input_current_min = INPUT_I_MIN, + .input_current_max = INPUT_I_MAX, + .input_current_min = INPUT_I_MIN, .input_current_step = INPUT_I_STEP, }; @@ -62,13 +62,13 @@ static const struct rt9490_init_setting default_init_setting = { static enum ec_error_list rt9490_read8(int chgnum, int reg, int *val) { return i2c_read8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, reg, val); + chg_chips[chgnum].i2c_addr_flags, reg, val); } static enum ec_error_list rt9490_write8(int chgnum, int reg, int val) { return i2c_write8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, reg, val); + chg_chips[chgnum].i2c_addr_flags, reg, val); } static enum ec_error_list rt9490_read16(int chgnum, int reg, uint16_t *val) @@ -76,7 +76,8 @@ static enum ec_error_list rt9490_read16(int chgnum, int reg, uint16_t *val) int reg_val; RETURN_ERROR(i2c_read16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, reg, ®_val)); + chg_chips[chgnum].i2c_addr_flags, reg, + ®_val)); *val = be16toh(reg_val); @@ -88,22 +89,21 @@ static enum ec_error_list rt9490_write16(int chgnum, int reg, uint16_t val) int reg_val = htobe16(val); return i2c_write16(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, reg, reg_val); + chg_chips[chgnum].i2c_addr_flags, reg, reg_val); } static int rt9490_field_update8(int chgnum, int reg, int mask, int val) { return i2c_field_update8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - reg, mask, val); + chg_chips[chgnum].i2c_addr_flags, reg, mask, + val); } static inline int rt9490_update8(int chgnum, int reg, int mask, enum mask_update_action action) { return i2c_update8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - reg, mask, action); + chg_chips[chgnum].i2c_addr_flags, reg, mask, action); } static inline int rt9490_set_bit(int chgnum, int reg, int mask) @@ -130,7 +130,7 @@ static const struct charger_info *rt9490_get_info(int chgnum) static enum ec_error_list rt9490_get_current(int chgnum, int *current) { uint16_t val = 0; - const struct charger_info * const info = rt9490_get_info(chgnum); + const struct charger_info *const info = rt9490_get_info(chgnum); RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_ICHG_CTRL, &val)); @@ -159,7 +159,7 @@ static enum ec_error_list rt9490_set_current(int chgnum, int current) static enum ec_error_list rt9490_get_voltage(int chgnum, int *voltage) { uint16_t val = 0; - const struct charger_info * const info = rt9490_get_info(chgnum); + const struct charger_info *const info = rt9490_get_info(chgnum); RETURN_ERROR(rt9490_read16(chgnum, RT9490_REG_VCHG_CTRL, &val)); @@ -287,48 +287,42 @@ static int rt9490_init_setting(int chgnum) /* Disable boost-mode output voltage */ RETURN_ERROR(rt9490_enable_otg_power(chgnum, 0)); RETURN_ERROR(rt9490_set_otg_current_voltage( - chgnum, - default_init_setting.boost_current, - default_init_setting.boost_voltage)); + chgnum, default_init_setting.boost_current, + default_init_setting.boost_voltage)); #endif /* Disable ILIM_HZ pin current limit */ - RETURN_ERROR(rt9490_clr_bit( - chgnum, RT9490_REG_CHG_CTRL5, RT9490_ILIM_HZ_EN)); + RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_CHG_CTRL5, + RT9490_ILIM_HZ_EN)); /* Disable BC 1.2 detection by default. It will be enabled on demand */ RETURN_ERROR(rt9490_enable_chgdet_flow(chgnum, false)); /* Disable WDT */ RETURN_ERROR(rt9490_enable_wdt(chgnum, false)); /* Disable battery thermal protection */ - RETURN_ERROR(rt9490_set_bit( - chgnum, RT9490_REG_ADD_CTRL0, RT9490_JEITA_COLD_HOT)); + RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_ADD_CTRL0, + RT9490_JEITA_COLD_HOT)); /* Disable AUTO_AICR / AUTO_MIVR */ - RETURN_ERROR(rt9490_clr_bit( - chgnum, - RT9490_REG_ADD_CTRL0, - RT9490_AUTO_AICR | RT9490_AUTO_MIVR)); + RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_ADD_CTRL0, + RT9490_AUTO_AICR | RT9490_AUTO_MIVR)); /* Disable charge timer */ - RETURN_ERROR(rt9490_clr_bit( - chgnum, - RT9490_REG_SAFETY_TMR_CTRL, - RT9490_EN_TRICHG_TMR | - RT9490_EN_PRECHG_TMR | - RT9490_EN_FASTCHG_TMR)); + RETURN_ERROR(rt9490_clr_bit(chgnum, RT9490_REG_SAFETY_TMR_CTRL, + RT9490_EN_TRICHG_TMR | + RT9490_EN_PRECHG_TMR | + RT9490_EN_FASTCHG_TMR)); RETURN_ERROR(rt9490_set_mivr(chgnum, default_init_setting.mivr)); RETURN_ERROR(rt9490_set_ieoc(chgnum, default_init_setting.eoc_current)); RETURN_ERROR(rt9490_set_iprec(chgnum, batt_info->precharge_current)); RETURN_ERROR(rt9490_enable_adc(chgnum, true)); RETURN_ERROR(rt9490_enable_jeita(chgnum, false)); RETURN_ERROR(rt9490_field_update8( - chgnum, RT9490_REG_CHG_CTRL1, RT9490_VAC_OVP_MASK, - RT9490_VAC_OVP_26V << RT9490_VAC_OVP_SHIFT)); - + chgnum, RT9490_REG_CHG_CTRL1, RT9490_VAC_OVP_MASK, + RT9490_VAC_OVP_26V << RT9490_VAC_OVP_SHIFT)); /* Mask all interrupts except BC12 done */ RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK0, RT9490_CHG_IRQ_MASK0_ALL)); RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK1, RT9490_CHG_IRQ_MASK1_ALL & - ~RT9490_BC12_DONE_MASK)); + ~RT9490_BC12_DONE_MASK)); RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK2, RT9490_CHG_IRQ_MASK2_ALL)); RETURN_ERROR(rt9490_set_bit(chgnum, RT9490_REG_CHG_IRQ_MASK3, @@ -344,7 +338,7 @@ static int rt9490_init_setting(int chgnum) int rt9490_enable_pwm_1mhz(int chgnum, bool en) { return rt9490_update8(chgnum, RT9490_REG_ADD_CTRL1, RT9490_PWM_1MHZ_EN, - en ? MASK_SET : MASK_CLR); + en ? MASK_SET : MASK_CLR); } static void rt9490_init(int chgnum) @@ -623,7 +617,7 @@ static void rt9490_update_charge_manager(int port, if (new_bc12_type != current_bc12_type) { if (current_bc12_type >= 0) charge_manager_update_charge(current_bc12_type, port, - NULL); + NULL); if (new_bc12_type != CHARGE_SUPPLIER_NONE) { struct charge_port_info chg = { @@ -660,17 +654,16 @@ static void rt9490_usb_charger_task_event(const int port, uint32_t evt) * to always trigger bc1.2 detection for other cases. */ bool is_non_pd_sink = !pd_capable(port) && - !usb_charger_port_is_sourcing_vbus(port) && - pd_check_vbus_level(port, VBUS_PRESENT); + !usb_charger_port_is_sourcing_vbus(port) && + pd_check_vbus_level(port, VBUS_PRESENT); /* vbus change, start bc12 detection */ if (evt & USB_CHG_EVENT_VBUS) { - if (is_non_pd_sink) rt9490_enable_chgdet_flow(CHARGER_SOLO, true); else - rt9490_update_charge_manager( - port, CHARGE_SUPPLIER_NONE); + rt9490_update_charge_manager(port, + CHARGE_SUPPLIER_NONE); } /* detection done, update charge_manager and stop detection */ -- cgit v1.2.1 From 225a5b9797b7c3b37a9632a3df2beb7f8206120a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:27 -0600 Subject: board/drawcia/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic28a8b310785831a604b5cd1fc210deccb12c46a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728237 Reviewed-by: Jeremy Bettis --- board/drawcia/board.c | 176 +++++++++++++++++++++++--------------------------- 1 file changed, 80 insertions(+), 96 deletions(-) diff --git a/board/drawcia/board.c b/board/drawcia/board.c index ce6247e931..a86c163db8 100644 --- a/board/drawcia/board.c +++ b/board/drawcia/board.c @@ -43,7 +43,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -182,48 +182,36 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, - [ADC_TEMP_SENSOR_4] = { - .name = "TEMP_SENSOR4", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH16 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, + [ADC_TEMP_SENSOR_4] = { .name = "TEMP_SENSOR4", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH16 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -298,17 +286,13 @@ static struct accelgyro_saved_data_t g_bma422_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Drivers */ struct motion_sensor_t motion_sensors[] = { @@ -564,8 +548,8 @@ __override void board_power_5v_enable(int enable) if (board_get_charger_chip_count() > 1) { if (sm5803_set_gpio0_level(1, !!enable)) - CPRINTUSB("Failed to %sable sub rails!", enable ? - "en" : "dis"); + CPRINTUSB("Failed to %sable sub rails!", + enable ? "en" : "dis"); } } @@ -573,11 +557,11 @@ __override uint8_t board_get_usb_pd_port_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CONFIG_USB_PD_PORT_MAX_COUNT; ccprints("Unhandled DB configuration: %d", db); @@ -588,11 +572,11 @@ __override uint8_t board_get_charger_chip_count(void) { enum fw_config_db db = get_cbi_fw_config_db(); - if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI - || db == DB_1A_HDMI_LTE) + if (db == DB_1A_HDMI || db == DB_NONE || db == DB_LTE_HDMI || + db == DB_1A_HDMI_LTE) return CHARGER_NUM - 1; - else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A - || db == DB_1C_1A_LTE) + else if (db == DB_1C || db == DB_1C_LTE || db == DB_1C_1A || + db == DB_1C_1A_LTE) return CHARGER_NUM; ccprints("Unhandled DB configuration: %d", db); @@ -697,33 +681,31 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, - [TEMP_SENSOR_4] = {.name = "5V regular", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_4}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, + [TEMP_SENSOR_4] = { .name = "5V regular", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -753,9 +735,8 @@ __override void lid_angle_peripheral_enable(int enable) } } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 20; @@ -774,14 +755,17 @@ __override void ocpc_get_pid_constants(int *kp, int *kp_div, * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, - {GPIO_KSO_L, 3}, {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, - {GPIO_KSO_L, 4}, {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, - {GPIO_KSI, 5}, {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, - {GPIO_KSI, 7}, {GPIO_KSI, 1}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { GPIO_KSO_L, 5 }, { GPIO_KSO_L, 6 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From 715e6fdabedd58dff02f3594cd8ee9d9f8ec7ffd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:56 -0600 Subject: chip/mt_scp/mt818x/ipi_table.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7371d7b3a3d87f2c08336d9802e04bf96aa7965a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729340 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/ipi_table.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/chip/mt_scp/mt818x/ipi_table.c b/chip/mt_scp/mt818x/ipi_table.c index 8569ab24a7..ef68e200b3 100644 --- a/chip/mt_scp/mt818x/ipi_table.c +++ b/chip/mt_scp/mt818x/ipi_table.c @@ -17,21 +17,24 @@ typedef void (*ipi_handler_t)(int32_t id, void *data, uint32_t len); #define ipi_arguments int32_t id, void *data, uint32_t len #if PASS == 1 -void ipi_handler_undefined(ipi_arguments) { } +void ipi_handler_undefined(ipi_arguments) +{ +} const int ipi_wakeup_undefined; #define table(type, name, x) x -#define ipi_x_func(suffix, args, number) \ - extern void __attribute__( \ - (used, weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ +#define ipi_x_func(suffix, args, number) \ + extern void \ + __attribute__((used, weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ ipi_##number##_##suffix(args); #define ipi_x_var(suffix, number) \ - extern int __attribute__( \ - (weak, alias(STRINGIFY(ipi_##suffix##_undefined)))) \ - ipi_##number##_##suffix; + extern int __attribute__((weak, \ + alias(STRINGIFY(ipi_##suffix##_undefined)))) \ + ipi_##number##_##suffix; #endif /* PASS == 1 */ @@ -41,11 +44,11 @@ const int ipi_wakeup_undefined; #undef ipi_x_func #undef ipi_x_var -#define table(type, name, x) \ - type name[] __aligned(4) \ - __attribute__((section(".rodata.ipi, \"a\" @"))) = {x} +#define table(type, name, x) \ + type name[] __aligned(4) \ + __attribute__((section(".rodata.ipi, \"a\" @"))) = { x } -#define ipi_x_var(suffix, number) \ +#define ipi_x_var(suffix, number) \ [number < IPI_COUNT ? number : -1] = &ipi_##number##_##suffix, #define ipi_x_func(suffix, args, number) ipi_x_var(suffix, number) -- cgit v1.2.1 From fb154e93a8426fba5ae8cbdf75efed1b2cf0b03f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:47 -0600 Subject: board/coral/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I06d6b217f883f5d8eb26f2004f91b7470e63cf05 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728158 Reviewed-by: Jeremy Bettis --- board/coral/board.c | 190 +++++++++++++++++++++++----------------------------- 1 file changed, 85 insertions(+), 105 deletions(-) diff --git a/board/coral/board.c b/board/coral/board.c index 21729489bc..1f1a024c14 100644 --- a/board/coral/board.c +++ b/board/coral/board.c @@ -53,15 +53,15 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) -#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) +#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 static int sku_id; @@ -128,66 +128,51 @@ void tablet_mode_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { /* Vfs = Vref = 2.816V, 10-bit unsigned reading */ - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_TEMP_SENSOR_AMB] = { - "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_BOARD_ID] = { - "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_BOARD_SKU_1] = { - "BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_BOARD_SKU_0] = { - "BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, + [ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_BOARD_SKU_1] = { "BRD_SKU_1", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_BOARD_SKU_0] = { "BRD_SKU_0", NPCX_ADC_CH4, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { 4, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_KBLIGHT] = { 4, PWM_CONFIG_DSLEEP, 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "accelgyro", - .port = I2C_PORT_GYRO, - .kbps = 400, - .scl = GPIO_EC_I2C_GYRO_SCL, - .sda = GPIO_EC_I2C_GYRO_SDA - }, - { - .name = "sensors", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, - { - .name = "batt", - .port = NPCX_I2C_PORT3, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "accelgyro", + .port = I2C_PORT_GYRO, + .kbps = 400, + .scl = GPIO_EC_I2C_GYRO_SCL, + .sda = GPIO_EC_I2C_GYRO_SDA }, + { .name = "sensors", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, + { .name = "batt", + .port = NPCX_I2C_PORT3, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -419,28 +404,28 @@ static void board_tcpc_init(void) gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET); #endif /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_DEFAULT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -564,8 +549,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Enable charging trigger by BC1.2 detection */ int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP || @@ -577,8 +562,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, return; charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -688,17 +673,17 @@ void board_hibernate_late(void) int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs in hibernate */ - {GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN}, + { GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN }, /* * BD99956 handles charge input automatically. We'll disable * charge output in hibernate. Charger will assert ACOK_OD * when VBUS or VCC are plugged in. */ - {GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, - {GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + { GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, + { GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, }; /* Change GPIOs' state in hibernate for better power consumption */ @@ -725,17 +710,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t mag_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -845,8 +826,8 @@ static void board_set_motion_sensor_count(uint8_t sku_id) * sensor. If a new SKU id is used that is not in the table, then the * number of motion sensors will remain as ARRAY_SIZE(motion_sensors). */ - motion_sensor_count = SKU_IS_CONVERTIBLE(sku_id) ? - ARRAY_SIZE(motion_sensors) : 0; + motion_sensor_count = + SKU_IS_CONVERTIBLE(sku_id) ? ARRAY_SIZE(motion_sensors) : 0; CPRINTS("Motion Sensor Count = %d", motion_sensor_count); } @@ -857,11 +838,11 @@ struct { } const coral_board_versions[] = { /* Vin = 3.3V, Ideal voltage, R2 values listed below */ /* R1 = 51.1 kOhm */ - { BOARD_VERSION_1, 200 }, /* 124 mV, 2.0 Kohm */ - { BOARD_VERSION_2, 366 }, /* 278 mV, 4.7 Kohm */ - { BOARD_VERSION_3, 550 }, /* 456 mV, 8.2 Kohm */ - { BOARD_VERSION_4, 752 }, /* 644 mV, 12.4 Kohm */ - { BOARD_VERSION_5, 927}, /* 860 mV, 18.0 Kohm */ + { BOARD_VERSION_1, 200 }, /* 124 mV, 2.0 Kohm */ + { BOARD_VERSION_2, 366 }, /* 278 mV, 4.7 Kohm */ + { BOARD_VERSION_3, 550 }, /* 456 mV, 8.2 Kohm */ + { BOARD_VERSION_4, 752 }, /* 644 mV, 12.4 Kohm */ + { BOARD_VERSION_5, 927 }, /* 860 mV, 18.0 Kohm */ { BOARD_VERSION_6, 1073 }, /* 993 mV, 22.0 Kohm */ { BOARD_VERSION_7, 1235 }, /* 1152 mV, 27.4 Kohm */ { BOARD_VERSION_8, 1386 }, /* 1318 mV, 34.0 Kohm */ @@ -948,8 +929,8 @@ static void print_form_factor_list(int low, int high) if (high > 255) high = 255; for (id = low; id <= high; id++) { - ccprintf("SKU ID %03d: %s\n", id, SKU_IS_CONVERTIBLE(id) ? - "Convertible" : "Clamshell"); + ccprintf("SKU ID %03d: %s\n", id, + SKU_IS_CONVERTIBLE(id) ? "Convertible" : "Clamshell"); /* Don't print too many lines at once */ if (!(++count % 5)) msleep(20); @@ -999,8 +980,7 @@ static int command_sku(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(sku, command_sku, - "", +DECLARE_CONSOLE_COMMAND(sku, command_sku, "", "Get board id, sku, form factor"); __override uint32_t board_get_sku_id(void) -- cgit v1.2.1 From 97f270a3a64b666e801185d9c844860990091824 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:40 -0600 Subject: zephyr/projects/nissa/include/nissa_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7a84e891d0b672e63368eb9514e86805dfffc8f8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730781 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/include/nissa_common.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/projects/nissa/include/nissa_common.h b/zephyr/projects/nissa/include/nissa_common.h index 7ee9056a71..8561d4825c 100644 --- a/zephyr/projects/nissa/include/nissa_common.h +++ b/zephyr/projects/nissa/include/nissa_common.h @@ -11,11 +11,11 @@ #include "usb_mux.h" enum nissa_sub_board_type { - NISSA_SB_UNKNOWN = -1, /* Uninitialised */ - NISSA_SB_NONE = 0, /* No board defined */ - NISSA_SB_C_A = 1, /* USB type C, USB type A */ - NISSA_SB_C_LTE = 2, /* USB type C, WWAN LTE */ - NISSA_SB_HDMI_A = 3, /* HDMI, USB type A */ + NISSA_SB_UNKNOWN = -1, /* Uninitialised */ + NISSA_SB_NONE = 0, /* No board defined */ + NISSA_SB_C_A = 1, /* USB type C, USB type A */ + NISSA_SB_C_LTE = 2, /* USB type C, WWAN LTE */ + NISSA_SB_HDMI_A = 3, /* HDMI, USB type A */ }; extern struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT]; -- cgit v1.2.1 From 7905e10c0e2dcb4f85e696cf8b31fddd52a23f7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:53 -0600 Subject: baseboard/octopus/variant_ec_ite8320.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If4b9d758492c602bca6314e7863088af0a82a0b6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727939 Reviewed-by: Jeremy Bettis --- baseboard/octopus/variant_ec_ite8320.c | 60 ++++++++++++++-------------------- 1 file changed, 25 insertions(+), 35 deletions(-) diff --git a/baseboard/octopus/variant_ec_ite8320.c b/baseboard/octopus/variant_ec_ite8320.c index 72c0021e89..e63986ab96 100644 --- a/baseboard/octopus/variant_ec_ite8320.c +++ b/baseboard/octopus/variant_ec_ite8320.c @@ -28,40 +28,30 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "sensor", - .port = IT83XX_I2C_CH_B, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "usbc0", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "usbc1", - .port = IT83XX_I2C_CH_E, - .kbps = 400, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, - { - .name = "eeprom", - .port = IT83XX_I2C_CH_F, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, + { .name = "power", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "sensor", + .port = IT83XX_I2C_CH_B, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "usbc0", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "usbc1", + .port = IT83XX_I2C_CH_E, + .kbps = 400, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, + { .name = "eeprom", + .port = IT83XX_I2C_CH_F, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From 04d6bc62e936ce73756eefe123b8f77f338b1043 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:37 -0600 Subject: core/cortex-m/fpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37ab831aa135bdf434b636f83e180abc74f60fff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729818 Reviewed-by: Jeremy Bettis --- core/cortex-m/fpu.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/core/cortex-m/fpu.c b/core/cortex-m/fpu.c index 29fa568fd8..03175b2045 100644 --- a/core/cortex-m/fpu.c +++ b/core/cortex-m/fpu.c @@ -9,8 +9,8 @@ #include "hooks.h" #include "task.h" -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPUTS(format, args...) cputs(CC_SYSTEM, format, ##args) /* Floating point unit common code */ @@ -65,8 +65,7 @@ static void fpu_warn(void) DECLARE_DEFERRED(fpu_warn); -test_mockable -void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp) +test_mockable void __keep fpu_irq(uint32_t excep_lr, uint32_t excep_sp) { /* * Get address of exception FPU exception frame. FPCAR register points -- cgit v1.2.1 From 6caf0ef8579b7b9003dae9ba243f4584312d8e26 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:13 -0600 Subject: zephyr/include/dt-bindings/battery.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9f138f3781449b857ee65ba21ee704ee7245fcb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730712 Reviewed-by: Jeremy Bettis --- zephyr/include/dt-bindings/battery.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/include/dt-bindings/battery.h b/zephyr/include/dt-bindings/battery.h index c87de79b45..a8c6fc0a95 100644 --- a/zephyr/include/dt-bindings/battery.h +++ b/zephyr/include/dt-bindings/battery.h @@ -10,11 +10,11 @@ * Macros used by LED devicetree files (led.dts) to define battery-level * range. */ -#define BATTERY_LEVEL_EMPTY 0 -#define BATTERY_LEVEL_SHUTDOWN 3 -#define BATTERY_LEVEL_CRITICAL 5 -#define BATTERY_LEVEL_LOW 10 -#define BATTERY_LEVEL_NEAR_FULL 97 -#define BATTERY_LEVEL_FULL 100 +#define BATTERY_LEVEL_EMPTY 0 +#define BATTERY_LEVEL_SHUTDOWN 3 +#define BATTERY_LEVEL_CRITICAL 5 +#define BATTERY_LEVEL_LOW 10 +#define BATTERY_LEVEL_NEAR_FULL 97 +#define BATTERY_LEVEL_FULL 100 #endif /* DT_BINDINGS_BATTERY_H_ */ -- cgit v1.2.1 From 70f58795693b0a1f8848e5207da48fbcf9cf6ced Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:37 -0600 Subject: driver/accelgyro_icm42607.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iffb6a43b9f552de1e2e7a6770d7303a4d185b0b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729916 Reviewed-by: Jeremy Bettis --- driver/accelgyro_icm42607.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/driver/accelgyro_icm42607.c b/driver/accelgyro_icm42607.c index 0edb1426ab..8d9adaa054 100644 --- a/driver/accelgyro_icm42607.c +++ b/driver/accelgyro_icm42607.c @@ -27,11 +27,11 @@ #endif #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCELGYRO_ICM42607_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; static int icm_switch_on_mclk(const struct motion_sensor_t *s) { @@ -156,8 +156,7 @@ static int icm42607_normalize(const struct motion_sensor_t *s, intv3_t v, v[Z] = (int16_t)UINT16_FROM_BYTE_ARRAY_LE(raw, 4); /* check if data is valid */ - if (v[X] == ICM42607_INVALID_DATA && - v[Y] == ICM42607_INVALID_DATA && + if (v[X] == ICM42607_INVALID_DATA && v[Y] == ICM42607_INVALID_DATA && v[Z] == ICM42607_INVALID_DATA) { return EC_ERROR_INVAL; } @@ -212,8 +211,8 @@ static int __maybe_unused icm42607_flush_fifo(const struct motion_sensor_t *s) } /* use FIFO threshold interrupt on INT1 */ -#define ICM42607_FIFO_INT_EN ICM42607_FIFO_THS_INT1_EN -#define ICM42607_FIFO_INT_STATUS ICM42607_FIFO_THS_INT +#define ICM42607_FIFO_INT_EN ICM42607_FIFO_THS_INT1_EN +#define ICM42607_FIFO_INT_STATUS ICM42607_FIFO_THS_INT static int __maybe_unused icm42607_enable_fifo(const struct motion_sensor_t *s, int enable) @@ -363,8 +362,8 @@ static int __maybe_unused icm42607_load_fifo(struct motion_sensor_t *s, return ret; for (i = 0; i < count; i += size) { - size = icm_fifo_decode_packet(&st->fifo_buffer[i], - &accel, &gyro); + size = icm_fifo_decode_packet(&st->fifo_buffer[i], &accel, + &gyro); /* exit if error or FIFO is empty */ if (size <= 0) return -size; @@ -464,7 +463,7 @@ static int icm42607_config_interrupt(const struct motion_sensor_t *s) return EC_SUCCESS; } -#endif /* ACCELGYRO_ICM42607_INT_ENABLE */ +#endif /* ACCELGYRO_ICM42607_INT_ENABLE */ static int icm42607_enable_sensor(const struct motion_sensor_t *s, int enable) { @@ -571,7 +570,7 @@ static int icm42607_set_data_rate(const struct motion_sensor_t *s, int rate, if (rate > 0) { if ((normalized_rate < min_rate) || - (normalized_rate > max_rate)) + (normalized_rate > max_rate)) return EC_RES_INVALID_PARAM; } @@ -612,8 +611,7 @@ out_unlock: return ret; } -static int icm42607_set_range(struct motion_sensor_t *s, int range, - int rnd) +static int icm42607_set_range(struct motion_sensor_t *s, int range, int rnd) { int reg, ret, reg_val; int newrange; @@ -1016,7 +1014,7 @@ static int icm42607_init_config(const struct motion_sensor_t *s) if (ret) return ret; - ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1, 0x02); + ret = icm_write8(s, ICM42607_REG_APEX_CONFIG1, 0x02); if (ret) return ret; -- cgit v1.2.1 From 75f12cde3caa1a55581ff02a8c024f0878ee517f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:10 -0600 Subject: zephyr/shim/chip/mchp/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id265b292936c7064c101dccedaa8b50225e8b0ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730815 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/chip/mchp/clock.c b/zephyr/shim/chip/mchp/clock.c index 3bdb6e4f99..9328627a4b 100644 --- a/zephyr/shim/chip/mchp/clock.c +++ b/zephyr/shim/chip/mchp/clock.c @@ -16,9 +16,9 @@ LOG_MODULE_REGISTER(shim_clock, LOG_LEVEL_ERR); -#define PCR_NODE DT_INST(0, microchip_xec_pcr) +#define PCR_NODE DT_INST(0, microchip_xec_pcr) #define HAL_PCR_REG_BASE_ADDR \ - ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) + ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(PCR_NODE, 0)) int clock_get_freq(void) { -- cgit v1.2.1 From da69577b71e40e6cab9d99b72b890933b4f52363 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:14 -0600 Subject: core/cortex-m0/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I21fecc12a52da1dff5ede70e1ed440c60ce18acc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729833 Reviewed-by: Jeremy Bettis --- core/cortex-m0/panic.c | 55 +++++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/core/cortex-m0/panic.c b/core/cortex-m0/panic.c index f1ee816c60..ce5a8b0b4d 100644 --- a/core/cortex-m0/panic.c +++ b/core/cortex-m0/panic.c @@ -19,9 +19,8 @@ /* Whether bus fault is ignored */ static int bus_fault_ignored; - /* Panic data goes at the end of RAM. */ -static struct panic_data * const pdata_ptr = PANIC_DATA_PTR; +static struct panic_data *const pdata_ptr = PANIC_DATA_PTR; /* Preceded by stack, rounded down to nearest 64-bit-aligned boundary */ static const uint32_t pstack_addr = ((uint32_t)pdata_ptr) & ~7; @@ -101,7 +100,7 @@ void panic_data_print(const struct panic_data *pdata) print_reg(12, sregs, CORTEX_PANIC_FRAME_REGISTER_R12); print_reg(13, lregs, in_handler ? CORTEX_PANIC_REGISTER_MSP : - CORTEX_PANIC_REGISTER_PSP); + CORTEX_PANIC_REGISTER_PSP); print_reg(14, sregs, CORTEX_PANIC_FRAME_REGISTER_LR); print_reg(15, sregs, CORTEX_PANIC_FRAME_REGISTER_PC); } @@ -126,10 +125,9 @@ void __keep report_panic(void) sp = is_frame_in_handler_stack( pdata->cm.regs[CORTEX_PANIC_REGISTER_LR]) ? pdata->cm.regs[CORTEX_PANIC_REGISTER_MSP] : - pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; + pdata->cm.regs[CORTEX_PANIC_REGISTER_PSP]; /* If stack is valid, copy exception frame to pdata */ - if ((sp & 3) == 0 && - sp >= CONFIG_RAM_BASE && + if ((sp & 3) == 0 && sp >= CONFIG_RAM_BASE && sp <= CONFIG_RAM_BASE + CONFIG_RAM_SIZE - 8 * sizeof(uint32_t)) { const uint32_t *sregs = (const uint32_t *)sp; int i; @@ -162,38 +160,41 @@ void exception_panic(void) "mov r5, lr\n" "stmia %[pregs]!, {r1-r5}\n" "mov sp, %[pstack]\n" - "bl report_panic\n" : : - [pregs] "r" (pdata_ptr->cm.regs), - [pstack] "r" (pstack_addr) : - /* Constraints protecting these from being clobbered. - * Gcc should be using r0 & r12 for pregs and pstack. */ - "r1", "r2", "r3", "r4", "r5", "r6", - /* clang warns that we're clobbering a reserved register: - * inline asm clobber list contains reserved registers: R7 - * [-Werror,-Winline-asm]. The intent of the clobber list is - * to force pregs and pstack to be in R0 and R12, which - * still holds. - */ + "bl report_panic\n" + : + : [pregs] "r"(pdata_ptr->cm.regs), [pstack] "r"(pstack_addr) + : + /* Constraints protecting these from being clobbered. + * Gcc should be using r0 & r12 for pregs and pstack. */ + "r1", "r2", "r3", "r4", "r5", "r6", + /* clang warns that we're clobbering a reserved register: + * inline asm clobber list contains reserved registers: R7 + * [-Werror,-Winline-asm]. The intent of the clobber list is + * to force pregs and pstack to be in R0 and R12, which + * still holds. + */ #ifndef __clang__ - "r7", + "r7", #endif - "r8", "r9", "r10", "r11", "cc", "memory" - ); + "r8", "r9", "r10", "r11", "cc", "memory"); } #ifdef CONFIG_SOFTWARE_PANIC void software_panic(uint32_t reason, uint32_t info) { - __asm__("mov " STRINGIFY(SOFTWARE_PANIC_INFO_REG) ", %0\n" - "mov " STRINGIFY(SOFTWARE_PANIC_REASON_REG) ", %1\n" - "bl exception_panic\n" - : : "r"(info), "r"(reason)); + __asm__("mov " STRINGIFY( + SOFTWARE_PANIC_INFO_REG) ", %0\n" + "mov " STRINGIFY( + SOFTWARE_PANIC_REASON_REG) ", %1\n" + "bl exception_panic\n" + : + : "r"(info), "r"(reason)); __builtin_unreachable(); } void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t *lregs; lregs = pdata->cm.regs; @@ -213,7 +214,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *lregs; if (pdata && pdata->struct_version == 2) { -- cgit v1.2.1 From bce9b85899834b0d36bbcb7830b81567754a074a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:15 -0600 Subject: include/motion_sense_fifo.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4d89f91529d1ee38c32d109ee518f7afa465cd69 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730370 Reviewed-by: Jeremy Bettis --- include/motion_sense_fifo.h | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/include/motion_sense_fifo.h b/include/motion_sense_fifo.h index 90d3f78879..5fdb602e39 100644 --- a/include/motion_sense_fifo.h +++ b/include/motion_sense_fifo.h @@ -12,8 +12,8 @@ enum motion_sense_async_event { ASYNC_EVENT_FLUSH = MOTIONSENSE_SENSOR_FLAG_FLUSH | MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, - ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR | - MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, + ASYNC_EVENT_ODR = MOTIONSENSE_SENSOR_FLAG_ODR | + MOTIONSENSE_SENSOR_FLAG_TIMESTAMP, }; /** @@ -48,9 +48,8 @@ void motion_sense_fifo_reset_needed_flags(void); * @param sensor The sensor that generated the async event. * @param event The event to insert. */ -void motion_sense_fifo_insert_async_event( - struct motion_sensor_t *sensor, - enum motion_sense_async_event event); +void motion_sense_fifo_insert_async_event(struct motion_sensor_t *sensor, + enum motion_sense_async_event event); /** * Insert a timestamp into the fifo. @@ -69,11 +68,9 @@ void motion_sense_fifo_add_timestamp(uint32_t timestamp); * @param time accurate time (ideally measured in an interrupt) the sample * was taken at */ -void motion_sense_fifo_stage_data( - struct ec_response_motion_sensor_data *data, - struct motion_sensor_t *sensor, - int valid_data, - uint32_t time); +void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data, + struct motion_sensor_t *sensor, + int valid_data, uint32_t time); /** * Commit all the currently staged data to the fifo. Doing so makes it readable @@ -89,8 +86,7 @@ void motion_sense_fifo_commit_data(void); * @param reset Whether or not to reset statistics after reading them. */ void motion_sense_fifo_get_info( - struct ec_response_motion_sense_fifo_info *fifo_info, - int reset); + struct ec_response_motion_sense_fifo_info *fifo_info, int reset); /** * Check whether or not the fifo has gone over its threshold. -- cgit v1.2.1 From 6ad48848e4208433e592a44fa1a23a13157afe86 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:01 -0600 Subject: chip/mt_scp/mt818x/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53a83ae981a96963d6ecef11f018a9da160d3c61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729349 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/registers.h | 1015 ++++++++++++++++++++-------------------- 1 file changed, 507 insertions(+), 508 deletions(-) diff --git a/chip/mt_scp/mt818x/registers.h b/chip/mt_scp/mt818x/registers.h index 36ac63ef12..706a8f7dca 100644 --- a/chip/mt_scp/mt818x/registers.h +++ b/chip/mt_scp/mt818x/registers.h @@ -12,90 +12,90 @@ #include "compile_time_macros.h" /* IRQ numbers */ -#define SCP_IRQ_IPC0 0 -#define SCP_IRQ_IPC1 1 -#define SCP_IRQ_IPC2 2 -#define SCP_IRQ_IPC3 3 -#define SCP_IRQ_SPM 4 -#define SCP_IRQ_CIRQ 5 -#define SCP_IRQ_EINT 6 -#define SCP_IRQ_PMIC 7 -#define SCP_IRQ_UART0 8 -#define SCP_IRQ_UART1 9 -#define SCP_IRQ_I2C0 10 -#define SCP_IRQ_I2C1 11 -#define SCP_IRQ_I2C2 12 -#define SCP_IRQ_CLOCK 13 -#define SCP_IRQ_MAD_FIFO 14 -#define SCP_IRQ_TIMER0 15 -#define SCP_IRQ_TIMER1 16 -#define SCP_IRQ_TIMER2 17 -#define SCP_IRQ_TIMER3 18 -#define SCP_IRQ_TIMER4 19 -#define SCP_IRQ_TIMER5 20 -#define SCP_IRQ_TIMER_STATUS 21 -#define SCP_IRQ_UART0_RX 22 -#define SCP_IRQ_UART1_RX 23 -#define SCP_IRQ_DMA 24 -#define SCP_IRQ_AUDIO 25 -#define SCP_IRQ_MD1_F216 26 -#define SCP_IRQ_MD1 27 -#define SCP_IRQ_C2K 28 -#define SCP_IRQ_SPI0 29 -#define SCP_IRQ_SPI1 30 -#define SCP_IRQ_SPI2 31 -#define SCP_IRQ_AP_EINT 32 -#define SCP_IRQ_DEBUG 33 -#define SCP_CCIF0 34 -#define SCP_CCIF1 35 -#define SCP_CCIF2 36 -#define SCP_IRQ_WDT 37 -#define SCP_IRQ_USB0 38 -#define SCP_IRQ_USB1 39 -#define SCP_IRQ_TWAM 40 -#define SCP_IRQ_INFRA 41 -#define SCP_IRQ_HWDVFS_HIGH 42 -#define SCP_IRQ_HWDVFS_LOW 43 -#define SCP_IRQ_CLOCK2 44 +#define SCP_IRQ_IPC0 0 +#define SCP_IRQ_IPC1 1 +#define SCP_IRQ_IPC2 2 +#define SCP_IRQ_IPC3 3 +#define SCP_IRQ_SPM 4 +#define SCP_IRQ_CIRQ 5 +#define SCP_IRQ_EINT 6 +#define SCP_IRQ_PMIC 7 +#define SCP_IRQ_UART0 8 +#define SCP_IRQ_UART1 9 +#define SCP_IRQ_I2C0 10 +#define SCP_IRQ_I2C1 11 +#define SCP_IRQ_I2C2 12 +#define SCP_IRQ_CLOCK 13 +#define SCP_IRQ_MAD_FIFO 14 +#define SCP_IRQ_TIMER0 15 +#define SCP_IRQ_TIMER1 16 +#define SCP_IRQ_TIMER2 17 +#define SCP_IRQ_TIMER3 18 +#define SCP_IRQ_TIMER4 19 +#define SCP_IRQ_TIMER5 20 +#define SCP_IRQ_TIMER_STATUS 21 +#define SCP_IRQ_UART0_RX 22 +#define SCP_IRQ_UART1_RX 23 +#define SCP_IRQ_DMA 24 +#define SCP_IRQ_AUDIO 25 +#define SCP_IRQ_MD1_F216 26 +#define SCP_IRQ_MD1 27 +#define SCP_IRQ_C2K 28 +#define SCP_IRQ_SPI0 29 +#define SCP_IRQ_SPI1 30 +#define SCP_IRQ_SPI2 31 +#define SCP_IRQ_AP_EINT 32 +#define SCP_IRQ_DEBUG 33 +#define SCP_CCIF0 34 +#define SCP_CCIF1 35 +#define SCP_CCIF2 36 +#define SCP_IRQ_WDT 37 +#define SCP_IRQ_USB0 38 +#define SCP_IRQ_USB1 39 +#define SCP_IRQ_TWAM 40 +#define SCP_IRQ_INFRA 41 +#define SCP_IRQ_HWDVFS_HIGH 42 +#define SCP_IRQ_HWDVFS_LOW 43 +#define SCP_IRQ_CLOCK2 44 /* RESERVED 45-52 */ -#define SCP_IRQ_AP_EINT2 53 -#define SCP_IRQ_AP_EINT_EVT 54 -#define SCP_IRQ_MAD_DATA 55 +#define SCP_IRQ_AP_EINT2 53 +#define SCP_IRQ_AP_EINT_EVT 54 +#define SCP_IRQ_MAD_DATA 55 -#define SCP_CFG_BASE 0x405C0000 +#define SCP_CFG_BASE 0x405C0000 -#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04) -#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08) +#define SCP_AP_RESOURCE REG32(SCP_CFG_BASE + 0x04) +#define SCP_BUS_RESOURCE REG32(SCP_CFG_BASE + 0x08) #ifdef CHIP_VARIANT_MT8186 -#define SCP_TCM_LOCK_CFG (CFGREG_BASE + 0x10) +#define SCP_TCM_LOCK_CFG (CFGREG_BASE + 0x10) #endif /* SCP to host interrupt */ -#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C) -#define IPC_SCP2HOST_SSHUB 0xff0000 -#define WDT_INT 0x100 -#define IPC_SCP2HOST 0xff -#define IPC_SCP2HOST_BIT 0x1 +#define SCP_HOST_INT REG32(SCP_CFG_BASE + 0x1C) +#define IPC_SCP2HOST_SSHUB 0xff0000 +#define WDT_INT 0x100 +#define IPC_SCP2HOST 0xff +#define IPC_SCP2HOST_BIT 0x1 /* SCP to SPM interrupt */ -#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) -#define SPM_INT_A2SPM BIT(0) -#define SPM_INT_B2SPM BIT(1) -#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) +#define SCP_SPM_INT REG32(SCP_CFG_BASE + 0x20) +#define SPM_INT_A2SPM BIT(0) +#define SPM_INT_B2SPM BIT(1) +#define SCP_SPM_INT2 REG32(SCP_CFG_BASE + 0x24) /* * AP side to SCP IPC * APMCU writes 1 bit to trigger ith IPC to SCP. * SCP writes 1 bit to ith bit to clear ith IPC. */ -#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28) - #define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n)) - #define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF -#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C) +#define SCP_GIPC_IN REG32(SCP_CFG_BASE + 0x28) +#define SCP_GIPC_IN_CLEAR_IPCN(n) (1 << (n)) +#define SCP_GPIC_IN_CLEAR_ALL 0x7FFFF +#define SCP_CONN_INT REG32(SCP_CFG_BASE + 0x2C) /* 8 general purpose registers, 0 ~ 7 */ -#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50) +#define SCP_GPR REG32_ADDR(SCP_CFG_BASE + 0x50) /* * SCP_GPR[0] * b15-b0 : scratchpad @@ -103,44 +103,44 @@ * SCP_GPR[1] * b15-b0 : power on state */ -#define SCP_PWRON_STATE SCP_GPR[1] -#define PWRON_DEFAULT 0xdee80000 -#define PWRON_WATCHDOG BIT(0) -#define PWRON_RESET BIT(1) +#define SCP_PWRON_STATE SCP_GPR[1] +#define PWRON_DEFAULT 0xdee80000 +#define PWRON_WATCHDOG BIT(0) +#define PWRON_RESET BIT(1) /* AP defined features */ -#define SCP_EXPECTED_FREQ SCP_GPR[3] -#define SCP_CURRENT_FREQ SCP_GPR[4] -#define SCP_REBOOT SCP_GPR[5] -#define READY_TO_REBOOT 0x34 -#define REBOOT_OK 1 +#define SCP_EXPECTED_FREQ SCP_GPR[3] +#define SCP_CURRENT_FREQ SCP_GPR[4] +#define SCP_REBOOT SCP_GPR[5] +#define READY_TO_REBOOT 0x34 +#define REBOOT_OK 1 /* Miscellaneous */ -#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90) -#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0) -#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4) -#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8) -#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC) -#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) -#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) -#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) -#define P_CACHE_SLP_PROT_EN BIT(3) -#define D_CACHE_SLP_PROT_EN BIT(4) -#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) -#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) +#define SCP_SEMAPHORE REG32(SCP_CFG_BASE + 0x90) +#define CORE_CONTROL REG32(SCP_CFG_BASE + 0xA0) +#define CORE_FPU_FLAGS REG32(SCP_CFG_BASE + 0xA4) +#define CORE_REG_SP REG32(SCP_CFG_BASE + 0xA8) +#define CORE_REG_LR REG32(SCP_CFG_BASE + 0xAC) +#define CORE_REG_PSP REG32(SCP_CFG_BASE + 0xB0) +#define CORE_REG_PC REG32(SCP_CFG_BASE + 0xB4) +#define SCP_SLP_PROTECT_CFG REG32(SCP_CFG_BASE + 0xC8) +#define P_CACHE_SLP_PROT_EN BIT(3) +#define D_CACHE_SLP_PROT_EN BIT(4) +#define SCP_ONE_TIME_LOCK REG32(SCP_CFG_BASE + 0xDC) +#define SCP_SECURE_CTRL REG32(SCP_CFG_BASE + 0xE0) #ifdef CHIP_VARIANT_MT8186 -#define JTAG_DBG_REQ_BIT BIT(3) -#define DISABLE_REMAP BIT(31) +#define JTAG_DBG_REQ_BIT BIT(3) +#define DISABLE_REMAP BIT(31) #else -#define DISABLE_REMAP BIT(22) +#define DISABLE_REMAP BIT(22) #endif -#define ENABLE_SPM_MASK_VREQ BIT(28) -#define DISABLE_JTAG BIT(21) -#define DISABLE_AP_TCM BIT(20) -#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) -#define DDREN_FIX_VALUE BIT(28) -#define AUTO_DDREN BIT(18) +#define ENABLE_SPM_MASK_VREQ BIT(28) +#define DISABLE_JTAG BIT(21) +#define DISABLE_AP_TCM BIT(20) +#define SCP_SYS_CTRL REG32(SCP_CFG_BASE + 0xE4) +#define DDREN_FIX_VALUE BIT(28) +#define AUTO_DDREN BIT(18) /* Memory remap control */ /* @@ -149,515 +149,514 @@ * EXT_ADDR1[13:8] remap register for addr msb 31~28 equal to 0x3 * EXT_ADDR0[5:0] remap register for addr msb 31~28 equal to 0x2 */ -#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120) +#define SCP_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x120) /* * EXT_ADDR7[29:24] remap register for addr msb 31~28 equal to 0xb * EXT_ADDR6[21:16] remap register for addr msb 31~28 equal to 0xa * EXT_ADDR5[13:8] remap register for addr msb 31~28 equal to 0x9 * EXT_ADDR4[5:0] remap register for addr msb 31~28 equal to 0x8 */ -#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124) +#define SCP_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x124) /* * AUD_ADDR[31:28] remap register for addr msb 31~28 equal to 0xd * EXT_ADDR10[21:16]remap register for addr msb 31~28 equal to 0xf * EXT_ADDR9[13:8] remap register for addr msb 31~28 equal to 0xe * EXT_ADDR8[5:0] remap register for addr msb 31~28 equal to 0xc */ -#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128) +#define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128) -#define SCP_REMAP_ADDR_SHIFT 28 -#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) +#define SCP_REMAP_ADDR_SHIFT 28 +#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) +#define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) /* Cached memory remap control */ -#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C) +#define SCP_L1_REMAP_CFG0 REG32(SCP_CFG_BASE + 0x12C) /* * L1C_EXT_ADDR1[29:16] remap register for addr msb 31~20 equal to 0x401 * L1C_EXT_ADDR0[13:0] remap register for addr msb 31~20 equal to 0x400 */ -#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130) +#define SCP_L1_REMAP_CFG1 REG32(SCP_CFG_BASE + 0x130) /* * L1C_EXT_ADDR3[29:16] remap register for addr msb 31~20 equal to 0x403 * L1C_EXT_ADDR2[13:0] remap register for addr msb 31~20 equal to 0x402 */ -#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134) +#define SCP_L1_REMAP_CFG2 REG32(SCP_CFG_BASE + 0x134) /* * L1C_EXT_ADDR5[29:16] remap register for addr msb 31~20 equal to 0x405 * L1C_EXT_ADDR4[13:0] remap register for addr msb 31~20 equal to 0x404 */ -#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138) +#define SCP_L1_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x138) /* * L1C_EXT_ADDR_OTHER1[13:8] Remap register for addr msb 31 to 28 equal to 0x1 * L1C_EXT_ADDR_OTHER0[5:0] Remap register for addr msb 31 to 28 equal to 0x0 * and not overlap with L1C_EXT_ADDR0 to L1C_EXT_ADDR7 */ -#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C) +#define SCP_L1_REMAP_OTHER REG32(SCP_CFG_BASE + 0x13C) -#define SCP_L1_EXT_ADDR_SHIFT 20 -#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28 -#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) -#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) +#define SCP_L1_EXT_ADDR_SHIFT 20 +#define SCP_L1_EXT_ADDR_OTHER_SHIFT 28 +#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) +#define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) /* Audio/voice FIFO */ -#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000) -#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE) -#define VIF_FIFO_RSTN (1 << 0) -#define VIF_FIFO_IRQ_EN (1 << 1) -#define VIF_FIFO_SRAM_PWR (1 << 2) -#define VIF_FIFO_RSTN_STATUS (1 << 4) -#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04) -#define VIF_FIFO_VALID (1 << 0) -#define VIF_FIFO_FULL (1 << 4) -#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff) -#define VIF_FIFO_MAX 256 -#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08) -#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C) +#define SCP_AUDIO_BASE (SCP_CFG_BASE + 0x1000) +#define SCP_VIF_FIFO_EN REG32(SCP_AUDIO_BASE) +#define VIF_FIFO_RSTN (1 << 0) +#define VIF_FIFO_IRQ_EN (1 << 1) +#define VIF_FIFO_SRAM_PWR (1 << 2) +#define VIF_FIFO_RSTN_STATUS (1 << 4) +#define SCP_VIF_FIFO_STATUS REG32(SCP_AUDIO_BASE + 0x04) +#define VIF_FIFO_VALID (1 << 0) +#define VIF_FIFO_FULL (1 << 4) +#define VIF_FIFO_LEVEL(status) (((status) >> 16) & 0xff) +#define VIF_FIFO_MAX 256 +#define SCP_VIF_FIFO_DATA REG32(SCP_AUDIO_BASE + 0x08) +#define SCP_VIF_FIFO_DATA_THRE REG32(SCP_AUDIO_BASE + 0x0C) /* VIF IRQ status clears on read! */ -#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10) +#define SCP_VIF_FIFO_IRQ_STATUS REG32(SCP_AUDIO_BASE + 0x10) /* Audio/voice serial interface */ -#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14) -#define RXIF_CFG0_RESET_VAL 0x2A130001 -#define RXIF_AFE_ON (1 << 0) -#define RXIF_SCKINV (1 << 1) -#define RXIF_RG_DL_2_IN_MODE(mode) (((mode) & 0xf) << 8) -#define RXIF_RGDL2_AMIC_16K (0x1 << 8) -#define RXIF_RGDL2_DMIC_16K (0x2 << 8) -#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8) -#define RXIF_RGDL2_AMIC_32K (0x5 << 8) -#define RXIF_RGDL2_MASK (0xf << 8) -#define RXIF_UP8X_RSP(p) (((p) & 0x7) << 16) -#define RXIF_RG_RX_READEN (1 << 19) -#define RXIF_MONO (1 << 20) -#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt) & 0xff) << 24) -#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18) -#define RXIF_CFG1_RESET_VAL 0x33180014 -#define RXIF_RG_SYNC_CNT_TBL(t) ((t) & 0x1ff) -#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t) & 0x1f) << 16) -#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r) & 0xf) << 24) -#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r) & 0xf) << 28) -#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C) -#define RXIF_SYNC_WORD(w) ((w) & 0xffff) -#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20) -#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24) -#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28) +#define SCP_RXIF_CFG0 REG32(SCP_AUDIO_BASE + 0x14) +#define RXIF_CFG0_RESET_VAL 0x2A130001 +#define RXIF_AFE_ON (1 << 0) +#define RXIF_SCKINV (1 << 1) +#define RXIF_RG_DL_2_IN_MODE(mode) (((mode)&0xf) << 8) +#define RXIF_RGDL2_AMIC_16K (0x1 << 8) +#define RXIF_RGDL2_DMIC_16K (0x2 << 8) +#define RXIF_RGDL2_DMIC_LP_16K (0x3 << 8) +#define RXIF_RGDL2_AMIC_32K (0x5 << 8) +#define RXIF_RGDL2_MASK (0xf << 8) +#define RXIF_UP8X_RSP(p) (((p)&0x7) << 16) +#define RXIF_RG_RX_READEN (1 << 19) +#define RXIF_MONO (1 << 20) +#define RXIF_RG_CLK_A16P7K_EN(cnt) (((cnt)&0xff) << 24) +#define SCP_RXIF_CFG1 REG32(SCP_AUDIO_BASE + 0x18) +#define RXIF_CFG1_RESET_VAL 0x33180014 +#define RXIF_RG_SYNC_CNT_TBL(t) ((t)&0x1ff) +#define RXIF_RG_SYNC_SEARCH_TBL(t) (((t)&0x1f) << 16) +#define RXIF_RG_SYNC_CHECK_ROUND(r) (((r)&0xf) << 24) +#define RXIF_RG_INSYNC_CHECK_ROUND(r) (((r)&0xf) << 28) +#define SCP_RXIF_CFG2 REG32(SCP_AUDIO_BASE + 0x1C) +#define RXIF_SYNC_WORD(w) ((w)&0xffff) +#define SCP_RXIF_OUT REG32(SCP_AUDIO_BASE + 0x20) +#define SCP_RXIF_STATUS REG32(SCP_AUDIO_BASE + 0x24) +#define SCP_RXIF_IRQ_EN REG32(SCP_AUDIO_BASE + 0x28) /* INTC control */ -#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) -#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) -#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) -#define IPC0_IRQ_EN BIT(0) -#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) -#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) -#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) -#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14) -#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18) -#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C) -#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80) -#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84) -#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88) -#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C) +#define SCP_INTC_BASE (SCP_CFG_BASE + 0x2000) +#define SCP_INTC_IRQ_STATUS REG32(SCP_INTC_BASE) +#define SCP_INTC_IRQ_ENABLE REG32(SCP_INTC_BASE + 0x04) +#define IPC0_IRQ_EN BIT(0) +#define SCP_INTC_IRQ_OUTPUT REG32(SCP_INTC_BASE + 0x08) +#define SCP_INTC_IRQ_WAKEUP REG32(SCP_INTC_BASE + 0x0C) +#define SCP_INTC_NMI REG32(SCP_INTC_BASE + 0x10) +#define SCP_INTC_SPM_WAKEUP REG32(SCP_INTC_BASE + 0x14) +#define SCP_INTC_SPM_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x18) +#define SCP_INTC_UART_RX_IRQ REG32(SCP_INTC_BASE + 0x1C) +#define SCP_INTC_IRQ_STATUS_MSB REG32(SCP_INTC_BASE + 0x80) +#define SCP_INTC_IRQ_ENABLE_MSB REG32(SCP_INTC_BASE + 0x84) +#define SCP_INTC_IRQ_OUTPUT_MSB REG32(SCP_INTC_BASE + 0x88) +#define SCP_INTC_IRQ_WAKEUP_MSB REG32(SCP_INTC_BASE + 0x8C) /* Timer */ -#define NUM_TIMERS 6 -#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n))) -#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n)) -#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) -#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) -#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) -#define TIMER_IRQ_ENABLE BIT(0) -#define TIMER_IRQ_STATUS BIT(4) -#define TIMER_IRQ_CLEAR BIT(5) -#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) -#define TIMER_CLK_32K (0 << 4) -#define TIMER_CLK_26M BIT(4) -#define TIMER_CLK_BCLK (2 << 4) -#define TIMER_CLK_PCLK (3 << 4) -#define TIMER_CLK_MASK (3 << 4) +#define NUM_TIMERS 6 +#define SCP_TIMER_BASE(n) (SCP_CFG_BASE + 0x3000 + (0x10 * (n))) +#define SCP_TIMER_EN(n) REG32(SCP_TIMER_BASE(n)) +#define SCP_TIMER_RESET_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x04) +#define SCP_TIMER_VAL(n) REG32(SCP_TIMER_BASE(n) + 0x08) +#define SCP_TIMER_IRQ_CTRL(n) REG32(SCP_TIMER_BASE(n) + 0x0C) +#define TIMER_IRQ_ENABLE BIT(0) +#define TIMER_IRQ_STATUS BIT(4) +#define TIMER_IRQ_CLEAR BIT(5) +#define SCP_TIMER_CLK_SEL(n) REG32(SCP_TIMER_BASE(n) + 0x40) +#define TIMER_CLK_32K (0 << 4) +#define TIMER_CLK_26M BIT(4) +#define TIMER_CLK_BCLK (2 << 4) +#define TIMER_CLK_PCLK (3 << 4) +#define TIMER_CLK_MASK (3 << 4) /* OS timer */ -#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080) -#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE) -#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04) -#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08) -#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C) -#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) -#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) -#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) -#define OSTIMER_LATCH0_EN BIT(5) -#define OSTIMER_LATCH1_EN BIT(13) -#define OSTIMER_LATCH2_EN BIT(21) -#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) -#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) -#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) -#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C) -#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30) -#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34) -#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38) +#define SCP_OSTIMER_BASE (SCP_CFG_BASE + 0x3080) +#define SCP_OSTIMER_CON REG32(SCP_OSTIMER_BASE) +#define SCP_OSTIMER_INIT_L REG32(SCP_OSTIMER_BASE + 0x04) +#define SCP_OSTIMER_INIT_H REG32(SCP_OSTIMER_BASE + 0x08) +#define SCP_OSTIMER_VAL_L REG32(SCP_OSTIMER_BASE + 0x0C) +#define SCP_OSTIMER_VAL_H REG32(SCP_OSTIMER_BASE + 0x10) +#define SCP_OSTIMER_TVAL REG32(SCP_OSTIMER_BASE + 0x14) +#define SCP_OSTIMER_IRQ_ACK REG32(SCP_OSTIMER_BASE + 0x18) +#define OSTIMER_LATCH0_EN BIT(5) +#define OSTIMER_LATCH1_EN BIT(13) +#define OSTIMER_LATCH2_EN BIT(21) +#define SCP_OSTIMER_LATCH_CTRL REG32(SCP_OSTIMER_BASE + 0x20) +#define SCP_OSTIMER_LATCH0_L REG32(SCP_OSTIMER_BASE + 0x24) +#define SCP_OSTIMER_LATCH0_H REG32(SCP_OSTIMER_BASE + 0x28) +#define SCP_OSTIMER_LATCH1_L REG32(SCP_OSTIMER_BASE + 0x2C) +#define SCP_OSTIMER_LATCH1_H REG32(SCP_OSTIMER_BASE + 0x30) +#define SCP_OSTIMER_LATCH2_L REG32(SCP_OSTIMER_BASE + 0x34) +#define SCP_OSTIMER_LATCH2_H REG32(SCP_OSTIMER_BASE + 0x38) /* Clock, PMIC wrapper, etc. */ -#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000) -#define SCP_CLK_SEL REG32(SCP_CLK_BASE) -#define CLK_SEL_SYS_26M 0 -#define CLK_SEL_32K 1 -#define CLK_SEL_ULPOSC_2 2 -#define CLK_SEL_ULPOSC_1 3 - -#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) -#define EN_CLK_SYS BIT(0) /* System clock */ -#define EN_CLK_HIGH BIT(1) /* ULPOSC */ -#define CG_CLK_HIGH BIT(2) -#define EN_SYS_IRQ BIT(16) -#define EN_HIGH_IRQ BIT(17) -#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) -#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) -#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) +#define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000) +#define SCP_CLK_SEL REG32(SCP_CLK_BASE) +#define CLK_SEL_SYS_26M 0 +#define CLK_SEL_32K 1 +#define CLK_SEL_ULPOSC_2 2 +#define CLK_SEL_ULPOSC_1 3 + +#define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) +#define EN_CLK_SYS BIT(0) /* System clock */ +#define EN_CLK_HIGH BIT(1) /* ULPOSC */ +#define CG_CLK_HIGH BIT(2) +#define EN_SYS_IRQ BIT(16) +#define EN_HIGH_IRQ BIT(17) +#define SCP_CLK_SAFE_ACK REG32(SCP_CLK_BASE + 0x08) +#define SCP_CLK_ACK REG32(SCP_CLK_BASE + 0x0C) +#define SCP_CLK_IRQ_ACK REG32(SCP_CLK_BASE + 0x10) /* * System clock counter value. * CLK_SYS_VAL[9:0] System clock counter initial/reset value. */ -#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14) -#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_SYS_VAL(n) ((n) & CLK_SYS_VAL_MASK) +#define SCP_CLK_SYS_VAL REG32(SCP_CLK_BASE + 0x14) +#define CLK_SYS_VAL_MASK 0x3ff /* 10 bits */ +#define CLK_SYS_VAL(n) ((n)&CLK_SYS_VAL_MASK) /* * ULPOSC clock counter value. * CLK_HIGH_VAL[9:0] ULPOSC clock counter initial/reset value. */ -#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18) -#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */ -#define CLK_HIGH_VAL(n) ((n) & CLK_HIGH_VAL_MASK) -#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C) -#define CKSW_SEL_SLOW_MASK 0x3 -#define CKSW_SEL_SLOW_DIV_MASK 0x30 -#define CKSW_SEL_SLOW_SYS_CLK 0 -#define CKSW_SEL_SLOW_32K_CLK 1 -#define CKSW_SEL_SLOW_ULPOSC2_CLK 2 -#define CKSW_SEL_SLOW_ULPOSC1_CLK 3 +#define SCP_CLK_HIGH_VAL REG32(SCP_CLK_BASE + 0x18) +#define CLK_HIGH_VAL_MASK 0x3ff /* 10 bits */ +#define CLK_HIGH_VAL(n) ((n)&CLK_HIGH_VAL_MASK) +#define SCP_CLK_SLOW_SEL REG32(SCP_CLK_BASE + 0x1C) +#define CKSW_SEL_SLOW_MASK 0x3 +#define CKSW_SEL_SLOW_DIV_MASK 0x30 +#define CKSW_SEL_SLOW_SYS_CLK 0 +#define CKSW_SEL_SLOW_32K_CLK 1 +#define CKSW_SEL_SLOW_ULPOSC2_CLK 2 +#define CKSW_SEL_SLOW_ULPOSC1_CLK 3 /* * Sleep mode control. * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the * voltage after returning from sleep mode. */ -#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) -#define EN_SLEEP_CTRL BIT(0) +#define SCP_CLK_SLEEP_CTRL REG32(SCP_CLK_BASE + 0x20) +#define EN_SLEEP_CTRL BIT(0) #ifdef CHIP_VARIANT_MT8186 -#define VREQ_COUNTER_MASK 0x7F +#define VREQ_COUNTER_MASK 0x7F #else -#define VREQ_COUNTER_MASK 0xfe +#define VREQ_COUNTER_MASK 0xfe #endif -#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) -#define SPM_SLEEP_MODE BIT(8) -#define SPM_SLEEP_MODE_CLK_AO BIT(9) -#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) -#define CLK_DIV1 0 -#define CLK_DIV2 1 -#define CLK_DIV4 2 -#define CLK_DIV8 3 -#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) -#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) -#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) -#define CG_TIMER_M BIT(0) -#define CG_TIMER_B BIT(1) -#define CG_MAD_M BIT(2) -#define CG_I2C_M BIT(3) -#define CG_I2C_B BIT(4) -#define CG_GPIO_M BIT(5) -#define CG_AP2P_M BIT(6) -#define CG_UART_M BIT(7) -#define CG_UART_B BIT(8) -#define CG_UART_RSTN BIT(9) -#define CG_UART1_M BIT(10) -#define CG_UART1_B BIT(11) -#define CG_UART1_RSTN BIT(12) -#define CG_SPI0 BIT(13) -#define CG_SPI1 BIT(14) -#define CG_SPI2 BIT(15) -#define CG_DMA_CH0 BIT(16) -#define CG_DMA_CH1 BIT(17) -#define CG_DMA_CH2 BIT(18) -#define CG_DMA_CH3 BIT(19) -#define CG_TWAM BIT(20) -#define CG_CACHE_I_CTRL BIT(21) -#define CG_CACHE_D_CTRL BIT(22) -#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) -#define PMICW_SLEEP_REQ BIT(0) -#define PMICW_SLEEP_ACK BIT(4) -#define PMICW_CLK_MUX BIT(8) -#define PMICW_DCM BIT(9) -#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) -#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) -#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) +#define VREQ_COUNTER_VAL(v) (((v) << 1) & VREQ_COUNTER_MASK) +#define SPM_SLEEP_MODE BIT(8) +#define SPM_SLEEP_MODE_CLK_AO BIT(9) +#define SCP_CLK_DIV_SEL REG32(SCP_CLK_BASE + 0x24) +#define CLK_DIV1 0 +#define CLK_DIV2 1 +#define CLK_DIV4 2 +#define CLK_DIV8 3 +#define SCP_CLK_DEBUG REG32(SCP_CLK_BASE + 0x28) +#define SCP_CLK_SRAM_POWERDOWN REG32(SCP_CLK_BASE + 0x2C) +#define SCP_CLK_GATE REG32(SCP_CLK_BASE + 0x30) +#define CG_TIMER_M BIT(0) +#define CG_TIMER_B BIT(1) +#define CG_MAD_M BIT(2) +#define CG_I2C_M BIT(3) +#define CG_I2C_B BIT(4) +#define CG_GPIO_M BIT(5) +#define CG_AP2P_M BIT(6) +#define CG_UART_M BIT(7) +#define CG_UART_B BIT(8) +#define CG_UART_RSTN BIT(9) +#define CG_UART1_M BIT(10) +#define CG_UART1_B BIT(11) +#define CG_UART1_RSTN BIT(12) +#define CG_SPI0 BIT(13) +#define CG_SPI1 BIT(14) +#define CG_SPI2 BIT(15) +#define CG_DMA_CH0 BIT(16) +#define CG_DMA_CH1 BIT(17) +#define CG_DMA_CH2 BIT(18) +#define CG_DMA_CH3 BIT(19) +#define CG_TWAM BIT(20) +#define CG_CACHE_I_CTRL BIT(21) +#define CG_CACHE_D_CTRL BIT(22) +#define SCP_PMICW_CTRL REG32(SCP_CLK_BASE + 0x34) +#define PMICW_SLEEP_REQ BIT(0) +#define PMICW_SLEEP_ACK BIT(4) +#define PMICW_CLK_MUX BIT(8) +#define PMICW_DCM BIT(9) +#define SCP_SLEEP_WAKE_DEBUG REG32(SCP_CLK_BASE + 0x38) +#define SCP_DCM_EN REG32(SCP_CLK_BASE + 0x3C) +#define SCP_WAKE_CKSW REG32(SCP_CLK_BASE + 0x40) #ifdef CHIP_VARIANT_MT8186 -#define WAKE_CKSW_SEL_NORMAL_BIT 0 -#define WAKE_CKSW_SEL_SLOW_BIT 4 -#define WAKE_CKSW_SEL_SLOW_MASK 0x3 +#define WAKE_CKSW_SEL_NORMAL_BIT 0 +#define WAKE_CKSW_SEL_SLOW_BIT 4 +#define WAKE_CKSW_SEL_SLOW_MASK 0x3 #else -#define WAKE_CKSW_SEL_SLOW_MASK 0x30 -#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10 +#define WAKE_CKSW_SEL_SLOW_MASK 0x30 +#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10 #endif -#define WAKE_CKSW_SEL_NORMAL_MASK 0x3 -#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44) -#define CLK_UART_SEL_MASK 0x3 -#define CLK_UART_SEL_26M 0x0 -#define CLK_UART_SEL_32K 0x1 +#define WAKE_CKSW_SEL_NORMAL_MASK 0x3 +#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44) +#define CLK_UART_SEL_MASK 0x3 +#define CLK_UART_SEL_26M 0x0 +#define CLK_UART_SEL_32K 0x1 /* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART_SEL_ULPOSC1_DIV10 0x2 -#define CLK_UART1_SEL_MASK (0x3 << 16) -#define CLK_UART1_SEL_26M (0x0 << 16) -#define CLK_UART1_SEL_32K (0x1 << 16) +#define CLK_UART_SEL_ULPOSC1_DIV10 0x2 +#define CLK_UART1_SEL_MASK (0x3 << 16) +#define CLK_UART1_SEL_26M (0x0 << 16) +#define CLK_UART1_SEL_32K (0x1 << 16) /* This is named ulposc_div_to_26m in datasheet */ -#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16) -#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48) -#define CLK_BCLK_SEL_MASK 0x3 -#define CLK_BCLK_SEL_SYS_DIV8 0x0 -#define CLK_BCLK_SEL_32K 0x1 -#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2 -#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C) -#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50) -#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54) -#define CPU_VREQ_HW_MODE 0x10001 +#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16) +#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48) +#define CLK_BCLK_SEL_MASK 0x3 +#define CLK_BCLK_SEL_SYS_DIV8 0x0 +#define CLK_BCLK_SEL_32K 0x1 +#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2 +#define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C) +#define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50) +#define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54) +#define CPU_VREQ_HW_MODE 0x10001 #ifdef CHIP_VARIANT_MT8186 -#define VREQ_SEL BIT(0) -#define VREQ_PMIC_WRAP_SEL BIT(1) -#define VREQ_VALUE BIT(4) -#define VREQ_EXT_SEL BIT(8) -#define VREQ_DVFS_SEL BIT(16) -#define VREQ_DVFS_VALUE BIT(20) -#define VREQ_DVFS_EXT_SEL BIT(24) -#define VREQ_SRCLKEN_SEL BIT(27) -#define VREQ_SRCLKEN_VALUE BIT(28) +#define VREQ_SEL BIT(0) +#define VREQ_PMIC_WRAP_SEL BIT(1) +#define VREQ_VALUE BIT(4) +#define VREQ_EXT_SEL BIT(8) +#define VREQ_DVFS_SEL BIT(16) +#define VREQ_DVFS_VALUE BIT(20) +#define VREQ_DVFS_EXT_SEL BIT(24) +#define VREQ_SRCLKEN_SEL BIT(27) +#define VREQ_SRCLKEN_VALUE BIT(28) #endif -#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58) -#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C) -#define CLK_HIGH_CORE_CG (1 << 1) -#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) -#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) -#define HIGH_AO BIT(0) -#define HIGH_CG_AO BIT(2) -#define HIGH_CORE_AO BIT(4) -#define HIGH_CORE_DIS_SUB BIT(5) -#define HIGH_CORE_CG_AO BIT(6) -#define HIGH_FINAL_VAL_MASK 0x1f00 -#define HIGH_FINAL_VAL_DEFAULT 0x300 -#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) -#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94) +#define SCP_CLK_CLEAR REG32(SCP_CLK_BASE + 0x58) +#define SCP_CLK_HIGH_CORE REG32(SCP_CLK_BASE + 0x5C) +#define CLK_HIGH_CORE_CG (1 << 1) +#define SCP_SLEEP_IRQ2 REG32(SCP_CLK_BASE + 0x64) +#define SCP_CLK_ON_CTRL REG32(SCP_CLK_BASE + 0x6C) +#define HIGH_AO BIT(0) +#define HIGH_CG_AO BIT(2) +#define HIGH_CORE_AO BIT(4) +#define HIGH_CORE_DIS_SUB BIT(5) +#define HIGH_CORE_CG_AO BIT(6) +#define HIGH_FINAL_VAL_MASK 0x1f00 +#define HIGH_FINAL_VAL_DEFAULT 0x300 +#define SCP_CLK_L1_SRAM_PD REG32(SCP_CLK_BASE + 0x80) +#define SCP_CLK_TCM_TAIL_SRAM_PD REG32(SCP_CLK_BASE + 0x94) #ifdef CHIP_VARIANT_MT8186 -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_BASE + 0x9C) +#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_BASE + 0x9C) #endif -#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0) -#define SLOW_WAKE_DISABLE 1 -#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4) -#define FAST_WAKE_CNT_END_MASK 0xfff -#define FAST_WAKE_CNT_END_DEFAULT 0x18 -#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000 +#define SCP_CLK_SLEEP REG32(SCP_CLK_BASE + 0xA0) +#define SLOW_WAKE_DISABLE 1 +#define SCP_FAST_WAKE_CNT_END REG32(SCP_CLK_BASE + 0xA4) +#define FAST_WAKE_CNT_END_MASK 0xfff +#define FAST_WAKE_CNT_END_DEFAULT 0x18 +#define MEM_CK_CS_ISO_CNT_END_MASK 0x7f0000 /* Peripherals */ -#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000) -#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000) -#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000) +#define SCP_I2C0_BASE (SCP_CFG_BASE + 0x5000) +#define SCP_I2C1_BASE (SCP_CFG_BASE + 0x6000) +#define SCP_I2C2_BASE (SCP_CFG_BASE + 0x7000) -#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000) -#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000) -#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000) -#define SCP_UART_COUNT 2 +#define SCP_GPIO_BASE (SCP_CFG_BASE + 0x8000) +#define SCP_UART0_BASE (SCP_CFG_BASE + 0x9000) +#define SCP_UART1_BASE (SCP_CFG_BASE + 0xE000) +#define SCP_UART_COUNT 2 /* External GPIO interrupt */ -#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000) -#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE) -#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040) -#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080) -#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0) -#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100) -#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140) -#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180) -#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0) -#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200) -#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240) -#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280) -#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300) -#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340) -#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380) -#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400) -#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420) -#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500) -#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600) -#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700) - -#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000) -#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200) -#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204) -#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208) -#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000) -#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000) -#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20) -#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000) -#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000) -#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000) +#define SCP_EINT_BASE (SCP_CFG_BASE + 0xA000) +#define SCP_EINT_STATUS REG32_ADDR(SCP_EINT_BASE) +#define SCP_EINT_ACK REG32_ADDR(SCP_EINT_BASE + 0x040) +#define SCP_EINT_MASK_GET REG32_ADDR(SCP_EINT_BASE + 0x080) +#define SCP_EINT_MASK_SET REG32_ADDR(SCP_EINT_BASE + 0x0C0) +#define SCP_EINT_MASK_CLR REG32_ADDR(SCP_EINT_BASE + 0x100) +#define SCP_EINT_SENS_GET REG32_ADDR(SCP_EINT_BASE + 0x140) +#define SCP_EINT_SENS_SET REG32_ADDR(SCP_EINT_BASE + 0x180) +#define SCP_EINT_SENS_CLR REG32_ADDR(SCP_EINT_BASE + 0x1C0) +#define SCP_EINT_SOFT_GET REG32_ADDR(SCP_EINT_BASE + 0x200) +#define SCP_EINT_SOFT_SET REG32_ADDR(SCP_EINT_BASE + 0x240) +#define SCP_EINT_SOFT_CLR REG32_ADDR(SCP_EINT_BASE + 0x280) +#define SCP_EINT_POLARITY_GET REG32_ADDR(SCP_EINT_BASE + 0x300) +#define SCP_EINT_POLARITY_SET REG32_ADDR(SCP_EINT_BASE + 0x340) +#define SCP_EINT_POLARITY_CLR REG32_ADDR(SCP_EINT_BASE + 0x380) +#define SCP_EINT_D0_EN REG32_ADDR(SCP_EINT_BASE + 0x400) +#define SCP_EINT_D1_EN REG32_ADDR(SCP_EINT_BASE + 0x420) +#define SCP_EINT_DBNC_GET REG32_ADDR(SCP_EINT_BASE + 0x500) +#define SCP_EINT_DBNC_SET REG32_ADDR(SCP_EINT_BASE + 0x600) +#define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700) + +#define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000) +#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200) +#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204) +#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208) +#define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000) +#define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000) +#define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20) +#define SCP_SPI0_BASE (SCP_CFG_BASE + 0xF000) +#define SCP_SPI1_BASE (SCP_CFG_BASE + 0x10000) +#define SCP_SPI2_BASE (SCP_CFG_BASE + 0x11000) #define CACHE_ICACHE 0 #define CACHE_DCACHE 1 #define CACHE_COUNT 2 -#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) -#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) -#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) -#define SCP_CACHE_CON_MCEN BIT(0) -#define SCP_CACHE_CON_CNTEN0 BIT(2) -#define SCP_CACHE_CON_CNTEN1 BIT(3) -#define SCP_CACHE_CON_CACHESIZE_SHIFT 8 -#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) -#define SCP_CACHE_CON_WAYEN BIT(10) - -#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) -#define SCP_CACHE_OP_EN BIT(0) -#define SCP_CACHE_OP_OP_SHIFT 1 -#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) - -#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT) -#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT) -#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT) - -#define SCP_CACHE_OP_TADDR_SHIFT 5 -#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT) -#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT) +#define SCP_CACHE_BASE (SCP_CFG_BASE + 0x14000) +#define SCP_CACHE_SEL(x) (SCP_CACHE_BASE + (x)*0x3000) +#define SCP_CACHE_CON(x) REG32(SCP_CACHE_SEL(x)) +#define SCP_CACHE_CON_MCEN BIT(0) +#define SCP_CACHE_CON_CNTEN0 BIT(2) +#define SCP_CACHE_CON_CNTEN1 BIT(3) +#define SCP_CACHE_CON_CACHESIZE_SHIFT 8 +#define SCP_CACHE_CON_CACHESIZE_MASK (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) +#define SCP_CACHE_CON_CACHESIZE_0KB (0x0 << SCP_CACHE_CON_CACHESIZE_SHIFT) +#define SCP_CACHE_CON_CACHESIZE_8KB (0x1 << SCP_CACHE_CON_CACHESIZE_SHIFT) +#define SCP_CACHE_CON_CACHESIZE_16KB (0x2 << SCP_CACHE_CON_CACHESIZE_SHIFT) +#define SCP_CACHE_CON_CACHESIZE_32KB (0x3 << SCP_CACHE_CON_CACHESIZE_SHIFT) +#define SCP_CACHE_CON_WAYEN BIT(10) + +#define SCP_CACHE_OP(x) REG32(SCP_CACHE_SEL(x) + 0x04) +#define SCP_CACHE_OP_EN BIT(0) +#define SCP_CACHE_OP_OP_SHIFT 1 +#define SCP_CACHE_OP_OP_MASK (0xf << SCP_CACHE_OP_OP_SHIFT) + +#define OP_INVALIDATE_ALL_LINES (0x1 << SCP_CACHE_OP_OP_SHIFT) +#define OP_INVALIDATE_ONE_LINE_BY_ADDRESS (0x2 << SCP_CACHE_OP_OP_SHIFT) +#define OP_INVALIDATE_ONE_LINE_BY_SET_WAY (0x4 << SCP_CACHE_OP_OP_SHIFT) +#define OP_CACHE_FLUSH_ALL_LINES (0x9 << SCP_CACHE_OP_OP_SHIFT) +#define OP_CACHE_FLUSH_ONE_LINE_BY_ADDRESS (0xa << SCP_CACHE_OP_OP_SHIFT) +#define OP_CACHE_FLUSH_ONE_LINE_BY_SET_WAY (0xc << SCP_CACHE_OP_OP_SHIFT) + +#define SCP_CACHE_OP_TADDR_SHIFT 5 +#define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT) +#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT) /* Cache statistics */ -#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08) -#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c) -#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10) -#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14) -#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18) -#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c) -#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20) -#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24) - -#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c) - -#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000) -#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4) -#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) -#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + \ - (reg)*4) -#define SCP_CACHE_ENTRY_C BIT(8) -#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) +#define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08) +#define SCP_CACHE_HCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x0c) +#define SCP_CACHE_CCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x10) +#define SCP_CACHE_CCNT0U(x) REG32(SCP_CACHE_SEL(x) + 0x14) +#define SCP_CACHE_HCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x18) +#define SCP_CACHE_HCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x1c) +#define SCP_CACHE_CCNT1L(x) REG32(SCP_CACHE_SEL(x) + 0x20) +#define SCP_CACHE_CCNT1U(x) REG32(SCP_CACHE_SEL(x) + 0x24) + +#define SCP_CACHE_REGION_EN(x) REG32(SCP_CACHE_SEL(x) + 0x2c) + +#define SCP_CACHE_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2000) +#define SCP_CACHE_ENTRY(x, reg) REG32(SCP_CACHE_ENTRY_BASE(x) + (reg)*4) +#define SCP_CACHE_END_ENTRY_BASE(x) (SCP_CACHE_SEL(x) + 0x2040) +#define SCP_CACHE_END_ENTRY(x, reg) REG32(SCP_CACHE_END_ENTRY_BASE(x) + (reg)*4) +#define SCP_CACHE_ENTRY_C BIT(8) +#define SCP_CACHE_ENTRY_BASEADDR_MASK (0xfffff << 12) /* ARMV7 regs */ -#define ARM_SCB_SCR REG32(0xE000ED10) -#define SCR_DEEPSLEEP BIT(2) +#define ARM_SCB_SCR REG32(0xE000ED10) +#define SCR_DEEPSLEEP BIT(2) /* AP regs */ -#define AP_BASE 0xA0000000 -#define TOPCK_BASE AP_BASE /* Top clock */ -#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */ +#define AP_BASE 0xA0000000 +#define TOPCK_BASE AP_BASE /* Top clock */ +#define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */ /* CLK_CFG_5 regs */ -#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090) -#define PWRAP_ULPOSC_MASK (0x3000000) -#define CLK26M (0 << 24) -#define OSC_D16 (1 << 24) -#define OSC_D4 (2 << 24) -#define OSC_D8 (3 << 24) -#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098) -#define PWRAP_ULPOSC_CG BIT(31) +#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090) +#define PWRAP_ULPOSC_MASK (0x3000000) +#define CLK26M (0 << 24) +#define OSC_D16 (1 << 24) +#define OSC_D4 (2 << 24) +#define OSC_D8 (3 << 24) +#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098) +#define PWRAP_ULPOSC_CG BIT(31) #ifdef CHIP_VARIANT_MT8186 /* SCP PLL MUX RG */ -#define CLK_CFG_UPDATE (TOPCK_BASE + 0x0004) -#define SCP_CK_UPDATE_SHFT 1 -#define CLK_CFG_0 (TOPCK_BASE + 0x0040) -#define CLK_CFG_0_SET (TOPCK_BASE + 0x0044) -#define CLK_CFG_0_CLR (TOPCK_BASE + 0x0048) -#define CLK_SCP_SEL_MSK 0x7 -#define CLK_SCP_SEL_SHFT 8 +#define CLK_CFG_UPDATE (TOPCK_BASE + 0x0004) +#define SCP_CK_UPDATE_SHFT 1 +#define CLK_CFG_0 (TOPCK_BASE + 0x0040) +#define CLK_CFG_0_SET (TOPCK_BASE + 0x0044) +#define CLK_CFG_0_CLR (TOPCK_BASE + 0x0048) +#define CLK_SCP_SEL_MSK 0x7 +#define CLK_SCP_SEL_SHFT 8 #endif /* OSC meter */ #ifdef CHIP_VARIANT_MT8186 -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) +#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0140) +#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x017C) #else -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104) -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C) +#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104) +#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x010C) #endif -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x3f << 16) +#define MISC_METER_DIVISOR_MASK 0xff000000 +#define MISC_METER_DIV_1 0 +#define DBG_MODE_MASK 3 +#define DBG_MODE_SET_CLOCK 0 +#define DBG_BIST_SOURCE_MASK (0x3f << 16) #ifdef CHIP_VARIANT_MT8186 -#define DBG_BIST_SOURCE_ULPOSC1 (35 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (34 << 16) +#define DBG_BIST_SOURCE_ULPOSC1 (35 << 16) +#define DBG_BIST_SOURCE_ULPOSC2 (34 << 16) #else -#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16) -#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16) +#define DBG_BIST_SOURCE_ULPOSC1 (0x26 << 16) +#define DBG_BIST_SOURCE_ULPOSC2 (0x25 << 16) #endif -#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) -#define CFG_FREQ_METER_RUN (1 << 4) -#define CFG_FREQ_METER_ENABLE (1 << 12) -#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) +#define AP_SCP_CFG_0 REG32(TOPCK_BASE + 0x0220) +#define CFG_FREQ_METER_RUN (1 << 4) +#define CFG_FREQ_METER_ENABLE (1 << 12) +#define AP_SCP_CFG_1 REG32(TOPCK_BASE + 0x0224) +#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF) /* GPIO */ -#define AP_GPIO_BASE (AP_BASE + 0x00005000) +#define AP_GPIO_BASE (AP_BASE + 0x00005000) /* * AP_GPIO_DIR * GPIO input/out direction, 1 bit per pin. * 0:input 1:output */ -#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4)) +#define AP_GPIO_DIR(n) REG32(AP_GPIO_BASE + ((n) << 4)) /* * AP_GPIO_DOUT, n in [0..5] * GPIO output level, 1 bit per pin * 0:low 1:high */ -#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4)) +#define AP_GPIO_DOUT(n) REG32(AP_GPIO_BASE + 0x100 + ((n) << 4)) /* * AP_GPIO_DIN, n in [0..5] * GPIO input level, 1 bit per pin * 0:low 1:high */ -#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4)) +#define AP_GPIO_DIN(n) REG32(AP_GPIO_BASE + 0x200 + ((n) << 4)) /* * AP_GPIO_MODE, n in [0..22] * Pin mode selection, 4 bit per pin * bit3 - write enable, set to 1 for hw to fetch bit2,1,0. * bit2-0 - mode 0 ~ 7 */ -#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4)) -#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0) -#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0) -#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0) -#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0) +#define AP_GPIO_MODE(n) REG32(AP_GPIO_BASE + 0x300 + ((n) << 4)) +#define AP_GPIO_TRAP REG32(AP_GPIO_BASE + 0x6B0) +#define AP_GPIO_UNIMPLEMENTED REG32(AP_GPIO_BASE + 0x6C0) +#define AP_GPIO_DBG REG32(AP_GPIO_BASE + 0x6D0) +#define AP_GPIO_BANK REG32(AP_GPIO_BASE + 0x6E0) /* AP_GPIO_SEC, n in [0..5] */ -#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4)) +#define AP_GPIO_SEC(n) REG32(AP_GPIO_BASE + 0xF00 + ((n) << 4)) #ifdef CHIP_VARIANT_MT8186 -#define AP_PLL_CON0 REG32(AP_BASE + 0xC000) -#define LTECLKSQ_EN BIT(0) -#define LTECLKSQ_LPF_EN BIT(1) -#define LTECLKSQ_HYS_EN BIT(2) -#define LTECLKSQ_VOD_EN BIT(3) -#define LTECLKSQ_HYS_SEL (0x1 << 4) -#define CLKSQ_RESERVE (0x1 << 10) -#define SSUSB26M_CK2_EN BIT(13) -#define SSUSB26M_CK_EN BIT(14) -#define XTAL26M_CK_EN BIT(15) -#define ULPOSC_CTRL_SEL (0xf << 16) +#define AP_PLL_CON0 REG32(AP_BASE + 0xC000) +#define LTECLKSQ_EN BIT(0) +#define LTECLKSQ_LPF_EN BIT(1) +#define LTECLKSQ_HYS_EN BIT(2) +#define LTECLKSQ_VOD_EN BIT(3) +#define LTECLKSQ_HYS_SEL (0x1 << 4) +#define CLKSQ_RESERVE (0x1 << 10) +#define SSUSB26M_CK2_EN BIT(13) +#define SSUSB26M_CK_EN BIT(14) +#define XTAL26M_CK_EN BIT(15) +#define ULPOSC_CTRL_SEL (0xf << 16) #endif /* @@ -667,15 +666,15 @@ * osc: 0 for ULPOSC1, 1 for ULPSOC2. */ #ifdef CHIP_VARIANT_MT8186 -#define AP_ULPOSC_BASE0 (AP_BASE + 0xC500) -#define AP_ULPOSC_BASE1 (AP_BASE + 0xC504) -#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc) * 0x80) -#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc) * 0x80) +#define AP_ULPOSC_BASE0 (AP_BASE + 0xC500) +#define AP_ULPOSC_BASE1 (AP_BASE + 0xC504) +#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x80) +#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x80) #else -#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700) -#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704) -#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc) * 0x8) -#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc) * 0x8) +#define AP_ULPOSC_BASE0 (AP_BASE + 0xC700) +#define AP_ULPOSC_BASE1 (AP_BASE + 0xC704) +#define AP_ULPOSC_CON02(osc) REG32(AP_ULPOSC_BASE0 + (osc)*0x8) +#define AP_ULPOSC_CON13(osc) REG32(AP_ULPOSC_BASE1 + (osc)*0x8) #endif /* * AP_ULPOSC_CON[0,2] @@ -687,25 +686,25 @@ * bit24-31: reserved */ #ifdef CHIP_VARIANT_MT8186 -#define OSC_CALI_MASK 0x3f -#define OSC_IBAND_SHIFT 6 -#define OSC_FBAND_MASK 0xf -#define OSC_FBAND_SHIFT 13 -#define OSC_DIV_SHIFT 17 +#define OSC_CALI_MASK 0x3f +#define OSC_IBAND_SHIFT 6 +#define OSC_FBAND_MASK 0xf +#define OSC_FBAND_SHIFT 13 +#define OSC_DIV_SHIFT 17 #else -#define OSC_CALI_MSK (0x3f << 0) -#define OSC_CALI_BITS 6 -#define OSC_IBAND_MASK (0x7f << 6) -#define OSC_FBAND_MASK (0x0f << 13) -#define OSC_DIV_MASK (0x1f << 17) -#define OSC_DIV_BITS 5 -#define OSC_RESERVED_MASK (0xff << 24) +#define OSC_CALI_MSK (0x3f << 0) +#define OSC_CALI_BITS 6 +#define OSC_IBAND_MASK (0x7f << 6) +#define OSC_FBAND_MASK (0x0f << 13) +#define OSC_DIV_MASK (0x1f << 17) +#define OSC_DIV_BITS 5 +#define OSC_RESERVED_MASK (0xff << 24) #endif -#define OSC_CP_EN BIT(23) +#define OSC_CP_EN BIT(23) /* AP_ULPOSC_CON[1,3] */ -#define OSC_MOD_MASK (0x03 << 0) -#define OSC_DIV2_EN BIT(2) +#define OSC_MOD_MASK (0x03 << 0) +#define OSC_DIV2_EN BIT(2) #define UNIMPLEMENTED_GPIO_BANK 0 @@ -719,24 +718,24 @@ * 3. Trace clk disable - gate trace clock * 4. DCM for CPU stall - gate CPU clock when CPU stall */ -#define CM4_MODIFICATION REG32(0xE00FE000) -#define CM4_DCM_FEATURE REG32(0xE00FE004) +#define CM4_MODIFICATION REG32(0xE00FE000) +#define CM4_DCM_FEATURE REG32(0xE00FE004) /* UART, 16550 compatible */ -#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) -#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] -#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n) -#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) +#define SCP_UART_BASE(n) CONCAT3(SCP_UART, n, _BASE) +#define UART_REG(n, offset) REG32_ADDR(SCP_UART_BASE(n))[offset] +#define UART_IRQ(n) CONCAT2(SCP_IRQ_UART, n) +#define UART_RX_IRQ(n) CONCAT3(SCP_IRQ_UART, n, _RX) /* Watchdog */ -#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84) -#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset) -#define SCP_WDT_CFG SCP_WDT_REG(0) -#define SCP_WDT_FREQ 33825 -#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ -#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) -#define SCP_WDT_ENABLE BIT(31) -#define SCP_WDT_RELOAD SCP_WDT_REG(4) -#define SCP_WDT_RELOAD_VALUE 1 +#define SCP_WDT_BASE (SCP_CFG_BASE + 0x84) +#define SCP_WDT_REG(offset) REG32(SCP_WDT_BASE + offset) +#define SCP_WDT_CFG SCP_WDT_REG(0) +#define SCP_WDT_FREQ 33825 +#define SCP_WDT_MAX_PERIOD 0xFFFFF /* 31 seconds */ +#define SCP_WDT_PERIOD(ms) (SCP_WDT_FREQ * (ms) / 1000) +#define SCP_WDT_ENABLE BIT(31) +#define SCP_WDT_RELOAD SCP_WDT_REG(4) +#define SCP_WDT_RELOAD_VALUE 1 #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_REGISTERS_H */ -- cgit v1.2.1 From 4dee977c71f9a2a347cc93405b93cf2bb7640521 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:17 -0600 Subject: builtin/stddef.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8d3fd22aa1b5feee8beffa23f2df46f2e02856a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729125 Reviewed-by: Jeremy Bettis --- builtin/stddef.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builtin/stddef.h b/builtin/stddef.h index 69fb1982c7..de8a67688e 100644 --- a/builtin/stddef.h +++ b/builtin/stddef.h @@ -36,7 +36,7 @@ typedef __WCHAR_TYPE__ wchar_t; * check for safety. */ #ifndef offsetof -#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER) +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif #endif /* __CROS_EC_STDDEF_H__ */ -- cgit v1.2.1 From 5b4c64bce2fd0beef196dca922cedeae8a825457 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:24 -0600 Subject: baseboard/brya/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8fe942d009f3af7e91ba823b977262400e0c5db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727866 Reviewed-by: Jeremy Bettis --- baseboard/brya/usb_pd_policy.c | 84 ++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 48 deletions(-) diff --git a/baseboard/brya/usb_pd_policy.c b/baseboard/brya/usb_pd_policy.c index e3e85539bf..3a2f1fbe29 100644 --- a/baseboard/brya/usb_pd_policy.c +++ b/baseboard/brya/usb_pd_policy.c @@ -25,8 +25,8 @@ #include "usb_pd_vdo.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -86,49 +86,38 @@ int board_vbus_source_enabled(int port) #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, - CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { @@ -170,8 +159,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) /* Track whether we've been enabled to ACK TBT EnterModes requests */ static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT]; -__override enum ec_status board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply) +__override enum ec_status +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) { /* Note: Host command has already bounds-checked port */ if (reply == TYPEC_TBT_UFP_REPLY_ACK) @@ -184,8 +173,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port, return EC_RES_SUCCESS; } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -198,7 +186,7 @@ static int svdm_tbt_compat_response_enter_mode( return 0; /* NAK */ if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); @@ -208,7 +196,7 @@ static int svdm_tbt_compat_response_enter_mode( * Mode that requires the reconfiguring of any pins. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); -- cgit v1.2.1 From 97117f8ca6d6b4445905a8cc3002276e01546dbf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:43 -0600 Subject: baseboard/honeybuns/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf540e1e08b2640de9562c004b496c101ed7b32d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727890 Reviewed-by: Jeremy Bettis --- baseboard/honeybuns/usb_pd_policy.c | 125 ++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 69 deletions(-) diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c index ab95a7f9b6..e40af6ea2e 100644 --- a/baseboard/honeybuns/usb_pd_policy.c +++ b/baseboard/honeybuns/usb_pd_policy.c @@ -21,45 +21,46 @@ #include "usb_tc_sm.h" #include "usbc_ppc.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define MP4245_VOLTAGE_WINDOW BIT(2) #define MP4245_VOLTAGE_WINDOW_MASK (MP4245_VOLTAGE_WINDOW - 1) -#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP | PDO_FIXED_UNCONSTRAINED) +#define PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP | \ + PDO_FIXED_UNCONSTRAINED) /* Voltage indexes for the PDOs */ enum volt_idx { - PDO_IDX_5V = 0, - PDO_IDX_9V = 1, - PDO_IDX_15V = 2, - PDO_IDX_20V = 3, + PDO_IDX_5V = 0, + PDO_IDX_9V = 1, + PDO_IDX_15V = 2, + PDO_IDX_20V = 3, PDO_IDX_COUNT }; /* PDOs */ const uint32_t pd_src_host_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), - [PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0), - [PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0), - [PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0), + [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + [PDO_IDX_9V] = PDO_FIXED(9000, 3000, 0), + [PDO_IDX_15V] = PDO_FIXED(15000, 3000, 0), + [PDO_IDX_20V] = PDO_FIXED(20000, 3000, 0), }; BUILD_ASSERT(ARRAY_SIZE(pd_src_host_pdo) == PDO_IDX_COUNT); #ifdef BOARD_C1_1A5_LIMIT const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), }; #else const uint32_t pd_src_display_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS), }; #endif const uint32_t pd_snk_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, 0, PDO_FIXED_FLAGS), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); @@ -74,7 +75,6 @@ static int command_hostpdo(int argc, char **argv) int limit; if (argc >= 2) { - limit = strtoi(argv[1], &e, 10); if ((limit < 0) || (limit > PDO_IDX_COUNT)) return EC_ERROR_PARAM1; @@ -85,8 +85,7 @@ static int command_hostpdo(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, - "<0|1|2|3|4>", +DECLARE_CONSOLE_COMMAND(hostpdo, command_hostpdo, "<0|1|2|3|4>", "Limit number of PDOs for C0"); int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) @@ -94,7 +93,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) int pdo_cnt = 0; if (port == USB_PD_PORT_HOST) { - *src_pdo = pd_src_host_pdo; + *src_pdo = pd_src_host_pdo; pdo_cnt = ARRAY_SIZE(pd_src_host_pdo); /* * This override is only active via a console command. Only used @@ -105,7 +104,7 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) if (src_host_pdo_cnt_override) pdo_cnt = src_host_pdo_cnt_override; } else { - *src_pdo = pd_src_display_pdo; + *src_pdo = pd_src_display_pdo; pdo_cnt = ARRAY_SIZE(pd_src_display_pdo); } @@ -118,15 +117,15 @@ int dpm_get_source_pdo(const uint32_t **src_pdo, const int port) * 1) If port == 0 and port data role is DFP, transition to pe_drs_send_swap * 2) If port == 1 and port data role is UFP, transition to pe_drs_send_swap */ -__override bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag) +__override bool port_discovery_dr_swap_policy(int port, enum pd_data_role dr, + bool dr_swap_flag) { /* * Port0: test if role is DFP * Port1: test if role is UFP */ - enum pd_data_role role_test = - (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : PD_ROLE_UFP; + enum pd_data_role role_test = (port == USB_PD_PORT_HOST) ? PD_ROLE_DFP : + PD_ROLE_UFP; /* * Request data role swap if not in the port's desired data role and if @@ -135,8 +134,8 @@ __override bool port_discovery_dr_swap_policy(int port, * rejects data role swap requests (eg compliance tester), want to limit * how many DR swap requests are attempted. */ - if (dr == role_test && (pd_dr_swap_attempt_count[port]++ < - PD_DR_SWAP_ATTEMPT_MAX)) + if (dr == role_test && + (pd_dr_swap_attempt_count[port]++ < PD_DR_SWAP_ATTEMPT_MAX)) return true; /* Do not perform a DR swap */ @@ -148,8 +147,7 @@ __override bool port_discovery_dr_swap_policy(int port, * * 1) No need to Vconn swap. This board does not require any cable information. */ -__override bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag) +__override bool port_discovery_vconn_swap_policy(int port, bool vconn_swap_flag) { return false; } @@ -193,8 +191,7 @@ void pd_power_supply_reset(int port) * (fixed 5V SRC_CAP) so VBUS is ready to be applied at the next * attached.src condition. */ - pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, - &unused_mv); + pd_extract_pdo_power(pd_src_host_pdo[0], &ma, &mv, &unused_mv); mp4245_set_voltage_out(mv); /* Ensure voltage is back to 5V */ pd_transition_voltage(1); @@ -243,8 +240,7 @@ void pd_transition_voltage(int idx) * by the PDO requested by sink. Note that USB PD uses idx = 1 for 1st * PDO of SRC_CAP which must always be 5V fixed supply. */ - pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, - &mv); + pd_extract_pdo_power(pd_src_host_pdo[idx - 1], &ma, &target_mv, &mv); /* Initialize sample delay buffer */ for (i = 0; i < MP4245_VOLTAGE_WINDOW; i++) @@ -327,11 +323,9 @@ int board_vbus_source_enabled(int port) void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) { - } -int pd_check_data_swap(int port, - enum pd_data_role data_role) +int pd_check_data_swap(int port, enum pd_data_role data_role) { int swap = 0; @@ -345,7 +339,6 @@ int pd_check_data_swap(int port, int pd_check_power_swap(int port) { - if (pd_get_power_role(port) == PD_ROLE_SINK) return 1; @@ -394,7 +387,7 @@ static void usb_tc_disconnect(void) DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, usb_tc_disconnect, HOOK_PRIO_DEFAULT); __override bool pd_can_charge_from_device(int port, const int pdo_cnt, - const uint32_t *pdos) + const uint32_t *pdos) { /* * This function is called to determine if this port can be charged by @@ -421,22 +414,17 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ USB_VID_GOOGLE); static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 0, /* Data caps as USB host */ - 1, /* Data caps as USB device */ - IDH_PTYPE_HUB, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_UNDEFINED, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); + 0, /* Data caps as USB host */ + 1, /* Data caps as USB device */ + IDH_PTYPE_HUB, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_UNDEFINED, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); -static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_RECONFIGURE, - USB_R30_SS_U32_U40_GEN2); +static const uint32_t vdo_ufp1 = + VDO_UFP1((VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_RECONFIGURE, + USB_R30_SS_U32_U40_GEN2); static int svdm_response_identity(int port, uint32_t *payload) { @@ -479,14 +467,16 @@ static int svdm_response_svids(int port, uint32_t *payload) #define OPOS_DP 1 -const uint32_t vdo_dp_modes[1] = { +const uint32_t vdo_dp_modes[1] = { VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */ - MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, - 0, /* DFP pin cfg supported */ - 0, /* usb2.0 signalling in AMode may be req */ - CABLE_RECEPTACLE, /* its a receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, 0, /* DFP pin + cfg + supported + */ + 0, /* usb2.0 signalling in AMode may be req */ + CABLE_RECEPTACLE, /* its a receptacle */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; static int svdm_response_modes(int port, uint32_t *payload) @@ -508,13 +498,12 @@ static int amode_dp_status(int port, uint32_t *payload) if (opos != OPOS_DP) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - mf, /* MF pref */ - vdm_is_dp_enabled(port), - 0, /* power low */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + mf, /* MF pref */ + vdm_is_dp_enabled(port), 0, /* power low */ 0x2); return 2; } @@ -536,8 +525,8 @@ static void svdm_configure_demux(int port, int enable, int mf) * stored in bit 0 of CBI fw_config. */ baseboard_set_mst_lane_control(mf); - CPRINTS("DP[%d]: DFP-D selected pin config %s", - port, mf ? "D" : "C"); + CPRINTS("DP[%d]: DFP-D selected pin config %s", port, + mf ? "D" : "C"); } else { demux &= ~USB_PD_MUX_DP_ENABLED; demux |= USB_PD_MUX_USB_ENABLED; @@ -573,7 +562,6 @@ static int svdm_enter_mode(int port, uint32_t *payload) /* SID & mode request is valid */ if ((PD_VDO_VID(payload[0]) == USB_SID_DISPLAYPORT) && (PD_VDO_OPOS(payload[0]) == OPOS_DP)) { - /* Store valid object position to indicate mode is active */ pd_ufp_set_dp_opos(port, OPOS_DP); @@ -623,8 +611,7 @@ const struct svdm_response svdm_rsp = { .exit_mode = &svdm_exit_mode, }; -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) +int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload) { /* We don't support, so ignore this message */ return 0; -- cgit v1.2.1 From 4701739345f9589e41a51e3022c20011c9fd10d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:27 -0600 Subject: common/usbc/usb_retimer_fw_update.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53da4c955632a6394ffb321fe114f72124c21ddd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729793 Reviewed-by: Jeremy Bettis --- common/usbc/usb_retimer_fw_update.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/common/usbc/usb_retimer_fw_update.c b/common/usbc/usb_retimer_fw_update.c index 1c3023db9b..1b8c2c288b 100644 --- a/common/usbc/usb_retimer_fw_update.c +++ b/common/usbc/usb_retimer_fw_update.c @@ -14,8 +14,8 @@ #include "usb_tc_sm.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -46,7 +46,7 @@ */ #define SUSPEND 1 -#define RESUME 0 +#define RESUME 0 /* Track current port AP requested to update retimer firmware */ static int cur_port; @@ -175,8 +175,8 @@ void usb_retimer_fw_update_process_op_cb(int port) result_mux_get = true; break; case USB_RETIMER_FW_UPDATE_SET_USB: - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, pd_get_polarity(port)); + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, + pd_get_polarity(port)); result_mux_get = true; break; case USB_RETIMER_FW_UPDATE_SET_SAFE: @@ -185,12 +185,12 @@ void usb_retimer_fw_update_process_op_cb(int port) break; case USB_RETIMER_FW_UPDATE_SET_TBT: usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED, - USB_SWITCH_CONNECT, pd_get_polarity(port)); + USB_SWITCH_CONNECT, pd_get_polarity(port)); result_mux_get = true; break; case USB_RETIMER_FW_UPDATE_DISCONNECT: - usb_mux_set(port, USB_PD_MUX_NONE, - USB_SWITCH_DISCONNECT, pd_get_polarity(port)); + usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, + pd_get_polarity(port)); result_mux_get = true; break; default: @@ -253,7 +253,7 @@ static void restore_port(void) { int port; - for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) { + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) { if (retimer_fw_update_get_port_state(port)) retimer_fw_update_port_handler(port, RESUME); } -- cgit v1.2.1 From 784f1b24146931556a369c1a70399e1ccdfc1817 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:41 -0600 Subject: board/galtic/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e15c6df5b55812894a00a654d4ea7db5ab1892c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728383 Reviewed-by: Jeremy Bettis --- board/galtic/board.c | 170 +++++++++++++++++++++------------------------------ 1 file changed, 71 insertions(+), 99 deletions(-) diff --git a/board/galtic/board.c b/board/galtic/board.c index 727e31508e..df339f7313 100644 --- a/board/galtic/board.c +++ b/board/galtic/board.c @@ -47,8 +47,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -131,34 +131,26 @@ static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -218,40 +210,31 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; /* USB Retimer */ -enum tusb544_conf { - USB_DP = 0, - USB_DP_INV, - USB, - USB_INV, - DP, - DP_INV -}; +enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV }; -static int board_tusb544_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state) { - int rv = EC_SUCCESS; + int rv = EC_SUCCESS; enum tusb544_conf usb_mode = 0; /* USB */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_DP_INV - : USB_DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_DP_INV : + USB_DP; } /* USB without DP */ else { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_INV - : USB; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_INV : + USB; } } /* DP without USB */ else if (mux_state & USB_PD_MUX_DP_ENABLED) { - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? DP_INV - : DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV : + DP; } /* Nothing enabled */ else @@ -320,11 +303,9 @@ static int board_tusb544_set(const struct usb_mux *me, return rv; } -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { - return ps8743_write(me, PS8743_REG_USB_EQ_RX, - PS8743_USB_EQ_RX_16_7_DB); + return ps8743_write(me, PS8743_REG_USB_EQ_RX, PS8743_USB_EQ_RX_16_7_DB); } const struct usb_mux usbc1_retimer = { @@ -392,8 +373,8 @@ static const struct ec_response_keybd_config galtic_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (get_cbi_fw_config_numeric_pad() == NUMERIC_PAD_PRESENT) return &galith_kb; @@ -532,8 +513,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -595,12 +575,10 @@ int board_set_active_charge_port(int port) charger_discharge_on_ac(0); return EC_SUCCESS; - } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -634,27 +612,21 @@ static struct mutex g_base_mutex; /* Sensor Data */ static struct accelgyro_saved_data_t g_bma253_data; -static struct kionix_accel_data g_kx022_data; +static struct kionix_accel_data g_kx022_data; static struct bmi_drv_data_t g_bmi160_data; static struct icm_drv_data_t g_icm426xx_data; -const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref_icm = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_icm = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref_bmi = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_bmi = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t bma253_lid_accel = { .name = "Lid Accel", @@ -826,26 +798,26 @@ DECLARE_HOOK(HOOK_INIT, board_sensors_init, HOOK_PRIO_DEFAULT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Vcore", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Vcore", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(98), \ @@ -859,8 +831,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_VCORE \ - { \ +#define THERMAL_VCORE \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -874,8 +846,8 @@ __maybe_unused static const struct ec_thermal_config thermal_vcore = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_AMBIENT \ - { \ +#define THERMAL_AMBIENT \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -941,8 +913,8 @@ static void get_battery_cell(void) { int val; - if (i2c_read16(I2C_PORT_USB_C0, ISL923X_ADDR_FLAGS, - ISL9238_REG_INFO2, &val) == EC_SUCCESS) { + if (i2c_read16(I2C_PORT_USB_C0, ISL923X_ADDR_FLAGS, ISL9238_REG_INFO2, + &val) == EC_SUCCESS) { /* PROG resistor read out. Number of battery cells [4:0] */ val = val & 0x001f; } @@ -958,7 +930,7 @@ static void get_battery_cell(void) CPRINTS("Get battery cells: %d", battery_cell); } -DECLARE_HOOK(HOOK_INIT, get_battery_cell, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, get_battery_cell, HOOK_PRIO_INIT_I2C + 1); enum battery_cell_type board_get_battery_cell_type(void) { -- cgit v1.2.1 From 2aefd00cdaa4bc2743ba38a210bf4e0d9c734302 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:37 -0600 Subject: board/kracko/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9ae1baee85214910edd7c2c8b93226ae40610b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728588 Reviewed-by: Jeremy Bettis --- board/kracko/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/kracko/cbi_ssfc.h b/board/kracko/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/kracko/cbi_ssfc.h +++ b/board/kracko/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From cd4091b55b34d8f645a154ea2c9606b13bdf9c48 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:51 -0600 Subject: board/trembyle/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3960782470a1d59f915c463a23cfa0c771e6756 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729034 Reviewed-by: Jeremy Bettis --- board/trembyle/board.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/board/trembyle/board.c b/board/trembyle/board.c index ae81323902..e4d8431e91 100644 --- a/board/trembyle/board.c +++ b/board/trembyle/board.c @@ -37,8 +37,8 @@ #include "gpio_list.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Motion sensors */ static struct mutex g_lid_mutex; @@ -205,8 +205,8 @@ static void board_chipset_resume(void) int val; rv = i2c_read8(I2C_PORT_USBA0, - PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); + PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1, + PS8811_REG1_USB_BEQ_LEVEL, &val); if (!rv) break; } @@ -220,10 +220,10 @@ static void board_chipset_resume(void) rv = i2c_write8(I2C_PORT_USBA1, PS8811_I2C_ADDR_FLAGS3 + PS8811_REG_PAGE1, PS8811_REG1_USB_BEQ_LEVEL, - (PS8811_BEQ_I2C_LEVEL_UP_13DB << - PS8811_BEQ_I2C_LEVEL_UP_SHIFT) | - (PS8811_BEQ_PIN_LEVEL_UP_18DB << - PS8811_BEQ_PIN_LEVEL_UP_SHIFT)); + (PS8811_BEQ_I2C_LEVEL_UP_13DB + << PS8811_BEQ_I2C_LEVEL_UP_SHIFT) | + (PS8811_BEQ_PIN_LEVEL_UP_18DB + << PS8811_BEQ_PIN_LEVEL_UP_SHIFT)); if (!rv) break; } @@ -233,9 +233,7 @@ static void board_chipset_resume(void) } if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 1); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1); } } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -246,9 +244,7 @@ static void board_chipset_suspend(void) ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); } } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); @@ -265,8 +261,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the PS8802 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_ps8802, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_ps8802, sizeof(struct usb_mux)); /* Set the AMD FP5 as the secondary MUX */ @@ -282,8 +277,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the PS8818 as the secondary MUX */ @@ -361,7 +355,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -452,8 +446,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_THERMISTOR \ - { \ +#define THERMAL_THERMISTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(92), \ @@ -470,8 +464,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(92), \ -- cgit v1.2.1 From f0a2e4c54bdc930ef17b5f0bd5bf5b98a1b7bb6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:25 -0600 Subject: board/kohaku/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibc22cf43208f121e3ed5ee002d35baaf630abbb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728564 Reviewed-by: Jeremy Bettis --- board/kohaku/board.h | 62 ++++++++++++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/board/kohaku/board.h b/board/kohaku/board.h index de87000f34..8b1339fc89 100644 --- a/board/kohaku/board.h +++ b/board/kohaku/board.h @@ -35,8 +35,7 @@ #define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT /* Camera VSYNC */ #define CONFIG_SYNC -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) /* BMA253 Lid accel */ #define CONFIG_ACCEL_BMA255 #define CONFIG_LID_ANGLE @@ -46,7 +45,7 @@ /* BH1730 and TCS3400 ALS */ #define CONFIG_ALS #define ALS_COUNT 2 -#define I2C_PORT_ALS I2C_PORT_SENSOR +#define I2C_PORT_ALS I2C_PORT_SENSOR #define CONFIG_ALS_BH1730 #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ @@ -70,18 +69,18 @@ * Kohaku will not use both BH1730_LUXTH3_1K condition * and BH1730_LUXTH4_1K condition. */ -#define BH1730_LUXTH1_1K 270 -#define BH1730_LUXTH1_D0_1K 19200 -#define BH1730_LUXTH1_D1_1K 30528 -#define BH1730_LUXTH2_1K 655360000 -#define BH1730_LUXTH2_D0_1K 11008 -#define BH1730_LUXTH2_D1_1K 10752 -#define BH1730_LUXTH3_1K 1030 -#define BH1730_LUXTH3_D0_1K 11008 -#define BH1730_LUXTH3_D1_1K 10752 -#define BH1730_LUXTH4_1K 3670 -#define BH1730_LUXTH4_D0_1K 11008 -#define BH1730_LUXTH4_D1_1K 10752 +#define BH1730_LUXTH1_1K 270 +#define BH1730_LUXTH1_D0_1K 19200 +#define BH1730_LUXTH1_D1_1K 30528 +#define BH1730_LUXTH2_1K 655360000 +#define BH1730_LUXTH2_D0_1K 11008 +#define BH1730_LUXTH2_D1_1K 10752 +#define BH1730_LUXTH3_1K 1030 +#define BH1730_LUXTH3_D0_1K 11008 +#define BH1730_LUXTH3_D1_1K 10752 +#define BH1730_LUXTH4_1K 3670 +#define BH1730_LUXTH4_D0_1K 11008 +#define BH1730_LUXTH4_D1_1K 10752 /* USB Type C and USB PD defines */ #define CONFIG_USB_PD_COMM_LOCKED @@ -130,16 +129,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -150,10 +149,10 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_TEMP_SENSOR_3, /* ADC2 */ - ADC_TEMP_SENSOR_4, /* ADC3 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_3, /* ADC2 */ + ADC_TEMP_SENSOR_4, /* ADC3 */ ADC_CH_COUNT }; @@ -168,10 +167,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum temp_sensor_id { TEMP_SENSOR_1, -- cgit v1.2.1 From a3ed759d2737c622b81406211baa1b395ca91766 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:34 -0600 Subject: board/drawcia/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4c404ae4b0392f4fedf6f530b2bedaa81bfa84a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728254 Reviewed-by: Jeremy Bettis --- board/drawcia/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/drawcia/cbi_ssfc.h b/board/drawcia/cbi_ssfc.h index 6f3591a496..3257d00e9b 100644 --- a/board/drawcia/cbi_ssfc.h +++ b/board/drawcia/cbi_ssfc.h @@ -55,5 +55,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 811dccb64056d2eacb777acfb86730367807cf88 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:15 -0600 Subject: baseboard/intelrvp/led_states.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I13a8facf7aadf5cb237bab71fca9b359b71f0689 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727902 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/led_states.h | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/baseboard/intelrvp/led_states.h b/baseboard/intelrvp/led_states.h index 907ff5c8b8..5d032c9960 100644 --- a/baseboard/intelrvp/led_states.h +++ b/baseboard/intelrvp/led_states.h @@ -10,19 +10,15 @@ #include "ec_commands.h" -#define LED_INDEFINITE UINT8_MAX -#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) -#define LED_OFF EC_LED_COLOR_COUNT +#define LED_INDEFINITE UINT8_MAX +#define LED_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define LED_OFF EC_LED_COLOR_COUNT /* * All LED states should have one phase defined, * and an additional phase can be defined for blinking */ -enum led_phase { - LED_PHASE_0, - LED_PHASE_1, - LED_NUM_PHASES -}; +enum led_phase { LED_PHASE_0, LED_PHASE_1, LED_NUM_PHASES }; /* * STATE_CHARGING_LVL_1 is when 0 <= charge_percentage < led_charge_level_1 @@ -51,10 +47,8 @@ struct led_descriptor { uint8_t time; }; - /* Charging LED state table - defined in board's led.c */ -extern struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; +extern struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES]; /* Charging LED state level 1 - defined in board's led.c */ extern const int led_charge_lvl_1; @@ -71,8 +65,8 @@ enum pwr_led_states { }; /* Power LED state table - defined in board's led.c */ -extern const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES]; +extern const struct led_descriptor led_pwr_state_table[PWR_LED_NUM_STATES] + [LED_NUM_PHASES]; /** * Set battery LED color - defined in board's led.c -- cgit v1.2.1 From 91d1617d4c412af072de4b682a79cf0ab4e6e984 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:44 -0600 Subject: core/cortex-m/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I219906a9e12057dc850b19a34ec32d53c10e943a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729821 Reviewed-by: Jeremy Bettis --- core/cortex-m/irq_handler.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/core/cortex-m/irq_handler.h b/core/cortex-m/irq_handler.h index dceda73958..e47b0f4d1e 100644 --- a/core/cortex-m/irq_handler.h +++ b/core/cortex-m/irq_handler.h @@ -23,20 +23,20 @@ * ensure it is enabled in the interrupt controller with the right priority. */ #define DECLARE_IRQ(irq, routine, priority) DECLARE_IRQ_(irq, routine, priority) -#define DECLARE_IRQ_(irq, routine, priority) \ - void IRQ_HANDLER(irq)(void); \ - typedef struct { \ - int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ - } irq_num_check_##irq; \ - static void __keep routine(void); \ - void IRQ_HANDLER(irq)(void) \ - { \ - void *ret = __builtin_return_address(0); \ - TASK_START_IRQ_HANDLER(ret); \ - routine(); \ - task_resched_if_needed(ret); \ - } \ - const struct irq_priority __keep IRQ_PRIORITY(irq) \ - __attribute__((section(".rodata.irqprio"))) \ - = {irq, priority} -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#define DECLARE_IRQ_(irq, routine, priority) \ + void IRQ_HANDLER(irq)(void); \ + typedef struct { \ + int fake[irq >= CONFIG_IRQ_COUNT ? -1 : 1]; \ + } irq_num_check_##irq; \ + static void __keep routine(void); \ + void IRQ_HANDLER(irq)(void) \ + { \ + void *ret = __builtin_return_address(0); \ + TASK_START_IRQ_HANDLER(ret); \ + routine(); \ + task_resched_if_needed(ret); \ + } \ + const struct irq_priority __keep IRQ_PRIORITY(irq) \ + __attribute__((section(".rodata.irqprio"))) = { irq, \ + priority } +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From d151548b9d9091b1b49c0cfc03ebe0c4193c561c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:09 -0600 Subject: board/mushu/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19c06ccd7f920aa96cab614b22db7fdaa32e395f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728715 Reviewed-by: Jeremy Bettis --- board/mushu/thermal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/board/mushu/thermal.c b/board/mushu/thermal.c index b61f36ab8a..3b6645ffa2 100644 --- a/board/mushu/thermal.c +++ b/board/mushu/thermal.c @@ -23,8 +23,7 @@ void fan_set_percent(int fan, int pct) new_rpm = fan_percent_to_rpm(fan, pct); actual_rpm = fan_get_rpm_actual(FAN_CH(fan)); - if (new_rpm && - actual_rpm < min_rpm && + if (new_rpm && actual_rpm < min_rpm && new_rpm < fans[fan].rpm->rpm_start) new_rpm = fans[fan].rpm->rpm_start; -- cgit v1.2.1 From 3c0dfa12e5cd96dc798ae2b4523c89f2021301da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:09 -0600 Subject: test/x25519.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idaea355021e4a3806512ce11f8a4bd8c7ca55516 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730320 Reviewed-by: Jeremy Bettis --- test/x25519.c | 197 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 196 insertions(+), 1 deletion(-) mode change 120000 => 100644 test/x25519.c diff --git a/test/x25519.c b/test/x25519.c deleted file mode 120000 index 75aefa9842..0000000000 --- a/test/x25519.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/test/x25519.c \ No newline at end of file diff --git a/test/x25519.c b/test/x25519.c new file mode 100644 index 0000000000..239369dac9 --- /dev/null +++ b/test/x25519.c @@ -0,0 +1,196 @@ +/* Copyright (c) 2015, Google Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ + +#include "console.h" +#include "common.h" +#include "curve25519.h" +#include "test_util.h" +#include "timer.h" +#include "util.h" +#include "watchdog.h" + +/* + * Define this to test 1 million iterations of x25519 (takes up to + * a few minutes on host, up to a few days on microcontroller). + */ +#undef TEST_X25519_1M_ITERATIONS + +static int test_x25519(void) +{ + /* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */ + static const uint8_t scalar1[32] = { + 0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d, + 0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd, + 0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18, + 0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4, + }; + static const uint8_t point1[32] = { + 0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb, + 0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c, + 0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b, + 0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c, + }; + static const uint8_t expected1[32] = { + 0xc3, 0xda, 0x55, 0x37, 0x9d, 0xe9, 0xc6, 0x90, + 0x8e, 0x94, 0xea, 0x4d, 0xf2, 0x8d, 0x08, 0x4f, + 0x32, 0xec, 0xcf, 0x03, 0x49, 0x1c, 0x71, 0xf7, + 0x54, 0xb4, 0x07, 0x55, 0x77, 0xa2, 0x85, 0x52, + }; + static const uint8_t scalar2[32] = { + 0x4b, 0x66, 0xe9, 0xd4, 0xd1, 0xb4, 0x67, 0x3c, + 0x5a, 0xd2, 0x26, 0x91, 0x95, 0x7d, 0x6a, 0xf5, + 0xc1, 0x1b, 0x64, 0x21, 0xe0, 0xea, 0x01, 0xd4, + 0x2c, 0xa4, 0x16, 0x9e, 0x79, 0x18, 0xba, 0x0d, + }; + static const uint8_t point2[32] = { + 0xe5, 0x21, 0x0f, 0x12, 0x78, 0x68, 0x11, 0xd3, + 0xf4, 0xb7, 0x95, 0x9d, 0x05, 0x38, 0xae, 0x2c, + 0x31, 0xdb, 0xe7, 0x10, 0x6f, 0xc0, 0x3c, 0x3e, + 0xfc, 0x4c, 0xd5, 0x49, 0xc7, 0x15, 0xa4, 0x93, + }; + static const uint8_t expected2[32] = { + 0x95, 0xcb, 0xde, 0x94, 0x76, 0xe8, 0x90, 0x7d, + 0x7a, 0xad, 0xe4, 0x5c, 0xb4, 0xb8, 0x73, 0xf8, + 0x8b, 0x59, 0x5a, 0x68, 0x79, 0x9f, 0xa1, 0x52, + 0xe6, 0xf8, 0xf7, 0x64, 0x7a, 0xac, 0x79, 0x57, + }; + uint8_t out[32]; + + X25519(out, scalar1, point1); + + if (memcmp(expected1, out, sizeof(out)) != 0) { + ccprintf("X25519 test one failed.\n"); + return 0; + } + + X25519(out, scalar2, point2); + + if (memcmp(expected2, out, sizeof(out)) != 0) { + ccprintf("X25519 test two failed.\n"); + return 0; + } + + return 1; +} + +static int test_x25519_small_order(void) +{ + static const uint8_t kSmallOrderPoint[32] = { + 0xe0, 0xeb, 0x7a, 0x7c, 0x3b, 0x41, 0xb8, 0xae, + 0x16, 0x56, 0xe3, 0xfa, 0xf1, 0x9f, 0xc4, 0x6a, + 0xda, 0x09, 0x8d, 0xeb, 0x9c, 0x32, 0xb1, 0xfd, + 0x86, 0x62, 0x05, 0x16, 0x5f, 0x49, 0xb8, + }; + uint8_t out[32], private_key[32]; + + memset(private_key, 0x11, sizeof(private_key)); + + if (X25519(out, private_key, kSmallOrderPoint)) { + ccprintf("X25519 returned success with a small-order input.\n"); + return 0; + } + + return 1; +} + +static int test_x25519_iterated(void) +{ + /* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */ + static const uint8_t expected_1K[32] = { + 0x68, 0x4c, 0xf5, 0x9b, 0xa8, 0x33, 0x09, 0x55, + 0x28, 0x00, 0xef, 0x56, 0x6f, 0x2f, 0x4d, 0x3c, + 0x1c, 0x38, 0x87, 0xc4, 0x93, 0x60, 0xe3, 0x87, + 0x5f, 0x2e, 0xb9, 0x4d, 0x99, 0x53, 0x2c, 0x51, + }; +#ifdef TEST_X25519_1M_ITERATIONS + static const uint8_t expected_1M[32] = { + 0x7c, 0x39, 0x11, 0xe0, 0xab, 0x25, 0x86, 0xfd, + 0x86, 0x44, 0x97, 0x29, 0x7e, 0x57, 0x5e, 0x6f, + 0x3b, 0xc6, 0x01, 0xc0, 0x88, 0x3c, 0x30, 0xdf, + 0x5f, 0x4d, 0xd2, 0xd2, 0x4f, 0x66, 0x54, 0x24 + }; +#endif + uint8_t scalar[32] = { 9 }, point[32] = { 9 }, out[32]; + unsigned i; + + for (i = 0; i < 1000; i++) { + watchdog_reload(); + X25519(out, scalar, point); + memcpy(point, scalar, sizeof(point)); + memcpy(scalar, out, sizeof(scalar)); + } + + if (memcmp(expected_1K, scalar, sizeof(expected_1K)) != 0) { + ccprintf("1,000 iterations X25519 test failed\n"); + return 0; + } + +#ifdef TEST_X25519_1M_ITERATIONS + for (; i < 1000000; i++) { + watchdog_reload(); + X25519(out, scalar, point); + memcpy(point, scalar, sizeof(point)); + memcpy(scalar, out, sizeof(scalar)); + if ((i % 10000) == 0) + ccprints("%d", i); + } + + if (memcmp(expected_1M, scalar, sizeof(expected_1M)) != 0) { + ccprintf("1,000,000 iterations X25519 test failed\n"); + return 0; + } +#endif + + return 1; +} + +static void test_x25519_speed(void) +{ + static const uint8_t scalar1[32] = { + 0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d, + 0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd, + 0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18, + 0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4, + }; + static const uint8_t point1[32] = { + 0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb, + 0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c, + 0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b, + 0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c, + }; + uint8_t out[32]; + timestamp_t t0, t1; + + X25519(out, scalar1, point1); + t0 = get_time(); + X25519(out, scalar1, point1); + t1 = get_time(); + ccprintf("X25519 duration %lld us\n", (long long)(t1.val - t0.val)); +} + +void run_test(int argc, char **argv) +{ + watchdog_reload(); + /* do not check speed, just as a benchmark */ + test_x25519_speed(); + + watchdog_reload(); + if (!test_x25519() || !test_x25519_iterated() || + !test_x25519_small_order()) { + test_fail(); + return; + } + + test_pass(); +} -- cgit v1.2.1 From 4ab1b480566ce2aafc1ea3a07eb52952f5b5a31a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:38 -0600 Subject: zephyr/shim/src/power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If60df059ee48c0a16ef4b973d8bb02039127deb7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730914 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/power.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/src/power.c b/zephyr/shim/src/power.c index 49f820e567..efdecb7a33 100644 --- a/zephyr/shim/src/power.c +++ b/zephyr/shim/src/power.c @@ -11,11 +11,8 @@ #if (SYSTEM_DT_POWER_SIGNAL_CONFIG) -const struct power_signal_info power_signal_list[] = { - DT_FOREACH_CHILD( - POWER_SIGNAL_LIST_NODE, - GEN_POWER_SIGNAL_STRUCT) -}; +const struct power_signal_info power_signal_list[] = { DT_FOREACH_CHILD( + POWER_SIGNAL_LIST_NODE, GEN_POWER_SIGNAL_STRUCT) }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); #endif /* SYSTEM_DT_POWER_SIGNAL_CONFIG */ -- cgit v1.2.1 From 1cb85ae13199b57f3a5ca617ba57c645883983d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:02 -0600 Subject: board/puff/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52c8ed8a39b838401a5ffce704ff68d8bb07c837 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728867 Reviewed-by: Jeremy Bettis --- board/puff/board.h | 106 ++++++++++++++++++++++++++--------------------------- 1 file changed, 51 insertions(+), 55 deletions(-) diff --git a/board/puff/board.h b/board/puff/board.h index 185c3d0076..021b8545fa 100644 --- a/board/puff/board.h +++ b/board/puff/board.h @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -85,7 +85,7 @@ #define CONFIG_CPU_PROCHOT_ACTIVE_LOW /* Dedicated barreljack charger port */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT 1 @@ -104,15 +104,15 @@ #define CONFIG_INA3221 /* b/143501304 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Fan and temp. */ #define CONFIG_FANS 1 @@ -136,7 +136,7 @@ #define CONFIG_USB_PD_DECODE_SOP #undef CONFIG_USB_CHARGER #define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PID 0x5040 +#define CONFIG_USB_PID 0x5040 #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DISCHARGE_PPC @@ -156,7 +156,7 @@ #define CONFIG_USBC_VCONN #define CONFIG_USBC_VCONN_SWAP -#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_0 0 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS @@ -168,12 +168,12 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -191,11 +191,11 @@ enum charge_port { }; enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -220,11 +220,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_COUNT -}; - +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT }; /* Board specific handlers */ void board_reset_pd_mcu(void); @@ -238,20 +234,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) unsigned int ec_config_get_bj_power(void); @@ -261,30 +257,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 4313b5bd5fba83a8a3a9f294d3a7d0ff2f027a20 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:37 -0600 Subject: board/rammus/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb79947c4539572f1bfc844ee759e0fc9cf13b48 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728853 Reviewed-by: Jeremy Bettis --- board/rammus/battery.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/board/rammus/battery.c b/board/rammus/battery.c index 1ae15e9dcc..5d394e4fc0 100644 --- a/board/rammus/battery.c +++ b/board/rammus/battery.c @@ -17,8 +17,8 @@ static enum battery_present batt_pres_prev = BP_NOT_SURE; /* Shutdown mode parameters to write to manufacturer access register */ -#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS +#define SB_SHUTDOWN_DATA 0x0010 static const struct battery_info info = { .voltage_max = 13200, @@ -63,8 +63,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* @@ -85,13 +86,13 @@ static int battery_check_disconnect(void) uint8_t data[6]; /* Check if battery charging + discharging is disabled. */ - rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, SB_ALT_MANUFACTURER_ACCESS, + data, sizeof(data)); if (rv) return BATTERY_DISCONNECT_ERROR; - if ((data[3] & (BATTERY_DISCHARGING_DISABLED | - BATTERY_CHARGING_DISABLED)) == + if ((data[3] & + (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) == (BATTERY_DISCHARGING_DISABLED | BATTERY_CHARGING_DISABLED)) return BATTERY_DISCONNECTED; -- cgit v1.2.1 From 77f6d77086a7e4b2e8c2ca2fb2f97830e508a4d2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:02 -0600 Subject: baseboard/grunt/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I30db049f875f9677cdd9715d4c959bd81cf29402 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727515 Reviewed-by: Jeremy Bettis --- baseboard/grunt/baseboard.c | 141 ++++++++++++++++++++------------------------ 1 file changed, 63 insertions(+), 78 deletions(-) diff --git a/baseboard/grunt/baseboard.c b/baseboard/grunt/baseboard.c index b1f110033a..c8f80e2589 100644 --- a/baseboard/grunt/baseboard.c +++ b/baseboard/grunt/baseboard.c @@ -47,34 +47,29 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_TEMP_SENSOR_SOC] = { - "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_VBUS] = { - "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID1] = { - "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, - [ADC_SKU_ID2] = { - "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 - }, + [ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_SOC] = { "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_SKU_ID1] = { "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_SKU_ID2] = { "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, - {GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"}, - {GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"}, - {GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"}, + { GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED" }, + { GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED" }, + { GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD" }, + { GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -156,7 +151,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -278,8 +273,8 @@ static uint32_t sku_id; static int ps8751_tune_mux(const struct usb_mux *me) { /* Tune USB mux registers for treeya's port 1 Rx measurement */ - if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) + if (((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf) mux_write(me, PS8XXX_REG_MUX_USB_C2SS_EQ, 0x40); return EC_SUCCESS; @@ -308,16 +303,12 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -338,8 +329,8 @@ int ppc_get_alert_status(int port) void board_overcurrent_event(int port, int is_overcurrented) { - enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L - : GPIO_USB_C1_OC_L; + enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L : + GPIO_USB_C1_OC_L; /* Note that the levels are inverted because the pin is active low. */ int lvl = is_overcurrented ? 0 : 1; @@ -371,7 +362,6 @@ const struct charger_config_t chg_chips[] = { }, }; - const int usb_port_enable[USB_PORT_COUNT] = { GPIO_EN_USB_A0_5V, GPIO_EN_USB_A1_5V, @@ -393,7 +383,6 @@ static void baseboard_chipset_resume(void) { /* Allow display backlight to turn on. See above backlight comment */ gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0); - } DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); @@ -469,17 +458,16 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 95% negotiated limit, * to account for the charger chip margin. */ charge_ma = charge_ma * 95 / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /* Keyboard scan setting */ @@ -513,19 +501,19 @@ __override struct keyboard_scan_config keyscan_config = { * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. */ static const struct thermistor_data_pair thermistor_data[] = { - { 2761 / THERMISTOR_SCALING_FACTOR, 0}, - { 2492 / THERMISTOR_SCALING_FACTOR, 10}, - { 2167 / THERMISTOR_SCALING_FACTOR, 20}, - { 1812 / THERMISTOR_SCALING_FACTOR, 30}, - { 1462 / THERMISTOR_SCALING_FACTOR, 40}, - { 1146 / THERMISTOR_SCALING_FACTOR, 50}, - { 878 / THERMISTOR_SCALING_FACTOR, 60}, - { 665 / THERMISTOR_SCALING_FACTOR, 70}, - { 500 / THERMISTOR_SCALING_FACTOR, 80}, - { 434 / THERMISTOR_SCALING_FACTOR, 85}, - { 376 / THERMISTOR_SCALING_FACTOR, 90}, - { 326 / THERMISTOR_SCALING_FACTOR, 95}, - { 283 / THERMISTOR_SCALING_FACTOR, 100} + { 2761 / THERMISTOR_SCALING_FACTOR, 0 }, + { 2492 / THERMISTOR_SCALING_FACTOR, 10 }, + { 2167 / THERMISTOR_SCALING_FACTOR, 20 }, + { 1812 / THERMISTOR_SCALING_FACTOR, 30 }, + { 1462 / THERMISTOR_SCALING_FACTOR, 40 }, + { 1146 / THERMISTOR_SCALING_FACTOR, 50 }, + { 878 / THERMISTOR_SCALING_FACTOR, 60 }, + { 665 / THERMISTOR_SCALING_FACTOR, 70 }, + { 500 / THERMISTOR_SCALING_FACTOR, 80 }, + { 434 / THERMISTOR_SCALING_FACTOR, 85 }, + { 376 / THERMISTOR_SCALING_FACTOR, 90 }, + { 326 / THERMISTOR_SCALING_FACTOR, 95 }, + { 283 / THERMISTOR_SCALING_FACTOR, 100 } }; static const struct thermistor_info thermistor_info = { @@ -537,8 +525,8 @@ static const struct thermistor_info thermistor_info = { static int board_get_temp(int idx, int *temp_k) { /* idx is the sensor index set below in temp_sensors[] */ - int mv = adc_read_channel( - idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER); + int mv = adc_read_channel(idx ? ADC_TEMP_SENSOR_SOC : + ADC_TEMP_SENSOR_CHARGER); int temp_c; if (mv < 0) @@ -550,9 +538,9 @@ static int board_get_temp(int idx, int *temp_k) } const struct temp_sensor_t temp_sensors[] = { - {"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0}, - {"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1}, - {"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0}, + { "Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0 }, + { "SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1 }, + { "CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -655,11 +643,11 @@ __override void lid_angle_peripheral_enable(int enable) static const int sku_thresh_mv[] = { /* Vin = 3.3V, Ideal voltage, R2 values listed below */ /* R1 = 51.1 kOhm */ - 200, /* 124 mV, 2.0 Kohm */ - 366, /* 278 mV, 4.7 Kohm */ - 550, /* 456 mV, 8.2 Kohm */ - 752, /* 644 mV, 12.4 Kohm */ - 927, /* 860 mV, 18.0 Kohm */ + 200, /* 124 mV, 2.0 Kohm */ + 366, /* 278 mV, 4.7 Kohm */ + 550, /* 456 mV, 8.2 Kohm */ + 752, /* 644 mV, 12.4 Kohm */ + 927, /* 860 mV, 18.0 Kohm */ 1073, /* 993 mV, 22.0 Kohm */ 1235, /* 1152 mV, 27.4 Kohm */ 1386, /* 1318 mV, 34.0 Kohm */ @@ -706,10 +694,9 @@ static uint32_t board_get_adc_sku_id(void) static int board_get_gpio_board_version(void) { - return - (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | - (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | - (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); + return (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | + (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | + (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); } static int board_version; @@ -767,8 +754,8 @@ int board_is_convertible(void) /* Kasumi360: 82 */ /* Treeya360: a8-af, be, bf*/ return (sku_id == 6 || sku_id == 82 || - ((sku_id >= 0xa8) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf); + ((sku_id >= 0xa8) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf); } int board_is_lid_angle_tablet_mode(void) @@ -782,13 +769,11 @@ __override uint32_t board_override_feature_flags0(uint32_t flags0) * Remove keyboard backlight feature for devices that don't support it. * All Treeya and Treeya360 models do not support keyboard backlight. */ - if (sku_id == 16 || sku_id == 17 || - sku_id == 20 || sku_id == 21 || - sku_id == 32 || sku_id == 33 || - sku_id == 40 || sku_id == 41 || + if (sku_id == 16 || sku_id == 17 || sku_id == 20 || sku_id == 21 || + sku_id == 32 || sku_id == 33 || sku_id == 40 || sku_id == 41 || sku_id == 44 || sku_id == 45 || - ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || - sku_id == 0xbe || sku_id == 0xbf) + ((sku_id >= 0xa0) && (sku_id <= 0xaf)) || sku_id == 0xbe || + sku_id == 0xbf) return (flags0 & ~EC_FEATURE_MASK_0(EC_FEATURE_PWM_KEYB)); else return flags0; -- cgit v1.2.1 From f7a180d6ab042645d9b0bf40ac682d83697c2da5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:47 -0600 Subject: zephyr/subsys/ap_pwrseq/power_host_sleep.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c6295cc0e2d4fec8def18afe4eb44e6fd14bf39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730932 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/power_host_sleep.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/power_host_sleep.c b/zephyr/subsys/ap_pwrseq/power_host_sleep.c index ff512fa941..4e05d730de 100644 --- a/zephyr/subsys/ap_pwrseq/power_host_sleep.c +++ b/zephyr/subsys/ap_pwrseq/power_host_sleep.c @@ -11,8 +11,9 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); #if CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI /* If host doesn't program S0ix lazy wake mask, use default S0ix mask */ -#define DEFAULT_WAKE_MASK_S0IX (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define DEFAULT_WAKE_MASK_S0IX \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) /* * Set the wake mask according to the current power state: @@ -33,7 +34,7 @@ void power_update_wake_mask(void) if (state == SYS_POWER_STATE_S0) wake_mask = 0; else if (lpc_is_active_wm_set_by_host() || - ap_power_get_lazy_wake_mask(state, &wake_mask)) + ap_power_get_lazy_wake_mask(state, &wake_mask)) return; #if CONFIG_AP_PWRSEQ_S0IX if ((state == SYS_POWER_STATE_S0ix) && (wake_mask == 0)) @@ -48,8 +49,8 @@ static void power_update_wake_mask_deferred(struct k_work *work) power_update_wake_mask(); } -static K_WORK_DELAYABLE_DEFINE( - power_update_wake_mask_deferred_data, power_update_wake_mask_deferred); +static K_WORK_DELAYABLE_DEFINE(power_update_wake_mask_deferred_data, + power_update_wake_mask_deferred); void ap_power_set_active_wake_mask(void) { @@ -74,14 +75,16 @@ void ap_power_set_active_wake_mask(void) * has changed again and the work is not processed, we should * reschedule it. */ - rv = k_work_reschedule( - &power_update_wake_mask_deferred_data, K_MSEC(5)); + rv = k_work_reschedule(&power_update_wake_mask_deferred_data, + K_MSEC(5)); } __ASSERT(rv >= 0, "Set wake mask work queue error"); } #else /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */ -static void ap_power_set_active_wake_mask(void) { } +static void ap_power_set_active_wake_mask(void) +{ +} #endif /* CONFIG_PLATFORM_EC_HOST_INTERFACE_ESPI */ #if CONFIG_AP_PWRSEQ_S0IX @@ -183,8 +186,8 @@ void ap_power_sleep_notify_transition(enum ap_power_sleep_type check_state) void ap_power_reset_host_sleep_state(void) { power_set_host_sleep_state(HOST_SLEEP_EVENT_DEFAULT_RESET); - ap_power_chipset_handle_host_sleep_event( - HOST_SLEEP_EVENT_DEFAULT_RESET, NULL); + ap_power_chipset_handle_host_sleep_event(HOST_SLEEP_EVENT_DEFAULT_RESET, + NULL); } /* TODO: hook to reset event */ @@ -195,13 +198,11 @@ void ap_power_handle_chipset_reset(void) } void ap_power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) + enum host_sleep_event state, struct host_sleep_event_context *ctx) { LOG_DBG("host sleep event = %d!", state); #if CONFIG_AP_PWRSEQ_S0IX if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) { - /* * Indicate to power state machine that a new host event for * s0ix/s3 suspend has been received and so chipset suspend -- cgit v1.2.1 From 131c5c6204915421d4b8b05f76827e454ab27241 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:21 -0600 Subject: board/endeavour/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia345747543798b9a29935ac8a15cc070cad5c871 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728293 Reviewed-by: Jeremy Bettis --- board/endeavour/board.h | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/board/endeavour/board.h b/board/endeavour/board.h index 9b0107b2c4..b7d50e3fef 100644 --- a/board/endeavour/board.h +++ b/board/endeavour/board.h @@ -12,7 +12,7 @@ * Allow dangerous commands. * TODO: Remove this config before production. */ -#undef CONFIG_SYSTEM_UNLOCKED +#undef CONFIG_SYSTEM_UNLOCKED #define CONFIG_USB_PD_COMM_LOCKED /* EC */ @@ -31,7 +31,7 @@ #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_POWER_BUTTON_IGNORE_LID #define CONFIG_PWM #define CONFIG_LTO @@ -64,7 +64,7 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 @@ -82,18 +82,18 @@ #define USB_PORT_COUNT 4 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_PSE NPCX_I2C_PORT0_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 +#define I2C_PORT_PSE NPCX_I2C_PORT0_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_VBOOT_HASH #define CONFIG_VSTORE @@ -109,15 +109,12 @@ enum charge_port { }; enum temp_sensor_id { - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ TEMP_SENSOR_COUNT }; -enum adc_channel { - ADC_VBUS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_LED_RED, -- cgit v1.2.1 From 697ca60c7b2eaff89862fcbe04b6def22f38a6a1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:46 -0600 Subject: board/akemi/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I754d1a914192506a402cf8e5434808cf153fa972 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727978 Reviewed-by: Jeremy Bettis --- board/akemi/board.h | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/board/akemi/board.h b/board/akemi/board.h index caf1a39147..c7eab2f48f 100644 --- a/board/akemi/board.h +++ b/board/akemi/board.h @@ -102,16 +102,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -119,8 +119,8 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ ADC_CH_COUNT }; @@ -131,11 +131,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, -- cgit v1.2.1 From 0492b8da2f4dfbaf5c1f2c444d4a3c2c3bc7385b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:38 -0600 Subject: core/nds32/task.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I69924b6d7f3d8540dd76d6ec9132c05272a36d80 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729866 Reviewed-by: Jeremy Bettis --- core/nds32/task.c | 122 ++++++++++++++++++++++++------------------------------ 1 file changed, 55 insertions(+), 67 deletions(-) diff --git a/core/nds32/task.c b/core/nds32/task.c index 5fc86d6050..f7b5674085 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -24,10 +24,10 @@ typedef union { * Note that sp must be the first element in the task struct * for __switchto() to work. */ - uint32_t sp; /* Saved stack pointer for context switch */ - atomic_t events; /* Bitmaps of received events */ - uint64_t runtime; /* Time spent in task */ - uint32_t *stack; /* Start of stack */ + uint32_t sp; /* Saved stack pointer for context switch */ + atomic_t events; /* Bitmaps of received events */ + uint64_t runtime; /* Time spent in task */ + uint32_t *stack; /* Start of stack */ }; } task_; @@ -42,11 +42,9 @@ CONFIG_TEST_TASK_LIST #undef TASK /* Task names for easier debugging */ -#define TASK(n, r, d, s) #n, -static const char * const task_names[] = { - "<< idle >>", - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST +#define TASK(n, r, d, s) #n, +static const char *const task_names[] = { + "<< idle >>", CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK @@ -54,12 +52,12 @@ static const char * const task_names[] = { static int task_will_switch; static uint32_t exc_sub_time; static uint64_t task_start_time; /* Time task scheduling started */ -static uint32_t exc_start_time; /* Time of task->exception transition */ -static uint32_t exc_end_time; /* Time of exception->task transition */ -static uint64_t exc_total_time; /* Total time in exceptions */ -static uint32_t svc_calls; /* Number of service calls */ -static uint32_t task_switches; /* Number of times active task changed */ -static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ +static uint32_t exc_start_time; /* Time of task->exception transition */ +static uint32_t exc_end_time; /* Time of exception->task transition */ +static uint64_t exc_total_time; /* Total time in exceptions */ +static uint32_t svc_calls; /* Number of service calls */ +static uint32_t task_switches; /* Number of times active task changed */ +static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif extern int __task_start(void); @@ -80,7 +78,7 @@ void __idle(void) /* doze mode */ IT83XX_ECPM_PLLCTRL = EC_PLL_DOZE; #endif - asm volatile ("dsb"); + asm volatile("dsb"); /* * Wait for the next irq event. This stops the CPU clock * (sleep / deep sleep, depending on chip config). @@ -100,20 +98,18 @@ static void task_exit_trap(void) } /* Startup parameters for all tasks. */ -#define TASK(n, r, d, s) { \ - .r0 = (uint32_t)d, \ - .pc = (uint32_t)r, \ - .stack_size = s, \ -}, +#define TASK(n, r, d, s) \ + { \ + .r0 = (uint32_t)d, \ + .pc = (uint32_t)r, \ + .stack_size = s, \ + }, static const struct { uint32_t r0; uint32_t pc; uint16_t stack_size; -} tasks_init[] = { - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -}; +} tasks_init[] = { TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST }; #undef TASK /* Contexts for all tasks */ @@ -122,20 +118,16 @@ static task_ tasks[TASK_ID_COUNT]; BUILD_ASSERT(TASK_ID_COUNT <= sizeof(unsigned) * 8); BUILD_ASSERT(TASK_ID_COUNT < (1 << (sizeof(task_id_t) * 8))); - /* Stacks for all tasks */ -#define TASK(n, r, d, s) + s -uint8_t task_stacks[0 - TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) - CONFIG_TASK_LIST - CONFIG_TEST_TASK_LIST -] __aligned(8); +#define TASK(n, r, d, s) +s +uint8_t task_stacks[0 TASK(IDLE, __idle, 0, IDLE_TASK_STACK_SIZE) + CONFIG_TASK_LIST CONFIG_TEST_TASK_LIST] __aligned(8); #undef TASK /* Reserve space to discard context on first context switch. */ -uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] __attribute__ - ((section(".bss.task_scratchpad"))); +uint32_t scratchpad[TASK_SCRATCHPAD_SIZE] + __attribute__((section(".bss.task_scratchpad"))); task_ *current_task = (task_ *)scratchpad; @@ -167,7 +159,7 @@ static atomic_t tasks_ready = BIT(TASK_ID_HOOKS); */ static atomic_t tasks_enabled = BIT(TASK_ID_HOOKS) | BIT(TASK_ID_IDLE); -int start_called; /* Has task swapping started */ +int start_called; /* Has task swapping started */ /* interrupt number of sw interrupt */ static int sw_int_num; @@ -213,22 +205,22 @@ void __ram_code interrupt_disable(void) { /* Mask all interrupts, only keep division by zero exception */ uint32_t val = BIT(30); - asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); - asm volatile ("dsb"); + asm volatile("mtsr %0, $INT_MASK" : : "r"(val)); + asm volatile("dsb"); } void __ram_code interrupt_enable(void) { /* Enable HW2 ~ HW15 and division by zero exception interrupts */ uint32_t val = (BIT(30) | 0xFFFC); - asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); + asm volatile("mtsr %0, $INT_MASK" : : "r"(val)); } inline bool is_interrupt_enabled(void) { uint32_t val = 0; - asm volatile ("mfsr %0, $INT_MASK" : "=r"(val)); + asm volatile("mfsr %0, $INT_MASK" : "=r"(val)); /* Interrupts are enabled if any of HW2 ~ HW15 is enabled */ return val & 0xFFFC; @@ -267,7 +259,7 @@ int task_start_called(void) * Also includes emulation of software triggering interrupt vector */ void __ram_code __keep syscall_handler(int desched, task_id_t resched, - int swirq) + int swirq) { /* are we emulating an interrupt ? */ if (swirq) { @@ -307,7 +299,7 @@ task_ *next_sched_task(void) #ifdef CONFIG_TASK_PROFILING if (current_task != new_task) { current_task->runtime += - (exc_start_time - exc_end_time - exc_sub_time); + (exc_start_time - exc_end_time - exc_sub_time); task_will_switch = 1; } #endif @@ -348,7 +340,7 @@ volatile int ec_int; void __ram_code start_irq_handler(void) { /* save r0, r1, and r2 for syscall */ - asm volatile ("smw.adm $r0, [$sp], $r2, 0"); + asm volatile("smw.adm $r0, [$sp], $r2, 0"); /* If this is a SW interrupt */ if (get_itype() & 8) ec_int = sw_int_num; @@ -369,7 +361,7 @@ void __ram_code start_irq_handler(void) irq_dist[ec_int]++; #endif /* restore r0, r1, and r2 */ - asm volatile ("lmw.bim $r0, [$sp], $r2, 0"); + asm volatile("lmw.bim $r0, [$sp], $r2, 0"); } void end_irq_handler(void) @@ -380,7 +372,7 @@ void end_irq_handler(void) * save r0 and fp (fp for restore r0-r5, r15, fp, lp and sp * while interrupt exit. */ - asm volatile ("smw.adm $r0, [$sp], $r0, 8"); + asm volatile("smw.adm $r0, [$sp], $r0, 8"); t = get_time().le.lo; p = t - exc_start_time; @@ -395,7 +387,7 @@ void end_irq_handler(void) } /* restore r0 and fp */ - asm volatile ("lmw.bim $r0, [$sp], $r0, 8"); + asm volatile("lmw.bim $r0, [$sp], $r0, 8"); #endif } @@ -483,37 +475,36 @@ uint32_t __ram_code read_clear_int_mask(void) { uint32_t int_mask, int_dis = BIT(30); - asm volatile( - "mfsr %0, $INT_MASK\n\t" - "mtsr %1, $INT_MASK\n\t" - "dsb\n\t" - : "=&r"(int_mask) - : "r"(int_dis)); + asm volatile("mfsr %0, $INT_MASK\n\t" + "mtsr %1, $INT_MASK\n\t" + "dsb\n\t" + : "=&r"(int_mask) + : "r"(int_dis)); return int_mask; } void __ram_code set_int_mask(uint32_t val) { - asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); + asm volatile("mtsr %0, $INT_MASK" : : "r"(val)); } static void set_int_priority(uint32_t val) { - asm volatile ("mtsr %0, $INT_PRI" : : "r"(val)); + asm volatile("mtsr %0, $INT_PRI" : : "r"(val)); } uint32_t get_int_ctrl(void) { uint32_t ret; - asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret)); + asm volatile("mfsr %0, $INT_CTRL" : "=r"(ret)); return ret; } void set_int_ctrl(uint32_t val) { - asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val)); + asm volatile("mtsr %0, $INT_CTRL" : : "r"(val)); } void task_enable_all_tasks(void) @@ -599,7 +590,7 @@ static void ivic_init_irqs(void) for (i = 0; i < exc_calls; i++) { uint8_t irq = __irqprio[i].irq; uint8_t prio = __irqprio[i].priority; - all_priorities |= (prio & 0x3) << (irq * 2); + all_priorities |= (prio & 0x3) << (irq * 2); } set_int_priority(all_priorities); } @@ -715,9 +706,7 @@ static int command_task_info(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, - NULL, - "Print task info"); +DECLARE_CONSOLE_COMMAND(taskinfo, command_task_info, NULL, "Print task info"); static int command_task_ready(int argc, char **argv) { @@ -731,8 +720,7 @@ static int command_task_ready(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, - "[setmask]", +DECLARE_CONSOLE_COMMAND(taskready, command_task_ready, "[setmask]", "Print/set ready tasks"); void task_pre_init(void) @@ -755,11 +743,11 @@ void task_pre_init(void) tasks[i].sp = (uint32_t)sp; /* Initial context on stack (see __switchto()) */ - sp[7] = tasks_init[i].r0; /* r0 */ - sp[15] = (uint32_t)task_exit_trap; /* lr */ - sp[1] = tasks_init[i].pc; /* pc */ - sp[0] = 0x70009; /* psw */ - sp[16] = (uint32_t)(sp + 17); /* sp */ + sp[7] = tasks_init[i].r0; /* r0 */ + sp[15] = (uint32_t)task_exit_trap; /* lr */ + sp[1] = tasks_init[i].pc; /* pc */ + sp[0] = 0x70009; /* psw */ + sp[16] = (uint32_t)(sp + 17); /* sp */ /* Fill unused stack; also used to detect stack overflow. */ for (sp = stack_next; sp < (uint32_t *)tasks[i].sp; sp++) -- cgit v1.2.1 From df07c03f78e8c17d0a5fd2bb3303e98051d5918c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:44 -0600 Subject: chip/mec1322/config_flash_layout.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12c43e209f6e2a05f09dacc1dd4864f7313610b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729316 Reviewed-by: Jeremy Bettis --- chip/mec1322/config_flash_layout.h | 40 ++++++++++++++++++-------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h index a5b064b8cc..ae56b49226 100644 --- a/chip/mec1322/config_flash_layout.h +++ b/chip/mec1322/config_flash_layout.h @@ -16,51 +16,49 @@ /* Non-memmapped, external SPI */ #define CONFIG_EXTERNAL_STORAGE -#undef CONFIG_MAPPED_STORAGE -#undef CONFIG_FLASH_PSTATE +#undef CONFIG_MAPPED_STORAGE +#undef CONFIG_FLASH_PSTATE #define CONFIG_SPI_FLASH /* EC region of SPI resides at end of ROM, protected region follows writable */ -#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x20000) #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 -#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) -#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_FLASH_SIZE_BYTES - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 /* Loader resides at the beginning of program memory */ -#define CONFIG_LOADER_MEM_OFF 0 -#define CONFIG_LOADER_SIZE 0xC00 +#define CONFIG_LOADER_MEM_OFF 0 +#define CONFIG_LOADER_SIZE 0xC00 /* Write protect Loader and RO Image */ -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF /* * Write protect 128k section of 256k physical flash which contains loader * and RO Images. */ -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * RO / RW images follow the loader in program memory. Either RO or RW * image will be loaded -- both cannot be loaded at the same time. */ -#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \ - CONFIG_LOADER_SIZE) -#define CONFIG_RO_SIZE (97 * 1024) -#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF -#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + CONFIG_LOADER_SIZE) +#define CONFIG_RO_SIZE (97 * 1024) +#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF +#define CONFIG_RW_SIZE CONFIG_RO_SIZE /* WP region consists of second half of SPI, and begins with the boot header */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 -#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 /* Loader / lfw image immediately follows the boot header on SPI */ -#define CONFIG_LOADER_STORAGE_OFF (CONFIG_BOOT_HEADER_STORAGE_OFF + \ - CONFIG_BOOT_HEADER_STORAGE_SIZE) +#define CONFIG_LOADER_STORAGE_OFF \ + (CONFIG_BOOT_HEADER_STORAGE_OFF + CONFIG_BOOT_HEADER_STORAGE_SIZE) /* RO image immediately follows the loader image */ -#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + \ - CONFIG_LOADER_SIZE) +#define CONFIG_RO_STORAGE_OFF (CONFIG_LOADER_STORAGE_OFF + CONFIG_LOADER_SIZE) /* RW image starts at the beginning of SPI */ -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ -- cgit v1.2.1 From 844866841f0784c0ddc4ef5b2fcb428ecefa9bc6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:20 -0600 Subject: board/moonbuggy/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92a6603d3b9f0a20a33f66e21b40bb116402b615 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728697 Reviewed-by: Jeremy Bettis --- board/moonbuggy/board.h | 85 ++++++++++++++++++++++++------------------------- 1 file changed, 41 insertions(+), 44 deletions(-) diff --git a/board/moonbuggy/board.h b/board/moonbuggy/board.h index b5e8424230..996ad95f05 100644 --- a/board/moonbuggy/board.h +++ b/board/moonbuggy/board.h @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -119,12 +119,12 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_PSE NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_PSE NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -134,11 +134,11 @@ #include "registers.h" enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -163,10 +163,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT }; /* Board specific handlers */ void led_alert(int enable); @@ -182,20 +179,20 @@ void ads_12v_interrupt(enum gpio_signal signal); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) unsigned int ec_config_get_thermal_solution(void); @@ -203,30 +200,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 82c31722f805b2951996031bdb5faf1f1e381c28 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:48 -0600 Subject: chip/npcx/lct.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id479441788e2b98c125f2dd7c78a9c17153ff315 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729407 Reviewed-by: Jeremy Bettis --- chip/npcx/lct.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/chip/npcx/lct.c b/chip/npcx/lct.c index e23fa3bf6a..0770b5e9e2 100644 --- a/chip/npcx/lct.c +++ b/chip/npcx/lct.c @@ -13,10 +13,10 @@ #include "timer.h" #include "util.h" -#define LCT_CLK_ENABLE_DELAY_USEC 150 +#define LCT_CLK_ENABLE_DELAY_USEC 150 -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) void npcx_lct_sel_power_src(enum NPCX_LCT_PWR_SRC pwr_src) { @@ -93,7 +93,6 @@ void npcx_lct_config(int seconds, int psl_ena, int int_ena) if (int_ena) SET_BIT(NPCX_LCTCONT, NPCX_LCTCONT_EVEN); - } uint32_t npcx_lct_get_time(void) @@ -102,21 +101,17 @@ uint32_t npcx_lct_get_time(void) uint8_t week, day, hour, minute; do { - week = NPCX_LCTWEEK; - day = NPCX_LCTDAY; - hour = NPCX_LCTHOUR; + week = NPCX_LCTWEEK; + day = NPCX_LCTDAY; + hour = NPCX_LCTHOUR; minute = NPCX_LCTMINUTE; second = NPCX_LCTSECOND; - } while (week != NPCX_LCTWEEK || - day != NPCX_LCTDAY || - hour != NPCX_LCTHOUR || - minute != NPCX_LCTMINUTE || + } while (week != NPCX_LCTWEEK || day != NPCX_LCTDAY || + hour != NPCX_LCTHOUR || minute != NPCX_LCTMINUTE || second != NPCX_LCTSECOND); - second += minute * SECS_PER_MINUTE + - hour * SECS_PER_HOUR + - day * SECS_PER_DAY + - week * SECS_PER_WEEK; + second += minute * SECS_PER_MINUTE + hour * SECS_PER_HOUR + + day * SECS_PER_DAY + week * SECS_PER_WEEK; return second; } @@ -164,9 +159,9 @@ static int command_lctalarm(int argc, char **argv) npcx_lct_config(seconds, 0, 1); task_disable_irq(NPCX_IRQ_LCT_WKINTF_2); /* Enable wake-up input sources & clear pending bit */ - NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKPCL(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; NPCX_WKINEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; - NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; + NPCX_WKEN(MIWU_TABLE_2, LCT_WUI_GROUP) |= LCT_WUI_MASK; task_enable_irq(NPCX_IRQ_LCT_WKINTF_2); npcx_lct_enable(1); -- cgit v1.2.1 From f377f91196da926efef4eb39e18dd915ab9be2d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:47 -0600 Subject: board/casta/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibdae3b275aaecbfce1e751c6f5e3a44ec8f06ccc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728116 Reviewed-by: Jeremy Bettis --- board/casta/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/casta/board.h b/board/casta/board.h index c8f4f7b1e7..c5ba310446 100644 --- a/board/casta/board.h +++ b/board/casta/board.h @@ -74,8 +74,8 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ ADC_CH_COUNT }; -- cgit v1.2.1 From acc1c3b2476f3fc3d4086e4e5f6b1eede2f01743 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:08 -0600 Subject: common/vboot/vboot.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie5aaadffbdb78ed30164338e58011c6893555994 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729808 Reviewed-by: Jeremy Bettis --- common/vboot/vboot.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/common/vboot/vboot.c b/common/vboot/vboot.c index 910156335d..2a528a57db 100644 --- a/common/vboot/vboot.c +++ b/common/vboot/vboot.c @@ -25,8 +25,8 @@ #include "vboot.h" #include "vb21_struct.h" -#define CPRINTS(format, args...) cprints(CC_VBOOT,"VB " format, ## args) -#define CPRINTF(format, args...) cprintf(CC_VBOOT,"VB " format, ## args) +#define CPRINTS(format, args...) cprints(CC_VBOOT, "VB " format, ##args) +#define CPRINTF(format, args...) cprintf(CC_VBOOT, "VB " format, ##args) static int has_matrix_keyboard(void) { @@ -45,34 +45,34 @@ static int verify_slot(enum ec_image slot) CPRINTS("Verifying %s", ec_image_to_string(slot)); - vb21_key = (const struct vb21_packed_key *)( - CONFIG_MAPPED_STORAGE_BASE + - CONFIG_EC_PROTECTED_STORAGE_OFF + - CONFIG_RO_PUBKEY_STORAGE_OFF); + vb21_key = + (const struct vb21_packed_key *)(CONFIG_MAPPED_STORAGE_BASE + + CONFIG_EC_PROTECTED_STORAGE_OFF + + CONFIG_RO_PUBKEY_STORAGE_OFF); rv = vb21_is_packed_key_valid(vb21_key); if (rv) { CPRINTS("Invalid key (%d)", rv); return EC_ERROR_VBOOT_KEY; } - key = (const struct rsa_public_key *) - ((const uint8_t *)vb21_key + vb21_key->key_offset); + key = (const struct rsa_public_key *)((const uint8_t *)vb21_key + + vb21_key->key_offset); if (slot == EC_IMAGE_RW_A) { data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + - CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_A_STORAGE_OFF); - vb21_sig = (const struct vb21_signature *)( - CONFIG_MAPPED_STORAGE_BASE + - CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_A_SIGN_STORAGE_OFF); + CONFIG_EC_WRITABLE_STORAGE_OFF + + CONFIG_RW_A_STORAGE_OFF); + vb21_sig = (const struct vb21_signature + *)(CONFIG_MAPPED_STORAGE_BASE + + CONFIG_EC_WRITABLE_STORAGE_OFF + + CONFIG_RW_A_SIGN_STORAGE_OFF); } else { data = (const uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + - CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_STORAGE_OFF); - vb21_sig = (const struct vb21_signature *)( - CONFIG_MAPPED_STORAGE_BASE + - CONFIG_EC_WRITABLE_STORAGE_OFF + - CONFIG_RW_B_SIGN_STORAGE_OFF); + CONFIG_EC_WRITABLE_STORAGE_OFF + + CONFIG_RW_B_STORAGE_OFF); + vb21_sig = (const struct vb21_signature + *)(CONFIG_MAPPED_STORAGE_BASE + + CONFIG_EC_WRITABLE_STORAGE_OFF + + CONFIG_RW_B_SIGN_STORAGE_OFF); } rv = vb21_is_signature_valid(vb21_sig, vb21_key); -- cgit v1.2.1 From 141dfba6da857728d7136e3a564c9c807456ec9a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:26 -0600 Subject: zephyr/projects/nissa/src/sub_board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idde4bda55570915c2696344369fddaa39877d8b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730798 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/sub_board.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c index 2a3333bab9..dac4cae0e0 100644 --- a/zephyr/projects/nissa/src/sub_board.c +++ b/zephyr/projects/nissa/src/sub_board.c @@ -66,7 +66,7 @@ static void hdmi_hpd_interrupt(const struct device *device, } static void lte_power_handler(struct ap_power_ev_callback *cb, - struct ap_power_ev_data data) + struct ap_power_ev_data data) { /* Enable rails for S5 */ const struct gpio_dt_spec *s5_rail = @@ -105,20 +105,18 @@ static void nereid_subboard_config(void) */ if (sb == NISSA_SB_C_A || sb == NISSA_SB_HDMI_A) { /* Configure VBUS enable, default off */ - gpio_pin_configure_dt( - GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), - GPIO_OUTPUT_LOW); + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), + GPIO_OUTPUT_LOW); } else { /* Turn off unused pins */ gpio_pin_configure_dt( GPIO_DT_FROM_NODELABEL(gpio_sub_usb_a1_ilimit_sdp), GPIO_DISCONNECTED); - gpio_pin_configure_dt( - GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), - GPIO_DISCONNECTED); + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_usb_a1_vbus), + GPIO_DISCONNECTED); /* Disable second USB-A port enable GPIO */ __ASSERT(USB_PORT_ENABLE_COUNT == 2, - "USB A port count != 2 (%d)", USB_PORT_ENABLE_COUNT); + "USB A port count != 2 (%d)", USB_PORT_ENABLE_COUNT); usb_port_enable[1] = -1; } /* @@ -127,9 +125,8 @@ static void nereid_subboard_config(void) */ if (sb == NISSA_SB_C_A || sb == NISSA_SB_C_LTE) { /* Configure interrupt input */ - gpio_pin_configure_dt( - GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), - GPIO_INPUT | GPIO_PULL_UP); + gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl), + GPIO_INPUT | GPIO_PULL_UP); } else { /* Disable the port 1 charger task */ task_disable_task(TASK_ID_USB_CHG_P1); @@ -197,9 +194,9 @@ static void nereid_subboard_config(void) /* Control LTE power when CPU entering or * exiting S5 state. */ - ap_power_ev_init_callback( - &power_cb, lte_power_handler, - AP_POWER_SHUTDOWN | AP_POWER_PRE_INIT); + ap_power_ev_init_callback(&power_cb, lte_power_handler, + AP_POWER_SHUTDOWN | + AP_POWER_PRE_INIT); ap_power_ev_add_callback(&power_cb); break; -- cgit v1.2.1 From 595cac322979f9ac8551e314f2342f505d7fe239 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:00 -0600 Subject: include/power/meteorlake.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94aaa2d7a8998a1972ac092b9cf3f5ae82df0466 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730388 Reviewed-by: Jeremy Bettis --- include/power/meteorlake.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/power/meteorlake.h b/include/power/meteorlake.h index 2e8792de20..1d4b59a701 100644 --- a/include/power/meteorlake.h +++ b/include/power/meteorlake.h @@ -11,11 +11,11 @@ #include "stdbool.h" /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_RSMRST_L_PGOOD) -- cgit v1.2.1 From 3df35c400b19625b65707fbefe44088ab7a9b19d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:41 -0600 Subject: board/dojo/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4489ca95b446dc9e8708819accb49e5936f8c4c7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728249 Reviewed-by: Jeremy Bettis --- board/dojo/battery.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/dojo/battery.c b/board/dojo/battery.c index 290bf6067c..40d1290309 100644 --- a/board/dojo/battery.c +++ b/board/dojo/battery.c @@ -178,19 +178,18 @@ int charger_profile_override(struct charge_state_data *curr) chg_temp = K_TO_C(chg_temp); prev_chg_lvl = chg_lvl; - if (chg_temp <= temp_chg_table[chg_lvl].lo_thre && - chg_lvl > 0) + if (chg_temp <= temp_chg_table[chg_lvl].lo_thre && chg_lvl > 0) chg_lvl--; else if (chg_temp >= temp_chg_table[chg_lvl].hi_thre && - chg_lvl < CHG_LEVEL_COUNT - 1) + chg_lvl < CHG_LEVEL_COUNT - 1) chg_lvl++; curr->requested_current = MIN(curr->requested_current, - temp_chg_table[chg_lvl].chg_curr); + temp_chg_table[chg_lvl].chg_curr); - if(chg_lvl != prev_chg_lvl) + if (chg_lvl != prev_chg_lvl) ccprints("Override chg curr to %dmA by chg LEVEL_%d", - curr->requested_current, chg_lvl); + curr->requested_current, chg_lvl); } return 0; -- cgit v1.2.1 From 9e61f21ea31dfdadd710de3e0476da8daf85a5e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:34 -0600 Subject: common/cec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic14c59460d83eb00f8ceb77661eb6512ccfff379 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729613 Reviewed-by: Jeremy Bettis --- common/cec.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/common/cec.c b/common/cec.c index 1bc3273c1d..c487e51b16 100644 --- a/common/cec.c +++ b/common/cec.c @@ -7,8 +7,8 @@ #include "console.h" #include "task.h" -#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args) /* * Mutex for the read-offset of the rx queue. Needed since the @@ -75,7 +75,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg, queue->buf[offset] = 0; offset = (offset + 1) % CEC_RX_BUFFER_SIZE; - for (i = 0 ; i < msg_len; i++) { + for (i = 0; i < msg_len; i++) { if (offset == queue->read_offset) { /* Buffer full */ return EC_ERROR_OVERFLOW; @@ -101,8 +101,7 @@ int cec_rx_queue_push(struct cec_rx_queue *queue, const uint8_t *msg, return EC_SUCCESS; } -int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg, - uint8_t *msg_len) +int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg, uint8_t *msg_len) { int i; @@ -126,9 +125,8 @@ int cec_rx_queue_pop(struct cec_rx_queue *queue, uint8_t *msg, queue->read_offset = (queue->read_offset + 1) % CEC_RX_BUFFER_SIZE; for (i = 0; i < *msg_len; i++) { msg[i] = queue->buf[queue->read_offset]; - queue->read_offset = (queue->read_offset + 1) % - CEC_RX_BUFFER_SIZE; - + queue->read_offset = + (queue->read_offset + 1) % CEC_RX_BUFFER_SIZE; } mutex_unlock(&rx_queue_readoffset_mutex); -- cgit v1.2.1 From 68278a8cf2e8e568193be17b45d700156b00588b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:34 -0600 Subject: driver/usb_mux/pi3usb3x532.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85f9b6ec694c8a062f3381c246588e4366428cb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730164 Reviewed-by: Jeremy Bettis --- driver/usb_mux/pi3usb3x532.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/usb_mux/pi3usb3x532.h b/driver/usb_mux/pi3usb3x532.h index 6b398fdace..13537e52f3 100644 --- a/driver/usb_mux/pi3usb3x532.h +++ b/driver/usb_mux/pi3usb3x532.h @@ -70,8 +70,8 @@ * dp0-1 : rx1, tx1 * hpd+/-: rfu2, rfu1 */ -#define PI3USB3X532_MODE_DP_USB_SWAP (PI3USB3X532_MODE_DP_USB | \ - PI3USB3X532_BIT_SWAP) +#define PI3USB3X532_MODE_DP_USB_SWAP \ + (PI3USB3X532_MODE_DP_USB | PI3USB3X532_BIT_SWAP) /* Get Vendor ID */ int pi3usb3x532_check_vendor(const struct usb_mux *me, int *val); -- cgit v1.2.1 From 8e4516c7c3de7a2eb72a02c2788bc0f5bab575de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:42 -0600 Subject: zephyr/projects/skyrim/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I022f465c4de6619f31249b92d2f418a599ee2413 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730804 Reviewed-by: Jeremy Bettis --- zephyr/projects/skyrim/usbc_config.c | 62 +++++++++++++++--------------------- 1 file changed, 25 insertions(+), 37 deletions(-) diff --git a/zephyr/projects/skyrim/usbc_config.c b/zephyr/projects/skyrim/usbc_config.c index c631e92892..873cbdc258 100644 --- a/zephyr/projects/skyrim/usbc_config.c +++ b/zephyr/projects/skyrim/usbc_config.c @@ -32,22 +32,14 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* USB-A ports */ -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; /* USB-C ports */ -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); static void reset_nct38xx_port(int port); @@ -112,7 +104,7 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); * not needed as well. usb_mux.c can handle the situation * properly. */ -static int ioex_set_flip(const struct usb_mux*, mux_state_t, bool *); +static int ioex_set_flip(const struct usb_mux *, mux_state_t, bool *); struct usb_mux_driver ioex_sbu_mux_driver = { .set = ioex_set_flip, }; @@ -132,13 +124,13 @@ struct usb_mux usbc1_sbu_mux = { }; int baseboard_anx7483_c0_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { return anx7483_set_default_tuning(me, mux_state); } int baseboard_anx7483_c1_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; @@ -278,7 +270,7 @@ static void setup_mux(void) if (cros_cbi_get_fw_config(FW_IO_DB, &val) != 0) CPRINTSUSB("Error finding FW_DB_IO in CBI FW_CONFIG"); - /* Val will have our dts default on error, so continue setup */ + /* Val will have our dts default on error, so continue setup */ if (val == FW_IO_DB_PS8811_PS8818) { CPRINTSUSB("C1: Setting PS8818 mux"); @@ -294,8 +286,7 @@ DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int rv; @@ -309,7 +300,7 @@ int board_set_active_charge_port(int port) * ahead and reset it so EN_SNK responds properly. */ if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } @@ -358,7 +349,7 @@ int board_set_active_charge_port(int port) * change because we'll brown out. */ if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { + NCT38XX_BOOT_DEAD_BATTERY) { reset_nct38xx_port(i); pd_set_error_recovery(i); } else { @@ -405,8 +396,7 @@ int board_set_active_charge_port(int port) * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv = EC_SUCCESS; @@ -416,12 +406,11 @@ int board_aoz1380_set_vbus_source_current_limit(int port, return rv; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } void sbu_fault_interrupt(enum gpio_signal signal) @@ -437,9 +426,9 @@ void usb_fault_interrupt(enum gpio_signal signal) int out; CPRINTSUSB("USB fault(%d), alerting the SoC", signal); - out = gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) - && gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) - && + out = gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_hub_fault_q_odl)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a0_fault_odl)) && gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(ioex_usb_a1_fault_db_odl)); gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_fault_odl), out); @@ -511,7 +500,6 @@ static void reset_nct38xx_port(int port) gpio_reset_port(ioex_port1); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -530,16 +518,16 @@ uint16_t tcpc_get_alert_status(void) * its reset line active. */ if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c0_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_0; } if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c1_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_1; } -- cgit v1.2.1 From 380d1637e9240a6d2cfb8b45e4439c675524a9ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:15 -0600 Subject: core/minute-ia/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I977c77cb483c73846e13fbc19234bdd11aea6904 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729856 Reviewed-by: Jeremy Bettis --- core/minute-ia/panic.c | 33 ++++++++++++--------------------- 1 file changed, 12 insertions(+), 21 deletions(-) diff --git a/core/minute-ia/panic.c b/core/minute-ia/panic.c index b4299d9e17..598e0e91bb 100644 --- a/core/minute-ia/panic.c +++ b/core/minute-ia/panic.c @@ -57,13 +57,12 @@ void panic_data_print(const struct panic_data *pdata) else if (pdata->x86.vector <= 20) panic_printf("Reason: %s\n", panic_reason[pdata->x86.vector]); else if (panic_sw_reason_is_valid(pdata->x86.vector)) { - panic_printf("Software panic reason %s\n", - panic_sw_reasons[pdata->x86.vector - - PANIC_SW_BASE]); + panic_printf( + "Software panic reason %s\n", + panic_sw_reasons[pdata->x86.vector - PANIC_SW_BASE]); panic_printf("Software panic info 0x%x\n", pdata->x86.error_code); - } - else + } else panic_printf("Interrupt vector number: 0x%08X (unknown)\n", pdata->x86.vector); panic_printf("\n"); @@ -91,12 +90,8 @@ void panic_data_print(const struct panic_data *pdata) * order pushed to the stack by hardware: see "Intel 64 and IA-32 * Architectures Software Developer's Manual", Volume 3A, Figure 6-4. */ -void exception_panic( - uint32_t vector, - uint32_t error_code, - uint32_t eip, - uint32_t cs, - uint32_t eflags) +void exception_panic(uint32_t vector, uint32_t error_code, uint32_t eip, + uint32_t cs, uint32_t eflags) { /* * If a panic were to occur during the reset procedure, we want @@ -176,26 +171,22 @@ void exception_panic( __builtin_unreachable(); } -noreturn -void software_panic(uint32_t reason, uint32_t info) +noreturn void software_panic(uint32_t reason, uint32_t info) { uint16_t code_segment; /* Get the current code segment */ - __asm__ volatile ("movw %%cs, %0":"=m" (code_segment)); + __asm__ volatile("movw %%cs, %0" : "=m"(code_segment)); - exception_panic(reason, - info, - (uint32_t)__builtin_return_address(0), - code_segment, - 0); + exception_panic(reason, info, (uint32_t)__builtin_return_address(0), + code_segment, 0); __builtin_unreachable(); } void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) { - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); /* Setup panic data structure */ memset(pdata, 0, CONFIG_PANIC_DATA_SIZE); @@ -212,7 +203,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); if (pdata && pdata->struct_version == 2) { *reason = pdata->x86.vector; -- cgit v1.2.1 From 8d04d29ef12c94d58bd3eeaa6af68b4cf5b00627 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:55 -0600 Subject: board/cerise/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b736197bfe8b7bcd52e229f9ae56153b9347cb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728118 Reviewed-by: Jeremy Bettis --- board/cerise/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/cerise/board.h b/board/cerise/board.h index 1cb8cd9266..07736a9dd9 100644 --- a/board/cerise/board.h +++ b/board/cerise/board.h @@ -56,7 +56,7 @@ /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -72,20 +72,20 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 2 -#define I2C_PORT_CHARGER board_get_charger_i2c() -#define I2C_PORT_SENSORS 1 -#define I2C_PORT_KB_DISCRETE 1 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 2 +#define I2C_PORT_CHARGER board_get_charger_i2c() +#define I2C_PORT_SENSORS 1 +#define I2C_PORT_KB_DISCRETE 1 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT -- cgit v1.2.1 From 41d29e221db1ca8715937eaf65c26b3d5d0f182a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:06 -0600 Subject: driver/usb_mux/amd_fp6.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie33a8606cde1b106066b2b14f8d89487ed7b8fb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730154 Reviewed-by: Jeremy Bettis --- driver/usb_mux/amd_fp6.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/driver/usb_mux/amd_fp6.h b/driver/usb_mux/amd_fp6.h index 913903e4c4..51988ab4f6 100644 --- a/driver/usb_mux/amd_fp6.h +++ b/driver/usb_mux/amd_fp6.h @@ -8,24 +8,24 @@ #ifndef __CROS_EC_USB_MUX_AMD_FP6_H #define __CROS_EC_USB_MUX_AMD_FP6_H -#define AMD_FP6_C0_MUX_I2C_ADDR 0x5C -#define AMD_FP6_C4_MUX_I2C_ADDR 0x52 +#define AMD_FP6_C0_MUX_I2C_ADDR 0x5C +#define AMD_FP6_C4_MUX_I2C_ADDR 0x52 -#define AMD_FP6_MUX_MODE_SAFE 0x0 -#define AMD_FP6_MUX_MODE_USB 0x1 -#define AMD_FP6_MUX_MODE_DP 0x2 -#define AMD_FP6_MUX_MODE_DOCK 0x3 -#define AMD_FP6_MUX_MODE_MASK GENMASK(1, 0) +#define AMD_FP6_MUX_MODE_SAFE 0x0 +#define AMD_FP6_MUX_MODE_USB 0x1 +#define AMD_FP6_MUX_MODE_DP 0x2 +#define AMD_FP6_MUX_MODE_DOCK 0x3 +#define AMD_FP6_MUX_MODE_MASK GENMASK(1, 0) -#define AMD_FP6_MUX_ORIENTATION BIT(4) -#define AMD_FP6_MUX_LOW_POWER BIT(5) +#define AMD_FP6_MUX_ORIENTATION BIT(4) +#define AMD_FP6_MUX_LOW_POWER BIT(5) -#define AMD_FP6_MUX_PORT_STATUS_OFFSET 6 -#define AMD_FP6_MUX_PORT_CMD_BUSY 0x0 -#define AMD_FP6_MUX_PORT_CMD_COMPLETE 0x1 -#define AMD_FP6_MUX_PORT_CMD_TIMEOUT 0x2 +#define AMD_FP6_MUX_PORT_STATUS_OFFSET 6 +#define AMD_FP6_MUX_PORT_CMD_BUSY 0x0 +#define AMD_FP6_MUX_PORT_CMD_COMPLETE 0x1 +#define AMD_FP6_MUX_PORT_CMD_TIMEOUT 0x2 -#define AMD_FP6_MUX_PD_STATUS_READY BIT(5) -#define AMD_FP6_MUX_PD_STATUS_OFFSET 1 +#define AMD_FP6_MUX_PD_STATUS_READY BIT(5) +#define AMD_FP6_MUX_PD_STATUS_OFFSET 1 #endif /* __CROS_EC_USB_MUX_AMD_FP6_H */ -- cgit v1.2.1 From ea27f6125aec9a07491e1f1db2d558ece525c79a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:58 -0600 Subject: board/lindar/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If488de700ae02886321ce026d3fbadc6b256a7e4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728637 Reviewed-by: Jeremy Bettis --- board/lindar/led.c | 342 ++++++++++++++++++++++++----------------------------- 1 file changed, 155 insertions(+), 187 deletions(-) diff --git a/board/lindar/led.c b/board/lindar/led.c index 6d602d5c4e..b449cdc265 100644 --- a/board/lindar/led.c +++ b/board/lindar/led.c @@ -23,44 +23,49 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -135,9 +140,8 @@ static void controller_write(uint8_t reg, uint8_t val) buf[0] = reg; buf[1] = val; - i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr, - buf, 2, 0, 0, - I2C_XFER_SINGLE); + i2c_xfer_unlocked(I2C_PORT_LIGHTBAR, ktd2061_i2c_addr, buf, 2, 0, 0, + I2C_XFER_SINGLE); } enum lightbar_states { @@ -187,51 +191,46 @@ struct lightbar_descriptor { uint8_t ticks; }; -#define BAR_INFINITE UINT8_MAX -#define LIGHTBAR_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) +#define BAR_INFINITE UINT8_MAX +#define LIGHTBAR_ONE_SEC (1000 / HOOK_TICK_INTERVAL_MS) #define LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP (3 * LIGHTBAR_ONE_SEC) int lightbar_resume_tick; -const struct lightbar_descriptor - lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = { - [LB_STATE_OFF] = {{BAR_OFF, BAR_INFINITE} }, - [LB_STATE_LID_CLOSE] = {{BAR_OFF, BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_ONLY] = {{BAR_OFF, BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_BAT_LOW] = {{BAR_COLOR_ORG_20_PERCENT, - BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_BAT_LV1] = {{BAR_COLOR_GRN_40_PERCENT, - BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_BAT_LV2] = {{BAR_COLOR_GRN_60_PERCENT, - BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_BAT_LV3] = {{BAR_COLOR_GRN_80_PERCENT, - BAR_INFINITE} }, - [LB_STATE_SLEEP_AC_BAT_LV4] = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} }, - [LB_STATE_SLEEP_BAT_LOW] = {{BAR_OFF, 5 * LIGHTBAR_ONE_SEC}, - {BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC} }, - [LB_STATE_SLEEP_BAT_ONLY] = {{BAR_OFF, BAR_INFINITE} }, - [LB_STATE_S0_AC_ONLY] = {{BAR_OFF, BAR_INFINITE} }, - [LB_STATE_S0_BAT_LOW] = {{BAR_COLOR_ORG_20_PERCENT, - BAR_INFINITE} }, - [LB_STATE_S0_BAT_LV1] = {{BAR_COLOR_GRN_40_PERCENT, - BAR_INFINITE} }, - [LB_STATE_S0_BAT_LV2] = {{BAR_COLOR_GRN_60_PERCENT, - BAR_INFINITE} }, - [LB_STATE_S0_BAT_LV3] = {{BAR_COLOR_GRN_80_PERCENT, - BAR_INFINITE} }, - [LB_STATE_S0_BAT_LV4] = {{BAR_COLOR_GRN_FULL, BAR_INFINITE} }, +const struct lightbar_descriptor lb_table[LB_NUM_STATES][LIGHTBAR_NUM_PHASES] = { + [LB_STATE_OFF] = { { BAR_OFF, BAR_INFINITE } }, + [LB_STATE_LID_CLOSE] = { { BAR_OFF, BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT, + BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT, + BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT, + BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT, + BAR_INFINITE } }, + [LB_STATE_SLEEP_AC_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } }, + [LB_STATE_SLEEP_BAT_LOW] = { { BAR_OFF, 5 * LIGHTBAR_ONE_SEC }, + { BAR_COLOR_ORG_FULL, LIGHTBAR_ONE_SEC } }, + [LB_STATE_SLEEP_BAT_ONLY] = { { BAR_OFF, BAR_INFINITE } }, + [LB_STATE_S0_AC_ONLY] = { { BAR_OFF, BAR_INFINITE } }, + [LB_STATE_S0_BAT_LOW] = { { BAR_COLOR_ORG_20_PERCENT, BAR_INFINITE } }, + [LB_STATE_S0_BAT_LV1] = { { BAR_COLOR_GRN_40_PERCENT, BAR_INFINITE } }, + [LB_STATE_S0_BAT_LV2] = { { BAR_COLOR_GRN_60_PERCENT, BAR_INFINITE } }, + [LB_STATE_S0_BAT_LV3] = { { BAR_COLOR_GRN_80_PERCENT, BAR_INFINITE } }, + [LB_STATE_S0_BAT_LV4] = { { BAR_COLOR_GRN_FULL, BAR_INFINITE } }, }; -#define DISABLE_LIGHTBAR 0x00 -#define ENABLE_LIGHTBAR 0x80 -#define I_OFF 0x00 -#define GRN_I_ON 0x1E -#define ORG_I_ON 0x28 -#define SEL_OFF 0x00 -#define SEL_1ST_LED BIT(7) -#define SEL_2ND_LED BIT(3) -#define SEL_BOTH (SEL_1ST_LED | SEL_2ND_LED) -#define SKU_ID_NONE 0x00 -#define SKU_ID_INVALID 0x01 +#define DISABLE_LIGHTBAR 0x00 +#define ENABLE_LIGHTBAR 0x80 +#define I_OFF 0x00 +#define GRN_I_ON 0x1E +#define ORG_I_ON 0x28 +#define SEL_OFF 0x00 +#define SEL_1ST_LED BIT(7) +#define SEL_2ND_LED BIT(3) +#define SEL_BOTH (SEL_1ST_LED | SEL_2ND_LED) +#define SKU_ID_NONE 0x00 +#define SKU_ID_INVALID 0x01 #define LB_SUPPORTED_SKUID_LOWER 458700 #define LB_SUPPORTED_SKUID_UPPER 458800 @@ -259,7 +258,7 @@ static bool lightbar_is_supported(void) * if system support lightbar or not. */ if (skuid >= LB_SUPPORTED_SKUID_LOWER && - skuid <= LB_SUPPORTED_SKUID_UPPER) + skuid <= LB_SUPPORTED_SKUID_UPPER) result = true; else result = false; @@ -310,8 +309,7 @@ static void lightbar_set_demo_state(enum lightbar_states tmp_state) LIGHTBAR_COUNT_FOR_RESUME_FROM_SLEEP; } ccprintf("lightbar_demo_state = %d; lightbar_resume_tick %d.\n", - lightbar_demo_state, - lightbar_resume_tick); + lightbar_demo_state, lightbar_resume_tick); } static enum lightbar_states lightbar_get_demo_state(void) @@ -321,8 +319,8 @@ static enum lightbar_states lightbar_get_demo_state(void) * simulate lightbar off. */ if ((lightbar_demo_state != LB_NUM_STATES) && - (lightbar_demo_state >= LB_STATE_S0_AC_ONLY) && - (lightbar_resume_tick == 0)) + (lightbar_demo_state >= LB_STATE_S0_AC_ONLY) && + (lightbar_resume_tick == 0)) return LB_STATE_OFF; return lightbar_demo_state; @@ -356,89 +354,65 @@ static bool lightbar_is_enabled(void) * ISEL_A12, ISEL_A34, ISEL_B12, ISEL_B34, ISEL_C12, ISEL_C34 */ const uint8_t lightbar_10_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = { - [BAR_RESET] = { - 0x00, 0x00, DISABLE_LIGHTBAR, - I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_OFF] = { - 0x00, 0x00, DISABLE_LIGHTBAR, - I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_ORG_20_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_40_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_60_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_80_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_FULL] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF - }, - [BAR_COLOR_ORG_FULL] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF - } + [BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, + I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, + SEL_OFF, SEL_OFF }, + [BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF, + I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, + SEL_OFF }, + [BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, + ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_OFF, SEL_BOTH, SEL_OFF, SEL_OFF, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_OFF, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_BOTH, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF, + I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF }, + [BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF } }; const uint8_t lightbar_12_led_cfg[LIGHTBAR_COLOR_TOTAL][KTD20XX_TOTOAL_REG] = { - [BAR_RESET] = { - 0x00, 0x00, DISABLE_LIGHTBAR, - I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_OFF] = { - 0x00, 0x00, DISABLE_LIGHTBAR, - I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_ORG_20_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_40_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_60_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF - }, - [BAR_COLOR_GRN_80_PERCENT] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED - }, - [BAR_COLOR_GRN_FULL] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - GRN_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH - }, - [BAR_COLOR_ORG_FULL] = { - 0x00, 0x00, ENABLE_LIGHTBAR, - I_OFF, ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, - SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH - } + [BAR_RESET] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, + I_OFF, I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, + SEL_OFF, SEL_OFF }, + [BAR_OFF] = { 0x00, 0x00, DISABLE_LIGHTBAR, I_OFF, I_OFF, I_OFF, I_OFF, + I_OFF, I_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, SEL_OFF, + SEL_OFF }, + [BAR_COLOR_ORG_20_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, + ORG_I_ON, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_2ND_LED, SEL_BOTH, SEL_OFF, SEL_OFF, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_40_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_OFF, SEL_2ND_LED, + SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_60_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_2ND_LED, + SEL_BOTH, SEL_OFF, SEL_OFF }, + [BAR_COLOR_GRN_80_PERCENT] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, I_OFF, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH, + SEL_OFF, SEL_2ND_LED }, + [BAR_COLOR_GRN_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, GRN_I_ON, I_OFF, + I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH }, + [BAR_COLOR_ORG_FULL] = { 0x00, 0x00, ENABLE_LIGHTBAR, I_OFF, ORG_I_ON, + I_OFF, I_OFF, I_OFF, I_OFF, SEL_BOTH, SEL_BOTH, + SEL_BOTH, SEL_BOTH, SEL_BOTH, SEL_BOTH } }; /* @@ -462,7 +436,7 @@ static void lightbar_set_color(enum ec_lightbar_colors color) controller_write(i, lightbar_ctrl[color][i]); controller_write(KTD20XX_CTRL_CFG, - lightbar_ctrl[color][KTD20XX_CTRL_CFG]); + lightbar_ctrl[color][KTD20XX_CTRL_CFG]); i2c_lock(I2C_PORT_LIGHTBAR, 0); } @@ -519,10 +493,10 @@ static void lightbar_sleep_exit(void) DECLARE_HOOK(HOOK_CHIPSET_RESUME, lightbar_sleep_exit, HOOK_PRIO_DEFAULT); -#define LB_BAT_THRESHOLD_1 16 -#define LB_BAT_THRESHOLD_2 40 -#define LB_BAT_THRESHOLD_3 60 -#define LB_BAT_THRESHOLD_4 80 +#define LB_BAT_THRESHOLD_1 16 +#define LB_BAT_THRESHOLD_2 40 +#define LB_BAT_THRESHOLD_3 60 +#define LB_BAT_THRESHOLD_4 80 static enum lightbar_states lightbar_get_state(void) { @@ -536,7 +510,7 @@ static enum lightbar_states lightbar_get_state(void) if (lightbar_resume_tick) { if ((battery_is_present() == BP_YES) && - charge_get_display_charge()) { + charge_get_display_charge()) { if (cur_bat_percent < LB_BAT_THRESHOLD_1) new_state = LB_STATE_S0_BAT_LOW; else if (cur_bat_percent < LB_BAT_THRESHOLD_2) @@ -557,7 +531,7 @@ static enum lightbar_states lightbar_get_state(void) if (extpower_is_present()) { if ((battery_is_present() == BP_YES) && - charge_get_display_charge()) { + charge_get_display_charge()) { if (cur_bat_percent < LB_BAT_THRESHOLD_1) new_state = LB_STATE_SLEEP_AC_BAT_LOW; else if (cur_bat_percent < LB_BAT_THRESHOLD_2) @@ -607,15 +581,14 @@ static void lightbar_update(void) if (lightbar_resume_tick) lightbar_resume_tick--; - if (desired_state != lb_cur_state && - desired_state < LB_NUM_STATES) { + if (desired_state != lb_cur_state && desired_state < LB_NUM_STATES) { /* State is changing */ lb_cur_state = desired_state; /* Reset ticks and period when state changes */ ticks = 0; period = lb_table[lb_cur_state][LIGHTBAR_PHASE_0].ticks + - lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks; + lb_table[lb_cur_state][LIGHTBAR_PHASE_1].ticks; /* * System will be waken up when AC status change in S0ix. Due to @@ -630,7 +603,8 @@ static void lightbar_update(void) /* If this state is undefined, turn lightbar off */ if (period == 0) { CPRINTS("Undefined lightbar behavior for lightbar state %d," - "turning off lightbar", lb_cur_state); + "turning off lightbar", + lb_cur_state); lightbar_set_color(BAR_OFF); return; } @@ -649,7 +623,6 @@ static void lightbar_update(void) /* Set the color for the given state and phase */ lightbar_set_color(lb_table[lb_cur_state][phase].color); - } DECLARE_HOOK(HOOK_TICK, lightbar_update, HOOK_PRIO_DEFAULT); @@ -663,17 +636,15 @@ static void lightbar_dump_status(void) int cbi_ssfc_lightbar; ccprintf("lightbar is %ssupported, %sabled, auto_control: %sabled\n", - lightbar_is_supported()?"":"un-", - lightbar_is_enabled()?"en":"dis", - lightbar_is_auto_control()?"en":"dis"); + lightbar_is_supported() ? "" : "un-", + lightbar_is_enabled() ? "en" : "dis", + lightbar_is_auto_control() ? "en" : "dis"); cbi_bid = get_board_id(); cbi_get_sku_id(&cbi_skuid); cbi_ssfc_lightbar = get_cbi_ssfc_lightbar(); - ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n", - cbi_bid, - cbi_skuid, - cbi_ssfc_lightbar); + ccprintf("board id = %d, skuid = %d, ssfc_lightbar = %d\n", cbi_bid, + cbi_skuid, cbi_ssfc_lightbar); } #ifdef CONFIG_CONSOLE_CMDHELP @@ -682,11 +653,11 @@ static int help(const char *cmd) ccprintf("Usage:\n"); ccprintf(" %s - dump lightbar status\n", cmd); ccprintf(" %s on - set on lightbar auto control\n", - cmd); + cmd); ccprintf(" %s off - set off lightbar auto control\n", - cmd); - ccprintf(" %s demo [%x - %x] - demo lightbar state\n", - cmd, LB_STATE_OFF, (LB_NUM_STATES - 1)); + cmd); + ccprintf(" %s demo [%x - %x] - demo lightbar state\n", cmd, + LB_STATE_OFF, (LB_NUM_STATES - 1)); return EC_SUCCESS; } #endif @@ -700,9 +671,9 @@ static int command_lightbar(int argc, char **argv) } if (!strcasecmp(argv[1], "help")) { - #ifdef CONFIG_CONSOLE_CMDHELP +#ifdef CONFIG_CONSOLE_CMDHELP help(argv[0]); - #endif +#endif return EC_SUCCESS; } @@ -744,8 +715,7 @@ static int command_lightbar(int argc, char **argv) return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, - "[help | on | off | demo]", +DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | on | off | demo]", "get/set lightbar status"); /****************************************************************************/ @@ -788,6 +758,4 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, - lpc_cmd_lightbar, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0)); -- cgit v1.2.1 From 9efae79693e95b62d9662662c40a9a2c204b9709 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:55 -0600 Subject: board/osiris/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib028764e6a4ebb700a0c4ac9c7aa391e7d6d22e5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728799 Reviewed-by: Jeremy Bettis --- board/osiris/fw_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/osiris/fw_config.h b/board/osiris/fw_config.h index c10e6a99ca..c44144e25c 100644 --- a/board/osiris/fw_config.h +++ b/board/osiris/fw_config.h @@ -21,10 +21,10 @@ enum ec_cfg_keyboard_backlight_type { union osiris_cbi_fw_config { struct { - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t reserved_1 : 1; - uint32_t audio : 2; - uint32_t reserved_2 : 28; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t reserved_1 : 1; + uint32_t audio : 2; + uint32_t reserved_2 : 28; }; uint32_t raw_value; }; -- cgit v1.2.1 From 4962736c660df0e773dc47595295b7e173c6a0b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:39 -0600 Subject: board/hammer/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I002cd83a98eebc7fdfb8860cde95e06c8ab6d9d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728315 Reviewed-by: Jeremy Bettis --- board/hammer/board.c | 89 +++++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 47 deletions(-) diff --git a/board/hammer/board.c b/board/hammer/board.c index 3e3491d3e1..12cf41e910 100644 --- a/board/hammer/board.c +++ b/board/hammer/board.c @@ -48,21 +48,21 @@ #define CROS_EC_SECTION "RO" #endif -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Hammer"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Hammer"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), #ifdef CONFIG_USB_ISOCHRONOUS [USB_STR_HEATMAP_NAME] = USB_STRING_DESC("Heatmap"), #endif @@ -84,28 +84,28 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); USB_SPI_CONFIG(usb_spi, USB_IFACE_I2C_SPI, USB_EP_I2C_SPI, 0); /* SPI interface is always enabled, no need to do anything. */ -void usb_spi_board_enable(struct usb_spi_config const *config) {} -void usb_spi_board_disable(struct usb_spi_config const *config) {} -#endif /* !HAS_SPI_TOUCHPAD */ +void usb_spi_board_enable(struct usb_spi_config const *config) +{ +} +void usb_spi_board_disable(struct usb_spi_config const *config) +{ +} +#endif /* !HAS_SPI_TOUCHPAD */ #ifdef CONFIG_I2C /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 400, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 400, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, #ifdef BOARD_WAND - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 100, - .scl = GPIO_CHARGER_I2C_SCL, - .sda = GPIO_CHARGER_I2C_SDA - }, + { .name = "charger", + .port = I2C_PORT_CHARGER, + .kbps = 100, + .scl = GPIO_CHARGER_I2C_SCL, + .sda = GPIO_CHARGER_I2C_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -125,7 +125,7 @@ const struct charger_config_t chg_chips[] = { #ifdef HAS_BACKLIGHT /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - {STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ}, + { STM32_TIM(TIM_KBLIGHT), STM32_TIM_CH(1), 0, KBLIGHT_PWM_FREQ }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); #endif /* HAS_BACKLIGHT */ @@ -154,26 +154,22 @@ __override struct keyboard_scan_config keyscan_config = { struct consumer const ec_ec_usart_consumer; static struct usart_config const ec_ec_usart; -struct queue const ec_ec_comm_server_input = QUEUE_DIRECT(64, uint8_t, - ec_ec_usart.producer, ec_ec_usart_consumer); -struct queue const ec_ec_comm_server_output = QUEUE_DIRECT(64, uint8_t, - null_producer, ec_ec_usart.consumer); +struct queue const ec_ec_comm_server_input = + QUEUE_DIRECT(64, uint8_t, ec_ec_usart.producer, ec_ec_usart_consumer); +struct queue const ec_ec_comm_server_output = + QUEUE_DIRECT(64, uint8_t, null_producer, ec_ec_usart.consumer); struct consumer const ec_ec_usart_consumer = { .queue = &ec_ec_comm_server_input, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = ec_ec_comm_server_written, }), }; static struct usart_config const ec_ec_usart = - USART_CONFIG(EC_EC_UART, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - USART_CONFIG_FLAG_HDSEL, - ec_ec_comm_server_input, - ec_ec_comm_server_output); + USART_CONFIG(EC_EC_UART, usart_rx_interrupt, usart_tx_interrupt, 115200, + USART_CONFIG_FLAG_HDSEL, ec_ec_comm_server_input, + ec_ec_comm_server_output); #endif /* BOARD_WAND && SECTION_IS_RW */ /****************************************************************************** @@ -280,9 +276,9 @@ static void board_tablet_mode_change(void) keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE); } DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, board_tablet_mode_change, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); /* Run after tablet_mode_init. */ -DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, board_tablet_mode_change, HOOK_PRIO_DEFAULT + 1); #endif /* @@ -295,7 +291,7 @@ int board_get_entropy(void *buffer, int len) uint8_t *data = buffer; uint32_t start; /* We expect one SOF per ms, so wait at most 2ms. */ - const uint32_t timeout = 2*MSEC; + const uint32_t timeout = 2 * MSEC; for (i = 0; i < len; i++) { STM32_CRS_ICR |= STM32_CRS_ICR_SYNCOKC; @@ -326,8 +322,7 @@ __override const char *board_read_serial(void) int i; for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) { - snprintf(&str[pos], sizeof(str)-pos, - "%02x", id[i]); + snprintf(&str[pos], sizeof(str) - pos, "%02x", id[i]); } } @@ -390,8 +385,8 @@ static const struct ec_response_keybd_config duck_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { if (IS_ENABLED(BOARD_ZED) || IS_ENABLED(BOARD_STAR) || IS_ENABLED(BOARD_GELATIN)) -- cgit v1.2.1 From 349f15d6d26fb071075a8bf15dd4ee9d68ab0d67 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:20 -0600 Subject: common/virtual_battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iece63432ecfaf86f9637fcbfd8f880076f1bf6ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729812 Reviewed-by: Jeremy Bettis --- common/virtual_battery.c | 42 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/common/virtual_battery.c b/common/virtual_battery.c index 8e88e22bcb..70e88a11ee 100644 --- a/common/virtual_battery.c +++ b/common/virtual_battery.c @@ -14,7 +14,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define BATT_MODE_UNINITIALIZED -1 @@ -34,12 +34,10 @@ static uint8_t cache_hit; static const uint8_t *batt_cmd_head; static int acc_write_len; -int virtual_battery_handler(struct ec_response_i2c_passthru *resp, - int in_len, int *err_code, int xferflags, - int read_len, int write_len, - const uint8_t *out) +int virtual_battery_handler(struct ec_response_i2c_passthru *resp, int in_len, + int *err_code, int xferflags, int read_len, + int write_len, const uint8_t *out) { - #if defined(CONFIG_BATTERY_PRESENT_GPIO) || \ defined(CONFIG_BATTERY_PRESENT_CUSTOM) /* @@ -74,7 +72,7 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp, } else { sb_cmd_state = READ_VB; *err_code = virtual_battery_operation(batt_cmd_head, - NULL, 0, 0); + NULL, 0, 0); /* * If the reg is not handled by virtual battery, we * do not support it. @@ -118,10 +116,8 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp, /* write to virtual battery */ case START: case WRITE_VB: - virtual_battery_operation(batt_cmd_head, - NULL, - 0, - acc_write_len); + virtual_battery_operation(batt_cmd_head, NULL, 0, + acc_write_len); break; /* read from virtual battery */ case READ_VB: @@ -129,15 +125,13 @@ int virtual_battery_handler(struct ec_response_i2c_passthru *resp, read_len += in_len; memset(&resp->data[0], 0, read_len); virtual_battery_operation(batt_cmd_head, - &resp->data[0], - read_len, - 0); + &resp->data[0], + read_len, 0); } break; default: reset_parse_state(); return EC_ERROR_INVAL; - } /* Reset the state in the end of messages */ reset_parse_state(); @@ -166,7 +160,8 @@ void copy_memmap_string(uint8_t *dest, int offset, int len) memmap_str = host_get_memmap(offset); /* memmap_str might not be NULL terminated */ memmap_strlen = *(memmap_str + EC_MEMMAP_TEXT_MAX - 1) == '\0' ? - strlen(memmap_str) : EC_MEMMAP_TEXT_MAX; + strlen(memmap_str) : + EC_MEMMAP_TEXT_MAX; dest[0] = memmap_strlen; memcpy(dest + 1, memmap_str, MIN(memmap_strlen, len - 1)); } @@ -180,10 +175,8 @@ static void copy_battery_info_string(uint8_t *dst, const uint8_t *src, int len) strncpy(dst + 1, src, len - 1); } -int virtual_battery_operation(const uint8_t *batt_cmd_head, - uint8_t *dest, - int read_len, - int write_len) +int virtual_battery_operation(const uint8_t *batt_cmd_head, uint8_t *dest, + int read_len, int write_len) { int val; int year, month, day; @@ -233,9 +226,8 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head, * typical SB defaults. */ batt_mode_cache = - MODE_INTERNAL_CHARGE_CONTROLLER | - MODE_ALARM | - MODE_CHARGER; + MODE_INTERNAL_CHARGE_CONTROLLER | + MODE_ALARM | MODE_CHARGER; memcpy(dest, &batt_mode_cache, bounded_read_len); } @@ -278,7 +270,7 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head, break; case SB_FULL_CHARGE_CAPACITY: if (curr_batt->flags & BATT_FLAG_BAD_FULL_CAPACITY || - curr_batt->flags & BATT_FLAG_BAD_VOLTAGE) + curr_batt->flags & BATT_FLAG_BAD_VOLTAGE) return EC_ERROR_BUSY; val = curr_batt->full_capacity; if (batt_mode_cache & MODE_CAPACITY) @@ -308,7 +300,7 @@ int virtual_battery_operation(const uint8_t *batt_cmd_head, break; case SB_REMAINING_CAPACITY: if (curr_batt->flags & BATT_FLAG_BAD_REMAINING_CAPACITY || - curr_batt->flags & BATT_FLAG_BAD_VOLTAGE) + curr_batt->flags & BATT_FLAG_BAD_VOLTAGE) return EC_ERROR_BUSY; val = curr_batt->remaining_capacity; if (batt_mode_cache & MODE_CAPACITY) -- cgit v1.2.1 From 36bf6fd427132e6fce72fedff6deaeeff1453930 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:21 -0600 Subject: board/drobit/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I290fe33a3395fa16422b799c6f0a62561aebe89e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728245 Reviewed-by: Jeremy Bettis --- board/drobit/board.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/board/drobit/board.c b/board/drobit/board.c index fdfab38b52..c04df3e5a5 100644 --- a/board/drobit/board.c +++ b/board/drobit/board.c @@ -41,7 +41,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -76,8 +76,8 @@ static const struct ec_response_keybd_config drobit_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &drobit_kb; } @@ -95,7 +95,7 @@ union volteer_cbi_fw_config fw_config_defaults = { const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -131,8 +131,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(72), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -159,8 +159,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(72), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -467,8 +467,8 @@ DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); /******************************************************************************/ /* Set the charge limit based upon desired maximum. */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Limit the input current to 98% negotiated limit, @@ -476,6 +476,5 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, */ charge_ma = charge_ma * 98 / 100; charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 2ea6540533dda9700b28ca9d0d3b17464f0b5cc3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:19 -0600 Subject: include/driver/charger/isl923x_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibcff21093dca2225efdb0433f542b71ef22ca6db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730273 Reviewed-by: Jeremy Bettis --- include/driver/charger/isl923x_public.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/driver/charger/isl923x_public.h b/include/driver/charger/isl923x_public.h index 2ee5f62cdb..2e57ec7d33 100644 --- a/include/driver/charger/isl923x_public.h +++ b/include/driver/charger/isl923x_public.h @@ -11,7 +11,7 @@ #include "common.h" #include "stdbool.h" -#define ISL923X_ADDR_FLAGS (0x09) +#define ISL923X_ADDR_FLAGS (0x09) extern const struct charger_drv isl923x_drv; -- cgit v1.2.1 From f0e659bffcf5c7d5657ec675b60dd33799a4f8bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:50 -0600 Subject: board/dojo/cbi_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie678a557808e0d54c8df69b0ff595e5fcc76c480 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728231 Reviewed-by: Jeremy Bettis --- board/dojo/cbi_fw_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/dojo/cbi_fw_config.h b/board/dojo/cbi_fw_config.h index 7f98585b84..66dcf1f782 100644 --- a/board/dojo/cbi_fw_config.h +++ b/board/dojo/cbi_fw_config.h @@ -17,8 +17,8 @@ enum fw_config_kblight_type { KB_BL_ABSENT = 0, KB_BL_PRESENT = 1, }; -#define FW_CONFIG_KB_BL_OFFSET 0 -#define FW_CONFIG_KB_BL_MASK GENMASK(0, 0) +#define FW_CONFIG_KB_BL_OFFSET 0 +#define FW_CONFIG_KB_BL_MASK GENMASK(0, 0) /* * Keyboard layout (bit 4-5) @@ -27,8 +27,8 @@ enum fw_config_kblayout_type { KB_BL_TOGGLE_KEY_ABSENT = 0, /* Vol-up key on T12 */ KB_BL_TOGGLE_KEY_PRESENT = 1, /* Vol-up key on T13 */ }; -#define FW_CONFIG_KB_LAYOUT_OFFSET 4 -#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(5, 4) +#define FW_CONFIG_KB_LAYOUT_OFFSET 4 +#define FW_CONFIG_KB_LAYOUT_MASK GENMASK(5, 4) enum fw_config_kblight_type get_cbi_fw_config_kblight(void); enum fw_config_kblayout_type get_cbi_fw_config_kblayout(void); -- cgit v1.2.1 From 06cbb185fa6ac5a453345f2d0fd7146db56c8d51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:23 -0600 Subject: board/nautilus/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6f6fa5a6c0cb7c0e2418d82d526acb905168561 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728721 Reviewed-by: Jeremy Bettis --- board/nautilus/battery.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/nautilus/battery.c b/board/nautilus/battery.c index aaa4a43c06..eca26a3a4e 100644 --- a/board/nautilus/battery.c +++ b/board/nautilus/battery.c @@ -17,19 +17,19 @@ static enum battery_present batt_pres_prev = BP_NOT_SURE; /* Shutdown mode parameters to write to manufacturer access register */ -#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHIP_MODE_REG SB_MANUFACTURER_ACCESS +#define SB_SHUTDOWN_DATA 0x0010 /* * Unlike other smart batteries, Nautilus battery uses different bit fields * in manufacturer access register for the conditions of the CHG/DSG FETs. */ -#define BATFETS_SHIFT (14) -#define BATFETS_MASK (0x3) -#define BATFETS_DISABLED (0x2) +#define BATFETS_SHIFT (14) +#define BATFETS_MASK (0x3) +#define BATFETS_DISABLED (0x2) -#define CHARGING_VOLTAGE_MV_SAFE 8400 -#define CHARGING_CURRENT_MA_SAFE 1500 +#define CHARGING_VOLTAGE_MV_SAFE 8400 +#define CHARGING_CURRENT_MA_SAFE 1500 static const struct battery_info info = { .voltage_max = 8700, @@ -160,8 +160,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* @@ -185,8 +186,7 @@ static int battery_check_disconnect(void) if (rv) return BATTERY_DISCONNECT_ERROR; - if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) == - BATFETS_DISABLED) + if (((batt_mfgacc >> BATFETS_SHIFT) & BATFETS_MASK) == BATFETS_DISABLED) return BATTERY_DISCONNECTED; return BATTERY_NOT_DISCONNECTED; -- cgit v1.2.1 From e2fd0422dcb9ab6c1d728748b1170ff9dad6b452 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:42 -0600 Subject: include/mock/fpsensor_state_mock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iac50868302a8587e7a600ff38920ba1218705176 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730358 Reviewed-by: Jeremy Bettis --- include/mock/fpsensor_state_mock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mock/fpsensor_state_mock.h b/include/mock/fpsensor_state_mock.h index eafe01851c..4571a1e987 100644 --- a/include/mock/fpsensor_state_mock.h +++ b/include/mock/fpsensor_state_mock.h @@ -15,4 +15,4 @@ extern const uint8_t default_fake_tpm_seed[FP_CONTEXT_TPM_BYTES]; int fpsensor_state_mock_set_tpm_seed( const uint8_t tpm_seed[FP_CONTEXT_TPM_BYTES]); -#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */ +#endif /* __MOCK_FPSENSOR_STATE_MOCK_H */ -- cgit v1.2.1 From 9e9cfa160d7f4c29cc2428ee4493e3bf07e8081e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:43 -0600 Subject: board/shuboz/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I595f053d6d210f022892d62f1201e24c39332eb5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728941 Reviewed-by: Jeremy Bettis --- board/shuboz/battery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/shuboz/battery.c b/board/shuboz/battery.c index 155cadab41..4e40c9357c 100644 --- a/board/shuboz/battery.c +++ b/board/shuboz/battery.c @@ -133,7 +133,7 @@ int charger_profile_override(struct charge_state_data *curr) return 0; if (current_level != 0) { - if (curr->requested_current > current_table[current_level-1]) + if (curr->requested_current > current_table[current_level - 1]) curr->requested_current = current_table[current_level - 1]; } -- cgit v1.2.1 From 8156b65736cad51b63f5722856698d414bcf4996 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:14 -0600 Subject: zephyr/include/soc/nuvoton_npcx/reg_def_cros.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62dbb4cb10b91849b601e8fdbe145ccdc886401d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730733 Reviewed-by: Jeremy Bettis --- zephyr/include/soc/nuvoton_npcx/reg_def_cros.h | 118 ++++++++++++------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h index c4d176851d..180c2e50a3 100644 --- a/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h +++ b/zephyr/include/soc/nuvoton_npcx/reg_def_cros.h @@ -40,21 +40,21 @@ struct kbs_reg { }; /* KBS register fields */ -#define NPCX_KBSBUFINDX 0 -#define NPCX_KBSEVT_KBSDONE 0 -#define NPCX_KBSEVT_KBSERR 1 -#define NPCX_KBSCTL_START 0 -#define NPCX_KBSCTL_KBSMODE 1 -#define NPCX_KBSCTL_KBSIEN 2 -#define NPCX_KBSCTL_KBSINC 3 -#define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2) -#define NPCX_KBSCFGINDX 0 +#define NPCX_KBSBUFINDX 0 +#define NPCX_KBSEVT_KBSDONE 0 +#define NPCX_KBSEVT_KBSERR 1 +#define NPCX_KBSCTL_START 0 +#define NPCX_KBSCTL_KBSMODE 1 +#define NPCX_KBSCTL_KBSIEN 2 +#define NPCX_KBSCTL_KBSINC 3 +#define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2) +#define NPCX_KBSCFGINDX 0 /* Index of 'Automatic Scan' configuration register */ -#define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */ -#define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */ -#define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */ -#define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */ -#define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */ +#define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */ +#define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */ +#define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */ +#define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */ +#define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */ /* * Monotonic Counter (MTC) device registers @@ -67,8 +67,8 @@ struct mtc_reg { }; /* MTC register fields */ -#define NPCX_WTC_PTO 30 -#define NPCX_WTC_WIE 31 +#define NPCX_WTC_PTO 30 +#define NPCX_WTC_WIE 31 /* SHI (Serial Host Interface) registers */ struct shi_reg { @@ -109,48 +109,48 @@ struct shi_reg { }; /* SHI register fields */ -#define NPCX_SHICFG1_EN 0 -#define NPCX_SHICFG1_MODE 1 -#define NPCX_SHICFG1_WEN 2 -#define NPCX_SHICFG1_AUTIBF 3 -#define NPCX_SHICFG1_AUTOBE 4 -#define NPCX_SHICFG1_DAS 5 -#define NPCX_SHICFG1_CPOL 6 -#define NPCX_SHICFG1_IWRAP 7 -#define NPCX_SHICFG2_SIMUL 0 -#define NPCX_SHICFG2_BUSY 1 -#define NPCX_SHICFG2_ONESHOT 2 -#define NPCX_SHICFG2_SLWU 3 -#define NPCX_SHICFG2_REEN 4 -#define NPCX_SHICFG2_RESTART 5 -#define NPCX_SHICFG2_REEVEN 6 -#define NPCX_EVENABLE_OBEEN 0 -#define NPCX_EVENABLE_OBHEEN 1 -#define NPCX_EVENABLE_IBFEN 2 -#define NPCX_EVENABLE_IBHFEN 3 -#define NPCX_EVENABLE_EOREN 4 -#define NPCX_EVENABLE_EOWEN 5 -#define NPCX_EVENABLE_STSREN 6 -#define NPCX_EVENABLE_IBOREN 7 -#define NPCX_EVSTAT_OBE 0 -#define NPCX_EVSTAT_OBHE 1 -#define NPCX_EVSTAT_IBF 2 -#define NPCX_EVSTAT_IBHF 3 -#define NPCX_EVSTAT_EOR 4 -#define NPCX_EVSTAT_EOW 5 -#define NPCX_EVSTAT_STSR 6 -#define NPCX_EVSTAT_IBOR 7 -#define NPCX_STATUS_OBES 6 -#define NPCX_STATUS_IBFS 7 -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG1_EN 0 +#define NPCX_SHICFG1_MODE 1 +#define NPCX_SHICFG1_WEN 2 +#define NPCX_SHICFG1_AUTIBF 3 +#define NPCX_SHICFG1_AUTOBE 4 +#define NPCX_SHICFG1_DAS 5 +#define NPCX_SHICFG1_CPOL 6 +#define NPCX_SHICFG1_IWRAP 7 +#define NPCX_SHICFG2_SIMUL 0 +#define NPCX_SHICFG2_BUSY 1 +#define NPCX_SHICFG2_ONESHOT 2 +#define NPCX_SHICFG2_SLWU 3 +#define NPCX_SHICFG2_REEN 4 +#define NPCX_SHICFG2_RESTART 5 +#define NPCX_SHICFG2_REEVEN 6 +#define NPCX_EVENABLE_OBEEN 0 +#define NPCX_EVENABLE_OBHEEN 1 +#define NPCX_EVENABLE_IBFEN 2 +#define NPCX_EVENABLE_IBHFEN 3 +#define NPCX_EVENABLE_EOREN 4 +#define NPCX_EVENABLE_EOWEN 5 +#define NPCX_EVENABLE_STSREN 6 +#define NPCX_EVENABLE_IBOREN 7 +#define NPCX_EVSTAT_OBE 0 +#define NPCX_EVSTAT_OBHE 1 +#define NPCX_EVSTAT_IBF 2 +#define NPCX_EVSTAT_IBHF 3 +#define NPCX_EVSTAT_EOR 4 +#define NPCX_EVSTAT_EOW 5 +#define NPCX_EVSTAT_STSR 6 +#define NPCX_EVSTAT_IBOR 7 +#define NPCX_STATUS_OBES 6 +#define NPCX_STATUS_IBFS 7 +#define NPCX_SHICFG3_OBUFLVLDIS 7 +#define NPCX_SHICFG4_IBUFLVLDIS 7 +#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) +#define NPCX_SHICFG5_IBUFLVL2DIS 7 +#define NPCX_EVSTAT2_IBHF2 0 +#define NPCX_EVSTAT2_CSNRE 1 +#define NPCX_EVSTAT2_CSNFE 2 +#define NPCX_EVENABLE2_IBHF2EN 0 +#define NPCX_EVENABLE2_CSNREEN 1 +#define NPCX_EVENABLE2_CSNFEEN 2 #endif /* _NUVOTON_NPCX_REG_DEF_CROS_H */ -- cgit v1.2.1 From 218c515be42bd0b2c15ed22bd9a0a4a60ebed5c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:08 -0600 Subject: chip/mt_scp/mt818x/system.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia4e0c6a946029f84826ccc9519252edef4b3045a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729342 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/system.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/chip/mt_scp/mt818x/system.c b/chip/mt_scp/mt818x/system.c index d07bd394a0..6184b75c27 100644 --- a/chip/mt_scp/mt818x/system.c +++ b/chip/mt_scp/mt818x/system.c @@ -79,10 +79,10 @@ void system_pre_init(void) /* CM4 Modification */ scp_cm4_mod(); - /* Clock */ - #ifdef CHIP_VARIANT_MT8183 +/* Clock */ +#ifdef CHIP_VARIANT_MT8183 scp_enable_clock(); - #endif +#endif /* Peripheral IRQ */ scp_enable_pirq(); @@ -127,7 +127,8 @@ void system_reset(int flags) } } - /* Set watchdog timer to small value, and spin wait for watchdog reset */ + /* Set watchdog timer to small value, and spin wait for watchdog reset + */ SCP_WDT_CFG = 0; SCP_WDT_CFG = SCP_WDT_ENABLE | SCP_WDT_PERIOD(1); watchdog_reload(); @@ -162,12 +163,9 @@ static void check_reset_cause(void) int system_is_reboot_warm(void) { const uint32_t cold_flags = - EC_RESET_FLAG_RESET_PIN | - EC_RESET_FLAG_POWER_ON | - EC_RESET_FLAG_WATCHDOG | - EC_RESET_FLAG_HARD | - EC_RESET_FLAG_SOFT | - EC_RESET_FLAG_HIBERNATE; + EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON | + EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_HARD | + EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HIBERNATE; check_reset_cause(); -- cgit v1.2.1 From c68f314da2a7341cf2d12565c54877286bcdeee2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:37 -0600 Subject: board/waddledoo2/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If15dc0c1e01fbe5d95fa83968880b151f17bfa3b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729113 Reviewed-by: Jeremy Bettis --- board/waddledoo2/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/waddledoo2/led.c b/board/waddledoo2/led.c index 85bd75ce99..47fe2a9def 100644 --- a/board/waddledoo2/led.c +++ b/board/waddledoo2/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 6280da0e1356bdfc7c4d655864abb38c7a3e256f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:01 -0600 Subject: driver/gl3590.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52367422960dc0ef738e2ffb92daffa34048ab41 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729987 Reviewed-by: Jeremy Bettis --- driver/gl3590.h | 50 +++++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/driver/gl3590.h b/driver/gl3590.h index 931035d95e..1d24785491 100644 --- a/driver/gl3590.h +++ b/driver/gl3590.h @@ -7,23 +7,23 @@ #include "stdbool.h" /* Registers definitions */ -#define GL3590_HUB_MODE_REG 0x0 -#define GL3590_HUB_MODE_I2C_READY 0x1 -#define GL3590_HUB_MODE_USB2_EN 0x2 -#define GL3590_HUB_MODE_USB3_EN 0x4 -#define GL3590_INT_REG 0x1 -#define GL3590_INT_PENDING 0x1 -#define GL3590_INT_CLEAR 0x1 -#define GL3590_RESPONSE_REG 0x2 -#define GL3590_RESPONSE_REG_SYNC_MASK 0x80 -#define GL3590_PORT_DISABLED_REG 0x4 -#define GL3590_PORT_EN_STS_REG 0x8 -#define GL3590_HUB_STS_REG 0xA -#define GL3590_HUB_STS_HOST_PWR_MASK 0x30 -#define GL3590_HUB_STS_HOST_PWR_SHIFT 4 -#define GL3590_DEFAULT_HOST_PWR_SRC 0x0 -#define GL3590_1_5_A_HOST_PWR_SRC 0x1 -#define GL3590_3_0_A_HOST_PWR_SRC 0x2 +#define GL3590_HUB_MODE_REG 0x0 +#define GL3590_HUB_MODE_I2C_READY 0x1 +#define GL3590_HUB_MODE_USB2_EN 0x2 +#define GL3590_HUB_MODE_USB3_EN 0x4 +#define GL3590_INT_REG 0x1 +#define GL3590_INT_PENDING 0x1 +#define GL3590_INT_CLEAR 0x1 +#define GL3590_RESPONSE_REG 0x2 +#define GL3590_RESPONSE_REG_SYNC_MASK 0x80 +#define GL3590_PORT_DISABLED_REG 0x4 +#define GL3590_PORT_EN_STS_REG 0x8 +#define GL3590_HUB_STS_REG 0xA +#define GL3590_HUB_STS_HOST_PWR_MASK 0x30 +#define GL3590_HUB_STS_HOST_PWR_SHIFT 4 +#define GL3590_DEFAULT_HOST_PWR_SRC 0x0 +#define GL3590_1_5_A_HOST_PWR_SRC 0x1 +#define GL3590_3_0_A_HOST_PWR_SRC 0x2 #define GL3590_I2C_ADDR0 0x50 @@ -42,14 +42,14 @@ void gl3590_irq_handler(int hub); /* Get power capabilities of UFP host connection */ enum ec_error_list gl3590_ufp_pwr(int hub, struct pwr_con_t *pwr); -#define GL3590_DFP1 BIT(0) -#define GL3590_DFP2 BIT(1) -#define GL3590_DFP3 BIT(2) -#define GL3590_DFP4 BIT(3) -#define GL3590_DFP5 BIT(4) -#define GL3590_DFP6 BIT(5) -#define GL3590_DFP7 BIT(6) -#define GL3590_DFP8 BIT(7) +#define GL3590_DFP1 BIT(0) +#define GL3590_DFP2 BIT(1) +#define GL3590_DFP3 BIT(2) +#define GL3590_DFP4 BIT(3) +#define GL3590_DFP5 BIT(4) +#define GL3590_DFP6 BIT(5) +#define GL3590_DFP7 BIT(6) +#define GL3590_DFP8 BIT(7) /* Enable/disable power to particular downstream facing ports */ int gl3590_enable_ports(int hub, uint8_t port_mask, bool enable); -- cgit v1.2.1 From 4e60ea691fe02f60549d847c56b1c27c2ff370ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:38 -0600 Subject: board/careena/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2173f1cf3d46921885cc6a9b77a6a6a8c1ea100e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728139 Reviewed-by: Jeremy Bettis --- board/careena/led.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/careena/led.c b/board/careena/led.c index 4188290b4f..698825bafc 100644 --- a/board/careena/led.c +++ b/board/careena/led.c @@ -20,7 +20,7 @@ #define BAT_LED_ON 0 #define BAT_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -28,7 +28,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -93,11 +93,10 @@ static void led_set_battery(void) battery_ticks++; /* override battery led for system suspend */ - if (chipset_in_state(CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY) && + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY) && charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x4 ? - LED_WHITE : LED_OFF); + led_set_color_battery(power_ticks++ & 0x4 ? LED_WHITE : + LED_OFF); return; } @@ -125,8 +124,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); -- cgit v1.2.1 From b6468e2e9ddaf1df778195f09f7de67cdd5e1b05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:27 -0600 Subject: common/ocpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I591b001827f0fb0a2ea201e2f2cc986d9d635eea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729697 Reviewed-by: Jeremy Bettis --- common/ocpc.c | 132 ++++++++++++++++++++++++++++------------------------------ 1 file changed, 64 insertions(+), 68 deletions(-) diff --git a/common/ocpc.c b/common/ocpc.c index 89d9b9cf4f..11958a33f0 100644 --- a/common/ocpc.c +++ b/common/ocpc.c @@ -32,23 +32,22 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHARGER, outstr) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) -#define CPRINT_VIZ(format, args...) \ -do { \ - if (viz_output) \ - cprintf(CC_CHARGER, format, ## args); \ -} while (0) -#define CPRINTS_DBG(format, args...) \ -do { \ - if (debug_output) \ - cprints(CC_CHARGER, format, ## args); \ -} while (0) -#define CPRINTF_DBG(format, args...) \ -do { \ - if (debug_output) \ - cprintf(CC_CHARGER, format, ## args); \ -} while (0) - +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINT_VIZ(format, args...) \ + do { \ + if (viz_output) \ + cprintf(CC_CHARGER, format, ##args); \ + } while (0) +#define CPRINTS_DBG(format, args...) \ + do { \ + if (debug_output) \ + cprints(CC_CHARGER, format, ##args); \ + } while (0) +#define CPRINTF_DBG(format, args...) \ + do { \ + if (debug_output) \ + cprintf(CC_CHARGER, format, ##args); \ + } while (0) /* Code refactor will be needed if more than 2 charger chips are present */ BUILD_ASSERT(CHARGER_NUM == 2); @@ -68,14 +67,14 @@ static int viz_output; #define RSYS_IDX 2 static int resistance_tbl[NUM_RESISTANCE_SAMPLES][3] = { /* Rsys+Rbatt Rbatt Rsys */ - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, - {CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0}, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, + { CONFIG_OCPC_DEF_RBATT_MOHMS, CONFIG_OCPC_DEF_RBATT_MOHMS, 0 }, }; static int resistance_tbl_idx; static int mean_resistance[3]; @@ -125,8 +124,8 @@ static void calc_resistance_stats(struct ocpc_data *ocpc) for (j = 0; j < NUM_RESISTANCE_SAMPLES; j++) sum += POW2(resistance_tbl[j][i] - mean_resistance[i]); - stddev_resistance[i] = fp_sqrtf(INT_TO_FP(sum / - NUM_RESISTANCE_SAMPLES)); + stddev_resistance[i] = + fp_sqrtf(INT_TO_FP(sum / NUM_RESISTANCE_SAMPLES)); stddev_resistance[i] = FP_TO_INT(stddev_resistance[i]); /* * Don't let our stddev collapse to 0 to continually consider @@ -149,8 +148,7 @@ static bool is_within_range(struct ocpc_data *ocpc, int combined, int rbatt, /* Discard measurements not within a 6 std. dev. window. */ if ((ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) { /* We only know the combined Rsys+Rbatt */ - valid = (combined > 0) && - (combined <= ub[COMBINED_IDX]) && + valid = (combined > 0) && (combined <= ub[COMBINED_IDX]) && (combined >= lb[COMBINED_IDX]); } else { valid = (rsys <= ub[RSYS_IDX]) && (rsys >= lb[RSYS_IDX]) && @@ -201,12 +199,12 @@ enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc, * out Rsys from Rbatt. */ combined = ((ocpc->vsys_aux_mv - battery->voltage) * 1000) / - battery->current; + battery->current; } else { rsys = ((ocpc->vsys_aux_mv - ocpc->vsys_mv) * 1000) / - ocpc->isys_ma; + ocpc->isys_ma; rbatt = ((ocpc->vsys_mv - battery->voltage) * 1000) / - battery->current; + battery->current; combined = rsys + rbatt; } @@ -222,35 +220,36 @@ enum ec_error_list ocpc_calc_resistances(struct ocpc_data *ocpc, resistance_tbl[resistance_tbl_idx][COMBINED_IDX] = MAX(combined, CONFIG_OCPC_DEF_RBATT_MOHMS); calc_resistance_stats(ocpc); - resistance_tbl_idx = (resistance_tbl_idx + 1) % - NUM_RESISTANCE_SAMPLES; + resistance_tbl_idx = + (resistance_tbl_idx + 1) % NUM_RESISTANCE_SAMPLES; } if (seeded) { ocpc->combined_rsys_rbatt_mo = - MAX(mean_resistance[COMBINED_IDX], - CONFIG_OCPC_DEF_RBATT_MOHMS); + MAX(mean_resistance[COMBINED_IDX], + CONFIG_OCPC_DEF_RBATT_MOHMS); if (!(ocpc->chg_flags[act_chg] & OCPC_NO_ISYS_MEAS_CAP)) { ocpc->rsys_mo = mean_resistance[RSYS_IDX]; ocpc->rbatt_mo = MAX(mean_resistance[RBATT_IDX], CONFIG_OCPC_DEF_RBATT_MOHMS); - CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm", - ocpc->rsys_mo, ocpc->rbatt_mo); + CPRINTS_DBG("Rsys: %dmOhm Rbatt: %dmOhm", ocpc->rsys_mo, + ocpc->rbatt_mo); } CPRINTS_DBG("Rsys+Rbatt: %dmOhm", ocpc->combined_rsys_rbatt_mo); } else { seeded = ++initial_samples >= (2 * NUM_RESISTANCE_SAMPLES) ? - true : false; + true : + false; } return EC_SUCCESS; } int ocpc_config_secondary_charger(int *desired_input_current, - struct ocpc_data *ocpc, - int voltage_mv, int current_ma) + struct ocpc_data *ocpc, int voltage_mv, + int current_ma) { int rv = EC_SUCCESS; struct batt_params batt; @@ -342,7 +341,6 @@ int ocpc_config_secondary_charger(int *desired_input_current, iterations = 0; } - /* * We need to induce a current flow that matches the requested current * by raising VSYS. Let's start by getting the latest data that we @@ -353,7 +351,6 @@ int ocpc_config_secondary_charger(int *desired_input_current, ocpc_get_adcs(ocpc); charger_get_params(&charger); - /* * If the system is in S5/G3, we can calculate the board and battery * resistances. @@ -378,9 +375,9 @@ int ocpc_config_secondary_charger(int *desired_input_current, /* Set our current target accordingly. */ if (batt.desired_voltage) { if (((batt.voltage < batt_info->voltage_min) || - ((batt.voltage < batt_info->voltage_normal) && - (current_ma >= 0) && - (current_ma <= batt_info->precharge_current))) && + ((batt.voltage < batt_info->voltage_normal) && + (current_ma >= 0) && + (current_ma <= batt_info->precharge_current))) && (ph != PHASE_PRECHARGE)) { /* * If the charger IC doesn't support the linear charge @@ -396,8 +393,7 @@ int ocpc_config_secondary_charger(int *desired_input_current, } } else if (batt.voltage < batt.desired_voltage) { if ((ph == PHASE_PRECHARGE) && - (current_ma > - batt_info->precharge_current)) { + (current_ma > batt_info->precharge_current)) { /* * Precharge phase is complete. Now set the * target VSYS to the battery voltage to prevent @@ -437,7 +433,6 @@ int ocpc_config_secondary_charger(int *desired_input_current, ph = ph == PHASE_CC ? PHASE_CV_TRIP : PHASE_CV_COMPLETE; if (ph == PHASE_CV_TRIP) i_ma_CC_CV = batt.current; - } } @@ -486,8 +481,7 @@ int ocpc_config_secondary_charger(int *desired_input_current, CPRINTS_DBG("min_vsys_target = %d", min_vsys_target); /* Obtain the drive from our PID controller. */ - if ((ocpc->last_vsys != OCPC_UNINIT) && - (ph > PHASE_PRECHARGE)) { + if ((ocpc->last_vsys != OCPC_UNINIT) && (ph > PHASE_PRECHARGE)) { drive = (k_p * error / k_p_div) + (k_i * ocpc->integral / k_i_div) + (k_d * derivative / k_d_div); @@ -521,23 +515,25 @@ int ocpc_config_secondary_charger(int *desired_input_current, * desired voltage. */ if (ph == PHASE_CV_TRIP) { - vsys_target = batt.desired_voltage + - ((i_ma_CC_CV * - ocpc->combined_rsys_rbatt_mo) / 1000); + vsys_target = + batt.desired_voltage + + ((i_ma_CC_CV * ocpc->combined_rsys_rbatt_mo) / 1000); CPRINTS_DBG("i_ma_CC_CV = %d", i_ma_CC_CV); } if (ph == PHASE_CV_COMPLETE) - vsys_target = batt.desired_voltage + - ((batt_info->precharge_current * - ocpc->combined_rsys_rbatt_mo) / 1000); + vsys_target = + batt.desired_voltage + ((batt_info->precharge_current * + ocpc->combined_rsys_rbatt_mo) / + 1000); /* * Ensure VSYS is no higher than the specified maximum battery voltage * plus the voltage drop across the system. */ - vsys_target = CLAMP(vsys_target, min_vsys_target, - batt_info->voltage_max + - (i_ma * ocpc->combined_rsys_rbatt_mo / 1000)); + vsys_target = + CLAMP(vsys_target, min_vsys_target, + batt_info->voltage_max + + (i_ma * ocpc->combined_rsys_rbatt_mo / 1000)); /* If we're input current limited, we cannot increase VSYS any more. */ CPRINTS_DBG("OCPC: Inst. Input Current: %dmA (Limit: %dmA)", @@ -550,7 +546,7 @@ int ocpc_config_secondary_charger(int *desired_input_current, * 95% of the limit. */ if (ocpc->secondary_ibus_ma >= - (*desired_input_current * 95 / 100)) + (*desired_input_current * 95 / 100)) icl_reached = true; } @@ -635,9 +631,8 @@ void ocpc_get_adcs(struct ocpc_data *ocpc) ocpc->isys_ma = val; } -__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { } @@ -647,8 +642,8 @@ static enum ec_error_list ocpc_precharge_enable(bool enable) int rv = charger_enable_linear_charge(CHARGER_PRIMARY, enable); if (rv) - CPRINTS("OCPC: Failed to %sble linear charge!", enable ? "ena" - : "dis"); + CPRINTS("OCPC: Failed to %sble linear charge!", + enable ? "ena" : "dis"); return rv; } @@ -669,8 +664,9 @@ void ocpc_reset(struct ocpc_data *ocpc) */ if (ocpc->active_chg_chip > CHARGER_PRIMARY) { voltage = (batt.voltage > 0 && - !(batt.flags & BATT_FLAG_BAD_VOLTAGE)) ? - batt.voltage : battery_get_info()->voltage_normal; + !(batt.flags & BATT_FLAG_BAD_VOLTAGE)) ? + batt.voltage : + battery_get_info()->voltage_normal; CPRINTS("OCPC: C%d Init VSYS to %dmV", ocpc->active_chg_chip, voltage); charger_set_voltage(ocpc->active_chg_chip, voltage); -- cgit v1.2.1 From 067760b8faefe131eeac9eb2364d0316e438daaf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:23 -0600 Subject: common/usb_host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e853198dc9980e249420f633dbdd58ac5dbee85 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729768 Reviewed-by: Jeremy Bettis --- common/usb_host_command.c | 43 ++++++++++++++++--------------------------- 1 file changed, 16 insertions(+), 27 deletions(-) diff --git a/common/usb_host_command.c b/common/usb_host_command.c index ccae57dd43..e4872750dd 100644 --- a/common/usb_host_command.c +++ b/common/usb_host_command.c @@ -16,7 +16,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_USB, outstr) -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, "USBHC: " format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOSTCMD, "USBHC: " format, ##args) enum usbhc_state { /* Not enabled (initial state, and when chipset is off) */ @@ -38,26 +38,16 @@ struct producer const hostcmd_producer; struct usb_stream_config const usbhc_stream; /* RX (Host->EC) queue */ -static struct queue const usb_to_hostcmd = QUEUE_DIRECT(64, - uint8_t, - usbhc_stream.producer, - hostcmd_consumer); +static struct queue const usb_to_hostcmd = + QUEUE_DIRECT(64, uint8_t, usbhc_stream.producer, hostcmd_consumer); /* TX (EC->Host) queue */ -static struct queue const hostcmd_to_usb = QUEUE_DIRECT(64, - uint8_t, - hostcmd_producer, - usbhc_stream.consumer); - -USB_STREAM_CONFIG_FULL(usbhc_stream, - USB_IFACE_HOSTCMD, - USB_CLASS_VENDOR_SPEC, - USB_SUBCLASS_GOOGLE_HOSTCMD, - USB_PROTOCOL_GOOGLE_HOSTCMD, - USB_STR_HOSTCMD_NAME, - USB_EP_HOSTCMD, - USB_MAX_PACKET_SIZE, - USB_MAX_PACKET_SIZE, - usb_to_hostcmd, +static struct queue const hostcmd_to_usb = + QUEUE_DIRECT(64, uint8_t, hostcmd_producer, usbhc_stream.consumer); + +USB_STREAM_CONFIG_FULL(usbhc_stream, USB_IFACE_HOSTCMD, USB_CLASS_VENDOR_SPEC, + USB_SUBCLASS_GOOGLE_HOSTCMD, USB_PROTOCOL_GOOGLE_HOSTCMD, + USB_STR_HOSTCMD_NAME, USB_EP_HOSTCMD, + USB_MAX_PACKET_SIZE, USB_MAX_PACKET_SIZE, usb_to_hostcmd, hostcmd_to_usb) static uint8_t in_msg[USBHC_MAX_REQUEST_SIZE]; @@ -94,7 +84,7 @@ static void usbhc_read(struct producer const *producer, size_t count) struct producer const hostcmd_producer = { .queue = &hostcmd_to_usb, - .ops = &((struct producer_ops const) { + .ops = &((struct producer_ops const){ .read = usbhc_read, }), }; @@ -229,7 +219,7 @@ static void usbhc_written(struct consumer const *consumer, size_t count) block_index += count; if (block_index < expected_size) - return; /* More to come. */ + return; /* More to come. */ if (IS_ENABLED(DEBUG)) CPRINTS("Rx complete (%d bytes)", block_index); @@ -247,13 +237,13 @@ static void usbhc_written(struct consumer const *consumer, size_t count) struct consumer const hostcmd_consumer = { .queue = &usb_to_hostcmd, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = usbhc_written, }), }; -static enum ec_status host_command_protocol_info( - struct host_cmd_handler_args *args) +static enum ec_status +host_command_protocol_info(struct host_cmd_handler_args *args) { struct ec_response_get_protocol_info *r = args->response; @@ -267,6 +257,5 @@ static enum ec_status host_command_protocol_info( return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - host_command_protocol_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info, EC_VER_MASK(0)); -- cgit v1.2.1 From ff068ef73ebd341c57f460e9b0879a6990ed8b03 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:40 -0600 Subject: util/genvif.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1950a607ad064924695f3ae94fb8d1316e268421 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730626 Reviewed-by: Jeremy Bettis --- util/genvif.h | 598 +++++++++++++++++++++++++++++----------------------------- 1 file changed, 299 insertions(+), 299 deletions(-) diff --git a/util/genvif.h b/util/genvif.h index b9b5ed77bd..2fb856beb4 100644 --- a/util/genvif.h +++ b/util/genvif.h @@ -24,399 +24,399 @@ struct vif_field_t { /* 3.2.15.2 Cable SVID Modes */ enum vif_cableSVIDModeList_indexes { - SVID_Mode_Enter, /* booleanFieldType */ - SVID_Mode_Recog_Mask, /* numericFieldType */ - SVID_Mode_Recog_Value, /* numericFieldType */ + SVID_Mode_Enter, /* booleanFieldType */ + SVID_Mode_Recog_Mask, /* numericFieldType */ + SVID_Mode_Recog_Value, /* numericFieldType */ CableSVID_Mode_Indexes }; struct vif_cableSVIDModeList_t { - struct vif_field_t vif_field[CableSVID_Mode_Indexes]; + struct vif_field_t vif_field[CableSVID_Mode_Indexes]; }; /* 3.2.15.1 Cable SVIDs */ enum vif_cableSVIDList_indexes { - SVID, /* numericFieldType */ - SVID_Num_Modes_Min, /* numericFieldType */ - SVID_Num_Modes_Max, /* numericFieldType */ - SVID_Modes_Fixed, /* booleanFieldType */ + SVID, /* numericFieldType */ + SVID_Num_Modes_Min, /* numericFieldType */ + SVID_Num_Modes_Max, /* numericFieldType */ + SVID_Modes_Fixed, /* booleanFieldType */ CableSVID_Indexes }; struct vif_cableSVIDList_t { - struct vif_field_t vif_field[CableSVID_Indexes]; + struct vif_field_t vif_field[CableSVID_Indexes]; struct vif_cableSVIDModeList_t - CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES]; + CableSVIDModeList[MAX_NUM_CABLE_SVID_MODES]; }; /* 3.2.12.2 SOP SVID Modes */ enum vif_sopSVIDModeList_indexes { - SVID_Mode_Enter_SOP, /* booleanFieldType */ - SVID_Mode_Recog_Mask_SOP, /* numericFieldType */ - SVID_Mode_Recog_Value_SOP, /* numericFieldType */ + SVID_Mode_Enter_SOP, /* booleanFieldType */ + SVID_Mode_Recog_Mask_SOP, /* numericFieldType */ + SVID_Mode_Recog_Value_SOP, /* numericFieldType */ SopSVID_Mode_Indexes }; struct vif_sopSVIDModeList_t { - struct vif_field_t vif_field[SopSVID_Mode_Indexes]; + struct vif_field_t vif_field[SopSVID_Mode_Indexes]; }; /* 3.2.12.1 SOP SVIDs */ enum vif_sopSVIDList_indexes { - SVID_SOP, /* numericFieldType */ - SVID_Num_Modes_Min_SOP, /* numericFieldType */ - SVID_Num_Modes_Max_SOP, /* numericFieldType */ - SVID_Modes_Fixed_SOP, /* booleanFieldType */ + SVID_SOP, /* numericFieldType */ + SVID_Num_Modes_Min_SOP, /* numericFieldType */ + SVID_Num_Modes_Max_SOP, /* numericFieldType */ + SVID_Modes_Fixed_SOP, /* booleanFieldType */ SopSVID_Indexes }; struct vif_sopSVIDList_t { - struct vif_field_t vif_field[SopSVID_Indexes]; + struct vif_field_t vif_field[SopSVID_Indexes]; - struct vif_sopSVIDModeList_t - SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES]; + struct vif_sopSVIDModeList_t SOPSVIDModeList[MAX_NUM_SOP_SVID_MODES]; }; /* 3.2.10.1 Sink PDOs */ enum vif_snkPdoList_indexes { - Snk_PDO_Supply_Type, /* numericFieldType */ - Snk_PDO_APDO_Type, /* numericFieldType */ - Snk_PDO_Voltage, /* numericFieldType */ - Snk_PDO_PDP_Rating, /* numericFieldType */ - Snk_PDO_Op_Power, /* numericFieldType */ - Snk_PDO_Min_Voltage, /* numericFieldType */ - Snk_PDO_Max_Voltage, /* numericFieldType */ - Snk_PDO_Op_Current, /* numericFieldType */ + Snk_PDO_Supply_Type, /* numericFieldType */ + Snk_PDO_APDO_Type, /* numericFieldType */ + Snk_PDO_Voltage, /* numericFieldType */ + Snk_PDO_PDP_Rating, /* numericFieldType */ + Snk_PDO_Op_Power, /* numericFieldType */ + Snk_PDO_Min_Voltage, /* numericFieldType */ + Snk_PDO_Max_Voltage, /* numericFieldType */ + Snk_PDO_Op_Current, /* numericFieldType */ Snk_PDO_Indexes }; struct vif_snkPdoList_t { - struct vif_field_t vif_field[Snk_PDO_Indexes]; + struct vif_field_t vif_field[Snk_PDO_Indexes]; }; /* 3.2.9.1 Source PDOs */ enum vif_srcPdoList_indexes { - Src_PDO_Supply_Type, /* numericFieldType */ - Src_PDO_APDO_Type, /* numericFieldType */ - Src_PDO_Peak_Current, /* numericFieldType */ - Src_PDO_Voltage, /* numericFieldType */ - Src_PDO_Max_Current, /* numericFieldType */ - Src_PDO_Min_Voltage, /* numericFieldType */ - Src_PDO_Max_Voltage, /* numericFieldType */ - Src_PDO_Max_Power, /* numericFieldType */ - Src_PD_OCP_OC_Debounce, /* numericFieldType */ - Src_PD_OCP_OC_Threshold, /* numericFieldType */ - Src_PD_OCP_UV_Debounce, /* numericFieldType */ - Src_PD_OCP_UV_Threshold_Type, /* numericFieldType */ - Src_PD_OCP_UV_Threshold, /* numericFieldType */ + Src_PDO_Supply_Type, /* numericFieldType */ + Src_PDO_APDO_Type, /* numericFieldType */ + Src_PDO_Peak_Current, /* numericFieldType */ + Src_PDO_Voltage, /* numericFieldType */ + Src_PDO_Max_Current, /* numericFieldType */ + Src_PDO_Min_Voltage, /* numericFieldType */ + Src_PDO_Max_Voltage, /* numericFieldType */ + Src_PDO_Max_Power, /* numericFieldType */ + Src_PD_OCP_OC_Debounce, /* numericFieldType */ + Src_PD_OCP_OC_Threshold, /* numericFieldType */ + Src_PD_OCP_UV_Debounce, /* numericFieldType */ + Src_PD_OCP_UV_Threshold_Type, /* numericFieldType */ + Src_PD_OCP_UV_Threshold, /* numericFieldType */ Src_PDO_Indexes }; struct vif_srcPdoList_t { - struct vif_field_t vif_field[Src_PDO_Indexes]; + struct vif_field_t vif_field[Src_PDO_Indexes]; }; /* 3.2.2.1.3 PCIe Endpoint Fields */ enum vif_PCIeEndpointListType_indexes { - USB4_PCIe_Endpoint_Vendor_ID, /* numericFieldType */ - USB4_PCIe_Endpoint_Device_ID, /* numericFieldType */ - USB4_PCIe_Endpoint_Class_Code, /* numericFieldType */ + USB4_PCIe_Endpoint_Vendor_ID, /* numericFieldType */ + USB4_PCIe_Endpoint_Device_ID, /* numericFieldType */ + USB4_PCIe_Endpoint_Class_Code, /* numericFieldType */ PCIe_Endpoint_Indexes }; struct vif_PCIeEndpointListType_t { - struct vif_field_t vif_field[PCIe_Endpoint_Indexes]; + struct vif_field_t vif_field[PCIe_Endpoint_Indexes]; }; /* 3.2.2.1.2 USB4 Router Fields */ enum vif_Usb4RouterListType_indexes { - USB4_Router_ID, /* numericFieldType */ - USB4_Silicon_VID, /* numericFieldType */ - USB4_Num_Lane_Adapters, /* numericFieldType */ - USB4_Num_USB3_DN_Adapters, /* numericFieldType */ - USB4_Num_DP_IN_Adapters, /* numericFieldType */ - USB4_Num_DP_OUT_Adapters, /* numericFieldType */ - USB4_Num_PCIe_DN_Adapters, /* numericFieldType */ - USB4_TBT3_Not_Supported, /* numericFieldType */ - USB4_PCIe_Wake_Supported, /* booleanFieldType */ - USB4_USB3_Wake_Supported, /* booleanFieldType */ - USB4_Num_Unused_Adapters, /* numericFieldType */ - USB4_TBT3_VID, /* numericFieldType */ - USB4_PCIe_Switch_Vendor_ID, /* numericFieldType */ - USB4_PCIe_Switch_Device_ID, /* numericFieldType */ - USB4_Num_PCIe_Endpoints, /* numericFieldType */ + USB4_Router_ID, /* numericFieldType */ + USB4_Silicon_VID, /* numericFieldType */ + USB4_Num_Lane_Adapters, /* numericFieldType */ + USB4_Num_USB3_DN_Adapters, /* numericFieldType */ + USB4_Num_DP_IN_Adapters, /* numericFieldType */ + USB4_Num_DP_OUT_Adapters, /* numericFieldType */ + USB4_Num_PCIe_DN_Adapters, /* numericFieldType */ + USB4_TBT3_Not_Supported, /* numericFieldType */ + USB4_PCIe_Wake_Supported, /* booleanFieldType */ + USB4_USB3_Wake_Supported, /* booleanFieldType */ + USB4_Num_Unused_Adapters, /* numericFieldType */ + USB4_TBT3_VID, /* numericFieldType */ + USB4_PCIe_Switch_Vendor_ID, /* numericFieldType */ + USB4_PCIe_Switch_Device_ID, /* numericFieldType */ + USB4_Num_PCIe_Endpoints, /* numericFieldType */ USB4_Router_Indexes }; struct vif_Usb4RouterListType_t { - struct vif_field_t vif_field[USB4_Router_Indexes]; + struct vif_field_t vif_field[USB4_Router_Indexes]; struct vif_PCIeEndpointListType_t - PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS]; + PCIeEndpointList[MAX_NUM_PCIE_ENDPOINTS]; }; /* 3.2.3 Component Fields */ enum vif_Component_indexes { - Component_Header, /* comment */ - Port_Label, /* nonEmptyString */ - Connector_Type, /* numericFieldType */ - USB4_Supported, /* booleanFieldType */ - USB4_Router_Index, /* numericFieldType */ - USB_PD_Support, /* booleanFieldType */ - PD_Port_Type, /* numericFieldType */ - Type_C_State_Machine, /* numericFieldType */ - Port_Battery_Powered, /* booleanFieldType */ - BC_1_2_Support, /* numericFieldType */ - Captive_Cable, /* booleanFieldType */ - Captive_Cable_Is_eMarked, /* booleanFieldType */ + Component_Header, /* comment */ + Port_Label, /* nonEmptyString */ + Connector_Type, /* numericFieldType */ + USB4_Supported, /* booleanFieldType */ + USB4_Router_Index, /* numericFieldType */ + USB_PD_Support, /* booleanFieldType */ + PD_Port_Type, /* numericFieldType */ + Type_C_State_Machine, /* numericFieldType */ + Port_Battery_Powered, /* booleanFieldType */ + BC_1_2_Support, /* numericFieldType */ + Captive_Cable, /* booleanFieldType */ + Captive_Cable_Is_eMarked, /* booleanFieldType */ /* 3.2.4 General PD Fields */ - General_PD_Header, /* comment */ - PD_Spec_Revision_Major, /* numericFieldType */ - PD_Spec_Revision_Minor, /* numericFieldType */ - PD_Spec_Version_Major, /* numericFieldType */ - PD_Spec_Version_Minor, /* numericFieldType */ - PD_Specification_Revision, /* numericFieldType */ + General_PD_Header, /* comment */ + PD_Spec_Revision_Major, /* numericFieldType */ + PD_Spec_Revision_Minor, /* numericFieldType */ + PD_Spec_Version_Major, /* numericFieldType */ + PD_Spec_Version_Minor, /* numericFieldType */ + PD_Specification_Revision, /* numericFieldType */ /* 3.2.4.1 SOP* Capabilities */ - SOP_Capable, /* booleanFieldType */ - SOP_P_Capable, /* booleanFieldType */ - SOP_PP_Capable, /* booleanFieldType */ - SOP_P_Debug_Capable, /* booleanFieldType */ - SOP_PP_Debug_Capable, /* booleanFieldType */ - - Manufacturer_Info_Supported_Port, /* booleanFieldType */ - Manufacturer_Info_VID_Port, /* numericFieldType */ - Manufacturer_Info_PID_Port, /* numericFieldType */ - Chunking_Implemented_SOP, /* booleanFieldType */ - Unchunked_Extended_Messages_Supported, /* booleanFieldType */ - Security_Msgs_Supported_SOP, /* booleanFieldType */ - Unconstrained_Power, /* booleanFieldType */ - Num_Fixed_Batteries, /* numericFieldType */ - Num_Swappable_Battery_Slots, /* numericFieldType */ - ID_Header_Connector_Type_SOP, /* numericFieldType */ + SOP_Capable, /* booleanFieldType */ + SOP_P_Capable, /* booleanFieldType */ + SOP_PP_Capable, /* booleanFieldType */ + SOP_P_Debug_Capable, /* booleanFieldType */ + SOP_PP_Debug_Capable, /* booleanFieldType */ + + Manufacturer_Info_Supported_Port, /* booleanFieldType */ + Manufacturer_Info_VID_Port, /* numericFieldType */ + Manufacturer_Info_PID_Port, /* numericFieldType */ + Chunking_Implemented_SOP, /* booleanFieldType */ + Unchunked_Extended_Messages_Supported, /* booleanFieldType */ + Security_Msgs_Supported_SOP, /* booleanFieldType */ + Unconstrained_Power, /* booleanFieldType */ + Num_Fixed_Batteries, /* numericFieldType */ + Num_Swappable_Battery_Slots, /* numericFieldType */ + ID_Header_Connector_Type_SOP, /* numericFieldType */ /* 3.2.4 General PD Fields */ - PD_Capabilities_Header, /* comment */ - USB_Comms_Capable, /* booleanFieldType */ - DR_Swap_To_DFP_Supported, /* booleanFieldType */ - DR_Swap_To_UFP_Supported, /* booleanFieldType */ - VCONN_Swap_To_On_Supported, /* booleanFieldType */ - VCONN_Swap_To_Off_Supported, /* booleanFieldType */ - Responds_To_Discov_SOP_UFP, /* booleanFieldType */ - Responds_To_Discov_SOP_DFP, /* booleanFieldType */ - Attempts_Discov_SOP, /* booleanFieldType */ - Power_Interruption_Available, /* numericFieldType */ - Data_Reset_Supported, /* booleanFieldType */ - Enter_USB_Supported, /* booleanFieldType */ + PD_Capabilities_Header, /* comment */ + USB_Comms_Capable, /* booleanFieldType */ + DR_Swap_To_DFP_Supported, /* booleanFieldType */ + DR_Swap_To_UFP_Supported, /* booleanFieldType */ + VCONN_Swap_To_On_Supported, /* booleanFieldType */ + VCONN_Swap_To_Off_Supported, /* booleanFieldType */ + Responds_To_Discov_SOP_UFP, /* booleanFieldType */ + Responds_To_Discov_SOP_DFP, /* booleanFieldType */ + Attempts_Discov_SOP, /* booleanFieldType */ + Power_Interruption_Available, /* numericFieldType */ + Data_Reset_Supported, /* booleanFieldType */ + Enter_USB_Supported, /* booleanFieldType */ /* 3.2.5 USB Type-C Fields */ - USB_Type_C_Header, /* comment */ - Type_C_Can_Act_As_Host, /* booleanFieldType */ - Type_C_Can_Act_As_Device, /* booleanFieldType */ + USB_Type_C_Header, /* comment */ + Type_C_Can_Act_As_Host, /* booleanFieldType */ + Type_C_Can_Act_As_Device, /* booleanFieldType */ /* 3.2.5 USB Type-C Fields */ - Type_C_Implements_Try_SRC, /* booleanFieldType */ - Type_C_Implements_Try_SNK, /* booleanFieldType */ - Type_C_Supports_Audio_Accessory, /* booleanFieldType */ - Type_C_Is_VCONN_Powered_Accessory, /* booleanFieldType */ - Type_C_Is_Debug_Target_SRC, /* booleanFieldType */ - Type_C_Is_Debug_Target_SNK, /* booleanFieldType */ - RP_Value, /* numericFieldType */ - Type_C_Supports_VCONN_Powered_Accessory,/* booleanFieldType */ - Type_C_Port_On_Hub, /* booleanFieldType */ - Type_C_Power_Source, /* numericFieldType */ - Type_C_Sources_VCONN, /* booleanFieldType */ - Type_C_Is_Alt_Mode_Controller, /* booleanFieldType */ - Type_C_Is_Alt_Mode_Adapter, /* booleanFieldType */ + Type_C_Implements_Try_SRC, /* booleanFieldType */ + Type_C_Implements_Try_SNK, /* booleanFieldType */ + Type_C_Supports_Audio_Accessory, /* booleanFieldType */ + Type_C_Is_VCONN_Powered_Accessory, /* booleanFieldType */ + Type_C_Is_Debug_Target_SRC, /* booleanFieldType */ + Type_C_Is_Debug_Target_SNK, /* booleanFieldType */ + RP_Value, /* numericFieldType */ + Type_C_Supports_VCONN_Powered_Accessory, /* booleanFieldType */ + Type_C_Port_On_Hub, /* booleanFieldType */ + Type_C_Power_Source, /* numericFieldType */ + Type_C_Sources_VCONN, /* booleanFieldType */ + Type_C_Is_Alt_Mode_Controller, /* booleanFieldType */ + Type_C_Is_Alt_Mode_Adapter, /* booleanFieldType */ /* 3.2.6 USB4 Port Fields (missing from output) */ - USB4_Port_Header, /* comment */ - USB4_Lane_0_Adapter, /* numericFieldType */ - USB4_Max_Speed, /* numericFieldType */ - USB4_DFP_Supported, /* booleanFieldType */ - USB4_UFP_Supported, /* booleanFieldType */ - USB4_USB3_Tunneling_Supported, /* booleanFieldType */ - USB4_DP_Tunneling_Supported, /* booleanFieldType */ - USB4_PCIe_Tunneling_Supported, /* booleanFieldType */ - USB4_TBT3_Compatibility_Supported, /* booleanFieldType */ - USB4_CL1_State_Supported, /* booleanFieldType */ - USB4_CL2_State_Supported, /* booleanFieldType */ - USB4_Num_Retimers, /* numericFieldType */ - USB4_DP_Bit_Rate, /* numericFieldType */ - USB4_Num_DP_Lanes, /* numericFieldType */ + USB4_Port_Header, /* comment */ + USB4_Lane_0_Adapter, /* numericFieldType */ + USB4_Max_Speed, /* numericFieldType */ + USB4_DFP_Supported, /* booleanFieldType */ + USB4_UFP_Supported, /* booleanFieldType */ + USB4_USB3_Tunneling_Supported, /* booleanFieldType */ + USB4_DP_Tunneling_Supported, /* booleanFieldType */ + USB4_PCIe_Tunneling_Supported, /* booleanFieldType */ + USB4_TBT3_Compatibility_Supported, /* booleanFieldType */ + USB4_CL1_State_Supported, /* booleanFieldType */ + USB4_CL2_State_Supported, /* booleanFieldType */ + USB4_Num_Retimers, /* numericFieldType */ + USB4_DP_Bit_Rate, /* numericFieldType */ + USB4_Num_DP_Lanes, /* numericFieldType */ /* 3.2.7 USB Data - Upstream Facing Port Fields */ - Device_Supports_USB_Data, /* booleanFieldType */ - Device_Speed, /* numericFieldType */ - Device_Contains_Captive_Retimer, /* booleanFieldType */ - Device_Truncates_DP_For_tDHPResponse, /* booleanFieldType */ - Device_Gen1x1_tLinkTurnaround, /* numericFieldType */ - Device_Gen2x1_tLinkTurnaround, /* numericFieldType */ + Device_Supports_USB_Data, /* booleanFieldType */ + Device_Speed, /* numericFieldType */ + Device_Contains_Captive_Retimer, /* booleanFieldType */ + Device_Truncates_DP_For_tDHPResponse, /* booleanFieldType */ + Device_Gen1x1_tLinkTurnaround, /* numericFieldType */ + Device_Gen2x1_tLinkTurnaround, /* numericFieldType */ /* 3.2.19 Product Power Fields */ - Product_Power_Header, /* comment */ - Product_Total_Source_Power_mW, /* numericFieldType */ - Port_Source_Power_Type, /* numericFieldType */ - Port_Source_Power_Gang, /* nonEmptyString */ - Port_Source_Power_Gang_Max_Power, /* numericFieldType */ + Product_Power_Header, /* comment */ + Product_Total_Source_Power_mW, /* numericFieldType */ + Port_Source_Power_Type, /* numericFieldType */ + Port_Source_Power_Gang, /* nonEmptyString */ + Port_Source_Power_Gang_Max_Power, /* numericFieldType */ /* 3.2.8 USB Data - Downstream Facing Port Fields */ - USB_Host_Header, /* comment */ - Host_Supports_USB_Data, /* booleanFieldType */ - Host_Speed, /* numericFieldType */ - Host_Contains_Captive_Retimer, /* booleanFieldType */ - Host_Truncates_DP_For_tDHPResponse, /* booleanFieldType */ - Host_Gen1x1_tLinkTurnaround, /* numericFieldType */ - Host_Gen2x1_tLinkTurnaround, /* numericFieldType */ - Host_Is_Embedded, /* booleanFieldType */ - Host_Suspend_Supported, /* booleanFieldType */ - Is_DFP_On_Hub, /* booleanFieldType */ - Hub_Port_Number, /* numericFieldType */ + USB_Host_Header, /* comment */ + Host_Supports_USB_Data, /* booleanFieldType */ + Host_Speed, /* numericFieldType */ + Host_Contains_Captive_Retimer, /* booleanFieldType */ + Host_Truncates_DP_For_tDHPResponse, /* booleanFieldType */ + Host_Gen1x1_tLinkTurnaround, /* numericFieldType */ + Host_Gen2x1_tLinkTurnaround, /* numericFieldType */ + Host_Is_Embedded, /* booleanFieldType */ + Host_Suspend_Supported, /* booleanFieldType */ + Is_DFP_On_Hub, /* booleanFieldType */ + Hub_Port_Number, /* numericFieldType */ /* 3.2.14 Battery Charging 1.2 Fields */ - BC_1_2_Header, /* comment */ - BC_1_2_Charging_Port_Type, /* numericFieldType */ + BC_1_2_Header, /* comment */ + BC_1_2_Charging_Port_Type, /* numericFieldType */ /* 3.2.9 PD Source Fields */ - PD_Source_Header, /* comment */ - PD_Power_As_Source, /* numericFieldType */ - EPR_Supported_As_Src, /* booleanFieldType */ - USB_Suspend_May_Be_Cleared, /* booleanFieldType */ - Sends_Pings, /* booleanFieldType */ - FR_Swap_Type_C_Current_Capability_As_Initial_Sink,/* numericFieldType */ - Master_Port, /* booleanFieldType */ - Num_Src_PDOs, /* numericFieldType */ - PD_OC_Protection, /* booleanFieldType */ - PD_OCP_Method, /* numericFieldType */ + PD_Source_Header, /* comment */ + PD_Power_As_Source, /* numericFieldType */ + EPR_Supported_As_Src, /* booleanFieldType */ + USB_Suspend_May_Be_Cleared, /* booleanFieldType */ + Sends_Pings, /* booleanFieldType */ + FR_Swap_Type_C_Current_Capability_As_Initial_Sink, /* numericFieldType + */ + Master_Port, /* booleanFieldType */ + Num_Src_PDOs, /* numericFieldType */ + PD_OC_Protection, /* booleanFieldType */ + PD_OCP_Method, /* numericFieldType */ /* insert: SrcPdoList */ /* 3.2.10 PD Sink Fields */ - PD_Sink_Header, /* comment */ - PD_Power_As_Sink, /* numericFieldType */ - EPR_Supported_As_Snk, /* booleanFieldType */ - No_USB_Suspend_May_Be_Set, /* booleanFieldType */ - GiveBack_May_Be_Set, /* booleanFieldType */ - Higher_Capability_Set, /* booleanFieldType */ - FR_Swap_Reqd_Type_C_Current_As_Initial_Source,/* numericFieldType */ - Num_Snk_PDOs, /* numericFieldType */ + PD_Sink_Header, /* comment */ + PD_Power_As_Sink, /* numericFieldType */ + EPR_Supported_As_Snk, /* booleanFieldType */ + No_USB_Suspend_May_Be_Set, /* booleanFieldType */ + GiveBack_May_Be_Set, /* booleanFieldType */ + Higher_Capability_Set, /* booleanFieldType */ + FR_Swap_Reqd_Type_C_Current_As_Initial_Source, /* numericFieldType */ + Num_Snk_PDOs, /* numericFieldType */ /* insert: SnkPdoList */ /* 3.2.11 PD Dual Role Fields */ - Dual_Role_Header, /* comment */ - Accepts_PR_Swap_As_Src, /* booleanFieldType */ - Accepts_PR_Swap_As_Snk, /* booleanFieldType */ - Requests_PR_Swap_As_Src, /* booleanFieldType */ - Requests_PR_Swap_As_Snk, /* booleanFieldType */ - FR_Swap_Supported_As_Initial_Sink, /* booleanFieldType */ + Dual_Role_Header, /* comment */ + Accepts_PR_Swap_As_Src, /* booleanFieldType */ + Accepts_PR_Swap_As_Snk, /* booleanFieldType */ + Requests_PR_Swap_As_Src, /* booleanFieldType */ + Requests_PR_Swap_As_Snk, /* booleanFieldType */ + FR_Swap_Supported_As_Initial_Sink, /* booleanFieldType */ /* 3.2.12 SOP Discover ID Fields */ - SOP_Discover_ID_Header, /* comment */ - XID_SOP, /* numericFieldType */ - Data_Capable_As_USB_Host_SOP, /* booleanFieldType */ - Data_Capable_As_USB_Device_SOP, /* booleanFieldType */ - Product_Type_UFP_SOP, /* numericFieldType */ - Product_Type_DFP_SOP, /* numericFieldType */ - DFP_VDO_Port_Number, /* numericFieldType */ - Modal_Operation_Supported_SOP, /* booleanFieldType */ - USB_VID_SOP, /* numericFieldType */ - PID_SOP, /* numericFieldType */ - bcdDevice_SOP, /* numericFieldType */ - Num_SVIDs_Min_SOP, /* numericFieldType */ - Num_SVIDs_Max_SOP, /* numericFieldType */ - SVID_Fixed_SOP, /* booleanFieldType */ + SOP_Discover_ID_Header, /* comment */ + XID_SOP, /* numericFieldType */ + Data_Capable_As_USB_Host_SOP, /* booleanFieldType */ + Data_Capable_As_USB_Device_SOP, /* booleanFieldType */ + Product_Type_UFP_SOP, /* numericFieldType */ + Product_Type_DFP_SOP, /* numericFieldType */ + DFP_VDO_Port_Number, /* numericFieldType */ + Modal_Operation_Supported_SOP, /* booleanFieldType */ + USB_VID_SOP, /* numericFieldType */ + PID_SOP, /* numericFieldType */ + bcdDevice_SOP, /* numericFieldType */ + Num_SVIDs_Min_SOP, /* numericFieldType */ + Num_SVIDs_Max_SOP, /* numericFieldType */ + SVID_Fixed_SOP, /* booleanFieldType */ /* 3.2.13 Alternate Mode Adapter (AMA) Fields */ - AMA_HW_Vers, /* numericFieldType */ - AMA_FW_Vers, /* numericFieldType */ - AMA_VCONN_Power, /* booleanFieldType */ - AMA_VCONN_Reqd, /* booleanFieldType */ - AMA_VBUS_Reqd, /* booleanFieldType */ - AMA_Superspeed_Support, /* numericFieldType */ + AMA_HW_Vers, /* numericFieldType */ + AMA_FW_Vers, /* numericFieldType */ + AMA_VCONN_Power, /* booleanFieldType */ + AMA_VCONN_Reqd, /* booleanFieldType */ + AMA_VBUS_Reqd, /* booleanFieldType */ + AMA_Superspeed_Support, /* numericFieldType */ /* 3.2.15 Cable/eMarker Fields */ - XID, /* numericFieldType */ - Data_Capable_As_USB_Host, /* booleanFieldType */ - Data_Capable_As_USB_Device, /* booleanFieldType */ - Product_Type, /* numericFieldType */ - Modal_Operation_Supported, /* booleanFieldType */ - USB_VID, /* numericFieldType */ - PID, /* numericFieldType */ - bcdDevice, /* numericFieldType */ - Cable_HW_Vers, /* numericFieldType */ - Cable_FW_Vers, /* numericFieldType */ - Type_C_To_Type_A_B_C, /* numericFieldType */ - Type_C_To_Type_C_Capt_Vdm_V2, /* numericFieldType */ - EPR_Mode_Capable, /* booleanFieldType */ - Cable_Latency, /* numericFieldType */ - Cable_Termination_Type, /* numericFieldType */ - Cable_VBUS_Current, /* numericFieldType */ - VBUS_Through_Cable, /* booleanFieldType */ - Cable_Superspeed_Support, /* numericFieldType */ - Cable_USB_Highest_Speed, /* numericFieldType */ - Max_VBUS_Voltage_Vdm_V2, /* numericFieldType */ - Manufacturer_Info_Supported, /* booleanFieldType */ - Manufacturer_Info_VID, /* numericFieldType */ - Manufacturer_Info_PID, /* numericFieldType */ - Chunking_Implemented, /* booleanFieldType */ - Security_Msgs_Supported, /* booleanFieldType */ - ID_Header_Connector_Type, /* numericFieldType */ - Cable_Num_SVIDs_Min, /* numericFieldType */ - Cable_Num_SVIDs_Max, /* numericFieldType */ - SVID_Fixed, /* booleanFieldType */ + XID, /* numericFieldType */ + Data_Capable_As_USB_Host, /* booleanFieldType */ + Data_Capable_As_USB_Device, /* booleanFieldType */ + Product_Type, /* numericFieldType */ + Modal_Operation_Supported, /* booleanFieldType */ + USB_VID, /* numericFieldType */ + PID, /* numericFieldType */ + bcdDevice, /* numericFieldType */ + Cable_HW_Vers, /* numericFieldType */ + Cable_FW_Vers, /* numericFieldType */ + Type_C_To_Type_A_B_C, /* numericFieldType */ + Type_C_To_Type_C_Capt_Vdm_V2, /* numericFieldType */ + EPR_Mode_Capable, /* booleanFieldType */ + Cable_Latency, /* numericFieldType */ + Cable_Termination_Type, /* numericFieldType */ + Cable_VBUS_Current, /* numericFieldType */ + VBUS_Through_Cable, /* booleanFieldType */ + Cable_Superspeed_Support, /* numericFieldType */ + Cable_USB_Highest_Speed, /* numericFieldType */ + Max_VBUS_Voltage_Vdm_V2, /* numericFieldType */ + Manufacturer_Info_Supported, /* booleanFieldType */ + Manufacturer_Info_VID, /* numericFieldType */ + Manufacturer_Info_PID, /* numericFieldType */ + Chunking_Implemented, /* booleanFieldType */ + Security_Msgs_Supported, /* booleanFieldType */ + ID_Header_Connector_Type, /* numericFieldType */ + Cable_Num_SVIDs_Min, /* numericFieldType */ + Cable_Num_SVIDs_Max, /* numericFieldType */ + SVID_Fixed, /* booleanFieldType */ /* 3.2.16 Active Cable Fields */ - Cable_SOP_PP_Controller, /* booleanFieldType */ - SBU_Supported, /* booleanFieldType */ - SBU_Type, /* numericFieldType */ - Active_Cable_Max_Operating_Temp, /* numericFieldType */ - Active_Cable_Shutdown_Temp, /* numericFieldType */ - Active_Cable_U3_CLd_Power, /* numericFieldType */ - Active_Cable_U3_U0_Trans_Mode, /* numericFieldType */ - Active_Cable_Physical_Connection, /* numericFieldType */ - Active_Cable_Active_Element, /* numericFieldType */ - Active_Cable_USB4_Support, /* booleanFieldType */ - Active_Cable_USB2_Supported, /* booleanFieldType */ - Active_Cable_USB2_Hub_Hops_Consumed, /* numericFieldType */ - Active_Cable_USB32_Supported, /* booleanFieldType */ - Active_Cable_USB_Lanes, /* numericFieldType */ - Active_Cable_Optically_Isolated, /* booleanFieldType */ - Active_Cable_USB_Gen, /* numericFieldType */ + Cable_SOP_PP_Controller, /* booleanFieldType */ + SBU_Supported, /* booleanFieldType */ + SBU_Type, /* numericFieldType */ + Active_Cable_Max_Operating_Temp, /* numericFieldType */ + Active_Cable_Shutdown_Temp, /* numericFieldType */ + Active_Cable_U3_CLd_Power, /* numericFieldType */ + Active_Cable_U3_U0_Trans_Mode, /* numericFieldType */ + Active_Cable_Physical_Connection, /* numericFieldType */ + Active_Cable_Active_Element, /* numericFieldType */ + Active_Cable_USB4_Support, /* booleanFieldType */ + Active_Cable_USB2_Supported, /* booleanFieldType */ + Active_Cable_USB2_Hub_Hops_Consumed, /* numericFieldType */ + Active_Cable_USB32_Supported, /* booleanFieldType */ + Active_Cable_USB_Lanes, /* numericFieldType */ + Active_Cable_Optically_Isolated, /* booleanFieldType */ + Active_Cable_USB_Gen, /* numericFieldType */ /* 3.2.17 VCONN Powered Devices */ - VPD_HW_Vers, /* numericFieldType */ - VPD_FW_Vers, /* numericFieldType */ - VPD_Max_VBUS_Voltage, /* numericFieldType */ - VPD_Charge_Through_Support, /* booleanFieldType */ - VPD_Charge_Through_Current, /* numericFieldType */ - VPD_VBUS_Impedance, /* numericFieldType */ - VPD_Ground_Impedance, /* numericFieldType */ + VPD_HW_Vers, /* numericFieldType */ + VPD_FW_Vers, /* numericFieldType */ + VPD_Max_VBUS_Voltage, /* numericFieldType */ + VPD_Charge_Through_Support, /* booleanFieldType */ + VPD_Charge_Through_Current, /* numericFieldType */ + VPD_VBUS_Impedance, /* numericFieldType */ + VPD_Ground_Impedance, /* numericFieldType */ /* 3.2.18 Repeater Fields */ - Repeater_One_Type, /* numericFieldType */ - Repeater_Two_Type, /* numericFieldType */ + Repeater_One_Type, /* numericFieldType */ + Repeater_Two_Type, /* numericFieldType */ Component_Indexes }; struct vif_Component_t { - struct vif_field_t vif_field[Component_Indexes]; + struct vif_field_t vif_field[Component_Indexes]; - struct vif_srcPdoList_t SrcPdoList[MAX_NUM_SRC_PDOS]; - struct vif_snkPdoList_t SnkPdoList[MAX_NUM_SNK_PDOS]; - struct vif_sopSVIDList_t SOPSVIDList[MAX_NUM_SOP_SVIDS]; - struct vif_cableSVIDList_t CableSVIDList[MAX_NUM_CABLE_SVIDS]; + struct vif_srcPdoList_t SrcPdoList[MAX_NUM_SRC_PDOS]; + struct vif_snkPdoList_t SnkPdoList[MAX_NUM_SNK_PDOS]; + struct vif_sopSVIDList_t SOPSVIDList[MAX_NUM_SOP_SVIDS]; + struct vif_cableSVIDList_t CableSVIDList[MAX_NUM_CABLE_SVIDS]; /* * The following fields are deprecated. They should not be written @@ -434,55 +434,55 @@ struct vif_Component_t { /* 3.2.2 Product Fields */ enum vif_Product_indexes { - USB4_Product_Header, /* comment */ - USB4_DROM_Vendor_ID, /* numericFieldType */ - USB4_Dock, /* booleanFieldType */ - USB4_Num_Internal_Host_Controllers, /* numericFieldType */ - USB4_Num_PCIe_DN_Bridges, /* numericFieldType */ - USB4_Device_HiFi_Bi_TMU_Mode_Required, /* booleanFieldType */ - USB4_Audio_Supported, /* booleanFieldType */ - USB4_HID_Supported, /* booleanFieldType */ - USB4_Printer_Supported, /* booleanFieldType */ - USB4_Mass_Storage_Supported, /* booleanFieldType */ - USB4_Video_Supported, /* booleanFieldType */ - USB4_Comms_Networking_Supported, /* booleanFieldType */ - USB4_Media_Transfer_Protocol_Supported, /* booleanFieldType */ - USB4_Smart_Card_Supported, /* booleanFieldType */ - USB4_Still_Image_Capture_Supported, /* booleanFieldType */ - USB4_Monitor_Device_Supported, /* booleanFieldType */ + USB4_Product_Header, /* comment */ + USB4_DROM_Vendor_ID, /* numericFieldType */ + USB4_Dock, /* booleanFieldType */ + USB4_Num_Internal_Host_Controllers, /* numericFieldType */ + USB4_Num_PCIe_DN_Bridges, /* numericFieldType */ + USB4_Device_HiFi_Bi_TMU_Mode_Required, /* booleanFieldType */ + USB4_Audio_Supported, /* booleanFieldType */ + USB4_HID_Supported, /* booleanFieldType */ + USB4_Printer_Supported, /* booleanFieldType */ + USB4_Mass_Storage_Supported, /* booleanFieldType */ + USB4_Video_Supported, /* booleanFieldType */ + USB4_Comms_Networking_Supported, /* booleanFieldType */ + USB4_Media_Transfer_Protocol_Supported, /* booleanFieldType */ + USB4_Smart_Card_Supported, /* booleanFieldType */ + USB4_Still_Image_Capture_Supported, /* booleanFieldType */ + USB4_Monitor_Device_Supported, /* booleanFieldType */ Product_Indexes }; struct vif_Product_t { - struct vif_field_t vif_field[Product_Indexes]; + struct vif_field_t vif_field[Product_Indexes]; struct vif_Usb4RouterListType_t USB4RouterList[MAX_NUM_USB4_ROUTERS]; }; enum vif_indexes { - VIF_Specification, /* version */ - Vendor_Name, /* nonEmptyString */ - Model_Part_Number, /* nonEmptyString */ - Product_Revision, /* nonEmptyString */ - TID, /* nonEmptyString */ - VIF_Product_Type, /* numericFieldType */ - Certification_Type, /* numericFieldType */ + VIF_Specification, /* version */ + Vendor_Name, /* nonEmptyString */ + Model_Part_Number, /* nonEmptyString */ + Product_Revision, /* nonEmptyString */ + TID, /* nonEmptyString */ + VIF_Product_Type, /* numericFieldType */ + Certification_Type, /* numericFieldType */ VIF_Indexes }; enum vif_app_indexes { - Vendor, /* nonEmptyString */ - Name, /* nonEmptyString */ - Version, /* version */ + Vendor, /* nonEmptyString */ + Name, /* nonEmptyString */ + Version, /* version */ VIF_App_Indexes }; struct vif_t { - struct vif_field_t vif_field[VIF_Indexes]; - struct vif_field_t vif_app_field[VIF_App_Indexes]; + struct vif_field_t vif_field[VIF_Indexes]; + struct vif_field_t vif_app_field[VIF_App_Indexes]; - struct vif_Product_t Product; - struct vif_Component_t Component[MAX_NUM_COMPONENTS]; + struct vif_Product_t Product; + struct vif_Component_t Component[MAX_NUM_COMPONENTS]; }; #endif /* __GENVIF_H__ */ -- cgit v1.2.1 From 93571549bc89e5468b7d5256b5fbd77e77033d8c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:03 -0600 Subject: util/ecst.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I97fe88b23c3fbc314b39c8b9e94c3e2f8047c613 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730616 Reviewed-by: Jeremy Bettis --- util/ecst.c | 874 ++++++++++++++++++++++++------------------------------------ 1 file changed, 344 insertions(+), 530 deletions(-) diff --git a/util/ecst.c b/util/ecst.c index 8d0ce940d6..3395f644a3 100644 --- a/util/ecst.c +++ b/util/ecst.c @@ -39,20 +39,21 @@ int is_mrider15 = FALSE; /* Chips information, RAM start address and RAM size. */ struct chip_info chip_info[] = { - [NPCX5M5G] = {NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE}, - [NPCX5M6G] = {NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE}, - [NPCX7M5] = {NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE}, - [NPCX7M6] = {NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE}, - [NPCX7M7] = {NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE}, - [NPCX9M3] = {NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE}, - [NPCX9M6] = {NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE}, + [NPCX5M5G] = { NPCX5M5G_RAM_ADDR, NPCX5M5G_RAM_SIZE }, + [NPCX5M6G] = { NPCX5M6G_RAM_ADDR, NPCX5M6G_RAM_SIZE }, + [NPCX7M5] = { NPCX7M5X_RAM_ADDR, NPCX7M5X_RAM_SIZE }, + [NPCX7M6] = { NPCX7M6X_RAM_ADDR, NPCX7M6X_RAM_SIZE }, + [NPCX7M7] = { NPCX7M7X_RAM_ADDR, NPCX7M7X_RAM_SIZE }, + [NPCX9M3] = { NPCX9M3X_RAM_ADDR, NPCX9M3X_RAM_SIZE }, + [NPCX9M6] = { NPCX9M6X_RAM_ADDR, NPCX9M6X_RAM_SIZE }, }; BUILD_ASSERT(ARRAY_SIZE(chip_info) == NPCX_CHIP_RAM_VAR_NONE); /* Support chips name strings */ -const char *supported_chips = "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, " - "npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, " - "npcx7m7wc, npcx9m3f or npcx9m6f"; +const char *supported_chips = + "npcx5m5g, npcx5m6g, npcx7m5g, npcx7m6g, " + "npcx7m6f, npcx7m6fb, npcx7m6fc, npcx7m7fc, npcx7m7wb, " + "npcx7m7wc, npcx9m3f or npcx9m6f"; static unsigned int calc_api_csum_bin(void); static unsigned int initialize_crc_32(void); @@ -70,16 +71,17 @@ static unsigned int finalize_crc_32(unsigned int crc); * and returns FALSE. */ static int splice_into_path(char *result, const char *path, int resultsz, - const char *prefix) { + const char *prefix) +{ char *last_delim, *result_last_delim; if (strlen(path) + strlen(prefix) + 1 > resultsz) { my_printf(TERR, - "\n\nfilename '%s' with prefix '%s' too long\n\n", - path, prefix); + "\n\nfilename '%s' with prefix '%s' too long\n\n", + path, prefix); my_printf(TINF, - "\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n", - strlen(path), strlen(prefix), resultsz); + "\n\n%zu + %zu + 1 needs to fit in %d bytes\n\n", + strlen(path), strlen(prefix), resultsz); return FALSE; } @@ -124,7 +126,7 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name) else if (str_cmp_no_case(chip_name, "npcx7m6fc") == 0) return NPCX7M6; else if (str_cmp_no_case(chip_name, "npcx7m6g") == 0) - return NPCX7M6; + return NPCX7M6; else if (str_cmp_no_case(chip_name, "npcx7m5g") == 0) return NPCX7M5; else if (str_cmp_no_case(chip_name, "npcx5m6g") == 0) @@ -149,7 +151,6 @@ static enum npcx_chip_ram_variant chip_to_ram_var(const char *chip_name) int main(int argc, char *argv[]) { - int mode_choose = FALSE; /* Do we get a bin File? */ int main_fw_hdr_flag = FALSE; @@ -160,7 +161,7 @@ int main(int argc, char *argv[]) /* Following variables: common to all modes */ int main_status = TRUE; - unsigned int main_temp = 0L; + unsigned int main_temp = 0L; char main_str_temp[TMP_STR_SIZE]; char *end_ptr; @@ -189,17 +190,15 @@ int main(int argc, char *argv[]) g_verbose = NO_VERBOSE; g_ram_start_address = chip_info[DEFAULT_CHIP].ram_addr; - g_ram_size = chip_info[DEFAULT_CHIP].ram_size; + g_ram_size = chip_info[DEFAULT_CHIP].ram_size; /* Set default values */ g_calc_type = CALC_TYPE_NONE; bin_params.spi_max_clk = SPI_MAX_CLOCK_DEFAULT; bin_params.spi_clk_ratio = 0x00; bin_params.spi_read_mode = SPI_READ_MODE_DEFAULT; - bin_params.fw_load_addr = - chip_info[DEFAULT_CHIP].ram_addr; - bin_params.fw_ep = - chip_info[DEFAULT_CHIP].ram_addr; + bin_params.fw_load_addr = chip_info[DEFAULT_CHIP].ram_addr; + bin_params.fw_ep = chip_info[DEFAULT_CHIP].ram_addr; bin_params.fw_err_detec_s_addr = FW_CRC_START_ADDR; bin_params.fw_err_detec_e_addr = FW_CRC_START_ADDR; bin_params.flash_size = FLASH_SIZE_DEFAULT; @@ -234,20 +233,18 @@ int main(int argc, char *argv[]) else if (str_cmp_no_case(hdr_args[arg_ind], "-vv") == 0) g_verbose = SUPER_VERBOSE; - else if (str_cmp_no_case(hdr_args[arg_ind], - "-mode") == 0) { + else if (str_cmp_no_case(hdr_args[arg_ind], "-mode") == 0) { mode_choose = TRUE; arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%s", main_str_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%s", main_str_temp) != + 1)) { my_printf(TERR, "\nCannot read operation mode"); my_printf(TERR, ", bt, bh or api. !\n"); main_status = FALSE; } else { /* bt, bh and api should not coexist */ - if (main_fw_hdr_flag || - main_api_flag || + if (main_fw_hdr_flag || main_api_flag || main_hdr_flag) { my_printf(TERR, "\nOperation modes bt"); my_printf(TERR, ", bh, and api should"); @@ -257,8 +254,8 @@ int main(int argc, char *argv[]) if (str_cmp_no_case(main_str_temp, "bt") == 0) main_fw_hdr_flag = TRUE; - else if (str_cmp_no_case(main_str_temp, - "bh") == 0) + else if (str_cmp_no_case(main_str_temp, "bh") == + 0) main_hdr_flag = TRUE; else if (str_cmp_no_case(main_str_temp, "api") == 0) @@ -266,8 +263,8 @@ int main(int argc, char *argv[]) else { my_printf(TERR, "\nInvalid operation mode "); - my_printf(TERR, - "(%s)\n", main_str_temp); + my_printf(TERR, "(%s)\n", + main_str_temp); main_status = FALSE; } } @@ -276,11 +273,10 @@ int main(int argc, char *argv[]) else if (str_cmp_no_case(hdr_args[arg_ind], "-chip") == 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%s", - main_str_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%s", main_str_temp) != + 1)) { my_printf(TERR, "\nCannot read chip name %s.\n", - supported_chips); + supported_chips); main_status = FALSE; } else { enum npcx_chip_ram_variant ram_variant; @@ -291,41 +287,38 @@ int main(int argc, char *argv[]) "\nInvalid chip name (%s) ", main_str_temp); my_printf(TERR, ", it should be %s.\n", - supported_chips); + supported_chips); main_status = FALSE; break; } - if ((bin_params.bin_params - & BIN_FW_LOAD_START_ADDR) == - 0x00000000) + if ((bin_params.bin_params & + BIN_FW_LOAD_START_ADDR) == 0x00000000) bin_params.fw_load_addr = - chip_info[ram_variant].ram_addr; + chip_info[ram_variant].ram_addr; - if ((bin_params.bin_params - & BIN_FW_ENTRY_POINT) == - 0x00000000) + if ((bin_params.bin_params & + BIN_FW_ENTRY_POINT) == 0x00000000) bin_params.fw_ep = - chip_info[ram_variant].ram_addr; + chip_info[ram_variant].ram_addr; g_ram_start_address = chip_info[ram_variant].ram_addr; - g_ram_size = - chip_info[ram_variant].ram_size; + g_ram_size = chip_info[ram_variant].ram_size; if ((ram_variant == NPCX5M5G) || - (ram_variant == NPCX5M6G)) { + (ram_variant == NPCX5M6G)) { is_mrider15 = TRUE; } } - /* -argfile Read argument file. File name must be after it.*/ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-argfile") == 0) { + /* -argfile Read argument file. File name must be after + * it.*/ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-argfile") == + 0) { arg_ind++; if (arg_ind < arg_num) { - strncpy(arg_file_name, - hdr_args[arg_ind], - sizeof(arg_file_name) - 1); + strncpy(arg_file_name, hdr_args[arg_ind], + sizeof(arg_file_name) - 1); arg_file_pointer = fopen(arg_file_name, "rt"); if (arg_file_pointer == NULL) { my_printf(TERR, @@ -340,16 +333,15 @@ int main(int argc, char *argv[]) (tmp_ind + arg_ind + 1) < arg_num; tmp_ind++) strncpy(tmp_hdr_args[tmp_ind], - hdr_args - [tmp_ind+arg_ind+1], + hdr_args[tmp_ind + + arg_ind + 1], ARG_SIZE); tmp_arg_num = tmp_ind; /* Read arguments from file to array */ for (arg_ind++; - fscanf(arg_file_pointer, - "%s", + fscanf(arg_file_pointer, "%s", hdr_args[arg_ind]) == 1; arg_ind++) ; @@ -359,9 +351,9 @@ int main(int argc, char *argv[]) /* Copy back the restored arguments. */ for (tmp_ind = 0; - (tmp_ind < tmp_arg_num) && - (arg_ind < MAX_ARGS); - tmp_ind++) { + (tmp_ind < tmp_arg_num) && + (arg_ind < MAX_ARGS); + tmp_ind++) { strncpy(hdr_args[arg_ind++], tmp_hdr_args[tmp_ind], ARG_SIZE); @@ -379,120 +371,113 @@ int main(int argc, char *argv[]) } else if (str_cmp_no_case(hdr_args[arg_ind], "-i") == 0) { arg_ind++; if (arg_ind < arg_num) { - strncpy(input_file_name, - hdr_args[arg_ind], - sizeof(input_file_name) - 1); + strncpy(input_file_name, hdr_args[arg_ind], + sizeof(input_file_name) - 1); } else { my_printf(TERR, "\nMissing Input File Name\n"); main_status = FALSE; } - /* -o Get output file name. */ + /* -o Get output file name. */ } else if (str_cmp_no_case(hdr_args[arg_ind], "-o") == 0) { arg_ind++; if (arg_ind < arg_num) { - strncpy(output_file_name, - hdr_args[arg_ind], + strncpy(output_file_name, hdr_args[arg_ind], sizeof(output_file_name) - 1); } else { my_printf(TERR, "\nMissing Output File Name.\n"); main_status = FALSE; } - /* -usearmrst get FW entry point from FW image offset 4.*/ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-usearmrst") == 0) { - if ((bin_params.bin_params & - BIN_FW_ENTRY_POINT) != 0x00000000) { + /* -usearmrst get FW entry point from FW image + * offset 4.*/ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-usearmrst") == + 0) { + if ((bin_params.bin_params & BIN_FW_ENTRY_POINT) != + 0x00000000) { my_printf(TERR, "\n-usearmrst not allowed, "); my_printf(TERR, "FW entry point already set "); my_printf(TERR, "using -fwep !\n"); main_status = FALSE; } else - bin_params.bin_params |= - BIN_FW_USER_ARM_RESET; - /* -nohcrs disable header CRC*/ + bin_params.bin_params |= BIN_FW_USER_ARM_RESET; + /* -nohcrs disable header CRC*/ } else if (str_cmp_no_case(hdr_args[arg_ind], "-nohcrc") == 0) - bin_params.bin_params |= - BIN_FW_HDR_CRC_DISABLE; + bin_params.bin_params |= BIN_FW_HDR_CRC_DISABLE; /* -ph merg header in BIN file. */ else if (str_cmp_no_case(hdr_args[arg_ind], "-ph") == 0) { - bin_params.bin_params |= - BIN_FW_HDR_OFFSET; - if ((strlen(hdr_args[arg_ind+1]) == 0) || - (sscanf(hdr_args[arg_ind+1], - "%x", - &main_temp) != 1)) + bin_params.bin_params |= BIN_FW_HDR_OFFSET; + if ((strlen(hdr_args[arg_ind + 1]) == 0) || + (sscanf(hdr_args[arg_ind + 1], "%x", &main_temp) != + 1)) bin_params.fw_hdr_offset = 0; else { arg_ind++; bin_params.fw_hdr_offset = main_temp; } - /* -spimaxclk Get SPI flash max clock. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-spimaxclk") == 0) { + /* -spimaxclk Get SPI flash max clock. */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-spimaxclk") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%d", &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%d", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read SPI Flash Max"); my_printf(TERR, " Clock !\n"); main_status = FALSE; } else bin_params.spi_max_clk = - (unsigned char) main_temp; - /* -spiclkratio Get SPI flash max clock ratio. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-spiclkratio") == 0) { + (unsigned char)main_temp; + /* -spiclkratio Get SPI flash max clock ratio. */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-spiclkratio") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%d", &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%d", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read SPI Clock Ratio\n"); main_status = FALSE; } else bin_params.spi_clk_ratio = - (unsigned char)main_temp; + (unsigned char)main_temp; - /* spireadmode get SPI read mode. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-spireadmode") == 0) { + /* spireadmode get SPI read mode. */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-spireadmode") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%20s", - main_str_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%20s", main_str_temp) != + 1)) { my_printf(TERR, "\nCannot read SPI Flash"); my_printf(TERR, " Read Mode !\n"); main_status = FALSE; } else { if (str_cmp_no_case(main_str_temp, - SPI_NORMAL_MODE_VAL) == 0) + SPI_NORMAL_MODE_VAL) == 0) bin_params.spi_read_mode = - (unsigned char) SPI_NORMAL_MODE; + (unsigned char)SPI_NORMAL_MODE; else if (str_cmp_no_case(main_str_temp, - SPI_SINGLE_MODE_VAL) == 0) + SPI_SINGLE_MODE_VAL) == + 0) bin_params.spi_read_mode = - (unsigned char) - SPI_SINGLE_MODE; + (unsigned char)SPI_SINGLE_MODE; else if (str_cmp_no_case(main_str_temp, - SPI_DUAL_MODE_VAL) == 0) + SPI_DUAL_MODE_VAL) == + 0) bin_params.spi_read_mode = - (unsigned char) - SPI_DUAL_MODE; + (unsigned char)SPI_DUAL_MODE; else if (str_cmp_no_case(main_str_temp, - SPI_QUAD_MODE_VAL) == 0) + SPI_QUAD_MODE_VAL) == + 0) bin_params.spi_read_mode = - (unsigned char) - SPI_QUAD_MODE; + (unsigned char)SPI_QUAD_MODE; else { my_printf(TERR, "\nInvalid SPI Flash Read "); my_printf(TERR, "Mode (%s), it should be ", main_str_temp); - my_printf(TERR, - "normal, singleMode, "); + my_printf(TERR, "normal, singleMode, "); my_printf(TERR, "dualMode or quadMode !\n"); main_status = FALSE; @@ -508,95 +493,88 @@ int main(int argc, char *argv[]) bin_params.bin_params |= BIN_FW_CRC_DISABLE; /* -fwloadaddr, Get the FW load address. */ - else if (str_cmp_no_case(hdr_args[arg_ind], - "-fwloadaddr") == 0) { + else if (str_cmp_no_case(hdr_args[arg_ind], "-fwloadaddr") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%x", - &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%x", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read FW Load "); my_printf(TERR, "\nstart address !\n"); main_status = FALSE; } else { /* Check that the address is 16-bytes aligned */ - if ((main_temp & - ADDR_16_BYTES_ALIGNED_MASK) != 0) { + if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) != + 0) { my_printf(TERR, "\nFW load address start "); my_printf(TERR, "address (0x%08X) is not ", main_temp); - my_printf(TERR, - "16-bytes aligned !\n"); + my_printf(TERR, "16-bytes aligned !\n"); main_status = FALSE; } else { - bin_params.fw_load_addr = - main_temp; + bin_params.fw_load_addr = main_temp; bin_params.bin_params |= - BIN_FW_LOAD_START_ADDR; + BIN_FW_LOAD_START_ADDR; } } - /* -fwep, Get the FW entry point. */ + /* -fwep, Get the FW entry point. */ } else if (str_cmp_no_case(hdr_args[arg_ind], "-fwep") == 0) { - if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET) - != 0x00000000) { - my_printf(TERR, - "\n-fwep not allowed, FW entry point"); + if ((bin_params.bin_params & BIN_FW_USER_ARM_RESET) != + 0x00000000) { + my_printf( + TERR, + "\n-fwep not allowed, FW entry point"); my_printf(TERR, " already set using -usearmrst!\n"); main_status = FALSE; } else { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%x", - &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%x", + &main_temp) != 1)) { my_printf(TERR, "\nCan't read FW E-Point\n"); main_status = FALSE; } else { - bin_params.fw_ep = - main_temp; + bin_params.fw_ep = main_temp; bin_params.bin_params |= - BIN_FW_ENTRY_POINT; + BIN_FW_ENTRY_POINT; } } - /* - * -crcstart, Get the address from where to calculate - * the FW CRC. - */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-crcstart") == 0) { + /* + * -crcstart, Get the address from where to calculate + * the FW CRC. + */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-crcstart") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%x", - &main_temp) != 1)) { - my_printf(TERR, - "\nCannot read FW CRC"); - my_printf(TERR, - " start address !\n"); + (sscanf(hdr_args[arg_ind], "%x", &main_temp) != + 1)) { + my_printf(TERR, "\nCannot read FW CRC"); + my_printf(TERR, " start address !\n"); main_status = FALSE; } else { bin_params.fw_err_detec_e_addr = bin_params.fw_err_detec_e_addr - - bin_params.fw_err_detec_s_addr - + main_temp; - bin_params.fw_err_detec_s_addr = - main_temp; + bin_params.fw_err_detec_s_addr + + main_temp; + bin_params.fw_err_detec_s_addr = main_temp; bin_params.bin_params |= BIN_FW_CKS_START; } - /* -crcsize, Get the area size that need to be CRCed. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-crcsize") == 0) { + /* -crcsize, Get the area size that need to be CRCed. + */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-crcsize") == + 0) { arg_ind++; main_temp = 0x00; if (hdr_args[arg_ind] == NULL) end_ptr = NULL; else - main_temp = strtol(hdr_args[arg_ind], - &end_ptr, 16); + main_temp = + strtol(hdr_args[arg_ind], &end_ptr, 16); if (hdr_args[arg_ind] == end_ptr) { my_printf(TERR, @@ -604,8 +582,8 @@ int main(int argc, char *argv[]) main_status = FALSE; } else { bin_params.fw_err_detec_e_addr = - bin_params.fw_err_detec_s_addr - + main_temp - 1; + bin_params.fw_err_detec_s_addr + + main_temp - 1; bin_params.bin_params |= BIN_FW_CKS_SIZE; } } @@ -613,9 +591,8 @@ int main(int argc, char *argv[]) else if (str_cmp_no_case(hdr_args[arg_ind], "-fwlen") == 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%x", - &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%x", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read FW length !\n"); main_status = FALSE; } else { @@ -624,25 +601,24 @@ int main(int argc, char *argv[]) } } /* flashsize, Get the flash size. */ - else if (str_cmp_no_case(hdr_args[arg_ind], - "-flashsize") == 0) { + else if (str_cmp_no_case(hdr_args[arg_ind], "-flashsize") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%d", - &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%d", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read Flash size !\n"); main_status = FALSE; } else bin_params.flash_size = main_temp; - /* -apisign, Get the method for error detect calculation. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-apisign") == 0) { + /* -apisign, Get the method for error detect + * calculation. */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-apisign") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%s", - main_str_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%s", main_str_temp) != + 1)) { my_printf(TERR, "\nCannot read API sign, CRC,"); my_printf(TERR, " CheckSum or None. !\n"); main_status = FALSE; @@ -666,23 +642,21 @@ int main(int argc, char *argv[]) main_str_temp); main_status = FALSE; } - } - /* -pointer, Get the FW image address. */ - } else if (str_cmp_no_case(hdr_args[arg_ind], - "-pointer") == 0) { + /* -pointer, Get the FW image address. */ + } else if (str_cmp_no_case(hdr_args[arg_ind], "-pointer") == + 0) { arg_ind++; if ((hdr_args[arg_ind] == NULL) || - (sscanf(hdr_args[arg_ind], - "%x", - &main_temp) != 1)) { + (sscanf(hdr_args[arg_ind], "%x", &main_temp) != + 1)) { my_printf(TERR, "\nCannot read FW Image address !\n"); main_status = FALSE; } else { /* Check that the address is 16-bytes aligned */ - if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) - != 0) { + if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) != + 0) { my_printf(TERR, "\nFW Image address (0x%08X)" " isn't 16-bytes aligned !\n", @@ -696,8 +670,7 @@ int main(int argc, char *argv[]) main_temp); my_printf(TERR, "is higher from flash size"); - my_printf(TERR, - " (0x%08X) !\n", + my_printf(TERR, " (0x%08X) !\n", MAX_FLASH_SIZE); main_status = FALSE; } else { @@ -713,8 +686,8 @@ int main(int argc, char *argv[]) if (hdr_args[arg_ind] == NULL) end_ptr = NULL; else - main_temp = strtol(hdr_args[arg_ind], - &end_ptr, 16); + main_temp = + strtol(hdr_args[arg_ind], &end_ptr, 16); if (hdr_args[arg_ind] == end_ptr) { my_printf(TERR, "\nCannot read BootLoader"); @@ -722,11 +695,12 @@ int main(int argc, char *argv[]) main_status = FALSE; } else { /* Check that the address is 16-bytes aligned */ - if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) - != 0) { - my_printf(TERR, - "\nFW Image address (0x%08X) ", - main_temp); + if ((main_temp & ADDR_16_BYTES_ALIGNED_MASK) != + 0) { + my_printf( + TERR, + "\nFW Image address (0x%08X) ", + main_temp); my_printf(TERR, "is not 16-bytes aligned!\n"); } @@ -737,8 +711,7 @@ int main(int argc, char *argv[]) main_temp); my_printf(TERR, " is higher from flash size"); - my_printf(TERR, - " (0x%08X) !\n", + my_printf(TERR, " (0x%08X) !\n", MAX_FLASH_SIZE); main_status = FALSE; } else { @@ -747,27 +720,25 @@ int main(int argc, char *argv[]) } } } else { - my_printf(TERR, - "\nUnknown flag: %s\n", + my_printf(TERR, "\nUnknown flag: %s\n", hdr_args[arg_ind]); main_status = FALSE; } } /* - * If the input and output file have the same name then exit with error. - */ + * If the input and output file have the same name then exit with error. + */ if (strcmp(output_file_name, input_file_name) == 0) { my_printf(TINF, - "Input file name (%s) should be differed from\n", - input_file_name); + "Input file name (%s) should be differed from\n", + input_file_name); my_printf(TINF, "Output file name (%s).\n", output_file_name); main_status = FALSE; } /* No problems reading argv? So go on... */ if (main_status) { - /* if output file already exist, then delete it. */ tmp_file = fopen(output_file_name, "w"); if (tmp_file != NULL) @@ -802,18 +773,17 @@ int main(int argc, char *argv[]) /* Say Bye Bye */ if (main_status) { my_printf(TPAS, "\n\n******************************"); - my_printf(TPAS, "\n*** SUCCESS ***"); - my_printf(TPAS, "\n******************************\n"); + my_printf(TPAS, "\n*** SUCCESS ***"); + my_printf(TPAS, "\n******************************\n"); exit(EXIT_SUCCESS); } else { my_printf(TERR, "\n\n******************************"); - my_printf(TERR, "\n*** FAILED ***"); - my_printf(TERR, "\n******************************\n"); + my_printf(TERR, "\n*** FAILED ***"); + my_printf(TERR, "\n******************************\n"); exit(EXIT_FAILURE); } - } /* @@ -930,12 +900,9 @@ void exit_with_usage(void) * Description: Copy the source file to the end of the destination file. *-------------------------------------------------------------------------- */ -int copy_file_to_file(char *dst_file_name, - char *src_file_name, - int offset, - int origin) +int copy_file_to_file(char *dst_file_name, char *src_file_name, int offset, + int origin) { - int index = 0; int result = 0; unsigned char local_val; @@ -1030,12 +997,9 @@ void my_printf(int error_level, char *fmt, ...) * Description: Writes to ELF or BIN files - whatever is open *-------------------------------------------------------------------------- */ -int write_to_file(unsigned int write_value, - unsigned int offset, - unsigned char num_of_bytes, - char *print_string) +int write_to_file(unsigned int write_value, unsigned int offset, + unsigned char num_of_bytes, char *print_string) { - int result = 0; int index; unsigned int localValue4; @@ -1046,32 +1010,23 @@ int write_to_file(unsigned int write_value, return FALSE; switch (num_of_bytes) { - case(1): + case (1): localValue1 = (unsigned char)write_value; - result = (int)(fwrite(&localValue1, 1, - 1, g_hfd_pointer)); - break; - case(2): + result = (int)(fwrite(&localValue1, 1, 1, g_hfd_pointer)); + break; + case (2): localValue2 = (unsigned short)write_value; - result = (int)(fwrite(&localValue2, - 2, - 1, - g_hfd_pointer)); + result = (int)(fwrite(&localValue2, 2, 1, g_hfd_pointer)); break; - case(4): + case (4): localValue4 = write_value; - result = (int)(fwrite(&localValue4, - 4, - 1, - g_hfd_pointer)); + result = (int)(fwrite(&localValue4, 4, 1, g_hfd_pointer)); break; default: /* Pad the same value N times. */ localValue1 = (unsigned char)write_value; for (index = 0; index < num_of_bytes; index++) - result = (int)(fwrite(&localValue1, - 1, - 1, + result = (int)(fwrite(&localValue1, 1, 1, g_hfd_pointer)); break; } @@ -1079,18 +1034,15 @@ int write_to_file(unsigned int write_value, my_printf(TINF, "\nIn write_to_file - %s", print_string); if (result) { - my_printf(TINF, - " - Offset %2d - value 0x%x", - offset, write_value); + my_printf(TINF, " - Offset %2d - value 0x%x", offset, + write_value); } else { - my_printf(TERR, - "\n\nCouldn't write %x to file at %x\n\n", - write_value, offset); + my_printf(TERR, "\n\nCouldn't write %x to file at %x\n\n", + write_value, offset); return FALSE; } return TRUE; - } /* @@ -1101,10 +1053,8 @@ int write_to_file(unsigned int write_value, * Description : Reads from open BIN file *-------------------------------------------------------------------------- */ -int read_from_file(unsigned int offset, - unsigned char size_to_read, - unsigned int *read_value, - char *print_string) +int read_from_file(unsigned int offset, unsigned char size_to_read, + unsigned int *read_value, char *print_string) { int result; unsigned int localValue4; @@ -1115,25 +1065,16 @@ int read_from_file(unsigned int offset, return FALSE; switch (size_to_read) { - case(1): - result = (int)(fread(&localValue1, - 1, - 1, - input_file_pointer)); + case (1): + result = (int)(fread(&localValue1, 1, 1, input_file_pointer)); *read_value = localValue1; break; - case(2): - result = (int)(fread(&localValue2, - 2, - 1, - input_file_pointer)); + case (2): + result = (int)(fread(&localValue2, 2, 1, input_file_pointer)); *read_value = localValue2; break; - case(4): - result = (int)(fread(&localValue4, - 4, - 1, - input_file_pointer)); + case (4): + result = (int)(fread(&localValue4, 4, 1, input_file_pointer)); *read_value = localValue4; break; default: @@ -1145,13 +1086,10 @@ int read_from_file(unsigned int offset, my_printf(TINF, "\nIn read_from_file - %s", print_string); if (result) { - my_printf(TINF, - " - Offset %d - value %x", - offset, *read_value); + my_printf(TINF, " - Offset %d - value %x", offset, *read_value); } else { - my_printf(TERR, - "\n\nCouldn't read from file at %x\n\n", - offset); + my_printf(TERR, "\n\nCouldn't read from file at %x\n\n", + offset); return FALSE; } @@ -1210,12 +1148,11 @@ void finalize_calculation(unsigned int *check_sum_crc) * given the previous checksum\crc *-------------------------------------------------------------------------- */ -void update_calculation(unsigned int *check_sum_crc, - unsigned char byte_to_add) +void update_calculation(unsigned int *check_sum_crc, unsigned char byte_to_add) { switch (g_calc_type) { case CALC_TYPE_NONE: - /* Do nothing */ + /* Do nothing */ break; case CALC_TYPE_CHECKSUM: *check_sum_crc += byte_to_add; @@ -1328,25 +1265,22 @@ int main_bin(struct tbinparams binary_params) bin_fw_offset = binary_params.fw_hdr_offset + HEADER_SIZE; my_printf(TINF, "\nBIN file: %s, size: %d (0x%x) bytes\n", - input_file_name, - bin_file_size_bytes, - bin_file_size_bytes); + input_file_name, bin_file_size_bytes, bin_file_size_bytes); /* Check validity of FW header offset. */ if (((int)binary_params.fw_hdr_offset < 0) || - (binary_params.fw_hdr_offset > bin_file_size_bytes)) { + (binary_params.fw_hdr_offset > bin_file_size_bytes)) { my_printf(TERR, "\nFW header offset 0x%08x (%d) should be in the" " range of 0 and file size (%d).\n", binary_params.fw_hdr_offset, - binary_params.fw_hdr_offset, - bin_file_size_bytes); + binary_params.fw_hdr_offset, bin_file_size_bytes); return FALSE; } /* Create the header file in the same directory as the input file. */ if (!splice_into_path(g_hdr_input_name, input_file_name, - sizeof(g_hdr_input_name), "hdr_")) + sizeof(g_hdr_input_name), "hdr_")) return FALSE; g_hfd_pointer = fopen(g_hdr_input_name, "w+b"); if (g_hfd_pointer == NULL) { @@ -1356,7 +1290,7 @@ int main_bin(struct tbinparams binary_params) if (strlen(output_file_name) == 0) { if (!splice_into_path(output_file_name, input_file_name, - sizeof(output_file_name), "out_")) + sizeof(output_file_name), "out_")) return FALSE; } @@ -1368,15 +1302,12 @@ int main_bin(struct tbinparams binary_params) ********************************************************************* */ /* Write the ancore. */ - if (!write_to_file(FW_HDR_ANCHOR, - HDR_ANCHOR_OFFSET, - 4, + if (!write_to_file(FW_HDR_ANCHOR, HDR_ANCHOR_OFFSET, 4, "HDR - FW Header ANCHOR ")) return FALSE; /* Write the extended anchor. */ if (binary_params.bin_params & BIN_FW_HDR_CRC_DISABLE) { - /* Write the ancore and the extended anchor. */ if (!write_to_file(FW_HDR_EXT_ANCHOR_DISABLE, HDR_EXTENDED_ANCHOR_OFFSET, 2, @@ -1409,14 +1340,13 @@ int main_bin(struct tbinparams binary_params) break; default: my_printf(TERR, "\n\nInvalid SPI Flash MAX clock (%d MHz) ", - binary_params.spi_max_clk); + binary_params.spi_max_clk); my_printf(TERR, "- it should be 20, 25, 33, 40 or 50 MHz"); return FALSE; } /* If SPI clock ratio set for MRIDER15, then it is error. */ if ((binary_params.spi_clk_ratio != 0x00) && (is_mrider15 == TRUE)) { - my_printf(TERR, "\nspiclkratio is not relevant for"); my_printf(TERR, " npcx5mng chips family !\n"); @@ -1439,13 +1369,13 @@ int main_bin(struct tbinparams binary_params) break; default: my_printf(TERR, "\n\nInvalid SPI Core Clock Ratio (%d) ", - binary_params.spi_clk_ratio); + binary_params.spi_clk_ratio); my_printf(TERR, "- it should be 1 or 2"); return FALSE; } if (!write_to_file(tmp_param, HDR_SPI_MAX_CLK_OFFSET, 1, - "HDR - SPI flash MAX Clock ")) + "HDR - SPI flash MAX Clock ")) return FALSE; /* Write the SPI flash Read Mode. */ @@ -1453,7 +1383,6 @@ int main_bin(struct tbinparams binary_params) /* If needed, set the unlimited burst bit. */ if (binary_params.bin_params & BIN_UNLIM_BURST_ENABLE) { if (is_mrider15 == TRUE) { - my_printf(TERR, "\nunlimburst is not relevant for"); my_printf(TERR, " npcx5mng chips family !\n"); @@ -1462,35 +1391,29 @@ int main_bin(struct tbinparams binary_params) tmp_param |= SPI_UNLIMITED_BURST_ENABLE; } - if (!write_to_file(tmp_param, - HDR_SPI_READ_MODE_OFFSET, 1, - "HDR - SPI flash Read Mode ")) + if (!write_to_file(tmp_param, HDR_SPI_READ_MODE_OFFSET, 1, + "HDR - SPI flash Read Mode ")) return FALSE; /* Write the error detection configuration. */ if (binary_params.bin_params & BIN_FW_CRC_DISABLE) { if (!write_to_file(FW_CRC_DISABLE, - HDR_ERR_DETECTION_CONF_OFFSET, - 1, + HDR_ERR_DETECTION_CONF_OFFSET, 1, "HDR - FW CRC Disabled ")) return FALSE; } else { /* Write the ancore and the extended anchor. */ - if (!write_to_file(FW_CRC_ENABLE, - HDR_ERR_DETECTION_CONF_OFFSET, 1, - "HDR - FW CRC Enabled ")) + if (!write_to_file(FW_CRC_ENABLE, HDR_ERR_DETECTION_CONF_OFFSET, + 1, "HDR - FW CRC Enabled ")) return FALSE; } /* FW entry point should be between the FW load address and RAM size */ - if ((binary_params.fw_load_addr > - (g_ram_start_address + g_ram_size)) || - (binary_params.fw_load_addr < g_ram_start_address)) { - my_printf(TERR, - "\nFW load address (0x%08x) should be between ", + if ((binary_params.fw_load_addr > (g_ram_start_address + g_ram_size)) || + (binary_params.fw_load_addr < g_ram_start_address)) { + my_printf(TERR, "\nFW load address (0x%08x) should be between ", binary_params.fw_load_addr); - my_printf(TERR, - "start (0x%08x) and end (0x%08x) of RAM ).", + my_printf(TERR, "start (0x%08x) and end (0x%08x) of RAM ).", g_ram_start_address, (g_ram_start_address + g_ram_size)); @@ -1499,8 +1422,8 @@ int main_bin(struct tbinparams binary_params) /* Write the FW load start address */ if (!write_to_file(binary_params.fw_load_addr, - HDR_FW_LOAD_START_ADDR_OFFSET, 4, - "HDR - FW load start address ")) + HDR_FW_LOAD_START_ADDR_OFFSET, 4, + "HDR - FW load start address ")) return FALSE; /* @@ -1512,25 +1435,22 @@ int main_bin(struct tbinparams binary_params) * size of the binary file minus the offset of the start of the * FW. */ - binary_params.fw_len = bin_file_size_bytes-bin_fw_offset; + binary_params.fw_len = bin_file_size_bytes - bin_fw_offset; } if ((int)binary_params.fw_len < 0) { my_printf(TERR, "\nFW length %d (0x%08x) should be greater than 0x0.", - binary_params.fw_len, - binary_params.fw_len); + binary_params.fw_len, binary_params.fw_len); return FALSE; } if (((int)binary_params.fw_len > - (bin_file_size_bytes - bin_fw_offset)) || - ((int)binary_params.fw_len > g_ram_size)) { - my_printf(TERR, - "\nFW length %d (0x%08x) should be within the", + (bin_file_size_bytes - bin_fw_offset)) || + ((int)binary_params.fw_len > g_ram_size)) { + my_printf(TERR, "\nFW length %d (0x%08x) should be within the", binary_params.fw_len, binary_params.fw_len); - my_printf(TERR, - " input-file (related to the FW offset)"); + my_printf(TERR, " input-file (related to the FW offset)"); my_printf(TERR, "\n (0x%08x) and within the RAM (RAM size: 0x%08x).", (bin_file_size_bytes - bin_fw_offset), g_ram_size); @@ -1538,61 +1458,48 @@ int main_bin(struct tbinparams binary_params) } if ((binary_params.bin_params & BIN_FW_USER_ARM_RESET) != 0x00000000) { - read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET), - 4, - &binary_params.fw_ep, - "read FW entry point for FW image "); - - if ((binary_params.fw_ep < - binary_params.fw_load_addr) || - (binary_params.fw_ep > - (binary_params.fw_load_addr + - binary_params.fw_len))) { + read_from_file((bin_fw_offset + ARM_FW_ENTRY_POINT_OFFSET), 4, + &binary_params.fw_ep, + "read FW entry point for FW image "); + + if ((binary_params.fw_ep < binary_params.fw_load_addr) || + (binary_params.fw_ep > + (binary_params.fw_load_addr + binary_params.fw_len))) { my_printf(TERR, "\nFW entry point (0x%08x) should be between", binary_params.fw_ep); - my_printf(TERR, - " the FW load address (0x%08x) ", + my_printf(TERR, " the FW load address (0x%08x) ", binary_params.fw_load_addr); - my_printf(TERR, - "and FW length (0x%08x).\n", + my_printf(TERR, "and FW length (0x%08x).\n", (binary_params.fw_load_addr + - binary_params.fw_len)); + binary_params.fw_len)); return FALSE; } } /* FW entry point should be between the FW load address and RAM size */ - if ((binary_params.fw_ep < - binary_params.fw_load_addr) || - (binary_params.fw_ep > - (binary_params.fw_load_addr + - binary_params.fw_len))) { + if ((binary_params.fw_ep < binary_params.fw_load_addr) || + (binary_params.fw_ep > + (binary_params.fw_load_addr + binary_params.fw_len))) { if (((binary_params.bin_params & BIN_FW_ENTRY_POINT) == - 0x00000000) && - ((binary_params.bin_params & - BIN_FW_LOAD_START_ADDR) != 0x00000000)) { - binary_params.fw_ep = - binary_params.fw_load_addr; + 0x00000000) && + ((binary_params.bin_params & BIN_FW_LOAD_START_ADDR) != + 0x00000000)) { + binary_params.fw_ep = binary_params.fw_load_addr; } else { - my_printf(TERR, - "\nFW entry point (0x%08x) should be ", + my_printf(TERR, "\nFW entry point (0x%08x) should be ", binary_params.fw_ep); - my_printf(TERR, - "\between the FW load address (0x%08x)", + my_printf(TERR, "\between the FW load address (0x%08x)", binary_params.fw_load_addr); - my_printf(TERR, - " and FW length (0x%08x).\n", + my_printf(TERR, " and FW length (0x%08x).\n", (binary_params.fw_load_addr + - binary_params.fw_len)); + binary_params.fw_len)); return FALSE; } } /* Write the FW entry point */ - if (!write_to_file(binary_params.fw_ep, - HDR_FW_ENTRY_POINT_OFFSET, - 4, + if (!write_to_file(binary_params.fw_ep, HDR_FW_ENTRY_POINT_OFFSET, 4, "HDR - FW Entry point ")) return FALSE; @@ -1602,17 +1509,15 @@ int main_bin(struct tbinparams binary_params) * In case the size was not set, then CRC end address is * the size of the binary file. */ - binary_params.fw_err_detec_e_addr = - binary_params.fw_len - 1; + binary_params.fw_err_detec_e_addr = binary_params.fw_len - 1; } else { /* CRC end address should be less than FW length. */ if (binary_params.fw_err_detec_e_addr > - (binary_params.fw_len - 1)) { + (binary_params.fw_len - 1)) { my_printf(TERR, "\nCRC end address (0x%08x) should be less ", binary_params.fw_err_detec_e_addr); - my_printf(TERR, - "than the FW length %d (0x%08x)", + my_printf(TERR, "than the FW length %d (0x%08x)", (binary_params.fw_len), (binary_params.fw_len)); return FALSE; @@ -1621,40 +1526,35 @@ int main_bin(struct tbinparams binary_params) /* Check CRC start and end addresses. */ if (binary_params.fw_err_detec_s_addr > - binary_params.fw_err_detec_e_addr) { + binary_params.fw_err_detec_e_addr) { my_printf(TERR, "\nCRC start address (0x%08x) should be less or ", binary_params.fw_err_detec_s_addr); my_printf(TERR, "equal to CRC end address (0x%08x)\nPlease check ", binary_params.fw_err_detec_e_addr); - my_printf(TERR, - "CRC start address and CRC size arguments."); + my_printf(TERR, "CRC start address and CRC size arguments."); return FALSE; } /* CRC start addr should be between the FW load address and RAM size */ - if (binary_params.fw_err_detec_s_addr > - binary_params.fw_len) { + if (binary_params.fw_err_detec_s_addr > binary_params.fw_len) { my_printf(TERR, "\nCRC start address (0x%08x) should ", binary_params.fw_err_detec_s_addr); - my_printf(TERR, "be FW length (0x%08x).", - binary_params.fw_len); + my_printf(TERR, "be FW length (0x%08x).", binary_params.fw_len); return FALSE; } /* Write the CRC start address */ if (!write_to_file(binary_params.fw_err_detec_s_addr, - HDR_FW_ERR_DETECT_START_ADDR_OFFSET, - 4, + HDR_FW_ERR_DETECT_START_ADDR_OFFSET, 4, "HDR - FW CRC Start ")) return FALSE; /* CRC end addr should be between the CRC start address and RAM size */ if ((binary_params.fw_err_detec_e_addr < - binary_params.fw_err_detec_s_addr) || - (binary_params.fw_err_detec_e_addr > - binary_params.fw_len)) { + binary_params.fw_err_detec_s_addr) || + (binary_params.fw_err_detec_e_addr > binary_params.fw_len)) { my_printf(TERR, "\nCRC end address (0x%08x) should be between the ", binary_params.fw_err_detec_e_addr); @@ -1667,8 +1567,7 @@ int main_bin(struct tbinparams binary_params) /* Write the CRC end address */ if (!write_to_file(binary_params.fw_err_detec_e_addr, - HDR_FW_ERR_DETECT_END_ADDR_OFFSET, - 4, + HDR_FW_ERR_DETECT_END_ADDR_OFFSET, 4, "HDR - FW CRC End ")) return FALSE; @@ -1678,22 +1577,18 @@ int main_bin(struct tbinparams binary_params) binary_params.fw_len += (16 - tmp_param); /* FW load address + FW length should be less than the RAM size. */ - if ((binary_params.fw_load_addr + - binary_params.fw_len) > - (g_ram_start_address + g_ram_size)) { + if ((binary_params.fw_load_addr + binary_params.fw_len) > + (g_ram_start_address + g_ram_size)) { my_printf(TERR, "\nFW load address + FW length should (0x%08x) be ", (binary_params.fw_load_addr + binary_params.fw_len)); - my_printf(TERR, - "less than the RAM size (0x%08x).", + my_printf(TERR, "less than the RAM size (0x%08x).", (g_ram_start_address + g_ram_size)); return FALSE; } /* Write the FW length */ - if (!write_to_file(binary_params.fw_len, - HDR_FW_LENGTH_OFFSET, - 4, + if (!write_to_file(binary_params.fw_len, HDR_FW_LENGTH_OFFSET, 4, "HDR - FW Length ")) return FALSE; @@ -1716,30 +1611,26 @@ int main_bin(struct tbinparams binary_params) break; default: my_printf(TERR, "\n\nInvalid Flash size (%d MBytes) -", - binary_params.flash_size); + binary_params.flash_size); my_printf(TERR, " it should be 1, 2, 4, 8 or 16 MBytes\n"); return FALSE; } - if (!write_to_file(tmp_param, - HDR_FLASH_SIZE_OFFSET, - 1, + if (!write_to_file(tmp_param, HDR_FLASH_SIZE_OFFSET, 1, "HDR - Flash size ")) return FALSE; /* Write the reserved bytes. */ if (!write_to_file(PAD_VALUE, HDR_RESERVED, 26, - "HDR - Reserved (26 bytes) ")) + "HDR - Reserved (26 bytes) ")) return FALSE; - /* Refresh the FW header bin file in order to calculate CRC */ if (g_hfd_pointer) { fclose(g_hfd_pointer); g_hfd_pointer = fopen(g_hdr_input_name, "r+b"); if (g_hfd_pointer == NULL) { - my_printf(TERR, - "\n\nCannot open %s\n\n", + my_printf(TERR, "\n\nCannot open %s\n\n", input_file_name); return FALSE; } @@ -1757,9 +1648,7 @@ int main_bin(struct tbinparams binary_params) binary_params.hdr_crc = 0; /* Write FW header CRC to header file */ - if (!write_to_file(binary_params.hdr_crc, - HDR_FW_HEADER_SIG_OFFSET, - 4, + if (!write_to_file(binary_params.hdr_crc, HDR_FW_HEADER_SIG_OFFSET, 4, "HDR - Header CRC ")) return FALSE; @@ -1767,11 +1656,11 @@ int main_bin(struct tbinparams binary_params) if ((binary_params.bin_params & BIN_FW_CRC_DISABLE) == 0) { /* Calculate ... */ g_calc_type = CALC_TYPE_CRC; - if (!calc_firmware_csum_bin(&binary_params.fw_crc, - (bin_fw_offset + - binary_params.fw_err_detec_s_addr), - (binary_params.fw_err_detec_e_addr - - binary_params.fw_err_detec_s_addr+1))) + if (!calc_firmware_csum_bin( + &binary_params.fw_crc, + (bin_fw_offset + binary_params.fw_err_detec_s_addr), + (binary_params.fw_err_detec_e_addr - + binary_params.fw_err_detec_s_addr + 1))) return FALSE; g_calc_type = CALC_TYPE_NONE; @@ -1779,9 +1668,7 @@ int main_bin(struct tbinparams binary_params) binary_params.fw_crc = 0; /* Write the FW CRC into file header file */ - if (!write_to_file(binary_params.fw_crc, - HDR_FW_IMAGE_SIG_OFFSET, - 4, + if (!write_to_file(binary_params.fw_crc, HDR_FW_IMAGE_SIG_OFFSET, 4, "HDR - FW CRC ")) return FALSE; @@ -1802,22 +1689,14 @@ int main_bin(struct tbinparams binary_params) fclose(output_file_pointer); if ((binary_params.bin_params & BIN_FW_HDR_OFFSET) != 0) { - copy_file_to_file(output_file_name, - input_file_name, - 0, - SEEK_SET); - copy_file_to_file(output_file_name, - g_hdr_input_name, - binary_params.fw_hdr_offset, + copy_file_to_file(output_file_name, input_file_name, 0, SEEK_SET); + copy_file_to_file(output_file_name, g_hdr_input_name, + binary_params.fw_hdr_offset, SEEK_SET); } else { - copy_file_to_file(output_file_name, - g_hdr_input_name, - 0, + copy_file_to_file(output_file_name, g_hdr_input_name, 0, SEEK_END); - copy_file_to_file(output_file_name, - input_file_name, - 0, + copy_file_to_file(output_file_name, input_file_name, 0, SEEK_END); } @@ -1848,20 +1727,16 @@ int calc_header_crc_bin(unsigned int *p_cksum) if (fseek(g_hfd_pointer, 0x00000000, SEEK_SET) < 0) return FALSE; - if (fread(g_header_array, - HEADER_SIZE, - 1, - g_hfd_pointer) != 1) + if (fread(g_header_array, HEADER_SIZE, 1, g_hfd_pointer) != 1) return FALSE; for (i = 0; i < (HEADER_SIZE - HEADER_CRC_FIELDS_SIZE); i++) { - /* * I had once the Verbose check inside the my_printf, but * it made ECST run sloooowwwwwly.... */ if (g_verbose == SUPER_VERBOSE) { - if (i%line_print_size == 0) + if (i % line_print_size == 0) my_printf(TDBG, "\n[%.4x]: ", i); my_printf(TDBG, "%.2x ", g_header_array[i]); @@ -1872,10 +1747,8 @@ int calc_header_crc_bin(unsigned int *p_cksum) if (g_verbose == SUPER_VERBOSE) { if ((i + 1) % line_print_size == 0) - my_printf(TDBG, - "FW Header ChecksumCRC = %.8x", - calc_header_checksum_crc); - + my_printf(TDBG, "FW Header ChecksumCRC = %.8x", + calc_header_checksum_crc); } } @@ -1895,11 +1768,9 @@ int calc_header_crc_bin(unsigned int *p_cksum) * Description: TBD ******************************************************************* */ -int calc_firmware_csum_bin(unsigned int *p_cksum, - unsigned int fw_offset, - unsigned int fw_length) +int calc_firmware_csum_bin(unsigned int *p_cksum, unsigned int fw_offset, + unsigned int fw_length) { - unsigned int i; unsigned int calc_read_bytes; unsigned int calc_num_of_bytes_to_read; @@ -1912,16 +1783,12 @@ int calc_firmware_csum_bin(unsigned int *p_cksum, calc_curr_position = fw_offset; if (g_verbose == REGULAR_VERBOSE) { - my_printf(TINF, - "\nFW Error Detect Start Dddress: 0x%08x", + my_printf(TINF, "\nFW Error Detect Start Dddress: 0x%08x", calc_curr_position); - my_printf(TINF, - "\nFW Error Detect End Dddress: 0x%08x", + my_printf(TINF, "\nFW Error Detect End Dddress: 0x%08x", calc_curr_position + calc_num_of_bytes_to_read - 1); - my_printf(TINF, - "\nFW Error Detect Size: %d (0x%X)", - calc_num_of_bytes_to_read, - calc_num_of_bytes_to_read); + my_printf(TINF, "\nFW Error Detect Size: %d (0x%X)", + calc_num_of_bytes_to_read, calc_num_of_bytes_to_read); } init_calculation(&calc_fw_checksum_crc); @@ -1932,13 +1799,10 @@ int calc_firmware_csum_bin(unsigned int *p_cksum, else calc_read_bytes = calc_num_of_bytes_to_read; - if (fseek(input_file_pointer, - calc_curr_position, SEEK_SET) < 0) + if (fseek(input_file_pointer, calc_curr_position, SEEK_SET) < 0) return 0; - if (fread(g_fw_array, - calc_read_bytes, - 1, - input_file_pointer) != 1) + if (fread(g_fw_array, calc_read_bytes, 1, input_file_pointer) != + 1) return 0; for (i = 0; i < calc_read_bytes; i++) { @@ -1947,9 +1811,8 @@ int calc_firmware_csum_bin(unsigned int *p_cksum, * but it made ECST run sloooowwwwwly.... */ if (g_verbose == SUPER_VERBOSE) { - if (i%line_print_size == 0) - my_printf(TDBG, - "\n[%.4x]: ", + if (i % line_print_size == 0) + my_printf(TDBG, "\n[%.4x]: ", calc_curr_position + i); my_printf(TDBG, "%.2x ", g_fw_array[i]); @@ -1960,8 +1823,7 @@ int calc_firmware_csum_bin(unsigned int *p_cksum, if (g_verbose == SUPER_VERBOSE) { if ((i + 1) % line_print_size == 0) - my_printf(TDBG, - "FW Checksum= %.8x", + my_printf(TDBG, "FW Checksum= %.8x", calc_fw_checksum_crc); } } @@ -2006,24 +1868,19 @@ int main_hdr(void) } if (strlen(output_file_name) == 0) - strncpy(tmp_file_name, - input_file_name, + strncpy(tmp_file_name, input_file_name, sizeof(tmp_file_name) - 1); else { - copy_file_to_file(output_file_name, - input_file_name, - 0, + copy_file_to_file(output_file_name, input_file_name, 0, SEEK_END); - strncpy(tmp_file_name, - output_file_name, + strncpy(tmp_file_name, output_file_name, sizeof(tmp_file_name) - 1); } /* Open Header file */ g_hdr_pointer = fopen(tmp_file_name, "r+b"); if (g_hdr_pointer == NULL) { - my_printf(TERR, - "\n\nCannot open %s file.\n\n", + my_printf(TERR, "\n\nCannot open %s file.\n\n", tmp_file_name); return FALSE; } @@ -2035,10 +1892,9 @@ int main_hdr(void) my_printf(TERR, "\n\nFW offset 0x%08x should be less than ", fw_offset); - my_printf(TERR, - "file size 0x%x (%d).\n\n", + my_printf(TERR, "file size 0x%x (%d).\n\n", bin_file_size_bytes, bin_file_size_bytes); - return FALSE; + return FALSE; } /* FW table should be less than file size. */ @@ -2046,7 +1902,7 @@ int main_hdr(void) my_printf(TERR, "\n\nFW table 0x%08x should be less ", ptr_fw_addr); my_printf(TERR, "than file size 0x%x (%d).\n\n", - bin_file_size_bytes, bin_file_size_bytes); + bin_file_size_bytes, bin_file_size_bytes); return FALSE; } @@ -2054,25 +1910,15 @@ int main_hdr(void) return FALSE; tmp_long_val = HDR_PTR_SIGNATURE; - result = (int)(fwrite(&tmp_long_val, - 4, - 1, - g_hdr_pointer)); - result |= (int)(fwrite(&ptr_fw_addr, - 4, - 1, - g_hdr_pointer)); + result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer)); + result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer)); if (result) { - my_printf(TINF, - "\nBootLoader Header file: %s\n", + my_printf(TINF, "\nBootLoader Header file: %s\n", tmp_file_name); - my_printf(TINF, - " Offset: 0x%08X, Signature: 0x%08X,", + my_printf(TINF, " Offset: 0x%08X, Signature: 0x%08X,", fw_offset, HDR_PTR_SIGNATURE); - my_printf(TINF, - " Pointer: 0x%08X\n", - ptr_fw_addr); + my_printf(TINF, " Pointer: 0x%08X\n", ptr_fw_addr); } else { my_printf(TERR, "\n\nCouldn't write signature (%x) and " @@ -2082,7 +1928,6 @@ int main_hdr(void) } } else { - if (strlen(output_file_name) == 0) { my_printf(TERR, "\n\nNo output file selected "); my_printf(TERR, "for BootLoader header file.\n\n"); @@ -2092,8 +1937,7 @@ int main_hdr(void) /* Open Output file */ g_hdr_pointer = fopen(output_file_name, "w+b"); if (g_hdr_pointer == NULL) { - my_printf(TERR, - "\n\nCannot open %s file.\n\n", + my_printf(TERR, "\n\nCannot open %s file.\n\n", output_file_name); return FALSE; } @@ -2102,23 +1946,15 @@ int main_hdr(void) return FALSE; tmp_long_val = HDR_PTR_SIGNATURE; - result = (int)(fwrite(&tmp_long_val, - 4, - 1, - g_hdr_pointer)); - result |= (int)(fwrite(&ptr_fw_addr, - 4, - 1, - g_hdr_pointer)); + result = (int)(fwrite(&tmp_long_val, 4, 1, g_hdr_pointer)); + result |= (int)(fwrite(&ptr_fw_addr, 4, 1, g_hdr_pointer)); if (result) { - my_printf(TINF, - "\nBootLoader Header file: %s\n", + my_printf(TINF, "\nBootLoader Header file: %s\n", output_file_name); my_printf(TINF, " Signature: 0x%08X, Pointer: 0x%08X\n", - HDR_PTR_SIGNATURE, - ptr_fw_addr); + HDR_PTR_SIGNATURE, ptr_fw_addr); } else { my_printf(TERR, "\n\nCouldn't write signature (%x) and ", @@ -2128,7 +1964,6 @@ int main_hdr(void) output_file_name); return FALSE; } - } /* Close if needed... */ @@ -2166,15 +2001,15 @@ int main_api(void) /* If API input file was not declared, then print error message. */ if (strlen(input_file_name) == 0) { - my_printf(TERR, + my_printf( + TERR, "\n\nNeed to define API input file, using -i flag\n\n"); return FALSE; - } if (strlen(output_file_name) == 0) { if (!splice_into_path(tmp_file_name, input_file_name, - sizeof(tmp_file_name), "api_")) + sizeof(tmp_file_name), "api_")) return FALSE; } else strncpy(tmp_file_name, output_file_name, @@ -2204,27 +2039,20 @@ int main_api(void) api_file_size_bytes = get_file_length(api_file_pointer); if (api_file_size_bytes < 0) return FALSE; - my_printf(TINF, - "\nAPI file: %s, size: %d bytes (0x%x)\n", - tmp_file_name, - api_file_size_bytes, - api_file_size_bytes); + my_printf(TINF, "\nAPI file: %s, size: %d bytes (0x%x)\n", + tmp_file_name, api_file_size_bytes, api_file_size_bytes); crc_checksum = calc_api_csum_bin(); if (fseek(api_file_pointer, api_file_size_bytes, SEEK_SET) < 0) return FALSE; - result = (int)(fwrite(&crc_checksum, - 4, - 1, - api_file_pointer)); + result = (int)(fwrite(&crc_checksum, 4, 1, api_file_pointer)); if (result) my_printf(TINF, "\nIn API BIN file - Offset 0x%08X - value 0x%08X", - api_file_size_bytes, - crc_checksum); + api_file_size_bytes, crc_checksum); else { my_printf(TERR, "\n\nCouldn't write %x to API BIN file at %08x\n\n", @@ -2241,7 +2069,6 @@ int main_api(void) return TRUE; } - /* ******************************************************************* * Function: calc_api_csum_bin @@ -2250,10 +2077,9 @@ int main_api(void) * Return: Return the CRC \ checksum, or "0" in case of fail. * Description: TBD ******************************************************************* -*/ + */ unsigned int calc_api_csum_bin(void) { - unsigned int i; unsigned int calc_read_bytes; int calc_num_of_bytes_to_read; @@ -2269,10 +2095,8 @@ unsigned int calc_api_csum_bin(void) my_printf(TDBG, "\nAPI CRC \\ Checksum First Byte Address: 0x%08x", calc_curr_position); - my_printf(TDBG, - "\nAPI CRC \\ Checksum Size: %d (0x%X)", - calc_num_of_bytes_to_read, - calc_num_of_bytes_to_read); + my_printf(TDBG, "\nAPI CRC \\ Checksum Size: %d (0x%X)", + calc_num_of_bytes_to_read, calc_num_of_bytes_to_read); } init_calculation(&calc_fw_checksum_crc); @@ -2283,13 +2107,10 @@ unsigned int calc_api_csum_bin(void) else calc_read_bytes = calc_num_of_bytes_to_read; - if (fseek(api_file_pointer, - calc_curr_position, SEEK_SET) < 0) + if (fseek(api_file_pointer, calc_curr_position, SEEK_SET) < 0) return 0; - if (fread(g_fw_array, - calc_read_bytes, - 1, - api_file_pointer) != 1) + if (fread(g_fw_array, calc_read_bytes, 1, api_file_pointer) != + 1) return 0; for (i = 0; i < calc_read_bytes; i++) { @@ -2298,10 +2119,9 @@ unsigned int calc_api_csum_bin(void) * but it made ecst run sloooowwwwwly.... */ if (g_verbose == SUPER_VERBOSE) { - if (i%line_print_size == 0) - my_printf(TDBG, - "\n[%.4x]: ", - calc_curr_position + i); + if (i % line_print_size == 0) + my_printf(TDBG, "\n[%.4x]: ", + calc_curr_position + i); my_printf(TDBG, "%.2x ", g_fw_array[i]); } @@ -2311,8 +2131,7 @@ unsigned int calc_api_csum_bin(void) if (g_verbose == SUPER_VERBOSE) { if ((i + 1) % line_print_size == 0) - my_printf(TDBG, - "FW Checksum= %.8x", + my_printf(TDBG, "FW Checksum= %.8x", calc_fw_checksum_crc); } } @@ -2323,14 +2142,13 @@ unsigned int calc_api_csum_bin(void) finalize_calculation(&calc_fw_checksum_crc); return calc_fw_checksum_crc; - } /* ************************************************************************** * CRC Handler ************************************************************************** -*/ + */ /* ******************************************************************* @@ -2343,7 +2161,7 @@ unsigned int calc_api_csum_bin(void) ******************************************************************* */ -#define P_32 0xEDB88320L +#define P_32 0xEDB88320L /* ******************************************************************* @@ -2394,7 +2212,7 @@ static void init_crc32_tab(void); unsigned int initialize_crc_32(void) { return 0xffffffffL; -} /* initialize_crc_32 */ +} /* initialize_crc_32 */ /* ******************************************************************* @@ -2410,7 +2228,6 @@ unsigned int initialize_crc_32(void) unsigned int update_crc_32(unsigned int crc, char c) { - unsigned int tmp, long_c; long_c = 0x000000ffL & (unsigned int)c; @@ -2423,7 +2240,7 @@ unsigned int update_crc_32(unsigned int crc, char c) return crc; -} /* update_crc_32 */ +} /* update_crc_32 */ /* ******************************************************************* @@ -2437,16 +2254,13 @@ unsigned int update_crc_32(unsigned int crc, char c) */ static void init_crc32_tab(void) { - int i, j; unsigned int crc; for (i = 0; i < 256; i++) { - crc = (unsigned int)i; for (j = 0; j < 8; j++) { - if (crc & 0x00000001L) crc = (crc >> 1) ^ P_32; else @@ -2458,7 +2272,7 @@ static void init_crc32_tab(void) crc_tab32_init = TRUE; -} /* init_crc32_tab */ +} /* init_crc32_tab */ /* ******************************************************************* @@ -2473,13 +2287,13 @@ static void init_crc32_tab(void) unsigned int finalize_crc_32(unsigned int crc) { - int i; unsigned int result = 0; for (i = 0; i < NUM_OF_BYTES; i++) - SET_VAR_BIT(result, NUM_OF_BYTES - (i+1), READ_VAR_BIT(crc, i)); + SET_VAR_BIT(result, NUM_OF_BYTES - (i + 1), + READ_VAR_BIT(crc, i)); return result; -} /* finalize_crc_32 */ +} /* finalize_crc_32 */ -- cgit v1.2.1 From 3fc2477991f72786457d7159d4e6f2585db7b0e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:55 -0600 Subject: board/grunt/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9893d4ac3e6df64074ad22b08fd4dd65be727a24 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728431 Reviewed-by: Jeremy Bettis --- board/grunt/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/grunt/board.h b/board/grunt/board.h index fe0d9e3d0f..2a002b0a31 100644 --- a/board/grunt/board.h +++ b/board/grunt/board.h @@ -16,7 +16,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -62,7 +62,7 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) #ifndef __ASSEMBLER__ -- cgit v1.2.1 From f83c5f887d241162f4fe372d685cfa1ce944339e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:20 -0600 Subject: board/dingdong/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0bebb89c4d1a550a57e99502e8ca833c96fbf09e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728225 Reviewed-by: Jeremy Bettis --- board/dingdong/usb_pd_policy.c | 56 ++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 32 deletions(-) diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c index 9bcc7f806f..c4054b1a18 100644 --- a/board/dingdong/usb_pd_policy.c +++ b/board/dingdong/usb_pd_policy.c @@ -20,8 +20,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Holds valid object position (opos) for entered mode */ static int alt_mode[PD_AMODE_COUNT]; @@ -69,28 +69,22 @@ int pd_check_power_swap(int port) return 0; } -int pd_check_data_swap(int port, - enum pd_data_role data_role) +int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always refuse data swap */ return 0; } -void pd_execute_data_swap(int port, - enum pd_data_role data_role) +void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Do nothing */ } -void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags) +void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { } /* ----------------- Vendor Defined Messages ------------------ */ @@ -103,8 +97,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 1, /* Vbus power required */ @@ -130,18 +124,16 @@ static int svdm_response_svids(int port, uint32_t *payload) #define OPOS_DP 1 #define OPOS_GFU 1 -const uint32_t vdo_dp_modes[1] = { - VDO_MODE_DP(0, /* UFP pin cfg supported : none */ +const uint32_t vdo_dp_modes[1] = { + VDO_MODE_DP(0, /* UFP pin cfg supported : none */ MODE_DP_PIN_E, /* DFP pin cfg supported */ - 1, /* no usb2.0 signalling in AMode */ - CABLE_PLUG, /* its a plug */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + 1, /* no usb2.0 signalling in AMode */ + CABLE_PLUG, /* its a plug */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; -const uint32_t vdo_goog_modes[1] = { - VDO_MODE_GOOGLE(MODE_GOOGLE_FU) -}; +const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) }; static int svdm_response_modes(int port, uint32_t *payload) { @@ -163,13 +155,14 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS_DP) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), - 0, /* power low */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power + low + */ 0x2); return 2; } @@ -249,8 +242,7 @@ const struct svdm_response svdm_rsp = { .exit_mode = &svdm_exit_mode, }; -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) +int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload) { int rsize; -- cgit v1.2.1 From e237e7e55e0314c0fb16377199b3d55f6c28f4f9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:16 -0600 Subject: board/kukui_scp/vdec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8798c310eba011be8ee7958d769fb0ca0a68cfea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728599 Reviewed-by: Jeremy Bettis --- board/kukui_scp/vdec.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/kukui_scp/vdec.h b/board/kukui_scp/vdec.h index 9cfb877e12..ddb7d1f36f 100644 --- a/board/kukui_scp/vdec.h +++ b/board/kukui_scp/vdec.h @@ -24,7 +24,8 @@ struct vdec_msg { unsigned char msg[48]; }; -BUILD_ASSERT(member_size(struct vdec_msg, msg) <= CONFIG_IPC_SHARED_OBJ_BUF_SIZE); +BUILD_ASSERT(member_size(struct vdec_msg, msg) <= + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void vdec_h264_service_init(void); -- cgit v1.2.1 From 9830d28010e176877a99ce349cfe03b97268888e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:48 -0600 Subject: board/ghost/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5fb4272452b1a5e5338feed376b4b8bb54672f05 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728406 Reviewed-by: Jeremy Bettis --- board/ghost/sensors.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/ghost/sensors.c b/board/ghost/sensors.c index 202f9c6ef8..a8e99ff582 100644 --- a/board/ghost/sensors.c +++ b/board/ghost/sensors.c @@ -81,8 +81,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -111,8 +111,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_AMBIENT \ - { \ +#define THERMAL_AMBIENT \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -142,8 +142,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(105), \ [EC_TEMP_THRESH_HALT] = C_TO_K(120), \ @@ -163,8 +163,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_WWAN \ - { \ +#define THERMAL_WWAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ -- cgit v1.2.1 From d66e2a482f1dec0aea779231b16ac358ad7231a6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:49 -0600 Subject: board/mrbland/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibb467ef1c9493262620ee537cc121da0e56aa4aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728708 Reviewed-by: Jeremy Bettis --- board/mrbland/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/mrbland/usbc_config.c b/board/mrbland/usbc_config.c index aac136415d..73666d087c 100644 --- a/board/mrbland/usbc_config.c +++ b/board/mrbland/usbc_config.c @@ -11,8 +11,8 @@ #include "console.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 199588f19d08e3268b2f21b4dffaa24c12eeab55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:36 -0600 Subject: util/uut/main.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d3d41bc5ac139b1eaade106937744cd54dcb90a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730664 Reviewed-by: Jeremy Bettis --- util/uut/main.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/util/uut/main.h b/util/uut/main.h index 2885e7368a..aa70eaa7ac 100644 --- a/util/uut/main.h +++ b/util/uut/main.h @@ -21,11 +21,11 @@ #define BASE_HEXADECIMAL 16 /* Verbose control messages display */ -#define DISPLAY_MSG(msg) \ -{ \ - if (verbose) \ - printf msg; \ -} +#define DISPLAY_MSG(msg) \ + { \ + if (verbose) \ + printf msg; \ + } #define SUCCESS true #define FAIL false -- cgit v1.2.1 From 6044839d7d73df71a9d9b27ce81460935ac3eb21 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:57 -0600 Subject: chip/stm32/usb_isochronous.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9cf362ccfe2cbd660a66e289a6134a026b0fa2b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729558 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_isochronous.h | 135 +++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 75 deletions(-) diff --git a/chip/stm32/usb_isochronous.h b/chip/stm32/usb_isochronous.h index efa4d94ab4..f751eb0b22 100644 --- a/chip/stm32/usb_isochronous.h +++ b/chip/stm32/usb_isochronous.h @@ -75,13 +75,9 @@ struct usb_isochronous_config; * * @return -EC_ERROR_CODE on failure, or number of bytes written on success. */ -int usb_isochronous_write_buffer( - struct usb_isochronous_config const *config, - const uint8_t *src, - size_t n, - size_t dst_offset, - int *buffer_id, - int commit); +int usb_isochronous_write_buffer(struct usb_isochronous_config const *config, + const uint8_t *src, size_t n, + size_t dst_offset, int *buffer_id, int commit); struct usb_isochronous_config { int endpoint; @@ -110,21 +106,15 @@ struct usb_isochronous_config { }; /* Define an USB isochronous interface */ -#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - TX_SIZE, \ - TX_CALLBACK, \ - SET_INTERFACE, \ - NUM_EXTRA_ENDPOINTS) \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - /* Declare buffer */ \ +#define USB_ISOCHRONOUS_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, TX_SIZE, \ + TX_CALLBACK, SET_INTERFACE, \ + NUM_EXTRA_ENDPOINTS) \ + BUILD_ASSERT(TX_SIZE > 0); \ + BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ + (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ + /* Declare buffer */ \ static usb_uint CONCAT2(NAME, _ep_tx_buffer_0)[TX_SIZE / 2] __usb_ram; \ static usb_uint CONCAT2(NAME, _ep_tx_buffer_1)[TX_SIZE / 2] __usb_ram; \ struct usb_isochronous_config const NAME = { \ @@ -136,62 +126,57 @@ struct usb_isochronous_config { CONCAT2(NAME, _ep_tx_buffer_0), \ CONCAT2(NAME, _ep_tx_buffer_1), \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 0, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_interface_descriptor \ - USB_CONF_DESC(CONCAT3(iface, INTERFACE, _1iface)) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 1, \ - .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x01 /* Isochronous IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 1, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_isochronous_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_isochronous_event(&NAME, evt); \ - } \ - static int CONCAT2(NAME, _handler)(usb_uint *rx, usb_uint *tx) \ - { \ - return usb_isochronous_iface_handler(&NAME, rx, tx); \ - } \ - USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_event)); \ + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 0, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_interface_descriptor USB_CONF_DESC( \ + CONCAT3(iface, INTERFACE, _1iface)) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 1, \ + .bNumEndpoints = 1 + NUM_EXTRA_ENDPOINTS, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x01 /* Isochronous IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 1, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_isochronous_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_isochronous_event(&NAME, evt); \ + } \ + static int CONCAT2(NAME, _handler)(usb_uint * rx, usb_uint * tx) \ + { \ + return usb_isochronous_iface_handler(&NAME, rx, tx); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _handler)); \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_tx), \ + CONCAT2(NAME, _ep_event)); void usb_isochronous_tx(struct usb_isochronous_config const *config); void usb_isochronous_event(struct usb_isochronous_config const *config, enum usb_ep_event event); int usb_isochronous_iface_handler(struct usb_isochronous_config const *config, - usb_uint *ep0_buf_rx, - usb_uint *ep0_buf_tx); + usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); #endif /* __CROS_EC_USB_ISOCHRONOUS_H */ -- cgit v1.2.1 From bd620239e73ab491598fc596a65a4171152699c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:58 -0600 Subject: baseboard/goroh/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5687eb4bde023694e16e31352341734d3faa2973 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727514 Reviewed-by: Jeremy Bettis --- baseboard/goroh/usbc_config.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/baseboard/goroh/usbc_config.c b/baseboard/goroh/usbc_config.c index 5a49d2ee2d..43f1513a3c 100644 --- a/baseboard/goroh/usbc_config.c +++ b/baseboard/goroh/usbc_config.c @@ -21,7 +21,7 @@ #include "gpio.h" #include "gpio_signal.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) #ifdef CONFIG_BRINGUP #define GPIO_SET_LEVEL(pin, lvl) gpio_set_level_verbose(CC_USBPD, pin, lvl) @@ -62,7 +62,6 @@ static int goroh_usb_c0_set_mux(const struct usb_mux *me, mux_state_t mux_state, mux_state = mux_state ^ USB_PD_MUX_POLARITY_INVERTED; return virtual_usb_mux_driver.set(me, mux_state, ack_required); - } static int goroh_usb_c0_get_mux(const struct usb_mux *me, @@ -128,7 +127,6 @@ void ppc_interrupt(enum gpio_signal signal) syv682x_interrupt(1); } - static void board_tcpc_init(void) { gpio_enable_interrupt(GPIO_USB_C0_FAULT_ODL); -- cgit v1.2.1 From b9490b7412d1473e3aabeb89fc853a021b5d023a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:48 -0600 Subject: board/nipperkin/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I856b7220e562e01d206b3036b0e9cce208093a5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728751 Reviewed-by: Jeremy Bettis --- board/nipperkin/board.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/nipperkin/board.h b/board/nipperkin/board.h index ce458113b2..3af121dac4 100644 --- a/board/nipperkin/board.h +++ b/board/nipperkin/board.h @@ -21,11 +21,11 @@ #define CONFIG_CMD_BUTTON /* USB Type C and USB PD defines */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Max Power = 100 W */ -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) #define CONFIG_CHARGER_PROFILE_OVERRIDE -- cgit v1.2.1 From 93399d3c6ac27c675d33ff46b4696b5cf0575595 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:33 -0600 Subject: include/rtc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie4657df4b5d194787cc07bbe9683a8df7cc710bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730400 Reviewed-by: Jeremy Bettis --- include/rtc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/rtc.h b/include/rtc.h index cff1ee0f64..1c75085840 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -10,14 +10,14 @@ #include "common.h" -#define SECS_PER_MINUTE 60 -#define SECS_PER_HOUR (60 * SECS_PER_MINUTE) -#define SECS_PER_DAY (24 * SECS_PER_HOUR) -#define SECS_PER_WEEK (7 * SECS_PER_DAY) -#define SECS_PER_YEAR (365 * SECS_PER_DAY) +#define SECS_PER_MINUTE 60 +#define SECS_PER_HOUR (60 * SECS_PER_MINUTE) +#define SECS_PER_DAY (24 * SECS_PER_HOUR) +#define SECS_PER_WEEK (7 * SECS_PER_DAY) +#define SECS_PER_YEAR (365 * SECS_PER_DAY) /* The seconds elapsed from 01-01-1970 to 01-01-2000 */ -#define SECS_TILL_YEAR_2K (946684800) -#define IS_LEAP_YEAR(x) \ +#define SECS_TILL_YEAR_2K (946684800) +#define IS_LEAP_YEAR(x) \ (((x) % 4 == 0) && (((x) % 100 != 0) || ((x) % 400 == 0))) struct calendar_date { -- cgit v1.2.1 From df13c1fa4711268e3c7a6542d9b8f6c1bd2f0b92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:26 -0600 Subject: board/gimble/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2e22c0fe454480e05d47666e5200dec3f8d20af2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728419 Reviewed-by: Jeremy Bettis --- board/gimble/usbc_config.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/gimble/usbc_config.c b/board/gimble/usbc_config.c index e747ab0df9..b67250f138 100644 --- a/board/gimble/usbc_config.c +++ b/board/gimble/usbc_config.c @@ -34,8 +34,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -160,12 +160,11 @@ void board_reset_pd_mcu(void) if (battery_hw_present()) gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C0_TCPC_RST_ODL, 1); gpio_set_level(GPIO_USB_C1_RT_RST_R_ODL, 1); - + /* wait for chips to come up */ msleep(PS8815_FW_INIT_DELAY_MS); } -- cgit v1.2.1 From 1a974a7248fa27ae661da660db27a6805579041c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:14 -0600 Subject: driver/ina2xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id5d28110f0b9b099011200710dc3e35ce4e2bc21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729981 Reviewed-by: Jeremy Bettis --- driver/ina2xx.h | 96 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 47 insertions(+), 49 deletions(-) diff --git a/driver/ina2xx.h b/driver/ina2xx.h index ec1e1ed92f..1fa3668114 100644 --- a/driver/ina2xx.h +++ b/driver/ina2xx.h @@ -8,28 +8,28 @@ #ifndef __CROS_EC_INA2XX_H #define __CROS_EC_INA2XX_H -#define INA2XX_REG_CONFIG 0x00 +#define INA2XX_REG_CONFIG 0x00 #define INA2XX_REG_SHUNT_VOLT 0x01 -#define INA2XX_REG_BUS_VOLT 0x02 -#define INA2XX_REG_POWER 0x03 -#define INA2XX_REG_CURRENT 0x04 -#define INA2XX_REG_CALIB 0x05 -#define INA2XX_REG_MASK 0x06 -#define INA2XX_REG_ALERT 0x07 - -#define INA2XX_CONFIG_MODE_MASK (7 << 0) -#define INA2XX_CONFIG_MODE_PWRDWN (0 << 0) -#define INA2XX_CONFIG_MODE_SHUNT BIT(0) -#define INA2XX_CONFIG_MODE_BUS BIT(1) -#define INA2XX_CONFIG_MODE_TRG (0 << 2) -#define INA2XX_CONFIG_MODE_CONT BIT(2) +#define INA2XX_REG_BUS_VOLT 0x02 +#define INA2XX_REG_POWER 0x03 +#define INA2XX_REG_CURRENT 0x04 +#define INA2XX_REG_CALIB 0x05 +#define INA2XX_REG_MASK 0x06 +#define INA2XX_REG_ALERT 0x07 + +#define INA2XX_CONFIG_MODE_MASK (7 << 0) +#define INA2XX_CONFIG_MODE_PWRDWN (0 << 0) +#define INA2XX_CONFIG_MODE_SHUNT BIT(0) +#define INA2XX_CONFIG_MODE_BUS BIT(1) +#define INA2XX_CONFIG_MODE_TRG (0 << 2) +#define INA2XX_CONFIG_MODE_CONT BIT(2) /* Conversion time for bus and shunt in micro-seconds */ enum ina2xx_conv_time { - INA2XX_CONV_TIME_140 = 0x00, - INA2XX_CONV_TIME_204 = 0x01, - INA2XX_CONV_TIME_332 = 0x02, - INA2XX_CONV_TIME_588 = 0x03, + INA2XX_CONV_TIME_140 = 0x00, + INA2XX_CONV_TIME_204 = 0x01, + INA2XX_CONV_TIME_332 = 0x02, + INA2XX_CONV_TIME_588 = 0x03, INA2XX_CONV_TIME_1100 = 0x04, INA2XX_CONV_TIME_2116 = 0x05, INA2XX_CONV_TIME_4156 = 0x06, @@ -37,29 +37,28 @@ enum ina2xx_conv_time { }; #define INA2XX_CONV_TIME_MASK 0x7 #define INA2XX_CONFIG_SHUNT_CONV_TIME(t) ((t) << 3) -#define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6) - -#define INA2XX_CONFIG_AVG_1 (0 << 9) -#define INA2XX_CONFIG_AVG_4 BIT(9) -#define INA2XX_CONFIG_AVG_16 (2 << 9) -#define INA2XX_CONFIG_AVG_64 (3 << 9) -#define INA2XX_CONFIG_AVG_128 (4 << 9) -#define INA2XX_CONFIG_AVG_256 (5 << 9) -#define INA2XX_CONFIG_AVG_512 (6 << 9) -#define INA2XX_CONFIG_AVG_1024 (7 << 9) - -#define INA2XX_MASK_EN_LEN BIT(0) -#define INA2XX_MASK_EN_APOL BIT(1) -#define INA2XX_MASK_EN_OVF BIT(2) -#define INA2XX_MASK_EN_CVRF BIT(3) -#define INA2XX_MASK_EN_AFF BIT(4) -#define INA2XX_MASK_EN_CNVR BIT(10) -#define INA2XX_MASK_EN_POL BIT(11) -#define INA2XX_MASK_EN_BUL BIT(12) -#define INA2XX_MASK_EN_BOL BIT(13) -#define INA2XX_MASK_EN_SUL BIT(14) -#define INA2XX_MASK_EN_SOL BIT(15) - +#define INA2XX_CONFIG_BUS_CONV_TIME(t) ((t) << 6) + +#define INA2XX_CONFIG_AVG_1 (0 << 9) +#define INA2XX_CONFIG_AVG_4 BIT(9) +#define INA2XX_CONFIG_AVG_16 (2 << 9) +#define INA2XX_CONFIG_AVG_64 (3 << 9) +#define INA2XX_CONFIG_AVG_128 (4 << 9) +#define INA2XX_CONFIG_AVG_256 (5 << 9) +#define INA2XX_CONFIG_AVG_512 (6 << 9) +#define INA2XX_CONFIG_AVG_1024 (7 << 9) + +#define INA2XX_MASK_EN_LEN BIT(0) +#define INA2XX_MASK_EN_APOL BIT(1) +#define INA2XX_MASK_EN_OVF BIT(2) +#define INA2XX_MASK_EN_CVRF BIT(3) +#define INA2XX_MASK_EN_AFF BIT(4) +#define INA2XX_MASK_EN_CNVR BIT(10) +#define INA2XX_MASK_EN_POL BIT(11) +#define INA2XX_MASK_EN_BUL BIT(12) +#define INA2XX_MASK_EN_BOL BIT(13) +#define INA2XX_MASK_EN_SUL BIT(14) +#define INA2XX_MASK_EN_SOL BIT(15) #if defined(CONFIG_INA231) && defined(CONFIG_INA219) #error CONFIG_INA231 and CONFIG_INA219 must not be both defined. @@ -68,28 +67,27 @@ enum ina2xx_conv_time { #ifdef CONFIG_INA231 /* Calibration value to get current LSB = 1mA */ -#define INA2XX_CALIB_1MA(rsense_mohm) (5120/(rsense_mohm)) +#define INA2XX_CALIB_1MA(rsense_mohm) (5120 / (rsense_mohm)) /* Bus voltage: mV per LSB */ -#define INA2XX_BUS_MV(reg) ((reg) * 125 / 100) +#define INA2XX_BUS_MV(reg) ((reg)*125 / 100) /* Shunt voltage: uV per LSB */ -#define INA2XX_SHUNT_UV(reg) ((reg) * 25 / 10) +#define INA2XX_SHUNT_UV(reg) ((reg)*25 / 10) /* Power LSB: mW per current LSB */ -#define INA2XX_POW_MW(reg) ((reg) * 25 * 1/*Current mA/LSB*/) +#define INA2XX_POW_MW(reg) ((reg)*25 * 1 /*Current mA/LSB*/) #else /* CONFIG_INA219 */ /* Calibration value to get current LSB = 1mA */ -#define INA2XX_CALIB_1MA(rsense_mohm) (40960/(rsense_mohm)) +#define INA2XX_CALIB_1MA(rsense_mohm) (40960 / (rsense_mohm)) /* Bus voltage: mV per LSB */ #define INA2XX_BUS_MV(reg) ((reg) / 2) /* Shunt voltage: uV */ -#define INA2XX_SHUNT_UV(reg) ((reg) * 10) +#define INA2XX_SHUNT_UV(reg) ((reg)*10) /* Power LSB: mW per current LSB */ -#define INA2XX_POW_MW(reg) ((reg) * 20 * 1/*Current mA/LSB*/) +#define INA2XX_POW_MW(reg) ((reg)*20 * 1 /*Current mA/LSB*/) #endif - /* Read INA2XX register. */ uint16_t ina2xx_read(uint8_t idx, uint8_t reg); -- cgit v1.2.1 From a3941716b31188264a8ba3ec408137e54eb488af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:56 -0600 Subject: test/compile_time_macros.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1a3a5056d5c90b84481e689b3fd786c300bdad15 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730494 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- test/compile_time_macros.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/test/compile_time_macros.c b/test/compile_time_macros.c index 7d4bee4aa6..f02fc366a4 100644 --- a/test/compile_time_macros.c +++ b/test/compile_time_macros.c @@ -9,10 +9,9 @@ #include "common.h" #include "test_util.h" - static int test_BIT(void) { - TEST_EQ(BIT(0), 0x00000001U, "%u"); + TEST_EQ(BIT(0), 0x00000001U, "%u"); TEST_EQ(BIT(25), 0x02000000U, "%u"); TEST_EQ(BIT(31), 0x80000000U, "%u"); @@ -21,7 +20,7 @@ static int test_BIT(void) static int test_BIT_ULL(void) { - TEST_EQ(BIT_ULL(0), 0x0000000000000001ULL, "%Lu"); + TEST_EQ(BIT_ULL(0), 0x0000000000000001ULL, "%Lu"); TEST_EQ(BIT_ULL(25), 0x0000000002000000ULL, "%Lu"); TEST_EQ(BIT_ULL(50), 0x0004000000000000ULL, "%Lu"); TEST_EQ(BIT_ULL(63), 0x8000000000000000ULL, "%Lu"); @@ -70,10 +69,10 @@ static int test_WRITE_BIT(void) static int test_GENMASK(void) { - TEST_EQ(GENMASK(0, 0), 0x00000001U, "%u"); - TEST_EQ(GENMASK(31, 0), 0xFFFFFFFFU, "%u"); - TEST_EQ(GENMASK(4, 4), 0x00000010U, "%u"); - TEST_EQ(GENMASK(4, 0), 0x0000001FU, "%u"); + TEST_EQ(GENMASK(0, 0), 0x00000001U, "%u"); + TEST_EQ(GENMASK(31, 0), 0xFFFFFFFFU, "%u"); + TEST_EQ(GENMASK(4, 4), 0x00000010U, "%u"); + TEST_EQ(GENMASK(4, 0), 0x0000001FU, "%u"); TEST_EQ(GENMASK(21, 21), 0x00200000U, "%u"); TEST_EQ(GENMASK(31, 31), 0x80000000U, "%u"); @@ -82,11 +81,11 @@ static int test_GENMASK(void) static int test_GENMASK_ULL(void) { - TEST_EQ(GENMASK_ULL(0, 0), 0x0000000000000001ULL, "%Lu"); - TEST_EQ(GENMASK_ULL(31, 0), 0x00000000FFFFFFFFULL, "%Lu"); - TEST_EQ(GENMASK_ULL(63, 0), 0xFFFFFFFFFFFFFFFFULL, "%Lu"); - TEST_EQ(GENMASK_ULL(4, 4), 0x0000000000000010ULL, "%Lu"); - TEST_EQ(GENMASK_ULL(4, 0), 0x000000000000001FULL, "%Lu"); + TEST_EQ(GENMASK_ULL(0, 0), 0x0000000000000001ULL, "%Lu"); + TEST_EQ(GENMASK_ULL(31, 0), 0x00000000FFFFFFFFULL, "%Lu"); + TEST_EQ(GENMASK_ULL(63, 0), 0xFFFFFFFFFFFFFFFFULL, "%Lu"); + TEST_EQ(GENMASK_ULL(4, 4), 0x0000000000000010ULL, "%Lu"); + TEST_EQ(GENMASK_ULL(4, 0), 0x000000000000001FULL, "%Lu"); TEST_EQ(GENMASK_ULL(21, 21), 0x0000000000200000ULL, "%Lu"); TEST_EQ(GENMASK_ULL(31, 31), 0x0000000080000000ULL, "%Lu"); TEST_EQ(GENMASK_ULL(63, 63), 0x8000000000000000ULL, "%Lu"); -- cgit v1.2.1 From 4f2857715031c3c5c96db22a70535e06f2aeb9e6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:44 -0600 Subject: chip/stm32/usb_hid_hw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9acf30a59cba1b57a21a444ab343339c4d9e9a54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729576 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_hid_hw.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/chip/stm32/usb_hid_hw.h b/chip/stm32/usb_hid_hw.h index a36a66567e..d4df34073d 100644 --- a/chip/stm32/usb_hid_hw.h +++ b/chip/stm32/usb_hid_hw.h @@ -25,10 +25,8 @@ struct usb_hid_config_t { * @param buffer_size: handler should set it to the size of returned * buffer. */ - int (*get_report)(uint8_t report_id, - uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size); + int (*get_report)(uint8_t report_id, uint8_t report_type, + const uint8_t **buffer_ptr, int *buffer_size); }; /* internal callbacks for HID class drivers */ -- cgit v1.2.1 From fdbc22f13a055865a833eaca8d7f01513a73a612 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:53 -0600 Subject: common/usb_update.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24bcd0be35fc2b986c8d4138e4fddd1588b8464c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729780 Reviewed-by: Jeremy Bettis --- common/usb_update.c | 114 ++++++++++++++++++++++++---------------------------- 1 file changed, 52 insertions(+), 62 deletions(-) diff --git a/common/usb_update.c b/common/usb_update.c index 3b307ede9a..7b463318b8 100644 --- a/common/usb_update.c +++ b/common/usb_update.c @@ -20,8 +20,8 @@ #include "usb-stream.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* * This file is an adaptation layer between the USB interface and the firmware @@ -47,37 +47,27 @@ struct consumer const update_consumer; struct usb_stream_config const usb_update; -static struct queue const update_to_usb = QUEUE_DIRECT(64, uint8_t, - null_producer, - usb_update.consumer); -static struct queue const usb_to_update = QUEUE_DIRECT(64, uint8_t, - usb_update.producer, - update_consumer); - -USB_STREAM_CONFIG_FULL(usb_update, - USB_IFACE_UPDATE, - USB_CLASS_VENDOR_SPEC, - USB_SUBCLASS_GOOGLE_UPDATE, - USB_PROTOCOL_GOOGLE_UPDATE, - USB_STR_UPDATE_NAME, - USB_EP_UPDATE, - USB_MAX_PACKET_SIZE, - USB_MAX_PACKET_SIZE, - usb_to_update, - update_to_usb) +static struct queue const update_to_usb = + QUEUE_DIRECT(64, uint8_t, null_producer, usb_update.consumer); +static struct queue const usb_to_update = + QUEUE_DIRECT(64, uint8_t, usb_update.producer, update_consumer); +USB_STREAM_CONFIG_FULL(usb_update, USB_IFACE_UPDATE, USB_CLASS_VENDOR_SPEC, + USB_SUBCLASS_GOOGLE_UPDATE, USB_PROTOCOL_GOOGLE_UPDATE, + USB_STR_UPDATE_NAME, USB_EP_UPDATE, USB_MAX_PACKET_SIZE, + USB_MAX_PACKET_SIZE, usb_to_update, update_to_usb) /* The receiver can be in one of the states below. */ enum rx_state { - rx_idle, /* Nothing happened yet. */ - rx_inside_block, /* Assembling a block to pass to the programmer. */ - rx_outside_block, /* Waiting for the next block to start or for the - reset command. */ + rx_idle, /* Nothing happened yet. */ + rx_inside_block, /* Assembling a block to pass to the programmer. */ + rx_outside_block, /* Waiting for the next block to start or for the + reset command. */ }; enum rx_state rx_state_ = rx_idle; -static uint8_t block_buffer[sizeof(struct update_command) + - CONFIG_UPDATE_PDU_SIZE]; +static uint8_t + block_buffer[sizeof(struct update_command) + CONFIG_UPDATE_PDU_SIZE]; static uint32_t block_size; static uint32_t block_index; @@ -117,8 +107,8 @@ static int pair_challenge(struct pair_challenge *challenge) * tmp2 = device_private * = HMAC_SHA256(device_secret, "device-identity") */ - hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE, - KEY_CONTEXT, sizeof(KEY_CONTEXT) - 1); + hmac_SHA256(tmp2, tmp, CONFIG_ROLLBACK_SECRET_SIZE, KEY_CONTEXT, + sizeof(KEY_CONTEXT) - 1); /* tmp = device_public = x25519(device_private, x25519_base_point) */ X25519_public_from_private(tmp, tmp2); @@ -128,10 +118,11 @@ static int pair_challenge(struct pair_challenge *challenge) X25519(tmp, tmp2, challenge->host_public); /* tmp2 = authenticator = HMAC_SHA256(shared_secret, nonce) */ - hmac_SHA256(tmp2, tmp, sizeof(tmp), - challenge->nonce, sizeof(challenge->nonce)); + hmac_SHA256(tmp2, tmp, sizeof(tmp), challenge->nonce, + sizeof(challenge->nonce)); QUEUE_ADD_UNITS(&update_to_usb, tmp2, - member_size(struct pair_challenge_response, authenticator)); + member_size(struct pair_challenge_response, + authenticator)); return 1; } #endif @@ -198,7 +189,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) /* Looks like this is a vendor command, let's verify it. */ if (update_pdu_valid(&cmd_buffer->cmd, - count - offsetof(struct update_frame_header, cmd))) { + count - offsetof(struct update_frame_header, + cmd))) { enum update_extra_command subcommand; uint8_t response; size_t response_size = sizeof(response); @@ -267,8 +259,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) break; #ifdef CONFIG_ROLLBACK case UPDATE_EXTRA_CMD_UNLOCK_ROLLBACK: - crec_flash_set_protect(EC_FLASH_PROTECT_ROLLBACK_AT_BOOT - , 0); + crec_flash_set_protect( + EC_FLASH_PROTECT_ROLLBACK_AT_BOOT, 0); response = EC_RES_SUCCESS; break; #ifdef CONFIG_ROLLBACK_SECRET_SIZE @@ -295,8 +287,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) } /* pair_challenge takes care of answering */ - return pair_challenge((struct pair_challenge *) - (buffer + header_size)); + return pair_challenge(( + struct pair_challenge *)(buffer + header_size)); } #endif #endif /* CONFIG_ROLLBACK_SECRET_SIZE */ @@ -322,11 +314,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) #ifdef CONFIG_TOUCHPAD_HASH_FW memcpy(tp.allowed_fw_hash, touchpad_fw_full_hash, - sizeof(tp.allowed_fw_hash)); + sizeof(tp.allowed_fw_hash)); #endif #endif /* CONFIG_TOUCHPAD_VIRTUAL_OFF */ - QUEUE_ADD_UNITS(&update_to_usb, - &tp, response_size); + QUEUE_ADD_UNITS(&update_to_usb, &tp, response_size); return 1; } case UPDATE_EXTRA_CMD_TOUCHPAD_DEBUG: { @@ -338,7 +329,8 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) * with the payload data, and put the response in data. */ response = touchpad_debug(buffer + header_size, - data_count, &data, &write_count); + data_count, &data, + &write_count); /* * On error, or if there is no data to write back, just @@ -374,11 +366,10 @@ static int try_vendor_command(struct consumer const *consumer, size_t count) } response = uart_console_read_buffer( - data[0], - (char *)output, - MIN(sizeof(output), - queue_space(&update_to_usb)), - &write_count); + data[0], (char *)output, + MIN(sizeof(output), + queue_space(&update_to_usb)), + &write_count); if (response != EC_RES_SUCCESS || write_count == 0) break; @@ -406,7 +397,7 @@ static uint64_t prev_activity_timestamp; * A flag indicating that at least one valid PDU containing flash update block * has been received in the current transfer session. */ -static uint8_t data_was_transferred; +static uint8_t data_was_transferred; /* Reply with an error to remote side, reset state. */ static void send_error_reset(uint8_t resp_value) @@ -459,10 +450,10 @@ static void update_out_handler(struct consumer const *consumer, size_t count) * digest = 0, and base = 0. */ if (!fetch_transfer_start(consumer, count, &u.upfr) || - be32toh(u.upfr.block_size) != - sizeof(struct update_frame_header) || - u.upfr.cmd.block_digest != 0 || - u.upfr.cmd.block_base != 0) { + be32toh(u.upfr.block_size) != + sizeof(struct update_frame_header) || + u.upfr.cmd.block_digest != 0 || + u.upfr.cmd.block_base != 0) { /* * Something is wrong, this payload is not a valid * update start PDU. Let'w indicate this by returning @@ -474,14 +465,14 @@ static void update_out_handler(struct consumer const *consumer, size_t count) } CPRINTS("FW update: starting..."); - fw_update_command_handler(&u.upfr.cmd, count - - offsetof(struct update_frame_header, - cmd), - &resp_size); + fw_update_command_handler( + &u.upfr.cmd, + count - offsetof(struct update_frame_header, cmd), + &resp_size); if (!u.startup_resp.return_value) { - rx_state_ = rx_outside_block; /* We're in business. */ - data_was_transferred = 0; /* No data received yet. */ + rx_state_ = rx_outside_block; /* We're in business. */ + data_was_transferred = 0; /* No data received yet. */ } /* Let the host know what updater had to say. */ @@ -509,8 +500,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count) } resp_value = 0; - QUEUE_ADD_UNITS(&update_to_usb, - &resp_value, 1); + QUEUE_ADD_UNITS(&update_to_usb, &resp_value, 1); rx_state_ = rx_idle; return; } @@ -528,7 +518,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count) /* Let's allocate a large enough buffer. */ block_size = be32toh(upfr.block_size) - - offsetof(struct update_frame_header, cmd); + offsetof(struct update_frame_header, cmd); /* * Only update start PDU is allowed to have a size 0 payload. @@ -545,7 +535,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count) * to the updater. */ block_index = sizeof(upfr) - - offsetof(struct update_frame_header, cmd); + offsetof(struct update_frame_header, cmd); memcpy(block_buffer, &upfr.cmd, block_index); block_size -= block_index; rx_state_ = rx_inside_block; @@ -567,7 +557,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count) send_error_reset(UPDATE_GEN_ERROR); return; } - return; /* More to come. */ + return; /* More to come. */ } /* @@ -588,7 +578,7 @@ static void update_out_handler(struct consumer const *consumer, size_t count) struct consumer const update_consumer = { .queue = &usb_to_update, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = update_out_handler, }), }; -- cgit v1.2.1 From bb692f91543f48d02d760fd66f14d33a053eb8eb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:37 -0600 Subject: driver/usb_mux/ps8740.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0c3b9862a71eddd2a8ea03c110fd9163e5f05a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730165 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8740.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/driver/usb_mux/ps8740.c b/driver/usb_mux/ps8740.c index 618c74cd65..df9fe09051 100644 --- a/driver/usb_mux/ps8740.c +++ b/driver/usb_mux/ps8740.c @@ -14,14 +14,12 @@ int ps8740_read(const struct usb_mux *me, uint8_t reg, int *val) { - return i2c_read8(me->i2c_port, me->i2c_addr_flags, - reg, val); + return i2c_read8(me->i2c_port, me->i2c_addr_flags, reg, val); } int ps8740_write(const struct usb_mux *me, uint8_t reg, uint8_t val) { - return i2c_write8(me->i2c_port, me->i2c_addr_flags, - reg, val); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, reg, val); } static int ps8740_init(const struct usb_mux *me) @@ -42,7 +40,7 @@ static int ps8740_init(const struct usb_mux *me) if (res) return res; - res = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2); + res = ps8740_read(me, PS8740_REG_CHIP_ID2, &id2); if (res) return res; -- cgit v1.2.1 From 95b9a36ebcbb05bb341152b3e6ad63acd28b7cfd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:45 -0600 Subject: util/cros_ec_dev.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib28a3f77d852a5bd7d2ea340f7f6049bf2f50d98 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730610 Reviewed-by: Jeremy Bettis --- util/cros_ec_dev.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/util/cros_ec_dev.h b/util/cros_ec_dev.h index 41930f97dd..7bf12befda 100644 --- a/util/cros_ec_dev.h +++ b/util/cros_ec_dev.h @@ -50,9 +50,9 @@ struct cros_ec_readmem { char *buffer; }; -#define CROS_EC_DEV_IOC ':' -#define CROS_EC_DEV_IOCXCMD _IOWR(':', 0, struct cros_ec_command) -#define CROS_EC_DEV_IOCRDMEM _IOWR(':', 1, struct cros_ec_readmem) +#define CROS_EC_DEV_IOC ':' +#define CROS_EC_DEV_IOCXCMD _IOWR(':', 0, struct cros_ec_command) +#define CROS_EC_DEV_IOCRDMEM _IOWR(':', 1, struct cros_ec_readmem) /* * @version: Command version number (often 0) @@ -84,12 +84,12 @@ struct cros_ec_readmem_v2 { uint8_t buffer[EC_MEMMAP_SIZE]; }; -#define CROS_EC_DEV_IOC_V2 0xEC -#define CROS_EC_DEV_IOCXCMD_V2 _IOWR(CROS_EC_DEV_IOC_V2, 0, \ - struct cros_ec_command_v2) -#define CROS_EC_DEV_IOCRDMEM_V2 _IOWR(CROS_EC_DEV_IOC_V2, 1, \ - struct cros_ec_readmem_v2) -#define CROS_EC_DEV_IOCEVENTMASK_V2 _IO(CROS_EC_DEV_IOC_V2, 2) +#define CROS_EC_DEV_IOC_V2 0xEC +#define CROS_EC_DEV_IOCXCMD_V2 \ + _IOWR(CROS_EC_DEV_IOC_V2, 0, struct cros_ec_command_v2) +#define CROS_EC_DEV_IOCRDMEM_V2 \ + _IOWR(CROS_EC_DEV_IOC_V2, 1, struct cros_ec_readmem_v2) +#define CROS_EC_DEV_IOCEVENTMASK_V2 _IO(CROS_EC_DEV_IOC_V2, 2) #ifdef __cplusplus } -- cgit v1.2.1 From fe739110a549fd33de4e3a8f53bc652077078342 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:18 -0600 Subject: include/mag_cal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5fdec73d48a1226aed5a445b2ebf5929c1a33268 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730348 Reviewed-by: Jeremy Bettis --- include/mag_cal.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/mag_cal.h b/include/mag_cal.h index 61b24c7da9..3d256a0777 100644 --- a/include/mag_cal.h +++ b/include/mag_cal.h @@ -14,8 +14,8 @@ #include "kasa.h" #define MAG_CAL_MAX_SAMPLES 0xffff -#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND) -#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */ +#define MAG_CAL_MIN_BATCH_WINDOW_US (2 * SECOND) +#define MAG_CAL_MIN_BATCH_SIZE 50 /* samples */ struct mag_cal_t { struct kasa_fit kasa_fit; @@ -38,4 +38,4 @@ void init_mag_cal(struct mag_cal_t *moc); * @return 1 if a new calibration value is available, 0 otherwise. */ int mag_cal_update(struct mag_cal_t *moc, const intv3_t v); -#endif /* __CROS_EC_MAG_CAL_H */ +#endif /* __CROS_EC_MAG_CAL_H */ -- cgit v1.2.1 From ffca7a20260fb1a105decd13cc74556f28c733b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:40 -0600 Subject: chip/mchp/lfw/ec_lfw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0c07a61ad9406f2c1dffbc4f09d03b94dad42077 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729245 Reviewed-by: Jeremy Bettis --- chip/mchp/lfw/ec_lfw.c | 73 +++++++++++++++++++++++--------------------------- 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/chip/mchp/lfw/ec_lfw.c b/chip/mchp/lfw/ec_lfw.c index 6f34a33a8d..6fd21b6c2a 100644 --- a/chip/mchp/lfw/ec_lfw.c +++ b/chip/mchp/lfw/ec_lfw.c @@ -41,15 +41,16 @@ #define LFW_SPI_BYTE_TRANSFER_TIMEOUT_US (1 * MSEC) #define LFW_SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 -__attribute__ ((section(".intvector"))) +__attribute__((section(".intvector"))) const struct int_vector_t hdr_int_vect = { /* init sp, unused. set by MEC ROM loader */ - (void *)lfw_stack_top, /* preserve ROM log. was (void *)0x11FA00, */ - &lfw_main, /* was &lfw_main, */ /* reset vector */ - &fault_handler, /* NMI handler */ - &fault_handler, /* HardFault handler */ - &fault_handler, /* MPU fault handler */ - &fault_handler /* Bus fault handler */ + (void *)lfw_stack_top, /* preserve ROM log. was (void *)0x11FA00, */ + &lfw_main, + /* was &lfw_main, */ /* reset vector */ + &fault_handler, /* NMI handler */ + &fault_handler, /* HardFault handler */ + &fault_handler, /* MPU fault handler */ + &fault_handler /* Bus fault handler */ }; /* SPI devices - from board.c */ @@ -123,7 +124,6 @@ void timer_init(void) /* Start counting in timer 0 */ MCHP_TMR32_CTL(0) |= BIT(5); - } /* @@ -132,14 +132,11 @@ void timer_init(void) * before starting SPI read to minimize probability of * timer wrap. */ -static int spi_flash_readloc(uint8_t *buf_usr, - unsigned int offset, - unsigned int bytes) +static int spi_flash_readloc(uint8_t *buf_usr, unsigned int offset, + unsigned int bytes) { - uint8_t cmd[4] = {SPI_FLASH_READ, - (offset >> 16) & 0xFF, - (offset >> 8) & 0xFF, - offset & 0xFF}; + uint8_t cmd[4] = { SPI_FLASH_READ, (offset >> 16) & 0xFF, + (offset >> 8) & 0xFF, offset & 0xFF }; if (offset + bytes > CONFIG_FLASH_SIZE_BYTES) return EC_ERROR_INVAL; @@ -156,8 +153,8 @@ static int spi_flash_readloc(uint8_t *buf_usr, */ int spi_image_load(uint32_t offset) { - uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + - CONFIG_PROGRAM_MEMORY_BASE); + uint8_t *buf = + (uint8_t *)(CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE); uint32_t i; #ifdef CONFIG_MCHP_LFW_DEBUG uint32_t crc_calc, crc_exp; @@ -172,13 +169,11 @@ int spi_image_load(uint32_t offset) for (i = 0; i < CONFIG_RO_SIZE; i += SPI_CHUNK_SIZE) #ifdef CONFIG_MCHP_LFW_DEBUG rc = spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); - if (rc != EC_SUCCESS) { - trace2(0, LFW, 0, - "spi_flash_readloc block %d ret = %d", - i, rc); - while (MCHP_PCR_PROC_CLK_CTL) - MCHP_PCR_CHIP_OSC_ID &= 0x1FE; - } + if (rc != EC_SUCCESS) { + trace2(0, LFW, 0, "spi_flash_readloc block %d ret = %d", i, rc); + while (MCHP_PCR_PROC_CLK_CTL) + MCHP_PCR_CHIP_OSC_ID &= 0x1FE; + } #else spi_flash_readloc(&buf[i], offset + i, SPI_CHUNK_SIZE); #endif @@ -234,7 +229,7 @@ timestamp_t get_time(void) { timestamp_t ts; - ts.le.hi = 0; /* clksrc_high; */ + ts.le.hi = 0; /* clksrc_high; */ ts.le.lo = __hw_clock_source_read(); return ts; } @@ -297,11 +292,17 @@ void uart_init(void) gpio_config_module(MODULE_UART, 1); } #else -void uart_write_c(char c __attribute__((unused))) {} +void uart_write_c(char c __attribute__((unused))) +{ +} -void uart_puts(const char *str __attribute__((unused))) {} +void uart_puts(const char *str __attribute__((unused))) +{ +} -void uart_init(void) {} +void uart_init(void) +{ +} #endif /* #ifdef CONFIG_UART_CONSOLE */ void fault_handler(void) @@ -312,12 +313,11 @@ void fault_handler(void) MCHP_PCR_SYS_RST = MCHP_PCR_SYS_SOFT_RESET; while (1) ; - } void jump_to_image(uintptr_t init_addr) { - void (*resetvec)(void) = (void(*)(void))init_addr; + void (*resetvec)(void) = (void (*)(void))init_addr; resetvec(); } @@ -329,16 +329,13 @@ void jump_to_image(uintptr_t init_addr) void system_init(void) { uint32_t wdt_sts = MCHP_VBAT_STS & MCHP_VBAT_STS_ANY_RST; - uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & - MCHP_PWR_RST_STS_SYS; + uint32_t rst_sts = MCHP_PCR_PWR_RST_STS & MCHP_PWR_RST_STS_SYS; - trace12(0, LFW, 0, - "VBAT_STS = 0x%08x PCR_PWR_RST_STS = 0x%08x", + trace12(0, LFW, 0, "VBAT_STS = 0x%08x PCR_PWR_RST_STS = 0x%08x", wdt_sts, rst_sts); if (rst_sts || wdt_sts) - MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) - = EC_IMAGE_UNKNOWN; + MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX) = EC_IMAGE_UNKNOWN; } enum ec_image system_get_image_copy(void) @@ -346,7 +343,6 @@ enum ec_image system_get_image_copy(void) return MCHP_VBAT_RAM(MCHP_IMAGETYPE_IDX); } - /* * lfw_main is entered by MEC BootROM or EC_RO/RW calling it directly. * NOTE: Based on LFW from MEC1322 @@ -360,11 +356,10 @@ enum ec_image system_get_image_copy(void) */ void lfw_main(void) { - uintptr_t init_addr; /* install vector table */ - *((uintptr_t *) 0xe000ed08) = (uintptr_t) &hdr_int_vect; + *((uintptr_t *)0xe000ed08) = (uintptr_t)&hdr_int_vect; /* Use 48 MHz processor clock to power through boot */ MCHP_PCR_PROC_CLK_CTL = 1; -- cgit v1.2.1 From 72ffddb1581f95ebb7e9eaedd37bbfbd8feaeb8a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:49 -0600 Subject: zephyr/drivers/cros_displight/cros_displight.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief68a960e0ec866846587c9a88284bb684abeba0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730668 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_displight/cros_displight.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/drivers/cros_displight/cros_displight.c b/zephyr/drivers/cros_displight/cros_displight.c index e730caf409..3dcfd35480 100644 --- a/zephyr/drivers/cros_displight/cros_displight.c +++ b/zephyr/drivers/cros_displight/cros_displight.c @@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define DISPLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0) #define DISPLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0) #define DISPLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0) -#define DISPLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC/DT_INST_PROP(0, frequency)) +#define DISPLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC / DT_INST_PROP(0, frequency)) static int displight_percent; @@ -38,8 +38,8 @@ static void displight_set_duty(int percent) pulse_ns = DIV_ROUND_NEAREST(DISPLIGHT_PWM_PERIOD_NS * percent, 100); - LOG_DBG("displight PWM %s set percent (%d), pulse %d", - pwm_dev->name, percent, pulse_ns); + LOG_DBG("displight PWM %s set percent (%d), pulse %d", pwm_dev->name, + percent, pulse_ns); rv = pwm_set(pwm_dev, DISPLIGHT_PWM_CHANNEL, DISPLIGHT_PWM_PERIOD_NS, pulse_ns, DISPLIGHT_PWM_FLAGS); -- cgit v1.2.1 From e795f51beb8ae5cdae784ce77b4e701cfbae4a3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:55 -0600 Subject: core/minute-ia/cpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If594d633b27ddb8be9cfaab70f7b9b58d7ab2b21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729849 Reviewed-by: Jeremy Bettis --- core/minute-ia/cpu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/core/minute-ia/cpu.h b/core/minute-ia/cpu.h index 09eb50e4ca..9853d45f31 100644 --- a/core/minute-ia/cpu.h +++ b/core/minute-ia/cpu.h @@ -8,6 +8,5 @@ #ifndef __CROS_EC_CPU_H #define __CROS_EC_CPU_H - void cpu_init(void); -#endif /* __CROS_EC_CPU_H */ +#endif /* __CROS_EC_CPU_H */ -- cgit v1.2.1 From 7403b1ad292c36d4af3be1f466b9c7148618ded3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:38 -0600 Subject: driver/retimer/ps8802.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3663dc23cfe758e4fee2ec3b6feae739806d94a5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730057 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8802.h | 130 ++++++++++++++++++++++++------------------------ 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/driver/retimer/ps8802.h b/driver/retimer/ps8802.h index 5f4b9e4e9c..552f1995a8 100644 --- a/driver/retimer/ps8802.h +++ b/driver/retimer/ps8802.h @@ -13,70 +13,70 @@ * PS8802 uses 7-bit I2C addresses 0x08 to 0x17 (ADDR=L). * Page 0 = 0x08, Page 1 = 0x09, Page 2 = 0x0A. */ -#define PS8802_I2C_ADDR_FLAGS 0x08 +#define PS8802_I2C_ADDR_FLAGS 0x08 /* * PS8802 uses 7-bit I2C addresses 0x28 to 0x37. * Page 0 = 0x028, Page 1 = 0x29, Page 2 = 0x2A. */ -#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28 +#define PS8802_I2C_ADDR_FLAGS_CUSTOM 0x28 /* * PAGE 0 Register Definitions */ -#define PS8802_REG_PAGE0 0x00 +#define PS8802_REG_PAGE0 0x00 -#define PS8802_REG0_TX_STATUS 0x72 -#define PS8802_REG0_RX_STATUS 0x76 -#define PS8802_STATUS_NORMAL_OPERATION BIT(7) -#define PS8802_STATUS_10_GBPS BIT(5) +#define PS8802_REG0_TX_STATUS 0x72 +#define PS8802_REG0_RX_STATUS 0x76 +#define PS8802_STATUS_NORMAL_OPERATION BIT(7) +#define PS8802_STATUS_10_GBPS BIT(5) /* * PAGE 1 Register Definitions */ -#define PS8802_REG_PAGE1 0x01 - -#define PS8802_800MV_LEVEL_TUNING 0x8A -#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03 -#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06 -#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07 -#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07 - -#define PS8802_REG_DCIRX 0x4B -#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7) -#define PS8802_FORCE_DCI_MODE BIT(6) +#define PS8802_REG_PAGE1 0x01 + +#define PS8802_800MV_LEVEL_TUNING 0x8A +#define PS8802_EXTRA_SWING_LEVEL_P0_DEFAULT 0X00 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_1 0X01 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_2 0X02 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_3 0X03 +#define PS8802_EXTRA_SWING_LEVEL_P0_DOWN_4 0X04 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_1 0X05 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_2 0X06 +#define PS8802_EXTRA_SWING_LEVEL_P0_UP_3 0X07 +#define PS8802_EXTRA_SWING_LEVEL_P0_MASK 0X07 + +#define PS8802_REG_DCIRX 0x4B +#define PS8802_AUTO_DCI_MODE_DISABLE BIT(7) +#define PS8802_FORCE_DCI_MODE BIT(6) /* * PAGE 2 Register Definitions */ -#define PS8802_REG_PAGE2 0x02 - -#define PS8802_REG2_USB_SSEQ_LEVEL 0x02 -#define PS8802_REG2_USB_CEQ_LEVEL 0x04 -#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003) -#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007) -#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F) -#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F) -#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F) -#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F) -#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF) -#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF) -#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF - -#define PS8802_REG2_MODE 0x06 -#define PS8802_MODE_DP_REG_CONTROL BIT(7) -#define PS8802_MODE_DP_ENABLE BIT(6) -#define PS8802_MODE_USB_REG_CONTROL BIT(5) -#define PS8802_MODE_USB_ENABLE BIT(4) -#define PS8802_MODE_FLIP_REG_CONTROL BIT(3) -#define PS8802_MODE_FLIP_ENABLE BIT(2) -#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1) -#define PS8802_MODE_IN_HPD_ENABLE BIT(0) +#define PS8802_REG_PAGE2 0x02 + +#define PS8802_REG2_USB_SSEQ_LEVEL 0x02 +#define PS8802_REG2_USB_CEQ_LEVEL 0x04 +#define PS8802_USBEQ_LEVEL_UP_12DB (0x0000 | 0x0003) +#define PS8802_USBEQ_LEVEL_UP_13DB (0x0400 | 0x0007) +#define PS8802_USBEQ_LEVEL_UP_16DB (0x0C00 | 0x000F) +#define PS8802_USBEQ_LEVEL_UP_17DB (0x1C00 | 0x001F) +#define PS8802_USBEQ_LEVEL_UP_18DB (0x3C00 | 0x003F) +#define PS8802_USBEQ_LEVEL_UP_19DB (0x7C00 | 0x007F) +#define PS8802_USBEQ_LEVEL_UP_20DB (0xFC00 | 0x00FF) +#define PS8802_USBEQ_LEVEL_UP_23DB (0xFD00 | 0x01FF) +#define PS8802_USBEQ_LEVEL_UP_MASK 0xFDFF + +#define PS8802_REG2_MODE 0x06 +#define PS8802_MODE_DP_REG_CONTROL BIT(7) +#define PS8802_MODE_DP_ENABLE BIT(6) +#define PS8802_MODE_USB_REG_CONTROL BIT(5) +#define PS8802_MODE_USB_ENABLE BIT(4) +#define PS8802_MODE_FLIP_REG_CONTROL BIT(3) +#define PS8802_MODE_FLIP_ENABLE BIT(2) +#define PS8802_MODE_IN_HPD_REG_CONTROL BIT(1) +#define PS8802_MODE_IN_HPD_ENABLE BIT(0) /* * Support power saving mode, Bit7 Disable @@ -84,23 +84,23 @@ * FLIP pin, Bit1 Display IN_HPD pin, [Bit6 Bit4] * 00: I2C standy by mode. */ -#define PS8802_MODE_STANDBY_MODE 0xAA - -#define PS8802_REG2_DPEQ_LEVEL 0x07 -#define PS8802_DPEQ_LEVEL_UP_9DB 0x00 -#define PS8802_DPEQ_LEVEL_UP_11DB 0x01 -#define PS8802_DPEQ_LEVEL_UP_12DB 0x02 -#define PS8802_DPEQ_LEVEL_UP_14DB 0x03 -#define PS8802_DPEQ_LEVEL_UP_17DB 0x04 -#define PS8802_DPEQ_LEVEL_UP_18DB 0x05 -#define PS8802_DPEQ_LEVEL_UP_19DB 0x06 -#define PS8802_DPEQ_LEVEL_UP_20DB 0x07 -#define PS8802_DPEQ_LEVEL_UP_21DB 0x08 -#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F - -#define PS8802_P1_ADDR 0x0A -#define PS8802_ADDR_CFG 0xB0 -#define PS8802_I2C_ADDR_FLAGS_ALT 0x50 +#define PS8802_MODE_STANDBY_MODE 0xAA + +#define PS8802_REG2_DPEQ_LEVEL 0x07 +#define PS8802_DPEQ_LEVEL_UP_9DB 0x00 +#define PS8802_DPEQ_LEVEL_UP_11DB 0x01 +#define PS8802_DPEQ_LEVEL_UP_12DB 0x02 +#define PS8802_DPEQ_LEVEL_UP_14DB 0x03 +#define PS8802_DPEQ_LEVEL_UP_17DB 0x04 +#define PS8802_DPEQ_LEVEL_UP_18DB 0x05 +#define PS8802_DPEQ_LEVEL_UP_19DB 0x06 +#define PS8802_DPEQ_LEVEL_UP_20DB 0x07 +#define PS8802_DPEQ_LEVEL_UP_21DB 0x08 +#define PS8802_DPEQ_LEVEL_UP_MASK 0x0F + +#define PS8802_P1_ADDR 0x0A +#define PS8802_ADDR_CFG 0xB0 +#define PS8802_I2C_ADDR_FLAGS_ALT 0x50 extern const struct usb_mux_driver ps8802_usb_mux_driver; @@ -108,11 +108,11 @@ int ps8802_i2c_wake(const struct usb_mux *me); int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data); int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data); int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, - int data); + int data); int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset, uint8_t field_mask, uint8_t set_value); int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset, - uint16_t field_mask, uint16_t set_value); + uint16_t field_mask, uint16_t set_value); int ps8802_chg_i2c_addr(int i2c_port); #endif /* __CROS_EC_USB_RETIMER_PS8802_H */ -- cgit v1.2.1 From 1218db1ca3d0633c1df3b39fcac2baf17bd7eee7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:35 -0600 Subject: board/kuldax/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12dc564c4d1fc2df66cc9b07916b5236e900807f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728602 Reviewed-by: Jeremy Bettis --- board/kuldax/fw_config.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/board/kuldax/fw_config.h b/board/kuldax/fw_config.h index 5ddb3b02a1..ff1f3583fe 100644 --- a/board/kuldax/fw_config.h +++ b/board/kuldax/fw_config.h @@ -13,15 +13,9 @@ * * Source of truth is the project/brask/brask/config.star configuration file. */ -enum ec_cfg_audio_type { - DB_AUDIO_UNKNOWN = 0, - DB_NAU88L25B_I2S = 1 -}; +enum ec_cfg_audio_type { DB_AUDIO_UNKNOWN = 0, DB_NAU88L25B_I2S = 1 }; -enum ec_cfg_bj_power { - BJ_135W = 0, - BJ_230W = 1 -}; +enum ec_cfg_bj_power { BJ_135W = 0, BJ_230W = 1 }; union brask_cbi_fw_config { struct { -- cgit v1.2.1 From c17e38001ec83c9355c6985473cc4f09f19b1c04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:26 -0600 Subject: chip/mchp/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c814fd38902a218962e458f2bf010b6f08af972 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729292 Reviewed-by: Jeremy Bettis --- chip/mchp/gpio.c | 67 +++++++++++++++++++++++++------------------------------- 1 file changed, 30 insertions(+), 37 deletions(-) diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index 5794229b34..2bae778247 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -18,8 +18,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) struct gpio_int_mapping { int8_t girq_id; @@ -38,10 +37,9 @@ struct gpio_int_mapping { * 4 0200 - 0235 12 * 5 0240 - 0276 26 */ -static const struct gpio_int_mapping int_map[] = { - { 11, 0 }, { 10, 1 }, { 9, 2 }, - { 8, 3 }, { 12, 4 }, { 26, 5 } -}; +static const struct gpio_int_mapping int_map[] = { { 11, 0 }, { 10, 1 }, + { 9, 2 }, { 8, 3 }, + { 12, 4 }, { 26, 5 } }; BUILD_ASSERT(ARRAY_SIZE(int_map) == MCHP_GPIO_MAX_PORT); /* @@ -98,7 +96,7 @@ static void disable_bgpo(uint32_t port, uint32_t mask) * 1-bit of val or if val == 0 returns 0 */ void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { int i; uint32_t val; @@ -171,16 +169,16 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) #ifdef CONFIG_GPIO_POWER_DOWN if (flags & GPIO_POWER_DOWN) { - val = (MCHP_GPIO_CTRL_PWR_OFF - | MCHP_GPIO_INTDET_DISABLED - | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + val = (MCHP_GPIO_CTRL_PWR_OFF | + MCHP_GPIO_INTDET_DISABLED | + MCHP_GPIO_CTRL_DIS_INPUT_BIT); MCHP_GPIO_CTL(port, i) = val; continue; } #endif - val &= ~(MCHP_GPIO_CTRL_PWR_MASK - | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + val &= ~(MCHP_GPIO_CTRL_PWR_MASK | + MCHP_GPIO_CTRL_DIS_INPUT_BIT); val |= MCHP_GPIO_CTRL_PWR_VTR; /* @@ -253,9 +251,9 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask) while (mask) { i = GPIO_MASK_TO_NUM(mask); mask &= ~BIT(i); - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF - | MCHP_GPIO_INTDET_DISABLED - | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + MCHP_GPIO_CTL(port, i) = + (MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED | + MCHP_GPIO_CTRL_DIS_INPUT_BIT); } } @@ -268,9 +266,9 @@ int gpio_power_off(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(gpio_list[signal].mask); port = gpio_list[signal].port; - MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF - | MCHP_GPIO_INTDET_DISABLED - | MCHP_GPIO_CTRL_DIS_INPUT_BIT); + MCHP_GPIO_CTL(port, i) = + (MCHP_GPIO_CTRL_PWR_OFF | MCHP_GPIO_INTDET_DISABLED | + MCHP_GPIO_CTRL_DIS_INPUT_BIT); return EC_SUCCESS; } @@ -313,7 +311,6 @@ int gpio_disable_interrupt(enum gpio_signal signal) port = gpio_list[signal].port; girq_id = int_map[port].girq_id; - MCHP_INT_DISABLE(girq_id) = BIT(i); return EC_SUCCESS; @@ -369,7 +366,6 @@ void gpio_pre_init(void) int is_warm = system_is_reboot_warm(); const struct gpio_info *g = gpio_list; - for (i = 0; i < GPIO_COUNT; i++, g++) { flags = g->flags; @@ -389,7 +385,7 @@ void gpio_pre_init(void) /* Use as GPIO, not alternate function */ gpio_set_alternate_function(g->port, g->mask, - GPIO_ALT_FUNC_NONE); + GPIO_ALT_FUNC_NONE); } } @@ -405,14 +401,13 @@ void gpio_pre_init(void) * assumption for the GPIO's that have been enabled. * 2. Clear NVIC pending to prevent ISR firing on false edge. */ -#define ENABLE_GPIO_GIRQ(x) \ - do { \ - MCHP_INT_SOURCE(x) = 0xfffffffful; \ - task_clear_pending_irq(MCHP_IRQ_GIRQ ## x); \ - task_enable_irq(MCHP_IRQ_GIRQ ## x); \ +#define ENABLE_GPIO_GIRQ(x) \ + do { \ + MCHP_INT_SOURCE(x) = 0xfffffffful; \ + task_clear_pending_irq(MCHP_IRQ_GIRQ##x); \ + task_enable_irq(MCHP_IRQ_GIRQ##x); \ } while (0) - static void gpio_init(void) { ENABLE_GPIO_GIRQ(8); @@ -427,7 +422,6 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); /************************************************************************/ /* Interrupt handlers */ - /** * Handler for each GIRQ interrupt. This reads and clears the interrupt * bits for the GIRQ interrupt, then finds and calls the corresponding @@ -448,8 +442,8 @@ static void gpio_interrupt(int girq, int port) MCHP_INT_SOURCE(girq) = sts; trace12(0, GPIO, 0, "GPIO GIRQ %d result = 0x%08x", girq, sts); - trace12(0, GPIO, 0, "GPIO ParIn[%d] = 0x%08x", - port, MCHP_GPIO_PARIN(port)); + trace12(0, GPIO, 0, "GPIO ParIn[%d] = 0x%08x", port, + MCHP_GPIO_PARIN(port)); for (i = 0; (i < GPIO_IH_COUNT) && sts; ++i, ++g) { if (g->port != port) @@ -459,9 +453,8 @@ static void gpio_interrupt(int girq, int port) if (bit) { bit--; if (sts & BIT(bit)) { - trace12(0, GPIO, 0, - "Bit[%d]: handler @ 0x%08x", bit, - (uint32_t)gpio_irq_handlers[i]); + trace12(0, GPIO, 0, "Bit[%d]: handler @ 0x%08x", + bit, (uint32_t)gpio_irq_handlers[i]); gpio_irq_handlers[i](i); } sts &= ~BIT(bit); @@ -469,10 +462,10 @@ static void gpio_interrupt(int girq, int port) } } -#define GPIO_IRQ_FUNC(irqfunc, girq, port)\ - static void irqfunc(void) \ - { \ - gpio_interrupt(girq, port);\ +#define GPIO_IRQ_FUNC(irqfunc, girq, port) \ + static void irqfunc(void) \ + { \ + gpio_interrupt(girq, port); \ } GPIO_IRQ_FUNC(__girq_8_interrupt, 8, 3); -- cgit v1.2.1 From 298b39750bda4d9b26385dde8791adb94084653f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:24 -0600 Subject: board/haboki/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6bfa5bbf47f75857747478f3358638e83ebe27ca Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728443 Reviewed-by: Jeremy Bettis --- board/haboki/board.h | 38 +++++++++++++++++--------------------- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/board/haboki/board.h b/board/haboki/board.h index 58dafb945f..fcb3015729 100644 --- a/board/haboki/board.h +++ b/board/haboki/board.h @@ -23,20 +23,21 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -69,8 +70,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -81,8 +82,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -105,21 +106,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 7f7e594bb18ace5dfaa65e9b72ec903a60eb02e8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:42 -0600 Subject: driver/tcpm/fusb307.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5336842196b8d1133f2f9ab41d53310a2b05f0ab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730091 Reviewed-by: Jeremy Bettis --- driver/tcpm/fusb307.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/tcpm/fusb307.h b/driver/tcpm/fusb307.h index 3f1f12901d..61e42a08d5 100644 --- a/driver/tcpm/fusb307.h +++ b/driver/tcpm/fusb307.h @@ -12,14 +12,14 @@ #define FUSB307_I2C_ADDR_FLAGS 0x50 -#define TCPC_REG_RESET 0xA2 -#define TCPC_REG_RESET_PD_RESET BIT(1) -#define TCPC_REG_RESET_SW_RESET BIT(0) - -#define TCPC_REG_GPIO1_CFG 0xA4 -#define TCPC_REG_GPIO1_CFG_GPO1_VAL BIT(2) -#define TCPC_REG_GPIO1_CFG_GPI1_EN BIT(1) -#define TCPC_REG_GPIO1_CFG_GPO1_EN BIT(0) +#define TCPC_REG_RESET 0xA2 +#define TCPC_REG_RESET_PD_RESET BIT(1) +#define TCPC_REG_RESET_SW_RESET BIT(0) + +#define TCPC_REG_GPIO1_CFG 0xA4 +#define TCPC_REG_GPIO1_CFG_GPO1_VAL BIT(2) +#define TCPC_REG_GPIO1_CFG_GPI1_EN BIT(1) +#define TCPC_REG_GPIO1_CFG_GPO1_EN BIT(0) int fusb307_power_supply_reset(int port); -- cgit v1.2.1 From bc10f2240f5f110eefe6032e0b3e1323950de6f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:46 -0600 Subject: board/banshee/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf93e4842f6e4bf3d853825dd587be0caf6b020e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728000 Reviewed-by: Jeremy Bettis --- board/banshee/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/banshee/i2c.c b/board/banshee/i2c.c index 69220b08d6..17dc4cc400 100644 --- a/board/banshee/i2c.c +++ b/board/banshee/i2c.c @@ -8,7 +8,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From d2d93975b73a8ae09a463bafd5ed0d18ce6d8ea0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:12 -0600 Subject: common/rollback.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46345879c6be12f39c5eafc322ad625371c8d191 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729705 Reviewed-by: Jeremy Bettis --- common/rollback.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/common/rollback.c b/common/rollback.c index 984058c49a..65779fc473 100644 --- a/common/rollback.c +++ b/common/rollback.c @@ -25,7 +25,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* Number of rollback regions */ #define ROLLBACK_REGIONS 2 @@ -188,12 +188,12 @@ failed: #ifdef CONFIG_ROLLBACK_UPDATE #ifdef CONFIG_ROLLBACK_SECRET_SIZE -static int add_entropy(uint8_t *dst, const uint8_t *src, - const uint8_t *add, unsigned int add_len) +static int add_entropy(uint8_t *dst, const uint8_t *src, const uint8_t *add, + unsigned int add_len) { int ret = 0; #ifdef CONFIG_SHA256 -BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE); + BUILD_ASSERT(SHA256_DIGEST_SIZE == CONFIG_ROLLBACK_SECRET_SIZE); struct sha256_ctx ctx; uint8_t *hash; #ifdef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE @@ -240,16 +240,16 @@ failed: * * @return EC_SUCCESS on success, EC_ERROR_* on error. */ -static int rollback_update(int32_t next_min_version, - const uint8_t *entropy, unsigned int length) +static int rollback_update(int32_t next_min_version, const uint8_t *entropy, + unsigned int length) { /* * When doing flash_write operation, the data needs to be in blocks * of CONFIG_FLASH_WRITE_SIZE, pad rollback_data as required. */ uint8_t block[CONFIG_FLASH_WRITE_SIZE * - DIV_ROUND_UP(sizeof(struct rollback_data), - CONFIG_FLASH_WRITE_SIZE)]; + DIV_ROUND_UP(sizeof(struct rollback_data), + CONFIG_FLASH_WRITE_SIZE)]; struct rollback_data *data = (struct rollback_data *)block; BUILD_ASSERT(sizeof(block) >= sizeof(*data)); int erase_size, offset, region, ret; @@ -260,7 +260,7 @@ static int rollback_update(int32_t next_min_version, } /* Initialize the rest of the block. */ - memset(&block[sizeof(*data)], 0xff, sizeof(block)-sizeof(*data)); + memset(&block[sizeof(*data)], 0xff, sizeof(block) - sizeof(*data)); region = get_latest_rollback(data); @@ -364,8 +364,7 @@ static int command_rollback_update(int argc, char **argv) return rollback_update_version(min_version); } -DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update, - "min_version", +DECLARE_CONSOLE_COMMAND(rollbackupdate, command_rollback_update, "min_version", "Update rollback info"); #ifdef CONFIG_ROLLBACK_SECRET_SIZE @@ -380,8 +379,7 @@ static int command_rollback_add_entropy(int argc, char **argv) return rollback_add_entropy(argv[1], len); } -DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy, - "data", +DECLARE_CONSOLE_COMMAND(rollbackaddent, command_rollback_add_entropy, "data", "Add entropy to rollback block"); #ifdef CONFIG_RNG @@ -438,8 +436,7 @@ hc_rollback_add_entropy(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; } -DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY, - hc_rollback_add_entropy, +DECLARE_HOST_COMMAND(EC_CMD_ADD_ENTROPY, hc_rollback_add_entropy, EC_VER_MASK(0)); #endif /* CONFIG_RNG */ #endif /* CONFIG_ROLLBACK_SECRET_SIZE */ @@ -467,14 +464,13 @@ static int command_rollback_info(int argc, char **argv) if (ret) goto failed; - ccprintf("rollback %d: %08x %08x %08x", - region, data.id, data.rollback_min_version, - data.cookie); + ccprintf("rollback %d: %08x %08x %08x", region, data.id, + data.rollback_min_version, data.cookie); #ifdef CONFIG_ROLLBACK_SECRET_SIZE if (!system_is_locked()) { /* If system is unlocked, show some of the secret. */ ccprintf(" [%02x..%02x]", data.secret[0], - data.secret[CONFIG_ROLLBACK_SECRET_SIZE-1]); + data.secret[CONFIG_ROLLBACK_SECRET_SIZE - 1]); } #endif if (min_region == region) @@ -487,8 +483,7 @@ failed: clear_rollback(&data); return ret; } -DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info, - NULL, +DECLARE_SAFE_CONSOLE_COMMAND(rollbackinfo, command_rollback_info, NULL, "Print rollback info"); static enum ec_status @@ -515,6 +510,5 @@ failed: clear_rollback(&data); return ret; } -DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO, - host_command_rollback_info, +DECLARE_HOST_COMMAND(EC_CMD_ROLLBACK_INFO, host_command_rollback_info, EC_VER_MASK(0)); -- cgit v1.2.1 From ed2a406c9d024fcfe85cf66cfbaa7b335c306eda Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:21 -0600 Subject: zephyr/projects/intelrvp/mtlrvp/src/board_power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fc41b40ecf73e22871c475287240d7bf9e26302 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730776 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/mtlrvp/src/board_power.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c index 6e5253ac55..081c04eb2c 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/board_power.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/board_power.c @@ -47,8 +47,9 @@ void board_ap_power_action_g3_s5(void) /* Turn on the PP3300_PRIM rail. */ power_signal_set(PWR_EN_PP3300_A, 1); - if (!power_wait_signals_timeout(IN_PGOOD_ALL_CORE, - AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { + if (!power_wait_signals_timeout( + IN_PGOOD_ALL_CORE, + AP_PWRSEQ_DT_VALUE(wait_signal_timeout))) { ap_power_ev_send_callbacks(AP_POWER_PRE_INIT); } } -- cgit v1.2.1 From e50b220f90f6652bb5dc14f33aa1451a74eb0482 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:14 -0600 Subject: board/crota/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6eaf0cfa5ba0fd17d77de63264bcb97c449bb78d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728213 Reviewed-by: Jeremy Bettis --- board/crota/led.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/board/crota/led.c b/board/crota/led.c index 0a9c9503fe..5986f8ccfa 100644 --- a/board/crota/led.c +++ b/board/crota/led.c @@ -24,20 +24,22 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_FACTORY_TEST] = { - {EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} - }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 59420a1ef7665f69d5b337138b368b58568ab534 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:24 -0600 Subject: chip/npcx/cec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee7fc5198c23ccd6e5f074f2ef2e01ff49346780 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729387 Reviewed-by: Jeremy Bettis --- chip/npcx/cec.c | 123 ++++++++++++++++++++++++++------------------------------ 1 file changed, 58 insertions(+), 65 deletions(-) diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index eb1cfefa0f..7807d4e359 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -22,21 +22,21 @@ #define CPRINTF(...) #define CPRINTS(...) #else -#define CPRINTF(format, args...) cprintf(CC_CEC, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CEC, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CEC, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CEC, format, ##args) #endif /* Time in us to timer clock ticks */ -#define APB1_TICKS(t) ((t) * apb1_freq_div_10k / 100) +#define APB1_TICKS(t) ((t)*apb1_freq_div_10k / 100) #if DEBUG_CEC /* Timer clock ticks to us */ -#define APB1_US(ticks) (100*(ticks)/apb1_freq_div_10k) +#define APB1_US(ticks) (100 * (ticks) / apb1_freq_div_10k) #endif /* Notification from interrupt to CEC task that data has been received */ #define TASK_EVENT_RECEIVED_DATA TASK_EVENT_CUSTOM_BIT(0) -#define TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1) -#define TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2) +#define TASK_EVENT_OKAY TASK_EVENT_CUSTOM_BIT(1) +#define TASK_EVENT_FAILED TASK_EVENT_CUSTOM_BIT(2) /* CEC broadcast address. Also the highest possible CEC address */ #define CEC_BROADCAST_ADDR 15 @@ -56,7 +56,7 @@ * free-time period less than in the spec. */ #define NOMINAL_BIT_TICKS APB1_TICKS(2400) - /* Resend */ +/* Resend */ #define FREE_TIME_RS_TICKS (2 * (NOMINAL_BIT_TICKS)) /* New initiator */ #define FREE_TIME_NI_TICKS (4 * (NOMINAL_BIT_TICKS)) @@ -64,33 +64,33 @@ #define FREE_TIME_PI_TICKS (6 * (NOMINAL_BIT_TICKS)) /* Start bit timing */ -#define START_BIT_LOW_TICKS APB1_TICKS(3700) -#define START_BIT_MIN_LOW_TICKS APB1_TICKS(3500) -#define START_BIT_MAX_LOW_TICKS APB1_TICKS(3900) -#define START_BIT_HIGH_TICKS APB1_TICKS(800) -#define START_BIT_MIN_DURATION_TICKS APB1_TICKS(4300) -#define START_BIT_MAX_DURATION_TICKS APB1_TICKS(5700) +#define START_BIT_LOW_TICKS APB1_TICKS(3700) +#define START_BIT_MIN_LOW_TICKS APB1_TICKS(3500) +#define START_BIT_MAX_LOW_TICKS APB1_TICKS(3900) +#define START_BIT_HIGH_TICKS APB1_TICKS(800) +#define START_BIT_MIN_DURATION_TICKS APB1_TICKS(4300) +#define START_BIT_MAX_DURATION_TICKS APB1_TICKS(5700) /* Data bit timing */ -#define DATA_ZERO_LOW_TICKS APB1_TICKS(1500) -#define DATA_ZERO_MIN_LOW_TICKS APB1_TICKS(1300) -#define DATA_ZERO_MAX_LOW_TICKS APB1_TICKS(1700) -#define DATA_ZERO_HIGH_TICKS APB1_TICKS(900) -#define DATA_ZERO_MIN_DURATION_TICKS APB1_TICKS(2050) -#define DATA_ZERO_MAX_DURATION_TICKS APB1_TICKS(2750) - -#define DATA_ONE_LOW_TICKS APB1_TICKS(600) -#define DATA_ONE_MIN_LOW_TICKS APB1_TICKS(400) -#define DATA_ONE_MAX_LOW_TICKS APB1_TICKS(800) -#define DATA_ONE_HIGH_TICKS APB1_TICKS(1800) -#define DATA_ONE_MIN_DURATION_TICKS APB1_TICKS(2050) -#define DATA_ONE_MAX_DURATION_TICKS APB1_TICKS(2750) +#define DATA_ZERO_LOW_TICKS APB1_TICKS(1500) +#define DATA_ZERO_MIN_LOW_TICKS APB1_TICKS(1300) +#define DATA_ZERO_MAX_LOW_TICKS APB1_TICKS(1700) +#define DATA_ZERO_HIGH_TICKS APB1_TICKS(900) +#define DATA_ZERO_MIN_DURATION_TICKS APB1_TICKS(2050) +#define DATA_ZERO_MAX_DURATION_TICKS APB1_TICKS(2750) + +#define DATA_ONE_LOW_TICKS APB1_TICKS(600) +#define DATA_ONE_MIN_LOW_TICKS APB1_TICKS(400) +#define DATA_ONE_MAX_LOW_TICKS APB1_TICKS(800) +#define DATA_ONE_HIGH_TICKS APB1_TICKS(1800) +#define DATA_ONE_MIN_DURATION_TICKS APB1_TICKS(2050) +#define DATA_ONE_MAX_DURATION_TICKS APB1_TICKS(2750) /* Time from low that it should be safe to sample an ACK */ #define NOMINAL_SAMPLE_TIME_TICKS APB1_TICKS(1050) -#define DATA_TIME(type, data) ((data) ? (DATA_ONE_ ## type ## _TICKS) : \ - (DATA_ZERO_ ## type ## _TICKS)) +#define DATA_TIME(type, data) \ + ((data) ? (DATA_ONE_##type##_TICKS) : (DATA_ZERO_##type##_TICKS)) #define DATA_HIGH(data) DATA_TIME(HIGH, data) #define DATA_LOW(data) DATA_TIME(LOW, data) @@ -119,26 +119,26 @@ * sure that if we get a timeout, something is wrong. */ #define CAP_START_LOW_TICKS (START_BIT_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS) -#define CAP_START_HIGH_TICKS (START_BIT_MAX_DURATION_TICKS - \ - START_BIT_MIN_LOW_TICKS + \ - VALID_TOLERANCE_TICKS) +#define CAP_START_HIGH_TICKS \ + (START_BIT_MAX_DURATION_TICKS - START_BIT_MIN_LOW_TICKS + \ + VALID_TOLERANCE_TICKS) #define CAP_DATA_LOW_TICKS (DATA_ZERO_MAX_LOW_TICKS + VALID_TOLERANCE_TICKS) -#define CAP_DATA_HIGH_TICKS (DATA_ONE_MAX_DURATION_TICKS - \ - DATA_ONE_MIN_LOW_TICKS + \ - VALID_TOLERANCE_TICKS) +#define CAP_DATA_HIGH_TICKS \ + (DATA_ONE_MAX_DURATION_TICKS - DATA_ONE_MIN_LOW_TICKS + \ + VALID_TOLERANCE_TICKS) -#define VALID_TIME(type, bit, t) \ - ((t) >= ((bit ## _MIN_ ## type ## _TICKS) - (VALID_TOLERANCE_TICKS)) \ - && (t) <= (bit ##_MAX_ ## type ## _TICKS) + (VALID_TOLERANCE_TICKS)) +#define VALID_TIME(type, bit, t) \ + ((t) >= ((bit##_MIN_##type##_TICKS) - (VALID_TOLERANCE_TICKS)) && \ + (t) <= (bit##_MAX_##type##_TICKS) + (VALID_TOLERANCE_TICKS)) #define VALID_LOW(bit, t) VALID_TIME(LOW, bit, t) -#define VALID_HIGH(bit, low_time, high_time) \ - (((low_time) + (high_time) <= \ - bit ## _MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \ - ((low_time) + (high_time) >= \ - bit ## _MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS)) -#define VALID_DATA_HIGH(data, low_time, high_time) ((data) ? \ - VALID_HIGH(DATA_ONE, low_time, high_time) : \ - VALID_HIGH(DATA_ZERO, low_time, high_time)) +#define VALID_HIGH(bit, low_time, high_time) \ + (((low_time) + (high_time) <= \ + bit##_MAX_DURATION_TICKS + VALID_TOLERANCE_TICKS) && \ + ((low_time) + (high_time) >= \ + bit##_MIN_DURATION_TICKS - VALID_TOLERANCE_TICKS)) +#define VALID_DATA_HIGH(data, low_time, high_time) \ + ((data) ? VALID_HIGH(DATA_ONE, low_time, high_time) : \ + VALID_HIGH(DATA_ZERO, low_time, high_time)) /* * CEC state machine states. Each state typically takes action on entry and @@ -179,10 +179,7 @@ enum cec_state { }; /* Edge to trigger capture timer interrupt on */ -enum cap_edge { - CAP_EDGE_FALLING, - CAP_EDGE_RISING -}; +enum cap_edge { CAP_EDGE_FALLING, CAP_EDGE_RISING }; /* Receive buffer and states */ struct cec_rx { @@ -408,13 +405,13 @@ void enter_state(enum cec_state new_state) break; case CEC_STATE_INITIATOR_EOM_LOW: gpio = 0; - timeout = DATA_LOW(cec_transfer_is_eom(&cec_tx.transfer, - cec_tx.len)); + timeout = DATA_LOW( + cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len)); break; case CEC_STATE_INITIATOR_EOM_HIGH: gpio = 1; - timeout = DATA_HIGH(cec_transfer_is_eom(&cec_tx.transfer, - cec_tx.len)); + timeout = DATA_HIGH( + cec_transfer_is_eom(&cec_tx.transfer, cec_tx.len)); break; case CEC_STATE_INITIATOR_ACK_LOW: gpio = 0; @@ -423,8 +420,8 @@ void enter_state(enum cec_state new_state) case CEC_STATE_INITIATOR_ACK_HIGH: gpio = 1; /* Aim for the middle of the safe sample time */ - timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS)/2 - - DATA_ONE_LOW_TICKS; + timeout = (DATA_ONE_LOW_TICKS + DATA_ZERO_LOW_TICKS) / 2 - + DATA_ONE_LOW_TICKS; break; case CEC_STATE_INITIATOR_ACK_VERIFY: cec_tx.ack = !gpio_get_level(CEC_GPIO_OUT); @@ -523,7 +520,8 @@ void enter_state(enum cec_state new_state) cap_edge = CAP_EDGE_FALLING; timeout = CAP_DATA_HIGH_TICKS; break; - /* No default case, since all states must be handled explicitly */ + /* No default case, since all states must be handled explicitly + */ } if (gpio >= 0) @@ -594,8 +592,7 @@ static void cec_event_timeout(void) cec_tx.len = 0; cec_tx.resends = 0; enter_state(CEC_STATE_IDLE); - task_set_event(TASK_ID_CEC, - TASK_EVENT_OKAY); + task_set_event(TASK_ID_CEC, TASK_EVENT_OKAY); } } else { if (cec_tx.resends < CEC_MAX_RESENDS) { @@ -607,8 +604,7 @@ static void cec_event_timeout(void) cec_tx.len = 0; cec_tx.resends = 0; enter_state(CEC_STATE_IDLE); - task_set_event(TASK_ID_CEC, - TASK_EVENT_FAILED); + task_set_event(TASK_ID_CEC, TASK_EVENT_FAILED); } } break; @@ -645,7 +641,6 @@ static void cec_event_timeout(void) case CEC_STATE_FOLLOWER_DATA_HIGH: enter_state(CEC_STATE_IDLE); break; - } } @@ -672,7 +667,7 @@ static void cec_event_cap(void) break; case CEC_STATE_FOLLOWER_START_LOW: /* Rising edge of start bit, validate low time */ - t = tmr_cap_get(); + t = tmr_cap_get(); if (VALID_LOW(START_BIT, t)) { cec_rx.low_ticks = t; enter_state(CEC_STATE_FOLLOWER_START_HIGH); @@ -942,7 +937,6 @@ static enum ec_status hc_cec_set(struct host_cmd_handler_args *args) } DECLARE_HOST_COMMAND(EC_CMD_CEC_SET, hc_cec_set, EC_VER_MASK(0)); - static enum ec_status hc_cec_get(struct host_cmd_handler_args *args) { struct ec_response_cec_get *response = args->response; @@ -990,13 +984,12 @@ static int cec_get_next_msg(uint8_t *out) } DECLARE_EVENT_SOURCE(EC_MKBP_EVENT_CEC_MESSAGE, cec_get_next_msg); - static void cec_init(void) { int mdl = NPCX_MFT_MODULE_1; /* APB1 is the clock we base the timers on */ - apb1_freq_div_10k = clock_get_apb1_freq()/10000; + apb1_freq_div_10k = clock_get_apb1_freq() / 10000; /* Ensure Multi-Function timer is powered up. */ CLEAR_BIT(NPCX_PWDWN_CTL(mdl), NPCX_PWDWN_CTL1_MFT1_PD); -- cgit v1.2.1 From 7fdbd34f0949c9dcff1fd72a29ff989a8850b0ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:59 -0600 Subject: board/coachz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17b3fb522507863b87fd96ce9eaf34216fbd03a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728168 Reviewed-by: Jeremy Bettis --- board/coachz/led.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/coachz/led.c b/board/coachz/led.c index 9dd8729a04..1562e69a15 100644 --- a/board/coachz/led.c +++ b/board/coachz/led.c @@ -35,15 +35,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_W_C0, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -84,16 +84,15 @@ static void board_led_set_battery(void) period = (1 + 1) * LED_ONE_SEC; battery_ticks = battery_ticks % period; if (battery_ticks < 1 * LED_ONE_SEC) { - if (charge_get_percent() < 10) - { - /* Blink amber light (1 sec on, 1 sec off) */ + if (charge_get_percent() < 10) { + /* Blink amber light (1 sec on, 1 sec + * off) */ color = LED_AMBER; - } - else - { - /* Blink white light (1 sec on, 1 sec off) */ + } else { + /* Blink white light (1 sec on, 1 sec + * off) */ color = LED_BLUE; - } + } } else { color = LED_OFF; } -- cgit v1.2.1 From f3b96b66ca23552e63ee86be208591ead0bba36c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:32 -0600 Subject: driver/ppc/aoz1380.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I593c313c629416431ce19dd9295bfd91b4dc2698 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730025 Reviewed-by: Jeremy Bettis --- driver/ppc/aoz1380.h | 1 - 1 file changed, 1 deletion(-) diff --git a/driver/ppc/aoz1380.h b/driver/ppc/aoz1380.h index 94f2b804b7..dfd8bb7703 100644 --- a/driver/ppc/aoz1380.h +++ b/driver/ppc/aoz1380.h @@ -33,7 +33,6 @@ extern const struct ppc_drv aoz1380_drv; int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp); - /** * Interrupt Handler for the AOZ1380. * -- cgit v1.2.1 From c6ebcfe4f64cebbc36cb45d9b7bd0878f169acc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:29 -0600 Subject: board/dalboz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If495762c7834e8ec2e4b788b9f0f9cdfc9dad7ad Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728218 Reviewed-by: Jeremy Bettis --- board/dalboz/led.c | 59 ++++++++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 26 deletions(-) diff --git a/board/dalboz/led.c b/board/dalboz/led.c index 53e94e84d6..8d2cfe4044 100644 --- a/board/dalboz/led.c +++ b/board/dalboz/led.c @@ -8,44 +8,51 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_RED, 2 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_RED, 2 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_RED, + 2 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_RED, + 2 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_pwr_state_table) == PWR_LED_NUM_STATES); -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From aeda14dfdf7508f63be00dfcc97e16315e94af20 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:33 -0600 Subject: driver/ioexpander/it8801.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib0dbe9d2e9ccc1bd4ef6f40cb5625acf8c73d456 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729986 Reviewed-by: Jeremy Bettis --- driver/ioexpander/it8801.h | 130 +++++++++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 64 deletions(-) diff --git a/driver/ioexpander/it8801.h b/driver/ioexpander/it8801.h index 05a17acf78..a1bb327e65 100644 --- a/driver/ioexpander/it8801.h +++ b/driver/ioexpander/it8801.h @@ -14,79 +14,81 @@ #define IT8801_I2C_ADDR2 0x39 /* Keyboard Matrix Scan control (KBS) */ -#define IT8801_REG_KSOMCR 0x40 -#define IT8801_REG_MASK_KSOSDIC BIT(7) -#define IT8801_REG_MASK_KSE BIT(6) -#define IT8801_REG_MASK_AKSOSC BIT(5) -#define IT8801_REG_KSIDR 0x41 -#define IT8801_REG_KSIEER 0x42 -#define IT8801_REG_KSIIER 0x43 -#define IT8801_REG_SMBCR 0xfa -#define IT8801_REG_MASK_ARE BIT(4) -#define IT8801_REG_GIECR 0xfb -#define IT8801_REG_MASK_GKSIIE BIT(3) -#define IT8801_REG_GPIO10 0x12 -#define IT8801_REG_GPIO00_KSO19 0x0a -#define IT8801_REG_GPIO01_KSO18 0x0b -#define IT8801_REG_GPIO22_KSO21 0x1c -#define IT8801_REG_GPIO23_KSO20 0x1d -#define IT8801_REG_MASK_GPIOAFS_PULLUP BIT(7) -#define IT8801_REG_MASK_GPIOAFS_FUNC2 BIT(6) -#define IT8801_REG_MASK_GPIODIR BIT(5) -#define IT8801_REG_MASK_GPIOPUE BIT(0) -#define IT8801_REG_GPIO23SOV BIT(3) -#define IT8801_REG_MASK_SELKSO2 0x02 -#define IT8801_REG_GISR 0xF9 -#define IT8801_REG_MASK_GISR_GKSIIS BIT(6) -#define IT8801_REG_MASK_GISR_GGPIOG2IS BIT(2) -#define IT8801_REG_MASK_GISR_GGPIOG1IS BIT(1) -#define IT8801_REG_MASK_GISR_GGPIOG0IS BIT(0) -#define IT8801_REG_MASK_GISR_GGPIOGXIS (IT8801_REG_MASK_GISR_GGPIOG2IS | \ - IT8801_REG_MASK_GISR_GGPIOG1IS | IT8801_REG_MASK_GISR_GGPIOG0IS) -#define IT8801_REG_LBVIDR 0xFE -#define IT8801_REG_HBVIDR 0xFF -#define IT8801_KSO_COUNT 18 +#define IT8801_REG_KSOMCR 0x40 +#define IT8801_REG_MASK_KSOSDIC BIT(7) +#define IT8801_REG_MASK_KSE BIT(6) +#define IT8801_REG_MASK_AKSOSC BIT(5) +#define IT8801_REG_KSIDR 0x41 +#define IT8801_REG_KSIEER 0x42 +#define IT8801_REG_KSIIER 0x43 +#define IT8801_REG_SMBCR 0xfa +#define IT8801_REG_MASK_ARE BIT(4) +#define IT8801_REG_GIECR 0xfb +#define IT8801_REG_MASK_GKSIIE BIT(3) +#define IT8801_REG_GPIO10 0x12 +#define IT8801_REG_GPIO00_KSO19 0x0a +#define IT8801_REG_GPIO01_KSO18 0x0b +#define IT8801_REG_GPIO22_KSO21 0x1c +#define IT8801_REG_GPIO23_KSO20 0x1d +#define IT8801_REG_MASK_GPIOAFS_PULLUP BIT(7) +#define IT8801_REG_MASK_GPIOAFS_FUNC2 BIT(6) +#define IT8801_REG_MASK_GPIODIR BIT(5) +#define IT8801_REG_MASK_GPIOPUE BIT(0) +#define IT8801_REG_GPIO23SOV BIT(3) +#define IT8801_REG_MASK_SELKSO2 0x02 +#define IT8801_REG_GISR 0xF9 +#define IT8801_REG_MASK_GISR_GKSIIS BIT(6) +#define IT8801_REG_MASK_GISR_GGPIOG2IS BIT(2) +#define IT8801_REG_MASK_GISR_GGPIOG1IS BIT(1) +#define IT8801_REG_MASK_GISR_GGPIOG0IS BIT(0) +#define IT8801_REG_MASK_GISR_GGPIOGXIS \ + (IT8801_REG_MASK_GISR_GGPIOG2IS | IT8801_REG_MASK_GISR_GGPIOG1IS | \ + IT8801_REG_MASK_GISR_GGPIOG0IS) +#define IT8801_REG_LBVIDR 0xFE +#define IT8801_REG_HBVIDR 0xFF +#define IT8801_KSO_COUNT 18 /* General Purpose I/O Port (GPIO) */ -#define IT8801_SUPPORT_GPIO_FLAGS (GPIO_OPEN_DRAIN | GPIO_INPUT | \ - GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | GPIO_INT_ANY) +#define IT8801_SUPPORT_GPIO_FLAGS \ + (GPIO_OPEN_DRAIN | GPIO_INPUT | GPIO_OUTPUT | GPIO_LOW | GPIO_HIGH | \ + GPIO_INT_ANY) -#define IT8801_REG_MASK_GPIOAFS_FUNC1 (0x00 << 7) +#define IT8801_REG_MASK_GPIOAFS_FUNC1 (0x00 << 7) /* IT8801 only supports GPIO 0/1/2 */ -#define IT8801_VALID_GPIO_G0_MASK 0xD9 -#define IT8801_VALID_GPIO_G1_MASK 0x3F -#define IT8801_VALID_GPIO_G2_MASK 0x0F +#define IT8801_VALID_GPIO_G0_MASK 0xD9 +#define IT8801_VALID_GPIO_G1_MASK 0x3F +#define IT8801_VALID_GPIO_G2_MASK 0x0F extern __override_proto const uint8_t it8801_kso_mapping[]; extern const struct ioexpander_drv it8801_ioexpander_drv; /* GPIO Register map */ /* Input pin status register */ -#define IT8801_REG_GPIO_IPSR(port) (0x00 + (port)) +#define IT8801_REG_GPIO_IPSR(port) (0x00 + (port)) /* Set output value register */ -#define IT8801_REG_GPIO_SOVR(port) (0x05 + (port)) +#define IT8801_REG_GPIO_SOVR(port) (0x05 + (port)) /* Control register */ -#define IT8801_REG_GPIO_CR(port, mask) \ - (0x0A + (port) * 8 + GPIO_MASK_TO_NUM(mask)) +#define IT8801_REG_GPIO_CR(port, mask) \ + (0x0A + (port)*8 + GPIO_MASK_TO_NUM(mask)) /* Interrupt status register */ -#define IT8801_REG_GPIO_ISR(port) (0x32 + (port)) +#define IT8801_REG_GPIO_ISR(port) (0x32 + (port)) /* Interrupt enable register */ -#define IT8801_REG_GPIO_IER(port) (0x37 + (port)) +#define IT8801_REG_GPIO_IER(port) (0x37 + (port)) /* Control register values */ -#define IT8801_GPIOAFS_SHIFT 6 /* bit 6~7 */ +#define IT8801_GPIOAFS_SHIFT 6 /* bit 6~7 */ -#define IT8801_GPIODIR BIT(5) /* direction, output=1 */ +#define IT8801_GPIODIR BIT(5) /* direction, output=1 */ /* input pin */ -#define IT8801_GPIOIOT_INT_RISING BIT(3) -#define IT8801_GPIOIOT_INT_FALLING BIT(4) +#define IT8801_GPIOIOT_INT_RISING BIT(3) +#define IT8801_GPIOIOT_INT_FALLING BIT(4) -#define IT8801_GPIODIR BIT(5) -#define IT8801_GPIOIOT BIT(4) -#define IT8801_GPIOPOL BIT(2) /* polarity */ -#define IT8801_GPIOPDE BIT(1) /* pull-down enable */ -#define IT8801_GPIOPUE BIT(0) /* pull-up enable */ +#define IT8801_GPIODIR BIT(5) +#define IT8801_GPIOIOT BIT(4) +#define IT8801_GPIOPOL BIT(2) /* polarity */ +#define IT8801_GPIOPDE BIT(1) /* pull-down enable */ +#define IT8801_GPIOPUE BIT(0) /* pull-up enable */ /* ISR for IT8801's SMB_INT# */ void io_expander_it8801_interrupt(enum gpio_signal signal); @@ -109,18 +111,18 @@ uint16_t it8801_pwm_get_raw_duty(enum pwm_channel ch); void it8801_pwm_set_duty(enum pwm_channel ch, int percent); int it8801_pwm_get_duty(enum pwm_channel ch); -#define IT8801_REG_PWMODDSR 0x5F -#define IT8801_REG_PWMMCR(n) (0x60 + ((n) - 1) * 8) -#define IT8801_REG_PWMDCR(n) (0x64 + ((n) - 1) * 8) -#define IT8801_REG_PWMPRSL(n) (0x66 + ((n) - 1) * 8) -#define IT8801_REG_PWMPRSM(n) (0x67 + ((n) - 1) * 8) +#define IT8801_REG_PWMODDSR 0x5F +#define IT8801_REG_PWMMCR(n) (0x60 + ((n)-1) * 8) +#define IT8801_REG_PWMDCR(n) (0x64 + ((n)-1) * 8) +#define IT8801_REG_PWMPRSL(n) (0x66 + ((n)-1) * 8) +#define IT8801_REG_PWMPRSM(n) (0x67 + ((n)-1) * 8) -#define IT8801_PWMMCR_MCR_MASK 0x3 -#define IT8801_PWMMCR_MCR_OFF 0 -#define IT8801_PWMMCR_MCR_BLINKING 1 -#define IT8801_PWMMCR_MCR_BREATHING 2 -#define IT8801_PWMMCR_MCR_ON 3 +#define IT8801_PWMMCR_MCR_MASK 0x3 +#define IT8801_PWMMCR_MCR_OFF 0 +#define IT8801_PWMMCR_MCR_BLINKING 1 +#define IT8801_PWMMCR_MCR_BREATHING 2 +#define IT8801_PWMMCR_MCR_ON 3 -#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */ +#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */ #endif /* __CROS_EC_KBEXPANDER_IT8801_H */ -- cgit v1.2.1 From 493aee25dd07ae0df8a6ab13cd51197f82c82325 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:02 -0600 Subject: fuzz/span.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4838e507f8714cab66d3433306a18fd835cc93b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730195 Reviewed-by: Jeremy Bettis --- fuzz/span.h | 92 ++++++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 60 insertions(+), 32 deletions(-) diff --git a/fuzz/span.h b/fuzz/span.h index 531df832a3..f4ed0ff7ed 100644 --- a/fuzz/span.h +++ b/fuzz/span.h @@ -9,48 +9,76 @@ #include -namespace fuzz { +namespace fuzz +{ -template -class span { - public: - typedef T value_type; +template class span { + public: + typedef T value_type; - constexpr span() : span(nullptr, nullptr) {} - constexpr span(T* begin, size_t size) : begin_(begin), end_(begin + size) {} - constexpr span(T* begin, T* end) : begin_(begin), end_(end) {} + constexpr span() + : span(nullptr, nullptr) + { + } + constexpr span(T *begin, size_t size) + : begin_(begin) + , end_(begin + size) + { + } + constexpr span(T *begin, T *end) + : begin_(begin) + , end_(end) + { + } - template - constexpr span(Container& container) - : begin_(container.begin()), end_(container.end()){}; + template + constexpr span(Container &container) + : begin_(container.begin()) + , end_(container.end()){}; - constexpr T* begin() const { return begin_; } - constexpr T* end() const { return end_; } + constexpr T *begin() const + { + return begin_; + } + constexpr T *end() const + { + return end_; + } - constexpr T* data() const { return begin_; } + constexpr T *data() const + { + return begin_; + } - constexpr bool empty() const { return begin_ == end_; } - constexpr size_t size() const { return end_ - begin_; } + constexpr bool empty() const + { + return begin_ == end_; + } + constexpr size_t size() const + { + return end_ - begin_; + } - private: - T* begin_; - T* end_; + private: + T *begin_; + T *end_; }; template -size_t CopyWithPadding(Source source, - Destination destination, - typename Destination::value_type fill_value) { - if (source.size() >= destination.size()) { - std::copy(source.begin(), source.begin() + destination.size(), - destination.begin()); - return destination.size(); - } - std::copy(source.begin(), source.end(), destination.begin()); - std::fill(destination.begin() + source.size(), destination.end(), fill_value); - return source.size(); +size_t CopyWithPadding(Source source, Destination destination, + typename Destination::value_type fill_value) +{ + if (source.size() >= destination.size()) { + std::copy(source.begin(), source.begin() + destination.size(), + destination.begin()); + return destination.size(); + } + std::copy(source.begin(), source.end(), destination.begin()); + std::fill(destination.begin() + source.size(), destination.end(), + fill_value); + return source.size(); } -} // namespace fuzz +} // namespace fuzz -#endif // __FUZZ_SPAN_H +#endif // __FUZZ_SPAN_H -- cgit v1.2.1 From 1b4fe5aef35a4af4b5785896d4fd55313aa18192 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:21 -0600 Subject: board/servo_v4p1/usb_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If93b6a98555e53af3146a03ce1099d9bc0dbb836 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728936 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_sm.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c index 94b5e0c08d..1c94749c47 100644 --- a/board/servo_v4p1/usb_sm.c +++ b/board/servo_v4p1/usb_sm.c @@ -11,8 +11,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -22,8 +22,8 @@ struct internal_ctx { usb_state_ptr last_entered; uint32_t running : 1; - uint32_t enter : 1; - uint32_t exit : 1; + uint32_t enter : 1; + uint32_t exit : 1; }; BUILD_ASSERT(sizeof(struct internal_ctx) == member_size(struct sm_ctx, internal)); @@ -64,9 +64,9 @@ static usb_state_ptr shared_parent_state(usb_state_ptr a, usb_state_ptr b) * functions. */ static void call_entry_functions(const int port, - struct internal_ctx *const internal, - const usb_state_ptr stop, - const usb_state_ptr current) + struct internal_ctx *const internal, + const usb_state_ptr stop, + const usb_state_ptr current) { if (current == stop) return; @@ -91,7 +91,7 @@ static void call_entry_functions(const int port, * during an exit function. */ static void call_exit_functions(const int port, const usb_state_ptr stop, - const usb_state_ptr current) + const usb_state_ptr current) { if (current == stop) return; @@ -105,7 +105,7 @@ static void call_exit_functions(const int port, const usb_state_ptr stop, void set_state(const int port, struct sm_ctx *const ctx, const usb_state_ptr new_state) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; usb_state_ptr last_state; usb_state_ptr shared_parent; @@ -115,8 +115,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * intended state to transition into. */ if (internal->exit) { - CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", - port, new_state, ctx->current); + CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", port, + new_state, ctx->current); return; } @@ -167,8 +167,8 @@ void set_state(const int port, struct sm_ctx *const ctx, * functions. */ static void call_run_functions(const int port, - const struct internal_ctx *const internal, - const usb_state_ptr current) + const struct internal_ctx *const internal, + const usb_state_ptr current) { if (!current) return; @@ -185,7 +185,7 @@ static void call_run_functions(const int port, void run_state(const int port, struct sm_ctx *const ctx) { - struct internal_ctx * const internal = (void *) ctx->internal; + struct internal_ctx *const internal = (void *)ctx->internal; internal->running = true; call_run_functions(port, internal, ctx->current); -- cgit v1.2.1 From e44b52169f3bb143b72aad7412e9b6cf371b5e24 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:04 -0600 Subject: board/mushu/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id91d2547723b5e4cb0f745d7e0e24d295cf9eb13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728713 Reviewed-by: Jeremy Bettis --- board/mushu/board.h | 54 +++++++++++++++++++++++------------------------------ 1 file changed, 23 insertions(+), 31 deletions(-) diff --git a/board/mushu/board.h b/board/mushu/board.h index 5f80b4a2e6..5a3193c388 100644 --- a/board/mushu/board.h +++ b/board/mushu/board.h @@ -13,10 +13,10 @@ /* Reduce flash usage */ #define CONFIG_USB_PD_DEBUG_LEVEL 2 -#undef CONFIG_CMD_ACCELSPOOF -#undef CONFIG_CMD_CHARGER_DUMP -#undef CONFIG_CMD_PPC_DUMP -#undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CMD_ACCELSPOOF +#undef CONFIG_CMD_CHARGER_DUMP +#undef CONFIG_CMD_PPC_DUMP +#undef CONFIG_CONSOLE_CMDHELP #define CONFIG_POWER_BUTTON #define CONFIG_KEYBOARD_PROTOCOL_8042 @@ -26,14 +26,12 @@ #define CONFIG_HOST_INTERFACE_ESPI #undef CONFIG_CMD_MFALLOW - #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096 /* Keyboard features */ #define CONFIG_PWM_KBLIGHT - /* Sensors */ /* BMI160 Base accel/gyro */ #define CONFIG_ACCELGYRO_BMI160 @@ -53,7 +51,7 @@ #define CONFIG_ALS_TCS3400 #define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) -#define I2C_PORT_ALS I2C_PORT_SENSOR +#define I2C_PORT_ALS I2C_PORT_SENSOR #define CONFIG_TEMP_SENSOR /* AMD SMBUS Temp sensors */ #define CONFIG_TEMP_SENSOR_AMD_R19ME4070 @@ -64,7 +62,7 @@ #define I2C_PORT_THERMAL I2C_PORT_SENSOR /* GPU features */ -#define I2C_PORT_GPU NPCX_I2C_PORT4_1 +#define I2C_PORT_GPU NPCX_I2C_PORT4_1 /* USB Type C and USB PD defines */ #undef CONFIG_USB_PD_TCPMV1 @@ -139,16 +137,16 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_PG_EC_RSMRST_ODL GPIO_PG_EC_RSMRST_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_A_RAILS +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A #ifndef __ASSEMBLER__ @@ -160,8 +158,8 @@ extern enum gpio_signal gpio_en_pp5000_a; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ ADC_CH_COUNT }; @@ -174,12 +172,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_FAN, - PWM_CH_FAN2, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_FAN, PWM_CH_FAN2, PWM_CH_COUNT }; enum fan_channel { FAN_CH_0 = 0, @@ -212,15 +205,14 @@ enum battery_type { BATTERY_TYPE_COUNT, }; - #undef PD_OPERATING_POWER_MW -#define PD_OPERATING_POWER_MW 15000 +#define PD_OPERATING_POWER_MW 15000 #undef PD_MAX_POWER_MW -#define PD_MAX_POWER_MW 100000 +#define PD_MAX_POWER_MW 100000 #undef PD_MAX_CURRENT_MA -#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_CURRENT_MA 5000 #undef PD_MAX_VOLTAGE_MV -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_VOLTAGE_MV 20000 #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From e7ff16a4066fe38880a28ec75fce22884a67258b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:31 -0600 Subject: board/drawcia/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8afbe92e64b7d16586dda803072eaf2c50772c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728253 Reviewed-by: Jeremy Bettis --- board/drawcia/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/drawcia/cbi_ssfc.c b/board/drawcia/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/drawcia/cbi_ssfc.c +++ b/board/drawcia/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 57178bfe617ce936d6a6e6c790be286149075597 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:40 -0600 Subject: include/driver/accel_bma2x2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I21a3e2cfbdf2a7b5614610c9c6a820f2469786d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730244 Reviewed-by: Jeremy Bettis --- include/driver/accel_bma2x2.h | 227 +++++++++++++++++++++--------------------- 1 file changed, 113 insertions(+), 114 deletions(-) diff --git a/include/driver/accel_bma2x2.h b/include/driver/accel_bma2x2.h index 3a46c7c050..606d0f9b7a 100644 --- a/include/driver/accel_bma2x2.h +++ b/include/driver/accel_bma2x2.h @@ -12,144 +12,143 @@ /*** Chip-specific registers ***/ /* REGISTER ADDRESS DEFINITIONS */ -#define BMA2x2_EEP_OFFSET 0x16 -#define BMA2x2_IMAGE_BASE 0x38 -#define BMA2x2_IMAGE_LEN 22 -#define BMA2x2_CHIP_ID_ADDR 0x00 -#define BMA255_CHIP_ID_MAJOR 0xfa +#define BMA2x2_EEP_OFFSET 0x16 +#define BMA2x2_IMAGE_BASE 0x38 +#define BMA2x2_IMAGE_LEN 22 +#define BMA2x2_CHIP_ID_ADDR 0x00 +#define BMA255_CHIP_ID_MAJOR 0xfa /* DATA ADDRESS DEFINITIONS */ -#define BMA2x2_X_AXIS_LSB_ADDR 0x02 -#define BMA2x2_X_AXIS_MSB_ADDR 0x03 -#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 -#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 -#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 -#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 -#define BMA2x2_TEMP_ADDR 0x08 +#define BMA2x2_X_AXIS_LSB_ADDR 0x02 +#define BMA2x2_X_AXIS_MSB_ADDR 0x03 +#define BMA2x2_Y_AXIS_LSB_ADDR 0x04 +#define BMA2x2_Y_AXIS_MSB_ADDR 0x05 +#define BMA2x2_Z_AXIS_LSB_ADDR 0x06 +#define BMA2x2_Z_AXIS_MSB_ADDR 0x07 +#define BMA2x2_TEMP_ADDR 0x08 -#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 +#define BMA2x2_AXIS_LSB_NEW_DATA 0x01 /* STATUS ADDRESS DEFINITIONS */ -#define BMA2x2_STAT1_ADDR 0x09 -#define BMA2x2_STAT2_ADDR 0x0A -#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B -#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C -#define BMA2x2_STAT_FIFO_ADDR 0x0E -#define BMA2x2_RANGE_SELECT_ADDR 0x0F -#define BMA2x2_RANGE_SELECT_MSK 0x0F -#define BMA2x2_RANGE_2G 3 -#define BMA2x2_RANGE_4G 5 -#define BMA2x2_RANGE_8G 8 -#define BMA2x2_RANGE_16G 12 - -#define BMA2x2_RANGE_TO_REG(_range) \ +#define BMA2x2_STAT1_ADDR 0x09 +#define BMA2x2_STAT2_ADDR 0x0A +#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B +#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C +#define BMA2x2_STAT_FIFO_ADDR 0x0E +#define BMA2x2_RANGE_SELECT_ADDR 0x0F +#define BMA2x2_RANGE_SELECT_MSK 0x0F +#define BMA2x2_RANGE_2G 3 +#define BMA2x2_RANGE_4G 5 +#define BMA2x2_RANGE_8G 8 +#define BMA2x2_RANGE_16G 12 + +#define BMA2x2_RANGE_TO_REG(_range) \ ((_range) < 8 ? BMA2x2_RANGE_2G + ((_range) / 4) * 2 : \ BMA2x2_RANGE_8G + ((_range) / 16) * 4) -#define BMA2x2_REG_TO_RANGE(_reg) \ - ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg) - BMA2x2_RANGE_2G : \ - 8 + ((_reg) - BMA2x2_RANGE_8G) * 2) - -#define BMA2x2_BW_SELECT_ADDR 0x10 -#define BMA2x2_BW_MSK 0x1F -#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ -#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ -#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ -#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ -#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ -#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ -#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ -#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ +#define BMA2x2_REG_TO_RANGE(_reg) \ + ((_reg) < BMA2x2_RANGE_8G ? 2 + (_reg)-BMA2x2_RANGE_2G : \ + 8 + ((_reg)-BMA2x2_RANGE_8G) * 2) + +#define BMA2x2_BW_SELECT_ADDR 0x10 +#define BMA2x2_BW_MSK 0x1F +#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.8125HZ */ +#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.625HZ */ +#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */ +#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */ +#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */ +#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */ +#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */ +#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */ /* Do not use BW lower than 7813, because __fls cannot be call for 0 */ -#define BMA2x2_BW_TO_REG(_bw) \ - ((_bw) < 125000 ? \ - BMA2x2_BW_7_81HZ + __fls(((_bw) * 10) / 78125) : \ - BMA2x2_BW_125HZ + __fls((_bw) / 125000)) - -#define BMA2x2_REG_TO_BW(_reg) \ - ((_reg) < BMA2x2_BW_125HZ ? \ - (78125 << ((_reg) - BMA2x2_BW_7_81HZ)) / 10 : \ - 125000 << ((_reg) - BMA2x2_BW_125HZ)) - -#define BMA2x2_MODE_CTRL_ADDR 0x11 -#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 -#define BMA2x2_DATA_CTRL_ADDR 0x13 -#define BMA2x2_DATA_HIGH_BW 0x80 -#define BMA2x2_DATA_SHADOW_DIS 0x40 -#define BMA2x2_RST_ADDR 0x14 -#define BMA2x2_CMD_SOFT_RESET 0xb6 +#define BMA2x2_BW_TO_REG(_bw) \ + ((_bw) < 125000 ? BMA2x2_BW_7_81HZ + __fls(((_bw)*10) / 78125) : \ + BMA2x2_BW_125HZ + __fls((_bw) / 125000)) + +#define BMA2x2_REG_TO_BW(_reg) \ + ((_reg) < BMA2x2_BW_125HZ ? \ + (78125 << ((_reg)-BMA2x2_BW_7_81HZ)) / 10 : \ + 125000 << ((_reg)-BMA2x2_BW_125HZ)) + +#define BMA2x2_MODE_CTRL_ADDR 0x11 +#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12 +#define BMA2x2_DATA_CTRL_ADDR 0x13 +#define BMA2x2_DATA_HIGH_BW 0x80 +#define BMA2x2_DATA_SHADOW_DIS 0x40 +#define BMA2x2_RST_ADDR 0x14 +#define BMA2x2_CMD_SOFT_RESET 0xb6 /* INTERRUPT ADDRESS DEFINITIONS */ -#define BMA2x2_INTR_ENABLE1_ADDR 0x16 -#define BMA2x2_INTR_ENABLE2_ADDR 0x17 -#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 -#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 -#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A -#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B -#define BMA2x2_INTR_SOURCE_ADDR 0x1E -#define BMA2x2_INTR_SET_ADDR 0x20 -#define BMA2x2_INTR_CTRL_ADDR 0x21 -#define BMA2x2_INTR_CTRL_RST_INT 0x80 +#define BMA2x2_INTR_ENABLE1_ADDR 0x16 +#define BMA2x2_INTR_ENABLE2_ADDR 0x17 +#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18 +#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19 +#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A +#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B +#define BMA2x2_INTR_SOURCE_ADDR 0x1E +#define BMA2x2_INTR_SET_ADDR 0x20 +#define BMA2x2_INTR_CTRL_ADDR 0x21 +#define BMA2x2_INTR_CTRL_RST_INT 0x80 /* FEATURE ADDRESS DEFINITIONS */ -#define BMA2x2_LOW_DURN_ADDR 0x22 -#define BMA2x2_LOW_THRES_ADDR 0x23 -#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 -#define BMA2x2_HIGH_DURN_ADDR 0x25 -#define BMA2x2_HIGH_THRES_ADDR 0x26 -#define BMA2x2_SLOPE_DURN_ADDR 0x27 -#define BMA2x2_SLOPE_THRES_ADDR 0x28 -#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 -#define BMA2x2_TAP_PARAM_ADDR 0x2A -#define BMA2x2_TAP_THRES_ADDR 0x2B -#define BMA2x2_ORIENT_PARAM_ADDR 0x2C -#define BMA2x2_THETA_BLOCK_ADDR 0x2D -#define BMA2x2_THETA_FLAT_ADDR 0x2E -#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F -#define BMA2x2_SELFTEST_ADDR 0x32 -#define BMA2x2_EEPROM_CTRL_ADDR 0x33 -#define BMA2x2_EEPROM_REMAIN_OFF 4 -#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 -#define BMA2x2_EEPROM_LOAD 0x08 -#define BMA2x2_EEPROM_RDY 0x04 -#define BMA2x2_EEPROM_PROG 0x02 -#define BMA2x2_EEPROM_PROG_EN 0x01 -#define BMA2x2_SERIAL_CTRL_ADDR 0x34 +#define BMA2x2_LOW_DURN_ADDR 0x22 +#define BMA2x2_LOW_THRES_ADDR 0x23 +#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24 +#define BMA2x2_HIGH_DURN_ADDR 0x25 +#define BMA2x2_HIGH_THRES_ADDR 0x26 +#define BMA2x2_SLOPE_DURN_ADDR 0x27 +#define BMA2x2_SLOPE_THRES_ADDR 0x28 +#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29 +#define BMA2x2_TAP_PARAM_ADDR 0x2A +#define BMA2x2_TAP_THRES_ADDR 0x2B +#define BMA2x2_ORIENT_PARAM_ADDR 0x2C +#define BMA2x2_THETA_BLOCK_ADDR 0x2D +#define BMA2x2_THETA_FLAT_ADDR 0x2E +#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F +#define BMA2x2_SELFTEST_ADDR 0x32 +#define BMA2x2_EEPROM_CTRL_ADDR 0x33 +#define BMA2x2_EEPROM_REMAIN_OFF 4 +#define BMA2x2_EEPROM_REMAIN_MSK 0xF0 +#define BMA2x2_EEPROM_LOAD 0x08 +#define BMA2x2_EEPROM_RDY 0x04 +#define BMA2x2_EEPROM_PROG 0x02 +#define BMA2x2_EEPROM_PROG_EN 0x01 +#define BMA2x2_SERIAL_CTRL_ADDR 0x34 /* OFFSET ADDRESS DEFINITIONS */ -#define BMA2x2_OFFSET_CTRL_ADDR 0x36 -#define BMA2x2_OFFSET_RESET 0x80 -#define BMA2x2_OFFSET_TRIGGER_OFF 5 -#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) -#define BMA2x2_OFFSET_CAL_READY 0x10 -#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 -#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 -#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 - -#define BMA2x2_OFC_SETTING_ADDR 0x37 -#define BMA2x2_OFC_TARGET_AXIS_OFF 1 -#define BMA2x2_OFC_TARGET_AXIS_LEN 2 +#define BMA2x2_OFFSET_CTRL_ADDR 0x36 +#define BMA2x2_OFFSET_RESET 0x80 +#define BMA2x2_OFFSET_TRIGGER_OFF 5 +#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF) +#define BMA2x2_OFFSET_CAL_READY 0x10 +#define BMA2x2_OFFSET_CAL_SLOW_X 0x04 +#define BMA2x2_OFFSET_CAL_SLOW_Y 0x02 +#define BMA2x2_OFFSET_CAL_SLOW_Z 0x01 + +#define BMA2x2_OFC_SETTING_ADDR 0x37 +#define BMA2x2_OFC_TARGET_AXIS_OFF 1 +#define BMA2x2_OFC_TARGET_AXIS_LEN 2 #define BMA2x2_OFC_TARGET_AXIS(_axis) \ (BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF) -#define BMA2x2_OFC_TARGET_0G 0 -#define BMA2x2_OFC_TARGET_PLUS_1G 1 -#define BMA2x2_OFC_TARGET_MINUS_1G 2 +#define BMA2x2_OFC_TARGET_0G 0 +#define BMA2x2_OFC_TARGET_PLUS_1G 1 +#define BMA2x2_OFC_TARGET_MINUS_1G 2 -#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 -#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 -#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A +#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38 +#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39 +#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A /* GP ADDRESS DEFINITIONS */ -#define BMA2x2_GP0_ADDR 0x3B -#define BMA2x2_GP1_ADDR 0x3C +#define BMA2x2_GP0_ADDR 0x3B +#define BMA2x2_GP1_ADDR 0x3C /* FIFO ADDRESS DEFINITIONS */ -#define BMA2x2_FIFO_MODE_ADDR 0x3E -#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F -#define BMA2x2_FIFO_WML_TRIG 0x30 +#define BMA2x2_FIFO_MODE_ADDR 0x3E +#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F +#define BMA2x2_FIFO_WML_TRIG 0x30 /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define BMA2x2_RESOLUTION 12 +#define BMA2x2_RESOLUTION 12 #endif /* __CROS_EC_ACCEL_BMA2x2_H */ -- cgit v1.2.1 From e0ee86371faea71282e8b81f0435e4e1bf8352b4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:42 -0600 Subject: zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc5fd9788443640170afdf558d35f9816d7adb85 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730950 Reviewed-by: Jeremy Bettis --- .../subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h index 81f5fbd477..ed28419ac5 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_non_dsx_common_pwrseq_sm_handler.h @@ -15,7 +15,7 @@ #include #include -#define DT_DRV_COMPAT intel_ap_pwrseq +#define DT_DRV_COMPAT intel_ap_pwrseq /* The wait time is ~150 msec, allow for safety margin. */ #define IN_PCH_SLP_SUS_WAIT_TIME_MS 250 @@ -25,7 +25,7 @@ void init_chipset_pwr_seq_state(void); enum power_states_ndsx chipset_pwr_seq_get_state(void); void request_start_from_g3(void); enum power_states_ndsx pwr_sm_get_state(void); -const char * const pwr_sm_get_state_name(enum power_states_ndsx state); +const char *const pwr_sm_get_state_name(enum power_states_ndsx state); void apshutdown(void); void ap_pwrseq_handle_chipset_reset(void); void set_start_from_g3_delay_seconds(uint32_t d_time); -- cgit v1.2.1 From 1c173ed60029301a1abdd472035b61e20131d2a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:52 -0600 Subject: chip/max32660/wdt_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I100b1a825b8faaecfd9a160573f6def2a0a90759 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729238 Reviewed-by: Jeremy Bettis --- chip/max32660/wdt_chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/max32660/wdt_chip.c b/chip/max32660/wdt_chip.c index 1c99c798fc..6d25e2b7ea 100644 --- a/chip/max32660/wdt_chip.c +++ b/chip/max32660/wdt_chip.c @@ -20,7 +20,7 @@ #define CPUTS(outstr) cputs(CC_COMMAND, outstr) #define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) -/* For a System clock of 96MHz, +/* For a System clock of 96MHz, * Time in seconds = 96000000 / 2 * 2^power * Example for MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 * Time in seconds = 96000000 / 2 * 2^29 -- cgit v1.2.1 From e43f4be95b93bbedd80ea5a0a0262e5702c139b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:40 -0600 Subject: zephyr/shim/src/chipset_api.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9e7a60d2b40087a64271db4170d394015cd9e4cd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730866 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/chipset_api.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/src/chipset_api.c b/zephyr/shim/src/chipset_api.c index 3bfa420980..ac073a0d91 100644 --- a/zephyr/shim/src/chipset_api.c +++ b/zephyr/shim/src/chipset_api.c @@ -38,7 +38,9 @@ void chipset_reset(enum chipset_shutdown_reason reason) /* TODO: b/214509787 * To be added later when this functionality is implemented in ap_pwrseq. */ -void chipset_throttle_cpu(int throttle) { } +void chipset_throttle_cpu(int throttle) +{ +} void init_reset_log(void) { -- cgit v1.2.1 From fee01bbba78181092052bb58cf5262e6d06639dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:08 -0600 Subject: board/brask/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ief2dfacc17605aa4b51b5bd136623ab3c46618fa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728095 Reviewed-by: Jeremy Bettis --- board/brask/sensors.c | 44 ++++++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/board/brask/sensors.c b/board/brask/sensors.c index 2803dd1025..2f69e81502 100644 --- a/board/brask/sensors.c +++ b/board/brask/sensors.c @@ -58,30 +58,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CPU] = { - .name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CPU - }, - [TEMP_SENSOR_2_CPU_VR] = { - .name = "CPU VR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_CPU_VR - }, - [TEMP_SENSOR_3_WIFI] = { - .name = "WIFI", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_WIFI - }, - [TEMP_SENSOR_4_DIMM] = { - .name = "DIMM", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_DIMM - }, + [TEMP_SENSOR_1_CPU] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_CPU }, + [TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_CPU_VR }, + [TEMP_SENSOR_3_WIFI] = { .name = "WIFI", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_WIFI }, + [TEMP_SENSOR_4_DIMM] = { .name = "DIMM", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_DIMM }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -95,8 +87,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From 1b6d4dada697a467b8ac4c401c95c6200dd6d5ef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:27 -0600 Subject: core/host/disabled.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4027981884a1a9c16f4b173b170b190e13022334 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729838 Reviewed-by: Jeremy Bettis --- core/host/disabled.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/core/host/disabled.c b/core/host/disabled.c index 759c215ebd..466f5629f9 100644 --- a/core/host/disabled.c +++ b/core/host/disabled.c @@ -5,6 +5,9 @@ /* Disabled functions */ -#define DISABLED(proto) proto { } +#define DISABLED(proto) \ + proto \ + { \ + } DISABLED(void clock_init(void)); -- cgit v1.2.1 From 41b11a37a0557979fe6983bd3e8dc64ef0cedf66 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:05 -0600 Subject: include/driver/accelgyro_bmi_common_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c1570c0468ebde3e29c9ddc0352b5cf3b5480d5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730269 Reviewed-by: Jeremy Bettis --- include/driver/accelgyro_bmi_common_public.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/driver/accelgyro_bmi_common_public.h b/include/driver/accelgyro_bmi_common_public.h index 52814c71bf..c31168e75c 100644 --- a/include/driver/accelgyro_bmi_common_public.h +++ b/include/driver/accelgyro_bmi_common_public.h @@ -10,14 +10,14 @@ /* Min and Max sampling frequency in mHz */ #define BMI_ACCEL_MIN_FREQ 12500 #define BMI_ACCEL_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(1600000, 100000) -#define BMI_GYRO_MIN_FREQ 25000 +#define BMI_GYRO_MIN_FREQ 25000 #define BMI_GYRO_MAX_FREQ MOTION_MAX_SENSOR_FREQUENCY(3200000, 100000) struct bmi_drv_data_t { struct accelgyro_saved_data_t saved_data[3]; - uint8_t flags; - uint8_t enabled_activities; - uint8_t disabled_activities; + uint8_t flags; + uint8_t enabled_activities; + uint8_t disabled_activities; #ifdef CONFIG_MAG_BMI_BMM150 struct bmm150_private_data compass; #endif @@ -26,7 +26,6 @@ struct bmi_drv_data_t { enum motionsensor_orientation orientation; enum motionsensor_orientation last_orientation; #endif - }; #endif /* __CROS_EC_DRIVER_ACCELGYRO_BMI_COMMON_PUBLIC_H */ -- cgit v1.2.1 From 9633138491ebd633f9d2a96334644cc2fe7aeb58 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:36 -0600 Subject: board/makomo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b503d9954b9f9091732b289fd006f17609f7bf4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728645 Reviewed-by: Jeremy Bettis --- board/makomo/led.c | 53 +++++++++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/board/makomo/led.c b/board/makomo/led.c index 140c31babe..c2fc156082 100644 --- a/board/makomo/led.c +++ b/board/makomo/led.c @@ -18,33 +18,38 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor -led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); __override void led_set_color_battery(enum ec_led_colors color) -- cgit v1.2.1 From 4006ab6004daf645f5112c63307090f96abe08de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:09 -0600 Subject: common/curve25519-generic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iedb88bee3cbd9839650cc53c59588a505d999634 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729602 Reviewed-by: Jeremy Bettis --- common/curve25519-generic.c | 945 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 944 insertions(+), 1 deletion(-) mode change 120000 => 100644 common/curve25519-generic.c diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c deleted file mode 120000 index 3218a877a2..0000000000 --- a/common/curve25519-generic.c +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/common/curve25519-generic.c \ No newline at end of file diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c new file mode 100644 index 0000000000..6b384e3365 --- /dev/null +++ b/common/curve25519-generic.c @@ -0,0 +1,944 @@ +/* Copyright 2015, Google Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION + * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN + * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ + +/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP + * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as + * public domain but this file has the ISC license just to keep licencing + * simple. + * + * The field functions are shared by Ed25519 and X25519 where possible. */ + +#include "curve25519.h" +#include "util.h" + +/* + * fe means field element. Here the field is \Z/(2^255-19). An element t, + * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77 + * t[3]+2^102 t[4]+...+2^230 t[9]. Bounds on each t[i] vary depending on + * context. + */ +typedef int32_t fe[10]; + +static const int64_t kBottom25Bits = INT64_C(0x1ffffff); +static const int64_t kBottom26Bits = INT64_C(0x3ffffff); +static const int64_t kTop39Bits = INT64_C(0xfffffffffe000000); +static const int64_t kTop38Bits = INT64_C(0xfffffffffc000000); + +static uint64_t load_3(const uint8_t *in) +{ + uint64_t result; + result = (uint64_t)in[0]; + result |= ((uint64_t)in[1]) << 8; + result |= ((uint64_t)in[2]) << 16; + return result; +} + +static uint64_t load_4(const uint8_t *in) +{ + uint64_t result; + result = (uint64_t)in[0]; + result |= ((uint64_t)in[1]) << 8; + result |= ((uint64_t)in[2]) << 16; + result |= ((uint64_t)in[3]) << 24; + return result; +} + +static void fe_frombytes(fe h, const uint8_t *s) +{ + /* Ignores top bit of h. */ + int64_t h0 = load_4(s); + int64_t h1 = load_3(s + 4) << 6; + int64_t h2 = load_3(s + 7) << 5; + int64_t h3 = load_3(s + 10) << 3; + int64_t h4 = load_3(s + 13) << 2; + int64_t h5 = load_4(s + 16); + int64_t h6 = load_3(s + 20) << 7; + int64_t h7 = load_3(s + 23) << 5; + int64_t h8 = load_3(s + 26) << 4; + int64_t h9 = (load_3(s + 29) & 8388607) << 2; + int64_t carry0; + int64_t carry1; + int64_t carry2; + int64_t carry3; + int64_t carry4; + int64_t carry5; + int64_t carry6; + int64_t carry7; + int64_t carry8; + int64_t carry9; + + carry9 = h9 + BIT(24); + h0 += (carry9 >> 25) * 19; + h9 -= carry9 & kTop39Bits; + carry1 = h1 + BIT(24); + h2 += carry1 >> 25; + h1 -= carry1 & kTop39Bits; + carry3 = h3 + BIT(24); + h4 += carry3 >> 25; + h3 -= carry3 & kTop39Bits; + carry5 = h5 + BIT(24); + h6 += carry5 >> 25; + h5 -= carry5 & kTop39Bits; + carry7 = h7 + BIT(24); + h8 += carry7 >> 25; + h7 -= carry7 & kTop39Bits; + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + carry2 = h2 + BIT(25); + h3 += carry2 >> 26; + h2 -= carry2 & kTop38Bits; + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + carry6 = h6 + BIT(25); + h7 += carry6 >> 26; + h6 -= carry6 & kTop38Bits; + carry8 = h8 + BIT(25); + h9 += carry8 >> 26; + h8 -= carry8 & kTop38Bits; + + h[0] = h0; + h[1] = h1; + h[2] = h2; + h[3] = h3; + h[4] = h4; + h[5] = h5; + h[6] = h6; + h[7] = h7; + h[8] = h8; + h[9] = h9; +} + +/* Preconditions: + * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. + * + * Write p=2^255-19; q=floor(h/p). + * Basic claim: q = floor(2^(-255)(h + 19 2^(-25)h9 + 2^(-1))). + * + * Proof: + * Have |h|<=p so |q|<=1 so |19^2 2^(-255) q|<1/4. + * Also have |h-2^230 h9|<2^231 so |19 2^(-255)(h-2^230 h9)|<1/4. + * + * Write y=2^(-1)-19^2 2^(-255)q-19 2^(-255)(h-2^230 h9). + * Then 0> 25; + q = (h0 + q) >> 26; + q = (h1 + q) >> 25; + q = (h2 + q) >> 26; + q = (h3 + q) >> 25; + q = (h4 + q) >> 26; + q = (h5 + q) >> 25; + q = (h6 + q) >> 26; + q = (h7 + q) >> 25; + q = (h8 + q) >> 26; + q = (h9 + q) >> 25; + + /* Goal: Output h-(2^255-19)q, which is between 0 and 2^255-20. */ + h0 += 19 * q; + /* Goal: Output h-2^255 q, which is between 0 and 2^255-20. */ + + h1 += h0 >> 26; + h0 &= kBottom26Bits; + h2 += h1 >> 25; + h1 &= kBottom25Bits; + h3 += h2 >> 26; + h2 &= kBottom26Bits; + h4 += h3 >> 25; + h3 &= kBottom25Bits; + h5 += h4 >> 26; + h4 &= kBottom26Bits; + h6 += h5 >> 25; + h5 &= kBottom25Bits; + h7 += h6 >> 26; + h6 &= kBottom26Bits; + h8 += h7 >> 25; + h7 &= kBottom25Bits; + h9 += h8 >> 26; + h8 &= kBottom26Bits; + h9 &= kBottom25Bits; + /* h10 = carry9 */ + + /* Goal: Output h0+...+2^255 h10-2^255 q, which is between 0 and + * 2^255-20. Have h0+...+2^230 h9 between 0 and 2^255-1; evidently 2^255 + * h10-2^255 q = 0. Goal: Output h0+...+2^230 h9. */ + + s[0] = h0 >> 0; + s[1] = h0 >> 8; + s[2] = h0 >> 16; + s[3] = (h0 >> 24) | ((uint32_t)(h1) << 2); + s[4] = h1 >> 6; + s[5] = h1 >> 14; + s[6] = (h1 >> 22) | ((uint32_t)(h2) << 3); + s[7] = h2 >> 5; + s[8] = h2 >> 13; + s[9] = (h2 >> 21) | ((uint32_t)(h3) << 5); + s[10] = h3 >> 3; + s[11] = h3 >> 11; + s[12] = (h3 >> 19) | ((uint32_t)(h4) << 6); + s[13] = h4 >> 2; + s[14] = h4 >> 10; + s[15] = h4 >> 18; + s[16] = h5 >> 0; + s[17] = h5 >> 8; + s[18] = h5 >> 16; + s[19] = (h5 >> 24) | ((uint32_t)(h6) << 1); + s[20] = h6 >> 7; + s[21] = h6 >> 15; + s[22] = (h6 >> 23) | ((uint32_t)(h7) << 3); + s[23] = h7 >> 5; + s[24] = h7 >> 13; + s[25] = (h7 >> 21) | ((uint32_t)(h8) << 4); + s[26] = h8 >> 4; + s[27] = h8 >> 12; + s[28] = (h8 >> 20) | ((uint32_t)(h9) << 6); + s[29] = h9 >> 2; + s[30] = h9 >> 10; + s[31] = h9 >> 18; +} + +/* h = f */ +static void fe_copy(fe h, const fe f) +{ + memmove(h, f, sizeof(int32_t) * 10); +} + +/* h = 0 */ +static void fe_0(fe h) +{ + memset(h, 0, sizeof(int32_t) * 10); +} + +/* h = 1 */ +static void fe_1(fe h) +{ + memset(h, 0, sizeof(int32_t) * 10); + h[0] = 1; +} + +/* h = f + g + * Can overlap h with f or g. + * + * Preconditions: + * |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. + * |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. + * + * Postconditions: + * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */ +static void fe_add(fe h, const fe f, const fe g) +{ + unsigned i; + for (i = 0; i < 10; i++) { + h[i] = f[i] + g[i]; + } +} + +/* h = f - g + * Can overlap h with f or g. + * + * Preconditions: + * |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. + * |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. + * + * Postconditions: + * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */ +static void fe_sub(fe h, const fe f, const fe g) +{ + unsigned i; + for (i = 0; i < 10; i++) { + h[i] = f[i] - g[i]; + } +} + +/* h = f * g + * Can overlap h with f or g. + * + * Preconditions: + * |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. + * |g| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. + * + * Postconditions: + * |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc. + * + * Notes on implementation strategy: + * + * Using schoolbook multiplication. + * Karatsuba would save a little in some cost models. + * + * Most multiplications by 2 and 19 are 32-bit precomputations; + * cheaper than 64-bit postcomputations. + * + * There is one remaining multiplication by 19 in the carry chain; + * one *19 precomputation can be merged into this, + * but the resulting data flow is considerably less clean. + * + * There are 12 carries below. + * 10 of them are 2-way parallelizable and vectorizable. + * Can get away with 11 carries, but then data flow is much deeper. + * + * With tighter constraints on inputs can squeeze carries into int32. */ +static void fe_mul(fe h, const fe f, const fe g) +{ + int32_t f0 = f[0]; + int32_t f1 = f[1]; + int32_t f2 = f[2]; + int32_t f3 = f[3]; + int32_t f4 = f[4]; + int32_t f5 = f[5]; + int32_t f6 = f[6]; + int32_t f7 = f[7]; + int32_t f8 = f[8]; + int32_t f9 = f[9]; + int32_t g0 = g[0]; + int32_t g1 = g[1]; + int32_t g2 = g[2]; + int32_t g3 = g[3]; + int32_t g4 = g[4]; + int32_t g5 = g[5]; + int32_t g6 = g[6]; + int32_t g7 = g[7]; + int32_t g8 = g[8]; + int32_t g9 = g[9]; + int32_t g1_19 = 19 * g1; /* 1.959375*2^29 */ + int32_t g2_19 = 19 * g2; /* 1.959375*2^30; still ok */ + int32_t g3_19 = 19 * g3; + int32_t g4_19 = 19 * g4; + int32_t g5_19 = 19 * g5; + int32_t g6_19 = 19 * g6; + int32_t g7_19 = 19 * g7; + int32_t g8_19 = 19 * g8; + int32_t g9_19 = 19 * g9; + int32_t f1_2 = 2 * f1; + int32_t f3_2 = 2 * f3; + int32_t f5_2 = 2 * f5; + int32_t f7_2 = 2 * f7; + int32_t f9_2 = 2 * f9; + int64_t f0g0 = f0 * (int64_t)g0; + int64_t f0g1 = f0 * (int64_t)g1; + int64_t f0g2 = f0 * (int64_t)g2; + int64_t f0g3 = f0 * (int64_t)g3; + int64_t f0g4 = f0 * (int64_t)g4; + int64_t f0g5 = f0 * (int64_t)g5; + int64_t f0g6 = f0 * (int64_t)g6; + int64_t f0g7 = f0 * (int64_t)g7; + int64_t f0g8 = f0 * (int64_t)g8; + int64_t f0g9 = f0 * (int64_t)g9; + int64_t f1g0 = f1 * (int64_t)g0; + int64_t f1g1_2 = f1_2 * (int64_t)g1; + int64_t f1g2 = f1 * (int64_t)g2; + int64_t f1g3_2 = f1_2 * (int64_t)g3; + int64_t f1g4 = f1 * (int64_t)g4; + int64_t f1g5_2 = f1_2 * (int64_t)g5; + int64_t f1g6 = f1 * (int64_t)g6; + int64_t f1g7_2 = f1_2 * (int64_t)g7; + int64_t f1g8 = f1 * (int64_t)g8; + int64_t f1g9_38 = f1_2 * (int64_t)g9_19; + int64_t f2g0 = f2 * (int64_t)g0; + int64_t f2g1 = f2 * (int64_t)g1; + int64_t f2g2 = f2 * (int64_t)g2; + int64_t f2g3 = f2 * (int64_t)g3; + int64_t f2g4 = f2 * (int64_t)g4; + int64_t f2g5 = f2 * (int64_t)g5; + int64_t f2g6 = f2 * (int64_t)g6; + int64_t f2g7 = f2 * (int64_t)g7; + int64_t f2g8_19 = f2 * (int64_t)g8_19; + int64_t f2g9_19 = f2 * (int64_t)g9_19; + int64_t f3g0 = f3 * (int64_t)g0; + int64_t f3g1_2 = f3_2 * (int64_t)g1; + int64_t f3g2 = f3 * (int64_t)g2; + int64_t f3g3_2 = f3_2 * (int64_t)g3; + int64_t f3g4 = f3 * (int64_t)g4; + int64_t f3g5_2 = f3_2 * (int64_t)g5; + int64_t f3g6 = f3 * (int64_t)g6; + int64_t f3g7_38 = f3_2 * (int64_t)g7_19; + int64_t f3g8_19 = f3 * (int64_t)g8_19; + int64_t f3g9_38 = f3_2 * (int64_t)g9_19; + int64_t f4g0 = f4 * (int64_t)g0; + int64_t f4g1 = f4 * (int64_t)g1; + int64_t f4g2 = f4 * (int64_t)g2; + int64_t f4g3 = f4 * (int64_t)g3; + int64_t f4g4 = f4 * (int64_t)g4; + int64_t f4g5 = f4 * (int64_t)g5; + int64_t f4g6_19 = f4 * (int64_t)g6_19; + int64_t f4g7_19 = f4 * (int64_t)g7_19; + int64_t f4g8_19 = f4 * (int64_t)g8_19; + int64_t f4g9_19 = f4 * (int64_t)g9_19; + int64_t f5g0 = f5 * (int64_t)g0; + int64_t f5g1_2 = f5_2 * (int64_t)g1; + int64_t f5g2 = f5 * (int64_t)g2; + int64_t f5g3_2 = f5_2 * (int64_t)g3; + int64_t f5g4 = f5 * (int64_t)g4; + int64_t f5g5_38 = f5_2 * (int64_t)g5_19; + int64_t f5g6_19 = f5 * (int64_t)g6_19; + int64_t f5g7_38 = f5_2 * (int64_t)g7_19; + int64_t f5g8_19 = f5 * (int64_t)g8_19; + int64_t f5g9_38 = f5_2 * (int64_t)g9_19; + int64_t f6g0 = f6 * (int64_t)g0; + int64_t f6g1 = f6 * (int64_t)g1; + int64_t f6g2 = f6 * (int64_t)g2; + int64_t f6g3 = f6 * (int64_t)g3; + int64_t f6g4_19 = f6 * (int64_t)g4_19; + int64_t f6g5_19 = f6 * (int64_t)g5_19; + int64_t f6g6_19 = f6 * (int64_t)g6_19; + int64_t f6g7_19 = f6 * (int64_t)g7_19; + int64_t f6g8_19 = f6 * (int64_t)g8_19; + int64_t f6g9_19 = f6 * (int64_t)g9_19; + int64_t f7g0 = f7 * (int64_t)g0; + int64_t f7g1_2 = f7_2 * (int64_t)g1; + int64_t f7g2 = f7 * (int64_t)g2; + int64_t f7g3_38 = f7_2 * (int64_t)g3_19; + int64_t f7g4_19 = f7 * (int64_t)g4_19; + int64_t f7g5_38 = f7_2 * (int64_t)g5_19; + int64_t f7g6_19 = f7 * (int64_t)g6_19; + int64_t f7g7_38 = f7_2 * (int64_t)g7_19; + int64_t f7g8_19 = f7 * (int64_t)g8_19; + int64_t f7g9_38 = f7_2 * (int64_t)g9_19; + int64_t f8g0 = f8 * (int64_t)g0; + int64_t f8g1 = f8 * (int64_t)g1; + int64_t f8g2_19 = f8 * (int64_t)g2_19; + int64_t f8g3_19 = f8 * (int64_t)g3_19; + int64_t f8g4_19 = f8 * (int64_t)g4_19; + int64_t f8g5_19 = f8 * (int64_t)g5_19; + int64_t f8g6_19 = f8 * (int64_t)g6_19; + int64_t f8g7_19 = f8 * (int64_t)g7_19; + int64_t f8g8_19 = f8 * (int64_t)g8_19; + int64_t f8g9_19 = f8 * (int64_t)g9_19; + int64_t f9g0 = f9 * (int64_t)g0; + int64_t f9g1_38 = f9_2 * (int64_t)g1_19; + int64_t f9g2_19 = f9 * (int64_t)g2_19; + int64_t f9g3_38 = f9_2 * (int64_t)g3_19; + int64_t f9g4_19 = f9 * (int64_t)g4_19; + int64_t f9g5_38 = f9_2 * (int64_t)g5_19; + int64_t f9g6_19 = f9 * (int64_t)g6_19; + int64_t f9g7_38 = f9_2 * (int64_t)g7_19; + int64_t f9g8_19 = f9 * (int64_t)g8_19; + int64_t f9g9_38 = f9_2 * (int64_t)g9_19; + int64_t h0 = f0g0 + f1g9_38 + f2g8_19 + f3g7_38 + f4g6_19 + f5g5_38 + + f6g4_19 + f7g3_38 + f8g2_19 + f9g1_38; + int64_t h1 = f0g1 + f1g0 + f2g9_19 + f3g8_19 + f4g7_19 + f5g6_19 + + f6g5_19 + f7g4_19 + f8g3_19 + f9g2_19; + int64_t h2 = f0g2 + f1g1_2 + f2g0 + f3g9_38 + f4g8_19 + f5g7_38 + + f6g6_19 + f7g5_38 + f8g4_19 + f9g3_38; + int64_t h3 = f0g3 + f1g2 + f2g1 + f3g0 + f4g9_19 + f5g8_19 + f6g7_19 + + f7g6_19 + f8g5_19 + f9g4_19; + int64_t h4 = f0g4 + f1g3_2 + f2g2 + f3g1_2 + f4g0 + f5g9_38 + f6g8_19 + + f7g7_38 + f8g6_19 + f9g5_38; + int64_t h5 = f0g5 + f1g4 + f2g3 + f3g2 + f4g1 + f5g0 + f6g9_19 + + f7g8_19 + f8g7_19 + f9g6_19; + int64_t h6 = f0g6 + f1g5_2 + f2g4 + f3g3_2 + f4g2 + f5g1_2 + f6g0 + + f7g9_38 + f8g8_19 + f9g7_38; + int64_t h7 = f0g7 + f1g6 + f2g5 + f3g4 + f4g3 + f5g2 + f6g1 + f7g0 + + f8g9_19 + f9g8_19; + int64_t h8 = f0g8 + f1g7_2 + f2g6 + f3g5_2 + f4g4 + f5g3_2 + f6g2 + + f7g1_2 + f8g0 + f9g9_38; + int64_t h9 = f0g9 + f1g8 + f2g7 + f3g6 + f4g5 + f5g4 + f6g3 + f7g2 + + f8g1 + f9g0; + int64_t carry0; + int64_t carry1; + int64_t carry2; + int64_t carry3; + int64_t carry4; + int64_t carry5; + int64_t carry6; + int64_t carry7; + int64_t carry8; + int64_t carry9; + + /* |h0| <= + * (1.65*1.65*2^52*(1+19+19+19+19)+1.65*1.65*2^50*(38+38+38+38+38)) i.e. + * |h0| <= 1.4*2^60; narrower ranges for h2, h4, h6, h8 |h1| <= + * (1.65*1.65*2^51*(1+1+19+19+19+19+19+19+19+19)) i.e. |h1| <= 1.7*2^59; + * narrower ranges for h3, h5, h7, h9 */ + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + /* |h0| <= 2^25 */ + /* |h4| <= 2^25 */ + /* |h1| <= 1.71*2^59 */ + /* |h5| <= 1.71*2^59 */ + + carry1 = h1 + BIT(24); + h2 += carry1 >> 25; + h1 -= carry1 & kTop39Bits; + carry5 = h5 + BIT(24); + h6 += carry5 >> 25; + h5 -= carry5 & kTop39Bits; + /* |h1| <= 2^24; from now on fits into int32 */ + /* |h5| <= 2^24; from now on fits into int32 */ + /* |h2| <= 1.41*2^60 */ + /* |h6| <= 1.41*2^60 */ + + carry2 = h2 + BIT(25); + h3 += carry2 >> 26; + h2 -= carry2 & kTop38Bits; + carry6 = h6 + BIT(25); + h7 += carry6 >> 26; + h6 -= carry6 & kTop38Bits; + /* |h2| <= 2^25; from now on fits into int32 unchanged */ + /* |h6| <= 2^25; from now on fits into int32 unchanged */ + /* |h3| <= 1.71*2^59 */ + /* |h7| <= 1.71*2^59 */ + + carry3 = h3 + BIT(24); + h4 += carry3 >> 25; + h3 -= carry3 & kTop39Bits; + carry7 = h7 + BIT(24); + h8 += carry7 >> 25; + h7 -= carry7 & kTop39Bits; + /* |h3| <= 2^24; from now on fits into int32 unchanged */ + /* |h7| <= 2^24; from now on fits into int32 unchanged */ + /* |h4| <= 1.72*2^34 */ + /* |h8| <= 1.41*2^60 */ + + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + carry8 = h8 + BIT(25); + h9 += carry8 >> 26; + h8 -= carry8 & kTop38Bits; + /* |h4| <= 2^25; from now on fits into int32 unchanged */ + /* |h8| <= 2^25; from now on fits into int32 unchanged */ + /* |h5| <= 1.01*2^24 */ + /* |h9| <= 1.71*2^59 */ + + carry9 = h9 + BIT(24); + h0 += (carry9 >> 25) * 19; + h9 -= carry9 & kTop39Bits; + /* |h9| <= 2^24; from now on fits into int32 unchanged */ + /* |h0| <= 1.1*2^39 */ + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + /* |h0| <= 2^25; from now on fits into int32 unchanged */ + /* |h1| <= 1.01*2^24 */ + + h[0] = h0; + h[1] = h1; + h[2] = h2; + h[3] = h3; + h[4] = h4; + h[5] = h5; + h[6] = h6; + h[7] = h7; + h[8] = h8; + h[9] = h9; +} + +/* h = f * f + * Can overlap h with f. + * + * Preconditions: + * |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. + * + * Postconditions: + * |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc. + * + * See fe_mul.c for discussion of implementation strategy. */ +static void fe_sq(fe h, const fe f) +{ + int32_t f0 = f[0]; + int32_t f1 = f[1]; + int32_t f2 = f[2]; + int32_t f3 = f[3]; + int32_t f4 = f[4]; + int32_t f5 = f[5]; + int32_t f6 = f[6]; + int32_t f7 = f[7]; + int32_t f8 = f[8]; + int32_t f9 = f[9]; + int32_t f0_2 = 2 * f0; + int32_t f1_2 = 2 * f1; + int32_t f2_2 = 2 * f2; + int32_t f3_2 = 2 * f3; + int32_t f4_2 = 2 * f4; + int32_t f5_2 = 2 * f5; + int32_t f6_2 = 2 * f6; + int32_t f7_2 = 2 * f7; + int32_t f5_38 = 38 * f5; /* 1.959375*2^30 */ + int32_t f6_19 = 19 * f6; /* 1.959375*2^30 */ + int32_t f7_38 = 38 * f7; /* 1.959375*2^30 */ + int32_t f8_19 = 19 * f8; /* 1.959375*2^30 */ + int32_t f9_38 = 38 * f9; /* 1.959375*2^30 */ + int64_t f0f0 = f0 * (int64_t)f0; + int64_t f0f1_2 = f0_2 * (int64_t)f1; + int64_t f0f2_2 = f0_2 * (int64_t)f2; + int64_t f0f3_2 = f0_2 * (int64_t)f3; + int64_t f0f4_2 = f0_2 * (int64_t)f4; + int64_t f0f5_2 = f0_2 * (int64_t)f5; + int64_t f0f6_2 = f0_2 * (int64_t)f6; + int64_t f0f7_2 = f0_2 * (int64_t)f7; + int64_t f0f8_2 = f0_2 * (int64_t)f8; + int64_t f0f9_2 = f0_2 * (int64_t)f9; + int64_t f1f1_2 = f1_2 * (int64_t)f1; + int64_t f1f2_2 = f1_2 * (int64_t)f2; + int64_t f1f3_4 = f1_2 * (int64_t)f3_2; + int64_t f1f4_2 = f1_2 * (int64_t)f4; + int64_t f1f5_4 = f1_2 * (int64_t)f5_2; + int64_t f1f6_2 = f1_2 * (int64_t)f6; + int64_t f1f7_4 = f1_2 * (int64_t)f7_2; + int64_t f1f8_2 = f1_2 * (int64_t)f8; + int64_t f1f9_76 = f1_2 * (int64_t)f9_38; + int64_t f2f2 = f2 * (int64_t)f2; + int64_t f2f3_2 = f2_2 * (int64_t)f3; + int64_t f2f4_2 = f2_2 * (int64_t)f4; + int64_t f2f5_2 = f2_2 * (int64_t)f5; + int64_t f2f6_2 = f2_2 * (int64_t)f6; + int64_t f2f7_2 = f2_2 * (int64_t)f7; + int64_t f2f8_38 = f2_2 * (int64_t)f8_19; + int64_t f2f9_38 = f2 * (int64_t)f9_38; + int64_t f3f3_2 = f3_2 * (int64_t)f3; + int64_t f3f4_2 = f3_2 * (int64_t)f4; + int64_t f3f5_4 = f3_2 * (int64_t)f5_2; + int64_t f3f6_2 = f3_2 * (int64_t)f6; + int64_t f3f7_76 = f3_2 * (int64_t)f7_38; + int64_t f3f8_38 = f3_2 * (int64_t)f8_19; + int64_t f3f9_76 = f3_2 * (int64_t)f9_38; + int64_t f4f4 = f4 * (int64_t)f4; + int64_t f4f5_2 = f4_2 * (int64_t)f5; + int64_t f4f6_38 = f4_2 * (int64_t)f6_19; + int64_t f4f7_38 = f4 * (int64_t)f7_38; + int64_t f4f8_38 = f4_2 * (int64_t)f8_19; + int64_t f4f9_38 = f4 * (int64_t)f9_38; + int64_t f5f5_38 = f5 * (int64_t)f5_38; + int64_t f5f6_38 = f5_2 * (int64_t)f6_19; + int64_t f5f7_76 = f5_2 * (int64_t)f7_38; + int64_t f5f8_38 = f5_2 * (int64_t)f8_19; + int64_t f5f9_76 = f5_2 * (int64_t)f9_38; + int64_t f6f6_19 = f6 * (int64_t)f6_19; + int64_t f6f7_38 = f6 * (int64_t)f7_38; + int64_t f6f8_38 = f6_2 * (int64_t)f8_19; + int64_t f6f9_38 = f6 * (int64_t)f9_38; + int64_t f7f7_38 = f7 * (int64_t)f7_38; + int64_t f7f8_38 = f7_2 * (int64_t)f8_19; + int64_t f7f9_76 = f7_2 * (int64_t)f9_38; + int64_t f8f8_19 = f8 * (int64_t)f8_19; + int64_t f8f9_38 = f8 * (int64_t)f9_38; + int64_t f9f9_38 = f9 * (int64_t)f9_38; + int64_t h0 = f0f0 + f1f9_76 + f2f8_38 + f3f7_76 + f4f6_38 + f5f5_38; + int64_t h1 = f0f1_2 + f2f9_38 + f3f8_38 + f4f7_38 + f5f6_38; + int64_t h2 = f0f2_2 + f1f1_2 + f3f9_76 + f4f8_38 + f5f7_76 + f6f6_19; + int64_t h3 = f0f3_2 + f1f2_2 + f4f9_38 + f5f8_38 + f6f7_38; + int64_t h4 = f0f4_2 + f1f3_4 + f2f2 + f5f9_76 + f6f8_38 + f7f7_38; + int64_t h5 = f0f5_2 + f1f4_2 + f2f3_2 + f6f9_38 + f7f8_38; + int64_t h6 = f0f6_2 + f1f5_4 + f2f4_2 + f3f3_2 + f7f9_76 + f8f8_19; + int64_t h7 = f0f7_2 + f1f6_2 + f2f5_2 + f3f4_2 + f8f9_38; + int64_t h8 = f0f8_2 + f1f7_4 + f2f6_2 + f3f5_4 + f4f4 + f9f9_38; + int64_t h9 = f0f9_2 + f1f8_2 + f2f7_2 + f3f6_2 + f4f5_2; + int64_t carry0; + int64_t carry1; + int64_t carry2; + int64_t carry3; + int64_t carry4; + int64_t carry5; + int64_t carry6; + int64_t carry7; + int64_t carry8; + int64_t carry9; + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + + carry1 = h1 + BIT(24); + h2 += carry1 >> 25; + h1 -= carry1 & kTop39Bits; + carry5 = h5 + BIT(24); + h6 += carry5 >> 25; + h5 -= carry5 & kTop39Bits; + + carry2 = h2 + BIT(25); + h3 += carry2 >> 26; + h2 -= carry2 & kTop38Bits; + carry6 = h6 + BIT(25); + h7 += carry6 >> 26; + h6 -= carry6 & kTop38Bits; + + carry3 = h3 + BIT(24); + h4 += carry3 >> 25; + h3 -= carry3 & kTop39Bits; + carry7 = h7 + BIT(24); + h8 += carry7 >> 25; + h7 -= carry7 & kTop39Bits; + + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + carry8 = h8 + BIT(25); + h9 += carry8 >> 26; + h8 -= carry8 & kTop38Bits; + + carry9 = h9 + BIT(24); + h0 += (carry9 >> 25) * 19; + h9 -= carry9 & kTop39Bits; + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + + h[0] = h0; + h[1] = h1; + h[2] = h2; + h[3] = h3; + h[4] = h4; + h[5] = h5; + h[6] = h6; + h[7] = h7; + h[8] = h8; + h[9] = h9; +} + +static void fe_invert(fe out, const fe z) +{ + fe t0; + fe t1; + fe t2; + fe t3; + int i; + + fe_sq(t0, z); + fe_sq(t1, t0); + for (i = 1; i < 2; ++i) { + fe_sq(t1, t1); + } + fe_mul(t1, z, t1); + fe_mul(t0, t0, t1); + fe_sq(t2, t0); + fe_mul(t1, t1, t2); + fe_sq(t2, t1); + for (i = 1; i < 5; ++i) { + fe_sq(t2, t2); + } + fe_mul(t1, t2, t1); + fe_sq(t2, t1); + for (i = 1; i < 10; ++i) { + fe_sq(t2, t2); + } + fe_mul(t2, t2, t1); + fe_sq(t3, t2); + for (i = 1; i < 20; ++i) { + fe_sq(t3, t3); + } + fe_mul(t2, t3, t2); + fe_sq(t2, t2); + for (i = 1; i < 10; ++i) { + fe_sq(t2, t2); + } + fe_mul(t1, t2, t1); + fe_sq(t2, t1); + for (i = 1; i < 50; ++i) { + fe_sq(t2, t2); + } + fe_mul(t2, t2, t1); + fe_sq(t3, t2); + for (i = 1; i < 100; ++i) { + fe_sq(t3, t3); + } + fe_mul(t2, t3, t2); + fe_sq(t2, t2); + for (i = 1; i < 50; ++i) { + fe_sq(t2, t2); + } + fe_mul(t1, t2, t1); + fe_sq(t1, t1); + for (i = 1; i < 5; ++i) { + fe_sq(t1, t1); + } + fe_mul(out, t1, t0); +} + +/* Replace (f,g) with (g,f) if b == 1; + * replace (f,g) with (f,g) if b == 0. + * + * Preconditions: b in {0,1}. */ +static void fe_cswap(fe f, fe g, unsigned int b) +{ + unsigned i; + b = 0 - b; + for (i = 0; i < 10; i++) { + int32_t x = f[i] ^ g[i]; + x &= b; + f[i] ^= x; + g[i] ^= x; + } +} + +/* h = f * 121666 + * Can overlap h with f. + * + * Preconditions: + * |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. + * + * Postconditions: + * |h| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. */ +static void fe_mul121666(fe h, fe f) +{ + int32_t f0 = f[0]; + int32_t f1 = f[1]; + int32_t f2 = f[2]; + int32_t f3 = f[3]; + int32_t f4 = f[4]; + int32_t f5 = f[5]; + int32_t f6 = f[6]; + int32_t f7 = f[7]; + int32_t f8 = f[8]; + int32_t f9 = f[9]; + int64_t h0 = f0 * (int64_t)121666; + int64_t h1 = f1 * (int64_t)121666; + int64_t h2 = f2 * (int64_t)121666; + int64_t h3 = f3 * (int64_t)121666; + int64_t h4 = f4 * (int64_t)121666; + int64_t h5 = f5 * (int64_t)121666; + int64_t h6 = f6 * (int64_t)121666; + int64_t h7 = f7 * (int64_t)121666; + int64_t h8 = f8 * (int64_t)121666; + int64_t h9 = f9 * (int64_t)121666; + int64_t carry0; + int64_t carry1; + int64_t carry2; + int64_t carry3; + int64_t carry4; + int64_t carry5; + int64_t carry6; + int64_t carry7; + int64_t carry8; + int64_t carry9; + + carry9 = h9 + BIT(24); + h0 += (carry9 >> 25) * 19; + h9 -= carry9 & kTop39Bits; + carry1 = h1 + BIT(24); + h2 += carry1 >> 25; + h1 -= carry1 & kTop39Bits; + carry3 = h3 + BIT(24); + h4 += carry3 >> 25; + h3 -= carry3 & kTop39Bits; + carry5 = h5 + BIT(24); + h6 += carry5 >> 25; + h5 -= carry5 & kTop39Bits; + carry7 = h7 + BIT(24); + h8 += carry7 >> 25; + h7 -= carry7 & kTop39Bits; + + carry0 = h0 + BIT(25); + h1 += carry0 >> 26; + h0 -= carry0 & kTop38Bits; + carry2 = h2 + BIT(25); + h3 += carry2 >> 26; + h2 -= carry2 & kTop38Bits; + carry4 = h4 + BIT(25); + h5 += carry4 >> 26; + h4 -= carry4 & kTop38Bits; + carry6 = h6 + BIT(25); + h7 += carry6 >> 26; + h6 -= carry6 & kTop38Bits; + carry8 = h8 + BIT(25); + h9 += carry8 >> 26; + h8 -= carry8 & kTop38Bits; + + h[0] = h0; + h[1] = h1; + h[2] = h2; + h[3] = h3; + h[4] = h4; + h[5] = h5; + h[6] = h6; + h[7] = h7; + h[8] = h8; + h[9] = h9; +} + +void x25519_scalar_mult(uint8_t out[32], const uint8_t scalar[32], + const uint8_t point[32]) +{ + fe x1, x2, z2, x3, z3, tmp0, tmp1; + unsigned swap; + int pos; + + uint8_t e[32]; + memcpy(e, scalar, 32); + e[0] &= 248; + e[31] &= 127; + e[31] |= 64; + fe_frombytes(x1, point); + fe_1(x2); + fe_0(z2); + fe_copy(x3, x1); + fe_1(z3); + + swap = 0; + for (pos = 254; pos >= 0; --pos) { + unsigned b = 1 & (e[pos / 8] >> (pos & 7)); + swap ^= b; + fe_cswap(x2, x3, swap); + fe_cswap(z2, z3, swap); + swap = b; + fe_sub(tmp0, x3, z3); + fe_sub(tmp1, x2, z2); + fe_add(x2, x2, z2); + fe_add(z2, x3, z3); + fe_mul(z3, tmp0, x2); + fe_mul(z2, z2, tmp1); + fe_sq(tmp0, tmp1); + fe_sq(tmp1, x2); + fe_add(x3, z3, z2); + fe_sub(z2, z3, z2); + fe_mul(x2, tmp1, tmp0); + fe_sub(tmp1, tmp1, tmp0); + fe_sq(z2, z2); + fe_mul121666(z3, tmp1); + fe_sq(x3, x3); + fe_add(tmp0, tmp0, z3); + fe_mul(z3, x1, z2); + fe_mul(z2, tmp1, tmp0); + } + fe_cswap(x2, x3, swap); + fe_cswap(z2, z3, swap); + + fe_invert(z2, z2); + fe_mul(x2, x2, z2); + fe_tobytes(out, x2); +} -- cgit v1.2.1 From a258f2e393ecaecaf81763dc7fb9cda57f74976b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:48 -0600 Subject: board/kinox/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95361e908772ca505f7e227ba21359f2dc190f45 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728553 Reviewed-by: Jeremy Bettis --- board/kinox/board.h | 103 ++++++++++++++++++++++------------------------------ 1 file changed, 44 insertions(+), 59 deletions(-) diff --git a/board/kinox/board.h b/board/kinox/board.h index 6637fbfec1..490d5e8fae 100644 --- a/board/kinox/board.h +++ b/board/kinox/board.h @@ -19,11 +19,11 @@ /* HDMI CEC */ #define CONFIG_CEC #define CEC_GPIO_OUT GPIO_HDMI_CEC_OUT -#define CEC_GPIO_IN GPIO_HDMI_CEC_IN +#define CEC_GPIO_IN GPIO_HDMI_CEC_IN #define CEC_GPIO_PULL_UP GPIO_HDMI_CEC_PULL_UP /* USB Type A Features */ -#define USB_PORT_COUNT 4 +#define USB_PORT_COUNT 4 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -38,18 +38,18 @@ #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* The design should support up to 100W. */ /* TODO(b/197702356): Set the max PD to 60W now and change it * to 100W after we verify it. */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -57,42 +57,42 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD -#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_OD +#define GPIO_RECOVERY_L_2 GPIO_GSC_EC_RECOVERY_BTN_OD /* I2C Bus Configuration */ -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 /* I2C control host command */ #define CONFIG_HOSTCMD_I2C_CONTROL @@ -116,24 +116,18 @@ * TODO(b/197478860): Enable the fan control. We need * to check the sensor value and adjust the fan speed. */ - #define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" -enum adp_id { - UNKNOWN, - TINY, - TIO1, - TIO2, - TYPEC -}; +enum adp_id { UNKNOWN, TINY, TIO1, TIO2, TYPEC }; struct adpater_id_params { int min_voltage; @@ -170,27 +164,18 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_PORT_COUNT }; enum pwm_channel { - PWM_CH_LED_GREEN, /* PWM0 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED_RED, /* PWM2 */ + PWM_CH_LED_GREEN, /* PWM0 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED_RED, /* PWM2 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From fec7f586e1165b4ab9689140b17a5df1b583f635 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:35 -0600 Subject: chip/host/host_test.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib34251b606df6ade098f3edc65d14689a8922e44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729150 Reviewed-by: Jeremy Bettis --- chip/host/host_test.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/host/host_test.h b/chip/host/host_test.h index e2bf5448c3..2a960714b9 100644 --- a/chip/host/host_test.h +++ b/chip/host/host_test.h @@ -14,4 +14,4 @@ /* Get emulator executable name */ const char *__get_prog_name(void); -#endif /* __CROS_EC_HOST_TEST_H */ +#endif /* __CROS_EC_HOST_TEST_H */ -- cgit v1.2.1 From 2bb5b7b873345e2e0f965ecf43e81f37e9e2bbad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:56 -0600 Subject: driver/ppc/sn5s330.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iffd4ca27c93af9235859003fddde1fa1af3c173a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730051 Reviewed-by: Jeremy Bettis --- driver/ppc/sn5s330.h | 114 +++++++++++++++++++++++++-------------------------- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h index 9768906182..ebcb46ce45 100644 --- a/driver/ppc/sn5s330.h +++ b/driver/ppc/sn5s330.h @@ -27,15 +27,15 @@ enum sn5s330_pp_idx { SN5S330_PP_COUNT, }; -#define SN5S330_FUNC_SET1 0x50 -#define SN5S330_FUNC_SET2 0x51 -#define SN5S330_FUNC_SET3 0x52 -#define SN5S330_FUNC_SET4 0x53 -#define SN5S330_FUNC_SET5 0x54 -#define SN5S330_FUNC_SET6 0x55 -#define SN5S330_FUNC_SET7 0x56 -#define SN5S330_FUNC_SET8 0x57 -#define SN5S330_FUNC_SET9 0x58 +#define SN5S330_FUNC_SET1 0x50 +#define SN5S330_FUNC_SET2 0x51 +#define SN5S330_FUNC_SET3 0x52 +#define SN5S330_FUNC_SET4 0x53 +#define SN5S330_FUNC_SET5 0x54 +#define SN5S330_FUNC_SET6 0x55 +#define SN5S330_FUNC_SET7 0x56 +#define SN5S330_FUNC_SET8 0x57 +#define SN5S330_FUNC_SET9 0x58 #define SN5S330_FUNC_SET10 0x59 #define SN5S330_FUNC_SET11 0x5A #define SN5S330_FUNC_SET12 0x5B @@ -62,72 +62,72 @@ enum sn5s330_pp_idx { #define SN5S330_INT_MASK_FALL_REG2 0x2A #define SN5S330_INT_MASK_FALL_REG3 0x2B -#define PPX_ILIM_DEGLITCH_0_US_20 0x1 -#define PPX_ILIM_DEGLITCH_0_US_50 0x2 -#define PPX_ILIM_DEGLITCH_0_US_100 0x3 -#define PPX_ILIM_DEGLITCH_0_US_200 0x4 -#define PPX_ILIM_DEGLITCH_0_US_1000 0x5 -#define PPX_ILIM_DEGLITCH_0_US_2000 0x6 -#define PPX_ILIM_DEGLITCH_0_US_10000 0x7 +#define PPX_ILIM_DEGLITCH_0_US_20 0x1 +#define PPX_ILIM_DEGLITCH_0_US_50 0x2 +#define PPX_ILIM_DEGLITCH_0_US_100 0x3 +#define PPX_ILIM_DEGLITCH_0_US_200 0x4 +#define PPX_ILIM_DEGLITCH_0_US_1000 0x5 +#define PPX_ILIM_DEGLITCH_0_US_2000 0x6 +#define PPX_ILIM_DEGLITCH_0_US_10000 0x7 /* Internal VBUS Switch Current Limit Settings (min) */ -#define SN5S330_ILIM_0_35 0 -#define SN5S330_ILIM_0_63 1 -#define SN5S330_ILIM_0_90 2 -#define SN5S330_ILIM_1_14 3 -#define SN5S330_ILIM_1_38 4 -#define SN5S330_ILIM_1_62 5 -#define SN5S330_ILIM_1_86 6 -#define SN5S330_ILIM_2_10 7 -#define SN5S330_ILIM_2_34 8 -#define SN5S330_ILIM_2_58 9 -#define SN5S330_ILIM_2_82 10 -#define SN5S330_ILIM_3_06 11 -#define SN5S330_ILIM_3_30 12 +#define SN5S330_ILIM_0_35 0 +#define SN5S330_ILIM_0_63 1 +#define SN5S330_ILIM_0_90 2 +#define SN5S330_ILIM_1_14 3 +#define SN5S330_ILIM_1_38 4 +#define SN5S330_ILIM_1_62 5 +#define SN5S330_ILIM_1_86 6 +#define SN5S330_ILIM_2_10 7 +#define SN5S330_ILIM_2_34 8 +#define SN5S330_ILIM_2_58 9 +#define SN5S330_ILIM_2_82 10 +#define SN5S330_ILIM_3_06 11 +#define SN5S330_ILIM_3_30 12 /* FUNC_SET_2 */ -#define SN5S330_SBU_EN BIT(4) +#define SN5S330_SBU_EN BIT(4) /* FUNC_SET_3 */ -#define SN5S330_PP1_EN BIT(0) -#define SN5S330_PP2_EN BIT(1) -#define SN5S330_VBUS_DISCH_EN BIT(2) -#define SN5S330_SET_RCP_MODE_PP1 BIT(5) -#define SN5S330_SET_RCP_MODE_PP2 BIT(6) +#define SN5S330_PP1_EN BIT(0) +#define SN5S330_PP2_EN BIT(1) +#define SN5S330_VBUS_DISCH_EN BIT(2) +#define SN5S330_SET_RCP_MODE_PP1 BIT(5) +#define SN5S330_SET_RCP_MODE_PP2 BIT(6) /* FUNC_SET_4 */ -#define SN5S330_VCONN_EN BIT(0) -#define SN5S330_CC_POLARITY BIT(1) -#define SN5S330_CC_EN BIT(4) -#define SN5S330_VCONN_ILIM_SEL BIT(5) +#define SN5S330_VCONN_EN BIT(0) +#define SN5S330_CC_POLARITY BIT(1) +#define SN5S330_CC_EN BIT(4) +#define SN5S330_VCONN_ILIM_SEL BIT(5) /* FUNC_SET_8 */ -#define SN5S330_VCONN_DEGLITCH_MASK (3 << 6) -#define SN5S330_VCONN_DEGLITCH_63_US (0 << 6) -#define SN5S330_VCONN_DEGLITCH_125_US BIT(6) -#define SN5S330_VCONN_DEGLITCH_640_US (2 << 6) -#define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6) +#define SN5S330_VCONN_DEGLITCH_MASK (3 << 6) +#define SN5S330_VCONN_DEGLITCH_63_US (0 << 6) +#define SN5S330_VCONN_DEGLITCH_125_US BIT(6) +#define SN5S330_VCONN_DEGLITCH_640_US (2 << 6) +#define SN5S330_VCONN_DEGLITCH_1280_US (3 << 6) /* FUNC_SET_9 */ -#define SN5S330_FORCE_OVP_EN_SBU BIT(1) -#define SN5S330_PP2_CONFIG BIT(2) -#define SN5S330_PWR_OVR_VBUS BIT(3) -#define SN5S330_OVP_EN_CC BIT(4) -#define SN5S330_CONFIG_UVP BIT(5) -#define SN5S330_FORCE_ON_VBUS_OVP BIT(6) -#define SN5S330_FORCE_ON_VBUS_UVP BIT(7) +#define SN5S330_FORCE_OVP_EN_SBU BIT(1) +#define SN5S330_PP2_CONFIG BIT(2) +#define SN5S330_PWR_OVR_VBUS BIT(3) +#define SN5S330_OVP_EN_CC BIT(4) +#define SN5S330_CONFIG_UVP BIT(5) +#define SN5S330_FORCE_ON_VBUS_OVP BIT(6) +#define SN5S330_FORCE_ON_VBUS_UVP BIT(7) /* INT_STATUS_REG3 */ -#define SN5S330_VBUS_GOOD BIT(0) +#define SN5S330_VBUS_GOOD BIT(0) /* INT_STATUS_REG4 */ -#define SN5S330_DIG_RES BIT(0) -#define SN5S330_DB_BOOT BIT(1) -#define SN5S330_VSAFE0V_STAT BIT(2) -#define SN5S330_VSAFE0V_MASK BIT(3) +#define SN5S330_DIG_RES BIT(0) +#define SN5S330_DB_BOOT BIT(1) +#define SN5S330_VSAFE0V_STAT BIT(2) +#define SN5S330_VSAFE0V_MASK BIT(3) /* FUNC_SET_10 */ -#define SN5S330_PP1_RCP_OFFSET BIT(4) +#define SN5S330_PP1_RCP_OFFSET BIT(4) /* * INT_MASK_RISE/FALL_EDGE_1 -- cgit v1.2.1 From 099250b1a657e2a608634caafb44a33b49721536 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:10 -0600 Subject: board/crota/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46d225e0d628239f3d08030731baa092605c0bb0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728211 Reviewed-by: Jeremy Bettis --- board/crota/i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/crota/i2c.c b/board/crota/i2c.c index e7172ef22b..6f9df1f5a9 100644 --- a/board/crota/i2c.c +++ b/board/crota/i2c.c @@ -9,7 +9,7 @@ #include "hooks.h" #include "i2c.h" -#define BOARD_ID_FAST_PLUS_CAPABLE 2 +#define BOARD_ID_FAST_PLUS_CAPABLE 2 /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { -- cgit v1.2.1 From 333496f3412c9cf8b1ec09a41ae5fae54d16794d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:59 -0600 Subject: chip/stm32/usb-stream.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b6ccb48f3b99be5f391ff4ac296dba3c54bf9e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729549 Reviewed-by: Jeremy Bettis --- chip/stm32/usb-stream.h | 212 ++++++++++++++++++++---------------------------- 1 file changed, 89 insertions(+), 123 deletions(-) diff --git a/chip/stm32/usb-stream.h b/chip/stm32/usb-stream.h index 915d8905cd..677ae462fd 100644 --- a/chip/stm32/usb-stream.h +++ b/chip/stm32/usb-stream.h @@ -118,32 +118,25 @@ extern struct producer_ops const usb_stream_producer_ops; * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1); * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1); */ -#define USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - INTERFACE_CLASS, \ - INTERFACE_SUBCLASS, \ - INTERFACE_PROTOCOL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - \ - BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ - BUILD_ASSERT(RX_SIZE > 0); \ - BUILD_ASSERT(TX_SIZE > 0); \ - BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ - (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ - BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ - (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ - \ - static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ - static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ - static struct usb_stream_state CONCAT2(NAME, _state); \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ +#define USB_STREAM_CONFIG_FULL(NAME, INTERFACE, INTERFACE_CLASS, \ + INTERFACE_SUBCLASS, INTERFACE_PROTOCOL, \ + INTERFACE_NAME, ENDPOINT, RX_SIZE, TX_SIZE, \ + RX_QUEUE, TX_QUEUE) \ + \ + BUILD_ASSERT(RX_SIZE <= USB_MAX_PACKET_SIZE); \ + BUILD_ASSERT(TX_SIZE <= USB_MAX_PACKET_SIZE); \ + BUILD_ASSERT(RX_SIZE > 0); \ + BUILD_ASSERT(TX_SIZE > 0); \ + BUILD_ASSERT((RX_SIZE < 64 && (RX_SIZE & 0x01) == 0) || \ + (RX_SIZE < 1024 && (RX_SIZE & 0x1f) == 0)); \ + BUILD_ASSERT((TX_SIZE < 64 && (TX_SIZE & 0x01) == 0) || \ + (TX_SIZE < 1024 && (TX_SIZE & 0x1f) == 0)); \ + \ + static usb_uint CONCAT2(NAME, _ep_rx_buffer)[RX_SIZE / 2] __usb_ram; \ + static usb_uint CONCAT2(NAME, _ep_tx_buffer)[TX_SIZE / 2] __usb_ram; \ + static struct usb_stream_state CONCAT2(NAME, _state); \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ struct usb_stream_config const NAME = { \ .state = &CONCAT2(NAME, _state), \ .endpoint = ENDPOINT, \ @@ -160,107 +153,80 @@ extern struct producer_ops const usb_stream_producer_ops; .queue = &RX_QUEUE, \ .ops = &usb_stream_producer_ops, \ }, \ - }; \ - const struct usb_interface_descriptor \ - USB_IFACE_DESC(INTERFACE) = { \ - .bLength = USB_DT_INTERFACE_SIZE, \ - .bDescriptorType = USB_DT_INTERFACE, \ - .bInterfaceNumber = INTERFACE, \ - .bAlternateSetting = 0, \ - .bNumEndpoints = 2, \ - .bInterfaceClass = INTERFACE_CLASS, \ - .bInterfaceSubClass = INTERFACE_SUBCLASS, \ - .bInterfaceProtocol = INTERFACE_PROTOCOL, \ - .iInterface = INTERFACE_NAME, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 0) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = 0x80 | ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk IN */, \ - .wMaxPacketSize = TX_SIZE, \ - .bInterval = 10, \ - }; \ - const struct usb_endpoint_descriptor \ - USB_EP_DESC(INTERFACE, 1) = { \ - .bLength = USB_DT_ENDPOINT_SIZE, \ - .bDescriptorType = USB_DT_ENDPOINT, \ - .bEndpointAddress = ENDPOINT, \ - .bmAttributes = 0x02 /* Bulk OUT */, \ - .wMaxPacketSize = RX_SIZE, \ - .bInterval = 0, \ - }; \ - static void CONCAT2(NAME, _ep_tx)(void) \ - { \ - usb_stream_tx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_rx)(void) \ - { \ - usb_stream_rx(&NAME); \ - } \ - static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ - { \ - usb_stream_event(&NAME, evt); \ - } \ - USB_DECLARE_EP(ENDPOINT, \ - CONCAT2(NAME, _ep_tx), \ - CONCAT2(NAME, _ep_rx), \ - CONCAT2(NAME, _ep_event)); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_stream_deferred(&NAME); } + }; \ + const struct usb_interface_descriptor USB_IFACE_DESC(INTERFACE) = { \ + .bLength = USB_DT_INTERFACE_SIZE, \ + .bDescriptorType = USB_DT_INTERFACE, \ + .bInterfaceNumber = INTERFACE, \ + .bAlternateSetting = 0, \ + .bNumEndpoints = 2, \ + .bInterfaceClass = INTERFACE_CLASS, \ + .bInterfaceSubClass = INTERFACE_SUBCLASS, \ + .bInterfaceProtocol = INTERFACE_PROTOCOL, \ + .iInterface = INTERFACE_NAME, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 0) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = 0x80 | ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk IN */, \ + .wMaxPacketSize = TX_SIZE, \ + .bInterval = 10, \ + }; \ + const struct usb_endpoint_descriptor USB_EP_DESC(INTERFACE, 1) = { \ + .bLength = USB_DT_ENDPOINT_SIZE, \ + .bDescriptorType = USB_DT_ENDPOINT, \ + .bEndpointAddress = ENDPOINT, \ + .bmAttributes = 0x02 /* Bulk OUT */, \ + .wMaxPacketSize = RX_SIZE, \ + .bInterval = 0, \ + }; \ + static void CONCAT2(NAME, _ep_tx)(void) \ + { \ + usb_stream_tx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_rx)(void) \ + { \ + usb_stream_rx(&NAME); \ + } \ + static void CONCAT2(NAME, _ep_event)(enum usb_ep_event evt) \ + { \ + usb_stream_event(&NAME, evt); \ + } \ + USB_DECLARE_EP(ENDPOINT, CONCAT2(NAME, _ep_tx), CONCAT2(NAME, _ep_rx), \ + CONCAT2(NAME, _ep_event)); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_stream_deferred(&NAME); \ + } /* This is a short version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE) +#define USB_STREAM_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT, RX_SIZE, \ + TX_SIZE, RX_QUEUE, TX_QUEUE) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, TX_QUEUE) /* Declare a utility interface for setting parity/baud. */ -#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ - static int CONCAT2(NAME, _interface_)(usb_uint *rx_buf, \ - usb_uint *tx_buf) \ - { return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ - rx_buf, tx_buf); } \ - USB_DECLARE_IFACE(INTERFACE, \ - CONCAT2(NAME, _interface_)) +#define USB_USART_IFACE(NAME, INTERFACE, USART_CFG) \ + static int CONCAT2(NAME, _interface_)(usb_uint * rx_buf, \ + usb_uint * tx_buf) \ + { \ + return usb_usart_interface(&NAME, &USART_CFG, INTERFACE, \ + rx_buf, tx_buf); \ + } \ + USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_)) /* This is a medium version for declaring Google serial endpoints */ -#define USB_STREAM_CONFIG_USART_IFACE(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE, \ - USART_CFG) \ - USB_STREAM_CONFIG_FULL(NAME, \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_SERIAL, \ - USB_PROTOCOL_GOOGLE_SERIAL, \ - INTERFACE_NAME, \ - ENDPOINT, \ - RX_SIZE, \ - TX_SIZE, \ - RX_QUEUE, \ - TX_QUEUE); \ +#define USB_STREAM_CONFIG_USART_IFACE(NAME, INTERFACE, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \ + TX_QUEUE, USART_CFG) \ + USB_STREAM_CONFIG_FULL(NAME, INTERFACE, USB_CLASS_VENDOR_SPEC, \ + USB_SUBCLASS_GOOGLE_SERIAL, \ + USB_PROTOCOL_GOOGLE_SERIAL, INTERFACE_NAME, \ + ENDPOINT, RX_SIZE, TX_SIZE, RX_QUEUE, \ + TX_QUEUE); \ USB_USART_IFACE(NAME, INTERFACE, USART_CFG) /* @@ -285,8 +251,8 @@ enum usb_usart { #define USB_USART_BAUD_MULTIPLIER 100 int usb_usart_interface(struct usb_stream_config const *config, - struct usart_config const *usart, - int interface, usb_uint *rx_buf, usb_uint *tx_buf); + struct usart_config const *usart, int interface, + usb_uint *rx_buf, usb_uint *tx_buf); /* * These functions are used by the trampoline functions defined above to -- cgit v1.2.1 From fcd066471349046d0e4a70893b9305bc2ffeb6b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:14 -0600 Subject: board/guybrush/board_fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1a17b23468cd1797920eb292ff1fdd738f4a42f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728439 Reviewed-by: Jeremy Bettis --- board/guybrush/board_fw_config.h | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/board/guybrush/board_fw_config.h b/board/guybrush/board_fw_config.h index 1de417d77a..b51eddaa08 100644 --- a/board/guybrush/board_fw_config.h +++ b/board/guybrush/board_fw_config.h @@ -13,26 +13,25 @@ /* * USB Daughter Board (2 bits) */ -#define FW_CONFIG_USB_DB_OFFSET 0 -#define FW_CONFIG_USB_DB_WIDTH 2 -#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0 -#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1 +#define FW_CONFIG_USB_DB_OFFSET 0 +#define FW_CONFIG_USB_DB_WIDTH 2 +#define FW_CONFIG_USB_DB_A1_PS8811_C1_PS8818 0 +#define FW_CONFIG_USB_DB_A1_ANX7491_C1_ANX7451 1 /* * Form Factor (1 bits) */ -#define FW_CONFIG_FORM_FACTOR_OFFSET 2 -#define FW_CONFIG_FORM_FACTOR_WIDTH 1 -#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0 -#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1 +#define FW_CONFIG_FORM_FACTOR_OFFSET 2 +#define FW_CONFIG_FORM_FACTOR_WIDTH 1 +#define FW_CONFIG_FORM_FACTOR_CLAMSHELL 0 +#define FW_CONFIG_FORM_FACTOR_CONVERTIBLE 1 /* * Keyboard Backlight (1 bit) */ -#define FW_CONFIG_KBLIGHT_OFFSET 3 -#define FW_CONFIG_KBLIGHT_WIDTH 1 -#define FW_CONFIG_KBLIGHT_NO 0 -#define FW_CONFIG_KBLIGHT_YES 1 - +#define FW_CONFIG_KBLIGHT_OFFSET 3 +#define FW_CONFIG_KBLIGHT_WIDTH 1 +#define FW_CONFIG_KBLIGHT_NO 0 +#define FW_CONFIG_KBLIGHT_YES 1 #endif /* _GUYBRUSH_CBI_FW_CONFIG__H_ */ -- cgit v1.2.1 From ea22292d1dc1be5c3dcd5520bef7e8109be1089f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:15 -0600 Subject: chip/mchp/dma_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9830427d0d2708b4fd38acfedcab13a89e4ec1fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729241 Reviewed-by: Jeremy Bettis --- chip/mchp/dma_chip.h | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/chip/mchp/dma_chip.h b/chip/mchp/dma_chip.h index 42bcb095f6..99f9fda90f 100644 --- a/chip/mchp/dma_chip.h +++ b/chip/mchp/dma_chip.h @@ -16,24 +16,22 @@ #include #include - #ifdef __cplusplus extern "C" { #endif /* Place any C interfaces here */ -void dma_xfr_start_rx(const struct dma_option *option, - uint32_t dma_xfr_ulen, - uint32_t count, void *memory); +void dma_xfr_start_rx(const struct dma_option *option, uint32_t dma_xfr_ulen, + uint32_t count, void *memory); void dma_xfr_prepare_tx(const struct dma_option *option, uint32_t count, - const void *memory, uint32_t dma_xfr_units); + const void *memory, uint32_t dma_xfr_units); void dma_clr_chan(enum dma_channel ch); -void dma_cfg_buffers(enum dma_channel ch, const void *membuf, - uint32_t nb, const void *pdev); +void dma_cfg_buffers(enum dma_channel ch, const void *membuf, uint32_t nb, + const void *pdev); /* * ch = zero based DMA channel number @@ -44,13 +42,13 @@ void dma_cfg_buffers(enum dma_channel ch, const void *membuf, * b[2] = 1 increment device address * b[3] = disable HW flow control */ -#define DMA_FLAG_D2M 0 -#define DMA_FLAG_M2D 1 -#define DMA_FLAG_INCR_MEM 2 -#define DMA_FLAG_INCR_DEV 4 -#define DMA_FLAG_SW_FLOW 8 -void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, - uint8_t dev_id, uint8_t flags); +#define DMA_FLAG_D2M 0 +#define DMA_FLAG_M2D 1 +#define DMA_FLAG_INCR_MEM 2 +#define DMA_FLAG_INCR_DEV 4 +#define DMA_FLAG_SW_FLOW 8 +void dma_cfg_xfr(enum dma_channel ch, uint8_t unit_len, uint8_t dev_id, + uint8_t flags); void dma_run(enum dma_channel ch); -- cgit v1.2.1 From 68eaf9f5224db77dc2a9bd727d9f377e0d46c1c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:22 -0600 Subject: baseboard/brya/prochot.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb21cc7bfb6eedc7a5488ca8450a13e739e2b921 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727865 Reviewed-by: Jeremy Bettis --- baseboard/brya/prochot.c | 76 +++++++++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 33 deletions(-) diff --git a/baseboard/brya/prochot.c b/baseboard/brya/prochot.c index 666f2ca35b..02c4ca5262 100644 --- a/baseboard/brya/prochot.c +++ b/baseboard/brya/prochot.c @@ -16,10 +16,10 @@ #include "task.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) -#define ADT_RATING_W (PD_MAX_POWER_MW / 1000) -#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0) +#define ADT_RATING_W (PD_MAX_POWER_MW / 1000) +#define PROCHOT_EVENT_200MS_TICK TASK_EVENT_CUSTOM_BIT(0) struct batt_para { int battery_continuous_discharge_mw; @@ -80,8 +80,9 @@ static int get_batt_parameter(void) rv |= sb_read(SB_DESIGN_VOLTAGE, &battery_design_voltage_mv); rv |= sb_read(SB_DESIGN_CAPACITY, &battery_design_capacity_mAh); - batt_params.battery_design_mWh = (battery_design_voltage_mv * - battery_design_capacity_mAh) / 1000; + batt_params.battery_design_mWh = + (battery_design_voltage_mv * battery_design_capacity_mAh) / + 1000; if (sb_read(SB_RELATIVE_STATE_OF_CHARGE, &batt_params.state_of_charge)) batt_params.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE; @@ -109,7 +110,7 @@ static int set_register_charge_option(void) int rv; rv = i2c_read16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS, - BQ25710_REG_CHARGE_OPTION_0, ®); + BQ25710_REG_CHARGE_OPTION_0, ®); if (rv == EC_SUCCESS) { reg = SET_BQ_FIELD(BQ257X0, CHARGE_OPTION_0, IADP_GAIN, 1, reg); /* if AC only, disable IDPM, @@ -127,7 +128,7 @@ static int set_register_charge_option(void) } return i2c_write16(I2C_PORT_CHARGER, BQ25710_SMBUS_ADDR1_FLAGS, - BQ25710_REG_CHARGE_OPTION_0, reg); + BQ25710_REG_CHARGE_OPTION_0, reg); } static void assert_prochot(void) @@ -154,7 +155,7 @@ static void assert_prochot(void) /* When battery is discharging, the battery current will be negative */ if (batt_params.battery_continuous_discharge_mw < 0) { total_W = adpt_mw + - ABS(batt_params.battery_continuous_discharge_mw); + ABS(batt_params.battery_continuous_discharge_mw); } else { /* we won't assert prochot when battery is charging. */ total_W = adpt_mw; @@ -177,15 +178,18 @@ static void assert_prochot(void) if (!battery_hw_present()) { gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { - batt_params.battery_continuous_discharge_mw = - ABS(batt_params.battery_continuous_discharge_mw); + batt_params.battery_continuous_discharge_mw = ABS( + batt_params.battery_continuous_discharge_mw); if ((batt_params.battery_continuous_discharge_mw / - 1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_ASSERTION_BATTERY_RATIO / 100) + 1000) > BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_ASSERTION_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if ((batt_params.battery_continuous_discharge_mw - / 1000) < BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_DEASSERTION_BATTERY_RATIO / 100) + else if ((batt_params.battery_continuous_discharge_mw / + 1000) < + BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_DEASSERTION_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } return; @@ -195,42 +199,48 @@ static void assert_prochot(void) /* if adapter >= 60W */ /* if no battery or battery < 10% */ if (!battery_hw_present() || - batt_params.state_of_charge <= 10) { - if (total_W > ADT_RATING_W * - PROCHOT_ASSERTION_PD_RATIO / 100) + batt_params.state_of_charge <= 10) { + if (total_W > + ADT_RATING_W * PROCHOT_ASSERTION_PD_RATIO / 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W <= ADT_RATING_W * - PROCHOT_DEASSERTION_PD_RATIO / 100) + else if (total_W <= + ADT_RATING_W * PROCHOT_DEASSERTION_PD_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { /* AC + battery */ - if (total_W > (ADT_RATING_W + - BATT_MAX_CONTINUE_DISCHARGE_WATT)) + if (total_W > + (ADT_RATING_W + BATT_MAX_CONTINUE_DISCHARGE_WATT)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W < (ADT_RATING_W + - BATT_MAX_CONTINUE_DISCHARGE_WATT) * - PROCHOT_DEASSERTION_PD_BATTERY_RATIO / 100) + else if (total_W < + (ADT_RATING_W + + BATT_MAX_CONTINUE_DISCHARGE_WATT) * + PROCHOT_DEASSERTION_PD_BATTERY_RATIO / + 100) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } } else { /* if adapter < 60W */ /* if no battery or battery < 10% */ if (!battery_hw_present() || - batt_params.state_of_charge <= 10) { + batt_params.state_of_charge <= 10) { if (total_W > (adapter_wattage * - PROCHOT_ASSERTION_ADAPTER_RATIO / 100)) + PROCHOT_ASSERTION_ADAPTER_RATIO / 100)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W <= (adapter_wattage * - PROCHOT_DEASSERTION_ADAPTER_RATIO / 100)) + else if (total_W <= + (adapter_wattage * + PROCHOT_DEASSERTION_ADAPTER_RATIO / 100)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } else { /* AC + battery */ if (total_W > (adapter_wattage + - BATT_MAX_CONTINUE_DISCHARGE_WATT)) + BATT_MAX_CONTINUE_DISCHARGE_WATT)) gpio_set_level(GPIO_EC_PROCHOT_ODL, 0); - else if (total_W < (adapter_wattage + - (BATT_MAX_CONTINUE_DISCHARGE_WATT * - PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO / 100))) + else if (total_W < + (adapter_wattage + + (BATT_MAX_CONTINUE_DISCHARGE_WATT * + PROCHOT_DEASSERTION_ADAPTER_BATT_RATIO / + 100))) gpio_set_level(GPIO_EC_PROCHOT_ODL, 1); } } -- cgit v1.2.1 From 85cb49fe4c322f4de463a675b0b56bf27451acd6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:32 -0600 Subject: chip/stm32/config-stm32f09x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide16434acf166232aeee8e9c98bc2a71bf1c8523 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729472 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32f09x.h | 52 +++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/chip/stm32/config-stm32f09x.h b/chip/stm32/config-stm32f09x.h index 527e84db1b..20bcf1728b 100644 --- a/chip/stm32/config-stm32f09x.h +++ b/chip/stm32/config-stm32f09x.h @@ -9,15 +9,15 @@ * Write protect sectors: 31 4KB sectors, one 132KB sector */ #define CONFIG_FLASH_SIZE_BYTES 0x00040000 -#define CONFIG_FLASH_BANK_SIZE 0x1000 -#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ -#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ +#define CONFIG_FLASH_BANK_SIZE 0x1000 +#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */ +#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */ /* No page mode on STM32F, so no benefit to larger write sizes */ #define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002 -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00008000 +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00008000 /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 @@ -43,33 +43,33 @@ * */ -#define _SECTOR_4KB (4 * 1024) -#define _SECTOR_132KB (132 * 1024) +#define _SECTOR_4KB (4 * 1024) +#define _SECTOR_132KB (132 * 1024) /* The EC uses one sector to emulate persistent state */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB -#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) +#define CONFIG_FW_PSTATE_SIZE _SECTOR_4KB +#define CONFIG_FW_PSTATE_OFF (30 * _SECTOR_4KB) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE _SECTOR_132KB +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (30 * _SECTOR_4KB) +#define CONFIG_RW_MEM_OFF \ + (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE _SECTOR_132KB -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 32 -#define WP_BANK_COUNT 31 -#define PSTATE_BANK 30 -#define PSTATE_BANK_COUNT 1 +#define PHYSICAL_BANKS 32 +#define WP_BANK_COUNT 31 +#define PSTATE_BANK 30 +#define PSTATE_BANK_COUNT 1 -- cgit v1.2.1 From f96ef43f2c609d2201c352c3e02a5b21df7edf11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:25 -0600 Subject: include/otp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2bf66d45834eb252a05cfaaa9c7b6cd806477c21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730374 Reviewed-by: Jeremy Bettis --- include/otp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/otp.h b/include/otp.h index 7851411202..a95bf28426 100644 --- a/include/otp.h +++ b/include/otp.h @@ -29,4 +29,4 @@ int otp_write_serial(const char *serialno); */ const char *otp_read_serial(void); -#endif /* __CROS_EC_OTP_H */ +#endif /* __CROS_EC_OTP_H */ -- cgit v1.2.1 From a2cc33019828765a669d1e9e14c1959f72e126cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:33:37 -0600 Subject: common/audio_codec_dmic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a8aa84ce4038673be36a78848092c06d90c99d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729565 Reviewed-by: Jeremy Bettis --- common/audio_codec_dmic.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/common/audio_codec_dmic.c b/common/audio_codec_dmic.c index c4f0b07a46..d3a6adccd2 100644 --- a/common/audio_codec_dmic.c +++ b/common/audio_codec_dmic.c @@ -8,7 +8,7 @@ #include "console.h" #include "host_command.h" -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) static enum ec_status dmic_get_max_gain(struct host_cmd_handler_args *args) { @@ -25,9 +25,9 @@ static enum ec_status dmic_set_gain_idx(struct host_cmd_handler_args *args) { const struct ec_param_ec_codec_dmic *p = args->params; - if (audio_codec_dmic_set_gain_idx( - p->set_gain_idx_param.channel, - p->set_gain_idx_param.gain) != EC_SUCCESS) + if (audio_codec_dmic_set_gain_idx(p->set_gain_idx_param.channel, + p->set_gain_idx_param.gain) != + EC_SUCCESS) return EC_RES_ERROR; return EC_RES_SUCCESS; @@ -38,8 +38,8 @@ static enum ec_status dmic_get_gain_idx(struct host_cmd_handler_args *args) const struct ec_param_ec_codec_dmic *p = args->params; struct ec_response_ec_codec_dmic_get_gain_idx *r = args->response; - if (audio_codec_dmic_get_gain_idx( - p->get_gain_idx_param.channel, &r->gain) != EC_SUCCESS) + if (audio_codec_dmic_get_gain_idx(p->get_gain_idx_param.channel, + &r->gain) != EC_SUCCESS) return EC_RES_ERROR; args->response_size = sizeof(*r); -- cgit v1.2.1 From 758bdfdbe22436e8ef1b78207abcd60a5cb890e1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:25 -0600 Subject: chip/ish/uart.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I47c121973fe91bf69a2f804d3441f62465a9d1cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729190 Reviewed-by: Jeremy Bettis --- chip/ish/uart.c | 38 ++++++++++++++++---------------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/chip/ish/uart.c b/chip/ish/uart.c index 71d8a41397..f292b34b2e 100644 --- a/chip/ish/uart.c +++ b/chip/ish/uart.c @@ -17,20 +17,14 @@ #include "system.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) static const uint32_t baud_conf[][BAUD_TABLE_MAX] = { - {B9600, 9600}, - {B57600, 57600}, - {B115200, 115200}, - {B921600, 921600}, - {B2000000, 2000000}, - {B3000000, 3000000}, - {B3250000, 3250000}, - {B3500000, 3500000}, - {B4000000, 4000000}, - {B19200, 19200}, + { B9600, 9600 }, { B57600, 57600 }, { B115200, 115200 }, + { B921600, 921600 }, { B2000000, 2000000 }, { B3000000, 3000000 }, + { B3250000, 3250000 }, { B3500000, 3500000 }, { B4000000, 4000000 }, + { B19200, 19200 }, }; static struct uart_ctx uart_ctx[UART_DEVICES] = { @@ -146,7 +140,7 @@ static int uart_return_baud_rate_by_id(int baud_rate_id) static void uart_hw_init(enum UART_PORT id) { - uint32_t divisor; /* baud rate divisor */ + uint32_t divisor; /* baud rate divisor */ uint8_t mcr = 0; uint8_t fcr = 0; struct uart_ctx *ctx = &uart_ctx[id]; @@ -156,7 +150,8 @@ static void uart_hw_init(enum UART_PORT id) divisor = (ctx->input_freq / ctx->baud_rate) >> 4; if (IS_ENABLED(CONFIG_ISH_DW_UART)) { /* calculate the fractional part */ - fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4); + fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - + (divisor << 4); } else { MUL(ctx->id) = (divisor * ctx->baud_rate); DIV(ctx->id) = (ctx->input_freq / 16); @@ -189,8 +184,7 @@ static void uart_hw_init(enum UART_PORT id) fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1; /* configure FIFOs */ - FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE - | FCR_RESET_RX | FCR_RESET_TX); + FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE | FCR_RESET_RX | FCR_RESET_TX); if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* enable UART unit */ @@ -229,8 +223,8 @@ static void uart_stop_hw(enum UART_PORT id) if (!IS_ENABLED(CONFIG_ISH_DW_UART)) { /* Manually clearing the fifo from possible noise. - * Entering D0i3 when fifo is not cleared may result in a hang. - */ + * Entering D0i3 when fifo is not cleared may result in a hang. + */ fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS; for (i = 0; i < fifo_len; i++) @@ -280,10 +274,10 @@ static void uart_drv_init(void) if (!IS_ENABLED(CONFIG_ISH_DW_UART)) /* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit - * to allow PMU to clock gate ISH - */ - HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN - | GIEN_UART1_EN | GIEN_PWR_MGMT); + * to allow PMU to clock gate ISH + */ + HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN | GIEN_UART1_EN | + GIEN_PWR_MGMT); task_enable_irq(ISH_DEBUG_UART_IRQ); } -- cgit v1.2.1 From 6c867258e9fe530b28a291a0f546bd4a8d897749 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:53 -0600 Subject: board/volmar/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia16edb419e08dd42edc9e3e2b5ffa0c689861875 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729065 Reviewed-by: Jeremy Bettis --- board/volmar/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/volmar/fans.c b/board/volmar/fans.c index 4fb92f2cf4..7cc1737775 100644 --- a/board/volmar/fans.c +++ b/board/volmar/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From f801112609f403060db03ca4d88f2a4f051b6a4c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:02 -0600 Subject: board/zinger/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib1704cb50634186a1c824018a3a9d012d21dec6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729143 Reviewed-by: Jeremy Bettis --- board/zinger/usb_pd_pdo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/zinger/usb_pd_pdo.c b/board/zinger/usb_pd_pdo.c index 13f8407d6d..11e5bcb8d3 100644 --- a/board/zinger/usb_pd_pdo.c +++ b/board/zinger/usb_pd_pdo.c @@ -9,7 +9,7 @@ /* Power Delivery Objects */ const uint32_t pd_src_pdo[] = { - [PDO_IDX_5V] = PDO_FIXED(5000, RATED_CURRENT, PDO_FIXED_FLAGS), + [PDO_IDX_5V] = PDO_FIXED(5000, RATED_CURRENT, PDO_FIXED_FLAGS), [PDO_IDX_12V] = PDO_FIXED(12000, RATED_CURRENT, PDO_FIXED_FLAGS), [PDO_IDX_20V] = PDO_FIXED(20000, RATED_CURRENT, PDO_FIXED_FLAGS), }; -- cgit v1.2.1 From 5a4176a03763a2e0f1ff1799dfe818583805a861 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:37 -0600 Subject: board/eldrid/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I84daeab7476d2ee1e48af6c8fe51120225551ba8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728265 Reviewed-by: Jeremy Bettis --- board/eldrid/board.h | 100 ++++++++++++++++++++++++--------------------------- 1 file changed, 47 insertions(+), 53 deletions(-) diff --git a/board/eldrid/board.h b/board/eldrid/board.h index df785a5573..4deae609d5 100644 --- a/board/eldrid/board.h +++ b/board/eldrid/board.h @@ -40,7 +40,7 @@ * TODO(b/170966461): Re-enable Vivaldi keyboard once * 8042 and MKBP drivers can coexist. */ -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI /* Sensors */ /* BMA253 accelerometer in base */ @@ -52,37 +52,36 @@ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(LID_ACCEL)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(LID_ACCEL)) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ /* BC 1.2 */ @@ -92,8 +91,8 @@ #define CONFIG_CUSTOM_FAN_CONTROL /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Retimer */ #undef CONFIG_USBC_RETIMER_INTEL_BB @@ -105,44 +104,43 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_ACCEL I2C_PORT_SENSOR -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -168,11 +166,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From b710633a36c40db85638b139b84c29e4764e657c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:57 -0600 Subject: driver/accelgyro_lsm6dsm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1baf2d4c53be540844403cc3d5cfb6e8b71a7177 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729895 Reviewed-by: Jeremy Bettis --- driver/accelgyro_lsm6dsm.c | 89 ++++++++++++++++++++-------------------------- 1 file changed, 39 insertions(+), 50 deletions(-) diff --git a/driver/accelgyro_lsm6dsm.c b/driver/accelgyro_lsm6dsm.c index 78dafc0e52..fcfe38d98e 100644 --- a/driver/accelgyro_lsm6dsm.c +++ b/driver/accelgyro_lsm6dsm.c @@ -25,11 +25,11 @@ #endif #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCEL_LSM6DSM_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; /** * Gets the sensor type associated with the dev_fifo enum. This type can be used @@ -55,7 +55,7 @@ static inline uint8_t get_sensor_type(enum dev_fifo fifo_type) static inline int get_xyz_reg(enum motionsensor_type type) { return LSM6DSM_ACCEL_OUT_X_L_ADDR - - (LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type; + (LSM6DSM_ACCEL_OUT_X_L_ADDR - LSM6DSM_GYRO_OUT_X_L_ADDR) * type; } /** @@ -77,13 +77,12 @@ __maybe_unused static int config_interrupt(const struct motion_sensor_t *accel) LSM6DSM_FIFO_CTRL1_ADDR, OUT_XYZ_SIZE / sizeof(uint16_t))); int1_ctrl_val |= LSM6DSM_INT_FIFO_TH | LSM6DSM_INT_FIFO_OVR | - LSM6DSM_INT_FIFO_FULL; + LSM6DSM_INT_FIFO_FULL; return st_raw_write8(accel->port, accel->i2c_spi_addr_flags, - LSM6DSM_INT1_CTRL, int1_ctrl_val); + LSM6DSM_INT1_CTRL, int1_ctrl_val); } - /** * fifo_disable - set fifo mode * @accel: Motion sensor pointer: must be MOTIONSENSE_TYPE_ACCEL. @@ -132,7 +131,6 @@ static int fifo_enable(const struct motion_sensor_t *accel) MOTIONSENSE_TYPE_MAG, }; - /* Search for min and max odr values for acc, gyro. */ for (i = FIFO_DEV_GYRO; i < FIFO_DEV_NUM; i++) { /* Check if sensor enabled with ODR. */ @@ -151,8 +149,7 @@ static int fifo_enable(const struct motion_sensor_t *accel) } /* FIFO ODR must be set before the decimation factors */ - odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) << - LSM6DSM_FIFO_CTRL5_ODR_OFF; + odr_reg_val = LSM6DSM_ODR_TO_REG(max_odr) << LSM6DSM_FIFO_CTRL5_ODR_OFF; err = st_raw_write8(accel->port, accel->i2c_spi_addr_flags, LSM6DSM_FIFO_CTRL5_ADDR, odr_reg_val); @@ -174,12 +171,13 @@ static int fifo_enable(const struct motion_sensor_t *accel) st_raw_write8(accel->port, accel->i2c_spi_addr_flags, LSM6DSM_FIFO_CTRL3_ADDR, (decimators[FIFO_DEV_GYRO] << LSM6DSM_FIFO_DEC_G_OFF) | - (decimators[FIFO_DEV_ACCEL] << LSM6DSM_FIFO_DEC_XL_OFF)); + (decimators[FIFO_DEV_ACCEL] + << LSM6DSM_FIFO_DEC_XL_OFF)); if (IS_ENABLED(CONFIG_LSM6DSM_SEC_I2C)) { ASSERT(ARRAY_SIZE(decimators) > FIFO_DEV_MAG); st_raw_write8(accel->port, accel->i2c_spi_addr_flags, - LSM6DSM_FIFO_CTRL4_ADDR, - decimators[FIFO_DEV_MAG]); + LSM6DSM_FIFO_CTRL4_ADDR, + decimators[FIFO_DEV_MAG]); /* * FIFO ODR is limited by odr of gyro or accel. @@ -204,12 +202,12 @@ static int fifo_enable(const struct motion_sensor_t *accel) */ if (max_odr > MAX(odrs[FIFO_DEV_ACCEL], odrs[FIFO_DEV_GYRO])) { st_write_data_with_mask(accel, - LSM6DSM_ODR_REG(accel->type), - LSM6DSM_ODR_MASK, - LSM6DSM_ODR_TO_REG(max_odr)); + LSM6DSM_ODR_REG(accel->type), + LSM6DSM_ODR_MASK, + LSM6DSM_ODR_TO_REG(max_odr)); } else { - st_write_data_with_mask(accel, - LSM6DSM_ODR_REG(accel->type), + st_write_data_with_mask( + accel, LSM6DSM_ODR_REG(accel->type), LSM6DSM_ODR_MASK, LSM6DSM_ODR_TO_REG(odrs[FIFO_DEV_ACCEL])); } @@ -275,8 +273,7 @@ static int fifo_next(struct lsm6dsm_data *private) * push_fifo_data - Scan data pattern and push upside */ static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo, - uint16_t flen, - uint32_t timestamp) + uint16_t flen, uint32_t timestamp) { struct motion_sensor_t *s; struct lsm6dsm_data *private = LSM6DSM_GET_DATA(accel); @@ -310,7 +307,6 @@ static void push_fifo_data(struct motion_sensor_t *accel, uint8_t *fifo, st_normalize(s, axis, fifo); } - if (IS_ENABLED(CONFIG_ACCEL_FIFO)) { struct ec_response_motion_sensor_data vect; @@ -356,8 +352,7 @@ static int load_fifo(struct motion_sensor_t *s, const struct fstatus *fsts) /* Read data and copy in buffer. */ err = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, - LSM6DSM_FIFO_DATA_ADDR, - fifo, length); + LSM6DSM_FIFO_DATA_ADDR, fifo, length); if (err != EC_SUCCESS) return err; @@ -398,17 +393,13 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) (!(*event & CONFIG_ACCEL_LSM6DSM_INT_EVENT))) return EC_ERROR_NOT_HANDLED; - while (!fifo_empty) { /* Read how many data pattern on FIFO to read. */ - RETURN_ERROR(st_raw_read_n_noinc(s->port, - s->i2c_spi_addr_flags, - LSM6DSM_FIFO_STS1_ADDR, - (uint8_t *)&fsts, - sizeof(fsts))); + RETURN_ERROR(st_raw_read_n_noinc( + s->port, s->i2c_spi_addr_flags, LSM6DSM_FIFO_STS1_ADDR, + (uint8_t *)&fsts, sizeof(fsts))); if (fsts.len & (LSM6DSM_FIFO_DATA_OVR | LSM6DSM_FIFO_FULL)) - CPRINTS("%s FIFO Overrun: %04x", - s->name, fsts.len); + CPRINTS("%s FIFO Overrun: %04x", s->name, fsts.len); fifo_empty = fsts.len & LSM6DSM_FIFO_EMPTY; if (!fifo_empty) { commit_needed = true; @@ -420,7 +411,7 @@ static int irq_handler(struct motion_sensor_t *s, uint32_t *event) return EC_SUCCESS; } -#endif /* ACCEL_LSM6DSM_INT_ENABLE */ +#endif /* ACCEL_LSM6DSM_INT_ENABLE */ /** * set_range - set full scale range @@ -520,10 +511,10 @@ int lsm6dsm_set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) * less often. */ if (normalized_rate > 0) - cal->batch_size = MAX( - MAG_CAL_MIN_BATCH_SIZE, - (normalized_rate * 1000) / - MAG_CAL_MIN_BATCH_WINDOW_US); + cal->batch_size = + MAX(MAG_CAL_MIN_BATCH_SIZE, + (normalized_rate * 1000) / + MAG_CAL_MIN_BATCH_WINDOW_US); else cal->batch_size = 0; CPRINTS("Batch size: %d", cal->batch_size); @@ -554,8 +545,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { CPRINTS("%s type:0x%X RS Error", s->name, s->type); return ret; @@ -610,8 +601,8 @@ static int init(struct motion_sensor_t *s) struct stprivate_data *data = s->drv_data; uint8_t ctrl_reg, reg_val = 0; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_WHO_AM_I_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_WHO_AM_I_REG, + &tmp); if (ret != EC_SUCCESS) return EC_ERROR_UNKNOWN; @@ -648,8 +639,8 @@ static int init(struct motion_sensor_t *s) goto err_unlock; /* Power ON Accel. */ - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - ctrl_reg, reg_val); + ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, ctrl_reg, + reg_val); if (ret != EC_SUCCESS) goto err_unlock; @@ -669,12 +660,12 @@ static int init(struct motion_sensor_t *s) /* Power ON Accel. */ ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - ctrl_reg, reg_val); + ctrl_reg, reg_val); if (ret != EC_SUCCESS) goto err_unlock; ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT); + LSM6DSM_CTRL3_ADDR, LSM6DSM_BOOT); if (ret != EC_SUCCESS) goto err_unlock; @@ -686,7 +677,7 @@ static int init(struct motion_sensor_t *s) /* Power OFF Accel. */ ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - ctrl_reg, 0); + ctrl_reg, 0); if (ret != EC_SUCCESS) goto err_unlock; } @@ -695,11 +686,9 @@ static int init(struct motion_sensor_t *s) * Output data not updated until have been read. * Prefer interrupt to be active low. */ - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CTRL3_ADDR, - LSM6DSM_BDU - | LSM6DSM_H_L_ACTIVE - | LSM6DSM_IF_INC); + ret = st_raw_write8( + s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL3_ADDR, + LSM6DSM_BDU | LSM6DSM_H_L_ACTIVE | LSM6DSM_IF_INC); if (ret != EC_SUCCESS) goto err_unlock; -- cgit v1.2.1 From 73ccdbf56f6df2f61b22c9045d587b40c4704c0b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:47 -0600 Subject: util/lbcc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5259adae9512e88aa9e39dc59959f6f1a3156e1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730648 Reviewed-by: Jeremy Bettis --- util/lbcc.c | 82 +++++++++++++++++++++++++++---------------------------------- 1 file changed, 36 insertions(+), 46 deletions(-) diff --git a/util/lbcc.c b/util/lbcc.c index 4a3633153e..7b405c191b 100644 --- a/util/lbcc.c +++ b/util/lbcc.c @@ -31,10 +31,10 @@ static const char usage[] = /* globals */ static int hit_errors; static int opt_verbose; -static int is_jump_target[EC_LB_PROG_LEN]; /* does program jump here? */ -static int is_instruction[EC_LB_PROG_LEN]; /* instruction or operand? */ -static char *label[EC_LB_PROG_LEN]; /* labels we've seen */ -static char *reloc_label[EC_LB_PROG_LEN]; /* put label target here */ +static int is_jump_target[EC_LB_PROG_LEN]; /* does program jump here? */ +static int is_instruction[EC_LB_PROG_LEN]; /* instruction or operand? */ +static char *label[EC_LB_PROG_LEN]; /* labels we've seen */ +static char *reloc_label[EC_LB_PROG_LEN]; /* put label target here */ static void Error(const char *format, ...) { @@ -66,32 +66,21 @@ struct safe_lightbar_program { #define OP(NAME, BYTES, MNEMONIC) NAME, #include "lightbar_opcode_list.h" -enum lightbyte_opcode { - LIGHTBAR_OPCODE_TABLE - MAX_OPCODE -}; +enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE }; #undef OP #define OP(NAME, BYTES, MNEMONIC) BYTES, #include "lightbar_opcode_list.h" -static const int num_operands[] = { - LIGHTBAR_OPCODE_TABLE -}; +static const int num_operands[] = { LIGHTBAR_OPCODE_TABLE }; #undef OP #define OP(NAME, BYTES, MNEMONIC) MNEMONIC, #include "lightbar_opcode_list.h" -static const char * const opcode_sym[] = { - LIGHTBAR_OPCODE_TABLE -}; +static const char *const opcode_sym[] = { LIGHTBAR_OPCODE_TABLE }; #undef OP -static const char * const control_sym[] = { - "beg", "end", "phase", "" -}; -static const char * const color_sym[] = { - "r", "g", "b", "" -}; +static const char *const control_sym[] = { "beg", "end", "phase", "" }; +static const char *const color_sym[] = { "r", "g", "b", "" }; static void read_binary(FILE *fp, struct safe_lightbar_program *prog) { @@ -232,7 +221,8 @@ static void set_jump_target(uint8_t targ) { if (targ >= EC_LB_PROG_LEN) { Warning("program jumps to 0x%02x, " - "which out of bounds\n", targ); + "which out of bounds\n", + targ); return; } is_jump_target[targ] = 1; @@ -266,7 +256,8 @@ static void disassemble_prog(FILE *fp, struct safe_lightbar_program *prog) for (i = 0; i < EC_LB_PROG_LEN; i++) if (is_jump_target[i] && !is_instruction[i]) { Warning("program jumps to 0x%02x, " - "which is not a valid instruction\n", i); + "which is not a valid instruction\n", + i); } } @@ -295,7 +286,6 @@ static int split_line(char *buf, const char *delim, struct parse_s *elt, elt[i].val = (uint32_t)strtoull(w, &e, 0); if (!e || !*e) elt[i].is_num = 1; - } return i; @@ -377,7 +367,6 @@ static int is_color_arg(char *buf, int expected, uint32_t *valp) } else color = 0; - *valp = ((led & 0xF) << 4) | ((control & 0x3) << 2) | (color & 0x3); return 1; } @@ -390,8 +379,8 @@ static void fixup_symbols(struct safe_lightbar_program *prog) if (reloc_label[i]) { /* Looking for reloc label */ for (j = 0; j < EC_LB_PROG_LEN; j++) { - if (label[j] && !strcmp(label[j], - reloc_label[i])) { + if (label[j] && + !strcmp(label[j], reloc_label[i])) { prog->p.data[i] = j; break; } @@ -402,7 +391,6 @@ static void fixup_symbols(struct safe_lightbar_program *prog) } } - static void compile(FILE *fp, struct safe_lightbar_program *prog) { char buf[128]; @@ -415,7 +403,6 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) int i; while (fgets(buf, sizeof(buf), fp)) { - /* We truncate lines that are too long */ s = strchr(buf, '\n'); if (chopping) { @@ -458,7 +445,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) if (opcode >= MAX_OPCODE) { Error("Unrecognized opcode \"%s\"" - " at line %d\n", token[wnum].word, line); + " at line %d\n", + token[wnum].word, line); continue; } @@ -488,7 +476,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) reloc_label[addr++] = strdup(token[wnum].word); else { Error("Missing first jump target " - "at line %d\n", line); + "at line %d\n", + line); break; } wnum++; @@ -496,7 +485,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) reloc_label[addr++] = strdup(token[wnum].word); else Error("Missing second jump target " - "at line %d\n", line); + "at line %d\n", + line); break; case SET_BRIGHTNESS: @@ -511,14 +501,13 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) case SET_RAMP_DELAY: /* one 32-bit arg */ if (token[wnum].is_num) { - prog->p.data[addr++] = - (token[wnum].val >> 24) & 0xff; - prog->p.data[addr++] = - (token[wnum].val >> 16) & 0xff; - prog->p.data[addr++] = - (token[wnum].val >> 8) & 0xff; - prog->p.data[addr++] = - token[wnum].val & 0xff; + prog->p.data[addr++] = (token[wnum].val >> 24) & + 0xff; + prog->p.data[addr++] = (token[wnum].val >> 16) & + 0xff; + prog->p.data[addr++] = (token[wnum].val >> 8) & + 0xff; + prog->p.data[addr++] = token[wnum].val & 0xff; } else { Error("Missing/invalid arg at line %d\n", line); } @@ -535,11 +524,11 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) prog->p.data[addr++] = token[wnum++].val; /* and the color immediate */ if (token[wnum].is_num) { - prog->p.data[addr++] = - token[wnum++].val; + prog->p.data[addr++] = token[wnum++].val; } else { Error("Missing/Invalid arg " - "at line %d\n", line); + "at line %d\n", + line); break; } break; @@ -559,7 +548,8 @@ static void compile(FILE *fp, struct safe_lightbar_program *prog) token[wnum++].val; } else { Error("Missing/Invalid arg " - "at line %d\n", line); + "at line %d\n", + line); break; } } @@ -604,7 +594,7 @@ int main(int argc, char *argv[]) else progname = argv[0]; - opterr = 0; /* quiet, you */ + opterr = 0; /* quiet, you */ while ((c = getopt(argc, argv, ":dv")) != -1) { switch (c) { case 'd': @@ -676,8 +666,8 @@ int main(int argc, char *argv[]) compile(ifp, &safe_prog); fclose(ifp); if (!hit_errors) { - if (1 != fwrite(safe_prog.p.data, - safe_prog.p.size, 1, ofp)) + if (1 != + fwrite(safe_prog.p.data, safe_prog.p.size, 1, ofp)) Error("%s: Unable to write to %s: %s\n", progname, outfile, strerror(errno)); else -- cgit v1.2.1 From 0bff45b4f396569f3d9172854f590fec3cbd611c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:41 -0600 Subject: board/lick/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0971f9a2147fe1b6509fe0c20b9fd1fe00711797 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728622 Reviewed-by: Jeremy Bettis --- board/lick/board.c | 71 ++++++++++++++++++++++++++---------------------------- 1 file changed, 34 insertions(+), 37 deletions(-) diff --git a/board/lick/board.c b/board/lick/board.c index 678634f785..0714e54cbc 100644 --- a/board/lick/board.c +++ b/board/lick/board.c @@ -31,11 +31,11 @@ #include "util.h" #include "battery_smart.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX7447 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX7447 0 +#define USB_PD_PORT_PS8751 1 static uint8_t sku_id; @@ -60,31 +60,31 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, /* Vbus sensing (1/10 voltage divider). */ - [ADC_VBUS_C0] = { - "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, - [ADC_VBUS_C1] = { - "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS_C0] = { "VBUS_C0", NPCX_ADC_CH9, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, + [ADC_VBUS_C1] = { "VBUS_C1", NPCX_ADC_CH4, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -94,11 +94,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate lid and base sensor into standard reference frame */ -const mat33_fp_t standard_rot_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t standard_rot_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct stprivate_data g_lis2dh_data; @@ -192,11 +190,10 @@ static int board_is_convertible(void) static void board_update_sensor_config_from_sku(void) { - motion_sensor_count = 0; - gmr_tablet_switch_disable(); - /* Base accel is not stuffed, don't allow line to float */ - gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + /* Base accel is not stuffed, don't allow line to float */ + gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, GPIO_INPUT | GPIO_PULL_DOWN); } static void cbi_init(void) @@ -232,11 +229,11 @@ int board_is_lid_angle_tablet_mode(void) } /* Battery functions */ -#define SB_OPTIONALMFG_FUNCTION2 0x3e +#define SB_OPTIONALMFG_FUNCTION2 0x3e /* Optional mfg function2 */ -#define SMART_QUICK_CHARGE (1<<12) +#define SMART_QUICK_CHARGE (1 << 12) /* Quick charge support */ -#define MODE_QUICK_CHARGE_SUPPORT (1<<4) +#define MODE_QUICK_CHARGE_SUPPORT (1 << 4) static void sb_quick_charge_mode(int enable) { -- cgit v1.2.1 From 83535c46a48dc1a13a0ecf3a81e2f9203f7de0fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:46 -0600 Subject: chip/host/reboot.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia358c8193b088bf8fe3898bd636b49478b686548 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729152 Reviewed-by: Jeremy Bettis --- chip/host/reboot.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/chip/host/reboot.h b/chip/host/reboot.h index 1c1201f451..485e0b167b 100644 --- a/chip/host/reboot.h +++ b/chip/host/reboot.h @@ -13,6 +13,7 @@ #ifndef TEST_FUZZ noreturn #endif -void emulator_reboot(void); + void + emulator_reboot(void); #endif -- cgit v1.2.1 From 16f0f90edc3cee01dbb185909c784b2758a155f1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:42 -0600 Subject: board/kano/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieab98b5e7b4bfc9e9bb2cae1dd4929a106df4b77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728480 Reviewed-by: Jeremy Bettis --- board/kano/charger.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/kano/charger.c b/board/kano/charger.c index 9f7c760858..fbfb3ae90a 100644 --- a/board/kano/charger.c +++ b/board/kano/charger.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 71b6852fa084e76277997a4a01c155bdc352bd7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:43 -0600 Subject: baseboard/zork/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a756034de04fc3f98c039c85a271d1af2e930a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727959 Reviewed-by: Jeremy Bettis --- baseboard/zork/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c index 8dcdfa7635..89418103ba 100644 --- a/baseboard/zork/usb_pd_policy.c +++ b/baseboard/zork/usb_pd_policy.c @@ -18,8 +18,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 7d589eae41124c4e7608e42d1cc3c2eac5878cf3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:36 -0600 Subject: board/beetley/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I882264deced3820efd3755b23710de21371e5c73 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728050 Reviewed-by: Jeremy Bettis --- board/beetley/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/beetley/usb_pd_policy.c b/board/beetley/usb_pd_policy.c index b7c0ca21df..814287a417 100644 --- a/board/beetley/usb_pd_policy.c +++ b/board/beetley/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From facec2f3436cc1d3f9c9c378bf8090394b68b316 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:57 -0600 Subject: chip/mec1322/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1247424515f00a293544c2a3721cb60799f168a6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729329 Reviewed-by: Jeremy Bettis --- chip/mec1322/hwtimer.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c index b0405ec321..83390d6f6a 100644 --- a/chip/mec1322/hwtimer.c +++ b/chip/mec1322/hwtimer.c @@ -15,8 +15,7 @@ void __hw_clock_event_set(uint32_t deadline) { - MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - - (0xffffffff - deadline); + MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline); MEC1322_TMR32_CTL(1) |= BIT(5); } @@ -50,9 +49,15 @@ static void __hw_clock_source_irq(int timer_id) process_timers(timer_id == 0); } -static void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); } +static void __hw_clock_source_irq_0(void) +{ + __hw_clock_source_irq(0); +} DECLARE_IRQ(MEC1322_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1); -static void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); } +static void __hw_clock_source_irq_1(void) +{ + __hw_clock_source_irq(1); +} DECLARE_IRQ(MEC1322_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1); static void configure_timer(int timer_id) -- cgit v1.2.1 From 8b4fa4b2483fad749a5919d59baa2a12bd594229 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:21 -0600 Subject: board/katsu/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib705dcc8fd93444592b83cba96b0ca102e5f2ae0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728526 Reviewed-by: Jeremy Bettis --- board/katsu/board.h | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/board/katsu/board.h b/board/katsu/board.h index afb5cf28e0..e4494630c9 100644 --- a/board/katsu/board.h +++ b/board/katsu/board.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_BOARD_H #define __CROS_EC_BOARD_H -#define BQ27541_ADDR 0x55 +#define BQ27541_ADDR 0x55 #define VARIANT_KUKUI_BATTERY_BQ27541 #define VARIANT_KUKUI_POGO_KEYBOARD @@ -27,11 +27,10 @@ #define CONFIG_USB_MUX_RUNTIME_CONFIG /* Battery */ -#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ +#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ #define CONFIG_CHARGER_MT6370_BACKLIGHT - /* Motion Sensors */ #ifdef SECTION_IS_RW #define CONFIG_ACCELGYRO_ICM426XX @@ -41,18 +40,17 @@ /* Camera VSYNC */ #define CONFIG_SYNC #define CONFIG_SYNC_COMMAND -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #endif /* SECTION_IS_RW */ /* I2C ports */ -#define I2C_PORT_CHARGER 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 1 +#define I2C_PORT_CHARGER 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 1 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_ACCEL 1 -#define I2C_PORT_BC12 1 +#define I2C_PORT_ACCEL 1 +#define I2C_PORT_BC12 1 /* Route sbs host requests to virtual battery driver */ #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B @@ -63,12 +61,12 @@ #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ (BIT(EC_MKBP_EVENT_SENSOR_FIFO) | BIT(EC_MKBP_EVENT_HOST_EVENT)) #undef CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define PD_OPERATING_POWER_MW 15000 -- cgit v1.2.1 From 8c38ad8065914309796d91d034cef7d81ae30997 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:36 -0600 Subject: common/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib43e66199979cee7d367b56acf29055c4117ba9a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729627 Reviewed-by: Jeremy Bettis --- common/espi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/common/espi.c b/common/espi.c index 0a747d3bda..d4324c1b31 100644 --- a/common/espi.c +++ b/common/espi.c @@ -12,7 +12,6 @@ #include "timer.h" #include "util.h" - const char *espi_vw_names[] = { "VW_SLP_S3_L", "VW_SLP_S4_L", @@ -41,7 +40,6 @@ const char *espi_vw_names[] = { }; BUILD_ASSERT(ARRAY_SIZE(espi_vw_names) == VW_SIGNAL_COUNT); - const char *espi_vw_get_wire_name(enum espi_vw_signal signal) { if (espi_signal_is_vw(signal)) @@ -50,7 +48,6 @@ const char *espi_vw_get_wire_name(enum espi_vw_signal signal) return NULL; } - int espi_signal_is_vw(int signal) { return ((signal >= VW_SIGNAL_START) && (signal < VW_SIGNAL_END)); -- cgit v1.2.1 From 71080a8a0ccba737b5ab4301821300fde83ed9ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:02 -0600 Subject: board/kukui_scp/isp_p2_srv.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icbb0de95bd74f66589dde50e51a42a4d5e6d7d56 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728595 Reviewed-by: Jeremy Bettis --- board/kukui_scp/isp_p2_srv.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/board/kukui_scp/isp_p2_srv.c b/board/kukui_scp/isp_p2_srv.c index dba330c6a8..a21cd585b5 100644 --- a/board/kukui_scp/isp_p2_srv.c +++ b/board/kukui_scp/isp_p2_srv.c @@ -19,19 +19,21 @@ static struct consumer const event_dip_consumer; static void event_dip_written(struct consumer const *consumer, size_t count); -static struct queue const event_dip_queue = QUEUE_DIRECT(4, - struct dip_msg_service, null_producer, event_dip_consumer); +static struct queue const event_dip_queue = QUEUE_DIRECT( + 4, struct dip_msg_service, null_producer, event_dip_consumer); static struct consumer const event_dip_consumer = { .queue = &event_dip_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_dip_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT8183 -void dip_msg_handler(void *data) {} +void dip_msg_handler(void *data) +{ +} #endif static void event_dip_written(struct consumer const *consumer, size_t count) -- cgit v1.2.1 From eeeaa9d70c495040c0f86e4894bfd5cb99707685 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:55 -0600 Subject: zephyr/shim/include/usbc/tusb1064_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e4ac0aa5240cc6b5c3823ca91584faedf1e2236 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730853 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tusb1064_usb_mux.h | 46 ++++++++++++++--------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/zephyr/shim/include/usbc/tusb1064_usb_mux.h b/zephyr/shim/include/usbc/tusb1064_usb_mux.h index 159f42c500..17f0ff7d21 100644 --- a/zephyr/shim/include/usbc/tusb1064_usb_mux.h +++ b/zephyr/shim/include/usbc/tusb1064_usb_mux.h @@ -8,35 +8,35 @@ #include "driver/usb_mux/tusb1064.h" -#define TUSB1064_USB_MUX_COMPAT ti_tusb1064 +#define TUSB1064_USB_MUX_COMPAT ti_tusb1064 #if defined(CONFIG_USB_MUX_TUSB1044) -#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &tusb1064_usb_mux_driver, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = \ - DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ - .hpd_update = &tusb1044_hpd_update, \ +#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &tusb1064_usb_mux_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ + .hpd_update = &tusb1044_hpd_update, \ } #elif defined(CONFIG_USB_MUX_TUSB546) -#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &tusb1064_usb_mux_driver, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = \ - DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &tusb1064_usb_mux_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ } #else -#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &tusb1064_usb_mux_driver, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = \ - DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_TUSB1064(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &tusb1064_usb_mux_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ } #endif /* defined(CONFIG_USB_MUX_TUSB1044) */ -- cgit v1.2.1 From 28064b54d556f3580f94a42ce61d7932264dd762 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:18 -0600 Subject: board/sasuke/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e97e864294be0ca553ce97a4d15312df65c0a21 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728908 Reviewed-by: Jeremy Bettis --- board/sasuke/led.c | 88 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 46 insertions(+), 42 deletions(-) diff --git a/board/sasuke/led.c b/board/sasuke/led.c index 37cbad75e5..6f84ce5edd 100644 --- a/board/sasuke/led.c +++ b/board/sasuke/led.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Power and battery LED control for sasuke + * Power and battery LED control for sasuke */ #include "chipset.h" @@ -12,8 +12,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 1; @@ -21,33 +21,36 @@ __override const int led_charge_lvl_2 = 100; /* sasuke : There are 3 leds for AC, Battery and Power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 0.5 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, + 0.5 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -55,14 +58,13 @@ __override void led_set_color_power(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; - } + } - if (color == EC_LED_COLOR_BLUE) - { - gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); + if (color == EC_LED_COLOR_BLUE) { + gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); + gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_ON_LVL); } else { /* LED_OFF and unsupported colors */ @@ -74,17 +76,16 @@ __override void led_set_color_battery(enum ec_led_colors color) { /* Don't set led if led_auto_control is disabled. */ if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED) || - !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + !led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { return; - } + } /* Battery leds must be turn off when blue led is on * because casta has 3-in-1 led. */ - if(!gpio_get_level(GPIO_PWR_LED_BLUE_L)) - { + if (!gpio_get_level(GPIO_PWR_LED_BLUE_L)) { gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); /*red*/ - gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/ + gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); /*green*/ return; } @@ -118,10 +119,13 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { if (led_id == EC_LED_ID_BATTERY_LED) { gpio_set_level(GPIO_PWR_LED_BLUE_L, LED_OFF_LVL); - gpio_set_level(GPIO_BAT_LED_GREEN_L, !brightness[EC_LED_COLOR_GREEN]); - gpio_set_level(GPIO_BAT_LED_RED_L, !brightness[EC_LED_COLOR_RED]); + gpio_set_level(GPIO_BAT_LED_GREEN_L, + !brightness[EC_LED_COLOR_GREEN]); + gpio_set_level(GPIO_BAT_LED_RED_L, + !brightness[EC_LED_COLOR_RED]); } else if (led_id == EC_LED_ID_POWER_LED) { - gpio_set_level(GPIO_PWR_LED_BLUE_L, !brightness[EC_LED_COLOR_BLUE]); + gpio_set_level(GPIO_PWR_LED_BLUE_L, + !brightness[EC_LED_COLOR_BLUE]); gpio_set_level(GPIO_BAT_LED_GREEN_L, LED_OFF_LVL); gpio_set_level(GPIO_BAT_LED_RED_L, LED_OFF_LVL); } -- cgit v1.2.1 From 1259479b7f1b79cf0058a8766033d4f5883241b1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:01 -0600 Subject: include/ec_ec_comm_client.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a06ea89c93761f646c97b0c0363b5d88a8a4ec9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730261 Reviewed-by: Jeremy Bettis --- include/ec_ec_comm_client.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/ec_ec_comm_client.h b/include/ec_ec_comm_client.h index 9a60daffe4..3dea3112dd 100644 --- a/include/ec_ec_comm_client.h +++ b/include/ec_ec_comm_client.h @@ -42,8 +42,7 @@ int ec_ec_client_base_get_static_info(void); * @return EC_RES_SUCCESS on success, EC_RES_ERROR on communication error, * else forwards the error code from the server. */ -int ec_ec_client_base_charge_control(int max_current, - int otg_voltage, +int ec_ec_client_base_charge_control(int max_current, int otg_voltage, int allow_charging); /** -- cgit v1.2.1 From 4e986ac1e776b06fd64e1832af1e8a8b92887b75 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:44 -0600 Subject: board/galtic/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib6e10b96e31a5f2f33d1e66cbda9cd984b7a66e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728384 Reviewed-by: Jeremy Bettis --- board/galtic/board.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/board/galtic/board.h b/board/galtic/board.h index 50f9fdca9c..0d482844a3 100644 --- a/board/galtic/board.h +++ b/board/galtic/board.h @@ -22,12 +22,13 @@ #define CONFIG_BC12_DETECT_PI3USB9201 /* Charger */ -#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -35,19 +36,19 @@ /* LED */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_BMI_COMM_I2C -#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */ +#define CONFIG_ACCELGYRO_ICM426XX /* Base accel */ #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_ICM_COMM_I2C @@ -86,11 +87,11 @@ #define CONFIG_THROTTLE_AP /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define CONFIG_USB_MUX_PS8743 /* C1: PS8743 Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define CONFIG_USB_MUX_PS8743 /* C1: PS8743 Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ -#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ #define CONFIG_USB_MUX_RUNTIME_CONFIG #define CONFIG_USB_MUX_VIRTUAL @@ -116,19 +117,14 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 4483025bf6388d420076f4f601477f0cd932a54e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:08 -0600 Subject: board/ambassador/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I604cda2501bcb90fe32653c5ac94efac9aaab398 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727982 Reviewed-by: Jeremy Bettis --- board/ambassador/usb_pd_policy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/ambassador/usb_pd_policy.c b/board/ambassador/usb_pd_policy.c index 5bc754453a..a89fd35074 100644 --- a/board/ambassador/usb_pd_policy.c +++ b/board/ambassador/usb_pd_policy.c @@ -19,9 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From a00313c1078677d6fccbdb865cea326db80b2a29 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:38 -0600 Subject: chip/ish/hid_subsys.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic928a65dd8cb3df0ff5fc44722eedc0997b68d07 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729179 Reviewed-by: Jeremy Bettis --- chip/ish/hid_subsys.c | 56 ++++++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/chip/ish/hid_subsys.c b/chip/ish/hid_subsys.c index bd3f331fdc..7f4c780f1f 100644 --- a/chip/ish/hid_subsys.c +++ b/chip/ish/hid_subsys.c @@ -11,8 +11,8 @@ #ifdef HID_SUBSYS_DEBUG #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) #else #define CPUTS(outstr) #define CPRINTS(format, args...) @@ -21,10 +21,15 @@ #define __packed __attribute__((packed)) -#define HECI_CLIENT_HID_GUID { 0x33AECD58, 0xB679, 0x4E54,\ - { 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 } } +#define HECI_CLIENT_HID_GUID \ + { \ + 0x33AECD58, 0xB679, 0x4E54, \ + { \ + 0x9B, 0xD9, 0xA0, 0x4D, 0x34, 0xF0, 0xC2, 0x26 \ + } \ + } -#define HID_SUBSYS_MAX_HID_DEVICES 3 +#define HID_SUBSYS_MAX_HID_DEVICES 3 /* * the following enum values and data structures with __packed are used for @@ -55,13 +60,13 @@ struct hid_device_info { uint16_t vid; } __packed; -struct hid_enum_payload { +struct hid_enum_payload { uint8_t num_of_hid_devices; struct hid_device_info dev_info[0]; } __packed; -#define COMMAND_MASK 0x7F -#define RESPONSE_FLAG 0x80 +#define COMMAND_MASK 0x7F +#define RESPONSE_FLAG 0x80 struct hid_msg_hdr { uint8_t command; /* bit 7 is used to indicate "response" */ uint8_t device_id; @@ -94,8 +99,8 @@ static struct hid_subsystem hid_subsys_ctx = { .heci_handle = HECI_INVALID_HANDLE, }; -#define handle_to_dev_id(_handle) ((uintptr_t)(_handle)) -#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id)) +#define handle_to_dev_id(_handle) ((uintptr_t)(_handle)) +#define dev_id_to_handle(_dev_id) ((hid_handle_t)(uintptr_t)(_dev_id)) static inline hid_handle_t device_index_to_handle(int device_index) { @@ -108,8 +113,8 @@ static inline int is_valid_handle(hid_handle_t handle) (uintptr_t)handle <= hid_subsys_ctx.num_of_hid_devices; } -static inline -struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle) +static inline struct hid_subsys_hid_device * +handle_to_hid_device(hid_handle_t handle) { if (!is_valid_handle(handle)) return NULL; @@ -117,7 +122,6 @@ struct hid_subsys_hid_device *handle_to_hid_device(hid_handle_t handle) return &hid_subsys_ctx.hid_devices[(uintptr_t)handle - 1]; } - hid_handle_t hid_subsys_register_device(const struct hid_device *dev_info) { struct hid_subsys_hid_device *hid_device; @@ -156,7 +160,7 @@ int hid_subsys_send_input_report(const hid_handle_t handle, uint8_t *buf, const size_t buf_size) { struct hid_subsys_hid_device *hid_device; - struct hid_msg_hdr hid_msg_hdr = {0}; + struct hid_msg_hdr hid_msg_hdr = { 0 }; struct heci_msg_item msg_item[2]; struct heci_msg_list msg_list; @@ -253,7 +257,7 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) * re-use hid_msg from host for reply. */ switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_GET_HID_DESCRIPTOR: + case HID_GET_HID_DESCRIPTOR: if (cbs->get_hid_descriptor) ret = cbs->get_hid_descriptor(handle, payload, buf_size); @@ -277,10 +281,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) case HID_SET_FEATURE_REPORT: if (cbs->set_feature_report) { - ret = cbs->set_feature_report(handle, - payload[0], - payload, - payload_size); + ret = cbs->set_feature_report(handle, payload[0], + payload, payload_size); /* * if no error, reply only with the report id. * re-use the first byte of payload @@ -293,8 +295,8 @@ static int handle_hid_device_msg(struct hid_msg *hid_msg) break; case HID_GET_INPUT_REPORT: if (cbs->get_input_report) - ret = cbs->get_input_report(handle, payload[0], - payload, buf_size); + ret = cbs->get_input_report(handle, payload[0], payload, + buf_size); break; @@ -331,21 +333,21 @@ static int handle_hid_subsys_msg(struct hid_msg *hid_msg) struct hid_enum_payload *enum_payload; switch (hid_msg->hdr.command & COMMAND_MASK) { - case HID_DM_ENUM_DEVICES: + case HID_DM_ENUM_DEVICES: enum_payload = (struct hid_enum_payload *)hid_msg->payload; for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { enum_payload->dev_info[i] = - hid_subsys_ctx.hid_devices[i].info; + hid_subsys_ctx.hid_devices[i].info; } enum_payload->num_of_hid_devices = - hid_subsys_ctx.num_of_hid_devices; + hid_subsys_ctx.num_of_hid_devices; /* reply payload size */ size = sizeof(enum_payload->num_of_hid_devices); size += enum_payload->num_of_hid_devices * - sizeof(enum_payload->dev_info[0]); + sizeof(enum_payload->dev_info[0]); break; @@ -408,7 +410,7 @@ static int hid_subsys_resume(const heci_handle_t heci_handle) for (i = 0; i < hid_subsys_ctx.num_of_hid_devices; i++) { if (hid_subsys_ctx.hid_devices[i].cbs->resume) ret |= hid_subsys_ctx.hid_devices[i].cbs->resume( - device_index_to_handle(i)); + device_index_to_handle(i)); } return ret; @@ -422,7 +424,7 @@ static int hid_subsys_suspend(const heci_handle_t heci_handle) for (i = hid_subsys_ctx.num_of_hid_devices - 1; i >= 0; i--) { if (hid_subsys_ctx.hid_devices[i].cbs->suspend) ret |= hid_subsys_ctx.hid_devices[i].cbs->suspend( - device_index_to_handle(i)); + device_index_to_handle(i)); } return ret; -- cgit v1.2.1 From 4dadad958779ea4b361980bb5e6491960e3150f5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:21 -0600 Subject: board/magolor/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87a03c7bc3de28c4fc290153639108065a69348a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728651 Reviewed-by: Jeremy Bettis --- board/magolor/cbi_ssfc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/magolor/cbi_ssfc.c b/board/magolor/cbi_ssfc.c index 7708bb9905..23791e4ee0 100644 --- a/board/magolor/cbi_ssfc.c +++ b/board/magolor/cbi_ssfc.c @@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } enum ec_ssfc_usb_mux get_cbi_ssfc_usb_mux(void) { - return (enum ec_ssfc_usb_mux) cached_ssfc.usb_mux; + return (enum ec_ssfc_usb_mux)cached_ssfc.usb_mux; } -- cgit v1.2.1 From 5bcf22d207d4a199ac727ebff73da39c99f8408f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:45 -0600 Subject: chip/mt_scp/rv32i_common/hostcmd.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I280a6a433378a8430f7f1282e46e43dfdb1dfa41 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729369 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/hostcmd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/chip/mt_scp/rv32i_common/hostcmd.c b/chip/mt_scp/rv32i_common/hostcmd.c index 42a463ee56..3bbdf6b97c 100644 --- a/chip/mt_scp/rv32i_common/hostcmd.c +++ b/chip/mt_scp/rv32i_common/hostcmd.c @@ -97,7 +97,8 @@ DECLARE_IPI(SCP_IPI_HOST_COMMAND, hostcmd_handler, 0); /* * Get protocol information */ -static enum ec_status hostcmd_get_protocol_info(struct host_cmd_handler_args *args) +static enum ec_status +hostcmd_get_protocol_info(struct host_cmd_handler_args *args) { struct ec_response_get_protocol_info *r = args->response; -- cgit v1.2.1 From 09d3bad856ebc592527a0b691c17844012ef2b95 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:46:00 -0600 Subject: board/mchpevb1/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieaa0adc98eb2a922e320884727ac395d4da78bfd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728657 Reviewed-by: Jeremy Bettis --- board/mchpevb1/led.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/board/mchpevb1/led.c b/board/mchpevb1/led.c index 7b9f7646cb..51b8fd1f0f 100644 --- a/board/mchpevb1/led.c +++ b/board/mchpevb1/led.c @@ -30,8 +30,7 @@ * NOTE: GPIO_BAT_LED_xxx defined in board.h */ -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -40,7 +39,7 @@ enum led_color { LED_RED, LED_AMBER, LED_GREEN, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int bat_led_set_color(enum led_color color) @@ -68,8 +67,7 @@ static int bat_led_set_color(enum led_color color) return EC_SUCCESS; } -void led_get_brightness_range(enum ec_led_id led_id, - uint8_t *brightness_range) +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { brightness_range[EC_LED_COLOR_RED] = 1; brightness_range[EC_LED_COLOR_GREEN] = 1; @@ -129,23 +127,29 @@ static void board_led_set_battery(void) case PWR_STATE_DISCHARGE: /* Less than 3%, blink one second every two second */ if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) && - charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE) + charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE) board_led_set_color_battery( (battery_ticks % LED_TOTAL_2SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + LED_ON_1SEC_TICKS) ? + LED_AMBER : + LED_OFF); /* Less than 10%, blink one second every four seconds */ else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) && - charge_get_percent() < LOW_BATTERY_PERCENTAGE) + charge_get_percent() < LOW_BATTERY_PERCENTAGE) board_led_set_color_battery( (battery_ticks % LED_TOTAL_4SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + LED_ON_1SEC_TICKS) ? + LED_AMBER : + LED_OFF); else board_led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: board_led_set_color_battery( (battery_ticks % LED_TOTAL_2SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_RED : LED_OFF); + LED_ON_1SEC_TICKS) ? + LED_RED : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: board_led_set_color_battery(LED_GREEN); @@ -154,7 +158,9 @@ static void board_led_set_battery(void) if (chflags & CHARGE_FLAG_FORCE_IDLE) board_led_set_color_battery( (battery_ticks % LED_TOTAL_4SECS_TICKS < - LED_ON_2SECS_TICKS) ? LED_GREEN : LED_AMBER); + LED_ON_2SECS_TICKS) ? + LED_GREEN : + LED_AMBER); else board_led_set_color_battery(LED_GREEN); break; @@ -165,7 +171,6 @@ static void board_led_set_battery(void) #endif } - static void led_second(void) { if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) -- cgit v1.2.1 From 6b97198215d2455aa036b96d3d33e812d14d1698 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:44 -0600 Subject: driver/retimer/ps8811.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9fa9bf79fb69e099b0475b30b14ef2b6019dd739 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730068 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8811.h | 300 ++++++++++++++++++++++++------------------------ 1 file changed, 150 insertions(+), 150 deletions(-) diff --git a/driver/retimer/ps8811.h b/driver/retimer/ps8811.h index 5721f31eae..d802d82d03 100644 --- a/driver/retimer/ps8811.h +++ b/driver/retimer/ps8811.h @@ -20,172 +20,172 @@ * PS8811 uses 7-bit I2C addresses 0x72 to 0x73 (ADDR=HH). * Page 0 = 0x72, Page 1 = 0x73. */ -#define PS8811_I2C_ADDR_FLAGS0 0x28 -#define PS8811_I2C_ADDR_FLAGS1 0x2A -#define PS8811_I2C_ADDR_FLAGS2 0x70 -#define PS8811_I2C_ADDR_FLAGS3 0x72 +#define PS8811_I2C_ADDR_FLAGS0 0x28 +#define PS8811_I2C_ADDR_FLAGS1 0x2A +#define PS8811_I2C_ADDR_FLAGS2 0x70 +#define PS8811_I2C_ADDR_FLAGS3 0x72 /* * PAGE 1 Register Definitions */ -#define PS8811_REG_PAGE1 0x01 - -#define PS8811_REG1_USB_AEQ_LEVEL 0x01 -#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) -#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0 -#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00 -#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01 -#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02 -#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03 -#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04 -#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05 -#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06 -#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07 -#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08 -#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09 -#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A -#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) -#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4 -#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00 -#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01 -#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02 -#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03 -#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04 -#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05 -#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06 -#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07 -#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08 -#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09 -#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A - -#define PS8811_REG1_USB_ADE_CONFIG 0x02 -#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0) -#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1) -#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) -#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5 -#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00 -#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07 -#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) -#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2 -#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00 -#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01 -#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02 -#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03 -#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04 -#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05 -#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06 -#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_BEQ_LEVEL 0x05 -#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) -#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0 -#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00 -#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01 -#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02 -#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03 -#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04 -#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05 -#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06 -#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07 -#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08 -#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09 -#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A -#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) -#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4 -#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00 -#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01 -#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02 -#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03 -#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04 -#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05 -#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06 -#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07 -#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08 -#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09 -#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A - -#define PS8811_REG1_USB_BDE_CONFIG 0x06 -#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0) -#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1) -#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) -#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5 -#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00 -#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 -#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) -#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2 -#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00 -#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_CHAN_A_SWING 0x66 -#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4) -#define PS8811_CHAN_A_SWING_SHIFT 4 - -#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73 -#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1) -#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1 -#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02 -#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05 -#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06 - -#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 -#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 -#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 -#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 -#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 -#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 -#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 - -#define PS8811_REG1_USB_CHAN_B_SWING 0xA4 -#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0) -#define PS8811_CHAN_B_SWING_SHIFT 0 +#define PS8811_REG_PAGE1 0x01 + +#define PS8811_REG1_USB_AEQ_LEVEL 0x01 +#define PS8811_AEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) +#define PS8811_AEQ_PIN_LEVEL_UP_SHIFT 0 +#define PS8811_AEQ_PIN_LEVEL_UP_9DB 0x00 +#define PS8811_AEQ_PIN_LEVEL_UP_10P5DB 0x01 +#define PS8811_AEQ_PIN_LEVEL_UP_12DB 0x02 +#define PS8811_AEQ_PIN_LEVEL_UP_13DB 0x03 +#define PS8811_AEQ_PIN_LEVEL_UP_16DB 0x04 +#define PS8811_AEQ_PIN_LEVEL_UP_17DB 0x05 +#define PS8811_AEQ_PIN_LEVEL_UP_18DB 0x06 +#define PS8811_AEQ_PIN_LEVEL_UP_19DB 0x07 +#define PS8811_AEQ_PIN_LEVEL_UP_20DB 0x08 +#define PS8811_AEQ_PIN_LEVEL_UP_21DB 0x09 +#define PS8811_AEQ_PIN_LEVEL_UP_23DB 0x0A +#define PS8811_AEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) +#define PS8811_AEQ_I2C_LEVEL_UP_SHIFT 4 +#define PS8811_AEQ_I2C_LEVEL_UP_9DB 0x00 +#define PS8811_AEQ_I2C_LEVEL_UP_10P5DB 0x01 +#define PS8811_AEQ_I2C_LEVEL_UP_12DB 0x02 +#define PS8811_AEQ_I2C_LEVEL_UP_13DB 0x03 +#define PS8811_AEQ_I2C_LEVEL_UP_16DB 0x04 +#define PS8811_AEQ_I2C_LEVEL_UP_17DB 0x05 +#define PS8811_AEQ_I2C_LEVEL_UP_18DB 0x06 +#define PS8811_AEQ_I2C_LEVEL_UP_19DB 0x07 +#define PS8811_AEQ_I2C_LEVEL_UP_20DB 0x08 +#define PS8811_AEQ_I2C_LEVEL_UP_21DB 0x09 +#define PS8811_AEQ_I2C_LEVEL_UP_23DB 0x0A + +#define PS8811_REG1_USB_ADE_CONFIG 0x02 +#define PS8811_AEQ_CONFIG_REG_ENABLE BIT(0) +#define PS8811_AEQ_ADAPTIVE_REG_ENABLE BIT(1) +#define PS8811_ADE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) +#define PS8811_ADE_PIN_MID_LEVEL_SHIFT 5 +#define PS8811_ADE_PIN_MID_LEVEL_0P5DB 0x00 +#define PS8811_ADE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_ADE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_ADE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_ADE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_ADE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_ADE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_ADE_PIN_MID_LEVEL_7P5DB 0x07 +#define PS8811_ADE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) +#define PS8811_ADE_PIN_LOW_LEVEL_SHIFT 2 +#define PS8811_ADE_PIN_LOW_LEVEL_0P5DB 0x00 +#define PS8811_ADE_PIN_LOW_LEVEL_1P5DB 0x01 +#define PS8811_ADE_PIN_LOW_LEVEL_2DB 0x02 +#define PS8811_ADE_PIN_LOW_LEVEL_3DB 0x03 +#define PS8811_ADE_PIN_LOW_LEVEL_3P5DB 0x04 +#define PS8811_ADE_PIN_LOW_LEVEL_4P5DB 0x05 +#define PS8811_ADE_PIN_LOW_LEVEL_6DB 0x06 +#define PS8811_ADE_PIN_LOW_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_BEQ_LEVEL 0x05 +#define PS8811_BEQ_PIN_LEVEL_UP_CONFIG_MASK GENMASK(3, 0) +#define PS8811_BEQ_PIN_LEVEL_UP_SHIFT 0 +#define PS8811_BEQ_PIN_LEVEL_UP_9DB 0x00 +#define PS8811_BEQ_PIN_LEVEL_UP_10P5DB 0x01 +#define PS8811_BEQ_PIN_LEVEL_UP_12DB 0x02 +#define PS8811_BEQ_PIN_LEVEL_UP_13DB 0x03 +#define PS8811_BEQ_PIN_LEVEL_UP_16DB 0x04 +#define PS8811_BEQ_PIN_LEVEL_UP_17DB 0x05 +#define PS8811_BEQ_PIN_LEVEL_UP_18DB 0x06 +#define PS8811_BEQ_PIN_LEVEL_UP_19DB 0x07 +#define PS8811_BEQ_PIN_LEVEL_UP_20DB 0x08 +#define PS8811_BEQ_PIN_LEVEL_UP_21DB 0x09 +#define PS8811_BEQ_PIN_LEVEL_UP_23DB 0x0A +#define PS8811_BEQ_I2C_LEVEL_UP_CONFIG_MASK GENMASK(7, 4) +#define PS8811_BEQ_I2C_LEVEL_UP_SHIFT 4 +#define PS8811_BEQ_I2C_LEVEL_UP_9DB 0x00 +#define PS8811_BEQ_I2C_LEVEL_UP_10P5DB 0x01 +#define PS8811_BEQ_I2C_LEVEL_UP_12DB 0x02 +#define PS8811_BEQ_I2C_LEVEL_UP_13DB 0x03 +#define PS8811_BEQ_I2C_LEVEL_UP_16DB 0x04 +#define PS8811_BEQ_I2C_LEVEL_UP_17DB 0x05 +#define PS8811_BEQ_I2C_LEVEL_UP_18DB 0x06 +#define PS8811_BEQ_I2C_LEVEL_UP_19DB 0x07 +#define PS8811_BEQ_I2C_LEVEL_UP_20DB 0x08 +#define PS8811_BEQ_I2C_LEVEL_UP_21DB 0x09 +#define PS8811_BEQ_I2C_LEVEL_UP_23DB 0x0A + +#define PS8811_REG1_USB_BDE_CONFIG 0x06 +#define PS8811_BEQ_CONFIG_REG_ENABLE BIT(0) +#define PS8811_BEQ_ADAPTIVE_REG_ENABLE BIT(1) +#define PS8811_BDE_PIN_MID_LEVEL_CONFIG_MASK GENMASK(7, 5) +#define PS8811_BDE_PIN_MID_LEVEL_SHIFT 5 +#define PS8811_BDE_PIN_MID_LEVEL_0P5DB 0x00 +#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 +#define PS8811_BDE_PIN_LOW_LEVEL_CONFIG_MASK GENMASK(4, 2) +#define PS8811_BDE_PIN_LOW_LEVEL_SHIFT 2 +#define PS8811_BDE_PIN_LOW_LEVEL_0P5DB 0x00 +#define PS8811_BDE_PIN_LOW_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_LOW_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_LOW_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_LOW_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_LOW_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_LOW_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_LOW_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_CHAN_A_SWING 0x66 +#define PS8811_CHAN_A_SWING_MASK GENMASK(6, 4) +#define PS8811_CHAN_A_SWING_SHIFT 4 + +#define PS8811_REG1_50OHM_ADJUST_CHAN_B 0x73 +#define PS8811_50OHM_ADJUST_CHAN_B_CONFIG_MASK GENMASK(3, 1) +#define PS8811_50OHM_ADJUST_CHAN_B_SHIFT 1 +#define PS8811_50OHM_ADJUST_CHAN_B_DEFAULT 0x00 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_6PCT 0x01 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_9PCT 0x02 +#define PS8811_50OHM_ADJUST_CHAN_B_MINUS_14PCT 0x03 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_7PCT 0x04 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_11PCT 0x05 +#define PS8811_50OHM_ADJUST_CHAN_B_PLUS_20PCT 0x06 + +#define PS8811_BDE_PIN_MID_LEVEL_1P5DB 0x01 +#define PS8811_BDE_PIN_MID_LEVEL_2DB 0x02 +#define PS8811_BDE_PIN_MID_LEVEL_3DB 0x03 +#define PS8811_BDE_PIN_MID_LEVEL_3P5DB 0x04 +#define PS8811_BDE_PIN_MID_LEVEL_4P5DB 0x05 +#define PS8811_BDE_PIN_MID_LEVEL_6DB 0x06 +#define PS8811_BDE_PIN_MID_LEVEL_7P5DB 0x07 + +#define PS8811_REG1_USB_CHAN_B_SWING 0xA4 +#define PS8811_CHAN_B_SWING_MASK GENMASK(2, 0) +#define PS8811_CHAN_B_SWING_SHIFT 0 /* De-emphasis -2.2 dB, Pre-shoot 1.2 dB */ -#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1 -#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13 +#define PS8811_CHAN_B_DE_2_2_PS_1_2_LSB 0x1 +#define PS8811_CHAN_B_DE_2_2_PS_1_2_MSB 0x13 /* De-emphasis -3.5 dB, Pre-shoot 0 dB */ -#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0 -#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5 +#define PS8811_CHAN_B_DE_3_5_PS_0_LSB 0x0 +#define PS8811_CHAN_B_DE_3_5_PS_0_MSB 0x5 /* De-emphasis -4.5 dB, Pre-shoot 0 dB */ -#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0 -#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6 +#define PS8811_CHAN_B_DE_4_5_PS_0_LSB 0x0 +#define PS8811_CHAN_B_DE_4_5_PS_0_MSB 0x6 /* De-emphasis -6 dB, Pre-shoot 1.5 dB */ -#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2 -#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16 +#define PS8811_CHAN_B_DE_6_PS_1_5_LSB 0x2 +#define PS8811_CHAN_B_DE_6_PS_1_5_MSB 0x16 /* De-emphasis -6 dB, Pre-shoot 3 dB */ -#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4 -#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16 +#define PS8811_CHAN_B_DE_6_PS_3_LSB 0x4 +#define PS8811_CHAN_B_DE_6_PS_3_MSB 0x16 -#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5 -#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0) +#define PS8811_REG1_USB_CHAN_B_DE_PS_LSB 0xA5 +#define PS8811_CHAN_B_DE_PS_LSB_MASK GENMASK(2, 0) -#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6 -#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0) +#define PS8811_REG1_USB_CHAN_B_DE_PS_MSB 0xA6 +#define PS8811_CHAN_B_DE_PS_MSB_MASK GENMASK(5, 0) int ps8811_i2c_read(const struct usb_mux *me, int page, int offset, int *data); int ps8811_i2c_write(const struct usb_mux *me, int page, int offset, int data); -- cgit v1.2.1 From f5260e4e7c88bd548ee76ed62af209392c3d105a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:56 -0600 Subject: board/servo_v4p1/fusb302b.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic3885f4c292397f6e7ff1e9de9f3503f39f644d2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728925 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/fusb302b.h | 318 ++++++++++++++++++++++---------------------- 1 file changed, 159 insertions(+), 159 deletions(-) diff --git a/board/servo_v4p1/fusb302b.h b/board/servo_v4p1/fusb302b.h index ec89c0c207..d9837c73ba 100644 --- a/board/servo_v4p1/fusb302b.h +++ b/board/servo_v4p1/fusb302b.h @@ -22,173 +22,173 @@ /* FUSB302B11MPX */ #define FUSB302_I2C_ADDR_B11_FLAGS 0x25 -#define TCPC_REG_DEVICE_ID 0x01 - -#define TCPC_REG_SWITCHES0 0x02 -#define TCPC_REG_SWITCHES0_CC2_PU_EN (1<<7) -#define TCPC_REG_SWITCHES0_CC1_PU_EN (1<<6) -#define TCPC_REG_SWITCHES0_VCONN_CC2 (1<<5) -#define TCPC_REG_SWITCHES0_VCONN_CC1 (1<<4) -#define TCPC_REG_SWITCHES0_MEAS_CC2 (1<<3) -#define TCPC_REG_SWITCHES0_MEAS_CC1 (1<<2) -#define TCPC_REG_SWITCHES0_CC2_PD_EN (1<<1) -#define TCPC_REG_SWITCHES0_CC1_PD_EN (1<<0) - -#define TCPC_REG_SWITCHES1 0x03 -#define TCPC_REG_SWITCHES1_POWERROLE (1<<7) -#define TCPC_REG_SWITCHES1_SPECREV1 (1<<6) -#define TCPC_REG_SWITCHES1_SPECREV0 (1<<5) -#define TCPC_REG_SWITCHES1_DATAROLE (1<<4) -#define TCPC_REG_SWITCHES1_AUTO_GCRC (1<<2) -#define TCPC_REG_SWITCHES1_TXCC2_EN (1<<1) -#define TCPC_REG_SWITCHES1_TXCC1_EN (1<<0) - -#define TCPC_REG_MEASURE 0x04 -#define TCPC_REG_MEASURE_MDAC_MASK 0x3F -#define TCPC_REG_MEASURE_VBUS (1<<6) +#define TCPC_REG_DEVICE_ID 0x01 + +#define TCPC_REG_SWITCHES0 0x02 +#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7) +#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6) +#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5) +#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4) +#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3) +#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2) +#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1) +#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0) + +#define TCPC_REG_SWITCHES1 0x03 +#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7) +#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6) +#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5) +#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4) +#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2) +#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1) +#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0) + +#define TCPC_REG_MEASURE 0x04 +#define TCPC_REG_MEASURE_MDAC_MASK 0x3F +#define TCPC_REG_MEASURE_VBUS (1 << 6) /* * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce * maximum error, which also matches suggested thresholds in datasheet * (Table 3. Host Interrupt Summary). */ -#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) - -#define TCPC_REG_CONTROL0 0x06 -#define TCPC_REG_CONTROL0_TX_FLUSH (1<<6) -#define TCPC_REG_CONTROL0_INT_MASK (1<<5) -#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_USB (1<<2) -#define TCPC_REG_CONTROL0_TX_START (1<<0) - -#define TCPC_REG_CONTROL1 0x07 -#define TCPC_REG_CONTROL1_ENSOP2DB (1<<6) -#define TCPC_REG_CONTROL1_ENSOP1DB (1<<5) -#define TCPC_REG_CONTROL1_BIST_MODE2 (1<<4) -#define TCPC_REG_CONTROL1_RX_FLUSH (1<<2) -#define TCPC_REG_CONTROL1_ENSOP2 (1<<1) -#define TCPC_REG_CONTROL1_ENSOP1 (1<<0) - -#define TCPC_REG_CONTROL2 0x08 +#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) + +#define TCPC_REG_CONTROL0 0x06 +#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6) +#define TCPC_REG_CONTROL0_INT_MASK (1 << 5) +#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2) +#define TCPC_REG_CONTROL0_TX_START (1 << 0) + +#define TCPC_REG_CONTROL1 0x07 +#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6) +#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5) +#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4) +#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2) +#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1) +#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0) + +#define TCPC_REG_CONTROL2 0x08 /* two-bit field, valid values below */ -#define TCPC_REG_CONTROL2_MODE_MASK (0x3< Date: Mon, 27 Jun 2022 13:56:10 -0600 Subject: board/nocturne/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I151ae4ead764652ee7fe6ef2d28e128b08398c31 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728760 Reviewed-by: Jeremy Bettis --- board/nocturne/led.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/board/nocturne/led.c b/board/nocturne/led.c index b214a8df84..7891d8459d 100644 --- a/board/nocturne/led.c +++ b/board/nocturne/led.c @@ -19,35 +19,35 @@ const enum ec_led_id supported_led_ids[] = { const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map_v3[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 36, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 15, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 36, 15, 0 }, - [EC_LED_COLOR_WHITE] = { 30, 9, 15 }, - [EC_LED_COLOR_AMBER] = { 30, 1, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 36, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 15, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 36, 15, 0 }, + [EC_LED_COLOR_WHITE] = { 30, 9, 15 }, + [EC_LED_COLOR_AMBER] = { 30, 1, 0 }, }; /* Map for board rev 2 */ struct pwm_led_color_map led_color_map_v2[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 62, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 31, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 100, 54, 0 }, - [EC_LED_COLOR_WHITE] = { 70, 54, 100 }, - [EC_LED_COLOR_AMBER] = { 100, 15, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 62, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 31, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 100, 54, 0 }, + [EC_LED_COLOR_WHITE] = { 70, 54, 100 }, + [EC_LED_COLOR_AMBER] = { 100, 15, 0 }, }; /* Map for board rev 0 and 1 */ struct pwm_led_color_map led_color_map_v0_1[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 1, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 1, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 1 }, - [EC_LED_COLOR_YELLOW] = { 1, 1, 0 }, - [EC_LED_COLOR_WHITE] = { 9, 15, 15 }, - [EC_LED_COLOR_AMBER] = { 15, 1, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 1, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 1, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 1 }, + [EC_LED_COLOR_YELLOW] = { 1, 1, 0 }, + [EC_LED_COLOR_WHITE] = { 9, 15, 15 }, + [EC_LED_COLOR_AMBER] = { 15, 1, 0 }, }; struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { { 0 } }; @@ -135,4 +135,4 @@ static void select_color_map(void) break; } } -DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM-1); +DECLARE_HOOK(HOOK_INIT, select_color_map, HOOK_PRIO_INIT_PWM - 1); -- cgit v1.2.1 From cfb6eec5504ce0be33f4f011a870c2ca1b3d1bed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:26 -0600 Subject: chip/stm32/usb_dwc_registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I634f827304562203dd8c530468fc7b5ed7d1352b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729572 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_registers.h | 14772 +++++++++++++++++++-------------------- 1 file changed, 7380 insertions(+), 7392 deletions(-) diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index faac9ca775..74e18dfc34 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -55,7479 +55,7467 @@ extern struct dwc_usb usb_ctl; * Added Alias Module Family Base Address to 0-instance Module Base Address * Simplify GBASE(mname) macro */ -#define GC_MODULE_OFFSET 0x10000 +#define GC_MODULE_OFFSET 0x10000 -#define GBASE(mname) \ - GC_ ## mname ## _BASE_ADDR -#define GOFFSET(mname, rname) \ - GC_ ## mname ## _ ## rname ## _OFFSET +#define GBASE(mname) GC_##mname##_BASE_ADDR +#define GOFFSET(mname, rname) GC_##mname##_##rname##_OFFSET -#define GREG8(mname, rname) \ - REG8(GBASE(mname) + GOFFSET(mname, rname)) -#define GREG32(mname, rname) \ - REG32(GBASE(mname) + GOFFSET(mname, rname)) +#define GREG8(mname, rname) REG8(GBASE(mname) + GOFFSET(mname, rname)) +#define GREG32(mname, rname) REG32(GBASE(mname) + GOFFSET(mname, rname)) #define GREG32_ADDR(mname, rname) \ REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname)) #define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value)) -#define GREAD(mname, rname) GREG32(mname, rname) +#define GREAD(mname, rname) GREG32(mname, rname) -#define GFIELD_MASK(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK +#define GFIELD_MASK(mname, rname, fname) GC_##mname##_##rname##_##fname##_MASK -#define GFIELD_LSB(mname, rname, fname) \ - GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB +#define GFIELD_LSB(mname, rname, fname) GC_##mname##_##rname##_##fname##_LSB -#define GREAD_FIELD(mname, rname, fname) \ - ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) +#define GREAD_FIELD(mname, rname, fname) \ + ((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) >> \ + GFIELD_LSB(mname, rname, fname)) -#define GWRITE_FIELD(mname, rname, fname, fval) \ - (GREG32(mname, rname) = \ - ((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) +#define GWRITE_FIELD(mname, rname, fname, fval) \ + (GREG32(mname, rname) = \ + ((GREG32(mname, rname) & \ + (~GFIELD_MASK(mname, rname, fname))) | \ + (((fval) << GFIELD_LSB(mname, rname, fname)) & \ + GFIELD_MASK(mname, rname, fname)))) - -#define GBASE_I(mname, i) (GBASE(mname) + i*GC_MODULE_OFFSET) +#define GBASE_I(mname, i) (GBASE(mname) + i * GC_MODULE_OFFSET) #define GREG32_I(mname, i, rname) \ - REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) + REG32(GBASE_I(mname, i) + GOFFSET(mname, rname)) #define GREG32_ADDR_I(mname, i, rname) \ - REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) + REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname)) #define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value)) -#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) +#define GREAD_I(mname, i, rname) GREG32_I(mname, i, rname) -#define GREAD_FIELD_I(mname, i, rname, fname) \ - ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \ - >> GFIELD_LSB(mname, rname, fname)) +#define GREAD_FIELD_I(mname, i, rname, fname) \ + ((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) >> \ + GFIELD_LSB(mname, rname, fname)) -#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ - (GREG32_I(mname, i, rname) = \ - ((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \ - (((fval) << GFIELD_LSB(mname, rname, fname)) & \ - GFIELD_MASK(mname, rname, fname)))) +#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \ + (GREG32_I(mname, i, rname) = \ + ((GREG32_I(mname, i, rname) & \ + (~GFIELD_MASK(mname, rname, fname))) | \ + (((fval) << GFIELD_LSB(mname, rname, fname)) & \ + GFIELD_MASK(mname, rname, fname)))) /* Replace masked bits with val << lsb */ #define REG_WRITE_MLV(reg, mask, lsb, val) \ - (reg = ((reg & ~mask) | ((val << lsb) & mask))) - + (reg = ((reg & ~mask) | ((val << lsb) & mask))) /* USB device controller */ -#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) -#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) -#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) -#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) -#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) -#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) -#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) -#define GINTSTS(bit) (1 << GC_USB_GINTSTS_ ## bit ## _LSB) -#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) -#define GINTMSK(bit) (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB) -#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) -#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) -#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) -#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) +#define GR_USB_REG(off) REG32(GC_USB_BASE_ADDR + (off)) +#define GR_USB_GOTGCTL GR_USB_REG(GC_USB_GOTGCTL_OFFSET) +#define GR_USB_GOTGINT GR_USB_REG(GC_USB_GOTGINT_OFFSET) +#define GR_USB_GAHBCFG GR_USB_REG(GC_USB_GAHBCFG_OFFSET) +#define GR_USB_GUSBCFG GR_USB_REG(GC_USB_GUSBCFG_OFFSET) +#define GR_USB_GRSTCTL GR_USB_REG(GC_USB_GRSTCTL_OFFSET) +#define GR_USB_GINTSTS GR_USB_REG(GC_USB_GINTSTS_OFFSET) +#define GINTSTS(bit) (1 << GC_USB_GINTSTS_##bit##_LSB) +#define GR_USB_GINTMSK GR_USB_REG(GC_USB_GINTMSK_OFFSET) +#define GINTMSK(bit) (1 << GC_USB_GINTMSK_##bit##MSK_LSB) +#define GR_USB_GRXSTSR GR_USB_REG(GC_USB_GRXSTSR_OFFSET) +#define GR_USB_GRXSTSP GR_USB_REG(GC_USB_GRXSTSP_OFFSET) +#define GR_USB_GRXFSIZ GR_USB_REG(GC_USB_GRXFSIZ_OFFSET) +#define GR_USB_GNPTXFSIZ GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET) /*#define GR_USB_GGPIO GR_USB_REG(GC_USB_GGPIO_OFFSET)*/ -#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) -#define GCCFG_VBDEN BIT(21) -#define GCCFG_PWRDWN BIT(16) -#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) +#define GR_USB_GCCFG GR_USB_REG(GC_USB_GCCFG_OFFSET) +#define GCCFG_VBDEN BIT(21) +#define GCCFG_PWRDWN BIT(16) +#define GR_USB_PCGCCTL GR_USB_REG(GC_USB_PCGCCTL_OFFSET) -#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) -#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) -#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) -#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) -#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) -#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) -#define GR_USB_DIEPTXF(n) \ - GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) -#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) -#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) -#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) -#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) -#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) -#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) -#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) -#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) -#define DAINT_OUTEP(ep) \ - (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) -#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) -#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) -#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) -#define DTHRCTL_RXTHREN BIT(16) -#define DTHRCTL_ISOTHREN BIT(1) -#define DTHRCTL_NONISOTHREN BIT(0) -#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) +#define GR_USB_GSNPSID GR_USB_REG(GC_USB_GSNPSID_OFFSET) +#define GR_USB_GHWCFG1 GR_USB_REG(GC_USB_GHWCFG1_OFFSET) +#define GR_USB_GHWCFG2 GR_USB_REG(GC_USB_GHWCFG2_OFFSET) +#define GR_USB_GHWCFG3 GR_USB_REG(GC_USB_GHWCFG3_OFFSET) +#define GR_USB_GHWCFG4 GR_USB_REG(GC_USB_GHWCFG4_OFFSET) +#define GR_USB_GDFIFOCFG GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET) +#define GR_USB_DIEPTXF(n) GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4) +#define GR_USB_DCFG GR_USB_REG(GC_USB_DCFG_OFFSET) +#define GR_USB_DCTL GR_USB_REG(GC_USB_DCTL_OFFSET) +#define GR_USB_DSTS GR_USB_REG(GC_USB_DSTS_OFFSET) +#define GR_USB_DIEPMSK GR_USB_REG(GC_USB_DIEPMSK_OFFSET) +#define GR_USB_DOEPMSK GR_USB_REG(GC_USB_DOEPMSK_OFFSET) +#define GR_USB_DAINT GR_USB_REG(GC_USB_DAINT_OFFSET) +#define GR_USB_DAINTMSK GR_USB_REG(GC_USB_DAINTMSK_OFFSET) +#define DAINT_INEP(ep) (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB)) +#define DAINT_OUTEP(ep) (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB)) +#define GR_USB_DTHRCTL GR_USB_REG(GC_USB_DTHRCTL_OFFSET) +#define DTHRCTL_TXTHRLEN_6 (0x40 << 2) +#define DTHRCTL_RXTHRLEN_6 (0x40 << 17) +#define DTHRCTL_RXTHREN BIT(16) +#define DTHRCTL_ISOTHREN BIT(1) +#define DTHRCTL_NONISOTHREN BIT(0) +#define GR_USB_DIEPEMPMSK GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET) -#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n) * 0x20 + (off)) -#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n) * 0x20 + (off)) -#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) -#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) -#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) -#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) -#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) -#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) -#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) -#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) -#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) -#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) -#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) +#define GR_USB_EPIREG(off, n) GR_USB_REG(0x900 + (n)*0x20 + (off)) +#define GR_USB_EPOREG(off, n) GR_USB_REG(0xb00 + (n)*0x20 + (off)) +#define GR_USB_DIEPCTL(n) GR_USB_EPIREG(0x00, n) +#define GR_USB_DIEPINT(n) GR_USB_EPIREG(0x08, n) +#define GR_USB_DIEPTSIZ(n) GR_USB_EPIREG(0x10, n) +#define GR_USB_DIEPDMA(n) GR_USB_EPIREG(0x14, n) +#define GR_USB_DTXFSTS(n) GR_USB_EPIREG(0x18, n) +#define GR_USB_DIEPDMAB(n) GR_USB_EPIREG(0x1c, n) +#define GR_USB_DOEPCTL(n) GR_USB_EPOREG(0x00, n) +#define GR_USB_DOEPINT(n) GR_USB_EPOREG(0x08, n) +#define GR_USB_DOEPTSIZ(n) GR_USB_EPOREG(0x10, n) +#define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) +#define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) -#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) -#define GOTGCTL_BVALOVAL BIT(7) +#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) +#define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ -#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) /* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) /* HS Burst Len */ -#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) +#define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) /* Bit 7 */ -#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) -#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL -#define GAHBCFG_PTXFELVL BIT(8) +#define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) +#define GAHBCFG_TXFELVL GAHBCFG_NP_TXF_EMP_LVL +#define GAHBCFG_PTXFELVL BIT(8) -#define GUSBCFG_TOUTCAL(n) (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \ - & GC_USB_GUSBCFG_TOUTCAL_MASK) -#define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ - & GC_USB_GUSBCFG_USBTRDTIM_MASK) +#define GUSBCFG_TOUTCAL(n) \ + (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) & GC_USB_GUSBCFG_TOUTCAL_MASK) +#define GUSBCFG_USBTRDTIM(n) \ + (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ -#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) -#define GUSBCFG_PHYSEL BIT(6) -#define GUSBCFG_SRPCAP BIT(8) -#define GUSBCFG_HNPCAP BIT(9) -#define GUSBCFG_ULPIFSLS BIT(17) -#define GUSBCFG_ULPIAR BIT(18) -#define GUSBCFG_ULPICSM BIT(19) -#define GUSBCFG_ULPIEVBUSD BIT(20) -#define GUSBCFG_ULPIEVBUSI BIT(21) -#define GUSBCFG_TSDPS BIT(22) -#define GUSBCFG_PCCI BIT(23) -#define GUSBCFG_PTCI BIT(24) -#define GUSBCFG_ULPIIPD BIT(25) -#define GUSBCFG_TSDPS BIT(22) - +#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_ULPIFSLS BIT(17) +#define GUSBCFG_ULPIAR BIT(18) +#define GUSBCFG_ULPICSM BIT(19) +#define GUSBCFG_ULPIEVBUSD BIT(20) +#define GUSBCFG_ULPIEVBUSI BIT(21) +#define GUSBCFG_TSDPS BIT(22) +#define GUSBCFG_PCCI BIT(23) +#define GUSBCFG_PTCI BIT(24) +#define GUSBCFG_ULPIIPD BIT(25) +#define GUSBCFG_TSDPS BIT(22) -#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) -#define GRSTCTL_TXFNUM(n) \ +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_TXFNUM(n) \ (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) -#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVADDR(a) \ +#define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVADDR(a) \ (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) +#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) -#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) -#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) -#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK -#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) -#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) -#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) +#define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_BULK (2 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) +#define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK +#define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) +#define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) -#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) -#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) -#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) - -#define DOEPDMA_BS_HOST_RDY (0 << 30) -#define DOEPDMA_BS_DMA_BSY (1 << 30) -#define DOEPDMA_BS_DMA_DONE (2 << 30) -#define DOEPDMA_BS_HOST_BSY (3 << 30) -#define DOEPDMA_BS_MASK (3 << 30) -#define DOEPDMA_RXSTS_MASK (3 << 28) -#define DOEPDMA_LAST BIT(27) -#define DOEPDMA_SP BIT(26) -#define DOEPDMA_IOC BIT(25) -#define DOEPDMA_SR BIT(24) -#define DOEPDMA_MTRF BIT(23) -#define DOEPDMA_NAK BIT(16) -#define DOEPDMA_RXBYTES(n) (((n) & 0xFFFF) << 0) -#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) - -#define DIEPDMA_BS_HOST_RDY (0 << 30) -#define DIEPDMA_BS_DMA_BSY (1 << 30) -#define DIEPDMA_BS_DMA_DONE (2 << 30) -#define DIEPDMA_BS_HOST_BSY (3 << 30) -#define DIEPDMA_BS_MASK (3 << 30) -#define DIEPDMA_TXSTS_MASK (3 << 28) -#define DIEPDMA_LAST BIT(27) -#define DIEPDMA_SP BIT(26) -#define DIEPDMA_IOC BIT(25) -#define DIEPDMA_TXBYTES(n) (((n) & 0xFFFF) << 0) -#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) +#define DXEPTSIZ_SUPCNT(n) ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB) +#define DXEPTSIZ_PKTCNT(n) ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB) +#define DXEPTSIZ_XFERSIZE(n) ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB) +#define DOEPDMA_BS_HOST_RDY (0 << 30) +#define DOEPDMA_BS_DMA_BSY (1 << 30) +#define DOEPDMA_BS_DMA_DONE (2 << 30) +#define DOEPDMA_BS_HOST_BSY (3 << 30) +#define DOEPDMA_BS_MASK (3 << 30) +#define DOEPDMA_RXSTS_MASK (3 << 28) +#define DOEPDMA_LAST BIT(27) +#define DOEPDMA_SP BIT(26) +#define DOEPDMA_IOC BIT(25) +#define DOEPDMA_SR BIT(24) +#define DOEPDMA_MTRF BIT(23) +#define DOEPDMA_NAK BIT(16) +#define DOEPDMA_RXBYTES(n) (((n)&0xFFFF) << 0) +#define DOEPDMA_RXBYTES_MASK (0xFFFF << 0) +#define DIEPDMA_BS_HOST_RDY (0 << 30) +#define DIEPDMA_BS_DMA_BSY (1 << 30) +#define DIEPDMA_BS_DMA_DONE (2 << 30) +#define DIEPDMA_BS_HOST_BSY (3 << 30) +#define DIEPDMA_BS_MASK (3 << 30) +#define DIEPDMA_TXSTS_MASK (3 << 28) +#define DIEPDMA_LAST BIT(27) +#define DIEPDMA_SP BIT(26) +#define DIEPDMA_IOC BIT(25) +#define DIEPDMA_TXBYTES(n) (((n)&0xFFFF) << 0) +#define DIEPDMA_TXBYTES_MASK (0xFFFF << 0) /* Register defs referenced from DWC block in CR50. This is not a native * ST block, so we'll use this modified regdefs list. */ -#define GC_USB_FS_BASE_ADDR 0x50000000 -#define GC_USB_HS_BASE_ADDR 0x40040000 +#define GC_USB_FS_BASE_ADDR 0x50000000 +#define GC_USB_HS_BASE_ADDR 0x40040000 #ifdef CONFIG_USB_DWC_FS -#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR +#define GC_USB_BASE_ADDR GC_USB_FS_BASE_ADDR #else -#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR +#define GC_USB_BASE_ADDR GC_USB_HS_BASE_ADDR #endif -#define GC_USB_GOTGCTL_OFFSET 0x0 -#define GC_USB_GOTGCTL_DEFAULT 0x0 -#define GC_USB_GOTGINT_OFFSET 0x4 -#define GC_USB_GOTGINT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_OFFSET 0x8 -#define GC_USB_GAHBCFG_DEFAULT 0x0 -#define GC_USB_GUSBCFG_OFFSET 0xc -#define GC_USB_GUSBCFG_DEFAULT 0x0 -#define GC_USB_GRSTCTL_OFFSET 0x10 -#define GC_USB_GRSTCTL_DEFAULT 0x0 -#define GC_USB_GINTSTS_OFFSET 0x14 -#define GC_USB_GINTSTS_DEFAULT 0x0 -#define GC_USB_GINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DEFAULT 0x0 -#define GC_USB_GRXSTSR_OFFSET 0x1c -#define GC_USB_GRXSTSR_DEFAULT 0x0 -#define GC_USB_GRXSTSP_OFFSET 0x20 -#define GC_USB_GRXSTSP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_OFFSET 0x24 -#define GC_USB_GRXFSIZ_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OFFSET 0x0 +#define GC_USB_GOTGCTL_DEFAULT 0x0 +#define GC_USB_GOTGINT_OFFSET 0x4 +#define GC_USB_GOTGINT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_OFFSET 0x8 +#define GC_USB_GAHBCFG_DEFAULT 0x0 +#define GC_USB_GUSBCFG_OFFSET 0xc +#define GC_USB_GUSBCFG_DEFAULT 0x0 +#define GC_USB_GRSTCTL_OFFSET 0x10 +#define GC_USB_GRSTCTL_DEFAULT 0x0 +#define GC_USB_GINTSTS_OFFSET 0x14 +#define GC_USB_GINTSTS_DEFAULT 0x0 +#define GC_USB_GINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DEFAULT 0x0 +#define GC_USB_GRXSTSR_OFFSET 0x1c +#define GC_USB_GRXSTSR_DEFAULT 0x0 +#define GC_USB_GRXSTSP_OFFSET 0x20 +#define GC_USB_GRXSTSP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_OFFSET 0x24 +#define GC_USB_GRXFSIZ_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_DEFAULT 0x0 -#define GC_USB_GCCFG_OFFSET 0x38 -#define GC_USB_GCCFG_DEFAULT 0x0 -#define GC_USB_GUID_OFFSET 0x3c -#define GC_USB_GUID_DEFAULT 0x0 -#define GC_USB_GSNPSID_OFFSET 0x40 -#define GC_USB_GSNPSID_DEFAULT 0x0 -#define GC_USB_GHWCFG1_OFFSET 0x44 -#define GC_USB_GHWCFG1_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OFFSET 0x48 -#define GC_USB_GHWCFG2_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OFFSET 0x4c -#define GC_USB_GHWCFG3_DEFAULT 0x0 -#define GC_USB_GHWCFG4_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_OFFSET 0x104 -#define GC_USB_DIEPTXF1_DEFAULT 0x1000 -#define GC_USB_DIEPTXF2_OFFSET 0x108 -#define GC_USB_DIEPTXF2_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_OFFSET 0x10c -#define GC_USB_DIEPTXF3_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_OFFSET 0x110 -#define GC_USB_DIEPTXF4_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_OFFSET 0x114 -#define GC_USB_DIEPTXF5_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_OFFSET 0x118 -#define GC_USB_DIEPTXF6_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_OFFSET 0x11c -#define GC_USB_DIEPTXF7_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_OFFSET 0x120 -#define GC_USB_DIEPTXF8_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_OFFSET 0x124 -#define GC_USB_DIEPTXF9_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_OFFSET 0x128 -#define GC_USB_DIEPTXF10_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_OFFSET 0x12c -#define GC_USB_DIEPTXF11_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_OFFSET 0x130 -#define GC_USB_DIEPTXF12_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_OFFSET 0x134 -#define GC_USB_DIEPTXF13_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_OFFSET 0x138 -#define GC_USB_DIEPTXF14_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_OFFSET 0x13c -#define GC_USB_DIEPTXF15_DEFAULT 0x0 -#define GC_USB_DCFG_OFFSET 0x800 -#define GC_USB_DCFG_DEFAULT 0x8000000 -#define GC_USB_DCTL_OFFSET 0x804 -#define GC_USB_DCTL_DEFAULT 0x0 -#define GC_USB_DSTS_OFFSET 0x808 -#define GC_USB_DSTS_DEFAULT 0x0 -#define GC_USB_DIEPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_DEFAULT 0x80 -#define GC_USB_DOEPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_DEFAULT 0x0 -#define GC_USB_DAINT_OFFSET 0x818 -#define GC_USB_DAINT_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OFFSET 0x81c -#define GC_USB_DAINTMSK_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DTHRCTL_OFFSET 0x830 -#define GC_USB_DTHRCTL_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_OFFSET 0x900 -#define GC_USB_DIEPCTL0_DEFAULT 0x0 -#define GC_USB_DIEPINT0_OFFSET 0x908 -#define GC_USB_DIEPINT0_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_OFFSET 0x914 -#define GC_USB_DIEPDMA0_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_OFFSET 0x918 -#define GC_USB_DTXFSTS0_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_OFFSET 0x91c -#define GC_USB_DIEPDMAB0_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DEFAULT 0x0 -#define GC_USB_DIEPINT1_OFFSET 0x928 -#define GC_USB_DIEPINT1_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_OFFSET 0x934 -#define GC_USB_DIEPDMA1_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_OFFSET 0x938 -#define GC_USB_DTXFSTS1_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_OFFSET 0x93c -#define GC_USB_DIEPDMAB1_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DEFAULT 0x0 -#define GC_USB_DIEPINT2_OFFSET 0x948 -#define GC_USB_DIEPINT2_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_OFFSET 0x954 -#define GC_USB_DIEPDMA2_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_OFFSET 0x958 -#define GC_USB_DTXFSTS2_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_OFFSET 0x95c -#define GC_USB_DIEPDMAB2_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DEFAULT 0x0 -#define GC_USB_DIEPINT3_OFFSET 0x968 -#define GC_USB_DIEPINT3_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_OFFSET 0x974 -#define GC_USB_DIEPDMA3_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_OFFSET 0x978 -#define GC_USB_DTXFSTS3_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_OFFSET 0x97c -#define GC_USB_DIEPDMAB3_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DEFAULT 0x0 -#define GC_USB_DIEPINT4_OFFSET 0x988 -#define GC_USB_DIEPINT4_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_OFFSET 0x994 -#define GC_USB_DIEPDMA4_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_OFFSET 0x998 -#define GC_USB_DTXFSTS4_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_OFFSET 0x99c -#define GC_USB_DIEPDMAB4_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DEFAULT 0x0 -#define GC_USB_DIEPINT5_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_OFFSET 0x9b4 -#define GC_USB_DIEPDMA5_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_OFFSET 0x9b8 -#define GC_USB_DTXFSTS5_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_OFFSET 0x9bc -#define GC_USB_DIEPDMAB5_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DEFAULT 0x0 -#define GC_USB_DIEPINT6_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_OFFSET 0x9d4 -#define GC_USB_DIEPDMA6_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_OFFSET 0x9d8 -#define GC_USB_DTXFSTS6_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_OFFSET 0x9dc -#define GC_USB_DIEPDMAB6_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DEFAULT 0x0 -#define GC_USB_DIEPINT7_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_OFFSET 0x9f4 -#define GC_USB_DIEPDMA7_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_OFFSET 0x9f8 -#define GC_USB_DTXFSTS7_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_OFFSET 0x9fc -#define GC_USB_DIEPDMAB7_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DEFAULT 0x0 -#define GC_USB_DIEPINT8_OFFSET 0xa08 -#define GC_USB_DIEPINT8_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_OFFSET 0xa14 -#define GC_USB_DIEPDMA8_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_OFFSET 0xa18 -#define GC_USB_DTXFSTS8_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_OFFSET 0xa1c -#define GC_USB_DIEPDMAB8_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DEFAULT 0x0 -#define GC_USB_DIEPINT9_OFFSET 0xa28 -#define GC_USB_DIEPINT9_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_OFFSET 0xa34 -#define GC_USB_DIEPDMA9_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_OFFSET 0xa38 -#define GC_USB_DTXFSTS9_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_OFFSET 0xa3c -#define GC_USB_DIEPDMAB9_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DEFAULT 0x0 -#define GC_USB_DIEPINT10_OFFSET 0xa48 -#define GC_USB_DIEPINT10_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_OFFSET 0xa54 -#define GC_USB_DIEPDMA10_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_OFFSET 0xa58 -#define GC_USB_DTXFSTS10_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_OFFSET 0xa5c -#define GC_USB_DIEPDMAB10_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DEFAULT 0x0 -#define GC_USB_DIEPINT11_OFFSET 0xa68 -#define GC_USB_DIEPINT11_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_OFFSET 0xa74 -#define GC_USB_DIEPDMA11_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_OFFSET 0xa78 -#define GC_USB_DTXFSTS11_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_OFFSET 0xa7c -#define GC_USB_DIEPDMAB11_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DEFAULT 0x0 -#define GC_USB_DIEPINT12_OFFSET 0xa88 -#define GC_USB_DIEPINT12_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_OFFSET 0xa94 -#define GC_USB_DIEPDMA12_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_OFFSET 0xa98 -#define GC_USB_DTXFSTS12_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_OFFSET 0xa9c -#define GC_USB_DIEPDMAB12_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DEFAULT 0x0 -#define GC_USB_DIEPINT13_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_OFFSET 0xab4 -#define GC_USB_DIEPDMA13_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_OFFSET 0xab8 -#define GC_USB_DTXFSTS13_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_OFFSET 0xabc -#define GC_USB_DIEPDMAB13_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DEFAULT 0x0 -#define GC_USB_DIEPINT14_OFFSET 0xac8 -#define GC_USB_DIEPINT14_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_OFFSET 0xad4 -#define GC_USB_DIEPDMA14_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_OFFSET 0xad8 -#define GC_USB_DTXFSTS14_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_OFFSET 0xadc -#define GC_USB_DIEPDMAB14_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DEFAULT 0x0 -#define GC_USB_DIEPINT15_OFFSET 0xae8 -#define GC_USB_DIEPINT15_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_OFFSET 0xaf4 -#define GC_USB_DIEPDMA15_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_OFFSET 0xaf8 -#define GC_USB_DTXFSTS15_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_OFFSET 0xafc -#define GC_USB_DIEPDMAB15_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OFFSET 0xb08 -#define GC_USB_DOEPINT0_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_OFFSET 0xb14 -#define GC_USB_DOEPDMA0_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_OFFSET 0xb1c -#define GC_USB_DOEPDMAB0_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OFFSET 0xb28 -#define GC_USB_DOEPINT1_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_OFFSET 0xb34 -#define GC_USB_DOEPDMA1_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_OFFSET 0xb3c -#define GC_USB_DOEPDMAB1_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OFFSET 0xb48 -#define GC_USB_DOEPINT2_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_OFFSET 0xb54 -#define GC_USB_DOEPDMA2_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_OFFSET 0xb5c -#define GC_USB_DOEPDMAB2_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OFFSET 0xb68 -#define GC_USB_DOEPINT3_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_OFFSET 0xb74 -#define GC_USB_DOEPDMA3_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_OFFSET 0xb7c -#define GC_USB_DOEPDMAB3_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OFFSET 0xb88 -#define GC_USB_DOEPINT4_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_OFFSET 0xb94 -#define GC_USB_DOEPDMA4_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_OFFSET 0xb9c -#define GC_USB_DOEPDMAB4_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OFFSET 0xba8 -#define GC_USB_DOEPINT5_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_OFFSET 0xbb4 -#define GC_USB_DOEPDMA5_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_OFFSET 0xbbc -#define GC_USB_DOEPDMAB5_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_OFFSET 0xbd4 -#define GC_USB_DOEPDMA6_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_OFFSET 0xbdc -#define GC_USB_DOEPDMAB6_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_OFFSET 0xbf4 -#define GC_USB_DOEPDMA7_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_OFFSET 0xbfc -#define GC_USB_DOEPDMAB7_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OFFSET 0xc08 -#define GC_USB_DOEPINT8_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_OFFSET 0xc14 -#define GC_USB_DOEPDMA8_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_OFFSET 0xc1c -#define GC_USB_DOEPDMAB8_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OFFSET 0xc28 -#define GC_USB_DOEPINT9_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_OFFSET 0xc34 -#define GC_USB_DOEPDMA9_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_OFFSET 0xc3c -#define GC_USB_DOEPDMAB9_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OFFSET 0xc48 -#define GC_USB_DOEPINT10_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_OFFSET 0xc54 -#define GC_USB_DOEPDMA10_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_OFFSET 0xc5c -#define GC_USB_DOEPDMAB10_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OFFSET 0xc68 -#define GC_USB_DOEPINT11_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_OFFSET 0xc74 -#define GC_USB_DOEPDMA11_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_OFFSET 0xc7c -#define GC_USB_DOEPDMAB11_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OFFSET 0xc88 -#define GC_USB_DOEPINT12_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_OFFSET 0xc94 -#define GC_USB_DOEPDMA12_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_OFFSET 0xc9c -#define GC_USB_DOEPDMAB12_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OFFSET 0xca8 -#define GC_USB_DOEPINT13_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_OFFSET 0xcb4 -#define GC_USB_DOEPDMA13_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_OFFSET 0xcbc -#define GC_USB_DOEPDMAB13_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_OFFSET 0xcd4 -#define GC_USB_DOEPDMA14_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_OFFSET 0xcdc -#define GC_USB_DOEPDMAB14_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OFFSET 0xce8 -#define GC_USB_DOEPINT15_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_OFFSET 0xcf4 -#define GC_USB_DOEPDMA15_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_OFFSET 0xcfc -#define GC_USB_DOEPDMAB15_DEFAULT 0x0 -#define GC_USB_PCGCCTL_OFFSET 0xe00 -#define GC_USB_PCGCCTL_DEFAULT 0x0 -#define GC_USB_DFIFO_OFFSET 0x20000 -#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 -#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 -#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 -#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 -#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 -#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 -#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 -#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 -#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 -#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 -#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 -#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 -#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 -#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 -#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 -#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 -#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 -#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 -#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 -#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 -#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 -#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 -#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 -#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 -#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 -#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 -#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 -#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 -#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 -#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 -#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 -#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 -#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 -#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 -#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 -#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 -#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 -#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 -#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 -#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 -#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 -#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e -#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 -#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 -#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 -#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 -#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 -#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 +#define GC_USB_GCCFG_OFFSET 0x38 +#define GC_USB_GCCFG_DEFAULT 0x0 +#define GC_USB_GUID_OFFSET 0x3c +#define GC_USB_GUID_DEFAULT 0x0 +#define GC_USB_GSNPSID_OFFSET 0x40 +#define GC_USB_GSNPSID_DEFAULT 0x0 +#define GC_USB_GHWCFG1_OFFSET 0x44 +#define GC_USB_GHWCFG1_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OFFSET 0x48 +#define GC_USB_GHWCFG2_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OFFSET 0x4c +#define GC_USB_GHWCFG3_DEFAULT 0x0 +#define GC_USB_GHWCFG4_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_OFFSET 0x104 +#define GC_USB_DIEPTXF1_DEFAULT 0x1000 +#define GC_USB_DIEPTXF2_OFFSET 0x108 +#define GC_USB_DIEPTXF2_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_OFFSET 0x10c +#define GC_USB_DIEPTXF3_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_OFFSET 0x110 +#define GC_USB_DIEPTXF4_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_OFFSET 0x114 +#define GC_USB_DIEPTXF5_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_OFFSET 0x118 +#define GC_USB_DIEPTXF6_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_OFFSET 0x11c +#define GC_USB_DIEPTXF7_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_OFFSET 0x120 +#define GC_USB_DIEPTXF8_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_OFFSET 0x124 +#define GC_USB_DIEPTXF9_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_OFFSET 0x128 +#define GC_USB_DIEPTXF10_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_OFFSET 0x12c +#define GC_USB_DIEPTXF11_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_OFFSET 0x130 +#define GC_USB_DIEPTXF12_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_OFFSET 0x134 +#define GC_USB_DIEPTXF13_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_OFFSET 0x138 +#define GC_USB_DIEPTXF14_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_OFFSET 0x13c +#define GC_USB_DIEPTXF15_DEFAULT 0x0 +#define GC_USB_DCFG_OFFSET 0x800 +#define GC_USB_DCFG_DEFAULT 0x8000000 +#define GC_USB_DCTL_OFFSET 0x804 +#define GC_USB_DCTL_DEFAULT 0x0 +#define GC_USB_DSTS_OFFSET 0x808 +#define GC_USB_DSTS_DEFAULT 0x0 +#define GC_USB_DIEPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_DEFAULT 0x80 +#define GC_USB_DOEPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_DEFAULT 0x0 +#define GC_USB_DAINT_OFFSET 0x818 +#define GC_USB_DAINT_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OFFSET 0x81c +#define GC_USB_DAINTMSK_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DTHRCTL_OFFSET 0x830 +#define GC_USB_DTHRCTL_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_OFFSET 0x900 +#define GC_USB_DIEPCTL0_DEFAULT 0x0 +#define GC_USB_DIEPINT0_OFFSET 0x908 +#define GC_USB_DIEPINT0_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_OFFSET 0x914 +#define GC_USB_DIEPDMA0_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_OFFSET 0x918 +#define GC_USB_DTXFSTS0_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_OFFSET 0x91c +#define GC_USB_DIEPDMAB0_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DEFAULT 0x0 +#define GC_USB_DIEPINT1_OFFSET 0x928 +#define GC_USB_DIEPINT1_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_OFFSET 0x934 +#define GC_USB_DIEPDMA1_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_OFFSET 0x938 +#define GC_USB_DTXFSTS1_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_OFFSET 0x93c +#define GC_USB_DIEPDMAB1_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DEFAULT 0x0 +#define GC_USB_DIEPINT2_OFFSET 0x948 +#define GC_USB_DIEPINT2_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_OFFSET 0x954 +#define GC_USB_DIEPDMA2_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_OFFSET 0x958 +#define GC_USB_DTXFSTS2_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_OFFSET 0x95c +#define GC_USB_DIEPDMAB2_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DEFAULT 0x0 +#define GC_USB_DIEPINT3_OFFSET 0x968 +#define GC_USB_DIEPINT3_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_OFFSET 0x974 +#define GC_USB_DIEPDMA3_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_OFFSET 0x978 +#define GC_USB_DTXFSTS3_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_OFFSET 0x97c +#define GC_USB_DIEPDMAB3_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DEFAULT 0x0 +#define GC_USB_DIEPINT4_OFFSET 0x988 +#define GC_USB_DIEPINT4_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_OFFSET 0x994 +#define GC_USB_DIEPDMA4_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_OFFSET 0x998 +#define GC_USB_DTXFSTS4_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_OFFSET 0x99c +#define GC_USB_DIEPDMAB4_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DEFAULT 0x0 +#define GC_USB_DIEPINT5_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_OFFSET 0x9b4 +#define GC_USB_DIEPDMA5_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_OFFSET 0x9b8 +#define GC_USB_DTXFSTS5_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_OFFSET 0x9bc +#define GC_USB_DIEPDMAB5_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DEFAULT 0x0 +#define GC_USB_DIEPINT6_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_OFFSET 0x9d4 +#define GC_USB_DIEPDMA6_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_OFFSET 0x9d8 +#define GC_USB_DTXFSTS6_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_OFFSET 0x9dc +#define GC_USB_DIEPDMAB6_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DEFAULT 0x0 +#define GC_USB_DIEPINT7_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_OFFSET 0x9f4 +#define GC_USB_DIEPDMA7_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_OFFSET 0x9f8 +#define GC_USB_DTXFSTS7_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_OFFSET 0x9fc +#define GC_USB_DIEPDMAB7_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DEFAULT 0x0 +#define GC_USB_DIEPINT8_OFFSET 0xa08 +#define GC_USB_DIEPINT8_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_OFFSET 0xa14 +#define GC_USB_DIEPDMA8_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_OFFSET 0xa18 +#define GC_USB_DTXFSTS8_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_OFFSET 0xa1c +#define GC_USB_DIEPDMAB8_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DEFAULT 0x0 +#define GC_USB_DIEPINT9_OFFSET 0xa28 +#define GC_USB_DIEPINT9_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_OFFSET 0xa34 +#define GC_USB_DIEPDMA9_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_OFFSET 0xa38 +#define GC_USB_DTXFSTS9_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_OFFSET 0xa3c +#define GC_USB_DIEPDMAB9_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DEFAULT 0x0 +#define GC_USB_DIEPINT10_OFFSET 0xa48 +#define GC_USB_DIEPINT10_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_OFFSET 0xa54 +#define GC_USB_DIEPDMA10_DEFAULT 0x0 +#define GC_USB_DTXFSTS10_OFFSET 0xa58 +#define GC_USB_DTXFSTS10_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_OFFSET 0xa5c +#define GC_USB_DIEPDMAB10_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DEFAULT 0x0 +#define GC_USB_DIEPINT11_OFFSET 0xa68 +#define GC_USB_DIEPINT11_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_OFFSET 0xa74 +#define GC_USB_DIEPDMA11_DEFAULT 0x0 +#define GC_USB_DTXFSTS11_OFFSET 0xa78 +#define GC_USB_DTXFSTS11_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_OFFSET 0xa7c +#define GC_USB_DIEPDMAB11_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DEFAULT 0x0 +#define GC_USB_DIEPINT12_OFFSET 0xa88 +#define GC_USB_DIEPINT12_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_OFFSET 0xa94 +#define GC_USB_DIEPDMA12_DEFAULT 0x0 +#define GC_USB_DTXFSTS12_OFFSET 0xa98 +#define GC_USB_DTXFSTS12_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_OFFSET 0xa9c +#define GC_USB_DIEPDMAB12_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DEFAULT 0x0 +#define GC_USB_DIEPINT13_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_OFFSET 0xab4 +#define GC_USB_DIEPDMA13_DEFAULT 0x0 +#define GC_USB_DTXFSTS13_OFFSET 0xab8 +#define GC_USB_DTXFSTS13_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_OFFSET 0xabc +#define GC_USB_DIEPDMAB13_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DEFAULT 0x0 +#define GC_USB_DIEPINT14_OFFSET 0xac8 +#define GC_USB_DIEPINT14_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_OFFSET 0xad4 +#define GC_USB_DIEPDMA14_DEFAULT 0x0 +#define GC_USB_DTXFSTS14_OFFSET 0xad8 +#define GC_USB_DTXFSTS14_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_OFFSET 0xadc +#define GC_USB_DIEPDMAB14_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DEFAULT 0x0 +#define GC_USB_DIEPINT15_OFFSET 0xae8 +#define GC_USB_DIEPINT15_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_OFFSET 0xaf4 +#define GC_USB_DIEPDMA15_DEFAULT 0x0 +#define GC_USB_DTXFSTS15_OFFSET 0xaf8 +#define GC_USB_DTXFSTS15_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_OFFSET 0xafc +#define GC_USB_DIEPDMAB15_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OFFSET 0xb08 +#define GC_USB_DOEPINT0_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_OFFSET 0xb14 +#define GC_USB_DOEPDMA0_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_OFFSET 0xb1c +#define GC_USB_DOEPDMAB0_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OFFSET 0xb28 +#define GC_USB_DOEPINT1_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_OFFSET 0xb34 +#define GC_USB_DOEPDMA1_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_OFFSET 0xb3c +#define GC_USB_DOEPDMAB1_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OFFSET 0xb48 +#define GC_USB_DOEPINT2_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_OFFSET 0xb54 +#define GC_USB_DOEPDMA2_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_OFFSET 0xb5c +#define GC_USB_DOEPDMAB2_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OFFSET 0xb68 +#define GC_USB_DOEPINT3_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_OFFSET 0xb74 +#define GC_USB_DOEPDMA3_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_OFFSET 0xb7c +#define GC_USB_DOEPDMAB3_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OFFSET 0xb88 +#define GC_USB_DOEPINT4_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_OFFSET 0xb94 +#define GC_USB_DOEPDMA4_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_OFFSET 0xb9c +#define GC_USB_DOEPDMAB4_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OFFSET 0xba8 +#define GC_USB_DOEPINT5_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_OFFSET 0xbb4 +#define GC_USB_DOEPDMA5_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_OFFSET 0xbbc +#define GC_USB_DOEPDMAB5_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_OFFSET 0xbd4 +#define GC_USB_DOEPDMA6_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_OFFSET 0xbdc +#define GC_USB_DOEPDMAB6_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_OFFSET 0xbf4 +#define GC_USB_DOEPDMA7_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_OFFSET 0xbfc +#define GC_USB_DOEPDMAB7_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OFFSET 0xc08 +#define GC_USB_DOEPINT8_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_OFFSET 0xc14 +#define GC_USB_DOEPDMA8_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_OFFSET 0xc1c +#define GC_USB_DOEPDMAB8_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OFFSET 0xc28 +#define GC_USB_DOEPINT9_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_OFFSET 0xc34 +#define GC_USB_DOEPDMA9_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_OFFSET 0xc3c +#define GC_USB_DOEPDMAB9_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OFFSET 0xc48 +#define GC_USB_DOEPINT10_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_OFFSET 0xc54 +#define GC_USB_DOEPDMA10_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_OFFSET 0xc5c +#define GC_USB_DOEPDMAB10_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OFFSET 0xc68 +#define GC_USB_DOEPINT11_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_OFFSET 0xc74 +#define GC_USB_DOEPDMA11_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_OFFSET 0xc7c +#define GC_USB_DOEPDMAB11_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OFFSET 0xc88 +#define GC_USB_DOEPINT12_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_OFFSET 0xc94 +#define GC_USB_DOEPDMA12_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_OFFSET 0xc9c +#define GC_USB_DOEPDMAB12_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OFFSET 0xca8 +#define GC_USB_DOEPINT13_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_OFFSET 0xcb4 +#define GC_USB_DOEPDMA13_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_OFFSET 0xcbc +#define GC_USB_DOEPDMAB13_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_OFFSET 0xcd4 +#define GC_USB_DOEPDMA14_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_OFFSET 0xcdc +#define GC_USB_DOEPDMAB14_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OFFSET 0xce8 +#define GC_USB_DOEPINT15_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_OFFSET 0xcf4 +#define GC_USB_DOEPDMA15_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_OFFSET 0xcfc +#define GC_USB_DOEPDMAB15_DEFAULT 0x0 +#define GC_USB_PCGCCTL_OFFSET 0xe00 +#define GC_USB_PCGCCTL_DEFAULT 0x0 +#define GC_USB_DFIFO_OFFSET 0x20000 +#define GC_USB_GOTGCTL_BVALIDOVEN_LSB 0x6 +#define GC_USB_GOTGCTL_BVALIDOVEN_MASK 0x40 +#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB 0x7 +#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK 0x80 +#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE 0x1 +#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_LSB 0x10 +#define GC_USB_GOTGCTL_CONIDSTS_MASK 0x10000 +#define GC_USB_GOTGCTL_CONIDSTS_SIZE 0x1 +#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CONIDSTS_OFFSET 0x0 +#define GC_USB_GOTGCTL_BSESVLD_LSB 0x13 +#define GC_USB_GOTGCTL_BSESVLD_MASK 0x80000 +#define GC_USB_GOTGCTL_BSESVLD_SIZE 0x1 +#define GC_USB_GOTGCTL_BSESVLD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_BSESVLD_OFFSET 0x0 +#define GC_USB_GOTGCTL_OTGVER_LSB 0x14 +#define GC_USB_GOTGCTL_OTGVER_MASK 0x100000 +#define GC_USB_GOTGCTL_OTGVER_SIZE 0x1 +#define GC_USB_GOTGCTL_OTGVER_DEFAULT 0x0 +#define GC_USB_GOTGCTL_OTGVER_OFFSET 0x0 +#define GC_USB_GOTGCTL_CURMOD_LSB 0x15 +#define GC_USB_GOTGCTL_CURMOD_MASK 0x200000 +#define GC_USB_GOTGCTL_CURMOD_SIZE 0x1 +#define GC_USB_GOTGCTL_CURMOD_DEFAULT 0x0 +#define GC_USB_GOTGCTL_CURMOD_OFFSET 0x0 +#define GC_USB_GOTGINT_SESENDDET_LSB 0x2 +#define GC_USB_GOTGINT_SESENDDET_MASK 0x4 +#define GC_USB_GOTGINT_SESENDDET_SIZE 0x1 +#define GC_USB_GOTGINT_SESENDDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESENDDET_OFFSET 0x4 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB 0x8 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB 0x9 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET 0x4 +#define GC_USB_GOTGINT_HSTNEGDET_LSB 0x11 +#define GC_USB_GOTGINT_HSTNEGDET_MASK 0x20000 +#define GC_USB_GOTGINT_HSTNEGDET_SIZE 0x1 +#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT 0x0 +#define GC_USB_GOTGINT_HSTNEGDET_OFFSET 0x4 +#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB 0x12 +#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000 +#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE 0x1 +#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x0 +#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET 0x4 +#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE 0x1 +#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x0 +#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET 0x8 +#define GC_USB_GAHBCFG_HBSTLEN_LSB 0x1 +#define GC_USB_GAHBCFG_HBSTLEN_MASK 0x1e +#define GC_USB_GAHBCFG_HBSTLEN_SIZE 0x4 +#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_HBSTLEN_OFFSET 0x8 +#define GC_USB_GAHBCFG_DMAEN_LSB 0x5 +#define GC_USB_GAHBCFG_DMAEN_MASK 0x20 +#define GC_USB_GAHBCFG_DMAEN_SIZE 0x1 +#define GC_USB_GAHBCFG_DMAEN_DEFAULT 0x0 +#define GC_USB_GAHBCFG_DMAEN_OFFSET 0x8 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB 0x7 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE 0x1 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET 0x8 -#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 -#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 -#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 -#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 -#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 -#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 -#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 -#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 -#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 -#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 -#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 -#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 -#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 -#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 -#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc +#define GC_USB_GAHBCFG_REMMEMSUPP_LSB 0x15 +#define GC_USB_GAHBCFG_REMMEMSUPP_MASK 0x200000 +#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE 0x1 +#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x0 +#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET 0x8 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB 0x16 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE 0x1 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x0 +#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET 0x8 +#define GC_USB_GAHBCFG_AHBSINGLE_LSB 0x17 +#define GC_USB_GAHBCFG_AHBSINGLE_MASK 0x800000 +#define GC_USB_GAHBCFG_AHBSINGLE_SIZE 0x1 +#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT 0x0 +#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET 0x8 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB 0x18 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK 0x1000000 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE 0x1 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT 0x0 +#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET 0x8 +#define GC_USB_GUSBCFG_TOUTCAL_LSB 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_MASK 0x7 +#define GC_USB_GUSBCFG_TOUTCAL_SIZE 0x3 +#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TOUTCAL_OFFSET 0xc -#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa -#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 -#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 -#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 -#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 -#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 -#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 -#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 -#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 -#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc +#define GC_USB_GUSBCFG_USBTRDTIM_LSB 0xa +#define GC_USB_GUSBCFG_USBTRDTIM_MASK 0x3c00 +#define GC_USB_GUSBCFG_USBTRDTIM_SIZE 0x4 +#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET 0xc +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB 15 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK 0x8000 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE 0x1 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIFSLS_LSB 17 +#define GC_USB_GUSBCFG_ULPIFSLS_MASK 0x20000 +#define GC_USB_GUSBCFG_ULPIFSLS_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIAUTORES_LSB 18 +#define GC_USB_GUSBCFG_ULPIAUTORES_MASK 0x40000 +#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB 19 +#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK 0x80000 +#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 -#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 -#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIEVBUSD_LSB 20 +#define GC_USB_GUSBCFG_ULPIEVBUSD_MASK 0x100000 +#define GC_USB_GUSBCFG_ULPIEVBUSD_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIEVBUSD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIEVBUSD_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 -#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 -#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIEVBUSI_LSB 21 +#define GC_USB_GUSBCFG_ULPIEVBUSI_MASK 0x200000 +#define GC_USB_GUSBCFG_ULPIEVBUSI_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIEVBUSI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIEVBUSI_OFFSET 0xc -#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 -#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc +#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB 22 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE 0x1 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x0 +#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET 0xc -#define GC_USB_GUSBCFG_PCCI_LSB 23 -#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) -#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc +#define GC_USB_GUSBCFG_PCCI_LSB 23 +#define GC_USB_GUSBCFG_PCCI_MASK BIT(23) +#define GC_USB_GUSBCFG_PCCI_SIZE 0x1 +#define GC_USB_GUSBCFG_PCCI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PCCI_OFFSET 0xc -#define GC_USB_GUSBCFG_PTCI_LSB 24 -#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) -#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 -#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 -#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc +#define GC_USB_GUSBCFG_PTCI_LSB 24 +#define GC_USB_GUSBCFG_PTCI_MASK BIT(24) +#define GC_USB_GUSBCFG_PTCI_SIZE 0x1 +#define GC_USB_GUSBCFG_PTCI_DEFAULT 0x0 +#define GC_USB_GUSBCFG_PTCI_OFFSET 0xc -#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 -#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) -#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 -#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc +#define GC_USB_GUSBCFG_ULPIIPD_LSB 25 +#define GC_USB_GUSBCFG_ULPIIPD_MASK BIT(25) +#define GC_USB_GUSBCFG_ULPIIPD_SIZE 0x1 +#define GC_USB_GUSBCFG_ULPIIPD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_ULPIIPD_OFFSET 0xc -#define GC_USB_GUSBCFG_FHMOD_LSB 29 -#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) -#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc +#define GC_USB_GUSBCFG_FHMOD_LSB 29 +#define GC_USB_GUSBCFG_FHMOD_MASK BIT(29) +#define GC_USB_GUSBCFG_FHMOD_SIZE 0x1 +#define GC_USB_GUSBCFG_FHMOD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_FHMOD_OFFSET 0xc -#define GC_USB_GUSBCFG_FDMOD_LSB 30 -#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) -#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 -#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 -#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc +#define GC_USB_GUSBCFG_FDMOD_LSB 30 +#define GC_USB_GUSBCFG_FDMOD_MASK BIT(30) +#define GC_USB_GUSBCFG_FDMOD_SIZE 0x1 +#define GC_USB_GUSBCFG_FDMOD_DEFAULT 0x0 +#define GC_USB_GUSBCFG_FDMOD_OFFSET 0xc -#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 -#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 -#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 -#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 -#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 -#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 -#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 -#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 -#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 -#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 -#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 -#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 -#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 -#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 -#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 -#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 -#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e -#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 -#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 -#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 -#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 -#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f -#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 -#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 -#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 -#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 -#define GC_USB_GINTSTS_CURMOD_LSB 0x0 -#define GC_USB_GINTSTS_CURMOD_MASK 0x1 -#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 -#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 -#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 -#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 -#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 -#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 -#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_OTGINT_LSB 0x2 -#define GC_USB_GINTSTS_OTGINT_MASK 0x4 -#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 -#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 -#define GC_USB_GINTSTS_SOF_LSB 0x3 -#define GC_USB_GINTSTS_SOF_MASK 0x8 -#define GC_USB_GINTSTS_SOF_SIZE 0x1 -#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 -#define GC_USB_GINTSTS_SOF_OFFSET 0x14 -#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 -#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 -#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 -#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 -#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 -#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 -#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 -#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 -#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 -#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 -#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 -#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 -#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa -#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 -#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBSUSP_LSB 0xb -#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 -#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_USBRST_LSB 0xc -#define GC_USB_GINTSTS_USBRST_MASK 0x1000 -#define GC_USB_GINTSTS_USBRST_SIZE 0x1 -#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 -#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 -#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd -#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 -#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 -#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 -#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 -#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe -#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 -#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 -#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 -#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 -#define GC_USB_GINTSTS_EOPF_LSB 0xf -#define GC_USB_GINTSTS_EOPF_MASK 0x8000 -#define GC_USB_GINTSTS_EOPF_SIZE 0x1 -#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 -#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 -#define GC_USB_GINTSTS_EPMIS_LSB 0x11 -#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 -#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 -#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 -#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 -#define GC_USB_GINTSTS_IEPINT_LSB 0x12 -#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 -#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_OEPINT_LSB 0x13 -#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 -#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 -#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 -#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 -#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 -#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 -#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 -#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 -#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 -#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 -#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 -#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 -#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 -#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 -#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 -#define GC_USB_GINTSTS_RESETDET_LSB 0x17 -#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 -#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 -#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 -#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 -#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c -#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 -#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 -#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 -#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 -#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e -#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 -#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 -#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 -#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f -#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 -#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 -#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 -#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 -#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 -#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 -#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 -#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 -#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 -#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 -#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 -#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 -#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 -#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 -#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 -#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 -#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa -#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 -#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb -#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 -#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc -#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 -#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd -#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 -#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe -#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf -#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 -#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 -#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 -#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 -#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 -#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 -#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 -#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 -#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 -#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 -#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 -#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 -#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 -#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 -#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 -#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 -#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 -#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 -#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 -#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 -#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 -#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d -#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 -#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e -#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 -#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 -#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f -#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 -#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 -#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 -#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 -#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSR_CHNUM_MASK 0xf -#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c -#define GC_USB_GRXSTSR_BCNT_LSB 0x4 -#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSR_BCNT_SIZE 0xb -#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c -#define GC_USB_GRXSTSR_DPID_LSB 0xf -#define GC_USB_GRXSTSR_DPID_MASK 0x18000 -#define GC_USB_GRXSTSR_DPID_SIZE 0x2 -#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c -#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c -#define GC_USB_GRXSTSR_FN_LSB 0x15 -#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSR_FN_SIZE 0x4 -#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSR_FN_OFFSET 0x1c -#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 -#define GC_USB_GRXSTSP_CHNUM_MASK 0xf -#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 -#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 -#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 -#define GC_USB_GRXSTSP_BCNT_LSB 0x4 -#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 -#define GC_USB_GRXSTSP_BCNT_SIZE 0xb -#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 -#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 -#define GC_USB_GRXSTSP_DPID_LSB 0xf -#define GC_USB_GRXSTSP_DPID_MASK 0x18000 -#define GC_USB_GRXSTSP_DPID_SIZE 0x2 -#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 -#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 -#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 -#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 -#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 -#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 -#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 -#define GC_USB_GRXSTSP_FN_LSB 0x15 -#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 -#define GC_USB_GRXSTSP_FN_SIZE 0x4 -#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 -#define GC_USB_GRXSTSP_FN_OFFSET 0x20 -#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff -#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb -#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 -#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 -#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 +#define GC_USB_GRSTCTL_CSFTRST_LSB 0x0 +#define GC_USB_GRSTCTL_CSFTRST_MASK 0x1 +#define GC_USB_GRSTCTL_CSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_CSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_CSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK 0x2 +#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE 0x1 +#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT 0x0 +#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_LSB 0x4 +#define GC_USB_GRSTCTL_RXFFLSH_MASK 0x10 +#define GC_USB_GRSTCTL_RXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_RXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFFLSH_LSB 0x5 +#define GC_USB_GRSTCTL_TXFFLSH_MASK 0x20 +#define GC_USB_GRSTCTL_TXFFLSH_SIZE 0x1 +#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFFLSH_OFFSET 0x10 +#define GC_USB_GRSTCTL_TXFNUM_LSB 0x6 +#define GC_USB_GRSTCTL_TXFNUM_MASK 0x7c0 +#define GC_USB_GRSTCTL_TXFNUM_SIZE 0x5 +#define GC_USB_GRSTCTL_TXFNUM_DEFAULT 0x0 +#define GC_USB_GRSTCTL_TXFNUM_OFFSET 0x10 +#define GC_USB_GRSTCTL_DMAREQ_LSB 0x1e +#define GC_USB_GRSTCTL_DMAREQ_MASK 0x40000000 +#define GC_USB_GRSTCTL_DMAREQ_SIZE 0x1 +#define GC_USB_GRSTCTL_DMAREQ_DEFAULT 0x0 +#define GC_USB_GRSTCTL_DMAREQ_OFFSET 0x10 +#define GC_USB_GRSTCTL_AHBIDLE_LSB 0x1f +#define GC_USB_GRSTCTL_AHBIDLE_MASK 0x80000000 +#define GC_USB_GRSTCTL_AHBIDLE_SIZE 0x1 +#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT 0x0 +#define GC_USB_GRSTCTL_AHBIDLE_OFFSET 0x10 +#define GC_USB_GINTSTS_CURMOD_LSB 0x0 +#define GC_USB_GINTSTS_CURMOD_MASK 0x1 +#define GC_USB_GINTSTS_CURMOD_SIZE 0x1 +#define GC_USB_GINTSTS_CURMOD_DEFAULT 0x0 +#define GC_USB_GINTSTS_CURMOD_OFFSET 0x14 +#define GC_USB_GINTSTS_MODEMIS_LSB 0x1 +#define GC_USB_GINTSTS_MODEMIS_MASK 0x2 +#define GC_USB_GINTSTS_MODEMIS_SIZE 0x1 +#define GC_USB_GINTSTS_MODEMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_MODEMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_OTGINT_LSB 0x2 +#define GC_USB_GINTSTS_OTGINT_MASK 0x4 +#define GC_USB_GINTSTS_OTGINT_SIZE 0x1 +#define GC_USB_GINTSTS_OTGINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OTGINT_OFFSET 0x14 +#define GC_USB_GINTSTS_SOF_LSB 0x3 +#define GC_USB_GINTSTS_SOF_MASK 0x8 +#define GC_USB_GINTSTS_SOF_SIZE 0x1 +#define GC_USB_GINTSTS_SOF_DEFAULT 0x0 +#define GC_USB_GINTSTS_SOF_OFFSET 0x14 +#define GC_USB_GINTSTS_RXFLVL_LSB 0x4 +#define GC_USB_GINTSTS_RXFLVL_MASK 0x10 +#define GC_USB_GINTSTS_RXFLVL_SIZE 0x1 +#define GC_USB_GINTSTS_RXFLVL_DEFAULT 0x0 +#define GC_USB_GINTSTS_RXFLVL_OFFSET 0x14 +#define GC_USB_GINTSTS_GINNAKEFF_LSB 0x6 +#define GC_USB_GINTSTS_GINNAKEFF_MASK 0x40 +#define GC_USB_GINTSTS_GINNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GINNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_GOUTNAKEFF_LSB 0x7 +#define GC_USB_GINTSTS_GOUTNAKEFF_MASK 0x80 +#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE 0x1 +#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x0 +#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET 0x14 +#define GC_USB_GINTSTS_ERLYSUSP_LSB 0xa +#define GC_USB_GINTSTS_ERLYSUSP_MASK 0x400 +#define GC_USB_GINTSTS_ERLYSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ERLYSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBSUSP_LSB 0xb +#define GC_USB_GINTSTS_USBSUSP_MASK 0x800 +#define GC_USB_GINTSTS_USBSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_USBSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_USBRST_LSB 0xc +#define GC_USB_GINTSTS_USBRST_MASK 0x1000 +#define GC_USB_GINTSTS_USBRST_SIZE 0x1 +#define GC_USB_GINTSTS_USBRST_DEFAULT 0x0 +#define GC_USB_GINTSTS_USBRST_OFFSET 0x14 +#define GC_USB_GINTSTS_ENUMDONE_LSB 0xd +#define GC_USB_GINTSTS_ENUMDONE_MASK 0x2000 +#define GC_USB_GINTSTS_ENUMDONE_SIZE 0x1 +#define GC_USB_GINTSTS_ENUMDONE_DEFAULT 0x0 +#define GC_USB_GINTSTS_ENUMDONE_OFFSET 0x14 +#define GC_USB_GINTSTS_ISOOUTDROP_LSB 0xe +#define GC_USB_GINTSTS_ISOOUTDROP_MASK 0x4000 +#define GC_USB_GINTSTS_ISOOUTDROP_SIZE 0x1 +#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT 0x0 +#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET 0x14 +#define GC_USB_GINTSTS_EOPF_LSB 0xf +#define GC_USB_GINTSTS_EOPF_MASK 0x8000 +#define GC_USB_GINTSTS_EOPF_SIZE 0x1 +#define GC_USB_GINTSTS_EOPF_DEFAULT 0x0 +#define GC_USB_GINTSTS_EOPF_OFFSET 0x14 +#define GC_USB_GINTSTS_EPMIS_LSB 0x11 +#define GC_USB_GINTSTS_EPMIS_MASK 0x20000 +#define GC_USB_GINTSTS_EPMIS_SIZE 0x1 +#define GC_USB_GINTSTS_EPMIS_DEFAULT 0x0 +#define GC_USB_GINTSTS_EPMIS_OFFSET 0x14 +#define GC_USB_GINTSTS_IEPINT_LSB 0x12 +#define GC_USB_GINTSTS_IEPINT_MASK 0x40000 +#define GC_USB_GINTSTS_IEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_IEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_IEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_OEPINT_LSB 0x13 +#define GC_USB_GINTSTS_OEPINT_MASK 0x80000 +#define GC_USB_GINTSTS_OEPINT_SIZE 0x1 +#define GC_USB_GINTSTS_OEPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_OEPINT_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_LSB 0x14 +#define GC_USB_GINTSTS_INCOMPISOIN_MASK 0x100000 +#define GC_USB_GINTSTS_INCOMPISOIN_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET 0x14 +#define GC_USB_GINTSTS_INCOMPLP_LSB 0x15 +#define GC_USB_GINTSTS_INCOMPLP_MASK 0x200000 +#define GC_USB_GINTSTS_INCOMPLP_SIZE 0x1 +#define GC_USB_GINTSTS_INCOMPLP_DEFAULT 0x0 +#define GC_USB_GINTSTS_INCOMPLP_OFFSET 0x14 +#define GC_USB_GINTSTS_FETSUSP_LSB 0x16 +#define GC_USB_GINTSTS_FETSUSP_MASK 0x400000 +#define GC_USB_GINTSTS_FETSUSP_SIZE 0x1 +#define GC_USB_GINTSTS_FETSUSP_DEFAULT 0x0 +#define GC_USB_GINTSTS_FETSUSP_OFFSET 0x14 +#define GC_USB_GINTSTS_RESETDET_LSB 0x17 +#define GC_USB_GINTSTS_RESETDET_MASK 0x800000 +#define GC_USB_GINTSTS_RESETDET_SIZE 0x1 +#define GC_USB_GINTSTS_RESETDET_DEFAULT 0x0 +#define GC_USB_GINTSTS_RESETDET_OFFSET 0x14 +#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB 0x1c +#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000 +#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE 0x1 +#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x0 +#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET 0x14 +#define GC_USB_GINTSTS_SESSREQINT_LSB 0x1e +#define GC_USB_GINTSTS_SESSREQINT_MASK 0x40000000 +#define GC_USB_GINTSTS_SESSREQINT_SIZE 0x1 +#define GC_USB_GINTSTS_SESSREQINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_SESSREQINT_OFFSET 0x14 +#define GC_USB_GINTSTS_WKUPINT_LSB 0x1f +#define GC_USB_GINTSTS_WKUPINT_MASK 0x80000000 +#define GC_USB_GINTSTS_WKUPINT_SIZE 0x1 +#define GC_USB_GINTSTS_WKUPINT_DEFAULT 0x0 +#define GC_USB_GINTSTS_WKUPINT_OFFSET 0x14 +#define GC_USB_GINTMSK_MODEMISMSK_LSB 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_MASK 0x2 +#define GC_USB_GINTMSK_MODEMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_MODEMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OTGINTMSK_LSB 0x2 +#define GC_USB_GINTMSK_OTGINTMSK_MASK 0x4 +#define GC_USB_GINTMSK_OTGINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OTGINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SOFMSK_LSB 0x3 +#define GC_USB_GINTMSK_SOFMSK_MASK 0x8 +#define GC_USB_GINTMSK_SOFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SOFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SOFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RXFLVLMSK_LSB 0x4 +#define GC_USB_GINTMSK_RXFLVLMSK_MASK 0x10 +#define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 +#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 +#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 +#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 +#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 +#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB 0x7 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB 0xa +#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK 0x400 +#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBSUSPMSK_LSB 0xb +#define GC_USB_GINTMSK_USBSUSPMSK_MASK 0x800 +#define GC_USB_GINTMSK_USBSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_USBRSTMSK_LSB 0xc +#define GC_USB_GINTMSK_USBRSTMSK_MASK 0x1000 +#define GC_USB_GINTMSK_USBRSTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_USBRSTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ENUMDONEMSK_LSB 0xd +#define GC_USB_GINTMSK_ENUMDONEMSK_MASK 0x2000 +#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB 0xe +#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_EOPFMSK_LSB 0xf +#define GC_USB_GINTMSK_EOPFMSK_MASK 0x8000 +#define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 +#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 +#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 +#define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 +#define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 +#define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 +#define GC_USB_GINTMSK_EPMISMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_EPMISMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_IEPINTMSK_LSB 0x12 +#define GC_USB_GINTMSK_IEPINTMSK_MASK 0x40000 +#define GC_USB_GINTMSK_IEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_IEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_OEPINTMSK_LSB 0x13 +#define GC_USB_GINTMSK_OEPINTMSK_MASK 0x80000 +#define GC_USB_GINTMSK_OEPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_OEPINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB 0x14 +#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000 +#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB 0x15 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK 0x200000 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_FETSUSPMSK_LSB 0x16 +#define GC_USB_GINTMSK_FETSUSPMSK_MASK 0x400000 +#define GC_USB_GINTMSK_FETSUSPMSK_SIZE 0x1 +#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_RESETDETMSK_LSB 0x17 +#define GC_USB_GINTMSK_RESETDETMSK_MASK 0x800000 +#define GC_USB_GINTMSK_RESETDETMSK_SIZE 0x1 +#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_RESETDETMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB 0x1c +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE 0x1 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_DISCONNINTMSK_LSB 0x1d +#define GC_USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000 +#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_SESSREQINTMSK_LSB 0x1e +#define GC_USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000 +#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_WKUPINTMSK_LSB 0x1f +#define GC_USB_GINTMSK_WKUPINTMSK_MASK 0x80000000 +#define GC_USB_GINTMSK_WKUPINTMSK_SIZE 0x1 +#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT 0x0 +#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET 0x18 +#define GC_USB_GRXSTSR_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSR_CHNUM_MASK 0xf +#define GC_USB_GRXSTSR_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSR_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSR_CHNUM_OFFSET 0x1c +#define GC_USB_GRXSTSR_BCNT_LSB 0x4 +#define GC_USB_GRXSTSR_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSR_BCNT_SIZE 0xb +#define GC_USB_GRXSTSR_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSR_BCNT_OFFSET 0x1c +#define GC_USB_GRXSTSR_DPID_LSB 0xf +#define GC_USB_GRXSTSR_DPID_MASK 0x18000 +#define GC_USB_GRXSTSR_DPID_SIZE 0x2 +#define GC_USB_GRXSTSR_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSR_DPID_OFFSET 0x1c +#define GC_USB_GRXSTSR_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSR_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSR_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSR_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSR_PKTSTS_OFFSET 0x1c +#define GC_USB_GRXSTSR_FN_LSB 0x15 +#define GC_USB_GRXSTSR_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSR_FN_SIZE 0x4 +#define GC_USB_GRXSTSR_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSR_FN_OFFSET 0x1c +#define GC_USB_GRXSTSP_CHNUM_LSB 0x0 +#define GC_USB_GRXSTSP_CHNUM_MASK 0xf +#define GC_USB_GRXSTSP_CHNUM_SIZE 0x4 +#define GC_USB_GRXSTSP_CHNUM_DEFAULT 0x0 +#define GC_USB_GRXSTSP_CHNUM_OFFSET 0x20 +#define GC_USB_GRXSTSP_BCNT_LSB 0x4 +#define GC_USB_GRXSTSP_BCNT_MASK 0x7ff0 +#define GC_USB_GRXSTSP_BCNT_SIZE 0xb +#define GC_USB_GRXSTSP_BCNT_DEFAULT 0x0 +#define GC_USB_GRXSTSP_BCNT_OFFSET 0x20 +#define GC_USB_GRXSTSP_DPID_LSB 0xf +#define GC_USB_GRXSTSP_DPID_MASK 0x18000 +#define GC_USB_GRXSTSP_DPID_SIZE 0x2 +#define GC_USB_GRXSTSP_DPID_DEFAULT 0x0 +#define GC_USB_GRXSTSP_DPID_OFFSET 0x20 +#define GC_USB_GRXSTSP_PKTSTS_LSB 0x11 +#define GC_USB_GRXSTSP_PKTSTS_MASK 0x1e0000 +#define GC_USB_GRXSTSP_PKTSTS_SIZE 0x4 +#define GC_USB_GRXSTSP_PKTSTS_DEFAULT 0x0 +#define GC_USB_GRXSTSP_PKTSTS_OFFSET 0x20 +#define GC_USB_GRXSTSP_FN_LSB 0x15 +#define GC_USB_GRXSTSP_FN_MASK 0x1e00000 +#define GC_USB_GRXSTSP_FN_SIZE 0x4 +#define GC_USB_GRXSTSP_FN_DEFAULT 0x0 +#define GC_USB_GRXSTSP_FN_OFFSET 0x20 +#define GC_USB_GRXFSIZ_RXFDEP_LSB 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_MASK 0x7ff +#define GC_USB_GRXFSIZ_RXFDEP_SIZE 0xb +#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT 0x0 +#define GC_USB_GRXFSIZ_RXFDEP_OFFSET 0x24 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK 0xffff +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET 0x28 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK 0xffff0000 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE 0x10 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT 0x0 +#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET 0x28 -#define GC_USB_GUID_GUID_LSB 0x0 -#define GC_USB_GUID_GUID_MASK 0xffffffff -#define GC_USB_GUID_GUID_SIZE 0x20 -#define GC_USB_GUID_GUID_DEFAULT 0x0 -#define GC_USB_GUID_GUID_OFFSET 0x3c -#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff -#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 -#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 -#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 -#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 -#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff -#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 -#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 -#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 -#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 -#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 -#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 -#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 -#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 -#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 -#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 -#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 -#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 -#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 -#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 -#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 -#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 -#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 -#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 -#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 -#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 -#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa -#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 -#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 -#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe -#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 -#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 -#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 -#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 -#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 -#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 -#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 -#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 -#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 -#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 -#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 -#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 -#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 -#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a -#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 -#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 -#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c -#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 -#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 -#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 -#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c -#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 -#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 -#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 -#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 -#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c -#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 -#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 -#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 -#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c -#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa -#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 -#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 -#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c -#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb -#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 -#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 -#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c -#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc -#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 -#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd -#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 -#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe -#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 -#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 -#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 -#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c -#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf -#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 -#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 -#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c -#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 -#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 -#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 -#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 -#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 -#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 -#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 -#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 -#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 -#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 -#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 -#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 -#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 -#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 -#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 -#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 -#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 +#define GC_USB_GUID_GUID_LSB 0x0 +#define GC_USB_GUID_GUID_MASK 0xffffffff +#define GC_USB_GUID_GUID_SIZE 0x20 +#define GC_USB_GUID_GUID_DEFAULT 0x0 +#define GC_USB_GUID_GUID_OFFSET 0x3c +#define GC_USB_GSNPSID_SYNOPSYSID_LSB 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_MASK 0xffffffff +#define GC_USB_GSNPSID_SYNOPSYSID_SIZE 0x20 +#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT 0x0 +#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET 0x40 +#define GC_USB_GHWCFG1_EPDIR_LSB 0x0 +#define GC_USB_GHWCFG1_EPDIR_MASK 0xffffffff +#define GC_USB_GHWCFG1_EPDIR_SIZE 0x20 +#define GC_USB_GHWCFG1_EPDIR_DEFAULT 0x0 +#define GC_USB_GHWCFG1_EPDIR_OFFSET 0x44 +#define GC_USB_GHWCFG2_OTGMODE_LSB 0x0 +#define GC_USB_GHWCFG2_OTGMODE_MASK 0x7 +#define GC_USB_GHWCFG2_OTGMODE_SIZE 0x3 +#define GC_USB_GHWCFG2_OTGMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGMODE_OFFSET 0x48 +#define GC_USB_GHWCFG2_OTGARCH_LSB 0x3 +#define GC_USB_GHWCFG2_OTGARCH_MASK 0x18 +#define GC_USB_GHWCFG2_OTGARCH_SIZE 0x2 +#define GC_USB_GHWCFG2_OTGARCH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_OTGARCH_OFFSET 0x48 +#define GC_USB_GHWCFG2_SINGPNT_LSB 0x5 +#define GC_USB_GHWCFG2_SINGPNT_MASK 0x20 +#define GC_USB_GHWCFG2_SINGPNT_SIZE 0x1 +#define GC_USB_GHWCFG2_SINGPNT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_SINGPNT_OFFSET 0x48 +#define GC_USB_GHWCFG2_HSPHYTYPE_LSB 0x6 +#define GC_USB_GHWCFG2_HSPHYTYPE_MASK 0xc0 +#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_FSPHYTYPE_LSB 0x8 +#define GC_USB_GHWCFG2_FSPHYTYPE_MASK 0x300 +#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE 0x2 +#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMDEVEPS_LSB 0xa +#define GC_USB_GHWCFG2_NUMDEVEPS_MASK 0x3c00 +#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET 0x48 +#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB 0xe +#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK 0x3c000 +#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE 0x4 +#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET 0x48 +#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB 0x12 +#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK 0x40000 +#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET 0x48 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB 0x13 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK 0x80000 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE 0x1 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT 0x0 +#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET 0x48 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB 0x14 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK 0x100000 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE 0x1 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT 0x0 +#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET 0x48 +#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB 0x16 +#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK 0xc00000 +#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_PTXQDEPTH_LSB 0x18 +#define GC_USB_GHWCFG2_PTXQDEPTH_MASK 0x3000000 +#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE 0x2 +#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG2_TKNQDEPTH_LSB 0x1a +#define GC_USB_GHWCFG2_TKNQDEPTH_MASK 0x7c000000 +#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE 0x5 +#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET 0x48 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK 0xf +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE 0x4 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB 0x4 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK 0x70 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE 0x3 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET 0x4c +#define GC_USB_GHWCFG3_OTGEN_LSB 0x7 +#define GC_USB_GHWCFG3_OTGEN_MASK 0x80 +#define GC_USB_GHWCFG3_OTGEN_SIZE 0x1 +#define GC_USB_GHWCFG3_OTGEN_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OTGEN_OFFSET 0x4c +#define GC_USB_GHWCFG3_I2CINTSEL_LSB 0x8 +#define GC_USB_GHWCFG3_I2CINTSEL_MASK 0x100 +#define GC_USB_GHWCFG3_I2CINTSEL_SIZE 0x1 +#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT 0x0 +#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET 0x4c +#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB 0x9 +#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK 0x200 +#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE 0x1 +#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET 0x4c +#define GC_USB_GHWCFG3_OPTFEATURE_LSB 0xa +#define GC_USB_GHWCFG3_OPTFEATURE_MASK 0x400 +#define GC_USB_GHWCFG3_OPTFEATURE_SIZE 0x1 +#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET 0x4c +#define GC_USB_GHWCFG3_RSTTYPE_LSB 0xb +#define GC_USB_GHWCFG3_RSTTYPE_MASK 0x800 +#define GC_USB_GHWCFG3_RSTTYPE_SIZE 0x1 +#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_RSTTYPE_OFFSET 0x4c +#define GC_USB_GHWCFG3_ADPSUPPORT_LSB 0xc +#define GC_USB_GHWCFG3_ADPSUPPORT_MASK 0x1000 +#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_HSICMODE_LSB 0xd +#define GC_USB_GHWCFG3_HSICMODE_MASK 0x2000 +#define GC_USB_GHWCFG3_HSICMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_HSICMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_HSICMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_BCSUPPORT_LSB 0xe +#define GC_USB_GHWCFG3_BCSUPPORT_MASK 0x4000 +#define GC_USB_GHWCFG3_BCSUPPORT_SIZE 0x1 +#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT 0x0 +#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET 0x4c +#define GC_USB_GHWCFG3_LPMMODE_LSB 0xf +#define GC_USB_GHWCFG3_LPMMODE_MASK 0x8000 +#define GC_USB_GHWCFG3_LPMMODE_SIZE 0x1 +#define GC_USB_GHWCFG3_LPMMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG3_LPMMODE_OFFSET 0x4c +#define GC_USB_GHWCFG3_DFIFODEPTH_LSB 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_MASK 0xffff0000 +#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE 0x10 +#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT 0x0 +#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET 0x4c +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK 0xf +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB 0x4 +#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK 0x10 +#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE 0x1 +#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET 0x50 +#define GC_USB_GHWCFG4_AHBFREQ_LSB 0x5 +#define GC_USB_GHWCFG4_AHBFREQ_MASK 0x20 +#define GC_USB_GHWCFG4_AHBFREQ_SIZE 0x1 +#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AHBFREQ_OFFSET 0x50 +#define GC_USB_GHWCFG4_HIBERNATION_LSB 0x6 +#define GC_USB_GHWCFG4_HIBERNATION_MASK 0x40 +#define GC_USB_GHWCFG4_HIBERNATION_SIZE 0x1 +#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT 0x0 +#define GC_USB_GHWCFG4_HIBERNATION_OFFSET 0x50 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB 0x7 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK 0x80 +#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE 0x1 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0 #define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe -#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 -#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 -#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 -#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 -#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 -#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 -#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 -#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 -#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 -#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 -#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 -#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 -#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 -#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 -#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 -#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 -#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 -#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 -#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 -#define GC_USB_GHWCFG4_INEPS_LSB 0x1a -#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 -#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 -#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 -#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e -#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 -#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 -#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f -#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 -#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 -#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 -#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff -#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 -#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 -#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc -#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 -#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 -#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c -#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c -#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c -#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c -#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 -#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c -#define GC_USB_DCFG_DEVSPD_LSB 0x0 -#define GC_USB_DCFG_DEVSPD_MASK 0x3 -#define GC_USB_DCFG_DEVSPD_SIZE 0x2 -#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 -#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 -#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 -#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 -#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 -#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 -#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 -#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 -#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 -#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 -#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 -#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 -#define GC_USB_DCFG_DEVADDR_LSB 0x4 -#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 -#define GC_USB_DCFG_DEVADDR_SIZE 0x7 -#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 -#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 -#define GC_USB_DCFG_PERFRINT_LSB 0xb -#define GC_USB_DCFG_PERFRINT_MASK 0x1800 -#define GC_USB_DCFG_PERFRINT_SIZE 0x2 -#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 -#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 -#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd -#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 -#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 -#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 -#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 -#define GC_USB_DCFG_XCVRDLY_LSB 0xe -#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 -#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 -#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 -#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 -#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf -#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 -#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 -#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 -#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 -#define GC_USB_DCFG_DESCDMA_LSB 0x17 -#define GC_USB_DCFG_DESCDMA_MASK 0x800000 -#define GC_USB_DCFG_DESCDMA_SIZE 0x1 -#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 -#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 -#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 -#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 -#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 -#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 -#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 -#define GC_USB_DCFG_RESVALID_LSB 0x1a -#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 -#define GC_USB_DCFG_RESVALID_SIZE 0x6 -#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 -#define GC_USB_DCFG_RESVALID_OFFSET 0x800 -#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 -#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 -#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 -#define GC_USB_DCTL_SFTDISCON_LSB 0x1 -#define GC_USB_DCTL_SFTDISCON_MASK 0x2 -#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 -#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 -#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 -#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 -#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 -#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 -#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 -#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 -#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 -#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 -#define GC_USB_DCTL_TSTCTL_LSB 0x4 -#define GC_USB_DCTL_TSTCTL_MASK 0x70 -#define GC_USB_DCTL_TSTCTL_SIZE 0x3 -#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 -#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 -#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 -#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 -#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 -#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 -#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 -#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 -#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 -#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 -#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_CGOUTNAK_LSB 0xa -#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 -#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 -#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 -#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 -#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb -#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 -#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 -#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 -#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 -#define GC_USB_DCTL_GMC_LSB 0xd -#define GC_USB_DCTL_GMC_MASK 0x6000 -#define GC_USB_DCTL_GMC_SIZE 0x2 -#define GC_USB_DCTL_GMC_DEFAULT 0x0 -#define GC_USB_DCTL_GMC_OFFSET 0x804 -#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf -#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 -#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 -#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 -#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 -#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 -#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 -#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 -#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 -#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 -#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 -#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 -#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 -#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 -#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 -#define GC_USB_DSTS_SUSPSTS_LSB 0x0 -#define GC_USB_DSTS_SUSPSTS_MASK 0x1 -#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 -#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 -#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 -#define GC_USB_DSTS_ENUMSPD_LSB 0x1 -#define GC_USB_DSTS_ENUMSPD_MASK 0x6 -#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 -#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 -#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 -#define GC_USB_DSTS_ERRTICERR_LSB 0x3 -#define GC_USB_DSTS_ERRTICERR_MASK 0x8 -#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 -#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 -#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 -#define GC_USB_DSTS_SOFFN_LSB 0x8 -#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 -#define GC_USB_DSTS_SOFFN_SIZE 0xe -#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 -#define GC_USB_DSTS_SOFFN_OFFSET 0x808 -#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 -#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 -#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 -#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 -#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 -#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 -#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 -#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 -#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 -#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 -#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 -#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 -#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 -#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 -#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 -#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 -#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 -#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc -#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 -#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd -#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 -#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 -#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe -#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 -#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 -#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 -#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 -#define GC_USB_DAINT_INEPINT0_LSB 0x0 -#define GC_USB_DAINT_INEPINT0_MASK 0x1 -#define GC_USB_DAINT_INEPINT0_SIZE 0x1 -#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT1_LSB 0x1 -#define GC_USB_DAINT_INEPINT1_MASK 0x2 -#define GC_USB_DAINT_INEPINT1_SIZE 0x1 -#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT2_LSB 0x2 -#define GC_USB_DAINT_INEPINT2_MASK 0x4 -#define GC_USB_DAINT_INEPINT2_SIZE 0x1 -#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT3_LSB 0x3 -#define GC_USB_DAINT_INEPINT3_MASK 0x8 -#define GC_USB_DAINT_INEPINT3_SIZE 0x1 -#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT4_LSB 0x4 -#define GC_USB_DAINT_INEPINT4_MASK 0x10 -#define GC_USB_DAINT_INEPINT4_SIZE 0x1 -#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT5_LSB 0x5 -#define GC_USB_DAINT_INEPINT5_MASK 0x20 -#define GC_USB_DAINT_INEPINT5_SIZE 0x1 -#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT6_LSB 0x6 -#define GC_USB_DAINT_INEPINT6_MASK 0x40 -#define GC_USB_DAINT_INEPINT6_SIZE 0x1 -#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT7_LSB 0x7 -#define GC_USB_DAINT_INEPINT7_MASK 0x80 -#define GC_USB_DAINT_INEPINT7_SIZE 0x1 -#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT8_LSB 0x8 -#define GC_USB_DAINT_INEPINT8_MASK 0x100 -#define GC_USB_DAINT_INEPINT8_SIZE 0x1 -#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT9_LSB 0x9 -#define GC_USB_DAINT_INEPINT9_MASK 0x200 -#define GC_USB_DAINT_INEPINT9_SIZE 0x1 -#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT10_LSB 0xa -#define GC_USB_DAINT_INEPINT10_MASK 0x400 -#define GC_USB_DAINT_INEPINT10_SIZE 0x1 -#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT11_LSB 0xb -#define GC_USB_DAINT_INEPINT11_MASK 0x800 -#define GC_USB_DAINT_INEPINT11_SIZE 0x1 -#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT12_LSB 0xc -#define GC_USB_DAINT_INEPINT12_MASK 0x1000 -#define GC_USB_DAINT_INEPINT12_SIZE 0x1 -#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT13_LSB 0xd -#define GC_USB_DAINT_INEPINT13_MASK 0x2000 -#define GC_USB_DAINT_INEPINT13_SIZE 0x1 -#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT14_LSB 0xe -#define GC_USB_DAINT_INEPINT14_MASK 0x4000 -#define GC_USB_DAINT_INEPINT14_SIZE 0x1 -#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_INEPINT15_LSB 0xf -#define GC_USB_DAINT_INEPINT15_MASK 0x8000 -#define GC_USB_DAINT_INEPINT15_SIZE 0x1 -#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 -#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 -#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 -#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 -#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 -#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 -#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 -#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 -#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 -#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 -#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 -#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 -#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 -#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 -#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 -#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 -#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 -#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 -#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 -#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 -#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a -#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 -#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b -#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 -#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c -#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 -#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d -#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 -#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e -#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 -#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 -#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f -#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 -#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 -#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 -#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 -#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 -#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 -#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 -#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 -#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 -#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 -#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 -#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 -#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 -#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 -#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 -#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 -#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 -#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 -#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 -#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 -#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 -#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa -#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 -#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb -#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 -#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc -#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 -#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd -#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 -#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe -#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 -#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf -#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 -#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 -#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 -#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 -#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 -#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 -#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 -#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 -#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 -#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 -#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 -#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 -#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 -#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 -#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 -#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 -#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 -#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 -#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 -#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 -#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 -#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a -#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 -#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b -#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 -#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c -#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 -#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d -#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 -#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e -#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 -#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c -#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f -#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 -#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 -#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 -#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c -#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff -#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 -#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 -#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff -#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc -#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 -#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c -#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 -#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 -#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc -#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb -#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 -#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 -#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 -#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 -#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 -#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 -#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 -#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 -#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 -#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 -#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 -#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b -#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 -#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 -#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 -#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 -#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 -#define GC_USB_DIEPCTL0_MPS_LSB 0x0 -#define GC_USB_DIEPCTL0_MPS_MASK 0x3 -#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 -#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 -#define GC_USB_DIEPCTL0_STALL_LSB 0x15 -#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 -#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 -#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 -#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 -#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 -#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 -#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 -#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 -#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 -#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 -#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 -#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 -#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 -#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 -#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 -#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 -#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 -#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c -#define GC_USB_DIEPCTL1_MPS_LSB 0x0 -#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL1_MPS_SIZE 0xb -#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 -#define GC_USB_DIEPCTL1_DPID_LSB 0x10 -#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 -#define GC_USB_DIEPCTL1_STALL_LSB 0x15 -#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 -#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 -#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 -#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 -#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 -#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 -#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 -#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 -#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 -#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 -#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 -#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 -#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 -#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 -#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 -#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c -#define GC_USB_DIEPCTL2_MPS_LSB 0x0 -#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL2_MPS_SIZE 0xb -#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 -#define GC_USB_DIEPCTL2_DPID_LSB 0x10 -#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 -#define GC_USB_DIEPCTL2_STALL_LSB 0x15 -#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 -#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 -#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 -#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 -#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 -#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 -#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 -#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 -#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 -#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 -#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 -#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 -#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 -#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 -#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 -#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c -#define GC_USB_DIEPCTL3_MPS_LSB 0x0 -#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL3_MPS_SIZE 0xb -#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 -#define GC_USB_DIEPCTL3_DPID_LSB 0x10 -#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 -#define GC_USB_DIEPCTL3_STALL_LSB 0x15 -#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 -#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 -#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 -#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 -#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 -#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 -#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 -#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 -#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 -#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 -#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 -#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 -#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 -#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 -#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 -#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c -#define GC_USB_DIEPCTL4_MPS_LSB 0x0 -#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL4_MPS_SIZE 0xb -#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 -#define GC_USB_DIEPCTL4_DPID_LSB 0x10 -#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 -#define GC_USB_DIEPCTL4_STALL_LSB 0x15 -#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 -#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 -#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 -#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 -#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 -#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 -#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 -#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 -#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 -#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 -#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 -#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 -#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 -#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 -#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 -#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c -#define GC_USB_DIEPCTL5_MPS_LSB 0x0 -#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL5_MPS_SIZE 0xb -#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_DPID_LSB 0x10 -#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_STALL_LSB 0x15 -#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 -#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 -#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 -#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 -#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 -#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc -#define GC_USB_DIEPCTL6_MPS_LSB 0x0 -#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL6_MPS_SIZE 0xb -#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_DPID_LSB 0x10 -#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_STALL_LSB 0x15 -#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 -#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 -#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 -#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 -#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 -#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc -#define GC_USB_DIEPCTL7_MPS_LSB 0x0 -#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL7_MPS_SIZE 0xb -#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_DPID_LSB 0x10 -#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_STALL_LSB 0x15 -#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 -#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 -#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 -#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 -#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 -#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc -#define GC_USB_DIEPCTL8_MPS_LSB 0x0 -#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL8_MPS_SIZE 0xb -#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_DPID_LSB 0x10 -#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_STALL_LSB 0x15 -#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 -#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 -#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 -#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 -#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 -#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 -#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 -#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 -#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c -#define GC_USB_DIEPCTL9_MPS_LSB 0x0 -#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL9_MPS_SIZE 0xb -#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_DPID_LSB 0x10 -#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_STALL_LSB 0x15 -#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 -#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 -#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 -#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 -#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 -#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 -#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 -#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 -#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c -#define GC_USB_DIEPCTL10_MPS_LSB 0x0 -#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL10_MPS_SIZE 0xb -#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_DPID_LSB 0x10 -#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_STALL_LSB 0x15 -#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 -#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 -#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 -#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 -#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 -#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 -#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 -#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 -#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB 0xe +#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK 0xc000 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE 0x2 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT 0x0 +#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET 0x50 +#define GC_USB_GHWCFG4_NUMCTLEPS_LSB 0x10 +#define GC_USB_GHWCFG4_NUMCTLEPS_MASK 0xf0000 +#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_IDDGFLTR_LSB 0x14 +#define GC_USB_GHWCFG4_IDDGFLTR_MASK 0x100000 +#define GC_USB_GHWCFG4_IDDGFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB 0x15 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK 0x200000 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_AVALIDFLTR_LSB 0x16 +#define GC_USB_GHWCFG4_AVALIDFLTR_MASK 0x400000 +#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_BVALIDFLTR_LSB 0x17 +#define GC_USB_GHWCFG4_BVALIDFLTR_MASK 0x800000 +#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_SESSENDFLTR_LSB 0x18 +#define GC_USB_GHWCFG4_SESSENDFLTR_MASK 0x1000000 +#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE 0x1 +#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT 0x0 +#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET 0x50 +#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB 0x19 +#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK 0x2000000 +#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE 0x1 +#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET 0x50 +#define GC_USB_GHWCFG4_INEPS_LSB 0x1a +#define GC_USB_GHWCFG4_INEPS_MASK 0x3c000000 +#define GC_USB_GHWCFG4_INEPS_SIZE 0x4 +#define GC_USB_GHWCFG4_INEPS_DEFAULT 0x0 +#define GC_USB_GHWCFG4_INEPS_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB 0x1e +#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK 0x40000000 +#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET 0x50 +#define GC_USB_GHWCFG4_DESCDMA_LSB 0x1f +#define GC_USB_GHWCFG4_DESCDMA_MASK 0x80000000 +#define GC_USB_GHWCFG4_DESCDMA_SIZE 0x1 +#define GC_USB_GHWCFG4_DESCDMA_DEFAULT 0x0 +#define GC_USB_GHWCFG4_DESCDMA_OFFSET 0x50 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK 0xffff +#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE 0x10 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET 0x5c +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xffff0000 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE 0x10 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x0 +#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET 0x5c +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 +#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc +#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 +#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET 0x104 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET 0x108 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET 0x108 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET 0x10c +#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET 0x10c +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET 0x110 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET 0x110 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET 0x114 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET 0x114 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET 0x118 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET 0x118 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET 0x11c +#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET 0x11c +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET 0x120 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET 0x120 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET 0x124 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET 0x124 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET 0x128 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET 0x128 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET 0x12c +#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET 0x12c +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET 0x130 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET 0x130 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET 0x134 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET 0x134 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET 0x138 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET 0x138 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK 0x7ff +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE 0xb +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET 0x13c +#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB 0x10 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK 0x3f0000 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE 0x6 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT 0x0 +#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET 0x13c +#define GC_USB_DCFG_DEVSPD_LSB 0x0 +#define GC_USB_DCFG_DEVSPD_MASK 0x3 +#define GC_USB_DCFG_DEVSPD_SIZE 0x2 +#define GC_USB_DCFG_DEVSPD_DEFAULT 0x0 +#define GC_USB_DCFG_DEVSPD_OFFSET 0x800 +#define GC_USB_DCFG_NZSTSOUTHSHK_LSB 0x2 +#define GC_USB_DCFG_NZSTSOUTHSHK_MASK 0x4 +#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE 0x1 +#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x0 +#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET 0x800 +#define GC_USB_DCFG_ENA32KHZSUSP_LSB 0x3 +#define GC_USB_DCFG_ENA32KHZSUSP_MASK 0x8 +#define GC_USB_DCFG_ENA32KHZSUSP_SIZE 0x1 +#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT 0x0 +#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET 0x800 +#define GC_USB_DCFG_DEVADDR_LSB 0x4 +#define GC_USB_DCFG_DEVADDR_MASK 0x7f0 +#define GC_USB_DCFG_DEVADDR_SIZE 0x7 +#define GC_USB_DCFG_DEVADDR_DEFAULT 0x0 +#define GC_USB_DCFG_DEVADDR_OFFSET 0x800 +#define GC_USB_DCFG_PERFRINT_LSB 0xb +#define GC_USB_DCFG_PERFRINT_MASK 0x1800 +#define GC_USB_DCFG_PERFRINT_SIZE 0x2 +#define GC_USB_DCFG_PERFRINT_DEFAULT 0x0 +#define GC_USB_DCFG_PERFRINT_OFFSET 0x800 +#define GC_USB_DCFG_ENDEVOUTNAK_LSB 0xd +#define GC_USB_DCFG_ENDEVOUTNAK_MASK 0x2000 +#define GC_USB_DCFG_ENDEVOUTNAK_SIZE 0x1 +#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT 0x0 +#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET 0x800 +#define GC_USB_DCFG_XCVRDLY_LSB 0xe +#define GC_USB_DCFG_XCVRDLY_MASK 0x4000 +#define GC_USB_DCFG_XCVRDLY_SIZE 0x1 +#define GC_USB_DCFG_XCVRDLY_DEFAULT 0x0 +#define GC_USB_DCFG_XCVRDLY_OFFSET 0x800 +#define GC_USB_DCFG_ERRATICINTMSK_LSB 0xf +#define GC_USB_DCFG_ERRATICINTMSK_MASK 0x8000 +#define GC_USB_DCFG_ERRATICINTMSK_SIZE 0x1 +#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT 0x0 +#define GC_USB_DCFG_ERRATICINTMSK_OFFSET 0x800 +#define GC_USB_DCFG_DESCDMA_LSB 0x17 +#define GC_USB_DCFG_DESCDMA_MASK 0x800000 +#define GC_USB_DCFG_DESCDMA_SIZE 0x1 +#define GC_USB_DCFG_DESCDMA_DEFAULT 0x0 +#define GC_USB_DCFG_DESCDMA_OFFSET 0x800 +#define GC_USB_DCFG_PERSCHINTVL_LSB 0x18 +#define GC_USB_DCFG_PERSCHINTVL_MASK 0x3000000 +#define GC_USB_DCFG_PERSCHINTVL_SIZE 0x2 +#define GC_USB_DCFG_PERSCHINTVL_DEFAULT 0x0 +#define GC_USB_DCFG_PERSCHINTVL_OFFSET 0x800 +#define GC_USB_DCFG_RESVALID_LSB 0x1a +#define GC_USB_DCFG_RESVALID_MASK 0xfc000000 +#define GC_USB_DCFG_RESVALID_SIZE 0x6 +#define GC_USB_DCFG_RESVALID_DEFAULT 0x2 +#define GC_USB_DCFG_RESVALID_OFFSET 0x800 +#define GC_USB_DCTL_RMTWKUPSIG_LSB 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_MASK 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_SIZE 0x1 +#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT 0x0 +#define GC_USB_DCTL_RMTWKUPSIG_OFFSET 0x804 +#define GC_USB_DCTL_SFTDISCON_LSB 0x1 +#define GC_USB_DCTL_SFTDISCON_MASK 0x2 +#define GC_USB_DCTL_SFTDISCON_SIZE 0x1 +#define GC_USB_DCTL_SFTDISCON_DEFAULT 0x0 +#define GC_USB_DCTL_SFTDISCON_OFFSET 0x804 +#define GC_USB_DCTL_GNPINNAKSTS_LSB 0x2 +#define GC_USB_DCTL_GNPINNAKSTS_MASK 0x4 +#define GC_USB_DCTL_GNPINNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GNPINNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_GOUTNAKSTS_LSB 0x3 +#define GC_USB_DCTL_GOUTNAKSTS_MASK 0x8 +#define GC_USB_DCTL_GOUTNAKSTS_SIZE 0x1 +#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT 0x0 +#define GC_USB_DCTL_GOUTNAKSTS_OFFSET 0x804 +#define GC_USB_DCTL_TSTCTL_LSB 0x4 +#define GC_USB_DCTL_TSTCTL_MASK 0x70 +#define GC_USB_DCTL_TSTCTL_SIZE 0x3 +#define GC_USB_DCTL_TSTCTL_DEFAULT 0x0 +#define GC_USB_DCTL_TSTCTL_OFFSET 0x804 +#define GC_USB_DCTL_SGNPINNAK_LSB 0x7 +#define GC_USB_DCTL_SGNPINNAK_MASK 0x80 +#define GC_USB_DCTL_SGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_SGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGNPINNAK_LSB 0x8 +#define GC_USB_DCTL_CGNPINNAK_MASK 0x100 +#define GC_USB_DCTL_CGNPINNAK_SIZE 0x1 +#define GC_USB_DCTL_CGNPINNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGNPINNAK_OFFSET 0x804 +#define GC_USB_DCTL_SGOUTNAK_LSB 0x9 +#define GC_USB_DCTL_SGOUTNAK_MASK 0x200 +#define GC_USB_DCTL_SGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_SGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_SGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_CGOUTNAK_LSB 0xa +#define GC_USB_DCTL_CGOUTNAK_MASK 0x400 +#define GC_USB_DCTL_CGOUTNAK_SIZE 0x1 +#define GC_USB_DCTL_CGOUTNAK_DEFAULT 0x0 +#define GC_USB_DCTL_CGOUTNAK_OFFSET 0x804 +#define GC_USB_DCTL_PWRONPRGDONE_LSB 0xb +#define GC_USB_DCTL_PWRONPRGDONE_MASK 0x800 +#define GC_USB_DCTL_PWRONPRGDONE_SIZE 0x1 +#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT 0x0 +#define GC_USB_DCTL_PWRONPRGDONE_OFFSET 0x804 +#define GC_USB_DCTL_GMC_LSB 0xd +#define GC_USB_DCTL_GMC_MASK 0x6000 +#define GC_USB_DCTL_GMC_SIZE 0x2 +#define GC_USB_DCTL_GMC_DEFAULT 0x0 +#define GC_USB_DCTL_GMC_OFFSET 0x804 +#define GC_USB_DCTL_IGNRFRMNUM_LSB 0xf +#define GC_USB_DCTL_IGNRFRMNUM_MASK 0x8000 +#define GC_USB_DCTL_IGNRFRMNUM_SIZE 0x1 +#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT 0x0 +#define GC_USB_DCTL_IGNRFRMNUM_OFFSET 0x804 +#define GC_USB_DCTL_NAKONBBLE_LSB 0x10 +#define GC_USB_DCTL_NAKONBBLE_MASK 0x10000 +#define GC_USB_DCTL_NAKONBBLE_SIZE 0x1 +#define GC_USB_DCTL_NAKONBBLE_DEFAULT 0x0 +#define GC_USB_DCTL_NAKONBBLE_OFFSET 0x804 +#define GC_USB_DCTL_ENCONTONBNA_LSB 0x11 +#define GC_USB_DCTL_ENCONTONBNA_MASK 0x20000 +#define GC_USB_DCTL_ENCONTONBNA_SIZE 0x1 +#define GC_USB_DCTL_ENCONTONBNA_DEFAULT 0x0 +#define GC_USB_DCTL_ENCONTONBNA_OFFSET 0x804 +#define GC_USB_DSTS_SUSPSTS_LSB 0x0 +#define GC_USB_DSTS_SUSPSTS_MASK 0x1 +#define GC_USB_DSTS_SUSPSTS_SIZE 0x1 +#define GC_USB_DSTS_SUSPSTS_DEFAULT 0x0 +#define GC_USB_DSTS_SUSPSTS_OFFSET 0x808 +#define GC_USB_DSTS_ENUMSPD_LSB 0x1 +#define GC_USB_DSTS_ENUMSPD_MASK 0x6 +#define GC_USB_DSTS_ENUMSPD_SIZE 0x2 +#define GC_USB_DSTS_ENUMSPD_DEFAULT 0x0 +#define GC_USB_DSTS_ENUMSPD_OFFSET 0x808 +#define GC_USB_DSTS_ERRTICERR_LSB 0x3 +#define GC_USB_DSTS_ERRTICERR_MASK 0x8 +#define GC_USB_DSTS_ERRTICERR_SIZE 0x1 +#define GC_USB_DSTS_ERRTICERR_DEFAULT 0x0 +#define GC_USB_DSTS_ERRTICERR_OFFSET 0x808 +#define GC_USB_DSTS_SOFFN_LSB 0x8 +#define GC_USB_DSTS_SOFFN_MASK 0x3fff00 +#define GC_USB_DSTS_SOFFN_SIZE 0xe +#define GC_USB_DSTS_SOFFN_DEFAULT 0x0 +#define GC_USB_DSTS_SOFFN_OFFSET 0x808 +#define GC_USB_DSTS_DEVLNSTS_LSB 0x16 +#define GC_USB_DSTS_DEVLNSTS_MASK 0xc00000 +#define GC_USB_DSTS_DEVLNSTS_SIZE 0x2 +#define GC_USB_DSTS_DEVLNSTS_DEFAULT 0x0 +#define GC_USB_DSTS_DEVLNSTS_OFFSET 0x808 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DIEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DIEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB 0x3 +#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK 0x8 +#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB 0x4 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB 0x5 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK 0x20 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB 0x6 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 +#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 +#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 +#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 +#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_BNAININTRMSK_LSB 0x9 +#define GC_USB_DIEPMSK_BNAININTRMSK_MASK 0x200 +#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DIEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DIEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DIEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_NAKMSK_OFFSET 0x810 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK 0x2 +#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_AHBERRMSK_LSB 0x2 +#define GC_USB_DOEPMSK_AHBERRMSK_MASK 0x4 +#define GC_USB_DOEPMSK_AHBERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_SETUPMSK_LSB 0x3 +#define GC_USB_DOEPMSK_SETUPMSK_MASK 0x8 +#define GC_USB_DOEPMSK_SETUPMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_SETUPMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB 0x4 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB 0x5 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK 0x20 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET 0x814 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB 0x8 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB 0x9 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK 0x200 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_BBLEERRMSK_LSB 0xc +#define GC_USB_DOEPMSK_BBLEERRMSK_MASK 0x1000 +#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NAKMSK_LSB 0xd +#define GC_USB_DOEPMSK_NAKMSK_MASK 0x2000 +#define GC_USB_DOEPMSK_NAKMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NAKMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NAKMSK_OFFSET 0x814 +#define GC_USB_DOEPMSK_NYETMSK_LSB 0xe +#define GC_USB_DOEPMSK_NYETMSK_MASK 0x4000 +#define GC_USB_DOEPMSK_NYETMSK_SIZE 0x1 +#define GC_USB_DOEPMSK_NYETMSK_DEFAULT 0x0 +#define GC_USB_DOEPMSK_NYETMSK_OFFSET 0x814 +#define GC_USB_DAINT_INEPINT0_LSB 0x0 +#define GC_USB_DAINT_INEPINT0_MASK 0x1 +#define GC_USB_DAINT_INEPINT0_SIZE 0x1 +#define GC_USB_DAINT_INEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT1_LSB 0x1 +#define GC_USB_DAINT_INEPINT1_MASK 0x2 +#define GC_USB_DAINT_INEPINT1_SIZE 0x1 +#define GC_USB_DAINT_INEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT2_LSB 0x2 +#define GC_USB_DAINT_INEPINT2_MASK 0x4 +#define GC_USB_DAINT_INEPINT2_SIZE 0x1 +#define GC_USB_DAINT_INEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT3_LSB 0x3 +#define GC_USB_DAINT_INEPINT3_MASK 0x8 +#define GC_USB_DAINT_INEPINT3_SIZE 0x1 +#define GC_USB_DAINT_INEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT4_LSB 0x4 +#define GC_USB_DAINT_INEPINT4_MASK 0x10 +#define GC_USB_DAINT_INEPINT4_SIZE 0x1 +#define GC_USB_DAINT_INEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT5_LSB 0x5 +#define GC_USB_DAINT_INEPINT5_MASK 0x20 +#define GC_USB_DAINT_INEPINT5_SIZE 0x1 +#define GC_USB_DAINT_INEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT6_LSB 0x6 +#define GC_USB_DAINT_INEPINT6_MASK 0x40 +#define GC_USB_DAINT_INEPINT6_SIZE 0x1 +#define GC_USB_DAINT_INEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT7_LSB 0x7 +#define GC_USB_DAINT_INEPINT7_MASK 0x80 +#define GC_USB_DAINT_INEPINT7_SIZE 0x1 +#define GC_USB_DAINT_INEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT8_LSB 0x8 +#define GC_USB_DAINT_INEPINT8_MASK 0x100 +#define GC_USB_DAINT_INEPINT8_SIZE 0x1 +#define GC_USB_DAINT_INEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT9_LSB 0x9 +#define GC_USB_DAINT_INEPINT9_MASK 0x200 +#define GC_USB_DAINT_INEPINT9_SIZE 0x1 +#define GC_USB_DAINT_INEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT10_LSB 0xa +#define GC_USB_DAINT_INEPINT10_MASK 0x400 +#define GC_USB_DAINT_INEPINT10_SIZE 0x1 +#define GC_USB_DAINT_INEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT11_LSB 0xb +#define GC_USB_DAINT_INEPINT11_MASK 0x800 +#define GC_USB_DAINT_INEPINT11_SIZE 0x1 +#define GC_USB_DAINT_INEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT12_LSB 0xc +#define GC_USB_DAINT_INEPINT12_MASK 0x1000 +#define GC_USB_DAINT_INEPINT12_SIZE 0x1 +#define GC_USB_DAINT_INEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT13_LSB 0xd +#define GC_USB_DAINT_INEPINT13_MASK 0x2000 +#define GC_USB_DAINT_INEPINT13_SIZE 0x1 +#define GC_USB_DAINT_INEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT14_LSB 0xe +#define GC_USB_DAINT_INEPINT14_MASK 0x4000 +#define GC_USB_DAINT_INEPINT14_SIZE 0x1 +#define GC_USB_DAINT_INEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_INEPINT15_LSB 0xf +#define GC_USB_DAINT_INEPINT15_MASK 0x8000 +#define GC_USB_DAINT_INEPINT15_SIZE 0x1 +#define GC_USB_DAINT_INEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_INEPINT15_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT0_LSB 0x10 +#define GC_USB_DAINT_OUTEPINT0_MASK 0x10000 +#define GC_USB_DAINT_OUTEPINT0_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT0_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT0_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT1_LSB 0x11 +#define GC_USB_DAINT_OUTEPINT1_MASK 0x20000 +#define GC_USB_DAINT_OUTEPINT1_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT1_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT1_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT2_LSB 0x12 +#define GC_USB_DAINT_OUTEPINT2_MASK 0x40000 +#define GC_USB_DAINT_OUTEPINT2_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT2_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT2_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT3_LSB 0x13 +#define GC_USB_DAINT_OUTEPINT3_MASK 0x80000 +#define GC_USB_DAINT_OUTEPINT3_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT3_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT3_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT4_LSB 0x14 +#define GC_USB_DAINT_OUTEPINT4_MASK 0x100000 +#define GC_USB_DAINT_OUTEPINT4_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT4_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT4_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT5_LSB 0x15 +#define GC_USB_DAINT_OUTEPINT5_MASK 0x200000 +#define GC_USB_DAINT_OUTEPINT5_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT5_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT5_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT6_LSB 0x16 +#define GC_USB_DAINT_OUTEPINT6_MASK 0x400000 +#define GC_USB_DAINT_OUTEPINT6_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT6_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT6_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT7_LSB 0x17 +#define GC_USB_DAINT_OUTEPINT7_MASK 0x800000 +#define GC_USB_DAINT_OUTEPINT7_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT7_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT7_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT8_LSB 0x18 +#define GC_USB_DAINT_OUTEPINT8_MASK 0x1000000 +#define GC_USB_DAINT_OUTEPINT8_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT8_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT8_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT9_LSB 0x19 +#define GC_USB_DAINT_OUTEPINT9_MASK 0x2000000 +#define GC_USB_DAINT_OUTEPINT9_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT9_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT9_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT10_LSB 0x1a +#define GC_USB_DAINT_OUTEPINT10_MASK 0x4000000 +#define GC_USB_DAINT_OUTEPINT10_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT10_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT10_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT11_LSB 0x1b +#define GC_USB_DAINT_OUTEPINT11_MASK 0x8000000 +#define GC_USB_DAINT_OUTEPINT11_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT11_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT11_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT12_LSB 0x1c +#define GC_USB_DAINT_OUTEPINT12_MASK 0x10000000 +#define GC_USB_DAINT_OUTEPINT12_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT12_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT12_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT13_LSB 0x1d +#define GC_USB_DAINT_OUTEPINT13_MASK 0x20000000 +#define GC_USB_DAINT_OUTEPINT13_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT13_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT13_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT14_LSB 0x1e +#define GC_USB_DAINT_OUTEPINT14_MASK 0x40000000 +#define GC_USB_DAINT_OUTEPINT14_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT14_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT14_OFFSET 0x818 +#define GC_USB_DAINT_OUTEPINT15_LSB 0x1f +#define GC_USB_DAINT_OUTEPINT15_MASK 0x80000000 +#define GC_USB_DAINT_OUTEPINT15_SIZE 0x1 +#define GC_USB_DAINT_OUTEPINT15_DEFAULT 0x0 +#define GC_USB_DAINT_OUTEPINT15_OFFSET 0x818 +#define GC_USB_DAINTMSK_INEPMSK0_LSB 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_MASK 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK1_LSB 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_MASK 0x2 +#define GC_USB_DAINTMSK_INEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK2_LSB 0x2 +#define GC_USB_DAINTMSK_INEPMSK2_MASK 0x4 +#define GC_USB_DAINTMSK_INEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK3_LSB 0x3 +#define GC_USB_DAINTMSK_INEPMSK3_MASK 0x8 +#define GC_USB_DAINTMSK_INEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK4_LSB 0x4 +#define GC_USB_DAINTMSK_INEPMSK4_MASK 0x10 +#define GC_USB_DAINTMSK_INEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK5_LSB 0x5 +#define GC_USB_DAINTMSK_INEPMSK5_MASK 0x20 +#define GC_USB_DAINTMSK_INEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK6_LSB 0x6 +#define GC_USB_DAINTMSK_INEPMSK6_MASK 0x40 +#define GC_USB_DAINTMSK_INEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK7_LSB 0x7 +#define GC_USB_DAINTMSK_INEPMSK7_MASK 0x80 +#define GC_USB_DAINTMSK_INEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK8_LSB 0x8 +#define GC_USB_DAINTMSK_INEPMSK8_MASK 0x100 +#define GC_USB_DAINTMSK_INEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK9_LSB 0x9 +#define GC_USB_DAINTMSK_INEPMSK9_MASK 0x200 +#define GC_USB_DAINTMSK_INEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK10_LSB 0xa +#define GC_USB_DAINTMSK_INEPMSK10_MASK 0x400 +#define GC_USB_DAINTMSK_INEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK11_LSB 0xb +#define GC_USB_DAINTMSK_INEPMSK11_MASK 0x800 +#define GC_USB_DAINTMSK_INEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK12_LSB 0xc +#define GC_USB_DAINTMSK_INEPMSK12_MASK 0x1000 +#define GC_USB_DAINTMSK_INEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK13_LSB 0xd +#define GC_USB_DAINTMSK_INEPMSK13_MASK 0x2000 +#define GC_USB_DAINTMSK_INEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK14_LSB 0xe +#define GC_USB_DAINTMSK_INEPMSK14_MASK 0x4000 +#define GC_USB_DAINTMSK_INEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_INEPMSK15_LSB 0xf +#define GC_USB_DAINTMSK_INEPMSK15_MASK 0x8000 +#define GC_USB_DAINTMSK_INEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_INEPMSK15_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK0_LSB 0x10 +#define GC_USB_DAINTMSK_OUTEPMSK0_MASK 0x10000 +#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK1_LSB 0x11 +#define GC_USB_DAINTMSK_OUTEPMSK1_MASK 0x20000 +#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK2_LSB 0x12 +#define GC_USB_DAINTMSK_OUTEPMSK2_MASK 0x40000 +#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK3_LSB 0x13 +#define GC_USB_DAINTMSK_OUTEPMSK3_MASK 0x80000 +#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK4_LSB 0x14 +#define GC_USB_DAINTMSK_OUTEPMSK4_MASK 0x100000 +#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK5_LSB 0x15 +#define GC_USB_DAINTMSK_OUTEPMSK5_MASK 0x200000 +#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK6_LSB 0x16 +#define GC_USB_DAINTMSK_OUTEPMSK6_MASK 0x400000 +#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK7_LSB 0x17 +#define GC_USB_DAINTMSK_OUTEPMSK7_MASK 0x800000 +#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK8_LSB 0x18 +#define GC_USB_DAINTMSK_OUTEPMSK8_MASK 0x1000000 +#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK9_LSB 0x19 +#define GC_USB_DAINTMSK_OUTEPMSK9_MASK 0x2000000 +#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK10_LSB 0x1a +#define GC_USB_DAINTMSK_OUTEPMSK10_MASK 0x4000000 +#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK11_LSB 0x1b +#define GC_USB_DAINTMSK_OUTEPMSK11_MASK 0x8000000 +#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK12_LSB 0x1c +#define GC_USB_DAINTMSK_OUTEPMSK12_MASK 0x10000000 +#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK13_LSB 0x1d +#define GC_USB_DAINTMSK_OUTEPMSK13_MASK 0x20000000 +#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK14_LSB 0x1e +#define GC_USB_DAINTMSK_OUTEPMSK14_MASK 0x40000000 +#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET 0x81c +#define GC_USB_DAINTMSK_OUTEPMSK15_LSB 0x1f +#define GC_USB_DAINTMSK_OUTEPMSK15_MASK 0x80000000 +#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE 0x1 +#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT 0x0 +#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET 0x81c +#define GC_USB_DVBUSDIS_DVBUSDIS_LSB 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_MASK 0xffff +#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE 0x10 +#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x0 +#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET 0x828 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK 0xfff +#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE 0xc +#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x0 +#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET 0x82c +#define GC_USB_DTHRCTL_NONISOTHREN_LSB 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_MASK 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ISOTHREN_LSB 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_MASK 0x2 +#define GC_USB_DTHRCTL_ISOTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ISOTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_TXTHRLEN_LSB 0x2 +#define GC_USB_DTHRCTL_TXTHRLEN_MASK 0x7fc +#define GC_USB_DTHRCTL_TXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB 0xb +#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK 0x1800 +#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE 0x2 +#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT 0x0 +#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHREN_LSB 0x10 +#define GC_USB_DTHRCTL_RXTHREN_MASK 0x10000 +#define GC_USB_DTHRCTL_RXTHREN_SIZE 0x1 +#define GC_USB_DTHRCTL_RXTHREN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHREN_OFFSET 0x830 +#define GC_USB_DTHRCTL_RXTHRLEN_LSB 0x11 +#define GC_USB_DTHRCTL_RXTHRLEN_MASK 0x3fe0000 +#define GC_USB_DTHRCTL_RXTHRLEN_SIZE 0x9 +#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET 0x830 +#define GC_USB_DTHRCTL_ARBPRKEN_LSB 0x1b +#define GC_USB_DTHRCTL_ARBPRKEN_MASK 0x8000000 +#define GC_USB_DTHRCTL_ARBPRKEN_SIZE 0x1 +#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT 0x0 +#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET 0x830 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK 0xffff +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE 0x10 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT 0x0 +#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET 0x834 +#define GC_USB_DIEPCTL0_MPS_LSB 0x0 +#define GC_USB_DIEPCTL0_MPS_MASK 0x3 +#define GC_USB_DIEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DIEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_MPS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_USBACTEP_OFFSET 0x900 +#define GC_USB_DIEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_NAKSTS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPTYPE_OFFSET 0x900 +#define GC_USB_DIEPCTL0_STALL_LSB 0x15 +#define GC_USB_DIEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_STALL_OFFSET 0x900 +#define GC_USB_DIEPCTL0_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL0_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL0_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_TXFNUM_OFFSET 0x900 +#define GC_USB_DIEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_CNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_SNAK_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPDIS_OFFSET 0x900 +#define GC_USB_DIEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL0_EPENA_OFFSET 0x900 +#define GC_USB_DIEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET 0x908 +#define GC_USB_DIEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT0_EPDISBLD_OFFSET 0x908 +#define GC_USB_DIEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_AHBERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT0_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT0_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TIMEOUT_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT0_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET 0x908 +#define GC_USB_DIEPINT0_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT0_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT0_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT0_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFEMP_OFFSET 0x908 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET 0x908 +#define GC_USB_DIEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BNAINTR_OFFSET 0x908 +#define GC_USB_DIEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET 0x908 +#define GC_USB_DIEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT0_BBLEERR_OFFSET 0x908 +#define GC_USB_DIEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET 0x908 +#define GC_USB_DIEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET 0x908 +#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET 0x910 +#define GC_USB_DIEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ0_PKTCNT_MASK 0x180000 +#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE 0x2 +#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET 0x910 +#define GC_USB_DIEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA0_DMAADDR_OFFSET 0x914 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET 0x918 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET 0x91c +#define GC_USB_DIEPCTL1_MPS_LSB 0x0 +#define GC_USB_DIEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL1_MPS_SIZE 0xb +#define GC_USB_DIEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_MPS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_USBACTEP_OFFSET 0x920 +#define GC_USB_DIEPCTL1_DPID_LSB 0x10 +#define GC_USB_DIEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_DPID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_NAKSTS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPTYPE_OFFSET 0x920 +#define GC_USB_DIEPCTL1_STALL_LSB 0x15 +#define GC_USB_DIEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_STALL_OFFSET 0x920 +#define GC_USB_DIEPCTL1_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL1_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL1_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_TXFNUM_OFFSET 0x920 +#define GC_USB_DIEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_CNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SNAK_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD0PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_SETD1PID_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPDIS_OFFSET 0x920 +#define GC_USB_DIEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL1_EPENA_OFFSET 0x920 +#define GC_USB_DIEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET 0x928 +#define GC_USB_DIEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT1_EPDISBLD_OFFSET 0x928 +#define GC_USB_DIEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_AHBERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT1_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT1_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TIMEOUT_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT1_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET 0x928 +#define GC_USB_DIEPINT1_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT1_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT1_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT1_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFEMP_OFFSET 0x928 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET 0x928 +#define GC_USB_DIEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BNAINTR_OFFSET 0x928 +#define GC_USB_DIEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET 0x928 +#define GC_USB_DIEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT1_BBLEERR_OFFSET 0x928 +#define GC_USB_DIEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET 0x928 +#define GC_USB_DIEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET 0x928 +#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET 0x930 +#define GC_USB_DIEPTSIZ1_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ1_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ1_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ1_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ1_MC_OFFSET 0x930 +#define GC_USB_DIEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA1_DMAADDR_OFFSET 0x934 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET 0x938 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET 0x93c +#define GC_USB_DIEPCTL2_MPS_LSB 0x0 +#define GC_USB_DIEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL2_MPS_SIZE 0xb +#define GC_USB_DIEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_MPS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_USBACTEP_OFFSET 0x940 +#define GC_USB_DIEPCTL2_DPID_LSB 0x10 +#define GC_USB_DIEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_DPID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_NAKSTS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPTYPE_OFFSET 0x940 +#define GC_USB_DIEPCTL2_STALL_LSB 0x15 +#define GC_USB_DIEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_STALL_OFFSET 0x940 +#define GC_USB_DIEPCTL2_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL2_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL2_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_TXFNUM_OFFSET 0x940 +#define GC_USB_DIEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_CNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SNAK_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD0PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_SETD1PID_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPDIS_OFFSET 0x940 +#define GC_USB_DIEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL2_EPENA_OFFSET 0x940 +#define GC_USB_DIEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET 0x948 +#define GC_USB_DIEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT2_EPDISBLD_OFFSET 0x948 +#define GC_USB_DIEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_AHBERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT2_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT2_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TIMEOUT_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT2_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET 0x948 +#define GC_USB_DIEPINT2_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT2_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT2_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT2_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFEMP_OFFSET 0x948 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET 0x948 +#define GC_USB_DIEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BNAINTR_OFFSET 0x948 +#define GC_USB_DIEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET 0x948 +#define GC_USB_DIEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT2_BBLEERR_OFFSET 0x948 +#define GC_USB_DIEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET 0x948 +#define GC_USB_DIEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET 0x948 +#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET 0x950 +#define GC_USB_DIEPTSIZ2_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ2_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ2_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ2_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ2_MC_OFFSET 0x950 +#define GC_USB_DIEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA2_DMAADDR_OFFSET 0x954 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET 0x958 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET 0x95c +#define GC_USB_DIEPCTL3_MPS_LSB 0x0 +#define GC_USB_DIEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL3_MPS_SIZE 0xb +#define GC_USB_DIEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_MPS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_USBACTEP_OFFSET 0x960 +#define GC_USB_DIEPCTL3_DPID_LSB 0x10 +#define GC_USB_DIEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_DPID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_NAKSTS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPTYPE_OFFSET 0x960 +#define GC_USB_DIEPCTL3_STALL_LSB 0x15 +#define GC_USB_DIEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_STALL_OFFSET 0x960 +#define GC_USB_DIEPCTL3_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL3_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL3_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_TXFNUM_OFFSET 0x960 +#define GC_USB_DIEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_CNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SNAK_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD0PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_SETD1PID_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPDIS_OFFSET 0x960 +#define GC_USB_DIEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL3_EPENA_OFFSET 0x960 +#define GC_USB_DIEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET 0x968 +#define GC_USB_DIEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT3_EPDISBLD_OFFSET 0x968 +#define GC_USB_DIEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_AHBERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT3_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT3_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TIMEOUT_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT3_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET 0x968 +#define GC_USB_DIEPINT3_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT3_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT3_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT3_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFEMP_OFFSET 0x968 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET 0x968 +#define GC_USB_DIEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BNAINTR_OFFSET 0x968 +#define GC_USB_DIEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET 0x968 +#define GC_USB_DIEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT3_BBLEERR_OFFSET 0x968 +#define GC_USB_DIEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET 0x968 +#define GC_USB_DIEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET 0x968 +#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET 0x970 +#define GC_USB_DIEPTSIZ3_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ3_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ3_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ3_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ3_MC_OFFSET 0x970 +#define GC_USB_DIEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA3_DMAADDR_OFFSET 0x974 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET 0x978 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET 0x97c +#define GC_USB_DIEPCTL4_MPS_LSB 0x0 +#define GC_USB_DIEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL4_MPS_SIZE 0xb +#define GC_USB_DIEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_MPS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_USBACTEP_OFFSET 0x980 +#define GC_USB_DIEPCTL4_DPID_LSB 0x10 +#define GC_USB_DIEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_DPID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_NAKSTS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPTYPE_OFFSET 0x980 +#define GC_USB_DIEPCTL4_STALL_LSB 0x15 +#define GC_USB_DIEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_STALL_OFFSET 0x980 +#define GC_USB_DIEPCTL4_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL4_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL4_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_TXFNUM_OFFSET 0x980 +#define GC_USB_DIEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_CNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SNAK_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD0PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_SETD1PID_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPDIS_OFFSET 0x980 +#define GC_USB_DIEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL4_EPENA_OFFSET 0x980 +#define GC_USB_DIEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET 0x988 +#define GC_USB_DIEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT4_EPDISBLD_OFFSET 0x988 +#define GC_USB_DIEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_AHBERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT4_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT4_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TIMEOUT_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT4_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET 0x988 +#define GC_USB_DIEPINT4_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT4_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT4_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT4_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFEMP_OFFSET 0x988 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET 0x988 +#define GC_USB_DIEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BNAINTR_OFFSET 0x988 +#define GC_USB_DIEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET 0x988 +#define GC_USB_DIEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT4_BBLEERR_OFFSET 0x988 +#define GC_USB_DIEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET 0x988 +#define GC_USB_DIEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET 0x988 +#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET 0x990 +#define GC_USB_DIEPTSIZ4_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ4_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ4_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ4_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ4_MC_OFFSET 0x990 +#define GC_USB_DIEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA4_DMAADDR_OFFSET 0x994 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET 0x998 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET 0x99c +#define GC_USB_DIEPCTL5_MPS_LSB 0x0 +#define GC_USB_DIEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL5_MPS_SIZE 0xb +#define GC_USB_DIEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_MPS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_USBACTEP_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_DPID_LSB 0x10 +#define GC_USB_DIEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_DPID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_NAKSTS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPTYPE_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_STALL_LSB 0x15 +#define GC_USB_DIEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_STALL_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL5_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL5_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_TXFNUM_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_CNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SNAK_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD0PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_SETD1PID_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPDIS_OFFSET 0x9a0 +#define GC_USB_DIEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL5_EPENA_OFFSET 0x9a0 +#define GC_USB_DIEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT5_EPDISBLD_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_AHBERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT5_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT5_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TIMEOUT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT5_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT5_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT5_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT5_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFEMP_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BNAINTR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT5_BBLEERR_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET 0x9a8 +#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET 0x9b0 +#define GC_USB_DIEPTSIZ5_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ5_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ5_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ5_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ5_MC_OFFSET 0x9b0 +#define GC_USB_DIEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA5_DMAADDR_OFFSET 0x9b4 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET 0x9b8 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET 0x9bc +#define GC_USB_DIEPCTL6_MPS_LSB 0x0 +#define GC_USB_DIEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL6_MPS_SIZE 0xb +#define GC_USB_DIEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_MPS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_USBACTEP_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_DPID_LSB 0x10 +#define GC_USB_DIEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_DPID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_NAKSTS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPTYPE_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_STALL_LSB 0x15 +#define GC_USB_DIEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_STALL_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL6_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL6_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_TXFNUM_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_CNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SNAK_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD0PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_SETD1PID_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPDIS_OFFSET 0x9c0 +#define GC_USB_DIEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL6_EPENA_OFFSET 0x9c0 +#define GC_USB_DIEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT6_EPDISBLD_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_AHBERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT6_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT6_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TIMEOUT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT6_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT6_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT6_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT6_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFEMP_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BNAINTR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT6_BBLEERR_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET 0x9c8 +#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET 0x9d0 +#define GC_USB_DIEPTSIZ6_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ6_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ6_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ6_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ6_MC_OFFSET 0x9d0 +#define GC_USB_DIEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA6_DMAADDR_OFFSET 0x9d4 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET 0x9d8 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET 0x9dc +#define GC_USB_DIEPCTL7_MPS_LSB 0x0 +#define GC_USB_DIEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL7_MPS_SIZE 0xb +#define GC_USB_DIEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_MPS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_USBACTEP_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_DPID_LSB 0x10 +#define GC_USB_DIEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_DPID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_NAKSTS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPTYPE_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_STALL_LSB 0x15 +#define GC_USB_DIEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_STALL_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL7_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL7_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_TXFNUM_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_CNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SNAK_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD0PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_SETD1PID_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPDIS_OFFSET 0x9e0 +#define GC_USB_DIEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL7_EPENA_OFFSET 0x9e0 +#define GC_USB_DIEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT7_EPDISBLD_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_AHBERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT7_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT7_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TIMEOUT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT7_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT7_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT7_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT7_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFEMP_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BNAINTR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT7_BBLEERR_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET 0x9e8 +#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET 0x9f0 +#define GC_USB_DIEPTSIZ7_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ7_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ7_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ7_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ7_MC_OFFSET 0x9f0 +#define GC_USB_DIEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA7_DMAADDR_OFFSET 0x9f4 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET 0x9f8 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET 0x9fc +#define GC_USB_DIEPCTL8_MPS_LSB 0x0 +#define GC_USB_DIEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL8_MPS_SIZE 0xb +#define GC_USB_DIEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_MPS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_USBACTEP_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_DPID_LSB 0x10 +#define GC_USB_DIEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_DPID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_NAKSTS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPTYPE_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_STALL_LSB 0x15 +#define GC_USB_DIEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_STALL_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL8_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL8_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_TXFNUM_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_CNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SNAK_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD0PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_SETD1PID_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPDIS_OFFSET 0xa00 +#define GC_USB_DIEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL8_EPENA_OFFSET 0xa00 +#define GC_USB_DIEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET 0xa08 +#define GC_USB_DIEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT8_EPDISBLD_OFFSET 0xa08 +#define GC_USB_DIEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_AHBERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT8_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT8_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TIMEOUT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT8_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT8_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT8_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT8_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFEMP_OFFSET 0xa08 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BNAINTR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET 0xa08 +#define GC_USB_DIEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT8_BBLEERR_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET 0xa08 +#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET 0xa10 +#define GC_USB_DIEPTSIZ8_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ8_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ8_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ8_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ8_MC_OFFSET 0xa10 +#define GC_USB_DIEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA8_DMAADDR_OFFSET 0xa14 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET 0xa18 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET 0xa1c +#define GC_USB_DIEPCTL9_MPS_LSB 0x0 +#define GC_USB_DIEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL9_MPS_SIZE 0xb +#define GC_USB_DIEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_MPS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_USBACTEP_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_DPID_LSB 0x10 +#define GC_USB_DIEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_DPID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_NAKSTS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPTYPE_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_STALL_LSB 0x15 +#define GC_USB_DIEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_STALL_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL9_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL9_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_TXFNUM_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_CNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SNAK_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD0PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_SETD1PID_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPDIS_OFFSET 0xa20 +#define GC_USB_DIEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL9_EPENA_OFFSET 0xa20 +#define GC_USB_DIEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET 0xa28 +#define GC_USB_DIEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT9_EPDISBLD_OFFSET 0xa28 +#define GC_USB_DIEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_AHBERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT9_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT9_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TIMEOUT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT9_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT9_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT9_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT9_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFEMP_OFFSET 0xa28 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BNAINTR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET 0xa28 +#define GC_USB_DIEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT9_BBLEERR_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET 0xa28 +#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET 0xa30 +#define GC_USB_DIEPTSIZ9_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ9_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ9_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ9_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ9_MC_OFFSET 0xa30 +#define GC_USB_DIEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA9_DMAADDR_OFFSET 0xa34 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT 0x0 +#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET 0xa38 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET 0xa3c +#define GC_USB_DIEPCTL10_MPS_LSB 0x0 +#define GC_USB_DIEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL10_MPS_SIZE 0xb +#define GC_USB_DIEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_MPS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_USBACTEP_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_DPID_LSB 0x10 +#define GC_USB_DIEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_DPID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_NAKSTS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPTYPE_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_STALL_LSB 0x15 +#define GC_USB_DIEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_STALL_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL10_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL10_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_TXFNUM_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_CNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SNAK_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD0PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_SETD1PID_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPDIS_OFFSET 0xa40 +#define GC_USB_DIEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL10_EPENA_OFFSET 0xa40 +#define GC_USB_DIEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET 0xa48 +#define GC_USB_DIEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT10_EPDISBLD_OFFSET 0xa48 +#define GC_USB_DIEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_AHBERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT10_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT10_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TIMEOUT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT10_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT10_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT10_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT10_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFEMP_OFFSET 0xa48 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BNAINTR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET 0xa48 +#define GC_USB_DIEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT10_BBLEERR_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET 0xa48 +#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET 0xa50 +#define GC_USB_DIEPTSIZ10_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ10_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ10_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ10_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ10_MC_OFFSET 0xa50 +#define GC_USB_DIEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA10_DMAADDR_OFFSET 0xa54 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c -#define GC_USB_DIEPCTL11_MPS_LSB 0x0 -#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL11_MPS_SIZE 0xb -#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_DPID_LSB 0x10 -#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_STALL_LSB 0x15 -#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 -#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 -#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 -#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 -#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 -#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 -#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 -#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 -#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET 0xa58 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET 0xa5c +#define GC_USB_DIEPCTL11_MPS_LSB 0x0 +#define GC_USB_DIEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL11_MPS_SIZE 0xb +#define GC_USB_DIEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_MPS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_USBACTEP_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_DPID_LSB 0x10 +#define GC_USB_DIEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_DPID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_NAKSTS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPTYPE_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_STALL_LSB 0x15 +#define GC_USB_DIEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_STALL_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL11_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL11_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_TXFNUM_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_CNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SNAK_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD0PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_SETD1PID_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPDIS_OFFSET 0xa60 +#define GC_USB_DIEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL11_EPENA_OFFSET 0xa60 +#define GC_USB_DIEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET 0xa68 +#define GC_USB_DIEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT11_EPDISBLD_OFFSET 0xa68 +#define GC_USB_DIEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_AHBERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT11_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT11_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TIMEOUT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT11_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT11_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT11_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT11_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFEMP_OFFSET 0xa68 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BNAINTR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET 0xa68 +#define GC_USB_DIEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT11_BBLEERR_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET 0xa68 +#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET 0xa70 +#define GC_USB_DIEPTSIZ11_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ11_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ11_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ11_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ11_MC_OFFSET 0xa70 +#define GC_USB_DIEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA11_DMAADDR_OFFSET 0xa74 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c -#define GC_USB_DIEPCTL12_MPS_LSB 0x0 -#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL12_MPS_SIZE 0xb -#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_DPID_LSB 0x10 -#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_STALL_LSB 0x15 -#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 -#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 -#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 -#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 -#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 -#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 -#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 -#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 -#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET 0xa78 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET 0xa7c +#define GC_USB_DIEPCTL12_MPS_LSB 0x0 +#define GC_USB_DIEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL12_MPS_SIZE 0xb +#define GC_USB_DIEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_MPS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_USBACTEP_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_DPID_LSB 0x10 +#define GC_USB_DIEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_DPID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_NAKSTS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPTYPE_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_STALL_LSB 0x15 +#define GC_USB_DIEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_STALL_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL12_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL12_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_TXFNUM_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_CNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SNAK_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD0PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_SETD1PID_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPDIS_OFFSET 0xa80 +#define GC_USB_DIEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL12_EPENA_OFFSET 0xa80 +#define GC_USB_DIEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET 0xa88 +#define GC_USB_DIEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT12_EPDISBLD_OFFSET 0xa88 +#define GC_USB_DIEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_AHBERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT12_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT12_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TIMEOUT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT12_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT12_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT12_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT12_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFEMP_OFFSET 0xa88 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BNAINTR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET 0xa88 +#define GC_USB_DIEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT12_BBLEERR_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET 0xa88 +#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET 0xa90 +#define GC_USB_DIEPTSIZ12_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ12_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ12_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ12_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ12_MC_OFFSET 0xa90 +#define GC_USB_DIEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA12_DMAADDR_OFFSET 0xa94 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c -#define GC_USB_DIEPCTL13_MPS_LSB 0x0 -#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL13_MPS_SIZE 0xb -#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_DPID_LSB 0x10 -#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_STALL_LSB 0x15 -#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 -#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 -#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 -#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 -#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 -#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET 0xa98 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET 0xa9c +#define GC_USB_DIEPCTL13_MPS_LSB 0x0 +#define GC_USB_DIEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL13_MPS_SIZE 0xb +#define GC_USB_DIEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_MPS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_USBACTEP_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_DPID_LSB 0x10 +#define GC_USB_DIEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_DPID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_NAKSTS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPTYPE_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_STALL_LSB 0x15 +#define GC_USB_DIEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_STALL_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL13_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL13_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_TXFNUM_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_CNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SNAK_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD0PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_SETD1PID_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPDIS_OFFSET 0xaa0 +#define GC_USB_DIEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL13_EPENA_OFFSET 0xaa0 +#define GC_USB_DIEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT13_EPDISBLD_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_AHBERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT13_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT13_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TIMEOUT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT13_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT13_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT13_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT13_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFEMP_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BNAINTR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT13_BBLEERR_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET 0xaa8 +#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET 0xab0 +#define GC_USB_DIEPTSIZ13_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ13_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ13_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ13_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ13_MC_OFFSET 0xab0 +#define GC_USB_DIEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA13_DMAADDR_OFFSET 0xab4 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc -#define GC_USB_DIEPCTL14_MPS_LSB 0x0 -#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL14_MPS_SIZE 0xb -#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_DPID_LSB 0x10 -#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_STALL_LSB 0x15 -#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 -#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 -#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 -#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 -#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 -#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 -#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 -#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 -#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET 0xab8 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET 0xabc +#define GC_USB_DIEPCTL14_MPS_LSB 0x0 +#define GC_USB_DIEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL14_MPS_SIZE 0xb +#define GC_USB_DIEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_MPS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_USBACTEP_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_DPID_LSB 0x10 +#define GC_USB_DIEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_DPID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_NAKSTS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPTYPE_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_STALL_LSB 0x15 +#define GC_USB_DIEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_STALL_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL14_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL14_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_TXFNUM_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_CNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SNAK_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD0PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_SETD1PID_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPDIS_OFFSET 0xac0 +#define GC_USB_DIEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL14_EPENA_OFFSET 0xac0 +#define GC_USB_DIEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET 0xac8 +#define GC_USB_DIEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT14_EPDISBLD_OFFSET 0xac8 +#define GC_USB_DIEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_AHBERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT14_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT14_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TIMEOUT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT14_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT14_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT14_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT14_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFEMP_OFFSET 0xac8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BNAINTR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET 0xac8 +#define GC_USB_DIEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT14_BBLEERR_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET 0xac8 +#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET 0xad0 +#define GC_USB_DIEPTSIZ14_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ14_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ14_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ14_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ14_MC_OFFSET 0xad0 +#define GC_USB_DIEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA14_DMAADDR_OFFSET 0xad4 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc -#define GC_USB_DIEPCTL15_MPS_LSB 0x0 -#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DIEPCTL15_MPS_SIZE 0xb -#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_DPID_LSB 0x10 -#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_STALL_LSB 0x15 -#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 -#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 -#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 -#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 -#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 -#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 -#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 -#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 -#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 -#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 -#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 -#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 -#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 -#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 -#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 -#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 -#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 -#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 -#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 -#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 -#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 -#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 -#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 -#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 -#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 -#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d -#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 -#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 -#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 -#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 -#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 +#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET 0xad8 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET 0xadc +#define GC_USB_DIEPCTL15_MPS_LSB 0x0 +#define GC_USB_DIEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DIEPCTL15_MPS_SIZE 0xb +#define GC_USB_DIEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_MPS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DIEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DIEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_USBACTEP_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_DPID_LSB 0x10 +#define GC_USB_DIEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DIEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DIEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_DPID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DIEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DIEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_NAKSTS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DIEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DIEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPTYPE_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_STALL_LSB 0x15 +#define GC_USB_DIEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DIEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DIEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_STALL_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_TXFNUM_LSB 0x16 +#define GC_USB_DIEPCTL15_TXFNUM_MASK 0x3c00000 +#define GC_USB_DIEPCTL15_TXFNUM_SIZE 0x4 +#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_TXFNUM_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DIEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DIEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_CNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DIEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DIEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DIEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SNAK_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DIEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DIEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD0PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DIEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DIEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_SETD1PID_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DIEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DIEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPDIS_OFFSET 0xae0 +#define GC_USB_DIEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DIEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DIEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DIEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DIEPCTL15_EPENA_OFFSET 0xae0 +#define GC_USB_DIEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET 0xae8 +#define GC_USB_DIEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DIEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DIEPINT15_EPDISBLD_OFFSET 0xae8 +#define GC_USB_DIEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DIEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DIEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DIEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_AHBERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TIMEOUT_LSB 0x3 +#define GC_USB_DIEPINT15_TIMEOUT_MASK 0x8 +#define GC_USB_DIEPINT15_TIMEOUT_SIZE 0x1 +#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TIMEOUT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB 0x4 +#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK 0x10 +#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INTKNEPMIS_LSB 0x5 +#define GC_USB_DIEPINT15_INTKNEPMIS_MASK 0x20 +#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE 0x1 +#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_INEPNAKEFF_LSB 0x6 +#define GC_USB_DIEPINT15_INEPNAKEFF_MASK 0x40 +#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE 0x1 +#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT 0x0 +#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFEMP_LSB 0x7 +#define GC_USB_DIEPINT15_TXFEMP_MASK 0x80 +#define GC_USB_DIEPINT15_TXFEMP_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFEMP_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFEMP_OFFSET 0xae8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB 0x8 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK 0x100 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE 0x1 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT 0x0 +#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DIEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DIEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DIEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BNAINTR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DIEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET 0xae8 +#define GC_USB_DIEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DIEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DIEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DIEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DIEPINT15_BBLEERR_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DIEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DIEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DIEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DIEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET 0xae8 +#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DIEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET 0xaf0 +#define GC_USB_DIEPTSIZ15_MC_LSB 0x1d +#define GC_USB_DIEPTSIZ15_MC_MASK 0x60000000 +#define GC_USB_DIEPTSIZ15_MC_SIZE 0x2 +#define GC_USB_DIEPTSIZ15_MC_DEFAULT 0x0 +#define GC_USB_DIEPTSIZ15_MC_OFFSET 0xaf0 +#define GC_USB_DIEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DIEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMA15_DMAADDR_OFFSET 0xaf4 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB 0x0 +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK 0xffff +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE 0x10 #define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0 -#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc -#define GC_USB_DOEPCTL0_MPS_LSB 0x0 -#define GC_USB_DOEPCTL0_MPS_MASK 0x3 -#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 -#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNP_LSB 0x14 -#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_STALL_LSB 0x15 -#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 -#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 -#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 -#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_SETUP_LSB 0x3 -#define GC_USB_DOEPINT0_SETUP_MASK 0x8 -#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 -#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 -#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 -#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 -#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f -#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 -#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 -#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 -#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 -#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d -#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 -#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 -#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 -#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c -#define GC_USB_DOEPCTL1_MPS_LSB 0x0 -#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL1_MPS_SIZE 0xb -#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_DPID_LSB 0x10 -#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNP_LSB 0x14 -#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_STALL_LSB 0x15 -#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 -#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 -#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 -#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_SETUP_LSB 0x3 -#define GC_USB_DOEPINT1_SETUP_MASK 0x8 -#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 -#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 -#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 -#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 -#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 -#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 -#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c -#define GC_USB_DOEPCTL2_MPS_LSB 0x0 -#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL2_MPS_SIZE 0xb -#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_DPID_LSB 0x10 -#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNP_LSB 0x14 -#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_STALL_LSB 0x15 -#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 -#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 -#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 -#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_SETUP_LSB 0x3 -#define GC_USB_DOEPINT2_SETUP_MASK 0x8 -#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 -#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 -#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 -#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 -#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 -#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 -#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c -#define GC_USB_DOEPCTL3_MPS_LSB 0x0 -#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL3_MPS_SIZE 0xb -#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_DPID_LSB 0x10 -#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNP_LSB 0x14 -#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_STALL_LSB 0x15 -#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 -#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 -#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 -#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_SETUP_LSB 0x3 -#define GC_USB_DOEPINT3_SETUP_MASK 0x8 -#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 -#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 -#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 -#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 -#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 -#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 -#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c -#define GC_USB_DOEPCTL4_MPS_LSB 0x0 -#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL4_MPS_SIZE 0xb -#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_DPID_LSB 0x10 -#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNP_LSB 0x14 -#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_STALL_LSB 0x15 -#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 -#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 -#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 -#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_SETUP_LSB 0x3 -#define GC_USB_DOEPINT4_SETUP_MASK 0x8 -#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 -#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 -#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 -#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 -#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 -#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 -#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c -#define GC_USB_DOEPCTL5_MPS_LSB 0x0 -#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL5_MPS_SIZE 0xb -#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_DPID_LSB 0x10 -#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNP_LSB 0x14 -#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_STALL_LSB 0x15 -#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 -#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 -#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 -#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_SETUP_LSB 0x3 -#define GC_USB_DOEPINT5_SETUP_MASK 0x8 -#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 -#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 -#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 -#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 -#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 -#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 -#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc -#define GC_USB_DOEPCTL6_MPS_LSB 0x0 -#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL6_MPS_SIZE 0xb -#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_DPID_LSB 0x10 -#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNP_LSB 0x14 -#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_STALL_LSB 0x15 -#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 -#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 -#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_SETUP_LSB 0x3 -#define GC_USB_DOEPINT6_SETUP_MASK 0x8 -#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 -#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 -#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 -#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 -#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc -#define GC_USB_DOEPCTL7_MPS_LSB 0x0 -#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL7_MPS_SIZE 0xb -#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_DPID_LSB 0x10 -#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNP_LSB 0x14 -#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_STALL_LSB 0x15 -#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 -#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 -#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_SETUP_LSB 0x3 -#define GC_USB_DOEPINT7_SETUP_MASK 0x8 -#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 -#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 -#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 -#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 -#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc -#define GC_USB_DOEPCTL8_MPS_LSB 0x0 -#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL8_MPS_SIZE 0xb -#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_DPID_LSB 0x10 -#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNP_LSB 0x14 -#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_STALL_LSB 0x15 -#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 -#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 -#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 -#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_SETUP_LSB 0x3 -#define GC_USB_DOEPINT8_SETUP_MASK 0x8 -#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 -#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 -#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 -#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 -#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 -#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 -#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c -#define GC_USB_DOEPCTL9_MPS_LSB 0x0 -#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL9_MPS_SIZE 0xb -#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_DPID_LSB 0x10 -#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNP_LSB 0x14 -#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_STALL_LSB 0x15 -#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 -#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 -#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 -#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_SETUP_LSB 0x3 -#define GC_USB_DOEPINT9_SETUP_MASK 0x8 -#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 -#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 -#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 -#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 -#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 -#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 -#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c -#define GC_USB_DOEPCTL10_MPS_LSB 0x0 -#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL10_MPS_SIZE 0xb -#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_DPID_LSB 0x10 -#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNP_LSB 0x14 -#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_STALL_LSB 0x15 -#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 -#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 -#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 -#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_SETUP_LSB 0x3 -#define GC_USB_DOEPINT10_SETUP_MASK 0x8 -#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 -#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 -#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 -#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 -#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 -#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 -#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c -#define GC_USB_DOEPCTL11_MPS_LSB 0x0 -#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL11_MPS_SIZE 0xb -#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_DPID_LSB 0x10 -#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNP_LSB 0x14 -#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_STALL_LSB 0x15 -#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 -#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 -#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 -#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_SETUP_LSB 0x3 -#define GC_USB_DOEPINT11_SETUP_MASK 0x8 -#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 -#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 -#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 -#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 -#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 -#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 -#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c -#define GC_USB_DOEPCTL12_MPS_LSB 0x0 -#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL12_MPS_SIZE 0xb -#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_DPID_LSB 0x10 -#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNP_LSB 0x14 -#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_STALL_LSB 0x15 -#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 -#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 -#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 -#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_SETUP_LSB 0x3 -#define GC_USB_DOEPINT12_SETUP_MASK 0x8 -#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 -#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 -#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 -#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 -#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 -#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 -#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c -#define GC_USB_DOEPCTL13_MPS_LSB 0x0 -#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL13_MPS_SIZE 0xb -#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_DPID_LSB 0x10 -#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNP_LSB 0x14 -#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_STALL_LSB 0x15 -#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 -#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 -#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 -#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_SETUP_LSB 0x3 -#define GC_USB_DOEPINT13_SETUP_MASK 0x8 -#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 -#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 -#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 -#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 -#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 -#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 -#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc -#define GC_USB_DOEPCTL14_MPS_LSB 0x0 -#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL14_MPS_SIZE 0xb -#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_DPID_LSB 0x10 -#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNP_LSB 0x14 -#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_STALL_LSB 0x15 -#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 -#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 -#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_SETUP_LSB 0x3 -#define GC_USB_DOEPINT14_SETUP_MASK 0x8 -#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 -#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 -#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 -#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 -#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc -#define GC_USB_DOEPCTL15_MPS_LSB 0x0 -#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff -#define GC_USB_DOEPCTL15_MPS_SIZE 0xb -#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf -#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 -#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 -#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_DPID_LSB 0x10 -#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 -#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 -#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 -#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 -#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 -#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 -#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 -#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 -#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNP_LSB 0x14 -#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 -#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_STALL_LSB 0x15 -#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 -#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 -#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a -#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 -#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b -#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 -#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 -#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c -#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 -#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d -#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 -#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 -#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e -#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 -#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 -#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f -#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 -#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 -#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 -#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 -#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 -#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 -#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 -#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 -#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 -#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 -#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 -#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 -#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_SETUP_LSB 0x3 -#define GC_USB_DOEPINT15_SETUP_MASK 0x8 -#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 -#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 -#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 -#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 -#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 -#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 -#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 -#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 -#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 -#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb -#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 -#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 -#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 -#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 -#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc -#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 -#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 -#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 -#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd -#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 -#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe -#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 -#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 -#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 -#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 -#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf -#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 -#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 -#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 -#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 -#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff -#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 -#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 -#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 -#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa -#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 -#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d -#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 -#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 -#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 -#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 -#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff -#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 -#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 -#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc -#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 -#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 -#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 -#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 -#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 -#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 -#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 -#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 -#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 -#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 -#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 -#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 -#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 -#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 -#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 -#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 -#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 -#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 -#define GC_USB_DFIFO_SIZE 0x1000 - +#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET 0xaf8 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET 0xafc +#define GC_USB_DOEPCTL0_MPS_LSB 0x0 +#define GC_USB_DOEPCTL0_MPS_MASK 0x3 +#define GC_USB_DOEPCTL0_MPS_SIZE 0x2 +#define GC_USB_DOEPCTL0_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_MPS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL0_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL0_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_USBACTEP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL0_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL0_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_NAKSTS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL0_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL0_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPTYPE_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNP_LSB 0x14 +#define GC_USB_DOEPCTL0_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL0_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNP_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_STALL_LSB 0x15 +#define GC_USB_DOEPCTL0_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL0_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL0_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_STALL_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL0_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL0_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_CNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL0_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL0_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL0_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_SNAK_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL0_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL0_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPDIS_OFFSET 0xb00 +#define GC_USB_DOEPCTL0_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL0_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL0_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL0_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL0_EPENA_OFFSET 0xb00 +#define GC_USB_DOEPINT0_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET 0xb08 +#define GC_USB_DOEPINT0_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT0_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_EPDISBLD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT0_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT0_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT0_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_AHBERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_SETUP_LSB 0x3 +#define GC_USB_DOEPINT0_SETUP_MASK 0x8 +#define GC_USB_DOEPINT0_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_SETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT0_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET 0xb08 +#define GC_USB_DOEPINT0_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT0_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT0_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT0_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT0_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT0_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BNAINTR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT0_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET 0xb08 +#define GC_USB_DOEPINT0_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT0_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT0_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT0_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT0_BBLEERR_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT0_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT0_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT0_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT0_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET 0xb08 +#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET 0xb08 +#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK 0x7f +#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE 0x7 +#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ0_PKTCNT_MASK 0x80000 +#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE 0x1 +#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET 0xb10 +#define GC_USB_DOEPTSIZ0_SUPCNT_LSB 0x1d +#define GC_USB_DOEPTSIZ0_SUPCNT_MASK 0x60000000 +#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE 0x2 +#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET 0xb10 +#define GC_USB_DOEPDMA0_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA0_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA0_DMAADDR_OFFSET 0xb14 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET 0xb1c +#define GC_USB_DOEPCTL1_MPS_LSB 0x0 +#define GC_USB_DOEPCTL1_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL1_MPS_SIZE 0xb +#define GC_USB_DOEPCTL1_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_MPS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL1_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL1_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_USBACTEP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_DPID_LSB 0x10 +#define GC_USB_DOEPCTL1_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL1_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL1_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_DPID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL1_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL1_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_NAKSTS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL1_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL1_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPTYPE_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNP_LSB 0x14 +#define GC_USB_DOEPCTL1_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL1_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNP_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_STALL_LSB 0x15 +#define GC_USB_DOEPCTL1_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL1_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL1_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_STALL_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL1_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL1_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_CNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL1_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL1_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL1_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SNAK_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL1_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL1_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD0PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL1_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL1_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_SETD1PID_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL1_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL1_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPDIS_OFFSET 0xb20 +#define GC_USB_DOEPCTL1_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL1_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL1_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL1_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL1_EPENA_OFFSET 0xb20 +#define GC_USB_DOEPINT1_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET 0xb28 +#define GC_USB_DOEPINT1_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT1_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_EPDISBLD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT1_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT1_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT1_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_AHBERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_SETUP_LSB 0x3 +#define GC_USB_DOEPINT1_SETUP_MASK 0x8 +#define GC_USB_DOEPINT1_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_SETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT1_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET 0xb28 +#define GC_USB_DOEPINT1_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT1_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT1_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT1_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT1_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT1_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BNAINTR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT1_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET 0xb28 +#define GC_USB_DOEPINT1_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT1_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT1_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT1_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT1_BBLEERR_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT1_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT1_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT1_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT1_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET 0xb28 +#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET 0xb28 +#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ1_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET 0xb30 +#define GC_USB_DOEPTSIZ1_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ1_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ1_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET 0xb30 +#define GC_USB_DOEPDMA1_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA1_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA1_DMAADDR_OFFSET 0xb34 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET 0xb3c +#define GC_USB_DOEPCTL2_MPS_LSB 0x0 +#define GC_USB_DOEPCTL2_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL2_MPS_SIZE 0xb +#define GC_USB_DOEPCTL2_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_MPS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL2_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL2_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_USBACTEP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_DPID_LSB 0x10 +#define GC_USB_DOEPCTL2_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL2_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL2_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_DPID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL2_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL2_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_NAKSTS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL2_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL2_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPTYPE_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNP_LSB 0x14 +#define GC_USB_DOEPCTL2_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL2_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNP_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_STALL_LSB 0x15 +#define GC_USB_DOEPCTL2_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL2_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL2_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_STALL_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL2_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL2_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_CNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL2_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL2_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL2_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SNAK_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL2_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL2_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD0PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL2_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL2_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_SETD1PID_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL2_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL2_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPDIS_OFFSET 0xb40 +#define GC_USB_DOEPCTL2_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL2_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL2_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL2_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL2_EPENA_OFFSET 0xb40 +#define GC_USB_DOEPINT2_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET 0xb48 +#define GC_USB_DOEPINT2_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT2_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_EPDISBLD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT2_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT2_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT2_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_AHBERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_SETUP_LSB 0x3 +#define GC_USB_DOEPINT2_SETUP_MASK 0x8 +#define GC_USB_DOEPINT2_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_SETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT2_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET 0xb48 +#define GC_USB_DOEPINT2_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT2_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT2_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT2_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT2_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT2_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BNAINTR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT2_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET 0xb48 +#define GC_USB_DOEPINT2_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT2_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT2_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT2_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT2_BBLEERR_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT2_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT2_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT2_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT2_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET 0xb48 +#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET 0xb48 +#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ2_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET 0xb50 +#define GC_USB_DOEPTSIZ2_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ2_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ2_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET 0xb50 +#define GC_USB_DOEPDMA2_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA2_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA2_DMAADDR_OFFSET 0xb54 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET 0xb5c +#define GC_USB_DOEPCTL3_MPS_LSB 0x0 +#define GC_USB_DOEPCTL3_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL3_MPS_SIZE 0xb +#define GC_USB_DOEPCTL3_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_MPS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL3_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL3_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_USBACTEP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_DPID_LSB 0x10 +#define GC_USB_DOEPCTL3_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL3_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL3_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_DPID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL3_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL3_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_NAKSTS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL3_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL3_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPTYPE_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNP_LSB 0x14 +#define GC_USB_DOEPCTL3_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL3_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNP_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_STALL_LSB 0x15 +#define GC_USB_DOEPCTL3_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL3_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL3_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_STALL_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL3_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL3_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_CNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL3_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL3_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL3_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SNAK_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL3_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL3_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD0PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL3_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL3_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_SETD1PID_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL3_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL3_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPDIS_OFFSET 0xb60 +#define GC_USB_DOEPCTL3_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL3_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL3_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL3_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL3_EPENA_OFFSET 0xb60 +#define GC_USB_DOEPINT3_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET 0xb68 +#define GC_USB_DOEPINT3_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT3_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_EPDISBLD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT3_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT3_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT3_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_AHBERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_SETUP_LSB 0x3 +#define GC_USB_DOEPINT3_SETUP_MASK 0x8 +#define GC_USB_DOEPINT3_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_SETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT3_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET 0xb68 +#define GC_USB_DOEPINT3_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT3_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT3_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT3_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT3_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT3_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BNAINTR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT3_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET 0xb68 +#define GC_USB_DOEPINT3_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT3_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT3_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT3_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT3_BBLEERR_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT3_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT3_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT3_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT3_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET 0xb68 +#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET 0xb68 +#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ3_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET 0xb70 +#define GC_USB_DOEPTSIZ3_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ3_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ3_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET 0xb70 +#define GC_USB_DOEPDMA3_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA3_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA3_DMAADDR_OFFSET 0xb74 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET 0xb7c +#define GC_USB_DOEPCTL4_MPS_LSB 0x0 +#define GC_USB_DOEPCTL4_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL4_MPS_SIZE 0xb +#define GC_USB_DOEPCTL4_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_MPS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL4_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL4_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_USBACTEP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_DPID_LSB 0x10 +#define GC_USB_DOEPCTL4_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL4_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL4_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_DPID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL4_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL4_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_NAKSTS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL4_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL4_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPTYPE_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNP_LSB 0x14 +#define GC_USB_DOEPCTL4_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL4_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNP_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_STALL_LSB 0x15 +#define GC_USB_DOEPCTL4_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL4_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL4_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_STALL_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL4_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL4_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_CNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL4_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL4_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL4_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SNAK_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL4_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL4_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD0PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL4_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL4_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_SETD1PID_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL4_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL4_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPDIS_OFFSET 0xb80 +#define GC_USB_DOEPCTL4_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL4_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL4_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL4_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL4_EPENA_OFFSET 0xb80 +#define GC_USB_DOEPINT4_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET 0xb88 +#define GC_USB_DOEPINT4_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT4_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_EPDISBLD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT4_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT4_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT4_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_AHBERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_SETUP_LSB 0x3 +#define GC_USB_DOEPINT4_SETUP_MASK 0x8 +#define GC_USB_DOEPINT4_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_SETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT4_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET 0xb88 +#define GC_USB_DOEPINT4_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT4_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT4_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT4_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT4_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT4_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BNAINTR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT4_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET 0xb88 +#define GC_USB_DOEPINT4_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT4_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT4_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT4_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT4_BBLEERR_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT4_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT4_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT4_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT4_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET 0xb88 +#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET 0xb88 +#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ4_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET 0xb90 +#define GC_USB_DOEPTSIZ4_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ4_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ4_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET 0xb90 +#define GC_USB_DOEPDMA4_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA4_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA4_DMAADDR_OFFSET 0xb94 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET 0xb9c +#define GC_USB_DOEPCTL5_MPS_LSB 0x0 +#define GC_USB_DOEPCTL5_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL5_MPS_SIZE 0xb +#define GC_USB_DOEPCTL5_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_MPS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL5_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL5_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_USBACTEP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_DPID_LSB 0x10 +#define GC_USB_DOEPCTL5_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL5_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL5_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_DPID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL5_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL5_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_NAKSTS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL5_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL5_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPTYPE_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNP_LSB 0x14 +#define GC_USB_DOEPCTL5_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL5_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNP_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_STALL_LSB 0x15 +#define GC_USB_DOEPCTL5_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL5_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL5_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_STALL_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL5_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL5_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_CNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL5_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL5_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL5_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SNAK_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL5_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL5_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD0PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL5_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL5_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_SETD1PID_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL5_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL5_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPDIS_OFFSET 0xba0 +#define GC_USB_DOEPCTL5_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL5_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL5_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL5_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL5_EPENA_OFFSET 0xba0 +#define GC_USB_DOEPINT5_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET 0xba8 +#define GC_USB_DOEPINT5_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT5_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_EPDISBLD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT5_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT5_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT5_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_AHBERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_SETUP_LSB 0x3 +#define GC_USB_DOEPINT5_SETUP_MASK 0x8 +#define GC_USB_DOEPINT5_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_SETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT5_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET 0xba8 +#define GC_USB_DOEPINT5_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT5_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT5_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT5_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT5_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT5_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BNAINTR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT5_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET 0xba8 +#define GC_USB_DOEPINT5_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT5_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT5_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT5_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT5_BBLEERR_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT5_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT5_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT5_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT5_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET 0xba8 +#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET 0xba8 +#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ5_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET 0xbb0 +#define GC_USB_DOEPTSIZ5_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ5_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ5_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET 0xbb0 +#define GC_USB_DOEPDMA5_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA5_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA5_DMAADDR_OFFSET 0xbb4 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET 0xbbc +#define GC_USB_DOEPCTL6_MPS_LSB 0x0 +#define GC_USB_DOEPCTL6_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL6_MPS_SIZE 0xb +#define GC_USB_DOEPCTL6_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_MPS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL6_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL6_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_USBACTEP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_DPID_LSB 0x10 +#define GC_USB_DOEPCTL6_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL6_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL6_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_DPID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL6_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL6_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_NAKSTS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL6_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL6_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPTYPE_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNP_LSB 0x14 +#define GC_USB_DOEPCTL6_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL6_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNP_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_STALL_LSB 0x15 +#define GC_USB_DOEPCTL6_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL6_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL6_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_STALL_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL6_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL6_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_CNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL6_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL6_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL6_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SNAK_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL6_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL6_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD0PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL6_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL6_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_SETD1PID_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL6_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL6_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPDIS_OFFSET 0xbc0 +#define GC_USB_DOEPCTL6_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL6_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL6_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL6_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL6_EPENA_OFFSET 0xbc0 +#define GC_USB_DOEPINT6_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT6_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_EPDISBLD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT6_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT6_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT6_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_AHBERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_SETUP_LSB 0x3 +#define GC_USB_DOEPINT6_SETUP_MASK 0x8 +#define GC_USB_DOEPINT6_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_SETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT6_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT6_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT6_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT6_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT6_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT6_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BNAINTR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT6_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT6_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT6_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT6_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT6_BBLEERR_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT6_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT6_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT6_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT6_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET 0xbc8 +#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET 0xbc8 +#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ6_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET 0xbd0 +#define GC_USB_DOEPTSIZ6_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ6_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ6_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET 0xbd0 +#define GC_USB_DOEPDMA6_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA6_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA6_DMAADDR_OFFSET 0xbd4 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET 0xbdc +#define GC_USB_DOEPCTL7_MPS_LSB 0x0 +#define GC_USB_DOEPCTL7_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL7_MPS_SIZE 0xb +#define GC_USB_DOEPCTL7_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_MPS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL7_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL7_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_USBACTEP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_DPID_LSB 0x10 +#define GC_USB_DOEPCTL7_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL7_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL7_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_DPID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL7_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL7_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_NAKSTS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL7_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL7_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPTYPE_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNP_LSB 0x14 +#define GC_USB_DOEPCTL7_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL7_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNP_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_STALL_LSB 0x15 +#define GC_USB_DOEPCTL7_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL7_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL7_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_STALL_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL7_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL7_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_CNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL7_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL7_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL7_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SNAK_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL7_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL7_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD0PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL7_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL7_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_SETD1PID_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL7_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL7_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPDIS_OFFSET 0xbe0 +#define GC_USB_DOEPCTL7_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL7_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL7_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL7_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL7_EPENA_OFFSET 0xbe0 +#define GC_USB_DOEPINT7_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT7_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_EPDISBLD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT7_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT7_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT7_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_AHBERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_SETUP_LSB 0x3 +#define GC_USB_DOEPINT7_SETUP_MASK 0x8 +#define GC_USB_DOEPINT7_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_SETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT7_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT7_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT7_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT7_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT7_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT7_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BNAINTR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT7_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT7_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT7_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT7_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT7_BBLEERR_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT7_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT7_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT7_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT7_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET 0xbe8 +#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET 0xbe8 +#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ7_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET 0xbf0 +#define GC_USB_DOEPTSIZ7_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ7_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ7_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET 0xbf0 +#define GC_USB_DOEPDMA7_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA7_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA7_DMAADDR_OFFSET 0xbf4 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET 0xbfc +#define GC_USB_DOEPCTL8_MPS_LSB 0x0 +#define GC_USB_DOEPCTL8_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL8_MPS_SIZE 0xb +#define GC_USB_DOEPCTL8_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_MPS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL8_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL8_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_USBACTEP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_DPID_LSB 0x10 +#define GC_USB_DOEPCTL8_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL8_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL8_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_DPID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL8_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL8_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_NAKSTS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL8_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL8_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPTYPE_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNP_LSB 0x14 +#define GC_USB_DOEPCTL8_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL8_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNP_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_STALL_LSB 0x15 +#define GC_USB_DOEPCTL8_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL8_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL8_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_STALL_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL8_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL8_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_CNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL8_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL8_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL8_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SNAK_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL8_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL8_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD0PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL8_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL8_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_SETD1PID_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL8_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL8_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPDIS_OFFSET 0xc00 +#define GC_USB_DOEPCTL8_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL8_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL8_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL8_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL8_EPENA_OFFSET 0xc00 +#define GC_USB_DOEPINT8_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET 0xc08 +#define GC_USB_DOEPINT8_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT8_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_EPDISBLD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT8_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT8_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT8_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_AHBERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_SETUP_LSB 0x3 +#define GC_USB_DOEPINT8_SETUP_MASK 0x8 +#define GC_USB_DOEPINT8_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_SETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT8_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET 0xc08 +#define GC_USB_DOEPINT8_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT8_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT8_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT8_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT8_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT8_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BNAINTR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT8_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET 0xc08 +#define GC_USB_DOEPINT8_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT8_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT8_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT8_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT8_BBLEERR_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT8_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT8_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT8_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT8_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET 0xc08 +#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET 0xc08 +#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ8_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET 0xc10 +#define GC_USB_DOEPTSIZ8_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ8_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ8_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET 0xc10 +#define GC_USB_DOEPDMA8_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA8_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA8_DMAADDR_OFFSET 0xc14 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET 0xc1c +#define GC_USB_DOEPCTL9_MPS_LSB 0x0 +#define GC_USB_DOEPCTL9_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL9_MPS_SIZE 0xb +#define GC_USB_DOEPCTL9_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_MPS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL9_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL9_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_USBACTEP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_DPID_LSB 0x10 +#define GC_USB_DOEPCTL9_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL9_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL9_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_DPID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL9_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL9_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_NAKSTS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL9_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL9_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPTYPE_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNP_LSB 0x14 +#define GC_USB_DOEPCTL9_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL9_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNP_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_STALL_LSB 0x15 +#define GC_USB_DOEPCTL9_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL9_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL9_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_STALL_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL9_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL9_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_CNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL9_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL9_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL9_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SNAK_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL9_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL9_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD0PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL9_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL9_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_SETD1PID_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL9_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL9_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPDIS_OFFSET 0xc20 +#define GC_USB_DOEPCTL9_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL9_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL9_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL9_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL9_EPENA_OFFSET 0xc20 +#define GC_USB_DOEPINT9_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET 0xc28 +#define GC_USB_DOEPINT9_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT9_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_EPDISBLD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT9_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT9_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT9_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_AHBERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_SETUP_LSB 0x3 +#define GC_USB_DOEPINT9_SETUP_MASK 0x8 +#define GC_USB_DOEPINT9_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_SETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT9_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET 0xc28 +#define GC_USB_DOEPINT9_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT9_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT9_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT9_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT9_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT9_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BNAINTR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT9_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET 0xc28 +#define GC_USB_DOEPINT9_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT9_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT9_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT9_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT9_BBLEERR_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT9_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT9_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT9_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT9_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET 0xc28 +#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET 0xc28 +#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ9_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET 0xc30 +#define GC_USB_DOEPTSIZ9_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ9_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ9_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET 0xc30 +#define GC_USB_DOEPDMA9_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA9_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA9_DMAADDR_OFFSET 0xc34 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET 0xc3c +#define GC_USB_DOEPCTL10_MPS_LSB 0x0 +#define GC_USB_DOEPCTL10_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL10_MPS_SIZE 0xb +#define GC_USB_DOEPCTL10_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_MPS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL10_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL10_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_USBACTEP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_DPID_LSB 0x10 +#define GC_USB_DOEPCTL10_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL10_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL10_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_DPID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL10_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL10_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_NAKSTS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL10_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL10_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPTYPE_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNP_LSB 0x14 +#define GC_USB_DOEPCTL10_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL10_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNP_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_STALL_LSB 0x15 +#define GC_USB_DOEPCTL10_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL10_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL10_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_STALL_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL10_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL10_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_CNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL10_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL10_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL10_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SNAK_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL10_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL10_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD0PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL10_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL10_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_SETD1PID_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL10_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL10_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPDIS_OFFSET 0xc40 +#define GC_USB_DOEPCTL10_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL10_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL10_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL10_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL10_EPENA_OFFSET 0xc40 +#define GC_USB_DOEPINT10_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET 0xc48 +#define GC_USB_DOEPINT10_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT10_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_EPDISBLD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT10_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT10_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT10_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_AHBERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_SETUP_LSB 0x3 +#define GC_USB_DOEPINT10_SETUP_MASK 0x8 +#define GC_USB_DOEPINT10_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_SETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT10_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET 0xc48 +#define GC_USB_DOEPINT10_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT10_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT10_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT10_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT10_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT10_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BNAINTR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT10_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET 0xc48 +#define GC_USB_DOEPINT10_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT10_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT10_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT10_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT10_BBLEERR_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT10_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT10_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT10_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT10_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET 0xc48 +#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET 0xc48 +#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ10_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET 0xc50 +#define GC_USB_DOEPTSIZ10_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ10_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ10_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET 0xc50 +#define GC_USB_DOEPDMA10_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA10_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA10_DMAADDR_OFFSET 0xc54 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET 0xc5c +#define GC_USB_DOEPCTL11_MPS_LSB 0x0 +#define GC_USB_DOEPCTL11_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL11_MPS_SIZE 0xb +#define GC_USB_DOEPCTL11_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_MPS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL11_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL11_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_USBACTEP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_DPID_LSB 0x10 +#define GC_USB_DOEPCTL11_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL11_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL11_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_DPID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL11_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL11_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_NAKSTS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL11_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL11_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPTYPE_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNP_LSB 0x14 +#define GC_USB_DOEPCTL11_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL11_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNP_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_STALL_LSB 0x15 +#define GC_USB_DOEPCTL11_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL11_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL11_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_STALL_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL11_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL11_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_CNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL11_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL11_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL11_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SNAK_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL11_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL11_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD0PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL11_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL11_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_SETD1PID_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL11_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL11_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPDIS_OFFSET 0xc60 +#define GC_USB_DOEPCTL11_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL11_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL11_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL11_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL11_EPENA_OFFSET 0xc60 +#define GC_USB_DOEPINT11_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET 0xc68 +#define GC_USB_DOEPINT11_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT11_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_EPDISBLD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT11_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT11_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT11_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_AHBERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_SETUP_LSB 0x3 +#define GC_USB_DOEPINT11_SETUP_MASK 0x8 +#define GC_USB_DOEPINT11_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_SETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT11_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET 0xc68 +#define GC_USB_DOEPINT11_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT11_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT11_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT11_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT11_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT11_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BNAINTR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT11_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET 0xc68 +#define GC_USB_DOEPINT11_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT11_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT11_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT11_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT11_BBLEERR_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT11_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT11_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT11_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT11_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET 0xc68 +#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET 0xc68 +#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ11_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET 0xc70 +#define GC_USB_DOEPTSIZ11_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ11_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ11_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET 0xc70 +#define GC_USB_DOEPDMA11_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA11_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA11_DMAADDR_OFFSET 0xc74 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET 0xc7c +#define GC_USB_DOEPCTL12_MPS_LSB 0x0 +#define GC_USB_DOEPCTL12_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL12_MPS_SIZE 0xb +#define GC_USB_DOEPCTL12_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_MPS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL12_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL12_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_USBACTEP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_DPID_LSB 0x10 +#define GC_USB_DOEPCTL12_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL12_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL12_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_DPID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL12_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL12_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_NAKSTS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL12_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL12_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPTYPE_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNP_LSB 0x14 +#define GC_USB_DOEPCTL12_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL12_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNP_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_STALL_LSB 0x15 +#define GC_USB_DOEPCTL12_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL12_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL12_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_STALL_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL12_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL12_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_CNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL12_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL12_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL12_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SNAK_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL12_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL12_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD0PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL12_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL12_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_SETD1PID_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL12_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL12_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPDIS_OFFSET 0xc80 +#define GC_USB_DOEPCTL12_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL12_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL12_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL12_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL12_EPENA_OFFSET 0xc80 +#define GC_USB_DOEPINT12_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET 0xc88 +#define GC_USB_DOEPINT12_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT12_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_EPDISBLD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT12_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT12_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT12_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_AHBERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_SETUP_LSB 0x3 +#define GC_USB_DOEPINT12_SETUP_MASK 0x8 +#define GC_USB_DOEPINT12_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_SETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT12_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET 0xc88 +#define GC_USB_DOEPINT12_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT12_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT12_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT12_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT12_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT12_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BNAINTR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT12_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET 0xc88 +#define GC_USB_DOEPINT12_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT12_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT12_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT12_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT12_BBLEERR_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT12_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT12_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT12_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT12_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET 0xc88 +#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET 0xc88 +#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ12_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET 0xc90 +#define GC_USB_DOEPTSIZ12_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ12_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ12_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET 0xc90 +#define GC_USB_DOEPDMA12_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA12_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA12_DMAADDR_OFFSET 0xc94 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET 0xc9c +#define GC_USB_DOEPCTL13_MPS_LSB 0x0 +#define GC_USB_DOEPCTL13_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL13_MPS_SIZE 0xb +#define GC_USB_DOEPCTL13_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_MPS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL13_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL13_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_USBACTEP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_DPID_LSB 0x10 +#define GC_USB_DOEPCTL13_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL13_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL13_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_DPID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL13_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL13_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_NAKSTS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL13_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL13_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPTYPE_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNP_LSB 0x14 +#define GC_USB_DOEPCTL13_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL13_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNP_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_STALL_LSB 0x15 +#define GC_USB_DOEPCTL13_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL13_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL13_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_STALL_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL13_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL13_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_CNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL13_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL13_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL13_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SNAK_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL13_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL13_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD0PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL13_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL13_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_SETD1PID_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL13_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL13_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPDIS_OFFSET 0xca0 +#define GC_USB_DOEPCTL13_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL13_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL13_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL13_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL13_EPENA_OFFSET 0xca0 +#define GC_USB_DOEPINT13_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET 0xca8 +#define GC_USB_DOEPINT13_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT13_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_EPDISBLD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT13_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT13_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT13_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_AHBERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_SETUP_LSB 0x3 +#define GC_USB_DOEPINT13_SETUP_MASK 0x8 +#define GC_USB_DOEPINT13_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_SETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT13_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET 0xca8 +#define GC_USB_DOEPINT13_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT13_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT13_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT13_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT13_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT13_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BNAINTR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT13_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET 0xca8 +#define GC_USB_DOEPINT13_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT13_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT13_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT13_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT13_BBLEERR_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT13_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT13_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT13_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT13_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET 0xca8 +#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET 0xca8 +#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ13_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET 0xcb0 +#define GC_USB_DOEPTSIZ13_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ13_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ13_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET 0xcb0 +#define GC_USB_DOEPDMA13_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA13_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA13_DMAADDR_OFFSET 0xcb4 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET 0xcbc +#define GC_USB_DOEPCTL14_MPS_LSB 0x0 +#define GC_USB_DOEPCTL14_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL14_MPS_SIZE 0xb +#define GC_USB_DOEPCTL14_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_MPS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL14_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL14_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_USBACTEP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_DPID_LSB 0x10 +#define GC_USB_DOEPCTL14_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL14_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL14_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_DPID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL14_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL14_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_NAKSTS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL14_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL14_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPTYPE_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNP_LSB 0x14 +#define GC_USB_DOEPCTL14_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL14_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNP_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_STALL_LSB 0x15 +#define GC_USB_DOEPCTL14_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL14_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL14_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_STALL_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL14_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL14_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_CNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL14_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL14_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL14_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SNAK_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL14_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL14_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD0PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL14_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL14_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_SETD1PID_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL14_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL14_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPDIS_OFFSET 0xcc0 +#define GC_USB_DOEPCTL14_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL14_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL14_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL14_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL14_EPENA_OFFSET 0xcc0 +#define GC_USB_DOEPINT14_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT14_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_EPDISBLD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT14_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT14_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT14_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_AHBERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_SETUP_LSB 0x3 +#define GC_USB_DOEPINT14_SETUP_MASK 0x8 +#define GC_USB_DOEPINT14_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_SETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT14_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT14_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT14_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT14_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT14_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT14_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BNAINTR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT14_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT14_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT14_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT14_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT14_BBLEERR_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT14_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT14_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT14_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT14_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET 0xcc8 +#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET 0xcc8 +#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ14_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET 0xcd0 +#define GC_USB_DOEPTSIZ14_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ14_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ14_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET 0xcd0 +#define GC_USB_DOEPDMA14_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA14_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA14_DMAADDR_OFFSET 0xcd4 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET 0xcdc +#define GC_USB_DOEPCTL15_MPS_LSB 0x0 +#define GC_USB_DOEPCTL15_MPS_MASK 0x7ff +#define GC_USB_DOEPCTL15_MPS_SIZE 0xb +#define GC_USB_DOEPCTL15_MPS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_MPS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_USBACTEP_LSB 0xf +#define GC_USB_DOEPCTL15_USBACTEP_MASK 0x8000 +#define GC_USB_DOEPCTL15_USBACTEP_SIZE 0x1 +#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_USBACTEP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_DPID_LSB 0x10 +#define GC_USB_DOEPCTL15_DPID_MASK 0x10000 +#define GC_USB_DOEPCTL15_DPID_SIZE 0x1 +#define GC_USB_DOEPCTL15_DPID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_DPID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_NAKSTS_LSB 0x11 +#define GC_USB_DOEPCTL15_NAKSTS_MASK 0x20000 +#define GC_USB_DOEPCTL15_NAKSTS_SIZE 0x1 +#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_NAKSTS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPTYPE_LSB 0x12 +#define GC_USB_DOEPCTL15_EPTYPE_MASK 0xc0000 +#define GC_USB_DOEPCTL15_EPTYPE_SIZE 0x2 +#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPTYPE_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNP_LSB 0x14 +#define GC_USB_DOEPCTL15_SNP_MASK 0x100000 +#define GC_USB_DOEPCTL15_SNP_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNP_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNP_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_STALL_LSB 0x15 +#define GC_USB_DOEPCTL15_STALL_MASK 0x200000 +#define GC_USB_DOEPCTL15_STALL_SIZE 0x1 +#define GC_USB_DOEPCTL15_STALL_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_STALL_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_CNAK_LSB 0x1a +#define GC_USB_DOEPCTL15_CNAK_MASK 0x4000000 +#define GC_USB_DOEPCTL15_CNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_CNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_CNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SNAK_LSB 0x1b +#define GC_USB_DOEPCTL15_SNAK_MASK 0x8000000 +#define GC_USB_DOEPCTL15_SNAK_SIZE 0x1 +#define GC_USB_DOEPCTL15_SNAK_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SNAK_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD0PID_LSB 0x1c +#define GC_USB_DOEPCTL15_SETD0PID_MASK 0x10000000 +#define GC_USB_DOEPCTL15_SETD0PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD0PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_SETD1PID_LSB 0x1d +#define GC_USB_DOEPCTL15_SETD1PID_MASK 0x20000000 +#define GC_USB_DOEPCTL15_SETD1PID_SIZE 0x1 +#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_SETD1PID_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPDIS_LSB 0x1e +#define GC_USB_DOEPCTL15_EPDIS_MASK 0x40000000 +#define GC_USB_DOEPCTL15_EPDIS_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPDIS_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPDIS_OFFSET 0xce0 +#define GC_USB_DOEPCTL15_EPENA_LSB 0x1f +#define GC_USB_DOEPCTL15_EPENA_MASK 0x80000000 +#define GC_USB_DOEPCTL15_EPENA_SIZE 0x1 +#define GC_USB_DOEPCTL15_EPENA_DEFAULT 0x0 +#define GC_USB_DOEPCTL15_EPENA_OFFSET 0xce0 +#define GC_USB_DOEPINT15_XFERCOMPL_LSB 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_MASK 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_SIZE 0x1 +#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT 0x0 +#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET 0xce8 +#define GC_USB_DOEPINT15_EPDISBLD_LSB 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_MASK 0x2 +#define GC_USB_DOEPINT15_EPDISBLD_SIZE 0x1 +#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_EPDISBLD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_AHBERR_LSB 0x2 +#define GC_USB_DOEPINT15_AHBERR_MASK 0x4 +#define GC_USB_DOEPINT15_AHBERR_SIZE 0x1 +#define GC_USB_DOEPINT15_AHBERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_AHBERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_SETUP_LSB 0x3 +#define GC_USB_DOEPINT15_SETUP_MASK 0x8 +#define GC_USB_DOEPINT15_SETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_SETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_SETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB 0x4 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK 0x10 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STSPHSERCVD_LSB 0x5 +#define GC_USB_DOEPINT15_STSPHSERCVD_MASK 0x20 +#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB 0x6 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK 0x40 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE 0x1 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET 0xce8 +#define GC_USB_DOEPINT15_OUTPKTERR_LSB 0x8 +#define GC_USB_DOEPINT15_OUTPKTERR_MASK 0x100 +#define GC_USB_DOEPINT15_OUTPKTERR_SIZE 0x1 +#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BNAINTR_LSB 0x9 +#define GC_USB_DOEPINT15_BNAINTR_MASK 0x200 +#define GC_USB_DOEPINT15_BNAINTR_SIZE 0x1 +#define GC_USB_DOEPINT15_BNAINTR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BNAINTR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_PKTDRPSTS_LSB 0xb +#define GC_USB_DOEPINT15_PKTDRPSTS_MASK 0x800 +#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE 0x1 +#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT 0x0 +#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET 0xce8 +#define GC_USB_DOEPINT15_BBLEERR_LSB 0xc +#define GC_USB_DOEPINT15_BBLEERR_MASK 0x1000 +#define GC_USB_DOEPINT15_BBLEERR_SIZE 0x1 +#define GC_USB_DOEPINT15_BBLEERR_DEFAULT 0x0 +#define GC_USB_DOEPINT15_BBLEERR_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NAKINTRPT_LSB 0xd +#define GC_USB_DOEPINT15_NAKINTRPT_MASK 0x2000 +#define GC_USB_DOEPINT15_NAKINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_NYETINTRPT_LSB 0xe +#define GC_USB_DOEPINT15_NYETINTRPT_MASK 0x4000 +#define GC_USB_DOEPINT15_NYETINTRPT_SIZE 0x1 +#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT 0x0 +#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET 0xce8 +#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB 0xf +#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK 0x8000 +#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE 0x1 +#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT 0x0 +#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET 0xce8 +#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK 0x7ffff +#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE 0x13 +#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_PKTCNT_LSB 0x13 +#define GC_USB_DOEPTSIZ15_PKTCNT_MASK 0x1ff80000 +#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE 0xa +#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET 0xcf0 +#define GC_USB_DOEPTSIZ15_RXDPID_LSB 0x1d +#define GC_USB_DOEPTSIZ15_RXDPID_MASK 0x60000000 +#define GC_USB_DOEPTSIZ15_RXDPID_SIZE 0x2 +#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT 0x0 +#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET 0xcf0 +#define GC_USB_DOEPDMA15_DMAADDR_LSB 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_MASK 0xffffffff +#define GC_USB_DOEPDMA15_DMAADDR_SIZE 0x20 +#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMA15_DMAADDR_OFFSET 0xcf4 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK 0xffffffff +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE 0x20 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT 0x0 +#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET 0xcfc +#define GC_USB_PCGCCTL_STOPPCLK_LSB 0x0 +#define GC_USB_PCGCCTL_STOPPCLK_MASK 0x1 +#define GC_USB_PCGCCTL_STOPPCLK_SIZE 0x1 +#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT 0x0 +#define GC_USB_PCGCCTL_STOPPCLK_OFFSET 0xe00 +#define GC_USB_PCGCCTL_GATEHCLK_LSB 0x1 +#define GC_USB_PCGCCTL_GATEHCLK_MASK 0x2 +#define GC_USB_PCGCCTL_GATEHCLK_SIZE 0x1 +#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT 0x0 +#define GC_USB_PCGCCTL_GATEHCLK_OFFSET 0xe00 +#define GC_USB_PCGCCTL_PWRCLMP_LSB 0x2 +#define GC_USB_PCGCCTL_PWRCLMP_MASK 0x4 +#define GC_USB_PCGCCTL_PWRCLMP_SIZE 0x1 +#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT 0x0 +#define GC_USB_PCGCCTL_PWRCLMP_OFFSET 0xe00 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB 0x3 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE 0x1 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x0 +#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET 0xe00 +#define GC_USB_PCGCCTL_PHYSLEEP_LSB 0x6 +#define GC_USB_PCGCCTL_PHYSLEEP_MASK 0x40 +#define GC_USB_PCGCCTL_PHYSLEEP_SIZE 0x1 +#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT 0x0 +#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET 0xe00 +#define GC_USB_PCGCCTL_L1SUSPENDED_LSB 0x7 +#define GC_USB_PCGCCTL_L1SUSPENDED_MASK 0x80 +#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE 0x1 +#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT 0x0 +#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET 0xe00 +#define GC_USB_DFIFO_SIZE 0x1000 #endif /* __CHIP_STM32_USB_DWC_REGISTERS_H */ -- cgit v1.2.1 From d14fbe1bba026c05d38d81da3fcc4e496d9c8307 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:28 -0600 Subject: zephyr/test/drivers/src/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3620abb2ca4d4f88afe259145f3885a3e1eb2071 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730976 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/panic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/panic.c b/zephyr/test/drivers/src/panic.c index f33a078253..2ee12b34c3 100644 --- a/zephyr/test/drivers/src/panic.c +++ b/zephyr/test/drivers/src/panic.c @@ -26,7 +26,7 @@ struct panic_test_fixture { static void *panic_test_setup(void) { - static struct panic_test_fixture panic_fixture = {0}; + static struct panic_test_fixture panic_fixture = { 0 }; return &panic_fixture; } -- cgit v1.2.1 From bfa7bd60a2b3a72fc85368eaee0d0673131c66ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:51 -0600 Subject: chip/ish/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I04720006bfad4de91443dd389a22bf8b429c3b4a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729159 Reviewed-by: Jeremy Bettis --- chip/ish/i2c.c | 161 +++++++++++++++++++++++++-------------------------------- 1 file changed, 69 insertions(+), 92 deletions(-) diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c index 11f3e0a0b1..7ed0b92cc2 100644 --- a/chip/ish/i2c.c +++ b/chip/ish/i2c.c @@ -19,65 +19,53 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) /*25MHz, 50MHz, 100MHz, 120MHz, 40MHz, 20MHz, 37MHz*/ -static uint16_t default_hcnt_scl_100[] = { - 4000, 4420, 4920, 4400, 4000, 4000, 4300 -}; +static uint16_t default_hcnt_scl_100[] = { 4000, 4420, 4920, 4400, + 4000, 4000, 4300 }; -static uint16_t default_lcnt_scl_100[] = { - 4720, 5180, 4990, 5333, 4700, 5200, 4950 -}; +static uint16_t default_lcnt_scl_100[] = { 4720, 5180, 4990, 5333, + 4700, 5200, 4950 }; -static uint16_t default_hcnt_scl_400[] = { - 600, 820, 1120, 800, 600, 600, 450 -}; +static uint16_t default_hcnt_scl_400[] = { 600, 820, 1120, 800, 600, 600, 450 }; -static uint16_t default_lcnt_scl_400[] = { - 1320, 1380, 1300, 1550, 1300, 1200, 1250 -}; +static uint16_t default_lcnt_scl_400[] = { 1320, 1380, 1300, 1550, + 1300, 1200, 1250 }; -static uint16_t default_hcnt_scl_1000[] = { - 260, 260, 260, 305, 260, 260, 260 -}; +static uint16_t default_hcnt_scl_1000[] = { 260, 260, 260, 305, 260, 260, 260 }; -static uint16_t default_lcnt_scl_1000[] = { - 500, 500, 500, 525, 500, 500, 500 -}; +static uint16_t default_lcnt_scl_1000[] = { 500, 500, 500, 525, 500, 500, 500 }; static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 }; static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 }; - #ifdef CHIP_VARIANT_ISH5P4 /* Change to I2C_FREQ_100 in real silicon platform */ -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100 -}; +static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_100, I2C_FREQ_100, + I2C_FREQ_100 }; #else -static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { - I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120 -}; +static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = { I2C_FREQ_120, I2C_FREQ_120, + I2C_FREQ_120 }; #endif static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = { { .bus = 0, - .base = (uint32_t *) ISH_I2C0_BASE, + .base = (uint32_t *)ISH_I2C0_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C0_IRQ, }, { .bus = 1, - .base = (uint32_t *) ISH_I2C1_BASE, + .base = (uint32_t *)ISH_I2C1_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C1_IRQ, }, { .bus = 2, - .base = (uint32_t *) ISH_I2C2_BASE, + .base = (uint32_t *)ISH_I2C2_BASE, .speed = I2C_SPEED_400KHZ, .int_pin = ISH_I2C2_IRQ, }, @@ -104,22 +92,20 @@ static struct i2c_bus_info board_config[ISH_I2C_PORT_COUNT] = { .fast_speed.sda_hold = DEFAULT_SDA_HOLD_FAST, .fast_plus_speed.sda_hold = DEFAULT_SDA_HOLD_FAST_PLUS, .high_speed.sda_hold = DEFAULT_SDA_HOLD_HIGH, - }, + }, }; -static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, - uint32_t data) +static inline void i2c_mmio_write(uint32_t *base, uint8_t offset, uint32_t data) { - REG32((uint32_t) ((uint8_t *)base + offset)) = data; + REG32((uint32_t)((uint8_t *)base + offset)) = data; } static inline uint32_t i2c_mmio_read(uint32_t *base, uint8_t offset) { - return REG32((uint32_t) ((uint8_t *)base + offset)); + return REG32((uint32_t)((uint8_t *)base + offset)); } -static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, - uint8_t offset) +static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, uint8_t offset) { uint32_t ret = i2c_mmio_read(addr, reg) >> offset; @@ -129,7 +115,6 @@ static inline uint8_t i2c_read_byte(uint32_t *addr, uint8_t reg, static void i2c_intr_switch(uint32_t *base, int mode) { switch (mode) { - case ENABLE_WRITE_INT: i2c_mmio_write(base, IC_INTR_MASK, IC_INTR_WRITE_MASK_VAL); break; @@ -157,8 +142,8 @@ static void i2c_intr_switch(uint32_t *base, int mode) } } -static void i2c_init_transaction(struct i2c_context *ctx, - uint16_t addr, uint8_t flags) +static void i2c_init_transaction(struct i2c_context *ctx, uint16_t addr, + uint8_t flags) { uint32_t con_value; uint32_t *base = ctx->base; @@ -169,64 +154,64 @@ static void i2c_init_transaction(struct i2c_context *ctx, i2c_intr_switch(base, DISABLE_INT); i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_TAR, (addr << IC_TAR_OFFSET) | - TAR_SPECIAL_VAL | IC_10BITADDR_MASTER_VAL); + i2c_mmio_write(base, IC_TAR, + (addr << IC_TAR_OFFSET) | TAR_SPECIAL_VAL | + IC_10BITADDR_MASTER_VAL); /* set Clock SCL Count */ switch (ctx->speed) { - case I2C_SPEED_100KHZ: i2c_mmio_write(base, IC_SS_SCL_HCNT, - NS_2_COUNTERS(bus_info->std_speed.hcnt, + NS_2_COUNTERS(bus_info->std_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_SS_SCL_LCNT, - NS_2_COUNTERS(bus_info->std_speed.lcnt, + NS_2_COUNTERS(bus_info->std_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->std_speed.sda_hold, + NS_2_COUNTERS(bus_info->std_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_400KHZ: i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_speed.sda_hold, + NS_2_COUNTERS(bus_info->fast_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_1MHZ: i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_plus_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_plus_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold, + NS_2_COUNTERS(bus_info->fast_plus_speed.sda_hold, clk_in_val)); break; case I2C_SPEED_3M4HZ: i2c_mmio_write(base, IC_HS_SCL_HCNT, - NS_2_COUNTERS(bus_info->high_speed.hcnt, + NS_2_COUNTERS(bus_info->high_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_HS_SCL_LCNT, - NS_2_COUNTERS(bus_info->high_speed.lcnt, + NS_2_COUNTERS(bus_info->high_speed.lcnt, clk_in_val)); i2c_mmio_write(base, IC_SDA_HOLD, - NS_2_COUNTERS(bus_info->high_speed.sda_hold, + NS_2_COUNTERS(bus_info->high_speed.sda_hold, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_HCNT, - NS_2_COUNTERS(bus_info->fast_speed.hcnt, + NS_2_COUNTERS(bus_info->fast_speed.hcnt, clk_in_val)); i2c_mmio_write(base, IC_FS_SCL_LCNT, - NS_2_COUNTERS(bus_info->fast_speed.lcnt, + NS_2_COUNTERS(bus_info->fast_speed.lcnt, clk_in_val)); break; @@ -248,15 +233,13 @@ static void i2c_init_transaction(struct i2c_context *ctx, i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_ENABLE); } -static void i2c_write_buffer(uint32_t *base, uint8_t len, - const uint8_t *buffer, ssize_t *cur_index, - ssize_t total_len) +static void i2c_write_buffer(uint32_t *base, uint8_t len, const uint8_t *buffer, + ssize_t *cur_index, ssize_t total_len) { int i; uint16_t out; for (i = 0; i < len; i++) { - ++(*cur_index); out = (buffer[i] << DATA_CMD_DAT_OFFSET) | DATA_CMD_WRITE_VAL; @@ -270,7 +253,7 @@ static void i2c_write_buffer(uint32_t *base, uint8_t len, } static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data, - unsigned restart_flag) + unsigned restart_flag) { /* this routine just set RX FIFO's control bit(s), * READ command or RESTART */ @@ -293,9 +276,8 @@ static void i2c_write_read_commands(uint32_t *base, uint8_t len, int more_data, } } -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { int i; ssize_t total_len; @@ -333,8 +315,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, /* Write W data */ if (out_size) - i2c_write_buffer(ctx->base, out_size, out, - &curr_index, total_len); + i2c_write_buffer(ctx->base, out_size, out, &curr_index, + total_len); /* Wait here until Tx is completed so that FIFO becomes empty. * This is optimized for smaller Tx data size. @@ -344,10 +326,8 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * */ expire_ts = __hw_clock_source_read() + I2C_TX_FLUSH_TIMEOUT_USEC; if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) { - while ((i2c_mmio_read(ctx->base, IC_STATUS) & BIT(IC_STATUS_TFE)) == 0) { - if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; break; @@ -358,7 +338,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, begin_indx = 0; while (in_size) { - int rd_size; /* read size for on i2c transaction */ + int rd_size; /* read size for on i2c transaction */ /* * check if in_size > ISH_I2C_FIFO_SIZE, then try to read @@ -383,11 +363,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * set R commands bit, start to read */ i2c_write_read_commands(ctx->base, rd_size, in_size, - (begin_indx == 0) && (repeat_start != 0)); - + (begin_indx == 0) && + (repeat_start != 0)); /* need timeout in case no ACK from peripheral */ - task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2*MSEC); + task_wait_event_mask(TASK_EVENT_I2C_IDLE, 2 * MSEC); if (ctx->interrupts & M_TX_ABRT) { ctx->error_flag = 1; @@ -396,8 +376,7 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, /* read data */ for (i = begin_indx; i < begin_indx + rd_size; i++) - in[i] = i2c_read_byte(ctx->base, - IC_DATA_CMD, 0); + in[i] = i2c_read_byte(ctx->base, IC_DATA_CMD, 0); begin_indx += rd_size; } /* while (in_size) */ @@ -411,7 +390,6 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, while ((i2c_mmio_read(ctx->base, IC_STATUS) & (BIT(IC_STATUS_MASTER_ACTIVITY) | BIT(IC_STATUS_TFE))) != BIT(IC_STATUS_TFE)) { - if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; break; @@ -432,12 +410,12 @@ static void i2c_interrupt_handler(struct i2c_context *ctx) uint32_t raw_intr; if (IS_ENABLED(INTR_DEBUG)) - raw_intr = 0x0000FFFF & i2c_mmio_read(ctx->base, - IC_RAW_INTR_STAT); + raw_intr = 0x0000FFFF & + i2c_mmio_read(ctx->base, IC_RAW_INTR_STAT); /* check interrupts */ ctx->interrupts = i2c_mmio_read(ctx->base, IC_INTR_STAT); - ctx->reason = (uint16_t) i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); + ctx->reason = (uint16_t)i2c_mmio_read(ctx->base, IC_TX_ABRT_SOURCE); if (IS_ENABLED(INTR_DEBUG)) CPRINTS("INTR_STAT = 0x%04x, TX_ABORT_SRC = 0x%04x, " @@ -467,9 +445,8 @@ static void i2c_isr_bus2(void) } DECLARE_IRQ(ISH_I2C2_IRQ, i2c_isr_bus2); -static void i2c_config_speed(struct i2c_context *ctx, int kbps) +static void i2c_config_speed(struct i2c_context *ctx, int kbps) { - if (kbps > 1000) ctx->speed = I2C_SPEED_3M4HZ; else if (kbps > 400) @@ -478,7 +455,6 @@ static void i2c_config_speed(struct i2c_context *ctx, int kbps) ctx->speed = I2C_SPEED_400KHZ; else ctx->speed = I2C_SPEED_100KHZ; - } static void i2c_init_hardware(struct i2c_context *ctx) @@ -486,8 +462,8 @@ static void i2c_init_hardware(struct i2c_context *ctx) static const uint8_t speed_val_arr[] = { [I2C_SPEED_100KHZ] = STD_SPEED_VAL, [I2C_SPEED_400KHZ] = FAST_SPEED_VAL, - [I2C_SPEED_1MHZ] = FAST_SPEED_VAL, - [I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL, + [I2C_SPEED_1MHZ] = FAST_SPEED_VAL, + [I2C_SPEED_3M4HZ] = HIGH_SPEED_VAL, }; uint32_t *base = ctx->base; @@ -495,19 +471,20 @@ static void i2c_init_hardware(struct i2c_context *ctx) /* disable interrupts */ i2c_intr_switch(base, DISABLE_INT); i2c_mmio_write(base, IC_ENABLE, IC_ENABLE_DISABLE); - i2c_mmio_write(base, IC_CON, (MASTER_MODE_VAL - | speed_val_arr[ctx->speed] - | IC_RESTART_EN_VAL - | IC_SLAVE_DISABLE_VAL)); + i2c_mmio_write(base, IC_CON, + (MASTER_MODE_VAL | speed_val_arr[ctx->speed] | + IC_RESTART_EN_VAL | IC_SLAVE_DISABLE_VAL)); i2c_mmio_write(base, IC_FS_SPKLEN, spkln[bus_freq[ctx->bus]]); i2c_mmio_write(base, IC_HS_SPKLEN, spkln[bus_freq[ctx->bus]]); /* get RX_FIFO and TX_FIFO depth */ - ctx->max_rx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - RX_BUFFER_DEPTH_OFFSET) + 1; - ctx->max_tx_depth = i2c_read_byte(base, IC_COMP_PARAM_1, - TX_BUFFER_DEPTH_OFFSET) + 1; + ctx->max_rx_depth = + i2c_read_byte(base, IC_COMP_PARAM_1, RX_BUFFER_DEPTH_OFFSET) + + 1; + ctx->max_tx_depth = + i2c_read_byte(base, IC_COMP_PARAM_1, TX_BUFFER_DEPTH_OFFSET) + + 1; } static void i2c_initial_board_config(struct i2c_context *ctx) -- cgit v1.2.1 From 43183f4825f9d902f94cb36660fed788c47dbb9a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:09 -0600 Subject: board/c2d2/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic4abd7b572a0b2589ac26608c1f5814342df5132 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728130 Reviewed-by: Jeremy Bettis --- board/c2d2/board.c | 204 +++++++++++++++++++++-------------------------------- 1 file changed, 80 insertions(+), 124 deletions(-) diff --git a/board/c2d2/board.c b/board/c2d2/board.c index 24b314118e..fb33ec8587 100644 --- a/board/c2d2/board.c +++ b/board/c2d2/board.c @@ -30,8 +30,8 @@ #include "gpio_list.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* Forward declarations */ static void update_vrefs_and_shifters(void); @@ -41,19 +41,19 @@ static bool is_ec_i2c_enabled(void); /* Global state tracking current pin configuration and operations */ static struct mutex vref_bus_state_mutex; static int vref_monitor_disable; -#define VREF_MON_DIS_H1_RST_HELD BIT(0) -#define VREF_MON_DIS_EC_PWR_HELD BIT(1) -#define VREF_MON_DIS_SPI_MODE BIT(2) +#define VREF_MON_DIS_H1_RST_HELD BIT(0) +#define VREF_MON_DIS_EC_PWR_HELD BIT(1) +#define VREF_MON_DIS_SPI_MODE BIT(2) /* * Tracks if bus pins are locked by a function like UART holding, I2C, * or SPI. */ enum bus_lock { - BUS_UNLOCKED, /* Normal UART; pins available for other functions */ - BUS_UART_HELD, /* UART locked to pins while holding RX low */ - BUS_SPI, /* SPI locked to pins */ - BUS_I2C, /* I2C bus locked to pins */ + BUS_UNLOCKED, /* Normal UART; pins available for other functions */ + BUS_UART_HELD, /* UART locked to pins while holding RX low */ + BUS_SPI, /* SPI locked to pins */ + BUS_I2C, /* I2C bus locked to pins */ }; /* A0/A1 (H1 UART or SPI) */ enum bus_lock h1_pins; @@ -88,11 +88,9 @@ static int command_bus_status(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status, - "", +DECLARE_CONSOLE_COMMAND(bus_status, command_bus_status, "", "Gets the bus state for swappable pins"); - /****************************************************************************** ** Chip-specific board configuration */ @@ -114,12 +112,11 @@ void board_config_pre_init(void) * i2c : no dma * tim16/17: no dma */ - STM32_SYSCFG_CFGR1 |= BIT(24); /* Remap SPI2_RX to channel 6 */ - STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */ - STM32_SYSCFG_CFGR1 |= BIT(10); /* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(24); /* Remap SPI2_RX to channel 6 */ + STM32_SYSCFG_CFGR1 |= BIT(26); /* Remap USART3 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(10); /* Remap USART1 RX/TX DMA */ } - /****************************************************************************** ** ADC channels */ @@ -147,18 +144,18 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("C2D2"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("CR50"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), - [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("C2D2 Shell"), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"), - [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("EC"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("C2D2"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("CR50"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("C2D2 Shell"), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("CPU"), + [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("EC"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -174,7 +171,7 @@ const struct i2c_port_t i2c_ports[] = { .port = I2C_PORT_EC, .kbps = 100, .scl = GPIO_UART_DBG_TX_EC_RX_SCL, - .sda = GPIO_UART_EC_TX_DBG_RX_SDA, + .sda = GPIO_UART_EC_TX_DBG_RX_SDA, .flags = I2C_PORT_FLAG_DYNAMIC_SPEED, }, { @@ -182,7 +179,7 @@ const struct i2c_port_t i2c_ports[] = { .port = I2C_PORT_AUX, .kbps = 100, .scl = GPIO_UART_DBG_TX_AP_RX_INA_SCL, - .sda = GPIO_UART_AP_TX_DBG_RX_INA_SDA, + .sda = GPIO_UART_AP_TX_DBG_RX_INA_SDA, .flags = I2C_PORT_FLAG_DYNAMIC_SPEED, }, }; @@ -203,14 +200,17 @@ const struct ite_dfu_config_t ite_dfu_config = { * let the i2c transactions fail instead of using the USB endpoint disable * status. */ -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 32 -#define USB_STREAM_TX_SIZE 64 +#define USB_STREAM_RX_SIZE 32 +#define USB_STREAM_TX_SIZE 64 /****************************************************************************** * Forward USART1 (EC) as a simple USB serial interface. @@ -219,33 +219,22 @@ int usb_i2c_board_is_enabled(void) { return 1; } static struct usart_config const usart1; struct usb_stream_config const usart1_usb; -static struct queue const usart1_to_usb = QUEUE_DIRECT(128, uint8_t, - usart1.producer, usart1_usb.consumer); -static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t, - usart1_usb.producer, usart1.consumer); +static struct queue const usart1_to_usb = + QUEUE_DIRECT(128, uint8_t, usart1.producer, usart1_usb.consumer); +static struct queue const usb_to_usart1 = + QUEUE_DIRECT(64, uint8_t, usart1_usb.producer, usart1.consumer); static struct usart_rx_dma const usart1_rx_dma = USART_RX_DMA(STM32_DMAC_CH5, 32); static struct usart_config const usart1 = - USART_CONFIG(usart1_hw, - usart1_rx_dma.usart_rx, - usart_tx_interrupt, - 115200, - 0, - usart1_to_usb, - usb_to_usart1); - -USB_STREAM_CONFIG_USART_IFACE(usart1_usb, - USB_IFACE_USART1_STREAM, - USB_STR_USART1_STREAM_NAME, - USB_EP_USART1_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart1, - usart1_to_usb, - usart1) + USART_CONFIG(usart1_hw, usart1_rx_dma.usart_rx, usart_tx_interrupt, + 115200, 0, usart1_to_usb, usb_to_usart1); +USB_STREAM_CONFIG_USART_IFACE(usart1_usb, USB_IFACE_USART1_STREAM, + USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart1, usart1_to_usb, usart1) /****************************************************************************** * Forward USART3 (CPU) as a simple USB serial interface. @@ -254,33 +243,22 @@ USB_STREAM_CONFIG_USART_IFACE(usart1_usb, static struct usart_config const usart3; struct usb_stream_config const usart3_usb; -static struct queue const usart3_to_usb = QUEUE_DIRECT(1024, uint8_t, - usart3.producer, usart3_usb.consumer); -static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t, - usart3_usb.producer, usart3.consumer); +static struct queue const usart3_to_usb = + QUEUE_DIRECT(1024, uint8_t, usart3.producer, usart3_usb.consumer); +static struct queue const usb_to_usart3 = + QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer); static struct usart_rx_dma const usart3_rx_dma = USART_RX_DMA(STM32_DMAC_CH3, 32); static struct usart_config const usart3 = - USART_CONFIG(usart3_hw, - usart3_rx_dma.usart_rx, - usart_tx_interrupt, - 115200, - 0, - usart3_to_usb, - usb_to_usart3); - -USB_STREAM_CONFIG_USART_IFACE(usart3_usb, - USB_IFACE_USART3_STREAM, - USB_STR_USART3_STREAM_NAME, - USB_EP_USART3_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart3, - usart3_to_usb, - usart3) + USART_CONFIG(usart3_hw, usart3_rx_dma.usart_rx, usart_tx_interrupt, + 115200, 0, usart3_to_usb, usb_to_usart3); +USB_STREAM_CONFIG_USART_IFACE(usart3_usb, USB_IFACE_USART3_STREAM, + USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart3, usart3_to_usb, usart3) /****************************************************************************** * Forward USART4 (cr50) as a simple USB serial interface. @@ -291,29 +269,19 @@ USB_STREAM_CONFIG_USART_IFACE(usart3_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(1024, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(1024, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG_USART_IFACE(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb, - usart4) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart4_to_usb, usb_to_usart4); + +USB_STREAM_CONFIG_USART_IFACE(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart4, usart4_to_usb, usart4) /****************************************************************************** * Set up SPI over USB @@ -322,7 +290,7 @@ USB_STREAM_CONFIG_USART_IFACE(usart4_usb, /* SPI devices */ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN}, + { CONFIG_SPI_FLASH_PORT, 1, GPIO_SPI_CSN }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); @@ -398,8 +366,7 @@ static int command_uart_parity(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, - "usart[2|3|4] [0|1|2]", +DECLARE_CONSOLE_COMMAND(parity, command_uart_parity, "usart[2|3|4] [0|1|2]", "Set parity on uart"); /****************************************************************************** @@ -431,8 +398,7 @@ static int command_uart_baud(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, - "usart[2|3|4] rate", +DECLARE_CONSOLE_COMMAND(baud, command_uart_baud, "usart[2|3|4] rate", "Set baud rate on uart"); /****************************************************************************** @@ -501,7 +467,7 @@ static int command_hold_usart_low(int argc, char **argv) /* Print status for get and set case. */ ccprintf("USART status: %s\n", - *bus == BUS_UART_HELD ? "held low" : "normal"); + *bus == BUS_UART_HELD ? "held low" : "normal"); return EC_SUCCESS; @@ -513,7 +479,6 @@ DECLARE_CONSOLE_COMMAND(hold_usart_low, command_hold_usart_low, "usart[1|3|4] [0|1]?", "Get/set the hold-low state for usart port"); - /****************************************************************************** * Console commands SPI programming */ @@ -650,8 +615,7 @@ busy_error_unlock: mutex_unlock(&vref_bus_state_mutex); return EC_ERROR_BUSY; } -DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi, - "[0|1800|3300]?", +DECLARE_CONSOLE_COMMAND(enable_spi, command_enable_spi, "[0|1800|3300]?", "Get/set the SPI Vref"); /****************************************************************************** @@ -819,7 +783,6 @@ static int command_vref_alternate(int argc, char **argv, ccprintf("%s held: %s\n", print_name, vref_monitor_disable & state_flag ? "yes" : "no"); - return EC_SUCCESS; busy_error_unlock: @@ -834,8 +797,7 @@ static int command_pwr_button(int argc, char **argv) GPIO_EN_SPIVREF_HOLDN_ECVREF_H1_PWRBTN, VREF_MON_DIS_EC_PWR_HELD, "Power button"); } -DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button, - "[0|1]?", +DECLARE_CONSOLE_COMMAND(pwr_button, command_pwr_button, "[0|1]?", "Get/set the power button state"); static int command_h1_reset(int argc, char **argv) @@ -843,8 +805,8 @@ static int command_h1_reset(int argc, char **argv) if ((argc == 2) && !strncasecmp("pulse", argv[1], strlen(argv[1]))) { int rv; int c = 2; - char *cmd_on[] = {"", "1", ""}; - char *cmd_off[] = {"", "0", ""}; + char *cmd_on[] = { "", "1", "" }; + char *cmd_off[] = { "", "0", "" }; rv = command_vref_alternate(c, cmd_on, GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL, @@ -853,11 +815,10 @@ static int command_h1_reset(int argc, char **argv) "H1 reset"); if (rv == EC_SUCCESS) { msleep(100); - rv = command_vref_alternate - (c, cmd_off, - GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL, - GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, - VREF_MON_DIS_H1_RST_HELD, "H1 reset"); + rv = command_vref_alternate( + c, cmd_off, GPIO_SPIVREF_RSVD_H1VREF_H1_RST_ODL, + GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, + VREF_MON_DIS_H1_RST_HELD, "H1 reset"); } return rv; } @@ -867,11 +828,9 @@ static int command_h1_reset(int argc, char **argv) GPIO_EN_SPIVREF_RSVD_H1VREF_H1_RST, VREF_MON_DIS_H1_RST_HELD, "H1 reset"); } -DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset, - "[0|1|pulse]?", +DECLARE_CONSOLE_COMMAND(h1_reset, command_h1_reset, "[0|1|pulse]?", "Get/set the h1 reset state"); - /****************************************************************************** * Vref detection logic */ @@ -886,8 +845,7 @@ static int command_h1_vref_present(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present, - "", +DECLARE_CONSOLE_COMMAND(h1_vref, command_h1_vref_present, "", "Get if the h1 vref is present"); /* Voltage thresholds for rail detection */ @@ -1033,11 +991,9 @@ static void update_vrefs_and_shifters(void) void set_up_comparator(void) { /* Overwrite any previous values. This is the only comparator usage */ - STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI | - STM32_COMP_CMP2OUTSEL_NONE | + STM32_COMP_CSR = STM32_COMP_CMP2HYST_HI | STM32_COMP_CMP2OUTSEL_NONE | STM32_COMP_CMP2INSEL_INM5 | /* Watch DAC_OUT2 (PA5) */ - STM32_COMP_CMP2MODE_LSPEED | - STM32_COMP_CMP2EN; + STM32_COMP_CMP2MODE_LSPEED | STM32_COMP_CMP2EN; /* Set Falling and Rising interrupts for COMP2 */ STM32_EXTI_FTSR |= EXTI_COMP2_EVENT; -- cgit v1.2.1 From 7e70d787d4f45c378f8d53de71bb52380428ce12 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:53 -0600 Subject: chip/stm32/i2c-stm32l4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85e38d123963642991d9ffb9271dcd38b252d022 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729519 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32l4.c | 69 ++++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 35 deletions(-) diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c index f7d311ba87..851adad21c 100644 --- a/chip/stm32/i2c-stm32l4.c +++ b/chip/stm32/i2c-stm32l4.c @@ -21,13 +21,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS -#define I2C_SLAVE_ERROR_CODE 0xec +#define I2C_SLAVE_ERROR_CODE 0xec #if (I2C_PORT_EC == STM32_I2C1_PORT) #define IRQ_SLAVE STM32_IRQ_I2C1 #else @@ -37,8 +37,8 @@ /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -50,8 +50,8 @@ void i2c_set_timeout(int port, uint32_t timeout) /* timing register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /** @@ -70,7 +70,7 @@ static int wait_isr(int port, int mask) /* Check for errors */ if (isr & (STM32_I2C_ISR_ARLO | STM32_I2C_ISR_BERR | - STM32_I2C_ISR_NACK)) + STM32_I2C_ISR_NACK)) return EC_ERROR_UNKNOWN; /* Check for desired mask */ @@ -115,8 +115,7 @@ static const uint32_t timingr_regs[I2C_CLK_SRC_COUNT][I2C_FREQ_COUNT] = { }; static void i2c_set_freq_port(const struct i2c_port_t *p, - enum stm32_i2c_clk_src src, - enum i2c_freq freq) + enum stm32_i2c_clk_src src, enum i2c_freq freq) { int port = p->port; @@ -209,8 +208,8 @@ static void i2c_event_handler(int port) STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_TXIE; /* Clear error status bits */ - STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF - | STM32_I2C_ICR_ARLOCF; + STM32_I2C_ICR(port) |= STM32_I2C_ICR_BERRCF | + STM32_I2C_ICR_ARLOCF; } /* Transfer matched our slave address */ @@ -286,8 +285,8 @@ static void i2c_event_handler(int port) STM32_I2C_TXDR(port) = slave_buffer[tx_idx++]; } else { - STM32_I2C_TXDR(port) - = I2C_SLAVE_ERROR_CODE; + STM32_I2C_TXDR(port) = + I2C_SLAVE_ERROR_CODE; tx_idx = 0; tx_end = 0; tx_pending = 0; @@ -309,9 +308,8 @@ DECLARE_IRQ(IRQ_SLAVE, i2c_event_interrupt, 2); /*****************************************************************************/ /* Interface */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -335,13 +333,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -364,11 +362,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(port) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -448,7 +446,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } void i2c_init(void) @@ -460,11 +458,12 @@ void i2c_init(void) i2c_init_port(p); #ifdef CONFIG_HOSTCMD_I2C_ADDR_FLAGS - STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE - | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE - | STM32_I2C_CR1_NACKIE; - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 - | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); + STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | + STM32_I2C_CR1_ADDRIE | + STM32_I2C_CR1_STOPIE | + STM32_I2C_CR1_NACKIE; + STM32_I2C_OAR1(I2C_PORT_EC) = + 0x8000 | (I2C_STRIP_FLAGS(CONFIG_HOSTCMD_I2C_ADDR_FLAGS) << 1); task_enable_irq(IRQ_SLAVE); #endif } -- cgit v1.2.1 From c52c4468a799fb68922e2d69a944e88765f7dc23 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:00 -0600 Subject: driver/sb_rmi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd8011f2d1302d621e9d7744845a25923212d5b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730062 Reviewed-by: Jeremy Bettis --- driver/sb_rmi.c | 59 ++++++++++++++++++++++++++++----------------------------- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c index 49783188e1..44bf4b9f42 100644 --- a/driver/sb_rmi.c +++ b/driver/sb_rmi.c @@ -16,7 +16,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) #define SB_RMI_MAILBOX_TIMEOUT_MS 200 #define SB_RMI_MAILBOX_RETRY_DELAY_MS 5 @@ -47,7 +47,6 @@ static int sb_rmi_assert_interrupt(bool assert) return sb_rmi_write(SB_RMI_SW_INTR_REG, assert ? 0x1 : 0x0); } - /** * Execute a SB-RMI mailbox transaction * @@ -60,34 +59,34 @@ static int sb_rmi_assert_interrupt(bool assert) */ int sb_rmi_mailbox_xfer(int cmd, uint32_t msg_in, uint32_t *msg_out_ptr) { - /** - * The sequence is as follows: - * 1. The initiator (BMC) indicates that command is to be serviced by - * firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F). This - * register must be set to 0x80 after reset. - * 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0 - * (SBRMI_x38). - * 3. For write operations or read operations which require additional - * addressing information as shown in the table above, the initiator - * (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] - * {SBRMI_x3C(MSB):SBRMI_x39(LSB)}. - * 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to - * notify firmware to perform the requested read or write command. - * 5. Firmware reads the message and performs the defined action. - * 6. Firmware writes the original command to outbound message register - * SBRMI::OutBndMsg_inst0 (SBRMI_x30). - * 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an - * ALERT (if enabled) to initiator (BMC) to indicate completion of the - * requested command. Firmware must (if applicable) put the message - * data into the message registers SBRMI::OutBndMsg_inst[4:1] - * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. - * 8. For a read operation, the initiator (BMC) reads the firmware - * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] - * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. - * 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the - * ALERT to initiator (BMC). It is recommended to clear the ALERT - * upon completion of the current mailbox command. - */ + /** + * The sequence is as follows: + * 1. The initiator (BMC) indicates that command is to be serviced by + * firmware by writing 0x80 to SBRMI::InBndMsg_inst7 (SBRMI_x3F). + * This register must be set to 0x80 after reset. + * 2. The initiator (BMC) writes the command to SBRMI::InBndMsg_inst0 + * (SBRMI_x38). + * 3. For write operations or read operations which require additional + * addressing information as shown in the table above, the initiator + * (BMC) writes Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] + * {SBRMI_x3C(MSB):SBRMI_x39(LSB)}. + * 4. The initiator (BMC) writes 0x01 to SBRMI::SoftwareInterrupt to + * notify firmware to perform the requested read or write command. + * 5. Firmware reads the message and performs the defined action. + * 6. Firmware writes the original command to outbound message register + * SBRMI::OutBndMsg_inst0 (SBRMI_x30). + * 7. Firmware will write SBRMI::Status[SwAlertSts]=1 to generate an + * ALERT (if enabled) to initiator (BMC) to indicate completion of + * the requested command. Firmware must (if applicable) put the message + * data into the message registers SBRMI::OutBndMsg_inst[4:1] + * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. + * 8. For a read operation, the initiator (BMC) reads the firmware + * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] + * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. + * 9. BMC must write 1'b1 to SBRMI::Status[SwAlertSts] to clear the + * ALERT to initiator (BMC). It is recommended to clear the ALERT + * upon completion of the current mailbox command. + */ int val; bool alerted; timestamp_t start; -- cgit v1.2.1 From eaafb478a26ae92c653d35675ea78ff8596c9380 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:21 -0600 Subject: baseboard/hatch/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic030dc6a3c2d35fbccabd593aaf5304c91676964 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727522 Reviewed-by: Jeremy Bettis --- baseboard/hatch/baseboard.h | 50 ++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h index dc39fcf8ac..866118de1a 100644 --- a/baseboard/hatch/baseboard.h +++ b/baseboard/hatch/baseboard.h @@ -15,13 +15,13 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) #define CONFIG_SPI_FLASH_REGS @@ -111,14 +111,14 @@ /* Common battery defines */ #define CONFIG_BATTERY_CUT_OFF -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_HW_PRESENT_CUSTOM #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_SMART -#undef CONFIG_BATT_HOST_FULL_FACTOR -#define CONFIG_BATT_HOST_FULL_FACTOR 100 +#undef CONFIG_BATT_HOST_FULL_FACTOR +#define CONFIG_BATT_HOST_FULL_FACTOR 100 /* USB Type C and USB PD defines */ #define CONFIG_USB_POWER_DELIVERY @@ -153,9 +153,9 @@ /* Include CLI command needed to support CCD testing. */ #define CONFIG_CMD_CHARGEN -#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_0 0 #if CONFIG_USB_PD_PORT_MAX_COUNT > 1 -#define USB_PD_PORT_TCPC_1 1 +#define USB_PD_PORT_TCPC_1 1 #endif /* BC 1.2 */ @@ -167,32 +167,32 @@ #endif /* TODO(b/122273953): Use correct PD delay values */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* TODO(b/122273953): Use correct PD power values */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_THERMAL NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER /* Other common defines */ #define CONFIG_BACKLIGHT_LID -#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD +#define GPIO_ENABLE_BACKLIGHT GPIO_EDP_BKLTEN_OD #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) -- cgit v1.2.1 From d3696fb8095337350b66da8c0e8164770b6893d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:24 -0600 Subject: board/quiche/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I831dc7afc2081b88731c46114d8548d3aa0381f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728851 Reviewed-by: Jeremy Bettis --- board/quiche/board.c | 98 +++++++++++++++++++++++----------------------------- 1 file changed, 44 insertions(+), 54 deletions(-) diff --git a/board/quiche/board.c b/board/quiche/board.c index 67d4c00297..95a69286a7 100644 --- a/board/quiche/board.c +++ b/board/quiche/board.c @@ -29,8 +29,8 @@ #include "usb_tc_sm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define QUICHE_PD_DEBUG_LVL 1 @@ -104,29 +104,29 @@ static void board_usbc_usb3_interrupt(enum gpio_signal signal) * signals is driven by USB/MST hub power sequencing requirements. */ const struct power_seq board_power_seq[] = { - {GPIO_EN_AC_JACK, 1, 20}, - {GPIO_EC_DFU_MUX_CTRL, 0, 0}, - {GPIO_EN_PP5000_A, 1, 31}, - {GPIO_MST_LP_CTL_L, 1, 0}, - {GPIO_EN_PP3300_B, 1, 1}, - {GPIO_EN_PP1100_A, 1, 100+30}, - {GPIO_EN_BB, 1, 30}, - {GPIO_EN_PP1050_A, 1, 30}, - {GPIO_EN_PP1200_A, 1, 20}, - {GPIO_EN_PP5000_C, 1, 20}, - {GPIO_EN_PP5000_HSPORT, 1, 31}, - {GPIO_EN_DP_SINK, 1, 80}, - {GPIO_MST_RST_L, 1, 61}, - {GPIO_EC_HUB2_RESET_L, 1, 41}, - {GPIO_EC_HUB3_RESET_L, 1, 33}, - {GPIO_DP_SINK_RESET, 1, 100}, - {GPIO_USBC_DP_PD_RST_L, 1, 100}, - {GPIO_USBC_UF_RESET_L, 1, 33}, - {GPIO_DEMUX_DUAL_DP_PD_N, 1, 100}, - {GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100}, - {GPIO_DEMUX_DP_HDMI_PD_N, 1, 10}, - {GPIO_DEMUX_DUAL_DP_MODE, 1, 10}, - {GPIO_DEMUX_DP_HDMI_MODE, 1, 5}, + { GPIO_EN_AC_JACK, 1, 20 }, + { GPIO_EC_DFU_MUX_CTRL, 0, 0 }, + { GPIO_EN_PP5000_A, 1, 31 }, + { GPIO_MST_LP_CTL_L, 1, 0 }, + { GPIO_EN_PP3300_B, 1, 1 }, + { GPIO_EN_PP1100_A, 1, 100 + 30 }, + { GPIO_EN_BB, 1, 30 }, + { GPIO_EN_PP1050_A, 1, 30 }, + { GPIO_EN_PP1200_A, 1, 20 }, + { GPIO_EN_PP5000_C, 1, 20 }, + { GPIO_EN_PP5000_HSPORT, 1, 31 }, + { GPIO_EN_DP_SINK, 1, 80 }, + { GPIO_MST_RST_L, 1, 61 }, + { GPIO_EC_HUB2_RESET_L, 1, 41 }, + { GPIO_EC_HUB3_RESET_L, 1, 33 }, + { GPIO_DP_SINK_RESET, 1, 100 }, + { GPIO_USBC_DP_PD_RST_L, 1, 100 }, + { GPIO_USBC_UF_RESET_L, 1, 33 }, + { GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 }, + { GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 }, + { GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 }, + { GPIO_DEMUX_DUAL_DP_MODE, 1, 10 }, + { GPIO_DEMUX_DP_HDMI_MODE, 1, 5 }, }; const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); @@ -134,13 +134,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Quiche"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Quiche"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -159,8 +159,7 @@ struct ppc_config_t ppc_chips[] = { * PS8802 set mux board tuning. * Adds in board specific gain and DP lane count configuration */ -static int board_ps8822_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8822_mux_set(const struct usb_mux *me, mux_state_t mux_state) { int rv = EC_SUCCESS; @@ -206,21 +205,15 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_HOST] = { - .i2c_port = I2C_PORT_I2C1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_DP] = { - .i2c_port = I2C_PORT_I2C1, - .i2c_addr_flags = SN5S330_ADDR2_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_USB3] = { - .i2c_port = I2C_PORT_I2C3, - .i2c_addr_flags = SN5S330_ADDR1_FLAGS, - .drv = &sn5s330_drv - }, + [USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_DP] = { .i2c_port = I2C_PORT_I2C1, + .i2c_addr_flags = SN5S330_ADDR2_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_USB3] = { .i2c_port = I2C_PORT_I2C3, + .i2c_addr_flags = SN5S330_ADDR1_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -366,14 +359,13 @@ static void board_usb_tc_disconnect(void) if (port == USB_PD_PORT_HOST) gpio_set_level(GPIO_UFP_PLUG_DET, 1); } -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \ +DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, HOOK_PRIO_DEFAULT); #endif /* SECTION_IS_RW */ static void board_init(void) { - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -438,6 +430,4 @@ static int command_dplane(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dplane, command_dplane, - "<2 | 4>", - "MST lane control."); +DECLARE_CONSOLE_COMMAND(dplane, command_dplane, "<2 | 4>", "MST lane control."); -- cgit v1.2.1 From bc9b85a9bdf1bccbd1ea17b2149e3d0b2be4cb11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:01 -0600 Subject: zephyr/projects/nissa/src/nereid/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38380e0d2ce954b3ab30d19dd3213232104753fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730789 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nereid/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/nissa/src/nereid/keyboard.c b/zephyr/projects/nissa/src/nereid/keyboard.c index d0d1406307..0671b6570d 100644 --- a/zephyr/projects/nissa/src/nereid/keyboard.c +++ b/zephyr/projects/nissa/src/nereid/keyboard.c @@ -22,8 +22,8 @@ static const struct ec_response_keybd_config nereid_kb_legacy = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &nereid_kb_legacy; } -- cgit v1.2.1 From e3d469a416dd9dab297931e17e8baf70be93880d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:56 -0600 Subject: board/felwinter/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba826c145fd31886d9544b28f675b5533e9383db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728352 Reviewed-by: Jeremy Bettis --- board/felwinter/board.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/board/felwinter/board.c b/board/felwinter/board.c index 7f39e58336..461b629374 100644 --- a/board/felwinter/board.c +++ b/board/felwinter/board.c @@ -29,8 +29,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /******************************************************************************/ /* USB-A charging control */ @@ -94,8 +94,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } @@ -126,7 +126,6 @@ static void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - /** * Deferred function to handle pen detect change */ @@ -149,8 +148,7 @@ DECLARE_HOOK(HOOK_INIT, pendetect_deferred, HOOK_PRIO_DEFAULT); void pen_detect_interrupt(enum gpio_signal s) { /* Trigger deferred notification of pen detect change */ - hook_call_deferred(&pendetect_deferred_data, - 500 * MSEC); + hook_call_deferred(&pendetect_deferred_data, 500 * MSEC); } void pen_config(void) -- cgit v1.2.1 From 815e5d3b08527a964a61f8c2994acfd570bbf7ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:53 -0600 Subject: test/is_enabled.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ieb284e7aa3cba9094dfab7f60377d5db6fa5bc36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730508 Reviewed-by: Jeremy Bettis --- test/is_enabled.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/is_enabled.c b/test/is_enabled.c index fe93bafc31..4813eb4734 100644 --- a/test/is_enabled.c +++ b/test/is_enabled.c @@ -7,8 +7,8 @@ #include "common.h" #include "test_util.h" -#undef CONFIG_UNDEFINED -#define CONFIG_BLANK +#undef CONFIG_UNDEFINED +#define CONFIG_BLANK static int test_undef(void) { -- cgit v1.2.1 From 8f073a32a1aa526f04bd01c31f282897d8f78332 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:16 -0600 Subject: include/driver/als_tcs3400_public.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c59ffad975a95cdd2e7143d5234b920f2636420 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730272 Reviewed-by: Jeremy Bettis --- include/driver/als_tcs3400_public.h | 45 +++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/include/driver/als_tcs3400_public.h b/include/driver/als_tcs3400_public.h index 812aeda8d3..ed3b5e5f63 100644 --- a/include/driver/als_tcs3400_public.h +++ b/include/driver/als_tcs3400_public.h @@ -11,34 +11,34 @@ #include "accelgyro.h" /* I2C Interface */ -#define TCS3400_I2C_ADDR_FLAGS 0x39 +#define TCS3400_I2C_ADDR_FLAGS 0x39 /* NOTE: The higher the ATIME value in reg, the shorter the accumulation time */ -#define TCS_MIN_ATIME 0x00 /* 712 ms */ -#define TCS_MAX_ATIME 0x70 /* 400 ms */ -#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ -#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ -#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ -#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME -#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME +#define TCS_MIN_ATIME 0x00 /* 712 ms */ +#define TCS_MAX_ATIME 0x70 /* 400 ms */ +#define TCS_ATIME_GRANULARITY 256 /* 256 atime settings */ +#define TCS_SATURATION_LEVEL 0xffff /* for 0 < atime < 0x70 */ +#define TCS_DEFAULT_ATIME TCS_MIN_ATIME /* 712 ms */ +#define TCS_CALIBRATION_ATIME TCS_MIN_ATIME +#define TCS_GAIN_UPSHIFT_ATIME TCS_MAX_ATIME /* Number of different ranges supported for atime adjustment support */ -#define TCS_MAX_ATIME_RANGES 13 -#define TCS_GAIN_TABLE_MAX_LUX 12999 -#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ +#define TCS_MAX_ATIME_RANGES 13 +#define TCS_GAIN_TABLE_MAX_LUX 12999 +#define TCS_ATIME_GAIN_FACTOR 100 /* table values are 100x actual value */ -#define TCS_MIN_AGAIN 0x00 /* 1x gain */ -#define TCS_MAX_AGAIN 0x03 /* 64x gain */ -#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ -#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN +#define TCS_MIN_AGAIN 0x00 /* 1x gain */ +#define TCS_MAX_AGAIN 0x03 /* 64x gain */ +#define TCS_CALIBRATION_AGAIN 0x02 /* 16x gain */ +#define TCS_DEFAULT_AGAIN TCS_CALIBRATION_AGAIN #define TCS_MAX_INTEGRATION_TIME 2780 /* 2780us */ -#define TCS_ATIME_DEC_STEP 5 -#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME +#define TCS_ATIME_DEC_STEP 5 +#define TCS_ATIME_INC_STEP TCS_GAIN_UPSHIFT_ATIME /* Min and Max sampling frequency in mHz */ -#define TCS3400_LIGHT_MIN_FREQ 149 -#define TCS3400_LIGHT_MAX_FREQ 1000 +#define TCS3400_LIGHT_MIN_FREQ 149 +#define TCS3400_LIGHT_MAX_FREQ 1000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= TCS3400_LIGHT_MAX_FREQ) #error "EC too slow for light sensor" #endif @@ -55,15 +55,16 @@ struct tcs_saturation_t { uint8_t again; /* Acquisition Time, controlled by the ATIME register */ - uint8_t atime; /* ATIME register setting */ + uint8_t atime; /* ATIME register setting */ }; /* tcs3400 rgb als driver data */ struct tcs3400_rgb_drv_data_t { - uint8_t calibration_mode;/* 0 = normal run mode, 1 = calibration mode */ + uint8_t calibration_mode; /* 0 = normal run mode, 1 = calibration mode + */ struct rgb_calibration_t calibration; - struct tcs_saturation_t saturation; /* saturation adjustment */ + struct tcs_saturation_t saturation; /* saturation adjustment */ }; extern const struct accelgyro_drv tcs3400_drv; -- cgit v1.2.1 From 3009a140bbde4618bde4228cb577b4cd5b6a8c18 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:02 -0600 Subject: board/gumboz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfd25d222c096ed0301d9311cd6d3923b48e9cf0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728434 Reviewed-by: Jeremy Bettis --- board/gumboz/board.h | 83 +++++++++++++++++++--------------------------------- 1 file changed, 30 insertions(+), 53 deletions(-) diff --git a/board/gumboz/board.h b/board/gumboz/board.h index 42e2b23c32..415d797132 100644 --- a/board/gumboz/board.h +++ b/board/gumboz/board.h @@ -20,7 +20,7 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PORT_ENABLE_DYNAMIC -#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000 #define CONFIG_CHARGER_PROFILE_OVERRIDE @@ -38,7 +38,7 @@ #define CONFIG_ACCELGYRO_LSM6DSM #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO #define CONFIG_TABLET_MODE @@ -48,42 +48,36 @@ #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL #define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL - - /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ /* This I2C moved. Temporarily detect and support the V0 HW. */ extern int I2C_PORT_BATTERY; -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_SIMPLO_COS, @@ -95,20 +89,11 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; -enum ioex_port { - IOEX_C0_NCT3807 = 0, - IOEX_C1_NCT3807, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT }; -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB3_C0_DP2_HPD \ - : GPIO_DP1_HPD) +#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD) enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -117,17 +102,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration -- cgit v1.2.1 From 2ec1a3fcefc38cc14005ed518a46ab2150dc7c04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:22 -0600 Subject: include/rgb_keyboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f9d08aa335a834245440b52040b5038c09f58d7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730396 Reviewed-by: Jeremy Bettis --- include/rgb_keyboard.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h index e795389225..d1454b0af0 100644 --- a/include/rgb_keyboard.h +++ b/include/rgb_keyboard.h @@ -10,16 +10,16 @@ #include "stddef.h" /* Use this instead of '3' for readability where applicable. */ -#define SIZE_OF_RGB sizeof(struct rgb_s) +#define SIZE_OF_RGB sizeof(struct rgb_s) -#define RGBKBD_MAX_GCC_LEVEL 0xff -#define RGBKBD_MAX_SCALE 0xff +#define RGBKBD_MAX_GCC_LEVEL 0xff +#define RGBKBD_MAX_SCALE 0xff -#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0]) +#define RGBKBD_CTX_TO_GRID(ctx) ((ctx) - &rgbkbds[0]) struct rgbkbd_cfg { /* Driver for LED IC */ - const struct rgbkbd_drv * const drv; + const struct rgbkbd_drv *const drv; /* SPI/I2C port (i.e. index of spi_devices[], i2c_ports[]) */ union { const uint8_t i2c; @@ -50,7 +50,7 @@ void rgbkbd_register_init_setting(const struct rgbkbd_init *setting); struct rgbkbd { /* Static configuration */ - const struct rgbkbd_cfg * const cfg; + const struct rgbkbd_cfg *const cfg; /* Current state of the port */ enum rgbkbd_state state; /* Buffer containing color info for each dot. */ @@ -85,8 +85,8 @@ struct rgbkbd_drv { * @param len Length of LEDs to be set. * @return enum ec_error_list */ - int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, - struct rgb_s scale, uint8_t len); + int (*set_scale)(struct rgbkbd *ctx, uint8_t offset, struct rgb_s scale, + uint8_t len); /** * Set global current control. * @@ -98,24 +98,24 @@ struct rgbkbd_drv { /* Represents a position of an LED in RGB matrix. */ struct rgbkbd_coord { - uint8_t y: 3; - uint8_t x: 5; + uint8_t y : 3; + uint8_t x : 5; }; - /* - * For optimization, LED coordinates are encoded in LED IDs. This saves us one - * translation. - */ +/* + * For optimization, LED coordinates are encoded in LED IDs. This saves us one + * translation. + */ union rgbkbd_coord_u8 { uint8_t u8; struct rgbkbd_coord coord; }; -#define RGBKBD_COORD(x,y) ((x) << 3 | (y)) +#define RGBKBD_COORD(x, y) ((x) << 3 | (y)) /* Delimiter for rgbkbd_map data */ -#define RGBKBD_DELM 0xff +#define RGBKBD_DELM 0xff /* Non-existent entry indicator for rgbkbd_table */ -#define RGBKBD_NONE 0x00 +#define RGBKBD_NONE 0x00 /* * The matrix consists of multiple grids: -- cgit v1.2.1 From 4b21a7d51fec2d3a6fdf0c71ecfc27b3c89a9d3b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:05 -0600 Subject: baseboard/intelrvp/ite_ec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib84307675577aacc93bf93da9f211d33b59412ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727898 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/ite_ec.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c index bafddc5f9e..15ed50d92c 100644 --- a/baseboard/intelrvp/ite_ec.c +++ b/baseboard/intelrvp/ite_ec.c @@ -139,15 +139,15 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) * enabling the VCONN on respective CC line */ gpio_set_level(tcpc_gpios[port].vconn.cc1_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); gpio_set_level(tcpc_gpios[port].vconn.cc2_pin, - !tcpc_gpios[port].vconn.pin_pol); + !tcpc_gpios[port].vconn.pin_pol); if (enabled) gpio_set_level((cc_pin != USBPD_CC_PIN_1) ? - tcpc_gpios[port].vconn.cc2_pin : - tcpc_gpios[port].vconn.cc1_pin, - tcpc_gpios[port].vconn.pin_pol); + tcpc_gpios[port].vconn.cc2_pin : + tcpc_gpios[port].vconn.cc1_pin, + tcpc_gpios[port].vconn.pin_pol); #endif } #endif -- cgit v1.2.1 From 046039b468f51449a11dc526d5d13c7ffaca8269 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:43 -0600 Subject: board/servo_v4p1/chg_control.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I437e08312a800cd9b47ad225626e582e40fb6fc1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728923 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/chg_control.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/board/servo_v4p1/chg_control.c b/board/servo_v4p1/chg_control.c index 19be03a755..8cbbacf019 100644 --- a/board/servo_v4p1/chg_control.c +++ b/board/servo_v4p1/chg_control.c @@ -10,7 +10,7 @@ #include "timer.h" #include "usb_pd.h" -#define CHG_P5V_POWER 0 +#define CHG_P5V_POWER 0 #define CHG_VBUS_POWER 1 void chg_reset(void) @@ -55,9 +55,11 @@ void chg_attach_cc_rds(bool en) * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as * ANALOG input */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*2)) | /* PA2 in ANALOG mode */ - (3 << (2*4))); /* PA4 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2)) | /* PA2 in + ANALOG + mode */ + (3 << (2 * 4))); /* PA4 in ANALOG mode */ } else { /* * Configure USB_CHG_CC1_MCU and USB_CHG_CC2_MCU as GPIO and @@ -71,10 +73,12 @@ void chg_attach_cc_rds(bool en) gpio_set_level(GPIO_USB_CHG_CC2_MCU, 1); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*2) | /* PA2 disable ADC */ - 3 << (2*4))) /* PA4 disable ADC */ - | (1 << (2*2) | /* Set as GPO */ - 1 << (2*4)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) & + ~(3 << (2 * 2) | /* PA2 disable ADC + */ + 3 << (2 * 4))) /* PA4 disable ADC + */ + | (1 << (2 * 2) | /* Set as GPO */ + 1 << (2 * 4)); /* Set as GPO */ } } -- cgit v1.2.1 From e82ce6928170220c8ba6483fd3d4f3458b01d12b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:10 -0600 Subject: include/link_defs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e56e7686e7f662bebbb49b633d85d5f6f8d9694 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730306 Reviewed-by: Jeremy Bettis --- include/link_defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/link_defs.h b/include/link_defs.h index d0558b396a..4c0c29b589 100644 --- a/include/link_defs.h +++ b/include/link_defs.h @@ -133,7 +133,7 @@ extern void *__dram_bss_end; /* Helper for special chip-specific memory sections */ #if defined(CONFIG_CHIP_MEMORY_REGIONS) || defined(CONFIG_DRAM_BASE) #define __SECTION(name) __attribute__((section("." STRINGIFY(name) ".50_auto"))) -#define __SECTION_KEEP(name) \ +#define __SECTION_KEEP(name) \ __keep __attribute__((section("." STRINGIFY(name) ".keep.50_auto"))) #else #define __SECTION(name) @@ -148,7 +148,7 @@ extern void *__dram_bss_end; #endif /* __CROS_EC_LINK_DEFS_H */ #ifdef CONFIG_PRESERVE_LOGS -#define __preserved_logs(name) \ +#define __preserved_logs(name) \ __attribute__((section(".preserved_logs." STRINGIFY(name)))) /* preserved_logs section. */ extern const char __preserved_logs_start[]; -- cgit v1.2.1 From 5b25ea272709a3e52100916f0192b19557237c6c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:44 -0600 Subject: include/power/alderlake_slg4bd44540.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic48a4c3ce2e4c4f2451acbc1e4f03eda52ecc942 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730381 Reviewed-by: Jeremy Bettis --- include/power/alderlake_slg4bd44540.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/power/alderlake_slg4bd44540.h b/include/power/alderlake_slg4bd44540.h index 387a583240..eb72df5a39 100644 --- a/include/power/alderlake_slg4bd44540.h +++ b/include/power/alderlake_slg4bd44540.h @@ -12,13 +12,13 @@ #define __CROS_EC_ALDERLAKE_SLG4BD44540_H /* Input state flags. */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) +#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) +#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) #define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) +#define IN_ALL_PM_SLP_DEASSERTED \ + (IN_PCH_SLP_S3_DEASSERTED | IN_PCH_SLP_S4_DEASSERTED | \ + IN_PCH_SLP_SUS_DEASSERTED) #define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_DSW_DPWROK) -- cgit v1.2.1 From 848ebe5e2f14f1bbf5c3b7f0fd10e950901ea208 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:29 -0600 Subject: board/rainier/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4948071e57ba05da9260708fde94b5b67cf73e81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728873 Reviewed-by: Jeremy Bettis --- board/rainier/board.c | 95 ++++++++++++++++++++++++--------------------------- 1 file changed, 44 insertions(+), 51 deletions(-) diff --git a/board/rainier/board.c b/board/rainier/board.c index c992584d76..6384859b72 100644 --- a/board/rainier/board.c +++ b/board/rainier/board.c @@ -40,8 +40,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -65,41 +65,39 @@ static void warm_reset_request_interrupt(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 16, 4096, 0, STM32_AIN(10)}, + [ADC_BOARD_ID] = { "BOARD_ID", 16, 4096, 0, STM32_AIN(10) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD"}, - {GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD"}, - {GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD"}, - {GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED"}, + { GPIO_PP1250_S3_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP1250_S3_PWR_GOOD" }, + { GPIO_PP900_S0_PG, POWER_SIGNAL_ACTIVE_HIGH, "PP900_S0_PWR_GOOD" }, + { GPIO_AP_CORE_PG, POWER_SIGNAL_ACTIVE_HIGH, "AP_PWR_GOOD" }, + { GPIO_AP_EC_S3_S0_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND_DEASSERTED" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); #ifdef CONFIG_TEMP_SENSOR_TMP432 /* Temperature sensors data; must be in same order as enum temp_sensor_id. */ const struct temp_sensor_t temp_sensors[] = { - {"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL, 4}, - {"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1, 4}, - {"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE2, 4}, + { "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL, 4 }, + { "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1, 4 }, + { "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE2, 4 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -108,9 +106,9 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); * same order as enum temp_sensor_id. To always ignore any temp, use 0. */ struct ec_thermal_config thermal_params[] = { - {{0, 0, 0}, 0, 0}, /* TMP432_Internal */ - {{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */ - {{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Internal */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_1 */ + { { 0, 0, 0 }, 0, 0 }, /* TMP432_Sensor_2 */ }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); #endif @@ -125,9 +123,8 @@ const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* Wake-up pins for hibernate */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_POWER_BUTTON_L, GPIO_CHARGER_INT_L -}; +const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, + GPIO_CHARGER_INT_L }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ @@ -173,8 +170,8 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * NOP because there is no internal power therefore no charging. @@ -190,7 +187,7 @@ int extpower_is_present(void) int pd_snk_is_vbus_provided(int port) { - /* Must be, if we're at a stage where this function is called. */ + /* Must be, if we're at a stage where this function is called. */ return 1; } @@ -207,8 +204,7 @@ static void board_spi_enable(void) spi_enable(&spi_devices[0], 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -220,9 +216,8 @@ static void board_spi_disable(void) gpio_config_module(MODULE_SPI_CONTROLLER, 0); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, - MOTION_SENSE_HOOK_PRIO + 1); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, + MOTION_SENSE_HOOK_PRIO + 1); static void board_init(void) { @@ -255,8 +250,8 @@ void board_config_pre_init(void) * Ch4: USART1_TX / Ch5: USART1_RX (1000) * Ch6: SPI2_RX / Ch7: SPI2_TX (0011) */ - STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | - (3 << 20) | (3 << 24); + STM32_DMA_CSELR(STM32_DMAC_CH4) = (8 << 12) | (8 << 16) | (3 << 20) | + (3 << 24); } void board_hibernate(void) @@ -301,16 +296,16 @@ struct { enum rainier_board_version version; int expect_mv; } const rainier_boards[] = { - { BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */ - { BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */ - { BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */ - { BOARD_VERSION_REV3, 427 }, /* 56K , 17.4K ohm */ - { BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */ - { BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */ - { BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */ - { BOARD_VERSION_REV7, 900 }, /* 56K , 56K ohm */ - { BOARD_VERSION_REV8, 1023 }, /* 47K , 61.9K ohm */ - { BOARD_VERSION_REV9, 1137 }, /* 47K , 80.6K ohm */ + { BOARD_VERSION_REV0, 109 }, /* 51.1K , 2.2K(gru 3.3K) ohm */ + { BOARD_VERSION_REV1, 211 }, /* 51.1k , 6.8K ohm */ + { BOARD_VERSION_REV2, 319 }, /* 51.1K , 11K ohm */ + { BOARD_VERSION_REV3, 427 }, /* 56K , 17.4K ohm */ + { BOARD_VERSION_REV4, 542 }, /* 51.1K , 22K ohm */ + { BOARD_VERSION_REV5, 666 }, /* 51.1K , 30K ohm */ + { BOARD_VERSION_REV6, 781 }, /* 51.1K , 39.2K ohm */ + { BOARD_VERSION_REV7, 900 }, /* 56K , 56K ohm */ + { BOARD_VERSION_REV8, 1023 }, /* 47K , 61.9K ohm */ + { BOARD_VERSION_REV9, 1137 }, /* 47K , 80.6K ohm */ { BOARD_VERSION_REV10, 1240 }, /* 56K , 124K ohm */ { BOARD_VERSION_REV11, 1343 }, /* 51.1K , 150K ohm */ { BOARD_VERSION_REV12, 1457 }, /* 47K , 200K ohm */ @@ -358,11 +353,9 @@ static struct mutex g_base_mutex; static struct bmi_drv_data_t g_bmi160_data; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct bmp280_drv_data_t bmp280_drv_data; -- cgit v1.2.1 From 7da9f0402ed27c5892aab5a7dd6a4370b1c92964 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:08 -0600 Subject: board/dooly/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic7a0f081ee1d563aeef0bb4d55b79069cb133d29 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726418 Reviewed-by: Jeremy Bettis --- board/dooly/led.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/dooly/led.c b/board/dooly/led.c index fefa8908fe..c8f0405260 100644 --- a/board/dooly/led.c +++ b/board/dooly/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -88,9 +88,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented -- cgit v1.2.1 From e63b4fdfc21c884775a7a15605f25b8f431aa815 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:57 -0600 Subject: driver/battery/max17055.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9bed5565ebb58ff2abe83f9a3902cf97cfcaf077 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729949 Reviewed-by: Jeremy Bettis --- driver/battery/max17055.c | 60 +++++++++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/driver/battery/max17055.c b/driver/battery/max17055.c index bb0b941937..382995d0df 100644 --- a/driver/battery/max17055.c +++ b/driver/battery/max17055.c @@ -16,13 +16,13 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* * For max17055 to finish battery presence detection, this is the minimal time * we have to wait since the last POR. LSB = 175ms. */ -#define RELIABLE_BATT_DETECT_TIME 0x10 +#define RELIABLE_BATT_DETECT_TIME 0x10 /* * Convert the register values to the units that match @@ -30,50 +30,48 @@ */ /* Voltage reg value to mV */ -#define VOLTAGE_CONV(REG) ((REG * 5) >> 6) +#define VOLTAGE_CONV(REG) ((REG * 5) >> 6) /* Current reg value to mA */ -#define CURRENT_CONV(REG) (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE) +#define CURRENT_CONV(REG) (((REG * 25) >> 4) / BATTERY_MAX17055_RSENSE) /* Capacity reg value to mAh */ -#define CAPACITY_CONV(REG) (REG * 5 / BATTERY_MAX17055_RSENSE) +#define CAPACITY_CONV(REG) (REG * 5 / BATTERY_MAX17055_RSENSE) /* Time reg value to minute */ -#define TIME_CONV(REG) ((REG * 3) >> 5) +#define TIME_CONV(REG) ((REG * 3) >> 5) /* Temperature reg value to 0.1K */ -#define TEMPERATURE_CONV(REG) (((REG * 10) >> 8) + 2731) +#define TEMPERATURE_CONV(REG) (((REG * 10) >> 8) + 2731) /* Percentage reg value to 1% */ -#define PERCENTAGE_CONV(REG) (REG >> 8) +#define PERCENTAGE_CONV(REG) (REG >> 8) /* Cycle count reg value (LSB = 1%) to absolute count (100%) */ -#define CYCLE_COUNT_CONV(REG) ((REG * 5) >> 9) +#define CYCLE_COUNT_CONV(REG) ((REG * 5) >> 9) /* Useful macros */ -#define MAX17055_READ_DEBUG(offset, ptr_reg) \ - do { \ - if (max17055_read(offset, ptr_reg)) { \ - CPRINTS("%s: failed to read reg %02x", \ - __func__, offset); \ - return; \ - } \ +#define MAX17055_READ_DEBUG(offset, ptr_reg) \ + do { \ + if (max17055_read(offset, ptr_reg)) { \ + CPRINTS("%s: failed to read reg %02x", __func__, \ + offset); \ + return; \ + } \ } while (0) -#define MAX17055_WRITE_DEBUG(offset, reg) \ - do { \ - if (max17055_write(offset, reg)) { \ - CPRINTS("%s: failed to read reg %02x", \ - __func__, offset); \ - return; \ - } \ +#define MAX17055_WRITE_DEBUG(offset, reg) \ + do { \ + if (max17055_write(offset, reg)) { \ + CPRINTS("%s: failed to read reg %02x", __func__, \ + offset); \ + return; \ + } \ } while (0) static int fake_state_of_charge = -1; static int max17055_read(int offset, int *data) { - return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, - offset, data); + return i2c_read16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data); } static int max17055_write(int offset, int data) { - return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, - offset, data); + return i2c_write16(I2C_PORT_BATTERY, MAX17055_ADDR_FLAGS, offset, data); } /* Return 1 if the device id is correct. */ @@ -269,7 +267,7 @@ enum battery_present battery_is_present(void) void battery_get_params(struct batt_params *batt) { int reg = 0; - struct batt_params batt_new = {0}; + struct batt_params batt_new = { 0 }; /* * Assuming the battery is responsive as long as @@ -293,7 +291,8 @@ void battery_get_params(struct batt_params *batt) batt_new.flags |= BATT_FLAG_BAD_STATE_OF_CHARGE; batt_new.state_of_charge = fake_state_of_charge >= 0 ? - fake_state_of_charge : PERCENTAGE_CONV(reg); + fake_state_of_charge : + PERCENTAGE_CONV(reg); if (max17055_read(REG_VOLTAGE, ®)) batt_new.flags |= BATT_FLAG_BAD_VOLTAGE; @@ -319,8 +318,7 @@ void battery_get_params(struct batt_params *batt) * and battery isn't full (and we read them all correctly). */ if (!(batt_new.flags & BATT_FLAG_BAD_STATE_OF_CHARGE) && - batt_new.desired_voltage && - batt_new.desired_current && + batt_new.desired_voltage && batt_new.desired_current && batt_new.state_of_charge < BATTERY_LEVEL_FULL) batt_new.flags |= BATT_FLAG_WANT_CHARGE; -- cgit v1.2.1 From 2c06aad3234f147d3251619ffe3f44cc536128fb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:59 -0600 Subject: include/btle_hci2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I489b5815a49a821592952036f821f448f9c885c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730215 Reviewed-by: Jeremy Bettis --- include/btle_hci2.h | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/include/btle_hci2.h b/include/btle_hci2.h index 193df3391b..afcc1669c4 100644 --- a/include/btle_hci2.h +++ b/include/btle_hci2.h @@ -14,40 +14,39 @@ struct hciCmdHdr { uint16_t opcode; uint8_t paramLen; } __packed; -#define CMD_MAKE_OPCODE(ogf, ocf) ((((uint16_t)((ogf) & 0x3f)) << 10) | ((ocf) & 0x03ff)) -#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f) -#define CMD_GET_OCF(opcode) ((opcode) & 0x03ff) - +#define CMD_MAKE_OPCODE(ogf, ocf) \ + ((((uint16_t)((ogf)&0x3f)) << 10) | ((ocf)&0x03ff)) +#define CMD_GET_OGF(opcode) (((opcode) >> 10) & 0x3f) +#define CMD_GET_OCF(opcode) ((opcode)&0x03ff) struct hciAclHdr { uint16_t hdr; uint16_t len; } __packed; -#define ACL_HDR_MASK_CONN_ID 0x0FFF -#define ACL_HDR_MASK_PB 0x3000 -#define ACL_HDR_MASK_BC 0xC000 -#define ACL_HDR_PB_FIRST_NONAUTO 0x0000 -#define ACL_HDR_PB_CONTINUED 0x1000 -#define ACL_HDR_PB_FIRST_AUTO 0x2000 -#define ACL_HDR_PB_COMPLETE 0x3000 +#define ACL_HDR_MASK_CONN_ID 0x0FFF +#define ACL_HDR_MASK_PB 0x3000 +#define ACL_HDR_MASK_BC 0xC000 +#define ACL_HDR_PB_FIRST_NONAUTO 0x0000 +#define ACL_HDR_PB_CONTINUED 0x1000 +#define ACL_HDR_PB_FIRST_AUTO 0x2000 +#define ACL_HDR_PB_COMPLETE 0x3000 struct hciScoHdr { uint16_t hdr; uint8_t len; } __packed; -#define SCO_HDR_MASK_CONN_ID 0x0FFF -#define SCO_HDR_MASK_STATUS 0x3000 -#define SCO_STATUS_ALL_OK 0x0000 -#define SCO_STATUS_UNKNOWN 0x1000 -#define SCO_STATUS_NO_DATA 0x2000 -#define SCO_STATUS_SOME_DATA 0x3000 +#define SCO_HDR_MASK_CONN_ID 0x0FFF +#define SCO_HDR_MASK_STATUS 0x3000 +#define SCO_STATUS_ALL_OK 0x0000 +#define SCO_STATUS_UNKNOWN 0x1000 +#define SCO_STATUS_NO_DATA 0x2000 +#define SCO_STATUS_SOME_DATA 0x3000 struct hciEvtHdr { uint8_t code; uint8_t len; } __packed; - void hci_cmd(uint8_t *hciCmdbuf); void hci_acl_to_host(uint8_t *data, uint16_t hdr, uint16_t len); void hci_acl_from_host(uint8_t *hciAclbuf); -- cgit v1.2.1 From 1a453b1aee607e944a1afa2ac0b7090678f50846 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:50 -0600 Subject: chip/stm32/flash-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifc962df548e7f0378acd3dc74a15949d893bdad3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729497 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-stm32f3.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index 138e690fcc..cfed457162 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -102,7 +102,7 @@ int crec_flash_physical_get_protect(int block) #elif defined(CHIP_FAMILY_STM32F4) !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) #endif - ); + ); } uint32_t crec_flash_physical_get_protect_flags(void) @@ -137,8 +137,7 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -173,7 +172,7 @@ int crec_flash_physical_restore_state(void) */ if (reset_flags & EC_RESET_FLAG_SYSJUMP) { prev = (const struct flash_wp_state *)system_get_jump_tag( - FLASH_SYSJUMP_TAG, &version, &size); + FLASH_SYSJUMP_TAG, &version, &size); if (prev && version == FLASH_HOOK_VERSION && size == sizeof(*prev)) entire_flash_locked = prev->entire_flash_locked; -- cgit v1.2.1 From 101f0a45945b1b03f2b400452127bd6c2714aeac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:28 -0600 Subject: board/lazor/sku.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie2c359e2631f2e612a53e832a9154d6c1082f991 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728630 Reviewed-by: Jeremy Bettis --- board/lazor/sku.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lazor/sku.c b/board/lazor/sku.c index 1f63d05bf6..d1843b8fe1 100644 --- a/board/lazor/sku.c +++ b/board/lazor/sku.c @@ -14,8 +14,8 @@ #include "system.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static uint8_t sku_id; -- cgit v1.2.1 From e33e72b54f0ce9876bba4f74d9376f12d4b94879 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:56 -0600 Subject: chip/mchp/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb591af36dd71ff47bfea2cdef8d398b1c61a89b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729240 Reviewed-by: Jeremy Bettis --- chip/mchp/adc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/chip/mchp/adc.c b/chip/mchp/adc.c index 9de5476077..fb7b332d08 100644 --- a/chip/mchp/adc.c +++ b/chip/mchp/adc.c @@ -53,7 +53,7 @@ static int start_single_and_wait(int timeout) /* clear GIRQ single status */ MCHP_INT_SOURCE(MCHP_ADC_GIRQ) = MCHP_ADC_GIRQ_SINGLE_BIT; /* make sure all writes are issued before starting conversion */ - asm volatile ("dsb"); + asm volatile("dsb"); /* Start conversion */ MCHP_ADC_CTRL |= BIT(1); @@ -77,7 +77,8 @@ int adc_read_channel(enum adc_channel ch) if (start_single_and_wait(ADC_SINGLE_READ_TIME)) value = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) / - adc->factor_div + adc->shift; + adc->factor_div + + adc->shift; else value = ADC_READ_ERROR; @@ -105,7 +106,8 @@ int adc_read_all_channels(int *data) for (i = 0; i < ADC_CH_COUNT; ++i) { adc = adc_channels + i; data[i] = (MCHP_ADC_READ(adc->channel) * adc->factor_mul) / - adc->factor_div + adc->shift; + adc->factor_div + + adc->shift; } exit_all_channels: -- cgit v1.2.1 From 9850d03b492dfd9da9271bd485feb376bd2a115a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:52 -0600 Subject: chip/stm32/usb_hw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17cff303152488fa0ec8445a5528123c14cc7397 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729556 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_hw.h | 53 +++++++++++++++++++++++++---------------------------- 1 file changed, 25 insertions(+), 28 deletions(-) diff --git a/chip/stm32/usb_hw.h b/chip/stm32/usb_hw.h index fc186ff7de..33f55f083e 100644 --- a/chip/stm32/usb_hw.h +++ b/chip/stm32/usb_hw.h @@ -19,12 +19,11 @@ enum usb_ep_event { #include "usb_dwc_hw.h" #else - /* * The STM32 has dedicated USB RAM visible on the APB1 bus (so all reads & * writes are 16-bits wide). The endpoint tables and the data buffers live in * this RAM. -*/ + */ /* Primitive to access the words in USB RAM */ typedef CONFIG_USB_RAM_ACCESS_TYPE usb_uint; @@ -87,8 +86,8 @@ enum usb_desc_patch_type { * The patches need to be setup before _before_ usb_init is executed (or, at * least, before the first call to memcpy_to_usbram_ep0_patch). */ -void set_descriptor_patch(enum usb_desc_patch_type type, - const void *address, uint16_t data); +void set_descriptor_patch(enum usb_desc_patch_type type, const void *address, + uint16_t data); /* Copy to USB ram, applying patches to src as required. */ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); @@ -106,44 +105,42 @@ void *memcpy_to_usbram_ep0_patch(const void *src, size_t n); #define _EP_RX_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _rx_typecheck) #define _EP_EVENT_HANDLER_TYPECHECK(num) _EP_HANDLER2(num, _evt_typecheck) -#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ - void _EP_TX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(tx_handler)))); \ - void _EP_RX_HANDLER(num)(void) \ - __attribute__ ((alias(STRINGIFY(rx_handler)))); \ - void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ - __attribute__ ((alias(STRINGIFY(evt_handler)))); \ - static __unused void \ - (*_EP_TX_HANDLER_TYPECHECK(num))(void) = tx_handler; \ - static __unused void \ - (*_EP_RX_HANDLER_TYPECHECK(num))(void) = rx_handler; \ - static __unused void \ - (*_EP_EVENT_HANDLER_TYPECHECK(num))(enum usb_ep_event evt)\ - = evt_handler +#define USB_DECLARE_EP(num, tx_handler, rx_handler, evt_handler) \ + void _EP_TX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(tx_handler)))); \ + void _EP_RX_HANDLER(num)(void) \ + __attribute__((alias(STRINGIFY(rx_handler)))); \ + void _EP_EVENT_HANDLER(num)(enum usb_ep_event evt) \ + __attribute__((alias(STRINGIFY(evt_handler)))); \ + static __unused void (*_EP_TX_HANDLER_TYPECHECK(num))(void) = \ + tx_handler; \ + static __unused void (*_EP_RX_HANDLER_TYPECHECK(num))(void) = \ + rx_handler; \ + static __unused void (*_EP_EVENT_HANDLER_TYPECHECK(num))( \ + enum usb_ep_event evt) = evt_handler /* arrays with all endpoint callbacks */ -extern void (*usb_ep_tx[]) (void); -extern void (*usb_ep_rx[]) (void); -extern void (*usb_ep_event[]) (enum usb_ep_event evt); +extern void (*usb_ep_tx[])(void); +extern void (*usb_ep_rx[])(void); +extern void (*usb_ep_event[])(enum usb_ep_event evt); /* array with interface-specific control request callbacks */ -extern int (*usb_iface_request[]) (usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); +extern int (*usb_iface_request[])(usb_uint *ep0_buf_rx, usb_uint *ep0_buf_tx); /* * Interface handler returns -1 on error, 0 if it wrote the last chunk of data, * or 1 if more data needs to be transferred on the next control request. */ #define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request) -#define USB_DECLARE_IFACE(num, handler) \ - int _IFACE_HANDLER(num)(usb_uint *ep0_buf_rx, \ - usb_uint *epo_buf_tx) \ - __attribute__ ((alias(STRINGIFY(handler)))); +#define USB_DECLARE_IFACE(num, handler) \ + int _IFACE_HANDLER(num)(usb_uint * ep0_buf_rx, usb_uint * epo_buf_tx) \ + __attribute__((alias(STRINGIFY(handler)))); #endif /* * In and out buffer sizes for host command over USB. */ -#define USBHC_MAX_REQUEST_SIZE 0x200 +#define USBHC_MAX_REQUEST_SIZE 0x200 #define USBHC_MAX_RESPONSE_SIZE 0x100 -#endif /* __CROS_EC_USB_HW_H */ +#endif /* __CROS_EC_USB_HW_H */ -- cgit v1.2.1 From 5ff32861da24ac1a39951031788850766ed668a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:55 -0600 Subject: board/lindar/ktd20xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I06721b855e9274228dd090236a65509afdb47b3d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728636 Reviewed-by: Jeremy Bettis --- board/lindar/ktd20xx.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/board/lindar/ktd20xx.h b/board/lindar/ktd20xx.h index ad93ee3de8..80689946a6 100644 --- a/board/lindar/ktd20xx.h +++ b/board/lindar/ktd20xx.h @@ -120,21 +120,21 @@ */ enum ktd20xx_register { - KTD20XX_ID_DATA = 0x00, - KTD20XX_STATUS_REG = 0x01, - KTD20XX_CTRL_CFG = 0x02, - KTD20XX_IRED_SET0 = 0x03, - KTD20XX_IGRN_SET0 = 0x04, - KTD20XX_IBLU_SET0 = 0x05, - KTD20XX_IRED_SET1 = 0x06, - KTD20XX_IGRN_SET1 = 0x07, - KTD20XX_IBLU_SET1 = 0x08, - KTD20XX_ISEL_A12 = 0x09, - KTD20XX_ISEL_A34 = 0x0A, - KTD20XX_ISEL_B12 = 0x0B, - KTD20XX_ISEL_B34 = 0x0C, - KTD20XX_ISEL_C12 = 0x0D, - KTD20XX_ISEL_C34 = 0x0E, + KTD20XX_ID_DATA = 0x00, + KTD20XX_STATUS_REG = 0x01, + KTD20XX_CTRL_CFG = 0x02, + KTD20XX_IRED_SET0 = 0x03, + KTD20XX_IGRN_SET0 = 0x04, + KTD20XX_IBLU_SET0 = 0x05, + KTD20XX_IRED_SET1 = 0x06, + KTD20XX_IGRN_SET1 = 0x07, + KTD20XX_IBLU_SET1 = 0x08, + KTD20XX_ISEL_A12 = 0x09, + KTD20XX_ISEL_A34 = 0x0A, + KTD20XX_ISEL_B12 = 0x0B, + KTD20XX_ISEL_B34 = 0x0C, + KTD20XX_ISEL_C12 = 0x0D, + KTD20XX_ISEL_C34 = 0x0E, KTD20XX_TOTOAL_REG }; -- cgit v1.2.1 From 2e3acdcdfface6a9c065df85e5bd7e0830c573b6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:57 -0600 Subject: board/host/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9f3a3356b6848ad32549a9d3a6f9e1541dd5bebc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728509 Reviewed-by: Jeremy Bettis --- board/host/usb_pd_policy.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/board/host/usb_pd_policy.c b/board/host/usb_pd_policy.c index b90db882ce..fe3e9b6a02 100644 --- a/board/host/usb_pd_policy.c +++ b/board/host/usb_pd_policy.c @@ -9,8 +9,8 @@ #include "usb_pd_pdo.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) test_mockable int pd_set_power_supply_ready(int port) { @@ -41,22 +41,18 @@ __override int pd_check_power_swap(int port) return 1; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap */ return 1; } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { } -- cgit v1.2.1 From 042bdf2ddba6b0227007671472441390721d731d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:30 -0600 Subject: baseboard/cherry/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b04f0b13181fa028344a189ba16a30ec7b3d0d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727868 Reviewed-by: Jeremy Bettis --- baseboard/cherry/baseboard.h | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h index a03c5c5dbd..b00949107c 100644 --- a/baseboard/cherry/baseboard.h +++ b/baseboard/cherry/baseboard.h @@ -93,13 +93,13 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_I2C_PASSTHRU_RESTRICTED #define CONFIG_I2C_VIRTUAL_BATTERY -#define I2C_PORT_CHARGER IT83XX_I2C_CH_A -#define I2C_PORT_BATTERY IT83XX_I2C_CH_A -#define I2C_PORT_ACCEL IT83XX_I2C_CH_B -#define I2C_PORT_PPC0 IT83XX_I2C_CH_C -#define I2C_PORT_PPC1 IT83XX_I2C_CH_E -#define I2C_PORT_USB0 IT83XX_I2C_CH_C -#define I2C_PORT_USB1 IT83XX_I2C_CH_E +#define I2C_PORT_CHARGER IT83XX_I2C_CH_A +#define I2C_PORT_BATTERY IT83XX_I2C_CH_A +#define I2C_PORT_ACCEL IT83XX_I2C_CH_B +#define I2C_PORT_PPC0 IT83XX_I2C_CH_C +#define I2C_PORT_PPC1 IT83XX_I2C_CH_E +#define I2C_PORT_USB0 IT83XX_I2C_CH_C +#define I2C_PORT_USB1 IT83XX_I2C_CH_E #define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C #define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY @@ -155,7 +155,7 @@ #define PD_MAX_VOLTAGE_MV 20000 #define PD_OPERATING_POWER_MW 15000 #define PD_MAX_POWER_MW 60000 -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* USB-A */ @@ -202,13 +202,12 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT) | \ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) | \ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) /* And the MKBP events */ #define CONFIG_MKBP_EVENT_WAKEUP_MASK \ - (BIT(EC_MKBP_EVENT_KEY_MATRIX) | \ - BIT(EC_MKBP_EVENT_HOST_EVENT)) + (BIT(EC_MKBP_EVENT_KEY_MATRIX) | BIT(EC_MKBP_EVENT_HOST_EVENT)) #ifndef __ASSEMBLER__ @@ -217,11 +216,11 @@ #include "power/mt8192.h" enum adc_channel { - ADC_VBUS, /* ADC 0 */ - ADC_BOARD_ID, /* ADC 1 */ - ADC_SKU_ID, /* ADC 2 */ - ADC_CHARGER_AMON_R, /* ADC 3 */ - ADC_CHARGER_PMON, /* ADC 6 */ + ADC_VBUS, /* ADC 0 */ + ADC_BOARD_ID, /* ADC 1 */ + ADC_SKU_ID, /* ADC 2 */ + ADC_CHARGER_AMON_R, /* ADC 3 */ + ADC_CHARGER_PMON, /* ADC 6 */ ADC_TEMP_SENSOR_CHARGER, /* ADC 7 */ /* Number of ADC channels */ @@ -239,7 +238,7 @@ void rt1718s_tcpc_interrupt(enum gpio_signal signal); /* RT1718S gpio to pin name mapping */ #define GPIO_EN_USB_C1_VBUS_L RT1718S_GPIO1 #define GPIO_EN_USB_C1_5V_OUT RT1718S_GPIO2 -#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 +#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASEBOARD_H */ -- cgit v1.2.1 From 158e10b12eea22daac7e19c0557dddde520d471c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:11 -0600 Subject: board/dooly/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9cf7926a70ebfe15e68ebb0e74ea7e450000b1c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726419 Reviewed-by: Jeremy Bettis --- board/dooly/usb_pd_policy.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/dooly/usb_pd_policy.c b/board/dooly/usb_pd_policy.c index a8d89130c2..9259586da2 100644 --- a/board/dooly/usb_pd_policy.c +++ b/board/dooly/usb_pd_policy.c @@ -19,9 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) - +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From f2a5afae28f8ada0c1532ae080725caebbf053c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:27 -0600 Subject: board/anahera/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie60a4f45f2c13541d2d2962137d34a83da03da82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727986 Reviewed-by: Jeremy Bettis --- board/anahera/charger.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/anahera/charger.c diff --git a/board/anahera/charger.c b/board/anahera/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/anahera/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/anahera/charger.c b/board/anahera/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/anahera/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From ae80fc82d10c3927a29f8be1b8281baa36b08ed0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:36 -0600 Subject: board/plankton/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I726f230313d145a37fdfc5de3fafdaf61e8633e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728836 Reviewed-by: Jeremy Bettis --- board/plankton/usb_pd_policy.c | 43 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 24 deletions(-) diff --git a/board/plankton/usb_pd_policy.c b/board/plankton/usb_pd_policy.c index 238f2297f5..51993dd1fa 100644 --- a/board/plankton/usb_pd_policy.c +++ b/board/plankton/usb_pd_policy.c @@ -18,8 +18,8 @@ #include "usb_pd_pdo.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Acceptable margin between requested VBUS and measured value */ #define MARGIN_MV 400 /* mV */ @@ -27,7 +27,6 @@ /* Whether alternate mode has been entered or not */ static int alt_mode; - void pd_set_input_current_limit(int port, uint32_t max_ma, uint32_t supply_voltage) { @@ -77,22 +76,18 @@ __override int pd_check_power_swap(int port) return 1; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always allow data swap */ return 1; } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { /* If Plankton is in USB hub mode, always act as UFP */ if (board_in_hub_mode() && dr_role == PD_ROLE_DFP && @@ -110,8 +105,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 1, /* Vbus power required */ @@ -139,13 +134,13 @@ static int svdm_response_svids(int port, uint32_t *payload) #define MODE_CNT 1 #define OPOS 1 -const uint32_t vdo_dp_mode[MODE_CNT] = { - VDO_MODE_DP(0, /* UFP pin cfg supported : none */ +const uint32_t vdo_dp_mode[MODE_CNT] = { + VDO_MODE_DP(0, /* UFP pin cfg supported : none */ MODE_DP_PIN_E, /* DFP pin cfg supported */ - 1, /* no usb2.0 signalling in AMode */ - CABLE_PLUG, /* its a plug */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + 1, /* no usb2.0 signalling in AMode */ + CABLE_PLUG, /* its a plug */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; static int svdm_response_modes(int port, uint32_t *payload) @@ -167,13 +162,13 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ !gpio_get_level(GPIO_USBC_SS_USB_MODE), - 0, /* power low */ + 0, /* power low */ 0x2); return 2; } -- cgit v1.2.1 From 4b37da1eaeb9642685a9ec5e08c4c33d238861ba Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:23 -0600 Subject: board/voema/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaaa5f7eaa1d962dd3fd8a1c4f4dbd8299510c9fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729071 Reviewed-by: Jeremy Bettis --- board/voema/board.c | 46 ++++++++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/board/voema/board.c b/board/voema/board.c index c5afc2dee7..b2f2a5ea3e 100644 --- a/board/voema/board.c +++ b/board/voema/board.c @@ -42,7 +42,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -77,8 +77,8 @@ static const struct ec_response_keybd_config voema_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &voema_kb; } @@ -89,16 +89,15 @@ __override const struct ec_response_keybd_config * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { 0, 4 }, { -1, -1 }, { 8, 2 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /******************************************************************************/ /* @@ -124,8 +123,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -150,8 +149,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -241,8 +240,7 @@ static void ps8815_reset(void) int val; gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(GPIO_USB_C1_RT_RST_ODL, 1); msleep(PS8815_FW_INIT_DELAY_MS); @@ -253,16 +251,16 @@ static void ps8815_reset(void) CPRINTS("%s: patching ps8815 registers", __func__); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, + 0x31) == EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(I2C_PORT_USB_C1, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(I2C_PORT_USB_C1, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -272,7 +270,7 @@ void board_reset_pd_mcu(void) /* Daughterboard specific reset for port 1 */ ps8815_reset(); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } __override void board_cbi_init(void) -- cgit v1.2.1 From f587ff16dd77318283994b83120b647584041e95 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:09 -0600 Subject: driver/mp2964.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10ffcc3ce1e99e55199df40a874973bbceded23f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730020 Reviewed-by: Jeremy Bettis --- driver/mp2964.h | 54 +++++++++++++++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/driver/mp2964.h b/driver/mp2964.h index f424887567..5d4dbca4a2 100644 --- a/driver/mp2964.h +++ b/driver/mp2964.h @@ -6,33 +6,33 @@ #ifndef __CROS_EC_PMIC_MP2964_H #define __CROS_EC_PMIC_MP2964_H -#define MP2964_PAGE 0x00 -#define MP2964_STORE_USER_ALL 0x15 -#define MP2964_RESTORE_USER_ALL 0x16 -#define MP2964_MFR_VOUT_TRIM 0x22 -#define MP2964_MFR_PHASE_NUM 0x29 -#define MP2964_MFR_IMON_SNS_OFFS 0x2c -#define MP2964_IOUT_CAL_GAIN_SET 0x38 -#define MP2964_MFR_TRANS_FAST 0x3d -#define MP2964_MFR_ALT_SET 0x3f -#define MP2964_MFR_CONFIG2 0x48 -#define MP2964_MFR_SLOPE_SR_DCM 0x4e -#define MP2964_MFR_ICC_MAX_SET 0x53 -#define MP2964_MFR_OCP_OVP_DAC_LIMIT 0x60 -#define MP2964_MFR_OCP_SET 0x62 -#define MP2964_PRODUCT_DATA_CODE 0x93 -#define MP2964_LOT_CODE_VR 0x94 -#define MP2964_MFR_PSI_TRIM4 0xb0 -#define MP2964_MFR_PSI_TRIM1 0xb1 -#define MP2964_MFR_PSI_TRIM3 0xb3 -#define MP2964_MFR_SLOPE_CNT_2P 0xd4 -#define MP2964_MFR_SLOPE_CNT_5P 0xe0 -#define MP2964_MFR_IMON_SVID1 0xe8 -#define MP2964_MFR_IMON_SVID2 0xe9 -#define MP2964_MFR_IMON_SVID3 0xea -#define MP2964_MFR_IMON_SVID4 0xeb -#define MP2964_MFR_IMON_SVID5 0xef -#define MP2964_MFR_IMON_SVID6 0xf0 +#define MP2964_PAGE 0x00 +#define MP2964_STORE_USER_ALL 0x15 +#define MP2964_RESTORE_USER_ALL 0x16 +#define MP2964_MFR_VOUT_TRIM 0x22 +#define MP2964_MFR_PHASE_NUM 0x29 +#define MP2964_MFR_IMON_SNS_OFFS 0x2c +#define MP2964_IOUT_CAL_GAIN_SET 0x38 +#define MP2964_MFR_TRANS_FAST 0x3d +#define MP2964_MFR_ALT_SET 0x3f +#define MP2964_MFR_CONFIG2 0x48 +#define MP2964_MFR_SLOPE_SR_DCM 0x4e +#define MP2964_MFR_ICC_MAX_SET 0x53 +#define MP2964_MFR_OCP_OVP_DAC_LIMIT 0x60 +#define MP2964_MFR_OCP_SET 0x62 +#define MP2964_PRODUCT_DATA_CODE 0x93 +#define MP2964_LOT_CODE_VR 0x94 +#define MP2964_MFR_PSI_TRIM4 0xb0 +#define MP2964_MFR_PSI_TRIM1 0xb1 +#define MP2964_MFR_PSI_TRIM3 0xb3 +#define MP2964_MFR_SLOPE_CNT_2P 0xd4 +#define MP2964_MFR_SLOPE_CNT_5P 0xe0 +#define MP2964_MFR_IMON_SVID1 0xe8 +#define MP2964_MFR_IMON_SVID2 0xe9 +#define MP2964_MFR_IMON_SVID3 0xea +#define MP2964_MFR_IMON_SVID4 0xeb +#define MP2964_MFR_IMON_SVID5 0xef +#define MP2964_MFR_IMON_SVID6 0xf0 struct mp2964_reg_val { uint8_t reg; -- cgit v1.2.1 From d55e9f2225723d9e493b2e0cc62b3d595ae24fd5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:30 -0600 Subject: include/memory_commands.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I65df50bfd3a5519abc16684d5a202bc6ced7184a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730353 Reviewed-by: Jeremy Bettis --- include/memory_commands.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/memory_commands.h b/include/memory_commands.h index 91020d8920..590bb9331f 100644 --- a/include/memory_commands.h +++ b/include/memory_commands.h @@ -13,4 +13,4 @@ /* Initializes the module. */ int memory_commands_init(void); -#endif /* __CROS_EC_MEMORY_COMMANDS_H */ +#endif /* __CROS_EC_MEMORY_COMMANDS_H */ -- cgit v1.2.1 From ea9e78111005b2c683cfb12f57c6d0eb3d50c317 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:25 -0600 Subject: zephyr/shim/src/bc12.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I516cc864c536d71334078715509e1be0092faa67 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730887 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/bc12.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c index 3bdab5f16e..4f1fd2db01 100644 --- a/zephyr/shim/src/bc12.c +++ b/zephyr/shim/src/bc12.c @@ -10,7 +10,7 @@ #include "usbc/utils.h" #include "usb_charge.h" -#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \ +#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(RT9490_BC12_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(PI3USB9201_COMPAT) @@ -20,10 +20,11 @@ struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP, BC12_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, - BC12_CHIP_RT9490) - DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, BC12_CHIP, - BC12_CHIP_PI3USB9201) + DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, + BC12_CHIP_RT9490) + DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, + BC12_CHIP, + BC12_CHIP_PI3USB9201) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 9b05c13a1d03b2b154af3a6a8fe9a695eb483aad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:40 -0600 Subject: board/marzipan/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c8765055abe19770ff1615cd4fa12440357ae52 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728667 Reviewed-by: Jeremy Bettis --- board/marzipan/board.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/board/marzipan/board.h b/board/marzipan/board.h index 28dc5d273a..bcb655d937 100644 --- a/board/marzipan/board.h +++ b/board/marzipan/board.h @@ -11,7 +11,7 @@ #include "baseboard.h" /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Keyboard */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP @@ -19,7 +19,7 @@ #define CONFIG_PWM_KBLIGHT /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE @@ -71,12 +71,7 @@ #include "gpio_signal.h" #include "registers.h" -enum adc_channel { - ADC_VBUS, - ADC_AMON_BMON, - ADC_PSYS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_AMON_BMON, ADC_PSYS, ADC_CH_COUNT }; /* Motion sensors */ enum sensor_id { @@ -86,11 +81,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_DISPLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_DISPLIGHT, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 0648cafc5a9c7f82e7ec3a5ec806e218c494be4c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:05 -0600 Subject: board/vell/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I425ff741dce4cef5fc3258c0686364f1ee806dd8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729055 Reviewed-by: Jeremy Bettis --- board/vell/usbc_config.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/vell/usbc_config.c b/board/vell/usbc_config.c index d2d759cbb4..29c436d01d 100644 --- a/board/vell/usbc_config.c +++ b/board/vell/usbc_config.c @@ -35,8 +35,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ const struct tcpc_config_t tcpc_config[] = { @@ -258,8 +258,8 @@ int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) } if (voltage < BC12_MIN_VOLTAGE) { - CPRINTS("%s: port %d: vbus %d lower than %d", __func__, - port, voltage, BC12_MIN_VOLTAGE); + CPRINTS("%s: port %d: vbus %d lower than %d", __func__, port, + voltage, BC12_MIN_VOLTAGE); return 1; } -- cgit v1.2.1 From b89b64b1b3e9324d672f2d5c3854741e49d48859 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:19 -0600 Subject: common/button.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44b2719f37ad11c4c1400f01745b702ed745676a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729595 Reviewed-by: Jeremy Bettis --- common/button.c | 54 ++++++++++++++++++++++++++---------------------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/common/button.c b/common/button.c index 145cd9db74..1020ed4672 100644 --- a/common/button.c +++ b/common/button.c @@ -24,7 +24,7 @@ #include "watchdog.h" /* Console output macro */ -#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SWITCH, format, ##args) struct button_state_t { uint64_t debounce_time; @@ -75,12 +75,12 @@ static int raw_button_pressed(const struct button_config *button) int simulated_value = 0; if (!(button->flags & BUTTON_FLAG_DISABLED)) { if (IS_ENABLED(CONFIG_ADC_BUTTONS) && - button_is_adc_detected(button->gpio)) { - physical_value = - adc_to_physical_value(button->gpio); + button_is_adc_detected(button->gpio)) { + physical_value = adc_to_physical_value(button->gpio); } else { - physical_value = (!!gpio_get_level(button->gpio) == - !!(button->flags & BUTTON_FLAG_ACTIVE_HIGH)); + physical_value = + (!!gpio_get_level(button->gpio) == + !!(button->flags & BUTTON_FLAG_ACTIVE_HIGH)); } #ifdef CONFIG_SIMULATED_BUTTON simulated_value = simulated_button_pressed(button); @@ -193,7 +193,7 @@ static int is_recovery_boot(void) if (system_jumped_to_this_image()) return 0; if (!(system_get_reset_flags() & - (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON))) + (EC_RESET_FLAG_RESET_PIN | EC_RESET_FLAG_POWER_ON))) return 0; if (!is_recovery_button_pressed()) return 0; @@ -202,7 +202,7 @@ static int is_recovery_boot(void) #endif /* CONFIG_BUTTON_TRIGGERED_RECOVERY */ static void button_reset(enum button button_type, - const struct button_config *button) + const struct button_config *button) { state[button_type].debounced_pressed = raw_button_pressed(button); state[button_type].debounce_time = 0; @@ -260,7 +260,6 @@ int button_disable_gpio(enum button button_type) } #endif - /* * Handle debounced button changing state. */ @@ -308,15 +307,14 @@ static void button_change_deferred(void) hook_call_deferred( &debug_mode_handle_data, 0); #endif - CPRINTS("Button '%s' was %s", - buttons[i].name, new_pressed ? - "pressed" : "released"); + CPRINTS("Button '%s' was %s", buttons[i].name, + new_pressed ? "pressed" : "released"); if (IS_ENABLED(CONFIG_MKBP_INPUT_DEVICES)) { mkbp_button_update(buttons[i].type, - new_pressed); + new_pressed); } else if (IS_ENABLED(HAS_TASK_KEYPROTO)) { keyboard_update_button(buttons[i].type, - new_pressed); + new_pressed); } } @@ -327,10 +325,11 @@ static void button_change_deferred(void) * Make sure the next deferred call happens on or before * each button needs it. */ - soonest_debounce_time = (soonest_debounce_time == 0) ? - state[i].debounce_time : - MIN(soonest_debounce_time, - state[i].debounce_time); + soonest_debounce_time = + (soonest_debounce_time == 0) ? + state[i].debounce_time : + MIN(soonest_debounce_time, + state[i].debounce_time); } } @@ -418,7 +417,7 @@ static void simulate_button(uint32_t button_mask, int press_ms) /* Defer the button release for specified duration */ hook_call_deferred(&simulate_button_release_deferred_data, - press_ms * MSEC); + press_ms * MSEC); } #endif /* #ifdef CONFIG_SIMULATED_BUTTON */ @@ -465,8 +464,7 @@ static int console_command_button(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(button, console_command_button, - "vup|vdown|rec msec", +DECLARE_CONSOLE_COMMAND(button, console_command_button, "vup|vdown|rec msec", "Simulate button press"); #endif /* CONFIG_CMD_BUTTON */ @@ -494,7 +492,6 @@ DECLARE_HOST_COMMAND(EC_CMD_BUTTON, host_command_button, EC_VER_MASK(0)); #endif /* CONFIG_HOSTCMD_BUTTON */ - #ifdef CONFIG_EMULATED_SYSRQ #ifdef CONFIG_DEDICATED_RECOVERY_BUTTON @@ -546,10 +543,10 @@ enum debug_state { STATE_WARM_RESET_EXEC, }; -#define DEBUG_BTN_POWER BIT(0) -#define DEBUG_BTN_VOL_UP BIT(1) -#define DEBUG_BTN_VOL_DN BIT(2) -#define DEBUG_TIMEOUT (10 * SECOND) +#define DEBUG_BTN_POWER BIT(0) +#define DEBUG_BTN_VOL_UP BIT(1) +#define DEBUG_BTN_VOL_DN BIT(2) +#define DEBUG_TIMEOUT (10 * SECOND) static enum debug_state curr_debug_state = STATE_DEBUG_NONE; static enum debug_state next_debug_state = STATE_DEBUG_NONE; @@ -721,8 +718,9 @@ static void debug_mode_handle(void) * Schedule a deferred call in case timeout hasn't * occurred yet. */ - hook_call_deferred(&debug_mode_handle_data, - (debug_state_deadline.val - now.val)); + hook_call_deferred( + &debug_mode_handle_data, + (debug_state_deadline.val - now.val)); } break; -- cgit v1.2.1 From a152b01660925d2a41f8f86070a3d5d51a6e0c09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:55 -0600 Subject: chip/max32660/clock_chip.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4146b8fc191a209ec945e905c69d039279be4a27 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729227 Reviewed-by: Jeremy Bettis --- chip/max32660/clock_chip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/max32660/clock_chip.c b/chip/max32660/clock_chip.c index 901c5d559c..3dcb4bee1b 100644 --- a/chip/max32660/clock_chip.c +++ b/chip/max32660/clock_chip.c @@ -26,9 +26,9 @@ typedef enum { SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */ - SYS_CLOCK_HFXIN = - MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ - SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ + SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 + */ + SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */ } sys_system_clock_t; -- cgit v1.2.1 From 1e9ada19f16228ddc3f4eb7b9206f2e10a6a67de Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:32 -0600 Subject: board/anahera/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie630c73999796b5bf026ab4ec56ab13fef6f5993 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727987 Reviewed-by: Jeremy Bettis --- board/anahera/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/anahera/fw_config.c b/board/anahera/fw_config.c index 3c64f055f6..1144a30fbe 100644 --- a/board/anahera/fw_config.c +++ b/board/anahera/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union anahera_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From a022b87f88522bdae5fcdb6be98c31f716067baf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:17 -0600 Subject: include/flash.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I322eb43403f7b0af6c63e644e6196fbb46e20cb2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730287 Reviewed-by: Jeremy Bettis --- include/flash.h | 48 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/include/flash.h b/include/flash.h index 240ab0369b..214e5b43d8 100644 --- a/include/flash.h +++ b/include/flash.h @@ -9,11 +9,11 @@ #define __CROS_EC_FLASH_H #include "common.h" -#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */ +#include "ec_commands.h" /* For EC_FLASH_PROTECT_* flags */ #ifdef CONFIG_FLASH_MULTIPLE_REGION -extern struct ec_flash_bank const flash_bank_array[ - CONFIG_FLASH_REGION_TYPE_COUNT]; +extern struct ec_flash_bank const + flash_bank_array[CONFIG_FLASH_REGION_TYPE_COUNT]; /* * Return the bank the offset is in. @@ -51,25 +51,25 @@ int crec_flash_bank_start_offset(int bank); int crec_flash_bank_erase_size(int bank); /* Number of physical flash banks */ -#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION +#define PHYSICAL_BANKS CONFIG_FLASH_MULTIPLE_REGION /* WP region offset and size in units of flash banks */ -#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF) +#define WP_BANK_OFFSET crec_flash_bank_index(CONFIG_WP_STORAGE_OFF) #define WP_BANK_COUNT \ (crec_flash_bank_count(CONFIG_WP_STORAGE_OFF, CONFIG_WP_STORAGE_SIZE)) -#else /* CONFIG_FLASH_MULTIPLE_REGION */ +#else /* CONFIG_FLASH_MULTIPLE_REGION */ /* Number of physical flash banks */ #ifndef PHYSICAL_BANKS #define PHYSICAL_BANKS (CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE) #endif /* WP region offset and size in units of flash banks */ -#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE) +#define WP_BANK_OFFSET (CONFIG_WP_STORAGE_OFF / CONFIG_FLASH_BANK_SIZE) #ifndef WP_BANK_COUNT -#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE) +#define WP_BANK_COUNT (CONFIG_WP_STORAGE_SIZE / CONFIG_FLASH_BANK_SIZE) #endif -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ /* Persistent protection state flash offset / size / bank */ #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK) @@ -82,33 +82,33 @@ int crec_flash_bank_erase_size(int bank); * When there is a dedicated flash bank used to store persistent state, * ensure the RO flash region excludes the PSTATE bank. */ -#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE +#define EC_FLASH_REGION_RO_SIZE CONFIG_RO_SIZE #ifndef PSTATE_BANK -#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE) +#define PSTATE_BANK (CONFIG_FW_PSTATE_OFF / CONFIG_FLASH_BANK_SIZE) #endif #ifndef PSTATE_BANK_COUNT -#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE) +#define PSTATE_BANK_COUNT (CONFIG_FW_PSTATE_SIZE / CONFIG_FLASH_BANK_SIZE) #endif -#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ +#else /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ /* Allow flashrom to program the entire write protected area */ -#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE -#define PSTATE_BANK_COUNT 0 -#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ +#define EC_FLASH_REGION_RO_SIZE CONFIG_WP_STORAGE_SIZE +#define PSTATE_BANK_COUNT 0 +#endif /* CONFIG_FLASH_PSTATE && CONFIG_FLASH_PSTATE_BANK */ #ifdef CONFIG_ROLLBACK /* * ROLLBACK region offset and size in units of flash banks. */ #ifdef CONFIG_FLASH_MULTIPLE_REGION -#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF) -#define ROLLBACK_BANK_COUNT \ +#define ROLLBACK_BANK_OFFSET crec_flash_bank_index(CONFIG_ROLLBACK_OFF) +#define ROLLBACK_BANK_COUNT \ crec_flash_bank_count(CONFIG_ROLLBACK_OFF, CONFIG_ROLLBACK_SIZE) #else -#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE) -#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE) -#endif /* CONFIG_FLASH_MULTIPLE_REGION */ -#endif /* CONFIG_ROLLBACK */ +#define ROLLBACK_BANK_OFFSET (CONFIG_ROLLBACK_OFF / CONFIG_FLASH_BANK_SIZE) +#define ROLLBACK_BANK_COUNT (CONFIG_ROLLBACK_SIZE / CONFIG_FLASH_BANK_SIZE) +#endif /* CONFIG_FLASH_MULTIPLE_REGION */ +#endif /* CONFIG_ROLLBACK */ /* This enum is useful to identify different regions during verification. */ enum flash_region { @@ -378,7 +378,7 @@ int crec_flash_write_pstate_mac_addr(const char *mac_addr); #ifdef CONFIG_EXTERNAL_STORAGE void crec_flash_lock_mapped_storage(int lock); #else -static inline void crec_flash_lock_mapped_storage(int lock) { }; +static inline void crec_flash_lock_mapped_storage(int lock){}; #endif /* CONFIG_EXTERNAL_STORAGE */ /** @@ -390,4 +390,4 @@ static inline void crec_flash_lock_mapped_storage(int lock) { }; */ int crec_board_flash_select(int select); -#endif /* __CROS_EC_FLASH_H */ +#endif /* __CROS_EC_FLASH_H */ -- cgit v1.2.1 From e09ae2f216b3ffd3401f88b12b42d09b5877dea4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:20 -0600 Subject: cts/hook/th.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie507103fdca5f4e4c01f6c77a77015774efc19a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729759 Reviewed-by: Jeremy Bettis --- cts/hook/th.c | 165 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 164 insertions(+), 1 deletion(-) mode change 120000 => 100644 cts/hook/th.c diff --git a/cts/hook/th.c b/cts/hook/th.c deleted file mode 120000 index 41eab28462..0000000000 --- a/cts/hook/th.c +++ /dev/null @@ -1 +0,0 @@ -dut.c \ No newline at end of file diff --git a/cts/hook/th.c b/cts/hook/th.c new file mode 100644 index 0000000000..1d6b1e145e --- /dev/null +++ b/cts/hook/th.c @@ -0,0 +1,164 @@ +/* Copyright 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Test hooks. + */ + +#include "common.h" +#include "console.h" +#include "cts_common.h" +#include "hooks.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "watchdog.h" + +static int init_hook_count; +static int tick_hook_count; +static int tick2_hook_count; +static int tick_count_seen_by_tick2; +static timestamp_t tick_time[2]; +static int second_hook_count; +static timestamp_t second_time[2]; +static int deferred_call_count; + +static void init_hook(void) +{ + init_hook_count++; +} +DECLARE_HOOK(HOOK_INIT, init_hook, HOOK_PRIO_DEFAULT); + +static void tick_hook(void) +{ + tick_hook_count++; + tick_time[0] = tick_time[1]; + tick_time[1] = get_time(); +} +DECLARE_HOOK(HOOK_TICK, tick_hook, HOOK_PRIO_DEFAULT); + +static void tick2_hook(void) +{ + tick2_hook_count++; + tick_count_seen_by_tick2 = tick_hook_count; +} +/* tick2_hook() prio means it should be called after tick_hook() */ +DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1); + +static void second_hook(void) +{ + second_hook_count++; + second_time[0] = second_time[1]; + second_time[1] = get_time(); +} +DECLARE_HOOK(HOOK_SECOND, second_hook, HOOK_PRIO_DEFAULT); + +static void deferred_func(void) +{ + deferred_call_count++; +} +DECLARE_DEFERRED(deferred_func); + +static void invalid_deferred_func(void) +{ + deferred_call_count++; +} + +static const struct deferred_data invalid_deferred_func_data = { + invalid_deferred_func +}; + +static enum cts_rc test_init_hook(void) +{ + if (init_hook_count != 1) + return CTS_RC_FAILURE; + return CTS_RC_SUCCESS; +} + +static enum cts_rc test_ticks(void) +{ + int64_t interval; + int error_pct; + + /* + * HOOK_SECOND must have been fired at least once when HOOK + * task starts. We only need to wait for just more than a second + * to allow it fires for the second time. + */ + msleep(1300); + + interval = tick_time[1].val - tick_time[0].val; + error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL; + if (error_pct < -10 || 10 < error_pct) { + CPRINTS("tick error=%d%% interval=%lld", error_pct, interval); + return CTS_RC_FAILURE; + } + + interval = second_time[1].val - second_time[0].val; + error_pct = (interval - SECOND) * 100 / SECOND; + if (error_pct < -10 || 10 < error_pct) { + CPRINTS("second error=%d%% interval=%lld", error_pct, interval); + return CTS_RC_FAILURE; + } + + return CTS_RC_SUCCESS; +} + +static enum cts_rc test_priority(void) +{ + usleep(HOOK_TICK_INTERVAL); + if (tick_hook_count != tick2_hook_count) + return CTS_RC_FAILURE; + if (tick_hook_count != tick_count_seen_by_tick2) + return CTS_RC_FAILURE; + return CTS_RC_SUCCESS; +} + +static enum cts_rc test_deferred(void) +{ + deferred_call_count = 0; + hook_call_deferred(&deferred_func_data, 50 * MSEC); + if (deferred_call_count != 0) { + CPRINTL("deferred_call_count=%d", deferred_call_count); + return CTS_RC_FAILURE; + } + msleep(100); + if (deferred_call_count != 1) { + CPRINTL("deferred_call_count=%d", deferred_call_count); + return CTS_RC_FAILURE; + } + + /* Test cancellation */ + deferred_call_count = 0; + hook_call_deferred(&deferred_func_data, 50 * MSEC); + msleep(25); + hook_call_deferred(&deferred_func_data, -1); + msleep(75); + if (deferred_call_count != 0) { + CPRINTL("deferred_call_count=%d", deferred_call_count); + return CTS_RC_FAILURE; + } + + /* Invalid deferred function */ + deferred_call_count = 0; + if (hook_call_deferred(&invalid_deferred_func_data, 50 * MSEC) == + EC_SUCCESS) { + CPRINTL("non_deferred_func_data"); + return CTS_RC_FAILURE; + } + msleep(100); + if (deferred_call_count != 0) { + CPRINTL("deferred_call_count=%d", deferred_call_count); + return CTS_RC_FAILURE; + } + + return CTS_RC_SUCCESS; +} + +#include "cts_testlist.h" + +void cts_task(void) +{ + cts_main_loop(tests, "Hook"); + task_wait_event(-1); +} -- cgit v1.2.1 From 707d8bf2741d54f79ed2713ca1f48411803ea221 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:00 -0600 Subject: chip/stm32/config-stm32l431.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I87d23979bfdf0f11e6ec0984e08c2b7d6e796281 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729482 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l431.h | 56 +++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/chip/stm32/config-stm32l431.h b/chip/stm32/config-stm32l431.h index 64d8d39327..d14b7ade00 100644 --- a/chip/stm32/config-stm32l431.h +++ b/chip/stm32/config-stm32l431.h @@ -4,22 +4,22 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ +#define CONFIG_FLASH_SIZE_BYTES 0x00040000 /* 256 kB */ #define CONFIG_FLASH_BANK_SIZE \ 0x800 /* 2 kB. NOTE: BANK in chrome-ec means page */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ /* * SRAM1 (48kB) at 0x20000000 * SRAM2 (16kB) at 0x10000000 (and aliased at 0x2000C000) * so they are contiguous. */ -#define CONFIG_RAM_BASE 0x20000000 -#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ +#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_SIZE 0x00010000 /* 64 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 @@ -45,36 +45,34 @@ * */ - - /* The EC uses one sector to emulate persistent state */ #define CONFIG_FLASH_PSTATE -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE +#define CONFIG_FW_PSTATE_OFF (62 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - \ - CONFIG_RW_STORAGE_OFF) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (62 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_RW_MEM_OFF \ + (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE + CONFIG_FW_PSTATE_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF - CONFIG_RW_STORAGE_OFF) -#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - CONFIG_EC_WRITABLE_STORAGE_OFF) +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - CONFIG_EC_WRITABLE_STORAGE_OFF) -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* We map each write protect sector to a bank */ -#define PHYSICAL_BANKS 128 -#define WP_BANK_COUNT 63 -#define PSTATE_BANK 62 -#define PSTATE_BANK_COUNT 1 +#define PHYSICAL_BANKS 128 +#define WP_BANK_COUNT 63 +#define PSTATE_BANK 62 +#define PSTATE_BANK_COUNT 1 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 -- cgit v1.2.1 From 570d14fdae901c97dbd510bc22c70c2bfce0d59a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:10 -0600 Subject: chip/npcx/gpio_chip-npcx7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibde7ab3bd682cff8083ca4913babde9a2cf06176 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729396 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx7.h | 347 +++++++++++++++++++++++--------------------- 1 file changed, 185 insertions(+), 162 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index 7f815e6d30..f3098506d7 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -82,7 +82,8 @@ #define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5) #define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support */ +#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \ + */ #endif /* MIWU1 */ @@ -151,7 +152,8 @@ #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if support*/ +#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \ + support*/ #endif /* Group H: NPCX_IRQ_WKINTH_1 */ @@ -194,7 +196,7 @@ /* Pin-Mux for PSL/UART2/SMB4_0 */ #ifdef NPCX_PSL_MODE_SUPPORT #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1) -#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */ +#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(A, UART2_SL)) /* CR_SOUT2 */ #define NPCX_ALT_GPIO_8_5 /* Used as PSL_OUT */ #else #define NPCX_ALT_GPIO_8_6 /* No I2CSDA since GPIO85 used as PSL_OUT */ @@ -214,7 +216,7 @@ /* Pin-Mux for PWM1/SMB6_0 */ #if NPCX7_PWM1_SEL #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */ -#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ #else #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */ #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */ @@ -289,7 +291,7 @@ #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ /* KSO08 & CR_SOUT */ #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) - /* KSO09 & CR_SIN */ +/* KSO09 & CR_SIN */ #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ @@ -309,17 +311,19 @@ /* Pin-Mux for UART2/32KHZ_OUT */ #if defined(NPCX_SECOND_UART) && (CONFIG_CONSOLE_UART == 1) -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, UART2_SL)) /* CR_SIN2 */ #else -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(A, 32K_OUT_SL)) /* 32KHZ_OUT */ #endif /* PSL module (Optional) */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */ -#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ -#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ +#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ +#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ +#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ #else #define NPCX_ALT_GPIO_D_2 /* NO PSL in NPCX7mnG series */ #define NPCX_ALT_GPIO_0_0 /* NO PSL in NPCX7mnG series */ @@ -328,8 +332,8 @@ #endif /* WOV module (Optional) */ -#if defined(NPCX_WOV_SUPPORT) && \ - (defined(CONFIG_AUDIO_CODEC_I2S_RX) || defined(CONFIG_AUDIO_CODEC_WOV)) +#if defined(NPCX_WOV_SUPPORT) && (defined(CONFIG_AUDIO_CODEC_I2S_RX) || \ + defined(CONFIG_AUDIO_CODEC_WOV)) #define NPCX_ALT_GPIO_9_5 /* Disable SPIP module if WOV is supported */ #define NPCX_ALT_GPIO_A_3 /* Disable SPIP module if WOV is supported */ #define NPCX_ALT_GPIO_A_1 /* Disable SPIP module if WOV is supported */ @@ -356,181 +360,200 @@ #define NPCX_ALT_GPIO_9_7 #endif -#define NPCX_ALT_TABLE { \ - NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ - NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ - NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ - NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ - NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */ \ - NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_4 /* DMIC_CLK */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_9_7 /* DMIC_IN */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_0 /* I2S_DATA */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ - NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ - NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ - NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ - NPCX_ALT_GPIO_E_1 /* ADC7 */ \ - NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ - NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ - NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ - NPCX_ALT_GPIO_F_0 /* ADC9 */ \ - NPCX_ALT_GPIO_F_1 /* ADC8 */ \ - NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ - NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ - NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ - NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ -} +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ + NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ + NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 \ + */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ + NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ + NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */ \ + NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_4 /* DMIC_CLK */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_9_7 /* DMIC_IN */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_0 /* I2S_DATA */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ + NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ + NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ + NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ + NPCX_ALT_GPIO_E_1 /* ADC7 */ \ + NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ + NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ + NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ + NPCX_ALT_GPIO_F_0 /* ADC9 */ \ + NPCX_ALT_GPIO_F_1 /* ADC8 */ \ + NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ + NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ + NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ + NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ + } /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ #else -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO(8, 4) +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO(8, 5) #endif -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN */ +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \ + */ #else -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) #endif -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since CLKOUT*/ +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since \ + CLKOUT*/ #else -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) #endif -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* Low-Voltage GPIO Control 4 */ -#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) -#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) -#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) -#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) -#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) -#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) -#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) -#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) +#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) +#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) +#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) +#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) +#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) +#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) +#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) /* Low-Voltage GPIO Control 5 */ -#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) -#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) -#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) +#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) +#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE /* 6 Low-Voltage Control Groups on npcx7 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, \ - { NPCX_LVOL_CTRL_ITEMS(4), }, \ - { NPCX_LVOL_CTRL_ITEMS(5), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(4), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(5), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX7_H */ -- cgit v1.2.1 From 10a08e5c6808e3351bac782395895fb5dfb481e9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:09 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If80b17053a61170f5edbe40950ad983a369af903 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730957 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c index 9258c4cee0..be4fdc4982 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c @@ -39,9 +39,8 @@ static void *usb_attach_5v_3a_pd_source_setup(void) /* Initialized the charger to supply 5V and 3A */ tcpci_partner_init(&test_fixture.source_5v_3a, PD_REV20); - test_fixture.source_5v_3a.extensions = - tcpci_src_emul_init(&test_fixture.src_ext, - &test_fixture.source_5v_3a, NULL); + test_fixture.source_5v_3a.extensions = tcpci_src_emul_init( + &test_fixture.src_ext, &test_fixture.source_5v_3a, NULL); test_fixture.src_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); @@ -64,8 +63,7 @@ static void usb_attach_5v_3a_pd_source_after(void *data) } ZTEST_SUITE(usb_attach_5v_3a_pd_source, drivers_predicate_post_main, - usb_attach_5v_3a_pd_source_setup, - usb_attach_5v_3a_pd_source_before, + usb_attach_5v_3a_pd_source_setup, usb_attach_5v_3a_pd_source_before, usb_attach_5v_3a_pd_source_after, NULL); ZTEST(usb_attach_5v_3a_pd_source, test_battery_is_charging) -- cgit v1.2.1 From 242a1c58a8eaa16ef0b2c7d6c5b78e0dfaf26e52 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:06 -0600 Subject: core/cortex-m0/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I64249eb5f30b9ea227d2fb0f5091599e042d1606 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729830 Reviewed-by: Jeremy Bettis --- core/cortex-m0/include/fpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m0/include/fpu.h b/core/cortex-m0/include/fpu.h index 3acec557a7..ce496f2b30 100644 --- a/core/cortex-m0/include/fpu.h +++ b/core/cortex-m0/include/fpu.h @@ -8,4 +8,4 @@ #ifndef __CROS_EC_FPU_H #define __CROS_EC_FPU_H -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ -- cgit v1.2.1 From 63551f0c69b1add8f99b03995169bd790d2d0b3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:21:46 -0600 Subject: chip/mt_scp/mt818x/hrtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Idfdc60851c845b735866856779c268b2bfe6c505 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729347 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt818x/hrtimer.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/chip/mt_scp/mt818x/hrtimer.c b/chip/mt_scp/mt818x/hrtimer.c index 89e0c1658b..974a0d98ac 100644 --- a/chip/mt_scp/mt818x/hrtimer.c +++ b/chip/mt_scp/mt818x/hrtimer.c @@ -50,22 +50,22 @@ static inline uint64_t timer_read_raw_system(void) * sys_high value. */ if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) : (TIMER_CLOCK_MHZ-1); + sys_high_adj = sys_high ? (sys_high - 1) : + (TIMER_CLOCK_MHZ - 1); - return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | - SCP_TIMER_VAL(TIMER_SYSTEM)); + return OVERFLOW_TICKS - + (((uint64_t)sys_high_adj << 32) | SCP_TIMER_VAL(TIMER_SYSTEM)); } static inline uint64_t timer_read_raw_event(void) { - return OVERFLOW_TICKS - (((uint64_t)event_high << 32) | - SCP_TIMER_VAL(TIMER_EVENT)); + return OVERFLOW_TICKS - + (((uint64_t)event_high << 32) | SCP_TIMER_VAL(TIMER_EVENT)); } static inline void timer_set_clock(int n, uint32_t clock_source) { - SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | - clock_source; + SCP_TIMER_EN(n) = (SCP_TIMER_EN(n) & ~TIMER_CLK_MASK) | clock_source; } static inline void timer_ack_irq(int n) @@ -182,7 +182,7 @@ int __hw_clock_source_init(uint32_t start_t) SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8; timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK); - sys_high = TIMER_CLOCK_MHZ-1; + sys_high = TIMER_CLOCK_MHZ - 1; timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); __hw_timer_enable_clock(TIMER_SYSTEM, 1); task_enable_irq(IRQ_TIMER(TIMER_SYSTEM)); @@ -200,8 +200,8 @@ uint32_t __hw_clock_source_read(void) uint32_t __hw_clock_event_get(void) { - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; + return (timer_read_raw_event() + timer_read_raw_system()) / + TIMER_CLOCK_MHZ; } static void __hw_clock_source_irq(int n) @@ -228,7 +228,7 @@ static void __hw_clock_source_irq(int n) process_timers(0); } else { /* Overflow, reload system timer */ - sys_high = TIMER_CLOCK_MHZ-1; + sys_high = TIMER_CLOCK_MHZ - 1; process_timers(1); } } else { @@ -238,10 +238,9 @@ static void __hw_clock_source_irq(int n) default: return; } - } -#define DECLARE_TIMER_IRQ(n) \ +#define DECLARE_TIMER_IRQ(n) \ DECLARE_IRQ(IRQ_TIMER(n), __hw_clock_source_irq_##n, 2); \ static void __hw_clock_source_irq_##n(void) \ { \ -- cgit v1.2.1 From 5c0649b7b493eb516533e2467ef8cf9451eb966c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:43 -0600 Subject: board/kuldax/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I65a672016aa9b2ca3388a8f8bd3a96827bcab3ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728608 Reviewed-by: Jeremy Bettis --- board/kuldax/sensors.c | 44 ++++++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/board/kuldax/sensors.c b/board/kuldax/sensors.c index 8455a8fbc2..0f91d47f3b 100644 --- a/board/kuldax/sensors.c +++ b/board/kuldax/sensors.c @@ -58,30 +58,22 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_CPU] = { - .name = "CPU", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_CPU - }, - [TEMP_SENSOR_2_CPU_VR] = { - .name = "CPU VR", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_CPU_VR - }, - [TEMP_SENSOR_3_WIFI] = { - .name = "WIFI", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_WIFI - }, - [TEMP_SENSOR_4_DIMM] = { - .name = "DIMM", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_DIMM - }, + [TEMP_SENSOR_1_CPU] = { .name = "CPU", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_CPU }, + [TEMP_SENSOR_2_CPU_VR] = { .name = "CPU VR", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_CPU_VR }, + [TEMP_SENSOR_3_WIFI] = { .name = "WIFI", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_WIFI }, + [TEMP_SENSOR_4_DIMM] = { .name = "DIMM", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_DIMM }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -95,8 +87,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From f83b3230696f3b39f431398ecd6c5ddbc50e1817 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:06 -0600 Subject: board/dooly/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id7cc49ca9abb3de56ddc8d1a2634d443382605a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726417 Reviewed-by: Jeremy Bettis --- board/dooly/board.h | 133 +++++++++++++++++++++++++--------------------------- 1 file changed, 63 insertions(+), 70 deletions(-) diff --git a/board/dooly/board.h b/board/dooly/board.h index 884117bbbc..3cdbb86028 100644 --- a/board/dooly/board.h +++ b/board/dooly/board.h @@ -15,13 +15,13 @@ * By default, enable all console messages except HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -49,14 +49,13 @@ /* TCS3400 ALS */ #define CONFIG_ALS -#define ALS_COUNT 1 +#define ALS_COUNT 1 #define CONFIG_ALS_TCS3400 -#define CONFIG_ALS_TCS3400_INT_EVENT\ +#define CONFIG_ALS_TCS3400_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(CLEAR_ALS) /* Sensors without hardware FIFO are in forced mode */ -#define CONFIG_ACCEL_FORCE_MODE_MASK \ - (BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS)) +#define CONFIG_ACCEL_FORCE_MODE_MASK (BIT(SCREEN_ACCEL) | BIT(CLEAR_ALS)) /* EC Defines */ #define CONFIG_ADC @@ -74,7 +73,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -83,7 +82,6 @@ #define CONFIG_VSTORE_SLOT_COUNT 1 #define CONFIG_SHA256 - /* EC Commands */ #define CONFIG_CMD_BUTTON /* Include CLI command needed to support CCD testing. */ @@ -120,7 +118,7 @@ #define CONFIG_CPU_PROCHOT_ACTIVE_LOW /* Dedicated barreljack charger port */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT 2 @@ -141,15 +139,15 @@ #define CONFIG_INA3221 /* b/143501304 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 4000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 2000 /* us */ #undef CONFIG_USBC_VCONN_SWAP_DELAY_US -#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ +#define CONFIG_USBC_VCONN_SWAP_DELAY_US 8000 /* us */ -#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* Fan and temp. */ #define CONFIG_FANS 1 @@ -173,7 +171,7 @@ #define CONFIG_USB_PD_DECODE_SOP #undef CONFIG_USB_CHARGER #define CONFIG_USB_POWER_DELIVERY -#define CONFIG_USB_PID 0x5040 +#define CONFIG_USB_PID 0x5040 #define CONFIG_USB_PD_ALT_MODE #define CONFIG_USB_PD_ALT_MODE_DFP #define CONFIG_USB_PD_DISCHARGE_PPC @@ -193,10 +191,10 @@ #define CONFIG_USBC_VCONN #define CONFIG_USBC_VCONN_SWAP -#define USB_PD_PORT_TCPC_0 0 +#define USB_PD_PORT_TCPC_0 0 #define BOARD_TCPC_C0_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS #define BOARD_TCPC_C0_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS -#define USB_PD_PORT_TCPC_1 1 +#define USB_PD_PORT_TCPC_1 1 #define BOARD_TCPC_C1_RESET_HOLD_DELAY ANX74XX_RESET_HOLD_MS #define BOARD_TCPC_C1_RESET_POST_DELAY ANX74XX_RESET_HOLD_MS @@ -208,16 +206,16 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_SENSORS NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_PPC1 NPCX_I2C_PORT2_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT7_0 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSORS NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_PPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT7_0 /* * LED backlight controller @@ -239,11 +237,11 @@ enum charge_port { }; enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -268,10 +266,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_COUNT }; enum sensor_id { SCREEN_ACCEL = 0, @@ -286,7 +281,6 @@ enum ssfc_led_id { SSFC_LED_COUNT, }; - /* Board specific handlers */ void board_reset_pd_mcu(void); void board_set_tcpc_power_mode(int port, int mode); @@ -299,20 +293,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit) (not used). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) /* @@ -321,11 +315,10 @@ void show_critical_error(void); /* * Led driver IC (2 bits). */ -#define EC_SSFC_LED_L 0 -#define EC_SSFC_LED_H 1 +#define EC_SSFC_LED_L 0 +#define EC_SSFC_LED_H 1 #define EC_SSFC_LED_MASK GENMASK(EC_SSFC_LED_H, EC_SSFC_LED_L) - unsigned int ec_config_get_bj_power(void); unsigned int ec_config_get_thermal_solution(void); unsigned int ec_ssfc_get_led_ic(void); @@ -335,31 +328,31 @@ void board_backlight_enable_interrupt(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From cc66f6ba7139ae554098380238b2b758d6c67460 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:00 -0600 Subject: driver/charger/rt946x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I816116800507bfd7a34d3ab8a76bae5ee83a8c59 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729966 Reviewed-by: Jeremy Bettis --- driver/charger/rt946x.c | 262 ++++++++++++++++++++++++------------------------ 1 file changed, 131 insertions(+), 131 deletions(-) diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c index 1f932b87f5..9949cfa12a 100644 --- a/driver/charger/rt946x.c +++ b/driver/charger/rt946x.c @@ -27,34 +27,34 @@ #include "util.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #define CPRINTS(format, args...) \ - cprints(CC_CHARGER, "%s " format, "RT946X", ## args) + cprints(CC_CHARGER, "%s " format, "RT946X", ##args) /* Charger parameters */ -#define CHARGER_NAME RT946X_CHARGER_NAME -#define CHARGE_V_MAX 4710 -#define CHARGE_V_MIN 3900 -#define CHARGE_V_STEP 10 -#define CHARGE_I_MAX 5000 -#define CHARGE_I_MIN 100 -#define CHARGE_I_OFF 0 -#define CHARGE_I_STEP 100 -#define INPUT_I_MAX 3250 -#define INPUT_I_MIN 100 -#define INPUT_I_STEP 50 +#define CHARGER_NAME RT946X_CHARGER_NAME +#define CHARGE_V_MAX 4710 +#define CHARGE_V_MIN 3900 +#define CHARGE_V_STEP 10 +#define CHARGE_I_MAX 5000 +#define CHARGE_I_MIN 100 +#define CHARGE_I_OFF 0 +#define CHARGE_I_STEP 100 +#define INPUT_I_MAX 3250 +#define INPUT_I_MIN 100 +#define INPUT_I_STEP 50 /* Charger parameters */ static const struct charger_info rt946x_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = CHARGE_I_MAX, - .current_min = CHARGE_I_MIN, + .current_max = CHARGE_I_MAX, + .current_min = CHARGE_I_MIN, .current_step = CHARGE_I_STEP, - .input_current_max = INPUT_I_MAX, - .input_current_min = INPUT_I_MIN, + .input_current_max = INPUT_I_MAX, + .input_current_min = INPUT_I_MIN, .input_current_step = INPUT_I_STEP, }; @@ -67,8 +67,8 @@ static const struct rt946x_init_setting default_init_setting = { .boost_current = 1500, }; -__attribute__((weak)) -const struct rt946x_init_setting *board_rt946x_init_setting(void) +__attribute__((weak)) const struct rt946x_init_setting * +board_rt946x_init_setting(void) { return &default_init_setting; } @@ -135,11 +135,17 @@ static const unsigned char mt6370_reg_en_hidden_mode[] = { }; static const unsigned char mt6370_val_en_hidden_mode[] = { - 0x96, 0x69, 0xC3, 0x3C, + 0x96, + 0x69, + 0xC3, + 0x3C, }; static const unsigned char mt6370_val_en_test_mode[] = { - 0x69, 0x96, 0x63, 0x70, + 0x69, + 0x96, + 0x63, + 0x70, }; #endif /* CONFIG_CHARGER_MT6370 */ @@ -192,17 +198,13 @@ enum rt946x_irq { }; static uint8_t rt946x_irqmask[RT946X_IRQ_COUNT] = { - 0xBF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFC, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, + 0xBF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; static const uint8_t rt946x_irq_maskall[RT946X_IRQ_COUNT] = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; #endif @@ -233,8 +235,7 @@ static enum ec_error_list rt946x_block_write(int chgnum, int reg, const uint8_t *val, int len) { return i2c_write_block(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - reg, val, len); + chg_chips[chgnum].i2c_addr_flags, reg, val, len); } static int rt946x_update_bits(int chgnum, int reg, int mask, int val) @@ -309,13 +310,13 @@ static int mt6370_enable_hidden_mode(int chgnum, int en) if (in_interrupt_context()) { CPRINTS("Err: use hidden mode in IRQ"); return EC_ERROR_INVAL; - } + } mutex_lock(&hidden_mode_lock); if (en) { if (hidden_mode_cnt == 0) { - rv = rt946x_block_write(chgnum, - mt6370_reg_en_hidden_mode[0], + rv = rt946x_block_write( + chgnum, mt6370_reg_en_hidden_mode[0], mt6370_val_en_hidden_mode, ARRAY_SIZE(mt6370_val_en_hidden_mode)); if (rv) @@ -386,15 +387,15 @@ static int mt6370_ichg_workaround(int chgnum, int new_ichg) static inline int rt946x_enable_wdt(int chgnum, int en) { - return (en ? rt946x_set_bit : rt946x_clr_bit) - (chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN); + return (en ? rt946x_set_bit : rt946x_clr_bit)( + chgnum, RT946X_REG_CHGCTRL13, RT946X_MASK_WDT_EN); } /* Enable high-impedance mode */ static inline int rt946x_enable_hz(int chgnum, int en) { - return (en ? rt946x_set_bit : rt946x_clr_bit) - (chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN); + return (en ? rt946x_set_bit : rt946x_clr_bit)( + chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_HZ_EN); } int rt946x_por_reset(void) @@ -470,7 +471,7 @@ static int rt946x_set_ieoc(int chgnum, unsigned int ieoc) CPRINTS("ieoc=%d", ieoc); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL9, RT946X_MASK_IEOC, - reg_ieoc << RT946X_SHIFT_IEOC); + reg_ieoc << RT946X_SHIFT_IEOC); } static int rt946x_set_mivr(int chgnum, unsigned int mivr) @@ -478,12 +479,12 @@ static int rt946x_set_mivr(int chgnum, unsigned int mivr) uint8_t reg_mivr = 0; reg_mivr = rt946x_closest_reg(RT946X_MIVR_MIN, RT946X_MIVR_MAX, - RT946X_MIVR_STEP, mivr); + RT946X_MIVR_STEP, mivr); CPRINTS("mivr=%d", mivr); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL6, RT946X_MASK_MIVR, - reg_mivr << RT946X_SHIFT_MIVR); + reg_mivr << RT946X_SHIFT_MIVR); } static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage) @@ -491,13 +492,14 @@ static int rt946x_set_boost_voltage(int chgnum, unsigned int voltage) uint8_t reg_voltage = 0; reg_voltage = rt946x_closest_reg(RT946X_BOOST_VOLTAGE_MIN, - RT946X_BOOST_VOLTAGE_MAX, RT946X_BOOST_VOLTAGE_STEP, voltage); + RT946X_BOOST_VOLTAGE_MAX, + RT946X_BOOST_VOLTAGE_STEP, voltage); CPRINTS("voltage=%d", voltage); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL5, - RT946X_MASK_BOOST_VOLTAGE, - reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE); + RT946X_MASK_BOOST_VOLTAGE, + reg_voltage << RT946X_SHIFT_BOOST_VOLTAGE); } static int rt946x_set_boost_current(int chgnum, unsigned int current) @@ -517,8 +519,8 @@ static int rt946x_set_boost_current(int chgnum, unsigned int current) CPRINTS("current=%d", current); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL10, - RT946X_MASK_BOOST_CURRENT, - i << RT946X_SHIFT_BOOST_CURRENT); + RT946X_MASK_BOOST_CURRENT, + i << RT946X_SHIFT_BOOST_CURRENT); } static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp) @@ -526,13 +528,14 @@ static int rt946x_set_ircmp_vclamp(int chgnum, unsigned int vclamp) uint8_t reg_vclamp = 0; reg_vclamp = rt946x_closest_reg(RT946X_IRCMP_VCLAMP_MIN, - RT946X_IRCMP_VCLAMP_MAX, RT946X_IRCMP_VCLAMP_STEP, vclamp); + RT946X_IRCMP_VCLAMP_MAX, + RT946X_IRCMP_VCLAMP_STEP, vclamp); CPRINTS("vclamp=%d", vclamp); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL18, - RT946X_MASK_IRCMP_VCLAMP, - reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP); + RT946X_MASK_IRCMP_VCLAMP, + reg_vclamp << RT946X_SHIFT_IRCMP_VCLAMP); } static int rt946x_set_ircmp_res(int chgnum, unsigned int res) @@ -540,7 +543,7 @@ static int rt946x_set_ircmp_res(int chgnum, unsigned int res) uint8_t reg_res = 0; reg_res = rt946x_closest_reg(RT946X_IRCMP_RES_MIN, RT946X_IRCMP_RES_MAX, - RT946X_IRCMP_RES_STEP, res); + RT946X_IRCMP_RES_STEP, res); CPRINTS("res=%d", res); @@ -554,7 +557,7 @@ static int rt946x_set_vprec(int chgnum, unsigned int vprec) uint8_t reg_vprec = 0; reg_vprec = rt946x_closest_reg(RT946X_VPREC_MIN, RT946X_VPREC_MAX, - RT946X_VPREC_STEP, vprec); + RT946X_VPREC_STEP, vprec); CPRINTS("vprec=%d", vprec); @@ -568,7 +571,7 @@ static int rt946x_set_iprec(int chgnum, unsigned int iprec) uint8_t reg_iprec = 0; reg_iprec = rt946x_closest_reg(RT946X_IPREC_MIN, RT946X_IPREC_MAX, - RT946X_IPREC_STEP, iprec); + RT946X_IPREC_STEP, iprec); CPRINTS("iprec=%d", iprec); @@ -642,12 +645,10 @@ static int rt946x_init_setting(int chgnum) rv = rt946x_set_ieoc(chgnum, setting->eoc_current); if (rv) return rv; - rv = rt946x_set_boost_voltage(chgnum, - setting->boost_voltage); + rv = rt946x_set_boost_voltage(chgnum, setting->boost_voltage); if (rv) return rv; - rv = rt946x_set_boost_current(chgnum, - setting->boost_current); + rv = rt946x_set_boost_current(chgnum, setting->boost_current); if (rv) return rv; rv = rt946x_set_ircmp_vclamp(chgnum, setting->ircmp_vclamp); @@ -657,7 +658,8 @@ static int rt946x_init_setting(int chgnum) if (rv) return rv; rv = rt946x_set_vprec(chgnum, batt_info->precharge_voltage ? - batt_info->precharge_voltage : batt_info->voltage_min); + batt_info->precharge_voltage : + batt_info->voltage_min); if (rv) return rv; rv = rt946x_set_iprec(chgnum, batt_info->precharge_current); @@ -665,8 +667,9 @@ static int rt946x_init_setting(int chgnum) return rv; #ifdef CONFIG_CHARGER_MT6370_BACKLIGHT - rt946x_write8(chgnum, MT6370_BACKLIGHT_BLEN, - MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN | + rt946x_write8( + chgnum, MT6370_BACKLIGHT_BLEN, + MT6370_MASK_BLED_EXT_EN | MT6370_MASK_BLED_EN | MT6370_MASK_BLED_1CH_EN | MT6370_MASK_BLED_2CH_EN | MT6370_MASK_BLED_3CH_EN | MT6370_MASK_BLED_4CH_EN | MT6370_BLED_CODE_LINEAR); @@ -681,8 +684,8 @@ static int rt946x_init_setting(int chgnum) #ifdef CONFIG_CHARGER_OTG static enum ec_error_list rt946x_enable_otg_power(int chgnum, int enabled) { - return (enabled ? rt946x_set_bit : rt946x_clr_bit) - (chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE); + return (enabled ? rt946x_set_bit : rt946x_clr_bit)( + chgnum, RT946X_REG_CHGCTRL1, RT946X_MASK_OPA_MODE); } static int rt946x_is_sourcing_otg_power(int chgnum, int port) @@ -700,16 +703,16 @@ static enum ec_error_list rt946x_set_input_current_limit(int chgnum, int input_current) { uint8_t reg_iin = 0; - const struct charger_info * const info = rt946x_get_info(chgnum); + const struct charger_info *const info = rt946x_get_info(chgnum); reg_iin = rt946x_closest_reg(info->input_current_min, - info->input_current_max, info->input_current_step, - input_current); + info->input_current_max, + info->input_current_step, input_current); CPRINTS("iin=%d", input_current); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_AICR, - reg_iin << RT946X_SHIFT_AICR); + reg_iin << RT946X_SHIFT_AICR); } static enum ec_error_list rt946x_get_input_current_limit(int chgnum, @@ -717,15 +720,15 @@ static enum ec_error_list rt946x_get_input_current_limit(int chgnum, { int rv; int val = 0; - const struct charger_info * const info = rt946x_get_info(chgnum); + const struct charger_info *const info = rt946x_get_info(chgnum); rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL3, &val); if (rv) return rv; val = (val & RT946X_MASK_AICR) >> RT946X_SHIFT_AICR; - *input_current = val * info->input_current_step - + info->input_current_min; + *input_current = + val * info->input_current_step + info->input_current_min; return EC_SUCCESS; } @@ -781,7 +784,6 @@ static enum ec_error_list rt946x_get_status(int chgnum, int *status) if (val & RT946X_MASK_CHG_VBATOV) *status |= CHARGER_VOLTAGE_OR; - rv = rt946x_read8(chgnum, RT946X_REG_CHGNTC, &val); if (rv) return rv; @@ -832,7 +834,7 @@ static enum ec_error_list rt946x_get_current(int chgnum, int *current) { int rv; int val = 0; - const struct charger_info * const info = rt946x_get_info(chgnum); + const struct charger_info *const info = rt946x_get_info(chgnum); rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL7, &val); if (rv) @@ -905,7 +907,7 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage) { int rv; int val = 0; - const struct charger_info * const info = rt946x_get_info(chgnum); + const struct charger_info *const info = rt946x_get_info(chgnum); rv = rt946x_read8(chgnum, RT946X_REG_CHGCTRL4, &val); if (rv) @@ -920,13 +922,13 @@ static enum ec_error_list rt946x_get_voltage(int chgnum, int *voltage) static enum ec_error_list rt946x_set_voltage(int chgnum, int voltage) { uint8_t reg_cv = 0; - const struct charger_info * const info = rt946x_get_info(chgnum); + const struct charger_info *const info = rt946x_get_info(chgnum); reg_cv = rt946x_closest_reg(info->voltage_min, info->voltage_max, - info->voltage_step, voltage); + info->voltage_step, voltage); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL4, RT946X_MASK_CV, - reg_cv << RT946X_SHIFT_CV); + reg_cv << RT946X_SHIFT_CV); } static enum ec_error_list rt946x_discharge_on_ac(int chgnum, int enable) @@ -940,8 +942,8 @@ static int rt946x_enable_ilim_pin(int chgnum, int en) { int ret; - ret = (en ? rt946x_set_bit : rt946x_clr_bit) - (chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN); + ret = (en ? rt946x_set_bit : rt946x_clr_bit)( + chgnum, RT946X_REG_CHGCTRL3, RT946X_MASK_ILIMEN); return ret; } @@ -1001,7 +1003,8 @@ static int rt946x_set_aicl_vth(int chgnum, uint8_t aicl_vth) uint8_t reg_aicl_vth = 0; reg_aicl_vth = rt946x_closest_reg(RT946X_AICLVTH_MIN, - RT946X_AICLVTH_MAX, RT946X_AICLVTH_STEP, aicl_vth); + RT946X_AICLVTH_MAX, + RT946X_AICLVTH_STEP, aicl_vth); return rt946x_update_bits(chgnum, RT946X_REG_CHGCTRL14, RT946X_MASK_AICLVTH, @@ -1079,14 +1082,13 @@ static void rt946x_init(int chgnum) static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat) { int ret, reg; - int chg_type = - (usb_stat & MT6370_MASK_USB_STATUS) >> MT6370_SHIFT_USB_STATUS; + int chg_type = (usb_stat & MT6370_MASK_USB_STATUS) >> + MT6370_SHIFT_USB_STATUS; int dp_2_3v, dm_2_3v; /* Only SDP/CDP/DCP could possibly be Apple/Samsung TA */ if (chg_type != MT6370_CHG_TYPE_SDPNSTD && - chg_type != MT6370_CHG_TYPE_CDP && - chg_type != MT6370_CHG_TYPE_DCP) + chg_type != MT6370_CHG_TYPE_CDP && chg_type != MT6370_CHG_TYPE_DCP) return chg_type; if (chg_type == MT6370_CHG_TYPE_SDPNSTD || @@ -1115,13 +1117,13 @@ static int mt6370_detect_apple_samsung_ta(int chgnum, int usb_stat) ret = rt946x_update_bits(chgnum, MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM, MT6370_MASK_APP_REF | MT6370_MASK_APP_SS_PL | - MT6370_MASK_APP_SS_EN); + MT6370_MASK_APP_SS_EN); ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, ®); dp_2_3v = reg & MT6370_MASK_APP_OUT; /* Check D- > 2.3 V */ - ret |= rt946x_update_bits(chgnum, - MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM, + ret |= rt946x_update_bits( + chgnum, MT6370_REG_QCSTATUS2, MT6360_MASK_CHECK_DPDM, MT6370_MASK_APP_REF | MT6370_MASK_APP_DPDM_IN | MT6370_MASK_APP_SS_PL | MT6370_MASK_APP_SS_EN); ret |= rt946x_read8(chgnum, MT6370_REG_QCSTATUS2, ®); @@ -1327,7 +1329,7 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val) if (in_interrupt_context()) { CPRINTS("Err: use ADC in IRQ"); return EC_ERROR_INVAL; - } + } mutex_lock(&adc_access_lock); #ifdef CONFIG_CHARGER_MT6370 mt6370_enable_hidden_mode(CHARGER_SOLO, 1); @@ -1355,8 +1357,8 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val) for (i = 0; i < max_wait_times; i++) { msleep(35); rv = mt6370_pmu_reg_test_bit(CHARGER_SOLO, RT946X_REG_CHGADC, - RT946X_SHIFT_ADC_START, - &adc_start); + RT946X_SHIFT_ADC_START, + &adc_start); if (!adc_start && rv == 0) break; } @@ -1377,8 +1379,9 @@ int rt946x_get_adc(enum rt946x_adc_in_sel adc_sel, int *adc_val) *adc_val = adc_result; #elif defined(CONFIG_CHARGER_MT6370) /* Calculate ADC value */ - adc_result = (adc_data_h * 256 + adc_data_l) - * mt6370_adc_unit[adc_sel] + mt6370_adc_offset[adc_sel]; + adc_result = + (adc_data_h * 256 + adc_data_l) * mt6370_adc_unit[adc_sel] + + mt6370_adc_offset[adc_sel]; /* For TS_BAT/TS_BUS, the real unit is 0.25, here we use 25(unit) */ if (adc_sel == MT6370_ADC_TS_BAT) @@ -1447,7 +1450,7 @@ static int mt6370_pmu_chg_mivr_irq_handler(int chgnum) int rv, ibus = 0, mivr_stat; rv = mt6370_pmu_reg_test_bit(chgnum, MT6370_REG_CHGSTAT1, - MT6370_SHIFT_MIVR_STAT, &mivr_stat); + MT6370_SHIFT_MIVR_STAT, &mivr_stat); if (rv) return rv; @@ -1557,9 +1560,8 @@ static void rt946x_usb_charger_task_init(const int unused_port) mt6370_get_bc12_device_type(chg_type); chg.current = mt6370_get_bc12_ilim(bc12_type); } else { - bc12_type = - rt946x_get_bc12_device_type(CHARGER_SOLO, - chg_type); + bc12_type = rt946x_get_bc12_device_type( + CHARGER_SOLO, chg_type); chg.current = rt946x_get_bc12_ilim(bc12_type); } CPRINTS("BC12 type %d", bc12_type); @@ -1568,8 +1570,8 @@ static void rt946x_usb_charger_task_init(const int unused_port) if (IS_ENABLED(CONFIG_WIRELESS_CHARGER_P9221_R7) && bc12_type == CHARGE_SUPPLIER_BC12_SDP && wpc_chip_is_online()) { - p9221_notify_vbus_change(1); - CPRINTS("WPC ON"); + p9221_notify_vbus_change(1); + CPRINTS("WPC ON"); } if (bc12_type == CHARGE_SUPPLIER_BC12_SDP && ++bc12_cnt < max_bc12_cnt) { @@ -1577,13 +1579,13 @@ static void rt946x_usb_charger_task_init(const int unused_port) * defer the workaround and awaiting for * waken up by the interrupt. */ - hook_call_deferred( - &rt946x_bc12_workaround_data, 5); + hook_call_deferred(&rt946x_bc12_workaround_data, + 5); goto wait_event; } charge_manager_update_charge(bc12_type, 0, &chg); -bc12_none: + bc12_none: rt946x_enable_bc12_detection(CHARGER_SOLO, 0); } @@ -1598,7 +1600,7 @@ bc12_none: charge_manager_update_charge(bc12_type, 0, NULL); } -wait_event: + wait_event: task_wait_event(-1); } } @@ -1618,8 +1620,8 @@ static int rt946x_ramp_max(int supplier, int sup_curr) int rt946x_enable_charger_boost(int en) { - return (en ? rt946x_set_bit : rt946x_clr_bit) - (CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN); + return (en ? rt946x_set_bit : rt946x_clr_bit)( + CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_CHG_EN); } /* @@ -1631,7 +1633,8 @@ int rt946x_is_vbus_ready(void) int val = 0; return rt946x_read8(CHARGER_SOLO, RT946X_REG_CHGSTATC, &val) ? - 0 : !!(val & RT946X_MASK_PWR_RDY); + 0 : + !!(val & RT946X_MASK_PWR_RDY); } int rt946x_is_charge_done(void) @@ -1649,10 +1652,10 @@ int rt946x_is_charge_done(void) int rt946x_cutoff_battery(void) { #ifdef CONFIG_CHARGER_MT6370 -/* - * We should lock ADC usage to prevent from using ADC while - * cut-off. Or this might cause the ADC power not turning off. - */ + /* + * We should lock ADC usage to prevent from using ADC while + * cut-off. Or this might cause the ADC power not turning off. + */ int rv; @@ -1675,7 +1678,7 @@ int rt946x_cutoff_battery(void) /* disable chg auto sensing */ mt6370_enable_hidden_mode(CHARGER_SOLO, 1); rv = rt946x_clr_bit(CHARGER_SOLO, MT6370_REG_CHGHIDDENCTRL15, - MT6370_MASK_ADC_TS_AUTO); + MT6370_MASK_ADC_TS_AUTO); mt6370_enable_hidden_mode(CHARGER_SOLO, 0); if (rv) goto out; @@ -1695,14 +1698,14 @@ out: int rt946x_enable_charge_termination(int en) { - return (en ? rt946x_set_bit : rt946x_clr_bit) - (CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE); + return (en ? rt946x_set_bit : rt946x_clr_bit)( + CHARGER_SOLO, RT946X_REG_CHGCTRL2, RT946X_MASK_TE); } int rt946x_enable_charge_eoc(int en) { - return (en ? rt946x_set_bit : rt946x_clr_bit) - (CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC); + return (en ? rt946x_set_bit : rt946x_clr_bit)( + CHARGER_SOLO, RT946X_REG_CHGCTRL9, RT946X_MASK_EOC); } #ifdef CONFIG_CHARGER_MT6370 @@ -1745,29 +1748,26 @@ int mt6370_db_set_voltages(int vbst, int vpos, int vneg) int rv; /* set display bias VBST */ - rv = rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVBST, - MT6370_MASK_DB_VBST, - rt946x_closest_reg(MT6370_DB_VBST_MIN, - MT6370_DB_VBST_MAX, - MT6370_DB_VBST_STEP, vbst)); + rv = rt946x_update_bits( + CHARGER_SOLO, MT6370_REG_DBVBST, MT6370_MASK_DB_VBST, + rt946x_closest_reg(MT6370_DB_VBST_MIN, MT6370_DB_VBST_MAX, + MT6370_DB_VBST_STEP, vbst)); /* set display bias VPOS */ - rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVPOS, - MT6370_MASK_DB_VPOS, - rt946x_closest_reg(MT6370_DB_VPOS_MIN, - MT6370_DB_VPOS_MAX, - MT6370_DB_VPOS_STEP, vpos)); + rv |= rt946x_update_bits( + CHARGER_SOLO, MT6370_REG_DBVPOS, MT6370_MASK_DB_VPOS, + rt946x_closest_reg(MT6370_DB_VPOS_MIN, MT6370_DB_VPOS_MAX, + MT6370_DB_VPOS_STEP, vpos)); /* set display bias VNEG */ - rv |= rt946x_update_bits(CHARGER_SOLO, MT6370_REG_DBVNEG, - MT6370_MASK_DB_VNEG, - rt946x_closest_reg(MT6370_DB_VNEG_MIN, - MT6370_DB_VNEG_MAX, - MT6370_DB_VNEG_STEP, vneg)); + rv |= rt946x_update_bits( + CHARGER_SOLO, MT6370_REG_DBVNEG, MT6370_MASK_DB_VNEG, + rt946x_closest_reg(MT6370_DB_VNEG_MIN, MT6370_DB_VNEG_MAX, + MT6370_DB_VNEG_STEP, vneg)); /* Enable VNEG/VPOS discharge when VNEG/VPOS rails disabled. */ - rv |= rt946x_update_bits(CHARGER_SOLO, - MT6370_REG_DBCTRL2, + rv |= rt946x_update_bits( + CHARGER_SOLO, MT6370_REG_DBCTRL2, MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC, MT6370_MASK_DB_VNEG_DISC | MT6370_MASK_DB_VPOS_DISC); -- cgit v1.2.1 From 94718819dab89cd68cdd18ef51b184ff863de7d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:25 -0600 Subject: board/oak/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9b3c508fdaab97be3187f071640f2dbdc40c8dc3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728789 Reviewed-by: Jeremy Bettis --- board/oak/board.c | 111 +++++++++++++++++++++++++----------------------------- 1 file changed, 51 insertions(+), 60 deletions(-) diff --git a/board/oak/board.c b/board/oak/board.c index 1c2e65b12a..77592eea99 100644 --- a/board/oak/board.c +++ b/board/oak/board.c @@ -52,8 +52,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Dispaly port hardware can connect to port 0, 1 or neither. */ #define PD_PORT_NONE -1 @@ -76,8 +76,8 @@ void usb_evt(enum gpio_signal signal) /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD"}, - {GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED"}, + { GPIO_SOC_POWER_GOOD, POWER_SIGNAL_ACTIVE_HIGH, "POWER_GOOD" }, + { GPIO_SUSPEND_L, POWER_SIGNAL_ACTIVE_LOW, "SUSPEND#_ASSERTED" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -87,39 +87,32 @@ const struct adc_t adc_channels[] = { * PSYS_MONITOR(PA2): ADC_IN2, 1.44 uA/W on 6.05k Ohm * output in mW */ - [ADC_PSYS] = {"PSYS", 379415, 4096, 0, STM32_AIN(2)}, + [ADC_PSYS] = { "PSYS", 379415, 4096, 0, STM32_AIN(2) }, /* AMON_BMON(PC0): ADC_IN10, output in uV */ - [ADC_AMON_BMON] = {"AMON_BMON", 183333, 4096, 0, STM32_AIN(10)}, + [ADC_AMON_BMON] = { "AMON_BMON", 183333, 4096, 0, STM32_AIN(10) }, /* VDC_BOOSTIN_SENSE(PC1): ADC_IN11, output in mV */ - [ADC_VBUS] = {"VBUS", 33000, 4096, 0, STM32_AIN(11)}, + [ADC_VBUS] = { "VBUS", 33000, 4096, 0, STM32_AIN(11) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C ports */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "pd", - .port = I2C_PORT_PD_MCU, - .kbps = 1000, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - } -}; +const struct i2c_port_t i2c_ports[] = { { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "pd", + .port = I2C_PORT_PD_MCU, + .kbps = 1000, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA } }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); #ifdef CONFIG_ACCELGYRO_BMI160 /* SPI devices */ -const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_ACCEL_PORT, 1, GPIO_SPI2_NSS } -}; +const struct spi_device_t spi_devices[] = { { CONFIG_SPI_ACCEL_PORT, 1, + GPIO_SPI2_NSS } }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); #endif @@ -184,21 +177,20 @@ const struct charger_config_t chg_chips[] = { * src/mainboard/google/${board}/acpi/dptf.asl */ const struct temp_sensor_t temp_sensors[] = { - {"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_LOCAL}, - {"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE1}, - {"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, - TMP432_IDX_REMOTE2}, - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, - 0}, + { "TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_LOCAL }, + { "TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE1 }, + { "TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val, + TMP432_IDX_REMOTE2 }, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); #ifdef HAS_TASK_ALS /* ALS instances. Must be in same order as enum als_id. */ struct als_t als[] = { - {"TI", opt3001_init, opt3001_read_lux, 5}, + { "TI", opt3001_init, opt3001_read_lux, 5 }, }; BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT); #endif @@ -208,14 +200,14 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { .usb_port = 0, .i2c_port = I2C_PORT_USB_MUX, .i2c_addr_flags = PI3USB3X532_I2C_ADDR0, - .driver = &pi3usb3x532_usb_mux_driver, + .driver = &pi3usb3x532_usb_mux_driver, }, { .usb_port = 1, .i2c_port = I2C_PORT_USB_MUX, #if (BOARD_REV <= OAK_REV4) .i2c_addr_flags = PI3USB3X532_I2C_ADDR1, - .driver = &pi3usb3x532_usb_mux_driver, + .driver = &pi3usb3x532_usb_mux_driver, #else .i2c_addr_flags = 0x10, .driver = &ps8740_usb_mux_driver, @@ -340,10 +332,12 @@ int board_set_active_charge_port(int charge_port) } else { /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L : - GPIO_USB_C1_CHARGE_L, 1); + GPIO_USB_C1_CHARGE_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 0); + GPIO_USB_C0_CHARGE_L, + 0); } return EC_SUCCESS; @@ -357,11 +351,11 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); pd_send_host_event(PD_EVENT_POWER_CHANGE); } @@ -552,8 +546,8 @@ void vbus_task(void *u) } if (wake) - usb_charger_task_set_event( - port, USB_CHG_EVENT_BC12); + usb_charger_task_set_event(port, + USB_CHG_EVENT_BC12); } task_wait_event(-1); } @@ -569,15 +563,15 @@ void vbus_task(void *u) #ifdef CONFIG_TEMP_SENSOR_TMP432 static void tmp432_set_power_deferred(void) { - /* Shut tmp432 down if not in S0 && no external power */ - if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) { - if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF)) + /* Shut tmp432 down if not in S0 && no external power */ + if (!extpower_is_present() && !chipset_in_state(CHIPSET_STATE_ON)) { + if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_OFF)) CPRINTS("ERROR: Can't shutdown TMP432."); - return; - } + return; + } - /* else, turn it on. */ - if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON)) + /* else, turn it on. */ + if (EC_SUCCESS != tmp432_set_power(TMP432_POWER_ON)) CPRINTS("ERROR: Can't turn on TMP432."); } DECLARE_DEFERRED(tmp432_set_power_deferred); @@ -602,7 +596,7 @@ static void board_chipset_pre_init(void) board_extpower_buffer_to_soc(); #if BOARD_REV >= OAK_REV5 /* Enable DP muxer */ - gpio_set_level(GPIO_DP_MUX_EN_L , 0); + gpio_set_level(GPIO_DP_MUX_EN_L, 0); gpio_set_level(GPIO_PARADE_MUX_EN, 1); #endif } @@ -615,13 +609,12 @@ static void board_chipset_shutdown(void) gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1); #if BOARD_REV >= OAK_REV5 /* Disable DP muxer */ - gpio_set_level(GPIO_DP_MUX_EN_L , 1); + gpio_set_level(GPIO_DP_MUX_EN_L, 1); gpio_set_level(GPIO_PARADE_MUX_EN, 0); #endif } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); - /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) { @@ -650,11 +643,9 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; #endif static struct kionix_accel_data g_kx022_data; -- cgit v1.2.1 From 9e1c4e272dcfa992daab2617f543a24f1b209cd4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:00 -0600 Subject: chip/mchp/qmspi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24ae1920837d05433abf27ce42e9fe0fc4c07745 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729309 Reviewed-by: Jeremy Bettis --- chip/mchp/qmspi.c | 100 ++++++++++++++++++++++++------------------------------ 1 file changed, 44 insertions(+), 56 deletions(-) diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c index b170d75283..a054abc178 100644 --- a/chip/mchp/qmspi.c +++ b/chip/mchp/qmspi.c @@ -21,14 +21,12 @@ #include "tfdp_chip.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #define QMSPI_TRANSFER_TIMEOUT (100 * MSEC) #define QMSPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) #define QMSPI_BYTE_TRANSFER_POLL_INTERVAL_US 20 - - #ifndef CONFIG_MCHP_QMSPI_TX_DMA #ifdef LFW /* @@ -137,8 +135,8 @@ static uint32_t qmspi_build_tx_descr(uint32_t ntx, uint32_t ndid) * value (1, 2, or 4). * Caller will apply close and last flags if applicable. */ -static uint64_t qmspi_build_rx_descr(uint32_t raddr, - uint32_t nrx, uint32_t ndid) +static uint64_t qmspi_build_rx_descr(uint32_t raddr, uint32_t nrx, + uint32_t ndid) { uint32_t d, dmau, na; uint64_t u; @@ -182,9 +180,9 @@ static uint64_t qmspi_build_rx_descr(uint32_t raddr, #ifdef CONFIG_MCHP_QMSPI_TX_DMA -#define QMSPI_ERR_ANY 0x80 -#define QMSPI_ERR_BAD_PTR 0x81 -#define QMSPI_ERR_OUT_OF_DESCR 0x85 +#define QMSPI_ERR_ANY 0x80 +#define QMSPI_ERR_BAD_PTR 0x81 +#define QMSPI_ERR_OUT_OF_DESCR 0x85 /* * bits[1:0] of word @@ -206,9 +204,9 @@ static void qmspi_descr_mode_ready(void) int i; MCHP_QMSPI0_CTRL = 0; - MCHP_QMSPI0_IEN = 0; - MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS; - MCHP_QMSPI0_STS = 0xfffffffful; + MCHP_QMSPI0_IEN = 0; + MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_CLR_FIFOS; + MCHP_QMSPI0_STS = 0xfffffffful; MCHP_QMSPI0_CTRL = MCHP_QMSPI_C_DESCR_MODE_EN; /* clear all descriptors */ for (i = 0; i < MCHP_QMSPI_MAX_DESCR; i++) @@ -229,8 +227,7 @@ static void qmspi_descr_mode_ready(void) * and remaining < 16 bytes in byte unit descriptor until all bytes * exhausted or out of descriptors error. */ -static uint32_t qmspi_descr_alloc(uint32_t did, - uint32_t descr, uint32_t nb) +static uint32_t qmspi_descr_alloc(uint32_t did, uint32_t descr, uint32_t nb) { uint32_t nu; @@ -238,8 +235,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did, if (did >= MCHP_QMSPI_MAX_DESCR) return 0xffff; - descr &= ~(MCHP_QMSPI_C_NUM_UNITS_MASK + - MCHP_QMSPI_C_XFRU_MASK); + descr &= + ~(MCHP_QMSPI_C_NUM_UNITS_MASK + MCHP_QMSPI_C_XFRU_MASK); if (nb < (MCHP_QMSPI_C_MAX_UNITS + 1)) { descr |= MCHP_QMSPI_C_XFRU_1B; @@ -252,7 +249,7 @@ static uint32_t qmspi_descr_alloc(uint32_t did, nb -= (nu << 4); } - descr |= ((did+1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); + descr |= ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); MCHP_QMSPI0_DESCR(did) = descr; if (nb) did++; @@ -271,9 +268,8 @@ static uint32_t qmspi_descr_alloc(uint32_t did, * channel and configure the DMA channel for memory to device transfer. */ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma, - uint32_t cfg, - const uint8_t *data, - uint32_t ndata) + uint32_t cfg, const uint8_t *data, + uint32_t ndata) { uint32_t d, d2, did, dma_cfg; @@ -282,7 +278,7 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma, if (ndata <= MCHP_QMSPI_TX_FIFO_LEN) { d2 = d + (ndata << MCHP_QMSPI_C_NUM_UNITS_BITPOS) + - MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA; + MCHP_QMSPI_C_XFRU_1B + MCHP_QMSPI_C_TX_DATA; d2 += ((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_BITPOS); MCHP_QMSPI0_DESCR(did) = d2; while (ndata--) @@ -290,12 +286,10 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma, } else { // TX DMA if (((uint32_t)data | ndata) & 0x03) { dma_cfg = 1; - d |= (MCHP_QMSPI_C_TX_DATA + - MCHP_QMSPI_C_TX_DMA_1B); + d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_1B); } else { dma_cfg = 4; - d |= (MCHP_QMSPI_C_TX_DATA + - MCHP_QMSPI_C_TX_DMA_4B); + d |= (MCHP_QMSPI_C_TX_DATA + MCHP_QMSPI_C_TX_DMA_4B); } did = qmspi_descr_alloc(did, d, ndata); if (did == 0xffff) @@ -303,10 +297,9 @@ static uint32_t qmspi_xmit_data_descr(const struct dma_option *opdma, dma_clr_chan(opdma->channel); dma_cfg_buffers(opdma->channel, data, ndata, - (void *)MCHP_QMSPI0_TX_FIFO_ADDR); - dma_cfg_xfr(opdma->channel, dma_cfg, - MCHP_DMA_QMSPI0_TX_REQ_ID, - (DMA_FLAG_M2D + DMA_FLAG_INCR_MEM)); + (void *)MCHP_QMSPI0_TX_FIFO_ADDR); + dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_TX_REQ_ID, + (DMA_FLAG_M2D + DMA_FLAG_INCR_MEM)); dma_run(opdma->channel); } @@ -327,8 +320,8 @@ void qmspi_cfg_irq_start(uint8_t flags) MCHP_QMSPI0_IEN = 0; if (flags & (1u << 1)) { - MCHP_QMSPI0_IEN = (MCHP_QMSPI_STS_DONE + - MCHP_QMSPI_STS_PROG_ERR); + MCHP_QMSPI0_IEN = + (MCHP_QMSPI_STS_DONE + MCHP_QMSPI_STS_PROG_ERR); MCHP_INT_ENABLE(MCHP_QMSPI_GIRQ) = MCHP_QMSPI_GIRQ_BIT; } @@ -349,10 +342,9 @@ void qmspi_cfg_irq_start(uint8_t flags) * returns last descriptor 0 <= index < MCHP_QMSPI_MAX_DESCR * or error (bit[7]==1) */ -uint8_t qmspi_xfr(const struct spi_device_t *spi_device, - uint32_t np_flags, - const uint8_t *txdata, uint32_t ntx, - uint8_t *rxdata, uint32_t nrx) +uint8_t qmspi_xfr(const struct spi_device_t *spi_device, uint32_t np_flags, + const uint8_t *txdata, uint32_t ntx, uint8_t *rxdata, + uint32_t nrx) { uint32_t d, did, dma_cfg; const struct dma_option *opdma; @@ -399,10 +391,9 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, opdma = spi_dma_option(spi_device, SPI_DMA_OPTION_RD); dma_clr_chan(opdma->channel); dma_cfg_buffers(opdma->channel, rxdata, nrx, - (void *)MCHP_QMSPI0_RX_FIFO_ADDR); - dma_cfg_xfr(opdma->channel, dma_cfg, - MCHP_DMA_QMSPI0_RX_REQ_ID, - (DMA_FLAG_D2M + DMA_FLAG_INCR_MEM)); + (void *)MCHP_QMSPI0_RX_FIFO_ADDR); + dma_cfg_xfr(opdma->channel, dma_cfg, MCHP_DMA_QMSPI0_RX_REQ_ID, + (DMA_FLAG_D2M + DMA_FLAG_INCR_MEM)); dma_run(opdma->channel); } @@ -466,8 +457,8 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, */ #ifdef CONFIG_MCHP_QMSPI_TX_DMA int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { uint32_t np_flags, ntx, nrx; int ret; @@ -482,9 +473,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device, nrx = (uint32_t)rxlen; np_flags = 0x010105; /* b[0]=1 close on done, b[2]=1 start */ - rc = qmspi_xfr(spi_device, np_flags, - txdata, ntx, - rxdata, nrx); + rc = qmspi_xfr(spi_device, np_flags, txdata, ntx, rxdata, nrx); if (rc & QMSPI_ERR_ANY) return EC_ERROR_INVAL; @@ -498,8 +487,8 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device, * Receive using DMA as above. */ int qmspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { const struct dma_option *opdma; uint32_t d, did, dmau; @@ -533,8 +522,7 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device, if (rxdata == NULL) return EC_ERROR_PARAM4; - u = qmspi_build_rx_descr((uint32_t)rxdata, - (uint32_t)rxlen, 2); + u = qmspi_build_rx_descr((uint32_t)rxdata, (uint32_t)rxlen, 2); d = (uint32_t)u; dmau = u >> 32; @@ -547,16 +535,16 @@ int qmspi_transaction_async(const struct spi_device_t *spi_device, dma_xfr_start_rx(opdma, dmau, (uint32_t)rxlen, rxdata); } - MCHP_QMSPI0_DESCR(did) |= (MCHP_QMSPI_C_CLOSE + - MCHP_QMSPI_C_DESCR_LAST); + MCHP_QMSPI0_DESCR(did) |= + (MCHP_QMSPI_C_CLOSE + MCHP_QMSPI_C_DESCR_LAST); MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_START; while (txlen--) { if (MCHP_QMSPI0_STS & MCHP_QMSPI_STS_TX_BUFF_FULL) { if (qmspi_wait(MCHP_QMSPI_STS_TX_BUFF_EMPTY, - MCHP_QMSPI_STS_TX_BUFF_EMPTY) != - EC_SUCCESS) { + MCHP_QMSPI_STS_TX_BUFF_EMPTY) != + EC_SUCCESS) { MCHP_QMSPI0_EXE = MCHP_QMSPI_EXE_STOP; return EC_ERROR_TIMEOUT; } @@ -673,8 +661,8 @@ int qmspi_enable(int hw_port, int enable) { uint8_t unused __attribute__((unused)) = 0; - trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", - hw_port, enable); + trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", hw_port, + enable); if (hw_port != QMSPI0_PORT) return EC_ERROR_INVAL; @@ -685,9 +673,9 @@ int qmspi_enable(int hw_port, int enable) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI); MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; unused = MCHP_QMSPI0_MODE_ACT_SRST; - MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE + - MCHP_QMSPI_M_SPI_MODE0 + - MCHP_QMSPI_M_CLKDIV_12M); + MCHP_QMSPI0_MODE = + (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0 + + MCHP_QMSPI_M_CLKDIV_12M); } else { MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; unused = MCHP_QMSPI0_MODE_ACT_SRST; -- cgit v1.2.1 From 8f0d4bf9c870b5222efe412d5083344d6ceb0b80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:17 -0600 Subject: zephyr/shim/include/usbc/bc12_pi3usb9201.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iccf75eda0232ab0bc13c5e01c05d491d17d82707 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730833 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/bc12_pi3usb9201.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/bc12_pi3usb9201.h b/zephyr/shim/include/usbc/bc12_pi3usb9201.h index 59b84cd868..85b1c00443 100644 --- a/zephyr/shim/include/usbc/bc12_pi3usb9201.h +++ b/zephyr/shim/include/usbc/bc12_pi3usb9201.h @@ -7,4 +7,7 @@ #define PI3USB9201_COMPAT pericom_pi3usb9201 -#define BC12_CHIP_PI3USB9201(id) { .drv = &pi3usb9201_drv, }, +#define BC12_CHIP_PI3USB9201(id) \ + { \ + .drv = &pi3usb9201_drv, \ + }, -- cgit v1.2.1 From 987395bd5a4f4de3b7d52cfeb51b2ae1dcc26e4b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:18:49 -0600 Subject: chip/max32660/uart_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I155697e078e30bf6da7b227c577792e5a078d144 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729237 Reviewed-by: Jeremy Bettis --- chip/max32660/uart_regs.h | 873 ++++++++++++++++++++++++---------------------- 1 file changed, 459 insertions(+), 414 deletions(-) diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h index a2de0cc0a0..d5e9f9bf0d 100644 --- a/chip/max32660/uart_regs.h +++ b/chip/max32660/uart_regs.h @@ -32,15 +32,15 @@ */ typedef struct { __IO uint32_t ctrl; /**< \b 0x00:<\tt> UART CTRL Register */ - __IO uint32_t - thresh_ctrl; /**< \b 0x04:<\tt> UART THRESH_CTRL Register */ + __IO uint32_t thresh_ctrl; /**< \b 0x04:<\tt> UART THRESH_CTRL + Register */ __I uint32_t status; /**< \b 0x08:<\tt> UART STATUS Register */ - __IO uint32_t int_en; /**< \b 0x0C:<\tt> UART INT_EN Register */ - __IO uint32_t int_fl; /**< \b 0x10:<\tt> UART INT_FL Register */ - __IO uint32_t baud0; /**< \b 0x14:<\tt> UART BAUD0 Register */ - __IO uint32_t baud1; /**< \b 0x18:<\tt> UART BAUD1 Register */ - __IO uint32_t fifo; /**< \b 0x1C:<\tt> UART FIFO Register */ - __IO uint32_t dma; /**< \b 0x20:<\tt> UART DMA Register */ + __IO uint32_t int_en; /**< \b 0x0C:<\tt> UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x10:<\tt> UART INT_FL Register */ + __IO uint32_t baud0; /**< \b 0x14:<\tt> UART BAUD0 Register */ + __IO uint32_t baud1; /**< \b 0x18:<\tt> UART BAUD1 Register */ + __IO uint32_t fifo; /**< \b 0x1C:<\tt> UART FIFO Register */ + __IO uint32_t dma; /**< \b 0x20:<\tt> UART DMA Register */ __IO uint32_t tx_fifo; /**< \b 0x24:<\tt> UART TX_FIFO Register */ } mxc_uart_regs_t; @@ -48,630 +48,675 @@ typedef struct { * UART Peripheral Register Offsets from the UART Base Peripheral * Address. */ -#define MXC_R_UART_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_CTRL \ + ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: \ 0x0x000 */ -#define MXC_R_UART_THRESH_CTRL \ - ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_THRESH_CTRL \ + ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: \ 0x0x004 */ -#define MXC_R_UART_STATUS \ - ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_STATUS \ + ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: \ 0x0x008 */ -#define MXC_R_UART_INT_EN \ - ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_INT_EN \ + ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: \ 0x0x00C */ -#define MXC_R_UART_INT_FL \ - ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_INT_FL \ + ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: \ 0x0x010 */ -#define MXC_R_UART_BAUD0 \ - ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_BAUD0 \ + ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: \ 0x0x014 */ -#define MXC_R_UART_BAUD1 \ - ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_BAUD1 \ + ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: \ 0x0x018 */ -#define MXC_R_UART_FIFO \ - ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_FIFO \ + ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: \ 0x0x01C */ -#define MXC_R_UART_DMA \ - ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_DMA \ + ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: \ 0x0x020 */ -#define MXC_R_UART_TX_FIFO \ - ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: \ +#define MXC_R_UART_TX_FIFO \ + ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: \ 0x0x024 */ /** * Control Register. */ #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ -#define MXC_F_UART_CTRL_ENABLE \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ -#define MXC_V_UART_CTRL_ENABLE_DIS \ +#define MXC_F_UART_CTRL_ENABLE \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE \ + Mask */ +#define MXC_V_UART_CTRL_ENABLE_DIS \ ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ -#define MXC_S_UART_CTRL_ENABLE_DIS \ - (MXC_V_UART_CTRL_ENABLE_DIS \ - << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ -#define MXC_V_UART_CTRL_ENABLE_EN \ - ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \ +#define MXC_S_UART_CTRL_ENABLE_DIS \ + (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< \ + CTRL_ENABLE_DIS \ + Setting \ + */ +#define MXC_V_UART_CTRL_ENABLE_EN \ + ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \ */ -#define MXC_S_UART_CTRL_ENABLE_EN \ - (MXC_V_UART_CTRL_ENABLE_EN \ - << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ +#define MXC_S_UART_CTRL_ENABLE_EN \ + (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< \ + CTRL_ENABLE_EN \ + Setting \ + */ #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ #define MXC_F_UART_CTRL_PARITY_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ -#define MXC_V_UART_CTRL_PARITY_EN_DIS \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< \ + CTRL_PARITY_EN \ + Mask */ +#define MXC_V_UART_CTRL_PARITY_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ -#define MXC_S_UART_CTRL_PARITY_EN_DIS \ - (MXC_V_UART_CTRL_PARITY_EN_DIS \ - << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */ -#define MXC_V_UART_CTRL_PARITY_EN_EN \ +#define MXC_S_UART_CTRL_PARITY_EN_DIS \ + (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ + CTRL_PARITY_EN_DIS \ + Setting \ + */ +#define MXC_V_UART_CTRL_PARITY_EN_EN \ ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ -#define MXC_S_UART_CTRL_PARITY_EN_EN \ - (MXC_V_UART_CTRL_PARITY_EN_EN \ - << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */ +#define MXC_S_UART_CTRL_PARITY_EN_EN \ + (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ + CTRL_PARITY_EN_EN \ + Setting \ + */ #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ -#define MXC_F_UART_CTRL_PARITY \ - ((uint32_t)( \ - 0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ -#define MXC_V_UART_CTRL_PARITY_EVEN \ +#define MXC_F_UART_CTRL_PARITY \ + ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY \ + Mask */ +#define MXC_V_UART_CTRL_PARITY_EVEN \ ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ -#define MXC_S_UART_CTRL_PARITY_EVEN \ - (MXC_V_UART_CTRL_PARITY_EVEN \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ -#define MXC_V_UART_CTRL_PARITY_ODD \ +#define MXC_S_UART_CTRL_PARITY_EVEN \ + (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_EVEN \ + Setting \ + */ +#define MXC_V_UART_CTRL_PARITY_ODD \ ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ -#define MXC_S_UART_CTRL_PARITY_ODD \ - (MXC_V_UART_CTRL_PARITY_ODD \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ -#define MXC_V_UART_CTRL_PARITY_MARK \ +#define MXC_S_UART_CTRL_PARITY_ODD \ + (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_ODD \ + Setting \ + */ +#define MXC_V_UART_CTRL_PARITY_MARK \ ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ -#define MXC_S_UART_CTRL_PARITY_MARK \ - (MXC_V_UART_CTRL_PARITY_MARK \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ -#define MXC_V_UART_CTRL_PARITY_SPACE \ +#define MXC_S_UART_CTRL_PARITY_MARK \ + (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_MARK \ + Setting \ + */ +#define MXC_V_UART_CTRL_PARITY_SPACE \ ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ -#define MXC_S_UART_CTRL_PARITY_SPACE \ - (MXC_V_UART_CTRL_PARITY_SPACE \ - << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ +#define MXC_S_UART_CTRL_PARITY_SPACE \ + (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_SPACE \ + Setting \ + */ #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ -#define MXC_F_UART_CTRL_PARMD \ - ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \ +#define MXC_F_UART_CTRL_PARMD \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask \ */ #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */ #define MXC_S_UART_CTRL_PARMD_1 \ - (MXC_V_UART_CTRL_PARMD_1 \ - << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */ + (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< \ + CTRL_PARMD_1 \ + Setting */ #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */ #define MXC_S_UART_CTRL_PARMD_0 \ - (MXC_V_UART_CTRL_PARMD_0 \ - << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */ + (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< \ + CTRL_PARMD_0 \ + Setting */ #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ #define MXC_F_UART_CTRL_TX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH \ + Mask */ #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ #define MXC_F_UART_CTRL_RX_FLUSH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH \ + Mask */ #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ -#define MXC_F_UART_CTRL_BITACC \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ -#define MXC_V_UART_CTRL_BITACC_FRAME \ +#define MXC_F_UART_CTRL_BITACC \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC \ + Mask */ +#define MXC_V_UART_CTRL_BITACC_FRAME \ ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ -#define MXC_S_UART_CTRL_BITACC_FRAME \ - (MXC_V_UART_CTRL_BITACC_FRAME \ - << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */ -#define MXC_V_UART_CTRL_BITACC_BIT \ +#define MXC_S_UART_CTRL_BITACC_FRAME \ + (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< \ + CTRL_BITACC_FRAME \ + Setting \ + */ +#define MXC_V_UART_CTRL_BITACC_BIT \ ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ -#define MXC_S_UART_CTRL_BITACC_BIT \ - (MXC_V_UART_CTRL_BITACC_BIT \ - << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */ +#define MXC_S_UART_CTRL_BITACC_BIT \ + (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< \ + CTRL_BITACC_BIT \ + Setting \ + */ #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ #define MXC_F_UART_CTRL_CHAR_SIZE \ - ((uint32_t)( \ - 0x3UL \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ -#define MXC_V_UART_CTRL_CHAR_SIZE_5 \ + ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< \ + CTRL_CHAR_SIZE \ + Mask */ +#define MXC_V_UART_CTRL_CHAR_SIZE_5 \ ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_5 \ - (MXC_V_UART_CTRL_CHAR_SIZE_5 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_6 \ +#define MXC_S_UART_CTRL_CHAR_SIZE_5 \ + (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_5 \ + Setting \ + */ +#define MXC_V_UART_CTRL_CHAR_SIZE_6 \ ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_6 \ - (MXC_V_UART_CTRL_CHAR_SIZE_6 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_7 \ +#define MXC_S_UART_CTRL_CHAR_SIZE_6 \ + (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_6 \ + Setting \ + */ +#define MXC_V_UART_CTRL_CHAR_SIZE_7 \ ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_7 \ - (MXC_V_UART_CTRL_CHAR_SIZE_7 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ -#define MXC_V_UART_CTRL_CHAR_SIZE_8 \ +#define MXC_S_UART_CTRL_CHAR_SIZE_7 \ + (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_7 \ + Setting \ + */ +#define MXC_V_UART_CTRL_CHAR_SIZE_8 \ ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_8 \ - (MXC_V_UART_CTRL_CHAR_SIZE_8 \ - << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ +#define MXC_S_UART_CTRL_CHAR_SIZE_8 \ + (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_8 \ + Setting \ + */ #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ #define MXC_F_UART_CTRL_STOPBITS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ -#define MXC_V_UART_CTRL_STOPBITS_1 \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS \ + Mask */ +#define MXC_V_UART_CTRL_STOPBITS_1 \ ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1 \ - (MXC_V_UART_CTRL_STOPBITS_1 \ - << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */ -#define MXC_V_UART_CTRL_STOPBITS_1_5 \ +#define MXC_S_UART_CTRL_STOPBITS_1 \ + (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ + CTRL_STOPBITS_1 \ + Setting \ + */ +#define MXC_V_UART_CTRL_STOPBITS_1_5 \ ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1_5 \ - (MXC_V_UART_CTRL_STOPBITS_1_5 \ - << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */ +#define MXC_S_UART_CTRL_STOPBITS_1_5 \ + (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ + CTRL_STOPBITS_1_5 \ + Setting \ + */ #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ #define MXC_F_UART_CTRL_FLOW_CTRL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ -#define MXC_V_UART_CTRL_FLOW_CTRL_EN \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< \ + CTRL_FLOW_CTRL \ + Mask */ +#define MXC_V_UART_CTRL_FLOW_CTRL_EN \ ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_EN \ - (MXC_V_UART_CTRL_FLOW_CTRL_EN \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */ -#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \ +#define MXC_S_UART_CTRL_FLOW_CTRL_EN \ + (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ + CTRL_FLOW_CTRL_EN \ + Setting \ + */ +#define MXC_V_UART_CTRL_FLOW_CTRL_DIS \ ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \ - (MXC_V_UART_CTRL_FLOW_CTRL_DIS \ - << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */ +#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \ + (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ + CTRL_FLOW_CTRL_DIS \ + Setting \ + */ #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ #define MXC_F_UART_CTRL_FLOW_POL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ -#define MXC_V_UART_CTRL_FLOW_POL_0 \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL \ + Mask */ +#define MXC_V_UART_CTRL_FLOW_POL_0 \ ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_0 \ - (MXC_V_UART_CTRL_FLOW_POL_0 \ - << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */ -#define MXC_V_UART_CTRL_FLOW_POL_1 \ +#define MXC_S_UART_CTRL_FLOW_POL_0 \ + (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ + CTRL_FLOW_POL_0 \ + Setting \ + */ +#define MXC_V_UART_CTRL_FLOW_POL_1 \ ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_1 \ - (MXC_V_UART_CTRL_FLOW_POL_1 \ - << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */ +#define MXC_S_UART_CTRL_FLOW_POL_1 \ + (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ + CTRL_FLOW_POL_1 \ + Setting \ + */ #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ -#define MXC_F_UART_CTRL_NULL_MODEM \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \ - Mask */ -#define MXC_V_UART_CTRL_NULL_MODEM_DIS \ +#define MXC_F_UART_CTRL_NULL_MODEM \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM \ + Mask */ +#define MXC_V_UART_CTRL_NULL_MODEM_DIS \ ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */ -#define MXC_S_UART_CTRL_NULL_MODEM_DIS \ - (MXC_V_UART_CTRL_NULL_MODEM_DIS \ - << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \ +#define MXC_S_UART_CTRL_NULL_MODEM_DIS \ + (MXC_V_UART_CTRL_NULL_MODEM_DIS \ + << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting \ */ -#define MXC_V_UART_CTRL_NULL_MODEM_EN \ +#define MXC_V_UART_CTRL_NULL_MODEM_EN \ ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */ -#define MXC_S_UART_CTRL_NULL_MODEM_EN \ - (MXC_V_UART_CTRL_NULL_MODEM_EN \ +#define MXC_S_UART_CTRL_NULL_MODEM_EN \ + (MXC_V_UART_CTRL_NULL_MODEM_EN \ << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */ #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ -#define MXC_F_UART_CTRL_BREAK \ - ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \ +#define MXC_F_UART_CTRL_BREAK \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask \ */ -#define MXC_V_UART_CTRL_BREAK_DIS \ - ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \ +#define MXC_V_UART_CTRL_BREAK_DIS \ + ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \ */ -#define MXC_S_UART_CTRL_BREAK_DIS \ - (MXC_V_UART_CTRL_BREAK_DIS \ - << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */ +#define MXC_S_UART_CTRL_BREAK_DIS \ + (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< \ + CTRL_BREAK_DIS \ + Setting */ #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ -#define MXC_S_UART_CTRL_BREAK_EN \ - (MXC_V_UART_CTRL_BREAK_EN \ - << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */ +#define MXC_S_UART_CTRL_BREAK_EN \ + (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< \ + CTRL_BREAK_EN \ + Setting */ #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ -#define MXC_F_UART_CTRL_CLKSEL \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ -#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \ +#define MXC_F_UART_CTRL_CLKSEL \ + ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL \ + Mask */ +#define MXC_V_UART_CTRL_CLKSEL_SYSTEM \ ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ -#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \ - (MXC_V_UART_CTRL_CLKSEL_SYSTEM \ - << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */ -#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ +#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \ + (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ + CTRL_CLKSEL_SYSTEM \ + Setting \ + */ +#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ -#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \ - (MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ - << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */ +#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \ + (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ + CTRL_CLKSEL_ALTERNATE \ + Setting \ + */ #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ #define MXC_F_UART_CTRL_RX_TO \ - ((uint32_t)( \ - 0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ + ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask \ + */ /** * Threshold Control register. */ -#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \ +#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS \ 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_RX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< \ + THRESH_CTRL_RX_FIFO_THRESH \ + Mask */ -#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \ +#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS \ 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_TX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< \ + THRESH_CTRL_TX_FIFO_THRESH \ + Mask */ -#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \ +#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS \ 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ -#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< \ - THRESH_CTRL_RTS_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< \ + THRESH_CTRL_RTS_FIFO_THRESH \ + Mask */ /** * Status Register. */ #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ #define MXC_F_UART_STATUS_TX_BUSY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< \ + STATUS_TX_BUSY \ + Mask */ #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ #define MXC_F_UART_STATUS_RX_BUSY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< \ + STATUS_RX_BUSY \ + Mask */ #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ #define MXC_F_UART_STATUS_PARITY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY \ + Mask */ #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ -#define MXC_F_UART_STATUS_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ +#define MXC_F_UART_STATUS_BREAK \ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK \ + Mask */ #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ -#define MXC_F_UART_STATUS_RX_EMPTY \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \ - Mask */ +#define MXC_F_UART_STATUS_RX_EMPTY \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY \ + Mask */ #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ #define MXC_F_UART_STATUS_RX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< \ + STATUS_RX_FULL \ + Mask */ #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ -#define MXC_F_UART_STATUS_TX_EMPTY \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \ - Mask */ +#define MXC_F_UART_STATUS_TX_EMPTY \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY \ + Mask */ #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ #define MXC_F_UART_STATUS_TX_FULL \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< \ + STATUS_TX_FULL \ + Mask */ -#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS \ - 8 /**< STATUS_RX_FIFO_CNT Position \ +#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS \ + 8 /**< STATUS_RX_FIFO_CNT Position \ */ -#define MXC_F_UART_STATUS_RX_FIFO_CNT \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT \ - Mask */ - -#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS \ - 16 /**< STATUS_TX_FIFO_CNT Position \ +#define MXC_F_UART_STATUS_RX_FIFO_CNT \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< \ + STATUS_RX_FIFO_CNT \ + Mask */ + +#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS \ + 16 /**< STATUS_TX_FIFO_CNT Position \ */ -#define MXC_F_UART_STATUS_TX_FIFO_CNT \ - ((uint32_t)( \ - 0x3FUL \ - << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT \ - Mask */ +#define MXC_F_UART_STATUS_TX_FIFO_CNT \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< \ + STATUS_TX_FIFO_CNT \ + Mask */ #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */ -#define MXC_F_UART_STATUS_RX_TO \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */ +#define MXC_F_UART_STATUS_RX_TO \ + ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO \ + Mask */ /** * Interrupt Enable Register. */ -#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \ +#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS \ 0 /**< INT_EN_RX_FRAME_ERROR Position */ -#define MXC_F_UART_INT_EN_RX_FRAME_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< \ - INT_EN_RX_FRAME_ERROR \ - Mask */ +#define MXC_F_UART_INT_EN_RX_FRAME_ERROR \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< \ + INT_EN_RX_FRAME_ERROR \ + Mask */ -#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \ +#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS \ 1 /**< INT_EN_RX_PARITY_ERROR Position */ -#define MXC_F_UART_INT_EN_RX_PARITY_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< \ - INT_EN_RX_PARITY_ERROR \ - Mask */ +#define MXC_F_UART_INT_EN_RX_PARITY_ERROR \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< \ + INT_EN_RX_PARITY_ERROR \ + Mask */ #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ #define MXC_F_UART_INT_EN_CTS_CHANGE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< \ + INT_EN_CTS_CHANGE \ + Mask */ #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ #define MXC_F_UART_INT_EN_RX_OVERRUN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< \ + INT_EN_RX_OVERRUN \ + Mask */ -#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \ +#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS \ 4 /**< INT_EN_RX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_EN_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< \ - INT_EN_RX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_INT_EN_RX_FIFO_THRESH \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< \ + INT_EN_RX_FIFO_THRESH \ + Mask */ -#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \ +#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS \ 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ -#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ - INT_EN_TX_FIFO_ALMOST_EMPTY \ - Mask */ - -#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \ +#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ + INT_EN_TX_FIFO_ALMOST_EMPTY \ + Mask */ + +#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS \ 6 /**< INT_EN_TX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_EN_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< \ - INT_EN_TX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_INT_EN_TX_FIFO_THRESH \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< \ + INT_EN_TX_FIFO_THRESH \ + Mask */ #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ -#define MXC_F_UART_INT_EN_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ +#define MXC_F_UART_INT_EN_BREAK \ + ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK \ + Mask */ #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ #define MXC_F_UART_INT_EN_RX_TIMEOUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< \ + INT_EN_RX_TIMEOUT \ + Mask */ #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ #define MXC_F_UART_INT_EN_LAST_BREAK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< \ + INT_EN_LAST_BREAK \ + Mask */ /** * Interrupt Status Flags. */ -#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \ +#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS \ 0 /**< INT_FL_RX_FRAME_ERROR Position */ -#define MXC_F_UART_INT_FL_RX_FRAME_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< \ - INT_FL_RX_FRAME_ERROR \ - Mask */ +#define MXC_F_UART_INT_FL_RX_FRAME_ERROR \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< \ + INT_FL_RX_FRAME_ERROR \ + Mask */ -#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \ +#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS \ 1 /**< INT_FL_RX_PARITY_ERROR Position */ -#define MXC_F_UART_INT_FL_RX_PARITY_ERROR \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< \ - INT_FL_RX_PARITY_ERROR \ - Mask */ +#define MXC_F_UART_INT_FL_RX_PARITY_ERROR \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< \ + INT_FL_RX_PARITY_ERROR \ + Mask */ #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ #define MXC_F_UART_INT_FL_CTS_CHANGE \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< \ + INT_FL_CTS_CHANGE \ + Mask */ #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ #define MXC_F_UART_INT_FL_RX_OVERRUN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< \ + INT_FL_RX_OVERRUN \ + Mask */ -#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \ +#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS \ 4 /**< INT_FL_RX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_FL_RX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< \ - INT_FL_RX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_INT_FL_RX_FIFO_THRESH \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< \ + INT_FL_RX_FIFO_THRESH \ + Mask */ -#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \ +#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS \ 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ -#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ - INT_FL_TX_FIFO_ALMOST_EMPTY \ - Mask */ - -#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \ +#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< \ + INT_FL_TX_FIFO_ALMOST_EMPTY \ + Mask */ + +#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS \ 6 /**< INT_FL_TX_FIFO_THRESH Position */ -#define MXC_F_UART_INT_FL_TX_FIFO_THRESH \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< \ - INT_FL_TX_FIFO_THRESH \ - Mask */ +#define MXC_F_UART_INT_FL_TX_FIFO_THRESH \ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< \ + INT_FL_TX_FIFO_THRESH \ + Mask */ #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ -#define MXC_F_UART_INT_FL_BREAK \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ +#define MXC_F_UART_INT_FL_BREAK \ + ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK \ + Mask */ #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ #define MXC_F_UART_INT_FL_RX_TIMEOUT \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< \ + INT_FL_RX_TIMEOUT \ + Mask */ #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ #define MXC_F_UART_INT_FL_LAST_BREAK \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK \ - Mask */ + ((uint32_t)(0x1UL \ + << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< \ + INT_FL_LAST_BREAK \ + Mask */ /** * Baud rate register. Integer portion. */ #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ -#define MXC_F_UART_BAUD0_IBAUD \ - ((uint32_t)(0xFFFUL \ - << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ +#define MXC_F_UART_BAUD0_IBAUD \ + ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD \ + Mask */ #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ -#define MXC_F_UART_BAUD0_FACTOR \ - ((uint32_t)(0x3UL \ - << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ -#define MXC_V_UART_BAUD0_FACTOR_128 \ +#define MXC_F_UART_BAUD0_FACTOR \ + ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR \ + Mask */ +#define MXC_V_UART_BAUD0_FACTOR_128 \ ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ -#define MXC_S_UART_BAUD0_FACTOR_128 \ - (MXC_V_UART_BAUD0_FACTOR_128 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_64 \ +#define MXC_S_UART_BAUD0_FACTOR_128 \ + (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_128 \ + Setting \ + */ +#define MXC_V_UART_BAUD0_FACTOR_64 \ ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ -#define MXC_S_UART_BAUD0_FACTOR_64 \ - (MXC_V_UART_BAUD0_FACTOR_64 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_32 \ +#define MXC_S_UART_BAUD0_FACTOR_64 \ + (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_64 \ + Setting \ + */ +#define MXC_V_UART_BAUD0_FACTOR_32 \ ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ -#define MXC_S_UART_BAUD0_FACTOR_32 \ - (MXC_V_UART_BAUD0_FACTOR_32 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ -#define MXC_V_UART_BAUD0_FACTOR_16 \ +#define MXC_S_UART_BAUD0_FACTOR_32 \ + (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_32 \ + Setting \ + */ +#define MXC_V_UART_BAUD0_FACTOR_16 \ ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ -#define MXC_S_UART_BAUD0_FACTOR_16 \ - (MXC_V_UART_BAUD0_FACTOR_16 \ - << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ +#define MXC_S_UART_BAUD0_FACTOR_16 \ + (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_16 \ + Setting \ + */ /** * Baud rate register. Decimal Setting. */ #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ -#define MXC_F_UART_BAUD1_DBAUD \ - ((uint32_t)(0xFFFUL \ - << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ +#define MXC_F_UART_BAUD1_DBAUD \ + ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD \ + Mask */ /** * FIFO Data buffer. */ #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ -#define MXC_F_UART_FIFO_FIFO \ - ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \ +#define MXC_F_UART_FIFO_FIFO \ + ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask \ */ - /** * DMA Configuration. */ #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */ -#define MXC_F_UART_DMA_TDMA_EN \ - ((uint32_t)( \ - 0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */ -#define MXC_V_UART_DMA_TDMA_EN_DIS \ +#define MXC_F_UART_DMA_TDMA_EN \ + ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN \ + Mask */ +#define MXC_V_UART_DMA_TDMA_EN_DIS \ ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_TDMA_EN_DIS \ - (MXC_V_UART_DMA_TDMA_EN_DIS \ - << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */ -#define MXC_V_UART_DMA_TDMA_EN_EN \ - ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \ +#define MXC_S_UART_DMA_TDMA_EN_DIS \ + (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ + DMA_TDMA_EN_DIS \ + Setting \ + */ +#define MXC_V_UART_DMA_TDMA_EN_EN \ + ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \ */ -#define MXC_S_UART_DMA_TDMA_EN_EN \ - (MXC_V_UART_DMA_TDMA_EN_EN \ - << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */ +#define MXC_S_UART_DMA_TDMA_EN_EN \ + (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ + DMA_TDMA_EN_EN \ + Setting \ + */ #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ -#define MXC_F_UART_DMA_RXDMA_EN \ - ((uint32_t)(0x1UL \ - << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ -#define MXC_V_UART_DMA_RXDMA_EN_DIS \ +#define MXC_F_UART_DMA_RXDMA_EN \ + ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN \ + Mask */ +#define MXC_V_UART_DMA_RXDMA_EN_DIS \ ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_RXDMA_EN_DIS \ - (MXC_V_UART_DMA_RXDMA_EN_DIS \ - << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ -#define MXC_V_UART_DMA_RXDMA_EN_EN \ +#define MXC_S_UART_DMA_RXDMA_EN_DIS \ + (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ + DMA_RXDMA_EN_DIS \ + Setting \ + */ +#define MXC_V_UART_DMA_RXDMA_EN_EN \ ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ -#define MXC_S_UART_DMA_RXDMA_EN_EN \ - (MXC_V_UART_DMA_RXDMA_EN_EN \ - << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ +#define MXC_S_UART_DMA_RXDMA_EN_EN \ + (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ + DMA_RXDMA_EN_EN \ + Setting \ + */ #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ -#define MXC_F_UART_DMA_TXDMA_LEVEL \ - ((uint32_t)(0x3FUL \ - << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \ +#define MXC_F_UART_DMA_TXDMA_LEVEL \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL \ Mask */ #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ -#define MXC_F_UART_DMA_RXDMA_LEVEL \ - ((uint32_t)(0x3FUL \ - << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \ +#define MXC_F_UART_DMA_RXDMA_LEVEL \ + ((uint32_t)(0x3FUL \ + << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL \ Mask */ /** * Transmit FIFO Status register. */ #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ -#define MXC_F_UART_TX_FIFO_DATA \ - ((uint32_t)(0x7FUL \ - << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ +#define MXC_F_UART_TX_FIFO_DATA \ + ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA \ + Mask */ #endif /* _UART_REGS_H_ */ -- cgit v1.2.1 From 2ba95c7d89a8d1d6d2f44e9f1186510d95716be8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:33 -0600 Subject: driver/tcpm/stub.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia905c799e66a238ced3ad1304a8e65b981a0aa73 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730100 Reviewed-by: Jeremy Bettis --- driver/tcpm/stub.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/driver/tcpm/stub.c b/driver/tcpm/stub.c index 863a88c044..2b98cc826a 100644 --- a/driver/tcpm/stub.c +++ b/driver/tcpm/stub.c @@ -22,8 +22,8 @@ static int init_alert_mask(int port) * signal the TCPM via the Alert# gpio line. */ mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED | - TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | - TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS; + TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | + TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS; /* Set the alert mask in TCPC */ rv = tcpc_alert_mask_set(port, mask); @@ -48,7 +48,7 @@ int tcpm_init(int port) } int tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { return tcpc_get_cc(port, cc1, cc2); } @@ -153,7 +153,7 @@ void tcpc_alert(int port) if (status & TCPC_REG_ALERT_TX_COMPLETE) { /* transmit complete */ pd_transmit_complete(port, status & TCPC_REG_ALERT_TX_SUCCESS ? - TCPC_TX_COMPLETE_SUCCESS : - TCPC_TX_COMPLETE_FAILED); + TCPC_TX_COMPLETE_SUCCESS : + TCPC_TX_COMPLETE_FAILED); } } -- cgit v1.2.1 From b049be6b8e41b845561d1a4d348ad09ac902f4fd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:15 -0600 Subject: common/usbc/usb_pe_ctvpd_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7df124057348949a232e4712702b1f749eb64c2d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729789 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pe_ctvpd_sm.c | 55 +++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/common/usbc/usb_pe_ctvpd_sm.c b/common/usbc/usb_pe_ctvpd_sm.c index 346a57a461..35e1af0fea 100644 --- a/common/usbc/usb_pe_ctvpd_sm.c +++ b/common/usbc/usb_pe_ctvpd_sm.c @@ -167,55 +167,48 @@ static void pe_request_run(const int port) /* Prepare to send ACK */ /* VDM Header */ - payload[0] = VDO( - USB_VID_GOOGLE, - 1, /* Structured VDM */ - VDO_SVDM_VERS(1) | - VDO_CMDT(CMDT_RSP_ACK) | - CMD_DISCOVER_IDENT); + payload[0] = VDO(USB_VID_GOOGLE, 1, /* Structured VDM */ + VDO_SVDM_VERS(1) | VDO_CMDT(CMDT_RSP_ACK) | + CMD_DISCOVER_IDENT); /* ID Header VDO */ - payload[1] = VDO_IDH( - 0, /* Not a USB Host */ - 1, /* Capable of being enumerated as USB Device */ - IDH_PTYPE_VPD, - 0, /* Modal Operation Not Supported */ - USB_VID_GOOGLE); + payload[1] = VDO_IDH(0, /* Not a USB Host */ + 1, /* Capable of being enumerated as USB + Device */ + IDH_PTYPE_VPD, 0, /* Modal Operation Not + Supported */ + USB_VID_GOOGLE); /* Cert State VDO */ payload[2] = 0; /* Product VDO */ - payload[3] = VDO_PRODUCT( - CONFIG_USB_PID, - USB_BCD_DEVICE); + payload[3] = VDO_PRODUCT(CONFIG_USB_PID, USB_BCD_DEVICE); /* VPD VDO */ payload[4] = VDO_VPD( - VPD_HW_VERSION, - VPD_FW_VERSION, - VPD_MAX_VBUS_20V, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_VBUS_IMP( - VPD_VBUS_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_GND_IMP( - VPD_GND_IMPEDANCE) - : 0, - IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED - : VPD_CTS_NOT_SUPPORTED); + VPD_HW_VERSION, VPD_FW_VERSION, VPD_MAX_VBUS_20V, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CT_CURRENT : 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? + VPD_VBUS_IMP(VPD_VBUS_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? + VPD_GND_IMP(VPD_GND_IMPEDANCE) : + 0, + IS_ENABLED(CONFIG_USB_CTVPD) ? VPD_CTS_SUPPORTED : + VPD_CTS_NOT_SUPPORTED); /* 20 bytes, 5 data objects */ tx_emsg[port].len = 20; /* Set to highest revision supported by both ports. */ prl_set_rev(port, TCPCI_MSG_SOP_PRIME, - (PD_HEADER_REV(header) > PD_REV30) ? - PD_REV30 : PD_HEADER_REV(header)); + (PD_HEADER_REV(header) > PD_REV30) ? + PD_REV30 : + PD_HEADER_REV(header)); /* Send the ACK */ prl_send_data_msg(port, TCPCI_MSG_SOP_PRIME, - PD_DATA_VENDOR_DEF); + PD_DATA_VENDOR_DEF); } } -- cgit v1.2.1 From a117c96d0d191ed1081e0f0a1301ce96e8bacf16 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:36 -0600 Subject: chip/mchp/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3901ac496db8c5258d496c1e6061c62e715edce4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729243 Reviewed-by: Jeremy Bettis --- chip/mchp/hwtimer.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c index 05ff69e7d9..8e6b3f1dda 100644 --- a/chip/mchp/hwtimer.c +++ b/chip/mchp/hwtimer.c @@ -16,8 +16,7 @@ void __hw_clock_event_set(uint32_t deadline) { - MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - - (0xffffffff - deadline); + MCHP_TMR32_CNT(1) = MCHP_TMR32_CNT(0) - (0xffffffff - deadline); MCHP_TMR32_CTL(1) |= BIT(5); } @@ -49,16 +48,21 @@ void __hw_clock_source_set(uint32_t ts) static void __hw_clock_source_irq(int timer_id) { MCHP_TMR32_STS(timer_id & 0x01) |= 1; - MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = - MCHP_TMR32_GIRQ_BIT(timer_id & 0x01); + MCHP_INT_SOURCE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(timer_id & 0x01); /* If IRQ is from timer 0, 32-bit timer overflowed */ process_timers(timer_id == 0); } -static void __hw_clock_source_irq_0(void) { __hw_clock_source_irq(0); } +static void __hw_clock_source_irq_0(void) +{ + __hw_clock_source_irq(0); +} DECLARE_IRQ(MCHP_IRQ_TIMER32_0, __hw_clock_source_irq_0, 1); -static void __hw_clock_source_irq_1(void) { __hw_clock_source_irq(1); } +static void __hw_clock_source_irq_1(void) +{ + __hw_clock_source_irq(1); +} DECLARE_IRQ(MCHP_IRQ_TIMER32_1, __hw_clock_source_irq_1, 1); static void configure_timer(int timer_id) @@ -88,7 +92,7 @@ static void configure_timer(int timer_id) int __hw_clock_source_init(uint32_t start_t) { MCHP_PCR_SLP_DIS_DEV_MASK(3, MCHP_PCR_SLP_EN3_BTMR32_0 + - MCHP_PCR_SLP_EN3_BTMR32_1); + MCHP_PCR_SLP_EN3_BTMR32_1); /* * The timer can only fire interrupt when its value reaches zero. @@ -111,8 +115,8 @@ int __hw_clock_source_init(uint32_t start_t) /* Enable interrupt */ task_enable_irq(MCHP_IRQ_TIMER32_0); task_enable_irq(MCHP_IRQ_TIMER32_1); - MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = MCHP_TMR32_GIRQ_BIT(0) + - MCHP_TMR32_GIRQ_BIT(1); + MCHP_INT_ENABLE(MCHP_TMR32_GIRQ) = + MCHP_TMR32_GIRQ_BIT(0) + MCHP_TMR32_GIRQ_BIT(1); /* * Not needed when using direct mode interrupts * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ); -- cgit v1.2.1 From c23b9ee2a76efa1417b8031f4132cc31810a4149 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:27 -0600 Subject: zephyr/shim/src/mkbp_event.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib76451c96a5d4a85a3839ef5ac605a514bfd3f61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727425 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/mkbp_event.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/src/mkbp_event.c b/zephyr/shim/src/mkbp_event.c index 39bcb001b8..0785e93706 100644 --- a/zephyr/shim/src/mkbp_event.c +++ b/zephyr/shim/src/mkbp_event.c @@ -7,7 +7,8 @@ const struct mkbp_event_source *zephyr_find_mkbp_event_source(uint8_t type) { - STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc) { + STRUCT_SECTION_FOREACH(mkbp_event_source, evtsrc) + { if (evtsrc->event_type == type) return evtsrc; } -- cgit v1.2.1 From 88a9602ccb4d083170bffd788398d75f50f955be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:21 -0600 Subject: board/coffeecake/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0d9b58a5e7e9670e4f661a992d40a0d99b28c5f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728152 Reviewed-by: Jeremy Bettis --- board/coffeecake/usb_pd_policy.c | 57 +++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 33 deletions(-) diff --git a/board/coffeecake/usb_pd_policy.c b/board/coffeecake/usb_pd_policy.c index c8c74688a8..aac1c9c45e 100644 --- a/board/coffeecake/usb_pd_policy.c +++ b/board/coffeecake/usb_pd_policy.c @@ -22,8 +22,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Holds valid object position (opos) for entered mode */ static int alt_mode[PD_AMODE_COUNT]; @@ -97,31 +97,24 @@ int pd_check_power_swap(int port) return 0; } -int pd_check_data_swap(int port, - enum pd_data_role data_role) +int pd_check_data_swap(int port, enum pd_data_role data_role) { /* We can swap to UFP */ return data_role == PD_ROLE_DFP; } -void pd_execute_data_swap(int port, - enum pd_data_role data_role) +void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* TODO: turn on pp5000, pp3300 */ } -void pd_check_pr_role(int port, - enum pd_power_role pr_role, - int flags) +void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { if (pr_role == PD_ROLE_SINK && !gpio_get_level(GPIO_AC_PRESENT_L)) pd_request_power_swap(port); - } -void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_DFP) pd_request_data_swap(port); @@ -136,8 +129,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 1, /* Vbus power required */ @@ -163,18 +156,16 @@ static int svdm_response_svids(int port, uint32_t *payload) #define OPOS_DP 1 #define OPOS_GFU 1 -const uint32_t vdo_dp_modes[1] = { - VDO_MODE_DP(0, /* UFP pin cfg supported : none */ +const uint32_t vdo_dp_modes[1] = { + VDO_MODE_DP(0, /* UFP pin cfg supported : none */ MODE_DP_PIN_C, /* DFP pin cfg supported */ - 1, /* no usb2.0 signalling in AMode */ - CABLE_PLUG, /* its a plug */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + 1, /* no usb2.0 signalling in AMode */ + CABLE_PLUG, /* its a plug */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; -const uint32_t vdo_goog_modes[1] = { - VDO_MODE_GOOGLE(MODE_GOOGLE_FU) -}; +const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) }; static int svdm_response_modes(int port, uint32_t *payload) { @@ -196,13 +187,14 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS_DP) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), - 0, /* power low */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power + low + */ 0x2); return 2; } @@ -281,8 +273,7 @@ const struct svdm_response svdm_rsp = { .exit_mode = &svdm_exit_mode, }; -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) +int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload) { int rsize; -- cgit v1.2.1 From 9bccd1036d86a8d762945773bc17c4650ecacc06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:15:17 -0600 Subject: include/queue.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7665f8c142e1f1d4fa4f2618c3e575f1bada0f61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730394 Reviewed-by: Jeremy Bettis --- include/queue.h | 91 +++++++++++++++++++++++++-------------------------------- 1 file changed, 39 insertions(+), 52 deletions(-) diff --git a/include/queue.h b/include/queue.h index 6cf72563cb..0645046f93 100644 --- a/include/queue.h +++ b/include/queue.h @@ -75,9 +75,9 @@ struct queue { struct queue_policy const *policy; - size_t buffer_units; /* size of buffer (in units) */ - size_t buffer_units_mask; /* size of buffer (in units) - 1*/ - size_t unit_bytes; /* size of unit (in byte) */ + size_t buffer_units; /* size of buffer (in units) */ + size_t buffer_units_mask; /* size of buffer (in units) - 1*/ + size_t unit_bytes; /* size of unit (in byte) */ uint8_t *buffer; }; @@ -86,14 +86,14 @@ struct queue { * and state structure. This macro creates a compound literal that can be used * to statically initialize a queue. */ -#define QUEUE(SIZE, TYPE, POLICY) \ - ((struct queue) { \ - .state = &((struct queue_state){}), \ - .policy = &POLICY, \ +#define QUEUE(SIZE, TYPE, POLICY) \ + ((struct queue){ \ + .state = &((struct queue_state){}), \ + .policy = &POLICY, \ .buffer_units = BUILD_CHECK_INLINE(SIZE, POWER_OF_TWO(SIZE)), \ - .buffer_units_mask = SIZE - 1, \ - .unit_bytes = sizeof(TYPE), \ - .buffer = (uint8_t *) &((TYPE[SIZE]){}), \ + .buffer_units_mask = SIZE - 1, \ + .unit_bytes = sizeof(TYPE), \ + .buffer = (uint8_t *)&((TYPE[SIZE]){}), \ }) /* Initialize the queue to empty state. */ @@ -143,7 +143,7 @@ void queue_next(struct queue const *q, struct queue_iterator *it); * buffer units. */ struct queue_chunk { - size_t count; + size_t count; void *buffer; }; @@ -206,12 +206,8 @@ size_t queue_add_unit(struct queue const *q, const void *src); size_t queue_add_units(struct queue const *q, const void *src, size_t count); /* Add multiple units to queue using supplied memcpy. */ -size_t queue_add_memcpy(struct queue const *q, - const void *src, - size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)); +size_t queue_add_memcpy(struct queue const *q, const void *src, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* Remove one unit from the begin of the queue. */ size_t queue_remove_unit(struct queue const *q, void *dest); @@ -220,27 +216,18 @@ size_t queue_remove_unit(struct queue const *q, void *dest); size_t queue_remove_units(struct queue const *q, void *dest, size_t count); /* Remove multiple units from the begin of the queue using supplied memcpy. */ -size_t queue_remove_memcpy(struct queue const *q, - void *dest, - size_t count, - void *(*memcpy)(void *dest, - const void *src, +size_t queue_remove_memcpy(struct queue const *q, void *dest, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* Peek (return but don't remove) the count elements starting with the i'th. */ -size_t queue_peek_units(struct queue const *q, - void *dest, - size_t i, +size_t queue_peek_units(struct queue const *q, void *dest, size_t i, size_t count); /* Peek (return but don't remove) the count elements starting with the i'th. */ -size_t queue_peek_memcpy(struct queue const *q, - void *dest, - size_t i, - size_t count, - void *(*memcpy)(void *dest, - const void *src, - size_t n)); +size_t +queue_peek_memcpy(struct queue const *q, void *dest, size_t i, size_t count, + void *(*memcpy)(void *dest, const void *src, size_t n)); /* * These macros will statically select the queue functions based on the number @@ -248,28 +235,28 @@ size_t queue_peek_memcpy(struct queue const *q, * and remove functions are much faster than calling the equivalent generic * version with a count of one. */ -#define QUEUE_ADD_UNITS(q, src, count) \ - ({ \ - size_t result; \ - \ - if (count == 1) \ - result = queue_add_unit(q, src); \ - else \ - result = queue_add_units(q, src, count); \ - \ - result; \ +#define QUEUE_ADD_UNITS(q, src, count) \ + ({ \ + size_t result; \ + \ + if (count == 1) \ + result = queue_add_unit(q, src); \ + else \ + result = queue_add_units(q, src, count); \ + \ + result; \ }) -#define QUEUE_REMOVE_UNITS(q, dest, count) \ - ({ \ - size_t result; \ - \ - if (count == 1) \ - result = queue_remove_unit(q, dest); \ - else \ - result = queue_remove_units(q, dest, count); \ - \ - result; \ +#define QUEUE_REMOVE_UNITS(q, dest, count) \ + ({ \ + size_t result; \ + \ + if (count == 1) \ + result = queue_remove_unit(q, dest); \ + else \ + result = queue_remove_units(q, dest, count); \ + \ + result; \ }) #endif /* __CROS_EC_QUEUE_H */ -- cgit v1.2.1 From 7a38ccf03f7ce36c74dbc1b622d30de84db1f726 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:07 -0600 Subject: common/usbc/usb_pd_dpm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb54411fa65cd26c4d8d2882434a1ea2a4f74128 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729786 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pd_dpm.c | 123 +++++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 63 deletions(-) diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 159331171e..389445d19c 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -33,8 +33,8 @@ #endif #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -55,16 +55,16 @@ static struct { #define DPM_CHK_FLAG(port, flag) (dpm[(port)].flags & (flag)) /* Flags for internal DPM state */ -#define DPM_FLAG_MODE_ENTRY_DONE BIT(0) -#define DPM_FLAG_EXIT_REQUEST BIT(1) -#define DPM_FLAG_ENTER_DP BIT(2) -#define DPM_FLAG_ENTER_TBT BIT(3) -#define DPM_FLAG_ENTER_USB4 BIT(4) -#define DPM_FLAG_ENTER_ANY (DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT \ - | DPM_FLAG_ENTER_USB4) -#define DPM_FLAG_SEND_ATTENTION BIT(5) +#define DPM_FLAG_MODE_ENTRY_DONE BIT(0) +#define DPM_FLAG_EXIT_REQUEST BIT(1) +#define DPM_FLAG_ENTER_DP BIT(2) +#define DPM_FLAG_ENTER_TBT BIT(3) +#define DPM_FLAG_ENTER_USB4 BIT(4) +#define DPM_FLAG_ENTER_ANY \ + (DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | DPM_FLAG_ENTER_USB4) +#define DPM_FLAG_SEND_ATTENTION BIT(5) #define DPM_FLAG_DATA_RESET_REQUESTED BIT(6) -#define DPM_FLAG_DATA_RESET_DONE BIT(7) +#define DPM_FLAG_DATA_RESET_DONE BIT(7) #ifdef CONFIG_ZEPHYR static int init_vdm_attention_mutex(const struct device *dev) @@ -120,9 +120,8 @@ enum ec_status pd_request_enter_mode(int port, enum typec_mode mode) return EC_RES_INVALID_PARAM; /* Only one enter request may be active at a time. */ - if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | - DPM_FLAG_ENTER_TBT | - DPM_FLAG_ENTER_USB4)) + if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | + DPM_FLAG_ENTER_USB4)) return EC_RES_BUSY; switch (mode) { @@ -158,14 +157,14 @@ void dpm_init(int port) void dpm_mode_exit_complete(int port) { DPM_CLR_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE | DPM_FLAG_EXIT_REQUEST | - DPM_FLAG_SEND_ATTENTION); + DPM_FLAG_SEND_ATTENTION); } static void dpm_set_mode_entry_done(int port) { DPM_SET_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE); DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | - DPM_FLAG_ENTER_USB4); + DPM_FLAG_ENTER_USB4); } void dpm_set_mode_exit_request(int port) @@ -210,7 +209,7 @@ static bool dpm_mode_entry_requested(int port, enum typec_mode mode) } void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { const uint16_t svid = PD_VDO_VID(vdm[0]); @@ -227,12 +226,12 @@ void dpm_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, } default: CPRINTS("C%d: Received unexpected VDM ACK for SVID %d", port, - svid); + svid); } } void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, - uint8_t vdm_cmd) + uint8_t vdm_cmd) { switch (svid) { case USB_SID_DISPLAYPORT: @@ -245,7 +244,7 @@ void dpm_vdm_naked(int port, enum tcpci_msg_type type, uint16_t svid, } default: CPRINTS("C%d: Received unexpected VDM NAK for SVID %d", port, - svid); + svid); } } @@ -261,16 +260,15 @@ static void dpm_attempt_mode_entry(int port) uint32_t vdm[VDO_MAX_SIZE]; enum tcpci_msg_type tx_type = TCPCI_MSG_SOP; bool enter_mode_requested = - IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? false : true; + IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? false : true; enum dpm_msg_setup_status status = MSG_SETUP_UNSUPPORTED; if (pd_get_data_role(port) != PD_ROLE_DFP) { - if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | - DPM_FLAG_ENTER_TBT | - DPM_FLAG_ENTER_USB4)) + if (DPM_CHK_FLAG(port, DPM_FLAG_ENTER_DP | DPM_FLAG_ENTER_TBT | + DPM_FLAG_ENTER_USB4)) DPM_CLR_FLAG(port, DPM_FLAG_ENTER_DP | - DPM_FLAG_ENTER_TBT | - DPM_FLAG_ENTER_USB4); + DPM_FLAG_ENTER_TBT | + DPM_FLAG_ENTER_USB4); /* * TODO(b/168030639): Notify the AP that the enter mode request * failed. @@ -298,9 +296,9 @@ static void dpm_attempt_mode_entry(int port) return; if (dp_entry_is_done(port) || - (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) && - tbt_entry_is_done(port)) || - (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) { + (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) && + tbt_entry_is_done(port)) || + (IS_ENABLED(CONFIG_USB_PD_USB4) && enter_usb_entry_is_done(port))) { dpm_set_mode_entry_done(port); return; } @@ -314,24 +312,23 @@ static void dpm_attempt_mode_entry(int port) return; if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) && - IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && - DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY) && - !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) && - !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) { + IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && + DPM_CHK_FLAG(port, DPM_FLAG_ENTER_ANY) && + !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) && + !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) { pd_dpm_request(port, DPM_REQUEST_DATA_RESET); DPM_SET_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED); return; } if (IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) && - IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && - !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) { + IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG) && + !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) { return; } /* Check if port, port partner and cable support USB4. */ - if (IS_ENABLED(CONFIG_USB_PD_USB4) && - board_is_tbt_usb4_port(port) && + if (IS_ENABLED(CONFIG_USB_PD_USB4) && board_is_tbt_usb4_port(port) && enter_usb_port_partner_is_capable(port) && enter_usb_cable_is_capable(port) && dpm_mode_entry_requested(port, TYPEC_MODE_USB4)) { @@ -351,14 +348,13 @@ static void dpm_attempt_mode_entry(int port) /* If not, check if they support Thunderbolt alt mode. */ if (IS_ENABLED(CONFIG_USB_PD_TBT_COMPAT_MODE) && - board_is_tbt_usb4_port(port) && - pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP, - USB_VID_INTEL) && - dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) { + board_is_tbt_usb4_port(port) && + pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP, + USB_VID_INTEL) && + dpm_mode_entry_requested(port, TYPEC_MODE_TBT)) { enter_mode_requested = true; vdo_count = ARRAY_SIZE(vdm); - status = tbt_setup_next_vdm(port, &vdo_count, vdm, - &tx_type); + status = tbt_setup_next_vdm(port, &vdo_count, vdm, &tx_type); } /* If not, check if they support DisplayPort alt mode. */ @@ -381,7 +377,7 @@ static void dpm_attempt_mode_entry(int port) * just mark setup done and get out of here. */ if (status != MSG_SETUP_SUCCESS && - !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) { + !DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) { if (enter_mode_requested) { /* * TODO(b/168030639): Notify the AP that mode entry @@ -427,9 +423,8 @@ static void dpm_attempt_mode_exit(int port) * is not supported, exit active modes individually. */ if (IS_ENABLED(CONFIG_USB_PD_DATA_RESET_MSG)) { - if (!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) - && !DPM_CHK_FLAG(port, - DPM_FLAG_DATA_RESET_DONE)) { + if (!DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED) && + !DPM_CHK_FLAG(port, DPM_FLAG_DATA_RESET_DONE)) { pd_dpm_request(port, DPM_REQUEST_DATA_RESET); DPM_SET_FLAG(port, DPM_FLAG_DATA_RESET_REQUESTED); return; @@ -523,7 +518,7 @@ void dpm_run(int port) * Note: request bitmasks should be accessed atomically as other ports may alter * them */ -static uint32_t max_current_claimed; +static uint32_t max_current_claimed; K_MUTEX_DEFINE(max_current_claimed_lock); /* Ports with PD sink needing > 1.5 A */ @@ -533,7 +528,7 @@ static atomic_t source_frs_max_requested; /* Ports with non-PD sinks, so current requirements are unknown */ static atomic_t non_pd_sink_max_requested; -#define LOWEST_PORT(p) __builtin_ctz(p) /* Undefined behavior if p == 0 */ +#define LOWEST_PORT(p) __builtin_ctz(p) /* Undefined behavior if p == 0 */ static int count_port_bits(uint32_t bitmask) { @@ -571,9 +566,9 @@ static void balance_source_ports(void) mutex_lock(&max_current_claimed_lock); /* Remove any ports which no longer require 3.0 A */ - removed_ports = max_current_claimed & ~(sink_max_pdo_requested | - source_frs_max_requested | - non_pd_sink_max_requested); + removed_ports = max_current_claimed & + ~(sink_max_pdo_requested | source_frs_max_requested | + non_pd_sink_max_requested); max_current_claimed &= ~removed_ports; /* Allocate 3.0 A to new PD sink ports that need it */ @@ -582,7 +577,7 @@ static void balance_source_ports(void) int new_max_port = LOWEST_PORT(new_ports); if (count_port_bits(max_current_claimed) < - CONFIG_USB_PD_3A_PORTS) { + CONFIG_USB_PD_3A_PORTS) { max_current_claimed |= BIT(new_max_port); typec_select_src_current_limit_rp(new_max_port, TYPEC_RP_3A0); @@ -590,7 +585,8 @@ static void balance_source_ports(void) /* Always downgrade non-PD ports first */ int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested & max_current_claimed); - typec_select_src_current_limit_rp(rem_non_pd, + typec_select_src_current_limit_rp( + rem_non_pd, typec_get_default_current_limit_rp(rem_non_pd)); max_current_claimed &= ~BIT(rem_non_pd); @@ -602,7 +598,7 @@ static void balance_source_ports(void) } else if (source_frs_max_requested & max_current_claimed) { /* Downgrade lowest FRS port from 3.0 A slot */ int rem_frs = LOWEST_PORT(source_frs_max_requested & - max_current_claimed); + max_current_claimed); pd_dpm_request(rem_frs, DPM_REQUEST_FRS_DET_DISABLE); max_current_claimed &= ~BIT(rem_frs); @@ -624,14 +620,15 @@ static void balance_source_ports(void) int new_frs_port = LOWEST_PORT(new_ports); if (count_port_bits(max_current_claimed) < - CONFIG_USB_PD_3A_PORTS) { + CONFIG_USB_PD_3A_PORTS) { max_current_claimed |= BIT(new_frs_port); pd_dpm_request(new_frs_port, DPM_REQUEST_FRS_DET_ENABLE); } else if (non_pd_sink_max_requested & max_current_claimed) { int rem_non_pd = LOWEST_PORT(non_pd_sink_max_requested & max_current_claimed); - typec_select_src_current_limit_rp(rem_non_pd, + typec_select_src_current_limit_rp( + rem_non_pd, typec_get_default_current_limit_rp(rem_non_pd)); max_current_claimed &= ~BIT(rem_non_pd); @@ -653,7 +650,7 @@ static void balance_source_ports(void) int new_max_port = LOWEST_PORT(new_ports); if (count_port_bits(max_current_claimed) < - CONFIG_USB_PD_3A_PORTS) { + CONFIG_USB_PD_3A_PORTS) { max_current_claimed |= BIT(new_max_port); typec_select_src_current_limit_rp(new_max_port, TYPEC_RP_3A0); @@ -766,8 +763,8 @@ void dpm_remove_sink(int port) atomic_clear_bits(&non_pd_sink_max_requested, BIT(port)); /* Restore selected default Rp on the port */ - typec_select_src_current_limit_rp(port, - typec_get_default_current_limit_rp(port)); + typec_select_src_current_limit_rp( + port, typec_get_default_current_limit_rp(port)); balance_source_ports(); } @@ -820,8 +817,8 @@ int dpm_get_source_current(const int port) return 500; } -__overridable enum pd_sdb_power_indicator board_get_pd_sdb_power_indicator( -enum pd_sdb_power_state power_state) +__overridable enum pd_sdb_power_indicator +board_get_pd_sdb_power_indicator(enum pd_sdb_power_state power_state) { /* * LED on for S0 and blinking for S0ix/S3. @@ -856,7 +853,7 @@ static uint8_t get_status_internal_temp(void) else if (temp_c < 2) temp_c = 1; - return (uint8_t) temp_c; + return (uint8_t)temp_c; #else return 0; #endif -- cgit v1.2.1 From ed900d75e11863e7460506b32b9d06736ecc5b98 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:48 -0600 Subject: driver/accel_kionix.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I22458749a0bfd18603febea376b6d8b67d61f114 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729888 Reviewed-by: Jeremy Bettis --- driver/accel_kionix.c | 159 ++++++++++++++++++++++---------------------------- 1 file changed, 69 insertions(+), 90 deletions(-) diff --git a/driver/accel_kionix.c b/driver/accel_kionix.c index 3b75e33e0b..e24034231c 100644 --- a/driver/accel_kionix.c +++ b/driver/accel_kionix.c @@ -23,7 +23,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /* Number of times to attempt to enable sensor before giving up. */ #define SENSOR_ENABLE_ATTEMPTS 3 @@ -46,32 +46,28 @@ #define T(s_) V(s_) #endif /* !defined(CONFIG_ACCEL_KXCJ9) || !defined(CONFIG_ACCEL_KX022) */ -STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR) int check_orientation_locked( - const struct motion_sensor_t *s); +STATIC_IF(CONFIG_KX022_ORIENTATION_SENSOR) +int check_orientation_locked(const struct motion_sensor_t *s); /* List of range values in +/-G's and their associated register values. */ static const struct accel_param_pair ranges[][3] = { #ifdef CONFIG_ACCEL_KX022 - { {2, KX022_GSEL_2G}, - {4, KX022_GSEL_4G}, - {8, KX022_GSEL_8G} }, + { { 2, KX022_GSEL_2G }, { 4, KX022_GSEL_4G }, { 8, KX022_GSEL_8G } }, #endif /* defined(CONFIG_ACCEL_KX022) */ #ifdef CONFIG_ACCEL_KXCJ9 - { {2, KXCJ9_GSEL_2G}, - {4, KXCJ9_GSEL_4G}, - {8, KXCJ9_GSEL_8G_14BIT} }, + { { 2, KXCJ9_GSEL_2G }, + { 4, KXCJ9_GSEL_4G }, + { 8, KXCJ9_GSEL_8G_14BIT } }, #endif /* defined(CONFIG_ACCEL_KXCJ9) */ }; /* List of resolution values in bits and their associated register values. */ static const struct accel_param_pair resolutions[][2] = { #ifdef CONFIG_ACCEL_KX022 - { {8, KX022_RES_8BIT}, - {16, KX022_RES_16BIT} }, + { { 8, KX022_RES_8BIT }, { 16, KX022_RES_16BIT } }, #endif /* defined(CONFIG_ACCEL_KX022) */ #ifdef CONFIG_ACCEL_KXCJ9 - { {8, KXCJ9_RES_8BIT}, - {12, KXCJ9_RES_12BIT} }, + { { 8, KXCJ9_RES_8BIT }, { 12, KXCJ9_RES_12BIT } }, #endif /* defined(CONFIG_ACCEL_KXCJ9) */ }; @@ -79,34 +75,34 @@ static const struct accel_param_pair resolutions[][2] = { static const struct accel_param_pair datarates[][13] = { #ifdef CONFIG_ACCEL_KX022 /* One duplicate because table sizes must match. */ - { {781, KX022_OSA_0_781HZ}, - {781, KX022_OSA_0_781HZ}, - {1563, KX022_OSA_1_563HZ}, - {3125, KX022_OSA_3_125HZ}, - {6250, KX022_OSA_6_250HZ}, - {12500, KX022_OSA_12_50HZ}, - {25000, KX022_OSA_25_00HZ}, - {50000, KX022_OSA_50_00HZ}, - {100000, KX022_OSA_100_0HZ}, - {200000, KX022_OSA_200_0HZ}, - {400000, KX022_OSA_400_0HZ}, - {800000, KX022_OSA_800_0HZ}, - {1600000, KX022_OSA_1600HZ} }, + { { 781, KX022_OSA_0_781HZ }, + { 781, KX022_OSA_0_781HZ }, + { 1563, KX022_OSA_1_563HZ }, + { 3125, KX022_OSA_3_125HZ }, + { 6250, KX022_OSA_6_250HZ }, + { 12500, KX022_OSA_12_50HZ }, + { 25000, KX022_OSA_25_00HZ }, + { 50000, KX022_OSA_50_00HZ }, + { 100000, KX022_OSA_100_0HZ }, + { 200000, KX022_OSA_200_0HZ }, + { 400000, KX022_OSA_400_0HZ }, + { 800000, KX022_OSA_800_0HZ }, + { 1600000, KX022_OSA_1600HZ } }, #endif /* defined(CONFIG_ACCEL_KX022) */ #ifdef CONFIG_ACCEL_KXCJ9 - { {0, KXCJ9_OSA_0_000HZ}, - {781, KXCJ9_OSA_0_781HZ}, - {1563, KXCJ9_OSA_1_563HZ}, - {3125, KXCJ9_OSA_3_125HZ}, - {6250, KXCJ9_OSA_6_250HZ}, - {12500, KXCJ9_OSA_12_50HZ}, - {25000, KXCJ9_OSA_25_00HZ}, - {50000, KXCJ9_OSA_50_00HZ}, - {100000, KXCJ9_OSA_100_0HZ}, - {200000, KXCJ9_OSA_200_0HZ}, - {400000, KXCJ9_OSA_400_0HZ}, - {800000, KXCJ9_OSA_800_0HZ}, - {1600000, KXCJ9_OSA_1600_HZ} }, + { { 0, KXCJ9_OSA_0_000HZ }, + { 781, KXCJ9_OSA_0_781HZ }, + { 1563, KXCJ9_OSA_1_563HZ }, + { 3125, KXCJ9_OSA_3_125HZ }, + { 6250, KXCJ9_OSA_6_250HZ }, + { 12500, KXCJ9_OSA_12_50HZ }, + { 25000, KXCJ9_OSA_25_00HZ }, + { 50000, KXCJ9_OSA_50_00HZ }, + { 100000, KXCJ9_OSA_100_0HZ }, + { 200000, KXCJ9_OSA_200_0HZ }, + { 400000, KXCJ9_OSA_400_0HZ }, + { 800000, KXCJ9_OSA_800_0HZ }, + { 1600000, KXCJ9_OSA_1600_HZ } }, #endif /* defined(CONFIG_ACCEL_KXCJ9) */ }; @@ -127,7 +123,7 @@ static int find_param_index(const int eng_val, const int round_up, if (eng_val <= pairs[i].val) return i; - if (eng_val < pairs[i+1].val) { + if (eng_val < pairs[i + 1].val) { if (round_up) return i + 1; else @@ -141,8 +137,7 @@ static int find_param_index(const int eng_val, const int round_up, /** * Read register from accelerometer. */ -static int raw_read8(const int port, - const uint16_t i2c_spi_addr_flags, +static int raw_read8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, int *data_ptr) { int rv = EC_ERROR_INVAL; @@ -160,8 +155,7 @@ static int raw_read8(const int port, #endif } else { - rv = i2c_read8(port, i2c_spi_addr_flags, - reg, data_ptr); + rv = i2c_read8(port, i2c_spi_addr_flags, reg, data_ptr); } return rv; } @@ -169,8 +163,7 @@ static int raw_read8(const int port, /** * Write register from accelerometer. */ -static int raw_write8(const int port, - const uint16_t i2c_spi_addr_flags, +static int raw_write8(const int port, const uint16_t i2c_spi_addr_flags, const int reg, int data) { int rv = EC_ERROR_INVAL; @@ -184,14 +177,12 @@ static int raw_write8(const int port, cmd, 2, NULL, 0); #endif } else { - rv = i2c_write8(port, i2c_spi_addr_flags, - reg, data); + rv = i2c_write8(port, i2c_spi_addr_flags, reg, data); } return rv; } -static int raw_read_multi(const int port, - const uint16_t i2c_spi_addr_flags, +static int raw_read_multi(const int port, const uint16_t i2c_spi_addr_flags, uint8_t reg, uint8_t *rxdata, int rxlen) { int rv = EC_ERROR_INVAL; @@ -204,8 +195,8 @@ static int raw_read_multi(const int port, ®, 1, rxdata, rxlen); #endif } else { - rv = i2c_read_block(port, i2c_spi_addr_flags, - reg, rxdata, rxlen); + rv = i2c_read_block(port, i2c_spi_addr_flags, reg, rxdata, + rxlen); } return rv; } @@ -233,15 +224,13 @@ static int disable_sensor(const struct motion_sensor_t *s, int *reg_val) * so that we can restore it later. */ for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) { - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - reg, reg_val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, reg_val); if (ret != EC_SUCCESS) continue; *reg_val &= ~pc1_field; - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - reg, *reg_val); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, *reg_val); if (ret == EC_SUCCESS) return EC_SUCCESS; } @@ -266,20 +255,18 @@ static int enable_sensor(const struct motion_sensor_t *s, int reg_val) pc1_field = KIONIX_PC1_FIELD(V(s)); for (i = 0; i < SENSOR_ENABLE_ATTEMPTS; i++) { - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - reg, ®_val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, ®_val); if (ret != EC_SUCCESS) continue; /* Enable tilt orientation mode if lid sensor */ if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) && - (s->location == MOTIONSENSE_LOC_LID) && - (V(s) == 0)) + (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0)) reg_val |= KX022_CNTL1_TPE; /* Enable accelerometer based on reg_val value. */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - reg, reg_val | pc1_field); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, + reg_val | pc1_field); /* On first success, we are done. */ if (ret == EC_SUCCESS) @@ -313,8 +300,7 @@ static int set_value(const struct motion_sensor_t *s, int reg, int val, /* Determine new value of control reg and attempt to write it. */ reg_val_new = (reg_val & ~field) | val; - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - reg, reg_val_new); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, reg_val_new); /* If successfully written, then save the range. */ if (ret == EC_SUCCESS) @@ -381,7 +367,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) ret = set_value(s, reg, odr_val, odr_field); if (ret == EC_SUCCESS) - data->base.odr = datarates[T(s)][index].val; + data->base.odr = datarates[T(s)][index].val; return ret; } @@ -414,9 +400,8 @@ static int get_offset(const struct motion_sensor_t *s, int16_t *offset, return EC_SUCCESS; } -static __maybe_unused enum motionsensor_orientation kx022_convert_orientation( - const struct motion_sensor_t *s, - int orientation) +static __maybe_unused enum motionsensor_orientation +kx022_convert_orientation(const struct motion_sensor_t *s, int orientation) { enum motionsensor_orientation res = MOTIONSENSE_ORIENTATION_UNKNOWN; @@ -447,8 +432,8 @@ static int check_orientation_locked(const struct motion_sensor_t *s) int orientation, raw_orientation; int ret; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - KX022_TSCP, &raw_orientation); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, KX022_TSCP, + &raw_orientation); if (ret != EC_SUCCESS) return ret; @@ -465,11 +450,11 @@ static int check_orientation_locked(const struct motion_sensor_t *s) bool motion_orientation_changed(const struct motion_sensor_t *s) { return ((struct kionix_accel_data *)s->drv_data)->orientation != - ((struct kionix_accel_data *)s->drv_data)->last_orientation; + ((struct kionix_accel_data *)s->drv_data)->last_orientation; } -enum motionsensor_orientation *motion_orientation_ptr( - const struct motion_sensor_t *s) +enum motionsensor_orientation * +motion_orientation_ptr(const struct motion_sensor_t *s) { return &((struct kionix_accel_data *)s->drv_data)->orientation; } @@ -494,8 +479,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v) mutex_lock(s->mutex); ret = raw_read_multi(s->port, s->i2c_spi_addr_flags, reg, acc, 6); if (IS_ENABLED(CONFIG_KX022_ORIENTATION_SENSOR) && - (s->location == MOTIONSENSE_LOC_LID) && - (V(s) == 0) && + (s->location == MOTIONSENSE_LOC_LID) && (V(s) == 0) && (ret == EC_SUCCESS)) ret = check_orientation_locked(s); mutex_unlock(s->mutex); @@ -520,7 +504,7 @@ static int read(const struct motion_sensor_t *s, intv3_t v) for (i = X; i <= Z; i++) { if (V(s)) { v[i] = (((int8_t)acc[i * 2 + 1]) << 4) | - (acc[i * 2] >> 4); + (acc[i * 2] >> 4); v[i] <<= 16 - resolution; } else { if (resolution == 8) @@ -550,8 +534,8 @@ static int init(struct motion_sensor_t *s) do { msleep(1); /* Read WHO_AM_I to be sure the device has booted */ - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - reg, &val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, + &val); if (ret == EC_SUCCESS) break; @@ -564,8 +548,7 @@ static int init(struct motion_sensor_t *s) } else { /* Write 0x00 to the internal register for KX022 */ reg = KX022_INTERNAL; - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - reg, 0x0); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, reg, 0x0); if (ret != EC_SUCCESS) { /* * For I2C communication, if ACK was not received @@ -574,11 +557,9 @@ static int init(struct motion_sensor_t *s) */ if (!ACCEL_ADDR_IS_SPI(s->i2c_spi_addr_flags)) { const uint16_t i2c_alt_addr_flags = - I2C_STRIP_FLAGS( - s->i2c_spi_addr_flags) - & ~2; - ret = raw_write8(s->port, - i2c_alt_addr_flags, + I2C_STRIP_FLAGS(s->i2c_spi_addr_flags) & + ~2; + ret = raw_write8(s->port, i2c_alt_addr_flags, reg, 0x0); } } @@ -620,8 +601,8 @@ static int init(struct motion_sensor_t *s) do { msleep(1); - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - reg, &val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, reg, + &val); /* Reset complete. */ if ((ret == EC_SUCCESS) && !(val & reset_field)) break; @@ -672,9 +653,7 @@ static int probe(const struct motion_sensor_t *s) { int val; - if (i2c_read8(s->port, - s->i2c_spi_addr_flags, - KIONIX_WHO_AM_I(V(s)), + if (i2c_read8(s->port, s->i2c_spi_addr_flags, KIONIX_WHO_AM_I(V(s)), &val) != EC_SUCCESS) return EC_ERROR_HW_INTERNAL; -- cgit v1.2.1 From eab66f46fc66c82dab87c62cb2df2f2506268b25 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:47 -0600 Subject: driver/temp_sensor/amd_r19me4070.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifdac222bcf0c7d023d8873c2a29a6462d484e855 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730102 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/amd_r19me4070.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/driver/temp_sensor/amd_r19me4070.c b/driver/temp_sensor/amd_r19me4070.c index b5f4e66d38..afe8741e77 100644 --- a/driver/temp_sensor/amd_r19me4070.c +++ b/driver/temp_sensor/amd_r19me4070.c @@ -13,14 +13,14 @@ #include "amd_r19me4070.h" #include "power.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* GPU I2C address */ -#define GPU_ADDR_FLAGS 0x0041 +#define GPU_ADDR_FLAGS 0x0041 -#define GPU_INIT_OFFSET 0x01 -#define GPU_TEMPERATURE_OFFSET 0x03 +#define GPU_INIT_OFFSET 0x01 +#define GPU_TEMPERATURE_OFFSET 0x03 static int initialized; /* @@ -34,8 +34,8 @@ static void gpu_init_temp_sensor(void) { int rv; rv = i2c_write_block(I2C_PORT_GPU, GPU_ADDR_FLAGS, GPU_INIT_OFFSET, - gpu_init_write_value, - ARRAY_SIZE(gpu_init_write_value)); + gpu_init_write_value, + ARRAY_SIZE(gpu_init_write_value)); if (rv == EC_SUCCESS) { initialized = 1; return; @@ -64,7 +64,7 @@ int get_temp_R19ME4070(int idx, int *temp_ptr) return EC_ERROR_BUSY; } rv = i2c_read_block(I2C_PORT_GPU, GPU_ADDR_FLAGS, - GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg)); + GPU_TEMPERATURE_OFFSET, reg, ARRAY_SIZE(reg)); if (rv) { CPRINTS("read GPU Temperature fail"); *temp_ptr = C_TO_K(0); -- cgit v1.2.1 From 963f4df974102f0f1d9426ede7331e997027e5db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:29 -0600 Subject: board/magolor/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4b0511f8c6f3018941ee5ce1fd683ec255b247c1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728643 Reviewed-by: Jeremy Bettis --- board/magolor/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/magolor/usb_pd_policy.c b/board/magolor/usb_pd_policy.c index 02bb449f60..f2e62044b5 100644 --- a/board/magolor/usb_pd_policy.c +++ b/board/magolor/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 0bb480adba618401722cecfb3c0c6de32a4f0655 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:35 -0600 Subject: board/homestar/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I78cddeb03104a72c9a21ed9c2430a6a4863bc88c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728469 Reviewed-by: Jeremy Bettis --- board/homestar/board.h | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/board/homestar/board.h b/board/homestar/board.h index 74de48df1d..d00e40d1c3 100644 --- a/board/homestar/board.h +++ b/board/homestar/board.h @@ -13,13 +13,13 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Switchcap */ #define CONFIG_LN9310 /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -90,10 +90,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 56510b59458b5204b8a1265c9d3d867ee0347198 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:08 -0600 Subject: include/i2c_private.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5513cc52f214256498aae9249cb390c8707e9d78 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730307 Reviewed-by: Jeremy Bettis --- include/i2c_private.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/i2c_private.h b/include/i2c_private.h index 0759f86ef2..083956e05d 100644 --- a/include/i2c_private.h +++ b/include/i2c_private.h @@ -29,10 +29,8 @@ * @param flags Flags (see I2C_XFER_* above) * @return EC_SUCCESS, or non-zero if error. */ -int chip_i2c_xfer(const int port, - const uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags); +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags); /** * Chip level function to set bus speed. -- cgit v1.2.1 From a36b7a6cb35b9a83aa5896caaab0c413c2c4fa95 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:39 -0600 Subject: core/cortex-m/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ae03f882c46824c1e55a5f04022e8787bc6327a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729819 Reviewed-by: Jeremy Bettis --- core/cortex-m/include/fpu.h | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/core/cortex-m/include/fpu.h b/core/cortex-m/include/fpu.h index 0949d336e2..d25e4ee552 100644 --- a/core/cortex-m/include/fpu.h +++ b/core/cortex-m/include/fpu.h @@ -12,24 +12,16 @@ static inline float sqrtf(float v) { float root; - asm volatile( - "fsqrts %0, %1" - : "=w" (root) - : "w" (v) - ); + asm volatile("fsqrts %0, %1" : "=w"(root) : "w"(v)); return root; } static inline float fabsf(float v) { float root; - asm volatile( - "fabss %0, %1" - : "=w" (root) - : "w" (v) - ); + asm volatile("fabss %0, %1" : "=w"(root) : "w"(v)); return root; } -#endif /* CONFIG_FPU */ +#endif /* CONFIG_FPU */ -#endif /* __CROS_EC_FPU_H */ +#endif /* __CROS_EC_FPU_H */ -- cgit v1.2.1 From 0c9f9a1cfc2d24c846818d84c2f1ae0d98d2354c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:28 -0600 Subject: board/reef/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icfee909f3caaab762312c4deff3fad6e35b543cf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728882 Reviewed-by: Jeremy Bettis --- board/reef/board.h | 60 ++++++++++++++++++++++++++---------------------------- 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/board/reef/board.h b/board/reef/board.h index d4cc2ccad2..e2583bbb93 100644 --- a/board/reef/board.h +++ b/board/reef/board.h @@ -12,24 +12,23 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF - /* EC console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO #define CONFIG_CMD_BATT_MFG_ACCESS #define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define BD9995X_IOUT_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V + BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V #define CONFIG_CHARGER_PSYS_READ #define BD9995X_PSYS_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW + BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW #define CONFIG_CMD_I2C_STRESS_TEST #define CONFIG_CMD_I2C_STRESS_TEST_ACCEL @@ -39,7 +38,7 @@ #define CONFIG_CMD_I2C_STRESS_TEST_TCPC /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_SMART @@ -60,7 +59,7 @@ #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON -#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES +#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT @@ -87,7 +86,7 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_TCPC_LOW_POWER -#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ +#define CONFIG_USB_PD_TCPM_MUX /* for both PS8751 and ANX3429 */ #define CONFIG_USB_PD_TCPM_ANX3429 #define CONFIG_USB_PD_TCPM_PS8751 #define CONFIG_USB_PD_TCPM_TCPCI @@ -115,8 +114,8 @@ /* EC */ #define CONFIG_ADC #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_FPU #define CONFIG_HOSTCMD_FLASH_SPI_INFO #define CONFIG_I2C @@ -145,7 +144,7 @@ #define CONFIG_WIRELESS #define CONFIG_WIRELESS_SUSPEND EC_WIRELESS_SWITCH_WLAN_POWER #define CONFIG_WLAN_POWER_ACTIVE_LOW -#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER +#define WIRELESS_GPIO_WLAN_POWER GPIO_WIRELESS_GPIO_WLAN_POWER #define CONFIG_PWR_STATE_DISCHARGE_FULL #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 512 @@ -165,7 +164,7 @@ #define CONFIG_FLASH_SIZE_BYTES 524288 #define CONFIG_SPI_FLASH_REGS -#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ +#define CONFIG_SPI_FLASH_W25Q40 /* FIXME: Should be GD25LQ40? */ /* * Enable 1 slot of secure temporary storage to support @@ -175,21 +174,21 @@ #define CONFIG_VSTORE_SLOT_COUNT 1 /* Optional feature - used by nuvoton */ -#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ +#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/ /* FIXME(dhendrix): these pins are just normal GPIOs on Reef. Do we need * to change some other setting to put them in GPIO mode? */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_GYRO NPCX_I2C_PORT1 -#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 -#define I2C_PORT_ALS NPCX_I2C_PORT2 -#define I2C_PORT_BARO NPCX_I2C_PORT2 -#define I2C_PORT_BATTERY NPCX_I2C_PORT3 -#define I2C_PORT_CHARGER NPCX_I2C_PORT3 +#define I2C_PORT_GYRO NPCX_I2C_PORT1 +#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 +#define I2C_PORT_ALS NPCX_I2C_PORT2 +#define I2C_PORT_BARO NPCX_I2C_PORT2 +#define I2C_PORT_BATTERY NPCX_I2C_PORT3 +#define I2C_PORT_CHARGER NPCX_I2C_PORT3 /* Accelerometer and Gyroscope are the same device. */ -#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_ACCEL I2C_PORT_GYRO /* Sensors */ #define CONFIG_MKBP_EVENT @@ -215,7 +214,6 @@ /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -223,9 +221,9 @@ /* ADC signal */ enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ - ADC_TEMP_SENSOR_AMB, /* ADC1 */ - ADC_BOARD_ID, /* ADC2 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC0 */ + ADC_TEMP_SENSOR_AMB, /* ADC1 */ + ADC_BOARD_ID, /* ADC2 */ ADC_CH_COUNT }; @@ -286,16 +284,16 @@ enum reef_board_version { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Reset PD MCU */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From 4684dffb4fea86ed67df58555ece8d2114f402ce Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:22 -0600 Subject: chip/npcx/gpio_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib302a155b6228f2e7f1141f70ab2433e501fdc2c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729397 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip.h | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h index 2d0b2b4e9b..52ab91585e 100644 --- a/chip/npcx/gpio_chip.h +++ b/chip/npcx/gpio_chip.h @@ -9,37 +9,40 @@ struct npcx_wui { uint8_t table : 2; uint8_t group : 3; - uint8_t bit : 3; + uint8_t bit : 3; }; /* Macros to initialize the MIWU mapping table. */ #define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index -#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \ - .bit = idx }) -#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) -#define WUI_NONE ((struct npcx_wui) { .table = MIWU_TABLE_COUNT, .group = 0, \ - .bit = 0 }) +#define WUI(tbl, grp, idx) \ + ((struct npcx_wui){ .table = tbl, .group = grp, .bit = idx }) +#define WUI_INT(tbl, grp) WUI(tbl, grp, 0) +#define WUI_NONE \ + ((struct npcx_wui){ .table = MIWU_TABLE_COUNT, .group = 0, .bit = 0 }) /* Macros to initialize the alternative and low voltage mapping table. */ -#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0}) -#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \ - .bit = pin, .valid = 1}) +#define NPCX_GPIO_NONE ((struct npcx_gpio){ .port = 0, .bit = 0, .valid = 0 }) +#define NPCX_GPIO(grp, pin) \ + ((struct npcx_gpio){ .port = GPIO_PORT_##grp, .bit = pin, .valid = 1 }) -#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ - .bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 }) -#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \ - .bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 }) -#define ALT(port, index, _alt) { .gpio = NPCX_GPIO(port, index), \ - .alt = (_alt) }, +#define NPCX_ALT(grp, pin) \ + ((struct npcx_alt){ .group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, \ + .inverted = 0 }) +#define NPCX_ALT_INV(grp, pin) \ + ((struct npcx_alt){ .group = ALT_GROUP_##grp, \ + .bit = NPCX_DEVALT##grp##_##pin, \ + .inverted = 1 }) +#define ALT(port, index, _alt) \ + { .gpio = NPCX_GPIO(port, index), .alt = (_alt) }, -#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \ - NPCX_LVOL_CTRL_##ctrl##_1, \ - NPCX_LVOL_CTRL_##ctrl##_2, \ - NPCX_LVOL_CTRL_##ctrl##_3, \ - NPCX_LVOL_CTRL_##ctrl##_4, \ - NPCX_LVOL_CTRL_##ctrl##_5, \ - NPCX_LVOL_CTRL_##ctrl##_6, \ - NPCX_LVOL_CTRL_##ctrl##_7, } +#define NPCX_LVOL_CTRL_ITEMS(ctrl) \ + { \ + NPCX_LVOL_CTRL_##ctrl##_0, NPCX_LVOL_CTRL_##ctrl##_1, \ + NPCX_LVOL_CTRL_##ctrl##_2, NPCX_LVOL_CTRL_##ctrl##_3, \ + NPCX_LVOL_CTRL_##ctrl##_4, NPCX_LVOL_CTRL_##ctrl##_5, \ + NPCX_LVOL_CTRL_##ctrl##_6, NPCX_LVOL_CTRL_##ctrl##_7, \ + } /** * Switch NPCX UART pins back to normal GPIOs. -- cgit v1.2.1 From 5ef9e581a4ee82cb7c5c8cae430a32407e6013dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:53 -0600 Subject: board/kinox/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I51c821e32da7ac6ddc00bcdf52232cf898d51202 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728554 Reviewed-by: Jeremy Bettis --- board/kinox/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kinox/fw_config.c b/board/kinox/fw_config.c index 02f39e70f4..f710ad1ed4 100644 --- a/board/kinox/fw_config.c +++ b/board/kinox/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union kinox_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 1ac81ec76d3b7c28f162a92016a4c7f8d22a0eb4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:40 -0600 Subject: board/taniks/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a8198e08ed6b442dd8f8350efe32682e85a03dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729007 Reviewed-by: Jeremy Bettis --- board/taniks/battery.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/taniks/battery.c b/board/taniks/battery.c index f62aae62a1..c84452e9bb 100644 --- a/board/taniks/battery.c +++ b/board/taniks/battery.c @@ -124,7 +124,9 @@ __override bool board_battery_is_initialized(void) bool batt_initialization_state; int batt_status; - batt_initialization_state = (battery_status(&batt_status) ? false : - !!(batt_status & STATUS_INITIALIZED)); + batt_initialization_state = + (battery_status(&batt_status) ? + false : + !!(batt_status & STATUS_INITIALIZED)); return batt_initialization_state; } -- cgit v1.2.1 From a5736db8229bb57cf44931d116d766704b4d6730 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:04 -0600 Subject: driver/led/ds2413.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3b476801dc61ed301de0f3daf07b7dcab3c9debd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729994 Reviewed-by: Jeremy Bettis --- driver/led/ds2413.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/driver/led/ds2413.c b/driver/led/ds2413.c index b856d85671..93d90f7656 100644 --- a/driver/led/ds2413.c +++ b/driver/led/ds2413.c @@ -19,12 +19,12 @@ enum led_color { LED_RED, LED_YELLOW, LED_GREEN, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -static const uint8_t led_masks[LED_COLOR_COUNT] = {0xff, 0xfe, 0xfc, 0xfd}; -static const char * const color_names[LED_COLOR_COUNT] = { - "off", "red", "yellow", "green"}; +static const uint8_t led_masks[LED_COLOR_COUNT] = { 0xff, 0xfe, 0xfc, 0xfd }; +static const char *const color_names[LED_COLOR_COUNT] = { "off", "red", + "yellow", "green" }; /** * Set the onewire LED GPIO controller outputs @@ -48,9 +48,9 @@ static int led_set_mask(int mask) /* Write and turn on the LEDs */ onewire_write(0x5a); onewire_write(mask); - onewire_write(~mask); /* Repeat inverted */ + onewire_write(~mask); /* Repeat inverted */ - rv = onewire_read(); /* Confirmation byte */ + rv = onewire_read(); /* Confirmation byte */ if (rv != 0xaa) return EC_ERROR_UNKNOWN; @@ -161,6 +161,5 @@ static int command_powerled(int argc, char **argv) return EC_ERROR_PARAM1; } DECLARE_CONSOLE_COMMAND(powerled, command_powerled, - "", - "Set power LED color"); + "", "Set power LED color"); #endif -- cgit v1.2.1 From e818602268197410e71f66704a0cbd889f8d3c27 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:20 -0600 Subject: zephyr/shim/include/fpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01c322d7a923f1f66af5c2def14d1f3108247651 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730827 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/fpu.h | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/zephyr/shim/include/fpu.h b/zephyr/shim/include/fpu.h index 8f78fb587d..6d15c94a93 100644 --- a/zephyr/shim/include/fpu.h +++ b/zephyr/shim/include/fpu.h @@ -25,11 +25,7 @@ static inline float sqrtf(float v) float root; /* Use the CPU instruction */ - __asm__ volatile( - "fsqrts %0, %1" - : "=w" (root) - : "w" (v) - ); + __asm__ volatile("fsqrts %0, %1" : "=w"(root) : "w"(v)); return root; } @@ -39,11 +35,7 @@ static inline float fabsf(float v) float root; /* Use the CPU instruction */ - __asm__ volatile( - "fabss %0, %1" - : "=w" (root) - : "w" (v) - ); + __asm__ volatile("fabss %0, %1" : "=w"(root) : "w"(v)); return root; } @@ -67,6 +59,6 @@ static inline float fabsf(float v) #error "Unsupported core: please add an implementation" #endif -#endif /* CONFIG_PLATFORM_EC_FPU */ +#endif /* CONFIG_PLATFORM_EC_FPU */ -#endif /* __CROS_EC_MATH_H */ +#endif /* __CROS_EC_MATH_H */ -- cgit v1.2.1 From bc2c28f0b0f18f09756343bc41c0df93eeded193 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:17 -0600 Subject: test/rsa.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0534763b9e25944eceb4229f4bfb411aab886406 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730519 Reviewed-by: Jeremy Bettis --- test/rsa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/rsa.c b/test/rsa.c index 8e4eeef54c..73c6ae0bfa 100644 --- a/test/rsa.c +++ b/test/rsa.c @@ -21,7 +21,7 @@ #include "rsa2048-F4.h" #endif -static uint32_t rsa_workbuf[3 * RSANUMBYTES/4]; +static uint32_t rsa_workbuf[3 * RSANUMBYTES / 4]; void run_test(int argc, char **argv) { @@ -45,7 +45,7 @@ void run_test(int argc, char **argv) ccprintf("RSA verify FAILED (as expected)\n"); /* Test with a wrong signature */ - good = rsa_verify(rsa_key, sig+1, hash, rsa_workbuf); + good = rsa_verify(rsa_key, sig + 1, hash, rsa_workbuf); if (good) { ccprintf("RSA verify OK (expected fail)\n"); test_fail(); -- cgit v1.2.1 From b7678ef2ed5961d3148141504c42fec73ff4243b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:34 -0600 Subject: util/uut/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib60134bb24d2e26e484386b31a9fe1a5feb7a923 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730663 Reviewed-by: Jeremy Bettis --- util/uut/main.c | 114 +++++++++++++++++++++++++++----------------------------- 1 file changed, 54 insertions(+), 60 deletions(-) diff --git a/util/uut/main.c b/util/uut/main.c index 146ddc0275..dddb77629b 100644 --- a/util/uut/main.c +++ b/util/uut/main.c @@ -36,20 +36,20 @@ #define DEFAULT_FLASH_OFFSET 0 /* The magic number in monitor header */ -#define MONITOR_HDR_TAG 0xA5075001 +#define MONITOR_HDR_TAG 0xA5075001 /* The location of monitor header */ -#define MONITOR_HDR_ADDR 0x200C3000 +#define MONITOR_HDR_ADDR 0x200C3000 /* The start address of the monitor little firmware to execute */ -#define MONITOR_ADDR 0x200C3020 +#define MONITOR_ADDR 0x200C3020 /* The start address to store the firmware segment to be programmed */ -#define FIRMWARE_START_ADDR 0x10090000 +#define FIRMWARE_START_ADDR 0x10090000 /* Divide the ec firmware image into 4K byte */ -#define FIRMWARE_SEGMENT 0x1000 +#define FIRMWARE_SEGMENT 0x1000 /* Register address for chip ID */ -#define NPCX_SRID_CR 0x400C101C +#define NPCX_SRID_CR 0x400C101C /* Register address for device ID */ -#define NPCX_DEVICE_ID_CR 0x400C1022 -#define NPCX_FLASH_BASE_ADDR 0x64000000 +#define NPCX_DEVICE_ID_CR 0x400C1022 +#define NPCX_FLASH_BASE_ADDR 0x64000000 /*--------------------------------------------------------------------------- * Global variables @@ -64,8 +64,8 @@ struct comport_fields port_cfg; *--------------------------------------------------------------------------- */ -static const char tool_name[] = {"LINUX UART Update Tool"}; -static const char tool_version[] = {"2.0.1"}; +static const char tool_name[] = { "LINUX UART Update Tool" }; +static const char tool_version[] = { "2.0.1" }; static char port_name[MAX_PARAM_SIZE]; static char opr_name[MAX_PARAM_SIZE]; @@ -185,7 +185,7 @@ enum EXIT_CODE { *--------------------------------------------------------------------------- */ static bool image_auto_write(uint32_t offset, uint8_t *buffer, - uint32_t file_size) + uint32_t file_size) { uint32_t data_buf[4]; uint32_t addr, chunk_remain, file_seg, flash_index, seg; @@ -199,8 +199,8 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer, file_seg = file_size; total = 0; while (file_seg) { - seg = (file_seg > FIRMWARE_SEGMENT) ? - FIRMWARE_SEGMENT : file_seg; + seg = (file_seg > FIRMWARE_SEGMENT) ? FIRMWARE_SEGMENT : + file_seg; /* * Check if the content of the segment is all 0xff. * If yes, there is no need to write. @@ -218,7 +218,7 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer, data_buf[2] = 0; data_buf[3] = flash_index; opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR, - sizeof(data_buf)); + sizeof(data_buf)); if (opr_execute_return(MONITOR_ADDR) != true) return false; file_seg -= seg; @@ -242,10 +242,11 @@ static bool image_auto_write(uint32_t offset, uint8_t *buffer, data_buf[3] = flash_index; /* Write the monitor header to RAM */ opr_write_chunk((uint8_t *)data_buf, MONITOR_HDR_ADDR, - sizeof(data_buf)); + sizeof(data_buf)); while (chunk_remain) { count = (chunk_remain > MAX_RW_DATA_SIZE) ? - MAX_RW_DATA_SIZE : chunk_remain; + MAX_RW_DATA_SIZE : + chunk_remain; if (opr_write_chunk(buffer, addr, count) != true) return false; @@ -281,13 +282,13 @@ static bool get_flash_size(uint32_t *flash_size) for (i = 0; i < ARRAY_SIZE(chip_info); i++) { if (chip_info[i].device_id == dev_id && - chip_info[i].chip_id == chip_id) { + chip_info[i].chip_id == chip_id) { *flash_size = chip_info[i].flash_size; return true; } } - printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n", - dev_id, chip_id); + printf("Unknown NPCX device ID:0x%02x chip ID:0x%02x\n", dev_id, + chip_id); return false; } @@ -315,8 +316,8 @@ static uint8_t *read_input_file(uint32_t size, const char *file_name) } input_fp = fopen(file_name, "r"); if (!input_fp) { - display_color_msg(FAIL, - "ERROR: cannot open file %s\n", file_name); + display_color_msg(FAIL, "ERROR: cannot open file %s\n", + file_name); free(buffer); return NULL; } @@ -396,9 +397,11 @@ int main(int argc, char *argv[]) * It might fail for garbage data drainage from H1, or * for timeout due to unstable data transfer yet. */ - display_color_msg(FAIL, + display_color_msg( + FAIL, "Host/Device synchronization failed, error = %d," - " fail count = %d\n", sr, sync_cnt); + " fail count = %d\n", + sr, sync_cnt); } if (sync_cnt > MAX_SYNC_RETRIES) exit_uart_app(EC_SYNC_ERR); @@ -412,8 +415,8 @@ int main(int argc, char *argv[]) if (!buffer) exit_uart_app(EC_FILE_ERR); - printf("Write file %s at %d with %d bytes\n", - file_name, flash_offset, size); + printf("Write file %s at %d with %d bytes\n", file_name, + flash_offset, size); if (image_auto_write(flash_offset, buffer, size)) { printf("Flash Done.\n"); free(buffer); @@ -429,7 +432,7 @@ int main(int argc, char *argv[]) if (get_flash_size(&flash_size)) { printf("Read %d bytes from flash...\n", flash_size); opr_read_mem(file_name, NPCX_FLASH_BASE_ADDR, - flash_size); + flash_size); exit_uart_app(EC_OK); } @@ -506,20 +509,13 @@ int main(int argc, char *argv[]) */ static const struct option long_opts[] = { - {"version", 0, 0, 'v'}, - {"help", 0, 0, 'h'}, - {"quiet", 0, 0, 'q'}, - {"console", 0, 0, 'c'}, - {"auto", 0, 0, 'A'}, - {"read-flash", 0, 0, 'r'}, - {"baudrate", 1, 0, 'b'}, - {"opr", 1, 0, 'o'}, - {"port", 1, 0, 'p'}, - {"file", 1, 0, 'f'}, - {"addr", 1, 0, 'a'}, - {"size", 1, 0, 's'}, - {"offset", 1, 0, 'O'}, - {NULL, 0, 0, 0} + { "version", 0, 0, 'v' }, { "help", 0, 0, 'h' }, + { "quiet", 0, 0, 'q' }, { "console", 0, 0, 'c' }, + { "auto", 0, 0, 'A' }, { "read-flash", 0, 0, 'r' }, + { "baudrate", 1, 0, 'b' }, { "opr", 1, 0, 'o' }, + { "port", 1, 0, 'p' }, { "file", 1, 0, 'f' }, + { "addr", 1, 0, 'a' }, { "size", 1, 0, 's' }, + { "offset", 1, 0, 'O' }, { NULL, 0, 0, 0 } }; static const char *short_opts = "vhqcArb:o:p:f:a:s:O:?"; @@ -528,9 +524,8 @@ static void param_parse_cmd_line(int argc, char *argv[]) { int opt, idx; - while ((opt = getopt_long(argc, argv, short_opts, - long_opts, &idx)) != -1) { - + while ((opt = getopt_long(argc, argv, short_opts, long_opts, &idx)) != + -1) { switch (opt) { case 'v': main_print_version(); @@ -558,23 +553,23 @@ static void param_parse_cmd_line(int argc, char *argv[]) break; case 'o': strncpy(opr_name, optarg, sizeof(opr_name)); - opr_name[sizeof(opr_name)-1] = '\0'; + opr_name[sizeof(opr_name) - 1] = '\0'; break; case 'p': strncpy(port_name, optarg, sizeof(port_name)); - port_name[sizeof(port_name)-1] = '\0'; + port_name[sizeof(port_name) - 1] = '\0'; break; case 'f': strncpy(file_name, optarg, sizeof(file_name)); - file_name[sizeof(file_name)-1] = '\0'; + file_name[sizeof(file_name) - 1] = '\0'; break; case 'a': strncpy(addr_str, optarg, sizeof(addr_str)); - addr_str[sizeof(addr_str)-1] = '\0'; + addr_str[sizeof(addr_str) - 1] = '\0'; break; case 's': strncpy(size_str, optarg, sizeof(size_str)); - size_str[sizeof(size_str)-1] = '\0'; + size_str[sizeof(size_str) - 1] = '\0'; break; case 'O': flash_offset = strtol(optarg, NULL, 0); @@ -595,12 +590,12 @@ static void param_parse_cmd_line(int argc, char *argv[]) */ static void param_check_opr_num(const char *opr) { - if ((strcasecmp(opr, OPR_WRITE_MEM) != 0) && - (strcasecmp(opr, OPR_READ_MEM) != 0) && - (strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) && - (strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) { - display_color_msg(FAIL, + (strcasecmp(opr, OPR_READ_MEM) != 0) && + (strcasecmp(opr, OPR_EXECUTE_EXIT) != 0) && + (strcasecmp(opr, OPR_EXECUTE_CONT) != 0)) { + display_color_msg( + FAIL, "ERROR: Operation %s not supported, Supported " "operations are %s, %s, %s & %s\n", opr, OPR_WRITE_MEM, OPR_READ_MEM, OPR_EXECUTE_EXIT, @@ -624,12 +619,11 @@ static uint32_t param_get_file_size(const char *file_name) struct stat fst; if (stat(file_name, &fst)) { - display_color_msg(FAIL, - "ERROR: Could not stat file [%s]\n", file_name); + display_color_msg(FAIL, "ERROR: Could not stat file [%s]\n", + file_name); return 0; } return fst.st_size; - } /*--------------------------------------------------------------------------- @@ -653,7 +647,7 @@ static uint32_t param_get_str_size(char *string) /* Verify string is non-NULL */ if ((string == NULL) || (strlen(string) == 0)) { display_color_msg(FAIL, - "ERROR: Zero length input string provided\n"); + "ERROR: Zero length input string provided\n"); return 0; } @@ -692,14 +686,14 @@ static void tool_usage(void) printf(" -c, --console - Print data to console (default is " "print to file)\n"); printf(" -p, --port - Serial port name (default is %s)\n", - DEFAULT_PORT_NAME); + DEFAULT_PORT_NAME); printf(" -b, --baudrate - COM Port baud-rate (default is %d)\n", - DEFAULT_BAUD_RATE); + DEFAULT_BAUD_RATE); printf(" -A, --auto - Enable auto mode. (default is off)\n"); printf(" -O, --offset - With --auto, assign the offset of"); printf(" flash where the image to be written.\n"); printf(" -r, --read-flash - With --file=, Read the whole" - " flash content and write it to .\n"); + " flash content and write it to .\n"); printf("\n"); printf("Operation specific switches:\n"); printf(" -o, --opr - Operation number (see list below)\n"); -- cgit v1.2.1 From 38d77e3e669bd9f48d8207e83931cfe9255082d2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:32 -0600 Subject: board/makomo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id02cffdb2aca8ec50150c89cd6bf4c66e284abda Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728653 Reviewed-by: Jeremy Bettis --- board/makomo/board.c | 105 ++++++++++++++++++++++----------------------------- 1 file changed, 45 insertions(+), 60 deletions(-) diff --git a/board/makomo/board.c b/board/makomo/board.c index e50f84f3fb..378376bf92 100644 --- a/board/makomo/board.c +++ b/board/makomo/board.c @@ -45,8 +45,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -58,40 +58,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -99,8 +93,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -156,8 +150,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -238,12 +231,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -300,8 +293,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -315,8 +307,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -355,17 +346,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1) } -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ /* Lid accel private data */ @@ -453,7 +440,7 @@ struct motion_sensor_t motion_sensors[] = { const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct it8801_pwm_t it8801_pwm_channels[] = { - [IT8801_PWM_CH_KBLIGHT] = {.index = 4}, + [IT8801_PWM_CH_KBLIGHT] = { .index = 4 }, }; void board_kblight_init(void) @@ -469,11 +456,11 @@ bool board_has_kb_backlight(void) #endif /* !VARIANT_KUKUI_NO_SENSORS */ /* Battery functions */ -#define SB_SMARTCHARGE 0x26 +#define SB_SMARTCHARGE 0x26 /* Quick charge enable bit */ -#define SMART_QUICK_CHARGE 0x02 +#define SMART_QUICK_CHARGE 0x02 /* Quick charge support bit */ -#define MODE_QUICK_CHARGE_SUPPORT 0x01 +#define MODE_QUICK_CHARGE_SUPPORT 0x01 static void sb_quick_charge_mode(int enable) { @@ -544,8 +531,8 @@ int board_get_battery_i2c(void) } #ifdef SECTION_IS_RW -static int it8801_get_target_channel(enum pwm_channel *channel, - int type, int index) +static int it8801_get_target_channel(enum pwm_channel *channel, int type, + int index) { switch (type) { case EC_PWM_TYPE_GENERIC: @@ -568,14 +555,13 @@ host_command_pwm_set_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - duty = (uint32_t) p->duty * 255 / 65535; + duty = (uint32_t)p->duty * 255 / 65535; it8801_pwm_set_raw_duty(channel, duty); it8801_pwm_enable(channel, p->duty > 0); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, - host_command_pwm_set_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_SET_DUTY, host_command_pwm_set_duty, EC_VER_MASK(0)); static enum ec_status @@ -589,12 +575,11 @@ host_command_pwm_get_duty(struct host_cmd_handler_args *args) if (it8801_get_target_channel(&channel, p->pwm_type, p->index)) return EC_RES_INVALID_PARAM; - r->duty = (uint32_t) it8801_pwm_get_raw_duty(channel) * 65535 / 255; + r->duty = (uint32_t)it8801_pwm_get_raw_duty(channel) * 65535 / 255; args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, - host_command_pwm_get_duty, +DECLARE_HOST_COMMAND(EC_CMD_PWM_GET_DUTY, host_command_pwm_get_duty, EC_VER_MASK(0)); #endif -- cgit v1.2.1 From 0a78b65677ae20987606265a22c77c3d69502851 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:25 -0600 Subject: cts/i2c/dut.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I15ce8df37654a042b2c3f1aff7b7b9aa3e25232e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729761 Reviewed-by: Jeremy Bettis --- cts/i2c/dut.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/cts/i2c/dut.c b/cts/i2c/dut.c index c7a3f9fccf..1b8e29b717 100644 --- a/cts/i2c/dut.c +++ b/cts/i2c/dut.c @@ -17,24 +17,24 @@ enum cts_rc write8_test(void) { - if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS, - WRITE8_OFF, WRITE8_DATA)) + if (i2c_write8(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE8_OFF, + WRITE8_DATA)) return CTS_RC_FAILURE; return CTS_RC_SUCCESS; } enum cts_rc write16_test(void) { - if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS, - WRITE16_OFF, WRITE16_DATA)) + if (i2c_write16(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE16_OFF, + WRITE16_DATA)) return CTS_RC_FAILURE; return CTS_RC_SUCCESS; } enum cts_rc write32_test(void) { - if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS, - WRITE32_OFF, WRITE32_DATA)) + if (i2c_write32(i2c_ports[0].port, TH_ADDR_FLAGS, WRITE32_OFF, + WRITE32_DATA)) return CTS_RC_FAILURE; return CTS_RC_SUCCESS; } @@ -43,8 +43,7 @@ enum cts_rc read8_test(void) { int data; - if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS, - READ8_OFF, &data)) + if (i2c_read8(i2c_ports[0].port, TH_ADDR_FLAGS, READ8_OFF, &data)) return CTS_RC_FAILURE; if (data != READ8_DATA) { CPRINTL("Expecting 0x%x but read 0x%x", READ8_DATA, data); @@ -58,8 +57,7 @@ enum cts_rc read16_test(void) { int data; - if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS, - READ16_OFF, &data)) + if (i2c_read16(i2c_ports[0].port, TH_ADDR_FLAGS, READ16_OFF, &data)) return CTS_RC_FAILURE; if (data != READ16_DATA) { CPRINTL("Expecting 0x%x but read 0x%x", READ16_DATA, data); @@ -73,8 +71,7 @@ enum cts_rc read32_test(void) { int data; - if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS, - READ32_OFF, &data)) + if (i2c_read32(i2c_ports[0].port, TH_ADDR_FLAGS, READ32_OFF, &data)) return CTS_RC_FAILURE; if (data != READ32_DATA) { CPRINTL("Read 0x%x expecting 0x%x", data, READ32_DATA); @@ -84,7 +81,6 @@ enum cts_rc read32_test(void) return CTS_RC_SUCCESS; } - #include "cts_testlist.h" void cts_task(void) -- cgit v1.2.1 From 009f7f9f6ed2ffa5294272baccdf75d8bf4ed716 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:23 -0600 Subject: board/moonbuggy/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8aa7bb33c42dc27c1316d0bdc53474ebe865485 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728698 Reviewed-by: Jeremy Bettis --- board/moonbuggy/led.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/moonbuggy/led.c b/board/moonbuggy/led.c index f05733a387..9d728b5834 100644 --- a/board/moonbuggy/led.c +++ b/board/moonbuggy/led.c @@ -19,16 +19,16 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) /* * Due to the CSME-Lite processing, upon startup the CPU transitions through * S0->S3->S5->S3->S0, causing the LED to turn on/off/on, so * delay turning off the LED during suspend/shutdown. */ -#define LED_CPU_DELAY_MS (2000 * MSEC) +#define LED_CPU_DELAY_MS (2000 * MSEC) -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -84,9 +84,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented @@ -243,8 +243,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|white|off|alert|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|alert|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From bce822182b25abbece9a3629f4f03fef65f77d3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:27 -0600 Subject: include/keyboard_protocol.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6359a840ed29f42aeb05ca4b8b75937e70e425a7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730298 Reviewed-by: Jeremy Bettis --- include/keyboard_protocol.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/keyboard_protocol.h b/include/keyboard_protocol.h index 362364ced4..d9a3d60d00 100644 --- a/include/keyboard_protocol.h +++ b/include/keyboard_protocol.h @@ -39,7 +39,9 @@ void keyboard_update_button(enum keyboard_button_type button, int is_pressed); /* MKBP protocol takes the whole keyboard matrix, and does not care about * individual key presses. */ -static inline void keyboard_state_changed(int row, int col, int is_pressed) {} +static inline void keyboard_state_changed(int row, int col, int is_pressed) +{ +} #else /** * Called by keyboard scan code once any key state change (after de-bounce), @@ -60,7 +62,7 @@ int board_has_keyboard_backlight(void); * to change KEYBOARD_ROW_REFRESH accordingly so that recovery mode can work on * the EC side of things (also see related CONFIG_KEYBOARD_REFRESH_ROW3) */ -__override_proto -const struct ec_response_keybd_config *board_vivaldi_keybd_config(void); +__override_proto const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void); -#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */ +#endif /* __CROS_EC_KEYBOARD_PROTOCOL_H */ -- cgit v1.2.1 From 1c6f1775f88d9fa100bbe645fb85a58e85460388 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:18 -0600 Subject: board/corori/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0b85dd23a00143d4961b7ff9165f5bc6bed62660 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728182 Reviewed-by: Jeremy Bettis --- board/corori/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/corori/usb_pd_policy.c b/board/corori/usb_pd_policy.c index fd9018a3f0..98b770be8f 100644 --- a/board/corori/usb_pd_policy.c +++ b/board/corori/usb_pd_policy.c @@ -10,8 +10,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 6beb3061b0d54a599067b5587c646a5fa0ec1e22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:15 -0600 Subject: board/gelarshie/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I805f79b0364f0b5cbb06fe1497d3e6e381fc28f5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728394 Reviewed-by: Jeremy Bettis --- board/gelarshie/board.h | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/board/gelarshie/board.h b/board/gelarshie/board.h index 45b8c42dcc..56777d12c6 100644 --- a/board/gelarshie/board.h +++ b/board/gelarshie/board.h @@ -12,7 +12,7 @@ /* On-body detection */ #define CONFIG_BODY_DETECTION -#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL +#define CONFIG_BODY_DETECTION_SENSOR LID_ACCEL #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */ #define CONFIG_GESTURE_DETECTION #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR) @@ -21,7 +21,7 @@ #define CONFIG_BUTTON_TRIGGERED_RECOVERY /* Internal SPI flash on NPCX7 */ -#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ +#define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Switchcap */ #define CONFIG_LN9310 @@ -37,7 +37,7 @@ #undef CONFIG_CMD_TASK_RESET /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_FUEL_GAUGE #define CONFIG_BATTERY_VENDOR_PARAM @@ -103,10 +103,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum pwm_channel { - PWM_CH_DISPLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_DISPLIGHT = 0, PWM_CH_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 5dfb4104c21c3e8f8676c32adce26bd6b7d1a9f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:35:30 -0600 Subject: zephyr/shim/include/linker.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e165d17eed6880d2f840b71b84896cd51ac3190 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730829 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/linker.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/shim/include/linker.h b/zephyr/shim/include/linker.h index 335f4f0f19..e2d75b2a7c 100644 --- a/zephyr/shim/include/linker.h +++ b/zephyr/shim/include/linker.h @@ -7,6 +7,6 @@ #define __CROS_EC_LINKER_H /* Put the start of shared memory after all allocated RAM symbols */ -#define __shared_mem_buf _image_ram_end +#define __shared_mem_buf _image_ram_end #endif -- cgit v1.2.1 From 004506b89138b58b3970a5ec25672c8052fbf4dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:50 -0600 Subject: driver/ppc/rt1739.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b685b68ae363ff05a56cf152b1ed7e53be3a38c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730035 Reviewed-by: Jeremy Bettis --- driver/ppc/rt1739.h | 208 ++++++++++++++++++++++++++-------------------------- 1 file changed, 104 insertions(+), 104 deletions(-) diff --git a/driver/ppc/rt1739.h b/driver/ppc/rt1739.h index 2f9b196011..951b69a350 100644 --- a/driver/ppc/rt1739.h +++ b/driver/ppc/rt1739.h @@ -16,110 +16,110 @@ #define RT1739_ADDR3_FLAGS 0x72 #define RT1739_ADDR4_FLAGS 0x73 -#define RT1739_REG_DEVICE_ID0 0x02 -#define RT1739_DEVICE_ID_ES1 0x11 -#define RT1739_DEVICE_ID_ES2 0x12 - -#define RT1739_REG_SW_RESET 0x04 -#define RT1739_SW_RESET BIT(0) - -#define RT1739_REG_INT_MASK4 0x0C -#define RT1739_FRS_RX_MASK BIT(4) - -#define RT1739_REG_INT_MASK5 0x0D -#define RT1739_BC12_SNK_DONE_MASK BIT(0) - -#define RT1739_REG_INT_EVENT4 0x14 - -#define RT1739_REG_INT_EVENT5 0x15 -#define RT1739_BC12_SNK_DONE_INT BIT(0) - -#define RT1739_REG_INT_STS4 0x1C -#define RT1739_VBUS_VALID BIT(2) -#define RT1739_VBUS_PRESENT BIT(0) - -#define RT1739_REG_SYS_CTRL 0x20 -#define RT1739_OT_EN BIT(4) -#define RT1739_SHUTDOWN_OFF BIT(0) - -#define RT1739_REG_VBUS_SWITCH_CTRL 0x21 -#define RT1739_LV_SRC_EN BIT(2) -#define RT1739_HV_SRC_EN BIT(1) -#define RT1739_HV_SNK_EN BIT(0) - -#define RT1739_REG_VBUS_CTRL1 0x23 -#define RT1739_HVLV_SCP_EN BIT(1) -#define RT1739_HVLV_OCRC_EN BIT(0) - -#define RT1739_REG_VBUS_OV_SETTING 0x24 - -#define RT1739_VBUS_OVP_SEL_SHIFT 0 -#define RT1739_VIN_HV_OVP_SEL_SHIFT 4 -#define RT1739_OVP_SEL_6_0V 0 -#define RT1739_OVP_SEL_6_8V 1 -#define RT1739_OVP_SEL_10_0V 2 -#define RT1739_OVP_SEL_11_5V 3 -#define RT1739_OVP_SEL_14_0V 4 -#define RT1739_OVP_SEL_17_0V 5 -#define RT1739_OVP_SEL_23_0V 6 - -#define RT1739_REG_VBUS_OC_SETTING 0x25 - -#define RT1739_LV_SRC_OCP_SHIFT 4 -#define RT1739_LV_SRC_OCP_SEL_1_25A (0 << RT1739_LV_SRC_OCP_SHIFT) -#define RT1739_LV_SRC_OCP_SEL_1_75A (1 << RT1739_LV_SRC_OCP_SHIFT) -#define RT1739_LV_SRC_OCP_SEL_2_25A (2 << RT1739_LV_SRC_OCP_SHIFT) -#define RT1739_LV_SRC_OCP_SEL_3_3A (3 << RT1739_LV_SRC_OCP_SHIFT) - -#define RT1739_HV_SINK_OCP_SHIFT 0 -#define RT1739_HV_SINK_OCP_SEL_1_25A (0 << RT1739_HV_SINK_OCP_SHIFT) -#define RT1739_HV_SINK_OCP_SEL_1_75A (1 << RT1739_HV_SINK_OCP_SHIFT) -#define RT1739_HV_SINK_OCP_SEL_3_3A (2 << RT1739_HV_SINK_OCP_SHIFT) -#define RT1739_HV_SINK_OCP_SEL_5_5A (3 << RT1739_HV_SINK_OCP_SHIFT) - -#define RT1739_VBUS_FAULT_DIS 0x26 -#define RT1739_OVP_DISVBUS_EN BIT(6) -#define RT1739_UVLO_DISVBUS_EN BIT(5) -#define RT1739_SRCP_DISVBUS_EN BIT(4) -#define RT1739_RCP_DISVBUS_EN BIT(3) -#define RT1739_SCP_DISVBUS_EN BIT(2) -#define RT1739_OCPS_DISVBUS_EN BIT(1) -#define RT1739_OCP_DISVBUS_EN BIT(0) - -#define RT1739_REG_VBUS_DET_EN 0x27 -#define RT1739_VBUS_SAFE5V_EN BIT(2) -#define RT1739_VBUS_SAFE0V_EN BIT(1) -#define RT1739_VBUS_PRESENT_EN BIT(0) - -#define RT1739_REG_CC_FRS_CTRL1 0x2D -#define RT1739_FRS_RX_EN BIT(1) - -#define RT1739_REG_VCONN_CTRL1 0x31 -#define RT1739_VCONN_ORIENT BIT(1) -#define RT1739_VCONN_EN BIT(0) - -#define RT1739_VCONN_ORIENT_CC1 MASK_SET -#define RT1739_VCONN_ORIENT_CC2 MASK_CLR - -#define RT1739_REG_VCONN_CTRL3 0x33 -#define RT1739_VCONN_CLIMIT_EN BIT(0) - -#define RT1739_REG_SBU_CTRL_01 0x38 -#define RT1739_SBUSW_MUX_SEL BIT(4) -#define RT1739_DM_SWEN BIT(1) -#define RT1739_DP_SWEN BIT(0) - -#define RT1739_REG_BC12_SNK_FUNC 0x40 -#define RT1739_BC12_SNK_EN BIT(7) - -#define RT1739_REG_BC12_STAT 0x41 -#define RT1739_PORT_STAT_MASK 0x0F -#define RT1739_PORT_STAT_SDP 0x0D -#define RT1739_PORT_STAT_CDP 0x0E -#define RT1739_PORT_STAT_DCP 0x0F - -#define RT1739_REG_SYS_CTRL1 0x60 -#define RT1739_OSC640K_FORCE_EN BIT(3) +#define RT1739_REG_DEVICE_ID0 0x02 +#define RT1739_DEVICE_ID_ES1 0x11 +#define RT1739_DEVICE_ID_ES2 0x12 + +#define RT1739_REG_SW_RESET 0x04 +#define RT1739_SW_RESET BIT(0) + +#define RT1739_REG_INT_MASK4 0x0C +#define RT1739_FRS_RX_MASK BIT(4) + +#define RT1739_REG_INT_MASK5 0x0D +#define RT1739_BC12_SNK_DONE_MASK BIT(0) + +#define RT1739_REG_INT_EVENT4 0x14 + +#define RT1739_REG_INT_EVENT5 0x15 +#define RT1739_BC12_SNK_DONE_INT BIT(0) + +#define RT1739_REG_INT_STS4 0x1C +#define RT1739_VBUS_VALID BIT(2) +#define RT1739_VBUS_PRESENT BIT(0) + +#define RT1739_REG_SYS_CTRL 0x20 +#define RT1739_OT_EN BIT(4) +#define RT1739_SHUTDOWN_OFF BIT(0) + +#define RT1739_REG_VBUS_SWITCH_CTRL 0x21 +#define RT1739_LV_SRC_EN BIT(2) +#define RT1739_HV_SRC_EN BIT(1) +#define RT1739_HV_SNK_EN BIT(0) + +#define RT1739_REG_VBUS_CTRL1 0x23 +#define RT1739_HVLV_SCP_EN BIT(1) +#define RT1739_HVLV_OCRC_EN BIT(0) + +#define RT1739_REG_VBUS_OV_SETTING 0x24 + +#define RT1739_VBUS_OVP_SEL_SHIFT 0 +#define RT1739_VIN_HV_OVP_SEL_SHIFT 4 +#define RT1739_OVP_SEL_6_0V 0 +#define RT1739_OVP_SEL_6_8V 1 +#define RT1739_OVP_SEL_10_0V 2 +#define RT1739_OVP_SEL_11_5V 3 +#define RT1739_OVP_SEL_14_0V 4 +#define RT1739_OVP_SEL_17_0V 5 +#define RT1739_OVP_SEL_23_0V 6 + +#define RT1739_REG_VBUS_OC_SETTING 0x25 + +#define RT1739_LV_SRC_OCP_SHIFT 4 +#define RT1739_LV_SRC_OCP_SEL_1_25A (0 << RT1739_LV_SRC_OCP_SHIFT) +#define RT1739_LV_SRC_OCP_SEL_1_75A (1 << RT1739_LV_SRC_OCP_SHIFT) +#define RT1739_LV_SRC_OCP_SEL_2_25A (2 << RT1739_LV_SRC_OCP_SHIFT) +#define RT1739_LV_SRC_OCP_SEL_3_3A (3 << RT1739_LV_SRC_OCP_SHIFT) + +#define RT1739_HV_SINK_OCP_SHIFT 0 +#define RT1739_HV_SINK_OCP_SEL_1_25A (0 << RT1739_HV_SINK_OCP_SHIFT) +#define RT1739_HV_SINK_OCP_SEL_1_75A (1 << RT1739_HV_SINK_OCP_SHIFT) +#define RT1739_HV_SINK_OCP_SEL_3_3A (2 << RT1739_HV_SINK_OCP_SHIFT) +#define RT1739_HV_SINK_OCP_SEL_5_5A (3 << RT1739_HV_SINK_OCP_SHIFT) + +#define RT1739_VBUS_FAULT_DIS 0x26 +#define RT1739_OVP_DISVBUS_EN BIT(6) +#define RT1739_UVLO_DISVBUS_EN BIT(5) +#define RT1739_SRCP_DISVBUS_EN BIT(4) +#define RT1739_RCP_DISVBUS_EN BIT(3) +#define RT1739_SCP_DISVBUS_EN BIT(2) +#define RT1739_OCPS_DISVBUS_EN BIT(1) +#define RT1739_OCP_DISVBUS_EN BIT(0) + +#define RT1739_REG_VBUS_DET_EN 0x27 +#define RT1739_VBUS_SAFE5V_EN BIT(2) +#define RT1739_VBUS_SAFE0V_EN BIT(1) +#define RT1739_VBUS_PRESENT_EN BIT(0) + +#define RT1739_REG_CC_FRS_CTRL1 0x2D +#define RT1739_FRS_RX_EN BIT(1) + +#define RT1739_REG_VCONN_CTRL1 0x31 +#define RT1739_VCONN_ORIENT BIT(1) +#define RT1739_VCONN_EN BIT(0) + +#define RT1739_VCONN_ORIENT_CC1 MASK_SET +#define RT1739_VCONN_ORIENT_CC2 MASK_CLR + +#define RT1739_REG_VCONN_CTRL3 0x33 +#define RT1739_VCONN_CLIMIT_EN BIT(0) + +#define RT1739_REG_SBU_CTRL_01 0x38 +#define RT1739_SBUSW_MUX_SEL BIT(4) +#define RT1739_DM_SWEN BIT(1) +#define RT1739_DP_SWEN BIT(0) + +#define RT1739_REG_BC12_SNK_FUNC 0x40 +#define RT1739_BC12_SNK_EN BIT(7) + +#define RT1739_REG_BC12_STAT 0x41 +#define RT1739_PORT_STAT_MASK 0x0F +#define RT1739_PORT_STAT_SDP 0x0D +#define RT1739_PORT_STAT_CDP 0x0E +#define RT1739_PORT_STAT_DCP 0x0F + +#define RT1739_REG_SYS_CTRL1 0x60 +#define RT1739_OSC640K_FORCE_EN BIT(3) extern const struct ppc_drv rt1739_ppc_drv; extern const struct bc12_drv rt1739_bc12_drv; -- cgit v1.2.1 From e0964fc123afaa32703fa5bbf03c43198d98d7c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:02 -0600 Subject: board/cherry/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I75d47f25cd2fcf46271513ed26fe0c741a01042b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728119 Reviewed-by: Jeremy Bettis --- board/cherry/board.c | 49 ++++++++++++++++++++----------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/board/cherry/board.c b/board/cherry/board.c index 8160dafa62..d343f0d69e 100644 --- a/board/cherry/board.c +++ b/board/cherry/board.c @@ -23,8 +23,8 @@ #include "system.h" #include "usb_mux.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Sensor */ static struct mutex g_base_mutex; @@ -35,17 +35,13 @@ static struct kionix_accel_data g_kx022_data; static struct accelgyro_saved_data_t g_bma422_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -201,8 +197,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* USB Mux */ -static int board_ps8762_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8762_mux_set(const struct usb_mux *me, mux_state_t mux_state) { /* Make sure the PS8802 is awake */ RETURN_ERROR(ps8802_i2c_wake(me)); @@ -210,21 +205,18 @@ static int board_ps8762_mux_set(const struct usb_mux *me, /* USB specific config */ if (mux_state & USB_PD_MUX_USB_ENABLED) { /* Boost the USB gain */ - RETURN_ERROR(ps8802_i2c_field_update16(me, - PS8802_REG_PAGE2, - PS8802_REG2_USB_SSEQ_LEVEL, - PS8802_USBEQ_LEVEL_UP_MASK, - PS8802_USBEQ_LEVEL_UP_12DB)); + RETURN_ERROR(ps8802_i2c_field_update16( + me, PS8802_REG_PAGE2, PS8802_REG2_USB_SSEQ_LEVEL, + PS8802_USBEQ_LEVEL_UP_MASK, + PS8802_USBEQ_LEVEL_UP_12DB)); } /* DP specific config */ if (mux_state & USB_PD_MUX_DP_ENABLED) { /* Boost the DP gain */ - RETURN_ERROR(ps8802_i2c_field_update8(me, - PS8802_REG_PAGE2, - PS8802_REG2_DPEQ_LEVEL, - PS8802_DPEQ_LEVEL_UP_MASK, - PS8802_DPEQ_LEVEL_UP_12DB)); + RETURN_ERROR(ps8802_i2c_field_update8( + me, PS8802_REG_PAGE2, PS8802_REG2_DPEQ_LEVEL, + PS8802_DPEQ_LEVEL_UP_MASK, PS8802_DPEQ_LEVEL_UP_12DB)); } return EC_SUCCESS; @@ -232,11 +224,10 @@ static int board_ps8762_mux_set(const struct usb_mux *me, static int board_ps8762_mux_init(const struct usb_mux *me) { - return ps8802_i2c_field_update8( - me, PS8802_REG_PAGE1, - PS8802_REG_DCIRX, - PS8802_AUTO_DCI_MODE_DISABLE | PS8802_FORCE_DCI_MODE, - PS8802_AUTO_DCI_MODE_DISABLE); + return ps8802_i2c_field_update8(me, PS8802_REG_PAGE1, PS8802_REG_DCIRX, + PS8802_AUTO_DCI_MODE_DISABLE | + PS8802_FORCE_DCI_MODE, + PS8802_AUTO_DCI_MODE_DISABLE); } static int board_anx3443_mux_set(const struct usb_mux *me, -- cgit v1.2.1 From 4683a715a7482b86640ce88637dc9994ef895e41 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:17 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I71637b6d094e66b9ced56de7becbe2b70521f0f4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730943 Reviewed-by: Jeremy Bettis --- .../drivers/src/integration/usbc/usb_pd_ctrl_msg.c | 32 ++++++++++------------ 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c index a049b92ccc..a68afd85d2 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_ctrl_msg.c @@ -41,10 +41,10 @@ struct usb_pd_ctrl_msg_test_source_fixture { struct usb_pd_ctrl_msg_test_fixture fixture; }; -static void tcpci_drp_emul_connect_partner( - struct tcpci_partner_data *partner_emul, - const struct emul *tcpci_emul, - const struct emul *charger_emul) +static void +tcpci_drp_emul_connect_partner(struct tcpci_partner_data *partner_emul, + const struct emul *tcpci_emul, + const struct emul *charger_emul) { /* * TODO(b/221439302) Updating the TCPCI emulator registers, updating the @@ -120,15 +120,13 @@ static void usb_pd_ctrl_msg_before(void *data) /* Initialized DRP */ tcpci_partner_init(&fixture->partner_emul, PD_REV20); - fixture->partner_emul.extensions = - tcpci_drp_emul_init(&fixture->drp_ext, &fixture->partner_emul, - fixture->drp_partner_pd_role, - tcpci_src_emul_init(&fixture->src_ext, - &fixture->partner_emul, - NULL), - tcpci_snk_emul_init(&fixture->snk_ext, - &fixture->partner_emul, - NULL)); + fixture->partner_emul.extensions = tcpci_drp_emul_init( + &fixture->drp_ext, &fixture->partner_emul, + fixture->drp_partner_pd_role, + tcpci_src_emul_init(&fixture->src_ext, &fixture->partner_emul, + NULL), + tcpci_snk_emul_init(&fixture->snk_ext, &fixture->partner_emul, + NULL)); /* Add additional Sink PDO to partner to verify * PE_DR_SNK_Get_Sink_Cap/PE_SRC_Get_Sink_Cap (these are shared PE * states) state was reached @@ -360,8 +358,8 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_mode2) struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; uint32_t bdo = BDO(BDO_MODE_CARRIER2, 0); - tcpci_partner_send_data_msg(&super_fixture->partner_emul, - PD_DATA_BIST, &bdo, 1, 0); + tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST, + &bdo, 1, 0); pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX); k_sleep(K_MSEC(10)); @@ -387,8 +385,8 @@ ZTEST_F(usb_pd_ctrl_msg_test_source, verify_bist_tx_test_data) struct usb_pd_ctrl_msg_test_fixture *super_fixture = &fixture->fixture; uint32_t bdo = BDO(BDO_MODE_TEST_DATA, 0); - tcpci_partner_send_data_msg(&super_fixture->partner_emul, - PD_DATA_BIST, &bdo, 1, 0); + tcpci_partner_send_data_msg(&super_fixture->partner_emul, PD_DATA_BIST, + &bdo, 1, 0); pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_BIST_TX); k_sleep(K_SECONDS(5)); -- cgit v1.2.1 From 31ab75ea62148103737632e68e6db927de5366f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:26 -0600 Subject: board/moonbuggy/pse.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia2e6ef25d4dbadf12b2b6bae230003a95be823b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728699 Reviewed-by: Jeremy Bettis --- board/moonbuggy/pse.c | 81 +++++++++++++++++++++++++-------------------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/board/moonbuggy/pse.c b/board/moonbuggy/pse.c index 84d5048a86..755e3c45e4 100644 --- a/board/moonbuggy/pse.c +++ b/board/moonbuggy/pse.c @@ -18,44 +18,44 @@ #include "timer.h" #include "util.h" -#define LTC4291_I2C_ADDR 0x2C - -#define LTC4291_REG_SUPEVN_COR 0x0B -#define LTC4291_REG_STATPWR 0x10 -#define LTC4291_REG_STATPIN 0x11 -#define LTC4291_REG_OPMD 0x12 -#define LTC4291_REG_DISENA 0x13 -#define LTC4291_REG_DETENA 0x14 -#define LTC4291_REG_DETPB 0x18 -#define LTC4291_REG_PWRPB 0x19 -#define LTC4291_REG_RSTPB 0x1A -#define LTC4291_REG_ID 0x1B -#define LTC4291_REG_DEVID 0x43 -#define LTC4291_REG_HPMD1 0x46 -#define LTC4291_REG_HPMD2 0x4B -#define LTC4291_REG_HPMD3 0x50 -#define LTC4291_REG_HPMD4 0x55 -#define LTC4291_REG_LPWRPB 0x6E - -#define LTC4291_FLD_STATPIN_AUTO BIT(0) -#define LTC4291_FLD_RSTPB_RSTALL BIT(4) - -#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) -#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) -#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) -#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) - -#define LTC4291_OPMD_AUTO 0xFF -#define LTC4291_DISENA_ALL 0x0F -#define LTC4291_DETENA_ALL 0xFF -#define LTC4291_ID 0x64 -#define LTC4291_DEVID 0x38 -#define LTC4291_HPMD_MIN 0x00 -#define LTC4291_HPMD_MAX 0xA8 - -#define LTC4291_PORT_MAX 4 - -#define LTC4291_RESET_DELAY_US (20 * MSEC) +#define LTC4291_I2C_ADDR 0x2C + +#define LTC4291_REG_SUPEVN_COR 0x0B +#define LTC4291_REG_STATPWR 0x10 +#define LTC4291_REG_STATPIN 0x11 +#define LTC4291_REG_OPMD 0x12 +#define LTC4291_REG_DISENA 0x13 +#define LTC4291_REG_DETENA 0x14 +#define LTC4291_REG_DETPB 0x18 +#define LTC4291_REG_PWRPB 0x19 +#define LTC4291_REG_RSTPB 0x1A +#define LTC4291_REG_ID 0x1B +#define LTC4291_REG_DEVID 0x43 +#define LTC4291_REG_HPMD1 0x46 +#define LTC4291_REG_HPMD2 0x4B +#define LTC4291_REG_HPMD3 0x50 +#define LTC4291_REG_HPMD4 0x55 +#define LTC4291_REG_LPWRPB 0x6E + +#define LTC4291_FLD_STATPIN_AUTO BIT(0) +#define LTC4291_FLD_RSTPB_RSTALL BIT(4) + +#define LTC4291_STATPWR_ON_PORT(port) (0x01 << (port)) +#define LTC4291_DETENA_EN_PORT(port) (0x11 << (port)) +#define LTC4291_DETPB_EN_PORT(port) (0x11 << (port)) +#define LTC4291_PWRPB_OFF_PORT(port) (0x10 << (port)) + +#define LTC4291_OPMD_AUTO 0xFF +#define LTC4291_DISENA_ALL 0x0F +#define LTC4291_DETENA_ALL 0xFF +#define LTC4291_ID 0x64 +#define LTC4291_DEVID 0x38 +#define LTC4291_HPMD_MIN 0x00 +#define LTC4291_HPMD_MAX 0xA8 + +#define LTC4291_PORT_MAX 4 + +#define LTC4291_RESET_DELAY_US (20 * MSEC) #define I2C_PSE_READ(reg, data) \ i2c_read8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) @@ -63,7 +63,7 @@ #define I2C_PSE_WRITE(reg, data) \ i2c_write8(I2C_PORT_PSE, LTC4291_I2C_ADDR, LTC4291_REG_##reg, (data)) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static int pse_write_hpmd(int port, int val) { @@ -204,8 +204,7 @@ static int command_pse(int argc, char **argv) else return EC_ERROR_PARAM2; } -DECLARE_CONSOLE_COMMAND(pse, command_pse, - " ", +DECLARE_CONSOLE_COMMAND(pse, command_pse, " ", "Set PSE port power"); static int ec_command_pse_status(int port, uint8_t *status) -- cgit v1.2.1 From 578bf584f4fd2bdc7649df5d40fc3f29dcae51d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:36 -0600 Subject: board/eve/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia107e2dd98e8302cb315e129cb8040356c9991d0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728347 Reviewed-by: Jeremy Bettis --- board/eve/led.c | 101 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 50 insertions(+), 51 deletions(-) diff --git a/board/eve/led.c b/board/eve/led.c index 91a7b24a2b..0d3992347b 100644 --- a/board/eve/led.c +++ b/board/eve/led.c @@ -19,8 +19,8 @@ #include "task.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_PWM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_PWM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #define LED_TICK_TIME (500 * MSEC) #define LED_TICKS_PER_BEAT 1 @@ -37,7 +37,9 @@ * (120, .5, .33). For the transitions of interest only S and I are changed and * they are changed linearly in HSI space. */ -static const uint8_t trans_steps[] = {0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100}; +static const uint8_t trans_steps[] = { + 0, 4, 9, 16, 24, 33, 44, 56, 69, 84, 100 +}; /* List of LED colors used */ enum led_color { @@ -65,11 +67,7 @@ enum led_pattern { LED_NUM_PATTERNS, }; -enum led_side { - LED_LEFT = 0, - LED_RIGHT, - LED_BOTH -}; +enum led_side { LED_LEFT = 0, LED_RIGHT, LED_BOTH }; struct led_info { /* LED pattern manage variables */ @@ -101,8 +99,8 @@ static int double_tap; static int led_charge_side; static struct led_info led[LED_BOTH]; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, EC_LED_ID_RIGHT_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); /* @@ -110,16 +108,18 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * particular pattern never changes from the first phase. */ static const struct led_phase pattern[LED_NUM_PATTERNS] = { - { {LED_OFF, LED_OFF}, {0, 0}, DOUBLE_TAP_TICK_LEN }, - { {LED_GREEN, LED_GREEN}, {0, 0}, DOUBLE_TAP_TICK_LEN }, - { {LED_WHITE, LED_GREEN}, {2, 4}, DOUBLE_TAP_TICK_LEN }, - { {LED_WHITE, LED_WHITE}, {0, 0}, DOUBLE_TAP_TICK_LEN }, - { {LED_WHITE, LED_RED}, {2, 4}, DOUBLE_TAP_TICK_LEN }, - { {LED_RED, LED_RED}, {0, 0}, DOUBLE_TAP_TICK_LEN}, - { {LED_RED, LED_RED_HALF}, {4, 4}, DOUBLE_TAP_TICK_LEN * 2 + - DOUBLE_TAP_TICK_LEN / 2}, - { {LED_RED, LED_OFF}, {1, 5}, DOUBLE_TAP_TICK_LEN * 3 + - DOUBLE_TAP_TICK_LEN / 2}, + { { LED_OFF, LED_OFF }, { 0, 0 }, DOUBLE_TAP_TICK_LEN }, + { { LED_GREEN, LED_GREEN }, { 0, 0 }, DOUBLE_TAP_TICK_LEN }, + { { LED_WHITE, LED_GREEN }, { 2, 4 }, DOUBLE_TAP_TICK_LEN }, + { { LED_WHITE, LED_WHITE }, { 0, 0 }, DOUBLE_TAP_TICK_LEN }, + { { LED_WHITE, LED_RED }, { 2, 4 }, DOUBLE_TAP_TICK_LEN }, + { { LED_RED, LED_RED }, { 0, 0 }, DOUBLE_TAP_TICK_LEN }, + { { LED_RED, LED_RED_HALF }, + { 4, 4 }, + DOUBLE_TAP_TICK_LEN * 2 + DOUBLE_TAP_TICK_LEN / 2 }, + { { LED_RED, LED_OFF }, + { 1, 5 }, + DOUBLE_TAP_TICK_LEN * 3 + DOUBLE_TAP_TICK_LEN / 2 }, }; /* @@ -129,12 +129,9 @@ static const struct led_phase pattern[LED_NUM_PATTERNS] = { #define PWM_CHAN_PER_LED 3 static const uint8_t color_brightness[LED_COLOR_COUNT][PWM_CHAN_PER_LED] = { /* {Red, Green, Blue}, */ - [LED_OFF] = {0, 0, 0}, - [LED_RED] = {80, 0, 0}, - [LED_GREEN] = {0, 80, 0}, - [LED_BLUE] = {0, 0, 80}, - [LED_WHITE] = {100, 100, 100}, - [LED_RED_HALF] = {40, 0, 0}, + [LED_OFF] = { 0, 0, 0 }, [LED_RED] = { 80, 0, 0 }, + [LED_GREEN] = { 0, 80, 0 }, [LED_BLUE] = { 0, 0, 80 }, + [LED_WHITE] = { 100, 100, 100 }, [LED_RED_HALF] = { 40, 0, 0 }, }; /* @@ -153,13 +150,13 @@ struct range_map { #error "LED: PULSE_RED battery level <= BLINK_RED level" #endif static const struct range_map pattern_tbl[] = { - {CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED}, - {5, PULSE_RED}, - {15, SOLID_RED}, - {25, WHITE_RED}, - {75, SOLID_WHITE}, - {95, WHITE_GREEN}, - {100, SOLID_GREEN}, + { CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC - 1, BLINK_RED }, + { 5, PULSE_RED }, + { 15, SOLID_RED }, + { 25, WHITE_RED }, + { 75, SOLID_WHITE }, + { 95, WHITE_GREEN }, + { 100, SOLID_GREEN }, }; enum led_state_change { @@ -323,18 +320,17 @@ static void led_setup_color_change(int old_idx, int new_idx, enum led_side side) */ total_change = ABS(led[side].rgb_current[rgb_index] - led[side].rgb_target[rgb_index]); - delta_per_step = (total_change << LED_FRAC_BITS) - / (ARRAY_SIZE(trans_steps) - 1); + delta_per_step = (total_change << LED_FRAC_BITS) / + (ARRAY_SIZE(trans_steps) - 1); step_value = 0; for (i = 0; i < ARRAY_SIZE(trans_steps); i++) { - led[side].trans[i] = start_lvl + - ((step_value + - (1 << (LED_FRAC_BITS - 1))) - >> LED_FRAC_BITS); + led[side].trans[i] = + start_lvl + + ((step_value + (1 << (LED_FRAC_BITS - 1))) >> + LED_FRAC_BITS); step_value += delta_per_step; } } - } static void led_adjust_color_step(int side) @@ -397,12 +393,10 @@ static void led_change_color(void) /* Will loop here until the color change is complete. */ while (led[LED_LEFT].state != LED_STATE_DONE || led[LED_RIGHT].state != LED_STATE_DONE) { - for (i = 0; i < LED_BOTH; i++) { if (led[i].state != LED_STATE_DONE) /* Move one step in the transition table */ led_adjust_color_step(i); - } msleep(LED_STEP_MSEC); } @@ -427,14 +421,19 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap) */ if (i == led_charge_side || !led[i].tap_tick_count) { led[i].ticks = 0; - led[i].tap_tick_count = tap ? - pattern[pattern_desired[i]].tap_len : 0; + led[i].tap_tick_count = + tap ? pattern[pattern_desired[i]] + .tap_len : + 0; led[i].pattern_sel = pattern_desired[i]; } } /* Determine pattern phase and color for current phase */ phase = led[i].ticks < LED_TICKS_PER_BEAT * - pattern[led[i].pattern_sel].len[0] ? 0 : 1; + pattern[led[i].pattern_sel] + .len[0] ? + 0 : + 1; color = pattern[led[i].pattern_sel].color[phase]; /* If color is changing, then setup the transition. */ if (led[i].color != color) { @@ -458,9 +457,10 @@ static void led_manage_patterns(enum led_pattern *pattern_desired, int tap) * count. */ if (pattern[led[i].pattern_sel].len[0]) - if (++led[i].ticks == LED_TICKS_PER_BEAT * - (pattern[led[i].pattern_sel].len[0] + - pattern[led[i].pattern_sel].len[1])) + if (++led[i].ticks == + LED_TICKS_PER_BEAT * + (pattern[led[i].pattern_sel].len[0] + + pattern[led[i].pattern_sel].len[1])) led[i].ticks = 0; /* If double tap display is active, decrement its counter */ @@ -535,8 +535,8 @@ static void led_select_pattern(enum led_pattern *pattern_desired, int tap) * charging side LED. */ if (chg_state == PWR_STATE_CHARGE_NEAR_FULL || - ((chg_state == PWR_STATE_DISCHARGE_FULL) - && extpower_is_present())) { + ((chg_state == PWR_STATE_DISCHARGE_FULL) && + extpower_is_present())) { new_pattern = SOLID_GREEN; } else if (chg_state == PWR_STATE_CHARGE) { new_pattern = SOLID_WHITE; @@ -586,7 +586,6 @@ static void led_init(void) led[i].tap_tick_count = 0; led[i].state = LED_STATE_DONE; } - } void led_task(void *u) -- cgit v1.2.1 From d033dbbc3f43e8b88dfec6116c66e077c7d26dc2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:37 -0600 Subject: chip/npcx/config_chip-npcx9.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia682f0073df45c19cf608ec13be0f3761b9df0dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729390 Reviewed-by: Jeremy Bettis --- chip/npcx/config_chip-npcx9.h | 69 +++++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 35 deletions(-) diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h index 7f154dbe42..aa47f4cc43 100644 --- a/chip/npcx/config_chip-npcx9.h +++ b/chip/npcx/config_chip-npcx9.h @@ -16,8 +16,8 @@ */ /* Chip ID for all variants */ -#define NPCX996F_CHIP_ID 0x21 -#define NPCX993F_CHIP_ID 0x25 +#define NPCX996F_CHIP_ID 0x21 +#define NPCX993F_CHIP_ID 0x25 /*****************************************************************************/ /* Hardware features */ @@ -25,7 +25,8 @@ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */ -#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \ + */ #define NPCX_UART_FIFO_SUPPORT /* Number of UART modules. */ @@ -55,10 +56,10 @@ /* PSL_OUT optional configuration */ /* Set PSL_OUT mode to pulse mode */ -#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) +#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0) /* set PSL_OUT to open-drain */ -#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) -#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 +#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1) +#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0 /* * Workaound the issue 3.10 in the NPCX99nF errata rev1.2 @@ -75,36 +76,35 @@ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX9M3F) - /* - * 256KB program RAM, but only 512K of Flash. After the boot header is - * added, a 256K image would be too large to fit in either RO or RW - * sections of Flash (each of which is half of it). Because other code - * assumes that image size is a multiple of Flash erase granularity, we - * sacrifice a whole sector. - */ -# define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) - /* program memory base address for Code RAM (0x100C0000 - 256KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE - - /* Override default NPCX_RAM_SIZE because we're excluding a block. */ -# undef NPCX_RAM_SIZE -# define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \ - NPCX_PROGRAM_MEMORY_SIZE + 0x1000) +/* + * 256KB program RAM, but only 512K of Flash. After the boot header is + * added, a 256K image would be too large to fit in either RO or RW + * sections of Flash (each of which is half of it). Because other code + * assumes that image size is a multiple of Flash erase granularity, we + * sacrifice a whole sector. + */ +#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000) +/* program memory base address for Code RAM (0x100C0000 - 256KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE + +/* Override default NPCX_RAM_SIZE because we're excluding a block. */ +#undef NPCX_RAM_SIZE +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000) #elif defined(CHIP_VARIANT_NPCX9M6F) - /* 192KB RAM for FW code */ -# define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) - /* program memory base address for Code RAM (0x100C0000 - 192KB) */ -# define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 -# define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ - /* Two blocks of data RAM - total size is 64KB */ -# define CONFIG_DATA_RAM_SIZE 0x00010000 -# define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for Code RAM (0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* Two blocks of data RAM - total size is 64KB */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE #else -# error "Unsupported chip variant" +#error "Unsupported chip variant" #endif /* Internal spi-flash setting */ @@ -112,5 +112,4 @@ #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */ #define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */ - #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */ -- cgit v1.2.1 From 87d37b600cc107c90f56de143fce6446607551b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:32 -0600 Subject: test/usb_prl_old.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1cf0358e23a0acce58876711a4052cd361cd611d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730568 Reviewed-by: Jeremy Bettis --- test/usb_prl_old.c | 308 +++++++++++++++++++++++++++-------------------------- 1 file changed, 155 insertions(+), 153 deletions(-) diff --git a/test/usb_prl_old.c b/test/usb_prl_old.c index a6ae6acb0e..c0b5d8696d 100644 --- a/test/usb_prl_old.c +++ b/test/usb_prl_old.c @@ -79,25 +79,18 @@ enum usb_rch_state rch_get_state(const int port) } #endif - static uint32_t test_data[] = { - 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, - 0x10111213, 0x14151617, 0x1819a0b0, 0xc0d0e0f0, - 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, - 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, - 0x40414243, 0x44454647, 0x48494a4b, 0x4c4d4e4f, - 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, - 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, - 0x70717273, 0x74757677, 0x78797a7b, 0x7c7d7e7f, - 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, - 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, - 0xa0a1a2a3, 0xa4a5a6a7, 0xa8a9aaab, 0xacadaeaf, - 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, - 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, - 0xd0d1d2d3, 0xd4d5d6d7, 0xd8d9dadb, 0xdcdddedf, - 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, - 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, - 0x11223344 + 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f, 0x10111213, 0x14151617, + 0x1819a0b0, 0xc0d0e0f0, 0x20212223, 0x24252627, 0x28292a2b, 0x2c2d2e2f, + 0x30313233, 0x34353637, 0x38393a3b, 0x3c3d3e3f, 0x40414243, 0x44454647, + 0x48494a4b, 0x4c4d4e4f, 0x50515253, 0x54555657, 0x58595a5b, 0x5c5d5e5f, + 0x60616263, 0x64656667, 0x68696a6b, 0x6c6d6e6f, 0x70717273, 0x74757677, + 0x78797a7b, 0x7c7d7e7f, 0x80818283, 0x84858687, 0x88898a8b, 0x8c8d8e8f, + 0x90919293, 0x94959697, 0x98999a9b, 0x9c9d9e9f, 0xa0a1a2a3, 0xa4a5a6a7, + 0xa8a9aaab, 0xacadaeaf, 0xb0b1b2b3, 0xb4b5b6b7, 0xb8b9babb, 0xbcbdbebf, + 0xc0c1c2c3, 0xc4c5c6c7, 0xc8c9cacb, 0xcccdcecf, 0xd0d1d2d3, 0xd4d5d6d7, + 0xd8d9dadb, 0xdcdddedf, 0xe0e1e2e3, 0xe4e5e6e7, 0xe8e9eaeb, 0xecedeeef, + 0xf0f1f2f3, 0xf4f5f6f7, 0xf8f9fafb, 0xfcfdfeff, 0x11223344 }; void pd_set_suspend(int port, int suspend) @@ -161,14 +154,15 @@ void inc_rx_id(int port) static int verify_goodcrc(int port, int role, int id) { return pd_test_tx_msg_verify_sop(port) && - pd_test_tx_msg_verify_short(port, PD_HEADER(PD_CTRL_GOOD_CRC, - role, role, id, 0, 0, 0)) && - pd_test_tx_msg_verify_crc(port) && - pd_test_tx_msg_verify_eop(port); + pd_test_tx_msg_verify_short(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, + role, id, 0, 0, 0)) && + pd_test_tx_msg_verify_crc(port) && + pd_test_tx_msg_verify_eop(port); } static void simulate_rx_msg(int port, uint16_t header, int cnt, - const uint32_t *data) + const uint32_t *data) { int i; @@ -194,8 +188,10 @@ static void simulate_rx_msg(int port, uint16_t header, int cnt, static void simulate_goodcrc(int port, int role, int id) { - simulate_rx_msg(port, PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, - pd_port[port].rev, 0), 0, NULL); + simulate_rx_msg(port, + PD_HEADER(PD_CTRL_GOOD_CRC, role, role, id, 0, + pd_port[port].rev, 0), + 0, NULL); } static void cycle_through_state_machine(int port, uint32_t num, uint32_t time) @@ -209,19 +205,19 @@ static void cycle_through_state_machine(int port, uint32_t num, uint32_t time) } static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type, - int chunk_num, int len) + int chunk_num, int len) { uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), - get_partner_data_role(port), - pd_port[port].msg_rx_id, - 1, pd_port[port].rev, 1); + get_partner_data_role(port), + pd_port[port].msg_rx_id, 1, + pd_port[port].rev, 1); uint32_t msg = PD_EXT_HEADER(chunk_num, 1, len); simulate_rx_msg(port, header, 1, (const uint32_t *)&msg); task_wait_event(30 * MSEC); if (!verify_goodcrc(port, pd_port[port].data_role, - pd_port[port].msg_rx_id)) + pd_port[port].msg_rx_id)) return 0; return 1; @@ -230,14 +226,15 @@ static int simulate_request_chunk(int port, enum pd_ext_msg_type msg_type, static int simulate_receive_ctrl_msg(int port, enum pd_ctrl_msg_type msg_type) { uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), - get_partner_data_role(port), pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + get_partner_data_role(port), + pd_port[port].msg_rx_id, 0, + pd_port[port].rev, 0); simulate_rx_msg(port, header, 0, NULL); task_wait_event(30 * MSEC); if (!verify_goodcrc(port, pd_port[port].data_role, - pd_port[port].msg_rx_id)) + pd_port[port].msg_rx_id)) return 0; return 1; @@ -265,7 +262,7 @@ static int verify_data_reception(int port, uint16_t header, int len) for (i = 0; i < cnt; i++) { if (i < len) { if (rx_emsg[port].buf[i] != - *((unsigned char *)test_data + i)) + *((unsigned char *)test_data + i)) return 0; } else { if (rx_emsg[port].buf[i] != 0) @@ -312,14 +309,15 @@ static int verify_chunk_data_reception(int port, uint16_t header, int len) } static int simulate_receive_data(int port, enum pd_data_msg_type msg_type, - int len) + int len) { int i; int nw = (len + 3) >> 2; uint8_t td[28]; uint16_t header = PD_HEADER(msg_type, get_partner_power_role(port), - get_partner_data_role(port), pd_port[port].msg_rx_id, - nw, pd_port[port].rev, 0); + get_partner_data_role(port), + pd_port[port].msg_rx_id, nw, + pd_port[port].rev, 0); pd_port[port].mock_pe_error = -1; pd_port[port].mock_pe_message_received = 0; @@ -338,7 +336,7 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type, task_wait_event(30 * MSEC); if (!verify_goodcrc(port, pd_port[port].data_role, - pd_port[port].msg_rx_id)) + pd_port[port].msg_rx_id)) return 0; inc_rx_id(port); @@ -347,7 +345,8 @@ static int simulate_receive_data(int port, enum pd_data_msg_type msg_type, } static int simulate_receive_extended_data(int port, - enum pd_data_msg_type msg_type, int len) + enum pd_data_msg_type msg_type, + int len) { int i; int j; @@ -385,24 +384,25 @@ static int simulate_receive_extended_data(int port, nw = (byte_len + 2 + 3) >> 2; header = PD_HEADER(msg_type, get_partner_power_role(port), - get_partner_data_role(port), pd_port[port].msg_rx_id, - nw, pd_port[port].rev, 1); + get_partner_data_role(port), + pd_port[port].msg_rx_id, nw, + pd_port[port].rev, 1); if (pd_port[port].mock_pe_error >= 0) { ccprintf("Mock pe error (%d) iteration (%d)\n", - pd_port[port].mock_pe_error, j); + pd_port[port].mock_pe_error, j); return 0; } if (IS_ENABLED(CONFIG_USB_PD_EXTENDED_MESSAGES) && - pd_port[port].mock_pe_message_received) { + pd_port[port].mock_pe_message_received) { ccprintf("Mock pe msg received iteration (%d)\n", j); return 0; } if (rx_emsg[port].len != 0) { ccprintf("emsg len (%d) != 0 iteration (%d)\n", - rx_emsg[port].len, j); + rx_emsg[port].len, j); return 0; } @@ -410,7 +410,7 @@ static int simulate_receive_extended_data(int port, cycle_through_state_machine(port, 1, MSEC); if (!verify_goodcrc(port, pd_port[port].data_role, - pd_port[port].msg_rx_id)) { + pd_port[port].msg_rx_id)) { ccprintf("Verify goodcrc bad iteration (%d)\n", j); return 0; } @@ -445,18 +445,17 @@ static int simulate_receive_extended_data(int port, return 0; } - if (!pd_test_tx_msg_verify_short(port, - PD_HEADER(msg_type, - pd_port[port].power_role, - pd_port[port].data_role, - pd_port[port].msg_tx_id, - 1, pd_port[port].rev, 1))) { + if (!pd_test_tx_msg_verify_short( + port, PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, + pd_port[port].msg_tx_id, 1, + pd_port[port].rev, 1))) { ccprintf("Verify msg short bad iteration (%d)\n", j); return 0; } - if (!pd_test_tx_msg_verify_word(port, - PD_EXT_HEADER(chunk_num, 1, 0))) { + if (!pd_test_tx_msg_verify_word(port, PD_EXT_HEADER(chunk_num, + 1, 0))) { ccprintf("Verify msg word bad iteration (%d)\n", j); return 0; } @@ -475,7 +474,7 @@ static int simulate_receive_extended_data(int port, /* Request next chunk packet was good. Send GoodCRC */ simulate_goodcrc(port, get_partner_power_role(port), - pd_port[port].msg_tx_id); + pd_port[port].msg_tx_id); cycle_through_state_machine(port, 1, MSEC); @@ -488,15 +487,16 @@ static int simulate_receive_extended_data(int port, } static int verify_ctrl_msg_transmission(int port, - enum pd_ctrl_msg_type msg_type) + enum pd_ctrl_msg_type msg_type) { if (!pd_test_tx_msg_verify_sop(port)) return 0; - if (!pd_test_tx_msg_verify_short(port, - PD_HEADER(msg_type, pd_port[port].power_role, - pd_port[port].data_role, pd_port[port].msg_tx_id, 0, - pd_port[port].rev, 0))) + if (!pd_test_tx_msg_verify_short( + port, + PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, pd_port[port].msg_tx_id, + 0, pd_port[port].rev, 0))) return 0; if (!pd_test_tx_msg_verify_crc(port)) @@ -508,8 +508,9 @@ static int verify_ctrl_msg_transmission(int port, return 1; } -static int simulate_send_ctrl_msg_request_from_pe(int port, - enum tcpci_msg_type type, enum pd_ctrl_msg_type msg_type) +static int +simulate_send_ctrl_msg_request_from_pe(int port, enum tcpci_msg_type type, + enum pd_ctrl_msg_type msg_type) { pd_port[port].mock_got_soft_reset = 0; pd_port[port].mock_pe_error = -1; @@ -521,7 +522,7 @@ static int simulate_send_ctrl_msg_request_from_pe(int port, } static int verify_data_msg_transmission(int port, - enum pd_data_msg_type msg_type, int len) + enum pd_data_msg_type msg_type, int len) { int i; int num_words = (len + 3) >> 2; @@ -531,10 +532,11 @@ static int verify_data_msg_transmission(int port, if (!pd_test_tx_msg_verify_sop(port)) return 0; - if (!pd_test_tx_msg_verify_short(port, - PD_HEADER(msg_type, pd_port[port].power_role, - pd_port[port].data_role, pd_port[port].msg_tx_id, - num_words, pd_port[port].rev, 0))) + if (!pd_test_tx_msg_verify_short( + port, + PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, pd_port[port].msg_tx_id, + num_words, pd_port[port].rev, 0))) return 0; for (i = 0; i < num_words; i++) { @@ -567,8 +569,9 @@ static int verify_data_msg_transmission(int port, return 1; } -static int simulate_send_data_msg_request_from_pe(int port, - enum tcpci_msg_type type, enum pd_data_msg_type msg_type, int len) +static int +simulate_send_data_msg_request_from_pe(int port, enum tcpci_msg_type type, + enum pd_data_msg_type msg_type, int len) { int i; uint8_t *buf = tx_emsg[port].buf; @@ -590,7 +593,8 @@ static int simulate_send_data_msg_request_from_pe(int port, } static int verify_extended_data_msg_transmission(int port, - enum pd_ext_msg_type msg_type, int len) + enum pd_ext_msg_type msg_type, + int len) { int i; int j; @@ -616,11 +620,11 @@ static int verify_extended_data_msg_transmission(int port, return 0; } - if (!pd_test_tx_msg_verify_short(port, - PD_HEADER(msg_type, pd_port[port].power_role, - pd_port[port].data_role, - pd_port[port].msg_tx_id, - nw, pd_port[port].rev, 1))) { + if (!pd_test_tx_msg_verify_short( + port, PD_HEADER(msg_type, pd_port[port].power_role, + pd_port[port].data_role, + pd_port[port].msg_tx_id, nw, + pd_port[port].rev, 1))) { ccprintf("failed tx short\n"); return 0; } @@ -642,9 +646,9 @@ static int verify_extended_data_msg_transmission(int port, nw = (byte_len + 3) >> 2; for (i = 0; i < nw; i++) { td = *(expected_data + data_offset++) << 0; - td |= *(expected_data + data_offset++) << 8; - td |= *(expected_data + data_offset++) << 16; - td |= *(expected_data + data_offset++) << 24; + td |= *(expected_data + data_offset++) << 8; + td |= *(expected_data + data_offset++) << 16; + td |= *(expected_data + data_offset++) << 24; switch (byte_len) { case 3: @@ -678,7 +682,7 @@ static int verify_extended_data_msg_transmission(int port, /* Send GoodCRC */ simulate_goodcrc(port, get_partner_power_role(port), - pd_port[port].msg_tx_id); + pd_port[port].msg_tx_id); cycle_through_state_machine(port, 1, MSEC); inc_tx_id(port); @@ -690,7 +694,7 @@ static int verify_extended_data_msg_transmission(int port, /* Let state machine settle */ cycle_through_state_machine(port, 10, MSEC); if (!simulate_request_chunk(port, msg_type, - chunk_number_to_send, dsize)) { + chunk_number_to_send, dsize)) { ccprintf("failed request chunk\n"); return 0; } @@ -702,9 +706,9 @@ static int verify_extended_data_msg_transmission(int port, return 1; } -static int simulate_send_extended_data_msg(int port, - enum tcpci_msg_type type, enum pd_ext_msg_type msg_type, - int len) +static int simulate_send_extended_data_msg(int port, enum tcpci_msg_type type, + enum pd_ext_msg_type msg_type, + int len) { int i; uint8_t *buf = tx_emsg[port].buf; @@ -723,8 +727,7 @@ static int simulate_send_extended_data_msg(int port, prl_send_ext_data_msg(port, type, msg_type); cycle_through_state_machine(port, 1, MSEC); - return verify_extended_data_msg_transmission(port, msg_type, - len); + return verify_extended_data_msg_transmission(port, msg_type, len); } uint8_t tc_get_pd_enabled(int port) @@ -753,8 +756,8 @@ enum pd_power_role pd_get_power_role(int port) static enum pd_power_role get_partner_power_role(int port) { - return pd_port[port].power_role == PD_ROLE_SINK ? - PD_ROLE_SOURCE : PD_ROLE_SINK; + return pd_port[port].power_role == PD_ROLE_SINK ? PD_ROLE_SOURCE : + PD_ROLE_SINK; } enum pd_data_role pd_get_data_role(int port) @@ -764,8 +767,8 @@ enum pd_data_role pd_get_data_role(int port) static enum pd_data_role get_partner_data_role(int port) { - return pd_port[port].data_role == PD_ROLE_UFP ? - PD_ROLE_DFP : PD_ROLE_UFP; + return pd_port[port].data_role == PD_ROLE_UFP ? PD_ROLE_DFP : + PD_ROLE_UFP; } enum pd_cable_plug tc_get_cable_plug(int port) @@ -828,14 +831,12 @@ static int test_prl_reset(void) prl_reset_soft(port); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); - TEST_EQ(rch_get_state(port), - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); - TEST_EQ(tch_get_state(port), - TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, "%u"); - TEST_EQ(prl_hr_get_state(port), - PRL_HR_WAIT_FOR_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); + TEST_EQ(tch_get_state(port), TCH_WAIT_FOR_MESSAGE_REQUEST_FROM_PE, + "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_REQUEST, "%u"); enable_prl(port, 0); return EC_SUCCESS; @@ -855,16 +856,17 @@ static int test_send_ctrl_msg(void) task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%u"); - TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, - TCPCI_MSG_SOP, PD_CTRL_ACCEPT), 0, "%d"); + TEST_NE(simulate_send_ctrl_msg_request_from_pe( + port, TCPCI_MSG_SOP, PD_CTRL_ACCEPT), + 0, "%d"); cycle_through_state_machine(port, 1, MSEC); simulate_goodcrc(port, get_partner_power_role(port), - pd_port[port].msg_tx_id); + pd_port[port].msg_tx_id); inc_tx_id(port); /* Let statemachine settle */ @@ -893,16 +895,17 @@ static int test_send_data_msg(void) for (i = 1; i <= 28; i++) { cycle_through_state_machine(port, 1, MSEC); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%u"); - TEST_NE(simulate_send_data_msg_request_from_pe(port, - TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i), 0, "%d"); + TEST_NE(simulate_send_data_msg_request_from_pe( + port, TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, i), + 0, "%d"); cycle_through_state_machine(port, 1, MSEC); simulate_goodcrc(port, get_partner_power_role(port), - pd_port[port].msg_tx_id); + pd_port[port].msg_tx_id); inc_tx_id(port); cycle_through_state_machine(port, 10, MSEC); @@ -929,12 +932,12 @@ static int test_send_data_msg_to_much_data(void) task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); /* Try to send 29-bytes */ - TEST_EQ(simulate_send_data_msg_request_from_pe(port, - TCPCI_MSG_SOP, PD_DATA_SOURCE_CAP, 29), 0, "%d"); + TEST_EQ(simulate_send_data_msg_request_from_pe(port, TCPCI_MSG_SOP, + PD_DATA_SOURCE_CAP, 29), + 0, "%d"); task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(30 * MSEC); @@ -976,12 +979,13 @@ static int test_send_extended_data_msg(void) cycle_through_state_machine(port, 10, MSEC); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%d"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, + "%d"); - TEST_NE(simulate_send_extended_data_msg(port, TCPCI_MSG_SOP, - PD_EXT_MANUFACTURER_INFO, i), - 0, "%d"); + TEST_NE(simulate_send_extended_data_msg( + port, TCPCI_MSG_SOP, PD_EXT_MANUFACTURER_INFO, + i), + 0, "%d"); cycle_through_state_machine(port, 10, MSEC); @@ -1007,8 +1011,8 @@ static int test_receive_soft_reset_msg(void) task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_EQ(rch_get_state(port), - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); pd_port[port].mock_got_soft_reset = 0; pd_port[port].mock_pe_error = -1; @@ -1037,11 +1041,10 @@ static int test_receive_soft_reset_msg(void) static int test_receive_control_msg(void) { int port = PORT0; - int expected_header = PD_HEADER(PD_CTRL_DR_SWAP, - get_partner_power_role(port), - get_partner_data_role(port), - pd_port[port].msg_rx_id, - 0, pd_port[port].rev, 0); + int expected_header = + PD_HEADER(PD_CTRL_DR_SWAP, get_partner_power_role(port), + get_partner_data_role(port), pd_port[port].msg_rx_id, + 0, pd_port[port].rev, 0); enable_prl(port, 1); @@ -1052,8 +1055,8 @@ static int test_receive_control_msg(void) task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_EQ(rch_get_state(port), - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + TEST_EQ(rch_get_state(port), RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, + "%u"); pd_port[port].mock_got_soft_reset = 0; pd_port[port].mock_pe_error = -1; @@ -1093,9 +1096,9 @@ static int test_receive_data_msg(void) task_wait_event(40 * MSEC); TEST_EQ(rch_get_state(port), - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); - TEST_NE(simulate_receive_data(port, - PD_DATA_BATTERY_STATUS, i), 0, "%d"); + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, i), + 0, "%d"); } enable_prl(port, 0); @@ -1119,11 +1122,12 @@ static int test_receive_extended_data_msg(void) task_wait_event(40 * MSEC); TEST_EQ(rch_get_state(port), - RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); + RCH_WAIT_FOR_MESSAGE_FROM_PROTOCOL_LAYER, "%u"); for (len = 29; len <= PD_MAX_EXTENDED_MSG_LEN; len++) { - TEST_NE(simulate_receive_extended_data(port, - PD_DATA_BATTERY_STATUS, len), 0, "%d"); + TEST_NE(simulate_receive_extended_data( + port, PD_DATA_BATTERY_STATUS, len), + 0, "%d"); } } else { /* @@ -1132,13 +1136,14 @@ static int test_receive_extended_data_msg(void) */ task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_NE(simulate_receive_extended_data(port, - PD_DATA_BATTERY_STATUS, 29), 0, "%d"); + TEST_NE(simulate_receive_extended_data( + port, PD_DATA_BATTERY_STATUS, 29), + 0, "%d"); task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_NE(simulate_receive_data(port, - PD_DATA_BATTERY_STATUS, 28), 0, "%d"); + TEST_NE(simulate_receive_data(port, PD_DATA_BATTERY_STATUS, 28), + 0, "%d"); } enable_prl(port, 0); @@ -1159,21 +1164,20 @@ static int test_send_soft_reset_msg(void) task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(40 * MSEC); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); - TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, - TCPCI_MSG_SOP, PD_CTRL_SOFT_RESET), 0, "%d"); + TEST_NE(simulate_send_ctrl_msg_request_from_pe(port, TCPCI_MSG_SOP, + PD_CTRL_SOFT_RESET), + 0, "%d"); task_wake(PD_PORT_TO_TASK_ID(port)); task_wait_event(30 * MSEC); simulate_goodcrc(port, get_partner_power_role(port), - pd_port[port].msg_tx_id); + pd_port[port].msg_tx_id); inc_tx_id(port); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_LAYER_RESET_FOR_TRANSMIT, "%u"); cycle_through_state_machine(port, 3, 10 * MSEC); @@ -1207,19 +1211,18 @@ static int test_pe_execute_hard_reset_msg(void) prl_execute_hard_reset(port); TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u"); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); cycle_through_state_machine(port, 1, 10 * MSEC); - TEST_EQ(prl_hr_get_state(port), - PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PHY_HARD_RESET_COMPLETE, + "%u"); cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET); TEST_NE(pd_port[port].mock_pe_hard_reset_sent, 0, "%d"); - TEST_EQ(prl_hr_get_state(port), - PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); /* Simulate policy engine indicating that it is done hard reset */ prl_hard_reset_complete(port); @@ -1254,19 +1257,18 @@ static int test_phy_execute_hard_reset_msg(void) pd_execute_hard_reset(port); TEST_EQ(prl_hr_get_state(port), PRL_HR_RESET_LAYER, "%u"); - TEST_EQ(prl_tx_get_state(port), - PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); + TEST_EQ(prl_tx_get_state(port), PRL_TX_WAIT_FOR_MESSAGE_REQUEST, "%u"); cycle_through_state_machine(port, 1, 10 * MSEC); - TEST_EQ(prl_hr_get_state(port), - PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); cycle_through_state_machine(port, 2, PD_T_PS_HARD_RESET); TEST_NE(pd_port[port].mock_pe_got_hard_reset, 0, "%d"); - TEST_EQ(prl_hr_get_state(port), - PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, "%u"); + TEST_EQ(prl_hr_get_state(port), PRL_HR_WAIT_FOR_PE_HARD_RESET_COMPLETE, + "%u"); /* Simulate policy engine indicating that it is done hard reset */ prl_hard_reset_complete(port); -- cgit v1.2.1 From be4037f8f683dd028292fc36a1682ffaf1692197 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:50 -0600 Subject: zephyr/subsys/ap_pwrseq/power_signals.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I165fbbfa13d29de6f5d30a16735b689dd3adde1a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730951 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/power_signals.c | 64 ++++++++++++++++----------------- 1 file changed, 30 insertions(+), 34 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/power_signals.c b/zephyr/subsys/ap_pwrseq/power_signals.c index 135a0d9ac1..d9f8041212 100644 --- a/zephyr/subsys/ap_pwrseq/power_signals.c +++ b/zephyr/subsys/ap_pwrseq/power_signals.c @@ -18,7 +18,7 @@ LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); #if DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq) BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(intel_ap_pwrseq) == 1, - "Only one node for intel_ap_pwrseq is allowed"); + "Only one node for intel_ap_pwrseq is allowed"); #endif BUILD_ASSERT(POWER_SIGNAL_COUNT <= 32, "Too many power signals"); @@ -41,49 +41,46 @@ struct ps_config { #define TAG_PWR_ENUM(tag, name) DT_CAT(tag, name) -#define PWR_ENUM(id, tag) \ - TAG_PWR_ENUM(tag, PWR_SIGNAL_ENUM(id)) +#define PWR_ENUM(id, tag) TAG_PWR_ENUM(tag, PWR_SIGNAL_ENUM(id)) -#define DBGNAME(id) \ - "(" DT_PROP(id, enum_name) ") " \ - DT_PROP(id, dbg_label) +#define DBGNAME(id) "(" DT_PROP(id, enum_name) ") " DT_PROP(id, dbg_label) -#define GEN_PS_ENTRY(id, src, tag) \ -{ \ - .debug_name = DBGNAME(id), \ - .source = src, \ - .src_enum = PWR_ENUM(id, tag), \ -}, - -#define GEN_PS_ENTRY_NO_ENUM(id, src) \ -{ \ - .debug_name = DBGNAME(id), \ - .source = src, \ -}, +#define GEN_PS_ENTRY(id, src, tag) \ + { \ + .debug_name = DBGNAME(id), \ + .source = src, \ + .src_enum = PWR_ENUM(id, tag), \ + }, +#define GEN_PS_ENTRY_NO_ENUM(id, src) \ + { \ + .debug_name = DBGNAME(id), \ + .source = src, \ + }, /* * Generate the power signal configuration array. */ static const struct ps_config sig_config[] = { -DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_gpio, GEN_PS_ENTRY, - PWR_SIG_SRC_GPIO, PWR_SIG_TAG_GPIO) -DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_vw, GEN_PS_ENTRY, - PWR_SIG_SRC_VW, PWR_SIG_TAG_VW) -DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_external, GEN_PS_ENTRY_NO_ENUM, - PWR_SIG_SRC_EXT) -DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_adc, GEN_PS_ENTRY, - PWR_SIG_SRC_ADC, PWR_SIG_TAG_ADC) + DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_gpio, GEN_PS_ENTRY, + PWR_SIG_SRC_GPIO, PWR_SIG_TAG_GPIO) + DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_vw, GEN_PS_ENTRY, + PWR_SIG_SRC_VW, PWR_SIG_TAG_VW) + DT_FOREACH_STATUS_OKAY_VARGS(intel_ap_pwrseq_external, + GEN_PS_ENTRY_NO_ENUM, + PWR_SIG_SRC_EXT) + DT_FOREACH_STATUS_OKAY_VARGS( + intel_ap_pwrseq_adc, GEN_PS_ENTRY, + PWR_SIG_SRC_ADC, PWR_SIG_TAG_ADC) }; -#define PWR_SIGNAL_POLLED(id) PWR_SIGNAL_ENUM(id), +#define PWR_SIGNAL_POLLED(id) PWR_SIGNAL_ENUM(id), /* * List of power signals that need to be polled. */ -static const uint8_t polled_signals[] = { -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, PWR_SIGNAL_POLLED) -}; +static const uint8_t polled_signals[] = { DT_FOREACH_STATUS_OKAY( + intel_ap_pwrseq_external, PWR_SIGNAL_POLLED) }; /* * Bitmasks of power signals. A previous copy is held so that @@ -112,7 +109,7 @@ static inline void check_debug(enum power_signal signal) */ if ((CONFIG_AP_PWRSEQ_LOG_LEVEL >= LOG_LEVEL_INF) && (debug_signals & POWER_SIGNAL_MASK(signal))) { - bool value = atomic_test_bit(&power_signals, signal); + bool value = atomic_test_bit(&power_signals, signal); if (value != atomic_test_bit(&prev_power_signals, signal)) { LOG_INF("%s -> %d", power_signal_name(signal), value); @@ -140,8 +137,7 @@ void power_signal_interrupt(enum power_signal signal, int value) } int power_wait_mask_signals_timeout(power_signal_mask_t mask, - power_signal_mask_t want, - int timeout) + power_signal_mask_t want, int timeout) { if (mask == 0) { return 0; @@ -166,7 +162,7 @@ int power_signal_get(enum power_signal signal) cp = &sig_config[signal]; switch (cp->source) { default: - return -EINVAL; /* should never happen */ + return -EINVAL; /* should never happen */ #if HAS_GPIO_SIGNALS case PWR_SIG_SRC_GPIO: -- cgit v1.2.1 From 925b0821d7dbe5c600cc93f68081af7d334a1d1e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:42 -0600 Subject: board/banshee/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If598465217eecccaae24e159147a9d55098276b6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728021 Reviewed-by: Jeremy Bettis --- board/banshee/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/banshee/fw_config.c b/board/banshee/fw_config.c index 2ce200cc4f..dba01cf28d 100644 --- a/board/banshee/fw_config.c +++ b/board/banshee/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union banshee_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 597b2cdf056542647c0e6e4c03a444ffe0c8e109 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:51:07 -0600 Subject: driver/led/is31fl3733b.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id1c1ed3d2e59afbfe4d159ba353cd88df491a42d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729995 Reviewed-by: Jeremy Bettis --- driver/led/is31fl3733b.c | 114 +++++++++++++++++++++++------------------------ 1 file changed, 55 insertions(+), 59 deletions(-) diff --git a/driver/led/is31fl3733b.c b/driver/led/is31fl3733b.c index 5b1df890f1..64e76f672f 100644 --- a/driver/led/is31fl3733b.c +++ b/driver/led/is31fl3733b.c @@ -14,63 +14,62 @@ #define CPRINTF(fmt, args...) cprintf(CC_RGBKBD, "RGBKBD: " fmt, ##args) #define CPRINTS(fmt, args...) cprints(CC_RGBKBD, "RGBKBD: " fmt, ##args) - /* This depends on ADDR1 and ADDR2. (GND, GND) = 0x50. */ -#define IS31FL3733B_ADDR_FLAGS 0x50 +#define IS31FL3733B_ADDR_FLAGS 0x50 -#define IS31FL3733B_ROW_SIZE 16 -#define IS31FL3733B_COL_SIZE 4 -#define IS31FL3733B_GRID_SIZE (IS31FL3733B_COL_SIZE * IS31FL3733B_ROW_SIZE) -#define IS31FL3733B_BUF_SIZE (SIZE_OF_RGB * IS31FL3733B_GRID_SIZE) +#define IS31FL3733B_ROW_SIZE 16 +#define IS31FL3733B_COL_SIZE 4 +#define IS31FL3733B_GRID_SIZE (IS31FL3733B_COL_SIZE * IS31FL3733B_ROW_SIZE) +#define IS31FL3733B_BUF_SIZE (SIZE_OF_RGB * IS31FL3733B_GRID_SIZE) /* IS31FL3733B registers */ -#define IS31FL3733B_REG_COMMAND 0xFD -#define IS31FL3733B_REG_COMMAND_WRITE_LOCK 0xFE -#define IS31FL3733B_REG_INT_MASK 0xF0 -#define IS31FL3733B_REG_INT_STATUS 0xF1 +#define IS31FL3733B_REG_COMMAND 0xFD +#define IS31FL3733B_REG_COMMAND_WRITE_LOCK 0xFE +#define IS31FL3733B_REG_INT_MASK 0xF0 +#define IS31FL3733B_REG_INT_STATUS 0xF1 -#define IS31FL3733B_PAGE_CTRL 0x00 -#define IS31FL3733B_PAGE_PWM 0x01 -#define IS31FL3733B_PAGE_AUTO 0x02 -#define IS31FL3733B_PAGE_FUNC 0x03 +#define IS31FL3733B_PAGE_CTRL 0x00 +#define IS31FL3733B_PAGE_PWM 0x01 +#define IS31FL3733B_PAGE_AUTO 0x02 +#define IS31FL3733B_PAGE_FUNC 0x03 /* FEh Command Register Write Lock */ -#define IS31FL3733B_WRITE_DISABLE 0x00 -#define IS31FL3733B_WRITE_ENABLE 0xC5 - -#define IS31FL3733B_INT_MASK_IAC BIT(3) -#define IS31FL3733B_INT_MASK_IAB BIT(2) -#define IS31FL3733B_INT_MASK_IS BIT(1) -#define IS31FL3733B_INT_MASK_IO BIT(0) -#define IS31FL3733B_INT_STATUS_ABM3 BIT(4) -#define IS31FL3733B_INT_STATUS_ABM2 BIT(3) -#define IS31FL3733B_INT_STATUS_ABM1 BIT(2) -#define IS31FL3733B_INT_STATUS_SB BIT(1) -#define IS31FL3733B_INT_STATUS_OB BIT(0) - -#define IS31FL3733B_FUNC_CFG 0x00 -#define IS31FL3733B_FUNC_GCC 0x01 -#define IS31FL3733B_FUNC_ABM1_1 0x02 -#define IS31FL3733B_FUNC_ABM1_2 0x03 -#define IS31FL3733B_FUNC_ABM1_3 0x04 -#define IS31FL3733B_FUNC_ABM1_4 0x05 -#define IS31FL3733B_FUNC_ABM2_1 0x06 -#define IS31FL3733B_FUNC_ABM2_2 0x07 -#define IS31FL3733B_FUNC_ABM2_3 0x08 -#define IS31FL3733B_FUNC_ABM2_4 0x09 -#define IS31FL3733B_FUNC_ABM3_1 0x0a -#define IS31FL3733B_FUNC_ABM3_2 0x0b -#define IS31FL3733B_FUNC_ABM3_3 0x0c -#define IS31FL3733B_FUNC_ABM3_4 0x0d -#define IS31FL3733B_FUNC_TUR 0x0e -#define IS31FL3733B_FUNC_SW_PU 0x0f -#define IS31FL3733B_FUNC_CS_PD 0x10 -#define IS31FL3733B_FUNC_RST 0x11 +#define IS31FL3733B_WRITE_DISABLE 0x00 +#define IS31FL3733B_WRITE_ENABLE 0xC5 + +#define IS31FL3733B_INT_MASK_IAC BIT(3) +#define IS31FL3733B_INT_MASK_IAB BIT(2) +#define IS31FL3733B_INT_MASK_IS BIT(1) +#define IS31FL3733B_INT_MASK_IO BIT(0) +#define IS31FL3733B_INT_STATUS_ABM3 BIT(4) +#define IS31FL3733B_INT_STATUS_ABM2 BIT(3) +#define IS31FL3733B_INT_STATUS_ABM1 BIT(2) +#define IS31FL3733B_INT_STATUS_SB BIT(1) +#define IS31FL3733B_INT_STATUS_OB BIT(0) + +#define IS31FL3733B_FUNC_CFG 0x00 +#define IS31FL3733B_FUNC_GCC 0x01 +#define IS31FL3733B_FUNC_ABM1_1 0x02 +#define IS31FL3733B_FUNC_ABM1_2 0x03 +#define IS31FL3733B_FUNC_ABM1_3 0x04 +#define IS31FL3733B_FUNC_ABM1_4 0x05 +#define IS31FL3733B_FUNC_ABM2_1 0x06 +#define IS31FL3733B_FUNC_ABM2_2 0x07 +#define IS31FL3733B_FUNC_ABM2_3 0x08 +#define IS31FL3733B_FUNC_ABM2_4 0x09 +#define IS31FL3733B_FUNC_ABM3_1 0x0a +#define IS31FL3733B_FUNC_ABM3_2 0x0b +#define IS31FL3733B_FUNC_ABM3_3 0x0c +#define IS31FL3733B_FUNC_ABM3_4 0x0d +#define IS31FL3733B_FUNC_TUR 0x0e +#define IS31FL3733B_FUNC_SW_PU 0x0f +#define IS31FL3733B_FUNC_CS_PD 0x10 +#define IS31FL3733B_FUNC_RST 0x11 static int is31fl3733b_read(struct rgbkbd *ctx, uint8_t addr, uint8_t *value) { - return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, - &addr, sizeof(addr), value, sizeof(*value)); + return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, &addr, + sizeof(addr), value, sizeof(*value)); } static int is31fl3733b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) @@ -80,8 +79,8 @@ static int is31fl3733b_write(struct rgbkbd *ctx, uint8_t addr, uint8_t value) [1] = value, }; - return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, - buf, sizeof(buf), NULL, 0); + return i2c_xfer(ctx->cfg->i2c, IS31FL3733B_ADDR_FLAGS, buf, sizeof(buf), + NULL, 0); } static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page) @@ -90,7 +89,7 @@ static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page) /* unlock page select once */ rv = is31fl3733b_write(ctx, IS31FL3733B_REG_COMMAND_WRITE_LOCK, - IS31FL3733B_WRITE_ENABLE); + IS31FL3733B_WRITE_ENABLE); if (rv) { return rv; } @@ -99,7 +98,7 @@ static int is31fl3733b_set_page(struct rgbkbd *ctx, uint8_t page) } static int is31fl3733b_get_config(struct rgbkbd *ctx, uint8_t addr, - uint8_t *value) + uint8_t *value) { int rv; @@ -112,7 +111,7 @@ static int is31fl3733b_get_config(struct rgbkbd *ctx, uint8_t addr, } static int is31fl3733b_set_config(struct rgbkbd *ctx, uint8_t addr, - uint8_t value) + uint8_t value) { int rv; @@ -150,7 +149,7 @@ static int is31fl3733b_enable(struct rgbkbd *ctx, bool enable) } static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset, - struct rgb_s *color, uint8_t len) + struct rgb_s *color, uint8_t len) { int led_addr, led_addr_row, led_addr_col; int i, rv; @@ -165,7 +164,7 @@ static int is31fl3733b_set_color(struct rgbkbd *ctx, uint8_t offset, led_addr_col = (offset + i) / ctx->cfg->row_len; led_addr = led_addr_row * 0x30 + led_addr_col; - rv = is31fl3733b_write(ctx, led_addr + 0x00, color[i].r); + rv = is31fl3733b_write(ctx, led_addr + 0x00, color[i].r); rv |= is31fl3733b_write(ctx, led_addr + 0x10, color[i].g); rv |= is31fl3733b_write(ctx, led_addr + 0x20, color[i].b); @@ -209,16 +208,13 @@ static int is31fl3733b_init(struct rgbkbd *ctx) } if (IS_ENABLED(CONFIG_RGB_KEYBOARD_DEBUG)) { - uint8_t val; int ret; - ret = is31fl3733b_get_config(ctx, - IS31FL3733B_FUNC_SW_PU, &val); + ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_SW_PU, &val); CPRINTS("SW_PU: val=0x%02x (rv=%d)", val, ret); - ret = is31fl3733b_get_config(ctx, - IS31FL3733B_FUNC_CS_PD, &val); + ret = is31fl3733b_get_config(ctx, IS31FL3733B_FUNC_CS_PD, &val); CPRINTS("CS_PD: val=0x%02x (rv=%d)", val, ret); } -- cgit v1.2.1 From 37dc319a473f580d4540d357d39b2fc7f2e9c000 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:30 -0600 Subject: board/anahera/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cb325c1f4c68fa1a25af6b2823873896cdc71be Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727105 Reviewed-by: Jeremy Bettis --- board/anahera/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/anahera/fans.c b/board/anahera/fans.c index 61671fd0a7..1ecf1d4a75 100644 --- a/board/anahera/fans.c +++ b/board/anahera/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From d9e6e8846634437d469893ecc019a47e60a54862 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:43 -0600 Subject: chip/stm32/flash-f.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee2bf280ff948727c76cbcf748538f26492b1e4a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729495 Reviewed-by: Jeremy Bettis --- chip/stm32/flash-f.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/chip/stm32/flash-f.h b/chip/stm32/flash-f.h index cbbe6ec86f..3f2b7174c1 100644 --- a/chip/stm32/flash-f.h +++ b/chip/stm32/flash-f.h @@ -9,16 +9,16 @@ #include enum flash_rdp_level { - FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ - FLASH_RDP_LEVEL_0, /**< No read protection. */ - FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in - * bootloader mode or JTAG attached. - * Changing to Level 0 from this level - * triggers mass erase. - */ - FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent - * and can never be disabled. - */ + FLASH_RDP_LEVEL_INVALID = -1, /**< Error occurred. */ + FLASH_RDP_LEVEL_0, /**< No read protection. */ + FLASH_RDP_LEVEL_1, /**< Reading flash is disabled while in + * bootloader mode or JTAG attached. + * Changing to Level 0 from this level + * triggers mass erase. + */ + FLASH_RDP_LEVEL_2, /**< Same as Level 1, but is permanent + * and can never be disabled. + */ }; bool is_flash_rdp_enabled(void); -- cgit v1.2.1 From a46806a817b3fcf89b5c4c11a788a882e007b2f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:12 -0600 Subject: chip/mchp/registers-mec172x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1da902c58f3d163e2a185f4ec832ce3002428772 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729312 Reviewed-by: Jeremy Bettis --- chip/mchp/registers-mec172x.h | 2050 ++++++++++++++++++++--------------------- 1 file changed, 1021 insertions(+), 1029 deletions(-) diff --git a/chip/mchp/registers-mec172x.h b/chip/mchp/registers-mec172x.h index dc811ea3c7..20b7f6bdf5 100644 --- a/chip/mchp/registers-mec172x.h +++ b/chip/mchp/registers-mec172x.h @@ -14,227 +14,227 @@ * NOTE: GIRQ22 aggregated output and its sources are not connected to * the NVIC. */ -#define MCHP_IRQ_GIRQ8 0 -#define MCHP_IRQ_GIRQ9 1 -#define MCHP_IRQ_GIRQ10 2 -#define MCHP_IRQ_GIRQ11 3 -#define MCHP_IRQ_GIRQ12 4 -#define MCHP_IRQ_GIRQ13 5 -#define MCHP_IRQ_GIRQ14 6 -#define MCHP_IRQ_GIRQ15 7 -#define MCHP_IRQ_GIRQ16 8 -#define MCHP_IRQ_GIRQ17 9 -#define MCHP_IRQ_GIRQ18 10 -#define MCHP_IRQ_GIRQ19 11 -#define MCHP_IRQ_GIRQ20 12 -#define MCHP_IRQ_GIRQ21 13 -#define MCHP_IRQ_GIRQ23 14 -#define MCHP_IRQ_GIRQ24 15 -#define MCHP_IRQ_GIRQ25 16 -#define MCHP_IRQ_GIRQ26 17 +#define MCHP_IRQ_GIRQ8 0 +#define MCHP_IRQ_GIRQ9 1 +#define MCHP_IRQ_GIRQ10 2 +#define MCHP_IRQ_GIRQ11 3 +#define MCHP_IRQ_GIRQ12 4 +#define MCHP_IRQ_GIRQ13 5 +#define MCHP_IRQ_GIRQ14 6 +#define MCHP_IRQ_GIRQ15 7 +#define MCHP_IRQ_GIRQ16 8 +#define MCHP_IRQ_GIRQ17 9 +#define MCHP_IRQ_GIRQ18 10 +#define MCHP_IRQ_GIRQ19 11 +#define MCHP_IRQ_GIRQ20 12 +#define MCHP_IRQ_GIRQ21 13 +#define MCHP_IRQ_GIRQ23 14 +#define MCHP_IRQ_GIRQ24 15 +#define MCHP_IRQ_GIRQ25 16 +#define MCHP_IRQ_GIRQ26 17 /* GIRQ13 direct sources */ -#define MCHP_IRQ_I2C_0 20 -#define MCHP_IRQ_I2C_1 21 -#define MCHP_IRQ_I2C_2 22 -#define MCHP_IRQ_I2C_3 23 -#define MCHP_IRQ_I2C_4 158 +#define MCHP_IRQ_I2C_0 20 +#define MCHP_IRQ_I2C_1 21 +#define MCHP_IRQ_I2C_2 22 +#define MCHP_IRQ_I2C_3 23 +#define MCHP_IRQ_I2C_4 158 /* GIRQ14 direct sources */ -#define MCHP_IRQ_DMA_0 24 -#define MCHP_IRQ_DMA_1 25 -#define MCHP_IRQ_DMA_2 26 -#define MCHP_IRQ_DMA_3 27 -#define MCHP_IRQ_DMA_4 28 -#define MCHP_IRQ_DMA_5 29 -#define MCHP_IRQ_DMA_6 30 -#define MCHP_IRQ_DMA_7 31 -#define MCHP_IRQ_DMA_8 32 -#define MCHP_IRQ_DMA_9 33 -#define MCHP_IRQ_DMA_10 34 -#define MCHP_IRQ_DMA_11 35 -#define MCHP_IRQ_DMA_12 36 -#define MCHP_IRQ_DMA_13 37 -#define MCHP_IRQ_DMA_14 38 -#define MCHP_IRQ_DMA_15 39 +#define MCHP_IRQ_DMA_0 24 +#define MCHP_IRQ_DMA_1 25 +#define MCHP_IRQ_DMA_2 26 +#define MCHP_IRQ_DMA_3 27 +#define MCHP_IRQ_DMA_4 28 +#define MCHP_IRQ_DMA_5 29 +#define MCHP_IRQ_DMA_6 30 +#define MCHP_IRQ_DMA_7 31 +#define MCHP_IRQ_DMA_8 32 +#define MCHP_IRQ_DMA_9 33 +#define MCHP_IRQ_DMA_10 34 +#define MCHP_IRQ_DMA_11 35 +#define MCHP_IRQ_DMA_12 36 +#define MCHP_IRQ_DMA_13 37 +#define MCHP_IRQ_DMA_14 38 +#define MCHP_IRQ_DMA_15 39 /* GIRQ15 direct sources */ -#define MCHP_IRQ_UART0 40 -#define MCHP_IRQ_UART1 41 -#define MCHP_IRQ_EMI0 42 -#define MCHP_IRQ_EMI1 43 -#define MCHP_IRQ_EMI2 44 -#define MCHP_IRQ_ACPIEC0_IBF 45 -#define MCHP_IRQ_ACPIEC0_OBE 46 -#define MCHP_IRQ_ACPIEC1_IBF 47 -#define MCHP_IRQ_ACPIEC1_OBE 48 -#define MCHP_IRQ_ACPIEC2_IBF 49 -#define MCHP_IRQ_ACPIEC2_OBE 50 -#define MCHP_IRQ_ACPIEC3_IBF 51 -#define MCHP_IRQ_ACPIEC3_OBE 52 -#define MCHP_IRQ_ACPIEC4_IBF 53 -#define MCHP_IRQ_ACPIEC4_OBE 54 -#define MCHP_IRQ_ACPIPM1_CTL 55 -#define MCHP_IRQ_ACPIPM1_EN 56 -#define MCHP_IRQ_ACPIPM1_STS 57 -#define MCHP_IRQ_8042EM_OBE 58 -#define MCHP_IRQ_8042EM_IBF 59 -#define MCHP_IRQ_MAILBOX_DATA 60 -#define MCHP_IRQ_BDP0 62 +#define MCHP_IRQ_UART0 40 +#define MCHP_IRQ_UART1 41 +#define MCHP_IRQ_EMI0 42 +#define MCHP_IRQ_EMI1 43 +#define MCHP_IRQ_EMI2 44 +#define MCHP_IRQ_ACPIEC0_IBF 45 +#define MCHP_IRQ_ACPIEC0_OBE 46 +#define MCHP_IRQ_ACPIEC1_IBF 47 +#define MCHP_IRQ_ACPIEC1_OBE 48 +#define MCHP_IRQ_ACPIEC2_IBF 49 +#define MCHP_IRQ_ACPIEC2_OBE 50 +#define MCHP_IRQ_ACPIEC3_IBF 51 +#define MCHP_IRQ_ACPIEC3_OBE 52 +#define MCHP_IRQ_ACPIEC4_IBF 53 +#define MCHP_IRQ_ACPIEC4_OBE 54 +#define MCHP_IRQ_ACPIPM1_CTL 55 +#define MCHP_IRQ_ACPIPM1_EN 56 +#define MCHP_IRQ_ACPIPM1_STS 57 +#define MCHP_IRQ_8042EM_OBE 58 +#define MCHP_IRQ_8042EM_IBF 59 +#define MCHP_IRQ_MAILBOX_DATA 60 +#define MCHP_IRQ_BDP0 62 /* GIRQ16 direct sources */ -#define MCHP_IRQ_PKE 65 -#define MCHP_IRQ_NDRNG 67 -#define MCHP_IRQ_AESH 68 +#define MCHP_IRQ_PKE 65 +#define MCHP_IRQ_NDRNG 67 +#define MCHP_IRQ_AESH 68 /* GIRQ17 direct sources */ -#define MCHP_IRQ_PECI_HOST 70 -#define MCHP_IRQ_TACH_0 71 -#define MCHP_IRQ_TACH_1 72 -#define MCHP_IRQ_TACH_2 73 -#define MCHP_IRQ_TACH_3 159 -#define MCHP_IRQ_FAN0_FAIL 74 -#define MCHP_IRQ_FAN0_STALL 75 -#define MCHP_IRQ_FAN1_FAIL 76 -#define MCHP_IRQ_FAN1_STALL 77 -#define MCHP_IRQ_ADC_SNGL 78 -#define MCHP_IRQ_ADC_RPT 79 -#define MCHP_IRQ_RCID0 80 -#define MCHP_IRQ_RCID1 81 -#define MCHP_IRQ_RCID2 82 -#define MCHP_IRQ_LED0_WDT 83 -#define MCHP_IRQ_LED1_WDT 84 -#define MCHP_IRQ_LED2_WDT 85 -#define MCHP_IRQ_LED3_WDT 86 -#define MCHP_IRQ_PHOT 87 +#define MCHP_IRQ_PECI_HOST 70 +#define MCHP_IRQ_TACH_0 71 +#define MCHP_IRQ_TACH_1 72 +#define MCHP_IRQ_TACH_2 73 +#define MCHP_IRQ_TACH_3 159 +#define MCHP_IRQ_FAN0_FAIL 74 +#define MCHP_IRQ_FAN0_STALL 75 +#define MCHP_IRQ_FAN1_FAIL 76 +#define MCHP_IRQ_FAN1_STALL 77 +#define MCHP_IRQ_ADC_SNGL 78 +#define MCHP_IRQ_ADC_RPT 79 +#define MCHP_IRQ_RCID0 80 +#define MCHP_IRQ_RCID1 81 +#define MCHP_IRQ_RCID2 82 +#define MCHP_IRQ_LED0_WDT 83 +#define MCHP_IRQ_LED1_WDT 84 +#define MCHP_IRQ_LED2_WDT 85 +#define MCHP_IRQ_LED3_WDT 86 +#define MCHP_IRQ_PHOT 87 /* GIRQ18 direct sources */ -#define MCHP_IRQ_SLAVE_SPI 90 -#define MCHP_IRQ_QMSPI0 91 -#define MCHP_IRQ_SPI0_TX 92 -#define MCHP_IRQ_SPI0_RX 93 -#define MCHP_IRQ_SPI1_TX 94 -#define MCHP_IRQ_SPI1_RX 95 -#define MCHP_IRQ_BCM0_ERR 96 -#define MCHP_IRQ_BCM0_BUSY 97 -#define MCHP_IRQ_PS2_0 100 -#define MCHP_IRQ_EEPROM 155 -#define MCHP_IRQ_CCT_TMR 146 -#define MCHP_IRQ_CCT_CAP0 147 -#define MCHP_IRQ_CCT_CAP1 148 -#define MCHP_IRQ_CCT_CAP2 149 -#define MCHP_IRQ_CCT_CAP3 150 -#define MCHP_IRQ_CCT_CAP4 151 -#define MCHP_IRQ_CCT_CAP5 152 -#define MCHP_IRQ_CCT_CMP0 153 -#define MCHP_IRQ_CCT_CMP1 154 +#define MCHP_IRQ_SLAVE_SPI 90 +#define MCHP_IRQ_QMSPI0 91 +#define MCHP_IRQ_SPI0_TX 92 +#define MCHP_IRQ_SPI0_RX 93 +#define MCHP_IRQ_SPI1_TX 94 +#define MCHP_IRQ_SPI1_RX 95 +#define MCHP_IRQ_BCM0_ERR 96 +#define MCHP_IRQ_BCM0_BUSY 97 +#define MCHP_IRQ_PS2_0 100 +#define MCHP_IRQ_EEPROM 155 +#define MCHP_IRQ_CCT_TMR 146 +#define MCHP_IRQ_CCT_CAP0 147 +#define MCHP_IRQ_CCT_CAP1 148 +#define MCHP_IRQ_CCT_CAP2 149 +#define MCHP_IRQ_CCT_CAP3 150 +#define MCHP_IRQ_CCT_CAP4 151 +#define MCHP_IRQ_CCT_CAP5 152 +#define MCHP_IRQ_CCT_CMP0 153 +#define MCHP_IRQ_CCT_CMP1 154 /* GIRQ19 direct sources */ -#define MCHP_IRQ_ESPI_PC 103 -#define MCHP_IRQ_ESPI_BM1 104 -#define MCHP_IRQ_ESPI_BM2 105 -#define MCHP_IRQ_ESPI_LTR 106 -#define MCHP_IRQ_ESPI_OOB_UP 107 -#define MCHP_IRQ_ESPI_OOB_DN 108 -#define MCHP_IRQ_ESPI_FC 109 -#define MCHP_IRQ_ESPI_RESET 110 -#define MCHP_IRQ_ESPI_VW_EN 156 -#define MCHP_IRQ_ESPI_SAF_DONE 166 -#define MCHP_IRQ_ESPI_SAF_ERR 166 -#define MCHP_IRQ_ESPI_SAF_CACHE 169 +#define MCHP_IRQ_ESPI_PC 103 +#define MCHP_IRQ_ESPI_BM1 104 +#define MCHP_IRQ_ESPI_BM2 105 +#define MCHP_IRQ_ESPI_LTR 106 +#define MCHP_IRQ_ESPI_OOB_UP 107 +#define MCHP_IRQ_ESPI_OOB_DN 108 +#define MCHP_IRQ_ESPI_FC 109 +#define MCHP_IRQ_ESPI_RESET 110 +#define MCHP_IRQ_ESPI_VW_EN 156 +#define MCHP_IRQ_ESPI_SAF_DONE 166 +#define MCHP_IRQ_ESPI_SAF_ERR 166 +#define MCHP_IRQ_ESPI_SAF_CACHE 169 /* GIRQ20 direct sources */ -#define MCHP_IRQ_OTP 173 -#define MCHP_IRQ_CLK32K_MON 174 +#define MCHP_IRQ_OTP 173 +#define MCHP_IRQ_CLK32K_MON 174 /* GIRQ21 direct sources */ -#define MCHP_IRQ_WDG 171 -#define MCHP_IRQ_WEEK_ALARM 114 -#define MCHP_IRQ_SUBWEEK 115 -#define MCHP_IRQ_WEEK_SEC 116 -#define MCHP_IRQ_WEEK_SUBSEC 117 -#define MCHP_IRQ_WEEK_SYSPWR 118 -#define MCHP_IRQ_RTC 119 -#define MCHP_IRQ_RTC_ALARM 120 -#define MCHP_IRQ_VCI_OVRD_IN 121 -#define MCHP_IRQ_VCI_IN0 122 -#define MCHP_IRQ_VCI_IN1 123 -#define MCHP_IRQ_VCI_IN2 124 -#define MCHP_IRQ_VCI_IN3 125 -#define MCHP_IRQ_VCI_IN4 126 -#define MCHP_IRQ_PS20A_WAKE 129 -#define MCHP_IRQ_PS20B_WAKE 130 -#define MCHP_IRQ_KSC_INT 135 -#define MCHP_IRQ_GLUE 172 +#define MCHP_IRQ_WDG 171 +#define MCHP_IRQ_WEEK_ALARM 114 +#define MCHP_IRQ_SUBWEEK 115 +#define MCHP_IRQ_WEEK_SEC 116 +#define MCHP_IRQ_WEEK_SUBSEC 117 +#define MCHP_IRQ_WEEK_SYSPWR 118 +#define MCHP_IRQ_RTC 119 +#define MCHP_IRQ_RTC_ALARM 120 +#define MCHP_IRQ_VCI_OVRD_IN 121 +#define MCHP_IRQ_VCI_IN0 122 +#define MCHP_IRQ_VCI_IN1 123 +#define MCHP_IRQ_VCI_IN2 124 +#define MCHP_IRQ_VCI_IN3 125 +#define MCHP_IRQ_VCI_IN4 126 +#define MCHP_IRQ_PS20A_WAKE 129 +#define MCHP_IRQ_PS20B_WAKE 130 +#define MCHP_IRQ_KSC_INT 135 +#define MCHP_IRQ_GLUE 172 /* GIRQ23 direct sources */ -#define MCHP_IRQ_TIMER16_0 136 -#define MCHP_IRQ_TIMER16_1 137 -#define MCHP_IRQ_TIMER16_2 138 -#define MCHP_IRQ_TIMER16_3 139 -#define MCHP_IRQ_TIMER32_0 140 -#define MCHP_IRQ_TIMER32_1 141 -#define MCHP_IRQ_CNTR_TM0 142 -#define MCHP_IRQ_CNTR_TM1 143 -#define MCHP_IRQ_CNTR_TM2 144 -#define MCHP_IRQ_CNTR_TM3 145 -#define MCHP_IRQ_RTOS_TIMER 111 -#define MCHP_IRQ_HTIMER0 112 -#define MCHP_IRQ_HTIMER1 113 +#define MCHP_IRQ_TIMER16_0 136 +#define MCHP_IRQ_TIMER16_1 137 +#define MCHP_IRQ_TIMER16_2 138 +#define MCHP_IRQ_TIMER16_3 139 +#define MCHP_IRQ_TIMER32_0 140 +#define MCHP_IRQ_TIMER32_1 141 +#define MCHP_IRQ_CNTR_TM0 142 +#define MCHP_IRQ_CNTR_TM1 143 +#define MCHP_IRQ_CNTR_TM2 144 +#define MCHP_IRQ_CNTR_TM3 145 +#define MCHP_IRQ_RTOS_TIMER 111 +#define MCHP_IRQ_HTIMER0 112 +#define MCHP_IRQ_HTIMER1 113 /* Must match CONFIG_IRQ_COUNT in config_chip.h */ #define MCHP_IRQ_MAX 180 /* Block base addresses */ -#define MCHP_WDG_BASE 0x40000400 -#define MCHP_TMR16_0_BASE 0x40000c00 -#define MCHP_TMR32_0_BASE 0x40000c80 -#define MCHP_CNT16_0_BASE 0x40000d00 -#define MCHP_DMA_BASE 0x40002400 -#define MCHP_PROCHOT_BASE 0x40003400 -#define MCHP_I2C0_BASE 0x40004000 -#define MCHP_I2C1_BASE 0x40004400 -#define MCHP_I2C2_BASE 0x40004800 -#define MCHP_I2C3_BASE 0x40004C00 -#define MCHP_I2C4_BASE 0x40005000 -#define MCHP_CACHE_CTRL_BASE 0x40005400 -#define MCHP_PWM_0_BASE 0x40005800 -#define MCHP_TACH_0_BASE 0x40006000 -#define MCHP_PECI_BASE 0x40006400 -#define MCHP_SPIEP_BASE 0x40007000 -#define MCHP_RTMR_BASE 0x40007400 -#define MCHP_ADC_BASE 0x40007c00 -#define MCHP_ESPI_SAF_BASE 0x40008000 -#define MCHP_TFDP_BASE 0x40008c00 -#define MCHP_GPSPI0_BASE 0x40009400 -#define MCHP_GPSPI1_BASE 0x40009480 -#define MCHP_HTIMER_BASE 0x40009800 -#define MCHP_KEYSCAN_BASE 0x40009c00 -#define MCHP_RPM2PWM0_BASE 0x4000a000 -#define MCHP_RPM2PWM1_BASE 0x4000a080 -#define MCHP_VBAT_BASE 0x4000a400 -#define MCHP_VBAT_RAM_BASE 0x4000a800 -#define MCHP_WKTIMER_BASE 0x4000ac80 -#define MCHP_VCI_BASE 0x4000ae00 -#define MCHP_BBLED_0_BASE 0x4000B800 -#define MCHP_BCL_0_BASE 0x4000cd00 -#define MCHP_INT_BASE 0x4000e000 -#define MCHP_EC_BASE 0x4000fc00 - -#define MCHP_QMSPI0_BASE 0x40070000 +#define MCHP_WDG_BASE 0x40000400 +#define MCHP_TMR16_0_BASE 0x40000c00 +#define MCHP_TMR32_0_BASE 0x40000c80 +#define MCHP_CNT16_0_BASE 0x40000d00 +#define MCHP_DMA_BASE 0x40002400 +#define MCHP_PROCHOT_BASE 0x40003400 +#define MCHP_I2C0_BASE 0x40004000 +#define MCHP_I2C1_BASE 0x40004400 +#define MCHP_I2C2_BASE 0x40004800 +#define MCHP_I2C3_BASE 0x40004C00 +#define MCHP_I2C4_BASE 0x40005000 +#define MCHP_CACHE_CTRL_BASE 0x40005400 +#define MCHP_PWM_0_BASE 0x40005800 +#define MCHP_TACH_0_BASE 0x40006000 +#define MCHP_PECI_BASE 0x40006400 +#define MCHP_SPIEP_BASE 0x40007000 +#define MCHP_RTMR_BASE 0x40007400 +#define MCHP_ADC_BASE 0x40007c00 +#define MCHP_ESPI_SAF_BASE 0x40008000 +#define MCHP_TFDP_BASE 0x40008c00 +#define MCHP_GPSPI0_BASE 0x40009400 +#define MCHP_GPSPI1_BASE 0x40009480 +#define MCHP_HTIMER_BASE 0x40009800 +#define MCHP_KEYSCAN_BASE 0x40009c00 +#define MCHP_RPM2PWM0_BASE 0x4000a000 +#define MCHP_RPM2PWM1_BASE 0x4000a080 +#define MCHP_VBAT_BASE 0x4000a400 +#define MCHP_VBAT_RAM_BASE 0x4000a800 +#define MCHP_WKTIMER_BASE 0x4000ac80 +#define MCHP_VCI_BASE 0x4000ae00 +#define MCHP_BBLED_0_BASE 0x4000B800 +#define MCHP_BCL_0_BASE 0x4000cd00 +#define MCHP_INT_BASE 0x4000e000 +#define MCHP_EC_BASE 0x4000fc00 + +#define MCHP_QMSPI0_BASE 0x40070000 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000 -#define MCHP_PCR_BASE 0x40080100 -#define MCHP_GPIO_BASE 0x40081000 -#define MCHP_OTP_BASE 0x40082000 - -#define MCHP_MBOX_BASE 0x400f0000 -#define MCHP_8042_BASE 0x400f0400 -#define MCHP_ACPI_EC_0_BASE 0x400f0800 -#define MCHP_ACPI_PM1_BASE 0x400f1c00 -#define MCHP_PORT92_BASE 0x400f2000 -#define MCHP_UART0_BASE 0x400f2400 -#define MCHP_UART1_BASE 0x400f2800 -#define MCHP_LPC_BASE 0x400f3000 -#define MCHP_ESPI_IO_BASE 0x400f3400 -#define MCHP_ESPI_MEM_BASE 0x400f3800 -#define MCHP_GLUE_BASE 0x400f3c00 -#define MCHP_EMI_0_BASE 0x400f4000 -#define MCHP_EMI_1_BASE 0x400f4400 -#define MCHP_EMI_2_BASE 0x400f4800 -#define MCHP_RTC_BASE 0x400f5000 -#define MCHP_BDP0_BASE 0x400f8000 -#define MCHP_ESPI_VW_BASE 0x400f9c00 -#define MCHP_CHIP_BASE 0x400fff00 +#define MCHP_PCR_BASE 0x40080100 +#define MCHP_GPIO_BASE 0x40081000 +#define MCHP_OTP_BASE 0x40082000 + +#define MCHP_MBOX_BASE 0x400f0000 +#define MCHP_8042_BASE 0x400f0400 +#define MCHP_ACPI_EC_0_BASE 0x400f0800 +#define MCHP_ACPI_PM1_BASE 0x400f1c00 +#define MCHP_PORT92_BASE 0x400f2000 +#define MCHP_UART0_BASE 0x400f2400 +#define MCHP_UART1_BASE 0x400f2800 +#define MCHP_LPC_BASE 0x400f3000 +#define MCHP_ESPI_IO_BASE 0x400f3400 +#define MCHP_ESPI_MEM_BASE 0x400f3800 +#define MCHP_GLUE_BASE 0x400f3c00 +#define MCHP_EMI_0_BASE 0x400f4000 +#define MCHP_EMI_1_BASE 0x400f4400 +#define MCHP_EMI_2_BASE 0x400f4800 +#define MCHP_RTC_BASE 0x400f5000 +#define MCHP_BDP0_BASE 0x400f8000 +#define MCHP_ESPI_VW_BASE 0x400f9c00 +#define MCHP_CHIP_BASE 0x400fff00 #ifndef __ASSEMBLER__ @@ -244,253 +244,252 @@ * Cortex-M4 bit-banding does require aliasing of the * DATA SRAM region. */ -#define MCHP_RAM_ALIAS(x) \ - ((x) >= 0x118000 ? (x) - 0x118000 + 0x20000000 : (x)) +#define MCHP_RAM_ALIAS(x) ((x) >= 0x118000 ? (x)-0x118000 + 0x20000000 : (x)) /* EC Chip Configuration */ /* 16-bit Device ID */ -#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E) +#define MCHP_CHIP_DEV_ID REG16(MCHP_CHIP_BASE + 0x1E) /* 8-bit Device Sub ID */ -#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D) +#define MCHP_CHIP_DEV_SUB_ID REG8(MCHP_CHIP_BASE + 0x1D) /* 8-bit Device Revision */ -#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C) +#define MCHP_CHIP_DEV_REV REG8(MCHP_CHIP_BASE + 0x1C) /* All in one */ -#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C) -#define MCHP_CHIP_DEVID_POS 16 -#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS) -#define MCHP_CHIP_SUBID_POS 8 -#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS) -#define MCHP_CHIP_REV_POS 0 -#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS) +#define MCHP_CHIP_DEVRID32 REG32(MCHP_CHIP_BASE + 0x1C) +#define MCHP_CHIP_DEVID_POS 16 +#define MCHP_CHIP_DEVID_MASK (0xfffful << MCHP_CHIP_DEVID_POS) +#define MCHP_CHIP_SUBID_POS 8 +#define MCHP_CHIP_SUBID_MASK (0xfful << MCHP_CHIP_SUBID_POS) +#define MCHP_CHIP_REV_POS 0 +#define MCHP_CHIP_REV_MASK (0xfful << MCHP_CHIP_REV_POS) #define MCHP_CHIP_EXTRACT_DEVID(d) \ - (((uint32_t)(d) & MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS) + (((uint32_t)(d)&MCHP_CHIP_DEVID_MASK) >> MCHP_CHIP_DEVID_POS) #define MCHP_CHIP_EXTRACT_SUBID(d) \ - (((uint32_t)(d) & MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS) + (((uint32_t)(d)&MCHP_CHIP_SUBID_MASK) >> MCHP_CHIP_SUBID_POS) #define MCHP_CHIP_EXTRACT_REV(d) \ - (((uint32_t)(d) & MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS) + (((uint32_t)(d)&MCHP_CHIP_REV_MASK) >> MCHP_CHIP_REV_POS) /* PCR clock control dividers */ -#define MCHP_PCR_CLK_CTL_FASTEST 1U -#define MCHP_PCR_CLK_CTL_96MHZ 1U -#define MCHP_PCR_CLK_CTL_48MHZ 2U -#define MCHP_PCR_CLK_CTL_24MHZ 4U -#define MCHP_PCR_CLK_CTL_12MHZ 8U +#define MCHP_PCR_CLK_CTL_FASTEST 1U +#define MCHP_PCR_CLK_CTL_96MHZ 1U +#define MCHP_PCR_CLK_CTL_48MHZ 2U +#define MCHP_PCR_CLK_CTL_24MHZ 4U +#define MCHP_PCR_CLK_CTL_12MHZ 8U /* Number of PCR Sleep Enable, Clock Required, and Reset registers */ #define MCHP_PCR_SLP_RST_REG_MAX 5 /* Sleep 0: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ -#define MCHP_PCR_OTP BIT(1) -#define MCHP_PCR_ISPI BIT(2) +#define MCHP_PCR_JTAG BIT(0) /* CLKREQ only */ +#define MCHP_PCR_OTP BIT(1) +#define MCHP_PCR_ISPI BIT(2) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN0_JTAG BIT(0) -#define MCHP_PCR_SLP_EN0_OTP BIT(1) -#define MCHP_PCR_SLP_EN0_ISPI BIT(2) -#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN0_JTAG BIT(0) +#define MCHP_PCR_SLP_EN0_OTP BIT(1) +#define MCHP_PCR_SLP_EN0_ISPI BIT(2) +#define MCHP_PCR_SLP_EN0_SLEEP 0xffffffff /* * Encode register number and bit position * b[4:0] = bit number * b[10:8] = zero based register number */ -#define MCHP_PCR_ERB(rnum, bnum) \ - ((((rnum) & 0x0f) << 8) | ((bnum) & 0x1f)) +#define MCHP_PCR_ERB(rnum, bnum) ((((rnum)&0x0f) << 8) | ((bnum)&0x1f)) /* PCR Sleep 1: Sleep Enable, Clock Required, and Reset bits */ -#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) -#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) -#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) -#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) -#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) -#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) -#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) -#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) -#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) -#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) -#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) -#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13) -#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) -#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) -#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) -#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) -#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) -#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) -#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) -#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) -#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) -#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) -#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) -#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) +#define MCHP_PCR_BTMR16_1 MCHP_PCR_ERB(1, 31) +#define MCHP_PCR_BTMR16_0 MCHP_PCR_ERB(1, 30) +#define MCHP_PCR_ECS MCHP_PCR_ERB(1, 29) +#define MCHP_PCR_PWM8 MCHP_PCR_ERB(1, 27) +#define MCHP_PCR_PWM7 MCHP_PCR_ERB(1, 26) +#define MCHP_PCR_PWM6 MCHP_PCR_ERB(1, 25) +#define MCHP_PCR_PWM5 MCHP_PCR_ERB(1, 24) +#define MCHP_PCR_PWM4 MCHP_PCR_ERB(1, 23) +#define MCHP_PCR_PWM3 MCHP_PCR_ERB(1, 22) +#define MCHP_PCR_PWM2 MCHP_PCR_ERB(1, 21) +#define MCHP_PCR_PWM1 MCHP_PCR_ERB(1, 20) +#define MCHP_PCR_TACH3 MCHP_PCR_ERB(1, 13) +#define MCHP_PCR_TACH2 MCHP_PCR_ERB(1, 12) +#define MCHP_PCR_TACH1 MCHP_PCR_ERB(1, 11) +#define MCHP_PCR_I2C0 MCHP_PCR_ERB(1, 10) +#define MCHP_PCR_WDT MCHP_PCR_ERB(1, 9) +#define MCHP_PCR_CPU MCHP_PCR_ERB(1, 8) +#define MCHP_PCR_TFDP MCHP_PCR_ERB(1, 7) +#define MCHP_PCR_DMA MCHP_PCR_ERB(1, 6) +#define MCHP_PCR_PMC MCHP_PCR_ERB(1, 5) +#define MCHP_PCR_PWM0 MCHP_PCR_ERB(1, 4) +#define MCHP_PCR_TACH0 MCHP_PCR_ERB(1, 2) +#define MCHP_PCR_PECI MCHP_PCR_ERB(1, 1) +#define MCHP_PCR_ECIA MCHP_PCR_ERB(1, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) -#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) -#define MCHP_PCR_SLP_EN1_ECS BIT(29) -#define MCHP_PCR_SLP_EN1_PWM_ALL (BIT(4) | BIT(20) | BIT(21) |\ - BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) -#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) -#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) -#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) -#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) -#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) -#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) -#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) -#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) -#define MCHP_PCR_SLP_EN1_TACH3 BIT(13) -#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) -#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) -#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) -#define MCHP_PCR_SLP_EN1_WDT BIT(9) -#define MCHP_PCR_SLP_EN1_CPU BIT(8) -#define MCHP_PCR_SLP_EN1_TFDP BIT(7) -#define MCHP_PCR_SLP_EN1_DMA BIT(6) -#define MCHP_PCR_SLP_EN1_PMC BIT(5) -#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) -#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) -#define MCHP_PCR_SLP_EN1_PECI BIT(1) -#define MCHP_PCR_SLP_EN1_ECIA BIT(0) +#define MCHP_PCR_SLP_EN1_BTMR16_1 BIT(31) +#define MCHP_PCR_SLP_EN1_BTMR16_0 BIT(30) +#define MCHP_PCR_SLP_EN1_ECS BIT(29) +#define MCHP_PCR_SLP_EN1_PWM_ALL \ + (BIT(4) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | \ + BIT(26) | BIT(27)) +#define MCHP_PCR_SLP_EN1_PWM8 BIT(27) +#define MCHP_PCR_SLP_EN1_PWM7 BIT(26) +#define MCHP_PCR_SLP_EN1_PWM6 BIT(25) +#define MCHP_PCR_SLP_EN1_PWM5 BIT(24) +#define MCHP_PCR_SLP_EN1_PWM4 BIT(23) +#define MCHP_PCR_SLP_EN1_PWM3 BIT(22) +#define MCHP_PCR_SLP_EN1_PWM2 BIT(21) +#define MCHP_PCR_SLP_EN1_PWM1 BIT(20) +#define MCHP_PCR_SLP_EN1_TACH3 BIT(13) +#define MCHP_PCR_SLP_EN1_TACH2 BIT(12) +#define MCHP_PCR_SLP_EN1_TACH1 BIT(11) +#define MCHP_PCR_SLP_EN1_I2C0 BIT(10) +#define MCHP_PCR_SLP_EN1_WDT BIT(9) +#define MCHP_PCR_SLP_EN1_CPU BIT(8) +#define MCHP_PCR_SLP_EN1_TFDP BIT(7) +#define MCHP_PCR_SLP_EN1_DMA BIT(6) +#define MCHP_PCR_SLP_EN1_PMC BIT(5) +#define MCHP_PCR_SLP_EN1_PWM0 BIT(4) +#define MCHP_PCR_SLP_EN1_TACH0 BIT(2) +#define MCHP_PCR_SLP_EN1_PECI BIT(1) +#define MCHP_PCR_SLP_EN1_ECIA BIT(0) /* all sleep enable 1 bits */ -#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN1_SLEEP 0xffffffff /* * block not used by default * Do not sleep ECIA, PMC, CPU and ECS */ -#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede +#define MCHP_PCR_SLP_EN1_UNUSED_BLOCKS 0xdffffede /* PCR Sleep 2: Sleep Enable, Clock Required 2, Reset bits */ -#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29) -#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27) -#define MCHP_PCR_BDP0 MCHP_PCR_ERB(2, 25) -#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23) -#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) -#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) -#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20) -#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) -#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) -#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) -#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 16) -#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) -#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) -#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) -#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) -#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) -#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) -#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0) +#define MCHP_PCR_GLUE MCHP_PCR_ERB(2, 29) +#define MCHP_PCR_SAF MCHP_PCR_ERB(2, 27) +#define MCHP_PCR_BDP0 MCHP_PCR_ERB(2, 25) +#define MCHP_PCR_ACPI_EC4 MCHP_PCR_ERB(2, 23) +#define MCHP_PCR_ACPI_EC3 MCHP_PCR_ERB(2, 22) +#define MCHP_PCR_ACPI_EC2 MCHP_PCR_ERB(2, 21) +#define MCHP_PCR_ESPI_SCR MCHP_PCR_ERB(2, 20) +#define MCHP_PCR_ESPI MCHP_PCR_ERB(2, 19) +#define MCHP_PCR_RTC MCHP_PCR_ERB(2, 18) +#define MCHP_PCR_MBOX MCHP_PCR_ERB(2, 17) +#define MCHP_PCR_8042 MCHP_PCR_ERB(2, 16) +#define MCHP_PCR_ACPI_PM1 MCHP_PCR_ERB(2, 15) +#define MCHP_PCR_ACPI_EC1 MCHP_PCR_ERB(2, 14) +#define MCHP_PCR_ACPI_EC0 MCHP_PCR_ERB(2, 13) +#define MCHP_PCR_GCFG MCHP_PCR_ERB(2, 12) +#define MCHP_PCR_UART1 MCHP_PCR_ERB(2, 2) +#define MCHP_PCR_UART0 MCHP_PCR_ERB(2, 1) +#define MCHP_PCR_EMI0 MCHP_PCR_ERB(2, 0) /* Command all blocks to sleep */ -#define MCHP_PCR_SLP_EN2_GLUE BIT(29) -#define MCHP_PCR_SLP_EN2_SAF BIT(27) -#define MCHP_PCR_SLP_EN2_BDP0 BIT(25) -#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) -#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) -#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) -#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) -#define MCHP_PCR_SLP_EN2_ESPI BIT(19) -#define MCHP_PCR_SLP_EN2_RTC BIT(18) -#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) -#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) -#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) -#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) -#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) -#define MCHP_PCR_SLP_EN2_GCFG BIT(12) -#define MCHP_PCR_SLP_EN2_UART1 BIT(2) -#define MCHP_PCR_SLP_EN2_UART0 BIT(1) -#define MCHP_PCR_SLP_EN2_EMI0 BIT(0) +#define MCHP_PCR_SLP_EN2_GLUE BIT(29) +#define MCHP_PCR_SLP_EN2_SAF BIT(27) +#define MCHP_PCR_SLP_EN2_BDP0 BIT(25) +#define MCHP_PCR_SLP_EN2_ACPI_EC4 BIT(23) +#define MCHP_PCR_SLP_EN2_ACPI_EC3 BIT(22) +#define MCHP_PCR_SLP_EN2_ACPI_EC2 BIT(21) +#define MCHP_PCR_SLP_EN2_ESPI_SCR BIT(20) +#define MCHP_PCR_SLP_EN2_ESPI BIT(19) +#define MCHP_PCR_SLP_EN2_RTC BIT(18) +#define MCHP_PCR_SLP_EN2_MAILBOX BIT(17) +#define MCHP_PCR_SLP_EN2_MIF8042 BIT(16) +#define MCHP_PCR_SLP_EN2_ACPI_PM1 BIT(15) +#define MCHP_PCR_SLP_EN2_ACPI_EC1 BIT(14) +#define MCHP_PCR_SLP_EN2_ACPI_EC0 BIT(13) +#define MCHP_PCR_SLP_EN2_GCFG BIT(12) +#define MCHP_PCR_SLP_EN2_UART1 BIT(2) +#define MCHP_PCR_SLP_EN2_UART0 BIT(1) +#define MCHP_PCR_SLP_EN2_EMI0 BIT(0) /* all sleep enable 2 bits */ -#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN2_SLEEP 0xffffffff /* PCR Sleep 3: Sleep Enable, Clock Required, and Reset */ -#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31) -#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) -#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) -#define MCHP_PCR_CRYPTO MCHP_PCR_ERB(3, 26) -#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25) -#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) -#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) -#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22) -#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21) -#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20) -#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19) -#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) -#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) -#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) -#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) -#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) -#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) -#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12) -#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) -#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) -#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9) -#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) -#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) +#define MCHP_PCR_PWM9 MCHP_PCR_ERB(3, 31) +#define MCHP_PCR_CCT0 MCHP_PCR_ERB(3, 30) +#define MCHP_PCR_HTMR1 MCHP_PCR_ERB(3, 29) +#define MCHP_PCR_CRYPTO MCHP_PCR_ERB(3, 26) +#define MCHP_PCR_LED3 MCHP_PCR_ERB(3, 25) +#define MCHP_PCR_BTMR32_1 MCHP_PCR_ERB(3, 24) +#define MCHP_PCR_BTMR32_0 MCHP_PCR_ERB(3, 23) +#define MCHP_PCR_BTMR16_3 MCHP_PCR_ERB(3, 22) +#define MCHP_PCR_BTMR16_2 MCHP_PCR_ERB(3, 21) +#define MCHP_PCR_I2C4 MCHP_PCR_ERB(3, 20) +#define MCHP_PCR_BCM0 MCHP_PCR_ERB(3, 19) +#define MCHP_PCR_LED2 MCHP_PCR_ERB(3, 18) +#define MCHP_PCR_LED1 MCHP_PCR_ERB(3, 17) +#define MCHP_PCR_LED0 MCHP_PCR_ERB(3, 16) +#define MCHP_PCR_I2C3 MCHP_PCR_ERB(3, 15) +#define MCHP_PCR_I2C2 MCHP_PCR_ERB(3, 14) +#define MCHP_PCR_I2C1 MCHP_PCR_ERB(3, 13) +#define MCHP_PCR_RPMPWM0 MCHP_PCR_ERB(3, 12) +#define MCHP_PCR_KEYSCAN MCHP_PCR_ERB(3, 11) +#define MCHP_PCR_HTMR0 MCHP_PCR_ERB(3, 10) +#define MCHP_PCR_GPSPI0 MCHP_PCR_ERB(3, 9) +#define MCHP_PCR_PS2_0 MCHP_PCR_ERB(3, 5) +#define MCHP_PCR_ADC MCHP_PCR_ERB(3, 3) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) -#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) -#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) -#define MCHP_PCR_SLP_EN3_CRYPTO BIT(26) -#define MCHP_PCR_SLP_EN3_LED3 BIT(25) -#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) -#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) -#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) -#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) -#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) -#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) -#define MCHP_PCR_SLP_EN3_LED2 BIT(18) -#define MCHP_PCR_SLP_EN3_LED1 BIT(17) -#define MCHP_PCR_SLP_EN3_LED0 BIT(16) -#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) -#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) -#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) -#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12) -#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) -#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) -#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) -#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) -#define MCHP_PCR_SLP_EN3_ADC BIT(3) -#define MCHP_PCR_SLP_EN3_ALL_CRYPTO BIT(26) +#define MCHP_PCR_SLP_EN3_PWM9 BIT(31) +#define MCHP_PCR_SLP_EN3_CCT0 BIT(30) +#define MCHP_PCR_SLP_EN3_HTMR1 BIT(29) +#define MCHP_PCR_SLP_EN3_CRYPTO BIT(26) +#define MCHP_PCR_SLP_EN3_LED3 BIT(25) +#define MCHP_PCR_SLP_EN3_BTMR32_1 BIT(24) +#define MCHP_PCR_SLP_EN3_BTMR32_0 BIT(23) +#define MCHP_PCR_SLP_EN3_BTMR16_3 BIT(22) +#define MCHP_PCR_SLP_EN3_BTMR16_2 BIT(21) +#define MCHP_PCR_SLP_EN3_I2C4 BIT(20) +#define MCHP_PCR_SLP_EN3_BCM0 BIT(19) +#define MCHP_PCR_SLP_EN3_LED2 BIT(18) +#define MCHP_PCR_SLP_EN3_LED1 BIT(17) +#define MCHP_PCR_SLP_EN3_LED0 BIT(16) +#define MCHP_PCR_SLP_EN3_I2C3 BIT(15) +#define MCHP_PCR_SLP_EN3_I2C2 BIT(14) +#define MCHP_PCR_SLP_EN3_I2C1 BIT(13) +#define MCHP_PCR_SLP_EN3_RPM2PWM0 BIT(12) +#define MCHP_PCR_SLP_EN3_KEYSCAN BIT(11) +#define MCHP_PCR_SLP_EN3_HTMR0 BIT(10) +#define MCHP_PCR_SLP_EN3_GPSPI0 BIT(9) +#define MCHP_PCR_SLP_EN3_PS2_0 BIT(5) +#define MCHP_PCR_SLP_EN3_ADC BIT(3) +#define MCHP_PCR_SLP_EN3_ALL_CRYPTO BIT(26) /* all sleep enable 3 bits */ -#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff -#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9) +#define MCHP_PCR_SLP_EN3_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN3_PWM_ALL (MCHP_PCR_SLP_EN3_PWM9) /* PCR Sleep 4: Sleep Enable, Clock Required, Reset */ -#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(4, 22) -#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) -#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) -#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12) -#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11) -#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10) -#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) -#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7) -#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) -#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5) -#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4) -#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3) -#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2) -#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1) -#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0) +#define MCHP_PCR_GPSPI1 MCHP_PCR_ERB(4, 22) +#define MCHP_PCR_PSPI MCHP_PCR_ERB(4, 14) +#define MCHP_PCR_PROCHOT MCHP_PCR_ERB(4, 13) +#define MCHP_PCR_RCID2 MCHP_PCR_ERB(4, 12) +#define MCHP_PCR_RCID1 MCHP_PCR_ERB(4, 11) +#define MCHP_PCR_RCID0 MCHP_PCR_ERB(4, 10) +#define MCHP_PCR_QMSPI MCHP_PCR_ERB(4, 8) +#define MCHP_PCR_RPMPWM1 MCHP_PCR_ERB(4, 7) +#define MCHP_PCR_RTMR MCHP_PCR_ERB(4, 6) +#define MCHP_PCR_CNT16_3 MCHP_PCR_ERB(4, 5) +#define MCHP_PCR_CNT16_2 MCHP_PCR_ERB(4, 4) +#define MCHP_PCR_CNT16_1 MCHP_PCR_ERB(4, 3) +#define MCHP_PCR_CNT16_0 MCHP_PCR_ERB(4, 2) +#define MCHP_PCR_PWM11 MCHP_PCR_ERB(4, 1) +#define MCHP_PCR_PWM10 MCHP_PCR_ERB(4, 0) /* Command blocks to sleep */ -#define MCHP_PCR_SLP_EN4_GPSPI1 BIT(22) -#define MCHP_PCR_SLP_EN4_PSPI BIT(14) -#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) -#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) -#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) -#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) -#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) -#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) -#define MCHP_PCR_SLP_EN4_RTMR BIT(6) -#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) -#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) -#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) -#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) -#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) -#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) +#define MCHP_PCR_SLP_EN4_GPSPI1 BIT(22) +#define MCHP_PCR_SLP_EN4_PSPI BIT(14) +#define MCHP_PCR_SLP_EN4_PROCHOT BIT(13) +#define MCHP_PCR_SLP_EN4_RCID2 BIT(12) +#define MCHP_PCR_SLP_EN4_RCID1 BIT(11) +#define MCHP_PCR_SLP_EN4_RCID0 BIT(10) +#define MCHP_PCR_SLP_EN4_QMSPI BIT(8) +#define MCHP_PCR_SLP_EN4_RPMPWM1 BIT(7) +#define MCHP_PCR_SLP_EN4_RTMR BIT(6) +#define MCHP_PCR_SLP_EN4_CNT16_3 BIT(5) +#define MCHP_PCR_SLP_EN4_CNT16_2 BIT(4) +#define MCHP_PCR_SLP_EN4_CNT16_1 BIT(3) +#define MCHP_PCR_SLP_EN4_CNT16_0 BIT(2) +#define MCHP_PCR_SLP_EN4_PWM11 BIT(1) +#define MCHP_PCR_SLP_EN4_PWM10 BIT(0) /* all sleep enable 4 bits */ -#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff +#define MCHP_PCR_SLP_EN4_SLEEP 0xffffffff #define MCHP_PCR_SLP_EN4_PWM_ALL \ (MCHP_PCR_SLP_EN4_PWM10 | MCHP_PCR_SLP_EN4_PWM11) @@ -502,29 +501,29 @@ #define MCHP_PCR_SLP_EN4_WAKE (~(MCHP_PCR_SLP_EN4_SLEEP)) /* Bit defines for MCHP_PCR_PWR_RST_STS */ -#define MCHP_PWR_RST_STS_MASK_RO 0xc8c -#define MCHP_PWR_RST_STS_MASK_RWC 0x170 +#define MCHP_PWR_RST_STS_MASK_RO 0xc8c +#define MCHP_PWR_RST_STS_MASK_RWC 0x170 #define MCHP_PWR_RST_STS_MASK \ ((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC)) -#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ -#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ -#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ -#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ -#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ -#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ -#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */ -#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ -#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ +#define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ +#define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ +#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ +#define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ +#define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ +#define MCHP_PWR_RST_STS_VBAT BIT(5) /* R/WC */ +#define MCHP_PWR_RST_STS_VTR BIT(4) /* R/WC */ +#define MCHP_PWR_RST_STS_HOST BIT(3) /* RO */ +#define MCHP_PWR_RST_STS_VCC_PWRGD BIT(2) /* RO */ /* Bit defines for MCHP_PCR_PWR_RST_CTL */ -#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 -#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) -#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST 0 -#define MCHP_PCR_PWR_OK_INV_BITPOS 0 +#define MCHP_PCR_PWR_HOST_RST_SEL_BITPOS 8 +#define MCHP_PCR_PWR_HOST_RST_PCI_RESET BIT(8) +#define MCHP_PCR_PWR_HOST_RST_ESPI_PLTRST 0 +#define MCHP_PCR_PWR_OK_INV_BITPOS 0 /* Bit defines for MCHP_PCR_SYS_RST */ -#define MCHP_PCR_SYS_SOFT_RESET BIT(8) +#define MCHP_PCR_SYS_SOFT_RESET BIT(8) /* * PCR Peripheral Reset Lock register @@ -534,110 +533,110 @@ * register, write to PCR reset enable register(s), and * write a lock value. */ -#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84) -#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d -#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c +#define MCHP_PCR_RST_LOCK REG32(MCHP_PCR_BASE + 0x84) +#define MCHP_PCR_RST_LOCK_VAL 0xa6382d4d +#define MCHP_PCR_RST_UNLOCK_VAL 0xa6382d4c /* PCR VBAT soft reset. Trigger a VBAT reset */ -#define MCHP_PCR_VBAT_SRST REG32(MCHP_PCR_BASE + 0x88) -#define MCHP_PCR_VBAT_SRST_EN BIT(0) +#define MCHP_PCR_VBAT_SRST REG32(MCHP_PCR_BASE + 0x88) +#define MCHP_PCR_VBAT_SRST_EN BIT(0) /* PCR 32KHz clock source select */ -#define MCHP_PCR_CK32_SS REG32(MCHP_PCR_BASE + 0x8c) -#define MCHP_PCR_CK32_SEL_MASK GENMASK(1, 0) -#define MCHP_PCR_CK32_SEL_SIL 0 -#define MCHP_PCR_CK32_SEL_XTAL 1 -#define MCHP_PCR_CK32_SEL_PIN 2 -#define MCHP_PCR_CK32_SEL_OFF 3 +#define MCHP_PCR_CK32_SS REG32(MCHP_PCR_BASE + 0x8c) +#define MCHP_PCR_CK32_SEL_MASK GENMASK(1, 0) +#define MCHP_PCR_CK32_SEL_SIL 0 +#define MCHP_PCR_CK32_SEL_XTAL 1 +#define MCHP_PCR_CK32_SEL_PIN 2 +#define MCHP_PCR_CK32_SEL_OFF 3 /* PCR 32KHz period count (RO) */ -#define MCHP_PCR_CK32_PER_CNT REG32(MCHP_PCR_BASE + 0xc0) -#define MCHP_PCR_CD32_PER_CNT_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_PER_CNT REG32(MCHP_PCR_BASE + 0xc0) +#define MCHP_PCR_CD32_PER_CNT_MSK GENMASK(15, 0) /* PCR 32KHz high pulse count (RO) */ -#define MCHP_PCR_CK32_HP_CNT REG32(MCHP_PCR_BASE + 0xc4) -#define MCHP_PCR_CK32_HP_CNT_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_HP_CNT REG32(MCHP_PCR_BASE + 0xc4) +#define MCHP_PCR_CK32_HP_CNT_MSK GENMASK(15, 0) /* PCR 32KHz minimum acceptable period count */ -#define MCHP_PCR_CK32_MIN_PER_CNT REG32(MCHP_PCR_BASE + 0xc8) -#define MCHP_PCR_CK32_MIN_PER_CNT_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_MIN_PER_CNT REG32(MCHP_PCR_BASE + 0xc8) +#define MCHP_PCR_CK32_MIN_PER_CNT_MSK GENMASK(15, 0) /* PCR 32KHz maximum acceptable period count */ -#define MCHP_PCR_CK32_MAX_PER_CNT REG32(MCHP_PCR_BASE + 0xcc) -#define MCHP_PCR_CK32_MAX_PER_CNT_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_MAX_PER_CNT REG32(MCHP_PCR_BASE + 0xcc) +#define MCHP_PCR_CK32_MAX_PER_CNT_MSK GENMASK(15, 0) /* PCR 32KHz duty cycle variation count (RO) */ -#define MCHP_PCR_CK32_DC_VAR_CNT REG32(MCHP_PCR_BASE + 0xd0) -#define MCHP_PCR_CK32_DC_VAR_CNT_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_DC_VAR_CNT REG32(MCHP_PCR_BASE + 0xd0) +#define MCHP_PCR_CK32_DC_VAR_CNT_MSK GENMASK(15, 0) /* PCR 32KHz duty cycle variation acceptable maximum */ -#define MCHP_PCR_CK32_DC_VAR_MAX REG32(MCHP_PCR_BASE + 0xd4) -#define MCHP_PCR_CK32_DC_VAR_MAX_MSK GENMASK(15, 0) +#define MCHP_PCR_CK32_DC_VAR_MAX REG32(MCHP_PCR_BASE + 0xd4) +#define MCHP_PCR_CK32_DC_VAR_MAX_MSK GENMASK(15, 0) /* PCR 32KHz valid count */ -#define MCHP_PCR_CK32_VAL_CNT REG32(MCHP_PCR_BASE + 0xd8) -#define MCHP_PCR_CK32_VAL_CNT_MSK GENMASK(7, 0) +#define MCHP_PCR_CK32_VAL_CNT REG32(MCHP_PCR_BASE + 0xd8) +#define MCHP_PCR_CK32_VAL_CNT_MSK GENMASK(7, 0) /* PCR 32KHz valid count minimum */ -#define MCHP_PCR_CK32_MIN_VAL_CNT REG32(MCHP_PCR_BASE + 0xdc) -#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK GENMASK(7, 0) +#define MCHP_PCR_CK32_MIN_VAL_CNT REG32(MCHP_PCR_BASE + 0xdc) +#define MCHP_PCR_CK32_MIN_VAL_CNT_MSK GENMASK(7, 0) /* PCR 32KHz control */ -#define MCHP_PCR_CK32_CTRL REG32(MCHP_PCR_BASE + 0xe0) -#define MCHP_PCR_CK32_CTRL_MSK (GENMASK(2, 0) | BIT(4) | BIT(24)) -#define MCHP_PCR_CK32_CTRL_PER_EN BIT(0) -#define MCHP_PCR_CK32_CTRL_DC_EN BIT(1) -#define MCHP_PCR_CK32_CTRL_VAL_EN BIT(2) -#define MCHP_PCR_CK32_CTRL_SRC_SIL BIT(3) -#define MCHP_PCR_CK32_CTRL_CLR_CNT BIT(24) +#define MCHP_PCR_CK32_CTRL REG32(MCHP_PCR_BASE + 0xe0) +#define MCHP_PCR_CK32_CTRL_MSK (GENMASK(2, 0) | BIT(4) | BIT(24)) +#define MCHP_PCR_CK32_CTRL_PER_EN BIT(0) +#define MCHP_PCR_CK32_CTRL_DC_EN BIT(1) +#define MCHP_PCR_CK32_CTRL_VAL_EN BIT(2) +#define MCHP_PCR_CK32_CTRL_SRC_SIL BIT(3) +#define MCHP_PCR_CK32_CTRL_CLR_CNT BIT(24) /* PCR 32KHz interrupt status */ -#define MCHP_PCR_CK32_INTR_STS REG8(MCHP_PCR_BASE + 0xe4) +#define MCHP_PCR_CK32_INTR_STS REG8(MCHP_PCR_BASE + 0xe4) /* PCR 32KHz interrupt enable */ -#define MCHP_PCR_CK32_INTR_EN REG8(MCHP_PCR_BASE + 0xe8) -#define MCHP_PCR_CK32_INTR_PULSE_RDY BIT(0) -#define MCHP_PCR_CK32_INTR_PASS_PER BIT(1) -#define MCHP_PCR_CK32_INTR_PASS_DUTY BIT(2) -#define MCHP_PCR_CK32_INTR_FAIL BIT(3) -#define MCHP_PCR_CK32_INTR_STALL BIT(4) -#define MCHP_PCR_CK32_INTR_VALID BIT(5) -#define MCHP_PCR_CK32_INTR_UNWELL BIT(6) +#define MCHP_PCR_CK32_INTR_EN REG8(MCHP_PCR_BASE + 0xe8) +#define MCHP_PCR_CK32_INTR_PULSE_RDY BIT(0) +#define MCHP_PCR_CK32_INTR_PASS_PER BIT(1) +#define MCHP_PCR_CK32_INTR_PASS_DUTY BIT(2) +#define MCHP_PCR_CK32_INTR_FAIL BIT(3) +#define MCHP_PCR_CK32_INTR_STALL BIT(4) +#define MCHP_PCR_CK32_INTR_VALID BIT(5) +#define MCHP_PCR_CK32_INTR_UNWELL BIT(6) /* EC Subsystem */ -#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) -#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) -#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) -#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) -#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) -#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) -#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) -#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40) -#define MCHP_EC_VCI_FW_OVRD REG32(MCHP_EC_BASE + 0x50) -#define MCHP_EC_BROM_STS REG32(MCHP_EC_BASE + 0x54) -#define MCHP_EC_VW_SRC_CFG REG32(MCHP_EC_BASE + 0x90) -#define MCHP_EC_CMP_CTRL REG32(MCHP_EC_BASE + 0x94) -#define MCHP_EC_CMP_SLP_CTRL REG32(MCHP_EC_BASE + 0x98) +#define MCHP_EC_AHB_ERR REG32(MCHP_EC_BASE + 0x04) +#define MCHP_EC_ID_RO REG32(MCHP_EC_BASE + 0x10) +#define MCHP_EC_AHB_ERR_EN REG32(MCHP_EC_BASE + 0x14) +#define MCHP_EC_INT_CTRL REG32(MCHP_EC_BASE + 0x18) +#define MCHP_EC_TRACE_EN REG32(MCHP_EC_BASE + 0x1c) +#define MCHP_EC_JTAG_EN REG32(MCHP_EC_BASE + 0x20) +#define MCHP_EC_WDT_CNT REG32(MCHP_EC_BASE + 0x28) +#define MCHP_EC_PECI_DISABLE REG8(MCHP_EC_BASE + 0x40) +#define MCHP_EC_VCI_FW_OVRD REG32(MCHP_EC_BASE + 0x50) +#define MCHP_EC_BROM_STS REG32(MCHP_EC_BASE + 0x54) +#define MCHP_EC_VW_SRC_CFG REG32(MCHP_EC_BASE + 0x90) +#define MCHP_EC_CMP_CTRL REG32(MCHP_EC_BASE + 0x94) +#define MCHP_EC_CMP_SLP_CTRL REG32(MCHP_EC_BASE + 0x98) /* AHB ERR Disable bit[0]=0(enable), 1(disable) */ -#define MCHP_EC_AHB_ERROR_ENABLE 0 -#define MCHP_EC_AHB_ERROR_DISABLE 1 +#define MCHP_EC_AHB_ERROR_ENABLE 0 +#define MCHP_EC_AHB_ERROR_DISABLE 1 /* MCHP_EC_JTAG_EN bit definitions */ -#define MCHP_JTAG_ENABLE 0x01 +#define MCHP_JTAG_ENABLE 0x01 /* bits [2:1] */ -#define MCHP_JTAG_MODE_4PIN 0x00 +#define MCHP_JTAG_MODE_4PIN 0x00 /* ARM 2-pin SWD plus 1-pin Serial Wire Viewer (ITM) */ -#define MCHP_JTAG_MODE_SWD_SWV 0x02 +#define MCHP_JTAG_MODE_SWD_SWV 0x02 /* ARM 2-pin SWD with no SWV */ -#define MCHP_JTAG_MODE_SWD 0x04 +#define MCHP_JTAG_MODE_SWD 0x04 /* EC Interrupt aggregator (ECIA) */ -#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ -#define MCHP_INT_GIRQ_FIRST 8 -#define MCHP_INT_GIRQ_LAST 26 -#define MCHP_INT_GIRQ_NUM (26-8+1) +#define MCHP_INT_GIRQ_LEN 20 /* 5 32-bit registers */ +#define MCHP_INT_GIRQ_FIRST 8 +#define MCHP_INT_GIRQ_LAST 26 +#define MCHP_INT_GIRQ_NUM (26 - 8 + 1) /* MCHP_INT_GIRQ_FIRST <= x <= MCHP_INT_GIRQ_LAST */ -#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x) - 8) * MCHP_INT_GIRQ_LEN)) +#define MCHP_INTx_BASE(x) (MCHP_INT_BASE + (((x)-8) * MCHP_INT_GIRQ_LEN)) /* * GPIO GIRQ's are not direct capable @@ -651,11 +650,13 @@ * GIRQ22 wake peripheral clock only * GIRQ24, GIRQ25 eSPI host to endpoint virtual wires */ -#define MCHP_INT_AGGR_ONLY_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\ - BIT(12) | BIT(22) | BIT(24) | BIT(25) | BIT(26)) +#define MCHP_INT_AGGR_ONLY_BITMAP \ + (BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(22) | BIT(24) | \ + BIT(25) | BIT(26)) -#define MCHP_INT_DIRECT_CAPABLE_BITMAP (BIT(13) | BIT(14) | BIT(15) |\ - BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23)) +#define MCHP_INT_DIRECT_CAPABLE_BITMAP \ + (BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | \ + BIT(20) | BIT(21) | BIT(23)) /* GIRQ13 I2C controllers 0 - 4. Direct capable */ #define MCHP_INT13_I2C(x) BIT(x) @@ -664,142 +665,142 @@ #define MCHP_INT14_DMA(x) BIT(x) /* GIQ15 interrupt sources. Direct capable */ -#define MCHP_INT15_UART_0 BIT(0) -#define MCHP_INT15_UART_1 BIT(1) -#define MCHP_INT15_EMI_0 BIT(2) -#define MCHP_INT15_EMI_1 BIT(3) -#define MCHP_INT15_EMI_2 BIT(4) -#define MCHP_INT15_ACPI_EC0_IBF BIT(5) -#define MCHP_INT15_ACPI_EC0_OBE BIT(6) -#define MCHP_INT15_ACPI_EC1_IBF BIT(7) -#define MCHP_INT15_ACPI_EC1_OBE BIT(8) -#define MCHP_INT15_ACPI_EC2_IBF BIT(9) -#define MCHP_INT15_ACPI_EC2_OBE BIT(10) -#define MCHP_INT15_ACPI_EC3_IBF BIT(11) -#define MCHP_INT15_ACPI_EC3_OBE BIT(12) -#define MCHP_INT15_ACPI_EC4_IBF BIT(13) -#define MCHP_INT15_ACPI_EC4_OBE BIT(14) -#define MCHP_INT15_ACPI_PM1_CTL BIT(15) -#define MCHP_INT15_ACPI_PM1_EN BIT(16) -#define MCHP_INT15_ACPI_PM1_STS BIT(17) -#define MCHP_INT15_8042_OBE BIT(18) -#define MCHP_INT15_8042_IBF BIT(19) -#define MCHP_INT15_MAILBOX BIT(20) -#define MCHP_INT15_BDP0 BIT(22) +#define MCHP_INT15_UART_0 BIT(0) +#define MCHP_INT15_UART_1 BIT(1) +#define MCHP_INT15_EMI_0 BIT(2) +#define MCHP_INT15_EMI_1 BIT(3) +#define MCHP_INT15_EMI_2 BIT(4) +#define MCHP_INT15_ACPI_EC0_IBF BIT(5) +#define MCHP_INT15_ACPI_EC0_OBE BIT(6) +#define MCHP_INT15_ACPI_EC1_IBF BIT(7) +#define MCHP_INT15_ACPI_EC1_OBE BIT(8) +#define MCHP_INT15_ACPI_EC2_IBF BIT(9) +#define MCHP_INT15_ACPI_EC2_OBE BIT(10) +#define MCHP_INT15_ACPI_EC3_IBF BIT(11) +#define MCHP_INT15_ACPI_EC3_OBE BIT(12) +#define MCHP_INT15_ACPI_EC4_IBF BIT(13) +#define MCHP_INT15_ACPI_EC4_OBE BIT(14) +#define MCHP_INT15_ACPI_PM1_CTL BIT(15) +#define MCHP_INT15_ACPI_PM1_EN BIT(16) +#define MCHP_INT15_ACPI_PM1_STS BIT(17) +#define MCHP_INT15_8042_OBE BIT(18) +#define MCHP_INT15_8042_IBF BIT(19) +#define MCHP_INT15_MAILBOX BIT(20) +#define MCHP_INT15_BDP0 BIT(22) /* GIRQ16 interrupt sources. Direct capable */ -#define MCHP_INT16_PKE_DONE BIT(0) -#define MCHP_INT16_RNG_DONE BIT(2) -#define MCHP_INT16_AESH_DONE BIT(3) +#define MCHP_INT16_PKE_DONE BIT(0) +#define MCHP_INT16_RNG_DONE BIT(2) +#define MCHP_INT16_AESH_DONE BIT(3) /* GIR17 interrupt sources. Direct capable */ -#define MCHP_INT17_PECI BIT(0) -#define MCHP_INT17_TACH_0 BIT(1) -#define MCHP_INT17_TACH_1 BIT(2) -#define MCHP_INT17_TACH_2 BIT(3) -#define MCHP_INT17_TACH_3 BIT(4) -#define MCHP_INT17_ADC_SINGLE BIT(8) -#define MCHP_INT17_ADC_REPEAT BIT(9) -#define MCHP_INT17_RCID_0 BIT(10) -#define MCHP_INT17_RCID_1 BIT(11) -#define MCHP_INT17_RCID_2 BIT(12) -#define MCHP_INT17_LED_WDT_0 BIT(13) -#define MCHP_INT17_LED_WDT_1 BIT(14) -#define MCHP_INT17_LED_WDT_2 BIT(15) -#define MCHP_INT17_LED_WDT_3 BIT(16) -#define MCHP_INT17_PROCHOT BIT(17) -#define MCHP_INT17_RPM2PWM0_FAIL BIT(20) -#define MCHP_INT17_RPM2PWM0_STALL BIT(21) -#define MCHP_INT17_RPM2PWM1_FAIL BIT(22) -#define MCHP_INT17_RPM2PWM1_STALL BIT(23) +#define MCHP_INT17_PECI BIT(0) +#define MCHP_INT17_TACH_0 BIT(1) +#define MCHP_INT17_TACH_1 BIT(2) +#define MCHP_INT17_TACH_2 BIT(3) +#define MCHP_INT17_TACH_3 BIT(4) +#define MCHP_INT17_ADC_SINGLE BIT(8) +#define MCHP_INT17_ADC_REPEAT BIT(9) +#define MCHP_INT17_RCID_0 BIT(10) +#define MCHP_INT17_RCID_1 BIT(11) +#define MCHP_INT17_RCID_2 BIT(12) +#define MCHP_INT17_LED_WDT_0 BIT(13) +#define MCHP_INT17_LED_WDT_1 BIT(14) +#define MCHP_INT17_LED_WDT_2 BIT(15) +#define MCHP_INT17_LED_WDT_3 BIT(16) +#define MCHP_INT17_PROCHOT BIT(17) +#define MCHP_INT17_RPM2PWM0_FAIL BIT(20) +#define MCHP_INT17_RPM2PWM0_STALL BIT(21) +#define MCHP_INT17_RPM2PWM1_FAIL BIT(22) +#define MCHP_INT17_RPM2PWM1_STALL BIT(23) /* GIRQ18 interrupt sources. Direct capable */ -#define MCHP_INT18_SPIEP BIT(0) -#define MCHP_INT18_QMSPI BIT(1) -#define MCHP_INT18_GPSPI0_TXBE BIT(2) -#define MCHP_INT18_GPSPI0_RXBF BIT(3) -#define MCHP_INT18_GPSPI1_TXBE BIT(4) -#define MCHP_INT18_GPSPI1_RXBF BIT(5) -#define MCHP_INT18_BCM0_BUSY BIT(6) -#define MCHP_INT18_BCM0_ERR BIT(7) -#define MCHP_INT18_PS2_0 BIT(10) -#define MCHP_INT18_PSPI BIT(13) -#define MCHP_INT18_CCT BIT(20) -#define MCHP_INT18_CCT_CAP0 BIT(21) -#define MCHP_INT18_CCT_CAP1 BIT(22) -#define MCHP_INT18_CCT_CAP2 BIT(23) -#define MCHP_INT18_CCT_CAP3 BIT(24) -#define MCHP_INT18_CCT_CAP4 BIT(25) -#define MCHP_INT18_CCT_CAP6 BIT(26) -#define MCHP_INT18_CCT_CMP0 BIT(27) -#define MCHP_INT18_CCT_CMP1 BIT(28) +#define MCHP_INT18_SPIEP BIT(0) +#define MCHP_INT18_QMSPI BIT(1) +#define MCHP_INT18_GPSPI0_TXBE BIT(2) +#define MCHP_INT18_GPSPI0_RXBF BIT(3) +#define MCHP_INT18_GPSPI1_TXBE BIT(4) +#define MCHP_INT18_GPSPI1_RXBF BIT(5) +#define MCHP_INT18_BCM0_BUSY BIT(6) +#define MCHP_INT18_BCM0_ERR BIT(7) +#define MCHP_INT18_PS2_0 BIT(10) +#define MCHP_INT18_PSPI BIT(13) +#define MCHP_INT18_CCT BIT(20) +#define MCHP_INT18_CCT_CAP0 BIT(21) +#define MCHP_INT18_CCT_CAP1 BIT(22) +#define MCHP_INT18_CCT_CAP2 BIT(23) +#define MCHP_INT18_CCT_CAP3 BIT(24) +#define MCHP_INT18_CCT_CAP4 BIT(25) +#define MCHP_INT18_CCT_CAP6 BIT(26) +#define MCHP_INT18_CCT_CMP0 BIT(27) +#define MCHP_INT18_CCT_CMP1 BIT(28) /* GIRQ19 interrupt sources. Direct capable */ -#define MCHP_INT19_ESPI_PC BIT(0) -#define MCHP_INT19_ESPI_BM1 BIT(1) -#define MCHP_INT19_ESPI_BM2 BIT(2) -#define MCHP_INT19_ESPI_LTR BIT(3) -#define MCHP_INT19_ESPI_OOB_TX BIT(4) -#define MCHP_INT19_ESPI_OOB_RX BIT(5) -#define MCHP_INT19_ESPI_FC BIT(6) -#define MCHP_INT19_ESPI_RESET BIT(7) -#define MCHP_INT19_ESPI_VW_EN BIT(8) -#define MCHP_INT19_ESPI_SAF BIT(9) -#define MCHP_INT19_ESPI_SAF_ERR BIT(10) -#define MCHP_INT19_ESPI_SAF_CACHE BIT(11) +#define MCHP_INT19_ESPI_PC BIT(0) +#define MCHP_INT19_ESPI_BM1 BIT(1) +#define MCHP_INT19_ESPI_BM2 BIT(2) +#define MCHP_INT19_ESPI_LTR BIT(3) +#define MCHP_INT19_ESPI_OOB_TX BIT(4) +#define MCHP_INT19_ESPI_OOB_RX BIT(5) +#define MCHP_INT19_ESPI_FC BIT(6) +#define MCHP_INT19_ESPI_RESET BIT(7) +#define MCHP_INT19_ESPI_VW_EN BIT(8) +#define MCHP_INT19_ESPI_SAF BIT(9) +#define MCHP_INT19_ESPI_SAF_ERR BIT(10) +#define MCHP_INT19_ESPI_SAF_CACHE BIT(11) /* GIRQ20 interrupt sources. Direct capable */ -#define MCHP_INT20_STAP_OBF BIT(0) -#define MCHP_INT20_STAP_IBF BIT(1) -#define MCHP_INT20_STAP_WAKE BIT(2) -#define MCHP_INT20_OTP BIT(3) -#define MCHP_INT20_ISPI BIT(8) -#define MCHP_INT20_CLK32K_MON BIT(9) +#define MCHP_INT20_STAP_OBF BIT(0) +#define MCHP_INT20_STAP_IBF BIT(1) +#define MCHP_INT20_STAP_WAKE BIT(2) +#define MCHP_INT20_OTP BIT(3) +#define MCHP_INT20_ISPI BIT(8) +#define MCHP_INT20_CLK32K_MON BIT(9) /* GIRQ21 interrupt sources. Direct capable */ -#define MCHP_INT21_WDG BIT(2) -#define MCHP_INT21_WEEK_ALARM BIT(3) -#define MCHP_INT21_WEEK_SUB BIT(4) -#define MCHP_INT21_WEEK_1SEC BIT(5) -#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) -#define MCHP_INT21_WEEK_PWR_PRES BIT(7) -#define MCHP_INT21_RTC BIT(8) -#define MCHP_INT21_RTC_ALARM BIT(9) -#define MCHP_INT21_VCI_OVRD BIT(10) -#define MCHP_INT21_VCI_IN0 BIT(11) -#define MCHP_INT21_VCI_IN1 BIT(12) -#define MCHP_INT21_VCI_IN2 BIT(13) -#define MCHP_INT21_VCI_IN3 BIT(14) -#define MCHP_INT21_VCI_IN4 BIT(15) -#define MCHP_INT21_PS2_0A_WAKE BIT(18) -#define MCHP_INT21_PS2_0B_WAKE BIT(19) -#define MCHP_INT21_KEYSCAN BIT(25) -#define MCHP_INT21_GLUE BIT(26) +#define MCHP_INT21_WDG BIT(2) +#define MCHP_INT21_WEEK_ALARM BIT(3) +#define MCHP_INT21_WEEK_SUB BIT(4) +#define MCHP_INT21_WEEK_1SEC BIT(5) +#define MCHP_INT21_WEEK_1SEC_SUB BIT(6) +#define MCHP_INT21_WEEK_PWR_PRES BIT(7) +#define MCHP_INT21_RTC BIT(8) +#define MCHP_INT21_RTC_ALARM BIT(9) +#define MCHP_INT21_VCI_OVRD BIT(10) +#define MCHP_INT21_VCI_IN0 BIT(11) +#define MCHP_INT21_VCI_IN1 BIT(12) +#define MCHP_INT21_VCI_IN2 BIT(13) +#define MCHP_INT21_VCI_IN3 BIT(14) +#define MCHP_INT21_VCI_IN4 BIT(15) +#define MCHP_INT21_PS2_0A_WAKE BIT(18) +#define MCHP_INT21_PS2_0B_WAKE BIT(19) +#define MCHP_INT21_KEYSCAN BIT(25) +#define MCHP_INT21_GLUE BIT(26) /* GIRQ22 peripheral wake only. GIRQ22 not connected to NVIC */ -#define MCHP_INT22_WAKE_ONLY_SPIEP BIT(0) -#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) -#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) -#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) -#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) -#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5) -#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) -#define MCHP_INT22_WAKE_ONLY_STAP BIT(15) +#define MCHP_INT22_WAKE_ONLY_SPIEP BIT(0) +#define MCHP_INT22_WAKE_ONLY_I2C0 BIT(1) +#define MCHP_INT22_WAKE_ONLY_I2C1 BIT(2) +#define MCHP_INT22_WAKE_ONLY_I2C2 BIT(3) +#define MCHP_INT22_WAKE_ONLY_I2C3 BIT(4) +#define MCHP_INT22_WAKE_ONLY_I2C4 BIT(5) +#define MCHP_INT22_WAKE_ONLY_ESPI BIT(9) +#define MCHP_INT22_WAKE_ONLY_STAP BIT(15) /* GIRQ23 sources. Direct capable */ -#define MCHP_INT23_BTMR16_0 BIT(0) -#define MCHP_INT23_BTMR16_1 BIT(1) -#define MCHP_INT23_BTMR16_2 BIT(2) -#define MCHP_INT23_BTMR16_3 BIT(3) -#define MCHP_INT23_BTMR32_0 BIT(4) -#define MCHP_INT23_BTMR32_1 BIT(5) -#define MCHP_INT23_CNT16_0 BIT(6) -#define MCHP_INT23_CNT16_1 BIT(7) -#define MCHP_INT23_CNT16_2 BIT(8) -#define MCHP_INT23_CNT16_3 BIT(9) -#define MCHP_INT21_RTMR BIT(10) -#define MCHP_INT21_HTMR_0 BIT(16) -#define MCHP_INT21_HTMR_1 BIT(17) +#define MCHP_INT23_BTMR16_0 BIT(0) +#define MCHP_INT23_BTMR16_1 BIT(1) +#define MCHP_INT23_BTMR16_2 BIT(2) +#define MCHP_INT23_BTMR16_3 BIT(3) +#define MCHP_INT23_BTMR32_0 BIT(4) +#define MCHP_INT23_BTMR32_1 BIT(5) +#define MCHP_INT23_CNT16_0 BIT(6) +#define MCHP_INT23_CNT16_1 BIT(7) +#define MCHP_INT23_CNT16_2 BIT(8) +#define MCHP_INT23_CNT16_3 BIT(9) +#define MCHP_INT21_RTMR BIT(10) +#define MCHP_INT21_HTMR_0 BIT(16) +#define MCHP_INT21_HTMR_1 BIT(17) /* GIRQ24 sources. Master-to-Slave v=[0:6], Source=[0:3] */ #define MCHP_INT24_MSVW_SRC(v, s) (1ul << ((4 * (v)) + (s))) @@ -808,19 +809,18 @@ #define MCHP_INT25_MSVW_SRC(v, s) (1ul << ((4 * ((v)-7)) + (s))) /* UART Peripheral 0 <= x <= 1 */ -#define MCHP_UART_INSTANCES 2 -#define MCHP_UART_SPACING 0x400 -#define MCHP_UART_CFG_OFS 0x300 +#define MCHP_UART_INSTANCES 2 +#define MCHP_UART_SPACING 0x400 +#define MCHP_UART_CFG_OFS 0x300 #define MCHP_UART_CONFIG_BASE(x) \ - (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_RUNTIME_BASE(x) \ - (MCHP_UART0_BASE + ((x) * MCHP_UART_SPACING)) -#define MCHP_UART_GIRQ 15 -#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) -#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) -#define MCHP_UART_GIRQ_BIT(x) BIT(x) + (MCHP_UART0_BASE + MCHP_UART_CFG_OFS + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_RUNTIME_BASE(x) (MCHP_UART0_BASE + ((x)*MCHP_UART_SPACING)) +#define MCHP_UART_GIRQ 15 +#define MCHP_UART0_GIRQ_BIT (MCHP_INT15_UART_0) +#define MCHP_UART1_GIRQ_BIT (MCHP_INT15_UART_1) +#define MCHP_UART_GIRQ_BIT(x) BIT(x) /* Bit defines for MCHP_UARTx_LSR */ -#define MCHP_LSR_TX_EMPTY BIT(5) +#define MCHP_LSR_TX_EMPTY BIT(5) /* * GPIO @@ -851,180 +851,174 @@ * Control 1 Address = 0x40081000 + (((4 << 5) + 0x1d) << 2) = 0x40081274 * */ -#define MCHP_GPIO_CTL(port, id) REG32(MCHP_GPIO_BASE + \ - (((port << 5) + id) << 2)) +#define MCHP_GPIO_CTL(port, id) \ + REG32(MCHP_GPIO_BASE + (((port << 5) + id) << 2)) /* MCHP implements 6 GPIO ports */ -#define MCHP_GPIO_MAX_PORT 6 -#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT +#define MCHP_GPIO_MAX_PORT 6 +#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT /* * In MECxxxx documentation GPIO numbers are octal, each control * register is located on a 32-bit boundary. */ -#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + \ - ((gpio_num) << 2)) +#define MCHP_GPIO_CTRL(gpio_num) REG32(MCHP_GPIO_BASE + ((gpio_num) << 2)) /* * GPIO control register bit fields */ -#define MCHP_GPIO_CTRL_PUD_BITPOS 0 -#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 -#define MCHP_GPIO_CTRL_PUD_MASK 0x03 -#define MCHP_GPIO_CTRL_PUD_NONE 0x00 -#define MCHP_GPIO_CTRL_PUD_PU 0x01 -#define MCHP_GPIO_CTRL_PUD_PD 0x02 -#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 -#define MCHP_GPIO_CTRL_PWR_BITPOS 2 -#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 -#define MCHP_GPIO_CTRL_PWR_MASK GENMASK(2, 1) -#define MCHP_GPIO_CTRL_PWR_VTR 0 -#define MCHP_GPIO_CTRL_PWR_OFF (0x02U << 2) -#define MCHP_GPIO_INTDET_MASK 0xF0U -#define MCHP_GPIO_INTDET_LVL_LO 0x00 -#define MCHP_GPIO_INTDET_LVL_HI 0x10U -#define MCHP_GPIO_INTDET_DISABLED 0x40U -#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0U -#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0U -#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0U -#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) -#define MCHP_GPIO_PUSH_PULL 0U -#define MCHP_GPIO_OPEN_DRAIN BIT(8) -#define MCHP_GPIO_INPUT 0U -#define MCHP_GPIO_OUTPUT BIT(9) -#define MCHP_GPIO_OUTSET_CTRL 0U -#define MCHP_GPIO_OUTSEL_PAR BIT(10) -#define MCHP_GPIO_POLARITY_NINV 0U -#define MCHP_GPIO_POLARITY_INV BIT(11) -#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x07U -#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x07U << 12) -#define MCHP_GPIO_CTRL_FUNC_GPIO 0 -#define MCHP_GPIO_CTRL_FUNC_1 (1U << 12) -#define MCHP_GPIO_CTRL_FUNC_2 (2U << 12) -#define MCHP_GPIO_CTRL_FUNC_3 (3U << 12) -#define MCHP_GPIO_CTRL_FUNC_4 (4U << 12) -#define MCHP_GPIO_CTRL_FUNC_5 (5U << 12) -#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) +#define MCHP_GPIO_CTRL_PUD_BITPOS 0 +#define MCHP_GPIO_CTRL_PUD_MASK0 0x03 +#define MCHP_GPIO_CTRL_PUD_MASK 0x03 +#define MCHP_GPIO_CTRL_PUD_NONE 0x00 +#define MCHP_GPIO_CTRL_PUD_PU 0x01 +#define MCHP_GPIO_CTRL_PUD_PD 0x02 +#define MCHP_GPIO_CTRL_PUD_KEEPER 0x03 +#define MCHP_GPIO_CTRL_PWR_BITPOS 2 +#define MCHP_GPIO_CTRL_PWR_MASK0 0x03 +#define MCHP_GPIO_CTRL_PWR_MASK GENMASK(2, 1) +#define MCHP_GPIO_CTRL_PWR_VTR 0 +#define MCHP_GPIO_CTRL_PWR_OFF (0x02U << 2) +#define MCHP_GPIO_INTDET_MASK 0xF0U +#define MCHP_GPIO_INTDET_LVL_LO 0x00 +#define MCHP_GPIO_INTDET_LVL_HI 0x10U +#define MCHP_GPIO_INTDET_DISABLED 0x40U +#define MCHP_GPIO_INTDET_EDGE_RIS 0xD0U +#define MCHP_GPIO_INTDET_EDGE_FALL 0xE0U +#define MCHP_GPIO_INTDET_EDGE_BOTH 0xF0U +#define MCHP_GPIO_INTDET_EDGE_EN BIT(7) +#define MCHP_GPIO_PUSH_PULL 0U +#define MCHP_GPIO_OPEN_DRAIN BIT(8) +#define MCHP_GPIO_INPUT 0U +#define MCHP_GPIO_OUTPUT BIT(9) +#define MCHP_GPIO_OUTSET_CTRL 0U +#define MCHP_GPIO_OUTSEL_PAR BIT(10) +#define MCHP_GPIO_POLARITY_NINV 0U +#define MCHP_GPIO_POLARITY_INV BIT(11) +#define MCHP_GPIO_CTRL_ALT_FUNC_BITPOS 12 +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK0 0x07U +#define MCHP_GPIO_CTRL_ALT_FUNC_MASK (0x07U << 12) +#define MCHP_GPIO_CTRL_FUNC_GPIO 0 +#define MCHP_GPIO_CTRL_FUNC_1 (1U << 12) +#define MCHP_GPIO_CTRL_FUNC_2 (2U << 12) +#define MCHP_GPIO_CTRL_FUNC_3 (3U << 12) +#define MCHP_GPIO_CTRL_FUNC_4 (4U << 12) +#define MCHP_GPIO_CTRL_FUNC_5 (5U << 12) +#define MCHP_GPIO_CTRL_OUT_LVL BIT(16) /* MEC172x implements input pad disable */ -#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 -#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15) +#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 +#define MCHP_GPIO_CTRL_DIS_INPUT_BIT BIT(15) /* * GPIO Parallel Input and Output registers. * gpio_bank in [0, 5] */ -#define MCHP_GPIO_PARIN(bank) \ - REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) -#define MCHP_GPIO_PAROUT(bank) \ - REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) +#define MCHP_GPIO_PARIN(bank) REG32(MCHP_GPIO_BASE + 0x0300 + ((bank) << 2)) +#define MCHP_GPIO_PAROUT(bank) REG32(MCHP_GPIO_BASE + 0x0380 + ((bank) << 2)) /* Basic timers */ -#define MCHP_TMR_SPACING 0x20 -#define MCHP_TMR16_INSTANCES 4 -#define MCHP_TMR32_INSTANCES 2 -#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) -#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) -#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n) * MCHP_TMR_SPACING) -#define MCHP_TMR16_GIRQ 23 -#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) -#define MCHP_TMR32_GIRQ 23 -#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) +#define MCHP_TMR_SPACING 0x20 +#define MCHP_TMR16_INSTANCES 4 +#define MCHP_TMR32_INSTANCES 2 +#define MCHP_TMR16_MAX (MCHP_TMR16_INSTANCES) +#define MCHP_TMR32_MAX (MCHP_TMR32_INSTANCES) +#define MCHP_TMR16_BASE(n) (MCHP_TMR16_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR32_BASE(n) (MCHP_TMR32_0_BASE + (n)*MCHP_TMR_SPACING) +#define MCHP_TMR16_GIRQ 23 +#define MCHP_TMR16_GIRQ_BIT(n) BIT(0 + (n)) +#define MCHP_TMR32_GIRQ 23 +#define MCHP_TMR32_GIRQ_BIT(n) BIT(4 + (n)) /* 16-bit Counter/timer */ -#define MCHP_CNT16_SPACING 0x20 -#define MCHP_CNT16_INSTANCES 4 -#define MCHP_CNT16_BASE(n) \ - (MCHP_CNT16_0_BASE + (n) * MCHP_CNT16_SPACING) -#define MCHP_CNT16_GIRQ 23 -#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x)) +#define MCHP_CNT16_SPACING 0x20 +#define MCHP_CNT16_INSTANCES 4 +#define MCHP_CNT16_BASE(n) (MCHP_CNT16_0_BASE + (n)*MCHP_CNT16_SPACING) +#define MCHP_CNT16_GIRQ 23 +#define MCHP_CNT16_GIRQ_BIT(x) BIT(6 + (x)) /* RTimer */ -#define MCHP_RTMR_GIRQ 21 -#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR +#define MCHP_RTMR_GIRQ 21 +#define MCHP_RTMR_GIRQ_BIT(x) MCHP_INT21_RTMR /* Watchdog */ /* MEC152x specific registers */ -#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10) -#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14) +#define MCHP_WDG_STATUS REG32(MCHP_WDG_BASE + 0x10) +#define MCHP_WDG_IEN REG32(MCHP_WDG_BASE + 0x14) /* Status */ -#define MCHP_WDG_STS_IRQ BIT(0) +#define MCHP_WDG_STS_IRQ BIT(0) /* Interrupt enable */ -#define MCHP_WDG_IEN_IRQ_EN BIT(0) -#define MCHP_WDG_GIRQ 21 -#define MCHP_WDG_GIRQ_BIT BIT(2) +#define MCHP_WDG_IEN_IRQ_EN BIT(0) +#define MCHP_WDG_GIRQ 21 +#define MCHP_WDG_GIRQ_BIT BIT(2) /* Control register has a bit to enable IRQ generation */ -#define MCHP_WDG_RESET_IRQ_EN BIT(9) +#define MCHP_WDG_RESET_IRQ_EN BIT(9) /* VBAT */ -#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) -#define MCHP_VBAT_CSS REG32(MCHP_VBAT_BASE + 0x8) -#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) -#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) -#define MCHP_VBAT_ROM_FEAT REG32(MCHP_VBAT_BASE + 0x28) -#define MCHP_VBAT_EMB_DEBOUNCE_EN REG32(MCHP_VBAT_BASE + 0x34) +#define MCHP_VBAT_STS REG32(MCHP_VBAT_BASE + 0x0) +#define MCHP_VBAT_CSS REG32(MCHP_VBAT_BASE + 0x8) +#define MCHP_VBAT_MONOTONIC_CTR_LO REG32(MCHP_VBAT_BASE + 0x20) +#define MCHP_VBAT_MONOTONIC_CTR_HI REG32(MCHP_VBAT_BASE + 0x24) +#define MCHP_VBAT_ROM_FEAT REG32(MCHP_VBAT_BASE + 0x28) +#define MCHP_VBAT_EMB_DEBOUNCE_EN REG32(MCHP_VBAT_BASE + 0x34) /* read 32-bit word at 32-bit offset x where 0 <= x <= 32 */ -#define MCHP_VBAT_RAM_SIZE 128 -#define MCHP_VBAT_RAM(wnum) \ - REG32(MCHP_VBAT_RAM_BASE + ((wnum) * 4)) -#define MCHP_VBAT_RAM8(bnum) \ - REG8(MCHP_VBAT_RAM_BASE + (bnum)) -#define MCHP_VBAT_VWIRE_BACKUP 30 +#define MCHP_VBAT_RAM_SIZE 128 +#define MCHP_VBAT_RAM(wnum) REG32(MCHP_VBAT_RAM_BASE + ((wnum)*4)) +#define MCHP_VBAT_RAM8(bnum) REG8(MCHP_VBAT_RAM_BASE + (bnum)) +#define MCHP_VBAT_VWIRE_BACKUP 30 /* * Miscellaneous firmware control fields * scratch pad index cannot be more than 32 as * MEC152x has 64 bytes = 16 words of scratch RAM */ -#define MCHP_IMAGETYPE_IDX 31 +#define MCHP_IMAGETYPE_IDX 31 /* Bit definition for MCHP_VBAT_STS */ -#define MCHP_VBAT_STS_SOFTRESET BIT(2) -#define MCHP_VBAT_STS_RESETI BIT(4) -#define MCHP_VBAT_STS_WDT BIT(5) -#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) -#define MCHP_VBAT_STS_VBAT_RST BIT(7) -#define MCHP_VBAT_STS_ANY_RST 0xF4u +#define MCHP_VBAT_STS_SOFTRESET BIT(2) +#define MCHP_VBAT_STS_RESETI BIT(4) +#define MCHP_VBAT_STS_WDT BIT(5) +#define MCHP_VBAT_STS_SYSRESETREQ BIT(6) +#define MCHP_VBAT_STS_VBAT_RST BIT(7) +#define MCHP_VBAT_STS_ANY_RST 0xF4u /* Bit definitions for MCHP_VBAT_CSS */ -#define MCHP_VBAT_CSS_SIL32K_EN BIT(0) -#define MCHP_VBAT_CSS_XTAL_EN BIT(8) -#define MCHP_VBAT_CSS_XTAL_SINGLE BIT(9) -#define MCHP_VBAT_CSS_XTAL_HSC_DIS BIT(10) -#define MCHP_VBAT_CSS_XTAL_CNT_POS 11 -#define MCHP_VBAT_CSS_XTAL_CNT_MASK (0x03U << 11) -#define MCHP_VBAT_CSS_SRC_POS 16 -#define MCHP_VBAT_CSS_SRC_MASK (0x03U << 16) -#define MCHP_VBAT_CSS_SRC_SIL_OSC 0 -#define MCHP_VBAT_CSS_SRC_XTAL (1U << 16) +#define MCHP_VBAT_CSS_SIL32K_EN BIT(0) +#define MCHP_VBAT_CSS_XTAL_EN BIT(8) +#define MCHP_VBAT_CSS_XTAL_SINGLE BIT(9) +#define MCHP_VBAT_CSS_XTAL_HSC_DIS BIT(10) +#define MCHP_VBAT_CSS_XTAL_CNT_POS 11 +#define MCHP_VBAT_CSS_XTAL_CNT_MASK (0x03U << 11) +#define MCHP_VBAT_CSS_SRC_POS 16 +#define MCHP_VBAT_CSS_SRC_MASK (0x03U << 16) +#define MCHP_VBAT_CSS_SRC_SIL_OSC 0 +#define MCHP_VBAT_CSS_SRC_XTAL (1U << 16) /* Switch from 32KHZ_IN input to silicon OSC when VTR goes down */ -#define MCHP_VBAT_CSS_SRC_SWPS (2U << 16) +#define MCHP_VBAT_CSS_SRC_SWPS (2U << 16) /* Switch from 32KHZ_IN input to XTAL on VBAT when VTR goes down */ -#define MCHP_VBAT_CSS_SRC_SWPX (3U << 16) +#define MCHP_VBAT_CSS_SRC_SWPX (3U << 16) /* Disable 32Khz silicon oscillator when VBAT goes off */ -#define MCHP_VBAT_CSS_NVB_SUPS BIT(18) +#define MCHP_VBAT_CSS_NVB_SUPS BIT(18) /* Blinking-Breathing LED 0 <= n <= 2 */ -#define MCHP_BBLEB_INSTANCES 4 -#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n) & 0x03) * 256)) +#define MCHP_BBLEB_INSTANCES 4 +#define MCHP_BBLED_BASE(n) (MCHP_BBLED_0_BASE + (((n)&0x03) * 256)) /* EMI */ -#define MCHP_EMI_INSTANCES 3 -#define MCHP_EMI_SPACING 0x400 -#define MCHP_EMI_ECREG_OFS 0x100 +#define MCHP_EMI_INSTANCES 3 +#define MCHP_EMI_SPACING 0x400 +#define MCHP_EMI_ECREG_OFS 0x100 /* base of EMI registers only accessible by EC */ #define MCHP_EMI_BASE(n) \ - (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n) * MCHP_EMI_SPACING)) + (MCHP_EMI_0_BASE + MCHP_EMI_ECREG_OFS + ((n)*MCHP_EMI_SPACING)) /* base of EMI registers accessible by EC and Host */ -#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n) * MCHP_EMI_SPACING)) -#define MCHP_EMI_GIRQ 15 -#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) +#define MCHP_EMI_RT_BASE(n) (MCHP_EMI_0_BASE + ((n)*MCHP_EMI_SPACING)) +#define MCHP_EMI_GIRQ 15 +#define MCHP_EMI_GIRQ_BIT(n) BIT(2 + (n)) /* Mailbox */ -#define MCHP_MBX_ECREGS_OFS 0x100 -#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE -#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) -#define MCHP_MBX_GIRQ 15 -#define MCHP_MBX_GIRQ_BIT BIT(20) +#define MCHP_MBX_ECREGS_OFS 0x100 +#define MCHP_MBX_RT_BASE MCHP_MBOX_BASE +#define MCHP_MBX_BASE (MCHP_MBOX_BASE + MCHP_MBX_ECREGS_OFS) +#define MCHP_MBX_GIRQ 15 +#define MCHP_MBX_GIRQ_BIT BIT(20) /* MEC172x includes one instance of the BIOS Debug Port * capable of capturing Host I/O port 0x80 and 0x90 writes. @@ -1034,130 +1028,128 @@ * Read with 16 or 32 access guarantees attributes/status bits * correspond to data in bits[7:0]. */ -#define MCHP_BDP0_HDATA REG32(MCHP_BDP0_BASE) -#define MCHP_BDP0_DATTR REG16(MCHP_BDP0_BASE + 0x100) -#define MCHP_BDP0_CONFIG REG32(MCHP_BDP0_BASE + 0x104) -#define MCHP_BDP0_STATUS REG8(MCHP_BDP0_BASE + 0x108) -#define MCHP_BDP0_INTR_EN REG8(MCHP_BDP0_BASE + 0x109) -#define MCHP_BDP0_STS_IEN REG16(MCHP_BDP0_BASE + 0x108) -#define MCHP_BDP0_SNAPSHOT REG32(MCHP_BDP0_BASE + 0x10C) -#define MCHP_BDP0_CAPTURE REG32(MCHP_BDP0_BASE + 0x110) -#define MCHP_BDP0_ACTV REG8(MCHP_BDP0_BASE + 0x330) -#define MCHP_BDP0_ALIAS_HDATA REG8(MCHP_BDP0_BASE + 0x400) -#define MCHP_BDP0_ALIAS_ACTV REG8(MCHP_BDP0_BASE + 0x730) -#define MCHP_BDP0_ALIAS_BLN REG8(MCHP_BDP0_BASE + 0x7F0) - -#define MCHP_BDP0_GIRQ 15 -#define MCHP_BDP0_GIRQ_BIT BIT(22) +#define MCHP_BDP0_HDATA REG32(MCHP_BDP0_BASE) +#define MCHP_BDP0_DATTR REG16(MCHP_BDP0_BASE + 0x100) +#define MCHP_BDP0_CONFIG REG32(MCHP_BDP0_BASE + 0x104) +#define MCHP_BDP0_STATUS REG8(MCHP_BDP0_BASE + 0x108) +#define MCHP_BDP0_INTR_EN REG8(MCHP_BDP0_BASE + 0x109) +#define MCHP_BDP0_STS_IEN REG16(MCHP_BDP0_BASE + 0x108) +#define MCHP_BDP0_SNAPSHOT REG32(MCHP_BDP0_BASE + 0x10C) +#define MCHP_BDP0_CAPTURE REG32(MCHP_BDP0_BASE + 0x110) +#define MCHP_BDP0_ACTV REG8(MCHP_BDP0_BASE + 0x330) +#define MCHP_BDP0_ALIAS_HDATA REG8(MCHP_BDP0_BASE + 0x400) +#define MCHP_BDP0_ALIAS_ACTV REG8(MCHP_BDP0_BASE + 0x730) +#define MCHP_BDP0_ALIAS_BLN REG8(MCHP_BDP0_BASE + 0x7F0) + +#define MCHP_BDP0_GIRQ 15 +#define MCHP_BDP0_GIRQ_BIT BIT(22) /* BDP DATATR as 16-bit value bit definitions */ -#define MCHP_BDP_DATTR_POS 0 -#define MCHP_BDP_DATTR_DATA_MASK 0xff -#define MCHP_BDP_DATTR_LANE_POS 8 -#define MCHP_BDP_DATTR_LANE_MASK GENMASK(9, 8) -#define MCHP_BDP_DATTR_LANE_0 0 -#define MCHP_BDP_DATTR_LANE_1 (1U << 8) -#define MCHP_BDP_DATTR_LANE_2 (2U << 8) -#define MCHP_BDP_DATTR_LANE_3 (3U << 8) -#define MCHP_BDP_DATTR_LEN_POS 10 -#define MCHP_BDP_DATTR_LEN_MASK GENMASK(11, 10) -#define MCHP_BDP_DATTR_LEN_1 0 -#define MCHP_BDP_DATTR_LEN_2 (1U << 10) -#define MCHP_BDP_DATTR_LEN_4 (2U << 10) -#define MCHP_BDP_DATTR_LEN_INVAL (3U << 10) -#define MCHP_BDP_DATTR_NE BIT(12) -#define MCHP_BDP_DATTR_OVR BIT(13) -#define MCHP_BDP_DATTR_THRH BIT(14) +#define MCHP_BDP_DATTR_POS 0 +#define MCHP_BDP_DATTR_DATA_MASK 0xff +#define MCHP_BDP_DATTR_LANE_POS 8 +#define MCHP_BDP_DATTR_LANE_MASK GENMASK(9, 8) +#define MCHP_BDP_DATTR_LANE_0 0 +#define MCHP_BDP_DATTR_LANE_1 (1U << 8) +#define MCHP_BDP_DATTR_LANE_2 (2U << 8) +#define MCHP_BDP_DATTR_LANE_3 (3U << 8) +#define MCHP_BDP_DATTR_LEN_POS 10 +#define MCHP_BDP_DATTR_LEN_MASK GENMASK(11, 10) +#define MCHP_BDP_DATTR_LEN_1 0 +#define MCHP_BDP_DATTR_LEN_2 (1U << 10) +#define MCHP_BDP_DATTR_LEN_4 (2U << 10) +#define MCHP_BDP_DATTR_LEN_INVAL (3U << 10) +#define MCHP_BDP_DATTR_NE BIT(12) +#define MCHP_BDP_DATTR_OVR BIT(13) +#define MCHP_BDP_DATTR_THRH BIT(14) /* BDP Configuration */ -#define MCHP_BDP_CFG_FLUSH_FIFO BIT(0) -#define MCHP_BDP_CFG_SNAPSHOT_CLR BIT(1) -#define MCHP_BDP_CFG_FIFO_THRH_POS 8 -#define MCHP_BDP_CFG_FIFO_THRH_1 0 -#define MCHP_BDP_CFG_FIFO_THRH_4 (1U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_8 (2U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_16 (3U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_20 (4U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_24 (5U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_28 (6U << 8) -#define MCHP_BDP_CFG_FIFO_THRH_30 (7U << 8) -#define MCHP_BDP_CFG_SRST BIT(31) +#define MCHP_BDP_CFG_FLUSH_FIFO BIT(0) +#define MCHP_BDP_CFG_SNAPSHOT_CLR BIT(1) +#define MCHP_BDP_CFG_FIFO_THRH_POS 8 +#define MCHP_BDP_CFG_FIFO_THRH_1 0 +#define MCHP_BDP_CFG_FIFO_THRH_4 (1U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_8 (2U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_16 (3U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_20 (4U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_24 (5U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_28 (6U << 8) +#define MCHP_BDP_CFG_FIFO_THRH_30 (7U << 8) +#define MCHP_BDP_CFG_SRST BIT(31) /* BDP Status */ -#define MCHP_BDP_STATUS_MASK GENMASK(2, 0) -#define MCHP_BDP_STATUS_NOT_EMPTY BIT(0) -#define MCHP_BDP_STATUS_OVERRUN BIT(1) -#define MCHP_BDP_STATUS_THRH BIT(2) +#define MCHP_BDP_STATUS_MASK GENMASK(2, 0) +#define MCHP_BDP_STATUS_NOT_EMPTY BIT(0) +#define MCHP_BDP_STATUS_OVERRUN BIT(1) +#define MCHP_BDP_STATUS_THRH BIT(2) /* BDP Interrupt enable */ -#define MCHP_BDP_IEN_THRH BIT(0) +#define MCHP_BDP_IEN_THRH BIT(0) /* PWM SZ 144 pin package has 9 PWM's */ -#define MCHP_PWM_INSTANCES 9 -#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) -#define MCHP_PWM_SPACING 16 -#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x) * MCHP_PWM_SPACING)) +#define MCHP_PWM_INSTANCES 9 +#define MCHP_PWM_ID_MAX (MCHP_PWM_INSTANCES) +#define MCHP_PWM_SPACING 16 +#define MCHP_PWM_BASE(x) (MCHP_PWM_0_BASE + ((x)*MCHP_PWM_SPACING)) /* TACH */ -#define MCHP_TACH_INSTANCES 4 -#define MCHP_TACH_SPACING 16 -#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x) * MCHP_TACH_SPACING)) -#define MCHP_TACH_GIRQ 17 -#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) +#define MCHP_TACH_INSTANCES 4 +#define MCHP_TACH_SPACING 16 +#define MCHP_TACH_BASE(x) (MCHP_TACH_0_BASE + ((x)*MCHP_TACH_SPACING)) +#define MCHP_TACH_GIRQ 17 +#define MCHP_TACH_GIRQ_BIT(x) BIT(1 + (x)) /* FAN */ -#define MCHP_FAN_INSTANCES 2 -#define MCHP_FAN_SPACING 0x80U -#define MCHP_FAN_BASE(x) \ - (MCHP_RPM2PWM0_BASE + ((x) * MCHP_FAN_SPACING)) -#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0) -#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2) -#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3) -#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4) -#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5) -#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6) -#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7) -#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8) -#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9) -#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa) -#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc) -#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe) -#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10) -#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11) +#define MCHP_FAN_INSTANCES 2 +#define MCHP_FAN_SPACING 0x80U +#define MCHP_FAN_BASE(x) (MCHP_RPM2PWM0_BASE + ((x)*MCHP_FAN_SPACING)) +#define MCHP_FAN_SETTING(x) REG16(MCHP_FAN_BASE(x) + 0x0) +#define MCHP_FAN_CFG1(x) REG8(MCHP_FAN_BASE(x) + 0x2) +#define MCHP_FAN_CFG2(x) REG8(MCHP_FAN_BASE(x) + 0x3) +#define MCHP_FAN_PWM_DIVIDE(x) REG8(MCHP_FAN_BASE(x) + 0x4) +#define MCHP_FAN_GAIN(x) REG8(MCHP_FAN_BASE(x) + 0x5) +#define MCHP_FAN_SPIN_UP(x) REG8(MCHP_FAN_BASE(x) + 0x6) +#define MCHP_FAN_STEP(x) REG8(MCHP_FAN_BASE(x) + 0x7) +#define MCHP_FAN_MIN_DRV(x) REG8(MCHP_FAN_BASE(x) + 0x8) +#define MCHP_FAN_VALID_CNT(x) REG8(MCHP_FAN_BASE(x) + 0x9) +#define MCHP_FAN_DRV_FAIL(x) REG16(MCHP_FAN_BASE(x) + 0xa) +#define MCHP_FAN_TARGET(x) REG16(MCHP_FAN_BASE(x) + 0xc) +#define MCHP_FAN_READING(x) REG16(MCHP_FAN_BASE(x) + 0xe) +#define MCHP_FAN_BASE_FREQ(x) REG8(MCHP_FAN_BASE(x) + 0x10) +#define MCHP_FAN_STATUS(x) REG8(MCHP_FAN_BASE(x) + 0x11) /* ACPI EC */ -#define MCHP_ACPI_EC_INSTANCES 5 -#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES) -#define MCHP_ACPI_EC_SPACING 0x400 -#define MCHP_ACPI_EC_BASE(x) \ - (MCHP_ACPI_EC_0_BASE + ((x) * MCHP_ACPI_EC_SPACING)) -#define MCHP_ACPI_EC_GIRQ 15 -#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x) * 2)) -#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x) * 2)) +#define MCHP_ACPI_EC_INSTANCES 5 +#define MCHP_ACPI_EC_MAX (MCHP_ACPI_EC_INSTANCES) +#define MCHP_ACPI_EC_SPACING 0x400 +#define MCHP_ACPI_EC_BASE(x) (MCHP_ACPI_EC_0_BASE + ((x)*MCHP_ACPI_EC_SPACING)) +#define MCHP_ACPI_EC_GIRQ 15 +#define MCHP_ACPI_EC_IBF_GIRQ_BIT(x) BIT(5 + ((x)*2)) +#define MCHP_ACPI_EC_OBE_GIRQ_BIT(x) BIT(6 + ((x)*2)) /* ACPI PM1 */ -#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 -#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE -#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) -#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) -#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) -#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) +#define MCHP_ACPI_PM1_ECREGS_OFS 0x100 +#define MCHP_ACPI_PM_RT_BASE MCHP_ACPI_PM1_BASE +#define MCHP_ACPI_PM_EC_BASE (MCHP_ACPI_PM1_BASE + MCHP_ACPI_PM1_ECREGS_OFS) +#define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) +#define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) +#define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) /* 8042 */ -#define MCHP_8042_ECREGS_OFS 0x100 -#define MCHP_8042_GIRQ 15 -#define MCHP_8042_OBE_GIRQ_BIT BIT(18) -#define MCHP_8042_IBF_GIRQ_BIT BIT(19) +#define MCHP_8042_ECREGS_OFS 0x100 +#define MCHP_8042_GIRQ 15 +#define MCHP_8042_OBE_GIRQ_BIT BIT(18) +#define MCHP_8042_IBF_GIRQ_BIT BIT(19) /* I2C controllers 0 - 4 include SMBus network layer functionality. */ -#define MCHP_I2C_CTRL0 0 -#define MCHP_I2C_CTRL1 1 -#define MCHP_I2C_CTRL2 2 -#define MCHP_I2C_CTRL3 3 -#define MCHP_I2C_CTRL4 4 -#define MCHP_I2C_CTRL_MAX 5 +#define MCHP_I2C_CTRL0 0 +#define MCHP_I2C_CTRL1 1 +#define MCHP_I2C_CTRL2 2 +#define MCHP_I2C_CTRL3 3 +#define MCHP_I2C_CTRL4 4 +#define MCHP_I2C_CTRL_MAX 5 -#define MCHP_I2C_SEP0 0x400 +#define MCHP_I2C_SEP0 0x400 /* * MEC172x SZ(144-pin) package implements 15 ports. No Port 11. @@ -1169,8 +1161,8 @@ * of port to controller. * Locking must occur by-controller (not by-port). */ -#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\ - || defined(CHIP_VARIANT_MEC1727LJ)) +#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \ + defined(CHIP_VARIANT_MEC1727LJ)) #define MCHP_I2C_PORT_MASK GENMASK(15, 0) #else #define MCHP_I2C_PORT_MASK (GENMASK(15, 0) & ~BIT(11)) @@ -1196,83 +1188,83 @@ enum MCHP_i2c_port { }; /* I2C ports & Configs */ -#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX -#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT +#define I2C_CONTROLLER_COUNT MCHP_I2C_CTRL_MAX +#define I2C_PORT_COUNT MCHP_I2C_PORT_COUNT /* All I2C controllers connected to GIRQ13 */ -#define MCHP_I2C_GIRQ 13 +#define MCHP_I2C_GIRQ 13 /* I2C[0:7] -> GIRQ13 bits[0:7] */ -#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) +#define MCHP_I2C_GIRQ_BIT(n) BIT((n)) /* Keyboard scan matrix */ -#define MCHP_KS_GIRQ 21 -#define MCHP_KS_GIRQ_BIT BIT(25) -#define MCHP_KS_DIRECT_NVIC 135 +#define MCHP_KS_GIRQ 21 +#define MCHP_KS_GIRQ_BIT BIT(25) +#define MCHP_KS_DIRECT_NVIC 135 /* ADC */ -#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ)\ - || defined(CHIP_VARIANT_MEC1727LJ)) +#if (defined(CHIP_VARIANT_MEC1721LJ) || defined(CHIP_VARIANT_MEC1723LJ) || \ + defined(CHIP_VARIANT_MEC1727LJ)) #define MCHP_ADC_CHAN_MASK GENMASK(15, 0) #else #define MCHP_ADC_CHAN_MASK GENMASK(7, 0) #endif -#define MCHP_ADC_GIRQ 17 -#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) -#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) -#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 -#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 -#define MCHP_ADC_CONFIG REG32(MCHP_ADC_BASE + 0x7c) -#define MCHP_ADC_CONFIG_DFLT 0x0101U -#define MCHP_ADC_CFG_CLK_LO_TM_MSK GENMASK(7, 0) -#define MCHP_ADC_CFG_CLK_HI_TM_MSK GENMASK(15, 8) -#define MCHP_ADC_VREF_CSEL REG32(MCHP_ADC_BASE + 0x80) -#define MCHP_ADC_VREF_CSEL_MSK(ch) (0x03U << ((ch) * 2U)) -#define MCHP_ADC_VREF_CSEL_GPIO(ch) BIT((ch) * 2U) -#define MCHP_ADC_VREF_CTRL REG32(MCHP_ADC_BASE + 0x84) -#define MCHP_ADC_VREF_CTRL_DFLT 0U -#define MCHP_ADC_VCTRL_CHRG_DLY_MSK GENMASK(15, 0) -#define MCHP_ADC_VCTRL_SW_DLY_MSK GENMASK(28, 16) -#define MCHP_ADC_VCTRL_DRV_UNUSED_LO BIT(29) -#define MCHP_ADC_VCTRL_SEL_STS_RO_POS 30 -#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK GENMASK(31, 30) -#define MCHP_ADC_SAR_ADC_CTRL REG32(MCHP_ADC_BASE + 0x88) -#define MCHP_ADC_SAR_ADC_CTRL_DFLT ((0x202U << 7) | (0x03U << 1)) -#define MCHP_ADC_SAC_DIFF_INPUT BIT(0) -#define MCHP_ADC_SAC_RES_POS 1 -#define MCHP_ADC_SAC_RES_MSK GENMASK(2, 1) -#define MCHP_ADC_SAC_RES_10BIT (2U << 1) -#define MCHP_ADC_SAC_RES_12BIT (3U << 1) -#define MCHP_ADC_SAC_RJ_10BIT BIT(3) -#define MCHP_ADC_SAC_WU_DLY_POS 7 -#define MCHP_ADC_SAC_WU_DLY_MSK GENMASK(16, 7) -#define MCHP_ADC_SAC_WU_DLY_DLFT (0x202U << 7) +#define MCHP_ADC_GIRQ 17 +#define MCHP_ADC_GIRQ_SINGLE_BIT BIT(8) +#define MCHP_ADC_GIRQ_REPEAT_BIT BIT(9) +#define MCHP_ADC_SINGLE_DIRECT_NVIC 78 +#define MCHP_ADC_REPEAT_DIRECT_NVIC 79 +#define MCHP_ADC_CONFIG REG32(MCHP_ADC_BASE + 0x7c) +#define MCHP_ADC_CONFIG_DFLT 0x0101U +#define MCHP_ADC_CFG_CLK_LO_TM_MSK GENMASK(7, 0) +#define MCHP_ADC_CFG_CLK_HI_TM_MSK GENMASK(15, 8) +#define MCHP_ADC_VREF_CSEL REG32(MCHP_ADC_BASE + 0x80) +#define MCHP_ADC_VREF_CSEL_MSK(ch) (0x03U << ((ch)*2U)) +#define MCHP_ADC_VREF_CSEL_GPIO(ch) BIT((ch)*2U) +#define MCHP_ADC_VREF_CTRL REG32(MCHP_ADC_BASE + 0x84) +#define MCHP_ADC_VREF_CTRL_DFLT 0U +#define MCHP_ADC_VCTRL_CHRG_DLY_MSK GENMASK(15, 0) +#define MCHP_ADC_VCTRL_SW_DLY_MSK GENMASK(28, 16) +#define MCHP_ADC_VCTRL_DRV_UNUSED_LO BIT(29) +#define MCHP_ADC_VCTRL_SEL_STS_RO_POS 30 +#define MCHP_ADC_VCTRL_SEL_STS_RO_MSK GENMASK(31, 30) +#define MCHP_ADC_SAR_ADC_CTRL REG32(MCHP_ADC_BASE + 0x88) +#define MCHP_ADC_SAR_ADC_CTRL_DFLT ((0x202U << 7) | (0x03U << 1)) +#define MCHP_ADC_SAC_DIFF_INPUT BIT(0) +#define MCHP_ADC_SAC_RES_POS 1 +#define MCHP_ADC_SAC_RES_MSK GENMASK(2, 1) +#define MCHP_ADC_SAC_RES_10BIT (2U << 1) +#define MCHP_ADC_SAC_RES_12BIT (3U << 1) +#define MCHP_ADC_SAC_RJ_10BIT BIT(3) +#define MCHP_ADC_SAC_WU_DLY_POS 7 +#define MCHP_ADC_SAC_WU_DLY_MSK GENMASK(16, 7) +#define MCHP_ADC_SAC_WU_DLY_DLFT (0x202U << 7) /* Hibernation timer */ -#define MCHP_HTIMER_SPACING 0x20 -#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n) * MCHP_HTIMER_SPACING)) -#define MCHP_HTIMER_GIRQ 21 +#define MCHP_HTIMER_SPACING 0x20 +#define MCHP_HTIMER_ADDR(n) (MCHP_HTIMER_BASE + ((n)*MCHP_HTIMER_SPACING)) +#define MCHP_HTIMER_GIRQ 21 /* HTIMER[0:1] -> GIRQ21 bits[1:2] */ -#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n)) -#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) +#define MCHP_HTIMER_GIRQ_BIT(n) BIT(1 + (n)) +#define MCHP_HTIMER_DIRECT_NVIC(n) (112 + (n)) /* General Purpose SPI (GP-SPI) */ -#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port) * 0x80)) -#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00) -#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04) -#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08) -#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c) -#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10) -#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14) -#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18) +#define MCHP_SPI_BASE(port) (MCHP_GPSPI0_BASE + ((port)*0x80)) +#define MCHP_SPI_AR(port) REG8(MCHP_SPI_BASE(port) + 0x00) +#define MCHP_SPI_CR(port) REG8(MCHP_SPI_BASE(port) + 0x04) +#define MCHP_SPI_SR(port) REG8(MCHP_SPI_BASE(port) + 0x08) +#define MCHP_SPI_TD(port) REG8(MCHP_SPI_BASE(port) + 0x0c) +#define MCHP_SPI_RD(port) REG8(MCHP_SPI_BASE(port) + 0x10) +#define MCHP_SPI_CC(port) REG8(MCHP_SPI_BASE(port) + 0x14) +#define MCHP_SPI_CG(port) REG8(MCHP_SPI_BASE(port) + 0x18) /* Addresses of TX/RX register used in tables */ -#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c) -#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10) +#define MCHP_SPI_TD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x0c) +#define MCHP_SPI_RD_ADDR(ctrl) (MCHP_SPI_BASE(ctrl) + 0x10) /* All GP-SPI controllers connected to GIRQ18 */ -#define MCHP_SPI_GIRQ 18 -#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x) * 2)) -#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x) * 2)) -#define MCHP_GPSPI0_ID 0 -#define MCHP_GPSPI1_ID 1 +#define MCHP_SPI_GIRQ 18 +#define MCHP_SPI_GIRQ_TXBE_BIT(x) BIT(2 + ((x)*2)) +#define MCHP_SPI_GIRQ_RXBF_BIT(x) BIT(3 + ((x)*2)) +#define MCHP_GPSPI0_ID 0 +#define MCHP_GPSPI1_ID 1 /* * Quad Master SPI (QMSPI) @@ -1280,43 +1272,43 @@ enum MCHP_i2c_port { * chip select timing and a local DMA unit with 3 RX channels and * 3 TX channels. It retains support of the legacy DMA block. */ -#define MCHP_QMSPI_MAX_DESCR 16 -#define MCHP_QMSPI_GIRQ 18 -#define MCHP_QMSPI_GIRQ_BIT BIT(1) +#define MCHP_QMSPI_MAX_DESCR 16 +#define MCHP_QMSPI_GIRQ 18 +#define MCHP_QMSPI_GIRQ_BIT BIT(1) #define MCHP_QMSPI_DIRECT_NVIC 91 /* SAF DMA mode when QMSPI when eSPI SAF is enabled */ -#define MCHP_QMSPI_M_SAF_EN BIT(2) +#define MCHP_QMSPI_M_SAF_EN BIT(2) /* Local DMA enables in Mode register */ -#define MCHP_QMSPI_M_LDRX_EN BIT(3) -#define MCHP_QMSPI_M_LDTX_EN BIT(4) +#define MCHP_QMSPI_M_LDRX_EN BIT(3) +#define MCHP_QMSPI_M_LDTX_EN BIT(4) /* Chip select implemented in bit[13:12] of the Mode register. */ -#define MCHP_QMSPI_M_CS_POS 12 -#define MCHP_QMSPI_M_CS_MASK0 0x03 -#define MCHP_QMSPI_M_CS_MASK GENMASK(13, 12) -#define MCHP_QMSPI_M_CS0 0U -#define MCHP_QMSPI_M_CS1 BIT(12) +#define MCHP_QMSPI_M_CS_POS 12 +#define MCHP_QMSPI_M_CS_MASK0 0x03 +#define MCHP_QMSPI_M_CS_MASK GENMASK(13, 12) +#define MCHP_QMSPI_M_CS0 0U +#define MCHP_QMSPI_M_CS1 BIT(12) /* QMSPI alternate clock divider when CS1 is active. */ -#define MCHP_QMSPI0_ALTM REG32(MCHP_QMSPI0_BASE + 0xc0) -#define MCHP_QMSPI0_ALTM_EN BIT(0) +#define MCHP_QMSPI0_ALTM REG32(MCHP_QMSPI0_BASE + 0xc0) +#define MCHP_QMSPI0_ALTM_EN BIT(0) /* QMSPI taps select */ -#define MCHP_QMSPI0_TAPS REG32(MCHP_QMSPI0_BASE + 0xd0) +#define MCHP_QMSPI0_TAPS REG32(MCHP_QMSPI0_BASE + 0xd0) /* QMSPI Taps adjust */ -#define MCHP_QMSPI0_TAPS_ADJ REG32(MCHP_QMSPI0_BASE + 0xd4) -#define MCHP_QMSPI0_TAPS_SCK_POS 0 -#define MCHP_QMSPI0_TAPS_SCK_MSK GENMASK(7, 0) -#define MCHP_QMSPI0_TAPS_CTL_POS 8 -#define MCHP_QMSPI0_TAPS_CTL_MSK GENMASK(15, 8) +#define MCHP_QMSPI0_TAPS_ADJ REG32(MCHP_QMSPI0_BASE + 0xd4) +#define MCHP_QMSPI0_TAPS_SCK_POS 0 +#define MCHP_QMSPI0_TAPS_SCK_MSK GENMASK(7, 0) +#define MCHP_QMSPI0_TAPS_CTL_POS 8 +#define MCHP_QMSPI0_TAPS_CTL_MSK GENMASK(15, 8) /* QMSPI Taps control */ -#define MCHP_QMSPI0_TAPS_CTRL REG32(MCHP_QMSPI0_BASE + 0xd4) -#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS 0 -#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK GENMASK(1, 0) -#define MCHP_QMSPI0_TAPS_CTRL_UPDATE BIT(2) -#define MCHP_QMSPI0_TAPS_CTRL_GO BIT(8) -#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS 16 -#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK GENMASK(18, 16) +#define MCHP_QMSPI0_TAPS_CTRL REG32(MCHP_QMSPI0_BASE + 0xd4) +#define MCHP_QMSPI0_TAPS_CTRL_MODE_POS 0 +#define MCHP_QMSPI0_TAPS_CTRL_MODE_MSK GENMASK(1, 0) +#define MCHP_QMSPI0_TAPS_CTRL_UPDATE BIT(2) +#define MCHP_QMSPI0_TAPS_CTRL_GO BIT(8) +#define MCHP_QMSPI0_TAPS_CTRL_MULT_POS 16 +#define MCHP_QMSPI0_TAPS_CTRL_MULT_MSK GENMASK(18, 16) /* QMSPI LDMA descriptor enables */ -#define MCHP_QMSPI0_LDRX_DEN REG32(MCHP_QMSPI0_BASE + 0x100) -#define MCHP_QMSPI0_LDTX_DEN REG32(MCHP_QMSPI0_BASE + 0x104) +#define MCHP_QMSPI0_LDRX_DEN REG32(MCHP_QMSPI0_BASE + 0x100) +#define MCHP_QMSPI0_LDTX_DEN REG32(MCHP_QMSPI0_BASE + 0x104) /* * QMSPI LDMA channel registers. * Each channel implement 3 32-bit registers: @@ -1331,74 +1323,74 @@ enum MCHP_i2c_port { #define MCHP_QMSPI0_LDTX_MBASE(n) REG32(MCHP_QMSPI0_BASE + 0x144 + ((n)*16U)) #define MCHP_QMSPI0_LDTX_LEN(n) REG32(MCHP_QMSPI0_BASE + 0x148 + ((n)*16U)) /* LDMA RX or TX channel control register */ -#define MCHP_QMSPI_LDC_MSK GENMASK(6, 0) -#define MCHP_QMSPI_LDC_EN BIT(0) -#define MCHP_QMSPI_LDC_RSTART_EN BIT(1) -#define MCHP_QMSPI_LDC_RSTART_MA_EN BIT(2) -#define MCHP_QMSPI_LDC_LEN_EN BIT(3) -#define MCHP_QMSPI_LDC_ACC_SZ_POS 4 -#define MCHP_QMSPI_LDC_ACC_SZ_MSK GENMASK(5, 4) -#define MCHP_QMSPI_LDC_ACC_1BYTE 0 -#define MCHP_QMSPI_LDC_ACC_2BYTES (1U << 4) -#define MCHP_QMSPI_LDC_ACC_4BYTES (2U << 4) -#define MCHP_QMSPI_LDC_INCR_ADDR BIT(6) +#define MCHP_QMSPI_LDC_MSK GENMASK(6, 0) +#define MCHP_QMSPI_LDC_EN BIT(0) +#define MCHP_QMSPI_LDC_RSTART_EN BIT(1) +#define MCHP_QMSPI_LDC_RSTART_MA_EN BIT(2) +#define MCHP_QMSPI_LDC_LEN_EN BIT(3) +#define MCHP_QMSPI_LDC_ACC_SZ_POS 4 +#define MCHP_QMSPI_LDC_ACC_SZ_MSK GENMASK(5, 4) +#define MCHP_QMSPI_LDC_ACC_1BYTE 0 +#define MCHP_QMSPI_LDC_ACC_2BYTES (1U << 4) +#define MCHP_QMSPI_LDC_ACC_4BYTES (2U << 4) +#define MCHP_QMSPI_LDC_INCR_ADDR BIT(6) /* eSPI */ /* IO BAR defines. Use with MCHP_ESPI_IO_BAR_xxxx macros */ -#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 -#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 -#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 -#define MCHP_ESPI_IO_BAR_ID_8042 3 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 -#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8 -#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 -#define MCHP_ESPI_IO_BAR_ID_P92 0xA -#define MCHP_ESPI_IO_BAR_ID_UART0 0xB -#define MCHP_ESPI_IO_BAR_ID_UART1 0xC -#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD -#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE -#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF -#define MCHP_ESPI_IO_BAR_BDP0 0x10 -#define MCHP_ESPI_IO_BAR_BDP0_ALT 0x11 -#define MCHP_ESPI_IO_BAR_RTC 0x12 -#define MCHP_ESPI_IO_BAR_TB32 0x14 -#define MCHP_ESPI_IO_BAR_GLUE 0x16 +#define MCHP_ESPI_IO_BAR_ID_CFG_PORT 0 +#define MCHP_ESPI_IO_BAR_ID_MEM_CMPNT 1 +#define MCHP_ESPI_IO_BAR_ID_MAILBOX 2 +#define MCHP_ESPI_IO_BAR_ID_8042 3 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC0 4 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC1 5 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC2 6 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC3 7 +#define MCHP_ESPI_IO_BAR_ID_ACPI_EC4 8 +#define MCHP_ESPI_IO_BAR_ID_ACPI_PM1 9 +#define MCHP_ESPI_IO_BAR_ID_P92 0xA +#define MCHP_ESPI_IO_BAR_ID_UART0 0xB +#define MCHP_ESPI_IO_BAR_ID_UART1 0xC +#define MCHP_ESPI_IO_BAR_ID_EMI0 0xD +#define MCHP_ESPI_IO_BAR_ID_EMI1 0xE +#define MCHP_ESPI_IO_BAR_ID_EMI2 0xF +#define MCHP_ESPI_IO_BAR_BDP0 0x10 +#define MCHP_ESPI_IO_BAR_BDP0_ALT 0x11 +#define MCHP_ESPI_IO_BAR_RTC 0x12 +#define MCHP_ESPI_IO_BAR_TB32 0x14 +#define MCHP_ESPI_IO_BAR_GLUE 0x16 /* Use with MCHP_ESPI_MBAR_EC_xxxx(x) macros */ -#define MCHP_ESPI_MBAR_ID_MBOX 0 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 -#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5 -#define MCHP_ESPI_MBAR_ID_EMI_0 6 -#define MCHP_ESPI_MBAR_ID_EMI_1 7 -#define MCHP_ESPI_MBAR_ID_EMI_2 8 -#define MCHP_ESPI_MBAR_ID_TB32 9 +#define MCHP_ESPI_MBAR_ID_MBOX 0 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_0 1 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_1 2 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_2 3 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_3 4 +#define MCHP_ESPI_MBAR_ID_ACPI_EC_4 5 +#define MCHP_ESPI_MBAR_ID_EMI_0 6 +#define MCHP_ESPI_MBAR_ID_EMI_1 7 +#define MCHP_ESPI_MBAR_ID_EMI_2 8 +#define MCHP_ESPI_MBAR_ID_TB32 9 /* Use with MCHP_ESPI_IO_SERIRQ_REG(x) */ -#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ -#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ -#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ -#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ -#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 -#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 -#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 -#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 -#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8 -#define MCHP_ESPI_SIRQ_UART0 9 -#define MCHP_ESPI_SIRQ_UART1 10 -#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ -#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ -#define MCHP_ESPI_SIRQ_EMI1_HEV 13 -#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 -#define MCHP_ESPI_SIRQ_EMI2_HEV 15 -#define MCHP_ESPI_SIRQ_EMI2_EC2H 16 -#define MCHP_ESPI_SIRQ_RTC 17 -#define MCHP_ESPI_SIRQ_EC 18 +#define MCHP_ESPI_SIRQ_MBOX 0 /* Host SIRQ */ +#define MCHP_ESPI_SIRQ_MBOX_SMI 1 /* Host SMI */ +#define MCHP_ESPI_SIRQ_8042_KB 2 /* KIRQ */ +#define MCHP_ESPI_SIRQ_8042_MS 3 /* MIRQ */ +#define MCHP_ESPI_SIRQ_ACPI_EC0_OBF 4 +#define MCHP_ESPI_SIRQ_ACPI_EC1_OBF 5 +#define MCHP_ESPI_SIRQ_ACPI_EC2_OBF 6 +#define MCHP_ESPI_SIRQ_ACPI_EC3_OBF 7 +#define MCHP_ESPI_SIRQ_ACPI_EC4_OBF 8 +#define MCHP_ESPI_SIRQ_UART0 9 +#define MCHP_ESPI_SIRQ_UART1 10 +#define MCHP_ESPI_SIRQ_EMI0_HEV 11 /* Host Event */ +#define MCHP_ESPI_SIRQ_EMI0_EC2H 12 /* EC to Host */ +#define MCHP_ESPI_SIRQ_EMI1_HEV 13 +#define MCHP_ESPI_SIRQ_EMI1_EC2H 14 +#define MCHP_ESPI_SIRQ_EMI2_HEV 15 +#define MCHP_ESPI_SIRQ_EMI2_EC2H 16 +#define MCHP_ESPI_SIRQ_RTC 17 +#define MCHP_ESPI_SIRQ_EC 18 #define MCHP_ESPI_MSVW_BASE (MCHP_ESPI_VW_BASE) #define MCHP_ESPI_SMVW_BASE ((MCHP_ESPI_VW_BASE) + 0x200ul) @@ -1407,23 +1399,23 @@ enum MCHP_i2c_port { * eSPI RESET, channel enables and operations except Master-to-Slave * WWires are all on GIRQ19 */ -#define MCHP_ESPI_GIRQ 19 -#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) -#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) -#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) -#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) -#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) -#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) -#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) -#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) -#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) -#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) -#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) -#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11) +#define MCHP_ESPI_GIRQ 19 +#define MCHP_ESPI_PC_GIRQ_BIT BIT(0) +#define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) +#define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) +#define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) +#define MCHP_ESPI_OOB_TX_GIRQ_BIT BIT(4) +#define MCHP_ESPI_OOB_RX_GIRQ_BIT BIT(5) +#define MCHP_ESPI_FC_GIRQ_BIT BIT(6) +#define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) +#define MCHP_ESPI_VW_EN_GIRQ_BIT BIT(8) +#define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) +#define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) +#define MCHP_ESPI_SAF_CACHE_GIRQ_BIT BIT(11) /* eSPI Master-to-Slave WWire interrupts are on GIRQ24 and GIRQ25 */ -#define MCHP_ESPI_MSVW_0_6_GIRQ 24 -#define MCHP_ESPI_MSVW_7_10_GIRQ 25 +#define MCHP_ESPI_MSVW_0_6_GIRQ 24 +#define MCHP_ESPI_MSVW_7_10_GIRQ 25 /* * Four source bits, SRC[0:3] per Master-to-Slave register * v = MSVW [0:10] @@ -1432,12 +1424,12 @@ enum MCHP_i2c_port { #define MCHP_ESPI_MSVW_GIRQ(v) (24 + ((v) > 6 ? 1 : 0)) #define MCHP_ESPI_MSVW_SRC_GIRQ_BIT(v, n) \ - (((v) > 6) ? (1ul << (((v)-7)+(n))) : (1ul << ((v)+(n)))) + (((v) > 6) ? (1ul << (((v)-7) + (n))) : (1ul << ((v) + (n)))) /* DMA */ -#define MCHP_DMA_MAX_CHAN 16 -#define MCHP_DMA_CH_OFS 0x40 -#define MCHP_DMA_CH_OFS_BITPOS 6 +#define MCHP_DMA_MAX_CHAN 16 +#define MCHP_DMA_CH_OFS 0x40 +#define MCHP_DMA_CH_OFS_BITPOS 6 #define MCHP_DMA_CH_BASE (MCHP_DMA_BASE + MCHP_DMA_CH_OFS) /* @@ -1473,22 +1465,22 @@ enum dma_channel { * Peripheral device DMA Device ID's for bits [15:9] * in DMA channel control register. */ -#define MCHP_DMA_I2C0_SLV_REQ_ID 0 -#define MCHP_DMA_I2C0_MTR_REQ_ID 1 -#define MCHP_DMA_I2C1_SLV_REQ_ID 2 -#define MCHP_DMA_I2C1_MTR_REQ_ID 3 -#define MCHP_DMA_I2C2_SLV_REQ_ID 4 -#define MCHP_DMA_I2C2_MTR_REQ_ID 5 -#define MCHP_DMA_I2C3_SLV_REQ_ID 6 -#define MCHP_DMA_I2C3_MTR_REQ_ID 7 -#define MCHP_DMA_I2C4_SLV_REQ_ID 8 -#define MCHP_DMA_I2C4_MTR_REQ_ID 9 -#define MCHP_DMA_QMSPI0_TX_REQ_ID 10 -#define MCHP_DMA_QMSPI0_RX_REQ_ID 11 -#define MCHP_DMA_SPI0_TX_REQ_ID 12 -#define MCHP_DMA_SPI0_RX_REQ_ID 13 -#define MCHP_DMA_SPI1_TX_REQ_ID 14 -#define MCHP_DMA_SPI1_RX_REQ_ID 15 +#define MCHP_DMA_I2C0_SLV_REQ_ID 0 +#define MCHP_DMA_I2C0_MTR_REQ_ID 1 +#define MCHP_DMA_I2C1_SLV_REQ_ID 2 +#define MCHP_DMA_I2C1_MTR_REQ_ID 3 +#define MCHP_DMA_I2C2_SLV_REQ_ID 4 +#define MCHP_DMA_I2C2_MTR_REQ_ID 5 +#define MCHP_DMA_I2C3_SLV_REQ_ID 6 +#define MCHP_DMA_I2C3_MTR_REQ_ID 7 +#define MCHP_DMA_I2C4_SLV_REQ_ID 8 +#define MCHP_DMA_I2C4_MTR_REQ_ID 9 +#define MCHP_DMA_QMSPI0_TX_REQ_ID 10 +#define MCHP_DMA_QMSPI0_RX_REQ_ID 11 +#define MCHP_DMA_SPI0_TX_REQ_ID 12 +#define MCHP_DMA_SPI0_RX_REQ_ID 13 +#define MCHP_DMA_SPI1_TX_REQ_ID 14 +#define MCHP_DMA_SPI1_RX_REQ_ID 15 /* * Hardware delay register. -- cgit v1.2.1 From 1d799b3b7c6022548b99185d463503564f6cc3b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:05 -0600 Subject: chip/it83xx/gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfc688b9b29584d1c95562a7177d03b142a21e6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729211 Reviewed-by: Jeremy Bettis --- chip/it83xx/gpio.c | 578 +++++++++++++++++++++++++++-------------------------- 1 file changed, 291 insertions(+), 287 deletions(-) diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index bace7eb663..99603c26a5 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -29,11 +29,11 @@ struct kbs_gpio_ctrl_t { static const struct kbs_gpio_ctrl_t kbs_gpio_ctrl_regs[] = { /* KSI pins 7:0 */ - {&IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN}, + { &IT83XX_KBS_KSIGCTRL, &IT83XX_KBS_KSIGOEN }, /* KSO pins 15:8 */ - {&IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN}, + { &IT83XX_KBS_KSOHGCTRL, &IT83XX_KBS_KSOHGOEN }, /* KSO pins 7:0 */ - {&IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN}, + { &IT83XX_KBS_KSOLGCTRL, &IT83XX_KBS_KSOLGOEN }, }; /** @@ -51,8 +51,8 @@ static volatile uint8_t *wuesr(uint8_t grp) * the address increases by fours. */ return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4*(grp-5)); + (volatile uint8_t *)(IT83XX_WUC_WUESR1 + grp - 1) : + (volatile uint8_t *)(IT83XX_WUC_WUESR5 + 4 * (grp - 5)); } /** @@ -70,8 +70,8 @@ static volatile uint8_t *wuemr(uint8_t grp) * the address increases by fours. */ return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5)); + (volatile uint8_t *)(IT83XX_WUC_WUEMR1 + grp - 1) : + (volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4 * (grp - 5)); } /** @@ -90,8 +90,8 @@ static volatile uint8_t *wubemr(uint8_t grp) * the address increases by fours. */ return (grp <= 4) ? - (volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) : - (volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5)); + (volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp - 1) : + (volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4 * (grp - 5)); } #endif @@ -112,140 +112,140 @@ static const struct { uint8_t wuc_mask; } gpio_irqs[] = { /* irq gpio_port,gpio_mask,wuc_group,wuc_mask */ - [IT83XX_IRQ_WKO20] = {GPIO_D, BIT(0), 2, BIT(0)}, - [IT83XX_IRQ_WKO21] = {GPIO_D, BIT(1), 2, BIT(1)}, - [IT83XX_IRQ_WKO22] = {GPIO_C, BIT(4), 2, BIT(2)}, - [IT83XX_IRQ_WKO23] = {GPIO_C, BIT(6), 2, BIT(3)}, - [IT83XX_IRQ_WKO24] = {GPIO_D, BIT(2), 2, BIT(4)}, + [IT83XX_IRQ_WKO20] = { GPIO_D, BIT(0), 2, BIT(0) }, + [IT83XX_IRQ_WKO21] = { GPIO_D, BIT(1), 2, BIT(1) }, + [IT83XX_IRQ_WKO22] = { GPIO_C, BIT(4), 2, BIT(2) }, + [IT83XX_IRQ_WKO23] = { GPIO_C, BIT(6), 2, BIT(3) }, + [IT83XX_IRQ_WKO24] = { GPIO_D, BIT(2), 2, BIT(4) }, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO40] = {GPIO_E, BIT(5), 4, BIT(0)}, - [IT83XX_IRQ_WKO45] = {GPIO_E, BIT(6), 4, BIT(5)}, - [IT83XX_IRQ_WKO46] = {GPIO_E, BIT(7), 4, BIT(6)}, + [IT83XX_IRQ_WKO40] = { GPIO_E, BIT(5), 4, BIT(0) }, + [IT83XX_IRQ_WKO45] = { GPIO_E, BIT(6), 4, BIT(5) }, + [IT83XX_IRQ_WKO46] = { GPIO_E, BIT(7), 4, BIT(6) }, #endif - [IT83XX_IRQ_WKO50] = {GPIO_K, BIT(0), 5, BIT(0)}, - [IT83XX_IRQ_WKO51] = {GPIO_K, BIT(1), 5, BIT(1)}, - [IT83XX_IRQ_WKO52] = {GPIO_K, BIT(2), 5, BIT(2)}, - [IT83XX_IRQ_WKO53] = {GPIO_K, BIT(3), 5, BIT(3)}, - [IT83XX_IRQ_WKO54] = {GPIO_K, BIT(4), 5, BIT(4)}, - [IT83XX_IRQ_WKO55] = {GPIO_K, BIT(5), 5, BIT(5)}, - [IT83XX_IRQ_WKO56] = {GPIO_K, BIT(6), 5, BIT(6)}, - [IT83XX_IRQ_WKO57] = {GPIO_K, BIT(7), 5, BIT(7)}, - [IT83XX_IRQ_WKO60] = {GPIO_H, BIT(0), 6, BIT(0)}, - [IT83XX_IRQ_WKO61] = {GPIO_H, BIT(1), 6, BIT(1)}, - [IT83XX_IRQ_WKO62] = {GPIO_H, BIT(2), 6, BIT(2)}, - [IT83XX_IRQ_WKO63] = {GPIO_H, BIT(3), 6, BIT(3)}, - [IT83XX_IRQ_WKO64] = {GPIO_F, BIT(4), 6, BIT(4)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(5), 6, BIT(5)}, - [IT83XX_IRQ_WKO65] = {GPIO_F, BIT(6), 6, BIT(6)}, - [IT83XX_IRQ_WKO67] = {GPIO_F, BIT(7), 6, BIT(7)}, - [IT83XX_IRQ_WKO70] = {GPIO_E, BIT(0), 7, BIT(0)}, - [IT83XX_IRQ_WKO71] = {GPIO_E, BIT(1), 7, BIT(1)}, - [IT83XX_IRQ_WKO72] = {GPIO_E, BIT(2), 7, BIT(2)}, - [IT83XX_IRQ_WKO73] = {GPIO_E, BIT(3), 7, BIT(3)}, - [IT83XX_IRQ_WKO74] = {GPIO_I, BIT(4), 7, BIT(4)}, - [IT83XX_IRQ_WKO75] = {GPIO_I, BIT(5), 7, BIT(5)}, - [IT83XX_IRQ_WKO76] = {GPIO_I, BIT(6), 7, BIT(6)}, - [IT83XX_IRQ_WKO77] = {GPIO_I, BIT(7), 7, BIT(7)}, - [IT83XX_IRQ_WKO80] = {GPIO_A, BIT(3), 8, BIT(0)}, - [IT83XX_IRQ_WKO81] = {GPIO_A, BIT(4), 8, BIT(1)}, - [IT83XX_IRQ_WKO82] = {GPIO_A, BIT(5), 8, BIT(2)}, - [IT83XX_IRQ_WKO83] = {GPIO_A, BIT(6), 8, BIT(3)}, - [IT83XX_IRQ_WKO84] = {GPIO_B, BIT(2), 8, BIT(4)}, - [IT83XX_IRQ_WKO85] = {GPIO_C, BIT(0), 8, BIT(5)}, - [IT83XX_IRQ_WKO86] = {GPIO_C, BIT(7), 8, BIT(6)}, - [IT83XX_IRQ_WKO87] = {GPIO_D, BIT(7), 8, BIT(7)}, - [IT83XX_IRQ_WKO88] = {GPIO_H, BIT(4), 9, BIT(0)}, - [IT83XX_IRQ_WKO89] = {GPIO_H, BIT(5), 9, BIT(1)}, - [IT83XX_IRQ_WKO90] = {GPIO_H, BIT(6), 9, BIT(2)}, - [IT83XX_IRQ_WKO91] = {GPIO_A, BIT(0), 9, BIT(3)}, - [IT83XX_IRQ_WKO92] = {GPIO_A, BIT(1), 9, BIT(4)}, - [IT83XX_IRQ_WKO93] = {GPIO_A, BIT(2), 9, BIT(5)}, - [IT83XX_IRQ_WKO94] = {GPIO_B, BIT(4), 9, BIT(6)}, - [IT83XX_IRQ_WKO95] = {GPIO_C, BIT(2), 9, BIT(7)}, - [IT83XX_IRQ_WKO96] = {GPIO_F, BIT(0), 10, BIT(0)}, - [IT83XX_IRQ_WKO97] = {GPIO_F, BIT(1), 10, BIT(1)}, - [IT83XX_IRQ_WKO98] = {GPIO_F, BIT(2), 10, BIT(2)}, - [IT83XX_IRQ_WKO99] = {GPIO_F, BIT(3), 10, BIT(3)}, - [IT83XX_IRQ_WKO100] = {GPIO_A, BIT(7), 10, BIT(4)}, - [IT83XX_IRQ_WKO101] = {GPIO_B, BIT(0), 10, BIT(5)}, - [IT83XX_IRQ_WKO102] = {GPIO_B, BIT(1), 10, BIT(6)}, - [IT83XX_IRQ_WKO103] = {GPIO_B, BIT(3), 10, BIT(7)}, - [IT83XX_IRQ_WKO104] = {GPIO_B, BIT(5), 11, BIT(0)}, - [IT83XX_IRQ_WKO105] = {GPIO_B, BIT(6), 11, BIT(1)}, - [IT83XX_IRQ_WKO106] = {GPIO_B, BIT(7), 11, BIT(2)}, - [IT83XX_IRQ_WKO107] = {GPIO_C, BIT(1), 11, BIT(3)}, - [IT83XX_IRQ_WKO108] = {GPIO_C, BIT(3), 11, BIT(4)}, - [IT83XX_IRQ_WKO109] = {GPIO_C, BIT(5), 11, BIT(5)}, - [IT83XX_IRQ_WKO110] = {GPIO_D, BIT(3), 11, BIT(6)}, - [IT83XX_IRQ_WKO111] = {GPIO_D, BIT(4), 11, BIT(7)}, - [IT83XX_IRQ_WKO112] = {GPIO_D, BIT(5), 12, BIT(0)}, - [IT83XX_IRQ_WKO113] = {GPIO_D, BIT(6), 12, BIT(1)}, - [IT83XX_IRQ_WKO114] = {GPIO_E, BIT(4), 12, BIT(2)}, - [IT83XX_IRQ_WKO115] = {GPIO_G, BIT(0), 12, BIT(3)}, - [IT83XX_IRQ_WKO116] = {GPIO_G, BIT(1), 12, BIT(4)}, - [IT83XX_IRQ_WKO117] = {GPIO_G, BIT(2), 12, BIT(5)}, - [IT83XX_IRQ_WKO118] = {GPIO_G, BIT(6), 12, BIT(6)}, - [IT83XX_IRQ_WKO119] = {GPIO_I, BIT(0), 12, BIT(7)}, - [IT83XX_IRQ_WKO120] = {GPIO_I, BIT(1), 13, BIT(0)}, - [IT83XX_IRQ_WKO121] = {GPIO_I, BIT(2), 13, BIT(1)}, - [IT83XX_IRQ_WKO122] = {GPIO_I, BIT(3), 13, BIT(2)}, + [IT83XX_IRQ_WKO50] = { GPIO_K, BIT(0), 5, BIT(0) }, + [IT83XX_IRQ_WKO51] = { GPIO_K, BIT(1), 5, BIT(1) }, + [IT83XX_IRQ_WKO52] = { GPIO_K, BIT(2), 5, BIT(2) }, + [IT83XX_IRQ_WKO53] = { GPIO_K, BIT(3), 5, BIT(3) }, + [IT83XX_IRQ_WKO54] = { GPIO_K, BIT(4), 5, BIT(4) }, + [IT83XX_IRQ_WKO55] = { GPIO_K, BIT(5), 5, BIT(5) }, + [IT83XX_IRQ_WKO56] = { GPIO_K, BIT(6), 5, BIT(6) }, + [IT83XX_IRQ_WKO57] = { GPIO_K, BIT(7), 5, BIT(7) }, + [IT83XX_IRQ_WKO60] = { GPIO_H, BIT(0), 6, BIT(0) }, + [IT83XX_IRQ_WKO61] = { GPIO_H, BIT(1), 6, BIT(1) }, + [IT83XX_IRQ_WKO62] = { GPIO_H, BIT(2), 6, BIT(2) }, + [IT83XX_IRQ_WKO63] = { GPIO_H, BIT(3), 6, BIT(3) }, + [IT83XX_IRQ_WKO64] = { GPIO_F, BIT(4), 6, BIT(4) }, + [IT83XX_IRQ_WKO65] = { GPIO_F, BIT(5), 6, BIT(5) }, + [IT83XX_IRQ_WKO65] = { GPIO_F, BIT(6), 6, BIT(6) }, + [IT83XX_IRQ_WKO67] = { GPIO_F, BIT(7), 6, BIT(7) }, + [IT83XX_IRQ_WKO70] = { GPIO_E, BIT(0), 7, BIT(0) }, + [IT83XX_IRQ_WKO71] = { GPIO_E, BIT(1), 7, BIT(1) }, + [IT83XX_IRQ_WKO72] = { GPIO_E, BIT(2), 7, BIT(2) }, + [IT83XX_IRQ_WKO73] = { GPIO_E, BIT(3), 7, BIT(3) }, + [IT83XX_IRQ_WKO74] = { GPIO_I, BIT(4), 7, BIT(4) }, + [IT83XX_IRQ_WKO75] = { GPIO_I, BIT(5), 7, BIT(5) }, + [IT83XX_IRQ_WKO76] = { GPIO_I, BIT(6), 7, BIT(6) }, + [IT83XX_IRQ_WKO77] = { GPIO_I, BIT(7), 7, BIT(7) }, + [IT83XX_IRQ_WKO80] = { GPIO_A, BIT(3), 8, BIT(0) }, + [IT83XX_IRQ_WKO81] = { GPIO_A, BIT(4), 8, BIT(1) }, + [IT83XX_IRQ_WKO82] = { GPIO_A, BIT(5), 8, BIT(2) }, + [IT83XX_IRQ_WKO83] = { GPIO_A, BIT(6), 8, BIT(3) }, + [IT83XX_IRQ_WKO84] = { GPIO_B, BIT(2), 8, BIT(4) }, + [IT83XX_IRQ_WKO85] = { GPIO_C, BIT(0), 8, BIT(5) }, + [IT83XX_IRQ_WKO86] = { GPIO_C, BIT(7), 8, BIT(6) }, + [IT83XX_IRQ_WKO87] = { GPIO_D, BIT(7), 8, BIT(7) }, + [IT83XX_IRQ_WKO88] = { GPIO_H, BIT(4), 9, BIT(0) }, + [IT83XX_IRQ_WKO89] = { GPIO_H, BIT(5), 9, BIT(1) }, + [IT83XX_IRQ_WKO90] = { GPIO_H, BIT(6), 9, BIT(2) }, + [IT83XX_IRQ_WKO91] = { GPIO_A, BIT(0), 9, BIT(3) }, + [IT83XX_IRQ_WKO92] = { GPIO_A, BIT(1), 9, BIT(4) }, + [IT83XX_IRQ_WKO93] = { GPIO_A, BIT(2), 9, BIT(5) }, + [IT83XX_IRQ_WKO94] = { GPIO_B, BIT(4), 9, BIT(6) }, + [IT83XX_IRQ_WKO95] = { GPIO_C, BIT(2), 9, BIT(7) }, + [IT83XX_IRQ_WKO96] = { GPIO_F, BIT(0), 10, BIT(0) }, + [IT83XX_IRQ_WKO97] = { GPIO_F, BIT(1), 10, BIT(1) }, + [IT83XX_IRQ_WKO98] = { GPIO_F, BIT(2), 10, BIT(2) }, + [IT83XX_IRQ_WKO99] = { GPIO_F, BIT(3), 10, BIT(3) }, + [IT83XX_IRQ_WKO100] = { GPIO_A, BIT(7), 10, BIT(4) }, + [IT83XX_IRQ_WKO101] = { GPIO_B, BIT(0), 10, BIT(5) }, + [IT83XX_IRQ_WKO102] = { GPIO_B, BIT(1), 10, BIT(6) }, + [IT83XX_IRQ_WKO103] = { GPIO_B, BIT(3), 10, BIT(7) }, + [IT83XX_IRQ_WKO104] = { GPIO_B, BIT(5), 11, BIT(0) }, + [IT83XX_IRQ_WKO105] = { GPIO_B, BIT(6), 11, BIT(1) }, + [IT83XX_IRQ_WKO106] = { GPIO_B, BIT(7), 11, BIT(2) }, + [IT83XX_IRQ_WKO107] = { GPIO_C, BIT(1), 11, BIT(3) }, + [IT83XX_IRQ_WKO108] = { GPIO_C, BIT(3), 11, BIT(4) }, + [IT83XX_IRQ_WKO109] = { GPIO_C, BIT(5), 11, BIT(5) }, + [IT83XX_IRQ_WKO110] = { GPIO_D, BIT(3), 11, BIT(6) }, + [IT83XX_IRQ_WKO111] = { GPIO_D, BIT(4), 11, BIT(7) }, + [IT83XX_IRQ_WKO112] = { GPIO_D, BIT(5), 12, BIT(0) }, + [IT83XX_IRQ_WKO113] = { GPIO_D, BIT(6), 12, BIT(1) }, + [IT83XX_IRQ_WKO114] = { GPIO_E, BIT(4), 12, BIT(2) }, + [IT83XX_IRQ_WKO115] = { GPIO_G, BIT(0), 12, BIT(3) }, + [IT83XX_IRQ_WKO116] = { GPIO_G, BIT(1), 12, BIT(4) }, + [IT83XX_IRQ_WKO117] = { GPIO_G, BIT(2), 12, BIT(5) }, + [IT83XX_IRQ_WKO118] = { GPIO_G, BIT(6), 12, BIT(6) }, + [IT83XX_IRQ_WKO119] = { GPIO_I, BIT(0), 12, BIT(7) }, + [IT83XX_IRQ_WKO120] = { GPIO_I, BIT(1), 13, BIT(0) }, + [IT83XX_IRQ_WKO121] = { GPIO_I, BIT(2), 13, BIT(1) }, + [IT83XX_IRQ_WKO122] = { GPIO_I, BIT(3), 13, BIT(2) }, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO123] = {GPIO_G, BIT(3), 13, BIT(3)}, - [IT83XX_IRQ_WKO124] = {GPIO_G, BIT(4), 13, BIT(4)}, - [IT83XX_IRQ_WKO125] = {GPIO_G, BIT(5), 13, BIT(5)}, - [IT83XX_IRQ_WKO126] = {GPIO_G, BIT(7), 13, BIT(6)}, + [IT83XX_IRQ_WKO123] = { GPIO_G, BIT(3), 13, BIT(3) }, + [IT83XX_IRQ_WKO124] = { GPIO_G, BIT(4), 13, BIT(4) }, + [IT83XX_IRQ_WKO125] = { GPIO_G, BIT(5), 13, BIT(5) }, + [IT83XX_IRQ_WKO126] = { GPIO_G, BIT(7), 13, BIT(6) }, #endif - [IT83XX_IRQ_WKO128] = {GPIO_J, BIT(0), 14, BIT(0)}, - [IT83XX_IRQ_WKO129] = {GPIO_J, BIT(1), 14, BIT(1)}, - [IT83XX_IRQ_WKO130] = {GPIO_J, BIT(2), 14, BIT(2)}, - [IT83XX_IRQ_WKO131] = {GPIO_J, BIT(3), 14, BIT(3)}, - [IT83XX_IRQ_WKO132] = {GPIO_J, BIT(4), 14, BIT(4)}, - [IT83XX_IRQ_WKO133] = {GPIO_J, BIT(5), 14, BIT(5)}, - [IT83XX_IRQ_WKO134] = {GPIO_J, BIT(6), 14, BIT(6)}, - [IT83XX_IRQ_WKO135] = {GPIO_J, BIT(7), 14, BIT(7)}, - [IT83XX_IRQ_WKO136] = {GPIO_L, BIT(0), 15, BIT(0)}, - [IT83XX_IRQ_WKO137] = {GPIO_L, BIT(1), 15, BIT(1)}, - [IT83XX_IRQ_WKO138] = {GPIO_L, BIT(2), 15, BIT(2)}, - [IT83XX_IRQ_WKO139] = {GPIO_L, BIT(3), 15, BIT(3)}, - [IT83XX_IRQ_WKO140] = {GPIO_L, BIT(4), 15, BIT(4)}, - [IT83XX_IRQ_WKO141] = {GPIO_L, BIT(5), 15, BIT(5)}, - [IT83XX_IRQ_WKO142] = {GPIO_L, BIT(6), 15, BIT(6)}, - [IT83XX_IRQ_WKO143] = {GPIO_L, BIT(7), 15, BIT(7)}, + [IT83XX_IRQ_WKO128] = { GPIO_J, BIT(0), 14, BIT(0) }, + [IT83XX_IRQ_WKO129] = { GPIO_J, BIT(1), 14, BIT(1) }, + [IT83XX_IRQ_WKO130] = { GPIO_J, BIT(2), 14, BIT(2) }, + [IT83XX_IRQ_WKO131] = { GPIO_J, BIT(3), 14, BIT(3) }, + [IT83XX_IRQ_WKO132] = { GPIO_J, BIT(4), 14, BIT(4) }, + [IT83XX_IRQ_WKO133] = { GPIO_J, BIT(5), 14, BIT(5) }, + [IT83XX_IRQ_WKO134] = { GPIO_J, BIT(6), 14, BIT(6) }, + [IT83XX_IRQ_WKO135] = { GPIO_J, BIT(7), 14, BIT(7) }, + [IT83XX_IRQ_WKO136] = { GPIO_L, BIT(0), 15, BIT(0) }, + [IT83XX_IRQ_WKO137] = { GPIO_L, BIT(1), 15, BIT(1) }, + [IT83XX_IRQ_WKO138] = { GPIO_L, BIT(2), 15, BIT(2) }, + [IT83XX_IRQ_WKO139] = { GPIO_L, BIT(3), 15, BIT(3) }, + [IT83XX_IRQ_WKO140] = { GPIO_L, BIT(4), 15, BIT(4) }, + [IT83XX_IRQ_WKO141] = { GPIO_L, BIT(5), 15, BIT(5) }, + [IT83XX_IRQ_WKO142] = { GPIO_L, BIT(6), 15, BIT(6) }, + [IT83XX_IRQ_WKO143] = { GPIO_L, BIT(7), 15, BIT(7) }, #ifdef IT83XX_GPIO_INT_FLEXIBLE - [IT83XX_IRQ_WKO144] = {GPIO_M, BIT(0), 16, BIT(0)}, - [IT83XX_IRQ_WKO145] = {GPIO_M, BIT(1), 16, BIT(1)}, - [IT83XX_IRQ_WKO146] = {GPIO_M, BIT(2), 16, BIT(2)}, - [IT83XX_IRQ_WKO147] = {GPIO_M, BIT(3), 16, BIT(3)}, - [IT83XX_IRQ_WKO148] = {GPIO_M, BIT(4), 16, BIT(4)}, - [IT83XX_IRQ_WKO149] = {GPIO_M, BIT(5), 16, BIT(5)}, - [IT83XX_IRQ_WKO150] = {GPIO_M, BIT(6), 16, BIT(6)}, + [IT83XX_IRQ_WKO144] = { GPIO_M, BIT(0), 16, BIT(0) }, + [IT83XX_IRQ_WKO145] = { GPIO_M, BIT(1), 16, BIT(1) }, + [IT83XX_IRQ_WKO146] = { GPIO_M, BIT(2), 16, BIT(2) }, + [IT83XX_IRQ_WKO147] = { GPIO_M, BIT(3), 16, BIT(3) }, + [IT83XX_IRQ_WKO148] = { GPIO_M, BIT(4), 16, BIT(4) }, + [IT83XX_IRQ_WKO149] = { GPIO_M, BIT(5), 16, BIT(5) }, + [IT83XX_IRQ_WKO150] = { GPIO_M, BIT(6), 16, BIT(6) }, #endif #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [IT83XX_IRQ_GPO0] = {GPIO_O, BIT(0), 19, BIT(0)}, - [IT83XX_IRQ_GPO1] = {GPIO_O, BIT(1), 19, BIT(1)}, - [IT83XX_IRQ_GPO2] = {GPIO_O, BIT(2), 19, BIT(2)}, - [IT83XX_IRQ_GPO3] = {GPIO_O, BIT(3), 19, BIT(3)}, - [IT83XX_IRQ_GPP0] = {GPIO_P, BIT(0), 20, BIT(0)}, - [IT83XX_IRQ_GPP1] = {GPIO_P, BIT(1), 20, BIT(1)}, - [IT83XX_IRQ_GPP2] = {GPIO_P, BIT(2), 20, BIT(2)}, - [IT83XX_IRQ_GPP3] = {GPIO_P, BIT(3), 20, BIT(3)}, - [IT83XX_IRQ_GPP4] = {GPIO_P, BIT(4), 20, BIT(4)}, - [IT83XX_IRQ_GPP5] = {GPIO_P, BIT(5), 20, BIT(5)}, - [IT83XX_IRQ_GPP6] = {GPIO_P, BIT(6), 20, BIT(6)}, - [IT83XX_IRQ_GPQ0] = {GPIO_Q, BIT(0), 21, BIT(0)}, - [IT83XX_IRQ_GPQ1] = {GPIO_Q, BIT(1), 21, BIT(1)}, - [IT83XX_IRQ_GPQ2] = {GPIO_Q, BIT(2), 21, BIT(2)}, - [IT83XX_IRQ_GPQ3] = {GPIO_Q, BIT(3), 21, BIT(3)}, - [IT83XX_IRQ_GPQ4] = {GPIO_Q, BIT(4), 21, BIT(4)}, - [IT83XX_IRQ_GPQ5] = {GPIO_Q, BIT(5), 21, BIT(5)}, - [IT83XX_IRQ_GPR0] = {GPIO_R, BIT(0), 22, BIT(0)}, - [IT83XX_IRQ_GPR1] = {GPIO_R, BIT(1), 22, BIT(1)}, - [IT83XX_IRQ_GPR2] = {GPIO_R, BIT(2), 22, BIT(2)}, - [IT83XX_IRQ_GPR3] = {GPIO_R, BIT(3), 22, BIT(3)}, - [IT83XX_IRQ_GPR4] = {GPIO_R, BIT(4), 22, BIT(4)}, - [IT83XX_IRQ_GPR5] = {GPIO_R, BIT(5), 22, BIT(5)}, + [IT83XX_IRQ_GPO0] = { GPIO_O, BIT(0), 19, BIT(0) }, + [IT83XX_IRQ_GPO1] = { GPIO_O, BIT(1), 19, BIT(1) }, + [IT83XX_IRQ_GPO2] = { GPIO_O, BIT(2), 19, BIT(2) }, + [IT83XX_IRQ_GPO3] = { GPIO_O, BIT(3), 19, BIT(3) }, + [IT83XX_IRQ_GPP0] = { GPIO_P, BIT(0), 20, BIT(0) }, + [IT83XX_IRQ_GPP1] = { GPIO_P, BIT(1), 20, BIT(1) }, + [IT83XX_IRQ_GPP2] = { GPIO_P, BIT(2), 20, BIT(2) }, + [IT83XX_IRQ_GPP3] = { GPIO_P, BIT(3), 20, BIT(3) }, + [IT83XX_IRQ_GPP4] = { GPIO_P, BIT(4), 20, BIT(4) }, + [IT83XX_IRQ_GPP5] = { GPIO_P, BIT(5), 20, BIT(5) }, + [IT83XX_IRQ_GPP6] = { GPIO_P, BIT(6), 20, BIT(6) }, + [IT83XX_IRQ_GPQ0] = { GPIO_Q, BIT(0), 21, BIT(0) }, + [IT83XX_IRQ_GPQ1] = { GPIO_Q, BIT(1), 21, BIT(1) }, + [IT83XX_IRQ_GPQ2] = { GPIO_Q, BIT(2), 21, BIT(2) }, + [IT83XX_IRQ_GPQ3] = { GPIO_Q, BIT(3), 21, BIT(3) }, + [IT83XX_IRQ_GPQ4] = { GPIO_Q, BIT(4), 21, BIT(4) }, + [IT83XX_IRQ_GPQ5] = { GPIO_Q, BIT(5), 21, BIT(5) }, + [IT83XX_IRQ_GPR0] = { GPIO_R, BIT(0), 22, BIT(0) }, + [IT83XX_IRQ_GPR1] = { GPIO_R, BIT(1), 22, BIT(1) }, + [IT83XX_IRQ_GPR2] = { GPIO_R, BIT(2), 22, BIT(2) }, + [IT83XX_IRQ_GPR3] = { GPIO_R, BIT(3), 22, BIT(3) }, + [IT83XX_IRQ_GPR4] = { GPIO_R, BIT(4), 22, BIT(4) }, + [IT83XX_IRQ_GPR5] = { GPIO_R, BIT(5), 22, BIT(5) }, #endif - [IT83XX_IRQ_COUNT] = { 0, 0, 0, 0}, + [IT83XX_IRQ_COUNT] = { 0, 0, 0, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1); @@ -263,7 +263,7 @@ static int gpio_to_irq(uint8_t port, uint8_t mask) for (i = 0; i < IT83XX_IRQ_COUNT; i++) { if (gpio_irqs[i].gpio_port == port && - gpio_irqs[i].gpio_mask == mask) + gpio_irqs[i].gpio_mask == mask) return i; } @@ -277,133 +277,133 @@ struct gpio_1p8v_t { static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = { #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC24, BIT(1)}, - [6] = {&IT83XX_GPIO_GRC24, BIT(5)}, - [7] = {&IT83XX_GPIO_GRC24, BIT(6)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC19, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC24, BIT(4)} }, - [GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, - [4] = {&IT83XX_GPIO_GRC24, BIT(2)}, - [6] = {&IT83XX_GPIO_GRC24, BIT(3)}, - [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(6)}, - [5] = {&IT83XX_GPIO_GRC22, BIT(4)}, - [6] = {&IT83XX_GPIO_GRC22, BIT(5)}, - [7] = {&IT83XX_GPIO_GRC22, BIT(6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, - [1] = {&IT83XX_GPIO_GCR28, BIT(6)}, - [2] = {&IT83XX_GPIO_GCR28, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(2)}, - [5] = {&IT83XX_GPIO_GRC22, BIT(3)}, - [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, - [GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)}, - [1] = {&IT83XX_GPIO_GCR28, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, - [GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(4)}, - [2] = {&IT83XX_GPIO_GCR28, BIT(3)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(3)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC21, BIT(0)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(7)}, - [6] = {&IT83XX_GPIO_GCR28, BIT(0)} }, - [GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, - [4] = {&IT83XX_GPIO_GRC23, BIT(7)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(4)}, - [6] = {&IT83XX_GPIO_GCR27, BIT(5)}, - [7] = {&IT83XX_GPIO_GCR27, BIT(6)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR27, BIT(0)}, - [5] = {&IT83XX_GPIO_GCR27, BIT(1)}, - [6] = {&IT83XX_GPIO_GCR27, BIT(2)}, - [7] = {&IT83XX_GPIO_GCR33, BIT(2)} }, - [GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR26, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR26, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR26, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR26, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR26, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR26, BIT(6)}, - [7] = {&IT83XX_GPIO_GCR26, BIT(7)} }, - [GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR25, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR25, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR25, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR25, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR25, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR25, BIT(6)}, - [7] = {&IT83XX_GPIO_GCR25, BIT(7)} }, + [GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC24, BIT(1) }, + [6] = { &IT83XX_GPIO_GRC24, BIT(5) }, + [7] = { &IT83XX_GPIO_GRC24, BIT(6) } }, + [GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) }, + [4] = { &IT83XX_GPIO_GRC22, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC19, BIT(7) }, + [6] = { &IT83XX_GPIO_GRC19, BIT(6) }, + [7] = { &IT83XX_GPIO_GRC24, BIT(4) } }, + [GPIO_C] = { [0] = { &IT83XX_GPIO_GRC22, BIT(7) }, + [1] = { &IT83XX_GPIO_GRC19, BIT(5) }, + [2] = { &IT83XX_GPIO_GRC19, BIT(4) }, + [4] = { &IT83XX_GPIO_GRC24, BIT(2) }, + [6] = { &IT83XX_GPIO_GRC24, BIT(3) }, + [7] = { &IT83XX_GPIO_GRC19, BIT(3) } }, + [GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) }, + [1] = { &IT83XX_GPIO_GRC19, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC19, BIT(0) }, + [3] = { &IT83XX_GPIO_GRC20, BIT(7) }, + [4] = { &IT83XX_GPIO_GRC20, BIT(6) }, + [5] = { &IT83XX_GPIO_GRC22, BIT(4) }, + [6] = { &IT83XX_GPIO_GRC22, BIT(5) }, + [7] = { &IT83XX_GPIO_GRC22, BIT(6) } }, + [GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) }, + [1] = { &IT83XX_GPIO_GCR28, BIT(6) }, + [2] = { &IT83XX_GPIO_GCR28, BIT(7) }, + [4] = { &IT83XX_GPIO_GRC22, BIT(2) }, + [5] = { &IT83XX_GPIO_GRC22, BIT(3) }, + [6] = { &IT83XX_GPIO_GRC20, BIT(4) }, + [7] = { &IT83XX_GPIO_GRC20, BIT(3) } }, + [GPIO_F] = { [0] = { &IT83XX_GPIO_GCR28, BIT(4) }, + [1] = { &IT83XX_GPIO_GCR28, BIT(5) }, + [2] = { &IT83XX_GPIO_GRC20, BIT(2) }, + [3] = { &IT83XX_GPIO_GRC20, BIT(1) }, + [4] = { &IT83XX_GPIO_GRC20, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC21, BIT(7) }, + [6] = { &IT83XX_GPIO_GRC21, BIT(6) }, + [7] = { &IT83XX_GPIO_GRC21, BIT(5) } }, + [GPIO_G] = { [0] = { &IT83XX_GPIO_GCR28, BIT(2) }, + [1] = { &IT83XX_GPIO_GRC21, BIT(4) }, + [2] = { &IT83XX_GPIO_GCR28, BIT(3) }, + [6] = { &IT83XX_GPIO_GRC21, BIT(3) } }, + [GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) }, + [1] = { &IT83XX_GPIO_GRC21, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC21, BIT(0) }, + [5] = { &IT83XX_GPIO_GCR27, BIT(7) }, + [6] = { &IT83XX_GPIO_GCR28, BIT(0) } }, + [GPIO_I] = { [0] = { &IT83XX_GPIO_GCR27, BIT(3) }, + [1] = { &IT83XX_GPIO_GRC23, BIT(4) }, + [2] = { &IT83XX_GPIO_GRC23, BIT(5) }, + [3] = { &IT83XX_GPIO_GRC23, BIT(6) }, + [4] = { &IT83XX_GPIO_GRC23, BIT(7) }, + [5] = { &IT83XX_GPIO_GCR27, BIT(4) }, + [6] = { &IT83XX_GPIO_GCR27, BIT(5) }, + [7] = { &IT83XX_GPIO_GCR27, BIT(6) } }, + [GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) }, + [1] = { &IT83XX_GPIO_GRC23, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC23, BIT(2) }, + [3] = { &IT83XX_GPIO_GRC23, BIT(3) }, + [4] = { &IT83XX_GPIO_GCR27, BIT(0) }, + [5] = { &IT83XX_GPIO_GCR27, BIT(1) }, + [6] = { &IT83XX_GPIO_GCR27, BIT(2) }, + [7] = { &IT83XX_GPIO_GCR33, BIT(2) } }, + [GPIO_K] = { [0] = { &IT83XX_GPIO_GCR26, BIT(0) }, + [1] = { &IT83XX_GPIO_GCR26, BIT(1) }, + [2] = { &IT83XX_GPIO_GCR26, BIT(2) }, + [3] = { &IT83XX_GPIO_GCR26, BIT(3) }, + [4] = { &IT83XX_GPIO_GCR26, BIT(4) }, + [5] = { &IT83XX_GPIO_GCR26, BIT(5) }, + [6] = { &IT83XX_GPIO_GCR26, BIT(6) }, + [7] = { &IT83XX_GPIO_GCR26, BIT(7) } }, + [GPIO_L] = { [0] = { &IT83XX_GPIO_GCR25, BIT(0) }, + [1] = { &IT83XX_GPIO_GCR25, BIT(1) }, + [2] = { &IT83XX_GPIO_GCR25, BIT(2) }, + [3] = { &IT83XX_GPIO_GCR25, BIT(3) }, + [4] = { &IT83XX_GPIO_GCR25, BIT(4) }, + [5] = { &IT83XX_GPIO_GCR25, BIT(5) }, + [6] = { &IT83XX_GPIO_GCR25, BIT(6) }, + [7] = { &IT83XX_GPIO_GCR25, BIT(7) } }, #if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2) - [GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR31, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR31, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR31, BIT(3)} }, - [GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)}, - [1] = {&IT83XX_GPIO_GCR32, BIT(1)}, - [2] = {&IT83XX_GPIO_GCR32, BIT(2)}, - [3] = {&IT83XX_GPIO_GCR32, BIT(3)}, - [4] = {&IT83XX_GPIO_GCR32, BIT(4)}, - [5] = {&IT83XX_GPIO_GCR32, BIT(5)}, - [6] = {&IT83XX_GPIO_GCR32, BIT(6)} }, + [GPIO_O] = { [0] = { &IT83XX_GPIO_GCR31, BIT(0) }, + [1] = { &IT83XX_GPIO_GCR31, BIT(1) }, + [2] = { &IT83XX_GPIO_GCR31, BIT(2) }, + [3] = { &IT83XX_GPIO_GCR31, BIT(3) } }, + [GPIO_P] = { [0] = { &IT83XX_GPIO_GCR32, BIT(0) }, + [1] = { &IT83XX_GPIO_GCR32, BIT(1) }, + [2] = { &IT83XX_GPIO_GCR32, BIT(2) }, + [3] = { &IT83XX_GPIO_GCR32, BIT(3) }, + [4] = { &IT83XX_GPIO_GCR32, BIT(4) }, + [5] = { &IT83XX_GPIO_GCR32, BIT(5) }, + [6] = { &IT83XX_GPIO_GCR32, BIT(6) } }, #endif #else - [GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC24, BIT(1)} }, - [GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC22, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC19, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC19, BIT(6)} }, - [GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC19, BIT(3)} }, - [GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC19, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC19, BIT(0)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(7)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(6)} }, - [GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)}, - [6] = {&IT83XX_GPIO_GRC20, BIT(4)}, - [7] = {&IT83XX_GPIO_GRC20, BIT(3)} }, - [GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC20, BIT(1)}, - [4] = {&IT83XX_GPIO_GRC20, BIT(0)}, - [5] = {&IT83XX_GPIO_GRC21, BIT(7)}, - [6] = {&IT83XX_GPIO_GRC21, BIT(6)}, - [7] = {&IT83XX_GPIO_GRC21, BIT(5)} }, - [GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)}, - [1] = {&IT83XX_GPIO_GRC21, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC21, BIT(0)} }, - [GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(5)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(6)}, - [4] = {&IT83XX_GPIO_GRC23, BIT(7)} }, - [GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)}, - [1] = {&IT83XX_GPIO_GRC23, BIT(1)}, - [2] = {&IT83XX_GPIO_GRC23, BIT(2)}, - [3] = {&IT83XX_GPIO_GRC23, BIT(3)} }, + [GPIO_A] = { [4] = { &IT83XX_GPIO_GRC24, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC24, BIT(1) } }, + [GPIO_B] = { [3] = { &IT83XX_GPIO_GRC22, BIT(1) }, + [4] = { &IT83XX_GPIO_GRC22, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC19, BIT(7) }, + [6] = { &IT83XX_GPIO_GRC19, BIT(6) } }, + [GPIO_C] = { [1] = { &IT83XX_GPIO_GRC19, BIT(5) }, + [2] = { &IT83XX_GPIO_GRC19, BIT(4) }, + [7] = { &IT83XX_GPIO_GRC19, BIT(3) } }, + [GPIO_D] = { [0] = { &IT83XX_GPIO_GRC19, BIT(2) }, + [1] = { &IT83XX_GPIO_GRC19, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC19, BIT(0) }, + [3] = { &IT83XX_GPIO_GRC20, BIT(7) }, + [4] = { &IT83XX_GPIO_GRC20, BIT(6) } }, + [GPIO_E] = { [0] = { &IT83XX_GPIO_GRC20, BIT(5) }, + [6] = { &IT83XX_GPIO_GRC20, BIT(4) }, + [7] = { &IT83XX_GPIO_GRC20, BIT(3) } }, + [GPIO_F] = { [2] = { &IT83XX_GPIO_GRC20, BIT(2) }, + [3] = { &IT83XX_GPIO_GRC20, BIT(1) }, + [4] = { &IT83XX_GPIO_GRC20, BIT(0) }, + [5] = { &IT83XX_GPIO_GRC21, BIT(7) }, + [6] = { &IT83XX_GPIO_GRC21, BIT(6) }, + [7] = { &IT83XX_GPIO_GRC21, BIT(5) } }, + [GPIO_H] = { [0] = { &IT83XX_GPIO_GRC21, BIT(2) }, + [1] = { &IT83XX_GPIO_GRC21, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC21, BIT(0) } }, + [GPIO_I] = { [1] = { &IT83XX_GPIO_GRC23, BIT(4) }, + [2] = { &IT83XX_GPIO_GRC23, BIT(5) }, + [3] = { &IT83XX_GPIO_GRC23, BIT(6) }, + [4] = { &IT83XX_GPIO_GRC23, BIT(7) } }, + [GPIO_J] = { [0] = { &IT83XX_GPIO_GRC23, BIT(0) }, + [1] = { &IT83XX_GPIO_GRC23, BIT(1) }, + [2] = { &IT83XX_GPIO_GRC23, BIT(2) }, + [3] = { &IT83XX_GPIO_GRC23, BIT(3) } }, #endif }; @@ -422,23 +422,23 @@ static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v) } static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { /* * If func is not ALT_FUNC_NONE, set for alternate function. * Otherwise, turn the pin into an input as it's default. */ if (func != GPIO_ALT_FUNC_NONE) - IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT | - GPCR_PORT_PIN_MODE_INPUT); + IT83XX_GPIO_CTRL(port, pin) &= + ~(GPCR_PORT_PIN_MODE_OUTPUT | GPCR_PORT_PIN_MODE_INPUT); else - IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT) - & ~GPCR_PORT_PIN_MODE_OUTPUT; + IT83XX_GPIO_CTRL(port, pin) = (IT83XX_GPIO_CTRL(port, pin) | + GPCR_PORT_PIN_MODE_INPUT) & + ~GPCR_PORT_PIN_MODE_OUTPUT; } void gpio_set_alternate_function(uint32_t port, uint32_t mask, - enum gpio_alternate_func func) + enum gpio_alternate_func func) { uint32_t pin = 0; @@ -473,7 +473,9 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, test_mockable int gpio_get_level(enum gpio_signal signal) { return (IT83XX_GPIO_DATA_MIRROR(gpio_list[signal].port) & - gpio_list[signal].mask) ? 1 : 0; + gpio_list[signal].mask) ? + 1 : + 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -483,10 +485,10 @@ void gpio_set_level(enum gpio_signal signal, int value) if (value) IT83XX_GPIO_DATA(gpio_list[signal].port) |= - gpio_list[signal].mask; + gpio_list[signal].mask; else IT83XX_GPIO_DATA(gpio_list[signal].port) &= - ~gpio_list[signal].mask; + ~gpio_list[signal].mask; /* restore interrupts */ set_int_mask(int_mask); } @@ -591,26 +593,26 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set input or output. */ if (flags & GPIO_OUTPUT) IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_OUTPUT) & - ~GPCR_PORT_PIN_MODE_INPUT; + (IT83XX_GPIO_CTRL(port, pin) | + GPCR_PORT_PIN_MODE_OUTPUT) & + ~GPCR_PORT_PIN_MODE_INPUT; else IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_INPUT) & - ~GPCR_PORT_PIN_MODE_OUTPUT; + (IT83XX_GPIO_CTRL(port, pin) | + GPCR_PORT_PIN_MODE_INPUT) & + ~GPCR_PORT_PIN_MODE_OUTPUT; /* Handle pullup / pulldown */ if (flags & GPIO_PULL_UP) { IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_PULLUP) & - ~GPCR_PORT_PIN_MODE_PULLDOWN; + (IT83XX_GPIO_CTRL(port, pin) | + GPCR_PORT_PIN_MODE_PULLUP) & + ~GPCR_PORT_PIN_MODE_PULLDOWN; } else if (flags & GPIO_PULL_DOWN) { IT83XX_GPIO_CTRL(port, pin) = - (IT83XX_GPIO_CTRL(port, pin) | - GPCR_PORT_PIN_MODE_PULLDOWN) & - ~GPCR_PORT_PIN_MODE_PULLUP; + (IT83XX_GPIO_CTRL(port, pin) | + GPCR_PORT_PIN_MODE_PULLDOWN) & + ~GPCR_PORT_PIN_MODE_PULLUP; } else { /* No pull up/down */ IT83XX_GPIO_CTRL(port, pin) &= @@ -620,7 +622,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* To select 1.8v or 3.3v support. */ gpio_1p8v_3p3v_sel_by_pin(port, pin, - (flags & GPIO_SEL_1P8V)); + (flags & GPIO_SEL_1P8V)); } pin++; @@ -804,10 +806,12 @@ void gpio_pre_init(void) */ if (IS_ENABLED(IT83XX_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) { for (i = 0; i < 8; i++) { - IT83XX_GPIO_CTRL(GPIO_K, i) = (GPCR_PORT_PIN_MODE_INPUT - | GPCR_PORT_PIN_MODE_PULLDOWN); - IT83XX_GPIO_CTRL(GPIO_L, i) = (GPCR_PORT_PIN_MODE_INPUT - | GPCR_PORT_PIN_MODE_PULLDOWN); + IT83XX_GPIO_CTRL(GPIO_K, i) = + (GPCR_PORT_PIN_MODE_INPUT | + GPCR_PORT_PIN_MODE_PULLDOWN); + IT83XX_GPIO_CTRL(GPIO_L, i) = + (GPCR_PORT_PIN_MODE_INPUT | + GPCR_PORT_PIN_MODE_PULLDOWN); } } -- cgit v1.2.1 From e0495d5e82762dcbecdb82ab4054f0a0469105dc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:09 -0600 Subject: board/beadrix/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e4ca1620649843ff1aeeb869bf41d40073006a2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728005 Reviewed-by: Jeremy Bettis --- board/beadrix/board.c | 215 +++++++++++++++++++++++--------------------------- 1 file changed, 100 insertions(+), 115 deletions(-) diff --git a/board/beadrix/board.c b/board/beadrix/board.c index 0fb2f9773b..52d643ecd2 100644 --- a/board/beadrix/board.c +++ b/board/beadrix/board.c @@ -39,8 +39,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -142,34 +142,26 @@ __override void board_pulse_entering_rw(void) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_SUB_ANALOG] = { - .name = "SUB_ANALOG", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH13 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_SUB_ANALOG] = { .name = "SUB_ANALOG", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH13 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -224,7 +216,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; static int board_nb7v904m_mux_set(const struct usb_mux *me, - mux_state_t mux_state); + mux_state_t mux_state); /* USB Retimer */ const struct usb_mux usbc1_retimer = { @@ -243,7 +235,8 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { .i2c_addr_flags = IT5205_I2C_ADDR1_FLAGS, .driver = &it5205_usb_mux_driver, }, - { /* Used as MUX only*/ + { + /* Used as MUX only*/ .usb_port = 1, .i2c_port = I2C_PORT_SUB_USB_C1, .i2c_addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, @@ -255,7 +248,7 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB Mux */ static int board_nb7v904m_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; int flipped = !!(mux_state & USB_PD_MUX_POLARITY_INVERTED); @@ -264,75 +257,71 @@ static int board_nb7v904m_mux_set(const struct usb_mux *me, /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { if (flipped) { /* CC2 */ - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_0_DB, - NB7V904M_CH_B_EQ_4_DB, - NB7V904M_CH_C_EQ_0_DB, - NB7V904M_CH_D_EQ_0_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_3P5_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D); + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_4_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D); } /* CC1 */ else { - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_0_DB, - NB7V904M_CH_B_EQ_0_DB, - NB7V904M_CH_C_EQ_4_DB, - NB7V904M_CH_D_EQ_0_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_3P5_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A); - } - } else { - /* USB only */ - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_0_DB, - NB7V904M_CH_B_EQ_4_DB, + rv |= nb7v904m_tune_usb_set_eq( + me, NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_0_DB, NB7V904M_CH_C_EQ_4_DB, NB7V904M_CH_D_EQ_0_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_3P5_DB, + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, NB7V904M_CH_C_GAIN_3P5_DB, NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_A, - NB7V904M_LOSS_PROFILE_A, + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_A, NB7V904M_LOSS_PROFILE_A); + } + } else { + /* USB only */ + rv |= nb7v904m_tune_usb_set_eq(me, + NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_4_DB, + NB7V904M_CH_C_EQ_4_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain( + me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_3P5_DB, + NB7V904M_CH_C_GAIN_3P5_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A, + NB7V904M_LOSS_PROFILE_A); } } else if (mux_state & USB_PD_MUX_DP_ENABLED) { /* 4 lanes DP */ - rv |= nb7v904m_tune_usb_set_eq(me, - NB7V904M_CH_A_EQ_0_DB, - NB7V904M_CH_B_EQ_0_DB, - NB7V904M_CH_C_EQ_0_DB, - NB7V904M_CH_D_EQ_0_DB); - rv |= nb7v904m_tune_usb_flat_gain(me, - NB7V904M_CH_A_GAIN_0_DB, - NB7V904M_CH_B_GAIN_0_DB, - NB7V904M_CH_C_GAIN_0_DB, - NB7V904M_CH_D_GAIN_0_DB); - rv |= nb7v904m_set_loss_profile_match(me, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D, - NB7V904M_LOSS_PROFILE_D); + rv |= nb7v904m_tune_usb_set_eq(me, NB7V904M_CH_A_EQ_0_DB, + NB7V904M_CH_B_EQ_0_DB, + NB7V904M_CH_C_EQ_0_DB, + NB7V904M_CH_D_EQ_0_DB); + rv |= nb7v904m_tune_usb_flat_gain(me, NB7V904M_CH_A_GAIN_0_DB, + NB7V904M_CH_B_GAIN_0_DB, + NB7V904M_CH_C_GAIN_0_DB, + NB7V904M_CH_D_GAIN_0_DB); + rv |= nb7v904m_set_loss_profile_match( + me, NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D, + NB7V904M_LOSS_PROFILE_D, NB7V904M_LOSS_PROFILE_D); } return rv; @@ -406,8 +395,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -476,8 +464,8 @@ int board_set_active_charge_port(int port) } /* Vconn control for integrated ITE TCPC */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -518,7 +506,7 @@ uint16_t tcpc_get_alert_status(void) } if (board_get_usb_pd_port_count() > 1 && - !gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) { + !gpio_get_level(GPIO_USB_C1_INT_V1_ODL)) { if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { /* TCPCI spec Rev 1.0 says to ignore bits 14:12. */ if (!(tcpc_config[1].flags & TCPC_FLAGS_TCPCI_REV2_0)) @@ -532,9 +520,8 @@ uint16_t tcpc_get_alert_status(void) return status; } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -550,25 +537,23 @@ int pd_snk_is_vbus_provided(int port) } /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ -const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { - .channel = 0, - .flags = PWM_CONFIG_DSLEEP, - .freq_hz = 10000, - } -}; +const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { + .channel = 0, + .flags = PWM_CONFIG_DSLEEP, + .freq_hz = 10000, + } }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -589,8 +574,8 @@ static const struct ec_response_keybd_config keybd1 = { /* No function keys, no numeric keypad and no screenlock key */ }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { /* * Future boards should use fw_config if needed. -- cgit v1.2.1 From 34265e888396bb1cfc2f19a30d68cbb5869ecf81 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:03 -0600 Subject: driver/temp_sensor/ec_adc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia898ea2526f7d7544efb1dd54039192d2f5e06ef Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730116 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/ec_adc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/temp_sensor/ec_adc.h b/driver/temp_sensor/ec_adc.h index 8ff213e95d..b14d5be4aa 100644 --- a/driver/temp_sensor/ec_adc.h +++ b/driver/temp_sensor/ec_adc.h @@ -21,4 +21,4 @@ */ int ec_adc_get_val(int idx, int *temp_ptr); -#endif /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */ +#endif /* __CROS_EC_TEMP_SENSOR_EC_ADC_H */ -- cgit v1.2.1 From 47ee1f3149caa1d69406cefc089cef7ae2dc9f2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:23 -0600 Subject: board/cappy2/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92c4f13d61cf1f37c96beef1b3391da048ea16aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728134 Reviewed-by: Jeremy Bettis --- board/cappy2/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cappy2/cbi_ssfc.c b/board/cappy2/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/cappy2/cbi_ssfc.c +++ b/board/cappy2/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 04eaead3f937a8c5219a39bcbc7d70f5ef8e9ead Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:37 -0600 Subject: include/timer.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifea78096fc47bb49e4011046cd91584c16ff8365 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730423 Reviewed-by: Jeremy Bettis --- include/timer.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/include/timer.h b/include/timer.h index 6f9b4ea7b0..42da647dc9 100644 --- a/include/timer.h +++ b/include/timer.h @@ -19,11 +19,11 @@ typedef long clock_t; #include "task_id.h" /* Time units in microseconds */ -#define MSEC 1000 -#define SECOND 1000000 -#define SEC_UL 1000000ul -#define MINUTE 60000000 -#define HOUR 3600000000ull /* Too big to fit in a signed int */ +#define MSEC 1000 +#define SECOND 1000000 +#define SEC_UL 1000000ul +#define MINUTE 60000000 +#define HOUR 3600000000ull /* Too big to fit in a signed int */ /* Microsecond timestamp. */ typedef union { @@ -34,7 +34,6 @@ typedef union { } le /* little endian words */; } timestamp_t; - /** * Initialize the timer module. */ @@ -195,4 +194,4 @@ static inline int time_after(uint32_t a, uint32_t b) extern timestamp_t *get_time_mock; #endif /* CONFIG_ZTEST */ -#endif /* __CROS_EC_TIMER_H */ +#endif /* __CROS_EC_TIMER_H */ -- cgit v1.2.1 From cc5d5bb3504b9df3c3726ec8b238f45e507591c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:11 -0600 Subject: driver/ina2xx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8aba00481f3e07db67d825b1022c9ea2fc65b433 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729980 Reviewed-by: Jeremy Bettis --- driver/ina2xx.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/driver/ina2xx.c b/driver/ina2xx.c index cf4389ba49..6a785d1122 100644 --- a/driver/ina2xx.c +++ b/driver/ina2xx.c @@ -14,7 +14,7 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) /* I2C base address */ #define INA2XX_I2C_ADDR_FLAGS 0x40 @@ -24,8 +24,8 @@ uint16_t ina2xx_read(uint8_t idx, uint8_t reg) int res; int val; - res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, - reg, &val); + res = i2c_read16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg, + &val); if (res) { CPRINTS("INA2XX I2C read failed"); return 0x0bad; @@ -38,8 +38,8 @@ int ina2xx_write(uint8_t idx, uint8_t reg, uint16_t val) int res; uint16_t be_val = (val >> 8) | ((val & 0xff) << 8); - res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, - reg, be_val); + res = i2c_write16(I2C_PORT_MASTER, INA2XX_I2C_ADDR_FLAGS | idx, reg, + be_val); if (res) CPRINTS("INA2XX I2C write failed"); return res; @@ -109,11 +109,10 @@ static void ina2xx_dump(uint8_t idx) ccprintf("Configuration: %04x\n", cfg); ccprintf("Shunt voltage: %04x => %d uV\n", sv, - INA2XX_SHUNT_UV((int)sv)); - ccprintf("Bus voltage : %04x => %d mV\n", bv, - INA2XX_BUS_MV((int)bv)); + INA2XX_SHUNT_UV((int)sv)); + ccprintf("Bus voltage : %04x => %d mV\n", bv, INA2XX_BUS_MV((int)bv)); ccprintf("Power : %04x => %d mW\n", pow, - INA2XX_POW_MW((int)pow)); + INA2XX_POW_MW((int)pow)); ccprintf("Current : %04x => %d mA\n", curr, curr); ccprintf("Calibration : %04x\n", calib); ccprintf("Mask/Enable : %04x\n", mask); -- cgit v1.2.1 From fe95147cea0ae9677808bb640c4be7ed05a9a34d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:29 -0600 Subject: board/kuldax/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0bad666a75f90a3eff5cf1e79c4f235780ab0363 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728601 Reviewed-by: Jeremy Bettis --- board/kuldax/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kuldax/fans.c b/board/kuldax/fans.c index f2a70636d0..62492fe063 100644 --- a/board/kuldax/fans.c +++ b/board/kuldax/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From ec4f00b87f65290c66299910b143615b196e01aa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:02 -0600 Subject: power/mt8186.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic24fcef55f8a7dfcfcab827a0b32a73cae41323c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727064 Reviewed-by: Jeremy Bettis --- power/mt8186.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/power/mt8186.c b/power/mt8186.c index 39fc636127..fcbe94dcee 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -71,10 +71,11 @@ #ifndef CONFIG_ZEPHYR /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_EC_SYSRST_ODL, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_RST"}, - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3"}, - {GPIO_AP_EC_WDTRST_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED"}, - {GPIO_AP_EC_WARM_RST_REQ, POWER_SIGNAL_ACTIVE_HIGH, "AP_WARM_RST_REQ"}, + { GPIO_AP_EC_SYSRST_ODL, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_RST" }, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3" }, + { GPIO_AP_EC_WDTRST_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" }, + { GPIO_AP_EC_WARM_RST_REQ, POWER_SIGNAL_ACTIVE_HIGH, + "AP_WARM_RST_REQ" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); #endif /* CONFIG_ZEPHYR */ @@ -278,7 +279,7 @@ enum power_state power_chipset_init(void) } else if (system_get_reset_flags() & EC_RESET_FLAG_AP_OFF) { exit_hard_off = 0; } else if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) && - gpio_get_level(GPIO_AC_PRESENT)) { + gpio_get_level(GPIO_AC_PRESENT)) { /* * If AC present, assume this is a wake-up by AC insert. * Boot EC only. @@ -473,16 +474,15 @@ static void power_button_changed(void) DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT); #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__override void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__override void power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { CPRINTS("Warning: Detected sleep hang! Waking host up!"); host_set_single_event(EC_HOST_EVENT_HANG_DETECT); } -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { CPRINTS("Handle sleep: %d", state); @@ -503,7 +503,6 @@ __override void power_chipset_handle_host_sleep_event( sleep_set_notify(SLEEP_NOTIFY_RESUME); task_wake(TASK_ID_CHIPSET); sleep_complete_resume(ctx); - } } #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */ -- cgit v1.2.1 From 0efcbdf297211369755a7f1ae543eb3f93100559 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:15 -0600 Subject: board/cappy2/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I28d1591e48b359cf795598e8a4f5c3ed7a32edd4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728131 Reviewed-by: Jeremy Bettis --- board/cappy2/battery.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/cappy2/battery.c b/board/cappy2/battery.c index a0aef7bd4c..8cdff76ad6 100644 --- a/board/cappy2/battery.c +++ b/board/cappy2/battery.c @@ -11,8 +11,8 @@ #include "common.h" #include "util.h" -#define CHARGING_VOLTAGE_MV_SAFE 8400 -#define CHARGING_CURRENT_MA_SAFE 1500 +#define CHARGING_VOLTAGE_MV_SAFE 8400 +#define CHARGING_CURRENT_MA_SAFE 1500 /* * Battery info for lalala battery types. Note that the fields @@ -165,13 +165,13 @@ int charger_profile_override(struct charge_state_data *curr) } enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { return EC_RES_INVALID_PARAM; } -- cgit v1.2.1 From 73c6d90a2788e692f88738868c6756c6d95398e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:42:10 -0600 Subject: zephyr/test/drivers/src/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6b3c914c05d9c592f603f6707736f2b1ffa27d13 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3731008 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/watchdog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/test/drivers/src/watchdog.c b/zephyr/test/drivers/src/watchdog.c index 8b91247f12..bddde3fa50 100644 --- a/zephyr/test/drivers/src/watchdog.c +++ b/zephyr/test/drivers/src/watchdog.c @@ -53,8 +53,8 @@ static void watchdog_before(void *state) /* When shuffling need watchdog initialized and running * for other tests. */ - (void) watchdog_init(); - (void) wdt_setup(wdt, 0); + (void)watchdog_init(); + (void)wdt_setup(wdt, 0); } /** -- cgit v1.2.1 From a396d5a10e03045921ae2e281ea9cbfe38a00633 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:25 -0600 Subject: board/brya/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I76e6abe2a47bcfd1b1d7a3b5f8a8d258053086bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728100 Reviewed-by: Jeremy Bettis --- board/brya/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brya/fw_config.c b/board/brya/fw_config.c index 414908a1f1..49d2dad145 100644 --- a/board/brya/fw_config.c +++ b/board/brya/fw_config.c @@ -10,7 +10,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static union brya_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From a93bfbd3769b98537f804ceedd7e743fa93d3237 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:12 -0600 Subject: board/trogdor/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6f76c9bfda5534b2f7da998ae20cdf76852d8eee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729036 Reviewed-by: Jeremy Bettis --- board/trogdor/usbc_config.c | 38 +++++++++++++++----------------------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/board/trogdor/usbc_config.c b/board/trogdor/usbc_config.c index a25b63bff9..9fe4928a44 100644 --- a/board/trogdor/usbc_config.c +++ b/board/trogdor/usbc_config.c @@ -25,8 +25,8 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { @@ -132,16 +132,12 @@ void ppc_interrupt(enum gpio_signal signal) /* Power Path Controller */ struct ppc_config_t ppc_chips[] = { - { - .i2c_port = I2C_PORT_TCPC0, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, + { .i2c_port = I2C_PORT_TCPC0, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + { .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -234,7 +230,7 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); @@ -280,8 +276,7 @@ void board_overcurrent_event(int port, int is_overcurrented) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -309,7 +304,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -333,23 +327,21 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* * Ignore lower charge ceiling on PD transition if our battery is * critical, as we may brownout. */ - if (supplier == CHARGE_SUPPLIER_PD && - charge_ma < 1500 && + if (supplier == CHARGE_SUPPLIER_PD && charge_ma < 1500 && charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { CPRINTS("Using max ilim %d", max_ma); charge_ma = max_ma; } - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } uint16_t tcpc_get_alert_status(void) -- cgit v1.2.1 From dce7e6016d663dd38d1485bdb7c1118062248801 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:27 -0600 Subject: board/hoho/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib56ebacdd03d032ac88f4008d2b1fe25d1ec5bd1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728306 Reviewed-by: Jeremy Bettis --- board/hoho/usb_pd_policy.c | 52 ++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c index 73f3fca16e..e291fca972 100644 --- a/board/hoho/usb_pd_policy.c +++ b/board/hoho/usb_pd_policy.c @@ -21,8 +21,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Holds valid object position (opos) for entered mode */ static int alt_mode[PD_AMODE_COUNT]; @@ -54,22 +54,18 @@ __override int pd_check_power_swap(int port) return 0; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* Always refuse data swap */ return 0; } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { } /* ----------------- Vendor Defined Messages ------------------ */ @@ -82,8 +78,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 1, /* Vbus power required */ @@ -109,18 +105,16 @@ static int svdm_response_svids(int port, uint32_t *payload) #define OPOS_DP 1 #define OPOS_GFU 1 -const uint32_t vdo_dp_modes[1] = { - VDO_MODE_DP(0, /* UFP pin cfg supported : none */ +const uint32_t vdo_dp_modes[1] = { + VDO_MODE_DP(0, /* UFP pin cfg supported : none */ MODE_DP_PIN_C, /* DFP pin cfg supported */ - 1, /* no usb2.0 signalling in AMode */ - CABLE_PLUG, /* its a plug */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK) /* Its a sink only */ + 1, /* no usb2.0 signalling in AMode */ + CABLE_PLUG, /* its a plug */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK) /* Its a sink only */ }; -const uint32_t vdo_goog_modes[1] = { - VDO_MODE_GOOGLE(MODE_GOOGLE_FU) -}; +const uint32_t vdo_goog_modes[1] = { VDO_MODE_GOOGLE(MODE_GOOGLE_FU) }; static int svdm_response_modes(int port, uint32_t *payload) { @@ -142,13 +136,14 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS_DP) return 0; /* nak */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - (hpd == 1), /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), - 0, /* power low */ + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + (hpd == 1), /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power + low + */ 0x2); return 2; } @@ -227,8 +222,7 @@ const struct svdm_response svdm_rsp = { .exit_mode = &svdm_exit_mode, }; -int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) +int pd_custom_vdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload) { int rsize; -- cgit v1.2.1 From 1e646b474fb1db9e3fedf7071ebdf3726c06daee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:44 -0600 Subject: board/mithrax/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1b8ec20f545d33ca178973c81a2a6f44a5d8d0d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728464 Reviewed-by: Jeremy Bettis --- board/mithrax/led.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/board/mithrax/led.c b/board/mithrax/led.c index 5abaed2a25..b70c707c57 100644 --- a/board/mithrax/led.c +++ b/board/mithrax/led.c @@ -11,26 +11,33 @@ #include "led_onoff_states.h" #include "system.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 94; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From c85e8b499756dfe94e72f9808aead9e89cca61ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:35 -0600 Subject: zephyr/shim/chip/npcx/include/rom_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I738124d7f1429126b455f24df377054ef887ee17 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728330 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/include/rom_chip.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h index aab166e6f1..8def236498 100644 --- a/zephyr/shim/chip/npcx/include/rom_chip.h +++ b/zephyr/shim/chip/npcx/include/rom_chip.h @@ -38,17 +38,17 @@ enum API_RETURN_STATUS_T { }; /* Macro functions of ROM api functions */ -#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40) +#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *)0x40) #define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \ - status) \ - (((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \ - (src_offset, dest_addr, size, sign, exe_addr, status)) + status) \ + (((download_from_flash_ptr)ADDR_DOWNLOAD_FROM_FLASH)( \ + src_offset, dest_addr, size, sign, exe_addr, status)) /* Declarations of ROM api functions */ -typedef void (*download_from_flash_ptr) ( +typedef void (*download_from_flash_ptr)( uint32_t src_offset, /* The offset of the data to be downloaded */ - uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ - uint32_t size, /* Number of bytes to download */ + uint32_t dest_addr, /* The address of the downloaded data in the RAM*/ + uint32_t size, /* Number of bytes to download */ enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */ uint32_t exe_addr, /* jump to this address after download if not zero */ enum API_RETURN_STATUS_T *status /* Status fo download */ -- cgit v1.2.1 From a3486587824e5e65257f8be74ed11e4e52c6adc8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:47 -0600 Subject: chip/stm32/usb_hid_keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic5383832ae9f42d51e04bf773a8d6bfd04d38465 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729555 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_hid_keyboard.c | 370 +++++++++++++++++++++--------------------- 1 file changed, 187 insertions(+), 183 deletions(-) diff --git a/chip/stm32/usb_hid_keyboard.c b/chip/stm32/usb_hid_keyboard.c index 99775fd7fb..8e96b6587a 100644 --- a/chip/stm32/usb_hid_keyboard.c +++ b/chip/stm32/usb_hid_keyboard.c @@ -28,7 +28,7 @@ #include "usb_hid_hw.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) static const int keyboard_debug; @@ -51,7 +51,7 @@ enum hid_protocol { static enum hid_protocol protocol = HID_REPORT_PROTOCOL; #if defined(CONFIG_KEYBOARD_ASSISTANT_KEY) || \ - defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) + defined(CONFIG_KEYBOARD_TABLET_MODE_SWITCH) #define HID_KEYBOARD_EXTRA_FIELD #endif @@ -126,19 +126,20 @@ struct usb_hid_keyboard_output_report { * Assistant key is mapped as 0xf0, but this key code is never actually send. */ const uint8_t keycodes[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, 0x00}, - {0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14}, - {0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08}, - {0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15}, - {0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a}, - {0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c}, - {0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18}, - {0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5}, - {0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13}, - {0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12}, - {0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00}, - {0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52}, - {0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50}, + { 0x00, 0x00, 0xe0, 0xe3, 0xe4, HID_KEYBOARD_ASSISTANT_KEY, 0x00, + 0x00 }, + { 0xe3, 0x29, 0x2b, 0x35, 0x04, 0x1d, 0x1e, 0x14 }, + { 0x3a, 0x3d, 0x3c, 0x3b, 0x07, 0x06, 0x20, 0x08 }, + { 0x05, 0x0a, 0x17, 0x22, 0x09, 0x19, 0x21, 0x15 }, + { 0x43, 0x40, 0x3f, 0x3e, 0x16, 0x1b, 0x1f, 0x1a }, + { 0x87, 0x00, 0x30, 0x00, 0x0e, 0x36, 0x25, 0x0c }, + { 0x11, 0x0b, 0x1c, 0x23, 0x0d, 0x10, 0x24, 0x18 }, + { 0x00, 0x00, 0x64, 0x00, 0x00, 0xe1, 0x00, 0xe5 }, + { 0x2e, 0x34, 0x2F, 0x2d, 0x33, 0x38, 0x27, 0x13 }, + { 0x00, 0x42, 0x41, 0x68, 0x0f, 0x37, 0x26, 0x12 }, + { 0xe6, 0x00, 0x89, 0x00, 0x31, 0x00, 0xe2, 0x00 }, + { 0x00, 0x2a, 0x00, 0x31, 0x28, 0x2c, 0x51, 0x52 }, + { 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x00, 0x4f, 0x50 }, }; /* HID descriptors */ @@ -177,80 +178,84 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { }; #endif -#define KEYBOARD_BASE_DESC \ - 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ - 0x09, 0x06, /* Usage (Keyboard) */ \ - 0xA1, 0x01, /* Collection (Application) */ \ - \ - /* Modifiers */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ - 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x08, /* Report Count (8) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ - \ - /* Normal keys */ \ - 0x95, 0x06, /* Report Count (6) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0xa4, /* Logical Maximum (164) */ \ - 0x05, 0x07, /* Usage Page (Key Codes) */ \ - 0x19, 0x00, /* Usage Minimum (0) */ \ - 0x29, 0xa4, /* Usage Maximum (164) */ \ - 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ - -#define KEYBOARD_TOP_ROW_DESC \ - /* Modifiers */ \ - 0x05, 0x0C, /* Consumer Page */ \ - 0x0A, 0x24, 0x02, /* AC Back (0x224) */ \ - 0x0A, 0x25, 0x02, /* AC Forward (0x225) */ \ - 0x0A, 0x27, 0x02, /* AC Refresh (0x227) */ \ - 0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */ \ - 0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */ \ - 0x09, 0x70, /* Display Brightness Decrement (0x70) */ \ - 0x09, 0x6F, /* Display Brightness Increment (0x6F) */ \ - 0x09, 0xE2, /* Mute (0xE2) */ \ - 0x09, 0xEA, /* Volume Decrement (0xEA) */ \ - 0x09, 0xE9, /* Volume Increment (0xE9) */ \ - 0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage 0x46) */ \ - 0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */ \ - 0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */ \ - 0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/ \ - 0x09, 0xCD, /* Play / Pause (0xCD) */ \ - 0x09, 0xB5, /* Scan Next Track (0xB5) */ \ - 0x09, 0xB6, /* Scan Previous Track (0xB6) */ \ - 0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */ \ - 0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage 0x2F) */ \ - 0x09, 0x32, /* Sleep (0x32) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x14, /* Report Count (20) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ \ - \ - /* 12-bit padding */ \ - 0x95, 0x0C, /* Report Count (12) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ - -#define KEYBOARD_TOP_ROW_FEATURE_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Google) */ \ - 0x09, 0x01, /* Usage (Top Row List) */ \ - 0xa1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x0a, /* Usage Page (Ordinal) */ \ - 0x19, 0x01, /* Usage Minimum (1) */ \ - 0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \ - 0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */ \ - 0x75, 0x20, /* Report Size (32) */ \ - 0xb1, 0x03, /* Feature (Cnst,Var,Abs) */ \ - 0xc0, /* End Collection */ +#define KEYBOARD_BASE_DESC \ + 0x05, 0x01, /* Usage Page (Generic Desktop) */ \ + 0x09, 0x06, /* Usage (Keyboard) */ \ + 0xA1, 0x01, /* Collection (Application) */ \ + \ + /* Modifiers */ \ + 0x05, 0x07, /* Usage Page (Key Codes) */ \ + 0x19, HID_KEYBOARD_MODIFIER_LOW, /* Usage Minimum */ \ + 0x29, HID_KEYBOARD_MODIFIER_HIGH, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x08, /* Report Count (8) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ \ + \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x81, 0x01, /* Input (Constant), ;Reserved byte */ \ + \ + /* Normal keys */ \ + 0x95, 0x06, /* Report Count (6) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0xa4, /* Logical Maximum (164) */ \ + 0x05, 0x07, /* Usage Page (Key Codes) */ \ + 0x19, 0x00, /* Usage Minimum (0) */ \ + 0x29, 0xa4, /* Usage Maximum (164) */ \ + 0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */ + +#define KEYBOARD_TOP_ROW_DESC \ + /* Modifiers */ \ + 0x05, 0x0C, /* Consumer Page */ \ + 0x0A, 0x24, 0x02, /* AC Back (0x224) */ \ + 0x0A, 0x25, 0x02, /* AC Forward (0x225) */ \ + 0x0A, 0x27, 0x02, /* AC Refresh (0x227) */ \ + 0x0A, 0x32, 0x02, /* AC View Toggle (0x232) */ \ + 0x0A, 0x9F, 0x02, /* AC Desktop Show All windows (0x29F) */ \ + 0x09, 0x70, /* Display Brightness Decrement (0x70) */ \ + 0x09, 0x6F, /* Display Brightness Increment (0x6F) */ \ + 0x09, 0xE2, /* Mute (0xE2) */ \ + 0x09, 0xEA, /* Volume Decrement (0xEA) */ \ + 0x09, 0xE9, /* Volume Increment (0xE9) */ \ + 0x0B, 0x46, 0x00, 0x07, 0x00, /* PrintScreen (Page 0x7, Usage \ + 0x46) */ \ + 0x0A, 0xD0, 0x02, /* Privacy Screen Toggle (0x2D0) */ \ + 0x09, 0x7A, /* Keyboard Brightness Decrement (0x7A) */ \ + 0x09, 0x79, /* Keyboard Brightness Increment (0x79)*/ \ + 0x09, 0xCD, /* Play / Pause (0xCD) */ \ + 0x09, 0xB5, /* Scan Next Track (0xB5) */ \ + 0x09, 0xB6, /* Scan Previous Track (0xB6) */ \ + 0x09, 0x7C, /* Keyboard Backlight OOC (0x7C) */ \ + 0x0B, 0x2F, 0x00, 0x0B, 0x00, /* Phone Mute (Page 0xB, Usage \ + 0x2F) */ \ + 0x09, 0x32, /* Sleep (0x32) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x14, /* Report Count (20) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ \ + \ + /* 12-bit padding */ \ + 0x95, 0x0C, /* Report Count (12) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ + +#define KEYBOARD_TOP_ROW_FEATURE_DESC \ + 0x06, 0xd1, 0xff, /* Usage Page (Google) */ \ + 0x09, 0x01, /* Usage (Top Row List) */ \ + 0xa1, 0x02, /* Collection (Logical) */ \ + 0x05, 0x0a, /* Usage Page (Ordinal) */ \ + 0x19, 0x01, /* Usage Minimum (1) */ \ + 0x29, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Usage Maximum */ \ + 0x95, CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS, /* Report Count */ \ + 0x75, 0x20, /* Report Size (32) */ \ + 0xb1, 0x03, /* Feature (Cnst,Var,Abs) */ \ + 0xc0, /* End Collection */ /* * Vendor-defined Usage Page 0xffd1: @@ -259,60 +264,62 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_KEYBOARD, 02) = { */ #ifdef HID_KEYBOARD_EXTRA_FIELD #ifdef CONFIG_KEYBOARD_ASSISTANT_KEY -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x19, 0x18, /* Usage Minimum */ \ - 0x29, 0x18, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ +#define KEYBOARD_ASSISTANT_KEY_DESC \ + 0x19, 0x18, /* Usage Minimum */ \ + 0x29, 0x18, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ #else /* No assistant key: just pad 1 bit. */ -#define KEYBOARD_ASSISTANT_KEY_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ +#define KEYBOARD_ASSISTANT_KEY_DESC \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ #endif /* !CONFIG_KEYBOARD_ASSISTANT_KEY */ #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x19, 0x19, /* Usage Minimum */ \ - 0x29, 0x19, /* Usage Maximum */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */ +#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ + 0x19, 0x19, /* Usage Minimum */ \ + 0x29, 0x19, /* Usage Maximum */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier \ + byte */ #else /* No tablet mode swtch: just pad 1 bit. */ -#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x81, 0x01, /* Input (Constant), ;1-bit padding */ +#define KEYBOARD_TABLET_MODE_SWITCH_DESC \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x81, 0x01, /* Input (Constant), ;1-bit padding */ #endif /* CONFIG_KEYBOARD_TABLET_MODE_SWITCH */ -#define KEYBOARD_VENDOR_DESC \ - 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ - \ - KEYBOARD_ASSISTANT_KEY_DESC \ - KEYBOARD_TABLET_MODE_SWITCH_DESC \ - \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x06, /* Report Size (6) */ \ - 0x81, 0x01, /* Input (Constant), ;6-bit padding */ +#define KEYBOARD_VENDOR_DESC \ + 0x06, 0xd1, 0xff, /* Usage Page (Vendor-defined 0xffd1) */ \ + \ + KEYBOARD_ASSISTANT_KEY_DESC KEYBOARD_TABLET_MODE_SWITCH_DESC \ + \ + 0x95, \ + 0x01, /* Report Count (1) */ \ + 0x75, 0x06, /* Report Size (6) */ \ + 0x81, 0x01, /* Input (Constant), ;6-bit padding */ #endif /* HID_KEYBOARD_EXTRA_FIELD */ -#define KEYBOARD_BACKLIGHT_DESC \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ - 0x09, 0x46, /* Usage (Display Brightness) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x75, 0x08, /* Report Size (8) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x64, /* Logical Maximum (100) */ \ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ - 0xC0, /* End Collection */ +#define KEYBOARD_BACKLIGHT_DESC \ + 0xA1, 0x02, /* Collection (Logical) */ \ + 0x05, 0x14, /* Usage Page (Alphanumeric Display) */ \ + 0x09, 0x46, /* Usage (Display Brightness) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x75, 0x08, /* Report Size (8) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x64, /* Logical Maximum (100) */ \ + 0x91, 0x02, /* Output (Data, Variable, Absolute) */ \ + 0xC0, /* End Collection */ /* * To allow dynamic detection of keyboard backlights, we define two descriptors. @@ -325,17 +332,15 @@ static const uint8_t report_desc[] = { KEYBOARD_BASE_DESC #ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC + KEYBOARD_VENDOR_DESC #endif #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC + KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC #endif - 0xC0 /* End Collection */ + 0xC0 /* End Collection */ }; - #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT /* HID : Report Descriptor with keyboard backlight */ @@ -344,32 +349,29 @@ static const uint8_t report_desc_with_backlight[] = { KEYBOARD_BASE_DESC #ifdef KEYBOARD_VENDOR_DESC - KEYBOARD_VENDOR_DESC + KEYBOARD_VENDOR_DESC #endif #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI - KEYBOARD_TOP_ROW_DESC - KEYBOARD_TOP_ROW_FEATURE_DESC + KEYBOARD_TOP_ROW_DESC KEYBOARD_TOP_ROW_FEATURE_DESC #endif - KEYBOARD_BACKLIGHT_DESC + KEYBOARD_BACKLIGHT_DESC - 0xC0 /* End Collection */ + 0xC0 /* End Collection */ }; #endif /* HID: HID Descriptor */ -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, - hid, hid_desc_kb) = { +const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_KEYBOARD, hid, + hid_desc_kb) = { .bLength = 9, .bDescriptorType = USB_HID_DT_HID, .bcdHID = 0x0100, .bCountryCode = 0x00, /* Hardware target country */ .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} + .desc = { { .bDescriptorType = USB_HID_DT_REPORT, + .wDescriptorLength = sizeof(report_desc) } } }; #define EP_TX_BUF_SIZE DIV_ROUND_UP(HID_KEYBOARD_REPORT_SIZE, 2) @@ -403,10 +405,10 @@ static void write_keyboard_report(void) * send the buffer: enable TX. */ - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report, + sizeof(report)); + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); } /* @@ -422,7 +424,7 @@ static void write_keyboard_report(void) static void hid_keyboard_rx(void) { struct usb_hid_keyboard_output_report report; - memcpy_from_usbram(&report, (void *) usb_sram_addr(hid_ep_rx_buf), + memcpy_from_usbram(&report, (void *)usb_sram_addr(hid_ep_rx_buf), HID_KEYBOARD_OUTPUT_REPORT_SIZE); CPRINTF("Keyboard backlight set to %d%%\n", report.brightness); @@ -439,10 +441,10 @@ static void hid_keyboard_tx(void) { hid_tx(USB_EP_HID_KEYBOARD); if (hid_ep_data_ready) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_tx_buf), - &report, sizeof(report)); - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_tx_buf), &report, + sizeof(report)); + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); hid_ep_data_ready = 0; } @@ -455,16 +457,14 @@ static void hid_keyboard_event(enum usb_ep_event evt) if (evt == USB_EVENT_RESET) { protocol = HID_REPORT_PROTOCOL; - hid_reset(USB_EP_HID_KEYBOARD, - hid_ep_tx_buf, + hid_reset(USB_EP_HID_KEYBOARD, hid_ep_tx_buf, HID_KEYBOARD_REPORT_SIZE, #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT - hid_ep_rx_buf, - HID_KEYBOARD_OUTPUT_REPORT_SIZE + hid_ep_rx_buf, HID_KEYBOARD_OUTPUT_REPORT_SIZE #else NULL, 0 #endif - ); + ); /* * Reload endpoint on reset, to make sure we report accurate @@ -547,8 +547,8 @@ static int hid_keyboard_get_report(uint8_t report_id, uint8_t report_type, #ifdef CONFIG_USB_HID_KEYBOARD_VIVALDI if (report_type == REPORT_TYPE_FEATURE) { *buffer_ptr = (uint8_t *)feature_report; - *buffer_size = (sizeof(uint32_t) * - CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS); + *buffer_size = + (sizeof(uint32_t) * CONFIG_USB_HID_KB_NUM_TOP_ROW_KEYS); return 0; } #endif @@ -572,8 +572,9 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, if (ret >= 0) return ret; - if (ep0_buf_rx[0] == (USB_DIR_OUT | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_SET_PROTOCOL << 8))) { + if (ep0_buf_rx[0] == + (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE | + (USB_HID_REQ_SET_PROTOCOL << 8))) { uint16_t value = ep0_buf_rx[1]; if (value >= HID_PROTOCOL_COUNT) @@ -584,19 +585,21 @@ static int hid_keyboard_iface_request(usb_uint *ep0_buf_rx, /* Reload endpoint with appropriate tx_count. */ btable_ep[USB_EP_HID_KEYBOARD].tx_count = (protocol == HID_BOOT_PROTOCOL) ? - HID_KEYBOARD_BOOT_SIZE : HID_KEYBOARD_REPORT_SIZE; - STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, - EP_TX_VALID, 0); + HID_KEYBOARD_BOOT_SIZE : + HID_KEYBOARD_REPORT_SIZE; + STM32_TOGGLE_EP(USB_EP_HID_KEYBOARD, EP_TX_MASK, EP_TX_VALID, + 0); btable_ep[0].tx_count = 0; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; - } else if (ep0_buf_rx[0] == (USB_DIR_IN | USB_TYPE_CLASS | - USB_RECIP_INTERFACE | (USB_HID_REQ_GET_PROTOCOL << 8))) { + } else if (ep0_buf_rx[0] == + (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE | + (USB_HID_REQ_GET_PROTOCOL << 8))) { uint8_t value = protocol; - memcpy_to_usbram((void *) usb_sram_addr(ep0_buf_tx), - &value, sizeof(value)); + memcpy_to_usbram((void *)usb_sram_addr(ep0_buf_tx), &value, + sizeof(value)); btable_ep[0].tx_count = 1; STM32_TOGGLE_EP(0, EP_TX_RX_MASK, EP_TX_RX_VALID, 0); return 0; @@ -615,7 +618,7 @@ void keyboard_clear_buffer(void) memset(&report, 0, sizeof(report)); #ifdef CONFIG_KEYBOARD_TABLET_MODE_SWITCH if (tablet_get_mode()) - report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - + report.extra |= 0x01 << (HID_KEYBOARD_TABLET_MODE_SWITCH - HID_KEYBOARD_EXTRA_LOW); #endif write_keyboard_report(); @@ -648,7 +651,7 @@ static uint32_t maybe_convert_function_key(int keycode) return SLEEP_KEY_MASK; if (index >= config->num_top_row_keys || - config->action_keys[index] == TK_ABSENT) + config->action_keys[index] == TK_ABSENT) return 0; /* not mapped */ return action_key[config->action_keys[index]].mask; } @@ -666,8 +669,8 @@ static void keyboard_process_queue(void) if (keyboard_debug) CPRINTF("Q%d (s%d ep%d hw%d)\n", queue_count(&key_queue), usb_is_suspended(), hid_ep_data_ready, - (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) - == EP_TX_VALID); + (STM32_USB_EP(USB_EP_HID_KEYBOARD) & EP_TX_MASK) == + EP_TX_VALID); mutex_lock(&key_queue_mutex); if (queue_count(&key_queue) == 0) { @@ -728,7 +731,7 @@ static void keyboard_process_queue(void) valid = 1; #endif } else if (ev.keycode >= HID_KEYBOARD_EXTRA_LOW && - ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { + ev.keycode <= HID_KEYBOARD_EXTRA_HIGH) { #ifdef HID_KEYBOARD_EXTRA_FIELD mask = 0x01 << (ev.keycode - HID_KEYBOARD_EXTRA_LOW); if (ev.pressed) @@ -738,7 +741,7 @@ static void keyboard_process_queue(void) valid = 1; #endif } else if (ev.keycode >= HID_KEYBOARD_MODIFIER_LOW && - ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { + ev.keycode <= HID_KEYBOARD_MODIFIER_HIGH) { mask = 0x01 << (ev.keycode - HID_KEYBOARD_MODIFIER_LOW); if (ev.pressed) report.modifiers |= mask; @@ -805,7 +808,7 @@ static void tablet_mode_change(void) } DECLARE_HOOK(HOOK_TABLET_MODE_CHANGE, tablet_mode_change, HOOK_PRIO_DEFAULT); /* Run after tablet_mode_init. */ -DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_INIT, tablet_mode_change, HOOK_PRIO_DEFAULT + 1); #endif void keyboard_state_changed(int row, int col, int is_pressed) @@ -821,7 +824,8 @@ void keyboard_state_changed(int row, int col, int is_pressed) } void clear_typematic_key(void) -{ } +{ +} #ifdef CONFIG_USB_HID_KEYBOARD_BACKLIGHT void usb_hid_keyboard_init(void) @@ -831,8 +835,8 @@ void usb_hid_keyboard_init(void) hid_config_kb.report_size = sizeof(report_desc_with_backlight); set_descriptor_patch(USB_DESC_KEYBOARD_BACKLIGHT, - &hid_desc_kb.desc[0].wDescriptorLength, - sizeof(report_desc_with_backlight)); + &hid_desc_kb.desc[0].wDescriptorLength, + sizeof(report_desc_with_backlight)); } } /* This needs to happen before usb_init (HOOK_PRIO_DEFAULT) */ -- cgit v1.2.1 From 0ab24b6b5ef90ef08a58215138dcf91f97d60245 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:40 -0600 Subject: board/shotzo/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d58562d08c0fd3f8f92cccf32b4323003e4980a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728951 Reviewed-by: Jeremy Bettis --- board/shotzo/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/shotzo/usb_pd_policy.c b/board/shotzo/usb_pd_policy.c index 1bba648eba..4caa440cc2 100644 --- a/board/shotzo/usb_pd_policy.c +++ b/board/shotzo/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 66275845002e3306bde3e0e21297fb99f909a31b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:18 -0600 Subject: board/ampton/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie8ac27ad6dfafdcd134794074e3789785d5eaafd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727985 Reviewed-by: Jeremy Bettis --- board/ampton/led.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/board/ampton/led.c b/board/ampton/led.c index 40b0acdd9c..31385aacb4 100644 --- a/board/ampton/led.c +++ b/board/ampton/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 0 -#define LED_ON_LVL 1 +#define LED_OFF_LVL 0 +#define LED_ON_LVL 1 __override const int led_charge_lvl_1; @@ -19,19 +19,27 @@ __override const int led_charge_lvl_2 = 94; /* Ampton: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 97c816ab548502f012abe69b6d600f7dac5aa66f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:45 -0600 Subject: chip/npcx/keyboard_raw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0ee1c61ec236f6cf99e534e4cc148c9ab6f6b76c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729401 Reviewed-by: Jeremy Bettis --- chip/npcx/keyboard_raw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c index 5d73765bff..d6270ed5de 100644 --- a/chip/npcx/keyboard_raw.c +++ b/chip/npcx/keyboard_raw.c @@ -20,7 +20,7 @@ void keyboard_raw_init(void) { /* Enable clock for KBS peripheral */ clock_enable_peripheral(CGC_OFFSET_KBS, CGC_KBS_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Ensure top-level interrupt is disabled */ keyboard_raw_enable_interrupt(0); @@ -63,7 +63,7 @@ void keyboard_raw_init(void) NPCX_WKEN(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; /* Select high to low transition (falling edge) */ - NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; + NPCX_WKEDG(MIWU_TABLE_WKKEY, MIWU_GROUP_WKKEY) = 0xFF; /* Enable interrupt of WK KBS */ keyboard_raw_enable_interrupt(1); -- cgit v1.2.1 From 6e22c158e49b47f58535ff1fc200cdc424029393 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:23 -0600 Subject: zephyr/test/drivers/include/test/drivers/tcpci_test_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie18e26b516fedf94909946f16aa18f68c8dfd887 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730970 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/include/test/drivers/tcpci_test_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h b/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h index e39738a9d5..a291e8162c 100644 --- a/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h +++ b/zephyr/test/drivers/include/test/drivers/tcpci_test_common.h @@ -18,7 +18,7 @@ */ void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val, int line); -#define check_tcpci_reg(emul, reg, exp_val) \ +#define check_tcpci_reg(emul, reg, exp_val) \ check_tcpci_reg_f((emul), (reg), (exp_val), __LINE__) /** @@ -32,7 +32,7 @@ void check_tcpci_reg_f(const struct emul *emul, int reg, uint16_t exp_val, */ void check_tcpci_reg_with_mask_f(const struct emul *emul, int reg, uint16_t exp_val, uint16_t mask, int line); -#define check_tcpci_reg_with_mask(emul, reg, exp_val, mask) \ +#define check_tcpci_reg_with_mask(emul, reg, exp_val, mask) \ check_tcpci_reg_with_mask_f((emul), (reg), (exp_val), (mask), __LINE__) /** -- cgit v1.2.1 From 559e975a638c5f501a9dfce15a9f88f3ab4f1c5c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:50 -0600 Subject: board/reef_mchp/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I89b9394ba3e2535a192dc6e7705bf08ca0a004b7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728891 Reviewed-by: Jeremy Bettis --- board/reef_mchp/battery.c | 60 +++++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 28 deletions(-) diff --git a/board/reef_mchp/battery.c b/board/reef_mchp/battery.c index c557533c9d..b4b5bf2dd0 100644 --- a/board/reef_mchp/battery.c +++ b/board/reef_mchp/battery.c @@ -22,7 +22,7 @@ #include "tfdp_chip.h" #define CPUTS(outstr) cputs(CC_CHARGER, outstr) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) enum battery_type { BATTERY_SONY_CORP, @@ -137,7 +137,7 @@ const struct battery_info batt_info_smp_cos4870 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 46, .charging_min_c = 0, @@ -185,7 +185,7 @@ const struct battery_info batt_info_sonycorp = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -242,7 +242,7 @@ const struct battery_info batt_info_panasoic = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -386,7 +386,7 @@ const struct battery_info batt_info_c22n1626 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 45, .charging_min_c = 0, @@ -400,7 +400,7 @@ static int batt_smp_cos4870_init(void) int batt_status; return battery_status(&batt_status) ? 0 : - batt_status & STATUS_INITIALIZED; + batt_status & STATUS_INITIALIZED; } static int batt_sony_corp_init(void) @@ -413,8 +413,9 @@ static int batt_sony_corp_init(void) * : 0b - Allowed to Discharge * : 1b - Not Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); } static int batt_panasonic_init(void) @@ -427,8 +428,9 @@ static int batt_panasonic_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); } static int batt_c22n1626_init(void) @@ -441,8 +443,9 @@ static int batt_c22n1626_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_PACK_STATUS, &batt_status) ? 0 : - !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_PACK_STATUS, &batt_status) ? + 0 : + !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); } static const struct ship_mode_info ship_mode_info_smp_cos4870 = { @@ -515,7 +518,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT); static inline const struct board_batt_params *board_get_batt_params(void) { return &info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type]; + DEFAULT_BATTERY_TYPE : + board_battery_type]; } enum battery_present battery_hw_present(void) @@ -545,8 +549,9 @@ static int board_get_battery_type(void) /* Initialize fast charging parameters */ chg_params = board_get_batt_params()->fast_chg_params; - prev_chg_profile_info = &chg_params->chg_profile_info[ - chg_params->default_temp_range_profile]; + prev_chg_profile_info = + &chg_params->chg_profile_info + [chg_params->default_temp_range_profile]; return board_battery_type; } @@ -561,8 +566,7 @@ static int board_get_battery_type(void) static void board_init_battery_type(void) { if (board_get_battery_type() != BATTERY_TYPE_COUNT) - CPRINTS("found batt:%s", - info[board_battery_type].manuf_name); + CPRINTS("found batt:%s", info[board_battery_type].manuf_name); else CPUTS("battery not found"); } @@ -577,16 +581,16 @@ int board_cut_off_battery(void) { int rv; const struct ship_mode_info *ship_mode_inf = - board_get_batt_params()->ship_mode_inf; + board_get_batt_params()->ship_mode_inf; /* Ship mode command must be sent twice to take effect */ rv = sb_write(ship_mode_inf->ship_mode_reg, - ship_mode_inf->ship_mode_data); + ship_mode_inf->ship_mode_data); if (rv != EC_SUCCESS) return rv; rv = sb_write(ship_mode_inf->ship_mode_reg, - ship_mode_inf->ship_mode_data); + ship_mode_inf->ship_mode_data); return rv; } @@ -599,7 +603,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) /* Do not discharge on AC if the battery is still waking up */ if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - !(curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.status & STATUS_FULLY_CHARGED)) return 0; /* @@ -616,8 +620,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) * and suspend USB charging and DC/DC converter. */ if (!battery_is_cut_off() && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; /* @@ -650,10 +654,10 @@ int charger_profile_override(struct charge_state_data *curr) return 0; } - return charger_profile_override_common(curr, - board_get_batt_params()->fast_chg_params, - &prev_chg_profile_info, - board_get_batt_params()->batt_info->voltage_max); + return charger_profile_override_common( + curr, board_get_batt_params()->fast_chg_params, + &prev_chg_profile_info, + board_get_batt_params()->batt_info->voltage_max); } /* @@ -679,7 +683,7 @@ enum battery_present battery_is_present(void) * Battery status will be inactive until it is initialized. */ if (batt_pres == BP_YES && batt_pres_prev != batt_pres && - !battery_is_cut_off()) { + !battery_is_cut_off()) { /* Re-init board battery if battery presence status changes */ if (board_get_battery_type() == BATTERY_TYPE_COUNT) { if (bd9995x_get_battery_voltage() >= -- cgit v1.2.1 From 1249d9082a9789111f18774da4985c0a9adfbd27 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:49 -0600 Subject: board/rammus/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I377c6b18eedd4af217be5a5914bee9930f13af22 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728856 Reviewed-by: Jeremy Bettis --- board/rammus/usb_pd_policy.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/board/rammus/usb_pd_policy.c b/board/rammus/usb_pd_policy.c index 652c9bb259..754882518f 100644 --- a/board/rammus/usb_pd_policy.c +++ b/board/rammus/usb_pd_policy.c @@ -21,12 +21,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -53,7 +53,8 @@ int pd_set_power_supply_ready(int port) { /* Disable charging */ gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_EC_L : - GPIO_EN_USB_C0_CHARGE_EC_L, 1); + GPIO_EN_USB_C0_CHARGE_EC_L, + 1); /* Ensure we advertise the proper available current quota */ charge_manager_source_port(port, 1); @@ -103,13 +104,11 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_SLP_SUS_L_PMIC); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) return; - gpio_set_level(GPIO_USB2_ID2, - (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_ID2, (data_role == PD_ROLE_UFP) ? 1 : 0); } -- cgit v1.2.1 From feadf69268c15aa542a172b548051c048e56ae0d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:19:44 -0600 Subject: test/cbi_wp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic7ea057726d0fb6931f38bd20d4be263da7040d4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730492 Reviewed-by: Jeremy Bettis --- test/cbi_wp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/test/cbi_wp.c b/test/cbi_wp.c index 7bdfa4b0c8..3082b3bf54 100644 --- a/test/cbi_wp.c +++ b/test/cbi_wp.c @@ -49,8 +49,7 @@ DECLARE_EC_TEST(test_wp) TEST_SUITE(test_suite_cbi_wp) { ztest_test_suite(test_cbi_wp, - ztest_unit_test_setup_teardown(test_wp, - test_setup, + ztest_unit_test_setup_teardown(test_wp, test_setup, test_teardown)); ztest_run_test_suite(test_cbi_wp); } -- cgit v1.2.1 From 57dac51a688cefdc3582593b5bd8113ef4b9b69a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:15 -0600 Subject: chip/it83xx/i2c_peripheral.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4b78bac0ab7ca7aa09df59717830e7fab73aef28 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729200 Reviewed-by: Jeremy Bettis --- chip/it83xx/i2c_peripheral.c | 76 ++++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 35 deletions(-) diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c index 1590c39bca..c5455327a0 100644 --- a/chip/it83xx/i2c_peripheral.c +++ b/chip/it83xx/i2c_peripheral.c @@ -16,7 +16,7 @@ #include "task.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) /* The size must be a power of 2 */ #define I2C_MAX_BUFFER_SIZE 0x100 @@ -27,10 +27,10 @@ /* Store controller to peripheral data of channel D, E, F by DMA */ static uint8_t in_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE] - __attribute__((section(".h2ram.pool.i2cslv"))); + __attribute__((section(".h2ram.pool.i2cslv"))); /* Store peripheral to controller data of channel D, E, F by DMA */ static uint8_t out_data[I2C_ENHANCED_PORT_COUNT][I2C_MAX_BUFFER_SIZE] - __attribute__((section(".h2ram.pool.i2cslv"))); + __attribute__((section(".h2ram.pool.i2cslv"))); /* Store read and write data of channel A by FIFO mode */ static uint8_t pbuffer[I2C_MAX_BUFFER_SIZE]; @@ -48,7 +48,7 @@ void buffer_index_reset(void) /* Data structure to define I2C peripheral control configuration. */ struct i2c_periph_ctrl_t { - int irq; /* peripheral irq */ + int irq; /* peripheral irq */ /* offset from base 0x00F03500 register; -1 means unused. */ int offset; enum clock_gate_offsets clock_gate; @@ -57,14 +57,22 @@ struct i2c_periph_ctrl_t { /* I2C peripheral control */ const struct i2c_periph_ctrl_t i2c_periph_ctrl[] = { - [IT83XX_I2C_CH_A] = {.irq = IT83XX_IRQ_SMB_A, .offset = -1, - .clock_gate = CGC_OFFSET_SMBA, .dma_index = -1}, - [IT83XX_I2C_CH_D] = {.irq = IT83XX_IRQ_SMB_D, .offset = 0x180, - .clock_gate = CGC_OFFSET_SMBD, .dma_index = 0}, - [IT83XX_I2C_CH_E] = {.irq = IT83XX_IRQ_SMB_E, .offset = 0x0, - .clock_gate = CGC_OFFSET_SMBE, .dma_index = 1}, - [IT83XX_I2C_CH_F] = {.irq = IT83XX_IRQ_SMB_F, .offset = 0x80, - .clock_gate = CGC_OFFSET_SMBF, .dma_index = 2}, + [IT83XX_I2C_CH_A] = { .irq = IT83XX_IRQ_SMB_A, + .offset = -1, + .clock_gate = CGC_OFFSET_SMBA, + .dma_index = -1 }, + [IT83XX_I2C_CH_D] = { .irq = IT83XX_IRQ_SMB_D, + .offset = 0x180, + .clock_gate = CGC_OFFSET_SMBD, + .dma_index = 0 }, + [IT83XX_I2C_CH_E] = { .irq = IT83XX_IRQ_SMB_E, + .offset = 0x0, + .clock_gate = CGC_OFFSET_SMBE, + .dma_index = 1 }, + [IT83XX_I2C_CH_F] = { .irq = IT83XX_IRQ_SMB_F, + .offset = 0x80, + .clock_gate = CGC_OFFSET_SMBF, + .dma_index = 2 }, }; void i2c_peripheral_read_write_data(int port) @@ -87,7 +95,8 @@ void i2c_peripheral_read_write_data(int port) for (i = 0; i < I2C_READ_MAXFIFO_DATA; i++) /* Return buffer data to controller */ IT83XX_SMB_SLDA = - pbuffer[(i + r_index) & I2C_SIZE_MASK]; + pbuffer[(i + r_index) & + I2C_SIZE_MASK]; /* Index to next 16 bytes of read buffer */ r_index += I2C_READ_MAXFIFO_DATA; @@ -97,9 +106,11 @@ void i2c_peripheral_read_write_data(int port) /* FIFO Full */ if (IT83XX_SMB_SFFSTA & IT83XX_SMB_SFFFULL) { for (i = 0; i < count; i++) - /* Get data from controller to buffer */ + /* Get data from controller to + * buffer */ pbuffer[(w_index + i) & - I2C_SIZE_MASK] = IT83XX_SMB_SLDA; + I2C_SIZE_MASK] = + IT83XX_SMB_SLDA; } /* Index to next byte of write buffer */ @@ -120,8 +131,8 @@ void i2c_peripheral_read_write_data(int port) else { for (i = 0; i < count; i++) /* Get data from controller to buffer */ - pbuffer[(i + w_index) & - I2C_SIZE_MASK] = IT83XX_SMB_SLDA; + pbuffer[(i + w_index) & I2C_SIZE_MASK] = + IT83XX_SMB_SLDA; } /* Reset read and write buffer index */ @@ -147,16 +158,15 @@ void i2c_peripheral_read_write_data(int port) /* Interrupt pending */ if (IT83XX_I2C_STR(ch) & IT83XX_I2C_INTPEND) { - periph_status = IT83XX_I2C_IRQ_ST(ch); /* Controller to read data */ if (periph_status & IT83XX_I2C_IDR_CLR) { - /* - * TODO(b:129360157): Return buffer data by - * "out_data" array. - * Ex: Write data to buffer from 0x00 to 0xFF - */ + /* + * TODO(b:129360157): Return buffer data by + * "out_data" array. + * Ex: Write data to buffer from 0x00 to 0xFF + */ for (i = 0; i < I2C_MAX_BUFFER_SIZE; i++) out_data[idx][i] = i; } @@ -168,10 +178,10 @@ void i2c_peripheral_read_write_data(int port) /* Peripheral finish */ if (periph_status & IT83XX_I2C_P_CLR) { if (wr_done[idx]) { - /* - * TODO(b:129360157): Handle controller write - * data by "in_data" array. - */ + /* + * TODO(b:129360157): Handle controller + * write data by "in_data" array. + */ CPRINTS("WData: %ph", HEX_BUF(in_data[idx], I2C_MAX_BUFFER_SIZE)); @@ -199,12 +209,10 @@ void i2c_periph_interrupt(int port) void i2c_peripheral_enable(int port, uint8_t periph_addr) { - clock_enable_peripheral(i2c_periph_ctrl[port].clock_gate, 0, 0); /* I2C peripheral channel A FIFO mode */ if (port < I2C_STANDARD_PORT_COUNT) { - /* This field defines the SMCLK0/1/2 clock/data low timeout. */ IT83XX_SMB_25MS = I2C_CLK_LOW_TIMEOUT; @@ -266,8 +274,8 @@ void i2c_peripheral_enable(int port, uint8_t periph_addr) IT83XX_I2C_IDR(ch) = periph_addr << 1; /* I2C interrupt enable and set acknowledge */ - IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT | - IT83XX_I2C_INTEN | IT83XX_I2C_ACK; + IT83XX_I2C_CTR(ch) = IT83XX_I2C_HALT | IT83XX_I2C_INTEN | + IT83XX_I2C_ACK; /* * bit3 : Peripheral ID write flag @@ -313,21 +321,19 @@ void i2c_peripheral_enable(int port, uint8_t periph_addr) } /* I2C module enable and command queue mode */ - IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | - IT83XX_I2C_MDL_EN; + IT83XX_I2C_CTR1(ch) = IT83XX_I2C_COMQ_EN | IT83XX_I2C_MDL_EN; } } static void i2c_peripheral_init(void) { - int i, p; + int i, p; /* DLM 52k~56k size select enable */ IT83XX_GCTRL_MCCR2 |= (1 << 4); /* Enable I2C Peripheral function */ for (i = 0; i < i2c_periphs_used; i++) { - /* I2c peripheral port mapping. */ p = i2c_periph_ports[i].port; -- cgit v1.2.1 From 99b5c43dff28d85764ee2454915e4fe1ce5465fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:51 -0600 Subject: board/kukui_scp/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba38542e6a3acbf1fe8324df17014aa5eef45d66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728593 Reviewed-by: Jeremy Bettis --- board/kukui_scp/board.h | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h index 0c42c0cf2a..bc4b5a0dda 100644 --- a/board/kukui_scp/board.h +++ b/board/kukui_scp/board.h @@ -16,8 +16,8 @@ #define CONFIG_FLASH_SIZE_BYTES 0x58000 /* Image file size: 256KB */ #endif -#undef CONFIG_LID_SWITCH -#undef CONFIG_FW_INCLUDE_RO +#undef CONFIG_LID_SWITCH +#undef CONFIG_FW_INCLUDE_RO #define CONFIG_MKBP_EVENT /* Sent MKBP event via IPI. */ #define CONFIG_MKBP_USE_CUSTOM @@ -68,8 +68,8 @@ /* IPI configs */ #define CONFIG_IPC_SHARED_OBJ_BUF_SIZE 288 -#define CONFIG_IPC_SHARED_OBJ_ADDR \ - (ICACHE_BASE - \ +#define CONFIG_IPC_SHARED_OBJ_ADDR \ + (ICACHE_BASE - \ (CONFIG_IPC_SHARED_OBJ_BUF_SIZE + 2 * 4 /* int32_t */) * 2) #define CONFIG_IPI #define CONFIG_RPMSG_NAME_SERVICE @@ -95,11 +95,10 @@ #define IPI_NS_SERVICE 0xFF - #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 8192 -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE /* * CONFIG_UART_CONSOLE * 0 - SCP UART0 @@ -112,8 +111,8 @@ #define CONFIG_UART_CONSOLE 0 #endif /* We let AP setup the correct pinmux. */ -#undef UART0_PINMUX_11_12 -#undef UART0_PINMUX_110_112 +#undef UART0_PINMUX_11_12 +#undef UART0_PINMUX_110_112 /* Track AP power state */ #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -- cgit v1.2.1 From d0a67785e0c683ee5649db6dcdb30a9f288c1bd9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:18 -0600 Subject: chip/stm32/usb_dwc_console.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic971717bec4555c6e37ed2994763a5c8b4a7da8a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729571 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc_console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chip/stm32/usb_dwc_console.h b/chip/stm32/usb_dwc_console.h index ab2206d359..f8a25d3894 100644 --- a/chip/stm32/usb_dwc_console.h +++ b/chip/stm32/usb_dwc_console.h @@ -10,4 +10,4 @@ extern struct dwc_usb_ep ep_console_ctl; -#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ +#endif /* __CHIP_STM32_USB_DWC_CONSOLE_H */ -- cgit v1.2.1 From 433eb8f0bb702260a5007f14f186335db7ff5581 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:53 -0600 Subject: test/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iad0e938e0ecb0160a012f5e04615a58f9f3450cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730539 Reviewed-by: Jeremy Bettis --- test/thermal.c | 68 +++++++++++++++++++++------------------------------------- 1 file changed, 25 insertions(+), 43 deletions(-) diff --git a/test/thermal.c b/test/thermal.c index 1161ecbf1b..69b19b7986 100644 --- a/test/thermal.c +++ b/test/thermal.c @@ -18,7 +18,6 @@ #include "timer.h" #include "util.h" - /*****************************************************************************/ /* Exported data */ @@ -95,7 +94,7 @@ static void reset_mocks(void) memset(thermal_params, 0, sizeof(thermal_params)); /* All sensors report error anyway */ - set_temps(-1, -1 , -1, -1); + set_temps(-1, -1, -1, -1); /* Reset expectations */ host_throttled = 0; @@ -105,7 +104,6 @@ static void reset_mocks(void) no_temps_read = 0; } - /*****************************************************************************/ /* Tests */ @@ -147,7 +145,6 @@ static int test_sensors_can_be_read(void) return EC_SUCCESS; } - static int test_one_fan(void) { reset_mocks(); @@ -448,42 +445,41 @@ static int test_several_limits(void) TEST_ASSERT(cpu_throttled == 0); TEST_ASSERT(cpu_shutdown == 0); - set_temps(500, 50, -1, 10); /* 1=low, 2=X, 3=low */ + set_temps(500, 50, -1, 10); /* 1=low, 2=X, 3=low */ sleep(2); TEST_ASSERT(host_throttled == 0); TEST_ASSERT(cpu_throttled == 0); TEST_ASSERT(cpu_shutdown == 0); - set_temps(500, 170, 210, 10); /* 1=warn, 2=high, 3=low */ + set_temps(500, 170, 210, 10); /* 1=warn, 2=high, 3=low */ sleep(2); TEST_ASSERT(host_throttled == 1); TEST_ASSERT(cpu_throttled == 1); TEST_ASSERT(cpu_shutdown == 0); - set_temps(500, 100, 50, 40); /* 1=low, 2=low, 3=high */ + set_temps(500, 100, 50, 40); /* 1=low, 2=low, 3=high */ sleep(2); TEST_ASSERT(host_throttled == 1); TEST_ASSERT(cpu_throttled == 1); TEST_ASSERT(cpu_shutdown == 0); - set_temps(500, 100, 50, 41); /* 1=low, 2=low, 3=shutdown */ + set_temps(500, 100, 50, 41); /* 1=low, 2=low, 3=shutdown */ sleep(2); TEST_ASSERT(host_throttled == 1); TEST_ASSERT(cpu_throttled == 1); TEST_ASSERT(cpu_shutdown == 1); - all_temps(0); /* reset from shutdown */ + all_temps(0); /* reset from shutdown */ sleep(2); TEST_ASSERT(host_throttled == 0); TEST_ASSERT(cpu_throttled == 0); - return EC_SUCCESS; } /* Tests for ncp15wb thermistor ADC-to-temp calculation */ -#define LOW_ADC_TEST_VALUE 887 /* 0 C */ -#define HIGH_ADC_TEST_VALUE 100 /* > 100C */ +#define LOW_ADC_TEST_VALUE 887 /* 0 C */ +#define HIGH_ADC_TEST_VALUE 100 /* > 100C */ static int test_ncp15wb_adc_to_temp(void) { @@ -496,18 +492,11 @@ static int test_ncp15wb_adc_to_temp(void) int adc; int temp; } adc_temp_datapoints[] = { - { 615, 30 }, - { 561, 35 }, - { 508, 40 }, - { 407, 50 }, - { 315, 60 }, - { 243, 70 }, - { 186, 80 }, - { 140, 90 }, - { 107, 100 }, + { 615, 30 }, { 561, 35 }, { 508, 40 }, + { 407, 50 }, { 315, 60 }, { 243, 70 }, + { 186, 80 }, { 140, 90 }, { 107, 100 }, }; - /* * Verify that calculated temp is decreasing for entire ADC range, * and that a tick down in ADC value results in no more than 1C @@ -518,8 +507,7 @@ static int test_ncp15wb_adc_to_temp(void) while (--i > HIGH_ADC_TEST_VALUE) { new_temp = ncp15wb_calculate_temp(i); - TEST_ASSERT(new_temp == temp || - new_temp == temp + 1); + TEST_ASSERT(new_temp == temp || new_temp == temp + 1); temp = new_temp; } @@ -539,9 +527,7 @@ static int test_thermistor_linear_interpolate(void) int i, t, t0; uint16_t mv; /* Simple test case - a straight line. */ - struct thermistor_data_pair line_data[] = { - { 100, 0 }, { 0, 100 } - }; + struct thermistor_data_pair line_data[] = { { 100, 0 }, { 0, 100 } }; struct thermistor_info line_info = { .scaling_factor = 1, .num_pairs = ARRAY_SIZE(line_data), @@ -576,19 +562,17 @@ static int test_thermistor_linear_interpolate(void) * of derived values but at temp - 1, temp + 1, and in between. */ struct { - uint16_t mv; /* not scaled */ + uint16_t mv; /* not scaled */ int temp; } cmp[] = { - { 3030, 1 }, { 2341, 5 }, { 2195, 9 }, - { 2120, 11 }, { 1966, 15 }, { 1811, 19 }, - { 1733, 21 }, { 1581, 25 }, { 1434, 29 }, - { 1363, 31 }, { 1227, 35 }, { 1100, 39 }, - { 1040, 41 }, { 929, 45 }, { 827, 49 }, - { 780, 51 }, { 693, 55 }, { 615, 59 }, - { 579, 61 }, { 514, 65 }, { 460, 69 }, - { 430, 71 }, { 382, 75 }, { 339, 79 }, - { 320, 81 }, { 285, 85 }, { 254, 89 }, - { 240, 91 }, { 214, 95 }, { 192, 99 }, + { 3030, 1 }, { 2341, 5 }, { 2195, 9 }, { 2120, 11 }, + { 1966, 15 }, { 1811, 19 }, { 1733, 21 }, { 1581, 25 }, + { 1434, 29 }, { 1363, 31 }, { 1227, 35 }, { 1100, 39 }, + { 1040, 41 }, { 929, 45 }, { 827, 49 }, { 780, 51 }, + { 693, 55 }, { 615, 59 }, { 579, 61 }, { 514, 65 }, + { 460, 69 }, { 430, 71 }, { 382, 75 }, { 339, 79 }, + { 320, 81 }, { 285, 85 }, { 254, 89 }, { 240, 91 }, + { 214, 95 }, { 192, 99 }, }; /* Return lowest temperature in data set if voltage is too high. */ @@ -602,9 +586,8 @@ static int test_thermistor_linear_interpolate(void) TEST_ASSERT(t == data[info.num_pairs - 1].temp); /* Simple line test */ - for (mv = line_data[0].mv; - mv > line_data[line_info.num_pairs - 1].mv; - mv--) { + for (mv = line_data[0].mv; mv > line_data[line_info.num_pairs - 1].mv; + mv--) { t = thermistor_linear_interpolate(mv, &line_info); TEST_ASSERT(mv == line_data[line_info.num_pairs - 1].temp - t); } @@ -614,8 +597,7 @@ static int test_thermistor_linear_interpolate(void) * decreases with increase in voltage (0-5V, 10mV steps). */ for (mv = data[0].mv * info.scaling_factor, t0 = data[0].temp; - mv > data[info.num_pairs - 1].mv; - mv -= 10) { + mv > data[info.num_pairs - 1].mv; mv -= 10) { int t1 = thermistor_linear_interpolate(mv, &info); TEST_ASSERT(t1 >= t0); -- cgit v1.2.1 From 6587a36c42251a6db20ad4d14f1b4286cb4008ff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:37 -0600 Subject: include/usb_pd_tcpc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2162dfc3336de626914be99b85c28637cf2a8e43 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730443 Reviewed-by: Jeremy Bettis --- include/usb_pd_tcpc.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/usb_pd_tcpc.h b/include/usb_pd_tcpc.h index 0a10f97e0e..fa1e39b84c 100644 --- a/include/usb_pd_tcpc.h +++ b/include/usb_pd_tcpc.h @@ -18,11 +18,11 @@ #ifdef TCPCI_I2C_PERIPHERAL /* Convert TCPC address to type-C port number */ -#define TCPC_ADDR_TO_PORT(addr) ((addr) \ - - I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) +#define TCPC_ADDR_TO_PORT(addr) \ + ((addr)-I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) /* Check if the i2c address belongs to TCPC */ -#define ADDR_IS_TCPC(addr) (((addr) & 0x7E) \ - == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) +#define ADDR_IS_TCPC(addr) \ + (((addr)&0x7E) == I2C_STRIP_FLAGS(CONFIG_TCPC_I2C_BASE_ADDR_FLAGS)) #endif /** @@ -52,7 +52,7 @@ int tcpc_alert_status(int port, int *alert); int tcpc_alert_status_clear(int port, uint16_t mask); int tcpc_alert_mask_set(int port, uint16_t mask); int tcpc_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2); + enum tcpc_cc_voltage_status *cc2); int tcpc_select_rp_value(int port, int rp); int tcpc_set_cc(int port, int pull); int tcpc_set_polarity(int port, int polarity); -- cgit v1.2.1 From 862eae94c19760820f710195197dfe827df5fac6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:19 -0600 Subject: include/aes.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie97e291af4590c6bc4b67eb722547e53e84be8bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730202 Reviewed-by: Jeremy Bettis --- include/aes.h | 130 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 1 deletion(-) mode change 120000 => 100644 include/aes.h diff --git a/include/aes.h b/include/aes.h deleted file mode 120000 index b30c680a6a..0000000000 --- a/include/aes.h +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/include/aes.h \ No newline at end of file diff --git a/include/aes.h b/include/aes.h new file mode 100644 index 0000000000..67a9002f4f --- /dev/null +++ b/include/aes.h @@ -0,0 +1,129 @@ +/* ==================================================================== + * Copyright (c) 2002-2006 The OpenSSL Project. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. All advertising materials mentioning features or use of this + * software must display the following acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" + * + * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For written permission, please contact + * openssl-core@openssl.org. + * + * 5. Products derived from this software may not be called "OpenSSL" + * nor may "OpenSSL" appear in their names without prior written + * permission of the OpenSSL Project. + * + * 6. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by the OpenSSL Project + * for use in the OpenSSL Toolkit (http://www.openssl.org/)" + * + * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY + * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR + * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * ==================================================================== */ + +#ifndef __CROS_EC_AES_H +#define __CROS_EC_AES_H + +#include + +#define AES_ENCRYPT 1 +#define AES_DECRYPT 0 + +/* AES_MAXNR is the maximum number of AES rounds. */ +#define AES_MAXNR 14 + +#define AES_BLOCK_SIZE 16 + +/* + * aes_key_st should be an opaque type, but EVP requires that the size be + * known. + */ +struct aes_key_st { + uint32_t rd_key[4 * (AES_MAXNR + 1)]; + unsigned rounds; +}; +typedef struct aes_key_st AES_KEY; + +/* + * These functions are provided by either common/aes.c, or assembly code, + * and should not be called directly. + */ +void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key); +void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key); +int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits, + AES_KEY *aeskey); +int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits, + AES_KEY *aeskey); + +/** + * AES_set_encrypt_key configures |aeskey| to encrypt with the |bits|-bit key, + * |key|. + * + * WARNING: unlike other OpenSSL functions, this returns zero on success and a + * negative number on error. + */ +static inline int AES_set_encrypt_key(const uint8_t *key, unsigned int bits, + AES_KEY *aeskey) +{ + return aes_nohw_set_encrypt_key(key, bits, aeskey); +} + +/** + * AES_set_decrypt_key configures |aeskey| to decrypt with the |bits|-bit key, + * |key|. + * + * WARNING: unlike other OpenSSL functions, this returns zero on success and a + * negative number on error. + */ +static inline int AES_set_decrypt_key(const uint8_t *key, unsigned int bits, + AES_KEY *aeskey) +{ + return aes_nohw_set_decrypt_key(key, bits, aeskey); +} + +/** + * AES_encrypt encrypts a single block from |in| to |out| with |key|. The |in| + * and |out| pointers may overlap. + */ +static inline void AES_encrypt(const uint8_t *in, uint8_t *out, + const AES_KEY *key) +{ + aes_nohw_encrypt(in, out, key); +} + +/** + * AES_decrypt decrypts a single block from |in| to |out| with |key|. The |in| + * and |out| pointers may overlap. + */ +static inline void AES_decrypt(const uint8_t *in, uint8_t *out, + const AES_KEY *key) +{ + aes_nohw_decrypt(in, out, key); +} + +#endif /* __CROS_EC_AES_H */ -- cgit v1.2.1 From 9e95f6bba2d57cdb84aa9bad2029a3713bfaa91a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:02 -0600 Subject: chip/it83xx/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d7e89a4e103d3047e293c454181f1db6553aba0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729197 Reviewed-by: Jeremy Bettis --- chip/it83xx/flash.c | 131 +++++++++++++++++++++++++--------------------------- 1 file changed, 63 insertions(+), 68 deletions(-) diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index ed02aa882f..5396a29e58 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -17,45 +17,45 @@ #include "shared_mem.h" #include "uart.h" -#define FLASH_DMA_START ((uint32_t) &__flash_dma_start) +#define FLASH_DMA_START ((uint32_t)&__flash_dma_start) #define FLASH_DMA_CODE __attribute__((section(".flash_direct_map"))) -#define FLASH_ILM0_ADDR ((uint32_t) &__ilm0_ram_code) +#define FLASH_ILM0_ADDR ((uint32_t)&__ilm0_ram_code) /* erase size of sector is 1KB or 4KB */ #define FLASH_SECTOR_ERASE_SIZE CONFIG_FLASH_ERASE_SIZE #ifdef IT83XX_CHIP_FLASH_IS_KGD /* page program command */ -#define FLASH_CMD_PAGE_WRITE 0x2 +#define FLASH_CMD_PAGE_WRITE 0x2 /* ector erase command (erase size is 4KB) */ -#define FLASH_CMD_SECTOR_ERASE 0x20 +#define FLASH_CMD_SECTOR_ERASE 0x20 /* command for flash write */ -#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE +#define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE #else /* Auto address increment programming */ -#define FLASH_CMD_AAI_WORD 0xAD +#define FLASH_CMD_AAI_WORD 0xAD /* Flash sector erase (1K bytes) command */ -#define FLASH_CMD_SECTOR_ERASE 0xD7 +#define FLASH_CMD_SECTOR_ERASE 0xD7 /* command for flash write */ -#define FLASH_CMD_WRITE FLASH_CMD_AAI_WORD +#define FLASH_CMD_WRITE FLASH_CMD_AAI_WORD #endif /* Write status register */ -#define FLASH_CMD_WRSR 0x01 +#define FLASH_CMD_WRSR 0x01 /* Write disable */ -#define FLASH_CMD_WRDI 0x04 +#define FLASH_CMD_WRDI 0x04 /* Write enable */ -#define FLASH_CMD_WREN 0x06 +#define FLASH_CMD_WREN 0x06 /* Read status register */ -#define FLASH_CMD_RS 0x05 +#define FLASH_CMD_RS 0x05 #if (CONFIG_FLASH_SIZE_BYTES == 0x80000) && defined(CHIP_CORE_NDS32) -#define FLASH_TEXT_START ((uint32_t) &__flash_text_start) +#define FLASH_TEXT_START ((uint32_t)&__flash_text_start) /* Apply workaround of the issue (b:111808417) */ #define IMMU_CACHE_TAG_INVALID /* The default tag index of immu. */ #define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000 /* immu cache size is 8K bytes. */ -#define IMMU_SIZE 0x2000 +#define IMMU_SIZE 0x2000 #endif static int stuck_locked; @@ -88,18 +88,18 @@ enum flash_status_mask { }; enum dlm_address_view { - SCAR0_ILM0_DLM13 = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */ - SCAR1_ILM1_DLM11 = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */ - SCAR2_ILM2_DLM14 = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */ - SCAR3_ILM3_DLM6 = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */ - SCAR4_ILM4_DLM7 = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */ - SCAR5_ILM5_DLM8 = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */ - SCAR6_ILM6_DLM9 = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */ - SCAR7_ILM7_DLM10 = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */ - SCAR8_ILM8_DLM4 = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */ - SCAR9_ILM9_DLM5 = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */ - SCAR10_ILM10_DLM2 = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */ - SCAR11_ILM11_DLM3 = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */ + SCAR0_ILM0_DLM13 = 0x8D000, /* DLM ~ 0x8DFFF H2RAM map LPC I/O */ + SCAR1_ILM1_DLM11 = 0x8B000, /* DLM ~ 0x8BFFF ram 44K ~ 48K */ + SCAR2_ILM2_DLM14 = 0x8E000, /* DLM ~ 0x8EFFF RO/RW flash code DMA */ + SCAR3_ILM3_DLM6 = 0x86000, /* DLM ~ 0x86FFF ram 24K ~ 28K */ + SCAR4_ILM4_DLM7 = 0x87000, /* DLM ~ 0x87FFF ram 28K ~ 32K */ + SCAR5_ILM5_DLM8 = 0x88000, /* DLM ~ 0x88FFF ram 32K ~ 36K */ + SCAR6_ILM6_DLM9 = 0x89000, /* DLM ~ 0x89FFF ram 36K ~ 40K */ + SCAR7_ILM7_DLM10 = 0x8A000, /* DLM ~ 0x8AFFF ram 40K ~ 44K */ + SCAR8_ILM8_DLM4 = 0x84000, /* DLM ~ 0x84FFF ram 16K ~ 20K */ + SCAR9_ILM9_DLM5 = 0x85000, /* DLM ~ 0x85FFF ram 20K ~ 24K */ + SCAR10_ILM10_DLM2 = 0x82000, /* DLM ~ 0x82FFF ram 8K ~ 12K */ + SCAR11_ILM11_DLM3 = 0x83000, /* DLM ~ 0x83FFF ram 12K ~ 16K */ SCAR12_ILM12_DLM12 = 0x8C000, /* DLM ~ 0x8CFFF immu cache */ }; @@ -177,8 +177,8 @@ void FLASH_DMA_CODE dma_flash_write_dat(uint8_t wdata) IT83XX_SMFI_ECINDDR = wdata; } -void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, - int rlen, uint8_t *rbuf, int cmd_end) +void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, int rlen, + uint8_t *rbuf, int cmd_end) { int i; @@ -197,10 +197,10 @@ void FLASH_DMA_CODE dma_flash_transaction(int wlen, uint8_t *wbuf, } void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask, - enum flash_status_mask target) + enum flash_status_mask target) { uint8_t status[1]; - uint8_t cmd_rs[] = {FLASH_CMD_RS}; + uint8_t cmd_rs[] = { FLASH_CMD_RS }; /* * We prefer no timeout here. We can always get the status @@ -220,7 +220,7 @@ void FLASH_DMA_CODE dma_flash_cmd_read_status(enum flash_status_mask mask, void FLASH_DMA_CODE dma_flash_cmd_write_enable(void) { - uint8_t cmd_we[] = {FLASH_CMD_WREN}; + uint8_t cmd_we[] = { FLASH_CMD_WREN }; /* enter EC-indirect follow mode */ dma_flash_follow_mode(); @@ -234,7 +234,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write_enable(void) void FLASH_DMA_CODE dma_flash_cmd_write_disable(void) { - uint8_t cmd_wd[] = {FLASH_CMD_WRDI}; + uint8_t cmd_wd[] = { FLASH_CMD_WRDI }; /* enter EC-indirect follow mode */ dma_flash_follow_mode(); @@ -248,8 +248,8 @@ void FLASH_DMA_CODE dma_flash_cmd_write_disable(void) void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd) { - uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF), - ((addr >> 8) & 0xFF), (addr & 0xFF)}; + uint8_t cmd_erase[] = { cmd, ((addr >> 16) & 0xFF), + ((addr >> 8) & 0xFF), (addr & 0xFF) }; /* enter EC-indirect follow mode */ dma_flash_follow_mode(); @@ -264,8 +264,8 @@ void FLASH_DMA_CODE dma_flash_cmd_erase(int addr, int cmd) void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf) { int i; - uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF), - ((addr >> 8) & 0xFF), (addr & 0xFF)}; + uint8_t flash_write[] = { FLASH_CMD_WRITE, ((addr >> 16) & 0xFF), + ((addr >> 8) & 0xFF), (addr & 0xFF) }; /* enter EC-indirect follow mode */ dma_flash_follow_mode(); @@ -281,12 +281,12 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf) * chunk worth of data. */ if (!(++addr % CONFIG_FLASH_WRITE_IDEAL_SIZE)) { - uint8_t w_en[] = {FLASH_CMD_WREN}; + uint8_t w_en[] = { FLASH_CMD_WREN }; dma_flash_fsce_high(); /* make sure busy bit cleared. */ dma_flash_cmd_read_status(FLASH_SR_BUSY, - FLASH_SR_NO_BUSY); + FLASH_SR_NO_BUSY); /* send write enable command */ dma_flash_transaction(sizeof(w_en), w_en, 0, NULL, 1); /* make sure busy bit cleared and write enabled. */ @@ -296,7 +296,7 @@ void FLASH_DMA_CODE dma_flash_cmd_write(int addr, int wlen, uint8_t *wbuf) flash_write[2] = (addr >> 8) & 0xff; flash_write[3] = addr & 0xff; dma_flash_transaction(sizeof(flash_write), flash_write, - 0, NULL, 0); + 0, NULL, 0); } } dma_flash_fsce_high(); @@ -340,7 +340,7 @@ int FLASH_DMA_CODE dma_flash_verify(int addr, int size, const char *data) if (flash[i] != 0xFF) return EC_ERROR_UNKNOWN; } - /* verify for write */ + /* verify for write */ } else { for (i = 0; i < size; i++) { if (flash[i] != wbuf[i]) @@ -395,8 +395,7 @@ static enum flash_wp_status flash_check_wp(void) * @param start_bank Start bank to protect * @param bank_count Number of banks to protect */ -static void flash_protect_banks(int start_bank, - int bank_count, +static void flash_protect_banks(int start_bank, int bank_count, enum flash_wp_interface wp_if) { int bank; @@ -507,13 +506,12 @@ int FLASH_DMA_CODE crec_flash_physical_erase(int offset, int size) */ if (IS_ENABLED(IT83XX_CHIP_FLASH_IS_KGD) && (size > 0x10000)) watchdog_reload(); - /* - * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS command - * during erasing. - */ + /* + * EC still need to handle AP's EC_CMD_GET_COMMS_STATUS + * command during erasing. + */ #ifdef IT83XX_IRQ_SPI_PERIPHERAL - if (IS_ENABLED(CONFIG_SPI) && - IS_ENABLED(HAS_TASK_HOSTCMD) && + if (IS_ENABLED(CONFIG_SPI) && IS_ENABLED(HAS_TASK_HOSTCMD) && IS_ENABLED(CONFIG_HOST_COMMAND_STATUS)) { if (IT83XX_SPI_RX_VLISR & IT83XX_SPI_RVLI) task_trigger_irq(IT83XX_IRQ_SPI_PERIPHERAL); @@ -555,17 +553,16 @@ int crec_flash_physical_protect_now(int all) { if (all) { /* Protect the entire flash */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_EC); all_protected = 1; } else { /* Protect the read-only section and persistent state */ - flash_protect_banks(WP_BANK_OFFSET, - WP_BANK_COUNT, FLASH_WP_EC); + flash_protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT, FLASH_WP_EC); #ifdef PSTATE_BANK - flash_protect_banks(PSTATE_BANK, - PSTATE_BANK_COUNT, FLASH_WP_EC); + flash_protect_banks(PSTATE_BANK, PSTATE_BANK_COUNT, + FLASH_WP_EC); #endif } @@ -612,8 +609,7 @@ uint32_t crec_flash_physical_get_protect_flags(void) */ uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -652,9 +648,8 @@ static void flash_enable_second_ilm(void) IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM0_ENABLE; IT83XX_SMFI_SCAR0H = BIT(3); /* copy code to ram */ - memcpy((void *)CHIP_RAMCODE_ILM0, - (const void *)FLASH_ILM0_ADDR, - IT83XX_ILM_BLOCK_SIZE); + memcpy((void *)CHIP_RAMCODE_ILM0, (const void *)FLASH_ILM0_ADDR, + IT83XX_ILM_BLOCK_SIZE); /* * Set the logic memory address(flash code of RO/RW) in flash * by programming the register SCAR0x bit19-bit0. @@ -675,7 +670,6 @@ static void flash_enable_second_ilm(void) static void flash_code_static_dma(void) { - /* Make sure no interrupt while enable static DMA */ interrupt_disable(); @@ -688,7 +682,7 @@ static void flash_code_static_dma(void) if (IS_ENABLED(CHIP_CORE_NDS32)) IT83XX_GCTRL_MCCR2 |= IT83XX_DLM14_ENABLE; memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START, - IT83XX_ILM_BLOCK_SIZE); + IT83XX_ILM_BLOCK_SIZE); if (IS_ENABLED(CHIP_CORE_RISCV)) IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE; /* Disable DLM 56k~60k region and be the ram code section */ @@ -745,7 +739,7 @@ int crec_flash_pre_init(void) reset_flags = system_get_reset_flags(); prot_flags = crec_flash_get_protect(); unwanted_prot_flags = EC_FLASH_PROTECT_ALL_NOW | - EC_FLASH_PROTECT_ERROR_INCONSISTENT; + EC_FLASH_PROTECT_ERROR_INCONSISTENT; /* * If we have already jumped between images, an earlier image could @@ -756,12 +750,12 @@ int crec_flash_pre_init(void) if (prot_flags & EC_FLASH_PROTECT_GPIO_ASSERTED) { /* Protect the entire flash of host interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_HOST); /* Protect the entire flash of DBGR interface */ - flash_protect_banks(0, - CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, + flash_protect_banks( + 0, CONFIG_FLASH_SIZE_BYTES / CONFIG_FLASH_BANK_SIZE, FLASH_WP_DBGR); /* * Write protect is asserted. If we want RO flash protected, @@ -769,8 +763,9 @@ int crec_flash_pre_init(void) */ if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); + int rv = + crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, + EC_FLASH_PROTECT_RO_NOW); if (rv) return rv; -- cgit v1.2.1 From bd28e003412090938d94eccab5a74a80ecf4f10f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:50 -0600 Subject: zephyr/shim/src/espi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3bc1d4849f5fbe81b1fc69f4163681bd547872a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730908 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/espi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c index 03a3eaf59b..d67dba87d9 100644 --- a/zephyr/shim/src/espi.c +++ b/zephyr/shim/src/espi.c @@ -492,7 +492,9 @@ DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, * This function is needed only for the obsolete platform which uses the GPIO * for KBC's IRQ. */ -void lpc_keyboard_resume_irq(void) {} +void lpc_keyboard_resume_irq(void) +{ +} void lpc_keyboard_clear_buffer(void) { @@ -534,8 +536,7 @@ static void kbc_ibf_obe_handler(uint32_t data) uint32_t status = I8042_AUX_DATA; if (is_ibf) { - keyboard_host_write(get_8042_data(data), - get_8042_type(data)); + keyboard_host_write(get_8042_data(data), get_8042_type(data)); } else if (IS_ENABLED(CONFIG_8042_AUX)) { espi_write_lpc_request(espi_dev, E8042_CLEAR_FLAG, &status); } -- cgit v1.2.1 From 97603d371c21e317e256297e85cd744e6a73872c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:09 -0600 Subject: zephyr/drivers/cros_rtc/cros_rtc_xec.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie15f5cdfa8648734824440b718bdfaebe0b69465 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730674 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_rtc/cros_rtc_xec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/drivers/cros_rtc/cros_rtc_xec.c b/zephyr/drivers/cros_rtc/cros_rtc_xec.c index ec8e0e6d07..3229105fd7 100644 --- a/zephyr/drivers/cros_rtc/cros_rtc_xec.c +++ b/zephyr/drivers/cros_rtc/cros_rtc_xec.c @@ -123,7 +123,7 @@ static const struct cros_rtc_xec_config cros_rtc_xec_cfg_0 = { static struct cros_rtc_xec_data cros_rtc_xec_data_0; -DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, - &cros_rtc_xec_data_0, &cros_rtc_xec_cfg_0, POST_KERNEL, +DEVICE_DT_INST_DEFINE(0, cros_rtc_xec_init, NULL, &cros_rtc_xec_data_0, + &cros_rtc_xec_cfg_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &cros_rtc_xec_driver_api); -- cgit v1.2.1 From 7efdcdfffa51699736b4af0e08e7d8396e0ca747 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:12 -0600 Subject: driver/temp_sensor/sb_tsi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iebd654ae40ea3847b3afcd39a6b50cbccc420882 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729875 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/sb_tsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/temp_sensor/sb_tsi.c b/driver/temp_sensor/sb_tsi.c index ffcd924b0e..8b4a1a91fc 100644 --- a/driver/temp_sensor/sb_tsi.c +++ b/driver/temp_sensor/sb_tsi.c @@ -19,8 +19,8 @@ static int raw_read8(const int offset, int *data_ptr) { - return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS, - offset, data_ptr); + return i2c_read8(I2C_PORT_THERMAL_AP, SB_TSI_I2C_ADDR_FLAGS, offset, + data_ptr); } int sb_tsi_get_val(int idx, int *temp_ptr) -- cgit v1.2.1 From f6c11e50401a03cd3f82f1b4123dbabcc1cfa2b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:44 -0600 Subject: board/rammus/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8e3d8cac16e8b4d402934629dc0bc3eb893545a5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728854 Reviewed-by: Jeremy Bettis --- board/rammus/cbi_ssfc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/rammus/cbi_ssfc.c b/board/rammus/cbi_ssfc.c index e1f6fa4bd2..9dc7842219 100644 --- a/board/rammus/cbi_ssfc.c +++ b/board/rammus/cbi_ssfc.c @@ -23,7 +23,7 @@ static void cbi_ssfc_init(void) CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value); } -DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_INIT_I2C + 1); enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { -- cgit v1.2.1 From b0dd467874017eee76abe93a5ebe770e079e3e04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:20 -0600 Subject: chip/stm32/usart_host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9340dfa2d2432c6c45f3b921081eb057d2953c80 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729543 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_host_command.c | 50 +++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 30 deletions(-) diff --git a/chip/stm32/usart_host_command.c b/chip/stm32/usart_host_command.c index f4d6a65fc4..b410bb41ed 100644 --- a/chip/stm32/usart_host_command.c +++ b/chip/stm32/usart_host_command.c @@ -19,8 +19,8 @@ #include "util.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_HOSTCMD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_HOSTCMD, format, ##args) /* * Timeout to wait for complete request packet @@ -51,7 +51,7 @@ /* * Max data size for a version 3 request/response packet. This is big enough - * to handle a request/response header, flash write offset/size and 512 bytes + * to handle a request/response header, flash write offset/size and 512 bytes * of request payload or 224 bytes of response payload. */ #define USART_MAX_REQUEST_SIZE 0x220 @@ -271,12 +271,12 @@ static struct usart_rx_dma const usart_host_command_rx_dma = { * Configure USART structure with hardware, interrupt handlers, baudrate. */ static struct usart_config const tl_usart = { - .hw = &CONFIG_UART_HOST_COMMAND_HW, - .rx = &usart_host_command_rx_dma.usart_rx, - .tx = &usart_host_command_tx_interrupt, - .state = &((struct usart_state){}), - .baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE, - .flags = 0, + .hw = &CONFIG_UART_HOST_COMMAND_HW, + .rx = &usart_host_command_rx_dma.usart_rx, + .tx = &usart_host_command_tx_interrupt, + .state = &((struct usart_state){}), + .baud = CONFIG_UART_HOST_COMMAND_BAUD_RATE, + .flags = 0, }; /* @@ -327,7 +327,7 @@ static void usart_host_command_process_request(void) { /* Handle usart_in_buffer as ec_host_request */ struct ec_host_request *ec_request = - (struct ec_host_request *)usart_in_buffer; + (struct ec_host_request *)usart_in_buffer; /* Prepare host_packet for host command task */ static struct host_packet uart_packet; @@ -362,16 +362,13 @@ static void usart_host_command_process_request(void) * Cancel deferred call to timeout handler as request * received was good. */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); + hook_call_deferred(&usart_host_command_request_timeout_data, -1); uart_packet.send_response = usart_host_command_process_response; uart_packet.request = usart_in_buffer; uart_packet.request_temp = NULL; uart_packet.request_max = sizeof(usart_in_buffer); - uart_packet.request_size = - host_request_expected_size(ec_request); + uart_packet.request_size = host_request_expected_size(ec_request); uart_packet.response = usart_out_buffer; uart_packet.response_max = sizeof(usart_out_buffer); uart_packet.response_size = 0; @@ -427,14 +424,10 @@ static void usart_host_command_process_response(struct host_packet *pkt) static void usart_host_command_reset(void) { /* Cancel deferred call to process_request. */ - hook_call_deferred( - &usart_host_command_process_request_data, - -1); + hook_call_deferred(&usart_host_command_process_request_data, -1); /* Cancel deferred call to timeout handler. */ - hook_call_deferred( - &usart_host_command_request_timeout_data, - -1); + hook_call_deferred(&usart_host_command_request_timeout_data, -1); /* * Disable interrupts before entering critical region @@ -491,7 +484,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, { /* Define ec_host_request pointer to process in bytes later*/ struct ec_host_request *ec_request = - (struct ec_host_request *) usart_in_buffer; + (struct ec_host_request *)usart_in_buffer; /* Once the header is received, store the datalen */ static int usart_in_datalen; @@ -504,8 +497,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, current_state == USART_HOST_CMD_RECEIVING || (usart_in_head + count) < USART_MAX_REQUEST_SIZE) { /* Copy all the bytes from DMA FIFO */ - memcpy(usart_in_buffer + usart_in_head, - src, count); + memcpy(usart_in_buffer + usart_in_head, src, count); } /* @@ -519,7 +511,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, if (current_state == USART_HOST_CMD_READY_TO_RX) { /* Kick deferred call to request timeout handler */ hook_call_deferred(&usart_host_command_request_timeout_data, - USART_REQ_RX_TIMEOUT); + USART_REQ_RX_TIMEOUT); /* Move current state to receiving */ current_state = USART_HOST_CMD_RECEIVING; @@ -551,8 +543,7 @@ size_t usart_host_command_rx_append_data(struct usart_config const *config, } else if (usart_in_head > usart_in_datalen) { /* Cancel deferred call to process_request */ hook_call_deferred( - &usart_host_command_process_request_data, - -1); + &usart_host_command_process_request_data, -1); /* Move state to overrun*/ current_state = USART_HOST_CMD_RX_OVERRUN; @@ -579,13 +570,12 @@ size_t usart_host_command_tx_remove_data(struct usart_config const *config, { size_t bytes_remaining = 0; - if (current_state == USART_HOST_CMD_SENDING && - usart_out_datalen != 0) { + if (current_state == USART_HOST_CMD_SENDING && usart_out_datalen != 0) { /* Calculate byte_remaining in out_buffer */ bytes_remaining = usart_out_datalen - usart_out_head; /* Get char on the head */ - *((uint8_t *) dest) = usart_out_buffer[usart_out_head++]; + *((uint8_t *)dest) = usart_out_buffer[usart_out_head++]; /* If no bytes remaining, reset layer to accept next * request. -- cgit v1.2.1 From 7e9db8755654e32a31217c6d9d0f3b2879ab858c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:46 -0600 Subject: board/berknip/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf4622b9af66d64a1be020ae027cc33e761eba25 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728053 Reviewed-by: Jeremy Bettis --- board/berknip/board.c | 142 ++++++++++++++++++++++---------------------------- 1 file changed, 62 insertions(+), 80 deletions(-) diff --git a/board/berknip/board.c b/board/berknip/board.c index 36b6b4f68f..f189263803 100644 --- a/board/berknip/board.c +++ b/board/berknip/board.c @@ -40,8 +40,8 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal); #include "gpio_list.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct pwm_t pwm_channels[] = { [PWM_CH_KBLIGHT] = { @@ -95,8 +95,7 @@ static void board_chipset_resume(void) if (ec_config_has_hdmi_retimer_pi3hdx1204()) { ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, check_hdmi_hpd_status()); } } @@ -105,9 +104,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); static void board_chipset_suspend(void) { if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0); } @@ -163,8 +160,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the TUSB544 as the secondary MUX */ usb_muxes[USBC_PORT_C1].next_mux = &usbc1_tusb544; @@ -176,8 +172,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the PS8743 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_ps8743, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_ps8743, sizeof(struct usb_mux)); /* Set the AMD FP5 as the secondary MUX */ usb_muxes[USBC_PORT_C1].next_mux = &usbc1_amd_fp5_usb_mux; @@ -201,67 +196,58 @@ struct usb_mux usb_muxes[] = { BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); static int board_tusb544_mux_set(const struct usb_mux *me, - mux_state_t mux_state) + mux_state_t mux_state) { int rv = EC_SUCCESS; if (mux_state & USB_PD_MUX_USB_ENABLED) { - - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_USB3_1_1, - TUSB544_EQ_RX_MASK, - TUSB544_EQ_RX_DFP_04_UFP_MINUS15); + rv = tusb544_i2c_field_update8( + me, TUSB544_REG_USB3_1_1, TUSB544_EQ_RX_MASK, + TUSB544_EQ_RX_DFP_04_UFP_MINUS15); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_USB3_1_1, - TUSB544_EQ_TX_MASK, - TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33); + rv = tusb544_i2c_field_update8( + me, TUSB544_REG_USB3_1_1, TUSB544_EQ_TX_MASK, + TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_USB3_1_2, - TUSB544_EQ_RX_MASK, - TUSB544_EQ_RX_DFP_04_UFP_MINUS15); + rv = tusb544_i2c_field_update8( + me, TUSB544_REG_USB3_1_2, TUSB544_EQ_RX_MASK, + TUSB544_EQ_RX_DFP_04_UFP_MINUS15); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_USB3_1_2, - TUSB544_EQ_TX_MASK, - TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33); + rv = tusb544_i2c_field_update8( + me, TUSB544_REG_USB3_1_2, TUSB544_EQ_TX_MASK, + TUSB544_EQ_TX_DFP_MINUS14_UFP_MINUS33); if (rv) return rv; } if (mux_state & USB_PD_MUX_DP_ENABLED) { - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_DISPLAYPORT_1, - TUSB544_EQ_RX_MASK, - TUSB544_EQ_RX_DFP_61_UFP_43); + rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1, + TUSB544_EQ_RX_MASK, + TUSB544_EQ_RX_DFP_61_UFP_43); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_DISPLAYPORT_1, - TUSB544_EQ_TX_MASK, - TUSB544_EQ_TX_DFP_61_UFP_43); + rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_1, + TUSB544_EQ_TX_MASK, + TUSB544_EQ_TX_DFP_61_UFP_43); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_DISPLAYPORT_2, - TUSB544_EQ_RX_MASK, - TUSB544_EQ_RX_DFP_61_UFP_43); + rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2, + TUSB544_EQ_RX_MASK, + TUSB544_EQ_RX_DFP_61_UFP_43); if (rv) return rv; - rv = tusb544_i2c_field_update8(me, - TUSB544_REG_DISPLAYPORT_2, - TUSB544_EQ_TX_MASK, - TUSB544_EQ_TX_DFP_61_UFP_43); + rv = tusb544_i2c_field_update8(me, TUSB544_REG_DISPLAYPORT_2, + TUSB544_EQ_TX_MASK, + TUSB544_EQ_TX_DFP_61_UFP_43); if (rv) return rv; @@ -346,10 +332,9 @@ static void hdmi_hpd_handler(void) gpio_set_level(GPIO_EC_DP1_HPD, hpd); ccprints("HDMI HPD %d", hpd); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && hpd); + pi3hdx1204_enable( + I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd); } DECLARE_DEFERRED(hdmi_hpd_handler); @@ -366,7 +351,7 @@ static void hdmi_hpd_interrupt(enum gpio_signal signal) /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -401,7 +386,7 @@ int board_get_temp(int idx, int *temp_k) /* adc power not ready when transition to S5 */ if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_SOFT_OFF)) + CHIPSET_STATE_SOFT_OFF)) return EC_ERROR_NOT_POWERED; channel = ADC_TEMP_SENSOR_SOC; @@ -413,7 +398,7 @@ int board_get_temp(int idx, int *temp_k) /* adc power not ready when transition to S5 */ if (chipset_in_or_transitioning_to_state( - CHIPSET_STATE_SOFT_OFF)) + CHIPSET_STATE_SOFT_OFF)) return EC_ERROR_NOT_POWERED; channel = ADC_TEMP_SENSOR_5V_REGULATOR; @@ -487,8 +472,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_THERMISTOR_SOC \ - { \ +#define THERMAL_THERMISTOR_SOC \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(62), \ [EC_TEMP_THRESH_HALT] = C_TO_K(66), \ @@ -506,7 +491,7 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_soc = * TODO(b/202062363): Remove when clang is fixed. */ #define THERMAL_THERMISTOR_CHARGER \ - { \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(99), \ [EC_TEMP_THRESH_HALT] = C_TO_K(99), \ @@ -515,16 +500,16 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_soc = [EC_TEMP_THRESH_HIGH] = C_TO_K(98), \ }, \ .temp_fan_off = C_TO_K(98), \ - .temp_fan_max = C_TO_K(99), \ + .temp_fan_max = C_TO_K(99), \ } -__maybe_unused static const struct ec_thermal_config - thermal_thermistor_charger = THERMAL_THERMISTOR_CHARGER; +__maybe_unused static const struct ec_thermal_config thermal_thermistor_charger = + THERMAL_THERMISTOR_CHARGER; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_THERMISTOR_5V \ - { \ +#define THERMAL_THERMISTOR_5V \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(60), \ [EC_TEMP_THRESH_HALT] = C_TO_K(99), \ @@ -541,8 +526,8 @@ __maybe_unused static const struct ec_thermal_config thermal_thermistor_5v = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ [EC_TEMP_THRESH_HALT] = C_TO_K(105), \ @@ -562,13 +547,13 @@ struct fan_step { }; static const struct fan_step fan_table0[] = { - {.on = 0, .off = 5, .rpm = 0}, - {.on = 29, .off = 5, .rpm = 3700}, - {.on = 38, .off = 19, .rpm = 4000}, - {.on = 48, .off = 33, .rpm = 4500}, - {.on = 62, .off = 43, .rpm = 4800}, - {.on = 76, .off = 52, .rpm = 5200}, - {.on = 100, .off = 67, .rpm = 6200}, + { .on = 0, .off = 5, .rpm = 0 }, + { .on = 29, .off = 5, .rpm = 3700 }, + { .on = 38, .off = 19, .rpm = 4000 }, + { .on = 48, .off = 33, .rpm = 4500 }, + { .on = 62, .off = 43, .rpm = 4800 }, + { .on = 76, .off = 52, .rpm = 5200 }, + { .on = 100, .off = 67, .rpm = 6200 }, }; /* All fan tables must have the same number of levels */ #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table0) @@ -608,8 +593,7 @@ int fan_percent_to_rpm(int fan, int pct) previous_pct = pct; - if (fan_table[current_level].rpm != - fan_get_rpm_target(FAN_CH(fan))) + if (fan_table[current_level].rpm != fan_get_rpm_target(FAN_CH(fan))) cprints(CC_THERMAL, "Setting fan RPM to %d", fan_table[current_level].rpm); @@ -632,15 +616,14 @@ DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT); * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, - {1, 4}, {1, 3}, {1, 6}, {1, 7}, {3, 1}, - {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, - {2, 4}, {2, 5}, {1, 2}, {2, 3}, {2, 2}, - {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, { 1, 4 }, + { 1, 3 }, { 1, 6 }, { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, + { 2, 6 }, { 2, 7 }, { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, + { 2, 3 }, { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif /***************************************************************************** @@ -685,9 +668,8 @@ enum gpio_signal board_usbc_port_to_hpd_gpio(int port) * from USB-PD messages.. */ else if (ec_config_has_mst_hub_rtd2141b()) - return (board_ver >= 3) - ? GPIO_USB_C1_HPD_IN_DB_V1 - : GPIO_NO_HPD; + return (board_ver >= 3) ? GPIO_USB_C1_HPD_IN_DB_V1 : + GPIO_NO_HPD; /* USB-C1 OPT1 DB uses DP2_HPD. */ return GPIO_DP2_HPD; -- cgit v1.2.1 From 8c60a9fa99c2684c6f4891f8752264bdcad71a5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:32 -0600 Subject: board/gingerbread/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic6763ca702ec02a55fd16a7c3d6a0622fc2adf6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728421 Reviewed-by: Jeremy Bettis --- board/gingerbread/board.c | 77 +++++++++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 42 deletions(-) diff --git a/board/gingerbread/board.c b/board/gingerbread/board.c index 3d80985c0a..1997ab0d3b 100644 --- a/board/gingerbread/board.c +++ b/board/gingerbread/board.c @@ -31,8 +31,8 @@ #include "usb_tc_sm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) #define QUICHE_PD_DEBUG_LVL 1 @@ -102,27 +102,27 @@ static void board_pwr_btn_interrupt(enum gpio_signal signal) * signals is driven by USB/MST hub power sequencing requirements. */ const struct power_seq board_power_seq[] = { - {GPIO_EN_AC_JACK, 1, 20}, - {GPIO_EN_PP5000_A, 1, 31}, - {GPIO_EN_PP3300_A, 1, 135}, - {GPIO_EN_BB, 1, 30}, - {GPIO_EN_PP1100_A, 1, 30}, - {GPIO_EN_PP1000_A, 1, 20}, - {GPIO_EN_PP1050_A, 1, 30}, - {GPIO_EN_PP1200_A, 1, 20}, - {GPIO_EN_PP5000_HSPORT, 1, 31}, - {GPIO_EN_DP_SINK, 1, 80}, - {GPIO_MST_LP_CTL_L, 1, 80}, - {GPIO_MST_RST_L, 1, 41}, - {GPIO_EC_HUB1_RESET_L, 1, 41}, - {GPIO_EC_HUB2_RESET_L, 1, 33}, - {GPIO_USBC_DP_PD_RST_L, 1, 100}, - {GPIO_USBC_UF_RESET_L, 1, 33}, - {GPIO_DEMUX_DUAL_DP_PD_N, 1, 100}, - {GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100}, - {GPIO_DEMUX_DP_HDMI_PD_N, 1, 10}, - {GPIO_DEMUX_DUAL_DP_MODE, 1, 10}, - {GPIO_DEMUX_DP_HDMI_MODE, 1, 1}, + { GPIO_EN_AC_JACK, 1, 20 }, + { GPIO_EN_PP5000_A, 1, 31 }, + { GPIO_EN_PP3300_A, 1, 135 }, + { GPIO_EN_BB, 1, 30 }, + { GPIO_EN_PP1100_A, 1, 30 }, + { GPIO_EN_PP1000_A, 1, 20 }, + { GPIO_EN_PP1050_A, 1, 30 }, + { GPIO_EN_PP1200_A, 1, 20 }, + { GPIO_EN_PP5000_HSPORT, 1, 31 }, + { GPIO_EN_DP_SINK, 1, 80 }, + { GPIO_MST_LP_CTL_L, 1, 80 }, + { GPIO_MST_RST_L, 1, 41 }, + { GPIO_EC_HUB1_RESET_L, 1, 41 }, + { GPIO_EC_HUB2_RESET_L, 1, 33 }, + { GPIO_USBC_DP_PD_RST_L, 1, 100 }, + { GPIO_USBC_UF_RESET_L, 1, 33 }, + { GPIO_DEMUX_DUAL_DP_PD_N, 1, 100 }, + { GPIO_DEMUX_DUAL_DP_RESET_N, 1, 100 }, + { GPIO_DEMUX_DP_HDMI_PD_N, 1, 10 }, + { GPIO_DEMUX_DUAL_DP_MODE, 1, 10 }, + { GPIO_DEMUX_DP_HDMI_MODE, 1, 1 }, }; const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); @@ -131,13 +131,13 @@ const size_t board_power_seq_count = ARRAY_SIZE(board_power_seq); * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Gingerbread"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = - USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Gingerbread"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = + USB_STRING_DESC(CROS_EC_SECTION ":" CROS_EC_VERSION32), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -205,14 +205,10 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { /* USB-C PPC Configuration */ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USB_PD_PORT_HOST] = { - .i2c_port = I2C_PORT_I2C3, - .i2c_addr_flags = SN5S330_ADDR0_FLAGS, - .drv = &sn5s330_drv - }, - [USB_PD_PORT_DP] = { - .drv = &board_ppc_null_drv - }, + [USB_PD_PORT_HOST] = { .i2c_port = I2C_PORT_I2C3, + .i2c_addr_flags = SN5S330_ADDR0_FLAGS, + .drv = &sn5s330_drv }, + [USB_PD_PORT_DP] = { .drv = &board_ppc_null_drv }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); @@ -239,7 +235,6 @@ void board_reset_pd_mcu(void) msleep(PS8805_FW_INIT_DELAY_MS); } - /* Power Delivery and charging functions */ void board_enable_usbc_interrupts(void) { @@ -253,7 +248,6 @@ void board_enable_usbc_interrupts(void) /* Enable HPD interrupt */ gpio_enable_interrupt(GPIO_DDI_MST_IN_HPD); - } /* Power Delivery and charging functions */ @@ -267,7 +261,6 @@ void board_disable_usbc_interrupts(void) /* Disable HPD interrupt */ gpio_disable_interrupt(GPIO_DDI_MST_IN_HPD); - } void board_tcpc_init(void) @@ -351,7 +344,7 @@ static void board_usb_tc_disconnect(void) gpio_set_level(GPIO_EC_HUB2_RESET_L, 0); } } -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, \ +DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, board_usb_tc_disconnect, HOOK_PRIO_DEFAULT); #endif /* SECTION_IS_RW */ -- cgit v1.2.1 From 898536608d5361d8cff631cf6361d1d3996712c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:56 -0600 Subject: zephyr/subsys/ap_pwrseq/signal_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib9a95dcbb5688a9e6d56bd53f864578abc33e84a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730952 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/signal_gpio.c | 36 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/signal_gpio.c b/zephyr/subsys/ap_pwrseq/signal_gpio.c index 9f8c3adb48..f4b74fd3be 100644 --- a/zephyr/subsys/ap_pwrseq/signal_gpio.c +++ b/zephyr/subsys/ap_pwrseq/signal_gpio.c @@ -8,16 +8,14 @@ #include #include "system.h" -#define MY_COMPAT intel_ap_pwrseq_gpio +#define MY_COMPAT intel_ap_pwrseq_gpio #if HAS_GPIO_SIGNALS -#define INIT_GPIO_SPEC(id) \ - GPIO_DT_SPEC_GET(id, gpios), +#define INIT_GPIO_SPEC(id) GPIO_DT_SPEC_GET(id, gpios), -const static struct gpio_dt_spec spec[] = { -DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_GPIO_SPEC) -}; +const static struct gpio_dt_spec spec[] = { DT_FOREACH_STATUS_OKAY( + MY_COMPAT, INIT_GPIO_SPEC) }; /* * Configuration for GPIO inputs. @@ -29,17 +27,16 @@ struct ps_gpio_int { unsigned no_enable : 1; }; -#define INIT_GPIO_CONFIG(id) \ - { \ - .flags = DT_PROP_OR(id, interrupt_flags, 0), \ - .signal = PWR_SIGNAL_ENUM(id), \ - .no_enable = DT_PROP(id, no_enable), \ - .output = DT_PROP(id, output), \ - }, +#define INIT_GPIO_CONFIG(id) \ + { \ + .flags = DT_PROP_OR(id, interrupt_flags, 0), \ + .signal = PWR_SIGNAL_ENUM(id), \ + .no_enable = DT_PROP(id, no_enable), \ + .output = DT_PROP(id, output), \ + }, -const static struct ps_gpio_int gpio_config[] = { -DT_FOREACH_STATUS_OKAY(MY_COMPAT, INIT_GPIO_CONFIG) -}; +const static struct ps_gpio_int gpio_config[] = { DT_FOREACH_STATUS_OKAY( + MY_COMPAT, INIT_GPIO_CONFIG) }; static struct gpio_callback int_cb[ARRAY_SIZE(gpio_config)]; @@ -123,7 +120,8 @@ void power_signal_gpio_init(void) * to the deasserted state. */ gpio_flags_t out_flags = system_jumped_to_this_image() ? - GPIO_OUTPUT : GPIO_OUTPUT_INACTIVE; + GPIO_OUTPUT : + GPIO_OUTPUT_INACTIVE; for (int i = 0; i < ARRAY_SIZE(gpio_config); i++) { if (gpio_config[i].output) { @@ -133,8 +131,8 @@ void power_signal_gpio_init(void) /* If interrupt, initialise it */ if (gpio_config[i].flags) { gpio_init_callback(&int_cb[i], - power_signal_gpio_interrupt, - BIT(spec[i].pin)); + power_signal_gpio_interrupt, + BIT(spec[i].pin)); gpio_add_callback(spec[i].port, &int_cb[i]); /* * If the interrupt is to be enabled at -- cgit v1.2.1 From d9033b55db20c38a53806e3950ce880cd0640adf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:48 -0600 Subject: driver/ioexpander/pcal6408.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I731f517f761a07194e970d630089d6d73efc7efb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729993 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pcal6408.c | 51 ++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/driver/ioexpander/pcal6408.c b/driver/ioexpander/pcal6408.c index 46de96b595..6ef0a9fe4d 100644 --- a/driver/ioexpander/pcal6408.c +++ b/driver/ioexpander/pcal6408.c @@ -12,8 +12,8 @@ #include "ioexpander.h" #include "pcal6408.h" -#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ## args) -#define CPRINTS(format, args...) cprints(CC_GPIO, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_GPIO, format, ##args) +#define CPRINTS(format, args...) cprints(CC_GPIO, format, ##args) #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT #error "This driver doesn't support get_port function" @@ -24,17 +24,16 @@ * we don't have to read it via i2c transaction every time. * Default value of interrupt mask register is 0xff. */ -uint8_t pcal6408_int_mask[] = { - [0 ... (CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = 0xff }; - +uint8_t pcal6408_int_mask[] = { [0 ...(CONFIG_IO_EXPANDER_PORT_COUNT - 1)] = + 0xff }; static int pcal6408_read(int ioex, int reg, int *data) { int rv; struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, data); + rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + data); return rv; } @@ -44,8 +43,8 @@ static int pcal6408_write(int ioex, int reg, int data) int rv; struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, data); + rv = i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + data); return rv; } @@ -56,8 +55,7 @@ static int pcal6408_ioex_check_is_valid(int port, int mask) return EC_ERROR_INVAL; if (mask & ~PCAL6408_VALID_GPIO_MASK) { - CPRINTF("GPIO%02d is not support in PCAL6408\n", - __fls(mask)); + CPRINTF("GPIO%02d is not support in PCAL6408\n", __fls(mask)); return EC_ERROR_INVAL; } @@ -110,7 +108,7 @@ static int pcal6408_ioex_set_level(int ioex, int port, int mask, int value) } static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask, - int *flags) + int *flags) { int rv, val; @@ -171,7 +169,7 @@ static int pcal6408_ioex_get_flags_by_mask(int ioex, int port, int mask, } static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask, - int flags) + int flags) { int rv, val; @@ -180,14 +178,13 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask, return rv; if (((flags & GPIO_INT_BOTH) == GPIO_INT_RISING) || - ((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) { + ((flags & GPIO_INT_BOTH) == GPIO_INT_FALLING)) { CPRINTF("PCAL6408 only support GPIO_INT_BOTH.\n"); return EC_ERROR_INVAL; } - if ((flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) && - !(flags & GPIO_INPUT)) { + !(flags & GPIO_INPUT)) { CPRINTF("Interrupt pin must be GPIO_INPUT.\n"); return EC_ERROR_INVAL; } @@ -269,7 +266,7 @@ static int pcal6408_ioex_set_flags_by_mask(int ioex, int port, int mask, } static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask, - int enable) + int enable) { int rv, val; @@ -302,7 +299,7 @@ static int pcal6408_ioex_enable_interrupt(int ioex, int port, int mask, pcal6408_int_mask[ioex] |= mask; rv = pcal6408_write(ioex, PCAL6408_REG_INT_MASK, - pcal6408_int_mask[ioex]); + pcal6408_int_mask[ioex]); return rv; } @@ -321,7 +318,7 @@ int pcal6408_ioex_event_handler(int ioex) * read status register will not. */ rv = i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - PCAL6408_REG_INT_STATUS, &int_status); + PCAL6408_REG_INT_STATUS, &int_status); if (rv != EC_SUCCESS) return rv; @@ -335,9 +332,7 @@ int pcal6408_ioex_event_handler(int ioex) return EC_SUCCESS; for (i = 0, g = ioex_list; i < ioex_ih_count; i++, g++) { - - if (ioex == g->ioex && 0 == g->port && - (int_status & g->mask)) { + if (ioex == g->ioex && 0 == g->port && (int_status & g->mask)) { ioex_irq_handlers[i](i + IOEX_SIGNAL_START); int_status &= ~g->mask; if (!int_status) @@ -349,10 +344,10 @@ int pcal6408_ioex_event_handler(int ioex) } const struct ioexpander_drv pcal6408_ioexpander_drv = { - .init = &pcal6408_ioex_init, - .get_level = &pcal6408_ioex_get_level, - .set_level = &pcal6408_ioex_set_level, - .get_flags_by_mask = &pcal6408_ioex_get_flags_by_mask, - .set_flags_by_mask = &pcal6408_ioex_set_flags_by_mask, - .enable_interrupt = &pcal6408_ioex_enable_interrupt, + .init = &pcal6408_ioex_init, + .get_level = &pcal6408_ioex_get_level, + .set_level = &pcal6408_ioex_set_level, + .get_flags_by_mask = &pcal6408_ioex_get_flags_by_mask, + .set_flags_by_mask = &pcal6408_ioex_set_flags_by_mask, + .enable_interrupt = &pcal6408_ioex_enable_interrupt, }; -- cgit v1.2.1 From f3ecca5564da30bc2276e029215af6ef78585fe5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:08 -0600 Subject: board/poppy/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ied42fb6687c4b81bd1fa0e039ae630cc677de390 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727753 Reviewed-by: Jeremy Bettis --- board/poppy/board.c | 189 +++++++++++++++++++++++----------------------------- 1 file changed, 82 insertions(+), 107 deletions(-) diff --git a/board/poppy/board.c b/board/poppy/board.c index 3aa99c1161..5e8e38faf7 100644 --- a/board/poppy/board.c +++ b/board/poppy/board.c @@ -52,10 +52,10 @@ #include "util.h" #include "espi.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_ANX74XX 0 /* Minimum input current limit. */ #define ILIM_MIN_MA 472 @@ -80,9 +80,9 @@ static void vbus_discharge_handler(void) { if (system_get_board_version() >= 2) { pd_set_vbus_discharge(0, - gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); + gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L)); pd_set_vbus_discharge(1, - gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); + gpio_get_level(GPIO_USB_C1_VBUS_WAKE_L)); } } DECLARE_DEFERRED(vbus_discharge_handler); @@ -154,16 +154,17 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* ADC channels */ const struct adc_t adc_channels[] = { /* Base detection */ - [ADC_BASE_DET] = {"BASE_DET", NPCX_ADC_CH0, - ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_BASE_DET] = { "BASE_DET", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, /* Vbus sensing (10x voltage divider). */ - [ADC_VBUS] = {"VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0}, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH2, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = {"AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT*1000/18, - ADC_READ_MAX+1, 0}, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH1, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, #ifdef BOARD_LUX /* * ISL9238 PSYS output is 1.44 uA/W over 12.4K resistor, to read @@ -171,49 +172,39 @@ const struct adc_t adc_channels[] = { * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = {"PSYS", NPCX_ADC_CH3, - ADC_MAX_VOLT*56250*2/(ADC_READ_MAX+1), 2, 0}, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 56250 * 2 / (ADC_READ_MAX + 1), 2, 0 }, #endif }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* I2C port map */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_I2C0_0_SCL, - .sda = GPIO_I2C0_0_SDA - }, - { - .name = "als", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_I2C0_1_SCL, - .sda = GPIO_I2C0_1_SDA - }, - { - .name = "charger", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "pmic", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "accelgyro", - .port = NPCX_I2C_PORT3, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_I2C0_0_SCL, + .sda = GPIO_I2C0_0_SDA }, + { .name = "als", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_I2C0_1_SCL, + .sda = GPIO_I2C0_1_SDA }, + { .name = "charger", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "pmic", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "accelgyro", + .port = NPCX_I2C_PORT3, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -271,7 +262,6 @@ const struct charger_config_t chg_chips[] = { }, }; - /** * Power on (or off) a single TCPC. * minimum on/off delays are included. @@ -349,9 +339,9 @@ void board_tcpc_init(void) */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); uint16_t tcpc_get_alert_status(void) { @@ -371,17 +361,17 @@ uint16_t tcpc_get_alert_status(void) } const struct temp_sensor_t temp_sensors[] = { - {"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0}, + { "Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0 }, /* These BD99992GW temp sensors are only readable in S0 */ - {"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM0}, - {"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM1}, - {"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM2}, - {"eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, - BD99992GW_ADC_CHANNEL_SYSTHERM3}, + { "Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM0 }, + { "Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM1 }, + { "DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM2 }, + { "eMMC", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val, + BD99992GW_ADC_CHANNEL_SYSTHERM3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -397,8 +387,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x8, &vrfault) != + EC_SUCCESS) return; if (!(vrfault & BIT(4))) @@ -507,8 +497,7 @@ static void board_pmic_enable_slp_s0_vr_decay(void) i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a); } -__override void power_board_handle_host_sleep_event( - enum host_sleep_event state) +__override void power_board_handle_host_sleep_event(enum host_sleep_event state) { if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) board_pmic_enable_slp_s0_vr_decay(); @@ -561,9 +550,9 @@ static void board_init(void) * force detection on both ports. */ gpio_set_flags(GPIO_USB_C0_VBUS_WAKE_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); gpio_set_flags(GPIO_USB_C1_VBUS_WAKE_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); vbus0_evt(GPIO_USB_C0_VBUS_WAKE_L); vbus1_evt(GPIO_USB_C1_VBUS_WAKE_L); @@ -582,10 +571,9 @@ static void board_init(void) */ if (system_get_board_version() >= 5) gpio_set_flags(GPIO_LED_YELLOW_C0_OLD, - GPIO_INPUT | GPIO_PULL_UP); + GPIO_INPUT | GPIO_PULL_UP); else - gpio_set_flags(GPIO_LED_YELLOW_C0, - GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_LED_YELLOW_C0, GPIO_INPUT | GPIO_PULL_UP); #ifdef BOARD_SORAKA /* @@ -594,18 +582,12 @@ static void board_init(void) * for better S0ix/S3 power */ if (system_get_board_version() >= 4) { - gpio_set_flags(GPIO_WLAN_PE_RST, - GPIO_INPUT | GPIO_PULL_UP); - gpio_set_flags(GPIO_PP3300_DX_LTE, - GPIO_INPUT | GPIO_PULL_UP); - gpio_set_flags(GPIO_LTE_GPS_OFF_L, - GPIO_INPUT | GPIO_PULL_UP); - gpio_set_flags(GPIO_LTE_BODY_SAR_L, - GPIO_INPUT | GPIO_PULL_UP); - gpio_set_flags(GPIO_LTE_WAKE_L, - GPIO_INPUT | GPIO_PULL_UP); - gpio_set_flags(GPIO_LTE_OFF_ODL, - GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_WLAN_PE_RST, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_PP3300_DX_LTE, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_LTE_GPS_OFF_L, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_LTE_BODY_SAR_L, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_LTE_WAKE_L, GPIO_INPUT | GPIO_PULL_UP); + gpio_set_flags(GPIO_LTE_OFF_ODL, GPIO_INPUT | GPIO_PULL_UP); } #endif @@ -671,10 +653,12 @@ int board_set_active_charge_port(int charge_port) #endif /* Make sure non-charging port is disabled */ gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_L : - GPIO_USB_C1_CHARGE_L, 1); + GPIO_USB_C1_CHARGE_L, + 1); /* Enable charging port */ gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 0); + GPIO_USB_C0_CHARGE_L, + 0); } return EC_SUCCESS; @@ -688,8 +672,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Adjust ILIM according to measurements to eliminate overshoot. */ charge_ma = (charge_ma - 500) * 31 / 32 + 472; @@ -706,8 +690,7 @@ void board_hibernate(void) uart_flush_output(); /* Trigger PMIC shutdown. */ - if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, - 0x49, 0x01)) { + if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) { /* * If we can't tell the PMIC to shutdown, instead reset * and don't start the AP. Hopefully we'll be able to @@ -763,31 +746,23 @@ static struct opt3001_drv_data_t g_opt3001_data = { }; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t mag_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; #ifdef BOARD_SORAKA -const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* For rev3 and older */ -const mat33_fp_t lid_standard_ref_old = { - {FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref_old = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; #else -const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; #endif struct motion_sensor_t motion_sensors[] = { -- cgit v1.2.1 From 5007adde845205b817896f67ceda6507e9e23165 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:49 -0600 Subject: board/zinger/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10e33b4bbae38446f9da582f6abb1cac06a6b798 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729140 Reviewed-by: Jeremy Bettis --- board/zinger/board.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/zinger/board.h b/board/zinger/board.h index 0be755eb5c..8d706af32f 100644 --- a/board/zinger/board.h +++ b/board/zinger/board.h @@ -41,7 +41,7 @@ #undef CONFIG_FLASH_PHYSICAL #undef CONFIG_FMAP /* Not using pstate but keep some space for the public key */ -#undef CONFIG_FW_PSTATE_SIZE +#undef CONFIG_FW_PSTATE_SIZE #define CONFIG_FW_PSTATE_SIZE 544 #define CONFIG_HIBERNATE #define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1 @@ -59,7 +59,7 @@ #undef CONFIG_USB_PD_DUAL_ROLE #undef CONFIG_USB_PD_INTERNAL_COMP #define CONFIG_USB_PD_LOGGING -#undef CONFIG_EVENT_LOG_SIZE +#undef CONFIG_EVENT_LOG_SIZE #define CONFIG_EVENT_LOG_SIZE 256 #define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED #define CONFIG_USB_PD_PORT_MAX_COUNT 1 @@ -105,10 +105,11 @@ enum adc_channel { #define ADC_CH_CC2_PD ADC_CH_CC1_PD /* 3.0A Rp */ -#define PD_SRC_VNC (PD_SRC_3_0_VNC_MV * 4096 / 3300/* 12-bit ADC, 3.3V range */) +#define PD_SRC_VNC \ + (PD_SRC_3_0_VNC_MV * 4096 / 3300 /* 12-bit ADC, 3.3V range */) /* delay necessary for the voltage transition on the power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Initialize all useful registers */ -- cgit v1.2.1 From 973729efcd4359648194bcf5c9602bef175f7a3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:21 -0600 Subject: board/atlas/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iabb40a95b73219200754dcc8721ee78430f4d3cc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727996 Reviewed-by: Jeremy Bettis --- board/atlas/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/atlas/led.c b/board/atlas/led.c index 9cb4dabfd3..6cc36c1e9a 100644 --- a/board/atlas/led.c +++ b/board/atlas/led.c @@ -18,13 +18,13 @@ const enum ec_led_id supported_led_ids[] = { const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 70, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 35, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 55, 15, 0 }, - [EC_LED_COLOR_WHITE] = { 62, 100, 31 }, - [EC_LED_COLOR_AMBER] = { 100, 31, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 70, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 35, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 55, 15, 0 }, + [EC_LED_COLOR_WHITE] = { 62, 100, 31 }, + [EC_LED_COLOR_AMBER] = { 100, 31, 0 }, }; /* -- cgit v1.2.1 From 19b2c9595256194fb1ce6d0ca6d44cd4a9ebd30b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:56 -0600 Subject: driver/retimer/tusb544.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I799e528db49cf6d23cb4aaaf6ab33cce36c99be1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730070 Reviewed-by: Jeremy Bettis --- driver/retimer/tusb544.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/driver/retimer/tusb544.c b/driver/retimer/tusb544.c index 9de543fd42..661f08cec2 100644 --- a/driver/retimer/tusb544.c +++ b/driver/retimer/tusb544.c @@ -10,28 +10,21 @@ static int tusb544_write(const struct usb_mux *me, int offset, int data) { - return i2c_write8(me->i2c_port, - me->i2c_addr_flags, - offset, data); + return i2c_write8(me->i2c_port, me->i2c_addr_flags, offset, data); } static int tusb544_read(const struct usb_mux *me, int offset, int *data) { - return i2c_read8(me->i2c_port, - me->i2c_addr_flags, - offset, data); + return i2c_read8(me->i2c_port, me->i2c_addr_flags, offset, data); } int tusb544_i2c_field_update8(const struct usb_mux *me, int offset, - uint8_t field_mask, uint8_t set_value) + uint8_t field_mask, uint8_t set_value) { int rv; - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags, offset, + field_mask, set_value); return rv; } -- cgit v1.2.1 From 3359ce7438e21964141a248779ce4a46caa2cba0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:05 -0600 Subject: board/gumboz/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I056f267e080ae17b3b71be4d6227aea221828ba8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728435 Reviewed-by: Jeremy Bettis --- board/gumboz/led.c | 51 ++++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/board/gumboz/led.c b/board/gumboz/led.c index ac27fe3a2c..8510426b9f 100644 --- a/board/gumboz/led.c +++ b/board/gumboz/led.c @@ -23,11 +23,9 @@ #define LED_TICKS_PER_CYCLE 10 #define LED_ON_TICKS 5 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_LEFT_LED, + EC_LED_ID_RIGHT_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -35,13 +33,10 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -enum led_port { - LEFT_PORT = 0, - RIGHT_PORT -}; +enum led_port { LEFT_PORT = 0, RIGHT_PORT }; static void led_set_color_battery(int port, enum led_color color) { @@ -51,9 +46,9 @@ static void led_set_color_battery(int port, enum led_color color) cbi_get_board_version(&board_ver); amber_led = (port == LEFT_PORT ? GPIO_LED_CHRG_L : - IOEX_C1_CHARGER_LED_AMBER_DB); + IOEX_C1_CHARGER_LED_AMBER_DB); white_led = (port == LEFT_PORT ? GPIO_LED_FULL_L : - IOEX_C1_CHARGER_LED_WHITE_DB); + IOEX_C1_CHARGER_LED_WHITE_DB); if ((board_ver >= 2) && (port == RIGHT_PORT)) { led_batt_on_lvl = 1; @@ -156,10 +151,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) led_set_color_battery(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) led_set_color_battery(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void led_set_battery(void) @@ -177,9 +172,12 @@ static void led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) { if (charge_get_percent() < 10) - led_set_color_battery(RIGHT_PORT, - (battery_ticks % LED_TICKS_PER_CYCLE - < LED_ON_TICKS) ? LED_WHITE : LED_OFF); + led_set_color_battery( + RIGHT_PORT, + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_battery(RIGHT_PORT, LED_OFF); } @@ -188,17 +186,19 @@ static void led_set_battery(void) led_set_color_battery(LEFT_PORT, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); else set_active_port_color(LED_WHITE); break; @@ -217,9 +217,10 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power((power_tick % - LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? - LED_WHITE : LED_OFF); + led_set_color_power( + (power_tick % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From 0216dc751d16df93e9c4b3160435f1a44db5bc15 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:31 -0600 Subject: power/cannonlake.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I58f1c34fc937659ced67cf8b168b6308eb3ba681 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730461 Reviewed-by: Jeremy Bettis --- power/cannonlake.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/power/cannonlake.c b/power/cannonlake.c index 392db669df..b4ffa94f41 100644 --- a/power/cannonlake.c +++ b/power/cannonlake.c @@ -16,9 +16,9 @@ #include "timer.h" /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) -static int forcing_shutdown; /* Forced shutdown in progress? */ +static int forcing_shutdown; /* Forced shutdown in progress? */ void chipset_force_shutdown(enum chipset_shutdown_reason reason) { @@ -47,7 +47,7 @@ void chipset_handle_espi_reset_assert(void) * power button. If yes, release power button. */ if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) && - forcing_shutdown) { + forcing_shutdown) { power_button_pch_release(); forcing_shutdown = 0; } -- cgit v1.2.1 From 8a5a1048bcd848940568a96609e20334173015b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:36 -0600 Subject: board/gooey/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0ebe15e11c4408006991cdb4e94568e234bde7c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728423 Reviewed-by: Jeremy Bettis --- board/gooey/board.c | 85 ++++++++++++++++++++++------------------------------- 1 file changed, 35 insertions(+), 50 deletions(-) diff --git a/board/gooey/board.c b/board/gooey/board.c index fe7e2c3792..03fcc5df8e 100644 --- a/board/gooey/board.c +++ b/board/gooey/board.c @@ -40,7 +40,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 /* C0 interrupt line shared by BC 1.2 and charger */ @@ -84,7 +84,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -114,8 +113,7 @@ DECLARE_DEFERRED(pendetect_deferred); void pen_detect_interrupt(enum gpio_signal s) { /* Trigger deferred notification of pen detect change */ - hook_call_deferred(&pendetect_deferred_data, - 500 * MSEC); + hook_call_deferred(&pendetect_deferred_data, 500 * MSEC); } void board_hibernate(void) @@ -132,27 +130,21 @@ void board_hibernate(void) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -291,7 +283,6 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) @@ -303,8 +294,7 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); raa489000_enable_asgate(0, false); return EC_SUCCESS; } @@ -317,8 +307,7 @@ int board_set_active_charge_port(int port) /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { CPRINTUSB("p%d: sink path enable failed.", port); return EC_ERROR_UNKNOWN; } @@ -360,17 +349,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* Sensor Data */ static struct stprivate_data g_lis2dwl_data; @@ -452,14 +437,14 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -508,8 +493,8 @@ static const struct ec_response_keybd_config gooey_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &gooey_keybd; } -- cgit v1.2.1 From 62ffaa5032b38dce2435784eb0e270661589427d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:26 -0600 Subject: chip/mt_scp/mt8195/clock_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3edf6975f8eff7d99ec56eafddda25e1a0e80ff4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729344 Reviewed-by: Jeremy Bettis --- chip/mt_scp/mt8195/clock_regs.h | 104 ++++++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 53 deletions(-) diff --git a/chip/mt_scp/mt8195/clock_regs.h b/chip/mt_scp/mt8195/clock_regs.h index 6e7ec6bdbb..0c1b55dbe5 100644 --- a/chip/mt_scp/mt8195/clock_regs.h +++ b/chip/mt_scp/mt8195/clock_regs.h @@ -9,55 +9,53 @@ #define __CROS_EC_CLOCK_REGS_H /* clock source select */ -#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) -#define CLK_SW_SEL_SYSTEM 0 -#define CLK_SW_SEL_32K 1 -#define CLK_SW_SEL_ULPOSC2 2 -#define CLK_SW_SEL_ULPOSC1 3 -#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) -#define CLK_HIGH_EN BIT(1) /* ULPOSC */ -#define CLK_HIGH_CG BIT(2) +#define SCP_CLK_SW_SEL REG32(SCP_CLK_CTRL_BASE + 0x0000) +#define CLK_SW_SEL_SYSTEM 0 +#define CLK_SW_SEL_32K 1 +#define CLK_SW_SEL_ULPOSC2 2 +#define CLK_SW_SEL_ULPOSC1 3 +#define SCP_CLK_ENABLE REG32(SCP_CLK_CTRL_BASE + 0x0004) +#define CLK_HIGH_EN BIT(1) /* ULPOSC */ +#define CLK_HIGH_CG BIT(2) /* clock general control */ -#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) -#define VREQ_PMIC_WRAP_SEL (0x3) +#define SCP_CLK_CTRL_GENERAL_CTRL REG32(SCP_CLK_CTRL_BASE + 0x009C) +#define VREQ_PMIC_WRAP_SEL (0x3) /* TOPCK clk */ -#define TOPCK_BASE AP_REG_BASE -#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010) -#define F_ULPOSC_CK_UPDATE BIT(21) -#define F_ULPOSC_CORE_CK_UPDATE BIT(22) -#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180) -#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184) -#define ULPOSC1_CLK_SEL (0x3 << 8) -#define PDN_F_ULPOSC_CK BIT(15) -#define ULPOSC2_CLK_SEL (0x3 << 16) -#define PDN_F_ULPOSC_CORE_CK BIT(23) +#define TOPCK_BASE AP_REG_BASE +#define AP_CLK_CFG_UPDATE3 REG32(TOPCK_BASE + 0x0010) +#define F_ULPOSC_CK_UPDATE BIT(21) +#define F_ULPOSC_CORE_CK_UPDATE BIT(22) +#define AP_CLK_CFG_29_SET REG32(TOPCK_BASE + 0x0180) +#define AP_CLK_CFG_29_CLR REG32(TOPCK_BASE + 0x0184) +#define ULPOSC1_CLK_SEL (0x3 << 8) +#define PDN_F_ULPOSC_CK BIT(15) +#define ULPOSC2_CLK_SEL (0x3 << 16) +#define PDN_F_ULPOSC_CORE_CK BIT(23) /* OSC meter */ -#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C) -#define DBG_MODE_MASK 3 -#define DBG_MODE_SET_CLOCK 0 -#define DBG_BIST_SOURCE_MASK (0x7f << 8) -#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8) -#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8) -#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218) -#define CFG_FREQ_METER_RUN BIT(4) -#define CFG_FREQ_METER_ENABLE BIT(7) -#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C) -#define CFG_CKGEN_LOAD_CNT 0x01ff0000 -#define CFG_FREQ_COUNTER(CFG1) ((CFG1) & 0xFFFF) -#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C) -#define MISC_METER_DIVISOR_MASK 0xff000000 -#define MISC_METER_DIV_1 0 +#define AP_CLK_DBG_CFG REG32(TOPCK_BASE + 0x020C) +#define DBG_MODE_MASK 3 +#define DBG_MODE_SET_CLOCK 0 +#define DBG_BIST_SOURCE_MASK (0x7f << 8) +#define DBG_BIST_SOURCE_ULPOSC1 (0x30 << 8) +#define DBG_BIST_SOURCE_ULPOSC2 (0x32 << 8) +#define AP_CLK26CALI_0 REG32(TOPCK_BASE + 0x0218) +#define CFG_FREQ_METER_RUN BIT(4) +#define CFG_FREQ_METER_ENABLE BIT(7) +#define AP_CLK26CALI_1 REG32(TOPCK_BASE + 0x021C) +#define CFG_CKGEN_LOAD_CNT 0x01ff0000 +#define CFG_FREQ_COUNTER(CFG1) ((CFG1)&0xFFFF) +#define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x022C) +#define MISC_METER_DIVISOR_MASK 0xff000000 +#define MISC_METER_DIV_1 0 /* * ULPOSC * osc: 0 for ULPOSC1, 1 for ULPOSC2. */ -#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) -#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) -#define AP_ULPOSC_CON0(osc) \ - REG32(AP_ULPOSC_CON0_BASE + (osc) * 0x10) -#define AP_ULPOSC_CON1(osc) \ - REG32(AP_ULPOSC_CON1_BASE + (osc) * 0x10) +#define AP_ULPOSC_CON0_BASE (AP_REG_BASE + 0xC2B0) +#define AP_ULPOSC_CON1_BASE (AP_REG_BASE + 0xC2B4) +#define AP_ULPOSC_CON0(osc) REG32(AP_ULPOSC_CON0_BASE + (osc)*0x10) +#define AP_ULPOSC_CON1(osc) REG32(AP_ULPOSC_CON1_BASE + (osc)*0x10) /* * AP_ULPOSC_CON0 * bit0-6: calibration @@ -69,14 +67,14 @@ * bit27: div2_en * bit28-31: reserved */ -#define OSC_CALI_SHIFT 0 -#define OSC_CALI_MASK 0x7f -#define OSC_IBAND_SHIFT 7 -#define OSC_FBAND_SHIFT 14 -#define OSC_DIV_SHIFT 18 -#define OSC_CP_EN BIT(24) -#define OSC_MOD_SHIFT 25 -#define OSC_DIV2_EN BIT(27) +#define OSC_CALI_SHIFT 0 +#define OSC_CALI_MASK 0x7f +#define OSC_IBAND_SHIFT 7 +#define OSC_FBAND_SHIFT 14 +#define OSC_DIV_SHIFT 18 +#define OSC_CP_EN BIT(24) +#define OSC_MOD_SHIFT 25 +#define OSC_DIV2_EN BIT(27) /* * AP_ULPOSC_CON1 * bit0-7: rsv1 @@ -84,9 +82,9 @@ * bit16-23: 32K calibration * bit24-31: bias */ -#define OSC_RSV1_SHIFT 0 -#define OSC_RSV2_SHIFT 8 -#define OSC_32KCALI_SHIFT 16 -#define OSC_BIAS_SHIFT 24 +#define OSC_RSV1_SHIFT 0 +#define OSC_RSV2_SHIFT 8 +#define OSC_32KCALI_SHIFT 16 +#define OSC_BIAS_SHIFT 24 #endif /* __CROS_EC_CLOCK_REGS_H */ -- cgit v1.2.1 From 2e6cb979e5b66caee6530475403e534f183d6a7a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:18 -0600 Subject: chip/stm32/gpio-stm32l4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3113a72401fb2491a62694e00efaa8f51144617 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729507 Reviewed-by: Jeremy Bettis --- chip/stm32/gpio-stm32l4.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/stm32/gpio-stm32l4.c b/chip/stm32/gpio-stm32l4.c index f4ec6f4412..2255e52363 100644 --- a/chip/stm32/gpio-stm32l4.c +++ b/chip/stm32/gpio-stm32l4.c @@ -38,7 +38,6 @@ static void gpio_init(void) task_enable_irq(STM32_IRQ_EXTI4); task_enable_irq(STM32_IRQ_EXTI9_5); task_enable_irq(STM32_IRQ_EXTI15_10); - } DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 058322595415f0ff3929db71d8f3db73f276d20a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:43:08 -0600 Subject: board/kukui_scp/mdp_ipi_message.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If2b3a4e9705cc4b41bcc45d04aba4d7c317d3e94 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728542 Reviewed-by: Jeremy Bettis --- board/kukui_scp/mdp_ipi_message.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/board/kukui_scp/mdp_ipi_message.c b/board/kukui_scp/mdp_ipi_message.c index eca40b741b..934ac1be1f 100644 --- a/board/kukui_scp/mdp_ipi_message.c +++ b/board/kukui_scp/mdp_ipi_message.c @@ -18,19 +18,23 @@ static struct consumer const event_mdp_consumer; static void event_mdp_written(struct consumer const *consumer, size_t count); -static struct queue const event_mdp_queue = QUEUE_DIRECT(4, - struct mdp_msg_service, null_producer, event_mdp_consumer); +static struct queue const event_mdp_queue = QUEUE_DIRECT( + 4, struct mdp_msg_service, null_producer, event_mdp_consumer); static struct consumer const event_mdp_consumer = { .queue = &event_mdp_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_mdp_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT8183 -void mdp_common_init(void) {} -void mdp_ipi_task_handler(void *pvParameters) {} +void mdp_common_init(void) +{ +} +void mdp_ipi_task_handler(void *pvParameters) +{ +} #endif static void event_mdp_written(struct consumer const *consumer, size_t count) -- cgit v1.2.1 From 48ab55d4a7fa7a72c219d9fbe95d3ee3bbc7bb77 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:29 -0600 Subject: zephyr/drivers/cros_shi/cros_shi_npcx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5db6ff66d66df215b2d1693b77ee1f9fae4f33b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730680 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_shi/cros_shi_npcx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c index b236980205..33f20155cb 100644 --- a/zephyr/drivers/cros_shi/cros_shi_npcx.c +++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c @@ -810,7 +810,7 @@ static int cros_shi_npcx_disable(const struct device *dev) } ret = clock_control_off(clk_dev, - (clock_control_subsys_t *)&config->clk_cfg); + (clock_control_subsys_t *)&config->clk_cfg); if (ret < 0) { DEBUG_CPRINTF("Turn off SHI clock fail %d", ret); return ret; -- cgit v1.2.1 From 7a7efc2c2bd70a91f59d5b5248c390aa075e8b7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:15 -0600 Subject: board/karma/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0033718540858f6b494d44846b139f4e56dc7fa5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728528 Reviewed-by: Jeremy Bettis --- board/karma/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/karma/board.c b/board/karma/board.c index 4e9f9166ff..ed80cde3d2 100644 --- a/board/karma/board.c +++ b/board/karma/board.c @@ -8,8 +8,8 @@ #include "hooks.h" #include "oz554.h" -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_I2C, format, ##args) void oz554_board_init(void) { -- cgit v1.2.1 From 3b4573f0d6ab6d4249039155bef2d21a7f05f5cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:44 -0600 Subject: chip/ish/hpet.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6855ec3ada53b868a6d53e2ccdd3d08c2c731986 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729181 Reviewed-by: Jeremy Bettis --- chip/ish/hpet.h | 67 +++++++++++++++++++++++++++------------------------------ 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h index 06738fafb1..293c1fe6f2 100644 --- a/chip/ish/hpet.h +++ b/chip/ish/hpet.h @@ -10,61 +10,58 @@ /* ISH HPET config and timer registers */ -#define TIMER0_CONF_CAP_REG 0x100 -#define TIMER0_COMP_VAL_REG 0x108 - +#define TIMER0_CONF_CAP_REG 0x100 +#define TIMER0_COMP_VAL_REG 0x108 /* HPET_GENERAL_CONFIG settings */ -#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10) -#define HPET_ENABLE_CNF BIT(0) -#define HPET_LEGACY_RT_CNF BIT(1) +#define HPET_GENERAL_CONFIG REG32(ISH_HPET_BASE + 0x10) +#define HPET_ENABLE_CNF BIT(0) +#define HPET_LEGACY_RT_CNF BIT(1) /* Interrupt status acknowledge register */ -#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20) +#define HPET_INTR_CLEAR REG32(ISH_HPET_BASE + 0x20) /* Main counter register. 64-bit */ -#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0) -#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4) +#define HPET_MAIN_COUNTER_64 REG64(ISH_HPET_BASE + 0xF0) +#define HPET_MAIN_COUNTER_64_LO REG32(ISH_HPET_BASE + 0xF0) +#define HPET_MAIN_COUNTER_64_HI REG32(ISH_HPET_BASE + 0xF4) /* HPET Timer 0/1/2 configuration*/ -#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x) * 0x20)) -#define HPET_Tn_INT_TYPE_CNF BIT(1) -#define HPET_Tn_INT_ENB_CNF BIT(2) -#define HPET_Tn_TYPE_CNF BIT(3) -#define HPET_Tn_VAL_SET_CNF BIT(6) -#define HPET_Tn_32MODE_CNF BIT(8) -#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9 -#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) +#define HPET_TIMER_CONF_CAP(x) REG32(ISH_HPET_BASE + 0x100 + ((x)*0x20)) +#define HPET_Tn_INT_TYPE_CNF BIT(1) +#define HPET_Tn_INT_ENB_CNF BIT(2) +#define HPET_Tn_TYPE_CNF BIT(3) +#define HPET_Tn_VAL_SET_CNF BIT(6) +#define HPET_Tn_32MODE_CNF BIT(8) +#define HPET_Tn_INT_ROUTE_CNF_SHIFT 0x9 +#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9) /* * HPET Timer 0/1/2 comparator values. 1/2 are always 32-bit. 0 can be * configured as 64-bit. */ -#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x) * 0x20)) -#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108) +#define HPET_TIMER_COMP(x) REG32(ISH_HPET_BASE + 0x108 + ((x)*0x20)) +#define HPET_TIMER0_COMP_64 REG64(ISH_HPET_BASE + 0x108) /* ISH 4/5: Special status register * Use this register to see HPET timer are settled after a write. */ -#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) -#define HPET_INT_STATUS_SETTLING BIT(1) -#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3)) -#define HPET_T0_CAP_SETTLING BIT(4) -#define HPET_T1_CAP_SETTLING BIT(5) -#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8)) -#define HPET_T1_CMP_SETTLING BIT(9) -#define HPET_MAIN_COUNTER_VALID BIT(13) -#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | \ - HPET_T1_CMP_SETTLING) -#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | \ - HPET_T0_CMP_SETTLING) -#define HPET_ANY_SETTLING (BIT(12) - 1) +#define HPET_CTRL_STATUS REG32(ISH_HPET_BASE + 0x160) +#define HPET_INT_STATUS_SETTLING BIT(1) +#define HPET_MAIN_COUNTER_SETTLING (BIT(2) | BIT(3)) +#define HPET_T0_CAP_SETTLING BIT(4) +#define HPET_T1_CAP_SETTLING BIT(5) +#define HPET_T0_CMP_SETTLING (BIT(7) | BIT(8)) +#define HPET_T1_CMP_SETTLING BIT(9) +#define HPET_MAIN_COUNTER_VALID BIT(13) +#define HPET_T1_SETTLING (HPET_T1_CAP_SETTLING | HPET_T1_CMP_SETTLING) +#define HPET_T0_SETTLING (HPET_T0_CAP_SETTLING | HPET_T0_CMP_SETTLING) +#define HPET_ANY_SETTLING (BIT(12) - 1) #if defined(CHIP_FAMILY_ISH3) -#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */ +#define ISH_HPET_CLK_FREQ 12000000 /* 12 MHz clock */ #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) -#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */ +#define ISH_HPET_CLK_FREQ 32768 /* 32.768 KHz clock */ #endif #endif /* __CROS_EC_HPET_H */ -- cgit v1.2.1 From 7f86894bc728ee5ae921f2c5721bec9db21a0623 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:45 -0600 Subject: include/driver/temp_sensor/pct2075.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I92250a4af94f79a81e8509e3ada49926a4a304eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730255 Reviewed-by: Jeremy Bettis --- include/driver/temp_sensor/pct2075.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/driver/temp_sensor/pct2075.h b/include/driver/temp_sensor/pct2075.h index c09d0e383c..5493e9e55c 100644 --- a/include/driver/temp_sensor/pct2075.h +++ b/include/driver/temp_sensor/pct2075.h @@ -17,10 +17,10 @@ #define PCT2075_I2C_ADDR_FLAGS6 (0x4E | I2C_FLAG_BIG_ENDIAN) #define PCT2075_I2C_ADDR_FLAGS7 (0x4F | I2C_FLAG_BIG_ENDIAN) -#define PCT2075_REG_TEMP 0x00 -#define PCT2075_REG_CONF 0x01 -#define PCT2075_REG_THYST 0x02 -#define PCT2075_REG_TOS 0x03 +#define PCT2075_REG_TEMP 0x00 +#define PCT2075_REG_CONF 0x01 +#define PCT2075_REG_THYST 0x02 +#define PCT2075_REG_TOS 0x03 /* * I2C port and address information for all the board PCT2075 sensors should be -- cgit v1.2.1 From 59d6cc9903c8138d307824a5a1e7fadb64abb2dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:22 -0600 Subject: core/host/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8a0ceed91c2aee9b96bac7f913603be8562fcd36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729836 Reviewed-by: Jeremy Bettis --- core/host/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/host/atomic.h b/core/host/atomic.h index a8d6882d0e..8e84406f1c 100644 --- a/core/host/atomic.h +++ b/core/host/atomic.h @@ -40,4 +40,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) { return __atomic_fetch_and(addr, bits, __ATOMIC_SEQ_CST); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 637c40a1b1cb532aad59f0d65ccdf3b8091b5a4d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:13:32 -0600 Subject: include/mkbp_event.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id3442cff02f523e60eea9623b9a26f111d3e2cb8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730354 Reviewed-by: Jeremy Bettis --- include/mkbp_event.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/include/mkbp_event.h b/include/mkbp_event.h index d9237dd33b..8173242497 100644 --- a/include/mkbp_event.h +++ b/include/mkbp_event.h @@ -51,11 +51,10 @@ struct mkbp_event_source { #ifdef CONFIG_PLATFORM_EC_MKBP_EVENT #include "zephyr_mkbp_event.h" #else -#define DECLARE_EVENT_SOURCE(type, func) \ - const struct mkbp_event_source __keep \ - __no_sanitize_address _evt_src_##type \ - __attribute__((section(".rodata.evtsrcs"))) \ - = {type, func} +#define DECLARE_EVENT_SOURCE(type, func) \ + const struct mkbp_event_source __keep __no_sanitize_address \ + _evt_src_##type \ + __attribute__((section(".rodata.evtsrcs"))) = { type, func } #endif -#endif /* __CROS_EC_MKBP_EVENT_H */ +#endif /* __CROS_EC_MKBP_EVENT_H */ -- cgit v1.2.1 From f5b67dd7e18de42df492b40e839562da5acc74ae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:27 -0600 Subject: common/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9fba1aff3233fcf436913cd853b36bea7ee9bbb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729670 Reviewed-by: Jeremy Bettis --- common/main.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/common/main.c b/common/main.c index 93e68fb1ca..2604637ad5 100644 --- a/common/main.c +++ b/common/main.c @@ -40,8 +40,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_SYSTEM, outstr) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) test_mockable __keep int main(void) { @@ -182,12 +182,12 @@ test_mockable __keep int main(void) if (IS_ENABLED(CONFIG_EEPROM_CBI_WP) && system_is_locked()) cbi_latch_eeprom_wp(); - /* - * Keyboard scan init/Button init can set recovery events to - * indicate to host entry into recovery mode. Before this is - * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be initialized - * correctly. - */ + /* + * Keyboard scan init/Button init can set recovery events to + * indicate to host entry into recovery mode. Before this is + * done, LPC_HOST_EVENT_ALWAYS_REPORT mask needs to be + * initialized correctly. + */ #ifdef CONFIG_HOSTCMD_X86 lpc_init_mask(); #endif @@ -228,9 +228,9 @@ test_mockable __keep int main(void) #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON | CONFIG_VOLUME_BUTTONS) */ /* Make sure recovery boot won't be paused. */ - if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) - && system_is_manual_recovery() - && (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) { + if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) && + system_is_manual_recovery() && + (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) { CPRINTS("Clear AP_IDLE for recovery mode"); system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE); } @@ -270,15 +270,14 @@ test_mockable __keep int main(void) rwsig_jump_now(); } } -#endif /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */ +#endif /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */ /* * Disable I2C raw mode for the ports which needed pre-task i2c * transactions as the task is about to start and the I2C can resume * to event based transactions. */ - if (IS_ENABLED(CONFIG_I2C_BITBANG) && - IS_ENABLED(CONFIG_I2C_CONTROLLER)) + if (IS_ENABLED(CONFIG_I2C_BITBANG) && IS_ENABLED(CONFIG_I2C_CONTROLLER)) enable_i2c_raw_mode(false); /* -- cgit v1.2.1 From aea3a67eacef50202a753743fb4853e50ef43c80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:49 -0600 Subject: board/host/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62a9cf47d8e839fabe030b42fbc43ddffa4d4bc9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728508 Reviewed-by: Jeremy Bettis --- board/host/charger.c | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/board/host/charger.c b/board/host/charger.c index 4db1f44351..9249b1d591 100644 --- a/board/host/charger.c +++ b/board/host/charger.c @@ -12,15 +12,15 @@ #include "util.h" static const struct charger_info mock_charger_info = { - .name = "MockCharger", - .voltage_max = 19200, - .voltage_min = 1024, + .name = "MockCharger", + .voltage_max = 19200, + .voltage_min = 1024, .voltage_step = 16, - .current_max = 8192, - .current_min = 128, + .current_max = 8192, + .current_min = 128, .current_step = 128, - .input_current_max = 8064, - .input_current_min = 128, + .input_current_max = 8064, + .input_current_min = 128, .input_current_step = 128, }; @@ -37,7 +37,6 @@ static const struct charger_info *mock_get_info(int chgnum) return &mock_charger_info; } - static enum ec_error_list mock_get_status(int chgnum, int *status) { *status = CHARGER_LEVEL_2; @@ -47,7 +46,6 @@ static enum ec_error_list mock_get_status(int chgnum, int *status) return EC_SUCCESS; } - static enum ec_error_list mock_set_mode(int chgnum, int mode) { if (mode & CHARGE_FLAG_INHIBIT_CHARGE) @@ -57,14 +55,12 @@ static enum ec_error_list mock_set_mode(int chgnum, int mode) return EC_SUCCESS; } - static enum ec_error_list mock_get_current(int chgnum, int *current) { *current = mock_current; return EC_SUCCESS; } - static enum ec_error_list mock_set_current(int chgnum, int current) { const struct charger_info *info = mock_get_info(chgnum); @@ -86,7 +82,6 @@ static enum ec_error_list mock_get_voltage(int chgnum, int *voltage) return EC_SUCCESS; } - static enum ec_error_list mock_set_voltage(int chgnum, int voltage) { mock_voltage = voltage; @@ -94,27 +89,23 @@ static enum ec_error_list mock_set_voltage(int chgnum, int voltage) return EC_SUCCESS; } - static enum ec_error_list mock_get_option(int chgnum, int *option) { *option = mock_option; return EC_SUCCESS; } - static enum ec_error_list mock_set_option(int chgnum, int option) { mock_option = option; return EC_SUCCESS; } - static enum ec_error_list mock_manufacturer_id(int chgnum, int *id) { return EC_SUCCESS; } - static enum ec_error_list mock_device_id(int chgnum, int *id) { return EC_SUCCESS; @@ -127,7 +118,6 @@ static enum ec_error_list mock_get_input_current_limit(int chgnum, return EC_SUCCESS; } - static enum ec_error_list mock_set_input_current_limit(int chgnum, int current) { const struct charger_info *info = mock_get_info(chgnum); @@ -144,7 +134,6 @@ static enum ec_error_list mock_set_input_current_limit(int chgnum, int current) return EC_SUCCESS; } - static enum ec_error_list mock_post_init(int chgnum) { mock_current = mock_input_current = CONFIG_CHARGER_INPUT_CURRENT; -- cgit v1.2.1 From dd9c35844c9d8a32f8cc4f86a38fb10b8b0a3760 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:51 -0600 Subject: driver/touchpad_gt7288.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iad727d232636d4deb3cb2157e12c202b02f4b1c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730148 Reviewed-by: Jeremy Bettis --- driver/touchpad_gt7288.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/driver/touchpad_gt7288.c b/driver/touchpad_gt7288.c index ac05b88323..deb4665e09 100644 --- a/driver/touchpad_gt7288.c +++ b/driver/touchpad_gt7288.c @@ -16,7 +16,7 @@ /* Define this to enable various warning messages during report parsing. */ #undef DEBUG_CHECKS -#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_TOUCHPAD, format, ##args) #define GT7288_I2C_ADDR_FLAGS 0x14 @@ -44,9 +44,8 @@ static int gt7288_read_desc(uint16_t register_id, uint8_t *data, size_t max_length) { - uint8_t reg_bytes[] = { - register_id & 0xFF, (register_id & 0xFF00) >> 8 - }; + uint8_t reg_bytes[] = { register_id & 0xFF, + (register_id & 0xFF00) >> 8 }; return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS, reg_bytes, sizeof(reg_bytes), data, max_length); } @@ -88,8 +87,8 @@ static void gt7288_translate_contact(const uint8_t *data, static int gt7288_read(uint8_t *data, size_t max_length) { - return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS, - NULL, 0, data, max_length); + return i2c_xfer(CONFIG_TOUCHPAD_I2C_PORT, GT7288_I2C_ADDR_FLAGS, NULL, + 0, data, max_length); } int gt7288_read_ptp_report(struct gt7288_ptp_report *report) @@ -102,8 +101,8 @@ int gt7288_read_ptp_report(struct gt7288_ptp_report *report) if (data[10] > GT7288_MAX_CONTACTS) { if (IS_ENABLED(DEBUG_CHECKS)) - CPRINTS("ERROR: too many contacts (%d > %d).", - data[10], GT7288_MAX_CONTACTS); + CPRINTS("ERROR: too many contacts (%d > %d).", data[10], + GT7288_MAX_CONTACTS); return EC_ERROR_HW_INTERNAL; } report->num_contacts = data[10]; @@ -150,8 +149,7 @@ static int command_gt7288_read_desc(int argc, char **argv) ccprintf("\n"); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc, - "register", +DECLARE_CONSOLE_COMMAND(gt7288_desc, command_gt7288_read_desc, "register", "Read a descriptor on the GT7288"); static int command_gt7288_read_report_descriptor(int argc, char **argv) -- cgit v1.2.1 From 77f12b39d58c3b7a7dd4c2f592975b4e838e2321 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:38 -0600 Subject: board/sasukette/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie2195cd9839c08ec250fd713a459c0733bb62ae9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728900 Reviewed-by: Jeremy Bettis --- board/sasukette/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/sasukette/cbi_ssfc.h b/board/sasukette/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/sasukette/cbi_ssfc.h +++ b/board/sasukette/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 2333b18a3c3929fd36c4111d3016bfd172f8d327 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:54 -0600 Subject: board/kano/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib17108e32a9a97af0300682310b584a750006e36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728483 Reviewed-by: Jeremy Bettis --- board/kano/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kano/keyboard.c b/board/kano/keyboard.c index 38e96620e2..9e9182331c 100644 --- a/board/kano/keyboard.c +++ b/board/kano/keyboard.c @@ -41,8 +41,8 @@ static const struct ec_response_keybd_config kano_kb = { }, .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &kano_kb; } -- cgit v1.2.1 From a3b6972673da5a0e91bb4d5f85b961dd5df60a69 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:57 -0600 Subject: board/dood/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9b4a48fec46cffcdea6d3ff592b593c56d946587 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728234 Reviewed-by: Jeremy Bettis --- board/dood/board.h | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/board/dood/board.h b/board/dood/board.h index 5b9b55af1b..be3262dd55 100644 --- a/board/dood/board.h +++ b/board/dood/board.h @@ -16,13 +16,13 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD /* I2C bus configuraiton */ -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define CONFIG_LED_COMMON /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT /* Sensors without hardware FIFO are in forced mode */ @@ -32,8 +32,7 @@ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE @@ -60,7 +59,6 @@ /* prevent pd reset when battery soc under 2% */ #define CONFIG_USB_PD_RESET_MIN_BATT_SOC 2 - #ifndef __ASSEMBLER__ /* support factory keyboard test */ @@ -70,10 +68,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -85,12 +83,7 @@ enum temp_sensor_id { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 621caa01f4cca56c36cc5ac10a4c8b932918dd16 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:29 -0600 Subject: driver/retimer/pi3dpx1207.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10061277a4a013b273878aee58b1c7e13849941d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730044 Reviewed-by: Jeremy Bettis --- driver/retimer/pi3dpx1207.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/driver/retimer/pi3dpx1207.h b/driver/retimer/pi3dpx1207.h index ec3c9b42bc..4a66273f4c 100644 --- a/driver/retimer/pi3dpx1207.h +++ b/driver/retimer/pi3dpx1207.h @@ -9,35 +9,35 @@ #ifndef __CROS_EC_USB_RETIMER_PI3PDX1207_H #define __CROS_EC_USB_RETIMER_PI3PDX1207_H -#define PI3DPX1207_I2C_ADDR_FLAGS 0x57 -#define PI3DPX1207_NUM_REGISTERS 32 +#define PI3DPX1207_I2C_ADDR_FLAGS 0x57 +#define PI3DPX1207_NUM_REGISTERS 32 /* Register Offset 0 - Revision and Vendor ID */ -#define PI3DPX1207_VID_OFFSET 0 +#define PI3DPX1207_VID_OFFSET 0 -#define PI3DPX1207B_VID 0x03 -#define PI3DPX1207C_VID 0x13 +#define PI3DPX1207B_VID 0x03 +#define PI3DPX1207C_VID 0x13 /* Register Offset 1 - Device Type/ID */ -#define PI3DPX1207_DID_OFFSET 1 +#define PI3DPX1207_DID_OFFSET 1 -#define PI3DPX1207_DID_ACTIVE_MUX 0x11 +#define PI3DPX1207_DID_ACTIVE_MUX 0x11 /* Register Offset 3 - Mode Control */ -#define PI3DPX1207_MODE_OFFSET 3 +#define PI3DPX1207_MODE_OFFSET 3 -#define PI3DPX1207_MODE_WATCHDOG_EN 0x02 +#define PI3DPX1207_MODE_WATCHDOG_EN 0x02 -#define PI3DPX1207B_MODE_GEN_APP_EN 0x08 +#define PI3DPX1207B_MODE_GEN_APP_EN 0x08 -#define PI3DPX1207_MODE_CONF_SAFE 0x00 -#define PI3DPX1207_MODE_CONF_DP 0x20 -#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30 -#define PI3DPX1207_MODE_CONF_USB 0x40 -#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50 -#define PI3DPX1207_MODE_CONF_USB_DP 0x60 -#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70 -#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0 +#define PI3DPX1207_MODE_CONF_SAFE 0x00 +#define PI3DPX1207_MODE_CONF_DP 0x20 +#define PI3DPX1207_MODE_CONF_DP_FLIP 0x30 +#define PI3DPX1207_MODE_CONF_USB 0x40 +#define PI3DPX1207_MODE_CONF_USB_FLIP 0x50 +#define PI3DPX1207_MODE_CONF_USB_DP 0x60 +#define PI3DPX1207_MODE_CONF_USB_DP_FLIP 0x70 +#define PI3DPX1207_MODE_CONF_USB_SUPER 0xC0 /* Supported USB retimer drivers */ extern const struct usb_mux_driver pi3dpx1207_usb_retimer; -- cgit v1.2.1 From c8443bddc4b19bb5f7ce0a8b8d9a254a4ebafb39 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:31 -0600 Subject: board/haboki/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8dccb44f050ae838b7452e1306c86da8c5740fbc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728446 Reviewed-by: Jeremy Bettis --- board/haboki/led.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/haboki/led.c b/board/haboki/led.c index 3e3a61edc2..358df00c72 100644 --- a/board/haboki/led.c +++ b/board/haboki/led.c @@ -18,10 +18,8 @@ #define POWER_LED_ON 0 #define POWER_LED_OFF 1 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -29,7 +27,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -127,9 +125,9 @@ static void led_set_battery(void) */ if (get_cbi_fw_config_tablet_mode() == TABLET_MODE_ABSENT) { if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - charge_get_state() != PWR_STATE_CHARGE) { - led_set_color_battery(power_ticks++ & 0x2 ? - LED_WHITE : LED_OFF); + charge_get_state() != PWR_STATE_CHARGE) { + led_set_color_battery(power_ticks++ & 0x2 ? LED_WHITE : + LED_OFF); return; } } @@ -158,8 +156,8 @@ static void led_set_battery(void) led_set_color_battery(LED_OFF); break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % 0x2) ? LED_WHITE : LED_OFF); + led_set_color_battery((battery_ticks % 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_WHITE); @@ -186,8 +184,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) - led_set_color_power( - (power_tick & 0x2) ? LED_WHITE : LED_OFF); + led_set_color_power((power_tick & 0x2) ? LED_WHITE : LED_OFF); else led_set_color_power(LED_OFF); } -- cgit v1.2.1 From cf0778cb32596557423f79e17688f793fa53ea9a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:44 -0600 Subject: include/common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37388e444566f214bddf0834fd9cd4675c281e90 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730229 Reviewed-by: Jeremy Bettis --- include/common.h | 87 +++++++++++++++++++++++++++----------------------------- 1 file changed, 42 insertions(+), 45 deletions(-) diff --git a/include/common.h b/include/common.h index 02989c692b..74c229261c 100644 --- a/include/common.h +++ b/include/common.h @@ -46,7 +46,7 @@ * #define BAZ CONCAT2(BAR, FOO) * Will evaluate to BAR1, which then evaluates to 42. */ -#define CONCAT_STAGE_1(w, x, y, z) w ## x ## y ## z +#define CONCAT_STAGE_1(w, x, y, z) w##x##y##z #define CONCAT2(w, x) CONCAT_STAGE_1(w, x, , ) #define CONCAT3(w, x, y) CONCAT_STAGE_1(w, x, y, ) #define CONCAT4(w, x, y, z) CONCAT_STAGE_1(w, x, y, z) @@ -58,20 +58,20 @@ * is safe with regards to using nested macros and defined arguments. */ #ifndef CONFIG_ZEPHYR -#define STRINGIFY0(name) #name -#define STRINGIFY(name) STRINGIFY0(name) -#endif /* CONFIG_ZEPHYR */ +#define STRINGIFY0(name) #name +#define STRINGIFY(name) STRINGIFY0(name) +#endif /* CONFIG_ZEPHYR */ /* Macros to access registers */ #define REG64_ADDR(addr) ((volatile uint64_t *)(addr)) #define REG32_ADDR(addr) ((volatile uint32_t *)(addr)) #define REG16_ADDR(addr) ((volatile uint16_t *)(addr)) -#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) +#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) #define REG64(addr) (*REG64_ADDR(addr)) #define REG32(addr) (*REG32_ADDR(addr)) #define REG16(addr) (*REG16_ADDR(addr)) -#define REG8(addr) (*REG8_ADDR(addr)) +#define REG8(addr) (*REG8_ADDR(addr)) /* * Define __aligned(n) and __packed if someone hasn't beat us to it. Linux @@ -184,7 +184,7 @@ */ #define __override_proto #define __override -#define __overridable __attribute__((weak)) +#define __overridable __attribute__((weak)) /* * Macros for combining bytes into larger integers. _LE and _BE signify little @@ -198,30 +198,29 @@ #define UINT32_FROM_BYTES(lsb, byte1, byte2, msb) \ ((lsb) | (byte1) << 8 | (byte2) << 16 | (msb) << 24) -#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \ +#define UINT32_FROM_BYTE_ARRAY_LE(data, lsb_index) \ UINT32_FROM_BYTES((data)[(lsb_index)], (data)[(lsb_index) + 1], \ (data)[(lsb_index) + 2], (data)[(lsb_index) + 3]) -#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \ +#define UINT32_FROM_BYTE_ARRAY_BE(data, msb_index) \ UINT32_FROM_BYTES((data)[(msb_index) + 3], (data)[(msb_index) + 2], \ (data)[(msb_index) + 1], (data)[(msb_index)]) /* There isn't really a better place for this */ #define C_TO_K(temp_c) ((temp_c) + 273) -#define K_TO_C(temp_c) ((temp_c) - 273) +#define K_TO_C(temp_c) ((temp_c)-273) /* * round_divide is part of math_utils, so you may need to import math_utils.h * and link math_utils.o if you use the following macros. */ #define CELSIUS_TO_DECI_KELVIN(temp_c) \ (round_divide(CELSIUS_TO_MILLI_KELVIN(temp_c), 100)) -#define DECI_KELVIN_TO_CELSIUS(temp_dk) \ - (MILLI_KELVIN_TO_CELSIUS((temp_dk) * 100)) -#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk) - 273150) +#define DECI_KELVIN_TO_CELSIUS(temp_dk) (MILLI_KELVIN_TO_CELSIUS((temp_dk)*100)) +#define MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk) ((temp_mk)-273150) #define MILLI_CELSIUS_TO_MILLI_KELVIN(temp_mc) ((temp_mc) + 273150) #define MILLI_KELVIN_TO_KELVIN(temp_mk) (round_divide((temp_mk), 1000)) -#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k) * 1000) +#define KELVIN_TO_MILLI_KELVIN(temp_k) ((temp_k)*1000) #define CELSIUS_TO_MILLI_KELVIN(temp_c) \ - (MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c) * 1000)) + (MILLI_CELSIUS_TO_MILLI_KELVIN((temp_c)*1000)) #define MILLI_KELVIN_TO_CELSIUS(temp_mk) \ (round_divide(MILLI_KELVIN_TO_MILLI_CELSIUS(temp_mk), 1000)) @@ -229,14 +228,15 @@ * TARGET_WITH_MARGIN(X, 5) returns X' where X' * 100.5% is almost equal to * but does not exceed X. */ #define TARGET_WITH_MARGIN(target, tenths_percent) \ - (((target) * 1000) / (1000 + (tenths_percent))) + (((target)*1000) / (1000 + (tenths_percent))) /* Call a function, and return the error value unless it returns EC_SUCCESS. */ -#define RETURN_ERROR(fn) do { \ - int error = (fn); \ - if (error != EC_SUCCESS) \ - return error; \ -} while (0) +#define RETURN_ERROR(fn) \ + do { \ + int error = (fn); \ + if (error != EC_SUCCESS) \ + return error; \ + } while (0) /* * Define test_mockable and test_mockable_static for mocking @@ -391,12 +391,12 @@ enum ec_error_list { * undefined, rather than defined to something else. This usually * involves tricks with __builtin_strcmp. */ -#define __cfg_select(cfg, empty, otherwise) \ +#define __cfg_select(cfg, empty, otherwise) \ __cfg_select_1(cfg, empty, otherwise) #define __cfg_select_placeholder_ _, -#define __cfg_select_1(value, empty, otherwise) \ +#define __cfg_select_1(value, empty, otherwise) \ __cfg_select_2(__cfg_select_placeholder_##value, empty, otherwise) -#define __cfg_select_2(arg1_or_junk, empty, otherwise) \ +#define __cfg_select_2(arg1_or_junk, empty, otherwise) \ __cfg_select_3(arg1_or_junk _, empty, otherwise) #define __cfg_select_3(_ignore1, _ignore2, select, ...) select @@ -405,13 +405,10 @@ enum ec_error_list { * handling the __builtin_strcmp trickery where a BUILD_ASSERT is * appropriate in the context. */ -#define __cfg_select_build_assert(cfg, value, empty, undef) \ - __cfg_select( \ - value, \ - empty, \ - BUILD_ASSERT( \ - __builtin_strcmp(cfg, #value) == 0); \ - undef) +#define __cfg_select_build_assert(cfg, value, empty, undef) \ + __cfg_select(value, empty, \ + BUILD_ASSERT(__builtin_strcmp(cfg, #value) == 0); \ + undef) /* * Attribute for generating an error if a function is used. @@ -436,16 +433,16 @@ enum ec_error_list { * technique requires that the optimizer be enabled so it can remove * the undefined function call. */ -#define __config_enabled(cfg, value) \ - __cfg_select( \ - value, 1, ({ \ - int __undefined = __builtin_strcmp(cfg, #value) == 0; \ - extern int IS_ENABLED_BAD_ARGS(void) __error( \ - cfg " must be , or not defined."); \ - if (!__undefined) \ - IS_ENABLED_BAD_ARGS(); \ - 0; \ - })) +#define __config_enabled(cfg, value) \ + __cfg_select(value, 1, ({ \ + int __undefined = \ + __builtin_strcmp(cfg, #value) == 0; \ + extern int IS_ENABLED_BAD_ARGS(void) __error( \ + cfg " must be , or not defined."); \ + if (!__undefined) \ + IS_ENABLED_BAD_ARGS(); \ + 0; \ + })) /** * Checks if a config option is enabled or disabled @@ -478,7 +475,7 @@ enum ec_error_list { * if the config option is enabled by Zephyr's definition. */ #define IS_ENABLED(option) __cfg_select(option, 1, Z_IS_ENABLED1(option)) -#endif /* CONFIG_ZEPHYR */ +#endif /* CONFIG_ZEPHYR */ /** * Makes a global variable static when a config option is enabled, @@ -490,7 +487,7 @@ enum ec_error_list { * should be defined to nothing or undefined. */ #ifndef CONFIG_ZEPHYR -#define STATIC_IF(option) \ +#define STATIC_IF(option) \ __cfg_select_build_assert(#option, option, static, extern) #else /* @@ -511,7 +508,7 @@ enum ec_error_list { * config option. */ #ifndef CONFIG_ZEPHYR -#define STATIC_IF_NOT(option) \ +#define STATIC_IF_NOT(option) \ __cfg_select_build_assert(#option, option, extern, static) #else /* @@ -522,4 +519,4 @@ enum ec_error_list { __cfg_select(option, extern, COND_CODE_1(option, (extern), (static))) #endif /* CONFIG_ZEPHYR */ -#endif /* __CROS_EC_COMMON_H */ +#endif /* __CROS_EC_COMMON_H */ -- cgit v1.2.1 From ce8dbc2d9030fd15e649d3be208606ae3c6984ee Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:43 -0600 Subject: zephyr/test/drivers/src/stubs.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic9abed527540efd9e131e64b0e5ac1f5a3ca64f2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730945 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/stubs.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/zephyr/test/drivers/src/stubs.c b/zephyr/test/drivers/src/stubs.c index a547198217..6ca43eb6b9 100644 --- a/zephyr/test/drivers/src/stubs.c +++ b/zephyr/test/drivers/src/stubs.c @@ -30,8 +30,8 @@ #include LOG_MODULE_REGISTER(stubs); -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* All of these definitions are just to get the test to link. None of these * functions are useful or behave as they should. Please remove them once the @@ -55,8 +55,7 @@ BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (!is_real_port && port != CHARGE_PORT_NONE) @@ -84,7 +83,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - CPRINTS("New charge port: p%d", port); /* @@ -117,7 +115,7 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } struct tcpc_config_t tcpc_config[] = { @@ -256,13 +254,13 @@ uint16_t tcpc_get_alert_status(void) */ if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_int_odl))) { if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(usb_c0_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_0; } if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_int_odl))) { if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l)) != 0) + GPIO_DT_FROM_NODELABEL(usb_c1_tcpc_rst_l)) != 0) status |= PD_STATUS_TCPC_ALERT_1; } -- cgit v1.2.1 From 4f69afa5bf4a59f8f4cf399838f89d9f4b18d6be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:01 -0600 Subject: util/lock/locks.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c04b69a40142d0141f08cf4f84a1384efecc41d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730652 Reviewed-by: Jeremy Bettis --- util/lock/locks.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/lock/locks.h b/util/lock/locks.h index 6875d91454..7584378d3a 100644 --- a/util/lock/locks.h +++ b/util/lock/locks.h @@ -31,8 +31,8 @@ #ifndef __UTIL_LOCKS_H #define __UTIL_LOCKS_H -#define SYSTEM_LOCKFILE_DIR "/run/lock" -#define LOCKFILE_NAME "firmware_utility_lock" -#define CROS_EC_LOCKFILE_NAME "cros_ec_lock" +#define SYSTEM_LOCKFILE_DIR "/run/lock" +#define LOCKFILE_NAME "firmware_utility_lock" +#define CROS_EC_LOCKFILE_NAME "cros_ec_lock" #endif /* __UTIL_LOCKS_H */ -- cgit v1.2.1 From 7c57226799b1a275435391e4a90d3fafb3986280 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:27 -0600 Subject: baseboard/mtscp-rv32i/vdec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9975d19d1a8b0496a5f29cda711da8556b0a9832 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727930 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/vdec.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/mtscp-rv32i/vdec.h b/baseboard/mtscp-rv32i/vdec.h index cdc16ba9e0..ce07e81352 100644 --- a/baseboard/mtscp-rv32i/vdec.h +++ b/baseboard/mtscp-rv32i/vdec.h @@ -19,7 +19,7 @@ struct vdec_msg { unsigned char msg[48]; }; BUILD_ASSERT(member_size(struct vdec_msg, msg) <= - CONFIG_IPC_SHARED_OBJ_BUF_SIZE); + CONFIG_IPC_SHARED_OBJ_BUF_SIZE); /* Functions provided by private overlay. */ void vdec_core_msg_handler(void *msg); -- cgit v1.2.1 From a1f6c2019b44aed7194ea1b3e56d1c89d4aa65d0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:08 -0600 Subject: include/byteorder.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib62fb12ef45e6f498d3d96439654baecc1dc0639 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730218 Reviewed-by: Jeremy Bettis --- include/byteorder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/byteorder.h b/include/byteorder.h index 8cfd810e54..b385dbd20c 100644 --- a/include/byteorder.h +++ b/include/byteorder.h @@ -8,4 +8,4 @@ #include -#endif /* __EC_INCLUDE_BYTEORDER_H */ +#endif /* __EC_INCLUDE_BYTEORDER_H */ -- cgit v1.2.1 From 20b6741321ebe3b2b1bfb32961d953f5accb45b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:14 -0600 Subject: board/coffeecake/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic495c045861ec18e0f20bf9401a55481c1429dcb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728171 Reviewed-by: Jeremy Bettis --- board/coffeecake/usb_pd_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/coffeecake/usb_pd_config.h b/board/coffeecake/usb_pd_config.h index e2c1dbb2db..d4543d64f7 100644 --- a/board/coffeecake/usb_pd_config.h +++ b/board/coffeecake/usb_pd_config.h @@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -100,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity) * use the right comparator : CC1 -> PA1 (COMP1 INP) * use VrefInt / 2 as INM (about 600mV) */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; } /* Initialize pins used for TX and put them in Hi-Z */ @@ -136,7 +136,7 @@ static inline int pd_adc_read(int port, int cc) * Check HOST_HIGH Rp setting. * Return 3300mV on host mode. */ - if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2*5))) == (1 << (2*5))) + if ((STM32_GPIO_MODER(GPIO_B) & (3 << (2 * 5))) == (1 << (2 * 5))) return 3300; else return 0; -- cgit v1.2.1 From 2902808f7f87f3bc690cec6b9a4a91453b3f3596 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:27 -0600 Subject: board/drobit/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c0eea7e66d41198bf767f859080ee7fd3cbabde Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728246 Reviewed-by: Jeremy Bettis --- board/drobit/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/drobit/led.c b/board/drobit/led.c index 47c3cca5b7..5aae69adee 100644 --- a/board/drobit/led.c +++ b/board/drobit/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 39eac5b29d576da4025df35ec7dbba1a3f64ab92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:03 -0600 Subject: common/mock/tcpm_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I32df5b6657f9924983d4ec08a9bcc8414e97a17a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729677 Reviewed-by: Jeremy Bettis --- common/mock/tcpm_mock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/mock/tcpm_mock.c b/common/mock/tcpm_mock.c index 2c212cf8c9..80cff1d653 100644 --- a/common/mock/tcpm_mock.c +++ b/common/mock/tcpm_mock.c @@ -31,7 +31,7 @@ int tcpm_dequeue_message(int port, uint32_t *payload, int *header) *header = mock_tcpm[port].mock_header; memcpy(payload, mock_tcpm[port].mock_rx_chk_buf, - sizeof(mock_tcpm[port].mock_rx_chk_buf)); + sizeof(mock_tcpm[port].mock_rx_chk_buf)); return EC_SUCCESS; } @@ -51,7 +51,7 @@ void mock_tcpm_reset(void) { int port; - for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) mock_tcpm[port].mock_has_pending_message = 0; } @@ -65,7 +65,7 @@ void mock_tcpm_rx_msg(int port, uint16_t header, int cnt, const uint32_t *data) if (cnt > 0) { int idx; - for (idx = 0 ; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE) ; ++idx) + for (idx = 0; (idx < cnt) && (idx < MOCK_CHK_BUF_SIZE); ++idx) mock_tcpm[port].mock_rx_chk_buf[idx] = data[idx]; } mock_tcpm[port].mock_has_pending_message = 1; -- cgit v1.2.1 From 92e833647ea40e21217ab42d2292caffc2c4d0a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:08 -0600 Subject: baseboard/intelrvp/ite_ec.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11c7966ca69e9f1bf635e02dc093b336b55482f0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727899 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/ite_ec.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/baseboard/intelrvp/ite_ec.h b/baseboard/intelrvp/ite_ec.h index c773a48b21..4e28379b5b 100644 --- a/baseboard/intelrvp/ite_ec.h +++ b/baseboard/intelrvp/ite_ec.h @@ -13,13 +13,13 @@ #define CONFIG_IT83XX_VCC_1P8V /* ADC channels */ -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH13 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH15 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH6 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH1 #ifdef CONFIG_USBC_VCONN - #define CONFIG_USBC_VCONN_SWAP - /* delay to turn on/off vconn */ +#define CONFIG_USBC_VCONN_SWAP +/* delay to turn on/off vconn */ #endif #endif /* __CROS_EC_ITE_EC_H */ -- cgit v1.2.1 From aa4c9a49ce7e5732e8828303711452e32fa8dd9d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:12 -0600 Subject: include/motion_sense.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia73e1931cf9aaada1535cea56e6cf60148d972b2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730369 Reviewed-by: Jeremy Bettis --- include/motion_sense.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/include/motion_sense.h b/include/motion_sense.h index 1f2e912ce5..4545d388d0 100644 --- a/include/motion_sense.h +++ b/include/motion_sense.h @@ -39,7 +39,6 @@ enum sensor_config { #define SENSOR_ACTIVE_S0_S3 (SENSOR_ACTIVE_S3 | SENSOR_ACTIVE_S0) #define SENSOR_ACTIVE_S0_S3_S5 (SENSOR_ACTIVE_S0_S3 | SENSOR_ACTIVE_S5) - /* * Events layout: * 0 8 10 @@ -49,29 +48,27 @@ enum sensor_config { */ /* First 8 events for sensor interrupt lines */ -#define TASK_EVENT_MOTION_INTERRUPT_NUM 8 +#define TASK_EVENT_MOTION_INTERRUPT_NUM 8 #define TASK_EVENT_MOTION_INTERRUPT_MASK \ ((1 << TASK_EVENT_MOTION_INTERRUPT_NUM) - 1) -#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \ - BUILD_CHECK_INLINE( \ - TASK_EVENT_CUSTOM_BIT(_sensor_id), \ - _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM) +#define TASK_EVENT_MOTION_SENSOR_INTERRUPT(_sensor_id) \ + BUILD_CHECK_INLINE(TASK_EVENT_CUSTOM_BIT(_sensor_id), \ + _sensor_id < TASK_EVENT_MOTION_INTERRUPT_NUM) /* Internal events to motion sense task.*/ #define TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT TASK_EVENT_MOTION_INTERRUPT_NUM -#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2 +#define TASK_EVENT_MOTION_INTERNAL_EVENT_NUM 2 #define TASK_EVENT_MOTION_FLUSH_PENDING \ TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT) #define TASK_EVENT_MOTION_ODR_CHANGE \ TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_INTERNAL_EVENT + 1) /* Activity events */ -#define TASK_EVENT_MOTION_FIRST_SW_EVENT \ +#define TASK_EVENT_MOTION_FIRST_SW_EVENT \ (TASK_EVENT_MOTION_INTERRUPT_NUM + TASK_EVENT_MOTION_INTERNAL_EVENT_NUM) -#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \ - (TASK_EVENT_CUSTOM_BIT( \ - TASK_EVENT_MOTION_FIRST_SW_EVENT + (_activity_id))) - +#define TASK_EVENT_MOTION_ACTIVITY_INTERRUPT(_activity_id) \ + (TASK_EVENT_CUSTOM_BIT(TASK_EVENT_MOTION_FIRST_SW_EVENT + \ + (_activity_id))) #define ROUND_UP_FLAG ((uint32_t)BIT(31)) #define BASE_ODR(_odr) ((_odr) & ~ROUND_UP_FLAG) @@ -87,13 +84,13 @@ enum sensor_config { * use peripheral addressing, it is up to the driver to use this * field as it sees fit */ -#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr) -#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI) +#define ACCEL_MK_I2C_ADDR_FLAGS(addr) (addr) +#define ACCEL_MK_SPI_ADDR_FLAGS(addr) ((addr) | I2C_FLAG_ADDR_IS_SPI) -#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags)) -#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags) & I2C_ADDR_MASK) +#define ACCEL_GET_I2C_ADDR(addr_flags) (I2C_STRIP_FLAGS(addr_flags)) +#define ACCEL_GET_SPI_ADDR(addr_flags) ((addr_flags)&I2C_ADDR_MASK) -#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags) & I2C_FLAG_ADDR_IS_SPI) +#define ACCEL_ADDR_IS_SPI(addr_flags) ((addr_flags)&I2C_FLAG_ADDR_IS_SPI) /* * Define the frequency to use in max_frequency based on the maximal frequency @@ -101,9 +98,10 @@ enum sensor_config { * Return a frequency the sensor supports. * Trigger a compilation error when the EC way to slow for the sensor. */ -#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) GENERIC_MIN( \ - (_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \ - (_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step))) +#define MOTION_MAX_SENSOR_FREQUENCY(_max, _step) \ + GENERIC_MIN( \ + (_max) / (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ >= (_step)), \ + (_step) << __fls(CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ / (_step))) struct motion_data_t { /* @@ -126,7 +124,7 @@ struct motion_data_t { * When set, spoof mode will allow the EC to report arbitrary values for any of * the components. */ -#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1) +#define MOTIONSENSE_FLAG_IN_SPOOF_MODE BIT(1) struct online_calib_data { /** @@ -353,8 +351,9 @@ static inline void ec_motion_sensor_clamp_i16s(int16_t *arr, const int32_t *v) } /* direct assignment */ -static inline void ec_motion_sensor_fill_values( - struct ec_response_motion_sensor_data *dst, const int32_t *v) +static inline void +ec_motion_sensor_fill_values(struct ec_response_motion_sensor_data *dst, + const int32_t *v) { dst->data[0] = v[0]; dst->data[1] = v[1]; -- cgit v1.2.1 From d9bada9f18f5c2f1bc781fa59f35d30bb0d1a6a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:04 -0600 Subject: common/update_fw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59e2870587e15bab2946742d77a162f0d8819f29 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729523 Reviewed-by: Jeremy Bettis --- common/update_fw.c | 65 ++++++++++++++++++++++++------------------------------ 1 file changed, 29 insertions(+), 36 deletions(-) diff --git a/common/update_fw.c b/common/update_fw.c index 068758e7b0..84fbe7cb9c 100644 --- a/common/update_fw.c +++ b/common/update_fw.c @@ -25,13 +25,13 @@ #include "touchpad_fw_hash.h" BUILD_ASSERT(sizeof(touchpad_fw_hashes) == - (CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE)); + (CONFIG_TOUCHPAD_FW_CHUNKS * SHA256_DIGEST_SIZE)); BUILD_ASSERT(sizeof(touchpad_fw_hashes[0]) == SHA256_DIGEST_SIZE); BUILD_ASSERT(sizeof(touchpad_fw_full_hash) == SHA256_DIGEST_SIZE); #endif -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* Section to be updated (i.e. not the current section). */ struct { @@ -47,9 +47,8 @@ struct { static int is_touchpad_block(uint32_t block_offset, size_t body_size) { return (block_offset >= CONFIG_TOUCHPAD_VIRTUAL_OFF) && - (block_offset + body_size) <= - (CONFIG_TOUCHPAD_VIRTUAL_OFF + - CONFIG_TOUCHPAD_VIRTUAL_SIZE); + (block_offset + body_size) <= (CONFIG_TOUCHPAD_VIRTUAL_OFF + + CONFIG_TOUCHPAD_VIRTUAL_SIZE); } #endif @@ -71,17 +70,15 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size) if (update_section.base_offset != update_section.top_offset && (block_offset >= update_section.base_offset) && ((block_offset + body_size) <= update_section.top_offset)) { - base = update_section.base_offset; - size = update_section.top_offset - - update_section.base_offset; + size = update_section.top_offset - update_section.base_offset; /* * If this is the first chunk for this section, it needs to * be erased. */ if (block_offset == base) { if (crec_flash_physical_erase(base, size) != - EC_SUCCESS) { + EC_SUCCESS) { CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n", __func__, __LINE__, base, size); return UPDATE_ERASE_FAILURE; @@ -96,14 +93,11 @@ static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size) return UPDATE_SUCCESS; #endif - CPRINTF("%s:%d %x, %d section base %x top %x\n", - __func__, __LINE__, - block_offset, body_size, - update_section.base_offset, + CPRINTF("%s:%d %x, %d section base %x top %x\n", __func__, __LINE__, + block_offset, body_size, update_section.base_offset, update_section.top_offset); return UPDATE_BAD_ADDR; - } int update_pdu_valid(struct update_command *cmd_body, size_t cmd_size) @@ -120,8 +114,8 @@ static void new_chunk_written(uint32_t block_offset) { } -static int contents_allowed(uint32_t block_offset, - size_t body_size, void *update_data) +static int contents_allowed(uint32_t block_offset, size_t body_size, + void *update_data) { #if defined(CONFIG_TOUCHPAD_VIRTUAL_OFF) && defined(CONFIG_TOUCHPAD_HASH_FW) if (is_touchpad_block(block_offset, body_size)) { @@ -132,9 +126,9 @@ static int contents_allowed(uint32_t block_offset, int good = 0; if (chunk >= CONFIG_TOUCHPAD_FW_CHUNKS || - (fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) { - CPRINTF("%s: TP invalid offset %08x\n", - __func__, fw_offset); + (fw_offset % CONFIG_UPDATE_PDU_SIZE) != 0) { + CPRINTF("%s: TP invalid offset %08x\n", __func__, + fw_offset); return 0; } @@ -143,10 +137,10 @@ static int contents_allowed(uint32_t block_offset, tmp = SHA256_final(&ctx); good = !memcmp(tmp, touchpad_fw_hashes[chunk], - SHA256_DIGEST_SIZE); + SHA256_DIGEST_SIZE); - CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__, - fw_offset, tmp[0], tmp[31], good ? "GOOD" : "BAD"); + CPRINTF("%s: TP %08x %02x..%02x (%s)\n", __func__, fw_offset, + tmp[0], tmp[31], good ? "GOOD" : "BAD"); return good; } @@ -194,7 +188,7 @@ void fw_update_start(struct first_response_pdu *rpdu) rpdu->common.offset = htobe32(update_section.base_offset); if (version) memcpy(rpdu->common.version, version, - sizeof(rpdu->common.version)); + sizeof(rpdu->common.version)); #ifdef CONFIG_ROLLBACK rpdu->common.min_rollback = htobe32(rollback_get_minimum_version()); @@ -216,13 +210,12 @@ void fw_update_start(struct first_response_pdu *rpdu) #endif } -void fw_update_command_handler(void *body, - size_t cmd_size, +void fw_update_command_handler(void *body, size_t cmd_size, size_t *response_size) { struct update_command *cmd_body = body; void *update_data; - uint8_t *error_code = body; /* Cache the address for code clarity. */ + uint8_t *error_code = body; /* Cache the address for code clarity. */ size_t body_size; uint32_t block_offset; @@ -285,11 +278,11 @@ void fw_update_command_handler(void *body, #ifdef CONFIG_TOUCHPAD_VIRTUAL_OFF if (is_touchpad_block(block_offset, body_size)) { if (touchpad_update_write( - block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF, - body_size, update_data) != EC_SUCCESS) { + block_offset - CONFIG_TOUCHPAD_VIRTUAL_OFF, + body_size, update_data) != EC_SUCCESS) { *error_code = UPDATE_WRITE_FAILURE; - CPRINTF("%s:%d update write error\n", - __func__, __LINE__); + CPRINTF("%s:%d update write error\n", __func__, + __LINE__); return; } @@ -301,8 +294,8 @@ void fw_update_command_handler(void *body, #endif CPRINTF("update: 0x%x\n", block_offset + CONFIG_PROGRAM_MEMORY_BASE); - if (crec_flash_physical_write(block_offset, body_size, update_data) - != EC_SUCCESS) { + if (crec_flash_physical_write(block_offset, body_size, update_data) != + EC_SUCCESS) { *error_code = UPDATE_WRITE_FAILURE; CPRINTF("%s:%d update write error\n", __func__, __LINE__); return; @@ -311,12 +304,12 @@ void fw_update_command_handler(void *body, new_chunk_written(block_offset); /* Verify that data was written properly. */ - if (memcmp(update_data, (void *) - (block_offset + CONFIG_PROGRAM_MEMORY_BASE), + if (memcmp(update_data, + (void *)(block_offset + CONFIG_PROGRAM_MEMORY_BASE), body_size)) { *error_code = UPDATE_VERIFY_ERROR; - CPRINTF("%s:%d update verification error\n", - __func__, __LINE__); + CPRINTF("%s:%d update verification error\n", __func__, + __LINE__); return; } -- cgit v1.2.1 From a083c32171c15cea59f557faf0dbc5971a3f7a3e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:52 -0600 Subject: board/cerise/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I10e4985b1884c6d91d0fa5555bfeef4d12fbc418 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728117 Reviewed-by: Jeremy Bettis --- board/cerise/board.c | 83 ++++++++++++++++++++++------------------------------ 1 file changed, 35 insertions(+), 48 deletions(-) diff --git a/board/cerise/board.c b/board/cerise/board.c index 61722dd530..8e3783e055 100644 --- a/board/cerise/board.c +++ b/board/cerise/board.c @@ -46,8 +46,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -59,40 +59,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -100,8 +94,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -157,8 +151,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -239,12 +232,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -301,8 +294,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -316,8 +308,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -359,17 +350,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t base_standard_ref = { - {0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref = { - {0, FLOAT_TO_FP(1), 0}, - {FLOAT_TO_FP(1), 0, 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ /* Lid accel private data */ -- cgit v1.2.1 From 68366f190aab16033c7f0528720f65a03576ea7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:17 -0600 Subject: board/nuwani/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4b1db245ab0414c50e25e8f4132e767806b677fe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728786 Reviewed-by: Jeremy Bettis --- board/nuwani/board.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/nuwani/board.h b/board/nuwani/board.h index 6bdffa73ac..b89bdc27aa 100644 --- a/board/nuwani/board.h +++ b/board/nuwani/board.h @@ -16,7 +16,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -47,7 +47,7 @@ /* * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. */ -#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US #define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) /* Second set of sensor drivers */ @@ -58,7 +58,6 @@ #ifndef __ASSEMBLER__ - enum battery_type { BATTERY_SMP, BATTERY_LGC, -- cgit v1.2.1 From b39e69b934b6c5177c3f10e928bc6ded111fbe64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:28 -0600 Subject: include/charger.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I361676f68c1b5a2557b2c67438fbb68a1747229b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730225 Reviewed-by: Jeremy Bettis --- include/charger.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/include/charger.h b/include/charger.h index 5a7188f4e3..3cda0c0083 100644 --- a/include/charger.h +++ b/include/charger.h @@ -50,7 +50,7 @@ struct charger_drv { enum ec_error_list (*post_init)(int chgnum); /* Get charger information */ - const struct charger_info * (*get_info)(int chgnum); + const struct charger_info *(*get_info)(int chgnum); /* Get smart battery charger status. Supported flags may vary. */ enum ec_error_list (*get_status)(int chgnum, int *status); @@ -85,12 +85,10 @@ struct charger_drv { enum ec_error_list (*get_voltage)(int chgnum, int *voltage); enum ec_error_list (*set_voltage)(int chgnum, int voltage); - /* Get the measured charge current and voltage in mA/mV */ enum ec_error_list (*get_actual_current)(int chgnum, int *current); enum ec_error_list (*get_actual_voltage)(int chgnum, int *voltage); - /* Discharge battery when on AC power. */ enum ec_error_list (*discharge_on_ac)(int chgnum, int enable); @@ -184,13 +182,13 @@ enum chg_id { void charger_get_params(struct charger_params *chg); /* Bits to indicate which fields of struct charger_params could not be read */ -#define CHG_FLAG_BAD_CURRENT 0x00000001 -#define CHG_FLAG_BAD_VOLTAGE 0x00000002 -#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004 -#define CHG_FLAG_BAD_STATUS 0x00000008 -#define CHG_FLAG_BAD_OPTION 0x00000010 +#define CHG_FLAG_BAD_CURRENT 0x00000001 +#define CHG_FLAG_BAD_VOLTAGE 0x00000002 +#define CHG_FLAG_BAD_INPUT_CURRENT 0x00000004 +#define CHG_FLAG_BAD_STATUS 0x00000008 +#define CHG_FLAG_BAD_OPTION 0x00000010 /* All of the above CHG_FLAG_BAD_* bits */ -#define CHG_FLAG_BAD_ANY 0x0000001f +#define CHG_FLAG_BAD_ANY 0x0000001f /** * Return the closest match the charger can supply to the requested current. -- cgit v1.2.1 From 84f1accf5b3ddcddc0101196fe5827a1e16203fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:01:52 -0600 Subject: board/redrix/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iecd534de1d19e00c08a3ccd03b6b042d1e419138 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728877 Reviewed-by: Jeremy Bettis --- board/redrix/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/redrix/board.c b/board/redrix/board.c index 5cf76b5447..37dd049a47 100644 --- a/board/redrix/board.c +++ b/board/redrix/board.c @@ -31,8 +31,8 @@ #include "gpio_list.h" /* Must come after other header files. */ /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Battery discharging over-current limit is 8A */ #define BATT_OC_LIMIT -8000 -- cgit v1.2.1 From b8a9f4d4e7b3f89c13f24726cd76ff9e5620219d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:12 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If795782cb9f1ae0048147c2a99e22503c1c69f09 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730973 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 04b98b4a28..ebc2816d1a 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -175,8 +175,8 @@ ZTEST_F(usbc_alt_mode, verify_discovery) uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; struct ec_response_typec_discovery *discovery = (struct ec_response_typec_discovery *)response_buffer; - host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, - response_buffer, sizeof(response_buffer)); + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, + sizeof(response_buffer)); /* The host command does not count the VDM header in identity_count. */ zassert_equal(discovery->identity_count, @@ -184,11 +184,10 @@ ZTEST_F(usbc_alt_mode, verify_discovery) "Expected %d identity VDOs, got %d", fixture->partner.identity_vdos - 1, discovery->identity_count); - zassert_mem_equal(discovery->discovery_vdo, - fixture->partner.identity_vdm + 1, - discovery->identity_count * - sizeof(*discovery->discovery_vdo), - "Discovered SOP identity ACK did not match"); + zassert_mem_equal( + discovery->discovery_vdo, fixture->partner.identity_vdm + 1, + discovery->identity_count * sizeof(*discovery->discovery_vdo), + "Discovered SOP identity ACK did not match"); zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", discovery->svid_count); zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, -- cgit v1.2.1 From eed779395f3c2a6ef27ba7231f703bce8e041f93 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:11 -0600 Subject: board/lantis/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I49babdd05d52338c2cd8ba1db419dcb02f85ba85 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728628 Reviewed-by: Jeremy Bettis --- board/lantis/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/lantis/cbi_ssfc.c b/board/lantis/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/lantis/cbi_ssfc.c +++ b/board/lantis/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 140fa9002f4e07a0308a9502cfe7912ad1fc95d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:43 -0600 Subject: baseboard/kalista/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1e4b146d68207052507f18be7a8b95ce2eaacc84 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727913 Reviewed-by: Jeremy Bettis --- baseboard/kalista/usb_pd_policy.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/baseboard/kalista/usb_pd_policy.c b/baseboard/kalista/usb_pd_policy.c index 85b26aac76..a8ff0df3a3 100644 --- a/baseboard/kalista/usb_pd_policy.c +++ b/baseboard/kalista/usb_pd_policy.c @@ -23,8 +23,8 @@ #include "usb_pd_pdo.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int board_vbus_source_enabled(int port) { @@ -58,8 +58,7 @@ int pd_snk_is_vbus_provided(int port) return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L); } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { } -- cgit v1.2.1 From 162287b957793eee6c8cadd0fbdafdff1ee5a644 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:22 -0600 Subject: driver/usb_mux/anx7451.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I743c65c6955393e703ea32a464fd2600d8d49081 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730160 Reviewed-by: Jeremy Bettis --- driver/usb_mux/anx7451.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/driver/usb_mux/anx7451.h b/driver/usb_mux/anx7451.h index 7eefb6e79e..b2dc58c66a 100644 --- a/driver/usb_mux/anx7451.h +++ b/driver/usb_mux/anx7451.h @@ -12,38 +12,38 @@ #include "usb_mux.h" /* I2C interface addresses */ -#define ANX7451_I2C_ADDR0_FLAGS 0x10 -#define ANX7451_I2C_ADDR1_FLAGS 0x14 -#define ANX7451_I2C_ADDR2_FLAGS 0x16 -#define ANX7451_I2C_ADDR3_FLAGS 0x11 +#define ANX7451_I2C_ADDR0_FLAGS 0x10 +#define ANX7451_I2C_ADDR1_FLAGS 0x14 +#define ANX7451_I2C_ADDR2_FLAGS 0x16 +#define ANX7451_I2C_ADDR3_FLAGS 0x11 /* This register is not documented in datasheet. */ -#define ANX7451_REG_POWER_CNTRL 0x2B -#define ANX7451_POWER_CNTRL_OFF 0xFF +#define ANX7451_REG_POWER_CNTRL 0x2B +#define ANX7451_POWER_CNTRL_OFF 0xFF /* * Ultra low power control register. * On ANX7451, this register should always be 0 (disabled). * See figure 2-2 in family programming guide. */ -#define ANX7451_REG_ULTRA_LOW_POWER 0xE6 +#define ANX7451_REG_ULTRA_LOW_POWER 0xE6 /* #define ANX7451_ULTRA_LOW_POWER_EN 0x06 */ -#define ANX7451_ULTRA_LOW_POWER_DIS 0x00 +#define ANX7451_ULTRA_LOW_POWER_DIS 0x00 /* Mux control register */ -#define ANX7451_REG_ULP_CFG_MODE 0xF8 -#define ANX7451_ULP_CFG_MODE_EN BIT(4) -#define ANX7451_ULP_CFG_MODE_SWAP BIT(3) -#define ANX7451_ULP_CFG_MODE_FLIP BIT(2) -#define ANX7451_ULP_CFG_MODE_DP_EN BIT(1) -#define ANX7451_ULP_CFG_MODE_USB_EN BIT(0) +#define ANX7451_REG_ULP_CFG_MODE 0xF8 +#define ANX7451_ULP_CFG_MODE_EN BIT(4) +#define ANX7451_ULP_CFG_MODE_SWAP BIT(3) +#define ANX7451_ULP_CFG_MODE_FLIP BIT(2) +#define ANX7451_ULP_CFG_MODE_DP_EN BIT(1) +#define ANX7451_ULP_CFG_MODE_USB_EN BIT(0) /* Register to set USB I2C address, defaults to 0x29 (7-bit) */ -#define ANX7451_REG_USB_I2C_ADDR 0x38 +#define ANX7451_REG_USB_I2C_ADDR 0x38 /* ANX7451 AUX FLIP control */ -#define ANX7451_REG_USB_AUX_FLIP_CTRL 0xA4 -#define ANX7451_USB_AUX_FLIP_EN 0x20 +#define ANX7451_REG_USB_AUX_FLIP_CTRL 0xA4 +#define ANX7451_USB_AUX_FLIP_EN 0x20 extern const struct usb_mux_driver anx7451_usb_mux_driver; -- cgit v1.2.1 From 1b9260267f600461afa03c831a3275b335fd43fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:14 -0600 Subject: common/motion_lid.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic4d5448ac584ec44523c2c583127da47fcdbc170 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729678 Reviewed-by: Jeremy Bettis --- common/motion_lid.c | 88 +++++++++++++++++++++++++---------------------------- 1 file changed, 41 insertions(+), 47 deletions(-) diff --git a/common/motion_lid.c b/common/motion_lid.c index 4e76bebb66..e96d186256 100644 --- a/common/motion_lid.c +++ b/common/motion_lid.c @@ -26,8 +26,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_MOTION_LID, outstr) -#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ## args) +#define CPRINTS(format, args...) cprints(CC_MOTION_LID, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_MOTION_LID, format, ##args) #ifdef CONFIG_TABLET_MODE /* Previous lid_angle. */ @@ -50,7 +50,7 @@ static int lid_angle_is_reliable; static intv3_t smoothed_base, smoothed_lid; /* 8.7 m/s^2 is the the maximum acceleration parallel to the hinge */ -#define SCALED_HINGE_VERTICAL_MAXIMUM \ +#define SCALED_HINGE_VERTICAL_MAXIMUM \ ((int)((8.7f * MOTION_SCALING_FACTOR) / MOTION_ONE_G)) #define SCALED_HINGE_VERTICAL_SMOOTHING_START \ @@ -88,21 +88,21 @@ static intv3_t smoothed_base, smoothed_lid; * frame before calculating lid angle). */ #ifdef CONFIG_ACCEL_STD_REF_FRAME_OLD -static const intv3_t hinge_axis = { 0, 1, 0}; +static const intv3_t hinge_axis = { 0, 1, 0 }; #define HINGE_AXIS Y #else -static const intv3_t hinge_axis = { 1, 0, 0}; +static const intv3_t hinge_axis = { 1, 0, 0 }; #define HINGE_AXIS X #endif -static const struct motion_sensor_t * const accel_base = +static const struct motion_sensor_t *const accel_base = &motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE]; -static const struct motion_sensor_t * const accel_lid = +static const struct motion_sensor_t *const accel_lid = &motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID]; STATIC_IF(CONFIG_TABLET_MODE) void motion_lid_set_tablet_mode(int reliable); -STATIC_IF(CONFIG_TABLET_MODE) int lid_angle_set_tablet_mode_threshold( - int angle, int hys); +STATIC_IF(CONFIG_TABLET_MODE) +int lid_angle_set_tablet_mode_threshold(int angle, int hys); STATIC_IF(CONFIG_TABLET_MODE) fp_t tablet_zone_lid_angle; STATIC_IF(CONFIG_TABLET_MODE) fp_t laptop_zone_lid_angle; @@ -142,18 +142,16 @@ __attribute__((weak)) int board_is_lid_angle_tablet_mode(void) * by using MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE. */ -#define DEFAULT_TABLET_MODE_ANGLE (180) -#define DEFAULT_TABLET_MODE_HYS (20) +#define DEFAULT_TABLET_MODE_ANGLE (180) +#define DEFAULT_TABLET_MODE_HYS (20) -#define TABLET_ZONE_ANGLE(a, h) ((a) + (h)) -#define LAPTOP_ZONE_ANGLE(a, h) ((a) - (h)) +#define TABLET_ZONE_ANGLE(a, h) ((a) + (h)) +#define LAPTOP_ZONE_ANGLE(a, h) ((a) - (h)) -static fp_t tablet_zone_lid_angle = - FLOAT_TO_FP(TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, - DEFAULT_TABLET_MODE_HYS)); -static fp_t laptop_zone_lid_angle = - FLOAT_TO_FP(LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, - DEFAULT_TABLET_MODE_HYS)); +static fp_t tablet_zone_lid_angle = FLOAT_TO_FP( + TABLET_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS)); +static fp_t laptop_zone_lid_angle = FLOAT_TO_FP( + LAPTOP_ZONE_ANGLE(DEFAULT_TABLET_MODE_ANGLE, DEFAULT_TABLET_MODE_HYS)); static int tablet_mode_lid_angle = DEFAULT_TABLET_MODE_ANGLE; static int tablet_mode_hys_degree = DEFAULT_TABLET_MODE_HYS; @@ -220,8 +218,8 @@ static int lid_angle_set_tablet_mode_threshold(int angle, int hys) #define MOTION_LID_SET_DPTF_PROFILE #endif -STATIC_IF(MOTION_LID_SET_DPTF_PROFILE) void motion_lid_set_dptf_profile( - int reliable); +STATIC_IF(MOTION_LID_SET_DPTF_PROFILE) +void motion_lid_set_dptf_profile(int reliable); #ifdef MOTION_LID_SET_DPTF_PROFILE /* @@ -322,11 +320,11 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid, * less than 1<<30. */ base_magnitude2 = scaled_base[X] * scaled_base[X] + - scaled_base[Y] * scaled_base[Y] + - scaled_base[Z] * scaled_base[Z]; + scaled_base[Y] * scaled_base[Y] + + scaled_base[Z] * scaled_base[Z]; lid_magnitude2 = scaled_lid[X] * scaled_lid[X] + - scaled_lid[Y] * scaled_lid[Y] + - scaled_lid[Z] * scaled_lid[Z]; + scaled_lid[Y] * scaled_lid[Y] + + scaled_lid[Z] * scaled_lid[Z]; /* * Check to see if they differ than more than NOISY_MAGNITUDE_DEVIATION. @@ -358,14 +356,16 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid, goto end_calculate_lid_angle; } - largest_hinge_accel = MAX(ABS(scaled_base[HINGE_AXIS]), - ABS(scaled_lid[HINGE_AXIS])); + largest_hinge_accel = + MAX(ABS(scaled_base[HINGE_AXIS]), ABS(scaled_lid[HINGE_AXIS])); - smoothed_ratio = MAX(INT_TO_FP(0), MIN(INT_TO_FP(1), - fp_div(INT_TO_FP(largest_hinge_accel - - SCALED_HINGE_VERTICAL_SMOOTHING_START), - INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM - - SCALED_HINGE_VERTICAL_SMOOTHING_START)))); + smoothed_ratio = MAX( + INT_TO_FP(0), + MIN(INT_TO_FP(1), + fp_div(INT_TO_FP(largest_hinge_accel - + SCALED_HINGE_VERTICAL_SMOOTHING_START), + INT_TO_FP(SCALED_HINGE_VERTICAL_MAXIMUM - + SCALED_HINGE_VERTICAL_SMOOTHING_START)))); /* Check hinge is not too vertical */ if (largest_hinge_accel > SCALED_HINGE_VERTICAL_MAXIMUM) { @@ -417,8 +417,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid, #ifdef CONFIG_TABLET_MODE /* Ignore large angles when the lid is closed. */ - if (!lid_is_open() && - (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) { + if (!lid_is_open() && (lid_to_base_fp > SMALL_LID_ANGLE_RANGE)) { reliable = 0; goto end_calculate_lid_angle; } @@ -434,8 +433,7 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid, * may wake us up. This is because we require at least 4 consecutive * reliable readings over a threshold to disable key scanning. */ - if (lid_is_open() && - (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) { + if (lid_is_open() && (lid_to_base_fp <= SMALL_LID_ANGLE_RANGE)) { reliable = 0; goto end_calculate_lid_angle; } @@ -451,10 +449,8 @@ static int calculate_lid_angle(const intv3_t base, const intv3_t lid, * prove the small angle we see is correct so we take the angle * as is. */ - if ((last_lid_angle_fp >= - FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) && - (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) && - (lid_is_open())) + if ((last_lid_angle_fp >= FLOAT_TO_FP(360) - DEBOUNCE_ANGLE_DELTA) && + (lid_to_base_fp <= DEBOUNCE_ANGLE_DELTA) && (lid_is_open())) last_lid_angle_fp = FLOAT_TO_FP(360) - lid_to_base_fp; else last_lid_angle_fp = lid_to_base_fp; @@ -471,7 +467,7 @@ end_calculate_lid_angle: if (IS_ENABLED(MOTION_LID_SET_DPTF_PROFILE)) motion_lid_set_dptf_profile(reliable); -#else /* CONFIG_TABLET_MODE */ +#else /* CONFIG_TABLET_MODE */ end_calculate_lid_angle: if (reliable) *lid_angle = FP_TO_INT(lid_to_base_fp + FLOAT_TO_FP(0.5)); @@ -494,8 +490,7 @@ void motion_lid_calc(void) { /* Calculate angle of lid accel. */ lid_angle_is_reliable = calculate_lid_angle( - accel_base->xyz, accel_lid->xyz, - &lid_angle_deg); + accel_base->xyz, accel_lid->xyz, &lid_angle_deg); if (IS_ENABLED(CONFIG_LID_ANGLE_UPDATE)) lid_angle_update(motion_lid_get_angle()); @@ -504,7 +499,6 @@ void motion_lid_calc(void) /*****************************************************************************/ /* Host commands */ - enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args) { const struct ec_params_motion_sense *in = args->params; @@ -519,7 +513,7 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args) */ if (in->kb_wake_angle.data != EC_MOTION_SENSE_NO_VALUE) lid_angle_set_wake_angle( - in->kb_wake_angle.data); + in->kb_wake_angle.data); out->kb_wake_angle.ret = lid_angle_get_wake_angle(); } else { @@ -542,8 +536,8 @@ enum ec_status host_cmd_motion_lid(struct host_cmd_handler_args *args) if (IS_ENABLED(CONFIG_TABLET_MODE)) { int ret; ret = lid_angle_set_tablet_mode_threshold( - in->tablet_mode_threshold.lid_angle, - in->tablet_mode_threshold.hys_degree); + in->tablet_mode_threshold.lid_angle, + in->tablet_mode_threshold.hys_degree); if (ret != EC_RES_SUCCESS) return ret; -- cgit v1.2.1 From 55badc6c9c30c758598e1ad3a3a82112c29d9f13 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:47 -0600 Subject: include/usb_prl_sm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c129fc3e44efde83de81bdbf82f80cf61b47990 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730447 Reviewed-by: Jeremy Bettis --- include/usb_prl_sm.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/usb_prl_sm.h b/include/usb_prl_sm.h index 6607bd2824..7e1984475f 100644 --- a/include/usb_prl_sm.h +++ b/include/usb_prl_sm.h @@ -80,8 +80,7 @@ void prl_run(int port, int evt, int en); * @param type port address * @param rev revision */ -void prl_set_rev(int port, enum tcpci_msg_type type, - enum pd_rev_type rev); +void prl_set_rev(int port, enum tcpci_msg_type type, enum pd_rev_type rev); /** * Get the PD revision @@ -100,7 +99,7 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type type); * @param msg Control message type */ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, - enum pd_ctrl_msg_type msg); + enum pd_ctrl_msg_type msg); /** * Sends a PD data message @@ -110,7 +109,7 @@ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, * @param msg Data message type */ void prl_send_data_msg(int port, enum tcpci_msg_type type, - enum pd_data_msg_type msg); + enum pd_data_msg_type msg); /** * Sends a PD extended data message @@ -120,7 +119,7 @@ void prl_send_data_msg(int port, enum tcpci_msg_type type, * @param msg Extended data message type */ void prl_send_ext_data_msg(int port, enum tcpci_msg_type type, - enum pd_ext_msg_type msg); + enum pd_ext_msg_type msg); /** * Informs the Protocol Layer that a hard reset has completed -- cgit v1.2.1 From 0a3c81b504be3367526254cd888fa9e6deea8389 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:22 -0600 Subject: zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9a2f95e0e077264f9ee72ae4446afa0d441e9e6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730678 Reviewed-by: Jeremy Bettis --- zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h | 82 ++++++++++++------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h index 3296f80992..3b18cf4282 100644 --- a/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h +++ b/zephyr/drivers/cros_rtc/renesas_rtc_idt1337ag.h @@ -7,54 +7,54 @@ #define __CROS_EC_RTC_IDT1337AG_H /* Setting bit 6 of register 0Ah selects the DAY as alarm source */ -#define SELECT_DAYS_ALARM 0x40 -#define DISABLE_ALARM 0x80 - -#define CONTROL_A1IE BIT(0) -#define CONTROL_A2IE BIT(1) -#define CONTROL_INTCN BIT(2) -#define CONTROL_EOSC BIT(7) - -#define STATUS_A1F BIT(0) -#define STATUS_A2F BIT(1) -#define STATUS_OSF BIT(7) - -#define NUM_TIMER_REGS 7 -#define NUM_ALARM_REGS 4 - -#define REG_SECONDS 0x00 -#define REG_MINUTES 0x01 -#define REG_HOURS 0x02 -#define REG_DAYS 0x03 -#define REG_DATE 0x04 -#define REG_MONTHS 0x05 -#define REG_YEARS 0x06 -#define REG_SECOND_ALARM1 0x07 -#define REG_MINUTE_ALARM1 0x08 -#define REG_HOUR_ALARM1 0x09 -#define REG_DAY_ALARM1 0x0a -#define REG_MINUTE_ALARM2 0x0b -#define REG_HOUR_ALARM2 0x0c -#define REG_DAY_ALARM2 0x0d -#define REG_CONTROL 0x0e -#define REG_STATUS 0x0f +#define SELECT_DAYS_ALARM 0x40 +#define DISABLE_ALARM 0x80 + +#define CONTROL_A1IE BIT(0) +#define CONTROL_A2IE BIT(1) +#define CONTROL_INTCN BIT(2) +#define CONTROL_EOSC BIT(7) + +#define STATUS_A1F BIT(0) +#define STATUS_A2F BIT(1) +#define STATUS_OSF BIT(7) + +#define NUM_TIMER_REGS 7 +#define NUM_ALARM_REGS 4 + +#define REG_SECONDS 0x00 +#define REG_MINUTES 0x01 +#define REG_HOURS 0x02 +#define REG_DAYS 0x03 +#define REG_DATE 0x04 +#define REG_MONTHS 0x05 +#define REG_YEARS 0x06 +#define REG_SECOND_ALARM1 0x07 +#define REG_MINUTE_ALARM1 0x08 +#define REG_HOUR_ALARM1 0x09 +#define REG_DAY_ALARM1 0x0a +#define REG_MINUTE_ALARM2 0x0b +#define REG_HOUR_ALARM2 0x0c +#define REG_DAY_ALARM2 0x0d +#define REG_CONTROL 0x0e +#define REG_STATUS 0x0f /* Macros for indexing time_reg buffer */ -#define SECONDS 0 -#define MINUTES 1 -#define HOURS 2 -#define DAYS 3 -#define DATE 4 -#define MONTHS 5 -#define YEARS 6 +#define SECONDS 0 +#define MINUTES 1 +#define HOURS 2 +#define DAYS 3 +#define DATE 4 +#define MONTHS 5 +#define YEARS 6 enum bcd_mask { SECONDS_MASK = 0x70, MINUTES_MASK = 0x70, HOURS24_MASK = 0x30, - DAYS_MASK = 0x00, - MONTHS_MASK = 0x10, - YEARS_MASK = 0xf0 + DAYS_MASK = 0x00, + MONTHS_MASK = 0x10, + YEARS_MASK = 0xf0 }; #endif /* __CROS_EC_RTC_IDT1337AG_H */ -- cgit v1.2.1 From 74907670c7025949e78526a10902cad26789aac4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:17 -0600 Subject: baseboard/mtscp-rv32i/mdp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If0ac8d205cb965a84a921dbe75df8ead72fb4775 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727927 Reviewed-by: Jeremy Bettis --- baseboard/mtscp-rv32i/mdp.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/baseboard/mtscp-rv32i/mdp.c b/baseboard/mtscp-rv32i/mdp.c index b0756a797a..f33c37c8c3 100644 --- a/baseboard/mtscp-rv32i/mdp.c +++ b/baseboard/mtscp-rv32i/mdp.c @@ -19,19 +19,23 @@ static void event_mdp_written(struct consumer const *consumer, size_t count) task_wake(TASK_ID_MDP_SERVICE); } static struct consumer const event_mdp_consumer; -static struct queue const event_mdp_queue = QUEUE_DIRECT(4, - struct mdp_msg_service, null_producer, event_mdp_consumer); +static struct queue const event_mdp_queue = QUEUE_DIRECT( + 4, struct mdp_msg_service, null_producer, event_mdp_consumer); static struct consumer const event_mdp_consumer = { .queue = &event_mdp_queue, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = event_mdp_written, }), }; /* Stub functions only provided by private overlays. */ #ifndef HAVE_PRIVATE_MT_SCP -void mdp_common_init(void) {} -void mdp_ipi_task_handler(void *pvParameters) {} +void mdp_common_init(void) +{ +} +void mdp_ipi_task_handler(void *pvParameters) +{ +} #endif static void mdp_ipi_handler(int id, void *data, unsigned int len) -- cgit v1.2.1 From df8b05aa9d89c0c2502584b1818352b491b890a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:10 -0600 Subject: baseboard/brya/baseboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iedd6f535e5d42f0e07e0f4e99fb249be7d39fcc3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727860 Reviewed-by: Jeremy Bettis --- baseboard/brya/baseboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/brya/baseboard.c b/baseboard/brya/baseboard.c index 7b9e3c2e00..e11bf9ef8b 100644 --- a/baseboard/brya/baseboard.c +++ b/baseboard/brya/baseboard.c @@ -41,5 +41,5 @@ __override void lid_angle_peripheral_enable(int enable) */ if (!chipset_in_state(CHIPSET_STATE_ON)) keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE); - } + } } -- cgit v1.2.1 From 68d1a3781e13f4ed86a6f47e178f7ace0e8f6634 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:32 -0600 Subject: board/primus/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8c43fe695bc8adb6d051ad51c0de6e63abdd7376 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727760 Reviewed-by: Jeremy Bettis --- board/primus/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/primus/fw_config.c b/board/primus/fw_config.c index 0384d05b9d..25a89255f7 100644 --- a/board/primus/fw_config.c +++ b/board/primus/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union primus_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From 82a9ca4fe94591b151dc1443c77390822c2e271a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:46 -0600 Subject: include/compile_time_macros.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I179b145058e91df63708a8d89cae1dbf6c9ceec4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730230 Reviewed-by: Jeremy Bettis --- include/compile_time_macros.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/compile_time_macros.h b/include/compile_time_macros.h index 0151f1a391..a227fb1f9a 100644 --- a/include/compile_time_macros.h +++ b/include/compile_time_macros.h @@ -69,7 +69,7 @@ /* Just in case - http://gcc.gnu.org/onlinedocs/gcc/Offsetof.html */ #ifndef offsetof -#define offsetof(type, member) __builtin_offsetof(type, member) +#define offsetof(type, member) __builtin_offsetof(type, member) #endif #define member_size(type, member) sizeof(((type *)0)->member) @@ -78,7 +78,7 @@ * Bit operation macros. */ #ifndef CONFIG_ZEPHYR -#define BIT(nr) (1U << (nr)) +#define BIT(nr) (1U << (nr)) /* * Set or clear of depending on . * It also supports setting and clearing (e.g. SET_BIT, CLR_BIT) macros. @@ -86,7 +86,7 @@ #define WRITE_BIT(var, bit, set) \ ((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit))) #endif -#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) /* * Create a bit mask from least significant bit |l| @@ -102,8 +102,8 @@ * warnings for BIT(31+1). */ #ifndef CONFIG_ZEPHYR -#define GENMASK(h, l) (((BIT(h)<<1) - 1) ^ (BIT(l) - 1)) -#define GENMASK_ULL(h, l) (((BIT_ULL(h)<<1) - 1) ^ (BIT_ULL(l) - 1)) +#define GENMASK(h, l) (((BIT(h) << 1) - 1) ^ (BIT(l) - 1)) +#define GENMASK_ULL(h, l) (((BIT_ULL(h) << 1) - 1) ^ (BIT_ULL(l) - 1)) #endif #endif /* __CROS_EC_COMPILE_TIME_MACROS_H */ -- cgit v1.2.1 From 8e25c708da7df73f7a2c961f2c9cb6e66b79b274 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:33 -0600 Subject: extra/rma_reset/rma_reset.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibb3b2bf57de9fa67b68c13d1111caa9ba2d7cb60 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730184 Reviewed-by: Jeremy Bettis --- extra/rma_reset/rma_reset.c | 140 ++++++++++++++++++++------------------------ 1 file changed, 65 insertions(+), 75 deletions(-) diff --git a/extra/rma_reset/rma_reset.c b/extra/rma_reset/rma_reset.c index fe1eb5e909..950b1227fd 100644 --- a/extra/rma_reset/rma_reset.c +++ b/extra/rma_reset/rma_reset.c @@ -27,24 +27,22 @@ #define EC_COORDINATE_SZ 32 #define EC_PRIV_KEY_SZ 32 #define EC_P256_UNCOMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ * 2 + 1) -#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ + 1) +#define EC_P256_COMPRESSED_PUB_KEY_SZ (EC_COORDINATE_SZ + 1) #define SERVER_ADDRESS \ "https://www.google.com/chromeos/partner/console/cr50reset/request" /* Test server keys for x25519 and p256 curves. */ static const uint8_t rma_test_server_x25519_public_key[] = { - 0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, - 0x0d, 0xd3, 0xb7, 0x92, 0xac, 0x54, 0xc5, 0xfd, - 0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, 0x2a, 0xb5, - 0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f + 0x03, 0xae, 0x2d, 0x2c, 0x06, 0x23, 0xe0, 0x73, 0x0d, 0xd3, 0xb7, + 0x92, 0xac, 0x54, 0xc5, 0xfd, 0x7e, 0x9c, 0xf0, 0xa8, 0xeb, 0x7e, + 0x2a, 0xb5, 0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f }; static const uint8_t rma_test_server_x25519_private_key[] = { - 0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, - 0x20, 0xbd, 0xd8, 0xbd, 0xc8, 0x7a, 0xbb, 0x07, - 0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, 0xec, 0xb3, - 0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad + 0x47, 0x3b, 0xa5, 0xdb, 0xc4, 0xbb, 0xd6, 0x77, 0x20, 0xbd, 0xd8, + 0xbd, 0xc8, 0x7a, 0xbb, 0x07, 0x03, 0x79, 0xba, 0x7b, 0x52, 0x8c, + 0xec, 0xb3, 0x4d, 0xaa, 0x69, 0xf5, 0x65, 0xb4, 0x31, 0xad }; #define RMA_TEST_SERVER_X25519_KEY_ID 0x10 @@ -57,10 +55,9 @@ static const uint8_t rma_test_server_x25519_private_key[] = { * openssl ec -in key.pem -text -noout */ static const uint8_t rma_test_server_p256_private_key[] = { - 0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a, - 0xa7, 0x6b, 0xea, 0x8f, 0x30, 0xcc, 0xf7, 0x3d, - 0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec, 0x7d, 0xe9, - 0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81 + 0x54, 0xb0, 0x82, 0x92, 0x54, 0x92, 0xfc, 0x4a, 0xa7, 0x6b, 0xea, + 0x8f, 0x30, 0xcc, 0xf7, 0x3d, 0xa2, 0xf6, 0xa7, 0xad, 0xf0, 0xec, + 0x7d, 0xe9, 0x26, 0x75, 0xd1, 0xec, 0xde, 0x20, 0x8f, 0x81 }; /* @@ -68,15 +65,12 @@ static const uint8_t rma_test_server_p256_private_key[] = { * prefix, 65 bytes total. */ static const uint8_t rma_test_server_p256_public_key[] = { - 0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc, - 0x68, 0xf4, 0x8c, 0x56, 0x65, 0x5a, 0xcb, 0xf8, - 0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b, 0xae, 0xd6, - 0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b, - 0x0a, 0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19, - 0x81, 0x76, 0x84, 0x92, 0x7f, 0x8d, 0xb2, 0xbe, - 0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00, 0x67, - 0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4, - 0x35 + 0x04, 0xe7, 0xbe, 0x37, 0xaa, 0x68, 0xca, 0xcc, 0x68, 0xf4, 0x8c, + 0x56, 0x65, 0x5a, 0xcb, 0xf8, 0xf4, 0x65, 0x3c, 0xd3, 0xc6, 0x1b, + 0xae, 0xd6, 0x51, 0x7a, 0xcc, 0x00, 0x8d, 0x59, 0x6d, 0x1b, 0x0a, + 0x66, 0xe8, 0x68, 0x5e, 0x6a, 0x82, 0x19, 0x81, 0x76, 0x84, 0x92, + 0x7f, 0x8d, 0xb2, 0xbe, 0xf5, 0x39, 0x50, 0xd5, 0xfe, 0xee, 0x00, + 0x67, 0xcf, 0x40, 0x5f, 0x68, 0x12, 0x83, 0x4f, 0xa4, 0x35 }; #define RMA_TEST_SERVER_P256_KEY_ID 0x20 @@ -84,8 +78,8 @@ static const uint8_t rma_test_server_p256_public_key[] = { /* Default values which can change based on command line arguments. */ static uint8_t server_key_id = RMA_TEST_SERVER_X25519_KEY_ID; -static uint8_t board_id[4] = {'Z', 'Z', 'C', 'R'}; -static uint8_t device_id[8] = {'T', 'H', 'X', 1, 1, 3, 8, 0xfe}; +static uint8_t board_id[4] = { 'Z', 'Z', 'C', 'R' }; +static uint8_t device_id[8] = { 'T', 'H', 'X', 1, 1, 3, 8, 0xfe }; static uint8_t hw_id[20] = "TESTSAMUS1234"; static char challenge[RMA_CHALLENGE_BUF_SIZE]; @@ -95,16 +89,11 @@ static char *progname; static char *short_opts = "a:b:c:d:hpk:tw:"; static const struct option long_opts[] = { /* name hasarg *flag val */ - {"auth_code", 1, NULL, 'a'}, - {"board_id", 1, NULL, 'b'}, - {"challenge", 1, NULL, 'c'}, - {"device_id", 1, NULL, 'd'}, - {"help", 0, NULL, 'h'}, - {"hw_id", 1, NULL, 'w'}, - {"key_id", 1, NULL, 'k'}, - {"p256", 0, NULL, 'p'}, - {"test", 0, NULL, 't'}, - {}, + { "auth_code", 1, NULL, 'a' }, { "board_id", 1, NULL, 'b' }, + { "challenge", 1, NULL, 'c' }, { "device_id", 1, NULL, 'd' }, + { "help", 0, NULL, 'h' }, { "hw_id", 1, NULL, 'w' }, + { "key_id", 1, NULL, 'k' }, { "p256", 0, NULL, 'p' }, + { "test", 0, NULL, 't' }, {}, }; void panic_assert_fail(const char *fname, int linenum); @@ -173,8 +162,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32], /* Extract public key into an octal array. */ EC_POINT_point2oct(group, EC_KEY_get0_public_key(key), - POINT_CONVERSION_UNCOMPRESSED, - buf, sizeof(buf), NULL); + POINT_CONVERSION_UNCOMPRESSED, buf, + sizeof(buf), NULL); /* If Y coordinate is an odd value, we are done. */ } while (!(buf[sizeof(buf) - 1] & 1)); @@ -195,8 +184,8 @@ static void p256_key_and_secret_seed(uint8_t pub_key[32], secret_point = EC_POINT_new(group); /* Multiply server public key by our private key. */ - EC_POINT_mul(group, secret_point, 0, pub, - EC_KEY_get0_private_key(key), 0); + EC_POINT_mul(group, secret_point, 0, pub, EC_KEY_get0_private_key(key), + 0); /* Pull the result back into the octal buffer. */ EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED, @@ -252,9 +241,8 @@ static void p256_calculate_secret(uint8_t secret[32], secret_point = EC_POINT_new(group); /* Multiply client's point by our private key. */ - EC_POINT_mul(group, secret_point, 0, - EC_KEY_get0_public_key(key), - priv, 0); + EC_POINT_mul(group, secret_point, 0, EC_KEY_get0_public_key(key), priv, + 0); /* Pull the result back into the octal buffer. */ EC_POINT_point2oct(group, secret_point, POINT_CONVERSION_UNCOMPRESSED, @@ -274,7 +262,7 @@ static int rma_server_side(const char *generated_challenge) /* Convert the challenge back into binary */ if (base32_decode(cptr, 8 * sizeof(c), generated_challenge, 9) != - 8 * sizeof(c)) { + 8 * sizeof(c)) { printf("Error decoding challenge\n"); return -1; } @@ -311,8 +299,8 @@ static int rma_server_side(const char *generated_challenge) * and DeviceID. */ hmac_SHA256(hmac, secret, sizeof(secret), cptr + 1, sizeof(c) - 1); - if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE, - hmac, RMA_AUTHCODE_CHARS * 5, 0)) { + if (base32_encode(authcode, RMA_AUTHCODE_BUF_SIZE, hmac, + RMA_AUTHCODE_CHARS * 5, 0)) { printf("Error encoding auth code\n"); return -1; } @@ -323,7 +311,7 @@ static int rma_server_side(const char *generated_challenge) static int rma_create_test_challenge(int p256_mode) { - uint8_t temp[32]; /* Private key or HMAC */ + uint8_t temp[32]; /* Private key or HMAC */ uint8_t secret_seed[32]; struct rma_challenge c; uint8_t *cptr = (uint8_t *)&c; @@ -334,8 +322,8 @@ static int rma_create_test_challenge(int p256_mode) memset(authcode, 0, sizeof(authcode)); memset(&c, 0, sizeof(c)); - c.version_key_id = RMA_CHALLENGE_VKID_BYTE( - RMA_CHALLENGE_VERSION, server_key_id); + c.version_key_id = + RMA_CHALLENGE_VKID_BYTE(RMA_CHALLENGE_VERSION, server_key_id); memcpy(&bid, board_id, sizeof(bid)); bid = be32toh(bid); @@ -361,8 +349,8 @@ static int rma_create_test_challenge(int p256_mode) * and DeviceID. Those are all in the right order in the challenge * struct, after the version/key id byte. */ - hmac_SHA256(temp, secret_seed, sizeof(secret_seed), - cptr + 1, sizeof(c) - 1); + hmac_SHA256(temp, secret_seed, sizeof(secret_seed), cptr + 1, + sizeof(c) - 1); if (base32_encode(authcode, sizeof(authcode), temp, RMA_AUTHCODE_CHARS * 5, 0)) return 1; @@ -382,7 +370,8 @@ static void dump_key(const char *title, const uint8_t *key, size_t key_size) printf("\n\n\%s\n", title); for (i = 0; i < key_size; i++) - printf("%02x%c", key[i], ((i + 1) % bytes_per_line) ? ' ':'\n'); + printf("%02x%c", key[i], + ((i + 1) % bytes_per_line) ? ' ' : '\n'); if (i % bytes_per_line) printf("\n"); @@ -453,25 +442,26 @@ static void usage(void) "--device_id --hw_id |\n" " --auth_code |\n" " --challenge \n" - "\n" - "This is used to generate the cr50 or server responses for rma " - "open.\n" - "The cr50 side can be used to generate a challenge response " - "and sends authoriztion code to reset device.\n" - "The server side can generate an authcode from cr50's " - "rma challenge.\n" - "\n" - " -c,--challenge The challenge generated by cr50\n" - " -k,--key_id Index of the server private key\n" - " -b,--board_id BoardID type field\n" - " -d,--device_id Device-unique identifier\n" - " -a,--auth_code Reset authorization code\n" - " -w,--hw_id Hardware id\n" - " -h,--help Show this message\n" - " -p,--p256 Use prime256v1 curve instead of x25519\n" - " -t,--test " - "Generate challenge using default test inputs\n" - "\n", progname); + "\n" + "This is used to generate the cr50 or server responses for rma " + "open.\n" + "The cr50 side can be used to generate a challenge response " + "and sends authoriztion code to reset device.\n" + "The server side can generate an authcode from cr50's " + "rma challenge.\n" + "\n" + " -c,--challenge The challenge generated by cr50\n" + " -k,--key_id Index of the server private key\n" + " -b,--board_id BoardID type field\n" + " -d,--device_id Device-unique identifier\n" + " -a,--auth_code Reset authorization code\n" + " -w,--hw_id Hardware id\n" + " -h,--help Show this message\n" + " -p,--p256 Use prime256v1 curve instead of x25519\n" + " -t,--test " + "Generate challenge using default test inputs\n" + "\n", + progname); } static int atoh(char *v) @@ -498,7 +488,7 @@ static int set_server_key_id(char *id) return 1; /* verify digits */ - if (!isxdigit(*id) || !isxdigit(*(id+1))) + if (!isxdigit(*id) || !isxdigit(*(id + 1))) return 1; server_key_id = atoh(id); @@ -520,7 +510,7 @@ static int set_board_id(char *id) return 1; for (i = 0; i < 4; i++) - board_id[i] = atoh((id + (i*2))); + board_id[i] = atoh((id + (i * 2))); return 0; } @@ -538,7 +528,7 @@ static int set_device_id(char *id) return 1; for (i = 0; i < 8; i++) - device_id[i] = atoh((id + (i*2))); + device_id[i] = atoh((id + (i * 2))); return 0; } @@ -635,14 +625,14 @@ int main(int argc, char **argv) case 'h': usage(); return 0; - case 0: /* auto-handled option */ + case 0: /* auto-handled option */ break; case '?': if (optopt) printf("Unrecognized option: -%c\n", optopt); else printf("Unrecognized option: %s\n", - argv[optind - 1]); + argv[optind - 1]); break; case ':': printf("Missing argument to %s\n", argv[optind - 1]); @@ -683,7 +673,7 @@ int main(int argc, char **argv) if (!k_flag || !b_flag || !d_flag || !w_flag) { printf("server-side: Flag -c is mandatory\n"); printf("cr50-side: Flags -k, -b, -d, and -w " - "are mandatory\n"); + "are mandatory\n"); return 1; } } -- cgit v1.2.1 From 36977e9a43ecec479d774b21bc58d86456cbff90 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:14:17 -0600 Subject: include/ocpc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ideaa568d9b8a86034436a512c218bd2c2b7f0d86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730371 Reviewed-by: Jeremy Bettis --- include/ocpc.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/include/ocpc.h b/include/ocpc.h index 3f7b08827f..b4041022bf 100644 --- a/include/ocpc.h +++ b/include/ocpc.h @@ -17,7 +17,7 @@ struct ocpc_data { int active_chg_chip; int combined_rsys_rbatt_mo; /* System resistance b/w output and Vbatt */ - int rsys_mo; /* System resistance b/w output and VSYS node */ + int rsys_mo; /* System resistance b/w output and VSYS node */ int rbatt_mo; /* Resistance between VSYS node and battery */ /* ADC values */ @@ -38,7 +38,7 @@ struct ocpc_data { #endif /* HAS_TASK_PD_C1 */ }; -#define OCPC_NO_ISYS_MEAS_CAP BIT(0) +#define OCPC_NO_ISYS_MEAS_CAP BIT(0) /** Set the VSYS target for the secondary charger IC. * @@ -49,8 +49,8 @@ struct ocpc_data { * @return EC_SUCCESS on success, error otherwise. */ int ocpc_config_secondary_charger(int *desired_input_current, - struct ocpc_data *ocpc, - int voltage_mv, int current_ma); + struct ocpc_data *ocpc, int voltage_mv, + int current_ma); /** Get the runtime data from the various ADCs. * @@ -59,9 +59,8 @@ int ocpc_config_secondary_charger(int *desired_input_current, void ocpc_get_adcs(struct ocpc_data *ocpc); /* Set the PID constants for the charging loop */ -__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div); +__overridable void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div); /* ** Set up some initial values for the OCPC data structure. This will call off -- cgit v1.2.1 From d36aebe60f84e6bbc16bb92430a54f74d1ad027f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:16 -0600 Subject: board/servo_v4p1/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c387da7cf79a4ff1b995ef0be42a929c99f61e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728935 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_pd_policy.c | 244 +++++++++++++++++++-------------------- 1 file changed, 117 insertions(+), 127 deletions(-) diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c index 26dc64c7d5..9dd4d113a7 100644 --- a/board/servo_v4p1/usb_pd_policy.c +++ b/board/servo_v4p1/usb_pd_policy.c @@ -26,57 +26,57 @@ #include "usb_pd_config.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) -#define DUT_PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ - PDO_FIXED_COMM_CAP) +#define DUT_PDO_FIXED_FLAGS \ + (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP | PDO_FIXED_COMM_CAP) #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP) -#define VBUS_UNCHANGED(curr, pend, new) (curr == new && pend == new) +#define VBUS_UNCHANGED(curr, pend, new) (curr == new &&pend == new) /* Macros to config the PD role */ #define CONF_SET_CLEAR(c, set, clear) ((c | (set)) & ~(clear)) -#define CONF_SRC(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_SNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) -#define CONF_PDSNK(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP) -#define CONF_DRP(c) CONF_SET_CLEAR(c, \ - CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_SNK_WITH_PD) -#define CONF_SRCDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC, \ - CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_SNKDTS(c) CONF_SET_CLEAR(c, \ - 0, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) -#define CONF_PDSNKDTS(c) CONF_SET_CLEAR(c, \ - CC_SNK_WITH_PD, \ - CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) -#define CONF_DRPDTS(c) CONF_SET_CLEAR(c, \ - CC_ALLOW_SRC | CC_ENABLE_DRP, \ - CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SRC(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_SNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_SNK_WITH_PD) +#define CONF_PDSNK(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP) +#define CONF_DRP(c) \ + CONF_SET_CLEAR(c, CC_DISABLE_DTS | CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_SNK_WITH_PD) +#define CONF_SRCDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC, \ + CC_ENABLE_DRP | CC_DISABLE_DTS | CC_SNK_WITH_PD) +#define CONF_SNKDTS(c) \ + CONF_SET_CLEAR(c, 0, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS | \ + CC_SNK_WITH_PD) +#define CONF_PDSNKDTS(c) \ + CONF_SET_CLEAR(c, CC_SNK_WITH_PD, \ + CC_ALLOW_SRC | CC_ENABLE_DRP | CC_DISABLE_DTS) +#define CONF_DRPDTS(c) \ + CONF_SET_CLEAR(c, CC_ALLOW_SRC | CC_ENABLE_DRP, \ + CC_DISABLE_DTS | CC_SNK_WITH_PD) /* Macros to apply Rd/Rp to CC lines */ -#define DUT_ACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC2_, r) : \ - CONCAT2(GPIO_USB_DUT_CC1_, r), \ +#define DUT_ACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC2_, r) : \ + CONCAT2(GPIO_USB_DUT_CC1_, r), \ flags) -#define DUT_INACTIVE_CC_SET(r, flags) \ - gpio_set_flags(cc_config & CC_POLARITY ? \ - CONCAT2(GPIO_USB_DUT_CC1_, r) : \ - CONCAT2(GPIO_USB_DUT_CC2_, r), \ +#define DUT_INACTIVE_CC_SET(r, flags) \ + gpio_set_flags(cc_config &CC_POLARITY ? \ + CONCAT2(GPIO_USB_DUT_CC1_, r) : \ + CONCAT2(GPIO_USB_DUT_CC2_, r), \ flags) -#define DUT_BOTH_CC_SET(r, flags) \ - do { \ +#define DUT_BOTH_CC_SET(r, flags) \ + do { \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC1_, r), flags); \ gpio_set_flags(CONCAT2(GPIO_USB_DUT_CC2_, r), flags); \ } while (0) @@ -98,15 +98,15 @@ * than 5V. */ static const uint16_t pd_src_voltages_mv[] = { - 5000, 9000, 10000, 12000, 15000, 20000, + 5000, 9000, 10000, 12000, 15000, 20000, }; static uint32_t pd_src_chg_pdo[ARRAY_SIZE(pd_src_voltages_mv)]; static uint8_t chg_pdo_cnt; const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), - PDO_BATT(4750, 21000, 15000), - PDO_VAR(4750, 21000, 3000), + PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); @@ -123,15 +123,15 @@ static int cc_config = CC_ALLOW_SRC | CC_EMCA_SERVO; /* Voltage thresholds for no connect in DTS mode */ static int pd_src_vnc_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV}, - {PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV}, - {PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV}, + { PD_SRC_3_0_VNC_MV, PD_SRC_1_5_VNC_MV }, + { PD_SRC_1_5_VNC_MV, PD_SRC_DEF_VNC_MV }, + { PD_SRC_3_0_VNC_MV, PD_SRC_DEF_VNC_MV }, }; /* Voltage thresholds for Ra attach in DTS mode */ static int pd_src_rd_threshold_dts[TYPEC_RP_RESERVED][2] = { - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV}, - {PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, - {PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV}, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_1_5_RD_THRESH_MV }, + { PD_SRC_1_5_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, + { PD_SRC_3_0_RD_THRESH_MV, PD_SRC_DEF_RD_THRESH_MV }, }; /* Voltage thresholds for no connect in normal SRC mode */ static int pd_src_vnc[TYPEC_RP_RESERVED] = { @@ -291,8 +291,8 @@ static void update_ports(void) break; /* Find the 'best' PDO <= voltage */ - pdo_index = - pd_find_pdo_index(pd_get_src_cap_cnt(CHG), + pdo_index = pd_find_pdo_index( + pd_get_src_cap_cnt(CHG), pd_get_src_caps(CHG), pd_src_voltages_mv[i], &pdo); /* Don't duplicate PDOs */ @@ -315,9 +315,9 @@ static void update_ports(void) } else { /* 5V PDO */ pd_src_chg_pdo[0] = PDO_FIXED_VOLT(PD_MIN_MV) | - PDO_FIXED_CURR(vbus[CHG].ma) | - DUT_PDO_FIXED_FLAGS | - PDO_FIXED_UNCONSTRAINED; + PDO_FIXED_CURR(vbus[CHG].ma) | + DUT_PDO_FIXED_FLAGS | + PDO_FIXED_UNCONSTRAINED; chg_pdo_cnt = 1; } @@ -342,8 +342,8 @@ int board_set_active_charge_port(int charge_port) return 0; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { if (port != CHG) return; @@ -389,8 +389,9 @@ int pd_tcpc_cc_nc(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) nc = cc_volt >= pd_src_vnc[rp_index]; else - nc = cc_volt >= pd_src_vnc_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + nc = cc_volt >= + pd_src_vnc_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : cc_sel]; return nc; } @@ -416,8 +417,10 @@ int pd_tcpc_cc_ra(int port, int cc_volt, int cc_sel) if (cc_config & CC_DISABLE_DTS) ra = cc_volt < pd_src_rd_threshold[rp_index]; else - ra = cc_volt < pd_src_rd_threshold_dts[rp_index][ - cc_config & CC_POLARITY ? !cc_sel : cc_sel]; + ra = cc_volt < + pd_src_rd_threshold_dts[rp_index] + [cc_config & CC_POLARITY ? !cc_sel : + cc_sel]; return ra; } @@ -459,13 +462,11 @@ int pd_adc_read(int port, int cc) * * This is basically a hack faking "vOpen" from TCPCI spec. */ - if ((cc_config & CC_DISABLE_DTS) && - port == DUT && + if ((cc_config & CC_DISABLE_DTS) && port == DUT && cc == ((cc_config & CC_POLARITY) ? 0 : 1)) { - - if ((cc_pull_stored == TYPEC_CC_RD) || - (cc_pull_stored == TYPEC_CC_RA) || - (cc_pull_stored == TYPEC_CC_RA_RD)) + if ((cc_pull_stored == TYPEC_CC_RD) || + (cc_pull_stored == TYPEC_CC_RA) || + (cc_pull_stored == TYPEC_CC_RA_RD)) mv = -1; else if (cc_pull_stored == TYPEC_CC_RP) mv = 3301; @@ -594,7 +595,7 @@ int pd_set_rp_rd(int port, int cc_pull, int rp_value) if (cc_pull == TYPEC_CC_RP) { rv = board_set_rp(rp_value); } else if ((cc_pull == TYPEC_CC_RD) || (cc_pull == TYPEC_CC_RA_RD) || - (cc_pull == TYPEC_CC_RA)) { + (cc_pull == TYPEC_CC_RA)) { /* * The DUT port uses a captive cable. It can present Rd on both * CC1 and CC2. If DTS mode is enabled, then present Rd on both @@ -673,7 +674,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port) * port, otherwise we provide no power. */ if (charge_port_is_active()) { - *src_pdo = pd_src_chg_pdo; + *src_pdo = pd_src_chg_pdo; pdo_cnt = chg_pdo_cnt; } @@ -697,8 +698,7 @@ __override void pd_transition_voltage(int idx) /* Wait for CHG transition */ deadline.val = get_time().val + PD_T_PS_TRANSITION; CPRINTS("Waiting for CHG port transition"); - while (charge_port_is_active() && - vbus[CHG].mv != mv && + while (charge_port_is_active() && vbus[CHG].mv != mv && get_time().val < deadline.val) msleep(10); @@ -760,8 +760,7 @@ void pd_power_supply_reset(int port) int pd_snk_is_vbus_provided(int port) { - return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : - GPIO_USB_DET_PP_CHG); + return gpio_get_level(port ? GPIO_USB_DET_PP_DUT : GPIO_USB_DET_PP_CHG); } __override int pd_check_power_swap(int port) @@ -778,7 +777,8 @@ __override int pd_check_power_swap(int port) if (port == CHG) return 0; - if (pd_get_power_role(port) == PD_ROLE_SINK && !(cc_config & CC_ALLOW_SRC)) + if (pd_get_power_role(port) == PD_ROLE_SINK && + !(cc_config & CC_ALLOW_SRC)) return 0; if (pd_snk_is_vbus_provided(CHG)) @@ -787,8 +787,7 @@ __override int pd_check_power_swap(int port) return 0; } -__override int pd_check_data_swap(int port, - enum pd_data_role data_role) +__override int pd_check_data_swap(int port, enum pd_data_role data_role) { /* * Servo should allow data role swaps to let DUT see the USB hub, but @@ -800,8 +799,7 @@ __override int pd_check_data_swap(int port, return allow_dr_swap; } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { if (port == CHG) return; @@ -838,12 +836,12 @@ __override void pd_execute_data_swap(int port, uservo_to_host(); break; default: - CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__, data_role); + CPRINTS("C%d: %s: Invalid data_role:%d", port, __func__, + data_role); } } -__override void pd_check_pr_role(int port, - enum pd_power_role pr_role, +__override void pd_check_pr_role(int port, enum pd_power_role pr_role, int flags) { /* @@ -854,9 +852,7 @@ __override void pd_check_pr_role(int port, */ } -__override void pd_check_dr_role(int port, - enum pd_data_role dr_role, - int flags) +__override void pd_check_dr_role(int port, enum pd_data_role dr_role, int flags) { if (port == CHG) return; @@ -866,15 +862,14 @@ __override void pd_check_dr_role(int port, pd_request_data_swap(port); } - /* ----------------- Vendor Defined Messages ------------------ */ /* * DP alt-mode config, user configurable. * Default is the mode disabled, supporting the C and D pin assignment, * multi-function preferred, and a plug. */ -static int alt_dp_config = (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | - ALT_DP_PLUG); +static int alt_dp_config = + (ALT_DP_PIN_C | ALT_DP_PIN_D | ALT_DP_MF_PREF | ALT_DP_PLUG); /** * Get the pins based on the user config. @@ -907,8 +902,8 @@ const uint32_t vdo_idh = VDO_IDH(0, /* data caps as USB host */ const uint32_t vdo_product = VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); const uint32_t vdo_ama = VDO_AMA(CONFIG_USB_PD_IDENTITY_HW_VERS, - CONFIG_USB_PD_IDENTITY_SW_VERS, - 0, 0, 0, 0, /* SS[TR][12] */ + CONFIG_USB_PD_IDENTITY_SW_VERS, 0, 0, 0, + 0, /* SS[TR][12] */ 0, /* Vconn power */ 0, /* Vconn power required */ 0, /* Vbus power required */ @@ -946,13 +941,13 @@ uint32_t vdo_dp_mode[MODE_CNT]; static int svdm_response_modes(int port, uint32_t *payload) { - vdo_dp_mode[0] = - VDO_MODE_DP(0, /* UFP pin cfg supported: none */ - alt_dp_config_pins(), /* DFP pin */ - 1, /* no usb2.0 signalling in AMode */ - alt_dp_config_cable(), /* plug or receptacle */ - MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ - MODE_DP_SNK); /* Its a sink only */ + vdo_dp_mode[0] = VDO_MODE_DP(0, /* UFP pin cfg supported: none */ + alt_dp_config_pins(), /* DFP pin */ + 1, /* no usb2.0 signalling in AMode */ + alt_dp_config_cable(), /* plug or + receptacle */ + MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ + MODE_DP_SNK); /* Its a sink only */ /* CCD uses the SBU lines; don't enable DP when dts-mode enabled */ if (!(cc_config & CC_DISABLE_DTS)) @@ -1007,17 +1002,17 @@ static int dp_status(int port, uint32_t *payload) int dp_enabled = !!(state & USB_PD_MUX_DP_ENABLED); if (opos != OPOS) - return 0; /* NAK */ - - payload[1] = VDO_DP_STATUS( - 0, /* IRQ_HPD */ - hpd, /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF pref */ - dp_enabled, - 0, /* power low */ - hpd ? 0x2 : 0); + return 0; /* NAK */ + + payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ + hpd, /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF + pref + */ + dp_enabled, 0, /* power low */ + hpd ? 0x2 : 0); return 2; } @@ -1038,7 +1033,7 @@ static int svdm_enter_mode(int port, uint32_t *payload) /* SID & mode request is valid */ if ((PD_VDO_VID(payload[0]) != USB_SID_DISPLAYPORT) || (PD_VDO_OPOS(payload[0]) != OPOS)) - return 0; /* NAK */ + return 0; /* NAK */ alt_mode = OPOS; return 1; @@ -1080,7 +1075,7 @@ const struct svdm_response svdm_rsp = { }; __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, - uint32_t **rpayload) + uint32_t **rpayload) { int cmd = PD_VDO_CMD(payload[0]); @@ -1092,7 +1087,7 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, case VDO_CMD_VERSION: /* guarantee last byte of payload is null character */ *(payload + cnt - 1) = 0; - CPRINTF("ver: %s\n", (char *)(payload+1)); + CPRINTF("ver: %s\n", (char *)(payload + 1)); break; case VDO_CMD_CURRENT: CPRINTF("Current: %dmA\n", payload[1]); @@ -1110,18 +1105,15 @@ static void print_cc_mode(void) /* Get current CCD status */ ccprintf("cc: %s\n", cc_config & CC_DETACH ? "off" : "on"); ccprintf("dts mode: %s\n", cc_config & CC_DISABLE_DTS ? "off" : "on"); - ccprintf("chg mode: %s\n", - get_dut_chg_en() ? "on" : "off"); + ccprintf("chg mode: %s\n", get_dut_chg_en() ? "on" : "off"); ccprintf("chg allowed: %s\n", cc_config & CC_ALLOW_SRC ? "on" : "off"); ccprintf("drp enabled: %s\n", cc_config & CC_ENABLE_DRP ? "on" : "off"); - ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : - "cc1"); + ccprintf("cc polarity: %s\n", cc_config & CC_POLARITY ? "cc2" : "cc1"); ccprintf("pd enabled: %s\n", pd_comm_is_enabled(DUT) ? "on" : "off"); - ccprintf("emca: %s\n", cc_config & CC_EMCA_SERVO ? - "emarked" : "non-emarked"); + ccprintf("emca: %s\n", + cc_config & CC_EMCA_SERVO ? "emarked" : "non-emarked"); } - static void do_cc(int cc_config_new) { int chargeable; @@ -1287,8 +1279,8 @@ static int cmd_fake_disconnect(int argc, char *argv[]) fake_pd_disconnect_duration_us = duration_ms * MSEC; hook_call_deferred(&fake_disconnect_start_data, delay_ms * MSEC); - ccprintf("Fake disconnect for %d ms starting in %d ms.\n", - duration_ms, delay_ms); + ccprintf("Fake disconnect for %d ms starting in %d ms.\n", duration_ms, + delay_ms); return EC_SUCCESS; } @@ -1298,7 +1290,7 @@ DECLARE_CONSOLE_COMMAND(fakedisconnect, cmd_fake_disconnect, static int cmd_ada_srccaps(int argc, char *argv[]) { int i; - const uint32_t * const ada_srccaps = pd_get_src_caps(CHG); + const uint32_t *const ada_srccaps = pd_get_src_caps(CHG); for (i = 0; i < pd_get_src_cap_cnt(CHG); ++i) { uint32_t max_ma, max_mv, unused; @@ -1314,8 +1306,7 @@ static int cmd_ada_srccaps(int argc, char *argv[]) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, - "", +DECLARE_CONSOLE_COMMAND(ada_srccaps, cmd_ada_srccaps, "", "Print adapter SrcCap"); static int cmd_dp_action(int argc, char *argv[]) @@ -1354,8 +1345,7 @@ static int cmd_dp_action(int argc, char *argv[]) } } } - CPRINTS("Pins: %s%s", - (alt_dp_config & ALT_DP_PIN_C) ? "C" : "", + CPRINTS("Pins: %s%s", (alt_dp_config & ALT_DP_PIN_C) ? "C" : "", (alt_dp_config & ALT_DP_PIN_D) ? "D" : ""); } else if (!strcasecmp(argv[1], "mf")) { if (argc >= 3) { @@ -1405,10 +1395,10 @@ static int cmd_dp_action(int argc, char *argv[]) } } CPRINTS("HPD source: %s", - (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" - : "external"); + (alt_dp_config & ALT_DP_OVERRIDE_HPD) ? "overridden" : + "external"); CPRINTS("HPD level: %d", get_hpd_level()); - } else if (!strcasecmp(argv[1], "help")) { + } else if (!strcasecmp(argv[1], "help")) { CPRINTS("Usage: usbc_action dp [enable|disable|hpd|mf|pins|" "plug]"); } -- cgit v1.2.1 From d7983ddec12b7c5abb0f2833002eea959c56b58a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:24 -0600 Subject: board/dalboz/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib865f28e0864a4382df5a48109df886a347007e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728217 Reviewed-by: Jeremy Bettis --- board/dalboz/board.c | 39 +++++++++++++-------------------------- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/board/dalboz/board.c b/board/dalboz/board.c index e8690d5cc1..4be54125b4 100644 --- a/board/dalboz/board.c +++ b/board/dalboz/board.c @@ -36,8 +36,8 @@ #include "usb_pd_tcpm.h" #include "usbc_ppc.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* This I2C moved. Temporarily detect and support the V0 HW. */ int I2C_PORT_BATTERY = I2C_PORT_BATTERY_V1; @@ -84,11 +84,9 @@ static struct stprivate_data g_lis2dwl_data; static struct lsm6dsm_data g_lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ struct motion_sensor_t motion_sensors[] = { @@ -203,9 +201,7 @@ static void board_chipset_resume(void) if (ec_config_has_hdmi_retimer_pi3hdx1204()) { ioex_set_level(IOEX_EN_PWR_HDMI_DB, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 1); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 1); } } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -215,16 +211,13 @@ static void board_chipset_suspend(void) ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0); if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); ioex_set_level(IOEX_EN_PWR_HDMI_DB, 0); } } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); -static int board_ps8743_mux_set(const struct usb_mux *me, - mux_state_t mux_state) +static int board_ps8743_mux_set(const struct usb_mux *me, mux_state_t mux_state) { if (mux_state & USB_PD_MUX_DP_ENABLED) /* Enable IN_HPD on the DB */ @@ -236,7 +229,6 @@ static int board_ps8743_mux_set(const struct usb_mux *me, return EC_SUCCESS; } - /***************************************************************************** * USB-C */ @@ -343,8 +335,7 @@ void ppc_interrupt(enum gpio_signal signal) int board_set_active_charge_port(int port) { - int is_valid_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; if (port == CHARGE_PORT_NONE) { @@ -365,7 +356,6 @@ int board_set_active_charge_port(int port) return EC_ERROR_INVAL; } - /* Check if the port is sourcing VBUS. */ if (ppc_is_sourcing_vbus(port)) { CPRINTFUSB("Skip enable C%d", port); @@ -467,7 +457,6 @@ static void reset_nct38xx_port(int port) msleep(NCT3807_RESET_POST_DELAY_MS); } - void board_reset_pd_mcu(void) { /* Reset TCPC0 */ @@ -538,11 +527,9 @@ int board_pd_set_frs_enable(int port, int enable) /* Use the TCPC to enable fast switch when FRS included */ if (port == USBC_PORT_C0) { - rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, !!enable); } else { - rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, - !!enable); + rv = ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, !!enable); } return rv; @@ -552,8 +539,8 @@ static void setup_fw_config(void) { uint32_t board_version = 0; - if (cbi_get_board_version(&board_version) == EC_SUCCESS - && board_version >= 2) { + if (cbi_get_board_version(&board_version) == EC_SUCCESS && + board_version >= 2) { ccprints("PS8743 USB MUX"); usb_muxes[USBC_PORT_C1].i2c_addr_flags = PS8743_I2C_ADDR1_FLAG; usb_muxes[USBC_PORT_C1].driver = &ps8743_usb_mux_driver; -- cgit v1.2.1 From cc141b22b3292d2a088060c2fb103ff2b30109a7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:49 -0600 Subject: zephyr/projects/corsola/src/krabby/led_tentacruel.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I86c540b58eb95d54f20f02ce91576775878d614a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730744 Reviewed-by: Jeremy Bettis --- .../projects/corsola/src/krabby/led_tentacruel.c | 58 +++++++++++++--------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/led_tentacruel.c b/zephyr/projects/corsola/src/krabby/led_tentacruel.c index e7416d6dd7..e1f0d11575 100644 --- a/zephyr/projects/corsola/src/krabby/led_tentacruel.c +++ b/zephyr/projects/corsola/src/krabby/led_tentacruel.c @@ -30,30 +30,40 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -75,8 +85,8 @@ static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); - LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", - ch->dev->name, percent, pulse_ns); + LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, + percent, pulse_ns); rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, ch->flags); -- cgit v1.2.1 From 06ce7061c98995e41fcaf5ee7e6839ebfa0017b2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:44 -0600 Subject: driver/temp_sensor/adt7481.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ida9d6b7dfb4f037da799055e422a66cc847c0d7d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730111 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/adt7481.h | 186 +++++++++++++++++++++---------------------- 1 file changed, 92 insertions(+), 94 deletions(-) diff --git a/driver/temp_sensor/adt7481.h b/driver/temp_sensor/adt7481.h index 78541a0a3b..8c63b679fb 100644 --- a/driver/temp_sensor/adt7481.h +++ b/driver/temp_sensor/adt7481.h @@ -8,120 +8,118 @@ #ifndef __CROS_EC_ADT7481_H #define __CROS_EC_ADT7481_H -#define ADT7481_I2C_ADDR_FLAGS 0x4B +#define ADT7481_I2C_ADDR_FLAGS 0x4B -#define ADT7481_IDX_LOCAL 0 -#define ADT7481_IDX_REMOTE1 1 -#define ADT7481_IDX_REMOTE2 2 +#define ADT7481_IDX_LOCAL 0 +#define ADT7481_IDX_REMOTE1 1 +#define ADT7481_IDX_REMOTE2 2 /* Chip-specific registers */ -#define ADT7481_LOCAL 0x00 -#define ADT7481_REMOTE1 0x01 -#define ADT7481_STATUS1_R 0x02 -#define ADT7481_CONFIGURATION1_R 0x03 -#define ADT7481_CONVERSION_RATE_R 0x04 -#define ADT7481_LOCAL_HIGH_LIMIT_R 0x05 -#define ADT7481_LOCAL_LOW_LIMIT_R 0x06 -#define ADT7481_REMOTE1_HIGH_LIMIT_R 0x07 -#define ADT7481_REMOTE1_LOW_LIMIT_R 0x08 -#define ADT7481_CONFIGURATION1_W 0x09 -#define ADT7481_CONVERSION_RATE_W 0x0a -#define ADT7481_LOCAL_HIGH_LIMIT_W 0x0b -#define ADT7481_LOCAL_LOW_LIMIT_W 0x0c -#define ADT7481_REMOTE1_HIGH_LIMIT_W 0x0d -#define ADT7481_REMOTE1_LOW_LIMIT_W 0x0e -#define ADT7481_ONESHOT_W 0x0f -#define ADT7481_REMOTE1_EXTD_R 0x10 -#define ADT7481_REMOTE1_OFFSET 0x11 -#define ADT7481_REMOTE1_OFFSET_EXTD 0x12 -#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD 0x13 -#define ADT7481_REMOTE1_LOW_LIMIT_EXTD 0x14 -#define ADT7481_REMOTE1_THERM_LIMIT 0x19 -#define ADT7481_LOCAL_THERM_LIMIT 0x20 -#define ADT7481_THERM_HYSTERESIS 0x21 -#define ADT7481_CONSECUTIVE_ALERT 0x22 -#define ADT7481_STATUS2_R 0x23 -#define ADT7481_CONFIGURATION2 0x24 -#define ADT7481_REMOTE2 0x30 -#define ADT7481_REMOTE2_HIGH_LIMIT 0x31 -#define ADT7481_REMOTE2_LOW_LIMIT 0x32 -#define ADT7481_REMOTE2_EXTD_R 0x33 -#define ADT7481_REMOTE2_OFFSET 0x34 -#define ADT7481_REMOTE2_OFFSET_EXTD 0x35 -#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD 0x36 -#define ADT7481_REMOTE2_LOW_LIMIT_EXTD 0x37 -#define ADT7481_REMOTE2_THERM_LIMIT 0x39 -#define ADT7481_DEVICE_ID 0x3d -#define ADT7481_MANUFACTURER_ID 0x3e +#define ADT7481_LOCAL 0x00 +#define ADT7481_REMOTE1 0x01 +#define ADT7481_STATUS1_R 0x02 +#define ADT7481_CONFIGURATION1_R 0x03 +#define ADT7481_CONVERSION_RATE_R 0x04 +#define ADT7481_LOCAL_HIGH_LIMIT_R 0x05 +#define ADT7481_LOCAL_LOW_LIMIT_R 0x06 +#define ADT7481_REMOTE1_HIGH_LIMIT_R 0x07 +#define ADT7481_REMOTE1_LOW_LIMIT_R 0x08 +#define ADT7481_CONFIGURATION1_W 0x09 +#define ADT7481_CONVERSION_RATE_W 0x0a +#define ADT7481_LOCAL_HIGH_LIMIT_W 0x0b +#define ADT7481_LOCAL_LOW_LIMIT_W 0x0c +#define ADT7481_REMOTE1_HIGH_LIMIT_W 0x0d +#define ADT7481_REMOTE1_LOW_LIMIT_W 0x0e +#define ADT7481_ONESHOT_W 0x0f +#define ADT7481_REMOTE1_EXTD_R 0x10 +#define ADT7481_REMOTE1_OFFSET 0x11 +#define ADT7481_REMOTE1_OFFSET_EXTD 0x12 +#define ADT7481_REMOTE1_HIGH_LIMIT_EXTD 0x13 +#define ADT7481_REMOTE1_LOW_LIMIT_EXTD 0x14 +#define ADT7481_REMOTE1_THERM_LIMIT 0x19 +#define ADT7481_LOCAL_THERM_LIMIT 0x20 +#define ADT7481_THERM_HYSTERESIS 0x21 +#define ADT7481_CONSECUTIVE_ALERT 0x22 +#define ADT7481_STATUS2_R 0x23 +#define ADT7481_CONFIGURATION2 0x24 +#define ADT7481_REMOTE2 0x30 +#define ADT7481_REMOTE2_HIGH_LIMIT 0x31 +#define ADT7481_REMOTE2_LOW_LIMIT 0x32 +#define ADT7481_REMOTE2_EXTD_R 0x33 +#define ADT7481_REMOTE2_OFFSET 0x34 +#define ADT7481_REMOTE2_OFFSET_EXTD 0x35 +#define ADT7481_REMOTE2_HIGH_LIMIT_EXTD 0x36 +#define ADT7481_REMOTE2_LOW_LIMIT_EXTD 0x37 +#define ADT7481_REMOTE2_THERM_LIMIT 0x39 +#define ADT7481_DEVICE_ID 0x3d +#define ADT7481_MANUFACTURER_ID 0x3e /* Config1 register bits */ -#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0) -#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1) -#define ADT7481_CONFIG1_TEMP_RANGE BIT(2) -#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3) +#define ADT7481_CONFIG1_REMOTE1_ALERT_MASK BIT(0) +#define ADT7481_CONFIG1_REMOTE2_ALERT_MASK BIT(1) +#define ADT7481_CONFIG1_TEMP_RANGE BIT(2) +#define ADT7481_CONFIG1_SEL_REMOTE2 BIT(3) /* ADT7481_CONFIG1_MODE bit is use to enable THERM mode */ -#define ADT7481_CONFIG1_MODE BIT(5) -#define ADT7481_CONFIG1_RUN_L BIT(6) +#define ADT7481_CONFIG1_MODE BIT(5) +#define ADT7481_CONFIG1_RUN_L BIT(6) /* mask all alerts on ALERT# pin */ -#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7) +#define ADT7481_CONFIG1_ALERT_MASK_L BIT(7) /* Config2 register bits */ -#define ADT7481_CONFIG2_LOCK BIT(7) +#define ADT7481_CONFIG2_LOCK BIT(7) /* Conversion Rate/Channel Select Register */ -#define ADT7481_CONV_RATE_MASK (0x0f) -#define ADT7481_CONV_RATE_16S (0x00) -#define ADT7481_CONV_RATE_8S (0x01) -#define ADT7481_CONV_RATE_4S (0x02) -#define ADT7481_CONV_RATE_2S (0x03) -#define ADT7481_CONV_RATE_1S (0x04) -#define ADT7481_CONV_RATE_500MS (0x05) -#define ADT7481_CONV_RATE_250MS (0x06) -#define ADT7481_CONV_RATE_125MS (0x07) -#define ADT7481_CONV_RATE_62500US (0x08) -#define ADT7481_CONV_RATE_31250US (0x09) -#define ADT7481_CONV_RATE_15500US (0x0a) +#define ADT7481_CONV_RATE_MASK (0x0f) +#define ADT7481_CONV_RATE_16S (0x00) +#define ADT7481_CONV_RATE_8S (0x01) +#define ADT7481_CONV_RATE_4S (0x02) +#define ADT7481_CONV_RATE_2S (0x03) +#define ADT7481_CONV_RATE_1S (0x04) +#define ADT7481_CONV_RATE_500MS (0x05) +#define ADT7481_CONV_RATE_250MS (0x06) +#define ADT7481_CONV_RATE_125MS (0x07) +#define ADT7481_CONV_RATE_62500US (0x08) +#define ADT7481_CONV_RATE_31250US (0x09) +#define ADT7481_CONV_RATE_15500US (0x0a) /* continuous mode 73 ms averaging */ -#define ADT7481_CONV_RATE_73MS_AVE (0x0b) -#define ADT7481_CONV_CHAN_SELECT_MASK (0x30) -#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4) -#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4) -#define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4) -#define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4) -#define ADT7481_CONV_AVERAGING_L BIT(7) - +#define ADT7481_CONV_RATE_73MS_AVE (0x0b) +#define ADT7481_CONV_CHAN_SELECT_MASK (0x30) +#define ADT7481_CONV_CHAN_SEL_ROUND_ROBIN (0 << 4) +#define ADT7481_CONV_CHAN_SEL_LOCAL BIT(4) +#define ADT7481_CONV_CHAN_SEL_REMOTE1 (2 << 4) +#define ADT7481_CONV_CHAN_SEL_REMOTE2 (3 << 4) +#define ADT7481_CONV_AVERAGING_L BIT(7) /* Status1 register bits */ -#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0) -#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1) -#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2) -#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3) -#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4) -#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5) -#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6) -#define ADT7481_STATUS1_BUSY BIT(7) +#define ADT7481_STATUS1_LOCAL_THERM_ALARM BIT(0) +#define ADT7481_STATUS1_REMOTE1_THERM_ALARM BIT(1) +#define ADT7481_STATUS1_REMOTE1_OPEN BIT(2) +#define ADT7481_STATUS1_REMOTE1_LOW_ALARM BIT(3) +#define ADT7481_STATUS1_REMOTE1_HIGH_ALARM BIT(4) +#define ADT7481_STATUS1_LOCAL_LOW_ALARM BIT(5) +#define ADT7481_STATUS1_LOCAL_HIGH_ALARM BIT(6) +#define ADT7481_STATUS1_BUSY BIT(7) /* Status2 register bits */ -#define ADT7481_STATUS2_ALERT BIT(0) -#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1) -#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2) -#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3) -#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4) +#define ADT7481_STATUS2_ALERT BIT(0) +#define ADT7481_STATUS2_REMOTE2_THERM_ALARM BIT(1) +#define ADT7481_STATUS2_REMOTE2_OPEN BIT(2) +#define ADT7481_STATUS2_REMOTE2_LOW_ALARM BIT(3) +#define ADT7481_STATUS2_REMOTE2_HIGH_ALARM BIT(4) /* Consecutive Alert register */ -#define ADT7481_CONSEC_MASK (0xf) -#define ADT7481_CONSEC_1 (0x0) -#define ADT7481_CONSEC_2 (0x2) -#define ADT7481_CONSEC_3 (0x6) -#define ADT7481_CONSEC_4 (0xe) -#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5) -#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6) -#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7) - +#define ADT7481_CONSEC_MASK (0xf) +#define ADT7481_CONSEC_1 (0x0) +#define ADT7481_CONSEC_2 (0x2) +#define ADT7481_CONSEC_3 (0x6) +#define ADT7481_CONSEC_4 (0xe) +#define ADT7481_CONSEC_EN_SCL_TIMEOUT BIT(5) +#define ADT7481_CONSEC_EN_SDA_TIMEOUT BIT(6) +#define ADT7481_CONSEC_MASK_LOCAL_ALERT BIT(7) /* Limits */ -#define ADT7481_HYSTERESIS_HIGH_LIMIT 255 -#define ADT7481_HYSTERESIS_LOW_LIMIT 0 +#define ADT7481_HYSTERESIS_HIGH_LIMIT 255 +#define ADT7481_HYSTERESIS_LOW_LIMIT 0 enum adt7481_power_state { ADT7481_POWER_OFF = 0, -- cgit v1.2.1 From 3a0d371574373fe5fa5f64d6c28a94de415bf19e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:39 -0600 Subject: board/reef_it8320/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c4e84ef9c96db8b3ca25625bc925c62ca6b6f7b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728888 Reviewed-by: Jeremy Bettis --- board/reef_it8320/board.c | 111 +++++++++++++++++++++------------------------- 1 file changed, 50 insertions(+), 61 deletions(-) diff --git a/board/reef_it8320/board.c b/board/reef_it8320/board.c index 1b6bc3d137..ccd2aac7ca 100644 --- a/board/reef_it8320/board.c +++ b/board/reef_it8320/board.c @@ -48,50 +48,40 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) -#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) +#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) #include "gpio_list.h" const struct adc_t adc_channels[] = { /* Convert to mV (3000mV/1024). */ - {"CHARGER", 3000, 1024, 0, CHIP_ADC_CH1}, /* GPI1 */ - {"AMBIENT", 3000, 1024, 0, CHIP_ADC_CH2}, /* GPI2 */ - {"BRD_ID", 3000, 1024, 0, CHIP_ADC_CH3}, /* GPI3 */ + { "CHARGER", 3000, 1024, 0, CHIP_ADC_CH1 }, /* GPI1 */ + { "AMBIENT", 3000, 1024, 0, CHIP_ADC_CH2 }, /* GPI2 */ + { "BRD_ID", 3000, 1024, 0, CHIP_ADC_CH3 }, /* GPI3 */ }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "mux", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_EC_I2C_C_SCL, - .sda = GPIO_EC_I2C_C_SDA - }, - { - .name = "batt", - .port = IT83XX_I2C_CH_E, - .kbps = 100, - .scl = GPIO_EC_I2C_E_SCL, - .sda = GPIO_EC_I2C_E_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "mux", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_EC_I2C_C_SCL, + .sda = GPIO_EC_I2C_C_SDA }, + { .name = "batt", + .port = IT83XX_I2C_CH_E, + .kbps = 100, + .scl = GPIO_EC_I2C_E_SCL, + .sda = GPIO_EC_I2C_E_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - .drv = &it83xx_tcpm_drv - }, - { - .bus_type = EC_BUS_TYPE_EMBEDDED, - .drv = &it83xx_tcpm_drv - }, + { .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv }, + { .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it83xx_tcpm_drv }, }; void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) @@ -126,9 +116,8 @@ static void it83xx_tcpc_update_hpd_status(const struct usb_mux *me, { int hpd_lvl = (mux_state & USB_PD_MUX_HPD_LVL) ? 1 : 0; int hpd_irq = (mux_state & USB_PD_MUX_HPD_IRQ) ? 1 : 0; - enum gpio_signal gpio = - me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL - : GPIO_USB_C0_HPD_1P8_ODL; + enum gpio_signal gpio = me->usb_port ? GPIO_USB_C1_HPD_1P8_ODL : + GPIO_USB_C0_HPD_1P8_ODL; /* This driver does not use host command ACKs */ *ack_required = false; @@ -165,18 +154,18 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { }; const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -234,12 +223,12 @@ static void board_init(void) gpio_enable_interrupt(GPIO_CHARGER_INT_L); /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_I2C + 1); @@ -303,8 +292,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Enable charging trigger by BC1.2 detection */ int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP || @@ -316,8 +305,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, return; charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -406,17 +395,17 @@ void board_hibernate_late(void) int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs in hibernate */ - {GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN}, + { GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN }, /* * BD99956 handles charge input automatically. We'll disable * charge output in hibernate. Charger will assert ACOK_OD * when VBUS or VCC are plugged in. */ - {GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, - {GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + { GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, + { GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, }; /* Change GPIOs' state in hibernate for better power consumption */ @@ -447,8 +436,8 @@ struct { int thresh_mv; } const reef_it8320_board_versions[] = { /* Vin = 3.3V, R1 = 46.4K, R2 values listed below */ - { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ - { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ + { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ + { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ { BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */ { BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */ { BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */ -- cgit v1.2.1 From f73de40965f26dbede4f406a4b2511d672901d51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:19 -0600 Subject: zephyr/projects/nissa/src/pujjo/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24dac2852d2ab9d2d6be6b47f2592a37aef93f61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730795 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/pujjo/fan.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/zephyr/projects/nissa/src/pujjo/fan.c b/zephyr/projects/nissa/src/pujjo/fan.c index 8914774452..1884380de8 100644 --- a/zephyr/projects/nissa/src/pujjo/fan.c +++ b/zephyr/projects/nissa/src/pujjo/fan.c @@ -28,8 +28,7 @@ static void fan_init(void) */ ret = cros_cbi_get_fw_config(FW_FAN, &val); if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", - FW_FAN); + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); return; } if (val != FW_FAN_PRESENT) { @@ -37,9 +36,8 @@ static void fan_init(void) fan_set_count(0); } else { /* Configure the fan enable GPIO */ - gpio_pin_configure_dt( - GPIO_DT_FROM_NODELABEL(gpio_fan_enable), - GPIO_OUTPUT); + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); } } DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); -- cgit v1.2.1 From f6bb860c31b7a4ed4aef73333137186f35451bb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:33 -0600 Subject: board/nautilus/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibfa62ad45169851f18de1fb8e667d85f02fff137 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728725 Reviewed-by: Jeremy Bettis --- board/nautilus/usb_pd_policy.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/board/nautilus/usb_pd_policy.c b/board/nautilus/usb_pd_policy.c index be4716b860..1129fd9cb2 100644 --- a/board/nautilus/usb_pd_policy.c +++ b/board/nautilus/usb_pd_policy.c @@ -21,12 +21,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -47,8 +47,8 @@ static void board_vbus_update_source_current(int port) * is controlled by GPIO_USB_C0/1_5V_EN. Both of these signals * can remain outputs. */ - gpio_set_level(gpio_3a_en, vbus_rp[port] == TYPEC_RP_3A0 ? - 1 : 0); + gpio_set_level(gpio_3a_en, + vbus_rp[port] == TYPEC_RP_3A0 ? 1 : 0); gpio_set_level(gpio_5v_en, vbus_en[port]); } else { /* @@ -60,8 +60,8 @@ static void board_vbus_update_source_current(int port) * 1505 mA. */ int flags = (vbus_rp[port] == TYPEC_RP_1A5 && vbus_en[port]) ? - (GPIO_INPUT | GPIO_PULL_UP) : - (GPIO_OUTPUT | GPIO_PULL_UP); + (GPIO_INPUT | GPIO_PULL_UP) : + (GPIO_OUTPUT | GPIO_PULL_UP); gpio_set_level(gpio_5v_en, vbus_en[port]); gpio_set_flags(gpio_5v_en, flags); } @@ -78,8 +78,7 @@ __override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : - GPIO_USB_C0_CHARGE_L, 1); + gpio_set_level(port ? GPIO_USB_C1_CHARGE_L : GPIO_USB_C0_CHARGE_L, 1); /* Ensure we advertise the proper available current quota */ charge_manager_source_port(port, 1); @@ -124,22 +123,19 @@ int pd_snk_is_vbus_provided(int port) GPIO_USB_C0_VBUS_WAKE_L); } - int pd_check_vconn_swap(int port) { /* in G3, do not allow vconn swap since pp5000_A rail is off */ return gpio_get_level(GPIO_PMIC_SLP_SUS_L); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) return; - gpio_set_level(GPIO_USB2_OTG_ID, - (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_OTG_ID, (data_role == PD_ROLE_UFP) ? 1 : 0); gpio_set_level(GPIO_USB2_OTG_VBUSSENSE, - (data_role == PD_ROLE_UFP) ? 1 : 0); + (data_role == PD_ROLE_UFP) ? 1 : 0); } -- cgit v1.2.1 From bcb65ea2f5b722cc982f2a6ed09983ef5c0af8b4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:07 -0600 Subject: common/uptime.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3723102e4f5aeeeb7a04e86db5f9a0ee48eae168 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729524 Reviewed-by: Jeremy Bettis --- common/uptime.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/common/uptime.c b/common/uptime.c index 3c3be3e55c..c8e914a6cc 100644 --- a/common/uptime.c +++ b/common/uptime.c @@ -32,14 +32,12 @@ host_command_get_uptime_info(struct host_cmd_handler_args *args) r->ec_reset_flags = system_get_reset_flags(); memset(r->recent_ap_reset, 0, sizeof(r->recent_ap_reset)); - rc = get_ap_reset_stats(recent_ap_reset, - ARRAY_SIZE(r->recent_ap_reset), + rc = get_ap_reset_stats(recent_ap_reset, ARRAY_SIZE(r->recent_ap_reset), &ap_resets_since_ec_boot); r->ap_resets_since_ec_boot = ap_resets_since_ec_boot; args->response_size = sizeof(*r); return rc == EC_SUCCESS ? EC_RES_SUCCESS : EC_RES_ERROR; } -DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO, - host_command_get_uptime_info, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_GET_UPTIME_INFO, host_command_get_uptime_info, + EC_VER_MASK(0)); -- cgit v1.2.1 From 337e8399e80a77d0f01a6aabbe8e8e1ac358628e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:11 -0600 Subject: core/cortex-m0/panic-internal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I228e1a10653b598fec1853efe37d4ef5f6eab468 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729832 Reviewed-by: Jeremy Bettis --- core/cortex-m0/panic-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m0/panic-internal.h b/core/cortex-m0/panic-internal.h index 51c12f65b2..6ed70d7db0 100644 --- a/core/cortex-m0/panic-internal.h +++ b/core/cortex-m0/panic-internal.h @@ -10,4 +10,4 @@ noreturn void exception_panic(void) __attribute__((naked)); -#endif /* __CROS_EC_PANIC_INTERNAL_H */ +#endif /* __CROS_EC_PANIC_INTERNAL_H */ -- cgit v1.2.1 From f2404f86b75008498beb622f42e7de13c545184c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:54 -0600 Subject: fuzz/fuzz_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3883c53b1905ab400f386cc2950e4a8e5d4859dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730192 Reviewed-by: Jeremy Bettis --- fuzz/fuzz_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fuzz/fuzz_config.h b/fuzz/fuzz_config.h index fb974ea727..f5fb4f66e1 100644 --- a/fuzz/fuzz_config.h +++ b/fuzz/fuzz_config.h @@ -90,11 +90,11 @@ #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO #define CONFIG_PERIPHERAL_CHARGER -#define I2C_PORT_WLC 0 -#define GPIO_WLC_IRQ_CONN 1 -#define GPIO_WLC_NRST_CONN 2 +#define I2C_PORT_WLC 0 +#define GPIO_WLC_IRQ_CONN 1 +#define GPIO_WLC_NRST_CONN 2 #define GPIO_PCHG_P0 GPIO_WLC_IRQ_CONN -#endif /* TEST_PCHG_FUZZ */ +#endif /* TEST_PCHG_FUZZ */ -#endif /* TEST_FUZZ */ -#endif /* __FUZZ_FUZZ_CONFIG_H */ +#endif /* TEST_FUZZ */ +#endif /* __FUZZ_FUZZ_CONFIG_H */ -- cgit v1.2.1 From 1d20a6d58004632376561ef9231d1f8d5ae03434 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:38:42 -0600 Subject: board/hammer/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1ed7c7fd6d8622fd365d675f15755dc605a55d03 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728316 Reviewed-by: Jeremy Bettis --- board/hammer/board.h | 97 +++++++++++++++++++++++++++------------------------- 1 file changed, 50 insertions(+), 47 deletions(-) diff --git a/board/hammer/board.h b/board/hammer/board.h index 768d15bc5b..6a5c14d9b9 100644 --- a/board/hammer/board.h +++ b/board/hammer/board.h @@ -46,27 +46,27 @@ /* Do not use a dedicated PSTATE bank */ #undef CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (44*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (44 * 1024) /* EC rollback protection block */ #define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) #define CONFIG_ROLLBACK_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF) +#define CONFIG_RW_MEM_OFF (CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - CONFIG_RW_MEM_OFF) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* The UART console is on USART1 (PA9/PA10) */ #undef CONFIG_UART_CONSOLE @@ -110,48 +110,48 @@ /* USB interface indexes (use define rather than enum to expand them) */ #ifdef SECTION_IS_RW -#define USB_IFACE_HID_KEYBOARD 0 -#define USB_IFACE_UPDATE 1 +#define USB_IFACE_HID_KEYBOARD 0 +#define USB_IFACE_UPDATE 1 #ifdef HAS_NO_TOUCHPAD -#define USB_IFACE_COUNT 2 +#define USB_IFACE_COUNT 2 #else /* !HAS_NO_TOUCHPAD */ -#define USB_IFACE_HID_TOUCHPAD 2 +#define USB_IFACE_HID_TOUCHPAD 2 /* Can be either I2C or SPI passthrough, depending on the board. */ -#define USB_IFACE_I2C_SPI 3 +#define USB_IFACE_I2C_SPI 3 #if defined(CONFIG_USB_ISOCHRONOUS) -#define USB_IFACE_ST_TOUCHPAD 4 -#define USB_IFACE_COUNT 5 -#else /* !CONFIG_USB_ISOCHRONOUS */ -#define USB_IFACE_COUNT 4 -#endif /* CONFIG_USB_ISOCHRONOUS */ +#define USB_IFACE_ST_TOUCHPAD 4 +#define USB_IFACE_COUNT 5 +#else /* !CONFIG_USB_ISOCHRONOUS */ +#define USB_IFACE_COUNT 4 +#endif /* CONFIG_USB_ISOCHRONOUS */ #endif /* !HAS_NO_TOUCHPAD */ -#else /* !SECTION_IS_RW */ -#define USB_IFACE_UPDATE 0 -#define USB_IFACE_COUNT 1 -#endif /* SECTION_IS_RW */ +#else /* !SECTION_IS_RW */ +#define USB_IFACE_UPDATE 0 +#define USB_IFACE_COUNT 1 +#endif /* SECTION_IS_RW */ /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_UPDATE 1 +#define USB_EP_CONTROL 0 +#define USB_EP_UPDATE 1 #ifdef SECTION_IS_RW -#define USB_EP_HID_KEYBOARD 2 +#define USB_EP_HID_KEYBOARD 2 #ifdef HAS_NO_TOUCHPAD -#define USB_EP_COUNT 3 +#define USB_EP_COUNT 3 #else /* !HAS_NO_TOUCHPAD */ -#define USB_EP_HID_TOUCHPAD 3 +#define USB_EP_HID_TOUCHPAD 3 /* Can be either I2C or SPI passthrough, depending on the board. */ -#define USB_EP_I2C_SPI 4 +#define USB_EP_I2C_SPI 4 #if defined(CONFIG_USB_ISOCHRONOUS) -#define USB_EP_ST_TOUCHPAD 5 -#define USB_EP_ST_TOUCHPAD_INT 6 -#define USB_EP_COUNT 7 +#define USB_EP_ST_TOUCHPAD 5 +#define USB_EP_ST_TOUCHPAD_INT 6 +#define USB_EP_COUNT 7 #else /* !CONFIG_USB_ISOCHRONOUS */ -#define USB_EP_COUNT 5 +#define USB_EP_COUNT 5 #endif /* CONFIG_USB_ISOCHRONOUS */ #endif /* !HAS_NO_TOUCHPAD */ -#else /* !SECTION_IS_RW */ -#define USB_EP_COUNT 2 -#endif /* SECTION_IS_RW */ +#else /* !SECTION_IS_RW */ +#define USB_EP_COUNT 2 +#endif /* SECTION_IS_RW */ /* Optional features */ #define CONFIG_BOARD_PRE_INIT @@ -177,13 +177,16 @@ #undef CONFIG_USB_I2C_MAX_WRITE_COUNT #ifdef VARIANT_HAMMER_TP_LARGE_PAGE /* Zed requires 516 byte per packet for touchpad update */ -#define CONFIG_USB_I2C_MAX_WRITE_COUNT (1024 - 4) /* 4 is maximum header size */ +#define CONFIG_USB_I2C_MAX_WRITE_COUNT (1024 - 4) /* 4 is maximum header size \ + */ #else -#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size */ +#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size \ + */ #endif #undef CONFIG_USB_I2C_MAX_READ_COUNT -#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size */ +#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size \ + */ #define CONFIG_I2C_XFER_LARGE_TRANSFER @@ -201,7 +204,7 @@ #define CONFIG_USB_HID_TOUCHPAD /* Virtual address for touchpad FW in USB updater. */ -#define CONFIG_TOUCHPAD_VIRTUAL_OFF 0x80000000 +#define CONFIG_TOUCHPAD_VIRTUAL_OFF 0x80000000 /* Include touchpad FW hashes in image */ #define CONFIG_TOUCHPAD_HASH_FW @@ -315,10 +318,10 @@ #endif /* Maximum current to draw. */ -#define MAX_CURRENT_MA 2000 +#define MAX_CURRENT_MA 2000 /* Maximum current/voltage to provide over OTG. */ -#define MAX_OTG_CURRENT_MA 2000 -#define MAX_OTG_VOLTAGE_MV 20000 +#define MAX_OTG_CURRENT_MA 2000 +#define MAX_OTG_VOLTAGE_MV 20000 #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 07742f3136907e289d07cbfe3d741de27371b950 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:42 -0600 Subject: board/reef_it8320/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iad42a6dceb9890e15f6bc93268f9934c7ae0eb86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728889 Reviewed-by: Jeremy Bettis --- board/reef_it8320/board.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/board/reef_it8320/board.h b/board/reef_it8320/board.h index cf29faa8f8..b3cb1691e8 100644 --- a/board/reef_it8320/board.h +++ b/board/reef_it8320/board.h @@ -19,24 +19,24 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF /* EC console commands */ #define CONFIG_CMD_BATT_MFG_ACCESS #define CONFIG_CMD_CHARGER_ADC_AMON_BMON -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define BD9995X_IOUT_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V + BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V #define CONFIG_CHARGER_PSYS_READ #define BD9995X_PSYS_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW + BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW /* Battery */ -#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" +#define CONFIG_BATTERY_DEVICE_CHEMISTRY "LION" #define CONFIG_BATTERY_CUT_OFF #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_SMART @@ -57,7 +57,7 @@ #define CONFIG_USB_CHARGER #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGER_PROFILE_OVERRIDE_COMMON -#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES +#undef CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES #define CONFIG_CHARGER_PROFILE_VOLTAGE_RANGES 3 #define CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT @@ -89,7 +89,7 @@ #define CONFIG_USB_PD_TCPMV2 #define CONFIG_USB_DRP_ACC_TRYSRC #define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */ +#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */ #define CONFIG_USB_PD_DECODE_SOP #define CONFIG_USB_PD_DEBUG_LEVEL 2 #define CONFIG_USB_PD_COMM_LOCKED @@ -112,7 +112,7 @@ /* EC */ #define CONFIG_ADC #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -162,15 +162,15 @@ #include "registers.h" /* I2C ports */ -#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C -#define I2C_PORT_BATTERY IT83XX_I2C_CH_E -#define I2C_PORT_CHARGER IT83XX_I2C_CH_E +#define I2C_PORT_USB_MUX IT83XX_I2C_CH_C +#define I2C_PORT_BATTERY IT83XX_I2C_CH_E +#define I2C_PORT_CHARGER IT83XX_I2C_CH_E /* ADC signal */ enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, /* ADC CH1 */ - ADC_TEMP_SENSOR_AMB, /* ADC CH2 */ - ADC_BOARD_ID, /* ADC CH3 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC CH1 */ + ADC_TEMP_SENSOR_AMB, /* ADC CH2 */ + ADC_BOARD_ID, /* ADC CH3 */ ADC_CH_COUNT }; @@ -200,16 +200,16 @@ enum reef_it8320_board_version { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Reset PD MCU */ void board_reset_pd_mcu(void); -- cgit v1.2.1 From 5f98708f1081b419cbf31879eefd919d99954ccb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:36 -0600 Subject: chip/mec1322/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ide148af5545c19b7f2c6358f4ce7a28bd26a018a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729305 Reviewed-by: Jeremy Bettis --- chip/mec1322/adc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c index 9c83173777..d925178fe7 100644 --- a/chip/mec1322/adc.c +++ b/chip/mec1322/adc.c @@ -48,7 +48,8 @@ int adc_read_channel(enum adc_channel ch) if (start_single_and_wait(ADC_SINGLE_READ_TIME)) value = MEC1322_ADC_READ(adc->channel) * adc->factor_mul / - adc->factor_div + adc->shift; + adc->factor_div + + adc->shift; else value = ADC_READ_ERROR; -- cgit v1.2.1 From 7d0e0c7cbeca71fd8d234967413474a0d9156529 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:57 -0600 Subject: board/phaser/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8f5629bd2ef82a89499974f64b1045314b0c389 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728822 Reviewed-by: Jeremy Bettis --- board/phaser/led.c | 49 ++++++++++++++++++++++++++----------------------- 1 file changed, 26 insertions(+), 23 deletions(-) diff --git a/board/phaser/led.c b/board/phaser/led.c index cce1c3289e..31cbba2a16 100644 --- a/board/phaser/led.c +++ b/board/phaser/led.c @@ -19,32 +19,35 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From ba397f82c11279d3f51a6d1c4bfb9870b458b55f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:15 -0600 Subject: common/btle_ll.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I467401d6eb28836aefe3e2e31cfa899d017af2e9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729594 Reviewed-by: Jeremy Bettis --- common/btle_ll.c | 149 +++++++++++++++++++++++++++---------------------------- 1 file changed, 74 insertions(+), 75 deletions(-) diff --git a/common/btle_ll.c b/common/btle_ll.c index d57eb3bfd3..0ae0531c2d 100644 --- a/common/btle_ll.c +++ b/common/btle_ll.c @@ -16,8 +16,8 @@ #ifdef CONFIG_BLUETOOTH_LL_DEBUG #define CPUTS(outstr) cputs(CC_BLUETOOTH_LL, outstr) -#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_BLUETOOTH_LL, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_BLUETOOTH_LL, format, ##args) #else /* CONFIG_BLUETOOTH_LL_DEBUG */ @@ -57,7 +57,7 @@ uint8_t is_first_data_packet; static uint64_t ll_random_address = 0xC5BADBADBAD1; /* Uninitialized */ static uint64_t ll_public_address = 0xC5BADBADBADF; /* Uninitialized */ -static uint8_t ll_channel_map[5] = {0xff, 0xff, 0xff, 0xff, 0x1f}; +static uint8_t ll_channel_map[5] = { 0xff, 0xff, 0xff, 0xff, 0x1f }; static uint8_t ll_filter_duplicates; @@ -161,8 +161,8 @@ static uint8_t ll_state_change_request(enum ll_state_t next_state) { /* Initialize the radio if it hasn't been initialized */ if (ll_state == UNINITIALIZED) { - if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT) - != EC_SUCCESS) + if (ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT) != + EC_SUCCESS) return HCI_ERR_Hardware_Failure; ll_state = STANDBY; } @@ -236,50 +236,50 @@ uint8_t initialize_connection(void) num_consecutive_failures = 0; /* Copy data into the appropriate portions of memory */ - memcpy((uint8_t *)&(conn_params.init_a), - payload_start, CONNECT_REQ_INITA_LEN); + memcpy((uint8_t *)&(conn_params.init_a), payload_start, + CONNECT_REQ_INITA_LEN); cur_offset += CONNECT_REQ_INITA_LEN; - memcpy((uint8_t *)&(conn_params.adv_a), - payload_start+cur_offset, CONNECT_REQ_ADVA_LEN); + memcpy((uint8_t *)&(conn_params.adv_a), payload_start + cur_offset, + CONNECT_REQ_ADVA_LEN); cur_offset += CONNECT_REQ_ADVA_LEN; - memcpy(&(conn_params.access_addr), - payload_start+cur_offset, CONNECT_REQ_ACCESS_ADDR_LEN); + memcpy(&(conn_params.access_addr), payload_start + cur_offset, + CONNECT_REQ_ACCESS_ADDR_LEN); cur_offset += CONNECT_REQ_ACCESS_ADDR_LEN; conn_params.crc_init_val = 0; - memcpy(&(conn_params.crc_init_val), - payload_start+cur_offset, CONNECT_REQ_CRC_INIT_VAL_LEN); + memcpy(&(conn_params.crc_init_val), payload_start + cur_offset, + CONNECT_REQ_CRC_INIT_VAL_LEN); cur_offset += CONNECT_REQ_CRC_INIT_VAL_LEN; - memcpy(&(conn_params.win_size), - payload_start+cur_offset, CONNECT_REQ_WIN_SIZE_LEN); + memcpy(&(conn_params.win_size), payload_start + cur_offset, + CONNECT_REQ_WIN_SIZE_LEN); cur_offset += CONNECT_REQ_WIN_SIZE_LEN; - memcpy(&(conn_params.win_offset), - payload_start+cur_offset, CONNECT_REQ_WIN_OFFSET_LEN); + memcpy(&(conn_params.win_offset), payload_start + cur_offset, + CONNECT_REQ_WIN_OFFSET_LEN); cur_offset += CONNECT_REQ_WIN_OFFSET_LEN; - memcpy(&(conn_params.interval), - payload_start+cur_offset, CONNECT_REQ_INTERVAL_LEN); + memcpy(&(conn_params.interval), payload_start + cur_offset, + CONNECT_REQ_INTERVAL_LEN); cur_offset += CONNECT_REQ_INTERVAL_LEN; - memcpy(&(conn_params.latency), - payload_start+cur_offset, CONNECT_REQ_LATENCY_LEN); + memcpy(&(conn_params.latency), payload_start + cur_offset, + CONNECT_REQ_LATENCY_LEN); cur_offset += CONNECT_REQ_LATENCY_LEN; - memcpy(&(conn_params.timeout), - payload_start+cur_offset, CONNECT_REQ_TIMEOUT_LEN); + memcpy(&(conn_params.timeout), payload_start + cur_offset, + CONNECT_REQ_TIMEOUT_LEN); cur_offset += CONNECT_REQ_TIMEOUT_LEN; conn_params.channel_map = 0; - memcpy(&(conn_params.channel_map), - payload_start+cur_offset, CONNECT_REQ_CHANNEL_MAP_LEN); + memcpy(&(conn_params.channel_map), payload_start + cur_offset, + CONNECT_REQ_CHANNEL_MAP_LEN); cur_offset += CONNECT_REQ_CHANNEL_MAP_LEN; - memcpy(&final_octet, payload_start+cur_offset, - CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN); + memcpy(&final_octet, payload_start + cur_offset, + CONNECT_REQ_HOP_INCREMENT_AND_SCA_LEN); /* last 5 bits of final_octet: */ conn_params.hop_increment = final_octet & 0x1f; @@ -288,9 +288,9 @@ uint8_t initialize_connection(void) /* Set up channel mapping table */ for (i = 0; i < 5; ++i) - remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map))+i); + remap_arr[i] = *(((uint8_t *)&(conn_params.channel_map)) + i); fill_remapping_table(&remap_table, remap_arr, - conn_params.hop_increment); + conn_params.hop_increment); /* Calculate transmission window parameters */ conn_params.transmitWindowSize = conn_params.win_size * 1250; @@ -332,7 +332,7 @@ uint8_t ll_read_allow_list_size(uint8_t *return_params) uint8_t ll_add_device_to_allow_list(uint8_t *params) { if (ble_radio_add_device_to_allow_list(¶ms[1], params[0]) == - EC_SUCCESS) + EC_SUCCESS) return HCI_SUCCESS; else return HCI_ERR_Host_Rejected_Due_To_Limited_Resources; @@ -341,7 +341,7 @@ uint8_t ll_add_device_to_allow_list(uint8_t *params) uint8_t ll_remove_device_from_allow_list(uint8_t *params) { if (ble_radio_remove_device_from_allow_list(¶ms[1], params[0]) == - EC_SUCCESS) + EC_SUCCESS) return HCI_SUCCESS; else return HCI_ERR_Hardware_Failure; @@ -449,27 +449,28 @@ uint8_t ll_set_advertising_params(uint8_t *params) case BLE_ADV_HEADER_PDU_TYPE_ADV_NONCONN_IND: case BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND: if (ll_adv_params.advIntervalMin < - (100000 / LL_ADV_INTERVAL_UNIT_US)) /* 100ms */ + (100000 / LL_ADV_INTERVAL_UNIT_US)) /* 100ms */ return HCI_ERR_Invalid_HCI_Command_Parameters; /* Fall through */ case BLE_ADV_HEADER_PDU_TYPE_ADV_IND: if (ll_adv_params.advIntervalMin > ll_adv_params.advIntervalMax) return HCI_ERR_Invalid_HCI_Command_Parameters; if (ll_adv_params.advIntervalMin < - (20000 / LL_ADV_INTERVAL_UNIT_US) || /* 20ms */ + (20000 / LL_ADV_INTERVAL_UNIT_US) || /* 20ms */ ll_adv_params.advIntervalMax > - (10240000 / LL_ADV_INTERVAL_UNIT_US)) /* 10.24s */ + (10240000 / LL_ADV_INTERVAL_UNIT_US)) /* 10.24s */ return HCI_ERR_Invalid_HCI_Command_Parameters; ll_adv_interval_us = (((ll_adv_params.advIntervalMin + - ll_adv_params.advIntervalMax) / 2) * - LL_ADV_INTERVAL_UNIT_US); + ll_adv_params.advIntervalMax) / + 2) * + LL_ADV_INTERVAL_UNIT_US); /* Don't time out */ ll_adv_timeout_us = -1; - break; + break; case BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND: ll_adv_interval_us = LL_ADV_DIRECT_INTERVAL_US; ll_adv_timeout_us = LL_ADV_DIRECT_TIMEOUT_US; - break; + break; default: return HCI_ERR_Invalid_HCI_Command_Parameters; } @@ -563,25 +564,25 @@ int ble_ll_adv(int chan) case BLE_ADV_HEADER_PDU_TYPE_SCAN_REQ: /* Scan requests are only allowed for ADV_IND and SCAN_IND */ if ((ll_adv_pdu.header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_IND && + BLE_ADV_HEADER_PDU_TYPE_ADV_IND && ll_adv_pdu.header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) || - /* The advertising address needs to match */ + BLE_ADV_HEADER_PDU_TYPE_ADV_SCAN_IND) || + /* The advertising address needs to match */ (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS], &ll_adv_pdu.payload[0], BLUETOOTH_ADDR_OCTETS))) { /* Don't send the scan response */ radio_disable(); return rv; } - break; + break; case BLE_ADV_HEADER_PDU_TYPE_CONNECT_REQ: /* Don't send a scan response */ radio_disable(); /* Connecting is only allowed for ADV_IND and ADV_DIRECT_IND */ if (ll_adv_pdu.header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_IND && + BLE_ADV_HEADER_PDU_TYPE_ADV_IND && ll_adv_pdu.header.adv.type != - BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND) + BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND) return rv; /* The advertising address needs to match */ if (memcmp(&ll_rcv_packet.payload[BLUETOOTH_ADDR_OCTETS], @@ -589,9 +590,9 @@ int ble_ll_adv(int chan) return rv; /* The InitAddr address needs to match for ADV_DIRECT_IND */ if (ll_adv_pdu.header.adv.type == - BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && - memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS], - &ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS)) + BLE_ADV_HEADER_PDU_TYPE_ADV_DIRECT_IND && + memcmp(&ll_adv_pdu.payload[BLUETOOTH_ADDR_OCTETS], + &ll_rcv_packet.payload[0], BLUETOOTH_ADDR_OCTETS)) return rv; /* Mark time that connect was received */ @@ -604,11 +605,11 @@ int ble_ll_adv(int chan) ll_state = CONNECTION; return rv; - break; + break; default: /* Unhandled response packet */ radio_disable(); return rv; - break; + break; } CPRINTF("ADV %u Response %u %u\n", tx_end, rsp_end, tx_rsp_end); @@ -632,7 +633,6 @@ int ble_ll_adv_event(void) return rv; } - void print_connection_state(void) { CPRINTF("vvvvvvvvvvvvvvvvvvvCONNECTION STATEvvvvvvvvvvvvvvvvvvv\n"); @@ -663,12 +663,12 @@ int connected_communicate(void) if (num_consecutive_failures > 0) { ble_radio_init(conn_params.access_addr, - conn_params.crc_init_val); + conn_params.crc_init_val); NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel)); NRF51_RADIO_DATAWHITEIV = comm_channel; - listen_time = last_receive_time + conn_params.connInterval - - get_time().val + conn_params.transmitWindowSize; + listen_time = last_receive_time + conn_params.connInterval - + get_time().val + conn_params.transmitWindowSize; /* * This listens for 1.25 times the expected amount @@ -680,12 +680,12 @@ int connected_communicate(void) * slightly longer than expected in the case that * there was a timing disagreement. */ - rv = ble_rx(&ll_rcv_packet, - listen_time + (listen_time >> 2), 0); + rv = ble_rx(&ll_rcv_packet, listen_time + (listen_time >> 2), + 0); } else { if (!is_first_data_packet) { - sleep_time = receive_time + - conn_params.connInterval - get_time().val; + sleep_time = receive_time + conn_params.connInterval - + get_time().val; /* * The time slept is 31/32 (96.875%) of the calculated * required sleep time because the code to receive @@ -695,8 +695,8 @@ int connected_communicate(void) } else { last_receive_time = time_of_connect_req; sleep_time = TRANSMIT_WINDOW_OFFSET_CONSTANT + - conn_params.transmitWindowOffset + - time_of_connect_req - get_time().val; + conn_params.transmitWindowOffset + + time_of_connect_req - get_time().val; if (sleep_time >= 0) { /* * Radio is on for longer than needed for first @@ -709,7 +709,7 @@ int connected_communicate(void) } ble_radio_init(conn_params.access_addr, - conn_params.crc_init_val); + conn_params.crc_init_val); NRF51_RADIO_FREQUENCY = NRF51_RADIO_FREQUENCY_VAL(chan2freq(comm_channel)); NRF51_RADIO_DATAWHITEIV = comm_channel; @@ -722,14 +722,13 @@ int connected_communicate(void) * how early the window opens in microseconds. */ if (!is_first_data_packet) - offset = last_receive_time + conn_params.connInterval - - get_time().val; + offset = last_receive_time + conn_params.connInterval - + get_time().val; else offset = 0; rv = ble_rx(&ll_rcv_packet, - offset + conn_params.transmitWindowSize, - 0); + offset + conn_params.transmitWindowSize, 0); } /* @@ -768,7 +767,7 @@ void bluetooth_ll_task(void) if (deadline.val == 0) { CPRINTS("ADV @%pP", &ll_adv_pdu); deadline.val = get_time().val + - (uint32_t)ll_adv_timeout_us; + (uint32_t)ll_adv_timeout_us; ll_adv_events = 0; } @@ -786,7 +785,7 @@ void bluetooth_ll_task(void) ll_state = STANDBY; break; } - break; + break; case STANDBY: deadline.val = 0; CPRINTS("Standby %d events", ll_adv_events); @@ -795,20 +794,20 @@ void bluetooth_ll_task(void) task_wait_event(-1); connection_initialized = 0; errors_recovered = 0; - break; + break; case TEST_RX: if (ble_test_rx() == HCI_SUCCESS) ll_test_packets++; /* Packets come every 625us, sleep to save power */ usleep(300); - break; + break; case TEST_TX: start = get_time().le.lo; ble_test_tx(); ll_test_packets++; end = get_time().le.lo; - usleep(625 - 82 - (end-start)); /* 625us */ - break; + usleep(625 - 82 - (end - start)); /* 625us */ + break; case UNINITIALIZED: ble_radio_init(BLE_ADV_ACCESS_ADDRESS, BLE_ADV_CRCINIT); ll_adv_events = 0; @@ -816,7 +815,7 @@ void bluetooth_ll_task(void) connection_initialized = 0; packet_tb_sent = &tx_packet_1; set_empty_data_packet(&tx_packet_1); - break; + break; case CONNECTION: if (!connection_initialized) { if (initialize_connection() != HCI_SUCCESS) { @@ -835,8 +834,7 @@ void bluetooth_ll_task(void) } else { num_consecutive_failures++; if ((get_time().val - last_rx_time) > - conn_params.connSupervisionTimeout) { - + conn_params.connSupervisionTimeout) { ll_state = STANDBY; CPRINTF("EXITING CONNECTION STATE " "DUE TO TIMEOUT.\n"); @@ -847,10 +845,11 @@ void bluetooth_ll_task(void) if (ll_state == STANDBY) { CPRINTF("Exiting connection state/Entering " "Standby state after %d connections " - "events\n", ll_conn_events); + "events\n", + ll_conn_events); print_connection_state(); } - break; + break; default: CPRINTS("Unhandled State ll_state = %d", ll_state); ll_state = UNINITIALIZED; -- cgit v1.2.1 From bae234d5e9553e6ec5b5d000af4044dbfe459ae7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:50 -0600 Subject: chip/stm32/usb_hid_touchpad.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibac2a930d67dba71ec545ac8611f31d33dfd8953 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729577 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_hid_touchpad.c | 533 ++++++++++++++++++++++++++++++------------ 1 file changed, 379 insertions(+), 154 deletions(-) diff --git a/chip/stm32/usb_hid_touchpad.c b/chip/stm32/usb_hid_touchpad.c index 0ead660432..d15a8fc86a 100644 --- a/chip/stm32/usb_hid_touchpad.c +++ b/chip/stm32/usb_hid_touchpad.c @@ -24,16 +24,16 @@ #include "usb_hid_touchpad.h" /* Console output macro */ -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) static const int touchpad_debug; -static struct queue const report_queue = QUEUE_NULL(8, - struct usb_hid_touchpad_report); +static struct queue const report_queue = + QUEUE_NULL(8, struct usb_hid_touchpad_report); static struct mutex report_queue_mutex; -#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) +#define HID_TOUCHPAD_REPORT_SIZE sizeof(struct usb_hid_touchpad_report) /* * Touchpad EP interval: Make sure this value is smaller than the typical @@ -65,58 +65,63 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { .bInterval = HID_TOUCHPAD_EP_INTERVAL_MS /* polling interval */ }; -#define FINGER_USAGE \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - 0x09, 0x22, /* Usage (Finger) */ \ - 0xA1, 0x02, /* Collection (Logical) */ \ - 0x09, 0x47, /* Usage (Confidence) */ \ - 0x09, 0x42, /* Usage (Tip Switch) */ \ - 0x09, 0x32, /* Usage (In Range) */ \ - 0x15, 0x00, /* Logical Minimum (0) */ \ - 0x25, 0x01, /* Logical Maximum (1) */ \ - 0x75, 0x01, /* Report Size (1) */ \ - 0x95, 0x03, /* Report Count (3) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ - 0x75, 0x04, /* Report Size (4) */ \ - 0x95, 0x01, /* Report Count (1) */ \ - 0x25, 0x0F, /* Logical Maximum (15) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x0D, /* Usage Page (Digitizer) */ \ - /* Logical Maximum of Pressure */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), \ - 0x75, 0x09, /* Report Size (9) */ \ - 0x09, 0x30, /* Usage (Tip pressure) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x09, 0x48, /* Usage (WIDTH) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x09, 0x49, /* Usage (HEIGHT) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ - 0x75, 0x0C, /* Report Size (12) */ \ - 0x55, 0x0E, /* Unit Exponent (-2) */ \ - 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ - 0x09, 0x30, /* Usage (X) */ \ - 0x35, 0x00, /* Physical Minimum (0) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), \ - /* Logical Maximum */ \ - 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ - (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), \ - /* Physical Maximum (tenth of mm) */ \ - 0x09, 0x31, /* Usage (Y) */ \ - 0x81, 0x02, /* Input (Data,Var,Abs) */ \ - 0xC0 /* End Collection */ +#define FINGER_USAGE \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ \ + 0x09, 0x22, /* Usage (Finger) */ \ + 0xA1, 0x02, /* Collection (Logical) */ \ + 0x09, 0x47, /* Usage (Confidence) */ \ + 0x09, 0x42, /* Usage (Tip Switch) */ \ + 0x09, 0x32, /* Usage (In Range) */ \ + 0x15, 0x00, /* Logical Minimum (0) */ \ + 0x25, 0x01, /* Logical Maximum (1) */ \ + 0x75, 0x01, /* Report Size (1) */ \ + 0x95, 0x03, /* Report Count (3) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x51, /* Usage (0x51) Contact identifier */ \ + 0x75, 0x04, /* Report Size (4) */ \ + 0x95, 0x01, /* Report Count (1) */ \ + 0x25, 0x0F, /* Logical Maximum (15) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x0D, /* Usage Page (Digitizer) */ /* Logical \ + Maximum of \ + Pressure */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE & 0xFF), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_PRESSURE >> 8), 0x75, \ + 0x09, /* Report Size (9) */ \ + 0x09, 0x30, /* Usage (Tip pressure) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x26, 0xFF, 0x0F, /* Logical Maximum (4095) */ \ + 0x75, 0x0C, /* Report Size (12) */ \ + 0x09, 0x48, /* Usage (WIDTH) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x09, 0x49, /* Usage (HEIGHT) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x05, 0x01, /* Usage Page (Generic Desktop Ctrls) */ \ + 0x75, 0x0C, /* Report Size (12) */ \ + 0x55, 0x0E, /* Unit Exponent (-2) */ \ + 0x65, 0x11, /* Unit (System: SI Linear, Length: cm) */ \ + 0x09, 0x30, /* Usage (X) */ \ + 0x35, 0x00, /* Physical Minimum (0) */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_X >> 8), /* Logical \ + Maximum */ \ + 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_X >> 8), /* Physical \ + Maximum \ + (tenth of \ + mm) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0x26, (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_LOGICAL_MAX_Y >> 8), /* Logical \ + Maximum */ \ + 0x46, (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y & 0xff), \ + (CONFIG_USB_HID_TOUCHPAD_PHYSICAL_MAX_Y >> 8), /* Physical \ + Maximum \ + (tenth of \ + mm) */ \ + 0x09, 0x31, /* Usage (Y) */ \ + 0x81, 0x02, /* Input (Data,Var,Abs) */ \ + 0xC0 /* End Collection */ /* * HID: Report Descriptor @@ -125,10 +130,10 @@ const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID_TOUCHPAD, 81) = { */ static const uint8_t report_desc[] = { /* Touchpad Collection */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x05, /* Usage (Touch Pad) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x05, /* Usage (Touch Pad) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x85, REPORT_ID_TOUCHPAD, /* Report ID (1, Touch) */ /* Finger 0 */ FINGER_USAGE, /* Finger 1 */ @@ -140,52 +145,52 @@ static const uint8_t report_desc[] = { /* Finger 4 */ FINGER_USAGE, /* Contact count */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x09, 0x54, /* Usage (Contact count) */ - 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ - 0x75, 0x07, /* Report Size (7) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x09, 0x54, /* Usage (Contact count) */ + 0x25, MAX_FINGERS, /* Logical Maximum (MAX_FINGERS) */ + 0x75, 0x07, /* Report Size (7) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Button */ - 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ - 0x05, 0x09, /* Usage (Button) */ - 0x19, 0x01, /* Usage Minimum (0x01) */ - 0x29, 0x01, /* Usage Maximum (0x01) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x01, /* Report Count (1) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ + 0x05, 0x01, /* Usage Page(Generic Desktop Ctrls) */ + 0x05, 0x09, /* Usage (Button) */ + 0x19, 0x01, /* Usage Minimum (0x01) */ + 0x29, 0x01, /* Usage Maximum (0x01) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x01, /* Report Count (1) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ /* Timestamp */ - 0x05, 0x0D, /* Usage Page (Digitizer) */ - 0x55, 0x0C, /* Unit Exponent (-4) */ - 0x66, 0x01, 0x10, /* Unit (Seconds) */ - 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ - 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ - 0x75, 0x10, /* Report Size (16) */ - 0x95, 0x01, /* Report Count (1) */ - 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ - 0x81, 0x02, /* Input (Data,Var,Abs) */ - - 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ - 0x09, 0x55, /* Usage (Contact Count Maximum) */ - 0x09, 0x59, /* Usage (Pad Type) */ - 0x25, 0x0F, /* Logical Maximum (15) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x02, /* Report Count (2) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + 0x05, 0x0D, /* Usage Page (Digitizer) */ + 0x55, 0x0C, /* Unit Exponent (-4) */ + 0x66, 0x01, 0x10, /* Unit (Seconds) */ + 0x47, 0xFF, 0xFF, 0x00, 0x00, /* Physical Maximum (65535) */ + 0x27, 0xFF, 0xFF, 0x00, 0x00, /* Logical Maximum (65535) */ + 0x75, 0x10, /* Report Size (16) */ + 0x95, 0x01, /* Report Count (1) */ + 0x09, 0x56, /* Usage (0x56, Relative Scan Time) */ + 0x81, 0x02, /* Input (Data,Var,Abs) */ + + 0x85, REPORT_ID_DEVICE_CAPS, /* Report ID (Device Capabilities) */ + 0x09, 0x55, /* Usage (Contact Count Maximum) */ + 0x09, 0x59, /* Usage (Pad Type) */ + 0x25, 0x0F, /* Logical Maximum (15) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x02, /* Report Count (2) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ /* Page 0xFF, usage 0xC5 is device certificate. */ - 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ - 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ - 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ - 0x75, 0x08, /* Report Size (8) */ - 0x96, 0x00, 0x01, /* Report Count (256) */ - 0xB1, 0x02, /* Feature (Data,Var,Abs) */ - - 0xC0, /* End Collection */ + 0x06, 0x00, 0xFF, /* Usage Page (Vendor Defined) */ + 0x85, REPORT_ID_DEVICE_CERT, /* Report ID (Device Certification) */ + 0x09, 0xC5, /* Usage (Vendor Usage 0xC5) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x26, 0xFF, 0x00, /* Logical Maximum (255) */ + 0x75, 0x08, /* Report Size (8) */ + 0x96, 0x00, 0x01, /* Report Count (256) */ + 0xB1, 0x02, /* Feature (Data,Var,Abs) */ + + 0xC0, /* End Collection */ }; /* A 256-byte default blob for the 'device certification status' feature report. @@ -195,59 +200,281 @@ static const uint8_t report_desc[] = { static const uint8_t device_cert_response[] = { REPORT_ID_DEVICE_CERT, - 0xFC, 0x28, 0xFE, 0x84, 0x40, 0xCB, 0x9A, 0x87, - 0x0D, 0xBE, 0x57, 0x3C, 0xB6, 0x70, 0x09, 0x88, - 0x07, 0x97, 0x2D, 0x2B, 0xE3, 0x38, 0x34, 0xB6, - 0x6C, 0xED, 0xB0, 0xF7, 0xE5, 0x9C, 0xF6, 0xC2, - 0x2E, 0x84, 0x1B, 0xE8, 0xB4, 0x51, 0x78, 0x43, - 0x1F, 0x28, 0x4B, 0x7C, 0x2D, 0x53, 0xAF, 0xFC, - 0x47, 0x70, 0x1B, 0x59, 0x6F, 0x74, 0x43, 0xC4, - 0xF3, 0x47, 0x18, 0x53, 0x1A, 0xA2, 0xA1, 0x71, - 0xC7, 0x95, 0x0E, 0x31, 0x55, 0x21, 0xD3, 0xB5, - 0x1E, 0xE9, 0x0C, 0xBA, 0xEC, 0xB8, 0x89, 0x19, - 0x3E, 0xB3, 0xAF, 0x75, 0x81, 0x9D, 0x53, 0xB9, - 0x41, 0x57, 0xF4, 0x6D, 0x39, 0x25, 0x29, 0x7C, - 0x87, 0xD9, 0xB4, 0x98, 0x45, 0x7D, 0xA7, 0x26, - 0x9C, 0x65, 0x3B, 0x85, 0x68, 0x89, 0xD7, 0x3B, - 0xBD, 0xFF, 0x14, 0x67, 0xF2, 0x2B, 0xF0, 0x2A, - 0x41, 0x54, 0xF0, 0xFD, 0x2C, 0x66, 0x7C, 0xF8, - 0xC0, 0x8F, 0x33, 0x13, 0x03, 0xF1, 0xD3, 0xC1, - 0x0B, 0x89, 0xD9, 0x1B, 0x62, 0xCD, 0x51, 0xB7, - 0x80, 0xB8, 0xAF, 0x3A, 0x10, 0xC1, 0x8A, 0x5B, - 0xE8, 0x8A, 0x56, 0xF0, 0x8C, 0xAA, 0xFA, 0x35, - 0xE9, 0x42, 0xC4, 0xD8, 0x55, 0xC3, 0x38, 0xCC, - 0x2B, 0x53, 0x5C, 0x69, 0x52, 0xD5, 0xC8, 0x73, - 0x02, 0x38, 0x7C, 0x73, 0xB6, 0x41, 0xE7, 0xFF, - 0x05, 0xD8, 0x2B, 0x79, 0x9A, 0xE2, 0x34, 0x60, - 0x8F, 0xA3, 0x32, 0x1F, 0x09, 0x78, 0x62, 0xBC, - 0x80, 0xE3, 0x0F, 0xBD, 0x65, 0x20, 0x08, 0x13, - 0xC1, 0xE2, 0xEE, 0x53, 0x2D, 0x86, 0x7E, 0xA7, - 0x5A, 0xC5, 0xD3, 0x7D, 0x98, 0xBE, 0x31, 0x48, - 0x1F, 0xFB, 0xDA, 0xAF, 0xA2, 0xA8, 0x6A, 0x89, - 0xD6, 0xBF, 0xF2, 0xD3, 0x32, 0x2A, 0x9A, 0xE4, - 0xCF, 0x17, 0xB7, 0xB8, 0xF4, 0xE1, 0x33, 0x08, - 0x24, 0x8B, 0xC4, 0x43, 0xA5, 0xE5, 0x24, 0xC2, + 0xFC, + 0x28, + 0xFE, + 0x84, + 0x40, + 0xCB, + 0x9A, + 0x87, + 0x0D, + 0xBE, + 0x57, + 0x3C, + 0xB6, + 0x70, + 0x09, + 0x88, + 0x07, + 0x97, + 0x2D, + 0x2B, + 0xE3, + 0x38, + 0x34, + 0xB6, + 0x6C, + 0xED, + 0xB0, + 0xF7, + 0xE5, + 0x9C, + 0xF6, + 0xC2, + 0x2E, + 0x84, + 0x1B, + 0xE8, + 0xB4, + 0x51, + 0x78, + 0x43, + 0x1F, + 0x28, + 0x4B, + 0x7C, + 0x2D, + 0x53, + 0xAF, + 0xFC, + 0x47, + 0x70, + 0x1B, + 0x59, + 0x6F, + 0x74, + 0x43, + 0xC4, + 0xF3, + 0x47, + 0x18, + 0x53, + 0x1A, + 0xA2, + 0xA1, + 0x71, + 0xC7, + 0x95, + 0x0E, + 0x31, + 0x55, + 0x21, + 0xD3, + 0xB5, + 0x1E, + 0xE9, + 0x0C, + 0xBA, + 0xEC, + 0xB8, + 0x89, + 0x19, + 0x3E, + 0xB3, + 0xAF, + 0x75, + 0x81, + 0x9D, + 0x53, + 0xB9, + 0x41, + 0x57, + 0xF4, + 0x6D, + 0x39, + 0x25, + 0x29, + 0x7C, + 0x87, + 0xD9, + 0xB4, + 0x98, + 0x45, + 0x7D, + 0xA7, + 0x26, + 0x9C, + 0x65, + 0x3B, + 0x85, + 0x68, + 0x89, + 0xD7, + 0x3B, + 0xBD, + 0xFF, + 0x14, + 0x67, + 0xF2, + 0x2B, + 0xF0, + 0x2A, + 0x41, + 0x54, + 0xF0, + 0xFD, + 0x2C, + 0x66, + 0x7C, + 0xF8, + 0xC0, + 0x8F, + 0x33, + 0x13, + 0x03, + 0xF1, + 0xD3, + 0xC1, + 0x0B, + 0x89, + 0xD9, + 0x1B, + 0x62, + 0xCD, + 0x51, + 0xB7, + 0x80, + 0xB8, + 0xAF, + 0x3A, + 0x10, + 0xC1, + 0x8A, + 0x5B, + 0xE8, + 0x8A, + 0x56, + 0xF0, + 0x8C, + 0xAA, + 0xFA, + 0x35, + 0xE9, + 0x42, + 0xC4, + 0xD8, + 0x55, + 0xC3, + 0x38, + 0xCC, + 0x2B, + 0x53, + 0x5C, + 0x69, + 0x52, + 0xD5, + 0xC8, + 0x73, + 0x02, + 0x38, + 0x7C, + 0x73, + 0xB6, + 0x41, + 0xE7, + 0xFF, + 0x05, + 0xD8, + 0x2B, + 0x79, + 0x9A, + 0xE2, + 0x34, + 0x60, + 0x8F, + 0xA3, + 0x32, + 0x1F, + 0x09, + 0x78, + 0x62, + 0xBC, + 0x80, + 0xE3, + 0x0F, + 0xBD, + 0x65, + 0x20, + 0x08, + 0x13, + 0xC1, + 0xE2, + 0xEE, + 0x53, + 0x2D, + 0x86, + 0x7E, + 0xA7, + 0x5A, + 0xC5, + 0xD3, + 0x7D, + 0x98, + 0xBE, + 0x31, + 0x48, + 0x1F, + 0xFB, + 0xDA, + 0xAF, + 0xA2, + 0xA8, + 0x6A, + 0x89, + 0xD6, + 0xBF, + 0xF2, + 0xD3, + 0x32, + 0x2A, + 0x9A, + 0xE4, + 0xCF, + 0x17, + 0xB7, + 0xB8, + 0xF4, + 0xE1, + 0x33, + 0x08, + 0x24, + 0x8B, + 0xC4, + 0x43, + 0xA5, + 0xE5, + 0x24, + 0xC2, }; /* Device capabilities feature report. */ static const uint8_t device_caps_response[] = { REPORT_ID_DEVICE_CAPS, - MAX_FINGERS, /* Contact Count Maximum */ - 0x00, /* Pad Type: Depressible click-pad */ + MAX_FINGERS, /* Contact Count Maximum */ + 0x00, /* Pad Type: Depressible click-pad */ }; -const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, - hid, hid_desc_tp) = { +const struct usb_hid_descriptor USB_CUSTOM_DESC_VAR(USB_IFACE_HID_TOUCHPAD, hid, + hid_desc_tp) = { .bLength = 9, .bDescriptorType = USB_HID_DT_HID, .bcdHID = 0x0100, .bCountryCode = 0x00, /* Hardware target country */ .bNumDescriptors = 1, - .desc = {{ - .bDescriptorType = USB_HID_DT_REPORT, - .wDescriptorLength = sizeof(report_desc) - }} + .desc = { { .bDescriptorType = USB_HID_DT_REPORT, + .wDescriptorLength = sizeof(report_desc) } } }; static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; @@ -258,8 +485,8 @@ static usb_uint hid_ep_buf[DIV_ROUND_UP(HID_TOUCHPAD_REPORT_SIZE, 2)] __usb_ram; */ static void write_touchpad_report(struct usb_hid_touchpad_report *report) { - memcpy_to_usbram((void *) usb_sram_addr(hid_ep_buf), - report, sizeof(*report)); + memcpy_to_usbram((void *)usb_sram_addr(hid_ep_buf), report, + sizeof(*report)); /* enable TX */ STM32_TOGGLE_EP(USB_EP_HID_TOUCHPAD, EP_TX_MASK, EP_TX_VALID, 0); @@ -289,8 +516,7 @@ static void hid_touchpad_process_queue(void) now = __hw_clock_source_read() / USB_HID_TOUCHPAD_TIMESTAMP_UNIT; if (usb_is_suspended() || - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) - == EP_TX_VALID) { + (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) == EP_TX_VALID) { usb_wake(); /* Let's trim old events from the queue, if any. */ @@ -307,8 +533,8 @@ static void hid_touchpad_process_queue(void) queue_peek_units(&report_queue, &report, 0, 1); - delta = (int)((uint16_t)(now - report.timestamp)) - * USB_HID_TOUCHPAD_TIMESTAMP_UNIT; + delta = (int)((uint16_t)(now - report.timestamp)) * + USB_HID_TOUCHPAD_TIMESTAMP_UNIT; if (touchpad_debug) CPRINTS("evt t=%d d=%d", report.timestamp, delta); @@ -345,8 +571,8 @@ void set_touchpad_report(struct usb_hid_touchpad_report *report) /* USB/EP ready and nothing in queue, just write the report. */ if (!usb_is_suspended() && - (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID - && queue_count(&report_queue) == 0) { + (STM32_USB_EP(USB_EP_HID_TOUCHPAD) & EP_TX_MASK) != EP_TX_VALID && + queue_count(&report_queue) == 0) { write_touchpad_report(report); mutex_unlock(&report_queue_mutex); return; @@ -385,7 +611,7 @@ static void hid_touchpad_event(enum usb_ep_event evt) hid_reset(USB_EP_HID_TOUCHPAD, hid_ep_buf, HID_TOUCHPAD_REPORT_SIZE, NULL, 0); else if (evt == USB_EVENT_DEVICE_RESUME && - queue_count(&report_queue) > 0) + queue_count(&report_queue) > 0) hook_call_deferred(&hid_touchpad_process_queue_data, 0); } @@ -393,8 +619,7 @@ USB_DECLARE_EP(USB_EP_HID_TOUCHPAD, hid_touchpad_tx, hid_touchpad_tx, hid_touchpad_event); static int get_report(uint8_t report_id, uint8_t report_type, - const uint8_t **buffer_ptr, - int *buffer_size) + const uint8_t **buffer_ptr, int *buffer_size) { switch (report_id) { case REPORT_ID_DEVICE_CAPS: -- cgit v1.2.1 From 15822379106462ec410d890fbe0463c0c51a0ab6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:45 -0600 Subject: zephyr/shim/src/console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4068022d9a470e5d96328ec9eb84bc59347b3e4f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730907 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/console.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c index f47136771d..a37b96ab58 100644 --- a/zephyr/shim/src/console.c +++ b/zephyr/shim/src/console.c @@ -153,8 +153,8 @@ static void shell_init_from_work(struct k_work *work) #endif /* Initialize the shell and re-enable both RX and TX */ - shell_init(shell_zephyr, uart_shell_dev, - shell_cfg_flags, log_backend, level); + shell_init(shell_zephyr, uart_shell_dev, shell_cfg_flags, log_backend, + level); /* * shell_init() always resets the priority back to the default. @@ -248,7 +248,7 @@ int zshim_run_ec_console_command(const struct zephyr_console_command *command, #if defined(CONFIG_CONSOLE_CHANNEL) && DT_NODE_EXISTS(DT_PATH(ec_console)) #define EC_CONSOLE DT_PATH(ec_console) -static const char * const disabled_channels[] = DT_PROP(EC_CONSOLE, disabled); +static const char *const disabled_channels[] = DT_PROP(EC_CONSOLE, disabled); static const size_t disabled_channel_count = DT_PROP_LEN(EC_CONSOLE, disabled); static int init_ec_console(const struct device *unused) { @@ -256,20 +256,22 @@ static int init_ec_console(const struct device *unused) console_channel_disable(disabled_channels[i]); return 0; -} SYS_INIT(init_ec_console, PRE_KERNEL_1, 50); +} +SYS_INIT(init_ec_console, PRE_KERNEL_1, 50); #endif /* CONFIG_CONSOLE_CHANNEL && DT_NODE_EXISTS(DT_PATH(ec_console)) */ static int init_ec_shell(const struct device *unused) { #if defined(CONFIG_SHELL_BACKEND_SERIAL) - shell_zephyr = shell_backend_uart_get_ptr(); + shell_zephyr = shell_backend_uart_get_ptr(); #elif defined(CONFIG_SHELL_BACKEND_DUMMY) /* nocheck */ - shell_zephyr = shell_backend_dummy_get_ptr(); /* nocheck */ + shell_zephyr = shell_backend_dummy_get_ptr(); /* nocheck */ #else #error A shell backend must be enabled #endif return 0; -} SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50); +} +SYS_INIT(init_ec_shell, PRE_KERNEL_1, 50); #ifdef TEST_BUILD const struct shell *get_ec_shell(void) @@ -348,7 +350,7 @@ static void zephyr_print(const char *buff, size_t size) * locked in ISRs. */ if (k_is_in_isr() || shell_stopped || - shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) { + shell_zephyr->ctx->state != SHELL_STATE_ACTIVE) { printk("%s", buff); } else { shell_fprintf(shell_zephyr, SHELL_NORMAL, "%s", buff); @@ -407,17 +409,17 @@ int cprints(enum console_channel channel, const char *format, ...) return EC_SUCCESS; rv = crec_snprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, "[%pT ", - PRINTF_TIMESTAMP_NOW); + PRINTF_TIMESTAMP_NOW); handle_sprintf_rv(rv, &len); va_start(args, format); rv = crec_vsnprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len, - format, args); + format, args); va_end(args); handle_sprintf_rv(rv, &len); rv = crec_snprintf(buff + len, CONFIG_SHELL_PRINTF_BUFF_SIZE - len, - "]\n"); + "]\n"); handle_sprintf_rv(rv, &len); zephyr_print(buff, len); -- cgit v1.2.1 From 604456c88999694eb15119c74047090413310a87 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:31 -0600 Subject: board/reef/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f5e91d9b0bbb65b6a5cf0f0172e8bbf0f05b0e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728883 Reviewed-by: Jeremy Bettis --- board/reef/led.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/board/reef/led.c b/board/reef/led.c index 807b1c109c..c4b8e53e36 100644 --- a/board/reef/led.c +++ b/board/reef/led.c @@ -27,8 +27,7 @@ #define LED_ON_1SEC_TICKS 1 #define LED_ON_2SECS_TICKS 2 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -36,7 +35,7 @@ enum led_color { LED_OFF = 0, LED_BLUE, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -112,16 +111,19 @@ static void led_set_battery(void) } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Blink once every four seconds. */ led_set_color_battery( - (suspend_ticks % LED_TOTAL_4SECS_TICKS) - < LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF); + (suspend_ticks % LED_TOTAL_4SECS_TICKS) < + LED_ON_1SEC_TICKS ? + LED_AMBER : + LED_OFF); } else { led_set_color_battery(LED_OFF); } break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % LED_TOTAL_2SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS < + LED_ON_1SEC_TICKS) ? + LED_AMBER : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_BLUE); @@ -130,7 +132,9 @@ static void led_set_battery(void) if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) led_set_color_battery( (battery_ticks % LED_TOTAL_4SECS_TICKS < - LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE); + LED_ON_2SECS_TICKS) ? + LED_AMBER : + LED_BLUE); else led_set_color_battery(LED_BLUE); break; -- cgit v1.2.1 From 32d8151915c66fc6a388582e21af7e3db81f4dcd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:55 -0600 Subject: baseboard/octopus/variant_ec_npcx796fb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia740d90c7fca12745336267926b637aed8a6ea08 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727940 Reviewed-by: Jeremy Bettis --- baseboard/octopus/variant_ec_npcx796fb.c | 77 ++++++++++++++------------------ 1 file changed, 33 insertions(+), 44 deletions(-) diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c index 8c3cbd2460..e9e6da03e5 100644 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ b/baseboard/octopus/variant_ec_npcx796fb.c @@ -31,49 +31,37 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* I2C port map configuration */ const struct i2c_port_t i2c_ports[] = { - { - .name = "battery", - .port = I2C_PORT_BATTERY, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "charger", - .port = I2C_PORT_CHARGER, - .kbps = 100, - .scl = GPIO_I2C4_SCL, - .sda = GPIO_I2C4_SDA - }, + { .name = "battery", + .port = I2C_PORT_BATTERY, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "charger", + .port = I2C_PORT_CHARGER, + .kbps = 100, + .scl = GPIO_I2C4_SCL, + .sda = GPIO_I2C4_SDA }, #ifndef VARIANT_OCTOPUS_NO_SENSORS - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 100, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 100, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, #endif }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -82,8 +70,9 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = PWM_CONFIG_DSLEEP, - .freq = 100 }, + [PWM_CH_KBLIGHT] = { .channel = 3, + .flags = PWM_CONFIG_DSLEEP, + .freq = 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); #endif -- cgit v1.2.1 From 1dd23cf30273c5695fcca68379b4a5415ead3130 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:02 -0600 Subject: include/spi_nor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I77a8e4a6e0ac190944496c8057db321ed4bb3f03 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730410 Reviewed-by: Jeremy Bettis --- include/spi_nor.h | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/include/spi_nor.h b/include/spi_nor.h index f0c379cd43..8f1caeded6 100644 --- a/include/spi_nor.h +++ b/include/spi_nor.h @@ -63,32 +63,32 @@ extern const unsigned int spi_nor_devices_used; /* Industry standard Serial NOR Flash opcodes. All other opcodes are part * specific and require SFDP discovery. */ -#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ -#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ -#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ +#define SPI_NOR_OPCODE_WRITE_STATUS 0x01 /* Write Status Register (1 Byte) */ +#define SPI_NOR_OPCODE_PAGE_PROGRAM 0x02 /* Page program */ +#define SPI_NOR_OPCODE_SLOW_READ 0x03 /* Read data (low frequency) */ #define SPI_NOR_OPCODE_WRITE_DISABLE 0x04 -#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ -#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 -#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ -#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ -#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ -#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ -#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ -#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ +#define SPI_NOR_OPCODE_READ_STATUS 0x05 /* Read Status Register */ +#define SPI_NOR_OPCODE_WRITE_ENABLE 0x06 +#define SPI_NOR_OPCODE_FAST_READ 0x0b /* Read data (high frequency) */ +#define SPI_NOR_OPCODE_SFDP 0x5a /* Read JEDEC SFDP */ +#define SPI_NOR_OPCODE_JEDEC_ID 0x9f /* Read JEDEC ID */ +#define SPI_NOR_OPCODE_WREAR 0xc5 /* Write extended address register */ +#define SPI_NOR_OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ +#define SPI_NOR_OPCODE_RDEAR 0xc8 /* Read extended address register */ /* Flags for SPI_NOR_OPCODE_READ_STATUS */ -#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ -#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ +#define SPI_NOR_STATUS_REGISTER_WIP BIT(0) /* Write in progres */ +#define SPI_NOR_STATUS_REGISTER_WEL BIT(1) /* Write enabled latch */ /* If needed in the future this driver can be extended to discover SFDP * advertised erase sizes and opcodes for SFDP v1.0+. */ -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_4KIB_ERASE 0x20 #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_64KIB_ERASE 0xd8 /* If needed in the future this driver can be extended to discover 4B entry and * exit methods for SFDP v1.5+. */ #define SPI_NOR_DRIVER_SPECIFIED_OPCODE_ENTER_4B 0xb7 -#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 +#define SPI_NOR_DRIVER_SPECIFIED_OPCODE_EXIT_4B 0xe9 /* JEDEC JEP106AR specifies 9 Manufacturer ID banks, read 12 to be sure. */ #define SPI_NOR_JEDEC_ID_BANKS 12 @@ -144,8 +144,8 @@ int spi_nor_read_jedec_id(const struct spi_nor_device_t *spi_nor_device, * @param data Destination buffer for data. * @return ec_error_list (non-zero on error and timeout). */ -int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, - uint32_t offset, size_t size, uint8_t *data); +int spi_nor_read(const struct spi_nor_device_t *spi_nor_device, uint32_t offset, + size_t size, uint8_t *data); /** * Erase flash on the Serial Flash Device. @@ -181,5 +181,4 @@ int spi_nor_write(const struct spi_nor_device_t *spi_nor_device, int spi_nor_write_ear(const struct spi_nor_device_t *spi_nor_device, const uint8_t value); - -#endif /* __CROS_EC_SPI_NOR_H */ +#endif /* __CROS_EC_SPI_NOR_H */ -- cgit v1.2.1 From 8b60298879327415c9bfc11505b593d857713b8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:12 -0600 Subject: test/lightbar.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibbbdc4360f82d3d757dd21f89b5d61edac2842b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730482 Reviewed-by: Jeremy Bettis --- test/lightbar.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/test/lightbar.c b/test/lightbar.c index 363d73a36b..3818c30684 100644 --- a/test/lightbar.c +++ b/test/lightbar.c @@ -20,9 +20,8 @@ static int get_seq(void) /* Get the state */ memset(&resp, 0, sizeof(resp)); params.cmd = LIGHTBAR_CMD_GET_SEQ; - rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); if (rv != EC_RES_SUCCESS) { ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv); return -1; @@ -41,9 +40,8 @@ static int set_seq(int s) memset(&resp, 0, sizeof(resp)); params.cmd = LIGHTBAR_CMD_SEQ; params.seq.num = s; - rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, - ¶ms, sizeof(params), - &resp, sizeof(resp)); + rv = test_send_host_command(EC_CMD_LIGHTBAR_CMD, 0, ¶ms, + sizeof(params), &resp, sizeof(resp)); if (rv != EC_RES_SUCCESS) { ccprintf("%s:%s(): rv = %d\n", __FILE__, __func__, rv); return -1; @@ -169,9 +167,8 @@ test_static int test_stop_timeout(void) TEST_ASSERT(set_seq(i) == EC_RES_SUCCESS); usleep(SECOND); /* What happened? */ - if (i == LIGHTBAR_RUN || - i == LIGHTBAR_S0S3 || i == LIGHTBAR_S3 || - i == LIGHTBAR_S3S5 || i == LIGHTBAR_S5) + if (i == LIGHTBAR_RUN || i == LIGHTBAR_S0S3 || + i == LIGHTBAR_S3 || i == LIGHTBAR_S3S5 || i == LIGHTBAR_S5) /* RUN or shutdown sequences should stop it */ TEST_ASSERT(get_seq() == LIGHTBAR_S0); else @@ -290,7 +287,7 @@ const struct lb_brightness_def lb_brightness_levels[] = { }, }; const unsigned int lb_brightness_levels_count = - ARRAY_SIZE(lb_brightness_levels); + ARRAY_SIZE(lb_brightness_levels); int lux_level_to_google_color(const int lux); extern int google_color_id; @@ -303,8 +300,8 @@ int lid_is_open(void) test_static int test_als_lightbar(void) { int lux_data[] = { 500, 100, 35, 15, 30, 35, 55, 70, 55, 100 }; - int exp_gcid[] = { 0, 0, 1, 2, 2, 2, 1, 0, 0, 0 }; - int exp_chg[] = { 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 }; + int exp_gcid[] = { 0, 0, 1, 2, 2, 2, 1, 0, 0, 0 }; + int exp_chg[] = { 0, 0, 1, 1, 0, 0, 1, 1, 0, 0 }; int i; BUILD_ASSERT(ARRAY_SIZE(lux_data) == ARRAY_SIZE(exp_gcid)); -- cgit v1.2.1 From 7cf63fd8ba1d6c1305eabe279b7477cf0eeb9c3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:52 -0600 Subject: board/host/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife0835934ef8eb9589a6bac5fa6faba9b1dd5887 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728472 Reviewed-by: Jeremy Bettis --- board/host/fan.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/host/fan.c b/board/host/fan.c index 1e1001f1cd..40d59609fd 100644 --- a/board/host/fan.c +++ b/board/host/fan.c @@ -22,7 +22,10 @@ const struct fan_rpm fan_rpm_0 = { }; const struct fan_t fans[CONFIG_FANS] = { - { .conf = &fan_conf_0, .rpm = &fan_rpm_0, }, + { + .conf = &fan_conf_0, + .rpm = &fan_rpm_0, + }, }; static int mock_enabled; -- cgit v1.2.1 From bdd7f101ff07910ef06d07231c8526ac2137e70b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:14 -0600 Subject: driver/wpc/p9221.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib40a3a3d7321cb718e02bb9357ae9b283dce0503 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730177 Reviewed-by: Jeremy Bettis --- driver/wpc/p9221.h | 392 ++++++++++++++++++++++++++--------------------------- 1 file changed, 193 insertions(+), 199 deletions(-) diff --git a/driver/wpc/p9221.h b/driver/wpc/p9221.h index 0bb0571b38..674d458b90 100644 --- a/driver/wpc/p9221.h +++ b/driver/wpc/p9221.h @@ -3,7 +3,6 @@ * found in the LICENSE file. */ - /* * IDT P9221-R7 Wireless Power Receiver driver definitions. */ @@ -16,248 +15,243 @@ #include "charge_manager.h" #include "task.h" - /* ========== Variant-specific configuration ============ */ -#define P9221_R7_ADDR_FLAGS 0x61 +#define P9221_R7_ADDR_FLAGS 0x61 /* * P9221 common registers */ -#define P9221_CHIP_ID_REG 0x00 -#define P9221_CHIP_ID 0x9220 -#define P9221_CHIP_REVISION_REG 0x02 -#define P9221_CUSTOMER_ID_REG 0x03 -#define P9221R7_CUSTOMER_ID_VAL 0x05 -#define P9221_OTP_FW_MAJOR_REV_REG 0x04 -#define P9221_OTP_FW_MINOR_REV_REG 0x06 -#define P9221_OTP_FW_DATE_REG 0x08 -#define P9221_OTP_FW_DATE_SIZE 12 -#define P9221_OTP_FW_TIME_REG 0x14 -#define P9221_OTP_FW_TIME_SIZE 8 -#define P9221_SRAM_FW_MAJOR_REV_REG 0x1C -#define P9221_SRAM_FW_MINOR_REV_REG 0x1E -#define P9221_SRAM_FW_DATE_REG 0x20 -#define P9221_SRAM_FW_DATE_SIZE 12 -#define P9221_SRAM_FW_TIME_REG 0x2C -#define P9221_SRAM_FW_TIME_SIZE 8 -#define P9221_STATUS_REG 0x34 -#define P9221_INT_REG 0x36 -#define P9221_INT_MASK 0xF7 -#define P9221_INT_ENABLE_REG 0x38 -#define P9221_GPP_TX_MF_ID 0x0072 +#define P9221_CHIP_ID_REG 0x00 +#define P9221_CHIP_ID 0x9220 +#define P9221_CHIP_REVISION_REG 0x02 +#define P9221_CUSTOMER_ID_REG 0x03 +#define P9221R7_CUSTOMER_ID_VAL 0x05 +#define P9221_OTP_FW_MAJOR_REV_REG 0x04 +#define P9221_OTP_FW_MINOR_REV_REG 0x06 +#define P9221_OTP_FW_DATE_REG 0x08 +#define P9221_OTP_FW_DATE_SIZE 12 +#define P9221_OTP_FW_TIME_REG 0x14 +#define P9221_OTP_FW_TIME_SIZE 8 +#define P9221_SRAM_FW_MAJOR_REV_REG 0x1C +#define P9221_SRAM_FW_MINOR_REV_REG 0x1E +#define P9221_SRAM_FW_DATE_REG 0x20 +#define P9221_SRAM_FW_DATE_SIZE 12 +#define P9221_SRAM_FW_TIME_REG 0x2C +#define P9221_SRAM_FW_TIME_SIZE 8 +#define P9221_STATUS_REG 0x34 +#define P9221_INT_REG 0x36 +#define P9221_INT_MASK 0xF7 +#define P9221_INT_ENABLE_REG 0x38 +#define P9221_GPP_TX_MF_ID 0x0072 /* * P9221 Rx registers (x != 5) */ -#define P9221_CHARGE_STAT_REG 0x3A -#define P9221_EPT_REG 0x3B -#define P9221_VOUT_ADC_REG 0x3C -#define P9221_VOUT_ADC_MASK 0x0FFF -#define P9221_VOUT_SET_REG 0x3E -#define P9221_MAX_VOUT_SET_MV_DEFAULT 9000 -#define P9221_VRECT_ADC_REG 0x40 -#define P9221_VRECT_ADC_MASK 0x0FFF -#define P9221_OVSET_REG 0x42 -#define P9221_OVSET_MASK 0x70 -#define P9221_OVSET_SHIFT 4 -#define P9221_RX_IOUT_REG 0x44 -#define P9221_DIE_TEMP_ADC_REG 0x46 -#define P9221_DIE_TEMP_ADC_MASK 0x0FFF -#define P9221_OP_FREQ_REG 0x48 -#define P9221_ILIM_SET_REG 0x4A -#define P9221_ALIGN_X_ADC_REG 0x4B -#define P9221_ALIGN_Y_ADC_REG 0x4C -#define P9221_OP_MODE_REG 0x4D -#define P9221_COM_REG 0x4E -#define P9221_FW_SWITCH_KEY_REG 0x4F -#define P9221_INT_CLEAR_REG 0x56 -#define P9221_RXID_REG 0x5C -#define P9221_RXID_LEN 6 -#define P9221_MPREQ_REG 0x5C -#define P9221_MPREQ_LEN 6 -#define P9221_FOD_REG 0x68 -#define P9221_NUM_FOD 16 -#define P9221_RX_RAWIOUT_REG 0x7A -#define P9221_RX_RAWIOUT_MASK 0xFFF -#define P9221_PMA_AD_REG 0x7C -#define P9221_RX_PINGFREQ_REG 0xFC -#define P9221_RX_PINGFREQ_MASK 0xFFF -#define P9221_LAST_REG 0xFF +#define P9221_CHARGE_STAT_REG 0x3A +#define P9221_EPT_REG 0x3B +#define P9221_VOUT_ADC_REG 0x3C +#define P9221_VOUT_ADC_MASK 0x0FFF +#define P9221_VOUT_SET_REG 0x3E +#define P9221_MAX_VOUT_SET_MV_DEFAULT 9000 +#define P9221_VRECT_ADC_REG 0x40 +#define P9221_VRECT_ADC_MASK 0x0FFF +#define P9221_OVSET_REG 0x42 +#define P9221_OVSET_MASK 0x70 +#define P9221_OVSET_SHIFT 4 +#define P9221_RX_IOUT_REG 0x44 +#define P9221_DIE_TEMP_ADC_REG 0x46 +#define P9221_DIE_TEMP_ADC_MASK 0x0FFF +#define P9221_OP_FREQ_REG 0x48 +#define P9221_ILIM_SET_REG 0x4A +#define P9221_ALIGN_X_ADC_REG 0x4B +#define P9221_ALIGN_Y_ADC_REG 0x4C +#define P9221_OP_MODE_REG 0x4D +#define P9221_COM_REG 0x4E +#define P9221_FW_SWITCH_KEY_REG 0x4F +#define P9221_INT_CLEAR_REG 0x56 +#define P9221_RXID_REG 0x5C +#define P9221_RXID_LEN 6 +#define P9221_MPREQ_REG 0x5C +#define P9221_MPREQ_LEN 6 +#define P9221_FOD_REG 0x68 +#define P9221_NUM_FOD 16 +#define P9221_RX_RAWIOUT_REG 0x7A +#define P9221_RX_RAWIOUT_MASK 0xFFF +#define P9221_PMA_AD_REG 0x7C +#define P9221_RX_PINGFREQ_REG 0xFC +#define P9221_RX_PINGFREQ_MASK 0xFFF +#define P9221_LAST_REG 0xFF /* * P9221R7 unique registers */ -#define P9221R7_INT_CLEAR_REG 0x3A -#define P9221R7_VOUT_SET_REG 0x3C -#define P9221R7_ILIM_SET_REG 0x3D -#define P9221R7_ILIM_SET_MAX 0x0E /* 0x0E = 1.6A */ -#define P9221R7_CHARGE_STAT_REG 0x3E -#define P9221R7_EPT_REG 0x3F -#define P9221R7_VRECT_REG 0x40 -#define P9221R7_VOUT_REG 0x42 -#define P9221R7_IOUT_REG 0x44 -#define P9221R7_OP_FREQ_REG 0x48 -#define P9221R7_SYSTEM_MODE_REG 0x4C -#define P9221R7_COM_CHAN_RESET_REG 0x50 -#define P9221R7_COM_CHAN_SEND_SIZE_REG 0x58 -#define P9221R7_COM_CHAN_SEND_IDX_REG 0x59 -#define P9221R7_COM_CHAN_RECV_SIZE_REG 0x5A -#define P9221R7_COM_CHAN_RECV_IDX_REG 0x5B -#define P9221R7_VRECT_ADC_REG 0x60 -#define P9221R7_VOUT_ADC_REG 0x62 -#define P9221R7_VOUT_ADC_MASK 0xFFF -#define P9221R7_IOUT_ADC_REG 0x64 -#define P9221R7_IOUT_ADC_MASK 0xFFF -#define P9221R7_DIE_TEMP_ADC_REG 0x66 -#define P9221R7_DIE_TEMP_ADC_MASK 0xFFF -#define P9221R7_AC_PERIOD_REG 0x68 -#define P9221R7_TX_PINGFREQ_REG 0x6A -#define P9221R7_EXT_TEMP_REG 0x6C -#define P9221R7_EXT_TEMP_MASK 0xFFF -#define P9221R7_FOD_REG 0x70 -#define P9221R7_NUM_FOD 16 -#define P9221R7_DEBUG_REG 0x80 -#define P9221R7_EPP_Q_FACTOR_REG 0x83 -#define P9221R7_EPP_TX_GUARANTEED_POWER_REG 0x84 -#define P9221R7_EPP_TX_POTENTIAL_POWER_REG 0x85 -#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG 0x86 -#define P9221R7_EPP_RENEGOTIATION_REG 0x87 -#define P9221R7_EPP_CUR_RPP_HEADER_REG 0x88 -#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG 0x89 -#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG 0x8A -#define P9221R7_EPP_CUR_FSK_MODULATION_REG 0x8B -#define P9221R7_EPP_REQ_RPP_HEADER_REG 0x8C -#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG 0x8D -#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG 0x8E -#define P9221R7_EPP_REQ_FSK_MODULATION_REG 0x8F -#define P9221R7_VRECT_TARGET_REG 0x90 -#define P9221R7_VRECT_KNEE_REG 0x92 -#define P9221R7_VRECT_CORRECTION_FACTOR_REG 0x93 -#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG 0x94 -#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG 0x96 -#define P9221R7_FOD_SECTION_REG 0x99 -#define P9221R7_VRECT_ADJ_REG 0x9E -#define P9221R7_ALIGN_X_ADC_REG 0xA0 -#define P9221R7_ALIGN_Y_ADC_REG 0xA1 -#define P9221R7_ASK_MODULATION_DEPTH_REG 0xA2 -#define P9221R7_OVSET_REG 0xA3 -#define P9221R7_OVSET_MASK 0x7 -#define P9221R7_EPP_TX_SPEC_REV_REG 0xA9 -#define P9221R7_EPP_TX_MFG_CODE_REG 0xAA -#define P9221R7_GP0_RESET_VOLT_REG 0xAC -#define P9221R7_GP1_RESET_VOLT_REG 0xAE -#define P9221R7_GP2_RESET_VOLT_REG 0xB0 -#define P9221R7_GP3_RESET_VOLT_REG 0xB2 -#define P9221R7_PROP_TX_ID_REG 0xB4 -#define P9221R7_PROP_TX_ID_SIZE 4 -#define P9221R7_DATA_SEND_BUF_START 0x100 -#define P9221R7_DATA_SEND_BUF_SIZE 0x80 -#define P9221R7_DATA_RECV_BUF_START 0x180 -#define P9221R7_DATA_RECV_BUF_SIZE 0x80 -#define P9221R7_MAX_PP_BUF_SIZE 16 -#define P9221R7_LAST_REG 0x1FF +#define P9221R7_INT_CLEAR_REG 0x3A +#define P9221R7_VOUT_SET_REG 0x3C +#define P9221R7_ILIM_SET_REG 0x3D +#define P9221R7_ILIM_SET_MAX 0x0E /* 0x0E = 1.6A */ +#define P9221R7_CHARGE_STAT_REG 0x3E +#define P9221R7_EPT_REG 0x3F +#define P9221R7_VRECT_REG 0x40 +#define P9221R7_VOUT_REG 0x42 +#define P9221R7_IOUT_REG 0x44 +#define P9221R7_OP_FREQ_REG 0x48 +#define P9221R7_SYSTEM_MODE_REG 0x4C +#define P9221R7_COM_CHAN_RESET_REG 0x50 +#define P9221R7_COM_CHAN_SEND_SIZE_REG 0x58 +#define P9221R7_COM_CHAN_SEND_IDX_REG 0x59 +#define P9221R7_COM_CHAN_RECV_SIZE_REG 0x5A +#define P9221R7_COM_CHAN_RECV_IDX_REG 0x5B +#define P9221R7_VRECT_ADC_REG 0x60 +#define P9221R7_VOUT_ADC_REG 0x62 +#define P9221R7_VOUT_ADC_MASK 0xFFF +#define P9221R7_IOUT_ADC_REG 0x64 +#define P9221R7_IOUT_ADC_MASK 0xFFF +#define P9221R7_DIE_TEMP_ADC_REG 0x66 +#define P9221R7_DIE_TEMP_ADC_MASK 0xFFF +#define P9221R7_AC_PERIOD_REG 0x68 +#define P9221R7_TX_PINGFREQ_REG 0x6A +#define P9221R7_EXT_TEMP_REG 0x6C +#define P9221R7_EXT_TEMP_MASK 0xFFF +#define P9221R7_FOD_REG 0x70 +#define P9221R7_NUM_FOD 16 +#define P9221R7_DEBUG_REG 0x80 +#define P9221R7_EPP_Q_FACTOR_REG 0x83 +#define P9221R7_EPP_TX_GUARANTEED_POWER_REG 0x84 +#define P9221R7_EPP_TX_POTENTIAL_POWER_REG 0x85 +#define P9221R7_EPP_TX_CAPABILITY_FLAGS_REG 0x86 +#define P9221R7_EPP_RENEGOTIATION_REG 0x87 +#define P9221R7_EPP_CUR_RPP_HEADER_REG 0x88 +#define P9221R7_EPP_CUR_NEGOTIATED_POWER_REG 0x89 +#define P9221R7_EPP_CUR_MAXIMUM_POWER_REG 0x8A +#define P9221R7_EPP_CUR_FSK_MODULATION_REG 0x8B +#define P9221R7_EPP_REQ_RPP_HEADER_REG 0x8C +#define P9221R7_EPP_REQ_NEGOTIATED_POWER_REG 0x8D +#define P9221R7_EPP_REQ_MAXIMUM_POWER_REG 0x8E +#define P9221R7_EPP_REQ_FSK_MODULATION_REG 0x8F +#define P9221R7_VRECT_TARGET_REG 0x90 +#define P9221R7_VRECT_KNEE_REG 0x92 +#define P9221R7_VRECT_CORRECTION_FACTOR_REG 0x93 +#define P9221R7_VRECT_MAX_CORRECTION_FACTOR_REG 0x94 +#define P9221R7_VRECT_MIN_CORRECTION_FACTOR_REG 0x96 +#define P9221R7_FOD_SECTION_REG 0x99 +#define P9221R7_VRECT_ADJ_REG 0x9E +#define P9221R7_ALIGN_X_ADC_REG 0xA0 +#define P9221R7_ALIGN_Y_ADC_REG 0xA1 +#define P9221R7_ASK_MODULATION_DEPTH_REG 0xA2 +#define P9221R7_OVSET_REG 0xA3 +#define P9221R7_OVSET_MASK 0x7 +#define P9221R7_EPP_TX_SPEC_REV_REG 0xA9 +#define P9221R7_EPP_TX_MFG_CODE_REG 0xAA +#define P9221R7_GP0_RESET_VOLT_REG 0xAC +#define P9221R7_GP1_RESET_VOLT_REG 0xAE +#define P9221R7_GP2_RESET_VOLT_REG 0xB0 +#define P9221R7_GP3_RESET_VOLT_REG 0xB2 +#define P9221R7_PROP_TX_ID_REG 0xB4 +#define P9221R7_PROP_TX_ID_SIZE 4 +#define P9221R7_DATA_SEND_BUF_START 0x100 +#define P9221R7_DATA_SEND_BUF_SIZE 0x80 +#define P9221R7_DATA_RECV_BUF_START 0x180 +#define P9221R7_DATA_RECV_BUF_SIZE 0x80 +#define P9221R7_MAX_PP_BUF_SIZE 16 +#define P9221R7_LAST_REG 0x1FF /* * System Mode Mask (r7+/0x4C) */ -#define P9221R7_SYSTEM_MODE_EXTENDED_MASK (1 << 3) +#define P9221R7_SYSTEM_MODE_EXTENDED_MASK (1 << 3) /* * TX ID GPP Mask (r7+/0xB4->0xB7) */ -#define P9221R7_PROP_TX_ID_GPP_MASK (1 << 29) +#define P9221R7_PROP_TX_ID_GPP_MASK (1 << 29) /* * Com Channel Commands */ -#define P9221R7_COM_CHAN_CCRESET BIT(7) -#define P9221_COM_CHAN_RETRIES 5 +#define P9221R7_COM_CHAN_CCRESET BIT(7) +#define P9221_COM_CHAN_RETRIES 5 /* * End of Power packet types */ -#define P9221_EOP_UNKNOWN 0x00 -#define P9221_EOP_EOC 0x01 -#define P9221_EOP_INTERNAL_FAULT 0x02 -#define P9221_EOP_OVER_TEMP 0x03 -#define P9221_EOP_OVER_VOLT 0x04 -#define P9221_EOP_OVER_CURRENT 0x05 -#define P9221_EOP_BATT_FAIL 0x06 -#define P9221_EOP_RECONFIG 0x07 -#define P9221_EOP_NO_RESPONSE 0x08 -#define P9221_EOP_NEGOTIATION_FAIL 0x0A -#define P9221_EOP_RESTART_POWER 0x0B +#define P9221_EOP_UNKNOWN 0x00 +#define P9221_EOP_EOC 0x01 +#define P9221_EOP_INTERNAL_FAULT 0x02 +#define P9221_EOP_OVER_TEMP 0x03 +#define P9221_EOP_OVER_VOLT 0x04 +#define P9221_EOP_OVER_CURRENT 0x05 +#define P9221_EOP_BATT_FAIL 0x06 +#define P9221_EOP_RECONFIG 0x07 +#define P9221_EOP_NO_RESPONSE 0x08 +#define P9221_EOP_NEGOTIATION_FAIL 0x0A +#define P9221_EOP_RESTART_POWER 0x0B /* * Command flags */ -#define P9221R7_COM_RENEGOTIATE P9221_COM_RENEGOTIATE -#define P9221R7_COM_SWITCH2RAM P9221_COM_SWITCH_TO_RAM_MASK -#define P9221R7_COM_CLRINT P9221_COM_CLEAR_INT_MASK -#define P9221R7_COM_SENDCSP P9221_COM_SEND_CHG_STAT_MASK -#define P9221R7_COM_SENDEPT P9221_COM_SEND_EOP_MASK -#define P9221R7_COM_LDOTGL P9221_COM_LDO_TOGGLE -#define P9221R7_COM_CCACTIVATE BIT(0) +#define P9221R7_COM_RENEGOTIATE P9221_COM_RENEGOTIATE +#define P9221R7_COM_SWITCH2RAM P9221_COM_SWITCH_TO_RAM_MASK +#define P9221R7_COM_CLRINT P9221_COM_CLEAR_INT_MASK +#define P9221R7_COM_SENDCSP P9221_COM_SEND_CHG_STAT_MASK +#define P9221R7_COM_SENDEPT P9221_COM_SEND_EOP_MASK +#define P9221R7_COM_LDOTGL P9221_COM_LDO_TOGGLE +#define P9221R7_COM_CCACTIVATE BIT(0) -#define P9221_COM_RENEGOTIATE BIT(7) -#define P9221_COM_SWITCH_TO_RAM_MASK BIT(6) -#define P9221_COM_CLEAR_INT_MASK BIT(5) -#define P9221_COM_SEND_CHG_STAT_MASK BIT(4) -#define P9221_COM_SEND_EOP_MASK BIT(3) -#define P9221_COM_LDO_TOGGLE BIT(1) +#define P9221_COM_RENEGOTIATE BIT(7) +#define P9221_COM_SWITCH_TO_RAM_MASK BIT(6) +#define P9221_COM_CLEAR_INT_MASK BIT(5) +#define P9221_COM_SEND_CHG_STAT_MASK BIT(4) +#define P9221_COM_SEND_EOP_MASK BIT(3) +#define P9221_COM_LDO_TOGGLE BIT(1) /* * Interrupt/Status flags for P9221 */ -#define P9221_STAT_VOUT BIT(7) -#define P9221_STAT_VRECT BIT(6) -#define P9221_STAT_ACMISSING BIT(5) -#define P9221_STAT_OV_TEMP BIT(2) -#define P9221_STAT_OV_VOLT BIT(1) -#define P9221_STAT_OV_CURRENT BIT(0) -#define P9221_STAT_LIMIT_MASK (P9221_STAT_OV_TEMP | \ - P9221_STAT_OV_VOLT | \ - P9221_STAT_OV_CURRENT) +#define P9221_STAT_VOUT BIT(7) +#define P9221_STAT_VRECT BIT(6) +#define P9221_STAT_ACMISSING BIT(5) +#define P9221_STAT_OV_TEMP BIT(2) +#define P9221_STAT_OV_VOLT BIT(1) +#define P9221_STAT_OV_CURRENT BIT(0) +#define P9221_STAT_LIMIT_MASK \ + (P9221_STAT_OV_TEMP | P9221_STAT_OV_VOLT | P9221_STAT_OV_CURRENT) /* * Interrupt/Status flags for P9221R7 */ -#define P9221R7_STAT_CCRESET BIT(12) -#define P9221R7_STAT_CCERROR BIT(11) -#define P9221R7_STAT_PPRCVD BIT(10) -#define P9221R7_STAT_CCDATARCVD BIT(9) -#define P9221R7_STAT_CCSENDBUSY BIT(8) -#define P9221R7_STAT_VOUTCHANGED BIT(7) -#define P9221R7_STAT_VRECTON BIT(6) -#define P9221R7_STAT_MODECHANGED BIT(5) -#define P9221R7_STAT_UV BIT(3) -#define P9221R7_STAT_OVT BIT(2) -#define P9221R7_STAT_OVV BIT(1) -#define P9221R7_STAT_OVC BIT(0) -#define P9221R7_STAT_MASK 0x1FFF -#define P9221R7_STAT_CC_MASK (P9221R7_STAT_CCRESET | \ - P9221R7_STAT_PPRCVD | \ - P9221R7_STAT_CCERROR | \ - P9221R7_STAT_CCDATARCVD | \ - P9221R7_STAT_CCSENDBUSY) -#define P9221R7_STAT_LIMIT_MASK (P9221R7_STAT_UV | \ - P9221R7_STAT_OVV | \ - P9221R7_STAT_OVT | \ - P9221R7_STAT_OVC) +#define P9221R7_STAT_CCRESET BIT(12) +#define P9221R7_STAT_CCERROR BIT(11) +#define P9221R7_STAT_PPRCVD BIT(10) +#define P9221R7_STAT_CCDATARCVD BIT(9) +#define P9221R7_STAT_CCSENDBUSY BIT(8) +#define P9221R7_STAT_VOUTCHANGED BIT(7) +#define P9221R7_STAT_VRECTON BIT(6) +#define P9221R7_STAT_MODECHANGED BIT(5) +#define P9221R7_STAT_UV BIT(3) +#define P9221R7_STAT_OVT BIT(2) +#define P9221R7_STAT_OVV BIT(1) +#define P9221R7_STAT_OVC BIT(0) +#define P9221R7_STAT_MASK 0x1FFF +#define P9221R7_STAT_CC_MASK \ + (P9221R7_STAT_CCRESET | P9221R7_STAT_PPRCVD | P9221R7_STAT_CCERROR | \ + P9221R7_STAT_CCDATARCVD | P9221R7_STAT_CCSENDBUSY) +#define P9221R7_STAT_LIMIT_MASK \ + (P9221R7_STAT_UV | P9221R7_STAT_OVV | P9221R7_STAT_OVT | \ + P9221R7_STAT_OVC) -#define P9221_DC_ICL_BPP_MA 1000 -#define P9221_DC_ICL_EPP_MA 1100 -#define P9221_DC_IVL_BPP_MV 5000 -#define P9221_DC_IVL_EPP_MV 9000 -#define P9221_EPP_THRESHOLD_UV 7000000 +#define P9221_DC_ICL_BPP_MA 1000 +#define P9221_DC_ICL_EPP_MA 1100 +#define P9221_DC_IVL_BPP_MV 5000 +#define P9221_DC_IVL_EPP_MV 9000 +#define P9221_EPP_THRESHOLD_UV 7000000 -#define true 1 -#define false 0 +#define true 1 +#define false 0 struct wpc_charger_info { - uint8_t online; /* wpc is online */ - uint8_t cust_id; /* customer id */ - uint8_t i2c_port; /* i2c port */ + uint8_t online; /* wpc is online */ + uint8_t cust_id; /* customer id */ + uint8_t i2c_port; /* i2c port */ /* Proprietary Packets receive buffer, to get Proprietary data from TX*/ uint8_t pp_buf[P9221R7_MAX_PP_BUF_SIZE]; uint8_t pp_buf_valid; @@ -267,8 +261,8 @@ struct wpc_charger_info { uint8_t rx_done; /* Message packets send buffer, used when send messages from RX to TX*/ uint8_t tx_buf[P9221R7_DATA_SEND_BUF_SIZE]; - uint8_t tx_id; /* TX device id */ - uint8_t tx_len; /* The data size need send to TX */ + uint8_t tx_id; /* TX device id */ + uint8_t tx_len; /* The data size need send to TX */ uint8_t tx_done; /* TX data send has done */ uint8_t tx_busy; /* when tx_busy=1, can't transfer data from RX to TX */ /* p9221_check_vbus=1 when VBUS has changed, need update charge state */ -- cgit v1.2.1 From 3ee1036ee32d12f4b92ac2b2557483b9113bd705 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:00 -0600 Subject: common/mock/tcpci_i2c_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I447666741c8570a34f602ddf1f5c8dde23d032fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729676 Reviewed-by: Jeremy Bettis --- common/mock/tcpci_i2c_mock.c | 325 ++++++++++++++++++++----------------------- 1 file changed, 153 insertions(+), 172 deletions(-) diff --git a/common/mock/tcpci_i2c_mock.c b/common/mock/tcpci_i2c_mock.c index c9b9f71738..8c526ca692 100644 --- a/common/mock/tcpci_i2c_mock.c +++ b/common/mock/tcpci_i2c_mock.c @@ -18,15 +18,19 @@ #define VERIFY_TIMEOUT (5 * SECOND) struct tcpci_reg { - uint8_t offset; - uint8_t size; - uint16_t value; - const char *name; + uint8_t offset; + uint8_t size; + uint16_t value; + const char *name; }; -#define TCPCI_REG(reg_name, reg_size) \ - [reg_name] = { .offset = (reg_name), .size = (reg_size), \ - .value = 0, .name = #reg_name, } +#define TCPCI_REG(reg_name, reg_size) \ + [reg_name] = { \ + .offset = (reg_name), \ + .size = (reg_size), \ + .value = 0, \ + .name = #reg_name, \ + } static struct tcpci_reg tcpci_regs[] = { TCPCI_REG(TCPC_REG_VENDOR_ID, 2), @@ -76,111 +80,109 @@ static int tx_retry_cnt = -1; static uint8_t rx_buffer[BUFFER_SIZE]; static int rx_pos = -1; -static const char * const ctrl_msg_name[] = { - [0] = "C-RSVD_0", - [PD_CTRL_GOOD_CRC] = "C-GOODCRC", - [PD_CTRL_GOTO_MIN] = "C-GOTOMIN", - [PD_CTRL_ACCEPT] = "C-ACCEPT", - [PD_CTRL_REJECT] = "C-REJECT", - [PD_CTRL_PING] = "C-PING", - [PD_CTRL_PS_RDY] = "C-PSRDY", - [PD_CTRL_GET_SOURCE_CAP] = "C-GET_SRC_CAP", - [PD_CTRL_GET_SINK_CAP] = "C-GET_SNK_CAP", - [PD_CTRL_DR_SWAP] = "C-DR_SWAP", - [PD_CTRL_PR_SWAP] = "C-PR_SWAP", - [PD_CTRL_VCONN_SWAP] = "C-VCONN_SW", - [PD_CTRL_WAIT] = "C-WAIT", - [PD_CTRL_SOFT_RESET] = "C-SOFT-RESET", - [14] = "C-RSVD_14", - [15] = "C-RSVD_15", - [PD_CTRL_NOT_SUPPORTED] = "C-NOT_SUPPORTED", - [PD_CTRL_GET_SOURCE_CAP_EXT] = "C-GET_SRC_CAP-EXT", - [PD_CTRL_GET_STATUS] = "C-GET-STATUS", - [PD_CTRL_FR_SWAP] = "C-FR_SWAP", - [PD_CTRL_GET_PPS_STATUS] = "C-GET_PPS_STATUS", - [PD_CTRL_GET_COUNTRY_CODES] = "C-GET_COUNTRY_CODES", - [PD_CTRL_GET_SINK_CAP_EXT] = "C-GET_SINK_CAP_EXT", - [PD_CTRL_GET_SOURCE_INFO] = "C-GET_SOURCE_INFO", - [PD_CTRL_GET_REVISION] = "C-GET_REVISION", +static const char *const ctrl_msg_name[] = { + [0] = "C-RSVD_0", + [PD_CTRL_GOOD_CRC] = "C-GOODCRC", + [PD_CTRL_GOTO_MIN] = "C-GOTOMIN", + [PD_CTRL_ACCEPT] = "C-ACCEPT", + [PD_CTRL_REJECT] = "C-REJECT", + [PD_CTRL_PING] = "C-PING", + [PD_CTRL_PS_RDY] = "C-PSRDY", + [PD_CTRL_GET_SOURCE_CAP] = "C-GET_SRC_CAP", + [PD_CTRL_GET_SINK_CAP] = "C-GET_SNK_CAP", + [PD_CTRL_DR_SWAP] = "C-DR_SWAP", + [PD_CTRL_PR_SWAP] = "C-PR_SWAP", + [PD_CTRL_VCONN_SWAP] = "C-VCONN_SW", + [PD_CTRL_WAIT] = "C-WAIT", + [PD_CTRL_SOFT_RESET] = "C-SOFT-RESET", + [14] = "C-RSVD_14", + [15] = "C-RSVD_15", + [PD_CTRL_NOT_SUPPORTED] = "C-NOT_SUPPORTED", + [PD_CTRL_GET_SOURCE_CAP_EXT] = "C-GET_SRC_CAP-EXT", + [PD_CTRL_GET_STATUS] = "C-GET-STATUS", + [PD_CTRL_FR_SWAP] = "C-FR_SWAP", + [PD_CTRL_GET_PPS_STATUS] = "C-GET_PPS_STATUS", + [PD_CTRL_GET_COUNTRY_CODES] = "C-GET_COUNTRY_CODES", + [PD_CTRL_GET_SINK_CAP_EXT] = "C-GET_SINK_CAP_EXT", + [PD_CTRL_GET_SOURCE_INFO] = "C-GET_SOURCE_INFO", + [PD_CTRL_GET_REVISION] = "C-GET_REVISION", }; -static const char * const data_msg_name[] = { - [0] = "D-RSVD_0", - [PD_DATA_SOURCE_CAP] = "D-SRC_CAP", - [PD_DATA_REQUEST] = "D-REQUEST", - [PD_DATA_BIST] = "D-BIST", - [PD_DATA_SINK_CAP] = "D-SNK_CAP", +static const char *const data_msg_name[] = { + [0] = "D-RSVD_0", + [PD_DATA_SOURCE_CAP] = "D-SRC_CAP", + [PD_DATA_REQUEST] = "D-REQUEST", + [PD_DATA_BIST] = "D-BIST", + [PD_DATA_SINK_CAP] = "D-SNK_CAP", /* 5-14 Reserved for REV 2.0 */ - [PD_DATA_BATTERY_STATUS] = "D-BATTERY_STATUS", - [PD_DATA_ALERT] = "D-ALERT", - [PD_DATA_GET_COUNTRY_INFO] = "D-GET_COUNTRY_CODES", + [PD_DATA_BATTERY_STATUS] = "D-BATTERY_STATUS", + [PD_DATA_ALERT] = "D-ALERT", + [PD_DATA_GET_COUNTRY_INFO] = "D-GET_COUNTRY_CODES", /* 8-14 Reserved for REV 3.0 */ - [PD_DATA_ENTER_USB] = "D-ENTER_USB", - [PD_DATA_EPR_REQUEST] = "D-EPR_REQUEST", - [PD_DATA_EPR_MODE] = "D-EPR_MODE", - [PD_DATA_SOURCE_INFO] = "D-EPR_SOURCE_INFO", - [PD_DATA_REVISION] = "D-REVISION", + [PD_DATA_ENTER_USB] = "D-ENTER_USB", + [PD_DATA_EPR_REQUEST] = "D-EPR_REQUEST", + [PD_DATA_EPR_MODE] = "D-EPR_MODE", + [PD_DATA_SOURCE_INFO] = "D-EPR_SOURCE_INFO", + [PD_DATA_REVISION] = "D-REVISION", /* 13-14 Reserved for REV 3.0 */ - [PD_DATA_VENDOR_DEF] = "D-VDM", + [PD_DATA_VENDOR_DEF] = "D-VDM", }; -static const char * const ext_msg_name[] = { - [0] = "X-RSVD_0", - [PD_EXT_SOURCE_CAP] = "X-SRC_CAP", - [PD_EXT_STATUS] = "X-STATUS", - [PD_EXT_GET_BATTERY_CAP] = "X-GET_BATTERY_CAP", - [PD_EXT_GET_BATTERY_STATUS] = "X-GET_BATTERY_STATUS", - [PD_EXT_BATTERY_CAP] = "X-BATTERY_CAP", - [PD_EXT_GET_MANUFACTURER_INFO] = "X-GET_MFR_INFO", - [PD_EXT_MANUFACTURER_INFO] = "X-MFR_INFO", - [PD_EXT_SECURITY_REQUEST] = "X-SECURITY_REQ", - [PD_EXT_SECURITY_RESPONSE] = "X-SECURITY_RESP", +static const char *const ext_msg_name[] = { + [0] = "X-RSVD_0", + [PD_EXT_SOURCE_CAP] = "X-SRC_CAP", + [PD_EXT_STATUS] = "X-STATUS", + [PD_EXT_GET_BATTERY_CAP] = "X-GET_BATTERY_CAP", + [PD_EXT_GET_BATTERY_STATUS] = "X-GET_BATTERY_STATUS", + [PD_EXT_BATTERY_CAP] = "X-BATTERY_CAP", + [PD_EXT_GET_MANUFACTURER_INFO] = "X-GET_MFR_INFO", + [PD_EXT_MANUFACTURER_INFO] = "X-MFR_INFO", + [PD_EXT_SECURITY_REQUEST] = "X-SECURITY_REQ", + [PD_EXT_SECURITY_RESPONSE] = "X-SECURITY_RESP", [PD_EXT_FIRMWARE_UPDATE_REQUEST] = "X-FW_UP_REQ", [PD_EXT_FIRMWARE_UPDATE_RESPONSE] = "X-FW_UP_RESP", - [PD_EXT_PPS_STATUS] = "X-PPS_STATUS", - [PD_EXT_COUNTRY_INFO] = "X-COUNTRY_INFO", - [PD_EXT_COUNTRY_CODES] = "X-COUNTRY_CODES", - [PD_EXT_SINK_CAP] = "X-SNK_CAP", - [PD_EXT_CONTROL] = "X-CONTROL", - [PD_EXT_EPR_SOURCE_CAP] = "X-EPR_SRC_CAP", - [PD_EXT_EPR_SINK_CAP] = "X-EPR_SNK_CAP", + [PD_EXT_PPS_STATUS] = "X-PPS_STATUS", + [PD_EXT_COUNTRY_INFO] = "X-COUNTRY_INFO", + [PD_EXT_COUNTRY_CODES] = "X-COUNTRY_CODES", + [PD_EXT_SINK_CAP] = "X-SNK_CAP", + [PD_EXT_CONTROL] = "X-CONTROL", + [PD_EXT_EPR_SOURCE_CAP] = "X-EPR_SRC_CAP", + [PD_EXT_EPR_SINK_CAP] = "X-EPR_SNK_CAP", }; -static const char * const rev_name[] = { +static const char *const rev_name[] = { [PD_REV10] = "1.0", [PD_REV20] = "2.0", [PD_REV30] = "3.0", [3] = "RSVD", }; -static const char * const drole_name[] = { +static const char *const drole_name[] = { [PD_ROLE_UFP] = "UFP", [PD_ROLE_DFP] = "DFP", }; -static const char * const prole_name[] = { +static const char *const prole_name[] = { [PD_ROLE_SINK] = "SNK", [PD_ROLE_SOURCE] = "SRC", }; static void print_header(const char *prefix, uint16_t header) { - int type = PD_HEADER_TYPE(header); + int type = PD_HEADER_TYPE(header); int drole = PD_HEADER_DROLE(header); - int rev = PD_HEADER_REV(header); + int rev = PD_HEADER_REV(header); int prole = PD_HEADER_PROLE(header); - int id = PD_HEADER_ID(header); - int cnt = PD_HEADER_CNT(header); - int ext = PD_HEADER_EXT(header); - const char *name = ext ? ext_msg_name[type] - : cnt - ? data_msg_name[type] - : ctrl_msg_name[type]; - - ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]", - prefix, header, - name, drole_name[drole], rev_name[rev], prole_name[prole], - id, cnt, ext); + int id = PD_HEADER_ID(header); + int cnt = PD_HEADER_CNT(header); + int ext = PD_HEADER_EXT(header); + const char *name = ext ? ext_msg_name[type] : + cnt ? data_msg_name[type] : + ctrl_msg_name[type]; + + ccprints("%s header=0x%x [%s %s %s %s id=%d cnt=%d ext=%d]", prefix, + header, name, drole_name[drole], rev_name[rev], + prole_name[prole], id, cnt, ext); } static bool dead_battery(void) @@ -193,11 +195,9 @@ static bool debug_accessory_indicator_supported(void) return true; } -static int verify_transmit(enum tcpci_msg_type want_tx_type, - int want_tx_retry, +static int verify_transmit(enum tcpci_msg_type want_tx_type, int want_tx_retry, enum pd_ctrl_msg_type want_ctrl_msg, - enum pd_data_msg_type want_data_msg, - int timeout) + enum pd_data_msg_type want_data_msg, int timeout) { uint64_t end_time = get_time().val + timeout; @@ -215,10 +215,10 @@ static int verify_transmit(enum tcpci_msg_type want_tx_type, tcpci_regs[TCPC_REG_TRANSMIT].value); int tx_retry = TCPC_REG_TRANSMIT_RETRY( tcpci_regs[TCPC_REG_TRANSMIT].value); - uint16_t header = UINT16_FROM_BYTE_ARRAY_LE( - tx_buffer, 1); - int pd_type = PD_HEADER_TYPE(header); - int pd_cnt = PD_HEADER_CNT(header); + uint16_t header = + UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1); + int pd_type = PD_HEADER_TYPE(header); + int pd_cnt = PD_HEADER_CNT(header); TEST_EQ(tx_type, want_tx_type, "%d"); if (want_tx_retry >= 0) @@ -246,46 +246,34 @@ int verify_tcpci_transmit(enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, enum pd_data_msg_type data_msg) { - return verify_transmit(tx_type, -1, - ctrl_msg, data_msg, - VERIFY_TIMEOUT); + return verify_transmit(tx_type, -1, ctrl_msg, data_msg, VERIFY_TIMEOUT); } int verify_tcpci_tx_timeout(enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout) + enum pd_data_msg_type data_msg, int timeout) { - return verify_transmit(tx_type, -1, - ctrl_msg, data_msg, - timeout); + return verify_transmit(tx_type, -1, ctrl_msg, data_msg, timeout); } int verify_tcpci_tx_retry_count(enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int retry_count) + enum pd_data_msg_type data_msg, int retry_count) { - return verify_transmit(tx_type, retry_count, - ctrl_msg, data_msg, + return verify_transmit(tx_type, retry_count, ctrl_msg, data_msg, VERIFY_TIMEOUT); } int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type, - enum pd_data_msg_type data_msg, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout) + enum pd_data_msg_type data_msg, uint8_t *data, + int data_bytes, int *msg_len, int timeout) { int rv; if (timeout <= 0) timeout = VERIFY_TIMEOUT; - rv = verify_transmit(tx_type, -1, - 0, data_msg, - timeout); + rv = verify_transmit(tx_type, -1, 0, data_msg, timeout); if (!rv) { TEST_NE(data, NULL, "%p"); TEST_GE(data_bytes, tx_msg_cnt, "%d"); @@ -296,13 +284,9 @@ int verify_tcpci_tx_with_data(enum tcpci_msg_type tx_type, return rv; } -int verify_tcpci_possible_tx(struct possible_tx possible[], - int possible_cnt, - int *found_index, - uint8_t *data, - int data_bytes, - int *msg_len, - int timeout) +int verify_tcpci_possible_tx(struct possible_tx possible[], int possible_cnt, + int *found_index, uint8_t *data, int data_bytes, + int *msg_len, int timeout) { bool assert_on_timeout = true; uint64_t end_time; @@ -328,10 +312,10 @@ int verify_tcpci_possible_tx(struct possible_tx possible[], int i; int tx_type = TCPC_REG_TRANSMIT_TYPE( tcpci_regs[TCPC_REG_TRANSMIT].value); - uint16_t header = UINT16_FROM_BYTE_ARRAY_LE( - tx_buffer, 1); - int pd_type = PD_HEADER_TYPE(header); - int pd_cnt = PD_HEADER_CNT(header); + uint16_t header = + UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1); + int pd_type = PD_HEADER_TYPE(header); + int pd_cnt = PD_HEADER_CNT(header); for (i = 0; i < possible_cnt; ++i) { int want_tx_type = possible[i].tx_type; @@ -352,8 +336,8 @@ int verify_tcpci_possible_tx(struct possible_tx possible[], continue; if (data != NULL) { - TEST_GE(data_bytes, - tx_msg_cnt, "%d"); + TEST_GE(data_bytes, tx_msg_cnt, + "%d"); memcpy(data, tx_buffer, tx_msg_cnt); } @@ -391,9 +375,9 @@ void mock_tcpci_receive(enum tcpci_msg_type sop, uint16_t header, for (i = 4; i < rx_buffer[0]; i += 4) { rx_buffer[i] = *payload & 0xFF; - rx_buffer[i+1] = (*payload >> 8) & 0xFF; - rx_buffer[i+2] = (*payload >> 16) & 0xFF; - rx_buffer[i+3] = (*payload >> 24) & 0xFF; + rx_buffer[i + 1] = (*payload >> 8) & 0xFF; + rx_buffer[i + 2] = (*payload >> 16) & 0xFF; + rx_buffer[i + 3] = (*payload >> 24) & 0xFF; payload++; } @@ -411,11 +395,11 @@ static void tcpci_reset_register_masks(void) /* * Using table 4-1 for default mask values */ - tcpci_regs[TCPC_REG_ALERT_MASK].value = 0x7FFF; - tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value = 0xFF; - tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value = 0xFF; - tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value = 0x01; - tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value = 0x07; + tcpci_regs[TCPC_REG_ALERT_MASK].value = 0x7FFF; + tcpci_regs[TCPC_REG_POWER_STATUS_MASK].value = 0xFF; + tcpci_regs[TCPC_REG_FAULT_STATUS_MASK].value = 0xFF; + tcpci_regs[TCPC_REG_EXT_STATUS_MASK].value = 0x01; + tcpci_regs[TCPC_REG_ALERT_EXTENDED_MASK].value = 0x07; } static void tcpci_reset_register_defaults(void) @@ -427,69 +411,68 @@ static void tcpci_reset_register_defaults(void) tcpci_regs[i].value = 0; /* Type-C Release 1,3 */ - tcpci_regs[TCPC_REG_TC_REV].value = 0x0013; + tcpci_regs[TCPC_REG_TC_REV].value = 0x0013; /* PD Revision 3.0 Version 1.2 */ - tcpci_regs[TCPC_REG_PD_REV].value = 0x3012; + tcpci_regs[TCPC_REG_PD_REV].value = 0x3012; /* PD Interface Revision 2.0, Version 1.1 */ - tcpci_regs[TCPC_REG_PD_INT_REV].value = 0x2011; + tcpci_regs[TCPC_REG_PD_INT_REV].value = 0x2011; tcpci_reset_register_masks(); tcpci_regs[TCPC_REG_CONFIG_STD_OUTPUT].value = - TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N | - TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N; + TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N | + TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N; tcpci_regs[TCPC_REG_POWER_CTRL].value = - TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS | - TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS; + TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS | + TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS; tcpci_regs[TCPC_REG_FAULT_STATUS].value = - TCPC_REG_FAULT_STATUS_ALL_REGS_RESET; + TCPC_REG_FAULT_STATUS_ALL_REGS_RESET; tcpci_regs[TCPC_REG_DEV_CAP_1].value = - TCPC_REG_DEV_CAP_1_SOURCE_VBUS | - TCPC_REG_DEV_CAP_1_SINK_VBUS | - TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP | - TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF; + TCPC_REG_DEV_CAP_1_SOURCE_VBUS | TCPC_REG_DEV_CAP_1_SINK_VBUS | + TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP | + TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF; /* * Using table 4-17 to get the default Role Control and * Message Header Info register values. */ switch (mock_tcpci_get_reg(TCPC_REG_DEV_CAP_1) & - TCPC_REG_DEV_CAP_1_PWRROLE_MASK) { + TCPC_REG_DEV_CAP_1_PWRROLE_MASK) { case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_OR_SNK: case TCPC_REG_DEV_CAP_1_PWRROLE_SNK: case TCPC_REG_DEV_CAP_1_PWRROLE_SNK_ACC: - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; - tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; + tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; break; case TCPC_REG_DEV_CAP_1_PWRROLE_DRP: if (dead_battery()) - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; else if (debug_accessory_indicator_supported()) - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A; else - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F; - tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F; + tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; break; case TCPC_REG_DEV_CAP_1_PWRROLE_SRC: if (!dead_battery()) - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x05; - tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x0D; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x05; + tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x0D; break; case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP_ADPT_CBL: case TCPC_REG_DEV_CAP_1_PWRROLE_SRC_SNK_DRP: if (dead_battery()) - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0A; else if (debug_accessory_indicator_supported()) - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x4A; else - tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F; - tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; + tcpci_regs[TCPC_REG_ROLE_CTRL].value = 0x0F; + tcpci_regs[TCPC_REG_MSG_HDR_INFO].value = 0x04; break; } } @@ -505,7 +488,7 @@ void mock_tcpci_set_reg(int reg_offset, uint16_t value) struct tcpci_reg *reg = tcpci_regs + reg_offset; reg->value = value; - ccprints("TCPCI mock set %s = 0x%x", reg->name, reg->value); + ccprints("TCPCI mock set %s = 0x%x", reg->name, reg->value); } void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask) @@ -514,8 +497,8 @@ void mock_tcpci_set_reg_bits(int reg_offset, uint16_t mask) uint16_t old_value = reg->value; reg->value |= mask; - ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x", - reg->name, mask, old_value, reg->value); + ccprints("TCPCI mock set bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name, + mask, old_value, reg->value); } void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask) @@ -524,8 +507,8 @@ void mock_tcpci_clr_reg_bits(int reg_offset, uint16_t mask) uint16_t old_value = reg->value; reg->value &= ~mask; - ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x", - reg->name, mask, old_value, reg->value); + ccprints("TCPCI mock clr bits %s (mask=0x%x) = 0x%x -> 0x%x", reg->name, + mask, old_value, reg->value); } uint16_t mock_tcpci_get_reg(int reg_offset) @@ -533,9 +516,8 @@ uint16_t mock_tcpci_get_reg(int reg_offset) return tcpci_regs[reg_offset].value; } -int tcpci_i2c_xfer(int port, uint16_t addr_flags, - const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int tcpci_i2c_xfer(int port, uint16_t addr_flags, const uint8_t *out, + int out_size, uint8_t *in, int in_size, int flags) { struct tcpci_reg *reg; @@ -554,10 +536,10 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags, return EC_ERROR_UNKNOWN; } memcpy(in, rx_buffer + rx_pos, in_size); - rx_pos += in_size; + rx_pos += in_size; if (rx_pos == rx_buffer[0] + 1) { - print_header("RX", UINT16_FROM_BYTE_ARRAY_LE( - rx_buffer, 2)); + print_header("RX", + UINT16_FROM_BYTE_ARRAY_LE(rx_buffer, 2)); rx_pos = -1; } return EC_SUCCESS; @@ -576,8 +558,8 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags, tx_pos += out_size; tx_msg_cnt = tx_pos; if (tx_pos > 0 && tx_pos == tx_buffer[0] + 1) { - print_header("TX", UINT16_FROM_BYTE_ARRAY_LE( - tx_buffer, 1)); + print_header("TX", + UINT16_FROM_BYTE_ARRAY_LE(tx_buffer, 1)); tx_pos = -1; tx_retry_cnt = -1; } @@ -638,8 +620,7 @@ int tcpci_i2c_xfer(int port, uint16_t addr_flags, else if (reg->size == 2) value = out[1] + (out[2] << 8); ccprints("%s TCPCI write %s = 0x%x", - task_get_name(task_get_current()), - reg->name, value); + task_get_name(task_get_current()), reg->name, value); if (reg->offset == TCPC_REG_ALERT) reg->value &= ~value; else -- cgit v1.2.1 From 87c7f72c730445f9bae831de500252e6d046b479 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:32 -0600 Subject: board/storo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3f0bf35554a7ba2f567b0760651790723daa1cdf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728958 Reviewed-by: Jeremy Bettis --- board/storo/board.h | 40 ++++++++++++++++------------------------ 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/board/storo/board.h b/board/storo/board.h index 4532d11b4e..d74a7e775c 100644 --- a/board/storo/board.h +++ b/board/storo/board.h @@ -27,9 +27,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -37,19 +38,19 @@ /* LED */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR /* Sensors */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT -#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ #define CONFIG_ACCEL_LIS2DWL #define CONFIG_ACCEL_KX022 -#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ +#define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_ICM42607 #define CONFIG_ACCELGYRO_BMI220 #define CONFIG_I2C_XFER_LARGE_TRANSFER @@ -57,7 +58,7 @@ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ @@ -95,12 +96,10 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ - -#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ - +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ #ifndef __ASSEMBLER__ @@ -113,22 +112,15 @@ enum chg_id { CHARGER_NUM, }; - - /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_TEMP_SENSOR_3, /* ADC15*/ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15*/ ADC_CH_COUNT }; -- cgit v1.2.1 From 43655359910fa7a4421cfb506800cee4aac3c270 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:36 -0600 Subject: board/nightfury/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0af434cd2d2d675f995f09ed49c07144b48b6b17 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728726 Reviewed-by: Jeremy Bettis --- board/nightfury/battery.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/nightfury/battery.c b/board/nightfury/battery.c index a3b251229b..5ef85f06fc 100644 --- a/board/nightfury/battery.c +++ b/board/nightfury/battery.c @@ -111,10 +111,10 @@ enum battery_present variant_battery_present(void) int charger_profile_override(struct charge_state_data *curr) { - if(chipset_in_state(CHIPSET_STATE_ANY_OFF)) + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) return 0; - if(curr->requested_current > CHARGING_CURRENT_45C) + if (curr->requested_current > CHARGING_CURRENT_45C) curr->requested_current = CHARGING_CURRENT_45C; return 0; @@ -124,13 +124,13 @@ int charger_profile_override(struct charge_state_data *curr) #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0) enum ec_status charger_profile_override_get_param(uint32_t param, - uint32_t *value) + uint32_t *value) { - return EC_RES_INVALID_PARAM; + return EC_RES_INVALID_PARAM; } enum ec_status charger_profile_override_set_param(uint32_t param, - uint32_t value) + uint32_t value) { - return EC_RES_INVALID_PARAM; + return EC_RES_INVALID_PARAM; } -- cgit v1.2.1 From 0c7bcf0813eb36c3b132c10d3d995d80741f3fdc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:53 -0600 Subject: board/vell/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I50c56a6b998d8d9e42df3e2288dc449deb7e7843 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729053 Reviewed-by: Jeremy Bettis --- board/vell/keyboard.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/board/vell/keyboard.c b/board/vell/keyboard.c index 7a51f8dd39..33e9bb9c07 100644 --- a/board/vell/keyboard.c +++ b/board/vell/keyboard.c @@ -48,7 +48,6 @@ __override const struct ec_response_keybd_config * board_vivaldi_keybd_config(void) { return &keybd1; - } #ifdef CONFIG_KEYBOARD_FACTORY_TEST @@ -58,13 +57,13 @@ board_vivaldi_keybd_config(void) * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {1, 4}, {1, 3}, {1, 6}, {1, 7}, - {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, - {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3}, - {2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, + { 0, 7 }, { 1, 4 }, { 1, 3 }, { 1, 6 }, { 1, 7 }, + { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, + { 2, 2 }, { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif -- cgit v1.2.1 From d77f639c74eb536d12f4482854ebd4b7e3f11ae7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:27 -0600 Subject: board/brya/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3ee5472402005393d502e05db72420f8e573f5f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728101 Reviewed-by: Jeremy Bettis --- board/brya/fw_config.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/brya/fw_config.h b/board/brya/fw_config.h index 6e4eb3ef58..7f9b472d83 100644 --- a/board/brya/fw_config.h +++ b/board/brya/fw_config.h @@ -27,12 +27,12 @@ enum ec_cfg_keyboard_backlight_type { union brya_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; - uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + enum ec_cfg_usb_db_type usb_db : 4; + uint32_t sd_db : 2; + uint32_t lte_db : 1; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + uint32_t reserved_1 : 21; }; uint32_t raw_value; }; -- cgit v1.2.1 From ab82ad436b0202fd9b6795ef4ae0a2f182e839d0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:34 -0600 Subject: board/kracko/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee538fb8cfa3d53d8d10eea6def5223574a35e27 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728587 Reviewed-by: Jeremy Bettis --- board/kracko/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kracko/cbi_ssfc.c b/board/kracko/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/kracko/cbi_ssfc.c +++ b/board/kracko/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From dfba38b8abc8ca0c83cc772fc209a9b001339cfb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:48 -0600 Subject: common/usb_port_power_dumb.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I37c4f4e39a5022d7901a090e13246623d61f9ee5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729778 Reviewed-by: Jeremy Bettis --- common/usb_port_power_dumb.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/common/usb_port_power_dumb.c b/common/usb_port_power_dumb.c index ea2d4eb668..f1f1881b6e 100644 --- a/common/usb_port_power_dumb.c +++ b/common/usb_port_power_dumb.c @@ -16,7 +16,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) static uint8_t charge_mode[USB_PORT_COUNT]; @@ -75,14 +75,13 @@ usb_port_command_set_mode(struct host_cmd_handler_args *args) { const struct ec_params_usb_charge_set_mode *p = args->params; - if (usb_charge_set_mode(p->usb_port_id, p->mode, - p->inhibit_charge) != EC_SUCCESS) + if (usb_charge_set_mode(p->usb_port_id, p->mode, p->inhibit_charge) != + EC_SUCCESS) return EC_RES_ERROR; return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, - usb_port_command_set_mode, +DECLARE_HOST_COMMAND(EC_CMD_USB_CHARGE_SET_MODE, usb_port_command_set_mode, EC_VER_MASK(0)); /*****************************************************************************/ @@ -108,18 +107,16 @@ static int command_set_mode(int argc, char **argv) /* fallthrough */ case 1: for (i = 0; i < USB_PORT_COUNT; i++) - ccprintf("Port %d: %s\n", - i, charge_mode[i] ? "on" : "off"); + ccprintf("Port %d: %s\n", i, + charge_mode[i] ? "on" : "off"); return EC_SUCCESS; } return EC_ERROR_PARAM_COUNT; } -DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode, - "[ ]", +DECLARE_CONSOLE_COMMAND(usbchargemode, command_set_mode, "[ ]", "Set USB charge mode"); - /*****************************************************************************/ /* Hooks */ @@ -135,10 +132,10 @@ static void usb_port_init(void) const uint8_t *prev; int version, size, i; - prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG, - &version, &size); + prev = (const uint8_t *)system_get_jump_tag(USB_SYSJUMP_TAG, &version, + &size); if (!prev || version != USB_HOOK_VERSION || - size != sizeof(charge_mode)) { + size != sizeof(charge_mode)) { usb_port_all_ports_off(); return; } @@ -162,4 +159,4 @@ static void usb_port_shutdown(void) usb_port_all_ports_off(); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, usb_port_shutdown, HOOK_PRIO_DEFAULT); -#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */ +#endif /* CONFIG_USB_PORT_POWER_DUMB_CUSTOM_HOOK */ -- cgit v1.2.1 From cf2973f18180a49cf8f4934658942fe58db3a87e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:39 -0600 Subject: chip/it83xx/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9c454e32ae8610a2a8a8518d6cbd25d4804f66c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729193 Reviewed-by: Jeremy Bettis --- chip/it83xx/clock.c | 113 ++++++++++++++++++++++++---------------------------- 1 file changed, 52 insertions(+), 61 deletions(-) diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index f548867d12..1040a99af1 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -24,11 +24,11 @@ /* Console output macros. */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) #ifdef CONFIG_LOW_POWER_IDLE #define SLEEP_SET_HTIMER_DELAY_USEC 250 -#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2) +#define SLEEP_FTIMER_SKIP_USEC (HOOK_TICK_INTERVAL * 2) static timestamp_t sleep_mode_t0; static timestamp_t sleep_mode_t1; @@ -40,13 +40,13 @@ static uint32_t ec_sleep; * Fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the heavy sleep mode is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) static int console_in_use_timeout_sec = 5; static timestamp_t console_expire_time; /* clock source is 32.768KHz */ -#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt) * 1000000 / 32768) -#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1) +#define TIMER_32P768K_CNT_TO_US(cnt) ((uint64_t)(cnt)*1000000 / 32768) +#define TIMER_CNT_8M_32P768K(cnt) (((cnt) / (8000000 / 32768)) + 1) #endif /*CONFIG_LOW_POWER_IDLE */ static int freq; @@ -66,10 +66,11 @@ static void clock_module_disable(void) IT83XX_GCTRL_MCCR &= ~BIT(7); clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0); clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB | - CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE | - CGC_OFFSET_SMBF), 0, 0); - clock_disable_peripheral((CGC_OFFSET_SSPI | CGC_OFFSET_PECI | - CGC_OFFSET_USB), 0, 0); + CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | + CGC_OFFSET_SMBE | CGC_OFFSET_SMBF), + 0, 0); + clock_disable_peripheral( + (CGC_OFFSET_SSPI | CGC_OFFSET_PECI | CGC_OFFSET_USB), 0, 0); } enum pll_freq_idx { @@ -78,19 +79,11 @@ enum pll_freq_idx { PLL_96_MHZ = 4, }; -static const uint8_t pll_to_idx[8] = { - 0, - 0, - PLL_24_MHZ, - 0, - PLL_48_MHZ, - 0, - 0, - PLL_96_MHZ -}; +static const uint8_t pll_to_idx[8] = { 0, 0, PLL_24_MHZ, 0, + PLL_48_MHZ, 0, 0, PLL_96_MHZ }; struct clock_pll_t { - int pll_freq; + int pll_freq; uint8_t pll_setting; uint8_t div_fnd; uint8_t div_uart; @@ -114,17 +107,17 @@ const struct clock_pll_t clock_pll_ctrl[] = { * SSPI: 48MHz(24MHz if PLL=24MHz) */ /* PLL:24MHz, MCU:24MHz, Fnd(e-flash):24MHz */ - [PLL_24_MHZ] = {24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2}, + [PLL_24_MHZ] = { 24000000, 2, 0, 0, 0, 0, 0, 2, 0, 0, 0x2 }, #ifdef CONFIG_IT83XX_FLASH_CLOCK_48MHZ /* PLL:48MHz, MCU:48MHz, Fnd:48MHz */ - [PLL_48_MHZ] = {48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5}, + [PLL_48_MHZ] = { 48000000, 4, 0, 1, 0, 1, 0, 6, 1, 0, 0x5 }, /* PLL:96MHz, MCU:96MHz, Fnd:48MHz */ - [PLL_96_MHZ] = {96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb}, + [PLL_96_MHZ] = { 96000000, 7, 1, 3, 1, 3, 1, 6, 3, 1, 0xb }, #else /* PLL:48MHz, MCU:48MHz, Fnd:24MHz */ - [PLL_48_MHZ] = {48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5}, + [PLL_48_MHZ] = { 48000000, 4, 1, 1, 0, 1, 0, 2, 1, 0, 0x5 }, /* PLL:96MHz, MCU:96MHz, Fnd:32MHz */ - [PLL_96_MHZ] = {96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb}, + [PLL_96_MHZ] = { 96000000, 7, 2, 3, 1, 3, 1, 4, 3, 1, 0xb }, #endif }; @@ -196,18 +189,18 @@ void __ram_code clock_pll_changed(void) clock_ec_pll_ctrl(EC_PLL_SLEEP); if (IS_ENABLED(CHIP_CORE_NDS32)) { /* Global interrupt enable */ - asm volatile ("setgie.e"); + asm volatile("setgie.e"); /* EC sleep */ asm("standby wake_grant"); /* Global interrupt disable */ - asm volatile ("setgie.d"); + asm volatile("setgie.d"); } else if (IS_ENABLED(CHIP_CORE_RISCV)) { /* Global interrupt enable */ - asm volatile ("csrsi mstatus, 0x8"); + asm volatile("csrsi mstatus, 0x8"); /* EC sleep */ asm("wfi"); /* Global interrupt disable */ - asm volatile ("csrci mstatus, 0x8"); + asm volatile("csrci mstatus, 0x8"); } /* New FND clock frequency */ IT83XX_ECPM_SCDCR0 = (pll_div_fnd << 4); @@ -220,18 +213,18 @@ static void clock_set_pll(enum pll_freq_idx idx) { int pll; - pll_div_fnd = clock_pll_ctrl[idx].div_fnd; - pll_div_ec = clock_pll_ctrl[idx].div_ec; + pll_div_fnd = clock_pll_ctrl[idx].div_fnd; + pll_div_ec = clock_pll_ctrl[idx].div_ec; pll_div_jtag = clock_pll_ctrl[idx].div_jtag; - pll_setting = clock_pll_ctrl[idx].pll_setting; + pll_setting = clock_pll_ctrl[idx].pll_setting; /* Update PLL settings or not */ if (((IT83XX_ECPM_PLLFREQR & 0xf) != pll_setting) || - ((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) || - ((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) { + ((IT83XX_ECPM_SCDCR0 & 0xf0) != (pll_div_fnd << 4)) || + ((IT83XX_ECPM_SCDCR3 & 0xf) != pll_div_ec)) { /* Enable hw timer to wakeup EC from the sleep mode */ - ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, - 1, 1, 5, 1, 0); + ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 1, 5, + 1, 0); task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq); #ifdef CONFIG_HOST_INTERFACE_ESPI /* @@ -264,13 +257,13 @@ static void clock_set_pll(enum pll_freq_idx idx) pll = pll_to_idx[IT83XX_ECPM_PLLFREQR & 0xf]; /* USB and UART */ IT83XX_ECPM_SCDCR1 = (clock_pll_ctrl[pll].div_usb << 4) | - clock_pll_ctrl[pll].div_uart; + clock_pll_ctrl[pll].div_uart; /* SSPI and SMB */ IT83XX_ECPM_SCDCR2 = (clock_pll_ctrl[pll].div_sspi << 4) | - clock_pll_ctrl[pll].div_smb; + clock_pll_ctrl[pll].div_smb; /* USBPD and PWM */ IT83XX_ECPM_SCDCR4 = (clock_pll_ctrl[pll].div_usbpd << 4) | - clock_pll_ctrl[pll].div_pwm; + clock_pll_ctrl[pll].div_pwm; /* Current PLL frequency */ freq = clock_pll_ctrl[pll].pll_freq; } @@ -284,8 +277,7 @@ void clock_init(void) /* Interrupt Vector Table Base Address, in 64k Byte unit */ IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF; -#if (PLL_CLOCK == 24000000) || \ - (PLL_CLOCK == 48000000) || \ +#if (PLL_CLOCK == 24000000) || (PLL_CLOCK == 48000000) || \ (PLL_CLOCK == 96000000) /* Set PLL frequency */ clock_set_pll(PLL_CLOCK / 24000000); @@ -345,8 +337,8 @@ int clock_get_freq(void) */ void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) { - volatile uint8_t *reg = (volatile uint8_t *) - (IT83XX_ECPM_BASE + (offset >> 8)); + volatile uint8_t *reg = + (volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8)); uint8_t reg_mask = offset & 0xff; /* @@ -368,8 +360,8 @@ void clock_enable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) */ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) { - volatile uint8_t *reg = (volatile uint8_t *) - (IT83XX_ECPM_BASE + (offset >> 8)); + volatile uint8_t *reg = + (volatile uint8_t *)(IT83XX_ECPM_BASE + (offset >> 8)); uint8_t reg_mask = offset & 0xff; uint8_t tmp_mask = 0; @@ -388,7 +380,7 @@ void clock_refresh_console_in_use(void) } static void clock_event_timer_clock_change(enum ext_timer_clock_source clock, - uint32_t count) + uint32_t count) { IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0); IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock; @@ -420,19 +412,19 @@ static int clock_allow_low_power_idle(void) /* If timer interrupt status is set, don't go to sleep mode. */ if (*et_ctrl_regs[EVENT_EXT_TIMER].isr & - et_ctrl_regs[EVENT_EXT_TIMER].mask) + et_ctrl_regs[EVENT_EXT_TIMER].mask) return 0; - /* - * If timer is less than 250us to expire, then we don't go to sleep - * mode. - */ + /* + * If timer is less than 250us to expire, then we don't go to + * sleep mode. + */ #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES if (EVENT_TIMER_COUNT_TO_US(ext_observation_reg_read(EVENT_EXT_TIMER)) < #else if (EVENT_TIMER_COUNT_TO_US(IT83XX_ETWD_ETXCNTOR(EVENT_EXT_TIMER)) < #endif - SLEEP_SET_HTIMER_DELAY_USEC) + SLEEP_SET_HTIMER_DELAY_USEC) return 0; /* @@ -442,7 +434,7 @@ static int clock_allow_low_power_idle(void) */ sleep_mode_t0 = get_time(); if ((sleep_mode_t0.le.lo > (0xffffffff - SLEEP_FTIMER_SKIP_USEC)) || - (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC)) + (sleep_mode_t0.le.lo < SLEEP_FTIMER_SKIP_USEC)) return 0; /* If we are waked up by console, then keep awake at least 5s. */ @@ -541,7 +533,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) /* EC sleep */ ec_sleep = 1; #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOST_INTERFACE_ESPI) + defined(CONFIG_HOST_INTERFACE_ESPI) /* Disable eSPI pad. */ espi_enable_pad(0); #endif @@ -567,7 +559,7 @@ void clock_sleep_mode_wakeup_isr(void) /* trigger a reboot if wake up EC from sleep mode (system hibernate) */ if (clock_ec_wake_from_sleep()) { #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ -defined(CONFIG_HOST_INTERFACE_ESPI) + defined(CONFIG_HOST_INTERFACE_ESPI) /* * Enable eSPI pad. * We will not need to enable eSPI pad here if Dx is able to @@ -587,7 +579,7 @@ defined(CONFIG_HOST_INTERFACE_ESPI) clock_ec_pll_ctrl(EC_PLL_DOZE); /* update free running timer */ c = LOW_POWER_TIMER_MASK - - IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER); + IT83XX_ETWD_ETXCNTOR(LOW_POWER_EXT_TIMER); st_us = TIMER_32P768K_CNT_TO_US(c); sleep_mode_t1.val = sleep_mode_t0.val + st_us; __hw_clock_source_set(sleep_mode_t1.le.lo); @@ -613,8 +605,8 @@ void __keep __idle_init(void) { console_expire_time.val = get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; /* init hw timer and clock source is 32.768 KHz */ - ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0, - 0xffffffff, 1, 1); + ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ, 1, 0, 0xffffffff, + 1, 1); /* * Print when the idle task starts. This is the lowest priority task, @@ -697,12 +689,11 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Total Time spent in sleep(sec): %.6lld(s)\n", - total_idle_sleep_time_us); + total_idle_sleep_time_us); ccprintf("Total time on: %.6llds\n\n", ts.val); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_CMD_IDLE_STATS */ -- cgit v1.2.1 From 77a0e410755dca9d1359ffac6ded68b487245154 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:31:38 -0600 Subject: board/drawcia/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I27e48e62e115de5845a530e18b21cd4197846268 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728255 Reviewed-by: Jeremy Bettis --- board/drawcia/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/drawcia/usb_pd_policy.c b/board/drawcia/usb_pd_policy.c index 7046e25d6c..042adc0a86 100644 --- a/board/drawcia/usb_pd_policy.c +++ b/board/drawcia/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From b939593b3c7c21944c9c627a63bac01b2b592189 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:11 -0600 Subject: driver/accel_lis2ds.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iad624702c78884348f1fe8b51f5daa6fe977194e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729910 Reviewed-by: Jeremy Bettis --- driver/accel_lis2ds.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/driver/accel_lis2ds.c b/driver/accel_lis2ds.c index 0743b428eb..29211488c0 100644 --- a/driver/accel_lis2ds.c +++ b/driver/accel_lis2ds.c @@ -28,10 +28,10 @@ #define ACCEL_LIS2DS_INT_ENABLE #endif -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) STATIC_IF(ACCEL_LIS2DS_INT_ENABLE) - volatile uint32_t last_interrupt_timestamp; +volatile uint32_t last_interrupt_timestamp; /** * lis2ds_enable_fifo - Enable/Disable FIFO in LIS2DS12 @@ -49,8 +49,8 @@ static int lis2ds_config_interrupt(const struct motion_sensor_t *s) int ret = EC_SUCCESS; /* Interrupt trigger level of power-on-reset is HIGH */ - RETURN_ERROR(st_write_data_with_mask(s, LIS2DS_H_ACTIVE_ADDR, - LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT)); + RETURN_ERROR(st_write_data_with_mask( + s, LIS2DS_H_ACTIVE_ADDR, LIS2DS_H_ACTIVE_MASK, LIS2DS_EN_BIT)); /* * Configure FIFO threshold to 1 sample: interrupt on watermark @@ -60,13 +60,13 @@ static int lis2ds_config_interrupt(const struct motion_sensor_t *s) * configured threshold. */ ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LIS2DS_FIFO_THS_ADDR, 1); + LIS2DS_FIFO_THS_ADDR, 1); if (ret != EC_SUCCESS) return ret; /* Enable interrupt on FIFO watermark and route to int1. */ - ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR, - LIS2DS_INT1_FTH, LIS2DS_EN_BIT); + ret = st_write_data_with_mask(s, LIS2DS_CTRL4_ADDR, LIS2DS_INT1_FTH, + LIS2DS_EN_BIT); return ret; } @@ -137,20 +137,17 @@ void lis2ds_interrupt(enum gpio_signal signal) /** * lis2ds_irq_handler - bottom half of the interrupt stack. */ -static int lis2ds_irq_handler(struct motion_sensor_t *s, - uint32_t *event) +static int lis2ds_irq_handler(struct motion_sensor_t *s, uint32_t *event) { int ret = EC_SUCCESS; uint16_t nsamples = 0; uint8_t fifo_src_samples[2]; - if ((s->type != MOTIONSENSE_TYPE_ACCEL) || (!(*event & CONFIG_ACCEL_LIS2DS_INT_EVENT))) return EC_ERROR_NOT_HANDLED; - ret = st_raw_read_n_noinc(s->port, - s->i2c_spi_addr_flags, + ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, LIS2DS_FIFO_SRC_ADDR, (uint8_t *)fifo_src_samples, sizeof(fifo_src_samples)); @@ -169,7 +166,7 @@ static int lis2ds_irq_handler(struct motion_sensor_t *s, return lis2ds_load_fifo(s, nsamples, last_interrupt_timestamp); } -#endif /* ACCEL_LIS2DS_INT_ENABLE */ +#endif /* ACCEL_LIS2DS_INT_ENABLE */ /** * set_range - set full scale range @@ -257,8 +254,8 @@ static int is_data_ready(const struct motion_sensor_t *s, int *ready) { int ret, tmp; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2DS_STATUS_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_STATUS_REG, + &tmp); if (ret != EC_SUCCESS) { CPRINTS("%s: type:0x%X RD XYZ Error %d", s->name, s->type, ret); return ret; @@ -309,8 +306,8 @@ static int init(struct motion_sensor_t *s) int ret = 0, tmp; struct stprivate_data *data = s->drv_data; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LIS2DS_WHO_AM_I_REG, &tmp); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LIS2DS_WHO_AM_I_REG, + &tmp); if (ret != EC_SUCCESS) return EC_ERROR_UNKNOWN; -- cgit v1.2.1 From 140557db3fa25363b203b2aa72d40d8eed1ca54b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:51 -0600 Subject: baseboard/asurada/regulator.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b12932140a830ad96ba39b7cefa099442d8ad04 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727853 Reviewed-by: Jeremy Bettis --- baseboard/asurada/regulator.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/baseboard/asurada/regulator.c b/baseboard/asurada/regulator.c index 35670bda82..dae6ba13ea 100644 --- a/baseboard/asurada/regulator.c +++ b/baseboard/asurada/regulator.c @@ -7,13 +7,12 @@ #include "bc12/mt6360_public.h" /* SD Card */ -int board_regulator_get_info(uint32_t index, char *name, - uint16_t *num_voltages, uint16_t *voltages_mv) +int board_regulator_get_info(uint32_t index, char *name, uint16_t *num_voltages, + uint16_t *voltages_mv) { enum mt6360_regulator_id id = index; - return mt6360_regulator_get_info(id, name, num_voltages, - voltages_mv); + return mt6360_regulator_get_info(id, name, num_voltages, voltages_mv); } int board_regulator_enable(uint32_t index, uint8_t enable) -- cgit v1.2.1 From ca6d35c577ceb3f87d9b43fc41d82d37e41f7986 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:00:13 -0600 Subject: board/poppy/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia9ed3e9798793f3cb528eabd0e07529921c98246 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728842 Reviewed-by: Jeremy Bettis --- board/poppy/led.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/board/poppy/led.c b/board/poppy/led.c index 0c2d7f1832..a2f31a7a74 100644 --- a/board/poppy/led.c +++ b/board/poppy/led.c @@ -31,17 +31,18 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void side_led_set_color(int port, enum led_color color) { int yellow_c0 = (system_get_board_version() >= 5) ? - GPIO_LED_YELLOW_C0 : GPIO_LED_YELLOW_C0_OLD; + GPIO_LED_YELLOW_C0 : + GPIO_LED_YELLOW_C0_OLD; gpio_set_level(port ? GPIO_LED_YELLOW_C1 : yellow_c0, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(port ? GPIO_LED_WHITE_C1 : GPIO_LED_WHITE_C0, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -104,8 +105,9 @@ static void board_led_set_battery(void) case PWR_STATE_DISCHARGE: if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) { if (charge_get_percent() <= 10) - side_led_set_color(0, - (battery_ticks & 0x4) ? LED_WHITE : LED_OFF); + side_led_set_color(0, (battery_ticks & 0x4) ? + LED_WHITE : + LED_OFF); else side_led_set_color(0, LED_OFF); } @@ -114,16 +116,16 @@ static void board_led_set_battery(void) side_led_set_color(1, LED_OFF); break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - LED_WHITE : LED_OFF); + set_active_port_color((battery_ticks & 0x2) ? LED_WHITE : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) - set_active_port_color((battery_ticks & 0x4) ? - LED_AMBER : LED_OFF); + set_active_port_color( + (battery_ticks & 0x4) ? LED_AMBER : LED_OFF); else set_active_port_color(LED_WHITE); break; -- cgit v1.2.1 From ae500dc34e79025227966c38630ecb855106d228 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:04 -0600 Subject: driver/usb_mux/amd_fp6.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia89059508d86fd7161972d351f2c26cd131e7222 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730153 Reviewed-by: Jeremy Bettis --- driver/usb_mux/amd_fp6.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/driver/usb_mux/amd_fp6.c b/driver/usb_mux/amd_fp6.c index 4f31fae186..0c0d52e599 100644 --- a/driver/usb_mux/amd_fp6.c +++ b/driver/usb_mux/amd_fp6.c @@ -15,8 +15,8 @@ #include "timer.h" #include "usb_mux.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* * The recommendation from "3.3.2 Command Timeout" is 250ms, @@ -50,8 +50,8 @@ static int amd_fp6_mux_port0_read(const struct usb_mux *me, uint8_t *val) * payload[1]: Port 0 Control/Status * payload[2]: Port 1 Control/Status (unused on FP6) */ - mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET) - & AMD_FP6_MUX_PD_STATUS_READY); + mux_ready = !!((payload[0] >> AMD_FP6_MUX_PD_STATUS_OFFSET) & + AMD_FP6_MUX_PD_STATUS_READY); if (!mux_ready) return EC_ERROR_BUSY; @@ -80,7 +80,6 @@ static int amd_fp6_mux_port0_write(const struct usb_mux *me, uint8_t write_val) */ start = get_time(); while (time_since32(start) < WRITE_CMD_TIMEOUT_MS * MSEC) { - RETURN_ERROR(amd_fp6_mux_port0_read(me, &read_val)); port_status = read_val >> AMD_FP6_MUX_PORT_STATUS_OFFSET; @@ -134,7 +133,6 @@ static void amd_fp6_set_mux_retry(void) CMD_RETRY_INTERVAL_MS * MSEC); } - static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { @@ -170,8 +168,8 @@ static int amd_fp6_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* Mux is not powered in Z1 */ if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; saved_mux_state[me->usb_port].write_pending = true; amd_fp6_set_mux_retry(); -- cgit v1.2.1 From 4aa8c309d58c496850c5bc780dae68effd0f6ada Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:16 -0600 Subject: board/dingdong/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibb172bd1c8a951a6ea2692116a242d9129cb253d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728205 Reviewed-by: Jeremy Bettis --- board/dingdong/usb_pd_pdo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/dingdong/usb_pd_pdo.c b/board/dingdong/usb_pd_pdo.c index 990c2de5ab..6caee22d29 100644 --- a/board/dingdong/usb_pd_pdo.c +++ b/board/dingdong/usb_pd_pdo.c @@ -15,6 +15,6 @@ const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); /* Fake PDOs : we just want our pre-defined voltages */ const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); -- cgit v1.2.1 From e1aa8221dee182cea98621b1ac7eed8cf6b8b75b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:15 -0600 Subject: board/chocodile_vpdmcu/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I80281edb0440b79a4952d9645a7a890ece7477ea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728122 Reviewed-by: Jeremy Bettis --- board/chocodile_vpdmcu/board.h | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/board/chocodile_vpdmcu/board.h b/board/chocodile_vpdmcu/board.h index 552f00aa09..dc39da47ca 100644 --- a/board/chocodile_vpdmcu/board.h +++ b/board/chocodile_vpdmcu/board.h @@ -34,7 +34,7 @@ #define CPU_CLOCK 48000000 /* the UART console is on USART1 (PA9/PA10) */ -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 /* Optional features */ @@ -43,23 +43,23 @@ #undef CONFIG_CMD_PD #undef CONFIG_USBC_VCONN #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_ADC_SAMPLE_TIME STM32_ADC_SMPR_41_5_CY #define CONFIG_BOARD_PRE_INIT #define CONFIG_COMMON_GPIO_SHORTNAMES -#undef CONFIG_DEBUG_ASSERT +#undef CONFIG_DEBUG_ASSERT #define CONFIG_FORCE_CONSOLE_RESUME #define CONFIG_HIBERNATE -#undef CONFIG_HOSTCMD_EVENTS +#undef CONFIG_HOSTCMD_EVENTS #define CONFIG_HW_CRC -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LOW_POWER_IDLE #define CONFIG_LTO #define CONFIG_STM_HWTIMER32 -#undef CONFIG_TASK_PROFILING -#undef CONFIG_UART_TX_BUF_SIZE -#undef CONFIG_UART_TX_DMA -#undef CONFIG_UART_RX_DMA +#undef CONFIG_TASK_PROFILING +#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_DMA +#undef CONFIG_UART_RX_DMA #define CONFIG_UART_TX_BUF_SIZE 128 #define CONFIG_USB_PD_PORT_MAX_COUNT 1 #define CONFIG_USB_PD_TCPC @@ -74,7 +74,7 @@ #define CONFIG_USB_PD_INTERNAL_COMP #define CONFIG_VBOOT_HASH #define CONFIG_WATCHDOG -#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_WATCHDOG_HELP #define CONFIG_USB_PID 0x5036 #define VPD_HW_VERSION 0x0001 @@ -92,10 +92,10 @@ /* GND impedance in milliohms */ #define VPD_GND_IMPEDANCE 33 -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * TODO(crosbug.com/p/50519): Remove CONFIG_SYSTEM_UNLOCKED prior to building * MP FW. @@ -103,19 +103,19 @@ #define CONFIG_SYSTEM_UNLOCKED #ifdef HAS_TASK_CONSOLE -#undef CONFIG_CONSOLE_HISTORY +#undef CONFIG_CONSOLE_HISTORY #define CONFIG_CONSOLE_HISTORY 2 #else -#undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CONSOLE_CMDHELP #define CONFIG_DEBUG_PRINTF #define UARTN CONFIG_UART_CONSOLE #define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE) #endif /* HAS_TASK_CONSOLE */ /* Use PSTATE embedded in the RO image, not in its own erase block */ -#undef CONFIG_FLASH_PSTATE_BANK -#undef CONFIG_FW_PSTATE_SIZE +#undef CONFIG_FLASH_PSTATE_BANK +#undef CONFIG_FW_PSTATE_SIZE #define CONFIG_FW_PSTATE_SIZE 0 /* Include math_util for bitmask_uint64 used in pd_timers */ @@ -125,7 +125,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" @@ -146,8 +146,8 @@ enum adc_channel { }; /* 1.5A Rp */ -#define PD_SRC_VNC PD_SRC_1_5_VNC_MV -#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV +#define PD_SRC_VNC PD_SRC_1_5_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 4701916d3fe5b9aebfadfc8e3109cc0b7eee5f9d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:07 -0600 Subject: driver/usb_mux/virtual.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic859916383a8dd49fd23116e064de162fe2a0874 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730174 Reviewed-by: Jeremy Bettis --- driver/usb_mux/virtual.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/driver/usb_mux/virtual.c b/driver/usb_mux/virtual.c index 23987fd676..96d06c051d 100644 --- a/driver/usb_mux/virtual.c +++ b/driver/usb_mux/virtual.c @@ -18,11 +18,11 @@ * configures the HPD mux state. Both states are independent of each other * may differ when the PD role changes when in dock mode. */ -#define USB_PD_MUX_HPD_STATE (USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ) -#define USB_PD_MUX_USB_DP_STATE (USB_PD_MUX_USB_ENABLED | \ - USB_PD_MUX_DP_ENABLED | USB_PD_MUX_POLARITY_INVERTED | \ - USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ - USB_PD_MUX_USB4_ENABLED) +#define USB_PD_MUX_HPD_STATE (USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ) +#define USB_PD_MUX_USB_DP_STATE \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_POLARITY_INVERTED | USB_PD_MUX_SAFE_MODE | \ + USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED) static mux_state_t virtual_mux_state[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -82,7 +82,8 @@ static int virtual_set_mux(const struct usb_mux *me, mux_state_t mux_state, * is still active. Otherwise, don't preserve HPD state. */ if (mux_state & USB_PD_MUX_DP_ENABLED) - new_mux_state = (mux_state & ~USB_PD_MUX_HPD_STATE) | + new_mux_state = + (mux_state & ~USB_PD_MUX_HPD_STATE) | (virtual_mux_state[port] & USB_PD_MUX_HPD_STATE); else new_mux_state = mux_state; @@ -112,8 +113,8 @@ void virtual_hpd_update(const struct usb_mux *me, mux_state_t mux_state, int port = me->usb_port; /* Current HPD related mux status + existing USB & DP mux status */ - mux_state_t new_mux_state = mux_state | - (virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE); + mux_state_t new_mux_state = + mux_state | (virtual_mux_state[port] & USB_PD_MUX_USB_DP_STATE); virtual_mux_update_state(port, new_mux_state, ack_required); } -- cgit v1.2.1 From c5d721e4be240cdaf97e7e92ec6671f3873a3190 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:28 -0600 Subject: board/dirinboz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4edf2366b63fac73f35ac6d1bea9c0209329016a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728206 Reviewed-by: Jeremy Bettis --- board/dirinboz/board.h | 79 ++++++++++++++++++-------------------------------- 1 file changed, 29 insertions(+), 50 deletions(-) diff --git a/board/dirinboz/board.h b/board/dirinboz/board.h index 67e083b51f..45bd93790e 100644 --- a/board/dirinboz/board.h +++ b/board/dirinboz/board.h @@ -20,7 +20,7 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PORT_ENABLE_DYNAMIC -#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000 #define CONFIG_CHARGER_PROFILE_OVERRIDE @@ -35,39 +35,35 @@ #undef CONFIG_LED_ONOFF_STATES /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ /* This I2C moved. Temporarily detect and support the V0 HW. */ extern int I2C_PORT_BATTERY; -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_SIMPLO_COS, @@ -79,20 +75,11 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; -enum ioex_port { - IOEX_C0_NCT3807 = 0, - IOEX_C1_NCT3807, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT }; -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB3_C0_DP2_HPD \ - : GPIO_DP1_HPD) +#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD) enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -101,17 +88,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration -- cgit v1.2.1 From 032c87d2c6697e99f8663e68f9ae1f8821353a3d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:15 -0600 Subject: common/led_pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2ccbecdac0794e32345d2f346322c533c64b4cff Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729668 Reviewed-by: Jeremy Bettis --- common/led_pwm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/common/led_pwm.c b/common/led_pwm.c index 05fe21e82b..e8f6c2bdf3 100644 --- a/common/led_pwm.c +++ b/common/led_pwm.c @@ -262,7 +262,7 @@ static void update_leds(void) } DECLARE_HOOK(HOOK_TICK, update_leds, HOOK_PRIO_DEFAULT); -#endif/* CONFIG_LED_PWM_TASK_DISABLED */ +#endif /* CONFIG_LED_PWM_TASK_DISABLED */ #ifdef CONFIG_CMD_LEDTEST static int command_ledtest(int argc, char **argv) @@ -280,9 +280,8 @@ static int command_ledtest(int argc, char **argv) led_id = supported_led_ids[pwm_led_id]; if (argc == 2) { - ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n", - pwm_led_id, led_id, - led_auto_control_is_enabled(led_id) != 0); + ccprintf("PWM LED %d: led_id=%d, auto_control=%d\n", pwm_led_id, + led_id, led_auto_control_is_enabled(led_id) != 0); return EC_SUCCESS; } if (!parse_bool(argv[2], &enable)) -- cgit v1.2.1 From 14dd71550404844d5811f20513ee11314aca535d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:19 -0600 Subject: chip/ish/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I19e3c724137ec38cd2abc65e840c1c692a88ffe7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729156 Reviewed-by: Jeremy Bettis --- chip/ish/flash.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chip/ish/flash.c b/chip/ish/flash.c index 2a1b9c0793..384a813c56 100644 --- a/chip/ish/flash.c +++ b/chip/ish/flash.c @@ -6,7 +6,6 @@ #include "common.h" #include "flash.h" - /** * Initialize the module. * -- cgit v1.2.1 From 7c86f58dbe3f3b7bc678c828a5ab6a9d1c194d39 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:35 -0600 Subject: board/npcx_evb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia19a846f7d268aa502725e465989ce35fb3dd07f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728769 Reviewed-by: Jeremy Bettis --- board/npcx_evb/board.c | 81 +++++++++++++++++++++++--------------------------- 1 file changed, 37 insertions(+), 44 deletions(-) diff --git a/board/npcx_evb/board.c b/board/npcx_evb/board.c index ee448bbbd2..b38dafc02d 100644 --- a/board/npcx_evb/board.c +++ b/board/npcx_evb/board.c @@ -35,16 +35,19 @@ /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_CH_0] = {"ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_1] = {"ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_CH_2] = {"ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_CH_0] = { "ADC0", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_1] = { "ADC1", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, + [ADC_CH_2] = { "ADC2", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, + 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000}, + [PWM_CH_FAN] = { 0, PWM_CONFIG_OPEN_DRAIN, 25000 }, #if (CONFIG_FANS == 2) [PWM_CH_FAN2] = { 2, 0, 25000 }, #endif @@ -56,14 +59,14 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = 0, /* Use MFT id to control fan */ + .ch = 0, /* Use MFT id to control fan */ .pgood_gpio = GPIO_PGOOD_FAN, .enable_gpio = -1, }; const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = 1, /* Use MFT id to control fan */ + .ch = 1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -91,9 +94,9 @@ BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT); /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, #if (CONFIG_FANS == 2) - [MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2}, + [MFT_CH_1] = { NPCX_MFT_MODULE_2, TCKC_LFCLK, PWM_CH_FAN2 }, #endif }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); @@ -101,48 +104,38 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master0-0", - .port = NPCX_I2C_PORT0_0, - .kbps = 100, - .scl = GPIO_I2C0_SCL0, - .sda = GPIO_I2C0_SDA0 - }, - { - .name = "master0-1", - .port = NPCX_I2C_PORT0_1, - .kbps = 100, - .scl = GPIO_I2C0_SCL1, - .sda = GPIO_I2C0_SDA1 - }, - { - .name = "master1", - .port = NPCX_I2C_PORT1, - .kbps = 100, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "master2", - .port = NPCX_I2C_PORT2, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "master3", - .port = NPCX_I2C_PORT3, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, + { .name = "master0-0", + .port = NPCX_I2C_PORT0_0, + .kbps = 100, + .scl = GPIO_I2C0_SCL0, + .sda = GPIO_I2C0_SDA0 }, + { .name = "master0-1", + .port = NPCX_I2C_PORT0_1, + .kbps = 100, + .scl = GPIO_I2C0_SCL1, + .sda = GPIO_I2C0_SDA1 }, + { .name = "master1", + .port = NPCX_I2C_PORT1, + .kbps = 100, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "master2", + .port = NPCX_I2C_PORT2, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "master3", + .port = NPCX_I2C_PORT3, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /******************************************************************************/ /* SPI devices */ const struct spi_device_t spi_devices[] = { - { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L}, + { CONFIG_SPI_FLASH_PORT, 0, GPIO_SPI_CS_L }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); -- cgit v1.2.1 From 3b0a979f4cbda340fa582fa3e821182c79ce401f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:20 -0600 Subject: zephyr/emul/emul_pi3usb9201.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03b744dc2954361ad4a00755e5c7bf8799ccad23 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730695 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_pi3usb9201.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/zephyr/emul/emul_pi3usb9201.c b/zephyr/emul/emul_pi3usb9201.c index 9115a84515..ee33152b84 100644 --- a/zephyr/emul/emul_pi3usb9201.c +++ b/zephyr/emul/emul_pi3usb9201.c @@ -72,10 +72,10 @@ static void pi3usb9201_emul_reset(struct i2c_emul *emul) data = CONTAINER_OF(emul, struct pi3usb9201_emul_data, emul); - data->reg[PI3USB9201_REG_CTRL_1] = 0; - data->reg[PI3USB9201_REG_CTRL_2] = 0; + data->reg[PI3USB9201_REG_CTRL_1] = 0; + data->reg[PI3USB9201_REG_CTRL_2] = 0; data->reg[PI3USB9201_REG_CLIENT_STS] = 0; - data->reg[PI3USB9201_REG_HOST_STS] = 0; + data->reg[PI3USB9201_REG_HOST_STS] = 0; } /** @@ -109,18 +109,18 @@ static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs, i2c_dump_msgs("emul", msgs, num_msgs, addr); if (num_msgs == 1) { - if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) - && (msgs[0].len == 2))) { + if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) && + (msgs[0].len == 2))) { LOG_ERR("Unexpected write msgs"); return -EIO; } return pi3usb9201_emul_set_reg(emul, msgs[0].buf[0], msgs[0].buf[1]); } else if (num_msgs == 2) { - if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) - && (msgs[0].len == 1) - && ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) - && (msgs[1].len == 1))) { + if (!(((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) && + (msgs[0].len == 1) && + ((msgs[1].flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) && + (msgs[1].len == 1))) { LOG_ERR("Unexpected read msgs"); return -EIO; } @@ -130,7 +130,6 @@ static int pi3usb9201_emul_transfer(struct i2c_emul *emul, struct i2c_msg *msgs, LOG_ERR("Unexpected num_msgs"); return -EIO; } - } /* Device instantiation */ @@ -151,7 +150,7 @@ static struct i2c_emul_api pi3usb9201_emul_api = { * @return 0 indicating success (always) */ static int pi3usb9201_emul_init(const struct emul *emul, - const struct device *parent) + const struct device *parent) { const struct pi3usb9201_emul_cfg *cfg = emul->cfg; struct pi3usb9201_emul_data *data = cfg->data; @@ -181,13 +180,14 @@ static int pi3usb9201_emul_init(const struct emul *emul, DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL) -#define PI3USB9201_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &pi3usb9201_emul_data_##n.emul; +#define PI3USB9201_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &pi3usb9201_emul_data_##n.emul; struct i2c_emul *pi3usb9201_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(PI3USB9201_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From 6f389d6f56ad469e4a36c4ff65e8b664cc403bfb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:31 -0600 Subject: board/beetley/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I484b2362fc471d265e3ddc2c6ec0851bb10177ba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728030 Reviewed-by: Jeremy Bettis --- board/beetley/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/beetley/cbi_ssfc.h b/board/beetley/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/beetley/cbi_ssfc.h +++ b/board/beetley/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 18e5eaec6193b477268d0a8a32ff6c2bfd4ec5c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:41 -0600 Subject: board/casta/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib140f1ce9ef06d48a8c520b8ae416d3f76763c18 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728140 Reviewed-by: Jeremy Bettis --- board/casta/battery.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/casta/battery.c b/board/casta/battery.c index 0ced18e734..246a05c43d 100644 --- a/board/casta/battery.c +++ b/board/casta/battery.c @@ -12,8 +12,8 @@ #include "common.h" #include "util.h" -#define CHARGING_VOLTAGE_MV_SAFE 8400 -#define CHARGING_CURRENT_MA_SAFE 1500 +#define CHARGING_VOLTAGE_MV_SAFE 8400 +#define CHARGING_CURRENT_MA_SAFE 1500 /* * Battery info for all casta battery types. Note that the fields @@ -95,12 +95,12 @@ int charger_profile_override(struct charge_state_data *curr) TEMP_OUT_OF_RANGE = TEMP_ZONE_COUNT } temp_zone; - /* - * Precharge must be executed when communication is failed on + /* + * Precharge must be executed when communication is failed on * dead battery. - */ - if(!(curr->batt.flags & BATT_FLAG_RESPONSIVE)) - return 0; + */ + if (!(curr->batt.flags & BATT_FLAG_RESPONSIVE)) + return 0; current = curr->requested_current; voltage = curr->requested_voltage; @@ -146,7 +146,7 @@ int charger_profile_override(struct charge_state_data *curr) break; } - if(voltage > batt_info->voltage_max) + if (voltage > batt_info->voltage_max) voltage = batt_info->voltage_max; curr->requested_voltage = MIN(curr->requested_voltage, voltage); -- cgit v1.2.1 From adc0d160aea5aa245bd6f90ce1e47b5c84b8a4ca Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:46 -0600 Subject: chip/stm32/i2c-stm32g4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I22003d732398279254b05d42cbc2a5357955ef65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729517 Reviewed-by: Jeremy Bettis --- chip/stm32/i2c-stm32g4.c | 55 ++++++++++++++++++++++++------------------------ 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/chip/stm32/i2c-stm32g4.c b/chip/stm32/i2c-stm32g4.c index fbb13e3453..4da300f45c 100644 --- a/chip/stm32/i2c-stm32g4.c +++ b/chip/stm32/i2c-stm32g4.c @@ -20,12 +20,12 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_I2C, outstr) -#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args) +#define CPRINTS(format, args...) cprints(CC_I2C, format, ##args) #define I2C_ERROR_FAILED_START EC_ERROR_INTERNAL_FIRST /* Transmit timeout in microseconds */ -#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) +#define I2C_TX_TIMEOUT_MASTER (10 * MSEC) enum i2c_freq_khz { freq_100 = 100, @@ -44,8 +44,8 @@ struct i2c_timing { /* timing register values for supported input clks / i2c clk rates */ static const uint32_t busyloop_us[I2C_FREQ_COUNT] = { [I2C_FREQ_1000KHZ] = 16, /* Enough for 2 bytes */ - [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ - [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ + [I2C_FREQ_400KHZ] = 40, /* Enough for 2 bytes */ + [I2C_FREQ_100KHZ] = 0, /* No busy looping at 100kHz (bus is slow) */ }; /* @@ -94,8 +94,8 @@ static const uint32_t i2c_regs_base[] = { /* I2C port state data */ struct i2c_port_data { - uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ - enum i2c_freq freq; /* Port clock speed */ + uint32_t timeout_us; /* Transaction timeout, or 0 to use default */ + enum i2c_freq freq; /* Port clock speed */ }; static struct i2c_port_data pdata[I2C_PORT_COUNT]; @@ -145,10 +145,10 @@ static void i2c_set_timingr_port(const struct i2c_port_t *p) } /* Assemble write value for timingr register */ timingr = (i2c_timingr[index].scll << STM32_I2C_TIMINGR_SCLL_OFF) | - (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) | - (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) | - (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) | - (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF); + (i2c_timingr[index].sclh << STM32_I2C_TIMINGR_SCLH_OFF) | + (i2c_timingr[index].sdadel << STM32_I2C_TIMINGR_SDADEL_OFF) | + (i2c_timingr[index].scldel << STM32_I2C_TIMINGR_SCLDEL_OFF) | + (i2c_timingr[index].presc << STM32_I2C_TIMINGR_PRESC_OFF); /* Write timingr value */ STM32_I2C_TIMINGR(base) = timingr; @@ -189,8 +189,8 @@ static void i2c_init_port(const struct i2c_port_t *p) mask = STM32_RCC_CCIPR_I2CNSEL_MASK << shift; clksel = STM32_RCC_CCIPR; clksel &= ~mask; - STM32_RCC_CCIPR = clksel | (STM32_RCC_CCIPR_I2CNSEL_HSI - << shift); + STM32_RCC_CCIPR = clksel | + (STM32_RCC_CCIPR_I2CNSEL_HSI << shift); } else if (port == 3) { /* i2c4sel is bits 1:0, no shift required */ STM32_RCC_CCIPR2 &= ~STM32_RCC_CCIPR2_I2C4SEL_MASK; @@ -260,9 +260,8 @@ static int wait_isr(int port, int mask) * Exported functions declared in i2c.h */ /* Perform an i2c transaction. */ -int chip_i2c_xfer(const int port, const uint16_t addr_flags, - const uint8_t *out, int out_bytes, - uint8_t *in, int in_bytes, int flags) +int chip_i2c_xfer(const int port, const uint16_t addr_flags, const uint8_t *out, + int out_bytes, uint8_t *in, int in_bytes, int flags) { int addr_8bit = I2C_STRIP_FLAGS(addr_flags) << 1; int rv = EC_SUCCESS; @@ -290,13 +289,13 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ - STM32_I2C_CR2(base) = ((out_bytes & 0xFF) << 16) - | addr_8bit - | ((in_bytes == 0 && xfer_stop) ? - STM32_I2C_CR2_AUTOEND : 0) - | ((in_bytes == 0 && !xfer_stop) ? - STM32_I2C_CR2_RELOAD : 0) - | (xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(base) = + ((out_bytes & 0xFF) << 16) | addr_8bit | + ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : + 0) | + ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : + 0) | + (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); @@ -319,11 +318,11 @@ int chip_i2c_xfer(const int port, const uint16_t addr_flags, * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ - STM32_I2C_CR2(base) = ((in_bytes & 0xFF) << 16) - | STM32_I2C_CR2_RD_WRN | addr_8bit - | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) - | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) - | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); + STM32_I2C_CR2(base) = + ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | + addr_8bit | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | + (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | + (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ @@ -402,7 +401,7 @@ int i2c_raw_get_sda(int port) int i2c_get_line_levels(int port) { return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) | - (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); + (i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0); } /*****************************************************************************/ -- cgit v1.2.1 From 82ac45d5a1801a2ae80f84a088ab3d3a7b1d3af2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:09 -0600 Subject: chip/stm32/registers-stm32f0.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id78c82f8d33ab6036ffa6460a6f71bd1e43a643e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729408 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f0.h | 1228 ++++++++++++++++++++-------------------- 1 file changed, 609 insertions(+), 619 deletions(-) diff --git a/chip/stm32/registers-stm32f0.h b/chip/stm32/registers-stm32f0.h index ee4963777b..867c1cc909 100644 --- a/chip/stm32/registers-stm32f0.h +++ b/chip/stm32/registers-stm32f0.h @@ -23,407 +23,402 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_RTC_WAKEUP 2 -#define STM32_IRQ_RTC_ALARM 2 -#define STM32_IRQ_FLASH 3 -#define STM32_IRQ_RCC 4 -#define STM32_IRQ_EXTI0_1 5 -#define STM32_IRQ_EXTI2_3 6 -#define STM32_IRQ_EXTI4_15 7 -#define STM32_IRQ_TSC 8 -#define STM32_IRQ_DMA_CHANNEL_1 9 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_RTC_WAKEUP 2 +#define STM32_IRQ_RTC_ALARM 2 +#define STM32_IRQ_FLASH 3 +#define STM32_IRQ_RCC 4 +#define STM32_IRQ_EXTI0_1 5 +#define STM32_IRQ_EXTI2_3 6 +#define STM32_IRQ_EXTI4_15 7 +#define STM32_IRQ_TSC 8 +#define STM32_IRQ_DMA_CHANNEL_1 9 #define STM32_IRQ_DMA_CHANNEL_2_3 10 #define STM32_IRQ_DMA_CHANNEL_4_7 11 -#define STM32_IRQ_ADC_COMP 12 +#define STM32_IRQ_ADC_COMP 12 #define STM32_IRQ_TIM1_BRK_UP_TRG 13 -#define STM32_IRQ_TIM1_CC 14 -#define STM32_IRQ_TIM2 15 -#define STM32_IRQ_TIM3 16 -#define STM32_IRQ_TIM6_DAC 17 -#define STM32_IRQ_TIM7 18 -#define STM32_IRQ_TIM14 19 -#define STM32_IRQ_TIM15 20 -#define STM32_IRQ_TIM16 21 -#define STM32_IRQ_TIM17 22 -#define STM32_IRQ_I2C1 23 -#define STM32_IRQ_I2C2 24 -#define STM32_IRQ_SPI1 25 -#define STM32_IRQ_SPI2 26 -#define STM32_IRQ_USART1 27 -#define STM32_IRQ_USART2 28 -#define STM32_IRQ_USART3_4 29 -#define STM32_IRQ_CEC_CAN 30 -#define STM32_IRQ_USB 31 +#define STM32_IRQ_TIM1_CC 14 +#define STM32_IRQ_TIM2 15 +#define STM32_IRQ_TIM3 16 +#define STM32_IRQ_TIM6_DAC 17 +#define STM32_IRQ_TIM7 18 +#define STM32_IRQ_TIM14 19 +#define STM32_IRQ_TIM15 20 +#define STM32_IRQ_TIM16 21 +#define STM32_IRQ_TIM17 22 +#define STM32_IRQ_I2C1 23 +#define STM32_IRQ_I2C2 24 +#define STM32_IRQ_SPI1 25 +#define STM32_IRQ_SPI2 26 +#define STM32_IRQ_USART1 27 +#define STM32_IRQ_USART2 28 +#define STM32_IRQ_USART3_4 29 +#define STM32_IRQ_CEC_CAN 30 +#define STM32_IRQ_USB 31 /* aliases for easier code sharing */ #define STM32_IRQ_COMP STM32_IRQ_ADC_COMP #define STM32_IRQ_USB_LP STM32_IRQ_USB - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_COMP_BASE 0x40010000 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_DBGMCU_BASE 0x40015800 +#define STM32_COMP_BASE 0x40010000 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 +#define STM32_DBGMCU_BASE 0x40015800 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 -#define STM32_FLASH_REGS_BASE 0x40022000 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_GPIOA_BASE 0x48000000 -#define STM32_GPIOB_BASE 0x48000400 -#define STM32_GPIOC_BASE 0x48000800 -#define STM32_GPIOD_BASE 0x48000C00 -#define STM32_GPIOE_BASE 0x48001000 -#define STM32_GPIOF_BASE 0x48001400 -#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ -#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ +#define STM32_FLASH_REGS_BASE 0x40022000 -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000C00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOG_BASE 0x48001800 /* only for stm32l4x6 */ +#define STM32_GPIOH_BASE 0x48001C00 /* only for stm32l4 */ -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_OPTB_BASE 0x1FFFF800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_OPTB_BASE 0x1FFFF800 -#define STM32_RCC_BASE 0x40021000 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RCC_BASE 0x40021000 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) - +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWD_PVD_LS_MASK (0x07 << 5) -#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5) -#define STM32_PWR_PVDE BIT(4) - -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - -#define STM32_PWR_CSR_EWUP1 BIT(8) -#define STM32_PWR_CSR_EWUP2 BIT(9) -#define STM32_PWR_CSR_EWUP3 BIT(10) -#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ -#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ - -#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ -#define STM32_CRS_CR_SYNCOKIE BIT(0) -#define STM32_CRS_CR_SYNCWARNIE BIT(1) -#define STM32_CRS_CR_ERRIE BIT(2) -#define STM32_CRS_CR_ESYNCIE BIT(3) -#define STM32_CRS_CR_CEN BIT(5) -#define STM32_CRS_CR_AUTOTRIMEN BIT(6) -#define STM32_CRS_CR_SWSYNC BIT(7) -#define STM32_CRS_CR_TRIM(n) (((n) & 0x3f) << 8) - -#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ -#define STM32_CRS_CFGR_RELOAD(n) (((n) & 0xffff) << 0) -#define STM32_CRS_CFGR_FELIM(n) (((n) & 0xff) << 16) -#define STM32_CRS_CFGR_SYNCDIV(n) (((n) & 7) << 24) -#define STM32_CRS_CFGR_SYNCSRC(n) (((n) & 3) << 28) -#define STM32_CRS_CFGR_SYNCPOL BIT(31) - -#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ -#define STM32_CRS_ISR_SYNCOKF BIT(0) -#define STM32_CRS_ISR_SYNCWARNF BIT(1) -#define STM32_CRS_ISR_ERRF BIT(2) -#define STM32_CRS_ISR_ESYNCF BIT(3) -#define STM32_CRS_ISR_SYNCERR BIT(8) -#define STM32_CRS_ISR_SYNCMISS BIT(9) -#define STM32_CRS_ISR_TRIMOVF BIT(10) -#define STM32_CRS_ISR_FEDIR BIT(15) -#define STM32_CRS_ISR_FECAP (0xffff << 16) - -#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ -#define STM32_CRS_ICR_SYNCOKC BIT(0) -#define STM32_CRS_ICR_SYNCWARINC BIT(1) -#define STM32_CRS_ICR_ERRC BIT(2) -#define STM32_CRS_ICR_ESYNCC BIT(3) - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ -#define STM32_RCC_APB2ENR_TIM16EN BIT(17) -#define STM32_RCC_APB2ENR_TIM17EN BIT(18) -#define STM32_RCC_DBGMCUEN BIT(22) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) -#define STM32_RCC_DACEN BIT(29) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) +#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWD_PVD_LS_MASK (0x07 << 5) +#define STM32_PWD_PVD_LS(n) ((n & 0x07) << 5) +#define STM32_PWR_PVDE BIT(4) + +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_PWR_CSR_EWUP1 BIT(8) +#define STM32_PWR_CSR_EWUP2 BIT(9) +#define STM32_PWR_CSR_EWUP3 BIT(10) +#define STM32_PWR_CSR_EWUP4 BIT(11) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP5 BIT(12) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP6 BIT(13) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP7 BIT(14) /* STM32F0xx only */ +#define STM32_PWR_CSR_EWUP8 BIT(15) /* STM32F0xx only */ + +#define STM32_CRS_CR REG32(STM32_CRS_BASE + 0x00) /* STM32F0XX */ +#define STM32_CRS_CR_SYNCOKIE BIT(0) +#define STM32_CRS_CR_SYNCWARNIE BIT(1) +#define STM32_CRS_CR_ERRIE BIT(2) +#define STM32_CRS_CR_ESYNCIE BIT(3) +#define STM32_CRS_CR_CEN BIT(5) +#define STM32_CRS_CR_AUTOTRIMEN BIT(6) +#define STM32_CRS_CR_SWSYNC BIT(7) +#define STM32_CRS_CR_TRIM(n) (((n)&0x3f) << 8) + +#define STM32_CRS_CFGR REG32(STM32_CRS_BASE + 0x04) /* STM32F0XX */ +#define STM32_CRS_CFGR_RELOAD(n) (((n)&0xffff) << 0) +#define STM32_CRS_CFGR_FELIM(n) (((n)&0xff) << 16) +#define STM32_CRS_CFGR_SYNCDIV(n) (((n)&7) << 24) +#define STM32_CRS_CFGR_SYNCSRC(n) (((n)&3) << 28) +#define STM32_CRS_CFGR_SYNCPOL BIT(31) + +#define STM32_CRS_ISR REG32(STM32_CRS_BASE + 0x08) /* STM32F0XX */ +#define STM32_CRS_ISR_SYNCOKF BIT(0) +#define STM32_CRS_ISR_SYNCWARNF BIT(1) +#define STM32_CRS_ISR_ERRF BIT(2) +#define STM32_CRS_ISR_ESYNCF BIT(3) +#define STM32_CRS_ISR_SYNCERR BIT(8) +#define STM32_CRS_ISR_SYNCMISS BIT(9) +#define STM32_CRS_ISR_TRIMOVF BIT(10) +#define STM32_CRS_ISR_FEDIR BIT(15) +#define STM32_CRS_ISR_FECAP (0xffff << 16) + +#define STM32_CRS_ICR REG32(STM32_CRS_BASE + 0x0c) /* STM32F0XX */ +#define STM32_CRS_ICR_SYNCOKC BIT(0) +#define STM32_CRS_ICR_SYNCWARINC BIT(1) +#define STM32_CRS_ICR_ERRC BIT(2) +#define STM32_CRS_ICR_ESYNCC BIT(3) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x0c) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_APB2ENR_ADCEN BIT(9) /* STM32F3/F0 */ +#define STM32_RCC_APB2ENR_TIM16EN BIT(17) +#define STM32_RCC_APB2ENR_TIM17EN BIT(18) +#define STM32_RCC_DBGMCUEN BIT(22) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x1c) +#define STM32_RCC_DACEN BIT(29) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x24) /* STM32F373 */ -#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) +#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ +#define STM32_RCC_CFGR3 REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CR2 REG32(STM32_RCC_BASE + 0x34) /* STM32F0XX */ -#define STM32_RCC_HB_DMA1 BIT(0) +#define STM32_RCC_HB_DMA1 BIT(0) /* STM32F373 */ -#define STM32_RCC_HB_DMA2 BIT(1) -#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ -#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ -#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ -#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ -#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ -#define STM32_RCC_PB1_USB BIT(23) -#define STM32_RCC_PB1_CRS BIT(27) - -#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) - +#define STM32_RCC_HB_DMA2 BIT(1) +#define STM32_RCC_PB2_TIM1 BIT(11) /* Except STM32F373 */ +#define STM32_RCC_PB2_TIM15 BIT(16) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM16 BIT(17) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM17 BIT(18) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB2_TIM19 BIT(19) /* STM32F373 */ +#define STM32_RCC_PB2_PMAD BIT(11) /* STM32TS */ +#define STM32_RCC_PB2_PMSE BIT(13) /* STM32TS */ +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32F373 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32F373 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32F0XX and STM32F373 */ +#define STM32_RCC_PB1_TIM18 BIT(9) /* STM32F373 */ +#define STM32_RCC_PB1_USB BIT(23) +#define STM32_RCC_PB1_CRS BIT(27) + +#define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CFGR2 REG32(STM32_SYSCFG_BASE + 0x18) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 20 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 20 /* --- SPI --- */ @@ -440,8 +435,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -451,155 +446,154 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(4) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB - -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 -#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_PGERR BIT(2) -#define FLASH_SR_WRPRTERR BIT(4) -#define FLASH_SR_ALL_ERR \ - (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) -#define FLASH_SR_EOP BIT(5) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_OPTPG BIT(4) -#define FLASH_CR_OPTER BIT(5) -#define FLASH_CR_STRT BIT(6) -#define FLASH_CR_LOCK BIT(7) -#define FLASH_CR_OPTWRE BIT(9) -#define FLASH_CR_OBL_LAUNCH BIT(13) -#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) -#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_OBR_RDP_MASK (3 << 1) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WRP01 0x08 -#define STM32_OPTB_WRP23 0x0c - -#define STM32_OPTB_COMPL_SHIFT 8 +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(4) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB + +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 +#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_PGERR BIT(2) +#define FLASH_SR_WRPRTERR BIT(4) +#define FLASH_SR_ALL_ERR (FLASH_SR_PGERR | FLASH_SR_WRPRTERR) +#define FLASH_SR_EOP BIT(5) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_OPTPG BIT(4) +#define FLASH_CR_OPTER BIT(5) +#define FLASH_CR_STRT BIT(6) +#define FLASH_CR_LOCK BIT(7) +#define FLASH_CR_OPTWRE BIT(9) +#define FLASH_CR_OBL_LAUNCH BIT(13) +#define STM32_FLASH_OPT_LOCKED (!(STM32_FLASH_CR & FLASH_CR_OPTWRE)) +#define STM32_FLASH_AR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_OBR_RDP_MASK (3 << 1) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WRP01 0x08 +#define STM32_OPTB_WRP23 0x0c + +#define STM32_OPTB_COMPL_SHIFT 8 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_PVD_EVENT BIT(16) -#define EXTI_RTC_ALR_EVENT BIT(17) -#define EXTI_COMP2_EVENT BIT(22) +#define EXTI_PVD_EVENT BIT(16) +#define EXTI_RTC_ALR_EVENT BIT(17) +#define EXTI_COMP2_EVENT BIT(22) /* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_ISR_ADRDY BIT(0) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_IER_AWDIE BIT(7) -#define STM32_ADC_IER_OVRIE BIT(4) -#define STM32_ADC_IER_EOSEQIE BIT(3) -#define STM32_ADC_IER_EOCIE BIT(2) -#define STM32_ADC_IER_EOSMPIE BIT(1) -#define STM32_ADC_IER_ADRDYIE BIT(0) - -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADDIS BIT(1) -#define STM32_ADC_CR_ADCAL BIT(31) -#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_ISR_ADRDY BIT(0) +#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_IER_AWDIE BIT(7) +#define STM32_ADC_IER_OVRIE BIT(4) +#define STM32_ADC_IER_EOSEQIE BIT(3) +#define STM32_ADC_IER_EOCIE BIT(2) +#define STM32_ADC_IER_EOSMPIE BIT(1) +#define STM32_ADC_IER_ADRDYIE BIT(0) + +#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR_ADEN BIT(0) +#define STM32_ADC_CR_ADDIS BIT(1) +#define STM32_ADC_CR_ADCAL BIT(31) +#define STM32_ADC_CFGR1 REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ #define STM32_ADC_CFGR1_AWDCH_MASK (0x1f << 26) -#define STM32_ADC_CFGR1_AWDEN BIT(23) -#define STM32_ADC_CFGR1_AWDSGL BIT(22) +#define STM32_ADC_CFGR1_AWDEN BIT(23) +#define STM32_ADC_CFGR1_AWDSGL BIT(22) /* Selects single vs continuous */ -#define STM32_ADC_CFGR1_CONT BIT(13) +#define STM32_ADC_CFGR1_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC_CFGR1_OVRMOD BIT(12) +#define STM32_ADC_CFGR1_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) +#define STM32_ADC_CFGR1_EXTEN_DIS (0 << 10) #define STM32_ADC_CFGR1_EXTEN_RISE (1 << 10) #define STM32_ADC_CFGR1_EXTEN_FALL (2 << 10) #define STM32_ADC_CFGR1_EXTEN_BOTH (3 << 10) #define STM32_ADC_CFGR1_EXTEN_MASK (3 << 10) /* External trigger selection */ -#define STM32_ADC_CFGR1_TRG0 (0 << 6) -#define STM32_ADC_CFGR1_TRG1 (1 << 6) -#define STM32_ADC_CFGR1_TRG2 (2 << 6) -#define STM32_ADC_CFGR1_TRG3 (3 << 6) -#define STM32_ADC_CFGR1_TRG4 (4 << 6) -#define STM32_ADC_CFGR1_TRG5 (5 << 6) -#define STM32_ADC_CFGR1_TRG6 (6 << 6) -#define STM32_ADC_CFGR1_TRG7 (7 << 6) -#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) +#define STM32_ADC_CFGR1_TRG0 (0 << 6) +#define STM32_ADC_CFGR1_TRG1 (1 << 6) +#define STM32_ADC_CFGR1_TRG2 (2 << 6) +#define STM32_ADC_CFGR1_TRG3 (3 << 6) +#define STM32_ADC_CFGR1_TRG4 (4 << 6) +#define STM32_ADC_CFGR1_TRG5 (5 << 6) +#define STM32_ADC_CFGR1_TRG6 (6 << 6) +#define STM32_ADC_CFGR1_TRG7 (7 << 6) +#define STM32_ADC_CFGR1_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC_CFGR1_DMACFG BIT(1) -#define STM32_ADC_CFGR1_DMAEN BIT(0) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_CFGR1_DMACFG BIT(1) +#define STM32_ADC_CFGR1_DMAEN BIT(0) +#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_SMPR REG32(STM32_ADC1_BASE + 0x14) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC_SMPR_SMP(s) ((s)-1) +#define STM32_ADC_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x1C) -#define STM32_COMP_CMP2LOCK BIT(31) -#define STM32_COMP_CMP2OUT BIT(30) -#define STM32_COMP_CMP2HYST_HI (3 << 28) -#define STM32_COMP_CMP2HYST_MED (2 << 28) -#define STM32_COMP_CMP2HYST_LOW (1 << 28) -#define STM32_COMP_CMP2HYST_NO (0 << 28) -#define STM32_COMP_CMP2POL BIT(27) +#define STM32_COMP_CMP2LOCK BIT(31) +#define STM32_COMP_CMP2OUT BIT(30) +#define STM32_COMP_CMP2HYST_HI (3 << 28) +#define STM32_COMP_CMP2HYST_MED (2 << 28) +#define STM32_COMP_CMP2HYST_LOW (1 << 28) +#define STM32_COMP_CMP2HYST_NO (0 << 28) +#define STM32_COMP_CMP2POL BIT(27) #define STM32_COMP_CMP2OUTSEL_TIM3_OCR (7 << 24) #define STM32_COMP_CMP2OUTSEL_TIM3_IC1 (6 << 24) @@ -608,32 +602,32 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP2OUTSEL_TIM1_OCR (3 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_IC1 (2 << 24) #define STM32_COMP_CMP2OUTSEL_TIM1_BRK (1 << 24) -#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) -#define STM32_COMP_WNDWEN BIT(23) - -#define STM32_COMP_CMP2INSEL_MASK (7 << 20) -#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ -#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) -#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) -#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) -#define STM32_COMP_CMP2INSEL_VREF (3 << 20) -#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) -#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) -#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) - -#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) -#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) -#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) -#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) -#define STM32_COMP_CMP2EN BIT(16) - -#define STM32_COMP_CMP1LOCK BIT(15) -#define STM32_COMP_CMP1OUT BIT(14) -#define STM32_COMP_CMP1HYST_HI (3 << 12) -#define STM32_COMP_CMP1HYST_MED (2 << 12) -#define STM32_COMP_CMP1HYST_LOW (1 << 12) -#define STM32_COMP_CMP1HYST_NO (0 << 12) -#define STM32_COMP_CMP1POL BIT(11) +#define STM32_COMP_CMP2OUTSEL_NONE (0 << 24) +#define STM32_COMP_WNDWEN BIT(23) + +#define STM32_COMP_CMP2INSEL_MASK (7 << 20) +#define STM32_COMP_CMP2INSEL_INM7 (6 << 20) /* STM32F373 only */ +#define STM32_COMP_CMP2INSEL_INM6 (6 << 20) +#define STM32_COMP_CMP2INSEL_INM5 (5 << 20) +#define STM32_COMP_CMP2INSEL_INM4 (4 << 20) +#define STM32_COMP_CMP2INSEL_VREF (3 << 20) +#define STM32_COMP_CMP2INSEL_VREF34 (2 << 20) +#define STM32_COMP_CMP2INSEL_VREF12 (1 << 20) +#define STM32_COMP_CMP2INSEL_VREF14 (0 << 20) + +#define STM32_COMP_CMP2MODE_VLSPEED (3 << 18) +#define STM32_COMP_CMP2MODE_LSPEED (2 << 18) +#define STM32_COMP_CMP2MODE_MSPEED (1 << 18) +#define STM32_COMP_CMP2MODE_HSPEED (0 << 18) +#define STM32_COMP_CMP2EN BIT(16) + +#define STM32_COMP_CMP1LOCK BIT(15) +#define STM32_COMP_CMP1OUT BIT(14) +#define STM32_COMP_CMP1HYST_HI (3 << 12) +#define STM32_COMP_CMP1HYST_MED (2 << 12) +#define STM32_COMP_CMP1HYST_LOW (1 << 12) +#define STM32_COMP_CMP1HYST_NO (0 << 12) +#define STM32_COMP_CMP1POL BIT(11) #define STM32_COMP_CMP1OUTSEL_TIM3_OCR (7 << 8) #define STM32_COMP_CMP1OUTSEL_TIM3_IC1 (6 << 8) @@ -642,25 +636,24 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_COMP_CMP1OUTSEL_TIM1_OCR (3 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_IC1 (2 << 8) #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8) -#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) - -#define STM32_COMP_CMP1INSEL_MASK (7 << 4) -#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ -#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) -#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) -#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) -#define STM32_COMP_CMP1INSEL_VREF (3 << 4) -#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) -#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) -#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) - -#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) -#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) -#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) -#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) -#define STM32_COMP_CMP1SW1 BIT(1) -#define STM32_COMP_CMP1EN BIT(0) - +#define STM32_COMP_CMP1OUTSEL_NONE (0 << 8) + +#define STM32_COMP_CMP1INSEL_MASK (7 << 4) +#define STM32_COMP_CMP1INSEL_INM7 (7 << 4) /* STM32F373 only */ +#define STM32_COMP_CMP1INSEL_INM6 (6 << 4) +#define STM32_COMP_CMP1INSEL_INM5 (5 << 4) +#define STM32_COMP_CMP1INSEL_INM4 (4 << 4) +#define STM32_COMP_CMP1INSEL_VREF (3 << 4) +#define STM32_COMP_CMP1INSEL_VREF34 (2 << 4) +#define STM32_COMP_CMP1INSEL_VREF12 (1 << 4) +#define STM32_COMP_CMP1INSEL_VREF14 (0 << 4) + +#define STM32_COMP_CMP1MODE_VLSPEED (3 << 2) +#define STM32_COMP_CMP1MODE_LSPEED (2 << 2) +#define STM32_COMP_CMP1MODE_MSPEED (1 << 2) +#define STM32_COMP_CMP1MODE_HSPEED (0 << 2) +#define STM32_COMP_CMP1SW1 BIT(1) +#define STM32_COMP_CMP1EN BIT(0) /* --- DMA --- */ @@ -727,11 +720,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -742,8 +735,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -752,108 +745,106 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #ifdef CHIP_VARIANT_STM32F09X #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) #else #define STM32_DMA_REGS(channel) STM32_DMA1_REGS #endif /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -863,28 +854,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 5cb4732802cf465eebb31ff095d3ac0faaf46a9d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:50 -0600 Subject: include/usb_sm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5ed781ff2d348615ed9dc1760f1bd9cc3a53aff3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730448 Reviewed-by: Jeremy Bettis --- include/usb_sm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/usb_sm.h b/include/usb_sm.h index 2b5939bc04..0688193453 100644 --- a/include/usb_sm.h +++ b/include/usb_sm.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_USB_SM_H #define __CROS_EC_USB_SM_H -#include "compiler.h" /* for typeof() on Zephyr */ +#include "compiler.h" /* for typeof() on Zephyr */ /* Function pointer that implements a portion of a usb state */ typedef void (*state_execution)(const int port); @@ -101,13 +101,13 @@ struct test_sm_data { /* Size fo the state machine array above */ const int size; /* The array of names for states, can be NULL */ - const char * const * const names; + const char *const *const names; /* The size of the above names array */ const int names_size; }; #endif /* Creates a state machine state that will never link. Useful with IS_ENABLED */ -#define GEN_NOT_SUPPORTED(state) extern typeof(state) state ## _NOT_SUPPORTED +#define GEN_NOT_SUPPORTED(state) extern typeof(state) state##_NOT_SUPPORTED #endif /* __CROS_EC_USB_SM_H */ -- cgit v1.2.1 From 91994fad04f705a45ce90d39477801daf043787a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:17 -0600 Subject: include/usb_i2c.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie53b2ef0204e0db4650e86d6f0f42a478c223a51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730436 Reviewed-by: Jeremy Bettis --- include/usb_i2c.h | 94 ++++++++++++++++++++++++------------------------------- 1 file changed, 41 insertions(+), 53 deletions(-) diff --git a/include/usb_i2c.h b/include/usb_i2c.h index fd79293014..6f7e7379ac 100644 --- a/include/usb_i2c.h +++ b/include/usb_i2c.h @@ -99,28 +99,28 @@ */ enum usb_i2c_error { - USB_I2C_SUCCESS = 0x0000, - USB_I2C_TIMEOUT = 0x0001, - USB_I2C_BUSY = 0x0002, + USB_I2C_SUCCESS = 0x0000, + USB_I2C_TIMEOUT = 0x0001, + USB_I2C_BUSY = 0x0002, USB_I2C_WRITE_COUNT_INVALID = 0x0003, - USB_I2C_READ_COUNT_INVALID = 0x0004, - USB_I2C_PORT_INVALID = 0x0005, - USB_I2C_DISABLED = 0x0006, - USB_I2C_MISSING_HANDLER = 0x0007, + USB_I2C_READ_COUNT_INVALID = 0x0004, + USB_I2C_PORT_INVALID = 0x0005, + USB_I2C_DISABLED = 0x0006, + USB_I2C_MISSING_HANDLER = 0x0007, USB_I2C_UNSUPPORTED_COMMAND = 0x0008, - USB_I2C_UNKNOWN_ERROR = 0x8000, + USB_I2C_UNKNOWN_ERROR = 0x8000, }; - #define USB_I2C_WRITE_BUFFER (CONFIG_USB_I2C_MAX_WRITE_COUNT + 4) /* If read payload is larger or equal to 128 bytes, header contains rc1 */ -#define USB_I2C_READ_BUFFER ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ? \ - (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \ - (CONFIG_USB_I2C_MAX_READ_COUNT + 6)) +#define USB_I2C_READ_BUFFER \ + ((CONFIG_USB_I2C_MAX_READ_COUNT < 128) ? \ + (CONFIG_USB_I2C_MAX_READ_COUNT + 4) : \ + (CONFIG_USB_I2C_MAX_READ_COUNT + 6)) -#define USB_I2C_BUFFER_SIZE \ - (USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? \ - USB_I2C_READ_BUFFER : USB_I2C_WRITE_BUFFER) +#define USB_I2C_BUFFER_SIZE \ + (USB_I2C_READ_BUFFER > USB_I2C_WRITE_BUFFER ? USB_I2C_READ_BUFFER : \ + USB_I2C_WRITE_BUFFER) BUILD_ASSERT(POWER_OF_TWO(USB_I2C_READ_BUFFER)); BUILD_ASSERT(POWER_OF_TWO(USB_I2C_WRITE_BUFFER)); @@ -156,28 +156,18 @@ extern struct consumer_ops const usb_i2c_consumer_ops; * ENDPOINT is the index of the USB bulk endpoint used for receiving and * transmitting bytes. */ -#define USB_I2C_CONFIG(NAME, \ - INTERFACE, \ - INTERFACE_NAME, \ - ENDPOINT) \ - static uint16_t \ - CONCAT2(NAME, _buffer_) \ - [USB_I2C_BUFFER_SIZE / 2]; \ - static void CONCAT2(NAME, _deferred_)(void); \ - DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ - static struct queue const CONCAT2(NAME, _to_usb_); \ - static struct queue const CONCAT3(usb_to_, NAME, _); \ - USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), \ - INTERFACE, \ - USB_CLASS_VENDOR_SPEC, \ - USB_SUBCLASS_GOOGLE_I2C, \ - USB_PROTOCOL_GOOGLE_I2C, \ - INTERFACE_NAME, \ - ENDPOINT, \ - USB_MAX_PACKET_SIZE, \ - USB_MAX_PACKET_SIZE, \ - CONCAT3(usb_to_, NAME, _), \ - CONCAT2(NAME, _to_usb_)) \ +#define USB_I2C_CONFIG(NAME, INTERFACE, INTERFACE_NAME, ENDPOINT) \ + static uint16_t CONCAT2(NAME, _buffer_)[USB_I2C_BUFFER_SIZE / 2]; \ + static void CONCAT2(NAME, _deferred_)(void); \ + DECLARE_DEFERRED(CONCAT2(NAME, _deferred_)); \ + static struct queue const CONCAT2(NAME, _to_usb_); \ + static struct queue const CONCAT3(usb_to_, NAME, _); \ + USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_), INTERFACE, \ + USB_CLASS_VENDOR_SPEC, USB_SUBCLASS_GOOGLE_I2C, \ + USB_PROTOCOL_GOOGLE_I2C, INTERFACE_NAME, \ + ENDPOINT, USB_MAX_PACKET_SIZE, \ + USB_MAX_PACKET_SIZE, CONCAT3(usb_to_, NAME, _), \ + CONCAT2(NAME, _to_usb_)) \ struct usb_i2c_config const NAME = { \ .buffer = CONCAT2(NAME, _buffer_), \ .deferred = &CONCAT2(NAME, _deferred__data), \ @@ -186,15 +176,17 @@ extern struct consumer_ops const usb_i2c_consumer_ops; .ops = &usb_i2c_consumer_ops, \ }, \ .tx_queue = &CONCAT2(NAME, _to_usb_), \ - }; \ - static struct queue const CONCAT2(NAME, _to_usb_) = \ - QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, \ - null_producer, CONCAT2(NAME, _usb_).consumer); \ - static struct queue const CONCAT3(usb_to_, NAME, _) = \ - QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t, \ - CONCAT2(NAME, _usb_).producer, NAME.consumer); \ - static void CONCAT2(NAME, _deferred_)(void) \ - { usb_i2c_deferred(&NAME); } + }; \ + static struct queue const CONCAT2(NAME, _to_usb_) = \ + QUEUE_DIRECT(USB_I2C_READ_BUFFER, uint8_t, null_producer, \ + CONCAT2(NAME, _usb_).consumer); \ + static struct queue const CONCAT3(usb_to_, NAME, _) = \ + QUEUE_DIRECT(USB_I2C_WRITE_BUFFER, uint8_t, \ + CONCAT2(NAME, _usb_).producer, NAME.consumer); \ + static void CONCAT2(NAME, _deferred_)(void) \ + { \ + usb_i2c_deferred(&NAME); \ + } /* * Handle I2C request in a deferred callback. @@ -224,11 +216,7 @@ int usb_i2c_board_is_enabled(void); * Function to call to register a handler for commands sent to the special i2c * address above. */ -int usb_i2c_register_cros_cmd_handler(int (*cmd_handler) - (void *data_in, - size_t in_size, - void *data_out, - size_t out_size)); - +int usb_i2c_register_cros_cmd_handler(int (*cmd_handler)( + void *data_in, size_t in_size, void *data_out, size_t out_size)); -#endif /* __CROS_USB_I2C_H */ +#endif /* __CROS_USB_I2C_H */ -- cgit v1.2.1 From 276a2b42f7722e91a2a7c07c732cd2db019ec40a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:53 -0600 Subject: baseboard/intelrvp/adlrvp.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I88a246537bc6c57459d6d05129491a93536d8140 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727893 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/adlrvp.h | 64 ++++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h index 9e7db0081c..fb2837cc2d 100644 --- a/baseboard/intelrvp/adlrvp.h +++ b/baseboard/intelrvp/adlrvp.h @@ -15,14 +15,14 @@ /* RVP Board ids */ #define CONFIG_BOARD_VERSION_GPIO -#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 -#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 -#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 -#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 -#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 -#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 -#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 -#define ADL_RVP_BOARD_ID(id) ((id) & 0x3F) +#define ADLM_LP4_RVP1_SKU_BOARD_ID 0x01 +#define ADLM_LP5_RVP2_SKU_BOARD_ID 0x02 +#define ADLM_LP5_RVP3_SKU_BOARD_ID 0x03 +#define ADLN_LP5_ERB_SKU_BOARD_ID 0x06 +#define ADLN_LP5_RVP_SKU_BOARD_ID 0x07 +#define ADLP_DDR5_RVP_SKU_BOARD_ID 0x12 +#define ADLP_LP5_T4_RVP_SKU_BOARD_ID 0x13 +#define ADL_RVP_BOARD_ID(id) ((id)&0x3F) /* MECC config */ #define CONFIG_INTEL_RVP_MECC_VERSION_1_0 @@ -36,7 +36,7 @@ /* ADL has new low-power features that require extra-wide virtual wire * pulses. The EDS specifies 100 microseconds. */ #undef CONFIG_ESPI_DEFAULT_VW_WIDTH_US -#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 +#define CONFIG_ESPI_DEFAULT_VW_WIDTH_US 100 /* USB PD config */ #if defined(HAS_TASK_PD_C3) @@ -50,7 +50,7 @@ #endif #define CONFIG_USB_MUX_VIRTUAL #define CONFIG_USB_MUX_TUSB1044 -#define PD_MAX_POWER_MW 100000 +#define PD_MAX_POWER_MW 100000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY @@ -58,10 +58,10 @@ /* Support NXP PCA9675 I/O expander. */ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_PCA9675 -#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 +#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX 0x21 /* DC Jack charge ports */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT #define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 #define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT @@ -69,38 +69,38 @@ #define CONFIG_USBC_PPC_SN5S330 #define CONFIG_USB_PD_VBUS_DETECT_PPC #define CONFIG_USB_PD_DISCHARGE_PPC -#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 +#define I2C_ADDR_SN5S330_TCPC_AIC_PPC 0x40 /* TCPC */ #define CONFIG_USB_PD_DISCHARGE #define CONFIG_USB_PD_TCPM_FUSB302 -#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 +#define I2C_ADDR_FUSB302_TCPC_AIC 0x22 /* Config BB retimer */ #define CONFIG_USBC_RETIMER_INTEL_BB #define CONFIG_USBC_RETIMER_FW_UPDATE /* Connector side BB retimers */ -#define I2C_PORT0_BB_RETIMER_ADDR 0x56 +#define I2C_PORT0_BB_RETIMER_ADDR 0x56 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_ADDR 0x57 +#define I2C_PORT1_BB_RETIMER_ADDR 0x57 #endif #if defined(HAS_TASK_PD_C2) -#define I2C_PORT2_BB_RETIMER_ADDR 0x58 +#define I2C_PORT2_BB_RETIMER_ADDR 0x58 #endif #if defined(HAS_TASK_PD_C3) -#define I2C_PORT3_BB_RETIMER_ADDR 0x59 +#define I2C_PORT3_BB_RETIMER_ADDR 0x59 #endif /* SOC side BB retimers (dual retimer config) */ -#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 +#define I2C_PORT0_BB_RETIMER_SOC_ADDR 0x54 #if defined(HAS_TASK_PD_C1) -#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 +#define I2C_PORT1_BB_RETIMER_SOC_ADDR 0x55 #endif /* I2C EEPROM */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO +#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_EEPROM I2C_PORT_PCA9555_BOARD_ID_GPIO /* Enable CBI */ #define CONFIG_CBI_EEPROM @@ -122,9 +122,9 @@ #define CONFIG_USB_PD_TCPC_LOW_POWER /* Config Fan */ -#define CONFIG_FANS 1 -#define BOARD_FAN_MIN_RPM 3000 -#define BOARD_FAN_MAX_RPM 10000 +#define CONFIG_FANS 1 +#define BOARD_FAN_MIN_RPM 3000 +#define BOARD_FAN_MAX_RPM 10000 /* Charger Configs */ #define CONFIG_CHARGER_RUNTIME_CONFIG @@ -133,15 +133,15 @@ /* Charger chip on ADL-N */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 /* Port 80 */ -#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS +#define PORT80_I2C_ADDR MAX695X_I2C_ADDR1_FLAGS /* Board Id */ -#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 +#define I2C_ADDR_PCA9555_BOARD_ID_GPIO 0x22 /* * Frequent watchdog timer resets are seen, with the @@ -160,7 +160,7 @@ * Support for EC_CMD_BATTERY_GET_STATIC version 1. */ #define CONFIG_BATTERY_V2 -#define CONFIG_BATTERY_COUNT 1 +#define CONFIG_BATTERY_COUNT 1 #define CONFIG_HOSTCMD_BATTERY_V2 /* Config to indicate battery type doesn't auto detect */ @@ -210,7 +210,7 @@ enum adlrvp_bitbang_i2c_channel { I2C_BITBANG_CHAN_IOEX_0, I2C_BITBANG_CHAN_COUNT }; -#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT +#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); void extpower_interrupt(enum gpio_signal signal); -- cgit v1.2.1 From c3be8733dcfba20676dbdc417f9c7d5cb2496a55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:22:42 -0600 Subject: board/bellis/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c7e795b3933e46108268f8f2f9c3a4a2f800790 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728051 Reviewed-by: Jeremy Bettis --- board/bellis/board.h | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/board/bellis/board.h b/board/bellis/board.h index 76f70f47c1..3948e704af 100644 --- a/board/bellis/board.h +++ b/board/bellis/board.h @@ -27,13 +27,13 @@ #undef STM32_PLLM #undef STM32_PLLN #undef STM32_PLLR -#define STM32_PLLM 1 +#define STM32_PLLM 1 #ifdef STM32_HSE_CLOCK -#define STM32_PLLN 12 +#define STM32_PLLN 12 #else -#define STM32_PLLN 10 +#define STM32_PLLN 10 #endif -#define STM32_PLLR 2 +#define STM32_PLLR 2 #define STM32_USE_PLL @@ -65,13 +65,12 @@ #define CONFIG_LED_ONOFF_STATES #define CONFIG_LED_POWER_LED -#undef CONFIG_WATCHDOG_PERIOD_MS +#undef CONFIG_WATCHDOG_PERIOD_MS #define CONFIG_WATCHDOG_PERIOD_MS 4000 - /* Motion Sensors */ #ifndef VARIANT_KUKUI_NO_SENSORS -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ #define CONFIG_ACCELGYRO_BMI160 /* Base accel */ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -93,34 +92,34 @@ #endif /* VARIANT_KUKUI_NO_SENSORS */ /* I2C ports */ -#define I2C_PORT_BC12 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_CHARGER 2 -#define I2C_PORT_SENSORS 2 -#define I2C_PORT_KB_DISCRETE 2 -#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_BATTERY 3 -#define I2C_PORT_TCPC0 0 +#define I2C_PORT_BC12 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_CHARGER 2 +#define I2C_PORT_SENSORS 2 +#define I2C_PORT_KB_DISCRETE 2 +#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY +#define I2C_PORT_BATTERY 3 +#define I2C_PORT_TCPC0 0 #undef I2C_CONTROLLER_COUNT #undef I2C_PORT_COUNT -#define I2C_CONTROLLER_COUNT 3 -#define I2C_PORT_COUNT 3 +#define I2C_CONTROLLER_COUNT 3 +#define I2C_PORT_COUNT 3 /* IT8801 I2C address */ -#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 +#define KB_DISCRETE_I2C_ADDR_FLAGS IT8801_I2C_ADDR1 /* Enable Accel over SPI */ -#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ +#define CONFIG_SPI_ACCEL_PORT 0 /* The first SPI controller port (SPI2) */ #define CONFIG_KEYBOARD_PROTOCOL_MKBP #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO /* Define the MKBP events which are allowed to wakeup AP in S3. */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) #undef CONFIG_GMR_TABLET_MODE #undef GPIO_TABLET_MODE_L -- cgit v1.2.1 From cc68f7ac90fae9c87b436f50cf411c91c5e6799c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:37 -0600 Subject: common/usbc/usb_tc_vpd_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie893a0695c6b3fa011238ab11e608f4e0c715a83 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729797 Reviewed-by: Jeremy Bettis --- common/usbc/usb_tc_vpd_sm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/common/usbc/usb_tc_vpd_sm.c b/common/usbc/usb_tc_vpd_sm.c index 70f3ed6327..11cc947cb1 100644 --- a/common/usbc/usb_tc_vpd_sm.c +++ b/common/usbc/usb_tc_vpd_sm.c @@ -17,15 +17,15 @@ /* USB Type-C VCONN Powered Device module */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) #else /* CONFIG_COMMON_RUNTIME */ #define CPRINTF(format, args...) #define CPRINTS(format, args...) #endif /* Type-C Layer Flags */ -#define TC_FLAGS_VCONN_ON BIT(0) +#define TC_FLAGS_VCONN_ON BIT(0) /** * This is the Type-C Port object that contains information needed to @@ -61,7 +61,7 @@ enum usb_tc_state { static const struct usb_state tc_states[]; /* List of human readable state names for console debugging */ -__maybe_unused static const char * const tc_state_names[] = { +__maybe_unused static const char *const tc_state_names[] = { #ifdef CONFIG_COMMON_RUNTIME [TC_DISABLED] = "Disabled", [TC_UNATTACHED_SNK] = "Unattached.SNK", @@ -270,11 +270,11 @@ static void tc_attach_wait_snk_run(const int port) if (tc[port].host_cc_state != host_new_cc_state) { tc[port].host_cc_state = host_new_cc_state; if (host_new_cc_state == PD_CC_DFP_ATTACHED) - tc[port].cc_debounce = get_time().val + - PD_T_CC_DEBOUNCE; + tc[port].cc_debounce = + get_time().val + PD_T_CC_DEBOUNCE; else - tc[port].cc_debounce = get_time().val + - PD_T_PD_DEBOUNCE; + tc[port].cc_debounce = + get_time().val + PD_T_PD_DEBOUNCE; return; } @@ -293,7 +293,7 @@ static void tc_attach_wait_snk_run(const int port) * CC2 pins is SNK.Open for at least tPDDebounce. */ if (tc[port].host_cc_state == PD_CC_DFP_ATTACHED && - (vpd_is_vconn_present() || vpd_is_host_vbus_present())) + (vpd_is_vconn_present() || vpd_is_host_vbus_present())) set_state_tc(port, TC_ATTACHED_SNK); else if (tc[port].host_cc_state == PD_CC_NONE) set_state_tc(port, TC_UNATTACHED_SNK); -- cgit v1.2.1 From 4f16e3198a0a1bdbefde57cc5aa8c1cd8bc1cbb2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:30 -0600 Subject: board/cappy2/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0dae6e34b51333d0a6354eff9c2c9f150f4e9294 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728137 Reviewed-by: Jeremy Bettis --- board/cappy2/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cappy2/usb_pd_policy.c b/board/cappy2/usb_pd_policy.c index fd9018a3f0..98b770be8f 100644 --- a/board/cappy2/usb_pd_policy.c +++ b/board/cappy2/usb_pd_policy.c @@ -10,8 +10,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From a0c7be53d6533df0111cecffc84035a652d74f25 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:38 -0600 Subject: zephyr/subsys/ap_pwrseq/include/signal_gpio.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0655256501f87e0872df70466e43d231a42e153a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730930 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/signal_gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/signal_gpio.h b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h index e797f0c21f..6dae7b1356 100644 --- a/zephyr/subsys/ap_pwrseq/include/signal_gpio.h +++ b/zephyr/subsys/ap_pwrseq/include/signal_gpio.h @@ -6,7 +6,7 @@ #ifndef __AP_PWRSEQ_SIGNAL_GPIO_H__ #define __AP_PWRSEQ_SIGNAL_GPIO_H__ -#define PWR_SIG_TAG_GPIO PWR_GPIO_ +#define PWR_SIG_TAG_GPIO PWR_GPIO_ /* * Generate enums for the GPIOs. @@ -21,13 +21,13 @@ enum pwr_sig_gpio { #if HAS_GPIO_SIGNALS -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_GPIO_ENUM) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_GPIO_ENUM) #endif - PWR_SIG_GPIO_COUNT + PWR_SIG_GPIO_COUNT }; -#undef PWR_GPIO_ENUM -#undef TAG_GPIO +#undef PWR_GPIO_ENUM +#undef TAG_GPIO /** * @brief Get the value of the GPIO power signal. -- cgit v1.2.1 From 962a1a0b18ebd347c2473f220d6fd7c2b9d58303 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:58 -0600 Subject: zephyr/projects/nissa/src/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2983811982bbed2baa0c22a07ed9199173b02914 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730788 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/led.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/zephyr/projects/nissa/src/led.c b/zephyr/projects/nissa/src/led.c index 27c78f8051..cd24991722 100644 --- a/zephyr/projects/nissa/src/led.c +++ b/zephyr/projects/nissa/src/led.c @@ -13,20 +13,25 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override void led_set_color_battery(enum ec_led_colors color) { -- cgit v1.2.1 From da528aa23c375fea32fcb6ed8eccdd2981f09811 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:53 -0600 Subject: include/usb_bb.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d60b85dab928d51704b32d88bc0cb2e833aaeb1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730428 Reviewed-by: Jeremy Bettis --- include/usb_bb.h | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/include/usb_bb.h b/include/usb_bb.h index e2303f13e6..c73c6339e1 100644 --- a/include/usb_bb.h +++ b/include/usb_bb.h @@ -17,7 +17,6 @@ #define USB_BB_EP0_PACKET_SIZE 8 #define USB_BB_CAP_DESC_TYPE 0x0d - #define USB_BB_CAPS_SVID_SIZE 4 struct usb_bb_caps_svid_descriptor { uint16_t wSVID; @@ -38,16 +37,14 @@ struct usb_bb_caps_base_descriptor { uint32_t bReserved; /* SBZ */ } __packed; - -#define USB_BB_VCONN_PWRON(x) (x << 15) -#define USB_BB_VCONN_PWR_1W 0 -#define USB_BB_VCONN_PWR_1p5W 1 -#define USB_BB_VCONN_PWR_2W 2 -#define USB_BB_VCONN_PWR_3W 3 -#define USB_BB_VCONN_PWR_4W 4 -#define USB_BB_VCONN_PWR_5W 5 -#define USB_BB_VCONN_PWR_6W 6 +#define USB_BB_VCONN_PWRON(x) (x << 15) +#define USB_BB_VCONN_PWR_1W 0 +#define USB_BB_VCONN_PWR_1p5W 1 +#define USB_BB_VCONN_PWR_2W 2 +#define USB_BB_VCONN_PWR_3W 3 +#define USB_BB_VCONN_PWR_4W 4 +#define USB_BB_VCONN_PWR_5W 5 +#define USB_BB_VCONN_PWR_6W 6 /* Note, 7W (111b) is reserved */ - #endif /* __CROS_EC_USB_BB_H */ -- cgit v1.2.1 From 09c03c5eb339f83de6a49bc361ad71bbb03b17cb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:35:04 -0600 Subject: common/console_output.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44db1efc89ddf01331c84283307b7bfbf42e3ef9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729619 Reviewed-by: Jeremy Bettis --- common/console_output.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/common/console_output.c b/common/console_output.c index 33b1466181..4cd45127c9 100644 --- a/common/console_output.c +++ b/common/console_output.c @@ -27,14 +27,14 @@ static uint32_t channel_mask_saved = CC_DEFAULT; * might also become more important if we have >32 channels - for example, if * we decide to replace enum console_channel with enum module_id. */ -static const char * const channel_names[] = { - #define CONSOLE_CHANNEL(enumeration, string) string, - #include "console_channel.inc" - #undef CONSOLE_CHANNEL +static const char *const channel_names[] = { +#define CONSOLE_CHANNEL(enumeration, string) string, +#include "console_channel.inc" +#undef CONSOLE_CHANNEL }; BUILD_ASSERT(ARRAY_SIZE(channel_names) == CC_CHANNEL_COUNT); /* ensure that we are not silently masking additional channels */ -BUILD_ASSERT(CC_CHANNEL_COUNT <= 8*sizeof(uint32_t)); +BUILD_ASSERT(CC_CHANNEL_COUNT <= 8 * sizeof(uint32_t)); static int console_channel_name_to_index(const char *name) { @@ -178,15 +178,13 @@ static int command_ch(int argc, char **argv) /* Print the list of channels */ ccputs(" # Mask E Channel\n"); for (i = 0; i < CC_CHANNEL_COUNT; i++) { - ccprintf("%2d %08x %c %s\n", - i, CC_MASK(i), + ccprintf("%2d %08x %c %s\n", i, CC_MASK(i), (channel_mask & CC_MASK(i)) ? '*' : ' ', channel_names[i]); cflush(); } return EC_SUCCESS; }; -DECLARE_SAFE_CONSOLE_COMMAND(chan, command_ch, - "[ save | restore | ]", +DECLARE_SAFE_CONSOLE_COMMAND(chan, command_ch, "[ save | restore | ]", "Save, restore, get or set console channel mask"); #endif /* CONFIG_CONSOLE_CHANNEL */ -- cgit v1.2.1 From 0ac4186826f60d8b07eb710796e7c1f9fde42bad Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:44 -0600 Subject: board/coral/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icc62203612896020182fcf83975b9c6e1c2771a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728157 Reviewed-by: Jeremy Bettis --- board/coral/battery.c | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/board/coral/battery.c b/board/coral/battery.c index 8dfb05d631..02dc763664 100644 --- a/board/coral/battery.c +++ b/board/coral/battery.c @@ -19,7 +19,7 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) /* Number of writes needed to invoke battery cutoff command */ #define SHIP_MODE_WRITES 2 @@ -412,7 +412,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT); static inline const struct board_batt_params *board_get_batt_params(void) { return &info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type]; + DEFAULT_BATTERY_TYPE : + board_battery_type]; } /* Get type of the battery connected on the board */ @@ -424,14 +425,16 @@ static int board_get_battery_type(void) if (!battery_manufacturer_name(manu_name, sizeof(manu_name))) { for (i = 0; i < BATTERY_TYPE_COUNT; i++) { if (!strcasecmp(manu_name, - info[i].fuel_gauge.manuf_name)) { + info[i].fuel_gauge.manuf_name)) { if (info[i].fuel_gauge.device_name == NULL) { board_battery_type = i; break; - } else if (!battery_device_name(device_name, - sizeof(device_name))) { + } else if (!battery_device_name( + device_name, + sizeof(device_name))) { if (!strcasecmp(device_name, - info[i].fuel_gauge.device_name)) { + info[i].fuel_gauge + .device_name)) { board_battery_type = i; break; } @@ -496,7 +499,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) /* Do not discharge on AC if the battery is still waking up */ if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - !(curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.status & STATUS_FULLY_CHARGED)) return 0; /* @@ -513,8 +516,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) * and suspend USB charging and DC/DC converter. */ if (!battery_is_cut_off() && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; /* @@ -548,13 +551,13 @@ enum battery_present battery_hw_present(void) return gpio_get_level(GPIO_EC_BATT_PRES_L) ? BP_NO : BP_YES; } - static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* Allow booting now that the battery has woke up */ @@ -595,12 +598,13 @@ static int battery_check_disconnect(void) /* Read the status of charge/discharge FETs */ if (info[board_battery_type].fuel_gauge.fet.mfgacc_support == 1) { rv = sb_read_mfgacc(PARAM_OPERATION_STATUS, - SB_ALT_MANUFACTURER_ACCESS, data, sizeof(data)); + SB_ALT_MANUFACTURER_ACCESS, data, + sizeof(data)); /* Get the lowest 16bits of the OperationStatus() data */ reg = data[2] | data[3] << 8; } else rv = sb_read(info[board_battery_type].fuel_gauge.fet.reg_addr, - ®); + ®); if (rv) return BATTERY_DISCONNECT_ERROR; @@ -650,7 +654,7 @@ enum battery_present battery_is_present(void) * error due to a failed sb_read. */ battery_report_present_timer_started = 0; - } else if (batt_pres == BP_YES && batt_pres_prev == BP_NO && + } else if (batt_pres == BP_YES && batt_pres_prev == BP_NO && !battery_report_present_timer_started) { /* * Wait 1/2 second before reporting present if it was @@ -674,11 +678,10 @@ int board_battery_initialized(void) return battery_hw_present() == batt_pres_prev; } - /* Customs options controllable by host command. */ #define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0) -#define PARAM_LEARN_MODE 0x10001 -#define PARAM_DISCONNECT_STATE 0x10002 +#define PARAM_LEARN_MODE 0x10001 +#define PARAM_DISCONNECT_STATE 0x10002 enum ec_status charger_profile_override_get_param(uint32_t param, uint32_t *value) -- cgit v1.2.1 From 8d9eb8c579146abd46e9f9302122743bcbf21079 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:21 -0600 Subject: builtin/stdint.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia466cfd84e1886e3cce6401b7656b00e4be91d0c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729126 Reviewed-by: Jeremy Bettis --- builtin/stdint.h | 60 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/builtin/stdint.h b/builtin/stdint.h index dedc9de475..87993d8e2d 100644 --- a/builtin/stdint.h +++ b/builtin/stdint.h @@ -6,43 +6,43 @@ #ifndef __CROS_EC_STDINT_H__ #define __CROS_EC_STDINT_H__ -typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed char int8_t; -typedef unsigned short uint16_t; -typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed short int16_t; -typedef unsigned int uint32_t; -typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef signed int int32_t; typedef unsigned long long uint64_t; -typedef signed long long int64_t; +typedef signed long long int64_t; -typedef unsigned int uintptr_t; -typedef int intptr_t; +typedef unsigned int uintptr_t; +typedef int intptr_t; /* uint_leastX_t represents the smallest type available with at least X bits. * uint_fastX_t represents the fastest type available with at least X bits. */ -typedef uint8_t uint_least8_t; -typedef uint16_t uint_least16_t; -typedef uint32_t uint_least32_t; -typedef uint64_t uint_least64_t; - -typedef int8_t int_least8_t; -typedef int16_t int_least16_t; -typedef int32_t int_least32_t; -typedef int64_t int_least64_t; - -typedef uint8_t uint_fast8_t; -typedef uint16_t uint_fast16_t; -typedef uint32_t uint_fast32_t; -typedef uint64_t uint_fast64_t; - -typedef int8_t int_fast8_t; -typedef int16_t int_fast16_t; -typedef int32_t int_fast32_t; -typedef int64_t int_fast64_t; +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; +typedef uint32_t uint_least32_t; +typedef uint64_t uint_least64_t; + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; +typedef int32_t int_least32_t; +typedef int64_t int_least64_t; + +typedef uint8_t uint_fast8_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +typedef uint64_t uint_fast64_t; + +typedef int8_t int_fast8_t; +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef int64_t int_fast64_t; #ifndef UINT8_MAX #define UINT8_MAX (255U) @@ -69,10 +69,10 @@ typedef int64_t int_fast64_t; #endif #ifndef UINT64_C -#define UINT64_C(c) c ## ULL +#define UINT64_C(c) c##ULL #endif #ifndef INT64_C -#define INT64_C(c) c ## LL +#define INT64_C(c) c##LL #endif #ifndef UINT64_MAX -- cgit v1.2.1 From 1d1981649b6e821ff0cbb069dd264d678bfefaf1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:22:47 -0600 Subject: chip/mt_scp/rv32i_common/hrtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaa3fb9567906308bd98a59b746f506506be52434 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729358 Reviewed-by: Jeremy Bettis --- chip/mt_scp/rv32i_common/hrtimer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/mt_scp/rv32i_common/hrtimer.c b/chip/mt_scp/rv32i_common/hrtimer.c index a844527494..9744aecb4b 100644 --- a/chip/mt_scp/rv32i_common/hrtimer.c +++ b/chip/mt_scp/rv32i_common/hrtimer.c @@ -65,8 +65,8 @@ static void timer_set_reset_value(int n, uint32_t reset_value) static void timer_set_clock(int n, uint32_t clock_source) { - SCP_CORE0_TIMER_EN(n) = - (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | clock_source; + SCP_CORE0_TIMER_EN(n) = (SCP_CORE0_TIMER_EN(n) & ~TIMER_CLK_SRC_MASK) | + clock_source; } static void timer_reset(int n) @@ -88,8 +88,8 @@ static uint64_t timer_read_raw_system(void) * sys_high value. */ if (timer_ctrl & TIMER_IRQ_STATUS) - sys_high_adj = sys_high ? (sys_high - 1) - : (TIMER_CLOCK_MHZ - 1); + sys_high_adj = sys_high ? (sys_high - 1) : + (TIMER_CLOCK_MHZ - 1); return OVERFLOW_TICKS - (((uint64_t)sys_high_adj << 32) | SCP_CORE0_TIMER_CUR_VAL(TIMER_SYSTEM)); @@ -159,8 +159,8 @@ uint32_t __hw_clock_source_read(void) uint32_t __hw_clock_event_get(void) { - return (timer_read_raw_event() + timer_read_raw_system()) - / TIMER_CLOCK_MHZ; + return (timer_read_raw_event() + timer_read_raw_system()) / + TIMER_CLOCK_MHZ; } void __hw_clock_event_clear(void) -- cgit v1.2.1 From 230149fcf3ed30a3e5e32a8c16e168775271042b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:46 -0600 Subject: board/zinger/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I82884b5dbf0227a57cb34bac6fb8c321c4ba71dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729139 Reviewed-by: Jeremy Bettis --- board/zinger/board.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/zinger/board.c b/board/zinger/board.c index f1249d6917..2be1e3e544 100644 --- a/board/zinger/board.c +++ b/board/zinger/board.c @@ -21,8 +21,8 @@ static uint32_t rsa_workbuf[3 * RSANUMWORDS]; /* RW firmware reset vector */ -static uint32_t * const rw_rst = - (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE+CONFIG_RW_MEM_OFF+4); +static uint32_t *const rw_rst = + (uint32_t *)(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF + 4); /* External interrupt EXTINT7 for external comparator on PA7 */ static void pd_rx_interrupt(void) @@ -57,8 +57,8 @@ static int check_rw_valid(void *rw_hash) return 0; good = rsa_verify((const struct rsa_public_key *)CONFIG_RO_PUBKEY_ADDR, - (const uint8_t *)CONFIG_RW_SIG_ADDR, - rw_hash, rsa_workbuf); + (const uint8_t *)CONFIG_RW_SIG_ADDR, rw_hash, + rsa_workbuf); if (!good) { debug_printf("RSA FAILED\n"); pd_log_event(PD_EVENT_ACC_RW_FAIL, 0, 0, NULL); @@ -75,8 +75,7 @@ int main(void) void *rw_hash; hardware_init(); - debug_printf("%s started\n", - is_ro_mode() ? "RO" : "RW"); + debug_printf("%s started\n", is_ro_mode() ? "RO" : "RW"); /* the RO partition protection is not enabled : do it */ if (!flash_physical_is_permanently_protected()) -- cgit v1.2.1 From 4478d66375fd9ad1f0cfa791d876febef02aba84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:29 -0600 Subject: chip/ish/watchdog.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6eddd753bc1708c944f013bc71b3fb7abf1e48ae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729191 Reviewed-by: Jeremy Bettis --- chip/ish/watchdog.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/chip/ish/watchdog.c b/chip/ish/watchdog.c index bf78f49312..81ede92d07 100644 --- a/chip/ish/watchdog.c +++ b/chip/ish/watchdog.c @@ -29,8 +29,8 @@ #include "watchdog.h" /* Units are hundreds of milliseconds */ -#define WDT_T1_PERIOD (100) /* 10 seconds */ -#define WDT_T2_PERIOD (10) /* 1 second */ +#define WDT_T1_PERIOD (100) /* 10 seconds */ +#define WDT_T2_PERIOD (10) /* 1 second */ int watchdog_init(void) { @@ -45,9 +45,8 @@ int watchdog_init(void) CCU_WDT_CD = WDT_CLOCK_HZ / 10; /* 10 Hz => 100 ms period */ /* Enable the watchdog timer and set initial T1/T2 values */ - WDT_CONTROL = WDT_CONTROL_ENABLE_BIT - | (WDT_T2_PERIOD << 8) - | WDT_T1_PERIOD; + WDT_CONTROL = WDT_CONTROL_ENABLE_BIT | (WDT_T2_PERIOD << 8) | + WDT_T1_PERIOD; task_enable_irq(ISH_WDT_IRQ); -- cgit v1.2.1 From 96b097c17d256ee1e88d29948d61d5a8200acbb8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:24 -0600 Subject: board/servo_v4p1/usb_tc_snk_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I35b1a225310e75dcea8d42dfe0d97569a0313ac8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728937 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_tc_snk_sm.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/servo_v4p1/usb_tc_snk_sm.c b/board/servo_v4p1/usb_tc_snk_sm.c index 95586943bf..5b3f2757e4 100644 --- a/board/servo_v4p1/usb_tc_snk_sm.c +++ b/board/servo_v4p1/usb_tc_snk_sm.c @@ -14,15 +14,15 @@ #include "usb_sm.h" #include "usb_tc_sm.h" -#define EVT_TIMEOUT_NEVER (-1) -#define EVT_TIMEOUT_5MS (5 * MSEC) +#define EVT_TIMEOUT_NEVER (-1) +#define EVT_TIMEOUT_5MS (5 * MSEC) /* * USB Type-C Sink * See Figure 4-13 in Release 1.4 of USB Type-C Spec. */ -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* Type-C Layer Flags */ @@ -36,9 +36,9 @@ enum usb_tc_state { static const struct usb_state tc_states[]; /* TypeC Power strings */ -static const char * const pwr2_5_str = "5V/0.5A"; -static const char * const pwr7_5_str = "5V/1.5A"; -static const char * const pwr15_str = "5V/3A"; +static const char *const pwr2_5_str = "5V/0.5A"; +static const char *const pwr7_5_str = "5V/1.5A"; +static const char *const pwr15_str = "5V/3A"; static struct type_c { /* state machine context */ @@ -101,8 +101,8 @@ static void print_alt_power(void) char const *pwr; cc = tc.polarity ? tc.cc2 : tc.cc1; - if (cc == TYPEC_CC_VOLT_OPEN || - cc == TYPEC_CC_VOLT_RA || cc == TYPEC_CC_VOLT_RD) { + if (cc == TYPEC_CC_VOLT_OPEN || cc == TYPEC_CC_VOLT_RA || + cc == TYPEC_CC_VOLT_RD) { /* Supply removed or not detected */ return; } -- cgit v1.2.1 From f874b7358478fb9496f6a855ee5917c7504b780a Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 29 Jun 2022 23:23:32 +0000 Subject: nvidia_gpu: Notify AP of GPU over temperature This patch adds nvidia_gpu_over_temp, which sends a host event to the AP and sets a flag in a shared memory. BUG=b:216485035 BRANCH=None TEST=make run-nvidia_gpu Signed-off-by: Daisuke Nojiri Change-Id: I774eac765f40fd4cef4b853781bcae7b8ae26d96 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735918 Reviewed-by: Tim Wawrzynczak --- driver/nvidia_gpu.c | 21 ++++++++++++++------- driver/nvidia_gpu.h | 7 +++++++ include/ec_commands.h | 8 ++++++++ test/nvidia_gpu.c | 14 ++++++++++++++ 4 files changed, 43 insertions(+), 7 deletions(-) diff --git a/driver/nvidia_gpu.c b/driver/nvidia_gpu.c index 3737b4ecd0..f549a03448 100644 --- a/driver/nvidia_gpu.c +++ b/driver/nvidia_gpu.c @@ -22,12 +22,6 @@ #define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ## args) #define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ## args) -/* - * BIT0~2: D-Notify level (0:D1, ... 4:D5) - * note: may need a bit for disabling dynamic boost. - */ -#define MEMMAP_D_NOTIFY_MASK GENMASK(2, 0) - test_export_static enum d_notify_level d_notify_level = D_NOTIFY_1; test_export_static bool policy_initialized = false; test_export_static const struct d_notify_policy *d_notify_policy = NULL; @@ -40,6 +34,18 @@ void nvidia_gpu_init_policy(const struct d_notify_policy *policy) } } +void nvidia_gpu_over_temp(int assert) +{ + uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU); + + if (assert) + *memmap_gpu |= EC_MEMMAP_GPU_OVERT_BIT; + else + *memmap_gpu &= ~EC_MEMMAP_GPU_OVERT_BIT; + + host_set_single_event(EC_HOST_EVENT_GPU); +} + static void set_d_notify_level(enum d_notify_level level) { uint8_t *memmap_gpu = (uint8_t *)host_get_memmap(EC_MEMMAP_GPU); @@ -48,7 +54,8 @@ static void set_d_notify_level(enum d_notify_level level) return; d_notify_level = level; - *memmap_gpu = (*memmap_gpu & ~MEMMAP_D_NOTIFY_MASK) | d_notify_level; + *memmap_gpu = (*memmap_gpu & ~EC_MEMMAP_GPU_D_NOTIFY_MASK) + | d_notify_level; host_set_single_event(EC_HOST_EVENT_GPU); CPRINTS("Set D-notify level to D%c", ('1' + (int)d_notify_level)); } diff --git a/driver/nvidia_gpu.h b/driver/nvidia_gpu.h index 267f6643f5..8991ec75c1 100644 --- a/driver/nvidia_gpu.h +++ b/driver/nvidia_gpu.h @@ -56,4 +56,11 @@ struct d_notify_policy { void nvidia_gpu_init_policy(const struct d_notify_policy *policies); +/** + * Notify the host of assertion or deassertion of GPU over temperature. + * + * @param assert True for assert. False for deassert. + */ +void nvidia_gpu_over_temp(int assert); + #endif /* DRIVER_NVIDIA_GPU_H */ diff --git a/include/ec_commands.h b/include/ec_commands.h index bddf95ca32..0c28b11dba 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -172,6 +172,14 @@ extern "C" { #define EC_MEMMAP_GPU 0xa6 /* GPU-specific, 8 bits */ /* Unused 0xa7 - 0xdf */ +/* + * Bit fields for EC_MEMMAP_GPU + * 0:2: D-Notify level (0:D1, ... 4:D5) + * 3: Over temperature + */ +#define EC_MEMMAP_GPU_D_NOTIFY_MASK GENMASK(2, 0) +#define EC_MEMMAP_GPU_OVERT_BIT BIT(3) + /* * ACPI is unable to access memory mapped data at or above this offset due to * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe diff --git a/test/nvidia_gpu.c b/test/nvidia_gpu.c index c408fa429e..03f9677578 100644 --- a/test/nvidia_gpu.c +++ b/test/nvidia_gpu.c @@ -185,6 +185,19 @@ static int test_ac_plug(void) return EC_SUCCESS; } +static int test_overt(void) +{ + nvidia_gpu_over_temp(1); + TEST_ASSERT(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + + nvidia_gpu_over_temp(0); + TEST_ASSERT(!(*memmap_gpu & EC_MEMMAP_GPU_OVERT_BIT)); + TEST_ASSERT(host_is_event_set(EC_HOST_EVENT_GPU)); + + return EC_SUCCESS; +} + static void board_gpu_init(void) { nvidia_gpu_init_policy(d_notify_policies); @@ -200,5 +213,6 @@ void run_test(int argc, char **argv) RUN_TEST(test_startup); RUN_TEST(test_ac_unplug); RUN_TEST(test_ac_plug); + RUN_TEST(test_overt); test_print_result(); } -- cgit v1.2.1 From 36b2c00b57094b66353d4c8ee7ec4b481bebe7db Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 29 Jun 2022 23:23:32 +0000 Subject: Agah: Enable GPU over temperature notification This patch makes the EC trigger GPU over temperature notification when GPU_OVERT_ODL is asserted. BUG=b:216485035 BRANCH=None TEST=None Signed-off-by: Daisuke Nojiri Change-Id: I5b52166fa7d4bea233502ed6b67a423512f8aba5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735919 Reviewed-by: Tim Wawrzynczak --- board/agah/board.c | 5 +++++ board/agah/board.h | 3 +++ board/agah/gpio.inc | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/board/agah/board.c b/board/agah/board.c index e4d48507ee..f37e1e504f 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -114,3 +114,8 @@ static int cc_blockseq(int argc, char *argv[]) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(blockseq, cc_blockseq, "[on/off]", NULL); + +void gpu_overt_interrupt(enum gpio_signal signal) +{ + nvidia_gpu_over_temp(gpio_get_level(signal)); +} diff --git a/board/agah/board.h b/board/agah/board.h index d03aba2580..3b9aec23ec 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -223,6 +223,9 @@ void board_power_interrupt(enum gpio_signal signal); /* IRQ for BJ plug/unplug. */ void bj_present_interrupt(enum gpio_signal signal); +/* IRQ for over temperature. */ +void gpu_overt_interrupt(enum gpio_signal signal); + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index 7f38c87057..f382863952 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -27,6 +27,7 @@ GPIO_INT(USB_C2_BC12_INT_ODL, PIN(8, 3), GPIO_INT_FALLING, bc12_inter GPIO_INT(USB_C2_TCPC_INT_ODL, PIN(A, 7), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(USB_C2_PPC_INT_ODL, PIN(7, 0), GPIO_INT_FALLING, ppc_interrupt) GPIO_INT(BJ_ADP_PRESENT_ODL, PIN(5, 6), GPIO_INT_BOTH | GPIO_PULL_UP, bj_present_interrupt) +GPIO_INT(GPU_OVERT_ODL, PIN(5, 0), GPIO_INT_BOTH, gpu_overt_interrupt) /* USED GPIOs: */ GPIO(CCD_MODE_ODL, PIN(E, 5), GPIO_INPUT) @@ -128,7 +129,6 @@ UNUSED(PIN(6, 6)) /* GPIO66 */ UNUSED(PIN(5, 7)) /* GPIO57/SER_IRQ/ESPI_ALERT_L */ UNUSED(PIN(8, 1)) /* GPIO81 */ UNUSED(PIN(7, 3)) /* GPIO73 */ -UNUSED(PIN(5, 0)) /* GPIO50 */ UNUSED(PIN(6, 0)) /* GPIO60 */ UNUSED(PIN(C, 2)) /* GPIOC2 */ UNUSED(PIN(E, 1)) /* GPIOE1 */ -- cgit v1.2.1 From 8cda1ea81a6a6d8df3c11e1909c5b8004f6924e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:15 -0600 Subject: board/gimble/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib5876e5043250f8a848a7da242d765af91bbb2db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728415 Reviewed-by: Jeremy Bettis --- board/gimble/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/gimble/keyboard.c b/board/gimble/keyboard.c index cec70e3d97..97cc41cee9 100644 --- a/board/gimble/keyboard.c +++ b/board/gimble/keyboard.c @@ -44,8 +44,8 @@ static const struct ec_response_keybd_config gimble_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &gimble_kb; } -- cgit v1.2.1 From f424e6bb307cf89b485f17e12cdfb0ad3db2f58a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:46 -0600 Subject: board/kukui/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I408515abd10c17f82f696161b01fb8ed60f7b0e1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728591 Reviewed-by: Jeremy Bettis --- board/kukui/board.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/board/kukui/board.h b/board/kukui/board.h index 8cedd195e1..91ccd000f9 100644 --- a/board/kukui/board.h +++ b/board/kukui/board.h @@ -37,9 +37,9 @@ /* Battery */ #ifdef BOARD_KRANE -#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ +#define BATTERY_DESIRED_CHARGING_CURRENT 3500 /* mA */ #else -#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */ +#define BATTERY_DESIRED_CHARGING_CURRENT 2000 /* mA */ #endif /* BOARD_KRANE */ #ifdef BOARD_KRANE @@ -79,19 +79,18 @@ /* Camera VSYNC */ #define CONFIG_SYNC #define CONFIG_SYNC_COMMAND -#define CONFIG_SYNC_INT_EVENT \ - TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) +#define CONFIG_SYNC_INT_EVENT TASK_EVENT_MOTION_SENSOR_INTERRUPT(VSYNC) #endif /* SECTION_IS_RW */ /* I2C ports */ -#define I2C_PORT_CHARGER 0 -#define I2C_PORT_TCPC0 0 -#define I2C_PORT_USB_MUX 0 -#define I2C_PORT_BATTERY 1 +#define I2C_PORT_CHARGER 0 +#define I2C_PORT_TCPC0 0 +#define I2C_PORT_USB_MUX 0 +#define I2C_PORT_BATTERY 1 #define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY -#define I2C_PORT_ACCEL 1 -#define I2C_PORT_BC12 1 -#define I2C_PORT_ALS 1 +#define I2C_PORT_ACCEL 1 +#define I2C_PORT_BC12 1 +#define I2C_PORT_ALS 1 /* Route sbs host requests to virtual battery driver */ #define VIRTUAL_BATTERY_ADDR_FLAGS 0x0B -- cgit v1.2.1 From cbbb80b5b92240ccf06c8e2a8d60270fae4f60e7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:45 -0600 Subject: board/reef_it8320/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I83f6cb879e28debc3e82204c4ba019fd8a65abf4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728884 Reviewed-by: Jeremy Bettis --- board/reef_it8320/led.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/board/reef_it8320/led.c b/board/reef_it8320/led.c index a1ea5964a8..54c6980a6e 100644 --- a/board/reef_it8320/led.c +++ b/board/reef_it8320/led.c @@ -27,8 +27,7 @@ #define LED_ON_1SEC_TICKS 1 #define LED_ON_2SECS_TICKS 2 -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -36,7 +35,7 @@ enum led_color { LED_OFF = 0, LED_BLUE, LED_AMBER, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static int led_set_color_battery(enum led_color color) @@ -113,16 +112,19 @@ static void led_set_battery(void) } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Blink once every four seconds. */ led_set_color_battery( - (suspend_ticks % LED_TOTAL_4SECS_TICKS) - < LED_ON_1SEC_TICKS ? LED_AMBER : LED_OFF); + (suspend_ticks % LED_TOTAL_4SECS_TICKS) < + LED_ON_1SEC_TICKS ? + LED_AMBER : + LED_OFF); } else { led_set_color_battery(LED_OFF); } break; case PWR_STATE_ERROR: - led_set_color_battery( - (battery_ticks % LED_TOTAL_2SECS_TICKS < - LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF); + led_set_color_battery((battery_ticks % LED_TOTAL_2SECS_TICKS < + LED_ON_1SEC_TICKS) ? + LED_AMBER : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: led_set_color_battery(LED_BLUE); @@ -131,7 +133,9 @@ static void led_set_battery(void) if (charge_get_flags() & CHARGE_FLAG_FORCE_IDLE) led_set_color_battery( (battery_ticks % LED_TOTAL_4SECS_TICKS < - LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE); + LED_ON_2SECS_TICKS) ? + LED_AMBER : + LED_BLUE); else led_set_color_battery(LED_BLUE); break; -- cgit v1.2.1 From 251da314493a92c6f970fe90259ddcd69edabc8a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:48 -0600 Subject: board/akemi/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1be458c98d0bb9dad2fb2b9ef309fefe9b842e00 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727979 Reviewed-by: Jeremy Bettis --- board/akemi/led.c | 51 ++++++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/board/akemi/led.c b/board/akemi/led.c index 80d52f7cc2..91b7d54aaf 100644 --- a/board/akemi/led.c +++ b/board/akemi/led.c @@ -19,33 +19,35 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 3 * LED_ONE_SEC}, - {LED_OFF, 0.5 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{LED_OFF, LED_INDEFINITE} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 3 * LED_ONE_SEC }, + { LED_OFF, 0.5 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { LED_OFF, LED_INDEFINITE } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_POWER_LED, - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED, + EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); @@ -58,7 +60,6 @@ __override void led_set_color_power(enum ec_led_colors color) gpio_set_level(GPIO_LED_3_L, LED_OFF_LVL); } - __override void led_set_color_battery(enum ec_led_colors color) { switch (color) { -- cgit v1.2.1 From defacf110d36e08b045c5e7473d633562a950a33 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:40 -0600 Subject: driver/ioexpander/pca9534.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9c976fdef4ead573a1dd15a6357a2bcadf8e46c0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730008 Reviewed-by: Jeremy Bettis --- driver/ioexpander/pca9534.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/driver/ioexpander/pca9534.h b/driver/ioexpander/pca9534.h index 0fec577576..96aa7c0bcb 100644 --- a/driver/ioexpander/pca9534.h +++ b/driver/ioexpander/pca9534.h @@ -8,12 +8,12 @@ #ifndef __CROS_EC_IOEXPANDER_PCA9534_H #define __CROS_EC_IOEXPANDER_PCA9534_H -#define PCA9534_REG_INPUT 0x0 +#define PCA9534_REG_INPUT 0x0 #define PCA9534_REG_OUTPUT 0x1 #define PCA9534_REG_CONFIG 0x3 #define PCA9534_OUTPUT 0 -#define PCA9534_INPUT 1 +#define PCA9534_INPUT 1 /* * Get input level. Note that this reflects the actual level on the @@ -26,8 +26,8 @@ * * @return EC_SUCCESS, or EC_ERROR_* on error. */ -int pca9534_get_level(const int port, const uint16_t addr_flags, - int pin, int *level); +int pca9534_get_level(const int port, const uint16_t addr_flags, int pin, + int *level); /* * Set output level. This function has no effect if the pin is @@ -40,8 +40,8 @@ int pca9534_get_level(const int port, const uint16_t addr_flags, * * @return EC_SUCCESS, or EC_ERROR_* on error. */ -int pca9534_set_level(const int port, const uint16_t addr_flags, - int pin, int level); +int pca9534_set_level(const int port, const uint16_t addr_flags, int pin, + int level); /* * Config a pin as input or output. @@ -53,7 +53,7 @@ int pca9534_set_level(const int port, const uint16_t addr_flags, * * @return EC_SUCCESS, or EC_ERROR_* on error. */ -int pca9534_config_pin(const int port, const uint16_t addr_flags, - int pin, int is_input); +int pca9534_config_pin(const int port, const uint16_t addr_flags, int pin, + int is_input); -#endif /* __CROS_EC_IOEXPANDER_PCA9534_H */ +#endif /* __CROS_EC_IOEXPANDER_PCA9534_H */ -- cgit v1.2.1 From fa86d06e469760fa7340f50c6ff0e4275c4f3a5d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:56:20 -0600 Subject: driver/temp_sensor/oti502.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id92fb5f3fb3bba17cda290e827a59b8f41013973 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730120 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/oti502.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/driver/temp_sensor/oti502.c b/driver/temp_sensor/oti502.c index b58d1c3e96..f517a41073 100644 --- a/driver/temp_sensor/oti502.c +++ b/driver/temp_sensor/oti502.c @@ -12,13 +12,13 @@ #include "hooks.h" #include "util.h" -static int temp_val_ambient; /* Ambient is chip temperature*/ -static int temp_val_object; /* Object is IR temperature */ +static int temp_val_ambient; /* Ambient is chip temperature*/ +static int temp_val_object; /* Object is IR temperature */ static int oti502_read_block(const int offset, uint8_t *data, int len) { - return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS, - offset, data, len); + return i2c_read_block(I2C_PORT_THERMAL, OTI502_I2C_ADDR_FLAGS, offset, + data, len); } int oti502_get_val(int idx, int *temp_ptr) -- cgit v1.2.1 From fb60c03ede29746734c6fb6bce5153bf728fe9db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:34 -0600 Subject: common/usb_pd_flags.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff042c5de96e9294331fc9e5d6f2fe8a55af534c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729773 Reviewed-by: Jeremy Bettis --- common/usb_pd_flags.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/usb_pd_flags.c b/common/usb_pd_flags.c index 073637e05b..a1a68d627f 100644 --- a/common/usb_pd_flags.c +++ b/common/usb_pd_flags.c @@ -17,7 +17,7 @@ BUILD_ASSERT(sizeof(usb_pd_flags) == sizeof(uint32_t)); enum usb_pd_vbus_detect get_usb_pd_vbus_detect(void) { if (IS_ENABLED(CONFIG_USB_PD_RUNTIME_FLAGS)) - return (enum usb_pd_vbus_detect) usb_pd_flags.vbus_detect; + return (enum usb_pd_vbus_detect)usb_pd_flags.vbus_detect; else if (IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC)) return (enum usb_pd_vbus_detect)USB_PD_VBUS_DETECT_TCPC; else if (IS_ENABLED(CONFIG_USD_PD_VBUS_DETECT_GPIO)) -- cgit v1.2.1 From dfa8498764e5710529a86ab02abd5b2c39581711 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:50 -0600 Subject: zephyr/projects/trogdor/lazor/src/power.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I79feff37c6e44aafec9202064c185c2597500f91 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730807 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/trogdor/lazor/src/power.c b/zephyr/projects/trogdor/lazor/src/power.c index ee4e1b3b8f..beca598750 100644 --- a/zephyr/projects/trogdor/lazor/src/power.c +++ b/zephyr/projects/trogdor/lazor/src/power.c @@ -51,7 +51,7 @@ static int board_power_handler_init(const struct device *unused) /* Setup a suspend/resume callback */ ap_power_ev_init_callback(&cb, board_power_change, AP_POWER_PRE_INIT | - AP_POWER_SHUTDOWN_COMPLETE); + AP_POWER_SHUTDOWN_COMPLETE); ap_power_ev_add_callback(&cb); return 0; } -- cgit v1.2.1 From b4992a36e1465abab4ebbe5d7da1e2aec02aa886 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:37:22 -0600 Subject: common/lightbar.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If183bc30f997ebe667548b8ffac94e1cd0962265 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729663 Reviewed-by: Jeremy Bettis --- common/lightbar.c | 317 +++++++++++++++++++++++------------------------------- 1 file changed, 132 insertions(+), 185 deletions(-) diff --git a/common/lightbar.c b/common/lightbar.c index f80287941d..8a2e1f32d9 100644 --- a/common/lightbar.c +++ b/common/lightbar.c @@ -33,11 +33,11 @@ * optional features in the current version should be marked with flags. */ #define LIGHTBAR_IMPLEMENTATION_VERSION 1 -#define LIGHTBAR_IMPLEMENTATION_FLAGS 0 +#define LIGHTBAR_IMPLEMENTATION_FLAGS 0 /* Console output macros */ #define CPUTS(outstr) cputs(CC_LIGHTBAR, outstr) -#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LIGHTBAR, format, ##args) #define FP_SCALE 10000 @@ -61,10 +61,10 @@ static struct p_state { int battery_is_power_on_prevented; /* Pattern variables for state S0. */ - uint16_t w0; /* primary phase */ - uint8_t ramp; /* ramp-in for S3->S0 */ + uint16_t w0; /* primary phase */ + uint8_t ramp; /* ramp-in for S3->S0 */ - uint8_t _pad0; /* next item is __packed */ + uint8_t _pad0; /* next item is __packed */ /* Tweakable parameters. */ union { @@ -162,7 +162,7 @@ static const struct lightbar_params_v1 default_params = { }, }; -#define LB_SYSJUMP_TAG 0x4c42 /* "LB" */ +#define LB_SYSJUMP_TAG 0x4c42 /* "LB" */ static void lightbar_preserve_state(void) { system_add_jump_tag(LB_SYSJUMP_TAG, 0, sizeof(st), &st); @@ -177,10 +177,8 @@ static void lightbar_restore_state(void) old_state = system_get_jump_tag(LB_SYSJUMP_TAG, 0, &size); if (old_state && size == sizeof(st)) { memcpy(&st, old_state, size); - CPRINTS("LB state restored: %d %d - %d %d/%d", - st.cur_seq, st.prev_seq, - st.battery_is_charging, - st.battery_percent, + CPRINTS("LB state restored: %d %d - %d %d/%d", st.cur_seq, + st.prev_seq, st.battery_is_charging, st.battery_percent, st.battery_level); } else { st.cur_seq = st.prev_seq = LIGHTBAR_S5; @@ -234,7 +232,7 @@ test_export_static int lux_level_to_google_color(const int lux) } /* See if we need to decrease brightness */ - for (i = google_color_id; i < lb_brightness_levels_count ; i++) + for (i = google_color_id; i < lb_brightness_levels_count; i++) if (lux >= lb_brightness_levels[i].lux_down) break; if (i > google_color_id) { @@ -242,7 +240,7 @@ test_export_static int lux_level_to_google_color(const int lux) return 1; } /* See if we need to increase brightness */ - for (i = google_color_id; i > 0; i--) + for (i = google_color_id; i > 0; i--) if (lux < lb_brightness_levels[i - 1].lux_up) break; if (i < google_color_id) { @@ -276,8 +274,8 @@ static int get_battery_level(void) /* Use some hysteresis to avoid flickering */ if (bl < st.battery_level || - (bl > st.battery_level - && pct >= (st.p.battery_threshold[st.battery_level] + 1))) { + (bl > st.battery_level && + pct >= (st.p.battery_threshold[st.battery_level] + 1))) { st.battery_level = bl; change = 1; } @@ -294,7 +292,7 @@ static int get_battery_level(void) */ if (pwm_get_enabled(PWM_CH_KBLIGHT)) { pct = pwm_get_duty(PWM_CH_KBLIGHT); - pct = (255 * pct) / 100; /* 00 - FF */ + pct = (255 * pct) / 100; /* 00 - FF */ if (pct > st.p.bright_bl_on_max[st.battery_is_charging]) pct = st.p.bright_bl_on_max[st.battery_is_charging]; else if (pct < st.p.bright_bl_on_min[st.battery_is_charging]) @@ -350,8 +348,7 @@ void demo_is_charging(int ischarge) return; st.battery_is_charging = ischarge; - CPRINTS("LB demo: battery_is_charging=%d", - st.battery_is_charging); + CPRINTS("LB demo: battery_is_charging=%d", st.battery_is_charging); } /* Bright/Dim keys */ @@ -409,7 +406,7 @@ static inline int cycle_010(uint8_t i) index = i & 0x3; return _ramp_table[bucket] + - ((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2); + ((_ramp_table[bucket + 1] - _ramp_table[bucket]) * index >> 2); } /******************************************************************************/ @@ -421,12 +418,12 @@ static uint32_t pending_msg; #define PENDING_MSG TASK_EVENT_CUSTOM_BIT(0) /* Interruptible delay. */ -#define WAIT_OR_RET(A) \ - do { \ - uint32_t msg = task_wait_event(A); \ - uint32_t p_msg = pending_msg; \ - if (msg & PENDING_MSG && p_msg != st.cur_seq) \ - return p_msg; \ +#define WAIT_OR_RET(A) \ + do { \ + uint32_t msg = task_wait_event(A); \ + uint32_t p_msg = pending_msg; \ + if (msg & PENDING_MSG && p_msg != st.cur_seq) \ + return p_msg; \ } while (0) /******************************************************************************/ @@ -501,7 +498,7 @@ static uint32_t sequence_S3S0(void) } /* Initial conditions */ - st.w0 = -256; /* start cycle_npn() quietly */ + st.w0 = -256; /* start cycle_npn() quietly */ st.ramp = 0; /* Ready for S0 */ @@ -583,7 +580,7 @@ static uint32_t sequence_S0(void) return 0; } -#else /* just simple google colors */ +#else /* just simple google colors */ static uint32_t sequence_S0(void) { @@ -711,7 +708,6 @@ static uint32_t sequence_S3(void) return 0; } - /* CPU is powering up. We generally boot fast enough that we don't have time * to do anything interesting in the S3 state, but go straight on to S0. */ static uint32_t sequence_S5S3(void) @@ -817,12 +813,10 @@ static uint32_t sequence_STOP(void) do { msg = task_wait_event(-1); CPRINTS("LB %s() got pending_msg %d", __func__, pending_msg); - } while (msg != PENDING_MSG || ( - pending_msg != LIGHTBAR_RUN && - pending_msg != LIGHTBAR_S0S3 && - pending_msg != LIGHTBAR_S3 && - pending_msg != LIGHTBAR_S3S5 && - pending_msg != LIGHTBAR_S5)); + } while (msg != PENDING_MSG || + (pending_msg != LIGHTBAR_RUN && pending_msg != LIGHTBAR_S0S3 && + pending_msg != LIGHTBAR_S3 && pending_msg != LIGHTBAR_S3S5 && + pending_msg != LIGHTBAR_S5)); return 0; } @@ -856,73 +850,47 @@ static const struct { unsigned int delay; } konami[] = { - {1, 0xff, 0xff, 0x00, 0}, - {2, 0xff, 0xff, 0x00, 100000}, - {1, 0x00, 0x00, 0x00, 0}, - {2, 0x00, 0x00, 0x00, 100000}, - - {1, 0xff, 0xff, 0x00, 0}, - {2, 0xff, 0xff, 0x00, 100000}, - {1, 0x00, 0x00, 0x00, 0}, - {2, 0x00, 0x00, 0x00, 100000}, - - {0, 0x00, 0x00, 0xff, 0}, - {3, 0x00, 0x00, 0xff, 100000}, - {0, 0x00, 0x00, 0x00, 0}, - {3, 0x00, 0x00, 0x00, 100000}, - - {0, 0x00, 0x00, 0xff, 0}, - {3, 0x00, 0x00, 0xff, 100000}, - {0, 0x00, 0x00, 0x00, 0}, - {3, 0x00, 0x00, 0x00, 100000}, - - {0, 0xff, 0x00, 0x00, 0}, - {1, 0xff, 0x00, 0x00, 100000}, - {0, 0x00, 0x00, 0x00, 0}, - {1, 0x00, 0x00, 0x00, 100000}, - - {2, 0x00, 0xff, 0x00, 0}, - {3, 0x00, 0xff, 0x00, 100000}, - {2, 0x00, 0x00, 0x00, 0}, - {3, 0x00, 0x00, 0x00, 100000}, - - {0, 0xff, 0x00, 0x00, 0}, - {1, 0xff, 0x00, 0x00, 100000}, - {0, 0x00, 0x00, 0x00, 0}, - {1, 0x00, 0x00, 0x00, 100000}, - - {2, 0x00, 0xff, 0x00, 0}, - {3, 0x00, 0xff, 0x00, 100000}, - {2, 0x00, 0x00, 0x00, 0}, - {3, 0x00, 0x00, 0x00, 100000}, - - {0, 0x00, 0xff, 0xff, 0}, - {2, 0x00, 0xff, 0xff, 100000}, - {0, 0x00, 0x00, 0x00, 0}, - {2, 0x00, 0x00, 0x00, 150000}, - - {1, 0xff, 0x00, 0xff, 0}, - {3, 0xff, 0x00, 0xff, 100000}, - {1, 0x00, 0x00, 0x00, 0}, - {3, 0x00, 0x00, 0x00, 250000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, - - {4, 0xff, 0xff, 0xff, 100000}, - {4, 0x00, 0x00, 0x00, 100000}, + { 1, 0xff, 0xff, 0x00, 0 }, { 2, 0xff, 0xff, 0x00, 100000 }, + { 1, 0x00, 0x00, 0x00, 0 }, { 2, 0x00, 0x00, 0x00, 100000 }, + + { 1, 0xff, 0xff, 0x00, 0 }, { 2, 0xff, 0xff, 0x00, 100000 }, + { 1, 0x00, 0x00, 0x00, 0 }, { 2, 0x00, 0x00, 0x00, 100000 }, + + { 0, 0x00, 0x00, 0xff, 0 }, { 3, 0x00, 0x00, 0xff, 100000 }, + { 0, 0x00, 0x00, 0x00, 0 }, { 3, 0x00, 0x00, 0x00, 100000 }, + + { 0, 0x00, 0x00, 0xff, 0 }, { 3, 0x00, 0x00, 0xff, 100000 }, + { 0, 0x00, 0x00, 0x00, 0 }, { 3, 0x00, 0x00, 0x00, 100000 }, + + { 0, 0xff, 0x00, 0x00, 0 }, { 1, 0xff, 0x00, 0x00, 100000 }, + { 0, 0x00, 0x00, 0x00, 0 }, { 1, 0x00, 0x00, 0x00, 100000 }, + + { 2, 0x00, 0xff, 0x00, 0 }, { 3, 0x00, 0xff, 0x00, 100000 }, + { 2, 0x00, 0x00, 0x00, 0 }, { 3, 0x00, 0x00, 0x00, 100000 }, + + { 0, 0xff, 0x00, 0x00, 0 }, { 1, 0xff, 0x00, 0x00, 100000 }, + { 0, 0x00, 0x00, 0x00, 0 }, { 1, 0x00, 0x00, 0x00, 100000 }, + + { 2, 0x00, 0xff, 0x00, 0 }, { 3, 0x00, 0xff, 0x00, 100000 }, + { 2, 0x00, 0x00, 0x00, 0 }, { 3, 0x00, 0x00, 0x00, 100000 }, + + { 0, 0x00, 0xff, 0xff, 0 }, { 2, 0x00, 0xff, 0xff, 100000 }, + { 0, 0x00, 0x00, 0x00, 0 }, { 2, 0x00, 0x00, 0x00, 150000 }, + + { 1, 0xff, 0x00, 0xff, 0 }, { 3, 0xff, 0x00, 0xff, 100000 }, + { 1, 0x00, 0x00, 0x00, 0 }, { 3, 0x00, 0x00, 0x00, 250000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, + + { 4, 0xff, 0xff, 0xff, 100000 }, { 4, 0x00, 0x00, 0x00, 100000 }, }; static uint32_t sequence_KONAMI_inner(void) @@ -930,8 +898,8 @@ static uint32_t sequence_KONAMI_inner(void) int i; for (i = 0; i < ARRAY_SIZE(konami); i++) { - lb_set_rgb(konami[i].led, - konami[i].r, konami[i].g, konami[i].b); + lb_set_rgb(konami[i].led, konami[i].r, konami[i].g, + konami[i].b); if (konami[i].delay) WAIT_OR_RET(konami[i].delay); } @@ -961,7 +929,7 @@ static int range(int val, int min, int ofs) { if (val <= min) return 0; - if (val >= min+ofs) + if (val >= min + ofs) return FP_SCALE; return (val - min) * FP_SCALE / ofs; } @@ -977,7 +945,7 @@ static uint32_t sequence_TAP_inner(int dir) uint32_t elapsed_time = 0; int i, l, ci, max_led; int f_osc, f_mult; - int gi, gr, gate[NUM_LEDS] = {0, 0, 0, 0}; + int gi, gr, gate[NUM_LEDS] = { 0, 0, 0, 0 }; uint8_t w = 0; #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT int f_min, f_delta, f_power; @@ -1010,7 +978,6 @@ static uint32_t sequence_TAP_inner(int dir) gate[gi - 1] = FP_SCALE; for (i = 0; i < NUM_LEDS; i++) { - #ifdef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT if (max_led > i) { f_mult = FP_SCALE; @@ -1019,7 +986,8 @@ static uint32_t sequence_TAP_inner(int dir) } else { switch (base_color) { case RED: - f_power = range(st.battery_percent, 0, + f_power = range( + st.battery_percent, 0, st.p.battery_threshold[0] - 1); break; case YELLOW: @@ -1174,9 +1142,9 @@ static inline uint32_t decode_32(uint32_t *dest) CPRINTS("pc 0x%02x near or out of bounds", pc); return EC_RES_INVALID_PARAM; } - *dest = cur_prog.data[pc++] << 24; + *dest = cur_prog.data[pc++] << 24; *dest |= cur_prog.data[pc++] << 16; - *dest |= cur_prog.data[pc++] << 8; + *dest |= cur_prog.data[pc++] << 8; *dest |= cur_prog.data[pc++]; return EC_SUCCESS; } @@ -1307,7 +1275,6 @@ static uint32_t lightbyte_SET_BRIGHTNESS(void) */ static uint32_t lightbyte_SET_COLOR_SINGLE(void) { - uint8_t packed_loc, led, control, color, value; int i; if (decode_8(&packed_loc) != EC_SUCCESS) @@ -1369,8 +1336,8 @@ static uint32_t lightbyte_GET_COLORS(void) int i; for (i = 0; i < NUM_LEDS; i++) lb_get_rgb(i, &led_desc[i][LB_CONT_COLOR0][LB_COL_RED], - &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN], - &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]); + &led_desc[i][LB_CONT_COLOR0][LB_COL_GREEN], + &led_desc[i][LB_CONT_COLOR0][LB_COL_BLUE]); return EC_SUCCESS; } @@ -1481,15 +1448,21 @@ static uint32_t lightbyte_CYCLE(void) for (w = 0;; w++) { for (i = 0; i < NUM_LEDS; i++) { - r = get_interp_value(i, LB_COL_RED, - cycle_010((w & 0xff) + - led_desc[i][LB_CONT_PHASE][LB_COL_RED])); - g = get_interp_value(i, LB_COL_GREEN, + r = get_interp_value( + i, LB_COL_RED, + cycle_010( + (w & 0xff) + + led_desc[i][LB_CONT_PHASE][LB_COL_RED])); + g = get_interp_value( + i, LB_COL_GREEN, cycle_010((w & 0xff) + - led_desc[i][LB_CONT_PHASE][LB_COL_GREEN])); - b = get_interp_value(i, LB_COL_BLUE, + led_desc[i][LB_CONT_PHASE] + [LB_COL_GREEN])); + b = get_interp_value( + i, LB_COL_BLUE, cycle_010((w & 0xff) + - led_desc[i][LB_CONT_PHASE][LB_COL_BLUE])); + led_desc[i][LB_CONT_PHASE] + [LB_COL_BLUE])); lb_set_rgb(i, r, g, b); } WAIT_OR_RET(lb_ramp_delay); @@ -1509,24 +1482,17 @@ static uint32_t lightbyte_HALT(void) #define OP(NAME, BYTES, MNEMONIC) NAME, #include "lightbar_opcode_list.h" -enum lightbyte_opcode { - LIGHTBAR_OPCODE_TABLE - MAX_OPCODE -}; +enum lightbyte_opcode { LIGHTBAR_OPCODE_TABLE MAX_OPCODE }; #undef OP -#define OP(NAME, BYTES, MNEMONIC) lightbyte_ ## NAME, +#define OP(NAME, BYTES, MNEMONIC) lightbyte_##NAME, #include "lightbar_opcode_list.h" -static uint32_t (*lightbyte_dispatch[])(void) = { - LIGHTBAR_OPCODE_TABLE -}; +static uint32_t (*lightbyte_dispatch[])(void) = { LIGHTBAR_OPCODE_TABLE }; #undef OP #define OP(NAME, BYTES, MNEMONIC) MNEMONIC, #include "lightbar_opcode_list.h" -static const char * const lightbyte_names[] = { - LIGHTBAR_OPCODE_TABLE -}; +static const char *const lightbyte_names[] = { LIGHTBAR_OPCODE_TABLE }; #undef OP static uint32_t sequence_PROGRAM(void) @@ -1563,7 +1529,7 @@ static uint32_t sequence_PROGRAM(void) return EC_RES_INVALID_PARAM; } else { CPRINTS("LB PROGRAM pc: 0x%02x, opcode 0x%02x -> %s", - old_pc, next_inst, lightbyte_names[next_inst]); + old_pc, next_inst, lightbyte_names[next_inst]); rc = lightbyte_dispatch[next_inst](); if (rc) { lb_set_brightness(saved_brightness); @@ -1588,15 +1554,16 @@ static inline int is_normal_sequence(enum lightbar_sequence seq) /* Link each sequence with a command to invoke it. */ struct lightbar_cmd_t { - const char * const string; + const char *const string; uint32_t (*sequence)(void); }; -#define LBMSG(state) { #state, sequence_##state } +#define LBMSG(state) \ + { \ +#state, sequence_##state \ + } #include "lightbar_msg_list.h" -static struct lightbar_cmd_t lightbar_cmds[] = { - LIGHTBAR_MSG_LIST -}; +static struct lightbar_cmd_t lightbar_cmds[] = { LIGHTBAR_MSG_LIST }; #undef LBMSG void lightbar_task(void) @@ -1608,9 +1575,9 @@ void lightbar_task(void) lightbar_restore_state(); while (1) { - CPRINTS("LB running cur_seq %d %s. prev_seq %d %s", - st.cur_seq, lightbar_cmds[st.cur_seq].string, - st.prev_seq, lightbar_cmds[st.prev_seq].string); + CPRINTS("LB running cur_seq %d %s. prev_seq %d %s", st.cur_seq, + lightbar_cmds[st.cur_seq].string, st.prev_seq, + lightbar_cmds[st.prev_seq].string); next_seq = lightbar_cmds[st.cur_seq].sequence(); if (next_seq) { CPRINTS("LB cur_seq %d %s returned pending msg %d %s", @@ -1622,8 +1589,8 @@ void lightbar_task(void) st.cur_seq = next_seq; } } else { - CPRINTS("LB cur_seq %d %s returned value 0", - st.cur_seq, lightbar_cmds[st.cur_seq].string); + CPRINTS("LB cur_seq %d %s returned value 0", st.cur_seq, + lightbar_cmds[st.cur_seq].string); switch (st.cur_seq) { case LIGHTBAR_S5S3: st.cur_seq = LIGHTBAR_S3; @@ -1733,16 +1700,12 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) lb_hc_cmd_reg(in); break; case LIGHTBAR_CMD_SET_RGB: - lb_set_rgb(in->set_rgb.led, - in->set_rgb.red, - in->set_rgb.green, + lb_set_rgb(in->set_rgb.led, in->set_rgb.red, in->set_rgb.green, in->set_rgb.blue); break; case LIGHTBAR_CMD_GET_RGB: - rv = lb_get_rgb(in->get_rgb.led, - &out->get_rgb.red, - &out->get_rgb.green, - &out->get_rgb.blue); + rv = lb_get_rgb(in->get_rgb.led, &out->get_rgb.red, + &out->get_rgb.green, &out->get_rgb.blue); if (rv == EC_RES_SUCCESS) args->response_size = sizeof(out->get_rgb); return rv; @@ -1777,8 +1740,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) break; case LIGHTBAR_CMD_SET_PROGRAM: CPRINTS("LB_set_program"); - memcpy(&next_prog, - &in->set_program, + memcpy(&next_prog, &in->set_program, sizeof(struct lightbar_program)); break; case LIGHTBAR_CMD_VERSION: @@ -1801,28 +1763,24 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) break; case LIGHTBAR_CMD_GET_PARAMS_V2_TIMING: CPRINTS("LB_get_params_v2_timing"); - memcpy(&out->get_params_v2_timing, - &st.p_v2.timing, + memcpy(&out->get_params_v2_timing, &st.p_v2.timing, sizeof(st.p_v2.timing)); args->response_size = sizeof(out->get_params_v2_timing); break; case LIGHTBAR_CMD_SET_PARAMS_V2_TIMING: CPRINTS("LB_set_params_v2_timing"); - memcpy(&st.p_v2.timing, - &in->set_v2par_timing, + memcpy(&st.p_v2.timing, &in->set_v2par_timing, sizeof(struct lightbar_params_v2_timing)); break; case LIGHTBAR_CMD_GET_PARAMS_V2_TAP: CPRINTS("LB_get_params_v2_tap"); - memcpy(&out->get_params_v2_tap, - &st.p_v2.tap, + memcpy(&out->get_params_v2_tap, &st.p_v2.tap, sizeof(struct lightbar_params_v2_tap)); args->response_size = sizeof(out->get_params_v2_tap); break; case LIGHTBAR_CMD_SET_PARAMS_V2_TAP: CPRINTS("LB_set_params_v2_tap"); - memcpy(&st.p_v2.tap, - &in->set_v2par_tap, + memcpy(&st.p_v2.tap, &in->set_v2par_tap, sizeof(struct lightbar_params_v2_tap)); break; case LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION: @@ -1833,47 +1791,40 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) break; case LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION: CPRINTS("LB_set_params_v2_oscillation"); - memcpy(&st.p_v2.osc, - &in->set_v2par_osc, + memcpy(&st.p_v2.osc, &in->set_v2par_osc, sizeof(struct lightbar_params_v2_oscillation)); break; case LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS: CPRINTS("LB_get_params_v2_brightness"); - memcpy(&out->get_params_v2_bright, - &st.p_v2.bright, + memcpy(&out->get_params_v2_bright, &st.p_v2.bright, sizeof(struct lightbar_params_v2_brightness)); args->response_size = sizeof(out->get_params_v2_bright); break; case LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS: CPRINTS("LB_set_params_v2_brightness"); - memcpy(&st.p_v2.bright, - &in->set_v2par_bright, + memcpy(&st.p_v2.bright, &in->set_v2par_bright, sizeof(struct lightbar_params_v2_brightness)); break; case LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS: CPRINTS("LB_get_params_v2_thlds"); - memcpy(&out->get_params_v2_thlds, - &st.p_v2.thlds, + memcpy(&out->get_params_v2_thlds, &st.p_v2.thlds, sizeof(struct lightbar_params_v2_thresholds)); args->response_size = sizeof(out->get_params_v2_thlds); break; case LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS: CPRINTS("LB_set_params_v2_thlds"); - memcpy(&st.p_v2.thlds, - &in->set_v2par_thlds, + memcpy(&st.p_v2.thlds, &in->set_v2par_thlds, sizeof(struct lightbar_params_v2_thresholds)); break; case LIGHTBAR_CMD_GET_PARAMS_V2_COLORS: CPRINTS("LB_get_params_v2_colors"); - memcpy(&out->get_params_v2_colors, - &st.p_v2.colors, + memcpy(&out->get_params_v2_colors, &st.p_v2.colors, sizeof(struct lightbar_params_v2_colors)); args->response_size = sizeof(out->get_params_v2_colors); break; case LIGHTBAR_CMD_SET_PARAMS_V2_COLORS: CPRINTS("LB_set_params_v2_colors"); - memcpy(&st.p_v2.colors, - &in->set_v2par_colors, + memcpy(&st.p_v2.colors, &in->set_v2par_colors, sizeof(struct lightbar_params_v2_colors)); break; default: @@ -1884,9 +1835,7 @@ static enum ec_status lpc_cmd_lightbar(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, - lpc_cmd_lightbar, - EC_VER_MASK(0)); +DECLARE_HOST_COMMAND(EC_CMD_LIGHTBAR_CMD, lpc_cmd_lightbar, EC_VER_MASK(0)); /****************************************************************************/ /* EC console commands */ @@ -1902,10 +1851,12 @@ static int help(const char *cmd) ccprintf(" %s init - load default vals\n", cmd); ccprintf(" %s brightness [NUM] - set intensity (0-ff)\n", cmd); ccprintf(" %s seq [NUM|SEQUENCE] - run given pattern" - " (no arg for list)\n", cmd); + " (no arg for list)\n", + cmd); ccprintf(" %s CTRL REG VAL - set LED controller regs\n", cmd); ccprintf(" %s LED RED GREEN BLUE - set color manually" - " (LED=%d for all)\n", cmd, NUM_LEDS); + " (LED=%d for all)\n", + cmd, NUM_LEDS); ccprintf(" %s LED - get current LED color\n", cmd); ccprintf(" %s demo [0|1] - turn demo mode on & off\n", cmd); #ifdef LIGHTBAR_SIMULATION @@ -1943,12 +1894,11 @@ static int command_lightbar(int argc, char **argv) struct ec_response_lightbar out; char *e; - if (argc == 1) { /* no args = dump 'em all */ + if (argc == 1) { /* no args = dump 'em all */ lb_hc_cmd_dump(&out); for (i = 0; i < ARRAY_SIZE(out.dump.vals); i++) ccprintf(" %02x %02x %02x\n", - out.dump.vals[i].reg, - out.dump.vals[i].ic0, + out.dump.vals[i].reg, out.dump.vals[i].ic0, out.dump.vals[i].ic1); return EC_SUCCESS; @@ -1987,8 +1937,7 @@ static int command_lightbar(int argc, char **argv) if (!strcasecmp(argv[1], "demo")) { if (argc > 2) { - if (!strcasecmp(argv[2], "on") || - argv[2][0] == '1') + if (!strcasecmp(argv[2], "on") || argv[2][0] == '1') demo_mode = 1; else if (!strcasecmp(argv[2], "off") || argv[2][0] == '0') @@ -2010,7 +1959,7 @@ static int command_lightbar(int argc, char **argv) num = find_msg_by_name(argv[2]); if (num >= LIGHTBAR_NUM_SEQUENCES) return EC_ERROR_PARAM2; - if (argc > 3) /* for testing TAP direction */ + if (argc > 3) /* for testing TAP direction */ force_dir = strtoi(argv[3], 0, 0); lightbar_sequence(num); return EC_SUCCESS; @@ -2056,13 +2005,11 @@ static int command_lightbar(int argc, char **argv) return EC_SUCCESS; } - #ifdef CONFIG_CONSOLE_CMDHELP help(argv[0]); #endif return EC_ERROR_INVAL; } -DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, - "[help | COMMAND [ARGS]]", +DECLARE_CONSOLE_COMMAND(lightbar, command_lightbar, "[help | COMMAND [ARGS]]", "Get/set lightbar state"); -- cgit v1.2.1 From 3e0fd4e9cc90c226798a1536931da928b8df10a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:14:30 -0600 Subject: chip/host/flash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d329206e5fbf4a4a97ec2f652643285165d6e34 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729148 Reviewed-by: Jeremy Bettis --- chip/host/flash.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/chip/host/flash.c b/chip/host/flash.c index 75212737e0..5d895222e7 100644 --- a/chip/host/flash.c +++ b/chip/host/flash.c @@ -26,8 +26,7 @@ test_mockable int flash_pre_op(void) static int flash_check_protect(int offset, int size) { int first_bank = offset / CONFIG_FLASH_BANK_SIZE; - int last_bank = DIV_ROUND_UP(offset + size, - CONFIG_FLASH_BANK_SIZE); + int last_bank = DIV_ROUND_UP(offset + size, CONFIG_FLASH_BANK_SIZE); int bank; for (bank = first_bank; bank < last_bank; ++bank) @@ -124,8 +123,7 @@ int crec_flash_physical_protect_now(int all) uint32_t crec_flash_physical_get_valid_flags(void) { - return EC_FLASH_PROTECT_RO_AT_BOOT | - EC_FLASH_PROTECT_RO_NOW | + return EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_ALL_NOW; } @@ -163,8 +161,9 @@ int crec_flash_pre_init(void) */ if ((prot_flags & EC_FLASH_PROTECT_RO_AT_BOOT) && !(prot_flags & EC_FLASH_PROTECT_RO_NOW)) { - int rv = crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, - EC_FLASH_PROTECT_RO_NOW); + int rv = + crec_flash_set_protect(EC_FLASH_PROTECT_RO_NOW, + EC_FLASH_PROTECT_RO_NOW); if (rv) return rv; -- cgit v1.2.1 From dd60411b0fb22843b8520ce26d885efd32c40c2c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:28 -0600 Subject: chip/npcx/header.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife57c37e9bec3dfdfeb85b3fc163dbd1cce6fb2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729383 Reviewed-by: Jeremy Bettis --- chip/npcx/header.c | 59 +++++++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/chip/npcx/header.c b/chip/npcx/header.c index 0ba3ee59d6..597678dc47 100644 --- a/chip/npcx/header.c +++ b/chip/npcx/header.c @@ -16,59 +16,60 @@ #include "registers.h" /* Signature used by fw header */ -#define SIG_FW_EC 0x2A3B4D5E +#define SIG_FW_EC 0x2A3B4D5E /* Definition used by error detection configuration */ -#define CHECK_CRC 0x00 -#define CHECK_CHECKSUM 0x01 -#define ERROR_DETECTION_EN 0x02 +#define CHECK_CRC 0x00 +#define CHECK_CHECKSUM 0x01 +#define ERROR_DETECTION_EN 0x02 #define ERROR_DETECTION_DIS 0x00 /* Code RAM addresses use by header */ /* Put FW at the begin of CODE RAM */ -#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE +#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE /* TODO: It will be filled automatically by ECST */ /* The entry point of reset handler (filled by ECST tool)*/ -#define FW_ENTRY_ADDR 0x100A8169 +#define FW_ENTRY_ADDR 0x100A8169 /* Error detection addresses use by header (A offset relative to flash image) */ -#define ERRCHK_START_ADDR 0x0 -#define ERRCHK_END_ADDR 0x0 +#define ERRCHK_START_ADDR 0x0 +#define ERRCHK_END_ADDR 0x0 /* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/ -#define FW_SIZE CONFIG_RO_SIZE +#define FW_SIZE CONFIG_RO_SIZE /* FW Header used by NPCX5M5G Booter */ struct __packed fw_header_t { - uint32_t anchor; /* A constant used to verify FW header */ - uint16_t ext_anchor; /* Enable/disable firmware header CRC check */ - uint8_t spi_max_freq; /* Spi maximum allowable clock frequency */ - uint8_t spi_read_mode; /* Spi read mode used for firmware loading */ - uint8_t cfg_err_detect; /* FW load error detection configuration */ - uint32_t fw_load_addr; /* Firmware load start address */ - uint32_t fw_entry; /* Firmware entry point */ + uint32_t anchor; /* A constant used to verify FW header */ + uint16_t ext_anchor; /* Enable/disable firmware header CRC check */ + uint8_t spi_max_freq; /* Spi maximum allowable clock frequency */ + uint8_t spi_read_mode; /* Spi read mode used for firmware loading */ + uint8_t cfg_err_detect; /* FW load error detection configuration */ + uint32_t fw_load_addr; /* Firmware load start address */ + uint32_t fw_entry; /* Firmware entry point */ uint32_t err_detect_start_addr; /* FW error detect start address */ - uint32_t err_detect_end_addr; /* FW error detect end address */ - uint32_t fw_length; /* Firmware length in bytes */ - uint8_t flash_size; /* Indicate SPI flash size */ - uint8_t reserved[26]; /* Reserved bytes */ - uint32_t sig_header; /* The CRC signature of the firmware header */ - uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */ + uint32_t err_detect_end_addr; /* FW error detect end address */ + uint32_t fw_length; /* Firmware length in bytes */ + uint8_t flash_size; /* Indicate SPI flash size */ + uint8_t reserved[26]; /* Reserved bytes */ + uint32_t sig_header; /* The CRC signature of the firmware header */ + uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */ } __aligned(1); -__keep __attribute__ ((section(".header"))) +__keep __attribute__((section(".header"))) const struct fw_header_t fw_header = { /* 00 */ SIG_FW_EC, /* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h */ - /* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h */ - /* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */ - /* 08 */ 0x00, /* Disable CRC check functionality */ + /* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h */ + /* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */ + /* 08 */ 0x00, /* Disable CRC check functionality */ /* 09 */ FW_START_ADDR, - /* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */ + /* 0D */ FW_ENTRY_ADDR, /* Filling by ECST tool with -usearmrst option + */ /* 11 */ ERRCHK_START_ADDR, /* 15 */ ERRCHK_END_ADDR, - /* 19 */ FW_SIZE,/* Filling by ECST tool */ - /* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh */ + /* 19 */ FW_SIZE, /* Filling by ECST tool */ + /* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh */ /* 1E-3F Other fields are filled by ECST tool or reserved */ }; -- cgit v1.2.1 From 4d8c049141377b0b85100a4fd3f76351fd02f6c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:20 -0600 Subject: driver/bc12/pi3usb9201.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6c32bb0f193ad98462fddaaf2ed6fc746a6137e3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729934 Reviewed-by: Jeremy Bettis --- driver/bc12/pi3usb9201.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/bc12/pi3usb9201.h b/driver/bc12/pi3usb9201.h index 3163a3eebc..f50b8278d9 100644 --- a/driver/bc12/pi3usb9201.h +++ b/driver/bc12/pi3usb9201.h @@ -21,8 +21,8 @@ /* Control_1 regiter bit definitions */ #define PI3USB9201_REG_CTRL_1_INT_MASK BIT(0) #define PI3USB9201_REG_CTRL_1_MODE_SHIFT 1 -#define PI3USB9201_REG_CTRL_1_MODE_MASK (0x7 << \ - PI3USB9201_REG_CTRL_1_MODE_SHIFT) +#define PI3USB9201_REG_CTRL_1_MODE_MASK \ + (0x7 << PI3USB9201_REG_CTRL_1_MODE_SHIFT) /* Control_2 regiter bit definitions */ #define PI3USB9201_REG_CTRL_2_AUTO_SW BIT(1) -- cgit v1.2.1 From 208d0f8a9179546c04e8253641d9aee0d3b51d19 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:23 -0600 Subject: zephyr/shim/include/usbc/bc12_rt9490.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibccd3e8a0714c0226f84507c553bb035a967b73d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730834 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/bc12_rt9490.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/zephyr/shim/include/usbc/bc12_rt9490.h b/zephyr/shim/include/usbc/bc12_rt9490.h index f9bc82f292..fe57e42524 100644 --- a/zephyr/shim/include/usbc/bc12_rt9490.h +++ b/zephyr/shim/include/usbc/bc12_rt9490.h @@ -7,4 +7,7 @@ #define RT9490_BC12_COMPAT richtek_rt9490_bc12 -#define BC12_CHIP_RT9490(id) { .drv = &rt9490_bc12_drv, }, +#define BC12_CHIP_RT9490(id) \ + { \ + .drv = &rt9490_bc12_drv, \ + }, -- cgit v1.2.1 From 3569aa91247b9cbb97989285b972e6070c2baee2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:21 -0600 Subject: board/chocodile_vpdmcu/vpd_api.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I40ec4090de0d01ed6ef0c03f589292d0dfb88240 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728124 Reviewed-by: Jeremy Bettis --- board/chocodile_vpdmcu/vpd_api.c | 106 ++++++++++++++++++++++++--------------- 1 file changed, 66 insertions(+), 40 deletions(-) diff --git a/board/chocodile_vpdmcu/vpd_api.c b/board/chocodile_vpdmcu/vpd_api.c index cdd2d9776d..d4c57f9ff0 100644 --- a/board/chocodile_vpdmcu/vpd_api.c +++ b/board/chocodile_vpdmcu/vpd_api.c @@ -35,7 +35,7 @@ #endif #undef CC_RA -#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel]) +#define CC_RA(cc, sel) (cc < pd_src_rd_threshold[sel]) #undef CC_RD #define CC_RD(cc, sel) ((cc >= pd_src_rd_threshold[sel]) && (cc < PD_SRC_VNC)) @@ -47,16 +47,16 @@ #define VBUS_DETECT_THRESHOLD 2500 /* mV */ #define VCONN_DETECT_THRESHOLD 2500 /* mV */ -#define SCALE(vmeas, sfactor) (((vmeas) * 1000) / (sfactor)) +#define SCALE(vmeas, sfactor) (((vmeas)*1000) / (sfactor)) /* * Type C power source charge current limits are identified by their cc * voltage (set by selecting the proper Rd resistor). Any voltage below * TYPE_C_SRC_500_THRESHOLD will not be identified as a type C charger. */ -#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */ -#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ -#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ +#define TYPE_C_SRC_DEFAULT_THRESHOLD 200 /* mV */ +#define TYPE_C_SRC_1500_THRESHOLD 660 /* mV */ +#define TYPE_C_SRC_3000_THRESHOLD 1230 /* mV */ /* Charge-Through pull up/down enabled */ static int ct_cc_pull; @@ -86,7 +86,7 @@ static int vpd_cc_voltage_to_status(int cc_volt, int cc_pull) return TYPEC_CC_VOLT_RA; else return TYPEC_CC_VOLT_OPEN; - /* If we have a pull-down, then we are sink, check for Rp. */ + /* If we have a pull-down, then we are sink, check for Rp. */ } else if (cc_pull == TYPEC_CC_RD || cc_pull == TYPEC_CC_RA_RD) { if (cc_volt >= TYPE_C_SRC_3000_THRESHOLD) return TYPEC_CC_VOLT_RP_3_0; @@ -218,8 +218,8 @@ void vpd_host_set_pull(int pull, int rp_value) void vpd_host_get_cc(int *cc) { - *cc = vpd_cc_voltage_to_status( - adc_read_channel(ADC_CC_VPDMCU), host_cc_pull); + *cc = vpd_cc_voltage_to_status(adc_read_channel(ADC_CC_VPDMCU), + host_cc_pull); } void vpd_rx_enable(int en) @@ -237,17 +237,23 @@ void vpd_config_cc_rp3a0_rd_l(enum vpd_pin cfg, int en) gpio_set_level(GPIO_CC_RP3A0_RD_L, en ? 1 : 0); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*2))) /* PA2 disable ADC */ - | (1 << (2*2)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 2))) /* PA2 + disable + ADC */ + | (1 << (2 * 2)); /* Set as GPO */ } else { /* Set PA2 pin to ANALOG function */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*2))); /* PA2 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 2))); /* PA2 in + ANALOG + mode */ /* Set PA3 pin to ANALOG function */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*3))); /* PA3 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 3))); /* PA3 in + ANALOG + mode */ /* Disable Window Mode. Select PA3 */ STM32_COMP_CSR &= ~STM32_COMP_WNDWEN; @@ -276,9 +282,11 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en) gpio_set_level(GPIO_CC1_RP3A0_RD_L, en ? 1 : 0); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*4))) /* PA4 disable ADC */ - | (1 << (2*4)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 4))) /* PA4 + disable + ADC */ + | (1 << (2 * 4)); /* Set as GPO */ } if (cfg == PIN_ADC || cfg == PIN_CMP) { @@ -286,13 +294,17 @@ void vpd_config_cc1_rp3a0_rd_l(enum vpd_pin cfg, int en) STM32_COMP_CSR &= ~STM32_COMP_CMP2EN; /* Set PA4 pin to Analog mode */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*4))); /* PA4 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 4))); /* PA4 in + ANALOG + mode */ if (cfg == PIN_CMP) { /* Set PA3 pin to ANALOG function */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*3))); /* PA3 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) | + (3 << (2 * 3))); /* PA3 in + ANALOG + mode */ /* Disable Window Mode. Select PA3*/ STM32_COMP_CSR &= ~STM32_COMP_WNDWEN; @@ -319,9 +331,11 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en) gpio_set_level(GPIO_CC2_RP3A0_RD_L, en ? 1 : 0); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - & ~(3 << (2*5))) /* PA5 disable ADC */ - | (1 << (2*5)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) & ~(3 << (2 * 5))) /* PA5 + disable + ADC */ + | (1 << (2 * 5)); /* Set as GPO */ } if (cfg == PIN_ADC || cfg == PIN_CMP) { @@ -329,13 +343,17 @@ void vpd_config_cc2_rp3a0_rd_l(enum vpd_pin cfg, int en) STM32_COMP_CSR &= ~STM32_COMP_CMP2EN; /* Set PA5 pin to ANALOG function */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*5))); /* PA5 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = + (STM32_GPIO_MODER(GPIO_A) | (3 << (2 * 5))); /* PA5 in + ANALOG + mode */ if (cfg == PIN_CMP) { /* Set PA3 pin to ANALOG function */ - STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) - | (3 << (2*3))); /* PA3 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A) | + (3 << (2 * 3))); /* PA3 in + ANALOG + mode */ /* Disable Window Mode. */ STM32_COMP_CSR &= ~STM32_COMP_WNDWEN; @@ -362,13 +380,17 @@ void vpd_config_cc1_rpusb_odh(enum vpd_pin cfg, int en) gpio_set_level(GPIO_CC1_RPUSB_ODH, en ? 1 : 0); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*0))) /* PB0 disable ADC */ - | (1 << (2*0)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 0))) /* PB0 + disable + ADC */ + | (1 << (2 * 0)); /* Set as GPO */ } else { /* Enable Analog mode */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - | (3 << (2*0))); /* PB0 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 0))); /* PB0 in + ANALOG + mode */ } } @@ -382,13 +404,17 @@ void vpd_config_cc2_rpusb_odh(enum vpd_pin cfg, int en) gpio_set_level(GPIO_CC2_RPUSB_ODH, en ? 1 : 0); /* Disable Analog mode and Enable GPO */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*1))) /* PB1 disable ADC */ - | (1 << (2*1)); /* Set as GPO */ + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 1))) /* PB1 + disable + ADC */ + | (1 << (2 * 1)); /* Set as GPO */ } else { /* Enable Analog mode */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - | (3 << (2*1))); /* PB1 in ANALOG mode */ + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) | (3 << (2 * 1))); /* PB1 in + ANALOG + mode */ } } @@ -405,7 +431,7 @@ inline int vpd_read_host_vbus(void) inline int vpd_read_ct_vbus(void) { return SCALE(adc_read_channel(ADC_CHARGE_VBUS_VSENSE), - VBUS_SCALE_FACTOR); + VBUS_SCALE_FACTOR); } inline int vpd_read_vconn(void) -- cgit v1.2.1 From 7a60170fc6e0c4694bb511884712b8dad3281601 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:27 -0600 Subject: driver/retimer/pi3dpx1207.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ac34775dde7b9529d264d18c3291c0ef520127d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730043 Reviewed-by: Jeremy Bettis --- driver/retimer/pi3dpx1207.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/driver/retimer/pi3dpx1207.c b/driver/retimer/pi3dpx1207.c index 8829c508a1..b75e88b25f 100644 --- a/driver/retimer/pi3dpx1207.c +++ b/driver/retimer/pi3dpx1207.c @@ -21,8 +21,7 @@ static uint8_t buf[PI3DPX1207_NUM_REGISTERS]; /** * Local utility functions */ -static int pi3dpx1207_i2c_write(const struct usb_mux *me, - uint8_t offset, +static int pi3dpx1207_i2c_write(const struct usb_mux *me, uint8_t offset, uint8_t val) { int rv = EC_SUCCESS; @@ -44,8 +43,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me, attempt = 0; do { attempt++; - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - NULL, 0, buf, offset); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, NULL, 0, + buf, offset); } while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES)); } @@ -55,8 +54,8 @@ static int pi3dpx1207_i2c_write(const struct usb_mux *me, attempt = 0; do { attempt++; - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - buf, offset + 1, NULL, 0); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf, + offset + 1, NULL, 0); } while ((rv != EC_SUCCESS) && (attempt < I2C_MAX_RETRIES)); } return rv; @@ -108,25 +107,25 @@ static int pi3dpx1207_set_mux(const struct usb_mux *me, mux_state_t mux_state, /* USB with DP */ if (mux_state & USB_PD_MUX_DP_ENABLED) { gpio_or_ioex_set_level(gpio_dp_enable, 1); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_USB_DP_FLIP - : PI3DPX1207_MODE_CONF_USB_DP; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_USB_DP_FLIP : + PI3DPX1207_MODE_CONF_USB_DP; } /* USB without DP */ else { gpio_or_ioex_set_level(gpio_dp_enable, 0); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_USB_FLIP - : PI3DPX1207_MODE_CONF_USB; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_USB_FLIP : + PI3DPX1207_MODE_CONF_USB; } } /* DP without USB */ else if (mux_state & USB_PD_MUX_DP_ENABLED) { gpio_or_ioex_set_level(gpio_enable, 1); gpio_or_ioex_set_level(gpio_dp_enable, 1); - mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? PI3DPX1207_MODE_CONF_DP_FLIP - : PI3DPX1207_MODE_CONF_DP; + mode_val |= (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + PI3DPX1207_MODE_CONF_DP_FLIP : + PI3DPX1207_MODE_CONF_DP; } /* Nothing enabled, power down the retimer */ else { -- cgit v1.2.1 From 4e4c939337422a5eacd45e247bbc1a3f38f041a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:13 -0600 Subject: chip/stm32/usb_dwc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie35e6efa332e399b523c5e5ddc0a07e08985584f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729570 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_dwc.c | 167 +++++++++++++++++++++++---------------------------- 1 file changed, 75 insertions(+), 92 deletions(-) diff --git a/chip/stm32/usb_dwc.c b/chip/stm32/usb_dwc.c index 0028806432..75d15dc48f 100644 --- a/chip/stm32/usb_dwc.c +++ b/chip/stm32/usb_dwc.c @@ -20,19 +20,17 @@ #include "usb_descriptor.h" #include "watchdog.h" - /****************************************************************************/ /* Debug output */ /* Console output macro */ -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) /* TODO: Something unexpected happened. Figure out how to report & fix it. */ -#define report_error(val) \ - CPRINTS("Unhandled USB event at %s line %d: 0x%x", \ - __FILE__, __LINE__, val) - +#define report_error(val) \ + CPRINTS("Unhandled USB event at %s line %d: 0x%x", __FILE__, __LINE__, \ + val) /****************************************************************************/ /* Standard USB stuff */ @@ -49,7 +47,7 @@ #endif #ifndef CONFIG_USB_BCD_DEV -#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ +#define CONFIG_USB_BCD_DEV 0x0100 /* 1.00 */ #endif #ifndef CONFIG_USB_SERIALNO @@ -58,7 +56,6 @@ static int usb_load_serial(void); #endif - /* USB Standard Device Descriptor */ static const struct usb_device_descriptor dev_desc = { .bLength = USB_DT_DEVICE_SIZE, @@ -81,25 +78,24 @@ static const struct usb_device_descriptor dev_desc = { const struct usb_config_descriptor USB_CONF_DESC(conf) = { .bLength = USB_DT_CONFIG_SIZE, .bDescriptorType = USB_DT_CONFIGURATION, - .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ + .wTotalLength = 0x0BAD, /* number of returned bytes, set at runtime */ .bNumInterfaces = USB_IFACE_COUNT, - .bConfigurationValue = 1, /* Caution: hard-coded value */ + .bConfigurationValue = 1, /* Caution: hard-coded value */ .iConfiguration = USB_STR_VERSION, .bmAttributes = 0x80 /* Reserved bit */ -#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ - | 0x40 +#ifdef CONFIG_USB_SELF_POWERED /* bus or self powered */ + | 0x40 #endif #ifdef CONFIG_USB_REMOTE_WAKEUP - | 0x20 + | 0x20 #endif , .bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2), }; const uint8_t usb_string_desc[] = { - 4, /* Descriptor size */ - USB_DT_STRING, - 0x09, 0x04 /* LangID = 0x0409: U.S. English */ + 4, /* Descriptor size */ + USB_DT_STRING, 0x09, 0x04 /* LangID = 0x0409: U.S. English */ }; /****************************************************************************/ @@ -113,7 +109,7 @@ static enum { } what_am_i_doing; #ifdef DEBUG_ME -static const char * const wat[3] = { +static const char *const wat[3] = { [WAITING_FOR_SETUP_PACKET] = "wait_for_setup", [DATA_STAGE_IN] = "data_in", [NO_DATA_STAGE] = "no_data", @@ -182,7 +178,6 @@ static enum { } device_state; static uint8_t configuration_value; - /* True if the HW Rx/OUT FIFO is currently listening. */ int rx_ep_is_active(uint32_t ep_num) { @@ -326,10 +321,9 @@ void usb_epN_rx(uint32_t ep_num) /* Bytes received decrement DOEPTSIZ XFERSIZE */ if (GR_USB_DOEPINT(ep_num) & DOEPINT_XFERCOMPL) { if (ep->out_expected > 0) { - ep->out_pending = - ep->out_expected - - (GR_USB_DOEPTSIZ(ep_num) & - GC_USB_DOEPTSIZ1_XFERSIZE_MASK); + ep->out_pending = ep->out_expected - + (GR_USB_DOEPTSIZ(ep_num) & + GC_USB_DOEPTSIZ1_XFERSIZE_MASK); } else { CPRINTF("usb_ep%d_rx: unexpected RX DOEPTSIZ %08x\n", ep_num, GR_USB_DOEPTSIZ(ep_num)); @@ -350,25 +344,22 @@ void usb_epN_rx(uint32_t ep_num) void epN_reset(uint32_t ep_num) { GR_USB_DOEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; + DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK; GR_USB_DIEPCTL(ep_num) = DXEPCTL_MPS(USB_MAX_PACKET_SIZE) | - DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | - DXEPCTL_TXFNUM(ep_num); - GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | - DAINT_OUTEP(ep_num); + DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_BULK | + DXEPCTL_TXFNUM(ep_num); + GR_USB_DAINTMSK |= DAINT_INEP(ep_num) | DAINT_OUTEP(ep_num); } - /****************************************************************************** * Internal and EP0 functions. */ - static void flush_all_fifos(void) { /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; + GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH; while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) ; } @@ -390,7 +381,6 @@ int send_in_packet(uint32_t ep_num) GR_USB_DIEPTSIZ(0) |= DXEPTSIZ_XFERSIZE(len); GR_USB_DIEPDMA(0) = (uint32_t)ep->in_data; - /* We're sending this much. */ ep->in_pending -= len; ep->in_packets -= 1; @@ -400,7 +390,6 @@ int send_in_packet(uint32_t ep_num) return len; } - /* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns * len, or negative on error. */ @@ -418,7 +407,7 @@ int initialize_in_transfer(const void *source, uint32_t len) #else /* HS OTG port requires an external phy to support HS */ ASSERT(!((usb->phy_type == USB_PHY_INTERNAL) && - (usb->speed == USB_SPEED_HS))); + (usb->speed == USB_SPEED_HS))); ASSERT(usb->irq == STM32_IRQ_OTG_HS); #endif @@ -435,7 +424,7 @@ int initialize_in_transfer(const void *source, uint32_t len) /* We will send as many packets as necessary, including a final * packet of < USB_MAX_PACKET_SIZE (maybe zero length) */ - ep->in_packets = (len + USB_MAX_PACKET_SIZE)/USB_MAX_PACKET_SIZE; + ep->in_packets = (len + USB_MAX_PACKET_SIZE) / USB_MAX_PACKET_SIZE; ep->in_pending = len; send_in_packet(0); @@ -495,8 +484,8 @@ static void expect_data_phase_in(enum table_case tc) /* Send the reply (data phase in) */ if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | - DXEPCTL_CNAK | DXEPCTL_EPENA; + GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK | + DXEPCTL_EPENA; else GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; @@ -508,7 +497,6 @@ static void expect_data_phase_in(enum table_case tc) /* Get an interrupt when either IN or OUT arrives */ GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0)); - } static void expect_data_phase_out(enum table_case tc) @@ -524,12 +512,12 @@ static void expect_status_phase_in(enum table_case tc) what_am_i_doing = NO_DATA_STAGE; /* Expect a zero-length IN for the Status phase */ - (void) initialize_in_transfer(0, 0); + (void)initialize_in_transfer(0, 0); /* Blindly following instructions here, too. */ if (tc == TABLE_CASE_SETUP) - GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP - | DXEPCTL_CNAK | DXEPCTL_EPENA; + GR_USB_DIEPCTL(0) |= DXEPCTL_USBACTEP | DXEPCTL_CNAK | + DXEPCTL_EPENA; else GR_USB_DIEPCTL(0) |= DXEPCTL_EPENA; @@ -549,7 +537,7 @@ static int handle_setup_with_in_stage(enum table_case tc, const void *data = 0; uint32_t len = 0; int ugly_hack = 0; - static const uint16_t zero; /* == 0 */ + static const uint16_t zero; /* == 0 */ switch (req->bRequest) { case USB_REQ_GET_DESCRIPTOR: { @@ -564,7 +552,7 @@ static int handle_setup_with_in_stage(enum table_case tc, case USB_DT_CONFIGURATION: data = __usb_desc; len = USB_DESC_SIZE; - ugly_hack = 1; /* see below */ + ugly_hack = 1; /* see below */ break; #ifdef CONFIG_USB_BOS case USB_DT_BOS: @@ -657,7 +645,7 @@ static int handle_setup_with_in_stage(enum table_case tc, /* Handle a Setup that comes with additional data for us. */ static int handle_setup_with_out_stage(enum table_case tc, - struct usb_setup_packet *req) + struct usb_setup_packet *req) { /* TODO: We don't support any of these. We should. */ report_error(-1); @@ -720,7 +708,7 @@ static int handle_setup_with_no_data_stage(enum table_case tc, configuration_value = req->wValue; device_state = DS_ADDRESS; break; - case 1: /* Caution: Only one config descriptor TODAY */ + case 1: /* Caution: Only one config descriptor TODAY */ /* TODO: All endpoints set to DATA0 toggle state */ configuration_value = req->wValue; device_state = DS_CONFIGURED; @@ -756,7 +744,7 @@ static void handle_setup(enum table_case tc) (struct usb_setup_packet *)ep->out_databuffer; int data_phase_in = req->bmRequestType & USB_DIR_IN; int data_phase_out = !data_phase_in && req->wLength; - int bytes = -1; /* default is to stall */ + int bytes = -1; /* default is to stall */ if (0 == (req->bmRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))) { /* Standard Device requests */ @@ -900,20 +888,20 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max * data packet size is 64 bytes. Total SPRAM available is 1024 slots. */ -#define MAX_CONTROL_EPS 3 -#define MAX_NORMAL_EPS 16 -#define FIFO_RAM_DEPTH 1024 +#define MAX_CONTROL_EPS 3 +#define MAX_NORMAL_EPS 16 +#define FIFO_RAM_DEPTH 1024 /* * Device RX FIFO size is thus: * (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85 */ -#define RXFIFO_SIZE ((4 * MAX_CONTROL_EPS + 6) + \ - 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ - (2 * MAX_NORMAL_EPS) + 1) +#define RXFIFO_SIZE \ + ((4 * MAX_CONTROL_EPS + 6) + 2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \ + (2 * MAX_NORMAL_EPS) + 1) /* * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46). */ -#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) +#define TXFIFO_SIZE (2 * (USB_MAX_PACKET_SIZE / 4)) /* * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1, * unconfigurable). @@ -925,20 +913,19 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in) BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE < FIFO_RAM_DEPTH); - /* Now put those constants into the correct registers */ static void setup_data_fifos(void) { int i; /* Programmer's Guide, p31 */ - GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ + GR_USB_GRXFSIZ = RXFIFO_SIZE; /* RXFIFO */ GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */ /* TXFIFO 1..15 */ for (i = 1; i < MAX_NORMAL_EPS; i++) - GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) | - (RXFIFO_SIZE + i * TXFIFO_SIZE)); + GR_USB_DIEPTXF(i) = + ((TXFIFO_SIZE << 16) | (RXFIFO_SIZE + i * TXFIFO_SIZE)); /* * TODO: The Programmer's Guide is confusing about when or whether to @@ -953,10 +940,10 @@ static void setup_data_fifos(void) */ /* Flush all FIFOs according to Section 2.1.1.2 */ - GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH - | GRSTCTL_RXFFLSH; + GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH; while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) - ; /* TODO: timeout 100ms */ + ; /* TODO: timeout 100ms */ } static void usb_init_endpoints(void) @@ -998,7 +985,6 @@ static void usb_enumdone(void) GR_USB_DCTL |= DCTL_CGOUTNAK; } - static void usb_interrupt(void) { uint32_t status = GR_USB_GINTSTS & GR_USB_GINTMSK; @@ -1027,10 +1013,10 @@ static void usb_interrupt(void) * let it know which direction(s) had an interrupt. */ if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) { - uint32_t intr_on_out = (oepint && - (daint & DAINT_OUTEP(0))); - uint32_t intr_on_in = (iepint && - (daint & DAINT_INEP(0))); + uint32_t intr_on_out = + (oepint && (daint & DAINT_OUTEP(0))); + uint32_t intr_on_in = + (iepint && (daint & DAINT_INEP(0))); ep0_interrupt(intr_on_out, intr_on_in); } @@ -1103,8 +1089,8 @@ void usb_reset_init_phy(void) if (usb->phy_type == USB_PHY_ULPI) { GR_USB_GCCFG &= ~GCCFG_PWRDWN; - GR_USB_GUSBCFG &= ~(GUSBCFG_TSDPS | - GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); + GR_USB_GUSBCFG &= + ~(GUSBCFG_TSDPS | GUSBCFG_ULPIFSLS | GUSBCFG_PHYSEL); GR_USB_GUSBCFG &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); /* No suspend */ GR_USB_GUSBCFG |= GUSBCFG_ULPICSM | GUSBCFG_ULPIAR; @@ -1168,11 +1154,11 @@ void usb_init(void) * GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) * | DCFG_DEVSPD_HSULPI; */ - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FSULPI; + GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) | + DCFG_DEVSPD_FSULPI; } else { - GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) - | DCFG_DEVSPD_FS48; + GR_USB_DCFG = (GR_USB_DCFG & ~GC_USB_DCFG_DEVSPD_MASK) | + DCFG_DEVSPD_FS48; } GR_USB_DCFG |= DCFG_NZLSOHSK; @@ -1190,10 +1176,11 @@ void usb_init(void) GR_USB_GAHBCFG |= GAHBCFG_TXFELVL | GAHBCFG_PTXFELVL; /* Device only, no SRP */ - GR_USB_GUSBCFG |= GUSBCFG_FDMOD - | GUSBCFG_TOUTCAL(7) - /* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */ - | GUSBCFG_USBTRDTIM(14); + GR_USB_GUSBCFG |= GUSBCFG_FDMOD | + GUSBCFG_TOUTCAL(7) + /* FIXME: Magic number! 14 is for 15MHz! Use 9 for + 30MHz */ + | GUSBCFG_USBTRDTIM(14); /* Be in disconnected state until we are ready */ usb_disconnect(); @@ -1225,15 +1212,15 @@ void usb_init(void) if (usb->dma_en) { GR_USB_DTHRCTL = DTHRCTL_TXTHRLEN_6 | DTHRCTL_RXTHRLEN_6; - GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN - | DTHRCTL_NONISOTHREN; + GR_USB_DTHRCTL |= DTHRCTL_RXTHREN | DTHRCTL_ISOTHREN | + DTHRCTL_NONISOTHREN; i = GR_USB_DTHRCTL; } GR_USB_GINTSTS = 0xFFFFFFFF; - GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL - | GAHBCFG_PTXFELVL; + GR_USB_GAHBCFG |= GAHBCFG_GLB_INTR_EN | GAHBCFG_TXFELVL | + GAHBCFG_PTXFELVL; if (!(usb->dma_en)) GR_USB_GINTMSK |= GINTMSK(RXFLVL); @@ -1241,7 +1228,7 @@ void usb_init(void) /* Unmask some endpoint interrupt causes */ GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK; GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK | - DOEPMSK_SETUPMSK; + DOEPMSK_SETUPMSK; /* Enable interrupt handlers */ task_enable_irq(usb->irq); @@ -1253,7 +1240,7 @@ void usb_init(void) /* Initialization events */ GINTMSK(USBRST) | GINTMSK(ENUMDONE) | /* Reset detected while suspended. Need to wake up. */ - GINTMSK(RESETDET) | /* TODO: Do we need this? */ + GINTMSK(RESETDET) | /* TODO: Do we need this? */ /* Idle, Suspend detected. Should go to sleep. */ GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP); @@ -1328,8 +1315,7 @@ static int command_usb(int argc, char **argv) return EC_ERROR_PARAM1; } -DECLARE_CONSOLE_COMMAND(usb, command_usb, - "[on|off|info]", +DECLARE_CONSOLE_COMMAND(usb, command_usb, "[on|off|info]", "Get/set the USB connection state and PHY selection"); #ifdef CONFIG_USB_SERIALNO @@ -1399,12 +1385,10 @@ static int command_serialno(int argc, char **argv) int i; if (argc != 1) { - if ((strcasecmp(argv[1], "set") == 0) && - (argc == 3)) { + if ((strcasecmp(argv[1], "set") == 0) && (argc == 3)) { ccprintf("Saving serial number\n"); rv = usb_save_serial(argv[2]); - } else if ((strcasecmp(argv[1], "load") == 0) && - (argc == 2)) { + } else if ((strcasecmp(argv[1], "load") == 0) && (argc == 2)) { ccprintf("Loading serial number\n"); rv = usb_load_serial(); } else @@ -1417,7 +1401,6 @@ static int command_serialno(int argc, char **argv) return rv; } -DECLARE_CONSOLE_COMMAND(serialno, command_serialno, - "load/set [value]", - "Read and write USB serial number"); -#endif /* CONFIG_USB_SERIALNO */ +DECLARE_CONSOLE_COMMAND(serialno, command_serialno, "load/set [value]", + "Read and write USB serial number"); +#endif /* CONFIG_USB_SERIALNO */ -- cgit v1.2.1 From ec42feaaa74b6d52b302fbc8c8d3b1e0e549612e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:32:37 -0600 Subject: chip/stm32/usb_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38561b85db80d7fbbdc7a42dc67c1b041cef3f46 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729553 Reviewed-by: Jeremy Bettis --- chip/stm32/usb_gpio.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/chip/stm32/usb_gpio.c b/chip/stm32/usb_gpio.c index 64d46875b5..c5bbd4a97d 100644 --- a/chip/stm32/usb_gpio.c +++ b/chip/stm32/usb_gpio.c @@ -11,8 +11,8 @@ void usb_gpio_tx(struct usb_gpio_config const *config) { - size_t i; - uint32_t mask = 1; + size_t i; + uint32_t mask = 1; uint32_t value = 0; for (i = 0; i < config->num_gpios; ++i, mask <<= 1) @@ -31,12 +31,12 @@ void usb_gpio_tx(struct usb_gpio_config const *config) void usb_gpio_rx(struct usb_gpio_config const *config) { - size_t i; - uint32_t mask = 1; - uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | - (uint32_t)(config->rx_ram[1]) << 16); - uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | - (uint32_t)(config->rx_ram[3]) << 16); + size_t i; + uint32_t mask = 1; + uint32_t set_mask = ((uint32_t)(config->rx_ram[0]) | + (uint32_t)(config->rx_ram[1]) << 16); + uint32_t clear_mask = ((uint32_t)(config->rx_ram[2]) | + (uint32_t)(config->rx_ram[3]) << 16); uint32_t ignore_mask = set_mask & clear_mask; config->state->set_mask = set_mask; @@ -69,10 +69,10 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) i = config->endpoint; - btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); + btable_ep[i].tx_addr = usb_sram_addr(config->tx_ram); btable_ep[i].tx_count = USB_GPIO_TX_PACKET_SIZE; - btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); + btable_ep[i].rx_addr = usb_sram_addr(config->rx_ram); btable_ep[i].rx_count = ((USB_GPIO_RX_PACKET_SIZE / 2) << 10); /* @@ -82,8 +82,8 @@ void usb_gpio_event(struct usb_gpio_config const *config, enum usb_ep_event evt) config->tx_ram[0] = 0; config->tx_ram[1] = 0; - STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ - (3 << 4) | /* TX Valid */ - (0 << 9) | /* Bulk EP */ + STM32_USB_EP(i) = ((i << 0) | /* Endpoint Addr*/ + (3 << 4) | /* TX Valid */ + (0 << 9) | /* Bulk EP */ (3 << 12)); /* RX Valid */ } -- cgit v1.2.1 From 99ad4e3c8ca7889623db54fbaca5658410b96397 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:25:41 -0600 Subject: util/comm-usb.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0611bfd809b0e094b0561935462030bea064230e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730609 Reviewed-by: Jeremy Bettis --- util/comm-usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/comm-usb.h b/util/comm-usb.h index f821a10fe8..e4961af800 100644 --- a/util/comm-usb.h +++ b/util/comm-usb.h @@ -34,4 +34,4 @@ int comm_init_usb(uint16_t vid, uint16_t pid); */ void comm_usb_exit(void); -#endif /* __UTIL_COMM_USB_H */ +#endif /* __UTIL_COMM_USB_H */ -- cgit v1.2.1 From 0c110ab2873d2b5146d404b3975a1fe9ed10b16b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:56 -0600 Subject: board/crota/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iffaf4cfac43a3c14400c0e740a8c52ab4313bb3b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728190 Reviewed-by: Jeremy Bettis --- board/crota/board.h | 151 +++++++++++++++++++++++----------------------------- 1 file changed, 68 insertions(+), 83 deletions(-) diff --git a/board/crota/board.h b/board/crota/board.h index 9343e1b111..5cd94147fd 100644 --- a/board/crota/board.h +++ b/board/crota/board.h @@ -22,7 +22,7 @@ #define CONFIG_MP2964 /* Sensors */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -36,14 +36,14 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_LIS2DWL #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) #define CONFIG_BODY_DETECTION -#define CONFIG_BODY_DETECTION_SENSOR BASE_ACCEL +#define CONFIG_BODY_DETECTION_SENSOR BASE_ACCEL #define CONFIG_BODY_DETECTION_VAR_NOISE_FACTOR 150 /* % */ #define CONFIG_GESTURE_DETECTION #define CONFIG_GESTURE_DETECTION_MASK BIT(CONFIG_BODY_DETECTION_SENSOR) @@ -54,7 +54,7 @@ #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -62,7 +62,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USBC_RETIMER_INTEL_BB @@ -77,17 +77,17 @@ #define CONFIG_USB_PD_FRS_PPC /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -95,35 +95,35 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL - -#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL + +#define GPIO_ID_1_EC_KB_BL_EN GPIO_EC_BATT_PRES_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT @@ -133,35 +133,35 @@ /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C1_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C1_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 -#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x54 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x58 +#define USBC_PORT_C1_SOC_BB_RETIMER_I2C_ADDR 0x54 /* Type-C connector facing Burnside Bridge retimer */ -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x56 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -181,7 +181,7 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* LED defines */ #define CONFIG_LED_ONOFF_STATES @@ -194,15 +194,15 @@ /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -222,18 +222,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum sensor_id { - LID_ACCEL = 0, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL = 0, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C1_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C1_NCT38XX, IOEX_PORT_COUNT }; enum battery_type { BATTERY_ATL, @@ -253,22 +244,16 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_LED2 = 0, /* PWM0 (white charger) */ - PWM_CH_LED1, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED2 = 0, /* PWM0 (white charger) */ + PWM_CH_LED1, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 73980b445adc2d341c2c648f1c354f3c6093b9c2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:29 -0600 Subject: board/storo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4fe321f0ba2f73b5fadabe10642f8e786e6f917c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728957 Reviewed-by: Jeremy Bettis --- board/storo/board.c | 291 +++++++++++++++++++++++----------------------------- 1 file changed, 130 insertions(+), 161 deletions(-) diff --git a/board/storo/board.c b/board/storo/board.c index d7e0305d1f..513a66c592 100644 --- a/board/storo/board.c +++ b/board/storo/board.c @@ -48,8 +48,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprints(CC_SYSTEM, format, ##args) #define INT_RECHECK_US 5000 @@ -139,34 +139,26 @@ static void pen_detect_interrupt(enum gpio_signal s) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, - [ADC_TEMP_SENSOR_3] = { - .name = "TEMP_SENSOR3", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH15 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, + [ADC_TEMP_SENSOR_3] = { .name = "TEMP_SENSOR3", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH15 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -226,14 +218,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }; /* USB Retimer */ -enum tusb544_conf { - USB_DP = 0, - USB_DP_INV, - USB, - USB_INV, - DP, - DP_INV -}; +enum tusb544_conf { USB_DP = 0, USB_DP_INV, USB, USB_INV, DP, DP_INV }; /* * Registers we care about of are all the same between NCS8510 and TUSB544, @@ -246,33 +231,32 @@ enum tusb544_conf { */ static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state) { - int rv = EC_SUCCESS; + int rv = EC_SUCCESS; int reg; enum tusb544_conf usb_mode = 0; if (mux_state & USB_PD_MUX_USB_ENABLED) { if (mux_state & USB_PD_MUX_DP_ENABLED) { /* USB with DP */ - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_DP_INV - : USB_DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_DP_INV : + USB_DP; } else { /* USB without DP */ - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? USB_INV - : USB; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? + USB_INV : + USB; } } else if (mux_state & USB_PD_MUX_DP_ENABLED) { /* DP without USB */ - usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? DP_INV - : DP; + usb_mode = (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? DP_INV : + DP; } else { return EC_SUCCESS; } - rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL6, ®); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6, + ®); if (rv) return rv; @@ -280,52 +264,52 @@ static int board_tusb544_set(const struct usb_mux *me, mux_state_t mux_state) reg &= ~TUSB544_VOD_DCGAIN_SEL; reg |= (TUSB544_VOD_DCGAIN_SETTING_5 << 2); - rv = i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL6, reg); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags, TUSB544_REG_GENERAL6, + reg); if (rv) return rv; /* Write the retimer config byte */ if (usb_mode == USB_INV) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x15); + TUSB544_REG_GENERAL4, 0x15); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_1, 0xff); + TUSB544_REG_USB3_1_1, 0xff); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_2, 0xff); + TUSB544_REG_USB3_1_2, 0xff); } else if (usb_mode == USB) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x11); + TUSB544_REG_GENERAL4, 0x11); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_1, 0xff); + TUSB544_REG_USB3_1_1, 0xff); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_2, 0xff); + TUSB544_REG_USB3_1_2, 0xff); } else if (usb_mode == USB_DP_INV) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x1F); + TUSB544_REG_GENERAL4, 0x1F); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_1, 0xff); + TUSB544_REG_USB3_1_1, 0xff); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_2, 0xff); + TUSB544_REG_USB3_1_2, 0xff); } else if (usb_mode == USB_DP) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x1B); + TUSB544_REG_GENERAL4, 0x1B); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_1, 0xff); + TUSB544_REG_USB3_1_1, 0xff); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_USB3_1_2, 0xff); + TUSB544_REG_USB3_1_2, 0xff); } else if (usb_mode == DP_INV) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x1E); + TUSB544_REG_GENERAL4, 0x1E); } else if (usb_mode == DP) { rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_GENERAL4, 0x1A); + TUSB544_REG_GENERAL4, 0x1A); } rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_DISPLAYPORT_1, 0x66); + TUSB544_REG_DISPLAYPORT_1, 0x66); rv |= i2c_write8(me->i2c_port, me->i2c_addr_flags, - TUSB544_REG_DISPLAYPORT_2, 0x66); + TUSB544_REG_DISPLAYPORT_2, 0x66); if (rv) return EC_ERROR_UNKNOWN; else @@ -461,8 +445,7 @@ int board_is_sourcing_vbus(int port) int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -526,9 +509,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 3; *kp_div = 14; @@ -553,17 +535,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct accelgyro_saved_data_t g_bma253_data; static struct bmi_drv_data_t g_bmi160_data; @@ -639,11 +617,9 @@ struct motion_sensor_t motion_sensors[] = { unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); -static const mat33_fp_t lid_lis2dwl_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_lis2dwl_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* Lid accel private data */ static struct stprivate_data g_lis2dwl_data; @@ -675,11 +651,9 @@ struct motion_sensor_t lis2dwl_lid_accel = { }, }; -static const mat33_fp_t lid_KX022_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_KX022_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static struct kionix_accel_data g_kx022_data; struct motion_sensor_t kx022_lid_accel = { @@ -710,11 +684,9 @@ struct motion_sensor_t kx022_lid_accel = { }; static struct icm_drv_data_t g_icm42607_data; -const mat33_fp_t based_ref_icm42607 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t based_ref_icm42607 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t icm42607_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -743,29 +715,26 @@ struct motion_sensor_t icm42607_base_accel = { }; struct motion_sensor_t icm42607_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM42607, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &icm42607_drv, - .mutex = &g_base_mutex, - .drv_data = &g_icm42607_data, - .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &based_ref_icm42607, - .min_frequency = ICM42607_GYRO_MIN_FREQ, - .max_frequency = ICM42607_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM42607, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm42607_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm42607_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &based_ref_icm42607, + .min_frequency = ICM42607_GYRO_MIN_FREQ, + .max_frequency = ICM42607_GYRO_MAX_FREQ, }; - static struct bmi_drv_data_t g_bmi220_data; -const mat33_fp_t based_ref_bmi220 = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t based_ref_bmi220 = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t bmi220_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, @@ -794,20 +763,20 @@ struct motion_sensor_t bmi220_base_accel = { }; struct motion_sensor_t bmi220_base_gyro = { - .name = "Base Gyro", - .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI220, - .type = MOTIONSENSE_TYPE_GYRO, - .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi260_drv, - .mutex = &g_base_mutex, - .drv_data = &g_bmi220_data, - .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, - .default_range = 1000, /* dps */ - .rot_standard_ref = &based_ref_bmi220, - .min_frequency = BMI_GYRO_MIN_FREQ, - .max_frequency = BMI_GYRO_MAX_FREQ, + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMI220, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &bmi260_drv, + .mutex = &g_base_mutex, + .drv_data = &g_bmi220_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &based_ref_bmi220, + .min_frequency = BMI_GYRO_MIN_FREQ, + .max_frequency = BMI_GYRO_MAX_FREQ, }; void board_init(void) @@ -846,13 +815,13 @@ void board_init(void) if (board_id > 2) { if (get_cbi_fw_config_tablet_mode()) { if (get_cbi_ssfc_base_sensor() == - SSFC_SENSOR_ICM42607) { + SSFC_SENSOR_ICM42607) { motion_sensors[BASE_ACCEL] = - icm42607_base_accel; + icm42607_base_accel; motion_sensors[BASE_GYRO] = icm42607_base_gyro; CPRINTF("BASE GYRO is ICM42607"); } else if (get_cbi_ssfc_base_sensor() == - SSFC_SENSOR_BMI220) { + SSFC_SENSOR_BMI220) { motion_sensors[BASE_ACCEL] = bmi220_base_accel; motion_sensors[BASE_GYRO] = bmi220_base_gyro; CPRINTF("BASE GYRO is BMI220"); @@ -864,7 +833,7 @@ void board_init(void) motion_sensors[LID_ACCEL] = lis2dwl_lid_accel; CPRINTF("LID_ACCEL is LIS2DWL"); } else if (get_cbi_ssfc_lid_sensor() == - SSFC_SENSOR_KX022) { + SSFC_SENSOR_KX022) { motion_sensors[LID_ACCEL] = kx022_lid_accel; CPRINTF("LID_ACCEL is KX022"); } else { @@ -878,7 +847,7 @@ void board_init(void) * line to float. */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); } } else { if (get_cbi_ssfc_base_sensor() == SSFC_SENSOR_ICM42607) { @@ -908,34 +877,34 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); void motion_interrupt(enum gpio_signal signal) { - switch (get_cbi_ssfc_base_sensor()) { - case SSFC_SENSOR_ICM42607: - icm42607_interrupt(signal); - break; - case SSFC_SENSOR_BMI220: - bmi260_interrupt(signal); - break; - case SSFC_SENSOR_BMI160: - default: - bmi160_interrupt(signal); - break; - } + switch (get_cbi_ssfc_base_sensor()) { + case SSFC_SENSOR_ICM42607: + icm42607_interrupt(signal); + break; + case SSFC_SENSOR_BMI220: + bmi260_interrupt(signal); + break; + case SSFC_SENSOR_BMI160: + default: + bmi160_interrupt(signal); + break; + } } /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Cpu", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Cpu", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 83de9b988cf98220617f51355ad50f4fc4757806 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:29 -0600 Subject: board/baklava/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I442af4730563d232a5861f99af01149fe6f46724 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727997 Reviewed-by: Jeremy Bettis --- board/baklava/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/baklava/board.h b/board/baklava/board.h index e061d2342d..1dca7bbf4a 100644 --- a/board/baklava/board.h +++ b/board/baklava/board.h @@ -21,8 +21,8 @@ #undef CONFIG_FLASH_PSTATE_LOCKED /* USB Type C and USB PD defines */ -#define USB_PD_PORT_HOST 0 -#define USB_PD_PORT_USB3 1 +#define USB_PD_PORT_HOST 0 +#define USB_PD_PORT_USB3 1 /* * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc @@ -40,9 +40,9 @@ #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 /* I2C port names */ -#define I2C_PORT_I2C1 0 -#define I2C_PORT_I2C2 1 -#define I2C_PORT_I2C3 2 +#define I2C_PORT_I2C1 0 +#define I2C_PORT_I2C2 1 +#define I2C_PORT_I2C3 2 /* Required symbolic I2C port names */ #define I2C_PORT_MP4245 I2C_PORT_I2C3 @@ -68,7 +68,7 @@ #define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN #define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN -enum debug_gpio { +enum debug_gpio { TRIGGER_1 = 0, TRIGGER_2, }; -- cgit v1.2.1 From ac77e7b17b6438c293f6120a57389c5ff80b7c6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:09 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I67152500692c736979c91855bba1337beabc7a2a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730934 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c index 0a27fd98f0..10c6bdf207 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_host_command.c @@ -27,8 +27,7 @@ host_command_reboot_ap_on_g3(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, - host_command_reboot_ap_on_g3, +DECLARE_HOST_COMMAND(EC_CMD_REBOOT_AP_ON_G3, host_command_reboot_ap_on_g3, EC_VER_MASK(0) | EC_VER_MASK(1)); /* End of host commands */ -- cgit v1.2.1 From 55346e35ecbf88969dce82ed08d8ab77e49e9970 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:48 -0600 Subject: board/galtic/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e6adf207248354f881ae167c4b88baaea13053c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728385 Reviewed-by: Jeremy Bettis --- board/galtic/cbi_ssfc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/galtic/cbi_ssfc.c b/board/galtic/cbi_ssfc.c index c760f37573..74deb858a0 100644 --- a/board/galtic/cbi_ssfc.c +++ b/board/galtic/cbi_ssfc.c @@ -27,15 +27,15 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } enum ec_ssfc_mux_redriver get_cbi_ssfc_mux_redriver(void) { - return (enum ec_ssfc_mux_redriver) cached_ssfc.mux_redriver; + return (enum ec_ssfc_mux_redriver)cached_ssfc.mux_redriver; } -- cgit v1.2.1 From 8a1a50222de05416bf51b699d39df0c0f0664885 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:27:05 -0600 Subject: board/coffeecake/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I398395cb76a11b546a0b5ddbe59c356eeae40d3f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728170 Reviewed-by: Jeremy Bettis --- board/coffeecake/board.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/board/coffeecake/board.c b/board/coffeecake/board.c index b344a5f745..f911100cfd 100644 --- a/board/coffeecake/board.c +++ b/board/coffeecake/board.c @@ -31,13 +31,11 @@ void vbus_event(enum gpio_signal signal); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "charger", - .port = I2C_PORT_SY21612, - .kbps = 400, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, + { .name = "charger", + .port = I2C_PORT_SY21612, + .kbps = 400, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -153,7 +151,7 @@ void board_config_pre_init(void) /* Set 5Vsafe Vdac */ board_set_usb_output_voltage(5000); /* Remap USART DMA to match the USART driver */ - STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10);/* Remap USART1 RX/TX DMA */ + STM32_SYSCFG_CFGR1 |= BIT(9) | BIT(10); /* Remap USART1 RX/TX DMA */ } #ifdef CONFIG_SPI_FLASH @@ -197,10 +195,9 @@ static void factory_validation_deferred(void) /* test mcdp via serial to validate function */ if (!mcdp_get_info(&info) && (MCDP_FAMILY(info.family) == 0x0010) && - (MCDP_CHIPID(info.chipid) == 0x2850)) { + (MCDP_CHIPID(info.chipid) == 0x2850)) { pd_log_event(PD_EVENT_VIDEO_CODEC, - PD_LOG_PORT_SIZE(0, sizeof(info)), - 0, &info); + PD_LOG_PORT_SIZE(0, sizeof(info)), 0, &info); } mcdp_disable(); @@ -215,7 +212,8 @@ static void board_post_init(void) * DUT powered - DRP SINK */ pd_set_dual_role(0, gpio_get_level(GPIO_AC_PRESENT_L) ? - PD_DRP_FORCE_SINK : PD_DRP_FORCE_SOURCE); + PD_DRP_FORCE_SINK : + PD_DRP_FORCE_SOURCE); } DECLARE_DEFERRED(board_post_init); @@ -233,10 +231,11 @@ static void board_init(void) gpio_enable_interrupt(GPIO_CHARGER_INT); gpio_enable_interrupt(GPIO_USB_C_VBUS_DET_L); /* Set PD_DISCHARGE initial state */ - gpio_set_level(GPIO_PD_DISCHARGE, gpio_get_level(GPIO_USB_C_VBUS_DET_L)); + gpio_set_level(GPIO_PD_DISCHARGE, + gpio_get_level(GPIO_USB_C_VBUS_DET_L)); /* Delay needed to allow HDMI MCU to boot. */ - hook_call_deferred(&factory_validation_deferred_data, 200*MSEC); + hook_call_deferred(&factory_validation_deferred_data, 200 * MSEC); /* Initialize buck-boost converter */ hook_call_deferred(&board_post_init_data, 0); } @@ -246,14 +245,14 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)}, - [ADC_VBUS_MON] = {"VBUS_MON", 13200, 4096, 0, STM32_AIN(2)}, - [ADC_DAC_REF_TP28] = {"DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4)}, - [ADC_DAC_VOLT] = {"DAC_VOLT", 3300, 4096, 0, STM32_AIN(5)}, + [ADC_CH_CC1_PD] = { "USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1) }, + [ADC_VBUS_MON] = { "VBUS_MON", 13200, 4096, 0, STM32_AIN(2) }, + [ADC_DAC_REF_TP28] = { "DAC_REF_TP28", 3300, 4096, 0, STM32_AIN(4) }, + [ADC_DAC_VOLT] = { "DAC_VOLT", 3300, 4096, 0, STM32_AIN(5) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -const void * const usb_strings[] = { +const void *const usb_strings[] = { [USB_STR_DESC] = usb_string_desc, [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), [USB_STR_PRODUCT] = USB_STRING_DESC("Hoho"), -- cgit v1.2.1 From 5e829026f862257fc59682dff6bfbcf89d4416d6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:30 -0600 Subject: board/oak/board_revs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I67f6f876810d1cf70087b81be51265f16068d8b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728791 Reviewed-by: Jeremy Bettis --- board/oak/board_revs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/oak/board_revs.h b/board/oak/board_revs.h index 34fc4bfc88..8d4d65be9b 100644 --- a/board/oak/board_revs.h +++ b/board/oak/board_revs.h @@ -12,7 +12,7 @@ #define OAK_REV3 3 #define OAK_REV4 4 #define OAK_REV5 5 -#define OAK_REV_LAST OAK_REV5 +#define OAK_REV_LAST OAK_REV5 #define OAK_REV_DEFAULT OAK_REV5 #if !defined(BOARD_REV) -- cgit v1.2.1 From 6895c72184c089767f2708ba0edc2926c5adc41f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:28:43 -0600 Subject: zephyr/emul/emul_bma255.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9bcbf4a73816b3f04fc18d404a811faefbcf5e2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730685 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_bma255.c | 314 +++++++++++++++++++++++----------------------- 1 file changed, 156 insertions(+), 158 deletions(-) diff --git a/zephyr/emul/emul_bma255.c b/zephyr/emul/emul_bma255.c index cd790dbc99..afd9f5fb7b 100644 --- a/zephyr/emul/emul_bma255.c +++ b/zephyr/emul/emul_bma255.c @@ -19,7 +19,7 @@ LOG_MODULE_REGISTER(emul_bma255); #include "driver/accel_bma2x2.h" -#define BMA_DATA_FROM_I2C_EMUL(_emul) \ +#define BMA_DATA_FROM_I2C_EMUL(_emul) \ CONTAINER_OF(CONTAINER_OF(_emul, struct i2c_common_emul_data, emul), \ struct bma_emul_data, common) @@ -210,18 +210,18 @@ void bma_emul_set_off(struct i2c_emul *emul, int axis, int16_t val) switch (axis) { case BMA_EMUL_AXIS_X: data->off_x = val; - data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = bma_emul_off_to_nvm( - data->off_x); + data->reg[BMA2x2_OFFSET_X_AXIS_ADDR] = + bma_emul_off_to_nvm(data->off_x); break; case BMA_EMUL_AXIS_Y: data->off_y = val; - data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = bma_emul_off_to_nvm( - data->off_y); + data->reg[BMA2x2_OFFSET_Y_AXIS_ADDR] = + bma_emul_off_to_nvm(data->off_y); break; case BMA_EMUL_AXIS_Z: data->off_z = val; - data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = bma_emul_off_to_nvm( - data->off_z); + data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = + bma_emul_off_to_nvm(data->off_z); break; } } @@ -312,70 +312,70 @@ void bma_emul_set_err_on_msb_first(struct i2c_emul *emul, bool set) /** Mask reserved bits in each register of BMA255 */ static const uint8_t bma_emul_rsvd_mask[] = { - [BMA2x2_CHIP_ID_ADDR] = 0x00, - [0x01] = 0xff, /* Reserved */ - [BMA2x2_X_AXIS_LSB_ADDR] = 0x0e, - [BMA2x2_X_AXIS_MSB_ADDR] = 0x00, - [BMA2x2_Y_AXIS_LSB_ADDR] = 0x0e, - [BMA2x2_Y_AXIS_MSB_ADDR] = 0x00, - [BMA2x2_Z_AXIS_LSB_ADDR] = 0x0e, - [BMA2x2_Z_AXIS_MSB_ADDR] = 0x00, - [BMA2x2_TEMP_ADDR] = 0x00, - [BMA2x2_STAT1_ADDR] = 0x00, - [BMA2x2_STAT2_ADDR] = 0x1f, - [BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00, - [BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00, - [0x0d] = 0xff, /* Reserved */ - [BMA2x2_STAT_FIFO_ADDR] = 0x00, - [BMA2x2_RANGE_SELECT_ADDR] = 0xf0, - [BMA2x2_BW_SELECT_ADDR] = 0xe0, - [BMA2x2_MODE_CTRL_ADDR] = 0x01, - [BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x9f, - [BMA2x2_DATA_CTRL_ADDR] = 0x3f, - [BMA2x2_RST_ADDR] = 0x00, - [0x15] = 0xff, /* Reserved */ - [BMA2x2_INTR_ENABLE1_ADDR] = 0x08, - [BMA2x2_INTR_ENABLE2_ADDR] = 0x80, - [BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0xf0, - [BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00, - [BMA2x2_INTR_DATA_SELECT_ADDR] = 0x18, - [BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00, - [0x1c] = 0xff, /* Reserved */ - [0x1d] = 0xff, /* Reserved */ - [BMA2x2_INTR_SOURCE_ADDR] = 0xc0, - [0x1f] = 0xff, /* Reserved */ - [BMA2x2_INTR_SET_ADDR] = 0xf0, - [BMA2x2_INTR_CTRL_ADDR] = 0x70, - [BMA2x2_LOW_DURN_ADDR] = 0x00, - [BMA2x2_LOW_THRES_ADDR] = 0x00, - [BMA2x2_LOW_HIGH_HYST_ADDR] = 0x38, - [BMA2x2_HIGH_DURN_ADDR] = 0x00, - [BMA2x2_HIGH_THRES_ADDR] = 0x00, - [BMA2x2_SLOPE_DURN_ADDR] = 0x00, - [BMA2x2_SLOPE_THRES_ADDR] = 0x00, - [BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x00, - [BMA2x2_TAP_PARAM_ADDR] = 0x38, - [BMA2x2_TAP_THRES_ADDR] = 0x20, - [BMA2x2_ORIENT_PARAM_ADDR] = 0x80, - [BMA2x2_THETA_BLOCK_ADDR] = 0x80, - [BMA2x2_THETA_FLAT_ADDR] = 0xc0, - [BMA2x2_FLAT_HOLD_TIME_ADDR] = 0xc8, - [BMA2x2_FIFO_WML_TRIG] = 0xc0, - [0x31] = 0xff, /* Reserved */ - [BMA2x2_SELFTEST_ADDR] = 0xf8, - [BMA2x2_EEPROM_CTRL_ADDR] = 0x00, - [BMA2x2_SERIAL_CTRL_ADDR] = 0xf8, - [0x35] = 0xff, /* Reserved */ - [BMA2x2_OFFSET_CTRL_ADDR] = 0x08, - [BMA2x2_OFC_SETTING_ADDR] = 0x80, - [BMA2x2_OFFSET_X_AXIS_ADDR] = 0x00, - [BMA2x2_OFFSET_Y_AXIS_ADDR] = 0x00, - [BMA2x2_OFFSET_Z_AXIS_ADDR] = 0x00, - [BMA2x2_GP0_ADDR] = 0x00, - [BMA2x2_GP1_ADDR] = 0x00, - [0x3d] = 0xff, /* Reserved */ - [BMA2x2_FIFO_MODE_ADDR] = 0x3c, - [BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00, + [BMA2x2_CHIP_ID_ADDR] = 0x00, + [0x01] = 0xff, /* Reserved */ + [BMA2x2_X_AXIS_LSB_ADDR] = 0x0e, + [BMA2x2_X_AXIS_MSB_ADDR] = 0x00, + [BMA2x2_Y_AXIS_LSB_ADDR] = 0x0e, + [BMA2x2_Y_AXIS_MSB_ADDR] = 0x00, + [BMA2x2_Z_AXIS_LSB_ADDR] = 0x0e, + [BMA2x2_Z_AXIS_MSB_ADDR] = 0x00, + [BMA2x2_TEMP_ADDR] = 0x00, + [BMA2x2_STAT1_ADDR] = 0x00, + [BMA2x2_STAT2_ADDR] = 0x1f, + [BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00, + [BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00, + [0x0d] = 0xff, /* Reserved */ + [BMA2x2_STAT_FIFO_ADDR] = 0x00, + [BMA2x2_RANGE_SELECT_ADDR] = 0xf0, + [BMA2x2_BW_SELECT_ADDR] = 0xe0, + [BMA2x2_MODE_CTRL_ADDR] = 0x01, + [BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x9f, + [BMA2x2_DATA_CTRL_ADDR] = 0x3f, + [BMA2x2_RST_ADDR] = 0x00, + [0x15] = 0xff, /* Reserved */ + [BMA2x2_INTR_ENABLE1_ADDR] = 0x08, + [BMA2x2_INTR_ENABLE2_ADDR] = 0x80, + [BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0xf0, + [BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00, + [BMA2x2_INTR_DATA_SELECT_ADDR] = 0x18, + [BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00, + [0x1c] = 0xff, /* Reserved */ + [0x1d] = 0xff, /* Reserved */ + [BMA2x2_INTR_SOURCE_ADDR] = 0xc0, + [0x1f] = 0xff, /* Reserved */ + [BMA2x2_INTR_SET_ADDR] = 0xf0, + [BMA2x2_INTR_CTRL_ADDR] = 0x70, + [BMA2x2_LOW_DURN_ADDR] = 0x00, + [BMA2x2_LOW_THRES_ADDR] = 0x00, + [BMA2x2_LOW_HIGH_HYST_ADDR] = 0x38, + [BMA2x2_HIGH_DURN_ADDR] = 0x00, + [BMA2x2_HIGH_THRES_ADDR] = 0x00, + [BMA2x2_SLOPE_DURN_ADDR] = 0x00, + [BMA2x2_SLOPE_THRES_ADDR] = 0x00, + [BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x00, + [BMA2x2_TAP_PARAM_ADDR] = 0x38, + [BMA2x2_TAP_THRES_ADDR] = 0x20, + [BMA2x2_ORIENT_PARAM_ADDR] = 0x80, + [BMA2x2_THETA_BLOCK_ADDR] = 0x80, + [BMA2x2_THETA_FLAT_ADDR] = 0xc0, + [BMA2x2_FLAT_HOLD_TIME_ADDR] = 0xc8, + [BMA2x2_FIFO_WML_TRIG] = 0xc0, + [0x31] = 0xff, /* Reserved */ + [BMA2x2_SELFTEST_ADDR] = 0xf8, + [BMA2x2_EEPROM_CTRL_ADDR] = 0x00, + [BMA2x2_SERIAL_CTRL_ADDR] = 0xf8, + [0x35] = 0xff, /* Reserved */ + [BMA2x2_OFFSET_CTRL_ADDR] = 0x08, + [BMA2x2_OFC_SETTING_ADDR] = 0x80, + [BMA2x2_OFFSET_X_AXIS_ADDR] = 0x00, + [BMA2x2_OFFSET_Y_AXIS_ADDR] = 0x00, + [BMA2x2_OFFSET_Z_AXIS_ADDR] = 0x00, + [BMA2x2_GP0_ADDR] = 0x00, + [BMA2x2_GP1_ADDR] = 0x00, + [0x3d] = 0xff, /* Reserved */ + [BMA2x2_FIFO_MODE_ADDR] = 0x3c, + [BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00, }; /** @@ -414,65 +414,65 @@ static void bma_emul_reset(struct i2c_emul *emul) data = BMA_DATA_FROM_I2C_EMUL(emul); - data->reg[BMA2x2_CHIP_ID_ADDR] = 0xfa; - data->reg[0x01] = 0x00; /* Reserved */ - data->reg[BMA2x2_X_AXIS_LSB_ADDR] = 0x00; - data->reg[BMA2x2_X_AXIS_MSB_ADDR] = 0x00; - data->reg[BMA2x2_Y_AXIS_LSB_ADDR] = 0x00; - data->reg[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00; - data->reg[BMA2x2_Z_AXIS_LSB_ADDR] = 0x00; - data->reg[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00; - data->reg[BMA2x2_TEMP_ADDR] = 0x00; - data->reg[BMA2x2_STAT1_ADDR] = 0x00; - data->reg[BMA2x2_STAT2_ADDR] = 0x00; - data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00; - data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00; - data->reg[0x0d] = 0xff; /* Reserved */ - data->reg[BMA2x2_STAT_FIFO_ADDR] = 0x00; - data->reg[BMA2x2_RANGE_SELECT_ADDR] = 0x03; - data->reg[BMA2x2_BW_SELECT_ADDR] = 0x0f; - data->reg[BMA2x2_MODE_CTRL_ADDR] = 0x00; - data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x00; - data->reg[BMA2x2_DATA_CTRL_ADDR] = 0x00; - data->reg[BMA2x2_RST_ADDR] = 0x00; - data->reg[0x15] = 0xff; /* Reserved */ - data->reg[BMA2x2_INTR_ENABLE1_ADDR] = 0x00; - data->reg[BMA2x2_INTR_ENABLE2_ADDR] = 0x00; - data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0x00; - data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00; - data->reg[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x00; - data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00; - data->reg[0x1c] = 0xff; /* Reserved */ - data->reg[0x1d] = 0xff; /* Reserved */ - data->reg[BMA2x2_INTR_SOURCE_ADDR] = 0x00; - data->reg[0x1f] = 0xff; /* Reserved */ - data->reg[BMA2x2_INTR_SET_ADDR] = 0x05; - data->reg[BMA2x2_INTR_CTRL_ADDR] = 0x00; - data->reg[BMA2x2_LOW_DURN_ADDR] = 0x09; - data->reg[BMA2x2_LOW_THRES_ADDR] = 0x30; - data->reg[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x81; - data->reg[BMA2x2_HIGH_DURN_ADDR] = 0x0f; - data->reg[BMA2x2_HIGH_THRES_ADDR] = 0xc0; - data->reg[BMA2x2_SLOPE_DURN_ADDR] = 0x00; - data->reg[BMA2x2_SLOPE_THRES_ADDR] = 0x14; - data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x14; - data->reg[BMA2x2_TAP_PARAM_ADDR] = 0x04; - data->reg[BMA2x2_TAP_THRES_ADDR] = 0x0a; - data->reg[BMA2x2_ORIENT_PARAM_ADDR] = 0x18; - data->reg[BMA2x2_THETA_BLOCK_ADDR] = 0x48; - data->reg[BMA2x2_THETA_FLAT_ADDR] = 0x08; - data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0x11; - data->reg[BMA2x2_FIFO_WML_TRIG] = 0x00; - data->reg[0x31] = 0xff; /* Reserved */ - data->reg[BMA2x2_SELFTEST_ADDR] = 0x00; - data->reg[BMA2x2_EEPROM_CTRL_ADDR] = 0xf0; - data->reg[BMA2x2_SERIAL_CTRL_ADDR] = 0x00; - data->reg[0x35] = 0x00; /* Reserved */ - data->reg[BMA2x2_OFFSET_CTRL_ADDR] = 0x10; - data->reg[BMA2x2_OFC_SETTING_ADDR] = 0x00; - data->reg[0x3d] = 0xff; /* Reserved */ - data->reg[BMA2x2_FIFO_MODE_ADDR] = 0x00; - data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00; + data->reg[BMA2x2_CHIP_ID_ADDR] = 0xfa; + data->reg[0x01] = 0x00; /* Reserved */ + data->reg[BMA2x2_X_AXIS_LSB_ADDR] = 0x00; + data->reg[BMA2x2_X_AXIS_MSB_ADDR] = 0x00; + data->reg[BMA2x2_Y_AXIS_LSB_ADDR] = 0x00; + data->reg[BMA2x2_Y_AXIS_MSB_ADDR] = 0x00; + data->reg[BMA2x2_Z_AXIS_LSB_ADDR] = 0x00; + data->reg[BMA2x2_Z_AXIS_MSB_ADDR] = 0x00; + data->reg[BMA2x2_TEMP_ADDR] = 0x00; + data->reg[BMA2x2_STAT1_ADDR] = 0x00; + data->reg[BMA2x2_STAT2_ADDR] = 0x00; + data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00; + data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00; + data->reg[0x0d] = 0xff; /* Reserved */ + data->reg[BMA2x2_STAT_FIFO_ADDR] = 0x00; + data->reg[BMA2x2_RANGE_SELECT_ADDR] = 0x03; + data->reg[BMA2x2_BW_SELECT_ADDR] = 0x0f; + data->reg[BMA2x2_MODE_CTRL_ADDR] = 0x00; + data->reg[BMA2x2_LOW_NOISE_CTRL_ADDR] = 0x00; + data->reg[BMA2x2_DATA_CTRL_ADDR] = 0x00; + data->reg[BMA2x2_RST_ADDR] = 0x00; + data->reg[0x15] = 0xff; /* Reserved */ + data->reg[BMA2x2_INTR_ENABLE1_ADDR] = 0x00; + data->reg[BMA2x2_INTR_ENABLE2_ADDR] = 0x00; + data->reg[BMA2x2_INTR_SLOW_NO_MOTION_ADDR] = 0x00; + data->reg[BMA2x2_INTR1_PAD_SELECT_ADDR] = 0x00; + data->reg[BMA2x2_INTR_DATA_SELECT_ADDR] = 0x00; + data->reg[BMA2x2_INTR2_PAD_SELECT_ADDR] = 0x00; + data->reg[0x1c] = 0xff; /* Reserved */ + data->reg[0x1d] = 0xff; /* Reserved */ + data->reg[BMA2x2_INTR_SOURCE_ADDR] = 0x00; + data->reg[0x1f] = 0xff; /* Reserved */ + data->reg[BMA2x2_INTR_SET_ADDR] = 0x05; + data->reg[BMA2x2_INTR_CTRL_ADDR] = 0x00; + data->reg[BMA2x2_LOW_DURN_ADDR] = 0x09; + data->reg[BMA2x2_LOW_THRES_ADDR] = 0x30; + data->reg[BMA2x2_LOW_HIGH_HYST_ADDR] = 0x81; + data->reg[BMA2x2_HIGH_DURN_ADDR] = 0x0f; + data->reg[BMA2x2_HIGH_THRES_ADDR] = 0xc0; + data->reg[BMA2x2_SLOPE_DURN_ADDR] = 0x00; + data->reg[BMA2x2_SLOPE_THRES_ADDR] = 0x14; + data->reg[BMA2x2_SLOW_NO_MOTION_THRES_ADDR] = 0x14; + data->reg[BMA2x2_TAP_PARAM_ADDR] = 0x04; + data->reg[BMA2x2_TAP_THRES_ADDR] = 0x0a; + data->reg[BMA2x2_ORIENT_PARAM_ADDR] = 0x18; + data->reg[BMA2x2_THETA_BLOCK_ADDR] = 0x48; + data->reg[BMA2x2_THETA_FLAT_ADDR] = 0x08; + data->reg[BMA2x2_FLAT_HOLD_TIME_ADDR] = 0x11; + data->reg[BMA2x2_FIFO_WML_TRIG] = 0x00; + data->reg[0x31] = 0xff; /* Reserved */ + data->reg[BMA2x2_SELFTEST_ADDR] = 0x00; + data->reg[BMA2x2_EEPROM_CTRL_ADDR] = 0xf0; + data->reg[BMA2x2_SERIAL_CTRL_ADDR] = 0x00; + data->reg[0x35] = 0x00; /* Reserved */ + data->reg[BMA2x2_OFFSET_CTRL_ADDR] = 0x10; + data->reg[BMA2x2_OFC_SETTING_ADDR] = 0x00; + data->reg[0x3d] = 0xff; /* Reserved */ + data->reg[BMA2x2_FIFO_MODE_ADDR] = 0x00; + data->reg[BMA2x2_FIFO_DATA_OUTPUT_ADDR] = 0x00; /* Restore registers backed in NVM */ bma_emul_restore_nvm(emul); @@ -532,7 +532,8 @@ static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val) } writes_rem = (data->reg[BMA2x2_EEPROM_CTRL_ADDR] & - BMA2x2_EEPROM_REMAIN_MSK) >> BMA2x2_EEPROM_REMAIN_OFF; + BMA2x2_EEPROM_REMAIN_MSK) >> + BMA2x2_EEPROM_REMAIN_OFF; /* Trigger write is set, write is unlocked and writes remaining */ if (val & BMA2x2_EEPROM_PROG && data->reg[BMA2x2_EEPROM_CTRL_ADDR] & BMA2x2_EEPROM_PROG_EN && @@ -544,10 +545,9 @@ static int bma_emul_handle_nvm_write(struct i2c_emul *emul, uint8_t val) data->nvm_gp1 = data->reg[BMA2x2_GP1_ADDR]; /* Decrement number of remaining writes and save it in reg */ writes_rem--; - data->reg[BMA2x2_EEPROM_CTRL_ADDR] &= - ~BMA2x2_EEPROM_REMAIN_MSK; + data->reg[BMA2x2_EEPROM_CTRL_ADDR] &= ~BMA2x2_EEPROM_REMAIN_MSK; data->reg[BMA2x2_EEPROM_CTRL_ADDR] |= - writes_rem << BMA2x2_EEPROM_REMAIN_OFF; + writes_rem << BMA2x2_EEPROM_REMAIN_OFF; } return 0; @@ -564,10 +564,10 @@ static void bma_emul_clear_int(struct i2c_emul *emul) data = BMA_DATA_FROM_I2C_EMUL(emul); - data->reg[BMA2x2_STAT1_ADDR] = 0x00; - data->reg[BMA2x2_STAT2_ADDR] = 0x00; - data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00; - data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00; + data->reg[BMA2x2_STAT1_ADDR] = 0x00; + data->reg[BMA2x2_STAT2_ADDR] = 0x00; + data->reg[BMA2x2_STAT_TAP_SLOPE_ADDR] = 0x00; + data->reg[BMA2x2_STAT_ORIENT_HIGH_ADDR] = 0x00; } /** @@ -631,7 +631,6 @@ static int bma_emul_handle_off_comp(struct i2c_emul *emul, uint8_t val) data->reg[BMA2x2_OFFSET_Z_AXIS_ADDR] = 0; } - trigger = (val & BMA2x2_OFFSET_TRIGGER_MASK) >> BMA2x2_OFFSET_TRIGGER_OFF; @@ -717,7 +716,6 @@ static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes) return -EIO; } - switch (reg) { case BMA2x2_RST_ADDR: if (val == BMA2x2_CMD_SOFT_RESET) { @@ -745,9 +743,9 @@ static int bma_emul_handle_write(struct i2c_emul *emul, int reg, int bytes) /* Only slow compensation bits are RW */ val &= BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y | BMA2x2_OFFSET_CAL_SLOW_Z; - val |= data->reg[reg] & ~(BMA2x2_OFFSET_CAL_SLOW_X | - BMA2x2_OFFSET_CAL_SLOW_Y | - BMA2x2_OFFSET_CAL_SLOW_Z); + val |= data->reg[reg] & + ~(BMA2x2_OFFSET_CAL_SLOW_X | BMA2x2_OFFSET_CAL_SLOW_Y | + BMA2x2_OFFSET_CAL_SLOW_Z); break; /* Change internal offset to value set in I2C message */ case BMA2x2_OFFSET_X_AXIS_ADDR: @@ -961,8 +959,7 @@ static int bma_emul_write_byte(struct i2c_emul *emul, int reg, uint8_t val, * * @return 0 indicating success (always) */ -static int bma_emul_init(const struct emul *emul, - const struct device *parent) +static int bma_emul_init(const struct emul *emul, const struct device *parent) { const struct i2c_common_emul_cfg *cfg = emul->cfg; struct i2c_common_emul_data *data = cfg->data; @@ -981,7 +978,7 @@ static int bma_emul_init(const struct emul *emul, return ret; } -#define BMA255_EMUL(n) \ +#define BMA255_EMUL(n) \ static struct bma_emul_data bma_emul_data_##n = { \ .nvm_x = DT_INST_PROP(n, nvm_off_x), \ .nvm_y = DT_INST_PROP(n, nvm_off_y), \ @@ -1010,27 +1007,28 @@ static int bma_emul_init(const struct emul *emul, .finish_read = NULL, \ .access_reg = bma_emul_access_reg, \ }, \ - }; \ - \ - static const struct i2c_common_emul_cfg bma_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ - .dev_label = DT_INST_LABEL(n), \ - .data = &bma_emul_data_##n.common, \ - .addr = DT_INST_REG_ADDR(n), \ - }; \ - EMUL_DEFINE(bma_emul_init, DT_DRV_INST(n), &bma_emul_cfg_##n, \ + }; \ + \ + static const struct i2c_common_emul_cfg bma_emul_cfg_##n = { \ + .i2c_label = DT_INST_BUS_LABEL(n), \ + .dev_label = DT_INST_LABEL(n), \ + .data = &bma_emul_data_##n.common, \ + .addr = DT_INST_REG_ADDR(n), \ + }; \ + EMUL_DEFINE(bma_emul_init, DT_DRV_INST(n), &bma_emul_cfg_##n, \ &bma_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL) -#define BMA255_EMUL_CASE(n) \ - case DT_INST_DEP_ORD(n): return &bma_emul_data_##n.common.emul; +#define BMA255_EMUL_CASE(n) \ + case DT_INST_DEP_ORD(n): \ + return &bma_emul_data_##n.common.emul; /** Check description in emul_bma255.h */ struct i2c_emul *bma_emul_get(int ord) { switch (ord) { - DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL_CASE) + DT_INST_FOREACH_STATUS_OKAY(BMA255_EMUL_CASE) default: return NULL; -- cgit v1.2.1 From f18a7b28b7ad94d42e3e28d332a5a0931cb435ac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:04:34 -0600 Subject: driver/temp_sensor/tmp411.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I736a0e9c06b02819bc810f02fc90a8d82eb5bb84 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729882 Reviewed-by: Jeremy Bettis --- driver/temp_sensor/tmp411.h | 132 ++++++++++++++++++++++---------------------- 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/driver/temp_sensor/tmp411.h b/driver/temp_sensor/tmp411.h index ef1b23278c..5295e275c2 100644 --- a/driver/temp_sensor/tmp411.h +++ b/driver/temp_sensor/tmp411.h @@ -8,83 +8,83 @@ #ifndef __CROS_EC_TMP411_H #define __CROS_EC_TMP411_H -#define TMP411_I2C_ADDR_FLAGS 0x4C +#define TMP411_I2C_ADDR_FLAGS 0x4C -#define TMP411_IDX_LOCAL 0 -#define TMP411_IDX_REMOTE1 1 -#define TMP411_IDX_REMOTE2 2 +#define TMP411_IDX_LOCAL 0 +#define TMP411_IDX_REMOTE1 1 +#define TMP411_IDX_REMOTE2 2 /* Chip-specific registers */ -#define TMP411_LOCAL 0x00 -#define TMP411_REMOTE1 0x01 -#define TMP411_STATUS_R 0x02 -#define TMP411_CONFIGURATION1_R 0x03 -#define TMP411_CONVERSION_RATE_R 0x04 -#define TMP411_LOCAL_HIGH_LIMIT_R 0x05 -#define TMP411_LOCAL_LOW_LIMIT_R 0x06 -#define TMP411_REMOTE1_HIGH_LIMIT_R 0x07 -#define TMP411_REMOTE1_LOW_LIMIT_R 0x08 -#define TMP411_CONFIGURATION1_W 0x09 -#define TMP411_CONVERSION_RATE_W 0x0a -#define TMP411_LOCAL_HIGH_LIMIT_W 0x0b -#define TMP411_LOCAL_LOW_LIMIT_W 0x0c -#define TMP411_REMOTE1_HIGH_LIMIT_W 0x0d -#define TMP411_REMOTE1_LOW_LIMIT_W 0x0e -#define TMP411_ONESHOT 0x0f -#define TMP411_REMOTE1_EXTD 0x10 -#define TMP411_REMOTE1_HIGH_LIMIT_EXTD 0x13 -#define TMP411_REMOTE1_LOW_LIMIT_EXTD 0x14 -#define TMP411_REMOTE2_HIGH_LIMIT_R 0x15 -#define TMP411_REMOTE2_HIGH_LIMIT_W 0x15 -#define TMP411_REMOTE2_LOW_LIMIT_R 0x16 -#define TMP411_REMOTE2_LOW_LIMIT_W 0x16 -#define TMP411_REMOTE2_HIGH_LIMIT_EXTD 0x17 -#define TMP411_REMOTE2_LOW_LIMIT_EXTD 0x18 -#define TMP411_REMOTE1_THERM_LIMIT 0x19 -#define TMP411_REMOTE2_THERM_LIMIT 0x1a -#define TMP411_STATUS_FAULT 0x1b -#define TMP411_CHANNEL_MASK 0x1f -#define TMP411_LOCAL_THERM_LIMIT 0x20 -#define TMP411_THERM_HYSTERESIS 0x21 -#define TMP411_CONSECUTIVE_ALERT 0x22 -#define TMP411_REMOTE2 0x23 -#define TMP411_REMOTE2_EXTD 0x24 -#define TMP411_BETA_RANGE_CH1 0x25 -#define TMP411_BETA_RANGE_CH2 0x26 -#define TMP411_NFACTOR_REMOTE1 0x27 -#define TMP411_NFACTOR_REMOTE2 0x28 -#define TMP411_LOCAL_EXTD 0x29 -#define TMP411_STATUS_LIMIT_HIGH 0x35 -#define TMP411_STATUS_LIMIT_LOW 0x36 -#define TMP411_STATUS_THERM 0x37 -#define TMP411_RESET_W 0xfc -#define TMP411_MANUFACTURER_ID 0xfe -#define TMP411_DEVICE_ID 0xff +#define TMP411_LOCAL 0x00 +#define TMP411_REMOTE1 0x01 +#define TMP411_STATUS_R 0x02 +#define TMP411_CONFIGURATION1_R 0x03 +#define TMP411_CONVERSION_RATE_R 0x04 +#define TMP411_LOCAL_HIGH_LIMIT_R 0x05 +#define TMP411_LOCAL_LOW_LIMIT_R 0x06 +#define TMP411_REMOTE1_HIGH_LIMIT_R 0x07 +#define TMP411_REMOTE1_LOW_LIMIT_R 0x08 +#define TMP411_CONFIGURATION1_W 0x09 +#define TMP411_CONVERSION_RATE_W 0x0a +#define TMP411_LOCAL_HIGH_LIMIT_W 0x0b +#define TMP411_LOCAL_LOW_LIMIT_W 0x0c +#define TMP411_REMOTE1_HIGH_LIMIT_W 0x0d +#define TMP411_REMOTE1_LOW_LIMIT_W 0x0e +#define TMP411_ONESHOT 0x0f +#define TMP411_REMOTE1_EXTD 0x10 +#define TMP411_REMOTE1_HIGH_LIMIT_EXTD 0x13 +#define TMP411_REMOTE1_LOW_LIMIT_EXTD 0x14 +#define TMP411_REMOTE2_HIGH_LIMIT_R 0x15 +#define TMP411_REMOTE2_HIGH_LIMIT_W 0x15 +#define TMP411_REMOTE2_LOW_LIMIT_R 0x16 +#define TMP411_REMOTE2_LOW_LIMIT_W 0x16 +#define TMP411_REMOTE2_HIGH_LIMIT_EXTD 0x17 +#define TMP411_REMOTE2_LOW_LIMIT_EXTD 0x18 +#define TMP411_REMOTE1_THERM_LIMIT 0x19 +#define TMP411_REMOTE2_THERM_LIMIT 0x1a +#define TMP411_STATUS_FAULT 0x1b +#define TMP411_CHANNEL_MASK 0x1f +#define TMP411_LOCAL_THERM_LIMIT 0x20 +#define TMP411_THERM_HYSTERESIS 0x21 +#define TMP411_CONSECUTIVE_ALERT 0x22 +#define TMP411_REMOTE2 0x23 +#define TMP411_REMOTE2_EXTD 0x24 +#define TMP411_BETA_RANGE_CH1 0x25 +#define TMP411_BETA_RANGE_CH2 0x26 +#define TMP411_NFACTOR_REMOTE1 0x27 +#define TMP411_NFACTOR_REMOTE2 0x28 +#define TMP411_LOCAL_EXTD 0x29 +#define TMP411_STATUS_LIMIT_HIGH 0x35 +#define TMP411_STATUS_LIMIT_LOW 0x36 +#define TMP411_STATUS_THERM 0x37 +#define TMP411_RESET_W 0xfc +#define TMP411_MANUFACTURER_ID 0xfe +#define TMP411_DEVICE_ID 0xff -#define TMP411A_DEVICE_ID_VAL 0x12 -#define TMP411B_DEVICE_ID_VAL 0x13 -#define TMP411C_DEVICE_ID_VAL 0x10 -#define TMP411d_DEVICE_ID_VAL 0x12 +#define TMP411A_DEVICE_ID_VAL 0x12 +#define TMP411B_DEVICE_ID_VAL 0x13 +#define TMP411C_DEVICE_ID_VAL 0x10 +#define TMP411d_DEVICE_ID_VAL 0x12 /* Config register bits */ -#define TMP411_CONFIG1_TEMP_RANGE BIT(2) +#define TMP411_CONFIG1_TEMP_RANGE BIT(2) /* TMP411_CONFIG1_MODE bit is use to enable THERM mode */ -#define TMP411_CONFIG1_MODE BIT(5) -#define TMP411_CONFIG1_RUN_L BIT(6) -#define TMP411_CONFIG1_ALERT_MASK_L BIT(7) +#define TMP411_CONFIG1_MODE BIT(5) +#define TMP411_CONFIG1_RUN_L BIT(6) +#define TMP411_CONFIG1_ALERT_MASK_L BIT(7) /* Status register bits */ -#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1) -#define TMP411_STATUS_OPEN BIT(2) -#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3) -#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4) -#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) -#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) -#define TMP411_STATUS_BUSY BIT(7) +#define TMP411_STATUS_TEMP_THERM_ALARM BIT(1) +#define TMP411_STATUS_OPEN BIT(2) +#define TMP411_STATUS_TEMP_LOW_ALARM BIT(3) +#define TMP411_STATUS_TEMP_HIGH_ALARM BIT(4) +#define TMP411_STATUS_LOCAL_TEMP_LOW_ALARM BIT(5) +#define TMP411_STATUS_LOCAL_TEMP_HIGH_ALARM BIT(6) +#define TMP411_STATUS_BUSY BIT(7) /* Limits */ -#define TMP411_HYSTERESIS_HIGH_LIMIT 255 -#define TMP411_HYSTERESIS_LOW_LIMIT 0 +#define TMP411_HYSTERESIS_HIGH_LIMIT 255 +#define TMP411_HYSTERESIS_LOW_LIMIT 0 enum tmp411_power_state { TMP411_POWER_OFF = 0, -- cgit v1.2.1 From 268a378fa2802844034ae6c1d0289e73d55157d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:32 -0600 Subject: include/usb_pd_policy.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I73601c617eb74bbf177f7c175e404015167f46f6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730441 Reviewed-by: Jeremy Bettis --- include/usb_pd_policy.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/usb_pd_policy.h b/include/usb_pd_policy.h index 04a7a68e7d..bd8af9d5f0 100644 --- a/include/usb_pd_policy.h +++ b/include/usb_pd_policy.h @@ -21,8 +21,9 @@ * @param dr_swap_flag Data Role Swap Flag bit * @param return True if state machine should perform a DR swap, elsf False */ -__override_proto bool port_discovery_dr_swap_policy(int port, - enum pd_data_role dr, bool dr_swap_flag); +__override_proto bool port_discovery_dr_swap_policy(int port, + enum pd_data_role dr, + bool dr_swap_flag); /** * Port Discovery VCONN Swap Policy @@ -35,6 +36,6 @@ __override_proto bool port_discovery_dr_swap_policy(int port, * @param return True if state machine should perform a VCONN swap, elsf False */ __override_proto bool port_discovery_vconn_swap_policy(int port, - bool vconn_swap_flag); + bool vconn_swap_flag); #endif /* __CROS_EC_USB_PD_POLICY_H */ -- cgit v1.2.1 From 43f6eddfa38598921622465e4c34d93f0461ef8d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:36:48 -0600 Subject: common/keyboard_8042.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I328779d2e401f23cdc4cd88bfdf5aeb71d854343 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729658 Reviewed-by: Jeremy Bettis --- common/keyboard_8042.c | 127 +++++++++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 68 deletions(-) diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c index 755b26f360..aebbf38e87 100644 --- a/common/keyboard_8042.c +++ b/common/keyboard_8042.c @@ -28,11 +28,11 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_KEYBOARD, outstr) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) #ifdef CONFIG_KEYBOARD_DEBUG #define CPUTS5(outstr) cputs(CC_KEYBOARD, outstr) -#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTS5(format, args...) cprints(CC_KEYBOARD, format, ##args) #else #define CPUTS5(outstr) #define CPRINTS5(format, args...) @@ -44,16 +44,16 @@ * #define CMD_KEYBOARD_LOG IS_ENABLED(CONFIG_MALLOC) */ #ifdef CONFIG_MALLOC -#define CMD_KEYBOARD_LOG 1 +#define CMD_KEYBOARD_LOG 1 #else -#define CMD_KEYBOARD_LOG 0 +#define CMD_KEYBOARD_LOG 0 #endif static enum { STATE_NORMAL = 0, STATE_SCANCODE, STATE_SETLEDS, - STATE_EX_SETLEDS_1, /* Expect 2-byte parameter */ + STATE_EX_SETLEDS_1, /* Expect 2-byte parameter */ STATE_EX_SETLEDS_2, STATE_WRITE_CMD_BYTE, STATE_WRITE_OUTPUT_PORT, @@ -123,9 +123,9 @@ static int i8042_keyboard_irq_enabled; static int i8042_aux_irq_enabled; /* i8042 global settings */ -static int keyboard_enabled; /* default the keyboard is disabled. */ -static int aux_chan_enabled; /* default the mouse is disabled. */ -static int keystroke_enabled; /* output keystrokes */ +static int keyboard_enabled; /* default the keyboard is disabled. */ +static int aux_chan_enabled; /* default the mouse is disabled. */ +static int keystroke_enabled; /* output keystrokes */ static uint8_t resend_command[MAX_SCAN_CODE_LEN]; static uint8_t resend_command_len; static uint8_t controller_ram_address; @@ -157,11 +157,11 @@ static enum scancode_set_list scancode_set = SCANCODE_SET_2; static uint8_t typematic_value_from_host; static int typematic_first_delay; static int typematic_inter_delay; -static int typematic_len; /* length of typematic_scan_code */ +static int typematic_len; /* length of typematic_scan_code */ static uint8_t typematic_scan_code[MAX_SCAN_CODE_LEN]; static timestamp_t typematic_deadline; -#define KB_SYSJUMP_TAG 0x4b42 /* "KB" */ +#define KB_SYSJUMP_TAG 0x4b42 /* "KB" */ #define KB_HOOK_VERSION 2 /* the previous keyboard state before reboot_ec. */ struct kb_state { @@ -174,7 +174,7 @@ struct kb_state { /* Keyboard event log */ /* Log the traffic between EC and host -- for debug only */ -#define MAX_KBLOG 512 /* Max events in keyboard log */ +#define MAX_KBLOG 512 /* Max events in keyboard log */ struct kblog_t { /* @@ -202,8 +202,8 @@ struct kblog_t { uint8_t byte; }; -static struct kblog_t *kblog_buf; /* Log buffer; NULL if not logging */ -static int kblog_len; /* Current log length */ +static struct kblog_t *kblog_buf; /* Log buffer; NULL if not logging */ +static int kblog_len; /* Current log length */ /** * Add event to keyboard log. @@ -266,8 +266,7 @@ static void aux_enable_irq(int enable) * @param to_host Data to send * @param chan Channel to send data on */ -static void i8042_send_to_host(int len, const uint8_t *bytes, - uint8_t chan) +static void i8042_send_to_host(int len, const uint8_t *bytes, uint8_t chan) { int i; struct data_byte data; @@ -364,8 +363,8 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col, #ifdef CONFIG_KEYBOARD_SCANCODE_CALLBACK { - enum ec_error_list r = keyboard_scancode_callback( - &make_code, pressed); + enum ec_error_list r = + keyboard_scancode_callback(&make_code, pressed); if (r != EC_SUCCESS) return r; } @@ -392,10 +391,10 @@ static enum ec_error_list matrix_callback(int8_t row, int8_t col, static void set_typematic_delays(uint8_t data) { typematic_value_from_host = data; - typematic_first_delay = MSEC * - (((typematic_value_from_host & 0x60) >> 5) + 1) * 250; - typematic_inter_delay = SECOND * - (1 << ((typematic_value_from_host & 0x18) >> 3)) * + typematic_first_delay = + MSEC * (((typematic_value_from_host & 0x60) >> 5) + 1) * 250; + typematic_inter_delay = + SECOND * (1 << ((typematic_value_from_host & 0x18) >> 3)) * ((typematic_value_from_host & 0x7) + 8) / 240; } @@ -442,7 +441,8 @@ void keyboard_state_changed(int row, int col, int is_pressed) if (mylabel & KEYCAP_LONG_LABEL_BIT) CPRINTS("KB (%d,%d)=%d %s", row, col, is_pressed, - get_keycap_long_label(mylabel & KEYCAP_LONG_LABEL_INDEX_BITMASK)); + get_keycap_long_label(mylabel & + KEYCAP_LONG_LABEL_INDEX_BITMASK)); else CPRINTS("KB (%d,%d)=%d %c", row, col, is_pressed, mylabel); #endif @@ -516,8 +516,8 @@ static void update_ctl_ram(uint8_t addr, uint8_t data) orig = controller_ram[addr]; controller_ram[addr] = data; - CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)", - addr, data, orig); + CPRINTS5("KB set CTR_RAM(0x%02x)=0x%02x (old:0x%02x)", addr, data, + orig); if (addr == 0x00) { /* Keyboard enable/disable */ @@ -567,7 +567,7 @@ static int handle_mouse_data(uint8_t data, uint8_t *output, int *count) data_port_state = STATE_NORMAL; break; - default: /* STATE_NORMAL */ + default: /* STATE_NORMAL */ return 0; } @@ -622,15 +622,13 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output) break; case STATE_WRITE_CMD_BYTE: - CPRINTS5("KB eaten by STATE_WRITE_CMD_BYTE: 0x%02x", - data); + CPRINTS5("KB eaten by STATE_WRITE_CMD_BYTE: 0x%02x", data); update_ctl_ram(controller_ram_address, data); data_port_state = STATE_NORMAL; break; case STATE_WRITE_OUTPUT_PORT: - CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x", - data); + CPRINTS5("KB eaten by STATE_WRITE_OUTPUT_PORT: 0x%02x", data); A20_status = (data & BIT(1)) ? 1 : 0; data_port_state = STATE_NORMAL; break; @@ -643,9 +641,9 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output) data_port_state = STATE_NORMAL; break; - default: /* STATE_NORMAL */ + default: /* STATE_NORMAL */ switch (data) { - case I8042_CMD_GSCANSET: /* also I8042_CMD_SSCANSET */ + case I8042_CMD_GSCANSET: /* also I8042_CMD_SSCANSET */ output[out_len++] = I8042_RET_ACK; data_port_state = STATE_SCANCODE; break; @@ -666,10 +664,10 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output) output[out_len++] = I8042_CMD_DIAG_ECHO; break; - case I8042_CMD_GETID: /* fall-thru */ + case I8042_CMD_GETID: /* fall-thru */ case I8042_CMD_OK_GETID: output[out_len++] = I8042_RET_ACK; - output[out_len++] = 0xab; /* Regular keyboards */ + output[out_len++] = 0xab; /* Regular keyboards */ output[out_len++] = 0x83; break; @@ -714,13 +712,12 @@ static int handle_keyboard_data(uint8_t data, uint8_t *output) /* U-boot hack. Just ignore; don't reply. */ break; - case I8042_CMD_SETALL_MB: /* fall-thru */ + case I8042_CMD_SETALL_MB: /* fall-thru */ case I8042_CMD_SETALL_MBR: case I8042_CMD_EX_ENABLE: default: output[out_len++] = I8042_RET_NAK; - CPRINTS("KB Unsupported i8042 data 0x%02x", - data); + CPRINTS("KB Unsupported i8042 data 0x%02x", data); break; } } @@ -770,7 +767,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) case I8042_DIS_KB: update_ctl_ram(0, read_ctl_ram(0) | I8042_KBD_DIS); reset_rate_and_delay(); - typematic_len = 0; /* stop typematic */ + typematic_len = 0; /* stop typematic */ keyboard_clear_buffer(); break; @@ -784,8 +781,8 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) output[out_len++] = (lpc_keyboard_input_pending() ? BIT(5) : 0) | (lpc_keyboard_has_char() ? BIT(4) : 0) | - (A20_status ? BIT(1) : 0) | - 1; /* Main processor in normal mode */ + (A20_status ? BIT(1) : 0) | 1; /* Main processor in + normal mode */ break; case I8042_WRITE_OUTPUT_PORT: @@ -793,7 +790,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) break; case I8042_RESET_SELF_TEST: - output[out_len++] = 0x55; /* Self test success */ + output[out_len++] = 0x55; /* Self test success */ break; case I8042_TEST_KB_PORT: @@ -809,7 +806,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output) break; case I8042_TEST_MOUSE: - output[out_len++] = 0; /* No error detected */ + output[out_len++] = 0; /* No error detected */ break; case I8042_ECHO_MOUSE: @@ -906,8 +903,8 @@ void keyboard_protocol_task(void *u) i8042_send_to_host(typematic_len, typematic_scan_code, CHAN_KBD); - typematic_deadline.val = t.val + - typematic_inter_delay; + typematic_deadline.val = + t.val + typematic_inter_delay; wait = typematic_inter_delay; } else { /* Wait for remaining interval */ @@ -970,7 +967,7 @@ static void send_aux_data_to_host_deferred(void) uint8_t data; if (IS_ENABLED(CONFIG_DEVICE_EVENT) && - chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) + chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) device_set_single_event(EC_DEVICE_EVENT_TRACKPAD); while (!queue_is_empty(&aux_to_host_queue)) { @@ -1069,8 +1066,8 @@ static int command_codeset(int argc, char **argv) if (argc == 2) { int set = strtoi(argv[1], NULL, 0); switch (set) { - case SCANCODE_SET_1: /* fall-thru */ - case SCANCODE_SET_2: /* fall-thru */ + case SCANCODE_SET_1: /* fall-thru */ + case SCANCODE_SET_2: /* fall-thru */ scancode_set = set; break; default: @@ -1109,8 +1106,8 @@ static int command_keyboard_log(int argc, char **argv) if (argc == 1) { ccprintf("KBC log (len=%d):\n", kblog_len); for (i = 0; kblog_buf && i < kblog_len; ++i) { - ccprintf("%c.%02x ", - kblog_buf[i].type, kblog_buf[i].byte); + ccprintf("%c.%02x ", kblog_buf[i].type, + kblog_buf[i].byte); if ((i & 15) == 15) { ccputs("\n"); cflush(); @@ -1126,9 +1123,9 @@ static int command_keyboard_log(int argc, char **argv) if (i) { if (!kblog_buf) { - int rv = SHARED_MEM_ACQUIRE_CHECK( - sizeof(*kblog_buf) * MAX_KBLOG, - (char **)&kblog_buf); + int rv = SHARED_MEM_ACQUIRE_CHECK(sizeof(*kblog_buf) * + MAX_KBLOG, + (char **)&kblog_buf); if (rv != EC_SUCCESS) kblog_buf = NULL; kblog_len = 0; @@ -1204,20 +1201,15 @@ static int command_8042_internal(int argc, char **argv) /* Zephyr only provides these as subcommands*/ #ifndef CONFIG_ZEPHYR -DECLARE_CONSOLE_COMMAND(typematic, command_typematic, - "[first] [inter]", +DECLARE_CONSOLE_COMMAND(typematic, command_typematic, "[first] [inter]", "Get/set typematic delays"); -DECLARE_CONSOLE_COMMAND(codeset, command_codeset, - "[set]", +DECLARE_CONSOLE_COMMAND(codeset, command_codeset, "[set]", "Get/set keyboard codeset"); -DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram, - "index [value]", +DECLARE_CONSOLE_COMMAND(ctrlram, command_controller_ram, "index [value]", "Get/set keyboard controller RAM"); -DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log, - "[on | off]", +DECLARE_CONSOLE_COMMAND(kblog, command_keyboard_log, "[on | off]", "Print or toggle keyboard event log"); -DECLARE_CONSOLE_COMMAND(kbd, command_keyboard, - "[on | off]", +DECLARE_CONSOLE_COMMAND(kbd, command_keyboard, "[on | off]", "Print or toggle keyboard info"); #endif @@ -1239,16 +1231,16 @@ static int command_8042(int argc, char **argv) else return EC_ERROR_PARAM1; } else { - char *ctlram_argv[] = {"ctrlram", "0"}; + char *ctlram_argv[] = { "ctrlram", "0" }; ccprintf("\n- Typematic:\n"); command_typematic(argc, argv); ccprintf("\n- Codeset:\n"); command_codeset(argc, argv); ccprintf("\n- Control RAM:\n"); - command_controller_ram( - sizeof(ctlram_argv) / sizeof(ctlram_argv[0]), - ctlram_argv); + command_controller_ram(sizeof(ctlram_argv) / + sizeof(ctlram_argv[0]), + ctlram_argv); if (CMD_KEYBOARD_LOG) { ccprintf("\n- Keyboard log:\n"); command_keyboard_log(argc, argv); @@ -1268,7 +1260,6 @@ DECLARE_CONSOLE_COMMAND(8042, command_8042, "Print 8042 state in one place"); #endif - /*****************************************************************************/ /* Hooks */ @@ -1290,8 +1281,8 @@ static void keyboard_preserve_state(void) state.ctlram = controller_ram[0]; state.keystroke_enabled = keystroke_enabled; - system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION, - sizeof(state), &state); + system_add_jump_tag(KB_SYSJUMP_TAG, KB_HOOK_VERSION, sizeof(state), + &state); } DECLARE_HOOK(HOOK_SYSJUMP, keyboard_preserve_state, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 0b874e640157eb30fd88674b048e8f8fbb51f136 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:56 -0600 Subject: board/brask/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I18ff02163b3f184dc6cfe710fd534cf2683706da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728091 Reviewed-by: Jeremy Bettis --- board/brask/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/brask/fans.c b/board/brask/fans.c index f2a70636d0..62492fe063 100644 --- a/board/brask/fans.c +++ b/board/brask/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 9859cec3c65ac54966fc49b4f9bfddc1ffb09dc7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:06:24 -0600 Subject: board/stm32l476g-eval/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife6eae3ccf1361bcf00aaca3fb1a1afd44f67d37 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728970 Reviewed-by: Jeremy Bettis --- board/stm32l476g-eval/board.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/board/stm32l476g-eval/board.c b/board/stm32l476g-eval/board.c index 70375abe95..dd57087581 100644 --- a/board/stm32l476g-eval/board.c +++ b/board/stm32l476g-eval/board.c @@ -32,14 +32,12 @@ void tick_event(void) DECLARE_HOOK(HOOK_TICK, tick_event, HOOK_PRIO_DEFAULT); #ifdef CTS_MODULE_I2C -const struct i2c_port_t i2c_ports[] = { - { - .name = "test", - .port = STM32_I2C2_PORT, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "test", + .port = STM32_I2C2_PORT, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); #endif -- cgit v1.2.1 From a02a54978e40f4c58c2951712b3cd23df537c763 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:00 -0600 Subject: board/taniks/i2c.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1b59aff957cfa0c59ac3473669aebcf62a8ec091 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729012 Reviewed-by: Jeremy Bettis --- board/taniks/i2c.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/taniks/i2c.c b/board/taniks/i2c.c index 769385c46f..64c5e8f127 100644 --- a/board/taniks/i2c.c +++ b/board/taniks/i2c.c @@ -44,7 +44,8 @@ const struct i2c_port_t i2c_ports[] = { }, { /* I2C4 C1 TCPC */ - /* TODO(b/211080526): Change TCPC1's (PS8815) I2C frequency from 400Khz to 1000Khz */ + /* TODO(b/211080526): Change TCPC1's (PS8815) I2C frequency from + 400Khz to 1000Khz */ .name = "tcpc1", .port = I2C_PORT_USB_C1_TCPC, .kbps = 1000, -- cgit v1.2.1 From 2963615d72817e9949ca004f4ce847f0392597cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:36 -0600 Subject: driver/tcpm/tcpci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5e52e0cb0661e731727c76af2028b20ae3f00890 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730109 Reviewed-by: Jeremy Bettis --- driver/tcpm/tcpci.c | 301 ++++++++++++++++++++++++---------------------------- 1 file changed, 137 insertions(+), 164 deletions(-) diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c index a55db12e1c..51451041ee 100644 --- a/driver/tcpm/tcpci.c +++ b/driver/tcpm/tcpci.c @@ -26,17 +26,17 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) STATIC_IF(CONFIG_USB_PD_DECODE_SOP) - bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; +bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; STATIC_IF(CONFIG_USB_PD_DECODE_SOP) - int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; +int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -#define TCPC_FLAGS_VSAFE0V(_flags) \ +#define TCPC_FLAGS_VSAFE0V(_flags) \ ((_flags & TCPC_FLAGS_TCPCI_REV2_0) && \ - !(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)) + !(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)) /**************************************************************************** * TCPCI DEBUG Helpers @@ -57,7 +57,7 @@ struct i2c_wrt_op { int mask; }; STATIC_IF(DEBUG_I2C_FAULT_LAST_WRITE_OP) - struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT]; +struct i2c_wrt_op last_write_op[CONFIG_USB_PD_PORT_MAX_COUNT]; /* * AutoDischargeDisconnect has caused a number of issues with the @@ -90,7 +90,7 @@ struct get_cc_values { int role; }; STATIC_IF(DEBUG_GET_CC) - struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT]; +struct get_cc_values last_get_cc[CONFIG_USB_PD_PORT_MAX_COUNT]; /* * Seeing RoleCtrl updates can help determine why GetCC is not @@ -130,13 +130,12 @@ int tcpc_addr_write(int port, int i2c_addr, int reg, int val) if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) { last_write_op[port].addr = i2c_addr; - last_write_op[port].reg = reg; - last_write_op[port].val = val & 0xFF; + last_write_op[port].reg = reg; + last_write_op[port].val = val & 0xFF; last_write_op[port].mask = 0; } - rv = i2c_write8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + rv = i2c_write8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); pd_device_accessed(port); return rv; @@ -150,13 +149,12 @@ int tcpc_addr_write16(int port, int i2c_addr, int reg, int val) if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) { last_write_op[port].addr = i2c_addr; - last_write_op[port].reg = reg; - last_write_op[port].val = val & 0xFFFF; + last_write_op[port].reg = reg; + last_write_op[port].val = val & 0xFFFF; last_write_op[port].mask = 0; } - rv = i2c_write16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + rv = i2c_write16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); pd_device_accessed(port); return rv; @@ -168,8 +166,7 @@ int tcpc_addr_read(int port, int i2c_addr, int reg, int *val) pd_wait_exit_low_power(port); - rv = i2c_read8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + rv = i2c_read8(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); pd_device_accessed(port); return rv; @@ -186,8 +183,7 @@ int tcpc_addr_read16_no_lpm_exit(int port, int i2c_addr, int reg, int *val) { int rv; - rv = i2c_read16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, val); + rv = i2c_read16(tcpc_config[port].i2c_info.port, i2c_addr, reg, val); pd_device_accessed(port); return rv; @@ -200,8 +196,8 @@ int tcpc_read_block(int port, int reg, uint8_t *in, int size) pd_wait_exit_low_power(port); rv = i2c_read_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, in, size); + tcpc_config[port].i2c_info.addr_flags, reg, in, + size); pd_device_accessed(port); return rv; @@ -214,15 +210,15 @@ int tcpc_write_block(int port, int reg, const uint8_t *out, int size) pd_wait_exit_low_power(port); rv = i2c_write_block(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, out, size); + tcpc_config[port].i2c_info.addr_flags, reg, out, + size); pd_device_accessed(port); return rv; } -int tcpc_xfer(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size) +int tcpc_xfer(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size) { int rv; /* Dispatching to tcpc_xfer_unlocked reduces code size growth. */ @@ -233,23 +229,22 @@ int tcpc_xfer(int port, const uint8_t *out, int out_size, return rv; } -int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, - uint8_t *in, int in_size, int flags) +int tcpc_xfer_unlocked(int port, const uint8_t *out, int out_size, uint8_t *in, + int in_size, int flags) { int rv; pd_wait_exit_low_power(port); rv = i2c_xfer_unlocked(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - out, out_size, in, in_size, flags); + tcpc_config[port].i2c_info.addr_flags, out, + out_size, in, in_size, flags); pd_device_accessed(port); return rv; } -int tcpc_update8(int port, int reg, - uint8_t mask, +int tcpc_update8(int port, int reg, uint8_t mask, enum mask_update_action action) { int rv; @@ -259,20 +254,19 @@ int tcpc_update8(int port, int reg, if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) { last_write_op[port].addr = i2c_addr; - last_write_op[port].reg = reg; - last_write_op[port].val = 0; + last_write_op[port].reg = reg; + last_write_op[port].val = 0; last_write_op[port].mask = (mask & 0xFF) | (action << 16); } - rv = i2c_update8(tcpc_config[port].i2c_info.port, - i2c_addr, reg, mask, action); + rv = i2c_update8(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask, + action); pd_device_accessed(port); return rv; } -int tcpc_update16(int port, int reg, - uint16_t mask, +int tcpc_update16(int port, int reg, uint16_t mask, enum mask_update_action action) { int rv; @@ -282,13 +276,13 @@ int tcpc_update16(int port, int reg, if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP)) { last_write_op[port].addr = i2c_addr; - last_write_op[port].reg = reg; - last_write_op[port].val = 0; + last_write_op[port].reg = reg; + last_write_op[port].val = 0; last_write_op[port].mask = (mask & 0xFFFF) | (action << 16); } - rv = i2c_update16(tcpc_config[port].i2c_info.port, - i2c_addr, reg, mask, action); + rv = i2c_update16(tcpc_config[port].i2c_info.port, i2c_addr, reg, mask, + action); pd_device_accessed(port); return rv; @@ -324,17 +318,14 @@ static int init_alert_mask(int port) */ if (get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) { mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED | - TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | - TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS | - TCPC_REG_ALERT_FAULT - | TCPC_REG_ALERT_POWER_STATUS - ; + TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | + TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS | + TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS; } else { mask = TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED | - TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | - TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS | - TCPC_REG_ALERT_FAULT - ; + TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_RX_STATUS | + TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS | + TCPC_REG_ALERT_FAULT; } /* TCPCI Rev2 includes SAFE0V alerts */ @@ -373,7 +364,7 @@ static int init_power_status_mask(int port) else mask = 0; - rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK , mask); + rv = tcpc_write(port, TCPC_REG_POWER_STATUS_MASK, mask); return rv; } @@ -399,11 +390,10 @@ int tcpci_tcpm_select_rp_value(int port, int rp) void tcpci_tcpc_discharge_vbus(int port, int enable) { if (IS_ENABLED(DEBUG_FORCED_DISCHARGE)) - CPRINTS("C%d: ForceDischarge %sABLED", - port, enable ? "EN" : "DIS"); + CPRINTS("C%d: ForceDischarge %sABLED", port, + enable ? "EN" : "DIS"); - tcpc_update8(port, - TCPC_REG_POWER_CTRL, + tcpc_update8(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_FORCE_DISCHARGE, (enable) ? MASK_SET : MASK_CLR); } @@ -416,11 +406,10 @@ void tcpci_tcpc_discharge_vbus(int port, int enable) void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable) { if (IS_ENABLED(DEBUG_AUTO_DISCHARGE_DISCONNECT)) - CPRINTS("C%d: AutoDischargeDisconnect %sABLED", - port, enable ? "EN" : "DIS"); + CPRINTS("C%d: AutoDischargeDisconnect %sABLED", port, + enable ? "EN" : "DIS"); - tcpc_update8(port, - TCPC_REG_POWER_CTRL, + tcpc_update8(port, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT, (enable) ? MASK_SET : MASK_CLR); } @@ -433,7 +422,7 @@ int tcpci_tcpc_debug_accessory(int port, bool enable) } int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, - enum tcpc_cc_voltage_status *cc2) + enum tcpc_cc_voltage_status *cc2) { int role; int status; @@ -493,13 +482,11 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, *cc2 |= cc2_present_rd << 2; if (IS_ENABLED(DEBUG_GET_CC) && - (last_get_cc[port].cc1 != *cc1 || - last_get_cc[port].cc2 != *cc2 || + (last_get_cc[port].cc1 != *cc1 || last_get_cc[port].cc2 != *cc2 || last_get_cc[port].cc_sts != status || last_get_cc[port].role != role)) { - - CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X", - port, *cc1, *cc2, status, role); + CPRINTS("C%d: GET_CC cc1=%d cc2=%d cc_sts=0x%X role=0x%X", port, + *cc1, *cc2, status, role); last_get_cc[port].cc1 = *cc1; last_get_cc[port].cc2 = *cc2; @@ -511,9 +498,8 @@ int tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, int tcpci_tcpm_set_cc(int port, int pull) { - int role = TCPC_REG_ROLE_CTRL_SET(TYPEC_NO_DRP, - tcpci_get_cached_rp(port), - pull, pull); + int role = TCPC_REG_ROLE_CTRL_SET( + TYPEC_NO_DRP, tcpci_get_cached_rp(port), pull, pull); if (IS_ENABLED(DEBUG_ROLE_CTRL_UPDATES)) CPRINTS("C%d: SET_CC pull=%d role=0x%X", port, pull, role); @@ -523,7 +509,7 @@ int tcpci_tcpm_set_cc(int port, int pull) #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE int tcpci_set_role_ctrl(int port, enum tcpc_drp drp, enum tcpc_rp_value rp, - enum tcpc_cc_pull pull) + enum tcpc_cc_pull pull) { int role = TCPC_REG_ROLE_CTRL_SET(drp, rp, pull, pull); @@ -552,16 +538,16 @@ int tcpci_tcpc_drp_toggle(int port) * * Set the Rp Value to be the minimal to save power */ - pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) - ? TYPEC_CC_RP : TYPEC_CC_RD; + pull = (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) ? + TYPEC_CC_RP : + TYPEC_CC_RD; rv = tcpci_set_role_ctrl(port, TYPEC_DRP, TYPEC_RP_USB, pull); if (rv) return rv; /* Set up to catch LOOK4CONNECTION alerts */ - rv = tcpc_update8(port, - TCPC_REG_TCPC_CTRL, + rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT, MASK_SET); if (rv) @@ -590,18 +576,15 @@ void tcpci_wake_low_power_mode(int port) * correctly support it */ i2c_write8(tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - TCPC_REG_COMMAND, TCPC_REG_COMMAND_WAKE_I2C); + tcpc_config[port].i2c_info.addr_flags, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_WAKE_I2C); } #endif int tcpci_tcpm_set_polarity(int port, enum tcpc_cc_polarity polarity) { - return tcpc_update8(port, - TCPC_REG_TCPC_CTRL, - TCPC_REG_TCPC_CTRL_SET(1), - polarity_rm_dts(polarity) - ? MASK_SET : MASK_CLR); + return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1), + polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR); } bool tcpci_tcpm_get_snk_ctrl(int port) @@ -611,14 +594,13 @@ bool tcpci_tcpm_get_snk_ctrl(int port) rv = tcpci_tcpm_get_power_status(port, &pwr_sts); - return rv == EC_SUCCESS && - pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS; + return rv == EC_SUCCESS && pwr_sts & TCPC_REG_POWER_STATUS_SINKING_VBUS; } int tcpci_tcpm_set_snk_ctrl(int port, int enable) { int cmd = enable ? TCPC_REG_COMMAND_SNK_CTRL_HIGH : - TCPC_REG_COMMAND_SNK_CTRL_LOW; + TCPC_REG_COMMAND_SNK_CTRL_LOW; return tcpc_write(port, TCPC_REG_COMMAND, cmd); } @@ -631,13 +613,13 @@ bool tcpci_tcpm_get_src_ctrl(int port) rv = tcpci_tcpm_get_power_status(port, &pwr_sts); return rv == EC_SUCCESS && - pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS; + pwr_sts & TCPC_REG_POWER_STATUS_SOURCING_VBUS; } int tcpci_tcpm_set_src_ctrl(int port, int enable) { int cmd = enable ? TCPC_REG_COMMAND_SRC_CTRL_HIGH : - TCPC_REG_COMMAND_SRC_CTRL_LOW; + TCPC_REG_COMMAND_SRC_CTRL_LOW; return tcpc_write(port, TCPC_REG_COMMAND, cmd); } @@ -708,12 +690,11 @@ int tcpci_tcpm_set_rx_enable(int port, int enable) rx_en[port] = enable; } - if (enable) { detect_sop_en = TCPC_REG_RX_DETECT_SOP_HRST_MASK; if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) && - sop_prime_en[port]) { + sop_prime_en[port]) { /* * Only the VCONN Source is allowed to communicate * with the Cable Plugs. @@ -730,10 +711,9 @@ int tcpci_tcpm_set_rx_enable(int port, int enable) #ifdef CONFIG_USB_PD_FRS int tcpci_tcpc_fast_role_swap_enable(int port, int enable) { - return tcpc_update8(port, - TCPC_REG_POWER_CTRL, - TCPC_REG_POWER_CTRL_FRS_ENABLE, - (enable) ? MASK_SET : MASK_CLR); + return tcpc_update8(port, TCPC_REG_POWER_CTRL, + TCPC_REG_POWER_CTRL_FRS_ENABLE, + (enable) ? MASK_SET : MASK_CLR); } #endif @@ -788,7 +768,7 @@ static int tcpci_rev2_0_tcpm_get_message_raw(int port, uint32_t *payload, /* The next two bytes are the header */ rv |= tcpc_xfer_unlocked(port, NULL, 0, (uint8_t *)head, 2, - cnt ? 0 : I2C_XFER_STOP); + cnt ? 0 : I2C_XFER_STOP); /* Encode message address in bits 31 to 28 */ *head &= 0x0000ffff; @@ -953,11 +933,11 @@ void tcpm_clear_pending_messages(int port) q->tail = q->head; } -int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, - uint16_t header, const uint32_t *data) +int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, uint16_t header, + const uint32_t *data) { int reg = TCPC_REG_TX_DATA; - int rv, cnt = 4*PD_HEADER_CNT(header); + int rv, cnt = 4 * PD_HEADER_CNT(header); /* If not SOP* transmission, just write to the transmit register */ if (type >= NUM_SOP_STAR_TYPES) { @@ -966,7 +946,7 @@ int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, * should ignore retry field for these 3 types). */ return tcpc_write(port, TCPC_REG_TRANSMIT, - TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type)); + TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type)); } if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) { @@ -983,13 +963,14 @@ int tcpci_tcpm_transmit(int port, enum tcpci_msg_type type, rv |= tcpc_xfer_unlocked(port, (uint8_t *)&cnt, 1, NULL, 0, 0); if (cnt > sizeof(header)) { rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header, - sizeof(header), NULL, 0, 0); + sizeof(header), NULL, 0, 0); rv |= tcpc_xfer_unlocked(port, (uint8_t *)data, - cnt-sizeof(header), NULL, 0, - I2C_XFER_STOP); + cnt - sizeof(header), NULL, 0, + I2C_XFER_STOP); } else { rv |= tcpc_xfer_unlocked(port, (uint8_t *)&header, - sizeof(header), NULL, 0, I2C_XFER_STOP); + sizeof(header), NULL, 0, + I2C_XFER_STOP); } tcpc_lock(port, 0); @@ -1075,15 +1056,13 @@ static int tcpci_handle_fault(int port, int fault) if (IS_ENABLED(DEBUG_I2C_FAULT_LAST_WRITE_OP) && fault & TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR) { if (last_write_op[port].mask == 0) - CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X", - port, + CPRINTS("C%d I2C WR 0x%02X 0x%02X value=0x%X", port, last_write_op[port].addr, last_write_op[port].reg, last_write_op[port].val); else CPRINTS("C%d I2C UP 0x%02X 0x%02X op=%d mask=0x%X", - port, - last_write_op[port].addr, + port, last_write_op[port].addr, last_write_op[port].reg, last_write_op[port].mask >> 16, last_write_op[port].mask & 0xFFFF); @@ -1091,8 +1070,8 @@ static int tcpci_handle_fault(int port, int fault) /* Report overcurrent to the OCP module if enabled */ if ((dev_cap_1[port] & TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING) && - IS_ENABLED(CONFIG_USBC_OCP) && - (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT)) + IS_ENABLED(CONFIG_USBC_OCP) && + (fault & TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT)) pd_handle_overcurrent(port); if (tcpc_config[port].drv->handle_fault) @@ -1101,16 +1080,15 @@ static int tcpci_handle_fault(int port, int fault) return rv; } -enum ec_error_list tcpci_set_bist_test_mode(const int port, - const bool enable) +enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable) { int rv; rv = tcpc_update8(port, TCPC_REG_TCPC_CTRL, - TCPC_REG_TCPC_CTRL_BIST_TEST_MODE, - enable ? MASK_SET : MASK_CLR); - rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK, - TCPC_REG_ALERT_RX_STATUS, enable ? MASK_CLR : MASK_SET); + TCPC_REG_TCPC_CTRL_BIST_TEST_MODE, + enable ? MASK_SET : MASK_CLR); + rv |= tcpc_update16(port, TCPC_REG_ALERT_MASK, TCPC_REG_ALERT_RX_STATUS, + enable ? MASK_CLR : MASK_SET); return rv; } @@ -1166,8 +1144,8 @@ static void tcpci_check_vbus_changed(int port, int alert, uint32_t *pd_event) if ((get_usb_pd_vbus_detect() == USB_PD_VBUS_DETECT_TCPC) && IS_ENABLED(CONFIG_USB_CHARGER)) { /* Update charge manager with new VBUS state */ - usb_charger_vbus_change(port, - !!(tcpc_vbus[port] & BIT(VBUS_PRESENT))); + usb_charger_vbus_change(port, !!(tcpc_vbus[port] & + BIT(VBUS_PRESENT))); if (pd_event) *pd_event |= TASK_EVENT_WAKE; @@ -1203,8 +1181,7 @@ void tcpci_tcpc_alert(int port) if (alert & TCPC_REG_ALERT_FAULT) { int fault; - if (tcpci_get_fault(port, &fault) == EC_SUCCESS && - fault != 0 && + if (tcpci_get_fault(port, &fault) == EC_SUCCESS && fault != 0 && tcpci_handle_fault(port, fault) == EC_SUCCESS && tcpci_clear_fault(port, fault) == EC_SUCCESS) CPRINTS("C%d FAULT 0x%02X handled", port, fault); @@ -1217,8 +1194,8 @@ void tcpci_tcpc_alert(int port) */ if (alert & TCPC_REG_ALERT_TX_COMPLETE) pd_transmit_complete(port, alert & TCPC_REG_ALERT_TX_SUCCESS ? - TCPC_TX_COMPLETE_SUCCESS : - TCPC_TX_COMPLETE_FAILED); + TCPC_TX_COMPLETE_SUCCESS : + TCPC_TX_COMPLETE_FAILED); /* Pull all RX messages from TCPC into EC memory */ failed_attempts = 0; @@ -1229,7 +1206,6 @@ void tcpci_tcpc_alert(int port) if (tcpm_alert_status(port, &alert)) ++failed_attempts; - /* * EC RX FIFO is full. Deassert ALERT# line to exit interrupt * handler by discarding pending message from TCPC RX FIFO. @@ -1237,8 +1213,8 @@ void tcpci_tcpc_alert(int port) if (retval == EC_ERROR_OVERFLOW) { CPRINTS("C%d: PD RX OVF!", port); tcpc_write16(port, TCPC_REG_ALERT, - TCPC_REG_ALERT_RX_STATUS | - TCPC_REG_ALERT_RX_BUF_OVF); + TCPC_REG_ALERT_RX_STATUS | + TCPC_REG_ALERT_RX_BUF_OVF); } /* Ensure we don't loop endlessly */ @@ -1307,8 +1283,8 @@ void tcpci_tcpc_alert(int port) alert & TCPC_REG_ALERT_TX_FAILED) CPRINTS("C%d Hard Reset sent", port); - if (tcpm_tcpc_has_frs_control(port) - && (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS)) + if (tcpm_tcpc_has_frs_control(port) && + (alert_ext & TCPC_REG_ALERT_EXT_SNK_FRS)) pd_got_frs_signal(port); /* @@ -1365,7 +1341,6 @@ int tcpci_get_chip_info(int port, int live, i = &cached_info[port]; - /* If already cached && live data is not asked, return cached value */ if (i->vendor_id && !live) { /* @@ -1463,9 +1438,9 @@ int tcpci_tcpm_init(int port) * Alert assertion when CC_STATUS.Looking4Connection changes state. */ if (tcpc_config[port].flags & TCPC_FLAGS_TCPCI_REV2_0) { - error = tcpc_update8(port, TCPC_REG_TCPC_CTRL, - TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT, - MASK_SET); + error = tcpc_update8( + port, TCPC_REG_TCPC_CTRL, + TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT, MASK_SET); if (error) CPRINTS("C%d: Failed to init TCPC_CTRL!", port); } @@ -1492,10 +1467,10 @@ int tcpci_tcpm_init(int port) tcpc_vbus[port] = 0; } else { /* Initial level, set appropriately */ - tcpc_vbus[port] = (power_status & - TCPC_REG_POWER_STATUS_VBUS_PRES) - ? BIT(VBUS_PRESENT) - : BIT(VBUS_SAFE0V); + tcpc_vbus[port] = + (power_status & TCPC_REG_POWER_STATUS_VBUS_PRES) ? + BIT(VBUS_PRESENT) : + BIT(VBUS_SAFE0V); } /* Enable/disable VBUS monitor by the flag */ @@ -1511,8 +1486,8 @@ int tcpci_tcpm_init(int port) * Force an update to the VBUS status in case the TCPC doesn't send a * power status changed interrupt later. */ - tcpci_check_vbus_changed(port, - TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS, + tcpci_check_vbus_changed( + port, TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_EXT_STATUS, NULL); error = init_alert_mask(port); @@ -1686,11 +1661,9 @@ static const struct tcpc_reg_dump_map tcpc_regs[] = { .name = "FAULT_STATUS_MASK", .size = 1, }, - { - .addr = TCPC_REG_EXT_STATUS_MASK, - .name = "EXT_STATUS_MASK", - .size = 1 - }, + { .addr = TCPC_REG_EXT_STATUS_MASK, + .name = "EXT_STATUS_MASK", + .size = 1 }, { .addr = TCPC_REG_ALERT_EXTENDED_MASK, .name = "ALERT_EXTENDED_MASK", @@ -1833,43 +1806,43 @@ void tcpc_dump_std_registers(int port) #endif const struct tcpm_drv tcpci_tcpm_drv = { - .init = &tcpci_tcpm_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &tcpci_tcpm_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .get_vbus_voltage = &tcpci_get_vbus_voltage, - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .get_vbus_voltage = &tcpci_get_vbus_voltage, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &tcpci_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &tcpci_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif .tcpc_enable_auto_discharge_disconnect = &tcpci_tcpc_enable_auto_discharge_disconnect, #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, - .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, - .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, - .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &tcpci_get_chip_info, + .get_snk_ctrl = &tcpci_tcpm_get_snk_ctrl, + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .get_src_ctrl = &tcpci_tcpm_get_src_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &tcpci_enter_low_power_mode, + .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP - .dump_registers = &tcpc_dump_std_registers, + .dump_registers = &tcpc_dump_std_registers, #endif }; -- cgit v1.2.1 From 61337be33e96688def59674a4ed32bf8c0d71ac6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:17 -0600 Subject: board/cappy2/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I68f875b4534d130cfead52c0fa0a68477e6636fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728132 Reviewed-by: Jeremy Bettis --- board/cappy2/board.c | 40 +++++++++++++++++----------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/board/cappy2/board.c b/board/cappy2/board.c index c6f560b503..6fe550d8ef 100644 --- a/board/cappy2/board.c +++ b/board/cappy2/board.c @@ -5,7 +5,6 @@ /* cappy2 board-specific configuration */ - #include "adc_chip.h" #include "button.h" #include "cbi_fw_config.h" @@ -39,8 +38,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -80,7 +79,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -159,7 +157,6 @@ __override void board_power_5v_enable(int enable) */ gpio_set_level(GPIO_EN_PP5000, !!enable); gpio_set_level(GPIO_EN_USB_A0_VBUS, !!enable); - } int board_is_sourcing_vbus(int port) @@ -168,13 +165,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < CONFIG_USB_PD_PORT_MAX_COUNT); + int is_real_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); int i; int old_port; @@ -234,8 +229,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -341,23 +336,22 @@ void board_init(void) /* modify AC DC prochot value */ isl923x_set_ac_prochot(CHARGER_SOLO, 4096); isl923x_set_dc_prochot(CHARGER_SOLO, 6000); - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Cpu", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Cpu", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 4fffc021298bc277fbec4198d16e4516723d43b0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:24 -0600 Subject: baseboard/hatch/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iae1dc68471dd2aa10fcae61acc69be7d4de529a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727523 Reviewed-by: Jeremy Bettis --- baseboard/hatch/battery.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/baseboard/hatch/battery.c b/baseboard/hatch/battery.c index 063aa3721d..5cca5b02d8 100644 --- a/baseboard/hatch/battery.c +++ b/baseboard/hatch/battery.c @@ -32,8 +32,9 @@ static int battery_init(void) { int batt_status; - return battery_status(&batt_status) ? 0 : - !!(batt_status & STATUS_INITIALIZED); + return battery_status(&batt_status) ? + 0 : + !!(batt_status & STATUS_INITIALIZED); } /* -- cgit v1.2.1 From 886cd3098186f14a1443d14e86e4d3f9e0ef066c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:20 -0600 Subject: driver/retimer/kb800x.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie0ee73ea331d72c6c5c786896032c869eee120dc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730041 Reviewed-by: Jeremy Bettis --- driver/retimer/kb800x.h | 68 ++++++++++++++++++++++--------------------------- 1 file changed, 31 insertions(+), 37 deletions(-) diff --git a/driver/retimer/kb800x.h b/driver/retimer/kb800x.h index 5f8cf2810d..dd8c969e2b 100644 --- a/driver/retimer/kb800x.h +++ b/driver/retimer/kb800x.h @@ -12,54 +12,49 @@ #include "gpio_signal.h" #include "usb_mux.h" -#define KB800X_I2C_ADDR0_FLAGS 0x08 -#define KB800X_I2C_ADDR1_FLAGS 0x0C +#define KB800X_I2C_ADDR0_FLAGS 0x08 +#define KB800X_I2C_ADDR1_FLAGS 0x0C extern const struct usb_mux_driver kb800x_usb_mux_driver; /* Set the protocol */ -#define KB800X_REG_PROTOCOL 0x0001 -#define KB800X_PROTOCOL_USB3 0x0 -#define KB800X_PROTOCOL_DPMF 0x1 -#define KB800X_PROTOCOL_DP 0x2 -#define KB800X_PROTOCOL_CIO 0x3 +#define KB800X_REG_PROTOCOL 0x0001 +#define KB800X_PROTOCOL_USB3 0x0 +#define KB800X_PROTOCOL_DPMF 0x1 +#define KB800X_PROTOCOL_DP 0x2 +#define KB800X_PROTOCOL_CIO 0x3 /* Configure the lane orientaitons */ -#define KB800X_REG_ORIENTATION 0x0002 -#define KB800X_ORIENTATION_POLARITY 0x1 -#define KB800X_ORIENTATION_DP_UFP 0x4 -#define KB800X_ORIENTATION_DP_DFP 0x6 -#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8 +#define KB800X_REG_ORIENTATION 0x0002 +#define KB800X_ORIENTATION_POLARITY 0x1 +#define KB800X_ORIENTATION_DP_UFP 0x4 +#define KB800X_ORIENTATION_DP_DFP 0x6 +#define KB800X_ORIENTATION_CIO_LANE_SWAP 0x8 /* Select one, 0x0 for non-legacy */ -#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4) -#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4) -#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_PASSIVE (0x1 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_UNIDIR (0x2 << 4) +#define KB800X_ORIENTATION_CIO_LEGACY_BIDIR (0x3 << 4) -#define KB800X_REG_RESET 0x0006 -#define KB800X_RESET_FSM BIT(0) -#define KB800X_RESET_MM BIT(1) -#define KB800X_RESET_SERDES BIT(2) -#define KB800X_RESET_COM BIT(3) -#define KB800X_RESET_MASK GENMASK(3, 0) +#define KB800X_REG_RESET 0x0006 +#define KB800X_RESET_FSM BIT(0) +#define KB800X_RESET_MM BIT(1) +#define KB800X_RESET_SERDES BIT(2) +#define KB800X_RESET_COM BIT(3) +#define KB800X_RESET_MASK GENMASK(3, 0) -#define KB800X_REG_XBAR_OVR 0x5040 -#define KB800X_XBAR_OVR_EN BIT(6) +#define KB800X_REG_XBAR_OVR 0x5040 +#define KB800X_XBAR_OVR_EN BIT(6) /* Registers to configure the elastic buffer input connection */ -#define KB800X_REG_XBAR_EB1SEL 0x5044 -#define KB800X_REG_XBAR_EB23SEL 0x5045 -#define KB800X_REG_XBAR_EB4SEL 0x5046 -#define KB800X_REG_XBAR_EB56SEL 0x5047 +#define KB800X_REG_XBAR_EB1SEL 0x5044 +#define KB800X_REG_XBAR_EB23SEL 0x5045 +#define KB800X_REG_XBAR_EB4SEL 0x5046 +#define KB800X_REG_XBAR_EB56SEL 0x5047 /* Registers to configure the elastic buffer output connection (x=0-7) */ -#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048+((x)/2)) +#define KB800X_REG_TXSEL_FROM_PHY(x) (0x5048 + ((x) / 2)) -enum kb800x_ss_lane { - KB800X_TX0 = 0, - KB800X_TX1, - KB800X_RX0, - KB800X_RX1 -}; +enum kb800x_ss_lane { KB800X_TX0 = 0, KB800X_TX1, KB800X_RX0, KB800X_RX1 }; enum kb800x_phy_lane { KB800X_A0 = 0, @@ -82,8 +77,8 @@ enum kb800x_eb { KB800X_EB6 }; -#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2*((x) & 0x1)) -#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x) & 0x1) +#define KB800X_FLIP_SS_LANE(x) ((x) + 1 - 2 * ((x)&0x1)) +#define KB800X_LANE_NUMBER_FROM_PHY(x) ((x)&0x1) #define KB800X_PHY_IS_AB(x) ((x) <= KB800X_B1) struct kb800x_control_t { @@ -106,5 +101,4 @@ struct kb800x_control_t { extern struct kb800x_control_t kb800x_control[]; - #endif /* __CROS_EC_KB800X_H */ -- cgit v1.2.1 From 4b9116bd8e649555a292ba47c63b6826d0eaf695 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:57 -0600 Subject: include/i2c_hid.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01faed06f5a800c8a3f5ca02ce2abff20a96f284 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730284 Reviewed-by: Jeremy Bettis --- include/i2c_hid.h | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/include/i2c_hid.h b/include/i2c_hid.h index 8568b42837..1a53be4d49 100644 --- a/include/i2c_hid.h +++ b/include/i2c_hid.h @@ -26,25 +26,25 @@ * I2C_HID_HID_DESC_REGISTER is defined in the ACPI table so please make sure * you have put in the same value there. */ -#define I2C_HID_HID_DESC_REGISTER 0x0001 -#define I2C_HID_REPORT_DESC_REGISTER 0x1000 -#define I2C_HID_INPUT_REPORT_REGISTER 0x2000 -#define I2C_HID_COMMAND_REGISTER 0x3000 -#define I2C_HID_DATA_REGISTER 0x3000 +#define I2C_HID_HID_DESC_REGISTER 0x0001 +#define I2C_HID_REPORT_DESC_REGISTER 0x1000 +#define I2C_HID_INPUT_REPORT_REGISTER 0x2000 +#define I2C_HID_COMMAND_REGISTER 0x3000 +#define I2C_HID_DATA_REGISTER 0x3000 /* I2C-HID commands */ -#define I2C_HID_CMD_RESET 0x01 -#define I2C_HID_CMD_GET_REPORT 0x02 -#define I2C_HID_CMD_SET_REPORT 0x03 -#define I2C_HID_CMD_GET_IDLE 0x04 -#define I2C_HID_CMD_SET_IDLE 0x05 -#define I2C_HID_CMD_GET_PROTOCOL 0x06 -#define I2C_HID_CMD_SET_PROTOCOL 0x07 -#define I2C_HID_CMD_SET_POWER 0x08 +#define I2C_HID_CMD_RESET 0x01 +#define I2C_HID_CMD_GET_REPORT 0x02 +#define I2C_HID_CMD_SET_REPORT 0x03 +#define I2C_HID_CMD_GET_IDLE 0x04 +#define I2C_HID_CMD_SET_IDLE 0x05 +#define I2C_HID_CMD_GET_PROTOCOL 0x06 +#define I2C_HID_CMD_SET_PROTOCOL 0x07 +#define I2C_HID_CMD_SET_POWER 0x08 /* Common HID fields */ -#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor) -#define I2C_HID_BCD_VERSION 0x0100 +#define I2C_HID_DESC_LENGTH sizeof(struct i2c_hid_descriptor) +#define I2C_HID_BCD_VERSION 0x0100 /* I2C-HID HID descriptor */ struct __packed i2c_hid_descriptor { -- cgit v1.2.1 From fb749409eb77f4f5db7ce7d55c185e8bdc63cdb8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:16:49 -0600 Subject: include/usb_api.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6008fc42582e59836fc631499b41edff3f59a83b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730427 Reviewed-by: Jeremy Bettis --- include/usb_api.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/usb_api.h b/include/usb_api.h index 79ee9406e9..057475fe87 100644 --- a/include/usb_api.h +++ b/include/usb_api.h @@ -76,7 +76,9 @@ void usb_restore_suspended_state(void); #ifdef CONFIG_USB_REMOTE_WAKEUP void usb_wake(void); #else -static inline void usb_wake(void) {} +static inline void usb_wake(void) +{ +} #endif /* Board-specific USB wake, for side-band wake, called by usb_wake above. */ -- cgit v1.2.1 From f5a29612673726078fcaa3b291dae5715b2674c9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:21 -0600 Subject: board/gelarshie/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I684ac8c4cf3b55671f1987be9050d512db002a2e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728396 Reviewed-by: Jeremy Bettis --- board/gelarshie/usbc_config.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/gelarshie/usbc_config.c b/board/gelarshie/usbc_config.c index 86a2f4663f..4813dbfdcc 100644 --- a/board/gelarshie/usbc_config.c +++ b/board/gelarshie/usbc_config.c @@ -11,8 +11,8 @@ #include "gpio.h" #include "usb_pd.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 804279cdb752ef48fa2cd0f263522c7d6c53b20c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:25 -0600 Subject: board/atlas/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib7d1562017e7809aaf98dbf2bb244fa9363f2f14 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728016 Reviewed-by: Jeremy Bettis --- board/atlas/usb_pd_policy.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/board/atlas/usb_pd_policy.c b/board/atlas/usb_pd_policy.c index 77a4941a9a..0d1cad4004 100644 --- a/board/atlas/usb_pd_policy.c +++ b/board/atlas/usb_pd_policy.c @@ -23,12 +23,12 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; int board_vbus_source_enabled(int port) { @@ -38,9 +38,9 @@ int board_vbus_source_enabled(int port) static void board_vbus_update_source_current(int port) { enum gpio_signal gpio_5v_en = port ? GPIO_USB_C1_5V_EN : - GPIO_USB_C0_5V_EN; + GPIO_USB_C0_5V_EN; enum gpio_signal gpio_3a_en = port ? GPIO_EN_USB_C1_3A : - GPIO_EN_USB_C0_3A; + GPIO_EN_USB_C0_3A; /* * 1.5 vs 3.0 A limit is controlled by a dedicated gpio where @@ -67,8 +67,8 @@ int pd_snk_is_vbus_provided(int port) int pd_set_power_supply_ready(int port) { /* Disable charging */ - gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L : - GPIO_EN_USB_C0_CHARGE_L, 1); + gpio_set_level(port ? GPIO_EN_USB_C1_CHARGE_L : GPIO_EN_USB_C0_CHARGE_L, + 1); /* Ensure we advertise the proper available current quota */ charge_manager_source_port(port, 1); @@ -111,15 +111,12 @@ int pd_check_vconn_swap(int port) return gpio_get_level(GPIO_PMIC_SLP_SUS_L); } -__override void pd_execute_data_swap(int port, - enum pd_data_role data_role) +__override void pd_execute_data_swap(int port, enum pd_data_role data_role) { /* Only port 0 supports device mode. */ if (port != 0) return; - gpio_set_level(GPIO_USB2_ID, - (data_role == PD_ROLE_UFP) ? 1 : 0); - gpio_set_level(GPIO_USB2_VBUSSENSE, - (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_ID, (data_role == PD_ROLE_UFP) ? 1 : 0); + gpio_set_level(GPIO_USB2_VBUSSENSE, (data_role == PD_ROLE_UFP) ? 1 : 0); } -- cgit v1.2.1 From a171399796289ad691c599cc9273cd00612a3873 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:07 -0600 Subject: chip/npcx/system_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8fbda8d15740fdc0a0656e83fb162d85db878911 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729443 Reviewed-by: Jeremy Bettis --- chip/npcx/system_chip.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index 2314f1458a..6da21b3e53 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -9,34 +9,34 @@ #define __CROS_EC_SYSTEM_CHIP_H /* Flags for BBRM_DATA_INDEX_WAKE */ -#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ -#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ -#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ +#define HIBERNATE_WAKE_MTC BIT(0) /* MTC alarm */ +#define HIBERNATE_WAKE_PIN BIT(1) /* Wake pin */ +#define HIBERNATE_WAKE_LCT BIT(2) /* LCT alarm */ /* * Indicate that EC enters hibernation via PSL. When EC wakes up from * hibernation and this flag is set, it will check the related status bit to * know the actual wake up source. (From LCT or physical wakeup pins) */ -#define HIBERNATE_WAKE_PSL BIT(3) +#define HIBERNATE_WAKE_PSL BIT(3) /* Indices for battery-backed ram (BBRAM) data position */ enum bbram_data_index { - BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ + BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */ - BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ - BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ - BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ - BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ - BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ + BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ + BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ + BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ + BBRM_DATA_INDEX_TRY_SLOT = 14, /* Vboot EC try slot */ + BBRM_DATA_INDEX_PD2 = 15, /* USB-PD saved port2 state */ /* Index 16-31 available for future use */ - BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ - BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of - * panic data starting at index - * 36. - */ - BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ - BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) - */ + BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ + BBRM_DATA_INDEX_PANIC_FLAGS = 35, /* Flag to indicate validity of + * panic data starting at index + * 36. + */ + BBRM_DATA_INDEX_PANIC_BKUP = 36, /* Panic data (index 35-63)*/ + BBRM_DATA_INDEX_LCT_TIME = 64, /* The start time of LCT(4 bytes) + */ }; enum psl_pin_t { @@ -69,7 +69,7 @@ void system_check_bbram_on_reset(void); #if defined(CHIP_FAMILY_NPCX5) /* Bypass for GMDA issue of ROM api utilities only on npcx5 series */ void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, - uint32_t size, uint32_t exeAddr); + uint32_t size, uint32_t exeAddr); /* Begin address for hibernate utility; defined in linker script */ extern unsigned int __flash_lpfw_start; -- cgit v1.2.1 From a3818fd090c1496c267c99e4f7726937ce2a4a9f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:02 -0600 Subject: driver/usb_mux/tusb1064.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I268d6ce97a5d4344ea60613eb046835f0e6efb9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730172 Reviewed-by: Jeremy Bettis --- driver/usb_mux/tusb1064.h | 67 +++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/driver/usb_mux/tusb1064.h b/driver/usb_mux/tusb1064.h index d6eb649532..3c6a7cd000 100644 --- a/driver/usb_mux/tusb1064.h +++ b/driver/usb_mux/tusb1064.h @@ -17,43 +17,43 @@ * F -> floating * 1 -> tied to VCC */ -#define TUSB1064_I2C_ADDR0_FLAGS 0x44 -#define TUSB1064_I2C_ADDR1_FLAGS 0x45 -#define TUSB1064_I2C_ADDR2_FLAGS 0x46 -#define TUSB1064_I2C_ADDR3_FLAGS 0x47 -#define TUSB1064_I2C_ADDR4_FLAGS 0x20 -#define TUSB1064_I2C_ADDR5_FLAGS 0x21 -#define TUSB1064_I2C_ADDR6_FLAGS 0x22 -#define TUSB1064_I2C_ADDR7_FLAGS 0x23 -#define TUSB1064_I2C_ADDR8_FLAGS 0x10 -#define TUSB1064_I2C_ADDR9_FLAGS 0x11 -#define TUSB1064_I2C_ADDR10_FLAGS 0x12 -#define TUSB1064_I2C_ADDR11_FLAGS 0x13 -#define TUSB1064_I2C_ADDR12_FLAGS 0x0C -#define TUSB1064_I2C_ADDR13_FLAGS 0x0D -#define TUSB1064_I2C_ADDR14_FLAGS 0x0E -#define TUSB1064_I2C_ADDR15_FLAGS 0x0F +#define TUSB1064_I2C_ADDR0_FLAGS 0x44 +#define TUSB1064_I2C_ADDR1_FLAGS 0x45 +#define TUSB1064_I2C_ADDR2_FLAGS 0x46 +#define TUSB1064_I2C_ADDR3_FLAGS 0x47 +#define TUSB1064_I2C_ADDR4_FLAGS 0x20 +#define TUSB1064_I2C_ADDR5_FLAGS 0x21 +#define TUSB1064_I2C_ADDR6_FLAGS 0x22 +#define TUSB1064_I2C_ADDR7_FLAGS 0x23 +#define TUSB1064_I2C_ADDR8_FLAGS 0x10 +#define TUSB1064_I2C_ADDR9_FLAGS 0x11 +#define TUSB1064_I2C_ADDR10_FLAGS 0x12 +#define TUSB1064_I2C_ADDR11_FLAGS 0x13 +#define TUSB1064_I2C_ADDR12_FLAGS 0x0C +#define TUSB1064_I2C_ADDR13_FLAGS 0x0D +#define TUSB1064_I2C_ADDR14_FLAGS 0x0E +#define TUSB1064_I2C_ADDR15_FLAGS 0x0F /* TUSB1064 General Register */ -#define TUSB1064_REG_GENERAL 0x0a -#define REG_GENERAL_CTLSEL_USB3 BIT(0) -#define REG_GENERAL_CTLSEL_ANYDP BIT(1) -#define REG_GENERAL_FLIPSEL BIT(2) +#define TUSB1064_REG_GENERAL 0x0a +#define REG_GENERAL_CTLSEL_USB3 BIT(0) +#define REG_GENERAL_CTLSEL_ANYDP BIT(1) +#define REG_GENERAL_FLIPSEL BIT(2) #if defined(CONFIG_USB_MUX_TUSB1044) || defined(CONFIG_USB_MUX_TUSB546) -#define REG_GENERAL_HPDIN_OVERRIDE BIT(3) +#define REG_GENERAL_HPDIN_OVERRIDE BIT(3) #else -#define REG_GENERAL_DP_EN_CTRL BIT(3) +#define REG_GENERAL_DP_EN_CTRL BIT(3) #endif -#define REG_GENERAL_EQ_OVERRIDE BIT(4) +#define REG_GENERAL_EQ_OVERRIDE BIT(4) /* AUX and DP Lane Control Register */ -#define TUSB1064_REG_AUXDPCTRL 0x13 +#define TUSB1064_REG_AUXDPCTRL 0x13 #define TUSB1064_AUXDPCTRL_AUX_SNOOP_DISABLE BIT(7) -#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR 0x30 -#define TUSB1064_AUXDPCTRL_DP3_DISABLE BIT(3) -#define TUSB1064_AUXDPCTRL_DP2_DISABLE BIT(2) -#define TUSB1064_AUXDPCTRL_DP1_DISABLE BIT(1) -#define TUSB1064_AUXDPCTRL_DP0_DISABLE BIT(0) +#define TUSB1064_AUXDPCTRL_AUX_SBU_OVR 0x30 +#define TUSB1064_AUXDPCTRL_DP3_DISABLE BIT(3) +#define TUSB1064_AUXDPCTRL_DP2_DISABLE BIT(2) +#define TUSB1064_AUXDPCTRL_DP1_DISABLE BIT(1) +#define TUSB1064_AUXDPCTRL_DP0_DISABLE BIT(0) /* Receiver Equalization GPIO Control */ #define TUSB1064_REG_DP1DP3EQ_SEL 0x10 @@ -78,19 +78,18 @@ #define TUSB1064_DP_EQ_RX_12_1_DB 0xF #ifndef TUSB1064_DP1EQ -#define TUSB1064_DP1EQ(nr) ((nr) << 4) +#define TUSB1064_DP1EQ(nr) ((nr) << 4) #endif #ifndef TUSB1064_DP3EQ -#define TUSB1064_DP3EQ(nr) ((nr) << 0) +#define TUSB1064_DP3EQ(nr) ((nr) << 0) #endif #ifndef TUSB1064_DP0EQ -#define TUSB1064_DP0EQ(nr) ((nr) << 4) +#define TUSB1064_DP0EQ(nr) ((nr) << 4) #endif #ifndef TUSB1064_DP2EQ -#define TUSB1064_DP2EQ(nr) ((nr) << 0) +#define TUSB1064_DP2EQ(nr) ((nr) << 0) #endif - /* TUSB1064 Receiver Equalization GPIO Control */ #define TUSB1064_REG_SSRX2RX1EQ_SEL 0x20 #define TUSB1064_REG_SSTXEQ_SEL 0x21 -- cgit v1.2.1 From ddad8da0bc22b84b9e4e861aeab63f80d49ac9af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:19 -0600 Subject: driver/charger/sy21612.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7b9721312b07d8e5f6c40991a8aca916eb33bfa2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729942 Reviewed-by: Jeremy Bettis --- driver/charger/sy21612.c | 59 ++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/driver/charger/sy21612.c b/driver/charger/sy21612.c index 7bc6caa4ea..394be47fdc 100644 --- a/driver/charger/sy21612.c +++ b/driver/charger/sy21612.c @@ -5,7 +5,6 @@ * SILERGY SY21612 buck-boost converter driver. */ - #include "console.h" #include "hooks.h" #include "i2c.h" @@ -15,8 +14,8 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHARGER, outstr) -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static int sy21612_clear_set_reg(int reg, int clear, int set) { @@ -31,8 +30,7 @@ static int sy21612_clear_set_reg(int reg, int clear, int set) val |= set; if (val != old_val || clear || set) - rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, - reg, val); + rv = i2c_write8(I2C_PORT_SY21612, SY21612_ADDR_FLAGS, reg, val); return rv; } @@ -44,64 +42,62 @@ static int sy21612_read(int reg, int *val) int sy21612_enable_regulator(int enable) { - return enable ? - sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_REG_EN) : - sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_REG_EN, 0); + return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0, + SY21612_CTRL1_REG_EN) : + sy21612_clear_set_reg(SY21612_CTRL1, + SY21612_CTRL1_REG_EN, 0); } int sy21612_enable_adc(int enable) { - return enable ? - sy21612_clear_set_reg(SY21612_CTRL1, 0, SY21612_CTRL1_ADC_EN) : - sy21612_clear_set_reg(SY21612_CTRL1, SY21612_CTRL1_ADC_EN, 0); + return enable ? sy21612_clear_set_reg(SY21612_CTRL1, 0, + SY21612_CTRL1_ADC_EN) : + sy21612_clear_set_reg(SY21612_CTRL1, + SY21612_CTRL1_ADC_EN, 0); } int sy21612_set_adc_mode(int auto_mode) { return auto_mode ? - sy21612_clear_set_reg(SY21612_CTRL1, - 0, SY21612_CTRL1_ADC_AUTO_MODE) : - sy21612_clear_set_reg(SY21612_CTRL1, - SY21612_CTRL1_ADC_AUTO_MODE, 0); + sy21612_clear_set_reg(SY21612_CTRL1, 0, + SY21612_CTRL1_ADC_AUTO_MODE) : + sy21612_clear_set_reg(SY21612_CTRL1, + SY21612_CTRL1_ADC_AUTO_MODE, 0); } int sy21612_set_vbus_discharge(int auto_discharge) { return auto_discharge ? - sy21612_clear_set_reg(SY21612_CTRL1, - SY21612_CTRL1_VBUS_NDISCHG, 0) : - sy21612_clear_set_reg(SY21612_CTRL1, - 0, SY21612_CTRL1_VBUS_NDISCHG); + sy21612_clear_set_reg(SY21612_CTRL1, + SY21612_CTRL1_VBUS_NDISCHG, 0) : + sy21612_clear_set_reg(SY21612_CTRL1, 0, + SY21612_CTRL1_VBUS_NDISCHG); } int sy21612_set_switching_freq(enum sy21612_switching_freq freq) { - return sy21612_clear_set_reg(SY21612_CTRL2, - SY21612_CTRL2_FREQ_MASK, + return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_FREQ_MASK, freq << SY21612_CTRL2_FREQ_SHIFT); } int sy21612_set_vbus_volt(enum sy21612_vbus_volt volt) { - return sy21612_clear_set_reg(SY21612_CTRL2, - SY21612_CTRL2_VBUS_MASK, + return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_MASK, volt << SY21612_CTRL2_VBUS_SHIFT); } int sy21612_set_vbus_adj(enum sy21612_vbus_adj adj) { - return sy21612_clear_set_reg(SY21612_CTRL2, - SY21612_CTRL2_VBUS_ADJ_MASK, + return sy21612_clear_set_reg(SY21612_CTRL2, SY21612_CTRL2_VBUS_ADJ_MASK, adj << SY21612_CTRL2_VBUS_ADJ_SHIFT); } int sy21612_set_sink_mode(int sink_mode) { - return sink_mode ? - sy21612_clear_set_reg(SY21612_PROT2, - 0, SY21612_PROT2_SINK_MODE) : - sy21612_clear_set_reg(SY21612_PROT2, - SY21612_PROT2_SINK_MODE, 0); + return sink_mode ? sy21612_clear_set_reg(SY21612_PROT2, 0, + SY21612_PROT2_SINK_MODE) : + sy21612_clear_set_reg(SY21612_PROT2, + SY21612_PROT2_SINK_MODE, 0); } int sy21612_is_power_good(void) @@ -208,6 +204,5 @@ static int command_sy21612(int argc, char **argv) return 0; } -DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612, - NULL, NULL); +DECLARE_CONSOLE_COMMAND(sy21612, command_sy21612, NULL, NULL); #endif -- cgit v1.2.1 From 2d0dc5c9700618abb2270e61da6344e5fc712a2e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:29 -0600 Subject: board/shotzo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I993f636be1b9eaf24da8762643fcfc2294a1f729 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728938 Reviewed-by: Jeremy Bettis --- board/shotzo/board.h | 40 ++++++++++++++++++---------------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/board/shotzo/board.h b/board/shotzo/board.h index 7235499624..df27eddb1f 100644 --- a/board/shotzo/board.h +++ b/board/shotzo/board.h @@ -23,21 +23,22 @@ /* Charger */ #define CONFIG_CHARGE_RAMP_HW -#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_SM5803 /* C0 and C1: Charger */ #define CONFIG_USB_PD_VBUS_DETECT_CHARGER #define CONFIG_USB_PD_5V_CHARGER_CTRL #define CONFIG_CHARGER_OTG -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCEL_BMA4XX /* 2nd source Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -70,8 +71,8 @@ /* TCPC */ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ -#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ +#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP /* C0: ITE EC TCPC */ +#define CONFIG_USB_PD_TCPM_PS8705 /* C1: PS8705 TCPC*/ #define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1 #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE #define CONFIG_USB_PD_TCPC_LOW_POWER @@ -82,8 +83,8 @@ #define CONFIG_STEINHART_HART_3V3_51K1_47K_4050B /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ /* USB Type A Features */ #define USB_PORT_COUNT 1 @@ -106,21 +107,16 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_SUB_ANALOG, /* ADC13 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ - ADC_TEMP_SENSOR_4, /* ADC16 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_SUB_ANALOG, /* ADC13 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_TEMP_SENSOR_4, /* ADC16 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 53aa69f15cd42e485990d95c684b20823b0d5250 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:36:27 -0600 Subject: board/genesis/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I54c65a3ceca015c78b6a87b428e5b18346d02c6c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728398 Reviewed-by: Jeremy Bettis --- board/genesis/board.h | 88 ++++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 46 deletions(-) diff --git a/board/genesis/board.h b/board/genesis/board.h index 9c9233590e..7a806597fc 100644 --- a/board/genesis/board.h +++ b/board/genesis/board.h @@ -12,8 +12,8 @@ #define CONFIG_UART_TX_BUF_SIZE 4096 /* NPCX7 config */ -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ -#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ /* Internal SPI flash on NPCX796FC is 512 kB */ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) @@ -40,7 +40,7 @@ #undef CONFIG_HIBERNATE #define CONFIG_HOST_INTERFACE_ESPI #define CONFIG_LED_COMMON -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_LTO #define CONFIG_PWM #define CONFIG_VBOOT_EFS2 @@ -118,13 +118,13 @@ /* I2C Bus Configuration */ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_INA NPCX_I2C_PORT0_0 -#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 -#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 -#define I2C_PORT_PSE NPCX_I2C_PORT4_1 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_INA NPCX_I2C_PORT0_0 +#define I2C_PORT_PPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT3_0 +#define I2C_PORT_PSE NPCX_I2C_PORT4_1 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD) @@ -134,11 +134,11 @@ #include "registers.h" enum adc_channel { - ADC_SNS_PP3300, /* ADC2 */ - ADC_SNS_PP1050, /* ADC7 */ - ADC_VBUS, /* ADC4 */ - ADC_PPVAR_IMON, /* ADC9 */ - ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_SNS_PP3300, /* ADC2 */ + ADC_SNS_PP1050, /* ADC7 */ + ADC_VBUS, /* ADC4 */ + ADC_PPVAR_IMON, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ /* Number of ADC channels */ ADC_CH_COUNT }; @@ -163,11 +163,7 @@ enum mft_channel { MFT_CH_COUNT, }; -enum temp_sensor_id { - TEMP_SENSOR_CORE, - TEMP_SENSOR_COUNT -}; - +enum temp_sensor_id { TEMP_SENSOR_CORE, TEMP_SENSOR_COUNT }; /* Board specific handlers */ void led_alert(int enable); @@ -179,20 +175,20 @@ void show_critical_error(void); /* * Barrel-jack power (4 bits). */ -#define EC_CFG_BJ_POWER_L 0 -#define EC_CFG_BJ_POWER_H 3 +#define EC_CFG_BJ_POWER_L 0 +#define EC_CFG_BJ_POWER_H 3 #define EC_CFG_BJ_POWER_MASK GENMASK(EC_CFG_BJ_POWER_H, EC_CFG_BJ_POWER_L) /* * USB Connector 4 not present (1 bit). */ -#define EC_CFG_NO_USB4_L 4 -#define EC_CFG_NO_USB4_H 4 +#define EC_CFG_NO_USB4_L 4 +#define EC_CFG_NO_USB4_H 4 #define EC_CFG_NO_USB4_MASK GENMASK(EC_CFG_NO_USB4_H, EC_CFG_NO_USB4_L) /* * Thermal solution config (3 bits). */ -#define EC_CFG_THERMAL_L 5 -#define EC_CFG_THERMAL_H 7 +#define EC_CFG_THERMAL_L 5 +#define EC_CFG_THERMAL_H 7 #define EC_CFG_THERMAL_MASK GENMASK(EC_CFG_THERMAL_H, EC_CFG_THERMAL_L) unsigned int ec_config_get_thermal_solution(void); @@ -200,30 +196,30 @@ unsigned int ec_config_get_thermal_solution(void); #endif /* !__ASSEMBLER__ */ /* Pin renaming */ -#define GPIO_WP_L GPIO_EC_WP_ODL -#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL -#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS -#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L +#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PP5000_A_PG_OD GPIO_PG_PP5000_A_OD +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_RECOVERY_L GPIO_EC_RECOVERY_BTN_ODL +#define GPIO_RECOVERY_L_2 GPIO_H1_EC_RECOVERY_BTN_ODL +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SYS_PWROK GPIO_EC_PCH_SYS_PWROK +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S4_L GPIO_SLP_S4_L +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_ROA_RAILS +#define GPIO_AC_PRESENT GPIO_BJ_ADP_PRESENT_L /* * There is no RSMRST input, so alias it to the output. This short-circuits * common_intel_x86_handle_rsmrst. */ -#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L +#define GPIO_PG_EC_RSMRST_ODL GPIO_PCH_RSMRST_L #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 012acfd058e69efb0783c85b221f66a6866bef48 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:48 -0600 Subject: baseboard/octopus/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib7e74b74cac2b0a70a93dfc209eae0b89b842412 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727937 Reviewed-by: Jeremy Bettis --- baseboard/octopus/cbi_ssfc.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/baseboard/octopus/cbi_ssfc.h b/baseboard/octopus/cbi_ssfc.h index 0b9eafc888..d2b2843ed5 100644 --- a/baseboard/octopus/cbi_ssfc.h +++ b/baseboard/octopus/cbi_ssfc.h @@ -18,8 +18,8 @@ enum ssfc_tcpc_p1 { SSFC_TCPC_P1_PS8751, SSFC_TCPC_P1_PS8755, }; -#define SSFC_TCPC_P1_OFFSET 0 -#define SSFC_TCPC_P1_MASK GENMASK(2, 0) +#define SSFC_TCPC_P1_OFFSET 0 +#define SSFC_TCPC_P1_MASK GENMASK(2, 0) /* * PPC Port 1 (Bits 3-5) @@ -29,8 +29,8 @@ enum ssfc_ppc_p1 { SSFC_PPC_P1_NX20P348X, SSFC_PPC_P1_SYV682X, }; -#define SSFC_PPC_P1_OFFSET 3 -#define SSFC_PPC_P1_MASK GENMASK(5, 3) +#define SSFC_PPC_P1_OFFSET 3 +#define SSFC_PPC_P1_MASK GENMASK(5, 3) /* * Charger (Bits 8-6) @@ -40,8 +40,8 @@ enum ssfc_charger { SSFC_CHARGER_ISL9238, SSFC_CHARGER_BQ25710, }; -#define SSFC_CHARGER_OFFSET 6 -#define SSFC_CHARGER_MASK GENMASK(8, 6) +#define SSFC_CHARGER_OFFSET 6 +#define SSFC_CHARGER_MASK GENMASK(8, 6) /* * Audio (Bits 11-9) @@ -56,8 +56,8 @@ enum ssfc_sensor { SSFC_SENSOR_ICM426XX, SSFC_SENSOR_BMI260, }; -#define SSFC_SENSOR_OFFSET 12 -#define SSFC_SENSOR_MASK GENMASK(14, 12) +#define SSFC_SENSOR_OFFSET 12 +#define SSFC_SENSOR_MASK GENMASK(14, 12) enum ssfc_tcpc_p1 get_cbi_ssfc_tcpc_p1(void); enum ssfc_ppc_p1 get_cbi_ssfc_ppc_p1(void); -- cgit v1.2.1 From 701489b755d5d78456b809a4dea26390ec62e644 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:52 -0600 Subject: board/ezkinil/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia3592f9533c659b9232a378bc06a2c5cddc86fea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728351 Reviewed-by: Jeremy Bettis --- board/ezkinil/led.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/board/ezkinil/led.c b/board/ezkinil/led.c index 7c425fa138..b16e09bd44 100644 --- a/board/ezkinil/led.c +++ b/board/ezkinil/led.c @@ -8,26 +8,34 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 100; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{LED_OFF, 1 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_BLUE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { LED_OFF, 1 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + }; BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES); const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From 3a1d34f7e0bd2136390983cc99da1d9cde2a8653 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:57 -0600 Subject: include/usb_tc_sm.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic72127682dde4a55592988253c4a0ef989d1600c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730450 Reviewed-by: Jeremy Bettis --- include/usb_tc_sm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/usb_tc_sm.h b/include/usb_tc_sm.h index 4aaacd522b..64676a79c0 100644 --- a/include/usb_tc_sm.h +++ b/include/usb_tc_sm.h @@ -24,7 +24,7 @@ enum try_src_override_t { * This is the maximum voltage a sink can request * while charging. */ -#define TYPE_C_VOLTAGE 5000 /* mV */ +#define TYPE_C_VOLTAGE 5000 /* mV */ /* * Type C default sink current (mA) @@ -32,7 +32,7 @@ enum try_src_override_t { * This is the maximum current a sink can draw if charging * while in the Audio Accessory State. */ -#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */ +#define TYPE_C_AUDIO_ACC_CURRENT 500 /* mA */ /** * Returns true if TypeC State machine is in attached source state. @@ -256,7 +256,7 @@ void pd_request_vconn_swap_off(int port); * @return 0 if cc1 is connected, else 1 for cc2 */ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Called by the state machine framework to initialize the -- cgit v1.2.1 From 47125f273f97a83f9f09aeb0c0997f88b61feb84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:00 -0600 Subject: board/sweetberry/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I44814045525a28cbafcb14e8e9b74c45f832a2fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728976 Reviewed-by: Jeremy Bettis --- board/sweetberry/board.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/board/sweetberry/board.h b/board/sweetberry/board.h index 55aab7d1ee..9290886784 100644 --- a/board/sweetberry/board.h +++ b/board/sweetberry/board.h @@ -48,28 +48,28 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_UPDATE 1 -#define USB_IFACE_POWER 2 -#define USB_IFACE_I2C 3 -#define USB_IFACE_COUNT 4 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_UPDATE 1 +#define USB_IFACE_POWER 2 +#define USB_IFACE_I2C 3 +#define USB_IFACE_COUNT 4 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_UPDATE 2 -#define USB_EP_POWER 3 -#define USB_EP_I2C 4 -#define USB_EP_COUNT 5 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_UPDATE 2 +#define USB_EP_POWER 3 +#define USB_EP_I2C 4 +#define USB_EP_COUNT 5 #define CONFIG_USB_I2C #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_0 0 -#define I2C_PORT_1 1 -#define I2C_PORT_2 2 -#define FMPI2C_PORT_3 3 -#define I2C_PORT_COUNT 4 +#define I2C_PORT_0 0 +#define I2C_PORT_1 1 +#define I2C_PORT_2 2 +#define FMPI2C_PORT_3 3 +#define I2C_PORT_COUNT 4 /* This is not actually a Chromium EC so disable some features. */ #undef CONFIG_WATCHDOG_HELP -- cgit v1.2.1 From 5d062d6ea8d5aa4a39b7024c10b2cef22695989f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:02 -0600 Subject: board/gimble/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I38861c8c35833d8fade2ee1bcce5f9c04d638d39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728411 Reviewed-by: Jeremy Bettis --- board/gimble/charger.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) mode change 120000 => 100644 board/gimble/charger.c diff --git a/board/gimble/charger.c b/board/gimble/charger.c deleted file mode 120000 index 476ce97df2..0000000000 --- a/board/gimble/charger.c +++ /dev/null @@ -1 +0,0 @@ -../../baseboard/brya/charger_bq25720.c \ No newline at end of file diff --git a/board/gimble/charger.c b/board/gimble/charger.c new file mode 100644 index 0000000000..cbc657271b --- /dev/null +++ b/board/gimble/charger.c @@ -0,0 +1,90 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "charger.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/charger/bq25710.h" +#include "usbc_ppc.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +#ifndef CONFIG_ZEPHYR +/* Charger Chip Configuration */ +const struct charger_config_t chg_chips[] = { + { + .i2c_port = I2C_PORT_CHARGER, + .i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS, + .drv = &bq25710_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(chg_chips) == CHARGER_NUM); +#endif + +int board_set_active_charge_port(int port) +{ + int is_valid_port = board_is_usb_pd_port_present(port); + int i; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTFUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +__overridable void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} -- cgit v1.2.1 From 0413bcfbc47cc728630724768e4754896aa15917 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:13 -0600 Subject: board/dingdong/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I969bc424ed8faf6ecc4a78535bd389e1509078e0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728204 Reviewed-by: Jeremy Bettis --- board/dingdong/usb_pd_config.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/board/dingdong/usb_pd_config.h b/board/dingdong/usb_pd_config.h index 2f01c275a8..e783ff874c 100644 --- a/board/dingdong/usb_pd_config.h +++ b/board/dingdong/usb_pd_config.h @@ -49,7 +49,7 @@ static inline void spi_enable_clock(int port) #define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0 #define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0 -#define TIM_CCR_CS 1 +#define TIM_CCR_CS 1 #define EXTI_COMP_MASK(p) BIT(21) #define IRQ_COMP STM32_IRQ_COMP /* triggers packet detection on comparator falling edge */ @@ -88,9 +88,8 @@ static inline void pd_tx_enable(int port, int polarity) static inline void pd_tx_disable(int port, int polarity) { /* output low on SPI TX (PB4) to disable the FET */ - STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) - & ~(3 << (2*4))) - | (1 << (2*4)); + STM32_GPIO_MODER(GPIO_B) = + (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2 * 4))) | (1 << (2 * 4)); /* put the low level reference in Hi-Z */ gpio_set_level(GPIO_PD_CC1_TX_EN, 0); } @@ -101,8 +100,8 @@ static inline void pd_select_polarity(int port, int polarity) * use the right comparator : CC1 -> PA1 (COMP1 INP) * use VrefInt / 2 as INM (about 600mV) */ - STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) - | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) | + STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; } /* Initialize pins used for TX and put them in Hi-Z */ @@ -111,7 +110,9 @@ static inline void pd_tx_init(void) gpio_config_module(MODULE_USB_PD, 1); } -static inline void pd_set_host_mode(int port, int enable) {} +static inline void pd_set_host_mode(int port, int enable) +{ +} static inline void pd_config_init(int port, uint8_t power_role) { -- cgit v1.2.1 From f0879b4959cf52636adb6ea9c4a579baa7ed0f80 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:00 -0600 Subject: board/kano/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b1b6c42059d2faef567c1cea26cf9ca4f74f4fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728523 Reviewed-by: Jeremy Bettis --- board/kano/sensors.c | 93 ++++++++++++++++++++++------------------------------ 1 file changed, 39 insertions(+), 54 deletions(-) diff --git a/board/kano/sensors.c b/board/kano/sensors.c index e3e2f9d920..b89de1def6 100644 --- a/board/kano/sensors.c +++ b/board/kano/sensors.c @@ -65,27 +65,19 @@ static enum base_accelgyro_type base_accelgyro_config; * TODO:(b/197200940): Verify lid and base orientation * matrix on proto board. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_bma422_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -static const mat33_fp_t base_bmi260_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_bma422_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +static const mat33_fp_t base_bmi260_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static struct motion_sensor_t bmi260_base_accel = { .name = "Base Accel", @@ -244,15 +236,15 @@ static void baseboard_sensors_detect(void) return; ret = i2c_read8(I2C_PORT_ACCEL, BMA4_I2C_ADDR_SECONDARY, - BMA4_CHIP_ID_ADDR, &val); + BMA4_CHIP_ID_ADDR, &val); if (ret == 0 && val == BMA422_CHIP_ID) { motion_sensors[LID_ACCEL] = bma422_lid_accel; ccprints("LID_ACCEL is BMA422"); } else ccprints("LID_ACCEL is KX022"); - ret = bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS, - BMI260_CHIP_ID, &val); + ret = bmi_read8(I2C_PORT_ACCEL, BMI260_ADDR0_FLAGS, BMI260_CHIP_ID, + &val); if (ret == 0 && val == BMI260_CHIP_ID_MAJOR) { motion_sensors[BASE_ACCEL] = bmi260_base_accel; motion_sensors[BASE_GYRO] = bmi260_base_gyro; @@ -263,8 +255,7 @@ static void baseboard_sensors_detect(void) ccprints("BASE ACCEL IS ICM426XX"); } } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_sensors_detect, - HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_sensors_detect, HOOK_PRIO_DEFAULT); static void baseboard_sensors_init(void) { @@ -285,24 +276,18 @@ void motion_interrupt(enum gpio_signal signal) /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_FAN] = { - .name = "FAN", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_FAN - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "CHARGER", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_FAN] = { .name = "FAN", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_FAN }, + [TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -316,8 +301,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = 0, \ [EC_TEMP_THRESH_HALT] = 0, \ @@ -346,8 +331,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -363,8 +348,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN_28W \ - { \ +#define THERMAL_FAN_28W \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -376,7 +361,7 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; .temp_fan_max = C_TO_K(62), \ } __maybe_unused static const struct ec_thermal_config thermal_fan_28w = - THERMAL_FAN_28W; + THERMAL_FAN_28W; /* * Set value to zero to disable charger thermal control. @@ -384,8 +369,8 @@ __maybe_unused static const struct ec_thermal_config thermal_fan_28w = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = 0, \ [EC_TEMP_THRESH_HALT] = 0, \ @@ -397,13 +382,13 @@ __maybe_unused static const struct ec_thermal_config thermal_fan_28w = .temp_fan_max = 0, \ } __maybe_unused static const struct ec_thermal_config thermal_charger = - THERMAL_CHARGER; + THERMAL_CHARGER; /* this should really be "const" */ struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_DDR_SOC] = THERMAL_CPU, [TEMP_SENSOR_2_FAN] = THERMAL_FAN, - [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, + [TEMP_SENSOR_3_CHARGER] = THERMAL_CHARGER, }; BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From 0b3d8f0a3611e9a1f58e805e2b370d7e9fbd04ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:40 -0600 Subject: zephyr/projects/corsola/src/krabby/charger_workaround.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id0b3ae033f7336b8813b7780a12978330bc974ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730741 Reviewed-by: Jeremy Bettis --- .../corsola/src/krabby/charger_workaround.c | 27 +++++++--------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/charger_workaround.c b/zephyr/projects/corsola/src/krabby/charger_workaround.c index 373917db56..3001327ed8 100644 --- a/zephyr/projects/corsola/src/krabby/charger_workaround.c +++ b/zephyr/projects/corsola/src/krabby/charger_workaround.c @@ -12,11 +12,9 @@ static void enter_hidden_mode(void) { i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - 0xF1, 0x69); + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF1, 0x69); i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - 0xF2, 0x96); + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF2, 0x96); } /* b/194967754#comment5: work around for IBUS ADC unstable issue */ @@ -28,22 +26,17 @@ static void ibus_adc_workaround(void) i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT9490_REG_ADC_CHANNEL0, - RT9490_VSYS_ADC_DIS, - MASK_SET); + RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_SET); enter_hidden_mode(); /* undocumented registers... */ i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - 0x52, 0xC4); + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x52, 0xC4); i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT9490_REG_ADC_CHANNEL0, - RT9490_VSYS_ADC_DIS, - MASK_CLR); + RT9490_REG_ADC_CHANNEL0, RT9490_VSYS_ADC_DIS, MASK_CLR); } /* b/214880220#comment44: lock i2c at 400khz */ @@ -56,12 +49,10 @@ static void i2c_speed_workaround(void) enter_hidden_mode(); /* Set to Auto mode, default run at 400kHz */ i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - 0x71, 0x22); + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0x71, 0x22); /* Manually select for 400kHz, valid only when 0x71[7] == 1 */ i2c_write8(chg_chips[CHARGER_SOLO].i2c_port, - chg_chips[CHARGER_SOLO].i2c_addr_flags, - 0xF7, 0x14); + chg_chips[CHARGER_SOLO].i2c_addr_flags, 0xF7, 0x14); } static void pwm_freq_workaround(void) @@ -81,9 +72,7 @@ static void eoc_deglitch_workaround(void) /* set end-of-charge deglitch time to 2ms */ i2c_update8(chg_chips[CHARGER_SOLO].i2c_port, chg_chips[CHARGER_SOLO].i2c_addr_flags, - RT9490_REG_ADD_CTRL0, - RT9490_TD_EOC, - MASK_CLR); + RT9490_REG_ADD_CTRL0, RT9490_TD_EOC, MASK_CLR); } static void board_rt9490_workaround(void) -- cgit v1.2.1 From e3045c2a456da2d35e2fad5e4f4e8d0338140e82 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:24:35 -0600 Subject: board/brya/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I33669083520e169445a41c1d3ff0821f6f3e313f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728104 Reviewed-by: Jeremy Bettis --- board/brya/sensors.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/board/brya/sensors.c b/board/brya/sensors.c index 51841b8599..a6dc9bd50b 100644 --- a/board/brya/sensors.c +++ b/board/brya/sensors.c @@ -55,18 +55,14 @@ static struct stprivate_data g_lis2dw12_data; static struct lsm6dso_data lsm6dso_data; /* TODO(b/184779333): calibrate the orientation matrix on later board stage */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TODO(b/184779743): verify orientation matrix */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TCS3400 private data */ static struct als_drv_data_t g_tcs3400_data = { @@ -292,8 +288,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -322,8 +318,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_AMBIENT \ - { \ +#define THERMAL_AMBIENT \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -351,8 +347,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ambient = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(105), \ [EC_TEMP_THRESH_HALT] = C_TO_K(120), \ @@ -372,8 +368,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_WWAN \ - { \ +#define THERMAL_WWAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(130), \ [EC_TEMP_THRESH_HALT] = C_TO_K(130), \ -- cgit v1.2.1 From 3bf010748d7d59746d1a023ddbd424003488719d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:49 -0600 Subject: board/shuboz/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I106723233b727e5ff2563be8306e8fa7caaf0de0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728943 Reviewed-by: Jeremy Bettis --- board/shuboz/board.h | 87 ++++++++++++++++++++-------------------------------- 1 file changed, 33 insertions(+), 54 deletions(-) diff --git a/board/shuboz/board.h b/board/shuboz/board.h index 6573273b93..9bb82a17e6 100644 --- a/board/shuboz/board.h +++ b/board/shuboz/board.h @@ -21,11 +21,11 @@ #define CONFIG_USB_PD_PORT_MAX_COUNT 2 #define CONFIG_USB_PORT_ENABLE_DYNAMIC -#undef PD_MAX_POWER_MW -#define PD_MAX_POWER_MW 45000 -#undef PD_MAX_CURRENT_MA -#define PD_MAX_CURRENT_MA 3000 -#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON +#undef PD_MAX_POWER_MW +#define PD_MAX_POWER_MW 45000 +#undef PD_MAX_CURRENT_MA +#define PD_MAX_CURRENT_MA 3000 +#undef CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON #define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 40000 #define CONFIG_CHARGER_PROFILE_OVERRIDE @@ -61,59 +61,46 @@ #define CONFIG_POWER_BUTTON_INIT_TIMEOUT 5 /* GPIO mapping from board specific name to EC common name. */ -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL -#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL -#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L -#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L -#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK -#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L -#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL -#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD -#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD -#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L -#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL +#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_EDP_BL_DISABLE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PCH_PWRBTN_L GPIO_EC_FCH_PWR_BTN_L +#define GPIO_PCH_RSMRST_L GPIO_EC_FCH_RSMRST_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L +#define GPIO_PCH_SYS_PWROK GPIO_EC_FCH_PWROK +#define GPIO_PCH_WAKE_L GPIO_EC_FCH_WAKE_L +#define GPIO_POWER_BUTTON_L GPIO_EC_PWR_BTN_ODL +#define GPIO_S0_PGOOD GPIO_S0_PWROK_OD +#define GPIO_S5_PGOOD GPIO_EC_PWROK_OD +#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L +#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE #ifndef __ASSEMBLER__ /* This I2C moved. Temporarily detect and support the V0 HW. */ extern int I2C_PORT_BATTERY; -enum adc_channel { - ADC_TEMP_SENSOR_CHARGER, - ADC_TEMP_SENSOR_SOC, - ADC_CH_COUNT -}; +enum adc_channel { ADC_TEMP_SENSOR_CHARGER, ADC_TEMP_SENSOR_SOC, ADC_CH_COUNT }; enum battery_type { BATTERY_CM1500, BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_KBLIGHT = 0, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT = 0, PWM_CH_COUNT }; -enum ioex_port { - IOEX_C0_NCT3807 = 0, - IOEX_C1_NCT3807, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT3807 = 0, IOEX_C1_NCT3807, IOEX_PORT_COUNT }; -#define PORT_TO_HPD(port) ((port == 0) \ - ? GPIO_USB3_C0_DP2_HPD \ - : GPIO_DP1_HPD) +#define PORT_TO_HPD(port) ((port == 0) ? GPIO_USB3_C0_DP2_HPD : GPIO_DP1_HPD) enum temp_sensor_id { TEMP_SENSOR_CHARGER = 0, @@ -122,17 +109,9 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum usba_port { - USBA_PORT_A0 = 0, - USBA_PORT_A1, - USBA_PORT_COUNT -}; +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; /***************************************************************************** * CBI EC FW Configuration -- cgit v1.2.1 From 29ff8f2d4cf2da66c2c5d42b04a48e985dc80125 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:30 -0600 Subject: board/panqueque/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e7df1a9f5fb34352ef1d8c84f8f4f14853db888 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728812 Reviewed-by: Jeremy Bettis --- board/panqueque/board.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/board/panqueque/board.h b/board/panqueque/board.h index 39aed68f8e..95249696fd 100644 --- a/board/panqueque/board.h +++ b/board/panqueque/board.h @@ -21,8 +21,8 @@ #undef CONFIG_FLASH_PSTATE_LOCKED /* USB Type C and USB PD defines */ -#define USB_PD_PORT_HOST 0 -#define USB_PD_PORT_USB3 1 +#define USB_PD_PORT_HOST 0 +#define USB_PD_PORT_USB3 1 /* * Only the host and display usbc ports are usb-pd capable. There is a 2nd usbc @@ -40,9 +40,9 @@ #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 /* I2C port names */ -#define I2C_PORT_I2C1 0 -#define I2C_PORT_I2C2 1 -#define I2C_PORT_I2C3 2 +#define I2C_PORT_I2C1 0 +#define I2C_PORT_I2C2 1 +#define I2C_PORT_I2C3 2 /* Required symbolic I2C port names */ #define I2C_PORT_MP4245 I2C_PORT_I2C3 @@ -68,7 +68,7 @@ #define GPIO_TRIGGER_1 GPIO_USB3_A5_CDP_EN #define GPIO_TRIGGER_2 GPIO_USB3_A6_CDP_EN -enum debug_gpio { +enum debug_gpio { TRIGGER_1 = 0, TRIGGER_2, }; -- cgit v1.2.1 From eb89833235bbe9c85715d8e110793c4d5961ff2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:28 -0600 Subject: board/plankton/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c538801c7ae491031617f421cebc6d01ce0178d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728833 Reviewed-by: Jeremy Bettis --- board/plankton/board.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/plankton/board.h b/board/plankton/board.h index 39ab706cd2..89bdad9d84 100644 --- a/board/plankton/board.h +++ b/board/plankton/board.h @@ -58,7 +58,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" @@ -77,18 +77,18 @@ enum board_src_cap { }; /* 3.0A Rp */ -#define PD_SRC_VNC PD_SRC_3_0_VNC_MV -#define PD_SNK_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV +#define PD_SRC_VNC PD_SRC_3_0_VNC_MV +#define PD_SNK_RD_THRESHOLD PD_SRC_3_0_RD_THRESH_MV /* delay necessary for the voltage transition on the power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 5000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Set USB PD source capability */ void board_set_source_cap(enum board_src_cap cap); -- cgit v1.2.1 From aa53bae7ac318d4f6e703676c11fc6e05cca37cd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:57:02 -0600 Subject: board/nucleo-f412zg/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I29640545a3dbc994c3ee223cfa58cd51395ff5f7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728780 Reviewed-by: Jeremy Bettis --- board/nucleo-f412zg/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/nucleo-f412zg/board.h b/board/nucleo-f412zg/board.h index f6e1368847..2ef279cb71 100644 --- a/board/nucleo-f412zg/board.h +++ b/board/nucleo-f412zg/board.h @@ -26,6 +26,6 @@ * Enable the blink example that exercises the LEDs. */ #define CONFIG_BLINK -#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3 +#define CONFIG_BLINK_LEDS GPIO_LED1, GPIO_LED2, GPIO_LED3 #endif /* __BOARD_H */ -- cgit v1.2.1 From 50072d66ea2c2d4082f88ee05904ac3316943c51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:58 -0600 Subject: chip/npcx/peci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iecd8b1b5e82f6f54c0410ac6eb5f1a1498b0ee72 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727021 Reviewed-by: Jeremy Bettis --- chip/npcx/peci.c | 66 +++++++++++++++++++++++++------------------------------- 1 file changed, 29 insertions(+), 37 deletions(-) diff --git a/chip/npcx/peci.c b/chip/npcx/peci.c index 6f82b932b0..7b198a81f9 100644 --- a/chip/npcx/peci.c +++ b/chip/npcx/peci.c @@ -19,31 +19,29 @@ #include "temp_sensor.h" #include "util.h" - /* Initial PECI baud rate */ -#define PECI_BAUD_RATE 750000 - -#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */ +#define PECI_BAUD_RATE 750000 +#define TEMP_AVG_LENGTH 4 /* Should be power of 2 */ /* PECI Time-out */ -#define PECI_DONE_TIMEOUT_US (10*MSEC) +#define PECI_DONE_TIMEOUT_US (10 * MSEC) -#define NULL_PENDING_TASK_ID 0xFFFFFFFF -#define PECI_MAX_FIFO_SIZE 16 -#define PROC_SOCKET 0x30 +#define NULL_PENDING_TASK_ID 0xFFFFFFFF +#define PECI_MAX_FIFO_SIZE 16 +#define PROC_SOCKET 0x30 /* PECI Command Code */ enum peci_command_t { - PECI_COMMAND_PING = 0x00, - PECI_COMMAND_GET_DIB = 0xF7, - PECI_COMMAND_GET_TEMP = 0x01, - PECI_COMMAND_RD_PKG_CFG = 0xA1, - PECI_COMMAND_WR_PKG_CFG = 0xA5, - PECI_COMMAND_RD_IAMSR = 0xB1, - PECI_COMMAND_RD_PCI_CFG = 0x61, - PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1, - PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5, - PECI_COMMAND_NONE = 0xFF + PECI_COMMAND_PING = 0x00, + PECI_COMMAND_GET_DIB = 0xF7, + PECI_COMMAND_GET_TEMP = 0x01, + PECI_COMMAND_RD_PKG_CFG = 0xA1, + PECI_COMMAND_WR_PKG_CFG = 0xA5, + PECI_COMMAND_RD_IAMSR = 0xB1, + PECI_COMMAND_RD_PCI_CFG = 0x61, + PECI_COMMAND_RD_PCI_CFG_LOCAL = 0xE1, + PECI_COMMAND_WR_PCI_CFG_LOCAL = 0xE5, + PECI_COMMAND_NONE = 0xFF }; #define PECI_COMMAND_GET_TEMP_WR_LENS 0x00 @@ -68,12 +66,8 @@ static int peci_pending_task_id; * @param *wr_data Buffer pointer of write data * @return TASK_EVENT_PECI_DONE that mean slave had a response */ -static uint32_t peci_trans( - uint8_t wr_length, - uint8_t rd_length, - enum peci_command_t cmd_code, - uint8_t *wr_data -) +static uint32_t peci_trans(uint8_t wr_length, uint8_t rd_length, + enum peci_command_t cmd_code, uint8_t *wr_data) { uint32_t events; /* Ensure no PECI transaction is in progress */ @@ -100,7 +94,7 @@ static uint32_t peci_trans( /* Write-Length */ if (cmd_code != PECI_COMMAND_PING) { if ((cmd_code == PECI_COMMAND_WR_PKG_CFG) || - (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) { + (cmd_code == PECI_COMMAND_WR_PCI_CFG_LOCAL)) { /*CMD+AWFCS*/ NPCX_PECI_WR_LENGTH = wr_length + 2; /* Enable AWFCS */ @@ -110,7 +104,7 @@ static uint32_t peci_trans( NPCX_PECI_WR_LENGTH = wr_length + 1; /* Enable AWFCS */ CLEAR_BIT(NPCX_PECI_CTL_STS, - NPCX_PECI_CTL_STS_AWFCS_EN); + NPCX_PECI_CTL_STS_AWFCS_EN); } } @@ -119,9 +113,7 @@ static uint32_t peci_trans( /* It should be using a interrupt , don't waste cpu computing power */ peci_pending_task_id = task_get_current(); - return task_wait_event_mask(TASK_EVENT_PECI_DONE, - PECI_DONE_TIMEOUT_US); - + return task_wait_event_mask(TASK_EVENT_PECI_DONE, PECI_DONE_TIMEOUT_US); } /** @@ -143,8 +135,8 @@ int peci_get_cpu_temp(void) /* Start PECI trans */ events = peci_trans(PECI_COMMAND_GET_TEMP_WR_LENS, - PECI_COMMAND_GET_TEMP_RD_LENS, - PECI_COMMAND_GET_TEMP, NULL); + PECI_COMMAND_GET_TEMP_RD_LENS, + PECI_COMMAND_GET_TEMP, NULL); /* if return DONE , that mean slave had a PECI response */ if ((events & TASK_EVENT_PECI_DONE) == TASK_EVENT_PECI_DONE) { /* check CRC & ABRT */ @@ -223,7 +215,7 @@ static void peci_freq_changed(void) * Maximum bit rate should not extend the field's boundaries. */ if (freq != 0) { - baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1; + baud = (uint8_t)(freq / (4 * PECI_BAUD_RATE)) - 1; /* Set maximum PECI baud rate (bit0 - bit4) */ if (baud > 0x1F) baud = 0x1F; @@ -247,7 +239,7 @@ static void peci_init(void) /* Enable clock for PECI peripheral */ clock_enable_peripheral(CGC_OFFSET_PECI, CGC_PECI_MASK, - CGC_MODE_RUN | CGC_MODE_SLEEP); + CGC_MODE_RUN | CGC_MODE_SLEEP); /* Set PECI freq */ peci_freq_changed(); @@ -269,7 +261,8 @@ static void peci_init(void) DECLARE_HOOK(HOOK_INIT, peci_init, HOOK_PRIO_DEFAULT); /* If received a PECI DONE interrupt, post the event to PECI task */ -static void peci_done_interrupt(void){ +static void peci_done_interrupt(void) +{ if (peci_pending_task_id != NULL_PENDING_TASK_ID) task_set_event(peci_pending_task_id, TASK_EVENT_PECI_DONE); peci_sts = NPCX_PECI_CTL_STS & 0x18; @@ -293,6 +286,5 @@ static int command_peci_temp(int argc, char **argv) ccprintf("CPU temp = %d K = %d\n", t, K_TO_C(t)); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, - NULL, - "Print CPU temperature"); +DECLARE_CONSOLE_COMMAND(pecitemp, command_peci_temp, NULL, + "Print CPU temperature"); -- cgit v1.2.1 From beb325d0cefeb96f054cad210ae1ff9b2a586323 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:40:28 -0600 Subject: common/usb_pd_alt_mode_dfp.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I01db9caccbb50bb247adf7338056b4b799a47a51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729770 Reviewed-by: Jeremy Bettis --- common/usb_pd_alt_mode_dfp.c | 259 +++++++++++++++++++++---------------------- 1 file changed, 126 insertions(+), 133 deletions(-) diff --git a/common/usb_pd_alt_mode_dfp.c b/common/usb_pd_alt_mode_dfp.c index 1de01f9c48..40535bf025 100644 --- a/common/usb_pd_alt_mode_dfp.c +++ b/common/usb_pd_alt_mode_dfp.c @@ -23,8 +23,8 @@ #include "util.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -51,8 +51,8 @@ uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT]; /* Console command multi-function preference set for a PD port. */ __maybe_unused bool dp_port_mf_allow[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true}; - + [0 ... CONFIG_USB_PD_PORT_MAX_COUNT - 1] = true +}; __overridable const struct svdm_response svdm_rsp = { .identity = NULL, @@ -60,8 +60,7 @@ __overridable const struct svdm_response svdm_rsp = { .modes = NULL, }; -static int pd_get_mode_idx(int port, enum tcpci_msg_type type, - uint16_t svid) +static int pd_get_mode_idx(int port, enum tcpci_msg_type type, uint16_t svid) { int amode_idx; struct partner_active_modes *active = @@ -75,8 +74,7 @@ static int pd_get_mode_idx(int port, enum tcpci_msg_type type, return -1; } -static int pd_allocate_mode(int port, enum tcpci_msg_type type, - uint16_t svid) +static int pd_allocate_mode(int port, enum tcpci_msg_type type, uint16_t svid) { int i, j; struct svdm_amode_data *modep; @@ -122,21 +120,20 @@ static int pd_allocate_mode(int port, enum tcpci_msg_type type, return -1; } -static int validate_mode_request(struct svdm_amode_data *modep, - uint16_t svid, int opos) +static int validate_mode_request(struct svdm_amode_data *modep, uint16_t svid, + int opos) { if (!modep->fx) return 0; if (svid != modep->fx->svid) { - CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n", - svid, modep->fx->svid); + CPRINTF("ERR:svid r:0x%04x != c:0x%04x\n", svid, + modep->fx->svid); return 0; } if (opos != modep->opos) { - CPRINTF("ERR:opos r:%d != c:%d\n", - opos, modep->opos); + CPRINTF("ERR:opos r:%d != c:%d\n", opos, modep->opos); return 0; } @@ -199,7 +196,7 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status) if (IS_ENABLED(CONFIG_CMD_MFALLOW)) mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) && - dp_port_mf_allow[port]; + dp_port_mf_allow[port]; else mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); @@ -229,8 +226,8 @@ int pd_dfp_dp_get_pin_mode(int port, uint32_t status) return 1 << get_next_bit(&pin_caps); } -struct svdm_amode_data *pd_get_amode_data(int port, - enum tcpci_msg_type type, uint16_t svid) +struct svdm_amode_data *pd_get_amode_data(int port, enum tcpci_msg_type type, + uint16_t svid) { int idx = pd_get_mode_idx(port, type, svid); struct partner_active_modes *active = @@ -244,8 +241,8 @@ struct svdm_amode_data *pd_get_amode_data(int port, * Enter default mode ( payload[0] == 0 ) or attempt to enter mode via svid & * opos */ -uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, - uint16_t svid, int opos) +uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, uint16_t svid, + int opos) { int mode_idx = pd_allocate_mode(port, type, svid); struct svdm_amode_data *modep; @@ -285,7 +282,7 @@ uint32_t pd_dfp_enter_mode(int port, enum tcpci_msg_type type, /* TODO(b/170372521) : Incorporate exit mode specific changes to DPM SM */ int pd_dfp_exit_mode(int port, enum tcpci_msg_type type, uint16_t svid, - int opos) + int opos) { struct svdm_amode_data *modep; struct partner_active_modes *active = @@ -358,7 +355,7 @@ void dfp_consume_attention(int port, uint32_t *payload) } void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload) + uint32_t *payload) { int ptype; struct pd_discovery *disc; @@ -372,8 +369,8 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, ptype = PD_IDH_PTYPE(payload[VDO_I(IDH)]); disc = pd_get_am_discovery_and_notify_access(port, type); - identity_size = MIN(sizeof(union disc_ident_ack), - (cnt - 1) * sizeof(uint32_t)); + identity_size = + MIN(sizeof(union disc_ident_ack), (cnt - 1) * sizeof(uint32_t)); /* Note: only store VDOs, not the VDM header */ memcpy(disc->identity.raw_value, payload + 1, identity_size); @@ -383,14 +380,14 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, case IDH_PTYPE_AMA: /* Leave vbus ON if the following macro is false */ if (IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE) && - IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) { + IS_ENABLED(CONFIG_USBC_VCONN_SWAP)) { /* Adapter is requesting vconn, try to supply it */ if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)])) pd_try_vconn_src(port); /* Only disable vbus if vconn was requested */ if (PD_VDO_AMA_VCONN_REQ(payload[VDO_I(AMA)]) && - !PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)])) + !PD_VDO_AMA_VBUS_REQ(payload[VDO_I(AMA)])) pd_power_supply_reset(port); } break; @@ -401,14 +398,14 @@ void dfp_consume_identity(int port, enum tcpci_msg_type type, int cnt, } void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload) + uint32_t *payload) { int i; uint32_t *ptr = payload + 1; int vdo = 1; uint16_t svid0, svid1; struct pd_discovery *disc = - pd_get_am_discovery_and_notify_access(port, type); + pd_get_am_discovery_and_notify_access(port, type); for (i = disc->svid_cnt; i < disc->svid_cnt + 12; i += 2) { if (i >= SVID_DISCOVERY_MAX) { @@ -447,13 +444,13 @@ void dfp_consume_svids(int port, enum tcpci_msg_type type, int cnt, } void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, - uint32_t *payload) + uint32_t *payload) { int svid_idx; struct svid_mode_data *mode_discovery = NULL; struct pd_discovery *disc = - pd_get_am_discovery_and_notify_access(port, type); - uint16_t response_svid = (uint16_t) PD_VDO_VID(payload[0]); + pd_get_am_discovery_and_notify_access(port, type); + uint16_t response_svid = (uint16_t)PD_VDO_VID(payload[0]); for (svid_idx = 0; svid_idx < disc->svid_cnt; ++svid_idx) { uint16_t svid = disc->svids[svid_idx].svid; @@ -467,15 +464,15 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, const struct svid_mode_data *requested_mode_data = pd_get_next_mode(port, type); CPRINTF("C%d: Mode response for undiscovered SVID %x, but TCPM " - "requested SVID %x\n", - port, response_svid, requested_mode_data->svid); + "requested SVID %x\n", + port, response_svid, requested_mode_data->svid); /* * Although SVIDs discovery seemed like it succeeded before, the * partner is now responding with undiscovered SVIDs. Discovery * cannot reasonably continue under these circumstances. */ pd_set_modes_discovery(port, type, requested_mode_data->svid, - PD_DISC_FAIL); + PD_DISC_FAIL); return; } @@ -483,15 +480,15 @@ void dfp_consume_modes(int port, enum tcpci_msg_type type, int cnt, if (mode_discovery->mode_cnt < 1) { CPRINTF("ERR:NOMODE\n"); pd_set_modes_discovery(port, type, mode_discovery->svid, - PD_DISC_FAIL); + PD_DISC_FAIL); return; } memcpy(mode_discovery->mode_vdo, &payload[1], - sizeof(uint32_t) * mode_discovery->mode_cnt); + sizeof(uint32_t) * mode_discovery->mode_cnt); disc->svid_idx++; pd_set_modes_discovery(port, type, mode_discovery->svid, - PD_DISC_COMPLETE); + PD_DISC_COMPLETE); } int pd_alt_mode(int port, enum tcpci_msg_type type, uint16_t svid) @@ -505,7 +502,7 @@ void pd_set_identity_discovery(int port, enum tcpci_msg_type type, enum pd_discovery_state disc) { struct pd_discovery *pd = - pd_get_am_discovery_and_notify_access(port, type); + pd_get_am_discovery_and_notify_access(port, type); pd->identity_discovery = disc; } @@ -519,7 +516,7 @@ enum pd_discovery_state pd_get_identity_discovery(int port, } const union disc_ident_ack *pd_get_identity_response(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { if (type >= DISCOVERY_TYPE_COUNT) return NULL; @@ -529,39 +526,39 @@ const union disc_ident_ack *pd_get_identity_response(int port, uint16_t pd_get_identity_vid(int port) { - const union disc_ident_ack *resp = pd_get_identity_response(port, - TCPCI_MSG_SOP); + const union disc_ident_ack *resp = + pd_get_identity_response(port, TCPCI_MSG_SOP); return resp->idh.usb_vendor_id; } uint16_t pd_get_identity_pid(int port) { - const union disc_ident_ack *resp = pd_get_identity_response(port, - TCPCI_MSG_SOP); + const union disc_ident_ack *resp = + pd_get_identity_response(port, TCPCI_MSG_SOP); return resp->product.product_id; } uint8_t pd_get_product_type(int port) { - const union disc_ident_ack *resp = pd_get_identity_response(port, - TCPCI_MSG_SOP); + const union disc_ident_ack *resp = + pd_get_identity_response(port, TCPCI_MSG_SOP); return resp->idh.product_type; } void pd_set_svids_discovery(int port, enum tcpci_msg_type type, - enum pd_discovery_state disc) + enum pd_discovery_state disc) { struct pd_discovery *pd = - pd_get_am_discovery_and_notify_access(port, type); + pd_get_am_discovery_and_notify_access(port, type); pd->svids_discovery = disc; } enum pd_discovery_state pd_get_svids_discovery(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { const struct pd_discovery *disc = pd_get_am_discovery(port, type); @@ -582,11 +579,11 @@ uint16_t pd_get_svid(int port, uint16_t svid_idx, enum tcpci_msg_type type) return disc->svids[svid_idx].svid; } -void pd_set_modes_discovery(int port, enum tcpci_msg_type type, - uint16_t svid, enum pd_discovery_state disc) +void pd_set_modes_discovery(int port, enum tcpci_msg_type type, uint16_t svid, + enum pd_discovery_state disc) { struct pd_discovery *pd = - pd_get_am_discovery_and_notify_access(port, type); + pd_get_am_discovery_and_notify_access(port, type); int svid_idx; for (svid_idx = 0; svid_idx < pd->svid_cnt; ++svid_idx) { @@ -601,7 +598,7 @@ void pd_set_modes_discovery(int port, enum tcpci_msg_type type, } enum pd_discovery_state pd_get_modes_discovery(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { const struct svid_mode_data *mode_data = pd_get_next_mode(port, type); @@ -615,8 +612,8 @@ enum pd_discovery_state pd_get_modes_discovery(int port, return mode_data->discovery; } -int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid, uint32_t *vdo_out) +int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, uint16_t svid, + uint32_t *vdo_out) { int idx; const struct pd_discovery *disc; @@ -637,7 +634,7 @@ int pd_get_mode_vdo_for_svid(int port, enum tcpci_msg_type type, } const struct svid_mode_data *pd_get_next_mode(int port, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { const struct pd_discovery *disc = pd_get_am_discovery(port, type); const struct svid_mode_data *failed_mode_data = NULL; @@ -672,7 +669,7 @@ const struct svid_mode_data *pd_get_next_mode(int port, } const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, - enum tcpci_msg_type type) + enum tcpci_msg_type type) { const struct pd_discovery *disc = pd_get_am_discovery(port, type); @@ -680,15 +677,15 @@ const uint32_t *pd_get_mode_vdo(int port, uint16_t svid_idx, } bool pd_is_mode_discovered_for_svid(int port, enum tcpci_msg_type type, - uint16_t svid) + uint16_t svid) { const struct pd_discovery *disc = pd_get_am_discovery(port, type); const struct svid_mode_data *mode_data; for (mode_data = disc->svids; mode_data < disc->svids + disc->svid_cnt; - ++mode_data) { + ++mode_data) { if (mode_data->svid == svid && - mode_data->discovery == PD_DISC_COMPLETE) + mode_data->discovery == PD_DISC_COMPLETE) return true; } @@ -812,7 +809,7 @@ bool is_usb2_cable_support(int port) return disc->identity.idh.product_type == IDH_PTYPE_PCABLE || pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 || disc->identity.product_t2.a2_rev30.usb_20_support == - USB2_SUPPORTED; + USB2_SUPPORTED; } bool is_cable_speed_gen2_capable(int port) @@ -823,13 +820,13 @@ bool is_cable_speed_gen2_capable(int port) switch (pd_get_rev(port, TCPCI_MSG_SOP_PRIME)) { case PD_REV20: return disc->identity.product_t1.p_rev20.ss == - USB_R20_SS_U31_GEN1_GEN2; + USB_R20_SS_U31_GEN1_GEN2; case PD_REV30: return disc->identity.product_t1.p_rev30.ss == - USB_R30_SS_U32_U40_GEN2 || + USB_R30_SS_U32_U40_GEN2 || disc->identity.product_t1.p_rev30.ss == - USB_R30_SS_U40_GEN3; + USB_R30_SS_U40_GEN3; default: return false; } @@ -844,9 +841,8 @@ bool is_active_cable_element_retimer(int port) * Revision 2 Active cables do not have Active element support. */ return is_pd_rev3(port, TCPCI_MSG_SOP_PRIME) && - disc->identity.idh.product_type == IDH_PTYPE_ACABLE && - disc->identity.product_t2.a2_rev30.active_elem == - ACTIVE_RETIMER; + disc->identity.idh.product_type == IDH_PTYPE_ACABLE && + disc->identity.product_t2.a2_rev30.active_elem == ACTIVE_RETIMER; } /* @@ -862,7 +858,9 @@ uint32_t pd_get_tbt_mode_vdo(int port, enum tcpci_msg_type type) uint32_t tbt_mode_vdo[PDO_MODES]; return pd_get_mode_vdo_for_svid(port, type, USB_VID_INTEL, - tbt_mode_vdo) ? tbt_mode_vdo[0] : 0; + tbt_mode_vdo) ? + tbt_mode_vdo[0] : + 0; } /* TODO (b/148528713): Need to enable Thunderbolt-compatible mode on TCPMv2 */ @@ -875,8 +873,8 @@ void set_tbt_compat_mode_ready(int port) /* Set usb mux to Thunderbolt-compatible mode */ usb_mux_set(port, USB_PD_MUX_TBT_COMPAT_ENABLED, - USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + USB_SWITCH_CONNECT, + polarity_rm_dts(pd_get_polarity(port))); } } @@ -902,18 +900,16 @@ static bool is_tbt_cable_superspeed(int port) return false; if (IS_ENABLED(CONFIG_USB_PD_REV30) && - is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) - return disc->identity.product_t1.p_rev30.ss == - USB_R30_SS_U32_U40_GEN1 || - disc->identity.product_t1.p_rev30.ss == - USB_R30_SS_U32_U40_GEN2 || - disc->identity.product_t1.p_rev30.ss == - USB_R30_SS_U40_GEN3; + is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) + return disc->identity.product_t1.p_rev30.ss == + USB_R30_SS_U32_U40_GEN1 || + disc->identity.product_t1.p_rev30.ss == + USB_R30_SS_U32_U40_GEN2 || + disc->identity.product_t1.p_rev30.ss == + USB_R30_SS_U40_GEN3; - return disc->identity.product_t1.p_rev20.ss == - USB_R20_SS_U31_GEN1 || - disc->identity.product_t1.p_rev20.ss == - USB_R20_SS_U31_GEN1_GEN2; + return disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1 || + disc->identity.product_t1.p_rev20.ss == USB_R20_SS_U31_GEN1_GEN2; } static enum tbt_compat_cable_speed usb_rev30_to_tbt_speed(enum usb_rev30_ss ss) @@ -958,26 +954,24 @@ enum tbt_compat_cable_speed get_tbt_cable_speed(int port) return TBT_SS_RES_0; disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); - cable_tbt_speed = - usb_rev30_to_tbt_speed(disc->identity.product_t1.p_rev30.ss); + cable_tbt_speed = usb_rev30_to_tbt_speed( + disc->identity.product_t1.p_rev30.ss); } else { cable_tbt_speed = cable_mode_resp.tbt_cable_speed; } - return max_tbt_speed < cable_tbt_speed ? - max_tbt_speed : cable_tbt_speed; + return max_tbt_speed < cable_tbt_speed ? max_tbt_speed : + cable_tbt_speed; } /* Note: Assumes that pins have already been set in safe state */ -int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, - uint32_t *payload) +int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, uint32_t *payload) { union tbt_dev_mode_enter_cmd enter_dev_mode = { .raw_value = 0 }; union tbt_mode_resp_device dev_mode_resp; union tbt_mode_resp_cable cable_mode_resp; enum tcpci_msg_type enter_mode_sop = - sop == TCPCI_MSG_SOP_PRIME_PRIME ? - TCPCI_MSG_SOP_PRIME : sop; + sop == TCPCI_MSG_SOP_PRIME_PRIME ? TCPCI_MSG_SOP_PRIME : sop; /* Table F-12 TBT3 Cable Enter Mode Command */ /* @@ -990,13 +984,12 @@ int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, VDO_SVDM_VERS(pd_get_vdo_ver(port, enter_mode_sop)); /* For TBT3 Cable Enter Mode Command, number of Objects is 1 */ - if ((sop == TCPCI_MSG_SOP_PRIME) || - (sop == TCPCI_MSG_SOP_PRIME_PRIME)) + if ((sop == TCPCI_MSG_SOP_PRIME) || (sop == TCPCI_MSG_SOP_PRIME_PRIME)) return 1; dev_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP); cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); /* Table F-13 TBT3 Device Enter Mode Command */ enter_dev_mode.vendor_spec_b1 = dev_mode_resp.vendor_spec_b1; @@ -1023,7 +1016,8 @@ int enter_tbt_compat_mode(int port, enum tcpci_msg_type sop, enum tbt_compat_rounded_support get_tbt_rounded_support(int port) { union tbt_mode_resp_cable cable_mode_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) + }; /* tbt_rounded_support is zero when uninitialized */ return cable_mode_resp.tbt_rounded; @@ -1055,7 +1049,6 @@ enum usb_rev30_ss get_usb4_cable_speed(int port) enum tbt_compat_cable_speed tbt_speed = get_tbt_cable_speed(port); enum usb_rev30_ss max_usb4_speed; - if (tbt_speed < TBT_SS_U31_GEN1) return USB_R30_SS_U2_ONLY; @@ -1063,19 +1056,19 @@ enum usb_rev30_ss get_usb4_cable_speed(int port) * Converting Thunderbolt-Compatible board speed to equivalent USB4 * speed. */ - max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ? - USB_R30_SS_U40_GEN3 : USB_R30_SS_U32_U40_GEN2; + max_usb4_speed = tbt_speed == TBT_SS_TBT_GEN3 ? USB_R30_SS_U40_GEN3 : + USB_R30_SS_U32_U40_GEN2; if ((get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) && - is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) { + is_pd_rev3(port, TCPCI_MSG_SOP_PRIME)) { const struct pd_discovery *disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); union active_cable_vdo1_rev30 a_rev30 = disc->identity.product_t1.a_rev30; if (a_rev30.vdo_ver >= VDO_VERSION_1_3) { - return max_usb4_speed < a_rev30.ss ? - max_usb4_speed : a_rev30.ss; + return max_usb4_speed < a_rev30.ss ? max_usb4_speed : + a_rev30.ss; } } @@ -1106,24 +1099,25 @@ uint32_t get_enter_usb_msg_payload(int port) enum retimer_active_element active_element = disc->identity.product_t2.a2_rev30.active_elem; eudo.cable_type = active_element == ACTIVE_RETIMER ? - CABLE_TYPE_ACTIVE_RETIMER : - CABLE_TYPE_ACTIVE_REDRIVER; + CABLE_TYPE_ACTIVE_RETIMER : + CABLE_TYPE_ACTIVE_REDRIVER; } else { cable_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - eudo.cable_type = - cable_mode_resp.retimer_type == USB_RETIMER ? - CABLE_TYPE_ACTIVE_RETIMER : - CABLE_TYPE_ACTIVE_REDRIVER; + eudo.cable_type = cable_mode_resp.retimer_type == + USB_RETIMER ? + CABLE_TYPE_ACTIVE_RETIMER : + CABLE_TYPE_ACTIVE_REDRIVER; } } else { cable_mode_resp.raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - eudo.cable_type = - cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE ? - CABLE_TYPE_ACTIVE_REDRIVER : CABLE_TYPE_PASSIVE; + eudo.cable_type = cable_mode_resp.tbt_active_passive == + TBT_CABLE_ACTIVE ? + CABLE_TYPE_ACTIVE_REDRIVER : + CABLE_TYPE_PASSIVE; } switch (disc->identity.product_t1.p_rev20.vbus_cur) { @@ -1179,17 +1173,17 @@ __overridable int svdm_enter_dp_mode(int port, uint32_t mode_caps) return -1; #endif - /* - * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL. - * DisplayPort Alternate mode requires that the SBU lines are used for - * AUX communication. - * However, in Chromebooks SBU signals are repurposed as USB2 signals - * for CCD. This functionality is accomplished by override fets whose - * state is controlled by CCD_MODE_ODL. - * - * This condition helps in debugging unexpected AUX timeout issues by - * indicating the state of the CCD override fets. - */ + /* + * TCPMv2: Enable logging of CCD line state CCD_MODE_ODL. + * DisplayPort Alternate mode requires that the SBU lines are + * used for AUX communication. However, in Chromebooks SBU + * signals are repurposed as USB2 signals for CCD. This + * functionality is accomplished by override fets whose state is + * controlled by CCD_MODE_ODL. + * + * This condition helps in debugging unexpected AUX timeout + * issues by indicating the state of the CCD override fets. + */ #ifdef GPIO_CCD_MODE_ODL if (!gpio_get_level(GPIO_CCD_MODE_ODL)) CPRINTS("WARNING: Tried to EnterMode DP with [CCD on AUX/SBU]"); @@ -1216,8 +1210,8 @@ __overridable int svdm_dp_status(int port, uint32_t *payload) { int opos = pd_alt_mode(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_STATUS | VDO_OPOS(opos)); + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS | VDO_OPOS(opos)); payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ 0, /* HPD level ... not applicable */ 0, /* exit DP? ... no */ @@ -1242,7 +1236,7 @@ mux_state_t svdm_dp_get_mux_mode(int port) if (IS_ENABLED(CONFIG_CMD_MFALLOW)) mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) && - dp_port_mf_allow[port]; + dp_port_mf_allow[port]; else mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); @@ -1267,7 +1261,7 @@ __overridable int svdm_dp_config(int port, uint32_t *payload) if (IS_ENABLED(CONFIG_CMD_MFALLOW)) mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) && - dp_port_mf_allow[port]; + dp_port_mf_allow[port]; else mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); @@ -1276,11 +1270,11 @@ __overridable int svdm_dp_config(int port, uint32_t *payload) CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode); - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -1304,7 +1298,7 @@ __overridable void svdm_dp_post_config(int port) typec_set_sbu(port, true); usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT, - polarity_rm_dts(pd_get_polarity(port))); + polarity_rm_dts(pd_get_polarity(port))); dp_flags[port] |= DP_FLAGS_DP_ON; if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) @@ -1317,8 +1311,8 @@ __overridable void svdm_dp_post_config(int port) svdm_hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ - usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + usb_mux_hpd_update(port, + USB_PD_MUX_HPD_LVL | USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) @@ -1337,8 +1331,7 @@ __overridable int svdm_dp_attention(int port, uint32_t *payload) dp_status[port] = payload[1]; - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -1402,7 +1395,7 @@ __overridable void svdm_exit_dp_mode(int port) svdm_set_hpd_gpio(port, 0); #endif /* CONFIG_USB_PD_DP_HPD_GPIO */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); #ifdef USB_PD_PORT_TCPC_MST if (port == USB_PD_PORT_TCPC_MST) baseboard_mst_enable_control(port, 0); @@ -1526,5 +1519,5 @@ static int command_mfallow(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(mfallow, command_mfallow, "port [true | false]", - "Controls Multifunction choice during DP Altmode."); + "Controls Multifunction choice during DP Altmode."); #endif -- cgit v1.2.1 From a70c4a3dd9ff098a78c682374b4e69a3a73405f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:39 -0600 Subject: test/usb_tcpmv2_td_pd_src_e5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I76477b0295369f38925f255a75af2ad6a756183d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730577 Reviewed-by: Jeremy Bettis --- test/usb_tcpmv2_td_pd_src_e5.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/usb_tcpmv2_td_pd_src_e5.c b/test/usb_tcpmv2_td_pd_src_e5.c index eac1b93e8f..0b6846ec22 100644 --- a/test/usb_tcpmv2_td_pd_src_e5.c +++ b/test/usb_tcpmv2_td_pd_src_e5.c @@ -71,12 +71,12 @@ int test_td_pd_src_e5(void) end_time += 6 * MSEC; while (get_time().val < end_time) { if (mock_tcpci_get_reg(TCPC_REG_TRANSMIT) == - TCPCI_MSG_TX_HARD_RESET) + TCPCI_MSG_TX_HARD_RESET) break; task_wait_event(1 * MSEC); } - TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), - TCPCI_MSG_TX_HARD_RESET, "%d"); + TEST_EQ(mock_tcpci_get_reg(TCPC_REG_TRANSMIT), TCPCI_MSG_TX_HARD_RESET, + "%d"); mock_set_alert(TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_FAILED); mock_tcpci_set_reg(TCPC_REG_TRANSMIT, 0); task_wait_event(1 * MSEC); -- cgit v1.2.1 From 2ddde30423f0179cb18b8c5f3a1054bf7d9b0df9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:39 -0600 Subject: board/gooey/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94c6c23fdca3bfa5dced6660da2ef3a10faa19f8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728424 Reviewed-by: Jeremy Bettis --- board/gooey/board.h | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/board/gooey/board.h b/board/gooey/board.h index 4681fb5dcf..417a5f6313 100644 --- a/board/gooey/board.h +++ b/board/gooey/board.h @@ -26,7 +26,8 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -40,8 +41,8 @@ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DWL /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ @@ -109,26 +110,17 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ ADC_CH_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 7e9b96c50994760f529dffe386487d3c601c623b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:06 -0600 Subject: board/asurada/led_hayato.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2dfb69693d0e015dd65b3be9605bc2aa9e4243fa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727993 Reviewed-by: Jeremy Bettis --- board/asurada/led_hayato.c | 61 ++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/board/asurada/led_hayato.c b/board/asurada/led_hayato.c index 1d3108c47b..4285127f5c 100644 --- a/board/asurada/led_hayato.c +++ b/board/asurada/led_hayato.c @@ -14,31 +14,40 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -78,12 +87,12 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { if (led_id == EC_LED_ID_BATTERY_LED) { brightness_range[EC_LED_COLOR_AMBER] = - MT6360_LED_BRIGHTNESS_MAX; + MT6360_LED_BRIGHTNESS_MAX; brightness_range[EC_LED_COLOR_WHITE] = - MT6360_LED_BRIGHTNESS_MAX; + MT6360_LED_BRIGHTNESS_MAX; } else if (led_id == EC_LED_ID_POWER_LED) { brightness_range[EC_LED_COLOR_WHITE] = - MT6360_LED_BRIGHTNESS_MAX; + MT6360_LED_BRIGHTNESS_MAX; } } -- cgit v1.2.1 From dccd34b93f76c2ae40f2b73d9a69005617268a72 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:13 -0600 Subject: zephyr/shim/chip/mchp/include/flash_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib1f7081beee601807dcfd45b7d07480a42d6db50 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730816 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/include/flash_chip.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/shim/chip/mchp/include/flash_chip.h b/zephyr/shim/chip/mchp/include/flash_chip.h index b3677fb45c..d2b71eea7d 100644 --- a/zephyr/shim/chip/mchp/include/flash_chip.h +++ b/zephyr/shim/chip/mchp/include/flash_chip.h @@ -11,10 +11,10 @@ * Similar to W25X40, both only have one status reg */ #define CONFIG_SPI_FLASH_W25X40 /* Internal SPI flash type. */ -#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ -#define CONFIG_FLASH_ERASE_SIZE 0x1000 -#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE +#define CONFIG_FLASH_WRITE_SIZE 0x1 /* minimum write size */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* one page size for write */ +#define CONFIG_FLASH_ERASE_SIZE 0x1000 +#define CONFIG_FLASH_BANK_SIZE CONFIG_FLASH_ERASE_SIZE /* RO image resides at 4KB offset in protected region * The first 4KB in the protected region starting at offset 0 contains @@ -23,7 +23,7 @@ * RW image is never loaded by the Boot-ROM therefore no TAG or Header * is needed. RW starts at offset 0 in RW storage region. */ -#define CONFIG_RO_STORAGE_OFF 0x1000 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0x1000 +#define CONFIG_RW_STORAGE_OFF 0 #endif /* __CROS_EC_FLASH_CHIP_H */ -- cgit v1.2.1 From 7fe8511843aa7eb96349719ea1ecacaccfb368fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:50 -0600 Subject: board/galtic/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39fec967e0daff7203c8e53d3c8e12b3501150da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728386 Reviewed-by: Jeremy Bettis --- board/galtic/cbi_ssfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/galtic/cbi_ssfc.h b/board/galtic/cbi_ssfc.h index 686dcb4d47..bcfddbca72 100644 --- a/board/galtic/cbi_ssfc.h +++ b/board/galtic/cbi_ssfc.h @@ -37,7 +37,7 @@ enum ec_ssfc_lid_sensor { * Mux Redriver (Bit 6) */ enum ec_ssfc_mux_redriver { - SSFC_MUX_DEFAULT = 0, /* IT5205 + TUSB544 */ + SSFC_MUX_DEFAULT = 0, /* IT5205 + TUSB544 */ SSFC_MUX_PS8743 = 1, }; -- cgit v1.2.1 From c1f7d5d6a28d23859b8911390712d332ba4fd126 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:46:19 -0600 Subject: driver/accel_lis2dw12.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4e70d02bdcbe0bcf166ef7d7dea1aae894fb5cfe Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729890 Reviewed-by: Jeremy Bettis --- driver/accel_lis2dw12.h | 167 ++++++++++++++++++++++++------------------------ 1 file changed, 82 insertions(+), 85 deletions(-) diff --git a/driver/accel_lis2dw12.h b/driver/accel_lis2dw12.h index c0f32427ff..e27d712a24 100644 --- a/driver/accel_lis2dw12.h +++ b/driver/accel_lis2dw12.h @@ -15,46 +15,46 @@ #include "stm_mems_common.h" /* Who am I. */ -#define LIS2DW12_WHO_AM_I_REG 0x0f -#define LIS2DW12_WHO_AM_I 0x44 +#define LIS2DW12_WHO_AM_I_REG 0x0f +#define LIS2DW12_WHO_AM_I 0x44 /* Registers sensor. */ -#define LIS2DW12_CTRL1_ADDR 0x20 -#define LIS2DW12_CTRL2_ADDR 0x21 -#define LIS2DW12_CTRL3_ADDR 0x22 +#define LIS2DW12_CTRL1_ADDR 0x20 +#define LIS2DW12_CTRL2_ADDR 0x21 +#define LIS2DW12_CTRL3_ADDR 0x22 -#define LIS2DW12_CTRL4_ADDR 0x23 +#define LIS2DW12_CTRL4_ADDR 0x23 /* CTRL4 bits. */ -#define LIS2DW12_INT1_FTH 0x02 -#define LIS2DW12_INT1_D_TAP 0x08 -#define LIS2DW12_INT1_S_TAP 0x40 +#define LIS2DW12_INT1_FTH 0x02 +#define LIS2DW12_INT1_D_TAP 0x08 +#define LIS2DW12_INT1_S_TAP 0x40 -#define LIS2DW12_CTRL5_ADDR 0x24 +#define LIS2DW12_CTRL5_ADDR 0x24 /* CTRL5 bits. */ -#define LIS2DW12_INT2_FTH 0x02 +#define LIS2DW12_INT2_FTH 0x02 -#define LIS2DW12_CTRL6_ADDR 0x25 -#define LIS2DW12_STATUS_REG 0x27 +#define LIS2DW12_CTRL6_ADDR 0x25 +#define LIS2DW12_STATUS_REG 0x27 /* STATUS bits. */ -#define LIS2DW12_STS_DRDY_UP 0x01 -#define LIS2DW12_SINGLE_TAP_UP 0x08 -#define LIS2DW12_DOUBLE_TAP_UP 0x10 -#define LIS2DW12_FIFO_THS_UP 0x80 +#define LIS2DW12_STS_DRDY_UP 0x01 +#define LIS2DW12_SINGLE_TAP_UP 0x08 +#define LIS2DW12_DOUBLE_TAP_UP 0x10 +#define LIS2DW12_FIFO_THS_UP 0x80 -#define LIS2DW12_OUT_X_L_ADDR 0x28 -#define LIS2DW12_OUT_X_H_ADDR 0x29 -#define LIS2DW12_OUT_Y_L_ADDR 0x2a -#define LIS2DW12_OUT_Y_H_ADDR 0x2b -#define LIS2DW12_OUT_Z_L_ADDR 0x2c -#define LIS2DW12_OUT_Z_H_ADDR 0x2d +#define LIS2DW12_OUT_X_L_ADDR 0x28 +#define LIS2DW12_OUT_X_H_ADDR 0x29 +#define LIS2DW12_OUT_Y_L_ADDR 0x2a +#define LIS2DW12_OUT_Y_H_ADDR 0x2b +#define LIS2DW12_OUT_Z_L_ADDR 0x2c +#define LIS2DW12_OUT_Z_H_ADDR 0x2d -#define LIS2DW12_FIFO_CTRL_ADDR 0x2e +#define LIS2DW12_FIFO_CTRL_ADDR 0x2e /* FIFO_CTRL bits. */ -#define LIS2DW12_FIFO_MODE_MASK 0xe0 +#define LIS2DW12_FIFO_MODE_MASK 0xe0 /* List of supported FIFO mode. */ enum lis2dw12_fmode { @@ -63,37 +63,37 @@ enum lis2dw12_fmode { LIS2DW12_FIFO_CONT_MODE = 6 }; -#define LIS2DW12_FIFO_THRESHOLD_MASK 0x1f +#define LIS2DW12_FIFO_THRESHOLD_MASK 0x1f -#define LIS2DW12_FIFO_SAMPLES_ADDR 0x2f -#define LIS2DW12_TAP_THS_X_ADDR 0x30 -#define LIS2DW12_TAP_THS_Y_ADDR 0x31 -#define LIS2DW12_TAP_THS_Z_ADDR 0x32 -#define LIS2DW12_INT_DUR_ADDR 0x33 +#define LIS2DW12_FIFO_SAMPLES_ADDR 0x2f +#define LIS2DW12_TAP_THS_X_ADDR 0x30 +#define LIS2DW12_TAP_THS_Y_ADDR 0x31 +#define LIS2DW12_TAP_THS_Z_ADDR 0x32 +#define LIS2DW12_INT_DUR_ADDR 0x33 -#define LIS2DW12_WAKE_UP_THS_ADDR 0x34 +#define LIS2DW12_WAKE_UP_THS_ADDR 0x34 /* TAP bits. */ -#define LIS2DW12_SINGLE_DOUBLE_TAP 0x80 +#define LIS2DW12_SINGLE_DOUBLE_TAP 0x80 /* FIFO_SAMPLES bits. */ -#define LIS2DW12_FIFO_DIFF_MASK 0x3f -#define LIS2DW12_FIFO_OVR_MASK 0x40 -#define LIS2DW12_FIFO_FTH_MASK 0x80 +#define LIS2DW12_FIFO_DIFF_MASK 0x3f +#define LIS2DW12_FIFO_OVR_MASK 0x40 +#define LIS2DW12_FIFO_FTH_MASK 0x80 -#define LIS2DW12_ABS_INT_CFG_ADDR 0x3f +#define LIS2DW12_ABS_INT_CFG_ADDR 0x3f /* INT Configuration bits. */ -#define LIS2DW12_DRDY_PULSED 0x80 -#define LIS2DW12_INT2_ON_INT1 0x40 -#define LIS2DW12_INT_ENABLE 0x20 +#define LIS2DW12_DRDY_PULSED 0x80 +#define LIS2DW12_INT2_ON_INT1 0x40 +#define LIS2DW12_INT_ENABLE 0x20 /* Alias Registers/Masks. */ -#define LIS2DW12_ACC_ODR_ADDR LIS2DW12_CTRL1_ADDR -#define LIS2DW12_ACC_ODR_MASK 0xf0 +#define LIS2DW12_ACC_ODR_ADDR LIS2DW12_CTRL1_ADDR +#define LIS2DW12_ACC_ODR_MASK 0xf0 -#define LIS2DW12_ACC_MODE_ADDR LIS2DW12_CTRL1_ADDR -#define LIS2DW12_ACC_MODE_MASK 0x0c +#define LIS2DW12_ACC_MODE_ADDR LIS2DW12_CTRL1_ADDR +#define LIS2DW12_ACC_MODE_MASK 0x0c /* Power mode selection. */ enum lis2sw12_mode { @@ -103,8 +103,8 @@ enum lis2sw12_mode { LIS2DW12_LOW_POWER_LIST_NUM }; -#define LIS2DW12_ACC_LPMODE_ADDR LIS2DW12_CTRL1_ADDR -#define LIS2DW12_ACC_LPMODE_MASK 0x03 +#define LIS2DW12_ACC_LPMODE_ADDR LIS2DW12_CTRL1_ADDR +#define LIS2DW12_ACC_LPMODE_MASK 0x03 /* * Low power mode selection. @@ -119,39 +119,39 @@ enum lis2sw12_lpmode { LIS2DW12_LOW_POWER_MODE_LIST_NUM }; -#define LIS2DW12_BDU_ADDR LIS2DW12_CTRL2_ADDR -#define LIS2DW12_BDU_MASK 0x08 +#define LIS2DW12_BDU_ADDR LIS2DW12_CTRL2_ADDR +#define LIS2DW12_BDU_MASK 0x08 -#define LIS2DW12_SOFT_RESET_ADDR LIS2DW12_CTRL2_ADDR -#define LIS2DW12_SOFT_RESET_MASK 0x40 +#define LIS2DW12_SOFT_RESET_ADDR LIS2DW12_CTRL2_ADDR +#define LIS2DW12_SOFT_RESET_MASK 0x40 -#define LIS2DW12_BOOT_ADDR LIS2DW12_CTRL2_ADDR -#define LIS2DW12_BOOT_MASK 0x80 +#define LIS2DW12_BOOT_ADDR LIS2DW12_CTRL2_ADDR +#define LIS2DW12_BOOT_MASK 0x80 -#define LIS2DW12_LIR_ADDR LIS2DW12_CTRL3_ADDR -#define LIS2DW12_LIR_MASK 0x10 +#define LIS2DW12_LIR_ADDR LIS2DW12_CTRL3_ADDR +#define LIS2DW12_LIR_MASK 0x10 -#define LIS2DW12_H_ACTIVE_ADDR LIS2DW12_CTRL3_ADDR -#define LIS2DW12_H_ACTIVE_MASK 0x08 +#define LIS2DW12_H_ACTIVE_ADDR LIS2DW12_CTRL3_ADDR +#define LIS2DW12_H_ACTIVE_MASK 0x08 -#define LIS2DW12_INT1_FTH_ADDR LIS2DW12_CTRL4_ADDR -#define LIS2DW12_INT1_FTH_MASK LIS2DW12_INT1_FTH +#define LIS2DW12_INT1_FTH_ADDR LIS2DW12_CTRL4_ADDR +#define LIS2DW12_INT1_FTH_MASK LIS2DW12_INT1_FTH -#define LIS2DW12_INT1_TAP_ADDR LIS2DW12_CTRL4_ADDR -#define LIS2DW12_INT1_DTAP_MASK 0x08 -#define LIS2DW12_INT1_STAP_MASK 0x40 +#define LIS2DW12_INT1_TAP_ADDR LIS2DW12_CTRL4_ADDR +#define LIS2DW12_INT1_DTAP_MASK 0x08 +#define LIS2DW12_INT1_STAP_MASK 0x40 -#define LIS2DW12_INT1_D_TAP_EN LIS2DW12_INT1_DTAP_MASK +#define LIS2DW12_INT1_D_TAP_EN LIS2DW12_INT1_DTAP_MASK -#define LIS2DW12_STATUS_TAP LIS2DW12_STS_DRDY_UP -#define LIS2DW12_SINGLE_TAP LIS2DW12_SINGLE_TAP_UP -#define LIS2DW12_DOUBLE_TAP LIS2DW12_DOUBLE_TAP_UP +#define LIS2DW12_STATUS_TAP LIS2DW12_STS_DRDY_UP +#define LIS2DW12_SINGLE_TAP LIS2DW12_SINGLE_TAP_UP +#define LIS2DW12_DOUBLE_TAP LIS2DW12_DOUBLE_TAP_UP -#define LIS2DW12_INT2_ON_INT1_ADDR LIS2DW12_ABS_INT_CFG_ADDR -#define LIS2DW12_INT2_ON_INT1_MASK LIS2DW12_INT2_ON_INT1 +#define LIS2DW12_INT2_ON_INT1_ADDR LIS2DW12_ABS_INT_CFG_ADDR +#define LIS2DW12_INT2_ON_INT1_MASK LIS2DW12_INT2_ON_INT1 -#define LIS2DW12_DRDY_PULSED_ADDR LIS2DW12_ABS_INT_CFG_ADDR -#define LIS2DW12_DRDY_PULSED_MASK LIS2DW12_DRDY_PULSED +#define LIS2DW12_DRDY_PULSED_ADDR LIS2DW12_ABS_INT_CFG_ADDR +#define LIS2DW12_DRDY_PULSED_MASK LIS2DW12_DRDY_PULSED /* Acc data rate for HR mode. */ enum lis2dw12_odr { @@ -168,8 +168,8 @@ enum lis2dw12_odr { }; /* Full scale range registers. */ -#define LIS2DW12_FS_ADDR LIS2DW12_CTRL6_ADDR -#define LIS2DW12_FS_MASK 0x30 +#define LIS2DW12_FS_ADDR LIS2DW12_CTRL6_ADDR +#define LIS2DW12_FS_MASK 0x30 /* Acc FS value. */ enum lis2dw12_fs { @@ -180,42 +180,39 @@ enum lis2dw12_fs { LIS2DW12_FS_LIST_NUM }; -#define LIS2DW12_ACCEL_FS_MAX_VAL 16 +#define LIS2DW12_ACCEL_FS_MAX_VAL 16 /* Acc Gain value. */ -#define LIS2DW12_FS_2G_GAIN 3904 -#define LIS2DW12_FS_4G_GAIN (LIS2DW12_FS_2G_GAIN << 1) -#define LIS2DW12_FS_8G_GAIN (LIS2DW12_FS_2G_GAIN << 2) -#define LIS2DW12_FS_16G_GAIN (LIS2DW12_FS_2G_GAIN << 3) +#define LIS2DW12_FS_2G_GAIN 3904 +#define LIS2DW12_FS_4G_GAIN (LIS2DW12_FS_2G_GAIN << 1) +#define LIS2DW12_FS_8G_GAIN (LIS2DW12_FS_2G_GAIN << 2) +#define LIS2DW12_FS_16G_GAIN (LIS2DW12_FS_2G_GAIN << 3) /* FS Full Scale value from Gain. */ #define LIS2DW12_GAIN_FS(_gain) \ (2 << (31 - __builtin_clz(_gain / LIS2DW12_FS_2G_GAIN))) /* Gain value from selected Full Scale. */ -#define LIS2DW12_FS_GAIN(_fs) \ - (LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs))) +#define LIS2DW12_FS_GAIN(_fs) (LIS2DW12_FS_2G_GAIN << (30 - __builtin_clz(_fs))) /* Reg value from Full Scale. */ -#define LIS2DW12_FS_REG(_fs) \ - (30 - __builtin_clz(_fs)) +#define LIS2DW12_FS_REG(_fs) (30 - __builtin_clz(_fs)) /* Normalized FS value from Full Scale. */ -#define LIS2DW12_NORMALIZE_FS(_fs) \ - (1 << (30 - __builtin_clz(_fs))) +#define LIS2DW12_NORMALIZE_FS(_fs) (1 << (30 - __builtin_clz(_fs))) /* * Sensor resolution in number of bits. * Sensor driver support 14 bits resolution. * TODO: Support all "LP Power Mode" (res. 12/14 bits). */ -#define LIS2DW12_RESOLUTION 14 +#define LIS2DW12_RESOLUTION 14 /** Maximum possible sample */ -#define LIS2DW12_SAMPLE_MAX ((1<<(LIS2DW12_RESOLUTION-1))-1) +#define LIS2DW12_SAMPLE_MAX ((1 << (LIS2DW12_RESOLUTION - 1)) - 1) /** Smallest possible sample */ -#define LIS2DW12_SAMPLE_MIN (-(1<<(LIS2DW12_RESOLUTION-1))) +#define LIS2DW12_SAMPLE_MIN (-(1 << (LIS2DW12_RESOLUTION - 1))) #ifdef CONFIG_ZTEST int lis2dw12_set_power_mode(const struct motion_sensor_t *s, -- cgit v1.2.1 From 0e11f27fbafc9cdc36f0bfda52f0685e509102c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:15 -0600 Subject: zephyr/shim/chip/mchp/include/system_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I25238ddf21bb571c520d6fb8afd470f6d1958007 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730817 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/mchp/include/system_chip.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h index a62ea4a525..5d60fff874 100644 --- a/zephyr/shim/chip/mchp/include/system_chip.h +++ b/zephyr/shim/chip/mchp/include/system_chip.h @@ -6,18 +6,18 @@ #ifndef __CROS_EC_SYSTEM_CHIP_H_ #define __CROS_EC_SYSTEM_CHIP_H_ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) #undef IS_BIT_SET -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) /******************************************************************************/ /* Optional M4 Registers */ -#define CPU_MPU_CTRL REG32(0xE000ED94) -#define CPU_MPU_RNR REG32(0xE000ED98) -#define CPU_MPU_RBAR REG32(0xE000ED9C) -#define CPU_MPU_RASR REG32(0xE000EDA0) +#define CPU_MPU_CTRL REG32(0xE000ED94) +#define CPU_MPU_RNR REG32(0xE000ED98) +#define CPU_MPU_RBAR REG32(0xE000ED9C) +#define CPU_MPU_RASR REG32(0xE000EDA0) void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr, uint32_t size, uint32_t exeAddr); -- cgit v1.2.1 From 6df9093e8c3bfaf3a06bdd053d582b3d420c8a63 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:39 -0600 Subject: zephyr/projects/skyrim/power_signals_guybrush.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7c57a745b010d32124cf63bab2a0c806978d8f3b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730803 Reviewed-by: Jeremy Bettis --- zephyr/projects/skyrim/power_signals_guybrush.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c index 11110886f2..ba9eb1a92f 100644 --- a/zephyr/projects/skyrim/power_signals_guybrush.c +++ b/zephyr/projects/skyrim/power_signals_guybrush.c @@ -20,7 +20,7 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* Power Signal Input List */ /* TODO: b/218904113: Convert to using Zephyr GPIOs */ @@ -76,13 +76,13 @@ void board_pwrbtn_to_pch(int level) start = get_time(); do { usleep(200); - if (gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ec_soc_rsmrst_l))) break; } while (time_since32(start) < timeout_rsmrst_rise_us); if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) ccprints("Error pwrbtn: RSMRST_L still low"); msleep(16); @@ -92,20 +92,22 @@ void board_pwrbtn_to_pch(int level) void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) { - /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr4x_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od))); + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_pg_lpddr4x_s3_od)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_pg_groupc_s0_od))); } void baseboard_en_pwr_s0(enum gpio_signal signal) { - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); /* Now chain off to the normal power signal interrupt handler. */ power_signal_interrupt(signal); -- cgit v1.2.1 From 5afc10f809acd06c70d79182275c8396cb31459f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:11 -0600 Subject: board/taniks/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52e437b858565ab2299c3d4b54f32da8e2447943 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729015 Reviewed-by: Jeremy Bettis --- board/taniks/sensors.c | 66 +++++++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 39 deletions(-) diff --git a/board/taniks/sensors.c b/board/taniks/sensors.c index e0fd53eb01..840e0e186b 100644 --- a/board/taniks/sensors.c +++ b/board/taniks/sensors.c @@ -22,8 +22,8 @@ #include "tablet_mode.h" #if 1 -#define CPRINTS(format, args...) ccprints(format, ## args) -#define CPRINTF(format, args...) ccprintf(format, ## args) +#define CPRINTS(format, args...) ccprints(format, ##args) +#define CPRINTF(format, args...) ccprintf(format, ##args) #else #define CPRINTS(format, args...) #define CPRINTF(format, args...) @@ -119,17 +119,13 @@ static struct lsm6dso_data lsm6dso_data; static struct lsm6dsm_data lsm6dsm_data = LSM6DSM_DATA; /* Matrix to rotate lid and base sensor into standard reference frame */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t bma422_lid_accel = { .name = "Lid Accel - BMA", @@ -287,7 +283,6 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); #endif - static void board_detect_motionsensor(void) { int ret; @@ -304,8 +299,8 @@ static void board_detect_motionsensor(void) return; /* Check lid accel chip */ - ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, - LIS2DW12_WHO_AM_I_REG, &val); + ret = i2c_read8(I2C_PORT_SENSOR, LIS2DW12_ADDR1, LIS2DW12_WHO_AM_I_REG, + &val); if (ret == 0 && val == LIS2DW12_WHO_AM_I) { CPRINTS("LID_ACCEL is LIS2DW12"); return; @@ -332,7 +327,7 @@ static void board_detect_motionsensor(void) CPRINTS("No LID_ACCEL are detected"); } DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_detect_motionsensor, - HOOK_PRIO_DEFAULT); + HOOK_PRIO_DEFAULT); static void baseboard_sensors_init(void) { @@ -344,27 +339,20 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "CHARGER", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, - [TEMP_SENSOR_4_CPUCHOKE] = { - .name = "CPU CHOKE", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_4_CPUCHOKE - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_3_CHARGER] = { .name = "CHARGER", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, + [TEMP_SENSOR_4_CPUCHOKE] = { .name = "CPU CHOKE", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_4_CPUCHOKE }, }; - BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* @@ -377,8 +365,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ @@ -407,8 +395,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(100), \ -- cgit v1.2.1 From 05b310dda90e1870c18926b2fb7e75adf7193a47 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:31 -0600 Subject: chip/ish/heci_client.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia1e60b0c26c7bdf35e9dfcbe0ba206deb019ebdc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729178 Reviewed-by: Jeremy Bettis --- chip/ish/heci_client.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/chip/ish/heci_client.h b/chip/ish/heci_client.h index 9dca4bff90..97fbfb319f 100644 --- a/chip/ish/heci_client.h +++ b/chip/ish/heci_client.h @@ -11,21 +11,21 @@ #include "hooks.h" -#define HECI_MAX_NUM_OF_CLIENTS 2 +#define HECI_MAX_NUM_OF_CLIENTS 2 -#define HECI_MAX_MSG_SIZE 4960 -#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4) -#define HECI_MAX_MSGS 3 +#define HECI_MAX_MSG_SIZE 4960 +#define HECI_IPC_PAYLOAD_SIZE (IPC_MAX_PAYLOAD_SIZE - 4) +#define HECI_MAX_MSGS 3 enum HECI_ERR { - HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0, - HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1, - HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2, + HECI_ERR_TOO_MANY_MSG_ITEMS = EC_ERROR_INTERNAL_FIRST + 0, + HECI_ERR_NO_CRED_FROM_CLIENT_IN_HOST = EC_ERROR_INTERNAL_FIRST + 1, + HECI_ERR_CLIENT_IS_NOT_CONNECTED = EC_ERROR_INTERNAL_FIRST + 2, }; -typedef void * heci_handle_t; +typedef void *heci_handle_t; -#define HECI_INVALID_HANDLE NULL +#define HECI_INVALID_HANDLE NULL struct heci_guid { uint32_t data1; @@ -57,8 +57,8 @@ struct heci_client { uint32_t max_msg_size; uint8_t protocol_ver; uint8_t max_n_of_connections; - uint8_t dma_header_length :7; - uint8_t dma_enabled :1; + uint8_t dma_header_length : 7; + uint8_t dma_enabled : 1; const struct heci_client_callbacks *cbs; }; @@ -91,7 +91,7 @@ void *heci_get_client_data(const heci_handle_t handle); int heci_send_msg(const heci_handle_t handle, uint8_t *buf, const size_t buf_size); int heci_send_msg_timestamp(const heci_handle_t handle, uint8_t *buf, - const size_t buf_size, uint32_t *timestamp); + const size_t buf_size, uint32_t *timestamp); /* * send client msgs(using list of buffer&size). * heci_msg_item with size == 0 is not acceptable. @@ -102,11 +102,11 @@ int heci_send_msgs(const heci_handle_t handle, int heci_send_fixed_client_msg(const uint8_t fw_addr, uint8_t *buf, const size_t buf_size); -#define HECI_CLIENT_ENTRY(heci_client) \ - void _heci_entry_##heci_client(void) \ - { \ +#define HECI_CLIENT_ENTRY(heci_client) \ + void _heci_entry_##heci_client(void) \ + { \ heci_register_client(&(heci_client)); \ - } \ + } \ DECLARE_HOOK(HOOK_INIT, _heci_entry_##heci_client, HOOK_PRIO_LAST - 1) #endif /* __HECI_CLIENT_H */ -- cgit v1.2.1 From e3df97358a251c8f4516b9a56ae33f31a2b0afc8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:27 -0600 Subject: driver/tcpm/anx7688.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I280d845e33494866093c82cd4f8f5d9c95244ad4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730075 Reviewed-by: Jeremy Bettis --- driver/tcpm/anx7688.c | 56 +++++++++++++++++++++++++-------------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/driver/tcpm/anx7688.c b/driver/tcpm/anx7688.c index 5e37352bc5..4ee87fdaa4 100644 --- a/driver/tcpm/anx7688.c +++ b/driver/tcpm/anx7688.c @@ -12,24 +12,24 @@ #include "usb_mux.h" #if defined(CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE) || \ - defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ + defined(CONFIG_USB_PD_TCPC_LOW_POWER) || \ defined(CONFIG_USB_PD_DISCHARGE_TCPC) #error "Unsupported config options of anx7688 PD driver" #endif -#define ANX7688_VENDOR_ALERT BIT(15) +#define ANX7688_VENDOR_ALERT BIT(15) -#define ANX7688_REG_STATUS 0x82 +#define ANX7688_REG_STATUS 0x82 #define ANX7688_REG_STATUS_LINK BIT(0) -#define ANX7688_REG_HPD 0x83 -#define ANX7688_REG_HPD_HIGH BIT(0) -#define ANX7688_REG_HPD_IRQ BIT(1) -#define ANX7688_REG_HPD_ENABLE BIT(2) +#define ANX7688_REG_HPD 0x83 +#define ANX7688_REG_HPD_HIGH BIT(0) +#define ANX7688_REG_HPD_IRQ BIT(1) +#define ANX7688_REG_HPD_ENABLE BIT(2) -#define ANX7688_USBC_ADDR_FLAGS 0x28 -#define ANX7688_REG_RAMCTRL 0xe7 -#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) +#define ANX7688_USBC_ADDR_FLAGS 0x28 +#define ANX7688_REG_RAMCTRL 0xe7 +#define ANX7688_REG_RAMCTRL_BOOT_DONE BIT(6) static int anx7688_init(int port) { @@ -85,9 +85,9 @@ static void anx7688_update_hpd_enable(int port) !(status & ANX7688_REG_STATUS_LINK)) { reg &= ~ANX7688_REG_HPD_IRQ; tcpc_write(port, ANX7688_REG_HPD, - (status & ANX7688_REG_STATUS_LINK) - ? reg | ANX7688_REG_HPD_ENABLE - : reg & ~ANX7688_REG_HPD_ENABLE); + (status & ANX7688_REG_STATUS_LINK) ? + reg | ANX7688_REG_HPD_ENABLE : + reg & ~ANX7688_REG_HPD_ENABLE); } } @@ -195,25 +195,25 @@ static bool anx7688_tcpm_check_vbus_level(int port, enum vbus_level level) /* ANX7688 is a TCPCI compatible port controller */ const struct tcpm_drv anx7688_tcpm_drv = { - .init = &anx7688_init, - .release = &anx7688_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &anx7688_init, + .release = &anx7688_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &anx7688_tcpm_check_vbus_level, + .check_vbus_level = &anx7688_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &anx7688_tcpc_alert, - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &anx7688_tcpc_alert, + .set_bist_test_mode = &tcpci_set_bist_test_mode, }; #ifdef CONFIG_USB_PD_TCPM_MUX -- cgit v1.2.1 From b4df1d712997cc960442111e7ea1998a6147a72c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:46 -0600 Subject: common/temp_sensor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I181de4933631359a713d76a7661b4dfb5309f471 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729737 Reviewed-by: Jeremy Bettis --- common/temp_sensor.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/common/temp_sensor.c b/common/temp_sensor.c index 66ba5298dc..3b5fca780b 100644 --- a/common/temp_sensor.c +++ b/common/temp_sensor.c @@ -44,8 +44,7 @@ static void update_mapped_memory(void) */ if (i == EC_TEMP_SENSOR_ENTRIES) mptr = host_get_memmap(EC_MEMMAP_TEMP_SENSOR_B); - else if (i >= EC_TEMP_SENSOR_ENTRIES + - EC_TEMP_SENSOR_B_ENTRIES) + else if (i >= EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES) break; switch (temp_sensor_read(i, &t)) { @@ -147,8 +146,7 @@ static int command_temps(int argc, char **argv) { return print_temps(); } -DECLARE_CONSOLE_COMMAND(temps, command_temps, - NULL, +DECLARE_CONSOLE_COMMAND(temps, command_temps, NULL, "Print temp sensors and fan speed"); #endif @@ -172,6 +170,5 @@ temp_sensor_command_get_info(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO, - temp_sensor_command_get_info, +DECLARE_HOST_COMMAND(EC_CMD_TEMP_SENSOR_GET_INFO, temp_sensor_command_get_info, EC_VER_MASK(0)); -- cgit v1.2.1 From 364257994cd98daab2732db7952c335cbf9883ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:30 -0600 Subject: board/chronicler/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4c8787c2055252fb90ee3e655a69e2fdb8d39272 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728147 Reviewed-by: Jeremy Bettis --- board/chronicler/board.h | 91 ++++++++++++++++++++++-------------------------- 1 file changed, 42 insertions(+), 49 deletions(-) diff --git a/board/chronicler/board.h b/board/chronicler/board.h index 1f6fb0f287..9fe197b87c 100644 --- a/board/chronicler/board.h +++ b/board/chronicler/board.h @@ -37,27 +37,27 @@ #undef CONFIG_ACCEL_FIFO_SIZE /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ -#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ -#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ +#define CONFIG_USBC_PPC_SN5S330 /* USBC port C0 */ +#define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ #define CONFIG_USB_PD_FRS_PPC #undef CONFIG_USB_PD_TCPC_RUNTIME_CONFIG #undef CONFIG_USB_PD_TCPM_TUSB422 @@ -72,8 +72,8 @@ #define CONFIG_FAN_RPM_CUSTOM /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_PROFILE_OVERRIDE /* Retimer */ @@ -89,44 +89,44 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER #define CONFIG_DEBUG_ASSERT_BRIEF /* Disable volume button command in EC console */ -#undef CONFIG_CMD_BUTTON +#undef CONFIG_CMD_BUTTON /* Disable volume button in ectool */ #undef CONFIG_HOSTCMD_BUTTON @@ -141,16 +141,9 @@ #include "usbc_config.h" -enum battery_type { - BATTERY_NVT_CP813907, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_NVT_CP813907, BATTERY_TYPE_COUNT }; -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_KBLIGHT, PWM_CH_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From ffc81b42b47620e7a9b908cc6273c6f86d5379df Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:05 -0600 Subject: board/madoo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie3af3abb05255de1816fe4c2f2eee1f626b1c5a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728638 Reviewed-by: Jeremy Bettis --- board/madoo/board.h | 49 ++++++++++++++++++++----------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/board/madoo/board.h b/board/madoo/board.h index 1a0e37ac90..701f168174 100644 --- a/board/madoo/board.h +++ b/board/madoo/board.h @@ -15,9 +15,10 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP /* EC console commands */ #define CONFIG_CMD_TCPC_DUMP @@ -31,7 +32,7 @@ /* PWM */ #define CONFIG_PWM -#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ /* USB */ #define CONFIG_BC12_DETECT_PI3USB9201 @@ -58,16 +59,16 @@ #define CONFIG_USB_PD_5V_EN_CUSTOM /* I2C configuration */ -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 #define I2C_PORT_SUB_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* TODO(b:147440290): Need to handle multiple charger ICs */ -#define I2C_PORT_CHARGER I2C_PORT_USB_C0 +#define I2C_PORT_CHARGER I2C_PORT_USB_C0 -#define I2C_PORT_ACCEL I2C_PORT_SENSOR +#define I2C_PORT_ACCEL I2C_PORT_SENSOR #define I2C_ADDR_EEPROM_FLAGS 0x50 /* 7b address */ @@ -75,16 +76,15 @@ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO -#define CONFIG_ACCEL_BMA255 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_BMA255 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Lid operates in forced mode, base in FIFO */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) #define CONFIG_ACCEL_FIFO -#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ +#define CONFIG_ACCEL_FIFO_SIZE 256 /* Must be a power of 2 */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) - #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE #define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL @@ -119,25 +119,16 @@ enum chg_id { }; enum adc_channel { - ADC_TEMP_SENSOR_1, /* ADC0 */ - ADC_TEMP_SENSOR_2, /* ADC1 */ - ADC_SUB_ANALOG, /* ADC2 */ - ADC_VSNS_PP3300_A, /* ADC9 */ + ADC_TEMP_SENSOR_1, /* ADC0 */ + ADC_TEMP_SENSOR_2, /* ADC1 */ + ADC_SUB_ANALOG, /* ADC2 */ + ADC_VSNS_PP3300_A, /* ADC9 */ ADC_CH_COUNT }; -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; -enum temp_sensor_id { - TEMP_SENSOR_1, - TEMP_SENSOR_2, - TEMP_SENSOR_COUNT -}; +enum temp_sensor_id { TEMP_SENSOR_1, TEMP_SENSOR_2, TEMP_SENSOR_COUNT }; enum pwm_channel { PWM_CH_KBLIGHT, -- cgit v1.2.1 From cd611de7d7907f14b74400f70d7d9774d97c5e14 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Fri, 1 Jul 2022 11:14:40 -0600 Subject: lazor: Disable some board-specific debug messages to free flash space Lazor is tight on flash space, and causing occasional CQ failures. Disable some board-specific debug messages to open up some more flash space. BUG=b:237748265 BRANCH=none TEST=RO: 56 bytes free -> 568 bytes free RW: 88 bytes free -> 600 bytes free Change-Id: If031d49125c3296b6cc3e41302a4266beb2f192c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3738988 Reviewed-by: Denis Brockus Reviewed-by: Jeremy Bettis --- board/lazor/board.c | 5 +++-- board/lazor/usbc_config.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/board/lazor/board.c b/board/lazor/board.c index e25b83d7db..8897ff8bd2 100644 --- a/board/lazor/board.c +++ b/board/lazor/board.c @@ -33,8 +33,9 @@ #include "usbc_config.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +/* Disable debug messages to free flash space */ +#define CPRINTS(format, args...) +#define CPRINTF(format, args...) #include "gpio_list.h" diff --git a/board/lazor/usbc_config.c b/board/lazor/usbc_config.c index fdf68b44de..a9390db9bb 100644 --- a/board/lazor/usbc_config.c +++ b/board/lazor/usbc_config.c @@ -27,8 +27,9 @@ #include "usbc_ocp.h" #include "usbc_ppc.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) +/* Disable debug messages to free flash space */ +#define CPRINTS(format, args...) +#define CPRINTF(format, args...) const struct charger_config_t chg_chips[] = { { -- cgit v1.2.1 From 98e7eff6e8fbb96e513cc00a9c767af5de6f8c34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:53 -0600 Subject: board/mchpevb1/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If3690150a251993b3b36ec9676112ee9507356fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728670 Reviewed-by: Jeremy Bettis --- board/mchpevb1/battery.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/board/mchpevb1/battery.c b/board/mchpevb1/battery.c index fcc09994bf..03774a1170 100644 --- a/board/mchpevb1/battery.c +++ b/board/mchpevb1/battery.c @@ -14,15 +14,15 @@ #include "util.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define PARAM_CUT_OFF_LOW 0x10 +#define PARAM_CUT_OFF_LOW 0x10 #define PARAM_CUT_OFF_HIGH 0x00 /* Battery info for BQ40Z55 */ static const struct battery_info info = { - .voltage_max = 8700, /* mV */ + .voltage_max = 8700, /* mV */ .voltage_normal = 7600, .voltage_min = 6000, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 46, .charging_min_c = 0, @@ -47,10 +47,10 @@ int board_cut_off_battery(void) buf[2] = PARAM_CUT_OFF_HIGH; i2c_lock(I2C_PORT_BATTERY, 1); - rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - buf, 3, NULL, 0, I2C_XFER_SINGLE); - rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, - buf, 3, NULL, 0, I2C_XFER_SINGLE); + rv = i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3, + NULL, 0, I2C_XFER_SINGLE); + rv |= i2c_xfer_unlocked(I2C_PORT_BATTERY, BATTERY_ADDR_FLAGS, buf, 3, + NULL, 0, I2C_XFER_SINGLE); i2c_lock(I2C_PORT_BATTERY, 0); return rv; @@ -223,8 +223,7 @@ static int command_fastcharge(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, - "[on|off]", +DECLARE_CONSOLE_COMMAND(fastcharge, command_fastcharge, "[on|off]", "Get or set fast charging profile"); -#endif /* CONFIG_CHARGER_PROFILE_OVERRIDE */ +#endif /* CONFIG_CHARGER_PROFILE_OVERRIDE */ -- cgit v1.2.1 From 284eb86aafe241e7322973b346de061ce646b302 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:04 -0600 Subject: chip/stm32/clock-stm32f3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8da571c9e5e151e7cc8bc32d6e1730c2fdf1b4b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729463 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32f3.c | 502 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 501 insertions(+), 1 deletion(-) mode change 120000 => 100644 chip/stm32/clock-stm32f3.c diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c deleted file mode 120000 index be91154e52..0000000000 --- a/chip/stm32/clock-stm32f3.c +++ /dev/null @@ -1 +0,0 @@ -clock-stm32f0.c \ No newline at end of file diff --git a/chip/stm32/clock-stm32f3.c b/chip/stm32/clock-stm32f3.c new file mode 100644 index 0000000000..5a57e289fa --- /dev/null +++ b/chip/stm32/clock-stm32f3.c @@ -0,0 +1,501 @@ +/* Copyright 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Clocks and power management settings */ + +#include "chipset.h" +#include "clock.h" +#include "clock-f.h" +#include "common.h" +#include "console.h" +#include "cpu.h" +#include "hooks.h" +#include "hwtimer.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "timer.h" +#include "uart.h" +#include "util.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_CLOCK, outstr) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) + +/* use 48Mhz USB-synchronized High-speed oscillator */ +#define HSI48_CLOCK 48000000 + +/* use PLL at 38.4MHz as system clock. */ +#define PLL_CLOCK 38400000 + +/* Low power idle statistics */ +#ifdef CONFIG_LOW_POWER_IDLE +static int idle_sleep_cnt; +static int idle_dsleep_cnt; +static uint64_t idle_dsleep_time_us; +static int dsleep_recovery_margin_us = 1000000; + +/* + * minimum delay to enter stop mode + * + * STOP_MODE_LATENCY: max time to wake up from STOP mode with regulator in low + * power mode is 5 us + PLL locking time is 200us. + * + * SET_RTC_MATCH_DELAY: max time to set RTC match alarm. If we set the alarm + * in the past, it will never wake up and cause a watchdog. + * For STM32F3, we are using HSE, which requires additional time to start up. + * Therefore, the latency for STM32F3 is set longer. + * + * RESTORE_HOST_ALARM_LATENCY: max latency between the deferred routine is + * called and the host alarm is actually restored. In practice, the max latency + * is measured as ~600us. 1000us should be conservative enough to guarantee + * we won't miss the host alarm. + */ +#ifdef CHIP_VARIANT_STM32F373 +#define STOP_MODE_LATENCY 500 /* us */ +#elif defined(CHIP_VARIANT_STM32F05X) +#define STOP_MODE_LATENCY 300 /* us */ +#elif (CPU_CLOCK == PLL_CLOCK) +#define STOP_MODE_LATENCY 300 /* us */ +#else +#define STOP_MODE_LATENCY 50 /* us */ +#endif +#define SET_RTC_MATCH_DELAY 200 /* us */ + +#ifdef CONFIG_HOSTCMD_RTC +#define RESTORE_HOST_ALARM_LATENCY 1000 /* us */ +#endif + +#endif /* CONFIG_LOW_POWER_IDLE */ + +/* + * RTC clock frequency (By default connected to LSI clock) + * + * The LSI on any given chip can be between 30 kHz to 60 kHz. + * Without calibration, LSI frequency may be off by as much as 50%. + * + * Set synchronous clock freq to (RTC clock source / 2) to maximize + * subsecond resolution. Set asynchronous clock to 1 Hz. + */ + +#define RTC_PREDIV_A 1 +#ifdef CONFIG_STM32_CLOCK_LSE +#define RTC_FREQ (32768 / (RTC_PREDIV_A + 1)) /* Hz */ +/* GCD(RTC_FREQ, 1000000) */ +#define RTC_GCD 64 +#else /* LSI clock, 40kHz-ish */ +#define RTC_FREQ (40000 / (RTC_PREDIV_A + 1)) /* Hz */ +/* GCD(RTC_FREQ, 1000000) */ +#define RTC_GCD 20000 +#endif +#define RTC_PREDIV_S (RTC_FREQ - 1) + +/* + * There are (1000000 / RTC_FREQ) us per RTC tick, take GCD of both terms + * for conversion calculations to fit in 32 bits. + */ +#define US_GCD (1000000 / RTC_GCD) +#define RTC_FREQ_GCD (RTC_FREQ / RTC_GCD) + +int32_t rtcss_to_us(uint32_t rtcss) +{ + return ((RTC_PREDIV_S - (rtcss & 0x7fff)) * US_GCD) / RTC_FREQ_GCD; +} + +uint32_t us_to_rtcss(int32_t us) +{ + return RTC_PREDIV_S - us * RTC_FREQ_GCD / US_GCD; +} + +void config_hispeed_clock(void) +{ +#ifdef CHIP_FAMILY_STM32F3 + /* Ensure that HSE is ON */ + wait_for_ready(&STM32_RCC_CR, BIT(16), BIT(17)); + + /* + * HSE = 24MHz, no prescalar, no MCO, with PLL *2 => 48MHz SYSCLK + * HCLK = SYSCLK, PCLK = HCLK / 2 = 24MHz + * ADCCLK = PCLK / 6 = 4MHz + * USB uses SYSCLK = 48MHz + */ + STM32_RCC_CFGR = 0x0041a400; + + /* Enable the PLL */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until the PLL is ready */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL */ + STM32_RCC_CFGR |= 0x2; + + /* Wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; +/* F03X and F05X and F070 don't have HSI48 */ +#elif defined(CHIP_VARIANT_STM32F03X) || defined(CHIP_VARIANT_STM32F05X) || \ + defined(CHIP_VARIANT_STM32F070) + /* If PLL is the clock source, PLL has already been set up. */ + if ((STM32_RCC_CFGR & 0xc) == 0x8) + return; + + /* Ensure that HSI is ON */ + wait_for_ready(&STM32_RCC_CR, BIT(0), BIT(1)); + + /* + * HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz + * therefore PCLK = FCLK = SYSCLK = 48MHz + */ + /* Switch the PLL source to HSI/2 */ + STM32_RCC_CFGR &= ~(0x00018000); + + /* + * Specify HSI/2 clock as input clock to PLL and set PLL (*12). + */ + STM32_RCC_CFGR |= 0x00280000; + + /* Enable the PLL. */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until PLL is ready. */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL. */ + STM32_RCC_CFGR |= 0x2; + + /* wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; +#else + /* Ensure that HSI48 is ON */ + wait_for_ready(&STM32_RCC_CR2, BIT(16), BIT(17)); + +#if (CPU_CLOCK == HSI48_CLOCK) + /* + * HSI48 = 48MHz, no prescaler, no MCO, no PLL + * therefore PCLK = FCLK = SYSCLK = 48MHz + * USB uses HSI48 = 48MHz + */ + +#ifdef CONFIG_USB + /* + * Configure and enable Clock Recovery System + * + * Since we are running from the internal RC HSI48 clock, the CSR + * is needed to guarantee an accurate 48MHz clock for USB. + * + * The default values configure the CRS to use the periodic USB SOF + * as the SYNC signal for calibrating the HSI48. + * + */ + + /* Enable Clock Recovery System */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS; + + /* Enable automatic trimming */ + STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN; + + /* Enable oscillator clock for the frequency error counter */ + STM32_CRS_CR |= STM32_CRS_CR_CEN; +#endif + + /* switch SYSCLK to HSI48 */ + STM32_RCC_CFGR = 0x00000003; + + /* wait until the HSI48 is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0xc) + ; + +#elif (CPU_CLOCK == PLL_CLOCK) + /* + * HSI48 = 48MHz, no prescalar, no MCO, with PLL *4/5 => 38.4MHz SYSCLK + * therefore PCLK = FCLK = SYSCLK = 38.4MHz + * USB uses HSI48 = 48MHz + */ + + /* If PLL is the clock source, PLL has already been set up. */ + if ((STM32_RCC_CFGR & 0xc) == 0x8) + return; + + /* + * Specify HSI48 clock as input clock to PLL and set PLL multiplier + * and divider. + */ + STM32_RCC_CFGR = 0x00098000; + STM32_RCC_CFGR2 = 0x4; + + /* Enable the PLL. */ + STM32_RCC_CR |= 0x01000000; + + /* Wait until PLL is ready. */ + while (!(STM32_RCC_CR & 0x02000000)) + ; + + /* Switch SYSCLK to PLL. */ + STM32_RCC_CFGR |= 0x2; + + /* wait until the PLL is the clock source */ + while ((STM32_RCC_CFGR & 0xc) != 0x8) + ; + +#else +#error "CPU_CLOCK must be either 48MHz or 38.4MHz" +#endif +#endif +} + +#ifdef CONFIG_HIBERNATE +void __enter_hibernate(uint32_t seconds, uint32_t microseconds) +{ + struct rtc_time_reg rtc; + + if (seconds || microseconds) + set_rtc_alarm(seconds, microseconds, &rtc, 0); + + /* interrupts off now */ + interrupt_disable(); + +#ifdef CONFIG_HIBERNATE_WAKEUP_PINS + /* enable the wake up pins */ + STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS; +#endif + STM32_PWR_CR |= 0xe; + CPU_SCB_SYSCTRL |= 0x4; + /* go to Standby mode */ + asm("wfi"); + + /* we should never reach that point */ + while (1) + ; +} +#endif + +#ifdef CONFIG_HOSTCMD_RTC +static void restore_host_wake_alarm_deferred(void) +{ + restore_host_wake_alarm(); +} +DECLARE_DEFERRED(restore_host_wake_alarm_deferred); +#endif + +#ifdef CONFIG_LOW_POWER_IDLE + +void clock_refresh_console_in_use(void) +{ +} + +void __idle(void) +{ + timestamp_t t0; + uint32_t rtc_diff; + int next_delay, margin_us; + struct rtc_time_reg rtc0, rtc1; + + while (1) { + interrupt_disable(); + + t0 = get_time(); + next_delay = __hw_clock_event_get() - t0.le.lo; + +#ifdef CONFIG_LOW_POWER_IDLE_LIMITED + if (idle_is_disabled()) + goto en_int; +#endif + + if (DEEP_SLEEP_ALLOWED && +#ifdef CONFIG_HOSTCMD_RTC + /* + * Don't go to deep sleep mode if we might miss the + * wake alarm that the host requested. Note that the + * host alarm always aligns to second. Considering the + * worst case, we have to ensure alarm won't go off + * within RESTORE_HOST_ALARM_LATENCY + 1 second after + * EC exits deep sleep mode. + */ + !is_host_wake_alarm_expired( + (timestamp_t)(next_delay + t0.val + SECOND + + RESTORE_HOST_ALARM_LATENCY)) && +#endif + (next_delay > (STOP_MODE_LATENCY + SET_RTC_MATCH_DELAY))) { + /* Deep-sleep in STOP mode */ + idle_dsleep_cnt++; + + uart_enable_wakeup(1); + + /* Set deep sleep bit */ + CPU_SCB_SYSCTRL |= 0x4; + + set_rtc_alarm(0, next_delay - STOP_MODE_LATENCY, &rtc0, + 0); + asm("wfi"); + + CPU_SCB_SYSCTRL &= ~0x4; + + uart_enable_wakeup(0); + + /* + * By default only HSI 8MHz is enabled here. Re-enable + * high-speed clock if in use. + */ + config_hispeed_clock(); + + /* Fast forward timer according to RTC counter */ + reset_rtc_alarm(&rtc1); + rtc_diff = get_rtc_diff(&rtc0, &rtc1); + t0.val = t0.val + rtc_diff; + force_time(t0); + +#ifdef CONFIG_HOSTCMD_RTC + hook_call_deferred( + &restore_host_wake_alarm_deferred_data, 0); +#endif + /* Record time spent in deep sleep. */ + idle_dsleep_time_us += rtc_diff; + + /* Calculate how close we were to missing deadline */ + margin_us = next_delay - rtc_diff; + if (margin_us < 0) + /* Use CPUTS to save stack space */ + CPUTS("Idle overslept!\n"); + + /* Record the closest to missing a deadline. */ + if (margin_us < dsleep_recovery_margin_us) + dsleep_recovery_margin_us = margin_us; + } else { + idle_sleep_cnt++; + + /* Normal idle : only CPU clock stopped */ + asm("wfi"); + } +#ifdef CONFIG_LOW_POWER_IDLE_LIMITED + en_int: +#endif + interrupt_enable(); + } +} +#endif /* CONFIG_LOW_POWER_IDLE */ + +int clock_get_freq(void) +{ + return CPU_CLOCK; +} + +void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles) +{ + volatile uint32_t unused __attribute__((unused)); + + if (bus == BUS_AHB) { + while (cycles--) + unused = STM32_DMA1_REGS->isr; + } else { /* APB */ + while (cycles--) + unused = STM32_USART_BRR(STM32_USART1_BASE); + } +} + +void clock_enable_module(enum module_id module, int enable) +{ + if (module == MODULE_ADC) { + if (enable) + STM32_RCC_APB2ENR |= STM32_RCC_APB2ENR_ADCEN; + else + STM32_RCC_APB2ENR &= ~STM32_RCC_APB2ENR_ADCEN; + return; + } else if (module == MODULE_USB) { + if (enable) + STM32_RCC_APB1ENR |= STM32_RCC_PB1_USB; + else + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_USB; + } +} + +int clock_is_module_enabled(enum module_id module) +{ + if (module == MODULE_ADC) + return !!(STM32_RCC_APB2ENR & STM32_RCC_APB2ENR_ADCEN); + else if (module == MODULE_USB) + return !!(STM32_RCC_APB1ENR & STM32_RCC_PB1_USB); + return 0; +} + +void rtc_init(void) +{ + rtc_unlock_regs(); + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + while (STM32_RTC_ISR & STM32_RTC_ISR_INITF) + ; + + /* Enable RTC alarm interrupt */ + STM32_RTC_CR |= STM32_RTC_CR_ALRAIE | STM32_RTC_CR_BYPSHAD; + STM32_EXTI_RTSR |= EXTI_RTC_ALR_EVENT; + task_enable_irq(STM32_IRQ_RTC_ALARM); + + rtc_lock_regs(); +} + +#if defined(CONFIG_CMD_RTC) || defined(CONFIG_HOSTCMD_RTC) +void rtc_set(uint32_t sec) +{ + struct rtc_time_reg rtc; + + sec_to_rtc(sec, &rtc); + rtc_unlock_regs(); + + /* Disable alarm */ + STM32_RTC_CR &= ~STM32_RTC_CR_ALRAE; + + /* Enter RTC initialize mode */ + STM32_RTC_ISR |= STM32_RTC_ISR_INIT; + while (!(STM32_RTC_ISR & STM32_RTC_ISR_INITF)) + ; + + /* Set clock prescalars */ + STM32_RTC_PRER = (RTC_PREDIV_A << 16) | RTC_PREDIV_S; + + STM32_RTC_TR = rtc.rtc_tr; + STM32_RTC_DR = rtc.rtc_dr; + /* Start RTC timer */ + STM32_RTC_ISR &= ~STM32_RTC_ISR_INIT; + + rtc_lock_regs(); +} +#endif + +#if defined(CONFIG_LOW_POWER_IDLE) && defined(CONFIG_COMMON_RUNTIME) +#ifdef CONFIG_CMD_IDLE_STATS +/** + * Print low power idle statistics + */ +static int command_idle_stats(int argc, char **argv) +{ + timestamp_t ts = get_time(); + + ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); + ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); + ccprintf("Time spent in deep-sleep: %.6llds\n", + idle_dsleep_time_us); + ccprintf("Total time on: %.6llds\n", ts.val); + ccprintf("Deep-sleep closest to wake deadline: %dus\n", + dsleep_recovery_margin_us); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", + "Print last idle stats"); +#endif /* CONFIG_CMD_IDLE_STATS */ +#endif -- cgit v1.2.1 From 603579741270831b39a56ed32adf9508f2a7877a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:02 -0600 Subject: board/felwinter/charger_isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf4f08375c8884be4818bbe7c4de6790a5af2c2b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728354 Reviewed-by: Jeremy Bettis --- board/felwinter/charger_isl9241.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/board/felwinter/charger_isl9241.c b/board/felwinter/charger_isl9241.c index 8bb38754dd..65d2860e35 100644 --- a/board/felwinter/charger_isl9241.c +++ b/board/felwinter/charger_isl9241.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) /* Charger Chip Configuration */ const struct charger_config_t chg_chips[] = { @@ -85,7 +84,6 @@ __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { charge_ma = (charge_ma * 90) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 598f6737b19b4d1fb8375d6b93fa116bbf9989c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:41 -0600 Subject: include/battery.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8f8909add60978837db0014341495b61307d0575 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730209 Reviewed-by: Jeremy Bettis --- include/battery.h | 72 +++++++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/include/battery.h b/include/battery.h index 9daf1ce981..8a99c9b7e6 100644 --- a/include/battery.h +++ b/include/battery.h @@ -23,32 +23,32 @@ #else /* !CONFIG_ZEPHYR */ /* Stop charge when charging and battery level >= this percentage */ -#define BATTERY_LEVEL_FULL 100 +#define BATTERY_LEVEL_FULL 100 /* Tell host we're charged when battery level >= this percentage */ #ifdef CONFIG_BATTERY_LEVEL_NEAR_FULL -#define BATTERY_LEVEL_NEAR_FULL CONFIG_BATTERY_LEVEL_NEAR_FULL +#define BATTERY_LEVEL_NEAR_FULL CONFIG_BATTERY_LEVEL_NEAR_FULL #else -#define BATTERY_LEVEL_NEAR_FULL 97 +#define BATTERY_LEVEL_NEAR_FULL 97 #endif /* * Send battery-low host event when discharging and battery level <= this level */ -#define BATTERY_LEVEL_LOW 10 +#define BATTERY_LEVEL_LOW 10 /* * Send battery-critical host event when discharging and battery level <= this * level. */ -#define BATTERY_LEVEL_CRITICAL 5 +#define BATTERY_LEVEL_CRITICAL 5 /* * Shut down main processor and/or hibernate EC when discharging and battery * level < this level. Setting this too low makes the battery discharge too * deeply, which isn't good for the battery health. */ -#define BATTERY_LEVEL_SHUTDOWN 3 +#define BATTERY_LEVEL_SHUTDOWN 3 #endif /* CONFIG_ZEPHYR */ @@ -66,7 +66,7 @@ enum battery_index { * Sometimes we have hardware to detect battery present, sometimes we have to * wait until we've been able to talk to the battery. */ -FORWARD_DECLARE_ENUM(battery_present) { +FORWARD_DECLARE_ENUM(battery_present){ BP_NOT_INIT = -1, BP_NO = 0, BP_YES = 1, @@ -97,10 +97,10 @@ struct battery_static_info { * char chemistry[32]; */ /* Max string size in the SB spec is 31. */ - char manufacturer_ext[32]; /* SB_MANUFACTURER_NAME */ - char model_ext[32]; /* SB_DEVICE_NAME */ - char serial_ext[32]; /* SB_SERIAL_NUMBER */ - char type_ext[32]; /* SB_DEVICE_CHEMISTRY */ + char manufacturer_ext[32]; /* SB_MANUFACTURER_NAME */ + char model_ext[32]; /* SB_DEVICE_NAME */ + char serial_ext[32]; /* SB_SERIAL_NUMBER */ + char type_ext[32]; /* SB_DEVICE_CHEMISTRY */ #ifdef CONFIG_BATTERY_VENDOR_PARAM uint8_t vendor_param[32]; #endif @@ -111,18 +111,18 @@ extern struct ec_response_battery_dynamic_info battery_dynamic[]; /* Battery parameters */ struct batt_params { - int temperature; /* Temperature in 0.1 K */ - int state_of_charge; /* State of charge (percent, 0-100) */ - int voltage; /* Battery voltage (mV) */ - int current; /* Battery current (mA); negative=discharging */ - int desired_voltage; /* Charging voltage desired by battery (mV) */ - int desired_current; /* Charging current desired by battery (mA) */ - int remaining_capacity; /* Remaining capacity in mAh */ - int full_capacity; /* Capacity in mAh (might change occasionally) */ - int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */ - int status; /* Battery status */ + int temperature; /* Temperature in 0.1 K */ + int state_of_charge; /* State of charge (percent, 0-100) */ + int voltage; /* Battery voltage (mV) */ + int current; /* Battery current (mA); negative=discharging */ + int desired_voltage; /* Charging voltage desired by battery (mV) */ + int desired_current; /* Charging current desired by battery (mA) */ + int remaining_capacity; /* Remaining capacity in mAh */ + int full_capacity; /* Capacity in mAh (might change occasionally) */ + int display_charge; /* Display charge in 10ths of a % (1000=100.0%) */ + int status; /* Battery status */ enum battery_present is_present; /* Is the battery physically present */ - int flags; /* Flags */ + int flags; /* Flags */ }; /* @@ -138,25 +138,25 @@ int battery_get_avg_voltage(void); /* in mV */ /* Flags for batt_params */ /* Battery wants to be charged */ -#define BATT_FLAG_WANT_CHARGE 0x00000001 +#define BATT_FLAG_WANT_CHARGE 0x00000001 /* Battery is responsive (talking to us via I2C) */ -#define BATT_FLAG_RESPONSIVE 0x00000002 +#define BATT_FLAG_RESPONSIVE 0x00000002 /* Bits to indicate which parameter(s) could not be read */ -#define BATT_FLAG_BAD_TEMPERATURE 0x00000004 -#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008 -#define BATT_FLAG_BAD_VOLTAGE 0x00000010 -#define BATT_FLAG_BAD_CURRENT 0x00000020 -#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040 -#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080 -#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100 -#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200 -#define BATT_FLAG_BAD_STATUS 0x00000400 -#define BATT_FLAG_IMBALANCED_CELL 0x00000800 -#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000 +#define BATT_FLAG_BAD_TEMPERATURE 0x00000004 +#define BATT_FLAG_BAD_STATE_OF_CHARGE 0x00000008 +#define BATT_FLAG_BAD_VOLTAGE 0x00000010 +#define BATT_FLAG_BAD_CURRENT 0x00000020 +#define BATT_FLAG_BAD_DESIRED_VOLTAGE 0x00000040 +#define BATT_FLAG_BAD_DESIRED_CURRENT 0x00000080 +#define BATT_FLAG_BAD_REMAINING_CAPACITY 0x00000100 +#define BATT_FLAG_BAD_FULL_CAPACITY 0x00000200 +#define BATT_FLAG_BAD_STATUS 0x00000400 +#define BATT_FLAG_IMBALANCED_CELL 0x00000800 +#define BATT_FLAG_BAD_AVERAGE_CURRENT 0x00001000 /* All of the above BATT_FLAG_BAD_* bits */ -#define BATT_FLAG_BAD_ANY 0x000017fc +#define BATT_FLAG_BAD_ANY 0x000017fc /* Battery constants */ struct battery_info { -- cgit v1.2.1 From 95f6b262c8ec11798d353f19f0ddfe0cafa8fa04 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:11 -0600 Subject: board/osiris/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iead12406d5706f440f16d517c636c4b9d30f4953 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728805 Reviewed-by: Jeremy Bettis --- board/osiris/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/osiris/usbc_config.h b/board/osiris/usbc_config.h index 3ea16a6d56..3551496f7d 100644 --- a/board/osiris/usbc_config.h +++ b/board/osiris/usbc_config.h @@ -9,14 +9,10 @@ #define __CROS_EC_USBC_CONFIG_H #ifndef CONFIG_ZEPHYR -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 #endif -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From 235ebb5ffc5fa001689b780dd923e5a8a42e195c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:56 -0600 Subject: core/riscv-rv32i/panic.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55c96927d8a45baf39f0cf5ef3e0cfa228bb8d82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729873 Reviewed-by: Jeremy Bettis --- core/riscv-rv32i/panic.c | 94 ++++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/core/riscv-rv32i/panic.c b/core/riscv-rv32i/panic.c index 5860fba072..35e86c9fca 100644 --- a/core/riscv-rv32i/panic.c +++ b/core/riscv-rv32i/panic.c @@ -13,7 +13,7 @@ /** * bit[3-0] @ mcause, general exception type information. */ -static const char * const exc_type[16] = { +static const char *const exc_type[16] = { "Instruction address misaligned", "Instruction access fault", "Illegal instruction", @@ -38,12 +38,12 @@ static const char * const exc_type[16] = { /* General purpose register (s0) for saving software panic reason */ #define SOFT_PANIC_GPR_REASON 11 /* General purpose register (s1) for saving software panic information */ -#define SOFT_PANIC_GPR_INFO 10 +#define SOFT_PANIC_GPR_INFO 10 void software_panic(uint32_t reason, uint32_t info) { - asm volatile ("mv s0, %0" : : "r"(reason) : "s0"); - asm volatile ("mv s1, %0" : : "r"(info) : "s1"); + asm volatile("mv s0, %0" : : "r"(reason) : "s0"); + asm volatile("mv s1, %0" : : "r"(info) : "s1"); if (in_interrupt_context()) asm("j excep_handler"); else @@ -58,7 +58,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) * If it was called earlier (eg. when saving riscv.mepc) calling it * once again won't remove any data */ - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); uint32_t warning_mepc; uint32_t *regs; @@ -85,7 +85,7 @@ void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception) void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) { - struct panic_data * const pdata = panic_get_data(); + struct panic_data *const pdata = panic_get_data(); uint32_t *regs; if (pdata && pdata->struct_version == 2) { @@ -100,34 +100,34 @@ void panic_get_reason(uint32_t *reason, uint32_t *info, uint8_t *exception) #endif /* CONFIG_SOFTWARE_PANIC */ static void print_panic_information(uint32_t *regs, uint32_t mcause, - uint32_t mepc) + uint32_t mepc) { panic_printf("=== EXCEPTION: MCAUSE=%x ===\n", mcause); - panic_printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - panic_printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - panic_printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - panic_printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", - regs[12], regs[13], regs[14], regs[15]); - panic_printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", - regs[16], regs[17], regs[18], regs[19]); - panic_printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", - regs[20], regs[21], regs[22], regs[23]); - panic_printf("A2 %08x A1 %08x A0 %08x TP %08x\n", - regs[24], regs[25], regs[26], regs[27]); - panic_printf("GP %08x RA %08x SP %08x MEPC %08x\n", - regs[28], regs[29], regs[30], mepc); + panic_printf("S11 %08x S10 %08x S9 %08x S8 %08x\n", regs[0], + regs[1], regs[2], regs[3]); + panic_printf("S7 %08x S6 %08x S5 %08x S4 %08x\n", regs[4], + regs[5], regs[6], regs[7]); + panic_printf("S3 %08x S2 %08x S1 %08x S0 %08x\n", regs[8], + regs[9], regs[10], regs[11]); + panic_printf("T6 %08x T5 %08x T4 %08x T3 %08x\n", regs[12], + regs[13], regs[14], regs[15]); + panic_printf("T2 %08x T1 %08x T0 %08x A7 %08x\n", regs[16], + regs[17], regs[18], regs[19]); + panic_printf("A6 %08x A5 %08x A4 %08x A3 %08x\n", regs[20], + regs[21], regs[22], regs[23]); + panic_printf("A2 %08x A1 %08x A0 %08x TP %08x\n", regs[24], + regs[25], regs[26], regs[27]); + panic_printf("GP %08x RA %08x SP %08x MEPC %08x\n", regs[28], + regs[29], regs[30], mepc); #ifdef CONFIG_DEBUG_EXCEPTIONS if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) { #ifdef CONFIG_SOFTWARE_PANIC panic_printf("Software panic reason: %s\n", - panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - - PANIC_SW_BASE)]); + panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - + PANIC_SW_BASE)]); panic_printf("Software panic info: %d\n", - regs[SOFT_PANIC_GPR_INFO]); + regs[SOFT_PANIC_GPR_INFO]); #endif } else { panic_printf("Exception type: %s\n", exc_type[(mcause & 0xf)]); @@ -138,7 +138,7 @@ static void print_panic_information(uint32_t *regs, uint32_t mcause, void report_panic(uint32_t *regs) { uint32_t i, mcause, mepc; - struct panic_data * const pdata = get_panic_data_write(); + struct panic_data *const pdata = get_panic_data_write(); mepc = get_mepc(); mcause = get_mcause(); @@ -171,36 +171,36 @@ void panic_data_print(const struct panic_data *pdata) #ifdef CONFIG_PANIC_CONSOLE_OUTPUT static void ccprint_panic_information(uint32_t *regs, uint32_t mcause, - uint32_t mepc) + uint32_t mepc) { ccprintf("=== EXCEPTION: MCAUSE=%x ===\n", mcause); - ccprintf("S11 %08x S10 %08x S9 %08x S8 %08x\n", - regs[0], regs[1], regs[2], regs[3]); - ccprintf("S7 %08x S6 %08x S5 %08x S4 %08x\n", - regs[4], regs[5], regs[6], regs[7]); - ccprintf("S3 %08x S2 %08x S1 %08x S0 %08x\n", - regs[8], regs[9], regs[10], regs[11]); - ccprintf("T6 %08x T5 %08x T4 %08x T3 %08x\n", - regs[12], regs[13], regs[14], regs[15]); - ccprintf("T2 %08x T1 %08x T0 %08x A7 %08x\n", - regs[16], regs[17], regs[18], regs[19]); + ccprintf("S11 %08x S10 %08x S9 %08x S8 %08x\n", regs[0], regs[1], + regs[2], regs[3]); + ccprintf("S7 %08x S6 %08x S5 %08x S4 %08x\n", regs[4], regs[5], + regs[6], regs[7]); + ccprintf("S3 %08x S2 %08x S1 %08x S0 %08x\n", regs[8], regs[9], + regs[10], regs[11]); + ccprintf("T6 %08x T5 %08x T4 %08x T3 %08x\n", regs[12], regs[13], + regs[14], regs[15]); + ccprintf("T2 %08x T1 %08x T0 %08x A7 %08x\n", regs[16], regs[17], + regs[18], regs[19]); cflush(); - ccprintf("A6 %08x A5 %08x A4 %08x A3 %08x\n", - regs[20], regs[21], regs[22], regs[23]); - ccprintf("A2 %08x A1 %08x A0 %08x TP %08x\n", - regs[24], regs[25], regs[26], regs[27]); - ccprintf("GP %08x RA %08x SP %08x MEPC %08x\n", - regs[28], regs[29], regs[30], mepc); + ccprintf("A6 %08x A5 %08x A4 %08x A3 %08x\n", regs[20], regs[21], + regs[22], regs[23]); + ccprintf("A2 %08x A1 %08x A0 %08x TP %08x\n", regs[24], regs[25], + regs[26], regs[27]); + ccprintf("GP %08x RA %08x SP %08x MEPC %08x\n", regs[28], regs[29], + regs[30], mepc); #ifdef CONFIG_DEBUG_EXCEPTIONS if ((regs[SOFT_PANIC_GPR_REASON] & 0xfffffff0) == PANIC_SW_BASE) { #ifdef CONFIG_SOFTWARE_PANIC ccprintf("Software panic reason: %s\n", - panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - - PANIC_SW_BASE)]); + panic_sw_reasons[(regs[SOFT_PANIC_GPR_REASON] - + PANIC_SW_BASE)]); ccprintf("Software panic info: %d\n", - regs[SOFT_PANIC_GPR_INFO]); + regs[SOFT_PANIC_GPR_INFO]); #endif /* CONFIG_SOFTWARE_PANIC */ } else { ccprintf("Exception type: %s\n", exc_type[(mcause & 0xf)]); -- cgit v1.2.1 From 5379f45ca919da37bcc14d3a68f7352630fcb4b9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:14 -0600 Subject: zephyr/projects/nissa/src/nivviks/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iefc16de81f3cc0b098df4448bc4f0a75d28f0284 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730793 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/nivviks/keyboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/nissa/src/nivviks/keyboard.c b/zephyr/projects/nissa/src/nivviks/keyboard.c index dc5c42e33a..406ea246b4 100644 --- a/zephyr/projects/nissa/src/nivviks/keyboard.c +++ b/zephyr/projects/nissa/src/nivviks/keyboard.c @@ -22,8 +22,8 @@ static const struct ec_response_keybd_config nivviks_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &nivviks_kb; } -- cgit v1.2.1 From 091c999194ea502780df83d0dd8a23fe88025745 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:00 -0600 Subject: zephyr/shim/include/usbc/utils.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4ccfd5f2bd19270ee079bdb120b1774994e4a30b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730855 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/utils.h | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/usbc/utils.h b/zephyr/shim/include/usbc/utils.h index 49b9aa4b71..fdb42bc3b6 100644 --- a/zephyr/shim/include/usbc/utils.h +++ b/zephyr/shim/include/usbc/utils.h @@ -5,18 +5,15 @@ #ifndef __CROS_EC_ZEPHYR_SHIM_USBC_UTIL - /* * Enable interrupt from the `irq` property of an instance's node. * * @param inst: instance number */ -#define BC12_GPIO_ENABLE_INTERRUPT(inst) \ - IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \ - (gpio_enable_dt_interrupt( \ - GPIO_INT_FROM_NODE(DT_INST_PHANDLE(inst, irq)));\ - ) \ - ) +#define BC12_GPIO_ENABLE_INTERRUPT(inst) \ + IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, irq), \ + (gpio_enable_dt_interrupt( \ + GPIO_INT_FROM_NODE(DT_INST_PHANDLE(inst, irq)));)) /* * Get the port number from a child of `named-usbc-port` node. @@ -32,5 +29,4 @@ */ #define USBC_PORT_FROM_INST(inst) USBC_PORT(DT_DRV_INST(inst)) - #endif /* __CROS_EC_ZEPHYR_SHIM_USBC_UTIL */ -- cgit v1.2.1 From f8891cc3420603d1846eafa528901cad4f4b6da2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:18:09 -0600 Subject: include/vec3.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaca1124fdf0e2f6a6ec4e335cd70d0cdc0ee6b5d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730455 Reviewed-by: Jeremy Bettis --- include/vec3.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/vec3.h b/include/vec3.h index e7fcf92041..50d15943bd 100644 --- a/include/vec3.h +++ b/include/vec3.h @@ -80,4 +80,4 @@ fp_t fpv3_norm_squared(const fpv3_t v); */ fp_t fpv3_norm(const fpv3_t v); -#endif /* __CROS_EC_VEC_3_H */ +#endif /* __CROS_EC_VEC_3_H */ -- cgit v1.2.1 From a9dd63f3838b10292635880d978bf5be4db8126e Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Fri, 1 Jul 2022 10:52:56 -0600 Subject: zephyr: tests: Update shuffle script to save logs Have the shuffle script save the output of each run to /tmp/shuffle___.log for later analysis. This is useful for further investigating tests that match the filter text and can also allows recycling the logs later to search for additional failures. The field in the file name can be: * `0-matches` indicating no matches found * `timed-out` indicating the test could not complete * `exit-code-N` indicating the run exited with non-zero code N * `N-matches` indicating N>0 matches were found. This outcome has higher priority than the others and will be written even if an error occurred. BRANCH=main BUG=None TEST=util/shuffle_test.sh Signed-off-by: Tristan Honscheid Change-Id: Ia921522f54e145f44f9dc4361a091f4da2bce510 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3738760 Reviewed-by: Yuval Peress --- util/shuffle_test.sh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh index 55c9055e06..69a6f694f3 100755 --- a/util/shuffle_test.sh +++ b/util/shuffle_test.sh @@ -11,23 +11,37 @@ zmake build --clobber test-drivers || exit 1 echo "Searching for '${1}'..." found_errors=0 loop_count=100 +start_time=$(date +%Y-%m-%d_%H.%M.%S) +log_dir="/tmp" EXECUTABLE=./build/zephyr/test-drivers/build-singleimage/zephyr/zephyr.exe while [ "${loop_count}" -gt 0 ]; do seed=${RANDOM} + log_file_prefix="${log_dir}"/shuffle_"${start_time}"_"${seed}" + echo "[$((100 - loop_count))] Using seed=${seed}" error_count=$(timeout 150s "${EXECUTABLE}" -seed="${seed}" 2>&1 | + tee "${log_file_prefix}".log | grep -c "${1}") status=$? + result="0-matches" if [ "${status}" -eq 124 ]; then echo " Timeout" + result="timed-out" elif [ "${status}" -ne 0 ]; then echo " Error/timeout" + result="exit-code-${status}" fi if [ "${error_count}" -gt 0 ]; then echo " Found ${error_count} errors matching '${1}'" + result="${error_count}-matches" fi + # Rename the log file to include the outcome + mv \ + "${log_file_prefix}".log \ + "${log_file_prefix}"_"${result}".log + found_errors=$((found_errors + error_count)) loop_count=$((loop_count - 1)) done -- cgit v1.2.1 From 12eefbeedba32a643b5de30ee76876ea6185ce70 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:21:56 -0600 Subject: board/banshee/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5bf0ba89f6e1f13511f0d8870ce1fc06cd903918 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728002 Reviewed-by: Jeremy Bettis --- board/banshee/led.c | 70 +++++++++++++++++++++-------------------------------- 1 file changed, 28 insertions(+), 42 deletions(-) diff --git a/board/banshee/led.c b/board/banshee/led.c index b1c6a6445f..fc51acf32e 100644 --- a/board/banshee/led.c +++ b/board/banshee/led.c @@ -28,16 +28,15 @@ #define LED_TICKS_PER_CYCLE 10 #define LED_ON_TICKS 5 -#define BREATH_LIGHT_LENGTH 55 -#define BREATH_HOLD_LENGTH 50 -#define BREATH_OFF_LENGTH 200 +#define BREATH_LIGHT_LENGTH 55 +#define BREATH_HOLD_LENGTH 50 +#define BREATH_OFF_LENGTH 200 const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, EC_LED_ID_POWER_LED, }; - enum breath_status { BREATH_LIGHT_UP = 0, BREATH_LIGHT_DOWN, @@ -45,26 +44,23 @@ enum breath_status { BREATH_OFF, }; -enum led_port { - RIGHT_PORT = 1, - LEFT_PORT -}; +enum led_port { RIGHT_PORT = 1, LEFT_PORT }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 50, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 50, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 8 }, - [EC_LED_COLOR_YELLOW] = { 40, 50, 0 }, - [EC_LED_COLOR_WHITE] = { 20, 50, 25 }, - [EC_LED_COLOR_AMBER] = { 45, 5, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 50, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 50, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 8 }, + [EC_LED_COLOR_YELLOW] = { 40, 50, 0 }, + [EC_LED_COLOR_WHITE] = { 20, 50, 25 }, + [EC_LED_COLOR_AMBER] = { 45, 5, 0 }, }; struct pwm_led_color_map pwr_led_color_map[EC_LED_COLOR_COUNT] = { - /* White, Green, Red */ - [EC_LED_COLOR_WHITE] = { BREATH_LIGHT_LENGTH, 0, 0 }, + /* White, Green, Red */ + [EC_LED_COLOR_WHITE] = { BREATH_LIGHT_LENGTH, 0, 0 }, }; /* @@ -88,13 +84,11 @@ struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = { }, }; - uint8_t breath_led_light_up; uint8_t breath_led_light_down; uint8_t breath_led_hold; uint8_t breath_led_off; - int breath_pwm_enable; int breath_led_status; static void breath_led_pwm_deferred(void); @@ -110,13 +104,11 @@ DECLARE_DEFERRED(breath_led_pwm_deferred); static void breath_led_pwm_deferred(void) { - switch (breath_led_status) { case BREATH_LIGHT_UP: - if (breath_led_light_up <= BREATH_LIGHT_LENGTH) - pwm_set_duty(PWM_CH_POWER_LED_W, - breath_led_light_up++); + if (breath_led_light_up <= BREATH_LIGHT_LENGTH) + pwm_set_duty(PWM_CH_POWER_LED_W, breath_led_light_up++); else { breath_led_light_up = 0; breath_led_light_down = BREATH_LIGHT_LENGTH; @@ -126,7 +118,7 @@ static void breath_led_pwm_deferred(void) break; case BREATH_HOLD: - if (breath_led_hold <= BREATH_HOLD_LENGTH) + if (breath_led_hold <= BREATH_HOLD_LENGTH) breath_led_hold++; else { breath_led_hold = 0; @@ -138,7 +130,7 @@ static void breath_led_pwm_deferred(void) if (breath_led_light_down != 0) pwm_set_duty(PWM_CH_POWER_LED_W, - breath_led_light_down--); + breath_led_light_down--); else { breath_led_light_down = BREATH_LIGHT_LENGTH; breath_led_status = BREATH_OFF; @@ -147,7 +139,7 @@ static void breath_led_pwm_deferred(void) break; case BREATH_OFF: - if (breath_led_off <= BREATH_OFF_LENGTH) + if (breath_led_off <= BREATH_OFF_LENGTH) breath_led_off++; else { breath_led_off = 0; @@ -157,12 +149,10 @@ static void breath_led_pwm_deferred(void) break; } - if (breath_pwm_enable) hook_call_deferred(&breath_led_pwm_deferred_data, 10 * MSEC); } - void breath_led_run(uint8_t enable) { if (enable && !breath_pwm_enable) { @@ -180,7 +170,6 @@ void breath_led_run(uint8_t enable) } } - void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { if (led_id == EC_LED_ID_BATTERY_LED) { @@ -192,7 +181,6 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) brightness_range[EC_LED_COLOR_WHITE] = 100; } else if (led_id == EC_LED_ID_POWER_LED) brightness_range[EC_LED_COLOR_WHITE] = 100; - } void set_pwr_led_color(enum pwm_led_id id, int color) @@ -265,8 +253,8 @@ static int led_get_charge_percent(void) static void select_active_port_led(int port) { if ((charge_get_state() == PWR_STATE_DISCHARGE && - led_get_charge_percent() < 10) || - charge_get_state() == PWR_STATE_ERROR) { + led_get_charge_percent() < 10) || + charge_get_state() == PWR_STATE_ERROR) { gpio_set_level(GPIO_LEFT_SIDE, 1); gpio_set_level(GPIO_RIGHT_SIDE, 1); } else if (port == RIGHT_PORT) { @@ -283,8 +271,7 @@ static void select_active_port_led(int port) static int led_power_enable(void) { - if (gpio_get_level(GPIO_LEFT_SIDE) || - gpio_get_level(GPIO_RIGHT_SIDE)) + if (gpio_get_level(GPIO_LEFT_SIDE) || gpio_get_level(GPIO_RIGHT_SIDE)) return true; return false; @@ -322,14 +309,15 @@ static void led_set_battery(void) if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { if (led_get_charge_percent() < 10) set_active_port_color((battery_ticks & 0x2) ? - EC_LED_COLOR_RED : -1); + EC_LED_COLOR_RED : + -1); else set_active_port_color(-1); } break; case PWR_STATE_ERROR: - set_active_port_color((battery_ticks & 0x2) ? - EC_LED_COLOR_RED : -1); + set_active_port_color((battery_ticks & 0x2) ? EC_LED_COLOR_RED : + -1); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(EC_LED_COLOR_GREEN); @@ -337,14 +325,14 @@ static void led_set_battery(void) case PWR_STATE_IDLE: if (chflags & CHARGE_FLAG_FORCE_IDLE) set_active_port_color((battery_ticks & 0x4) ? - EC_LED_COLOR_AMBER : -1); + EC_LED_COLOR_AMBER : + -1); else set_active_port_color(EC_LED_COLOR_AMBER); break; default: break; } - } static void led_set_power(void) @@ -352,8 +340,7 @@ static void led_set_power(void) if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { breath_led_run(1); return; - } - else + } else breath_led_run(0); if (chipset_in_state(CHIPSET_STATE_ON)) { @@ -369,6 +356,5 @@ static void led_tick(void) led_set_battery(); if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) led_set_power(); - } DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From f8cae398638d824e5953ed8af252cbe9ff9bc536 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:25:51 -0600 Subject: chip/npcx/spiflashfw/npcx_monitor.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb7958e17f599720fa629e1cb075721ac7cd43c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729437 Reviewed-by: Jeremy Bettis --- chip/npcx/spiflashfw/npcx_monitor.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/chip/npcx/spiflashfw/npcx_monitor.c b/chip/npcx/spiflashfw/npcx_monitor.c index f22037f8de..573c44190e 100644 --- a/chip/npcx/spiflashfw/npcx_monitor.c +++ b/chip/npcx/spiflashfw/npcx_monitor.c @@ -49,7 +49,7 @@ void sspi_flash_execute_cmd(uint8_t code, uint8_t cts) /* set UMA_CODE */ NPCX_UMA_CODE = code; /* execute UMA flash transaction */ - NPCX_UMA_CTS = cts; + NPCX_UMA_CTS = cts; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } @@ -76,7 +76,7 @@ void sspi_flash_wait_ready(void) sspi_flash_execute_cmd(CMD_READ_STATUS_REG, MASK_CMD_ONLY); do { /* Read status register */ - NPCX_UMA_CTS = MASK_RD_1BYTE; + NPCX_UMA_CTS = MASK_RD_1BYTE; while (IS_BIT_SET(NPCX_UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) ; } while (NPCX_UMA_DB0 & mask); /* Wait for Busy clear */ @@ -108,7 +108,7 @@ void sspi_flash_set_address(uint32_t dest_addr) } void sspi_flash_burst_write(unsigned int dest_addr, unsigned int bytes, - const char *data) + const char *data) { unsigned int i; /* Chip Select down. */ @@ -197,7 +197,7 @@ void sspi_flash_physical_erase(int offset, int size) /* Alignment has been checked in upper layer */ for (; size > 0; size -= NPCX_MONITOR_FLASH_ERASE_SIZE, - offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { + offset += NPCX_MONITOR_FLASH_ERASE_SIZE) { /* Enable write */ sspi_flash_write_enable(); /* Set erase address */ @@ -221,7 +221,7 @@ int sspi_flash_verify(int offset, int size, const char *data) uint8_t cmp_data; ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset); - ptr_mram = (uint8_t *)data; + ptr_mram = (uint8_t *)data; result = 1; /* Disable tri-state */ @@ -255,12 +255,11 @@ int sspi_flash_get_image_used(const char *fw_base) for (size--; size > 0 && image[size] != 0xea; size--) ; - return size ? size + 1 : 0; /* 0xea byte IS part of the image */ - + return size ? size + 1 : 0; /* 0xea byte IS part of the image */ } /* Entry function of spi upload function */ -uint32_t __attribute__ ((section(".startup_text"))) +uint32_t __attribute__((section(".startup_text"))) sspi_flash_upload(int spi_offset, int spi_size) { /* @@ -315,7 +314,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* Start to write */ if (image_base != NULL) sspi_flash_physical_write(spi_offset, sz_image, - image_base); + image_base); /* Verify data */ if (sspi_flash_verify(spi_offset, sz_image, image_base)) *flag_upload |= 0x02; -- cgit v1.2.1 From 042a6c8af33cc408b9bee17c22dfad4d3d465525 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:54 -0600 Subject: board/moli/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I94bb1eb0dcdcb3d4587ff67f625cefe5f18a26b5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728688 Reviewed-by: Jeremy Bettis --- board/moli/board.c | 52 +++++++++++++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/board/moli/board.c b/board/moli/board.c index 4a6445a8d6..93cb64d4a0 100644 --- a/board/moli/board.c +++ b/board/moli/board.c @@ -24,8 +24,8 @@ #include "usbc_ppc.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) static void power_monitor(void); DECLARE_DEFERRED(power_monitor); @@ -124,13 +124,11 @@ static const struct { int current; } bj_power[] = { { /* 0 - 90W (also default) */ - .voltage = 19000, - .current = 4740 - }, + .voltage = 19000, + .current = 4740 }, { /* 1 - 135W */ - .voltage = 19000, - .current = 6920 - }, + .voltage = 19000, + .current = 6920 }, }; static unsigned int ec_config_get_bj_power(void) @@ -146,7 +144,7 @@ static unsigned int ec_config_get_bj_power(void) return bj; } -#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ +#define ADP_DEBOUNCE_MS 1000 /* Debounce time for BJ plug/unplug */ /* Debounced connection state of the barrel jack */ static int8_t adp_connected = -1; static void adp_connect_deferred(void) @@ -249,25 +247,25 @@ void board_overcurrent_event(int port, int is_overcurrented) * * All measurements are in milliwatts. */ -#define THROT_TYPE_A_FRONT BIT(0) -#define THROT_TYPE_A_REAR BIT(1) -#define THROT_TYPE_C0 BIT(2) -#define THROT_TYPE_C1 BIT(3) -#define THROT_PROCHOT BIT(5) +#define THROT_TYPE_A_FRONT BIT(0) +#define THROT_TYPE_A_REAR BIT(1) +#define THROT_TYPE_C0 BIT(2) +#define THROT_TYPE_C1 BIT(3) +#define THROT_PROCHOT BIT(5) /* * Power gain if front USB A ports are limited. */ -#define POWER_GAIN_TYPE_A 3200 +#define POWER_GAIN_TYPE_A 3200 /* * Power gain if Type C port is limited. */ -#define POWER_GAIN_TYPE_C 8800 +#define POWER_GAIN_TYPE_C 8800 /* * Power is averaged over 10 ms, with a reading every 2 ms. */ -#define POWER_DELAY_MS 2 -#define POWER_READINGS (10/POWER_DELAY_MS) +#define POWER_DELAY_MS 2 +#define POWER_READINGS (10 / POWER_DELAY_MS) #include "gpio_list.h" /* Must come after other header files. */ @@ -283,8 +281,7 @@ static void power_monitor(void) * If CPU is off or suspended, no need to throttle * or restrict power. */ - if (chipset_in_state(CHIPSET_STATE_ANY_OFF | - CHIPSET_STATE_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF | CHIPSET_STATE_SUSPEND)) { /* * Slow down monitoring, assume no throttling required. */ @@ -312,7 +309,7 @@ static void power_monitor(void) */ power = (adc_read_channel(ADC_VBUS) * adc_read_channel(ADC_PPVAR_IMON)) / - 1000; + 1000; /* Init power table */ if (history[0] == 0) { for (i = 0; i < POWER_READINGS; i++) @@ -339,8 +336,7 @@ static void power_monitor(void) * For barrel-jack supplies, the rating can be * exceeded briefly, so use the average. */ - if (charge_manager_get_supplier() == - CHARGE_SUPPLIER_PD) + if (charge_manager_get_supplier() == CHARGE_SUPPLIER_PD) power = max; else power = total / POWER_READINGS; @@ -403,16 +399,18 @@ static void power_monitor(void) gpio_set_level(GPIO_EC_PROCHOT_ODL, prochot); } if (diff & THROT_TYPE_C0) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C0) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(0, rp); tcpm_select_rp_value(0, rp); pd_update_contract(0); } if (diff & THROT_TYPE_C1) { - enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) - ? TYPEC_RP_1A5 : TYPEC_RP_3A0; + enum tcpc_rp_value rp = (new_state & THROT_TYPE_C1) ? + TYPEC_RP_1A5 : + TYPEC_RP_3A0; ppc_set_vbus_source_current_limit(1, rp); tcpm_select_rp_value(1, rp); -- cgit v1.2.1 From e7cfa905612365e2771e54660b1e6e0ea69674f9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:25 -0600 Subject: util/gen_emmc_transfer_data.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I805cc6cdb8837869d478b8968f86ab1619af8f49 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730622 Reviewed-by: Jeremy Bettis --- util/gen_emmc_transfer_data.c | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/util/gen_emmc_transfer_data.c b/util/gen_emmc_transfer_data.c index 98417beb9b..65620f6c6a 100644 --- a/util/gen_emmc_transfer_data.c +++ b/util/gen_emmc_transfer_data.c @@ -16,8 +16,8 @@ #include /* eMMC transfer block size */ -#define BLOCK_SIZE 512 -#define BLOCK_RAW_DATA "bootblock_raw_data" +#define BLOCK_SIZE 512 +#define BLOCK_RAW_DATA "bootblock_raw_data" uint16_t crc16_arg(uint8_t data, uint16_t previous_crc) { @@ -42,12 +42,11 @@ void header_format(FILE *fin, FILE *fout) size_t cnt = 0; fprintf(fout, "/* This file is auto-generated. Do not modify. */\n" - "#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n" - "#define __CROS_EC_BOOTBLOCK_DATA_H\n" - "\n" - "#include \n" - "\n" - ); + "#ifndef __CROS_EC_BOOTBLOCK_DATA_H\n" + "#define __CROS_EC_BOOTBLOCK_DATA_H\n" + "\n" + "#include \n" + "\n"); fprintf(fout, "static const uint8_t %s[] __attribute__((aligned(4))) =\n" @@ -64,18 +63,19 @@ void header_format(FILE *fin, FILE *fout) if (cnt == 0) break; else if (cnt < BLOCK_SIZE) - memset(&data[cnt], 0xff, BLOCK_SIZE-cnt); + memset(&data[cnt], 0xff, BLOCK_SIZE - cnt); fprintf(fout, "\t/* Block %d (%ld) */\n", blk, cnt); fprintf(fout, "\t0xff, 0xfe, /* idle, start bit. */"); for (j = 0; j < sizeof(data); j++) { - fprintf(fout, "%s0x%02x,", - (j % 8) == 0 ? "\n\t" : " ", data[j]); + fprintf(fout, "%s0x%02x,", (j % 8) == 0 ? "\n\t" : " ", + data[j]); crc16 = crc16_arg(data[j], crc16); } fprintf(fout, "\n"); - fprintf(fout, "\t0x%02x, 0x%02x, 0xff," + fprintf(fout, + "\t0x%02x, 0x%02x, 0xff," " /* CRC, end bit, idle */\n", crc16 >> 8, crc16 & 0xff); } @@ -96,16 +96,14 @@ int main(int argc, char **argv) FILE *fout = NULL; const char short_opts[] = "i:ho:"; - const struct option long_opts[] = { - { "input", 1, NULL, 'i' }, - { "help", 0, NULL, 'h' }, - { "out", 1, NULL, 'o' }, - { NULL } - }; + const struct option long_opts[] = { { "input", 1, NULL, 'i' }, + { "help", 0, NULL, 'h' }, + { "out", 1, NULL, 'o' }, + { NULL } }; const char usage[] = "USAGE: %s [-i ] -o \n"; - while ((nopt = getopt_long(argc, argv, short_opts, long_opts, - NULL)) != -1) { + while ((nopt = getopt_long(argc, argv, short_opts, long_opts, NULL)) != + -1) { switch (nopt) { case 'i': /* -i or --input*/ input_name = optarg; -- cgit v1.2.1 From a7c2b8f7d9cabd28781810a8ada61cb2de7fffd5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:31:40 -0600 Subject: chip/stm32/usart_rx_interrupt-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11e3823174a621f6139eb1d5c5a1b1821a35609f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729421 Reviewed-by: Jeremy Bettis --- chip/stm32/usart_rx_interrupt-stm32f4.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/stm32/usart_rx_interrupt-stm32f4.c b/chip/stm32/usart_rx_interrupt-stm32f4.c index b796ae1175..7035a21a4a 100644 --- a/chip/stm32/usart_rx_interrupt-stm32f4.c +++ b/chip/stm32/usart_rx_interrupt-stm32f4.c @@ -26,8 +26,8 @@ static void usart_rx_init(struct usart_config const *config) static void usart_rx_interrupt_handler(struct usart_config const *config) { - intptr_t base = config->hw->base; - int32_t status = STM32_USART_SR(base); + intptr_t base = config->hw->base; + int32_t status = STM32_USART_SR(base); if (status & STM32_USART_SR_RXNE) { uint8_t byte = STM32_USART_RDR(base); -- cgit v1.2.1 From fa56661d714378f304e2191e5cfbc51917c5b63a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:28 -0600 Subject: board/morphius/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife44a3f13f0818cd4fe589ace6369938a7cf25c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728700 Reviewed-by: Jeremy Bettis --- board/morphius/board.c | 91 +++++++++++++++++++++----------------------------- 1 file changed, 38 insertions(+), 53 deletions(-) diff --git a/board/morphius/board.c b/board/morphius/board.c index beca0d89f0..99434e485c 100644 --- a/board/morphius/board.c +++ b/board/morphius/board.c @@ -59,21 +59,15 @@ static bool ignore_c1_dp; static struct mutex g_lid_mutex; static struct mutex g_base_mutex; -mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -const mat33_fp_t base_standard_ref_1 = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; -mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +const mat33_fp_t base_standard_ref_1 = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; +mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -304,8 +298,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the PS8802 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_ps8802, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_ps8802, sizeof(struct usb_mux)); /* Set the AMD FP5 as the secondary MUX */ @@ -323,8 +316,7 @@ static void setup_mux(void) * Replace usb_muxes[USBC_PORT_C1] with the AMD FP5 * table entry. */ - memcpy(&usb_muxes[USBC_PORT_C1], - &usbc1_amd_fp5_usb_mux, + memcpy(&usb_muxes[USBC_PORT_C1], &usbc1_amd_fp5_usb_mux, sizeof(struct usb_mux)); /* Set the PS8818 as the secondary MUX */ @@ -400,11 +392,9 @@ int board_usbc_port_to_hpd_gpio_or_ioex(int port) * this will be removed when version_2 hardware is retired. */ else if (ec_config_has_mst_hub_rtd2141b()) - return (board_ver >= 4) - ? GPIO_USB_C1_HPD_IN_DB_V1 - : (board_ver == 3) - ? IOEX_USB_C1_HPD_IN_DB - : GPIO_EC_DP1_HPD; + return (board_ver >= 4) ? GPIO_USB_C1_HPD_IN_DB_V1 : + (board_ver == 3) ? IOEX_USB_C1_HPD_IN_DB : + GPIO_EC_DP1_HPD; /* USB-C1 OPT1 DB uses DP2_HPD. */ return GPIO_DP2_HPD; @@ -486,7 +476,7 @@ DECLARE_HOOK(HOOK_INIT, setup_fw_config, HOOK_PRIO_INIT_I2C + 2); /* Physical fans. These are logically separate from pwm_channels. */ const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = -1, }; @@ -584,8 +574,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(105), \ @@ -605,11 +595,11 @@ static void setup_fans(void) DECLARE_HOOK(HOOK_INIT, setup_fans, HOOK_PRIO_DEFAULT); /* Battery functions */ -#define SB_OPTIONALMFG_FUNCTION2 0x26 -#define SMART_CHARGE_SUPPORT 0x01 -#define SMART_CHARGE_ENABLE 0x02 -#define SB_SMART_CHARGE_ENABLE 1 -#define SB_SMART_CHARGE_DISABLE 0 +#define SB_OPTIONALMFG_FUNCTION2 0x26 +#define SMART_CHARGE_SUPPORT 0x01 +#define SMART_CHARGE_ENABLE 0x02 +#define SB_SMART_CHARGE_ENABLE 1 +#define SB_SMART_CHARGE_DISABLE 0 static void sb_smart_charge_mode(int enable) { @@ -651,18 +641,18 @@ __override void ppc_interrupt(enum gpio_signal signal) * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 * current limits. */ -__override int board_aoz1380_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) +__override int +board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) { int rv; /* Use the TCPC to set the current limit */ if (port == 0) { rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); + (rp == TYPEC_RP_3A0) ? 1 : 0); } else if (board_ver >= 3) { rv = ioex_set_level(IOEX_USB_C1_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); + (rp == TYPEC_RP_3A0) ? 1 : 0); } else { rv = 1; } @@ -716,8 +706,7 @@ static void board_chipset_resume(void) ioex_set_level(IOEX_HDMI_POWER_EN_DB, 1); msleep(PI3HDX1204_POWER_ON_DELAY_MS); } - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, check_hdmi_hpd_status()); } } @@ -735,16 +724,14 @@ static void board_chipset_suspend(void) sb_smart_charge_mode(SB_SMART_CHARGE_ENABLE); if (ec_config_has_hdmi_retimer_pi3hdx1204()) { - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - 0); + pi3hdx1204_enable(I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, 0); if (board_ver >= 3) ioex_set_level(IOEX_HDMI_POWER_EN_DB, 0); } /* Wait 500ms before allowing DP event to cause resume. */ - if (ec_config_has_mst_hub_rtd2141b() - && (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) { + if (ec_config_has_mst_hub_rtd2141b() && + (dp_flags[USBC_PORT_C1] & DP_FLAGS_DP_ON)) { ignore_c1_dp = true; hook_call_deferred(&board_chipset_suspend_delay_data, 500 * MSEC); @@ -789,15 +776,14 @@ BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {3, 0}, {2, 2}, {2, 3}, {1, 2}, {2, 5}, - {2, 4}, {2, 1}, {2, 7}, {2, 6}, {1, 5}, - {2, 0}, {3, 1}, {1, 7}, {1, 6}, {-1, -1}, - {1, 3}, {1, 4}, {-1, -1}, {-1, -1}, {0, 7}, - {0, 6}, {1, 0}, {1, 1}, {0, 5}, + { 3, 0 }, { 2, 2 }, { 2, 3 }, { 1, 2 }, { 2, 5 }, { 2, 4 }, + { 2, 1 }, { 2, 7 }, { 2, 6 }, { 1, 5 }, { 2, 0 }, { 3, 1 }, + { 1, 7 }, { 1, 6 }, { -1, -1 }, { 1, 3 }, { 1, 4 }, { -1, -1 }, + { -1, -1 }, { 0, 7 }, { 0, 6 }, { 1, 0 }, { 1, 1 }, { 0, 5 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); #endif /***************************************************************************** @@ -840,10 +826,9 @@ static void hdmi_hpd_handler(void) gpio_set_level(GPIO_EC_DP1_HPD, hpd); ccprints("HDMI HPD %d", hpd); - pi3hdx1204_enable(I2C_PORT_TCPC1, - PI3HDX1204_I2C_ADDR_FLAGS, - chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) - && hpd); + pi3hdx1204_enable( + I2C_PORT_TCPC1, PI3HDX1204_I2C_ADDR_FLAGS, + chipset_in_or_transitioning_to_state(CHIPSET_STATE_ON) && hpd); } DECLARE_DEFERRED(hdmi_hpd_handler); -- cgit v1.2.1 From f4b8703b5d963fcf47e3fc68451a5f6a4eace097 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:15 -0600 Subject: driver/retimer/bb_retimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifaddf33b0d93672577f1fa73c17ffa79f5a4927e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730053 Reviewed-by: Jeremy Bettis --- driver/retimer/bb_retimer.c | 100 ++++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 51 deletions(-) diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index c515505900..3efbaaab6a 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -16,34 +16,32 @@ #include "usb_pd.h" #include "util.h" -#define BB_RETIMER_REG_SIZE 4 -#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1) -#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2) -#define BB_RETIMER_MUX_DATA_PRESENT (USB_PD_MUX_USB_ENABLED \ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_SAFE_MODE \ - | USB_PD_MUX_TBT_COMPAT_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_REG_SIZE 4 +#define BB_RETIMER_READ_SIZE (BB_RETIMER_REG_SIZE + 1) +#define BB_RETIMER_WRITE_SIZE (BB_RETIMER_REG_SIZE + 2) +#define BB_RETIMER_MUX_DATA_PRESENT \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) -#define BB_RETIMER_MUX_USB_ALT_MODE (USB_PD_MUX_USB_ENABLED\ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_TBT_COMPAT_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_MUX_USB_ALT_MODE \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_TBT_COMPAT_ENABLED | USB_PD_MUX_USB4_ENABLED) -#define BB_RETIMER_MUX_USB_DP_MODE (USB_PD_MUX_USB_ENABLED \ - | USB_PD_MUX_DP_ENABLED \ - | USB_PD_MUX_USB4_ENABLED) +#define BB_RETIMER_MUX_USB_DP_MODE \ + (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \ + USB_PD_MUX_USB4_ENABLED) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define BB_RETIMER_I2C_RETRY 5 +#define BB_RETIMER_I2C_RETRY 5 /** * Utility functions */ -static int bb_retimer_read(const struct usb_mux *me, - const uint8_t offset, uint32_t *data) +static int bb_retimer_read(const struct usb_mux *me, const uint8_t offset, + uint32_t *data) { int rv, retry = 0; uint8_t buf[BB_RETIMER_READ_SIZE]; @@ -60,15 +58,15 @@ static int bb_retimer_read(const struct usb_mux *me, * byte[1:4] : Data [LSB -> MSB] * Stop */ - rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, - &offset, 1, buf, BB_RETIMER_READ_SIZE); + rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, &offset, 1, buf, + BB_RETIMER_READ_SIZE); if (rv == EC_SUCCESS) break; if (++retry >= BB_RETIMER_I2C_RETRY) { - CPRINTS("C%d: Retimer I2C read err=%d", - me->usb_port, rv); + CPRINTS("C%d: Retimer I2C read err=%d", me->usb_port, + rv); return rv; } msleep(10); @@ -82,8 +80,8 @@ static int bb_retimer_read(const struct usb_mux *me, return EC_SUCCESS; } -static int bb_retimer_write(const struct usb_mux *me, - const uint8_t offset, uint32_t data) +static int bb_retimer_write(const struct usb_mux *me, const uint8_t offset, + uint32_t data) { int rv, retry = 0; uint8_t buf[BB_RETIMER_WRITE_SIZE]; @@ -109,14 +107,14 @@ static int bb_retimer_write(const struct usb_mux *me, */ while (1) { rv = i2c_xfer(me->i2c_port, me->i2c_addr_flags, buf, - BB_RETIMER_WRITE_SIZE, NULL, 0); + BB_RETIMER_WRITE_SIZE, NULL, 0); if (rv == EC_SUCCESS) break; if (++retry >= BB_RETIMER_I2C_RETRY) { - CPRINTS("C%d: Retimer I2C write err=%d", - me->usb_port, rv); + CPRINTS("C%d: Retimer I2C write err=%d", me->usb_port, + rv); break; } msleep(10); @@ -157,7 +155,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, uint32_t *set_retimer_con) { union tbt_mode_resp_cable cable_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) + }; union tbt_mode_resp_device dev_resp; enum idh_ptype cable_type = get_usb_pd_cable_type(port); @@ -171,7 +170,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * */ if (is_active_cable_element_retimer(port) && - (mux_state & BB_RETIMER_MUX_USB_DP_MODE)) + (mux_state & BB_RETIMER_MUX_USB_DP_MODE)) *set_retimer_con |= BB_RETIMER_RE_TIMER_DRIVER; /* @@ -184,7 +183,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, */ if ((mux_state & BB_RETIMER_MUX_USB_ALT_MODE) && ((cable_type == IDH_PTYPE_ACABLE) || - cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE)) + cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE)) *set_retimer_con |= BB_RETIMER_ACTIVE_PASSIVE; if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED || @@ -239,7 +238,7 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, */ if ((cable_type == IDH_PTYPE_ACABLE || cable_resp.tbt_active_passive == TBT_CABLE_ACTIVE) && - cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) + cable_resp.lsrx_comm == UNIDIR_LSRX_COMM) *set_retimer_con |= BB_RETIMER_TBT_ACTIVE_LINK_TRAINING; /* @@ -251,9 +250,9 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * 10..11b - Reserved */ *set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT( - mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ? - get_tbt_cable_speed(port) : - get_usb4_cable_speed(port)); + mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED ? + get_tbt_cable_speed(port) : + get_usb4_cable_speed(port)); /* * Bits 29-28: TBT_GEN_SUPPORT @@ -262,8 +261,8 @@ static void retimer_set_state_dfp(int port, mux_state_t mux_state, * 20.0625Gb/s, 20.000Gb/s) * 10..11b - Reserved */ - *set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION( - cable_resp.tbt_rounded); + *set_retimer_con |= + BB_RETIMER_TBT_CABLE_GENERATION(cable_resp.tbt_rounded); } } @@ -284,7 +283,8 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, /* TODO:b/168890624: Set USB4 retimer config for UFP */ if (mux_state & USB_PD_MUX_TBT_COMPAT_ENABLED) { union tbt_dev_mode_enter_cmd ufp_tbt_enter_mode = { - .raw_value = pd_ufp_get_enter_mode(port)}; + .raw_value = pd_ufp_get_enter_mode(port) + }; /* * Bit 2: RE_TIMER_DRIVER * 0 - Re-driver @@ -316,9 +316,9 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, */ if ((IS_ENABLED(CONFIG_USBC_RETIMER_INTEL_BB_VPRO_CAPABLE) && ufp_tbt_enter_mode.intel_spec_b0 == - VENDOR_SPECIFIC_SUPPORTED) || + VENDOR_SPECIFIC_SUPPORTED) || ufp_tbt_enter_mode.vendor_spec_b1 == - VENDOR_SPECIFIC_SUPPORTED) + VENDOR_SPECIFIC_SUPPORTED) *set_retimer_con |= BB_RETIMER_VPRO_DOCK_DP_OVERDRIVE; /* @@ -352,7 +352,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, * Set according to TBT3 Enter Mode bit 18:16 */ *set_retimer_con |= BB_RETIMER_USB4_TBT_CABLE_SPEED_SUPPORT( - ufp_tbt_enter_mode.tbt_cable_speed); + ufp_tbt_enter_mode.tbt_cable_speed); /* * Bits 29-28: TBT_GEN_SUPPORT * 00b - 3rd generation TBT (10.3125 and 20.625Gb/s) @@ -363,7 +363,7 @@ static void retimer_set_state_ufp(int port, mux_state_t mux_state, * Set according to TBT3 Enter Mode bit 20:19 */ *set_retimer_con |= BB_RETIMER_TBT_CABLE_GENERATION( - ufp_tbt_enter_mode.tbt_rounded); + ufp_tbt_enter_mode.tbt_rounded); } } @@ -429,7 +429,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, */ dp_pin_mode = get_dp_pin_mode(port); if (dp_pin_mode == MODE_DP_PIN_C || - dp_pin_mode == MODE_DP_PIN_D) + dp_pin_mode == MODE_DP_PIN_D) set_retimer_con |= BB_RETIMER_DP_PIN_ASSIGNMENT; /* @@ -472,7 +472,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, /* Writing the register4 */ return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, - set_retimer_con); + set_retimer_con); } void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, @@ -544,8 +544,7 @@ static int retimer_init(const struct usb_mux *me) if (data != BB_RETIMER_DEVICE_ID) return EC_ERROR_INVAL; #else - if ((data != BB_RETIMER_VENDOR_ID_1) && - data != BB_RETIMER_VENDOR_ID_2) + if ((data != BB_RETIMER_VENDOR_ID_1) && data != BB_RETIMER_VENDOR_ID_2) return EC_ERROR_INVAL; rv = bb_retimer_read(me, BB_RETIMER_REG_DEVICE_ID, &data); @@ -615,10 +614,9 @@ static int console_command_bb_retimer(int argc, char **argv) else { rv = bb_retimer_write(mux, reg, val); if (rv == EC_SUCCESS) { - rv = bb_retimer_read( - mux, reg, &data); - if (rv == EC_SUCCESS && data != val) - rv = EC_ERROR_UNKNOWN; + rv = bb_retimer_read(mux, reg, &data); + if (rv == EC_SUCCESS && data != val) + rv = EC_ERROR_UNKNOWN; } } if (rv == EC_SUCCESS) -- cgit v1.2.1 From 865d2c52cecc4ac98a219cdadda0e05adf7a131c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:38 -0600 Subject: board/delbin/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icbc5c4551ea319b6fbd6dd4a9d037e6d025b2734 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728197 Reviewed-by: Jeremy Bettis --- board/delbin/board.c | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/board/delbin/board.c b/board/delbin/board.c index 0e84dd2da6..a015c87ed7 100644 --- a/board/delbin/board.c +++ b/board/delbin/board.c @@ -43,7 +43,7 @@ #include "gpio_list.h" /* Must come after other header files. */ -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -122,7 +122,7 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_PRE_DEFAULT); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -158,8 +158,8 @@ const struct fan_t fans[FAN_CH_COUNT] = { /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -186,8 +186,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -314,23 +314,22 @@ static void ps8815_reset(int port) } gpio_set_level(ps8xxx_rst_odl, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, - PS8815_PWR_H_RST_H_DELAY_MS)); + msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); gpio_set_level(ps8xxx_rst_odl, 1); msleep(PS8815_FW_INIT_DELAY_MS); CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__); - if (i2c_read8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f was %02x", val); - if (i2c_write8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == EC_SUCCESS) + if (i2c_write8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, 0x31) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f set to 0x31"); - if (i2c_read8(i2c_port, - PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == EC_SUCCESS) + if (i2c_read8(i2c_port, PS8XXX_I2C_ADDR1_P2_FLAGS, 0x0f, &val) == + EC_SUCCESS) CPRINTS("ps8815: reg 0x0f now %02x", val); } @@ -338,10 +337,10 @@ void board_reset_pd_mcu(void) { ps8815_reset(USBC_PORT_C0); usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); ps8815_reset(USBC_PORT_C1); usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } /******************************************************************************/ @@ -393,8 +392,8 @@ static const struct ec_response_keybd_config delbin_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY | KEYBD_CAP_NUMERIC_KEYPAD, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &delbin_kb; } @@ -405,19 +404,19 @@ static void ps8811_init(void) /* Set Channel A output swing to Level1 */ rv = i2c_write8(I2C_PORT_USB_1_MIX, - PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10); + PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x66, 0x10); /* Set 50 ohm termination adjuct for B channel: -9%*/ rv |= i2c_write8(I2C_PORT_USB_1_MIX, - PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04); + PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0x73, 0x04); /* Set Channel B output swing to Level3 */ rv |= i2c_write8(I2C_PORT_USB_1_MIX, - PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03); + PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA4, 0x03); /* Set PS level for B channel */ rv |= i2c_write8(I2C_PORT_USB_1_MIX, - PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84); + PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA5, 0x84); /* Set DE level for B channel */ rv |= i2c_write8(I2C_PORT_USB_1_MIX, - PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16); + PS8811_I2C_ADDR_FLAGS0 + PS8811_REG_PAGE1, 0xA6, 0x16); } /* Called on AP S5 -> S0ix transition */ -- cgit v1.2.1 From c2fa2659e0340dfffc098a3fee6205a1adc0f8fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:51 -0600 Subject: test/inductive_charging.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6e511d7dfb651672139720ada6344ef77e2bc47c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730479 Reviewed-by: Jeremy Bettis --- test/inductive_charging.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/inductive_charging.c b/test/inductive_charging.c index d487e171fd..7892c7fab4 100644 --- a/test/inductive_charging.c +++ b/test/inductive_charging.c @@ -17,8 +17,8 @@ #define START_CHARGE_DELAY 5000 /* ms */ #define MONITOR_CHARGE_DONE_DELAY 1000 /* ms */ -#define TEST_CHECK_CHARGE_DELAY (START_CHARGE_DELAY + \ - MONITOR_CHARGE_DONE_DELAY + 500) /* ms */ +#define TEST_CHECK_CHARGE_DELAY \ + (START_CHARGE_DELAY + MONITOR_CHARGE_DONE_DELAY + 500) /* ms */ static void wait_for_lid_debounce(void) { -- cgit v1.2.1 From fa5e3f01cc37d66df49329a63516d0919adf00f4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:28 -0600 Subject: zephyr/test/drivers/include/test/drivers/utils.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0df69832f37afcaa254ca18138aa40e1dfa43940 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730925 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/include/test/drivers/utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index d934144a67..0ffb8b4066 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -466,7 +466,7 @@ void host_cmd_typec_control(int port, enum typec_control_command command, enum typec_mode mode); #define GPIO_ACOK_OD_NODE DT_NODELABEL(gpio_acok_od) -#define GPIO_ACOK_OD_PIN DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios) +#define GPIO_ACOK_OD_PIN DT_GPIO_PIN(GPIO_ACOK_OD_NODE, gpios) /** * Set whether or not AC is enabled. -- cgit v1.2.1 From ad886253b73dbf062c01959aa7effcea1dcdb117 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:42 -0600 Subject: zephyr/test/drivers/src/bmi160.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I95758e9a67985f51a662a0af6c66c5b34d101d31 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730954 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bmi160.c | 147 ++++++++++++++++++++------------------- 1 file changed, 74 insertions(+), 73 deletions(-) diff --git a/zephyr/test/drivers/src/bmi160.c b/zephyr/test/drivers/src/bmi160.c index 56e38e6f9a..473858f5ea 100644 --- a/zephyr/test/drivers/src/bmi160.c +++ b/zephyr/test/drivers/src/bmi160.c @@ -17,28 +17,27 @@ #include "driver/accelgyro_bmi_common.h" #include "test/drivers/test_state.h" -#define BMI_ORD DT_DEP_ORD(DT_NODELABEL(accel_bmi160)) -#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_accel)) -#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro)) -#define BMI_INT_EVENT \ +#define BMI_ORD DT_DEP_ORD(DT_NODELABEL(accel_bmi160)) +#define BMI_ACC_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_accel)) +#define BMI_GYR_SENSOR_ID SENSOR_ID(DT_NODELABEL(ms_bmi160_gyro)) +#define BMI_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(SENSOR_ID(DT_ALIAS(bmi160_int))) /** How accurate comparision of vectors should be */ -#define V_EPS 8 +#define V_EPS 8 /** Convert from one type of vector to another */ -#define convert_int3v_int16(v, r) do { \ - r[0] = v[0]; \ - r[1] = v[1]; \ - r[2] = v[2]; \ +#define convert_int3v_int16(v, r) \ + do { \ + r[0] = v[0]; \ + r[1] = v[1]; \ + r[2] = v[2]; \ } while (0) /** Rotation used in some tests */ -static const mat33_fp_t test_rotation = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t test_rotation = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /** Rotate given vector by test rotation */ static void rotate_int3v_by_test_rotation(intv3_t v) { @@ -125,7 +124,8 @@ static void compare_int3v_f(intv3_t exp_v, intv3_t v, int eps, int line) int i; for (i = 0; i < 3; i++) { - zassert_within(exp_v[i], v[i], eps, + zassert_within( + exp_v[i], v[i], eps, "Expected [%d; %d; %d], got [%d; %d; %d]; line: %d", exp_v[0], exp_v[1], exp_v[2], v[0], v[1], v[2], line); } @@ -172,8 +172,7 @@ ZTEST_USER(bmi160, test_bmi_acc_get_offset) ms->rot_standard_ref = NULL; /* Test get offset without rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v(exp_v, ret_v); @@ -183,8 +182,7 @@ ZTEST_USER(bmi160, test_bmi_acc_get_offset) rotate_int3v_by_test_rotation(exp_v); /* Test get offset with rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v(exp_v, ret_v); @@ -235,8 +233,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_get_offset) ms->rot_standard_ref = NULL; /* Test get offset without rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v_eps(exp_v, ret_v, 64); @@ -246,8 +243,7 @@ ZTEST_USER(bmi160, test_bmi_gyr_get_offset) rotate_int3v_by_test_rotation(exp_v); /* Test get offset with rotation */ - zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), - NULL); + zassert_equal(EC_SUCCESS, ms->drv->get_offset(ms, ret, &temp), NULL); zassert_equal(temp, (int16_t)EC_MOTION_SENSE_INVALID_CALIB_TEMP, NULL); convert_int3v_int16(ret, ret_v); compare_int3v_eps(exp_v, ret_v, 64); @@ -312,7 +308,8 @@ ZTEST_USER(bmi160, test_bmi_acc_set_offset) compare_int3v_eps(exp_v, ret_v, 64); /* Accelerometer offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_ACC_EN, NULL); + BMI160_OFFSET_ACC_EN, + NULL); /* Setup rotation and rotate input for set_offset function */ ms->rot_standard_ref = &test_rotation; @@ -326,7 +323,8 @@ ZTEST_USER(bmi160, test_bmi_acc_set_offset) compare_int3v_eps(exp_v, ret_v, 64); /* Accelerometer offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_ACC_EN, NULL); + BMI160_OFFSET_ACC_EN, + NULL); } /** @@ -384,7 +382,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_offset) compare_int3v(exp_v, ret_v); /* Gyroscope offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_GYRO_EN, NULL); + BMI160_OFFSET_GYRO_EN, + NULL); /* Setup rotation and rotate input for set_offset function */ ms->rot_standard_ref = &test_rotation; @@ -397,7 +396,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_set_offset) get_emul_gyr_offset(emul, ret_v); compare_int3v(exp_v, ret_v); zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_GYRO_EN, NULL); + BMI160_OFFSET_GYRO_EN, + NULL); } /** @@ -414,8 +414,8 @@ static void check_set_acc_range_f(struct i2c_emul *emul, zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd), "set_range failed; line: %d", line); zassert_equal(exp_range, ms->current_range, - "Expected range %d, got %d; line %d", - exp_range, ms->current_range, line); + "Expected range %d, got %d; line %d", exp_range, + ms->current_range, line); range_reg = bmi_emul_get_reg(emul, BMI160_ACC_RANGE); switch (exp_range) { @@ -443,7 +443,7 @@ static void check_set_acc_range_f(struct i2c_emul *emul, "Expected range reg 0x%x, got 0x%x; line %d", exp_range_reg, range_reg, line); } -#define check_set_acc_range(emul, ms, range, rnd, exp_range) \ +#define check_set_acc_range(emul, ms, range, rnd, exp_range) \ check_set_acc_range_f(emul, ms, range, rnd, exp_range, __LINE__) /** Test set accelerometer range with and without I2C errors */ @@ -466,12 +466,12 @@ ZTEST_USER(bmi160, test_bmi_acc_set_range) /* Test fail on write */ zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 0), NULL); zassert_equal(start_range, ms->current_range, NULL); - zassert_equal(BMI160_GSEL_2G, - bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL); + zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE), + NULL); zassert_equal(EC_ERROR_INVAL, ms->drv->set_range(ms, 12, 1), NULL); zassert_equal(start_range, ms->current_range, NULL); - zassert_equal(BMI160_GSEL_2G, - bmi_emul_get_reg(emul, BMI160_ACC_RANGE), NULL); + zassert_equal(BMI160_GSEL_2G, bmi_emul_get_reg(emul, BMI160_ACC_RANGE), + NULL); /* Do not fail on write */ i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -519,8 +519,8 @@ static void check_set_gyr_range_f(struct i2c_emul *emul, zassert_equal(EC_SUCCESS, ms->drv->set_range(ms, range, rnd), "set_range failed; line: %d", line); zassert_equal(exp_range, ms->current_range, - "Expected range %d, got %d; line %d", - exp_range, ms->current_range, line); + "Expected range %d, got %d; line %d", exp_range, + ms->current_range, line); range_reg = bmi_emul_get_reg(emul, BMI160_GYR_RANGE); switch (exp_range) { @@ -551,7 +551,7 @@ static void check_set_gyr_range_f(struct i2c_emul *emul, "Expected range reg 0x%x, got 0x%x; line %d", exp_range_reg, range_reg, line); } -#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \ +#define check_set_gyr_range(emul, ms, range, rnd, exp_range) \ check_set_gyr_range_f(emul, ms, range, rnd, exp_range, __LINE__) /** Test set gyroscope range with and without I2C errors */ @@ -693,10 +693,10 @@ static void check_set_acc_rate_f(struct i2c_emul *emul, } zassert_equal(exp_rate_reg, rate_reg, - "Expected rate reg 0x%x, got 0x%x; line %d", - exp_rate_reg, rate_reg, line); + "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg, + rate_reg, line); } -#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \ +#define check_set_acc_rate(emul, ms, rate, rnd, exp_rate) \ check_set_acc_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__) /** Test set and get accelerometer rate with and without I2C errors */ @@ -750,8 +750,8 @@ ZTEST_USER(bmi160, test_bmi_acc_rate) check_set_acc_rate(emul, ms, 200000, 1, 200000); /* Test out of range rate with rounding down */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 0), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 12499, 0), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -760,10 +760,10 @@ ZTEST_USER(bmi160, test_bmi_acc_rate) ms->drv->set_data_rate(ms, 2000000, 0), NULL); /* Test out of range rate with rounding up */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 1), NULL); - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 6250, 1), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1), + NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 6250, 1), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 200001, 1), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -882,10 +882,10 @@ static void check_set_gyr_rate_f(struct i2c_emul *emul, } zassert_equal(exp_rate_reg, rate_reg, - "Expected rate reg 0x%x, got 0x%x; line %d", - exp_rate_reg, rate_reg, line); + "Expected rate reg 0x%x, got 0x%x; line %d", exp_rate_reg, + rate_reg, line); } -#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \ +#define check_set_gyr_rate(emul, ms, rate, rnd, exp_rate) \ check_set_gyr_rate_f(emul, ms, rate, rnd, exp_rate, __LINE__) /** Test set and get gyroscope rate with and without I2C errors */ @@ -933,8 +933,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate) check_set_gyr_rate(emul, ms, 200000, 1, 200000); /* Test out of range rate with rounding down */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 0), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 0), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 24999, 0), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -943,8 +943,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_rate) ms->drv->set_data_rate(ms, 4000000, 0), NULL); /* Test out of range rate with rounding up */ - zassert_equal(EC_RES_INVALID_PARAM, - ms->drv->set_data_rate(ms, 1, 1), NULL); + zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 1, 1), + NULL); zassert_equal(EC_RES_INVALID_PARAM, ms->drv->set_data_rate(ms, 12499, 1), NULL); zassert_equal(EC_RES_INVALID_PARAM, @@ -1019,7 +1019,7 @@ ZTEST_USER(bmi160, test_bmi_scale) { struct motion_sensor_t *ms; int16_t ret_scale[3]; - int16_t exp_scale[3] = {100, 231, 421}; + int16_t exp_scale[3] = { 100, 231, 421 }; int16_t t; /* Test accelerometer */ @@ -1131,9 +1131,9 @@ ZTEST_USER(bmi160, test_bmi_acc_read) struct i2c_emul *emul; intv3_t ret_v; intv3_t exp_v; - int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE}; + int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE }; emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_ACC_SENSOR_ID]; @@ -1239,9 +1239,9 @@ ZTEST_USER(bmi160, test_bmi_gyr_read) struct i2c_emul *emul; intv3_t ret_v; intv3_t exp_v; - int16_t scale[3] = {MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE, - MOTION_SENSE_DEFAULT_SCALE}; + int16_t scale[3] = { MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE, + MOTION_SENSE_DEFAULT_SCALE }; emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_GYR_SENSOR_ID]; @@ -1368,11 +1368,9 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib) intv3_t ret_off; int range; int rate; - mat33_fp_t rot = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} - }; + mat33_fp_t rot = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_ACC_SENSOR_ID]; @@ -1447,7 +1445,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib) compare_int3v_eps(exp_off, ret_off, 64); /* Acelerometer offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_ACC_EN, NULL); + BMI160_OFFSET_ACC_EN, + NULL); /* Enable rotation with negative value on Z axis */ ms->rot_standard_ref = &rot; @@ -1463,7 +1462,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib) compare_int3v_eps(exp_off, ret_off, 64); /* Acelerometer offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_ACC_EN, NULL); + BMI160_OFFSET_ACC_EN, + NULL); /* Set positive rotation on Z axis */ rot[2][2] = FLOAT_TO_FP(1); @@ -1479,7 +1479,8 @@ ZTEST_USER(bmi160, test_bmi_acc_perform_calib) compare_int3v_eps(exp_off, ret_off, 64); /* Acelerometer offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_ACC_EN, NULL); + BMI160_OFFSET_ACC_EN, + NULL); /* Disable rotation */ ms->rot_standard_ref = NULL; } @@ -1569,7 +1570,8 @@ ZTEST_USER(bmi160, test_bmi_gyr_perform_calib) compare_int3v_eps(exp_off, ret_off, 32); /* Gyroscope offset should be enabled */ zassert_true(bmi_emul_get_reg(emul, BMI160_OFFSET_EN_GYR98) & - BMI160_OFFSET_GYRO_EN, NULL); + BMI160_OFFSET_GYRO_EN, + NULL); } /** Test init function of BMI160 accelerometer and gyroscope sensors */ @@ -1622,9 +1624,8 @@ static int emul_fifo_func(struct i2c_emul *emul, int reg, uint8_t *val, */ static void check_fifo_f(struct motion_sensor_t *ms_acc, struct motion_sensor_t *ms_gyr, - struct bmi_emul_frame *frame, - int acc_range, int gyr_range, - int line) + struct bmi_emul_frame *frame, int acc_range, + int gyr_range, int line) { struct ec_response_motion_sensor_data vector; struct bmi_emul_frame *f_acc, *f_gyr; @@ -1705,7 +1706,7 @@ static void check_fifo_f(struct motion_sensor_t *ms_acc, zassert_is_null(f_gyr, "Not all gyroscope frames are read, line %d", line); } -#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \ +#define check_fifo(ms_acc, ms_gyr, frame, acc_range, gyr_range) \ check_fifo_f(ms_acc, ms_gyr, frame, acc_range, gyr_range, __LINE__) /** Test irq handler of accelerometer sensor */ -- cgit v1.2.1 From 5bfa4f12e631e021aa1b042f66db894f5ed0dff0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:32 -0600 Subject: chip/it83xx/adc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I326c38c94cfeed3cc9ecea0c13470ae6463ef74a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729165 Reviewed-by: Jeremy Bettis --- chip/it83xx/adc.c | 78 +++++++++++++++++++++++++++---------------------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 2839da5af2..991edafa90 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -17,7 +17,7 @@ #include "timer.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) /* Global variables */ static struct mutex adc_lock; @@ -26,42 +26,42 @@ static volatile task_id_t task_waiting; /* Data structure of ADC channel control registers. */ const struct adc_ctrl_t adc_ctrl_regs[] = { - {&IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL}, - {&IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL}, - {&IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL}, - {&IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL}, - {&IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL}, - {&IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL}, - {&IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL}, - {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL}, - {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL}, - {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL}, - {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL}, - {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL}, + { &IT83XX_ADC_VCH0CTL, &IT83XX_ADC_VCH0DATM, &IT83XX_ADC_VCH0DATL }, + { &IT83XX_ADC_VCH1CTL, &IT83XX_ADC_VCH1DATM, &IT83XX_ADC_VCH1DATL }, + { &IT83XX_ADC_VCH2CTL, &IT83XX_ADC_VCH2DATM, &IT83XX_ADC_VCH2DATL }, + { &IT83XX_ADC_VCH3CTL, &IT83XX_ADC_VCH3DATM, &IT83XX_ADC_VCH3DATL }, + { &IT83XX_ADC_VCH4CTL, &IT83XX_ADC_VCH4DATM, &IT83XX_ADC_VCH4DATL }, + { &IT83XX_ADC_VCH5CTL, &IT83XX_ADC_VCH5DATM, &IT83XX_ADC_VCH5DATL }, + { &IT83XX_ADC_VCH6CTL, &IT83XX_ADC_VCH6DATM, &IT83XX_ADC_VCH6DATL }, + { &IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL }, + { &IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL }, + { &IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL }, + { &IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL }, + { &IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL }, }; BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); #ifdef CONFIG_ADC_VOLTAGE_COMPARATOR -#define VCMP_ADC_CH_MASK_H BIT(3) -#define VCMP_ADC_CH_MASK_L 0x7 +#define VCMP_ADC_CH_MASK_H BIT(3) +#define VCMP_ADC_CH_MASK_L 0x7 /* 10-bits resolution */ -#define VCMP_RESOLUTION BIT(10) -#define VCMP_MAX_MVOLT 3000 +#define VCMP_RESOLUTION BIT(10) +#define VCMP_MAX_MVOLT 3000 /* Data structure of voltage comparator control registers. */ const struct vcmp_ctrl_t vcmp_ctrl_regs[] = { - {&IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM, - &IT83XX_ADC_CMP0THRDATL}, - {&IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM, - &IT83XX_ADC_CMP1THRDATL}, - {&IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM, - &IT83XX_ADC_CMP2THRDATL}, - {&IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM, - &IT83XX_ADC_CMP3THRDATL}, - {&IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM, - &IT83XX_ADC_CMP4THRDATL}, - {&IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM, - &IT83XX_ADC_CMP5THRDATL}, + { &IT83XX_ADC_VCMP0CTL, &IT83XX_ADC_VCMP0CSELM, &IT83XX_ADC_CMP0THRDATM, + &IT83XX_ADC_CMP0THRDATL }, + { &IT83XX_ADC_VCMP1CTL, &IT83XX_ADC_VCMP1CSELM, &IT83XX_ADC_CMP1THRDATM, + &IT83XX_ADC_CMP1THRDATL }, + { &IT83XX_ADC_VCMP2CTL, &IT83XX_ADC_VCMP2CSELM, &IT83XX_ADC_CMP2THRDATM, + &IT83XX_ADC_CMP2THRDATL }, + { &IT83XX_ADC_VCMP3CTL, &IT83XX_ADC_VCMP3CSELM, &IT83XX_ADC_CMP3THRDATM, + &IT83XX_ADC_CMP3THRDATL }, + { &IT83XX_ADC_VCMP4CTL, &IT83XX_ADC_VCMP4CSELM, &IT83XX_ADC_CMP4THRDATM, + &IT83XX_ADC_CMP4THRDATL }, + { &IT83XX_ADC_VCMP5CTL, &IT83XX_ADC_VCMP5CSELM, &IT83XX_ADC_CMP5THRDATM, + &IT83XX_ADC_CMP5THRDATL }, }; BUILD_ASSERT(ARRAY_SIZE(vcmp_ctrl_regs) == CHIP_VCMP_COUNT); #endif @@ -120,8 +120,8 @@ static void adc_disable_channel(int ch) static int adc_data_valid(enum chip_adc_channel adc_ch) { return (adc_ch <= CHIP_ADC_CH7) ? - (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) : - (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13))); + (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) : + (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13))); } int adc_read_channel(enum adc_channel ch) @@ -153,13 +153,13 @@ int adc_read_channel(enum adc_channel ch) * next read. */ atomic_clear_bits(task_get_event_bitmap(task_get_current()), - TASK_EVENT_ADC_DONE); + TASK_EVENT_ADC_DONE); /* data valid of adc channel[x] */ if (adc_data_valid(adc_ch)) { /* read adc raw data msb and lsb */ adc_raw_data = (*adc_ctrl_regs[adc_ch].adc_datm << 8) + - *adc_ctrl_regs[adc_ch].adc_datl; + *adc_ctrl_regs[adc_ch].adc_datl; /* W/C data valid flag */ if (adc_ch <= CHIP_ADC_CH7) @@ -168,15 +168,15 @@ int adc_read_channel(enum adc_channel ch) IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13)); mv = adc_raw_data * adc_channels[ch].factor_mul / - adc_channels[ch].factor_div + adc_channels[ch].shift; + adc_channels[ch].factor_div + + adc_channels[ch].shift; valid = 1; } if (!valid) { CPRINTS("ADC failed to read!!! (regs=%x, %x, ch=%d, evt=%x)", - IT83XX_ADC_ADCDVSTS, - IT83XX_ADC_ADCDVSTS2, - adc_ch, events); + IT83XX_ADC_ADCDVSTS, IT83XX_ADC_ADCDVSTS2, adc_ch, + events); } adc_disable_channel(adc_ch); @@ -292,8 +292,8 @@ static void voltage_comparator_init(void) */ /* Select which ADC channel output voltage into comparator */ - *vcmp_ctrl_regs[idx].vcmp_ctrl |= - vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_L; + *vcmp_ctrl_regs[idx].vcmp_ctrl |= vcmp_list[idx].adc_ch & + VCMP_ADC_CH_MASK_L; if (vcmp_list[idx].adc_ch & VCMP_ADC_CH_MASK_H) *vcmp_ctrl_regs[idx].vcmp_adc_chm |= ADC_VCMP_VCMPCSELM; -- cgit v1.2.1 From 5042ee7c654ded9ba8b099dad8fa9a5cc0f7f075 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:44 -0600 Subject: board/gooey/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib44b268622f24ff5edef94e16c9b3d79a61c97dd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728426 Reviewed-by: Jeremy Bettis --- board/gooey/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/gooey/usb_pd_policy.c b/board/gooey/usb_pd_policy.c index b7c0ca21df..814287a417 100644 --- a/board/gooey/usb_pd_policy.c +++ b/board/gooey/usb_pd_policy.c @@ -13,8 +13,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From dd816a11c94d178e1a0ce228fd273bdb728b7a30 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:32:30 -0600 Subject: zephyr/projects/intelrvp/src/intel_rvp_led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icfe5f3d7a3bd34db493e8c1a6ef90d229062ec2c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730779 Reviewed-by: Jeremy Bettis --- zephyr/projects/intelrvp/src/intel_rvp_led.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/projects/intelrvp/src/intel_rvp_led.c b/zephyr/projects/intelrvp/src/intel_rvp_led.c index b382dcc485..0ef5b01fcd 100644 --- a/zephyr/projects/intelrvp/src/intel_rvp_led.c +++ b/zephyr/projects/intelrvp/src/intel_rvp_led.c @@ -26,8 +26,8 @@ #define LED_PULSE_TICK (125 * MSEC) -#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */ -#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec */ +#define LED_FAST_PULSE_PERIOD (250 / 125) /* 250 ms */ +#define LED_SLOW_PULSE_PERIOD ((2 * MSEC) / 125) /* 2 sec */ struct led_pulse_data { bool led_is_pulsing; @@ -56,13 +56,13 @@ static void pulse_led_deferred(void) * and in OFF state in second half of the pulse period. */ if (rvp_led[i].led_tick_count < - (rvp_led[i].led_pulse_period >> 1)) + (rvp_led[i].led_pulse_period >> 1)) set_pwm_led_color(i, EC_LED_COLOR_GREEN); else set_pwm_led_color(i, LED_OFF); rvp_led[i].led_tick_count = (rvp_led[i].led_tick_count + 1) % - rvp_led[i].led_pulse_period; + rvp_led[i].led_pulse_period; call_deferred = true; } @@ -73,7 +73,7 @@ static void pulse_led_deferred(void) static void pulse_leds(enum pwm_led_id id, int period) { rvp_led[id].led_pulse_period = period; - rvp_led[id].led_is_pulsing = true; + rvp_led[id].led_is_pulsing = true; pulse_led_deferred(); } @@ -96,7 +96,7 @@ static void update_charger_led(enum pwm_led_id id) rvp_led[id].led_is_pulsing = false; set_pwm_led_color(id, EC_LED_COLOR_GREEN); } else if (chg_st == PWR_STATE_DISCHARGE || - chg_st == PWR_STATE_DISCHARGE_FULL) { + chg_st == PWR_STATE_DISCHARGE_FULL) { if (extpower_is_present()) { /* Discharging: * Flash slower (2 second period, 100% duty cycle) -- cgit v1.2.1 From 92297806bf815a4a80c9a52d8cadc4ee7835452c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:55 -0600 Subject: chip/it83xx/ec2i_chip.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d570bf36aa1a31d873d94574f20b1f2c2e985a0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729208 Reviewed-by: Jeremy Bettis --- chip/it83xx/ec2i_chip.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/chip/it83xx/ec2i_chip.h b/chip/it83xx/ec2i_chip.h index c8069f4ff5..248b3bdcae 100644 --- a/chip/it83xx/ec2i_chip.h +++ b/chip/it83xx/ec2i_chip.h @@ -8,9 +8,9 @@ #ifndef __CROS_EC_EC2I_CHIP_H #define __CROS_EC_EC2I_CHIP_H -#define P80L_P80LB 0 -#define P80L_P80LE 0x3F -#define P80L_P80LC 0 +#define P80L_P80LB 0 +#define P80L_P80LE 0x3F +#define P80L_P80LC 0 #define P80L_BRAM_BANK1_SIZE_MASK 0x3F /* Index list of the host interface registers of PNPCFG */ -- cgit v1.2.1 From e84c1fe8b8c752d0ba9eccce20202696f4f2862c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:46 -0600 Subject: zephyr/shim/chip/npcx/npcx_monitor/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib560e661f0a112f18e8abda7edd80b28f53d7c19 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728333 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/npcx_monitor/registers.h | 504 ++++++++++++------------- 1 file changed, 252 insertions(+), 252 deletions(-) diff --git a/zephyr/shim/chip/npcx/npcx_monitor/registers.h b/zephyr/shim/chip/npcx/npcx_monitor/registers.h index cc0a6b96fe..a52ba34349 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/registers.h +++ b/zephyr/shim/chip/npcx/npcx_monitor/registers.h @@ -21,32 +21,32 @@ #define REG64_ADDR(addr) ((volatile uint64_t *)(addr)) #define REG32_ADDR(addr) ((volatile uint32_t *)(addr)) #define REG16_ADDR(addr) ((volatile uint16_t *)(addr)) -#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) +#define REG8_ADDR(addr) ((volatile uint8_t *)(addr)) #define REG64(addr) (*REG64_ADDR(addr)) #define REG32(addr) (*REG32_ADDR(addr)) #define REG16(addr) (*REG16_ADDR(addr)) -#define REG8(addr) (*REG8_ADDR(addr)) +#define REG8(addr) (*REG8_ADDR(addr)) /* Standard macros / definitions */ #define GENERIC_MAX(x, y) ((x) > (y) ? (x) : (y)) #define GENERIC_MIN(x, y) ((x) < (y) ? (x) : (y)) #ifndef MAX -#define MAX(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MAX(temp_a, temp_b); \ +#define MAX(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MAX(temp_a, temp_b); \ }) #endif #ifndef MIN -#define MIN(a, b) \ - ({ \ - __typeof__(a) temp_a = (a); \ - __typeof__(b) temp_b = (b); \ - \ - GENERIC_MIN(temp_a, temp_b); \ +#define MIN(a, b) \ + ({ \ + __typeof__(a) temp_a = (a); \ + __typeof__(b) temp_b = (b); \ + \ + GENERIC_MIN(temp_a, temp_b); \ }) #endif #ifndef NULL @@ -58,32 +58,35 @@ * Macro Functions */ /* Bit functions */ -#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) -#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) -#define UPDATE_BIT(reg, bit, cond) { if (cond) \ - SET_BIT(reg, bit); \ - else \ - CLEAR_BIT(reg, bit); } +#define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) +#define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) +#define UPDATE_BIT(reg, bit, cond) \ + { \ + if (cond) \ + SET_BIT(reg, bit); \ + else \ + CLEAR_BIT(reg, bit); \ + } /* Field functions */ -#define GET_POS_FIELD(pos, size) pos -#define GET_SIZE_FIELD(pos, size) size -#define FIELD_POS(field) GET_POS_##field -#define FIELD_SIZE(field) GET_SIZE_##field +#define GET_POS_FIELD(pos, size) pos +#define GET_SIZE_FIELD(pos, size) size +#define FIELD_POS(field) GET_POS_##field +#define FIELD_SIZE(field) GET_SIZE_##field /* Read field functions */ #define GET_FIELD(reg, field) \ _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) -#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) +#define _GET_FIELD_(reg, f_pos, f_size) \ + (((reg) >> (f_pos)) & ((1 << (f_size)) - 1)) /* Write field functions */ #define SET_FIELD(reg, field, value) \ _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) -#define _SET_FIELD_(reg, f_pos, f_size, value) \ - ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ - | ((value) << (f_pos))) - +#define _SET_FIELD_(reg, f_pos, f_size, value) \ + ((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | \ + ((value) << (f_pos))) /* NPCX7 & NPCX9 */ -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) +#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) /******************************************************************************/ /* @@ -91,270 +94,267 @@ */ /* Modules Map */ -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_PMC_BASE_ADDR 0x4000D000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 -#define NPCX_SHM_BASE_ADDR 0x40010000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 -#define NPCX_FIU_BASE_ADDR 0x40020000 -#define NPCX_KBSCAN_REGS_BASE 0x400A3000 -#define NPCX_WOV_BASE_ADDR 0x400A4000 -#define NPCX_APM_BASE_ADDR 0x400A4800 -#define NPCX_GLUE_REGS_BASE 0x400A5000 -#define NPCX_BBRAM_BASE_ADDR 0x400AF000 -#define NPCX_PS2_BASE_ADDR 0x400B1000 -#define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_LFCG_BASE_ADDR 0x400B5100 -#define NPCX_FMUL2_BASE_ADDR 0x400B5200 -#define NPCX_MTC_BASE_ADDR 0x400B7000 -#define NPCX_MSWC_BASE_ADDR 0x400C1000 -#define NPCX_SCFG_BASE_ADDR 0x400C3000 -#define NPCX_KBC_BASE_ADDR 0x400C7000 -#define NPCX_ADC_BASE_ADDR 0x400D1000 -#define NPCX_SPI_BASE_ADDR 0x400D2000 -#define NPCX_PECI_BASE_ADDR 0x400D4000 -#define NPCX_TWD_BASE_ADDR 0x400D8000 +#define NPCX_ESPI_BASE_ADDR 0x4000A000 +#define NPCX_MDC_BASE_ADDR 0x4000C000 +#define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_SIB_BASE_ADDR 0x4000E000 +#define NPCX_SHI_BASE_ADDR 0x4000F000 +#define NPCX_SHM_BASE_ADDR 0x40010000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 +#define NPCX_FIU_BASE_ADDR 0x40020000 +#define NPCX_KBSCAN_REGS_BASE 0x400A3000 +#define NPCX_WOV_BASE_ADDR 0x400A4000 +#define NPCX_APM_BASE_ADDR 0x400A4800 +#define NPCX_GLUE_REGS_BASE 0x400A5000 +#define NPCX_BBRAM_BASE_ADDR 0x400AF000 +#define NPCX_PS2_BASE_ADDR 0x400B1000 +#define NPCX_HFCG_BASE_ADDR 0x400B5000 +#define NPCX_LFCG_BASE_ADDR 0x400B5100 +#define NPCX_FMUL2_BASE_ADDR 0x400B5200 +#define NPCX_MTC_BASE_ADDR 0x400B7000 +#define NPCX_MSWC_BASE_ADDR 0x400C1000 +#define NPCX_SCFG_BASE_ADDR 0x400C3000 +#define NPCX_KBC_BASE_ADDR 0x400C7000 +#define NPCX_ADC_BASE_ADDR 0x400D1000 +#define NPCX_SPI_BASE_ADDR 0x400D2000 +#define NPCX_PECI_BASE_ADDR 0x400D4000 +#define NPCX_TWD_BASE_ADDR 0x400D8000 /* Multi-Modules Map */ -#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) -#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) -#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) - +#define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl)*0x2000L)) +#define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl)*0x2000L)) +#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl)*0x2000L)) +#define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl)*0x2000L)) +#define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl)*0x2000L)) +#define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl)*0x2000L)) /******************************************************************************/ /* System Configuration (SCFG) Registers */ -#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) -#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) -#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) -#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) -#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) -#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) - -#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) -#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) -#define BLKSEL 0 +#define NPCX_DEVCNT REG8(NPCX_SCFG_BASE_ADDR + 0x000) +#define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) +#define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) +#define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) +#define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) +#define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) +#define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) +#define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) + +#define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) +#define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) +#define BLKSEL 0 /* SCFG register fields */ -#define NPCX_DEVCNT_F_SPI_TRIS 6 -#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) -#define NPCX_DEVCNT_JEN1_HEN 5 -#define NPCX_DEVCNT_JEN0_HEN 4 -#define NPCX_STRPST_TRIST 1 -#define NPCX_STRPST_TEST 2 -#define NPCX_STRPST_JEN1 4 -#define NPCX_STRPST_JEN0 5 -#define NPCX_STRPST_SPI_COMP 7 -#define NPCX_RSTCTL_VCC1_RST_STS 0 -#define NPCX_RSTCTL_DBGRST_STS 1 -#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 -#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 -#define NPCX_RSTCTL_HIPRST_MODE 6 -#define NPCX_DEV_CTL4_F_SPI_SLLK 2 -#define NPCX_DEV_CTL4_SPI_SP_SEL 4 -#define NPCX_DEV_CTL4_WP_IF 5 -#define NPCX_DEV_CTL4_VCC1_RST_LK 6 -#define NPCX_DEVPU0_I2C0_0_PUE 0 -#define NPCX_DEVPU0_I2C0_1_PUE 1 -#define NPCX_DEVPU0_I2C1_0_PUE 2 -#define NPCX_DEVPU0_I2C2_0_PUE 4 -#define NPCX_DEVPU0_I2C3_0_PUE 6 -#define NPCX_DEVPU1_F_SPI_PUD_EN 7 +#define NPCX_DEVCNT_F_SPI_TRIS 6 +#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) +#define NPCX_DEVCNT_JEN1_HEN 5 +#define NPCX_DEVCNT_JEN0_HEN 4 +#define NPCX_STRPST_TRIST 1 +#define NPCX_STRPST_TEST 2 +#define NPCX_STRPST_JEN1 4 +#define NPCX_STRPST_JEN0 5 +#define NPCX_STRPST_SPI_COMP 7 +#define NPCX_RSTCTL_VCC1_RST_STS 0 +#define NPCX_RSTCTL_DBGRST_STS 1 +#define NPCX_RSTCTL_VCC1_RST_SCRATCH 3 +#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5 +#define NPCX_RSTCTL_HIPRST_MODE 6 +#define NPCX_DEV_CTL4_F_SPI_SLLK 2 +#define NPCX_DEV_CTL4_SPI_SP_SEL 4 +#define NPCX_DEV_CTL4_WP_IF 5 +#define NPCX_DEV_CTL4_VCC1_RST_LK 6 +#define NPCX_DEVPU0_I2C0_0_PUE 0 +#define NPCX_DEVPU0_I2C0_1_PUE 1 +#define NPCX_DEVPU0_I2C1_0_PUE 2 +#define NPCX_DEVPU0_I2C2_0_PUE 4 +#define NPCX_DEVPU0_I2C3_0_PUE 6 +#define NPCX_DEVPU1_F_SPI_PUD_EN 7 /* DEVALT */ /* pin-mux for SPI/FIU */ -#define NPCX_DEVALT0_SPIP_SL 0 -#define NPCX_DEVALT0_GPIO_NO_SPIP 3 -#define NPCX_DEVALT0_F_SPI_CS1_2 4 -#define NPCX_DEVALT0_F_SPI_CS1_1 5 -#define NPCX_DEVALT0_F_SPI_QUAD 6 -#define NPCX_DEVALT0_NO_F_SPI 7 +#define NPCX_DEVALT0_SPIP_SL 0 +#define NPCX_DEVALT0_GPIO_NO_SPIP 3 +#define NPCX_DEVALT0_F_SPI_CS1_2 4 +#define NPCX_DEVALT0_F_SPI_CS1_1 5 +#define NPCX_DEVALT0_F_SPI_QUAD 6 +#define NPCX_DEVALT0_NO_F_SPI 7 /******************************************************************************/ /* Flash Interface Unit (FIU) Registers */ -#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) -#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) -#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) -#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) -#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) -#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) -#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) -#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) -#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) -#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) -#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) -#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) -#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) -#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) -#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) -#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) -#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) -#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) -#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) +#define NPCX_FIU_CFG REG8(NPCX_FIU_BASE_ADDR + 0x000) +#define NPCX_BURST_CFG REG8(NPCX_FIU_BASE_ADDR + 0x001) +#define NPCX_RESP_CFG REG8(NPCX_FIU_BASE_ADDR + 0x002) +#define NPCX_SPI_FL_CFG REG8(NPCX_FIU_BASE_ADDR + 0x014) +#define NPCX_UMA_CODE REG8(NPCX_FIU_BASE_ADDR + 0x016) +#define NPCX_UMA_AB0 REG8(NPCX_FIU_BASE_ADDR + 0x017) +#define NPCX_UMA_AB1 REG8(NPCX_FIU_BASE_ADDR + 0x018) +#define NPCX_UMA_AB2 REG8(NPCX_FIU_BASE_ADDR + 0x019) +#define NPCX_UMA_DB0 REG8(NPCX_FIU_BASE_ADDR + 0x01A) +#define NPCX_UMA_DB1 REG8(NPCX_FIU_BASE_ADDR + 0x01B) +#define NPCX_UMA_DB2 REG8(NPCX_FIU_BASE_ADDR + 0x01C) +#define NPCX_UMA_DB3 REG8(NPCX_FIU_BASE_ADDR + 0x01D) +#define NPCX_UMA_CTS REG8(NPCX_FIU_BASE_ADDR + 0x01E) +#define NPCX_UMA_ECTS REG8(NPCX_FIU_BASE_ADDR + 0x01F) +#define NPCX_UMA_DB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x020) +#define NPCX_FIU_RD_CMD REG8(NPCX_FIU_BASE_ADDR + 0x030) +#define NPCX_FIU_DMM_CYC REG8(NPCX_FIU_BASE_ADDR + 0x032) +#define NPCX_FIU_EXT_CFG REG8(NPCX_FIU_BASE_ADDR + 0x033) +#define NPCX_FIU_UMA_AB0_3 REG32(NPCX_FIU_BASE_ADDR + 0x034) /* FIU register fields */ -#define NPCX_RESP_CFG_IAD_EN 0 -#define NPCX_RESP_CFG_DEV_SIZE_EX 2 -#define NPCX_UMA_CTS_A_SIZE 3 -#define NPCX_UMA_CTS_C_SIZE 4 -#define NPCX_UMA_CTS_RD_WR 5 -#define NPCX_UMA_CTS_DEV_NUM 6 -#define NPCX_UMA_CTS_EXEC_DONE 7 -#define NPCX_UMA_ECTS_SW_CS0 0 -#define NPCX_UMA_ECTS_SW_CS1 1 -#define NPCX_UMA_ECTS_SEC_CS 2 -#define NPCX_UMA_ECTS_UMA_LOCK 3 +#define NPCX_RESP_CFG_IAD_EN 0 +#define NPCX_RESP_CFG_DEV_SIZE_EX 2 +#define NPCX_UMA_CTS_A_SIZE 3 +#define NPCX_UMA_CTS_C_SIZE 4 +#define NPCX_UMA_CTS_RD_WR 5 +#define NPCX_UMA_CTS_DEV_NUM 6 +#define NPCX_UMA_CTS_EXEC_DONE 7 +#define NPCX_UMA_ECTS_SW_CS0 0 +#define NPCX_UMA_ECTS_SW_CS1 1 +#define NPCX_UMA_ECTS_SEC_CS 2 +#define NPCX_UMA_ECTS_UMA_LOCK 3 /******************************************************************************/ /* KBC Registers */ -#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) -#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) -#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) -#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) -#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) -#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) -#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) -#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) +#define NPCX_HICTRL REG8(NPCX_KBC_BASE_ADDR + 0x000) +#define NPCX_HIIRQC REG8(NPCX_KBC_BASE_ADDR + 0x002) +#define NPCX_HIKMST REG8(NPCX_KBC_BASE_ADDR + 0x004) +#define NPCX_HIKDO REG8(NPCX_KBC_BASE_ADDR + 0x006) +#define NPCX_HIMDO REG8(NPCX_KBC_BASE_ADDR + 0x008) +#define NPCX_KBCVER REG8(NPCX_KBC_BASE_ADDR + 0x009) +#define NPCX_HIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00A) +#define NPCX_SHIKMDI REG8(NPCX_KBC_BASE_ADDR + 0x00B) /* KBC register field */ -#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ -#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ -#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ -#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ -#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ -#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ -#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ -#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ +#define NPCX_HICTRL_OBFKIE 0 /* Automatic Serial IRQ1 for KBC */ +#define NPCX_HICTRL_OBFMIE 1 /* Automatic Serial IRQ12 for Mouse*/ +#define NPCX_HICTRL_OBECIE 2 /* KBC OBE interrupt enable */ +#define NPCX_HICTRL_IBFCIE 3 /* KBC IBF interrupt enable */ +#define NPCX_HICTRL_PMIHIE 4 /* Automatic Serial IRQ11 for PMC1 */ +#define NPCX_HICTRL_PMIOCIE 5 /* PMC1 OBE interrupt enable */ +#define NPCX_HICTRL_PMICIE 6 /* PMC1 IBF interrupt enable */ +#define NPCX_HICTRL_FW_OBF 7 /* Firmware control over OBF */ -#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ +#define NPCX_HIKMST_OBF 0 /* KB output buffer is full */ /******************************************************************************/ /* Timer Watch Dog (TWD) Registers */ -#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) -#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) -#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) -#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) -#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) -#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) -#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) -#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) -#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) +#define NPCX_TWCFG REG8(NPCX_TWD_BASE_ADDR + 0x000) +#define NPCX_TWCP REG8(NPCX_TWD_BASE_ADDR + 0x002) +#define NPCX_TWDT0 REG16(NPCX_TWD_BASE_ADDR + 0x004) +#define NPCX_T0CSR REG8(NPCX_TWD_BASE_ADDR + 0x006) +#define NPCX_WDCNT REG8(NPCX_TWD_BASE_ADDR + 0x008) +#define NPCX_WDSDM REG8(NPCX_TWD_BASE_ADDR + 0x00A) +#define NPCX_TWMT0 REG16(NPCX_TWD_BASE_ADDR + 0x00C) +#define NPCX_TWMWD REG8(NPCX_TWD_BASE_ADDR + 0x00E) +#define NPCX_WDCP REG8(NPCX_TWD_BASE_ADDR + 0x010) /* TWD register fields */ -#define NPCX_TWCFG_LTWCFG 0 -#define NPCX_TWCFG_LTWCP 1 -#define NPCX_TWCFG_LTWDT0 2 -#define NPCX_TWCFG_LWDCNT 3 -#define NPCX_TWCFG_WDCT0I 4 -#define NPCX_TWCFG_WDSDME 5 -#define NPCX_TWCFG_WDRST_MODE 6 -#define NPCX_TWCFG_WDC2POR 7 -#define NPCX_T0CSR_RST 0 -#define NPCX_T0CSR_TC 1 -#define NPCX_T0CSR_WDLTD 3 -#define NPCX_T0CSR_WDRST_STS 4 -#define NPCX_T0CSR_WD_RUN 5 -#define NPCX_T0CSR_TESDIS 7 +#define NPCX_TWCFG_LTWCFG 0 +#define NPCX_TWCFG_LTWCP 1 +#define NPCX_TWCFG_LTWDT0 2 +#define NPCX_TWCFG_LWDCNT 3 +#define NPCX_TWCFG_WDCT0I 4 +#define NPCX_TWCFG_WDSDME 5 +#define NPCX_TWCFG_WDRST_MODE 6 +#define NPCX_TWCFG_WDC2POR 7 +#define NPCX_T0CSR_RST 0 +#define NPCX_T0CSR_TC 1 +#define NPCX_T0CSR_WDLTD 3 +#define NPCX_T0CSR_WDRST_STS 4 +#define NPCX_T0CSR_WD_RUN 5 +#define NPCX_T0CSR_TESDIS 7 /******************************************************************************/ /* SPI Register */ -#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) -#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) -#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) +#define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) +#define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) +#define NPCX_SPI_STAT REG8(NPCX_SPI_BASE_ADDR + 0x04) /* SPI register fields */ -#define NPCX_SPI_CTL1_SPIEN 0 -#define NPCX_SPI_CTL1_SNM 1 -#define NPCX_SPI_CTL1_MOD 2 -#define NPCX_SPI_CTL1_EIR 5 -#define NPCX_SPI_CTL1_EIW 6 -#define NPCX_SPI_CTL1_SCM 7 -#define NPCX_SPI_CTL1_SCIDL 8 -#define NPCX_SPI_CTL1_SCDV 9 -#define NPCX_SPI_STAT_BSY 0 -#define NPCX_SPI_STAT_RBF 1 +#define NPCX_SPI_CTL1_SPIEN 0 +#define NPCX_SPI_CTL1_SNM 1 +#define NPCX_SPI_CTL1_MOD 2 +#define NPCX_SPI_CTL1_EIR 5 +#define NPCX_SPI_CTL1_EIW 6 +#define NPCX_SPI_CTL1_SCM 7 +#define NPCX_SPI_CTL1_SCIDL 8 +#define NPCX_SPI_CTL1_SCDV 9 +#define NPCX_SPI_STAT_BSY 0 +#define NPCX_SPI_STAT_RBF 1 /******************************************************************************/ /* Flash Utiltiy definition */ /* * Flash commands for the W25Q16CV SPI flash */ -#define CMD_READ_ID 0x9F -#define CMD_READ_MAN_DEV_ID 0x90 -#define CMD_WRITE_EN 0x06 -#define CMD_WRITE_STATUS 0x50 -#define CMD_READ_STATUS_REG 0x05 -#define CMD_READ_STATUS_REG2 0x35 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_FLASH_PROGRAM 0x02 -#define CMD_SECTOR_ERASE 0x20 -#define CMD_BLOCK_32K_ERASE 0x52 -#define CMD_BLOCK_64K_ERASE 0xd8 -#define CMD_PROGRAM_UINT_SIZE 0x08 -#define CMD_PAGE_SIZE 0x00 -#define CMD_READ_ID_TYPE 0x47 -#define CMD_FAST_READ 0x0B +#define CMD_READ_ID 0x9F +#define CMD_READ_MAN_DEV_ID 0x90 +#define CMD_WRITE_EN 0x06 +#define CMD_WRITE_STATUS 0x50 +#define CMD_READ_STATUS_REG 0x05 +#define CMD_READ_STATUS_REG2 0x35 +#define CMD_WRITE_STATUS_REG 0x01 +#define CMD_FLASH_PROGRAM 0x02 +#define CMD_SECTOR_ERASE 0x20 +#define CMD_BLOCK_32K_ERASE 0x52 +#define CMD_BLOCK_64K_ERASE 0xd8 +#define CMD_PROGRAM_UINT_SIZE 0x08 +#define CMD_PAGE_SIZE 0x00 +#define CMD_READ_ID_TYPE 0x47 +#define CMD_FAST_READ 0x0B /* * Status registers for the W25Q16CV SPI flash */ -#define SPI_FLASH_SR2_SUS BIT(7) -#define SPI_FLASH_SR2_CMP BIT(6) -#define SPI_FLASH_SR2_LB3 BIT(5) -#define SPI_FLASH_SR2_LB2 BIT(4) -#define SPI_FLASH_SR2_LB1 BIT(3) -#define SPI_FLASH_SR2_QE BIT(1) -#define SPI_FLASH_SR2_SRP1 BIT(0) -#define SPI_FLASH_SR1_SRP0 BIT(7) -#define SPI_FLASH_SR1_SEC BIT(6) -#define SPI_FLASH_SR1_TB BIT(5) -#define SPI_FLASH_SR1_BP2 BIT(4) -#define SPI_FLASH_SR1_BP1 BIT(3) -#define SPI_FLASH_SR1_BP0 BIT(2) -#define SPI_FLASH_SR1_WEL BIT(1) -#define SPI_FLASH_SR1_BUSY BIT(0) - +#define SPI_FLASH_SR2_SUS BIT(7) +#define SPI_FLASH_SR2_CMP BIT(6) +#define SPI_FLASH_SR2_LB3 BIT(5) +#define SPI_FLASH_SR2_LB2 BIT(4) +#define SPI_FLASH_SR2_LB1 BIT(3) +#define SPI_FLASH_SR2_QE BIT(1) +#define SPI_FLASH_SR2_SRP1 BIT(0) +#define SPI_FLASH_SR1_SRP0 BIT(7) +#define SPI_FLASH_SR1_SEC BIT(6) +#define SPI_FLASH_SR1_TB BIT(5) +#define SPI_FLASH_SR1_BP2 BIT(4) +#define SPI_FLASH_SR1_BP1 BIT(3) +#define SPI_FLASH_SR1_BP0 BIT(2) +#define SPI_FLASH_SR1_WEL BIT(1) +#define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ -#define FIU_CHIP_SELECT 0 +#define FIU_CHIP_SELECT 0 /* Create UMA control mask */ -#define MASK(bit) (0x1 << (bit)) -#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ -#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ -#define RD_WR 0x05 /* 0: Read 1: Write */ -#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ -#define EXEC_DONE 0x07 -#define D_SIZE_1 0x01 -#define D_SIZE_2 0x02 -#define D_SIZE_3 0x03 -#define D_SIZE_4 0x04 -#define FLASH_SEL MASK(DEV_NUM) - -#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) -#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) -#define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - |MASK(A_SIZE) | D_SIZE_1) -#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) -#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) -#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) -#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) -#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) -#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) -#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) -#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) -#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) -#define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_1) -#define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(C_SIZE) | D_SIZE_2) -#define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ - | MASK(A_SIZE)) - +#define MASK(bit) (0x1 << (bit)) +#define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ +#define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ +#define RD_WR 0x05 /* 0: Read 1: Write */ +#define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ +#define EXEC_DONE 0x07 +#define D_SIZE_1 0x01 +#define D_SIZE_2 0x02 +#define D_SIZE_3 0x03 +#define D_SIZE_4 0x04 +#define FLASH_SEL MASK(DEV_NUM) + +#define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) +#define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) +#define MASK_CMD_ADR_WR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE) | D_SIZE_1) +#define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) +#define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) +#define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) +#define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) +#define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) +#define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) +#define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) +#define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) +#define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) +#define MASK_CMD_WR_1BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_1) +#define MASK_CMD_WR_2BYTE \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(C_SIZE) | D_SIZE_2) +#define MASK_CMD_WR_ADR \ + (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) | MASK(A_SIZE)) #endif /* __CROS_EC_REGISTERS_H */ -- cgit v1.2.1 From ba1b078a15365d3db357af9049182c94dcc81447 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:05 -0600 Subject: board/felwinter/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib4d685fd7f1d48d4438e2b035062ec2980cbeb81 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728355 Reviewed-by: Jeremy Bettis --- board/felwinter/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/felwinter/fans.c b/board/felwinter/fans.c index 636364a6de..dad20e180d 100644 --- a/board/felwinter/fans.c +++ b/board/felwinter/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From f7341c2b37085975816314573f57e3c65a8927a9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:40 -0600 Subject: chip/stm32/adc-stm32l4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2fc40b0b91c615f4c49c024f4bcfdcbef707c684 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729454 Reviewed-by: Jeremy Bettis --- chip/stm32/adc-stm32l4.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c index 8609d44f5d..f8d52f939e 100644 --- a/chip/stm32/adc-stm32l4.c +++ b/chip/stm32/adc-stm32l4.c @@ -21,7 +21,7 @@ struct adc_profile_t { /* Register values. */ uint32_t cfgr1_reg; uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ + uint32_t smpr_reg; /* Default Sampling Rate */ uint32_t ier_reg; /* DMA config. */ const struct dma_option *dma_option; @@ -36,11 +36,11 @@ struct adc_profile_t { #endif #if defined(CHIP_FAMILY_STM32L4) -#define ADC_CALIBRATION_TIMEOUT_US 100000U -#define ADC_ENABLE_TIMEOUT_US 200000U -#define ADC_CONVERSION_TIMEOUT_US 200000U +#define ADC_CALIBRATION_TIMEOUT_US 100000U +#define ADC_ENABLE_TIMEOUT_US 200000U +#define ADC_CONVERSION_TIMEOUT_US 200000U -#define NUMBER_OF_ADC_CHANNEL 2 +#define NUMBER_OF_ADC_CHANNEL 2 uint8_t adc1_initialized; #endif @@ -51,15 +51,15 @@ uint8_t adc1_initialized; #endif static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, + STM32_DMA_CCR_CIRC, }; static const struct adc_profile_t profile = { /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT | STM32_ADC_CFGR1_DMACFG, .cfgr2_reg = 0, .smpr_reg = CONFIG_ADC_SAMPLE_TIME, @@ -87,7 +87,7 @@ static void adc_init(const struct adc_t *adc) /* set ADC clock to 20MHz */ STM32_ADC1_CCR &= ~0x003C0000; - STM32_ADC1_CCR |= 0x00080000; + STM32_ADC1_CCR |= 0x00080000; STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOA; STM32_RCC_AHB2ENR |= STM32_RCC_HB2_GPIOB; @@ -101,13 +101,13 @@ static void adc_init(const struct adc_t *adc) } static void adc_configure(int ain_id, int ain_rank, - enum stm32_adc_smpr sample_rate) + enum stm32_adc_smpr sample_rate) { /* Select Sampling time and channel to convert */ - if (ain_id <= 10) { + if (ain_id <= 10) { STM32_ADC1_SMPR1 &= ~(7 << ((ain_id - 1) * 3)); STM32_ADC1_SMPR1 |= (sample_rate << ((ain_id - 1) * 3)); - } else { + } else { STM32_ADC1_SMPR2 &= ~(7 << ((ain_id - 11) * 3)); STM32_ADC1_SMPR2 |= (sample_rate << ((ain_id - 11) * 3)); } @@ -172,7 +172,8 @@ int adc_read_channel(enum adc_channel ch) /* wait for the end of calibration */ wait_loop_index = ((ADC_CALIBRATION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + (CPU_CLOCK / (100000 * 2))) / + 10); while (STM32_ADC1_CR & STM32_ADC1_CR_ADCAL) { if (wait_loop_index-- == 0) break; @@ -181,8 +182,9 @@ int adc_read_channel(enum adc_channel ch) /* Enable ADC */ STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY; STM32_ADC1_CR |= STM32_ADC1_CR_ADEN; - wait_loop_index = ((ADC_ENABLE_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + wait_loop_index = + ((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / + 10); while (!(STM32_ADC1_ISR & STM32_ADC1_ISR_ADRDY)) { wait_loop_index--; if (wait_loop_index == 0) @@ -196,8 +198,8 @@ int adc_read_channel(enum adc_channel ch) STM32_ADC1_CR |= BIT(3); /* JADSTART */ /* Wait for end of injected conversion */ - wait_loop_index = ((ADC_CONVERSION_TIMEOUT_US * - (CPU_CLOCK / (100000 * 2))) / 10); + wait_loop_index = + ((ADC_CONVERSION_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / 10); while (!(STM32_ADC1_ISR & BIT(6))) { if (wait_loop_index-- == 0) break; -- cgit v1.2.1 From b3d34a9203f82782bd4a60b4ade00005a52fd031 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:34:26 -0600 Subject: board/felwinter/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53a57de7bc0821b7bd81f5dff8c3f4ceff561a34 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728361 Reviewed-by: Jeremy Bettis --- board/felwinter/usbc_config.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/board/felwinter/usbc_config.c b/board/felwinter/usbc_config.c index 3d39650ba8..f303dedf3d 100644 --- a/board/felwinter/usbc_config.c +++ b/board/felwinter/usbc_config.c @@ -33,8 +33,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) /* USBC TCPC configuration */ struct tcpc_config_t tcpc_config[] = { @@ -139,24 +139,23 @@ struct usb_mux usb_muxes[] = { BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); static const struct usb_mux usb_muxes_c1 = { - .usb_port = USBC_PORT_C1, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C1_MUX, - .i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR, - .next_mux = &usbc1_tcss_usb_mux, + .usb_port = USBC_PORT_C1, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C1_MUX, + .i2c_addr_flags = USBC_PORT_C1_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc1_tcss_usb_mux, }; static const struct usb_mux usb_muxes_c2 = { - .usb_port = USBC_PORT_C2, - .driver = &bb_usb_retimer, - .hpd_update = bb_retimer_hpd_update, - .i2c_port = I2C_PORT_USB_C2_MUX, - .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, - .next_mux = &usbc2_tcss_usb_mux, + .usb_port = USBC_PORT_C2, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C2_MUX, + .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + .next_mux = &usbc2_tcss_usb_mux, }; - /* BC1.2 charger detect configuration */ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { [USBC_PORT_C2] = { @@ -254,7 +253,6 @@ void board_reset_pd_mcu(void) if (ec_cfg_usb_db_type() == DB_USB4_NCT3807) gpio_set_level(GPIO_USB_C1_RST_ODL, 0); - /* * delay for power-on to reset-off and min. assertion time */ @@ -392,10 +390,9 @@ __override bool board_is_dts_port(int port) __override bool board_is_tbt_usb4_port(int port) { - if (((port == USBC_PORT_C2) && - (ec_cfg_usb_mb_type() == MB_USB4_TBT)) || - ((port == USBC_PORT_C1) && - (ec_cfg_usb_db_type() == DB_USB4_NCT3807))) + if (((port == USBC_PORT_C2) && (ec_cfg_usb_mb_type() == MB_USB4_TBT)) || + ((port == USBC_PORT_C1) && + (ec_cfg_usb_db_type() == DB_USB4_NCT3807))) return true; return false; -- cgit v1.2.1 From d3fab55f4daf3f6c0ecd4f583f83783c238b8796 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:25:43 -0600 Subject: board/casta/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I85789ac69a93d5014d6e611102b2268b948d19db Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728115 Reviewed-by: Jeremy Bettis --- board/casta/board.c | 46 ++++++++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/board/casta/board.c b/board/casta/board.c index 24dafc9fee..8fe51fe191 100644 --- a/board/casta/board.c +++ b/board/casta/board.c @@ -37,10 +37,10 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) static uint8_t sku_id; @@ -65,27 +65,27 @@ static void ppc_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_AMB] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_CHARGER] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_AMB] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_CHARGER] = { "TEMP_CHARGER", NPCX_ADC_CH1, + ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* TODO(b/119872005): Casta: confirm thermistor parts */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -103,13 +103,12 @@ const unsigned int chg_cnt = ARRAY_SIZE(chg_chips); * I2C callbacks to ensure bus free time for battery I2C transactions is at * least 5ms. */ -#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC) +#define BATTERY_FREE_MIN_DELTA_US (5 * MSEC) static timestamp_t battery_last_i2c_time; static int is_battery_i2c(const int port, const uint16_t addr_flags) { - return (port == I2C_PORT_BATTERY) - && (addr_flags == BATTERY_ADDR_FLAGS); + return (port == I2C_PORT_BATTERY) && (addr_flags == BATTERY_ADDR_FLAGS); } static int is_battery_port(int port) @@ -157,7 +156,7 @@ DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C); static void board_init(void) { - if(get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710) + if (get_cbi_ssfc_charger() != SSFC_CHARGER_BQ25710) return; chg_chips[0].drv = &bq25710_drv; @@ -174,7 +173,6 @@ static void set_input_limit_on_ac_removal(void) return; charger_set_input_current_limit(0, CONFIG_CHARGER_INPUT_CURRENT); - } DECLARE_HOOK(HOOK_AC_CHANGE, set_input_limit_on_ac_removal, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 433ecc6459cf7448e11afb81731777b50a4aa4ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:15 -0600 Subject: driver/bc12/mt6360.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I869e6a4502c0d22b30300a1e574631a82d13a3a1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729933 Reviewed-by: Jeremy Bettis --- driver/bc12/mt6360.c | 58 ++++++++++++++++++---------------------------------- 1 file changed, 20 insertions(+), 38 deletions(-) diff --git a/driver/bc12/mt6360.c b/driver/bc12/mt6360.c index 487883ec62..e5226b7394 100644 --- a/driver/bc12/mt6360.c +++ b/driver/bc12/mt6360.c @@ -19,20 +19,20 @@ #include "util.h" /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #define CPRINTS(format, args...) \ - cprints(CC_USBCHARGE, "%s " format, "MT6360", ## args) + cprints(CC_USBCHARGE, "%s " format, "MT6360", ##args) static enum ec_error_list mt6360_read8(int reg, int *val) { return i2c_read8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags, - reg, val); + reg, val); } static enum ec_error_list mt6360_write8(int reg, int val) { return i2c_write8(mt6360_config.i2c_port, mt6360_config.i2c_addr_flags, - reg, val); + reg, val); } static int mt6360_update_bits(int reg, int mask, int val) @@ -121,7 +121,7 @@ static void mt6360_update_charge_manager(int port, if (new_bc12_type != current_bc12_type) { if (current_bc12_type >= 0) charge_manager_update_charge(current_bc12_type, port, - NULL); + NULL); if (new_bc12_type != CHARGE_SUPPLIER_NONE) { struct charge_port_info chg = { @@ -146,10 +146,9 @@ static void mt6360_handle_bc12_irq(int port) /* Check vbus again to avoid timing issue */ if (pd_snk_is_vbus_provided(port)) mt6360_update_charge_manager( - port, mt6360_get_bc12_device_type()); + port, mt6360_get_bc12_device_type()); else - mt6360_update_charge_manager( - 0, CHARGE_SUPPLIER_NONE); + mt6360_update_charge_manager(0, CHARGE_SUPPLIER_NONE); } /* write clear */ @@ -168,9 +167,8 @@ static void mt6360_usb_charger_task_event(const int port, uint32_t evt) /* vbus change, start bc12 detection */ if (evt & USB_CHG_EVENT_VBUS) { bool is_sink = pd_get_power_role(port) == PD_ROLE_SINK; - bool is_non_pd_sink = !pd_capable(port) && - is_sink && - pd_snk_is_vbus_provided(port); + bool is_non_pd_sink = !pd_capable(port) && is_sink && + pd_snk_is_vbus_provided(port); if (is_sink) mt6360_clr_bit(MT6360_REG_CHG_CTRL1, MT6360_MASK_HZ); @@ -197,15 +195,15 @@ static int mt6360_regulator_write8(uint8_t addr, int reg, int val) * Note: The checksum from I2C_FLAG_PEC happens to be correct because * length == 1 -> the high 3 bits of the offset byte is 0. */ - return i2c_write8(mt6360_config.i2c_port, - addr | I2C_FLAG_PEC, reg, val); + return i2c_write8(mt6360_config.i2c_port, addr | I2C_FLAG_PEC, reg, + val); } static int mt6360_regulator_read8(int addr, int reg, int *val) { int rv; uint8_t crc = 0, real_crc; - uint8_t out[3] = {(addr << 1) | 1, reg}; + uint8_t out[3] = { (addr << 1) | 1, reg }; rv = i2c_read16(mt6360_config.i2c_port, addr, reg, val); if (rv) @@ -262,22 +260,10 @@ static const uint16_t MT6360_LDO5_VOSEL_TABLE[8] = { }; static const uint16_t MT6360_LDO6_VOSEL_TABLE[16] = { - [0x0] = 500, - [0x1] = 600, - [0x2] = 700, - [0x3] = 800, - [0x4] = 900, - [0x5] = 1000, - [0x6] = 1100, - [0x7] = 1200, - [0x8] = 1300, - [0x9] = 1400, - [0xA] = 1500, - [0xB] = 1600, - [0xC] = 1700, - [0xD] = 1800, - [0xE] = 1900, - [0xF] = 2000, + [0x0] = 500, [0x1] = 600, [0x2] = 700, [0x3] = 800, + [0x4] = 900, [0x5] = 1000, [0x6] = 1100, [0x7] = 1200, + [0x8] = 1300, [0x9] = 1400, [0xA] = 1500, [0xB] = 1600, + [0xC] = 1700, [0xD] = 1800, [0xE] = 1900, [0xF] = 2000, }; /* LDO7 VOSEL table is the same as LDO6's. */ @@ -410,14 +396,12 @@ int mt6360_regulator_enable(enum mt6360_regulator_id id, uint8_t enable) if (enable) return mt6360_regulator_update_bits( - data->addr, - data->reg_en_ctrl2, + data->addr, data->reg_en_ctrl2, MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN, MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN); else return mt6360_regulator_update_bits( - data->addr, - data->reg_en_ctrl2, + data->addr, data->reg_en_ctrl2, MT6360_MASK_RGL_SW_OP_EN | MT6360_MASK_RGL_SW_EN, MT6360_MASK_RGL_SW_OP_EN); } @@ -468,8 +452,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv, step = (mv - MT6360_BUCK_VOSEL_MIN) / MT6360_BUCK_VOSEL_STEP_MV; - return mt6360_regulator_update_bits(data->addr, - data->reg_ctrl3, + return mt6360_regulator_update_bits(data->addr, data->reg_ctrl3, data->mask_vosel, step); } @@ -489,8 +472,7 @@ int mt6360_regulator_set_voltage(enum mt6360_regulator_id id, int min_mv, if (mv + step * MT6360_LDO_VOCAL_STEP_MV > max_mv) continue; return mt6360_regulator_update_bits( - data->addr, - data->reg_ctrl3, + data->addr, data->reg_ctrl3, data->mask_vosel | data->mask_vocal, (i << data->shift_vosel) | step); } -- cgit v1.2.1 From ac24c771a0575418490f812b97dddefbfa5e628d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:13 -0600 Subject: driver/mp4245.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8b44059e28ce7d5f76d0684f21b9be750a9a82f9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730030 Reviewed-by: Jeremy Bettis --- driver/mp4245.c | 75 +++++++++++++++++++++++---------------------------------- 1 file changed, 30 insertions(+), 45 deletions(-) diff --git a/driver/mp4245.c b/driver/mp4245.c index 60df5affaf..097053de42 100644 --- a/driver/mp4245.c +++ b/driver/mp4245.c @@ -11,7 +11,6 @@ #include "mp4245.h" #include "util.h" - static int mp4245_reg16_write(int offset, int data) { return i2c_write16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, offset, @@ -29,8 +28,8 @@ int mp4245_set_voltage_out(int desired_mv) * * VOUT_COMMAND = (Vdes (mV) * 1024 / 1000) / 1024 */ - vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1)) - / MP4245_VOUT_1V; + vout = (desired_mv * MP4245_VOUT_FROM_MV + (MP4245_VOUT_1V >> 1)) / + MP4245_VOUT_1V; return mp4245_reg16_write(MP4245_CMD_VOUT_COMMAND, vout); } @@ -50,7 +49,7 @@ int mp4245_votlage_out_enable(int enable) int cmd_val = enable ? MP4245_CMD_OPERATION_ON : 0; return i2c_write8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_OPERATION, cmd_val); + MP4245_CMD_OPERATION, cmd_val); } int mp3245_get_vbus(int *mv, int *ma) @@ -61,9 +60,9 @@ int mp3245_get_vbus(int *mv, int *ma) /* Get Vbus/Ibus raw measurements */ rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_READ_VOUT, &vbus); + MP4245_CMD_READ_VOUT, &vbus); rv |= i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_READ_IOUT, &ibus); + MP4245_CMD_READ_IOUT, &ibus); if (rv == EC_SUCCESS) { /* Convert Vbus/Ibus to mV/mA */ @@ -82,34 +81,21 @@ struct mp4245_info { uint8_t len; }; -static struct mp4245_info mp4245_cmds[] = { - {MP4245_CMD_OPERATION, 1}, - {MP4245_CMD_CLEAR_FAULTS, 1}, - {MP4245_CMD_WRITE_PROTECT, 1}, - {MP4245_CMD_STORE_USER_ALL, 1}, - {MP4245_CMD_RESTORE_USER_ALL, 1}, - {MP4245_CMD_VOUT_MODE, 1}, - {MP4245_CMD_VOUT_COMMAND, 2}, - {MP4245_CMD_VOUT_SCALE_LOOP, 2}, - {MP4245_CMD_STATUS_BYTE, 1}, - {MP4245_CMD_STATUS_WORD, 2}, - {MP4245_CMD_STATUS_VOUT, 1}, - {MP4245_CMD_STATUS_INPUT, 1}, - {MP4245_CMD_STATUS_TEMP, 1}, - {MP4245_CMD_STATUS_CML, 1}, - {MP4245_CMD_READ_VIN, 2}, - {MP4245_CMD_READ_VOUT, 2}, - {MP4245_CMD_READ_IOUT, 2}, - {MP4245_CMD_READ_TEMP, 2}, - {MP4245_CMD_MFR_MODE_CTRL, 1}, - {MP4245_CMD_MFR_CURRENT_LIM, 1}, - {MP4245_CMD_MFR_LINE_DROP, 1}, - {MP4245_CMD_MFR_OT_FAULT_LIM, 1}, - {MP4245_CMD_MFR_OT_WARN_LIM, 1}, - {MP4245_CMD_MFR_CRC_ERROR, 1}, - {MP4245_CMD_MFF_MTP_CFG_CODE, 1}, - {MP4245_CMD_MFR_MTP_REV_NUM, 1}, - {MP4245_CMD_MFR_STATUS_MASK, 1}, +static struct mp4245_info mp4245_cmds[] = { + { MP4245_CMD_OPERATION, 1 }, { MP4245_CMD_CLEAR_FAULTS, 1 }, + { MP4245_CMD_WRITE_PROTECT, 1 }, { MP4245_CMD_STORE_USER_ALL, 1 }, + { MP4245_CMD_RESTORE_USER_ALL, 1 }, { MP4245_CMD_VOUT_MODE, 1 }, + { MP4245_CMD_VOUT_COMMAND, 2 }, { MP4245_CMD_VOUT_SCALE_LOOP, 2 }, + { MP4245_CMD_STATUS_BYTE, 1 }, { MP4245_CMD_STATUS_WORD, 2 }, + { MP4245_CMD_STATUS_VOUT, 1 }, { MP4245_CMD_STATUS_INPUT, 1 }, + { MP4245_CMD_STATUS_TEMP, 1 }, { MP4245_CMD_STATUS_CML, 1 }, + { MP4245_CMD_READ_VIN, 2 }, { MP4245_CMD_READ_VOUT, 2 }, + { MP4245_CMD_READ_IOUT, 2 }, { MP4245_CMD_READ_TEMP, 2 }, + { MP4245_CMD_MFR_MODE_CTRL, 1 }, { MP4245_CMD_MFR_CURRENT_LIM, 1 }, + { MP4245_CMD_MFR_LINE_DROP, 1 }, { MP4245_CMD_MFR_OT_FAULT_LIM, 1 }, + { MP4245_CMD_MFR_OT_WARN_LIM, 1 }, { MP4245_CMD_MFR_CRC_ERROR, 1 }, + { MP4245_CMD_MFF_MTP_CFG_CODE, 1 }, { MP4245_CMD_MFR_MTP_REV_NUM, 1 }, + { MP4245_CMD_MFR_STATUS_MASK, 1 }, }; static void mp4245_dump_reg(void) @@ -124,7 +110,7 @@ static void mp4245_dump_reg(void) mp4245_cmds[i].cmd, &val); } else { rv = i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - mp4245_cmds[i].cmd, &val); + mp4245_cmds[i].cmd, &val); } if (!rv) @@ -142,23 +128,23 @@ void mp4245_get_status(void) int vout; /* Get Operation register */ - i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_OPERATION, &on); + i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_OPERATION, + &on); /* Vbus on/off is bit 7 */ on >>= 7; /* Get status word */ i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_STATUS_WORD, &status); + MP4245_CMD_STATUS_WORD, &status); /* Get Vbus measurement */ - i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_READ_VOUT, &vbus); + i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_VOUT, + &vbus); vbus = MP4245_VOUT_TO_MV(vbus); /* Get Ibus measurement */ - i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_READ_IOUT, &ibus); + i2c_read16(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, MP4245_CMD_READ_IOUT, + &ibus); ibus = MP4245_IOUT_TO_MA(ibus); /* Get Vout command (sets Vbus level) */ @@ -168,7 +154,7 @@ void mp4245_get_status(void) /* Get Input current limit */ i2c_read8(I2C_PORT_MP4245, MP4245_I2C_ADDR_FLAGS, - MP4245_CMD_MFR_CURRENT_LIM, &ilim); + MP4245_CMD_MFR_CURRENT_LIM, &ilim); ilim *= MP4245_ILIM_STEP_MA; ccprintf("mp4245 Vbus %s:\n", on ? "On" : "Off"); @@ -208,6 +194,5 @@ static int command_mp4245(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245, - "", +DECLARE_CONSOLE_COMMAND(mp4245, command_mp4245, "", "Turn on/off|set vbus."); -- cgit v1.2.1 From 5e5a814493b5daf1df85c23548389b483bb9f8ea Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:11 -0600 Subject: board/driblee/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0778b3bbb1c66d74626f9c09c5bd20c12f62e7d3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728244 Reviewed-by: Jeremy Bettis --- board/driblee/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/driblee/cbi_ssfc.h b/board/driblee/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/driblee/cbi_ssfc.h +++ b/board/driblee/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From e97100030afd5798b479a0f421f86d99bd6d721f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:06:42 -0600 Subject: extra/usb_gpio/usb_gpio.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I00976ca4b072d2b63fc123b9aa28859caa6412b3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730188 Reviewed-by: Jeremy Bettis --- extra/usb_gpio/usb_gpio.c | 94 +++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 57 deletions(-) diff --git a/extra/usb_gpio/usb_gpio.c b/extra/usb_gpio/usb_gpio.c index 8973f3d304..40db84dd10 100644 --- a/extra/usb_gpio/usb_gpio.c +++ b/extra/usb_gpio/usb_gpio.c @@ -11,54 +11,46 @@ #include #include -#define CHECK(expression) \ - ({ \ - int error__ = (expression); \ - \ - if (error__ != 0) { \ - fprintf(stderr, \ - "libusb error: %s:%d %s\n", \ - __FILE__, \ - __LINE__, \ - libusb_error_name(error__)); \ - return error__; \ - } \ - \ - error__; \ +#define CHECK(expression) \ + ({ \ + int error__ = (expression); \ + \ + if (error__ != 0) { \ + fprintf(stderr, "libusb error: %s:%d %s\n", __FILE__, \ + __LINE__, libusb_error_name(error__)); \ + return error__; \ + } \ + \ + error__; \ }) #define TRANSFER_TIMEOUT_MS 100 -static int gpio_write(libusb_device_handle *device, - uint32_t set_mask, +static int gpio_write(libusb_device_handle *device, uint32_t set_mask, uint32_t clear_mask) { uint8_t command[8]; - int transferred; + int transferred; - command[0] = (set_mask >> 0) & 0xff; - command[1] = (set_mask >> 8) & 0xff; + command[0] = (set_mask >> 0) & 0xff; + command[1] = (set_mask >> 8) & 0xff; command[2] = (set_mask >> 16) & 0xff; command[3] = (set_mask >> 24) & 0xff; - command[4] = (clear_mask >> 0) & 0xff; - command[5] = (clear_mask >> 8) & 0xff; + command[4] = (clear_mask >> 0) & 0xff; + command[5] = (clear_mask >> 8) & 0xff; command[6] = (clear_mask >> 16) & 0xff; command[7] = (clear_mask >> 24) & 0xff; - CHECK(libusb_bulk_transfer(device, - LIBUSB_ENDPOINT_OUT | 2, - command, - sizeof(command), - &transferred, + CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_OUT | 2, command, + sizeof(command), &transferred, TRANSFER_TIMEOUT_MS)); if (transferred != sizeof(command)) { fprintf(stderr, "Failed to transfer full command " "(sent %d of %d bytes)\n", - transferred, - (int)sizeof(command)); + transferred, (int)sizeof(command)); return LIBUSB_ERROR_OTHER; } @@ -68,38 +60,29 @@ static int gpio_write(libusb_device_handle *device, static int gpio_read(libusb_device_handle *device, uint32_t *mask) { uint8_t response[4]; - int transferred; + int transferred; /* * The first query does triggers the sampling of the GPIO values, the * second query reads them back. */ - CHECK(libusb_bulk_transfer(device, - LIBUSB_ENDPOINT_IN | 2, - response, - sizeof(response), - &transferred, + CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response, + sizeof(response), &transferred, TRANSFER_TIMEOUT_MS)); - CHECK(libusb_bulk_transfer(device, - LIBUSB_ENDPOINT_IN | 2, - response, - sizeof(response), - &transferred, + CHECK(libusb_bulk_transfer(device, LIBUSB_ENDPOINT_IN | 2, response, + sizeof(response), &transferred, TRANSFER_TIMEOUT_MS)); if (transferred != sizeof(response)) { fprintf(stderr, "Failed to transfer full response " "(read %d of %d bytes)\n", - transferred, - (int)sizeof(response)); + transferred, (int)sizeof(response)); return LIBUSB_ERROR_OTHER; } - *mask = (response[0] << 0 | - response[1] << 8 | - response[2] << 16 | + *mask = (response[0] << 0 | response[1] << 8 | response[2] << 16 | response[3] << 24); return 0; @@ -107,13 +90,13 @@ static int gpio_read(libusb_device_handle *device, uint32_t *mask) int main(int argc, char **argv) { - libusb_context *context; + libusb_context *context; libusb_device_handle *device; - uint16_t vendor_id = 0x18d1; /* Google */ - uint16_t product_id = 0x500f; /* discovery-stm32f072 */ - int interface = 1; /* gpio interface */ + uint16_t vendor_id = 0x18d1; /* Google */ + uint16_t product_id = 0x500f; /* discovery-stm32f072 */ + int interface = 1; /* gpio interface */ - if (!(argc == 2 && strcmp(argv[1], "read") == 0) && + if (!(argc == 2 && strcmp(argv[1], "read") == 0) && !(argc == 4 && strcmp(argv[1], "write") == 0)) { puts("Usage: usb_gpio read\n" " usb_gpio write \n"); @@ -122,15 +105,12 @@ int main(int argc, char **argv) CHECK(libusb_init(&context)); - device = libusb_open_device_with_vid_pid(context, - vendor_id, - product_id); + device = + libusb_open_device_with_vid_pid(context, vendor_id, product_id); if (device == NULL) { - fprintf(stderr, - "Unable to find device 0x%04x:0x%04x\n", - vendor_id, - product_id); + fprintf(stderr, "Unable to find device 0x%04x:0x%04x\n", + vendor_id, product_id); return 1; } @@ -146,7 +126,7 @@ int main(int argc, char **argv) } if (argc == 4 && strcmp(argv[1], "write") == 0) { - uint32_t set_mask = strtol(argv[2], NULL, 0); + uint32_t set_mask = strtol(argv[2], NULL, 0); uint32_t clear_mask = strtol(argv[3], NULL, 0); CHECK(gpio_write(device, set_mask, clear_mask)); -- cgit v1.2.1 From d78a68e682aa4eff0a5250af8e69a4b5de642e63 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:31 -0600 Subject: include/keyboard_raw.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0a8e49232d770299f0f603a3ac1d461c143e3844 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730299 Reviewed-by: Jeremy Bettis --- include/keyboard_raw.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/include/keyboard_raw.h b/include/keyboard_raw.h index 6989ae36a7..a35d39dfa2 100644 --- a/include/keyboard_raw.h +++ b/include/keyboard_raw.h @@ -18,7 +18,7 @@ /* Column values for keyboard_raw_drive_column() */ enum keyboard_column_index { - KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */ + KEYBOARD_COLUMN_ALL = -2, /* Drive all columns */ KEYBOARD_COLUMN_NONE = -1, /* Drive no columns (tri-state all) */ /* 0 ~ KEYBOARD_COLS_MAX-1 for the corresponding column */ }; @@ -70,7 +70,9 @@ void keyboard_raw_enable_interrupt(int enable); void keyboard_raw_gpio_interrupt(enum gpio_signal signal); #else -static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) { } +static inline void keyboard_raw_gpio_interrupt(enum gpio_signal signal) +{ +} #endif /* !HAS_TASK_KEYSCAN */ /** @@ -89,11 +91,13 @@ int keyboard_factory_test_scan(void); */ int keyboard_raw_is_input_low(int port, int id); -static inline int keyboard_raw_get_cols(void) { +static inline int keyboard_raw_get_cols(void) +{ return keyboard_cols; } -static inline void keyboard_raw_set_cols(int cols) { +static inline void keyboard_raw_set_cols(int cols) +{ #ifdef CONFIG_KEYBOARD_LANGUAGE_ID /* Keyboard ID is probably encoded right after the last column. Scanner * would read keyboard ID if the column size is decreased. */ @@ -118,4 +122,4 @@ static inline void keyboard_raw_set_cols(int cols) { void board_keyboard_drive_col(int col); #endif -#endif /* __CROS_EC_KEYBOARD_RAW_H */ +#endif /* __CROS_EC_KEYBOARD_RAW_H */ -- cgit v1.2.1 From 0aa83e405856dccf26221961cd99510357e872b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:13:46 -0600 Subject: baseboard/asurada/hibernate.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0f89427740e30200b37836f02a4c4934cb06ce04 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727851 Reviewed-by: Jeremy Bettis --- baseboard/asurada/hibernate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/baseboard/asurada/hibernate.c b/baseboard/asurada/hibernate.c index b26bd44adc..47d8a47f0c 100644 --- a/baseboard/asurada/hibernate.c +++ b/baseboard/asurada/hibernate.c @@ -23,8 +23,8 @@ __override void board_hibernate_late(void) */ if (board_get_version() <= 1) { if (IS_ENABLED(BOARD_ASURADA) || - (IS_ENABLED(CONFIG_ZEPHYR) && - IS_ENABLED(CONFIG_BOARD_ASURADA))) + (IS_ENABLED(CONFIG_ZEPHYR) && + IS_ENABLED(CONFIG_BOARD_ASURADA))) return; } -- cgit v1.2.1 From ae3fecbf71d65bf73e6649af7b810b8b9848be06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:06 -0600 Subject: board/gimble/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I7d08c35ad444e800ae05723384c6244e04aac436 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728412 Reviewed-by: Jeremy Bettis --- board/gimble/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gimble/fans.c b/board/gimble/fans.c index d966056331..53294139f6 100644 --- a/board/gimble/fans.c +++ b/board/gimble/fans.c @@ -25,7 +25,7 @@ BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); static const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From d58b140606cd5c0074afc1852f79d3e5b0ceebc6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:52 -0600 Subject: test/usb_sm_framework_h3.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6516a8341009256bffe74db2748a9e6f473f47b0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730571 Reviewed-by: Jeremy Bettis --- test/usb_sm_framework_h3.c | 610 +++++++++++++++++++++++++++++---------------- 1 file changed, 393 insertions(+), 217 deletions(-) diff --git a/test/usb_sm_framework_h3.c b/test/usb_sm_framework_h3.c index ba544a749a..09904dfb8f 100644 --- a/test/usb_sm_framework_h3.c +++ b/test/usb_sm_framework_h3.c @@ -112,7 +112,7 @@ enum state_id { EXIT_C, }; -#define PORT0 0 +#define PORT0 0 struct sm_ { /* struct sm_obj must be first */ @@ -198,7 +198,6 @@ static void sm_test_super_A2_exit(const int port) sm[port].seq[sm[port].idx++] = EXIT_A2; } - static void sm_test_super_B2_entry(const int port) { sm[port].seq[sm[port].idx++] = ENTER_B2; @@ -269,7 +268,6 @@ static void sm_test_A4_exit(const int port) sm[port].seq[sm[port].idx++] = EXIT_A4; } - static void sm_test_A5_entry(const int port) { sm[port].sv_tmp = 0; @@ -291,7 +289,6 @@ static void sm_test_A5_exit(const int port) sm[port].seq[sm[port].idx++] = EXIT_A5; } - static void sm_test_A6_entry(const int port) { sm[port].sv_tmp = 0; @@ -355,7 +352,6 @@ static void sm_test_B4_exit(const int port) sm[port].seq[sm[port].idx++] = EXIT_B4; } - static void sm_test_B5_entry(const int port) { sm[port].sv_tmp = 0; @@ -377,7 +373,6 @@ static void sm_test_B5_exit(const int port) sm[port].seq[sm[port].idx++] = EXIT_B5; } - static void sm_test_B6_entry(const int port) { sm[port].sv_tmp = 0; @@ -440,63 +435,88 @@ test_static int test_hierarchy_0(void) set_state_sm(port, SM_TEST_A4); run_sm(); - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; for (; i < SEQUENCE_SIZE; i++) TEST_EQ(sm[port].seq[i], 0, "%d"); @@ -512,71 +532,104 @@ test_static int test_hierarchy_1(void) set_state_sm(port, SM_TEST_A4); run_sm(); - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; for (i = 33; i < SEQUENCE_SIZE; i++) TEST_EQ(sm[port].seq[i], 0, "%d"); @@ -586,88 +639,130 @@ test_static int test_hierarchy_1(void) test_static int test_hierarchy_2(void) { - int port = PORT0; int i = 0; set_state_sm(port, SM_TEST_A4); run_sm(); - TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_C, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; for (; i < SEQUENCE_SIZE; i++) TEST_EQ(sm[port].seq[i], 0, "%d"); @@ -677,100 +772,154 @@ test_static int test_hierarchy_2(void) test_static int test_hierarchy_3(void) { - int port = PORT0; int i = 0; set_state_sm(port, SM_TEST_A4); run_sm(); - TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; - + TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); + ++i; + run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_C, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); + ++i; + + run_sm(); + TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); + ++i; - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_C, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A7, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A7, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A6, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i; - - run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); ++i; + run_sm(); + TEST_EQ(sm[port].seq[i], EXIT_A6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A5, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_A1, "%d"); + ++i; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A4, "%d"); + ++i; for (; i < SEQUENCE_SIZE; i++) TEST_EQ(sm[port].seq[i], 0, "%d"); @@ -787,35 +936,53 @@ test_static int test_set_state_from_parents(void) test_control.a3_entry_to = &states[SM_TEST_B4]; run_sm(); set_state_sm(port, SM_TEST_A4); - TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); ++i; + TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A3, "%d"); + ++i; /* Does not enter or exit A4 */ - TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_A3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B4, "%d"); + ++i; /* Ensure we didn't go further than above statements */ TEST_EQ(sm[port].seq[i], 0, "%d"); test_control.b3_run_to = &states[SM_TEST_B5]; run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B3, "%d"); + ++i; /* Does not run b2 or b1 */ - TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B4, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B3, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B5, "%d"); + ++i; /* Ensure we didn't go further than above statements */ TEST_EQ(sm[port].seq[i], 0, "%d"); run_sm(); - TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); ++i; + TEST_EQ(sm[port].seq[i], RUN_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], RUN_B1, "%d"); + ++i; /* Ensure we didn't go further than above statements */ TEST_EQ(sm[port].seq[i], 0, "%d"); @@ -827,15 +994,24 @@ test_static int test_set_state_from_parents(void) test_control.c_entry_to = &states[SM_TEST_A7]; test_control.c_exit_to = &states[SM_TEST_A4]; run_sm(); - TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); ++i; - TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); ++i; + TEST_EQ(sm[port].seq[i], EXIT_B5, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B2, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B6, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_B1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], EXIT_C, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A1, "%d"); + ++i; + TEST_EQ(sm[port].seq[i], ENTER_A7, "%d"); + ++i; /* Ensure we didn't go further than above statements */ TEST_EQ(sm[port].seq[i], 0, "%d"); -- cgit v1.2.1 From 0f7df8c86d96f441e0e7a0fdb381a7c80cb9a90f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:21 -0600 Subject: chip/mchp/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8eac00a7f09b797b04108bbea701b6d07f3bc95f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729290 Reviewed-by: Jeremy Bettis --- chip/mchp/fan.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/mchp/fan.c b/chip/mchp/fan.c index 17b60b703d..b5023c13d3 100644 --- a/chip/mchp/fan.c +++ b/chip/mchp/fan.c @@ -38,7 +38,6 @@ static int rpm_setting; static int duty_setting; static int in_rpm_mode = 1; - static void clear_status(void) { /* Clear DRIVE_FAIL, FAN_SPIN, and FAN_STALL bits */ @@ -78,14 +77,14 @@ void fan_set_duty(int ch, int percent) duty_setting = percent; MCHP_FAN_SETTING(0) = (percent * MAX_FAN_DRIVER_SETTING / 100) - << FAN_DRIVER_SETTING_SHIFT; + << FAN_DRIVER_SETTING_SHIFT; clear_status(); } int fan_get_duty(int ch) { - duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT) - * 100 / MAX_FAN_DRIVER_SETTING; + duty_setting = (MCHP_FAN_SETTING(0) >> FAN_DRIVER_SETTING_SHIFT) * 100 / + MAX_FAN_DRIVER_SETTING; return duty_setting; } -- cgit v1.2.1 From be3e2d6cdd49f8f957d6efc94e8c6f4e17b54634 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:11 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iee2782fc32c857462eaa2ca869b22c2756405cd1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730922 Reviewed-by: Jeremy Bettis --- .../x86_non_dsx_common_pwrseq_sm_handler.c | 65 ++++++++++------------ 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index 561c789e80..2bbcce4d39 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -8,8 +8,7 @@ #include -static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, - CONFIG_AP_PWRSEQ_STACK_SIZE); +static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE); static struct k_thread pwrseq_thread_data; static struct pwrseq_context pwrseq_ctx; /* S5 inactive timer*/ @@ -26,13 +25,12 @@ static ATOMIC_DEFINE(flags, FLAGS_MAX); /* Delay in ms when starting from G3 */ static uint32_t start_from_g3_delay_ms; - LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); /** * @brief power_state names for debug */ -static const char * const pwrsm_dbg[] = { +static const char *const pwrsm_dbg[] = { [SYS_POWER_STATE_G3] = "G3", [SYS_POWER_STATE_S5] = "S5", [SYS_POWER_STATE_S4] = "S4", @@ -94,7 +92,7 @@ enum power_states_ndsx pwr_sm_get_state(void) return pwrseq_ctx.power_state; } -const char * const pwr_sm_get_state_name(enum power_states_ndsx state) +const char *const pwr_sm_get_state_name(enum power_states_ndsx state) { return pwrsm_dbg[state]; } @@ -235,7 +233,7 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_G3S5: if ((power_get_signals() & PWRSEQ_G3S5_UP_SIGNAL) == - PWRSEQ_G3S5_UP_VALUE) + PWRSEQ_G3S5_UP_VALUE) return SYS_POWER_STATE_S5; else return SYS_POWER_STATE_S5G3; @@ -243,15 +241,15 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_S5: /* In S5 make sure no more signal lost */ /* If A-rails are stable then move to higher state */ - if (board_ap_power_check_power_rails_enabled() - && rsmrst_power_is_good()) { + if (board_ap_power_check_power_rails_enabled() && + rsmrst_power_is_good()) { /* rsmrst is intact */ rsmrst_pass_thru_handler(); if (signals_valid_and_off(IN_PCH_SLP_S5)) { k_timer_stop(&s5_inactive_timer); /* Clear the timer running flag */ atomic_clear_bit(flags, - S5_INACTIVE_TIMER_RUNNING); + S5_INACTIVE_TIMER_RUNNING); /* Clear any request to exit hard-off */ atomic_clear_bit(flags, START_FROM_G3); LOG_INF("Clearing request to exit G3"); @@ -277,20 +275,20 @@ static int common_pwr_sm_run(int state) * and it is started (and the flag is set), * otherwise it is already set, so no change. */ - if (!atomic_test_and_set_bit(flags, - S5_INACTIVE_TIMER_RUNNING)) { + if (!atomic_test_and_set_bit( + flags, S5_INACTIVE_TIMER_RUNNING)) { /* * Timer is not started, or needs * restarting. */ k_timer_start(&s5_inactive_timer, - K_SECONDS(AP_PWRSEQ_DT_VALUE( - s5_inactivity_timeout)), - K_NO_WAIT); + K_SECONDS(AP_PWRSEQ_DT_VALUE( + s5_inactivity_timeout)), + K_NO_WAIT); } else if (k_timer_status_get(&s5_inactive_timer) > 0) { /* Timer is expired */ atomic_clear_bit(flags, - S5_INACTIVE_TIMER_RUNNING); + S5_INACTIVE_TIMER_RUNNING); return SYS_POWER_STATE_S5G3; } } @@ -373,7 +371,7 @@ static int common_pwr_sm_run(int state) case SYS_POWER_STATE_S0ix: /* System in S0 only if SLP_S0 and SLP_S3 are de-asserted */ if (power_signals_off(IN_PCH_SLP_S0) && - signals_valid_and_off(IN_PCH_SLP_S3)) { + signals_valid_and_off(IN_PCH_SLP_S3)) { /* TODO: Make sure ap reset handling is done * before leaving S0ix. */ @@ -425,19 +423,19 @@ static int common_pwr_sm_run(int state) return SYS_POWER_STATE_S0S3; #if CONFIG_AP_PWRSEQ_S0IX - /* - * SLP_S0 may assert in system idle scenario without a kernel - * freeze call. This may cause interrupt storm since there is - * no freeze/unfreeze of threads/process in the idle scenario. - * Ignore the SLP_S0 assertions in idle scenario by checking - * the host sleep state. - */ + /* + * SLP_S0 may assert in system idle scenario without a + * kernel freeze call. This may cause interrupt storm + * since there is no freeze/unfreeze of threads/process + * in the idle scenario. Ignore the SLP_S0 assertions in + * idle scenario by checking the host sleep state. + */ } else if (ap_power_sleep_get_notify() == - AP_POWER_SLEEP_SUSPEND && - power_signals_on(IN_PCH_SLP_S0)) { + AP_POWER_SLEEP_SUSPEND && + power_signals_on(IN_PCH_SLP_S0)) { return SYS_POWER_STATE_S0S0ix; } else if (ap_power_sleep_get_notify() == - AP_POWER_SLEEP_RESUME) { + AP_POWER_SLEEP_RESUME) { ap_power_sleep_notify_transition(AP_POWER_SLEEP_RESUME); #endif /* CONFIG_AP_PWRSEQ_S0IX */ } @@ -537,9 +535,8 @@ static void pwrseq_loop_thread(void *p1, void *p2, void *p3) this_in_signals = power_get_signals(); if (this_in_signals != last_in_signals || - curr_state != last_state) { - LOG_INF("power state %d = %s, in 0x%04x", - curr_state, + curr_state != last_state) { + LOG_INF("power state %d = %s, in 0x%04x", curr_state, pwr_sm_get_state_name(curr_state), this_in_signals); last_in_signals = this_in_signals; @@ -569,14 +566,12 @@ static void pwrseq_loop_thread(void *p1, void *p2, void *p3) static inline void create_pwrseq_thread(void) { - k_thread_create(&pwrseq_thread_data, - pwrseq_thread_stack, + k_thread_create(&pwrseq_thread_data, pwrseq_thread_stack, K_KERNEL_STACK_SIZEOF(pwrseq_thread_stack), - (k_thread_entry_t)pwrseq_loop_thread, - NULL, NULL, NULL, + (k_thread_entry_t)pwrseq_loop_thread, NULL, NULL, NULL, CONFIG_AP_PWRSEQ_THREAD_PRIORITY, 0, - IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART) ? K_NO_WAIT - : K_FOREVER); + IS_ENABLED(CONFIG_AP_PWRSEQ_AUTOSTART) ? K_NO_WAIT : + K_FOREVER); k_thread_name_set(&pwrseq_thread_data, "pwrseq_task"); } -- cgit v1.2.1 From 9f64c0742a83e205bbd651439fd5fb7f0aebc0e2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:30 -0600 Subject: driver/ioexpander/it8801.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I46e9bbca3c74f717449756950a1acd9b4272bb9f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729985 Reviewed-by: Jeremy Bettis --- driver/ioexpander/it8801.c | 97 +++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/driver/ioexpander/it8801.c b/driver/ioexpander/it8801.c index dbf13c4da8..382f6dc547 100644 --- a/driver/ioexpander/it8801.c +++ b/driver/ioexpander/it8801.c @@ -17,7 +17,7 @@ #include "util.h" #include "keyboard_backlight.h" -#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ## args) +#define CPRINTS(format, args...) cprints(CC_KEYSCAN, format, ##args) static int it8801_ioex_set_level(int ioex, int port, int mask, int value); static void it8801_ioex_event_handler(void); @@ -25,14 +25,14 @@ DECLARE_DEFERRED(it8801_ioex_event_handler); static int it8801_read(int reg, int *data) { - return i2c_read8(I2C_PORT_KB_DISCRETE, - KB_DISCRETE_I2C_ADDR_FLAGS, reg, data); + return i2c_read8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg, + data); } __maybe_unused static int it8801_write(int reg, int data) { - return i2c_write8(I2C_PORT_KB_DISCRETE, - KB_DISCRETE_I2C_ADDR_FLAGS, reg, data); + return i2c_write8(I2C_PORT_KB_DISCRETE, KB_DISCRETE_I2C_ADDR_FLAGS, reg, + data); } struct it8801_vendor_id_t { @@ -41,8 +41,8 @@ struct it8801_vendor_id_t { }; static const struct it8801_vendor_id_t it8801_vendor_id_verify[] = { - { 0x12, IT8801_REG_HBVIDR}, - { 0x83, IT8801_REG_LBVIDR}, + { 0x12, IT8801_REG_HBVIDR }, + { 0x83, IT8801_REG_LBVIDR }, }; static int it8801_check_vendor_id(void) @@ -133,10 +133,10 @@ void keyboard_raw_task_start(void) keyboard_raw_enable_interrupt(1); } -__overridable const uint8_t it8801_kso_mapping[] = { - 0, 1, 20, 3, 4, 5, 6, 17, 18, 16, 15, 11, 12, +__overridable const uint8_t it8801_kso_mapping[] = { 0, 1, 20, 3, 4, 5, 6, + 17, 18, 16, 15, 11, 12, #ifdef CONFIG_KEYBOARD_KEYPAD - 13, 14 + 13, 14 #endif }; BUILD_ASSERT(ARRAY_SIZE(it8801_kso_mapping) == KEYBOARD_COLS_MAX); @@ -179,11 +179,11 @@ test_mockable void keyboard_raw_drive_column(int col) if (col == IT8801_REG_MASK_SELKSO2) { /* Output high(so selected). */ it8801_ioex_set_level(0, 2, - IT8801_REG_GPIO23SOV, 1); + IT8801_REG_GPIO23SOV, 1); } else { /* Output low(so not selected). */ it8801_ioex_set_level(0, 2, - IT8801_REG_GPIO23SOV, 0); + IT8801_REG_GPIO23SOV, 0); } } } @@ -229,25 +229,25 @@ static int it8801_ioex_read(int ioex, int reg, int *data) { struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, data); + return i2c_read8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + data); } static int it8801_ioex_write(int ioex, int reg, int data) { struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, data); + return i2c_write8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + data); } static int it8801_ioex_update(int ioex, int reg, int data, - enum mask_update_action action) + enum mask_update_action action) { struct ioexpander_config_t *ioex_p = &ioex_config[ioex]; - return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, - reg, data, action); + return i2c_update8(ioex_p->i2c_host_port, ioex_p->i2c_addr_flags, reg, + data, action); } static const int it8801_valid_gpio_group[] = { @@ -340,15 +340,15 @@ static int it8801_ioex_set_level(int ioex, int port, int mask, int value) it8801_gpio_sov[port] &= ~mask; rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port), - it8801_gpio_sov[port]); + it8801_gpio_sov[port]); } mutex_unlock(&ioex_mutex); return rv; } -static int it8801_ioex_get_flags_by_mask(int ioex, int port, - int mask, int *flags) +static int it8801_ioex_get_flags_by_mask(int ioex, int port, int mask, + int *flags) { int rv, val; @@ -378,8 +378,8 @@ static int it8801_ioex_get_flags_by_mask(int ioex, int port, return EC_SUCCESS; } -static int it8801_ioex_set_flags_by_mask(int ioex, int port, - int mask, int flags) +static int it8801_ioex_set_flags_by_mask(int ioex, int port, int mask, + int flags) { int rv, val; @@ -388,13 +388,13 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port, if (flags & ~IT8801_SUPPORT_GPIO_FLAGS) { CPRINTS("Flag 0x%08x is not supported at port %d, mask %d", - flags, port, mask); + flags, port, mask); return EC_ERROR_INVAL; } /* GPIO alternate function switching(GPIO[00, 12:15, 20:23]). */ rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_CR(port, mask), - IT8801_REG_MASK_GPIOAFS_FUNC1); + IT8801_REG_MASK_GPIOAFS_FUNC1); if (rv) return rv; @@ -418,7 +418,7 @@ static int it8801_ioex_set_flags_by_mask(int ioex, int port, it8801_gpio_sov[port] &= ~mask; rv = it8801_ioex_write(ioex, IT8801_REG_GPIO_SOVR(port), - it8801_gpio_sov[port]); + it8801_gpio_sov[port]); if (rv) goto unlock_mutex; @@ -451,13 +451,13 @@ static int it8801_ioex_enable_interrupt(int ioex, int port, int mask, return EC_ERROR_INVAL; /* Clear pending interrupt */ - rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port), - mask, MASK_SET); + rv = it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port), mask, + MASK_SET); if (rv) return rv; - return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port), - mask, enable ? MASK_SET : MASK_CLR); + return it8801_ioex_update(ioex, IT8801_REG_GPIO_IER(port), mask, + enable ? MASK_SET : MASK_CLR); } #ifdef CONFIG_ZEPHYR @@ -483,7 +483,7 @@ static void it8801_ioex_irq(int ioex, int port) /* Clear pending interrupt */ it8801_ioex_update(ioex, IT8801_REG_GPIO_ISR(port), - g->mask, MASK_SET); + g->mask, MASK_SET); if (!data) break; @@ -502,7 +502,7 @@ static void it8801_ioex_event_handler(void) /* Wake the keyboard scan task if KSI interrupts are triggered */ if (IS_ENABLED(CONFIG_KEYBOARD_DISCRETE) && - data & IT8801_REG_MASK_GISR_GKSIIS) + data & IT8801_REG_MASK_GISR_GKSIIS) task_wake(TASK_ID_KEYSCAN); /* @@ -535,14 +535,14 @@ static int it8801_ioex_get_port(int ioex, int port, int *val) #endif const struct ioexpander_drv it8801_ioexpander_drv = { - .init = &it8801_ioex_init, - .get_level = &it8801_ioex_get_level, - .set_level = &it8801_ioex_set_level, + .init = &it8801_ioex_init, + .get_level = &it8801_ioex_get_level, + .set_level = &it8801_ioex_set_level, .get_flags_by_mask = &it8801_ioex_get_flags_by_mask, .set_flags_by_mask = &it8801_ioex_set_flags_by_mask, - .enable_interrupt = &it8801_ioex_enable_interrupt, + .enable_interrupt = &it8801_ioex_enable_interrupt, #ifdef CONFIG_IO_EXPANDER_SUPPORT_GET_PORT - .get_port = &it8801_ioex_get_port, + .get_port = &it8801_ioex_get_port, #endif }; @@ -582,13 +582,13 @@ struct it8801_pwm_gpio_map { }; const static struct it8801_pwm_gpio_map it8801_pwm_gpio_map[] = { - [1] = {.port = 1, .mask = BIT(2), .pushpull_en = BIT(0)}, - [2] = {.port = 1, .mask = BIT(3), .pushpull_en = BIT(1)}, - [3] = {.port = 1, .mask = BIT(4), .pushpull_en = BIT(2)}, - [4] = {.port = 1, .mask = BIT(5), .pushpull_en = BIT(3)}, - [7] = {.port = 2, .mask = BIT(0), .pushpull_en = BIT(4)}, - [8] = {.port = 2, .mask = BIT(3), .pushpull_en = BIT(5)}, - [9] = {.port = 2, .mask = BIT(2), .pushpull_en = BIT(6)}, + [1] = { .port = 1, .mask = BIT(2), .pushpull_en = BIT(0) }, + [2] = { .port = 1, .mask = BIT(3), .pushpull_en = BIT(1) }, + [3] = { .port = 1, .mask = BIT(4), .pushpull_en = BIT(2) }, + [4] = { .port = 1, .mask = BIT(5), .pushpull_en = BIT(3) }, + [7] = { .port = 2, .mask = BIT(0), .pushpull_en = BIT(4) }, + [8] = { .port = 2, .mask = BIT(3), .pushpull_en = BIT(5) }, + [9] = { .port = 2, .mask = BIT(2), .pushpull_en = BIT(6) }, }; void it8801_pwm_enable(enum pwm_channel ch, int enabled) @@ -609,10 +609,10 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled) */ if (it8801_pwm_channels[ch].index <= 7) it8801_write(IT8801_REG_GPIO_CR(port, mask), - 0x1 << IT8801_GPIOAFS_SHIFT); + 0x1 << IT8801_GPIOAFS_SHIFT); else it8801_write(IT8801_REG_GPIO_CR(port, mask), - 0x2 << IT8801_GPIOAFS_SHIFT); + 0x2 << IT8801_GPIOAFS_SHIFT); it8801_read(IT8801_REG_PWMMCR(it8801_pwm_channels[ch].index), &val); val &= (~IT8801_PWMMCR_MCR_MASK); @@ -628,7 +628,6 @@ void it8801_pwm_enable(enum pwm_channel ch, int enabled) if (enabled) val |= it8801_pwm_gpio_map[index].pushpull_en; it8801_write(IT8801_REG_PWMODDSR, val); - } int it8801_pwm_get_enabled(enum pwm_channel ch) @@ -706,4 +705,4 @@ const struct kblight_drv kblight_it8801 = { .get_enabled = it8801_kblight_get_enabled, }; #endif -#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */ +#endif /* CONFIG_IO_EXPANDER_IT8801_PWM */ -- cgit v1.2.1 From 5891c51d030db298d6a32d6260b88110345aac7d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:34:43 -0600 Subject: zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2764c0fa272218c9f93cf7666c37dcd7ca7a5ce7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728332 Reviewed-by: Jeremy Bettis --- zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h index c5415d94db..caf96a8351 100644 --- a/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h +++ b/zephyr/shim/chip/npcx/npcx_monitor/npcx_monitor.h @@ -7,11 +7,11 @@ #include -#define NPCX_MONITOR_UUT_TAG 0xA5075001 -#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 +#define NPCX_MONITOR_UUT_TAG 0xA5075001 +#define NPCX_MONITOR_HEADER_ADDR 0x200C3000 /* Flag to record the progress of programming SPI flash */ -#define SPI_PROGRAMMING_FLAG 0x200C4000 +#define SPI_PROGRAMMING_FLAG 0x200C4000 struct monitor_header_tag { /* offset 0x00: TAG NPCX_MONITOR_TAG */ @@ -23,9 +23,9 @@ struct monitor_header_tag { /* offset 0x0C: The Flash address to be programmed (Absolute address) */ uint32_t dest_addr; /* offset 0x10: Maximum allowable flash clock frequency */ - uint8_t max_clock; + uint8_t max_clock; /* offset 0x11: SPI Flash read mode */ - uint8_t read_mode; + uint8_t read_mode; /* offset 0x12: Reserved */ uint16_t reserved; } __packed; -- cgit v1.2.1 From 5236c3121358df5a3a55c04b53037cb52fc572fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:28:07 -0600 Subject: chip/stm32/config-stm32l476.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8c029c4c8d31c68329fcdec1bdf1f7ec8d5a83e7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729484 Reviewed-by: Jeremy Bettis --- chip/stm32/config-stm32l476.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/chip/stm32/config-stm32l476.h b/chip/stm32/config-stm32l476.h index 7f6fbb0f84..618a40a0f7 100644 --- a/chip/stm32/config-stm32l476.h +++ b/chip/stm32/config-stm32l476.h @@ -4,20 +4,20 @@ */ /* Memory mapping */ -#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ -#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ -#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ -#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ +#define CONFIG_FLASH_SIZE_BYTES 0x00100000 /* 1 MB */ +#define CONFIG_FLASH_BANK_SIZE 0x800 /* 2 kB */ +#define CONFIG_FLASH_ERASE_SIZE 0x800 /* 2 KB */ +#define CONFIG_FLASH_WRITE_SIZE 0x8 /* 64 bits (without 8 bits ECC) */ /* Ideal write size in page-mode */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x100 /* 256 (32 double words) */ -#define CONFIG_RAM_BASE 0x20000000 +#define CONFIG_RAM_BASE 0x20000000 /* Only using SRAM1. SRAM2 (32 KB) is ignored. */ -#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ +#define CONFIG_RAM_SIZE 0x00018000 /* 96 kB */ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 82 /* DFU Address */ -#define STM32_DFU_BASE 0x1fff0000 +#define STM32_DFU_BASE 0x1fff0000 -- cgit v1.2.1 From 56e2fffac9822aa3e3a69d1226d063d3038617d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:07 -0600 Subject: board/kappa/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I69d7e0f20c0624e66e0a32cf33c3df03fdb33676 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728486 Reviewed-by: Jeremy Bettis --- board/kappa/board.c | 64 +++++++++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 36 deletions(-) diff --git a/board/kappa/board.c b/board/kappa/board.c index a0d5fda409..266a2cccf5 100644 --- a/board/kappa/board.c +++ b/board/kappa/board.c @@ -44,8 +44,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -57,40 +57,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -98,8 +92,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -132,8 +126,7 @@ struct ioexpander_config_t ioex_config[CONFIG_IO_EXPANDER_PORT_COUNT] = { /******************************************************************************/ /* SPI devices */ /* TODO: to be added once sensors land via CL:1714436 */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { @@ -155,8 +148,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -221,12 +213,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) -- cgit v1.2.1 From f661c3dae33fcbc55f9ddd9c345051d0bc65b04d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:27:40 -0600 Subject: util/uut/opr.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic2afe92ea13e17baf7f3bf47ad03eaf74e341edc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730665 Reviewed-by: Jeremy Bettis --- util/uut/opr.c | 75 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 40 insertions(+), 35 deletions(-) diff --git a/util/uut/opr.c b/util/uut/opr.c index 5c979afb16..6e8edfe863 100644 --- a/util/uut/opr.c +++ b/util/uut/opr.c @@ -34,7 +34,7 @@ int port_handle = INVALID_HANDLE_VALUE; *--------------------------------------------------------------------------- */ #define MAX_PORT_NAME_SIZE 32 -#define OPR_TIMEOUT 10L /* 10 seconds */ +#define OPR_TIMEOUT 10L /* 10 seconds */ #define FLASH_ERASE_TIMEOUT 120L /* 120 seconds */ #define STS_MSG_MIN_SIZE 8 @@ -119,9 +119,8 @@ bool opr_open_port(const char *port_name, struct comport_fields port_cfg) if (port_handle <= 0) { display_color_msg(FAIL, "\nERROR: COM Port failed to open.\n"); - DISPLAY_MSG( - ("Please select the right serial port or check if " - "other serial\n")); + DISPLAY_MSG(("Please select the right serial port or check if " + "other serial\n")); DISPLAY_MSG(("communication applications are opened.\n")); return false; } @@ -150,13 +149,13 @@ bool opr_write_chunk(uint8_t *buffer, uint32_t addr, uint32_t size) struct command_node wr_cmd_buf; if (size > MAX_RW_DATA_SIZE) { - display_color_msg(FAIL, - "ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE); + display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n", + MAX_RW_DATA_SIZE); } /* Initialize response size */ wr_cmd_buf.resp_size = 1; - cmd_create_write(addr, size, buffer, - wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size); + cmd_create_write(addr, size, buffer, wr_cmd_buf.cmd, + &wr_cmd_buf.cmd_size); return opr_send_cmds(&wr_cmd_buf, 1); } @@ -179,13 +178,13 @@ bool opr_read_chunk(uint8_t *buffer, uint32_t addr, uint32_t size) struct command_node rd_cmd_buf; if (size > MAX_RW_DATA_SIZE) { - display_color_msg(FAIL, - "ERROR: Block cannot exceed %d\n", MAX_RW_DATA_SIZE); + display_color_msg(FAIL, "ERROR: Block cannot exceed %d\n", + MAX_RW_DATA_SIZE); return false; } - cmd_create_read(addr, ((uint8_t)size - 1), - rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size); + cmd_create_read(addr, ((uint8_t)size - 1), rd_cmd_buf.cmd, + &rd_cmd_buf.cmd_size); rd_cmd_buf.resp_size = size + 3; if (opr_send_cmds(&rd_cmd_buf, 1)) { if (resp_buf[0] == (uint8_t)(UFPP_READ_CMD)) { @@ -228,7 +227,7 @@ void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size) wr_cmd_buf.resp_size = 1; DISPLAY_MSG(("Writing [%d] bytes in [%d] packets\n", size, - ((size + (block_size - 1)) / block_size))); + ((size + (block_size - 1)) / block_size))); /* Read first token from string */ if (console) @@ -248,21 +247,21 @@ void opr_write_mem(uint8_t *buffer, uint32_t addr, uint32_t size) /* Prepare the next iteration */ token = strtok(NULL, seps); } - write_size = (size_remain > block_size) ? - block_size : size_remain; + write_size = (size_remain > block_size) ? block_size : + size_remain; if (console) { cmd_create_write(cur_addr, write_size, data_buf, - wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size); + wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size); } else { cmd_create_write(cur_addr, write_size, buffer, - wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size); + wr_cmd_buf.cmd, &wr_cmd_buf.cmd_size); buffer += write_size; } if (opr_send_cmds(&wr_cmd_buf, 1) != true) break; cmd_disp_write(resp_buf, write_size, cmd_idx, - ((size + (block_size - 1)) / block_size)); + ((size + (block_size - 1)) / block_size)); cur_addr += write_size; size_remain -= write_size; cmd_idx++; @@ -302,7 +301,8 @@ void opr_read_mem(char *output, uint32_t addr, uint32_t size) output_file_id = fopen(output, "w+b"); if (output_file_id == NULL) { - display_color_msg(FAIL, + display_color_msg( + FAIL, "ERROR: could not open output file [%s]\n", output); return; @@ -310,21 +310,22 @@ void opr_read_mem(char *output, uint32_t addr, uint32_t size) } DISPLAY_MSG(("Reading [%d] bytes in [%d] packets\n", size, - ((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE))); + ((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE))); for (cur_addr = addr; cur_addr < (addr + size); - cur_addr += MAX_RW_DATA_SIZE) { + cur_addr += MAX_RW_DATA_SIZE) { bytes_left = (uint32_t)(addr + size - cur_addr); read_size = MIN(bytes_left, MAX_RW_DATA_SIZE); cmd_create_read(cur_addr, ((uint8_t)read_size - 1), - rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size); + rd_cmd_buf.cmd, &rd_cmd_buf.cmd_size); rd_cmd_buf.resp_size = read_size + 3; if (opr_send_cmds(&rd_cmd_buf, 1) != true) break; - cmd_disp_read(resp_buf, read_size, cmd_idx, + cmd_disp_read( + resp_buf, read_size, cmd_idx, ((size + (MAX_RW_DATA_SIZE - 1)) / MAX_RW_DATA_SIZE)); if (console) @@ -386,8 +387,8 @@ bool opr_execute_return(uint32_t addr) * Check the response command code is UFPP_FCALL_RSLT_CMD and * the return value from monitor is 0x03. (program finish and verify ok) */ - if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD) - || resp_buf[2] != 0x03) + if (resp_buf[1] != (uint8_t)(UFPP_FCALL_RSLT_CMD) || + resp_buf[2] != 0x03) return false; return true; } @@ -473,29 +474,31 @@ bool opr_scan_baudrate(void) sr = opr_check_sync(baud); step = (baud * BR_BIG_STEP) / 100; if (sr == SR_OK) { - printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n", - baud, resp_buf[0]); + printf("SR_OK: Baud rate - %d, resp_buf - 0x%x\n", baud, + resp_buf[0]); synched = true; step = (baud * BR_SMALL_STEP) / 100; } else if (sr == SR_WRONG_DATA) { printf("SR_WRONG_DATA: Baud rate - %d, resp_buf - " - "0x%x\n", baud, resp_buf[0]); + "0x%x\n", + baud, resp_buf[0]); data_received = true; step = (baud * BR_MEDIUM_STEP) / 100; } else if (sr == SR_TIMEOUT) { printf("SR_TIMEOUT: Baud rate - %d, resp_buf - 0x%x\n", - baud, resp_buf[0]); + baud, resp_buf[0]); if (synched || data_received) break; } else if (sr == SR_ERROR) { printf("SR_ERROR: Baud rate - %d, resp_buf - 0x%x\n", - baud, resp_buf[0]); + baud, resp_buf[0]); if (synched || data_received) break; } else printf("Unknown error code: Baud rate - %d, resp_buf - " - "0x%x\n", baud, resp_buf[0]); + "0x%x\n", + baud, resp_buf[0]); } return true; @@ -524,7 +527,7 @@ static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num) for (cmd = 0; cmd < cmd_num; cmd++, cur_cmd++) { if (com_port_write_bin(port_handle, cur_cmd->cmd, - cur_cmd->cmd_size) == true) { + cur_cmd->cmd_size) == true) { time(&start); do { @@ -533,15 +536,17 @@ static bool opr_send_cmds(struct command_node *cmd_buf, uint32_t cmd_num) } while ((read < cur_cmd->resp_size) && (elapsed_time <= OPR_TIMEOUT)); com_port_read_bin(port_handle, resp_buf, - cur_cmd->resp_size); + cur_cmd->resp_size); if (elapsed_time > OPR_TIMEOUT) - display_color_msg(FAIL, + display_color_msg( + FAIL, "ERROR: [%d] bytes received for read, " "[%d] bytes are expected\n", read, cur_cmd->resp_size); } else { - display_color_msg(FAIL, + display_color_msg( + FAIL, "ERROR: Failed to send Command number %d\n", cmd); return false; -- cgit v1.2.1 From 778efec4f606cdf42ad499e45fc0c59960bd8160 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:42 -0600 Subject: board/boten/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifddf98b805bece3d0d6808d472ca8a6b46579006 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728088 Reviewed-by: Jeremy Bettis --- board/boten/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/boten/cbi_ssfc.c b/board/boten/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/boten/cbi_ssfc.c +++ b/board/boten/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 65135e2c0482c5d6c80bf0049136a88a0a4301f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:51 -0600 Subject: driver/usb_mux/ps8822.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24ae2b1082c89719fdd2b373a4a152292cf4d67f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730170 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8822.h | 64 ++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/driver/usb_mux/ps8822.h b/driver/usb_mux/ps8822.h index 86b911db70..282a30e642 100644 --- a/driver/usb_mux/ps8822.h +++ b/driver/usb_mux/ps8822.h @@ -11,48 +11,48 @@ #include "usb_mux.h" -#define PS8822_I2C_ADDR0_FLAG 0x10 -#define PS8822_I2C_ADDR1_FLAG 0x18 -#define PS8822_I2C_ADDR2_FLAG 0x58 -#define PS8822_I2C_ADDR3_FLAG 0x60 +#define PS8822_I2C_ADDR0_FLAG 0x10 +#define PS8822_I2C_ADDR1_FLAG 0x18 +#define PS8822_I2C_ADDR2_FLAG 0x58 +#define PS8822_I2C_ADDR3_FLAG 0x60 -#define PS8822_REG_PAGE0 0x00 +#define PS8822_REG_PAGE0 0x00 /* Mode register for setting mux */ -#define PS8822_REG_MODE 0x01 -#define PS8822_MODE_ALT_DP_EN BIT(7) -#define PS8822_MODE_USB_EN BIT(6) -#define PS8822_MODE_FLIP BIT(5) -#define PS8822_MODE_PIN_E BIT(4) +#define PS8822_REG_MODE 0x01 +#define PS8822_MODE_ALT_DP_EN BIT(7) +#define PS8822_MODE_USB_EN BIT(6) +#define PS8822_MODE_FLIP BIT(5) +#define PS8822_MODE_PIN_E BIT(4) -#define PS8822_REG_CONFIG 0x02 +#define PS8822_REG_CONFIG 0x02 #define PS8822_CONFIG_HPD_IN_DIS BIT(7) -#define PS8822_CONFIG_DP_PLUG BIT(6) +#define PS8822_CONFIG_DP_PLUG BIT(6) -#define PS8822_REG_DEV_ID1 0x06 -#define PS8822_REG_DEV_ID2 0x07 -#define PS8822_REG_DEV_ID3 0x08 -#define PS8822_REG_DEV_ID4 0x09 -#define PS8822_REG_DEV_ID5 0x0A -#define PS8822_REG_DEV_ID6 0x0B +#define PS8822_REG_DEV_ID1 0x06 +#define PS8822_REG_DEV_ID2 0x07 +#define PS8822_REG_DEV_ID3 0x08 +#define PS8822_REG_DEV_ID4 0x09 +#define PS8822_REG_DEV_ID5 0x0A +#define PS8822_REG_DEV_ID6 0x0B #define PS8822_ID_LEN 6 -#define PS8822_REG_PAGE1 0x01 -#define PS8822_REG_DP_EQ 0xB6 -#define PS8822_DP_EQ_AUTO_EN BIT(7) +#define PS8822_REG_PAGE1 0x01 +#define PS8822_REG_DP_EQ 0xB6 +#define PS8822_DP_EQ_AUTO_EN BIT(7) -#define PS8822_DPEQ_LEVEL_UP_9DB 0x00 -#define PS8822_DPEQ_LEVEL_UP_11DB 0x01 -#define PS8822_DPEQ_LEVEL_UP_12DB 0x02 -#define PS8822_DPEQ_LEVEL_UP_14DB 0x03 -#define PS8822_DPEQ_LEVEL_UP_17DB 0x04 -#define PS8822_DPEQ_LEVEL_UP_18DB 0x05 -#define PS8822_DPEQ_LEVEL_UP_19DB 0x06 -#define PS8822_DPEQ_LEVEL_UP_20DB 0x07 -#define PS8822_DPEQ_LEVEL_UP_21DB 0x08 -#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F -#define PS8822_REG_DP_EQ_SHIFT 3 +#define PS8822_DPEQ_LEVEL_UP_9DB 0x00 +#define PS8822_DPEQ_LEVEL_UP_11DB 0x01 +#define PS8822_DPEQ_LEVEL_UP_12DB 0x02 +#define PS8822_DPEQ_LEVEL_UP_14DB 0x03 +#define PS8822_DPEQ_LEVEL_UP_17DB 0x04 +#define PS8822_DPEQ_LEVEL_UP_18DB 0x05 +#define PS8822_DPEQ_LEVEL_UP_19DB 0x06 +#define PS8822_DPEQ_LEVEL_UP_20DB 0x07 +#define PS8822_DPEQ_LEVEL_UP_21DB 0x08 +#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F +#define PS8822_REG_DP_EQ_SHIFT 3 /** * Set DP Rx Equalization value -- cgit v1.2.1 From d7b77b62accbbe1d8086afffe288060a93cf7670 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:23 -0600 Subject: zephyr/shim/src/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4cfdd84ca0fdb48d3d2ec950bb4ffad3e25b5493 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730861 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/battery.c | 43 ++++++++++++++++++++----------------------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/zephyr/shim/src/battery.c b/zephyr/shim/src/battery.c index 73f72f2e81..37cc4db15a 100644 --- a/zephyr/shim/src/battery.c +++ b/zephyr/shim/src/battery.c @@ -8,7 +8,7 @@ #include "battery_fuel_gauge.h" #define NODE_FUEL_GAUGE(node) \ -{ \ + { \ .manuf_name = DT_PROP(node, manuf_name), \ .device_name = DT_PROP(node, device_name), \ .ship_mode = { \ @@ -34,32 +34,29 @@ (.imbalance_mv = DT_STRING_TOKEN(node, imbalance_mv),), ()) \ }, -#define NODE_BATT_INFO(node) \ -{ \ - .voltage_max = DT_PROP(node, voltage_max), \ - .voltage_normal = DT_PROP(node, voltage_normal), \ - .voltage_min = DT_PROP(node, voltage_min), \ - .precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \ - .precharge_current = DT_PROP_OR(node, precharge_current, 0), \ - .start_charging_min_c = DT_PROP(node, start_charging_min_c), \ - .start_charging_max_c = DT_PROP(node, start_charging_max_c), \ - .charging_min_c = DT_PROP(node, charging_min_c), \ - .charging_max_c = DT_PROP(node, charging_max_c), \ - .discharging_min_c = DT_PROP(node, discharging_min_c), \ - .discharging_max_c = DT_PROP(node, discharging_max_c), \ -}, +#define NODE_BATT_INFO(node) \ + { \ + .voltage_max = DT_PROP(node, voltage_max), \ + .voltage_normal = DT_PROP(node, voltage_normal), \ + .voltage_min = DT_PROP(node, voltage_min), \ + .precharge_voltage = DT_PROP_OR(node, precharge_voltage, 0), \ + .precharge_current = DT_PROP_OR(node, precharge_current, 0), \ + .start_charging_min_c = DT_PROP(node, start_charging_min_c), \ + .start_charging_max_c = DT_PROP(node, start_charging_max_c), \ + .charging_min_c = DT_PROP(node, charging_min_c), \ + .charging_max_c = DT_PROP(node, charging_max_c), \ + .discharging_min_c = DT_PROP(node, discharging_min_c), \ + .discharging_max_c = DT_PROP(node, discharging_max_c), \ + }, -#define NODE_BATT_PARAMS(node) \ -{ \ - .fuel_gauge = NODE_FUEL_GAUGE(node) \ - .batt_info = NODE_BATT_INFO(node) \ -}, +#define NODE_BATT_PARAMS(node) \ + { .fuel_gauge = NODE_FUEL_GAUGE(node).batt_info = \ + NODE_BATT_INFO(node) }, #if DT_HAS_COMPAT_STATUS_OKAY(battery_smart) -const struct board_batt_params board_battery_info[] = { - DT_FOREACH_STATUS_OKAY(battery_smart, NODE_BATT_PARAMS) -}; +const struct board_batt_params board_battery_info[] = { DT_FOREACH_STATUS_OKAY( + battery_smart, NODE_BATT_PARAMS) }; #if DT_NODE_EXISTS(DT_NODELABEL(default_battery)) #define BAT_ENUM(node) DT_CAT(BATTERY_, node) -- cgit v1.2.1 From f346414e62c3306ef3318fcb6a83a0db6301d1c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:24 -0600 Subject: driver/tcpm/anx74xx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0890079ec8e623ccd7b778b8561b9bd3a30c29f3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730088 Reviewed-by: Jeremy Bettis --- driver/tcpm/anx74xx.h | 323 +++++++++++++++++++++++++------------------------- 1 file changed, 160 insertions(+), 163 deletions(-) diff --git a/driver/tcpm/anx74xx.h b/driver/tcpm/anx74xx.h index 19ac3e304f..7cd979bbbf 100644 --- a/driver/tcpm/anx74xx.h +++ b/driver/tcpm/anx74xx.h @@ -18,42 +18,42 @@ #define ANX74XX_I2C_ADDR3_FLAGS 0x3E #define ANX74XX_I2C_ADDR4_FLAGS 0x40 -#define ANX74XX_REG_IRQ_POL_LOW 0x00 -#define ANX74XX_REG_IRQ_POL_HIGH 0x02 +#define ANX74XX_REG_IRQ_POL_LOW 0x00 +#define ANX74XX_REG_IRQ_POL_HIGH 0x02 -#define ANX74XX_REG_VENDOR_ID_L 0x00 -#define ANX74XX_REG_VENDOR_ID_H 0x01 -#define ANX74XX_VENDOR_ID 0xAAAA +#define ANX74XX_REG_VENDOR_ID_L 0x00 +#define ANX74XX_REG_VENDOR_ID_H 0x01 +#define ANX74XX_VENDOR_ID 0xAAAA /* ANX F/W version：0x50:0x44 which contains otp firmware version */ -#define ANX74XX_REG_FW_VERSION 0x44 +#define ANX74XX_REG_FW_VERSION 0x44 -#define ANX74XX_REG_IRQ_STATUS 0x53 +#define ANX74XX_REG_IRQ_STATUS 0x53 -#define ANX74XX_REG_INTP_VCONN_CTRL 0x33 -#define ANX74XX_REG_VCONN_DISABLE 0x0f -#define ANX74XX_REG_VCONN_1_ENABLE BIT(4) -#define ANX74XX_REG_VCONN_2_ENABLE BIT(5) -#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2) +#define ANX74XX_REG_INTP_VCONN_CTRL 0x33 +#define ANX74XX_REG_VCONN_DISABLE 0x0f +#define ANX74XX_REG_VCONN_1_ENABLE BIT(4) +#define ANX74XX_REG_VCONN_2_ENABLE BIT(5) +#define ANX74XX_REG_R_INTERRUPT_OPEN_DRAIN BIT(2) -#define ANX74XX_STANDBY_MODE (0) -#define ANX74XX_NORMAL_MODE (1) +#define ANX74XX_STANDBY_MODE (0) +#define ANX74XX_NORMAL_MODE (1) -#define ANX74XX_REG_TX_CTRL_1 0x81 -#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1) -#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2) +#define ANX74XX_REG_TX_CTRL_1 0x81 +#define ANX74XX_REG_TX_HARD_RESET_REQ BIT(1) +#define ANX74XX_REG_TX_CABLE_RESET_REQ BIT(2) -#define ANX74XX_REG_TX_CTRL_2 0x82 -#define ANX74XX_REG_TX_WR_FIFO 0x83 -#define ANX74XX_REG_TX_FIFO_CTRL 0x9a -#define ANX74XX_REG_TX_HEADER_L 0x2c -#define ANX74XX_REG_TX_HEADER_H 0x2d -#define ANX74XX_REG_TX_START_ADDR_0 0x6d -#define ANX74XX_REG_TX_START_ADDR_1 0xd0 +#define ANX74XX_REG_TX_CTRL_2 0x82 +#define ANX74XX_REG_TX_WR_FIFO 0x83 +#define ANX74XX_REG_TX_FIFO_CTRL 0x9a +#define ANX74XX_REG_TX_HEADER_L 0x2c +#define ANX74XX_REG_TX_HEADER_H 0x2d +#define ANX74XX_REG_TX_START_ADDR_0 0x6d +#define ANX74XX_REG_TX_START_ADDR_1 0xd0 -#define ANX74XX_REG_CTRL_COMMAND 0xdb -#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0) -#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1) +#define ANX74XX_REG_CTRL_COMMAND 0xdb +#define ANX74XX_REG_TX_SEND_DATA_REQ BIT(0) +#define ANX74XX_REG_TX_HARD_RST_REQ BIT(1) #define ANX74XX_REG_TX_BIST_CTRL 0x9D #define ANX74XX_REG_TX_BIST_MODE BIT(4) @@ -62,166 +62,163 @@ #define ANX74XX_REG_TX_BIST_ENABLE BIT(1) #define ANX74XX_REG_TX_BIST_START BIT(0) -#define ANX74XX_REG_PD_HEADER 0x69 -#define ANX74XX_REG_PD_RX_DATA_OBJ 0x11 -#define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d - -#define ANX74XX_REG_ANALOG_STATUS 0x40 -#define ANX74XX_REG_VBUS_STATUS BIT(4) -#define ANX74XX_REG_CC_PULL_RD 0xfd -#define ANX74XX_REG_CC_PULL_RP 0x02 - - -#define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94 -#define ANX74XX_REG_REPLY_SOP_EN BIT(3) -#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4) -#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5) - -#define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c -#define ANX74XX_REG_SPEC_REV_BIT_POS (3) -#define ANX74XX_REG_DATA_ROLE_BIT_POS (2) -#define ANX74XX_REG_PWR_ROLE_BIT_POS (1) -#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0) +#define ANX74XX_REG_PD_HEADER 0x69 +#define ANX74XX_REG_PD_RX_DATA_OBJ 0x11 +#define ANX74XX_REG_PD_RX_DATA_OBJ_M 0x4d + +#define ANX74XX_REG_ANALOG_STATUS 0x40 +#define ANX74XX_REG_VBUS_STATUS BIT(4) +#define ANX74XX_REG_CC_PULL_RD 0xfd +#define ANX74XX_REG_CC_PULL_RP 0x02 + +#define ANX74XX_REG_TX_AUTO_GOODCRC_2 0x94 +#define ANX74XX_REG_REPLY_SOP_EN BIT(3) +#define ANX74XX_REG_REPLY_SOP_1_EN BIT(4) +#define ANX74XX_REG_REPLY_SOP_2_EN BIT(5) + +#define ANX74XX_REG_TX_AUTO_GOODCRC_1 0x9c +#define ANX74XX_REG_SPEC_REV_BIT_POS (3) +#define ANX74XX_REG_DATA_ROLE_BIT_POS (2) +#define ANX74XX_REG_PWR_ROLE_BIT_POS (1) +#define ANX74XX_REG_AUTO_GOODCRC_EN BIT(0) #define ANX74XX_REG_AUTO_GOODCRC_SET(drole, prole) \ ((PD_REV20 << ANX74XX_REG_SPEC_REV_BIT_POS) | \ - ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \ - ((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS) | \ - ANX74XX_REG_AUTO_GOODCRC_EN) - - -#define ANX74XX_REG_ANALOG_CTRL_0 0x41 -#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7) - -#define ANX74XX_REG_ANALOG_CTRL_1 0x42 -#define ANX74XX_REG_ANALOG_CTRL_5 0x46 -#define ANX74XX_REG_ANALOG_CTRL_6 0x47 -#define ANX74XX_REG_CC_PULL_RP_36K 0x00 -#define ANX74XX_REG_CC_PULL_RP_12K 0x01 -#define ANX74XX_REG_CC_PULL_RP_4K 0x02 - -#define ANX74XX_REG_R_SWITCH_CC_CLR 0x0f -#define ANX74XX_REG_R_SWITCH_CC2_SET 0x10 -#define ANX74XX_REG_R_SWITCH_CC1_SET 0x20 -#define ANX74XX_REG_AUX_SWAP_SET_CC1 0x30 -#define ANX74XX_REG_AUX_SWAP_SET_CC2 0xc0 - -#define ANX74XX_REG_ANALOG_CTRL_11 0x4c -#define ANX74XX_REG_ANALOG_CTRL_12 0x4d - -#define ANX74XX_REG_MUX_ML0_RX2 BIT(0) -#define ANX74XX_REG_MUX_ML0_RX1 BIT(1) -#define ANX74XX_REG_MUX_ML3_RX2 BIT(2) -#define ANX74XX_REG_MUX_ML3_RX1 BIT(3) -#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4) -#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5) -#define ANX74XX_REG_MUX_ML1_TX2 BIT(6) -#define ANX74XX_REG_MUX_ML1_TX1 BIT(7) - -#define ANX74XX_REG_MUX_ML2_TX2 BIT(4) -#define ANX74XX_REG_MUX_ML2_TX1 BIT(5) -#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6) -#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7) - -#define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a -#define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01 -#define ANX74XX_REG_TX_MODE_ENABLE 0x04 - -#define ANX74XX_REG_SELECT_CC1 0x02 - -#define ANX74XX_REG_GPIO_CTRL_4_5 0x3f -#define ANX74XX_REG_VBUS_OP_ENABLE 0x04 -#define ANX74XX_REG_VBUS_GPIO_MODE 0xfe - -#define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b -#define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c -#define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e -#define ANX74XX_REG_EXT_SOP BIT(6) -#define ANX74XX_REG_EXT_SOP_PRIME BIT(7) -#define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e -#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0) -#define ANX74XX_REG_EXT_HARD_RST BIT(2) -#define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f -#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2) - -#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b -#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0) -#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1) -#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2) -#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3) -#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c - -#define ANX74XX_REG_CLEAR_SET_BITS 0xff -#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6) -#define ANX74XX_REG_ALERT_MSG_RECV BIT(5) -#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4) -#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3) -#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2) -#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1) -#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0) - -#define ANX74XX_REG_ANALOG_CTRL_2 0x43 -#define ANX74XX_REG_MODE_TRANS 0x01 - -#define ANX74XX_REG_SET_VBUS 0x20 - -#define ANX74XX_REG_ANALOG_CTRL_7 0x48 -#define ANX74XX_REG_STATUS_CC_RD 0x01 -#define ANX74XX_REG_STATUS_CC_RA 0x03 -#define ANX74XX_REG_STATUS_CC1(reg) ((reg & 0x0C) >> 2) -#define ANX74XX_REG_STATUS_CC2(reg) ((reg & 0x03) >> 0) - -#define ANX74XX_REG_HPD_CONTROL 0xfd - -#define ANX74XX_REG_HPD_CTRL_0 0x36 -#define ANX74XX_REG_DISCHARGE_CTRL 0x80 -#define ANX74XX_REG_HPD_OP_MODE 0x08 -#define ANX74XX_REG_HPD_DEFAULT 0x00 -#define ANX74XX_REG_HPD_OUT_DATA 0x10 + ((drole) << ANX74XX_REG_DATA_ROLE_BIT_POS) | \ + ((prole) << ANX74XX_REG_PWR_ROLE_BIT_POS) | \ + ANX74XX_REG_AUTO_GOODCRC_EN) + +#define ANX74XX_REG_ANALOG_CTRL_0 0x41 +#define ANX74XX_REG_R_PIN_CABLE_DET BIT(7) + +#define ANX74XX_REG_ANALOG_CTRL_1 0x42 +#define ANX74XX_REG_ANALOG_CTRL_5 0x46 +#define ANX74XX_REG_ANALOG_CTRL_6 0x47 +#define ANX74XX_REG_CC_PULL_RP_36K 0x00 +#define ANX74XX_REG_CC_PULL_RP_12K 0x01 +#define ANX74XX_REG_CC_PULL_RP_4K 0x02 + +#define ANX74XX_REG_R_SWITCH_CC_CLR 0x0f +#define ANX74XX_REG_R_SWITCH_CC2_SET 0x10 +#define ANX74XX_REG_R_SWITCH_CC1_SET 0x20 +#define ANX74XX_REG_AUX_SWAP_SET_CC1 0x30 +#define ANX74XX_REG_AUX_SWAP_SET_CC2 0xc0 + +#define ANX74XX_REG_ANALOG_CTRL_11 0x4c +#define ANX74XX_REG_ANALOG_CTRL_12 0x4d + +#define ANX74XX_REG_MUX_ML0_RX2 BIT(0) +#define ANX74XX_REG_MUX_ML0_RX1 BIT(1) +#define ANX74XX_REG_MUX_ML3_RX2 BIT(2) +#define ANX74XX_REG_MUX_ML3_RX1 BIT(3) +#define ANX74XX_REG_MUX_SSRX_RX2 BIT(4) +#define ANX74XX_REG_MUX_SSRX_RX1 BIT(5) +#define ANX74XX_REG_MUX_ML1_TX2 BIT(6) +#define ANX74XX_REG_MUX_ML1_TX1 BIT(7) + +#define ANX74XX_REG_MUX_ML2_TX2 BIT(4) +#define ANX74XX_REG_MUX_ML2_TX1 BIT(5) +#define ANX74XX_REG_MUX_SSTX_TX2 BIT(6) +#define ANX74XX_REG_MUX_SSTX_TX1 BIT(7) + +#define ANX74XX_REG_CC_SOFTWARE_CTRL 0x4a +#define ANX74XX_REG_CC_SW_CTRL_ENABLE 0x01 +#define ANX74XX_REG_TX_MODE_ENABLE 0x04 + +#define ANX74XX_REG_SELECT_CC1 0x02 + +#define ANX74XX_REG_GPIO_CTRL_4_5 0x3f +#define ANX74XX_REG_VBUS_OP_ENABLE 0x04 +#define ANX74XX_REG_VBUS_GPIO_MODE 0xfe + +#define ANX74XX_REG_IRQ_EXT_MASK_1 0x3b +#define ANX74XX_REG_IRQ_EXT_MASK_2 0x3c +#define ANX74XX_REG_IRQ_EXT_SOURCE_1 0x3e +#define ANX74XX_REG_EXT_SOP BIT(6) +#define ANX74XX_REG_EXT_SOP_PRIME BIT(7) +#define ANX74XX_REG_IRQ_EXT_SOURCE_2 0x4e +#define ANX74XX_REG_EXT_SOP_PRIME_PRIME BIT(0) +#define ANX74XX_REG_EXT_HARD_RST BIT(2) +#define ANX74XX_REG_IRQ_EXT_SOURCE_3 0x4f +#define ANX74XX_REG_CLEAR_SOFT_IRQ BIT(2) + +#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG 0x6b +#define ANX74XX_REG_IRQ_CC_MSG_INT BIT(0) +#define ANX74XX_REG_IRQ_CC_STATUS_INT BIT(1) +#define ANX74XX_REG_IRQ_GOOD_CRC_INT BIT(2) +#define ANX74XX_REG_IRQ_TX_FAIL_INT BIT(3) +#define ANX74XX_REG_IRQ_SOURCE_RECV_MSG_MASK 0x6c + +#define ANX74XX_REG_CLEAR_SET_BITS 0xff +#define ANX74XX_REG_ALERT_HARD_RST_RECV BIT(6) +#define ANX74XX_REG_ALERT_MSG_RECV BIT(5) +#define ANX74XX_REG_ALERT_TX_MSG_ERROR BIT(4) +#define ANX74XX_REG_ALERT_TX_ACK_RECV BIT(3) +#define ANX74XX_REG_ALERT_TX_CABLE_RESETOK BIT(2) +#define ANX74XX_REG_ALERT_TX_HARD_RESETOK BIT(1) +#define ANX74XX_REG_ALERT_CC_CHANGE BIT(0) + +#define ANX74XX_REG_ANALOG_CTRL_2 0x43 +#define ANX74XX_REG_MODE_TRANS 0x01 + +#define ANX74XX_REG_SET_VBUS 0x20 + +#define ANX74XX_REG_ANALOG_CTRL_7 0x48 +#define ANX74XX_REG_STATUS_CC_RD 0x01 +#define ANX74XX_REG_STATUS_CC_RA 0x03 +#define ANX74XX_REG_STATUS_CC1(reg) ((reg & 0x0C) >> 2) +#define ANX74XX_REG_STATUS_CC2(reg) ((reg & 0x03) >> 0) + +#define ANX74XX_REG_HPD_CONTROL 0xfd + +#define ANX74XX_REG_HPD_CTRL_0 0x36 +#define ANX74XX_REG_DISCHARGE_CTRL 0x80 +#define ANX74XX_REG_HPD_OP_MODE 0x08 +#define ANX74XX_REG_HPD_DEFAULT 0x00 +#define ANX74XX_REG_HPD_OUT_DATA 0x10 #define ANX74XX_REG_RECVD_MSG_INT 0x98 -#define ANX74XX_REG_CC_STATUS 0x99 -#define ANX74XX_REG_CTRL_FW 0x2E +#define ANX74XX_REG_CC_STATUS 0x99 +#define ANX74XX_REG_CTRL_FW 0x2E #define CLEAR_RX_BUFFER (1) -#define ANX74XX_REG_POWER_DOWN_CTRL 0x0d -#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7) -#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6) -#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5) -#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4) -#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3) -#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2) +#define ANX74XX_REG_POWER_DOWN_CTRL 0x0d +#define ANX74XX_REG_STATUS_CC1_VRD_USB BIT(7) +#define ANX74XX_REG_STATUS_CC1_VRD_1P5 BIT(6) +#define ANX74XX_REG_STATUS_CC1_VRD_3P0 BIT(5) +#define ANX74XX_REG_STATUS_CC2_VRD_USB BIT(4) +#define ANX74XX_REG_STATUS_CC2_VRD_1P5 BIT(3) +#define ANX74XX_REG_STATUS_CC2_VRD_3P0 BIT(2) /* defined in the inter-bock Spec: 4.2.10 CC Detect Status */ -#define ANX74XX_REG_CC_STATUS_MASK 0xf -#define BIT_VALUE_OF_SRC_CC_RD 0x01 -#define BIT_VALUE_OF_SRC_CC_RA 0x02 +#define ANX74XX_REG_CC_STATUS_MASK 0xf +#define BIT_VALUE_OF_SRC_CC_RD 0x01 +#define BIT_VALUE_OF_SRC_CC_RA 0x02 #define BIT_VALUE_OF_SNK_CC_DEFAULT 0x04 -#define BIT_VALUE_OF_SNK_CC_1_P_5 0x08 -#define BIT_VALUE_OF_SNK_CC_3_P_0 0x0C -#define ANX74XX_CC_RA_MASK (BIT_VALUE_OF_SRC_CC_RA | \ - (BIT_VALUE_OF_SRC_CC_RA << 4)) -#define ANX74XX_CC_RD_MASK (BIT_VALUE_OF_SRC_CC_RD | \ - (BIT_VALUE_OF_SRC_CC_RD << 4)) +#define BIT_VALUE_OF_SNK_CC_1_P_5 0x08 +#define BIT_VALUE_OF_SNK_CC_3_P_0 0x0C +#define ANX74XX_CC_RA_MASK \ + (BIT_VALUE_OF_SRC_CC_RA | (BIT_VALUE_OF_SRC_CC_RA << 4)) +#define ANX74XX_CC_RD_MASK \ + (BIT_VALUE_OF_SRC_CC_RD | (BIT_VALUE_OF_SRC_CC_RD << 4)) /* * RESETN low to PWR_EN low delay */ -#define ANX74XX_RST_L_PWR_L_DELAY_MS 1 +#define ANX74XX_RST_L_PWR_L_DELAY_MS 1 /* * minimum power off-to-on delay to reset chip */ -#define ANX74XX_PWR_L_PWR_H_DELAY_MS 10 +#define ANX74XX_PWR_L_PWR_H_DELAY_MS 10 /* * parameter T4: PWR_EN high to RESETN high delay */ -#define ANX74XX_PWR_H_RST_H_DELAY_MS 10 +#define ANX74XX_PWR_H_RST_H_DELAY_MS 10 extern const struct tcpm_drv anx74xx_tcpm_drv; extern const struct usb_mux_driver anx74xx_tcpm_usb_mux_driver; void anx74xx_tcpc_set_vbus(int port, int enable); void anx74xx_tcpc_clear_hpd_status(int port); void anx74xx_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #ifdef CONFIG_CMD_I2C_STRESS_TEST_TCPC extern struct i2c_stress_test_dev anx74xx_i2c_stress_test_dev; -- cgit v1.2.1 From 2680606d60c58dbf918642f92d0ef0cd7c6f7b63 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:24:17 -0600 Subject: chip/npcx/gpio_chip-npcx9.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id42226c06008f6a83955f1c12d6a291f9c90e536 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729382 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx9.h | 351 +++++++++++++++++++++++--------------------- 1 file changed, 187 insertions(+), 164 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h index 005a03d83e..93ac5aadba 100644 --- a/chip/npcx/gpio_chip-npcx9.h +++ b/chip/npcx/gpio_chip-npcx9.h @@ -200,7 +200,7 @@ /* Pin-Mux for PWM1/SMB6_0 */ #if NPCX9_PWM1_SEL #define NPCX_ALT_GPIO_C_1 /* No I2CSDA since GPIOC2 used as PWM1 */ -#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ +#define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(4, PWM1_SL)) /* PWM1 */ #else #define NPCX_ALT_GPIO_C_1 ALT(C, 1, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SDA0 */ #define NPCX_ALT_GPIO_C_2 ALT(C, 2, NPCX_ALT(2, I2C6_0_SL)) /* SMB6SCL0 */ @@ -219,17 +219,17 @@ #define NPCX_ALT_GPIO_3_7 ALT(3, 7, NPCX_ALT(F, ADC5_SL)) /* ADC5 */ #define NPCX_ALT_GPIO_3_4 ALT(3, 4, NPCX_ALT(F, ADC6_SL)) /* ADC6 */ #endif -#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8 */ -#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7 */ -#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9 */ +#define NPCX_ALT_GPIO_F_1 ALT(F, 1, NPCX_ALT(F, ADC8_SL)) /* ADC8 */ +#define NPCX_ALT_GPIO_E_1 ALT(E, 1, NPCX_ALT(F, ADC7_SL)) /* ADC7 */ +#define NPCX_ALT_GPIO_F_0 ALT(F, 0, NPCX_ALT(F, ADC9_SL)) /* ADC9 */ #define NPCX_ALT_GPIO_E_0 ALT(E, 0, NPCX_ALT(F, ADC10_SL)) /* AD10 */ #define NPCX_ALT_GPIO_C_7 ALT(C, 7, NPCX_ALT(F, ADC11_SL)) /* AD11 */ /* PS/2 Module */ -#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */ -#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */ -#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */ -#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ +#define NPCX_ALT_GPIO_6_7 ALT(6, 7, NPCX_ALT(3, PS2_0_SL)) /* PS2_CLK0 */ +#define NPCX_ALT_GPIO_7_0 ALT(7, 0, NPCX_ALT(3, PS2_0_SL)) /* PS2_DATA0 */ +#define NPCX_ALT_GPIO_6_2 ALT(6, 2, NPCX_ALT(3, PS2_1_SL)) /* PS2_CLK1 */ +#define NPCX_ALT_GPIO_6_3 ALT(6, 3, NPCX_ALT(3, PS2_1_SL)) /* PS2_DATA1 */ #if defined(CONFIG_PS2) && defined(NPCX_PS2_MODULE_3) #define NPCX_ALT_GPIO_A_7 ALT(A, 7, NPCX_ALT(C, PS2_3_SL2)) /* PS2_DAT3 */ #else @@ -237,12 +237,16 @@ #endif /* UART Module */ -#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 */ -#define NPCX_ALT_GPIO_6_5 ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2))/* CR_SOUT1_SL2 */ -#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */ -#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL */ -#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */ -#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL */ +#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \ + */ +#define NPCX_ALT_GPIO_6_5 \ + ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2)) /* CR_SOUT1_SL2 */ +#define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */ +#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \ + */ +#define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */ +#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \ + */ /* PWM Module */ #define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */ @@ -282,7 +286,7 @@ #define NPCX_ALT_GPIO_1_2 ALT(1, 2, NPCX_ALT_INV(8, NO_KSO07_SL)) /* KSO07 */ /* KSO08 & CR_SOUT */ #define NPCX_ALT_GPIO_1_1 ALT(1, 1, NPCX_ALT_INV(9, NO_KSO08_SL)) - /* KSO09 & CR_SIN */ +/* KSO09 & CR_SIN */ #define NPCX_ALT_GPIO_1_0 ALT(1, 0, NPCX_ALT_INV(9, NO_KSO09_SL)) #define NPCX_ALT_GPIO_0_7 ALT(0, 7, NPCX_ALT_INV(9, NO_KSO10_SL)) /* KSO10 */ #define NPCX_ALT_GPIO_0_6 ALT(0, 6, NPCX_ALT_INV(9, NO_KSO11_SL)) /* KSO11 */ @@ -294,177 +298,196 @@ #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ /* PSL module */ -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 */ -#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ -#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ -#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */ +#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ +#define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ +#define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ +#define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */ /* SPI Module */ #define NPCX_ALT_GPIO_9_5 ALT(9, 5, NPCX_ALT(0, SPIP_SL)) /* SPIP_MISO */ #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ -#define NPCX_ALT_TABLE { \ - NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ - NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ - NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ - NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ - NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ - NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ - NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_C_7 /* ADC11 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ - NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ - NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */ \ - NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */ \ - NPCX_ALT_GPIO_D_7 /* PSL_GPO */ \ - NPCX_ALT_GPIO_E_0 /* ADC10 */ \ - NPCX_ALT_GPIO_E_1 /* ADC7 */ \ - NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ - NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ - NPCX_ALT_GPIO_F_0 /* ADC9 */ \ - NPCX_ALT_GPIO_F_1 /* ADC8 */ \ - NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ - NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ - NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ - NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ -} +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ + NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ + NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 \ + */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ + NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ + NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ + NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ + NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_C_7 /* ADC11 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ + NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ + NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */ \ + NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */ \ + NPCX_ALT_GPIO_D_7 /* PSL_GPO */ \ + NPCX_ALT_GPIO_E_0 /* ADC10 */ \ + NPCX_ALT_GPIO_E_1 /* ADC7 */ \ + NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ + NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ + NPCX_ALT_GPIO_F_0 /* ADC9 */ \ + NPCX_ALT_GPIO_F_1 /* ADC8 */ \ + NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ + NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ + NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ + NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ + } /*****************************************************************************/ /* Macro functions for Low-Voltage mapping table */ /* Low-Voltage GPIO Control 0 */ -#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) -#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) -#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) -#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) -#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) -#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) -#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) -#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) +#define NPCX_LVOL_CTRL_0_0 NPCX_GPIO(B, 5) +#define NPCX_LVOL_CTRL_0_1 NPCX_GPIO(B, 4) +#define NPCX_LVOL_CTRL_0_2 NPCX_GPIO(B, 3) +#define NPCX_LVOL_CTRL_0_3 NPCX_GPIO(B, 2) +#define NPCX_LVOL_CTRL_0_4 NPCX_GPIO(9, 0) +#define NPCX_LVOL_CTRL_0_5 NPCX_GPIO(8, 7) +#define NPCX_LVOL_CTRL_0_6 NPCX_GPIO(0, 0) +#define NPCX_LVOL_CTRL_0_7 NPCX_GPIO(3, 3) /* Low-Voltage GPIO Control 1 */ -#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) -#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) -#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) -#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) -#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) -#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_0 NPCX_GPIO(9, 2) +#define NPCX_LVOL_CTRL_1_1 NPCX_GPIO(9, 1) +#define NPCX_LVOL_CTRL_1_2 NPCX_GPIO(D, 1) +#define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) +#define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) +#define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ -#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) -#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) -#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) -#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) +#define NPCX_LVOL_CTRL_2_0 NPCX_GPIO(7, 4) +#define NPCX_LVOL_CTRL_2_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_3 NPCX_GPIO(7, 3) +#define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) +#define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) +#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_2_7 NPCX_GPIO(3, 4) /* Low-Voltage GPIO Control 3 */ -#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) -#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) -#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) -#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) -#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) -#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) +#define NPCX_LVOL_CTRL_3_0 NPCX_GPIO(C, 6) +#define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) +#define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) +#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_3_4 NPCX_GPIO(8, 2) +#define NPCX_LVOL_CTRL_3_5 NPCX_GPIO(7, 5) +#define NPCX_LVOL_CTRL_3_6 NPCX_GPIO(8, 0) +#define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* Low-Voltage GPIO Control 4 */ -#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) -#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) -#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) -#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) -#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) -#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) -#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) -#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) +#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) +#define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) +#define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) +#define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) +#define NPCX_LVOL_CTRL_4_4 NPCX_GPIO(F, 5) +#define NPCX_LVOL_CTRL_4_5 NPCX_GPIO(F, 4) +#define NPCX_LVOL_CTRL_4_6 NPCX_GPIO(E, 4) +#define NPCX_LVOL_CTRL_4_7 NPCX_GPIO(E, 3) /* Low-Voltage GPIO Control 5 */ -#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) -#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) -#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE -#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_0 NPCX_GPIO(7, 2) +#define NPCX_LVOL_CTRL_5_1 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_2 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_3 NPCX_GPIO(5, 0) +#define NPCX_LVOL_CTRL_5_4 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_5 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_6 NPCX_GPIO_NONE +#define NPCX_LVOL_CTRL_5_7 NPCX_GPIO_NONE /* 6 Low-Voltage Control Groups on npcx7 */ -#define NPCX_LVOL_TABLE { { NPCX_LVOL_CTRL_ITEMS(0), }, \ - { NPCX_LVOL_CTRL_ITEMS(1), }, \ - { NPCX_LVOL_CTRL_ITEMS(2), }, \ - { NPCX_LVOL_CTRL_ITEMS(3), }, \ - { NPCX_LVOL_CTRL_ITEMS(4), }, \ - { NPCX_LVOL_CTRL_ITEMS(5), }, } +#define NPCX_LVOL_TABLE \ + { \ + { \ + NPCX_LVOL_CTRL_ITEMS(0), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(1), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(2), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(3), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(4), \ + }, \ + { \ + NPCX_LVOL_CTRL_ITEMS(5), \ + }, \ + } #endif /* __CROS_EC_GPIO_CHIP_NPCX9_H */ -- cgit v1.2.1 From 7e67c3fa797f906582245e8f9765aa38ee6dcd66 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:44:34 -0600 Subject: core/nds32/math.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If7765817f6b011a170d3efa14c8953cf46dbee89 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729864 Reviewed-by: Jeremy Bettis --- core/nds32/math.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/core/nds32/math.c b/core/nds32/math.c index 496fcc0e5d..c8f695804e 100644 --- a/core/nds32/math.c +++ b/core/nds32/math.c @@ -12,19 +12,19 @@ union ieee_float_shape_type { }; /* Get a 32 bit int from a float. */ -#define GET_FLOAT_WORD(i, d) \ - do { \ +#define GET_FLOAT_WORD(i, d) \ + do { \ union ieee_float_shape_type gf_u; \ - gf_u.value = (d); \ - (i) = gf_u.word; \ + gf_u.value = (d); \ + (i) = gf_u.word; \ } while (0) /* Set a float from a 32 bit int. */ -#define SET_FLOAT_WORD(d, i) \ - do { \ +#define SET_FLOAT_WORD(d, i) \ + do { \ union ieee_float_shape_type sf_u; \ - sf_u.word = (i); \ - (d) = sf_u.value; \ + sf_u.word = (i); \ + (d) = sf_u.value; \ } while (0) float fabsf(float x) -- cgit v1.2.1 From fc8eb69c23b087ca75aa0b9464e02eb1f74c73c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:22 -0600 Subject: test/flash_write_protect.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12e5cccb5652ff539de0321620c37c1e2bc150bd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730501 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/flash_write_protect.c | 1 - 1 file changed, 1 deletion(-) diff --git a/test/flash_write_protect.c b/test/flash_write_protect.c index 888482076f..b8d729331d 100644 --- a/test/flash_write_protect.c +++ b/test/flash_write_protect.c @@ -97,7 +97,6 @@ test_static int test_cbi_wb_asserted_immediately(void) /* Now make sure EC_CBI_WP is asserted immediately. */ TEST_EQ(gpio_get_level(GPIO_EC_CBI_WP), 1, "%d"); - return EC_SUCCESS; } -- cgit v1.2.1 From 997c9ac51f8bcca24745c890ebdfdf8253411a11 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:41:03 -0600 Subject: common/usbc/usb_pd_console.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b5916097879023656b2134dc289609fb5e7798b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729784 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pd_console.c | 65 ++++++++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/common/usbc/usb_pd_console.c b/common/usbc/usb_pd_console.c index 23a02b31e7..332b32c7a3 100644 --- a/common/usbc/usb_pd_console.c +++ b/common/usbc/usb_pd_console.c @@ -16,7 +16,8 @@ #ifndef TEST_USB_PD_CONSOLE static #endif -int command_pd(int argc, char **argv) + int + command_pd(int argc, char **argv) { int port; char *e; @@ -43,7 +44,7 @@ int command_pd(int argc, char **argv) return EC_SUCCESS; } } else if (IS_ENABLED(CONFIG_USB_PD_TRY_SRC) && - !strcasecmp(argv[1], "trysrc")) { + !strcasecmp(argv[1], "trysrc")) { enum try_src_override_t ov = tc_get_try_src_override(); if (argc >= 3) { @@ -111,7 +112,7 @@ int command_pd(int argc, char **argv) else if (!strcasecmp(argv[3], "data")) pd_dpm_request(port, DPM_REQUEST_DR_SWAP); else if (IS_ENABLED(CONFIG_USBC_VCONN_SWAP) && - !strcasecmp(argv[3], "vconn")) + !strcasecmp(argv[3], "vconn")) pd_dpm_request(port, DPM_REQUEST_VCONN_SWAP); else return EC_ERROR_PARAM3; @@ -135,23 +136,23 @@ int command_pd(int argc, char **argv) case PD_DRP_FORCE_SOURCE: ccprintf("force source\n"); break; - cflush(); + cflush(); } } else { if (!strcasecmp(argv[3], "on")) pd_set_dual_role(port, - PD_DRP_TOGGLE_ON); + PD_DRP_TOGGLE_ON); else if (!strcasecmp(argv[3], "off")) pd_set_dual_role(port, - PD_DRP_TOGGLE_OFF); + PD_DRP_TOGGLE_OFF); else if (!strcasecmp(argv[3], "freeze")) pd_set_dual_role(port, PD_DRP_FREEZE); else if (!strcasecmp(argv[3], "sink")) pd_set_dual_role(port, - PD_DRP_FORCE_SINK); + PD_DRP_FORCE_SINK); else if (!strcasecmp(argv[3], "source")) pd_set_dual_role(port, - PD_DRP_FORCE_SOURCE); + PD_DRP_FORCE_SOURCE); else return EC_ERROR_PARAM4; } @@ -161,24 +162,23 @@ int command_pd(int argc, char **argv) if (!strcasecmp(argv[2], "state")) { cflush(); - ccprintf("Port C%d CC%d, %s - Role: %s-%s", - port, pd_get_polarity(port) + 1, - pd_comm_is_enabled(port) ? "Enable" : "Disable", - pd_get_power_role(port) == - PD_ROLE_SOURCE ? "SRC" : "SNK", - pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP"); + ccprintf("Port C%d CC%d, %s - Role: %s-%s", port, + pd_get_polarity(port) + 1, + pd_comm_is_enabled(port) ? "Enable" : "Disable", + pd_get_power_role(port) == PD_ROLE_SOURCE ? "SRC" : + "SNK", + pd_get_data_role(port) == PD_ROLE_DFP ? "DFP" : "UFP"); if (IS_ENABLED(CONFIG_USBC_VCONN)) ccprintf("%s ", tc_is_vconn_src(port) ? "-VC" : ""); ccprintf("TC State: %s, Flags: 0x%04x", - tc_get_current_state(port), - tc_get_flags(port)); + tc_get_current_state(port), tc_get_flags(port)); if (IS_ENABLED(CONFIG_USB_PE_SM)) ccprintf(" PE State: %s, Flags: 0x%04x\n", - pe_get_current_state(port), - pe_get_flags(port)); + pe_get_current_state(port), + pe_get_flags(port)); else ccprintf("\n"); @@ -189,8 +189,7 @@ int command_pd(int argc, char **argv) ccprintf("Port C%d CC%d\n", port, pd_get_task_cc_state(port)); } - if (IS_ENABLED(CONFIG_CMD_PD_TIMER) && - !strcasecmp(argv[2], "timer")) { + if (IS_ENABLED(CONFIG_CMD_PD_TIMER) && !strcasecmp(argv[2], "timer")) { pd_timer_dump(port); } @@ -198,23 +197,23 @@ int command_pd(int argc, char **argv) } #ifndef TEST_USB_PD_CONSOLE DECLARE_CONSOLE_COMMAND(pd, command_pd, - "version" - "\ndump [0|1|2|3]" + "version" + "\ndump [0|1|2|3]" #ifdef CONFIG_USB_PD_TRY_SRC - "\ntrysrc [0|1|2]" + "\ntrysrc [0|1|2]" #endif - "\n\t state" - "\n\t srccaps" - "\n\t cc" + "\n\t state" + "\n\t srccaps" + "\n\t cc" #ifdef CONFIG_CMD_PD_TIMER - "\n\t timer" + "\n\t timer" #endif /* CONFIG_CMD_PD_TIMER */ #ifdef CONFIG_USB_PD_DUAL_ROLE - "|tx|charger|dev" - "\n\t disable|enable|soft|hard" - "\n\t dualrole [on|off|freeze|sink|source]" - "\n\t swap [power|data|vconn]" + "|tx|charger|dev" + "\n\t disable|enable|soft|hard" + "\n\t dualrole [on|off|freeze|sink|source]" + "\n\t swap [power|data|vconn]" #endif /* CONFIG_USB_PD_DUAL_ROLE */ - , - "USB PD"); + , + "USB PD"); #endif -- cgit v1.2.1 From 63bbacdacbbadc9436ef01a767ad3876249df3fa Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:20 -0600 Subject: board/pirika/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I356345bb71881332242e7a47f91109fb2a21875e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728830 Reviewed-by: Jeremy Bettis --- board/pirika/led.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/board/pirika/led.c b/board/pirika/led.c index 2fe70f5fe8..8d5b564c74 100644 --- a/board/pirika/led.c +++ b/board/pirika/led.c @@ -9,28 +9,37 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {LED_OFF, 2 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { LED_OFF, 2 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From b1579096c51391415944d3e2d6d374472129bf0e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:38 -0600 Subject: board/cret/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9cdf674005ea81cc4f39e5ae400fff1f276ac442 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728166 Reviewed-by: Jeremy Bettis --- board/cret/board.c | 57 +++++++++++++++++++++++------------------------------- 1 file changed, 24 insertions(+), 33 deletions(-) diff --git a/board/cret/board.c b/board/cret/board.c index 57bddae55e..e0b6cd6e68 100644 --- a/board/cret/board.c +++ b/board/cret/board.c @@ -44,8 +44,8 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 @@ -86,7 +86,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void sub_hdmi_hpd_interrupt(enum gpio_signal s) @@ -202,7 +201,7 @@ static void reconfigure_5v_gpio(void) gpio_set_flags(GPIO_VOLUP_BTN_ODL, GPIO_OUT_LOW); } } -DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, reconfigure_5v_gpio, HOOK_PRIO_INIT_I2C + 1); #endif /* BOARD_WADDLEDOO */ static void set_5v_gpio(int level) @@ -220,7 +219,6 @@ __override void board_power_5v_enable(int enable) * DB. */ set_5v_gpio(!!enable); - } __override uint8_t board_get_usb_pd_port_count(void) @@ -239,13 +237,11 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) { - int is_real_port = (port >= 0 && - port < board_get_usb_pd_port_count()); + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); int i; int old_port; @@ -308,8 +304,8 @@ int board_set_active_charge_port(int port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { int icl = MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT); @@ -334,17 +330,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; static struct stprivate_data g_lis2dh_data; static struct lsm6dso_data lsm6dso_data; @@ -424,20 +416,19 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -__override void ocpc_get_pid_constants(int *kp, int *kp_div, - int *ki, int *ki_div, - int *kd, int *kd_div) +__override void ocpc_get_pid_constants(int *kp, int *kp_div, int *ki, + int *ki_div, int *kd, int *kd_div) { *kp = 1; *kp_div = 20; @@ -568,8 +559,8 @@ static const struct ec_response_keybd_config cret_keybd = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &cret_keybd; } -- cgit v1.2.1 From 29e82b8a0081d535f3c9a6144a436aa40e1f5577 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Fri, 1 Jul 2022 11:22:49 -0600 Subject: lazor: Enable LTO Enabling LTO buys us about 12K of flash space. BUG=b:237748265 BRANCH=none TEST=make BOARD=lazor Signed-off-by: Jack Rosenthal Change-Id: I4c14e1de61c80e4485459ce7ca1ab3383e11d730 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3738989 Commit-Queue: Diana Z Reviewed-by: Diana Z --- board/lazor/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/lazor/board.h b/board/lazor/board.h index bdc16d7594..a7f825b5b7 100644 --- a/board/lazor/board.h +++ b/board/lazor/board.h @@ -14,6 +14,7 @@ #define CONFIG_FLASH_SIZE_BYTES (512 * 1024) /* 512KB internal spi flash */ /* Reduce flash usage */ +#define CONFIG_LTO #define CONFIG_USB_PD_DEBUG_LEVEL 2 /* Switchcap */ -- cgit v1.2.1 From 47cecbbfc04efe6f1db7866959cd4d48e0ace382 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:47 -0600 Subject: chip/npcx/fan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I682745f88207c30249dec1c7b3a851b4fbb9ba30 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729379 Reviewed-by: Jeremy Bettis --- chip/npcx/fan.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/chip/npcx/fan.c b/chip/npcx/fan.c index 5b56f33edf..c6ed978dbe 100644 --- a/chip/npcx/fan.c +++ b/chip/npcx/fan.c @@ -25,7 +25,7 @@ #if !(DEBUG_FAN) #define CPRINTS(...) #else -#define CPRINTS(format, args...) cprints(CC_PWM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_PWM, format, ##args) #endif /* Tacho measurement state */ @@ -92,7 +92,7 @@ static int rpm_pre[FAN_CH_COUNT]; #define TACHO_MAX_CNT (BIT(16) - 1) /* Margin of target rpm */ -#define RPM_MARGIN(rpm_target) (((rpm_target) * RPM_DEVIATION) / 100) +#define RPM_MARGIN(rpm_target) (((rpm_target)*RPM_DEVIATION) / 100) /** * MFT get fan rpm value @@ -154,14 +154,14 @@ void mft_set_apb1_prescaler(int ch) uint16_t prescaler_divider = 0; /* Set clock prescaler divider to MFT module*/ - prescaler_divider = (uint16_t)(clock_get_apb1_freq() - / fan_status[ch].mft_freq); + prescaler_divider = + (uint16_t)(clock_get_apb1_freq() / fan_status[ch].mft_freq); if (prescaler_divider >= 1) prescaler_divider = prescaler_divider - 1; if (prescaler_divider > 0xFF) prescaler_divider = 0xFF; - NPCX_TPRSC(mdl) = (uint8_t) prescaler_divider; + NPCX_TPRSC(mdl) = (uint8_t)prescaler_divider; } /** @@ -184,7 +184,6 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Need to initialize MFT or not */ if (enable_mft_read_rpm) { - /* Initialize tacho sampling rate */ if (clk_src == TCKC_LFCLK) p_status->mft_freq = INT_32K_CLOCK; @@ -195,7 +194,7 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Set mode 5 to MFT module */ SET_FIELD(NPCX_TMCTRL(mdl), NPCX_TMCTRL_MDSEL_FIELD, - NPCX_MFT_MDSEL_5); + NPCX_MFT_MDSEL_5); /* Set MFT operation frequency */ if (clk_src == TCKC_PRESCALE_APB1_CLK) @@ -203,11 +202,11 @@ static void fan_config(int ch, int enable_mft_read_rpm) /* Set the low power mode or not. */ UPDATE_BIT(NPCX_TCKC(mdl), NPCX_TCKC_LOW_PWR, - clk_src == TCKC_LFCLK); + clk_src == TCKC_LFCLK); /* Set the default count-down timer. */ NPCX_TCNT1(mdl) = TACHO_MAX_CNT; - NPCX_TCRA(mdl) = TACHO_MAX_CNT; + NPCX_TCRA(mdl) = TACHO_MAX_CNT; /* Set the edge polarity to rising. */ SET_BIT(NPCX_TMCTRL(mdl), NPCX_TMCTRL_TAEDG); @@ -300,7 +299,7 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target) * In this case, don't step the PWM duty too aggressively. * See b:225208265 for more detail. */ - if (rpm_pre[ch] == 0 && rpm_actual == 0) { + if (rpm_pre[ch] == 0 && rpm_actual == 0) { rpm_diff = RPM_MARGIN(rpm_target) + 1; } else { rpm_diff = rpm_target - rpm_actual; @@ -319,7 +318,7 @@ enum fan_status fan_smart_control(int ch, int rpm_actual, int rpm_target) fan_adjust_duty(ch, rpm_diff, duty); return FAN_STATUS_CHANGING; - /* Decrease PWM duty */ + /* Decrease PWM duty */ } else if (rpm_diff < -RPM_MARGIN(rpm_target)) { if (duty == 1 && rpm_target != 0) return FAN_STATUS_FRUSTRATED; @@ -340,11 +339,12 @@ void fan_tick_func(void) { int ch; - for (ch = 0; ch < FAN_CH_COUNT ; ch++) { + for (ch = 0; ch < FAN_CH_COUNT; ch++) { volatile struct fan_status_t *p_status = fan_status + ch; /* Make sure rpm mode is enabled */ if (p_status->fan_mode != TACHO_FAN_RPM) { - /* Fan in duty mode still want rpm_actual being updated. */ + /* Fan in duty mode still want rpm_actual being updated. + */ p_status->rpm_actual = mft_fan_rpm(ch); if (p_status->rpm_actual > 0) p_status->auto_status = FAN_STATUS_LOCKED; @@ -357,8 +357,8 @@ void fan_tick_func(void) /* Get actual rpm */ p_status->rpm_actual = mft_fan_rpm(ch); /* Do smart fan stuff */ - p_status->auto_status = fan_smart_control(ch, - p_status->rpm_actual, p_status->rpm_target); + p_status->auto_status = fan_smart_control( + ch, p_status->rpm_actual, p_status->rpm_target); } } DECLARE_HOOK(HOOK_TICK, fan_tick_func, HOOK_PRIO_DEFAULT); @@ -530,7 +530,7 @@ enum fan_status fan_get_status(int ch) int fan_is_stalled(int ch) { return fan_get_enabled(ch) && fan_get_duty(ch) && - fan_status[ch].cur_state == TACHO_UNDERFLOW; + fan_status[ch].cur_state == TACHO_UNDERFLOW; } /** -- cgit v1.2.1 From 8d3c81e09b70bbc184ee8fc153e372011e37c14c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:28:09 -0600 Subject: board/corori/cbi_ssfc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9cac9b225f81012431c333b9d6100a8b1cecdf5e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728161 Reviewed-by: Jeremy Bettis --- board/corori/cbi_ssfc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/corori/cbi_ssfc.c b/board/corori/cbi_ssfc.c index c4b859f133..39fd4929a1 100644 --- a/board/corori/cbi_ssfc.c +++ b/board/corori/cbi_ssfc.c @@ -27,10 +27,10 @@ DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) { - return (enum ec_ssfc_base_sensor) cached_ssfc.base_sensor; + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; } enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) { - return (enum ec_ssfc_lid_sensor) cached_ssfc.lid_sensor; + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; } -- cgit v1.2.1 From 3d4430e92e71a45a62c72079531ac87451fb17c3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:17 -0600 Subject: board/servo_v4/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5ab61115bf402abd068cca5847f0e1e316552afd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728905 Reviewed-by: Jeremy Bettis --- board/servo_v4/board.c | 181 +++++++++++++++++++++---------------------------- 1 file changed, 79 insertions(+), 102 deletions(-) diff --git a/board/servo_v4/board.c b/board/servo_v4/board.c index b304408f74..26bdad6faa 100644 --- a/board/servo_v4/board.c +++ b/board/servo_v4/board.c @@ -33,8 +33,8 @@ #include "usb-stream.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /****************************************************************************** * GPIO interrupt handlers. @@ -175,23 +175,22 @@ void board_config_pre_init(void) /* ADC channels */ const struct adc_t adc_channels[] = { /* USB PD CC lines sensing. Converted to mV (3300mV/4096). */ - [ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)}, - [ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)}, - [ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)}, - [ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)}, - [ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)}, - [ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)}, - [ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)}, + [ADC_CHG_CC1_PD] = { "CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2) }, + [ADC_CHG_CC2_PD] = { "CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4) }, + [ADC_DUT_CC1_PD] = { "DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0) }, + [ADC_DUT_CC2_PD] = { "DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5) }, + [ADC_SBU1_DET] = { "SBU1_DET", 3300, 4096, 0, STM32_AIN(3) }, + [ADC_SBU2_DET] = { "SBU2_DET", 3300, 4096, 0, STM32_AIN(7) }, + [ADC_SUB_C_REF] = { "SUB_C_REF", 3300, 4096, 0, STM32_AIN(1) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); - /****************************************************************************** * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 /****************************************************************************** * Forward USART3 as a simple USB serial interface. @@ -200,29 +199,19 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); static struct usart_config const usart3; struct usb_stream_config const usart3_usb; -static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t, - usart3.producer, usart3_usb.consumer); -static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t, - usart3_usb.producer, usart3.consumer); +static struct queue const usart3_to_usb = + QUEUE_DIRECT(64, uint8_t, usart3.producer, usart3_usb.consumer); +static struct queue const usb_to_usart3 = + QUEUE_DIRECT(64, uint8_t, usart3_usb.producer, usart3.consumer); static struct usart_config const usart3 = - USART_CONFIG(usart3_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart3_to_usb, - usb_to_usart3); - -USB_STREAM_CONFIG(usart3_usb, - USB_IFACE_USART3_STREAM, - USB_STR_USART3_STREAM_NAME, - USB_EP_USART3_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart3, - usart3_to_usb) + USART_CONFIG(usart3_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart3_to_usb, usb_to_usart3); +USB_STREAM_CONFIG(usart3_usb, USB_IFACE_USART3_STREAM, + USB_STR_USART3_STREAM_NAME, USB_EP_USART3_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart3, + usart3_to_usb) /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -231,44 +220,34 @@ USB_STREAM_CONFIG(usart3_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 9600, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 9600, 0, + usart4_to_usb, usb_to_usart4); + +USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4, + usart4_to_usb) /* * Define usb interface descriptor for the `EMPTY` usb interface, to satisfy * UEFI and kernel requirements (see b/183857501). */ -const struct usb_interface_descriptor -USB_IFACE_DESC(USB_IFACE_EMPTY) = { - .bLength = USB_DT_INTERFACE_SIZE, - .bDescriptorType = USB_DT_INTERFACE, - .bInterfaceNumber = USB_IFACE_EMPTY, - .bAlternateSetting = 0, - .bNumEndpoints = 0, - .bInterfaceClass = USB_CLASS_VENDOR_SPEC, +const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_EMPTY) = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = USB_IFACE_EMPTY, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = 0, .bInterfaceProtocol = 0, - .iInterface = 0, + .iInterface = 0, }; /****************************************************************************** @@ -276,39 +255,38 @@ USB_IFACE_DESC(USB_IFACE_EMPTY) = { */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4"), - [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("Servo V4"), + [USB_STR_SERIALNO] = USB_STRING_DESC("1234-a"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"), - [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), - [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), + [USB_STR_USART3_STREAM_NAME] = USB_STRING_DESC("DUT UART"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("Atmega UART"), + [USB_STR_UPDATE_NAME] = USB_STRING_DESC("Firmware update"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); - - /****************************************************************************** * Support I2C bridging over USB. */ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "master", - .port = I2C_PORT_MASTER, - .kbps = 100, - .scl = GPIO_MASTER_I2C_SCL, - .sda = GPIO_MASTER_I2C_SDA - }, + { .name = "master", + .port = I2C_PORT_MASTER, + .kbps = 100, + .scl = GPIO_MASTER_I2C_SCL, + .sda = GPIO_MASTER_I2C_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Initialize board. @@ -317,14 +295,13 @@ int usb_i2c_board_is_enabled(void) { return 1; } /* * Support tca6416 I2C ioexpander. */ -#define GPIOX_I2C_ADDR_FLAGS 0x20 -#define GPIOX_IN_PORT_A 0x0 -#define GPIOX_IN_PORT_B 0x1 -#define GPIOX_OUT_PORT_A 0x2 -#define GPIOX_OUT_PORT_B 0x3 -#define GPIOX_DIR_PORT_A 0x6 -#define GPIOX_DIR_PORT_B 0x7 - +#define GPIOX_I2C_ADDR_FLAGS 0x20 +#define GPIOX_IN_PORT_A 0x0 +#define GPIOX_IN_PORT_B 0x1 +#define GPIOX_OUT_PORT_A 0x2 +#define GPIOX_OUT_PORT_B 0x3 +#define GPIOX_DIR_PORT_A 0x6 +#define GPIOX_DIR_PORT_B 0x7 /* Write a GPIO output on the tca6416 I2C ioexpander. */ static void write_ioexpander(int bank, int gpio, int val) @@ -394,15 +371,15 @@ static void init_ioexpander(void) * Max observed USB low across sampled systems: 666mV * Min observed USB high across sampled systems: 3026mV */ -#define GND_MAX_MV 700 -#define USB_HIGH_MV 2500 -#define SBU_DIRECT 0 -#define SBU_FLIP 1 +#define GND_MAX_MV 700 +#define USB_HIGH_MV 2500 +#define SBU_DIRECT 0 +#define SBU_FLIP 1 -#define MODE_SBU_DISCONNECT 0 -#define MODE_SBU_CONNECT 1 -#define MODE_SBU_FLIP 2 -#define MODE_SBU_OTHER 3 +#define MODE_SBU_DISCONNECT 0 +#define MODE_SBU_CONNECT 1 +#define MODE_SBU_FLIP 2 +#define MODE_SBU_OTHER 3 static void ccd_measure_sbu(void); DECLARE_DEFERRED(ccd_measure_sbu); @@ -445,12 +422,12 @@ static void ccd_measure_sbu(void) } else { count++; } - /* - * If SuzyQ is enabled, we'll poll for a persistent no-signal for - * 500ms. Since USB is differential, we should never see GND/GND - * while the device is connected. - * If disconnected, electrically remove SuzyQ. - */ + /* + * If SuzyQ is enabled, we'll poll for a persistent no-signal + * for 500ms. Since USB is differential, we should never see + * GND/GND while the device is connected. If disconnected, + * electrically remove SuzyQ. + */ } else if ((mux_en) && (sbu1 < GND_MAX_MV) && (sbu2 < GND_MAX_MV)) { /* Check for SBU disconnect if connected. */ if (last != MODE_SBU_DISCONNECT) { -- cgit v1.2.1 From 6a797c3e410f3786c07ab8742eeef2494830f05a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:25 -0600 Subject: zephyr/shim/include/usbc/it5205_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I190fa45dae52e00fa0ed2c404e906888e001bfed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730851 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/it5205_usb_mux.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/include/usbc/it5205_usb_mux.h b/zephyr/shim/include/usbc/it5205_usb_mux.h index 58412e0bd3..f3b4f7cf66 100644 --- a/zephyr/shim/include/usbc/it5205_usb_mux.h +++ b/zephyr/shim/include/usbc/it5205_usb_mux.h @@ -8,15 +8,15 @@ #include "usb_mux/it5205_public.h" -#define IT5205_USB_MUX_COMPAT ite_it5205 +#define IT5205_USB_MUX_COMPAT ite_it5205 -#define USB_MUX_CONFIG_IT5205(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &it5205_usb_mux_driver, \ - .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ - .i2c_addr_flags = \ - DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ +#define USB_MUX_CONFIG_IT5205(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &it5205_usb_mux_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ } #endif /* __ZEPHYR_SHIM_IT5205_USB_MUX_H */ -- cgit v1.2.1 From 456af9abf63eb8b98c70f5d1ed2e21053976ebe2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:30 -0600 Subject: include/device_state.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I12009f710e06349579ff724e805ee58da2294ec5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730240 Reviewed-by: Jeremy Bettis --- include/device_state.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/device_state.h b/include/device_state.h index e7894ba998..4ef0fa4c25 100644 --- a/include/device_state.h +++ b/include/device_state.h @@ -84,4 +84,4 @@ int device_set_state(enum device_type device, enum device_state state); */ void board_update_device_state(enum device_type device); -#endif /* __CROS_DEVICE_STATE_H */ +#endif /* __CROS_DEVICE_STATE_H */ -- cgit v1.2.1 From fd9b114e835d021cc0625f1c31e567b8988277d3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:26 -0600 Subject: test/usb_prl.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I446351fd9ea4cc4ebb830ddae831a43075e103de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730546 Reviewed-by: Jeremy Bettis --- test/usb_prl.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/test/usb_prl.c b/test/usb_prl.c index 3ef3450649..1b4f78a0fe 100644 --- a/test/usb_prl.c +++ b/test/usb_prl.c @@ -34,14 +34,14 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { static enum pd_power_role get_partner_power_role(int port) { - return pd_get_power_role(port) == PD_ROLE_SINK ? - PD_ROLE_SOURCE : PD_ROLE_SINK; + return pd_get_power_role(port) == PD_ROLE_SINK ? PD_ROLE_SOURCE : + PD_ROLE_SINK; } static enum pd_data_role get_partner_data_role(int port) { - return pd_get_data_role(port) == PD_ROLE_UFP ? - PD_ROLE_DFP : PD_ROLE_UFP; + return pd_get_data_role(port) == PD_ROLE_UFP ? PD_ROLE_DFP : + PD_ROLE_UFP; } static void enable_prl(int port, int en) @@ -50,7 +50,7 @@ static void enable_prl(int port, int en) mock_tc_port[port].pd_enable = en; - task_wait_event(10*MSEC); + task_wait_event(10 * MSEC); prl_set_rev(port, TCPCI_MSG_SOP, mock_tc_port[port].rev); } @@ -59,16 +59,16 @@ static int test_receive_control_msg(void) { int port = PORT0; uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP, - get_partner_power_role(port), - get_partner_data_role(port), - mock_tc_port[port].msg_rx_id, - 0, mock_tc_port[port].rev, 0); + get_partner_power_role(port), + get_partner_data_role(port), + mock_tc_port[port].msg_rx_id, 0, + mock_tc_port[port].rev, 0); /* Set up the message to be received. */ mock_tcpm_rx_msg(port, header, 0, NULL); /* Process the message. */ - task_wait_event(10*MSEC); + task_wait_event(10 * MSEC); /* Check results. */ TEST_NE(mock_pe_port[port].mock_pe_message_received, 0, "%d"); @@ -94,7 +94,7 @@ static int test_send_control_msg(void) /* Simulate the TX complete that the PD_INT handler would signal */ pd_transmit_complete(port, TCPC_TX_COMPLETE_SUCCESS); - task_wait_event(10*MSEC); + task_wait_event(10 * MSEC); /* Check results. */ TEST_NE(mock_pe_port[port].mock_pe_message_sent, 0, "%d"); @@ -111,16 +111,16 @@ static int test_discard_queued_tx_when_rx_happens(void) { int port = PORT0; uint16_t header = PD_HEADER(PD_CTRL_DR_SWAP, - get_partner_power_role(port), - get_partner_data_role(port), - mock_tc_port[port].msg_rx_id, - 0, mock_tc_port[port].rev, 0); + get_partner_power_role(port), + get_partner_data_role(port), + mock_tc_port[port].msg_rx_id, 0, + mock_tc_port[port].rev, 0); uint8_t *buf = tx_emsg[port].buf; uint8_t len = 8; uint8_t i = 0; /* Set up the message to be sent. */ - for (i = 0 ; i < len ; i++) + for (i = 0; i < len; i++) buf[i] = (uint8_t)i; tx_emsg[port].len = len; @@ -130,7 +130,7 @@ static int test_discard_queued_tx_when_rx_happens(void) mock_tcpm_rx_msg(port, header, 0, NULL); /* Process the message. */ - task_wait_event(10*MSEC); + task_wait_event(10 * MSEC); /* Check results. Source should have discarded its message queued up * to TX, and should have received the message from the sink. @@ -173,7 +173,6 @@ void run_test(int argc, char **argv) RUN_TEST(test_discard_queued_tx_when_rx_happens); /* TODO add tests here */ - /* Do basic state machine validity checks last. */ RUN_TEST(test_prl_no_parent_cycles); RUN_TEST(test_prl_all_states_named); -- cgit v1.2.1 From a49bbd01c2c1e0b9d5e34637cf9d8cc7226b2e2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:37 -0600 Subject: board/boten/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie7736d90c9585157a8bf3ce6994c1fdc05802cb1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728038 Reviewed-by: Jeremy Bettis --- board/boten/board.c | 83 ++++++++++++++++++++++------------------------------- 1 file changed, 34 insertions(+), 49 deletions(-) diff --git a/board/boten/board.c b/board/boten/board.c index 76ee055fe4..83845098d0 100644 --- a/board/boten/board.c +++ b/board/boten/board.c @@ -40,7 +40,7 @@ #include "usb_pd.h" #include "usb_pd_tcpm.h" -#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) #define INT_RECHECK_US 5000 /* C0 interrupt line shared by BC 1.2 and charger */ @@ -84,7 +84,6 @@ static void usb_c0_interrupt(enum gpio_signal s) /* Check the line again in 5ms */ hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); - } static void c0_ccsbu_ovp_interrupt(enum gpio_signal s) @@ -114,8 +113,7 @@ DECLARE_DEFERRED(pendetect_deferred); void pen_detect_interrupt(enum gpio_signal s) { /* Trigger deferred notification of pen detect change */ - hook_call_deferred(&pendetect_deferred_data, - 500 * MSEC); + hook_call_deferred(&pendetect_deferred_data, 500 * MSEC); } void board_hibernate(void) @@ -147,27 +145,21 @@ __override void board_pulse_entering_rw(void) /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_VSNS_PP3300_A] = { - .name = "PP3300_A_PGOOD", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH0 - }, - [ADC_TEMP_SENSOR_1] = { - .name = "TEMP_SENSOR1", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH2 - }, - [ADC_TEMP_SENSOR_2] = { - .name = "TEMP_SENSOR2", - .factor_mul = ADC_MAX_MVOLT, - .factor_div = ADC_READ_MAX + 1, - .shift = 0, - .channel = CHIP_ADC_CH3 - }, + [ADC_VSNS_PP3300_A] = { .name = "PP3300_A_PGOOD", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH0 }, + [ADC_TEMP_SENSOR_1] = { .name = "TEMP_SENSOR1", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH2 }, + [ADC_TEMP_SENSOR_2] = { .name = "TEMP_SENSOR2", + .factor_mul = ADC_MAX_MVOLT, + .factor_div = ADC_READ_MAX + 1, + .shift = 0, + .channel = CHIP_ADC_CH3 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -276,7 +268,6 @@ int board_is_sourcing_vbus(int port) tcpc_read(port, TCPC_REG_POWER_STATUS, ®val); return !!(regval & TCPC_REG_POWER_STATUS_SOURCING_VBUS); - } int board_set_active_charge_port(int port) @@ -288,8 +279,7 @@ int board_set_active_charge_port(int port) /* Disable all ports. */ if (port == CHARGE_PORT_NONE) { - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW); + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_LOW); raa489000_enable_asgate(0, false); return EC_SUCCESS; } @@ -302,8 +292,7 @@ int board_set_active_charge_port(int port) /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || - tcpc_write(0, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { + tcpc_write(0, TCPC_REG_COMMAND, TCPC_REG_COMMAND_SNK_CTRL_HIGH)) { CPRINTUSB("p%d: sink path enable failed.", port); return EC_ERROR_UNKNOWN; } @@ -345,17 +334,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrices to rotate accelerometers into the standard reference. */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* Sensor Data */ static struct stprivate_data g_lis2dwl_data; @@ -459,7 +444,7 @@ void board_init(void) gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ gpio_set_flags(GPIO_BASE_SIXAXIS_INT_L, - GPIO_INPUT | GPIO_PULL_DOWN); + GPIO_INPUT | GPIO_PULL_DOWN); /* only clamshell sku todo */ gpio_set_flags(GPIO_PEN_DET_ODL, GPIO_INPUT | GPIO_PULL_DOWN); @@ -488,14 +473,14 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); /* Thermistors */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Memory", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, + [TEMP_SENSOR_1] = { .name = "Memory", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -- cgit v1.2.1 From c694c632168ffae9f134696088de2029720a84cf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:20 -0600 Subject: board/hoho/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibd7217380ef097c4d258c32aca4d7a85365b954e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728322 Reviewed-by: Jeremy Bettis --- board/hoho/board.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/hoho/board.h b/board/hoho/board.h index 635abfbeda..28e558869e 100644 --- a/board/hoho/board.h +++ b/board/hoho/board.h @@ -43,7 +43,7 @@ #define CONFIG_USB_PD_IDENTITY_HW_VERS 1 #define CONFIG_USB_PD_IDENTITY_SW_VERS 1 #define CONFIG_USB_PD_LOGGING -#undef CONFIG_EVENT_LOG_SIZE +#undef CONFIG_EVENT_LOG_SIZE #define CONFIG_EVENT_LOG_SIZE 256 #define CONFIG_USB_PD_PORT_MAX_COUNT 1 #define CONFIG_USB_PD_TCPC @@ -72,7 +72,7 @@ /* Timer selection */ #define TIM_CLOCK32 2 -#define TIM_ADC 3 +#define TIM_ADC 3 #include "gpio_signal.h" @@ -95,14 +95,14 @@ enum usb_strings { }; /* we are never a source : don't care about power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 1000 -#define PD_MAX_POWER_MW 1500 -#define PD_MAX_CURRENT_MA 300 -#define PD_MAX_VOLTAGE_MV 5000 +#define PD_MAX_POWER_MW 1500 +#define PD_MAX_CURRENT_MA 300 +#define PD_MAX_VOLTAGE_MV 5000 #endif /* !__ASSEMBLER__ */ @@ -110,10 +110,10 @@ enum usb_strings { #define USB_DEV_CLASS USB_CLASS_BILLBOARD /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_COUNT 0 +#define USB_IFACE_COUNT 0 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_COUNT 1 +#define USB_EP_CONTROL 0 +#define USB_EP_COUNT 1 #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 761db14ef422056e76515a2a38f848d5fb410cbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:09:24 -0600 Subject: include/curve25519.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I880c41231b4a941eae1d3d1fbd56a7769dc1505f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730238 Reviewed-by: Jeremy Bettis --- include/curve25519.h | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) mode change 120000 => 100644 include/curve25519.h diff --git a/include/curve25519.h b/include/curve25519.h deleted file mode 120000 index b9943bd4ac..0000000000 --- a/include/curve25519.h +++ /dev/null @@ -1 +0,0 @@ -../third_party/boringssl/include/curve25519.h \ No newline at end of file diff --git a/include/curve25519.h b/include/curve25519.h new file mode 100644 index 0000000000..447790ec45 --- /dev/null +++ b/include/curve25519.h @@ -0,0 +1,68 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CURVE25519_H +#define __CROS_EC_CURVE25519_H + +#include + +/* Curve25519. + * + * Curve25519 is an elliptic curve. See https://tools.ietf.org/html/rfc7748. + */ + +/* X25519. + * + * X25519 is the Diffie-Hellman primitive built from curve25519. It is + * sometimes referred to as “curve25519”, but “X25519” is a more precise + * name. + * See http://cr.yp.to/ecdh.html and https://tools.ietf.org/html/rfc7748. + */ + +#define X25519_PRIVATE_KEY_LEN 32 +#define X25519_PUBLIC_VALUE_LEN 32 + +/** + * Generate a public/private key pair. + * @param out_public_value generated public key. + * @param out_private_value generated private key. + */ +void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]); + +/** + * Diffie-Hellman function. + * @param out_shared_key + * @param private_key + * @param out_public_value + * @return one on success and zero on error. + * + * X25519() writes a shared key to @out_shared_key that is calculated from the + * given private key and the peer's public value. + * + * Don't use the shared key directly, rather use a KDF and also include the two + * public values as inputs. + */ +int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32], + const uint8_t peers_public_value[32]); + +/** + * Compute the matching public key. + * @param out_public_value computed public key. + * @param private_key private key to use. + * + * X25519_public_from_private() calculates a Diffie-Hellman public value from + * the given private key and writes it to @out_public_value. + */ +void X25519_public_from_private(uint8_t out_public_value[32], + const uint8_t private_key[32]); + +/* + * Low-level x25519 function, defined by either the generic or cortex-m0 + * implementation. Must not be called directly. + */ +void x25519_scalar_mult(uint8_t out[32], const uint8_t scalar[32], + const uint8_t point[32]); + +#endif /* __CROS_EC_CURVE25519_H */ -- cgit v1.2.1 From 713559c93ee533e019bff4f10fc3027c677d5ff9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:39:47 -0600 Subject: board/host/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e176700b60b8d0daecfeae3c90a33825b8b5eb0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728471 Reviewed-by: Jeremy Bettis --- board/host/board.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/board/host/board.h b/board/host/board.h index 979763af4e..97d9789f9a 100644 --- a/board/host/board.h +++ b/board/host/board.h @@ -65,25 +65,25 @@ enum { }; /* Standard-current Rp */ -#define PD_SRC_VNC PD_SRC_DEF_VNC_MV -#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV +#define PD_SRC_VNC PD_SRC_DEF_VNC_MV +#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV /* delay necessary for the voltage transition on the power supply */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 20000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 20000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 20000 /* us */ /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MIN_CURRENT_MA 500 -#define PD_MIN_POWER_MW 7500 +#define PD_MIN_CURRENT_MA 500 +#define PD_MIN_POWER_MW 7500 /* Configuration for fake Fingerprint Sensor */ #define CONFIG_SPI_CONTROLLER -#define CONFIG_SPI_FP_PORT 1 /* SPI1: third master config */ +#define CONFIG_SPI_FP_PORT 1 /* SPI1: third master config */ #define CONFIG_RNG void fps_event(enum gpio_signal signal); @@ -92,7 +92,7 @@ void fps_event(enum gpio_signal signal); #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#define I2C_PORT_EEPROM 0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_PORT_EEPROM 0 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #endif /* __CROS_EC_BOARD_H */ -- cgit v1.2.1 From 9371da2646f4ab0d2e82d6892592d46d0ecc928c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:50 -0600 Subject: baseboard/kukui/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icb00c6d8b65a88eb20a6e0ae12bcda1376f6f939 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727916 Reviewed-by: Jeremy Bettis --- baseboard/kukui/baseboard.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/baseboard/kukui/baseboard.h b/baseboard/kukui/baseboard.h index 59e161571f..8f7f5ede4e 100644 --- a/baseboard/kukui/baseboard.h +++ b/baseboard/kukui/baseboard.h @@ -18,7 +18,7 @@ #if defined(VARIANT_KUKUI_BATTERY_MAX17055) #define CONFIG_BATTERY_MAX17055 #define CONFIG_BATTERY_MAX17055_ALERT -#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ +#define BATTERY_MAX17055_RSENSE 5 /* m-ohm */ #elif defined(VARIANT_KUKUI_BATTERY_MM8013) #define CONFIG_BATTERY_MM8013 #elif defined(VARIANT_KUKUI_BATTERY_BQ27541) @@ -47,7 +47,7 @@ #define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE /* TCPC MT6370 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* @@ -64,7 +64,7 @@ #define CONFIG_CHARGE_RAMP_HW /* TCPC FUSB302 */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 160000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* b/2230219: 15V has better charging performance than 20V */ @@ -115,16 +115,16 @@ #define PD_OPERATING_POWER_MW 30000 -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) #else /* !VARIANT_KUKUI_JACUZZI */ -#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +#define CONFIG_MKBP_HOST_EVENT_WAKEUP_MASK \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #endif /* VARIANT_KUKUI_JACUZZI */ @@ -144,9 +144,9 @@ /* Optional modules */ #define CONFIG_ADC -#undef CONFIG_ADC_WATCHDOG +#undef CONFIG_ADC_WATCHDOG #define CONFIG_CHIPSET_MT8183 -#undef CONFIG_CMD_ACCELS +#undef CONFIG_CMD_ACCELS #define CONFIG_EMULATED_SYSRQ #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER @@ -207,8 +207,8 @@ #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 4096 -#define GPIO_LID_OPEN GPIO_HALL_INT_L -#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT +#define GPIO_LID_OPEN GPIO_HALL_INT_L +#define GPIO_KB_DISCRETE_INT GPIO_IT8801_SMB_INT #ifndef VARIANT_KUKUI_NO_SENSORS #define CONFIG_ACCEL_FIFO @@ -241,11 +241,11 @@ #define CONFIG_BATTERY_PRESENT_CUSTOM #define CONFIG_BATTERY_REVIVE_DISCONNECT -#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) +#define PD_MAX_POWER_MW ((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000) #ifdef BOARD_KODAMA -#define PD_MAX_CURRENT_MA 2000 +#define PD_MAX_CURRENT_MA 2000 #else -#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_CURRENT_MA 3000 #endif /* Optional for testing */ @@ -263,7 +263,7 @@ */ #if defined(VARIANT_KUKUI_EC_STM32F098) || defined(VARIANT_KUKUI_EC_STM32L431) /* Timer selection */ -#define TIM_CLOCK32 2 +#define TIM_CLOCK32 2 #define TIM_WATCHDOG 7 /* 48 MHz SYSCLK clock frequency */ @@ -273,11 +273,11 @@ #define CPU_CLOCK 48000000 #endif -#undef CONFIG_HIBERNATE +#undef CONFIG_HIBERNATE #define CONFIG_SPI_CONTROLLER #define CONFIG_STM_HWTIMER32 #define CONFIG_WATCHDOG_HELP -#undef CONFIG_UART_CONSOLE +#undef CONFIG_UART_CONSOLE #define CONFIG_UART_CONSOLE 1 #define CONFIG_UART_RX_DMA -- cgit v1.2.1 From 95fe3441b2a2ac0b7369b317df268c6b322a7ac1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:10 -0600 Subject: driver/tcpm/ps8xxx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib60be3a094d5179dc5ca93fd045118f18a08ad4e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730097 Reviewed-by: Jeremy Bettis --- driver/tcpm/ps8xxx.h | 118 +++++++++++++++++++++++++-------------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index eeddd22640..571b2d4ccb 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -11,67 +11,67 @@ #ifndef __CROS_EC_USB_PD_TCPM_PS8XXX_H #define __CROS_EC_USB_PD_TCPM_PS8XXX_H -#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags) - 3) -#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags) - 2) +#define PS8751_P3_TO_P0_FLAGS(p3_flags) ((p3_flags)-3) +#define PS8751_P3_TO_P1_FLAGS(p3_flags) ((p3_flags)-2) -#define PS8751_BIST_TIMER_FREQ 15000000 -#define PS8751_BIST_DELAY_MS 50 +#define PS8751_BIST_TIMER_FREQ 15000000 +#define PS8751_BIST_DELAY_MS 50 -#define PS8751_BIST_COUNTER (PS8751_BIST_TIMER_FREQ / MSEC \ - * PS8751_BIST_DELAY_MS) +#define PS8751_BIST_COUNTER \ + (PS8751_BIST_TIMER_FREQ / MSEC * PS8751_BIST_DELAY_MS) #define PS8751_BIST_COUNTER_BYTE0 (PS8751_BIST_COUNTER & 0xff) #define PS8751_BIST_COUNTER_BYTE1 ((PS8751_BIST_COUNTER >> 8) & 0xff) #define PS8751_BIST_COUNTER_BYTE2 ((PS8751_BIST_COUNTER >> 16) & 0xff) -#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B -#define RP_DETECT_DISABLE 0x30 +#define PS8XXX_REG_RP_DETECT_CONTROL 0x9B +#define RP_DETECT_DISABLE 0x30 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30 -#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */ -#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC -#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD -#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE -#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF -#define PS8XXX_REG_DET_CTRL0 0x08 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE 0xA0 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON 0x30 +#define PS8XXX_REG_I2C_DEBUGGING_ENABLE_OFF 0x31 /* default */ +#define PS8XXX_REG_BIST_CONT_MODE_BYTE0 0xBC +#define PS8XXX_REG_BIST_CONT_MODE_BYTE1 0xBD +#define PS8XXX_REG_BIST_CONT_MODE_BYTE2 0xBE +#define PS8XXX_REG_BIST_CONT_MODE_CTR 0xBF +#define PS8XXX_REG_DET_CTRL0 0x08 -#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0 -#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK 0xC0 +#define PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF 0x80 -#define MUX_IN_HPD_ASSERTION_REG 0xD0 -#define IN_HPD BIT(0) +#define MUX_IN_HPD_ASSERTION_REG 0xD0 +#define IN_HPD BIT(0) #define HPD_IRQ BIT(1) -#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B +#define PS8XXX_P1_REG_MUX_USB_DCI_CFG 0x4B -#define PS8755_P0_REG_SM 0x06 -#define PS8755_P0_REG_SM_VALUE 0x80 +#define PS8755_P0_REG_SM 0x06 +#define PS8755_P0_REG_SM_VALUE 0x80 #if defined(CONFIG_USB_PD_TCPM_PS8751) /* Vendor defined registers */ -#define PS8XXX_REG_VENDOR_ID_L 0x00 -#define PS8XXX_REG_VENDOR_ID_H 0x01 -#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 -#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4 -#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 -#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 -#define PS8751_REG_MUX_USB_DCI_CFG 0xED +#define PS8XXX_REG_VENDOR_ID_L 0x00 +#define PS8XXX_REG_VENDOR_ID_H 0x01 +#define PS8XXX_REG_MUX_DP_EQ_CONFIGURATION 0xD3 +#define PS8XXX_REG_MUX_DP_OUTPUT_CONFIGURATION 0xD4 +#define PS8XXX_REG_MUX_USB_C2SS_EQ 0xE7 +#define PS8XXX_REG_MUX_USB_C2SS_HS_THRESHOLD 0xE8 +#define PS8751_REG_MUX_USB_DCI_CFG 0xED #endif /* Vendor defined registers */ -#define PS8815_P1_REG_HW_REVISION 0xF0 +#define PS8815_P1_REG_HW_REVISION 0xF0 /* Vendor defined registers */ -#define PS8815_REG_APTX_EQ_AT_10G 0x20 -#define PS8815_REG_RX_EQ_AT_10G 0x22 -#define PS8815_REG_APTX_EQ_AT_5G 0x24 -#define PS8815_REG_RX_EQ_AT_5G 0x26 +#define PS8815_REG_APTX_EQ_AT_10G 0x20 +#define PS8815_REG_RX_EQ_AT_10G 0x22 +#define PS8815_REG_APTX_EQ_AT_5G 0x24 +#define PS8815_REG_RX_EQ_AT_5G 0x26 -#define PS8815_REG_RESERVED_D1 0xD1 -#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7) -#define PS8815_REG_RESERVED_F4 0xF4 -#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6) +#define PS8815_REG_RESERVED_D1 0xD1 +#define PS8815_REG_RESERVED_D1_FRS_EN BIT(7) +#define PS8815_REG_RESERVED_F4 0xF4 +#define PS8815_REG_RESERVED_F4_FRS_EN BIT(6) /* * Below register is defined from Parade PS8815 Register Table, @@ -79,37 +79,37 @@ */ /* Displayport related settings */ -#define PS8815_REG_DP_EQ_SETTING 0xF8 -#define PS8815_AUTO_EQ_DISABLE BIT(7) -#define PS8815_DPEQ_LOSS_UP_21DB 0x09 -#define PS8815_DPEQ_LOSS_UP_20DB 0x08 -#define PS8815_DPEQ_LOSS_UP_19DB 0x07 -#define PS8815_DPEQ_LOSS_UP_18DB 0x06 -#define PS8815_DPEQ_LOSS_UP_17DB 0x05 -#define PS8815_DPEQ_LOSS_UP_16DB 0x04 -#define PS8815_DPEQ_LOSS_UP_13DB 0x03 -#define PS8815_DPEQ_LOSS_UP_12DB 0x02 -#define PS8815_DPEQ_LOSS_UP_10DB 0x01 -#define PS8815_DPEQ_LOSS_UP_9DB 0x00 -#define PS8815_REG_DP_EQ_COMP_SHIFT 3 -#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1) +#define PS8815_REG_DP_EQ_SETTING 0xF8 +#define PS8815_AUTO_EQ_DISABLE BIT(7) +#define PS8815_DPEQ_LOSS_UP_21DB 0x09 +#define PS8815_DPEQ_LOSS_UP_20DB 0x08 +#define PS8815_DPEQ_LOSS_UP_19DB 0x07 +#define PS8815_DPEQ_LOSS_UP_18DB 0x06 +#define PS8815_DPEQ_LOSS_UP_17DB 0x05 +#define PS8815_DPEQ_LOSS_UP_16DB 0x04 +#define PS8815_DPEQ_LOSS_UP_13DB 0x03 +#define PS8815_DPEQ_LOSS_UP_12DB 0x02 +#define PS8815_DPEQ_LOSS_UP_10DB 0x01 +#define PS8815_DPEQ_LOSS_UP_9DB 0x00 +#define PS8815_REG_DP_EQ_COMP_SHIFT 3 +#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1) /* * PS8805 register to distinguish chip revision * bit 7-4: 1010b is A3 chip, 0000b is A2 chip */ -#define PS8805_P0_REG_CHIP_REVISION 0x62 +#define PS8805_P0_REG_CHIP_REVISION 0x62 /* * PS8805 GPIO control register. Note the device I2C address of 0x1A is * independent of the ADDR pin on the chip, and not the same address being used * for TCPCI functions. */ -#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A -#define PS8805_REG_GPIO_CONTROL 0x21 -#define PS8805_REG_GPIO_0 BIT(7) -#define PS8805_REG_GPIO_1 BIT(5) -#define PS8805_REG_GPIO_2 BIT(6) +#define PS8805_VENDOR_DEFINED_I2C_ADDR 0x1A +#define PS8805_REG_GPIO_CONTROL 0x21 +#define PS8805_REG_GPIO_0 BIT(7) +#define PS8805_REG_GPIO_1 BIT(5) +#define PS8805_REG_GPIO_2 BIT(6) enum ps8805_gpio { PS8805_GPIO_0, -- cgit v1.2.1 From 816a5b2ff6c1a3bfbd3e49769b44447ae3d52a9e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:27:13 -0600 Subject: chip/stm32/clock-stm32h7.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib8673e42e9aa26823e9e03d3766cd87f9c47da1f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729466 Reviewed-by: Jeremy Bettis --- chip/stm32/clock-stm32h7.c | 131 ++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 66 deletions(-) diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 6c4c42d59b..bb73d5dc0c 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -13,7 +13,6 @@ * but at least yields predictable behavior. */ - #include #include "chipset.h" @@ -31,7 +30,7 @@ /* Check chip family and variant for compatibility */ #ifndef CHIP_FAMILY_STM32H7 -#error Source clock-stm32h7.c does not support this chip family. +#error Source clock-stm32h7.c does not support this chip family. #endif #ifndef CHIP_VARIANT_STM32H7X3 #error Unsupported chip variant. @@ -39,13 +38,13 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CLOCK, format, ##args) enum clock_osc { - OSC_HSI = 0, /* High-speed internal oscillator */ - OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ - OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ - OSC_PLL, /* PLL */ + OSC_HSI = 0, /* High-speed internal oscillator */ + OSC_CSI, /* Multi-speed internal oscillator: NOT IMPLEMENTED */ + OSC_HSE, /* High-speed external oscillator: NOT IMPLEMENTED */ + OSC_PLL, /* PLL */ }; enum voltage_scale { @@ -57,12 +56,12 @@ enum voltage_scale { }; enum freq { - FREQ_1KHZ = 1000, - FREQ_32KHZ = 32 * FREQ_1KHZ, - FREQ_1MHZ = 1000000, - FREQ_2MHZ = 2 * FREQ_1MHZ, - FREQ_16MHZ = 16 * FREQ_1MHZ, - FREQ_64MHZ = 64 * FREQ_1MHZ, + FREQ_1KHZ = 1000, + FREQ_32KHZ = 32 * FREQ_1KHZ, + FREQ_1MHZ = 1000000, + FREQ_2MHZ = 2 * FREQ_1MHZ, + FREQ_16MHZ = 16 * FREQ_1MHZ, + FREQ_64MHZ = 64 * FREQ_1MHZ, FREQ_140MHZ = 140 * FREQ_1MHZ, FREQ_200MHZ = 200 * FREQ_1MHZ, FREQ_280MHZ = 280 * FREQ_1MHZ, @@ -144,13 +143,13 @@ static void clock_flash_latency(enum freq axi_freq, enum voltage_scale vos) * * @param output_freq The target output frequency. */ -static void clock_pll1_configure(enum freq output_freq) { +static void clock_pll1_configure(enum freq output_freq) +{ uint32_t divm = 4; // Input prescaler (16MHz max for PLL -- 64/4 ==> 16) - uint32_t divn; // Pll multiplier - uint32_t divp; // Output 1 prescaler + uint32_t divn; // Pll multiplier + uint32_t divp; // Output 1 prescaler - switch (output_freq) - { + switch (output_freq) { case FREQ_400MHZ: /* * PLL1 configuration: @@ -190,8 +189,8 @@ static void clock_pll1_configure(enum freq output_freq) { * Using VCO wide-range setting, STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE, * requires input frequency to be between 2MHz and 16MHz. */ - ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK/divm)); - ASSERT((STM32_HSI_CLOCK/divm) <= FREQ_16MHZ); + ASSERT(FREQ_2MHZ <= (STM32_HSI_CLOCK / divm)); + ASSERT((STM32_HSI_CLOCK / divm) <= FREQ_16MHZ); /* * Ensure that we actually reach the target frequency. @@ -199,14 +198,14 @@ static void clock_pll1_configure(enum freq output_freq) { ASSERT((STM32_HSI_CLOCK / divm * divn / divp) == output_freq); /* Configure PLL1 using 64 Mhz HSI as input */ - STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI - | STM32_RCC_PLLCKSEL_DIVM1(divm); + STM32_RCC_PLLCKSELR = STM32_RCC_PLLCKSEL_PLLSRC_HSI | + STM32_RCC_PLLCKSEL_DIVM1(divm); /* in integer mode, wide range VCO with 16Mhz input, use divP */ - STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE - | STM32_RCC_PLLCFG_PLL1RGE_8M_16M - | STM32_RCC_PLLCFG_DIVP1EN; - STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) - | STM32_RCC_PLLDIV_DIVN(divn); + STM32_RCC_PLLCFGR = STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE | + STM32_RCC_PLLCFG_PLL1RGE_8M_16M | + STM32_RCC_PLLCFG_DIVP1EN; + STM32_RCC_PLL1DIVR = STM32_RCC_PLLDIV_DIVP(divp) | + STM32_RCC_PLLDIV_DIVN(divn); } /** @@ -215,22 +214,22 @@ static void clock_pll1_configure(enum freq output_freq) { * @param sysclk The input system clock, after the system clock prescaler. * @return The bus clock speed selected and configured */ -static enum freq clock_peripheral_configure(enum freq sysclk) { - switch (sysclk) - { +static enum freq clock_peripheral_configure(enum freq sysclk) +{ + switch (sysclk) { case FREQ_64MHZ: /* Restore /1 HPRE (AHB prescaler) */ /* Disable downstream prescalers */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; + STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV1 | + STM32_RCC_D1CFGR_D1PPRE_DIV1 | + STM32_RCC_D1CFGR_D1CPRE_DIV1; /* TODO(b/149512910): Adjust more peripheral prescalers */ return FREQ_64MHZ; case FREQ_400MHZ: /* Put /2 on HPRE (AHB prescaler) to keep at the 200MHz max */ - STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 - | STM32_RCC_D1CFGR_D1PPRE_DIV1 - | STM32_RCC_D1CFGR_D1CPRE_DIV1; + STM32_RCC_D1CFGR = STM32_RCC_D1CFGR_HPRE_DIV2 | + STM32_RCC_D1CFGR_D1PPRE_DIV1 | + STM32_RCC_D1CFGR_D1CPRE_DIV1; /* TODO(b/149512910): Adjust more peripheral prescalers */ return FREQ_200MHZ; default: @@ -293,16 +292,16 @@ static void clock_switch_osc(enum clock_osc osc) static void switch_voltage_scale(enum voltage_scale vos) { - volatile uint32_t *const vos_reg = &STM32_PWR_D3CR; - const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY; - const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK; - const uint32_t vos_values[] = { - /* See note below about VOS0. */ - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS1, - STM32_PWR_D3CR_VOS2, - STM32_PWR_D3CR_VOS3, - }; + volatile uint32_t *const vos_reg = &STM32_PWR_D3CR; + const uint32_t vos_ready = STM32_PWR_D3CR_VOSRDY; + const uint32_t vos_mask = STM32_PWR_D3CR_VOSMASK; + const uint32_t vos_values[] = { + /* See note below about VOS0. */ + STM32_PWR_D3CR_VOS1, + STM32_PWR_D3CR_VOS1, + STM32_PWR_D3CR_VOS2, + STM32_PWR_D3CR_VOS3, + }; BUILD_ASSERT(ARRAY_SIZE(vos_values) == VOLTAGE_SCALE_COUNT); /* @@ -344,7 +343,8 @@ static void clock_set_osc(enum clock_osc osc) case OSC_HSI: /* Switch to HSI */ clock_switch_osc(osc); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); + current_bus_freq = + clock_peripheral_configure(target_sysclk_freq); /* Use more optimized flash latency settings for 64-MHz ACLK */ clock_flash_latency(current_bus_freq, target_voltage_scale); /* Turn off the PLL1 to save power */ @@ -368,7 +368,8 @@ static void clock_set_osc(enum clock_osc osc) clock_pll1_configure(target_sysclk_freq); /* turn on PLL1 and wait until it's ready */ clock_enable_osc(OSC_PLL, true); - current_bus_freq = clock_peripheral_configure(target_sysclk_freq); + current_bus_freq = + clock_peripheral_configure(target_sysclk_freq); /* Increase flash latency before transition the clock */ clock_flash_latency(current_bus_freq, target_voltage_scale); @@ -408,9 +409,9 @@ static int dsleep_recovery_margin_us = 1000000; static void low_power_init(void) { /* Clock LPTIM1 on the 32-kHz LSI for STOP mode time keeping */ - STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R & - ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) - | STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; + STM32_RCC_D2CCIP2R = + (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_LPTIM1SEL_MASK) | + STM32_RCC_D2CCIP2_LPTIM1SEL_LSI; /* configure LPTIM1 as our 1-Khz low power timer in STOP mode */ STM32_RCC_APB1LENR |= STM32_RCC_PB1_LPTIM1; @@ -428,9 +429,8 @@ static void low_power_init(void) STM32_EXTI_CPUIMR2 |= BIT(15); /* [15] wkup47: LPTIM1 wake-up */ /* optimize power vs latency in STOP mode */ - STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) - | STM32_PWR_CR_SVOS5 - | STM32_PWR_CR_FLPS; + STM32_PWR_CR = (STM32_PWR_CR & ~STM32_PWR_CR_SVOS_MASK) | + STM32_PWR_CR_SVOS5 | STM32_PWR_CR_FLPS; } void clock_refresh_console_in_use(void) @@ -596,17 +596,16 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Num of prevented sleep: %d\n", - idle_sleep_prevented_cnt); + idle_sleep_prevented_cnt); ccprintf("Total time on: %.6llds\n", ts.val); ccprintf("Deep-sleep closest to wake deadline: %dus\n", - dsleep_recovery_margin_us); + dsleep_recovery_margin_us); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print last idle stats"); #endif /* CONFIG_CMD_IDLE_STATS */ #endif /* CONFIG_LOW_POWER_IDLE */ @@ -638,11 +637,11 @@ void clock_init(void) * by putting it on the fixed 64-Mhz HSI clock. * per_ck is clocked directly by the HSI (as per the default settings). */ - STM32_RCC_D2CCIP1R = (STM32_RCC_D2CCIP1R & - ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | - STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) - | STM32_RCC_D2CCIP1R_SPI123SEL_PERCK - | STM32_RCC_D2CCIP1R_SPI45SEL_HSI; + STM32_RCC_D2CCIP1R = + (STM32_RCC_D2CCIP1R & ~(STM32_RCC_D2CCIP1R_SPI123SEL_MASK | + STM32_RCC_D2CCIP1R_SPI45SEL_MASK)) | + STM32_RCC_D2CCIP1R_SPI123SEL_PERCK | + STM32_RCC_D2CCIP1R_SPI45SEL_HSI; /* Use more optimized flash latency settings for ACLK = HSI = 64 Mhz */ clock_flash_latency(FREQ_64MHZ, VOLTAGE_SCALE3); @@ -670,5 +669,5 @@ static int command_clock(int argc, char **argv) ccprintf("Clock frequency is now %d Hz\n", clock_get_freq()); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(clock, command_clock, - "hsi | pll", "Set clock frequency"); +DECLARE_CONSOLE_COMMAND(clock, command_clock, "hsi | pll", + "Set clock frequency"); -- cgit v1.2.1 From 0b268f93d13a1d79a59f965d03000ab2bd821eeb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:49:47 -0600 Subject: driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Change-Id: I3017f28e3adf85569125b199b4c003146a84379f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729975 Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/libfp/fpc_private.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c index 75ab9727ef..e383bb14d9 100644 --- a/driver/fingerprint/fpc/libfp/fpc_private.c +++ b/driver/fingerprint/fpc/libfp/fpc_private.c @@ -18,8 +18,8 @@ #include "driver/fingerprint/fpc/fpc_sensor.h" -#define CPRINTF(format, args...) cprintf(CC_FP, format, ## args) -#define CPRINTS(format, args...) cprints(CC_FP, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_FP, format, ##args) +#define CPRINTS(format, args...) cprints(CC_FP, format, ##args) /* Minimum reset duration */ #define FP_SENSOR_RESET_DURATION_US (10 * MSEC) @@ -31,7 +31,7 @@ #define FP_SENSOR_OPEN_DELAY_US (500 * MSEC) /* Decode internal error codes from FPC's sensor library */ -#define FPC_GET_INTERNAL_CODE(res) (((res) & 0x000fc000) >> 14) +#define FPC_GET_INTERNAL_CODE(res) (((res)&0x000fc000) >> 14) /* There was a finger on the sensor when calibrating finger detect */ #define FPC_INTERNAL_FINGER_DFD FPC_ERROR_INTERNAL_38 @@ -63,14 +63,14 @@ static struct ec_response_fp_info fpc1145_info = { /* Sensor IC commands */ enum fpc_cmd { - FPC_CMD_STATUS = 0x14, - FPC_CMD_INT_STS = 0x18, - FPC_CMD_INT_CLR = 0x1C, - FPC_CMD_FINGER_QUERY = 0x20, - FPC_CMD_SLEEP = 0x28, - FPC_CMD_DEEPSLEEP = 0x2C, - FPC_CMD_SOFT_RESET = 0xF8, - FPC_CMD_HW_ID = 0xFC, + FPC_CMD_STATUS = 0x14, + FPC_CMD_INT_STS = 0x18, + FPC_CMD_INT_CLR = 0x1C, + FPC_CMD_FINGER_QUERY = 0x20, + FPC_CMD_SLEEP = 0x28, + FPC_CMD_DEEPSLEEP = 0x2C, + FPC_CMD_SOFT_RESET = 0xF8, + FPC_CMD_HW_ID = 0xFC, }; /* Maximum size of a sensor command SPI transfer */ -- cgit v1.2.1 From 81d381c4867d7f516056382124d4dddb80627db0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:35 -0600 Subject: board/liara/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I61f11a80d9cf24633ddc7a85ed7f6ca6796a3fc7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728620 Reviewed-by: Jeremy Bettis --- board/liara/board.c | 74 ++++++++++++++++++++++------------------------------- 1 file changed, 31 insertions(+), 43 deletions(-) diff --git a/board/liara/board.c b/board/liara/board.c index c8fdeff2cd..6a32557f43 100644 --- a/board/liara/board.c +++ b/board/liara/board.c @@ -25,52 +25,40 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_POWER_BUTTON_L, GPIO_EC_RST_ODL, }; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /* I2C port map. */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_I2C0_SCL, - .sda = GPIO_I2C0_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 400, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, - { - .name = "thermal", - .port = I2C_PORT_THERMAL_AP, - .kbps = 400, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA - }, - { - .name = "kblight", - .port = I2C_PORT_KBLIGHT, - .kbps = 100, - .scl = GPIO_I2C5_SCL, - .sda = GPIO_I2C5_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_I2C7_SCL, - .sda = GPIO_I2C7_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_I2C0_SCL, + .sda = GPIO_I2C0_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 400, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, + { .name = "thermal", + .port = I2C_PORT_THERMAL_AP, + .kbps = 400, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA }, + { .name = "kblight", + .port = I2C_PORT_KBLIGHT, + .kbps = 100, + .scl = GPIO_I2C5_SCL, + .sda = GPIO_I2C5_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_I2C7_SCL, + .sda = GPIO_I2C7_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -- cgit v1.2.1 From 76d82b776016c02b1555ec55d57abef528b69050 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:03 -0600 Subject: cts/common/cts_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I52a0fe7d596f5ec997fe1386980c11a32ad59226 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729739 Reviewed-by: Jeremy Bettis --- cts/common/cts_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cts/common/cts_common.c b/cts/common/cts_common.c index 8975636655..d58ecc706e 100644 --- a/cts/common/cts_common.c +++ b/cts/common/cts_common.c @@ -11,7 +11,7 @@ __attribute__((weak)) void clean_state(void) /* Each test overrides as needed */ } -void cts_main_loop(const struct cts_test* tests, const char *name) +void cts_main_loop(const struct cts_test *tests, const char *name) { enum cts_rc rc; int i; -- cgit v1.2.1 From 9f5a844244b1152c4b0535bd8507be1ebc7e3018 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:07:56 -0600 Subject: include/body_detection.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2bef98a0cf4a08f3720de548391fe8183dcf7259 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730214 Reviewed-by: Jeremy Bettis --- include/body_detection.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/include/body_detection.h b/include/body_detection.h index 59af6580c6..87c6d91b18 100644 --- a/include/body_detection.h +++ b/include/body_detection.h @@ -9,10 +9,7 @@ #include #include -enum body_detect_states { - BODY_DETECTION_OFF_BODY, - BODY_DETECTION_ON_BODY -}; +enum body_detect_states { BODY_DETECTION_OFF_BODY, BODY_DETECTION_ON_BODY }; /* get/set the state of body detection */ enum body_detect_states body_detect_get_state(void); -- cgit v1.2.1 From c546e1b07ec88cd9749b42720ae0593b86292a1c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:22:33 -0600 Subject: test/shmalloc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb5eda7d533a472645e65c54a5425c16e4531eee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730522 Reviewed-by: Jeremy Bettis --- test/shmalloc.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/test/shmalloc.c b/test/shmalloc.c index a596d173e7..b77f720ac9 100644 --- a/test/shmalloc.c +++ b/test/shmalloc.c @@ -36,14 +36,14 @@ static uint32_t next = 127; static uint32_t myrand(void) { next = next * 1103515245 + 12345; - return ((uint32_t)(next/65536) % 32768); + return ((uint32_t)(next / 65536) % 32768); } /* Keep track of buffers allocated by the test function. */ static struct { void *buf; size_t buffer_size; -} allocations[12]; /* Up to 12 buffers could be allocated concurrently. */ +} allocations[12]; /* Up to 12 buffers could be allocated concurrently. */ /* * Verify that allocated and free buffers do not overlap, and that our and @@ -77,8 +77,7 @@ static int check_for_overlaps(void) * multiple times to keep things simple. */ allocated_count = 0; - for (allocced_buf = allocced_buf_chain; - allocced_buf; + for (allocced_buf = allocced_buf_chain; allocced_buf; allocced_buf = allocced_buf->next_buffer) { int allocated_size, allocation_size; @@ -117,8 +116,8 @@ static int check_for_overlaps(void) } } if (allocations_count != allocated_count) { - ccprintf("count mismatch (%d != %d)!\n", - allocations_count, allocated_count); + ccprintf("count mismatch (%d != %d)!\n", allocations_count, + allocated_count); return 0; } return 1; @@ -146,10 +145,10 @@ static int shmem_is_ok(int line) running_size += pbuf->buffer_size; if (count++ > 100) - goto bailout; /* Is there a loop? */ + goto bailout; /* Is there a loop? */ top = (struct shm_buffer *)((uintptr_t)pbuf + - pbuf->buffer_size); + pbuf->buffer_size); if (pbuf->next_buffer) { if (top >= pbuf->next_buffer) { ccprintf("%s:%d" @@ -193,7 +192,7 @@ static int shmem_is_ok(int line) return 1; - bailout: +bailout: ccprintf("Line %d, counter %d. The list has been corrupted, " "total size %d, running size %d\n", line, counter, total_size, running_size); @@ -229,8 +228,7 @@ void run_test(int argc, char **argv) if (test_map & ~ALL_PATHS_MASK) { ccprintf("Unexpected mask bits set: %x" ", counter %d\n", - test_map & ~ALL_PATHS_MASK, - counter); + test_map & ~ALL_PATHS_MASK, counter); test_fail(); return; } @@ -261,7 +259,7 @@ void run_test(int argc, char **argv) */ if (shared_mem_acquire(alloc_size, &shptr) == EC_SUCCESS) { - allocations[index].buf = (void *) shptr; + allocations[index].buf = (void *)shptr; allocations[index].buffer_size = alloc_size; /* @@ -269,8 +267,8 @@ void run_test(int argc, char **argv) * modified. */ while (alloc_size--) - shptr[alloc_size] = - shptr[alloc_size] ^ 0xff; + shptr[alloc_size] = shptr[alloc_size] ^ + 0xff; if (!shmem_is_ok(__LINE__)) { test_fail(); @@ -294,8 +292,8 @@ void run_test(int argc, char **argv) } } - ccprintf("Did not pass all paths, map %x != %x\n", - test_map, ALL_PATHS_MASK); + ccprintf("Did not pass all paths, map %x != %x\n", test_map, + ALL_PATHS_MASK); test_fail(); } -- cgit v1.2.1 From 681d0b5e60f0ece1ffdd5e853e583b00120adc9f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:08 -0600 Subject: board/adlrvpp_npcx/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id51e7619c315cd1b5c9e778a588ea2f2c99f1026 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727968 Reviewed-by: Jeremy Bettis --- board/adlrvpp_npcx/board.h | 76 +++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/board/adlrvpp_npcx/board.h b/board/adlrvpp_npcx/board.h index c787beea84..3db2df61b6 100644 --- a/board/adlrvpp_npcx/board.h +++ b/board/adlrvpp_npcx/board.h @@ -20,76 +20,76 @@ * which purpose. */ /* Power sequencing */ -#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N -#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3 -#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N -#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N -#define GPIO_EN_PP3300_A GPIO_EC_DS3 -#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK -#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK +#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N +#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3 +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N +#define GPIO_EN_PP3300_A GPIO_EC_DS3 +#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK +#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK /* Sensors */ -#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N +#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N /* Buttons */ -#define GPIO_LID_OPEN GPIO_SMC_LID -#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP -#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL /* H1 */ -#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW /* AC & Battery */ -#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT -#define GPIO_AC_PRESENT GPIO_BC_ACOK -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT +#define GPIO_AC_PRESENT GPIO_BC_ACOK +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET /* eSPI/Host communication */ -#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N -#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC -#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL +#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N +#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC +#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL /* LED */ -#define GPIO_BAT_LED_RED_L GPIO_LED_1_L -#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L +#define GPIO_BAT_LED_RED_L GPIO_LED_1_L +#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L /* FAN */ -#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC +#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC /* I2C ports & Configs */ /* Charger */ -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 /* Battery */ -#define I2C_PORT_BATTERY NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT7_0 /* Board ID */ -#define I2C_PORT_PCA9555_BOARD_ID_GPIO NPCX_I2C_PORT7_0 +#define I2C_PORT_PCA9555_BOARD_ID_GPIO NPCX_I2C_PORT7_0 /* Port 80 */ -#define I2C_PORT_PORT80 NPCX_I2C_PORT7_0 +#define I2C_PORT_PORT80 NPCX_I2C_PORT7_0 /* USB-C I2C */ -#define I2C_PORT_TYPEC_0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TYPEC_0 NPCX_I2C_PORT0_0 /* * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2 * on the RVP to reduce BOM stuffing options. */ -#define I2C_PORT_TYPEC_1 NPCX_I2C_PORT2_0 +#define I2C_PORT_TYPEC_1 NPCX_I2C_PORT2_0 #if defined(HAS_TASK_PD_C2) -#define I2C_PORT_TYPEC_2 NPCX_I2C_PORT1_0 +#define I2C_PORT_TYPEC_2 NPCX_I2C_PORT1_0 #endif #if defined(HAS_TASK_PD_C3) -#define I2C_PORT_TYPEC_3 NPCX_I2C_PORT3_0 +#define I2C_PORT_TYPEC_3 NPCX_I2C_PORT3_0 #endif #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 0d00f4f0c14ae5fce8e75e21b9cd38ef88e73ef6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:19:31 -0600 Subject: chip/mchp/gpspi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iba7593813e4ade6e57cc094b212a8200b2373d61 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729293 Reviewed-by: Jeremy Bettis --- chip/mchp/gpspi.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c index c92813b300..963cb3507c 100644 --- a/chip/mchp/gpspi.c +++ b/chip/mchp/gpspi.c @@ -20,7 +20,7 @@ #include "tfdp_chip.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) /* One byte at 12 MHz full duplex = 0.67 us */ @@ -91,8 +91,8 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) #endif int gpspi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int hw_port, ctrl; int ret = EC_SUCCESS; @@ -232,7 +232,6 @@ int gpspi_enable(int hw_port, int enable) ctrl = (uint32_t)hw_port & 0x0f; if (enable) { - if (ctrl) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_GPSPI1); else -- cgit v1.2.1 From c95e4f934372c084ad06f1228aebb91c6964c42c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:09:59 -0600 Subject: board/vell/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iff32ac9ffbd170e7987d738f01a39af8907fbe16 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729067 Reviewed-by: Jeremy Bettis --- board/vell/sensors.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/board/vell/sensors.c b/board/vell/sensors.c index 0528a62717..ed2281b3fc 100644 --- a/board/vell/sensors.c +++ b/board/vell/sensors.c @@ -207,8 +207,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(95), \ @@ -225,8 +225,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(95), \ @@ -244,8 +244,8 @@ __maybe_unused static const struct ec_thermal_config thermal_charger = /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_WWAN \ - { \ +#define THERMAL_WWAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -264,8 +264,8 @@ __maybe_unused static const struct ec_thermal_config thermal_wwan = * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_DDR \ - { \ +#define THERMAL_DDR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -274,8 +274,7 @@ __maybe_unused static const struct ec_thermal_config thermal_wwan = [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ }, \ } -__maybe_unused static const struct ec_thermal_config thermal_ddr = - THERMAL_DDR; +__maybe_unused static const struct ec_thermal_config thermal_ddr = THERMAL_DDR; /* * TODO(b/203839956): update for Alder Lake/vell @@ -284,8 +283,8 @@ __maybe_unused static const struct ec_thermal_config thermal_ddr = * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_REGULATOR \ - { \ +#define THERMAL_REGULATOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(80), \ [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ @@ -299,7 +298,7 @@ __maybe_unused static const struct ec_thermal_config thermal_regulator = struct ec_thermal_config thermal_params[] = { [TEMP_SENSOR_1_SOC] = thermal_cpu, - [TEMP_SENSOR_2_CHARGER] = thermal_charger, + [TEMP_SENSOR_2_CHARGER] = thermal_charger, [TEMP_SENSOR_3_WWAN] = thermal_wwan, [TEMP_SENSOR_4_DDR] = thermal_ddr, [TEMP_SENSOR_5_REGULATOR] = thermal_regulator, -- cgit v1.2.1 From c68b4f83ef79dd3c15dc0ac11e674e4e0a596d51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:51 -0600 Subject: include/driver/temp_sensor/thermistor.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If0d5183eac01d0f822b013bd340d8d6d825162c3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730257 Reviewed-by: Jeremy Bettis --- include/driver/temp_sensor/thermistor.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/driver/temp_sensor/thermistor.h b/include/driver/temp_sensor/thermistor.h index adcd5c5be4..84e19b90c9 100644 --- a/include/driver/temp_sensor/thermistor.h +++ b/include/driver/temp_sensor/thermistor.h @@ -9,13 +9,13 @@ #define __CROS_EC_TEMP_SENSOR_THERMISTOR_H struct thermistor_data_pair { - uint8_t mv; /* Scaled voltage level at ADC (in mV) */ - uint8_t temp; /* Temperature in Celsius */ + uint8_t mv; /* Scaled voltage level at ADC (in mV) */ + uint8_t temp; /* Temperature in Celsius */ }; struct thermistor_info { - uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ - uint8_t num_pairs; /* Number of data pairs. */ + uint8_t scaling_factor; /* Scaling factor for voltage in data pair. */ + uint8_t num_pairs; /* Number of data pairs. */ /* * Values between given data pairs will be calculated as points on -- cgit v1.2.1 From 180fdb326031ab476137b89bf8238aa79e10edc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:45:00 -0600 Subject: board/madoo/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8726694cb17d4a4529553296198b1137b62a2844 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728626 Reviewed-by: Jeremy Bettis --- board/madoo/battery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/madoo/battery.c b/board/madoo/battery.c index 92afe149f3..f3c87c7455 100644 --- a/board/madoo/battery.c +++ b/board/madoo/battery.c @@ -12,7 +12,7 @@ #include "extpower.h" /* Shutdown mode parameter to write to manufacturer access register */ -#define SB_SHUTDOWN_DATA 0x0010 +#define SB_SHUTDOWN_DATA 0x0010 const struct board_batt_params board_battery_info[] = { [BATTERY_SIMPLO_HIGHPOWER] = { -- cgit v1.2.1 From e4f5bac08de9ade73489b0430e14adc85a13c6fc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:27 -0600 Subject: board/servo_v4/usb_pd_pdo.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic8b2cb4e147959cf8d8c273187e1b8862e5f46b9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728921 Reviewed-by: Jeremy Bettis --- board/servo_v4/usb_pd_pdo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/servo_v4/usb_pd_pdo.c b/board/servo_v4/usb_pd_pdo.c index 8df0eac2c2..225f17d99c 100644 --- a/board/servo_v4/usb_pd_pdo.c +++ b/board/servo_v4/usb_pd_pdo.c @@ -12,9 +12,9 @@ #define CHG_PDO_FIXED_FLAGS (PDO_FIXED_DATA_SWAP) const uint32_t pd_snk_pdo[] = { - PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), - PDO_BATT(4750, 21000, 15000), - PDO_VAR(4750, 21000, 3000), + PDO_FIXED(5000, 500, CHG_PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), }; const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); @@ -48,7 +48,7 @@ int charge_manager_get_source_pdo(const uint32_t **src_pdo, const int port) * port, otherwise we provide no power. */ if (charge_port_is_active()) { - *src_pdo = pd_src_chg_pdo; + *src_pdo = pd_src_chg_pdo; pdo_cnt = chg_pdo_cnt; } -- cgit v1.2.1 From 208b79694a6eb26f1949fd0c59392d71020337ef Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:30:50 -0600 Subject: zephyr/include/emul/tcpc/emul_ps8xxx.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icce5ea7e9f303513b1e99867590e577b1edfa3bc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730725 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_ps8xxx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/include/emul/tcpc/emul_ps8xxx.h b/zephyr/include/emul/tcpc/emul_ps8xxx.h index aff21e94c7..75091f2232 100644 --- a/zephyr/include/emul/tcpc/emul_ps8xxx.h +++ b/zephyr/include/emul/tcpc/emul_ps8xxx.h @@ -47,7 +47,7 @@ enum ps8xxx_emul_port { }; /* For now all devices supported by this emulator has the same FW rev reg */ -#define PS8XXX_REG_FW_REV 0x82 +#define PS8XXX_REG_FW_REV 0x82 /** * @brief Get pointer to specific "hidden" I2C device -- cgit v1.2.1 From 7ab7343fed7c0fce39864dac8b45549b8f04a5e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:28 -0600 Subject: board/jinlon/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3a52945307a6aaec0887b063640c54e8ab3f4861 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728519 Reviewed-by: Jeremy Bettis --- board/jinlon/thermal.c | 129 +++++++++++++++++++++++++------------------------ 1 file changed, 66 insertions(+), 63 deletions(-) diff --git a/board/jinlon/thermal.c b/board/jinlon/thermal.c index 03437fa3cd..a62adf6ea2 100644 --- a/board/jinlon/thermal.c +++ b/board/jinlon/thermal.c @@ -16,7 +16,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -40,109 +40,108 @@ static const struct fan_step *fan_step_table; static const struct fan_step fan_table_clamshell[] = { { /* level 0 */ - .on = {0, -1, 54, 37}, - .off = {99, -1, 99, 99}, - .rpm = {0, 0}, + .on = { 0, -1, 54, 37 }, + .off = { 99, -1, 99, 99 }, + .rpm = { 0, 0 }, }, { /* level 1 */ - .on = {0, -1, 57, 39}, - .off = {99, -1, 54, 37}, - .rpm = {3950, 3850}, + .on = { 0, -1, 57, 39 }, + .off = { 99, -1, 54, 37 }, + .rpm = { 3950, 3850 }, }, { /* level 2 */ - .on = {0, -1, 58, 40}, - .off = {99, -1, 57, 39}, - .rpm = {4200, 4100}, + .on = { 0, -1, 58, 40 }, + .off = { 99, -1, 57, 39 }, + .rpm = { 4200, 4100 }, }, { /* level 3 */ - .on = {0, -1, 59, 41}, - .off = {99, -1, 58, 40}, - .rpm = {4550, 4450}, + .on = { 0, -1, 59, 41 }, + .off = { 99, -1, 58, 40 }, + .rpm = { 4550, 4450 }, }, { /* level 4 */ - .on = {62, -1, 60, 42}, - .off = {58, -1, 59, 41}, - .rpm = {4900, 4800}, + .on = { 62, -1, 60, 42 }, + .off = { 58, -1, 59, 41 }, + .rpm = { 4900, 4800 }, }, { /* level 5 */ - .on = {64, -1, 61, 43}, - .off = {62, -1, 60, 42}, - .rpm = {5250, 5150}, + .on = { 64, -1, 61, 43 }, + .off = { 62, -1, 60, 42 }, + .rpm = { 5250, 5150 }, }, { /* level 6 */ - .on = {65, -1, 64, 45}, - .off = {63, -1, 61, 43}, - .rpm = {5400, 5300}, + .on = { 65, -1, 64, 45 }, + .off = { 63, -1, 61, 43 }, + .rpm = { 5400, 5300 }, }, { /* level 7 */ - .on = {100, -1, 100, 100}, - .off = {65, -1, 62, 44}, - .rpm = {6000, 5900}, + .on = { 100, -1, 100, 100 }, + .off = { 65, -1, 62, 44 }, + .rpm = { 6000, 5900 }, }, }; static const struct fan_step fan_table_tablet[] = { { /* level 0 */ - .on = {0, -1, 55, 41}, - .off = {99, -1, 99, 99}, - .rpm = {0, 0}, + .on = { 0, -1, 55, 41 }, + .off = { 99, -1, 99, 99 }, + .rpm = { 0, 0 }, }, { /* level 1 */ - .on = {0, -1, 56, 42}, - .off = {99, -1, 55, 41}, - .rpm = {0, 0}, + .on = { 0, -1, 56, 42 }, + .off = { 99, -1, 55, 41 }, + .rpm = { 0, 0 }, }, { /* level 2 */ - .on = {0, -1, 57, 43}, - .off = {99, -1, 56, 42}, - .rpm = {4000, 3350}, + .on = { 0, -1, 57, 43 }, + .off = { 99, -1, 56, 42 }, + .rpm = { 4000, 3350 }, }, { /* level 3 */ - .on = {0, -1, 58, 44}, - .off = {99, -1, 57, 43}, - .rpm = {4200, 3400}, + .on = { 0, -1, 58, 44 }, + .off = { 99, -1, 57, 43 }, + .rpm = { 4200, 3400 }, }, { /* level 4 */ - .on = {60, -1, 59, 45}, - .off = {58, -1, 58, 44}, - .rpm = {4400, 3500}, + .on = { 60, -1, 59, 45 }, + .off = { 58, -1, 58, 44 }, + .rpm = { 4400, 3500 }, }, { /* level 5 */ - .on = {62, -1, 60, 46}, - .off = {60, -1, 59, 45}, - .rpm = {4800, 4350}, + .on = { 62, -1, 60, 46 }, + .off = { 60, -1, 59, 45 }, + .rpm = { 4800, 4350 }, }, { /* level 6 */ - .on = {65, -1, 61, 47}, - .off = {62, -1, 60, 46}, - .rpm = {5000, 4500}, + .on = { 65, -1, 61, 47 }, + .off = { 62, -1, 60, 46 }, + .rpm = { 5000, 4500 }, }, { /* level 7 */ - .on = {100, -1, 100, 100}, - .off = {65, -1, 61, 47}, - .rpm = {5200, 5100}, + .on = { 100, -1, 100, 100 }, + .off = { 65, -1, 61, 47 }, + .rpm = { 5200, 5100 }, }, }; #define NUM_FAN_LEVELS ARRAY_SIZE(fan_table_clamshell) -BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == - ARRAY_SIZE(fan_table_tablet)); +BUILD_ASSERT(ARRAY_SIZE(fan_table_clamshell) == ARRAY_SIZE(fan_table_tablet)); int fan_table_to_rpm(int fan, int *temp) { @@ -165,12 +164,15 @@ int fan_table_to_rpm(int fan, int *temp) */ if (temp[TEMP_SENSOR_1] < prev_tmp[TEMP_SENSOR_1] || - temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] || - temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) { + temp[TEMP_SENSOR_3] < prev_tmp[TEMP_SENSOR_3] || + temp[TEMP_SENSOR_4] < prev_tmp[TEMP_SENSOR_4]) { for (i = current_level; i > 0; i--) { - if (temp[TEMP_SENSOR_1] < fan_step_table[i].off[TEMP_SENSOR_1] && - temp[TEMP_SENSOR_4] < fan_step_table[i].off[TEMP_SENSOR_4] && - temp[TEMP_SENSOR_3] < fan_step_table[i].off[TEMP_SENSOR_3]) + if (temp[TEMP_SENSOR_1] < + fan_step_table[i].off[TEMP_SENSOR_1] && + temp[TEMP_SENSOR_4] < + fan_step_table[i].off[TEMP_SENSOR_4] && + temp[TEMP_SENSOR_3] < + fan_step_table[i].off[TEMP_SENSOR_3]) current_level = i - 1; else break; @@ -179,9 +181,12 @@ int fan_table_to_rpm(int fan, int *temp) temp[TEMP_SENSOR_3] > prev_tmp[TEMP_SENSOR_3] || temp[TEMP_SENSOR_4] > prev_tmp[TEMP_SENSOR_4]) { for (i = current_level; i < NUM_FAN_LEVELS; i++) { - if ((temp[TEMP_SENSOR_1] > fan_step_table[i].on[TEMP_SENSOR_1] && - temp[TEMP_SENSOR_4] > fan_step_table[i].on[TEMP_SENSOR_4]) || - temp[TEMP_SENSOR_3] > fan_step_table[i].on[TEMP_SENSOR_3]) + if ((temp[TEMP_SENSOR_1] > + fan_step_table[i].on[TEMP_SENSOR_1] && + temp[TEMP_SENSOR_4] > + fan_step_table[i].on[TEMP_SENSOR_4]) || + temp[TEMP_SENSOR_3] > + fan_step_table[i].on[TEMP_SENSOR_3]) current_level = i + 1; else break; @@ -212,10 +217,8 @@ int fan_table_to_rpm(int fan, int *temp) void board_override_fan_control(int fan, int *tmp) { - if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND)) { + if (chipset_in_state(CHIPSET_STATE_ON | CHIPSET_STATE_ANY_SUSPEND)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, tmp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, tmp)); } } -- cgit v1.2.1 From 30f16aa311f3a0c9cfbda47bf2fe02f654468187 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:24 -0600 Subject: board/endeavour/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ied1bc054842985c82d11115b1656c261f9881036 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728294 Reviewed-by: Jeremy Bettis --- board/endeavour/led.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/endeavour/led.c b/board/endeavour/led.c index b75de503e5..95d2592801 100644 --- a/board/endeavour/led.c +++ b/board/endeavour/led.c @@ -15,7 +15,7 @@ #include "timer.h" #include "util.h" -const enum ec_led_id supported_led_ids[] = {EC_LED_ID_POWER_LED}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); enum led_color { @@ -71,9 +71,9 @@ static int set_color(enum ec_led_id id, enum led_color color, int duty) } } -#define LED_PULSE_US (2 * SECOND) +#define LED_PULSE_US (2 * SECOND) /* 40 msec for nice and smooth transition. */ -#define LED_PULSE_TICK_US (40 * MSEC) +#define LED_PULSE_TICK_US (40 * MSEC) /* When pulsing is enabled, brightness is incremented by every * usec from 0 to 100% in LED_PULSE_US usec. Then it's decremented @@ -190,8 +190,7 @@ static int command_led(int argc, char **argv) } return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(led, command_led, - "[debug|red|white|off|crit]", +DECLARE_CONSOLE_COMMAND(led, command_led, "[debug|red|white|off|crit]", "Turn on/off LED."); void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From d2aec63c0cb4224cd9813bf9277286de827c2a22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:13 -0600 Subject: zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic29145991de7de66c84a1400ae18eb36834b8e9c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730935 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c index 5183824117..de3b4d7656 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_mtl_pwrseq_sm.c @@ -33,8 +33,8 @@ static void generate_pwrok_handler(void) power_signal_set(PWR_EC_PCH_SYS_PWROK, all_sys_pwrgd_in); /* PCH_PWROK is set to combined result of ALL_SYS_PWRGD and SLP_S3 */ - power_signal_set(PWR_PCH_PWROK, all_sys_pwrgd_in && - !power_signal_get(PWR_SLP_S3)); + power_signal_set(PWR_PCH_PWROK, + all_sys_pwrgd_in && !power_signal_get(PWR_SLP_S3)); } /* Chipset specific power state machine handler */ -- cgit v1.2.1 From 0083ecb8ff6f65306cb7693a2891f3cf5c5f2b8f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:13:14 -0600 Subject: board/woomax/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0e36b941395717d025b04a0bd20e0978dca6a4eb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729134 Reviewed-by: Jeremy Bettis --- board/woomax/led.c | 50 +++++++++++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 21 deletions(-) diff --git a/board/woomax/led.c b/board/woomax/led.c index 4c229d86f5..5eee8367bb 100644 --- a/board/woomax/led.c +++ b/board/woomax/led.c @@ -17,29 +17,37 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_WHITE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, -- cgit v1.2.1 From 9a6651b6eb5861062c3c22b7d6a5e615bcab6e13 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:30 -0600 Subject: chip/stm32/registers-stm32l4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I53cca7d69dc4d3e08fe095c25e7d44796d07860d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729409 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32l4.h | 1899 ++++++++++++++++++++-------------------- 1 file changed, 947 insertions(+), 952 deletions(-) diff --git a/chip/stm32/registers-stm32l4.h b/chip/stm32/registers-stm32l4.h index 156994cc10..c70a3bf862 100644 --- a/chip/stm32/registers-stm32l4.h +++ b/chip/stm32/registers-stm32l4.h @@ -20,364 +20,364 @@ #endif /****** STM32 specific Interrupt Numbers ********/ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD_PVM 1 -#define STM32_IRQ_TAMP_STAMP 2 -#define STM32_IRQ_RTC_WKUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_CAN1_TX 19 -#define STM32_IRQ_CAN1_RX0 20 -#define STM32_IRQ_CAN1_RX1 21 -#define STM32_IRQ_CAN1_SCE 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM1_BRK_TIM15 24 -#define STM32_IRQ_TIM1_UP_TIM16 25 -#define STM32_IRQ_TIM1_TRG_COM 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_SDMMC1 49 -#define STM32_IRQ_TIM5 50 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_COMP 64 -#define LSTM32_IRQ_PTIM1 65 -#define STM32_IRQ_LPTIM2 66 -#define STM32_IRQ_DMA2_CHANNEL6 68 -#define STM32_IRQ_DMA2_CHANNEL7 69 -#define STM32_IRQ_LPUART1 70 -#define STM32_IRQ_QUADSPI 71 -#define STM32_IRQ_I2C3_EV 72 -#define STM32_IRQ_I2C3_ER 73 -#define STM32_IRQ_SAI1 74 -#define STM32_IRQ_SWPMI1 76 -#define STM32_IRQ_TSC 77 -#define STM32_IRQ_RNG 80 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_CRS 82 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD_PVM 1 +#define STM32_IRQ_TAMP_STAMP 2 +#define STM32_IRQ_RTC_WKUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_ADC1 18 +#define STM32_IRQ_CAN1_TX 19 +#define STM32_IRQ_CAN1_RX0 20 +#define STM32_IRQ_CAN1_RX1 21 +#define STM32_IRQ_CAN1_SCE 22 +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM1_BRK_TIM15 24 +#define STM32_IRQ_TIM1_UP_TIM16 25 +#define STM32_IRQ_TIM1_TRG_COM 26 +#define STM32_IRQ_TIM1_CC 27 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_SDMMC1 49 +#define STM32_IRQ_TIM5 50 +#define STM32_IRQ_SPI3 51 +#define STM32_IRQ_TIM6_DAC 54 +#define STM32_IRQ_TIM7 55 +#define STM32_IRQ_DMA2_CHANNEL1 56 +#define STM32_IRQ_DMA2_CHANNEL2 57 +#define STM32_IRQ_DMA2_CHANNEL3 58 +#define STM32_IRQ_DMA2_CHANNEL4 59 +#define STM32_IRQ_DMA2_CHANNEL5 60 +#define STM32_IRQ_COMP 64 +#define LSTM32_IRQ_PTIM1 65 +#define STM32_IRQ_LPTIM2 66 +#define STM32_IRQ_DMA2_CHANNEL6 68 +#define STM32_IRQ_DMA2_CHANNEL7 69 +#define STM32_IRQ_LPUART1 70 +#define STM32_IRQ_QUADSPI 71 +#define STM32_IRQ_I2C3_EV 72 +#define STM32_IRQ_I2C3_ER 73 +#define STM32_IRQ_SAI1 74 +#define STM32_IRQ_SWPMI1 76 +#define STM32_IRQ_TSC 77 +#define STM32_IRQ_RNG 80 +#define STM32_IRQ_FPU 81 +#define STM32_IRQ_CRS 82 /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 -#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 -#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 - +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_11 STM32_IRQ_DMA2_CHANNEL3 +#define STM32_IRQ_DMA_CHANNEL_12 STM32_IRQ_DMA2_CHANNEL4 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL5 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_15 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_USART9 STM32_IRQ_LPUART1 /* Peripheral base addresses */ -#define FLASH_BASE 0x08000000UL -#define FLASH_END 0x0803FFFFUL -#define FLASH_BANK1_END 0x0803FFFFUL -#define SRAM1_BASE 0x20000000UL -#define SRAM2_BASE 0x10000000UL -#define PERIPH_BASE 0x40000000UL -#define QSPI_BASE 0x90000000UL -#define QSPI_R_BASE 0xA0001000UL -#define SRAM1_BB_BASE 0x22000000UL -#define PERIPH_BB_BASE 0x42000000UL +#define FLASH_BASE 0x08000000UL +#define FLASH_END 0x0803FFFFUL +#define FLASH_BANK1_END 0x0803FFFFUL +#define SRAM1_BASE 0x20000000UL +#define SRAM2_BASE 0x10000000UL +#define PERIPH_BASE 0x40000000UL +#define QSPI_BASE 0x90000000UL +#define QSPI_R_BASE 0xA0001000UL +#define SRAM1_BB_BASE 0x22000000UL +#define PERIPH_BB_BASE 0x42000000UL /* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE -#define SRAM1_SIZE_MAX 0x0000C000UL -#define SRAM2_SIZE 0x00004000UL +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE +#define SRAM1_SIZE_MAX 0x0000C000UL +#define SRAM2_SIZE 0x00004000UL #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0) -#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) \ - & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x100U << 10U) : \ - (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & \ - (0x0000FFFFU)) << 10U)) +#define FLASH_SIZE \ + (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == \ + 0x0000FFFFU)) ? \ + (0x100U << 10U) : \ + (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) \ + << 10U)) /*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) /*!< APB1 peripherals */ -#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) -#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) -#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) -#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) -#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) -#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) -#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) - -#define STM32_USART9_BASE STM32_LPUART1_BASE +#define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define STM32_TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define STM32_TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define STM32_TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define STM32_RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define STM32_WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define STM32_IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define STM32_SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define STM32_SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define STM32_USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define STM32_USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define STM32_I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define STM32_I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define STM32_I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define STM32_CRS_BASE (APB1PERIPH_BASE + 0x6000UL) +#define STM32_CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define STM32_PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define STM32_DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define STM32_OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define STM32_LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define STM32_LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define STM32_SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define STM32_LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + +#define STM32_USART9_BASE STM32_LPUART1_BASE /*!< APB2 peripherals */ -#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) -#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) -#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) -#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) -#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) -#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) -#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) -#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) -#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) -#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) -#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define STM32_SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define STM32_VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define STM32_OMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define STM32_COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define STM32_EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define STM32_FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define STM32_SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define STM32_TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define STM32_SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define STM32_USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define STM32_TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define STM32_TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define STM32_SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /*!< AHB1 peripherals */ -#define STM32_DMA1_BASE (AHB1PERIPH_BASE) -#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) -#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) -#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) -#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) -#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) -#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) -#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) -#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) -#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) -#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) -#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) -#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) -#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) -#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) -#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) -#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) -#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) +#define STM32_DMA1_BASE (AHB1PERIPH_BASE) +#define STM32_DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define STM32_RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define STM32_FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define STM32_CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define STM32_TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) +#define STM32_DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define STM32_DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define STM32_DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define STM32_DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define STM32_DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define STM32_DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define STM32_DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define STM32_DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) +#define STM32_DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define STM32_DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define STM32_DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define STM32_DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define STM32_DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define STM32_DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define STM32_DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define STM32_DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) /*!< AHB2 peripherals */ -#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) -#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) -#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) -#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) -#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) -#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) -#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ -#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) -#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) -#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) -#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) +#define STM32_GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define STM32_GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define STM32_GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define STM32_GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define STM32_GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define STM32_GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define STM32_GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) /* stm32l4x6 */ +#define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) +#define STM32_ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define STM32_ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) +#define STM32_RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) /* Debug MCU registers base address */ -#define STM32_DBGMCU_BASE 0xE0042000UL -#define STM32_PACKAGE_BASE 0x1FFF7500UL -#define STM32_UID_BASE 0x1FFF7590UL -#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL +#define STM32_DBGMCU_BASE 0xE0042000UL +#define STM32_PACKAGE_BASE 0x1FFF7500UL +#define STM32_UID_BASE 0x1FFF7590UL +#define STM32_FLASHSIZE_BASE 0x1FFF75E0UL -#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE -#define STM32_UNIQUE_ID_BASE STM32_UID_BASE -#define STM32_OPTB_BASE 0x1FFF7800 +#define STM32_FLASH_REGS_BASE STM32_FLASH_R_BASE +#define STM32_UNIQUE_ID_BASE STM32_UID_BASE +#define STM32_OPTB_BASE 0x1FFF7800 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) - -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) + +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) #define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) - -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR3_WUFIE BIT(22) + +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) -#define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ - -#define GPIO_ALT_F0 0x0 -#define GPIO_ALT_F1 0x1 -#define GPIO_ALT_F2 0x2 -#define GPIO_ALT_F3 0x3 -#define GPIO_ALT_F4 0x4 -#define GPIO_ALT_F5 0x5 -#define GPIO_ALT_F6 0x6 -#define GPIO_ALT_F7 0x7 -#define GPIO_ALT_F8 0x8 -#define GPIO_ALT_F9 0x9 -#define GPIO_ALT_FA 0xA -#define GPIO_ALT_FB 0xB -#define GPIO_ALT_FC 0xC -#define GPIO_ALT_FD 0xD -#define GPIO_ALT_FE 0xE -#define GPIO_ALT_FF 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) +#define STM32_GPIO_BRR(b) REG32((b) + 0x28) +#define STM32_GPIO_ASCR(b) REG32((b) + 0x2C) /* only for stm32l4x6 */ + +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 +#define GPIO_ALT_F6 0x6 +#define GPIO_ALT_F7 0x7 +#define GPIO_ALT_F8 0x8 +#define GPIO_ALT_F9 0x9 +#define GPIO_ALT_FA 0xA +#define GPIO_ALT_FB 0xB +#define GPIO_ALT_FC 0xC +#define GPIO_ALT_FD 0xD +#define GPIO_ALT_FE 0xE +#define GPIO_ALT_FF 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) -#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) -#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) -#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) -#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 -#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_ADDCODE(isr) (((isr) >> 16) & 0xfe) +#define STM32_I2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_I2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_I2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) - -#define PWR_CR1_LPMS_POS 0U -#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) -#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK -#define PWR_CR1_LPMS_STOP0 (0x00000000UL) -#define PWR_CR1_LPMS_STOP1_POS 0U -#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) -#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK -#define PWR_CR1_LPMS_STOP2_POS 1U -#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) -#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK -#define PWR_CR1_LPMS_STANDBY_POS 0U -#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) -#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK -#define PWR_CR1_LPMS_SHUTDOWN_POS 2U -#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) -#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK -#define PWR_CR1_VOS_POS 9U -#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS PWR_CR1_VOS_MSK -#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) -#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) - +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) + +#define PWR_CR1_LPMS_POS 0U +#define PWR_CR1_LPMS_MSK (0x7UL << PWR_CR1_LPMS_POS) +#define PWR_CR1_LPMS PWR_CR1_LPMS_MSK +#define PWR_CR1_LPMS_STOP0 (0x00000000UL) +#define PWR_CR1_LPMS_STOP1_POS 0U +#define PWR_CR1_LPMS_STOP1_MSK (0x1UL << PWR_CR1_LPMS_STOP1_POS) +#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_MSK +#define PWR_CR1_LPMS_STOP2_POS 1U +#define PWR_CR1_LPMS_STOP2_MSK (0x1UL << PWR_CR1_LPMS_STOP2_POS) +#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_MSK +#define PWR_CR1_LPMS_STANDBY_POS 0U +#define PWR_CR1_LPMS_STANDBY_MSK (0x3UL << PWR_CR1_LPMS_STANDBY_POS) +#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_MSK +#define PWR_CR1_LPMS_SHUTDOWN_POS 2U +#define PWR_CR1_LPMS_SHUTDOWN_MSK (0x1UL << PWR_CR1_LPMS_SHUTDOWN_POS) +#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_MSK +#define PWR_CR1_VOS_POS 9U +#define PWR_CR1_VOS_MSK (0x3UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS PWR_CR1_VOS_MSK +#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_POS) +#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_POS) /* --- Macro usage in ec code --- */ #define STM32_RCC_AHB2ENR_GPIOMASK \ @@ -388,133 +388,131 @@ #define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) #define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) #define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN +#define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN -#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN -#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN -#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN +#define STM32_RCC_PB2_TIM1 STM32_RCC_APB2ENR_TIM1EN +#define STM32_RCC_PB2_TIM15 STM32_RCC_APB2ENR_TIM15EN +#define STM32_RCC_PB2_TIM16 STM32_RCC_APB2ENR_TIM16EN #ifndef CHIP_VARIANT_STM32L431X -#define STM32_RCC_PB2_TIM8 BIT(13) +#define STM32_RCC_PB2_TIM8 BIT(13) #endif #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTH BIT(7) #define STM32_RCC_CCIPR_USART1SEL_SHIFT (0) -#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) +#define STM32_RCC_CCIPR_USART1SEL_MASK (3 << STM32_RCC_CCIPR_USART1SEL_SHIFT) #define STM32_RCC_CCIPR_USART2SEL_SHIFT (2) -#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) +#define STM32_RCC_CCIPR_USART2SEL_MASK (3 << STM32_RCC_CCIPR_USART2SEL_SHIFT) #define STM32_RCC_CCIPR_USART3SEL_SHIFT (4) -#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) +#define STM32_RCC_CCIPR_USART3SEL_MASK (3 << STM32_RCC_CCIPR_USART3SEL_SHIFT) #define STM32_RCC_CCIPR_UART4SEL_SHIFT (6) -#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) +#define STM32_RCC_CCIPR_UART4SEL_MASK (3 << STM32_RCC_CCIPR_UART4SEL_SHIFT) #define STM32_RCC_CCIPR_UART5SEL_SHIFT (8) -#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) +#define STM32_RCC_CCIPR_UART5SEL_MASK (3 << STM32_RCC_CCIPR_UART5SEL_SHIFT) #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT (10) -#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPUART1SEL_MASK (3 << STM32_RCC_CCIPR_LPUART1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C1SEL_SHIFT (12) -#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C1SEL_MASK (3 << STM32_RCC_CCIPR_I2C1SEL_SHIFT) #define STM32_RCC_CCIPR_I2C2SEL_SHIFT (14) -#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C2SEL_MASK (3 << STM32_RCC_CCIPR_I2C2SEL_SHIFT) #define STM32_RCC_CCIPR_I2C3SEL_SHIFT (16) -#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) +#define STM32_RCC_CCIPR_I2C3SEL_MASK (3 << STM32_RCC_CCIPR_I2C3SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM1SEL_SHIFT (18) -#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM1SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM1SEL_SHIFT) #define STM32_RCC_CCIPR_LPTIM2SEL_SHIFT (20) -#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) +#define STM32_RCC_CCIPR_LPTIM2SEL_MASK (3 << STM32_RCC_CCIPR_LPTIM2SEL_SHIFT) #define STM32_RCC_CCIPR_SAI1SEL_SHIFT (22) -#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI1SEL_MASK (3 << STM32_RCC_CCIPR_SAI1SEL_SHIFT) #define STM32_RCC_CCIPR_SAI2SEL_SHIFT (24) -#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) +#define STM32_RCC_CCIPR_SAI2SEL_MASK (3 << STM32_RCC_CCIPR_SAI2SEL_SHIFT) #define STM32_RCC_CCIPR_CLK48SEL_SHIFT (26) -#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) +#define STM32_RCC_CCIPR_CLK48SEL_MASK (3 << STM32_RCC_CCIPR_CLK48SEL_SHIFT) #define STM32_RCC_CCIPR_ADCSEL_SHIFT (28) -#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) +#define STM32_RCC_CCIPR_ADCSEL_MASK (3 << STM32_RCC_CCIPR_ADCSEL_SHIFT) #define STM32_RCC_CCIPR_SWPMI1SEL_SHIFT (30) -#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) +#define STM32_RCC_CCIPR_SWPMI1SEL_MASK BIT(STM32_RCC_CCIPR_SWPMI1SEL_SHIFT) #define STM32_RCC_CCIPR_DFSDM1SEL_SHIFT (31) -#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) +#define STM32_RCC_CCIPR_DFSDM1SEL_MASK BIT(STM32_RCC_CCIPR_DFSDM1SEL_SHIFT) /* Possible clock sources for each peripheral */ -#define STM32_RCC_CCIPR_UART_PCLK 0 -#define STM32_RCC_CCIPR_UART_SYSCLK 1 -#define STM32_RCC_CCIPR_UART_HSI16 2 -#define STM32_RCC_CCIPR_UART_LSE 3 - -#define STM32_RCC_CCIPR_I2C_PCLK 0 -#define STM32_RCC_CCIPR_I2C_SYSCLK 1 -#define STM32_RCC_CCIPR_I2C_HSI16 2 - -#define STM32_RCC_CCIPR_LPTIM_PCLK 0 -#define STM32_RCC_CCIPR_LPTIM_LSI 1 -#define STM32_RCC_CCIPR_LPTIM_HSI16 2 -#define STM32_RCC_CCIPR_LPTIM_LSE 3 - -#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 -#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 -#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 -#define STM32_RCC_CCIPR_SAI_EXTCLK 3 - -#define STM32_RCC_CCIPR_CLK48_NONE 0 -#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 -#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 -#define STM32_RCC_CCIPR_CLK48_MSI 3 - -#define STM32_RCC_CCIPR_ADC_NONE 0 -#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 -#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 -#define STM32_RCC_CCIPR_ADC_SYSCLK 3 - -#define STM32_RCC_CCIPR_SWPMI_PCLK 0 -#define STM32_RCC_CCIPR_SWPMI_HSI16 1 - -#define STM32_RCC_CCIPR_DFSDM_PCLK 0 -#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 - - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CCIPR_UART_PCLK 0 +#define STM32_RCC_CCIPR_UART_SYSCLK 1 +#define STM32_RCC_CCIPR_UART_HSI16 2 +#define STM32_RCC_CCIPR_UART_LSE 3 + +#define STM32_RCC_CCIPR_I2C_PCLK 0 +#define STM32_RCC_CCIPR_I2C_SYSCLK 1 +#define STM32_RCC_CCIPR_I2C_HSI16 2 + +#define STM32_RCC_CCIPR_LPTIM_PCLK 0 +#define STM32_RCC_CCIPR_LPTIM_LSI 1 +#define STM32_RCC_CCIPR_LPTIM_HSI16 2 +#define STM32_RCC_CCIPR_LPTIM_LSE 3 + +#define STM32_RCC_CCIPR_SAI_PLLSAI1CLK 0 +#define STM32_RCC_CCIPR_SAI_PLLSAI2CLK 1 +#define STM32_RCC_CCIPR_SAI_PLLSAI3CLK 2 +#define STM32_RCC_CCIPR_SAI_EXTCLK 3 + +#define STM32_RCC_CCIPR_CLK48_NONE 0 +#define STM32_RCC_CCIPR_CLK48_PLL48M2CLK 1 +#define STM32_RCC_CCIPR_CLK48_PLL48M1CLK 2 +#define STM32_RCC_CCIPR_CLK48_MSI 3 + +#define STM32_RCC_CCIPR_ADC_NONE 0 +#define STM32_RCC_CCIPR_ADC_PLLADC1CLK 1 +#define STM32_RCC_CCIPR_ADC_PLLADC2CLK 2 +#define STM32_RCC_CCIPR_ADC_SYSCLK 3 + +#define STM32_RCC_CCIPR_SWPMI_PCLK 0 +#define STM32_RCC_CCIPR_SWPMI_HSI16 1 + +#define STM32_RCC_CCIPR_DFSDM_PCLK 0 +#define STM32_RCC_CCIPR_DFSDM_SYSCLK 1 + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) #define STM32_RCC_PLLSAI1CFGR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_RESERVED REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_RESERVED0 REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_RESERVED1 REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_RESERVED2 REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_RESERVED3 REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_RESERVED4 REG32(STM32_RCC_BASE + 0x64) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_RESERVED5 REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_RESERVED6 REG32(STM32_RCC_BASE + 0x84) +#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_RESERVED7 REG32(STM32_RCC_BASE + 0x8C) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) #define STM32_RCC_PLLSAI1_SUPPORT #define STM32_RCC_PLLP_SUPPORT @@ -522,236 +520,236 @@ #define STM32_RCC_PLLP_DIV_2_31_SUPPORT #define STM32_RCC_PLLSAI1P_DIV_2_31_SUPPORT -#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 /******************** BIT DEFINITION FOR STM32_RCC_CR REGISTER **************/ -#define STM32_RCC_CR_MSION_POS 0U -#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) -#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK -#define STM32_RCC_CR_MSIRDY_POS 1U -#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) -#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK -#define STM32_RCC_CR_MSIPLLEN_POS 2U -#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) -#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK -#define STM32_RCC_CR_MSIRGSEL_POS 3U -#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) -#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK +#define STM32_RCC_CR_MSION_POS 0U +#define STM32_RCC_CR_MSION_MSK (0x1UL << STM32_RCC_CR_MSION_POS) +#define STM32_RCC_CR_MSION STM32_RCC_CR_MSION_MSK +#define STM32_RCC_CR_MSIRDY_POS 1U +#define STM32_RCC_CR_MSIRDY_MSK (0x1UL << STM32_RCC_CR_MSIRDY_POS) +#define STM32_RCC_CR_MSIRDY STM32_RCC_CR_MSIRDY_MSK +#define STM32_RCC_CR_MSIPLLEN_POS 2U +#define STM32_RCC_CR_MSIPLLEN_MSK (0x1UL << STM32_RCC_CR_MSIPLLEN_POS) +#define STM32_RCC_CR_MSIPLLEN STM32_RCC_CR_MSIPLLEN_MSK +#define STM32_RCC_CR_MSIRGSEL_POS 3U +#define STM32_RCC_CR_MSIRGSEL_MSK (0x1UL << STM32_RCC_CR_MSIRGSEL_POS) +#define STM32_RCC_CR_MSIRGSEL STM32_RCC_CR_MSIRGSEL_MSK /*!< MSIRANGE CONFIGURATION : 12 FREQUENCY RANGES AVAILABLE */ -#define STM32_RCC_CR_MSIRANGE_POS 4U -#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK -#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) -#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) - -#define STM32_RCC_CR_HSION_POS 8U -#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) -#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK -#define STM32_RCC_CR_HSIKERON_POS 9U -#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) -#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK -#define STM32_RCC_CR_HSIRDY_POS 10U -#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) -#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK -#define STM32_RCC_CR_HSIASFS_POS 11U -#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) -#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK - -#define STM32_RCC_CR_HSEON_POS 16U -#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) -#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK -#define STM32_RCC_CR_HSERDY_POS 17U -#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) -#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK -#define STM32_RCC_CR_HSEBYP_POS 18U -#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) -#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK -#define STM32_RCC_CR_CSSON_POS 19U -#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) -#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK - -#define STM32_RCC_CR_PLLON_POS 24U -#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) -#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK -#define STM32_RCC_CR_PLLRDY_POS 25U -#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) -#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK -#define STM32_RCC_CR_PLLSAI1ON_POS 26U -#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) -#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK -#define STM32_RCC_CR_PLLSAI1RDY_POS 27U -#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) -#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK +#define STM32_RCC_CR_MSIRANGE_POS 4U +#define STM32_RCC_CR_MSIRANGE_MSK (0xFUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE STM32_RCC_CR_MSIRANGE_MSK +#define STM32_RCC_CR_MSIRANGE_0 (0x0UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_1 (0x1UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_2 (0x2UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_3 (0x3UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_4 (0x4UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_5 (0x5UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_6 (0x6UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_7 (0x7UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_8 (0x8UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_9 (0x9UL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_10 (0xAUL << STM32_RCC_CR_MSIRANGE_POS) +#define STM32_RCC_CR_MSIRANGE_11 (0xBUL << STM32_RCC_CR_MSIRANGE_POS) + +#define STM32_RCC_CR_HSION_POS 8U +#define STM32_RCC_CR_HSION_MSK (0x1UL << STM32_RCC_CR_HSION_POS) +#define STM32_RCC_CR_HSION STM32_RCC_CR_HSION_MSK +#define STM32_RCC_CR_HSIKERON_POS 9U +#define STM32_RCC_CR_HSIKERON_MSK (0x1UL << STM32_RCC_CR_HSIKERON_POS) +#define STM32_RCC_CR_HSIKERON STM32_RCC_CR_HSIKERON_MSK +#define STM32_RCC_CR_HSIRDY_POS 10U +#define STM32_RCC_CR_HSIRDY_MSK (0x1UL << STM32_RCC_CR_HSIRDY_POS) +#define STM32_RCC_CR_HSIRDY STM32_RCC_CR_HSIRDY_MSK +#define STM32_RCC_CR_HSIASFS_POS 11U +#define STM32_RCC_CR_HSIASFS_MSK (0x1UL << STM32_RCC_CR_HSIASFS_POS) +#define STM32_RCC_CR_HSIASFS STM32_RCC_CR_HSIASFS_MSK + +#define STM32_RCC_CR_HSEON_POS 16U +#define STM32_RCC_CR_HSEON_MSK (0x1UL << STM32_RCC_CR_HSEON_POS) +#define STM32_RCC_CR_HSEON STM32_RCC_CR_HSEON_MSK +#define STM32_RCC_CR_HSERDY_POS 17U +#define STM32_RCC_CR_HSERDY_MSK (0x1UL << STM32_RCC_CR_HSERDY_POS) +#define STM32_RCC_CR_HSERDY STM32_RCC_CR_HSERDY_MSK +#define STM32_RCC_CR_HSEBYP_POS 18U +#define STM32_RCC_CR_HSEBYP_MSK (0x1UL << STM32_RCC_CR_HSEBYP_POS) +#define STM32_RCC_CR_HSEBYP STM32_RCC_CR_HSEBYP_MSK +#define STM32_RCC_CR_CSSON_POS 19U +#define STM32_RCC_CR_CSSON_MSK (0x1UL << STM32_RCC_CR_CSSON_POS) +#define STM32_RCC_CR_CSSON STM32_RCC_CR_CSSON_MSK + +#define STM32_RCC_CR_PLLON_POS 24U +#define STM32_RCC_CR_PLLON_MSK (0x1UL << STM32_RCC_CR_PLLON_POS) +#define STM32_RCC_CR_PLLON STM32_RCC_CR_PLLON_MSK +#define STM32_RCC_CR_PLLRDY_POS 25U +#define STM32_RCC_CR_PLLRDY_MSK (0x1UL << STM32_RCC_CR_PLLRDY_POS) +#define STM32_RCC_CR_PLLRDY STM32_RCC_CR_PLLRDY_MSK +#define STM32_RCC_CR_PLLSAI1ON_POS 26U +#define STM32_RCC_CR_PLLSAI1ON_MSK (0x1UL << STM32_RCC_CR_PLLSAI1ON_POS) +#define STM32_RCC_CR_PLLSAI1ON STM32_RCC_CR_PLLSAI1ON_MSK +#define STM32_RCC_CR_PLLSAI1RDY_POS 27U +#define STM32_RCC_CR_PLLSAI1RDY_MSK (0x1UL << STM32_RCC_CR_PLLSAI1RDY_POS) +#define STM32_RCC_CR_PLLSAI1RDY STM32_RCC_CR_PLLSAI1RDY_MSK /******************** BIT DEFINITION FOR STM32_RCC_ICSCR REGISTER ***********/ /*!< MSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_MSICAL_POS 0U -#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK -#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) -#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_POS 0U +#define STM32_RCC_ICSCR_MSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL STM32_RCC_ICSCR_MSICAL_MSK +#define STM32_RCC_ICSCR_MSICAL_0 (0x01UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_1 (0x02UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_2 (0x04UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_3 (0x08UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_4 (0x10UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_5 (0x20UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_6 (0x40UL << STM32_RCC_ICSCR_MSICAL_POS) +#define STM32_RCC_ICSCR_MSICAL_7 (0x80UL << STM32_RCC_ICSCR_MSICAL_POS) /*!< MSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_MSITRIM_POS 8U -#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK -#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) -#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_POS 8U +#define STM32_RCC_ICSCR_MSITRIM_MSK (0xFFUL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM STM32_RCC_ICSCR_MSITRIM_MSK +#define STM32_RCC_ICSCR_MSITRIM_0 (0x01UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_1 (0x02UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_2 (0x04UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_3 (0x08UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_4 (0x10UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_5 (0x20UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_6 (0x40UL << STM32_RCC_ICSCR_MSITRIM_POS) +#define STM32_RCC_ICSCR_MSITRIM_7 (0x80UL << STM32_RCC_ICSCR_MSITRIM_POS) /*!< HSICAL CONFIGURATION */ -#define STM32_RCC_ICSCR_HSICAL_POS 16U -#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK -#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) -#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_POS 16U +#define STM32_RCC_ICSCR_HSICAL_MSK (0xFFUL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL STM32_RCC_ICSCR_HSICAL_MSK +#define STM32_RCC_ICSCR_HSICAL_0 (0x01UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_1 (0x02UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_2 (0x04UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_3 (0x08UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_4 (0x10UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_5 (0x20UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_6 (0x40UL << STM32_RCC_ICSCR_HSICAL_POS) +#define STM32_RCC_ICSCR_HSICAL_7 (0x80UL << STM32_RCC_ICSCR_HSICAL_POS) /*!< HSITRIM CONFIGURATION */ -#define STM32_RCC_ICSCR_HSITRIM_POS 24U -#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK -#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) -#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_POS 24U +#define STM32_RCC_ICSCR_HSITRIM_MSK (0x1FUL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM STM32_RCC_ICSCR_HSITRIM_MSK +#define STM32_RCC_ICSCR_HSITRIM_0 (0x01UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_1 (0x02UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_2 (0x04UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_3 (0x08UL << STM32_RCC_ICSCR_HSITRIM_POS) +#define STM32_RCC_ICSCR_HSITRIM_4 (0x10UL << STM32_RCC_ICSCR_HSITRIM_POS) /**************** BIT DEFINITION FOR STM32_RCC_CFGR REGISTER **************/ /*!< SW CONFIGURATION */ -#define STM32_RCC_CFGR_SW_POS 0U -#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK -#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_POS 0U +#define STM32_RCC_CFGR_SW_MSK (0x3UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW STM32_RCC_CFGR_SW_MSK +#define STM32_RCC_CFGR_SW_0 (0x1UL << STM32_RCC_CFGR_SW_POS) +#define STM32_RCC_CFGR_SW_1 (0x2UL << STM32_RCC_CFGR_SW_POS) -#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) -#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) -#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) +#define STM32_RCC_CFGR_SW_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SW_HSI (0x00000001UL) +#define STM32_RCC_CFGR_SW_HSE (0x00000002UL) +#define STM32_RCC_CFGR_SW_PLL (0x00000003UL) /*!< SWS CONFIGURATION */ -#define STM32_RCC_CFGR_SWS_POS 2U -#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK -#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_POS 2U +#define STM32_RCC_CFGR_SWS_MSK (0x3UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS STM32_RCC_CFGR_SWS_MSK +#define STM32_RCC_CFGR_SWS_0 (0x1UL << STM32_RCC_CFGR_SWS_POS) +#define STM32_RCC_CFGR_SWS_1 (0x2UL << STM32_RCC_CFGR_SWS_POS) -#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) -#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) -#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) -#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) +#define STM32_RCC_CFGR_SWS_MSI (0x00000000UL) +#define STM32_RCC_CFGR_SWS_HSI (0x00000004UL) +#define STM32_RCC_CFGR_SWS_HSE (0x00000008UL) +#define STM32_RCC_CFGR_SWS_PLL (0x0000000CUL) /*!< HPRE CONFIGURATION */ -#define STM32_RCC_CFGR_HPRE_POS 4U -#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK -#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) -#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) - -#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) -#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) -#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) -#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) -#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) -#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) -#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) -#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) +#define STM32_RCC_CFGR_HPRE_POS 4U +#define STM32_RCC_CFGR_HPRE_MSK (0xFUL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE STM32_RCC_CFGR_HPRE_MSK +#define STM32_RCC_CFGR_HPRE_0 (0x1UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_1 (0x2UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_2 (0x4UL << STM32_RCC_CFGR_HPRE_POS) +#define STM32_RCC_CFGR_HPRE_3 (0x8UL << STM32_RCC_CFGR_HPRE_POS) + +#define STM32_RCC_CFGR_HPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_HPRE_DIV2 (0x00000080UL) +#define STM32_RCC_CFGR_HPRE_DIV4 (0x00000090UL) +#define STM32_RCC_CFGR_HPRE_DIV8 (0x000000A0UL) +#define STM32_RCC_CFGR_HPRE_DIV16 (0x000000B0UL) +#define STM32_RCC_CFGR_HPRE_DIV64 (0x000000C0UL) +#define STM32_RCC_CFGR_HPRE_DIV128 (0x000000D0UL) +#define STM32_RCC_CFGR_HPRE_DIV256 (0x000000E0UL) +#define STM32_RCC_CFGR_HPRE_DIV512 (0x000000F0UL) /*!< PPRE1 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE1_POS 8U -#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK -#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) -#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) - -#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) -#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) -#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) -#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) +#define STM32_RCC_CFGR_PPRE1_POS 8U +#define STM32_RCC_CFGR_PPRE1_MSK (0x7UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1 STM32_RCC_CFGR_PPRE1_MSK +#define STM32_RCC_CFGR_PPRE1_0 (0x1UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_1 (0x2UL << STM32_RCC_CFGR_PPRE1_POS) +#define STM32_RCC_CFGR_PPRE1_2 (0x4UL << STM32_RCC_CFGR_PPRE1_POS) + +#define STM32_RCC_CFGR_PPRE1_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE1_DIV2 (0x00000400UL) +#define STM32_RCC_CFGR_PPRE1_DIV4 (0x00000500UL) +#define STM32_RCC_CFGR_PPRE1_DIV8 (0x00000600UL) +#define STM32_RCC_CFGR_PPRE1_DIV16 (0x00000700UL) /*!< PPRE2 CONFIGURATION */ -#define STM32_RCC_CFGR_PPRE2_POS 11U -#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK -#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) -#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) - -#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) -#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) -#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) -#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) - -#define STM32_RCC_CFGR_STOPWUCK_POS 15U -#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) -#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK +#define STM32_RCC_CFGR_PPRE2_POS 11U +#define STM32_RCC_CFGR_PPRE2_MSK (0x7UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2 STM32_RCC_CFGR_PPRE2_MSK +#define STM32_RCC_CFGR_PPRE2_0 (0x1UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_1 (0x2UL << STM32_RCC_CFGR_PPRE2_POS) +#define STM32_RCC_CFGR_PPRE2_2 (0x4UL << STM32_RCC_CFGR_PPRE2_POS) + +#define STM32_RCC_CFGR_PPRE2_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_PPRE2_DIV2 (0x00002000UL) +#define STM32_RCC_CFGR_PPRE2_DIV4 (0x00002800UL) +#define STM32_RCC_CFGR_PPRE2_DIV8 (0x00003000UL) +#define STM32_RCC_CFGR_PPRE2_DIV16 (0x00003800UL) + +#define STM32_RCC_CFGR_STOPWUCK_POS 15U +#define STM32_RCC_CFGR_STOPWUCK_MSK (0x1UL << STM32_RCC_CFGR_STOPWUCK_POS) +#define STM32_RCC_CFGR_STOPWUCK STM32_RCC_CFGR_STOPWUCK_MSK /*!< MCOSEL CONFIGURATION */ -#define STM32_RCC_CFGR_MCOSEL_POS 24U -#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK -#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) -#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) - -#define STM32_RCC_CFGR_MCOPRE_POS 28U -#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK -#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) -#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) - -#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) -#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) +#define STM32_RCC_CFGR_MCOSEL_POS 24U +#define STM32_RCC_CFGR_MCOSEL_MSK (0xFUL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL STM32_RCC_CFGR_MCOSEL_MSK +#define STM32_RCC_CFGR_MCOSEL_0 (0x1UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_1 (0x2UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_2 (0x4UL << STM32_RCC_CFGR_MCOSEL_POS) +#define STM32_RCC_CFGR_MCOSEL_3 (0x8UL << STM32_RCC_CFGR_MCOSEL_POS) + +#define STM32_RCC_CFGR_MCOPRE_POS 28U +#define STM32_RCC_CFGR_MCOPRE_MSK (0x7UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE STM32_RCC_CFGR_MCOPRE_MSK +#define STM32_RCC_CFGR_MCOPRE_0 (0x1UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_1 (0x2UL << STM32_RCC_CFGR_MCOPRE_POS) +#define STM32_RCC_CFGR_MCOPRE_2 (0x4UL << STM32_RCC_CFGR_MCOPRE_POS) + +#define STM32_RCC_CFGR_MCOPRE_DIV1 (0x00000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV2 (0x10000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV4 (0x20000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV8 (0x30000000UL) +#define STM32_RCC_CFGR_MCOPRE_DIV16 (0x40000000UL) /* LEGACY ALIASES */ -#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE -#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 -#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 -#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 -#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 -#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 +#define STM32_RCC_CFGR_MCO_PRE STM32_RCC_CFGR_MCOPRE +#define STM32_RCC_CFGR_MCO_PRE_1 STM32_RCC_CFGR_MCOPRE_DIV1 +#define STM32_RCC_CFGR_MCO_PRE_2 STM32_RCC_CFGR_MCOPRE_DIV2 +#define STM32_RCC_CFGR_MCO_PRE_4 STM32_RCC_CFGR_MCOPRE_DIV4 +#define STM32_RCC_CFGR_MCO_PRE_8 STM32_RCC_CFGR_MCOPRE_DIV8 +#define STM32_RCC_CFGR_MCO_PRE_16 STM32_RCC_CFGR_MCOPRE_DIV16 /**************** BIT DEFINITION FOR STM32_RCC_PLLCFGR REGISTER ***********/ -#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U +#define STM32_RCC_PLLCFGR_PLLSRC_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_POS) #define STM32_RCC_PLLCFGR_PLLSRC STM32_RCC_PLLCFGR_PLLSRC_MSK @@ -766,59 +764,59 @@ #define STM32_RCC_PLLCFGR_PLLSRC_HSE_POS 0U #define STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK \ (0x3UL << STM32_RCC_PLLCFGR_PLLSRC_HSE_POS) -#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK - -#define STM32_RCC_PLLCFGR_PLLM_POS 4U -#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK -#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) -#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) - -#define STM32_RCC_PLLCFGR_PLLN_POS 8U -#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK -#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) -#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) - -#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U -#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) -#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK -#define STM32_RCC_PLLCFGR_PLLP_POS 17U -#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) -#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK -#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U -#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) -#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK - -#define STM32_RCC_PLLCFGR_PLLQ_POS 21U -#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK -#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) -#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) - -#define STM32_RCC_PLLCFGR_PLLREN_POS 24U -#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) -#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK -#define STM32_RCC_PLLCFGR_PLLR_POS 25U -#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK -#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) -#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) - -#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U -#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK -#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) -#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLSRC_HSE STM32_RCC_PLLCFGR_PLLSRC_HSE_MSK + +#define STM32_RCC_PLLCFGR_PLLM_POS 4U +#define STM32_RCC_PLLCFGR_PLLM_MSK (0x7UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM STM32_RCC_PLLCFGR_PLLM_MSK +#define STM32_RCC_PLLCFGR_PLLM_0 (0x1UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_1 (0x2UL << STM32_RCC_PLLCFGR_PLLM_POS) +#define STM32_RCC_PLLCFGR_PLLM_2 (0x4UL << STM32_RCC_PLLCFGR_PLLM_POS) + +#define STM32_RCC_PLLCFGR_PLLN_POS 8U +#define STM32_RCC_PLLCFGR_PLLN_MSK (0x7FUL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN STM32_RCC_PLLCFGR_PLLN_MSK +#define STM32_RCC_PLLCFGR_PLLN_0 (0x01UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_1 (0x02UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_2 (0x04UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_3 (0x08UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_4 (0x10UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_5 (0x20UL << STM32_RCC_PLLCFGR_PLLN_POS) +#define STM32_RCC_PLLCFGR_PLLN_6 (0x40UL << STM32_RCC_PLLCFGR_PLLN_POS) + +#define STM32_RCC_PLLCFGR_PLLPEN_POS 16U +#define STM32_RCC_PLLCFGR_PLLPEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLPEN_POS) +#define STM32_RCC_PLLCFGR_PLLPEN STM32_RCC_PLLCFGR_PLLPEN_MSK +#define STM32_RCC_PLLCFGR_PLLP_POS 17U +#define STM32_RCC_PLLCFGR_PLLP_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLP_POS) +#define STM32_RCC_PLLCFGR_PLLP STM32_RCC_PLLCFGR_PLLP_MSK +#define STM32_RCC_PLLCFGR_PLLQEN_POS 20U +#define STM32_RCC_PLLCFGR_PLLQEN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLQEN_POS) +#define STM32_RCC_PLLCFGR_PLLQEN STM32_RCC_PLLCFGR_PLLQEN_MSK + +#define STM32_RCC_PLLCFGR_PLLQ_POS 21U +#define STM32_RCC_PLLCFGR_PLLQ_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ STM32_RCC_PLLCFGR_PLLQ_MSK +#define STM32_RCC_PLLCFGR_PLLQ_0 (0x1UL << STM32_RCC_PLLCFGR_PLLQ_POS) +#define STM32_RCC_PLLCFGR_PLLQ_1 (0x2UL << STM32_RCC_PLLCFGR_PLLQ_POS) + +#define STM32_RCC_PLLCFGR_PLLREN_POS 24U +#define STM32_RCC_PLLCFGR_PLLREN_MSK (0x1UL << STM32_RCC_PLLCFGR_PLLREN_POS) +#define STM32_RCC_PLLCFGR_PLLREN STM32_RCC_PLLCFGR_PLLREN_MSK +#define STM32_RCC_PLLCFGR_PLLR_POS 25U +#define STM32_RCC_PLLCFGR_PLLR_MSK (0x3UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR STM32_RCC_PLLCFGR_PLLR_MSK +#define STM32_RCC_PLLCFGR_PLLR_0 (0x1UL << STM32_RCC_PLLCFGR_PLLR_POS) +#define STM32_RCC_PLLCFGR_PLLR_1 (0x2UL << STM32_RCC_PLLCFGR_PLLR_POS) + +#define STM32_RCC_PLLCFGR_PLLPDIV_POS 27U +#define STM32_RCC_PLLCFGR_PLLPDIV_MSK (0x1FUL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV STM32_RCC_PLLCFGR_PLLPDIV_MSK +#define STM32_RCC_PLLCFGR_PLLPDIV_0 (0x01UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_1 (0x02UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_2 (0x04UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_3 (0x08UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) +#define STM32_RCC_PLLCFGR_PLLPDIV_4 (0x10UL << STM32_RCC_PLLCFGR_PLLPDIV_POS) /**************** BIT DEFINITION FOR STM32_RCC_PLLSAI1CFGR REGISTER ********/ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS 8U @@ -840,7 +838,7 @@ #define STM32_RCC_PLLSAI1CFGR_PLLSAI1N_6 \ (0x40UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1N_POS) -#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U +#define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS 16U #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK \ (0x1UL << STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_POS) #define STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN STM32_RCC_PLLSAI1CFGR_PLLSAI1PEN_MSK @@ -1701,102 +1699,100 @@ #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SYSCFGEN BIT(0) -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_SYSCFGEN BIT(0) +#define STM32_RCC_PB2_USART1 BIT(14) -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB2_GPIOA BIT(0) -#define STM32_RCC_HB2_GPIOB BIT(1) -#define STM32_RCC_HB2_GPIOC BIT(2) -#define STM32_RCC_HB2_GPIOD BIT(3) -#define STM32_RCC_HB2_GPIOE BIT(4) -#define STM32_RCC_HB2_GPIOH BIT(7) -#define STM32_RCC_HB2_ADC1 BIT(13) +#define STM32_RCC_HB2_GPIOA BIT(0) +#define STM32_RCC_HB2_GPIOB BIT(1) +#define STM32_RCC_HB2_GPIOC BIT(2) +#define STM32_RCC_HB2_GPIOD BIT(3) +#define STM32_RCC_HB2_GPIOE BIT(4) +#define STM32_RCC_HB2_GPIOH BIT(7) +#define STM32_RCC_HB2_ADC1 BIT(13) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ -#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xff000000 -#define RESET_CAUSE_RMVF BIT(23) +#define STM32_RCC_RESET_CAUSE STM32_RCC_CSR +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xff000000 +#define RESET_CAUSE_RMVF BIT(23) /* Power cause in PWR CSR register */ -#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR -#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF BIT(8) -#define RESET_CAUSE_SBF_CLR BIT(8) +#define STM32_PWR_RESET_CAUSE STM32_PWR_CSR +#define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR +#define RESET_CAUSE_SBF BIT(8) +#define RESET_CAUSE_SBF_CLR BIT(8) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_WUTE BIT(10) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_CR_WUTIE BIT(14) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_WUTWF BIT(2) -#define STM32_RTC_ISR_INITS BIT(4) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_ISR_WUTF BIT(9) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_WUTE BIT(10) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_WUTIE BIT(14) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_WUTWF BIT(2) +#define STM32_RTC_ISR_INITS BIT(4) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_WUTF BIT(9) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) #define STM32_RTC_CLEAR_FLAG(x) \ - (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ - (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 - -#define RTC_TR_PM_POS 22U -#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) -#define RTC_TR_PM RTC_TR_PM_MSK -#define RTC_TR_HT_POS 20U -#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) -#define RTC_TR_HT RTC_TR_HT_MSK -#define RTC_TR_HU_POS 16U -#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) -#define RTC_TR_HU RTC_TR_HU_MSK -#define RTC_TR_MNT_POS 12U -#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) -#define RTC_TR_MNT RTC_TR_MNT_MSK -#define RTC_TR_MNU_POS 8U -#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) -#define RTC_TR_MNU RTC_TR_MNU_MSK -#define RTC_TR_ST_POS 4U -#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) -#define RTC_TR_ST RTC_TR_ST_MSK -#define RTC_TR_SU_POS 0U -#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) -#define RTC_TR_SU RTC_TR_SU_MSK - - + (STM32_RTC_ISR = (~((x) | STM32_RTC_ISR_INIT) | \ + (STM32_RTC_ISR & STM32_RTC_ISR_INIT))) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 + +#define RTC_TR_PM_POS 22U +#define RTC_TR_PM_MSK (0x1UL << RTC_TR_PM_POS) +#define RTC_TR_PM RTC_TR_PM_MSK +#define RTC_TR_HT_POS 20U +#define RTC_TR_HT_MSK (0x3UL << RTC_TR_HT_POS) +#define RTC_TR_HT RTC_TR_HT_MSK +#define RTC_TR_HU_POS 16U +#define RTC_TR_HU_MSK (0xFUL << RTC_TR_HU_POS) +#define RTC_TR_HU RTC_TR_HU_MSK +#define RTC_TR_MNT_POS 12U +#define RTC_TR_MNT_MSK (0x7UL << RTC_TR_MNT_POS) +#define RTC_TR_MNT RTC_TR_MNT_MSK +#define RTC_TR_MNU_POS 8U +#define RTC_TR_MNU_MSK (0xFUL << RTC_TR_MNU_POS) +#define RTC_TR_MNU RTC_TR_MNU_MSK +#define RTC_TR_ST_POS 4U +#define RTC_TR_ST_MSK (0x7UL << RTC_TR_ST_POS) +#define RTC_TR_ST RTC_TR_ST_MSK +#define RTC_TR_SU_POS 0U +#define RTC_TR_SU_MSK (0xFUL << RTC_TR_SU_POS) +#define RTC_TR_SU RTC_TR_SU_MSK /* --- SPI --- */ @@ -1813,8 +1809,8 @@ struct stm32_spi_regs { unsigned int crcpr; unsigned int rxcrcr; unsigned int txcrcr; - unsigned int i2scfgr; /* STM32L only */ - unsigned int i2spr; /* STM32L only */ + unsigned int i2scfgr; /* STM32L only */ + unsigned int i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -1824,152 +1820,152 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_ERR_MASK (0xc3fa) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0xff) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) -#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) -#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) -#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) -#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) -#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_ERR_MASK (0xc3fa) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0xff) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0xff) +#define STM32_FLASH_ECCR REG32(STM32_FLASH_REGS_BASE + 0x18) +#define STM32_FLASH_OPTR REG32(STM32_FLASH_REGS_BASE + 0x20) +#define STM32_FLASH_PCROP1SR REG32(STM32_FLASH_REGS_BASE + 0x24) +#define STM32_FLASH_PCROP1ER REG32(STM32_FLASH_REGS_BASE + 0x28) +#define STM32_FLASH_WRP1AR REG32(STM32_FLASH_REGS_BASE + 0x2C) +#define STM32_FLASH_WRP1BR REG32(STM32_FLASH_REGS_BASE + 0x30) /* Minimum number of bytes that can be written to flash */ -#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE +#define STM32_FLASH_MIN_WRITE_SIZE CONFIG_FLASH_WRITE_SIZE -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) +#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BASE + 0x18) +#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BASE + 0x20) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) -#define EXTI_RTC_ALR_EVENT BIT(18) +#define EXTI_RTC_ALR_EVENT BIT(18) /* --- ADC --- */ -#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC1_ISR_ADRDY BIT(0) -#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC1_IER_AWDIE BIT(7) -#define STM32_ADC1_IER_OVRIE BIT(4) -#define STM32_ADC1_IER_EOSEQIE BIT(3) -#define STM32_ADC1_IER_EOCIE BIT(2) -#define STM32_ADC1_IER_EOSMPIE BIT(1) -#define STM32_ADC1_IER_ADRDYIE BIT(0) - -#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC1_CR_ADEN BIT(0) -#define STM32_ADC1_CR_ADDIS BIT(1) -#define STM32_ADC1_CR_ADSTP BIT(4) -#define STM32_ADC1_CR_ADVREGEN BIT(28) -#define STM32_ADC1_CR_DEEPPWD BIT(29) -#define STM32_ADC1_CR_ADCAL BIT(31) -#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC1_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC1_ISR_ADRDY BIT(0) +#define STM32_ADC1_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC1_IER_AWDIE BIT(7) +#define STM32_ADC1_IER_OVRIE BIT(4) +#define STM32_ADC1_IER_EOSEQIE BIT(3) +#define STM32_ADC1_IER_EOCIE BIT(2) +#define STM32_ADC1_IER_EOSMPIE BIT(1) +#define STM32_ADC1_IER_ADRDYIE BIT(0) + +#define STM32_ADC1_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC1_CR_ADEN BIT(0) +#define STM32_ADC1_CR_ADDIS BIT(1) +#define STM32_ADC1_CR_ADSTP BIT(4) +#define STM32_ADC1_CR_ADVREGEN BIT(28) +#define STM32_ADC1_CR_DEEPPWD BIT(29) +#define STM32_ADC1_CR_ADCAL BIT(31) +#define STM32_ADC1_CFGR REG32(STM32_ADC1_BASE + 0x0C) /* Analog watchdog channel selection */ -#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) -#define STM32_ADC1_CFGR_AWDEN BIT(23) -#define STM32_ADC1_CFGR_AWDSGL BIT(22) -#define STM32_ADC1_CFGR_AUTDLY BIT(14) +#define STM32_ADC1_CFGR_AWDCH_MASK (0x1f << 26) +#define STM32_ADC1_CFGR_AWDEN BIT(23) +#define STM32_ADC1_CFGR_AWDSGL BIT(22) +#define STM32_ADC1_CFGR_AUTDLY BIT(14) /* Selects single vs continuous */ -#define STM32_ADC1_CFGR_CONT BIT(13) +#define STM32_ADC1_CFGR_CONT BIT(13) /* Selects ADC_DR overwrite vs preserve */ -#define STM32_ADC1_CFGR_OVRMOD BIT(12) +#define STM32_ADC1_CFGR_OVRMOD BIT(12) /* External trigger polarity selection */ -#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) -#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) -#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) -#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) -#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) -#define STM32_ADC1_CFGR_ALIGN BIT(5) +#define STM32_ADC1_CFGR_EXTEN_DIS (0 << 10) +#define STM32_ADC1_CFGR_EXTEN_RISE (1 << 10) +#define STM32_ADC1_CFGR_EXTEN_FALL (2 << 10) +#define STM32_ADC1_CFGR_EXTEN_BOTH (3 << 10) +#define STM32_ADC1_CFGR_EXTEN_MASK (3 << 10) +#define STM32_ADC1_CFGR_ALIGN BIT(5) /* External trigger selection */ -#define STM32_ADC1_CFGR_TRG0 (0 << 6) -#define STM32_ADC1_CFGR_TRG1 (1 << 6) -#define STM32_ADC1_CFGR_TRG2 (2 << 6) -#define STM32_ADC1_CFGR_TRG3 (3 << 6) -#define STM32_ADC1_CFGR_TRG4 (4 << 6) -#define STM32_ADC1_CFGR_TRG5 (5 << 6) -#define STM32_ADC1_CFGR_TRG6 (6 << 6) -#define STM32_ADC1_CFGR_TRG7 (7 << 6) -#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) +#define STM32_ADC1_CFGR_TRG0 (0 << 6) +#define STM32_ADC1_CFGR_TRG1 (1 << 6) +#define STM32_ADC1_CFGR_TRG2 (2 << 6) +#define STM32_ADC1_CFGR_TRG3 (3 << 6) +#define STM32_ADC1_CFGR_TRG4 (4 << 6) +#define STM32_ADC1_CFGR_TRG5 (5 << 6) +#define STM32_ADC1_CFGR_TRG6 (6 << 6) +#define STM32_ADC1_CFGR_TRG7 (7 << 6) +#define STM32_ADC1_CFGR_TRG_MASK (7 << 6) /* Selects circular vs one-shot */ -#define STM32_ADC1_CFGR_DMACFG BIT(1) -#define STM32_ADC1_CFGR_DMAEN BIT(0) -#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC1_CFGR_DMACFG BIT(1) +#define STM32_ADC1_CFGR_DMAEN BIT(0) +#define STM32_ADC1_CFGR2 REG32(STM32_ADC1_BASE + 0x10) /* Sampling time selection - 1.5 ADC cycles min, 239.5 cycles max */ -#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC1_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC1_SMPR2 REG32(STM32_ADC1_BASE + 0x18) /* Macro to convert enum stm32_adc_smpr to SMP bits of the ADC_SMPR register */ -#define STM32_ADC1_SMPR_SMP(s) ((s) - 1) -#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) -#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) -#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) -#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) -#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) +#define STM32_ADC1_SMPR_SMP(s) ((s)-1) +#define STM32_ADC1_TR REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC1_CHSELR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC1_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC1_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC1_JDR1 REG32(STM32_ADC1_BASE + 0x80) +#define STM32_ADC1_JDR2 REG32(STM32_ADC1_BASE + 0x84) +#define STM32_ADC1_JDR3 REG32(STM32_ADC1_BASE + 0x88) +#define STM32_ADC1_JDR4 REG32(STM32_ADC1_BASE + 0x8C) +#define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- DMA --- */ @@ -2021,11 +2017,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -2036,8 +2032,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -2046,68 +2042,67 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From b9ee86a64f98c802dc83efe2a26c076652ae9794 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:29:45 -0600 Subject: board/delbin/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I858cfcfc9ea89420e603c3e010f2ed6b7ee1be35 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728222 Reviewed-by: Jeremy Bettis --- board/delbin/sensors.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/board/delbin/sensors.c b/board/delbin/sensors.c index a3d5015e2b..10dcd6b7b6 100644 --- a/board/delbin/sensors.c +++ b/board/delbin/sensors.c @@ -34,22 +34,18 @@ static struct bmi_drv_data_t g_bmi260_data; static struct icm_drv_data_t g_icm426xx_data; /* Rotation matrix for the lid accelerometer */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; const mat33_fp_t base_standard_ref_icm = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)}, + { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) }, }; struct motion_sensor_t icm426xx_base_accel = { -- cgit v1.2.1 From d2333719929838c0cf7c4bfcc7522987a5aef42f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:38:33 -0600 Subject: zephyr/shim/src/motionsense_sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5e81637d1550cceb8961c0ede814ef54ec89cbe4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730897 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/motionsense_sensors.c | 239 ++++++++++++++++------------------ 1 file changed, 113 insertions(+), 126 deletions(-) diff --git a/zephyr/shim/src/motionsense_sensors.c b/zephyr/shim/src/motionsense_sensors.c index f0b76adf33..c9ab9ab85e 100644 --- a/zephyr/shim/src/motionsense_sensors.c +++ b/zephyr/shim/src/motionsense_sensors.c @@ -13,11 +13,11 @@ LOG_MODULE_REGISTER(shim_cros_motionsense_sensors); -#define SENSOR_MUTEX_NODE DT_PATH(motionsense_mutex) -#define SENSOR_MUTEX_NAME(id) DT_CAT(MUTEX_, id) +#define SENSOR_MUTEX_NODE DT_PATH(motionsense_mutex) +#define SENSOR_MUTEX_NAME(id) DT_CAT(MUTEX_, id) #if DT_NODE_EXISTS(SENSOR_MUTEX_NODE) -#define DECLARE_SENSOR_MUTEX(id) K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id)); +#define DECLARE_SENSOR_MUTEX(id) K_MUTEX_DEFINE(SENSOR_MUTEX_NAME(id)); /* * Declare mutex for @@ -28,18 +28,12 @@ LOG_MODULE_REGISTER(shim_cros_motionsense_sensors); DT_FOREACH_CHILD(SENSOR_MUTEX_NODE, DECLARE_SENSOR_MUTEX) #endif /* DT_NODE_EXISTS(SENSOR_MUTEX_NODE) */ -#define MAT_ITEM(i, id) FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i))) -#define DECLARE_SENSOR_ROT_REF(id) \ - const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = { \ - { \ - FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 0, 1, 2) \ - }, \ - { \ - FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 3, 4, 5) \ - }, \ - { \ - FOR_EACH_FIXED_ARG(MAT_ITEM, (,), id, 6, 7, 8) \ - }, \ +#define MAT_ITEM(i, id) FLOAT_TO_FP((int32_t)(DT_PROP_BY_IDX(id, mat33, i))) +#define DECLARE_SENSOR_ROT_REF(id) \ + const mat33_fp_t SENSOR_ROT_STD_REF_NAME(id) = { \ + { FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 0, 1, 2) }, \ + { FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 3, 4, 5) }, \ + { FOR_EACH_FIXED_ARG(MAT_ITEM, (, ), id, 6, 7, 8) }, \ }; /* @@ -59,12 +53,12 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) * * A driver data can be shared among the motion sensors. */ -#define SENSOR_DATA_NAME(id) DT_CAT(SENSOR_DAT_, id) -#define SENSOR_DATA_NODE DT_PATH(motionsense_sensor_data) +#define SENSOR_DATA_NAME(id) DT_CAT(SENSOR_DAT_, id) +#define SENSOR_DATA_NODE DT_PATH(motionsense_sensor_data) -#define SENSOR_DATA(inst, compat, create_data_macro) \ - create_data_macro(DT_INST(inst, compat), \ - SENSOR_DATA_NAME(DT_INST(inst, compat))) +#define SENSOR_DATA(inst, compat, create_data_macro) \ + create_data_macro(DT_INST(inst, compat), \ + SENSOR_DATA_NAME(DT_INST(inst, compat))) /* * CREATE_SENSOR_DATA is a helper macro that gets @@ -93,17 +87,17 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) * CREATE_SENSOR_DATA(cros_ec_drvdata_tcs3400_clear, \ * CREATE_SENSOR_DATA_TCS3400_CLEAR) */ -#define CREATE_SENSOR_DATA(compat, create_data_macro) \ - LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA, (), \ - compat, create_data_macro) +#define CREATE_SENSOR_DATA(compat, create_data_macro) \ + LISTIFY(DT_NUM_INST_STATUS_OKAY(compat), SENSOR_DATA, (), compat, \ + create_data_macro) /* * sensor_drv_list.inc is included three times in this file. This is the first * time and it is for creating sensor driver-specific data. So we ignore * CREATE_MOTION_SENSOR() that creates motion sensor at this time. */ -#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, \ - s_min_freq, s_max_freq) +#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \ + s_max_freq) /* * Here, we declare all sensor driver data. How to create the data is @@ -119,33 +113,31 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) * See motionsense-sensor-base.yaml and cros-ec,motionsense-mutex.yaml * for DT example and details. */ -#define SENSOR_MUTEX(id) \ - IF_ENABLED(DT_NODE_HAS_PROP(id, mutex), \ - (.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)),)) +#define SENSOR_MUTEX(id) \ + IF_ENABLED(DT_NODE_HAS_PROP(id, mutex), \ + (.mutex = &SENSOR_MUTEX_NAME(DT_PHANDLE(id, mutex)), )) /* * Set the interrupt pin which is referred by the phandle. */ -#define SENSOR_INT_SIGNAL(id) \ - IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \ - (.int_signal = GPIO_SIGNAL(DT_PHANDLE(id, int_signal)),)) +#define SENSOR_INT_SIGNAL(id) \ + IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \ + (.int_signal = GPIO_SIGNAL(DT_PHANDLE(id, int_signal)), )) /* * Set flags based on values defined in the node. */ -#define SENSOR_FLAGS(id) \ - .flags = 0 \ - IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \ - (|MOTIONSENSE_FLAG_INT_SIGNAL)) \ - , +#define SENSOR_FLAGS(id) \ + .flags = 0 IF_ENABLED(DT_NODE_HAS_PROP(id, int_signal), \ + (| MOTIONSENSE_FLAG_INT_SIGNAL)), /* * Get I2C port number which is referred by phandle. * See motionsense-sensor-base.yaml for DT example and details. */ -#define SENSOR_I2C_PORT(id) \ - IF_ENABLED(DT_NODE_HAS_PROP(id, port), \ - (.port = I2C_PORT(DT_PHANDLE(id, port)),)) +#define SENSOR_I2C_PORT(id) \ + IF_ENABLED(DT_NODE_HAS_PROP(id, port), \ + (.port = I2C_PORT(DT_PHANDLE(id, port)), )) /* * Get I2C or SPI address. @@ -161,75 +153,73 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) * See motionsense-sensor-base.yaml and cros-ec,motionsense-rotation-ref.yaml * for DT example and details. */ -#define SENSOR_ROT_STD_REF(id) \ - IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref), \ - (.rot_standard_ref = \ - &SENSOR_ROT_STD_REF_NAME(DT_PHANDLE(id, rot_standard_ref)),)) +#define SENSOR_ROT_STD_REF(id) \ + IF_ENABLED(DT_NODE_HAS_PROP(id, rot_standard_ref), \ + (.rot_standard_ref = &SENSOR_ROT_STD_REF_NAME( \ + DT_PHANDLE(id, rot_standard_ref)), )) /* * Get the address of driver-specific data which is referred by phandle. * See motionsense-sensor-base.yaml for DT example and details. */ -#define SENSOR_DRV_DATA(id) \ - IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data), \ - (.drv_data = &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)),)) +#define SENSOR_DRV_DATA(id) \ + IF_ENABLED(DT_NODE_HAS_PROP(id, drv_data), \ + (.drv_data = \ + &SENSOR_DATA_NAME(DT_PHANDLE(id, drv_data)), )) /* * Get odr and ec_rate for the motion sensor. * See motionsense-sensor-base.yaml and cros-ec,motionsense-sensor-config.yaml * for DT example and details. */ -#define SET_CONFIG_EC(cfg_id, cfg_suffix) \ - [SENSOR_CONFIG_##cfg_suffix] = { \ - IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr), \ - (.odr = DT_PROP(cfg_id, odr),)) \ - IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate), \ - (.ec_rate = DT_PROP(cfg_id, ec_rate),)) \ +#define SET_CONFIG_EC(cfg_id, cfg_suffix) \ + [SENSOR_CONFIG_##cfg_suffix] = { \ + IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, odr), \ + (.odr = DT_PROP(cfg_id, odr), )) \ + IF_ENABLED(DT_NODE_HAS_PROP(cfg_id, ec_rate), \ + (.ec_rate = DT_PROP(cfg_id, ec_rate), )) \ } /* Get configs */ -#define CREATE_SENSOR_CONFIG(cfgs_id) \ - .config = { \ - IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)), \ - (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP),)) \ - IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)), \ - (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0), EC_S0),)) \ - IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s3)), \ - (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s3), EC_S3),)) \ - IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s5)), \ - (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s5), EC_S5),)) \ +#define CREATE_SENSOR_CONFIG(cfgs_id) \ + .config = { \ + IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ap)), \ + (SET_CONFIG_EC(DT_CHILD(cfgs_id, ap), AP), )) \ + IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(cfgs_id, ec_s0)), \ + (SET_CONFIG_EC(DT_CHILD(cfgs_id, ec_s0), \ + EC_S0), )) \ + IF_ENABLED(DT_NODE_EXISTS( \ + DT_CHILD(cfgs_id, ec_s3)), \ + (SET_CONFIG_EC(DT_CHILD(cfgs_id, \ + ec_s3), \ + EC_S3), )) \ + IF_ENABLED(DT_NODE_EXISTS(DT_CHILD( \ + cfgs_id, ec_s5)), \ + (SET_CONFIG_EC( \ + DT_CHILD(cfgs_id, \ + ec_s5), \ + EC_S5), )) \ } -#define SENSOR_CONFIG(id) \ - IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)), \ - (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)),)) +#define SENSOR_CONFIG(id) \ + IF_ENABLED(DT_NODE_EXISTS(DT_CHILD(id, configs)), \ + (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)), )) /* Get and assign the basic information for a motion sensor */ -#define SENSOR_BASIC_INFO(id) \ - .name = DT_LABEL(id), \ - .active_mask = DT_STRING_TOKEN(id, active_mask), \ - .location = DT_STRING_TOKEN(id, location), \ - .default_range = DT_PROP(id, default_range), \ - SENSOR_I2C_SPI_ADDR_FLAGS(id) \ - SENSOR_MUTEX(id) \ - SENSOR_I2C_PORT(id) \ - SENSOR_ROT_STD_REF(id) \ - SENSOR_DRV_DATA(id) \ - SENSOR_CONFIG(id) \ - SENSOR_INT_SIGNAL(id) \ - SENSOR_FLAGS(id) +#define SENSOR_BASIC_INFO(id) \ + .name = DT_LABEL(id), .active_mask = DT_STRING_TOKEN(id, active_mask), \ + .location = DT_STRING_TOKEN(id, location), \ + .default_range = DT_PROP(id, default_range), \ + SENSOR_I2C_SPI_ADDR_FLAGS(id) SENSOR_MUTEX(id) SENSOR_I2C_PORT(id) \ + SENSOR_ROT_STD_REF(id) SENSOR_DRV_DATA(id) SENSOR_CONFIG(id) \ + SENSOR_INT_SIGNAL(id) SENSOR_FLAGS(id) /* Create motion sensor node with node ID */ -#define DO_MK_SENSOR_ENTRY( \ - id, s_chip, s_type, s_drv, s_min_freq, s_max_freq) \ - [SENSOR_ID(id)] = { \ - SENSOR_BASIC_INFO(id) \ - .chip = s_chip, \ - .type = s_type, \ - .drv = &s_drv, \ - .min_frequency = s_min_freq, \ - .max_frequency = s_max_freq \ - }, +#define DO_MK_SENSOR_ENTRY(id, s_chip, s_type, s_drv, s_min_freq, s_max_freq) \ + [SENSOR_ID(id)] = { SENSOR_BASIC_INFO(id).chip = s_chip, \ + .type = s_type, .drv = &s_drv, \ + .min_frequency = s_min_freq, \ + .max_frequency = s_max_freq }, /* Construct an entry iff the alternate_for property is missing. */ #define MK_SENSOR_ENTRY(inst, s_compat, s_chip, s_type, s_drv, s_min_freq, \ @@ -289,9 +279,9 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) * MOTIONSENSE_TYPE_LIGHT_RGB, tcs3400_rgb_drv, 0, 0) * ----------------------------------------------- */ -#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, \ - s_min_freq, s_max_freq) \ - LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY, (),\ +#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \ + s_max_freq) \ + LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ENTRY, (), \ s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq) /* @@ -309,10 +299,10 @@ struct motion_sensor_t motion_sensors[] = { * of alternate sensors that will be used at runtime. */ #undef CREATE_MOTION_SENSOR -#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \ - s_max_freq) \ - LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, (),\ - s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq) +#define CREATE_MOTION_SENSOR(s_compat, s_chip, s_type, s_drv, s_min_freq, \ + s_max_freq) \ + LISTIFY(DT_NUM_INST_STATUS_OKAY(s_compat), MK_SENSOR_ALT_ENTRY, (), \ + s_compat, s_chip, s_type, s_drv, s_min_freq, s_max_freq) /* * The list of alternate motion sensors that may be used at runtime to replace @@ -356,12 +346,11 @@ const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); * }; */ #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, als_sensors) -#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id) \ +#define ALS_SENSOR_ENTRY_WITH_COMMA(i, id) \ &motion_sensors[SENSOR_ID(DT_PHANDLE_BY_IDX(id, als_sensors, i))], -const struct motion_sensor_t *motion_als_sensors[] = { - LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors), - ALS_SENSOR_ENTRY_WITH_COMMA, (), SENSOR_INFO_NODE) -}; +const struct motion_sensor_t *motion_als_sensors[] = { LISTIFY( + DT_PROP_LEN(SENSOR_INFO_NODE, als_sensors), ALS_SENSOR_ENTRY_WITH_COMMA, + (), SENSOR_INFO_NODE) }; BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); #endif @@ -378,28 +367,27 @@ BUILD_ASSERT(ARRAY_SIZE(motion_als_sensors) == ALS_COUNT); * }; */ #if DT_NODE_HAS_PROP(SENSOR_INFO_NODE, sensor_irqs) -#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id) \ - gpio_enable_dt_interrupt( \ +#define SENSOR_GPIO_ENABLE_INTERRUPT(i, id) \ + gpio_enable_dt_interrupt( \ GPIO_INT_FROM_NODE(DT_PHANDLE_BY_IDX(id, sensor_irqs, i))); -static void sensor_enable_irqs(void) -{ +static void sensor_enable_irqs(void){ LISTIFY(DT_PROP_LEN(SENSOR_INFO_NODE, sensor_irqs), - SENSOR_GPIO_ENABLE_INTERRUPT, (), SENSOR_INFO_NODE) -} -DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT); + SENSOR_GPIO_ENABLE_INTERRUPT, (), SENSOR_INFO_NODE) +} DECLARE_HOOK(HOOK_INIT, sensor_enable_irqs, HOOK_PRIO_DEFAULT); #endif /* Handle the alternative motion sensors */ -#define CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id) \ - do { \ - if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID( \ - DT_PHANDLE(id, alternate_ssfc_indicator)))) { \ - LOG_INF("Replacing \"%s\" for \"%s\" based on SSFC", \ - motion_sensors[SENSOR_ID(DT_PHANDLE(id, \ - alternate_for))].name, \ - motion_sensors_alt[SENSOR_ID(id)].name); \ - ENABLE_ALT_MOTION_SENSOR(id); \ - } \ +#define CHECK_SSFC_AND_ENABLE_ALT_SENSOR(id) \ + do { \ + if (cros_cbi_ssfc_check_match(CBI_SSFC_VALUE_ID( \ + DT_PHANDLE(id, alternate_ssfc_indicator)))) { \ + LOG_INF("Replacing \"%s\" for \"%s\" based on SSFC", \ + motion_sensors[SENSOR_ID(DT_PHANDLE( \ + id, alternate_for))] \ + .name, \ + motion_sensors_alt[SENSOR_ID(id)].name); \ + ENABLE_ALT_MOTION_SENSOR(id); \ + } \ } while (0) #define ALT_SENSOR_CHECK_SSFC_ID(id) \ @@ -428,8 +416,7 @@ int motion_sense_probe(enum sensor_alt_id alt_idx) return res; } -void motion_sensors_check_ssfc(void) -{ +void motion_sensors_check_ssfc(void){ DT_FOREACH_CHILD(SENSOR_ALT_NODE, ALT_SENSOR_CHECK_SSFC_ID) } #endif /* DT_NODE_EXISTS(SENSOR_ALT_NODE) */ @@ -440,13 +427,13 @@ void motion_sensors_check_ssfc(void) #define DEF_MOTION_ISR_NAME(id) \ DEF_MOTION_ISR_NAME_ENUM_WITH_SUFFIX(DEF_MOTION_ISR_NAME_ENUM(id)) -#define DEF_MOTION_ISR(id) \ -void DEF_MOTION_ISR_NAME(id)(enum gpio_signal signal) \ -{ \ - __ASSERT(motion_sensors[SENSOR_ID(id)].drv->interrupt, \ - "No interrupt handler for signal: %x", signal); \ - motion_sensors[SENSOR_ID(id)].drv->interrupt(signal); \ -} +#define DEF_MOTION_ISR(id) \ + void DEF_MOTION_ISR_NAME(id)(enum gpio_signal signal) \ + { \ + __ASSERT(motion_sensors[SENSOR_ID(id)].drv->interrupt, \ + "No interrupt handler for signal: %x", signal); \ + motion_sensors[SENSOR_ID(id)].drv->interrupt(signal); \ + } #define DEF_MOTION_CHECK_ISR(id) \ COND_CODE_1(DT_NODE_HAS_PROP(id, int_signal), (DEF_MOTION_ISR(id)), ()) -- cgit v1.2.1 From 276c3d446a7e9f6e13a3a229ce32948fcc223d45 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:04:40 -0600 Subject: board/servo_v4p1/ccd_measure_sbu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1f20e589b944fc5450e782b5b500d8a60ffa129e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728929 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/ccd_measure_sbu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/board/servo_v4p1/ccd_measure_sbu.c b/board/servo_v4p1/ccd_measure_sbu.c index b9c9680cc9..75f836cfb1 100644 --- a/board/servo_v4p1/ccd_measure_sbu.c +++ b/board/servo_v4p1/ccd_measure_sbu.c @@ -11,8 +11,8 @@ #include "ioexpanders.h" #include "timer.h" -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) /* * Define voltage thresholds for SBU USB detection. @@ -20,15 +20,15 @@ * Max observed USB low across sampled systems: 666mV * Min observed USB high across sampled systems: 3026mV */ -#define GND_MAX_MV 700 -#define USB_HIGH_MV 2500 -#define SBU_DIRECT 0 -#define SBU_FLIP 1 +#define GND_MAX_MV 700 +#define USB_HIGH_MV 2500 +#define SBU_DIRECT 0 +#define SBU_FLIP 1 -#define MODE_SBU_DISCONNECT 0 -#define MODE_SBU_CONNECT 1 -#define MODE_SBU_FLIP 2 -#define MODE_SBU_OTHER 3 +#define MODE_SBU_DISCONNECT 0 +#define MODE_SBU_CONNECT 1 +#define MODE_SBU_FLIP 2 +#define MODE_SBU_OTHER 3 static void ccd_measure_sbu(void); DECLARE_DEFERRED(ccd_measure_sbu); -- cgit v1.2.1 From f0c66e97e108df477740c2bc68780a8836ac7ec6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:05 -0600 Subject: driver/gyro_l3gd20h.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iec54af10188122c3394e2995171682195e21a2fd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729988 Reviewed-by: Jeremy Bettis --- driver/gyro_l3gd20h.c | 79 +++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 43 deletions(-) diff --git a/driver/gyro_l3gd20h.c b/driver/gyro_l3gd20h.c index 77dd888542..fd480d1f99 100644 --- a/driver/gyro_l3gd20h.c +++ b/driver/gyro_l3gd20h.c @@ -17,8 +17,8 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_ACCEL, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /* * Struct for pairing an engineering value with the register value for a @@ -33,15 +33,13 @@ struct gyro_param_pair { * List of angular rate range values in +/-dps's * and their associated register values. */ -const struct gyro_param_pair dps_ranges[] = { - {245, L3GD20_DPS_SEL_245}, - {500, L3GD20_DPS_SEL_500}, - {2000, L3GD20_DPS_SEL_2000_0}, - {2000, L3GD20_DPS_SEL_2000_1} -}; +const struct gyro_param_pair dps_ranges[] = { { 245, L3GD20_DPS_SEL_245 }, + { 500, L3GD20_DPS_SEL_500 }, + { 2000, L3GD20_DPS_SEL_2000_0 }, + { 2000, L3GD20_DPS_SEL_2000_1 } }; -static inline const struct gyro_param_pair *get_range_table( - enum motionsensor_type type, int *psize) +static inline const struct gyro_param_pair * +get_range_table(enum motionsensor_type type, int *psize) { if (psize) *psize = ARRAY_SIZE(dps_ranges); @@ -50,19 +48,19 @@ static inline const struct gyro_param_pair *get_range_table( /* List of ODR values in mHz and their associated register values. */ const struct gyro_param_pair gyro_odr[] = { - {0, L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK}, - {12500, L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK}, - {25000, L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK}, - {50000, L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK}, - {50000, L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK}, - {100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK}, - {200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK}, - {400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK}, - {800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK}, + { 0, L3GD20_ODR_PD | L3GD20_LOW_ODR_MASK }, + { 12500, L3GD20_ODR_12_5HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK }, + { 25000, L3GD20_ODR_25HZ | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK }, + { 50000, L3GD20_ODR_50HZ_0 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK }, + { 50000, L3GD20_ODR_50HZ_1 | L3GD20_ODR_PD_MASK | L3GD20_LOW_ODR_MASK }, + { 100000, L3GD20_ODR_100HZ | L3GD20_ODR_PD_MASK }, + { 200000, L3GD20_ODR_200HZ | L3GD20_ODR_PD_MASK }, + { 400000, L3GD20_ODR_400HZ | L3GD20_ODR_PD_MASK }, + { 800000, L3GD20_ODR_800HZ | L3GD20_ODR_PD_MASK }, }; -static inline const struct gyro_param_pair *get_odr_table( - enum motionsensor_type type, int *psize) +static inline const struct gyro_param_pair * +get_odr_table(enum motionsensor_type type, int *psize) { if (psize) *psize = ARRAY_SIZE(gyro_odr); @@ -86,14 +84,14 @@ static inline int get_xyz_reg(enum motionsensor_type type) * outside the range of values, it returns the closest valid reg value. */ static int get_reg_val(const int eng_val, const int round_up, - const struct gyro_param_pair *pairs, const int size) + const struct gyro_param_pair *pairs, const int size) { int i; for (i = 0; i < size - 1; i++) { if (eng_val <= pairs[i].val) break; - if (eng_val < pairs[i+1].val) { + if (eng_val < pairs[i + 1].val) { if (round_up) i += 1; break; @@ -106,7 +104,8 @@ static int get_reg_val(const int eng_val, const int round_up, * @return engineering value that matches the given reg val */ static int get_engineering_val(const int reg_val, - const struct gyro_param_pair *pairs, const int size) + const struct gyro_param_pair *pairs, + const int size) { int i; for (i = 0; i < size; i++) { @@ -120,7 +119,7 @@ static int get_engineering_val(const int reg_val, * Read register from Gyrometer. */ static inline int raw_read8(const int port, const int addr, const int reg, - int *data_ptr) + int *data_ptr) { return i2c_read8(port, addr, reg, data_ptr); } @@ -129,14 +128,12 @@ static inline int raw_read8(const int port, const int addr, const int reg, * Write register from Gyrometer. */ static inline int raw_write8(const int port, const int addr, const int reg, - int data) + int data) { return i2c_write8(port, addr, reg, data); } -static int set_range(struct motion_sensor_t *s, - int range, - int rnd) +static int set_range(struct motion_sensor_t *s, int range, int rnd) { int ret, ctrl_val, range_tbl_size; uint8_t ctrl_reg, reg_val; @@ -162,8 +159,8 @@ static int set_range(struct motion_sensor_t *s, /* Now that we have set the range, update the driver's value. */ if (ret == EC_SUCCESS) - s->current_range = get_engineering_val(reg_val, ranges, - range_tbl_size); + s->current_range = + get_engineering_val(reg_val, ranges, range_tbl_size); gyro_cleanup: mutex_unlock(s->mutex); @@ -175,9 +172,7 @@ static int get_resolution(const struct motion_sensor_t *s) return L3GD20_RESOLUTION; } -static int set_data_rate(const struct motion_sensor_t *s, - int rate, - int rnd) +static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) { int ret, val, odr_tbl_size; uint8_t ctrl_reg, reg_val; @@ -199,13 +194,13 @@ static int set_data_rate(const struct motion_sensor_t *s, goto gyro_cleanup; val = (val & ~(L3GD20_ODR_MASK | L3GD20_ODR_PD_MASK)) | - (reg_val & ~L3GD20_LOW_ODR_MASK); + (reg_val & ~L3GD20_LOW_ODR_MASK); ret = raw_write8(s->port, s->addr, ctrl_reg, val); /* Now that we have set the odr, update the driver's value. */ if (ret == EC_SUCCESS) - data->base.odr = get_engineering_val(reg_val, data_rates, - odr_tbl_size); + data->base.odr = + get_engineering_val(reg_val, data_rates, odr_tbl_size); ret = raw_read8(s->port, s->addr, L3GD20_LOW_ODR, &val); if (ret != EC_SUCCESS) @@ -263,9 +258,8 @@ static int get_data_rate(const struct motion_sensor_t *s) return data->base.odr; } -static int set_offset(const struct motion_sensor_t *s, - const int16_t *offset, - int16_t temp) +static int set_offset(const struct motion_sensor_t *s, const int16_t *offset, + int16_t temp) { /* temperature is ignored */ struct l3gd20_data *data = s->drv_data; @@ -275,9 +269,8 @@ static int set_offset(const struct motion_sensor_t *s, return EC_SUCCESS; } -static int get_offset(const struct motion_sensor_t *s, - int16_t *offset, - int16_t *temp) +static int get_offset(const struct motion_sensor_t *s, int16_t *offset, + int16_t *temp) { struct l3gd20_data *data = s->drv_data; offset[X] = data->offset[X]; -- cgit v1.2.1 From c578329bacfc9ec2aea70f6f4fd6eaa7ef421bab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:44 -0600 Subject: test/motion_lid.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iaf8689d7f1676b86b14f6f488bff515fdf983f39 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730514 Reviewed-by: Jeremy Bettis --- test/motion_lid.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/test/motion_lid.c b/test/motion_lid.c index 9935767a68..a241612c12 100644 --- a/test/motion_lid.c +++ b/test/motion_lid.c @@ -48,8 +48,7 @@ static int accel_read(const struct motion_sensor_t *s, intv3_t v) return EC_SUCCESS; } -static int accel_set_range(struct motion_sensor_t *s, - const int range, +static int accel_set_range(struct motion_sensor_t *s, const int range, const int rnd) { s->current_range = range; @@ -63,9 +62,8 @@ static int accel_get_resolution(const struct motion_sensor_t *s) int test_data_rate[2] = { 0 }; -static int accel_set_data_rate(const struct motion_sensor_t *s, - const int rate, - const int rnd) +static int accel_set_data_rate(const struct motion_sensor_t *s, const int rate, + const int rnd) { test_data_rate[s - motion_sensors] = rate; return EC_SUCCESS; @@ -148,11 +146,10 @@ static void wait_for_valid_sample(void) static int test_lid_angle(void) { - - struct motion_sensor_t *base = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_BASE]; - struct motion_sensor_t *lid = &motion_sensors[ - CONFIG_LID_ANGLE_SENSOR_LID]; + struct motion_sensor_t *base = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE]; + struct motion_sensor_t *lid = + &motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID]; int lid_angle; /* We don't have TASK_CHIP so simulate init ourselves */ @@ -189,10 +186,9 @@ static int test_lid_angle(void) wait_for_valid_sample(); lid_angle = motion_lid_get_angle(); - cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d", - lid->xyz[X], lid->xyz[Y], lid->xyz[Z], - base->xyz[X], base->xyz[Y], base->xyz[Z], - lid_angle); + cprints(CC_ACCEL, "LID(%d, %d, %d)/BASE(%d, %d, %d): %d", lid->xyz[X], + lid->xyz[Y], lid->xyz[Z], base->xyz[X], base->xyz[Y], + base->xyz[Z], lid_angle); TEST_ASSERT(lid_angle == 0); /* Set lid open to 90 degrees. */ @@ -319,7 +315,6 @@ static int test_lid_angle(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); -- cgit v1.2.1 From 38a690157ebde518e7de3504c5b4a0e00562cef0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:33 -0600 Subject: zephyr/subsys/ap_pwrseq/include/power_signals.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I08c308c05199802d80ff29e7085e276c9034b360 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730929 Reviewed-by: Jeremy Bettis --- zephyr/subsys/ap_pwrseq/include/power_signals.h | 30 ++++++++++++------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/power_signals.h b/zephyr/subsys/ap_pwrseq/include/power_signals.h index 8755f1005a..8eda988468 100644 --- a/zephyr/subsys/ap_pwrseq/include/power_signals.h +++ b/zephyr/subsys/ap_pwrseq/include/power_signals.h @@ -48,10 +48,10 @@ * included if that signal source is configured in the * devicetree. */ -#define HAS_GPIO_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_gpio) -#define HAS_VW_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw) -#define HAS_EXT_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_external) -#define HAS_ADC_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_adc) +#define HAS_GPIO_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_gpio) +#define HAS_VW_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw) +#define HAS_EXT_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_external) +#define HAS_ADC_SIGNALS DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_adc) /** * @brief Definitions for AP power sequence signals. @@ -62,11 +62,9 @@ /** * @brief Generate the enum for this power signal. */ -#define PWR_SIGNAL_ENUM(id) \ - DT_STRING_UPPER_TOKEN(id, enum_name) +#define PWR_SIGNAL_ENUM(id) DT_STRING_UPPER_TOKEN(id, enum_name) -#define PWR_SIGNAL_ENUM_COMMA(id) \ - PWR_SIGNAL_ENUM(id), +#define PWR_SIGNAL_ENUM_COMMA(id) PWR_SIGNAL_ENUM(id), /** * @brief Enum of all power signals. * @@ -78,11 +76,14 @@ * must be the same as in power_signals.c */ enum power_signal { -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_SIGNAL_ENUM_COMMA) -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, PWR_SIGNAL_ENUM_COMMA) -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, PWR_SIGNAL_ENUM_COMMA) -DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, PWR_SIGNAL_ENUM_COMMA) - POWER_SIGNAL_COUNT, + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_gpio, PWR_SIGNAL_ENUM_COMMA) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_vw, + PWR_SIGNAL_ENUM_COMMA) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_external, + PWR_SIGNAL_ENUM_COMMA) + DT_FOREACH_STATUS_OKAY(intel_ap_pwrseq_adc, + PWR_SIGNAL_ENUM_COMMA) + POWER_SIGNAL_COUNT, }; #undef PWR_SIGNAL_ENUM_COMMA @@ -301,8 +302,7 @@ static inline bool power_signals_off(power_signal_mask_t want) * @return negative If the signals did not match before the timeout. */ int power_wait_mask_signals_timeout(power_signal_mask_t want, - power_signal_mask_t mask, - int timeout); + power_signal_mask_t mask, int timeout); /** * @brief Wait until the selected power signals match, with timeout -- cgit v1.2.1 From 258e22b213f8b7509c86f8f63fdeaa18f75a7de4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:03 -0600 Subject: chip/stm32/fpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I951b71bcd762c67fc6d8c4f00f03b1a7f23331d4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729502 Reviewed-by: Jeremy Bettis --- chip/stm32/fpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/chip/stm32/fpu.c b/chip/stm32/fpu.c index b61d0354f7..34a6400baf 100644 --- a/chip/stm32/fpu.c +++ b/chip/stm32/fpu.c @@ -38,5 +38,6 @@ __attribute__((naked)) void IRQ_HANDLER(STM32_IRQ_FPU)(void) "pop {r0, pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(STM32_IRQ_FPU) - __attribute__((section(".rodata.irqprio"))) - = {STM32_IRQ_FPU, 0}; /* highest priority */ + __attribute__((section(".rodata.irqprio"))) = { STM32_IRQ_FPU, + 0 }; /* highest priority + */ -- cgit v1.2.1 From 6b6744ad3d3d13a5fffd56d9c74181ed0c791fbb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:50:07 -0600 Subject: driver/gyro_l3gd20h.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifb99ec92d42c16c6e3fedb791cca1e15eb4aaea6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729979 Reviewed-by: Jeremy Bettis --- driver/gyro_l3gd20h.h | 110 +++++++++++++++++++++++++------------------------- 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/driver/gyro_l3gd20h.h b/driver/gyro_l3gd20h.h index 7a7ed6b7da..13679ba2da 100644 --- a/driver/gyro_l3gd20h.h +++ b/driver/gyro_l3gd20h.h @@ -15,65 +15,65 @@ * 7-bit address is 110101Xb. Where 'X' is determined * by the voltage on the ADDR pin. */ -#define L3GD20_ADDR0_FLAGS 0x6a -#define L3GD20_ADDR1_FLAGS 0x6b +#define L3GD20_ADDR0_FLAGS 0x6a +#define L3GD20_ADDR1_FLAGS 0x6b /* who am I */ -#define L3GD20_WHO_AM_I 0xd7 +#define L3GD20_WHO_AM_I 0xd7 /* Chip specific registers. */ -#define L3GD20_WHO_AM_I_REG 0x0f -#define L3GD20_CTRL_REG1 0x20 -#define L3GD20_CTRL_REG2 0x21 -#define L3GD20_CTRL_REG3 0x22 -#define L3GD20_CTRL_REG4 0x23 -#define L3GD20_CTRL_REG5 0x24 -#define L3GD20_CTRL_REFERENCE 0x25 -#define L3GD20_OUT_TEMP 0x26 -#define L3GD20_STATUS_REG 0x27 -#define L3GD20_OUT_X_L 0x28 -#define L3GD20_OUT_X_H 0x29 -#define L3GD20_OUT_Y_L 0x2a -#define L3GD20_OUT_Y_H 0x2b -#define L3GD20_OUT_Z_L 0x2c -#define L3GD20_OUT_Z_H 0x2d -#define L3GD20_FIFO_CTRL_REG 0x2e -#define L3GD20_FIFO_SRC_REG 0x2f -#define L3GD20_INT1_CFG 0x30 -#define L3GD20_INT1_SRC 0x31 -#define L3GD20_INT1_TSH_XH 0x32 -#define L3GD20_INT1_TSH_XL 0x33 -#define L3GD20_INT1_TSH_YH 0x34 -#define L3GD20_INT1_TSH_YL 0x35 -#define L3GD20_INT1_TSH_ZH 0x36 -#define L3GD20_INT1_TSH_ZL 0x37 -#define L3GD20_INT1_DURATION 0x38 -#define L3GD20_LOW_ODR 0x39 +#define L3GD20_WHO_AM_I_REG 0x0f +#define L3GD20_CTRL_REG1 0x20 +#define L3GD20_CTRL_REG2 0x21 +#define L3GD20_CTRL_REG3 0x22 +#define L3GD20_CTRL_REG4 0x23 +#define L3GD20_CTRL_REG5 0x24 +#define L3GD20_CTRL_REFERENCE 0x25 +#define L3GD20_OUT_TEMP 0x26 +#define L3GD20_STATUS_REG 0x27 +#define L3GD20_OUT_X_L 0x28 +#define L3GD20_OUT_X_H 0x29 +#define L3GD20_OUT_Y_L 0x2a +#define L3GD20_OUT_Y_H 0x2b +#define L3GD20_OUT_Z_L 0x2c +#define L3GD20_OUT_Z_H 0x2d +#define L3GD20_FIFO_CTRL_REG 0x2e +#define L3GD20_FIFO_SRC_REG 0x2f +#define L3GD20_INT1_CFG 0x30 +#define L3GD20_INT1_SRC 0x31 +#define L3GD20_INT1_TSH_XH 0x32 +#define L3GD20_INT1_TSH_XL 0x33 +#define L3GD20_INT1_TSH_YH 0x34 +#define L3GD20_INT1_TSH_YL 0x35 +#define L3GD20_INT1_TSH_ZH 0x36 +#define L3GD20_INT1_TSH_ZL 0x37 +#define L3GD20_INT1_DURATION 0x38 +#define L3GD20_LOW_ODR 0x39 -#define L3GD20_DPS_SEL_245 (0 << 4) -#define L3GD20_DPS_SEL_500 BIT(4) -#define L3GD20_DPS_SEL_2000_0 (2 << 4) -#define L3GD20_DPS_SEL_2000_1 (3 << 4) +#define L3GD20_DPS_SEL_245 (0 << 4) +#define L3GD20_DPS_SEL_500 BIT(4) +#define L3GD20_DPS_SEL_2000_0 (2 << 4) +#define L3GD20_DPS_SEL_2000_1 (3 << 4) -#define L3GD20_ODR_PD (0 << 3) -#define L3GD20_ODR_12_5HZ (0 << 6) -#define L3GD20_ODR_25HZ BIT(6) -#define L3GD20_ODR_50HZ_0 (2 << 6) -#define L3GD20_ODR_50HZ_1 (3 << 6) -#define L3GD20_ODR_100HZ (0 << 6) -#define L3GD20_ODR_200HZ BIT(6) -#define L3GD20_ODR_400HZ (2 << 6) -#define L3GD20_ODR_800HZ (3 << 6) +#define L3GD20_ODR_PD (0 << 3) +#define L3GD20_ODR_12_5HZ (0 << 6) +#define L3GD20_ODR_25HZ BIT(6) +#define L3GD20_ODR_50HZ_0 (2 << 6) +#define L3GD20_ODR_50HZ_1 (3 << 6) +#define L3GD20_ODR_100HZ (0 << 6) +#define L3GD20_ODR_200HZ BIT(6) +#define L3GD20_ODR_400HZ (2 << 6) +#define L3GD20_ODR_800HZ (3 << 6) -#define L3GD20_ODR_MASK (3 << 6) -#define L3GD20_STS_ZYXDA_MASK BIT(3) -#define L3GD20_RANGE_MASK (3 << 4) -#define L3GD20_LOW_ODR_MASK BIT(0) -#define L3GD20_ODR_PD_MASK BIT(3) +#define L3GD20_ODR_MASK (3 << 6) +#define L3GD20_STS_ZYXDA_MASK BIT(3) +#define L3GD20_RANGE_MASK (3 << 4) +#define L3GD20_LOW_ODR_MASK BIT(0) +#define L3GD20_ODR_PD_MASK BIT(3) /* Min and Max sampling frequency in mHz */ -#define L3GD20_GYRO_MIN_FREQ 12500 -#define L3GD20_GYRO_MAX_FREQ \ +#define L3GD20_GYRO_MIN_FREQ 12500 +#define L3GD20_GYRO_MAX_FREQ \ MOTION_MAX_SENSOR_FREQUENCY(800000, L3GD20_GYRO_MIN_FREQ) /* @@ -81,8 +81,8 @@ * Address : 0X27 */ enum l3gd20_status { - L3GD20_STS_DOWN = 0x00, - L3GD20_STS_ZYXDA_UP = 0x08, + L3GD20_STS_DOWN = 0x00, + L3GD20_STS_ZYXDA_UP = 0x08, }; /* @@ -91,12 +91,12 @@ enum l3gd20_status { * Bit Group Name: BDU */ enum l3gd20_bdu { - L3GD20_BDU_DISABLE = 0x00, - L3GD20_BDU_ENABLE = 0x80, + L3GD20_BDU_DISABLE = 0x00, + L3GD20_BDU_ENABLE = 0x80, }; /* Sensor resolution in number of bits. This sensor has fixed resolution. */ -#define L3GD20_RESOLUTION 16 +#define L3GD20_RESOLUTION 16 extern const struct accelgyro_drv l3gd20h_drv; struct l3gd20_data { -- cgit v1.2.1 From 8baeaf9011772079714c0b26f55ba8300ef01254 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:03 -0600 Subject: zephyr/shim/include/usbc/virtual_usb_mux.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I17c3ed33c7fe1e4e2e7a846ec44ef229c81e459c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730844 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/virtual_usb_mux.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/shim/include/usbc/virtual_usb_mux.h b/zephyr/shim/include/usbc/virtual_usb_mux.h index 5f4c2fb466..b7afa202c0 100644 --- a/zephyr/shim/include/usbc/virtual_usb_mux.h +++ b/zephyr/shim/include/usbc/virtual_usb_mux.h @@ -8,13 +8,13 @@ #include "usb_mux.h" -#define VIRTUAL_USB_MUX_COMPAT cros_ec_usbc_mux_virtual +#define VIRTUAL_USB_MUX_COMPAT cros_ec_usbc_mux_virtual -#define USB_MUX_CONFIG_VIRTUAL(mux_id, port_id, idx) \ - { \ - USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ - .driver = &virtual_usb_mux_driver, \ - .hpd_update = &virtual_hpd_update, \ +#define USB_MUX_CONFIG_VIRTUAL(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &virtual_usb_mux_driver, \ + .hpd_update = &virtual_hpd_update, \ } #endif /* __ZEPHYR_SHIM_VIRTUAL_USB_MUX_H */ -- cgit v1.2.1 From 2ee9c65cf30cfab88f043cf0c1e912acfa92520b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:19:06 -0600 Subject: board/adlrvpp_mchp1727/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I28de8c470a20c4f4b18dfb4b7f7868fd9ef3b83a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727967 Reviewed-by: Jeremy Bettis --- board/adlrvpp_mchp1727/board.h | 86 +++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/board/adlrvpp_mchp1727/board.h b/board/adlrvpp_mchp1727/board.h index d806c92314..dcfdadba65 100644 --- a/board/adlrvpp_mchp1727/board.h +++ b/board/adlrvpp_mchp1727/board.h @@ -32,7 +32,7 @@ * #undef CONFIG_CLOCK_SRC_EXTERNAL * CONFIG_CLOCK_CRYSTAL is a don't care */ -#undef CONFIG_CLOCK_SRC_EXTERNAL +#undef CONFIG_CLOCK_SRC_EXTERNAL /* MEC1727 integrated SPI chip 512KB SST25PF040C */ #define CONFIG_SPI_FLASH_W25X40 @@ -52,10 +52,10 @@ #undef ADC_TEMP_SNS_DDR_CHANNEL #undef ADC_TEMP_SNS_SKIN_CHANNEL #undef ADC_TEMP_SNS_VR_CHANNEL -#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH3 -#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH5 -#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH4 -#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH0 +#define ADC_TEMP_SNS_AMBIENT_CHANNEL CHIP_ADC_CH3 +#define ADC_TEMP_SNS_DDR_CHANNEL CHIP_ADC_CH5 +#define ADC_TEMP_SNS_SKIN_CHANNEL CHIP_ADC_CH4 +#define ADC_TEMP_SNS_VR_CHANNEL CHIP_ADC_CH0 /* * ADC maximum voltage is a board level configuration. @@ -74,73 +74,73 @@ * which purpose. */ /* Power sequencing */ -#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD -#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N -#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3 -#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N -#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N -#define GPIO_EN_PP3300_A GPIO_EC_DS3 -#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK -#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK +#define GPIO_EC_SPI_OE_N GPIO_EC_SPI_OE_MECC +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_ALL_SYS_PWRGD +#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD +#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S0_N +#define GPIO_PG_EC_DSW_PWROK GPIO_VCCPDSW_3P3 +#define GPIO_SLP_SUS_L GPIO_PM_SLP_SUS_EC_N +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_PCH_RSMRST_L GPIO_PM_RSMRST_N +#define GPIO_PCH_PWRBTN_L GPIO_PM_PWRBTN_N +#define GPIO_EN_PP3300_A GPIO_EC_DS3 +#define GPIO_SYS_PWROK_EC GPIO_SYS_PWROK +#define GPIO_PCH_DSW_PWROK GPIO_EC_DSW_PWROK /* Sensors */ -#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION -#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N +#define GPIO_TABLET_MODE_L GPIO_SLATE_MODE_INDICATION +#define GPIO_CPU_PROCHOT GPIO_PROCHOT_EC_N /* Buttons */ -#define GPIO_LID_OPEN GPIO_SMC_LID -#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP -#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC -#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL +#define GPIO_LID_OPEN GPIO_SMC_LID +#define GPIO_VOLUME_UP_L GPIO_VOLUME_UP +#define GPIO_VOLUME_DOWN_L GPIO_VOL_DN_EC +#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL /* H1 */ -#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_FLASH_WP_ODL +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW /* AC & Battery */ -#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT -#define GPIO_AC_PRESENT GPIO_BC_ACOK -#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET +#define GPIO_DC_JACK_PRESENT GPIO_STD_ADP_PRSNT +#define GPIO_AC_PRESENT GPIO_BC_ACOK +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_DET /* eSPI/Host communication */ -#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N -#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC -#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL +#define GPIO_ESPI_RESET_L GPIO_LPC_ESPI_RST_N +#define GPIO_PCH_WAKE_L GPIO_SMC_WAKE_SCI_N_MECC +#define GPIO_EC_INT_L GPIO_EC_PCH_MKBP_INT_ODL /* LED */ -#define GPIO_BAT_LED_RED_L GPIO_LED_1_L -#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L +#define GPIO_BAT_LED_RED_L GPIO_LED_1_L +#define GPIO_PWR_LED_WHITE_L GPIO_LED_2_L /* FAN */ -#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC +#define GPIO_FAN_POWER_EN GPIO_THERM_SEN_MECC /* Charger */ -#define I2C_PORT_CHARGER MCHP_I2C_PORT0 +#define I2C_PORT_CHARGER MCHP_I2C_PORT0 /* Battery */ -#define I2C_PORT_BATTERY MCHP_I2C_PORT0 +#define I2C_PORT_BATTERY MCHP_I2C_PORT0 /* Board ID */ -#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0 +#define I2C_PORT_PCA9555_BOARD_ID_GPIO MCHP_I2C_PORT0 /* Port 80 */ -#define I2C_PORT_PORT80 MCHP_I2C_PORT0 +#define I2C_PORT_PORT80 MCHP_I2C_PORT0 /* USB-C I2C */ -#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT6 +#define I2C_PORT_TYPEC_0 MCHP_I2C_PORT6 /* * Note: I2C for Type-C Port-1 is swapped with Type-C Port-2 * on the RVP to reduce BOM stuffing options. */ -#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT3 +#define I2C_PORT_TYPEC_1 MCHP_I2C_PORT3 #if defined(HAS_TASK_PD_C2) -#define I2C_PORT_TYPEC_2 MCHP_I2C_PORT7 -#define I2C_PORT_TYPEC_3 MCHP_I2C_PORT2 +#define I2C_PORT_TYPEC_2 MCHP_I2C_PORT7 +#define I2C_PORT_TYPEC_3 MCHP_I2C_PORT2 #endif #ifndef __ASSEMBLER__ -- cgit v1.2.1 From 7cade92a673bc1a9caf32a2dae97174ccfb943d8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:59:12 -0600 Subject: board/pirika/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib09f9cd36a60b5d1af0236131bd846e22aab590a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728827 Reviewed-by: Jeremy Bettis --- board/pirika/board.h | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/board/pirika/board.h b/board/pirika/board.h index 932653e1ae..d25bb17f33 100644 --- a/board/pirika/board.h +++ b/board/pirika/board.h @@ -25,12 +25,13 @@ #define CONFIG_BC12_DETECT_PI3USB9201 /* Charger */ -#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */ +#define CONFIG_CHARGER_RAA489000 /* C0 and C1: Charger */ #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#undef CONFIG_CHARGER_SINGLE_CHIP +#undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) @@ -38,14 +39,14 @@ /* LED */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* PWM */ #define CONFIG_PWM /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ #define CONFIG_ACCEL_LSM6DSM_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) /* Sensors without hardware FIFO are in forced mode */ @@ -83,10 +84,10 @@ #define CONFIG_CHIPSET_CAN_THROTTLE /* USB Mux and Retimer */ -#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ -#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ +#define CONFIG_USB_MUX_IT5205 /* C1: ITE Mux */ +#define I2C_PORT_USB_MUX I2C_PORT_USB_C0 /* Required for ITE Mux */ -#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ +#define CONFIG_USBC_RETIMER_TUSB544 /* C1 Redriver: TUSB544 */ /* Keyboard */ #define CONFIG_KEYBOARD_VIVALDI @@ -110,19 +111,14 @@ enum pwm_channel { }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* ADC channels */ enum adc_channel { - ADC_VSNS_PP3300_A, /* ADC0 */ - ADC_TEMP_SENSOR_1, /* ADC2 */ - ADC_TEMP_SENSOR_2, /* ADC3 */ - ADC_TEMP_SENSOR_3, /* ADC15 */ + ADC_VSNS_PP3300_A, /* ADC0 */ + ADC_TEMP_SENSOR_1, /* ADC2 */ + ADC_TEMP_SENSOR_2, /* ADC3 */ + ADC_TEMP_SENSOR_3, /* ADC15 */ ADC_CH_COUNT }; -- cgit v1.2.1 From 70db1a80eb798b3a8a3a1d0ae0a36312026b375c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:24:51 -0600 Subject: test/usb_typec_drp_acc_trysrc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9fbb8cc19206fa96c5eac659ce51247c49f9b5ec Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730315 Reviewed-by: Jeremy Bettis --- test/usb_typec_drp_acc_trysrc.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/test/usb_typec_drp_acc_trysrc.c b/test/usb_typec_drp_acc_trysrc.c index 106370db72..47599d7975 100644 --- a/test/usb_typec_drp_acc_trysrc.c +++ b/test/usb_typec_drp_acc_trysrc.c @@ -34,11 +34,9 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - { - .driver = &mock_usb_mux_driver, - } -}; +const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { { + .driver = &mock_usb_mux_driver, +} }; void charge_manager_set_ceil(int port, enum ceil_requestor requestor, int ceil) { @@ -732,8 +730,8 @@ __maybe_unused static int test_auto_toggle_delay_early_connect(void) /* Ensure the auto toggle enable was never called */ task_wait_event(SECOND); - TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle, - TIMER_DISABLED, "%" PRIu64); + TEST_EQ(mock_tcpc.first_call_to_enable_auto_toggle, TIMER_DISABLED, + "%" PRIu64); /* Ensure that the first CC set call was to Rd. */ TEST_GT(cc_pull_count, 0, "%d"); -- cgit v1.2.1 From f5770848e1127822a7eb030577811c3830951d8c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:58 -0600 Subject: driver/tcpm/mt6370.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id835340a9ff5f92c1e36933f367c779acafd713d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730080 Reviewed-by: Jeremy Bettis --- driver/tcpm/mt6370.h | 192 +++++++++++++++++++++++++-------------------------- 1 file changed, 96 insertions(+), 96 deletions(-) diff --git a/driver/tcpm/mt6370.h b/driver/tcpm/mt6370.h index cdc3112a3e..c0bc3ceecc 100644 --- a/driver/tcpm/mt6370.h +++ b/driver/tcpm/mt6370.h @@ -10,158 +10,158 @@ /* MT6370 Private RegMap */ -#define MT6370_REG_PHY_CTRL1 0x80 -#define MT6370_REG_PHY_CTRL2 0x81 -#define MT6370_REG_PHY_CTRL3 0x82 -#define MT6370_REG_PHY_CTRL6 0x85 - -#define MT6370_REG_CLK_CTRL2 0x87 -#define MT6370_REG_CLK_CTRL3 0x88 - -#define MT6370_REG_RUST_STATUS 0x8A -#define MT6370_REG_RUST_INT_EVENT 0x8B -#define MT6370_REG_RUST_MASK 0x8C -#define MT6370_REG_BMC_CTRL 0x90 -#define MT6370_REG_BMCIO_RXDZSEL 0x93 -#define MT6370_REG_VCONN_CLIMITEN 0x95 - -#define MT6370_REG_OVP_FLAG_SEL 0x96 - -#define MT6370_REG_RT_STATUS 0x97 -#define MT6370_REG_RT_INT 0x98 -#define MT6370_REG_RT_MASK 0x99 -#define RT5081_REG_BMCIO_RXDZEN 0x9A -#define MT6370_REG_IDLE_CTRL 0x9B -#define MT6370_REG_INTRST_CTRL 0x9C -#define MT6370_REG_WATCHDOG_CTRL 0x9D -#define MT6370_REG_I2CRST_CTRL 0X9E - -#define MT6370_REG_SWRESET 0xA0 -#define MT6370_REG_TTCPC_FILTER 0xA1 -#define MT6370_REG_DRP_TOGGLE_CYCLE 0xA2 -#define MT6370_REG_DRP_DUTY_CTRL 0xA3 -#define MT6370_REG_RUST_DETECTION 0xAD -#define MT6370_REG_RUST_CONTROL 0xAE -#define MT6370_REG_BMCIO_RXDZEN 0xAF -#define MT6370_REG_DRP_RUST 0xB9 - -#define MT6370_REG_UNLOCK_PW2 0xF0 -#define MT6370_REG_UNLOCK_PW1 0xF1 - -#define MT6370_TCPC_I2C_ADDR_FLAGS 0x4E +#define MT6370_REG_PHY_CTRL1 0x80 +#define MT6370_REG_PHY_CTRL2 0x81 +#define MT6370_REG_PHY_CTRL3 0x82 +#define MT6370_REG_PHY_CTRL6 0x85 + +#define MT6370_REG_CLK_CTRL2 0x87 +#define MT6370_REG_CLK_CTRL3 0x88 + +#define MT6370_REG_RUST_STATUS 0x8A +#define MT6370_REG_RUST_INT_EVENT 0x8B +#define MT6370_REG_RUST_MASK 0x8C +#define MT6370_REG_BMC_CTRL 0x90 +#define MT6370_REG_BMCIO_RXDZSEL 0x93 +#define MT6370_REG_VCONN_CLIMITEN 0x95 + +#define MT6370_REG_OVP_FLAG_SEL 0x96 + +#define MT6370_REG_RT_STATUS 0x97 +#define MT6370_REG_RT_INT 0x98 +#define MT6370_REG_RT_MASK 0x99 +#define RT5081_REG_BMCIO_RXDZEN 0x9A +#define MT6370_REG_IDLE_CTRL 0x9B +#define MT6370_REG_INTRST_CTRL 0x9C +#define MT6370_REG_WATCHDOG_CTRL 0x9D +#define MT6370_REG_I2CRST_CTRL 0X9E + +#define MT6370_REG_SWRESET 0xA0 +#define MT6370_REG_TTCPC_FILTER 0xA1 +#define MT6370_REG_DRP_TOGGLE_CYCLE 0xA2 +#define MT6370_REG_DRP_DUTY_CTRL 0xA3 +#define MT6370_REG_RUST_DETECTION 0xAD +#define MT6370_REG_RUST_CONTROL 0xAE +#define MT6370_REG_BMCIO_RXDZEN 0xAF +#define MT6370_REG_DRP_RUST 0xB9 + +#define MT6370_REG_UNLOCK_PW2 0xF0 +#define MT6370_REG_UNLOCK_PW1 0xF1 + +#define MT6370_TCPC_I2C_ADDR_FLAGS 0x4E /* * MT6370_REG_PHY_CTRL1 0x80 */ -#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt, \ - rx_filter) \ - ((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) | \ +#define MT6370_REG_PHY_CTRL1_SET(retry_discard, toggle_cnt, bus_idle_cnt, \ + rx_filter) \ + ((retry_discard << 7) | (toggle_cnt << 4) | (bus_idle_cnt << 2) | \ (rx_filter & 0x03)) /* * MT6370_REG_CLK_CTRL2 0x87 */ -#define MT6370_REG_CLK_DIV_600K_EN BIT(7) -#define MT6370_REG_CLK_BCLK2_EN BIT(6) -#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5) -#define MT6370_REG_CLK_DIV_300K_EN BIT(3) -#define MT6370_REG_CLK_CK_300K_EN BIT(2) -#define MT6370_REG_CLK_BCLK_EN BIT(1) -#define MT6370_REG_CLK_BCLK_TH_EN BIT(0) +#define MT6370_REG_CLK_DIV_600K_EN BIT(7) +#define MT6370_REG_CLK_BCLK2_EN BIT(6) +#define MT6370_REG_CLK_BCLK2_TG_EN BIT(5) +#define MT6370_REG_CLK_DIV_300K_EN BIT(3) +#define MT6370_REG_CLK_CK_300K_EN BIT(2) +#define MT6370_REG_CLK_BCLK_EN BIT(1) +#define MT6370_REG_CLK_BCLK_TH_EN BIT(0) /* * MT6370_REG_CLK_CTRL3 0x88 */ -#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7) -#define MT6370_REG_CLK_CK_24M_EN BIT(6) -#define MT6370_REG_CLK_OSC_RG_EN BIT(5) -#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4) -#define MT6370_REG_CLK_CK_2P4M_EN BIT(3) -#define MT6370_REG_CLK_PCLK_EN BIT(2) -#define MT6370_REG_CLK_PCLK_RG_EN BIT(1) -#define MT6370_REG_CLK_PCLK_TG_EN BIT(0) +#define MT6370_REG_CLK_OSCMUX_RG_EN BIT(7) +#define MT6370_REG_CLK_CK_24M_EN BIT(6) +#define MT6370_REG_CLK_OSC_RG_EN BIT(5) +#define MT6370_REG_CLK_DIV_2P4M_EN BIT(4) +#define MT6370_REG_CLK_CK_2P4M_EN BIT(3) +#define MT6370_REG_CLK_PCLK_EN BIT(2) +#define MT6370_REG_CLK_PCLK_RG_EN BIT(1) +#define MT6370_REG_CLK_PCLK_TG_EN BIT(0) /* * MT6370_REG_RX_TX_DBG 0x8b */ -#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7) -#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6) +#define MT6370_REG_RX_TX_DBG_RX_BUSY BIT(7) +#define MT6370_REG_RX_TX_DBG_TX_BUSY BIT(6) /* * MT6370_REG_BMC_CTRL 0x90 */ -#define MT6370_REG_IDLE_EN BIT(6) -#define MT6370_REG_DISCHARGE_EN BIT(5) -#define MT6370_REG_BMCIO_LPRPRD BIT(4) -#define MT6370_REG_BMCIO_LPEN BIT(3) -#define MT6370_REG_BMCIO_BG_EN BIT(2) -#define MT6370_REG_VBUS_DET_EN BIT(1) -#define MT6370_REG_BMCIO_OSC_EN BIT(0) -#define MT6370_REG_BMC_CTRL_DEFAULT \ - (MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \ +#define MT6370_REG_IDLE_EN BIT(6) +#define MT6370_REG_DISCHARGE_EN BIT(5) +#define MT6370_REG_BMCIO_LPRPRD BIT(4) +#define MT6370_REG_BMCIO_LPEN BIT(3) +#define MT6370_REG_BMCIO_BG_EN BIT(2) +#define MT6370_REG_VBUS_DET_EN BIT(1) +#define MT6370_REG_BMCIO_OSC_EN BIT(0) +#define MT6370_REG_BMC_CTRL_DEFAULT \ + (MT6370_REG_BMCIO_BG_EN | MT6370_REG_VBUS_DET_EN | \ MT6370_REG_BMCIO_OSC_EN) /* * MT6370_REG_BMCIO_RXDZSEL 0x93 */ -#define MT6370_MASK_OCCTRL_SEL 0xE0 -#define MT6370_OCCTRL_600MA 0x80 -#define MT6370_MASK_BMCIO_RXDZSEL BIT(0) +#define MT6370_MASK_OCCTRL_SEL 0xE0 +#define MT6370_OCCTRL_600MA 0x80 +#define MT6370_MASK_BMCIO_RXDZSEL BIT(0) /* * MT6370_REG_OVP_FLAG_SEL 0x96 */ -#define MT6370_MASK_DISCHARGE_LVL 0x03 -#define MT6370_REG_DISCHARGE_LVL BIT(0) +#define MT6370_MASK_DISCHARGE_LVL 0x03 +#define MT6370_REG_DISCHARGE_LVL BIT(0) /* * MT6370_REG_RT_STATUS 0x97 */ -#define MT6370_REG_RA_DETACH BIT(5) -#define MT6370_REG_VBUS_80 BIT(1) +#define MT6370_REG_RA_DETACH BIT(5) +#define MT6370_REG_VBUS_80 BIT(1) /* * MT6370_REG_RT_INT 0x98 */ -#define MT6370_REG_INT_RA_DETACH BIT(5) -#define MT6370_REG_INT_WATCHDOG BIT(2) -#define MT6370_REG_INT_VBUS_80 BIT(1) -#define MT6370_REG_INT_WAKEUP BIT(0) +#define MT6370_REG_INT_RA_DETACH BIT(5) +#define MT6370_REG_INT_WATCHDOG BIT(2) +#define MT6370_REG_INT_VBUS_80 BIT(1) +#define MT6370_REG_INT_WAKEUP BIT(0) /* * MT6370_REG_RT_MASK 0x99 */ -#define MT6370_REG_M_RA_DETACH BIT(5) -#define MT6370_REG_M_WATCHDOG BIT(2) -#define MT6370_REG_M_VBUS_80 BIT(1) -#define MT6370_REG_M_WAKEUP BIT(0) +#define MT6370_REG_M_RA_DETACH BIT(5) +#define MT6370_REG_M_WATCHDOG BIT(2) +#define MT6370_REG_M_VBUS_80 BIT(1) +#define MT6370_REG_M_WAKEUP BIT(0) /* * MT6370_REG_IDLE_CTRL 0x9B */ -#define MT6370_REG_CK_300K_SEL BIT(7) -#define MT6370_REG_SHIPPING_OFF BIT(5) -#define MT6370_REG_ENEXTMSG BIT(4) -#define MT6370_REG_AUTOIDLE_EN BIT(3) +#define MT6370_REG_CK_300K_SEL BIT(7) +#define MT6370_REG_SHIPPING_OFF BIT(5) +#define MT6370_REG_ENEXTMSG BIT(4) +#define MT6370_REG_AUTOIDLE_EN BIT(3) /* timeout = (tout*2+1) * 6.4ms */ #ifdef CONFIG_USB_PD_REV30 -#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ - ((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) | \ +#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ + ((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07) | \ MT6370_REG_ENEXTMSG) #else -#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ +#define MT6370_REG_IDLE_SET(ck300, ship_dis, auto_idle, tout) \ ((ck300 << 7) | (ship_dis << 5) | (auto_idle << 3) | (tout & 0x07)) #endif @@ -169,28 +169,28 @@ * MT6370_REG_INTRST_CTRL 0x9C */ -#define MT6370_REG_INTRST_EN BIT(7) +#define MT6370_REG_INTRST_EN BIT(7) /* timeout = (tout+1) * 0.2sec */ -#define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03)) +#define MT6370_REG_INTRST_SET(en, tout) ((en << 7) | (tout & 0x03)) /* * MT6370_REG_WATCHDOG_CTRL 0x9D */ -#define MT6370_REG_WATCHDOG_EN BIT(7) +#define MT6370_REG_WATCHDOG_EN BIT(7) /* timeout = (tout+1) * 0.4sec */ -#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07)) +#define MT6370_REG_WATCHDOG_CTRL_SET(en, tout) ((en << 7) | (tout & 0x07)) /* * MT6370_REG_I2CRST_CTRL 0x9E */ -#define MT6370_REG_I2CRST_EN BIT(7) +#define MT6370_REG_I2CRST_EN BIT(7) /* timeout = (tout+1) * 12.5ms */ -#define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f)) +#define MT6370_REG_I2CRST_SET(en, tout) ((en << 7) | (tout & 0x0f)) extern const struct tcpm_drv mt6370_tcpm_drv; -- cgit v1.2.1 From 35a33a1b047710d50ec6e9962a536cdea3470b55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:24 -0600 Subject: board/drobit/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ife87b477840949015fc0542cdd2ea0d2ba057c19 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728263 Reviewed-by: Jeremy Bettis --- board/drobit/board.h | 95 ++++++++++++++++++++++++---------------------------- 1 file changed, 43 insertions(+), 52 deletions(-) diff --git a/board/drobit/board.h b/board/drobit/board.h index 12cfe834c6..9c7982f294 100644 --- a/board/drobit/board.h +++ b/board/drobit/board.h @@ -29,7 +29,7 @@ /* LED defines */ #define CONFIG_LED_ONOFF_STATES -#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 +#define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* Keyboard features */ #define CONFIG_KEYBOARD_VIVALDI @@ -42,20 +42,20 @@ #undef CONFIG_ACCEL_FIFO_SIZE /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 /* TODO: b/144165680 - measure and check these values on Volteer */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ /* * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 #define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY #ifdef BOARD_DROBIT_ECMODEENTRY @@ -68,11 +68,11 @@ /* Enabling USB4 mode */ #define CONFIG_USB_PD_USB4 -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 -#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x40 +#define USBC_PORT_C1_BB_RETIMER_I2C_ADDR 0x41 /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USBC PPC*/ @@ -87,8 +87,8 @@ /* Fan features */ /* charger defines */ -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* * Macros for GPIO signals used in common code that don't match the @@ -96,42 +96,41 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_EN_PP5000 GPIO_EN_PP5000_A -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_LID_OPEN GPIO_EC_LID_OPEN -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK -#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_L -#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_EN_PP5000 GPIO_EN_PP5000_A +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_LID_OPEN GPIO_EC_LID_OPEN +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_H1_PACKET_MODE +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_WAKE_ODL +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_ODL +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SLP_S0_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_PCH_DSW_PWROK GPIO_EC_PCH_DSW_PWROK +#define GPIO_POWER_BUTTON_L GPIO_H1_EC_PWR_BTN_ODL +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_USB_C1_BC12_INT_ODL GPIO_USB_C1_MIX_INT_ODL /* I2C Bus Configuration */ #define CONFIG_I2C -#define I2C_PORT_USB_C1_MIX NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 -#define I2C_PORT_POWER NPCX_I2C_PORT5_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_USB_C1_MIX NPCX_I2C_PORT0_0 +#define I2C_PORT_USB_C0 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_1_MIX NPCX_I2C_PORT3_0 +#define I2C_PORT_POWER NPCX_I2C_PORT5_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_BATTERY I2C_PORT_POWER -#define I2C_PORT_CHARGER I2C_PORT_EEPROM +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_EEPROM -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_I2C_CONTROLLER - #ifndef __ASSEMBLER__ #include "gpio_signal.h" @@ -142,11 +141,7 @@ enum battery_type { BATTERY_TYPE_COUNT, }; -enum pwm_channel { - PWM_CH_FAN = 0, - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN = 0, PWM_CH_KBLIGHT, PWM_CH_COUNT }; enum sensor_id { LID_ACCEL = 0, @@ -155,11 +150,7 @@ enum sensor_id { SENSOR_COUNT, }; -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void board_reset_pd_mcu(void); -- cgit v1.2.1 From 55a16b191952fe6802d0b02a0f94ad6db2a69180 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:23:49 -0600 Subject: test/usb_sm_checks.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia648c6996e68a882f057a54308455748a8f50e52 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730570 Reviewed-by: Jeremy Bettis --- test/usb_sm_checks.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/test/usb_sm_checks.h b/test/usb_sm_checks.h index d8e5f8ea06..93d5896632 100644 --- a/test/usb_sm_checks.h +++ b/test/usb_sm_checks.h @@ -11,11 +11,9 @@ int test_tc_no_parent_cycles(void); int test_tc_all_states_named(void); - int test_prl_no_parent_cycles(void); int test_prl_all_states_named(void); - int test_pe_no_parent_cycles(void); int test_pe_all_states_named(void); -- cgit v1.2.1 From d19cda7c43620a97f75436350b7e4ae9987cead5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:01 -0600 Subject: chip/stm32/otp-stm32f4.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5fb5bd2ddbb3c97f0ff267b97ffffd4711c1e7d9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729405 Reviewed-by: Jeremy Bettis --- chip/stm32/otp-stm32f4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/stm32/otp-stm32f4.c b/chip/stm32/otp-stm32f4.c index 45ce38d159..b962a08cd8 100644 --- a/chip/stm32/otp-stm32f4.c +++ b/chip/stm32/otp-stm32f4.c @@ -18,8 +18,7 @@ #ifdef CONFIG_SERIALNO_LEN /* Which block to use */ #define OTP_SERIAL_BLOCK 0 -#define OTP_SERIAL_ADDR \ - REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) +#define OTP_SERIAL_ADDR REG32_ADDR(STM32_OTP_BLOCK_DATA(OTP_SERIAL_BLOCK, 0)) /* Number of word used in the block */ #define OTP_SERIAL_BLOCK_SIZE (CONFIG_SERIALNO_LEN / sizeof(uint32_t)) @@ -40,7 +39,7 @@ static int otp_write(uint8_t block, int size, const char *data) if (size >= STM32_OTP_BLOCK_SIZE) return EC_ERROR_PARAM2; return crec_flash_physical_write(STM32_OTP_BLOCK_DATA(block, 0) - - CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_PROGRAM_MEMORY_BASE, size * sizeof(uint32_t), data); } @@ -74,7 +73,7 @@ static int otp_set_protect(uint8_t block) lock = REG32(STM32_OTP_LOCK(block)); lock &= ~STM32_OPT_LOCK_MASK(block); rv = crec_flash_physical_write(STM32_OTP_LOCK(block) - - CONFIG_PROGRAM_MEMORY_BASE, + CONFIG_PROGRAM_MEMORY_BASE, sizeof(uint32_t), (char *)&lock); if (rv) return rv; -- cgit v1.2.1 From 429a0ad5792a6e9ca8dbdb4cfc494c1dc2cd2e2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:37:10 -0600 Subject: board/gimble/fw_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I728814a105571770f10ef8b78ad8daf44a7c86a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728413 Reviewed-by: Jeremy Bettis --- board/gimble/fw_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/gimble/fw_config.c b/board/gimble/fw_config.c index 1589811ad0..d50b388550 100644 --- a/board/gimble/fw_config.c +++ b/board/gimble/fw_config.c @@ -9,7 +9,7 @@ #include "cros_board_info.h" #include "fw_config.h" -#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) static union brya_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); -- cgit v1.2.1 From ff60ea9d5493da9864bc77e06bc117346ecef4c4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:18 -0600 Subject: zephyr/projects/brya/include/gpio_map.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I70c689777e447548c3c8c20897f7d1a834898671 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730734 Reviewed-by: Jeremy Bettis --- zephyr/projects/brya/include/gpio_map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/brya/include/gpio_map.h b/zephyr/projects/brya/include/gpio_map.h index 98f3463132..83d819d110 100644 --- a/zephyr/projects/brya/include/gpio_map.h +++ b/zephyr/projects/brya/include/gpio_map.h @@ -9,7 +9,7 @@ #include #include -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED +#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #define GPIO_SEQ_EC_DSW_PWROK GPIO_PG_EC_DSW_PWROK -- cgit v1.2.1 From 4e5ba213530dcb009b6b1d841baafbb84d0e7fc5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:18:27 -0600 Subject: baseboard/volteer/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If24723d71c8cfe93be8f3dd2732c4da41469d9d8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727953 Reviewed-by: Jeremy Bettis --- baseboard/volteer/usb_pd_policy.c | 84 +++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 48 deletions(-) diff --git a/baseboard/volteer/usb_pd_policy.c b/baseboard/volteer/usb_pd_policy.c index 5b9000b3f7..ffd16b0088 100644 --- a/baseboard/volteer/usb_pd_policy.c +++ b/baseboard/volteer/usb_pd_policy.c @@ -14,8 +14,8 @@ #include "usb_pd.h" #include "system.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { @@ -79,49 +79,38 @@ int board_vbus_source_enabled(int port) #define OPOS_TBT 1 -static const union tbt_mode_resp_device vdo_tbt_modes[1] = { - { - .tbt_alt_mode = 0x0001, - .tbt_adapter = TBT_ADAPTER_TBT3, - .intel_spec_b0 = 0, - .vendor_spec_b0 = 0, - .vendor_spec_b1 = 0, - } -}; - -static const uint32_t vdo_idh = VDO_IDH( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - USB_VID_GOOGLE); - -static const uint32_t vdo_idh_rev30 = VDO_IDH_REV30( - 1, /* Data caps as USB host */ - 0, /* Not a USB device */ - IDH_PTYPE_PERIPH, - 1, /* Supports alt modes */ - IDH_PTYPE_DFP_HOST, - USB_TYPEC_RECEPTACLE, - USB_VID_GOOGLE); - -static const uint32_t vdo_product = VDO_PRODUCT( - CONFIG_USB_PID, CONFIG_USB_BCD_DEV); +static const union tbt_mode_resp_device vdo_tbt_modes[1] = { { + .tbt_alt_mode = 0x0001, + .tbt_adapter = TBT_ADAPTER_TBT3, + .intel_spec_b0 = 0, + .vendor_spec_b0 = 0, + .vendor_spec_b1 = 0, +} }; + +static const uint32_t vdo_idh = VDO_IDH(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt + modes */ + USB_VID_GOOGLE); + +static const uint32_t vdo_idh_rev30 = + VDO_IDH_REV30(1, /* Data caps as USB host */ + 0, /* Not a USB device */ + IDH_PTYPE_PERIPH, 1, /* Supports alt modes */ + IDH_PTYPE_DFP_HOST, USB_TYPEC_RECEPTACLE, USB_VID_GOOGLE); + +static const uint32_t vdo_product = + VDO_PRODUCT(CONFIG_USB_PID, CONFIG_USB_BCD_DEV); /* TODO(b/168890624): add USB4 to capability once USB4 response implemented */ static const uint32_t vdo_ufp1 = VDO_UFP1( - (VDO_UFP1_CAPABILITY_USB20 - | VDO_UFP1_CAPABILITY_USB32), - USB_TYPEC_RECEPTACLE, - VDO_UFP1_ALT_MODE_TBT3, - USB_R30_SS_U40_GEN3); - -static const uint32_t vdo_dfp = VDO_DFP( - (VDO_DFP_HOST_CAPABILITY_USB20 - | VDO_DFP_HOST_CAPABILITY_USB32 - | VDO_DFP_HOST_CAPABILITY_USB4), - USB_TYPEC_RECEPTACLE, - 1 /* Port 1 */); + (VDO_UFP1_CAPABILITY_USB20 | VDO_UFP1_CAPABILITY_USB32), + USB_TYPEC_RECEPTACLE, VDO_UFP1_ALT_MODE_TBT3, USB_R30_SS_U40_GEN3); + +static const uint32_t vdo_dfp = + VDO_DFP((VDO_DFP_HOST_CAPABILITY_USB20 | VDO_DFP_HOST_CAPABILITY_USB32 | + VDO_DFP_HOST_CAPABILITY_USB4), + USB_TYPEC_RECEPTACLE, 1 /* Port 1 */); static int svdm_tbt_compat_response_identity(int port, uint32_t *payload) { @@ -163,8 +152,8 @@ static int svdm_tbt_compat_response_modes(int port, uint32_t *payload) /* Track whether we've been enabled to ACK TBT EnterModes requests */ static bool tbt_ufp_ack_allowed[CONFIG_USB_PD_PORT_MAX_COUNT]; -__override enum ec_status board_set_tbt_ufp_reply(int port, - enum typec_tbt_ufp_reply reply) +__override enum ec_status +board_set_tbt_ufp_reply(int port, enum typec_tbt_ufp_reply reply) { /* Note: Host command has already bounds-checked port */ if (reply == TYPEC_TBT_UFP_REPLY_ACK) @@ -177,8 +166,7 @@ __override enum ec_status board_set_tbt_ufp_reply(int port, return EC_RES_SUCCESS; } -static int svdm_tbt_compat_response_enter_mode( - int port, uint32_t *payload) +static int svdm_tbt_compat_response_enter_mode(int port, uint32_t *payload) { mux_state_t mux_state = 0; @@ -191,7 +179,7 @@ static int svdm_tbt_compat_response_enter_mode( return 0; /* NAK */ if ((PD_VDO_VID(payload[0]) != USB_VID_INTEL) || - (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) + (PD_VDO_OPOS(payload[0]) != OPOS_TBT)) return 0; /* NAK */ mux_state = usb_mux_get(port); @@ -201,7 +189,7 @@ static int svdm_tbt_compat_response_enter_mode( * Mode that requires the reconfiguring of any pins. */ if ((mux_state & USB_PD_MUX_USB_ENABLED) || - (mux_state & USB_PD_MUX_SAFE_MODE)) { + (mux_state & USB_PD_MUX_SAFE_MODE)) { pd_ufp_set_enter_mode(port, payload); set_tbt_compat_mode_ready(port); -- cgit v1.2.1 From ec9baa734b15aafe15ac3d41ac1ad95cf3449abd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:30:53 -0600 Subject: board/dojo/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I507dddaf1917bb4bca6ad995e8f98aa0a73271e6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728232 Reviewed-by: Jeremy Bettis --- board/dojo/led.c | 82 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 44 insertions(+), 38 deletions(-) diff --git a/board/dojo/led.c b/board/dojo/led.c index 38d0e4904b..4f59ca89b7 100644 --- a/board/dojo/led.c +++ b/board/dojo/led.c @@ -38,7 +38,7 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; enum led_port { @@ -49,15 +49,15 @@ enum led_port { static void battery_led_set_color(enum led_port port, enum led_color color) { pwm_enable(port ? PWM_CH_LED_C1_AMBER : PWM_CH_LED_C0_AMBER, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); pwm_enable(port ? PWM_CH_LED_C1_WHITE : PWM_CH_LED_C0_WHITE, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } static void power_led_set_color(enum led_color color) { pwm_enable(PWM_CH_LED_PWR, - (color == LED_WHITE) ? PWR_LED_ON : PWR_LED_OFF); + (color == LED_WHITE) ? PWR_LED_ON : PWR_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -83,17 +83,17 @@ void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) static int led_set_color(enum ec_led_id led_id, enum led_color color) { switch (led_id) { - case EC_LED_ID_RIGHT_LED: - battery_led_set_color(RIGHT_PORT, color); - break; - case EC_LED_ID_LEFT_LED: - battery_led_set_color(LEFT_PORT, color); - break; - case EC_LED_ID_POWER_LED: - power_led_set_color(color); - break; - default: - return EC_ERROR_UNKNOWN; + case EC_LED_ID_RIGHT_LED: + battery_led_set_color(RIGHT_PORT, color); + break; + case EC_LED_ID_LEFT_LED: + battery_led_set_color(LEFT_PORT, color); + break; + case EC_LED_ID_POWER_LED: + power_led_set_color(color); + break; + default: + return EC_ERROR_UNKNOWN; } return EC_SUCCESS; @@ -121,10 +121,10 @@ static void set_active_port_color(enum led_color color) if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) battery_led_set_color(RIGHT_PORT, - (port == RIGHT_PORT) ? color : LED_OFF); + (port == RIGHT_PORT) ? color : LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) battery_led_set_color(LEFT_PORT, - (port == LEFT_PORT) ? color : LED_OFF); + (port == LEFT_PORT) ? color : LED_OFF); } static void board_led_set_battery(void) @@ -142,18 +142,20 @@ static void board_led_set_battery(void) break; case PWR_STATE_DISCHARGE: if (charge_get_percent() <= 10) { - battery_led_blink_cycle = battery_ticks % - (2 * TIMES_TICK_ONE_SEC); + battery_led_blink_cycle = + battery_ticks % (2 * TIMES_TICK_ONE_SEC); if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) battery_led_set_color(RIGHT_PORT, - (battery_led_blink_cycle < - TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + (battery_led_blink_cycle < + TIMES_TICK_ONE_SEC) ? + LED_AMBER : + LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) battery_led_set_color(LEFT_PORT, - (battery_led_blink_cycle < - TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + (battery_led_blink_cycle < + TIMES_TICK_ONE_SEC) ? + LED_AMBER : + LED_OFF); } else { if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) battery_led_set_color(RIGHT_PORT, LED_OFF); @@ -165,25 +167,28 @@ static void board_led_set_battery(void) battery_led_blink_cycle = battery_ticks % TIMES_TICK_ONE_SEC; if (led_auto_control_is_enabled(EC_LED_ID_RIGHT_LED)) battery_led_set_color(RIGHT_PORT, - (battery_led_blink_cycle < - TIMES_TICK_HALF_SEC) ? - LED_AMBER : LED_OFF); + (battery_led_blink_cycle < + TIMES_TICK_HALF_SEC) ? + LED_AMBER : + LED_OFF); if (led_auto_control_is_enabled(EC_LED_ID_LEFT_LED)) battery_led_set_color(LEFT_PORT, - (battery_led_blink_cycle < - TIMES_TICK_HALF_SEC) ? - LED_AMBER : LED_OFF); + (battery_led_blink_cycle < + TIMES_TICK_HALF_SEC) ? + LED_AMBER : + LED_OFF); break; case PWR_STATE_CHARGE_NEAR_FULL: set_active_port_color(LED_WHITE); break; case PWR_STATE_IDLE: /* External power connected in IDLE */ if (chflags & CHARGE_FLAG_FORCE_IDLE) { - battery_led_blink_cycle = battery_ticks % - (2 * TIMES_TICK_ONE_SEC); - set_active_port_color((battery_led_blink_cycle < - TIMES_TICK_ONE_SEC) ? - LED_AMBER : LED_OFF); + battery_led_blink_cycle = + battery_ticks % (2 * TIMES_TICK_ONE_SEC); + set_active_port_color( + (battery_led_blink_cycle < TIMES_TICK_ONE_SEC) ? + LED_AMBER : + LED_OFF); } else set_active_port_color(LED_WHITE); break; @@ -205,7 +210,8 @@ static void board_led_set_power(void) } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { power_led_blink_cycle = power_ticks % (2 * TIMES_TICK_ONE_SEC); power_led_set_color(power_led_blink_cycle < TIMES_TICK_ONE_SEC ? - LED_WHITE : LED_OFF); + LED_WHITE : + LED_OFF); } else { power_led_set_color(LED_OFF); } @@ -214,7 +220,7 @@ static void board_led_set_power(void) /* Called by hook task every TICK */ static void led_tick(void) { - if(led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) + if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) board_led_set_power(); board_led_set_battery(); -- cgit v1.2.1 From 56cf21f601c688114d1ae9a5e3321ee6034fee6d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:23:31 -0600 Subject: board/boldar/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia5fbc53fda8d574b98219355b2fa3e8b7ae21377 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728065 Reviewed-by: Jeremy Bettis --- board/boldar/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/boldar/led.c b/board/boldar/led.c index 6ee71bbe19..1cd5d092a2 100644 --- a/board/boldar/led.c +++ b/board/boldar/led.c @@ -19,16 +19,16 @@ const enum ec_led_id supported_led_ids[] = { const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); struct pwm_led_color_map led_color_map[] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 100, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 100, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, /* The green LED seems to be brighter than the others, so turn down * green from its natural level for these secondary colors. */ - [EC_LED_COLOR_YELLOW] = { 100, 70, 0 }, - [EC_LED_COLOR_WHITE] = { 100, 70, 100 }, - [EC_LED_COLOR_AMBER] = { 100, 20, 0 }, + [EC_LED_COLOR_YELLOW] = { 100, 70, 0 }, + [EC_LED_COLOR_WHITE] = { 100, 70, 100 }, + [EC_LED_COLOR_AMBER] = { 100, 20, 0 }, }; struct pwm_led pwm_leds[] = { -- cgit v1.2.1 From 7e97a5460c4e30ce617ce84da8256543dec46cc8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:11 -0600 Subject: cts/gpio/dut.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ffce5bd03fa42ce14d38bf6424bc992cc7d467d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729741 Reviewed-by: Jeremy Bettis --- cts/gpio/dut.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cts/gpio/dut.c b/cts/gpio/dut.c index 7ed613911c..33742e7472 100644 --- a/cts/gpio/dut.c +++ b/cts/gpio/dut.c @@ -21,7 +21,7 @@ enum cts_rc set_high_test(void) { gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW); gpio_set_level(GPIO_OUTPUT_TEST, 1); - msleep(READ_WAIT_TIME_MS*2); + msleep(READ_WAIT_TIME_MS * 2); return CTS_RC_SUCCESS; } @@ -29,7 +29,7 @@ enum cts_rc set_low_test(void) { gpio_set_flags(GPIO_OUTPUT_TEST, GPIO_ODR_LOW); gpio_set_level(GPIO_OUTPUT_TEST, 0); - msleep(READ_WAIT_TIME_MS*2); + msleep(READ_WAIT_TIME_MS * 2); return CTS_RC_SUCCESS; } -- cgit v1.2.1 From a35a0397726fc87016310e6df6cf7aa5fb63e15c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:11 -0600 Subject: zephyr/emul/emul_kb_raw.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic45bcae0c25cb86efe934773ee9b38cb07f704c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730692 Reviewed-by: Jeremy Bettis --- zephyr/emul/emul_kb_raw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/emul/emul_kb_raw.c b/zephyr/emul/emul_kb_raw.c index 238c9673bb..1f999f807e 100644 --- a/zephyr/emul/emul_kb_raw.c +++ b/zephyr/emul/emul_kb_raw.c @@ -109,7 +109,7 @@ static const struct cros_kb_raw_driver_api emul_kb_raw_driver_api = { static struct kb_raw_emul_data kb_raw_emul_data_##n = { \ .matrix = kb_raw_emul_matrix_##n, \ }; \ - \ + \ static const struct kb_raw_emul_cfg kb_raw_emul_cfg_##n = { \ .dev_label = DT_INST_LABEL(n), \ .data = &kb_raw_emul_data_##n, \ -- cgit v1.2.1 From 5bb77295d3fc555d92df54e93ab65f33ee048128 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:33 -0600 Subject: baseboard/herobrine/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I35a3a12d98874d666a4dfb3785ede63613e4dc3d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727526 Reviewed-by: Jeremy Bettis --- baseboard/herobrine/usb_pd_policy.c | 39 +++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/baseboard/herobrine/usb_pd_policy.c b/baseboard/herobrine/usb_pd_policy.c index 7ca2688aef..0710a799c2 100644 --- a/baseboard/herobrine/usb_pd_policy.c +++ b/baseboard/herobrine/usb_pd_policy.c @@ -12,8 +12,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) int pd_check_vconn_swap(int port) { @@ -23,10 +23,10 @@ int pd_check_vconn_swap(int port) static uint8_t vbus_en[CONFIG_USB_PD_PORT_MAX_COUNT]; #if CONFIG_USB_PD_PORT_MAX_COUNT == 1 -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5 }; #else -static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = {TYPEC_RP_1A5, - TYPEC_RP_1A5}; +static uint8_t vbus_rp[CONFIG_USB_PD_PORT_MAX_COUNT] = { TYPEC_RP_1A5, + TYPEC_RP_1A5 }; #endif static void board_vbus_update_source_current(int port) @@ -107,11 +107,11 @@ __override int svdm_dp_config(int port, uint32_t *payload) * (3) plug a monitor to the port-1 dongle. */ - payload[0] = VDO(USB_SID_DISPLAYPORT, 1, - CMD_DP_CONFIG | VDO_OPOS(opos)); - payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ - 1, /* DPv1.3 signaling */ - 2); /* UFP connected */ + payload[0] = + VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ return 2; }; @@ -187,8 +187,7 @@ __override int svdm_dp_attention(int port, uint32_t *payload) * because of the board USB-C topology (limited to 2 * lanes DP). */ - usb_mux_set(port, USB_PD_MUX_DOCK, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_DOCK, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } else { /* Disconnect the DP port selection mux. */ @@ -200,13 +199,11 @@ __override int svdm_dp_attention(int port, uint32_t *payload) ppc_set_sbu(port, 0); /* Disconnect the DP but keep the USB SS lines in TCPC chip. */ - usb_mux_set(port, USB_PD_MUX_USB_ENABLED, - USB_SWITCH_CONNECT, + usb_mux_set(port, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, polarity_rm_dts(pd_get_polarity(port))); } - if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && - (irq || lvl)) + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && (irq || lvl)) /* * Wake up the AP. IRQ or level high indicates a DP sink is now * present. @@ -231,16 +228,16 @@ __override int svdm_dp_attention(int port, uint32_t *payload) gpio_set_level(hpd, 1); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } else if (irq & !lvl) { CPRINTF("ERR:HPD:IRQ&LOW\n"); return 0; } else { gpio_set_level(hpd, lvl); /* Set the minimum time delay (2ms) for the next HPD IRQ */ - svdm_hpd_deadline[port] = get_time().val + - HPD_USTREAM_DEBOUNCE_LVL; + svdm_hpd_deadline[port] = + get_time().val + HPD_USTREAM_DEBOUNCE_LVL; } return 1; @@ -255,7 +252,7 @@ __override void svdm_exit_dp_mode(int port) /* Signal AP for the HPD low event */ usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); gpio_set_level(GPIO_DP_HOT_PLUG_DET, 0); } } -- cgit v1.2.1 From e739d3e1e6ce7cb8dae18f46910deb557ff9e3b7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:17:33 -0600 Subject: chip/it83xx/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibf7801bdbb74abe40491da2f415c2f18ac81d47e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729204 Reviewed-by: Jeremy Bettis --- chip/it83xx/pwm.c | 44 ++++++++++++++++++++++++-------------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/chip/it83xx/pwm.c b/chip/it83xx/pwm.c index fda8dd23d6..6c80c6bf2e 100644 --- a/chip/it83xx/pwm.c +++ b/chip/it83xx/pwm.c @@ -15,28 +15,28 @@ #include "math_util.h" #define PWM_CTRX_MIN 100 -#define PWM_EC_FREQ 8000000 +#define PWM_EC_FREQ 8000000 const struct pwm_ctrl_t pwm_ctrl_regs[] = { - { &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0}, - { &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1}, - { &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2}, - { &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3}, - { &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4}, - { &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5}, - { &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6}, - { &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7}, + { &IT83XX_PWM_DCR0, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA0 }, + { &IT83XX_PWM_DCR1, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA1 }, + { &IT83XX_PWM_DCR2, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA2 }, + { &IT83XX_PWM_DCR3, &IT83XX_PWM_PCSSGL, &IT83XX_GPIO_GPCRA3 }, + { &IT83XX_PWM_DCR4, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA4 }, + { &IT83XX_PWM_DCR5, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA5 }, + { &IT83XX_PWM_DCR6, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA6 }, + { &IT83XX_PWM_DCR7, &IT83XX_PWM_PCSSGH, &IT83XX_GPIO_GPCRA7 }, }; const struct pwm_ctrl_t2 pwm_clock_ctrl_regs[] = { { &IT83XX_PWM_CTR, &IT83XX_PWM_C0CPRS, &IT83XX_PWM_C0CPRS, - &IT83XX_PWM_PCFSR, 0x01}, + &IT83XX_PWM_PCFSR, 0x01 }, { &IT83XX_PWM_CTR1, &IT83XX_PWM_C4CPRS, &IT83XX_PWM_C4MCPRS, - &IT83XX_PWM_PCFSR, 0x02}, + &IT83XX_PWM_PCFSR, 0x02 }, { &IT83XX_PWM_CTR2, &IT83XX_PWM_C6CPRS, &IT83XX_PWM_C6MCPRS, - &IT83XX_PWM_PCFSR, 0x04}, + &IT83XX_PWM_PCFSR, 0x04 }, { &IT83XX_PWM_CTR3, &IT83XX_PWM_C7CPRS, &IT83XX_PWM_C7MCPRS, - &IT83XX_PWM_PCFSR, 0x08}, + &IT83XX_PWM_PCFSR, 0x08 }, }; static int pwm_get_cycle_time(enum pwm_channel ch) @@ -76,9 +76,10 @@ void pwm_enable(enum pwm_channel ch, int enabled) if (enabled) *pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x00; else - *pwm_ctrl_regs[pwm_reg_index].pwm_pin = 0x80 | - ((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ? - 4 : 2); + *pwm_ctrl_regs[pwm_reg_index].pwm_pin = + 0x80 | + ((pwm_channels[ch].flags & PWM_CONFIG_ACTIVE_LOW) ? 4 : + 2); } int pwm_get_enabled(enum pwm_channel ch) @@ -88,7 +89,9 @@ int pwm_get_enabled(enum pwm_channel ch) /* pin is PWM function and PWMs clock counter was enabled */ return ((*pwm_ctrl_regs[ch].pwm_pin & ~0x04) == 0x00 && - IT83XX_PWM_ZTIER & 0x02) ? 1 : 0; + IT83XX_PWM_ZTIER & 0x02) ? + 1 : + 0; } void pwm_set_duty(enum pwm_channel ch, int percent) @@ -202,7 +205,8 @@ static int pwm_ch_freq(enum pwm_channel ch) int actual_freq = -1, targe_freq, deviation; int pcfsr, ctr, pcfsr_sel, pcs_shift, pcs_mask; int pwm_clk_src = (pwm_channels[ch].flags & PWM_CONFIG_DSLEEP) ? - 32768 : PWM_EC_FREQ; + 32768 : + PWM_EC_FREQ; targe_freq = pwm_channels[ch].freq_hz; deviation = (targe_freq / 100) + 1; @@ -251,8 +255,8 @@ static int pwm_ch_freq(enum pwm_channel ch) *pwm_ctrl_regs[ch].pwm_clock_source |= pcs_mask; *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_lsb = pcfsr & 0xFF; - *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb = - (pcfsr >> 8) & 0xFF; + *pwm_clock_ctrl_regs[pcfsr_sel].pwm_cpr_msb = (pcfsr >> 8) & + 0xFF; } return actual_freq; -- cgit v1.2.1 From 9314bea0e45825cb68e03393f1421fbdce9a2859 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:26:04 -0600 Subject: board/cherry/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia179103c4edd1c0d958ada620d06b2b7fd8e34cb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728143 Reviewed-by: Jeremy Bettis --- board/cherry/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/cherry/board.h b/board/cherry/board.h index 73f7d4044d..e9119e6a34 100644 --- a/board/cherry/board.h +++ b/board/cherry/board.h @@ -26,14 +26,15 @@ #define CONFIG_LED_ONOFF_STATES_BAT_LOW 10 /* PD / USB-C / PPC */ -#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console */ +#undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \ + */ /* Optional console commands */ #define CONFIG_CMD_FLASH #define CONFIG_CMD_SCRATCHPAD #define CONFIG_CMD_STACKOVERFLOW -#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 +#define CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV 9000 /* Keyboard */ #define CONFIG_KEYBOARD_REFRESH_ROW3 -- cgit v1.2.1 From 6acb160e0a51f5ecb61c046c5d69e656dd48f09f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:07:37 -0600 Subject: board/taeko/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3c5708c9ac704bee30374fbf8d6c624a89d223c1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728986 Reviewed-by: Jeremy Bettis --- board/taeko/usbc_config.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/board/taeko/usbc_config.h b/board/taeko/usbc_config.h index 9030333dbc..98b7ab28a0 100644 --- a/board/taeko/usbc_config.h +++ b/board/taeko/usbc_config.h @@ -8,13 +8,9 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_C1, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; void config_usb_db_type(void); -- cgit v1.2.1 From fcbc1bb1b0c68c39657da5a703541efce5eab79c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:16:36 -0600 Subject: baseboard/kalista/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9736afe0e7e505d4a2d22676aaa75f3f801d2bbc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727910 Reviewed-by: Jeremy Bettis --- baseboard/kalista/baseboard.h | 68 ++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 36 deletions(-) diff --git a/baseboard/kalista/baseboard.h b/baseboard/kalista/baseboard.h index 717d26b313..608617ca3e 100644 --- a/baseboard/kalista/baseboard.h +++ b/baseboard/kalista/baseboard.h @@ -12,7 +12,7 @@ * Allow dangerous commands. * TODO: Remove this config before production. */ -#undef CONFIG_SYSTEM_UNLOCKED +#undef CONFIG_SYSTEM_UNLOCKED #define CONFIG_USB_PD_COMM_LOCKED /* EC */ @@ -32,7 +32,7 @@ #define CONFIG_FPU #define CONFIG_I2C #define CONFIG_I2C_CONTROLLER -#undef CONFIG_LID_SWITCH +#undef CONFIG_LID_SWITCH #define CONFIG_POWER_BUTTON_IGNORE_LID #define CONFIG_PWM #define CONFIG_LTO @@ -47,7 +47,7 @@ #define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN #define WIRELESS_GPIO_WWAN GPIO_PP3300_DX_LTE #define CEC_GPIO_OUT GPIO_CEC_OUT -#define CEC_GPIO_IN GPIO_CEC_IN +#define CEC_GPIO_IN GPIO_CEC_IN #define CEC_GPIO_PULL_UP GPIO_CEC_PULL_UP #define CONFIG_FANS 1 #define CONFIG_FAN_RPM_CUSTOM @@ -70,7 +70,7 @@ #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 @@ -105,20 +105,20 @@ #define USB_PORT_COUNT 4 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 1 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 -#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_THERMAL NPCX_I2C_PORT3 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT0_1 +#define I2C_PORT_BACKLIGHT NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_TCPC0_FLAGS 0x0b -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_TCPC0_FLAGS 0x0b +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Verify and jump to RW image on boot */ #define CONFIG_VBOOT_EFS @@ -140,23 +140,22 @@ * end of RW_A and RW_B, respectively. */ #define CONFIG_RW_B -#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF -#undef CONFIG_RO_SIZE -#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) -#undef CONFIG_RW_SIZE -#define CONFIG_RW_SIZE CONFIG_RO_SIZE -#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE) -#define CONFIG_RW_A_SIGN_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) -#define CONFIG_RW_B_SIGN_STORAGE_OFF (CONFIG_RW_B_STORAGE_OFF + \ - CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_MEM_OFF CONFIG_RO_MEM_OFF +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE (CONFIG_FLASH_SIZE_BYTES / 4) +#undef CONFIG_RW_SIZE +#define CONFIG_RW_SIZE CONFIG_RO_SIZE +#define CONFIG_RW_A_STORAGE_OFF CONFIG_RW_STORAGE_OFF +#define CONFIG_RW_B_STORAGE_OFF (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE) +#define CONFIG_RW_A_SIGN_STORAGE_OFF \ + (CONFIG_RW_A_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) +#define CONFIG_RW_B_SIGN_STORAGE_OFF \ + (CONFIG_RW_B_STORAGE_OFF + CONFIG_RW_SIZE - CONFIG_RW_SIG_SIZE) #undef CONFIG_EC_PROTECTED_STORAGE_SIZE -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE #undef CONFIG_EC_WRITABLE_STORAGE_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE #define CONFIG_RWSIG #define CONFIG_RWSIG_TYPE_RWSIG @@ -182,15 +181,12 @@ enum charge_port { }; enum temp_sensor_id { - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ TEMP_SENSOR_COUNT }; -enum adc_channel { - ADC_VBUS, - ADC_CH_COUNT -}; +enum adc_channel { ADC_VBUS, ADC_CH_COUNT }; enum pwm_channel { PWM_CH_LED_RED, @@ -223,8 +219,8 @@ enum OEM_ID { * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ -- cgit v1.2.1 From faa19aaeac2038ad2ae35e61c7c2a8237f9248af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:20:34 -0600 Subject: board/anahera/fw_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I66e9499531743c43b00a26df76014dc5f6caa43d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727988 Reviewed-by: Jeremy Bettis --- board/anahera/fw_config.h | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/board/anahera/fw_config.h b/board/anahera/fw_config.h index 92bc9e55e7..ddbb741ffc 100644 --- a/board/anahera/fw_config.h +++ b/board/anahera/fw_config.h @@ -19,10 +19,7 @@ enum ec_cfg_keyboard_backlight_type { KEYBOARD_BACKLIGHT_ENABLED = 1 }; -enum ec_cfg_eps_type { - EPS_DISABLED = 0, - EPS_ENABLED = 1 -}; +enum ec_cfg_eps_type { EPS_DISABLED = 0, EPS_ENABLED = 1 }; enum ec_cfg_ite_type { LTE_NOT_PRESENT = 0, @@ -31,14 +28,14 @@ enum ec_cfg_ite_type { union anahera_cbi_fw_config { struct { - uint32_t sd_db : 2; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - enum ec_cfg_ite_type lte_db : 2; - uint32_t ufc : 2; - enum ec_cfg_eps_type eps : 1; - uint32_t boot_device : 2; - uint32_t reserved_1 : 19; + uint32_t sd_db : 2; + enum ec_cfg_keyboard_backlight_type kb_bl : 1; + uint32_t audio : 3; + enum ec_cfg_ite_type lte_db : 2; + uint32_t ufc : 2; + enum ec_cfg_eps_type eps : 1; + uint32_t boot_device : 2; + uint32_t reserved_1 : 19; }; uint32_t raw_value; }; -- cgit v1.2.1 From e07ee44293e3ceca0bc2c7e0b6df7f2ce1619e62 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:08 -0600 Subject: chip/ish/power_mgt.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I258b8735eba07c6ab80353f95488c75014268d97 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729161 Reviewed-by: Jeremy Bettis --- chip/ish/power_mgt.c | 62 ++++++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/chip/ish/power_mgt.c b/chip/ish/power_mgt.c index 70c3b35aa5..d6546d9fa4 100644 --- a/chip/ish/power_mgt.c +++ b/chip/ish/power_mgt.c @@ -52,7 +52,7 @@ static void pg_exit_restore_hw(void) * fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the low speed clock is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) /* power management internal context data structure */ struct pm_context { @@ -172,20 +172,20 @@ static void init_aon_task(void) * limit: 0x67 * Present = 1, DPL = 0 */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); + desc_lo = GEN_GDT_DESC_LO((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); + desc_up = GEN_GDT_DESC_UP((uint32_t)&main_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); add_gdt_entry(desc_lo, desc_up); /* set GDT entry 4 for TSS descriptor of aontask * limit: 0x67 * Present = 1, DPL = 0, Accessed = 1 */ - desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); - desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, - GDT_DESC_TSS_LIMIT, GDT_DESC_TSS_FLAGS); + desc_lo = GEN_GDT_DESC_LO((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); + desc_up = GEN_GDT_DESC_UP((uint32_t)aon_tss, GDT_DESC_TSS_LIMIT, + GDT_DESC_TSS_FLAGS); pm_ctx.aon_tss_selector[1] = add_gdt_entry(desc_lo, desc_up); /* set GDT entry 5 for LDT descriptor of aontask @@ -205,12 +205,12 @@ static void init_aon_task(void) "pop %eax;"); aon_share->main_fw_ro_addr = (uint32_t)&__aon_ro_start; - aon_share->main_fw_ro_size = (uint32_t)&__aon_ro_end - - (uint32_t)&__aon_ro_start; + aon_share->main_fw_ro_size = + (uint32_t)&__aon_ro_end - (uint32_t)&__aon_ro_start; aon_share->main_fw_rw_addr = (uint32_t)&__aon_rw_start; - aon_share->main_fw_rw_size = (uint32_t)&__aon_rw_end - - (uint32_t)&__aon_rw_start; + aon_share->main_fw_rw_size = + (uint32_t)&__aon_rw_end - (uint32_t)&__aon_rw_start; aon_share->uma_msb = IPC_UMA_RANGE_LOWER_1; @@ -258,8 +258,7 @@ static void switch_to_aontask(void) interrupt_enable(); } -noreturn -static void handle_reset_in_aontask(enum ish_pm_state pm_state) +noreturn static void handle_reset_in_aontask(enum ish_pm_state pm_state) { pm_ctx.aon_share->pm_state = pm_state; @@ -318,10 +317,8 @@ static uint32_t convert_both_edge_gpio_to_single_edge(void) * interrupt trigger mode enabled pins. */ for (i = 0; i < 32; i++) { - if (ISH_GPIO_GIMR & BIT(i) && - ISH_GPIO_GRER & BIT(i) && + if (ISH_GPIO_GIMR & BIT(i) && ISH_GPIO_GRER & BIT(i) && ISH_GPIO_GFER & BIT(i)) { - /* Record the pin so we can restore it later */ both_edge_pins |= BIT(i); @@ -513,7 +510,6 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us) int pm_state = ISH_PM_STATE_D0I0; if (DEEP_SLEEP_ALLOWED) { - /* check if the console use has expired. */ if (sleep_mask & SLEEP_MASK_CONSOLE) { if (cur_time.val > pm_ctx.console_expire_time.val) { @@ -525,8 +521,7 @@ static int d0ix_decide(timestamp_t cur_time, uint32_t idle_us) } if (IS_ENABLED(CONFIG_ISH_PM_D0I3) && - idle_us >= CONFIG_ISH_D0I3_MIN_USEC && - pm_ctx.aon_valid) + idle_us >= CONFIG_ISH_D0I3_MIN_USEC && pm_ctx.aon_valid) pm_state = ISH_PM_STATE_D0I3; else if (IS_ENABLED(CONFIG_ISH_PM_D0I2) && @@ -633,7 +628,8 @@ void ish_pm_init(void) PMU_MASK_EVENT = ~PMU_MASK_EVENT_BIT_ALL; if (IS_ENABLED(CONFIG_ISH_NEW_PM)) { - PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | FABRIC_IDLE_COUNT; + PMU_ISH_FABRIC_CNT = (PMU_ISH_FABRIC_CNT & 0xffff0000) | + FABRIC_IDLE_COUNT; PMU_PGCB_CLKGATE_CTRL = TRUNK_CLKGATE_COUNT; } @@ -656,11 +652,9 @@ void ish_pm_init(void) } } -noreturn -void ish_pm_reset(enum ish_pm_state pm_state) +noreturn void ish_pm_reset(enum ish_pm_state pm_state) { - if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && - pm_ctx.aon_valid) { + if (IS_ENABLED(CONFIG_ISH_PM_AONTASK) && pm_ctx.aon_valid) { handle_reset_in_aontask(pm_state); } else { ish_mia_reset(); @@ -679,8 +673,8 @@ void __idle(void) * time in order to give a fixed window on boot */ disable_sleep(SLEEP_MASK_CONSOLE); - pm_ctx.console_expire_time.val = get_time().val + - CONSOLE_IN_USE_ON_BOOT_TIME; + pm_ctx.console_expire_time.val = + get_time().val + CONSOLE_IN_USE_ON_BOOT_TIME; while (1) { t0 = get_time(); @@ -742,13 +736,11 @@ static int command_idle_stats(int argc, char **argv) DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", "Print power management statistics"); - /** * main FW only need handle PMU wakeup interrupt for D0i1 state, aontask will * handle PMU wakeup interrupt for other low power states */ -__maybe_unused -static void pmu_wakeup_isr(void) +__maybe_unused static void pmu_wakeup_isr(void) { /* at current nothing need to do */ } @@ -763,8 +755,7 @@ DECLARE_IRQ(ISH_PMU_WAKEUP_IRQ, pmu_wakeup_isr); * */ -__maybe_unused noreturn -static void reset_prep_isr(void) +__maybe_unused noreturn static void reset_prep_isr(void) { /* mask reset prep avail interrupt */ PMU_RST_PREP = PMU_RST_PREP_INT_MASK; @@ -784,8 +775,7 @@ static void reset_prep_isr(void) DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_isr); #endif -__maybe_unused -static void handle_d3(uint32_t irq_vec) +__maybe_unused static void handle_d3(uint32_t irq_vec) { PMU_D3_STATUS = PMU_D3_STATUS; @@ -839,5 +829,5 @@ void ish_pm_refresh_console_in_use(void) /* Set console in use expire time. */ pm_ctx.console_expire_time = get_time(); pm_ctx.console_expire_time.val += - pm_ctx.console_in_use_timeout_sec * SECOND; + pm_ctx.console_in_use_timeout_sec * SECOND; } -- cgit v1.2.1 From 2b5d7746f20d73496f352cc8bc3b8637c068026d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:29:31 -0600 Subject: chip/stm32/host_command_common.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11c8e8c5eeab52d0984835d28d29ac689118e4f7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729511 Reviewed-by: Jeremy Bettis --- chip/stm32/host_command_common.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/stm32/host_command_common.c b/chip/stm32/host_command_common.c index b39a298c64..faa866da25 100644 --- a/chip/stm32/host_command_common.c +++ b/chip/stm32/host_command_common.c @@ -17,8 +17,8 @@ static enum fp_transport_type curr_transport_type = FP_TRANSPORT_TYPE_UNKNOWN; /* * Get protocol information */ -static enum ec_status host_command_protocol_info(struct host_cmd_handler_args - *args) +static enum ec_status +host_command_protocol_info(struct host_cmd_handler_args *args) { enum ec_status ret_status = EC_RES_INVALID_COMMAND; @@ -39,8 +39,7 @@ static enum ec_status host_command_protocol_info(struct host_cmd_handler_args return ret_status; } -DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, - host_command_protocol_info, +DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, host_command_protocol_info, EC_VER_MASK(0)); #endif /* CONFIG_I2C_PERIPHERAL */ -- cgit v1.2.1 From eb37337205d15f2f1c15357277a43e8b32133708 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:30:18 -0600 Subject: chip/stm32/registers-stm32f7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I526397c1a4b504f06e63523b9fca9adf0cd8997d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729530 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f7.h | 1591 ++++++++++++++++++++-------------------- 1 file changed, 789 insertions(+), 802 deletions(-) diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h index 7c039c9d61..59fc3228a4 100644 --- a/chip/stm32/registers-stm32f7.h +++ b/chip/stm32/registers-stm32f7.h @@ -19,100 +19,99 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -123,464 +122,461 @@ * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012000 -#define STM32_ADC_BASE 0x40012300 - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 - - -#define STM32_DBGMCU_BASE 0xE0042000 - -#define STM32_DMA1_BASE 0x40026000 -#define STM32_DMA2_BASE 0x40026400 - -#define STM32_EXTI_BASE 0x40013C00 - -#define STM32_FLASH_REGS_BASE 0x40023c00 - -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ -#define STM32_GPIOG_BASE 0x40021800 -#define STM32_GPIOH_BASE 0x40021C00 - -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 - -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 - -#define STM32_OPTB_BASE 0x1FFFC000 -#define STM32_OTP_BASE 0x1FFF7800 - -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 - -#define STM32_RCC_BASE 0x40023800 - -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ - -#define STM32_SYSCFG_BASE 0x40013800 - -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ -#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ -#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ - -#define STM32_UNIQUE_ID_BASE 0x1fff7a10 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 - -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 - -#define STM32_WWDG_BASE 0x40002C00 - +#define STM32_ADC1_BASE 0x40012000 +#define STM32_ADC_BASE 0x40012300 + +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 + +#define STM32_DBGMCU_BASE 0xE0042000 + +#define STM32_DMA1_BASE 0x40026000 +#define STM32_DMA2_BASE 0x40026400 + +#define STM32_EXTI_BASE 0x40013C00 + +#define STM32_FLASH_REGS_BASE 0x40023c00 + +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021400 /* see RM0402/0390 table 1 */ +#define STM32_GPIOG_BASE 0x40021800 +#define STM32_GPIOH_BASE 0x40021C00 + +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 + +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 + +#define STM32_OPTB_BASE 0x1FFFC000 +#define STM32_OTP_BASE 0x1FFF7800 + +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 + +#define STM32_RCC_BASE 0x40023800 + +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ + +#define STM32_SYSCFG_BASE 0x40013800 + +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40014000 /* STM32F41x only */ +#define STM32_TIM10_BASE 0x40014400 /* STM32F41x only */ +#define STM32_TIM11_BASE 0x40014800 /* STM32F41x only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ + +#define STM32_UNIQUE_ID_BASE 0x1fff7a10 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 + +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 + +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - -#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) -#define FMPI2C_CR1_PE BIT(0) -#define FMPI2C_CR1_TXDMAEN BIT(14) -#define FMPI2C_CR1_RXDMAEN BIT(15) -#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) -#define FMPI2C_CR2_RD_WRN BIT(10) -#define FMPI2C_READ 1 -#define FMPI2C_WRITE 0 -#define FMPI2C_CR2_START BIT(13) -#define FMPI2C_CR2_STOP BIT(14) -#define FMPI2C_CR2_NACK BIT(15) -#define FMPI2C_CR2_RELOAD BIT(24) -#define FMPI2C_CR2_AUTOEND BIT(25) -#define FMPI2C_CR2_SADD(addr) ((addr) & 0x3ff) -#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) -#define FMPI2C_CR2_SIZE(size) (((size) & 0xff) << 16) -#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) -#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) -#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) -#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) -#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 -#define FMPI2C_TIMINGR_PRESC(val) (((val) & 0xf) << 28) -#define FMPI2C_TIMINGR_SCLDEL(val) (((val) & 0xf) << 20) -#define FMPI2C_TIMINGR_SDADEL(val) (((val) & 0xf) << 16) -#define FMPI2C_TIMINGR_SCLH(val) (((val) & 0xff) << 8) -#define FMPI2C_TIMINGR_SCLL(val) (((val) & 0xff) << 0) -#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) - -#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) -#define FMPI2C_ISR_TXE BIT(0) -#define FMPI2C_ISR_TXIS BIT(1) -#define FMPI2C_ISR_RXNE BIT(2) -#define FMPI2C_ISR_ADDR BIT(3) -#define FMPI2C_ISR_NACKF BIT(4) -#define FMPI2C_ISR_STOPF BIT(5) -#define FMPI2C_ISR_BERR BIT(8) -#define FMPI2C_ISR_ARLO BIT(9) -#define FMPI2C_ISR_BUSY BIT(15) -#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) - -#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) -#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) -#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) + +#define STM32_FMPI2C_CR1(n) REG32(stm32_i2c_reg(n, 0x00)) +#define FMPI2C_CR1_PE BIT(0) +#define FMPI2C_CR1_TXDMAEN BIT(14) +#define FMPI2C_CR1_RXDMAEN BIT(15) +#define STM32_FMPI2C_CR2(n) REG32(stm32_i2c_reg(n, 0x04)) +#define FMPI2C_CR2_RD_WRN BIT(10) +#define FMPI2C_READ 1 +#define FMPI2C_WRITE 0 +#define FMPI2C_CR2_START BIT(13) +#define FMPI2C_CR2_STOP BIT(14) +#define FMPI2C_CR2_NACK BIT(15) +#define FMPI2C_CR2_RELOAD BIT(24) +#define FMPI2C_CR2_AUTOEND BIT(25) +#define FMPI2C_CR2_SADD(addr) ((addr)&0x3ff) +#define FMPI2C_CR2_SADD_MASK FMPI2C_CR2_SADD(0x3ff) +#define FMPI2C_CR2_SIZE(size) (((size)&0xff) << 16) +#define FMPI2C_CR2_SIZE_MASK FMPI2C_CR2_SIZE(0xf) +#define STM32_FMPI2C_OAR1(n) REG32(stm32_i2c_reg(n, 0x08)) +#define STM32_FMPI2C_OAR2(n) REG32(stm32_i2c_reg(n, 0x0C)) +#define STM32_FMPI2C_TIMINGR(n) REG32(stm32_i2c_reg(n, 0x10)) +#define TIMINGR_THE_RIGHT_VALUE 0xC0000E12 +#define FMPI2C_TIMINGR_PRESC(val) (((val)&0xf) << 28) +#define FMPI2C_TIMINGR_SCLDEL(val) (((val)&0xf) << 20) +#define FMPI2C_TIMINGR_SDADEL(val) (((val)&0xf) << 16) +#define FMPI2C_TIMINGR_SCLH(val) (((val)&0xff) << 8) +#define FMPI2C_TIMINGR_SCLL(val) (((val)&0xff) << 0) +#define STM32_FMPI2C_TIMEOUTR(n) REG32(stm32_i2c_reg(n, 0x14)) + +#define STM32_FMPI2C_ISR(n) REG32(stm32_i2c_reg(n, 0x18)) +#define FMPI2C_ISR_TXE BIT(0) +#define FMPI2C_ISR_TXIS BIT(1) +#define FMPI2C_ISR_RXNE BIT(2) +#define FMPI2C_ISR_ADDR BIT(3) +#define FMPI2C_ISR_NACKF BIT(4) +#define FMPI2C_ISR_STOPF BIT(5) +#define FMPI2C_ISR_BERR BIT(8) +#define FMPI2C_ISR_ARLO BIT(9) +#define FMPI2C_ISR_BUSY BIT(15) +#define STM32_FMPI2C_ICR(n) REG32(stm32_i2c_reg(n, 0x1C)) + +#define STM32_FMPI2C_PECR(n) REG32(stm32_i2c_reg(n, 0x20)) +#define STM32_FMPI2C_RXDR(n) REG32(stm32_i2c_reg(n, 0x24)) +#define STM32_FMPI2C_TXDR(n) REG32(stm32_i2c_reg(n, 0x28)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) #ifdef CHIP_VARIANT_STM32F76X /* Required or recommended clocks for stm32f767/769 */ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI */ +#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 #define STM32F4_TIMER_CLOCK (STM32F4_IO_CLOCK * 2) -#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ -#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ +#define STM32F4_PLLP_DIV 2 /* sys = VCO/2 = 180 Mhz */ +#define STM32F4_AHB_PRE 0x0 /* AHB = sysclk = 180 Mhz */ #define STM32F4_APB1_PRE 0x5 /* APB1 = AHB /4 = 45 Mhz */ #define STM32F4_APB2_PRE 0x5 /* APB2 = AHB /4 = 45 Mhz */ -#define STM32_FLASH_ACR_LATENCY (5 << 0) +#define STM32_FLASH_ACR_LATENCY (5 << 0) #else #error "No valid clocks defined" #endif -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04) /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 0 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 0 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 6 -#define PLLCFGR_PLLN(val) (((val) & 0x1ff) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLN_OFF 6 +#define PLLCFGR_PLLN(val) (((val)&0x1ff) << PLLCFGR_PLLN_OFF) /* Main CPU Clock */ -#define PLLCFGR_PLLP_OFF 16 -#define PLLCFGR_PLLP(val) (((val) & 0x3) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLP_OFF 16 +#define PLLCFGR_PLLP(val) (((val)&0x3) << PLLCFGR_PLLP_OFF) -#define PLLCFGR_PLLSRC_HSI (0 << 22) -#define PLLCFGR_PLLSRC_HSE BIT(22) +#define PLLCFGR_PLLSRC_HSI (0 << 22) +#define PLLCFGR_PLLSRC_HSE BIT(22) /* USB OTG FS: Must equal 48MHz */ -#define PLLCFGR_PLLQ_OFF 24 -#define PLLCFGR_PLLQ(val) (((val) & 0xf) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLQ_OFF 24 +#define PLLCFGR_PLLQ(val) (((val)&0xf) << PLLCFGR_PLLQ_OFF) /* SYSTEM */ -#define PLLCFGR_PLLR_OFF 28 -#define PLLCFGR_PLLR(val) (((val) & 0x7) << PLLCFGR_PLLR_OFF) - -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSE (1 << 0) -#define STM32_RCC_CFGR_SW_PLL (2 << 0) -#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSE (1 << 2) -#define STM32_RCC_CFGR_SWS_PLL (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define PLLCFGR_PLLR_OFF 28 +#define PLLCFGR_PLLR(val) (((val)&0x7) << PLLCFGR_PLLR_OFF) + +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSE (1 << 0) +#define STM32_RCC_CFGR_SW_PLL (2 << 0) +#define STM32_RCC_CFGR_SW_PLL_R (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSE (1 << 2) +#define STM32_RCC_CFGR_SWS_PLL (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL_R (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: nonlinear values, look up in RM0390 */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 10 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 10 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 13 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 13 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) -#define RCC_AHB1RSTR_OTGHSRST BIT(29) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x10) +#define RCC_AHB1RSTR_OTGHSRST BIT(29) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) -#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) -#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_AHB1ENR_GPIOMASK (0xff << 0) +#define STM32_RCC_AHB1ENR_BKPSRAMEN BIT(18) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(21) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(22) /* TODO(nsanders): normalize naming.*/ -#define STM32_RCC_HB1_DMA1 BIT(21) -#define STM32_RCC_HB1_DMA2 BIT(22) -#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) -#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) - -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_PWREN BIT(28) -#define STM32_RCC_I2C1EN BIT(21) -#define STM32_RCC_I2C2EN BIT(22) -#define STM32_RCC_I2C3EN BIT(23) -#define STM32_RCC_FMPI2C4EN BIT(24) - -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) -#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ - -#define STM32_RCC_PB2_USART6 BIT(5) -#define STM32_RCC_SYSCFGEN BIT(14) - -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) - -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_RCC_PB2_TIM9 BIT(16) -#define STM32_RCC_PB2_TIM10 BIT(17) -#define STM32_RCC_PB2_TIM11 BIT(18) - -#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) -#define DCKCFGR2_FMPI2C1SEL(val) (((val) & 0x3) << 22) -#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) -#define FMPI2C1SEL_APB 0x0 - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) - +#define STM32_RCC_HB1_DMA1 BIT(21) +#define STM32_RCC_HB1_DMA2 BIT(22) +#define STM32_RCC_AHB1ENR_OTGHSEN BIT(29) +#define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) + +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_PWREN BIT(28) +#define STM32_RCC_I2C1EN BIT(21) +#define STM32_RCC_I2C2EN BIT(22) +#define STM32_RCC_I2C3EN BIT(23) +#define STM32_RCC_FMPI2C4EN BIT(24) + +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x44) +#define STM32_RCC_APB2ENR_ADC1EN BIT(8) /* STM32F4 */ + +#define STM32_RCC_PB2_USART6 BIT(5) +#define STM32_RCC_SYSCFGEN BIT(14) + +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x54) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x64) + +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x74) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_RCC_PB2_TIM9 BIT(16) +#define STM32_RCC_PB2_TIM10 BIT(17) +#define STM32_RCC_PB2_TIM11 BIT(18) + +#define STM32_RCC_DCKCFGR2 REG32(STM32_RCC_BASE + 0x94) +#define DCKCFGR2_FMPI2C1SEL(val) (((val)&0x3) << 22) +#define DCKCFGR2_FMPI2C1SEL_MASK (0x3 << 22) +#define FMPI2C1SEL_APB 0x0 + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -597,8 +593,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -608,146 +604,142 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_SHIFT 0 -#define STM32_FLASH_ACR_LAT_MASK 0xf -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) -#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define FLASH_SR_EOP BIT(0) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_PGPERR BIT(6) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_RDERR BIT(8) -#define FLASH_SR_ALL_ERR \ +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_SHIFT 0 +#define STM32_FLASH_ACR_LAT_MASK 0xf +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define FLASH_SR_EOP BIT(0) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_PGPERR BIT(6) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_RDERR BIT(8) +#define FLASH_SR_ALL_ERR \ (FLASH_SR_OPERR | FLASH_SR_WRPERR | FLASH_SR_PGAERR | \ FLASH_SR_PGPERR | FLASH_SR_PGSERR | FLASH_SR_RDERR) -#define FLASH_SR_BUSY BIT(16) -#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_MER BIT(2) -#define STM32_FLASH_CR_SNB_OFFSET (3) -#define STM32_FLASH_CR_SNB(sec) \ - (((sec) & 0xf) << STM32_FLASH_CR_SNB_OFFSET) -#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) -#define STM32_FLASH_CR_PSIZE_OFFSET (8) -#define STM32_FLASH_CR_PSIZE(size) \ - (((size) & 0x3) << STM32_FLASH_CR_PSIZE_OFFSET) -#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_LOCK BIT(31) -#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define FLASH_OPTLOCK BIT(0) -#define FLASH_OPTSTRT BIT(1) -#define STM32_FLASH_BOR_LEV_OFFSET (2) -#define STM32_FLASH_RDP_MASK (0xFF << 8) -#define STM32_FLASH_nWRP_OFFSET (16) -#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) -#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) - -#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) -#define STM32_OPTB_RDP_OFF 0x00 -#define STM32_OPTB_USER_OFF 0x02 -#define STM32_OPTB_WRP_OFF(n) (0x08 + (n&3) * 2) -#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) -#define STM32_OPTB_nWRP(_bank) BIT(_bank) -#define STM32_OPTB_nWRP_ALL (0xFF) - -#define STM32_OPTB_COMPL_SHIFT 8 - -#define STM32_OTP_BLOCK_NB 16 -#define STM32_OTP_BLOCK_SIZE 32 +#define FLASH_SR_BUSY BIT(16) +#define STM32_FLASH_CR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_MER BIT(2) +#define STM32_FLASH_CR_SNB_OFFSET (3) +#define STM32_FLASH_CR_SNB(sec) (((sec)&0xf) << STM32_FLASH_CR_SNB_OFFSET) +#define STM32_FLASH_CR_SNB_MASK (STM32_FLASH_CR_SNB(0xf)) +#define STM32_FLASH_CR_PSIZE_OFFSET (8) +#define STM32_FLASH_CR_PSIZE(size) (((size)&0x3) << STM32_FLASH_CR_PSIZE_OFFSET) +#define STM32_FLASH_CR_PSIZE_MASK (STM32_FLASH_CR_PSIZE(0x3)) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_LOCK BIT(31) +#define STM32_FLASH_OPTCR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define FLASH_OPTLOCK BIT(0) +#define FLASH_OPTSTRT BIT(1) +#define STM32_FLASH_BOR_LEV_OFFSET (2) +#define STM32_FLASH_RDP_MASK (0xFF << 8) +#define STM32_FLASH_nWRP_OFFSET (16) +#define STM32_FLASH_nWRP(_bank) BIT(_bank + STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_nWRP_ALL (0xFF << STM32_FLASH_nWRP_OFFSET) +#define STM32_FLASH_OPT_LOCKED (STM32_FLASH_OPTCR & FLASH_OPTLOCK) + +#define STM32_OPTB_RDP_USER REG32(STM32_OPTB_BASE + 0x00) +#define STM32_OPTB_RDP_OFF 0x00 +#define STM32_OPTB_USER_OFF 0x02 +#define STM32_OPTB_WRP_OFF(n) (0x08 + (n & 3) * 2) +#define STM32_OPTB_WP REG32(STM32_OPTB_BASE + 0x08) +#define STM32_OPTB_nWRP(_bank) BIT(_bank) +#define STM32_OPTB_nWRP_ALL (0xFF) + +#define STM32_OPTB_COMPL_SHIFT 8 + +#define STM32_OTP_BLOCK_NB 16 +#define STM32_OTP_BLOCK_SIZE 32 #define STM32_OTP_BLOCK_DATA(_block, _offset) \ - (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset) * 4) -#define STM32_OTP_UNLOCK_BYTE 0x00 -#define STM32_OTP_LOCK_BYTE 0xFF -#define STM32_OTP_LOCK_BASE \ + (STM32_OTP_BASE + STM32_OTP_BLOCK_SIZE * (_block) + (_offset)*4) +#define STM32_OTP_UNLOCK_BYTE 0x00 +#define STM32_OTP_LOCK_BYTE 0xFF +#define STM32_OTP_LOCK_BASE \ (STM32_OTP_BASE + STM32_OTP_BLOCK_NB * STM32_OTP_BLOCK_SIZE) -#define STM32_OTP_LOCK(_block) \ - (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) -#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) +#define STM32_OTP_LOCK(_block) (STM32_OTP_LOCK_BASE + ((_block) / 4) * 4) +#define STM32_OPT_LOCK_MASK(_block) ((0xFF << ((_block) % 4) * 8)) /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CR2_ADON BIT(0) -#define STM32_ADC_CR2_CONT BIT(1) -#define STM32_ADC_CR2_CAL BIT(2) -#define STM32_ADC_CR2_RSTCAL BIT(3) -#define STM32_ADC_CR2_ALIGN BIT(11) -#define STM32_ADC_CR2_SWSTART BIT(30) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CR2_ADON BIT(0) +#define STM32_ADC_CR2_CONT BIT(1) +#define STM32_ADC_CR2_CAL BIT(2) +#define STM32_ADC_CR2_RSTCAL BIT(3) +#define STM32_ADC_CR2_ALIGN BIT(11) +#define STM32_ADC_CR2_SWSTART BIT(30) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x28 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -838,12 +830,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -852,12 +844,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -868,184 +859,181 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) - - -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0x7 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) ((channel) << 25) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) + +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) +#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) + +#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) + +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) + +#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) + +#define STM32_USB_ISTR_EP_ID_MASK (0x000f) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) + +#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) + +#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) +#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) +#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) +#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) + +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -1055,28 +1043,27 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From b45791df941d4e1257d495f281da9078e924c64a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:46 -0600 Subject: board/eldrid/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I66785e212c4af191dbe22455729d49b15f75e5c0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728308 Reviewed-by: Jeremy Bettis --- board/eldrid/thermal.c | 56 ++++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/board/eldrid/thermal.c b/board/eldrid/thermal.c index 3f20b16d70..e78cf7dd47 100644 --- a/board/eldrid/thermal.c +++ b/board/eldrid/thermal.c @@ -15,8 +15,7 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) - +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) /******************************************************************************/ /* EC thermal management configuration */ @@ -30,8 +29,8 @@ /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -56,8 +55,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_INDUCTOR \ - { \ +#define THERMAL_INDUCTOR \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -102,39 +101,39 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {-1, -1, 44, -1}, - .off = {-1, -1, 0, -1}, - .rpm = {0}, + .on = { -1, -1, 44, -1 }, + .off = { -1, -1, 0, -1 }, + .rpm = { 0 }, }, { /* level 1 */ - .on = {-1, -1, 46, -1}, - .off = {-1, -1, 44, -1}, - .rpm = {3200}, + .on = { -1, -1, 46, -1 }, + .off = { -1, -1, 44, -1 }, + .rpm = { 3200 }, }, { /* level 2 */ - .on = {-1, -1, 50, -1}, - .off = {-1, -1, 45, -1}, - .rpm = {3600}, + .on = { -1, -1, 50, -1 }, + .off = { -1, -1, 45, -1 }, + .rpm = { 3600 }, }, { /* level 3 */ - .on = {-1, -1, 54, -1}, - .off = {-1, -1, 49, -1}, - .rpm = {4100}, + .on = { -1, -1, 54, -1 }, + .off = { -1, -1, 49, -1 }, + .rpm = { 4100 }, }, { /* level 4 */ - .on = {-1, -1, 58, -1}, - .off = {-1, -1, 53, -1}, - .rpm = {4900}, + .on = { -1, -1, 58, -1 }, + .off = { -1, -1, 53, -1 }, + .rpm = { 4900 }, }, { /* level 5 */ - .on = {-1, -1, 60, -1}, - .off = {-1, -1, 57, -1}, - .rpm = {5200}, + .on = { -1, -1, 60, -1 }, + .off = { -1, -1, 57, -1 }, + .rpm = { 5200 }, }, }; @@ -162,16 +161,16 @@ int fan_table_to_rpm(int fan, int *temp) if (temp[TEMP_SENSOR_3_DDR_SOC] < prev_temp[TEMP_SENSOR_3_DDR_SOC]) { for (i = current_level; i > 0; i--) { if (temp[TEMP_SENSOR_3_DDR_SOC] < - fan_table[i].off[TEMP_SENSOR_3_DDR_SOC]) + fan_table[i].off[TEMP_SENSOR_3_DDR_SOC]) current_level = i - 1; else break; } } else if (temp[TEMP_SENSOR_3_DDR_SOC] > - prev_temp[TEMP_SENSOR_3_DDR_SOC]) { + prev_temp[TEMP_SENSOR_3_DDR_SOC]) { for (i = current_level; i < num_fan_levels; i++) { if (temp[TEMP_SENSOR_3_DDR_SOC] > - fan_table[i].on[TEMP_SENSOR_3_DDR_SOC]) + fan_table[i].on[TEMP_SENSOR_3_DDR_SOC]) current_level = i; else break; @@ -207,8 +206,7 @@ void board_override_fan_control(int fan, int *temp) { if (chipset_in_state(CHIPSET_STATE_ON)) { fan_set_rpm_mode(FAN_CH(fan), 1); - fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(fan, temp)); + fan_set_rpm_target(FAN_CH(fan), fan_table_to_rpm(fan, temp)); } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Stop fan when enter S0ix */ fan_set_rpm_mode(FAN_CH(fan), 1); -- cgit v1.2.1 From 9608ffb38e303edc43fd3843dea8c999d372be85 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:15:29 -0600 Subject: chip/ish/heci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id9fe634ee955eec5c220eb2c406e7e8ec38c3665 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729177 Reviewed-by: Jeremy Bettis --- chip/ish/heci.c | 106 +++++++++++++++++++++++++++++--------------------------- 1 file changed, 54 insertions(+), 52 deletions(-) diff --git a/chip/ish/heci.c b/chip/ish/heci.c index 4a9bc9551b..6adcece752 100644 --- a/chip/ish/heci.c +++ b/chip/ish/heci.c @@ -15,19 +15,19 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_LPC, outstr) -#define CPRINTS(format, args...) cprints(CC_LPC, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_LPC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_LPC, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_LPC, format, ##args) struct heci_header { uint8_t fw_addr; uint8_t host_addr; uint16_t length; /* [8:0] length, [14:9] reserved, [15] msg_complete */ } __packed; -#define HECI_MSG_CMPL_SHIFT 15 -#define HECI_MSG_LENGTH_MASK 0x01FF -#define HECI_MSG_LENGTH(length) ((length) & HECI_MSG_LENGTH_MASK) +#define HECI_MSG_CMPL_SHIFT 15 +#define HECI_MSG_LENGTH_MASK 0x01FF +#define HECI_MSG_LENGTH(length) ((length)&HECI_MSG_LENGTH_MASK) #define HECI_MSG_IS_COMPLETED(length) \ - (!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT))) + (!!((length) & (0x01 << HECI_MSG_CMPL_SHIFT))) BUILD_ASSERT(HECI_IPC_PAYLOAD_SIZE == (IPC_MAX_PAYLOAD_SIZE - sizeof(struct heci_header))); @@ -38,26 +38,26 @@ struct heci_msg { } __packed; /* HECI addresses */ -#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */ -#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */ +#define HECI_HBM_ADDRESS 0 /* HECI Bus Message */ +#define HECI_DYN_CLIENT_ADDR_START 0x20 /* Dynamic client start addr */ /* A fw client has the same value for both handle and fw address */ -#define TO_FW_ADDR(handle) ((uintptr_t)(handle)) -#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr)) +#define TO_FW_ADDR(handle) ((uintptr_t)(handle)) +#define TO_HECI_HANDLE(fw_addr) ((heci_handle_t)(uintptr_t)(fw_addr)) /* convert client fw address to client context index */ -#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr) - HECI_DYN_CLIENT_ADDR_START) +#define TO_CLIENT_CTX_IDX(fw_addr) ((fw_addr)-HECI_DYN_CLIENT_ADDR_START) /* should be less than HECI_INVALID_HANDLE - 1 */ BUILD_ASSERT(HECI_MAX_NUM_OF_CLIENTS < 0x0FE); struct heci_client_connect { - uint8_t is_connected; /* client is connected to host */ - uint8_t host_addr; /* connected host address */ + uint8_t is_connected; /* client is connected to host */ + uint8_t host_addr; /* connected host address */ /* receiving message */ uint8_t ignore_rx_msg; - uint8_t rx_msg[HECI_MAX_MSG_SIZE]; - size_t rx_msg_length; + uint8_t rx_msg[HECI_MAX_MSG_SIZE]; + size_t rx_msg_length; uint32_t flow_ctrl_creds; /* flow control */ struct mutex lock; /* protects against 2 writers */ @@ -67,7 +67,7 @@ struct heci_client_connect { struct heci_client_context { const struct heci_client *client; - void *data; /* client specific data */ + void *data; /* client specific data */ struct heci_client_connect connect; /* connection context */ struct ss_subsys_device ss_device; /* system state receiver device */ @@ -82,7 +82,7 @@ struct heci_bus_context { /* declare heci bus */ struct heci_bus_context heci_bus_ctx = { - .ipc_handle = IPC_INVALID_HANDLE, + .ipc_handle = IPC_INVALID_HANDLE, }; static inline struct heci_client_context * @@ -118,11 +118,14 @@ static inline int heci_is_valid_handle(const heci_handle_t handle) /* find heci device that contains this system state device in it */ #define ss_device_to_heci_client_context(ss_dev) \ - ((struct heci_client_context *)((void *)(ss_dev) - \ - (void *)(&(((struct heci_client_context *)0)->ss_device)))) -#define client_context_to_handle(cli_ctx) \ - ((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) \ - / sizeof(heci_bus_ctx.client_ctxs[0]) + 1)) + ((struct heci_client_context \ + *)((void *)(ss_dev) - \ + (void *)(&( \ + ((struct heci_client_context *)0)->ss_device)))) +#define client_context_to_handle(cli_ctx) \ + ((heci_handle_t)((uint32_t)((cli_ctx) - &heci_bus_ctx.client_ctxs[0]) / \ + sizeof(heci_bus_ctx.client_ctxs[0]) + \ + 1)) /* * each heci device registered as system state device which gets @@ -132,7 +135,7 @@ static inline int heci_is_valid_handle(const heci_handle_t handle) static int heci_client_suspend(struct ss_subsys_device *ss_device) { struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); + ss_device_to_heci_client_context(ss_device); heci_handle_t handle = client_context_to_handle(cli_ctx); if (cli_ctx->client->cbs->suspend) @@ -144,7 +147,7 @@ static int heci_client_suspend(struct ss_subsys_device *ss_device) static int heci_client_resume(struct ss_subsys_device *ss_device) { struct heci_client_context *cli_ctx = - ss_device_to_heci_client_context(ss_device); + ss_device_to_heci_client_context(ss_device); heci_handle_t handle = client_context_to_handle(cli_ctx); if (cli_ctx->client->cbs->resume) @@ -239,8 +242,8 @@ static int heci_send_heci_msg_timestamp(struct heci_msg *msg, timestamp); if (written != length) { - CPRINTF("%s error : len = %d err = %d\n", __func__, - (int)length, written); + CPRINTF("%s error : len = %d err = %d\n", __func__, (int)length, + written); return -EC_ERROR_UNKNOWN; } @@ -381,7 +384,6 @@ int heci_send_msg(const heci_handle_t handle, uint8_t *buf, return heci_send_msg_timestamp(handle, buf, buf_size, NULL); } - int heci_send_msgs(const heci_handle_t handle, const struct heci_msg_list *msg_list) { @@ -453,8 +455,8 @@ int heci_send_msgs(const heci_handle_t handle, /* no leftovers, send the last msg here */ if (msg_sent == total_size) { - msg.hdr.length |= - (uint16_t)1 << HECI_MSG_CMPL_SHIFT; + msg.hdr.length |= (uint16_t)1 + << HECI_MSG_CMPL_SHIFT; } heci_send_heci_msg(&msg); @@ -488,7 +490,6 @@ err_locked: mutex_unlock(&connect->lock); return total_size; - } /* For now, we only support fixed client payload size < IPC payload size */ @@ -535,9 +536,9 @@ static int handle_version_req(struct hbm_version_req *ver_req) return EC_SUCCESS; } -#define BITS_PER_BYTE 8 +#define BITS_PER_BYTE 8 /* get number of bits for one element of "valid_addresses" array */ -#define BITS_PER_ELEMENT \ +#define BITS_PER_ELEMENT \ (sizeof(((struct hbm_enum_res *)0)->valid_addresses[0]) * BITS_PER_BYTE) static int handle_enum_req(struct hbm_enum_req *enum_req) @@ -604,11 +605,11 @@ static int handle_client_prop_req(struct hbm_client_prop_req *client_prop_req) client_prop->protocol_name = client->protocol_id; client_prop->protocol_version = client->protocol_ver; client_prop->max_number_of_connections = - client->max_n_of_connections; + client->max_n_of_connections; client_prop->max_msg_length = client->max_msg_size; client_prop->dma_hdr_len = client->dma_header_length; - client_prop->dma_hdr_len |= client->dma_enabled ? - CLIENT_DMA_ENABLE : 0; + client_prop->dma_hdr_len |= + client->dma_enabled ? CLIENT_DMA_ENABLE : 0; } heci_send_heci_msg(&heci_msg); @@ -642,8 +643,8 @@ static int heci_send_flow_control(uint8_t fw_addr) return EC_SUCCESS; } -static int handle_client_connect_req( - struct hbm_client_connect_req *client_connect_req) +static int +handle_client_connect_req(struct hbm_client_connect_req *client_connect_req) { struct hbm_client_connect_res *client_connect_res; struct heci_msg heci_msg; @@ -663,7 +664,7 @@ static int handle_client_connect_req( client_connect_res->host_addr = client_connect_req->host_addr; if (!heci_is_valid_client_addr(client_connect_req->fw_addr)) { client_connect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; } else if (!client_connect_req->host_addr) { client_connect_res->status = HECI_CONNECT_STATUS_INVALID_PARAMETER; @@ -671,7 +672,7 @@ static int handle_client_connect_req( connect = heci_get_client_connect(client_connect_req->fw_addr); if (connect->is_connected) { client_connect_res->status = - HECI_CONNECT_STATUS_ALREADY_EXISTS; + HECI_CONNECT_STATUS_ALREADY_EXISTS; } else { connect->is_connected = 1; connect->host_addr = client_connect_req->host_addr; @@ -729,8 +730,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length) connect = &cli_ctx->connect; payload_size = HECI_MSG_LENGTH(msg->hdr.length); - if (connect->is_connected && - msg->hdr.host_addr == connect->host_addr) { + if (connect->is_connected && msg->hdr.host_addr == connect->host_addr) { if (!connect->ignore_rx_msg && connect->rx_msg_length + payload_size > HECI_MAX_MSG_SIZE) { connect->ignore_rx_msg = 1; /* too big. discard */ @@ -760,7 +760,7 @@ static void heci_handle_client_msg(struct heci_msg *msg, size_t length) } static int handle_client_disconnect_req( - struct hbm_client_disconnect_req *client_disconnect_req) + struct hbm_client_disconnect_req *client_disconnect_req) { struct hbm_client_disconnect_res *client_disconnect_res; struct heci_msg heci_msg; @@ -772,8 +772,9 @@ static int handle_client_disconnect_req( CPRINTS("Got HECI disconnect request"); - heci_build_hbm_header(&heci_msg.hdr, sizeof(i2h->cmd) + - sizeof(*client_disconnect_res)); + heci_build_hbm_header(&heci_msg.hdr, + sizeof(i2h->cmd) + + sizeof(*client_disconnect_res)); i2h = (struct hbm_i2h *)heci_msg.payload; i2h->cmd = HECI_BUS_MSG_CLIENT_DISCONNECT_RESP; @@ -789,7 +790,7 @@ static int handle_client_disconnect_req( if (!heci_is_valid_client_addr(fw_addr) || !heci_is_client_connected(fw_addr)) { client_disconnect_res->status = - HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; + HECI_CONNECT_STATUS_CLIENT_NOT_FOUND; } else { connect = heci_get_client_connect(fw_addr); if (connect->host_addr != host_addr) { @@ -891,8 +892,8 @@ static int is_hbm_validity(struct hbm_h2i *h2i, size_t length) } if (valid_msg_len != length) { - CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", - h2i->cmd, valid_msg_len, length); + CPRINTF("invalid cmd(%d) valid : %d, cur : %zd\n", h2i->cmd, + valid_msg_len, length); /* TODO: invalid cmd. not sure to reply with error ? */ return 0; } @@ -922,7 +923,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length) case HECI_BUS_MSG_CLIENT_CONNECT_REQ: handle_client_connect_req( - (struct hbm_client_connect_req *)data); + (struct hbm_client_connect_req *)data); break; case HECI_BUS_MSG_FLOW_CONTROL: @@ -931,7 +932,7 @@ static void heci_handle_hbm(struct hbm_h2i *h2i, size_t length) case HECI_BUS_MSG_CLIENT_DISCONNECT_REQ: handle_client_disconnect_req( - (struct hbm_client_disconnect_req *)data); + (struct hbm_client_disconnect_req *)data); break; case HECI_BUS_MSG_HOST_STOP_REQ: @@ -991,7 +992,7 @@ static void heci_handle_heci_msg(struct heci_msg *heci_msg, size_t msg_length) } /* event flag for HECI msg */ -#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0) +#define EVENT_FLAG_BIT_HECI_MSG TASK_EVENT_CUSTOM_BIT(0) void heci_rx_task(void) { @@ -1017,8 +1018,9 @@ void heci_rx_task(void) continue; } - if (HECI_MSG_LENGTH(heci_msg.hdr.length) + sizeof(heci_msg.hdr) - == msg_len) + if (HECI_MSG_LENGTH(heci_msg.hdr.length) + + sizeof(heci_msg.hdr) == + msg_len) heci_handle_heci_msg(&heci_msg, msg_len); else CPRINTS("msg len mismatch.. discard.."); -- cgit v1.2.1 From 297a16450a9b79c5fdee2c3ba0742f2973c46bc4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:36:01 -0600 Subject: zephyr/shim/include/power_host_sleep.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8ae73f8cde5a247f55fe933ba2b8d7f03dbf802e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730847 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/power_host_sleep.h | 45 +++++++++++++++++----------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/zephyr/shim/include/power_host_sleep.h b/zephyr/shim/include/power_host_sleep.h index cc7fe04847..390de39691 100644 --- a/zephyr/shim/include/power_host_sleep.h +++ b/zephyr/shim/include/power_host_sleep.h @@ -24,31 +24,31 @@ /* power.h */ enum power_state { /* Steady states */ - POWER_G3 = 0, /* - * System is off (not technically all the way into G3, - * which means totally unpowered...) - */ - POWER_S5, /* System is soft-off */ - POWER_S4, /* System is suspended to disk */ - POWER_S3, /* Suspend; RAM on, processor is asleep */ - POWER_S0, /* System is on */ + POWER_G3 = 0, /* + * System is off (not technically all the way into G3, + * which means totally unpowered...) + */ + POWER_S5, /* System is soft-off */ + POWER_S4, /* System is suspended to disk */ + POWER_S3, /* Suspend; RAM on, processor is asleep */ + POWER_S0, /* System is on */ #if CONFIG_AP_PWRSEQ_S0IX POWER_S0ix, #endif /* Transitions */ - POWER_G3S5, /* G3 -> S5 (at system init time) */ - POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ - POWER_S3S0, /* S3 -> S0 */ - POWER_S0S3, /* S0 -> S3 */ - POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ - POWER_S5G3, /* S5 -> G3 */ - POWER_S3S4, /* S3 -> S4 */ - POWER_S4S3, /* S4 -> S3 */ - POWER_S4S5, /* S4 -> S5 */ - POWER_S5S4, /* S5 -> S4 */ + POWER_G3S5, /* G3 -> S5 (at system init time) */ + POWER_S5S3, /* S5 -> S3 (skips S4 on non-Intel systems) */ + POWER_S3S0, /* S3 -> S0 */ + POWER_S0S3, /* S0 -> S3 */ + POWER_S3S5, /* S3 -> S5 (skips S4 on non-Intel systems) */ + POWER_S5G3, /* S5 -> G3 */ + POWER_S3S4, /* S3 -> S4 */ + POWER_S4S3, /* S4 -> S3 */ + POWER_S4S5, /* S4 -> S5 */ + POWER_S5S4, /* S5 -> S4 */ #if CONFIG_AP_PWRSEQ_S0IX - POWER_S0ixS0, /* S0ix -> S0 */ - POWER_S0S0ix, /* S0 -> S0ix */ + POWER_S0ixS0, /* S0ix -> S0 */ + POWER_S0S0ix, /* S0 -> S0ix */ #endif }; @@ -56,12 +56,11 @@ enum power_state { /* Context to pass to a host sleep command handler. */ struct host_sleep_event_context { uint32_t sleep_transitions; /* Number of sleep transitions observed */ - uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ + uint16_t sleep_timeout_ms; /* Timeout in milliseconds */ }; void ap_power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx); + enum host_sleep_event state, struct host_sleep_event_context *ctx); void power_set_host_sleep_state(enum host_sleep_event state); #endif /* CONFIG_AP_PWRSEQ_HOST_SLEEP */ -- cgit v1.2.1 From 8e328d84ff82eeb1bb2233992058d2e496523971 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:37 -0600 Subject: driver/tcpm/fusb302.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3e86f9ad4c1552edd3d01c1c3769831d61807349 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730077 Reviewed-by: Jeremy Bettis --- driver/tcpm/fusb302.h | 318 +++++++++++++++++++++++++------------------------- 1 file changed, 159 insertions(+), 159 deletions(-) diff --git a/driver/tcpm/fusb302.h b/driver/tcpm/fusb302.h index 717b28df18..875bfa2292 100644 --- a/driver/tcpm/fusb302.h +++ b/driver/tcpm/fusb302.h @@ -24,173 +24,173 @@ /* FUSB302B11MPX */ #define FUSB302_I2C_ADDR_B11_FLAGS 0x25 -#define TCPC_REG_DEVICE_ID 0x01 - -#define TCPC_REG_SWITCHES0 0x02 -#define TCPC_REG_SWITCHES0_CC2_PU_EN (1<<7) -#define TCPC_REG_SWITCHES0_CC1_PU_EN (1<<6) -#define TCPC_REG_SWITCHES0_VCONN_CC2 (1<<5) -#define TCPC_REG_SWITCHES0_VCONN_CC1 (1<<4) -#define TCPC_REG_SWITCHES0_MEAS_CC2 (1<<3) -#define TCPC_REG_SWITCHES0_MEAS_CC1 (1<<2) -#define TCPC_REG_SWITCHES0_CC2_PD_EN (1<<1) -#define TCPC_REG_SWITCHES0_CC1_PD_EN (1<<0) - -#define TCPC_REG_SWITCHES1 0x03 -#define TCPC_REG_SWITCHES1_POWERROLE (1<<7) -#define TCPC_REG_SWITCHES1_SPECREV1 (1<<6) -#define TCPC_REG_SWITCHES1_SPECREV0 (1<<5) -#define TCPC_REG_SWITCHES1_DATAROLE (1<<4) -#define TCPC_REG_SWITCHES1_AUTO_GCRC (1<<2) -#define TCPC_REG_SWITCHES1_TXCC2_EN (1<<1) -#define TCPC_REG_SWITCHES1_TXCC1_EN (1<<0) - -#define TCPC_REG_MEASURE 0x04 -#define TCPC_REG_MEASURE_MDAC_MASK 0x3F -#define TCPC_REG_MEASURE_VBUS (1<<6) +#define TCPC_REG_DEVICE_ID 0x01 + +#define TCPC_REG_SWITCHES0 0x02 +#define TCPC_REG_SWITCHES0_CC2_PU_EN (1 << 7) +#define TCPC_REG_SWITCHES0_CC1_PU_EN (1 << 6) +#define TCPC_REG_SWITCHES0_VCONN_CC2 (1 << 5) +#define TCPC_REG_SWITCHES0_VCONN_CC1 (1 << 4) +#define TCPC_REG_SWITCHES0_MEAS_CC2 (1 << 3) +#define TCPC_REG_SWITCHES0_MEAS_CC1 (1 << 2) +#define TCPC_REG_SWITCHES0_CC2_PD_EN (1 << 1) +#define TCPC_REG_SWITCHES0_CC1_PD_EN (1 << 0) + +#define TCPC_REG_SWITCHES1 0x03 +#define TCPC_REG_SWITCHES1_POWERROLE (1 << 7) +#define TCPC_REG_SWITCHES1_SPECREV1 (1 << 6) +#define TCPC_REG_SWITCHES1_SPECREV0 (1 << 5) +#define TCPC_REG_SWITCHES1_DATAROLE (1 << 4) +#define TCPC_REG_SWITCHES1_AUTO_GCRC (1 << 2) +#define TCPC_REG_SWITCHES1_TXCC2_EN (1 << 1) +#define TCPC_REG_SWITCHES1_TXCC1_EN (1 << 0) + +#define TCPC_REG_MEASURE 0x04 +#define TCPC_REG_MEASURE_MDAC_MASK 0x3F +#define TCPC_REG_MEASURE_VBUS (1 << 6) /* * MDAC reference voltage step size is 42 mV. Round our thresholds to reduce * maximum error, which also matches suggested thresholds in datasheet * (Table 3. Host Interrupt Summary). */ -#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) - -#define TCPC_REG_CONTROL0 0x06 -#define TCPC_REG_CONTROL0_TX_FLUSH (1<<6) -#define TCPC_REG_CONTROL0_INT_MASK (1<<5) -#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2<<2) -#define TCPC_REG_CONTROL0_HOST_CUR_USB (1<<2) -#define TCPC_REG_CONTROL0_TX_START (1<<0) - -#define TCPC_REG_CONTROL1 0x07 -#define TCPC_REG_CONTROL1_ENSOP2DB (1<<6) -#define TCPC_REG_CONTROL1_ENSOP1DB (1<<5) -#define TCPC_REG_CONTROL1_BIST_MODE2 (1<<4) -#define TCPC_REG_CONTROL1_RX_FLUSH (1<<2) -#define TCPC_REG_CONTROL1_ENSOP2 (1<<1) -#define TCPC_REG_CONTROL1_ENSOP1 (1<<0) - -#define TCPC_REG_CONTROL2 0x08 +#define TCPC_REG_MEASURE_MDAC_MV(mv) (DIV_ROUND_NEAREST((mv), 42) & 0x3f) + +#define TCPC_REG_CONTROL0 0x06 +#define TCPC_REG_CONTROL0_TX_FLUSH (1 << 6) +#define TCPC_REG_CONTROL0_INT_MASK (1 << 5) +#define TCPC_REG_CONTROL0_HOST_CUR_MASK (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_3A0 (3 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_1A5 (2 << 2) +#define TCPC_REG_CONTROL0_HOST_CUR_USB (1 << 2) +#define TCPC_REG_CONTROL0_TX_START (1 << 0) + +#define TCPC_REG_CONTROL1 0x07 +#define TCPC_REG_CONTROL1_ENSOP2DB (1 << 6) +#define TCPC_REG_CONTROL1_ENSOP1DB (1 << 5) +#define TCPC_REG_CONTROL1_BIST_MODE2 (1 << 4) +#define TCPC_REG_CONTROL1_RX_FLUSH (1 << 2) +#define TCPC_REG_CONTROL1_ENSOP2 (1 << 1) +#define TCPC_REG_CONTROL1_ENSOP1 (1 << 0) + +#define TCPC_REG_CONTROL2 0x08 /* two-bit field, valid values below */ -#define TCPC_REG_CONTROL2_MODE_MASK (0x3< Date: Mon, 27 Jun 2022 15:22:06 -0600 Subject: test/queue.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0fbd6da9efe76d170ca50ba15051ca13b07f57e6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730532 Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- test/queue.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/test/queue.c b/test/queue.c index e0be1b5d9a..f25906ca6d 100644 --- a/test/queue.c +++ b/test/queue.c @@ -40,7 +40,7 @@ static int test_queue8_init(void) static int test_queue8_fifo(void) { - char buf1[3] = {1, 2, 3}; + char buf1[3] = { 1, 2, 3 }; char buf2[3]; TEST_ASSERT(queue_add_units(&test_queue8, buf1 + 0, 1) == 1); @@ -55,7 +55,7 @@ static int test_queue8_fifo(void) static int test_queue8_multiple_units_add(void) { - char buf1[5] = {1, 2, 3, 4, 5}; + char buf1[5] = { 1, 2, 3, 4, 5 }; char buf2[5]; TEST_ASSERT(queue_space(&test_queue8) >= 5); @@ -68,7 +68,7 @@ static int test_queue8_multiple_units_add(void) static int test_queue8_removal(void) { - char buf1[5] = {1, 2, 3, 4, 5}; + char buf1[5] = { 1, 2, 3, 4, 5 }; char buf2[5]; TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5); @@ -105,7 +105,7 @@ static int test_queue8_removal(void) static int test_queue8_peek(void) { - char buf1[5] = {1, 2, 3, 4, 5}; + char buf1[5] = { 1, 2, 3, 4, 5 }; char buf2[5]; TEST_ASSERT(queue_add_units(&test_queue8, buf1, 5) == 5); @@ -122,7 +122,7 @@ static int test_queue8_peek(void) static int test_queue2_odd_even(void) { - uint16_t buf1[3] = {1, 2, 3}; + uint16_t buf1[3] = { 1, 2, 3 }; uint16_t buf2[3]; TEST_ASSERT(queue_add_units(&test_queue2, buf1, 1) == 1); @@ -147,7 +147,7 @@ static int test_queue2_odd_even(void) static int test_queue8_chunks(void) { - static uint8_t const data[3] = {1, 2, 3}; + static uint8_t const data[3] = { 1, 2, 3 }; struct queue_chunk chunk; chunk = queue_get_write_chunk(&test_queue8, 0); @@ -161,7 +161,7 @@ static int test_queue8_chunks(void) chunk = queue_get_read_chunk(&test_queue8); TEST_ASSERT(chunk.count == 3); - TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 3); + TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 3); TEST_ASSERT(queue_advance_head(&test_queue8, 3) == 3); TEST_ASSERT(queue_is_empty(&test_queue8)); @@ -171,7 +171,7 @@ static int test_queue8_chunks(void) static int test_queue8_chunks_wrapped(void) { - static uint8_t const data[3] = {1, 2, 3}; + static uint8_t const data[3] = { 1, 2, 3 }; /* Move near the end of the queue */ TEST_ASSERT(queue_advance_tail(&test_queue8, 6) == 6); @@ -213,7 +213,7 @@ static int test_queue8_chunks_wrapped(void) static int test_queue8_chunks_full(void) { - static uint8_t const data[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + static uint8_t const data[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; struct queue_chunk chunk; /* Move near the end of the queue */ @@ -230,7 +230,7 @@ static int test_queue8_chunks_full(void) chunk = queue_get_read_chunk(&test_queue8); TEST_ASSERT(chunk.count == 2); - TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data, 2); + TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data, 2); /* Signal that we have read both units */ TEST_ASSERT(queue_advance_head(&test_queue8, 2) == 2); @@ -239,8 +239,7 @@ static int test_queue8_chunks_full(void) chunk = queue_get_read_chunk(&test_queue8); TEST_ASSERT(chunk.count == 6); - TEST_ASSERT_ARRAY_EQ((uint8_t *) chunk.buffer, data + 2, 6); - + TEST_ASSERT_ARRAY_EQ((uint8_t *)chunk.buffer, data + 2, 6); return EC_SUCCESS; } @@ -287,12 +286,12 @@ static int test_queue8_chunks_offset(void) /* Check offsetting by 1 */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).count == 7); TEST_ASSERT(queue_get_write_chunk(&test_queue8, 1).buffer == - test_queue8.buffer + 1); + test_queue8.buffer + 1); /* Check offsetting by 4 */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 4); TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer == - test_queue8.buffer + 4); + test_queue8.buffer + 4); /* Check offset wrapping around */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 10).count == 0); @@ -309,12 +308,12 @@ static int test_queue8_chunks_offset(void) /* Get writable chunk to right of tail. */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).count == 2); TEST_ASSERT(queue_get_write_chunk(&test_queue8, 2).buffer == - test_queue8.buffer + 6); + test_queue8.buffer + 6); /* Get writable chunk wrapped and before head. */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).count == 2); TEST_ASSERT(queue_get_write_chunk(&test_queue8, 4).buffer == - test_queue8.buffer); + test_queue8.buffer); /* Check offsetting into non-writable memory. */ TEST_ASSERT(queue_get_write_chunk(&test_queue8, 6).count == 0); -- cgit v1.2.1 From 5d3777836235c3d75a85edc7c57661d50069ad7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:38:10 -0600 Subject: common/mock/usb_prl_mock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I687881f928d657bad91912032a869eee23f3257b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729693 Reviewed-by: Jeremy Bettis --- common/mock/usb_prl_mock.c | 48 +++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/common/mock/usb_prl_mock.c b/common/mock/usb_prl_mock.c index d5f4781829..d9c0d086a6 100644 --- a/common/mock/usb_prl_mock.c +++ b/common/mock/usb_prl_mock.c @@ -45,14 +45,15 @@ void mock_prl_reset(void) memset(mock_prl_port, 0, sizeof(mock_prl_port)); - for (port = 0 ; port < CONFIG_USB_PD_PORT_MAX_COUNT ; ++port) { + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) { mock_prl_port[port].last_tx_type = TCPCI_MSG_INVALID; mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID; } } void prl_end_ams(int port) -{} +{ +} void prl_execute_hard_reset(int port) { @@ -67,7 +68,8 @@ enum pd_rev_type prl_get_rev(int port, enum tcpci_msg_type partner) } void prl_hard_reset_complete(int port) -{} +{ +} int prl_is_running(int port) { @@ -80,10 +82,11 @@ __overridable bool prl_is_busy(int port) } void prl_reset_soft(int port) -{} +{ +} void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, - enum pd_ctrl_msg_type msg) + enum pd_ctrl_msg_type msg) { mock_prl_port[port].last_ctrl_msg = msg; mock_prl_port[port].last_data_msg = 0; @@ -91,7 +94,7 @@ void prl_send_ctrl_msg(int port, enum tcpci_msg_type type, } void prl_send_data_msg(int port, enum tcpci_msg_type type, - enum pd_data_msg_type msg) + enum pd_data_msg_type msg) { mock_prl_port[port].last_data_msg = msg; mock_prl_port[port].last_ctrl_msg = 0; @@ -99,30 +102,28 @@ void prl_send_data_msg(int port, enum tcpci_msg_type type, } void prl_send_ext_data_msg(int port, enum tcpci_msg_type type, - enum pd_ext_msg_type msg) -{} - -void prl_set_rev(int port, enum tcpci_msg_type partner, - enum pd_rev_type rev) -{} + enum pd_ext_msg_type msg) +{ +} +void prl_set_rev(int port, enum tcpci_msg_type partner, enum pd_rev_type rev) +{ +} -int mock_prl_wait_for_tx_msg(int port, - enum tcpci_msg_type tx_type, +int mock_prl_wait_for_tx_msg(int port, enum tcpci_msg_type tx_type, enum pd_ctrl_msg_type ctrl_msg, - enum pd_data_msg_type data_msg, - int timeout) + enum pd_data_msg_type data_msg, int timeout) { uint64_t end_time = get_time().val + timeout; while (get_time().val < end_time) { if (mock_prl_port[port].last_tx_type != TCPCI_MSG_INVALID) { - TEST_EQ(mock_prl_port[port].last_tx_type, - tx_type, "%d"); - TEST_EQ(mock_prl_port[port].last_ctrl_msg, - ctrl_msg, "%d"); - TEST_EQ(mock_prl_port[port].last_data_msg, - data_msg, "%d"); + TEST_EQ(mock_prl_port[port].last_tx_type, tx_type, + "%d"); + TEST_EQ(mock_prl_port[port].last_ctrl_msg, ctrl_msg, + "%d"); + TEST_EQ(mock_prl_port[port].last_data_msg, data_msg, + "%d"); mock_prl_clear_last_sent_msg(port); return EC_SUCCESS; } @@ -191,8 +192,7 @@ void prl_run(int port, int evt, int en) } if (mock_prl_port[port].error_tx_type != TCPCI_MSG_INVALID) { ccprints("pe_error %d", mock_prl_port[port].error); - pe_report_error(port, - mock_prl_port[port].error, + pe_report_error(port, mock_prl_port[port].error, mock_prl_port[port].error_tx_type); mock_prl_port[port].error = 0; mock_prl_port[port].error_tx_type = TCPCI_MSG_INVALID; -- cgit v1.2.1 From 80c74b9d32232e597448820b98b073215fbb0d0e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:55:28 -0600 Subject: board/nautilus/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I8272e7938b55d750f73d34c0f1bf3eed16573650 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728723 Reviewed-by: Jeremy Bettis --- board/nautilus/board.h | 65 +++++++++++++++++++++++--------------------------- 1 file changed, 30 insertions(+), 35 deletions(-) diff --git a/board/nautilus/board.h b/board/nautilus/board.h index 3af9ee9b03..cf545050e7 100644 --- a/board/nautilus/board.h +++ b/board/nautilus/board.h @@ -88,8 +88,8 @@ #define CONFIG_CMD_CHARGER_ADC_AMON_BMON #define CONFIG_HOSTCMD_PD_CONTROL #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON @@ -128,7 +128,7 @@ /* Depends on how fast the AP boots and typical ODRs */ #define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3) -#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 2048 #define CONFIG_TABLET_MODE @@ -162,27 +162,27 @@ #define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2 /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 -#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 -#define I2C_PORT_CHARGER NPCX_I2C_PORT1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT1 -#define I2C_PORT_PMIC NPCX_I2C_PORT2 -#define I2C_PORT_MP2949 NPCX_I2C_PORT2 -#define I2C_PORT_GYRO NPCX_I2C_PORT3 -#define I2C_PORT_BARO NPCX_I2C_PORT3 -#define I2C_PORT_ACCEL I2C_PORT_GYRO -#define I2C_PORT_THERMAL I2C_PORT_PMIC +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_1 NPCX_I2C_PORT0_1 +#define I2C_PORT_USB_CHARGER_0 NPCX_I2C_PORT1 +#define I2C_PORT_CHARGER NPCX_I2C_PORT1 +#define I2C_PORT_BATTERY NPCX_I2C_PORT1 +#define I2C_PORT_PMIC NPCX_I2C_PORT2 +#define I2C_PORT_MP2949 NPCX_I2C_PORT2 +#define I2C_PORT_GYRO NPCX_I2C_PORT3 +#define I2C_PORT_BARO NPCX_I2C_PORT3 +#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_THERMAL I2C_PORT_PMIC /* I2C addresses */ -#define I2C_ADDR_BD99992_FLAGS 0x30 -#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_MP2949_FLAGS 0x20 #ifndef __ASSEMBLER__ @@ -191,9 +191,9 @@ /* Nautilus doesn't have systherm0 and systherm3 */ enum temp_sensor_id { - TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ TEMP_SENSOR_COUNT }; @@ -211,28 +211,23 @@ enum sensor_id { SENSOR_COUNT, }; -enum adc_channel { - ADC_BASE_DET, - ADC_VBUS, - ADC_AMON_BMON, - ADC_CH_COUNT -}; +enum adc_channel { ADC_BASE_DET, ADC_VBUS, ADC_AMON_BMON, ADC_CH_COUNT }; /* TODO(crosbug.com/p/61098): Verify the numbers below. */ /* * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ int board_get_version(void); -- cgit v1.2.1 From acfb6767a27429fcfc21774b6f1440cc41e41024 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 14:15:50 -0700 Subject: common: Move strcasecmp and strtoull to util_stdlib.c The util_stdlib.c file contains the EC implementation of C standard library functions. strcasecmp and strtoull are part of the C standard library, so they should be in util_stdlib.c. BRANCH=none BUG=b:234181908 TEST=make buildall -j TEST=Using icetower v0.1, Segger J-Trace, and servo micro: ./test/run_device_tests.py -b dartmonkey -t utils_str Test "utils_str": PASSED Signed-off-by: Tom Hughes Change-Id: I7bd92df31eabf850ef4091e99803948abba6f912 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724487 Reviewed-by: Jack Rosenthal --- common/util.c | 54 +--------------------------------------------- common/util_stdlib.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/util.h | 1 + zephyr/CMakeLists.txt | 3 +++ 4 files changed, 65 insertions(+), 53 deletions(-) diff --git a/common/util.c b/common/util.c index d2521304b9..c911a83ce9 100644 --- a/common/util.c +++ b/common/util.c @@ -9,19 +9,7 @@ #include "console.h" #include "util.h" -__stdlib_compat int strcasecmp(const char *s1, const char *s2) -{ - int diff; - - do { - diff = tolower(*s1) - tolower(*s2); - if (diff) - return diff; - } while (*(s1++) && *(s2++)); - return 0; -} - -static int find_base(int base, int *c, const char **nptr) +int find_base(int base, int *c, const char **nptr) { if ((base == 0 || base == 16) && *c == '0' && (**nptr == 'x' || **nptr == 'X')) { @@ -71,46 +59,6 @@ int strtoi(const char *nptr, char **endptr, int base) return neg ? -result : result; } -#ifndef CONFIG_ZEPHYR -__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr, - int base) -{ - uint64_t result = 0; - int c = '\0'; - - while ((c = *nptr++) && isspace(c)) - ; - - if (c == '+') { - c = *nptr++; - } else if (c == '-') { - if (endptr) - *endptr = (char *)nptr - 1; - return result; - } - - base = find_base(base, &c, &nptr); - - while (c) { - if (c >= '0' && c < '0' + MIN(base, 10)) - result = result * base + (c - '0'); - else if (c >= 'A' && c < 'A' + base - 10) - result = result * base + (c - 'A' + 10); - else if (c >= 'a' && c < 'a' + base - 10) - result = result * base + (c - 'a' + 10); - else - break; - - c = *nptr++; - } - - if (endptr) - *endptr = (char *)nptr - 1; - return result; -} -#endif /* !CONFIG_ZEPHYR */ -BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t)); - int parse_bool(const char *s, int *dest) { /* off, disable, false, no */ diff --git a/common/util_stdlib.c b/common/util_stdlib.c index 04394feead..e42788c4af 100644 --- a/common/util_stdlib.c +++ b/common/util_stdlib.c @@ -9,6 +9,27 @@ #include "console.h" #include "util.h" +/* + * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll + * use the EC implementation. + */ +__stdlib_compat int strcasecmp(const char *s1, const char *s2) +{ + int diff; + + do { + diff = tolower(*s1) - tolower(*s2); + if (diff) + return diff; + } while (*(s1++) && *(s2++)); + return 0; +} + +/* + * TODO(b/237712836): Remove this conditional once strcasecmp is added to + * Zephyr's libc. + */ +#ifndef CONFIG_ZEPHYR __stdlib_compat size_t strlen(const char *s) { int len = 0; @@ -112,6 +133,44 @@ __stdlib_compat char *strstr(const char *s1, const char *s2) return NULL; } +__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr, + int base) +{ + uint64_t result = 0; + int c = '\0'; + + while ((c = *nptr++) && isspace(c)) + ; + + if (c == '+') { + c = *nptr++; + } else if (c == '-') { + if (endptr) + *endptr = (char *)nptr - 1; + return result; + } + + base = find_base(base, &c, &nptr); + + while (c) { + if (c >= '0' && c < '0' + MIN(base, 10)) + result = result * base + (c - '0'); + else if (c >= 'A' && c < 'A' + base - 10) + result = result * base + (c - 'A' + 10); + else if (c >= 'a' && c < 'a' + base - 10) + result = result * base + (c - 'a' + 10); + else + break; + + c = *nptr++; + } + + if (endptr) + *endptr = (char *)nptr - 1; + return result; +} +BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t)); + __stdlib_compat int atoi(const char *nptr) { int result = 0; @@ -325,3 +384,4 @@ __stdlib_compat int strncmp(const char *s1, const char *s2, size_t n) } return 0; } +#endif /* !CONFIG_ZEPHYR */ diff --git a/include/util.h b/include/util.h index 04b44accb7..8339838abd 100644 --- a/include/util.h +++ b/include/util.h @@ -234,6 +234,7 @@ int alignment_log2(unsigned int x); */ void reverse(void *dest, size_t len); +int find_base(int base, int *c, const char **nptr); /****************************************************************************/ /* Conditional stuff. * diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index fbee307dc4..444e320dad 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -145,6 +145,9 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c" "${PLATFORM_EC}/common/system.c" "${PLATFORM_EC}/common/uart_printf.c" "${PLATFORM_EC}/common/util.c" + # TODO(b/237712836): Remove once + # Zephyr's libc has strcasecmp. + "${PLATFORM_EC}/common/util_stdlib.c" "${PLATFORM_EC}/common/version.c") # Now include files that depend on or relate to other CONFIG options, sorted by -- cgit v1.2.1 From 59dd0a83a5a4a98b520b7cddc7adbf2c9e7add7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:39 -0600 Subject: board/kracko/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ice3bc3d6d8df0ab90f5d6190d39889b8bd421cea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728589 Reviewed-by: Jeremy Bettis --- board/kracko/led.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/board/kracko/led.c b/board/kracko/led.c index af78cfa883..5ebb483219 100644 --- a/board/kracko/led.c +++ b/board/kracko/led.c @@ -10,8 +10,8 @@ #include "led_common.h" #include "led_onoff_states.h" -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1; @@ -19,18 +19,24 @@ __override const int led_charge_lvl_2 = 100; /* Kracko: Note there is only LED for charge / power */ __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; -- cgit v1.2.1 From a187c4931670205bccc04763024b97b0c956d586 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:25 -0600 Subject: board/reef/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icb08496298d379d5cb91dbefb3c02c7ccc98d17a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728865 Reviewed-by: Jeremy Bettis --- board/reef/board.c | 165 ++++++++++++++++++++++++----------------------------- 1 file changed, 74 insertions(+), 91 deletions(-) diff --git a/board/reef/board.c b/board/reef/board.c index e224169f3b..0902da3584 100644 --- a/board/reef/board.c +++ b/board/reef/board.c @@ -53,15 +53,15 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) -#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) -#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) +#define IN_ALL_SYS_PG POWER_SIGNAL_MASK(X86_ALL_SYS_PG) +#define IN_PGOOD_PP3300 POWER_SIGNAL_MASK(X86_PGOOD_PP3300) +#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000) -#define USB_PD_PORT_ANX74XX 0 -#define USB_PD_PORT_PS8751 1 +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 static void tcpc_alert_event(enum gpio_signal signal) { @@ -126,61 +126,48 @@ void tablet_mode_interrupt(enum gpio_signal signal) /* ADC channels */ const struct adc_t adc_channels[] = { /* Vfs = Vref = 2.816V, 10-bit unsigned reading */ - [ADC_TEMP_SENSOR_CHARGER] = { - "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_TEMP_SENSOR_AMB] = { - "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, - [ADC_BOARD_ID] = { - "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, ADC_READ_MAX + 1, 0 - }, + [ADC_TEMP_SENSOR_CHARGER] = { "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_AMB] = { "AMBIENT", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_BOARD_ID] = { "BRD_ID", NPCX_ADC_CH2, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { [PWM_CH_LED_GREEN] = { 2, PWM_CONFIG_DSLEEP, 100 }, - [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 3, PWM_CONFIG_DSLEEP, 100 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc0", - .port = NPCX_I2C_PORT0_0, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = NPCX_I2C_PORT0_1, - .kbps = 400, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "accelgyro", - .port = I2C_PORT_GYRO, - .kbps = 400, - .scl = GPIO_EC_I2C_GYRO_SCL, - .sda = GPIO_EC_I2C_GYRO_SDA - }, - { - .name = "sensors", - .port = NPCX_I2C_PORT2, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, - { - .name = "batt", - .port = NPCX_I2C_PORT3, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, +const struct i2c_port_t i2c_ports[] = { + { .name = "tcpc0", + .port = NPCX_I2C_PORT0_0, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = NPCX_I2C_PORT0_1, + .kbps = 400, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "accelgyro", + .port = I2C_PORT_GYRO, + .kbps = 400, + .scl = GPIO_EC_I2C_GYRO_SCL, + .sda = GPIO_EC_I2C_GYRO_SDA }, + { .name = "sensors", + .port = NPCX_I2C_PORT2, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, + { .name = "batt", + .port = NPCX_I2C_PORT3, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -413,28 +400,28 @@ void board_tcpc_init(void) gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET); #endif /* - * Initialize HPD to low; after sysjump SOC needs to see - * HPD pulse to enable video path - */ + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ for (int port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; ++port) usb_mux_hpd_update(port, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + USB_PD_MUX_HPD_IRQ_DEASSERTED); } -DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C+1); +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_BATTERY] = {.name = "Battery", - .type = TEMP_SENSOR_TYPE_BATTERY, - .read = charge_get_battery_temp, - .idx = 0}, - [TEMP_SENSOR_AMBIENT] = {.name = "Ambient", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_51k1_47k_4050b, - .idx = ADC_TEMP_SENSOR_AMB}, - [TEMP_SENSOR_CHARGER] = {.name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_13k7_47k_4050b, - .idx = ADC_TEMP_SENSOR_CHARGER}, + [TEMP_SENSOR_BATTERY] = { .name = "Battery", + .type = TEMP_SENSOR_TYPE_BATTERY, + .read = charge_get_battery_temp, + .idx = 0 }, + [TEMP_SENSOR_AMBIENT] = { .name = "Ambient", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_51k1_47k_4050b, + .idx = ADC_TEMP_SENSOR_AMB }, + [TEMP_SENSOR_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_13k7_47k_4050b, + .idx = ADC_TEMP_SENSOR_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -551,8 +538,8 @@ int board_set_active_charge_port(int charge_port) * @param charge_ma Desired charge limit (mA). * @param charge_mv Negotiated charge voltage (mV). */ -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Enable charging trigger by BC1.2 detection */ int bc12_enable = (supplier == CHARGE_SUPPLIER_BC12_CDP || @@ -564,8 +551,8 @@ void board_set_charge_limit(int port, int supplier, int charge_ma, return; charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } /** @@ -675,17 +662,17 @@ void board_hibernate_late(void) int i; const uint32_t hibernate_pins[][2] = { /* Turn off LEDs in hibernate */ - {GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP}, - {GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN}, + { GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP }, + { GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN }, /* * BD99956 handles charge input automatically. We'll disable * charge output in hibernate. Charger will assert ACOK_OD * when VBUS or VCC are plugged in. */ - {GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, - {GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN}, + { GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, + { GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN }, }; /* Change GPIOs' state in hibernate for better power consumption */ @@ -712,17 +699,13 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Matrix to rotate accelrator into standard reference frame */ -const mat33_fp_t base_standard_ref = { - { 0, FLOAT_TO_FP(-1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -const mat33_fp_t mag_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t mag_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct kionix_accel_data g_kx022_data; @@ -890,8 +873,8 @@ struct { int thresh_mv; } const reef_board_versions[] = { /* Vin = 3.3V, R1 = 46.4K, R2 values listed below */ - { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ - { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ + { BOARD_VERSION_1, 328 * 1.03 }, /* 5.11 Kohm */ + { BOARD_VERSION_2, 670 * 1.03 }, /* 11.8 Kohm */ { BOARD_VERSION_3, 1012 * 1.03 }, /* 20.5 Kohm */ { BOARD_VERSION_4, 1357 * 1.03 }, /* 32.4 Kohm */ { BOARD_VERSION_5, 1690 * 1.03 }, /* 48.7 Kohm */ -- cgit v1.2.1 From d6f6090e7267f227b5107090266bdd30be74d005 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:23:27 -0600 Subject: chip/npcx/clock.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icf63042d0ae4bc223746a54f011207f249f778f1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729388 Reviewed-by: Jeremy Bettis --- chip/npcx/clock.c | 73 ++++++++++++++++++++++++++----------------------------- 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 4656e83a52..2525815359 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -26,10 +26,10 @@ /* Console output macros */ #define CPUTS(outstr) cputs(CC_CLOCK, outstr) -#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CLOCK, format, ##args) -#define WAKE_INTERVAL 61 /* Unit: 61 usec */ -#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */ +#define WAKE_INTERVAL 61 /* Unit: 61 usec */ +#define IDLE_PARAMS 0x7 /* Support deep idle, instant wake-up */ /* Low power idle statistics */ #ifdef CONFIG_LOW_POWER_IDLE @@ -40,7 +40,7 @@ static uint64_t idle_dsleep_time_us; * Fixed amount of time to keep the console in use flag true after boot in * order to give a permanent window in which the low speed clock is not used. */ -#define CONSOLE_IN_USE_ON_BOOT_TIME (15*SECOND) +#define CONSOLE_IN_USE_ON_BOOT_TIME (15 * SECOND) static int console_in_use_timeout_sec = 15; static timestamp_t console_expire_time; #endif @@ -79,7 +79,6 @@ void clock_disable_peripheral(uint32_t offset, uint32_t mask, uint32_t mode) /* Set PD bit to 1 */ NPCX_PWDWN_CTL(offset) |= reg_mask; - } /*****************************************************************************/ @@ -100,13 +99,13 @@ void clock_init(void) * unstable for a little which can affect peripheral communication like * eSPI. Skip this if not needed (e.g. RW jump) */ - if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML - || NPCX_HFCGMH != HFCGMH) { + if (NPCX_HFCGN != HFCGN || NPCX_HFCGML != HFCGML || + NPCX_HFCGMH != HFCGMH) { /* * Configure frequency multiplier M/N values according to * the requested OSC_CLK (Unit:Hz). */ - NPCX_HFCGN = HFCGN; + NPCX_HFCGN = HFCGN; NPCX_HFCGML = HFCGML; NPCX_HFCGMH = HFCGMH; @@ -119,11 +118,11 @@ void clock_init(void) /* Set all clock prescalers of core and peripherals. */ #if defined(CHIP_FAMILY_NPCX5) - NPCX_HFCGP = (FPRED << 4); + NPCX_HFCGP = (FPRED << 4); NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2)); #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 - NPCX_HFCGP = ((FPRED << 4) | AHB6DIV); - NPCX_HFCBCD = (FIUDIV << 4); + NPCX_HFCGP = ((FPRED << 4) | AHB6DIV); + NPCX_HFCBCD = (FIUDIV << 4); NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4)); #if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4)); @@ -143,7 +142,7 @@ void clock_init(void) void clock_turbo(void) { /* Configure Frequency multiplier values to 50MHz */ - NPCX_HFCGN = 0x02; + NPCX_HFCGN = 0x02; NPCX_HFCGML = 0xEC; NPCX_HFCGMH = 0x0B; @@ -255,7 +254,8 @@ int clock_get_apb3_freq(void) void clock_wait_cycles(uint32_t cycles) { asm volatile("1: subs %0, #1\n" - " bne 1b\n" : "+r"(cycles)); + " bne 1b\n" + : "+r"(cycles)); } #ifdef CONFIG_LOW_POWER_IDLE @@ -378,12 +378,11 @@ void __idle(void) * more detail. * Workaround: Apply the same bypass of idle. */ - asm ("push {r0-r5}\n" - "wfi\n" - "ldm %0, {r0-r5}\n" - "pop {r0-r5}\n" - "isb\n" :: "r" (0x100A8000) - ); + asm("push {r0-r5}\n" + "wfi\n" + "ldm %0, {r0-r5}\n" + "pop {r0-r5}\n" + "isb\n" ::"r"(0x100A8000)); /* Get time delay cause of deep idle */ next_evt_us = __hw_clock_get_sleep_time(evt_count); @@ -431,12 +430,11 @@ void __idle(void) * TODO (ML): Workaround method for wfi issue. * Please see task.c for more detail */ - asm ("push {r0-r5}\n" - "wfi\n" - "ldm %0, {r0-r5}\n" - "pop {r0-r5}\n" - "isb\n" :: "r" (0x100A8000) - ); + asm("push {r0-r5}\n" + "wfi\n" + "ldm %0, {r0-r5}\n" + "pop {r0-r5}\n" + "isb\n" ::"r"(0x100A8000)); } /* @@ -448,7 +446,6 @@ void __idle(void) } #endif /* CONFIG_LOW_POWER_IDLE */ - #ifdef CONFIG_LOW_POWER_IDLE /** * Print low power idle statistics @@ -460,13 +457,12 @@ static int command_idle_stats(int argc, char **argv) ccprintf("Num idle calls that sleep: %d\n", idle_sleep_cnt); ccprintf("Num idle calls that deep-sleep: %d\n", idle_dsleep_cnt); ccprintf("Time spent in deep-sleep: %.6llds\n", - idle_dsleep_time_us); + idle_dsleep_time_us); ccprintf("Total time on: %.6llds\n", ts.val); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, - "", - "Print last idle stats"); +DECLARE_CONSOLE_COMMAND(idlestats, command_idle_stats, "", + "Print last idle stats"); /** * Configure deep sleep clock settings. @@ -501,17 +497,16 @@ static int command_dsleep(int argc, char **argv) ccprintf("Sleep mask: %08x\n", (int)sleep_mask); ccprintf("Console in use timeout: %d sec\n", - console_in_use_timeout_sec); + console_in_use_timeout_sec); ccprintf("PMCSR register: 0x%02x\n", NPCX_PMCSR); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, - "[ on | off | sec]", - "Deep sleep clock settings:\nUse 'on' to force deep " - "sleep not to use low speed clock.\nUse 'off' to " - "allow deep sleep to auto-select using the low speed " - "clock.\n" - "Give a timeout value for the console in use timeout.\n" - "See also 'sleepmask'."); +DECLARE_CONSOLE_COMMAND(dsleep, command_dsleep, "[ on | off | sec]", + "Deep sleep clock settings:\nUse 'on' to force deep " + "sleep not to use low speed clock.\nUse 'off' to " + "allow deep sleep to auto-select using the low speed " + "clock.\n" + "Give a timeout value for the console in use timeout.\n" + "See also 'sleepmask'."); #endif /* CONFIG_LOW_POWER_IDLE */ -- cgit v1.2.1 From e967466e308c1689af0772a6bd071d3b637b18ed Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:30 -0600 Subject: chip/stm32/adc-stm32f0.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3edbac7ab7ac77ce7507ce2ef0369a6b495c842c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729450 Reviewed-by: Jeremy Bettis --- chip/stm32/adc-stm32f0.c | 45 ++++++++++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index b0654132cd..e2069c8266 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -21,7 +21,7 @@ struct adc_profile_t { /* Register values. */ uint32_t cfgr1_reg; uint32_t cfgr2_reg; - uint32_t smpr_reg; /* Default Sampling Rate */ + uint32_t smpr_reg; /* Default Sampling Rate */ uint32_t ier_reg; /* DMA config. */ const struct dma_option *dma_option; @@ -31,7 +31,8 @@ struct adc_profile_t { #ifdef CONFIG_ADC_PROFILE_SINGLE static const struct dma_option dma_single = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT, }; @@ -41,12 +42,9 @@ static const struct dma_option dma_single = { static const struct adc_profile_t profile = { /* Sample all channels once using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, - .cfgr2_reg = 0, - .smpr_reg = CONFIG_ADC_SAMPLE_TIME, - .ier_reg = 0, - .dma_option = &dma_single, - .dma_buffer_size = 1, + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD, .cfgr2_reg = 0, + .smpr_reg = CONFIG_ADC_SAMPLE_TIME, .ier_reg = 0, + .dma_option = &dma_single, .dma_buffer_size = 1, }; #endif @@ -57,15 +55,15 @@ static const struct adc_profile_t profile = { #endif static const struct dma_option dma_continuous = { - STM32_DMAC_ADC, (void *)&STM32_ADC_DR, + STM32_DMAC_ADC, + (void *)&STM32_ADC_DR, STM32_DMA_CCR_MSIZE_32_BIT | STM32_DMA_CCR_PSIZE_32_BIT | - STM32_DMA_CCR_CIRC, + STM32_DMA_CCR_CIRC, }; static const struct adc_profile_t profile = { /* Sample all channels continuously using DMA */ - .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | - STM32_ADC_CFGR1_CONT | + .cfgr1_reg = STM32_ADC_CFGR1_OVRMOD | STM32_ADC_CFGR1_CONT | STM32_ADC_CFGR1_DMACFG, .cfgr2_reg = 0, .smpr_reg = CONFIG_ADC_SAMPLE_TIME, @@ -114,7 +112,7 @@ static void adc_configure(int ain_id, enum stm32_adc_smpr sample_rate) { /* Sampling time */ if (sample_rate == STM32_ADC_SMPR_DEFAULT || - sample_rate >= STM32_ADC_SMPR_COUNT) + sample_rate >= STM32_ADC_SMPR_COUNT) STM32_ADC_SMPR = profile.smpr_reg; else STM32_ADC_SMPR = STM32_ADC_SMPR_SMP(sample_rate); @@ -160,12 +158,12 @@ static void adc_interval_read(int ain_id, int interval_ms) adc_configure(ain_id, STM32_ADC_SMPR_DEFAULT); /* EXTEN=01 -> hardware trigger detection on rising edge */ - STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) - | STM32_ADC_CFGR1_EXTEN_RISE; + STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_EXTEN_MASK) | + STM32_ADC_CFGR1_EXTEN_RISE; /* EXTSEL=TRG3 -> Trigger on TIM3_TRGO */ STM32_ADC_CFGR1 = (STM32_ADC_CFGR1 & ~STM32_ADC_CFGR1_TRG_MASK) | - STM32_ADC_CFGR1_TRG3; + STM32_ADC_CFGR1_TRG3; __hw_timer_enable_clock(TIM_ADC, 1); @@ -293,9 +291,18 @@ int adc_set_watchdog_delay(int delay_ms) #else /* CONFIG_ADC_WATCHDOG */ -static int adc_watchdog_enabled(void) { return 0; } -static int adc_enable_watchdog_no_lock(void) { return 0; } -static int adc_disable_watchdog_no_lock(void) { return 0; } +static int adc_watchdog_enabled(void) +{ + return 0; +} +static int adc_enable_watchdog_no_lock(void) +{ + return 0; +} +static int adc_disable_watchdog_no_lock(void) +{ + return 0; +} #endif /* CONFIG_ADC_WATCHDOG */ -- cgit v1.2.1 From 1b8eec0ee2b050afa2d450bfe499fb2d7a180028 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:35:28 -0600 Subject: board/fusb307bgevb/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icae390a7526876e13a051eafb47143aa4c84c1ae Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728379 Reviewed-by: Jeremy Bettis --- board/fusb307bgevb/board.c | 90 ++++++++++++++++------------------------------ 1 file changed, 31 insertions(+), 59 deletions(-) diff --git a/board/fusb307bgevb/board.c b/board/fusb307bgevb/board.c index f3f4da1a74..853b38c0a3 100644 --- a/board/fusb307bgevb/board.c +++ b/board/fusb307bgevb/board.c @@ -24,8 +24,8 @@ #include "usb_common.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -156,20 +156,15 @@ static enum gpio_signal const usb_gpio_list[] = { * This instantiates struct usb_gpio_config const usb_gpio, plus several other * variables, all named something beginning with usb_gpio_ */ -USB_GPIO_CONFIG(usb_gpio, - usb_gpio_list, - USB_IFACE_GPIO, - USB_EP_GPIO); +USB_GPIO_CONFIG(usb_gpio, usb_gpio_list, USB_IFACE_GPIO, USB_EP_GPIO); /****************************************************************************** * Setup USART1 as a loopback device, it just echo's back anything sent to it. */ static struct usart_config const loopback_usart; -static struct queue const loopback_queue = - QUEUE_DIRECT(64, uint8_t, - loopback_usart.producer, - loopback_usart.consumer); +static struct queue const loopback_queue = QUEUE_DIRECT( + 64, uint8_t, loopback_usart.producer, loopback_usart.consumer); static struct usart_rx_dma const loopback_rx_dma = USART_RX_DMA(STM32_DMAC_CH3, 8); @@ -177,14 +172,9 @@ static struct usart_rx_dma const loopback_rx_dma = static struct usart_tx_dma const loopback_tx_dma = USART_TX_DMA(STM32_DMAC_CH2, 16); -static struct usart_config const loopback_usart = - USART_CONFIG(usart1_hw, - loopback_rx_dma.usart_rx, - loopback_tx_dma.usart_tx, - 115200, - 0, - loopback_queue, - loopback_queue); +static struct usart_config const loopback_usart = USART_CONFIG( + usart1_hw, loopback_rx_dma.usart_rx, loopback_tx_dma.usart_tx, 115200, + 0, loopback_queue, loopback_queue); /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -192,46 +182,34 @@ static struct usart_config const loopback_usart = static struct usart_config const forward_usart; struct usb_stream_config const forward_usb; -static struct queue const usart_to_usb = QUEUE_DIRECT(64, uint8_t, - forward_usart.producer, - forward_usb.consumer); -static struct queue const usb_to_usart = QUEUE_DIRECT(64, uint8_t, - forward_usb.producer, - forward_usart.consumer); +static struct queue const usart_to_usb = + QUEUE_DIRECT(64, uint8_t, forward_usart.producer, forward_usb.consumer); +static struct queue const usb_to_usart = + QUEUE_DIRECT(64, uint8_t, forward_usb.producer, forward_usart.consumer); static struct usart_tx_dma const forward_tx_dma = USART_TX_DMA(STM32_DMAC_CH7, 16); static struct usart_config const forward_usart = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - forward_tx_dma.usart_tx, - 115200, - 0, - usart_to_usb, - usb_to_usart); - -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 - -USB_STREAM_CONFIG(forward_usb, - USB_IFACE_STREAM, - USB_STR_STREAM_NAME, - USB_EP_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart, - usart_to_usb) + USART_CONFIG(usart4_hw, usart_rx_interrupt, forward_tx_dma.usart_tx, + 115200, 0, usart_to_usb, usb_to_usart); + +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 + +USB_STREAM_CONFIG(forward_usb, USB_IFACE_STREAM, USB_STR_STREAM_NAME, + USB_EP_STREAM, USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, + usb_to_usart, usart_to_usb) /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("fusb307bgevb"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("fusb307bgevb"), + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_STREAM_NAME] = USB_STRING_DESC("Forward"), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"), }; @@ -240,15 +218,11 @@ BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); /****************************************************************************** * I2C interface. */ -const struct i2c_port_t i2c_ports[] = { - { - .name = "tcpc", - .port = I2C_PORT_TCPC, - .kbps = 400 /* kHz */, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - } -}; +const struct i2c_port_t i2c_ports[] = { { .name = "tcpc", + .port = I2C_PORT_TCPC, + .kbps = 400 /* kHz */, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA } }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /****************************************************************************** @@ -265,7 +239,6 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; - uint16_t tcpc_get_alert_status(void) { uint16_t status = 0; @@ -329,6 +302,5 @@ static void board_init(void) queue_init(&usb_to_usart); usart_init(&loopback_usart); usart_init(&forward_usart); - } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 21692110231eaf6b985d08f36db11df74d6c6c7c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:03 -0600 Subject: board/waddledee/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a1a0baf266f614bf44a0ccd1510d9bf654beae8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729107 Reviewed-by: Jeremy Bettis --- board/waddledee/led.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/waddledee/led.c b/board/waddledee/led.c index 058d23d761..121a760515 100644 --- a/board/waddledee/led.c +++ b/board/waddledee/led.c @@ -20,13 +20,13 @@ const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); * Board has one physical LED with red, green, and blue */ struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Red, Green, Blue */ - [EC_LED_COLOR_RED] = { 100, 0, 0 }, - [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, - [EC_LED_COLOR_YELLOW] = { 50, 50, 0 }, - [EC_LED_COLOR_WHITE] = { 50, 50, 50 }, - [EC_LED_COLOR_AMBER] = { 70, 30, 0 }, + /* Red, Green, Blue */ + [EC_LED_COLOR_RED] = { 100, 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 100, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 50, 50, 0 }, + [EC_LED_COLOR_WHITE] = { 50, 50, 50 }, + [EC_LED_COLOR_AMBER] = { 70, 30, 0 }, }; /* One logical LED with red, green, and blue channels. */ -- cgit v1.2.1 From 192839afdbf06a58ac6f5e33066593a69236ab9d Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 17:21:00 -0600 Subject: TCPMv2: Synchronize DP and DPM states Leave DisplayPort alt mode state machine in inactive state after failed entry. Reset DP state machine to start state after DP entry request from AP. Avoid repeatedly cycling DP state machine, independently of DPM, after failed DP mode entry sequence. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I2e1a5ab36a38cba51e19f39e1f9ea9a8944e1849 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726953 Commit-Queue: Diana Z Reviewed-by: Diana Z --- common/usbc/dp_alt_mode.c | 8 ++++++-- common/usbc/usb_pd_dpm.c | 2 ++ include/usb_dp_alt_mode.h | 11 +++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c index 0b34d42cb1..ac2b965b72 100644 --- a/common/usbc/dp_alt_mode.c +++ b/common/usbc/dp_alt_mode.c @@ -72,6 +72,11 @@ bool dp_is_active(int port) return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_PREPARE_EXIT; } +bool dp_is_idle(int port) +{ + return dp_state[port] == DP_INACTIVE || dp_state[port] == DP_START; +} + void dp_init(int port) { dp_state[port] = DP_START; @@ -126,8 +131,7 @@ static void dp_exit_to_usb_mode(int port) * the EC to enter again later, so leave the state machine ready for * that possibility. */ - dp_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) - ? DP_START : DP_INACTIVE; + dp_state[port] = DP_INACTIVE; } void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 389445d19c..8bce6b9bc3 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -126,6 +126,8 @@ enum ec_status pd_request_enter_mode(int port, enum typec_mode mode) switch (mode) { case TYPEC_MODE_DP: + if (dp_is_idle(port)) + dp_init(port); DPM_SET_FLAG(port, DPM_FLAG_ENTER_DP); break; #ifdef CONFIG_USB_PD_TBT_COMPAT_MODE diff --git a/include/usb_dp_alt_mode.h b/include/usb_dp_alt_mode.h index f7c2df77ef..c42a0377c6 100644 --- a/include/usb_dp_alt_mode.h +++ b/include/usb_dp_alt_mode.h @@ -33,6 +33,17 @@ void dp_init(int port); */ bool dp_is_active(int port); +/* + * Returns True if DisplayPort mode entry has not started, or mode exit has + * already finished. + * TODO(b/235984702): Consolidate the DP state API + * + * @param port USB-C port number + * @return True if DisplayPort mode is in inactive state + * False otherwise. + */ +bool dp_is_idle(int port); + /* * Checks whether the mode entry sequence for DisplayPort alternate mode is done * for a port. -- cgit v1.2.1 From ec181c329d336bd3d418b583fb98068bef147652 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Mon, 27 Jun 2022 10:48:57 -0600 Subject: TCPMv2: Treat VDM response timeout as NAK In PE_VDM_REQUEST_DPM, treat a VDM response timeout the same as a NAK. The DPM will then abandon the mode entry (typically) process. This avoids getting stuck in a loop with a partner that non-compliantly advertises alternate mode support but refuses to enter. BUG=b:207522204,b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: If28b5370deccab119f8d4248229496ecd79eec76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726955 Reviewed-by: Diana Z Commit-Queue: Diana Z --- common/usbc/usb_pe_drp_sm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index 0852914cd9..8d537a0e68 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -6136,6 +6136,24 @@ static void pe_vdm_request_dpm_run(int port) static void pe_vdm_request_dpm_exit(int port) { + if (PE_CHK_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT)) { + PE_CLR_FLAG(port, PE_FLAGS_VDM_REQUEST_TIMEOUT); + PE_SET_FLAG(port, PE_FLAGS_VDM_SETUP_DONE); + + /* + * Mark failure to respond as discovery failure. + * + * For PD 2.0 partners (6.10.3 Applicability of Structured VDM + * Commands Note 3): + * + * If Structured VDMs are not supported, a Structured VDM + * Command received by a DFP or UFP Shall be Ignored. + */ + dpm_vdm_naked(port, pe[port].tx_type, + PD_VDO_VID(pe[port].vdm_data[0]), + PD_VDO_CMD(pe[port].vdm_data[0])); + } + /* * Force Tx type to be reset before reentering a VDM state, unless the * current VDM request will be resumed. -- cgit v1.2.1 From 30fcb4251724e2db3c69425f441c9ffaf7d2a3d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:01 -0600 Subject: core/cortex-m0/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6476e2382f5f8a74b1e30380b9003d94a33e722a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729828 Reviewed-by: Jeremy Bettis --- core/cortex-m0/atomic.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 7ec856ed62..88b19bf534 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -16,22 +16,22 @@ * * There is no load/store exclusive on ARMv6-M, just disable interrupts */ -#define ATOMIC_OP(asm_op, a, v) \ -({ \ - uint32_t reg0, reg1; \ - \ - __asm__ __volatile__(".syntax unified\n" \ - " cpsid i\n" \ - " ldr %0, [%2]\n" \ - " mov %1, %0\n" \ - #asm_op" %0, %0, %3\n" \ - " str %0, [%2]\n" \ - " cpsie i\n" \ - : "=&l"(reg0), "=&l"(reg1) \ - : "l"(a), "r"(v) \ - : "cc", "memory"); \ - reg1; \ -}) +#define ATOMIC_OP(asm_op, a, v) \ + ({ \ + uint32_t reg0, reg1; \ + \ + __asm__ __volatile__(".syntax unified\n" \ + " cpsid i\n" \ + " ldr %0, [%2]\n" \ + " mov %1, %0\n" #asm_op \ + " %0, %0, %3\n" \ + " str %0, [%2]\n" \ + " cpsie i\n" \ + : "=&l"(reg0), "=&l"(reg1) \ + : "l"(a), "r"(v) \ + : "cc", "memory"); \ + reg1; \ + }) static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits) { @@ -62,8 +62,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr) " ldr %0, [%1]\n" " str %2, [%1]\n" " cpsie i\n" - : "=&l" (ret) - : "l" (addr), "r" (0) + : "=&l"(ret) + : "l"(addr), "r"(0) : "cc", "memory"); return ret; @@ -74,4 +74,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return ATOMIC_OP(ands, addr, bits); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1 From 593a73ce0a79514c567f6f6955d24a7c548db7af Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:05 -0600 Subject: common/queue_policies.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id218d09f5c5e4941564376819f79585f231a0871 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729729 Reviewed-by: Jeremy Bettis --- common/queue_policies.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/queue_policies.c b/common/queue_policies.c index 090c837fae..370990887c 100644 --- a/common/queue_policies.c +++ b/common/queue_policies.c @@ -29,14 +29,14 @@ void queue_remove_direct(struct queue_policy const *policy, size_t count) struct producer const null_producer = { .queue = NULL, - .ops = &((struct producer_ops const) { - .read = NULL, + .ops = &((struct producer_ops const){ + .read = NULL, }), }; struct consumer const null_consumer = { .queue = NULL, - .ops = &((struct consumer_ops const) { + .ops = &((struct consumer_ops const){ .written = NULL, }), }; -- cgit v1.2.1 From 4a1bc7c7d9e8d4a723d644d745e5fe84bec55f01 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:26:24 -0600 Subject: chip/npcx/wov.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I4f2b89c374e1ee1505411c58f09abfa5c01e7ffc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729448 Reviewed-by: Jeremy Bettis --- chip/npcx/wov.c | 387 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 191 insertions(+), 196 deletions(-) diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c index 5c3e915200..5796078c8f 100644 --- a/chip/npcx/wov.c +++ b/chip/npcx/wov.c @@ -26,7 +26,7 @@ #define CPRINTS(...) #else #define CPUTS(outstr) cputs(CC_AUDIO_CODEC, outstr) -#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ## args) +#define CPRINTS(format, args...) cprints(CC_AUDIO_CODEC, format, ##args) #endif /* WOV FIFO status. */ @@ -64,106 +64,106 @@ #define WOV_FMUL2_CLK_TUNING_DELAY_TIME (4 * 1000) /* The size of RAM buffer to store the voice data */ -#define VOICE_BUF_SIZE 16000 +#define VOICE_BUF_SIZE 16000 /* PLL setting options. */ struct wov_pll_set_options_val { - uint8_t pll_indv; /* Input Divider */ - uint16_t pll_fbdv; /* Feedback Divider */ - uint8_t pll_otdv1; /* Output devide 1. */ - uint8_t pll_otdv2; /* Output devide 2. */ + uint8_t pll_indv; /* Input Divider */ + uint16_t pll_fbdv; /* Feedback Divider */ + uint8_t pll_otdv1; /* Output devide 1. */ + uint8_t pll_otdv2; /* Output devide 2. */ uint32_t pll_ext_div; /* Index for the table pll_ext_div */ }; /* PLL External Divider Load Values. */ struct wov_pll_ext_div_val { - uint8_t pll_ediv; /* Required PLL external divider */ + uint8_t pll_ediv; /* Required PLL external divider */ uint8_t pll_ediv_dc; /* Required PLL external divider DC */ }; static const struct wov_pll_ext_div_val pll_ext_div[] = { - {0x2F, 0x78}, /* 12 */ - {0x57, 0x7C}, /* 13 */ - {0x2B, 0x7C}, /* 14 */ - {0x55, 0x7E}, /* 15 */ - {0x2A, 0x7E}, /* 16 */ - {0x15, 0x7F}, /* 17 */ - {0x4A, 0x7F}, /* 18 */ - {0x65, 0x3F}, /* 19 */ - {0x32, 0x3F}, /* 20 */ - {0x19, 0x5F}, /* 21 */ - {0x4C, 0x5F}, /* 22 */ - {0x66, 0x2F}, /* 23 */ - {0x73, 0x2F}, /* 24 */ - {0x39, 0x57}, /* 25 */ - {0x5C, 0x57}, /* 26 */ - {0x6E, 0x2B}, /* 27 */ - {0x77, 0x2B}, /* 28 */ - {0x3B, 0x55}, /* 29 */ - {0x5D, 0x55}, /* 30 */ - {0x2E, 0x2A}, /* 31 */ - {0x17, 0x2A}, /* 32 */ - {0x4B, 0x15}, /* 33 */ - {0x25, 0x15}, /* 34 */ - {0x52, 0x4A}, /* 35 */ - {0x69, 0x4A}, /* 36 */ - {0x34, 0x65}, /* 37 */ - {0x1A, 0x65}, /* 38 */ - {0x0D, 0x32}, /* 39 */ - {0x46, 0x32}, /* 40 */ - {0x63, 0x19}, /* 41 */ - {0x31, 0x19}, /* 42 */ - {0x58, 0x4C}, /* 43 */ - {0x6C, 0x4C}, /* 44 */ - {0x76, 0x66}, /* 45 */ - {0x7B, 0x66}, /* 46 */ - {0x3D, 0x73}, /* 47 */ - {0x5E, 0x73}, /* 48 */ - {0x6F, 0x39}, /* 49 */ - {0x37, 0x39}, /* 50 */ - {0x5B, 0x5C}, /* 51 */ - {0x2D, 0x5C}, /* 52 */ - {0x56, 0x6E}, /* 53 */ - {0x6B, 0x6E}, /* 54 */ - {0x35, 0x77}, /* 55 */ - {0x5A, 0x77}, /* 56 */ - {0x6D, 0x3B}, /* 57 */ - {0x36, 0x3B}, /* 58 */ - {0x1B, 0x5D}, /* 59 */ - {0x4D, 0x5D}, /* 60 */ - {0x26, 0x2E}, /* 61 */ - {0x13, 0x2E}, /* 62 */ - {0x49, 0x17}, /* 63 */ - {0x24, 0x17}, /* 64 */ - {0x12, 0x4B}, /* 65 */ - {0x09, 0x4B}, /* 66 */ - {0x44, 0x25} /* 67 */ + { 0x2F, 0x78 }, /* 12 */ + { 0x57, 0x7C }, /* 13 */ + { 0x2B, 0x7C }, /* 14 */ + { 0x55, 0x7E }, /* 15 */ + { 0x2A, 0x7E }, /* 16 */ + { 0x15, 0x7F }, /* 17 */ + { 0x4A, 0x7F }, /* 18 */ + { 0x65, 0x3F }, /* 19 */ + { 0x32, 0x3F }, /* 20 */ + { 0x19, 0x5F }, /* 21 */ + { 0x4C, 0x5F }, /* 22 */ + { 0x66, 0x2F }, /* 23 */ + { 0x73, 0x2F }, /* 24 */ + { 0x39, 0x57 }, /* 25 */ + { 0x5C, 0x57 }, /* 26 */ + { 0x6E, 0x2B }, /* 27 */ + { 0x77, 0x2B }, /* 28 */ + { 0x3B, 0x55 }, /* 29 */ + { 0x5D, 0x55 }, /* 30 */ + { 0x2E, 0x2A }, /* 31 */ + { 0x17, 0x2A }, /* 32 */ + { 0x4B, 0x15 }, /* 33 */ + { 0x25, 0x15 }, /* 34 */ + { 0x52, 0x4A }, /* 35 */ + { 0x69, 0x4A }, /* 36 */ + { 0x34, 0x65 }, /* 37 */ + { 0x1A, 0x65 }, /* 38 */ + { 0x0D, 0x32 }, /* 39 */ + { 0x46, 0x32 }, /* 40 */ + { 0x63, 0x19 }, /* 41 */ + { 0x31, 0x19 }, /* 42 */ + { 0x58, 0x4C }, /* 43 */ + { 0x6C, 0x4C }, /* 44 */ + { 0x76, 0x66 }, /* 45 */ + { 0x7B, 0x66 }, /* 46 */ + { 0x3D, 0x73 }, /* 47 */ + { 0x5E, 0x73 }, /* 48 */ + { 0x6F, 0x39 }, /* 49 */ + { 0x37, 0x39 }, /* 50 */ + { 0x5B, 0x5C }, /* 51 */ + { 0x2D, 0x5C }, /* 52 */ + { 0x56, 0x6E }, /* 53 */ + { 0x6B, 0x6E }, /* 54 */ + { 0x35, 0x77 }, /* 55 */ + { 0x5A, 0x77 }, /* 56 */ + { 0x6D, 0x3B }, /* 57 */ + { 0x36, 0x3B }, /* 58 */ + { 0x1B, 0x5D }, /* 59 */ + { 0x4D, 0x5D }, /* 60 */ + { 0x26, 0x2E }, /* 61 */ + { 0x13, 0x2E }, /* 62 */ + { 0x49, 0x17 }, /* 63 */ + { 0x24, 0x17 }, /* 64 */ + { 0x12, 0x4B }, /* 65 */ + { 0x09, 0x4B }, /* 66 */ + { 0x44, 0x25 } /* 67 */ }; /* WOV interrupts */ static const uint8_t wov_interupts[] = { - 0, /* VAD_INTEN */ - 1, /* VAD_WKEN */ - 8, /* CFIFO_NE_IE */ - 9, /* CFIFO_OIT_IE */ + 0, /* VAD_INTEN */ + 1, /* VAD_WKEN */ + 8, /* CFIFO_NE_IE */ + 9, /* CFIFO_OIT_IE */ 10, /* CFIFO_OWT_WE */ 11, /* CFIFO_OVRN_IE */ 12, /* I2S_FIFO_OVRN_IE */ - 13 /* I2S_FIFO_UNDRN_IE */ + 13 /* I2S_FIFO_UNDRN_IE */ }; struct wov_ppl_divider { uint16_t pll_frame_len; /* PLL frame length. */ - uint16_t pll_fbdv; /* PLL feedback divider. */ - uint8_t pll_indv; /* PLL Input Divider. */ - uint8_t pll_otdv1; /* PLL Output Divider 1. */ - uint8_t pll_otdv2; /* PLL Output Divider 2. */ - uint8_t pll_ediv; /* PLL External Divide Factor. */ + uint16_t pll_fbdv; /* PLL feedback divider. */ + uint8_t pll_indv; /* PLL Input Divider. */ + uint8_t pll_otdv1; /* PLL Output Divider 1. */ + uint8_t pll_otdv2; /* PLL Output Divider 2. */ + uint8_t pll_ediv; /* PLL External Divide Factor. */ }; struct wov_cfifo_buf { uint32_t *buf; /* Pointer to a buffer. */ - int size; /* Buffer size in words. */ + int size; /* Buffer size in words. */ }; struct wov_config wov_conf; @@ -205,11 +205,11 @@ void wov_cfifo_read_handler_l(uint32_t num_elements) cfifo_buf.size -= num_elements; } -static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, - int32_t total_div, int32_t vco_freq, - struct wov_ppl_divider *pll_div) +static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, int32_t total_div, + int32_t vco_freq, + struct wov_ppl_divider *pll_div) { - int32_t d_1, d_2, d_e; + int32_t d_1, d_2, d_e; /* * Please see comments in wov_calc_pll_div_l function below. @@ -221,10 +221,10 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, continue; if (total_div == (d_in * d_e * d_1 * d_2)) { - pll_div->pll_indv = d_in; + pll_div->pll_indv = d_in; pll_div->pll_otdv1 = d_1; pll_div->pll_otdv2 = d_2; - pll_div->pll_ediv = d_e; + pll_div->pll_ediv = d_e; return EC_SUCCESS; } } @@ -243,7 +243,8 @@ static enum ec_error_list wov_calc_pll_div_s(int32_t d_in, * @return None */ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq, - uint32_t sample_rate, struct wov_ppl_divider *pll_div) + uint32_t sample_rate, + struct wov_ppl_divider *pll_div) { int32_t d_f; int32_t total_div; @@ -292,12 +293,11 @@ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq, if ((vco_freq < 500) || (vco_freq > 1600)) continue; if (wov_calc_pll_div_s(d_in, total_div, - vco_freq, pll_div) == - EC_SUCCESS) { - pll_div->pll_fbdv = d_f; + vco_freq, + pll_div) == EC_SUCCESS) { + pll_div->pll_fbdv = d_f; return EC_SUCCESS; } - } } } @@ -340,12 +340,13 @@ static enum ec_error_list wov_set_i2s_config_l(void) int32_t start_delay_0, start_delay_1; ret_code = wov_calc_pll_div_l(wov_conf.i2s_clock, - wov_conf.sample_per_sec, &pll_div); + wov_conf.sample_per_sec, &pll_div); if (ret_code == EC_SUCCESS) { /* Configure the PLL. */ - ret_code = wov_pll_clk_div_config( - pll_div.pll_otdv1, pll_div.pll_otdv2, pll_div.pll_fbdv, - pll_div.pll_indv); + ret_code = wov_pll_clk_div_config(pll_div.pll_otdv1, + pll_div.pll_otdv2, + pll_div.pll_fbdv, + pll_div.pll_indv); if (ret_code != EC_SUCCESS) return ret_code; @@ -414,10 +415,10 @@ static enum ec_error_list wov_set_i2s_config_l(void) udelay(100); ret_code = wov_i2s_channel_config(0, wov_conf.bit_depth, - trigger_0, start_delay_0); + trigger_0, start_delay_0); ret_code = wov_i2s_channel_config(1, wov_conf.bit_depth, - trigger_1, start_delay_1); + trigger_1, start_delay_1); } return EC_SUCCESS; @@ -471,14 +472,14 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_LEFT: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x00); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, APM_OUT_MIX_NO_INPUT); apm_set_vad_input_channel(APM_IN_LEFT); @@ -493,11 +494,11 @@ static enum ec_error_list wov_set_mic_source_l(void) SET_FIELD(NPCX_WOV_FIFO_CNT, NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_CROSS_INPUT, - APM_OUT_MIX_NO_INPUT); + APM_OUT_MIX_NO_INPUT); apm_set_vad_input_channel(APM_IN_RIGHT); wov_i2s_channel1_disable(1); break; @@ -505,16 +506,16 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_MONO: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x02); + 0x02); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x02); + 0x02); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, - APM_OUT_MIX_NORMAL_INPUT); + APM_OUT_MIX_NORMAL_INPUT); apm_set_vad_input_channel(APM_IN_AVERAGE_LEFT_RIGHT); wov_i2s_channel1_disable(0); break; @@ -522,14 +523,14 @@ static enum ec_error_list wov_set_mic_source_l(void) case WOV_SRC_STEREO: if (wov_conf.bit_depth == 16) SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x01); else SET_FIELD(NPCX_WOV_FIFO_CNT, - NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); + NPCX_WOV_FIFO_CNT_CFIFO_ISEL, 0x03); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT, - 0x01); + 0x01); SET_FIELD(NPCX_APM_CR_DMIC, NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT, - 0x01); + 0x01); apm_digital_mixer_config(APM_OUT_MIX_NORMAL_INPUT, APM_OUT_MIX_NORMAL_INPUT); wov_i2s_channel1_disable(0); @@ -586,7 +587,7 @@ static void wov_interrupt_handler(void) wov_inten = GET_FIELD(NPCX_WOV_WOV_INTEN, NPCX_WOV_STATUS_BITS); wov_status = wov_inten & - GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS); + GET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS); /* * Voice activity detected. @@ -602,7 +603,7 @@ static void wov_interrupt_handler(void) WOV_CALLBACK(WOV_EVENT_ERROR_CORE_FIFO_OVERRUN); wov_core_fifo_reset(); } else if (WOV_IS_CFIFO_INT_THRESHOLD(wov_status) && - (cfifo_buf.buf != NULL)) { + (cfifo_buf.buf != NULL)) { /* * Core FIFO threshold or FIFO not empty event occurred. * - Read data from core FIFO to the buffer. @@ -635,7 +636,6 @@ static void wov_interrupt_handler(void) wov_i2s_fifo_reset(); } - /* Clear the WoV status register. */ SET_FIELD(NPCX_WOV_STATUS, NPCX_WOV_STATUS_BITS, wov_status); } @@ -651,19 +651,17 @@ DECLARE_IRQ(NPCX_IRQ_WOV, wov_interrupt_handler, 4); static void wov_fmul2_enable(int enable) { if (enable) { - /* If clock disabled, then enable it. */ if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) { + NPCX_FMUL2_FM2CTRL_FMUL2_DIS)) { /* Enable clock tuning. */ CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_TUNE_DIS); + NPCX_FMUL2_FM2CTRL_TUNE_DIS); /* Enable clock. */ CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_FMUL2_DIS); + NPCX_FMUL2_FM2CTRL_FMUL2_DIS); udelay(WOV_FMUL2_CLK_TUNING_DELAY_TIME); - } } else SET_BIT(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS); @@ -688,7 +686,7 @@ void wov_fmul2_conf_tuning(void) { /* Check if FMUL2 is enabled, then do nothing. */ if (IS_BIT_SET(NPCX_FMUL2_FM2CTRL, NPCX_FMUL2_FM2CTRL_FMUL2_DIS) == - 0x00) + 0x00) return; /* Enable clock tuning. */ @@ -968,7 +966,6 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src) wov_fmul2_enable(0); else wov_pll_enable(0); - } /** @@ -981,9 +978,9 @@ void wov_set_clk_selection(enum wov_clk_src_sel clk_src) * PLL External Divider Load Values table. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_pll_clk_ext_div_config( - enum wov_pll_ext_div_sel ext_div_sel, - uint32_t div_factor) +enum ec_error_list +wov_pll_clk_ext_div_config(enum wov_pll_ext_div_sel ext_div_sel, + uint32_t div_factor) { /* Sets the clock division factor for the PLL external divider. * The divide factor should be in the range of 2 to 67. @@ -1045,13 +1042,13 @@ void wov_pll_enable(int enable) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_pll_clk_div_config(uint32_t out_div_1, - uint32_t out_div_2, - uint32_t feedback_div, - uint32_t in_div) + uint32_t out_div_2, + uint32_t feedback_div, + uint32_t in_div) { /* Parameter check. */ - if ((out_div_1 < 1) || (out_div_1 > 7) || - (out_div_2 < 1) || (out_div_2 > 7)) + if ((out_div_1 < 1) || (out_div_1 > 7) || (out_div_2 < 1) || + (out_div_2 > 7)) return EC_ERROR_INVAL; /* @@ -1255,7 +1252,7 @@ int wov_set_buffer(uint32_t *buf, int size_in_words) cfifo_threshold = wov_get_cfifo_threshold_l(); if (size_in_words != - ((size_in_words / cfifo_threshold) * cfifo_threshold)) + ((size_in_words / cfifo_threshold) * cfifo_threshold)) return EC_ERROR_INVAL; cfifo_buf.buf = buf; @@ -1298,21 +1295,17 @@ void wov_apm_active(int enable) * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_global_config( - enum wov_floating_mode i2s_hiz_data, - enum wov_floating_mode i2s_hiz, - enum wov_clk_inverted_mode clk_invert, - int out_pull_en, - enum wov_pull_upd_down_sel out_pull_mode, - int in_pull_en, - enum wov_pull_upd_down_sel in_pull_mode, - enum wov_test_mode test_mode) + enum wov_floating_mode i2s_hiz_data, enum wov_floating_mode i2s_hiz, + enum wov_clk_inverted_mode clk_invert, int out_pull_en, + enum wov_pull_upd_down_sel out_pull_mode, int in_pull_en, + enum wov_pull_upd_down_sel in_pull_mode, enum wov_test_mode test_mode) { /* Check the parameters correctness. */ if ((i2s_hiz_data == WOV_FLOATING) && - ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), - NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0) || - (GET_FIELD(NPCX_WOV_I2S_CNTL(1), - NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == 0))) + ((GET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == + 0) || + (GET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL) == + 0))) return EC_ERROR_INVAL; /* Set the parameters. */ @@ -1375,9 +1368,9 @@ enum ec_error_list wov_i2s_global_config( * @return EC_ERROR_INVAL or EC_SUCCESS */ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, - uint32_t bit_count, - enum wov_i2s_chan_trigger trigger, - int32_t start_delay) + uint32_t bit_count, + enum wov_i2s_chan_trigger trigger, + int32_t start_delay) { /* Check the parameters correctnes. */ if ((channel_num != 0) && (channel_num != 1)) @@ -1392,7 +1385,7 @@ enum ec_error_list wov_i2s_channel_config(uint32_t channel_num, /* Set the parameters. */ SET_FIELD(NPCX_WOV_I2S_CNTL(channel_num), NPCX_WOV_I2S_CNTL_I2S_BCNT, - (bit_count - 1)); + (bit_count - 1)); if (trigger == WOV_I2S_SAMPLED_1_AFTER_0) CLEAR_BIT(NPCX_WOV_I2S_CNTL(channel_num), @@ -1459,8 +1452,8 @@ int wov_set_sample_depth(int bits_num) if (wov_conf.mode != WOV_MODE_OFF) return EC_ERROR_INVALID_CONFIG; - if ((bits_num != 16) && (bits_num != 18) && - (bits_num != 20) && (bits_num != 24)) + if ((bits_num != 16) && (bits_num != 18) && (bits_num != 20) && + (bits_num != 24)) return EC_ERROR_INVAL; wov_conf.bit_depth = bits_num; @@ -1529,8 +1522,8 @@ void wov_set_gain(int left_chan_gain, int right_chan_gain) wov_conf.left_chan_gain = left_chan_gain; wov_conf.right_chan_gain = right_chan_gain; - (void) apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT, - left_chan_gain, right_chan_gain); + (void)apm_adc_gain_config(APM_ADC_CHAN_GAINS_INDEPENDENT, + left_chan_gain, right_chan_gain); } /** @@ -1571,10 +1564,10 @@ void wov_enable_agc(int enable) * @param min_applied_gain - Minimum Gain Value to apply to the ADC path. * @return EC_ERROR_INVAL or EC_SUCCESS */ -enum ec_error_list wov_set_agc_config(int stereo, float target, - int noise_gate_threshold, uint8_t hold_time, - uint16_t attack_time, uint16_t decay_time, - float max_applied_gain, float min_applied_gain) +enum ec_error_list +wov_set_agc_config(int stereo, float target, int noise_gate_threshold, + uint8_t hold_time, uint16_t attack_time, uint16_t decay_time, + float max_applied_gain, float min_applied_gain) { int target_code; int ngth_code; @@ -1607,7 +1600,7 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (attack_time_code = 0; attack_time_code <= 0x0F; - attack_time_code++) { + attack_time_code++) { if (((attack_time_code + 1) * 32) == attack_time) break; } @@ -1622,15 +1615,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (max_applied_gain_code = 0; max_applied_gain_code < 16; - max_applied_gain_code++) { + max_applied_gain_code++) { if ((max_applied_gain_code * 1.5) == max_applied_gain) break; } if (max_applied_gain_code == 16) { for (max_applied_gain_code = 18; max_applied_gain_code < 32; - max_applied_gain_code++) { + max_applied_gain_code++) { if (((max_applied_gain_code * 1.5) - 4) == - max_applied_gain) + max_applied_gain) break; } } @@ -1638,15 +1631,15 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; for (min_applied_gain_code = 0; min_applied_gain_code < 16; - min_applied_gain_code++) { + min_applied_gain_code++) { if ((min_applied_gain_code * 1.5) == min_applied_gain) break; } if (min_applied_gain_code == 16) { for (min_applied_gain_code = 18; min_applied_gain_code < 32; - min_applied_gain_code++) { + min_applied_gain_code++) { if (((min_applied_gain_code * 1.5) - 4) == - min_applied_gain) + min_applied_gain) break; } } @@ -1654,14 +1647,14 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, return EC_ERROR_INVAL; gain_cfg.stereo_enable = stereo, - gain_cfg.agc_target = (enum apm_adc_target_out_level) target_code; + gain_cfg.agc_target = (enum apm_adc_target_out_level)target_code; gain_cfg.nois_gate_en = (noise_gate_threshold != 0); - gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold) ngth_code; - gain_cfg.hold_time = (enum apm_agc_adj_hold_time) hold_time; - gain_cfg.attack_time = (enum apm_gain_ramp_time) attack_time_code; - gain_cfg.decay_time = (enum apm_gain_ramp_time) decay_time_code; - gain_cfg.gain_max = (enum apm_gain_values) max_applied_gain_code; - gain_cfg.gain_min = (enum apm_gain_values) min_applied_gain_code; + gain_cfg.nois_gate_thold = (enum apm_noise_gate_threshold)ngth_code; + gain_cfg.hold_time = (enum apm_agc_adj_hold_time)hold_time; + gain_cfg.attack_time = (enum apm_gain_ramp_time)attack_time_code; + gain_cfg.decay_time = (enum apm_gain_ramp_time)decay_time_code; + gain_cfg.gain_max = (enum apm_gain_values)max_applied_gain_code; + gain_cfg.gain_min = (enum apm_gain_values)min_applied_gain_code; ret_code = apm_adc_auto_gain_config(&gain_cfg); @@ -1676,7 +1669,6 @@ enum ec_error_list wov_set_agc_config(int stereo, float target, */ int wov_set_vad_sensitivity(int sensitivity_db) { - if ((sensitivity_db < 0) || (sensitivity_db > 31)) return EC_ERROR_INVAL; @@ -1752,27 +1744,27 @@ void wov_set_i2s_bclk(uint32_t i2s_clock) * @return EC error code. */ enum ec_error_list wov_set_i2s_tdm_config(int ch0_delay, int ch1_delay, - uint32_t flags) + uint32_t flags) { if (wov_conf.mode != WOV_MODE_OFF) return EC_ERROR_INVALID_CONFIG; - if ((ch0_delay < 0) || (ch0_delay > 496) || - (ch1_delay < -1) || (ch1_delay > 496)) + if ((ch0_delay < 0) || (ch0_delay > 496) || (ch1_delay < -1) || + (ch1_delay > 496)) return EC_ERROR_INVAL; wov_conf.i2s_start_delay_0 = ch0_delay; wov_conf.i2s_start_delay_1 = ch1_delay; SET_FIELD(NPCX_WOV_I2S_CNTL(0), NPCX_WOV_I2S_CNTL_I2S_ST_DEL, - ch0_delay); + ch0_delay); if (ch1_delay == -1) wov_i2s_channel1_disable(1); else { wov_i2s_channel1_disable(0); SET_FIELD(NPCX_WOV_I2S_CNTL(1), NPCX_WOV_I2S_CNTL_I2S_ST_DEL, - ch1_delay); + ch1_delay); } if (flags & 0x0001) @@ -1820,7 +1812,7 @@ void wov_handle_event(enum wov_events event) } #ifdef DEBUG_AUDIO_CODEC -static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0}; +static uint32_t voice_buffer[VOICE_BUF_SIZE] = { 0 }; /* voice data 16Khz 2ch 16bit 1s */ static int command_wov(int argc, char **argv) @@ -1845,8 +1837,9 @@ static int command_wov(int argc, char **argv) /* Start to capature voice data and store in RAM buffer */ if (strcasecmp(argv[1], "capram") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) { + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) { CPRINTS("Start RAM Catpure..."); wov_start_ram_capture(); return EC_SUCCESS; @@ -1980,8 +1973,9 @@ static int command_wov(int argc, char **argv) wov_set_mode(WOV_MODE_VAD); } else if (strcasecmp(argv[2], "ram") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) wov_set_mode(WOV_MODE_RAM); else return EC_ERROR_INVAL; @@ -1989,8 +1983,9 @@ static int command_wov(int argc, char **argv) wov_set_mode(WOV_MODE_I2S); } else if (strcasecmp(argv[2], "rami2s") == 0) { if (wov_set_buffer((uint32_t *)voice_buffer, - sizeof(voice_buffer) / sizeof(uint32_t)) - == EC_SUCCESS) + sizeof(voice_buffer) / + sizeof(uint32_t)) == + EC_SUCCESS) wov_set_mode(WOV_MODE_RAM_AND_I2S); else return EC_ERROR_INVAL; @@ -2013,7 +2008,7 @@ static int command_wov(int argc, char **argv) if (strcasecmp(argv[1], "fmul2") == 0) { if (strcasecmp(argv[2], "enable") == 0) { CLEAR_BIT(NPCX_FMUL2_FM2CTRL, - NPCX_FMUL2_FM2CTRL_TUNE_DIS); + NPCX_FMUL2_FM2CTRL_TUNE_DIS); return EC_SUCCESS; } if (strcasecmp(argv[2], "disable") == 0) { @@ -2050,22 +2045,22 @@ static int command_wov(int argc, char **argv) } DECLARE_CONSOLE_COMMAND(wov, command_wov, - "init\n" - "mute \n" - "capram\n" - "cfgsrc \n" - "cfgbit <16|18|20|24>\n" - "cfgsfs <8000|12000|16000|24000|32000|48000>\n" - "cfgbck <32fs|48fs|64fs|128fs|256fs>\n" - "cfgfmt \n" - "cfgmod \n" - "cfgtdm [0~496 0~496 0~3]>\n" - "cfgdckV <0.75|1.0|1.2|2.4|3.0>\n" - "cfgdckR <0.75|1.0|1.2|2.4|3.0>\n" - "cfgdckI <0.75|1.0|1.2|2.4|3.0>\n" - "cfgget\n" - "fmul2 \n" - "vadsens <0~31>\n" - "gain <0~31>", - "wov configuration"); + "init\n" + "mute \n" + "capram\n" + "cfgsrc \n" + "cfgbit <16|18|20|24>\n" + "cfgsfs <8000|12000|16000|24000|32000|48000>\n" + "cfgbck <32fs|48fs|64fs|128fs|256fs>\n" + "cfgfmt \n" + "cfgmod \n" + "cfgtdm [0~496 0~496 0~3]>\n" + "cfgdckV <0.75|1.0|1.2|2.4|3.0>\n" + "cfgdckR <0.75|1.0|1.2|2.4|3.0>\n" + "cfgdckI <0.75|1.0|1.2|2.4|3.0>\n" + "cfgget\n" + "fmul2 \n" + "vadsens <0~31>\n" + "gain <0~31>", + "wov configuration"); #endif -- cgit v1.2.1 From d3e576d23c67f479ad29505d5acdcff53425cab8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:29:55 -0600 Subject: zephyr/emul/tcpc/emul_tcpci_partner_snk.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1c26c944c7d4dd4401449244c763d16f9bd02e36 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730707 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci_partner_snk.c | 73 +++++++++++++++---------------- 1 file changed, 35 insertions(+), 38 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_snk.c b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c index 7ae3662170..6ac498151d 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_snk.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_snk.c @@ -16,9 +16,9 @@ LOG_MODULE_REGISTER(tcpci_snk_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); #include "usb_pd.h" /** Length of PDO, RDO and BIST request object in SOP message in bytes */ -#define TCPCI_MSG_DO_LEN 4 +#define TCPCI_MSG_DO_LEN 4 /** Length of header in SOP message in bytes */ -#define TCPCI_MSG_HEADER_LEN 2 +#define TCPCI_MSG_HEADER_LEN 2 /** * @brief Get number of PDOs that will be present in sink capability message @@ -51,18 +51,17 @@ static int tcpci_snk_emul_num_of_pdos(struct tcpci_snk_emul_data *data) * @return -ENOMEM when there is no free memory for message * @return -EINVAL on TCPCI emulator add RX message error */ -static int tcpci_snk_emul_send_capability_msg( - struct tcpci_snk_emul_data *data, - struct tcpci_partner_data *common_data, - uint64_t delay) +static int +tcpci_snk_emul_send_capability_msg(struct tcpci_snk_emul_data *data, + struct tcpci_partner_data *common_data, + uint64_t delay) { int pdos; /* Find number of PDOs */ pdos = tcpci_snk_emul_num_of_pdos(data); - return tcpci_partner_send_data_msg(common_data, - PD_DATA_SINK_CAP, + return tcpci_partner_send_data_msg(common_data, PD_DATA_SINK_CAP, data->pdo, pdos, delay); } @@ -95,8 +94,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo, /* Voltage doesn't match */ return -1; } - missing_current = PDO_FIXED_CURRENT(snk_pdo) - - PDO_FIXED_CURRENT(src_pdo); + missing_current = + PDO_FIXED_CURRENT(snk_pdo) - PDO_FIXED_CURRENT(src_pdo); break; case PDO_TYPE_BATTERY: if ((PDO_BATT_MIN_VOLTAGE(snk_pdo) < @@ -111,8 +110,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo, * = P / V * 5 [A] = P / V * 500 * 10[mA] */ missing_current = (PDO_BATT_MAX_POWER(snk_pdo) - - PDO_BATT_MAX_POWER(src_pdo)) * 500 / - PDO_BATT_MAX_VOLTAGE(src_pdo); + PDO_BATT_MAX_POWER(src_pdo)) * + 500 / PDO_BATT_MAX_VOLTAGE(src_pdo); break; case PDO_TYPE_VARIABLE: if ((PDO_VAR_MIN_VOLTAGE(snk_pdo) < @@ -147,8 +146,8 @@ static int tcpci_snk_emul_are_pdos_complementary(uint32_t src_pdo, * @return PDO on success * @return 0 when there is no PDO of given index in message */ -static uint32_t tcpci_snk_emul_get_pdo_from_cap( - const struct tcpci_emul_msg *msg, int pdo_num) +static uint32_t +tcpci_snk_emul_get_pdo_from_cap(const struct tcpci_emul_msg *msg, int pdo_num) { int addr; @@ -240,10 +239,10 @@ static uint32_t tcpci_snk_emul_create_rdo(uint32_t src_pdo, uint32_t snk_pdo, * @param common_data Pointer to common TCPCI partner data * @param msg Source capability message */ -static void tcpci_snk_emul_handle_source_cap( - struct tcpci_snk_emul_data *data, - struct tcpci_partner_data *common_data, - const struct tcpci_emul_msg *msg) +static void +tcpci_snk_emul_handle_source_cap(struct tcpci_snk_emul_data *data, + struct tcpci_partner_data *common_data, + const struct tcpci_emul_msg *msg) { uint32_t rdo = 0; uint32_t pdo; @@ -269,11 +268,10 @@ static void tcpci_snk_emul_handle_source_cap( for (int i = skip_first_pdo; i < snk_pdos; i++) { missing_current = tcpci_snk_emul_are_pdos_complementary( - pdo, data->pdo[i]); + pdo, data->pdo[i]); if (missing_current == 0) { - rdo = tcpci_snk_emul_create_rdo(pdo, - data->pdo[i], - pdo_num + 1); + rdo = tcpci_snk_emul_create_rdo( + pdo, data->pdo[i], pdo_num + 1); break; } } @@ -363,10 +361,10 @@ void tcpci_snk_emul_clear_alert_received(struct tcpci_snk_emul_data *data) * @param TCPCI_PARTNER_COMMON_MSG_HANDLED Message was handled * @param TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED Message wasn't handled */ -static enum tcpci_partner_handler_res tcpci_snk_emul_handle_sop_msg( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data, - const struct tcpci_emul_msg *msg) +static enum tcpci_partner_handler_res +tcpci_snk_emul_handle_sop_msg(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data, + const struct tcpci_emul_msg *msg) { struct tcpci_snk_emul_data *data = CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext); @@ -404,20 +402,19 @@ static enum tcpci_partner_handler_res tcpci_snk_emul_handle_sop_msg( __ASSERT(data->wait_for_ps_rdy, "Unexpected PS RDY message"); tcpci_snk_emul_stop_partner_transition_timer( - data, common_data); + data, common_data); data->pd_completed = true; return TCPCI_PARTNER_COMMON_MSG_HANDLED; case PD_CTRL_REJECT: tcpci_partner_stop_sender_response_timer(common_data); /* Request rejected. Ask for capabilities again. */ - tcpci_partner_send_control_msg(common_data, - PD_CTRL_GET_SOURCE_CAP, - 0); + tcpci_partner_send_control_msg( + common_data, PD_CTRL_GET_SOURCE_CAP, 0); return TCPCI_PARTNER_COMMON_MSG_HANDLED; case PD_CTRL_ACCEPT: tcpci_partner_stop_sender_response_timer(common_data); tcpci_snk_emul_start_partner_transition_timer( - data, common_data); + data, common_data); return TCPCI_PARTNER_COMMON_MSG_HANDLED; default: return TCPCI_PARTNER_COMMON_MSG_NOT_HANDLED; @@ -459,9 +456,9 @@ static void tcpci_snk_emul_hard_reset(struct tcpci_partner_extension *ext, * @return 0 on success * @return negative on TCPCI connect error */ -static int tcpci_snk_emul_connect_to_tcpci( - struct tcpci_partner_extension *ext, - struct tcpci_partner_data *common_data) +static int +tcpci_snk_emul_connect_to_tcpci(struct tcpci_partner_extension *ext, + struct tcpci_partner_data *common_data) { struct tcpci_snk_emul_data *data = CONTAINER_OF(ext, struct tcpci_snk_emul_data, ext); @@ -489,10 +486,10 @@ struct tcpci_partner_extension_ops tcpci_snk_emul_ops = { .connect = tcpci_snk_emul_connect_to_tcpci, }; -struct tcpci_partner_extension *tcpci_snk_emul_init( - struct tcpci_snk_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext) +struct tcpci_partner_extension * +tcpci_snk_emul_init(struct tcpci_snk_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext) { struct tcpci_partner_extension *snk_ext = &data->ext; -- cgit v1.2.1 From be1ecccc583ee24f059fd3d5efbe4222ac47ea21 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:00 -0600 Subject: board/icarus/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2ebeb1763e9194a7cafd9957ba9e5545ec307149 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728510 Reviewed-by: Jeremy Bettis --- board/icarus/board.c | 88 +++++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 46 deletions(-) diff --git a/board/icarus/board.c b/board/icarus/board.c index 4dcb55d472..762a1c7c31 100644 --- a/board/icarus/board.c +++ b/board/icarus/board.c @@ -40,8 +40,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #include "gpio_list.h" @@ -51,18 +51,21 @@ * The connector has 24 pins total, and there is no pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {GPIO_KSO_H, 4}, {GPIO_KSO_H, 0}, {GPIO_KSO_H, 1}, - {GPIO_KSO_H, 3}, {GPIO_KSO_H, 2}, {-1, -1}, {-1, -1}, - {GPIO_KSO_L, 5}, {GPIO_KSO_L, 6}, {-1, -1}, {GPIO_KSO_L, 3}, - {GPIO_KSO_L, 2}, {GPIO_KSI, 0}, {GPIO_KSO_L, 1}, {GPIO_KSO_L, 4}, - {GPIO_KSI, 3}, {GPIO_KSI, 2}, {GPIO_KSO_L, 0}, {GPIO_KSI, 5}, - {GPIO_KSI, 4}, {GPIO_KSO_L, 7}, {GPIO_KSI, 6}, {GPIO_KSI, 7}, - {GPIO_KSI, 1}, {-1, -1}, {GPIO_KSO_H, 5}, {-1, -1}, - {GPIO_KSO_H, 6}, {-1, -1}, {-1, -1}, + { -1, -1 }, { GPIO_KSO_H, 4 }, { GPIO_KSO_H, 0 }, + { GPIO_KSO_H, 1 }, { GPIO_KSO_H, 3 }, { GPIO_KSO_H, 2 }, + { -1, -1 }, { -1, -1 }, { GPIO_KSO_L, 5 }, + { GPIO_KSO_L, 6 }, { -1, -1 }, { GPIO_KSO_L, 3 }, + { GPIO_KSO_L, 2 }, { GPIO_KSI, 0 }, { GPIO_KSO_L, 1 }, + { GPIO_KSO_L, 4 }, { GPIO_KSI, 3 }, { GPIO_KSI, 2 }, + { GPIO_KSO_L, 0 }, { GPIO_KSI, 5 }, { GPIO_KSI, 4 }, + { GPIO_KSO_L, 7 }, { GPIO_KSI, 6 }, { GPIO_KSI, 7 }, + { GPIO_KSI, 1 }, { -1, -1 }, { GPIO_KSO_H, 5 }, + { -1, -1 }, { GPIO_KSO_H, 6 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* Wake-up pins for hibernate */ const enum gpio_signal hibernate_wake_pins[] = { @@ -75,39 +78,33 @@ const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH1}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH2}, - [ADC_VBUS] = {"VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, - CHIP_ADC_CH0}, + [ADC_BOARD_ID] = { "BOARD_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH1 }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", ADC_MAX_MVOLT, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH2 }, + [ADC_VBUS] = { "VBUS", ADC_MAX_MVOLT * 10, ADC_READ_MAX + 1, 0, + CHIP_ADC_CH0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = IT83XX_I2C_CH_C, - .kbps = 400, - .scl = GPIO_I2C_C_SCL, - .sda = GPIO_I2C_C_SDA - }, - { - .name = "other", - .port = IT83XX_I2C_CH_B, - .kbps = 100, - .scl = GPIO_I2C_B_SCL, - .sda = GPIO_I2C_B_SDA - }, - { - .name = "battery", - .port = IT83XX_I2C_CH_A, - .kbps = 100, - .scl = GPIO_I2C_A_SCL, - .sda = GPIO_I2C_A_SDA - }, + { .name = "typec", + .port = IT83XX_I2C_CH_C, + .kbps = 400, + .scl = GPIO_I2C_C_SCL, + .sda = GPIO_I2C_C_SDA }, + { .name = "other", + .port = IT83XX_I2C_CH_B, + .kbps = 100, + .scl = GPIO_I2C_B_SCL, + .sda = GPIO_I2C_B_SDA }, + { .name = "battery", + .port = IT83XX_I2C_CH_A, + .kbps = 100, + .scl = GPIO_I2C_A_SCL, + .sda = GPIO_I2C_A_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -115,8 +112,8 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -139,8 +136,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -204,12 +200,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) -- cgit v1.2.1 From f2733dc3d8b4808e4509f37fabd640aa203bbc1b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:44:26 -0600 Subject: board/lazor/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I071d4f2fb2b7e4e39aba0d0340e1ca297dab3676 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728629 Reviewed-by: Jeremy Bettis --- board/lazor/led.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/lazor/led.c b/board/lazor/led.c index f9c91c1c6a..404b6b0956 100644 --- a/board/lazor/led.c +++ b/board/lazor/led.c @@ -32,15 +32,15 @@ enum led_color { LED_OFF = 0, LED_AMBER, LED_BLUE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_Y_C1, - (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_AMBER) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_B_C1, - (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_BLUE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -- cgit v1.2.1 From 2a1e548dc461046adc15d216c020c09665c2d53e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:20:17 -0600 Subject: chip/mchp/spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: If1bf877389c160a35b5c040f6f057298b22c98a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729300 Reviewed-by: Jeremy Bettis --- chip/mchp/spi.c | 63 ++++++++++++++++++++------------------------------------- 1 file changed, 22 insertions(+), 41 deletions(-) diff --git a/chip/mchp/spi.c b/chip/mchp/spi.c index 48712e8b7e..34db702f56 100644 --- a/chip/mchp/spi.c +++ b/chip/mchp/spi.c @@ -23,7 +23,7 @@ #include "tfdp_chip.h" #define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ##args) #define SPI_BYTE_TRANSFER_TIMEOUT_US (3 * MSEC) #define SPI_BYTE_TRANSFER_POLL_INTERVAL_US 100 @@ -33,49 +33,31 @@ #endif static const struct dma_option spi_rx_option[] = { - { - MCHP_DMAC_QMSPI0_RX, - (void *)(MCHP_QMSPI0_RX_FIFO_ADDR), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_QMSPI0_RX, (void *)(MCHP_QMSPI0_RX_FIFO_ADDR), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) #if CONFIG_MCHP_GPSPI & 0x01 - { - MCHP_DMAC_SPI0_RX, - (void *)&MCHP_SPI_RD(0), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_SPI0_RX, (void *)&MCHP_SPI_RD(0), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #endif #if CONFIG_MCHP_GPSPI & 0x02 - { - MCHP_DMAC_SPI1_RX, - (void *)&MCHP_SPI_RD(1), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_SPI1_RX, (void *)&MCHP_SPI_RD(1), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #endif #endif }; static const struct dma_option spi_tx_option[] = { - { - MCHP_DMAC_QMSPI0_TX, - (void *)(MCHP_QMSPI0_TX_FIFO_ADDR), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_QMSPI0_TX, (void *)(MCHP_QMSPI0_TX_FIFO_ADDR), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) #if CONFIG_MCHP_GPSPI & 0x01 - { - MCHP_DMAC_SPI0_TX, - (void *)&MCHP_SPI_TD(0), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_SPI0_TX, (void *)&MCHP_SPI_TD(0), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #endif #if CONFIG_MCHP_GPSPI & 0x02 - { - MCHP_DMAC_SPI1_TX, - (void *)&MCHP_SPI_TD(1), - MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM - }, + { MCHP_DMAC_SPI1_TX, (void *)&MCHP_SPI_TD(1), + MCHP_DMA_XFER_SIZE(1) + MCHP_DMA_INC_MEM }, #endif #endif }; @@ -131,8 +113,7 @@ static void spi_mutex_unlock(uint8_t hw_port) * Public SPI interface */ -const void *spi_dma_option(const struct spi_device_t *spi_device, - int is_tx) +const void *spi_dma_option(const struct spi_device_t *spi_device, int is_tx) { uint32_t n; @@ -157,8 +138,8 @@ const void *spi_dma_option(const struct spi_device_t *spi_device, } int spi_transaction_async(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rc; @@ -169,13 +150,13 @@ int spi_transaction_async(const struct spi_device_t *spi_device, #if defined(CONFIG_MCHP_GPSPI) && !defined(LFW) case GPSPI0_PORT: case GPSPI1_PORT: - rc = gpspi_transaction_async(spi_device, txdata, - txlen, rxdata, rxlen); + rc = gpspi_transaction_async(spi_device, txdata, txlen, rxdata, + rxlen); break; #endif case QMSPI0_PORT: - rc = qmspi_transaction_async(spi_device, txdata, - txlen, rxdata, rxlen); + rc = qmspi_transaction_async(spi_device, txdata, txlen, rxdata, + rxlen); break; default: rc = EC_ERROR_INVAL; @@ -243,8 +224,8 @@ int spi_transaction_wait(const struct spi_device_t *spi_device) * without the overhead of DMA setup. */ int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) + const uint8_t *txdata, int txlen, uint8_t *rxdata, + int rxlen) { int rc; -- cgit v1.2.1 From 96afbd5bc9850f9349f667adc8ac41382e9a60a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:40:21 -0600 Subject: zephyr/test/crc/main.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id086449de6ead283284948e4064285667529a8a4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730924 Reviewed-by: Jeremy Bettis --- zephyr/test/crc/main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/zephyr/test/crc/main.c b/zephyr/test/crc/main.c index 50f7be79a0..7e490e15a0 100644 --- a/zephyr/test/crc/main.c +++ b/zephyr/test/crc/main.c @@ -21,7 +21,6 @@ static void test_crc8_known_data(void) void test_main(void) { - ztest_test_suite(test_task_shim, - ztest_unit_test(test_crc8_known_data)); + ztest_test_suite(test_task_shim, ztest_unit_test(test_crc8_known_data)); ztest_run_test_suite(test_task_shim); } -- cgit v1.2.1 From 8b2efa172e965d3699256f86b913b2a94165d653 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:16:10 -0600 Subject: chip/ish/power_mgt.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I2606f830558973780177d65f27eebbf4627cb685 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729162 Reviewed-by: Jeremy Bettis --- chip/ish/power_mgt.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/chip/ish/power_mgt.h b/chip/ish/power_mgt.h index a1fd5aabb6..1b6131b321 100644 --- a/chip/ish/power_mgt.h +++ b/chip/ish/power_mgt.h @@ -17,8 +17,8 @@ extern void clear_fabric_error(void); extern void i2c_port_restore(void); extern void lapic_restore(void); -#define FABRIC_IDLE_COUNT 50 -#define TRUNK_CLKGATE_COUNT 0xf +#define FABRIC_IDLE_COUNT 50 +#define TRUNK_CLKGATE_COUNT 0xf /* power states for ISH */ enum ish_pm_state { @@ -58,8 +58,7 @@ static inline void ish_mia_halt(void) } /* reset ISH mintue-ia cpu core */ -noreturn -static inline void ish_mia_reset(void) +noreturn static inline void ish_mia_reset(void) { /** * ISH HW looks at the rising edge of this bit to -- cgit v1.2.1 From e3404c4e99c55b8d7ff11d2896494d157404b56e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:37:08 -0600 Subject: zephyr/shim/include/zephyr_console_shim.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id8746bf8eebd3475abe4a387b975f71f87dc214a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730856 Reviewed-by: Jeremy Bettis --- zephyr/shim/include/zephyr_console_shim.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/include/zephyr_console_shim.h b/zephyr/shim/include/zephyr_console_shim.h index 5880c3f400..87bee7498f 100644 --- a/zephyr/shim/include/zephyr_console_shim.h +++ b/zephyr/shim/include/zephyr_console_shim.h @@ -20,9 +20,7 @@ struct zephyr_console_command { }; #ifdef CONFIG_SHELL_HELP -#define _HELP_ARGS(A, H) \ - .argdesc = A, \ - .help = H, +#define _HELP_ARGS(A, H) .argdesc = A, .help = H, #else #define _HELP_ARGS(A, H) #endif @@ -44,8 +42,7 @@ int zshim_run_ec_console_command(const struct zephyr_console_command *command, #define _ZEPHYR_SHELL_COMMAND_SHIM_2(NAME, ROUTINE_ID, ARGDESC, HELP, \ WRAPPER_ID, ENTRY_ID) \ static const struct zephyr_console_command ENTRY_ID = { \ - .handler = ROUTINE_ID, \ - _HELP_ARGS(ARGDESC, HELP) \ + .handler = ROUTINE_ID, _HELP_ARGS(ARGDESC, HELP) \ }; \ static int WRAPPER_ID(const struct shell *shell, size_t argc, \ char **argv) \ -- cgit v1.2.1 From 3a2c6b3cc05ff497b64304d004b1eef6e6fc2b06 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:40:09 -0600 Subject: board/it8xxx2_pdevb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I81bb9e8c9f250eb4777f415665c0fda18c7ca545 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728514 Reviewed-by: Jeremy Bettis --- board/it8xxx2_pdevb/board.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/board/it8xxx2_pdevb/board.h b/board/it8xxx2_pdevb/board.h index d23898f3aa..710e878564 100644 --- a/board/it8xxx2_pdevb/board.h +++ b/board/it8xxx2_pdevb/board.h @@ -42,12 +42,12 @@ #define CONFIG_USB_PD_CUSTOM_PDO #define CONFIG_USB_PD_3A_PORTS 0 #define CONFIG_USB_PD_DUAL_ROLE -#define CONFIG_USB_PD_PORT_MAX_COUNT 2 -#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 +#define CONFIG_USB_PD_PORT_MAX_COUNT 2 +#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2 #define CONFIG_USB_PD_TCPMV2 #define CONFIG_USB_DRP_ACC_TRYSRC #define CONFIG_USB_PD_REV30 -#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */ +#define CONFIG_USB_PID 0x1234 /* Invalid PID for development board */ #define CONFIG_USB_PD_DEBUG_LEVEL 2 #define CONFIG_USB_PD_TCPM_ITE_ON_CHIP #define CONFIG_USB_PD_TRY_SRC @@ -82,16 +82,16 @@ enum adc_channel { /* Define typical operating power and max power */ #define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 /* Try to negotiate to 20V since i2c noise problems should be fixed. */ -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_VOLTAGE_MV 20000 /* TODO: determine the following board specific type-C power constants */ /* * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ -- cgit v1.2.1 From 1d7a54a44ed1adc73e6304768da834e718581b50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:42:33 -0600 Subject: core/cortex-m/cpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6a506bffda1dd6c0174b327fa6b612f3df20ad66 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729816 Reviewed-by: Jeremy Bettis --- core/cortex-m/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c index 7c31892c18..a9ded5c24d 100644 --- a/core/cortex-m/cpu.c +++ b/core/cortex-m/cpu.c @@ -16,7 +16,8 @@ void cpu_init(void) /* Enable reporting of memory faults, bus faults and usage faults */ CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA | - CPU_NVIC_SHCSR_BUSFAULTENA | CPU_NVIC_SHCSR_USGFAULTENA; + CPU_NVIC_SHCSR_BUSFAULTENA | + CPU_NVIC_SHCSR_USGFAULTENA; } #ifdef CONFIG_ARMV7M_CACHE -- cgit v1.2.1 From ccedb2090f49fd2d244b892df086a2b179dd59b4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:17:40 -0600 Subject: baseboard/nucleo-h743zi/base-board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I83ab497c8158447e704862893b69cf282ecdb94a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727934 Reviewed-by: Jeremy Bettis --- baseboard/nucleo-h743zi/base-board.h | 78 ++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h index df5e4bfa8c..10f780505d 100644 --- a/baseboard/nucleo-h743zi/base-board.h +++ b/baseboard/nucleo-h743zi/base-board.h @@ -53,25 +53,25 @@ * * We need 2 independently erasable blocks, at a minimum. */ -#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) -#define CONFIG_ROLLBACK_OFF ((CONFIG_FLASH_SIZE_BYTES / 2) - \ - CONFIG_ROLLBACK_SIZE) +#define CONFIG_ROLLBACK_SIZE (2 * CONFIG_FLASH_BANK_SIZE) +#define CONFIG_ROLLBACK_OFF \ + ((CONFIG_FLASH_SIZE_BYTES / 2) - CONFIG_ROLLBACK_SIZE) -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF -#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE CONFIG_ROLLBACK_OFF +#define CONFIG_RW_MEM_OFF (CONFIG_FLASH_SIZE_BYTES / 2) +#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES / 2) -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* Disabled features */ @@ -98,25 +98,25 @@ #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED #undef CONFIG_SHAREDLIB_SIZE -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 #define CONFIG_STM_HWTIMER32 #define CONFIG_WATCHDOG_HELP #define CONFIG_WP_ACTIVE_HIGH #ifndef TEST_BUILD - /* TODO(hesling): Fix the illogical dependency between spi.c - * and host_command.c - * - * Currently, the chip/stm32/spi.c depends on functions defined in - * common/host_command.c. When unit test builds use their own tasklist - * without the HOSTCMD task, host_command.c is excluded from the build, - * but chip/stm32/spi.c remains (because of CONFIG_SPI). - * This triggers an undefined reference linker error. - * The reproduce case: - * - Allow CONFIG_SPI in TEST_BUILDs - * - make BOARD=nucleo-h743zi tests - */ -# define CONFIG_SPI +/* TODO(hesling): Fix the illogical dependency between spi.c + * and host_command.c + * + * Currently, the chip/stm32/spi.c depends on functions defined in + * common/host_command.c. When unit test builds use their own tasklist + * without the HOSTCMD task, host_command.c is excluded from the build, + * but chip/stm32/spi.c remains (because of CONFIG_SPI). + * This triggers an undefined reference linker error. + * The reproduce case: + * - Allow CONFIG_SPI in TEST_BUILDs + * - make BOARD=nucleo-h743zi tests + */ +#define CONFIG_SPI #endif /* @@ -146,10 +146,10 @@ #define CONFIG_CMD_IDLE_STATS #ifdef SECTION_IS_RO - /* RO verifies the RW partition signature */ -# define CONFIG_RSA -# define CONFIG_RWSIG -#endif /* SECTION_IS_RO */ +/* RO verifies the RW partition signature */ +#define CONFIG_RSA +#define CONFIG_RWSIG +#endif /* SECTION_IS_RO */ #define CONFIG_RSA_KEY_SIZE 3072 #define CONFIG_RSA_EXPONENT_3 @@ -160,7 +160,7 @@ */ #undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE #ifdef SECTION_IS_RW -# undef CONFIG_ROLLBACK_UPDATE +#undef CONFIG_ROLLBACK_UPDATE #endif /* * Add rollback protection @@ -169,11 +169,11 @@ #define CONFIG_ROLLBACK_MPU_PROTECT #ifndef __ASSEMBLER__ - /* Timer selection */ -# define TIM_CLOCK32 2 -# define TIM_WATCHDOG 16 -# include "gpio_signal.h" - void button_event(enum gpio_signal signal); +/* Timer selection */ +#define TIM_CLOCK32 2 +#define TIM_WATCHDOG 16 +#include "gpio_signal.h" +void button_event(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BASE_BOARD_H */ -- cgit v1.2.1 From c5ef72683f646e90654b764cfc67943a86a797a4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:55:23 -0600 Subject: driver/tcpm/rt1718s.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I058c5038d235368de4043f6cce2e3fa214153654 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730107 Reviewed-by: Jeremy Bettis --- driver/tcpm/rt1718s.c | 200 ++++++++++++++++++++++++-------------------------- 1 file changed, 97 insertions(+), 103 deletions(-) diff --git a/driver/tcpm/rt1718s.c b/driver/tcpm/rt1718s.c index e985419668..ce9ad2ea43 100644 --- a/driver/tcpm/rt1718s.c +++ b/driver/tcpm/rt1718s.c @@ -22,26 +22,25 @@ #include "usb_pe_sm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) -#define RT1718S_SW_RESET_DELAY_MS 2 +#define RT1718S_SW_RESET_DELAY_MS 2 /* Time for delay deasserting EN_FRS after FRS VBUS drop. */ -#define RT1718S_FRS_DIS_DELAY (5 * MSEC) +#define RT1718S_FRS_DIS_DELAY (5 * MSEC) -#define FLAG_FRS_ENABLED BIT(0) -#define FLAG_FRS_RX_SIGNALLED BIT(1) -#define FLAG_FRS_VBUS_VALID_FALL BIT(2) +#define FLAG_FRS_ENABLED BIT(0) +#define FLAG_FRS_RX_SIGNALLED BIT(1) +#define FLAG_FRS_VBUS_VALID_FALL BIT(2) static atomic_t frs_flag[CONFIG_USB_PD_PORT_MAX_COUNT]; /* i2c_write function which won't wake TCPC from low power mode. */ static int rt1718s_write(int port, int reg, int val, int len) { if (reg > 0xFF) { - return i2c_write_offset16( - tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, val, len); + return i2c_write_offset16(tcpc_config[port].i2c_info.port, + tcpc_config[port].i2c_info.addr_flags, + reg, val, len); } else if (len == 1) { return tcpc_write(port, reg, val); } else { @@ -52,10 +51,9 @@ static int rt1718s_write(int port, int reg, int val, int len) static int rt1718s_read(int port, int reg, int *val, int len) { if (reg > 0xFF) { - return i2c_read_offset16( - tcpc_config[port].i2c_info.port, - tcpc_config[port].i2c_info.addr_flags, - reg, val, len); + return i2c_read_offset16(tcpc_config[port].i2c_info.port, + tcpc_config[port].i2c_info.addr_flags, + reg, val, len); } else if (len == 1) { return tcpc_read(port, reg, val); } else { @@ -97,13 +95,12 @@ int rt1718s_read16(int port, int reg, int *val) return rt1718s_read(port, reg, val, 2); } - int rt1718s_sw_reset(int port) { int rv; - rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3, - RT1718S_SWRESET_MASK, 0xFF); + rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL3, RT1718S_SWRESET_MASK, + 0xFF); msleep(RT1718S_SW_RESET_DELAY_MS); @@ -114,44 +111,43 @@ int rt1718s_sw_reset(int port) static int rt1718s_enable_bc12_sink(int port, bool en) { return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC, - RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN, - en ? 0xFF : 0); + RT1718S_RT2_BC12_SNK_FUNC_BC12_SNK_EN, + en ? 0xFF : 0); } static int rt1718s_set_bc12_sink_spec_ta(int port, bool en) { - return rt1718s_update_bits8(port, - RT1718S_RT2_BC12_SNK_FUNC, - RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN, en ? 0xFF : 0); + return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC, + RT1718S_RT2_BC12_SNK_FUNC_SPEC_TA_EN, + en ? 0xFF : 0); } static int rt1718s_set_bc12_sink_dcdt_sel(int port, uint8_t dcdt_sel) { - return rt1718s_update_bits8(port, - RT1718S_RT2_BC12_SNK_FUNC, - RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK, dcdt_sel); + return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC, + RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_MASK, + dcdt_sel); } static int rt1718s_set_bc12_sink_vlgc_option(int port, bool en) { - return rt1718s_update_bits8(port, - RT1718S_RT2_BC12_SNK_FUNC, - RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT, en ? 0xFF : 0); + return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC, + RT1718S_RT2_BC12_SNK_FUNC_VLGC_OPT, + en ? 0xFF : 0); } static int rt1718s_set_bc12_sink_vport_sel(int port, uint8_t sel) { - return rt1718s_update_bits8(port, - RT1718S_RT2_DPDM_CTR1_DPDM_SET, - RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel); + return rt1718s_update_bits8( + port, RT1718S_RT2_DPDM_CTR1_DPDM_SET, + RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_MASK, sel); } static int rt1718s_set_bc12_sink_wait_vbus(int port, bool en) { - return rt1718s_update_bits8(port, - RT1718S_RT2_BC12_SNK_FUNC, - RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS, - en ? 0xFF : 0); + return rt1718s_update_bits8(port, RT1718S_RT2_BC12_SNK_FUNC, + RT1718S_RT2_BC12_SNK_FUNC_BC12_WAIT_VBUS, + en ? 0xFF : 0); } /* @@ -161,27 +157,27 @@ static int rt1718s_bc12_init(int port) { /* Enable vendor defined BC12 function */ RETURN_ERROR(rt1718s_write8(port, RT1718S_RT_MASK6, - RT1718S_RT_MASK6_M_BC12_SNK_DONE | - RT1718S_RT_MASK6_M_BC12_TA_CHG)); + RT1718S_RT_MASK6_M_BC12_SNK_DONE | + RT1718S_RT_MASK6_M_BC12_TA_CHG)); RETURN_ERROR(rt1718s_write8(port, RT1718S_RT2_SBU_CTRL_01, - RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN | - RT1718S_RT2_SBU_CTRL_01_DM_SWEN | - RT1718S_RT2_SBU_CTRL_01_DP_SWEN)); + RT1718S_RT2_SBU_CTRL_01_DPDM_VIEN | + RT1718S_RT2_SBU_CTRL_01_DM_SWEN | + RT1718S_RT2_SBU_CTRL_01_DP_SWEN)); /* Disable 2.7v mode */ RETURN_ERROR(rt1718s_set_bc12_sink_spec_ta(port, false)); /* DCDT select 600ms timeout */ - RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel(port, - RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS)); + RETURN_ERROR(rt1718s_set_bc12_sink_dcdt_sel( + port, RT1718S_RT2_BC12_SNK_FUNC_DCDT_SEL_600MS)); /* Disable vlgc option */ RETURN_ERROR(rt1718s_set_bc12_sink_vlgc_option(port, false)); /* DPDM voltage selection */ - RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel(port, - RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V)); + RETURN_ERROR(rt1718s_set_bc12_sink_vport_sel( + port, RT1718S_RT2_DPDM_CTR1_DPDM_SET_DPDM_VSRC_SEL_0_65V)); /* Disable sink wait vbus */ RETURN_ERROR(rt1718s_set_bc12_sink_wait_vbus(port, false)); @@ -197,22 +193,24 @@ static int rt1718s_workaround(int port) switch (device_id) { case RT1718S_DEVICE_ID_ES1: - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3, - RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG, - 0xFF)); + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_VCONN_CONTROL_3, + RT1718S_VCONN_CONTROL_3_VCONN_OVP_DEG, 0xFF)); /* fallthrough */ case RT1718S_DEVICE_ID_ES2: - RETURN_ERROR(rt1718s_update_bits8(port, TCPC_REG_FAULT_CTRL, - TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, - 0xFF)); - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4, - RT1718S_VCON_CTRL4_UVP_CP_EN | - RT1718S_VCON_CTRL4_OCP_CP_EN, - 0)); - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_2, - RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 | - RT1718S_VCONN_CONTROL_2_OVP_EN_CC2, - 0xFF)); + RETURN_ERROR(rt1718s_update_bits8( + port, TCPC_REG_FAULT_CTRL, + TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS, 0xFF)); + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_VCON_CTRL4, + RT1718S_VCON_CTRL4_UVP_CP_EN | + RT1718S_VCON_CTRL4_OCP_CP_EN, + 0)); + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_VCONN_CONTROL_2, + RT1718S_VCONN_CONTROL_2_OVP_EN_CC1 | + RT1718S_VCONN_CONTROL_2_OVP_EN_CC2, + 0xFF)); break; default: /* do nothing */ @@ -271,12 +269,13 @@ static int rt1718s_init(int port) /* Set VBUS_VOL_SEL to 20V */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_RT2_VBUS_VOL_CTRL, - RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL, - RT1718S_VBUS_VOL_TO_REG(20))); + RT1718S_RT2_VBUS_VOL_CTRL_VOL_SEL, + RT1718S_VBUS_VOL_TO_REG(20))); /* Set VCONN_OCP_SEL to 400mA */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCONN_CONTROL_3, - RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL, 0x7F)); + RT1718S_VCONN_CONTROL_3_VCONN_OCP_SEL, + 0x7F)); /* Increase the Vconn OCP shoot detection from 200ns to 3~5us */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_VCON_CTRL4, @@ -287,9 +286,10 @@ static int rt1718s_init(int port) /* Tcpc connect invalid disabled. Exit shipping mode */ RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1, - RT1718S_SYS_CTRL1_TCPC_CONN_INVALID, 0x00)); - RETURN_ERROR(rt1718s_update_bits8(port, RT1718S_SYS_CTRL1, - RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF)); + RT1718S_SYS_CTRL1_TCPC_CONN_INVALID, + 0x00)); + RETURN_ERROR(rt1718s_update_bits8( + port, RT1718S_SYS_CTRL1, RT1718S_SYS_CTRL1_SHIPPING_OFF, 0xFF)); /* Clear alert and fault */ RETURN_ERROR(rt1718s_write8(port, TCPC_REG_FAULT_STATUS, 0xFF)); @@ -303,8 +303,7 @@ static int rt1718s_init(int port) * tcpci_tcpm_init. */ RETURN_ERROR(tcpc_update16(port, TCPC_REG_ALERT_MASK, - TCPC_REG_ALERT_MASK_VENDOR_DEF, - MASK_SET)); + TCPC_REG_ALERT_MASK_VENDOR_DEF, MASK_SET)); if (IS_ENABLED(CONFIG_USB_PD_FRS)) { memset(frs_flag, 0, @@ -368,7 +367,7 @@ static void rt1718s_update_charge_manager(int port, if (new_bc12_type != current_bc12_type) { if (current_bc12_type != CHARGE_SUPPLIER_NONE) charge_manager_update_charge(current_bc12_type, port, - NULL); + NULL); if (new_bc12_type != CHARGE_SUPPLIER_NONE) { struct charge_port_info chg = { @@ -391,16 +390,15 @@ static void rt1718s_bc12_usb_charger_task_init(const int port) static void rt1718s_bc12_usb_charger_task_event(const int port, uint32_t evt) { bool is_non_pd_sink = !pd_capable(port) && - !usb_charger_port_is_sourcing_vbus(port) && - pd_check_vbus_level(port, VBUS_PRESENT); + !usb_charger_port_is_sourcing_vbus(port) && + pd_check_vbus_level(port, VBUS_PRESENT); if (evt & USB_CHG_EVENT_VBUS) { - if (is_non_pd_sink) rt1718s_enable_bc12_sink(port, true); else - rt1718s_update_charge_manager( - port, CHARGE_SUPPLIER_NONE); + rt1718s_update_charge_manager(port, + CHARGE_SUPPLIER_NONE); } /* detection done, update charge_manager and stop detection */ @@ -534,8 +532,7 @@ void rt1718s_vendor_defined_alert(int port) return; /* ES1 workaround: disable Vconn discharge */ rv = rt1718s_update_bits8(port, RT1718S_SYS_CTRL2, - RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN, - 0); + RT1718S_SYS_CTRL2_VCONN_DISCHARGE_EN, 0); if (rv) return; @@ -547,7 +544,6 @@ __overridable int board_rt1718s_set_snk_enable(int port, int enable) return EC_SUCCESS; } - static int rt1718s_tcpm_set_snk_ctrl(int port, int enable) { int rv; @@ -721,8 +717,7 @@ void rt1718s_gpio_set_flags(int port, enum rt1718s_gpio signal, uint32_t flags) void rt1718s_gpio_set_level(int port, enum rt1718s_gpio signal, int value) { rt1718s_update_bits8(port, RT1718S_GPIO_CTRL(signal), - RT1718S_GPIO_CTRL_O, - value ? 0xFF : 0); + RT1718S_GPIO_CTRL_O, value ? 0xFF : 0); } int rt1718s_gpio_get_level(int port, enum rt1718s_gpio signal) @@ -739,7 +734,6 @@ static int command_rt1718s_gpio(int argc, char **argv) uint32_t flags; for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (tcpc_config[i].drv != &rt1718s_tcpm_drv) continue; @@ -751,7 +745,7 @@ static int command_rt1718s_gpio(int argc, char **argv) return EC_ERROR_UNKNOWN; ccprintf("C%d GPIO%d OD=%d PU=%d PD=%d OE=%d HL=%d\n", - i, j+1, !(flags & RT1718S_GPIO_CTRL_OD_N), + i, j + 1, !(flags & RT1718S_GPIO_CTRL_OD_N), !!(flags & RT1718S_GPIO_CTRL_PU), !!(flags & RT1718S_GPIO_CTRL_PD), !!(flags & RT1718S_GPIO_CTRL_OE), @@ -780,42 +774,42 @@ static int rt1718s_set_sbu(int port, bool enable) /* RT1718S is a TCPCI compatible port controller */ const struct tcpm_drv rt1718s_tcpm_drv = { - .init = &rt1718s_init, - .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &rt1718s_init, + .release = &tcpci_tcpm_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &tcpci_tcpm_set_cc, - .set_polarity = &tcpci_tcpm_set_polarity, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &tcpci_tcpm_set_cc, + .set_polarity = &tcpci_tcpm_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &rt1718s_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &rt1718s_alert, + .set_vconn = &rt1718s_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &rt1718s_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = &tcpci_tcpc_drp_toggle, + .drp_toggle = &tcpci_tcpc_drp_toggle, #endif - .get_chip_info = &tcpci_get_chip_info, - .set_snk_ctrl = &rt1718s_tcpm_set_snk_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &tcpci_get_chip_info, + .set_snk_ctrl = &rt1718s_tcpm_set_snk_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &rt1718s_enter_low_power_mode, + .enter_low_power_mode = &rt1718s_enter_low_power_mode, #endif #ifdef CONFIG_USB_PD_FRS_TCPC - .set_frs_enable = &rt1718s_set_frs_enable, + .set_frs_enable = &rt1718s_set_frs_enable, #endif - .set_bist_test_mode = &tcpci_set_bist_test_mode, + .set_bist_test_mode = &tcpci_set_bist_test_mode, #ifdef CONFIG_USB_PD_TCPM_SBU - .set_sbu = &rt1718s_set_sbu, + .set_sbu = &rt1718s_set_sbu, #endif }; -- cgit v1.2.1 From 8a07568d05503ddb99563857283442df4980e9d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:33:33 -0600 Subject: board/eve/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic220e28587fc56860454dfbea2714163c0bda875 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728297 Reviewed-by: Jeremy Bettis --- board/eve/board.h | 76 +++++++++++++++++++++++++++---------------------------- 1 file changed, 37 insertions(+), 39 deletions(-) diff --git a/board/eve/board.h b/board/eve/board.h index c1549becfb..70f105beae 100644 --- a/board/eve/board.h +++ b/board/eve/board.h @@ -12,7 +12,7 @@ * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. */ -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE #define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF @@ -26,7 +26,7 @@ #define CONFIG_FLASH_SIZE_BYTES 0x80000 #define CONFIG_FPU /* 7 day delay before hibernate */ -#undef CONFIG_HIBERNATE_DELAY_SEC +#undef CONFIG_HIBERNATE_DELAY_SEC #define CONFIG_HIBERNATE_DELAY_SEC (3600 * 24 * 7) /* 1 day delay before hibernate if battery is less than 10% */ #define CONFIG_HIBERNATE_BATT_PCT 10 @@ -65,7 +65,7 @@ #define CONFIG_HOSTCMD_PD_CONTROL /* EC console history configuration */ -#undef CONFIG_CONSOLE_HISTORY +#undef CONFIG_CONSOLE_HISTORY #define CONFIG_CONSOLE_HISTORY 1 /* SOC */ @@ -78,7 +78,7 @@ #define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_L_PGOOD #define CONFIG_KEYBOARD_COL2_INVERTED -#undef CONFIG_KEYBOARD_VIVALDI +#undef CONFIG_KEYBOARD_VIVALDI #define CONFIG_KEYBOARD_PROTOCOL_8042 #define CONFIG_KEYBOARD_REFRESH_ROW3 #define CONFIG_TABLET_MODE @@ -108,12 +108,12 @@ #define CONFIG_CHARGER_SENSE_RESISTOR 10 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define BD9995X_IOUT_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V + BD9995X_CMD_PMON_IOUT_CTRL_SET_IOUT_GAIN_SET_20V #define BD9995X_PSYS_GAIN_SELECT \ - BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW + BD9995X_CMD_PMON_IOUT_CTRL_SET_PMON_GAIN_SET_02UAW #define CONFIG_EXTPOWER_GPIO -#undef CONFIG_EXTPOWER_DEBOUNCE_MS -#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 1000 #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_COMMON @@ -138,7 +138,7 @@ #define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) #define CONFIG_ACCELGYRO_SEC_ADDR_FLAGS BMM150_ADDR0_FLAGS -#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT /* Unused */ +#define CONFIG_ACCELGYRO_BMI160_INT2_OUTPUT /* Unused */ #define CONFIG_MAG_CALIBRATE #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_INVALID_CHECK @@ -195,26 +195,26 @@ #define CONFIG_USBC_VCONN_SWAP /* Optional feature to configure npcx chip */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ -#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */ +#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 as TACH */ /* I2C ports */ -#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 -#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 -#define I2C_PORT_GYRO NPCX_I2C_PORT1 -#define I2C_PORT_ACCEL I2C_PORT_GYRO -#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 -#define I2C_PORT_ALS NPCX_I2C_PORT2 -#define I2C_PORT_PMIC NPCX_I2C_PORT3 -#define I2C_PORT_BATTERY NPCX_I2C_PORT3 -#define I2C_PORT_CHARGER NPCX_I2C_PORT3 -#define I2C_PORT_THERMAL I2C_PORT_PMIC -#define I2C_PORT_MP2949 NPCX_I2C_PORT3 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT0_1 +#define I2C_PORT_GYRO NPCX_I2C_PORT1 +#define I2C_PORT_ACCEL I2C_PORT_GYRO +#define I2C_PORT_LID_ACCEL NPCX_I2C_PORT2 +#define I2C_PORT_ALS NPCX_I2C_PORT2 +#define I2C_PORT_PMIC NPCX_I2C_PORT3 +#define I2C_PORT_BATTERY NPCX_I2C_PORT3 +#define I2C_PORT_CHARGER NPCX_I2C_PORT3 +#define I2C_PORT_THERMAL I2C_PORT_PMIC +#define I2C_PORT_MP2949 NPCX_I2C_PORT3 /* I2C addresses */ -#define I2C_ADDR_BD99992_FLAGS 0x30 -#define I2C_ADDR_MP2949_FLAGS 0x20 +#define I2C_ADDR_BD99992_FLAGS 0x30 +#define I2C_ADDR_MP2949_FLAGS 0x20 #ifndef __ASSEMBLER__ @@ -234,11 +234,11 @@ enum board_version_list { }; enum temp_sensor_id { - TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ - TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ - TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ - TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ - TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ + TEMP_SENSOR_BATTERY, /* BD99956GW TSENSE */ + TEMP_SENSOR_AMBIENT, /* BD99992GW SYSTHERM0 */ + TEMP_SENSOR_CHARGER, /* BD99992GW SYSTHERM1 */ + TEMP_SENSOR_DRAM, /* BD99992GW SYSTHERM2 */ + TEMP_SENSOR_EMMC, /* BD99992GW SYSTHERM3 */ TEMP_SENSOR_GYRO, TEMP_SENSOR_COUNT }; @@ -282,24 +282,22 @@ enum sensor_id { SENSOR_COUNT, }; -enum adc_channel { - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_COUNT }; /* * delay to turn on the power supply max is ~16ms. * delay to turn off the power supply max is about ~180ms. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* delay to turn on/off vconn */ /* Define typical operating power and max power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 45000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* Board specific handlers */ int board_get_version(void); -- cgit v1.2.1 From dcdb57c1c92a12f15794a53f47ccc7bea6a62830 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:39:36 -0600 Subject: common/stillness_detector.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59b358ea6e4562228db5a83baa5794a2a7dc3297 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729734 Reviewed-by: Jeremy Bettis --- common/stillness_detector.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/common/stillness_detector.c b/common/stillness_detector.c index c33472aa22..e95f262d11 100644 --- a/common/stillness_detector.c +++ b/common/stillness_detector.c @@ -23,8 +23,8 @@ static bool stillness_batch_complete(struct still_det *still_det, uint32_t sample_time) { bool complete = false; - uint32_t batch_window = time_until(still_det->window_start_time, - sample_time); + uint32_t batch_window = + time_until(still_det->window_start_time, sample_time); /* Checking if enough data is accumulated */ if (batch_window >= still_det->min_batch_window && @@ -51,8 +51,8 @@ static inline fp_t compute_variance(fp_t acc_squared, fp_t acc, fp_t inv) return fp_mul((acc_squared - fp_mul(fp_sq(acc), inv)), inv); } -bool still_det_update(struct still_det *still_det, uint32_t sample_time, - fp_t x, fp_t y, fp_t z) +bool still_det_update(struct still_det *still_det, uint32_t sample_time, fp_t x, + fp_t y, fp_t z) { fp_t inv = FLOAT_TO_FP(0.0f), var_x, var_y, var_z; bool complete = false; @@ -88,12 +88,12 @@ bool still_det_update(struct still_det *still_det, uint32_t sample_time, return complete; } /* Calculating the VAR = sum(x^2)/n - sum(x)^2/n^2 */ - var_x = compute_variance( - still_det->acc_xx, still_det->acc_x, inv); - var_y = compute_variance( - still_det->acc_yy, still_det->acc_y, inv); - var_z = compute_variance( - still_det->acc_zz, still_det->acc_z, inv); + var_x = compute_variance(still_det->acc_xx, still_det->acc_x, + inv); + var_y = compute_variance(still_det->acc_yy, still_det->acc_y, + inv); + var_z = compute_variance(still_det->acc_zz, still_det->acc_z, + inv); /* Checking if sensor is still */ if (var_x < still_det->var_threshold && var_y < still_det->var_threshold && -- cgit v1.2.1 From 533a1730566e8c9ddc5ee79300d57033fd53942f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:02:23 -0600 Subject: board/reef/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I59d26c383bc2902083981dba6bbd60ab635a1a7c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728864 Reviewed-by: Jeremy Bettis --- board/reef/battery.c | 57 ++++++++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/board/reef/battery.c b/board/reef/battery.c index 83a3679b26..e0d20d7692 100644 --- a/board/reef/battery.c +++ b/board/reef/battery.c @@ -20,7 +20,7 @@ #include "i2c.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) enum battery_type { BATTERY_SONY_CORP, @@ -135,7 +135,7 @@ const struct battery_info batt_info_smp_cos4870 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 46, .charging_min_c = 0, @@ -183,7 +183,7 @@ const struct battery_info batt_info_sonycorp = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -240,7 +240,7 @@ const struct battery_info batt_info_panasoic = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 50, .charging_min_c = 0, @@ -384,7 +384,7 @@ const struct battery_info batt_info_c22n1626 = { * unwanted low VSYS_Prochot# assertion can be avoided. */ .voltage_min = 6100, - .precharge_current = 256, /* mA */ + .precharge_current = 256, /* mA */ .start_charging_min_c = 0, .start_charging_max_c = 45, .charging_min_c = 0, @@ -398,7 +398,7 @@ static int batt_smp_cos4870_init(void) int batt_status; return battery_status(&batt_status) ? 0 : - batt_status & STATUS_INITIALIZED; + batt_status & STATUS_INITIALIZED; } static int batt_sony_corp_init(void) @@ -411,8 +411,9 @@ static int batt_sony_corp_init(void) * : 0b - Allowed to Discharge * : 1b - Not Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !(batt_status & SONY_DISCHARGE_DISABLE_FET_BIT); } static int batt_panasonic_init(void) @@ -425,8 +426,9 @@ static int batt_panasonic_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? 0 : - !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_MANUFACTURER_ACCESS, &batt_status) ? + 0 : + !!(batt_status & PANASONIC_DISCHARGE_ENABLE_FET_BIT); } static int batt_c22n1626_init(void) @@ -439,8 +441,9 @@ static int batt_c22n1626_init(void) * : 0b - Not Allowed to Discharge * : 1b - Allowed to Discharge */ - return sb_read(SB_PACK_STATUS, &batt_status) ? 0 : - !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); + return sb_read(SB_PACK_STATUS, &batt_status) ? + 0 : + !!(batt_status & C22N1626_DISCHARGE_ENABLE_FET_BIT); } static const struct ship_mode_info ship_mode_info_smp_cos4870 = { @@ -461,7 +464,7 @@ static const struct ship_mode_info ship_mode_info_panasonic = { .batt_init = batt_panasonic_init, }; -static const struct ship_mode_info ship_mode_info_c22n1626= { +static const struct ship_mode_info ship_mode_info_c22n1626 = { .ship_mode_reg = 0x00, .ship_mode_data = 0x0010, .batt_init = batt_c22n1626_init, @@ -513,7 +516,8 @@ BUILD_ASSERT(ARRAY_SIZE(info) == BATTERY_TYPE_COUNT); static inline const struct board_batt_params *board_get_batt_params(void) { return &info[board_battery_type == BATTERY_TYPE_COUNT ? - DEFAULT_BATTERY_TYPE : board_battery_type]; + DEFAULT_BATTERY_TYPE : + board_battery_type]; } enum battery_present battery_hw_present(void) @@ -540,8 +544,9 @@ static int board_get_battery_type(void) /* Initialize fast charging parameters */ chg_params = board_get_batt_params()->fast_chg_params; - prev_chg_profile_info = &chg_params->chg_profile_info[ - chg_params->default_temp_range_profile]; + prev_chg_profile_info = + &chg_params->chg_profile_info + [chg_params->default_temp_range_profile]; return board_battery_type; } @@ -571,11 +576,11 @@ int board_cut_off_battery(void) { int rv; const struct ship_mode_info *ship_mode_inf = - board_get_batt_params()->ship_mode_inf; + board_get_batt_params()->ship_mode_inf; /* Ship mode command must be sent twice to take effect */ rv = sb_write(ship_mode_inf->ship_mode_reg, - ship_mode_inf->ship_mode_data); + ship_mode_inf->ship_mode_data); if (rv != EC_SUCCESS) return rv; @@ -591,7 +596,7 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) /* Do not discharge on AC if the battery is still waking up */ if (!(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - !(curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.status & STATUS_FULLY_CHARGED)) return 0; /* @@ -608,8 +613,8 @@ static int charger_should_discharge_on_ac(struct charge_state_data *curr) * and suspend USB charging and DC/DC converter. */ if (!battery_is_cut_off() && - !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && - (curr->batt.status & STATUS_FULLY_CHARGED)) + !(curr->batt.flags & BATT_FLAG_WANT_CHARGE) && + (curr->batt.status & STATUS_FULLY_CHARGED)) return 1; /* @@ -642,10 +647,10 @@ int charger_profile_override(struct charge_state_data *curr) return 0; } - return charger_profile_override_common(curr, - board_get_batt_params()->fast_chg_params, - &prev_chg_profile_info, - board_get_batt_params()->batt_info->voltage_max); + return charger_profile_override_common( + curr, board_get_batt_params()->fast_chg_params, + &prev_chg_profile_info, + board_get_batt_params()->batt_info->voltage_max); } /* @@ -671,7 +676,7 @@ enum battery_present battery_is_present(void) * Battery status will be inactive until it is initialized. */ if (batt_pres == BP_YES && batt_pres_prev != batt_pres && - !battery_is_cut_off()) { + !battery_is_cut_off()) { /* Re-init board battery if battery presence status changes */ if (board_get_battery_type() == BATTERY_TYPE_COUNT) { if (bd9995x_get_battery_voltage() >= -- cgit v1.2.1 From f5916e81d3b0850a18510f13719e6527adc1a973 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:42:12 -0600 Subject: board/kodama/battery.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I0aad68b65e854ca30c46143fc6912618b4862491 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728559 Reviewed-by: Jeremy Bettis --- board/kodama/battery.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/kodama/battery.c b/board/kodama/battery.c index 1dbff92a00..727ad83727 100644 --- a/board/kodama/battery.c +++ b/board/kodama/battery.c @@ -14,7 +14,7 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) const struct board_batt_params board_battery_info[] = { [BATTERY_SIMPLO] = { @@ -95,9 +95,9 @@ int charger_profile_override(struct charge_state_data *curr) * When smart battery temperature is more than 45 deg C, the max * charging voltage is 4100mV. */ - if (curr->state == ST_CHARGE && bat_temp_c >= 450 - && !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) - curr->requested_voltage = 4100; + if (curr->state == ST_CHARGE && bat_temp_c >= 450 && + !(curr->batt.flags & BATT_FLAG_BAD_TEMPERATURE)) + curr->requested_voltage = 4100; else curr->requested_voltage = batt_info->voltage_max; -- cgit v1.2.1 From 93303436cfe3af79138d313c531f323cbc68412d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:20:38 -0600 Subject: test/hooks.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Iadd3037bdedd42ab6320588fdaacf58dc43c212b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730506 Reviewed-by: Jeremy Bettis --- test/hooks.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/test/hooks.c b/test/hooks.c index 8d12494688..e47ebf43dc 100644 --- a/test/hooks.c +++ b/test/hooks.c @@ -41,7 +41,7 @@ static void tick2_hook(void) tick_count_seen_by_tick2 = tick_hook_count; } /* tick2_hook() prio means it should be called after tick_hook() */ -DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT+1); +DECLARE_HOOK(HOOK_TICK, tick2_hook, HOOK_PRIO_DEFAULT + 1); static void second_hook(void) { @@ -62,9 +62,7 @@ static void non_deferred_func(void) deferred_call_count++; } -static const struct deferred_data non_deferred_func_data = { - non_deferred_func -}; +static const struct deferred_data non_deferred_func_data = { non_deferred_func }; static int test_init_hook(void) { @@ -85,8 +83,7 @@ static int test_ticks(void) usleep(1300 * MSEC); interval = tick_time[1].val - tick_time[0].val; - error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / - HOOK_TICK_INTERVAL; + error_pct = (interval - HOOK_TICK_INTERVAL) * 100 / HOOK_TICK_INTERVAL; TEST_ASSERT_ABS_LESS(error_pct, 10); interval = second_time[1].val - second_time[0].val; -- cgit v1.2.1 From 106afede0f003a27ee8391e904d33017a9c6422a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:05:34 -0600 Subject: board/shotzo/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I98987e126b1a18c5c140c3350ad48ab24dfa50c4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728950 Reviewed-by: Jeremy Bettis --- board/shotzo/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/shotzo/cbi_ssfc.h b/board/shotzo/cbi_ssfc.h index ddfada8a68..8df1d86271 100644 --- a/board/shotzo/cbi_ssfc.h +++ b/board/shotzo/cbi_ssfc.h @@ -55,5 +55,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From 31a5f8401465da2c5ebbb67ae0605695dddc8e94 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:11:08 -0600 Subject: include/event_log.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I62574a23408d9a492228414cf405b34523cf6c3a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730264 Reviewed-by: Jeremy Bettis --- include/event_log.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/event_log.h b/include/event_log.h index 45b10a3a2d..f7e7244a54 100644 --- a/include/event_log.h +++ b/include/event_log.h @@ -8,14 +8,14 @@ struct event_log_entry { uint32_t timestamp; /* relative timestamp in milliseconds */ - uint8_t type; /* event type, caller-defined */ - uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */ - uint16_t data; /* type-defined data payload */ + uint8_t type; /* event type, caller-defined */ + uint8_t size; /* [7:5] caller-def'd [4:0] payload size in bytes */ + uint16_t data; /* type-defined data payload */ uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */ } __packed; -#define EVENT_LOG_SIZE_MASK 0x1f -#define EVENT_LOG_SIZE(size) ((size) & EVENT_LOG_SIZE_MASK) +#define EVENT_LOG_SIZE_MASK 0x1f +#define EVENT_LOG_SIZE(size) ((size)&EVENT_LOG_SIZE_MASK) /* The timestamp is the microsecond counter shifted to get about a ms. */ #define EVENT_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */ @@ -23,8 +23,8 @@ struct event_log_entry { #define EVENT_LOG_NO_ENTRY 0xff /* Add an entry to the event log. */ -void log_add_event(uint8_t type, uint8_t size, uint16_t data, - void *payload, uint32_t timestamp); +void log_add_event(uint8_t type, uint8_t size, uint16_t data, void *payload, + uint32_t timestamp); /* * Remove and return an entry from the event log, if available. -- cgit v1.2.1 From 472aca6dfa4d815c381ee74f1476b49a8f0a815d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:53:46 -0600 Subject: board/mithrax/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I03bc981e5689ad6709f1ed5cb06c6449fb1dd1c2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728465 Reviewed-by: Jeremy Bettis --- board/mithrax/sensors.c | 58 ++++++++++++++++++++----------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/board/mithrax/sensors.c b/board/mithrax/sensors.c index fff002dda6..dd9cf4d699 100644 --- a/board/mithrax/sensors.c +++ b/board/mithrax/sensors.c @@ -46,18 +46,14 @@ K_MUTEX_DEFINE(g_base_accel_mutex); static struct stprivate_data g_lis2dw12_data; static struct lsm6dso_data lsm6dso_data; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; /* TODO(b/184779743): verify orientation matrix */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -146,24 +142,18 @@ DECLARE_HOOK(HOOK_INIT, baseboard_sensors_init, HOOK_PRIO_INIT_I2C + 1); /* Temperature sensor configuration */ const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1_DDR_SOC] = { - .name = "DDR and SOC", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1_DDR_SOC - }, - [TEMP_SENSOR_2_FAN] = { - .name = "FAN", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2_FAN - }, - [TEMP_SENSOR_3_CHARGER] = { - .name = "Charger", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3_CHARGER - }, + [TEMP_SENSOR_1_DDR_SOC] = { .name = "DDR and SOC", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1_DDR_SOC }, + [TEMP_SENSOR_2_FAN] = { .name = "FAN", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2_FAN }, + [TEMP_SENSOR_3_CHARGER] = { .name = "Charger", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3_CHARGER }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); @@ -177,8 +167,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -207,8 +197,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_FAN \ - { \ +#define THERMAL_FAN \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(60), \ [EC_TEMP_THRESH_HALT] = C_TO_K(70), \ @@ -221,8 +211,8 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; } __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ -- cgit v1.2.1 From 39635ae24f5b1c8ea9a434dfae1464adf57e3e00 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:10:39 -0600 Subject: board/volet/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I254e7cb6f7d239d296c63804003be1fc75284919 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729062 Reviewed-by: Jeremy Bettis --- board/volet/led.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/board/volet/led.c b/board/volet/led.c index ba4af36163..fc16d7f3ff 100644 --- a/board/volet/led.c +++ b/board/volet/led.c @@ -19,23 +19,28 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{EC_LED_COLOR_BLUE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_AMBER, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_BLUE, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_AMBER, + 2 * LED_ONE_SEC } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 06ec2bcb1d14dcf95e8d3223becace38666b4403 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:45:37 -0600 Subject: driver/accel_bma2x2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I84419a1c36800f79bd3181cea72381bc350f8621 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729764 Reviewed-by: Jeremy Bettis --- driver/accel_bma2x2.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/driver/accel_bma2x2.c b/driver/accel_bma2x2.c index 6d2d596bea..fde60997ab 100644 --- a/driver/accel_bma2x2.c +++ b/driver/accel_bma2x2.c @@ -20,7 +20,7 @@ #include "util.h" #define CPUTS(outstr) cputs(CC_ACCEL, outstr) -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) /* Number of times to attempt to enable sensor before giving up. */ #define SENSOR_ENABLE_ATTEMPTS 5 @@ -45,7 +45,7 @@ static inline int raw_write8(const int port, const uint16_t i2c_addr_flags, static int set_range(struct motion_sensor_t *s, int range, int rnd) { - int ret, range_val, reg_val, range_reg_val; + int ret, range_val, reg_val, range_reg_val; /* Range has to be between 2G-16G */ if (range < 2) @@ -105,16 +105,16 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd) mutex_lock(s->mutex); /* Determine the new value of control reg and attempt to write it. */ - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - BMA2x2_BW_SELECT_ADDR, &odr_reg_val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR, + &odr_reg_val); if (ret != EC_SUCCESS) { mutex_unlock(s->mutex); return ret; } reg_val = (odr_reg_val & ~BMA2x2_BW_MSK) | odr_val; /* Set output data rate. */ - ret = raw_write8(s->port, s->i2c_spi_addr_flags, - BMA2x2_BW_SELECT_ADDR, reg_val); + ret = raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_BW_SELECT_ADDR, + reg_val); /* If successfully written, then save the new data rate. */ if (ret == EC_SUCCESS) @@ -212,8 +212,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable) if (!enable) return EC_SUCCESS; - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - BMA2x2_OFFSET_CTRL_ADDR, &val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFFSET_CTRL_ADDR, + &val); if (ret) return ret; if (!(val & BMA2x2_OFFSET_CAL_READY)) @@ -237,8 +237,8 @@ static int perform_calib(struct motion_sensor_t *s, int enable) val = ((BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(X)) | (BMA2x2_OFC_TARGET_0G << BMA2x2_OFC_TARGET_AXIS(Y)) | (val << BMA2x2_OFC_TARGET_AXIS(Z))); - raw_write8(s->port, s->i2c_spi_addr_flags, - BMA2x2_OFC_SETTING_ADDR, val); + raw_write8(s->port, s->i2c_spi_addr_flags, BMA2x2_OFC_SETTING_ADDR, + val); for (i = X; i <= Z; i++) { val = (i + 1) << BMA2x2_OFFSET_TRIGGER_OFF; @@ -275,8 +275,8 @@ static int init(struct motion_sensor_t *s) /* This driver requires a mutex */ ASSERT(s->mutex); - ret = raw_read8(s->port, s->i2c_spi_addr_flags, - BMA2x2_CHIP_ID_ADDR, &val); + ret = raw_read8(s->port, s->i2c_spi_addr_flags, BMA2x2_CHIP_ID_ADDR, + &val); if (ret) return EC_ERROR_UNKNOWN; -- cgit v1.2.1 From ee1b9bd2dd1dc10efb6ac6c3e139dfda5ce824be Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:34:48 -0600 Subject: common/chargen.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia4cabcaa8cb19e90a4a78f5049232ce694ba2941 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729617 Reviewed-by: Jeremy Bettis --- common/chargen.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/common/chargen.c b/common/chargen.c index 1a57e7f539..824017b91b 100644 --- a/common/chargen.c +++ b/common/chargen.c @@ -17,8 +17,8 @@ * Microseconds time to drain entire UART_TX console buffer at 115200 b/s, 10 * bits per character. */ -#define BUFFER_DRAIN_TIME_US (1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE \ - / CONFIG_UART_BAUD_RATE) +#define BUFFER_DRAIN_TIME_US \ + (1000000UL * 10 * CONFIG_UART_TX_BUF_SIZE / CONFIG_UART_BAUD_RATE) /* * Generate a stream of characters on the UART (and USB) console. @@ -80,7 +80,7 @@ static int command_chargen(int argc, char **argv) * Let's let other tasks run for a bit while buffer is * being drained a little. */ - usleep(BUFFER_DRAIN_TIME_US/10); + usleep(BUFFER_DRAIN_TIME_US / 10); current_time = get_time(); @@ -110,7 +110,7 @@ static int command_chargen(int argc, char **argv) c = '0'; else if (c == ('Z' + 1)) c = 'a'; - else if (c == ('9' + 1)) + else if (c == ('9' + 1)) c = 'A'; } @@ -128,6 +128,5 @@ DECLARE_SAFE_CONSOLE_COMMAND(chargen, command_chargen, #endif "Generate a constant stream of characters on the " "UART console,\nrepeating every 'seq_length' " - "characters, up to 'num_chars' total." - ); -#endif /* !SECTION_IS_RO */ + "characters, up to 'num_chars' total."); +#endif /* !SECTION_IS_RO */ -- cgit v1.2.1 From 4617360a86c7224092b78e4fb0828b2c6b359ccf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:48:23 -0600 Subject: driver/bc12/pi3usb9281.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6bfb6db80c45931601b47be91e9b76318c15b65e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729935 Reviewed-by: Jeremy Bettis --- driver/bc12/pi3usb9281.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/driver/bc12/pi3usb9281.c b/driver/bc12/pi3usb9281.c index 3c3a0a7256..e2475ea038 100644 --- a/driver/bc12/pi3usb9281.c +++ b/driver/bc12/pi3usb9281.c @@ -19,9 +19,9 @@ #include "usb_pd.h" #include "util.h" - /* Console output macros */ +/* Console output macros */ #define CPUTS(outstr) cputs(CC_USBCHARGE, outstr) -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) /* I2C address */ #define PI3USB9281_I2C_ADDR_FLAGS 0x25 @@ -30,10 +30,10 @@ #define PI3USB9281_SW_RESET_DELAY 20 /* Wait after a charger is detected to debounce pin contact order */ -#define PI3USB9281_DETECT_DEBOUNCE_MS 1000 -#define PI3USB9281_RESET_DEBOUNCE_MS 100 -#define PI3USB9281_RESET_STARTUP_DELAY (200 * MSEC) -#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS 40 +#define PI3USB9281_DETECT_DEBOUNCE_MS 1000 +#define PI3USB9281_RESET_DEBOUNCE_MS 100 +#define PI3USB9281_RESET_STARTUP_DELAY (200 * MSEC) +#define PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS 40 /* Store the state of our USB data switches so that they can be restored. */ static int usb_switch_state[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -69,8 +69,7 @@ static uint8_t pi3usb9281_do_read(int port, uint8_t reg, int with_lock) if (with_lock) select_chip(port); - res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, - reg, &val); + res = i2c_read8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, &val); if (with_lock) unselect_chip(port); @@ -91,8 +90,8 @@ static uint8_t pi3usb9281_read(int port, uint8_t reg) return pi3usb9281_do_read(port, reg, 1); } -static int pi3usb9281_do_write( - int port, uint8_t reg, uint8_t val, int with_lock) +static int pi3usb9281_do_write(int port, uint8_t reg, uint8_t val, + int with_lock) { struct pi3usb9281_config *chip = &pi3usb9281_chips[port]; int res; @@ -100,8 +99,7 @@ static int pi3usb9281_do_write( if (with_lock) select_chip(port); - res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, - reg, val); + res = i2c_write8(chip->i2c_port, PI3USB9281_I2C_ADDR_FLAGS, reg, val); if (with_lock) unselect_chip(port); @@ -120,8 +118,9 @@ static int pi3usb9281_write(int port, uint8_t reg, uint8_t val) static int pi3usb9281_do_write_ctrl(int port, uint8_t ctrl, int with_lock) { return pi3usb9281_do_write(port, PI3USB9281_REG_CONTROL, - (ctrl & PI3USB9281_CTRL_MASK) | - PI3USB9281_CTRL_RSVD_1, with_lock); + (ctrl & PI3USB9281_CTRL_MASK) | + PI3USB9281_CTRL_RSVD_1, + with_lock); } static int pi3usb9281_write_ctrl(int port, uint8_t ctrl) @@ -156,7 +155,6 @@ static void pi3usb9281_init(int port) pi3usb9281_enable_interrupts(port); } - int pi3usb9281_enable_interrupts(int port) { uint8_t ctrl; @@ -297,7 +295,7 @@ static int pc3usb9281_read_interrupt(int port) do { /* Read (& clear) possible attach & detach interrupt */ if (pi3usb9281_get_interrupts(port) & - PI3USB9281_INT_ATTACH_DETACH) + PI3USB9281_INT_ATTACH_DETACH) return EC_SUCCESS; msleep(PI3USB9281_RESET_STARTUP_DELAY_INTERVAL_MS); } while (get_time().val < timeout.val); @@ -418,7 +416,6 @@ static uint32_t bc12_detect(int port) static void pi3usb9281_usb_charger_task_event(const int port, uint32_t evt) { - /* Interrupt from the Pericom chip, determine charger type */ if (evt & USB_CHG_EVENT_BC12) { /* Read interrupt register to clear on chip */ @@ -443,7 +440,8 @@ static void pi3usb9281_usb_charger_task_event(const int port, uint32_t evt) if (evt & USB_CHG_EVENT_VBUS) { pi3usb9281_enable_interrupts(port); if (!IS_ENABLED(CONFIG_USB_PD_VBUS_DETECT_TCPC)) - CPRINTS("VBUS p%d %d", port, pd_snk_is_vbus_provided(port)); + CPRINTS("VBUS p%d %d", port, + pd_snk_is_vbus_provided(port)); } } -- cgit v1.2.1 From d5711ac690549b2d177bf90616507edc42606eab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:47:30 -0600 Subject: driver/als_opt3001.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9701526c022b68fdd2c37e0d2e1059eef55a4134 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729903 Reviewed-by: Jeremy Bettis --- driver/als_opt3001.h | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/driver/als_opt3001.h b/driver/als_opt3001.h index 96b47232d1..69b18f8e9a 100644 --- a/driver/als_opt3001.h +++ b/driver/als_opt3001.h @@ -9,39 +9,39 @@ #define __CROS_EC_ALS_OPT3001_H /* I2C interface */ -#define OPT3001_I2C_ADDR1_FLAGS 0x44 -#define OPT3001_I2C_ADDR2_FLAGS 0x45 -#define OPT3001_I2C_ADDR3_FLAGS 0x46 -#define OPT3001_I2C_ADDR4_FLAGS 0x47 +#define OPT3001_I2C_ADDR1_FLAGS 0x44 +#define OPT3001_I2C_ADDR2_FLAGS 0x45 +#define OPT3001_I2C_ADDR3_FLAGS 0x46 +#define OPT3001_I2C_ADDR4_FLAGS 0x47 /* OPT3001 registers */ -#define OPT3001_REG_RESULT 0x00 -#define OPT3001_REG_CONFIGURE 0x01 -#define OPT3001_RANGE_OFFSET 12 -#define OPT3001_RANGE_MASK 0x0fff -#define OPT3001_MODE_OFFSET 9 -#define OPT3001_MODE_MASK 0xf9ff +#define OPT3001_REG_RESULT 0x00 +#define OPT3001_REG_CONFIGURE 0x01 +#define OPT3001_RANGE_OFFSET 12 +#define OPT3001_RANGE_MASK 0x0fff +#define OPT3001_MODE_OFFSET 9 +#define OPT3001_MODE_MASK 0xf9ff enum opt3001_mode { OPT3001_MODE_SUSPEND, OPT3001_MODE_FORCED, OPT3001_MODE_CONTINUOUS, }; -#define OPT3001_REG_INT_LIMIT_LSB 0x02 -#define OPT3001_REG_INT_LIMIT_MSB 0x03 -#define OPT3001_REG_MAN_ID 0x7e -#define OPT3001_REG_DEV_ID 0x7f +#define OPT3001_REG_INT_LIMIT_LSB 0x02 +#define OPT3001_REG_INT_LIMIT_MSB 0x03 +#define OPT3001_REG_MAN_ID 0x7e +#define OPT3001_REG_DEV_ID 0x7f /* OPT3001 register values */ -#define OPT3001_MANUFACTURER_ID 0x5449 -#define OPT3001_DEVICE_ID 0x3001 +#define OPT3001_MANUFACTURER_ID 0x5449 +#define OPT3001_DEVICE_ID 0x3001 /* * Min and Max sampling frequency in mHz. * Due to integration set at 800ms, we limit max frequency to 1Hz. */ -#define OPT3001_LIGHT_MIN_FREQ 100 -#define OPT3001_LIGHT_MAX_FREQ 1000 +#define OPT3001_LIGHT_MIN_FREQ 100 +#define OPT3001_LIGHT_MAX_FREQ 1000 #if (CONFIG_EC_MAX_SENSOR_FREQ_MILLIHZ <= OPT3001_LIGHT_MAX_FREQ) #error "EC too slow for light sensor" #endif @@ -50,7 +50,7 @@ enum opt3001_mode { int opt3001_init(void); int opt3001_read_lux(int *lux, int af); #else -#define OPT3001_GET_DATA(_s) ((struct opt3001_drv_data_t *)(_s)->drv_data) +#define OPT3001_GET_DATA(_s) ((struct opt3001_drv_data_t *)(_s)->drv_data) struct opt3001_drv_data_t { int rate; @@ -68,4 +68,4 @@ extern const struct accelgyro_drv opt3001_drv; extern struct i2c_stress_test_dev opt3001_i2c_stress_test_dev; #endif -#endif /* __CROS_EC_ALS_OPT3001_H */ +#endif /* __CROS_EC_ALS_OPT3001_H */ -- cgit v1.2.1 From e9810103cf4b558616a1ab7de32012f0ad53b699 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:10:54 -0600 Subject: include/driver/temp_sensor/tmp112.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I9d5c0f7fba31b62d373bd07d438b6f7926ee8ed1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730258 Reviewed-by: Jeremy Bettis --- include/driver/temp_sensor/tmp112.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/driver/temp_sensor/tmp112.h b/include/driver/temp_sensor/tmp112.h index d1b97b138c..60950660a1 100644 --- a/include/driver/temp_sensor/tmp112.h +++ b/include/driver/temp_sensor/tmp112.h @@ -13,10 +13,10 @@ #define TMP112_I2C_ADDR_FLAGS2 (0x4A | I2C_FLAG_BIG_ENDIAN) #define TMP112_I2C_ADDR_FLAGS3 (0x4B | I2C_FLAG_BIG_ENDIAN) -#define TMP112_REG_TEMP 0x00 -#define TMP112_REG_CONF 0x01 -#define TMP112_REG_HYST 0x02 -#define TMP112_REG_MAX 0x03 +#define TMP112_REG_TEMP 0x00 +#define TMP112_REG_CONF 0x01 +#define TMP112_REG_HYST 0x02 +#define TMP112_REG_MAX 0x03 /* * I2C port and address information for all the board TMP112 sensors should be -- cgit v1.2.1 From c803fd79947b000075d3e832c825713cb15c0f43 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:12:01 -0600 Subject: board/waddledee/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I83f6d07311b5f7f239bb8d9faf7a7176a0ce5926 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729086 Reviewed-by: Jeremy Bettis --- board/waddledee/cbi_ssfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/waddledee/cbi_ssfc.h b/board/waddledee/cbi_ssfc.h index 935049b6ae..942f0cf5f4 100644 --- a/board/waddledee/cbi_ssfc.h +++ b/board/waddledee/cbi_ssfc.h @@ -56,5 +56,4 @@ enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); */ enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); - #endif /* _DEDEDE_CBI_SSFC__H_ */ -- cgit v1.2.1 From e1e7362a5a27774d171bc38c28926d3db4c63cb1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:12:54 -0600 Subject: include/lid_angle.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I21d887e8f73fae04eaccf06f57e965aa85c01717 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730301 Reviewed-by: Jeremy Bettis --- include/lid_angle.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/lid_angle.h b/include/lid_angle.h index 24275db313..eca6d99b03 100644 --- a/include/lid_angle.h +++ b/include/lid_angle.h @@ -32,4 +32,4 @@ void lid_angle_set_wake_angle(int ang); */ __override_proto void lid_angle_peripheral_enable(int enable); -#endif /* __CROS_EC_LID_ANGLE_H */ +#endif /* __CROS_EC_LID_ANGLE_H */ -- cgit v1.2.1 From 45239a4cb30caeec1079c8843b9e5d7beed94d89 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:39:02 -0600 Subject: zephyr/shim/src/tcpc.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I070d0d43574b4efd681b87a7ada4e811091b3fea Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730916 Reviewed-by: Jeremy Bettis --- zephyr/shim/src/tcpc.c | 42 ++++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index 0f96beff15..aef3a05b3c 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -15,31 +15,37 @@ #include "usbc/tcpci.h" #include "usbc/utils.h" -#if DT_HAS_COMPAT_STATUS_OKAY(CCGXXF_TCPC_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(FUSB302_TCPC_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(IT8XXX2_TCPC_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(PS8XXX_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(NCT38XX_TCPC_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(TCPCI_COMPAT) \ +#if DT_HAS_COMPAT_STATUS_OKAY(CCGXXF_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(FUSB302_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(IT8XXX2_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(PS8XXX_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(NCT38XX_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(TCPCI_COMPAT) #define TCPC_CONFIG(id, fn) [USBC_PORT(id)] = fn(id) -#define MAYBE_CONST COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, \ - (), (const)) +#define MAYBE_CONST \ + COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const)) MAYBE_CONST struct tcpc_config_t tcpc_config[] = { DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG, TCPC_CONFIG_CCGXXF) - DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_FUSB302) - DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_IT8XXX2) - DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_PS8XXX) - DT_FOREACH_STATUS_OKAY_VARGS(NCT38XX_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_NCT38XX) - DT_FOREACH_STATUS_OKAY_VARGS(TCPCI_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_TCPCI) + DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_FUSB302) + DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_IT8XXX2) + DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_PS8XXX) + DT_FOREACH_STATUS_OKAY_VARGS( + NCT38XX_TCPC_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_NCT38XX) + DT_FOREACH_STATUS_OKAY_VARGS( + TCPCI_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_TCPCI) }; #endif /* DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 19efefd1c39785d6042f9e8998259a1ae4bd0d65 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:56:32 -0600 Subject: board/npcx9_evb/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id895ddcf236a3d2e44f152e243c0558134fde9c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728768 Reviewed-by: Jeremy Bettis --- board/npcx9_evb/board.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/board/npcx9_evb/board.h b/board/npcx9_evb/board.h index a0d209c938..e707c0258e 100644 --- a/board/npcx9_evb/board.h +++ b/board/npcx9_evb/board.h @@ -25,9 +25,9 @@ #define CONFIG_I2C_CONTROLLER #define CONFIG_KEYBOARD_PROTOCOL_8042 -#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ +#undef CONFIG_LOW_POWER_IDLE /* Deep Sleep Support */ #define CONFIG_POWER_BUTTON -#undef CONFIG_PSTORE +#undef CONFIG_PSTORE #define CONFIG_PWM_KBLIGHT #define CONFIG_VBOOT_HASH #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */ @@ -43,14 +43,14 @@ /* I2C port for CONFIG_CMD_I2CWEDGE */ #define I2C_PORT_MASTER NPCX_I2C_PORT0_0 -#define I2C_PORT_HOST 0 +#define I2C_PORT_HOST 0 /* Fans for testing */ #define CONFIG_FANS 1 #define CONFIG_TEMP_SENSOR #define CONFIG_TEMP_SENSOR_TMP112 -#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0 +#define I2C_PORT_THERMAL NPCX_I2C_PORT2_0 #define CONFIG_KEYBOARD_KSO_HIGH_DRIVE /* Quasi-bidirectional buf for KSOs */ #define CONFIG_HIBERNATE_PSL /* Use PSL (Power Switch Logic) for hibernate */ @@ -60,15 +60,15 @@ /* Select which UART Controller is the Console UART */ #undef CONFIG_CONSOLE_UART -#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ +#define CONFIG_CONSOLE_UART 0 /* 0:UART1 1:UART2 */ /* * This definition below actually doesn't define which UART controller to be * used. Instead, it defines which pinouts (GPIO10/11 or GPIO64/65) are * connected to "UART1" controller. */ -#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ -#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ -#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */ +#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART1 */ +#define NPCX_TACH_SEL2 0 /* 0:GPIO40/73 1:GPIO93/A6 as TACH */ +#define NPCX9_PWM1_SEL 0 /* 0:GPIOC2 as I2CSCL0 1:as PWM1 */ #ifndef __ASSEMBLER__ @@ -94,7 +94,7 @@ enum tmp112_sensor { }; enum temp_sensor_id { - TEMP_SENSOR_SYSTHERM0, /* TMP100 */ + TEMP_SENSOR_SYSTHERM0, /* TMP100 */ TEMP_SENSOR_COUNT }; -- cgit v1.2.1 From d520868a422c7ed8c05cb4963b0d3a70c18a61f8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:26:57 -0600 Subject: util/lock/ipc_lock.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ic3a577d1fe878bb7f5df24833610ed4b94c3cd32 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730651 Reviewed-by: Jeremy Bettis --- util/lock/ipc_lock.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/util/lock/ipc_lock.h b/util/lock/ipc_lock.h index 5d0d321af4..93b5f19d19 100644 --- a/util/lock/ipc_lock.h +++ b/util/lock/ipc_lock.h @@ -32,17 +32,17 @@ #define __UTIL_IPC_LOCK_H struct ipc_lock { - int is_held; /* internal */ - const char *filename; /* provided by the developer */ - int fd; /* internal */ + int is_held; /* internal */ + const char *filename; /* provided by the developer */ + int fd; /* internal */ }; /* don't use C99 initializers here, so this can be used in C++ code */ -#define LOCKFILE_INIT(lockfile) \ - { \ - 0, /* is_held */ \ - lockfile, /* filename */ \ - -1, /* fd */ \ +#define LOCKFILE_INIT(lockfile) \ + { \ + 0, /* is_held */ \ + lockfile, /* filename */ \ + -1, /* fd */ \ } /* -- cgit v1.2.1 From fc35dd52268d92267f0b2a3dd3cdc24b577a1a78 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:53:36 -0600 Subject: driver/retimer/ps8802.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ia6dbe45e147611e604671ccdfd3d26d41a8a5810 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730056 Reviewed-by: Jeremy Bettis --- driver/retimer/ps8802.c | 151 +++++++++++++++++------------------------------- 1 file changed, 53 insertions(+), 98 deletions(-) diff --git a/driver/retimer/ps8802.c b/driver/retimer/ps8802.c index 9738123ace..7a2dfde0ba 100644 --- a/driver/retimer/ps8802.c +++ b/driver/retimer/ps8802.c @@ -16,22 +16,19 @@ #define PS8802_DEBUG 0 #define PS8802_I2C_WAKE_DELAY 500 -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USB, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USB, format, ##args) int ps8802_i2c_read(const struct usb_mux *me, int page, int offset, int *data) { int rv; - rv = i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) ccprintf("%s(%d:0x%02X, 0x%02X) =>0x%02X\n", __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, *data); + me->i2c_port, me->i2c_addr_flags + page, offset, + *data); return rv; } @@ -42,58 +39,43 @@ int ps8802_i2c_write(const struct usb_mux *me, int page, int offset, int data) int pre_val, post_val; if (PS8802_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write8(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write8(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X) " - "0x%02X=>0x%02X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + "0x%02X=>0x%02X\n", + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; } -int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, - int data) +int ps8802_i2c_write16(const struct usb_mux *me, int page, int offset, int data) { int rv; int pre_val, post_val; if (PS8802_DEBUG) - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_write16(me->i2c_port, - me->i2c_addr_flags + page, - offset, data); + rv = i2c_write16(me->i2c_port, me->i2c_addr_flags + page, offset, data); if (PS8802_DEBUG) { - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%04X) " "0x%04X=>0x%04X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, data, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, data, pre_val, post_val); } return rv; @@ -106,62 +88,46 @@ int ps8802_i2c_field_update8(const struct usb_mux *me, int page, int offset, int pre_val, post_val; if (PS8802_DEBUG) - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update8(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update8(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8802_DEBUG) { - i2c_read8(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read8(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%02X) " "0x%02X=>0x%02X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; } int ps8802_i2c_field_update16(const struct usb_mux *me, int page, int offset, - uint16_t field_mask, uint16_t set_value) + uint16_t field_mask, uint16_t set_value) { int rv; int pre_val, post_val; if (PS8802_DEBUG) - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &pre_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &pre_val); - rv = i2c_field_update16(me->i2c_port, - me->i2c_addr_flags + page, - offset, - field_mask, - set_value); + rv = i2c_field_update16(me->i2c_port, me->i2c_addr_flags + page, offset, + field_mask, set_value); if (PS8802_DEBUG) { - i2c_read16(me->i2c_port, - me->i2c_addr_flags + page, - offset, &post_val); + i2c_read16(me->i2c_port, me->i2c_addr_flags + page, offset, + &post_val); ccprintf("%s(%d:0x%02X, 0x%02X, 0x%02X, 0x%04X) " "0x%04X=>0x%04X\n", - __func__, - me->i2c_port, - me->i2c_addr_flags + page, - offset, field_mask, set_value, - pre_val, post_val); + __func__, me->i2c_port, me->i2c_addr_flags + page, + offset, field_mask, set_value, pre_val, post_val); } return rv; @@ -179,9 +145,7 @@ int ps8802_i2c_wake(const struct usb_mux *me) /* If in standby, first read will fail, second should succeed. */ for (int i = 0; i < 2; i++) { - rv = ps8802_i2c_read(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, + rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &data); if (rv == EC_SUCCESS) return rv; @@ -200,7 +164,7 @@ static int ps8802_enter_low_power_mode(const struct usb_mux *me) int rv; rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, - PS8802_MODE_STANDBY_MODE); + PS8802_MODE_STANDBY_MODE); if (rv) CPRINTS("C%d: PS8802: Failed to enter low power mode!", @@ -225,8 +189,8 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, *ack_required = false; if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) - return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS - : EC_ERROR_NOT_POWERED; + return (mux_state == USB_PD_MUX_NONE) ? EC_SUCCESS : + EC_ERROR_NOT_POWERED; /* Make sure the PS8802 is awake */ rv = ps8802_i2c_wake(me); @@ -234,18 +198,16 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, return rv; if (PS8802_DEBUG) - ccprintf("%s(%d, 0x%02X) %s %s %s\n", - __func__, me->usb_port, mux_state, - (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", - (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", - (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ? "FLIP" : ""); + ccprintf("%s(%d, 0x%02X) %s %s %s\n", __func__, me->usb_port, + mux_state, + (mux_state & USB_PD_MUX_USB_ENABLED) ? "USB" : "", + (mux_state & USB_PD_MUX_DP_ENABLED) ? "DP" : "", + (mux_state & USB_PD_MUX_POLARITY_INVERTED) ? "FLIP" : + ""); /* Set the mode and flip */ - val = (PS8802_MODE_DP_REG_CONTROL | - PS8802_MODE_USB_REG_CONTROL | - PS8802_MODE_FLIP_REG_CONTROL | - PS8802_MODE_IN_HPD_REG_CONTROL); + val = (PS8802_MODE_DP_REG_CONTROL | PS8802_MODE_USB_REG_CONTROL | + PS8802_MODE_FLIP_REG_CONTROL | PS8802_MODE_IN_HPD_REG_CONTROL); if (mux_state & USB_PD_MUX_USB_ENABLED) val |= PS8802_MODE_USB_ENABLE; @@ -254,10 +216,7 @@ static int ps8802_set_mux(const struct usb_mux *me, mux_state_t mux_state, if (mux_state & USB_PD_MUX_POLARITY_INVERTED) val |= PS8802_MODE_FLIP_ENABLE; - rv = ps8802_i2c_write(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, - val); + rv = ps8802_i2c_write(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, val); return rv; } @@ -276,10 +235,7 @@ static int ps8802_get_mux(const struct usb_mux *me, mux_state_t *mux_state) if (rv) return rv; - rv = ps8802_i2c_read(me, - PS8802_REG_PAGE2, - PS8802_REG2_MODE, - &val); + rv = ps8802_i2c_read(me, PS8802_REG_PAGE2, PS8802_REG2_MODE, &val); if (rv) return rv; @@ -309,8 +265,7 @@ int ps8802_chg_i2c_addr(int i2c_port) { int rv; - rv = i2c_write8(i2c_port, - PS8802_P1_ADDR, PS8802_ADDR_CFG, + rv = i2c_write8(i2c_port, PS8802_P1_ADDR, PS8802_ADDR_CFG, PS8802_I2C_ADDR_FLAGS_ALT); return rv; -- cgit v1.2.1 From ca3756710567d8ae6a0ff1417194f41713a648f6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:03:43 -0600 Subject: board/sasukette/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I33b294e7a1513af39c833b625a72fe2b53807896 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728913 Reviewed-by: Jeremy Bettis --- board/sasukette/usb_pd_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/sasukette/usb_pd_policy.c b/board/sasukette/usb_pd_policy.c index 15faf41ffc..89df538eaa 100644 --- a/board/sasukette/usb_pd_policy.c +++ b/board/sasukette/usb_pd_policy.c @@ -11,8 +11,8 @@ #include "driver/tcpm/tcpci.h" #include "usb_pd.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) int pd_check_vconn_swap(int port) { -- cgit v1.2.1 From 468d4c451db761aadd3edc06c9c83f47e26c9776 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:41 -0600 Subject: baseboard/honeybuns/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ib626cc16024785f9a5d5ae4153c02a64d4ec0dc0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727889 Reviewed-by: Jeremy Bettis --- baseboard/honeybuns/baseboard.h | 67 ++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h index a22be156fe..65f3eb456f 100644 --- a/baseboard/honeybuns/baseboard.h +++ b/baseboard/honeybuns/baseboard.h @@ -40,30 +40,30 @@ /* Do not use a dedicated PSTATE bank */ #undef CONFIG_FLASH_PSTATE_BANK -#define CONFIG_SHAREDLIB_SIZE 0 +#define CONFIG_SHAREDLIB_SIZE 0 -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_STORAGE_OFF 0 -#define CONFIG_RO_SIZE (64*1024) +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RO_SIZE (64 * 1024) -#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF) -#define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE_BYTES - \ - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) +#define CONFIG_RW_MEM_OFF (CONFIG_RO_SIZE + CONFIG_RO_MEM_OFF) +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_RW_SIZE \ + (CONFIG_FLASH_SIZE_BYTES - (CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF)) -#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF -#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE -#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF -#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE +#define CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_RO_MEM_OFF +#define CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_RO_SIZE +#define CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_RW_MEM_OFF +#define CONFIG_EC_WRITABLE_STORAGE_SIZE CONFIG_RW_SIZE -#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF -#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 #define CONFIG_STM_HWTIMER32 #define TIM_CLOCK32 2 -#define TIM_CLOCK_MSB 3 +#define TIM_CLOCK_MSB 3 #define TIM_CLOCK_LSB 15 #define TIM_WATCHDOG 7 @@ -80,7 +80,7 @@ #define CONFIG_UART_TX_DMA_PH DMAMUX_REQ_USART3_TX /* CBI Configs */ -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 #define CONFIG_CBI_EEPROM #define CONFIG_BOARD_VERSION_CBI #define CONFIG_CMD_CBI @@ -101,12 +101,12 @@ #define CONFIG_USB_MS_EXTENDED_COMPAT_ID_DESCRIPTOR /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_UPDATE 1 -#define USB_EP_COUNT 2 +#define USB_EP_CONTROL 0 +#define USB_EP_UPDATE 1 +#define USB_EP_COUNT 2 -#define USB_IFACE_UPDATE 0 -#define USB_IFACE_COUNT 1 +#define USB_IFACE_UPDATE 0 +#define USB_IFACE_COUNT 1 #ifndef __ASSEMBLER__ /* USB string indexes */ @@ -197,14 +197,14 @@ enum usb_strings { #define CONFIG_SHA256 /* Define typical operating power and max power. */ -#define PD_MAX_VOLTAGE_MV 5000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 5000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 15000 #define PD_OPERATING_POWER_MW 15000 /* TODO(b:147314141): Verify these timings */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* I2C Bus Configuration */ #define CONFIG_I2C @@ -216,8 +216,8 @@ enum usb_strings { * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_WP_L GPIO_EC_WP_L +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_WP_L GPIO_EC_WP_L #ifndef __ASSEMBLER__ @@ -226,8 +226,8 @@ enum usb_strings { struct power_seq { enum gpio_signal signal; /* power/reset gpio_signal to control */ - int level; /* level to set in power sequence */ - unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */ + int level; /* level to set in power sequence */ + unsigned int delay_ms; /* delay (in msec) after setting gpio_signal */ }; enum mf_preference { @@ -239,9 +239,7 @@ enum mf_preference { * This is required as adc_channel is included in adc.h which ends up being * included when TCPMv2 functions are included */ -enum adc_channel { - ADC_CH_COUNT -}; +enum adc_channel { ADC_CH_COUNT }; extern const struct power_seq board_power_seq[]; extern const size_t board_power_seq_count; @@ -279,7 +277,6 @@ int baseboard_config_usbc_usb3_ppc(void); */ void baseboard_usb3_check_state(void); - /* * Set MST_LANE_CONTROL gpio to match the DP pin configuration selected * by the host in the DP Configure SVDM message. @@ -323,7 +320,7 @@ int c1_ps8805_is_sourcing_vbus(int port); * @param port: The Type-C port number. * @param enable: 1: Turn on VBUS, 0: turn off VBUS. * @return EC_SUCCESS on success, error otherwise. - */ + */ int c1_ps8805_vbus_source_enable(int port, int enable); #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 5f61001bf520321d84dd4a14743f166ea2e92528 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:17:00 -0600 Subject: include/usb_common.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ifa9913f65273f8a00d2c475658a00f00eae18f95 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730430 Reviewed-by: Jeremy Bettis --- include/usb_common.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/include/usb_common.h b/include/usb_common.h index bd779780ee..4d770e1559 100644 --- a/include/usb_common.h +++ b/include/usb_common.h @@ -33,10 +33,10 @@ enum pd_drp_next_states { * us of a connection. * */ -enum pd_drp_next_states drp_auto_toggle_next_state(uint64_t *drp_sink_time, - enum pd_power_role power_role, enum pd_dual_role_states drp_state, - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2, - bool auto_toggle_supported); +enum pd_drp_next_states drp_auto_toggle_next_state( + uint64_t *drp_sink_time, enum pd_power_role power_role, + enum pd_dual_role_states drp_state, enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2, bool auto_toggle_supported); enum pd_pref_type { /* prefer voltage larger than or equal to pd_pref_config.mv */ @@ -105,7 +105,8 @@ int usb_get_battery_soc(void); * @return current limit (mA) with DTS flag set if appropriate */ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, - enum tcpc_cc_voltage_status cc1, enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc1, + enum tcpc_cc_voltage_status cc2); /** * Returns the polarity of a Sink. @@ -115,7 +116,7 @@ typec_current_t usb_get_typec_current_limit(enum tcpc_cc_polarity polarity, * @return polarity */ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Returns the polarity of a Source. @@ -125,7 +126,7 @@ enum tcpc_cc_polarity get_snk_polarity(enum tcpc_cc_voltage_status cc1, * @return polarity */ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1, - enum tcpc_cc_voltage_status cc2); + enum tcpc_cc_voltage_status cc2); /** * Find PDO index that offers the most amount of power and stays within @@ -137,8 +138,8 @@ enum tcpc_cc_polarity get_src_polarity(enum tcpc_cc_voltage_status cc1, * @param pdo raw pdo corresponding to index, or index 0 on error (output) * @return index of PDO within source cap packet */ -int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t * const src_caps, - int max_mv, uint32_t *selected_pdo); +int pd_find_pdo_index(uint32_t src_cap_cnt, const uint32_t *const src_caps, + int max_mv, uint32_t *selected_pdo); /** * Extract power information out of a Power Data Object (PDO) @@ -161,7 +162,7 @@ void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv, * @param port USB-C port number */ void pd_build_request(int32_t vpd_vdo, uint32_t *rdo, uint32_t *ma, - uint32_t *mv, int port); + uint32_t *mv, int port); /** * Notifies a task that is waiting on a system jump, that it's complete. -- cgit v1.2.1 From 3a41cf13988ba1e465e770f7f4f140241780cecb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:32 -0600 Subject: core/host/irq_handler.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I55e35249e1eaa05f25d704568aed7bec9d5f89aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729840 Reviewed-by: Jeremy Bettis --- core/host/irq_handler.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/core/host/irq_handler.h b/core/host/irq_handler.h index 17e3df52d9..883a8c1239 100644 --- a/core/host/irq_handler.h +++ b/core/host/irq_handler.h @@ -15,16 +15,16 @@ * Macro to connect the interrupt handler "routine" to the irq number "irq" and * ensure it is enabled in the interrupt controller with the right priority. */ -#define DECLARE_IRQ(irq, routine, priority) \ - static void __keep routine(void); \ - void IRQ_HANDLER(irq)(void) \ - { \ - void *ret = __builtin_return_address(0); \ - task_start_irq_handler(ret); \ - routine(); \ - task_resched_if_needed(ret); \ - } \ - const struct irq_priority __keep IRQ_PRIORITY(irq) \ - __attribute__((section(".rodata.irqprio"))) \ - = {irq, priority} -#endif /* __CROS_EC_IRQ_HANDLER_H */ +#define DECLARE_IRQ(irq, routine, priority) \ + static void __keep routine(void); \ + void IRQ_HANDLER(irq)(void) \ + { \ + void *ret = __builtin_return_address(0); \ + task_start_irq_handler(ret); \ + routine(); \ + task_resched_if_needed(ret); \ + } \ + const struct irq_priority __keep IRQ_PRIORITY(irq) \ + __attribute__((section(".rodata.irqprio"))) = { irq, \ + priority } +#endif /* __CROS_EC_IRQ_HANDLER_H */ -- cgit v1.2.1 From 68042a0269a7aa7c54f456262a66aad0e02760bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:33:47 -0600 Subject: zephyr/projects/trogdor/lazor/src/hibernate.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I560db080aab73bfa2fc7fd79ace1350b90ed3712 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730806 Reviewed-by: Jeremy Bettis --- zephyr/projects/trogdor/lazor/src/hibernate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/projects/trogdor/lazor/src/hibernate.c b/zephyr/projects/trogdor/lazor/src/hibernate.c index 5ad97a8c48..58ab375ca8 100644 --- a/zephyr/projects/trogdor/lazor/src/hibernate.c +++ b/zephyr/projects/trogdor/lazor/src/hibernate.c @@ -17,12 +17,12 @@ void board_hibernate(void) * Sensors are unpowered in hibernate. Apply PD to the * interrupt lines such that they don't float. */ - gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL( - gpio_accel_gyro_int_l), - GPIO_DISCONNECTED); - gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL( - gpio_lid_accel_int_l), - GPIO_DISCONNECTED); + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_accel_gyro_int_l), + GPIO_DISCONNECTED); + gpio_pin_configure_dt( + GPIO_DT_FROM_NODELABEL(gpio_lid_accel_int_l), + GPIO_DISCONNECTED); } /* -- cgit v1.2.1 From eae9efb36d303cd421e6f5ec844d0842dfd42ff3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:08:05 -0600 Subject: board/taniks/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5b6b15394d269b113e6c5cbf84fdd42917a7ea82 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729014 Reviewed-by: Jeremy Bettis --- board/taniks/led.c | 61 +++++++++++++++++++++++++++++------------------------- 1 file changed, 33 insertions(+), 28 deletions(-) diff --git a/board/taniks/led.c b/board/taniks/led.c index 1631bce51f..ec53a2613a 100644 --- a/board/taniks/led.c +++ b/board/taniks/led.c @@ -14,44 +14,49 @@ #include "led_common.h" #include "gpio.h" -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) -#define LED_OFF_LVL 1 -#define LED_ON_LVL 0 +#define LED_OFF_LVL 1 +#define LED_ON_LVL 0 __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 97; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_RED, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_FACTORY_TEST] = {{EC_LED_COLOR_RED, 2 * LED_ONE_SEC}, - {EC_LED_COLOR_GREEN, 2 * LED_ONE_SEC} }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_RED, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_GREEN, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_RED, 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_RED, 2 * LED_ONE_SEC }, + { EC_LED_COLOR_GREEN, + 2 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 3 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = {{LED_OFF, LED_INDEFINITE} }, -}; + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 3 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED -}; +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, + EC_LED_ID_POWER_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -- cgit v1.2.1 From 11033857174f369fe98faec2947665ac11f7a739 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:14:20 -0600 Subject: baseboard/brya/charger_bq25720.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I13ab137c5acd4bf20be330808a59708765936c34 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727864 Reviewed-by: Jeremy Bettis --- baseboard/brya/charger_bq25720.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/baseboard/brya/charger_bq25720.c b/baseboard/brya/charger_bq25720.c index 184cc68eaa..cbc657271b 100644 --- a/baseboard/brya/charger_bq25720.c +++ b/baseboard/brya/charger_bq25720.c @@ -15,9 +15,8 @@ #include "usb_pd.h" #include "util.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) #ifndef CONFIG_ZEPHYR /* Charger Chip Configuration */ @@ -86,7 +85,6 @@ int board_set_active_charge_port(int port) __overridable void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, int charge_mv) { - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), - charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } -- cgit v1.2.1 From 5e5f644fad6bd925da52251a2c8868e770872520 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:21:28 -0600 Subject: test/motion_angle_data_literals_tablet.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I14a45488dfe8ce1204c65c54baba4151b55258f3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730486 Reviewed-by: Jeremy Bettis --- test/motion_angle_data_literals_tablet.c | 2038 +++++++++++++++--------------- 1 file changed, 1019 insertions(+), 1019 deletions(-) diff --git a/test/motion_angle_data_literals_tablet.c b/test/motion_angle_data_literals_tablet.c index 456779f457..76ed6186c4 100644 --- a/test/motion_angle_data_literals_tablet.c +++ b/test/motion_angle_data_literals_tablet.c @@ -11,1030 +11,1030 @@ * The arrays contain actual accelerator readings. */ const float kAccelerometerVerticalHingeTestData[] = { - -0.0766145f, 6.02381f, 7.85298f, -0.268151f, -8.84897f, - -1.3216f, -0.402226f, 5.11401f, 8.77236f, -1.10133f, - -10.1706f, 1.24498f, -1.18752f, 6.40688f, 8.0924f, - -2.60489f, -8.99262f, 2.58574f, 0.632069f, 9.05008f, - 3.61046f, 1.50356f, -9.67257f, 1.93451f, 0.411803f, - 8.81066f, 0.268151f, -0.00957681f, -8.7532f, 2.15478f, - -0.0191536f, 9.49062f, -0.68953f, 0.0383072f, -8.94474f, - 2.99754f, -0.871489f, 9.80665f, 1.53229f, -0.92895f, - -9.88326f, 0.957681f, 0.507571f, 9.19373f, 1.71425f, - 0.287304f, -9.03093f, 0.651223f, 0.363919f, 9.71088f, - 1.18752f, 1.10133f, -10.0556f, 2.98796f, 0.23942f, - 9.39485f, 1.0343f, 0.842759f, -9.73961f, -1.12049f, - 0.172383f, 9.50977f, 1.18752f, 0.0383072f, -9.9503f, - 0.957681f, -0.373495f, 9.96946f, 1.01514f, 0.794875f, - -10.1897f, -1.38864f, -9.50977f, -1.04387f, 0.325611f, - -9.76834f, 1.05345f, -0.679953f, -9.76834f, -0.641646f, - 0.488417f, -9.2895f, 0.316035f, 0.258574f, -9.29908f, - -0.890643f, 0.469264f, -9.33739f, 0.823605f, -0.45011f, - -9.69173f, -1.02472f, 0.536301f, -9.52892f, 0.90022f, - -0.411803f, -9.34696f, -0.890643f, 0.430956f, -9.48104f, - 0.823605f, -0.603339f, -9.7875f, -0.565032f, 0.574608f, - -9.96946f, 0.536301f, -0.699107f, -9.57681f, -0.823605f, - 0.641646f, -9.43316f, 0.593762f, -0.775721f, -9.35654f, - -1.04387f, 0.440533f, -9.77792f, 1.01514f, -0.881066f, - -9.32781f, -1.10133f, 0.306458f, -9.414f, 0.995988f, - 0.0287304f, -9.26077f, -1.01514f, 0.268151f, -9.29908f, - 0.881066f, 0.00957681f, -9.42358f, -0.679953f, 0.201113f, - -9.49062f, 0.488417f, -0.00957681f, -9.47146f, -0.363919f, - 0.191536f, -9.32781f, 0.124498f, 0.124498f, -9.5385f, - -0.0766145f, 0.268151f, -9.32781f, -0.172383f, 0.0574608f, - -9.69173f, 0.21069f, 0.354342f, -9.50019f, -0.306458f, - 0.0383072f, -9.54808f, 0.507571f, 0.363919f, -9.20331f, - -0.775721f, 0.0574608f, -9.59596f, 0.651223f, 0.679953f, - -9.56723f, -0.794875f, -0.0287304f, -9.49062f, 0.794875f, - 0.612916f, -9.06924f, -1.10133f, -0.201113f, -9.20331f, - 1.90578f, 1.46525f, -9.29908f, -2.17394f, 0.603339f, - -0.995988f, 0.0766145f, 9.58638f, -0.344765f, -0.92895f, - -9.1267f, -2.03986f, -0.497994f, 10.477f, -2.49955f, - -0.0957681f, -10.4866f, -1.5706f, -0.23942f, 9.13627f, - -1.92494f, -0.325611f, -9.05008f, -1.5706f, -0.0383072f, - 10.1323f, -1.87705f, -0.632069f, -9.52892f, -1.20668f, - 0.105345f, 9.14585f, -1.13964f, -0.718261f, -9.02135f, - -1.58975f, 0.296881f, 9.50019f, -1.74298f, -1.00556f, - -9.27993f, -1.09176f, 0.23942f, 9.87369f, -1.04387f, - -0.995988f, -9.35654f, -2.08774f, -0.526724f, 9.89284f, - -1.40779f, -0.459687f, -9.50977f, -2.70066f, -1.47483f, - 8.95431f, -1.92494f, 0.526724f, -8.95431f, -1.05345f, - -0.938527f, 9.14585f, -3.02627f, 1.04387f, -8.78193f, - 1.00556f, -3.56257f, 9.0022f, 1.96325f, 2.36547f, - -9.83538f, 1.02472f, -2.59531f, 9.49062f, 1.0726f, - 1.77171f, -9.06924f, 0.0861913f, -2.17394f, 9.21289f, - -0.823605f, 1.52271f, -10.1323f, 0.316035f, -3.09331f, - 10.0844f, 0.555455f, 2.00155f, -9.75877f, 1.51314f, - -2.24097f, 9.61511f, 0.670376f, 1.35033f, -9.77792f, - 0.986411f, -3.36146f, 9.59596f, 1.77171f, 2.29843f, - -9.48104f, 1.4461f, -2.8922f, 8.88728f, 1.84832f, - 2.38462f, -9.19373f, 1.75256f, -2.6432f, 9.89284f, - 1.38864f, 2.19309f, -9.20331f, 9.98861f, -0.718261f, - -0.746991f, 10.6111f, 0.632069f, 0.948104f, 8.99262f, - -0.258574f, 0.517148f, 9.10754f, 0.21069f, -1.21625f, - 9.90242f, -0.162806f, 0.0287304f, 10.5249f, -0.0861913f, - 0.229843f, 9.83538f, 0.0f, 0.181959f, 10.4291f, - -0.172383f, -0.47884f, 9.43316f, 0.201113f, -0.268151f, - 9.76834f, -0.134075f, -0.354342f, 10.0556f, 1.0726f, - 0.277727f, 9.93115f, -1.05345f, 0.363919f, 9.79707f, - 0.651223f, 0.699107f, 10.0173f, -0.775721f, 0.0670376f, - 9.49062f, 0.296881f, 0.919373f, 10.1801f, -0.68953f, - -0.651223f, 9.70131f, 1.00556f, 0.248997f, 9.42358f, - -0.995988f, 1.45567f, 9.13627f, -1.35033f, 2.36547f, - 9.40442f, 0.976834f, -4.34787f, 8.79151f, -0.90022f, - 1.56102f, 8.92558f, 0.6608f, -2.3942f, 9.59596f, - -0.363919f, 1.40779f, 9.05966f, 0.181959f, -2.1452f, - 9.48104f, -0.612916f, 2.36547f, 9.03093f, 0.21069f, - -2.18351f, 9.74919f, -1.5706f, 2.07817f, 8.85855f, - 1.04387f, -2.30801f, 8.81066f, -1.66636f, 3.4285f, - 8.52336f, 0.440533f, -4.52983f, 9.27993f, -2.19309f, - 2.2697f, 8.83939f, 0.90022f, -2.48039f, 9.1267f, - -2.77727f, 1.4461f, 8.78193f, 0.814029f, -4.24253f, - 8.90643f, -3.39977f, 0.651223f, 8.86812f, 1.08218f, - -2.34632f, 9.42358f, -3.26569f, 0.402226f, 8.94474f, - 0.526724f, -2.65278f, 9.38527f, -3.21781f, 0.0f, - 9.20331f, 0.143652f, -2.71024f, 9.44273f, -2.8922f, - -0.497994f, 9.35654f, 0.105345f, -2.78685f, 9.09797f, - -3.4285f, -1.00556f, 8.81066f, 0.785298f, -3.84988f, - 9.31823f, -3.09331f, -1.4461f, 8.68616f, 0.555455f, - -3.27527f, 9.414f, -2.5187f, -1.79086f, 8.59997f, - 0.766145f, -3.47638f, 9.0022f, -2.67193f, -2.43251f, - 8.77236f, 1.39821f, -2.85389f, 8.25521f, -3.29442f, - -2.46124f, 8.15944f, 1.09176f, -3.51469f, 8.72447f, - -2.69108f, -2.48997f, 8.91601f, 0.881066f, -3.66792f, - 8.92558f, -2.33674f, -2.31759f, 8.84897f, 1.06303f, - -3.055f, 8.92558f, -2.49955f, -2.29843f, 8.81066f, - 0.919373f, -2.56658f, 9.31823f, -2.78685f, -1.81959f, - 9.06924f, 0.411803f, -2.86347f, 9.38527f, -2.78685f, - -1.70467f, 9.25119f, 0.335188f, -4.67348f, 9.165f, - -3.9648f, -0.622492f, 8.65743f, 0.248997f, -3.055f, - 9.414f, -3.67749f, 0.0287304f, 8.82982f, 0.852336f, - -2.50912f, 8.82024f, -3.47638f, 0.201113f, 8.98304f, - 1.06303f, -3.33273f, 8.89685f, -3.64876f, 0.718261f, - 8.91601f, 1.52271f, -2.70066f, 8.95431f, -3.56257f, - 1.35991f, 9.05008f, 1.67594f, -3.16992f, 9.08839f, - -3.16035f, 2.03028f, 9.07881f, 1.64721f, -3.04542f, - 8.91601f, -3.11246f, 2.52828f, 8.88728f, 2.07817f, - -1.99198f, 9.1267f, -2.806f, 0.162806f, 9.1267f, - 2.806f, -2.07817f, 9.14585f, -2.31759f, 2.16436f, - 8.8777f, 2.19309f, -1.88663f, 9.88326f, -2.5187f, - 1.94409f, 9.1267f, 2.46124f, -2.806f, 7.64229f, - -6.0717f, 2.9305f, 8.07325f, 5.64074f, -2.63362f, - 4.29999f, -7.9679f, 0.622492f, 4.71179f, 7.74764f, - -3.41892f, 4.42448f, -8.99262f, 1.13964f, 3.98395f, - 8.47547f, -1.9824f, -0.699107f, -9.46189f, -0.794875f, - -0.593762f, 9.24162f, -2.74854f, 1.88663f, -8.8777f, - -0.153229f, 0.861913f, 8.98304f, -2.48039f, -1.52271f, - -9.32781f, -3.39977f, 0.0574608f, 8.99262f, -5.88974f, - -0.746991f, -3.93607f, -8.01579f, -1.17795f, 8.41801f, - -4.17549f, -2.30801f, -2.61447f, -9.44273f, -2.3942f, - 7.46991f, -5.01825f, -1.0343f, 1.89621f, -8.8777f, - -0.890643f, 8.65743f, -4.31914f, -2.16436f, 1.49398f, - -9.69173f, -1.37906f, 9.05008f, -2.43251f, -1.87705f, - 0.402226f, -8.95431f, -2.01113f, 8.72447f, -3.54342f, - -0.344765f, -2.95923f, -8.42759f, -0.92895f, 8.99262f, - -2.34632f, -0.392649f, -6.70376f, -6.55054f, -0.919373f, - 8.80109f, -2.35589f, -0.0766145f, -8.8777f, -5.89931f, - 0.890643f, 9.7875f, 2.24097f, -0.536301f, -8.08282f, - -4.88417f, -0.191536f, 9.21289f, 1.16837f, -0.440533f, - -7.93917f, -4.81713f, -0.890643f, 9.08839f, 1.75256f, - -1.20668f, -9.414f, -2.57616f, -0.708684f, 9.50977f, - 1.40779f, -1.14922f, -9.8258f, -1.24498f, -0.584185f, - 9.63427f, 0.727837f, -0.181959f, -9.25119f, -2.31759f, - -0.0574608f, 9.64384f, -0.612916f, 1.21625f, -9.50977f, - -1.16837f, 0.756568f, 9.45231f, -0.316035f, 1.21625f, - -10.5441f, -0.45011f, 1.5706f, 9.7875f, -1.22583f, - 9.07881f, 0.0766145f, -2.34632f, 9.26077f, 0.316035f, - 4.28083f, 8.72447f, 0.584185f, -3.27527f, 8.39886f, - 0.47884f, 3.98395f, 9.26077f, 2.35589f, -2.98796f, - 9.52892f, -1.61848f, 3.73495f, 8.91601f, 2.98796f, - -3.36146f, 9.7875f, -2.31759f, 3.60088f, 8.86812f, - 3.32315f, -3.62961f, 9.76834f, -2.46124f, 2.72939f, - 2.31759f, 10.2089f, -2.3942f, 0.995988f, -8.68616f, - 5.5737f, 1.13006f, 9.04051f, -2.09732f, 1.26414f, - -8.51378f, 4.40533f, 0.852336f, 9.91199f, -2.07817f, - 0.622492f, -9.18416f, 4.29999f, 0.229843f, 10.0269f, - -1.08218f, 0.220267f, -9.40442f, 4.40533f, 0.0766145f, - 9.54808f, -1.89621f, 0.967257f, -9.05966f, 3.92649f, - 0.335188f, 9.62469f, -0.497994f, 0.430956f, -9.71088f, - 4.02226f, 0.718261f, 9.63427f, 1.59933f, 0.383072f, - -8.88728f, 3.24654f, 0.42138f, 8.71489f, 2.55701f, - 0.68953f, -9.64384f, 1.67594f, 1.0726f, -7.0198f, - 7.20176f, 0.641646f, -9.17458f, 4.18506f, -0.402226f, - -2.46124f, 8.78193f, -0.0383072f, -8.31267f, 4.03184f, - 0.23942f, 2.27928f, 10.4675f, -0.517148f, -9.47146f, - 4.14676f, -1.37906f, 9.59596f, -4.07972f, 3.45723f, - -9.663f, 1.71425f, -0.134075f, 6.95276f, -5.80354f, - 0.268151f, -5.38217f, 7.03895f, 0.00957681f, 5.20978f, - -7.75721f, -0.047884f, -2.83473f, 8.53294f, -0.306458f, - 1.64721f, -8.64786f, 0.766145f, 0.162806f, 8.84897f, - -0.191536f, -2.58574f, -9.19373f, 0.0f, 4.05099f, - 8.52336f, -0.0383072f, -3.10289f, -9.17458f, 0.45011f, - 4.11803f, 9.19373f, 0.0957681f, -2.47082f, -9.61511f, - 0.804452f, 3.98395f, 8.52336f, 0.114922f, 4.00311f, - -8.76278f, 0.699107f, 4.53941f, 8.28394f, -0.0383072f, - 7.95833f, -6.57927f, -0.124498f, 3.52426f, 10.1035f, - -0.229843f, 6.68461f, -6.2345f, -0.153229f, 3.04542f, - 9.59596f, -0.344765f, 7.47949f, -7.29753f, 0.114922f, - 3.90734f, 9.03093f, -0.383072f, 7.57525f, -7.20176f, - -0.172383f, 3.70622f, 9.8258f, -0.335188f, 7.21134f, - -6.7325f, -0.172383f, 2.71024f, 10.2855f, -0.114922f, - 6.608f, -7.41245f, -0.201113f, 1.87705f, 9.39485f, - 1.37906f, -0.0670376f, -9.47146f, 1.1971f, 1.8579f, - 9.49062f, 0.842759f, -1.63763f, -8.95431f, 0.679953f, - 2.8922f, 9.1267f, 1.43652f, -1.58017f, -9.01178f, - 0.890643f, 3.66792f, 9.22246f, 0.746991f, -1.18752f, - -9.04051f, 2.12605f, 2.72939f, 9.52892f, 3.79242f, - 1.48441f, -9.04051f, 4.57771f, -0.785298f, 9.61511f, - 4.61602f, 1.21625f, -8.4659f, 4.94163f, -0.574608f, - 8.4659f, 4.67348f, 1.48441f, -8.23605f, 4.86502f, - -0.852336f, 9.24162f, 5.12359f, 0.92895f, -9.03093f, - 5.84185f, -0.430956f, 8.92558f, 5.38217f, 0.440533f, - -8.37971f, 6.72292f, -0.220267f, 8.02536f, 6.608f, - 1.6089f, -6.30154f, 6.33985f, 0.277727f, 6.58884f, - 9.85453f, 1.39821f, 0.153229f, 10.0844f, -1.46525f, - 0.45011f, 9.68215f, 1.90578f, -0.0766145f, 9.98861f, - -1.96325f, 0.536301f, 9.90242f, 2.20267f, 0.143652f, - 9.94073f, -2.20267f, 0.191536f, 9.46189f, 1.95367f, - 0.0957681f, 9.74919f, -2.06859f, 0.296881f, 9.30866f, - 1.64721f, 0.153229f, 9.84496f, -1.92494f, 0.574608f, - 7.38372f, 0.488417f, 6.76123f, 8.83939f, -1.37906f, - -3.11246f, 9.2895f, 0.153229f, -0.976834f, 9.86411f, - -0.0574608f, -0.957681f, 9.26077f, 0.833182f, 2.07817f, - 9.26077f, -0.938527f, -0.957681f, 10.0269f, -0.354342f, - 2.43251f, 9.84496f, 0.153229f, -0.957681f, 0.986411f, - -8.74362f, 1.34075f, 2.09732f, 9.165f, -1.84832f, - -1.25456f, -10.228f, 2.19309f, 0.42138f, 9.73004f, - -1.23541f, -1.49398f, -10.1706f, 0.172383f, -1.22583f, - 10.2089f, -0.593762f, -2.2314f, -9.663f, -0.526724f, - -1.6089f, 9.65342f, 0.593762f, -2.38462f, -9.165f, - -1.4461f, -2.46124f, 9.42358f, 0.430956f, -2.38462f, - -9.73004f, 0.0383072f, -2.31759f, 9.57681f, -0.47884f, - -2.44209f, -9.5385f, -0.746991f, -2.32716f, 9.58638f, - 0.612916f, -2.34632f, -10.1418f, -1.0726f, -1.92494f, - 9.90242f, 0.890643f, -2.84431f, 9.38527f, -2.38462f, - -1.69509f, -9.50977f, 2.73897f, -3.88818f, 7.9296f, - -2.40378f, -1.5706f, -8.4659f, 2.62405f, -8.91601f, - -2.98796f, 0.497994f, -8.97347f, 2.79643f, 0.373495f, - -10.3717f, 1.02472f, -0.105345f, -10.0461f, -1.02472f, - 0.679953f, -4.89375f, 8.17859f, 0.0766145f, -6.12916f, - -7.61356f, 0.172383f, -6.4835f, 7.5561f, -0.363919f, - -6.09085f, -7.46991f, 0.699107f, -6.19619f, 7.62314f, - -0.248997f, -5.78439f, -7.52737f, 1.55144f, -6.33985f, - 7.50822f, -0.45011f, -5.6982f, -7.48906f, 1.48441f, - -6.36858f, 7.46991f, -0.373495f, -5.72693f, -7.44118f, - 1.63763f, -6.33027f, 7.8434f, -0.316035f, -6.54096f, - -7.57525f, 1.37906f, -6.69419f, 7.52737f, -0.258574f, - -6.41646f, -7.37414f, 1.21625f, -6.62715f, 7.61356f, - -0.392649f, -6.24408f, -7.48906f, 1.23541f, -6.18662f, - 7.60398f, -0.201113f, -5.9472f, -7.45076f, 1.39821f, - -6.14831f, 7.86256f, -0.584185f, -6.26323f, -7.50822f, - 1.6089f, -5.26724f, 8.74362f, -0.153229f, -4.57771f, - -8.41801f, 0.6608f, -3.56257f, 8.82024f, 0.114922f, - -2.86347f, -8.82982f, 0.948104f, -2.53785f, 9.27035f, - 0.23942f, -2.33674f, -9.29908f, 1.02472f, -2.12605f, - 9.67257f, 0.354342f, -2.1452f, -9.45231f, 0.335188f, - -1.71425f, 9.36612f, 0.287304f, -1.41737f, -9.27035f, - -0.229843f, -2.65278f, 8.94474f, -0.306458f, -0.737414f, - -9.414f, 0.172383f, -8.72447f, 5.46836f, 0.325611f, - -10.2663f, -1.80044f, -0.143652f, -9.35654f, -0.794875f, - -0.756568f, -10.1801f, 1.0343f, 1.20668f, -9.54808f, - -0.986411f, -0.766145f, -9.165f, 0.890643f, 1.13964f, - -8.92558f, -0.555455f, -1.22583f, -9.68215f, 0.976834f, - 0.344765f, -9.14585f, 4.05099f, -1.31202f, -9.57681f, - 0.68953f, 1.51314f, -9.54808f, 0.0957681f, 1.45567f, - -9.18416f, -0.229843f, -0.6608f, -9.71088f, 0.047884f, - 1.35033f, -9.87369f, 0.0383072f, -0.909797f, -8.57124f, - 1.1971f, 3.86903f, -9.76834f, -1.13964f, -2.2697f, - -9.38527f, 0.890643f, 2.74854f, -9.38527f, -1.20668f, - -2.3942f, -8.74362f, 1.4461f, 3.45723f, -8.99262f, - -1.72383f, -2.56658f, -9.48104f, 1.13006f, 2.98796f, - -8.80109f, -1.76213f, -2.52828f, -9.69173f, 1.15879f, - 2.3942f, -8.98304f, -1.68552f, -1.71425f, -8.93516f, - 1.25456f, 3.26569f, -9.61511f, -1.38864f, -2.46124f, - -9.37569f, 1.4461f, 3.40934f, -8.83939f, -2.1069f, - -2.42293f, -9.165f, 1.61848f, 2.9305f, -9.165f, - -2.04944f, -2.50912f, -9.31823f, 0.823605f, 0.0f, - -9.48104f, -0.909797f, 0.497994f, -9.30866f, 1.0343f, - -0.775721f, -9.01178f, -1.15879f, 0.814029f, -9.25119f, - 0.948104f, -0.00957681f, -8.80109f, -1.16837f, 0.737414f, - -9.62469f, 1.39821f, -0.248997f, -9.39485f, -1.45567f, - 0.957681f, -9.57681f, 1.79086f, -0.296881f, -9.50019f, - -1.81002f, 0.842759f, -10.0652f, 1.45567f, -0.248997f, - -9.05966f, -1.61848f, 0.871489f, -9.69173f, 1.56102f, - -0.459687f, -8.91601f, -1.77171f, 0.890643f, -9.48104f, - -0.47884f, -0.497994f, -9.48104f, 0.296881f, 0.632069f, - -10.094f, 0.191536f, -0.248997f, -10.4387f, -0.0670376f, - 0.6608f, -8.08282f, 4.95121f, -1.31202f, -8.17859f, - -4.70221f, 1.80044f, -7.9296f, 5.04698f, -0.536301f, - -8.38928f, -4.80756f, 0.68953f, -8.10198f, 5.23851f, - -0.507571f, -7.97748f, -5.17148f, 1.21625f, -8.37013f, - 5.22894f, -0.497994f, -8.01579f, -5.23851f, 0.976834f, - -8.20732f, 5.20978f, -0.335188f, -7.99663f, -5.19063f, - 0.995988f, -8.26478f, 5.02782f, -0.0957681f, -8.0924f, - -5.0374f, 0.948104f, -8.36055f, 5.02782f, -0.268151f, - -8.02536f, -5.09486f, 0.995988f, -8.28394f, 5.01825f, - -0.191536f, -8.20732f, -5.06613f, 0.861913f, -8.37971f, - 5.06613f, -0.325611f, -8.20732f, -5.00867f, 0.92895f, - -8.3414f, 5.04698f, -0.124498f, -8.13071f, -5.14275f, - 0.852336f, -8.29351f, 5.07571f, -0.0766145f, -8.07325f, - -5.10444f, 0.976834f, -8.47547f, 4.77883f, -0.392649f, - -8.13071f, -4.86502f, 1.05345f, -8.60955f, 2.71981f, - 2.79643f, -9.25119f, 1.31202f, -0.306458f, -9.14585f, - 1.02472f, 1.51314f, -8.64786f, -1.33118f, -1.13964f, - -9.35654f, 1.01514f, 2.31759f, -8.72447f, -1.49398f, - -1.72383f, -9.73004f, 1.58017f, 2.7677f, -9.73004f, - -1.84832f, -1.93451f, -9.15543f, 1.33118f, 2.20267f, - -8.93516f, -1.64721f, -0.995988f, -9.45231f, 0.727837f, - 1.81959f, -9.51935f, -0.909797f, -2.78685f, -9.93115f, - 0.191536f, 0.890643f, -9.84496f, -0.23942f, -0.976834f, - -9.61511f, -0.21069f, 0.517148f, -8.80109f, -0.153229f, - -0.430956f, -9.50019f, 0.373495f, 0.948104f, -9.27035f, - -0.555455f, -0.344765f, -9.57681f, 0.172383f, 0.881066f, - -9.43316f, -0.335188f, -0.756568f, -9.50977f, -0.0191536f, - 0.497994f, -9.42358f, -0.181959f, -0.737414f, -9.92157f, - 0.306458f, 0.545878f, -10.0173f, -0.248997f, -0.134075f, - -9.79707f, 0.0287304f, 0.536301f, -9.71088f, -0.162806f, - -0.181959f, -9.60554f, -0.047884f, 0.804452f, -9.39485f, - -0.181959f, -0.593762f, -9.64384f, -0.047884f, 0.612916f, - -9.58638f, -0.201113f, -0.363919f, -9.56723f, 0.248997f, - 0.411803f, -10.1706f, -0.316035f, -0.526724f, -9.63427f, - 0.459687f, 1.09176f, -9.71088f, -0.603339f, -0.23942f, - -9.62469f, -0.0383072f, 0.68953f, -9.50019f, -0.0861913f, - -1.13006f, -9.80665f, -0.134075f, 0.335188f, -9.40442f, - -0.114922f, -0.354342f, -9.34696f, 0.153229f, 1.54187f, - -9.10754f, -0.526724f, -1.00556f, -9.7875f, 0.0287304f, - 0.775721f, -9.58638f, -0.172383f, -0.641646f, -9.60554f, - 0.258574f, 0.919373f, -9.31823f, -0.402226f, -0.603339f, - -9.5385f, -0.0766145f, 0.92895f, -9.09797f, -0.220267f, - -0.354342f, -9.61511f, -0.335188f, 0.316035f, -9.27993f, - 0.0766145f, -0.47884f, -9.40442f, 0.23942f, 0.6608f, - -9.40442f, -0.335188f, -0.603339f, -9.85453f, -0.0766145f, - 0.459687f, -9.54808f, -0.0670376f, -0.287304f, -9.63427f, - -0.344765f, 0.296881f, -9.32781f, 0.0574608f, -0.220267f, - -9.71088f, 0.181959f, 0.354342f, -9.95988f, -0.248997f, - 0.201113f, -9.8258f, -0.0383072f, 0.833182f, -9.83538f, - -0.047884f, -0.670376f, -9.44273f, 0.0670376f, 0.6608f, - -8.90643f, -0.392649f, -0.354342f, -9.54808f, 0.0957681f, - 0.90022f, -9.05008f, -0.411803f, -0.335188f, -9.52892f, - 0.201113f, 1.12049f, -9.23204f, -0.459687f, -0.842759f, - -9.61511f, -0.162806f, 0.248997f, -9.87369f, 0.124498f, - -1.12049f, -9.70131f, -0.0383072f, 0.670376f, -9.50977f, - -0.162806f, -0.890643f, -9.15543f, 0.488417f, 1.51314f, - -8.94474f, -0.852336f, -0.90022f, -9.60554f, -0.23942f, - 0.622492f, -9.35654f, 0.0f, -0.948104f, -9.64384f, - -0.191536f, 1.21625f, -9.2895f, -0.0766145f, -0.785298f, - -9.55765f, -0.306458f, 0.555455f, -9.73004f, 0.172383f, - -0.603339f, -9.663f, -0.306458f, 0.383072f, -9.63427f, - 0.172383f, -0.354342f, -9.70131f, -0.373495f, 0.68953f, - -9.69173f, 0.181959f, -1.0343f, -9.47146f, -0.526724f, - 0.823605f, -9.23204f, 0.220267f, -1.36948f, -9.36612f, - -0.0670376f, 1.05345f, -8.91601f, -0.316035f, -0.814029f, - -9.93115f, -0.268151f, 1.58017f, -10.0748f, 0.143652f, - -1.26414f, -9.87369f, 0.047884f, 2.09732f, -9.39485f, - -0.344765f, -1.48441f, -9.48104f, 0.967257f, 0.699107f, - -9.34696f, -1.15879f, -0.105345f, -9.414f, 0.852336f, - 0.756568f, -9.62469f, -1.0343f, -0.114922f, -9.80665f, - 0.814029f, 0.737414f, -9.23204f, -1.0726f, -0.23942f, - -9.47146f, 0.890643f, 0.392649f, -9.24162f, -1.08218f, - -0.229843f, -9.42358f, 0.775721f, 0.325611f, -9.21289f, - -0.986411f, -0.201113f, -9.52892f, 1.79086f, 2.04944f, - -9.32781f, -2.15478f, -1.39821f, -8.86812f, 2.07817f, - 2.2697f, -8.91601f, -2.24097f, -1.7334f, -9.34696f, - 1.68552f, 2.29843f, -8.78193f, -2.19309f, -1.58017f, - -9.62469f, 1.7334f, 2.35589f, -9.165f, -2.18351f, - -1.63763f, -9.99819f, 2.28886f, 2.27928f, -10.0365f, - -2.36547f, -1.69509f, -10.726f, -0.488417f, -0.363919f, - -9.25119f, 0.976834f, -3.03585f, -9.31823f, 1.41737f, - 2.09732f, -8.8777f, -1.76213f, 0.651223f, -9.71088f, - 1.00556f, 2.28886f, -9.36612f, -1.13006f, -1.53229f, - -9.87369f, 0.814029f, 1.46525f, -9.92157f, -0.919373f, - -0.957681f, -9.35654f, 0.0191536f, 1.09176f, -9.9503f, - -0.0574608f, -1.0726f, -9.50977f, -0.181959f, 0.603339f, - -8.90643f, -0.172383f, -0.0766145f, -9.85453f, -0.287304f, - 0.833182f, -9.76834f, 0.181959f, -0.402226f, -9.50977f, - -0.0957681f, 0.287304f, -9.7875f, 0.0191536f, -0.47884f, - -9.58638f, 0.047884f, 0.344765f, -9.44273f, -0.181959f, - -0.0861913f, -9.57681f, 0.0287304f, 0.555455f, -9.42358f, - -0.220267f, 0.0f, -9.73004f, -0.229843f, 0.21069f, - -9.51935f, 0.0670376f, -0.21069f, -10.0173f, -0.00957681f, - 0.105345f, -9.68215f, -0.0670376f, -0.124498f, -9.50977f, - 0.114922f, 0.287304f, -9.42358f, -0.229843f, 0.0957681f, - -9.57681f, -0.181959f, 0.181959f, -9.32781f, -0.047884f, - 0.105345f, -10.0078f, -0.258574f, -2.19309f, -9.70131f, - 0.248997f, 1.64721f, -9.55765f, -0.612916f, 0.105345f, - -8.76278f, 0.191536f, 0.919373f, -9.414f, -0.0383072f, - -0.641646f, -9.74919f, 0.0670376f, 0.814029f, -9.80665f, - -0.134075f, -0.804452f, -9.44273f, 0.0957681f, 1.01514f, - -9.71088f, 0.220267f, -0.584185f, -9.32781f, -0.248997f, - 0.957681f, -9.76834f, 0.0766145f, -0.440533f, -9.414f, - -0.21069f, 0.708684f, -9.73004f, 0.0574608f, -0.593762f, - -9.27035f, -0.172383f, 0.756568f, -9.663f, 0.287304f, - 0.172383f, -9.10754f, -0.507571f, 0.718261f, -9.49062f, - 0.229843f, 0.0574608f, -9.50977f, -0.402226f, 0.162806f, - -10.1418f, -0.0670376f, -0.411803f, -9.32781f, -0.0383072f, - 0.804452f, -9.57681f, 0.229843f, -0.21069f, -9.57681f, - -0.296881f, 0.469264f, -9.54808f, 2.03986f, 0.641646f, - -10.0269f, -1.00556f, -0.45011f, -8.77236f, 0.402226f, - 0.718261f, -9.37569f, -0.047884f, -0.344765f, -9.98861f, - -1.48441f, 0.047884f, -9.33739f, 1.33118f, -0.23942f, - -9.30866f, -0.68953f, 0.220267f, -10.0556f, 0.708684f, - 0.201113f, -7.12514f, 6.70376f, 0.105345f, -6.81869f, - -6.33985f, 0.92895f, -8.70532f, 5.46836f, 0.220267f, - -8.41801f, -5.36301f, 0.0574608f, -9.84496f, 3.82115f, - 0.248997f, -9.9503f, -3.5913f, -0.229843f, -10.3238f, - 3.09331f, -0.0574608f, -9.71088f, -2.66235f, 0.6608f, - -8.68616f, 1.53229f, 0.641646f, -9.17458f, -1.22583f, - 0.507571f, -10.0078f, -1.09176f, -0.622492f, -10.0078f, - 1.3216f, -0.497994f, -9.46189f, -1.17795f, 0.0766145f, - -9.23204f, 1.01514f, 0.248997f, -9.38527f, -1.94409f, - 0.296881f, -9.21289f, 1.79086f, -0.21069f, -9.10754f, - -2.12605f, 0.440533f, -9.09797f, 1.82917f, 0.172383f, - -9.02135f, -1.54187f, 0.047884f, -9.35654f, 1.54187f, - 0.047884f, -8.99262f, -1.66636f, -0.0191536f, -9.29908f, - 1.49398f, 0.344765f, -9.663f, -1.65679f, -0.593762f, - -9.29908f, 1.58975f, 0.296881f, -9.69173f, -1.1971f, - -0.153229f, -9.5385f, 1.16837f, 0.114922f, -9.80665f, - -1.22583f, 0.268151f, -9.43316f, 1.08218f, -0.114922f, - -9.74919f, -1.27372f, 0.775721f, -9.38527f, 1.11091f, - -0.440533f, -9.49062f, -1.20668f, 0.574608f, -9.37569f, - 0.995988f, -0.536301f, -9.33739f, -1.06303f, 0.871489f, - -9.5385f, 0.948104f, -0.699107f, -9.44273f, -0.976834f, - 0.871489f, -9.72046f, 0.890643f, -0.746991f, -9.87369f, - -1.33118f, 0.488417f, -9.46189f, 1.13006f, 0.248997f, - -8.92558f, -1.0343f, -0.134075f, -9.07881f, 1.04387f, - 0.737414f, -8.82982f, -0.814029f, -1.46525f, -9.20331f, - 1.06303f, 0.105345f, -9.94073f, -0.957681f, -0.153229f, - -9.35654f, 0.948104f, -0.603339f, -9.31823f, 1.34075f, - 2.03028f, -8.82024f, -1.76213f, -0.861913f, -8.42759f, - -0.440533f, 4.67348f, -8.94474f, 0.201113f, -5.08528f, - -7.51779f, -0.948104f, 5.77481f, -8.15944f, 0.833182f, - -5.63116f, -9.69173f, -0.948104f, 2.36547f, -10.1801f, - 0.679953f, -2.2314f, -9.11712f, 1.72383f, 0.574608f, - -8.83939f, -2.03986f, -0.0287304f, -9.31823f, 1.92494f, - 0.804452f, -9.79707f, -2.03028f, -0.517148f, -8.3414f, - 2.68151f, 1.9824f, -8.24563f, -2.71024f, -2.1069f, - -9.15543f, 2.41336f, 2.28886f, -7.49864f, -3.03585f, - -3.66792f, -8.59997f, 2.00155f, 2.59531f, -9.07881f, - -2.11647f, -2.52828f, -9.64384f, 1.89621f, 2.11647f, - -9.36612f, -2.16436f, -1.83875f, -9.01178f, 1.69509f, - 2.19309f, -9.17458f, -1.94409f, -1.56102f, -9.27993f, - 1.49398f, 2.28886f, -9.51935f, -1.72383f, -2.2697f, - -9.10754f, 1.52271f, 2.43251f, -8.84897f, -2.02071f, - -2.02071f, -9.08839f, 1.51314f, 2.55701f, -9.11712f, - -1.8579f, -2.21224f, -9.09797f, 1.47483f, 2.52828f, - -9.13627f, -1.8579f, -2.09732f, -9.06924f, 1.46525f, - 2.43251f, -8.92558f, -1.90578f, -2.09732f, -9.19373f, - 1.50356f, 2.3942f, -9.21289f, -1.82917f, -2.26013f, - -8.5904f, 2.16436f, 2.33674f, -8.51378f, -2.36547f, - -1.83875f, -8.25521f, 3.62961f, 2.03028f, -7.91044f, - -3.74453f, -1.12049f, -8.61913f, 3.84988f, 1.62806f, - -8.83939f, -3.97437f, -1.26414f, -8.23605f, 4.52025f, - 2.13563f, -8.83939f, -4.35745f, -1.14922f, -7.4316f, - 6.02381f, 2.34632f, -7.33583f, -5.84185f, -1.79086f, - -6.63673f, 6.67503f, 2.37505f, -6.44519f, -6.359f, - -1.62806f, -6.06212f, 7.51779f, 2.38462f, -6.25365f, - -7.23049f, -1.80044f, -5.25767f, 8.64786f, 2.09732f, - -4.32872f, -8.68616f, -2.03986f, -4.39575f, 7.97748f, - 2.00155f, -3.77326f, -8.42759f, -0.775721f, -4.64475f, - 8.32224f, 1.61848f, -4.29999f, -8.60955f, -0.622492f, - -4.7501f, 8.5042f, 1.81959f, -4.79798f, -8.4659f, - -1.08218f, -4.64475f, 8.37013f, 1.92494f, -4.53941f, - -8.5904f, -1.13964f, -4.77883f, 8.73405f, 2.11647f, - -3.33273f, -9.414f, -1.37906f, -9.73004f, -0.92895f, - 0.603339f, -9.67257f, 0.852336f, -1.11091f, -9.87369f, - -0.047884f, 0.153229f, -9.98861f, 0.0670376f, -0.440533f, - -9.61511f, 0.651223f, 0.181959f, -9.5385f, -0.785298f, - 0.612916f, -9.50019f, 0.335188f, -0.23942f, -8.88728f, - -0.536301f, 0.00957681f, -9.95988f, 0.670376f, 0.134075f, - -9.29908f, -0.881066f, 0.0861913f, -9.67257f, 0.488417f, - 0.220267f, -9.62469f, -0.545878f, 0.306458f, -9.58638f, - 0.344765f, 0.306458f, -9.165f, -0.574608f, 0.0287304f, - -9.65342f, 0.143652f, 0.287304f, -10.0844f, -0.191536f, - 0.440533f, -9.40442f, 0.679953f, 0.21069f, -9.37569f, - -0.881066f, 0.402226f, -9.79707f, 1.34075f, 0.785298f, - -10.1801f, -1.13964f, -0.220267f, -9.14585f, 2.29843f, - 0.794875f, -9.36612f, -2.24097f, -0.316035f, -8.83939f, - 3.37104f, 0.727837f, -8.70532f, -3.25611f, 0.0766145f, - -8.24563f, 4.42448f, 0.814029f, -8.14029f, -4.27126f, - -0.392649f, -7.63272f, 5.38217f, 0.957681f, -7.05811f, - -5.5737f, -0.0383072f, -7.57525f, 5.93762f, 1.29287f, - -7.02938f, -6.02381f, -0.651223f, -7.46991f, 6.18662f, - 1.76213f, -7.35499f, -6.21535f, -1.37906f, -7.35499f, - 6.38773f, 1.47483f, -7.40287f, -6.27281f, -0.967257f, - -7.02938f, 6.79953f, 1.30245f, -6.95276f, -6.68461f, - -0.890643f, -6.42604f, 7.32626f, 1.09176f, -6.4835f, - -7.19218f, -0.354342f, -6.41646f, 7.57525f, 0.938527f, - -6.11958f, -7.50822f, -0.229843f, -5.88016f, 7.71891f, - 0.794875f, -5.17148f, -7.70933f, 0.105345f, -5.74608f, - 7.85298f, 0.727837f, -5.09486f, -7.72848f, 0.114922f, - -5.9472f, 7.83383f, 0.727837f, -5.91847f, -7.65187f, - -0.0287304f, -5.97593f, 7.77637f, 0.718261f, -6.01423f, - -7.63272f, 0.191536f, -5.95677f, 7.78594f, 0.526724f, - -5.73651f, -7.6806f, 0.507571f, -5.95677f, 7.89129f, - 0.459687f, -5.66947f, -7.74764f, 0.517148f, -5.93762f, - 7.85298f, 0.430956f, -5.81312f, -7.69018f, 0.459687f, - -5.9855f, 7.78594f, 0.469264f, -5.86101f, -7.65187f, - 0.517148f, -6.03339f, 7.82425f, 0.411803f, -5.75566f, - -7.67102f, 0.526724f, -6.00466f, 7.79552f, 0.402226f, - -5.68862f, -7.67102f, 0.42138f, -6.00466f, 7.79552f, - 0.497994f, -5.60243f, -7.69975f, 0.201113f, -6.13873f, - 7.65187f, 0.42138f, -5.3247f, -7.62314f, 0.172383f, - -6.608f, 7.40287f, 0.258574f, -5.77481f, -7.46991f, - 0.593762f, -7.18261f, 6.82826f, 0.134075f, -6.75165f, - -6.71334f, 0.526724f, -7.88171f, 5.79397f, -0.181959f, - -7.19218f, -5.70778f, 1.54187f, -8.4659f, 4.54898f, - -0.842759f, -7.90087f, -4.30956f, 1.95367f, -10.5728f, - 0.632069f, -1.96325f, -9.84496f, 0.153229f, 1.82917f, - -9.27993f, -0.0861913f, -0.92895f, -9.31823f, 0.047884f, - 1.46525f, -9.93115f, 0.325611f, -1.1971f, -10.2759f, - -0.114922f, 2.3942f, -9.59596f, -0.0766145f, -0.316035f, - -9.97903f, 0.363919f, -1.13964f, -9.04051f, 2.50912f, - 1.31202f, -8.67659f, -2.58574f, -0.603339f, -9.83538f, - 1.00556f, 1.40779f, -9.09797f, -0.92895f, -0.948104f, - -9.165f, 0.699107f, 1.24498f, -8.8777f, -0.517148f, - -0.699107f, -9.57681f, 0.507571f, 0.641646f, -9.65342f, - -0.229843f, -0.565032f, -9.55765f, 0.287304f, 0.47884f, - -8.91601f, -0.201113f, -0.833182f, -9.69173f, 0.134075f, - 0.411803f, -9.47146f, 0.162806f, 0.172383f, -9.5385f, - -0.21069f, 0.143652f, -9.30866f, 0.497994f, -0.105345f, - -9.8258f, 0.507571f, 0.507571f, -9.50977f, -0.248997f, - 0.383072f, -9.60554f, 0.641646f, 0.948104f, -9.27993f, - -0.220267f, -0.0766145f, -10.0844f, 0.430956f, 0.986411f, - -9.52892f, -0.00957681f, 0.517148f, -9.02135f, 0.411803f, - 1.43652f, -9.42358f, -0.00957681f, -0.258574f, -9.27035f, - 1.54187f, 0.45011f, -9.84496f, -0.995988f, 0.316035f, - -9.8258f, -0.402226f, 0.842759f, -8.93516f, 0.967257f, - -0.785298f, -8.94474f, 2.63362f, 0.545878f, -9.25119f, - -2.78685f, 0.0383072f, -7.71891f, 5.74608f, 0.909797f, - -9.34696f, -5.07571f, -0.651223f, -8.63828f, 4.58729f, - 0.430956f, -8.69574f, -4.29041f, -1.16837f, -7.39329f, - 7.83383f, 0.612916f, -7.62314f, -7.28795f, -0.229843f, - -6.17704f, 7.59441f, 1.89621f, -5.58328f, -7.56568f, - 0.153229f, -5.53539f, 8.00621f, 0.967257f, -4.83629f, - -7.9679f, 0.411803f, -4.95121f, 8.04452f, 0.248997f, - -4.46279f, -8.20732f, 0.201113f, -4.99909f, 8.42759f, - 0.105345f, -4.89375f, -8.30309f, -0.0287304f, -4.52983f, - 8.5042f, 0.306458f, -4.72137f, -8.5042f, 0.0f, - -4.36702f, 8.72447f, 0.0f, -4.43406f, -8.68616f, - 0.181959f, -4.15633f, 8.8777f, 0.430956f, -3.98395f, - -9.02135f, 0.584185f, -4.14676f, 8.68616f, 0.0670376f, - -3.9648f, -8.85855f, 1.09176f, -4.18506f, 8.84897f, - -0.114922f, -4.35745f, -8.77236f, 0.248997f, -4.22337f, - 8.07325f, 0.325611f, -3.67749f, -8.5042f, 1.37906f, - -9.15543f, 3.87861f, 2.11647f, -9.27993f, -2.25055f, - -1.5706f, -9.31823f, 0.0670376f, 1.47483f, -10.1897f, - -0.0766145f, -0.354342f, -9.24162f, -0.162806f, 0.0670376f, - -9.81623f, 0.325611f, -1.0343f, -5.88016f, 7.79552f, - 1.65679f, -8.16902f, -5.56412f, -2.83473f, -8.38928f, - 4.31914f, 1.39821f, -8.81066f, -4.41491f, -1.08218f, - -8.82982f, 4.46279f, 0.986411f, -8.61913f, -4.73094f, - -0.727837f, -8.06367f, 3.85945f, 1.38864f, -8.16902f, - -3.98395f, -0.766145f, -8.73405f, 3.92649f, 1.63763f, - -8.71489f, -4.10845f, -1.61848f, -8.91601f, 3.36146f, - 2.04944f, -9.08839f, -3.47638f, -1.97282f, -8.82024f, - 3.40934f, 2.29843f, -8.83939f, -3.66792f, -2.24097f, - -8.88728f, 3.553f, 2.17394f, -8.84897f, -3.78284f, - -2.21224f, -8.73405f, 4.01268f, 2.21224f, -8.74362f, - -4.22337f, -2.07817f, -8.63828f, 3.90734f, 2.20267f, - -8.97347f, -3.77326f, -1.87705f, -8.39886f, 4.48195f, - 2.08774f, -9.06924f, -4.30956f, -1.71425f, -7.44118f, - 6.41646f, 1.83875f, -7.72848f, -6.76123f, -1.05345f, - -6.08127f, 7.51779f, 1.35991f, -4.92248f, -7.63272f, - 0.0766145f, -6.33027f, 7.44118f, 1.49398f, -6.03339f, - -7.42203f, -0.430956f, -6.13873f, 7.53695f, 1.42694f, - -6.27281f, -7.45076f, -0.90022f, -6.17704f, 7.54652f, - 1.37906f, -6.14831f, -7.51779f, -0.42138f, -6.06212f, - 7.56568f, 1.47483f, -6.2345f, -7.46033f, -0.316035f, - -6.02381f, 7.67102f, 1.49398f, -6.22492f, -7.50822f, - -0.497994f, -5.67905f, 7.85298f, 1.71425f, -6.03339f, - -7.57525f, -1.05345f, -5.06613f, 8.05409f, 1.83875f, - -4.82671f, -7.97748f, -0.565032f, -4.54898f, 8.23605f, - 1.99198f, -4.42448f, -8.42759f, -1.06303f, -4.24253f, - 8.7532f, 2.17394f, -4.40533f, -8.81066f, -2.05901f, - -3.44765f, 9.10754f, 1.92494f, -3.01669f, -9.39485f, - -0.68953f, -3.055f, 8.68616f, 2.11647f, -3.4285f, - -8.73405f, -1.3216f, -2.72939f, 8.88728f, 2.11647f, - -2.61447f, -9.02135f, -1.21625f, -2.55701f, 9.38527f, - 2.30801f, -2.15478f, -9.663f, -2.33674f, -2.48039f, - 9.23204f, 2.2314f, -1.53229f, -9.71088f, -1.13964f, - -3.66792f, 8.72447f, 2.24097f, -2.29843f, -8.88728f, - -2.31759f, -8.54251f, 3.89776f, 1.75256f, -9.05966f, - -2.90177f, -2.06859f, -9.29908f, 2.04944f, 1.6089f, - -9.86411f, -1.71425f, -1.16837f, -10.2855f, 1.29287f, - 0.766145f, -10.1993f, -1.1971f, -0.373495f, -9.89284f, - 1.1971f, 0.995988f, -9.14585f, -1.48441f, -0.201113f, - -9.43316f, 0.306458f, 1.45567f, -9.19373f, -0.6608f, - -0.727837f, -9.15543f, -0.0287304f, 0.047884f, -9.40442f, - 0.0287304f, 0.392649f, -9.9503f, -0.948104f, 0.0287304f, - -10.1323f, 1.06303f, -0.47884f, -10.0078f, -0.45011f, - 0.23942f, -9.52892f, 0.287304f, -0.191536f, -9.45231f, - -0.545878f, 0.42138f, -9.52892f, 0.354342f, -0.584185f, - -9.86411f, -0.258574f, 0.699107f, -9.44273f, 0.0f, - -0.42138f, -8.4659f, 3.95522f, 0.354342f, -8.57124f, - -4.1276f, 0.430956f, -8.71489f, 4.04141f, 0.306458f, - -8.95431f, -3.9648f, -0.603339f, -8.89685f, 3.58173f, - 0.354342f, -8.52336f, -3.85945f, 0.258574f, -9.35654f, - 3.54342f, -0.785298f, -9.02135f, -3.69665f, 0.92895f, - -8.76278f, 2.84431f, -1.17795f, -8.56167f, -2.806f, - 2.07817f, -8.89685f, 3.13162f, -1.49398f, -8.5042f, - -3.16035f, 2.03028f, -9.09797f, 4.00311f, -0.995988f, - -9.71088f, -3.79242f, 2.70066f, -9.04051f, 3.58173f, - -1.01514f, -8.04452f, -3.64876f, 1.81002f, -7.86256f, - 4.94163f, -0.201113f, -7.46991f, -5.02782f, 1.81959f, - -7.41245f, 6.46434f, -0.47884f, -7.44118f, -6.31112f, - 0.976834f, -6.57927f, 6.68461f, -0.114922f, -6.36858f, - -6.40688f, 2.35589f, -6.02381f, 7.31668f, -0.469264f, - -5.43005f, -7.24007f, 2.43251f, -6.87615f, 7.48906f, - -0.536301f, -7.03895f, -7.15387f, 0.90022f, -5.9855f, - 7.72848f, -0.201113f, -5.78439f, -7.47949f, 1.13964f, - -6.06212f, 7.9296f, -0.268151f, -5.25767f, -7.76679f, - 1.63763f, -5.70778f, 8.29351f, -0.162806f, -4.72137f, - -8.14029f, 1.20668f, -5.29597f, 8.42759f, 0.143652f, - -4.75967f, -8.42759f, 0.603339f, -5.11401f, 8.44674f, - 0.565032f, -4.85544f, -8.43717f, -0.00957681f, -5.43963f, - 8.23605f, 0.919373f, -5.1619f, -8.05409f, -0.325611f, - -5.60243f, 8.0924f, 0.718261f, -5.48751f, -7.86256f, - -0.047884f, -5.84185f, 7.98706f, 1.11091f, -5.58328f, - -7.91044f, 0.162806f, -5.79397f, 7.8434f, 1.16837f, - -5.47793f, -7.69975f, -0.392649f, -5.78439f, 7.77637f, - 1.36948f, -5.63116f, -7.61356f, -0.651223f, -5.95677f, - 7.73806f, 1.55144f, -5.19063f, -7.69975f, -0.833182f, - -6.22492f, 7.5561f, 1.49398f, -5.46836f, -7.53695f, - -0.833182f, -6.87615f, 6.98149f, 1.25456f, -6.53138f, - -6.82826f, -0.871489f, -7.40287f, 6.03339f, 0.6608f, - -6.67503f, -5.9855f, 0.344765f, -8.00621f, 4.66391f, - 0.574608f, -7.71891f, -4.67348f, 0.641646f, -9.48104f, - 2.24097f, 1.0343f, -9.77792f, -2.03028f, -0.995988f, - -9.76834f, 1.30245f, 1.05345f, -9.72046f, -1.25456f, - -0.593762f, -9.47146f, 0.507571f, 1.1971f, -10.4675f, - -0.459687f, -0.804452f, -9.67257f, 0.201113f, 1.15879f, - -9.60554f, -0.383072f, -1.13006f, -9.42358f, -0.0191536f, - 1.08218f, -10.0844f, -0.0574608f, -0.823605f, -7.12514f, - 6.99107f, -0.488417f, -7.20176f, -6.6463f, 1.63763f, - -7.16345f, 6.86657f, -0.430956f, -7.46991f, -6.47392f, - 0.823605f, -7.09641f, 7.1443f, -0.804452f, -6.6463f, - -7.00065f, 1.76213f, -7.50822f, 6.62715f, -0.277727f, - -5.86101f, -7.06768f, 0.986411f, -7.2688f, 7.23049f, - -0.47884f, -7.28795f, -6.97192f, 1.51314f, -7.37414f, - 6.62715f, -0.287304f, -7.24964f, -6.39731f, 0.995988f, - -7.40287f, 6.56969f, -0.392649f, -7.11557f, -6.44519f, - 1.14922f, -7.3071f, 6.8953f, -0.584185f, -6.56011f, - -6.91445f, 1.78129f, -7.51779f, 6.78038f, -0.612916f, - -5.74608f, -7.02938f, 3.48596f, -7.24007f, 6.33985f, - -0.325611f, -6.8953f, -6.03339f, 0.536301f, -8.99262f, - 5.01825f, -0.258574f, -9.73961f, -4.56814f, 0.632069f, - -9.79707f, 1.66636f, 0.287304f, -9.21289f, -1.87705f, - -0.105345f, -9.77792f, 1.10133f, 0.995988f, -8.88728f, - -1.47483f, -0.335188f, -9.44273f, 1.24498f, 0.497994f, - -9.44273f, -1.34075f, -0.268151f, -9.7875f, 1.0726f, - 0.68953f, -9.39485f, -1.27372f, -0.162806f, -8.86812f, - 2.24097f, 0.545878f, -8.61913f, -2.47082f, 0.632069f, - -9.0022f, 2.02071f, 0.718261f, -9.36612f, -2.12605f, - -0.440533f, -9.22246f, 2.29843f, 1.05345f, -9.10754f, - -2.46124f, -0.402226f, -9.55765f, 2.32716f, 0.842759f, - -9.19373f, -2.50912f, -0.497994f, -8.95431f, 2.62405f, - 1.0726f, -9.15543f, -2.73897f, -0.737414f, -9.54808f, - 2.34632f, 1.11091f, -9.05966f, -2.55701f, -0.440533f, - -10.0556f, -0.746991f, 1.15879f, -8.90643f, 1.48441f, - -1.74298f, -8.53294f, -2.1452f, 2.67193f, -9.15543f, - 2.84431f, -1.62806f, -8.94474f, 1.81959f, 0.42138f, - -9.30866f, -1.75256f, -0.746991f, -9.92157f, 2.12605f, - 0.670376f, -9.35654f, -2.24097f, -0.699107f, -9.49062f, - 2.12605f, 1.25456f, -8.91601f, -2.36547f, -0.411803f, - -8.86812f, 2.40378f, 0.948104f, -8.95431f, -2.47082f, - -0.871489f, -8.90643f, 2.65278f, 1.49398f, -8.95431f, - -2.88262f, -1.18752f, -8.95431f, 3.15077f, 1.25456f, - -9.05966f, -3.34231f, -1.10133f, -9.02135f, 2.9305f, - 1.25456f, -9.03093f, -3.26569f, -1.0726f, -9.32781f, - 2.87304f, 1.0726f, -8.97347f, -3.26569f, -0.794875f, - -9.1267f, 2.94966f, 1.10133f, -9.06924f, -3.20823f, - -0.679953f, -9.06924f, 3.01669f, 1.01514f, -8.98304f, - -3.21781f, -0.507571f, -9.165f, 3.18908f, 0.555455f, - -9.03093f, -3.49553f, -0.354342f, -9.04051f, 3.32315f, - 0.344765f, -9.05966f, -3.48596f, -0.181959f, -8.76278f, - 3.02627f, 0.708684f, -8.90643f, -3.23696f, -0.248997f, - -8.85855f, 2.79643f, 0.641646f, -8.90643f, -2.96881f, - -0.306458f, -8.92558f, 2.7677f, 0.833182f, -8.91601f, - -3.02627f, -0.430956f, -8.94474f, 2.86347f, 1.00556f, - -8.86812f, -3.16035f, -0.565032f, -8.98304f, 2.94966f, - 1.1971f, -9.07881f, -3.20823f, -0.766145f, -8.89685f, - 2.92093f, 1.12049f, -8.89685f, -3.09331f, -0.842759f, - -8.83939f, 2.97839f, 0.967257f, -8.85855f, -3.1795f, - -0.919373f, -8.93516f, 3.15077f, 1.42694f, -8.90643f, - -3.43807f, -0.948104f, -8.99262f, 3.20823f, 1.33118f, - -8.92558f, -3.43807f, -1.0726f, -8.86812f, 3.01669f, - 1.52271f, -8.77236f, -3.33273f, -1.08218f, -8.81066f, - 3.23696f, 1.50356f, -8.82024f, -3.4668f, -1.13964f, - -8.86812f, 3.41892f, 1.40779f, -8.90643f, -3.62961f, - -1.06303f, -8.82982f, 3.38061f, 1.55144f, -8.79151f, - -3.62003f, -1.08218f, -8.82024f, 3.12204f, 1.67594f, - -8.82024f, -3.41892f, -1.15879f, -8.73405f, 3.25611f, - 1.75256f, -8.72447f, -3.4285f, -1.28329f, -8.79151f, - 3.32315f, 1.96325f, -8.78193f, -3.5913f, -1.55144f, - -8.71489f, 3.27527f, 2.02071f, -8.73405f, -3.48596f, - -1.67594f, -8.82024f, 3.16035f, 2.02071f, -8.7532f, - -3.41892f, -1.62806f, -8.73405f, 3.40934f, 1.90578f, - -8.74362f, -3.62003f, -1.38864f, -8.74362f, 3.41892f, - 1.93451f, -8.68616f, -3.66792f, -1.45567f, -8.70532f, - 3.40934f, 1.99198f, -8.68616f, -3.62961f, -1.78129f, - -8.69574f, 3.56257f, 1.93451f, -8.72447f, -3.77326f, - -1.45567f, -8.79151f, 3.45723f, 2.13563f, -8.74362f, - -3.68707f, -1.54187f, -8.79151f, 3.25611f, 2.03986f, - -8.65743f, -3.62003f, -1.6089f, -8.80109f, 3.32315f, - 1.92494f, -8.69574f, -3.5913f, -1.88663f, -8.99262f, - 3.13162f, 1.91536f, -8.63828f, -3.50511f, -1.42694f, - -8.69574f, 3.19865f, 2.22182f, -8.86812f, -3.43807f, - -1.80044f, -8.89685f, 2.61447f, 2.05901f, -8.7532f, - -2.85389f, -1.39821f, -9.32781f, 2.38462f, 2.08774f, - -8.85855f, -2.67193f, -1.5706f, -9.72046f, 1.13006f, - 1.86748f, -9.03093f, -0.756568f, -1.0343f, -10.3334f, - 0.42138f, -1.53229f, -9.57681f, -0.220267f, 1.26414f, - -8.95431f, -0.383072f, 0.201113f, -9.73961f, 0.651223f, - -0.565032f, -10.3334f, -0.651223f, -0.0574608f, -9.68215f, - 0.536301f, 1.02472f, -9.56723f, -0.823605f, -0.296881f, - -9.58638f, 0.890643f, 0.0287304f, -9.50977f, -0.957681f, - -0.0957681f, -9.54808f, 0.890643f, 0.0861913f, -9.72046f, - -1.04387f, -0.248997f, -9.35654f, 1.00556f, 0.335188f, - -9.47146f, -0.948104f, -0.325611f, -9.45231f, 0.90022f, - 0.0383072f, -9.70131f, -0.814029f, -0.191536f, -9.51935f, - 0.756568f, 0.335188f, -9.69173f, -0.861913f, -0.0383072f, - -9.58638f, 0.775721f, 0.306458f, -9.73004f, -0.986411f, - 0.00957681f, -9.47146f, 0.833182f, 0.258574f, -9.64384f, - -0.766145f, -0.287304f, -9.5385f, 0.699107f, 0.335188f, - -9.60554f, -0.842759f, -0.153229f, -9.5385f, 0.785298f, - 0.402226f, -9.73961f, -0.890643f, -0.191536f, -9.43316f, - 0.785298f, 0.411803f, -9.663f, -0.737414f, -0.392649f, - -9.56723f, 0.775721f, 0.335188f, -9.60554f, -0.766145f, - -0.287304f, -9.49062f, 0.679953f, 0.344765f, -9.67257f, - -0.785298f, -0.201113f, -9.44273f, 0.699107f, 0.316035f, - -9.62469f, -0.737414f, -0.220267f, -9.54808f, 0.679953f, - 0.440533f, -9.96946f, -0.497994f, -0.392649f, -9.61511f, - 0.440533f, 0.363919f, -9.46189f, -0.383072f, -0.383072f, - -9.48104f, 0.306458f, 0.565032f, -9.69173f, -1.0726f, - -0.766145f, -9.05008f, 0.909797f, 0.775721f, -9.63427f, - -0.430956f, -0.737414f, -9.54808f, 0.344765f, 0.718261f, - -9.58638f, -0.383072f, -0.229843f, -9.5385f, 0.172383f, - 0.632069f, -9.62469f, -0.335188f, -0.545878f, -9.52892f, - 0.306458f, 0.622492f, -9.48104f, -0.383072f, -0.392649f, - -9.44273f, 0.23942f, 0.68953f, -9.70131f, -0.344765f, - -0.354342f, -9.59596f, 0.229843f, 0.565032f, -9.40442f, - -0.392649f, -0.497994f, -9.43316f, 0.248997f, 0.555455f, - -9.34696f, -0.373495f, -0.220267f, -9.34696f, 0.181959f, - 0.392649f, -10.4579f, 0.0670376f, 0.181959f, -9.5385f, - -0.229843f, 0.296881f, -9.29908f, -0.0287304f, -0.42138f, - -9.45231f, 0.00957681f, 0.565032f, -9.84496f, -0.0766145f, - 0.105345f, -9.64384f, -0.0574608f, 0.277727f, -9.67257f, - -0.21069f, -0.306458f, -9.29908f, 0.047884f, 0.469264f, - -9.64384f, -0.248997f, 0.114922f, -9.52892f, 0.0191536f, - 0.201113f, -9.64384f, -0.411803f, -0.0861913f, -9.67257f, - 0.248997f, 0.0670376f, -9.73004f, -0.383072f, -0.00957681f, - -9.59596f, 0.268151f, -0.047884f, -9.77792f, -0.162806f, - 0.0766145f, -9.68215f, 0.00957681f, 0.153229f, -9.68215f, - -0.0957681f, 0.143652f, -9.50977f, -0.0957681f, 0.23942f, - -9.60554f, -0.316035f, 0.0f, -9.43316f, 0.124498f, - 0.134075f, -9.52892f, -0.47884f, -0.134075f, -9.50019f, - 0.316035f, -0.00957681f, -9.88326f, -0.23942f, -0.0670376f, - -9.5385f, 0.0861913f, 0.316035f, -9.60554f, -0.0766145f, - 0.220267f, -9.62469f, -0.00957681f, -0.172383f, -9.74919f, - -0.00957681f, 0.0766145f, -9.43316f, -0.105345f, 0.0957681f, - -9.69173f, -0.0670376f, 0.00957681f, -9.51935f, -0.0383072f, - -0.0383072f, -9.71088f, 0.0191536f, 0.0766145f, -9.50977f, - -0.0957681f, 0.0766145f, -9.56723f, -0.105345f, 0.0861913f, - -9.2895f, -0.114922f, 0.153229f, -9.71088f, -0.162806f, - 0.0861913f, -9.50019f, 0.0287304f, 0.0861913f, -9.64384f, - -0.0191536f, 0.287304f, -9.50977f, -0.134075f, -0.0383072f, - -9.50019f, 0.143652f, 0.21069f, -9.44273f, -0.23942f, - -0.344765f, -9.64384f, -0.0287304f, 0.172383f, -9.48104f, - -0.0574608f, -0.0957681f, -9.69173f, -0.181959f, 0.201113f, - -9.48104f, 0.114922f, -0.0574608f, -9.75877f, -0.0670376f, - 0.0191536f, -9.55765f, 0.0383072f, 0.172383f, -9.61511f, - -0.0574608f, 0.268151f, -9.24162f, -0.0957681f, -0.0574608f, - -9.56723f, 0.047884f, 0.325611f, -9.51935f, -0.134075f, - -0.459687f, -9.47146f, 0.0f, 0.622492f, -9.49062f, - -0.0670376f, -0.488417f, -9.59596f, 0.0f, 0.823605f, - -9.48104f, -0.0383072f, -0.574608f, -9.5385f, -0.335188f, - 0.641646f, -9.54808f, 0.296881f, -0.536301f, -9.48104f, - -0.363919f, 0.641646f, -9.50977f, 0.287304f, -0.45011f, - -9.46189f, -0.047884f, 1.13964f, -9.57681f, 0.0f, - -0.632069f, -9.57681f, -0.316035f, 0.909797f, -9.63427f, - 0.258574f, -0.517148f, -9.64384f, -0.344765f, 0.545878f, - -9.59596f, 0.296881f, -0.440533f, -9.54808f, -0.0574608f, - 0.746991f, -9.59596f, -0.0383072f, -0.296881f, -9.49062f, - 0.00957681f, 0.852336f, -9.46189f, -0.124498f, -0.21069f, - -9.57681f, 0.0766145f, 0.641646f, -9.37569f, -0.181959f, - -0.42138f, -9.70131f, 0.344765f, 0.737414f, -9.24162f, - -0.469264f, -0.794875f, -9.47146f, 0.0f, 0.699107f, - -9.76834f, 0.0287304f, -0.746991f, -9.48104f, -0.153229f, - 1.33118f, -9.36612f, 0.0957681f, -0.948104f, -9.74919f, - -0.201113f, 1.10133f, -9.35654f, 0.181959f, -0.909797f, - -9.54808f, 0.0957681f, 0.881066f, -9.73961f, 0.153229f, - -1.05345f, -9.49062f, -0.306458f, 1.04387f, -9.51935f, - 0.584185f, -0.766145f, -9.93115f, -0.814029f, 0.727837f, - -9.75877f, 1.0726f, -0.316035f, -9.72046f, -0.296881f, - 0.162806f, -9.47146f, 0.392649f, 0.0766145f, -9.40442f, - 0.21069f, 0.287304f, -9.37569f, -0.248997f, 0.536301f, - -9.5385f, 0.0861913f, 0.114922f, -9.40442f, -0.0287304f, - -0.0383072f, -10.0461f, 0.181959f, -0.00957681f, -9.32781f, - -0.181959f, 0.622492f, -9.46189f, 0.296881f, -0.201113f, - -9.35654f, -0.201113f, 0.201113f, -9.31823f, -0.402226f, - 0.21069f, -9.91199f, 0.517148f, 1.01514f, -9.87369f, - 0.047884f, -0.047884f, -9.56723f, 0.248997f, -0.114922f, - -9.76834f, -0.335188f, 0.0383072f, -9.02135f, 0.316035f, - 0.105345f, -9.5385f, -0.335188f, 0.0287304f, -9.59596f, - 0.344765f, 0.670376f, -9.70131f, 0.0287304f, -0.383072f, - -10.4579f, 0.402226f, 0.411803f, -10.4291f, -0.45011f, - 0.306458f, -9.44273f, 0.545878f, 0.430956f, -9.79707f, - 0.507571f, -0.679953f, -9.26077f, -0.469264f, 1.26414f, - -9.51935f, 0.775721f, -0.114922f, -9.19373f, -0.718261f, - 0.718261f, -9.68215f, 0.881066f, -0.316035f, -9.01178f, - -0.890643f, 0.938527f, -9.25119f, 1.04387f, -0.861913f, - -8.76278f, -0.881066f, -0.823605f, -9.71088f, 0.354342f, - -0.181959f, -9.32781f, -0.248997f, -0.0957681f, -10.4387f, - 0.995988f, -0.268151f, -10.2376f, -0.699107f, 0.536301f, - -9.98861f, 0.555455f, -0.0574608f, -9.49062f, -0.459687f, - 0.823605f, -9.79707f, 0.316035f, 0.268151f, -8.85855f, - -0.488417f, -0.574608f, -9.663f, 0.373495f, -0.287304f, - -9.42358f, 0.0191536f, -1.65679f, -9.42358f, 1.0726f, - 1.80044f, -9.63427f, -0.21069f, -1.66636f, -9.31823f, - 0.306458f, 2.83473f, -9.17458f, 0.814029f, -2.98796f, - -8.67659f, 0.143652f, 1.7334f, -9.31823f, 1.23541f, - -1.15879f, -9.13627f, -1.75256f, 0.785298f, -8.80109f, - 2.54743f, -0.0766145f, -9.91199f, -0.134075f, 1.21625f, - -9.72046f, 0.488417f, 0.363919f, -9.14585f, -0.277727f, - 1.0343f, -9.21289f, 0.718261f, -0.143652f, -9.48104f, - -0.296881f, -0.114922f, -9.2895f, 0.565032f, 0.565032f, - -10.2663f, 0.459687f, -0.143652f, -9.56723f, -0.105345f, - 0.459687f, -10.094f, 0.68953f, -0.306458f, -9.59596f, - -0.172383f, 0.957681f, -10.094f, 0.0861913f, -0.220267f, - -9.34696f, 0.191536f, 0.392649f, -9.79707f, -0.181959f, - -0.488417f, -9.55765f, 0.555455f, 1.0343f, -10.1227f, - 0.0191536f, -0.976834f, -9.40442f, 0.354342f, 0.871489f, - -9.69173f, 0.593762f, -0.296881f, -9.14585f, -0.517148f, - 1.31202f, -9.69173f, 0.861913f, -0.775721f, -9.07881f, - -0.68953f, 0.497994f, -9.90242f, 0.919373f, 0.00957681f, - -9.43316f, -0.68953f, 0.325611f, -9.79707f, 0.507571f, - 0.114922f, -9.40442f, -0.316035f, 0.430956f, -9.8258f, - 0.536301f, -0.0191536f, -9.32781f, -0.258574f, 0.258574f, - -9.93115f, 0.383072f, 0.143652f, -9.48104f, -0.181959f, - 0.6608f, -9.55765f, 0.0861913f, -0.0383072f, -9.37569f, - 0.0287304f, 0.430956f, -9.39485f, 0.325611f, 0.0287304f, - -9.32781f, -0.0861913f, 0.392649f, -9.50019f, 0.651223f, - 0.23942f, -9.40442f, -0.469264f, 0.545878f, -9.75877f, - 0.536301f, 0.0574608f, -9.38527f, -0.411803f, 0.47884f, - -9.87369f, 0.574608f, 0.0383072f, -9.54808f, -0.402226f, - 0.258574f, -9.65342f, 0.325611f, 0.23942f, -9.56723f, - -0.220267f, 0.6608f, -9.50977f, 0.134075f, 0.0766145f, - -9.38527f, -0.047884f, 0.536301f, -9.70131f, 0.0f, - -0.42138f, -9.35654f, 0.181959f, 0.881066f, -9.71088f, - 0.181959f, -0.402226f, -9.50019f, -0.00957681f, 0.727837f, - -9.49062f, 0.306458f, -0.0766145f, -9.27993f, -0.268151f, - 0.766145f, -9.73961f, 0.181959f, -0.517148f, -9.49062f, - -0.0287304f, 0.986411f, -9.86411f, 0.0383072f, -0.383072f, - -9.47146f, 0.0383072f, 0.986411f, -9.50977f, 0.402226f, - -0.383072f, -9.10754f, -0.363919f, 0.823605f, -10.0365f, - 0.90022f, -0.497994f, -9.59596f, -0.651223f, 0.833182f, - -9.73961f, 0.517148f, -0.0957681f, -9.31823f, -0.440533f, - 0.641646f, -9.56723f, 0.0191536f, -0.114922f, -9.33739f, - -0.047884f, 0.593762f, -9.67257f, -0.23942f, -0.459687f, - -9.51935f, 0.258574f, 0.794875f, -9.39485f, 0.0574608f, - -0.172383f, -9.29908f, -0.0574608f, 0.440533f, -10.0078f, - 0.134075f, -0.536301f, -9.45231f, -0.0670376f, 0.766145f, - -10.0748f, -0.0287304f, -0.584185f, -9.55765f, -0.0766145f, - 1.06303f, -9.73961f, 0.392649f, -0.402226f, -9.50019f, - -0.316035f, 1.35991f, -9.75877f, 0.229843f, -0.373495f, - -9.51935f, -0.248997f, 1.39821f, -10.2855f, 0.191536f, - -0.181959f, -10.1514f, -0.124498f, 1.23541f, -10.0461f, - 0.105345f, -0.440533f, -9.88326f, 0.0574608f, -0.0191536f, - -9.60554f, -0.201113f, 0.0957681f, -9.33739f, 0.047884f, - -0.248997f, -9.29908f, -0.23942f, 0.373495f, -9.04051f, - -0.0861913f, -0.00957681f, -9.24162f, -0.114922f, 1.78129f, - -9.414f, -0.124498f, -1.16837f, -9.68215f, -0.181959f, - 1.35033f, -9.60554f, 0.0191536f, -1.4461f, -9.19373f, - -0.220267f, 1.84832f, -9.23204f, -0.00957681f, -1.70467f, - -9.11712f, -0.181959f, 1.50356f, -8.74362f, -0.143652f, - -1.97282f, -8.89685f, 0.143652f, 1.88663f, -8.90643f, - -0.373495f, -1.25456f, -8.81066f, -0.124498f, 1.31202f, - -8.79151f, -0.134075f, -0.92895f, -8.99262f, -0.536301f, - 0.430956f, -9.31823f, 0.373495f, -0.181959f, -10.2855f, - -0.153229f, 0.708684f, -10.5536f, 0.229843f, -0.105345f, - -10.2855f, -0.220267f, -0.105345f, -9.95988f, 0.296881f, - -0.162806f, -9.79707f, -0.0861913f, 0.536301f, -9.39485f, - -0.124498f, -0.392649f, -10.2759f, 0.047884f, 1.09176f, - -9.61511f, -0.191536f, -0.517148f, -10.0461f, 0.229843f, - 1.5706f, -9.56723f, -0.430956f, -0.584185f, -9.5385f, - 0.287304f, 0.938527f, -9.49062f, -0.47884f, -0.287304f, - -9.56723f, -0.248997f, 0.497994f, -9.50977f, 0.0766145f, - -0.957681f, -9.79707f, -0.191536f, 0.296881f, -9.40442f, - 0.00957681f, -0.0383072f, -9.61511f, 0.0191536f, 0.268151f, - -9.31823f, -0.201113f, -0.344765f, -9.48104f, 0.45011f, - 0.555455f, -9.29908f, -0.746991f, 0.0191536f, -9.03093f, - 0.248997f, 0.612916f, -8.97347f, -0.459687f, 0.459687f, - -9.11712f, -0.277727f, -0.402226f, -9.0022f, 0.191536f, - 0.191536f, -10.6207f, -0.0766145f, 0.641646f, -10.1897f, - -0.00957681f, 0.344765f, -10.0844f, 0.0574608f, 0.201113f, - -10.1131f, -0.124498f, 0.191536f, -9.38527f, -0.153229f, - -0.0191536f, -9.43316f, -0.0574608f, -0.134075f, -9.42358f, - -0.47884f, 0.172383f, -9.27035f, 0.143652f, 0.21069f, - -10.343f, -0.0383072f, -0.373495f, -9.8258f, 0.0861913f, - 0.316035f, -10.1706f, -0.181959f, -0.143652f, -9.74919f, - 0.114922f, 0.258574f, -9.50977f, -0.430956f, 0.0670376f, - -9.29908f, 0.172383f, 0.344765f, -9.86411f, -0.68953f, - 0.0191536f, -10.0748f, 0.737414f, 0.440533f, -9.91199f, - -0.622492f, -0.430956f, -9.86411f, 0.708684f, 0.335188f, - -9.88326f, -0.392649f, 0.153229f, -9.77792f, 0.354342f, - -0.191536f, -9.60554f, 0.0670376f, 0.0670376f, -9.31823f, - -0.277727f, -0.0957681f, -9.55765f, 0.593762f, 0.153229f, - -9.23204f, -0.852336f, -0.201113f, -9.63427f, 0.42138f, - 0.507571f, -9.42358f, -0.603339f, -0.641646f, -9.64384f, - 0.42138f, 0.718261f, -9.47146f, -0.507571f, -0.995988f, - -9.83538f, 0.134075f, 0.603339f, -9.32781f, -0.172383f, - -0.861913f, -9.60554f, 0.181959f, 1.05345f, -9.72046f, - -0.0574608f, -1.21625f, -9.57681f, -0.00957681f, 1.1971f, - -9.69173f, 0.363919f, -1.31202f, -9.29908f, -0.306458f, - 1.37906f, -9.33739f, 0.766145f, -1.41737f, -9.05008f, - -0.0574608f, 1.09176f, -9.07881f, 0.727837f, -0.861913f, - -9.42358f, -0.785298f, 0.632069f, -9.48104f, 1.01514f, - 0.047884f, -9.69173f, -1.04387f, -0.124498f, -8.99262f, - 1.11091f, 0.325611f, -9.70131f, -0.363919f, -0.325611f, - -9.50019f, 0.737414f, 1.31202f, -9.76834f, -0.162806f, - -1.10133f, -9.68215f, 0.296881f, 1.04387f, -9.77792f, - 0.603339f, -0.0957681f, -9.83538f, -0.47884f, 0.909797f, - -10.4387f, 0.0766145f, -0.459687f, -9.9503f, 0.047884f, - 1.38864f, -9.60554f, -0.584185f, 0.459687f, -9.75877f, - 0.536301f, -0.124498f, -9.74919f, -0.172383f, 0.651223f, - -10.4483f, 0.229843f, -0.268151f, -9.50019f, -1.58975f, - 0.622492f, -9.64384f, 1.58975f, -0.114922f, -8.96389f, - -1.69509f, 1.16837f, -8.72447f, 1.71425f, -1.04387f, - -8.91601f, -0.90022f, 1.92494f, -8.84897f, 1.04387f, - -0.833182f, -8.86812f, -0.0574608f, 1.17795f, -8.91601f, - 0.47884f, -1.47483f, -9.22246f, 1.25456f, 1.76213f, - -8.88728f, -1.42694f, -2.36547f, -10.1227f, 2.24097f, - 2.09732f, -9.09797f, -2.35589f, -3.11246f, -9.84496f, - 2.75812f, 2.1069f, -9.26077f, -2.98796f, -2.33674f, - -9.01178f, 0.0766145f, 4.2138f, -8.45632f, 1.02472f, - -3.69665f, -8.51378f, -0.344765f, 3.95522f, -8.90643f, - 2.00155f, -3.78284f, -9.05966f, -0.497994f, 3.50511f, - -9.42358f, 1.86748f, -3.62003f, -9.68215f, -0.488417f, - 3.74453f, -9.48104f, 1.69509f, -3.18908f, -9.93115f, - -0.871489f, 3.54342f, -9.68215f, 2.03986f, -2.8922f, - -9.85453f, -0.861913f, 3.16035f, -9.81623f, 2.08774f, - -2.66235f, -9.95988f, -0.852336f, 2.74854f, -9.59596f, - 1.83875f, -2.15478f, -10.0652f, -0.622492f, 2.28886f, - -9.5385f, 1.46525f, -2.18351f, -9.67257f, -0.632069f, - 2.01113f, -9.43316f, 1.3216f, -1.67594f, -9.42358f, - -0.679953f, 1.05345f, -9.45231f, 1.5706f, -1.23541f, - -9.2895f, -0.459687f, 1.39821f, -9.5385f, 1.46525f, - -1.16837f, -9.58638f, -0.316035f, 1.47483f, -9.54808f, - 1.20668f, -1.26414f, -9.60554f, -0.411803f, 1.39821f, - -9.31823f, 1.14922f, -1.14922f, -9.76834f, -0.354342f, - 1.35991f, -9.52892f, 1.11091f, -1.35991f, -9.81623f, - 0.0574608f, 1.46525f, -9.663f, 0.833182f, -1.1971f, - -9.80665f, 0.21069f, 1.62806f, -9.70131f, 0.641646f, - -1.24498f, -9.9503f, 0.497994f, 1.53229f, -9.88326f, - 0.325611f, -1.05345f, -9.86411f, 0.565032f, 1.58017f, - -9.87369f, 0.220267f, -1.24498f, -9.94073f, 0.268151f, - 1.97282f, -9.91199f, 0.584185f, -1.35033f, -9.25119f, - 0.306458f, 1.13006f, -9.46189f, 0.383072f, -1.11091f, - -8.97347f, -0.0670376f, 1.22583f, -8.98304f, 0.459687f, - -0.488417f, -9.30866f, -0.737414f, 1.23541f, -9.13627f, - 1.00556f, -0.526724f, -10.6781f, -0.775721f, 0.373495f, - -10.5919f, 1.13964f, 0.42138f, -9.54808f, -2.07817f, - 0.68953f, -9.26077f, 1.82917f, -0.105345f, -9.03093f, - -0.976834f, 0.430956f, -9.47146f, 0.995988f, -0.181959f, - -9.86411f, -0.23942f, 0.124498f, -9.73004f, 0.153229f, - 0.871489f, -9.97903f, -0.220267f, 0.162806f, -9.59596f, - 0.153229f, 0.430956f, -9.8258f, -0.114922f, 0.0957681f, - -9.76834f, 0.00957681f, -0.0287304f, -10.1801f, -0.268151f, - 0.258574f, -10.0844f, 0.23942f, 0.0766145f, -10.1131f, - 0.794875f, 0.0f, -9.86411f, -0.593762f, 0.909797f, - -9.29908f, -2.09732f, 1.72383f, -9.17458f, 1.89621f, - -1.58975f, -8.91601f, -2.16436f, 1.94409f, -9.1267f, - 2.03986f, -1.96325f, -9.30866f, -2.42293f, 2.02071f, - -9.43316f, 2.26013f, -1.38864f, -9.8258f, -2.2697f, - 1.16837f, -9.44273f, 2.16436f, -1.09176f, -9.14585f, - -2.03986f, 1.26414f, -9.01178f, 1.82917f, -1.28329f, - -8.89685f, -2.09732f, 1.64721f, -8.95431f, 1.93451f, - -1.69509f, -8.8777f, -2.19309f, 1.28329f, -9.03093f, - 2.11647f, -1.40779f, -9.31823f, -2.2697f, 1.09176f, - -9.11712f, 2.06859f, -1.3216f, -9.2895f, -2.21224f, - 1.4461f, -9.165f, 2.00155f, -1.48441f, -8.98304f, - -2.20267f, 1.46525f, -8.83939f, 2.00155f, -1.24498f, - -9.14585f, -2.26013f, 1.43652f, -9.01178f, 2.1069f, - -1.45567f, -9.1267f, -2.29843f, 1.63763f, -9.04051f, - 2.12605f, -1.76213f, -9.18416f, -2.27928f, 1.9824f, - -9.09797f, 2.07817f, -1.79086f, -9.08839f, -2.00155f, - 1.79086f, -9.44273f, 1.87705f, -1.62806f, -9.14585f, - -2.31759f, 1.84832f, -8.86812f, 2.06859f, 1.61848f, - -9.165f, -2.24097f, 2.05901f, -9.0022f, 2.02071f, - -1.7334f, -9.04051f, -2.1452f, 2.04944f, -9.2895f, - 2.06859f, -1.70467f, -9.20331f, -2.22182f, 2.06859f, - -9.33739f, 2.09732f, -1.76213f, -9.34696f, -2.13563f, - 1.99198f, -9.1267f, 1.9824f, -1.84832f, -8.88728f, - -1.79086f, 1.55144f, -9.03093f, 1.62806f, -1.61848f, - -9.1267f, -1.58975f, 1.47483f, -9.19373f, 1.49398f, - -1.47483f, -8.92558f, -1.48441f, 1.76213f, -8.69574f, - 1.18752f, -1.76213f, -9.24162f, -1.35991f, 1.49398f, - -9.48104f, 1.23541f, -1.61848f, -9.51935f, 1.86748f, - 2.00155f, -8.71489f, -1.24498f, -2.11647f, -5.6982f, - 8.15944f, 1.27372f, -4.52983f, -7.99663f, -0.775721f, - -4.00311f, 8.31267f, 0.632069f, -3.68707f, -8.03494f, - 0.344765f, -2.16436f, 7.79552f, 3.7158f, -1.7334f, - -7.74764f, -4.22337f, -1.56102f, 8.78193f, 4.39575f, - -1.58017f, -8.76278f, -4.5011f, -1.72383f, 9.05008f, - 5.25767f, -1.93451f, -9.11712f, -3.9648f, -0.995988f, - 7.97748f, 5.34386f, -1.33118f, -7.92002f, -4.03184f, - -0.670376f, 9.17458f, 4.3766f, 0.220267f, -9.60554f, - -4.13718f, -0.746991f, 7.33583f, 5.34386f, -1.1971f, - -7.28795f, -5.14275f, 0.871489f, 7.90087f, 5.80354f, - 0.584185f, -8.33182f, -3.04542f, 0.986411f, 7.59441f, - 6.49307f, -0.0670376f, -7.85298f, -5.92804f, 2.07817f, - 8.83939f, 5.4109f, 0.325611f, -9.59596f, -3.83072f, - 0.718261f, 7.38372f, 5.99508f, 0.248997f, -8.29351f, - -5.10444f, 1.72383f, 7.83383f, 5.85143f, 2.12605f, - -9.15543f, -4.03184f, 2.05901f, 7.37414f, 5.79397f, - 2.19309f, -8.49463f, -4.95121f, 2.13563f, 7.91044f, - 4.29999f, 2.1452f, -8.76278f, -2.24097f, 1.31202f, - 8.59997f, 5.72693f, 0.746991f, -9.55765f, -3.54342f, - 1.36948f, 8.5042f, 5.09486f, 1.17795f, -9.62469f, - -4.1276f, 1.77171f, 8.69574f, 5.46836f, 1.63763f, - -9.40442f, -2.32716f, 1.91536f, 7.75721f, 5.25767f, - 2.04944f, -8.81066f, -2.40378f, 0.392649f, 7.73806f, - 5.63116f, 1.45567f, -9.24162f, -1.49398f, -0.258574f, - 6.82826f, 7.34541f, -0.42138f, -9.07881f, -1.30245f, - -0.517148f, 6.97192f, 7.6806f, -0.890643f, -9.58638f, - -4.81713f, -0.21069f, 3.13162f, 9.20331f, -0.967257f, - -10.0748f, 0.181959f, -0.948104f, -5.9855f, 7.4316f, - -1.00556f, -9.5385f, 0.497994f, 0.162806f, -8.47547f, - 4.32872f, 0.248997f, -9.165f, -2.27928f, 0.143652f, - -8.6287f, 4.47237f, 0.354342f, -9.51935f, 0.986411f, + -0.0766145f, 6.02381f, 7.85298f, -0.268151f, -8.84897f, + -1.3216f, -0.402226f, 5.11401f, 8.77236f, -1.10133f, + -10.1706f, 1.24498f, -1.18752f, 6.40688f, 8.0924f, + -2.60489f, -8.99262f, 2.58574f, 0.632069f, 9.05008f, + 3.61046f, 1.50356f, -9.67257f, 1.93451f, 0.411803f, + 8.81066f, 0.268151f, -0.00957681f, -8.7532f, 2.15478f, + -0.0191536f, 9.49062f, -0.68953f, 0.0383072f, -8.94474f, + 2.99754f, -0.871489f, 9.80665f, 1.53229f, -0.92895f, + -9.88326f, 0.957681f, 0.507571f, 9.19373f, 1.71425f, + 0.287304f, -9.03093f, 0.651223f, 0.363919f, 9.71088f, + 1.18752f, 1.10133f, -10.0556f, 2.98796f, 0.23942f, + 9.39485f, 1.0343f, 0.842759f, -9.73961f, -1.12049f, + 0.172383f, 9.50977f, 1.18752f, 0.0383072f, -9.9503f, + 0.957681f, -0.373495f, 9.96946f, 1.01514f, 0.794875f, + -10.1897f, -1.38864f, -9.50977f, -1.04387f, 0.325611f, + -9.76834f, 1.05345f, -0.679953f, -9.76834f, -0.641646f, + 0.488417f, -9.2895f, 0.316035f, 0.258574f, -9.29908f, + -0.890643f, 0.469264f, -9.33739f, 0.823605f, -0.45011f, + -9.69173f, -1.02472f, 0.536301f, -9.52892f, 0.90022f, + -0.411803f, -9.34696f, -0.890643f, 0.430956f, -9.48104f, + 0.823605f, -0.603339f, -9.7875f, -0.565032f, 0.574608f, + -9.96946f, 0.536301f, -0.699107f, -9.57681f, -0.823605f, + 0.641646f, -9.43316f, 0.593762f, -0.775721f, -9.35654f, + -1.04387f, 0.440533f, -9.77792f, 1.01514f, -0.881066f, + -9.32781f, -1.10133f, 0.306458f, -9.414f, 0.995988f, + 0.0287304f, -9.26077f, -1.01514f, 0.268151f, -9.29908f, + 0.881066f, 0.00957681f, -9.42358f, -0.679953f, 0.201113f, + -9.49062f, 0.488417f, -0.00957681f, -9.47146f, -0.363919f, + 0.191536f, -9.32781f, 0.124498f, 0.124498f, -9.5385f, + -0.0766145f, 0.268151f, -9.32781f, -0.172383f, 0.0574608f, + -9.69173f, 0.21069f, 0.354342f, -9.50019f, -0.306458f, + 0.0383072f, -9.54808f, 0.507571f, 0.363919f, -9.20331f, + -0.775721f, 0.0574608f, -9.59596f, 0.651223f, 0.679953f, + -9.56723f, -0.794875f, -0.0287304f, -9.49062f, 0.794875f, + 0.612916f, -9.06924f, -1.10133f, -0.201113f, -9.20331f, + 1.90578f, 1.46525f, -9.29908f, -2.17394f, 0.603339f, + -0.995988f, 0.0766145f, 9.58638f, -0.344765f, -0.92895f, + -9.1267f, -2.03986f, -0.497994f, 10.477f, -2.49955f, + -0.0957681f, -10.4866f, -1.5706f, -0.23942f, 9.13627f, + -1.92494f, -0.325611f, -9.05008f, -1.5706f, -0.0383072f, + 10.1323f, -1.87705f, -0.632069f, -9.52892f, -1.20668f, + 0.105345f, 9.14585f, -1.13964f, -0.718261f, -9.02135f, + -1.58975f, 0.296881f, 9.50019f, -1.74298f, -1.00556f, + -9.27993f, -1.09176f, 0.23942f, 9.87369f, -1.04387f, + -0.995988f, -9.35654f, -2.08774f, -0.526724f, 9.89284f, + -1.40779f, -0.459687f, -9.50977f, -2.70066f, -1.47483f, + 8.95431f, -1.92494f, 0.526724f, -8.95431f, -1.05345f, + -0.938527f, 9.14585f, -3.02627f, 1.04387f, -8.78193f, + 1.00556f, -3.56257f, 9.0022f, 1.96325f, 2.36547f, + -9.83538f, 1.02472f, -2.59531f, 9.49062f, 1.0726f, + 1.77171f, -9.06924f, 0.0861913f, -2.17394f, 9.21289f, + -0.823605f, 1.52271f, -10.1323f, 0.316035f, -3.09331f, + 10.0844f, 0.555455f, 2.00155f, -9.75877f, 1.51314f, + -2.24097f, 9.61511f, 0.670376f, 1.35033f, -9.77792f, + 0.986411f, -3.36146f, 9.59596f, 1.77171f, 2.29843f, + -9.48104f, 1.4461f, -2.8922f, 8.88728f, 1.84832f, + 2.38462f, -9.19373f, 1.75256f, -2.6432f, 9.89284f, + 1.38864f, 2.19309f, -9.20331f, 9.98861f, -0.718261f, + -0.746991f, 10.6111f, 0.632069f, 0.948104f, 8.99262f, + -0.258574f, 0.517148f, 9.10754f, 0.21069f, -1.21625f, + 9.90242f, -0.162806f, 0.0287304f, 10.5249f, -0.0861913f, + 0.229843f, 9.83538f, 0.0f, 0.181959f, 10.4291f, + -0.172383f, -0.47884f, 9.43316f, 0.201113f, -0.268151f, + 9.76834f, -0.134075f, -0.354342f, 10.0556f, 1.0726f, + 0.277727f, 9.93115f, -1.05345f, 0.363919f, 9.79707f, + 0.651223f, 0.699107f, 10.0173f, -0.775721f, 0.0670376f, + 9.49062f, 0.296881f, 0.919373f, 10.1801f, -0.68953f, + -0.651223f, 9.70131f, 1.00556f, 0.248997f, 9.42358f, + -0.995988f, 1.45567f, 9.13627f, -1.35033f, 2.36547f, + 9.40442f, 0.976834f, -4.34787f, 8.79151f, -0.90022f, + 1.56102f, 8.92558f, 0.6608f, -2.3942f, 9.59596f, + -0.363919f, 1.40779f, 9.05966f, 0.181959f, -2.1452f, + 9.48104f, -0.612916f, 2.36547f, 9.03093f, 0.21069f, + -2.18351f, 9.74919f, -1.5706f, 2.07817f, 8.85855f, + 1.04387f, -2.30801f, 8.81066f, -1.66636f, 3.4285f, + 8.52336f, 0.440533f, -4.52983f, 9.27993f, -2.19309f, + 2.2697f, 8.83939f, 0.90022f, -2.48039f, 9.1267f, + -2.77727f, 1.4461f, 8.78193f, 0.814029f, -4.24253f, + 8.90643f, -3.39977f, 0.651223f, 8.86812f, 1.08218f, + -2.34632f, 9.42358f, -3.26569f, 0.402226f, 8.94474f, + 0.526724f, -2.65278f, 9.38527f, -3.21781f, 0.0f, + 9.20331f, 0.143652f, -2.71024f, 9.44273f, -2.8922f, + -0.497994f, 9.35654f, 0.105345f, -2.78685f, 9.09797f, + -3.4285f, -1.00556f, 8.81066f, 0.785298f, -3.84988f, + 9.31823f, -3.09331f, -1.4461f, 8.68616f, 0.555455f, + -3.27527f, 9.414f, -2.5187f, -1.79086f, 8.59997f, + 0.766145f, -3.47638f, 9.0022f, -2.67193f, -2.43251f, + 8.77236f, 1.39821f, -2.85389f, 8.25521f, -3.29442f, + -2.46124f, 8.15944f, 1.09176f, -3.51469f, 8.72447f, + -2.69108f, -2.48997f, 8.91601f, 0.881066f, -3.66792f, + 8.92558f, -2.33674f, -2.31759f, 8.84897f, 1.06303f, + -3.055f, 8.92558f, -2.49955f, -2.29843f, 8.81066f, + 0.919373f, -2.56658f, 9.31823f, -2.78685f, -1.81959f, + 9.06924f, 0.411803f, -2.86347f, 9.38527f, -2.78685f, + -1.70467f, 9.25119f, 0.335188f, -4.67348f, 9.165f, + -3.9648f, -0.622492f, 8.65743f, 0.248997f, -3.055f, + 9.414f, -3.67749f, 0.0287304f, 8.82982f, 0.852336f, + -2.50912f, 8.82024f, -3.47638f, 0.201113f, 8.98304f, + 1.06303f, -3.33273f, 8.89685f, -3.64876f, 0.718261f, + 8.91601f, 1.52271f, -2.70066f, 8.95431f, -3.56257f, + 1.35991f, 9.05008f, 1.67594f, -3.16992f, 9.08839f, + -3.16035f, 2.03028f, 9.07881f, 1.64721f, -3.04542f, + 8.91601f, -3.11246f, 2.52828f, 8.88728f, 2.07817f, + -1.99198f, 9.1267f, -2.806f, 0.162806f, 9.1267f, + 2.806f, -2.07817f, 9.14585f, -2.31759f, 2.16436f, + 8.8777f, 2.19309f, -1.88663f, 9.88326f, -2.5187f, + 1.94409f, 9.1267f, 2.46124f, -2.806f, 7.64229f, + -6.0717f, 2.9305f, 8.07325f, 5.64074f, -2.63362f, + 4.29999f, -7.9679f, 0.622492f, 4.71179f, 7.74764f, + -3.41892f, 4.42448f, -8.99262f, 1.13964f, 3.98395f, + 8.47547f, -1.9824f, -0.699107f, -9.46189f, -0.794875f, + -0.593762f, 9.24162f, -2.74854f, 1.88663f, -8.8777f, + -0.153229f, 0.861913f, 8.98304f, -2.48039f, -1.52271f, + -9.32781f, -3.39977f, 0.0574608f, 8.99262f, -5.88974f, + -0.746991f, -3.93607f, -8.01579f, -1.17795f, 8.41801f, + -4.17549f, -2.30801f, -2.61447f, -9.44273f, -2.3942f, + 7.46991f, -5.01825f, -1.0343f, 1.89621f, -8.8777f, + -0.890643f, 8.65743f, -4.31914f, -2.16436f, 1.49398f, + -9.69173f, -1.37906f, 9.05008f, -2.43251f, -1.87705f, + 0.402226f, -8.95431f, -2.01113f, 8.72447f, -3.54342f, + -0.344765f, -2.95923f, -8.42759f, -0.92895f, 8.99262f, + -2.34632f, -0.392649f, -6.70376f, -6.55054f, -0.919373f, + 8.80109f, -2.35589f, -0.0766145f, -8.8777f, -5.89931f, + 0.890643f, 9.7875f, 2.24097f, -0.536301f, -8.08282f, + -4.88417f, -0.191536f, 9.21289f, 1.16837f, -0.440533f, + -7.93917f, -4.81713f, -0.890643f, 9.08839f, 1.75256f, + -1.20668f, -9.414f, -2.57616f, -0.708684f, 9.50977f, + 1.40779f, -1.14922f, -9.8258f, -1.24498f, -0.584185f, + 9.63427f, 0.727837f, -0.181959f, -9.25119f, -2.31759f, + -0.0574608f, 9.64384f, -0.612916f, 1.21625f, -9.50977f, + -1.16837f, 0.756568f, 9.45231f, -0.316035f, 1.21625f, + -10.5441f, -0.45011f, 1.5706f, 9.7875f, -1.22583f, + 9.07881f, 0.0766145f, -2.34632f, 9.26077f, 0.316035f, + 4.28083f, 8.72447f, 0.584185f, -3.27527f, 8.39886f, + 0.47884f, 3.98395f, 9.26077f, 2.35589f, -2.98796f, + 9.52892f, -1.61848f, 3.73495f, 8.91601f, 2.98796f, + -3.36146f, 9.7875f, -2.31759f, 3.60088f, 8.86812f, + 3.32315f, -3.62961f, 9.76834f, -2.46124f, 2.72939f, + 2.31759f, 10.2089f, -2.3942f, 0.995988f, -8.68616f, + 5.5737f, 1.13006f, 9.04051f, -2.09732f, 1.26414f, + -8.51378f, 4.40533f, 0.852336f, 9.91199f, -2.07817f, + 0.622492f, -9.18416f, 4.29999f, 0.229843f, 10.0269f, + -1.08218f, 0.220267f, -9.40442f, 4.40533f, 0.0766145f, + 9.54808f, -1.89621f, 0.967257f, -9.05966f, 3.92649f, + 0.335188f, 9.62469f, -0.497994f, 0.430956f, -9.71088f, + 4.02226f, 0.718261f, 9.63427f, 1.59933f, 0.383072f, + -8.88728f, 3.24654f, 0.42138f, 8.71489f, 2.55701f, + 0.68953f, -9.64384f, 1.67594f, 1.0726f, -7.0198f, + 7.20176f, 0.641646f, -9.17458f, 4.18506f, -0.402226f, + -2.46124f, 8.78193f, -0.0383072f, -8.31267f, 4.03184f, + 0.23942f, 2.27928f, 10.4675f, -0.517148f, -9.47146f, + 4.14676f, -1.37906f, 9.59596f, -4.07972f, 3.45723f, + -9.663f, 1.71425f, -0.134075f, 6.95276f, -5.80354f, + 0.268151f, -5.38217f, 7.03895f, 0.00957681f, 5.20978f, + -7.75721f, -0.047884f, -2.83473f, 8.53294f, -0.306458f, + 1.64721f, -8.64786f, 0.766145f, 0.162806f, 8.84897f, + -0.191536f, -2.58574f, -9.19373f, 0.0f, 4.05099f, + 8.52336f, -0.0383072f, -3.10289f, -9.17458f, 0.45011f, + 4.11803f, 9.19373f, 0.0957681f, -2.47082f, -9.61511f, + 0.804452f, 3.98395f, 8.52336f, 0.114922f, 4.00311f, + -8.76278f, 0.699107f, 4.53941f, 8.28394f, -0.0383072f, + 7.95833f, -6.57927f, -0.124498f, 3.52426f, 10.1035f, + -0.229843f, 6.68461f, -6.2345f, -0.153229f, 3.04542f, + 9.59596f, -0.344765f, 7.47949f, -7.29753f, 0.114922f, + 3.90734f, 9.03093f, -0.383072f, 7.57525f, -7.20176f, + -0.172383f, 3.70622f, 9.8258f, -0.335188f, 7.21134f, + -6.7325f, -0.172383f, 2.71024f, 10.2855f, -0.114922f, + 6.608f, -7.41245f, -0.201113f, 1.87705f, 9.39485f, + 1.37906f, -0.0670376f, -9.47146f, 1.1971f, 1.8579f, + 9.49062f, 0.842759f, -1.63763f, -8.95431f, 0.679953f, + 2.8922f, 9.1267f, 1.43652f, -1.58017f, -9.01178f, + 0.890643f, 3.66792f, 9.22246f, 0.746991f, -1.18752f, + -9.04051f, 2.12605f, 2.72939f, 9.52892f, 3.79242f, + 1.48441f, -9.04051f, 4.57771f, -0.785298f, 9.61511f, + 4.61602f, 1.21625f, -8.4659f, 4.94163f, -0.574608f, + 8.4659f, 4.67348f, 1.48441f, -8.23605f, 4.86502f, + -0.852336f, 9.24162f, 5.12359f, 0.92895f, -9.03093f, + 5.84185f, -0.430956f, 8.92558f, 5.38217f, 0.440533f, + -8.37971f, 6.72292f, -0.220267f, 8.02536f, 6.608f, + 1.6089f, -6.30154f, 6.33985f, 0.277727f, 6.58884f, + 9.85453f, 1.39821f, 0.153229f, 10.0844f, -1.46525f, + 0.45011f, 9.68215f, 1.90578f, -0.0766145f, 9.98861f, + -1.96325f, 0.536301f, 9.90242f, 2.20267f, 0.143652f, + 9.94073f, -2.20267f, 0.191536f, 9.46189f, 1.95367f, + 0.0957681f, 9.74919f, -2.06859f, 0.296881f, 9.30866f, + 1.64721f, 0.153229f, 9.84496f, -1.92494f, 0.574608f, + 7.38372f, 0.488417f, 6.76123f, 8.83939f, -1.37906f, + -3.11246f, 9.2895f, 0.153229f, -0.976834f, 9.86411f, + -0.0574608f, -0.957681f, 9.26077f, 0.833182f, 2.07817f, + 9.26077f, -0.938527f, -0.957681f, 10.0269f, -0.354342f, + 2.43251f, 9.84496f, 0.153229f, -0.957681f, 0.986411f, + -8.74362f, 1.34075f, 2.09732f, 9.165f, -1.84832f, + -1.25456f, -10.228f, 2.19309f, 0.42138f, 9.73004f, + -1.23541f, -1.49398f, -10.1706f, 0.172383f, -1.22583f, + 10.2089f, -0.593762f, -2.2314f, -9.663f, -0.526724f, + -1.6089f, 9.65342f, 0.593762f, -2.38462f, -9.165f, + -1.4461f, -2.46124f, 9.42358f, 0.430956f, -2.38462f, + -9.73004f, 0.0383072f, -2.31759f, 9.57681f, -0.47884f, + -2.44209f, -9.5385f, -0.746991f, -2.32716f, 9.58638f, + 0.612916f, -2.34632f, -10.1418f, -1.0726f, -1.92494f, + 9.90242f, 0.890643f, -2.84431f, 9.38527f, -2.38462f, + -1.69509f, -9.50977f, 2.73897f, -3.88818f, 7.9296f, + -2.40378f, -1.5706f, -8.4659f, 2.62405f, -8.91601f, + -2.98796f, 0.497994f, -8.97347f, 2.79643f, 0.373495f, + -10.3717f, 1.02472f, -0.105345f, -10.0461f, -1.02472f, + 0.679953f, -4.89375f, 8.17859f, 0.0766145f, -6.12916f, + -7.61356f, 0.172383f, -6.4835f, 7.5561f, -0.363919f, + -6.09085f, -7.46991f, 0.699107f, -6.19619f, 7.62314f, + -0.248997f, -5.78439f, -7.52737f, 1.55144f, -6.33985f, + 7.50822f, -0.45011f, -5.6982f, -7.48906f, 1.48441f, + -6.36858f, 7.46991f, -0.373495f, -5.72693f, -7.44118f, + 1.63763f, -6.33027f, 7.8434f, -0.316035f, -6.54096f, + -7.57525f, 1.37906f, -6.69419f, 7.52737f, -0.258574f, + -6.41646f, -7.37414f, 1.21625f, -6.62715f, 7.61356f, + -0.392649f, -6.24408f, -7.48906f, 1.23541f, -6.18662f, + 7.60398f, -0.201113f, -5.9472f, -7.45076f, 1.39821f, + -6.14831f, 7.86256f, -0.584185f, -6.26323f, -7.50822f, + 1.6089f, -5.26724f, 8.74362f, -0.153229f, -4.57771f, + -8.41801f, 0.6608f, -3.56257f, 8.82024f, 0.114922f, + -2.86347f, -8.82982f, 0.948104f, -2.53785f, 9.27035f, + 0.23942f, -2.33674f, -9.29908f, 1.02472f, -2.12605f, + 9.67257f, 0.354342f, -2.1452f, -9.45231f, 0.335188f, + -1.71425f, 9.36612f, 0.287304f, -1.41737f, -9.27035f, + -0.229843f, -2.65278f, 8.94474f, -0.306458f, -0.737414f, + -9.414f, 0.172383f, -8.72447f, 5.46836f, 0.325611f, + -10.2663f, -1.80044f, -0.143652f, -9.35654f, -0.794875f, + -0.756568f, -10.1801f, 1.0343f, 1.20668f, -9.54808f, + -0.986411f, -0.766145f, -9.165f, 0.890643f, 1.13964f, + -8.92558f, -0.555455f, -1.22583f, -9.68215f, 0.976834f, + 0.344765f, -9.14585f, 4.05099f, -1.31202f, -9.57681f, + 0.68953f, 1.51314f, -9.54808f, 0.0957681f, 1.45567f, + -9.18416f, -0.229843f, -0.6608f, -9.71088f, 0.047884f, + 1.35033f, -9.87369f, 0.0383072f, -0.909797f, -8.57124f, + 1.1971f, 3.86903f, -9.76834f, -1.13964f, -2.2697f, + -9.38527f, 0.890643f, 2.74854f, -9.38527f, -1.20668f, + -2.3942f, -8.74362f, 1.4461f, 3.45723f, -8.99262f, + -1.72383f, -2.56658f, -9.48104f, 1.13006f, 2.98796f, + -8.80109f, -1.76213f, -2.52828f, -9.69173f, 1.15879f, + 2.3942f, -8.98304f, -1.68552f, -1.71425f, -8.93516f, + 1.25456f, 3.26569f, -9.61511f, -1.38864f, -2.46124f, + -9.37569f, 1.4461f, 3.40934f, -8.83939f, -2.1069f, + -2.42293f, -9.165f, 1.61848f, 2.9305f, -9.165f, + -2.04944f, -2.50912f, -9.31823f, 0.823605f, 0.0f, + -9.48104f, -0.909797f, 0.497994f, -9.30866f, 1.0343f, + -0.775721f, -9.01178f, -1.15879f, 0.814029f, -9.25119f, + 0.948104f, -0.00957681f, -8.80109f, -1.16837f, 0.737414f, + -9.62469f, 1.39821f, -0.248997f, -9.39485f, -1.45567f, + 0.957681f, -9.57681f, 1.79086f, -0.296881f, -9.50019f, + -1.81002f, 0.842759f, -10.0652f, 1.45567f, -0.248997f, + -9.05966f, -1.61848f, 0.871489f, -9.69173f, 1.56102f, + -0.459687f, -8.91601f, -1.77171f, 0.890643f, -9.48104f, + -0.47884f, -0.497994f, -9.48104f, 0.296881f, 0.632069f, + -10.094f, 0.191536f, -0.248997f, -10.4387f, -0.0670376f, + 0.6608f, -8.08282f, 4.95121f, -1.31202f, -8.17859f, + -4.70221f, 1.80044f, -7.9296f, 5.04698f, -0.536301f, + -8.38928f, -4.80756f, 0.68953f, -8.10198f, 5.23851f, + -0.507571f, -7.97748f, -5.17148f, 1.21625f, -8.37013f, + 5.22894f, -0.497994f, -8.01579f, -5.23851f, 0.976834f, + -8.20732f, 5.20978f, -0.335188f, -7.99663f, -5.19063f, + 0.995988f, -8.26478f, 5.02782f, -0.0957681f, -8.0924f, + -5.0374f, 0.948104f, -8.36055f, 5.02782f, -0.268151f, + -8.02536f, -5.09486f, 0.995988f, -8.28394f, 5.01825f, + -0.191536f, -8.20732f, -5.06613f, 0.861913f, -8.37971f, + 5.06613f, -0.325611f, -8.20732f, -5.00867f, 0.92895f, + -8.3414f, 5.04698f, -0.124498f, -8.13071f, -5.14275f, + 0.852336f, -8.29351f, 5.07571f, -0.0766145f, -8.07325f, + -5.10444f, 0.976834f, -8.47547f, 4.77883f, -0.392649f, + -8.13071f, -4.86502f, 1.05345f, -8.60955f, 2.71981f, + 2.79643f, -9.25119f, 1.31202f, -0.306458f, -9.14585f, + 1.02472f, 1.51314f, -8.64786f, -1.33118f, -1.13964f, + -9.35654f, 1.01514f, 2.31759f, -8.72447f, -1.49398f, + -1.72383f, -9.73004f, 1.58017f, 2.7677f, -9.73004f, + -1.84832f, -1.93451f, -9.15543f, 1.33118f, 2.20267f, + -8.93516f, -1.64721f, -0.995988f, -9.45231f, 0.727837f, + 1.81959f, -9.51935f, -0.909797f, -2.78685f, -9.93115f, + 0.191536f, 0.890643f, -9.84496f, -0.23942f, -0.976834f, + -9.61511f, -0.21069f, 0.517148f, -8.80109f, -0.153229f, + -0.430956f, -9.50019f, 0.373495f, 0.948104f, -9.27035f, + -0.555455f, -0.344765f, -9.57681f, 0.172383f, 0.881066f, + -9.43316f, -0.335188f, -0.756568f, -9.50977f, -0.0191536f, + 0.497994f, -9.42358f, -0.181959f, -0.737414f, -9.92157f, + 0.306458f, 0.545878f, -10.0173f, -0.248997f, -0.134075f, + -9.79707f, 0.0287304f, 0.536301f, -9.71088f, -0.162806f, + -0.181959f, -9.60554f, -0.047884f, 0.804452f, -9.39485f, + -0.181959f, -0.593762f, -9.64384f, -0.047884f, 0.612916f, + -9.58638f, -0.201113f, -0.363919f, -9.56723f, 0.248997f, + 0.411803f, -10.1706f, -0.316035f, -0.526724f, -9.63427f, + 0.459687f, 1.09176f, -9.71088f, -0.603339f, -0.23942f, + -9.62469f, -0.0383072f, 0.68953f, -9.50019f, -0.0861913f, + -1.13006f, -9.80665f, -0.134075f, 0.335188f, -9.40442f, + -0.114922f, -0.354342f, -9.34696f, 0.153229f, 1.54187f, + -9.10754f, -0.526724f, -1.00556f, -9.7875f, 0.0287304f, + 0.775721f, -9.58638f, -0.172383f, -0.641646f, -9.60554f, + 0.258574f, 0.919373f, -9.31823f, -0.402226f, -0.603339f, + -9.5385f, -0.0766145f, 0.92895f, -9.09797f, -0.220267f, + -0.354342f, -9.61511f, -0.335188f, 0.316035f, -9.27993f, + 0.0766145f, -0.47884f, -9.40442f, 0.23942f, 0.6608f, + -9.40442f, -0.335188f, -0.603339f, -9.85453f, -0.0766145f, + 0.459687f, -9.54808f, -0.0670376f, -0.287304f, -9.63427f, + -0.344765f, 0.296881f, -9.32781f, 0.0574608f, -0.220267f, + -9.71088f, 0.181959f, 0.354342f, -9.95988f, -0.248997f, + 0.201113f, -9.8258f, -0.0383072f, 0.833182f, -9.83538f, + -0.047884f, -0.670376f, -9.44273f, 0.0670376f, 0.6608f, + -8.90643f, -0.392649f, -0.354342f, -9.54808f, 0.0957681f, + 0.90022f, -9.05008f, -0.411803f, -0.335188f, -9.52892f, + 0.201113f, 1.12049f, -9.23204f, -0.459687f, -0.842759f, + -9.61511f, -0.162806f, 0.248997f, -9.87369f, 0.124498f, + -1.12049f, -9.70131f, -0.0383072f, 0.670376f, -9.50977f, + -0.162806f, -0.890643f, -9.15543f, 0.488417f, 1.51314f, + -8.94474f, -0.852336f, -0.90022f, -9.60554f, -0.23942f, + 0.622492f, -9.35654f, 0.0f, -0.948104f, -9.64384f, + -0.191536f, 1.21625f, -9.2895f, -0.0766145f, -0.785298f, + -9.55765f, -0.306458f, 0.555455f, -9.73004f, 0.172383f, + -0.603339f, -9.663f, -0.306458f, 0.383072f, -9.63427f, + 0.172383f, -0.354342f, -9.70131f, -0.373495f, 0.68953f, + -9.69173f, 0.181959f, -1.0343f, -9.47146f, -0.526724f, + 0.823605f, -9.23204f, 0.220267f, -1.36948f, -9.36612f, + -0.0670376f, 1.05345f, -8.91601f, -0.316035f, -0.814029f, + -9.93115f, -0.268151f, 1.58017f, -10.0748f, 0.143652f, + -1.26414f, -9.87369f, 0.047884f, 2.09732f, -9.39485f, + -0.344765f, -1.48441f, -9.48104f, 0.967257f, 0.699107f, + -9.34696f, -1.15879f, -0.105345f, -9.414f, 0.852336f, + 0.756568f, -9.62469f, -1.0343f, -0.114922f, -9.80665f, + 0.814029f, 0.737414f, -9.23204f, -1.0726f, -0.23942f, + -9.47146f, 0.890643f, 0.392649f, -9.24162f, -1.08218f, + -0.229843f, -9.42358f, 0.775721f, 0.325611f, -9.21289f, + -0.986411f, -0.201113f, -9.52892f, 1.79086f, 2.04944f, + -9.32781f, -2.15478f, -1.39821f, -8.86812f, 2.07817f, + 2.2697f, -8.91601f, -2.24097f, -1.7334f, -9.34696f, + 1.68552f, 2.29843f, -8.78193f, -2.19309f, -1.58017f, + -9.62469f, 1.7334f, 2.35589f, -9.165f, -2.18351f, + -1.63763f, -9.99819f, 2.28886f, 2.27928f, -10.0365f, + -2.36547f, -1.69509f, -10.726f, -0.488417f, -0.363919f, + -9.25119f, 0.976834f, -3.03585f, -9.31823f, 1.41737f, + 2.09732f, -8.8777f, -1.76213f, 0.651223f, -9.71088f, + 1.00556f, 2.28886f, -9.36612f, -1.13006f, -1.53229f, + -9.87369f, 0.814029f, 1.46525f, -9.92157f, -0.919373f, + -0.957681f, -9.35654f, 0.0191536f, 1.09176f, -9.9503f, + -0.0574608f, -1.0726f, -9.50977f, -0.181959f, 0.603339f, + -8.90643f, -0.172383f, -0.0766145f, -9.85453f, -0.287304f, + 0.833182f, -9.76834f, 0.181959f, -0.402226f, -9.50977f, + -0.0957681f, 0.287304f, -9.7875f, 0.0191536f, -0.47884f, + -9.58638f, 0.047884f, 0.344765f, -9.44273f, -0.181959f, + -0.0861913f, -9.57681f, 0.0287304f, 0.555455f, -9.42358f, + -0.220267f, 0.0f, -9.73004f, -0.229843f, 0.21069f, + -9.51935f, 0.0670376f, -0.21069f, -10.0173f, -0.00957681f, + 0.105345f, -9.68215f, -0.0670376f, -0.124498f, -9.50977f, + 0.114922f, 0.287304f, -9.42358f, -0.229843f, 0.0957681f, + -9.57681f, -0.181959f, 0.181959f, -9.32781f, -0.047884f, + 0.105345f, -10.0078f, -0.258574f, -2.19309f, -9.70131f, + 0.248997f, 1.64721f, -9.55765f, -0.612916f, 0.105345f, + -8.76278f, 0.191536f, 0.919373f, -9.414f, -0.0383072f, + -0.641646f, -9.74919f, 0.0670376f, 0.814029f, -9.80665f, + -0.134075f, -0.804452f, -9.44273f, 0.0957681f, 1.01514f, + -9.71088f, 0.220267f, -0.584185f, -9.32781f, -0.248997f, + 0.957681f, -9.76834f, 0.0766145f, -0.440533f, -9.414f, + -0.21069f, 0.708684f, -9.73004f, 0.0574608f, -0.593762f, + -9.27035f, -0.172383f, 0.756568f, -9.663f, 0.287304f, + 0.172383f, -9.10754f, -0.507571f, 0.718261f, -9.49062f, + 0.229843f, 0.0574608f, -9.50977f, -0.402226f, 0.162806f, + -10.1418f, -0.0670376f, -0.411803f, -9.32781f, -0.0383072f, + 0.804452f, -9.57681f, 0.229843f, -0.21069f, -9.57681f, + -0.296881f, 0.469264f, -9.54808f, 2.03986f, 0.641646f, + -10.0269f, -1.00556f, -0.45011f, -8.77236f, 0.402226f, + 0.718261f, -9.37569f, -0.047884f, -0.344765f, -9.98861f, + -1.48441f, 0.047884f, -9.33739f, 1.33118f, -0.23942f, + -9.30866f, -0.68953f, 0.220267f, -10.0556f, 0.708684f, + 0.201113f, -7.12514f, 6.70376f, 0.105345f, -6.81869f, + -6.33985f, 0.92895f, -8.70532f, 5.46836f, 0.220267f, + -8.41801f, -5.36301f, 0.0574608f, -9.84496f, 3.82115f, + 0.248997f, -9.9503f, -3.5913f, -0.229843f, -10.3238f, + 3.09331f, -0.0574608f, -9.71088f, -2.66235f, 0.6608f, + -8.68616f, 1.53229f, 0.641646f, -9.17458f, -1.22583f, + 0.507571f, -10.0078f, -1.09176f, -0.622492f, -10.0078f, + 1.3216f, -0.497994f, -9.46189f, -1.17795f, 0.0766145f, + -9.23204f, 1.01514f, 0.248997f, -9.38527f, -1.94409f, + 0.296881f, -9.21289f, 1.79086f, -0.21069f, -9.10754f, + -2.12605f, 0.440533f, -9.09797f, 1.82917f, 0.172383f, + -9.02135f, -1.54187f, 0.047884f, -9.35654f, 1.54187f, + 0.047884f, -8.99262f, -1.66636f, -0.0191536f, -9.29908f, + 1.49398f, 0.344765f, -9.663f, -1.65679f, -0.593762f, + -9.29908f, 1.58975f, 0.296881f, -9.69173f, -1.1971f, + -0.153229f, -9.5385f, 1.16837f, 0.114922f, -9.80665f, + -1.22583f, 0.268151f, -9.43316f, 1.08218f, -0.114922f, + -9.74919f, -1.27372f, 0.775721f, -9.38527f, 1.11091f, + -0.440533f, -9.49062f, -1.20668f, 0.574608f, -9.37569f, + 0.995988f, -0.536301f, -9.33739f, -1.06303f, 0.871489f, + -9.5385f, 0.948104f, -0.699107f, -9.44273f, -0.976834f, + 0.871489f, -9.72046f, 0.890643f, -0.746991f, -9.87369f, + -1.33118f, 0.488417f, -9.46189f, 1.13006f, 0.248997f, + -8.92558f, -1.0343f, -0.134075f, -9.07881f, 1.04387f, + 0.737414f, -8.82982f, -0.814029f, -1.46525f, -9.20331f, + 1.06303f, 0.105345f, -9.94073f, -0.957681f, -0.153229f, + -9.35654f, 0.948104f, -0.603339f, -9.31823f, 1.34075f, + 2.03028f, -8.82024f, -1.76213f, -0.861913f, -8.42759f, + -0.440533f, 4.67348f, -8.94474f, 0.201113f, -5.08528f, + -7.51779f, -0.948104f, 5.77481f, -8.15944f, 0.833182f, + -5.63116f, -9.69173f, -0.948104f, 2.36547f, -10.1801f, + 0.679953f, -2.2314f, -9.11712f, 1.72383f, 0.574608f, + -8.83939f, -2.03986f, -0.0287304f, -9.31823f, 1.92494f, + 0.804452f, -9.79707f, -2.03028f, -0.517148f, -8.3414f, + 2.68151f, 1.9824f, -8.24563f, -2.71024f, -2.1069f, + -9.15543f, 2.41336f, 2.28886f, -7.49864f, -3.03585f, + -3.66792f, -8.59997f, 2.00155f, 2.59531f, -9.07881f, + -2.11647f, -2.52828f, -9.64384f, 1.89621f, 2.11647f, + -9.36612f, -2.16436f, -1.83875f, -9.01178f, 1.69509f, + 2.19309f, -9.17458f, -1.94409f, -1.56102f, -9.27993f, + 1.49398f, 2.28886f, -9.51935f, -1.72383f, -2.2697f, + -9.10754f, 1.52271f, 2.43251f, -8.84897f, -2.02071f, + -2.02071f, -9.08839f, 1.51314f, 2.55701f, -9.11712f, + -1.8579f, -2.21224f, -9.09797f, 1.47483f, 2.52828f, + -9.13627f, -1.8579f, -2.09732f, -9.06924f, 1.46525f, + 2.43251f, -8.92558f, -1.90578f, -2.09732f, -9.19373f, + 1.50356f, 2.3942f, -9.21289f, -1.82917f, -2.26013f, + -8.5904f, 2.16436f, 2.33674f, -8.51378f, -2.36547f, + -1.83875f, -8.25521f, 3.62961f, 2.03028f, -7.91044f, + -3.74453f, -1.12049f, -8.61913f, 3.84988f, 1.62806f, + -8.83939f, -3.97437f, -1.26414f, -8.23605f, 4.52025f, + 2.13563f, -8.83939f, -4.35745f, -1.14922f, -7.4316f, + 6.02381f, 2.34632f, -7.33583f, -5.84185f, -1.79086f, + -6.63673f, 6.67503f, 2.37505f, -6.44519f, -6.359f, + -1.62806f, -6.06212f, 7.51779f, 2.38462f, -6.25365f, + -7.23049f, -1.80044f, -5.25767f, 8.64786f, 2.09732f, + -4.32872f, -8.68616f, -2.03986f, -4.39575f, 7.97748f, + 2.00155f, -3.77326f, -8.42759f, -0.775721f, -4.64475f, + 8.32224f, 1.61848f, -4.29999f, -8.60955f, -0.622492f, + -4.7501f, 8.5042f, 1.81959f, -4.79798f, -8.4659f, + -1.08218f, -4.64475f, 8.37013f, 1.92494f, -4.53941f, + -8.5904f, -1.13964f, -4.77883f, 8.73405f, 2.11647f, + -3.33273f, -9.414f, -1.37906f, -9.73004f, -0.92895f, + 0.603339f, -9.67257f, 0.852336f, -1.11091f, -9.87369f, + -0.047884f, 0.153229f, -9.98861f, 0.0670376f, -0.440533f, + -9.61511f, 0.651223f, 0.181959f, -9.5385f, -0.785298f, + 0.612916f, -9.50019f, 0.335188f, -0.23942f, -8.88728f, + -0.536301f, 0.00957681f, -9.95988f, 0.670376f, 0.134075f, + -9.29908f, -0.881066f, 0.0861913f, -9.67257f, 0.488417f, + 0.220267f, -9.62469f, -0.545878f, 0.306458f, -9.58638f, + 0.344765f, 0.306458f, -9.165f, -0.574608f, 0.0287304f, + -9.65342f, 0.143652f, 0.287304f, -10.0844f, -0.191536f, + 0.440533f, -9.40442f, 0.679953f, 0.21069f, -9.37569f, + -0.881066f, 0.402226f, -9.79707f, 1.34075f, 0.785298f, + -10.1801f, -1.13964f, -0.220267f, -9.14585f, 2.29843f, + 0.794875f, -9.36612f, -2.24097f, -0.316035f, -8.83939f, + 3.37104f, 0.727837f, -8.70532f, -3.25611f, 0.0766145f, + -8.24563f, 4.42448f, 0.814029f, -8.14029f, -4.27126f, + -0.392649f, -7.63272f, 5.38217f, 0.957681f, -7.05811f, + -5.5737f, -0.0383072f, -7.57525f, 5.93762f, 1.29287f, + -7.02938f, -6.02381f, -0.651223f, -7.46991f, 6.18662f, + 1.76213f, -7.35499f, -6.21535f, -1.37906f, -7.35499f, + 6.38773f, 1.47483f, -7.40287f, -6.27281f, -0.967257f, + -7.02938f, 6.79953f, 1.30245f, -6.95276f, -6.68461f, + -0.890643f, -6.42604f, 7.32626f, 1.09176f, -6.4835f, + -7.19218f, -0.354342f, -6.41646f, 7.57525f, 0.938527f, + -6.11958f, -7.50822f, -0.229843f, -5.88016f, 7.71891f, + 0.794875f, -5.17148f, -7.70933f, 0.105345f, -5.74608f, + 7.85298f, 0.727837f, -5.09486f, -7.72848f, 0.114922f, + -5.9472f, 7.83383f, 0.727837f, -5.91847f, -7.65187f, + -0.0287304f, -5.97593f, 7.77637f, 0.718261f, -6.01423f, + -7.63272f, 0.191536f, -5.95677f, 7.78594f, 0.526724f, + -5.73651f, -7.6806f, 0.507571f, -5.95677f, 7.89129f, + 0.459687f, -5.66947f, -7.74764f, 0.517148f, -5.93762f, + 7.85298f, 0.430956f, -5.81312f, -7.69018f, 0.459687f, + -5.9855f, 7.78594f, 0.469264f, -5.86101f, -7.65187f, + 0.517148f, -6.03339f, 7.82425f, 0.411803f, -5.75566f, + -7.67102f, 0.526724f, -6.00466f, 7.79552f, 0.402226f, + -5.68862f, -7.67102f, 0.42138f, -6.00466f, 7.79552f, + 0.497994f, -5.60243f, -7.69975f, 0.201113f, -6.13873f, + 7.65187f, 0.42138f, -5.3247f, -7.62314f, 0.172383f, + -6.608f, 7.40287f, 0.258574f, -5.77481f, -7.46991f, + 0.593762f, -7.18261f, 6.82826f, 0.134075f, -6.75165f, + -6.71334f, 0.526724f, -7.88171f, 5.79397f, -0.181959f, + -7.19218f, -5.70778f, 1.54187f, -8.4659f, 4.54898f, + -0.842759f, -7.90087f, -4.30956f, 1.95367f, -10.5728f, + 0.632069f, -1.96325f, -9.84496f, 0.153229f, 1.82917f, + -9.27993f, -0.0861913f, -0.92895f, -9.31823f, 0.047884f, + 1.46525f, -9.93115f, 0.325611f, -1.1971f, -10.2759f, + -0.114922f, 2.3942f, -9.59596f, -0.0766145f, -0.316035f, + -9.97903f, 0.363919f, -1.13964f, -9.04051f, 2.50912f, + 1.31202f, -8.67659f, -2.58574f, -0.603339f, -9.83538f, + 1.00556f, 1.40779f, -9.09797f, -0.92895f, -0.948104f, + -9.165f, 0.699107f, 1.24498f, -8.8777f, -0.517148f, + -0.699107f, -9.57681f, 0.507571f, 0.641646f, -9.65342f, + -0.229843f, -0.565032f, -9.55765f, 0.287304f, 0.47884f, + -8.91601f, -0.201113f, -0.833182f, -9.69173f, 0.134075f, + 0.411803f, -9.47146f, 0.162806f, 0.172383f, -9.5385f, + -0.21069f, 0.143652f, -9.30866f, 0.497994f, -0.105345f, + -9.8258f, 0.507571f, 0.507571f, -9.50977f, -0.248997f, + 0.383072f, -9.60554f, 0.641646f, 0.948104f, -9.27993f, + -0.220267f, -0.0766145f, -10.0844f, 0.430956f, 0.986411f, + -9.52892f, -0.00957681f, 0.517148f, -9.02135f, 0.411803f, + 1.43652f, -9.42358f, -0.00957681f, -0.258574f, -9.27035f, + 1.54187f, 0.45011f, -9.84496f, -0.995988f, 0.316035f, + -9.8258f, -0.402226f, 0.842759f, -8.93516f, 0.967257f, + -0.785298f, -8.94474f, 2.63362f, 0.545878f, -9.25119f, + -2.78685f, 0.0383072f, -7.71891f, 5.74608f, 0.909797f, + -9.34696f, -5.07571f, -0.651223f, -8.63828f, 4.58729f, + 0.430956f, -8.69574f, -4.29041f, -1.16837f, -7.39329f, + 7.83383f, 0.612916f, -7.62314f, -7.28795f, -0.229843f, + -6.17704f, 7.59441f, 1.89621f, -5.58328f, -7.56568f, + 0.153229f, -5.53539f, 8.00621f, 0.967257f, -4.83629f, + -7.9679f, 0.411803f, -4.95121f, 8.04452f, 0.248997f, + -4.46279f, -8.20732f, 0.201113f, -4.99909f, 8.42759f, + 0.105345f, -4.89375f, -8.30309f, -0.0287304f, -4.52983f, + 8.5042f, 0.306458f, -4.72137f, -8.5042f, 0.0f, + -4.36702f, 8.72447f, 0.0f, -4.43406f, -8.68616f, + 0.181959f, -4.15633f, 8.8777f, 0.430956f, -3.98395f, + -9.02135f, 0.584185f, -4.14676f, 8.68616f, 0.0670376f, + -3.9648f, -8.85855f, 1.09176f, -4.18506f, 8.84897f, + -0.114922f, -4.35745f, -8.77236f, 0.248997f, -4.22337f, + 8.07325f, 0.325611f, -3.67749f, -8.5042f, 1.37906f, + -9.15543f, 3.87861f, 2.11647f, -9.27993f, -2.25055f, + -1.5706f, -9.31823f, 0.0670376f, 1.47483f, -10.1897f, + -0.0766145f, -0.354342f, -9.24162f, -0.162806f, 0.0670376f, + -9.81623f, 0.325611f, -1.0343f, -5.88016f, 7.79552f, + 1.65679f, -8.16902f, -5.56412f, -2.83473f, -8.38928f, + 4.31914f, 1.39821f, -8.81066f, -4.41491f, -1.08218f, + -8.82982f, 4.46279f, 0.986411f, -8.61913f, -4.73094f, + -0.727837f, -8.06367f, 3.85945f, 1.38864f, -8.16902f, + -3.98395f, -0.766145f, -8.73405f, 3.92649f, 1.63763f, + -8.71489f, -4.10845f, -1.61848f, -8.91601f, 3.36146f, + 2.04944f, -9.08839f, -3.47638f, -1.97282f, -8.82024f, + 3.40934f, 2.29843f, -8.83939f, -3.66792f, -2.24097f, + -8.88728f, 3.553f, 2.17394f, -8.84897f, -3.78284f, + -2.21224f, -8.73405f, 4.01268f, 2.21224f, -8.74362f, + -4.22337f, -2.07817f, -8.63828f, 3.90734f, 2.20267f, + -8.97347f, -3.77326f, -1.87705f, -8.39886f, 4.48195f, + 2.08774f, -9.06924f, -4.30956f, -1.71425f, -7.44118f, + 6.41646f, 1.83875f, -7.72848f, -6.76123f, -1.05345f, + -6.08127f, 7.51779f, 1.35991f, -4.92248f, -7.63272f, + 0.0766145f, -6.33027f, 7.44118f, 1.49398f, -6.03339f, + -7.42203f, -0.430956f, -6.13873f, 7.53695f, 1.42694f, + -6.27281f, -7.45076f, -0.90022f, -6.17704f, 7.54652f, + 1.37906f, -6.14831f, -7.51779f, -0.42138f, -6.06212f, + 7.56568f, 1.47483f, -6.2345f, -7.46033f, -0.316035f, + -6.02381f, 7.67102f, 1.49398f, -6.22492f, -7.50822f, + -0.497994f, -5.67905f, 7.85298f, 1.71425f, -6.03339f, + -7.57525f, -1.05345f, -5.06613f, 8.05409f, 1.83875f, + -4.82671f, -7.97748f, -0.565032f, -4.54898f, 8.23605f, + 1.99198f, -4.42448f, -8.42759f, -1.06303f, -4.24253f, + 8.7532f, 2.17394f, -4.40533f, -8.81066f, -2.05901f, + -3.44765f, 9.10754f, 1.92494f, -3.01669f, -9.39485f, + -0.68953f, -3.055f, 8.68616f, 2.11647f, -3.4285f, + -8.73405f, -1.3216f, -2.72939f, 8.88728f, 2.11647f, + -2.61447f, -9.02135f, -1.21625f, -2.55701f, 9.38527f, + 2.30801f, -2.15478f, -9.663f, -2.33674f, -2.48039f, + 9.23204f, 2.2314f, -1.53229f, -9.71088f, -1.13964f, + -3.66792f, 8.72447f, 2.24097f, -2.29843f, -8.88728f, + -2.31759f, -8.54251f, 3.89776f, 1.75256f, -9.05966f, + -2.90177f, -2.06859f, -9.29908f, 2.04944f, 1.6089f, + -9.86411f, -1.71425f, -1.16837f, -10.2855f, 1.29287f, + 0.766145f, -10.1993f, -1.1971f, -0.373495f, -9.89284f, + 1.1971f, 0.995988f, -9.14585f, -1.48441f, -0.201113f, + -9.43316f, 0.306458f, 1.45567f, -9.19373f, -0.6608f, + -0.727837f, -9.15543f, -0.0287304f, 0.047884f, -9.40442f, + 0.0287304f, 0.392649f, -9.9503f, -0.948104f, 0.0287304f, + -10.1323f, 1.06303f, -0.47884f, -10.0078f, -0.45011f, + 0.23942f, -9.52892f, 0.287304f, -0.191536f, -9.45231f, + -0.545878f, 0.42138f, -9.52892f, 0.354342f, -0.584185f, + -9.86411f, -0.258574f, 0.699107f, -9.44273f, 0.0f, + -0.42138f, -8.4659f, 3.95522f, 0.354342f, -8.57124f, + -4.1276f, 0.430956f, -8.71489f, 4.04141f, 0.306458f, + -8.95431f, -3.9648f, -0.603339f, -8.89685f, 3.58173f, + 0.354342f, -8.52336f, -3.85945f, 0.258574f, -9.35654f, + 3.54342f, -0.785298f, -9.02135f, -3.69665f, 0.92895f, + -8.76278f, 2.84431f, -1.17795f, -8.56167f, -2.806f, + 2.07817f, -8.89685f, 3.13162f, -1.49398f, -8.5042f, + -3.16035f, 2.03028f, -9.09797f, 4.00311f, -0.995988f, + -9.71088f, -3.79242f, 2.70066f, -9.04051f, 3.58173f, + -1.01514f, -8.04452f, -3.64876f, 1.81002f, -7.86256f, + 4.94163f, -0.201113f, -7.46991f, -5.02782f, 1.81959f, + -7.41245f, 6.46434f, -0.47884f, -7.44118f, -6.31112f, + 0.976834f, -6.57927f, 6.68461f, -0.114922f, -6.36858f, + -6.40688f, 2.35589f, -6.02381f, 7.31668f, -0.469264f, + -5.43005f, -7.24007f, 2.43251f, -6.87615f, 7.48906f, + -0.536301f, -7.03895f, -7.15387f, 0.90022f, -5.9855f, + 7.72848f, -0.201113f, -5.78439f, -7.47949f, 1.13964f, + -6.06212f, 7.9296f, -0.268151f, -5.25767f, -7.76679f, + 1.63763f, -5.70778f, 8.29351f, -0.162806f, -4.72137f, + -8.14029f, 1.20668f, -5.29597f, 8.42759f, 0.143652f, + -4.75967f, -8.42759f, 0.603339f, -5.11401f, 8.44674f, + 0.565032f, -4.85544f, -8.43717f, -0.00957681f, -5.43963f, + 8.23605f, 0.919373f, -5.1619f, -8.05409f, -0.325611f, + -5.60243f, 8.0924f, 0.718261f, -5.48751f, -7.86256f, + -0.047884f, -5.84185f, 7.98706f, 1.11091f, -5.58328f, + -7.91044f, 0.162806f, -5.79397f, 7.8434f, 1.16837f, + -5.47793f, -7.69975f, -0.392649f, -5.78439f, 7.77637f, + 1.36948f, -5.63116f, -7.61356f, -0.651223f, -5.95677f, + 7.73806f, 1.55144f, -5.19063f, -7.69975f, -0.833182f, + -6.22492f, 7.5561f, 1.49398f, -5.46836f, -7.53695f, + -0.833182f, -6.87615f, 6.98149f, 1.25456f, -6.53138f, + -6.82826f, -0.871489f, -7.40287f, 6.03339f, 0.6608f, + -6.67503f, -5.9855f, 0.344765f, -8.00621f, 4.66391f, + 0.574608f, -7.71891f, -4.67348f, 0.641646f, -9.48104f, + 2.24097f, 1.0343f, -9.77792f, -2.03028f, -0.995988f, + -9.76834f, 1.30245f, 1.05345f, -9.72046f, -1.25456f, + -0.593762f, -9.47146f, 0.507571f, 1.1971f, -10.4675f, + -0.459687f, -0.804452f, -9.67257f, 0.201113f, 1.15879f, + -9.60554f, -0.383072f, -1.13006f, -9.42358f, -0.0191536f, + 1.08218f, -10.0844f, -0.0574608f, -0.823605f, -7.12514f, + 6.99107f, -0.488417f, -7.20176f, -6.6463f, 1.63763f, + -7.16345f, 6.86657f, -0.430956f, -7.46991f, -6.47392f, + 0.823605f, -7.09641f, 7.1443f, -0.804452f, -6.6463f, + -7.00065f, 1.76213f, -7.50822f, 6.62715f, -0.277727f, + -5.86101f, -7.06768f, 0.986411f, -7.2688f, 7.23049f, + -0.47884f, -7.28795f, -6.97192f, 1.51314f, -7.37414f, + 6.62715f, -0.287304f, -7.24964f, -6.39731f, 0.995988f, + -7.40287f, 6.56969f, -0.392649f, -7.11557f, -6.44519f, + 1.14922f, -7.3071f, 6.8953f, -0.584185f, -6.56011f, + -6.91445f, 1.78129f, -7.51779f, 6.78038f, -0.612916f, + -5.74608f, -7.02938f, 3.48596f, -7.24007f, 6.33985f, + -0.325611f, -6.8953f, -6.03339f, 0.536301f, -8.99262f, + 5.01825f, -0.258574f, -9.73961f, -4.56814f, 0.632069f, + -9.79707f, 1.66636f, 0.287304f, -9.21289f, -1.87705f, + -0.105345f, -9.77792f, 1.10133f, 0.995988f, -8.88728f, + -1.47483f, -0.335188f, -9.44273f, 1.24498f, 0.497994f, + -9.44273f, -1.34075f, -0.268151f, -9.7875f, 1.0726f, + 0.68953f, -9.39485f, -1.27372f, -0.162806f, -8.86812f, + 2.24097f, 0.545878f, -8.61913f, -2.47082f, 0.632069f, + -9.0022f, 2.02071f, 0.718261f, -9.36612f, -2.12605f, + -0.440533f, -9.22246f, 2.29843f, 1.05345f, -9.10754f, + -2.46124f, -0.402226f, -9.55765f, 2.32716f, 0.842759f, + -9.19373f, -2.50912f, -0.497994f, -8.95431f, 2.62405f, + 1.0726f, -9.15543f, -2.73897f, -0.737414f, -9.54808f, + 2.34632f, 1.11091f, -9.05966f, -2.55701f, -0.440533f, + -10.0556f, -0.746991f, 1.15879f, -8.90643f, 1.48441f, + -1.74298f, -8.53294f, -2.1452f, 2.67193f, -9.15543f, + 2.84431f, -1.62806f, -8.94474f, 1.81959f, 0.42138f, + -9.30866f, -1.75256f, -0.746991f, -9.92157f, 2.12605f, + 0.670376f, -9.35654f, -2.24097f, -0.699107f, -9.49062f, + 2.12605f, 1.25456f, -8.91601f, -2.36547f, -0.411803f, + -8.86812f, 2.40378f, 0.948104f, -8.95431f, -2.47082f, + -0.871489f, -8.90643f, 2.65278f, 1.49398f, -8.95431f, + -2.88262f, -1.18752f, -8.95431f, 3.15077f, 1.25456f, + -9.05966f, -3.34231f, -1.10133f, -9.02135f, 2.9305f, + 1.25456f, -9.03093f, -3.26569f, -1.0726f, -9.32781f, + 2.87304f, 1.0726f, -8.97347f, -3.26569f, -0.794875f, + -9.1267f, 2.94966f, 1.10133f, -9.06924f, -3.20823f, + -0.679953f, -9.06924f, 3.01669f, 1.01514f, -8.98304f, + -3.21781f, -0.507571f, -9.165f, 3.18908f, 0.555455f, + -9.03093f, -3.49553f, -0.354342f, -9.04051f, 3.32315f, + 0.344765f, -9.05966f, -3.48596f, -0.181959f, -8.76278f, + 3.02627f, 0.708684f, -8.90643f, -3.23696f, -0.248997f, + -8.85855f, 2.79643f, 0.641646f, -8.90643f, -2.96881f, + -0.306458f, -8.92558f, 2.7677f, 0.833182f, -8.91601f, + -3.02627f, -0.430956f, -8.94474f, 2.86347f, 1.00556f, + -8.86812f, -3.16035f, -0.565032f, -8.98304f, 2.94966f, + 1.1971f, -9.07881f, -3.20823f, -0.766145f, -8.89685f, + 2.92093f, 1.12049f, -8.89685f, -3.09331f, -0.842759f, + -8.83939f, 2.97839f, 0.967257f, -8.85855f, -3.1795f, + -0.919373f, -8.93516f, 3.15077f, 1.42694f, -8.90643f, + -3.43807f, -0.948104f, -8.99262f, 3.20823f, 1.33118f, + -8.92558f, -3.43807f, -1.0726f, -8.86812f, 3.01669f, + 1.52271f, -8.77236f, -3.33273f, -1.08218f, -8.81066f, + 3.23696f, 1.50356f, -8.82024f, -3.4668f, -1.13964f, + -8.86812f, 3.41892f, 1.40779f, -8.90643f, -3.62961f, + -1.06303f, -8.82982f, 3.38061f, 1.55144f, -8.79151f, + -3.62003f, -1.08218f, -8.82024f, 3.12204f, 1.67594f, + -8.82024f, -3.41892f, -1.15879f, -8.73405f, 3.25611f, + 1.75256f, -8.72447f, -3.4285f, -1.28329f, -8.79151f, + 3.32315f, 1.96325f, -8.78193f, -3.5913f, -1.55144f, + -8.71489f, 3.27527f, 2.02071f, -8.73405f, -3.48596f, + -1.67594f, -8.82024f, 3.16035f, 2.02071f, -8.7532f, + -3.41892f, -1.62806f, -8.73405f, 3.40934f, 1.90578f, + -8.74362f, -3.62003f, -1.38864f, -8.74362f, 3.41892f, + 1.93451f, -8.68616f, -3.66792f, -1.45567f, -8.70532f, + 3.40934f, 1.99198f, -8.68616f, -3.62961f, -1.78129f, + -8.69574f, 3.56257f, 1.93451f, -8.72447f, -3.77326f, + -1.45567f, -8.79151f, 3.45723f, 2.13563f, -8.74362f, + -3.68707f, -1.54187f, -8.79151f, 3.25611f, 2.03986f, + -8.65743f, -3.62003f, -1.6089f, -8.80109f, 3.32315f, + 1.92494f, -8.69574f, -3.5913f, -1.88663f, -8.99262f, + 3.13162f, 1.91536f, -8.63828f, -3.50511f, -1.42694f, + -8.69574f, 3.19865f, 2.22182f, -8.86812f, -3.43807f, + -1.80044f, -8.89685f, 2.61447f, 2.05901f, -8.7532f, + -2.85389f, -1.39821f, -9.32781f, 2.38462f, 2.08774f, + -8.85855f, -2.67193f, -1.5706f, -9.72046f, 1.13006f, + 1.86748f, -9.03093f, -0.756568f, -1.0343f, -10.3334f, + 0.42138f, -1.53229f, -9.57681f, -0.220267f, 1.26414f, + -8.95431f, -0.383072f, 0.201113f, -9.73961f, 0.651223f, + -0.565032f, -10.3334f, -0.651223f, -0.0574608f, -9.68215f, + 0.536301f, 1.02472f, -9.56723f, -0.823605f, -0.296881f, + -9.58638f, 0.890643f, 0.0287304f, -9.50977f, -0.957681f, + -0.0957681f, -9.54808f, 0.890643f, 0.0861913f, -9.72046f, + -1.04387f, -0.248997f, -9.35654f, 1.00556f, 0.335188f, + -9.47146f, -0.948104f, -0.325611f, -9.45231f, 0.90022f, + 0.0383072f, -9.70131f, -0.814029f, -0.191536f, -9.51935f, + 0.756568f, 0.335188f, -9.69173f, -0.861913f, -0.0383072f, + -9.58638f, 0.775721f, 0.306458f, -9.73004f, -0.986411f, + 0.00957681f, -9.47146f, 0.833182f, 0.258574f, -9.64384f, + -0.766145f, -0.287304f, -9.5385f, 0.699107f, 0.335188f, + -9.60554f, -0.842759f, -0.153229f, -9.5385f, 0.785298f, + 0.402226f, -9.73961f, -0.890643f, -0.191536f, -9.43316f, + 0.785298f, 0.411803f, -9.663f, -0.737414f, -0.392649f, + -9.56723f, 0.775721f, 0.335188f, -9.60554f, -0.766145f, + -0.287304f, -9.49062f, 0.679953f, 0.344765f, -9.67257f, + -0.785298f, -0.201113f, -9.44273f, 0.699107f, 0.316035f, + -9.62469f, -0.737414f, -0.220267f, -9.54808f, 0.679953f, + 0.440533f, -9.96946f, -0.497994f, -0.392649f, -9.61511f, + 0.440533f, 0.363919f, -9.46189f, -0.383072f, -0.383072f, + -9.48104f, 0.306458f, 0.565032f, -9.69173f, -1.0726f, + -0.766145f, -9.05008f, 0.909797f, 0.775721f, -9.63427f, + -0.430956f, -0.737414f, -9.54808f, 0.344765f, 0.718261f, + -9.58638f, -0.383072f, -0.229843f, -9.5385f, 0.172383f, + 0.632069f, -9.62469f, -0.335188f, -0.545878f, -9.52892f, + 0.306458f, 0.622492f, -9.48104f, -0.383072f, -0.392649f, + -9.44273f, 0.23942f, 0.68953f, -9.70131f, -0.344765f, + -0.354342f, -9.59596f, 0.229843f, 0.565032f, -9.40442f, + -0.392649f, -0.497994f, -9.43316f, 0.248997f, 0.555455f, + -9.34696f, -0.373495f, -0.220267f, -9.34696f, 0.181959f, + 0.392649f, -10.4579f, 0.0670376f, 0.181959f, -9.5385f, + -0.229843f, 0.296881f, -9.29908f, -0.0287304f, -0.42138f, + -9.45231f, 0.00957681f, 0.565032f, -9.84496f, -0.0766145f, + 0.105345f, -9.64384f, -0.0574608f, 0.277727f, -9.67257f, + -0.21069f, -0.306458f, -9.29908f, 0.047884f, 0.469264f, + -9.64384f, -0.248997f, 0.114922f, -9.52892f, 0.0191536f, + 0.201113f, -9.64384f, -0.411803f, -0.0861913f, -9.67257f, + 0.248997f, 0.0670376f, -9.73004f, -0.383072f, -0.00957681f, + -9.59596f, 0.268151f, -0.047884f, -9.77792f, -0.162806f, + 0.0766145f, -9.68215f, 0.00957681f, 0.153229f, -9.68215f, + -0.0957681f, 0.143652f, -9.50977f, -0.0957681f, 0.23942f, + -9.60554f, -0.316035f, 0.0f, -9.43316f, 0.124498f, + 0.134075f, -9.52892f, -0.47884f, -0.134075f, -9.50019f, + 0.316035f, -0.00957681f, -9.88326f, -0.23942f, -0.0670376f, + -9.5385f, 0.0861913f, 0.316035f, -9.60554f, -0.0766145f, + 0.220267f, -9.62469f, -0.00957681f, -0.172383f, -9.74919f, + -0.00957681f, 0.0766145f, -9.43316f, -0.105345f, 0.0957681f, + -9.69173f, -0.0670376f, 0.00957681f, -9.51935f, -0.0383072f, + -0.0383072f, -9.71088f, 0.0191536f, 0.0766145f, -9.50977f, + -0.0957681f, 0.0766145f, -9.56723f, -0.105345f, 0.0861913f, + -9.2895f, -0.114922f, 0.153229f, -9.71088f, -0.162806f, + 0.0861913f, -9.50019f, 0.0287304f, 0.0861913f, -9.64384f, + -0.0191536f, 0.287304f, -9.50977f, -0.134075f, -0.0383072f, + -9.50019f, 0.143652f, 0.21069f, -9.44273f, -0.23942f, + -0.344765f, -9.64384f, -0.0287304f, 0.172383f, -9.48104f, + -0.0574608f, -0.0957681f, -9.69173f, -0.181959f, 0.201113f, + -9.48104f, 0.114922f, -0.0574608f, -9.75877f, -0.0670376f, + 0.0191536f, -9.55765f, 0.0383072f, 0.172383f, -9.61511f, + -0.0574608f, 0.268151f, -9.24162f, -0.0957681f, -0.0574608f, + -9.56723f, 0.047884f, 0.325611f, -9.51935f, -0.134075f, + -0.459687f, -9.47146f, 0.0f, 0.622492f, -9.49062f, + -0.0670376f, -0.488417f, -9.59596f, 0.0f, 0.823605f, + -9.48104f, -0.0383072f, -0.574608f, -9.5385f, -0.335188f, + 0.641646f, -9.54808f, 0.296881f, -0.536301f, -9.48104f, + -0.363919f, 0.641646f, -9.50977f, 0.287304f, -0.45011f, + -9.46189f, -0.047884f, 1.13964f, -9.57681f, 0.0f, + -0.632069f, -9.57681f, -0.316035f, 0.909797f, -9.63427f, + 0.258574f, -0.517148f, -9.64384f, -0.344765f, 0.545878f, + -9.59596f, 0.296881f, -0.440533f, -9.54808f, -0.0574608f, + 0.746991f, -9.59596f, -0.0383072f, -0.296881f, -9.49062f, + 0.00957681f, 0.852336f, -9.46189f, -0.124498f, -0.21069f, + -9.57681f, 0.0766145f, 0.641646f, -9.37569f, -0.181959f, + -0.42138f, -9.70131f, 0.344765f, 0.737414f, -9.24162f, + -0.469264f, -0.794875f, -9.47146f, 0.0f, 0.699107f, + -9.76834f, 0.0287304f, -0.746991f, -9.48104f, -0.153229f, + 1.33118f, -9.36612f, 0.0957681f, -0.948104f, -9.74919f, + -0.201113f, 1.10133f, -9.35654f, 0.181959f, -0.909797f, + -9.54808f, 0.0957681f, 0.881066f, -9.73961f, 0.153229f, + -1.05345f, -9.49062f, -0.306458f, 1.04387f, -9.51935f, + 0.584185f, -0.766145f, -9.93115f, -0.814029f, 0.727837f, + -9.75877f, 1.0726f, -0.316035f, -9.72046f, -0.296881f, + 0.162806f, -9.47146f, 0.392649f, 0.0766145f, -9.40442f, + 0.21069f, 0.287304f, -9.37569f, -0.248997f, 0.536301f, + -9.5385f, 0.0861913f, 0.114922f, -9.40442f, -0.0287304f, + -0.0383072f, -10.0461f, 0.181959f, -0.00957681f, -9.32781f, + -0.181959f, 0.622492f, -9.46189f, 0.296881f, -0.201113f, + -9.35654f, -0.201113f, 0.201113f, -9.31823f, -0.402226f, + 0.21069f, -9.91199f, 0.517148f, 1.01514f, -9.87369f, + 0.047884f, -0.047884f, -9.56723f, 0.248997f, -0.114922f, + -9.76834f, -0.335188f, 0.0383072f, -9.02135f, 0.316035f, + 0.105345f, -9.5385f, -0.335188f, 0.0287304f, -9.59596f, + 0.344765f, 0.670376f, -9.70131f, 0.0287304f, -0.383072f, + -10.4579f, 0.402226f, 0.411803f, -10.4291f, -0.45011f, + 0.306458f, -9.44273f, 0.545878f, 0.430956f, -9.79707f, + 0.507571f, -0.679953f, -9.26077f, -0.469264f, 1.26414f, + -9.51935f, 0.775721f, -0.114922f, -9.19373f, -0.718261f, + 0.718261f, -9.68215f, 0.881066f, -0.316035f, -9.01178f, + -0.890643f, 0.938527f, -9.25119f, 1.04387f, -0.861913f, + -8.76278f, -0.881066f, -0.823605f, -9.71088f, 0.354342f, + -0.181959f, -9.32781f, -0.248997f, -0.0957681f, -10.4387f, + 0.995988f, -0.268151f, -10.2376f, -0.699107f, 0.536301f, + -9.98861f, 0.555455f, -0.0574608f, -9.49062f, -0.459687f, + 0.823605f, -9.79707f, 0.316035f, 0.268151f, -8.85855f, + -0.488417f, -0.574608f, -9.663f, 0.373495f, -0.287304f, + -9.42358f, 0.0191536f, -1.65679f, -9.42358f, 1.0726f, + 1.80044f, -9.63427f, -0.21069f, -1.66636f, -9.31823f, + 0.306458f, 2.83473f, -9.17458f, 0.814029f, -2.98796f, + -8.67659f, 0.143652f, 1.7334f, -9.31823f, 1.23541f, + -1.15879f, -9.13627f, -1.75256f, 0.785298f, -8.80109f, + 2.54743f, -0.0766145f, -9.91199f, -0.134075f, 1.21625f, + -9.72046f, 0.488417f, 0.363919f, -9.14585f, -0.277727f, + 1.0343f, -9.21289f, 0.718261f, -0.143652f, -9.48104f, + -0.296881f, -0.114922f, -9.2895f, 0.565032f, 0.565032f, + -10.2663f, 0.459687f, -0.143652f, -9.56723f, -0.105345f, + 0.459687f, -10.094f, 0.68953f, -0.306458f, -9.59596f, + -0.172383f, 0.957681f, -10.094f, 0.0861913f, -0.220267f, + -9.34696f, 0.191536f, 0.392649f, -9.79707f, -0.181959f, + -0.488417f, -9.55765f, 0.555455f, 1.0343f, -10.1227f, + 0.0191536f, -0.976834f, -9.40442f, 0.354342f, 0.871489f, + -9.69173f, 0.593762f, -0.296881f, -9.14585f, -0.517148f, + 1.31202f, -9.69173f, 0.861913f, -0.775721f, -9.07881f, + -0.68953f, 0.497994f, -9.90242f, 0.919373f, 0.00957681f, + -9.43316f, -0.68953f, 0.325611f, -9.79707f, 0.507571f, + 0.114922f, -9.40442f, -0.316035f, 0.430956f, -9.8258f, + 0.536301f, -0.0191536f, -9.32781f, -0.258574f, 0.258574f, + -9.93115f, 0.383072f, 0.143652f, -9.48104f, -0.181959f, + 0.6608f, -9.55765f, 0.0861913f, -0.0383072f, -9.37569f, + 0.0287304f, 0.430956f, -9.39485f, 0.325611f, 0.0287304f, + -9.32781f, -0.0861913f, 0.392649f, -9.50019f, 0.651223f, + 0.23942f, -9.40442f, -0.469264f, 0.545878f, -9.75877f, + 0.536301f, 0.0574608f, -9.38527f, -0.411803f, 0.47884f, + -9.87369f, 0.574608f, 0.0383072f, -9.54808f, -0.402226f, + 0.258574f, -9.65342f, 0.325611f, 0.23942f, -9.56723f, + -0.220267f, 0.6608f, -9.50977f, 0.134075f, 0.0766145f, + -9.38527f, -0.047884f, 0.536301f, -9.70131f, 0.0f, + -0.42138f, -9.35654f, 0.181959f, 0.881066f, -9.71088f, + 0.181959f, -0.402226f, -9.50019f, -0.00957681f, 0.727837f, + -9.49062f, 0.306458f, -0.0766145f, -9.27993f, -0.268151f, + 0.766145f, -9.73961f, 0.181959f, -0.517148f, -9.49062f, + -0.0287304f, 0.986411f, -9.86411f, 0.0383072f, -0.383072f, + -9.47146f, 0.0383072f, 0.986411f, -9.50977f, 0.402226f, + -0.383072f, -9.10754f, -0.363919f, 0.823605f, -10.0365f, + 0.90022f, -0.497994f, -9.59596f, -0.651223f, 0.833182f, + -9.73961f, 0.517148f, -0.0957681f, -9.31823f, -0.440533f, + 0.641646f, -9.56723f, 0.0191536f, -0.114922f, -9.33739f, + -0.047884f, 0.593762f, -9.67257f, -0.23942f, -0.459687f, + -9.51935f, 0.258574f, 0.794875f, -9.39485f, 0.0574608f, + -0.172383f, -9.29908f, -0.0574608f, 0.440533f, -10.0078f, + 0.134075f, -0.536301f, -9.45231f, -0.0670376f, 0.766145f, + -10.0748f, -0.0287304f, -0.584185f, -9.55765f, -0.0766145f, + 1.06303f, -9.73961f, 0.392649f, -0.402226f, -9.50019f, + -0.316035f, 1.35991f, -9.75877f, 0.229843f, -0.373495f, + -9.51935f, -0.248997f, 1.39821f, -10.2855f, 0.191536f, + -0.181959f, -10.1514f, -0.124498f, 1.23541f, -10.0461f, + 0.105345f, -0.440533f, -9.88326f, 0.0574608f, -0.0191536f, + -9.60554f, -0.201113f, 0.0957681f, -9.33739f, 0.047884f, + -0.248997f, -9.29908f, -0.23942f, 0.373495f, -9.04051f, + -0.0861913f, -0.00957681f, -9.24162f, -0.114922f, 1.78129f, + -9.414f, -0.124498f, -1.16837f, -9.68215f, -0.181959f, + 1.35033f, -9.60554f, 0.0191536f, -1.4461f, -9.19373f, + -0.220267f, 1.84832f, -9.23204f, -0.00957681f, -1.70467f, + -9.11712f, -0.181959f, 1.50356f, -8.74362f, -0.143652f, + -1.97282f, -8.89685f, 0.143652f, 1.88663f, -8.90643f, + -0.373495f, -1.25456f, -8.81066f, -0.124498f, 1.31202f, + -8.79151f, -0.134075f, -0.92895f, -8.99262f, -0.536301f, + 0.430956f, -9.31823f, 0.373495f, -0.181959f, -10.2855f, + -0.153229f, 0.708684f, -10.5536f, 0.229843f, -0.105345f, + -10.2855f, -0.220267f, -0.105345f, -9.95988f, 0.296881f, + -0.162806f, -9.79707f, -0.0861913f, 0.536301f, -9.39485f, + -0.124498f, -0.392649f, -10.2759f, 0.047884f, 1.09176f, + -9.61511f, -0.191536f, -0.517148f, -10.0461f, 0.229843f, + 1.5706f, -9.56723f, -0.430956f, -0.584185f, -9.5385f, + 0.287304f, 0.938527f, -9.49062f, -0.47884f, -0.287304f, + -9.56723f, -0.248997f, 0.497994f, -9.50977f, 0.0766145f, + -0.957681f, -9.79707f, -0.191536f, 0.296881f, -9.40442f, + 0.00957681f, -0.0383072f, -9.61511f, 0.0191536f, 0.268151f, + -9.31823f, -0.201113f, -0.344765f, -9.48104f, 0.45011f, + 0.555455f, -9.29908f, -0.746991f, 0.0191536f, -9.03093f, + 0.248997f, 0.612916f, -8.97347f, -0.459687f, 0.459687f, + -9.11712f, -0.277727f, -0.402226f, -9.0022f, 0.191536f, + 0.191536f, -10.6207f, -0.0766145f, 0.641646f, -10.1897f, + -0.00957681f, 0.344765f, -10.0844f, 0.0574608f, 0.201113f, + -10.1131f, -0.124498f, 0.191536f, -9.38527f, -0.153229f, + -0.0191536f, -9.43316f, -0.0574608f, -0.134075f, -9.42358f, + -0.47884f, 0.172383f, -9.27035f, 0.143652f, 0.21069f, + -10.343f, -0.0383072f, -0.373495f, -9.8258f, 0.0861913f, + 0.316035f, -10.1706f, -0.181959f, -0.143652f, -9.74919f, + 0.114922f, 0.258574f, -9.50977f, -0.430956f, 0.0670376f, + -9.29908f, 0.172383f, 0.344765f, -9.86411f, -0.68953f, + 0.0191536f, -10.0748f, 0.737414f, 0.440533f, -9.91199f, + -0.622492f, -0.430956f, -9.86411f, 0.708684f, 0.335188f, + -9.88326f, -0.392649f, 0.153229f, -9.77792f, 0.354342f, + -0.191536f, -9.60554f, 0.0670376f, 0.0670376f, -9.31823f, + -0.277727f, -0.0957681f, -9.55765f, 0.593762f, 0.153229f, + -9.23204f, -0.852336f, -0.201113f, -9.63427f, 0.42138f, + 0.507571f, -9.42358f, -0.603339f, -0.641646f, -9.64384f, + 0.42138f, 0.718261f, -9.47146f, -0.507571f, -0.995988f, + -9.83538f, 0.134075f, 0.603339f, -9.32781f, -0.172383f, + -0.861913f, -9.60554f, 0.181959f, 1.05345f, -9.72046f, + -0.0574608f, -1.21625f, -9.57681f, -0.00957681f, 1.1971f, + -9.69173f, 0.363919f, -1.31202f, -9.29908f, -0.306458f, + 1.37906f, -9.33739f, 0.766145f, -1.41737f, -9.05008f, + -0.0574608f, 1.09176f, -9.07881f, 0.727837f, -0.861913f, + -9.42358f, -0.785298f, 0.632069f, -9.48104f, 1.01514f, + 0.047884f, -9.69173f, -1.04387f, -0.124498f, -8.99262f, + 1.11091f, 0.325611f, -9.70131f, -0.363919f, -0.325611f, + -9.50019f, 0.737414f, 1.31202f, -9.76834f, -0.162806f, + -1.10133f, -9.68215f, 0.296881f, 1.04387f, -9.77792f, + 0.603339f, -0.0957681f, -9.83538f, -0.47884f, 0.909797f, + -10.4387f, 0.0766145f, -0.459687f, -9.9503f, 0.047884f, + 1.38864f, -9.60554f, -0.584185f, 0.459687f, -9.75877f, + 0.536301f, -0.124498f, -9.74919f, -0.172383f, 0.651223f, + -10.4483f, 0.229843f, -0.268151f, -9.50019f, -1.58975f, + 0.622492f, -9.64384f, 1.58975f, -0.114922f, -8.96389f, + -1.69509f, 1.16837f, -8.72447f, 1.71425f, -1.04387f, + -8.91601f, -0.90022f, 1.92494f, -8.84897f, 1.04387f, + -0.833182f, -8.86812f, -0.0574608f, 1.17795f, -8.91601f, + 0.47884f, -1.47483f, -9.22246f, 1.25456f, 1.76213f, + -8.88728f, -1.42694f, -2.36547f, -10.1227f, 2.24097f, + 2.09732f, -9.09797f, -2.35589f, -3.11246f, -9.84496f, + 2.75812f, 2.1069f, -9.26077f, -2.98796f, -2.33674f, + -9.01178f, 0.0766145f, 4.2138f, -8.45632f, 1.02472f, + -3.69665f, -8.51378f, -0.344765f, 3.95522f, -8.90643f, + 2.00155f, -3.78284f, -9.05966f, -0.497994f, 3.50511f, + -9.42358f, 1.86748f, -3.62003f, -9.68215f, -0.488417f, + 3.74453f, -9.48104f, 1.69509f, -3.18908f, -9.93115f, + -0.871489f, 3.54342f, -9.68215f, 2.03986f, -2.8922f, + -9.85453f, -0.861913f, 3.16035f, -9.81623f, 2.08774f, + -2.66235f, -9.95988f, -0.852336f, 2.74854f, -9.59596f, + 1.83875f, -2.15478f, -10.0652f, -0.622492f, 2.28886f, + -9.5385f, 1.46525f, -2.18351f, -9.67257f, -0.632069f, + 2.01113f, -9.43316f, 1.3216f, -1.67594f, -9.42358f, + -0.679953f, 1.05345f, -9.45231f, 1.5706f, -1.23541f, + -9.2895f, -0.459687f, 1.39821f, -9.5385f, 1.46525f, + -1.16837f, -9.58638f, -0.316035f, 1.47483f, -9.54808f, + 1.20668f, -1.26414f, -9.60554f, -0.411803f, 1.39821f, + -9.31823f, 1.14922f, -1.14922f, -9.76834f, -0.354342f, + 1.35991f, -9.52892f, 1.11091f, -1.35991f, -9.81623f, + 0.0574608f, 1.46525f, -9.663f, 0.833182f, -1.1971f, + -9.80665f, 0.21069f, 1.62806f, -9.70131f, 0.641646f, + -1.24498f, -9.9503f, 0.497994f, 1.53229f, -9.88326f, + 0.325611f, -1.05345f, -9.86411f, 0.565032f, 1.58017f, + -9.87369f, 0.220267f, -1.24498f, -9.94073f, 0.268151f, + 1.97282f, -9.91199f, 0.584185f, -1.35033f, -9.25119f, + 0.306458f, 1.13006f, -9.46189f, 0.383072f, -1.11091f, + -8.97347f, -0.0670376f, 1.22583f, -8.98304f, 0.459687f, + -0.488417f, -9.30866f, -0.737414f, 1.23541f, -9.13627f, + 1.00556f, -0.526724f, -10.6781f, -0.775721f, 0.373495f, + -10.5919f, 1.13964f, 0.42138f, -9.54808f, -2.07817f, + 0.68953f, -9.26077f, 1.82917f, -0.105345f, -9.03093f, + -0.976834f, 0.430956f, -9.47146f, 0.995988f, -0.181959f, + -9.86411f, -0.23942f, 0.124498f, -9.73004f, 0.153229f, + 0.871489f, -9.97903f, -0.220267f, 0.162806f, -9.59596f, + 0.153229f, 0.430956f, -9.8258f, -0.114922f, 0.0957681f, + -9.76834f, 0.00957681f, -0.0287304f, -10.1801f, -0.268151f, + 0.258574f, -10.0844f, 0.23942f, 0.0766145f, -10.1131f, + 0.794875f, 0.0f, -9.86411f, -0.593762f, 0.909797f, + -9.29908f, -2.09732f, 1.72383f, -9.17458f, 1.89621f, + -1.58975f, -8.91601f, -2.16436f, 1.94409f, -9.1267f, + 2.03986f, -1.96325f, -9.30866f, -2.42293f, 2.02071f, + -9.43316f, 2.26013f, -1.38864f, -9.8258f, -2.2697f, + 1.16837f, -9.44273f, 2.16436f, -1.09176f, -9.14585f, + -2.03986f, 1.26414f, -9.01178f, 1.82917f, -1.28329f, + -8.89685f, -2.09732f, 1.64721f, -8.95431f, 1.93451f, + -1.69509f, -8.8777f, -2.19309f, 1.28329f, -9.03093f, + 2.11647f, -1.40779f, -9.31823f, -2.2697f, 1.09176f, + -9.11712f, 2.06859f, -1.3216f, -9.2895f, -2.21224f, + 1.4461f, -9.165f, 2.00155f, -1.48441f, -8.98304f, + -2.20267f, 1.46525f, -8.83939f, 2.00155f, -1.24498f, + -9.14585f, -2.26013f, 1.43652f, -9.01178f, 2.1069f, + -1.45567f, -9.1267f, -2.29843f, 1.63763f, -9.04051f, + 2.12605f, -1.76213f, -9.18416f, -2.27928f, 1.9824f, + -9.09797f, 2.07817f, -1.79086f, -9.08839f, -2.00155f, + 1.79086f, -9.44273f, 1.87705f, -1.62806f, -9.14585f, + -2.31759f, 1.84832f, -8.86812f, 2.06859f, 1.61848f, + -9.165f, -2.24097f, 2.05901f, -9.0022f, 2.02071f, + -1.7334f, -9.04051f, -2.1452f, 2.04944f, -9.2895f, + 2.06859f, -1.70467f, -9.20331f, -2.22182f, 2.06859f, + -9.33739f, 2.09732f, -1.76213f, -9.34696f, -2.13563f, + 1.99198f, -9.1267f, 1.9824f, -1.84832f, -8.88728f, + -1.79086f, 1.55144f, -9.03093f, 1.62806f, -1.61848f, + -9.1267f, -1.58975f, 1.47483f, -9.19373f, 1.49398f, + -1.47483f, -8.92558f, -1.48441f, 1.76213f, -8.69574f, + 1.18752f, -1.76213f, -9.24162f, -1.35991f, 1.49398f, + -9.48104f, 1.23541f, -1.61848f, -9.51935f, 1.86748f, + 2.00155f, -8.71489f, -1.24498f, -2.11647f, -5.6982f, + 8.15944f, 1.27372f, -4.52983f, -7.99663f, -0.775721f, + -4.00311f, 8.31267f, 0.632069f, -3.68707f, -8.03494f, + 0.344765f, -2.16436f, 7.79552f, 3.7158f, -1.7334f, + -7.74764f, -4.22337f, -1.56102f, 8.78193f, 4.39575f, + -1.58017f, -8.76278f, -4.5011f, -1.72383f, 9.05008f, + 5.25767f, -1.93451f, -9.11712f, -3.9648f, -0.995988f, + 7.97748f, 5.34386f, -1.33118f, -7.92002f, -4.03184f, + -0.670376f, 9.17458f, 4.3766f, 0.220267f, -9.60554f, + -4.13718f, -0.746991f, 7.33583f, 5.34386f, -1.1971f, + -7.28795f, -5.14275f, 0.871489f, 7.90087f, 5.80354f, + 0.584185f, -8.33182f, -3.04542f, 0.986411f, 7.59441f, + 6.49307f, -0.0670376f, -7.85298f, -5.92804f, 2.07817f, + 8.83939f, 5.4109f, 0.325611f, -9.59596f, -3.83072f, + 0.718261f, 7.38372f, 5.99508f, 0.248997f, -8.29351f, + -5.10444f, 1.72383f, 7.83383f, 5.85143f, 2.12605f, + -9.15543f, -4.03184f, 2.05901f, 7.37414f, 5.79397f, + 2.19309f, -8.49463f, -4.95121f, 2.13563f, 7.91044f, + 4.29999f, 2.1452f, -8.76278f, -2.24097f, 1.31202f, + 8.59997f, 5.72693f, 0.746991f, -9.55765f, -3.54342f, + 1.36948f, 8.5042f, 5.09486f, 1.17795f, -9.62469f, + -4.1276f, 1.77171f, 8.69574f, 5.46836f, 1.63763f, + -9.40442f, -2.32716f, 1.91536f, 7.75721f, 5.25767f, + 2.04944f, -8.81066f, -2.40378f, 0.392649f, 7.73806f, + 5.63116f, 1.45567f, -9.24162f, -1.49398f, -0.258574f, + 6.82826f, 7.34541f, -0.42138f, -9.07881f, -1.30245f, + -0.517148f, 6.97192f, 7.6806f, -0.890643f, -9.58638f, + -4.81713f, -0.21069f, 3.13162f, 9.20331f, -0.967257f, + -10.0748f, 0.181959f, -0.948104f, -5.9855f, 7.4316f, + -1.00556f, -9.5385f, 0.497994f, 0.162806f, -8.47547f, + 4.32872f, 0.248997f, -9.165f, -2.27928f, 0.143652f, + -8.6287f, 4.47237f, 0.354342f, -9.51935f, 0.986411f, }; const size_t kAccelerometerVerticalHingeTestDataLength = - ARRAY_SIZE(kAccelerometerVerticalHingeTestData); + ARRAY_SIZE(kAccelerometerVerticalHingeTestData); const float kAccelerometerVerticalHingeUnstableTestData[] = { - 8.5904f, -1.36948f, -3.74453f, 8.72447f, 1.1971f, 4.00311f, - 8.80109f, -3.08373f, 2.27928f, 8.95431f, -1.90578f, -1.10133f, - 8.93516f, -2.03986f, 0.248997f, 9.05008f, 1.53229f, -0.708684f, - -8.78193f, 1.43652f, -2.63362f, -8.66701f, 0.220267f, 2.79643f, - -8.66701f, -2.06859f, 2.42293f, -8.79151f, -2.88262f, -1.16837f, - 8.74362f, -1.9824f, 3.53384f, 9.04051f, 0.0574608f, -1.36948f, - 8.78193f, -4.1276f, 2.58574f, 8.8777f, 0.201113f, -1.80044f, - 8.70532f, -0.296881f, 1.52271f, 9.02135f, -0.871489f, -2.43251f, - -9.09797f, -1.3216f, -3.60088f, -8.97347f, 2.52828f, 2.6432f, - -8.82024f, 1.87705f, 0.354342f, -7.93917f, -4.38618f, 0.258574f, - -8.81066f, 1.91536f, -2.92093f, -8.04452f, -5.4492f, 3.28484f, - -8.86812f, 2.05901f, 0.890643f, -8.01579f, -5.65989f, -2.20267f, - -9.0022f, 2.18351f, -2.9305f, -8.80109f, -4.01268f, 3.055f, - -9.37569f, -1.04387f, 0.277727f, -6.80911f, 2.806f, -6.0717f, - -8.79151f, -8.79151f, -2.11647f, -8.6287f, -1.53229f, 3.58173f, - -8.97347f, -0.335188f, 1.26414f, 8.5042f, 1.51314f, -2.20267f, - -9.19373f, -1.37906f, 1.41737f, -7.67102f, 2.8922f, -5.09486f, - -8.81066f, 0.986411f, 2.30801f, -8.53294f, 3.26569f, -3.11246f, - -9.03093f, 1.06303f, 1.39821f, -8.8777f, -4.47237f, -0.632069f, - -8.74362f, -1.83875f, -0.0957681f, -7.92002f, 1.0343f, -3.84988f, - -8.92558f, 0.440533f, 1.26414f, -8.71489f, -0.153229f, -3.64876f, + 8.5904f, -1.36948f, -3.74453f, 8.72447f, 1.1971f, 4.00311f, + 8.80109f, -3.08373f, 2.27928f, 8.95431f, -1.90578f, -1.10133f, + 8.93516f, -2.03986f, 0.248997f, 9.05008f, 1.53229f, -0.708684f, + -8.78193f, 1.43652f, -2.63362f, -8.66701f, 0.220267f, 2.79643f, + -8.66701f, -2.06859f, 2.42293f, -8.79151f, -2.88262f, -1.16837f, + 8.74362f, -1.9824f, 3.53384f, 9.04051f, 0.0574608f, -1.36948f, + 8.78193f, -4.1276f, 2.58574f, 8.8777f, 0.201113f, -1.80044f, + 8.70532f, -0.296881f, 1.52271f, 9.02135f, -0.871489f, -2.43251f, + -9.09797f, -1.3216f, -3.60088f, -8.97347f, 2.52828f, 2.6432f, + -8.82024f, 1.87705f, 0.354342f, -7.93917f, -4.38618f, 0.258574f, + -8.81066f, 1.91536f, -2.92093f, -8.04452f, -5.4492f, 3.28484f, + -8.86812f, 2.05901f, 0.890643f, -8.01579f, -5.65989f, -2.20267f, + -9.0022f, 2.18351f, -2.9305f, -8.80109f, -4.01268f, 3.055f, + -9.37569f, -1.04387f, 0.277727f, -6.80911f, 2.806f, -6.0717f, + -8.79151f, -8.79151f, -2.11647f, -8.6287f, -1.53229f, 3.58173f, + -8.97347f, -0.335188f, 1.26414f, 8.5042f, 1.51314f, -2.20267f, + -9.19373f, -1.37906f, 1.41737f, -7.67102f, 2.8922f, -5.09486f, + -8.81066f, 0.986411f, 2.30801f, -8.53294f, 3.26569f, -3.11246f, + -9.03093f, 1.06303f, 1.39821f, -8.8777f, -4.47237f, -0.632069f, + -8.74362f, -1.83875f, -0.0957681f, -7.92002f, 1.0343f, -3.84988f, + -8.92558f, 0.440533f, 1.26414f, -8.71489f, -0.153229f, -3.64876f, }; const size_t kAccelerometerVerticalHingeUnstableTestDataLength = - ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData); + ARRAY_SIZE(kAccelerometerVerticalHingeUnstableTestData); -- cgit v1.2.1 From a953752911223799941cc233ce6a1d342f65c136 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:32:39 -0600 Subject: board/eldrid/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Icdcd738de816cb92e6213944e282581ea28954a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728266 Reviewed-by: Jeremy Bettis --- board/eldrid/led.c | 67 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 32 deletions(-) diff --git a/board/eldrid/led.c b/board/eldrid/led.c index 26526e0b76..8c9166175e 100644 --- a/board/eldrid/led.c +++ b/board/eldrid/led.c @@ -27,36 +27,39 @@ __override const int led_charge_lvl_1 = 5; __override const int led_charge_lvl_2 = 95; __override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_LVL_2] = {{EC_LED_COLOR_AMBER, LED_INDEFINITE} }, - [STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S0_BAT_LOW] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [STATE_DISCHARGE_S3] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_DISCHARGE_S5] = {{LED_OFF, LED_INDEFINITE} }, - [STATE_BATTERY_ERROR] = { - {EC_LED_COLOR_WHITE, 0.4 * LED_ONE_SEC}, - {LED_OFF, 0.4 * LED_ONE_SEC} - }, - [STATE_FACTORY_TEST] = { - {EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} - }, -}; + led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { + [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, + LED_INDEFINITE } }, + [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_WHITE, + 0.4 * LED_ONE_SEC }, + { LED_OFF, 0.4 * LED_ONE_SEC } }, + [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + }; __override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = {{EC_LED_COLOR_WHITE, LED_INDEFINITE} }, - [PWR_LED_STATE_SUSPEND_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 1 * LED_ONE_SEC} }, - [PWR_LED_STATE_SUSPEND_NO_AC] = {{EC_LED_COLOR_WHITE, 1 * LED_ONE_SEC}, - {LED_OFF, 6 * LED_ONE_SEC} }, - [PWR_LED_STATE_OFF] = { - {LED_OFF, LED_INDEFINITE} }, -}; - + led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { + [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, + [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 1 * LED_ONE_SEC } }, + [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, + 6 * LED_ONE_SEC } }, + [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, + }; const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED, @@ -80,10 +83,10 @@ __override void led_set_color_battery(enum ec_led_colors color) side_select_duty = 100; break; default: - /* - * We need to turn off led here since curr.ac won't update - * immediately but led will update every 200ms. - */ + /* + * We need to turn off led here since curr.ac won't + * update immediately but led will update every 200ms. + */ side_select_duty = 50; color = LED_OFF; } -- cgit v1.2.1 From e19fe6918aa1bdc461929350af3eadc89cf523da Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:41:55 -0600 Subject: zephyr/test/drivers/src/test_rules.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I310bdc8f8e89383c83be94c8db181a2d688c3660 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730960 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/test_rules.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/test_rules.c b/zephyr/test/drivers/src/test_rules.c index d0595452c7..d46aa9900d 100644 --- a/zephyr/test/drivers/src/test_rules.c +++ b/zephyr/test/drivers/src/test_rules.c @@ -11,7 +11,7 @@ #include "usb_pd_tcpm.h" static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test, - void *data) + void *data) { ARG_UNUSED(test); ARG_UNUSED(data); -- cgit v1.2.1 From 8fb6caa00a1088633b246bca5116c4b89fc9760e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:08:38 -0600 Subject: include/chipset.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6ac893d9a460de3f9494ea116182f0e3b20dd1df Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730227 Reviewed-by: Jeremy Bettis --- include/chipset.h | 78 +++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 25 deletions(-) diff --git a/include/chipset.h b/include/chipset.h index 840db3aa60..c049452bb8 100644 --- a/include/chipset.h +++ b/include/chipset.h @@ -29,17 +29,18 @@ * I'll compare it myself with the state(s) I want." */ enum chipset_state_mask { - CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */ - CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */ - CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */ - CHIPSET_STATE_ON = 0x08, /* On (S0) */ - CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */ + CHIPSET_STATE_HARD_OFF = 0x01, /* Hard off (G3) */ + CHIPSET_STATE_SOFT_OFF = 0x02, /* Soft off (S5, S4) */ + CHIPSET_STATE_SUSPEND = 0x04, /* Suspend (S3) */ + CHIPSET_STATE_ON = 0x08, /* On (S0) */ + CHIPSET_STATE_STANDBY = 0x10, /* Standby (S0ix) */ /* Common combinations */ - CHIPSET_STATE_ANY_OFF = (CHIPSET_STATE_HARD_OFF | - CHIPSET_STATE_SOFT_OFF), /* Any off state */ + CHIPSET_STATE_ANY_OFF = + (CHIPSET_STATE_HARD_OFF | CHIPSET_STATE_SOFT_OFF), /* Any off + state */ /* This combination covers any kind of suspend i.e. S3 or S0ix. */ - CHIPSET_STATE_ANY_SUSPEND = (CHIPSET_STATE_SUSPEND | - CHIPSET_STATE_STANDBY), + CHIPSET_STATE_ANY_SUSPEND = + (CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY), }; enum critical_shutdown { @@ -138,23 +139,47 @@ static inline int chipset_in_or_transitioning_to_state(int state_mask) return state_mask & CHIPSET_STATE_ANY_OFF; } -static inline void chipset_exit_hard_off(void) { } -static inline void chipset_throttle_cpu(int throttle) { } +static inline void chipset_exit_hard_off(void) +{ +} +static inline void chipset_throttle_cpu(int throttle) +{ +} static inline void chipset_force_shutdown(enum chipset_shutdown_reason reason) { } -static inline void chipset_reset(enum chipset_shutdown_reason reason) { } -static inline void power_interrupt(enum gpio_signal signal) { } -static inline void chipset_handle_espi_reset_assert(void) { } -static inline void chipset_handle_reboot(void) { } -static inline void chipset_reset_request_interrupt(enum gpio_signal signal) { } -static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) { } -static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) { } -static inline void chipset_power_good_interrupt(enum gpio_signal signal) { } -static inline void chipset_watchdog_interrupt(enum gpio_signal signal) { } +static inline void chipset_reset(enum chipset_shutdown_reason reason) +{ +} +static inline void power_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_handle_espi_reset_assert(void) +{ +} +static inline void chipset_handle_reboot(void) +{ +} +static inline void chipset_reset_request_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_warm_reset_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_ap_rst_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_power_good_interrupt(enum gpio_signal signal) +{ +} +static inline void chipset_watchdog_interrupt(enum gpio_signal signal) +{ +} -static inline void init_reset_log(void) { } +static inline void init_reset_log(void) +{ +} #endif /* !CONFIG_AP_POWER_CONTROL */ @@ -215,8 +240,9 @@ void chipset_watchdog_interrupt(enum gpio_signal signal); * @param now Current time * @return Action to take */ -__override_proto enum critical_shutdown board_system_is_idle( - uint64_t last_shutdown_time, uint64_t *target, uint64_t now); +__override_proto enum critical_shutdown +board_system_is_idle(uint64_t last_shutdown_time, uint64_t *target, + uint64_t now); #ifdef CONFIG_CMD_AP_RESET_LOG @@ -239,7 +265,9 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, #else -static inline void report_ap_reset(enum chipset_shutdown_reason reason) { } +static inline void report_ap_reset(enum chipset_shutdown_reason reason) +{ +} test_mockable_static_inline enum ec_error_list get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, @@ -250,4 +278,4 @@ get_ap_reset_stats(struct ap_reset_log_entry *reset_log_entries, #endif /* !CONFIG_CMD_AP_RESET_LOG */ -#endif /* __CROS_EC_CHIPSET_H */ +#endif /* __CROS_EC_CHIPSET_H */ -- cgit v1.2.1 From eefceb00e22c0a3624925d08e11f5467cf253f6e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:54:46 -0600 Subject: board/mrbland/led.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I3886334a9530b8e05a817c4af2d90e336bb221ee Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728707 Reviewed-by: Jeremy Bettis --- board/mrbland/led.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/mrbland/led.c b/board/mrbland/led.c index a8d2fcda30..0ab6a7fe24 100644 --- a/board/mrbland/led.c +++ b/board/mrbland/led.c @@ -38,15 +38,15 @@ enum led_color { LED_GREEN, LED_AMBER, LED_WHITE, - LED_COLOR_COUNT /* Number of colors, not a color itself */ + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; static void led_set_color_battery(enum led_color color) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, - (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_RED) ? BAT_LED_ON : BAT_LED_OFF); gpio_set_level(GPIO_EC_CHG_LED_G_C0, - (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_GREEN) ? BAT_LED_ON : BAT_LED_OFF); if (color == LED_AMBER) { gpio_set_level(GPIO_EC_CHG_LED_R_C0, BAT_LED_ON); gpio_set_level(GPIO_EC_CHG_LED_G_C0, BAT_LED_ON); @@ -56,7 +56,7 @@ static void led_set_color_battery(enum led_color color) static void led_set_color_power(enum led_color color) { gpio_set_level(GPIO_EC_PWRBTN_LED, - (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); + (color == LED_WHITE) ? BAT_LED_ON : BAT_LED_OFF); } void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) @@ -105,13 +105,13 @@ static void board_led_set_battery(void) case PWR_STATE_CHARGE: case PWR_STATE_CHARGE_NEAR_FULL: if (chipset_in_state(CHIPSET_STATE_ON | - CHIPSET_STATE_ANY_SUSPEND | - CHIPSET_STATE_ANY_OFF)) { + CHIPSET_STATE_ANY_SUSPEND | + CHIPSET_STATE_ANY_OFF)) { if (percent <= BATTERY_LEVEL_CRITICAL) { /* battery capa <= 5%, Red */ color = LED_RED; } else if (percent > BATTERY_LEVEL_CRITICAL && - percent < BATTERY_LEVEL_NEAR_FULL) { + percent < BATTERY_LEVEL_NEAR_FULL) { /* 5% < battery capa < 97%, Orange */ color = LED_AMBER; } else { @@ -203,7 +203,7 @@ void led_control(enum ec_led_id led_id, enum ec_led_state state) enum led_color color; if ((led_id != EC_LED_ID_RECOVERY_HW_REINIT_LED) && - (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) + (led_id != EC_LED_ID_SYSRQ_DEBUG_LED)) return; if (state == LED_STATE_RESET) { -- cgit v1.2.1 From f2ea2ddb6eb60eb9bcb374a0ef3f54a84ace91e0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:31:01 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ibac351ace9f6f1a898df925ef0dbd62d1d7a06aa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730729 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h index 8334f5f01d..2340e37eba 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_faulty_snk.h @@ -63,7 +63,7 @@ struct tcpci_faulty_snk_action { }; /* Count of actions which is treated by emulator as infinite */ -#define TCPCI_FAULTY_SNK_INFINITE_ACTION 0 +#define TCPCI_FAULTY_SNK_INFINITE_ACTION 0 /** * @brief Initialise USB-C malfunctioning sink device data structure @@ -74,10 +74,10 @@ struct tcpci_faulty_snk_action { * * @return Pointer to USB-C malfunctioning sink extension */ -struct tcpci_partner_extension *tcpci_faulty_snk_emul_init( - struct tcpci_faulty_snk_emul_data *data, - struct tcpci_partner_data *common_data, - struct tcpci_partner_extension *ext); +struct tcpci_partner_extension * +tcpci_faulty_snk_emul_init(struct tcpci_faulty_snk_emul_data *data, + struct tcpci_partner_data *common_data, + struct tcpci_partner_extension *ext); /** * @brief Add action to perform by USB-C malfunctioning sink extension -- cgit v1.2.1 From ed28cf4307afe22d80ca9b54f0ac2b68c0fd5cf8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:14 -0600 Subject: driver/sync.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1239b62ce13e7a3a86a53f301e82fc079ed152fc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730087 Reviewed-by: Jeremy Bettis --- driver/sync.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/sync.h b/driver/sync.h index bf21987b74..76542b3f46 100644 --- a/driver/sync.h +++ b/driver/sync.h @@ -14,4 +14,4 @@ extern const struct accelgyro_drv sync_drv; void sync_interrupt(enum gpio_signal signal); -#endif /* __CROS_EC_VSYNC_H */ +#endif /* __CROS_EC_VSYNC_H */ -- cgit v1.2.1 From 6231805e9ba8a395f301bbb3e93921587492a606 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:54:02 -0600 Subject: driver/sensorhub_lsm6dsm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6d3abb8f4e90f27b2200128018427137fc20bc86 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730063 Reviewed-by: Jeremy Bettis --- driver/sensorhub_lsm6dsm.c | 134 ++++++++++++++++++++++----------------------- 1 file changed, 64 insertions(+), 70 deletions(-) diff --git a/driver/sensorhub_lsm6dsm.c b/driver/sensorhub_lsm6dsm.c index 7957925bf1..e4f9c28b74 100644 --- a/driver/sensorhub_lsm6dsm.c +++ b/driver/sensorhub_lsm6dsm.c @@ -13,10 +13,10 @@ #include "driver/sensorhub_lsm6dsm.h" #include "driver/stm_mems_common.h" -#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_ACCEL, format, ##args) -static int set_reg_bit_field(const struct motion_sensor_t *s, - uint8_t reg, uint8_t bit_field) +static int set_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg, + uint8_t bit_field) { int tmp; int ret; @@ -29,8 +29,8 @@ static int set_reg_bit_field(const struct motion_sensor_t *s, return st_raw_write8(s->port, s->i2c_spi_addr_flags, reg, tmp); } -static int clear_reg_bit_field(const struct motion_sensor_t *s, - uint8_t reg, uint8_t bit_field) +static int clear_reg_bit_field(const struct motion_sensor_t *s, uint8_t reg, + uint8_t bit_field) { int tmp; int ret; @@ -45,14 +45,13 @@ static int clear_reg_bit_field(const struct motion_sensor_t *s, static inline int enable_sensorhub_func(const struct motion_sensor_t *s) { - return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR, - LSM6DSM_EMBED_FUNC_EN); + return set_reg_bit_field(s, LSM6DSM_CTRL10_ADDR, LSM6DSM_EMBED_FUNC_EN); } static inline int disable_sensorhub_func(const struct motion_sensor_t *s) { return clear_reg_bit_field(s, LSM6DSM_CTRL10_ADDR, - LSM6DSM_EMBED_FUNC_EN); + LSM6DSM_EMBED_FUNC_EN); } /* @@ -65,13 +64,13 @@ static inline int disable_sensorhub_func(const struct motion_sensor_t *s) static inline int enable_ereg_bank_acc(const struct motion_sensor_t *s) { return set_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR, - LSM6DSM_FUNC_CFG_EN); + LSM6DSM_FUNC_CFG_EN); } static inline int disable_ereg_bank_acc(const struct motion_sensor_t *s) { return clear_reg_bit_field(s, LSM6DSM_FUNC_CFG_ACC_ADDR, - LSM6DSM_FUNC_CFG_EN); + LSM6DSM_FUNC_CFG_EN); } static inline int enable_aux_i2c_controller(const struct motion_sensor_t *s) @@ -87,22 +86,21 @@ static inline int disable_aux_i2c_controller(const struct motion_sensor_t *s) } static inline int restore_controller_cfg(const struct motion_sensor_t *s, - int cache) + int cache) { return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CONTROLLER_CFG_ADDR, cache); } -static int enable_i2c_pass_through(const struct motion_sensor_t *s, - int *cache) +static int enable_i2c_pass_through(const struct motion_sensor_t *s, int *cache) { int ret; ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CONTROLLER_CFG_ADDR, cache); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x MCR error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x MCR error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } @@ -115,19 +113,18 @@ static int enable_i2c_pass_through(const struct motion_sensor_t *s, LSM6DSM_CONTROLLER_CFG_ADDR, *cache | LSM6DSM_EXT_TRIGGER_EN); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x MCETEN error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } msleep(10); - ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CONTROLLER_CFG_ADDR, - *cache & ~(LSM6DSM_EXT_TRIGGER_EN - | LSM6DSM_I2C_CONTROLLER_ON)); + ret = st_raw_write8( + s->port, s->i2c_spi_addr_flags, LSM6DSM_CONTROLLER_CFG_ADDR, + *cache & ~(LSM6DSM_EXT_TRIGGER_EN | LSM6DSM_I2C_CONTROLLER_ON)); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x MCC error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x MCC error ret: %d\n", __func__, + s->name, s->type, ret); restore_controller_cfg(s, *cache); return ret; } @@ -137,33 +134,31 @@ static int enable_i2c_pass_through(const struct motion_sensor_t *s, LSM6DSM_I2C_PASS_THRU_MODE); } -static inline int power_down_accel(const struct motion_sensor_t *s, - int *cache) +static inline int power_down_accel(const struct motion_sensor_t *s, int *cache) { int ret; - ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CTRL1_ADDR, cache); + ret = st_raw_read8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR, + cache); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x CTRL1R error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } - return st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CTRL1_ADDR, + return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR, *cache & ~LSM6DSM_XL_ODR_MASK); } static inline int restore_ctrl1(const struct motion_sensor_t *s, int cache) { - return st_raw_write8(s->port, s->i2c_spi_addr_flags, - LSM6DSM_CTRL1_ADDR, cache); + return st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_CTRL1_ADDR, + cache); } static int config_slv0_read(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint16_t reg, uint8_t len) + const uint16_t slv_addr_flags, uint16_t reg, + uint8_t len) { int ret; uint16_t addr_8bit = I2C_STRIP_FLAGS(slv_addr_flags) << 1; @@ -172,16 +167,16 @@ static int config_slv0_read(const struct motion_sensor_t *s, LSM6DSM_SLV0_ADD_ADDR, (addr_8bit | LSM6DSM_SLV0_RD_BIT)); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x SA error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x SA error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } ret = st_raw_write8(s->port, s->i2c_spi_addr_flags, LSM6DSM_SLV0_SUBADD_ADDR, reg); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x RA error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x RA error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } @@ -193,8 +188,8 @@ static int config_slv0_read(const struct motion_sensor_t *s, LSM6DSM_SLV0_CONFIG_ADDR, (len & LSM6DSM_SLV0_NUM_OPS_MASK)); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x CFG error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x CFG error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } @@ -202,16 +197,16 @@ static int config_slv0_read(const struct motion_sensor_t *s, } int sensorhub_config_ext_reg(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint8_t reg, uint8_t val) + const uint16_t slv_addr_flags, uint8_t reg, + uint8_t val) { int ret; int tmp; ret = enable_i2c_pass_through(s, &tmp); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } @@ -227,44 +222,44 @@ int sensorhub_config_slv0_read(const struct motion_sensor_t *s, int ret; if (len <= 0 || len > OUT_XYZ_SIZE) { - CPRINTF("%s: %s type:0x%x Invalid length: %d\n", - __func__, s->name, s->type, len); + CPRINTF("%s: %s type:0x%x Invalid length: %d\n", __func__, + s->name, s->type, len); return EC_ERROR_INVAL; } ret = power_down_accel(s, &tmp_xl_cfg); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x PDXL error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } ret = enable_ereg_bank_acc(s); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x ENERB error ret: %d\n", __func__, + s->name, s->type, ret); goto out_restore_ctrl1; } ret = config_slv0_read(s, slv_addr_flags, reg, len); disable_ereg_bank_acc(s); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x CS0R error ret: %d\n", __func__, + s->name, s->type, ret); goto out_restore_ctrl1; } ret = enable_sensorhub_func(s); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x ENSH error ret: %d\n", __func__, + s->name, s->type, ret); goto out_restore_ctrl1; } ret = enable_aux_i2c_controller(s); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x ENI2CM error ret: %d\n", __func__, + s->name, s->type, ret); disable_sensorhub_func(s); } out_restore_ctrl1: @@ -282,41 +277,40 @@ int sensorhub_slv0_data_read(const struct motion_sensor_t *s, uint8_t *raw) * contents of that register. */ ret = st_raw_read_n_noinc(s->port, s->i2c_spi_addr_flags, - LSM6DSM_SENSORHUB1_REG, - raw, OUT_XYZ_SIZE); + LSM6DSM_SENSORHUB1_REG, raw, OUT_XYZ_SIZE); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x SH1R error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } return EC_SUCCESS; } int sensorhub_check_and_rst(const struct motion_sensor_t *s, - const uint16_t slv_addr_flags, - uint8_t whoami_reg, uint8_t whoami_val, - uint8_t rst_reg, uint8_t rst_val) + const uint16_t slv_addr_flags, uint8_t whoami_reg, + uint8_t whoami_val, uint8_t rst_reg, + uint8_t rst_val) { int ret, tmp; int tmp_controller_cfg; ret = enable_i2c_pass_through(s, &tmp_controller_cfg); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x ENI2C error ret: %d\n", __func__, + s->name, s->type, ret); return ret; } ret = st_raw_read8(s->port, slv_addr_flags, whoami_reg, &tmp); if (ret != EC_SUCCESS) { - CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x WAIR error ret: %d\n", __func__, + s->name, s->type, ret); goto err_restore_controller_cfg; } if (tmp != whoami_val) { - CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n", - __func__, s->name, s->type, ret); + CPRINTF("%s: %s type:0x%x WAIC error ret: %d\n", __func__, + s->name, s->type, ret); ret = EC_ERROR_UNKNOWN; goto err_restore_controller_cfg; } -- cgit v1.2.1 From e4e33c7a5548765a440d56a8359795688be62523 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:41:25 -0600 Subject: board/kindred/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I11502a1f9ccf6340b3d895b374326c65ed6b988c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728531 Reviewed-by: Jeremy Bettis --- board/kindred/board.c | 116 +++++++++++++++++++++++--------------------------- 1 file changed, 53 insertions(+), 63 deletions(-) diff --git a/board/kindred/board.c b/board/kindred/board.c index 78ec2abf0c..7e31c17b74 100644 --- a/board/kindred/board.c +++ b/board/kindred/board.c @@ -46,8 +46,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static int lid_device_id; static int base_device_id; @@ -66,17 +66,16 @@ const int usb_port_enable[CONFIG_USB_PORT_POWER_SMART_PORT_COUNT] = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); static void ppc_interrupt(enum gpio_signal signal) { @@ -137,16 +136,16 @@ static void bc12_interrupt(enum gpio_signal signal) /******************************************************************************/ /* SPI devices */ -const struct spi_device_t spi_devices[] = { -}; +const struct spi_device_t spi_devices[] = {}; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); /******************************************************************************/ /* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ const struct pwm_t pwm_channels[] = { - [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, - [PWM_CH_FAN] = {.channel = 5, .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000}, + [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, .freq = 10000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); @@ -213,23 +212,17 @@ static struct accelgyro_saved_data_t g_bma255_data; static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t base_icm_ref = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(-1), 0, 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t base_icm_ref = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t kx022_lid_accel = { .name = "Lid Accel", @@ -302,7 +295,6 @@ struct motion_sensor_t icm426xx_base_gyro = { .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; - struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { .name = "Lid Accel", @@ -382,7 +374,7 @@ unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); const struct fan_conf fan_conf_0 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_0, /* Use MFT id to control fan */ + .ch = MFT_CH_0, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; @@ -401,38 +393,37 @@ const struct fan_t fans[FAN_CH_COUNT] = { /******************************************************************************/ /* MFT channels. These are logically separate from pwm_channels. */ const struct mft_t mft_channels[] = { - [MFT_CH_0] = {NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN}, + [MFT_CH_0] = { NPCX_MFT_MODULE_1, TCKC_LFCLK, PWM_CH_FAN }, }; BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT); /* ADC channels */ const struct adc_t adc_channels[] = { - [ADC_TEMP_SENSOR_1] = { - "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_2] = { - "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, - [ADC_TEMP_SENSOR_3] = { - "TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT, ADC_READ_MAX+1, 0}, + [ADC_TEMP_SENSOR_1] = { "TEMP_AMB", NPCX_ADC_CH0, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_2] = { "TEMP_CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, + [ADC_TEMP_SENSOR_3] = { "TEMP_WIFI", NPCX_ADC_CH3, ADC_MAX_VOLT, + ADC_READ_MAX + 1, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); const struct temp_sensor_t temp_sensors[] = { - [TEMP_SENSOR_1] = {.name = "Temp1", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_1}, - [TEMP_SENSOR_2] = {.name = "Temp2", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_2}, - [TEMP_SENSOR_3] = {.name = "Temp3", - .type = TEMP_SENSOR_TYPE_BOARD, - .read = get_temp_3v3_30k9_47k_4050b, - .idx = ADC_TEMP_SENSOR_3}, + [TEMP_SENSOR_1] = { .name = "Temp1", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_1 }, + [TEMP_SENSOR_2] = { .name = "Temp2", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_2 }, + [TEMP_SENSOR_3] = { .name = "Temp3", + .type = TEMP_SENSOR_TYPE_BOARD, + .read = get_temp_3v3_30k9_47k_4050b, + .idx = ADC_TEMP_SENSOR_3 }, }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); - /* Hatch Temperature sensors */ /* * TODO(b/124316213): These setting need to be reviewed and set appropriately @@ -442,8 +433,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); /* * TODO(b/202062363): Remove when clang is fixed. */ -#define THERMAL_A \ - { \ +#define THERMAL_A \ + { \ .temp_host = { \ [EC_TEMP_THRESH_WARN] = 0, \ [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ @@ -498,7 +489,6 @@ static void board_gpio_set_pp5000(void) } else if (board_id >= 1) { reset_gpio_flags(GPIO_EN_PP5000_A_V1, GPIO_OUT_LOW); } - } bool board_is_convertible(void) @@ -582,15 +572,14 @@ static void determine_accel_devices(void) if (read_time == 0 && board_is_convertible()) { /* Read g sensor chip id*/ - i2c_read8(I2C_PORT_ACCEL, - KX022_ADDR0_FLAGS, KX022_WHOAMI, &lid_device_id); + i2c_read8(I2C_PORT_ACCEL, KX022_ADDR0_FLAGS, KX022_WHOAMI, + &lid_device_id); /* Read gyro sensor id*/ - i2c_read8(I2C_PORT_ACCEL, - ICM426XX_ADDR0_FLAGS, - ICM426XX_REG_WHO_AM_I, &base_device_id); + i2c_read8(I2C_PORT_ACCEL, ICM426XX_ADDR0_FLAGS, + ICM426XX_REG_WHO_AM_I, &base_device_id); - CPRINTS("Motion Sensor Base id = %d Lid id =%d", - base_device_id, lid_device_id); + CPRINTS("Motion Sensor Base id = %d Lid id =%d", base_device_id, + lid_device_id); if (lid_device_id == KX022_WHO_AM_I_VAL) { motion_sensors[LID_ACCEL] = kx022_lid_accel; @@ -657,7 +646,8 @@ __override void board_chipset_forced_shutdown(void) { hook_call_deferred(&check_reboot_deferred_data, -1); } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_forced_shutdown, + HOOK_PRIO_DEFAULT); static void check_reboot_deferred(void) { -- cgit v1.2.1 From 48624714027b0c38835c34a36fa09df8208f1ab1 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Fri, 17 Jun 2022 11:00:59 -0700 Subject: CCGXXF: Add S/W logic to reset CCGXXF chip As CCGXXF's reset line is connected to an internal LDO, an external GPIOs should not control the reset line which can prevent CCGXXF booting from dead battery hence added a software mechanism to reset the chip. BUG=none BRANCH=none TEST=CCGXXF chip resets on MTLRVP Change-Id: I53b3605158df5cd26915cfac8511f035b991bbe0 Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712181 Reviewed-by: Tanu Malhotra Reviewed-by: Brandon Breitenstein Reviewed-by: Diana Z --- driver/tcpm/ccgxxf.c | 5 +++++ driver/tcpm/ccgxxf.h | 22 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c index b206da44c2..216b812e5e 100644 --- a/driver/tcpm/ccgxxf.c +++ b/driver/tcpm/ccgxxf.c @@ -32,6 +32,11 @@ static void ccgxxf_dump_registers(int port) } #endif +int ccgxxf_reset(int port) +{ + return tcpc_write16(port, CCGXXF_REG_FWU_COMMAND, CCGXXF_FWU_CMD_RESET); +} + const struct tcpm_drv ccgxxf_tcpm_drv = { .init = &tcpci_tcpm_init, .release = &tcpci_tcpm_release, diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h index c20a6b18a6..7d97962351 100644 --- a/driver/tcpm/ccgxxf.h +++ b/driver/tcpm/ccgxxf.h @@ -20,6 +20,28 @@ #define CCGXXF_REG_FW_VERSION 0x94 #define CCGXXF_REG_FW_VERSION_BUILD 0x96 +/* Firmware update / reset control register */ +#define CCGXXF_REG_FWU_COMMAND 0x92 +#define CCGXXF_FWU_CMD_RESET 0x0077 + +/** + * Reset CCGXXF chip + * + * CCGXXF's reset line is connected to an internal LDO hence external GPIOs + * should not control the reset line as it can prevent it booting from dead + * battery, instead a software mechanism can be used to reset the chip. + * Care must be taken by board level function in below scenarios; + * 1. During dead battery boot from CCGXXF ports, do not reset the chip as + * it will lose the dead battery boot scenario content. + * 2. If dual port solution chip is used, resetting one port resets other port + * as well. + * 3. Built-in I/O expander also gets reset. + * + * @param port Type-C port number + * @return EC_SUCCESS or error + */ +int ccgxxf_reset(int port); + extern const struct tcpm_drv ccgxxf_tcpm_drv; /* CCGXXF built in I/O expander definitions */ -- cgit v1.2.1 From 14b8270edd02c5bbff124e8c5c263fe0669897af Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Thu, 30 Jun 2022 14:33:04 -0700 Subject: docs/fingerprint: Update dragonclaw power numbers When measuring power, I found I was getting slightly different numbers. It looks like the difference occurred when I measured with the debugger (JLink) connected. The numbers in this commit were measured with the debugger physically disconnected. I also disconnected servo micro, reattached it and restarted servod before running the test. BRANCH=none BUG=b:180945056 TEST=view in gitiles Signed-off-by: Tom Hughes Change-Id: If976e45b5300ae451d10c227d3d3e738555bc5f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739313 Reviewed-by: Bobby Casey Reviewed-by: Andrea Grandi --- docs/fingerprint/fingerprint-dev-for-partners.md | 5 ++++ docs/fingerprint/fingerprint.md | 31 ++++++++++++------------ 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/docs/fingerprint/fingerprint-dev-for-partners.md b/docs/fingerprint/fingerprint-dev-for-partners.md index e78fde5caa..98ed217e93 100644 --- a/docs/fingerprint/fingerprint-dev-for-partners.md +++ b/docs/fingerprint/fingerprint-dev-for-partners.md @@ -315,6 +315,11 @@ You can get a summary of the power over `N` seconds with: (chroot) $ dut-control -t N pp3300_dx_mcu_mv pp3300_dx_fp_mv pp1800_dx_fp_mv pp3300_dx_mcu_mw pp3300_dx_fp_mw pp1800_dx_fp_mw ``` +When measuring the power, make sure that any debuggers are disconnected. The +most reliable way to make sure it is disconnected is to physically disconnect +the debugger and servo_micro from the board. Then re-attach servo_micro and +restart `servod`. + *** note The `_mv` suffix denotes millivolt and `_mw` suffix denotes milliwatt. diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md index 04f5a6bab9..e1b1bd1f9a 100644 --- a/docs/fingerprint/fingerprint.md +++ b/docs/fingerprint/fingerprint.md @@ -322,7 +322,8 @@ a lot easier during both development and testing. ## Power See [Measuring Power] for instructions on how to measure power with the -fingerprint development boards. +fingerprint development boards. *Make sure that any debuggers are completely +disconnected.* ### Dragonclaw v0.2 @@ -341,13 +342,13 @@ fingerprint development boards. ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 113 533.56 40.91 658.52 447.06 -@@ pp1800_dx_fp_mv 113 1800.00 0.00 1800.00 1800.00 -@@ pp1800_dx_fp_mw 113 0.00 0.00 0.00 0.00 -@@ pp3300_dx_fp_mv 113 3280.00 0.00 3280.00 3280.00 -@@ pp3300_dx_fp_mw 113 0.01 0.05 0.26 0.00 -@@ pp3300_dx_mcu_mv 113 3280.00 0.00 3280.00 3280.00 -@@ pp3300_dx_mcu_mw 113 24.67 0.00 24.67 24.67 +@@ sample_msecs 465 129.06 22.68 396.32 94.61 +@@ pp1800_dx_fp_mv 465 1800.00 0.00 1800.00 1800.00 +@@ pp1800_dx_fp_mw 465 0.00 0.00 0.00 0.00 +@@ pp3300_dx_fp_mv 465 3280.02 0.37 3288.00 3280.00 +@@ pp3300_dx_fp_mw 465 0.01 0.04 0.26 0.00 +@@ pp3300_dx_mcu_mv 465 3280.00 0.00 3280.00 3280.00 +@@ pp3300_dx_mcu_mw 465 20.76 0.12 22.04 20.73 ``` #### MCU in low power mode (suspend) @@ -358,13 +359,13 @@ fingerprint development boards. ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 115 526.56 36.79 607.60 426.58 -@@ pp1800_dx_fp_mv 115 1800.00 0.00 1800.00 1800.00 -@@ pp1800_dx_fp_mw 115 0.00 0.00 0.00 0.00 -@@ pp3300_dx_fp_mv 115 3287.30 2.25 3288.00 3280.00 -@@ pp3300_dx_fp_mw 115 0.00 0.02 0.26 0.00 -@@ pp3300_dx_mcu_mv 115 3280.97 2.62 3288.00 3280.00 -@@ pp3300_dx_mcu_mw 115 4.02 0.64 10.76 3.94 +@@ sample_msecs 462 129.89 15.65 381.76 97.02 +@@ pp1800_dx_fp_mv 462 1800.00 0.00 1800.00 1800.00 +@@ pp1800_dx_fp_mw 462 0.00 0.00 0.00 0.00 +@@ pp3300_dx_fp_mv 462 3287.65 1.63 3288.00 3280.00 +@@ pp3300_dx_fp_mw 462 0.00 0.03 0.26 0.00 +@@ pp3300_dx_mcu_mv 462 3283.31 3.94 3288.00 3280.00 +@@ pp3300_dx_mcu_mw 462 1.55 0.08 1.58 1.31 ``` ### Icetower v0.1 -- cgit v1.2.1 From d84ada1a3179b13395d3e1c17a5b67e93bdc10f5 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Fri, 1 Jul 2022 13:58:00 -0700 Subject: chip/stm32: Remove duplicate USB macros Through build errors in crrev.com/c/3086363 it has come to my attention that a number of USB-related macros are both defined in various chip-specific register files, as well as the common registers.h. This is tolerated by the compiler, as long as the definitions are exactly identical. However, even seemingly benign whitespace changes, such as crrev.com/c/3729534, will cause compiler errors. This CL removes from the chip-specific files any USB macro declaration that already exists in the common file. BUG=b:236386294 BRANCH=none TEST=none Signed-off-by: Jes B. Klinke Change-Id: Ib374b4e480d99d7e9c55255145db57d1f3795703 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3740760 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f3.h | 77 ------------------------------------------ chip/stm32/registers-stm32f7.h | 77 ------------------------------------------ chip/stm32/registers-stm32g4.h | 53 ----------------------------- chip/stm32/registers-stm32h7.h | 74 ---------------------------------------- chip/stm32/registers-stm32l.h | 77 ------------------------------------------ chip/stm32/registers-stm32l5.h | 75 ---------------------------------------- 6 files changed, 433 deletions(-) diff --git a/chip/stm32/registers-stm32f3.h b/chip/stm32/registers-stm32f3.h index 30eefb7ce0..a96f98e38d 100644 --- a/chip/stm32/registers-stm32f3.h +++ b/chip/stm32/registers-stm32f3.h @@ -902,83 +902,6 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) #define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = \ - (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) - /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) #define STM32_RNG_CR_RNGEN BIT(2) diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h index 59fc3228a4..d48df6f894 100644 --- a/chip/stm32/registers-stm32f7.h +++ b/chip/stm32/registers-stm32f7.h @@ -969,83 +969,6 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) #define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = \ - (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) - /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) #define STM32_RNG_CR_RNGEN BIT(2) diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h index 5ad6194795..25c57c2540 100644 --- a/chip/stm32/registers-stm32g4.h +++ b/chip/stm32/registers-stm32g4.h @@ -1398,60 +1398,7 @@ enum dmamux1_request { #define STM32_CRC_CR_REV_IN_WORD (3 << 5) #define STM32_CRC_CR_REV_OUT BIT(7) - /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) #define STM32_USB_BCDR_DPPU BIT(15) /* --- USB Endpoint bit definitions --- */ diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h index 1ae8e3bdaa..2053a85830 100644 --- a/chip/stm32/registers-stm32h7.h +++ b/chip/stm32/registers-stm32h7.h @@ -1130,80 +1130,6 @@ enum dmamux1_request { #define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) #define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) #define STM32_RNG_CR_RNGEN BIT(2) diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h index 37b31ac302..033bbf44b0 100644 --- a/chip/stm32/registers-stm32l.h +++ b/chip/stm32/registers-stm32l.h @@ -770,83 +770,6 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) #define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) -/* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) - /* --- TRNG --- */ #define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) #define STM32_RNG_CR_RNGEN BIT(2) diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index 84177f715b..28b2a253d3 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -2207,83 +2207,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC1_CCR REG32(STM32_ADC1_BASE + 0x308) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) - -#define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) #define STM32_USB_BCDR_DPPU BIT(15) -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 -#define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 -#define EP_TX_STALL 0x0010 -#define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 -#define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 -#define EP_RX_STALL 0x1000 -#define EP_RX_DISAB 0x0000 - -#define EP_STATUS_OUT 0x0100 - -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) -#define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) - -#define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = \ - (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) - /* --- DMA --- */ /* -- cgit v1.2.1 From 7af732d17855c46080b1de87ba0fecded34dce37 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Sat, 2 Jul 2022 11:07:13 +1000 Subject: zephyr: Remove unreferenced GPIO/IOEX enum-names Remove unreferenced GPIO/IOEX enum names. BUG=none TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: I32b540a94f76821c24b72c1150f5f4ca76ef2aac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3740390 Reviewed-by: Sam Hurst --- zephyr/dts/bindings/gpio/gpio-enum-name.yaml | 108 ++------------------- zephyr/projects/brya/gpio.dts | 5 - .../projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts | 2 - zephyr/projects/skyrim/gpio.dts | 8 -- 4 files changed, 6 insertions(+), 117 deletions(-) diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml index 608a2c8236..f4b5d0a89e 100644 --- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml +++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml @@ -4,12 +4,17 @@ properties: type: string description: Enum used in code. - These names should only be used for legacy common code. + These names MUST ONLY be referenced by legacy code that is + included with Zephyr projects. Some development boards like trogdor, volteer etc. shim in the older baseboard/board headers and code, so they are also using most of these names. When these boards get removed, these names can be removed + + Do not add any more names to this list. Please remove + any names that are not referenced by Zephyr projects (or + are not in included common legacy code) enum: - GPIO_AC_PRESENT - GPIO_AP_EC_SYSRST_ODL @@ -126,128 +131,27 @@ properties: - GPIO_VOLUME_DOWN_L - GPIO_VOLUME_UP_L - GPIO_WARM_RESET_L - - IOEX_5V_DC_DC_MODE_CTRL - - IOEX_ATMEL_MISO - - IOEX_ATMEL_MOSI - - IOEX_ATMEL_RESET_L - - IOEX_ATMEL_SCLK - - IOEX_ATMEL_SS - - IOEX_BAT_LED_AMBER_L - - IOEX_BAT_LED_GREEN_FULL_L - - IOEX_BAT_LED_RED_L - - IOEX_BAT_LED_WHITE_L - - IOEX_BOARD_ID_DET0 - - IOEX_BOARD_ID_DET1 - - IOEX_BOARD_ID_DET2 - - IOEX_C1_CHARGER_LED_AMBER_DB - - IOEX_C1_CHARGER_LED_WHITE_DB - - IOEX_DAC_BUF1_LATCH_FAULT_L - - IOEX_DAC_BUF2_LATCH_FAULT_L - - IOEX_DONGLE_DET - - IOEX_DUT_CHG_EN - - IOEX_EN_PP3300_DP - - IOEX_EN_PP3300_ETH - - IOEX_EN_PP5000_ALT_3P3 - - IOEX_EN_PP5000_USB_A0_VBUS - - IOEX_EN_PP5000_USB_A1_VBUS_DB - - IOEX_EN_PWR_HDMI - - IOEX_EN_PWR_HDMI_DB - - IOEX_EN_USB_A0_5V - - IOEX_EN_USB_A1_5V_DB - - IOEX_EN_USB_A1_5V_DB_OPT1 - - IOEX_EN_USB_A1_5V_DB_OPT2 - - IOEX_EN_VOUT_BUF_CC1 - - IOEX_EN_VOUT_BUF_CC2 - - IOEX_FAULT_CLEAR_CC - - IOEX_HDMI_DATA_EN - - IOEX_HDMI_DATA_EN_DB - - IOEX_HDMI_POWER_EN_DB - - IOEX_HOST_CHRG_DET - - IOEX_HOST_OR_CHG_CTL - - IOEX_ID_1_USB_C0_FRS_EN - - IOEX_ID_1_USB_C0_OC_ODL - - IOEX_ID_1_USB_C0_RT_RST_ODL - - IOEX_ID_1_USB_C1_OC_ODL - - IOEX_ID_1_USB_C2_FRS_EN - - IOEX_ID_1_USB_C2_OC_ODL - - IOEX_ID_1_USB_C2_RT_RST_ODL - - IOEX_KB_BL_EN - - IOEX_LED_BLUE - - IOEX_LED_GREEN - - IOEX_LED_ORANGE - - IOEX_PP3300_DP_FAULT_L - - IOEX_PP5000_SRC_SEL - - IOEX_PPC_ID - - IOEX_PWR_LED_WHITE_L - - IOEX_SBU_FLIP_SEL - - IOEX_SBU_UART_SEL - - IOEX_SYS_PWR_IRQ_ODL - - IOEX_TCA_GPIO_DBG_LED_K_ODL - - IOEX_UART_18_SEL - - IOEX_USB3_A0_FAULT_L - - IOEX_USB3_A0_MUX_EN_L - - IOEX_USB3_A0_MUX_SEL - - IOEX_USB3_A0_PWR_EN - - IOEX_USB3_A1_FAULT_L - - IOEX_USB3_A1_MUX_SEL - - IOEX_USB3_A1_PWR_EN - - IOEX_USB_A0_CHARGE_EN_L - - IOEX_USB_A0_LIMIT_SDP - - IOEX_USB_A0_RETIMER_EN - - IOEX_USB_A0_RETIMER_RST - - IOEX_USB_A1_CHARGE_EN_DB_L - - IOEX_USB_A1_CHARGE_EN_DB_L_OPT1 - - IOEX_USB_A1_CHARGE_EN_DB_L_OPT2 - - IOEX_USB_A1_FAULT_DB_ODL - - IOEX_USB_A1_LIMIT_SDP_DB - IOEX_USB_A1_RETIMER_EN - - IOEX_USB_A1_RETIMER_EN_OPT1 - - IOEX_USB_A1_RETIMER_EN_OPT2 - - IOEX_USB_A1_RETIMER_RST - - IOEX_USB_A1_RETIMER_RST_DB - IOEX_USB_C0_BB_RETIMER_LS_EN - IOEX_USB_C0_BB_RETIMER_RST - IOEX_USB_C0_C1_OC - - IOEX_USB_C0_DATA_EN - - IOEX_USB_C0_FAULT_ODL - IOEX_USB_C0_FRS_EN - - IOEX_USB_C0_OC_ODL - - IOEX_USB_C0_PPC_EN_L - IOEX_USB_C0_PPC_ILIM_3A_EN - - IOEX_USB_C0_RT_RST_ODL - IOEX_USB_C0_SBU_FLIP - IOEX_USB_C0_TCPC_FASTSW_CTL_EN - IOEX_USB_C0_USB_MUX_CNTRL_0 - IOEX_USB_C0_USB_MUX_CNTRL_1 - IOEX_USB_C1_BB_RETIMER_LS_EN - IOEX_USB_C1_BB_RETIMER_RST - - IOEX_USB_C1_DATA_EN - IOEX_USB_C1_FAULT_ODL - - IOEX_USB_C1_FRS_EN - IOEX_USB_C1_HPD - IOEX_USB_C1_HPD_IN_DB - - IOEX_USB_C1_IN_HPD - - IOEX_USB_C1_MUX_RST_DB - - IOEX_USB_C1_OC_ODL - - IOEX_USB_C1_POWER_SWITCH_ID - - IOEX_USB_C1_PPC_EN_L - IOEX_USB_C1_PPC_ILIM_3A_EN - - IOEX_USB_C1_RT_RST_ODL - IOEX_USB_C1_SBU_FLIP - IOEX_USB_C1_TCPC_FASTSW_CTL_EN - IOEX_USB_C2_BB_RETIMER_LS_EN - IOEX_USB_C2_BB_RETIMER_RST - IOEX_USB_C2_C3_OC - IOEX_USB_C2_FRS_EN - - IOEX_USB_C2_OC_ODL - - IOEX_USB_C2_RT_RST_ODL - - IOEX_USB_C2_USB_MUX_CNTRL_0 - - IOEX_USB_C2_USB_MUX_CNTRL_1 - IOEX_USB_C3_BB_RETIMER_LS_EN - IOEX_USB_C3_BB_RETIMER_RST - - IOEX_USB_DUTCHG_FLT_ODL - - IOEX_USBH_PWRDN_L - - IOEX_USERVO_FASTBOOT_MUX_SEL - - IOEX_USERVO_FAULT_L - - IOEX_USERVO_POWER_EN - - IOEX_VBUS_DISCHRG_EN diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts index 2b853f4d3b..7f7d5e77eb 100644 --- a/zephyr/projects/brya/gpio.dts +++ b/zephyr/projects/brya/gpio.dts @@ -272,7 +272,6 @@ }; usb_c0_oc_odl { gpios = <&ioex_port1 4 GPIO_ODR_HIGH>; - enum-name = "IOEX_USB_C0_OC_ODL"; no-auto-init; }; usb_c0_frs_en { @@ -282,22 +281,18 @@ }; usb_c0_rt_rst_odl: usb_c0_rt_rst_odl { gpios = <&ioex_port1 7 GPIO_ODR_LOW>; - enum-name = "IOEX_USB_C0_RT_RST_ODL"; no-auto-init; }; usb_c2_rt_rst_odl: usb_c2_rt_rst_odl { gpios = <&ioex_port2 2 GPIO_ODR_LOW>; - enum-name = "IOEX_USB_C2_RT_RST_ODL"; no-auto-init; }; usb_c1_oc_odl { gpios = <&ioex_port2 3 GPIO_ODR_HIGH>; - enum-name = "IOEX_USB_C1_OC_ODL"; no-auto-init; }; usb_c2_oc_odl { gpios = <&ioex_port2 4 GPIO_ODR_HIGH>; - enum-name = "IOEX_USB_C2_OC_ODL"; no-auto-init; }; usb_c2_frs_en { diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 7e1cb9c704..cab165cd33 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -319,11 +319,9 @@ }; usb-c2-usb-mux-cntrl-1 { gpios = <&ioex_c2_port 4 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_1"; }; usb-c2-usb-mux-cntrl-0 { gpios = <&ioex_c2_port 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C2_USB_MUX_CNTRL_0"; }; usb_c3_bb_retimer_rst: usb-c3-bb-retimer-rst { gpios = <&ioex_c3_port 0 GPIO_OUTPUT_LOW>; diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index 56448288a6..fd28d80df3 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -191,7 +191,6 @@ }; usb_c0_ppc_en_l { gpios = <&ioex_c0_port1 0 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C0_PPC_EN_L"; }; usb_c0_ppc_ilim_3a_en { gpios = <&ioex_c0_port1 1 GPIO_OUTPUT_LOW>; @@ -199,15 +198,12 @@ }; ioex_usb_c0_sbu_fault_odl: usb_c0_sbu_fault_odl { gpios = <&ioex_c0_port1 2 GPIO_INPUT>; - enum-name = "IOEX_USB_C0_FAULT_ODL"; }; ioex_en_pp5000_usb_a0_vbus: en_pp5000_usb_a0_vbus { gpios = <&ioex_c0_port1 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_EN_PP5000_USB_A0_VBUS"; }; ioex_usb_a0_fault_odl: usb_a0_fault_odl { gpios = <&ioex_c0_port1 6 GPIO_INPUT>; - enum-name = "IOEX_USB3_A0_FAULT_L"; }; usb_c0_sbu_flip { gpios = <&ioex_c0_port1 7 GPIO_OUTPUT_LOW>; @@ -220,7 +216,6 @@ }; usb_a1_retimer_rst { gpios = <&ioex_c1_port0 1 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_A1_RETIMER_RST"; }; usb_c1_in_hpd { gpios = <&ioex_c1_port0 3 GPIO_OUTPUT_LOW>; @@ -232,7 +227,6 @@ }; usb_c1_ppc_en_l { gpios = <&ioex_c1_port1 0 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_USB_C1_PPC_EN_L"; }; usb_c1_ppc_ilim_3a_en { gpios = <&ioex_c1_port1 1 GPIO_OUTPUT_LOW>; @@ -244,11 +238,9 @@ }; ioex_en_pp5000_usb_a1_vbus: en_pp5000_usb_a1_vbus { gpios = <&ioex_c1_port1 5 GPIO_OUTPUT_LOW>; - enum-name = "IOEX_EN_PP5000_USB_A1_VBUS_DB"; }; ioex_usb_a1_fault_db_odl: usb_a1_fault_db_odl { gpios = <&ioex_c1_port1 6 GPIO_INPUT>; - enum-name = "IOEX_USB_A1_FAULT_DB_ODL"; }; usb_c1_sbu_flip { gpios = <&ioex_c1_port1 7 GPIO_OUTPUT_LOW>; -- cgit v1.2.1 From b4903c8769323aca3ef3682f38bc078a4830320b Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Fri, 1 Jul 2022 16:19:26 +1000 Subject: nissa: allow dynamic I2C speed setting for PS8745 The normal speed for this bus is too fast for window programming mode for the PS8745, which makes firmware updating much more efficient. Allow dynamic speed setting so the AP can reduce speed in order to use window mode. BUG=b:237593618 TEST=Firmware update succeeds with window mode enabled on Nereid BRANCH=none Change-Id: If9e88972425df81a30ea99233240879b0e974ebd Signed-off-by: Peter Marheine Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726603 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/joxer_overlay.dts | 10 ++++++++++ zephyr/projects/nissa/nereid_overlay.dts | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index 158629b1e9..b777d13074 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -319,6 +319,16 @@ pinctrl-names = "default"; }; +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + &i2c5 { label = "I2C_USB_C0_TCPC"; clock-frequency = ; diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index 8f73dfbfc4..112411e5cc 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -319,6 +319,16 @@ pinctrl-names = "default"; }; +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + &i2c5 { label = "I2C_USB_C0_TCPC"; clock-frequency = ; -- cgit v1.2.1 From 8f1d5ebb52572b4bab7d53fc55c6807b6dc6e763 Mon Sep 17 00:00:00 2001 From: Elsie Shih Date: Fri, 17 Jun 2022 10:05:00 +0800 Subject: moli: add custom fan control Follow Moli Fan Table_0616.xlsx to add fan table. BUG=b:236294162 BRANCH=none TEST=make BOARD=moli Signed-off-by: Elsie Shih Change-Id: I4d6ae85da33c3f7bc896bfaf253ad2d5e76d6c7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3708383 Reviewed-by: Scott Chao Reviewed-by: Zhuohao Lee --- board/moli/board.h | 1 + board/moli/build.mk | 1 + board/moli/fans.c | 12 ++--- board/moli/sensors.c | 8 ++- board/moli/thermal.c | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 153 insertions(+), 14 deletions(-) create mode 100644 board/moli/thermal.c diff --git a/board/moli/board.h b/board/moli/board.h index f1821ca758..ae5d94a25b 100644 --- a/board/moli/board.h +++ b/board/moli/board.h @@ -131,6 +131,7 @@ /* Fan */ #define CONFIG_FANS FAN_CH_COUNT #define RPM_DEVIATION 1 +#define CONFIG_CUSTOM_FAN_CONTROL /* Include math_util for bitmask_uint64 used in pd_timers */ #define CONFIG_MATH_UTIL diff --git a/board/moli/build.mk b/board/moli/build.mk index 00fc2723cd..548879ba3b 100644 --- a/board/moli/build.mk +++ b/board/moli/build.mk @@ -18,4 +18,5 @@ board-y+=i2c.o board-y+=led.o board-y+=pwm.o board-y+=sensors.o +board-y+=thermal.o board-y+=usbc_config.o diff --git a/board/moli/fans.c b/board/moli/fans.c index 62492fe063..fe0e535df2 100644 --- a/board/moli/fans.c +++ b/board/moli/fans.c @@ -30,16 +30,10 @@ static const struct fan_conf fan_conf_0 = { .enable_gpio = GPIO_EN_PP5000_FAN, }; -/* - * TOOD(b/197478860): need to update for real fan - * - * Prototype fan spins at about 7200 RPM at 100% PWM. - * Set minimum at around 30% PWM. - */ static const struct fan_rpm fan_rpm_0 = { - .rpm_min = 2200, - .rpm_start = 2200, - .rpm_max = 7200, + .rpm_min = 1500, + .rpm_start = 1500, + .rpm_max = 5200, }; const struct fan_t fans[FAN_CH_COUNT] = { diff --git a/board/moli/sensors.c b/board/moli/sensors.c index 7ae3ee2889..81a2c84559 100644 --- a/board/moli/sensors.c +++ b/board/moli/sensors.c @@ -79,14 +79,12 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); #define THERMAL_CPU \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(100), \ + [EC_TEMP_THRESH_HALT] = C_TO_K(110), \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(98), \ }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(50), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; diff --git a/board/moli/thermal.c b/board/moli/thermal.c new file mode 100644 index 0000000000..67c112e3a8 --- /dev/null +++ b/board/moli/thermal.c @@ -0,0 +1,145 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "chipset.h" +#include "common.h" +#include "console.h" +#include "fan.h" +#include "hooks.h" +#include "host_command.h" +#include "temp_sensor.h" +#include "thermal.h" +#include "util.h" +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_THERMAL, outstr) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) + +struct fan_step { + /* + * Sensor 1~4 trigger point, set -1 if we're not using this + * sensor to determine fan speed. + */ + int8_t on[TEMP_SENSOR_COUNT]; + /* + * Sensor 1~4 trigger point, set -1 if we're not using this + * sensor to determine fan speed. + */ + int8_t off[TEMP_SENSOR_COUNT]; + /* Fan rpm */ + uint16_t rpm[FAN_CH_COUNT]; +}; + +static const struct fan_step fan_table[] = { + { + /* level 0 */ + .on = {-1, 47, -1}, + .off = {-1, 0, -1}, + .rpm = {1900}, + }, + { + /* level 1 */ + .on = {-1, 50, -1}, + .off = {-1, 47, -1}, + .rpm = {2500}, + }, + { + /* level 2 */ + .on = {-1, 60, -1}, + .off = {-1, 57, -1}, + .rpm = {3000}, + }, + { + /* level 3 */ + .on = {-1, 70, -1}, + .off = {-1, 67, -1}, + .rpm = {3500}, + }, + { + /* level 4 */ + .on = {-1, 80, -1}, + .off = {-1, 77, -1}, + .rpm = {4000}, + }, + { + /* level 5 */ + .on = {-1, 90, -1}, + .off = {-1, 87, -1}, + .rpm = {4500}, + }, +}; +const int num_fan_levels = ARRAY_SIZE(fan_table); + +int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor) +{ + /* current fan level */ + static int current_level; + /* previous fan level */ + static int prev_current_level; + /* previous sensor temperature */ + static int prev_temp[TEMP_SENSOR_COUNT]; + int i; + int new_rpm = 0; + + /* + * Compare the current and previous temperature, we have + * the three paths : + * 1. decreasing path. (check the release point) + * 2. increasing path. (check the trigger point) + * 3. invariant path. (return the current RPM) + */ + if (temp[temp_sensor] < prev_temp[temp_sensor]) { + for (i = current_level; i > 0; i--) { + if (temp[temp_sensor] < + fan_table[i].off[temp_sensor]) + current_level = i - 1; + else + break; + } + } else if (temp[temp_sensor] > + prev_temp[temp_sensor]) { + for (i = current_level; i < num_fan_levels; i++) { + if (temp[temp_sensor] >= + fan_table[i].on[temp_sensor]) + current_level = i; + else + break; + } + } + if (current_level < 0) + current_level = 0; + if (current_level >= num_fan_levels) + current_level = num_fan_levels - 1; + + if (current_level != prev_current_level) { + CPRINTS("temp: %d, prev_temp: %d", temp[temp_sensor], + prev_temp[temp_sensor]); + CPRINTS("current_level: %d", current_level); + } + + prev_temp[temp_sensor] = temp[temp_sensor]; + prev_current_level = current_level; + + switch (fan) { + case FAN_CH_0: + new_rpm = fan_table[current_level].rpm[FAN_CH_0]; + break; + default: + break; + } + return new_rpm; +} + +void board_override_fan_control(int fan, int *temp) +{ + if (chipset_in_state(CHIPSET_STATE_ON)) { + fan_set_rpm_mode(FAN_CH(fan), 1); + fan_set_rpm_target(FAN_CH(fan), + fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_2_CPU_VR)); + } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { + /* Stop fan when enter S0ix */ + fan_set_rpm_mode(FAN_CH(fan), 1); + fan_set_rpm_target(FAN_CH(fan), 0); + } +} -- cgit v1.2.1 From b7d77ec7b9a3b25878f877bb2de5f80ce0f16500 Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Wed, 29 Jun 2022 08:36:25 +0800 Subject: Xivu : GPIO initial. This patch according to the HW circuit that modify GPIO setting. The Xivu have no HDMI relate pin, Remove the sub-board.c from CMakeLists. BUG=b:237432830 BRANCH=none TEST=zmake build xivu success. Signed-off-by: Logan_Liao Change-Id: I234f78fc4dc149ed235b60b63a89de8007116730 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733929 Reviewed-by: Logan Liao Reviewed-by: Peter Marheine Commit-Queue: Logan Liao Tested-by: Logan Liao --- zephyr/projects/nissa/CMakeLists.txt | 6 +++++- zephyr/projects/nissa/src/sub_board.c | 2 +- zephyr/projects/nissa/src/xivu/charger.c | 20 +++++++++++++------- zephyr/projects/nissa/xivu_generated.dts | 8 ++------ zephyr/projects/nissa/xivu_keyboard.dts | 2 ++ zephyr/projects/nissa/xivu_overlay.dts | 30 ++++++++++-------------------- zephyr/projects/nissa/xivu_pwm_leds.dts | 9 ++++++++- 7 files changed, 41 insertions(+), 36 deletions(-) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 47f98daf9f..b2bb2c67d2 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -8,7 +8,6 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) zephyr_include_directories(include) zephyr_library_sources("src/common.c") -zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c") if(DEFINED CONFIG_BOARD_NIVVIKS) @@ -18,6 +17,7 @@ if(DEFINED CONFIG_BOARD_NIVVIKS) "src/nivviks/form_factor.c" "src/nivviks/keyboard.c" ) + zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/nivviks/fan.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nivviks/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nivviks/charger.c") @@ -28,6 +28,7 @@ if(DEFINED CONFIG_BOARD_NEREID) "src/led.c" "src/nereid/keyboard.c" ) + zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nereid/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nereid/charger.c") endif() @@ -36,6 +37,7 @@ if(DEFINED CONFIG_BOARD_CRAASK) "src/craask/led.c" ) project(craask) + zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c") endif() @@ -45,6 +47,7 @@ if(DEFINED CONFIG_BOARD_PUJJO) "src/led.c" "src/pujjo/keyboard.c" ) + zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") @@ -63,6 +66,7 @@ if(DEFINED CONFIG_BOARD_JOXER) "src/led.c" "src/joxer/keyboard.c" ) + zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/joxer/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/joxer/charger.c") endif() diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c index dac4cae0e0..38c7f1f616 100644 --- a/zephyr/projects/nissa/src/sub_board.c +++ b/zephyr/projects/nissa/src/sub_board.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ diff --git a/zephyr/projects/nissa/src/xivu/charger.c b/zephyr/projects/nissa/src/xivu/charger.c index baa204f825..123696746e 100644 --- a/zephyr/projects/nissa/src/xivu/charger.c +++ b/zephyr/projects/nissa/src/xivu/charger.c @@ -36,13 +36,19 @@ int extpower_is_present(void) */ __override void board_check_extpower(void) { - static int last_extpower_present; - int extpower_present = extpower_is_present(); - - if (last_extpower_present ^ extpower_present) - extpower_handle_update(extpower_present); - - last_extpower_present = extpower_present; + int extpower_present; + + if (pd_is_connected(0)) + extpower_present = extpower_is_present(); + else + extpower_present = 0; + + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), + extpower_present); + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), + extpower_present); } __override void board_hibernate(void) diff --git a/zephyr/projects/nissa/xivu_generated.dts b/zephyr/projects/nissa/xivu_generated.dts index 1a4d5f044f..df10058274 100644 --- a/zephyr/projects/nissa/xivu_generated.dts +++ b/zephyr/projects/nissa/xivu_generated.dts @@ -79,7 +79,7 @@ gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { gpios = <&gpio6 1 GPIO_OUTPUT>; }; - gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpio_ec_acok_otg_c1: ec_acok_otg_c1 { gpios = <&gpioe 4 GPIO_OUTPUT>; }; gpio_ec_soc_int_odl: ec_soc_int_odl { @@ -108,10 +108,6 @@ gpio_ec_wp_odl: ec_wp_odl { gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; }; - gpio_en_kb_bl: en_kb_bl { - gpios = <&gpioa 0 GPIO_OUTPUT>; - enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; - }; gpio_en_pp3300_s5: en_pp3300_s5 { gpios = <&gpiob 6 GPIO_OUTPUT>; enum-name = "GPIO_TEMP_SENSOR_POWER"; @@ -132,7 +128,7 @@ gpios = <&gpio0 0 GPIO_INPUT_PULL_UP>; enum-name = "GPIO_POWER_BUTTON_L"; }; - gpio_hdmi_sel: hdmi_sel { + gpio_ec_acok_otg_c0: ec_acok_otg_c0 { gpios = <&gpioc 6 GPIO_OUTPUT>; }; gpio_imu_int_l: imu_int_l { diff --git a/zephyr/projects/nissa/xivu_keyboard.dts b/zephyr/projects/nissa/xivu_keyboard.dts index d3fd354b8f..e97165cc92 100644 --- a/zephyr/projects/nissa/xivu_keyboard.dts +++ b/zephyr/projects/nissa/xivu_keyboard.dts @@ -27,6 +27,8 @@ &kso10_gp07 &kso11_gp06 &kso12_gp05 + &kso13_gp04 + &kso14_gp82 >; pinctrl-names = "default"; }; diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts index 1ff3022124..b949cdcb03 100644 --- a/zephyr/projects/nissa/xivu_overlay.dts +++ b/zephyr/projects/nissa/xivu_overlay.dts @@ -92,15 +92,6 @@ gpios = <&gpiod 4 GPIO_OUTPUT>; no-auto-init; }; - - gpio_sb_3: sb_3 { - gpios = <&gpiof 4 GPIO_OPEN_DRAIN>; - no-auto-init; - }; - gpio_sb_4: sb_4 { - gpios = <&gpiof 5 GPIO_INPUT>; - no-auto-init; - }; }; /* @@ -109,7 +100,6 @@ aliases { /* * Input GPIO when used with type-C port 1 - * Output when used with HDMI sub-board */ gpio-usb-c1-int-odl = &gpio_sb_1; gpio-en-rails-odl = &gpio_sb_1; @@ -117,11 +107,6 @@ * Sub-board with type A USB, enable. */ gpio-en-usb-a1-vbus = &gpio_sb_2; - /* - * HPD pins for HDMI sub-board. - */ - gpio-hdmi-en-odl = &gpio_sb_3; - gpio-hpd-odl = &gpio_sb_4; /* * Enable S5 rails for LTE sub-board */ @@ -234,11 +219,16 @@ }; }; - kblight { - compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm6 6 0 PWM_POLARITY_NORMAL>; - frequency = <10000>; - }; + unused-pins { + compatible = "unused-gpios"; + unused-gpios = + <&gpio3 3 0>, + <&gpio3 6 0>, + <&gpiod 7 0>, + <&gpio6 0 0>, + <&gpiof 2 0>, + <&gpiof 3 0>; + }; /* * Set I2C pins for type C sub-board to be diff --git a/zephyr/projects/nissa/xivu_pwm_leds.dts b/zephyr/projects/nissa/xivu_pwm_leds.dts index 592275ff71..59325ecf09 100644 --- a/zephyr/projects/nissa/xivu_pwm_leds.dts +++ b/zephyr/projects/nissa/xivu_pwm_leds.dts @@ -9,7 +9,8 @@ pwm_led0: pwm_led_0 { pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>, <&pwm0 0 0 PWM_POLARITY_INVERTED>, - <&pwm1 1 0 PWM_POLARITY_INVERTED>; + <&pwm1 1 0 PWM_POLARITY_INVERTED>, + <&pwm6 6 0 PWM_POLARITY_INVERTED>; }; }; @@ -61,3 +62,9 @@ pinctrl-0 = <&pwm2_gpc4>; pinctrl-names = "default"; }; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; -- cgit v1.2.1 From 5fdc963a5563e25f66fe0b79963979f524ece5e9 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Fri, 1 Jul 2022 13:45:57 +0800 Subject: burnet: Fix SPI NSS leakage on S5 Pull low the SPI_NSS to prevent leakage on S5. BUG=b:173647487 BRANCH=firmware-kukui-12573.B TEST=On Burnet. No leakage on sensor SPI. Signed-off-by: Devin Lu Change-Id: I4f15b019dc16913e98b0cc2a0050dd6c7847afdf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739986 Reviewed-by: Chen-Tsung Hsieh Tested-by: Devin Lu Commit-Queue: Devin Lu --- board/burnet/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/burnet/board.c b/board/burnet/board.c index 3e99529f81..153625fb7d 100644 --- a/board/burnet/board.c +++ b/board/burnet/board.c @@ -309,6 +309,8 @@ static void board_spi_disable(void) /* Set pins to a state calming the sensor down. */ gpio_set_flags(GPIO_EC_SENSOR_SPI_CK, GPIO_OUT_LOW); gpio_set_level(GPIO_EC_SENSOR_SPI_CK, 0); + gpio_set_flags(GPIO_EC_SENSOR_SPI_NSS, GPIO_OUT_LOW); + gpio_set_level(GPIO_EC_SENSOR_SPI_NSS, 0); gpio_config_module(MODULE_SPI_CONTROLLER, 0); /* Disable spi peripheral and clocks. */ -- cgit v1.2.1 From bfa47ad210a6efffdd0b6fe32b884ba38c4cb2b1 Mon Sep 17 00:00:00 2001 From: ridden_liu Date: Tue, 28 Jun 2022 13:50:26 +0800 Subject: Xivu: Implement Battery Parameter Setup battery parameter for xivu. BUG=b:237192635 BRANCH=xivu TEST=zmake build xivu Signed-off-by: ridden_liu Change-Id: I81e5a5636b608bffe850b51c3ec6f98e81142813 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726601 Reviewed-by: Andrew McRae --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/smp,c31n2005.yaml | 48 ++++++++++++++++++++++++++ zephyr/projects/nissa/prj_xivu.conf | 8 +++++ zephyr/projects/nissa/xivu_overlay.dts | 4 +-- 4 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 zephyr/dts/bindings/battery/smp,c31n2005.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index 93118e50de..62ef63c99d 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -30,6 +30,7 @@ properties: - "panasonic,ap16l5j-009" - "panasonic,ap19a5k" - "powertech,batgqa05l22" + - "smp,c31n2005" - "smp,l20m3pg0" - "smp,l20m3pg1" - "smp,l20m3pg2" diff --git a/zephyr/dts/bindings/battery/smp,c31n2005.yaml b/zephyr/dts/bindings/battery/smp,c31n2005.yaml new file mode 100644 index 0000000000..afdc0e9816 --- /dev/null +++ b/zephyr/dts/bindings/battery/smp,c31n2005.yaml @@ -0,0 +1,48 @@ +# SMP Li-Po 4335mAh +description: "SMP LiPo 4335mAh AS3GWQd3jB C490-42" +compatible: "smp,c31n2005" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "smp,c31n2005" + + # Fuel gauge + manuf_name: + default: "SMP" + device_name: + default: "C31N2005" + ship_mode_reg_addr: + default: 0x00 + ship_mode_reg_data: + default: [ 0x0010, 0x0010 ] + fet_reg_addr: + default: 0x99 + fet_reg_mask: + default: 0x000c + fet_disconnect_val: + default: 0x000c + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11880 + voltage_min: + default: 9000 + precharge_current: + default: 256 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 45 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 60 diff --git a/zephyr/projects/nissa/prj_xivu.conf b/zephyr/projects/nissa/prj_xivu.conf index fc46adb7f7..c64fcd4d4d 100644 --- a/zephyr/projects/nissa/prj_xivu.conf +++ b/zephyr/projects/nissa/prj_xivu.conf @@ -37,3 +37,11 @@ CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=22 CONFIG_ADC_CMP_NPCX=y CONFIG_SENSOR=y CONFIG_SENSOR_SHELL=n + +# Battery support +CONFIG_PLATFORM_EC_BATTERY=y +CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y +CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y +CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y +CONFIG_PLATFORM_EC_BATTERY_SMART=y +CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts index b949cdcb03..ecfd4e475d 100644 --- a/zephyr/projects/nissa/xivu_overlay.dts +++ b/zephyr/projects/nissa/xivu_overlay.dts @@ -19,8 +19,8 @@ }; batteries { - default_battery: lgc { - compatible = "lgc,ap18c8k", "battery-smart"; + default_battery: smp_c31n2005 { + compatible = "smp,c31n2005", "battery-smart"; }; }; -- cgit v1.2.1 From c26d1863dadb7eb703d2d2847c5f076924d3a206 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Wed, 13 Apr 2022 18:02:06 +0800 Subject: zephyr: krabby: Use pinctrl API to instead of hardcode register If I2C3 is using GPIOF group, we must set SMB3PSEL=0 register of PMER3 while system entering G3 mode that will saving power number. BUG=b:226296649 BRANCH=none TEST=Setting SMB3PSEL=0 after entering G3 will reduce the average power number from 6.2mA to 1.8mA. Signed-off-by: Tim Lin Change-Id: I37f41010f429a64a73653a2478006d0cb3777d7e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735444 Reviewed-by: Ting Shen --- zephyr/projects/corsola/i2c_krabby.dts | 13 ++++++++++++- zephyr/projects/corsola/src/krabby/hooks.c | 17 ++++++++--------- 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/corsola/i2c_krabby.dts b/zephyr/projects/corsola/i2c_krabby.dts index 75cf3834eb..d1e74531f3 100644 --- a/zephyr/projects/corsola/i2c_krabby.dts +++ b/zephyr/projects/corsola/i2c_krabby.dts @@ -48,6 +48,15 @@ }; +&pinctrl { + i2c3_clk_gpf2_sleep: i2c3_clk_gpf2_sleep { + pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_DEFAULT>; + }; + i2c3_data_gpf3_sleep: i2c3_data_gpf3_sleep { + pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_DEFAULT>; + }; +}; + i2c_pwr_cbi: &i2c0 { /* EC_I2C_PWR_CBI */ label = "I2C_PWR_CBI"; @@ -87,7 +96,9 @@ i2c_pwr_cbi: &i2c0 { sda-gpios = <&gpiof 3 0>; pinctrl-0 = <&i2c3_clk_gpf2_default &i2c3_data_gpf3_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c3_clk_gpf2_sleep + &i2c3_data_gpf3_sleep>; + pinctrl-names = "default", "sleep"; prescale-scl-low = <1>; }; diff --git a/zephyr/projects/corsola/src/krabby/hooks.c b/zephyr/projects/corsola/src/krabby/hooks.c index 6f0a192e85..f921518a82 100644 --- a/zephyr/projects/corsola/src/krabby/hooks.c +++ b/zephyr/projects/corsola/src/krabby/hooks.c @@ -5,6 +5,7 @@ #include #include +#include #include #include "charger.h" @@ -13,23 +14,21 @@ #include "gpio.h" #include "hooks.h" +#define I2C3_NODE DT_NODELABEL(i2c3) +PINCTRL_DT_DEFINE(I2C3_NODE); + static void board_i2c3_ctrl(bool enable) { if (DEVICE_DT_GET( DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(i2c3), scl_gpios, 0)) == DEVICE_DT_GET(DT_NODELABEL(gpiof))) { - /* - * TODO(b/226296649): - * Use pinctrl APIs to enable/disable an interface. - */ - struct gctrl_it8xxx2_regs *const gctrl_base = - (struct gctrl_it8xxx2_regs *)DT_REG_ADDR( - DT_NODELABEL(gctrl)); + const struct pinctrl_dev_config *pcfg = + PINCTRL_DT_DEV_CONFIG_GET(I2C3_NODE); if (enable) { - gctrl_base->GCTRL_PMER3 |= IT8XXX2_GCTRL_SMB3PSEL; + pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT); } else { - gctrl_base->GCTRL_PMER3 &= ~IT8XXX2_GCTRL_SMB3PSEL; + pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP); } } } -- cgit v1.2.1 From 712c9294e62ff28c7ae8f8da7deda2d7b9551e87 Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 4 Jul 2022 12:11:45 +0800 Subject: dojo: Add CONFIG_BATTERY_REVIVE_DISCONNECT If battery is found to be in disconnect state, take it out of this state by applying this config to force-apply precharge current. BUG=none BRANCH=cherry TEST=make sure that battery can be taken out of disconnect state. Signed-off-by: Tommy Chung Change-Id: I97c64fd8e96d6b3af117221874fb769f5fb2935b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742843 Reviewed-by: Ting Shen --- board/dojo/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/dojo/board.h b/board/dojo/board.h index 5c018fccda..a8f0556f86 100644 --- a/board/dojo/board.h +++ b/board/dojo/board.h @@ -29,6 +29,7 @@ #define CONFIG_BATTERY_COUNT 1 #define CONFIG_HOSTCMD_BATTERY_V2 #define CONFIG_BATTERY_PRESENT_CUSTOM +#define CONFIG_BATTERY_REVIVE_DISCONNECT #define CONFIG_BATTERY_VENDOR_PARAM /* BC12 */ -- cgit v1.2.1 From 1eb23b30eb80a9f7d47dd8490f155c0f453b227e Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Wed, 29 Jun 2022 10:57:58 +0800 Subject: dojo: Do enable/disable nvme separately Enable/Disable nvme sould be done separately for specific SOC PCIE function demand. Also, set enable nvme priority to HOOK_PRIO_FIRST when chipset resume (see bug for more details). BUG=b:236790585 BRANCH=cherry TEST=make sure that nvme power on timing will not cause PCIe driver timeout when chipset resume. Signed-off-by: Tommy Chung Change-Id: I60b84b3f2c29f6886269cf5fbe78054d93a5a85e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3734209 Reviewed-by: Ting Shen --- board/dojo/board.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index 7ca737f337..690f9aa547 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -402,16 +402,26 @@ static void board_init(void) } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -static void board_do_chipset_resume(void) +static void enable_nvme(void) { gpio_set_level(GPIO_EN_PP3300_SSD, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_nvme, HOOK_PRIO_FIRST); + +static void disable_nvme(void) +{ + gpio_set_level(GPIO_EN_PP3300_SSD, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, disable_nvme, HOOK_PRIO_DEFAULT); + +static void board_do_chipset_resume(void) +{ gpio_set_level(GPIO_EN_KB_BL, 1); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_do_chipset_resume, HOOK_PRIO_DEFAULT); static void board_do_chipset_suspend(void) { - gpio_set_level(GPIO_EN_PP3300_SSD, 0); gpio_set_level(GPIO_EN_KB_BL, 0); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_do_chipset_suspend, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From 665f765ae202e744bb98a14d6fb1e2268f35adce Mon Sep 17 00:00:00 2001 From: "jimmy.wu" Date: Mon, 4 Jul 2022 14:21:15 +0800 Subject: zephyr: Add battery info for Pujjo. Add SMP L22M3PG0/L22M3PG1, Sunwoda L22D3PG0/L22D3PG1, Celxpert L22C3PG0 for Pujjo. BUG=b:236791102 TEST=zmake build pujjo BRANCH=none Signed-off-by: jimmy.wu Change-Id: I5be61b6bbe70db1999820d1760bdc393dca5a679 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739112 Reviewed-by: Andrew McRae --- zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml | 8 ++-- zephyr/dts/bindings/battery/smp,l22m3pg0.yaml | 6 +-- zephyr/dts/bindings/battery/smp,l22m3pg1.yaml | 54 ++++++++++++++++++++++ zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml | 10 ++-- zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml | 54 ++++++++++++++++++++++ 5 files changed, 120 insertions(+), 12 deletions(-) create mode 100644 zephyr/dts/bindings/battery/smp,l22m3pg1.yaml create mode 100644 zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml diff --git a/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml index 64ac926990..3354866154 100644 --- a/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml +++ b/zephyr/dts/bindings/battery/celxpert,l22c3pg0.yaml @@ -24,11 +24,11 @@ properties: fet_mfgacc_support: default: 0 fet_reg_addr: - default: 0x34 + default: 0x00 fet_reg_mask: - default: 0x0100 + default: 0x0018 fet_disconnect_val: - default: 0x0100 + default: 0x0000 # Battery info voltage_max: @@ -50,5 +50,5 @@ properties: discharging_min_c: default: -20 discharging_max_c: - default: 70 + default: 60 diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml index e0b9722675..6060e75f50 100644 --- a/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml +++ b/zephyr/dts/bindings/battery/smp,l22m3pg0.yaml @@ -24,11 +24,11 @@ properties: fet_mfgacc_support: default: 0 fet_reg_addr: - default: 0x34 + default: 0x00 fet_reg_mask: - default: 0x0100 + default: 0x0018 fet_disconnect_val: - default: 0x0100 + default: 0x0000 # Battery info voltage_max: diff --git a/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml new file mode 100644 index 0000000000..42a248fe34 --- /dev/null +++ b/zephyr/dts/bindings/battery/smp,l22m3pg1.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "SMP L22M3PG1" +compatible: "smp,l22m3pg1" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "smp,l22m3pg1" + + # Fuel gauge + manuf_name: + default: "SMP" + device_name: + default: "L22M3PG1" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x00 + fet_reg_mask: + default: 0x0018 + fet_disconnect_val: + default: 0x0000 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11520 + voltage_min: + default: 9000 + precharge_current: + default: 248 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 60 + diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml index 9d4da91747..e07d02cf9b 100644 --- a/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml +++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg0.yaml @@ -24,11 +24,11 @@ properties: fet_mfgacc_support: default: 0 fet_reg_addr: - default: 0x34 + default: 0x00 fet_reg_mask: - default: 0x0100 + default: 0x0018 fet_disconnect_val: - default: 0x0100 + default: 0x0000 # Battery info voltage_max: @@ -46,9 +46,9 @@ properties: charging_min_c: default: 0 charging_max_c: - default: 63 + default: 60 discharging_min_c: default: -20 discharging_max_c: - default: 63 + default: 60 diff --git a/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml new file mode 100644 index 0000000000..c17e287443 --- /dev/null +++ b/zephyr/dts/bindings/battery/sunwoda,l22d3pg1.yaml @@ -0,0 +1,54 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "SUNWODA L22D3PG1" +compatible: "sunwoda,l22d3pg1" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "sunwoda,l22d3pg1" + + # Fuel gauge + manuf_name: + default: "Sunwoda" + device_name: + default: "L22D3PG1" + ship_mode_reg_addr: + default: 0x34 + ship_mode_reg_data: + default: [ 0x0000, 0x1000 ] + fet_mfgacc_support: + default: 0 + fet_reg_addr: + default: 0x00 + fet_reg_mask: + default: 0x0018 + fet_disconnect_val: + default: 0x0000 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11520 + voltage_min: + default: 9000 + precharge_current: + default: 251 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 60 + -- cgit v1.2.1 From 94091319db02b44a9f003b9a1cd15f7e85c27401 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Fri, 1 Jul 2022 11:52:38 +0800 Subject: Nereid: Do not enable i2c4 on SKU2 (HDMI+type A) Since the SKU doesn't use i2c4, disable it to ensure that EC can enter deep doze mode in the s0ix state. BRANCH=none BUG=b:236668079, b:237717730 TEST=Verified that EC can enter deep doze mode in the s0ix state. Signed-off-by: Dino Li Change-Id: I3fe47d5656c8489467f38e3201c5f5cf0c447ccd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739988 Reviewed-by: Peter Marheine --- zephyr/projects/nissa/nereid_overlay.dts | 13 ++++++++++++- zephyr/projects/nissa/src/sub_board.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index 112411e5cc..3f56f74364 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -277,6 +277,15 @@ pinctrl-names = "default"; }; +&pinctrl { + i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; + }; + i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; + }; +}; + &i2c0 { label = "I2C_EEPROM"; clock-frequency = ; @@ -316,7 +325,9 @@ clock-frequency = ; pinctrl-0 = <&i2c4_clk_gpe0_default &i2c4_data_gpe7_default>; - pinctrl-names = "default"; + pinctrl-1 = <&i2c4_clk_gpe0_sleep + &i2c4_data_gpe7_sleep>; + pinctrl-names = "default", "sleep"; }; &i2c_ec_i2c_sub_usb_c1 { diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c index 38c7f1f616..688fce0584 100644 --- a/zephyr/projects/nissa/src/sub_board.c +++ b/zephyr/projects/nissa/src/sub_board.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -86,6 +87,30 @@ static void lte_power_handler(struct ap_power_ev_callback *cb, } } +#ifdef CONFIG_SOC_IT8XXX2 +/* + * On it8xxx2, the below condition will break the EC to enter deep doze mode + * (b:237717730): + * Enhance i2c (GPE0/E7, GPH1/GPH2 or GPA4/GPA5) is enabled and its clock and + * data pins aren't both at high level. + * + * Since HDMI+type A SKU doesn't use i2c4, disable it for better power number. + */ +#define I2C4_NODE DT_NODELABEL(i2c4) +#if DT_NODE_EXISTS(I2C4_NODE) +PINCTRL_DT_DEFINE(I2C4_NODE); + +/* disable i2c4 alternate function */ +static void soc_it8xxx2_disable_i2c4_alt(void) +{ + const struct pinctrl_dev_config *pcfg = + PINCTRL_DT_DEV_CONFIG_GET(I2C4_NODE); + + pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP); +} +#endif +#endif /* CONFIG_SOC_IT8XXX2 */ + /** * Configure GPIOs (and other pin functions) that vary with present sub-board. * @@ -145,6 +170,10 @@ static void nereid_subboard_config(void) static struct gpio_callback hdmi_hpd_cb; int rv, irq_key; +#if CONFIG_SOC_IT8XXX2 && DT_NODE_EXISTS(I2C4_NODE) + /* disable i2c4 alternate function for better power number */ + soc_it8xxx2_disable_i2c4_alt(); +#endif /* HDMI power enable outputs */ gpio_pin_configure_dt(GPIO_DT_FROM_ALIAS(gpio_en_rails_odl), GPIO_OUTPUT_INACTIVE | GPIO_OPEN_DRAIN | -- cgit v1.2.1 From 742cbc8e6c1188afb52a2e0761be179a9216b37b Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Thu, 30 Jun 2022 10:41:58 +0800 Subject: tentacruel: Implement LED function Config the EC LED setting. BUG=b:237593733 TEST=zmake build tentacruel --clobber BRANCH=None Signed-off-by: jeffrey_lin Change-Id: I0dd5444fb1ebf41bed5f795e836bc36b188806de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3737302 Reviewed-by: Chen-Tsung Hsieh Reviewed-by: Jacky Wang Reviewed-by: Ting Shen --- .../projects/corsola/src/krabby/led_tentacruel.c | 30 +++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/zephyr/projects/corsola/src/krabby/led_tentacruel.c b/zephyr/projects/corsola/src/krabby/led_tentacruel.c index e1f0d11575..18a66752e2 100644 --- a/zephyr/projects/corsola/src/krabby/led_tentacruel.c +++ b/zephyr/projects/corsola/src/krabby/led_tentacruel.c @@ -5,8 +5,8 @@ #include #include - #include "board_led.h" +#include "chipset.h" #include "common.h" #include "led_common.h" #include "led_onoff_states.h" @@ -37,11 +37,14 @@ __override struct led_descriptor LED_INDEFINITE } }, [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, - [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, + LED_INDEFINITE } }, [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC }, { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, + [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, + 1 * LED_ONE_SEC }, + { LED_OFF, 3 * LED_ONE_SEC } }, [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC }, @@ -155,3 +158,24 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) return EC_SUCCESS; } + +__override enum led_states board_led_get_state(enum led_states desired_state) +{ + /* + * Battery error LED behavior as below: + * S0: Blinking Amber LED, 1s on/ 1s off + * S3/S5: following S3/S5 behavior + * Add function to let battery error LED follow S3/S5 behavior in S3/S5. + */ + + if (desired_state == STATE_BATTERY_ERROR) { + if (chipset_in_state(CHIPSET_STATE_ON)) { + return desired_state; + } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { + return STATE_DISCHARGE_S3; + } else { + return STATE_DISCHARGE_S5; + } + } + return desired_state; +} -- cgit v1.2.1 From 5f83422692c525f301510528c4497984ce342a07 Mon Sep 17 00:00:00 2001 From: "Jes B. Klinke" Date: Thu, 7 Apr 2022 09:39:49 -0700 Subject: board/hyperdebug: Add board for OpenTitan development HyperDebug is a USB-connected device, which is to be used in conjunction with an OpenTitan development board during development of OpenTitan firmware. HyperDebug will serve a purpose similar to uServo, that is, it will forward several UART ports via USB, and allow GPIO and SPI/I2C manipulation via USB from the development host computer. This CL adds the first iteration of board/hyperdebug, with declaration for UART, SPI and I2C forwarding, and names for each GPIO pin based on its physical location on on of two 70-pin DIL expansion ports on the HyperDebug board. BUG=b:192262089 TEST=User HyperDebug in place of UltraDebug for uploading firmware \ and sending TPM commands to AndreiBoard BRANCH=none Signed-off-by: Jes B. Klinke Change-Id: I44b26d2890d0d4ed44d6bcd59a4de992a594c03f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086363 Reviewed-by: Aseda Aboagye --- board/hyperdebug/board.c | 368 +++++++++++++++++++++++++++++++++++++++++++ board/hyperdebug/board.h | 154 ++++++++++++++++++ board/hyperdebug/build.mk | 13 ++ board/hyperdebug/ec.tasklist | 11 ++ board/hyperdebug/gpio.inc | 191 ++++++++++++++++++++++ 5 files changed, 737 insertions(+) create mode 100644 board/hyperdebug/board.c create mode 100644 board/hyperdebug/board.h create mode 100644 board/hyperdebug/build.mk create mode 100644 board/hyperdebug/ec.tasklist create mode 100644 board/hyperdebug/gpio.inc diff --git a/board/hyperdebug/board.c b/board/hyperdebug/board.c new file mode 100644 index 0000000000..ab822fc054 --- /dev/null +++ b/board/hyperdebug/board.c @@ -0,0 +1,368 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* HyperDebug board configuration */ + +#include "common.h" +#include "console.h" +#include "ec_version.h" +#include "gpio.h" +#include "i2c.h" +#include "queue_policies.h" +#include "registers.h" +#include "spi.h" +#include "task.h" +#include "timer.h" +#include "usart-stm32l5.h" +#include "usb_hw.h" +#include "usb_spi.h" +#include "usb-stream.h" +#include "gpio_list.h" + +void board_config_pre_init(void) +{ + /* enable SYSCFG clock */ + STM32_RCC_APB2ENR |= STM32_RCC_SYSCFGEN; +} + +/****************************************************************************** + * Forward UARTs as a USB serial interface. + */ + +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 + +/****************************************************************************** + * Forward USART1 as a simple USB serial interface. + */ + +static struct usart_config const usart1; +struct usb_stream_config const usart1_usb; + +static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t, + usart1.producer, usart1_usb.consumer); +static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t, + usart1_usb.producer, usart1.consumer); + +static struct usart_config const usart1 = + USART_CONFIG(usart1_hw, + usart_rx_interrupt, + usart_tx_interrupt, + 115200, + 0, + usart1_to_usb, + usb_to_usart1); + +USB_STREAM_CONFIG(usart1_usb, + USB_IFACE_USART1_STREAM, + USB_STR_USART1_STREAM_NAME, + USB_EP_USART1_STREAM, + USB_STREAM_RX_SIZE, + USB_STREAM_TX_SIZE, + usb_to_usart1, + usart1_to_usb) + +/****************************************************************************** + * Forward USART2 as a simple USB serial interface. + */ + +static struct usart_config const usart2; +struct usb_stream_config const usart2_usb; + +static struct queue const usart2_to_usb = QUEUE_DIRECT(64, uint8_t, + usart2.producer, usart2_usb.consumer); +static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t, + usart2_usb.producer, usart2.consumer); + +static struct usart_config const usart2 = + USART_CONFIG(usart2_hw, + usart_rx_interrupt, + usart_tx_interrupt, + 115200, + 0, + usart2_to_usb, + usb_to_usart2); + +USB_STREAM_CONFIG(usart2_usb, + USB_IFACE_USART2_STREAM, + USB_STR_USART2_STREAM_NAME, + USB_EP_USART2_STREAM, + USB_STREAM_RX_SIZE, + USB_STREAM_TX_SIZE, + usb_to_usart2, + usart2_to_usb) + +/****************************************************************************** + * Forward USART4 as a simple USB serial interface. + */ + +static struct usart_config const usart4; +struct usb_stream_config const usart4_usb; + +static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, + usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, + usart4_usb.producer, usart4.consumer); + +static struct usart_config const usart4 = + USART_CONFIG(usart4_hw, + usart_rx_interrupt, + usart_tx_interrupt, + 115200, + 0, + usart4_to_usb, + usb_to_usart4); + +USB_STREAM_CONFIG(usart4_usb, + USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, + USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, + USB_STREAM_TX_SIZE, + usb_to_usart4, + usart4_to_usb) + +/****************************************************************************** + * Forward LPUART (USART9) as a simple USB serial interface. + */ + +static struct usart_config const usart9; +struct usb_stream_config const usart9_usb; + +static struct queue const usart9_to_usb = QUEUE_DIRECT(64, uint8_t, + usart9.producer, usart9_usb.consumer); +static struct queue const usb_to_usart9 = QUEUE_DIRECT(64, uint8_t, + usart9_usb.producer, usart9.consumer); + +static struct usart_config const usart9 = + USART_CONFIG(usart9_hw, + usart_rx_interrupt, + usart_tx_interrupt, + 115200, + 0, + usart9_to_usb, + usb_to_usart9); + +USB_STREAM_CONFIG(usart9_usb, + USB_IFACE_USART9_STREAM, + USB_STR_USART9_STREAM_NAME, + USB_EP_USART9_STREAM, + USB_STREAM_RX_SIZE, + USB_STREAM_TX_SIZE, + usb_to_usart9, + usart9_to_usb) + +/****************************************************************************** + * Support SPI bridging over USB, this requires usb_spi_board_enable and + * usb_spi_board_disable to be defined to enable and disable the SPI bridge. + */ + +/* SPI devices */ +const struct spi_device_t spi_devices[] = { + { 1 /* SPI2 */, 7, GPIO_SPI2_CS}, +}; +const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); + +void usb_spi_board_enable(struct usb_spi_config const *config) +{ + /* Configure SPI GPIOs */ + gpio_config_module(MODULE_SPI, 1); + gpio_config_module(MODULE_SPI_FLASH, 1); + + /* Set all SPI pins to high speed */ + STM32_GPIO_OSPEEDR(GPIO_F) |= 0xFFF00000; + STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000000C3; + STM32_GPIO_OSPEEDR(GPIO_C) |= 0x000000F0; + + /* Enable clocks to SPI2 module */ + STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_SPI2EN; + + /* Reset SPI2 */ + STM32_RCC_APB1RSTR1 |= STM32_RCC_APB1RSTR1_SPI2RST; + STM32_RCC_APB1RSTR1 &= ~STM32_RCC_APB1RSTR1_SPI2RST; + + spi_enable(&spi_devices[0], 1); +} + +void usb_spi_board_disable(struct usb_spi_config const *config) +{ + spi_enable(&spi_devices[0], 0); + + /* Disable clocks to SPI2 module */ + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; + + /* Release SPI GPIOs */ + gpio_config_module(MODULE_SPI_FLASH, 0); +} + +USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0); + +/****************************************************************************** + * Support I2C bridging over USB. + */ + +/* I2C ports */ +const struct i2c_port_t i2c_ports[] = { + { + .name = "controller", + .port = I2C_PORT_CONTROLLER, + .kbps = 100, + .scl = GPIO_TPM_I2C1_HOST_SCL, + .sda = GPIO_TPM_I2C1_HOST_SDA + }, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +int usb_i2c_board_is_enabled(void) { return 1; } + +/****************************************************************************** + * Define the strings used in our USB descriptors. + */ + +const void *const usb_strings[] = { + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("HyperDebug"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("HyperDebug Shell"), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("UART1"), + [USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("UART2"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART4"), + [USB_STR_USART9_STREAM_NAME] = USB_STRING_DESC("UART9"), +}; + +BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); + +/****************************************************************************** + * Initialize board. + */ + +static void board_init(void) +{ + STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0x0000FF00; + + /* We know VDDIO2 is present, enable the GPIO circuit. */ + STM32_PWR_CR2 |= STM32_PWR_CR2_IOSV; + + /* USB to serial queues */ + queue_init(&usart1_to_usb); + queue_init(&usb_to_usart1); + queue_init(&usart2_to_usb); + queue_init(&usb_to_usart2); + queue_init(&usart4_to_usb); + queue_init(&usb_to_usart4); + queue_init(&usart9_to_usb); + queue_init(&usb_to_usart9); + + STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0x0F000000; + /* UART init */ + usart_init(&usart1); + usart_init(&usart2); + usart_init(&usart4); + usart_init(&usart9); + + /* Structured endpoints */ + usb_spi_enable(&usb_spi, 1); + STM32_GPIO_BSRR(STM32_GPIOE_BASE) |= 0xF0000000; +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +/** + * Find a GPIO signal by name. + * + * This is copied from gpio.c unfortunately, as it is static over there. + * + * @param name Signal name to find + * + * @return the signal index, or GPIO_COUNT if no match. + */ +static enum gpio_signal find_signal_by_name(const char *name) +{ + int i; + + if (!name || !*name) + return GPIO_COUNT; + + for (i = 0; i < GPIO_COUNT; i++) + if (gpio_is_implemented(i) && + !strcasecmp(name, gpio_get_name(i))) + return i; + + return GPIO_COUNT; +} + +/* + * Set the mode of a GPIO pin: input/opendrain/pushpull. + */ +static int command_gpio_mode(int argc, char **argv) +{ + int gpio; + int flags; + + if (argc < 3) + return EC_ERROR_PARAM_COUNT; + + gpio = find_signal_by_name(argv[1]); + if (gpio == GPIO_COUNT) + return EC_ERROR_PARAM1; + flags = gpio_get_flags(gpio); + + flags = flags & ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OPEN_DRAIN); + if (strcasecmp(argv[2], "input") == 0) + flags |= GPIO_INPUT; + else if (strcasecmp(argv[2], "opendrain") == 0) + flags |= GPIO_OUTPUT | GPIO_OPEN_DRAIN; + else if (strcasecmp(argv[2], "pushpull") == 0) + flags |= GPIO_OUTPUT; + else + return EC_ERROR_PARAM2; + + /* Update GPIO flags. */ + gpio_set_flags(gpio, flags); + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND_FLAGS(gpiomode, command_gpio_mode, + "name ", + "Set a GPIO mode", + CMD_FLAG_RESTRICTED +); + +/* + * Set the weak pulling of a GPIO pin: up/down/none. + */ +static int command_gpio_pull_mode(int argc, char **argv) +{ + int gpio; + int flags; + + if (argc < 3) + return EC_ERROR_PARAM_COUNT; + + gpio = find_signal_by_name(argv[1]); + if (gpio == GPIO_COUNT) + return EC_ERROR_PARAM1; + flags = gpio_get_flags(gpio); + + flags = flags & ~(GPIO_PULL_UP | GPIO_PULL_DOWN); + if (strcasecmp(argv[2], "none") == 0) + ; + else if (strcasecmp(argv[2], "up") == 0) + flags |= GPIO_PULL_UP; + else if (strcasecmp(argv[2], "down") == 0) + flags |= GPIO_PULL_DOWN; + else + return EC_ERROR_PARAM2; + + /* Update GPIO flags. */ + gpio_set_flags(gpio, flags); + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND_FLAGS(gpiopullmode, command_gpio_pull_mode, + "name ", + "Set a GPIO weak pull mode", + CMD_FLAG_RESTRICTED +); diff --git a/board/hyperdebug/board.h b/board/hyperdebug/board.h new file mode 100644 index 0000000000..e58921e704 --- /dev/null +++ b/board/hyperdebug/board.h @@ -0,0 +1,154 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* HyperDebug configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +#define CONFIG_LTO + +/* 48 MHz SYSCLK clock frequency */ +#define CPU_CLOCK 48000000 + +#define CONFIG_BOARD_PRE_INIT + +#define CONFIG_ROM_BASE 0x0 +#define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE) + +/* Enable USB forwarding on UART 1, 2, 4 and the LPUART (UART9) */ +#define CONFIG_STREAM_USART +#define CONFIG_STREAM_USART1 +#define CONFIG_STREAM_USART2 +#undef CONFIG_STREAM_USART3 +#define CONFIG_STREAM_USART4 +#undef CONFIG_STREAM_USART5 +#define CONFIG_STREAM_USART9 +#define CONFIG_STREAM_USB +#define CONFIG_CMD_USART_INFO + +/* The UART console is on UART3 */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 3 +#undef CONFIG_UART_TX_DMA +#undef CONFIG_UART_RX_DMA + +/* Optional features */ +#define CONFIG_STM_HWTIMER32 +#define CONFIG_HW_CRC +#undef CONFIG_PVD +/* + * See 'Programmable voltage detector characteristics' in the + * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a falling + * voltage threshold of min:2.09V, max:2.27V. + */ +#define PVD_THRESHOLD (1) + +/* USB Configuration */ + +#define CONFIG_USB +#define CONFIG_USB_PID 0x520e +#define CONFIG_USB_CONSOLE + +/* + * Enabling USB updating would exceed the number of USB endpoints + * supported by the hardware. We will have to rely on the built-in + * DFU support of STM32 chips. + */ +#undef CONFIG_USB_UPDATE + +#undef CONFIG_USB_MAXPOWER_MA +#define CONFIG_USB_MAXPOWER_MA 100 + +#define CONFIG_USB_SERIALNO +#define DEFAULT_SERIALNO "Uninitialized" + +/* USB interface indexes (use define rather than enum to expand them) */ +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_SPI 1 +#define USB_IFACE_I2C 2 +#define USB_IFACE_USART1_STREAM 3 +#define USB_IFACE_USART2_STREAM 4 +#define USB_IFACE_USART4_STREAM 5 +#define USB_IFACE_USART9_STREAM 6 +#define USB_IFACE_COUNT 7 + +/* USB endpoint indexes (use define rather than enum to expand them) */ +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_SPI 2 +#define USB_EP_I2C 3 +#define USB_EP_USART1_STREAM 4 +#define USB_EP_USART2_STREAM 5 +#define USB_EP_USART4_STREAM 6 +#define USB_EP_USART9_STREAM 7 +#define USB_EP_COUNT 8 + +/* + * Do not enable the common EC command gpioset for recasting of GPIO + * type. Instead, board specific commands are used for implementing + * the OpenTitan tool requirements. + */ +#undef CONFIG_CMD_GPIO_EXTENDED +#define CONFIG_GPIO_GET_EXTENDED + +/* Enable control of SPI over USB */ +#define CONFIG_USB_SPI +#define CONFIG_USB_SPI_BUFFER_SIZE 2048 +#define CONFIG_SPI_CONTROLLER + +/* Enable control of I2C over USB */ +#define CONFIG_USB_I2C +#define CONFIG_I2C +#define CONFIG_I2C_CONTROLLER +#define I2C_PORT_CONTROLLER 0 +#define CONFIG_STM32_SPI1_CONTROLLER + + +/* See i2c_ite_flash_support.c for more information about these values */ +/*#define CONFIG_ITE_FLASH_SUPPORT */ +/*#define CONFIG_I2C_XFER_LARGE_TRANSFER */ +#undef CONFIG_USB_I2C_MAX_WRITE_COUNT +#undef CONFIG_USB_I2C_MAX_READ_COUNT +#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4) +#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6) + +/* This is not actually an EC so disable some features. */ +#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_LID_SWITCH + +/* + * Allow dangerous commands all the time, since we don't have a write protect + * switch. + */ +#define CONFIG_SYSTEM_UNLOCKED + +#ifndef __ASSEMBLER__ + +/* Timer selection */ +#define TIM_CLOCK32 2 + +#include "gpio_signal.h" + +/* USB string indexes */ +enum usb_strings { + USB_STR_DESC = 0, + USB_STR_VENDOR, + USB_STR_PRODUCT, + USB_STR_SERIALNO, + USB_STR_VERSION, + USB_STR_CONSOLE_NAME, + USB_STR_SPI_NAME, + USB_STR_I2C_NAME, + USB_STR_USART1_STREAM_NAME, + USB_STR_USART2_STREAM_NAME, + USB_STR_USART4_STREAM_NAME, + USB_STR_USART9_STREAM_NAME, + + USB_STR_COUNT +}; + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/hyperdebug/build.mk b/board/hyperdebug/build.mk new file mode 100644 index 0000000000..140ec9f8c2 --- /dev/null +++ b/board/hyperdebug/build.mk @@ -0,0 +1,13 @@ +# -*- makefile -*- +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is STmicro STM32F302R8 +CHIP:=stm32 +CHIP_FAMILY:=stm32l5 +CHIP_VARIANT:=stm32l552xe + +board-y=board.o diff --git a/board/hyperdebug/ec.tasklist b/board/hyperdebug/ec.tasklist new file mode 100644 index 0000000000..650d5f3550 --- /dev/null +++ b/board/hyperdebug/ec.tasklist @@ -0,0 +1,11 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) diff --git a/board/hyperdebug/gpio.inc b/board/hyperdebug/gpio.inc new file mode 100644 index 0000000000..5ea99ec7a4 --- /dev/null +++ b/board/hyperdebug/gpio.inc @@ -0,0 +1,191 @@ +/* -*- mode:c -*- + * + * Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of all GPIO pins available for Host computer to manipulate. + * The are named based on their location on the two 70-pin DIL + * connectors on either side of the HyperDebug board. Pins with + * special functions are commented out, and declared with relevant + * symbolic name further below. + */ +GPIO(CN11_1, PIN(C, 10), GPIO_INPUT) +GPIO(CN11_2, PIN(C, 11), GPIO_INPUT) +GPIO(CN11_3, PIN(C, 12), GPIO_INPUT) +GPIO(CN11_4, PIN(D, 2), GPIO_INPUT) +GPIO(CN11_7, PIN(H, 3), GPIO_INPUT) +GPIO(CN11_9, PIN(F, 6), GPIO_INPUT) +GPIO(CN11_11, PIN(F, 7), GPIO_INPUT) +/*GPIO(CN11_13, PIN(A, 13), GPIO_INPUT) SWDIO */ +/*GPIO(CN11_15, PIN(A, 14), GPIO_INPUT) SWCLK */ +GPIO(CN11_17, PIN(A, 15), GPIO_INPUT) +/*GPIO(CN11_21, PIN(B, 7), GPIO_INPUT) Nucleo LED */ +GPIO(CN11_23, PIN(C, 13), GPIO_INPUT) +GPIO(CN11_25, PIN(C, 14), GPIO_INPUT) +GPIO(CN11_27, PIN(C, 15), GPIO_INPUT) +/*GPIO(CN11_28, PIN(A, 0), GPIO_INPUT) UART4 */ +GPIO(CN11_29, PIN(H, 0), GPIO_INPUT) +/*GPIO(CN11_30, PIN(A, 1), GPIO_INPUT) UART4 */ +GPIO(CN11_31, PIN(H, 1), GPIO_INPUT) +/*GPIO(CN11_32, PIN(A, 4), GPIO_INPUT) USB CC */ +GPIO(CN11_34, PIN(B, 0), GPIO_INPUT) +/*GPIO(CN11_35, PIN(C, 2), GPIO_INPUT) SPI2 */ +GPIO(CN11_36, PIN(C, 1), GPIO_INPUT) +/*GPIO(CN11_37, PIN(C, 3), GPIO_INPUT) SPI2 */ +GPIO(CN11_38, PIN(C, 0), GPIO_INPUT) +GPIO(CN11_39, PIN(D, 4), GPIO_INPUT) +GPIO(CN11_40, PIN(D, 3), GPIO_INPUT) +GPIO(CN11_41, PIN(D, 5), GPIO_INPUT) +GPIO(CN11_42, PIN(G, 2), GPIO_INPUT) +GPIO(CN11_43, PIN(D, 6), GPIO_INPUT) +GPIO(CN11_44, PIN(G, 3), GPIO_INPUT) +GPIO(CN11_45, PIN(D, 7), GPIO_INPUT) +GPIO(CN11_46, PIN(E, 2), GPIO_INPUT) +GPIO(CN11_47, PIN(E, 3), GPIO_INPUT) +GPIO(CN11_48, PIN(E, 4), GPIO_INPUT) +GPIO(CN11_50, PIN(E, 5), GPIO_INPUT) +GPIO(CN11_51, PIN(F, 1), GPIO_INPUT) +GPIO(CN11_52, PIN(F, 2), GPIO_INPUT) +GPIO(CN11_53, PIN(F, 0), GPIO_INPUT) +GPIO(CN11_54, PIN(F, 8), GPIO_INPUT) +/*GPIO(CN11_55, PIN(D, 1), GPIO_INPUT) SPI2 */ +GPIO(CN11_56, PIN(F, 9), GPIO_INPUT) +/*GPIO(CN11_57, PIN(D, 0), GPIO_INPUT) SPI2 */ +GPIO(CN11_58, PIN(G, 1), GPIO_INPUT) +GPIO(CN11_59, PIN(G, 0), GPIO_INPUT) +/*GPIO(CN11_61, PIN(E, 1), GPIO_INPUT) */ +GPIO(CN11_62, PIN(E, 6), GPIO_INPUT) +/*GPIO(CN11_63, PIN(G, 9), GPIO_INPUT) UART1 */ +GPIO(CN11_64, PIN(G, 15), GPIO_INPUT) +GPIO(CN11_65, PIN(G, 12), GPIO_INPUT) +/*GPIO(CN11_66, PIN(G, 10), GPIO_INPUT) UART1 */ +/*GPIO(CN11_68, PIN(G, 13), GPIO_INPUT) I2C1 */ +/*GPIO(CN11_69, PIN(D, 9), GPIO_INPUT) UART3 */ +GPIO(CN12_1, PIN(C, 9), GPIO_INPUT) +GPIO(CN12_2, PIN(C, 8), GPIO_INPUT) +GPIO(CN12_3, PIN(B, 8), GPIO_INPUT) +GPIO(CN12_4, PIN(C, 6), GPIO_INPUT) +GPIO(CN12_5, PIN(B, 9), GPIO_INPUT) +/*GPIO(CN12_10, PIN(D, 8), GPIO_INPUT) UART3 */ +/*GPIO(CN12_11, PIN(A, 5), GPIO_INPUT) USB CC */ +/*GPIO(CN12_12, PIN(A, 12), GPIO_INPUT) USB */ +GPIO(CN12_13, PIN(A, 6), GPIO_INPUT) +/*GPIO(CN12_14, PIN(A, 11), GPIO_INPUT) USB */ +GPIO(CN12_15, PIN(A, 7), GPIO_INPUT) +GPIO(CN12_17, PIN(B, 6), GPIO_INPUT) +GPIO(CN12_18, PIN(B, 11), GPIO_INPUT) +/*GPIO(CN12_19, PIN(C, 7), GPIO_INPUT) Nucleo LED */ +/*GPIO(CN12_21, PIN(A, 9), GPIO_INPUT) Nucleo LED */ +GPIO(CN12_22, PIN(B, 2), GPIO_INPUT) +GPIO(CN12_23, PIN(A, 8), GPIO_INPUT) +GPIO(CN12_24, PIN(B, 1), GPIO_INPUT) +GPIO(CN12_25, PIN(B, 10), GPIO_INPUT) +GPIO(CN12_26, PIN(B, 15), GPIO_INPUT) +GPIO(CN12_27, PIN(B, 4), GPIO_INPUT) +/*GPIO(CN12_28, PIN(B, 14), GPIO_INPUT) I2C2 */ +GPIO(CN12_29, PIN(B, 5), GPIO_INPUT) +/*GPIO(CN12_30, PIN(B, 13), GPIO_INPUT) I2C2 */ +GPIO(CN12_31, PIN(B, 3), GPIO_INPUT) +GPIO(CN12_33, PIN(A, 10), GPIO_INPUT) +/*GPIO(CN12_35, PIN(A, 2), GPIO_INPUT) UART2 */ +GPIO(CN12_36, PIN(F, 5), GPIO_INPUT) +/*GPIO(CN12_37, PIN(A, 3), GPIO_INPUT) UART2 */ +GPIO(CN12_38, PIN(F, 4), GPIO_INPUT) +GPIO(CN12_40, PIN(E, 8), GPIO_INPUT) +GPIO(CN12_41, PIN(D, 13), GPIO_INPUT) +GPIO(CN12_42, PIN(F, 10), GPIO_INPUT) +GPIO(CN12_43, PIN(D, 12), GPIO_INPUT) +GPIO(CN12_44, PIN(E, 7), GPIO_INPUT) +GPIO(CN12_45, PIN(D, 11), GPIO_INPUT) +GPIO(CN12_46, PIN(D, 14), GPIO_INPUT) +/*GPIO(CN12_47, PIN(E, 10), GPIO_INPUT) */ +GPIO(CN12_48, PIN(D, 15), GPIO_INPUT) +/*GPIO(CN12_49, PIN(E, 12), GPIO_INPUT) */ +GPIO(CN12_50, PIN(F, 14), GPIO_INPUT) +/*GPIO(CN12_51, PIN(E, 14), GPIO_INPUT) */ +GPIO(CN12_52, PIN(E, 9), GPIO_INPUT) +/*GPIO(CN12_53, PIN(E, 15), GPIO_INPUT) */ +/*GPIO(CN12_55, PIN(E, 13), GPIO_INPUT) */ +/*GPIO(CN12_56, PIN(E, 11), GPIO_INPUT) */ +GPIO(CN12_57, PIN(F, 13), GPIO_INPUT) +GPIO(CN12_58, PIN(F, 3), GPIO_INPUT) +GPIO(CN12_59, PIN(F, 12), GPIO_INPUT) +GPIO(CN12_60, PIN(F, 15), GPIO_INPUT) +/*GPIO(CN12_61, PIN(G, 14), GPIO_INPUT) I2C1 */ +GPIO(CN12_62, PIN(F, 11), GPIO_INPUT) +GPIO(CN12_64, PIN(E, 0), GPIO_INPUT) +GPIO(CN12_65, PIN(D, 10), GPIO_INPUT) +/*GPIO(CN12_66, PIN(G, 8), GPIO_INPUT) LPUART */ +/*GPIO(CN12_67, PIN(G, 7), GPIO_INPUT) LPUART */ +GPIO(CN12_68, PIN(G, 5), GPIO_INPUT) +GPIO(CN12_69, PIN(G, 4), GPIO_INPUT) +GPIO(CN12_70, PIN(G, 6), GPIO_INPUT) + +GPIO(POR_N, PIN(E, 1), GPIO_INPUT) + +GPIO(QSPI_DEV_CLK, PIN(E, 10), GPIO_OUT_LOW) +GPIO(QSPI_DEV_CS_L, PIN(E, 11), GPIO_OUT_LOW) +GPIO(QSPI_DEV_D0, PIN(E, 12), GPIO_OUT_LOW) +GPIO(QSPI_DEV_D1, PIN(E, 13), GPIO_OUT_LOW) +GPIO(QSPI_DEV_D2, PIN(E, 14), GPIO_OUT_LOW) +GPIO(QSPI_DEV_D3, PIN(E, 15), GPIO_OUT_LOW) + +/* I2C pins should be configured as inputs until I2C module is */ +/* initialized. This will avoid driving the lines unintentionally.*/ +GPIO(TPM_I2C1_HOST_SCL, PIN(G, 14), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(TPM_I2C1_HOST_SDA, PIN(G, 13), GPIO_OUTPUT | GPIO_OPEN_DRAIN) +GPIO(INA_I2C2_DEV_SCL, PIN(B, 13), GPIO_ALTERNATE) +GPIO(INA_I2C2_DEV_SDA, PIN(B, 14), GPIO_ALTERNATE) + +/* These pins are used for USART and are set to alternate mode below */ +GPIO(USART1_AP_TX, PIN(G, 9), GPIO_INPUT) +GPIO(USART1_AP_RX, PIN(G, 10), GPIO_INPUT) +GPIO(USART2_OT_TX, PIN(A, 2), GPIO_INPUT) +GPIO(USART2_OT_RX, PIN(A, 3), GPIO_INPUT) +GPIO(USART3_FP_MCU_TX, PIN(D, 8), GPIO_INPUT) +GPIO(USART3_FP_MCU_RX, PIN(D, 9), GPIO_INPUT) +GPIO(USART4_EC_TX, PIN(A, 0), GPIO_INPUT) +GPIO(USART4_EC_RX, PIN(A, 1), GPIO_INPUT) +GPIO(LPUART1_HYPER_RX, PIN(G, 7), GPIO_INPUT) +GPIO(LPUART1_HYPER_TX, PIN(G, 8), GPIO_INPUT) + +GPIO(SPI2_CS, PIN(D, 0), GPIO_OUT_HIGH) +GPIO(SPI2_SCK, PIN(D, 1), GPIO_ALTERNATE) +GPIO(SPI2_CIDO, PIN(C, 2), GPIO_ALTERNATE) +GPIO(SPI2_CODI, PIN(C, 3), GPIO_ALTERNATE) + + +/* USB pins */ +GPIO(USB_FS_DM, PIN(A, 11), GPIO_ALTERNATE) +GPIO(USB_FS_DP, PIN(A, 12), GPIO_ALTERNATE) +GPIO(CC1, PIN(A, 4), GPIO_ANALOG) +GPIO(CC2, PIN(A, 5), GPIO_ANALOG) + +/* Signals for hardware on the Nucleo board itself */ +GPIO(NUCLEO_LED1, PIN(C, 7), GPIO_OUT_HIGH) /* Green */ +GPIO(NUCLEO_LED2, PIN(B, 7), GPIO_OUT_LOW) /* Blue */ +GPIO(NUCLEO_LED3, PIN(A, 9), GPIO_OUT_LOW) /* Red */ + +/* Unimplemented signals since we are not an EC */ +UNIMPLEMENTED(ENTERING_RW) +UNIMPLEMENTED(WP_L) + + +ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* USB: PA11/12 */ + +ALTERNATE(PIN_MASK(G, 0x0600), 7, MODULE_UART, 0) /* USART1: PG09/PG10 - AP UART */ +ALTERNATE(PIN_MASK(A, 0x000C), 7, MODULE_UART, 0) /* USART2: PA02/PA03 - OT UART */ +ALTERNATE(PIN_MASK(D, 0x0300), 7, MODULE_UART, 0) /* USART3: PD08/PD09 - HyperDebug console */ +ALTERNATE(PIN_MASK(A, 0x0003), 8, MODULE_UART, 0) /* USART4: PA00/PA01 - EC UART */ +ALTERNATE(PIN_MASK(G, 0x0180), 8, MODULE_UART, 0) /* LPUART1: PG07/PG08 - FP MCU UART */ + +ALTERNATE(PIN_MASK(B, 0x6000), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C2: PB13/14 */ +ALTERNATE(PIN_MASK(G, 0x6000), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1: PG13/14 */ +ALTERNATE(PIN_MASK(C, 0x0003), 4, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C3: PC00/01 */ +/*ALTERNATE(PIN_MASK(E, 0xFC00), 10, MODULE_SPI_FLASH, 0) / * QSPI: PE10-15 */ +/*ALTERNATE(PIN_MASK(D, 0x0001), 5, MODULE_SPI, 0) / * SPI2: PD00 CS */ +ALTERNATE(PIN_MASK(D, 0x0002), 5, MODULE_SPI, 0) /* SPI2: PD01 SCK */ +ALTERNATE(PIN_MASK(C, 0x000C), 5, MODULE_SPI, 0) /* SPI2: PC02/03 CIDO/DOCI */ -- cgit v1.2.1 From ec3a9e5f02217419940492e5009ff5b8c4835a5f Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Thu, 30 Jun 2022 17:09:11 +0530 Subject: nissa: use power-good-pin property of temperature sensors Legacy implementaion uses CONFIG_TEMP_SENSOR_POWER. Use power-good-pin property and disable this config. power-good-pin is mapped to GPIO EC dsw pwrok which indicates PP3300_A rail is up and stable. BUG=b:237343123 BRANCH=none TEST=Verify temperature sensor functionality on Nivviks zmake testall is successful Change-Id: I262b4d30ef44b87291b0622b116f2eaa2cec709e Signed-off-by: Deepti Deshatty Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739985 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/craask_overlay.dts | 2 ++ zephyr/projects/nissa/joxer_overlay.dts | 3 +++ zephyr/projects/nissa/nereid_overlay.dts | 3 +++ zephyr/projects/nissa/nivviks_overlay.dts | 2 ++ zephyr/projects/nissa/prj.conf | 1 - zephyr/projects/nissa/pujjo_overlay.dts | 2 ++ zephyr/projects/nissa/xivu_overlay.dts | 2 ++ 7 files changed, 14 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask_overlay.dts index 1ff3022124..f6d95db207 100644 --- a/zephyr/projects/nissa/craask_overlay.dts +++ b/zephyr/projects/nissa/craask_overlay.dts @@ -141,6 +141,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -154,6 +155,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index b777d13074..9f8cd1b864 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -156,6 +156,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -169,6 +170,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; ambient { compatible = "cros-ec,temp-sensor-thermistor", @@ -182,6 +184,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_3>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index 3f56f74364..95bfe2fa03 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -156,6 +156,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -169,6 +170,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; ambient { compatible = "cros-ec,temp-sensor-thermistor", @@ -182,6 +184,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_3>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts index bc10f510a5..7d9fb6008e 100644 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ b/zephyr/projects/nissa/nivviks_overlay.dts @@ -145,6 +145,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -158,6 +159,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; diff --git a/zephyr/projects/nissa/prj.conf b/zephyr/projects/nissa/prj.conf index df988de149..930db794b5 100644 --- a/zephyr/projects/nissa/prj.conf +++ b/zephyr/projects/nissa/prj.conf @@ -79,7 +79,6 @@ CONFIG_PLATFORM_EC_MKBP_USE_GPIO_AND_HOST_EVENT=y # Temperature sensor support CONFIG_PLATFORM_EC_TEMP_SENSOR=y CONFIG_PLATFORM_EC_THERMISTOR=y -CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y CONFIG_PLATFORM_EC_TEMP_SENSOR_FIRST_READ_DELAY=y # CBI EEPROM support diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts index c185d46e11..afa0b0b1c4 100644 --- a/zephyr/projects/nissa/pujjo_overlay.dts +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -145,6 +145,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -158,6 +159,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts index ecfd4e475d..7099b2e05a 100644 --- a/zephyr/projects/nissa/xivu_overlay.dts +++ b/zephyr/projects/nissa/xivu_overlay.dts @@ -126,6 +126,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_1>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; charger { compatible = "cros-ec,temp-sensor-thermistor", @@ -139,6 +140,7 @@ temp_host_halt = <90>; temp_host_release_high = <80>; adc = <&adc_temp_sensor_2>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; }; }; -- cgit v1.2.1 From 905412da08b88373f16be832b0d932d30402b13c Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Thu, 30 Jun 2022 13:04:45 +0800 Subject: power/mt8186: fix the init value of is_exiting_off is_exiting_off means that EC wants to leave S5/G3. If EC is already in S0 during initialization, this flag should be false. BUG=b:237499922 TEST=1) `reboot ro` 2) wait until device reaches S0 3) `sysjump rw` 4) `apshutdown` make sure AP stays at G3 BRANCH=none Signed-off-by: Ting Shen Change-Id: Ibac81cd5d1b62d153fc9aa77d33e04754bb0db9a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735621 Tested-by: Ting Shen Reviewed-by: Eric Yilun Lin Commit-Queue: Ting Shen --- power/mt8186.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/power/mt8186.c b/power/mt8186.c index fcbe94dcee..a9f871d3d6 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -298,9 +298,14 @@ enum power_state power_chipset_init(void) */ battery_wait_for_stable(); - if (exit_hard_off) - /* Auto-power on */ - mt8186_exit_off(); + if (exit_hard_off) { + if (init_state == POWER_S5 || init_state == POWER_G3) { + /* Auto-power on */ + mt8186_exit_off(); + } else { + is_exiting_off = false; + } + } if (init_state != POWER_G3 && !exit_hard_off) /* Force shutdown from S5 if the PMIC is already up. */ -- cgit v1.2.1 From 315d5adc57c19244865abbb6532a4dc16b30f31c Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 4 Jul 2022 19:55:59 +0800 Subject: dojo: Set up board SSFC parsing Set up basic file to use for parsing SSFC. Currently, SSFC is set to recognize 2nd source of base sensor and lid sensor. BUG=b:237963220 BRANCH=cherry TEST=make BOARD=dojo Signed-off-by: Tommy Chung Change-Id: I50af96214b2e263e704580b06ecf93d4f9c95295 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742857 Reviewed-by: Ting Shen Reviewed-by: Devin Lu Commit-Queue: Ting Shen --- board/dojo/build.mk | 2 +- board/dojo/cbi_ssfc.c | 36 ++++++++++++++++++++++++++++++++ board/dojo/cbi_ssfc.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 board/dojo/cbi_ssfc.c create mode 100644 board/dojo/cbi_ssfc.h diff --git a/board/dojo/build.mk b/board/dojo/build.mk index 25af05d562..e32df81d01 100644 --- a/board/dojo/build.mk +++ b/board/dojo/build.mk @@ -11,4 +11,4 @@ CHIP_FAMILY:=it8xxx2 CHIP_VARIANT:=it81202bx_1024 BASEBOARD:=cherry -board-y+=led.o battery.o board.o cbi_fw_config.o +board-y+=led.o battery.o board.o cbi_fw_config.o cbi_ssfc.o diff --git a/board/dojo/cbi_ssfc.c b/board/dojo/cbi_ssfc.c new file mode 100644 index 0000000000..6ece151e12 --- /dev/null +++ b/board/dojo/cbi_ssfc.c @@ -0,0 +1,36 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "cbi_ssfc.h" +#include "common.h" +#include "console.h" +#include "cros_board_info.h" +#include "hooks.h" + +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) + +/* Cache SSFC on init since we don't expect it to change in runtime */ +static union dojo_cbi_ssfc cached_ssfc; +BUILD_ASSERT(sizeof(cached_ssfc) == sizeof(uint32_t)); + +static void cbi_ssfc_init(void) +{ + if (cbi_get_ssfc(&cached_ssfc.raw_value) != EC_SUCCESS) + /* Default to 0 when CBI isn't populated */ + cached_ssfc.raw_value = 0; + + CPRINTS("Read CBI SSFC : 0x%04X", cached_ssfc.raw_value); +} +DECLARE_HOOK(HOOK_INIT, cbi_ssfc_init, HOOK_PRIO_FIRST); + +enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void) +{ + return (enum ec_ssfc_base_sensor)cached_ssfc.base_sensor; +} + +enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void) +{ + return (enum ec_ssfc_lid_sensor)cached_ssfc.lid_sensor; +} diff --git a/board/dojo/cbi_ssfc.h b/board/dojo/cbi_ssfc.h new file mode 100644 index 0000000000..53caad7ac8 --- /dev/null +++ b/board/dojo/cbi_ssfc.h @@ -0,0 +1,57 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef _DOJO_CBI_SSFC__H_ +#define _DOJO_CBI_SSFC__H_ + +#include "stdint.h" + +/**************************************************************************** + * Dojo CBI Second Source Factory Cache + */ + +/* + * Base Sensor (Bits 0-2) + */ +enum ec_ssfc_base_sensor { + SSFC_SENSOR_BASE_DEFAULT = 0, + SSFC_SENSOR_ICM42607 = 1, + SSFC_SENSOR_ICM426XX = 2, + SSFC_SENSOR_BMI260 = 3, +}; + +/* + * Lid Sensor (Bits 3-5) + */ +enum ec_ssfc_lid_sensor { + SSFC_SENSOR_LID_DEFAULT = 0, + SSFC_SENSOR_BMA422 = 1, + SSFC_SENSOR_KX022 = 2, +}; + +union dojo_cbi_ssfc { + struct { + uint32_t base_sensor : 3; + uint32_t lid_sensor : 3; + uint32_t reserved_2 : 26; + }; + uint32_t raw_value; +}; + +/** + * Get the Base sensor type from SSFC_CONFIG. + * + * @return the Base sensor board type. + */ +enum ec_ssfc_base_sensor get_cbi_ssfc_base_sensor(void); + +/** + * Get the Lid sensor type from SSFC_CONFIG. + * + * @return the Lid sensor board type. + */ +enum ec_ssfc_lid_sensor get_cbi_ssfc_lid_sensor(void); + +#endif /* _DOJO_CBI_SSFC__H_ */ -- cgit v1.2.1 From a7831a51a33f019e50bc80ab7992ea1c269e7b26 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 5 Jul 2022 13:15:40 +0000 Subject: zephyr: test: drop few macro that have been upstreamed These are now available upstream: https://github.com/zephyrproject-rtos/zephyr/pull/46961 Drop the internal definitions to avoid a "macro redefined" error. BRANCH=none BUG=b:217755888 TEST=zmake test test-drivers Signed-off-by: Fabio Baltieri Cq-Depend: chromium:3745817 Change-Id: I8829b772057401be42a7f628c86940716b1b907e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3746257 Reviewed-by: Yuval Peress --- zephyr/test/drivers/include/test/drivers/utils.h | 95 ------------------------ 1 file changed, 95 deletions(-) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index 0ffb8b4066..6e57d2171a 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -51,101 +51,6 @@ void test_set_chipset_to_g3(void); */ #define zassume_unreachable(msg, ...) zassert_unreachable(msg, ##__VA_ARGS__) -/** - * @brief Assume that @a cond is true - * @param cond Condition to check - * @param msg Optional message to print if the assumption fails - */ -#define zassume_true(cond, msg, ...) zassert_true(cond, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a cond is false - * @param cond Condition to check - * @param msg Optional message to print if the assumption fails - */ -#define zassume_false(cond, msg, ...) zassert_false(cond, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a cond is 0 (success) - * @param cond Condition to check - * @param msg Optional message to print if the assumption fails - */ -#define zassume_ok(cond, msg, ...) zassert_ok(cond, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a ptr is NULL - * @param ptr Pointer to compare - * @param msg Optional message to print if the assumption fails - */ -#define zassume_is_null(ptr, msg, ...) zassert_is_null(ptr, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a ptr is not NULL - * @param ptr Pointer to compare - * @param msg Optional message to print if the assumption fails - */ -#define zassume_not_null(ptr, msg, ...) \ - zassert_not_null(ptr, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a a equals @a b - * - * @a a and @a b won't be converted and will be compared directly. - * - * @param a Value to compare - * @param b Value to compare - * @param msg Optional message to print if the assumption fails - */ -#define zassume_equal(a, b, msg, ...) zassert_equal(a, b, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a a does not equal @a b - * - * @a a and @a b won't be converted and will be compared directly. - * - * @param a Value to compare - * @param b Value to compare - * @param msg Optional message to print if the assumption fails - */ -#define zassume_not_equal(a, b, msg, ...) \ - zassert_not_equal(a, b, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a a equals @a b - * - * @a a and @a b will be converted to `void *` before comparing. - * - * @param a Value to compare - * @param b Value to compare - * @param msg Optional message to print if the assumption fails - */ -#define zassume_equal_ptr(a, b, msg, ...) \ - zassert_equal_ptr(a, b, msg, ##__VA_ARGS__) - -/** - * @brief Assume that @a a is within @a b with delta @a d - * - * @param a Value to compare - * @param b Value to compare - * @param d Delta - * @param msg Optional message to print if the assumption fails - */ -#define zassume_within(a, b, d, msg, ...) \ - zassert_within(a, b, d, msg, ##__VA_ARGS__) - -/** - * @brief Assume that 2 memory buffers have the same contents - * - * This macro calls the final memory comparison assumption macro. - * Using double expansion allows providing some arguments by macros that - * would expand to more than one values (ANSI-C99 defines that all the macro - * arguments have to be expanded before macro call). - * - * @param ... Arguments, see @ref zassume_mem_equal__ - * for real arguments accepted. - */ -#define zassume_mem_equal(...) zassert_mem_equal(##__VA_ARGS__) - /** * Run the host command to get the charge state for a given charger number. * -- cgit v1.2.1 From 89c8a8c43cff2e598a049a273bd7ee13f9e2b5d0 Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Wed, 29 Jun 2022 14:13:03 +0800 Subject: Xivu: Implement LED behavior This patch adds led_policy and led_pins dts files for xivu and enables common led_driver code. Implement LED behavior. Power LED: Discharge in S0 : White on Discharge in S3 : Blinking White, 1sec on /3sec off Discharge in S5 : Off Charge LED: Charge : Amber on Full charge : White on Battery Low(0~10%) in S0 : Blinking Amber, 1sec on /3sec off Battery Low(0~10%) in S3 : Blinking White, 1sec on /3sec off Battery Low(0~10%) in S5 : Off Battery Error in S0 : Blinking Amber, 1sec on /1sec off Battery Error in S3 : Blinking White, 1sec on /3sec off Battery Error in S5 : Off BUG=b:237224850 BRANCH=none TEST=zmake build xivu Signed-off-by: johnwc_yeh Change-Id: I1d19810560248eab08187d1bfd86651150b9f478 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733877 Reviewed-by: Elthan Huang Reviewed-by: Peter Marheine --- zephyr/projects/nissa/BUILD.py | 3 +- zephyr/projects/nissa/CMakeLists.txt | 3 - zephyr/projects/nissa/prj_xivu.conf | 4 + zephyr/projects/nissa/src/xivu/led.c | 56 ------ zephyr/projects/nissa/xivu_led_pins.dts | 112 +++++++++++ zephyr/projects/nissa/xivu_led_policy.dts | 300 ++++++++++++++++++++++++++++++ zephyr/projects/nissa/xivu_pwm_leds.dts | 70 ------- 7 files changed, 418 insertions(+), 130 deletions(-) delete mode 100644 zephyr/projects/nissa/src/xivu/led.c create mode 100644 zephyr/projects/nissa/xivu_led_pins.dts create mode 100644 zephyr/projects/nissa/xivu_led_policy.dts delete mode 100644 zephyr/projects/nissa/xivu_pwm_leds.dts diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index 05f99d88fe..cfbeab0dda 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -92,7 +92,8 @@ xivu = register_nissa_project( here / "xivu_motionsense.dts", here / "xivu_keyboard.dts", here / "xivu_power_signals.dts", - here / "xivu_pwm_leds.dts", + here / "xivu_led_pins.dts", + here / "xivu_led_policy.dts", ], extra_kconfig_files=[here / "prj_xivu.conf"], ) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index b2bb2c67d2..4bfc879758 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -53,9 +53,6 @@ if(DEFINED CONFIG_BOARD_PUJJO) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") endif() if(DEFINED CONFIG_BOARD_XIVU) - zephyr_library_sources( - "src/xivu/led.c" - ) project(xivu) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/xivu/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/xivu/charger.c") diff --git a/zephyr/projects/nissa/prj_xivu.conf b/zephyr/projects/nissa/prj_xivu.conf index c64fcd4d4d..4211fc8215 100644 --- a/zephyr/projects/nissa/prj_xivu.conf +++ b/zephyr/projects/nissa/prj_xivu.conf @@ -45,3 +45,7 @@ CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y CONFIG_PLATFORM_EC_BATTERY_SMART=y CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y + +# LED +CONFIG_PLATFORM_EC_LED_COMMON=n +CONFIG_PLATFORM_EC_LED_DT=y diff --git a/zephyr/projects/nissa/src/xivu/led.c b/zephyr/projects/nissa/src/xivu/led.c deleted file mode 100644 index fbe5c88218..0000000000 --- a/zephyr/projects/nissa/src/xivu/led.c +++ /dev/null @@ -1,56 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - * - * Battery LED control for nissa - */ -#include "common.h" -#include "ec_commands.h" -#include "led_common.h" -#include "led_onoff_states.h" -#include "led_pwm.h" - -__override const int led_charge_lvl_1 = 5; -__override const int led_charge_lvl_2 = 97; -__override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_BLUE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 1 * LED_ONE_SEC } }, - [STATE_FACTORY_TEST] = { { EC_LED_COLOR_AMBER, - 2 * LED_ONE_SEC }, - { EC_LED_COLOR_BLUE, - 2 * LED_ONE_SEC } }, - }; - -__override void led_set_color_battery(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_RED: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_RED); - break; - case EC_LED_COLOR_BLUE: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_BLUE); - break; - case EC_LED_COLOR_AMBER: - set_pwm_led_color(EC_LED_ID_BATTERY_LED, EC_LED_COLOR_AMBER); - break; - default: /* LED_OFF and other unsupported colors */ - set_pwm_led_color(EC_LED_ID_BATTERY_LED, -1); - break; - } -} diff --git a/zephyr/projects/nissa/xivu_led_pins.dts b/zephyr/projects/nissa/xivu_led_pins.dts new file mode 100644 index 0000000000..67c11f0019 --- /dev/null +++ b/zephyr/projects/nissa/xivu_led_pins.dts @@ -0,0 +1,112 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwm_pins { + compatible = "cros-ec,pwm-pin-config"; + pwm_led_y_c0: pwm_led_y_c0 { + #led-pin-cells = <1>; + pwms = <&pwm2 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c0: pwm_led_w_c0 { + #led-pin-cells = <1>; + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_y_c1: pwm_led_y_c1 { + #led-pin-cells = <1>; + pwms = <&pwm6 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + + pwm_led_w_c1: pwm_led_w_c1 { + #led-pin-cells = <1>; + pwms = <&pwm1 0 PWM_HZ(324) PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + pwm-frequency = <324>; + + color_off_left: color-off-left { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_LEFT_LED"; + led-pins = <&pwm_led_y_c1 0>, + <&pwm_led_w_c1 0>; + }; + + color_off_right: color-off-right { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_RIGHT_LED"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_w_c0 0>; + }; + + color_amber_left: color-amber-left { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_led_y_c1 1>, + <&pwm_led_w_c1 0>; + }; + + color_amber_right: color-amber-right { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_AMBER"; + led-pins = <&pwm_led_y_c0 1>, + <&pwm_led_w_c0 0>; + }; + + color_white_left: color-white-left { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_LEFT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_led_y_c1 0>, + <&pwm_led_w_c1 1>; + }; + + color_white_right: color-white-right { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_RIGHT_LED"; + br-color = "EC_LED_COLOR_WHITE"; + led-pins = <&pwm_led_y_c0 0>, + <&pwm_led_w_c0 1>; + }; + }; +}; + +/* LED2 */ +&pwm0 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm0_gpc3>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm1 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm1_gpc2>; + pinctrl-names = "default"; +}; + +/* LED1 */ +&pwm2 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm2_gpc4>; + pinctrl-names = "default"; +}; + +/* LED0 */ +&pwm6 { + status = "okay"; + clock-bus = "NPCX_CLOCK_BUS_LFCLK"; + pinctrl-0 = <&pwm6_gpc0>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/xivu_led_policy.dts b/zephyr/projects/nissa/xivu_led_policy.dts new file mode 100644 index 0000000000..a86cb27407 --- /dev/null +++ b/zephyr/projects/nissa/xivu_led_policy.dts @@ -0,0 +1,300 @@ +#include + +/ { + led-colors { + compatible = "cros-ec,led-colors"; + + power-state-charge-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to Amber */ + color-1 { + led-color = <&color_amber_left>; + }; + }; + + power-state-charge-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to Amber */ + color-1 { + led-color = <&color_amber_right>; + }; + }; + + power-state-near-full-left { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <1>; /* Left port */ + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED to White */ + color-1 { + led-color = <&color_white_left>; + }; + }; + + power-state-near-full-right { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + charge-port = <0>; /* Right port */ + + /* Turn off the left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + /* Left LED to White */ + color-0 { + led-color = <&color_white_left>; + }; + /* Right LED to White */ + color-1 { + led-color = <&color_white_right>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec, off 3 sec */ + color-0 { + led-color = <&color_white_left>; + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off_left>; + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-charge-s0-batt-low-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED - Amber 1 sec, off 3 sec */ + color-1 { + led-color = <&color_amber_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-charge-s0-batt-low-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S0"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED - Amber 1 sec, off 3 sec */ + color-1 { + led-color = <&color_amber_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-charge-s3-batt-low-left { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-charge-s3-batt-low-right { + charge-state = "PWR_STATE_CHARGE"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S3"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-charge-s5-batt-low { + charge-state = "PWR_STATE_CHARGE"; + chipset-state = "POWER_S5"; + /* Battery percent range (>= Empty, <= Low) */ + batt-lvl = ; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + + power-state-error-s0-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S0"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -Amber 1 sec, off 1 sec */ + color-1 { + led-color = <&color_amber_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <1000>; + }; + }; + + power-state-error-s0-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S0"; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -Amber 1 sec, off 1 sec */ + color-1 { + led-color = <&color_amber_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <1000>; + }; + }; + + power-state-error-s3-left { + charge-state = "PWR_STATE_ERROR"; + charge-port = <1>; /* Left port */ + chipset-state = "POWER_S3"; + + /* Turn off the right LED */ + color-0 { + led-color = <&color_off_right>; + }; + /* Left LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_left>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_left>; + period-ms = <3000>; + }; + }; + + power-state-error-s3-right { + charge-state = "PWR_STATE_ERROR"; + charge-port = <0>; /* Right port */ + chipset-state = "POWER_S3"; + + /* Turn off the Left LED */ + color-0 { + led-color = <&color_off_left>; + }; + /* Right LED -White 1 sec, off 3 sec */ + color-1 { + led-color = <&color_white_right>; + period-ms = <1000>; + }; + color-2 { + led-color = <&color_off_right>; + period-ms = <3000>; + }; + }; + + power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off_left>; + }; + color-1 { + led-color = <&color_off_right>; + }; + }; + }; +}; diff --git a/zephyr/projects/nissa/xivu_pwm_leds.dts b/zephyr/projects/nissa/xivu_pwm_leds.dts deleted file mode 100644 index 59325ecf09..0000000000 --- a/zephyr/projects/nissa/xivu_pwm_leds.dts +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm2 2 0 PWM_POLARITY_INVERTED>, - <&pwm0 0 0 PWM_POLARITY_INVERTED>, - <&pwm1 1 0 PWM_POLARITY_INVERTED>, - <&pwm6 6 0 PWM_POLARITY_INVERTED>; - }; - }; - - cros-pwmleds { - compatible = "cros-ec,pwm-leds"; - - leds = <&pwm_led0>; - frequency = <324>; - - /**/ - color-map-red = <100 0 0>; - color-map-green = < 0 100 0>; - color-map-blue = < 0 0 100>; - color-map-yellow = < 0 50 50>; - color-map-white = <100 100 100>; - color-map-amber = <100 5 0>; - - brightness-range = <100 100 100 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - pwm_led_0@0 { - reg = <0>; - ec-led-name = "EC_LED_ID_BATTERY_LED"; - }; - }; -}; - -/* Enable LEDs to work while CPU suspended */ - -&pwm0 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm0_gpc3>; - pinctrl-names = "default"; -}; - -&pwm1 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm1_gpc2>; - pinctrl-names = "default"; -}; - -&pwm2 { - status = "okay"; - clock-bus = "NPCX_CLOCK_BUS_LFCLK"; - pinctrl-0 = <&pwm2_gpc4>; - pinctrl-names = "default"; -}; - -&pwm6 { - status = "okay"; - pinctrl-0 = <&pwm6_gpc0>; - pinctrl-names = "default"; -}; -- cgit v1.2.1 From e475ed0b4e4e806cc301d19ea5ded2f510058608 Mon Sep 17 00:00:00 2001 From: Sam McNally Date: Wed, 6 Jul 2022 11:38:31 +1000 Subject: nissa: Ensure all motionsense sensor DTS entries are correctly ordered. b/238139272 tracks fixing the underlying issue, so update the TODOs to reference it. BUG=b:238139272 TEST=None BRANCH=None Signed-off-by: Sam McNally Change-Id: If72b1c121a4a45f7d5e5b6f735903438beaec1c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747456 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/craask_motionsense.dts | 53 ++++++++++++++------------- zephyr/projects/nissa/joxer_motionsense.dts | 2 +- zephyr/projects/nissa/nereid_motionsense.dts | 2 +- zephyr/projects/nissa/nivviks_motionsense.dts | 2 +- zephyr/projects/nissa/pujjo_motionsense.dts | 2 +- zephyr/projects/nissa/xivu_motionsense.dts | 53 ++++++++++++++------------- 6 files changed, 60 insertions(+), 54 deletions(-) diff --git a/zephyr/projects/nissa/craask_motionsense.dts b/zephyr/projects/nissa/craask_motionsense.dts index 8870f2e94f..e9daeb7fe9 100644 --- a/zephyr/projects/nissa/craask_motionsense.dts +++ b/zephyr/projects/nissa/craask_motionsense.dts @@ -74,19 +74,24 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. */ motionsense-sensor { - base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Base Accel"; + label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -101,32 +106,17 @@ }; }; - base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Gyro"; + label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; drv-data = <&lsm6dso_data>; - }; - - lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; - status = "okay"; - - label = "Lid Accel"; - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -140,6 +130,19 @@ }; }; }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + }; }; motionsense-sensor-info { diff --git a/zephyr/projects/nissa/joxer_motionsense.dts b/zephyr/projects/nissa/joxer_motionsense.dts index 596b3eb148..a5a1756c89 100644 --- a/zephyr/projects/nissa/joxer_motionsense.dts +++ b/zephyr/projects/nissa/joxer_motionsense.dts @@ -73,7 +73,7 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. - * TODO:(b/229577857) The first entries of the array must be + * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS * processing which makes the devicetree entries independent. */ diff --git a/zephyr/projects/nissa/nereid_motionsense.dts b/zephyr/projects/nissa/nereid_motionsense.dts index 596b3eb148..a5a1756c89 100644 --- a/zephyr/projects/nissa/nereid_motionsense.dts +++ b/zephyr/projects/nissa/nereid_motionsense.dts @@ -73,7 +73,7 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. - * TODO:(b/229577857) The first entries of the array must be + * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS * processing which makes the devicetree entries independent. */ diff --git a/zephyr/projects/nissa/nivviks_motionsense.dts b/zephyr/projects/nissa/nivviks_motionsense.dts index f42526db32..a0c242fdf9 100644 --- a/zephyr/projects/nissa/nivviks_motionsense.dts +++ b/zephyr/projects/nissa/nivviks_motionsense.dts @@ -80,7 +80,7 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. - * TODO:(b/229577857) The first entries of the array must be + * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS * processing which makes the devicetree entries independent. */ diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts index 69ebf04c59..c2b6883242 100644 --- a/zephyr/projects/nissa/pujjo_motionsense.dts +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -74,7 +74,7 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. - * TODO:(b/229577857) The first entries of the array must be + * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS * processing which makes the devicetree entries independent. */ diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts index 8870f2e94f..e9daeb7fe9 100644 --- a/zephyr/projects/nissa/xivu_motionsense.dts +++ b/zephyr/projects/nissa/xivu_motionsense.dts @@ -74,19 +74,24 @@ * List of motion sensors that creates motion_sensors array. * The label "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. */ motionsense-sensor { - base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; + lid_accel: lid-accel { + compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Base Accel"; + label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_BASE"; - mutex = <&base_mutex>; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&lis2dw12_data>; + i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -101,32 +106,17 @@ }; }; - base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; + base_accel: base-accel { + compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Gyro"; + label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; drv-data = <&lsm6dso_data>; - }; - - lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; - status = "okay"; - - label = "Lid Accel"; - active-mask = "SENSOR_ACTIVE_S0_S3"; - location = "MOTIONSENSE_LOC_LID"; - mutex = <&lid_mutex>; - port = <&i2c_ec_i2c_sensor>; - rot-standard-ref = <&lid_rot_ref>; - default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -140,6 +130,19 @@ }; }; }; + + base_gyro: base-gyro { + compatible = "cros-ec,lsm6dso-gyro"; + status = "okay"; + + label = "Base Gyro"; + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&lsm6dso_data>; + }; }; motionsense-sensor-info { -- cgit v1.2.1 From a711381bcdbb866c15982b1898101a99760b3bd4 Mon Sep 17 00:00:00 2001 From: Sam McNally Date: Wed, 6 Jul 2022 11:42:11 +1000 Subject: nissa: Configure lsm6dso-gyro default-range to round-up. lsm6dso doesn't support a range of exactly 1000, so a rounded-down range is used by default. This is inadequate for Android requirements. Round-up instead for all nissa motionsense configs using lsm6dso-gyro. BUG=b:238044505 TEST=android.hardware.cts.SensorParameterRangeTest#testGyroscopeRange BRANCH=None Change-Id: Ic3e734bea9979c6ae8a57e1479654ee27277d90f Signed-off-by: Sam McNally Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747457 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/craask_motionsense.dts | 1 + zephyr/projects/nissa/nivviks_motionsense.dts | 1 + zephyr/projects/nissa/pujjo_motionsense.dts | 1 + zephyr/projects/nissa/xivu_motionsense.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/zephyr/projects/nissa/craask_motionsense.dts b/zephyr/projects/nissa/craask_motionsense.dts index e9daeb7fe9..8f217aa945 100644 --- a/zephyr/projects/nissa/craask_motionsense.dts +++ b/zephyr/projects/nissa/craask_motionsense.dts @@ -141,6 +141,7 @@ mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ drv-data = <&lsm6dso_data>; }; }; diff --git a/zephyr/projects/nissa/nivviks_motionsense.dts b/zephyr/projects/nissa/nivviks_motionsense.dts index a0c242fdf9..662ca949ec 100644 --- a/zephyr/projects/nissa/nivviks_motionsense.dts +++ b/zephyr/projects/nissa/nivviks_motionsense.dts @@ -151,6 +151,7 @@ mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ drv-data = <&lsm6dso_data>; }; }; diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts index c2b6883242..baeafe04ee 100644 --- a/zephyr/projects/nissa/pujjo_motionsense.dts +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -145,6 +145,7 @@ mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ drv-data = <&lsm6dso_data>; }; }; diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts index e9daeb7fe9..8f217aa945 100644 --- a/zephyr/projects/nissa/xivu_motionsense.dts +++ b/zephyr/projects/nissa/xivu_motionsense.dts @@ -141,6 +141,7 @@ mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; + default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ drv-data = <&lsm6dso_data>; }; }; -- cgit v1.2.1 From 236441f492ec9adcdcce11f60f5d696b187b0efa Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Tue, 28 Jun 2022 13:36:01 +0800 Subject: kingler: enable anx7447 AUX PU/PD Though kingler has external PU/PD on AUXP and AUXN pins, we still see some glitches on some monitors. The gliches can also be reduced with an extra 100pF caps on AUXP and AUXN, and it can also be fixed by enable AUX PU/PD. BUG=b:235552923 TEST=output to Thinkvision(P24h-2L) BRANCH=none Change-Id: Ice7e02863d382e3c7c34ab0b382bce04e1a20b81 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726602 Auto-Submit: Eric Yilun Lin Tested-by: Eric Yilun Lin Commit-Queue: Ting Shen Reviewed-by: Ting Shen --- zephyr/projects/corsola/prj_npcx993_base.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/projects/corsola/prj_npcx993_base.conf b/zephyr/projects/corsola/prj_npcx993_base.conf index 4d4a6f8bde..7f56f1f346 100644 --- a/zephyr/projects/corsola/prj_npcx993_base.conf +++ b/zephyr/projects/corsola/prj_npcx993_base.conf @@ -72,6 +72,7 @@ CONFIG_PLATFORM_EC_USB_PD_LOGGING=y CONFIG_PLATFORM_EC_USB_PD_DEBUG_FIXED_LEVEL=y CONFIG_PLATFORM_EC_USB_PD_DEBUG_LEVEL=2 CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_ANX7447_AUX_PU_PD=y CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S=y CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y -- cgit v1.2.1 From c8dcbfaa12aa2401d2aac4c4819977bd74fe447b Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 4 Jul 2022 20:38:19 +0800 Subject: dojo: Update base sensor by board version and SSFC value BUG=b:237963220 BRANCH=cherry TEST=make sure that all base sensors work correctly with corresponding board version and ssfc value. Signed-off-by: Tommy Chung Change-Id: I2ba9d3bf3bc4b93ebefae466b8f1027d4bfb6aa7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739114 Reviewed-by: Devin Lu Reviewed-by: Ting Shen Reviewed-by: Chen-Tsung Hsieh --- board/dojo/board.c | 153 +++++++++++++++++++++++++++++++++++++---------------- board/dojo/board.h | 5 ++ 2 files changed, 112 insertions(+), 46 deletions(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index 690f9aa547..0b124d80ab 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -5,6 +5,7 @@ /* Dojo board configuration */ #include "cbi_fw_config.h" +#include "cbi_ssfc.h" #include "charge_manager.h" #include "charge_state_v2.h" #include "common.h" @@ -13,6 +14,7 @@ #include "driver/accel_kionix.h" #include "driver/accel_kx022.h" #include "driver/accelgyro_icm426xx.h" +#include "driver/accelgyro_icm42607.h" #include "driver/accelgyro_icm_common.h" #include "driver/accelgyro_bmi_common_public.h" #include "driver/accelgyro_bmi260_public.h" @@ -31,6 +33,7 @@ #define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) uint32_t board_version; +enum ec_ssfc_base_sensor base_sensor; /* Keyboard scan setting */ __override struct keyboard_scan_config keyscan_config = { @@ -110,21 +113,26 @@ static struct mutex g_base_mutex; static struct mutex g_lid_mutex; static struct icm_drv_data_t g_icm426xx_data; +static struct icm_drv_data_t g_icm42607_data; static struct bmi_drv_data_t g_bmi260_data; static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ -static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(-1), 0 }, - { 0, 0, FLOAT_TO_FP(1) } }; +static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, { 0, FLOAT_TO_FP(-1), 0 }, { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t bmi260_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, - { FLOAT_TO_FP(1), 0, 0 }, - { 0, 0, FLOAT_TO_FP(1) } }; +static const mat33_fp_t icm42607_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; + +static const mat33_fp_t icm426xx_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -135,44 +143,46 @@ struct motion_sensor_t motion_sensors[] = { [BASE_ACCEL] = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, + .chip = MOTIONSENSE_CHIP_BMI260, .type = MOTIONSENSE_TYPE_ACCEL, .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, + .drv = &bmi260_drv, .mutex = &g_base_mutex, - .drv_data = &g_icm426xx_data, + .drv_data = &g_bmi260_data, .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, - .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */ + .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, .rot_standard_ref = &base_standard_ref, - .min_frequency = ICM426XX_ACCEL_MIN_FREQ, - .max_frequency = ICM426XX_ACCEL_MAX_FREQ, + .min_frequency = BMI_ACCEL_MIN_FREQ, + .max_frequency = BMI_ACCEL_MAX_FREQ, + .default_range = 4, /* g */ .config = { /* EC use accel for angle detection */ [SENSOR_CONFIG_EC_S0] = { .odr = 10000 | ROUND_UP_FLAG, .ec_rate = 100 * MSEC, }, + /* Sensor on in S3 */ [SENSOR_CONFIG_EC_S3] = { .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100 * MSEC, }, }, }, [BASE_GYRO] = { .name = "Base Gyro", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_ICM426XX, + .chip = MOTIONSENSE_CHIP_BMI260, .type = MOTIONSENSE_TYPE_GYRO, .location = MOTIONSENSE_LOC_BASE, - .drv = &icm426xx_drv, + .drv = &bmi260_drv, .mutex = &g_base_mutex, - .drv_data = &g_icm426xx_data, + .drv_data = &g_bmi260_data, .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, .default_range = 1000, /* dps */ .rot_standard_ref = &base_standard_ref, - .min_frequency = ICM426XX_GYRO_MIN_FREQ, - .max_frequency = ICM426XX_GYRO_MAX_FREQ, + .min_frequency = BMI_GYRO_MIN_FREQ, + .max_frequency = BMI_GYRO_MAX_FREQ, }, [LID_ACCEL] = { .name = "Lid Accel", @@ -204,69 +214,117 @@ struct motion_sensor_t motion_sensors[] = { }; const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); -struct motion_sensor_t bmi260_base_accel = { +struct motion_sensor_t icm42607_base_accel = { .name = "Base Accel", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI260, + .chip = MOTIONSENSE_CHIP_ICM42607, .type = MOTIONSENSE_TYPE_ACCEL, .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi260_drv, + .drv = &icm42607_drv, .mutex = &g_base_mutex, - .drv_data = &g_bmi260_data, + .drv_data = &g_icm42607_data, .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, - .rot_standard_ref = &bmi260_standard_ref, - .min_frequency = BMI_ACCEL_MIN_FREQ, - .max_frequency = BMI_ACCEL_MAX_FREQ, - .default_range = 4, /* g */ + .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, + .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs.*/ + .rot_standard_ref = &icm42607_standard_ref, + .min_frequency = ICM42607_ACCEL_MIN_FREQ, + .max_frequency = ICM42607_ACCEL_MAX_FREQ, .config = { /* EC use accel for angle detection */ [SENSOR_CONFIG_EC_S0] = { .odr = 10000 | ROUND_UP_FLAG, - .ec_rate = 100 * MSEC, }, - /* Sensor on in S3 */ + /* EC use accel for angle detection */ [SENSOR_CONFIG_EC_S3] = { .odr = 10000 | ROUND_UP_FLAG, + }, + }, +}; + +struct motion_sensor_t icm42607_base_gyro = { + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM42607, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm42607_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm42607_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = ICM42607_ADDR0_FLAGS, + .default_range = 1000, /* dps */ + .rot_standard_ref = &icm42607_standard_ref, + .min_frequency = ICM42607_GYRO_MIN_FREQ, + .max_frequency = ICM42607_GYRO_MAX_FREQ, +}; + +struct motion_sensor_t icm426xx_base_accel = { + .name = "Base Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_ICM426XX, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_BASE, + .drv = &icm426xx_drv, + .mutex = &g_base_mutex, + .drv_data = &g_icm426xx_data, + .port = I2C_PORT_ACCEL, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, + .default_range = 4, /* g, to meet CDD 7.3.1/C-1-4 reqs. */ + .rot_standard_ref = &icm426xx_standard_ref, + .min_frequency = ICM426XX_ACCEL_MIN_FREQ, + .max_frequency = ICM426XX_ACCEL_MAX_FREQ, + .config = { + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 10000 | ROUND_UP_FLAG, .ec_rate = 100 * MSEC, }, + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + }, }, }; -struct motion_sensor_t bmi260_base_gyro = { +struct motion_sensor_t icm426xx_base_gyro = { .name = "Base Gyro", .active_mask = SENSOR_ACTIVE_S0_S3, - .chip = MOTIONSENSE_CHIP_BMI260, + .chip = MOTIONSENSE_CHIP_ICM426XX, .type = MOTIONSENSE_TYPE_GYRO, .location = MOTIONSENSE_LOC_BASE, - .drv = &bmi260_drv, + .drv = &icm426xx_drv, .mutex = &g_base_mutex, - .drv_data = &g_bmi260_data, + .drv_data = &g_icm426xx_data, .port = I2C_PORT_ACCEL, - .i2c_spi_addr_flags = BMI260_ADDR0_FLAGS, + .i2c_spi_addr_flags = ICM426XX_ADDR0_FLAGS, .default_range = 1000, /* dps */ - .rot_standard_ref = &bmi260_standard_ref, - .min_frequency = BMI_GYRO_MIN_FREQ, - .max_frequency = BMI_GYRO_MAX_FREQ, + .rot_standard_ref = &icm426xx_standard_ref, + .min_frequency = ICM426XX_GYRO_MIN_FREQ, + .max_frequency = ICM426XX_GYRO_MAX_FREQ, }; static void board_update_motion_sensor_config(void) { - if (board_version >= 2) { - motion_sensors[BASE_ACCEL] = bmi260_base_accel; - motion_sensors[BASE_GYRO] = bmi260_base_gyro; - ccprints("BASE Accelgyro is BMI260"); - } else { + if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX) { + motion_sensors[BASE_ACCEL] = icm426xx_base_accel; + motion_sensors[BASE_GYRO] = icm426xx_base_gyro; ccprints("BASE Accelgyro is ICM426XX"); + } else if (base_sensor == SSFC_SENSOR_ICM42607) { + motion_sensors[BASE_ACCEL] = icm42607_base_accel; + motion_sensors[BASE_GYRO] = icm42607_base_gyro; + ccprints("BASE Accelgyro is ICM42607"); + } else { + ccprints("BASE Accelgyro is BMI260"); } } void motion_interrupt(enum gpio_signal signal) { - if (board_version >= 2) - bmi260_interrupt(signal); - else + if (board_version <= 1 || base_sensor == SSFC_SENSOR_ICM426XX) icm426xx_interrupt(signal); + else if (base_sensor == SSFC_SENSOR_ICM42607) + icm42607_interrupt(signal); + else + bmi260_interrupt(signal); } /* PWM */ @@ -397,6 +455,9 @@ static void board_init(void) /* Store board version for use of something */ cbi_get_board_version(&board_version); + /* Store base sensor to recognize which base sensor we are using */ + base_sensor = get_cbi_ssfc_base_sensor(); + board_update_motion_sensor_config(); board_update_vol_up_key(); } diff --git a/board/dojo/board.h b/board/dojo/board.h index a8f0556f86..ac0c5cdb61 100644 --- a/board/dojo/board.h +++ b/board/dojo/board.h @@ -62,6 +62,11 @@ #define CONFIG_ACCELGYRO_ICM426XX_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) +/* ICM42607 Base accel/gyro*/ +#define CONFIG_ACCELGYRO_ICM42607 +#define CONFIG_ACCELGYRO_ICM42607_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) + /* BMI260 accel/gyro in base */ #define CONFIG_ACCELGYRO_BMI260 #define CONFIG_ACCELGYRO_BMI260_INT_EVENT \ -- cgit v1.2.1 From fe6253bb8b38d9324d57307e75c759ce2710953a Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 4 Jul 2022 17:10:55 +0800 Subject: power/mt8192: Apply chipset resume init and suspend complete hooks BUG=b:236790585 BRANCH=cherry TEST=make buildall -j Signed-off-by: Tommy Chung Change-Id: Icfadb0368a85d4829cf6b12510ecf8ffb7f4632b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742850 Reviewed-by: Ting Shen Commit-Queue: Ting Shen --- power/mt8192.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/power/mt8192.c b/power/mt8192.c index c977d6f617..fcf1b197fe 100644 --- a/power/mt8192.c +++ b/power/mt8192.c @@ -394,6 +394,11 @@ enum power_state power_handle_state(enum power_state state) return POWER_S3; case POWER_S3S0: +#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK + /* Call hooks prior to chipset resume */ + hook_notify(HOOK_CHIPSET_RESUME_INIT); +#endif + if (power_wait_signals(IN_PGOOD_S0)) { chipset_force_shutdown(CHIPSET_SHUTDOWN_WAIT); return POWER_S0S3; @@ -418,6 +423,10 @@ enum power_state power_handle_state(enum power_state state) case POWER_S0S3: /* Call hooks before we remove power rails */ hook_notify(HOOK_CHIPSET_SUSPEND); +#ifdef CONFIG_CHIPSET_RESUME_INIT_HOOK + /* Call hooks after chipset suspend */ + hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE); +#endif #ifdef CONFIG_POWER_SLEEP_FAILURE_DETECTION sleep_suspend_transition(); -- cgit v1.2.1 From 5afbafe092fcb820707bea39a47030061e0e035b Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Mon, 4 Jul 2022 17:17:04 +0800 Subject: dojo: Apply HOOK_CHIPSET_RESUME_INIT on enable_nvme BUG=b:236790585 BRANCH=cherry TEST=make sure that nvme power on timing will not cause PCIe driver timeout when chipset resume. Signed-off-by: Tommy Chung Change-Id: I8e6e0960f0bcdc60b9280392e2bc0da54ec8c2c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742851 Commit-Queue: Ting Shen Reviewed-by: Ting Shen --- board/dojo/board.c | 2 +- board/dojo/board.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index 0b124d80ab..fcb2db6d9b 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -467,7 +467,7 @@ static void enable_nvme(void) { gpio_set_level(GPIO_EN_PP3300_SSD, 1); } -DECLARE_HOOK(HOOK_CHIPSET_RESUME, enable_nvme, HOOK_PRIO_FIRST); +DECLARE_HOOK(HOOK_CHIPSET_RESUME_INIT, enable_nvme, HOOK_PRIO_FIRST); static void disable_nvme(void) { diff --git a/board/dojo/board.h b/board/dojo/board.h index ac0c5cdb61..7c09649759 100644 --- a/board/dojo/board.h +++ b/board/dojo/board.h @@ -37,6 +37,9 @@ /* Charger */ #define CONFIG_CHARGER_PROFILE_OVERRIDE +/* Chipset */ +#define CONFIG_CHIPSET_RESUME_INIT_HOOK + /* PD / USB-C / PPC */ #undef CONFIG_USB_PD_DEBUG_LEVEL /* default to 1, configurable in ec console \ */ -- cgit v1.2.1 From e205e2fe5e7eb5c10afba2b35704a66db86a8cc4 Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Wed, 6 Jul 2022 14:58:17 +0800 Subject: charge_manager: return max available power in PD_POWER_INFO command When DPS enabled, it could select a low but more efficient PDO for charging. If the selected power is less than usb-min-ac-watts, a "low-power charger connected" popup appears and causes user confution. In this case, we should return the maximum available power instead the current selected power. BUG=b:237988097 TEST=When DPS picks a PDO less than usb-min-ac-watts, verify: 1) no "low-power charger" warning popup 2) `ectool usbpdpower` prints the maximum possible PDO power BRANCH=tomato Signed-off-by: Ting Shen Change-Id: Iaec76c9c81ee930222841b047efefb12162086c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747172 Reviewed-by: Eric Yilun Lin Tested-by: Ting Shen Commit-Queue: Ting Shen --- common/charge_manager.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index d74410ebe8..8895be9cf2 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -475,6 +475,8 @@ static void charge_manager_fill_power_info(int port, } } else { int use_ramp_current; + uint32_t max_mv, max_ma, pdo, unused; + switch (sup) { case CHARGE_SUPPLIER_PD: r->type = USB_CHG_TYPE_PD; @@ -523,7 +525,24 @@ static void charge_manager_fill_power_info(int port, r->type = USB_CHG_TYPE_OTHER; #endif } - r->meas.voltage_max = available_charge[sup][port].voltage; + + if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled() && + sup == CHARGE_SUPPLIER_PD) { + /* + * Returns the maximum power the system can request when + * DPS enabled. This is to prevent the system think it's + * using a low power charger. + */ + pd_find_pdo_index(pd_get_src_cap_cnt(port), + pd_get_src_caps(port), + pd_get_max_voltage(), &pdo); + pd_extract_pdo_power(pdo, &max_ma, &max_mv, &unused); + } else { + max_mv = available_charge[sup][port].voltage; + max_ma = available_charge[sup][port].current; + } + + r->meas.voltage_max = max_mv; /* * Report unknown charger CHARGE_DETECT_DELAY after supplier @@ -564,15 +583,12 @@ static void charge_manager_fill_power_info(int port, */ r->meas.current_max = chg_ramp_is_stable() ? r->meas.current_lim : chg_ramp_max(port, sup, - available_charge[sup][port].current); + max_ma); - r->max_power = - r->meas.current_max * r->meas.voltage_max; } else { - r->meas.current_max = r->meas.current_lim = - available_charge[sup][port].current; - r->max_power = POWER(available_charge[sup][port]); + r->meas.current_max = r->meas.current_lim = max_ma; } + r->max_power = r->meas.current_max * r->meas.voltage_max; r->meas.voltage_now = get_vbus_voltage(port, r->role); } -- cgit v1.2.1 From b5fe12673bab3076e67cc6fc0df16aaf952d83fc Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 5 Jul 2022 12:30:19 +0000 Subject: zephyr: drop stale i2c_map.h This is not referenced anywhere, looks like it's stale, let's drop it. BRANCH=none BUG=none TEST=zmake build kingler TEST=zmake build krabby Signed-off-by: Fabio Baltieri Change-Id: I1a765b8df818ab4026fe19cd9278fb79a80b8a48 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3746256 Reviewed-by: Andrew McRae --- zephyr/projects/corsola/include/i2c_map.h | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100644 zephyr/projects/corsola/include/i2c_map.h diff --git a/zephyr/projects/corsola/include/i2c_map.h b/zephyr/projects/corsola/include/i2c_map.h deleted file mode 100644 index e2f6c53ed2..0000000000 --- a/zephyr/projects/corsola/include/i2c_map.h +++ /dev/null @@ -1,13 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_I2C_MAP_H -#define __ZEPHYR_I2C_MAP_H - -#include - -#include "i2c/i2c.h" - -#endif /* __ZEPHYR_I2C_MAP_H */ -- cgit v1.2.1 From 54de8d24958a253298eaa4551f2c2474a94d1650 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 6 Jul 2022 16:06:25 +0800 Subject: rt1718s: ignore cached source flag for enable sourcing When FRS happens (failed or succeed), the cached source flag may not reflect the correct status immediately. So, ignore the source flag to update the VBUS charge supplier and enable source control. BUG=b:234352018 TEST=unplug FRS hub with adapter connected, and the VBUS supplier disappeared. BRANCH=cherry Change-Id: Ia735efb3ea15733be01990613ab256d8e73a7f4a Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747170 Auto-Submit: Eric Yilun Lin Commit-Queue: Ting Shen Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen --- driver/ppc/rt1718s.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/driver/ppc/rt1718s.c b/driver/ppc/rt1718s.c index 3bcb161e25..1864bd3c47 100644 --- a/driver/ppc/rt1718s.c +++ b/driver/ppc/rt1718s.c @@ -65,18 +65,10 @@ static int rt1718s_is_sourcing_vbus(int port) static int rt1718s_vbus_source_enable(int port, int enable) { - atomic_t prev_flag; - if (enable) - prev_flag = - atomic_or(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED); + atomic_or(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED); else - prev_flag = atomic_clear_bits(&flags[port], - RT1718S_FLAGS_SOURCE_ENABLED); - - /* Return if status doesn't change */ - if (!!(prev_flag & RT1718S_FLAGS_SOURCE_ENABLED) == !!enable) - return EC_SUCCESS; + atomic_clear_bits(&flags[port], RT1718S_FLAGS_SOURCE_ENABLED); RETURN_ERROR(tcpm_set_src_ctrl(port, enable)); -- cgit v1.2.1 From c5fa16ae5fadac9aa5b3bb5e36e304ab9335317b Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 6 Jul 2022 16:10:25 +0800 Subject: cherry: do not use the cached VBUS value Ignore the cached value in case of the FRS happening and let the cached VBUS status outdated. BUG=b:234352018 TEST=unplug FRS hub with adapter connected, and the VBUS supplier disappeared. BRANCH=cherry Change-Id: Ie87734976fc24eb1618e166d9eca0462f97d6ab8 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747171 Auto-Submit: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Ting Shen Tested-by: Eric Yilun Lin --- baseboard/cherry/usb_pd_policy.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/baseboard/cherry/usb_pd_policy.c b/baseboard/cherry/usb_pd_policy.c index 6aa3eb0909..a6badfb160 100644 --- a/baseboard/cherry/usb_pd_policy.c +++ b/baseboard/cherry/usb_pd_policy.c @@ -203,16 +203,11 @@ int pd_snk_is_vbus_provided(int port) void pd_power_supply_reset(int port) { - int prev_en; - - prev_en = ppc_is_sourcing_vbus(port); - /* Disable VBUS. */ ppc_vbus_source_enable(port, 0); /* Enable discharge if we were previously sourcing 5V */ - if (prev_en) - pd_set_vbus_discharge(port, 1); + pd_set_vbus_discharge(port, 1); if (port == 1) rt1718s_gpio_set_level(port, GPIO_EN_USB_C1_5V_OUT, 0); -- cgit v1.2.1 From b6058211c0259083cb1bdeb731d580e8ae760996 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Mon, 4 Jul 2022 16:05:26 +0800 Subject: Nereid: don't check IRQ line if port doesn't exist The check causes that the check_c1_line() to be registered every 5ms. But the operation isn't required on one port SKU. BRANCH=none BUG=b:236668079, b:237717730 TEST=Saved ~5mW on one port SKU. Signed-off-by: Dino Li Change-Id: I27bd6311a5327221ba87a0043e64a05a4df28a1e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742849 Reviewed-by: Peter Marheine --- zephyr/projects/nissa/src/nereid/usbc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/src/nereid/usbc.c b/zephyr/projects/nissa/src/nereid/usbc.c index 9e12f05188..b352d578f2 100644 --- a/zephyr/projects/nissa/src/nereid/usbc.c +++ b/zephyr/projects/nissa/src/nereid/usbc.c @@ -364,7 +364,8 @@ void usb_c1_interrupt(enum gpio_signal s) void board_handle_initial_typec_irq(void) { check_c0_line(); - check_c1_line(); + if (board_get_usb_pd_port_count() == 2) + check_c1_line(); } /* * This must run after sub-board detection (which happens in EC main()), -- cgit v1.2.1 From 2b020b9b1a7578bf382163801aa0f65eb4edb343 Mon Sep 17 00:00:00 2001 From: YH Lin Date: Wed, 22 Jun 2022 00:22:37 +0000 Subject: ec: add cbi data tag/field for factory_calibration_data Add a CBI factory_calibration_data tag to carry 32 bit data in the CBI as well as the accessor for this data. BUG=b:236048046 TEST=None BRANCH=None Signed-off-by: YH Lin Change-Id: Iab31422b8a6d2e25e238aa0c6c72a297b6663e09 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716800 Reviewed-by: Jack Rosenthal --- common/cbi.c | 8 ++++++++ include/cros_board_info.h | 1 + include/ec_commands.h | 1 + test/cbi.c | 5 +++++ util/cbi-util.c | 15 ++++++++++++++- util/ectool.c | 1 + 6 files changed, 30 insertions(+), 1 deletion(-) diff --git a/common/cbi.c b/common/cbi.c index 678f429530..f878e4492e 100644 --- a/common/cbi.c +++ b/common/cbi.c @@ -311,6 +311,14 @@ int cbi_get_rework_id(uint64_t *id) return cbi_get_board_info(CBI_TAG_REWORK_ID, (uint8_t *)id, &size); } +int cbi_get_factory_calibration_data(uint32_t *calibration_data) +{ + uint8_t size = sizeof(*calibration_data); + + return cbi_get_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA, + (uint8_t *)calibration_data, &size); +} + static enum ec_status hc_cbi_get(struct host_cmd_handler_args *args) { const struct __ec_align4 ec_params_get_cbi *p = args->params; diff --git a/include/cros_board_info.h b/include/cros_board_info.h index aed845393f..a1f4485619 100644 --- a/include/cros_board_info.h +++ b/include/cros_board_info.h @@ -99,6 +99,7 @@ int cbi_get_fw_config(uint32_t *fw_config); int cbi_get_pcb_supplier(uint32_t *pcb_supplier); int cbi_get_ssfc(uint32_t *ssfc); int cbi_get_rework_id(uint64_t *id); +int cbi_get_factory_calibration_data(uint32_t *calibration_data); /** * Get data from CBI store diff --git a/include/ec_commands.h b/include/ec_commands.h index 0c28b11dba..759cdca27b 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -6034,6 +6034,7 @@ enum cbi_data_tag { /* Second Source Factory Cache */ CBI_TAG_SSFC = 8, /* uint32_t bit field */ CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */ + CBI_TAG_FACTORY_CALIBRATION_DATA = 10, /* uint32_t bit field */ CBI_TAG_COUNT, }; diff --git a/test/cbi.c b/test/cbi.c index 58c29c4276..a5a38dcb10 100644 --- a/test/cbi.c +++ b/test/cbi.c @@ -185,6 +185,9 @@ DECLARE_EC_TEST(test_all_tags) zassert_equal(cbi_set_board_info(CBI_TAG_REWORK_ID, &d8, sizeof(d8)), EC_SUCCESS, NULL); count++; + zassert_equal(cbi_set_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA, &d8, + sizeof(d8)), EC_SUCCESS, NULL); + count++; /* Read out all */ zassert_equal(cbi_get_board_version(&d32), EC_SUCCESS, NULL); @@ -219,6 +222,8 @@ DECLARE_EC_TEST(test_all_tags) zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8); zassert_equal(cbi_get_ssfc(&d32), EC_SUCCESS, NULL); zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8); + zassert_equal(cbi_get_factory_calibration_data(&d32), EC_SUCCESS, NULL); + zassert_equal(d32, d8, "0x%x, 0x%x", d32, d8); zassert_equal(cbi_get_rework_id(&d64), EC_SUCCESS, NULL); /* This should be zassert_equal, but for EC test fmt is always "0x%x" * which will generate compilation error. diff --git a/util/cbi-util.c b/util/cbi-util.c index fb38cd86e1..20268e43a4 100644 --- a/util/cbi-util.c +++ b/util/cbi-util.c @@ -41,6 +41,7 @@ enum { OPT_PCB_SUPPLIER, OPT_SSFC, OPT_REWORK_ID, + OPT_FACTORY_CALIBRATION_DATA, OPT_SIZE, OPT_ERASE_BYTE, OPT_SHOW_ALL, @@ -59,6 +60,7 @@ static const struct option opts_create[] = { { "pcb_supplier", 1, 0, OPT_PCB_SUPPLIER }, { "ssfc", 1, 0, OPT_SSFC }, { "rework_id", 1, 0, OPT_REWORK_ID }, + { "factory_calibration_data", 1, 0, OPT_FACTORY_CALIBRATION_DATA}, { "size", 1, 0, OPT_SIZE }, { "erase_byte", 1, 0, OPT_ERASE_BYTE }, { NULL, 0, 0, 0 } @@ -72,7 +74,7 @@ static const char *field_name[] = { /* Same order as enum cbi_data_tag */ "BOARD_VERSION", "OEM_ID", "SKU_ID", "DRAM_PART_NUM", "OEM_NAME", "MODEL_ID", "FW_CONFIG", "PCB_SUPPLIER", - "SSFC", "REWORK_ID", + "SSFC", "REWORK_ID", "FACTORY_CALIBRATION_DATA", }; BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT); @@ -96,6 +98,7 @@ const char help_create[] = " --pcb_supplier PCB supplier\n" " --ssfc Second Source Factory Cache bit-field\n" " --rework_id REWORK_ID\n" + " --factory_calibration_data Factory calibration data\n" "\n" " must be a positive integer <= 0XFFFFFFFF, must be a\n" " positive integer <= 0xFFFFFFFFFFFFFFFF and field size can be\n" @@ -306,6 +309,7 @@ static int cmd_create(int argc, char **argv) struct integer_field pcb_supplier; struct integer_field ssfc; struct long_integer_field rework; + struct integer_field factory_calibration_data; const char *dram_part_num; const char *oem_name; } bi; @@ -390,6 +394,11 @@ static int cmd_create(int argc, char **argv) if (parse_uint64_field(optarg, &bi.rework)) return -1; break; + case OPT_FACTORY_CALIBRATION_DATA: + if (parse_integer_field(optarg, + &bi.factory_calibration_data)) + return -1; + break; } } @@ -422,6 +431,9 @@ static int cmd_create(int argc, char **argv) bi.pcb_supplier.size); p = cbi_set_data(p, CBI_TAG_SSFC, &bi.ssfc.val, bi.ssfc.size); p = cbi_set_data(p, CBI_TAG_REWORK_ID, &bi.rework.val, bi.rework.size); + p = cbi_set_data(p, CBI_TAG_FACTORY_CALIBRATION_DATA, + &bi.factory_calibration_data.val, + bi.factory_calibration_data.size); p = cbi_set_string(p, CBI_TAG_DRAM_PART_NUM, bi.dram_part_num); p = cbi_set_string(p, CBI_TAG_OEM_NAME, bi.oem_name); @@ -556,6 +568,7 @@ static int cmd_show(int argc, char **argv) print_integer(buf, CBI_TAG_PCB_SUPPLIER); print_integer(buf, CBI_TAG_SSFC); print_integer(buf, CBI_TAG_REWORK_ID); + print_integer(buf, CBI_TAG_FACTORY_CALIBRATION_DATA); print_string(buf, CBI_TAG_DRAM_PART_NUM); print_string(buf, CBI_TAG_OEM_NAME); diff --git a/util/ectool.c b/util/ectool.c index 6e4bd1ff35..d80a3404cf 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -8241,6 +8241,7 @@ static void cmd_cbi_help(char *cmd) " 7: PCB_VENDOR\n" " 8: SSFC\n" " 9: REWORK_ID\n" + " 10: FACTORY_CALIBRATION_DATA\n" " is the size of the data in byte. It should be zero for\n" " string types.\n" " is an integer or a string to be set\n" -- cgit v1.2.1 From e7adeb81a7f570c9a89b8309b6622eab73b8ee50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:58:54 -0600 Subject: board/phaser/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I5c0e3b09b8449d45cbff332de3277c17d2afbe77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728821 Reviewed-by: Jeremy Bettis --- board/phaser/board.h | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/board/phaser/board.h b/board/phaser/board.h index a03782b245..fbdc55ff3a 100644 --- a/board/phaser/board.h +++ b/board/phaser/board.h @@ -44,8 +44,8 @@ #define CONFIG_CMD_ACCEL_INFO /* Sensors */ -#define CONFIG_ACCEL_LIS2DE /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_LIS2DE /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -60,8 +60,8 @@ /* Additional PPC second source */ #define CONFIG_USBC_PPC_SYV682X -#define CONFIG_USBC_PPC_DEDICATED_INT -#undef CONFIG_SYV682X_HV_ILIM +#define CONFIG_USBC_PPC_DEDICATED_INT +#undef CONFIG_SYV682X_HV_ILIM #define CONFIG_SYV682X_HV_ILIM SYV682X_HV_ILIM_5_50 /* SYV682 isn't connected to CC, so TCPC must provide VCONN */ #define CONFIG_USBC_PPC_SYV682X_NO_CC @@ -72,10 +72,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT, }; @@ -86,18 +86,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; /* List of possible batteries */ enum battery_type { -- cgit v1.2.1 From 266cdc9f4b81a02243e211d98032c5efe6e724b8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:20 -0600 Subject: board/gimble/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I25475ec995513e2d5678d4f86d96ec03c89f17fa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728418 Reviewed-by: Jeremy Bettis --- board/gimble/thermal.c | 62 ++++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/board/gimble/thermal.c b/board/gimble/thermal.c index 14797c9dfd..b985c9de75 100644 --- a/board/gimble/thermal.c +++ b/board/gimble/thermal.c @@ -15,7 +15,7 @@ #include "util.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -40,45 +40,45 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {43, -1, -1}, - .off = {0, -1, -1}, - .rpm = {0}, - .rpm_tablet = {0}, + .on = { 43, -1, -1 }, + .off = { 0, -1, -1 }, + .rpm = { 0 }, + .rpm_tablet = { 0 }, }, { /* level 1 */ - .on = {45, -1, -1}, - .off = {43, -1, -1}, - .rpm = {3400}, - .rpm_tablet = {3400}, + .on = { 45, -1, -1 }, + .off = { 43, -1, -1 }, + .rpm = { 3400 }, + .rpm_tablet = { 3400 }, }, { /* level 2 */ - .on = {46, -1, -1}, - .off = {44, -1, -1}, - .rpm = {3800}, - .rpm_tablet = {3700}, + .on = { 46, -1, -1 }, + .off = { 44, -1, -1 }, + .rpm = { 3800 }, + .rpm_tablet = { 3700 }, }, { /* level 3 */ - .on = {48, -1, -1}, - .off = {45, -1, -1}, - .rpm = {4200}, - .rpm_tablet = {4100}, + .on = { 48, -1, -1 }, + .off = { 45, -1, -1 }, + .rpm = { 4200 }, + .rpm_tablet = { 4100 }, }, { /* level 4 */ - .on = {50, -1, -1}, - .off = {47, -1, -1}, - .rpm = {4800}, - .rpm_tablet = {4800}, + .on = { 50, -1, -1 }, + .off = { 47, -1, -1 }, + .rpm = { 4800 }, + .rpm_tablet = { 4800 }, }, { /* level 5 */ - .on = {52, -1, -1}, - .off = {49, -1, -1}, - .rpm = {5400}, - .rpm_tablet = {5200}, + .on = { 52, -1, -1 }, + .off = { 49, -1, -1 }, + .rpm = { 5400 }, + .rpm_tablet = { 5200 }, }, }; const int num_fan_levels = ARRAY_SIZE(fan_table); @@ -104,17 +104,14 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor) */ if (temp[temp_sensor] < prev_temp[temp_sensor]) { for (i = current_level; i > 0; i--) { - if (temp[temp_sensor] < - fan_table[i].off[temp_sensor]) + if (temp[temp_sensor] < fan_table[i].off[temp_sensor]) current_level = i - 1; else break; } - } else if (temp[temp_sensor] > - prev_temp[temp_sensor]) { + } else if (temp[temp_sensor] > prev_temp[temp_sensor]) { for (i = current_level; i < num_fan_levels; i++) { - if (temp[temp_sensor] >= - fan_table[i].on[temp_sensor]) + if (temp[temp_sensor] >= fan_table[i].on[temp_sensor]) current_level = i; else break; @@ -149,7 +146,8 @@ void board_override_fan_control(int fan, int *temp) if (chipset_in_state(CHIPSET_STATE_ON)) { fan_set_rpm_mode(FAN_CH(fan), 1); fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_1_DDR_SOC)); + fan_table_to_rpm(FAN_CH(fan), temp, + TEMP_SENSOR_1_DDR_SOC)); } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Stop fan when enter S0ix */ fan_set_rpm_mode(FAN_CH(fan), 1); -- cgit v1.2.1 From d6a4ab5e0c93f785bcef6e55e17032765ce414df Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:54 -0600 Subject: board/agah/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ia1268612cb0cb5e119dc64d61afda3dcb960d8da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727974 Reviewed-by: Jeremy Bettis --- board/agah/sensors.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/board/agah/sensors.c b/board/agah/sensors.c index fccc85998e..56e98f2812 100644 --- a/board/agah/sensors.c +++ b/board/agah/sensors.c @@ -73,8 +73,8 @@ const struct temp_sensor_t temp_sensors[] = { }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -87,8 +87,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -#define THERMAL_GPU \ - { \ +#define THERMAL_GPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(85), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ @@ -99,8 +99,7 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; .temp_fan_off = C_TO_K(35), \ .temp_fan_max = C_TO_K(60), \ } -__maybe_unused static const struct ec_thermal_config thermal_gpu = - THERMAL_GPU; +__maybe_unused static const struct ec_thermal_config thermal_gpu = THERMAL_GPU; /* * Inductor limits - used for both charger and PP3300 regulator @@ -113,8 +112,8 @@ __maybe_unused static const struct ec_thermal_config thermal_gpu = * Inductors: limit of 125c * PCB: limit is 80c */ -#define THERMAL_CHARGER \ - { \ +#define THERMAL_CHARGER \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(105), \ [EC_TEMP_THRESH_HALT] = C_TO_K(120), \ -- cgit v1.2.1 From 0c8de66b7b87c4c76369c776ca64b072cfd542c8 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:41 -0600 Subject: driver/tcpm/anx7447.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I04ee768ed9f4386ab88a097e07d23e7c15a24ced Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730072 Reviewed-by: Jeremy Bettis --- driver/tcpm/anx7447.c | 127 +++++++++++++++++++++++--------------------------- 1 file changed, 59 insertions(+), 68 deletions(-) diff --git a/driver/tcpm/anx7447.c b/driver/tcpm/anx7447.c index ae21b6e263..d872cbba1d 100644 --- a/driver/tcpm/anx7447.c +++ b/driver/tcpm/anx7447.c @@ -16,8 +16,8 @@ #include "usb_pd.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) #define VSAFE5V_MIN 3800 #define VSAFE0V_MAX 800 @@ -53,17 +53,16 @@ static bool anx_frs_dis[CONFIG_USB_PD_PORT_MAX_COUNT]; * ANX7447 SPI address. */ const struct anx7447_i2c_addr anx7447_i2c_addrs_flags[] = { - {AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS}, - {AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS}, - {AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS}, - {AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS} + { AN7447_TCPC0_I2C_ADDR_FLAGS, AN7447_SPI0_I2C_ADDR_FLAGS }, + { AN7447_TCPC1_I2C_ADDR_FLAGS, AN7447_SPI1_I2C_ADDR_FLAGS }, + { AN7447_TCPC2_I2C_ADDR_FLAGS, AN7447_SPI2_I2C_ADDR_FLAGS }, + { AN7447_TCPC3_I2C_ADDR_FLAGS, AN7447_SPI3_I2C_ADDR_FLAGS } }; static inline int anx7447_reg_write(int port, int reg, int val) { int rv = i2c_write8(tcpc_config[port].i2c_info.port, - anx[port].i2c_addr_flags, - reg, val); + anx[port].i2c_addr_flags, reg, val); #ifdef CONFIG_USB_PD_TCPC_LOW_POWER pd_device_accessed(port); #endif @@ -73,8 +72,7 @@ static inline int anx7447_reg_write(int port, int reg, int val) static inline int anx7447_reg_read(int port, int reg, int *val) { int rv = i2c_read8(tcpc_config[port].i2c_info.port, - anx[port].i2c_addr_flags, - reg, val); + anx[port].i2c_addr_flags, reg, val); #ifdef CONFIG_USB_PD_TCPC_LOW_POWER pd_device_accessed(port); #endif @@ -151,7 +149,7 @@ static inline void anx7447_reg_write_or(int port, int reg, int v_or) anx7447_reg_write(port, reg, (val | v_or)); } -#define ANX7447_FLASH_DONE_TIMEOUT_US (100 * MSEC) +#define ANX7447_FLASH_DONE_TIMEOUT_US (100 * MSEC) static int anx7447_wait_for_flash_done(int port) { @@ -270,17 +268,16 @@ static int command_anx_ocm(int argc, char **argv) rv = anx7447_flash_erase_internal( port, 1 /* write to console if empty */); if (rv) - ccprintf("C%d: Failed to erase OCM flash (%d)\n", - port, rv); + ccprintf("C%d: Failed to erase OCM flash (%d)\n", port, + rv); } - ccprintf("C%d: OCM flash is %sempty.\n", - port, anx7447_flash_is_empty(port) ? "" : "not "); + ccprintf("C%d: OCM flash is %sempty.\n", port, + anx7447_flash_is_empty(port) ? "" : "not "); return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm, - "port [erase]", +DECLARE_CONSOLE_COMMAND(anx_ocm, command_anx_ocm, "port [erase]", "Print OCM status or erases OCM for a given port."); #endif @@ -308,21 +305,20 @@ static int anx7447_init(int port) } } if (!I2C_STRIP_FLAGS(anx[port].i2c_addr_flags)) { - ccprintf("TCPC I2C addr 0x%x is invalid for ANX7447\n", - I2C_STRIP_FLAGS(tcpc_config[port] - .i2c_info.addr_flags)); + ccprintf( + "TCPC I2C addr 0x%x is invalid for ANX7447\n", + I2C_STRIP_FLAGS(tcpc_config[port].i2c_info.addr_flags)); return EC_ERROR_UNKNOWN; } - rv = tcpci_tcpm_init(port); if (rv) return rv; #ifdef CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE_COMMAND /* Check and print OCM status to console. */ - CPRINTS("C%d: OCM flash is %sempty", - port, anx7447_flash_is_empty(port) ? "" : "not "); + CPRINTS("C%d: OCM flash is %sempty", port, + anx7447_flash_is_empty(port) ? "" : "not "); #endif /* @@ -344,7 +340,8 @@ static int anx7447_init(int port) return rv; /* Set VBUS_VOLTAGE_ALARM_HI threshold */ - RETURN_ERROR(tcpc_write16(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 0x3FF)); + RETURN_ERROR( + tcpc_write16(port, TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG, 0x3FF)); /* Set VCONN_VOLTAGE_ALARM_HI threshold to 6V */ RETURN_ERROR(tcpc_write16(port, VCONN_VOLTAGE_ALARM_HI_CFG, 0xF0)); @@ -392,8 +389,7 @@ static int anx7447_init(int port) * Note that bypassing the usb_mux API is okay for internal driver calls * since the task calling init already holds this port's mux lock. */ - if (me != NULL && - !(me->flags & USB_MUX_FLAG_NOT_TCPC)) + if (me != NULL && !(me->flags & USB_MUX_FLAG_NOT_TCPC)) rv = anx7447_mux_set(me, USB_PD_MUX_NONE, &unused); #endif /* CONFIG_USB_PD_TCPM_MUX */ @@ -553,8 +549,7 @@ static int anx7447_set_frs_enable(int port, int enable) static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT]; void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required) + mux_state_t mux_state, bool *ack_required) { int reg = 0; int port = me->usb_port; @@ -658,8 +653,8 @@ static void anx7447_mux_safemode(const struct usb_mux *me, int on_off) reg &= ~(ANX7447_REG_SAFE_MODE); mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg); - CPRINTS("C%d set mux to safemode %s, reg = 0x%x", - me->usb_port, (on_off) ? "on" : "off", reg); + CPRINTS("C%d set mux to safemode %s, reg = 0x%x", me->usb_port, + (on_off) ? "on" : "off", reg); } static inline void anx7447_configure_aux_src(const struct usb_mux *me, @@ -676,8 +671,8 @@ static inline void anx7447_configure_aux_src(const struct usb_mux *me, mux_write(me, ANX7447_REG_ANALOG_CTRL_9, reg); - CPRINTS("C%d set aux_src to %s, reg = 0x%x", - me->usb_port, (on_off) ? "on" : "off", reg); + CPRINTS("C%d set aux_src to %s, reg = 0x%x", me->usb_port, + (on_off) ? "on" : "off", reg); } #endif @@ -704,8 +699,8 @@ static int anx7447_mux_set(const struct usb_mux *me, mux_state_t mux_state, cc_direction = mux_state & USB_PD_MUX_POLARITY_INVERTED; mux_type = mux_state & USB_PD_MUX_DOCK; - CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x", - port, mux_state, mux_type); + CPRINTS("C%d mux_state = 0x%x, mux_type = 0x%x", port, mux_state, + mux_type); if (cc_direction == 0) { /* cc1 connection */ if (mux_type == USB_PD_MUX_DOCK) { @@ -829,14 +824,10 @@ static int anx7447_set_cc(int port, int pull) } /* Override for tcpci_tcpm_set_polarity */ -static int anx7447_set_polarity(int port, - enum tcpc_cc_polarity polarity) +static int anx7447_set_polarity(int port, enum tcpc_cc_polarity polarity) { - return tcpc_update8(port, - TCPC_REG_TCPC_CTRL, - TCPC_REG_TCPC_CTRL_SET(1), - polarity_rm_dts(polarity) - ? MASK_SET : MASK_CLR); + return tcpc_update8(port, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_SET(1), + polarity_rm_dts(polarity) ? MASK_SET : MASK_CLR); } #ifdef CONFIG_CMD_TCPC_DUMP @@ -920,15 +911,15 @@ static void anx7447_dump_registers(int port) for (i = 0; i < ARRAY_SIZE(anx7447_alt_regs); i++) { anx7447_reg_read(port, anx7447_alt_regs[i].addr, &val); ccprintf(" %-26s(ALT/0x%02x) = 0x%02x\n", - anx7447_alt_regs[i].name, - anx7447_alt_regs[i].addr, (uint8_t)val); + anx7447_alt_regs[i].name, anx7447_alt_regs[i].addr, + (uint8_t)val); cflush(); } } #endif /* defined(CONFIG_CMD_TCPC_DUMP) */ static int anx7447_get_chip_info(int port, int live, - struct ec_response_pd_chip_info_v1 *chip_info) + struct ec_response_pd_chip_info_v1 *chip_info) { int main_version = 0x0, build_version = 0x0; @@ -983,43 +974,43 @@ enum ec_error_list anx7447_set_bist_test_mode(const int port, const bool enable) * overrides for set_cc and set_polarity. */ const struct tcpm_drv anx7447_tcpm_drv = { - .init = &anx7447_init, - .release = &anx7447_release, - .get_cc = &tcpci_tcpm_get_cc, + .init = &anx7447_init, + .release = &anx7447_release, + .get_cc = &tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC - .check_vbus_level = &tcpci_tcpm_check_vbus_level, + .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif - .get_vbus_voltage = &anx7447_get_vbus_voltage, - .select_rp_value = &tcpci_tcpm_select_rp_value, - .set_cc = &anx7447_set_cc, - .set_polarity = &anx7447_set_polarity, + .get_vbus_voltage = &anx7447_get_vbus_voltage, + .select_rp_value = &tcpci_tcpm_select_rp_value, + .set_cc = &anx7447_set_cc, + .set_polarity = &anx7447_set_polarity, #ifdef CONFIG_USB_PD_DECODE_SOP - .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, + .sop_prime_enable = &tcpci_tcpm_sop_prime_enable, #endif - .set_vconn = &tcpci_tcpm_set_vconn, - .set_msg_header = &tcpci_tcpm_set_msg_header, - .set_rx_enable = &tcpci_tcpm_set_rx_enable, - .get_message_raw = &tcpci_tcpm_get_message_raw, - .transmit = &tcpci_tcpm_transmit, - .tcpc_alert = &anx7447_tcpc_alert, + .set_vconn = &tcpci_tcpm_set_vconn, + .set_msg_header = &tcpci_tcpm_set_msg_header, + .set_rx_enable = &tcpci_tcpm_set_rx_enable, + .get_message_raw = &tcpci_tcpm_get_message_raw, + .transmit = &tcpci_tcpm_transmit, + .tcpc_alert = &anx7447_tcpc_alert, #ifdef CONFIG_USB_PD_DISCHARGE_TCPC - .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, + .tcpc_discharge_vbus = &tcpci_tcpc_discharge_vbus, #endif #ifdef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE - .drp_toggle = anx7447_tcpc_drp_toggle, + .drp_toggle = anx7447_tcpc_drp_toggle, #endif - .get_chip_info = &anx7447_get_chip_info, - .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, - .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, + .get_chip_info = &anx7447_get_chip_info, + .set_snk_ctrl = &tcpci_tcpm_set_snk_ctrl, + .set_src_ctrl = &tcpci_tcpm_set_src_ctrl, #ifdef CONFIG_USB_PD_TCPC_LOW_POWER - .enter_low_power_mode = &tcpci_enter_low_power_mode, + .enter_low_power_mode = &tcpci_enter_low_power_mode, #endif #ifdef CONFIG_USB_PD_FRS_TCPC - .set_frs_enable = &anx7447_set_frs_enable, + .set_frs_enable = &anx7447_set_frs_enable, #endif - .set_bist_test_mode = &anx7447_set_bist_test_mode, + .set_bist_test_mode = &anx7447_set_bist_test_mode, #ifdef CONFIG_CMD_TCPC_DUMP - .dump_registers = &anx7447_dump_registers, + .dump_registers = &anx7447_dump_registers, #endif }; -- cgit v1.2.1 From c706c7847837f6454584b75fb663c65fe59433c7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:59 -0600 Subject: zephyr/subsys/ap_pwrseq/include/x86_power_signals.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic8b7cbb55504159dd24b700504542be81916e032 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730931 Reviewed-by: Jeremy Bettis --- .../subsys/ap_pwrseq/include/x86_power_signals.h | 95 +++++++++------------- 1 file changed, 38 insertions(+), 57 deletions(-) diff --git a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h index 1547dc0fc4..75aecdd191 100644 --- a/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h +++ b/zephyr/subsys/ap_pwrseq/include/x86_power_signals.h @@ -8,10 +8,10 @@ #ifndef __X86_POWER_SIGNALS_H__ #define __X86_POWER_SIGNALS_H__ -#define IN_PCH_SLP_S0 POWER_SIGNAL_MASK(PWR_SLP_S0) -#define IN_PCH_SLP_S3 POWER_SIGNAL_MASK(PWR_SLP_S3) -#define IN_PCH_SLP_S4 POWER_SIGNAL_MASK(PWR_SLP_S4) -#define IN_PCH_SLP_S5 POWER_SIGNAL_MASK(PWR_SLP_S5) +#define IN_PCH_SLP_S0 POWER_SIGNAL_MASK(PWR_SLP_S0) +#define IN_PCH_SLP_S3 POWER_SIGNAL_MASK(PWR_SLP_S3) +#define IN_PCH_SLP_S4 POWER_SIGNAL_MASK(PWR_SLP_S4) +#define IN_PCH_SLP_S5 POWER_SIGNAL_MASK(PWR_SLP_S5) /* * Define the chipset specific power signal masks and values @@ -25,39 +25,29 @@ #define PWRSEQ_G3S5_UP_SIGNAL IN_PCH_SLP_SUS #define PWRSEQ_G3S5_UP_VALUE 0 -#define MASK_ALL_POWER_GOOD \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ - POWER_SIGNAL_MASK(PWR_PG_PP1P05)) - -#define MASK_VW_POWER \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ - POWER_SIGNAL_MASK(PWR_SLP_SUS)) +#define MASK_ALL_POWER_GOOD \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | \ + POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD) | \ + POWER_SIGNAL_MASK(PWR_DSW_PWROK) | POWER_SIGNAL_MASK(PWR_PG_PP1P05)) + +#define MASK_VW_POWER \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ + POWER_SIGNAL_MASK(PWR_SLP_SUS)) #define VALUE_VW_POWER \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK)) - -#define MASK_S0 \ - (MASK_ALL_POWER_GOOD | \ - POWER_SIGNAL_MASK(PWR_SLP_S0) | \ - POWER_SIGNAL_MASK(PWR_SLP_S3) | \ - POWER_SIGNAL_MASK(PWR_SLP_SUS) | \ - POWER_SIGNAL_MASK(PWR_SLP_S4) | \ - POWER_SIGNAL_MASK(PWR_SLP_S5)) -#define VALUE_S0 MASK_ALL_POWER_GOOD - -#define MASK_S3 MASK_S0 -#define VALUE_S3 \ - (MASK_ALL_POWER_GOOD | \ - POWER_SIGNAL_MASK(PWR_SLP_S3)) - -#define MASK_S5 \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ - POWER_SIGNAL_MASK(PWR_SLP_S3) | \ - POWER_SIGNAL_MASK(PWR_SLP_S4) | \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK)) + +#define MASK_S0 \ + (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) | \ + POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_SUS) | \ + POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define VALUE_S0 MASK_ALL_POWER_GOOD + +#define MASK_S3 MASK_S0 +#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3)) + +#define MASK_S5 \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_DSW_PWROK) | \ + POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) #define VALUE_S5 MASK_S5 @@ -68,32 +58,23 @@ #define PWRSEQ_G3S5_UP_VALUE IN_PGOOD_ALL_CORE #define MASK_ALL_POWER_GOOD \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD)) + (POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD)) -#define MASK_VW_POWER \ - POWER_SIGNAL_MASK(PWR_RSMRST) -#define VALUE_VW_POWER \ - POWER_SIGNAL_MASK(PWR_RSMRST) +#define MASK_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST) +#define VALUE_VW_POWER POWER_SIGNAL_MASK(PWR_RSMRST) -#define MASK_S0 \ - (MASK_ALL_POWER_GOOD | \ - POWER_SIGNAL_MASK(PWR_SLP_S0) | \ - POWER_SIGNAL_MASK(PWR_SLP_S3) | \ - POWER_SIGNAL_MASK(PWR_SLP_S4) | \ +#define MASK_S0 \ + (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S0) | \ + POWER_SIGNAL_MASK(PWR_SLP_S3) | POWER_SIGNAL_MASK(PWR_SLP_S4) | \ POWER_SIGNAL_MASK(PWR_SLP_S5)) -#define VALUE_S0 MASK_ALL_POWER_GOOD +#define VALUE_S0 MASK_ALL_POWER_GOOD -#define MASK_S3 MASK_S0 -#define VALUE_S3 \ - (MASK_ALL_POWER_GOOD | \ - POWER_SIGNAL_MASK(PWR_SLP_S3)) +#define MASK_S3 MASK_S0 +#define VALUE_S3 (MASK_ALL_POWER_GOOD | POWER_SIGNAL_MASK(PWR_SLP_S3)) -#define MASK_S5 \ - (POWER_SIGNAL_MASK(PWR_RSMRST) | \ - POWER_SIGNAL_MASK(PWR_SLP_S3) | \ - POWER_SIGNAL_MASK(PWR_SLP_S4) | \ - POWER_SIGNAL_MASK(PWR_SLP_S5)) +#define MASK_S5 \ + (POWER_SIGNAL_MASK(PWR_RSMRST) | POWER_SIGNAL_MASK(PWR_SLP_S3) | \ + POWER_SIGNAL_MASK(PWR_SLP_S4) | POWER_SIGNAL_MASK(PWR_SLP_S5)) #define VALUE_S5 MASK_S5 #else -- cgit v1.2.1 From b4b52c4e17cc6b905209a6ad2935222d5267ad59 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:07 -0600 Subject: board/brya/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I6cd58090d3049ce7fa71ae70789932be1b16d038 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728098 Reviewed-by: Jeremy Bettis --- board/brya/board.h | 147 ++++++++++++++++++++++++----------------------------- 1 file changed, 66 insertions(+), 81 deletions(-) diff --git a/board/brya/board.h b/board/brya/board.h index 88e5dc5915..ae7e61dc68 100644 --- a/board/brya/board.h +++ b/board/brya/board.h @@ -39,7 +39,7 @@ #define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER /* Sensors */ -#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ +#define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ #define CONFIG_ACCEL_LSM6DSO_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) @@ -63,19 +63,18 @@ /* Lid accel */ #define CONFIG_LID_ANGLE #define CONFIG_LID_ANGLE_UPDATE -#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL -#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL #define CONFIG_ACCEL_LIS2DWL #define CONFIG_ACCEL_LIS2DW12_INT_EVENT \ TASK_EVENT_MOTION_SENSOR_INTERRUPT(LID_ACCEL) - /* Sensor console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -83,7 +82,7 @@ #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX -#define CONFIG_IO_EXPANDER_PORT_COUNT 2 +#define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define CONFIG_USB_PD_FRS_PPC @@ -101,17 +100,17 @@ #define CONFIG_USBC_PPC_NX20P3483 /* TODO: b/177608416 - measure and check these values on brya */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -119,67 +118,67 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL -#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL +#define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_MUX NPCX_I2C_PORT3_0 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* * see b/174768555#comment22 */ -#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 -#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57 +#define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 +#define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57 /* Enabling Thunderbolt-compatible mode */ #define CONFIG_USB_PD_TBT_COMPAT_MODE @@ -196,15 +195,15 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_BQ25720 #define CONFIG_CHARGER_BQ25720_VSYS_TH2_CUSTOM -#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 +#define CONFIG_CHARGER_BQ25720_VSYS_TH2_DV 70 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_BQ25710_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_BQ25710_PSYS_SENSING /* @@ -215,7 +214,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -244,37 +243,23 @@ enum sensor_id { SENSOR_COUNT }; -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C2_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT }; -enum battery_type { - BATTERY_POWER_TECH, - BATTERY_LGC011, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_POWER_TECH, BATTERY_LGC011, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_LED2 = 0, /* PWM0 (white charger) */ - PWM_CH_LED3, /* PWM1 (orange on DB) */ - PWM_CH_LED1, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_LED4, /* PWM7 (white on DB) */ + PWM_CH_LED2 = 0, /* PWM0 (white charger) */ + PWM_CH_LED3, /* PWM1 (orange on DB) */ + PWM_CH_LED1, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_LED4, /* PWM7 (white on DB) */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From ae5c2f3f52a80bf9dea16fed19b4e1c298575661 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:14 -0600 Subject: board/lazor/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ia5be3357cc7fa1b9ccff7970e1bd04fa5ba20365 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728618 Reviewed-by: Jeremy Bettis --- board/lazor/board.c | 151 ++++++++++++++++++++-------------------------------- 1 file changed, 58 insertions(+), 93 deletions(-) diff --git a/board/lazor/board.c b/board/lazor/board.c index 8897ff8bd2..f61da16406 100644 --- a/board/lazor/board.c +++ b/board/lazor/board.c @@ -47,10 +47,8 @@ __override struct keyboard_scan_config keyscan_config = { * Unmask 0x08 in [0] (KSO_00/KSI_03, the new location of Search key); * as it still uses the legacy location (KSO_01/KSI_00). */ - .actual_key_mask = { - 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, - 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca - }, + .actual_key_mask = { 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xa4, + 0xff, 0xfe, 0x55, 0xfa, 0xca }, /* Other values should be the same as the default configuration. */ .debounce_down_us = 9 * MSEC, .debounce_up_us = 30 * MSEC, @@ -65,55 +63,44 @@ __override struct keyboard_scan_config keyscan_config = { * that we don't have pin 0. */ const int keyboard_factory_scan_pins[][2] = { - {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, - {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, - {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, - {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, - {2, 5}, {1, 2}, {2, 3}, {2, 2}, {3, 0}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, - {-1, -1}, + { -1, -1 }, { 0, 5 }, { 1, 1 }, { 1, 0 }, { 0, 6 }, { 0, 7 }, + { -1, -1 }, { -1, -1 }, { 1, 4 }, { 1, 3 }, { -1, -1 }, { 1, 6 }, + { 1, 7 }, { 3, 1 }, { 2, 0 }, { 1, 5 }, { 2, 6 }, { 2, 7 }, + { 2, 1 }, { 2, 4 }, { 2, 5 }, { 1, 2 }, { 2, 3 }, { 2, 2 }, + { 3, 0 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, { -1, -1 }, + { -1, -1 }, }; const int keyboard_factory_scan_pins_used = - ARRAY_SIZE(keyboard_factory_scan_pins); + ARRAY_SIZE(keyboard_factory_scan_pins); /* I2C port map */ const struct i2c_port_t i2c_ports[] = { - { - .name = "power", - .port = I2C_PORT_POWER, - .kbps = 100, - .scl = GPIO_EC_I2C_POWER_SCL, - .sda = GPIO_EC_I2C_POWER_SDA - }, - { - .name = "tcpc0", - .port = I2C_PORT_TCPC0, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C0_PD_SCL, - .sda = GPIO_EC_I2C_USB_C0_PD_SDA - }, - { - .name = "tcpc1", - .port = I2C_PORT_TCPC1, - .kbps = 1000, - .scl = GPIO_EC_I2C_USB_C1_PD_SCL, - .sda = GPIO_EC_I2C_USB_C1_PD_SDA - }, - { - .name = "eeprom", - .port = I2C_PORT_EEPROM, - .kbps = 400, - .scl = GPIO_EC_I2C_EEPROM_SCL, - .sda = GPIO_EC_I2C_EEPROM_SDA - }, - { - .name = "sensor", - .port = I2C_PORT_SENSOR, - .kbps = 400, - .scl = GPIO_EC_I2C_SENSOR_SCL, - .sda = GPIO_EC_I2C_SENSOR_SDA - }, + { .name = "power", + .port = I2C_PORT_POWER, + .kbps = 100, + .scl = GPIO_EC_I2C_POWER_SCL, + .sda = GPIO_EC_I2C_POWER_SDA }, + { .name = "tcpc0", + .port = I2C_PORT_TCPC0, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C0_PD_SCL, + .sda = GPIO_EC_I2C_USB_C0_PD_SDA }, + { .name = "tcpc1", + .port = I2C_PORT_TCPC1, + .kbps = 1000, + .scl = GPIO_EC_I2C_USB_C1_PD_SCL, + .sda = GPIO_EC_I2C_USB_C1_PD_SDA }, + { .name = "eeprom", + .port = I2C_PORT_EEPROM, + .kbps = 400, + .scl = GPIO_EC_I2C_EEPROM_SCL, + .sda = GPIO_EC_I2C_EEPROM_SDA }, + { .name = "sensor", + .port = I2C_PORT_SENSOR, + .kbps = 400, + .scl = GPIO_EC_I2C_SENSOR_SCL, + .sda = GPIO_EC_I2C_SENSOR_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); @@ -121,37 +108,22 @@ const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); /* ADC channels */ const struct adc_t adc_channels[] = { /* Measure VBUS through a 1/10 voltage divider */ - [ADC_VBUS] = { - "VBUS", - NPCX_ADC_CH1, - ADC_MAX_VOLT * 10, - ADC_READ_MAX + 1, - 0 - }, + [ADC_VBUS] = { "VBUS", NPCX_ADC_CH1, ADC_MAX_VOLT * 10, + ADC_READ_MAX + 1, 0 }, /* * Adapter current output or battery charging/discharging current (uV) * 18x amplification on charger side. */ - [ADC_AMON_BMON] = { - "AMON_BMON", - NPCX_ADC_CH2, - ADC_MAX_VOLT * 1000 / 18, - ADC_READ_MAX + 1, - 0 - }, + [ADC_AMON_BMON] = { "AMON_BMON", NPCX_ADC_CH2, ADC_MAX_VOLT * 1000 / 18, + ADC_READ_MAX + 1, 0 }, /* * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor, to read * 0.8V @ 99 W, i.e. 124000 uW/mV. Using ADC_MAX_VOLT*124000 and * ADC_READ_MAX+1 as multiplier/divider leads to overflows, so we * only divide by 2 (enough to avoid precision issues). */ - [ADC_PSYS] = { - "PSYS", - NPCX_ADC_CH3, - ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), - 2, - 0 - }, + [ADC_PSYS] = { "PSYS", NPCX_ADC_CH3, + ADC_MAX_VOLT * 124000 * 2 / (ADC_READ_MAX + 1), 2, 0 }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); @@ -178,29 +150,21 @@ enum base_accelgyro_type { }; /* Matrix to rotate accelerometer into standard reference frame */ -const mat33_fp_t base_standard_ref_bmi160 = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_bmi160 = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -const mat33_fp_t base_standard_ref_icm426xx = { - { 0, FLOAT_TO_FP(1), 0}, - { FLOAT_TO_FP(1), 0, 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +const mat33_fp_t base_standard_ref_icm426xx = { { 0, FLOAT_TO_FP(1), 0 }, + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t lid_standard_ref_bma255 = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref_bma255 = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; -static const mat33_fp_t lid_standard_ref_kx022 = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(1)} -}; +static const mat33_fp_t lid_standard_ref_kx022 = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -372,7 +336,7 @@ static void board_detect_motionsensor(void) /* Check lid accel chip */ ret = i2c_read8(I2C_PORT_SENSOR, BMA2x2_I2C_ADDR1_FLAGS, - BMA2x2_CHIP_ID_ADDR, &val); + BMA2x2_CHIP_ID_ADDR, &val); if (ret) motion_sensors[LID_ACCEL] = kx022_lid_accel; @@ -385,10 +349,11 @@ static void board_detect_motionsensor(void) motion_sensors[BASE_GYRO] = icm426xx_base_gyro; } - base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) - ? BASE_GYRO_ICM426XX : BASE_GYRO_BMI160; - CPRINTS("Base Accelgyro: %s", (val == ICM426XX_CHIP_ICM40608) - ? "ICM40608" : "BMI160"); + base_accelgyro_config = (val == ICM426XX_CHIP_ICM40608) ? + BASE_GYRO_ICM426XX : + BASE_GYRO_BMI160; + CPRINTS("Base Accelgyro: %s", + (val == ICM426XX_CHIP_ICM40608) ? "ICM40608" : "BMI160"); } static void board_update_sensor_config_from_sku(void) -- cgit v1.2.1 From 7468eea7d9cb4d30112ffd79f2521c55afc89213 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:31 -0600 Subject: board/osiris/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I55fd69eb42cc15ceb05bf183a80ba3954f22d314 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728795 Reviewed-by: Jeremy Bettis --- board/osiris/board.h | 124 +++++++++++++++++++++++---------------------------- 1 file changed, 56 insertions(+), 68 deletions(-) diff --git a/board/osiris/board.h b/board/osiris/board.h index aee05b025e..d52f52878e 100644 --- a/board/osiris/board.h +++ b/board/osiris/board.h @@ -25,7 +25,7 @@ #define CONFIG_LED_ONOFF_STATES /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB #undef CONFIG_USB_PD_TCPM_NCT38XX @@ -48,17 +48,17 @@ #define CONFIG_USBC_PPC_SYV682X /* TODO: b/177608416 - measure and check these values on osiris */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ /* * Passive USB-C cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 60000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -66,56 +66,55 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL - +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* I2C Bus Configuration */ -#define I2C_PORT_RGBKB NPCX_I2C_PORT0_0 +#define I2C_PORT_RGBKB NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C1_TCPC NPCX_I2C_PORT4_1 -#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C0_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C1_BC12 NPCX_I2C_PORT6_1 -#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 +#define I2C_PORT_USB_C1_MUX NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_MP2964 NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 -#define I2C_ADDR_MP2964_FLAGS 0x20 +#define I2C_ADDR_MP2964_FLAGS 0x20 /* Thermal features */ #define CONFIG_THERMISTOR @@ -123,32 +122,32 @@ #define CONFIG_TEMP_SENSOR_POWER #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 #define CONFIG_CHARGE_RAMP_SW -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #undef CONFIG_VOLUME_BUTTONS /* RGB Keyboard */ #define CONFIG_KEYBOARD_BACKLIGHT -#define GPIO_RGBKBD_SDB_L GPIO_EC_KB_BL_EN_L +#define GPIO_RGBKBD_SDB_L GPIO_EC_KB_BL_EN_L #ifdef SECTION_IS_RW #define CONFIG_RGB_KEYBOARD -#define CONFIG_LED_DRIVER_IS31FL3733B /* is31fl3733b on I2C */ +#define CONFIG_LED_DRIVER_IS31FL3733B /* is31fl3733b on I2C */ #endif -#define RGB_GRID0_COL 12 -#define RGB_GRID0_ROW 1 -#define I2C_PORT_KBMCU I2C_PORT_RGBKB +#define RGB_GRID0_COL 12 +#define RGB_GRID0_ROW 1 +#define I2C_PORT_KBMCU I2C_PORT_RGBKB #define CONFIG_KEYBOARD_FACTORY_TEST #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -166,28 +165,17 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum battery_type { - BATTERY_COSMX_AP22ABN, - BATTERY_TYPE_COUNT -}; +enum battery_type { BATTERY_COSMX_AP22ABN, BATTERY_TYPE_COUNT }; enum pwm_channel { - PWM_CH_FAN = 0, /* PWM5 */ - PWM_CH_FAN2, /* PWM3 */ + PWM_CH_FAN = 0, /* PWM5 */ + PWM_CH_FAN2, /* PWM3 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_1, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_1, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT }; #ifdef CONFIG_KEYBOARD_FACTORY_TEST extern const int keyboard_factory_scan_pins[][2]; -- cgit v1.2.1 From 8215f047456fec5682a23dfae44171211ff40aae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:50 -0600 Subject: extra/ftdi_hostcmd/test_cmds.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Idbf9e30205e384c290cef42d8cd9bf45f7cda89d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730178 Reviewed-by: Jeremy Bettis --- extra/ftdi_hostcmd/test_cmds.c | 296 +++++++++++++++++++---------------------- 1 file changed, 137 insertions(+), 159 deletions(-) diff --git a/extra/ftdi_hostcmd/test_cmds.c b/extra/ftdi_hostcmd/test_cmds.c index edacfbb93c..5acac192d7 100644 --- a/extra/ftdi_hostcmd/test_cmds.c +++ b/extra/ftdi_hostcmd/test_cmds.c @@ -22,7 +22,7 @@ static struct mpsse_context *mpsse; /* enum ec_status meaning */ static const char *ec_strerr(enum ec_status r) { - static const char * const strs[] = { + static const char *const strs[] = { "SUCCESS", "INVALID_COMMAND", "ERROR", @@ -47,10 +47,9 @@ static const char *ec_strerr(enum ec_status r) return ""; }; - -/**************************************************************************** - * Debugging output - */ + /**************************************************************************** + * Debugging output + */ #define LINELEN 16 @@ -64,8 +63,7 @@ static void showline(uint8_t *buf, int len) printf(" "); printf(" "); for (i = 0; i < len; i++) - printf("%c", - (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.'); + printf("%c", (buf[i] >= ' ' && buf[i] <= '~') ? buf[i] : '.'); printf("\n"); } @@ -104,8 +102,8 @@ static uint8_t txbuf[128]; * Load the output buffer with a proto v3 request (header, then data, with * checksum correct in header). */ -static size_t prepare_request(int cmd, int version, - const uint8_t *data, size_t data_len) +static size_t prepare_request(int cmd, int version, const uint8_t *data, + size_t data_len) { struct ec_host_request *request; size_t i, total_len; @@ -113,8 +111,8 @@ static size_t prepare_request(int cmd, int version, total_len = sizeof(*request) + data_len; if (total_len > sizeof(txbuf)) { - printf("Request too large (%zd > %zd)\n", - total_len, sizeof(txbuf)); + printf("Request too large (%zd > %zd)\n", total_len, + sizeof(txbuf)); return -1; } @@ -153,8 +151,7 @@ static int send_request(uint8_t *txbuf, size_t len) tptr = Transfer(mpsse, txbuf, len); if (!tptr) { - fprintf(stderr, "Transfer failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Transfer failed: %s\n", ErrorString(mpsse)); return -1; } @@ -178,7 +175,6 @@ static int send_request(uint8_t *txbuf, size_t len) return ret; } - /* Timeout flag, so we don't wait forever */ static int timedout; static void alarm_handler(int sig) @@ -195,8 +191,8 @@ static void alarm_handler(int sig) * 0 = response received (check hdr for EC result and body size) * -1 = problems */ -static int get_response(struct ec_host_response *hdr, - uint8_t *bodydest, size_t bodylen) +static int get_response(struct ec_host_response *hdr, uint8_t *bodydest, + size_t bodylen) { uint8_t *hptr = 0, *bptr = 0; uint8_t sum = 0; @@ -237,8 +233,7 @@ static int get_response(struct ec_host_response *hdr, /* Now read the response header */ hptr = Read(mpsse, sizeof(*hdr)); if (!hptr) { - fprintf(stderr, "Read failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Read failed: %s\n", ErrorString(mpsse)); goto out; } show("Header(%d):\n", hptr, sizeof(*hdr)); @@ -247,14 +242,12 @@ static int get_response(struct ec_host_response *hdr, /* Check the header */ if (hdr->struct_version != EC_HOST_RESPONSE_VERSION) { printf("response version %d (should be %d)\n", - hdr->struct_version, - EC_HOST_RESPONSE_VERSION); + hdr->struct_version, EC_HOST_RESPONSE_VERSION); goto out; } if (hdr->data_len > bodylen) { - printf("response data_len %d is > %zd\n", - hdr->data_len, + printf("response data_len %d is > %zd\n", hdr->data_len, bodylen); goto out; } @@ -290,19 +283,13 @@ out: return ret; } - /* * Send command, wait for result. Return zero if communication succeeded; check * response to see if the EC liked the command. */ -static int send_cmd(int cmd, int version, - void *outbuf, - size_t outsize, - struct ec_host_response *resp, - void *inbuf, - size_t insize) +static int send_cmd(int cmd, int version, void *outbuf, size_t outsize, + struct ec_host_response *resp, void *inbuf, size_t insize) { - size_t len; int ret = -1; @@ -312,8 +299,7 @@ static int send_cmd(int cmd, int version, return -1; if (MPSSE_OK != Start(mpsse)) { - fprintf(stderr, "Start failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Start failed: %s\n", ErrorString(mpsse)); return -1; } @@ -322,15 +308,13 @@ static int send_cmd(int cmd, int version, ret = 0; if (MPSSE_OK != Stop(mpsse)) { - fprintf(stderr, "Stop failed: %s\n", - ErrorString(mpsse)); + fprintf(stderr, "Stop failed: %s\n", ErrorString(mpsse)); return -1; } return ret; } - /**************************************************************************** * Probe for basic protocol info */ @@ -352,10 +336,8 @@ static int probe_v3(void) if (opt_verbose) printf("Trying EC_CMD_GET_PROTOCOL_INFO...\n"); - ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0, - 0, 0, - &resp, - &info, sizeof(info)); + ret = send_cmd(EC_CMD_GET_PROTOCOL_INFO, 0, 0, 0, &resp, &info, + sizeof(info)); if (ret) { printf("EC_CMD_GET_PROTOCOL_INFO failed\n"); @@ -363,8 +345,8 @@ static int probe_v3(void) } if (EC_RES_SUCCESS != resp.result) { - printf("EC result is %d: %s\n", - resp.result, ec_strerr(resp.result)); + printf("EC result is %d: %s\n", resp.result, + ec_strerr(resp.result)); return -1; } @@ -378,8 +360,7 @@ static int probe_v3(void) info.max_request_packet_size); printf(" max_response_packet_size: %d\n", info.max_response_packet_size); - printf(" flags: 0x%x\n", - info.flags); + printf(" flags: 0x%x\n", info.flags); return 0; } @@ -390,118 +371,118 @@ static int probe_v3(void) struct lookup { uint16_t cmd; - const char * const desc; + const char *const desc; }; static struct lookup cmd_table[] = { - {0x00, "EC_CMD_PROTO_VERSION"}, - {0x01, "EC_CMD_HELLO"}, - {0x02, "EC_CMD_GET_VERSION"}, - {0x03, "EC_CMD_READ_TEST"}, - {0x04, "EC_CMD_GET_BUILD_INFO"}, - {0x05, "EC_CMD_GET_CHIP_INFO"}, - {0x06, "EC_CMD_GET_BOARD_VERSION"}, - {0x07, "EC_CMD_READ_MEMMAP"}, - {0x08, "EC_CMD_GET_CMD_VERSIONS"}, - {0x09, "EC_CMD_GET_COMMS_STATUS"}, - {0x0a, "EC_CMD_TEST_PROTOCOL"}, - {0x0b, "EC_CMD_GET_PROTOCOL_INFO"}, - {0x0c, "EC_CMD_GSV_PAUSE_IN_S5"}, - {0x0d, "EC_CMD_GET_FEATURES"}, - {0x10, "EC_CMD_FLASH_INFO"}, - {0x11, "EC_CMD_FLASH_READ"}, - {0x12, "EC_CMD_FLASH_WRITE"}, - {0x13, "EC_CMD_FLASH_ERASE"}, - {0x15, "EC_CMD_FLASH_PROTECT"}, - {0x16, "EC_CMD_FLASH_REGION_INFO"}, - {0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM"}, - {0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM"}, - {0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT"}, - {0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT"}, - {0x24, "EC_CMD_PWM_SET_FAN_DUTY"}, - {0x28, "EC_CMD_LIGHTBAR_CMD"}, - {0x29, "EC_CMD_LED_CONTROL"}, - {0x2a, "EC_CMD_VBOOT_HASH"}, - {0x2b, "EC_CMD_MOTION_SENSE_CMD"}, - {0x2c, "EC_CMD_FORCE_LID_OPEN"}, - {0x30, "EC_CMD_USB_CHARGE_SET_MODE"}, - {0x40, "EC_CMD_PSTORE_INFO"}, - {0x41, "EC_CMD_PSTORE_READ"}, - {0x42, "EC_CMD_PSTORE_WRITE"}, - {0x44, "EC_CMD_RTC_GET_VALUE"}, - {0x45, "EC_CMD_RTC_GET_ALARM"}, - {0x46, "EC_CMD_RTC_SET_VALUE"}, - {0x47, "EC_CMD_RTC_SET_ALARM"}, - {0x48, "EC_CMD_PORT80_LAST_BOOT"}, - {0x48, "EC_CMD_PORT80_READ"}, - {0x50, "EC_CMD_THERMAL_SET_THRESHOLD"}, - {0x51, "EC_CMD_THERMAL_GET_THRESHOLD"}, - {0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL"}, - {0x53, "EC_CMD_TMP006_GET_CALIBRATION"}, - {0x54, "EC_CMD_TMP006_SET_CALIBRATION"}, - {0x55, "EC_CMD_TMP006_GET_RAW"}, - {0x60, "EC_CMD_MKBP_STATE"}, - {0x61, "EC_CMD_MKBP_INFO"}, - {0x62, "EC_CMD_MKBP_SIMULATE_KEY"}, - {0x64, "EC_CMD_MKBP_SET_CONFIG"}, - {0x65, "EC_CMD_MKBP_GET_CONFIG"}, - {0x66, "EC_CMD_KEYSCAN_SEQ_CTRL"}, - {0x67, "EC_CMD_GET_NEXT_EVENT"}, - {0x70, "EC_CMD_TEMP_SENSOR_GET_INFO"}, - {0x87, "EC_CMD_HOST_EVENT_GET_B"}, - {0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK"}, - {0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK"}, - {0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK"}, - {0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK"}, - {0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK"}, - {0x8c, "EC_CMD_HOST_EVENT_CLEAR"}, - {0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK"}, - {0x8f, "EC_CMD_HOST_EVENT_CLEAR_B"}, - {0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT"}, - {0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS"}, - {0x92, "EC_CMD_GPIO_SET"}, - {0x93, "EC_CMD_GPIO_GET"}, - {0x94, "EC_CMD_I2C_READ"}, - {0x95, "EC_CMD_I2C_WRITE"}, - {0x96, "EC_CMD_CHARGE_CONTROL"}, - {0x97, "EC_CMD_CONSOLE_SNAPSHOT"}, - {0x98, "EC_CMD_CONSOLE_READ"}, - {0x99, "EC_CMD_BATTERY_CUT_OFF"}, - {0x9a, "EC_CMD_USB_MUX"}, - {0x9b, "EC_CMD_LDO_SET"}, - {0x9c, "EC_CMD_LDO_GET"}, - {0x9d, "EC_CMD_POWER_INFO"}, - {0x9e, "EC_CMD_I2C_PASSTHRU"}, - {0x9f, "EC_CMD_HANG_DETECT"}, - {0xa0, "EC_CMD_CHARGE_STATE"}, - {0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT"}, - {0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT"}, - {0xb0, "EC_CMD_SB_READ_WORD"}, - {0xb1, "EC_CMD_SB_WRITE_WORD"}, - {0xb2, "EC_CMD_SB_READ_BLOCK"}, - {0xb3, "EC_CMD_SB_WRITE_BLOCK"}, - {0xb4, "EC_CMD_BATTERY_VENDOR_PARAM"}, - {0xb5, "EC_CMD_SB_FW_UPDATE"}, - {0xd2, "EC_CMD_REBOOT_EC"}, - {0xd3, "EC_CMD_GET_PANIC_INFO"}, - {0xd1, "EC_CMD_REBOOT"}, - {0xdb, "EC_CMD_RESEND_RESPONSE"}, - {0xdc, "EC_CMD_VERSION0"}, - {0x100, "EC_CMD_PD_EXCHANGE_STATUS"}, - {0x104, "EC_CMD_PD_HOST_EVENT_STATUS"}, - {0x101, "EC_CMD_USB_PD_CONTROL"}, - {0x102, "EC_CMD_USB_PD_PORTS"}, - {0x103, "EC_CMD_USB_PD_POWER_INFO"}, - {0x110, "EC_CMD_USB_PD_FW_UPDATE"}, - {0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY"}, - {0x112, "EC_CMD_USB_PD_DEV_INFO"}, - {0x113, "EC_CMD_USB_PD_DISCOVERY"}, - {0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE"}, - {0x115, "EC_CMD_PD_GET_LOG_ENTRY"}, - {0x116, "EC_CMD_USB_PD_GET_AMODE"}, - {0x117, "EC_CMD_USB_PD_SET_AMODE"}, - {0x118, "EC_CMD_PD_WRITE_LOG_ENTRY"}, - {0x200, "EC_CMD_BLOB"}, + { 0x00, "EC_CMD_PROTO_VERSION" }, + { 0x01, "EC_CMD_HELLO" }, + { 0x02, "EC_CMD_GET_VERSION" }, + { 0x03, "EC_CMD_READ_TEST" }, + { 0x04, "EC_CMD_GET_BUILD_INFO" }, + { 0x05, "EC_CMD_GET_CHIP_INFO" }, + { 0x06, "EC_CMD_GET_BOARD_VERSION" }, + { 0x07, "EC_CMD_READ_MEMMAP" }, + { 0x08, "EC_CMD_GET_CMD_VERSIONS" }, + { 0x09, "EC_CMD_GET_COMMS_STATUS" }, + { 0x0a, "EC_CMD_TEST_PROTOCOL" }, + { 0x0b, "EC_CMD_GET_PROTOCOL_INFO" }, + { 0x0c, "EC_CMD_GSV_PAUSE_IN_S5" }, + { 0x0d, "EC_CMD_GET_FEATURES" }, + { 0x10, "EC_CMD_FLASH_INFO" }, + { 0x11, "EC_CMD_FLASH_READ" }, + { 0x12, "EC_CMD_FLASH_WRITE" }, + { 0x13, "EC_CMD_FLASH_ERASE" }, + { 0x15, "EC_CMD_FLASH_PROTECT" }, + { 0x16, "EC_CMD_FLASH_REGION_INFO" }, + { 0x20, "EC_CMD_PWM_GET_FAN_TARGET_RPM" }, + { 0x21, "EC_CMD_PWM_SET_FAN_TARGET_RPM" }, + { 0x22, "EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT" }, + { 0x23, "EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT" }, + { 0x24, "EC_CMD_PWM_SET_FAN_DUTY" }, + { 0x28, "EC_CMD_LIGHTBAR_CMD" }, + { 0x29, "EC_CMD_LED_CONTROL" }, + { 0x2a, "EC_CMD_VBOOT_HASH" }, + { 0x2b, "EC_CMD_MOTION_SENSE_CMD" }, + { 0x2c, "EC_CMD_FORCE_LID_OPEN" }, + { 0x30, "EC_CMD_USB_CHARGE_SET_MODE" }, + { 0x40, "EC_CMD_PSTORE_INFO" }, + { 0x41, "EC_CMD_PSTORE_READ" }, + { 0x42, "EC_CMD_PSTORE_WRITE" }, + { 0x44, "EC_CMD_RTC_GET_VALUE" }, + { 0x45, "EC_CMD_RTC_GET_ALARM" }, + { 0x46, "EC_CMD_RTC_SET_VALUE" }, + { 0x47, "EC_CMD_RTC_SET_ALARM" }, + { 0x48, "EC_CMD_PORT80_LAST_BOOT" }, + { 0x48, "EC_CMD_PORT80_READ" }, + { 0x50, "EC_CMD_THERMAL_SET_THRESHOLD" }, + { 0x51, "EC_CMD_THERMAL_GET_THRESHOLD" }, + { 0x52, "EC_CMD_THERMAL_AUTO_FAN_CTRL" }, + { 0x53, "EC_CMD_TMP006_GET_CALIBRATION" }, + { 0x54, "EC_CMD_TMP006_SET_CALIBRATION" }, + { 0x55, "EC_CMD_TMP006_GET_RAW" }, + { 0x60, "EC_CMD_MKBP_STATE" }, + { 0x61, "EC_CMD_MKBP_INFO" }, + { 0x62, "EC_CMD_MKBP_SIMULATE_KEY" }, + { 0x64, "EC_CMD_MKBP_SET_CONFIG" }, + { 0x65, "EC_CMD_MKBP_GET_CONFIG" }, + { 0x66, "EC_CMD_KEYSCAN_SEQ_CTRL" }, + { 0x67, "EC_CMD_GET_NEXT_EVENT" }, + { 0x70, "EC_CMD_TEMP_SENSOR_GET_INFO" }, + { 0x87, "EC_CMD_HOST_EVENT_GET_B" }, + { 0x88, "EC_CMD_HOST_EVENT_GET_SMI_MASK" }, + { 0x89, "EC_CMD_HOST_EVENT_GET_SCI_MASK" }, + { 0x8d, "EC_CMD_HOST_EVENT_GET_WAKE_MASK" }, + { 0x8a, "EC_CMD_HOST_EVENT_SET_SMI_MASK" }, + { 0x8b, "EC_CMD_HOST_EVENT_SET_SCI_MASK" }, + { 0x8c, "EC_CMD_HOST_EVENT_CLEAR" }, + { 0x8e, "EC_CMD_HOST_EVENT_SET_WAKE_MASK" }, + { 0x8f, "EC_CMD_HOST_EVENT_CLEAR_B" }, + { 0x90, "EC_CMD_SWITCH_ENABLE_BKLIGHT" }, + { 0x91, "EC_CMD_SWITCH_ENABLE_WIRELESS" }, + { 0x92, "EC_CMD_GPIO_SET" }, + { 0x93, "EC_CMD_GPIO_GET" }, + { 0x94, "EC_CMD_I2C_READ" }, + { 0x95, "EC_CMD_I2C_WRITE" }, + { 0x96, "EC_CMD_CHARGE_CONTROL" }, + { 0x97, "EC_CMD_CONSOLE_SNAPSHOT" }, + { 0x98, "EC_CMD_CONSOLE_READ" }, + { 0x99, "EC_CMD_BATTERY_CUT_OFF" }, + { 0x9a, "EC_CMD_USB_MUX" }, + { 0x9b, "EC_CMD_LDO_SET" }, + { 0x9c, "EC_CMD_LDO_GET" }, + { 0x9d, "EC_CMD_POWER_INFO" }, + { 0x9e, "EC_CMD_I2C_PASSTHRU" }, + { 0x9f, "EC_CMD_HANG_DETECT" }, + { 0xa0, "EC_CMD_CHARGE_STATE" }, + { 0xa1, "EC_CMD_CHARGE_CURRENT_LIMIT" }, + { 0xa2, "EC_CMD_EXT_POWER_CURRENT_LIMIT" }, + { 0xb0, "EC_CMD_SB_READ_WORD" }, + { 0xb1, "EC_CMD_SB_WRITE_WORD" }, + { 0xb2, "EC_CMD_SB_READ_BLOCK" }, + { 0xb3, "EC_CMD_SB_WRITE_BLOCK" }, + { 0xb4, "EC_CMD_BATTERY_VENDOR_PARAM" }, + { 0xb5, "EC_CMD_SB_FW_UPDATE" }, + { 0xd2, "EC_CMD_REBOOT_EC" }, + { 0xd3, "EC_CMD_GET_PANIC_INFO" }, + { 0xd1, "EC_CMD_REBOOT" }, + { 0xdb, "EC_CMD_RESEND_RESPONSE" }, + { 0xdc, "EC_CMD_VERSION0" }, + { 0x100, "EC_CMD_PD_EXCHANGE_STATUS" }, + { 0x104, "EC_CMD_PD_HOST_EVENT_STATUS" }, + { 0x101, "EC_CMD_USB_PD_CONTROL" }, + { 0x102, "EC_CMD_USB_PD_PORTS" }, + { 0x103, "EC_CMD_USB_PD_POWER_INFO" }, + { 0x110, "EC_CMD_USB_PD_FW_UPDATE" }, + { 0x111, "EC_CMD_USB_PD_RW_HASH_ENTRY" }, + { 0x112, "EC_CMD_USB_PD_DEV_INFO" }, + { 0x113, "EC_CMD_USB_PD_DISCOVERY" }, + { 0x114, "EC_CMD_PD_CHARGE_PORT_OVERRIDE" }, + { 0x115, "EC_CMD_PD_GET_LOG_ENTRY" }, + { 0x116, "EC_CMD_USB_PD_GET_AMODE" }, + { 0x117, "EC_CMD_USB_PD_SET_AMODE" }, + { 0x118, "EC_CMD_PD_WRITE_LOG_ENTRY" }, + { 0x200, "EC_CMD_BLOB" }, }; #define ARRAY_SIZE(A) (sizeof(A) / sizeof(A[0])) @@ -531,15 +512,13 @@ static void scan_commands(uint16_t start, uint16_t stop) printf("Supported host commands:\n"); for (i = start; i <= stop; i++) { - if (opt_verbose) printf("Querying CMD %02x\n", i); q_vers.cmd = i; - if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1, - &q_vers, sizeof(q_vers), - &ec_resp, - &r_vers, sizeof(r_vers))) { + if (0 != send_cmd(EC_CMD_GET_CMD_VERSIONS, 1, &q_vers, + sizeof(q_vers), &ec_resp, &r_vers, + sizeof(r_vers))) { printf("query failed on cmd %02x - aborting\n", i); return; } @@ -556,8 +535,7 @@ static void scan_commands(uint16_t start, uint16_t stop) break; default: printf("lookup of cmd %02x returned %d %s\n", i, - ec_resp.result, - ec_strerr(ec_resp.result)); + ec_resp.result, ec_strerr(ec_resp.result)); } } } -- cgit v1.2.1 From 2369c8f88a3bd87ebe53df1dbcb10b3810b9370e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:40 -0600 Subject: board/crota/sensors.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ia76038ddd526c61bcaebc42430b34280824726da Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728214 Reviewed-by: Jeremy Bettis --- board/crota/sensors.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/board/crota/sensors.c b/board/crota/sensors.c index 05eae65783..a50ad4a298 100644 --- a/board/crota/sensors.c +++ b/board/crota/sensors.c @@ -55,18 +55,14 @@ static struct stprivate_data g_lis2dw12_data; static struct lsm6dso_data lsm6dso_data; /* TODO(b/184779333): calibrate the orientation matrix on later board stage */ -static const mat33_fp_t lid_standard_ref = { - { FLOAT_TO_FP(1), 0, 0}, - { 0, FLOAT_TO_FP(-1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* TODO(b/184779743): verify orientation matrix */ -static const mat33_fp_t base_standard_ref = { - { FLOAT_TO_FP(-1), 0, 0}, - { 0, FLOAT_TO_FP(1), 0}, - { 0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; struct motion_sensor_t motion_sensors[] = { [LID_ACCEL] = { @@ -182,8 +178,8 @@ const struct temp_sensor_t temp_sensors[] = { }; BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); -#define THERMAL_CPU \ - { \ +#define THERMAL_CPU \ + { \ .temp_host = { \ [EC_TEMP_THRESH_HIGH] = C_TO_K(77), \ [EC_TEMP_THRESH_HALT] = C_TO_K(80), \ @@ -196,18 +192,16 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -#define THERMAL_CHARGER \ - { \ - .temp_fan_off = C_TO_K(59), \ - .temp_fan_max = C_TO_K(65), \ +#define THERMAL_CHARGER \ + { \ + .temp_fan_off = C_TO_K(59), .temp_fan_max = C_TO_K(65), \ } __maybe_unused static const struct ec_thermal_config thermal_charger = THERMAL_CHARGER; -#define THERMAL_AMBIENT \ - { \ - .temp_fan_off = C_TO_K(26), \ - .temp_fan_max = C_TO_K(31), \ +#define THERMAL_AMBIENT \ + { \ + .temp_fan_off = C_TO_K(26), .temp_fan_max = C_TO_K(31), \ } __maybe_unused static const struct ec_thermal_config thermal_ambient = THERMAL_AMBIENT; -- cgit v1.2.1 From a321b179230c9e1de0c34237a6391c7ea4b77439 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:54 -0600 Subject: include/battery_smart.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I82d808aac6d435766d9cf8f94cbe99df74bf1bd6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730211 Reviewed-by: Jeremy Bettis --- include/battery_smart.h | 270 ++++++++++++++++++++++++------------------------ 1 file changed, 135 insertions(+), 135 deletions(-) diff --git a/include/battery_smart.h b/include/battery_smart.h index cdc69e4ffd..40737750ba 100644 --- a/include/battery_smart.h +++ b/include/battery_smart.h @@ -11,168 +11,168 @@ #include "common.h" /* Smart battery and charger I2C address */ -#define BATTERY_ADDR_FLAGS 0x0B -#define CHARGER_ADDR_FLAGS 0x09 +#define BATTERY_ADDR_FLAGS 0x0B +#define CHARGER_ADDR_FLAGS 0x09 /* Charger functions */ -#define SB_CHARGER_SPEC_INFO 0x11 -#define SB_CHARGE_MODE 0x12 -#define SB_CHARGER_STATUS 0x13 -#define SB_CHARGING_CURRENT 0x14 -#define SB_CHARGING_VOLTAGE 0x15 -#define SB_ALARM_WARNING 0x16 +#define SB_CHARGER_SPEC_INFO 0x11 +#define SB_CHARGE_MODE 0x12 +#define SB_CHARGER_STATUS 0x13 +#define SB_CHARGING_CURRENT 0x14 +#define SB_CHARGING_VOLTAGE 0x15 +#define SB_ALARM_WARNING 0x16 /* Battery functions */ -#define SB_MANUFACTURER_ACCESS 0x00 -#define SB_REMAINING_CAPACITY_ALARM 0x01 -#define SB_REMAINING_TIME_ALARM 0x02 -#define SB_BATTERY_MODE 0x03 -#define SB_AT_RATE 0x04 -#define SB_AT_RATE_TIME_TO_FULL 0x05 -#define SB_AT_RATE_TIME_TO_EMPTY 0x06 -#define SB_AT_RATE_OK 0x07 -#define SB_TEMPERATURE 0x08 -#define SB_VOLTAGE 0x09 -#define SB_CURRENT 0x0a -#define SB_AVERAGE_CURRENT 0x0b -#define SB_MAX_ERROR 0x0c -#define SB_RELATIVE_STATE_OF_CHARGE 0x0d -#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e -#define SB_REMAINING_CAPACITY 0x0f -#define SB_FULL_CHARGE_CAPACITY 0x10 -#define SB_RUN_TIME_TO_EMPTY 0x11 -#define SB_AVERAGE_TIME_TO_EMPTY 0x12 -#define SB_AVERAGE_TIME_TO_FULL 0x13 -#define SB_CHARGING_CURRENT 0x14 -#define SB_CHARGING_VOLTAGE 0x15 -#define SB_BATTERY_STATUS 0x16 -#define SB_CYCLE_COUNT 0x17 -#define SB_DESIGN_CAPACITY 0x18 -#define SB_DESIGN_VOLTAGE 0x19 -#define SB_SPECIFICATION_INFO 0x1a -#define SB_MANUFACTURE_DATE 0x1b -#define SB_SERIAL_NUMBER 0x1c -#define SB_MANUFACTURER_NAME 0x20 -#define SB_DEVICE_NAME 0x21 -#define SB_DEVICE_CHEMISTRY 0x22 -#define SB_MANUFACTURER_DATA 0x23 -#define SB_OPTIONAL_MFG_FUNC1 0x3C -#define SB_OPTIONAL_MFG_FUNC2 0x3D -#define SB_OPTIONAL_MFG_FUNC3 0x3E -#define SB_OPTIONAL_MFG_FUNC4 0x3F +#define SB_MANUFACTURER_ACCESS 0x00 +#define SB_REMAINING_CAPACITY_ALARM 0x01 +#define SB_REMAINING_TIME_ALARM 0x02 +#define SB_BATTERY_MODE 0x03 +#define SB_AT_RATE 0x04 +#define SB_AT_RATE_TIME_TO_FULL 0x05 +#define SB_AT_RATE_TIME_TO_EMPTY 0x06 +#define SB_AT_RATE_OK 0x07 +#define SB_TEMPERATURE 0x08 +#define SB_VOLTAGE 0x09 +#define SB_CURRENT 0x0a +#define SB_AVERAGE_CURRENT 0x0b +#define SB_MAX_ERROR 0x0c +#define SB_RELATIVE_STATE_OF_CHARGE 0x0d +#define SB_ABSOLUTE_STATE_OF_CHARGE 0x0e +#define SB_REMAINING_CAPACITY 0x0f +#define SB_FULL_CHARGE_CAPACITY 0x10 +#define SB_RUN_TIME_TO_EMPTY 0x11 +#define SB_AVERAGE_TIME_TO_EMPTY 0x12 +#define SB_AVERAGE_TIME_TO_FULL 0x13 +#define SB_CHARGING_CURRENT 0x14 +#define SB_CHARGING_VOLTAGE 0x15 +#define SB_BATTERY_STATUS 0x16 +#define SB_CYCLE_COUNT 0x17 +#define SB_DESIGN_CAPACITY 0x18 +#define SB_DESIGN_VOLTAGE 0x19 +#define SB_SPECIFICATION_INFO 0x1a +#define SB_MANUFACTURE_DATE 0x1b +#define SB_SERIAL_NUMBER 0x1c +#define SB_MANUFACTURER_NAME 0x20 +#define SB_DEVICE_NAME 0x21 +#define SB_DEVICE_CHEMISTRY 0x22 +#define SB_MANUFACTURER_DATA 0x23 +#define SB_OPTIONAL_MFG_FUNC1 0x3C +#define SB_OPTIONAL_MFG_FUNC2 0x3D +#define SB_OPTIONAL_MFG_FUNC3 0x3E +#define SB_OPTIONAL_MFG_FUNC4 0x3F /* Extension of smart battery spec, may not be supported on all platforms */ -#define SB_PACK_STATUS 0x43 -#define SB_ALT_MANUFACTURER_ACCESS 0x44 -#define SB_MANUFACTURE_INFO 0x70 +#define SB_PACK_STATUS 0x43 +#define SB_ALT_MANUFACTURER_ACCESS 0x44 +#define SB_MANUFACTURE_INFO 0x70 /* Battery mode */ #define MODE_INTERNAL_CHARGE_CONTROLLER BIT(0) -#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1) -#define MODE_CONDITION_CYCLE BIT(7) -#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8) -#define MODE_PRIMARY_BATTERY BIT(9) -#define MODE_ALARM BIT(13) -#define MODE_CHARGER BIT(14) -#define MODE_CAPACITY BIT(15) +#define MODE_PRIMARY_BATTERY_SUPPORT BIT(1) +#define MODE_CONDITION_CYCLE BIT(7) +#define MODE_CHARGE_CONTROLLER_ENABLED BIT(8) +#define MODE_PRIMARY_BATTERY BIT(9) +#define MODE_ALARM BIT(13) +#define MODE_CHARGER BIT(14) +#define MODE_CAPACITY BIT(15) /* Battery status */ -#define STATUS_ERR_CODE_MASK 0xf -#define STATUS_CODE_OK 0 -#define STATUS_CODE_BUSY 1 -#define STATUS_CODE_RESERVED 2 -#define STATUS_CODE_UNSUPPORTED 3 -#define STATUS_CODE_ACCESS_DENIED 4 -#define STATUS_CODE_OVERUNDERFLOW 5 -#define STATUS_CODE_BADSIZE 6 -#define STATUS_CODE_UNKNOWN_ERROR 7 -#define STATUS_FULLY_DISCHARGED BIT(4) -#define STATUS_FULLY_CHARGED BIT(5) -#define STATUS_DISCHARGING BIT(6) -#define STATUS_INITIALIZED BIT(7) -#define STATUS_REMAINING_TIME_ALARM BIT(8) +#define STATUS_ERR_CODE_MASK 0xf +#define STATUS_CODE_OK 0 +#define STATUS_CODE_BUSY 1 +#define STATUS_CODE_RESERVED 2 +#define STATUS_CODE_UNSUPPORTED 3 +#define STATUS_CODE_ACCESS_DENIED 4 +#define STATUS_CODE_OVERUNDERFLOW 5 +#define STATUS_CODE_BADSIZE 6 +#define STATUS_CODE_UNKNOWN_ERROR 7 +#define STATUS_FULLY_DISCHARGED BIT(4) +#define STATUS_FULLY_CHARGED BIT(5) +#define STATUS_DISCHARGING BIT(6) +#define STATUS_INITIALIZED BIT(7) +#define STATUS_REMAINING_TIME_ALARM BIT(8) #define STATUS_REMAINING_CAPACITY_ALARM BIT(9) #define STATUS_TERMINATE_DISCHARGE_ALARM BIT(11) -#define STATUS_OVERTEMP_ALARM BIT(12) -#define STATUS_TERMINATE_CHARGE_ALARM BIT(14) -#define STATUS_OVERCHARGED_ALARM BIT(15) +#define STATUS_OVERTEMP_ALARM BIT(12) +#define STATUS_TERMINATE_CHARGE_ALARM BIT(14) +#define STATUS_OVERCHARGED_ALARM BIT(15) /* Battery Spec Info */ -#define BATTERY_SPEC_REVISION_MASK 0x000F -#define BATTERY_SPEC_REVISION_SHIFT 0 -#define BATTERY_SPEC_VERSION_MASK 0x00F0 -#define BATTERY_SPEC_VERSION_SHIFT 4 -#define BATTERY_SPEC_VSCALE_MASK 0x0F00 -#define BATTERY_SPEC_VSCALE_SHIFT 8 -#define BATTERY_SPEC_IPSCALE_MASK 0xF000 -#define BATTERY_SPEC_IPSCALE_SHIFT 12 - -#define BATTERY_SPEC_VERSION(INFO) ((INFO & BATTERY_SPEC_VERSION_MASK) >> \ - BATTERY_SPEC_VERSION_SHIFT) +#define BATTERY_SPEC_REVISION_MASK 0x000F +#define BATTERY_SPEC_REVISION_SHIFT 0 +#define BATTERY_SPEC_VERSION_MASK 0x00F0 +#define BATTERY_SPEC_VERSION_SHIFT 4 +#define BATTERY_SPEC_VSCALE_MASK 0x0F00 +#define BATTERY_SPEC_VSCALE_SHIFT 8 +#define BATTERY_SPEC_IPSCALE_MASK 0xF000 +#define BATTERY_SPEC_IPSCALE_SHIFT 12 + +#define BATTERY_SPEC_VERSION(INFO) \ + ((INFO & BATTERY_SPEC_VERSION_MASK) >> BATTERY_SPEC_VERSION_SHIFT) /* Smart battery version info */ -#define BATTERY_SPEC_VER_1_0 1 -#define BATTERY_SPEC_VER_1_1 2 -#define BATTERY_SPEC_VER_1_1_WITH_PEC 3 +#define BATTERY_SPEC_VER_1_0 1 +#define BATTERY_SPEC_VER_1_1 2 +#define BATTERY_SPEC_VER_1_1_WITH_PEC 3 /* Smart battery revision info */ -#define BATTERY_SPEC_REVISION_1 1 +#define BATTERY_SPEC_REVISION_1 1 /* Charger alarm warning */ -#define ALARM_OVER_CHARGED 0x8000 -#define ALARM_TERMINATE_CHARGE 0x4000 -#define ALARM_RESERVED_2000 0x2000 -#define ALARM_OVER_TEMP 0x1000 -#define ALARM_TERMINATE_DISCHARGE 0x0800 -#define ALARM_RESERVED_0400 0x0400 -#define ALARM_REMAINING_CAPACITY 0x0200 -#define ALARM_REMAINING_TIME 0x0100 -#define ALARM_STATUS_INITIALIZE 0x0080 -#define ALARM_STATUS_DISCHARGING 0x0040 -#define ALARM_STATUS_FULLY_CHARGED 0x0020 -#define ALARM_STATUS_FULLY_DISCHARGED 0x0010 +#define ALARM_OVER_CHARGED 0x8000 +#define ALARM_TERMINATE_CHARGE 0x4000 +#define ALARM_RESERVED_2000 0x2000 +#define ALARM_OVER_TEMP 0x1000 +#define ALARM_TERMINATE_DISCHARGE 0x0800 +#define ALARM_RESERVED_0400 0x0400 +#define ALARM_REMAINING_CAPACITY 0x0200 +#define ALARM_REMAINING_TIME 0x0100 +#define ALARM_STATUS_INITIALIZE 0x0080 +#define ALARM_STATUS_DISCHARGING 0x0040 +#define ALARM_STATUS_FULLY_CHARGED 0x0020 +#define ALARM_STATUS_FULLY_DISCHARGED 0x0010 /* Charge mode */ -#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0) -#define CHARGE_FLAG_ENABLE_POLLING BIT(1) -#define CHARGE_FLAG_POR_RESET BIT(2) -#define CHARGE_FLAG_RESET_TO_ZERO BIT(3) +#define CHARGE_FLAG_INHIBIT_CHARGE BIT(0) +#define CHARGE_FLAG_ENABLE_POLLING BIT(1) +#define CHARGE_FLAG_POR_RESET BIT(2) +#define CHARGE_FLAG_RESET_TO_ZERO BIT(3) /* Charger status */ -#define CHARGER_CHARGE_INHIBITED BIT(0) -#define CHARGER_POLLING_ENABLED BIT(1) -#define CHARGER_VOLTAGE_NOTREG BIT(2) -#define CHARGER_CURRENT_NOTREG BIT(3) -#define CHARGER_LEVEL_2 BIT(4) -#define CHARGER_LEVEL_3 BIT(5) -#define CHARGER_CURRENT_OR BIT(6) -#define CHARGER_VOLTAGE_OR BIT(7) -#define CHARGER_RES_OR BIT(8) -#define CHARGER_RES_COLD BIT(9) -#define CHARGER_RES_HOT BIT(10) -#define CHARGER_RES_UR BIT(11) -#define CHARGER_ALARM_INHIBITED BIT(12) -#define CHARGER_POWER_FAIL BIT(13) -#define CHARGER_BATTERY_PRESENT BIT(14) -#define CHARGER_AC_PRESENT BIT(15) -#define CHARGER_BYPASS_MODE BIT(16) +#define CHARGER_CHARGE_INHIBITED BIT(0) +#define CHARGER_POLLING_ENABLED BIT(1) +#define CHARGER_VOLTAGE_NOTREG BIT(2) +#define CHARGER_CURRENT_NOTREG BIT(3) +#define CHARGER_LEVEL_2 BIT(4) +#define CHARGER_LEVEL_3 BIT(5) +#define CHARGER_CURRENT_OR BIT(6) +#define CHARGER_VOLTAGE_OR BIT(7) +#define CHARGER_RES_OR BIT(8) +#define CHARGER_RES_COLD BIT(9) +#define CHARGER_RES_HOT BIT(10) +#define CHARGER_RES_UR BIT(11) +#define CHARGER_ALARM_INHIBITED BIT(12) +#define CHARGER_POWER_FAIL BIT(13) +#define CHARGER_BATTERY_PRESENT BIT(14) +#define CHARGER_AC_PRESENT BIT(15) +#define CHARGER_BYPASS_MODE BIT(16) /* Charger specification info */ -#define INFO_CHARGER_SPEC(INFO) ((INFO) & 0xf) -#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) +#define INFO_CHARGER_SPEC(INFO) ((INFO)&0xf) +#define INFO_SELECTOR_SUPPORT(INFO) (((INFO) >> 4) & 1) /* Manufacturer Access parameters */ -#define PARAM_SAFETY_STATUS 0x51 -#define PARAM_OPERATION_STATUS 0x54 -#define PARAM_FIRMWARE_RUNTIME 0x62 +#define PARAM_SAFETY_STATUS 0x51 +#define PARAM_OPERATION_STATUS 0x54 +#define PARAM_FIRMWARE_RUNTIME 0x62 /* Operation status masks -- 6 byte reply */ /* reply[3] */ -#define BATTERY_DISCHARGING_DISABLED 0x20 -#define BATTERY_CHARGING_DISABLED 0x40 +#define BATTERY_DISCHARGING_DISABLED 0x20 +#define BATTERY_CHARGING_DISABLED 0x40 /* Battery manufacture date */ -#define MANUFACTURE_DATE_DAY_MASK 0x001F -#define MANUFACTURE_DATE_DAY_SHIFT 0 -#define MANUFACTURE_DATE_MONTH_MASK 0x01E0 -#define MANUFACTURE_DATE_MONTH_SHIFT 5 -#define MANUFACTURE_DATE_YEAR_MASK 0xFE00 -#define MANUFACTURE_DATE_YEAR_SHIFT 9 -#define MANUFACTURE_DATE_YEAR_OFFSET 1980 -#define MANUFACTURE_RUNTIME_SIZE 4 +#define MANUFACTURE_DATE_DAY_MASK 0x001F +#define MANUFACTURE_DATE_DAY_SHIFT 0 +#define MANUFACTURE_DATE_MONTH_MASK 0x01E0 +#define MANUFACTURE_DATE_MONTH_SHIFT 5 +#define MANUFACTURE_DATE_YEAR_MASK 0xFE00 +#define MANUFACTURE_DATE_YEAR_SHIFT 9 +#define MANUFACTURE_DATE_YEAR_OFFSET 1980 +#define MANUFACTURE_RUNTIME_SIZE 4 /* Read from battery */ int sb_read(int cmd, int *param); -- cgit v1.2.1 From b84a7aee32eb8d7628f1315f4bfd5e17bca5755a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:16 -0600 Subject: power/mt8192.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ie1b5443b0f9da5a6686e8cde7378edd5dcdefc26 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727065 Reviewed-by: Jeremy Bettis --- power/mt8192.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/power/mt8192.c b/power/mt8192.c index fcf1b197fe..c3d0ce3267 100644 --- a/power/mt8192.c +++ b/power/mt8192.c @@ -81,9 +81,9 @@ /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED"}, + { GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_AP_EC_WATCHDOG_L, POWER_SIGNAL_ACTIVE_LOW, "AP_WDT_ASSERTED" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -218,10 +218,10 @@ enum power_state power_chipset_init(void) return POWER_S0; } } else if ((reset_flags & EC_RESET_FLAG_AP_OFF) || - (reset_flags & EC_RESET_FLAG_AP_IDLE)) { + (reset_flags & EC_RESET_FLAG_AP_IDLE)) { exit_hard_off = 0; } else if ((reset_flags & EC_RESET_FLAG_HIBERNATE) && - gpio_get_level(GPIO_AC_PRESENT)) { + gpio_get_level(GPIO_AC_PRESENT)) { /* * If AC present, assume this is a wake-up by AC insert. * Boot EC only. @@ -516,16 +516,16 @@ static void power_button_changed(void) DECLARE_HOOK(HOOK_POWER_BUTTON_CHANGE, power_button_changed, HOOK_PRIO_DEFAULT); #ifdef CONFIG_POWER_TRACK_HOST_SLEEP_STATE -__overridable void power_chipset_handle_sleep_hang( - enum sleep_hang_type hang_type) +__overridable void +power_chipset_handle_sleep_hang(enum sleep_hang_type hang_type) { CPRINTS("Warning: Detected sleep hang! Waking host up!"); host_set_single_event(EC_HOST_EVENT_HANG_DETECT); } -__override void power_chipset_handle_host_sleep_event( - enum host_sleep_event state, - struct host_sleep_event_context *ctx) +__override void +power_chipset_handle_host_sleep_event(enum host_sleep_event state, + struct host_sleep_event_context *ctx) { CPRINTS("Handle sleep: %d", state); @@ -546,7 +546,6 @@ __override void power_chipset_handle_host_sleep_event( sleep_set_notify(SLEEP_NOTIFY_RESUME); task_wake(TASK_ID_CHIPSET); sleep_complete_resume(ctx); - } } #endif /* CONFIG_POWER_TRACK_HOST_SLEEP_STATE */ -- cgit v1.2.1 From 23ae48367161acd1e9f8a8c21881661e29fb2bff Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:46 -0600 Subject: zephyr/emul/tcpc/emul_tcpci.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Id9e097a5408ffed37baa93926219cb3e7ea94e64 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730703 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_tcpci.c | 150 +++++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/zephyr/emul/tcpc/emul_tcpci.c b/zephyr/emul/tcpc/emul_tcpci.c index 5f1ac5e502..4a728cd6a7 100644 --- a/zephyr/emul/tcpc/emul_tcpci.c +++ b/zephyr/emul/tcpc/emul_tcpci.c @@ -28,7 +28,6 @@ LOG_MODULE_REGISTER(tcpci_emul, CONFIG_TCPCI_EMUL_LOG_LEVEL); */ static int tcpci_emul_reg_bytes(int reg) { - switch (reg) { case TCPC_REG_VENDOR_ID: case TCPC_REG_PRODUCT_ID: @@ -392,7 +391,8 @@ int tcpci_emul_add_rx_msg(const struct emul *emul, if (ctx->rx_msg == NULL) { get_reg(ctx, TCPC_REG_DEV_CAP_2, &dev_cap_2); if ((!(dev_cap_2 & TCPC_REG_DEV_CAP_2_LONG_MSG) && - rx_msg->cnt > 31) || rx_msg->cnt > 265) { + rx_msg->cnt > 31) || + rx_msg->cnt > 265) { LOG_ERR("Too long first message (%d)", rx_msg->cnt); i2c_common_emul_unlock_data(&ctx->common.emul); return -EINVAL; @@ -454,12 +454,12 @@ void tcpci_emul_set_rev(const struct emul *emul, enum tcpci_emul_rev rev) case TCPCI_EMUL_REV1_0_VER1_0: tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV, (TCPC_REG_PD_INT_REV_REV_1_0 << 8) | - TCPC_REG_PD_INT_REV_VER_1_0); + TCPC_REG_PD_INT_REV_VER_1_0); return; case TCPCI_EMUL_REV2_0_VER1_1: tcpci_emul_set_reg(emul, TCPC_REG_PD_INT_REV, (TCPC_REG_PD_INT_REV_REV_2_0 << 8) | - TCPC_REG_PD_INT_REV_VER_1_1); + TCPC_REG_PD_INT_REV_VER_1_1); return; } } @@ -494,9 +494,9 @@ void tcpci_emul_set_partner_ops(const struct emul *emul, * * @return Voltage visible at CC resistor side */ -static enum tcpc_cc_voltage_status tcpci_emul_detected_volt_for_res( - enum tcpc_cc_pull res, - enum tcpc_cc_voltage_status volt) +static enum tcpc_cc_voltage_status +tcpci_emul_detected_volt_for_res(enum tcpc_cc_pull res, + enum tcpc_cc_voltage_status volt) { switch (res) { case TYPEC_CC_RD: @@ -569,8 +569,7 @@ int tcpci_emul_connect_partner(const struct emul *emul, /* If CC status is TYPEC_CC_VOLT_RP_*, then BIT(2) is ignored */ cc_status = TCPC_REG_CC_STATUS_SET( - partner_power_role == PD_ROLE_SOURCE ? 1 : 0, - cc2_v, cc1_v); + partner_power_role == PD_ROLE_SOURCE ? 1 : 0, cc2_v, cc1_v); set_reg(ctx, TCPC_REG_CC_STATUS, cc_status); get_reg(ctx, TCPC_REG_ALERT, &alert); set_reg(ctx, TCPC_REG_ALERT, alert | TCPC_REG_ALERT_CC_STATUS); @@ -675,67 +674,67 @@ void tcpci_emul_partner_msg_status(const struct emul *emul, /** Mask reserved bits in each register of TCPCI */ static const uint8_t tcpci_emul_rsvd_mask[] = { - [TCPC_REG_VENDOR_ID] = 0x00, - [TCPC_REG_VENDOR_ID + 1] = 0x00, - [TCPC_REG_PRODUCT_ID] = 0x00, - [TCPC_REG_PRODUCT_ID + 1] = 0x00, - [TCPC_REG_BCD_DEV] = 0x00, - [TCPC_REG_BCD_DEV + 1] = 0xff, - [TCPC_REG_TC_REV] = 0x00, - [TCPC_REG_TC_REV + 1] = 0x00, - [TCPC_REG_PD_REV] = 0x00, - [TCPC_REG_PD_REV + 1] = 0x00, - [TCPC_REG_PD_INT_REV] = 0x00, - [TCPC_REG_PD_INT_REV + 1] = 0x00, - [0x0c ... 0x0f] = 0xff, /* Reserved */ - [TCPC_REG_ALERT] = 0x00, - [TCPC_REG_ALERT + 1] = 0x00, - [TCPC_REG_ALERT_MASK] = 0x00, - [TCPC_REG_ALERT_MASK + 1] = 0x00, - [TCPC_REG_POWER_STATUS_MASK] = 0x00, - [TCPC_REG_FAULT_STATUS_MASK] = 0x00, - [TCPC_REG_EXT_STATUS_MASK] = 0xfe, - [TCPC_REG_ALERT_EXTENDED_MASK] = 0xf8, - [TCPC_REG_CONFIG_STD_OUTPUT] = 0x00, - [TCPC_REG_TCPC_CTRL] = 0x00, - [TCPC_REG_ROLE_CTRL] = 0x80, - [TCPC_REG_FAULT_CTRL] = 0x80, - [TCPC_REG_POWER_CTRL] = 0x00, - [TCPC_REG_CC_STATUS] = 0xc0, - [TCPC_REG_POWER_STATUS] = 0x00, - [TCPC_REG_FAULT_STATUS] = 0x00, - [TCPC_REG_EXT_STATUS] = 0xfe, - [TCPC_REG_ALERT_EXT] = 0xf8, - [0x22] = 0xff, /* Reserved */ - [TCPC_REG_COMMAND] = 0x00, - [TCPC_REG_DEV_CAP_1] = 0x00, - [TCPC_REG_DEV_CAP_1 + 1] = 0x00, - [TCPC_REG_DEV_CAP_2] = 0x80, - [TCPC_REG_DEV_CAP_2 + 1] = 0x00, - [TCPC_REG_STD_INPUT_CAP] = 0xe0, - [TCPC_REG_STD_OUTPUT_CAP] = 0x00, - [TCPC_REG_CONFIG_EXT_1] = 0xfc, - [0x2b] = 0xff, /* Reserved */ - [TCPC_REG_GENERIC_TIMER] = 0x00, - [TCPC_REG_GENERIC_TIMER + 1] = 0x00, - [TCPC_REG_MSG_HDR_INFO] = 0xe0, - [TCPC_REG_RX_DETECT] = 0x00, - [TCPC_REG_RX_BUFFER ... 0x4f] = 0x00, - [TCPC_REG_TRANSMIT ... 0x69] = 0x00, - [TCPC_REG_VBUS_VOLTAGE] = 0xf0, - [TCPC_REG_VBUS_VOLTAGE + 1] = 0x00, - [TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x00, - [TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0xfc, - [TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x00, - [TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0xfc, - [TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00, - [TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0xfc, - [TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00, - [TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0xfc, - [TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00, - [TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00, - [0x7c ... 0x7f] = 0xff, /* Reserved */ - [0x80 ... TCPCI_EMUL_REG_COUNT - 1] = 0x00, + [TCPC_REG_VENDOR_ID] = 0x00, + [TCPC_REG_VENDOR_ID + 1] = 0x00, + [TCPC_REG_PRODUCT_ID] = 0x00, + [TCPC_REG_PRODUCT_ID + 1] = 0x00, + [TCPC_REG_BCD_DEV] = 0x00, + [TCPC_REG_BCD_DEV + 1] = 0xff, + [TCPC_REG_TC_REV] = 0x00, + [TCPC_REG_TC_REV + 1] = 0x00, + [TCPC_REG_PD_REV] = 0x00, + [TCPC_REG_PD_REV + 1] = 0x00, + [TCPC_REG_PD_INT_REV] = 0x00, + [TCPC_REG_PD_INT_REV + 1] = 0x00, + [0x0c ... 0x0f] = 0xff, /* Reserved */ + [TCPC_REG_ALERT] = 0x00, + [TCPC_REG_ALERT + 1] = 0x00, + [TCPC_REG_ALERT_MASK] = 0x00, + [TCPC_REG_ALERT_MASK + 1] = 0x00, + [TCPC_REG_POWER_STATUS_MASK] = 0x00, + [TCPC_REG_FAULT_STATUS_MASK] = 0x00, + [TCPC_REG_EXT_STATUS_MASK] = 0xfe, + [TCPC_REG_ALERT_EXTENDED_MASK] = 0xf8, + [TCPC_REG_CONFIG_STD_OUTPUT] = 0x00, + [TCPC_REG_TCPC_CTRL] = 0x00, + [TCPC_REG_ROLE_CTRL] = 0x80, + [TCPC_REG_FAULT_CTRL] = 0x80, + [TCPC_REG_POWER_CTRL] = 0x00, + [TCPC_REG_CC_STATUS] = 0xc0, + [TCPC_REG_POWER_STATUS] = 0x00, + [TCPC_REG_FAULT_STATUS] = 0x00, + [TCPC_REG_EXT_STATUS] = 0xfe, + [TCPC_REG_ALERT_EXT] = 0xf8, + [0x22] = 0xff, /* Reserved */ + [TCPC_REG_COMMAND] = 0x00, + [TCPC_REG_DEV_CAP_1] = 0x00, + [TCPC_REG_DEV_CAP_1 + 1] = 0x00, + [TCPC_REG_DEV_CAP_2] = 0x80, + [TCPC_REG_DEV_CAP_2 + 1] = 0x00, + [TCPC_REG_STD_INPUT_CAP] = 0xe0, + [TCPC_REG_STD_OUTPUT_CAP] = 0x00, + [TCPC_REG_CONFIG_EXT_1] = 0xfc, + [0x2b] = 0xff, /* Reserved */ + [TCPC_REG_GENERIC_TIMER] = 0x00, + [TCPC_REG_GENERIC_TIMER + 1] = 0x00, + [TCPC_REG_MSG_HDR_INFO] = 0xe0, + [TCPC_REG_RX_DETECT] = 0x00, + [TCPC_REG_RX_BUFFER... 0x4f] = 0x00, + [TCPC_REG_TRANSMIT... 0x69] = 0x00, + [TCPC_REG_VBUS_VOLTAGE] = 0xf0, + [TCPC_REG_VBUS_VOLTAGE + 1] = 0x00, + [TCPC_REG_VBUS_SINK_DISCONNECT_THRESH] = 0x00, + [TCPC_REG_VBUS_SINK_DISCONNECT_THRESH + 1] = 0xfc, + [TCPC_REG_VBUS_STOP_DISCHARGE_THRESH] = 0x00, + [TCPC_REG_VBUS_STOP_DISCHARGE_THRESH + 1] = 0xfc, + [TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG] = 0x00, + [TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG + 1] = 0xfc, + [TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG] = 0x00, + [TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG + 1] = 0xfc, + [TCPC_REG_VBUS_NONDEFAULT_TARGET] = 0x00, + [TCPC_REG_VBUS_NONDEFAULT_TARGET + 1] = 0x00, + [0x7c ... 0x7f] = 0xff, /* Reserved */ + [0x80 ... TCPCI_EMUL_REG_COUNT - 1] = 0x00, }; /** @@ -1094,7 +1093,7 @@ int tcpci_emul_write_byte(const struct emul *emul, int reg, uint8_t val, if (bytes > 1) { LOG_ERR("Writing byte %d to 2 byte register 0x%x", - bytes, reg); + bytes, reg); tcpci_emul_set_i2c_interface_err(emul); return -EIO; } @@ -1143,8 +1142,9 @@ static int tcpci_emul_handle_command(const struct emul *emul) * Start DRP toggling only if auto discharge is disabled, * DRP is enabled and CC1/2 are both Rp or Rd */ - if (!(pwr_ctrl & TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT) - && TCPC_REG_ROLE_CTRL_DRP(role_ctrl) && + if (!(pwr_ctrl & + TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT) && + TCPC_REG_ROLE_CTRL_DRP(role_ctrl) && (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TCPC_REG_ROLE_CTRL_CC2(role_ctrl)) && (TCPC_REG_ROLE_CTRL_CC1(role_ctrl) == TYPEC_CC_RP || @@ -1361,8 +1361,8 @@ int tcpci_emul_handle_write(const struct emul *emul, int reg, int msg_len) /* Check if I2C write message has correct length */ if (msg_len != reg_bytes) { tcpci_emul_set_i2c_interface_err(emul); - LOG_ERR("Writing byte %d to %d byte register 0x%x", - msg_len, reg_bytes, reg); + LOG_ERR("Writing byte %d to %d byte register 0x%x", msg_len, + reg_bytes, reg); return -EIO; } -- cgit v1.2.1 From 1b59a8aee03896742a5acf1070ef33cb765bda91 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:05 -0600 Subject: common/usbc/dp_alt_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I8b2ed38ab7e084613ececa48c4f4f1ad9e790f9e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729781 Reviewed-by: Jeremy Bettis --- common/usbc/dp_alt_mode.c | 51 +++++++++++++++++++++-------------------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/common/usbc/dp_alt_mode.c b/common/usbc/dp_alt_mode.c index ac2b965b72..a5b4908112 100644 --- a/common/usbc/dp_alt_mode.c +++ b/common/usbc/dp_alt_mode.c @@ -20,8 +20,8 @@ #include "usb_pd_tcpm.h" #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -47,24 +47,20 @@ static enum dp_states dp_state[CONFIG_USB_PD_PORT_MAX_COUNT]; * Default of 0 indicates no command expected. */ static const uint8_t state_vdm_cmd[DP_STATE_COUNT] = { - [DP_START] = CMD_ENTER_MODE, - [DP_ENTER_ACKED] = CMD_DP_STATUS, - [DP_PREPARE_CONFIG] = CMD_DP_CONFIG, - [DP_PREPARE_EXIT] = CMD_EXIT_MODE, + [DP_START] = CMD_ENTER_MODE, [DP_ENTER_ACKED] = CMD_DP_STATUS, + [DP_PREPARE_CONFIG] = CMD_DP_CONFIG, [DP_PREPARE_EXIT] = CMD_EXIT_MODE, [DP_ENTER_RETRY] = CMD_ENTER_MODE, }; /* * Track if we're retrying due to an Enter Mode NAK */ -#define DP_FLAG_RETRY BIT(0) +#define DP_FLAG_RETRY BIT(0) static atomic_t dpm_dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT]; -#define DP_SET_FLAG(port, flag) \ - atomic_or(&dpm_dp_flags[port], (flag)) -#define DP_CLR_FLAG(port, flag) \ - atomic_clear_bits(&dpm_dp_flags[port], (flag)) +#define DP_SET_FLAG(port, flag) atomic_or(&dpm_dp_flags[port], (flag)) +#define DP_CLR_FLAG(port, flag) atomic_clear_bits(&dpm_dp_flags[port], (flag)) #define DP_CHK_FLAG(port, flag) (dpm_dp_flags[port] & (flag)) bool dp_is_active(int port) @@ -85,8 +81,7 @@ void dp_init(int port) bool dp_entry_is_done(int port) { - return dp_state[port] == DP_ACTIVE || - dp_state[port] == DP_INACTIVE; + return dp_state[port] == DP_ACTIVE || dp_state[port] == DP_INACTIVE; } static void dp_entry_failed(int port) @@ -96,8 +91,8 @@ static void dp_entry_failed(int port) dpm_dp_flags[port] = 0; } -static bool dp_response_valid(int port, enum tcpci_msg_type type, - char *cmdt, int vdm_cmd) +static bool dp_response_valid(int port, enum tcpci_msg_type type, char *cmdt, + int vdm_cmd) { enum dp_states st = dp_state[port]; @@ -108,7 +103,8 @@ static bool dp_response_valid(int port, enum tcpci_msg_type type, if (type != TCPCI_MSG_SOP || (st != DP_INACTIVE && state_vdm_cmd[st] != vdm_cmd)) { CPRINTS("C%d: Received unexpected DP VDM %s (cmd %d) from" - " %s in state %d", port, cmdt, vdm_cmd, + " %s in state %d", + port, cmdt, vdm_cmd, type == TCPCI_MSG_SOP ? "port partner" : "cable plug", st); dp_entry_failed(port); @@ -135,7 +131,7 @@ static void dp_exit_to_usb_mode(int port) } void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { const struct svdm_amode_data *modep = pd_get_amode_data(port, type, USB_SID_DISPLAYPORT); @@ -185,8 +181,8 @@ void dp_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, break; default: /* Invalid or unexpected negotiation state */ - CPRINTF("%s called with invalid state %d\n", - __func__, dp_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + dp_state[port]); dp_entry_failed(port); break; } @@ -221,8 +217,8 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) dp_exit_to_usb_mode(port); break; default: - CPRINTS("C%d: NAK for cmd %d in state %d", port, - vdm_cmd, dp_state[port]); + CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd, + dp_state[port]); dp_entry_failed(port); break; } @@ -231,8 +227,8 @@ void dp_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, uint32_t *vdm) { - const struct svdm_amode_data *modep = pd_get_amode_data(port, - TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); + const struct svdm_amode_data *modep = + pd_get_amode_data(port, TCPCI_MSG_SOP, USB_SID_DISPLAYPORT); int vdo_count_ret; if (*vdo_count < VDO_MAX_SIZE) @@ -243,7 +239,7 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, case DP_ENTER_RETRY: /* Enter the first supported mode for DisplayPort. */ vdm[0] = pd_dfp_enter_mode(port, TCPCI_MSG_SOP, - USB_SID_DISPLAYPORT, 0); + USB_SID_DISPLAYPORT, 0); if (vdm[0] == 0) return MSG_SETUP_ERROR; /* CMDT_INIT is 0, so this is a no-op */ @@ -316,8 +312,7 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, return MSG_SETUP_MUX_WAIT; case DP_PREPARE_EXIT: /* DPM should call setup only after safe state is set */ - vdm[0] = VDO(USB_SID_DISPLAYPORT, - 1, /* structured */ + vdm[0] = VDO(USB_SID_DISPLAYPORT, 1, /* structured */ CMD_EXIT_MODE); vdm[0] |= VDO_OPOS(modep->opos); @@ -331,8 +326,8 @@ enum dpm_msg_setup_status dp_setup_next_vdm(int port, int *vdo_count, */ return MSG_SETUP_ERROR; default: - CPRINTF("%s called with invalid state %d\n", - __func__, dp_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + dp_state[port]); return MSG_SETUP_ERROR; } -- cgit v1.2.1 From 8e8d1d878071f41b7ee2eb4a9d6bfb729879af0a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:38 -0600 Subject: board/osiris/keyboard.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ibde10f26f91d8077c4c2f524e51d06d7630d196f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728801 Reviewed-by: Jeremy Bettis --- board/osiris/keyboard.c | 95 ++++++++++++++++++++++--------------------------- 1 file changed, 42 insertions(+), 53 deletions(-) diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c index 2a6d25916c..2c8a32c24f 100644 --- a/board/osiris/keyboard.c +++ b/board/osiris/keyboard.c @@ -12,29 +12,28 @@ #include "rgb_keyboard.h" #include "timer.h" - -#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_KEYBOARD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_KEYBOARD, format, ##args) const struct key { uint8_t row; uint8_t col; } vivaldi_keys[] = { - {.row = 4, .col = 2}, /* T1 */ - {.row = 3, .col = 2}, /* T2 */ - {.row = 2, .col = 2}, /* T3 */ - {.row = 1, .col = 2}, /* T4 */ - {.row = 4, .col = 4}, /* T5 */ - {.row = 3, .col = 4}, /* T6 */ - {.row = 2, .col = 4}, /* T7 */ - {.row = 2, .col = 9}, /* T8 */ - {.row = 1, .col = 9}, /* T9 */ - {.row = 1, .col = 4}, /* T10 */ - {.row = 0, .col = 4}, /* T11 */ - {.row = 1, .col = 5}, /* T12 */ - {.row = 3, .col = 5}, /* T13 */ - {.row = 2, .col = 1}, /* T14 */ - {.row = 0, .col = 1}, /* T15 */ + { .row = 4, .col = 2 }, /* T1 */ + { .row = 3, .col = 2 }, /* T2 */ + { .row = 2, .col = 2 }, /* T3 */ + { .row = 1, .col = 2 }, /* T4 */ + { .row = 4, .col = 4 }, /* T5 */ + { .row = 3, .col = 4 }, /* T6 */ + { .row = 2, .col = 4 }, /* T7 */ + { .row = 2, .col = 9 }, /* T8 */ + { .row = 1, .col = 9 }, /* T9 */ + { .row = 1, .col = 4 }, /* T10 */ + { .row = 0, .col = 4 }, /* T11 */ + { .row = 1, .col = 5 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 2, .col = 1 }, /* T14 */ + { .row = 0, .col = 1 }, /* T15 */ }; BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); @@ -55,8 +54,8 @@ static const struct ec_response_keybd_config osiris_vivaldi_kb = { .capabilities = KEYBD_CAP_SCRNLOCK_KEY, }; -__override const struct ec_response_keybd_config -*board_vivaldi_keybd_config(void) +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) { return &osiris_vivaldi_kb; } @@ -81,23 +80,13 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { - DELM, - LED(0, 0), DELM, - LED(1, 0), DELM, - LED(2, 0), DELM, - LED(3, 0), DELM, - LED(4, 0), DELM, - LED(5, 0), DELM, - LED(6, 0), DELM, - LED(7, 0), DELM, - LED(8, 0), DELM, - LED(9, 0), DELM, - LED(10, 0), DELM, - LED(11, 0), DELM, - DELM, + DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0), + DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0), + DELM, LED(8, 0), DELM, LED(9, 0), DELM, LED(10, 0), DELM, LED(11, 0), + DELM, DELM, }; #undef LED #undef DELM @@ -121,28 +110,28 @@ __override struct keyboard_scan_config keyscan_config = { }; static uint16_t scancode_set2_rgb[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000}, - {0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016}, - {0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a}, - {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d}, - {0x0078, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d}, - {0x0051, 0x0007, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043}, - {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c}, - {0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059}, - {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d}, - {0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001A}, - {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, - {0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066}, - {0xe06b, 0xe074, 0xe069, 0x0067, 0xe0c6, 0x0064, 0x0015, 0xe07d}, - {0x0073, 0x0066, 0xe071, 0x005d, 0x005a, 0xe04a, 0x0070, 0x0021}, - {0x0023, 0xe05a, 0x0075, 0x0067, 0xe069, 0xe07a, 0x007d, 0x0069}, + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 }, + { 0x001f, 0x0076, 0x0017, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 }, + { 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d }, + { 0x0078, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d }, + { 0x0051, 0x0007, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c }, + { 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d }, + { 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001A }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, + { 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 }, + { 0xe06b, 0xe074, 0xe069, 0x0067, 0xe0c6, 0x0064, 0x0015, 0xe07d }, + { 0x0073, 0x0066, 0xe071, 0x005d, 0x005a, 0xe04a, 0x0070, 0x0021 }, + { 0x0023, 0xe05a, 0x0075, 0x0067, 0xe069, 0xe07a, 0x007d, 0x0069 }, }; static void keyboard_matrix_init(void) { CPRINTS("%s", __func__); - register_scancode_set2((uint16_t *) &scancode_set2_rgb, - sizeof(scancode_set2_rgb)); + register_scancode_set2((uint16_t *)&scancode_set2_rgb, + sizeof(scancode_set2_rgb)); } DECLARE_HOOK(HOOK_INIT, keyboard_matrix_init, HOOK_PRIO_PRE_DEFAULT); -- cgit v1.2.1 From b26974519bc372ae6b20f4ee40abb4f41e6cc31c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:46 -0600 Subject: board/kinox/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I71be2827b92312f4d1fffe178970fe7115b618c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728557 Reviewed-by: Jeremy Bettis --- board/kinox/pwm.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/board/kinox/pwm.c b/board/kinox/pwm.c index 90db5670f7..519ba751b1 100644 --- a/board/kinox/pwm.c +++ b/board/kinox/pwm.c @@ -11,22 +11,17 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_LED_GREEN] = { - .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP | - PWM_CONFIG_OPEN_DRAIN, - .freq = 2000 - }, - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, - [PWM_CH_LED_RED] = { - .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 2000 - }, + [PWM_CH_LED_GREEN] = { .channel = 0, + .flags = PWM_CONFIG_ACTIVE_LOW | + PWM_CONFIG_DSLEEP | + PWM_CONFIG_OPEN_DRAIN, + .freq = 2000 }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_LED_RED] = { .channel = 2, + .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, + .freq = 2000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From 793f84faac1eca8596b4a3dc8177fee7d3b11f64 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:46 -0600 Subject: board/agah/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I32de4f6fb91dc39675b5394cb6d9148f6e72530c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727095 Reviewed-by: Jeremy Bettis --- board/agah/board.h | 116 +++++++++++++++++++++++++---------------------------- 1 file changed, 54 insertions(+), 62 deletions(-) diff --git a/board/agah/board.h b/board/agah/board.h index 3b9aec23ec..28f9423b5f 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -50,7 +50,7 @@ #undef CONFIG_VOLUME_BUTTONS /* USB Type A Features */ -#define USB_PORT_COUNT 1 +#define USB_PORT_COUNT 1 #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ @@ -67,14 +67,14 @@ #define CONFIG_USBC_PPC_SYV682X #define CONFIG_USB_PD_FRS_PPC -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ -#define PD_VCONN_SWAP_DELAY 5000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 100000 -#define PD_MAX_CURRENT_MA 5000 -#define PD_MAX_VOLTAGE_MV 20000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 100000 +#define PD_MAX_CURRENT_MA 5000 +#define PD_MAX_VOLTAGE_MV 20000 /* * Macros for GPIO signals used in common code that don't match the @@ -82,55 +82,55 @@ * then redefined here to so it's more clear which signal is being used for * which purpose. */ -#define GPIO_AC_PRESENT GPIO_ACOK_OD -#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL -#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL -#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL -#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW -#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV -#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE -#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL -#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L -#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST -#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L -#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L -#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK +#define GPIO_AC_PRESENT GPIO_ACOK_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL +#define GPIO_EC_INT_L GPIO_EC_PCH_INT_ODL +#define GPIO_ENABLE_BACKLIGHT GPIO_EC_EN_EDP_BL +#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW +#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV +#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE +#define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +#define GPIO_TEMP_SENSOR_POWER GPIO_SEQ_EC_DSW_PWROK /* * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup * signal. */ -#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL -#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG -#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK -#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL -#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL -#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL -#define GPIO_WP_L GPIO_EC_WP_ODL +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_POWER_BUTTON_L GPIO_GSC_EC_PWR_BTN_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL +#define GPIO_WP_L GPIO_EC_WP_ODL /* System has back-lit keyboard */ #define CONFIG_PWM_KBLIGHT /* I2C Bus Configuration */ -#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C2_TCPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_PPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C2_PPC NPCX_I2C_PORT2_0 -#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT1_0 -#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 +#define I2C_PORT_USB_C0_BC12 NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C2_BC12 NPCX_I2C_PORT2_0 -#define I2C_PORT_USBA1_RT NPCX_I2C_PORT6_1 +#define I2C_PORT_USBA1_RT NPCX_I2C_PORT6_1 -#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 -#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 -#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 +#define I2C_PORT_BATTERY NPCX_I2C_PORT5_0 +#define I2C_PORT_CHARGER NPCX_I2C_PORT7_0 +#define I2C_PORT_EEPROM NPCX_I2C_PORT7_0 -#define I2C_ADDR_EEPROM_FLAGS 0x50 +#define I2C_ADDR_EEPROM_FLAGS 0x50 /* Thermal features */ #define CONFIG_THERMISTOR @@ -139,18 +139,18 @@ #define CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS 500 #define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B -#define CONFIG_FANS FAN_CH_COUNT +#define CONFIG_FANS FAN_CH_COUNT /* Charger defines */ #define CONFIG_CHARGER_ISL9241 -#define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Barrel jack adapter settings */ -#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT -#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 +#undef CONFIG_DEDICATED_CHARGE_PORT_COUNT +#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1 /* This is the next available port # after USB-C ports. */ -#define DEDICATED_CHARGE_PORT 2 +#define DEDICATED_CHARGE_PORT 2 /* * Older boards have a different ADC assignment. @@ -160,7 +160,7 @@ #ifndef __ASSEMBLER__ -#include "gpio_signal.h" /* needed by registers.h */ +#include "gpio_signal.h" /* needed by registers.h */ #include "registers.h" #include "usbc_config.h" @@ -187,25 +187,17 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_LED2 = 0, /* PWM0 (white charger) */ - PWM_CH_LED1, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ - PWM_CH_FAN, /* PWM5 */ - PWM_CH_FAN2, /* PWM4 */ + PWM_CH_LED2 = 0, /* PWM0 (white charger) */ + PWM_CH_LED1, /* PWM2 (orange charger) */ + PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_FAN, /* PWM5 */ + PWM_CH_FAN2, /* PWM4 */ PWM_CH_COUNT }; -enum fan_channel { - FAN_CH_0 = 0, - FAN_CH_1, - FAN_CH_COUNT -}; +enum fan_channel { FAN_CH_0 = 0, FAN_CH_1, FAN_CH_COUNT }; -enum mft_channel { - MFT_CH_0 = 0, - MFT_CH_1, - MFT_CH_COUNT -}; +enum mft_channel { MFT_CH_0 = 0, MFT_CH_1, MFT_CH_COUNT }; enum charge_port { CHARGE_PORT_TYPEC0, -- cgit v1.2.1 From 9a709c4cedeb3d644ef946c54cba7d1317d9b602 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:32 -0600 Subject: util/iteflash.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I2f7bf2754eb11b52dbe4c31ae3c6a495ecc14a60 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730647 Reviewed-by: Jeremy Bettis --- util/iteflash.c | 504 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 273 insertions(+), 231 deletions(-) diff --git a/util/iteflash.c b/util/iteflash.c index 8cf388069e..6cec35306b 100644 --- a/util/iteflash.c +++ b/util/iteflash.c @@ -38,65 +38,65 @@ #define CR50_USB_PID 0x5014 /* Cr50 exposed properties of the USB I2C endpoint. */ -#define CR50_I2C_SUBCLASS 82 -#define CR50_I2C_PROTOCOL 1 +#define CR50_I2C_SUBCLASS 82 +#define CR50_I2C_PROTOCOL 1 -#define CROS_CMD_ADDR 0x78 /* USB_I2C_CMD_ADDR 0xF0 >> 1 */ -#define CROS_CMD_ITE_SYNC 0 +#define CROS_CMD_ADDR 0x78 /* USB_I2C_CMD_ADDR 0xF0 >> 1 */ +#define CROS_CMD_ITE_SYNC 0 /* DBGR I2C addresses */ -#define I2C_CMD_ADDR 0x5A -#define I2C_DATA_ADDR 0x35 +#define I2C_CMD_ADDR 0x5A +#define I2C_DATA_ADDR 0x35 #define I2C_BLOCK_ADDR 0x79 #define FTDI_I2C_FREQ 400000 /* I2C pins on the FTDI interface */ -#define SCL_BIT BIT(0) -#define SDA_BIT BIT(1) +#define SCL_BIT BIT(0) +#define SDA_BIT BIT(1) /* Chip ID register value */ #define CHIP_ID 0x8380 /* Embedded flash page size */ -#define PAGE_SIZE (1<<8) +#define PAGE_SIZE (1 << 8) /* Embedded flash block write size for different programming modes. */ -#define FTDI_BLOCK_WRITE_SIZE (1<<16) +#define FTDI_BLOCK_WRITE_SIZE (1 << 16) /* JEDEC SPI Flash commands */ -#define SPI_CMD_PAGE_PROGRAM 0x02 -#define SPI_CMD_WRITE_DISABLE 0x04 -#define SPI_CMD_READ_STATUS 0x05 -#define SPI_CMD_WRITE_ENABLE 0x06 -#define SPI_CMD_FAST_READ 0x0B -#define SPI_CMD_CHIP_ERASE 0x60 -#define SPI_CMD_SECTOR_ERASE_1K 0xD7 -#define SPI_CMD_SECTOR_ERASE_4K 0x20 -#define SPI_CMD_WORD_PROGRAM 0xAD -#define SPI_CMD_EWSR 0x50 /* Enable Write Status Register */ -#define SPI_CMD_WRSR 0x01 /* Write Status Register */ -#define SPI_CMD_RDID 0x9F /* Read Flash ID */ +#define SPI_CMD_PAGE_PROGRAM 0x02 +#define SPI_CMD_WRITE_DISABLE 0x04 +#define SPI_CMD_READ_STATUS 0x05 +#define SPI_CMD_WRITE_ENABLE 0x06 +#define SPI_CMD_FAST_READ 0x0B +#define SPI_CMD_CHIP_ERASE 0x60 +#define SPI_CMD_SECTOR_ERASE_1K 0xD7 +#define SPI_CMD_SECTOR_ERASE_4K 0x20 +#define SPI_CMD_WORD_PROGRAM 0xAD +#define SPI_CMD_EWSR 0x50 /* Enable Write Status Register */ +#define SPI_CMD_WRSR 0x01 /* Write Status Register */ +#define SPI_CMD_RDID 0x9F /* Read Flash ID */ /* Size for FTDI outgoing buffer */ -#define FTDI_CMD_BUF_SIZE (1<<12) +#define FTDI_CMD_BUF_SIZE (1 << 12) /* Reset Status */ -#define RSTS_VCCDO_PW_ON 0x40 -#define RSTS_VFSPIPG 0x20 -#define RSTS_HGRST 0x08 -#define RSTS_GRST 0x04 +#define RSTS_VCCDO_PW_ON 0x40 +#define RSTS_VFSPIPG 0x20 +#define RSTS_HGRST 0x08 +#define RSTS_GRST 0x04 /* I2C MUX Configuration: TCA9543 or PCA9546 */ -#define I2C_MUX_CMD_ADDR 0x70 -#define I2C_MUX_CMD_NONE 0x00 -#define I2C_MUX_CMD_INAS 0x01 -#define I2C_MUX_CMD_EC 0x02 +#define I2C_MUX_CMD_ADDR 0x70 +#define I2C_MUX_CMD_NONE 0x00 +#define I2C_MUX_CMD_INAS 0x01 +#define I2C_MUX_CMD_EC 0x02 /* Eflash Type*/ -#define EFLASH_TYPE_8315 0x01 -#define EFLASH_TYPE_KGD 0x02 -#define EFLASH_TYPE_NONE 0xFF +#define EFLASH_TYPE_8315 0x01 +#define EFLASH_TYPE_KGD 0x02 +#define EFLASH_TYPE_NONE 0xFF uint8_t eflash_type; uint8_t spi_cmd_sector_erase; @@ -104,7 +104,6 @@ uint8_t spi_cmd_sector_erase; /* Embedded flash number of pages in a sector erase */ uint8_t sector_erase_pages; - static volatile sig_atomic_t exit_requested; struct i2c_interface; @@ -113,17 +112,17 @@ struct i2c_interface; struct iteflash_config { char *input_filename; char *output_filename; - int send_waveform; /* boolean */ - int erase; /* boolean */ + int send_waveform; /* boolean */ + int erase; /* boolean */ int i2c_mux; /* boolean */ - int debug; /* boolean */ - int disable_watchdog; /* boolean */ - int disable_protect_path; /* boolean */ + int debug; /* boolean */ + int disable_watchdog; /* boolean */ + int disable_protect_path; /* boolean */ int block_write_size; int usb_interface; int usb_vid; int usb_pid; - int verify; /* boolean */ + int verify; /* boolean */ char *usb_serial; char *i2c_dev_path; const struct i2c_interface *i2c_if; @@ -134,8 +133,8 @@ struct iteflash_config { struct common_hnd { struct iteflash_config conf; int flash_size; - int flash_cmd_v2; /* boolean */ - int dbgr_addr_3bytes; /* boolean */ + int flash_cmd_v2; /* boolean */ + int dbgr_addr_3bytes; /* boolean */ union { int i2c_dev_fd; struct usb_endpoint uep; @@ -162,13 +161,13 @@ struct i2c_interface { int (*send_special_waveform)(struct common_hnd *chnd); /* Required, must not be NULL. */ int (*byte_transfer)(struct common_hnd *chnd, uint8_t addr, - uint8_t *data, int write, int numbytes); + uint8_t *data, int write, int numbytes); /* Required, must be positive. */ int default_block_write_size; }; -static int spi_flash_command_short(struct common_hnd *chnd, - uint8_t cmd, char *desc); +static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd, + char *desc); static void null_and_free(void **ptr) { @@ -192,7 +191,7 @@ static void config_release(struct iteflash_config *conf) } /* number of bytes to send consecutively before checking for ACKs */ -#define FTDI_TX_BUFFER_LIMIT 32 +#define FTDI_TX_BUFFER_LIMIT 32 static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, uint8_t *data, int write, int numbytes) @@ -202,7 +201,7 @@ static inline int i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, return -1; return chnd->conf.i2c_if->byte_transfer(chnd, addr, data, write, - numbytes); + numbytes); } static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, @@ -225,8 +224,10 @@ static int linux_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, ret = ioctl(chnd->i2c_dev_fd, I2C_RDWR, &msgset); if (ret < 0) { extra_int = errno; - fprintf(stderr, "%s: ioctl() failed with return value %d and " - "errno %d\n", __func__, ret, extra_int); + fprintf(stderr, + "%s: ioctl() failed with return value %d and " + "errno %d\n", + __func__, ret, extra_int); if (ret == -1 && extra_int) ret = -abs(extra_int); } else if (ret < nmsgs) { @@ -250,12 +251,17 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf, for (i = 0; i < tcnt; i++) { /* WORKAROUND: force SDA before sending the next byte */ - *b++ = SET_BITS_LOW; *b++ = SDA_BIT; *b++ = SCL_BIT | SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = SDA_BIT; + *b++ = SCL_BIT | SDA_BIT; /* write byte */ *b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG; - *b++ = 0x07; *b++ = *tbuf++; + *b++ = 0x07; + *b++ = *tbuf++; /* prepare for ACK */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT; /* read ACK */ *b++ = MPSSE_DO_READ | MPSSE_BITMODE | MPSSE_LSB; *b++ = 0; @@ -267,7 +273,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf, * On the last byte, or every FTDI_TX_BUFFER_LIMIT bytes, read * the ACK bits. */ - if (i == tcnt-1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) { + if (i == tcnt - 1 || (tx_buffered == FTDI_TX_BUFFER_LIMIT)) { /* write data */ ret = ftdi_write_data(ftdi, buf, b - buf); if (ret < 0) { @@ -280,7 +286,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf, ack_idx = 0; do { ret = ftdi_read_data(ftdi, &ack[ack_idx], - remaining_data); + remaining_data); if (ret < 0) { fprintf(stderr, "read ACK failed\n"); return ret; @@ -299,7 +305,7 @@ static int i2c_add_send_byte(struct ftdi_context *ftdi, uint8_t *buf, fprintf(stderr, "write ACK fail: %d, 0x%02x\n", ret, failed_ack); - return -ENXIO; + return -ENXIO; } /* reset for next set of transactions */ @@ -318,20 +324,32 @@ static int i2c_add_recv_bytes(struct ftdi_context *ftdi, uint8_t *buf, for (i = 0; i < rcnt; i++) { /* set SCL low */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT; /* read the byte on the wire */ - *b++ = MPSSE_DO_READ; *b++ = 0; *b++ = 0; + *b++ = MPSSE_DO_READ; + *b++ = 0; + *b++ = 0; if (i == rcnt - 1) { /* NACK last byte */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT; *b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG; - *b++ = 0; *b++ = 0xff; *b++ = SEND_IMMEDIATE; + *b++ = 0; + *b++ = 0xff; + *b++ = SEND_IMMEDIATE; } else { /* ACK all other bytes */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT | SDA_BIT; *b++ = MPSSE_DO_WRITE | MPSSE_BITMODE | MPSSE_WRITE_NEG; - *b++ = 0; *b++ = 0; *b++ = SEND_IMMEDIATE; + *b++ = 0; + *b++ = 0; + *b++ = SEND_IMMEDIATE; } } @@ -401,7 +419,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, write ? sizeof(usb_buffer) : USB_I2C_HEADER_SIZE + extra, usb_buffer, sizeof(usb_buffer), 1, &response_size); - if (response_size < (USB_I2C_HEADER_SIZE + (write ? 0 : numbytes))) { + if (response_size < (USB_I2C_HEADER_SIZE + (write ? 0 : numbytes))) { fprintf(stderr, "%s: got too few bytes (%zd) in response\n", __func__, response_size); return -1; @@ -417,8 +435,7 @@ static int ccd_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, rv = usb_buffer[1]; rv = (rv << 8) + usb_buffer[0]; - fprintf(stderr, "%s: usb i2c error %d\n", - __func__, + fprintf(stderr, "%s: usb i2c error %d\n", __func__, (((uint16_t)usb_buffer[1]) << 8) + usb_buffer[0]); return -rv; @@ -445,14 +462,26 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, /* START condition */ /* SCL & SDA high */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0; - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = 0; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = 0; /* SCL high, SDA low */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT; - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SDA_BIT; /* SCL low, SDA low */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT; - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SCL_BIT | SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT | SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SCL_BIT | SDA_BIT; /* send address */ slave_addr = (addr << 1) | (write ? 0 : 1); @@ -467,7 +496,7 @@ static int ftdi_i2c_byte_transfer(struct common_hnd *chnd, uint8_t addr, b = buf; if (write) /* write data */ ret = i2c_add_send_byte(ftdi, buf, b, data, numbytes, - chnd->conf.debug); + chnd->conf.debug); else /* read data */ ret = i2c_add_recv_bytes(ftdi, buf, b, data, numbytes); @@ -475,11 +504,19 @@ exit_xfer: b = buf; /* STOP condition */ /* SCL high, SDA low */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT; - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SDA_BIT; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = SDA_BIT; /* SCL high, SDA high */ - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0; - *b++ = SET_BITS_LOW; *b++ = 0; *b++ = 0; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = 0; + *b++ = SET_BITS_LOW; + *b++ = 0; + *b++ = 0; rets = ftdi_write_data(ftdi, buf, b - buf); if (rets < 0) @@ -549,21 +586,16 @@ static int check_flashid(struct common_hnd *chnd) { int ret = 0; uint8_t id[16], i; - struct cmds commands[] = { - {0x07, 0x7f}, - {0x06, 0xff}, - {0x04, 0x00}, - {0x05, 0xfe}, - {0x08, 0x00}, - {0x05, 0xfd}, - {0x08, 0x9f} - }; + struct cmds commands[] = { { 0x07, 0x7f }, { 0x06, 0xff }, + { 0x04, 0x00 }, { 0x05, 0xfe }, + { 0x08, 0x00 }, { 0x05, 0xfd }, + { 0x08, 0x9f } }; for (i = 0; i < ARRAY_SIZE(commands); i++) { ret = i2c_write_byte(chnd, commands[i].addr, commands[i].cmd); if (ret) { fprintf(stderr, "Flash ID Failed : cmd %x ,data %x\n", - commands[i].addr, commands[i].cmd); + commands[i].addr, commands[i].cmd); return ret; } } @@ -595,7 +627,7 @@ static int check_chipid(struct common_hnd *chnd) int ret; uint8_t ver = 0xff; uint32_t id = 0xffff; - uint16_t v2[7] = {128, 192, 256, 384, 512, 0, 1024}; + uint16_t v2[7] = { 128, 192, 256, 384, 512, 0, 1024 }; /* * Chip Version is mapping from bit 3-0 * Flash size is mapping from bit 7-4 @@ -637,7 +669,7 @@ static int check_chipid(struct common_hnd *chnd) if ((id & 0xff00) != (CHIP_ID & 0xff00)) { id |= 0xff0000; - ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id+2); + ret = get_3rd_chip_id_byte(chnd, (uint8_t *)&id + 2); if (ret < 0) return ret; @@ -657,7 +689,7 @@ static int check_chipid(struct common_hnd *chnd) } /* compute embedded flash size from CHIPVER field */ if (chnd->flash_cmd_v2) - chnd->flash_size = v2[(ver & 0xF0)>>5] * 1024; + chnd->flash_size = v2[(ver & 0xF0) >> 5] * 1024; else chnd->flash_size = (128 + (ver & 0xF0)) * 1024; @@ -667,7 +699,7 @@ static int check_chipid(struct common_hnd *chnd) } printf("CHIPID %05x, CHIPVER %02x, Flash size %d kB\n", id, ver, - chnd->flash_size / 1024); + chnd->flash_size / 1024); return 0; } @@ -739,7 +771,7 @@ static int dbgr_disable_protect_path(struct common_hnd *chnd) ret |= i2c_write_byte(chnd, 0x2f, 0x20); for (i = 0; i < 32; i++) { - ret |= i2c_write_byte(chnd, 0x2e, 0xa0+i); + ret |= i2c_write_byte(chnd, 0x2e, 0xa0 + i); ret |= i2c_write_byte(chnd, 0x30, 0); } @@ -778,8 +810,8 @@ static int spi_flash_follow_mode_exit(struct common_hnd *chnd, char *desc) ret = (ret ? -EIO : 0); if (ret < 0) - fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n", - desc, ret); + fprintf(stderr, "Flash %s exit follow mode FAILED (%d)\n", desc, + ret); return ret; } @@ -799,8 +831,8 @@ static int dbgr_stop_ec(struct common_hnd *chnd) } /* SPI Flash generic command, short version */ -static int spi_flash_command_short(struct common_hnd *chnd, - uint8_t cmd, char *desc) +static int spi_flash_command_short(struct common_hnd *chnd, uint8_t cmd, + char *desc) { int ret = 0; @@ -817,8 +849,8 @@ static int spi_flash_command_short(struct common_hnd *chnd, } /* SPI Flash set erase page */ -static int spi_flash_set_erase_page(struct common_hnd *chnd, - int page, char *desc) +static int spi_flash_set_erase_page(struct common_hnd *chnd, int page, + char *desc) { int ret = 0; @@ -840,7 +872,7 @@ static int spi_poll_busy(struct common_hnd *chnd, char *desc) int ret = -EIO; if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS, - "read status for busy bit") < 0) { + "read status for busy bit") < 0) { fprintf(stderr, "Flash %s wait busy cleared FAILED\n", desc); goto failed_read_status; } @@ -867,7 +899,7 @@ static int spi_check_write_enable(struct common_hnd *chnd, char *desc) int ret = -EIO; if (spi_flash_command_short(chnd, SPI_CMD_READ_STATUS, - "read status for write enable bit") < 0) { + "read status for write enable bit") < 0) { fprintf(stderr, "Flash %s wait WE FAILED\n", desc); goto failed_read_status; } @@ -893,12 +925,8 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi) int ret; static const uint16_t divisor = 60000000 / (2 * FTDI_I2C_FREQ * 3 / 2 /* 3-phase CLK */) - 1; - uint8_t clock_buf[] = { - EN_3_PHASE, - DIS_DIV_5, - TCK_DIVISOR, - divisor & 0xff, - divisor >> 8}; + uint8_t clock_buf[] = { EN_3_PHASE, DIS_DIV_5, TCK_DIVISOR, + divisor & 0xff, divisor >> 8 }; ret = ftdi_set_latency_timer(ftdi, 16 /* ms */); if (ret < 0) @@ -929,7 +957,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi) /* Special waveform definition */ #define SPECIAL_LEN_USEC 50000ULL /* us */ -#define SPECIAL_FREQ 400000ULL +#define SPECIAL_FREQ 400000ULL #define SPECIAL_PATTERN 0x0000020301010302ULL #define SPECIAL_PATTERN_SDA_L_SCL_L 0x0000000000000000ULL @@ -938,7 +966,7 @@ static int ftdi_config_i2c(struct ftdi_context *ftdi) #define SPECIAL_PATTERN_SDA_H_SCL_H 0x0303030303030303ULL #define TICK_COUNT 24 -#define MSEC 1000 +#define MSEC 1000 #define USEC 1000000 #define SPECIAL_BUFFER_SIZE \ @@ -953,8 +981,8 @@ static int connect_to_ccd_i2c_bridge(struct common_hnd *chnd) CR50_I2C_PROTOCOL, &chnd->uep); if (rv) { - fprintf(stderr, "%s: usb_findit returned error %d\n", - __func__, rv); + fprintf(stderr, "%s: usb_findit returned error %d\n", __func__, + rv); } return rv; @@ -964,13 +992,11 @@ static int ccd_trigger_special_waveform(struct common_hnd *chnd) { uint8_t response[20]; size_t rsize; - uint8_t req[] = { - 0, /* Port 0. Might be necessary to modify. */ - CROS_CMD_ADDR, /* Chrome OS dedicated address. */ - 1, /* Will send a single byte command. */ - 0, /* No need to read back anything. */ - CROS_CMD_ITE_SYNC - }; + uint8_t req[] = { 0, /* Port 0. Might be necessary to modify. */ + CROS_CMD_ADDR, /* Chrome OS dedicated address. */ + 1, /* Will send a single byte command. */ + 0, /* No need to read back anything. */ + CROS_CMD_ITE_SYNC }; usb_trx(&chnd->uep, req, sizeof(req), response, sizeof(response), 1, &rsize); @@ -997,7 +1023,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd) int i; uint64_t *wave; struct ftdi_context *ftdi = chnd->ftdi_hnd; - uint8_t release_lines[] = {SET_BITS_LOW, 0, 0}; + uint8_t release_lines[] = { SET_BITS_LOW, 0, 0 }; wave = malloc(SPECIAL_BUFFER_SIZE); if (!wave) { @@ -1036,7 +1062,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd) usleep(5000); /* program each special tick */ - for (i = 0; i < TICK_COUNT; ) { + for (i = 0; i < TICK_COUNT;) { wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L; wave[i++] = SPECIAL_PATTERN_SDA_H_SCL_L; wave[i++] = SPECIAL_PATTERN_SDA_L_SCL_L; @@ -1060,7 +1086,7 @@ static int ftdi_send_special_waveform(struct common_hnd *chnd) ftdi_config_i2c(ftdi); ftdi_write_data(ftdi, release_lines, sizeof(release_lines)); - free_and_return: +free_and_return: free(wave); return ret; } @@ -1072,7 +1098,8 @@ static int send_special_waveform(struct common_hnd *chnd) int iterations; if (!chnd->conf.i2c_if->send_special_waveform) { - fprintf(stderr, "This binary does not support sending the ITE " + fprintf(stderr, + "This binary does not support sending the ITE " "special waveform with the chosen I2C interface.\n"); return -1; } @@ -1098,7 +1125,7 @@ static int send_special_waveform(struct common_hnd *chnd) ret = -1; if (!(iterations % max_iterations)) fprintf(stderr, "!please reset EC if flashing" - " sequence is not starting!\n"); + " sequence is not starting!\n"); } } while (ret && (iterations++ < max_iterations)); @@ -1111,10 +1138,10 @@ static int send_special_waveform(struct common_hnd *chnd) } static int windex; -static const char wheel[] = {'|', '/', '-', '\\' }; +static const char wheel[] = { '|', '/', '-', '\\' }; static void draw_spinner(uint32_t remaining, uint32_t size) { - int percent = (size - remaining)*100/size; + int percent = (size - remaining) * 100 / size; fprintf(stderr, "\r%c%3d%%", wheel[windex++], percent); windex %= sizeof(wheel); } @@ -1129,8 +1156,8 @@ static int spi_send_cmd_fast_read(struct common_hnd *chnd, uint32_t addr) ret = spi_flash_command_short(chnd, SPI_CMD_FAST_READ, "fast read"); /* Send address */ ret |= i2c_write_byte(chnd, 0x08, ((addr >> 16) & 0xff)); /* addr_h */ - ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff)); /* addr_m */ - ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff)); /* addr_l */ + ret |= i2c_write_byte(chnd, 0x08, ((addr >> 8) & 0xff)); /* addr_m */ + ret |= i2c_write_byte(chnd, 0x08, (addr & 0xff)); /* addr_l */ /* fake byte */ ret |= i2c_write_byte(chnd, 0x08, 0x00); /* use i2c block read command */ @@ -1149,8 +1176,10 @@ static int command_read_pages(struct common_hnd *chnd, uint32_t address, int cnt; if (address & 0xFF) { - fprintf(stderr, "page read requested at non-page boundary: " - "0x%X\n", address); + fprintf(stderr, + "page read requested at non-page boundary: " + "0x%X\n", + address); return -EINVAL; } @@ -1216,8 +1245,8 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, goto failed_write; while (remaining) { - cnt = (remaining > block_write_size) ? - block_write_size : remaining; + cnt = (remaining > block_write_size) ? block_write_size : + remaining; addr_H = (address >> 16) & 0xFF; addr_M = (address >> 8) & 0xFF; addr_L = address & 0xFF; @@ -1226,7 +1255,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, /* Write enable */ if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE, - "write enable for AAI write") < 0) + "write enable for AAI write") < 0) goto failed_write; /* Check write enable bit */ @@ -1235,7 +1264,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, /* Setup write */ if (spi_flash_command_short(chnd, SPI_CMD_WORD_PROGRAM, - "AAI write") < 0) + "AAI write") < 0) goto failed_write; /* Set eflash page address */ @@ -1244,7 +1273,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, res |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_L, 1, 1); if (res < 0) { fprintf(stderr, "Flash write set page FAILED (%d)\n", - res); + res); goto failed_write; } @@ -1267,13 +1296,13 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, res |= i2c_write_byte(chnd, 0x10, 0x00); if (res < 0) { fprintf(stderr, "Flash end data write FAILED (%d)\n", - res); + res); goto failed_write; } /* Write disable */ if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable for AAI write") < 0) + "write disable for AAI write") < 0) goto failed_write; /* Wait until available */ @@ -1288,7 +1317,7 @@ static int command_write_pages(struct common_hnd *chnd, uint32_t address, res = size; failed_write: if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable exit AAI write") < 0) + "write disable exit AAI write") < 0) res = -EIO; if (spi_flash_follow_mode_exit(chnd, "AAI write") < 0) @@ -1308,13 +1337,13 @@ static int command_write_pages3(struct common_hnd *chnd, uint32_t address, /* SMB_SPI_Flash_Write_Enable */ if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE, - "SPI Command Write Enable") < 0) { + "SPI Command Write Enable") < 0) { ret = -EIO; goto failed_write; } if (spi_flash_command_short(chnd, SPI_CMD_PAGE_PROGRAM, - "SPI_CMD_PAGE_PROGRAM") < 0) { + "SPI_CMD_PAGE_PROGRAM") < 0) { ret = -EIO; goto failed_write; } @@ -1339,8 +1368,6 @@ failed_write: return ret; } - - static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off) { int res = -EIO; @@ -1361,7 +1388,7 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off) draw_spinner(remaining, len); if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE, - "write enable for erase") < 0) + "write enable for erase") < 0) goto failed_erase; if (spi_check_write_enable(chnd, "erase") < 0) @@ -1370,28 +1397,28 @@ static int command_erase(struct common_hnd *chnd, uint32_t len, uint32_t off) /* do chip erase */ if (remaining == chnd->flash_size) { if (spi_flash_command_short(chnd, SPI_CMD_CHIP_ERASE, - "chip erase") < 0) + "chip erase") < 0) goto failed_erase; goto wait_busy_cleared; } /* do sector erase */ if (spi_flash_command_short(chnd, spi_cmd_sector_erase, - "sector erase") < 0) + "sector erase") < 0) goto failed_erase; if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0) goto failed_erase; -wait_busy_cleared: + wait_busy_cleared: if (spi_poll_busy(chnd, "erase") < 0) goto failed_erase; if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable for erase") < 0) + "write disable for erase") < 0) goto failed_erase; - if (remaining == chnd->flash_size) { + if (remaining == chnd->flash_size) { remaining = 0; draw_spinner(remaining, len); } else { @@ -1406,7 +1433,7 @@ wait_busy_cleared: failed_erase: if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable exit erase") < 0) + "write disable exit erase") < 0) res = -EIO; if (spi_flash_follow_mode_exit(chnd, "erase") < 0) @@ -1421,8 +1448,8 @@ failed_erase: * reset issue while flash. * Add such function to prevent the reset issue. */ -static int command_erase2(struct common_hnd *chnd, uint32_t len, - uint32_t off, uint32_t reset) +static int command_erase2(struct common_hnd *chnd, uint32_t len, uint32_t off, + uint32_t reset) { int res = -EIO; int page = 0; @@ -1446,11 +1473,10 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len, goto failed_erase; while (remaining) { - draw_spinner(remaining, len); if (spi_flash_command_short(chnd, SPI_CMD_WRITE_ENABLE, - "write enable for erase") < 0) + "write enable for erase") < 0) goto failed_erase; if (spi_check_write_enable(chnd, "erase") < 0) @@ -1458,7 +1484,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len, /* do sector erase */ if (spi_flash_command_short(chnd, spi_cmd_sector_erase, - "sector erase") < 0) + "sector erase") < 0) goto failed_erase; if (spi_flash_set_erase_page(chnd, page, "sector erase") < 0) @@ -1468,7 +1494,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len, goto failed_erase; if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable for erase") < 0) + "write disable for erase") < 0) goto failed_erase; if (reset) { @@ -1479,7 +1505,6 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len, page += sector_erase_pages; remaining -= sector_erase_pages * PAGE_SIZE; draw_spinner(remaining, len); - } /* No error so far */ @@ -1488,7 +1513,7 @@ static int command_erase2(struct common_hnd *chnd, uint32_t len, failed_erase: if (spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "write disable exit erase") < 0) + "write disable exit erase") < 0) res = -EIO; if (spi_flash_follow_mode_exit(chnd, "erase") < 0) @@ -1582,8 +1607,10 @@ static int write_flash(struct common_hnd *chnd, const char *filename, } res = fread(buffer, 1, size, hnd); if (res <= 0) { - fprintf(stderr, "%s: Failed to read %d bytes from %s with " - "ferror() %d\n", __func__, size, filename, ferror(hnd)); + fprintf(stderr, + "%s: Failed to read %d bytes from %s with " + "ferror() %d\n", + __func__, size, filename, ferror(hnd)); free(buffer); fclose(hnd); return -EIO; @@ -1636,8 +1663,10 @@ static int write_flash2(struct common_hnd *chnd, const char *filename, } res = fread(buffer, 1, size, hnd); if (res <= 0) { - fprintf(stderr, "%s: Failed to read %d bytes from %s with " - "ferror() %d\n", __func__, size, filename, ferror(hnd)); + fprintf(stderr, + "%s: Failed to read %d bytes from %s with " + "ferror() %d\n", + __func__, size, filename, ferror(hnd)); fclose(hnd); free(buffer); return -EIO; @@ -1667,7 +1696,8 @@ __send_aai_cmd: ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &addr_l, 1, 1); /* Send first two bytes of buffe */ ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset], 1, 1); - ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset+1], 1, 1); + ret |= i2c_byte_transfer(chnd, I2C_DATA_ADDR, &buffer[offset + 1], 1, + 1); /* we had sent two bytes */ offset += 2; res -= 2; @@ -1689,8 +1719,8 @@ __send_aai_cmd: two_bytes_sent = 0; cnt -= 2; } - if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset], - 1, cnt) < 0) { + if (i2c_byte_transfer(chnd, I2C_BLOCK_ADDR, &buffer[offset], 1, + cnt) < 0) { ret = -EIO; goto failed_write; } @@ -1706,7 +1736,7 @@ __send_aai_cmd: i2c_write_byte(chnd, 0x10, 0x00); /* write disable command */ spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "SPI write disable"); + "SPI write disable"); goto __send_aai_cmd; } } @@ -1717,7 +1747,7 @@ failed_write: i2c_write_byte(chnd, 0x10, 0x00); /* write disable command */ spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "SPI write disable"); + "SPI write disable"); failed_enter_mode: /* exit follow mode */ spi_flash_follow_mode_exit(chnd, "AAI write"); @@ -1764,8 +1794,10 @@ static int write_flash3(struct common_hnd *chnd, const char *filename, } res = fread(buf, 1, size, hnd); if (res <= 0) { - fprintf(stderr, "%s: Failed to read %d bytes from %s with " - "ferror() %d\n", __func__, size, filename, ferror(hnd)); + fprintf(stderr, + "%s: Failed to read %d bytes from %s with " + "ferror() %d\n", + __func__, size, filename, ferror(hnd)); fclose(hnd); free(buf); return -EIO; @@ -1787,8 +1819,8 @@ static int write_flash3(struct common_hnd *chnd, const char *filename, cnt = (res > block_write_size) ? block_write_size : res; if (chnd->conf.erase && is_empty_page(&buf[offset], cnt)) { /* do nothing */ - } else if (command_write_pages3(chnd, offset, cnt, &buf[offset]) - < 0) { + } else if (command_write_pages3(chnd, offset, cnt, + &buf[offset]) < 0) { ret = -EIO; goto failed_write; } @@ -1801,7 +1833,7 @@ static int write_flash3(struct common_hnd *chnd, const char *filename, failed_write: free(buf); spi_flash_command_short(chnd, SPI_CMD_WRITE_DISABLE, - "SPI write disable"); + "SPI write disable"); spi_flash_follow_mode_exit(chnd, "Page program"); if (ret < 0) fprintf(stderr, "%s: Error writing to flash\n", __func__); @@ -1811,8 +1843,6 @@ failed_write: return ret; } - - /* Return zero on success, a non-zero value on failures. */ static int verify_flash(struct common_hnd *chnd, const char *filename, uint32_t offset) @@ -1820,7 +1850,7 @@ static int verify_flash(struct common_hnd *chnd, const char *filename, int res; int file_size; FILE *hnd; - uint8_t *buffer = malloc(chnd->flash_size); + uint8_t *buffer = malloc(chnd->flash_size); uint8_t *buffer2 = malloc(chnd->flash_size); if (!buffer || !buffer2) { @@ -1841,9 +1871,10 @@ static int verify_flash(struct common_hnd *chnd, const char *filename, file_size = fread(buffer, 1, chnd->flash_size, hnd); if (file_size <= 0) { - fprintf(stderr, "%s: Failed to read %d bytes from %s with " - "ferror() %d\n", __func__, chnd->flash_size, filename, - ferror(hnd)); + fprintf(stderr, + "%s: Failed to read %d bytes from %s with " + "ferror() %d\n", + __func__, chnd->flash_size, filename, ferror(hnd)); fclose(hnd); res = -EIO; goto exit; @@ -1863,8 +1894,8 @@ exit: return res; } -static struct ftdi_context *open_ftdi_device(int vid, int pid, - int interface, const char *serial) +static struct ftdi_context *open_ftdi_device(int vid, int pid, int interface, + const char *serial) { struct ftdi_context *ftdi; int ret; @@ -1904,17 +1935,19 @@ static int linux_i2c_interface_init(struct common_hnd *chnd) return -1; } printf("Attempting to open Linux i2c-dev path %s\n", - chnd->conf.i2c_dev_path); + chnd->conf.i2c_dev_path); chnd->i2c_dev_fd = open(chnd->conf.i2c_dev_path, O_RDWR); if (chnd->i2c_dev_fd < 0) { err = errno; perror("Failed to open Linux i2c-dev file path with error"); - fprintf(stderr, "Linux i2c-dev file path from --i2c_dev_path " - "is: %s\n", chnd->conf.i2c_dev_path); + fprintf(stderr, + "Linux i2c-dev file path from --i2c_dev_path " + "is: %s\n", + chnd->conf.i2c_dev_path); return err ? err : -1; } printf("Successfully opened Linux i2c-dev path %s\n", - chnd->conf.i2c_dev_path); + chnd->conf.i2c_dev_path); return 0; } @@ -1923,15 +1956,15 @@ static int linux_i2c_interface_shutdown(struct common_hnd *chnd) int err; printf("Attempting to close Linux i2c-dev file descriptor %d\n", - chnd->i2c_dev_fd); + chnd->i2c_dev_fd); if (close(chnd->i2c_dev_fd)) { err = errno; perror("Failed to close Linux i2c-dev file descriptor with " - "error"); + "error"); return err ? err : -1; } printf("Successfully closed Linux i2c-dev file descriptor %d\n", - chnd->i2c_dev_fd); + chnd->i2c_dev_fd); return 0; } @@ -1951,8 +1984,9 @@ static int ccd_i2c_interface_shutdown(struct common_hnd *chnd) static int ftdi_i2c_interface_init(struct common_hnd *chnd) { chnd->ftdi_hnd = open_ftdi_device(chnd->conf.usb_vid, - chnd->conf.usb_pid, chnd->conf.usb_interface, - chnd->conf.usb_serial); + chnd->conf.usb_pid, + chnd->conf.usb_interface, + chnd->conf.usb_serial); if (chnd->ftdi_hnd == NULL) return -1; return 0; @@ -2045,31 +2079,31 @@ static int strdup_with_errmsg(const char *source, char **dest, const char *name) return ret; } -static const struct option longopts[] = { - {"block-write-size", 1, 0, 'b'}, - {"debug", 0, 0, 'd'}, - {"erase", 0, 0, 'e'}, - {"help", 0, 0, 'h'}, - {"i2c-dev-path", 1, 0, 'D'}, - {"i2c-interface", 1, 0, 'c'}, - {"i2c-mux", 0, 0, 'm'}, - {"interface", 1, 0, 'i'}, - {"nodisable-protect-path", 0, 0, 'Z'}, - {"nodisable-watchdog", 0, 0, 'z'}, - {"noverify", 0, 0, 'n'}, - {"product", 1, 0, 'p'}, - {"range", 1, 0, 'R'}, - {"read", 1, 0, 'r'}, - {"send-waveform", 1, 0, 'W'}, - {"serial", 1, 0, 's'}, - {"vendor", 1, 0, 'v'}, - {"write", 1, 0, 'w'}, - {NULL, 0, 0, 0} -}; +static const struct option longopts[] = { { "block-write-size", 1, 0, 'b' }, + { "debug", 0, 0, 'd' }, + { "erase", 0, 0, 'e' }, + { "help", 0, 0, 'h' }, + { "i2c-dev-path", 1, 0, 'D' }, + { "i2c-interface", 1, 0, 'c' }, + { "i2c-mux", 0, 0, 'm' }, + { "interface", 1, 0, 'i' }, + { "nodisable-protect-path", 0, 0, + 'Z' }, + { "nodisable-watchdog", 0, 0, 'z' }, + { "noverify", 0, 0, 'n' }, + { "product", 1, 0, 'p' }, + { "range", 1, 0, 'R' }, + { "read", 1, 0, 'r' }, + { "send-waveform", 1, 0, 'W' }, + { "serial", 1, 0, 's' }, + { "vendor", 1, 0, 'v' }, + { "write", 1, 0, 'w' }, + { NULL, 0, 0, 0 } }; static void display_usage(const char *program) { - fprintf(stderr, "Usage: %s [-d] [-v ] [-p ] \\\n" + fprintf(stderr, + "Usage: %s [-d] [-v ] [-p ] \\\n" "\t[-c ] [-D /dev/i2c-] [-i <1|2>] [-S] \\\n" "\t[-s ] [-e] [-r ] [-W <0|1|false|true>] \\\n" "\t[-w ] [-R base[:size]] [-m] [-b ]\n", @@ -2083,14 +2117,16 @@ static void display_usage(const char *program) "\tonly applicable with --i2c-interface=linux\n"); fprintf(stderr, "-i, --interface <1> : FTDI interface: A=1, B=2," " ...\n"); - fprintf(stderr, "-m, --i2c-mux : Enable i2c-mux (to EC).\n" + fprintf(stderr, + "-m, --i2c-mux : Enable i2c-mux (to EC).\n" "\tSpecify this flag only if the board has an I2C MUX and\n" "\tyou are not using servod.\n"); fprintf(stderr, "-n, --noverify : Don't auto verify.\n"); fprintf(stderr, "-b, --block-write-size : Perform writes in\n" - "\tblocks of this many bytes.\n"); + "\tblocks of this many bytes.\n"); fprintf(stderr, "-p, --product <0x1234> : USB product ID\n"); - fprintf(stderr, "-R, --range base[:size] : Allow to read or write" + fprintf(stderr, + "-R, --range base[:size] : Allow to read or write" " just a slice\n" "\tof the file, starting at : bytes, or til\n" "\tthe end of the file if is not specified, expressed\n" @@ -2099,15 +2135,16 @@ static void display_usage(const char *program) " write it into .\n"); fprintf(stderr, "-s, --serial : USB serial string\n"); fprintf(stderr, "-v, --vendor <0x1234> : USB vendor ID\n"); - fprintf(stderr, "-W, --send-waveform <0|1|false|true> : Send the" + fprintf(stderr, + "-W, --send-waveform <0|1|false|true> : Send the" " special waveform.\n" "\tDefault is true. Set to false if ITE direct firmware\n" "\tupdate mode has already been enabled.\n"); fprintf(stderr, "-w, --write : Write to flash.\n"); fprintf(stderr, "-z, --nodisable-watchdog : Do *not* disable EC " - "watchdog.\n"); + "watchdog.\n"); fprintf(stderr, "-Z, --nodisable-protect-path : Do *not* disable EC " - "protect path.\n"); + "protect path.\n"); } /* @@ -2119,7 +2156,7 @@ static int parse_range_options(char *str, struct iteflash_config *conf) char *size; if (!str) { - fprintf(stderr, "missing range base address specification\n"); + fprintf(stderr, "missing range base address specification\n"); return -1; } @@ -2165,14 +2202,16 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf) } else if (!strcasecmp(optarg, "ftdi")) { conf->i2c_if = &ftdi_i2c_interface; } else { - fprintf(stderr, "Unexpected -c / " - "--i2c-interface value: %s\n", optarg); + fprintf(stderr, + "Unexpected -c / " + "--i2c-interface value: %s\n", + optarg); ret = -1; } break; case 'D': ret = strdup_with_errmsg(optarg, &conf->i2c_dev_path, - "-D / --i2c-dev-path"); + "-D / --i2c-dev-path"); break; case 'd': conf->debug = 1; @@ -2202,11 +2241,11 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf) break; case 'r': ret = strdup_with_errmsg(optarg, &conf->input_filename, - "-r / --read"); + "-r / --read"); break; case 's': ret = strdup_with_errmsg(optarg, &conf->usb_serial, - "-s / --serial"); + "-s / --serial"); break; case 'v': conf->usb_vid = strtol(optarg, NULL, 16); @@ -2222,13 +2261,15 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf) conf->send_waveform = 1; break; } - fprintf(stderr, "Unexpected -W / --special-waveform " - "value: %s\n", optarg); + fprintf(stderr, + "Unexpected -W / --special-waveform " + "value: %s\n", + optarg); ret = -1; break; case 'w': ret = strdup_with_errmsg(optarg, &conf->output_filename, - "-w / --write"); + "-w / --write"); break; case 'z': conf->disable_watchdog = 0; @@ -2247,8 +2288,8 @@ static int parse_parameters(int argc, char **argv, struct iteflash_config *conf) static void sighandler(int signum) { int status; - printf("\nCaught signal %d: %s\nExiting...\n", - signum, strsignal(signum)); + printf("\nCaught signal %d: %s\nExiting...\n", signum, + strsignal(signum)); wait(&status); exit_requested = status; } @@ -2318,7 +2359,8 @@ int main(int argc, char **argv) ret = check_chipid(&chnd); if (ret) { - fprintf(stderr, "Failed to get ITE chip ID. This " + fprintf(stderr, + "Failed to get ITE chip ID. This " "could be because the ITE direct firmware " "update (DFU) mode is not enabled.\n"); goto return_after_init; @@ -2370,12 +2412,12 @@ int main(int argc, char **argv) if (chnd.flash_cmd_v2) switch (eflash_type) { case EFLASH_TYPE_8315: - ret = write_flash2(&chnd, - chnd.conf.output_filename, 0); + ret = write_flash2( + &chnd, chnd.conf.output_filename, 0); break; case EFLASH_TYPE_KGD: - ret = write_flash3(&chnd, - chnd.conf.output_filename, 0); + ret = write_flash3( + &chnd, chnd.conf.output_filename, 0); break; default: printf("Invalid EFLASH TYPE!"); @@ -2396,7 +2438,7 @@ int main(int argc, char **argv) /* Normal exit */ ret = 0; - return_after_init: +return_after_init: /* * Exit DBGR mode. This ensures EC won't hold clock/data pins of I2C. * Avoid resetting EC here because flash_ec will after iteflash exits. @@ -2415,7 +2457,7 @@ int main(int argc, char **argv) ret = other_ret; } - return_after_parse: +return_after_parse: config_release(&chnd.conf); return ret; } -- cgit v1.2.1 From 7b173ca86cffe9033888bf9b9321b6cfd0db35b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:11 -0600 Subject: include/throttle_ap.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Idba6a25d6e02eda5b0069d10bb0e73d367ed535d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730422 Reviewed-by: Jeremy Bettis --- include/throttle_ap.h | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/include/throttle_ap.h b/include/throttle_ap.h index 20ce3ecf59..a5e1a91a96 100644 --- a/include/throttle_ap.h +++ b/include/throttle_ap.h @@ -20,8 +20,8 @@ enum throttle_level { * Types of throttling desired. These are independent. */ enum throttle_type { - THROTTLE_SOFT = 0, /* for example, host events */ - THROTTLE_HARD, /* for example, PROCHOT */ + THROTTLE_SOFT = 0, /* for example, host events */ + THROTTLE_HARD, /* for example, PROCHOT */ NUM_THROTTLE_TYPES }; @@ -58,12 +58,11 @@ struct prochot_cfg { * @param type Type of throttling desired * @param source Which task is requesting throttling */ -#if defined(CONFIG_THROTTLE_AP) || \ +#if defined(CONFIG_THROTTLE_AP) || \ defined(CONFIG_THROTTLE_AP_ON_BAT_DISCHG_CURRENT) || \ defined(CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE) -void throttle_ap(enum throttle_level level, - enum throttle_type type, +void throttle_ap(enum throttle_level level, enum throttle_type type, enum throttle_sources source); /** @@ -103,11 +102,11 @@ void throttle_ap_c10_input_interrupt(enum gpio_signal signal); static inline void throttle_ap(enum throttle_level level, enum throttle_type type, enum throttle_sources source) -{} +{ +} #endif -void throttle_gpu(enum throttle_level level, - enum throttle_type type, +void throttle_gpu(enum throttle_level level, enum throttle_type type, enum throttle_sources source); -#endif /* __CROS_EC_THROTTLE_AP_H */ +#endif /* __CROS_EC_THROTTLE_AP_H */ -- cgit v1.2.1 From 2b8e6c8a813f0e5314da1dd940f06078e9850b05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:02 -0600 Subject: board/kuldax/usbc_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I4ed878874550a2c11f6d86fd82730e46e5297d90 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728604 Reviewed-by: Jeremy Bettis --- board/kuldax/usbc_config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/kuldax/usbc_config.h b/board/kuldax/usbc_config.h index b294eb69c8..439d36e19a 100644 --- a/board/kuldax/usbc_config.h +++ b/board/kuldax/usbc_config.h @@ -8,11 +8,8 @@ #ifndef __CROS_EC_USBC_CONFIG_H #define __CROS_EC_USBC_CONFIG_H -#define CONFIG_USB_PD_PORT_MAX_COUNT 1 +#define CONFIG_USB_PD_PORT_MAX_COUNT 1 -enum usbc_port { - USBC_PORT_C0 = 0, - USBC_PORT_COUNT -}; +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_COUNT }; #endif /* __CROS_EC_USBC_CONFIG_H */ -- cgit v1.2.1 From 9dda866745dc265965a656cf79862016f1cb2870 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:24 -0600 Subject: driver/charger/sm5803.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I2987ecff1d3df11f7cb8655ce6a4404f82730d6d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729968 Reviewed-by: Jeremy Bettis --- driver/charger/sm5803.c | 257 ++++++++++++++++++++++-------------------------- 1 file changed, 116 insertions(+), 141 deletions(-) diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c index e65bb67e75..d90294b8c9 100644 --- a/driver/charger/sm5803.c +++ b/driver/charger/sm5803.c @@ -29,22 +29,22 @@ #endif /* Console output macros */ -#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ## args) -#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) #define UNKNOWN_DEV_ID -1 static int dev_id = UNKNOWN_DEV_ID; static const struct charger_info sm5803_charger_info = { - .name = CHARGER_NAME, - .voltage_max = CHARGE_V_MAX, - .voltage_min = CHARGE_V_MIN, + .name = CHARGER_NAME, + .voltage_max = CHARGE_V_MAX, + .voltage_min = CHARGE_V_MIN, .voltage_step = CHARGE_V_STEP, - .current_max = CHARGE_I_MAX, - .current_min = CHARGE_I_MIN, + .current_max = CHARGE_I_MAX, + .current_min = CHARGE_I_MIN, .current_step = CHARGE_I_STEP, - .input_current_max = INPUT_I_MAX, - .input_current_min = INPUT_I_MIN, + .input_current_max = INPUT_I_MAX, + .input_current_min = INPUT_I_MIN, .input_current_step = INPUT_I_STEP, }; @@ -77,9 +77,8 @@ static int attempt_bfet_enable; */ static bool fast_charge_disabled; - -#define CHARGING_FAILURE_MAX_COUNT 5 -#define CHARGING_FAILURE_INTERVAL MINUTE +#define CHARGING_FAILURE_MAX_COUNT 5 +#define CHARGING_FAILURE_INTERVAL MINUTE static int sm5803_is_sourcing_otg_power(int chgnum, int port); static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id); @@ -88,58 +87,51 @@ static enum ec_error_list sm5803_set_current(int chgnum, int current); static inline enum ec_error_list chg_read8(int chgnum, int offset, int *value) { return i2c_read8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list chg_write8(int chgnum, int offset, int value) { return i2c_write8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - offset, value); + chg_chips[chgnum].i2c_addr_flags, offset, value); } static inline enum ec_error_list meas_read8(int chgnum, int offset, int *value) { - return i2c_read8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_MEAS_FLAGS, + return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS, offset, value); } static inline enum ec_error_list meas_write8(int chgnum, int offset, int value) { - return i2c_write8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_MEAS_FLAGS, - offset, value); + return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MEAS_FLAGS, + offset, value); } static inline enum ec_error_list main_read8(int chgnum, int offset, int *value) { - return i2c_read8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_MAIN_FLAGS, + return i2c_read8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS, offset, value); } static inline enum ec_error_list main_write8(int chgnum, int offset, int value) { - return i2c_write8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_MAIN_FLAGS, - offset, value); + return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_MAIN_FLAGS, + offset, value); } static inline enum ec_error_list test_write8(int chgnum, int offset, int value) { - return i2c_write8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_TEST_FLAGS, - offset, value); + return i2c_write8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS, + offset, value); } -static inline enum ec_error_list test_update8(int chgnum, const int offset, - const uint8_t mask, - const enum mask_update_action action) +static inline enum ec_error_list +test_update8(int chgnum, const int offset, const uint8_t mask, + const enum mask_update_action action) { - return i2c_update8(chg_chips[chgnum].i2c_port, - SM5803_ADDR_TEST_FLAGS, offset, mask, action); + return i2c_update8(chg_chips[chgnum].i2c_port, SM5803_ADDR_TEST_FLAGS, + offset, mask, action); } /* @@ -166,7 +158,7 @@ static int sm5803_set_full_clock_speed(int chgnum) } if (val & SM5803_CLOCK_SEL_LOW) { rv = main_write8(chgnum, SM5803_REG_CLOCK_SEL, - val & ~SM5803_CLOCK_SEL_LOW); + val & ~SM5803_CLOCK_SEL_LOW); } out: @@ -177,8 +169,9 @@ out: return rv; } -static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask, - const enum mask_update_action action) +static enum ec_error_list +sm5803_flow1_update(int chgnum, const uint8_t mask, + const enum mask_update_action action) { int rv; @@ -186,8 +179,7 @@ static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask, mutex_lock(&flow1_access_lock[chgnum]); rv = i2c_update8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - SM5803_REG_FLOW1, + chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW1, mask, action); mutex_unlock(&flow1_access_lock[chgnum]); @@ -195,16 +187,16 @@ static enum ec_error_list sm5803_flow1_update(int chgnum, const uint8_t mask, return rv; } -static enum ec_error_list sm5803_flow2_update(int chgnum, const uint8_t mask, - const enum mask_update_action action) +static enum ec_error_list +sm5803_flow2_update(int chgnum, const uint8_t mask, + const enum mask_update_action action) { int rv; mutex_lock(&flow2_access_lock[chgnum]); rv = i2c_update8(chg_chips[chgnum].i2c_port, - chg_chips[chgnum].i2c_addr_flags, - SM5803_REG_FLOW2, + chg_chips[chgnum].i2c_addr_flags, SM5803_REG_FLOW2, mask, action); mutex_unlock(&flow2_access_lock[chgnum]); @@ -345,15 +337,16 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) */ if (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) { - rv = sm5803_flow2_update(chgnum, - SM5803_FLOW2_AUTO_ENABLED, - MASK_SET); + rv = sm5803_flow2_update( + chgnum, SM5803_FLOW2_AUTO_ENABLED, + MASK_SET); fast_charge_disabled = false; } else { - rv = sm5803_flow2_update(chgnum, - SM5803_FLOW2_AUTO_TRKL_EN | + rv = sm5803_flow2_update( + chgnum, + SM5803_FLOW2_AUTO_TRKL_EN | SM5803_FLOW2_AUTO_PRECHG_EN, - MASK_SET); + MASK_SET); fast_charge_disabled = true; } } else { @@ -380,9 +373,8 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK, MASK_SET); } else { if (chgnum == CHARGER_PRIMARY) - rv |= sm5803_flow2_update(chgnum, - SM5803_FLOW2_AUTO_ENABLED, - MASK_CLR); + rv |= sm5803_flow2_update( + chgnum, SM5803_FLOW2_AUTO_ENABLED, MASK_CLR); if (chgnum == CHARGER_SECONDARY) { rv |= sm5803_flow1_update(CHARGER_PRIMARY, @@ -396,7 +388,6 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) regval); } - /* Disable sink mode, unless currently sourcing out */ if (!sm5803_is_sourcing_otg_power(chgnum, chgnum)) rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_SINK, @@ -404,7 +395,6 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) } return rv; - } /* @@ -412,8 +402,8 @@ enum ec_error_list sm5803_vbus_sink_enable(int chgnum, int enable) * boot. This should prevent us from re-running inits after sysjumps. */ static bool chip_inited[CHARGER_NUM]; -#define SM5803_SYSJUMP_TAG 0x534D /* SM */ -#define SM5803_HOOK_VERSION 1 +#define SM5803_SYSJUMP_TAG 0x534D /* SM */ +#define SM5803_HOOK_VERSION 1 static void init_status_preserve(void) { @@ -427,10 +417,9 @@ static void init_status_retrieve(void) const uint8_t *tag_contents; int version, size; - tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG, - &version, &size); + tag_contents = system_get_jump_tag(SM5803_SYSJUMP_TAG, &version, &size); if (tag_contents && (version == SM5803_HOOK_VERSION) && - (size == sizeof(chip_inited))) + (size == sizeof(chip_inited))) /* Valid init status found, restore before charger chip init */ memcpy(&chip_inited, tag_contents, size); } @@ -548,7 +537,7 @@ static void sm5803_init(int chgnum) rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id); if (rv) { CPRINTS("%s %d: Failed to read platform during init", - CHARGER_NAME, chgnum); + CHARGER_NAME, chgnum); return; } platform_id &= SM5803_PLATFORM_ID; @@ -557,10 +546,10 @@ static void sm5803_init(int chgnum) /* 3S Battery inits */ /* set 13.3V VBAT_SNSP TH GPADC THRESHOLD*/ rv |= meas_write8(chgnum, 0x26, - SM5803_VBAT_SNSP_MAXTH_3S_LEVEL); + SM5803_VBAT_SNSP_MAXTH_3S_LEVEL); /* OV_VBAT HW second level (14.1V) */ rv |= chg_write8(chgnum, 0x21, - SM5803_VBAT_PWR_MINTH_3S_LEVEL); + SM5803_VBAT_PWR_MINTH_3S_LEVEL); rv |= main_write8(chgnum, 0x30, 0xC0); rv |= main_write8(chgnum, 0x80, 0x01); rv |= main_write8(chgnum, 0x1A, 0x08); @@ -606,11 +595,11 @@ static void sm5803_init(int chgnum) * threshold for interrupt generation. */ rv |= meas_write8(chgnum, 0x26, - SM5803_VBAT_SNSP_MAXTH_2S_LEVEL); + SM5803_VBAT_SNSP_MAXTH_2S_LEVEL); /* Set OV_VBAT HW second level threshold as 9.4V */ rv |= chg_write8(chgnum, 0x21, - SM5803_VBAT_PWR_MINTH_2S_LEVEL); + SM5803_VBAT_PWR_MINTH_2S_LEVEL); rv |= main_write8(chgnum, 0x30, 0xC0); rv |= main_write8(chgnum, 0x80, 0x01); @@ -676,12 +665,9 @@ static void sm5803_init(int chgnum) * Turn on GPADCs to default. Enable the IBAT_CHG ADC in order to * measure battery current and calculate system resistance. */ - reg = SM5803_GPADCC1_TINT_EN | - SM5803_GPADCC1_VSYS_EN | - SM5803_GPADCC1_VCHGPWR_EN | - SM5803_GPADCC1_VBUS_EN | - SM5803_GPADCC1_IBAT_CHG_EN | - SM5803_GPADCC1_IBAT_DIS_EN | + reg = SM5803_GPADCC1_TINT_EN | SM5803_GPADCC1_VSYS_EN | + SM5803_GPADCC1_VCHGPWR_EN | SM5803_GPADCC1_VBUS_EN | + SM5803_GPADCC1_IBAT_CHG_EN | SM5803_GPADCC1_IBAT_DIS_EN | SM5803_GPADCC1_VBATSNSP_EN; rv |= meas_write8(chgnum, SM5803_REG_GPADC_CONFIG1, reg); @@ -707,26 +693,26 @@ static void sm5803_init(int chgnum) rv |= chg_write8(chgnum, SM5803_REG_DPM_VL_SET_LSB, (reg & 0x7)); /* Set default input current */ - reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT) - & SM5803_CHG_ILIM_RAW; + reg = SM5803_CURRENT_TO_REG(CONFIG_CHARGER_INPUT_CURRENT) & + SM5803_CHG_ILIM_RAW; rv |= chg_write8(chgnum, SM5803_REG_CHG_ILIM, reg); /* Configure charger insertion interrupts */ rv |= main_write8(chgnum, SM5803_REG_INT1_EN, SM5803_INT1_CHG); /* Enable end of charge interrupts for logging */ - rv |= main_write8(chgnum, SM5803_REG_INT4_EN, SM5803_INT4_CHG_FAIL | - SM5803_INT4_CHG_DONE | - SM5803_INT4_OTG_FAIL); + rv |= main_write8(chgnum, SM5803_REG_INT4_EN, + SM5803_INT4_CHG_FAIL | SM5803_INT4_CHG_DONE | + SM5803_INT4_OTG_FAIL); /* Set TINT interrupts for higher threshold 360 K */ rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH, - SM5803_TINT_HIGH_LEVEL); + SM5803_TINT_HIGH_LEVEL); /* * Set TINT interrupts for lower threshold to 0 when not * throttled to prevent trigger interrupts continually */ rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH, - SM5803_TINT_MIN_LEVEL); + SM5803_TINT_MIN_LEVEL); /* * Configure VBAT_SNSP high interrupt to fire after thresholds are set. @@ -735,7 +721,6 @@ static void sm5803_init(int chgnum) reg |= SM5803_INT2_VBATSNSP; rv |= main_write8(chgnum, SM5803_REG_INT2_EN, reg); - /* Configure TINT interrupts to fire after thresholds are set */ rv |= main_write8(chgnum, SM5803_REG_INT2_EN, SM5803_INT2_TINT); @@ -792,7 +777,7 @@ static void sm5803_init(int chgnum) rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_MAX_TH, reg); reg = (6000 * 10) / 292; rv |= meas_write8(chgnum, SM5803_REG_BFET_PWR_HWSAFE_MAX_TH, - reg); + reg); rv |= main_read8(chgnum, SM5803_REG_INT3_EN, ®); reg |= SM5803_INT3_BFET_PWR_LIMIT | SM5803_INT3_BFET_PWR_HWSAFE_LIMIT; @@ -892,9 +877,8 @@ static void sm5803_disable_runtime_low_power_mode(void) CPRINTS("%s %d: Failed to set in disable runtime LPM", CHARGER_NAME, chgnum); } -DECLARE_HOOK(HOOK_USB_PD_CONNECT, - sm5803_disable_runtime_low_power_mode, - HOOK_PRIO_FIRST); +DECLARE_HOOK(HOOK_USB_PD_CONNECT, sm5803_disable_runtime_low_power_mode, + HOOK_PRIO_FIRST); static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable) { @@ -923,18 +907,15 @@ static enum ec_error_list sm5803_enable_linear_charge(int chgnum, bool enable) batt_info->precharge_current); /* Enable linear charge mode. */ - rv |= sm5803_flow1_update(chgnum, - SM5803_FLOW1_LINEAR_CHARGE_EN, - MASK_SET); + rv |= sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN, + MASK_SET); rv |= chg_read8(chgnum, SM5803_REG_FLOW3, ®val); regval |= BIT(6) | BIT(5) | BIT(4); rv |= chg_write8(chgnum, SM5803_REG_FLOW3, regval); } else { - rv = sm5803_flow1_update(chgnum, - SM5803_FLOW1_LINEAR_CHARGE_EN, + rv = sm5803_flow1_update(chgnum, SM5803_FLOW1_LINEAR_CHARGE_EN, MASK_CLR); - rv |= sm5803_flow2_update(chgnum, - SM5803_FLOW2_AUTO_ENABLED, + rv |= sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED, MASK_CLR); rv |= chg_read8(chgnum, SM5803_REG_FLOW3, ®val); regval &= ~(BIT(6) | BIT(5) | BIT(4) | @@ -983,9 +964,8 @@ static void sm5803_enable_runtime_low_power_mode(void) CPRINTS("%s %d: Failed to set in enable runtime LPM", CHARGER_NAME, chgnum); } -DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, - sm5803_enable_runtime_low_power_mode, - HOOK_PRIO_LAST); +DECLARE_HOOK(HOOK_USB_PD_DISCONNECT, sm5803_enable_runtime_low_power_mode, + HOOK_PRIO_LAST); void sm5803_disable_low_power_mode(int chgnum) { @@ -1044,7 +1024,6 @@ void sm5803_enable_low_power_mode(int chgnum) reg |= SM5803_PHOT1_VBUS_MON_EN; rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg); - if (rv) CPRINTS("%s %d: Failed to set in enable low power mode", CHARGER_NAME, chgnum); @@ -1065,8 +1044,8 @@ void sm5803_restart_charging(void) * Enough time has passed since our last failure, * restart the timing and count from now. */ - failure_tracker[act_chg].time.val = now.val + - CHARGING_FAILURE_INTERVAL; + failure_tracker[act_chg].time.val = + now.val + CHARGING_FAILURE_INTERVAL; failure_tracker[act_chg].count = 1; sm5803_vbus_sink_enable(act_chg, 1); @@ -1129,27 +1108,27 @@ void sm5803_handle_interrupt(int chgnum) if ((meas_reg <= SM5803_TINT_LOW_LEVEL) && throttled) { throttled = false; throttle_ap(THROTTLE_OFF, THROTTLE_HARD, - THROTTLE_SRC_THERMAL); + THROTTLE_SRC_THERMAL); /* * Set back higher threshold to 360 K and set lower * threshold to 0. */ rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH, - SM5803_TINT_MIN_LEVEL); + SM5803_TINT_MIN_LEVEL); rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH, - SM5803_TINT_HIGH_LEVEL); + SM5803_TINT_HIGH_LEVEL); } else if (meas_reg >= SM5803_TINT_HIGH_LEVEL) { throttled = true; throttle_ap(THROTTLE_ON, THROTTLE_HARD, - THROTTLE_SRC_THERMAL); + THROTTLE_SRC_THERMAL); /* * Set back lower threshold to 330 K and set higher * threshold to maximum. */ rv |= meas_write8(chgnum, SM5803_REG_TINT_HIGH_TH, - SM5803_TINT_MAX_LEVEL); + SM5803_TINT_MAX_LEVEL); rv |= meas_write8(chgnum, SM5803_REG_TINT_LOW_TH, - SM5803_TINT_LOW_LEVEL); + SM5803_TINT_LOW_LEVEL); } /* * If the interrupt came in and we're not currently throttling @@ -1165,25 +1144,23 @@ void sm5803_handle_interrupt(int chgnum) rv = main_read8(chgnum, SM5803_REG_PLATFORM, &platform_id); if (rv) { CPRINTS("%s %d: Failed to read platform in interrupt", - CHARGER_NAME, chgnum); + CHARGER_NAME, chgnum); return; } platform_id &= SM5803_PLATFORM_ID; act_chg = charge_manager_get_active_charge_port(); - rv = meas_read8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MEAS_MSB, - &meas_reg); + rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_MSB, + &meas_reg); if (rv) return; meas_volt = meas_reg << 2; - rv = meas_read8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MEAS_LSB, - &meas_reg); + rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MEAS_LSB, + &meas_reg); if (rv) return; meas_volt |= meas_reg & 0x03; - rv = meas_read8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MAX_TH, &meas_reg); + rv = meas_read8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH, + &meas_reg); if (rv) return; @@ -1192,8 +1169,7 @@ void sm5803_handle_interrupt(int chgnum) CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! - " "VBAT %d mV", CHARGER_NAME, CHARGER_PRIMARY, - meas_reg * 408/10, - meas_volt * 102/10); + meas_reg * 408 / 10, meas_volt * 102 / 10); } if (is_platform_id_3s(platform_id)) { @@ -1201,28 +1177,27 @@ void sm5803_handle_interrupt(int chgnum) CPRINTS("%s %d : VBAT_SNSP_HIGH_TH: %d mV ! " "- VBAT %d mV", CHARGER_NAME, CHARGER_PRIMARY, - meas_reg * 616/10, - meas_volt * 154/10); + meas_reg * 616 / 10, meas_volt * 154 / 10); } /* Set Vbat Threshold to Max value to re-arm the interrupt */ - rv = meas_write8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MAX_TH, 0xFF); + rv = meas_write8(CHARGER_PRIMARY, SM5803_REG_VBATSNSP_MAX_TH, + 0xFF); /* Disable battery charge */ rv |= sm5803_flow1_update(chgnum, CHARGER_MODE_DISABLED, - MASK_CLR); + MASK_CLR); if (is_platform_id_2s(platform_id)) { /* 2S battery: set VBAT_SENSP TH 9V */ rv |= meas_write8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MAX_TH, - SM5803_VBAT_SNSP_MAXTH_2S_LEVEL); + SM5803_REG_VBATSNSP_MAX_TH, + SM5803_VBAT_SNSP_MAXTH_2S_LEVEL); } if (is_platform_id_3s(platform_id)) { /* 3S battery: set VBAT_SENSP TH 13.3V */ rv |= meas_write8(CHARGER_PRIMARY, - SM5803_REG_VBATSNSP_MAX_TH, - SM5803_VBAT_SNSP_MAXTH_3S_LEVEL); + SM5803_REG_VBATSNSP_MAX_TH, + SM5803_VBAT_SNSP_MAXTH_3S_LEVEL); } active_restart_port = act_chg; @@ -1243,7 +1218,7 @@ void sm5803_handle_interrupt(int chgnum) act_chg = charge_manager_get_active_charge_port(); CPRINTS("%s BFET power limit reached! (%s)", CHARGER_NAME, (int_reg & SM5803_INT3_BFET_PWR_LIMIT) ? "warn" : - "FATAL"); + "FATAL"); CPRINTS("\tVbat: %dmV", bp.voltage); CPRINTS("\tIbat: %dmA", bp.current); charger_get_voltage(act_chg, &val); @@ -1280,7 +1255,7 @@ void sm5803_handle_interrupt(int chgnum) hook_call_deferred(&sm5803_restart_charging_data, 30 * SECOND); } else if ((status_reg & SM5803_STATUS_CHG_OV_VBAT) && - act_chg == CHARGER_PRIMARY) { + act_chg == CHARGER_PRIMARY) { active_restart_port = act_chg; hook_call_deferred(&sm5803_restart_charging_data, 1 * SECOND); @@ -1312,11 +1287,12 @@ void sm5803_handle_interrupt(int chgnum) * will detect us as sinking in this failure case. */ if (status_reg == 0) - rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE | - SM5803_FLOW1_DIRECTCHG_SRC_EN, - MASK_CLR); + rv = sm5803_flow1_update( + chgnum, + CHARGER_MODE_SOURCE | + SM5803_FLOW1_DIRECTCHG_SRC_EN, + MASK_CLR); } - } static void sm5803_irq_deferred(void) @@ -1347,7 +1323,6 @@ static enum ec_error_list sm5803_get_dev_id(int chgnum, int *id) *id = dev_id; return rv; - } static const struct charger_info *sm5803_get_info(int chgnum) @@ -1367,7 +1342,6 @@ static enum ec_error_list sm5803_get_status(int chgnum, int *status) if (rv) return rv; - if ((reg & SM5803_FLOW1_MODE) == CHARGER_MODE_DISABLED && !(reg & SM5803_FLOW1_LINEAR_CHARGE_EN)) *status |= CHARGER_CHARGE_INHIBITED; @@ -1500,8 +1474,7 @@ static enum ec_error_list sm5803_set_voltage(int chgnum, int voltage) /* Once battery is connected, set up fast charge enable */ if (fast_charge_disabled && chgnum == CHARGER_PRIMARY && battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) { - rv = sm5803_flow2_update(chgnum, - SM5803_FLOW2_AUTO_ENABLED, + rv = sm5803_flow2_update(chgnum, SM5803_FLOW2_AUTO_ENABLED, MASK_SET); fast_charge_disabled = false; } @@ -1549,7 +1522,7 @@ static enum ec_error_list sm5803_discharge_on_ac(int chgnum, int enable) } static enum ec_error_list sm5803_get_vbus_voltage(int chgnum, int port, - int *voltage) + int *voltage) { enum ec_error_list rv; int reg; @@ -1718,13 +1691,13 @@ static enum ec_error_list sm5803_set_otg_current_voltage(int chgnum, reg &= ~SM5803_DISCH_CONF5_CLS_LIMIT; reg |= MIN((output_current / SM5803_CLS_CURRENT_STEP), - SM5803_DISCH_CONF5_CLS_LIMIT); + SM5803_DISCH_CONF5_CLS_LIMIT); rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF5, reg); reg = SM5803_VOLTAGE_TO_REG(output_voltage); rv = chg_write8(chgnum, SM5803_REG_VPWR_MSB, (reg >> 3)); rv |= chg_write8(chgnum, SM5803_REG_DISCH_CONF2, - reg & SM5803_DISCH_CONF5_VPWR_LSB); + reg & SM5803_DISCH_CONF5_VPWR_LSB); return rv; } @@ -1765,7 +1738,7 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled) return rv; selected_current = (reg & SM5803_DISCH_CONF5_CLS_LIMIT) * - SM5803_CLS_CURRENT_STEP; + SM5803_CLS_CURRENT_STEP; sm5803_set_otg_current_voltage(chgnum, selected_current, 4800); /* @@ -1773,8 +1746,9 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled) * DIRECTCHG_SOURCE_EN - enable current loop * (for designs with no external Vbus FET) */ - rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE | - SM5803_FLOW1_DIRECTCHG_SRC_EN, + rv = sm5803_flow1_update(chgnum, + CHARGER_MODE_SOURCE | + SM5803_FLOW1_DIRECTCHG_SRC_EN, MASK_SET); usleep(4000); @@ -1810,9 +1784,11 @@ static enum ec_error_list sm5803_enable_otg_power(int chgnum, int enabled) return rv; if ((reg & SM5803_FLOW1_MODE) != CHARGER_MODE_SINK || status) - rv = sm5803_flow1_update(chgnum, CHARGER_MODE_SOURCE | - SM5803_FLOW1_DIRECTCHG_SRC_EN, - MASK_CLR); + rv = sm5803_flow1_update( + chgnum, + CHARGER_MODE_SOURCE | + SM5803_FLOW1_DIRECTCHG_SRC_EN, + MASK_CLR); } return rv; @@ -1839,7 +1815,6 @@ static enum ec_error_list sm5803_set_vsys_compensation(int chgnum, int current_ma, int voltage_mv) { - int rv; int regval; int r; -- cgit v1.2.1 From 8cf48c7ba73a059f333c522d7fcb906804f4f4dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:29 -0600 Subject: chip/stm32/registers-stm32g4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I6340e661eee7f7430a9ae6ca451e75e7a1a70401 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729531 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32g4.h | 1877 ++++++++++++++++++++-------------------- 1 file changed, 924 insertions(+), 953 deletions(-) diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h index 25c57c2540..20fc015d79 100644 --- a/chip/stm32/registers-stm32g4.h +++ b/chip/stm32/registers-stm32g4.h @@ -19,87 +19,87 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_ADC1 18 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 -#define STM32_IRQ_FDCAN_IT0 21 -#define STM32_IRQ_FDCAN_IT1 22 -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM15 24 -#define STM32_IRQ_TIM16 25 -#define STM32_IRQ_TIM17 26 -#define STM32_IRQ_TIM1_CC 27 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 -#define STM32_IRQ_TIM8_BREAK 43 -#define STM32_IRQ_TIM8_UP 44 -#define STM32_IRQ_TIM8_TRG_COM 45 -#define STM32_IRQ_TIM8_CC 46 -#define STM32_IRQ_LPTIM1 49 -#define STM32_IRQ_SPI3 51 -#define STM32_IRQ_USART4 52 -#define STM32_IRQ_TIM6_DAC 54 -#define STM32_IRQ_TIM7 55 -#define STM32_IRQ_DMA2_CHANNEL1 56 -#define STM32_IRQ_DMA2_CHANNEL2 57 -#define STM32_IRQ_DMA2_CHANNEL3 58 -#define STM32_IRQ_DMA2_CHANNEL4 59 -#define STM32_IRQ_DMA2_CHANNEL5 60 -#define STM32_IRQ_UCPD1 63 -#define STM32_IRQ_COMP_1_2_3 64 -#define STM32_IRQ_COMP_4 65 -#define STM32_IRQ_CRS 75 -#define STM32_IRQ_SAI1 76 -#define STM32_IRQ_FPU 81 -#define STM32_IRQ_RNG 90 -#define STM32_IRQ_LPUART 91 -#define STM32_IRQ_I2C3_EV 92 -#define STM32_IRQ_I2C3_ER 93 -#define STM32_IRQ_DMAMUX_OVR 94 -#define STM32_IRQ_DMA1_CHANNEL8 96 -#define STM32_IRQ_DMA2_CHANNEL6 97 -#define STM32_IRQ_DMA2_CHANNEL7 98 -#define STM32_IRQ_DMA2_CHANNEL8 99 -#define STM32_IRQ_CORDIC 100 -#define STM32_IRQ_FMAC 101 +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_ADC1 18 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 +#define STM32_IRQ_FDCAN_IT0 21 +#define STM32_IRQ_FDCAN_IT1 22 +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM15 24 +#define STM32_IRQ_TIM16 25 +#define STM32_IRQ_TIM17 26 +#define STM32_IRQ_TIM1_CC 27 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 +#define STM32_IRQ_TIM8_BREAK 43 +#define STM32_IRQ_TIM8_UP 44 +#define STM32_IRQ_TIM8_TRG_COM 45 +#define STM32_IRQ_TIM8_CC 46 +#define STM32_IRQ_LPTIM1 49 +#define STM32_IRQ_SPI3 51 +#define STM32_IRQ_USART4 52 +#define STM32_IRQ_TIM6_DAC 54 +#define STM32_IRQ_TIM7 55 +#define STM32_IRQ_DMA2_CHANNEL1 56 +#define STM32_IRQ_DMA2_CHANNEL2 57 +#define STM32_IRQ_DMA2_CHANNEL3 58 +#define STM32_IRQ_DMA2_CHANNEL4 59 +#define STM32_IRQ_DMA2_CHANNEL5 60 +#define STM32_IRQ_UCPD1 63 +#define STM32_IRQ_COMP_1_2_3 64 +#define STM32_IRQ_COMP_4 65 +#define STM32_IRQ_CRS 75 +#define STM32_IRQ_SAI1 76 +#define STM32_IRQ_FPU 81 +#define STM32_IRQ_RNG 90 +#define STM32_IRQ_LPUART 91 +#define STM32_IRQ_I2C3_EV 92 +#define STM32_IRQ_I2C3_ER 93 +#define STM32_IRQ_DMAMUX_OVR 94 +#define STM32_IRQ_DMA1_CHANNEL8 96 +#define STM32_IRQ_DMA2_CHANNEL6 97 +#define STM32_IRQ_DMA2_CHANNEL7 98 +#define STM32_IRQ_DMA2_CHANNEL8 99 +#define STM32_IRQ_CORDIC 100 +#define STM32_IRQ_FMAC 101 /* LPUART gets accessed as UART9 in STM32 uart driver */ #define STM32_IRQ_USART9 STM32_IRQ_LPUART /* To simplify code generation, define DMA channel 13 - 14 */ -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV @@ -111,144 +111,144 @@ #endif /* Embedded flash option bytes base address */ -#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL -#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL +#define STM32_OPTB_BANK1_BASE 0x1FFF7800UL +#define STM32_OPTB_BANK2_BASE 0x1FFF8000UL /* Peripheral base addresses */ -#define STM32_PERIPH_BASE (0x40000000UL) +#define STM32_PERIPH_BASE (0x40000000UL) /* Peripheral memory map */ -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) -#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) +#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000UL) +#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000UL) +#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000UL) +#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x08000000UL) /* APB1 peripherals */ -#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset) -#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL) -#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL) -#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL) -#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL) -#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL) -#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL) -#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL) -#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL) -#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL) -#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL) -#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL) -#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL) -#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL) -#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL) -#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL) -#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL) -#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL) +#define STM32_APB1PERIPH(offset) (STM32_APB1PERIPH_BASE + offset) +#define STM32_TIM2_BASE STM32_APB1PERIPH(0x0000UL) +#define STM32_TIM3_BASE STM32_APB1PERIPH(0x0400UL) +#define STM32_TIM4_BASE STM32_APB1PERIPH(0x0800UL) +#define STM32_TIM6_BASE STM32_APB1PERIPH(0x1000UL) +#define STM32_TIM7_BASE STM32_APB1PERIPH(0x1400UL) +#define STM32_CRS_BASE STM32_APB1PERIPH(0x2000UL) +#define STM32_TAMP_BASE STM32_APB1PERIPH(0x2400UL) +#define STM32_RTC_BASE STM32_APB1PERIPH(0x2800UL) +#define STM32_WWDG_BASE STM32_APB1PERIPH(0x2C00UL) +#define STM32_IWDG_BASE STM32_APB1PERIPH(0x3000UL) +#define STM32_SPI2_BASE STM32_APB1PERIPH(0x3800UL) +#define STM32_SPI3_BASE STM32_APB1PERIPH(0x3C00UL) +#define STM32_USART2_BASE STM32_APB1PERIPH(0x4400UL) +#define STM32_USART3_BASE STM32_APB1PERIPH(0x4800UL) +#define STM32_UART4_BASE STM32_APB1PERIPH(0x4C00UL) +#define STM32_I2C1_BASE STM32_APB1PERIPH(0x5400UL) +#define STM32_I2C2_BASE STM32_APB1PERIPH(0x5800UL) /* USB_IP Peripheral Registers base address */ -#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL) +#define STM32_USB_FS_BASE STM32_APB1PERIPH(0x5C00UL) /* USB_IP Packet Memory Area base address */ -#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL) -#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL) +#define STM32_USB_PMAADDR STM32_APB1PERIPH(0x6000UL) +#define STM32_FDCAN1_BASE STM32_APB1PERIPH(0x6400UL) /* FDCAN configuration registers base address */ -#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL) -#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL) -#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL) -#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL) -#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) +#define STM32_FDCAN_CONFIG_BASE STM32_APB1PERIPH(0x6500UL) +#define STM32_PWR_BASE STM32_APB1PERIPH(0x7000UL) +#define STM32_I2C3_BASE STM32_APB1PERIPH(0x7800UL) +#define STM32_LPTIM1_BASE STM32_APB1PERIPH(0x7C00UL) +#define STM32_LPUART1_BASE STM32_APB1PERIPH(0x8000UL) +#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) /* UART9 is used as link to LPUART in STM32 uart.c implementation */ -#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL) -#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) -#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL) -#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL) +#define STM32_USART9_BASE STM32_APB1PERIPH(0x8000UL) +#define STM32_I2C4_BASE STM32_APB1PERIPH(0x8400UL) +#define STM32_UCPD1_BASE STM32_APB1PERIPH(0xA000UL) +#define STM32_SRAMCAN_BASE STM32_APB1PERIPH(0xA400UL) /* APB2 peripherals */ -#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset) -#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL) -#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL) -#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL) -#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL) -#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL) -#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL) -#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL) -#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL) -#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL) -#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL) -#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL) -#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL) -#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL) -#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL) -#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL) -#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL) -#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL) -#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL) -#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) -#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define STM32_APB2PERIPH(offset) (STM32_APB2PERIPH_BASE + offset) +#define STM32_SYSCFG_BASE STM32_APB2PERIPH(0x0000UL) +#define STM32_VREFBUF_BASE STM32_APB2PERIPH(0x0030UL) +#define STM32_COMP1_BASE STM32_APB2PERIPH(0x0200UL) +#define STM32_COMP2_BASE STM32_APB2PERIPH(0x0204UL) +#define STM32_COMP3_BASE STM32_APB2PERIPH(0x0208UL) +#define STM32_COMP4_BASE STM32_APB2PERIPH(0x020CUL) +#define STM32_OPAMP_BASE STM32_APB2PERIPH(0x0300UL) +#define STM32_OPAMP1_BASE STM32_APB2PERIPH(0x0300UL) +#define STM32_OPAMP2_BASE STM32_APB2PERIPH(0x0304UL) +#define STM32_OPAMP3_BASE STM32_APB2PERIPH(0x0308UL) +#define STM32_EXTI_BASE STM32_APB2PERIPH(0x0400UL) +#define STM32_TIM1_BASE STM32_APB2PERIPH(0x2C00UL) +#define STM32_SPI1_BASE STM32_APB2PERIPH(0x3000UL) +#define STM32_TIM8_BASE STM32_APB2PERIPH(0x3400UL) +#define STM32_USART1_BASE STM32_APB2PERIPH(0x3800UL) +#define STM32_TIM15_BASE STM32_APB2PERIPH(0x4000UL) +#define STM32_TIM16_BASE STM32_APB2PERIPH(0x4400UL) +#define STM32_TIM17_BASE STM32_APB2PERIPH(0x4800UL) +#define STM32_SAI1_BASE STM32_APB2PERIPH(0x5400UL) +#define STM32_SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define STM32_SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) /* AHB1 peripherals */ -#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset) -#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL) -#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL) -#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL) -#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL) -#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL) -#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL) -#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL) -#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL) - -#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset) -#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL) -#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL) -#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL) -#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL) -#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL) -#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL) - -#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset) -#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL) -#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL) -#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL) -#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL) -#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL) -#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL) - -#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset) -#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL) -#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL) -#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL) -#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL) -#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL) -#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL) -#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL) -#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL) -#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL) -#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL) -#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL) -#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL) -#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL) -#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL) -#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL) -#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL) -#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL) -#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL) +#define STM32_AHB1PERIPH(offset) (STM32_AHB1PERIPH_BASE + offset) +#define STM32_DMA1_BASE STM32_AHB1PERIPH(0x0000UL) +#define STM32_DMA2_BASE STM32_AHB1PERIPH(0x0400UL) +#define STM32_DMAMUX_BASE STM32_AHB1PERIPH(0x0800UL) +#define STM32_CORDIC_BASE STM32_AHB1PERIPH(0x0C00UL) +#define STM32_RCC_BASE STM32_AHB1PERIPH(0x1000UL) +#define STM32_FMAC_BASE STM32_AHB1PERIPH(0x1400UL) +#define STM32_FLASH_REGS_BASE STM32_AHB1PERIPH(0x2000UL) +#define STM32_CRC_BASE STM32_AHB1PERIPH(0x3000UL) + +#define STM32_DMA1_CHAN(offset) (STM32_DMA1_BASE + offset) +#define STM32_DMA1_Channel1_BASE STM32_DMA1_CHAN(0x0008UL) +#define STM32_DMA1_Channel2_BASE STM32_DMA1_CHAN(0x001CUL) +#define STM32_DMA1_Channel3_BASE STM32_DMA1_CHAN(0x0030UL) +#define STM32_DMA1_Channel4_BASE STM32_DMA1_CHAN(0x0044UL) +#define STM32_DMA1_Channel5_BASE STM32_DMA1_CHAN(0x0058UL) +#define STM32_DMA1_Channel6_BASE STM32_DMA1_CHAN(0x006CUL) + +#define STM32_DMA2_CHAN(offset) (STM32_DMA2_BASE + offset) +#define STM32_DMA2_Channel1_BASE STM32_DMA2_CHAN(0x0008UL) +#define STM32_DMA2_Channel2_BASE STM32_DMA2_CHAN(0x001CUL) +#define STM32_DMA2_Channel3_BASE STM32_DMA2_CHAN(0x0030UL) +#define STM32_DMA2_Channel4_BASE STM32_DMA2_CHAN(0x0044UL) +#define STM32_DMA2_Channel5_BASE STM32_DMA2_CHAN(0x0058UL) +#define STM32_DMA2_Channel6_BASE STM32_DMA2_CHAN(0x006CUL) + +#define STM32_DMAMUX(offset) (STM32_DMAMUX_BASE + offset) +#define STM32_DMAMUX_Channel0_BASE STM32_DMAMUX(0x0000UL) +#define STM32_DMAMUX_Channel1_BASE STM32_DMAMUX(0x0004UL) +#define STM32_DMAMUX_Channel2_BASE STM32_DMAMUX(0x0008UL) +#define STM32_DMAMUX_Channel3_BASE STM32_DMAMUX(0x000CUL) +#define STM32_DMAMUX_Channel4_BASE STM32_DMAMUX(0x0010UL) +#define STM32_DMAMUX_Channel5_BASE STM32_DMAMUX(0x0014UL) +#define STM32_DMAMUX_Channel6_BASE STM32_DMAMUX(0x0020UL) +#define STM32_DMAMUX_Channel7_BASE STM32_DMAMUX(0x0024UL) +#define STM32_DMAMUX_Channel8_BASE STM32_DMAMUX(0x0028UL) +#define STM32_DMAMUX_Channel9_BASE STM32_DMAMUX(0x002CUL) +#define STM32_DMAMUX_Channel10_BASE STM32_DMAMUX(0x0030UL) +#define STM32_DMAMUX_Channel11_BASE STM32_DMAMUX(0x0034UL) +#define STM32_DMAMUX_RequestGenerator0_BASE STM32_DMAMUX(0x0100UL) +#define STM32_DMAMUX_RequestGenerator1_BASE STM32_DMAMUX(0x0104UL) +#define STM32_DMAMUX_RequestGenerator2_BASE STM32_DMAMUX(0x0108UL) +#define STM32_DMAMUX_RequestGenerator3_BASE STM32_DMAMUX(0x010CUL) +#define STM32_DMAMUX_ChannelStatus_BASE STM32_DMAMUX(0x0080UL) +#define STM32_DMAMUX_RequestGenStatus_BASE STM32_DMAMUX(0x0140UL) /* AHB2 peripherals */ -#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset) -#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL) -#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL) -#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL) -#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL) -#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL) -#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL) -#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL) -#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL) -#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL) -#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL) -#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL) -#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL) -#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL) - -#define STM32_UNIQUE_ID_BASE 0x1FFF7590 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_AHB2PERIPH(offset) (STM32_AHB2PERIPH_BASE + offset) +#define STM32_GPIOA_BASE STM32_AHB2PERIPH(0x0000UL) +#define STM32_GPIOB_BASE STM32_AHB2PERIPH(0x0400UL) +#define STM32_GPIOC_BASE STM32_AHB2PERIPH(0x0800UL) +#define STM32_GPIOD_BASE STM32_AHB2PERIPH(0x0C00UL) +#define STM32_GPIOE_BASE STM32_AHB2PERIPH(0x1000UL) +#define STM32_GPIOF_BASE STM32_AHB2PERIPH(0x1400UL) +#define STM32_GPIOG_BASE STM32_AHB2PERIPH(0x1800UL) +#define STM32_ADC1_BASE STM32_AHB2PERIPH(0x08000000UL) +#define STM32_ADC2_BASE STM32_AHB2PERIPH(0x08000100UL) +#define STM32_ADC12_COMMON_BASE STM32_AHB2PERIPH(0x08000300UL) +#define STM32_DAC_BASE STM32_AHB2PERIPH(0x08000800UL) +#define STM32_DAC1_BASE STM32_AHB2PERIPH(0x08000800UL) +#define STM32_DAC3_BASE STM32_AHB2PERIPH(0x08001000UL) +#define STM32_RNG_BASE STM32_AHB2PERIPH(0x08060800UL) + +#define STM32_UNIQUE_ID_BASE 0x1FFF7590 +#define STM32_DBGMCU_BASE 0xE0042000 #ifndef __ASSEMBLER__ @@ -256,319 +256,299 @@ /* --- UCPD --- */ #define STM32_UCPD_REG(port, offset) \ - REG32(((STM32_UCPD1_BASE + ((port) * 0x400)) + (offset))) - -#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00) -#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04) -#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c) -#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10) -#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14) -#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18) -#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c) -#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20) -#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24) -#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28) -#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c) -#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30) -#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34) -#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38) + REG32(((STM32_UCPD1_BASE + ((port)*0x400)) + (offset))) + +#define STM32_UCPD_CFGR1(port) STM32_UCPD_REG(port, 0x00) +#define STM32_UCPD_CFGR2(port) STM32_UCPD_REG(port, 0x04) +#define STM32_UCPD_CR(port) STM32_UCPD_REG(port, 0x0c) +#define STM32_UCPD_IMR(port) STM32_UCPD_REG(port, 0x10) +#define STM32_UCPD_SR(port) STM32_UCPD_REG(port, 0x14) +#define STM32_UCPD_ICR(port) STM32_UCPD_REG(port, 0x18) +#define STM32_UCPD_TX_ORDSETR(port) STM32_UCPD_REG(port, 0x1c) +#define STM32_UCPD_TX_PAYSZR(port) STM32_UCPD_REG(port, 0x20) +#define STM32_UCPD_TXDR(port) STM32_UCPD_REG(port, 0x24) +#define STM32_UCPD_RX_ORDSETR(port) STM32_UCPD_REG(port, 0x28) +#define STM32_UCPD_RX_PAYSZR(port) STM32_UCPD_REG(port, 0x2c) +#define STM32_UCPD_RXDR(port) STM32_UCPD_REG(port, 0x30) +#define STM32_UCPD_RX_ORDEXTR1(port) STM32_UCPD_REG(port, 0x34) +#define STM32_UCPD_RX_ORDEXTR2(port) STM32_UCPD_REG(port, 0x38) /* --- UCPD CFGR1 Bit Definitions --- */ -#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0 -#define STM32_UCPD_CFGR1_HBITCLKD_MASK ((0x3f) << \ - (STM32_UCPD_CFGR1_HBITCLKD_SHIFT)) -#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_HBITCLKD_SHIFT) -#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6 -#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_IFRGAP_SHIFT)) -#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_IFRGAP_SHIFT) -#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11 -#define STM32_UCPD_CFGR1_TRANSWIN_MASK ((0x1f) << \ - (STM32_UCPD_CFGR1_TRANSWIN_SHIFT)) -#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_TRANSWIN_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17 -#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_PSC_CLK_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20 -#define STM32_UCPD_CFGR1_RXORDSETEN_MASK ((0x1ff) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) ((x) << \ - STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) -#define STM32_UCPD_CFGR1_TXDMAEN BIT(29) -#define STM32_UCPD_CFGR1_RXDMAEN BIT(30) -#define STM32_UCPD_CFGR1_UCPDEN BIT(31) +#define STM32_UCPD_CFGR1_HBITCLKD_SHIFT 0 +#define STM32_UCPD_CFGR1_HBITCLKD_MASK \ + ((0x3f) << (STM32_UCPD_CFGR1_HBITCLKD_SHIFT)) +#define STM32_UCPD_CFGR1_HBITCLKD_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_HBITCLKD_SHIFT) +#define STM32_UCPD_CFGR1_IFRGAP_SHIFT 6 +#define STM32_UCPD_CFGR1_IFRGAP_MASK ((0x1f) << (STM32_UCPD_CFGR1_IFRGAP_SHIFT)) +#define STM32_UCPD_CFGR1_IFRGAP_VAL(x) ((x) << STM32_UCPD_CFGR1_IFRGAP_SHIFT) +#define STM32_UCPD_CFGR1_TRANSWIN_SHIFT 11 +#define STM32_UCPD_CFGR1_TRANSWIN_MASK \ + ((0x1f) << (STM32_UCPD_CFGR1_TRANSWIN_SHIFT)) +#define STM32_UCPD_CFGR1_TRANSWIN_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_TRANSWIN_SHIFT) +#define STM32_UCPD_CFGR1_PSC_CLK_SHIFT 17 +#define STM32_UCPD_CFGR1_PSC_CLK_MASK ((0x7) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT) +#define STM32_UCPD_CFGR1_PSC_CLK_VAL(x) ((x) << STM32_UCPD_CFGR1_PSC_CLK_SHIFT) +#define STM32_UCPD_CFGR1_RXORDSETEN_SHIFT 20 +#define STM32_UCPD_CFGR1_RXORDSETEN_MASK \ + ((0x1ff) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) +#define STM32_UCPD_CFGR1_RXORDSETEN_VAL(x) \ + ((x) << STM32_UCPD_CFGR1_RXORDSETEN_SHIFT) +#define STM32_UCPD_CFGR1_TXDMAEN BIT(29) +#define STM32_UCPD_CFGR1_RXDMAEN BIT(30) +#define STM32_UCPD_CFGR1_UCPDEN BIT(31) /* --- UCPD CFGR2 Bit Definitions --- */ -#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0) -#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1) -#define STM32_UCPD_CFGR2_FORCECLK BIT(2) -#define STM32_UCPD_CFGR2_WUPEN BIT(3) +#define STM32_UCPD_CFGR2_RXFILTDIS BIT(0) +#define STM32_UCPD_CFGR2_RXFILT2N3 BIT(1) +#define STM32_UCPD_CFGR2_FORCECLK BIT(2) +#define STM32_UCPD_CFGR2_WUPEN BIT(3) /* --- UCPD CR Bit Definitions --- */ -#define STM32_UCPD_CR_TXMODE_SHIFT 0 -#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_TXMODE_SHIFT)) -#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT) -#define STM32_UCPD_CR_TXSEND BIT(2) -#define STM32_UCPD_CR_TXHRST BIT(3) -#define STM32_UCPD_CR_RXMODE BIT(4) -#define STM32_UCPD_CR_PHYRXEN BIT(5) -#define STM32_UCPD_CR_PHYCCSEL BIT(6) -#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7 -#define STM32_UCPD_CR_ANASUBMODE_MASK ((0x3) << \ - (STM32_UCPD_CR_ANASUBMODE_SHIFT)) -#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << \ - STM32_UCPD_CR_ANASUBMODE_SHIFT) -#define STM32_UCPD_CR_ANAMODE BIT(9) -#define STM32_UCPD_CR_CCENABLE_SHIFT 10 -#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << \ - (STM32_UCPD_CR_CCENABLE_SHIFT)) -#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << \ - STM32_UCPD_CR_CCENABLE_SHIFT) -#define STM32_UCPD_CR_FRSRXEN BIT(16) -#define STM32_UCPD_CR_FRSTX BIT(17) -#define STM32_UCPD_CR_RDCH BIT(18) -#define STM32_UCPD_CR_CC1TCDIS BIT(20) -#define STM32_UCPD_CR_CC2TCDIS BIT(21) +#define STM32_UCPD_CR_TXMODE_SHIFT 0 +#define STM32_UCPD_CR_TXMODE_MASK ((0x3) << (STM32_UCPD_CR_TXMODE_SHIFT)) +#define STM32_UCPD_CR_TXMODE_VAL(x) ((x) << STM32_UCPD_CR_TXMODE_SHIFT) +#define STM32_UCPD_CR_TXSEND BIT(2) +#define STM32_UCPD_CR_TXHRST BIT(3) +#define STM32_UCPD_CR_RXMODE BIT(4) +#define STM32_UCPD_CR_PHYRXEN BIT(5) +#define STM32_UCPD_CR_PHYCCSEL BIT(6) +#define STM32_UCPD_CR_ANASUBMODE_SHIFT 7 +#define STM32_UCPD_CR_ANASUBMODE_MASK \ + ((0x3) << (STM32_UCPD_CR_ANASUBMODE_SHIFT)) +#define STM32_UCPD_CR_ANASUBMODE_VAL(x) ((x) << STM32_UCPD_CR_ANASUBMODE_SHIFT) +#define STM32_UCPD_CR_ANAMODE BIT(9) +#define STM32_UCPD_CR_CCENABLE_SHIFT 10 +#define STM32_UCPD_CR_CCENABLE_MASK ((0x3) << (STM32_UCPD_CR_CCENABLE_SHIFT)) +#define STM32_UCPD_CR_CCENABLE_VAL(x) ((x) << STM32_UCPD_CR_CCENABLE_SHIFT) +#define STM32_UCPD_CR_FRSRXEN BIT(16) +#define STM32_UCPD_CR_FRSTX BIT(17) +#define STM32_UCPD_CR_RDCH BIT(18) +#define STM32_UCPD_CR_CC1TCDIS BIT(20) +#define STM32_UCPD_CR_CC2TCDIS BIT(21) /* TX mode message types */ -#define STM32_UCPD_CR_TXMODE_DEF 0 -#define STM32_UCPD_CR_TXMODE_CBL_RST 1 -#define STM32_UCPD_CR_TXMODE_BIST 2 +#define STM32_UCPD_CR_TXMODE_DEF 0 +#define STM32_UCPD_CR_TXMODE_CBL_RST 1 +#define STM32_UCPD_CR_TXMODE_BIST 2 /* --- UCPD IMR Bit Definitions --- */ -#define STM32_UCPD_IMR_TXISIE BIT(0) -#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1) -#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2) -#define STM32_UCPD_IMR_TXMSGABTIE BIT(3) -#define STM32_UCPD_IMR_HRSTDISCIE BIT(4) -#define STM32_UCPD_IMR_HRSTSENTIE BIT(5) -#define STM32_UCPD_IMR_TXUNDIE BIT(6) -#define STM32_UCPD_IMR_RXNEIE BIT(8) -#define STM32_UCPD_IMR_RXORDDETIE BIT(9) -#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10) -#define STM32_UCPD_IMR_RXOVRIE BIT(11) -#define STM32_UCPD_IMR_RXMSGENDIE BIT(12) -#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14) -#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15) -#define STM32_UCPD_IMR_FRSEVTIE BIT(20) +#define STM32_UCPD_IMR_TXISIE BIT(0) +#define STM32_UCPD_IMR_TXMSGDISCIE BIT(1) +#define STM32_UCPD_IMR_TXMSGSENTIE BIT(2) +#define STM32_UCPD_IMR_TXMSGABTIE BIT(3) +#define STM32_UCPD_IMR_HRSTDISCIE BIT(4) +#define STM32_UCPD_IMR_HRSTSENTIE BIT(5) +#define STM32_UCPD_IMR_TXUNDIE BIT(6) +#define STM32_UCPD_IMR_RXNEIE BIT(8) +#define STM32_UCPD_IMR_RXORDDETIE BIT(9) +#define STM32_UCPD_IMR_RXHRSTDETIE BIT(10) +#define STM32_UCPD_IMR_RXOVRIE BIT(11) +#define STM32_UCPD_IMR_RXMSGENDIE BIT(12) +#define STM32_UCPD_IMR_TYPECEVT1IE BIT(14) +#define STM32_UCPD_IMR_TYPECEVT2IE BIT(15) +#define STM32_UCPD_IMR_FRSEVTIE BIT(20) /* --- UCPD SR Bit Definitions --- */ -#define STM32_UCPD_SR_TXIS BIT(0) -#define STM32_UCPD_SR_TXMSGDISC BIT(1) -#define STM32_UCPD_SR_TXMSGSENT BIT(2) -#define STM32_UCPD_SR_TXMSGABT BIT(3) -#define STM32_UCPD_SR_HRSTDISC BIT(4) -#define STM32_UCPD_SR_HRSTSENT BIT(5) -#define STM32_UCPD_SR_TXUND BIT(6) -#define STM32_UCPD_SR_RXNE BIT(8) -#define STM32_UCPD_SR_RXORDDET BIT(9) -#define STM32_UCPD_SR_RXHRSTDET BIT(10) -#define STM32_UCPD_SR_RXOVR BIT(11) -#define STM32_UCPD_SR_RXMSGEND BIT(12) -#define STM32_UCPD_SR_RXERR BIT(13) -#define STM32_UCPD_SR_TYPECEVT1 BIT(14) -#define STM32_UCPD_SR_TYPECEVT2 BIT(15) -#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16 -#define STM32_UCPD_SR_VSTATE_CC1_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC1_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC1_SHIFT) -#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18 -#define STM32_UCPD_SR_VSTATE_CC2_MASK ((0x3) << \ - (STM32_UCPD_SR_VSTATE_CC2_SHIFT)) -#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << \ - STM32_UCPD_SR_VSTATE_CC2_SHIFT) -#define STM32_UCPD_SR_FRSEVT BIT(20) - -#define STM32_UCPD_SR_VSTATE_OPEN 3 -#define STM32_UCPD_SR_VSTATE_RA 0 +#define STM32_UCPD_SR_TXIS BIT(0) +#define STM32_UCPD_SR_TXMSGDISC BIT(1) +#define STM32_UCPD_SR_TXMSGSENT BIT(2) +#define STM32_UCPD_SR_TXMSGABT BIT(3) +#define STM32_UCPD_SR_HRSTDISC BIT(4) +#define STM32_UCPD_SR_HRSTSENT BIT(5) +#define STM32_UCPD_SR_TXUND BIT(6) +#define STM32_UCPD_SR_RXNE BIT(8) +#define STM32_UCPD_SR_RXORDDET BIT(9) +#define STM32_UCPD_SR_RXHRSTDET BIT(10) +#define STM32_UCPD_SR_RXOVR BIT(11) +#define STM32_UCPD_SR_RXMSGEND BIT(12) +#define STM32_UCPD_SR_RXERR BIT(13) +#define STM32_UCPD_SR_TYPECEVT1 BIT(14) +#define STM32_UCPD_SR_TYPECEVT2 BIT(15) +#define STM32_UCPD_SR_VSTATE_CC1_SHIFT 16 +#define STM32_UCPD_SR_VSTATE_CC1_MASK \ + ((0x3) << (STM32_UCPD_SR_VSTATE_CC1_SHIFT)) +#define STM32_UCPD_SR_VSTATE_CC1_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC1_SHIFT) +#define STM32_UCPD_SR_VSTATE_CC2_SHIFT 18 +#define STM32_UCPD_SR_VSTATE_CC2_MASK \ + ((0x3) << (STM32_UCPD_SR_VSTATE_CC2_SHIFT)) +#define STM32_UCPD_SR_VSTATE_CC2_VAL(x) ((x) << STM32_UCPD_SR_VSTATE_CC2_SHIFT) +#define STM32_UCPD_SR_FRSEVT BIT(20) + +#define STM32_UCPD_SR_VSTATE_OPEN 3 +#define STM32_UCPD_SR_VSTATE_RA 0 /* --- UCPD ICR Bit Definitions --- */ -#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1) -#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2) -#define STM32_UCPD_ICR_TXMSGABTCF BIT(3) -#define STM32_UCPD_ICR_HRSTDISCCF BIT(4) -#define STM32_UCPD_ICR_HRSTSENTCF BIT(5) -#define STM32_UCPD_ICR_TXUNDCF BIT(6) -#define STM32_UCPD_ICR_RXORDDETCF BIT(9) -#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10) -#define STM32_UCPD_ICR_RXOVRCF BIT(11) -#define STM32_UCPD_ICR_RXMSGENDCF BIT(12) -#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14) -#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15) -#define STM32_UCPD_ICR_FRSEVTCF BIT(20) - +#define STM32_UCPD_ICR_TXMSGDISCCF BIT(1) +#define STM32_UCPD_ICR_TXMSGSENTCF BIT(2) +#define STM32_UCPD_ICR_TXMSGABTCF BIT(3) +#define STM32_UCPD_ICR_HRSTDISCCF BIT(4) +#define STM32_UCPD_ICR_HRSTSENTCF BIT(5) +#define STM32_UCPD_ICR_TXUNDCF BIT(6) +#define STM32_UCPD_ICR_RXORDDETCF BIT(9) +#define STM32_UCPD_ICR_RXHRSTDETCF BIT(10) +#define STM32_UCPD_ICR_RXOVRCF BIT(11) +#define STM32_UCPD_ICR_RXMSGENDCF BIT(12) +#define STM32_UCPD_ICR_TYPECEVT1CF BIT(14) +#define STM32_UCPD_ICR_TYPECEVT2CF BIT(15) +#define STM32_UCPD_ICR_FRSEVTCF BIT(20) /* --- UCPD TX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_TX_ORDSETR_SHIFT 0 -#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << \ - (STM32_UCPD_TX_ORDSETR_SHIFT)) -#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT) +#define STM32_UCPD_TX_ORDSETR_SHIFT 0 +#define STM32_UCPD_TX_ORDSETR_MASK ((0xfffff) << (STM32_UCPD_TX_ORDSETR_SHIFT)) +#define STM32_UCPD_TX_ORDSETR_VAL(x) ((x) << STM32_UCPD_TX_ORDSETR_SHIFT) /* --- UCPD TX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_TX_PAYSZR_SHIFT 0 -#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_TX_PAYSZR_SHIFT)) -#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT) +#define STM32_UCPD_TX_PAYSZR_SHIFT 0 +#define STM32_UCPD_TX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_TX_PAYSZR_SHIFT)) +#define STM32_UCPD_TX_PAYSZR_VAL(x) ((x) << STM32_UCPD_TX_PAYSZR_SHIFT) /* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_TXDR_SHIFT 0 -#define STM32_UCPD_TXDR_MASK ((0xff) << \ - (STM32_UCPD_TXDR_SHIFT)) -#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT) +#define STM32_UCPD_TXDR_SHIFT 0 +#define STM32_UCPD_TXDR_MASK ((0xff) << (STM32_UCPD_TXDR_SHIFT)) +#define STM32_UCPD_TXDR_VAL(x) ((x) << STM32_UCPD_TXDR_SHIFT) /* --- UCPD RX_ORDSETR Bit Definitions --- */ -#define STM32_UCPD_RXORDSETR_SHIFT 0 -#define STM32_UCPD_RXORDSETR_MASK ((0x7) << \ - (STM32_UCPD_RXORDSETR_SHIFT)) -#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT) -#define STM32_UCPD_RXSOP3OF4 BIT(3) -#define STM32_UCPD_RXSOPKINVALID_SHIFT 4 -#define STM32_UCPD_RXSOPKINVALID_MASK ((0x7) << \ - (STM32_UCPD_RXSOPKINVALID_SHIFT)) -#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << \ - STM32_UCPD_RXSOPKINVALID_SHIFT) +#define STM32_UCPD_RXORDSETR_SHIFT 0 +#define STM32_UCPD_RXORDSETR_MASK ((0x7) << (STM32_UCPD_RXORDSETR_SHIFT)) +#define STM32_UCPD_RXORDSETR_VAL(x) ((x) << STM32_UCPD_RXORDSETR_SHIFT) +#define STM32_UCPD_RXSOP3OF4 BIT(3) +#define STM32_UCPD_RXSOPKINVALID_SHIFT 4 +#define STM32_UCPD_RXSOPKINVALID_MASK \ + ((0x7) << (STM32_UCPD_RXSOPKINVALID_SHIFT)) +#define STM32_UCPD_RXSOPKINVALID_VAL(x) ((x) << STM32_UCPD_RXSOPKINVALID_SHIFT) /* --- UCPD RX_PAYSZR Bit Definitions --- */ -#define STM32_UCPD_RX_PAYSZR_SHIFT 0 -#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << \ - (STM32_UCPD_RX_PAYSZR_SHIFT)) -#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT) +#define STM32_UCPD_RX_PAYSZR_SHIFT 0 +#define STM32_UCPD_RX_PAYSZR_MASK ((0x3ff) << (STM32_UCPD_RX_PAYSZR_SHIFT)) +#define STM32_UCPD_RX_PAYSZR_VAL(x) ((x) << STM32_UCPD_RX_PAYSZR_SHIFT) /* --- UCPD TXDR Bit Definitions --- */ -#define STM32_UCPD_RXDR_SHIFT 0 -#define STM32_UCPD_RXDR_MASK ((0xff) << \ - (STM32_UCPD_RXDR_SHIFT)) -#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT) - +#define STM32_UCPD_RXDR_SHIFT 0 +#define STM32_UCPD_RXDR_MASK ((0xff) << (STM32_UCPD_RXDR_SHIFT)) +#define STM32_UCPD_RXDR_VAL(x) ((x) << STM32_UCPD_RXDR_SHIFT) /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) /* --- USART bit definitions -- */ -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) - -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) - -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) - +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) + +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) + +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* --- GPIO --- */ -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_I2C3 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_LPUART 0xC -#define GPIO_ALT_SAI1 0xD -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_I2C3 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_LPUART 0xC +#define GPIO_ALT_SAI1 0xD +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ #define stm32g4_i2c_reg(base, offset) ((uint16_t *)((base) + (offset))) -#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00)) -#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04)) -#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08)) -#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C)) -#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10)) -#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14)) -#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18)) -#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C)) -#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20)) -#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24)) -#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28)) +#define STM32_I2C_CR1(base) REG32(stm32g4_i2c_reg(base, 0x00)) +#define STM32_I2C_CR2(base) REG32(stm32g4_i2c_reg(base, 0x04)) +#define STM32_I2C_OAR1(base) REG16(stm32g4_i2c_reg(base, 0x08)) +#define STM32_I2C_OAR2(base) REG16(stm32g4_i2c_reg(base, 0x0C)) +#define STM32_I2C_TIMINGR(base) REG32(stm32g4_i2c_reg(base, 0x10)) +#define STM32_I2C_TIMEOUTR(base) REG32(stm32g4_i2c_reg(base, 0x14)) +#define STM32_I2C_ISR(base) REG32(stm32g4_i2c_reg(base, 0x18)) +#define STM32_I2C_ICR(base) REG32(stm32g4_i2c_reg(base, 0x1C)) +#define STM32_I2C_PECR(base) REG32(stm32g4_i2c_reg(base, 0x20)) +#define STM32_I2C_RXDR(base) REG32(stm32g4_i2c_reg(base, 0x24)) +#define STM32_I2C_TXDR(base) REG32(stm32g4_i2c_reg(base, 0x28)) /* --- I2C CR1 Bit Definitions --- */ -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_TXIE BIT(1) -#define STM32_I2C_CR1_RXIE BIT(2) -#define STM32_I2C_CR1_ADDRIE BIT(3) -#define STM32_I2C_CR1_NACKIE BIT(4) -#define STM32_I2C_CR1_STOPIE BIT(5) -#define STM32_I2C_CR1_ERRIE BIT(7) -#define STM32_I2C_CR1_WUPEN BIT(18) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_WUPEN BIT(18) /* --- I2C CR2 Bit Definitions --- */ -#define STM32_I2C_CR2_RD_WRN BIT(10) -#define STM32_I2C_CR2_START BIT(13) -#define STM32_I2C_CR2_STOP BIT(14) -#define STM32_I2C_CR2_NACK BIT(15) -#define STM32_I2C_CR2_RELOAD BIT(24) -#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_AUTOEND BIT(25) /* --- I2C ISR Bit Definitions --- */ -#define STM32_I2C_ISR_TXE BIT(0) -#define STM32_I2C_ISR_TXIS BIT(1) -#define STM32_I2C_ISR_RXNE BIT(2) -#define STM32_I2C_ISR_ADDR BIT(3) -#define STM32_I2C_ISR_NACK BIT(4) -#define STM32_I2C_ISR_STOP BIT(5) -#define STM32_I2C_ISR_TC BIT(6) -#define STM32_I2C_ISR_TCR BIT(7) -#define STM32_I2C_ISR_BERR BIT(8) -#define STM32_I2C_ISR_ARLO BIT(9) -#define STM32_I2C_ISR_OVR BIT(10) -#define STM32_I2C_ISR_PECERR BIT(11) -#define STM32_I2C_ISR_TIMEOUT BIT(12) -#define STM32_I2C_ISR_ALERT BIT(13) -#define STM32_I2C_ISR_BUSY BIT(15) -#define STM32_I2C_ISR_DIR BIT(16) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_NACK BIT(4) +#define STM32_I2C_ISR_STOP BIT(5) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_OVR BIT(10) +#define STM32_I2C_ISR_PECERR BIT(11) +#define STM32_I2C_ISR_TIMEOUT BIT(12) +#define STM32_I2C_ISR_ALERT BIT(13) +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_DIR BIT(16) /* --- I2C ICR Bit Definitions --- */ -#define STM32_I2C_ICR_ADDRCF BIT(3) -#define STM32_I2C_ICR_NACKCF BIT(4) -#define STM32_I2C_ICR_STOPCF BIT(5) -#define STM32_I2C_ICR_BERRCF BIT(8) -#define STM32_I2C_ICR_ARLOCF BIT(9) -#define STM32_I2C_ICR_OVRCF BIT(10) -#define STM32_I2C_ICR_TIMEOUTCF BIT(12) -#define STM32_I2C_ICR_ALL 0x3F38 +#define STM32_I2C_ICR_ADDRCF BIT(3) +#define STM32_I2C_ICR_NACKCF BIT(4) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_OVRCF BIT(10) +#define STM32_I2C_ICR_TIMEOUTCF BIT(12) +#define STM32_I2C_ICR_ALL 0x3F38 /* --- I2C TIMINGR bit Definitions --- */ #define STM32_I2C_TIMINGR_SCLL_OFF 0 @@ -579,277 +559,271 @@ /* --- Power / Reset / Clocks --- */ -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) -#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) -#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) -#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) -#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) -#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) -#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) -#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) -#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) -#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) -#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) -#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_AHB1RSTR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_AHB2RSTR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_AHB3RSTR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_APB1RSTR1 REG32(STM32_RCC_BASE + 0x38) +#define STM32_RCC_APB1RSTR2 REG32(STM32_RCC_BASE + 0x3C) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x40) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x48) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x4C) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x50) +#define STM32_RCC_APB1ENR1 REG32(STM32_RCC_BASE + 0x58) +#define STM32_RCC_APB1ENR2 REG32(STM32_RCC_BASE + 0x5C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x60) +#define STM32_RCC_AHB1SMENR REG32(STM32_RCC_BASE + 0x68) +#define STM32_RCC_AHB2SMENR REG32(STM32_RCC_BASE + 0x6C) +#define STM32_RCC_AHB3SMENR REG32(STM32_RCC_BASE + 0x70) +#define STM32_RCC_APB1SMENR1 REG32(STM32_RCC_BASE + 0x78) +#define STM32_RCC_APB1SMENR2 REG32(STM32_RCC_BASE + 0x7C) +#define STM32_RCC_APB2SMENR REG32(STM32_RCC_BASE + 0x80) +#define STM32_RCC_CCIPR REG32(STM32_RCC_BASE + 0x88) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x90) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x94) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x98) +#define STM32_RCC_CCIPR2 REG32(STM32_RCC_BASE + 0x9C) #define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 #define STM32_RCC_AHBENR STM32_RCC_APB1ENR /* --- RCC CR Bit Definitions --- */ -#define STM32_RCC_CR_HSION BIT(8) -#define STM32_RCC_CR_HSIRDY BIT(10) -#define STM32_RCC_CR_HSEON BIT(16) -#define STM32_RCC_CR_HSERDY BIT(17) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_CR_HSION BIT(8) +#define STM32_RCC_CR_HSIRDY BIT(10) +#define STM32_RCC_CR_HSEON BIT(16) +#define STM32_RCC_CR_HSERDY BIT(17) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) /* --- RCC PLLCFGR Bit Definitions --- */ -#define PLLCFGR_PLLSRC_OFF 0 -#define PLLCFGR_PLLSRC(val) (((val) & 0x3) << PLLCFGR_PLLSRC_OFF) -#define PLLCFGR_PLLSRC_HSI 2 -#define PLLCFGR_PLLSRC_HSE 3 +#define PLLCFGR_PLLSRC_OFF 0 +#define PLLCFGR_PLLSRC(val) (((val)&0x3) << PLLCFGR_PLLSRC_OFF) +#define PLLCFGR_PLLSRC_HSI 2 +#define PLLCFGR_PLLSRC_HSE 3 /* PLL Division factor */ -#define PLLCFGR_PLLM_OFF 4 -#define PLLCFGR_PLLM(val) (((val) & 0x1f) << PLLCFGR_PLLM_OFF) +#define PLLCFGR_PLLM_OFF 4 +#define PLLCFGR_PLLM(val) (((val)&0x1f) << PLLCFGR_PLLM_OFF) /* PLL Multiplication factor */ -#define PLLCFGR_PLLN_OFF 8 -#define PLLCFGR_PLLN(val) (((val) & 0x7f) << PLLCFGR_PLLN_OFF) -#define PLLCFGR_PLLQ_EN BIT(20) -#define PLLCFGR_PLLQ_OFF 21 -#define PLLCFGR_PLLQ(val) (((val) & 0x3) << PLLCFGR_PLLQ_OFF) +#define PLLCFGR_PLLN_OFF 8 +#define PLLCFGR_PLLN(val) (((val)&0x7f) << PLLCFGR_PLLN_OFF) +#define PLLCFGR_PLLQ_EN BIT(20) +#define PLLCFGR_PLLQ_OFF 21 +#define PLLCFGR_PLLQ(val) (((val)&0x3) << PLLCFGR_PLLQ_OFF) /* System and main CPU clock */ -#define PLLCFGR_PLLR_EN BIT(24) -#define PLLCFGR_PLLR_OFF 25 -#define PLLCFGR_PLLR(val) (((val) & 0x3) << PLLCFGR_PLLR_OFF) -#define PLLCFGR_PLLP_OFF 27 -#define PLLCFGR_PLLP(val) (((val) & 0x1f) << PLLCFGR_PLLP_OFF) +#define PLLCFGR_PLLR_EN BIT(24) +#define PLLCFGR_PLLR_OFF 25 +#define PLLCFGR_PLLR(val) (((val)&0x3) << PLLCFGR_PLLR_OFF) +#define PLLCFGR_PLLP_OFF 27 +#define PLLCFGR_PLLP(val) (((val)&0x1f) << PLLCFGR_PLLP_OFF) /* --- RCC CFGR Bit Definitions --- */ -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define STM32_RCC_CFGR_SW_HSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (1 << 2) +#define STM32_RCC_CFGR_SWS_HSE (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) /* AHB Prescalar: */ -#define CFGR_HPRE_OFF 4 -#define CFGR_HPRE(val) (((val) & 0xf) << CFGR_HPRE_OFF) +#define CFGR_HPRE_OFF 4 +#define CFGR_HPRE(val) (((val)&0xf) << CFGR_HPRE_OFF) /* APB1 Low Speed Prescalar < 45MHz */ -#define CFGR_PPRE1_OFF 8 -#define CFGR_PPRE1(val) (((val) & 0x7) << CFGR_PPRE1_OFF) +#define CFGR_PPRE1_OFF 8 +#define CFGR_PPRE1(val) (((val)&0x7) << CFGR_PPRE1_OFF) /* APB2 High Speed Prescalar < 90MHz */ -#define CFGR_PPRE2_OFF 11 -#define CFGR_PPRE2(val) (((val) & 0x7) << CFGR_PPRE2_OFF) +#define CFGR_PPRE2_OFF 11 +#define CFGR_PPRE2(val) (((val)&0x7) << CFGR_PPRE2_OFF) /* RTC CLock: Must equal 1MHz */ -#define CFGR_RTCPRE_OFF 16 -#define CFGR_RTCPRE(val) (((val) & 0x1f) << CFGR_RTCPRE_OFF) +#define CFGR_RTCPRE_OFF 16 +#define CFGR_RTCPRE(val) (((val)&0x1f) << CFGR_RTCPRE_OFF) /* --- RCC AHB1ENR Bit Definitions --- */ -#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) -#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) -#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2) +#define STM32_RCC_AHB1ENR_DMA1EN BIT(0) +#define STM32_RCC_AHB1ENR_DMA2EN BIT(1) +#define STM32_RCC_AHB1ENR_DMAMUXEN BIT(2) /* --- RCC AHB2ENR Bit Definitions --- */ -#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) -#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) -#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) -#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) -#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) -#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5) -#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6) -#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0) -#define STM32_RCC_AHB2ENR_ADC12EN BIT(13) -#define STM32_RCC_APB2ENR_ADC345EN BIT(14) -#define STM32_RCC_AHB2ENR_RNGEN BIT(26) +#define STM32_RCC_AHB2ENR_GPIO_PORTA BIT(0) +#define STM32_RCC_AHB2ENR_GPIO_PORTB BIT(1) +#define STM32_RCC_AHB2ENR_GPIO_PORTC BIT(2) +#define STM32_RCC_AHB2ENR_GPIO_PORTD BIT(3) +#define STM32_RCC_AHB2ENR_GPIO_PORTE BIT(4) +#define STM32_RCC_AHB2ENR_GPIO_PORTF BIT(5) +#define STM32_RCC_AHB2ENR_GPIO_PORTG BIT(6) +#define STM32_RCC_AHB2ENR_GPIOMASK (0x7f << 0) +#define STM32_RCC_AHB2ENR_ADC12EN BIT(13) +#define STM32_RCC_APB2ENR_ADC345EN BIT(14) +#define STM32_RCC_AHB2ENR_RNGEN BIT(26) /* --- RCC APB1ENR1 Bit Definitions --- */ -#define STM32_RCC_APB1ENR1_TIM2EN BIT(0) -#define STM32_RCC_APB1ENR1_TIM3EN BIT(1) -#define STM32_RCC_APB1ENR1_TIM4EN BIT(2) -#define STM32_RCC_APB1ENR1_TIM5EN BIT(3) -#define STM32_RCC_APB1ENR1_TIM6EN BIT(4) -#define STM32_RCC_APB1ENR1_TIM7EN BIT(5) -#define STM32_RCC_APB1ENR1_WWDGEN BIT(11) -#define STM32_RCC_APB1ENR1_USART2 BIT(17) -#define STM32_RCC_APB1ENR1_USART3 BIT(18) -#define STM32_RCC_APB1ENR1_UART4 BIT(19) -#define STM32_RCC_APB1ENR1_UART5 BIT(20) -#define STM32_RCC_APB1ENR1_I2C1EN BIT(21) -#define STM32_RCC_APB1ENR1_I2C2EN BIT(22) -#define STM32_RCC_APB1ENR1_USBEN BIT(23) -#define STM32_RCC_APB1ENR1_PWREN BIT(28) -#define STM32_RCC_APB1ENR1_I2C3EN BIT(30) +#define STM32_RCC_APB1ENR1_TIM2EN BIT(0) +#define STM32_RCC_APB1ENR1_TIM3EN BIT(1) +#define STM32_RCC_APB1ENR1_TIM4EN BIT(2) +#define STM32_RCC_APB1ENR1_TIM5EN BIT(3) +#define STM32_RCC_APB1ENR1_TIM6EN BIT(4) +#define STM32_RCC_APB1ENR1_TIM7EN BIT(5) +#define STM32_RCC_APB1ENR1_WWDGEN BIT(11) +#define STM32_RCC_APB1ENR1_USART2 BIT(17) +#define STM32_RCC_APB1ENR1_USART3 BIT(18) +#define STM32_RCC_APB1ENR1_UART4 BIT(19) +#define STM32_RCC_APB1ENR1_UART5 BIT(20) +#define STM32_RCC_APB1ENR1_I2C1EN BIT(21) +#define STM32_RCC_APB1ENR1_I2C2EN BIT(22) +#define STM32_RCC_APB1ENR1_USBEN BIT(23) +#define STM32_RCC_APB1ENR1_PWREN BIT(28) +#define STM32_RCC_APB1ENR1_I2C3EN BIT(30) #define STM32_RCC_PWREN STM32_RCC_APB1ENR1_PWREN /* --- RCC APB1ENR2 Bit Definitions --- */ -#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) -#define STM32_RCC_APB1ENR2_I2C4EN BIT(1) -#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8) +#define STM32_RCC_APB1ENR2_LPUART1EN BIT(0) +#define STM32_RCC_APB1ENR2_I2C4EN BIT(1) +#define STM32_RCC_APB1ENR2_UPCD1EN BIT(8) /* --- RCC APB2ENR Bit Definitions --- */ -#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0) -#define STM32_RCC_APB2ENR_TIM1 BIT(11) -#define STM32_RCC_APB2ENR_SPI1EN BIT(12) -#define STM32_RCC_APB2ENR_TIM8 BIT(13) -#define STM32_RCC_APB2ENR_USART1 BIT(14) -#define STM32_RCC_APB2ENR_SPI4EN BIT(15) -#define STM32_RCC_APB2ENR_TIM15 BIT(16) -#define STM32_RCC_APB2ENR_TIM16 BIT(17) -#define STM32_RCC_APB2ENR_TIM17 BIT(18) -#define STM32_RCC_APB2ENR_TIM20 BIT(20) - -#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1 +#define STM32_RCC_APB2ENR_SYSCFGEN BIT(0) +#define STM32_RCC_APB2ENR_TIM1 BIT(11) +#define STM32_RCC_APB2ENR_SPI1EN BIT(12) +#define STM32_RCC_APB2ENR_TIM8 BIT(13) +#define STM32_RCC_APB2ENR_USART1 BIT(14) +#define STM32_RCC_APB2ENR_SPI4EN BIT(15) +#define STM32_RCC_APB2ENR_TIM15 BIT(16) +#define STM32_RCC_APB2ENR_TIM16 BIT(17) +#define STM32_RCC_APB2ENR_TIM17 BIT(18) +#define STM32_RCC_APB2ENR_TIM20 BIT(20) + +#define STM32_RCC_PB2_USART1 STM32_RCC_APB2ENR_USART1 /* gpio.c needs STM32_RCC_SYSCFGEN */ #define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN /* --- RCC APB1RSTR1 Bit Definitions --- */ -#define STM32_RCC_APB1RSTR1_USB_RST BIT(23) -#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1 -#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST +#define STM32_RCC_APB1RSTR1_USB_RST BIT(23) +#define STM32_RCC_APB1RSTR STM32_RCC_APB1RSTR1 +#define STM32_RCC_PB1_USB STM32_RCC_APB1RSTR1_USB_RST /* --- RCC CSR Bit Definitions --- */ -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) /* --- RCC CCIPR Bit Definitions --- */ -#define STM32_RCC_CCIPR_UART_SYSCLK 0x1 -#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0 -#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_UART_SYSCLK 0x1 +#define STM32_RCC_CCIPR_USART1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_USART1SEL_SHIFT 0 +#define STM32_RCC_CCIPR_LPUART1SEL_MASK 0x3 #define STM32_RCC_CCIPR_LPUART1SEL_SHIFT 10 -#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12 -#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14 -#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16 +#define STM32_RCC_CCIPR_I2C1SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C1SEL_SHIFT 12 +#define STM32_RCC_CCIPR_I2C2SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C2SEL_SHIFT 14 +#define STM32_RCC_CCIPR_I2C3SEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2C3SEL_SHIFT 16 -#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3 +#define STM32_RCC_CCIPR2_I2C4SEL_MASK 0x3 -#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3 +#define STM32_RCC_CCIPR_I2CNSEL_MASK 0x3 #define STM32_RCC_CCIPR_I2CNSEL_SHIFT(n) (STM32_RCC_CCIPR_I2C1SEL_SHIFT + n * 2) -#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2 +#define STM32_RCC_CCIPR_I2CNSEL_HSI 0x2 /* --- RCC CRRCR Bit Definitions */ -#define RCC_CRRCR_HSI48O BIT(0) -#define RCC_CRRCR_HSIRDY BIT(1) +#define RCC_CRRCR_HSI48O BIT(0) +#define RCC_CRRCR_HSIRDY BIT(1) /* Reset causes definitions */ /* * Reset causes in RCC CSR register. The generic names are required */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define STM32_RCC_CSR_RMVF BIT(24) -#define STM32_RCC_CSR_BORRS BIT(25) -#define STM32_RCC_CSR_PIN BIT(26) -#define STM32_RCC_CSR_POR BIT(27) -#define STM32_RCC_CSR_SFT BIT(28) -#define STM32_RCC_CSR_IWDG BIT(29) -#define STM32_RCC_CSR_WWDG BIT(30) -#define STM32_RCC_CSR_LPWR BIT(31) - - -#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | \ - STM32_RCC_CSR_IWDG) -#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT -#define RESET_CAUSE_POR STM32_RCC_CSR_POR -#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN -#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF -#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | \ - STM32_RCC_CSR_BORRS) +#define STM32_RCC_CSR_RMVF BIT(24) +#define STM32_RCC_CSR_BORRS BIT(25) +#define STM32_RCC_CSR_PIN BIT(26) +#define STM32_RCC_CSR_POR BIT(27) +#define STM32_RCC_CSR_SFT BIT(28) +#define STM32_RCC_CSR_IWDG BIT(29) +#define STM32_RCC_CSR_WWDG BIT(30) +#define STM32_RCC_CSR_LPWR BIT(31) + +#define RESET_CAUSE_WDG (STM32_RCC_CSR_WWDG | STM32_RCC_CSR_IWDG) +#define RESET_CAUSE_SFT STM32_RCC_CSR_SFT +#define RESET_CAUSE_POR STM32_RCC_CSR_POR +#define RESET_CAUSE_PIN STM32_RCC_CSR_PIN +#define RESET_CAUSE_RMVF STM32_RCC_CSR_RMVF +#define RESET_CAUSE_OTHER (STM32_RCC_CSR_LPWR | STM32_RCC_CSR_BORRS) /* Power cause in PWR CSR register */ -#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14) -#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_SCR_CSBF BIT(8) -#define STM32_PWR_SR1_SBF BIT(8) +#define STM32_PWR_CR1 REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x08) +#define STM32_PWR_CR4 REG32(STM32_PWR_BASE + 0x0C) +#define STM32_PWR_SR1 REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_SR2 REG32(STM32_PWR_BASE + 0x14) +#define STM32_PWR_SCR REG32(STM32_PWR_BASE + 0x18) +#define STM32_PWR_SCR_CSBF BIT(8) +#define STM32_PWR_SR1_SBF BIT(8) #define STM32_PWR_RESET_CAUSE STM32_PWR_SR1 -#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF +#define RESET_CAUSE_SBF STM32_PWR_SR1_SBF #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR -#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF +#define RESET_CAUSE_SBF_CLR STM32_PWR_SCR_CSBF -#define STM32_PWR_CR1_DBP BIT(8) +#define STM32_PWR_CR1_DBP BIT(8) -#define STM32_PWR_CR3_UCPD1_STDBY BIT(13) -#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14) +#define STM32_PWR_CR3_UCPD1_STDBY BIT(13) +#define STM32_PWR_CR3_UCPD1_DBDIS BIT(14) /* --- System Config Registers --- */ -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) -#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_SYSCFG_CMPCR REG32(STM32_SYSCFG_BASE + 0x20) +#define STM32_SYSCFG_CFGR REG32(STM32_SYSCFG_BASE + 0x2C) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18) - - -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38) - -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48) -#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x18) + +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_CALR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_SHIFTR REG32(STM32_RTC_BASE + 0x2C) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TSSSR REG32(STM32_RTC_BASE + 0x38) + +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x48) +#define STM32_RTC_ALRMBSSR REG32(STM32_RTC_BASE + 0x44) /* --- RTC CR Bit Definitions --- */ -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) /* --- RTC ICSR Bit Definitions --- */ -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) /* --- RTC PRER Bit Definitions --- */ -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) - +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) /* --- Tamper and Backup --- */ -#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n)) -#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n) -#define STM32_BKP_BYTES 64 - +#define STM32_TAMP_BKPxR(n) REG32(STM32_TAMP_BASE + 0x100 + 4 * (n)) +#define STM32_BKP_DATA(n) STM32_TAMP_BKPxR(n) +#define STM32_BKP_BYTES 64 /* --- SPI --- */ @@ -877,223 +851,222 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) +#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- DBGMCU CR Bit Definitions --- */ -#define STM32_DBGMCU_CR_SLEEP BIT(0) -#define STM32_DBGMCU_CR_STOP BIT(1) -#define STM32_DBGMCU_CR_STBY BIT(2) -#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5)|BIT(6)|BIT(7)) -#define STM32_DBGMCU_CR_TRACE_EN BIT(5) -#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) -#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6)|BIT(7)) +#define STM32_DBGMCU_CR_SLEEP BIT(0) +#define STM32_DBGMCU_CR_STOP BIT(1) +#define STM32_DBGMCU_CR_STBY BIT(2) +#define STM32_DBGMCU_CR_TRACE_MASK (BIT(5) | BIT(6) | BIT(7)) +#define STM32_DBGMCU_CR_TRACE_EN BIT(5) +#define STM32_DBGMCU_CR_TRACE_MODE_ASYNC 0 +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC1 BIT(6) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC2 BIT(7) +#define STM32_DBGMCU_CR_TRACE_MODE_SYNC4 (BIT(6) | BIT(7)) /* --- DBGMCU APB1FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) -#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) -#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) -#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) -#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) -#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) -#define STM32_DBGMCU_APB1FZ_RTC BIT(10) -#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) -#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) -#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) -#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) -#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30) +#define STM32_DBGMCU_APB1FZ_TIM2 BIT(0) +#define STM32_DBGMCU_APB1FZ_TIM3 BIT(1) +#define STM32_DBGMCU_APB1FZ_TIM4 BIT(2) +#define STM32_DBGMCU_APB1FZ_TIM5 BIT(3) +#define STM32_DBGMCU_APB1FZ_TIM6 BIT(4) +#define STM32_DBGMCU_APB1FZ_TIM7 BIT(5) +#define STM32_DBGMCU_APB1FZ_RTC BIT(10) +#define STM32_DBGMCU_APB1FZ_WWDG BIT(11) +#define STM32_DBGMCU_APB1FZ_IWDG BIT(12) +#define STM32_DBGMCU_APB1FZ_I2C1_SMBUS_TIMEOUT BIT(21) +#define STM32_DBGMCU_APB1FZ_I2C2_SMBUS_TIMEOUT BIT(22) +#define STM32_DBGMCU_APB1FZ_I2C3_SMBUS_TIMEOUT BIT(30) /* --- DBGMCU APB2FZ Bit Definitions --- */ -#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11) -#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13) -#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16) -#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17) -#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18) -#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20) +#define STM32_DBGMCU_APB2FZ_TIM1 BIT(11) +#define STM32_DBGMCU_APB2FZ_TIM8 BIT(13) +#define STM32_DBGMCU_APB2FZ_TIM15 BIT(16) +#define STM32_DBGMCU_APB2FZ_TIM16 BIT(17) +#define STM32_DBGMCU_APB2FZ_TIM17 BIT(18) +#define STM32_DBGMCU_APB2FZ_TIM20 BIT(20) /* --- Flash --- */ -#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off)) -#define STM32_FLASH_ACR STM32_FLASH_REG(0x00) -#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04) -#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08) -#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c) -#define STM32_FLASH_SR STM32_FLASH_REG(0x10) -#define STM32_FLASH_CR STM32_FLASH_REG(0x14) -#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18) +#define STM32_FLASH_REG(off) REG32(STM32_FLASH_REGS_BASE + (off)) +#define STM32_FLASH_ACR STM32_FLASH_REG(0x00) +#define STM32_FLASH_PDKEYR STM32_FLASH_REG(0x04) +#define STM32_FLASH_KEYR STM32_FLASH_REG(0x08) +#define STM32_FLASH_OPTKEYR STM32_FLASH_REG(0x0c) +#define STM32_FLASH_SR STM32_FLASH_REG(0x10) +#define STM32_FLASH_CR STM32_FLASH_REG(0x14) +#define STM32_FLASH_ECCR STM32_FLASH_REG(0x18) /* * Bank 1 Option Byte Copy Registers. These registers are loaded from the option * bytes location in flash at reset, assuming that option byte loading has not * been disabled. */ -#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20) -#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24) -#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28) -#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C) -#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30) +#define STM32_FLASH_OPTR STM32_FLASH_REG(0x20) +#define STM32_FLASH_PCROP1SR STM32_FLASH_REG(0x24) +#define STM32_FLASH_PCROP1ER STM32_FLASH_REG(0x28) +#define STM32_FLASH_WRP1AR STM32_FLASH_REG(0x2C) +#define STM32_FLASH_WRP1BR STM32_FLASH_REG(0x30) /* * Bank 2 Option Byte Copy Registers. These will only exist for category 3 * devices. */ -#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44) -#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48) -#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C) -#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50) +#define STM32_FLASH_PCROP2SR STM32_FLASH_REG(0x44) +#define STM32_FLASH_PCROP2ER STM32_FLASH_REG(0x48) +#define STM32_FLASH_WRP2AR STM32_FLASH_REG(0x4C) +#define STM32_FLASH_WRP2BR STM32_FLASH_REG(0x50) -#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70) -#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74) +#define STM32_FLASH_SEC_SIZE1 STM32_FLASH_REG(0x70) +#define STM32_FLASH_SEC_SIZE2 STM32_FLASH_REG(0x74) /* --- FLASH CR Bit Definitions --- */ #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_PRFTEN BIT(8) -#define STM32_FLASH_ACR_ICEN BIT(9) -#define STM32_FLASH_ACR_DCEN BIT(10) -#define STM32_FLASH_ACR_ICRST BIT(11) -#define STM32_FLASH_ACR_DCRST BIT(12) +#define STM32_FLASH_ACR_LATENCY_MASK (0xf << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_PRFTEN BIT(8) +#define STM32_FLASH_ACR_ICEN BIT(9) +#define STM32_FLASH_ACR_DCEN BIT(10) +#define STM32_FLASH_ACR_ICRST BIT(11) +#define STM32_FLASH_ACR_DCRST BIT(12) /* --- FLASH KEYR Bit Definitions --- */ -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB /* --- FLASH OPTKEYR Bit Definitions --- */ -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F /* --- FLASH SR Bit Definitions --- */ -#define FLASH_SR_BUSY BIT(16) -#define FLASH_SR_OPTVERR BIT(15) -#define FLASH_SR_RDERR BIT(14) -#define FLASH_SR_FASTERR BIT(9) -#define FLASH_SR_MISERR BIT(8) -#define FLASH_SR_PGSERR BIT(7) -#define FLASH_SR_SIZERR BIT(6) -#define FLASH_SR_PGAERR BIT(5) -#define FLASH_SR_WRPERR BIT(4) -#define FLASH_SR_PROGERR BIT(3) -#define FLASH_SR_OPERR BIT(1) -#define FLASH_SR_ERR_MASK (FLASH_SR_OPTVERR | FLASH_SR_RDERR | \ - FLASH_SR_FASTERR | FLASH_SR_PGSERR | \ - FLASH_SR_SIZERR | FLASH_SR_PGAERR | \ - FLASH_SR_WRPERR | FLASH_SR_PROGERR | \ - FLASH_SR_OPERR) +#define FLASH_SR_BUSY BIT(16) +#define FLASH_SR_OPTVERR BIT(15) +#define FLASH_SR_RDERR BIT(14) +#define FLASH_SR_FASTERR BIT(9) +#define FLASH_SR_MISERR BIT(8) +#define FLASH_SR_PGSERR BIT(7) +#define FLASH_SR_SIZERR BIT(6) +#define FLASH_SR_PGAERR BIT(5) +#define FLASH_SR_WRPERR BIT(4) +#define FLASH_SR_PROGERR BIT(3) +#define FLASH_SR_OPERR BIT(1) +#define FLASH_SR_ERR_MASK \ + (FLASH_SR_OPTVERR | FLASH_SR_RDERR | FLASH_SR_FASTERR | \ + FLASH_SR_PGSERR | FLASH_SR_SIZERR | FLASH_SR_PGAERR | \ + FLASH_SR_WRPERR | FLASH_SR_PROGERR | FLASH_SR_OPERR) /* --- FLASH CR Bit Definitions --- */ -#define FLASH_CR_PG BIT(0) -#define FLASH_CR_PER BIT(1) -#define FLASH_CR_STRT BIT(16) -#define FLASH_CR_OPTSTRT BIT(17) -#define FLASH_CR_OBL_LAUNCH BIT(27) -#define FLASH_CR_OPTLOCK BIT(30) -#define FLASH_CR_LOCK BIT(31) -#define FLASH_CR_PNB(sec) (((sec) & 0x7f) << 3) -#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f) - -#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2) +#define FLASH_CR_PG BIT(0) +#define FLASH_CR_PER BIT(1) +#define FLASH_CR_STRT BIT(16) +#define FLASH_CR_OPTSTRT BIT(17) +#define FLASH_CR_OBL_LAUNCH BIT(27) +#define FLASH_CR_OPTLOCK BIT(30) +#define FLASH_CR_LOCK BIT(31) +#define FLASH_CR_PNB(sec) (((sec)&0x7f) << 3) +#define FLASH_CR_PNB_MASK FLASH_CR_PNB(0x7f) + +#define STM32_FLASH_MIN_WRITE_SIZE (CONFIG_FLASH_WRITE_SIZE * 2) /* --- FLASH Option bytes --- */ -#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00) -#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08) -#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10) -#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18) -#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20) -#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28) - -#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00) -#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08) -#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10) -#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18) -#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20) -#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28) +#define STM32_OPTB_USER_RDP REG32(STM32_OPTB_BANK1_BASE + 0x00) +#define STM32_OPTB_PCROP1_START REG32(STM32_OPTB_BANK1_BASE + 0x08) +#define STM32_OPTB_PCROP1_END REG32(STM32_OPTB_BANK1_BASE + 0x10) +#define STM32_OPTB_WRP1AR REG32(STM32_OPTB_BANK1_BASE + 0x18) +#define STM32_OPTB_WRP1BR REG32(STM32_OPTB_BANK1_BASE + 0x20) +#define STM32_OPTB_SECURE1_MEM REG32(STM32_OPTB_BANK1_BASE + 0x28) + +#define STM32_OPTB_UNUSED REG32(STM32_OPTB_BANK2_BASE + 0x00) +#define STM32_OPTB_PCROP2_START REG32(STM32_OPTB_BANK2_BASE + 0x08) +#define STM32_OPTB_PCROP2_END REG32(STM32_OPTB_BANK2_BASE + 0x10) +#define STM32_OPTB_WRP2AR REG32(STM32_OPTB_BANK2_BASE + 0x18) +#define STM32_OPTB_WRP2BR REG32(STM32_OPTB_BANK2_BASE + 0x20) +#define STM32_OPTB_SECURE2_MEM REG32(STM32_OPTB_BANK2_BASE + 0x28) /* Read option bytes from flash memory for Bank 1 */ -#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8)) -#define STM32_OPTB_BANK1_COMP_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n) * 8) + 0x4) -#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8)) -#define STM32_OPTB_BANK2_COMP_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n) * 8) + 0x4) - -#define STM32_OPTB_USER_DBANK BIT(22) -#define STM32_OPTB_USER_nBOOT1 BIT(23) -#define STM32_OPTB_USER_nSWBOOT0 BIT(26) -#define STM32_OPTB_USER_nBOOT0 BIT(27) +#define STM32_OPTB_BANK1_READ(n) REG32(STM32_OPTB_BANK1_BASE + ((n)*8)) +#define STM32_OPTB_BANK1_COMP_READ(n) \ + REG32(STM32_OPTB_BANK1_BASE + ((n)*8) + 0x4) +#define STM32_OPTB_BANK2_READ(n) REG32(STM32_OPTB_BANK2_BASE + ((n)*8)) +#define STM32_OPTB_BANK2_COMP_READ(n) \ + REG32(STM32_OPTB_BANK2_BASE + ((n)*8) + 0x4) + +#define STM32_OPTB_USER_DBANK BIT(22) +#define STM32_OPTB_USER_nBOOT1 BIT(23) +#define STM32_OPTB_USER_nSWBOOT0 BIT(26) +#define STM32_OPTB_USER_nBOOT0 BIT(27) #define STM32_OPTB_ENTRY_NUM 6 /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) #define EXTI_RTC_ALR_EVENT BIT(17) /* --- ADC --- */ -#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4) - +#define STM32_ADC_ISR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_IER REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_CFGR REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_CFGR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC_TR1 REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_TR2 REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_TR3 REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_JOFR(n) REG32(STM32_ADC1_BASE + 0x14 + ((n)&3) * 4) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x30 + ((n)&3) * 4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x80 + ((n)&3) * 4) /* --- ADC CR Bit Definitions --- */ -#define STM32_ADC_CR_ADEN BIT(0) -#define STM32_ADC_CR_ADSTART BIT(2) -#define STM32_ADC_CR_ADVREGEN BIT(28) -#define STM32_ADC_CR_CAL BIT(31) +#define STM32_ADC_CR_ADEN BIT(0) +#define STM32_ADC_CR_ADSTART BIT(2) +#define STM32_ADC_CR_ADVREGEN BIT(28) +#define STM32_ADC_CR_CAL BIT(31) -#define STM32_ADC_CFGR_CONT BIT(13) -#define STM32_ADC_CR2_ALIGN BIT(15) +#define STM32_ADC_CFGR_CONT BIT(13) +#define STM32_ADC_CR2_ALIGN BIT(15) /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -1175,11 +1148,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -1190,8 +1163,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -1200,78 +1173,77 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA2_REGS ((stm32_dma_regs_t *)STM32_DMA2_BASE) #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CSELR(channel) \ - REG32(((channel) < STM32_DMAC_PER_CTLR ? \ - STM32_DMA1_BASE : STM32_DMA2_BASE) + 0xA8) +#define STM32_DMA_CSELR(channel) \ + REG32(((channel) < STM32_DMAC_PER_CTLR ? STM32_DMA1_BASE : \ + STM32_DMA2_BASE) + \ + 0xA8) /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX. */ /* DMAMUX registers */ -#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) -#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) -#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) -#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) -#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) -#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) +#define STM32_DMAMUX_CxCR(x) REG32(STM32_DMAMUX_BASE + 4 * (x)) +#define STM32_DMAMUX_CSR REG32(STM32_DMAMUX_BASE + 0x80) +#define STM32_DMAMUX_CFR REG32(STM32_DMAMUX_BASE + 0x84) +#define STM32_DMAMUX_RGxCR(x) REG32(STM32_DMAMUX_BASE + 0x100 + 4 * (x)) +#define STM32_DMAMUX_RGSR REG32(STM32_DMAMUX_BASE + 0x140) +#define STM32_DMAMUX_RGCFR REG32(STM32_DMAMUX_BASE + 0x144) enum dmamux1_request { DMAMUX_REQ_ADC1 = 5, @@ -1378,41 +1350,41 @@ enum dmamux1_request { #define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- USB --- */ -#define STM32_USB_BCDR_DPPU BIT(15) +#define STM32_USB_BCDR_DPPU BIT(15) /* --- USB Endpoint bit definitions --- */ -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 @@ -1422,31 +1394,30 @@ enum dmamux1_request { #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- RNG CR Bit Definitions --- */ -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) /* --- RNG SR_DRDY Bit Definitions --- */ -#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_SR_DRDY BIT(0) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From a002187fd09c917454a9a6cdaf03096df80c6dcb Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:47 -0600 Subject: common/charge_manager.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I945f776e68aa9fb65307693c7307ac34139d3950 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729614 Reviewed-by: Jeremy Bettis --- common/charge_manager.c | 234 +++++++++++++++++++++++------------------------- 1 file changed, 111 insertions(+), 123 deletions(-) diff --git a/common/charge_manager.c b/common/charge_manager.c index 8895be9cf2..cad4123cb8 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -30,13 +30,13 @@ #error Mock defined HAS_MOCK_CHARGE_MANAGER #endif -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) #define POWER(charge_port) ((charge_port.current) * (charge_port.voltage)) /* Timeout for delayed override power swap, allow for 500ms extra */ -#define POWER_SWAP_TIMEOUT (PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + \ - PD_T_SAFE_0V + 500 * MSEC) +#define POWER_SWAP_TIMEOUT \ + (PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON + PD_T_SAFE_0V + 500 * MSEC) /* * Default charge supplier priority @@ -79,9 +79,7 @@ __overridable const int supplier_priority[] = { }; BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT); -const char *charge_supplier_name[] = { - CHARGE_SUPPLIER_NAME -}; +const char *charge_supplier_name[] = { CHARGE_SUPPLIER_NAME }; BUILD_ASSERT(ARRAY_SIZE(charge_supplier_name) == CHARGE_SUPPLIER_COUNT); /* Keep track of available charge for each charge port. */ @@ -209,9 +207,8 @@ static int is_connected(int port) */ static int charge_manager_spoof_dualrole_capability(void) { - return (system_get_image_copy() == EC_IMAGE_RO && - system_is_locked()) || !left_safe_mode; - + return (system_get_image_copy() == EC_IMAGE_RO && system_is_locked()) || + !left_safe_mode; } #endif /* !CONFIG_CHARGE_MANAGER_DRP_CHARGING */ @@ -262,9 +259,9 @@ static int charge_manager_is_seeded(void) if (!is_valid_port(j)) continue; if (available_charge[i][j].current == - CHARGE_CURRENT_UNINITIALIZED || + CHARGE_CURRENT_UNINITIALIZED || available_charge[i][j].voltage == - CHARGE_VOLTAGE_UNINITIALIZED) + CHARGE_VOLTAGE_UNINITIALIZED) return 0; } } @@ -345,8 +342,8 @@ static enum charge_supplier get_current_supplier(int port) return supplier; } -static enum usb_power_roles get_current_power_role(int port, - enum charge_supplier supplier) +static enum usb_power_roles +get_current_power_role(int port, enum charge_supplier supplier) { enum usb_power_roles role; if (charge_port == port) @@ -402,8 +399,8 @@ static int get_vbus_voltage(int port, enum usb_power_roles current_role) int charge_manager_get_vbus_voltage(int port) { - return get_vbus_voltage(port, get_current_power_role(port, - get_current_supplier(port))); + return get_vbus_voltage( + port, get_current_power_role(port, get_current_supplier(port))); } #ifdef CONFIG_CMD_VBUS @@ -432,8 +429,7 @@ static int command_vbus(int argc, char **argv) return EC_SUCCESS; } -DECLARE_CONSOLE_COMMAND(vbus, command_vbus, - "[port]", +DECLARE_CONSOLE_COMMAND(vbus, command_vbus, "[port]", "Print VBUS & VSYS of the given port"); #endif @@ -443,8 +439,9 @@ DECLARE_CONSOLE_COMMAND(vbus, command_vbus, * @param port Charge port. * @param r USB PD power info to be updated. */ -static void charge_manager_fill_power_info(int port, - struct ec_response_usb_pd_power_info *r) +static void +charge_manager_fill_power_info(int port, + struct ec_response_usb_pd_power_info *r) { enum charge_supplier sup = get_current_supplier(port); @@ -527,7 +524,7 @@ static void charge_manager_fill_power_info(int port, } if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled() && - sup == CHARGE_SUPPLIER_PD) { + sup == CHARGE_SUPPLIER_PD) { /* * Returns the maximum power the system can request when * DPS enabled. This is to prevent the system think it's @@ -556,15 +553,15 @@ static void charge_manager_fill_power_info(int port, * lose power again). */ #ifdef CONFIG_BATTERY - if (get_time().val < registration_time[port].val + - CHARGE_DETECT_DELAY) + if (get_time().val < + registration_time[port].val + CHARGE_DETECT_DELAY) r->type = USB_CHG_TYPE_UNKNOWN; #endif #if defined(HAS_TASK_CHG_RAMP) || defined(CONFIG_CHARGE_RAMP_HW) /* Read ramped current if active charging port */ - use_ramp_current = - (charge_port == port) && chg_ramp_allowed(port, sup); + use_ramp_current = (charge_port == port) && + chg_ramp_allowed(port, sup); #else use_ramp_current = 0; #endif @@ -581,9 +578,10 @@ static void charge_manager_fill_power_info(int port, * If ramp is not allowed, max current is just the * available charge current. */ - r->meas.current_max = chg_ramp_is_stable() ? - r->meas.current_lim : chg_ramp_max(port, sup, - max_ma); + r->meas.current_max = + chg_ramp_is_stable() ? + r->meas.current_lim : + chg_ramp_max(port, sup, max_ma); } else { r->meas.current_max = r->meas.current_lim = max_ma; @@ -618,8 +616,8 @@ void charge_manager_save_log(int port) (pinfo.dualrole ? CHARGE_FLAGS_DUAL_ROLE : 0); pd_log_event(PD_EVENT_MCU_CHARGE, - PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)), - flags, &pinfo.meas); + PD_LOG_PORT_SIZE(port, sizeof(pinfo.meas)), flags, + &pinfo.meas); } #endif /* CONFIG_USB_PD_LOGGING */ @@ -680,7 +678,6 @@ static void charge_manager_get_best_charge_port(int *new_port, /* Skip port selection on OVERRIDE_DONT_CHARGE. */ if (override_port != OVERRIDE_DONT_CHARGE) { - /* * Charge supplier selection logic: * 1. Prefer DPS charge port. @@ -710,8 +707,7 @@ static void charge_manager_get_best_charge_port(int *new_port, * charge on another override port. */ if (override_port != OVERRIDE_OFF && - override_port == port && - override_port != j) + override_port == port && override_port != j) continue; #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING @@ -736,31 +732,36 @@ static void charge_manager_get_best_charge_port(int *new_port, supplier = i; port = j; break; - /* Select if no supplier chosen yet. */ + /* Select if no supplier chosen yet. */ } else if (supplier == CHARGE_SUPPLIER_NONE || - /* ..or if supplier priority is higher. */ - supplier_priority[i] < - supplier_priority[supplier] || - /* ..or if this is our override port. */ - (j == override_port && - port != override_port) || - /* ..or if priority is tied and.. */ - (supplier_priority[i] == - supplier_priority[supplier] && - /* candidate port can supply more power or.. */ - (candidate_port_power > best_port_power || - /* - * candidate port is the active port and can - * supply the same amount of power. - */ - (candidate_port_power == best_port_power && - charge_port == j)))) { + /* ..or if supplier priority is + higher. */ + supplier_priority[i] < + supplier_priority[supplier] || + /* ..or if this is our override port. + */ + (j == override_port && + port != override_port) || + /* ..or if priority is tied and.. */ + (supplier_priority[i] == + supplier_priority[supplier] && + /* candidate port can supply more + power or.. */ + (candidate_port_power > + best_port_power || + /* + * candidate port is the active + * port and can supply the same + * amount of power. + */ + (candidate_port_power == + best_port_power && + charge_port == j)))) { supplier = i; port = j; best_port_power = candidate_port_power; } } - } #ifdef CONFIG_BATTERY @@ -768,8 +769,7 @@ static void charge_manager_get_best_charge_port(int *new_port, * if no battery present then retain same charge port * and charge supplier to avoid the port switching */ - if (charge_port != CHARGE_SUPPLIER_NONE && - charge_port != port && + if (charge_port != CHARGE_SUPPLIER_NONE && charge_port != port && (battery_is_present() == BP_NO || (battery_is_present() == BP_YES && battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL))) { @@ -812,9 +812,8 @@ static void charge_manager_refresh(void) * the port, for example, if the port has become a charge * source. */ - if (active_charge_port_initialized && - new_port == charge_port && - new_supplier == charge_supplier) + if (active_charge_port_initialized && new_port == charge_port && + new_supplier == charge_supplier) break; /* @@ -874,8 +873,8 @@ static void charge_manager_refresh(void) /* Enforce port charge ceiling. */ ceil = charge_manager_get_ceil(new_port); if (left_safe_mode && ceil != CHARGE_CEIL_NONE) - new_charge_current = MIN(ceil, - new_charge_current_uncapped); + new_charge_current = + MIN(ceil, new_charge_current_uncapped); else new_charge_current = new_charge_current_uncapped; @@ -896,19 +895,19 @@ static void charge_manager_refresh(void) if (new_port != charge_port || new_charge_current != charge_current || new_supplier != charge_supplier) { #ifdef HAS_TASK_CHG_RAMP - chg_ramp_charge_supplier_change( - new_port, new_supplier, new_charge_current, - registration_time[new_port], - new_charge_voltage); + chg_ramp_charge_supplier_change(new_port, new_supplier, + new_charge_current, + registration_time[new_port], + new_charge_voltage); #else #ifdef CONFIG_CHARGE_RAMP_HW /* Enable or disable charge ramp */ charger_set_hw_ramp(chg_ramp_allowed(new_port, new_supplier)); #endif board_set_charge_limit(new_port, new_supplier, - new_charge_current, - new_charge_current_uncapped, - new_charge_voltage); + new_charge_current, + new_charge_current_uncapped, + new_charge_voltage); #endif /* HAS_TASK_CHG_RAMP */ power_changed = 1; @@ -976,9 +975,9 @@ static void charge_manager_refresh(void) if (is_pd_port(updated_new_port)) { /* Check if we can get requested voltage/current */ if ((IS_ENABLED(CONFIG_USB_PD_TCPMV1) && - IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) || + IS_ENABLED(CONFIG_USB_PD_DUAL_ROLE)) || (IS_ENABLED(CONFIG_USB_PD_TCPMV2) && - IS_ENABLED(CONFIG_USB_PE_SM))) { + IS_ENABLED(CONFIG_USB_PE_SM))) { uint32_t pdo; uint32_t max_voltage; uint32_t max_current; @@ -989,9 +988,9 @@ static void charge_manager_refresh(void) * than requested. If yes, send new power request */ if (pd_get_requested_voltage(updated_new_port) != - charge_voltage || + charge_voltage || pd_get_requested_current(updated_new_port) != - charge_current_uncapped) + charge_current_uncapped) new_req = true; if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled()) { @@ -1063,8 +1062,7 @@ DECLARE_DEFERRED(charger_detect_debounced); * @param charge Charge port current / voltage. */ static void charge_manager_make_change(enum charge_manager_change_type change, - int supplier, - int port, + int supplier, int port, const struct charge_port_info *charge) { int i; @@ -1080,9 +1078,8 @@ static void charge_manager_make_change(enum charge_manager_change_type change, case CHANGE_CHARGE: /* Ignore changes where charge is identical */ if (available_charge[supplier][port].current == - charge->current && - available_charge[supplier][port].voltage == - charge->voltage) + charge->current && + available_charge[supplier][port].voltage == charge->voltage) return; if (charge->current > 0 && available_charge[supplier][port].current == 0) @@ -1116,12 +1113,13 @@ static void charge_manager_make_change(enum charge_manager_change_type change, } /* Remove override when a charger is plugged */ - if (clear_override && override_port != port + if (clear_override && + override_port != port #ifndef CONFIG_CHARGE_MANAGER_DRP_CHARGING /* only remove override when it's a dedicated charger */ && dualrole_capability[port] == CAP_DEDICATED #endif - ) { + ) { override_port = OVERRIDE_OFF; if (delayed_override_port != OVERRIDE_OFF) { delayed_override_port = OVERRIDE_OFF; @@ -1149,7 +1147,7 @@ static void charge_manager_make_change(enum charge_manager_change_type change, /* * If we have a charge on our delayed override port within * the deadline, make it our override port. - */ + */ if (port == delayed_override_port && charge->current > 0 && is_sink(delayed_override_port) && get_time().val < delayed_override_deadline.val) { @@ -1234,11 +1232,10 @@ void typec_set_input_current_limit(int port, typec_current_t max_ma, NULL); } -void charge_manager_update_charge(int supplier, - int port, +void charge_manager_update_charge(int supplier, int port, const struct charge_port_info *charge) { - struct charge_port_info zero = {0}; + struct charge_port_info zero = { 0 }; if (!charge) charge = &zero; charge_manager_make_change(CHANGE_CHARGE, supplier, port, charge); @@ -1320,8 +1317,8 @@ int charge_manager_set_override(int port) if (override_port != port) { override_port = port; if (charge_manager_is_seeded()) - hook_call_deferred( - &charge_manager_refresh_data, 0); + hook_call_deferred(&charge_manager_refresh_data, + 0); } } /* @@ -1329,13 +1326,13 @@ int charge_manager_set_override(int port) * power swap and set the delayed override for swap completion. */ else if (!is_sink(port) && dualrole_capability[port] == CAP_DUALROLE) { - delayed_override_deadline.val = get_time().val + - POWER_SWAP_TIMEOUT; + delayed_override_deadline.val = + get_time().val + POWER_SWAP_TIMEOUT; delayed_override_port = port; hook_call_deferred(&charge_override_timeout_data, POWER_SWAP_TIMEOUT); pd_request_power_swap(port); - /* Can't charge from requested port -- return error. */ + /* Can't charge from requested port -- return error. */ } else retval = EC_ERROR_INVAL; @@ -1393,7 +1390,7 @@ int charge_manager_get_power_limit_uw(void) /* Bitmap of ports used as power source */ static volatile uint32_t source_port_bitmap; -BUILD_ASSERT(sizeof(source_port_bitmap)*8 >= CONFIG_USB_PD_PORT_MAX_COUNT); +BUILD_ASSERT(sizeof(source_port_bitmap) * 8 >= CONFIG_USB_PD_PORT_MAX_COUNT); static inline int has_other_active_source(int port) { @@ -1424,7 +1421,7 @@ static int can_supply_max_current(int port) if (p == port) continue; if (source_port_rp[p] == - CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) + CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) return 0; } return 1; @@ -1450,8 +1447,8 @@ void charge_manager_source_port(int port, int enable) /* Set port limit according to policy */ for (p = 0; p < board_get_usb_pd_port_count(); p++) { rp = can_supply_max_current(p) ? - CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT : - CONFIG_USB_PD_PULLUP; + CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT : + CONFIG_USB_PD_PULLUP; source_port_rp[p] = rp; #ifdef CONFIG_USB_PD_LOGGING @@ -1503,8 +1500,7 @@ static enum ec_status hc_pd_power_info(struct host_cmd_handler_args *args) args->response_size = sizeof(*r); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO, - hc_pd_power_info, +DECLARE_HOST_COMMAND(EC_CMD_USB_PD_POWER_INFO, hc_pd_power_info, EC_VER_MASK(0)); static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args) @@ -1516,8 +1512,7 @@ static enum ec_status hc_charge_port_count(struct host_cmd_handler_args *args) return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT, - hc_charge_port_count, +DECLARE_HOST_COMMAND(EC_CMD_CHARGE_PORT_COUNT, hc_charge_port_count, EC_VER_MASK(0)); static enum ec_status @@ -1531,15 +1526,15 @@ hc_charge_port_override(struct host_cmd_handler_args *args) return EC_RES_INVALID_PARAM; return charge_manager_set_override(override_port) == EC_SUCCESS ? - EC_RES_SUCCESS : EC_RES_ERROR; + EC_RES_SUCCESS : + EC_RES_ERROR; } -DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE, - hc_charge_port_override, +DECLARE_HOST_COMMAND(EC_CMD_PD_CHARGE_PORT_OVERRIDE, hc_charge_port_override, EC_VER_MASK(0)); #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 -static enum ec_status hc_override_dedicated_charger_limit( - struct host_cmd_handler_args *args) +static enum ec_status +hc_override_dedicated_charger_limit(struct host_cmd_handler_args *args) { const struct ec_params_dedicated_charger_limit *p = args->params; struct charge_port_info ci = { @@ -1560,8 +1555,7 @@ static enum ec_status hc_override_dedicated_charger_limit( return EC_RES_SUCCESS; } DECLARE_HOST_COMMAND(EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, - hc_override_dedicated_charger_limit, - EC_VER_MASK(0)); + hc_override_dedicated_charger_limit, EC_VER_MASK(0)); #endif static int command_charge_port_override(int argc, char **argv) @@ -1578,12 +1572,12 @@ static int command_charge_port_override(int argc, char **argv) ret = charge_manager_set_override(port); } - ccprintf("Override: %d\n", (argc >= 2 && ret == EC_SUCCESS) ? - port : override_port); + ccprintf("Override: %d\n", + (argc >= 2 && ret == EC_SUCCESS) ? port : override_port); return ret; } -DECLARE_CONSOLE_COMMAND(chgoverride, command_charge_port_override, - "[port | -1 | -2]", +DECLARE_CONSOLE_COMMAND( + chgoverride, command_charge_port_override, "[port | -1 | -2]", "Force charging from a given port (-1 = off, -2 = disable charging)"); #ifdef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT @@ -1620,13 +1614,11 @@ hc_external_power_limit(struct host_cmd_handler_args *args) { const struct ec_params_external_power_limit_v1 *p = args->params; - charge_manager_set_external_power_limit(p->current_lim, - p->voltage_lim); + charge_manager_set_external_power_limit(p->current_lim, p->voltage_lim); return EC_RES_SUCCESS; } -DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT, - hc_external_power_limit, +DECLARE_HOST_COMMAND(EC_CMD_EXTERNAL_POWER_LIMIT, hc_external_power_limit, EC_VER_MASK(1)); static int command_external_power_limit(int argc, char **argv) @@ -1655,8 +1647,8 @@ static int command_external_power_limit(int argc, char **argv) return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(chglim, command_external_power_limit, - "[max_current (mA)] [max_voltage (mV)]", - "Set max charger current / voltage"); + "[max_current (mA)] [max_voltage (mV)]", + "Set max charger current / voltage"); #endif /* CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT */ #ifdef CONFIG_CMD_CHARGE_SUPPLIER_INFO @@ -1671,10 +1663,10 @@ static int charge_supplier_info(int argc, char **argv) port_printed = 0; for (s = 0; s < CHARGE_SUPPLIER_COUNT; s++) { if (available_charge[s][p].current == 0 && - available_charge[s][p].voltage == 0) + available_charge[s][p].voltage == 0) continue; if (charge_manager_get_active_charge_port() == p && - charge_manager_get_supplier() == s) + charge_manager_get_supplier() == s) ccprintf("*"); else ccprintf(" "); @@ -1685,8 +1677,7 @@ static int charge_supplier_info(int argc, char **argv) ccprintf(" "); } ccprintf("%-10s %4d %5dmA %5dmV\n", - charge_supplier_name[s], - supplier_priority[s], + charge_supplier_name[s], supplier_priority[s], available_charge[s][p].current, available_charge[s][p].voltage); } @@ -1697,25 +1688,22 @@ static int charge_supplier_info(int argc, char **argv) ccprintf("\n"); return 0; } -DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info, - NULL, "print chg supplier info"); +DECLARE_CONSOLE_COMMAND(chgsup, charge_supplier_info, NULL, + "print chg supplier info"); #endif -__overridable -int board_charge_port_is_sink(int port) +__overridable int board_charge_port_is_sink(int port) { return 1; } -__overridable -int board_charge_port_is_connected(int port) +__overridable int board_charge_port_is_connected(int port) { return 1; } -__overridable -void board_fill_source_power_info(int port, - struct ec_response_usb_pd_power_info *r) +__overridable void +board_fill_source_power_info(int port, struct ec_response_usb_pd_power_info *r) { r->meas.voltage_now = 0; r->meas.voltage_max = 0; -- cgit v1.2.1 From 5b0fda1b6239d71a9625ec485012d8dbffc33b0a Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Wed, 22 Jun 2022 11:05:42 -0600 Subject: zephyr:test: Add tests for EC_CMD_HOST_EVENT_CLEAR Validate EC_CMD_HOST_EVENT_CLEAR/_B BUG=b:236161288, b:236161216 BRANCH=none TEST=zmake test test-drivers Signed-off-by: Al Semjonovs Change-Id: I15afb442625190a7b1359c806aaec5d9c6526649 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3717918 Reviewed-by: Jeremy Bettis --- .../drivers/src/host_cmd/host_event_commands.c | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/zephyr/test/drivers/src/host_cmd/host_event_commands.c b/zephyr/test/drivers/src/host_cmd/host_event_commands.c index cbcc3dd2e8..48b4d1a059 100644 --- a/zephyr/test/drivers/src/host_cmd/host_event_commands.c +++ b/zephyr/test/drivers/src/host_cmd/host_event_commands.c @@ -186,3 +186,73 @@ ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_cmd) event_set[i].result, ret_val); } } + +enum ec_status host_event_mask_cmd_helper(uint32_t command, uint32_t mask, + struct ec_response_host_event_mask *r) +{ + enum ec_status ret_val; + + struct ec_params_host_event_mask params = { + .mask = mask, + }; + struct host_cmd_handler_args args = + BUILD_HOST_COMMAND(command, 0, *r, params); + + ret_val = host_command_process(&args); + + return ret_val; +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR clear host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear__cmd) +{ + enum ec_status ret_val; + host_event_t events; + host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + struct ec_response_host_event_mask response = { 0 }; + + host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY); + events = host_get_events(); + + zassert_true(events & mask, "events=0x%X", events); + + ret_val = host_event_mask_cmd_helper(EC_CMD_HOST_EVENT_CLEAR, mask, + &response); + + zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d", + EC_RES_SUCCESS, ret_val); + + events = host_get_events(); + zassert_false(events & mask, "events=0x%X", events); +} + +/** + * @brief TestPurpose: Verify EC_CMD_HOST_EVENT_CLEAR_B clear host command. + */ +ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_b_cmd) +{ + enum ec_status ret_val; + host_event_t events_b; + host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + + struct ec_response_host_event_mask response = { 0 }; + struct ec_response_host_event result = { 0 }; + + host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY); + + host_event_cmd_helper(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result); + events_b = result.value; + zassert_true(events_b & mask, "events_b=0x%X", events_b); + + ret_val = host_event_mask_cmd_helper(EC_CMD_HOST_EVENT_CLEAR_B, mask, + &response); + + zassert_equal(ret_val, EC_RES_SUCCESS, "Expected %d, returned %d", + EC_RES_SUCCESS, ret_val); + + host_event_cmd_helper(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result); + events_b = result.value; + zassert_false(events_b & mask, "events_b=0x%X", events_b); +} -- cgit v1.2.1 From 97604ddf8736038907352d0a586a26bb6ddec0d4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:02 -0600 Subject: common/onewire.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I431bab09fee768b6f0935faa3ceab2b88ce37f0b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749468 Reviewed-by: Jeremy Bettis --- common/onewire.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/common/onewire.c b/common/onewire.c index 254abffcaa..235a358257 100644 --- a/common/onewire.c +++ b/common/onewire.c @@ -18,8 +18,9 @@ */ #define T_RSTL 602 /* Reset low pulse; 600-960 us */ #define T_MSP 72 /* Presence detect sample time; 70-75 us */ -#define T_RSTH (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin \ - */ +#define T_RSTH \ + (68 + 260 + 5 + 2) /* Reset high; tPDHmax + tPDLmax + tRECmin \ + */ #define T_SLOT 70 /* Timeslot; >67 us */ #define T_W0L 63 /* Write 0 low; 62-120 us */ #define T_W1L 7 /* Write 1 low; 5-15 us */ -- cgit v1.2.1 From f526613a6059a5164415b59754ef9a4b23416e59 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 6 Jul 2022 11:50:02 -0700 Subject: Revert boringssl clang-format changes The clang-format commits changed symlinks to copies of the files, so there are duplicates of each file. This reverts the following commits: c9501c326e164dceab6c87da57fa96c224c57155 4006ab6004daf645f5112c63307090f96abe08de 3c0dfa12e5cd96dc798ae2b4523c89f2021301da 4e35122258a2958a06866404e703370efcbe7c31 662b592c868995287a82174e5ed84205fa2230e9 862eae94c19760820f710195197dfe827df5fac6 761db14ef422056e76515a2a38f848d5fb410cbb 3c0dfa12e5cd96dc798ae2b4523c89f2021301da BRANCH=none BUG=b:236386294 TEST=none Signed-off-by: Tom Hughes Change-Id: Ic428544700a240f26f2032936a8b7cbb00cb35e6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749638 Reviewed-by: Jack Rosenthal Reviewed-by: Jeremy Bettis --- common/aes-gcm.c | 921 +----------------------------------------- common/aes.c | 831 +------------------------------------- common/curve25519-generic.c | 945 +------------------------------------------- common/curve25519.c | 70 +--- include/aes-gcm.h | 142 +------ include/aes.h | 130 +----- include/curve25519.h | 69 +--- test/x25519.c | 197 +-------- 8 files changed, 8 insertions(+), 3297 deletions(-) mode change 100644 => 120000 common/aes-gcm.c mode change 100644 => 120000 common/aes.c mode change 100644 => 120000 common/curve25519-generic.c mode change 100644 => 120000 common/curve25519.c mode change 100644 => 120000 include/aes-gcm.h mode change 100644 => 120000 include/aes.h mode change 100644 => 120000 include/curve25519.h mode change 100644 => 120000 test/x25519.c diff --git a/common/aes-gcm.c b/common/aes-gcm.c deleted file mode 100644 index 33a0e34434..0000000000 --- a/common/aes-gcm.c +++ /dev/null @@ -1,920 +0,0 @@ -/* ==================================================================== - * Copyright (c) 2008 The OpenSSL Project. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * 3. All advertising materials mentioning features or use of this - * software must display the following acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" - * - * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to - * endorse or promote products derived from this software without - * prior written permission. For written permission, please contact - * openssl-core@openssl.org. - * - * 5. Products derived from this software may not be called "OpenSSL" - * nor may "OpenSSL" appear in their names without prior written - * permission of the OpenSSL Project. - * - * 6. Redistributions of any form whatsoever must retain the following - * acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit (http://www.openssl.org/)" - * - * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY - * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR - * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * ==================================================================== */ - -#include "aes-gcm.h" -#include "common.h" -#include "util.h" - -#define STRICT_ALIGNMENT 1 - -#define OPENSSL_memcpy memcpy -#define OPENSSL_memset memset -#define CRYPTO_memcmp safe_memcmp - -#ifdef CORE_CORTEX_M -#define GHASH_ASM -#define OPENSSL_ARM -#define __ARM_ARCH__ 7 -#endif - -static inline uint32_t CRYPTO_bswap4(uint32_t x) -{ - return __builtin_bswap32(x); -} - -static inline uint64_t CRYPTO_bswap8(uint64_t x) -{ - return __builtin_bswap64(x); -} - -static inline size_t load_word_le(const void *in) -{ - size_t v; - OPENSSL_memcpy(&v, in, sizeof(v)); - return v; -} - -static inline void store_word_le(void *out, size_t v) -{ - OPENSSL_memcpy(out, &v, sizeof(v)); -} - -#define PACK(s) ((size_t)(s) << (sizeof(size_t) * 8 - 16)) -#define REDUCE1BIT(V) \ - do { \ - if (sizeof(size_t) == 8) { \ - uint64_t T = UINT64_C(0xe100000000000000) & \ - (0 - ((V).lo & 1)); \ - (V).lo = ((V).hi << 63) | ((V).lo >> 1); \ - (V).hi = ((V).hi >> 1) ^ T; \ - } else { \ - uint32_t T = 0xe1000000U & \ - (0 - (uint32_t)((V).lo & 1)); \ - (V).lo = ((V).hi << 63) | ((V).lo >> 1); \ - (V).hi = ((V).hi >> 1) ^ ((uint64_t)T << 32); \ - } \ - } while (0) - -static void gcm_init_4bit(u128 Htable[16], uint64_t H[2]) -{ - u128 V; - - Htable[0].hi = 0; - Htable[0].lo = 0; - V.hi = H[0]; - V.lo = H[1]; - - Htable[8] = V; - REDUCE1BIT(V); - Htable[4] = V; - REDUCE1BIT(V); - Htable[2] = V; - REDUCE1BIT(V); - Htable[1] = V; - Htable[3].hi = V.hi ^ Htable[2].hi, Htable[3].lo = V.lo ^ Htable[2].lo; - V = Htable[4]; - Htable[5].hi = V.hi ^ Htable[1].hi, Htable[5].lo = V.lo ^ Htable[1].lo; - Htable[6].hi = V.hi ^ Htable[2].hi, Htable[6].lo = V.lo ^ Htable[2].lo; - Htable[7].hi = V.hi ^ Htable[3].hi, Htable[7].lo = V.lo ^ Htable[3].lo; - V = Htable[8]; - Htable[9].hi = V.hi ^ Htable[1].hi, Htable[9].lo = V.lo ^ Htable[1].lo; - Htable[10].hi = V.hi ^ Htable[2].hi, - Htable[10].lo = V.lo ^ Htable[2].lo; - Htable[11].hi = V.hi ^ Htable[3].hi, - Htable[11].lo = V.lo ^ Htable[3].lo; - Htable[12].hi = V.hi ^ Htable[4].hi, - Htable[12].lo = V.lo ^ Htable[4].lo; - Htable[13].hi = V.hi ^ Htable[5].hi, - Htable[13].lo = V.lo ^ Htable[5].lo; - Htable[14].hi = V.hi ^ Htable[6].hi, - Htable[14].lo = V.lo ^ Htable[6].lo; - Htable[15].hi = V.hi ^ Htable[7].hi, - Htable[15].lo = V.lo ^ Htable[7].lo; - -#if defined(GHASH_ASM) && defined(OPENSSL_ARM) - for (int j = 0; j < 16; ++j) { - V = Htable[j]; - Htable[j].hi = V.lo; - Htable[j].lo = V.hi; - } -#endif -} - -#if !defined(GHASH_ASM) || defined(OPENSSL_AARCH64) || defined(OPENSSL_PPC64LE) -static const size_t rem_4bit[16] = { PACK(0x0000), PACK(0x1C20), PACK(0x3840), - PACK(0x2460), PACK(0x7080), PACK(0x6CA0), - PACK(0x48C0), PACK(0x54E0), PACK(0xE100), - PACK(0xFD20), PACK(0xD940), PACK(0xC560), - PACK(0x9180), PACK(0x8DA0), PACK(0xA9C0), - PACK(0xB5E0) }; - -static void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]) -{ - u128 Z; - int cnt = 15; - size_t rem, nlo, nhi; - - nlo = ((const uint8_t *)Xi)[15]; - nhi = nlo >> 4; - nlo &= 0xf; - - Z.hi = Htable[nlo].hi; - Z.lo = Htable[nlo].lo; - - while (1) { - rem = (size_t)Z.lo & 0xf; - Z.lo = (Z.hi << 60) | (Z.lo >> 4); - Z.hi = (Z.hi >> 4); - if (sizeof(size_t) == 8) { - Z.hi ^= rem_4bit[rem]; - } else { - Z.hi ^= (uint64_t)rem_4bit[rem] << 32; - } - - Z.hi ^= Htable[nhi].hi; - Z.lo ^= Htable[nhi].lo; - - if (--cnt < 0) { - break; - } - - nlo = ((const uint8_t *)Xi)[cnt]; - nhi = nlo >> 4; - nlo &= 0xf; - - rem = (size_t)Z.lo & 0xf; - Z.lo = (Z.hi << 60) | (Z.lo >> 4); - Z.hi = (Z.hi >> 4); - if (sizeof(size_t) == 8) { - Z.hi ^= rem_4bit[rem]; - } else { - Z.hi ^= (uint64_t)rem_4bit[rem] << 32; - } - - Z.hi ^= Htable[nlo].hi; - Z.lo ^= Htable[nlo].lo; - } - - Xi[0] = CRYPTO_bswap8(Z.hi); - Xi[1] = CRYPTO_bswap8(Z.lo); -} - -// Streamed gcm_mult_4bit, see CRYPTO_gcm128_[en|de]crypt for -// details... Compiler-generated code doesn't seem to give any -// performance improvement, at least not on x86[_64]. It's here -// mostly as reference and a placeholder for possible future -// non-trivial optimization[s]... -static void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) -{ - u128 Z; - int cnt; - size_t rem, nlo, nhi; - - do { - cnt = 15; - nlo = ((const uint8_t *)Xi)[15]; - nlo ^= inp[15]; - nhi = nlo >> 4; - nlo &= 0xf; - - Z.hi = Htable[nlo].hi; - Z.lo = Htable[nlo].lo; - - while (1) { - rem = (size_t)Z.lo & 0xf; - Z.lo = (Z.hi << 60) | (Z.lo >> 4); - Z.hi = (Z.hi >> 4); - if (sizeof(size_t) == 8) { - Z.hi ^= rem_4bit[rem]; - } else { - Z.hi ^= (uint64_t)rem_4bit[rem] << 32; - } - - Z.hi ^= Htable[nhi].hi; - Z.lo ^= Htable[nhi].lo; - - if (--cnt < 0) { - break; - } - - nlo = ((const uint8_t *)Xi)[cnt]; - nlo ^= inp[cnt]; - nhi = nlo >> 4; - nlo &= 0xf; - - rem = (size_t)Z.lo & 0xf; - Z.lo = (Z.hi << 60) | (Z.lo >> 4); - Z.hi = (Z.hi >> 4); - if (sizeof(size_t) == 8) { - Z.hi ^= rem_4bit[rem]; - } else { - Z.hi ^= (uint64_t)rem_4bit[rem] << 32; - } - - Z.hi ^= Htable[nlo].hi; - Z.lo ^= Htable[nlo].lo; - } - - Xi[0] = CRYPTO_bswap8(Z.hi); - Xi[1] = CRYPTO_bswap8(Z.lo); - } while (inp += 16, len -= 16); -} -#else // GHASH_ASM -void gcm_gmult_4bit(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_4bit(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, - size_t len); -#endif - -#define GCM_MUL(ctx, Xi) gcm_gmult_4bit((ctx)->Xi.u, (ctx)->Htable) -#if defined(GHASH_ASM) -#define GHASH(ctx, in, len) gcm_ghash_4bit((ctx)->Xi.u, (ctx)->Htable, in, len) -// GHASH_CHUNK is "stride parameter" missioned to mitigate cache -// trashing effect. In other words idea is to hash data while it's -// still in L1 cache after encryption pass... -#define GHASH_CHUNK (3 * 1024) -#endif - -#if defined(GHASH_ASM) - -#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64) -#define GCM_FUNCREF_4BIT -void gcm_init_clmul(u128 Htable[16], const uint64_t Xi[2]); -void gcm_gmult_clmul(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_clmul(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, - size_t len); - -#if defined(OPENSSL_X86_64) -#define GHASH_ASM_X86_64 -void gcm_init_avx(u128 Htable[16], const uint64_t Xi[2]); -void gcm_gmult_avx(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_avx(uint64_t Xi[2], const u128 Htable[16], const uint8_t *in, - size_t len); -#define AESNI_GCM -size_t aesni_gcm_encrypt(const uint8_t *in, uint8_t *out, size_t len, - const void *key, uint8_t ivec[16], uint64_t *Xi); -size_t aesni_gcm_decrypt(const uint8_t *in, uint8_t *out, size_t len, - const void *key, uint8_t ivec[16], uint64_t *Xi); -#endif - -#if defined(OPENSSL_X86) -#define GHASH_ASM_X86 -void gcm_gmult_4bit_mmx(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_4bit_mmx(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len); -#endif - -#elif defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64) -#if __ARM_ARCH__ >= 7 -#define GHASH_ASM_ARM -#define GCM_FUNCREF_4BIT - -#if defined(OPENSSL_ARM_PMULL) -static int pmull_capable(void) -{ - return CRYPTO_is_ARMv8_PMULL_capable(); -} - -void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]); -void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, - size_t len); -#else -static int pmull_capable(void) -{ - return 0; -} -static void gcm_init_v8(u128 Htable[16], const uint64_t Xi[2]) -{ -} -static void gcm_gmult_v8(uint64_t Xi[2], const u128 Htable[16]) -{ -} -static void gcm_ghash_v8(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) -{ -} -#endif - -#if defined(OPENSSL_ARM_NEON) -// 32-bit ARM also has support for doing GCM with NEON instructions. -static int neon_capable(void) -{ - return CRYPTO_is_NEON_capable(); -} - -void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]); -void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, - size_t len); -#else -// AArch64 only has the ARMv8 versions of functions. -static int neon_capable(void) -{ - return 0; -} -static void gcm_init_neon(u128 Htable[16], const uint64_t Xi[2]) -{ -} -static void gcm_gmult_neon(uint64_t Xi[2], const u128 Htable[16]) -{ -} -static void gcm_ghash_neon(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) -{ -} -#endif - -#endif -#elif defined(OPENSSL_PPC64LE) -#define GHASH_ASM_PPC64LE -#define GCM_FUNCREF_4BIT -void gcm_init_p8(u128 Htable[16], const uint64_t Xi[2]); -void gcm_gmult_p8(uint64_t Xi[2], const u128 Htable[16]); -void gcm_ghash_p8(uint64_t Xi[2], const u128 Htable[16], const uint8_t *inp, - size_t len); -#endif -#endif - -#ifdef GCM_FUNCREF_4BIT -#undef GCM_MUL -#define GCM_MUL(ctx, Xi) (*gcm_gmult_p)((ctx)->Xi.u, (ctx)->Htable) -#ifdef GHASH -#undef GHASH -#define GHASH(ctx, in, len) (*gcm_ghash_p)((ctx)->Xi.u, (ctx)->Htable, in, len) -#endif -#endif - -#ifdef GHASH -// kSizeTWithoutLower4Bits is a mask that can be used to zero the lower four -// bits of a |size_t|. -static const size_t kSizeTWithoutLower4Bits = (size_t)-16; -#endif - -static void CRYPTO_ghash_init(gmult_func *out_mult, ghash_func *out_hash, - u128 *out_key, u128 out_table[16], - const uint8_t *gcm_key) -{ - union { - uint64_t u[2]; - uint8_t c[16]; - } H; - - OPENSSL_memcpy(H.c, gcm_key, 16); - - // H is stored in host byte order - H.u[0] = CRYPTO_bswap8(H.u[0]); - H.u[1] = CRYPTO_bswap8(H.u[1]); - - OPENSSL_memcpy(out_key, H.c, 16); - -#if defined(GHASH_ASM_X86_64) - if (crypto_gcm_clmul_enabled()) { - if (((OPENSSL_ia32cap_get()[1] >> 22) & 0x41) == - 0x41) { // AVX+MOVBE - gcm_init_avx(out_table, H.u); - *out_mult = gcm_gmult_avx; - *out_hash = gcm_ghash_avx; - *out_is_avx = 1; - return; - } - gcm_init_clmul(out_table, H.u); - *out_mult = gcm_gmult_clmul; - *out_hash = gcm_ghash_clmul; - return; - } -#elif defined(GHASH_ASM_X86) - if (crypto_gcm_clmul_enabled()) { - gcm_init_clmul(out_table, H.u); - *out_mult = gcm_gmult_clmul; - *out_hash = gcm_ghash_clmul; - return; - } -#elif defined(GHASH_ASM_ARM) - if (pmull_capable()) { - gcm_init_v8(out_table, H.u); - *out_mult = gcm_gmult_v8; - *out_hash = gcm_ghash_v8; - return; - } - - if (neon_capable()) { - gcm_init_neon(out_table, H.u); - *out_mult = gcm_gmult_neon; - *out_hash = gcm_ghash_neon; - return; - } -#elif defined(GHASH_ASM_PPC64LE) - if (CRYPTO_is_PPC64LE_vcrypto_capable()) { - gcm_init_p8(out_table, H.u); - *out_mult = gcm_gmult_p8; - *out_hash = gcm_ghash_p8; - return; - } -#endif - - gcm_init_4bit(out_table, H.u); -#if defined(GHASH_ASM_X86) - *out_mult = gcm_gmult_4bit_mmx; - *out_hash = gcm_ghash_4bit_mmx; -#else - *out_mult = gcm_gmult_4bit; - *out_hash = gcm_ghash_4bit; -#endif -} - -void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *aes_key, - block128_f block, int block_is_hwaes) -{ - OPENSSL_memset(ctx, 0, sizeof(*ctx)); - ctx->block = block; - - uint8_t gcm_key[16]; - OPENSSL_memset(gcm_key, 0, sizeof(gcm_key)); - (*block)(gcm_key, gcm_key, aes_key); - - CRYPTO_ghash_init(&ctx->gmult, &ctx->ghash, &ctx->H, ctx->Htable, - gcm_key); -} - -void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key, - const uint8_t *iv, size_t len) -{ - unsigned int ctr; -#ifdef GCM_FUNCREF_4BIT - void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; -#endif - - ctx->Yi.u[0] = 0; - ctx->Yi.u[1] = 0; - ctx->Xi.u[0] = 0; - ctx->Xi.u[1] = 0; - ctx->len.u[0] = 0; // AAD length - ctx->len.u[1] = 0; // message length - ctx->ares = 0; - ctx->mres = 0; - - if (len == 12) { - OPENSSL_memcpy(ctx->Yi.c, iv, 12); - ctx->Yi.c[15] = 1; - ctr = 1; - } else { - uint64_t len0 = len; - - while (len >= 16) { - for (size_t i = 0; i < 16; ++i) { - ctx->Yi.c[i] ^= iv[i]; - } - GCM_MUL(ctx, Yi); - iv += 16; - len -= 16; - } - if (len) { - for (size_t i = 0; i < len; ++i) { - ctx->Yi.c[i] ^= iv[i]; - } - GCM_MUL(ctx, Yi); - } - len0 <<= 3; - ctx->Yi.u[1] ^= CRYPTO_bswap8(len0); - - GCM_MUL(ctx, Yi); - ctr = CRYPTO_bswap4(ctx->Yi.d[3]); - } - - (*ctx->block)(ctx->Yi.c, ctx->EK0.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); -} - -int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len) -{ - unsigned int n; - uint64_t alen = ctx->len.u[0]; -#ifdef GCM_FUNCREF_4BIT - void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; -#ifdef GHASH - void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) = ctx->ghash; -#endif -#endif - - if (ctx->len.u[1]) { - return 0; - } - - alen += len; - if (alen > (UINT64_C(1) << 61) || (sizeof(len) == 8 && alen < len)) { - return 0; - } - ctx->len.u[0] = alen; - - n = ctx->ares; - if (n) { - while (n && len) { - ctx->Xi.c[n] ^= *(aad++); - --len; - n = (n + 1) % 16; - } - if (n == 0) { - GCM_MUL(ctx, Xi); - } else { - ctx->ares = n; - return 1; - } - } - - // Process a whole number of blocks. -#ifdef GHASH - size_t len_blocks = len & kSizeTWithoutLower4Bits; - if (len_blocks != 0) { - GHASH(ctx, aad, len_blocks); - aad += len_blocks; - len -= len_blocks; - } -#else - while (len >= 16) { - for (size_t i = 0; i < 16; ++i) { - ctx->Xi.c[i] ^= aad[i]; - } - GCM_MUL(ctx, Xi); - aad += 16; - len -= 16; - } -#endif - - // Process the remainder. - if (len != 0) { - n = (unsigned int)len; - for (size_t i = 0; i < len; ++i) { - ctx->Xi.c[i] ^= aad[i]; - } - } - - ctx->ares = n; - return 1; -} - -int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key, - const uint8_t *in, uint8_t *out, size_t len) -{ - unsigned int n, ctr; - uint64_t mlen = ctx->len.u[1]; - block128_f block = ctx->block; -#ifdef GCM_FUNCREF_4BIT - void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; -#ifdef GHASH - void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) = ctx->ghash; -#endif -#endif - - mlen += len; - if (mlen > ((UINT64_C(1) << 36) - 32) || - (sizeof(len) == 8 && mlen < len)) { - return 0; - } - ctx->len.u[1] = mlen; - - if (ctx->ares) { - // First call to encrypt finalizes GHASH(AAD) - GCM_MUL(ctx, Xi); - ctx->ares = 0; - } - - ctr = CRYPTO_bswap4(ctx->Yi.d[3]); - - n = ctx->mres; - if (n) { - while (n && len) { - ctx->Xi.c[n] ^= *(out++) = *(in++) ^ ctx->EKi.c[n]; - --len; - n = (n + 1) % 16; - } - if (n == 0) { - GCM_MUL(ctx, Xi); - } else { - ctx->mres = n; - return 1; - } - } - if (STRICT_ALIGNMENT && - ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) { - for (size_t i = 0; i < len; ++i) { - if (n == 0) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - } - ctx->Xi.c[n] ^= out[i] = in[i] ^ ctx->EKi.c[n]; - n = (n + 1) % 16; - if (n == 0) { - GCM_MUL(ctx, Xi); - } - } - - ctx->mres = n; - return 1; - } -#if defined(GHASH) && defined(GHASH_CHUNK) - while (len >= GHASH_CHUNK) { - size_t j = GHASH_CHUNK; - - while (j) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - store_word_le( - out + i, - load_word_le(in + i) ^ - ctx->EKi.t[i / sizeof(size_t)]); - } - out += 16; - in += 16; - j -= 16; - } - GHASH(ctx, out - GHASH_CHUNK, GHASH_CHUNK); - len -= GHASH_CHUNK; - } - size_t len_blocks = len & kSizeTWithoutLower4Bits; - if (len_blocks != 0) { - while (len >= 16) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - store_word_le( - out + i, - load_word_le(in + i) ^ - ctx->EKi.t[i / sizeof(size_t)]); - } - out += 16; - in += 16; - len -= 16; - } - GHASH(ctx, out - len_blocks, len_blocks); - } -#else - while (len >= 16) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - size_t tmp = load_word_le(in + i) ^ - ctx->EKi.t[i / sizeof(size_t)]; - store_word_le(out + i, tmp); - ctx->Xi.t[i / sizeof(size_t)] ^= tmp; - } - GCM_MUL(ctx, Xi); - out += 16; - in += 16; - len -= 16; - } -#endif - if (len) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - while (len--) { - ctx->Xi.c[n] ^= out[n] = in[n] ^ ctx->EKi.c[n]; - ++n; - } - } - - ctx->mres = n; - return 1; -} - -int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key, - const unsigned char *in, unsigned char *out, - size_t len) -{ - unsigned int n, ctr; - uint64_t mlen = ctx->len.u[1]; - block128_f block = ctx->block; -#ifdef GCM_FUNCREF_4BIT - void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; -#ifdef GHASH - void (*gcm_ghash_p)(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len) = ctx->ghash; -#endif -#endif - - mlen += len; - if (mlen > ((UINT64_C(1) << 36) - 32) || - (sizeof(len) == 8 && mlen < len)) { - return 0; - } - ctx->len.u[1] = mlen; - - if (ctx->ares) { - // First call to decrypt finalizes GHASH(AAD) - GCM_MUL(ctx, Xi); - ctx->ares = 0; - } - - ctr = CRYPTO_bswap4(ctx->Yi.d[3]); - - n = ctx->mres; - if (n) { - while (n && len) { - uint8_t c = *(in++); - *(out++) = c ^ ctx->EKi.c[n]; - ctx->Xi.c[n] ^= c; - --len; - n = (n + 1) % 16; - } - if (n == 0) { - GCM_MUL(ctx, Xi); - } else { - ctx->mres = n; - return 1; - } - } - if (STRICT_ALIGNMENT && - ((uintptr_t)in | (uintptr_t)out) % sizeof(size_t) != 0) { - for (size_t i = 0; i < len; ++i) { - uint8_t c; - if (n == 0) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - } - c = in[i]; - out[i] = c ^ ctx->EKi.c[n]; - ctx->Xi.c[n] ^= c; - n = (n + 1) % 16; - if (n == 0) { - GCM_MUL(ctx, Xi); - } - } - - ctx->mres = n; - return 1; - } -#if defined(GHASH) && defined(GHASH_CHUNK) - while (len >= GHASH_CHUNK) { - size_t j = GHASH_CHUNK; - - GHASH(ctx, in, GHASH_CHUNK); - while (j) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - store_word_le( - out + i, - load_word_le(in + i) ^ - ctx->EKi.t[i / sizeof(size_t)]); - } - out += 16; - in += 16; - j -= 16; - } - len -= GHASH_CHUNK; - } - size_t len_blocks = len & kSizeTWithoutLower4Bits; - if (len_blocks != 0) { - GHASH(ctx, in, len_blocks); - while (len >= 16) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - store_word_le( - out + i, - load_word_le(in + i) ^ - ctx->EKi.t[i / sizeof(size_t)]); - } - out += 16; - in += 16; - len -= 16; - } - } -#else - while (len >= 16) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - for (size_t i = 0; i < 16; i += sizeof(size_t)) { - size_t c = load_word_le(in + i); - store_word_le(out + i, - c ^ ctx->EKi.t[i / sizeof(size_t)]); - ctx->Xi.t[i / sizeof(size_t)] ^= c; - } - GCM_MUL(ctx, Xi); - out += 16; - in += 16; - len -= 16; - } -#endif - if (len) { - (*block)(ctx->Yi.c, ctx->EKi.c, key); - ++ctr; - ctx->Yi.d[3] = CRYPTO_bswap4(ctr); - while (len--) { - uint8_t c = in[n]; - ctx->Xi.c[n] ^= c; - out[n] = c ^ ctx->EKi.c[n]; - ++n; - } - } - - ctx->mres = n; - return 1; -} - -int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len) -{ - uint64_t alen = ctx->len.u[0] << 3; - uint64_t clen = ctx->len.u[1] << 3; -#ifdef GCM_FUNCREF_4BIT - void (*gcm_gmult_p)(uint64_t Xi[2], const u128 Htable[16]) = ctx->gmult; -#endif - - if (ctx->mres || ctx->ares) { - GCM_MUL(ctx, Xi); - } - - alen = CRYPTO_bswap8(alen); - clen = CRYPTO_bswap8(clen); - - ctx->Xi.u[0] ^= alen; - ctx->Xi.u[1] ^= clen; - GCM_MUL(ctx, Xi); - - ctx->Xi.u[0] ^= ctx->EK0.u[0]; - ctx->Xi.u[1] ^= ctx->EK0.u[1]; - - if (tag && len <= sizeof(ctx->Xi)) { - return CRYPTO_memcmp(ctx->Xi.c, tag, len) == 0; - } else { - return 0; - } -} - -void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, unsigned char *tag, size_t len) -{ - CRYPTO_gcm128_finish(ctx, NULL, 0); - OPENSSL_memcpy(tag, ctx->Xi.c, - len <= sizeof(ctx->Xi.c) ? len : sizeof(ctx->Xi.c)); -} - -#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64) -int crypto_gcm_clmul_enabled(void) -{ -#ifdef GHASH_ASM - const uint32_t *ia32cap = OPENSSL_ia32cap_get(); - return (ia32cap[0] & (1 << 24)) && // check FXSR bit - (ia32cap[1] & (1 << 1)); // check PCLMULQDQ bit -#else - return 0; -#endif -} -#endif diff --git a/common/aes-gcm.c b/common/aes-gcm.c new file mode 120000 index 0000000000..3176d85ff8 --- /dev/null +++ b/common/aes-gcm.c @@ -0,0 +1 @@ +../third_party/boringssl/common/aes-gcm.c \ No newline at end of file diff --git a/common/aes.c b/common/aes.c deleted file mode 100644 index beebc9d2fc..0000000000 --- a/common/aes.c +++ /dev/null @@ -1,830 +0,0 @@ -/* ==================================================================== - * Copyright (c) 2002-2006 The OpenSSL Project. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * 3. All advertising materials mentioning features or use of this - * software must display the following acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" - * - * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to - * endorse or promote products derived from this software without - * prior written permission. For written permission, please contact - * openssl-core@openssl.org. - * - * 5. Products derived from this software may not be called "OpenSSL" - * nor may "OpenSSL" appear in their names without prior written - * permission of the OpenSSL Project. - * - * 6. Redistributions of any form whatsoever must retain the following - * acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit (http://www.openssl.org/)" - * - * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY - * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR - * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * ==================================================================== */ - -#include "aes.h" -#include "common.h" -#include "endian.h" - -static inline uint32_t GETU32(const void *in) -{ - return be32toh(*(uint32_t *)in); -} - -static inline void PUTU32(void *out, uint32_t v) -{ - *(uint32_t *)out = htobe32(v); -} - -// Te0[x] = S [x].[02, 01, 01, 03]; -// Te1[x] = S [x].[03, 02, 01, 01]; -// Te2[x] = S [x].[01, 03, 02, 01]; -// Te3[x] = S [x].[01, 01, 03, 02]; -// -// Td0[x] = Si[x].[0e, 09, 0d, 0b]; -// Td1[x] = Si[x].[0b, 0e, 09, 0d]; -// Td2[x] = Si[x].[0d, 0b, 0e, 09]; -// Td3[x] = Si[x].[09, 0d, 0b, 0e]; -// Td4[x] = Si[x].[01]; - -static const uint32_t Te0[256] = { - 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, 0xfff2f20dU, - 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, 0x60303050U, 0x02010103U, - 0xce6767a9U, 0x562b2b7dU, 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, - 0xec76769aU, 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, - 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, 0x41adadecU, - 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, 0x239c9cbfU, 0x53a4a4f7U, - 0xe4727296U, 0x9bc0c05bU, 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, - 0x4c26266aU, 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, - 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, 0xe2717193U, - 0xabd8d873U, 0x62313153U, 0x2a15153fU, 0x0804040cU, 0x95c7c752U, - 0x46232365U, 0x9dc3c35eU, 0x30181828U, 0x379696a1U, 0x0a05050fU, - 0x2f9a9ab5U, 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, - 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, 0x1209091bU, - 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, 0x361b1b2dU, 0xdc6e6eb2U, - 0xb45a5aeeU, 0x5ba0a0fbU, 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, - 0x7db3b3ceU, 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, - 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, 0x40202060U, - 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, 0xd46a6abeU, 0x8dcbcb46U, - 0x67bebed9U, 0x7239394bU, 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, - 0x85cfcf4aU, 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, - 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, 0x8a4545cfU, - 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, 0xa05050f0U, 0x783c3c44U, - 0x259f9fbaU, 0x4ba8a8e3U, 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, - 0x058f8f8aU, 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, - 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, 0x20101030U, - 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, 0x81cdcd4cU, 0x180c0c14U, - 0x26131335U, 0xc3ecec2fU, 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, - 0x2e171739U, 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, - 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, 0xc06060a0U, - 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, 0x44222266U, 0x542a2a7eU, - 0x3b9090abU, 0x0b888883U, 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, - 0x2814143cU, 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, - 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, 0x924949dbU, - 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, 0x9fc2c25dU, 0xbdd3d36eU, - 0x43acacefU, 0xc46262a6U, 0x399191a8U, 0x319595a4U, 0xd3e4e437U, - 0xf279798bU, 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, - 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, 0xd86c6cb4U, - 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, 0xca6565afU, 0xf47a7a8eU, - 0x47aeaee9U, 0x10080818U, 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, - 0x5c2e2e72U, 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, - 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, 0x964b4bddU, - 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, 0xe0707090U, 0x7c3e3e42U, - 0x71b5b5c4U, 0xcc6666aaU, 0x904848d8U, 0x06030305U, 0xf7f6f601U, - 0x1c0e0e12U, 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, - 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, 0xd9e1e138U, - 0xebf8f813U, 0x2b9898b3U, 0x22111133U, 0xd26969bbU, 0xa9d9d970U, - 0x078e8e89U, 0x339494a7U, 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, - 0xc9e9e920U, 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, - 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, 0x65bfbfdaU, - 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, 0x824141c3U, 0x299999b0U, - 0x5a2d2d77U, 0x1e0f0f11U, 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, - 0x2c16163aU, -}; - -static const uint32_t Te1[256] = { - 0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU, 0x0dfff2f2U, - 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U, 0x50603030U, 0x03020101U, - 0xa9ce6767U, 0x7d562b2bU, 0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, - 0x9aec7676U, 0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU, - 0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U, 0xec41adadU, - 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU, 0xbf239c9cU, 0xf753a4a4U, - 0x96e47272U, 0x5b9bc0c0U, 0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, - 0x6a4c2626U, 0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU, - 0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U, 0x93e27171U, - 0x73abd8d8U, 0x53623131U, 0x3f2a1515U, 0x0c080404U, 0x5295c7c7U, - 0x65462323U, 0x5e9dc3c3U, 0x28301818U, 0xa1379696U, 0x0f0a0505U, - 0xb52f9a9aU, 0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U, - 0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U, 0x1b120909U, - 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU, 0x2d361b1bU, 0xb2dc6e6eU, - 0xeeb45a5aU, 0xfb5ba0a0U, 0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, - 0xce7db3b3U, 0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U, - 0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU, 0x60402020U, - 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU, 0xbed46a6aU, 0x468dcbcbU, - 0xd967bebeU, 0x4b723939U, 0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, - 0x4a85cfcfU, 0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU, - 0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U, 0xcf8a4545U, - 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU, 0xf0a05050U, 0x44783c3cU, - 0xba259f9fU, 0xe34ba8a8U, 0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, - 0x8a058f8fU, 0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U, - 0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U, 0x30201010U, - 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U, 0x4c81cdcdU, 0x14180c0cU, - 0x35261313U, 0x2fc3ececU, 0xe1be5f5fU, 0xa2359797U, 0xcc884444U, - 0x392e1717U, 0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU, - 0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U, 0xa0c06060U, - 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU, 0x66442222U, 0x7e542a2aU, - 0xab3b9090U, 0x830b8888U, 0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, - 0x3c281414U, 0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU, - 0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU, 0xdb924949U, - 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU, 0x5d9fc2c2U, 0x6ebdd3d3U, - 0xef43acacU, 0xa6c46262U, 0xa8399191U, 0xa4319595U, 0x37d3e4e4U, - 0x8bf27979U, 0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU, - 0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U, 0xb4d86c6cU, - 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU, 0xafca6565U, 0x8ef47a7aU, - 0xe947aeaeU, 0x18100808U, 0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, - 0x725c2e2eU, 0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U, - 0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU, 0xdd964b4bU, - 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU, 0x90e07070U, 0x427c3e3eU, - 0xc471b5b5U, 0xaacc6666U, 0xd8904848U, 0x05060303U, 0x01f7f6f6U, - 0x121c0e0eU, 0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U, - 0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU, 0x38d9e1e1U, - 0x13ebf8f8U, 0xb32b9898U, 0x33221111U, 0xbbd26969U, 0x70a9d9d9U, - 0x89078e8eU, 0xa7339494U, 0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, - 0x20c9e9e9U, 0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU, - 0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU, 0xda65bfbfU, - 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U, 0xc3824141U, 0xb0299999U, - 0x775a2d2dU, 0x111e0f0fU, 0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, - 0x3a2c1616U, -}; - -static const uint32_t Te2[256] = { - 0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU, 0xf20dfff2U, - 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U, 0x30506030U, 0x01030201U, - 0x67a9ce67U, 0x2b7d562bU, 0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, - 0x769aec76U, 0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU, - 0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U, 0xadec41adU, - 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU, 0x9cbf239cU, 0xa4f753a4U, - 0x7296e472U, 0xc05b9bc0U, 0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, - 0x266a4c26U, 0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU, - 0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U, 0x7193e271U, - 0xd873abd8U, 0x31536231U, 0x153f2a15U, 0x040c0804U, 0xc75295c7U, - 0x23654623U, 0xc35e9dc3U, 0x18283018U, 0x96a13796U, 0x050f0a05U, - 0x9ab52f9aU, 0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U, - 0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U, 0x091b1209U, - 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU, 0x1b2d361bU, 0x6eb2dc6eU, - 0x5aeeb45aU, 0xa0fb5ba0U, 0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, - 0xb3ce7db3U, 0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U, - 0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU, 0x20604020U, - 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU, 0x6abed46aU, 0xcb468dcbU, - 0xbed967beU, 0x394b7239U, 0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, - 0xcf4a85cfU, 0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU, - 0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U, 0x45cf8a45U, - 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU, 0x50f0a050U, 0x3c44783cU, - 0x9fba259fU, 0xa8e34ba8U, 0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, - 0x8f8a058fU, 0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U, - 0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U, 0x10302010U, - 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U, 0xcd4c81cdU, 0x0c14180cU, - 0x13352613U, 0xec2fc3ecU, 0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, - 0x17392e17U, 0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU, - 0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U, 0x60a0c060U, - 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU, 0x22664422U, 0x2a7e542aU, - 0x90ab3b90U, 0x88830b88U, 0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, - 0x143c2814U, 0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU, - 0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU, 0x49db9249U, - 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU, 0xc25d9fc2U, 0xd36ebdd3U, - 0xacef43acU, 0x62a6c462U, 0x91a83991U, 0x95a43195U, 0xe437d3e4U, - 0x798bf279U, 0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU, - 0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U, 0x6cb4d86cU, - 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU, 0x65afca65U, 0x7a8ef47aU, - 0xaee947aeU, 0x08181008U, 0xbad56fbaU, 0x7888f078U, 0x256f4a25U, - 0x2e725c2eU, 0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U, - 0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU, 0x4bdd964bU, - 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU, 0x7090e070U, 0x3e427c3eU, - 0xb5c471b5U, 0x66aacc66U, 0x48d89048U, 0x03050603U, 0xf601f7f6U, - 0x0e121c0eU, 0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U, - 0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU, 0xe138d9e1U, - 0xf813ebf8U, 0x98b32b98U, 0x11332211U, 0x69bbd269U, 0xd970a9d9U, - 0x8e89078eU, 0x94a73394U, 0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, - 0xe920c9e9U, 0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU, - 0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU, 0xbfda65bfU, - 0xe631d7e6U, 0x42c68442U, 0x68b8d068U, 0x41c38241U, 0x99b02999U, - 0x2d775a2dU, 0x0f111e0fU, 0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, - 0x163a2c16U, -}; - -static const uint32_t Te3[256] = { - 0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U, 0xf2f20dffU, - 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U, 0x30305060U, 0x01010302U, - 0x6767a9ceU, 0x2b2b7d56U, 0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, - 0x76769aecU, 0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU, - 0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU, 0xadadec41U, - 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U, 0x9c9cbf23U, 0xa4a4f753U, - 0x727296e4U, 0xc0c05b9bU, 0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, - 0x26266a4cU, 0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U, - 0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U, 0x717193e2U, - 0xd8d873abU, 0x31315362U, 0x15153f2aU, 0x04040c08U, 0xc7c75295U, - 0x23236546U, 0xc3c35e9dU, 0x18182830U, 0x9696a137U, 0x05050f0aU, - 0x9a9ab52fU, 0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU, - 0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU, 0x09091b12U, - 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U, 0x1b1b2d36U, 0x6e6eb2dcU, - 0x5a5aeeb4U, 0xa0a0fb5bU, 0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, - 0xb3b3ce7dU, 0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U, - 0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U, 0x20206040U, - 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U, 0x6a6abed4U, 0xcbcb468dU, - 0xbebed967U, 0x39394b72U, 0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, - 0xcfcf4a85U, 0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU, - 0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U, 0x4545cf8aU, - 0xf9f910e9U, 0x02020604U, 0x7f7f81feU, 0x5050f0a0U, 0x3c3c4478U, - 0x9f9fba25U, 0xa8a8e34bU, 0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, - 0x8f8f8a05U, 0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U, - 0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U, 0x10103020U, - 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU, 0xcdcd4c81U, 0x0c0c1418U, - 0x13133526U, 0xecec2fc3U, 0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, - 0x1717392eU, 0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU, - 0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U, 0x6060a0c0U, - 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U, 0x22226644U, 0x2a2a7e54U, - 0x9090ab3bU, 0x8888830bU, 0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, - 0x14143c28U, 0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU, - 0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U, 0x4949db92U, - 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U, 0xc2c25d9fU, 0xd3d36ebdU, - 0xacacef43U, 0x6262a6c4U, 0x9191a839U, 0x9595a431U, 0xe4e437d3U, - 0x79798bf2U, 0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU, - 0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U, 0x6c6cb4d8U, - 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU, 0x6565afcaU, 0x7a7a8ef4U, - 0xaeaee947U, 0x08081810U, 0xbabad56fU, 0x787888f0U, 0x25256f4aU, - 0x2e2e725cU, 0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U, - 0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU, 0x4b4bdd96U, - 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU, 0x707090e0U, 0x3e3e427cU, - 0xb5b5c471U, 0x6666aaccU, 0x4848d890U, 0x03030506U, 0xf6f601f7U, - 0x0e0e121cU, 0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U, - 0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U, 0xe1e138d9U, - 0xf8f813ebU, 0x9898b32bU, 0x11113322U, 0x6969bbd2U, 0xd9d970a9U, - 0x8e8e8907U, 0x9494a733U, 0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, - 0xe9e920c9U, 0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U, - 0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU, 0xbfbfda65U, - 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U, 0x4141c382U, 0x9999b029U, - 0x2d2d775aU, 0x0f0f111eU, 0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, - 0x16163a2cU, -}; - -static const uint32_t Td0[256] = { - 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, 0x3bab6bcbU, - 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, 0x2030fa55U, 0xad766df6U, - 0x88cc7691U, 0xf5024c25U, 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, - 0xb562a38fU, 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, - 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, 0x038f5fe7U, - 0x15929c95U, 0xbf6d7aebU, 0x955259daU, 0xd4be832dU, 0x587421d3U, - 0x49e06929U, 0x8ec9c844U, 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, - 0x27b971ddU, 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, - 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, 0xb16477e0U, - 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, 0x70486858U, 0x8f45fd19U, - 0x94de6c87U, 0x527bf8b7U, 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, - 0x6655ab2aU, 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, - 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, 0x8acf1c2bU, - 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, 0x65daf4cdU, 0x0605bed5U, - 0xd134621fU, 0xc4a6fe8aU, 0x342e539dU, 0xa2f355a0U, 0x058ae132U, - 0xa4f6eb75U, 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, - 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, 0x91548db5U, - 0x71c45d05U, 0x0406d46fU, 0x605015ffU, 0x1998fb24U, 0xd6bde997U, - 0x894043ccU, 0x67d99e77U, 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, - 0x79c8eedbU, 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, - 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, 0xfd0efffbU, - 0x0f853856U, 0x3daed51eU, 0x362d3927U, 0x0a0fd964U, 0x685ca621U, - 0x9b5b54d1U, 0x24362e3aU, 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, - 0x1b9b919eU, 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, - 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, 0x0e090d0bU, - 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, 0x57f11985U, 0xaf75074cU, - 0xee99ddbbU, 0xa37f60fdU, 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, - 0x5bfb7e34U, 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, - 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, 0x854a247dU, - 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, 0x1d9e2f4bU, 0xdcb230f3U, - 0x0d8652ecU, 0x77c1e3d0U, 0x2bb3166cU, 0xa970b999U, 0x119448faU, - 0x47e96422U, 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, - 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, 0xa6f581cfU, - 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, 0x2c3a9de4U, 0x5078920dU, - 0x6a5fcc9bU, 0x547e4662U, 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, - 0x82c3aff5U, 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, - 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, 0xcd267809U, - 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, 0xe6956e65U, 0xaaffe67eU, - 0x21bccf08U, 0xef15e8e6U, 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, - 0x29b07cd6U, 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, - 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, 0xf104984aU, - 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, 0x764dd68dU, 0x43efb04dU, - 0xccaa4d54U, 0xe49604dfU, 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, - 0x4665517fU, 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, - 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, 0x9ad7618cU, - 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, 0xcea927eeU, 0xb761c935U, - 0xe11ce5edU, 0x7a47b13cU, 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, - 0x73c737bfU, 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, - 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, 0x161dc372U, - 0xbce2250cU, 0x283c498bU, 0xff0d9541U, 0x39a80171U, 0x080cb3deU, - 0xd8b4e49cU, 0x6456c190U, 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, - 0xd0b85742U, -}; - -static const uint32_t Td1[256] = { - 0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU, 0xcb3bab6bU, - 0xf11f9d45U, 0xabacfa58U, 0x934be303U, 0x552030faU, 0xf6ad766dU, - 0x9188cc76U, 0x25f5024cU, 0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, - 0x8fb562a3U, 0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U, - 0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U, 0xe7038f5fU, - 0x9515929cU, 0xebbf6d7aU, 0xda955259U, 0x2dd4be83U, 0xd3587421U, - 0x2949e069U, 0x448ec9c8U, 0x6a75c289U, 0x78f48e79U, 0x6b99583eU, - 0xdd27b971U, 0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU, - 0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU, 0xe0b16477U, - 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU, 0x58704868U, 0x198f45fdU, - 0x8794de6cU, 0xb7527bf8U, 0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, - 0x2a6655abU, 0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U, - 0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U, 0x2b8acf1cU, - 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U, 0xcd65daf4U, 0xd50605beU, - 0x1fd13462U, 0x8ac4a6feU, 0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, - 0x75a4f6ebU, 0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U, - 0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU, 0xb591548dU, - 0x0571c45dU, 0x6f0406d4U, 0xff605015U, 0x241998fbU, 0x97d6bde9U, - 0xcc894043U, 0x7767d99eU, 0xbdb0e842U, 0x8807898bU, 0x38e7195bU, - 0xdb79c8eeU, 0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U, - 0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U, 0xfbfd0effU, - 0x560f8538U, 0x1e3daed5U, 0x27362d39U, 0x640a0fd9U, 0x21685ca6U, - 0xd19b5b54U, 0x3a24362eU, 0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, - 0x9e1b9b91U, 0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU, - 0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U, 0x0b0e090dU, - 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U, 0x8557f119U, 0x4caf7507U, - 0xbbee99ddU, 0xfda37f60U, 0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, - 0x345bfb7eU, 0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U, - 0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U, 0x7d854a24U, - 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U, 0x4b1d9e2fU, 0xf3dcb230U, - 0xec0d8652U, 0xd077c1e3U, 0x6c2bb316U, 0x99a970b9U, 0xfa119448U, - 0x2247e964U, 0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U, - 0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU, 0xcfa6f581U, - 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU, 0xe42c3a9dU, 0x0d507892U, - 0x9b6a5fccU, 0x62547e46U, 0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, - 0xf582c3afU, 0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U, - 0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU, 0x09cd2678U, - 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU, 0x65e6956eU, 0x7eaaffe6U, - 0x0821bccfU, 0xe6ef15e8U, 0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, - 0xd629b07cU, 0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U, - 0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U, 0x4af10498U, - 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U, 0x8d764dd6U, 0x4d43efb0U, - 0x54ccaa4dU, 0xdfe49604U, 0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, - 0x7f466551U, 0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U, - 0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U, 0x8c9ad761U, - 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU, 0xeecea927U, 0x35b761c9U, - 0xede11ce5U, 0x3c7a47b1U, 0x599cd2dfU, 0x3f55f273U, 0x791814ceU, - 0xbf73c737U, 0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU, - 0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U, 0x72161dc3U, - 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U, 0x7139a801U, 0xde080cb3U, - 0x9cd8b4e4U, 0x906456c1U, 0x617bcb84U, 0x70d532b6U, 0x74486c5cU, - 0x42d0b857U, -}; - -static const uint32_t Td2[256] = { - 0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U, 0x6bcb3babU, - 0x45f11f9dU, 0x58abacfaU, 0x03934be3U, 0xfa552030U, 0x6df6ad76U, - 0x769188ccU, 0x4c25f502U, 0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, - 0xa38fb562U, 0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU, - 0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U, 0x5fe7038fU, - 0x9c951592U, 0x7aebbf6dU, 0x59da9552U, 0x832dd4beU, 0x21d35874U, - 0x692949e0U, 0xc8448ec9U, 0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, - 0x71dd27b9U, 0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU, - 0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U, 0x77e0b164U, - 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U, 0x68587048U, 0xfd198f45U, - 0x6c8794deU, 0xf8b7527bU, 0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, - 0xab2a6655U, 0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U, - 0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U, 0x1c2b8acfU, - 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U, 0xf4cd65daU, 0xbed50605U, - 0x621fd134U, 0xfe8ac4a6U, 0x539d342eU, 0x55a0a2f3U, 0xe132058aU, - 0xeb75a4f6U, 0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU, - 0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U, 0x8db59154U, - 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U, 0xfb241998U, 0xe997d6bdU, - 0x43cc8940U, 0x9e7767d9U, 0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, - 0xeedb79c8U, 0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U, - 0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU, 0xfffbfd0eU, - 0x38560f85U, 0xd51e3daeU, 0x3927362dU, 0xd9640a0fU, 0xa621685cU, - 0x54d19b5bU, 0x2e3a2436U, 0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, - 0x919e1b9bU, 0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U, - 0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU, 0x0d0b0e09U, - 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU, 0x198557f1U, 0x074caf75U, - 0xddbbee99U, 0x60fda37fU, 0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, - 0x7e345bfbU, 0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U, - 0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U, 0x247d854aU, - 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U, 0x2f4b1d9eU, 0x30f3dcb2U, - 0x52ec0d86U, 0xe3d077c1U, 0x166c2bb3U, 0xb999a970U, 0x48fa1194U, - 0x642247e9U, 0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U, - 0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U, 0x81cfa6f5U, - 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU, 0x9de42c3aU, 0x920d5078U, - 0xcc9b6a5fU, 0x4662547eU, 0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, - 0xaff582c3U, 0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U, - 0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU, 0x7809cd26U, - 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU, 0x6e65e695U, 0xe67eaaffU, - 0xcf0821bcU, 0xe8e6ef15U, 0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, - 0x7cd629b0U, 0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U, - 0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U, 0x984af104U, - 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U, 0xd68d764dU, 0xb04d43efU, - 0x4d54ccaaU, 0x04dfe496U, 0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, - 0x517f4665U, 0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU, - 0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U, 0x618c9ad7U, - 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U, 0x27eecea9U, 0xc935b761U, - 0xe5ede11cU, 0xb13c7a47U, 0xdf599cd2U, 0x733f55f2U, 0xce791814U, - 0x37bf73c7U, 0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U, - 0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U, 0xc372161dU, - 0x250cbce2U, 0x498b283cU, 0x9541ff0dU, 0x017139a8U, 0xb3de080cU, - 0xe49cd8b4U, 0xc1906456U, 0x84617bcbU, 0xb670d532U, 0x5c74486cU, - 0x5742d0b8U, -}; - -static const uint32_t Td3[256] = { - 0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU, 0xab6bcb3bU, - 0x9d45f11fU, 0xfa58abacU, 0xe303934bU, 0x30fa5520U, 0x766df6adU, - 0xcc769188U, 0x024c25f5U, 0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, - 0x62a38fb5U, 0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU, - 0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU, 0x8f5fe703U, - 0x929c9515U, 0x6d7aebbfU, 0x5259da95U, 0xbe832dd4U, 0x7421d358U, - 0xe0692949U, 0xc9c8448eU, 0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, - 0xb971dd27U, 0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU, - 0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U, 0x6477e0b1U, - 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U, 0x48685870U, 0x45fd198fU, - 0xde6c8794U, 0x7bf8b752U, 0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, - 0x55ab2a66U, 0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U, - 0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU, 0xcf1c2b8aU, - 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU, 0xdaf4cd65U, 0x05bed506U, - 0x34621fd1U, 0xa6fe8ac4U, 0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, - 0xf6eb75a4U, 0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU, - 0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU, 0x548db591U, - 0xc45d0571U, 0x06d46f04U, 0x5015ff60U, 0x98fb2419U, 0xbde997d6U, - 0x4043cc89U, 0xd99e7767U, 0xe842bdb0U, 0x898b8807U, 0x195b38e7U, - 0xc8eedb79U, 0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U, - 0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU, 0x0efffbfdU, - 0x8538560fU, 0xaed51e3dU, 0x2d392736U, 0x0fd9640aU, 0x5ca62168U, - 0x5b54d19bU, 0x362e3a24U, 0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, - 0x9b919e1bU, 0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU, - 0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U, 0x090d0b0eU, - 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U, 0xf1198557U, 0x75074cafU, - 0x99ddbbeeU, 0x7f60fda3U, 0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, - 0xfb7e345bU, 0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U, - 0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U, 0x4a247d85U, - 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U, 0x9e2f4b1dU, 0xb230f3dcU, - 0x8652ec0dU, 0xc1e3d077U, 0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, - 0xe9642247U, 0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U, - 0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U, 0xf581cfa6U, - 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU, 0x3a9de42cU, 0x78920d50U, - 0x5fcc9b6aU, 0x7e466254U, 0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, - 0xc3aff582U, 0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU, - 0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU, 0x267809cdU, - 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U, 0x956e65e6U, 0xffe67eaaU, - 0xbccf0821U, 0x15e8e6efU, 0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, - 0xb07cd629U, 0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U, - 0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U, 0x04984af1U, - 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U, 0x4dd68d76U, 0xefb04d43U, - 0xaa4d54ccU, 0x9604dfe4U, 0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, - 0x65517f46U, 0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU, - 0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU, 0xd7618c9aU, - 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU, 0xa927eeceU, 0x61c935b7U, - 0x1ce5ede1U, 0x47b13c7aU, 0xd2df599cU, 0xf2733f55U, 0x14ce7918U, - 0xc737bf73U, 0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U, - 0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U, 0x1dc37216U, - 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU, 0xa8017139U, 0x0cb3de08U, - 0xb4e49cd8U, 0x56c19064U, 0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, - 0xb85742d0U, -}; - -static const uint8_t Td4[256] = { - 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, 0xbfU, 0x40U, - 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, 0x7cU, 0xe3U, 0x39U, 0x82U, - 0x9bU, 0x2fU, 0xffU, 0x87U, 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, - 0xe9U, 0xcbU, 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, - 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, 0x08U, 0x2eU, - 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, 0x76U, 0x5bU, 0xa2U, 0x49U, - 0x6dU, 0x8bU, 0xd1U, 0x25U, 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, - 0x98U, 0x16U, 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, - 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, 0x5eU, 0x15U, - 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, 0x90U, 0xd8U, 0xabU, 0x00U, - 0x8cU, 0xbcU, 0xd3U, 0x0aU, 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, - 0x45U, 0x06U, 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, - 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, 0x3aU, 0x91U, - 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, 0x97U, 0xf2U, 0xcfU, 0xceU, - 0xf0U, 0xb4U, 0xe6U, 0x73U, 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, - 0x35U, 0x85U, 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, - 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, 0x6fU, 0xb7U, - 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, 0xfcU, 0x56U, 0x3eU, 0x4bU, - 0xc6U, 0xd2U, 0x79U, 0x20U, 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, - 0x5aU, 0xf4U, 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, - 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, 0x60U, 0x51U, - 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, 0x2dU, 0xe5U, 0x7aU, 0x9fU, - 0x93U, 0xc9U, 0x9cU, 0xefU, 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, - 0xf5U, 0xb0U, 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, - 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, 0xe1U, 0x69U, - 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, -}; - -static const uint32_t rcon[] = { - 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, - 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, - // for 128-bit blocks, Rijndael never uses more than 10 rcon values -}; - -int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits, AES_KEY *aeskey) -{ - uint32_t *rk; - int i = 0; - uint32_t temp; - - if (!key || !aeskey) { - return -1; - } - - switch (bits) { - case 128: - aeskey->rounds = 10; - break; - case 192: - aeskey->rounds = 12; - break; - case 256: - aeskey->rounds = 14; - break; - default: - return -2; - } - - rk = aeskey->rd_key; - - rk[0] = GETU32(key); - rk[1] = GETU32(key + 4); - rk[2] = GETU32(key + 8); - rk[3] = GETU32(key + 12); - if (bits == 128) { - while (1) { - temp = rk[3]; - rk[4] = rk[0] ^ - (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ - (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ - (Te0[(temp)&0xff] & 0x0000ff00) ^ - (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; - rk[5] = rk[1] ^ rk[4]; - rk[6] = rk[2] ^ rk[5]; - rk[7] = rk[3] ^ rk[6]; - if (++i == 10) { - return 0; - } - rk += 4; - } - } - rk[4] = GETU32(key + 16); - rk[5] = GETU32(key + 20); - if (bits == 192) { - while (1) { - temp = rk[5]; - rk[6] = rk[0] ^ - (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ - (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ - (Te0[(temp)&0xff] & 0x0000ff00) ^ - (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; - rk[7] = rk[1] ^ rk[6]; - rk[8] = rk[2] ^ rk[7]; - rk[9] = rk[3] ^ rk[8]; - if (++i == 8) { - return 0; - } - rk[10] = rk[4] ^ rk[9]; - rk[11] = rk[5] ^ rk[10]; - rk += 6; - } - } - rk[6] = GETU32(key + 24); - rk[7] = GETU32(key + 28); - if (bits == 256) { - while (1) { - temp = rk[7]; - rk[8] = rk[0] ^ - (Te2[(temp >> 16) & 0xff] & 0xff000000) ^ - (Te3[(temp >> 8) & 0xff] & 0x00ff0000) ^ - (Te0[(temp)&0xff] & 0x0000ff00) ^ - (Te1[(temp >> 24)] & 0x000000ff) ^ rcon[i]; - rk[9] = rk[1] ^ rk[8]; - rk[10] = rk[2] ^ rk[9]; - rk[11] = rk[3] ^ rk[10]; - if (++i == 7) { - return 0; - } - temp = rk[11]; - rk[12] = rk[4] ^ (Te2[(temp >> 24)] & 0xff000000) ^ - (Te3[(temp >> 16) & 0xff] & 0x00ff0000) ^ - (Te0[(temp >> 8) & 0xff] & 0x0000ff00) ^ - (Te1[(temp)&0xff] & 0x000000ff); - rk[13] = rk[5] ^ rk[12]; - rk[14] = rk[6] ^ rk[13]; - rk[15] = rk[7] ^ rk[14]; - - rk += 8; - } - } - return 0; -} - -int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits, AES_KEY *aeskey) -{ - uint32_t *rk; - int i, j, status; - uint32_t temp; - - // first, start with an encryption schedule - status = AES_set_encrypt_key(key, bits, aeskey); - if (status < 0) { - return status; - } - - rk = aeskey->rd_key; - - // invert the order of the round keys: - for (i = 0, j = 4 * aeskey->rounds; i < j; i += 4, j -= 4) { - temp = rk[i]; - rk[i] = rk[j]; - rk[j] = temp; - temp = rk[i + 1]; - rk[i + 1] = rk[j + 1]; - rk[j + 1] = temp; - temp = rk[i + 2]; - rk[i + 2] = rk[j + 2]; - rk[j + 2] = temp; - temp = rk[i + 3]; - rk[i + 3] = rk[j + 3]; - rk[j + 3] = temp; - } - // apply the inverse MixColumn transform to all round keys but the first - // and the last: - for (i = 1; i < (int)aeskey->rounds; i++) { - rk += 4; - rk[0] = Td0[Te1[(rk[0] >> 24)] & 0xff] ^ - Td1[Te1[(rk[0] >> 16) & 0xff] & 0xff] ^ - Td2[Te1[(rk[0] >> 8) & 0xff] & 0xff] ^ - Td3[Te1[(rk[0]) & 0xff] & 0xff]; - rk[1] = Td0[Te1[(rk[1] >> 24)] & 0xff] ^ - Td1[Te1[(rk[1] >> 16) & 0xff] & 0xff] ^ - Td2[Te1[(rk[1] >> 8) & 0xff] & 0xff] ^ - Td3[Te1[(rk[1]) & 0xff] & 0xff]; - rk[2] = Td0[Te1[(rk[2] >> 24)] & 0xff] ^ - Td1[Te1[(rk[2] >> 16) & 0xff] & 0xff] ^ - Td2[Te1[(rk[2] >> 8) & 0xff] & 0xff] ^ - Td3[Te1[(rk[2]) & 0xff] & 0xff]; - rk[3] = Td0[Te1[(rk[3] >> 24)] & 0xff] ^ - Td1[Te1[(rk[3] >> 16) & 0xff] & 0xff] ^ - Td2[Te1[(rk[3] >> 8) & 0xff] & 0xff] ^ - Td3[Te1[(rk[3]) & 0xff] & 0xff]; - } - return 0; -} - -void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key) -{ - const uint32_t *rk; - uint32_t s0, s1, s2, s3, t0, t1, t2, t3; - int r; - - rk = key->rd_key; - - // map byte array block to cipher state - // and add initial round key: - s0 = GETU32(in) ^ rk[0]; - s1 = GETU32(in + 4) ^ rk[1]; - s2 = GETU32(in + 8) ^ rk[2]; - s3 = GETU32(in + 12) ^ rk[3]; - - // Nr - 1 full rounds: - r = key->rounds >> 1; - for (;;) { - t0 = Te0[(s0 >> 24)] ^ Te1[(s1 >> 16) & 0xff] ^ - Te2[(s2 >> 8) & 0xff] ^ Te3[(s3)&0xff] ^ rk[4]; - t1 = Te0[(s1 >> 24)] ^ Te1[(s2 >> 16) & 0xff] ^ - Te2[(s3 >> 8) & 0xff] ^ Te3[(s0)&0xff] ^ rk[5]; - t2 = Te0[(s2 >> 24)] ^ Te1[(s3 >> 16) & 0xff] ^ - Te2[(s0 >> 8) & 0xff] ^ Te3[(s1)&0xff] ^ rk[6]; - t3 = Te0[(s3 >> 24)] ^ Te1[(s0 >> 16) & 0xff] ^ - Te2[(s1 >> 8) & 0xff] ^ Te3[(s2)&0xff] ^ rk[7]; - - rk += 8; - if (--r == 0) { - break; - } - - s0 = Te0[(t0 >> 24)] ^ Te1[(t1 >> 16) & 0xff] ^ - Te2[(t2 >> 8) & 0xff] ^ Te3[(t3)&0xff] ^ rk[0]; - s1 = Te0[(t1 >> 24)] ^ Te1[(t2 >> 16) & 0xff] ^ - Te2[(t3 >> 8) & 0xff] ^ Te3[(t0)&0xff] ^ rk[1]; - s2 = Te0[(t2 >> 24)] ^ Te1[(t3 >> 16) & 0xff] ^ - Te2[(t0 >> 8) & 0xff] ^ Te3[(t1)&0xff] ^ rk[2]; - s3 = Te0[(t3 >> 24)] ^ Te1[(t0 >> 16) & 0xff] ^ - Te2[(t1 >> 8) & 0xff] ^ Te3[(t2)&0xff] ^ rk[3]; - } - - // apply last round and map cipher state to byte array block: - s0 = (Te2[(t0 >> 24)] & 0xff000000) ^ - (Te3[(t1 >> 16) & 0xff] & 0x00ff0000) ^ - (Te0[(t2 >> 8) & 0xff] & 0x0000ff00) ^ - (Te1[(t3)&0xff] & 0x000000ff) ^ rk[0]; - PUTU32(out, s0); - s1 = (Te2[(t1 >> 24)] & 0xff000000) ^ - (Te3[(t2 >> 16) & 0xff] & 0x00ff0000) ^ - (Te0[(t3 >> 8) & 0xff] & 0x0000ff00) ^ - (Te1[(t0)&0xff] & 0x000000ff) ^ rk[1]; - PUTU32(out + 4, s1); - s2 = (Te2[(t2 >> 24)] & 0xff000000) ^ - (Te3[(t3 >> 16) & 0xff] & 0x00ff0000) ^ - (Te0[(t0 >> 8) & 0xff] & 0x0000ff00) ^ - (Te1[(t1)&0xff] & 0x000000ff) ^ rk[2]; - PUTU32(out + 8, s2); - s3 = (Te2[(t3 >> 24)] & 0xff000000) ^ - (Te3[(t0 >> 16) & 0xff] & 0x00ff0000) ^ - (Te0[(t1 >> 8) & 0xff] & 0x0000ff00) ^ - (Te1[(t2)&0xff] & 0x000000ff) ^ rk[3]; - PUTU32(out + 12, s3); -} - -void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key) -{ - const uint32_t *rk; - uint32_t s0, s1, s2, s3, t0, t1, t2, t3; - int r; - - rk = key->rd_key; - - // map byte array block to cipher state - // and add initial round key: - s0 = GETU32(in) ^ rk[0]; - s1 = GETU32(in + 4) ^ rk[1]; - s2 = GETU32(in + 8) ^ rk[2]; - s3 = GETU32(in + 12) ^ rk[3]; - - // Nr - 1 full rounds: - r = key->rounds >> 1; - for (;;) { - t0 = Td0[(s0 >> 24)] ^ Td1[(s3 >> 16) & 0xff] ^ - Td2[(s2 >> 8) & 0xff] ^ Td3[(s1)&0xff] ^ rk[4]; - t1 = Td0[(s1 >> 24)] ^ Td1[(s0 >> 16) & 0xff] ^ - Td2[(s3 >> 8) & 0xff] ^ Td3[(s2)&0xff] ^ rk[5]; - t2 = Td0[(s2 >> 24)] ^ Td1[(s1 >> 16) & 0xff] ^ - Td2[(s0 >> 8) & 0xff] ^ Td3[(s3)&0xff] ^ rk[6]; - t3 = Td0[(s3 >> 24)] ^ Td1[(s2 >> 16) & 0xff] ^ - Td2[(s1 >> 8) & 0xff] ^ Td3[(s0)&0xff] ^ rk[7]; - - rk += 8; - if (--r == 0) { - break; - } - - s0 = Td0[(t0 >> 24)] ^ Td1[(t3 >> 16) & 0xff] ^ - Td2[(t2 >> 8) & 0xff] ^ Td3[(t1)&0xff] ^ rk[0]; - s1 = Td0[(t1 >> 24)] ^ Td1[(t0 >> 16) & 0xff] ^ - Td2[(t3 >> 8) & 0xff] ^ Td3[(t2)&0xff] ^ rk[1]; - s2 = Td0[(t2 >> 24)] ^ Td1[(t1 >> 16) & 0xff] ^ - Td2[(t0 >> 8) & 0xff] ^ Td3[(t3)&0xff] ^ rk[2]; - s3 = Td0[(t3 >> 24)] ^ Td1[(t2 >> 16) & 0xff] ^ - Td2[(t1 >> 8) & 0xff] ^ Td3[(t0)&0xff] ^ rk[3]; - } - - // apply last round and - // map cipher state to byte array block: - s0 = ((uint32_t)Td4[(t0 >> 24)] << 24) ^ - ((uint32_t)Td4[(t3 >> 16) & 0xff] << 16) ^ - ((uint32_t)Td4[(t2 >> 8) & 0xff] << 8) ^ - ((uint32_t)Td4[(t1)&0xff]) ^ rk[0]; - PUTU32(out, s0); - s1 = ((uint32_t)Td4[(t1 >> 24)] << 24) ^ - ((uint32_t)Td4[(t0 >> 16) & 0xff] << 16) ^ - ((uint32_t)Td4[(t3 >> 8) & 0xff] << 8) ^ - ((uint32_t)Td4[(t2)&0xff]) ^ rk[1]; - PUTU32(out + 4, s1); - s2 = ((uint32_t)Td4[(t2 >> 24)] << 24) ^ - ((uint32_t)Td4[(t1 >> 16) & 0xff] << 16) ^ - ((uint32_t)Td4[(t0 >> 8) & 0xff] << 8) ^ - ((uint32_t)Td4[(t3)&0xff]) ^ rk[2]; - PUTU32(out + 8, s2); - s3 = ((uint32_t)Td4[(t3 >> 24)] << 24) ^ - ((uint32_t)Td4[(t2 >> 16) & 0xff] << 16) ^ - ((uint32_t)Td4[(t1 >> 8) & 0xff] << 8) ^ - ((uint32_t)Td4[(t0)&0xff]) ^ rk[3]; - PUTU32(out + 12, s3); -} diff --git a/common/aes.c b/common/aes.c new file mode 120000 index 0000000000..ed10836943 --- /dev/null +++ b/common/aes.c @@ -0,0 +1 @@ +../third_party/boringssl/common/aes.c \ No newline at end of file diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c deleted file mode 100644 index 6b384e3365..0000000000 --- a/common/curve25519-generic.c +++ /dev/null @@ -1,944 +0,0 @@ -/* Copyright 2015, Google Inc. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ - -/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP - * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as - * public domain but this file has the ISC license just to keep licencing - * simple. - * - * The field functions are shared by Ed25519 and X25519 where possible. */ - -#include "curve25519.h" -#include "util.h" - -/* - * fe means field element. Here the field is \Z/(2^255-19). An element t, - * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77 - * t[3]+2^102 t[4]+...+2^230 t[9]. Bounds on each t[i] vary depending on - * context. - */ -typedef int32_t fe[10]; - -static const int64_t kBottom25Bits = INT64_C(0x1ffffff); -static const int64_t kBottom26Bits = INT64_C(0x3ffffff); -static const int64_t kTop39Bits = INT64_C(0xfffffffffe000000); -static const int64_t kTop38Bits = INT64_C(0xfffffffffc000000); - -static uint64_t load_3(const uint8_t *in) -{ - uint64_t result; - result = (uint64_t)in[0]; - result |= ((uint64_t)in[1]) << 8; - result |= ((uint64_t)in[2]) << 16; - return result; -} - -static uint64_t load_4(const uint8_t *in) -{ - uint64_t result; - result = (uint64_t)in[0]; - result |= ((uint64_t)in[1]) << 8; - result |= ((uint64_t)in[2]) << 16; - result |= ((uint64_t)in[3]) << 24; - return result; -} - -static void fe_frombytes(fe h, const uint8_t *s) -{ - /* Ignores top bit of h. */ - int64_t h0 = load_4(s); - int64_t h1 = load_3(s + 4) << 6; - int64_t h2 = load_3(s + 7) << 5; - int64_t h3 = load_3(s + 10) << 3; - int64_t h4 = load_3(s + 13) << 2; - int64_t h5 = load_4(s + 16); - int64_t h6 = load_3(s + 20) << 7; - int64_t h7 = load_3(s + 23) << 5; - int64_t h8 = load_3(s + 26) << 4; - int64_t h9 = (load_3(s + 29) & 8388607) << 2; - int64_t carry0; - int64_t carry1; - int64_t carry2; - int64_t carry3; - int64_t carry4; - int64_t carry5; - int64_t carry6; - int64_t carry7; - int64_t carry8; - int64_t carry9; - - carry9 = h9 + BIT(24); - h0 += (carry9 >> 25) * 19; - h9 -= carry9 & kTop39Bits; - carry1 = h1 + BIT(24); - h2 += carry1 >> 25; - h1 -= carry1 & kTop39Bits; - carry3 = h3 + BIT(24); - h4 += carry3 >> 25; - h3 -= carry3 & kTop39Bits; - carry5 = h5 + BIT(24); - h6 += carry5 >> 25; - h5 -= carry5 & kTop39Bits; - carry7 = h7 + BIT(24); - h8 += carry7 >> 25; - h7 -= carry7 & kTop39Bits; - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - carry2 = h2 + BIT(25); - h3 += carry2 >> 26; - h2 -= carry2 & kTop38Bits; - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - carry6 = h6 + BIT(25); - h7 += carry6 >> 26; - h6 -= carry6 & kTop38Bits; - carry8 = h8 + BIT(25); - h9 += carry8 >> 26; - h8 -= carry8 & kTop38Bits; - - h[0] = h0; - h[1] = h1; - h[2] = h2; - h[3] = h3; - h[4] = h4; - h[5] = h5; - h[6] = h6; - h[7] = h7; - h[8] = h8; - h[9] = h9; -} - -/* Preconditions: - * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. - * - * Write p=2^255-19; q=floor(h/p). - * Basic claim: q = floor(2^(-255)(h + 19 2^(-25)h9 + 2^(-1))). - * - * Proof: - * Have |h|<=p so |q|<=1 so |19^2 2^(-255) q|<1/4. - * Also have |h-2^230 h9|<2^231 so |19 2^(-255)(h-2^230 h9)|<1/4. - * - * Write y=2^(-1)-19^2 2^(-255)q-19 2^(-255)(h-2^230 h9). - * Then 0> 25; - q = (h0 + q) >> 26; - q = (h1 + q) >> 25; - q = (h2 + q) >> 26; - q = (h3 + q) >> 25; - q = (h4 + q) >> 26; - q = (h5 + q) >> 25; - q = (h6 + q) >> 26; - q = (h7 + q) >> 25; - q = (h8 + q) >> 26; - q = (h9 + q) >> 25; - - /* Goal: Output h-(2^255-19)q, which is between 0 and 2^255-20. */ - h0 += 19 * q; - /* Goal: Output h-2^255 q, which is between 0 and 2^255-20. */ - - h1 += h0 >> 26; - h0 &= kBottom26Bits; - h2 += h1 >> 25; - h1 &= kBottom25Bits; - h3 += h2 >> 26; - h2 &= kBottom26Bits; - h4 += h3 >> 25; - h3 &= kBottom25Bits; - h5 += h4 >> 26; - h4 &= kBottom26Bits; - h6 += h5 >> 25; - h5 &= kBottom25Bits; - h7 += h6 >> 26; - h6 &= kBottom26Bits; - h8 += h7 >> 25; - h7 &= kBottom25Bits; - h9 += h8 >> 26; - h8 &= kBottom26Bits; - h9 &= kBottom25Bits; - /* h10 = carry9 */ - - /* Goal: Output h0+...+2^255 h10-2^255 q, which is between 0 and - * 2^255-20. Have h0+...+2^230 h9 between 0 and 2^255-1; evidently 2^255 - * h10-2^255 q = 0. Goal: Output h0+...+2^230 h9. */ - - s[0] = h0 >> 0; - s[1] = h0 >> 8; - s[2] = h0 >> 16; - s[3] = (h0 >> 24) | ((uint32_t)(h1) << 2); - s[4] = h1 >> 6; - s[5] = h1 >> 14; - s[6] = (h1 >> 22) | ((uint32_t)(h2) << 3); - s[7] = h2 >> 5; - s[8] = h2 >> 13; - s[9] = (h2 >> 21) | ((uint32_t)(h3) << 5); - s[10] = h3 >> 3; - s[11] = h3 >> 11; - s[12] = (h3 >> 19) | ((uint32_t)(h4) << 6); - s[13] = h4 >> 2; - s[14] = h4 >> 10; - s[15] = h4 >> 18; - s[16] = h5 >> 0; - s[17] = h5 >> 8; - s[18] = h5 >> 16; - s[19] = (h5 >> 24) | ((uint32_t)(h6) << 1); - s[20] = h6 >> 7; - s[21] = h6 >> 15; - s[22] = (h6 >> 23) | ((uint32_t)(h7) << 3); - s[23] = h7 >> 5; - s[24] = h7 >> 13; - s[25] = (h7 >> 21) | ((uint32_t)(h8) << 4); - s[26] = h8 >> 4; - s[27] = h8 >> 12; - s[28] = (h8 >> 20) | ((uint32_t)(h9) << 6); - s[29] = h9 >> 2; - s[30] = h9 >> 10; - s[31] = h9 >> 18; -} - -/* h = f */ -static void fe_copy(fe h, const fe f) -{ - memmove(h, f, sizeof(int32_t) * 10); -} - -/* h = 0 */ -static void fe_0(fe h) -{ - memset(h, 0, sizeof(int32_t) * 10); -} - -/* h = 1 */ -static void fe_1(fe h) -{ - memset(h, 0, sizeof(int32_t) * 10); - h[0] = 1; -} - -/* h = f + g - * Can overlap h with f or g. - * - * Preconditions: - * |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. - * |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. - * - * Postconditions: - * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */ -static void fe_add(fe h, const fe f, const fe g) -{ - unsigned i; - for (i = 0; i < 10; i++) { - h[i] = f[i] + g[i]; - } -} - -/* h = f - g - * Can overlap h with f or g. - * - * Preconditions: - * |f| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. - * |g| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. - * - * Postconditions: - * |h| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. */ -static void fe_sub(fe h, const fe f, const fe g) -{ - unsigned i; - for (i = 0; i < 10; i++) { - h[i] = f[i] - g[i]; - } -} - -/* h = f * g - * Can overlap h with f or g. - * - * Preconditions: - * |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. - * |g| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. - * - * Postconditions: - * |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc. - * - * Notes on implementation strategy: - * - * Using schoolbook multiplication. - * Karatsuba would save a little in some cost models. - * - * Most multiplications by 2 and 19 are 32-bit precomputations; - * cheaper than 64-bit postcomputations. - * - * There is one remaining multiplication by 19 in the carry chain; - * one *19 precomputation can be merged into this, - * but the resulting data flow is considerably less clean. - * - * There are 12 carries below. - * 10 of them are 2-way parallelizable and vectorizable. - * Can get away with 11 carries, but then data flow is much deeper. - * - * With tighter constraints on inputs can squeeze carries into int32. */ -static void fe_mul(fe h, const fe f, const fe g) -{ - int32_t f0 = f[0]; - int32_t f1 = f[1]; - int32_t f2 = f[2]; - int32_t f3 = f[3]; - int32_t f4 = f[4]; - int32_t f5 = f[5]; - int32_t f6 = f[6]; - int32_t f7 = f[7]; - int32_t f8 = f[8]; - int32_t f9 = f[9]; - int32_t g0 = g[0]; - int32_t g1 = g[1]; - int32_t g2 = g[2]; - int32_t g3 = g[3]; - int32_t g4 = g[4]; - int32_t g5 = g[5]; - int32_t g6 = g[6]; - int32_t g7 = g[7]; - int32_t g8 = g[8]; - int32_t g9 = g[9]; - int32_t g1_19 = 19 * g1; /* 1.959375*2^29 */ - int32_t g2_19 = 19 * g2; /* 1.959375*2^30; still ok */ - int32_t g3_19 = 19 * g3; - int32_t g4_19 = 19 * g4; - int32_t g5_19 = 19 * g5; - int32_t g6_19 = 19 * g6; - int32_t g7_19 = 19 * g7; - int32_t g8_19 = 19 * g8; - int32_t g9_19 = 19 * g9; - int32_t f1_2 = 2 * f1; - int32_t f3_2 = 2 * f3; - int32_t f5_2 = 2 * f5; - int32_t f7_2 = 2 * f7; - int32_t f9_2 = 2 * f9; - int64_t f0g0 = f0 * (int64_t)g0; - int64_t f0g1 = f0 * (int64_t)g1; - int64_t f0g2 = f0 * (int64_t)g2; - int64_t f0g3 = f0 * (int64_t)g3; - int64_t f0g4 = f0 * (int64_t)g4; - int64_t f0g5 = f0 * (int64_t)g5; - int64_t f0g6 = f0 * (int64_t)g6; - int64_t f0g7 = f0 * (int64_t)g7; - int64_t f0g8 = f0 * (int64_t)g8; - int64_t f0g9 = f0 * (int64_t)g9; - int64_t f1g0 = f1 * (int64_t)g0; - int64_t f1g1_2 = f1_2 * (int64_t)g1; - int64_t f1g2 = f1 * (int64_t)g2; - int64_t f1g3_2 = f1_2 * (int64_t)g3; - int64_t f1g4 = f1 * (int64_t)g4; - int64_t f1g5_2 = f1_2 * (int64_t)g5; - int64_t f1g6 = f1 * (int64_t)g6; - int64_t f1g7_2 = f1_2 * (int64_t)g7; - int64_t f1g8 = f1 * (int64_t)g8; - int64_t f1g9_38 = f1_2 * (int64_t)g9_19; - int64_t f2g0 = f2 * (int64_t)g0; - int64_t f2g1 = f2 * (int64_t)g1; - int64_t f2g2 = f2 * (int64_t)g2; - int64_t f2g3 = f2 * (int64_t)g3; - int64_t f2g4 = f2 * (int64_t)g4; - int64_t f2g5 = f2 * (int64_t)g5; - int64_t f2g6 = f2 * (int64_t)g6; - int64_t f2g7 = f2 * (int64_t)g7; - int64_t f2g8_19 = f2 * (int64_t)g8_19; - int64_t f2g9_19 = f2 * (int64_t)g9_19; - int64_t f3g0 = f3 * (int64_t)g0; - int64_t f3g1_2 = f3_2 * (int64_t)g1; - int64_t f3g2 = f3 * (int64_t)g2; - int64_t f3g3_2 = f3_2 * (int64_t)g3; - int64_t f3g4 = f3 * (int64_t)g4; - int64_t f3g5_2 = f3_2 * (int64_t)g5; - int64_t f3g6 = f3 * (int64_t)g6; - int64_t f3g7_38 = f3_2 * (int64_t)g7_19; - int64_t f3g8_19 = f3 * (int64_t)g8_19; - int64_t f3g9_38 = f3_2 * (int64_t)g9_19; - int64_t f4g0 = f4 * (int64_t)g0; - int64_t f4g1 = f4 * (int64_t)g1; - int64_t f4g2 = f4 * (int64_t)g2; - int64_t f4g3 = f4 * (int64_t)g3; - int64_t f4g4 = f4 * (int64_t)g4; - int64_t f4g5 = f4 * (int64_t)g5; - int64_t f4g6_19 = f4 * (int64_t)g6_19; - int64_t f4g7_19 = f4 * (int64_t)g7_19; - int64_t f4g8_19 = f4 * (int64_t)g8_19; - int64_t f4g9_19 = f4 * (int64_t)g9_19; - int64_t f5g0 = f5 * (int64_t)g0; - int64_t f5g1_2 = f5_2 * (int64_t)g1; - int64_t f5g2 = f5 * (int64_t)g2; - int64_t f5g3_2 = f5_2 * (int64_t)g3; - int64_t f5g4 = f5 * (int64_t)g4; - int64_t f5g5_38 = f5_2 * (int64_t)g5_19; - int64_t f5g6_19 = f5 * (int64_t)g6_19; - int64_t f5g7_38 = f5_2 * (int64_t)g7_19; - int64_t f5g8_19 = f5 * (int64_t)g8_19; - int64_t f5g9_38 = f5_2 * (int64_t)g9_19; - int64_t f6g0 = f6 * (int64_t)g0; - int64_t f6g1 = f6 * (int64_t)g1; - int64_t f6g2 = f6 * (int64_t)g2; - int64_t f6g3 = f6 * (int64_t)g3; - int64_t f6g4_19 = f6 * (int64_t)g4_19; - int64_t f6g5_19 = f6 * (int64_t)g5_19; - int64_t f6g6_19 = f6 * (int64_t)g6_19; - int64_t f6g7_19 = f6 * (int64_t)g7_19; - int64_t f6g8_19 = f6 * (int64_t)g8_19; - int64_t f6g9_19 = f6 * (int64_t)g9_19; - int64_t f7g0 = f7 * (int64_t)g0; - int64_t f7g1_2 = f7_2 * (int64_t)g1; - int64_t f7g2 = f7 * (int64_t)g2; - int64_t f7g3_38 = f7_2 * (int64_t)g3_19; - int64_t f7g4_19 = f7 * (int64_t)g4_19; - int64_t f7g5_38 = f7_2 * (int64_t)g5_19; - int64_t f7g6_19 = f7 * (int64_t)g6_19; - int64_t f7g7_38 = f7_2 * (int64_t)g7_19; - int64_t f7g8_19 = f7 * (int64_t)g8_19; - int64_t f7g9_38 = f7_2 * (int64_t)g9_19; - int64_t f8g0 = f8 * (int64_t)g0; - int64_t f8g1 = f8 * (int64_t)g1; - int64_t f8g2_19 = f8 * (int64_t)g2_19; - int64_t f8g3_19 = f8 * (int64_t)g3_19; - int64_t f8g4_19 = f8 * (int64_t)g4_19; - int64_t f8g5_19 = f8 * (int64_t)g5_19; - int64_t f8g6_19 = f8 * (int64_t)g6_19; - int64_t f8g7_19 = f8 * (int64_t)g7_19; - int64_t f8g8_19 = f8 * (int64_t)g8_19; - int64_t f8g9_19 = f8 * (int64_t)g9_19; - int64_t f9g0 = f9 * (int64_t)g0; - int64_t f9g1_38 = f9_2 * (int64_t)g1_19; - int64_t f9g2_19 = f9 * (int64_t)g2_19; - int64_t f9g3_38 = f9_2 * (int64_t)g3_19; - int64_t f9g4_19 = f9 * (int64_t)g4_19; - int64_t f9g5_38 = f9_2 * (int64_t)g5_19; - int64_t f9g6_19 = f9 * (int64_t)g6_19; - int64_t f9g7_38 = f9_2 * (int64_t)g7_19; - int64_t f9g8_19 = f9 * (int64_t)g8_19; - int64_t f9g9_38 = f9_2 * (int64_t)g9_19; - int64_t h0 = f0g0 + f1g9_38 + f2g8_19 + f3g7_38 + f4g6_19 + f5g5_38 + - f6g4_19 + f7g3_38 + f8g2_19 + f9g1_38; - int64_t h1 = f0g1 + f1g0 + f2g9_19 + f3g8_19 + f4g7_19 + f5g6_19 + - f6g5_19 + f7g4_19 + f8g3_19 + f9g2_19; - int64_t h2 = f0g2 + f1g1_2 + f2g0 + f3g9_38 + f4g8_19 + f5g7_38 + - f6g6_19 + f7g5_38 + f8g4_19 + f9g3_38; - int64_t h3 = f0g3 + f1g2 + f2g1 + f3g0 + f4g9_19 + f5g8_19 + f6g7_19 + - f7g6_19 + f8g5_19 + f9g4_19; - int64_t h4 = f0g4 + f1g3_2 + f2g2 + f3g1_2 + f4g0 + f5g9_38 + f6g8_19 + - f7g7_38 + f8g6_19 + f9g5_38; - int64_t h5 = f0g5 + f1g4 + f2g3 + f3g2 + f4g1 + f5g0 + f6g9_19 + - f7g8_19 + f8g7_19 + f9g6_19; - int64_t h6 = f0g6 + f1g5_2 + f2g4 + f3g3_2 + f4g2 + f5g1_2 + f6g0 + - f7g9_38 + f8g8_19 + f9g7_38; - int64_t h7 = f0g7 + f1g6 + f2g5 + f3g4 + f4g3 + f5g2 + f6g1 + f7g0 + - f8g9_19 + f9g8_19; - int64_t h8 = f0g8 + f1g7_2 + f2g6 + f3g5_2 + f4g4 + f5g3_2 + f6g2 + - f7g1_2 + f8g0 + f9g9_38; - int64_t h9 = f0g9 + f1g8 + f2g7 + f3g6 + f4g5 + f5g4 + f6g3 + f7g2 + - f8g1 + f9g0; - int64_t carry0; - int64_t carry1; - int64_t carry2; - int64_t carry3; - int64_t carry4; - int64_t carry5; - int64_t carry6; - int64_t carry7; - int64_t carry8; - int64_t carry9; - - /* |h0| <= - * (1.65*1.65*2^52*(1+19+19+19+19)+1.65*1.65*2^50*(38+38+38+38+38)) i.e. - * |h0| <= 1.4*2^60; narrower ranges for h2, h4, h6, h8 |h1| <= - * (1.65*1.65*2^51*(1+1+19+19+19+19+19+19+19+19)) i.e. |h1| <= 1.7*2^59; - * narrower ranges for h3, h5, h7, h9 */ - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - /* |h0| <= 2^25 */ - /* |h4| <= 2^25 */ - /* |h1| <= 1.71*2^59 */ - /* |h5| <= 1.71*2^59 */ - - carry1 = h1 + BIT(24); - h2 += carry1 >> 25; - h1 -= carry1 & kTop39Bits; - carry5 = h5 + BIT(24); - h6 += carry5 >> 25; - h5 -= carry5 & kTop39Bits; - /* |h1| <= 2^24; from now on fits into int32 */ - /* |h5| <= 2^24; from now on fits into int32 */ - /* |h2| <= 1.41*2^60 */ - /* |h6| <= 1.41*2^60 */ - - carry2 = h2 + BIT(25); - h3 += carry2 >> 26; - h2 -= carry2 & kTop38Bits; - carry6 = h6 + BIT(25); - h7 += carry6 >> 26; - h6 -= carry6 & kTop38Bits; - /* |h2| <= 2^25; from now on fits into int32 unchanged */ - /* |h6| <= 2^25; from now on fits into int32 unchanged */ - /* |h3| <= 1.71*2^59 */ - /* |h7| <= 1.71*2^59 */ - - carry3 = h3 + BIT(24); - h4 += carry3 >> 25; - h3 -= carry3 & kTop39Bits; - carry7 = h7 + BIT(24); - h8 += carry7 >> 25; - h7 -= carry7 & kTop39Bits; - /* |h3| <= 2^24; from now on fits into int32 unchanged */ - /* |h7| <= 2^24; from now on fits into int32 unchanged */ - /* |h4| <= 1.72*2^34 */ - /* |h8| <= 1.41*2^60 */ - - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - carry8 = h8 + BIT(25); - h9 += carry8 >> 26; - h8 -= carry8 & kTop38Bits; - /* |h4| <= 2^25; from now on fits into int32 unchanged */ - /* |h8| <= 2^25; from now on fits into int32 unchanged */ - /* |h5| <= 1.01*2^24 */ - /* |h9| <= 1.71*2^59 */ - - carry9 = h9 + BIT(24); - h0 += (carry9 >> 25) * 19; - h9 -= carry9 & kTop39Bits; - /* |h9| <= 2^24; from now on fits into int32 unchanged */ - /* |h0| <= 1.1*2^39 */ - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - /* |h0| <= 2^25; from now on fits into int32 unchanged */ - /* |h1| <= 1.01*2^24 */ - - h[0] = h0; - h[1] = h1; - h[2] = h2; - h[3] = h3; - h[4] = h4; - h[5] = h5; - h[6] = h6; - h[7] = h7; - h[8] = h8; - h[9] = h9; -} - -/* h = f * f - * Can overlap h with f. - * - * Preconditions: - * |f| bounded by 1.65*2^26,1.65*2^25,1.65*2^26,1.65*2^25,etc. - * - * Postconditions: - * |h| bounded by 1.01*2^25,1.01*2^24,1.01*2^25,1.01*2^24,etc. - * - * See fe_mul.c for discussion of implementation strategy. */ -static void fe_sq(fe h, const fe f) -{ - int32_t f0 = f[0]; - int32_t f1 = f[1]; - int32_t f2 = f[2]; - int32_t f3 = f[3]; - int32_t f4 = f[4]; - int32_t f5 = f[5]; - int32_t f6 = f[6]; - int32_t f7 = f[7]; - int32_t f8 = f[8]; - int32_t f9 = f[9]; - int32_t f0_2 = 2 * f0; - int32_t f1_2 = 2 * f1; - int32_t f2_2 = 2 * f2; - int32_t f3_2 = 2 * f3; - int32_t f4_2 = 2 * f4; - int32_t f5_2 = 2 * f5; - int32_t f6_2 = 2 * f6; - int32_t f7_2 = 2 * f7; - int32_t f5_38 = 38 * f5; /* 1.959375*2^30 */ - int32_t f6_19 = 19 * f6; /* 1.959375*2^30 */ - int32_t f7_38 = 38 * f7; /* 1.959375*2^30 */ - int32_t f8_19 = 19 * f8; /* 1.959375*2^30 */ - int32_t f9_38 = 38 * f9; /* 1.959375*2^30 */ - int64_t f0f0 = f0 * (int64_t)f0; - int64_t f0f1_2 = f0_2 * (int64_t)f1; - int64_t f0f2_2 = f0_2 * (int64_t)f2; - int64_t f0f3_2 = f0_2 * (int64_t)f3; - int64_t f0f4_2 = f0_2 * (int64_t)f4; - int64_t f0f5_2 = f0_2 * (int64_t)f5; - int64_t f0f6_2 = f0_2 * (int64_t)f6; - int64_t f0f7_2 = f0_2 * (int64_t)f7; - int64_t f0f8_2 = f0_2 * (int64_t)f8; - int64_t f0f9_2 = f0_2 * (int64_t)f9; - int64_t f1f1_2 = f1_2 * (int64_t)f1; - int64_t f1f2_2 = f1_2 * (int64_t)f2; - int64_t f1f3_4 = f1_2 * (int64_t)f3_2; - int64_t f1f4_2 = f1_2 * (int64_t)f4; - int64_t f1f5_4 = f1_2 * (int64_t)f5_2; - int64_t f1f6_2 = f1_2 * (int64_t)f6; - int64_t f1f7_4 = f1_2 * (int64_t)f7_2; - int64_t f1f8_2 = f1_2 * (int64_t)f8; - int64_t f1f9_76 = f1_2 * (int64_t)f9_38; - int64_t f2f2 = f2 * (int64_t)f2; - int64_t f2f3_2 = f2_2 * (int64_t)f3; - int64_t f2f4_2 = f2_2 * (int64_t)f4; - int64_t f2f5_2 = f2_2 * (int64_t)f5; - int64_t f2f6_2 = f2_2 * (int64_t)f6; - int64_t f2f7_2 = f2_2 * (int64_t)f7; - int64_t f2f8_38 = f2_2 * (int64_t)f8_19; - int64_t f2f9_38 = f2 * (int64_t)f9_38; - int64_t f3f3_2 = f3_2 * (int64_t)f3; - int64_t f3f4_2 = f3_2 * (int64_t)f4; - int64_t f3f5_4 = f3_2 * (int64_t)f5_2; - int64_t f3f6_2 = f3_2 * (int64_t)f6; - int64_t f3f7_76 = f3_2 * (int64_t)f7_38; - int64_t f3f8_38 = f3_2 * (int64_t)f8_19; - int64_t f3f9_76 = f3_2 * (int64_t)f9_38; - int64_t f4f4 = f4 * (int64_t)f4; - int64_t f4f5_2 = f4_2 * (int64_t)f5; - int64_t f4f6_38 = f4_2 * (int64_t)f6_19; - int64_t f4f7_38 = f4 * (int64_t)f7_38; - int64_t f4f8_38 = f4_2 * (int64_t)f8_19; - int64_t f4f9_38 = f4 * (int64_t)f9_38; - int64_t f5f5_38 = f5 * (int64_t)f5_38; - int64_t f5f6_38 = f5_2 * (int64_t)f6_19; - int64_t f5f7_76 = f5_2 * (int64_t)f7_38; - int64_t f5f8_38 = f5_2 * (int64_t)f8_19; - int64_t f5f9_76 = f5_2 * (int64_t)f9_38; - int64_t f6f6_19 = f6 * (int64_t)f6_19; - int64_t f6f7_38 = f6 * (int64_t)f7_38; - int64_t f6f8_38 = f6_2 * (int64_t)f8_19; - int64_t f6f9_38 = f6 * (int64_t)f9_38; - int64_t f7f7_38 = f7 * (int64_t)f7_38; - int64_t f7f8_38 = f7_2 * (int64_t)f8_19; - int64_t f7f9_76 = f7_2 * (int64_t)f9_38; - int64_t f8f8_19 = f8 * (int64_t)f8_19; - int64_t f8f9_38 = f8 * (int64_t)f9_38; - int64_t f9f9_38 = f9 * (int64_t)f9_38; - int64_t h0 = f0f0 + f1f9_76 + f2f8_38 + f3f7_76 + f4f6_38 + f5f5_38; - int64_t h1 = f0f1_2 + f2f9_38 + f3f8_38 + f4f7_38 + f5f6_38; - int64_t h2 = f0f2_2 + f1f1_2 + f3f9_76 + f4f8_38 + f5f7_76 + f6f6_19; - int64_t h3 = f0f3_2 + f1f2_2 + f4f9_38 + f5f8_38 + f6f7_38; - int64_t h4 = f0f4_2 + f1f3_4 + f2f2 + f5f9_76 + f6f8_38 + f7f7_38; - int64_t h5 = f0f5_2 + f1f4_2 + f2f3_2 + f6f9_38 + f7f8_38; - int64_t h6 = f0f6_2 + f1f5_4 + f2f4_2 + f3f3_2 + f7f9_76 + f8f8_19; - int64_t h7 = f0f7_2 + f1f6_2 + f2f5_2 + f3f4_2 + f8f9_38; - int64_t h8 = f0f8_2 + f1f7_4 + f2f6_2 + f3f5_4 + f4f4 + f9f9_38; - int64_t h9 = f0f9_2 + f1f8_2 + f2f7_2 + f3f6_2 + f4f5_2; - int64_t carry0; - int64_t carry1; - int64_t carry2; - int64_t carry3; - int64_t carry4; - int64_t carry5; - int64_t carry6; - int64_t carry7; - int64_t carry8; - int64_t carry9; - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - - carry1 = h1 + BIT(24); - h2 += carry1 >> 25; - h1 -= carry1 & kTop39Bits; - carry5 = h5 + BIT(24); - h6 += carry5 >> 25; - h5 -= carry5 & kTop39Bits; - - carry2 = h2 + BIT(25); - h3 += carry2 >> 26; - h2 -= carry2 & kTop38Bits; - carry6 = h6 + BIT(25); - h7 += carry6 >> 26; - h6 -= carry6 & kTop38Bits; - - carry3 = h3 + BIT(24); - h4 += carry3 >> 25; - h3 -= carry3 & kTop39Bits; - carry7 = h7 + BIT(24); - h8 += carry7 >> 25; - h7 -= carry7 & kTop39Bits; - - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - carry8 = h8 + BIT(25); - h9 += carry8 >> 26; - h8 -= carry8 & kTop38Bits; - - carry9 = h9 + BIT(24); - h0 += (carry9 >> 25) * 19; - h9 -= carry9 & kTop39Bits; - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - - h[0] = h0; - h[1] = h1; - h[2] = h2; - h[3] = h3; - h[4] = h4; - h[5] = h5; - h[6] = h6; - h[7] = h7; - h[8] = h8; - h[9] = h9; -} - -static void fe_invert(fe out, const fe z) -{ - fe t0; - fe t1; - fe t2; - fe t3; - int i; - - fe_sq(t0, z); - fe_sq(t1, t0); - for (i = 1; i < 2; ++i) { - fe_sq(t1, t1); - } - fe_mul(t1, z, t1); - fe_mul(t0, t0, t1); - fe_sq(t2, t0); - fe_mul(t1, t1, t2); - fe_sq(t2, t1); - for (i = 1; i < 5; ++i) { - fe_sq(t2, t2); - } - fe_mul(t1, t2, t1); - fe_sq(t2, t1); - for (i = 1; i < 10; ++i) { - fe_sq(t2, t2); - } - fe_mul(t2, t2, t1); - fe_sq(t3, t2); - for (i = 1; i < 20; ++i) { - fe_sq(t3, t3); - } - fe_mul(t2, t3, t2); - fe_sq(t2, t2); - for (i = 1; i < 10; ++i) { - fe_sq(t2, t2); - } - fe_mul(t1, t2, t1); - fe_sq(t2, t1); - for (i = 1; i < 50; ++i) { - fe_sq(t2, t2); - } - fe_mul(t2, t2, t1); - fe_sq(t3, t2); - for (i = 1; i < 100; ++i) { - fe_sq(t3, t3); - } - fe_mul(t2, t3, t2); - fe_sq(t2, t2); - for (i = 1; i < 50; ++i) { - fe_sq(t2, t2); - } - fe_mul(t1, t2, t1); - fe_sq(t1, t1); - for (i = 1; i < 5; ++i) { - fe_sq(t1, t1); - } - fe_mul(out, t1, t0); -} - -/* Replace (f,g) with (g,f) if b == 1; - * replace (f,g) with (f,g) if b == 0. - * - * Preconditions: b in {0,1}. */ -static void fe_cswap(fe f, fe g, unsigned int b) -{ - unsigned i; - b = 0 - b; - for (i = 0; i < 10; i++) { - int32_t x = f[i] ^ g[i]; - x &= b; - f[i] ^= x; - g[i] ^= x; - } -} - -/* h = f * 121666 - * Can overlap h with f. - * - * Preconditions: - * |f| bounded by 1.1*2^26,1.1*2^25,1.1*2^26,1.1*2^25,etc. - * - * Postconditions: - * |h| bounded by 1.1*2^25,1.1*2^24,1.1*2^25,1.1*2^24,etc. */ -static void fe_mul121666(fe h, fe f) -{ - int32_t f0 = f[0]; - int32_t f1 = f[1]; - int32_t f2 = f[2]; - int32_t f3 = f[3]; - int32_t f4 = f[4]; - int32_t f5 = f[5]; - int32_t f6 = f[6]; - int32_t f7 = f[7]; - int32_t f8 = f[8]; - int32_t f9 = f[9]; - int64_t h0 = f0 * (int64_t)121666; - int64_t h1 = f1 * (int64_t)121666; - int64_t h2 = f2 * (int64_t)121666; - int64_t h3 = f3 * (int64_t)121666; - int64_t h4 = f4 * (int64_t)121666; - int64_t h5 = f5 * (int64_t)121666; - int64_t h6 = f6 * (int64_t)121666; - int64_t h7 = f7 * (int64_t)121666; - int64_t h8 = f8 * (int64_t)121666; - int64_t h9 = f9 * (int64_t)121666; - int64_t carry0; - int64_t carry1; - int64_t carry2; - int64_t carry3; - int64_t carry4; - int64_t carry5; - int64_t carry6; - int64_t carry7; - int64_t carry8; - int64_t carry9; - - carry9 = h9 + BIT(24); - h0 += (carry9 >> 25) * 19; - h9 -= carry9 & kTop39Bits; - carry1 = h1 + BIT(24); - h2 += carry1 >> 25; - h1 -= carry1 & kTop39Bits; - carry3 = h3 + BIT(24); - h4 += carry3 >> 25; - h3 -= carry3 & kTop39Bits; - carry5 = h5 + BIT(24); - h6 += carry5 >> 25; - h5 -= carry5 & kTop39Bits; - carry7 = h7 + BIT(24); - h8 += carry7 >> 25; - h7 -= carry7 & kTop39Bits; - - carry0 = h0 + BIT(25); - h1 += carry0 >> 26; - h0 -= carry0 & kTop38Bits; - carry2 = h2 + BIT(25); - h3 += carry2 >> 26; - h2 -= carry2 & kTop38Bits; - carry4 = h4 + BIT(25); - h5 += carry4 >> 26; - h4 -= carry4 & kTop38Bits; - carry6 = h6 + BIT(25); - h7 += carry6 >> 26; - h6 -= carry6 & kTop38Bits; - carry8 = h8 + BIT(25); - h9 += carry8 >> 26; - h8 -= carry8 & kTop38Bits; - - h[0] = h0; - h[1] = h1; - h[2] = h2; - h[3] = h3; - h[4] = h4; - h[5] = h5; - h[6] = h6; - h[7] = h7; - h[8] = h8; - h[9] = h9; -} - -void x25519_scalar_mult(uint8_t out[32], const uint8_t scalar[32], - const uint8_t point[32]) -{ - fe x1, x2, z2, x3, z3, tmp0, tmp1; - unsigned swap; - int pos; - - uint8_t e[32]; - memcpy(e, scalar, 32); - e[0] &= 248; - e[31] &= 127; - e[31] |= 64; - fe_frombytes(x1, point); - fe_1(x2); - fe_0(z2); - fe_copy(x3, x1); - fe_1(z3); - - swap = 0; - for (pos = 254; pos >= 0; --pos) { - unsigned b = 1 & (e[pos / 8] >> (pos & 7)); - swap ^= b; - fe_cswap(x2, x3, swap); - fe_cswap(z2, z3, swap); - swap = b; - fe_sub(tmp0, x3, z3); - fe_sub(tmp1, x2, z2); - fe_add(x2, x2, z2); - fe_add(z2, x3, z3); - fe_mul(z3, tmp0, x2); - fe_mul(z2, z2, tmp1); - fe_sq(tmp0, tmp1); - fe_sq(tmp1, x2); - fe_add(x3, z3, z2); - fe_sub(z2, z3, z2); - fe_mul(x2, tmp1, tmp0); - fe_sub(tmp1, tmp1, tmp0); - fe_sq(z2, z2); - fe_mul121666(z3, tmp1); - fe_sq(x3, x3); - fe_add(tmp0, tmp0, z3); - fe_mul(z3, x1, z2); - fe_mul(z2, tmp1, tmp0); - } - fe_cswap(x2, x3, swap); - fe_cswap(z2, z3, swap); - - fe_invert(z2, z2); - fe_mul(x2, x2, z2); - fe_tobytes(out, x2); -} diff --git a/common/curve25519-generic.c b/common/curve25519-generic.c new file mode 120000 index 0000000000..3218a877a2 --- /dev/null +++ b/common/curve25519-generic.c @@ -0,0 +1 @@ +../third_party/boringssl/common/curve25519-generic.c \ No newline at end of file diff --git a/common/curve25519.c b/common/curve25519.c deleted file mode 100644 index 19be3a63a7..0000000000 --- a/common/curve25519.c +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright 2015, Google Inc. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ - -/* This code is mostly taken from the ref10 version of Ed25519 in SUPERCOP - * 20141124 (http://bench.cr.yp.to/supercop.html). That code is released as - * public domain but this file has the ISC license just to keep licencing - * simple. - * - * The field functions are shared by Ed25519 and X25519 where possible. */ - -#include "common.h" -#include "curve25519.h" -#include "trng.h" -#include "util.h" -#define CRYPTO_memcmp safe_memcmp - -#ifdef CONFIG_RNG -void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) -{ - rand_bytes(out_private_key, 32); - - /* All X25519 implementations should decode scalars correctly (see - * https://tools.ietf.org/html/rfc7748#section-5). However, if an - * implementation doesn't then it might interoperate with random keys a - * fraction of the time because they'll, randomly, happen to be - * correctly formed. - * - * Thus we do the opposite of the masking here to make sure that our - * private keys are never correctly masked and so, hopefully, any - * incorrect implementations are deterministically broken. - * - * This does not affect security because, although we're throwing away - * entropy, a valid implementation of scalarmult should throw away the - * exact same bits anyway. */ - out_private_key[0] |= 7; - out_private_key[31] &= 63; - out_private_key[31] |= 128; - - X25519_public_from_private(out_public_value, out_private_key); -} -#endif - -int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32], - const uint8_t peer_public_value[32]) -{ - static const uint8_t kZeros[32] = { 0 }; - x25519_scalar_mult(out_shared_key, private_key, peer_public_value); - /* The all-zero output results when the input is a point of small order. - */ - return CRYPTO_memcmp(kZeros, out_shared_key, 32) != 0; -} - -void X25519_public_from_private(uint8_t out_public_value[32], - const uint8_t private_key[32]) -{ - static const uint8_t kMongomeryBasePoint[32] = { 9 }; - x25519_scalar_mult(out_public_value, private_key, kMongomeryBasePoint); -} diff --git a/common/curve25519.c b/common/curve25519.c new file mode 120000 index 0000000000..aa9bebe86e --- /dev/null +++ b/common/curve25519.c @@ -0,0 +1 @@ +../third_party/boringssl/common/curve25519.c \ No newline at end of file diff --git a/include/aes-gcm.h b/include/aes-gcm.h deleted file mode 100644 index 2227ddb384..0000000000 --- a/include/aes-gcm.h +++ /dev/null @@ -1,141 +0,0 @@ -/* ==================================================================== - * Copyright (c) 2008 The OpenSSL Project. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * 3. All advertising materials mentioning features or use of this - * software must display the following acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" - * - * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to - * endorse or promote products derived from this software without - * prior written permission. For written permission, please contact - * openssl-core@openssl.org. - * - * 5. Products derived from this software may not be called "OpenSSL" - * nor may "OpenSSL" appear in their names without prior written - * permission of the OpenSSL Project. - * - * 6. Redistributions of any form whatsoever must retain the following - * acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit (http://www.openssl.org/)" - * - * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY - * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR - * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * ==================================================================== */ - -#ifndef __CROS_EC_AES_GCM_H -#define __CROS_EC_AES_GCM_H - -#include "common.h" -#include "util.h" - -// block128_f is the type of a 128-bit, block cipher. -typedef void (*block128_f)(const uint8_t in[16], uint8_t out[16], - const void *key); - -// GCM definitions -typedef struct { - uint64_t hi, lo; -} u128; - -// gmult_func multiplies |Xi| by the GCM key and writes the result back to -// |Xi|. -typedef void (*gmult_func)(uint64_t Xi[2], const u128 Htable[16]); - -// ghash_func repeatedly multiplies |Xi| by the GCM key and adds in blocks from -// |inp|. The result is written back to |Xi| and the |len| argument must be a -// multiple of 16. -typedef void (*ghash_func)(uint64_t Xi[2], const u128 Htable[16], - const uint8_t *inp, size_t len); - -// This differs from upstream's |gcm128_context| in that it does not have the -// |key| pointer, in order to make it |memcpy|-friendly. Rather the key is -// passed into each call that needs it. -struct gcm128_context { - // Following 6 names follow names in GCM specification - union { - uint64_t u[2]; - uint32_t d[4]; - uint8_t c[16]; - size_t t[16 / sizeof(size_t)]; - } Yi, EKi, EK0, len, Xi; - - // Note that the order of |Xi|, |H| and |Htable| is fixed by the - // MOVBE-based, x86-64, GHASH assembly. - u128 H; - u128 Htable[16]; - gmult_func gmult; - ghash_func ghash; - - unsigned int mres, ares; - block128_f block; -}; - -// GCM. -// -// This API differs from the upstream API slightly. The |GCM128_CONTEXT| does -// not have a |key| pointer that points to the key as upstream's version does. -// Instead, every function takes a |key| parameter. This way |GCM128_CONTEXT| -// can be safely copied. - -typedef struct gcm128_context GCM128_CONTEXT; - -// CRYPTO_gcm128_init initialises |ctx| to use |block| (typically AES) with -// the given key. |block_is_hwaes| is one if |block| is |aes_hw_encrypt|. -void CRYPTO_gcm128_init(GCM128_CONTEXT *ctx, const void *key, block128_f block, - int block_is_hwaes); - -// CRYPTO_gcm128_setiv sets the IV (nonce) for |ctx|. The |key| must be the -// same key that was passed to |CRYPTO_gcm128_init|. -void CRYPTO_gcm128_setiv(GCM128_CONTEXT *ctx, const void *key, - const uint8_t *iv, size_t iv_len); - -// CRYPTO_gcm128_aad sets the authenticated data for an instance of GCM. -// This must be called before and data is encrypted. It returns one on success -// and zero otherwise. -int CRYPTO_gcm128_aad(GCM128_CONTEXT *ctx, const uint8_t *aad, size_t len); - -// CRYPTO_gcm128_encrypt encrypts |len| bytes from |in| to |out|. The |key| -// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one -// on success and zero otherwise. -int CRYPTO_gcm128_encrypt(GCM128_CONTEXT *ctx, const void *key, - const uint8_t *in, uint8_t *out, size_t len); - -// CRYPTO_gcm128_decrypt decrypts |len| bytes from |in| to |out|. The |key| -// must be the same key that was passed to |CRYPTO_gcm128_init|. It returns one -// on success and zero otherwise. -int CRYPTO_gcm128_decrypt(GCM128_CONTEXT *ctx, const void *key, - const uint8_t *in, uint8_t *out, size_t len); - -// CRYPTO_gcm128_finish calculates the authenticator and compares it against -// |len| bytes of |tag|. It returns one on success and zero otherwise. -int CRYPTO_gcm128_finish(GCM128_CONTEXT *ctx, const uint8_t *tag, size_t len); - -// CRYPTO_gcm128_tag calculates the authenticator and copies it into |tag|. -// The minimum of |len| and 16 bytes are copied into |tag|. -void CRYPTO_gcm128_tag(GCM128_CONTEXT *ctx, uint8_t *tag, size_t len); - -#endif // __CROS_EC_AES_GCM_H diff --git a/include/aes-gcm.h b/include/aes-gcm.h new file mode 120000 index 0000000000..ba62939792 --- /dev/null +++ b/include/aes-gcm.h @@ -0,0 +1 @@ +../third_party/boringssl/include/aes-gcm.h \ No newline at end of file diff --git a/include/aes.h b/include/aes.h deleted file mode 100644 index 67a9002f4f..0000000000 --- a/include/aes.h +++ /dev/null @@ -1,129 +0,0 @@ -/* ==================================================================== - * Copyright (c) 2002-2006 The OpenSSL Project. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * 3. All advertising materials mentioning features or use of this - * software must display the following acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit. (http://www.openssl.org/)" - * - * 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to - * endorse or promote products derived from this software without - * prior written permission. For written permission, please contact - * openssl-core@openssl.org. - * - * 5. Products derived from this software may not be called "OpenSSL" - * nor may "OpenSSL" appear in their names without prior written - * permission of the OpenSSL Project. - * - * 6. Redistributions of any form whatsoever must retain the following - * acknowledgment: - * "This product includes software developed by the OpenSSL Project - * for use in the OpenSSL Toolkit (http://www.openssl.org/)" - * - * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY - * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR - * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. - * ==================================================================== */ - -#ifndef __CROS_EC_AES_H -#define __CROS_EC_AES_H - -#include - -#define AES_ENCRYPT 1 -#define AES_DECRYPT 0 - -/* AES_MAXNR is the maximum number of AES rounds. */ -#define AES_MAXNR 14 - -#define AES_BLOCK_SIZE 16 - -/* - * aes_key_st should be an opaque type, but EVP requires that the size be - * known. - */ -struct aes_key_st { - uint32_t rd_key[4 * (AES_MAXNR + 1)]; - unsigned rounds; -}; -typedef struct aes_key_st AES_KEY; - -/* - * These functions are provided by either common/aes.c, or assembly code, - * and should not be called directly. - */ -void aes_nohw_encrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key); -void aes_nohw_decrypt(const uint8_t *in, uint8_t *out, const AES_KEY *key); -int aes_nohw_set_encrypt_key(const uint8_t *key, unsigned bits, - AES_KEY *aeskey); -int aes_nohw_set_decrypt_key(const uint8_t *key, unsigned bits, - AES_KEY *aeskey); - -/** - * AES_set_encrypt_key configures |aeskey| to encrypt with the |bits|-bit key, - * |key|. - * - * WARNING: unlike other OpenSSL functions, this returns zero on success and a - * negative number on error. - */ -static inline int AES_set_encrypt_key(const uint8_t *key, unsigned int bits, - AES_KEY *aeskey) -{ - return aes_nohw_set_encrypt_key(key, bits, aeskey); -} - -/** - * AES_set_decrypt_key configures |aeskey| to decrypt with the |bits|-bit key, - * |key|. - * - * WARNING: unlike other OpenSSL functions, this returns zero on success and a - * negative number on error. - */ -static inline int AES_set_decrypt_key(const uint8_t *key, unsigned int bits, - AES_KEY *aeskey) -{ - return aes_nohw_set_decrypt_key(key, bits, aeskey); -} - -/** - * AES_encrypt encrypts a single block from |in| to |out| with |key|. The |in| - * and |out| pointers may overlap. - */ -static inline void AES_encrypt(const uint8_t *in, uint8_t *out, - const AES_KEY *key) -{ - aes_nohw_encrypt(in, out, key); -} - -/** - * AES_decrypt decrypts a single block from |in| to |out| with |key|. The |in| - * and |out| pointers may overlap. - */ -static inline void AES_decrypt(const uint8_t *in, uint8_t *out, - const AES_KEY *key) -{ - aes_nohw_decrypt(in, out, key); -} - -#endif /* __CROS_EC_AES_H */ diff --git a/include/aes.h b/include/aes.h new file mode 120000 index 0000000000..b30c680a6a --- /dev/null +++ b/include/aes.h @@ -0,0 +1 @@ +../third_party/boringssl/include/aes.h \ No newline at end of file diff --git a/include/curve25519.h b/include/curve25519.h deleted file mode 100644 index 447790ec45..0000000000 --- a/include/curve25519.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CURVE25519_H -#define __CROS_EC_CURVE25519_H - -#include - -/* Curve25519. - * - * Curve25519 is an elliptic curve. See https://tools.ietf.org/html/rfc7748. - */ - -/* X25519. - * - * X25519 is the Diffie-Hellman primitive built from curve25519. It is - * sometimes referred to as “curve25519”, but “X25519” is a more precise - * name. - * See http://cr.yp.to/ecdh.html and https://tools.ietf.org/html/rfc7748. - */ - -#define X25519_PRIVATE_KEY_LEN 32 -#define X25519_PUBLIC_VALUE_LEN 32 - -/** - * Generate a public/private key pair. - * @param out_public_value generated public key. - * @param out_private_value generated private key. - */ -void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]); - -/** - * Diffie-Hellman function. - * @param out_shared_key - * @param private_key - * @param out_public_value - * @return one on success and zero on error. - * - * X25519() writes a shared key to @out_shared_key that is calculated from the - * given private key and the peer's public value. - * - * Don't use the shared key directly, rather use a KDF and also include the two - * public values as inputs. - */ -int X25519(uint8_t out_shared_key[32], const uint8_t private_key[32], - const uint8_t peers_public_value[32]); - -/** - * Compute the matching public key. - * @param out_public_value computed public key. - * @param private_key private key to use. - * - * X25519_public_from_private() calculates a Diffie-Hellman public value from - * the given private key and writes it to @out_public_value. - */ -void X25519_public_from_private(uint8_t out_public_value[32], - const uint8_t private_key[32]); - -/* - * Low-level x25519 function, defined by either the generic or cortex-m0 - * implementation. Must not be called directly. - */ -void x25519_scalar_mult(uint8_t out[32], const uint8_t scalar[32], - const uint8_t point[32]); - -#endif /* __CROS_EC_CURVE25519_H */ diff --git a/include/curve25519.h b/include/curve25519.h new file mode 120000 index 0000000000..b9943bd4ac --- /dev/null +++ b/include/curve25519.h @@ -0,0 +1 @@ +../third_party/boringssl/include/curve25519.h \ No newline at end of file diff --git a/test/x25519.c b/test/x25519.c deleted file mode 100644 index 239369dac9..0000000000 --- a/test/x25519.c +++ /dev/null @@ -1,196 +0,0 @@ -/* Copyright (c) 2015, Google Inc. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY - * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION - * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ - -#include "console.h" -#include "common.h" -#include "curve25519.h" -#include "test_util.h" -#include "timer.h" -#include "util.h" -#include "watchdog.h" - -/* - * Define this to test 1 million iterations of x25519 (takes up to - * a few minutes on host, up to a few days on microcontroller). - */ -#undef TEST_X25519_1M_ITERATIONS - -static int test_x25519(void) -{ - /* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */ - static const uint8_t scalar1[32] = { - 0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d, - 0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd, - 0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18, - 0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4, - }; - static const uint8_t point1[32] = { - 0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb, - 0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c, - 0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b, - 0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c, - }; - static const uint8_t expected1[32] = { - 0xc3, 0xda, 0x55, 0x37, 0x9d, 0xe9, 0xc6, 0x90, - 0x8e, 0x94, 0xea, 0x4d, 0xf2, 0x8d, 0x08, 0x4f, - 0x32, 0xec, 0xcf, 0x03, 0x49, 0x1c, 0x71, 0xf7, - 0x54, 0xb4, 0x07, 0x55, 0x77, 0xa2, 0x85, 0x52, - }; - static const uint8_t scalar2[32] = { - 0x4b, 0x66, 0xe9, 0xd4, 0xd1, 0xb4, 0x67, 0x3c, - 0x5a, 0xd2, 0x26, 0x91, 0x95, 0x7d, 0x6a, 0xf5, - 0xc1, 0x1b, 0x64, 0x21, 0xe0, 0xea, 0x01, 0xd4, - 0x2c, 0xa4, 0x16, 0x9e, 0x79, 0x18, 0xba, 0x0d, - }; - static const uint8_t point2[32] = { - 0xe5, 0x21, 0x0f, 0x12, 0x78, 0x68, 0x11, 0xd3, - 0xf4, 0xb7, 0x95, 0x9d, 0x05, 0x38, 0xae, 0x2c, - 0x31, 0xdb, 0xe7, 0x10, 0x6f, 0xc0, 0x3c, 0x3e, - 0xfc, 0x4c, 0xd5, 0x49, 0xc7, 0x15, 0xa4, 0x93, - }; - static const uint8_t expected2[32] = { - 0x95, 0xcb, 0xde, 0x94, 0x76, 0xe8, 0x90, 0x7d, - 0x7a, 0xad, 0xe4, 0x5c, 0xb4, 0xb8, 0x73, 0xf8, - 0x8b, 0x59, 0x5a, 0x68, 0x79, 0x9f, 0xa1, 0x52, - 0xe6, 0xf8, 0xf7, 0x64, 0x7a, 0xac, 0x79, 0x57, - }; - uint8_t out[32]; - - X25519(out, scalar1, point1); - - if (memcmp(expected1, out, sizeof(out)) != 0) { - ccprintf("X25519 test one failed.\n"); - return 0; - } - - X25519(out, scalar2, point2); - - if (memcmp(expected2, out, sizeof(out)) != 0) { - ccprintf("X25519 test two failed.\n"); - return 0; - } - - return 1; -} - -static int test_x25519_small_order(void) -{ - static const uint8_t kSmallOrderPoint[32] = { - 0xe0, 0xeb, 0x7a, 0x7c, 0x3b, 0x41, 0xb8, 0xae, - 0x16, 0x56, 0xe3, 0xfa, 0xf1, 0x9f, 0xc4, 0x6a, - 0xda, 0x09, 0x8d, 0xeb, 0x9c, 0x32, 0xb1, 0xfd, - 0x86, 0x62, 0x05, 0x16, 0x5f, 0x49, 0xb8, - }; - uint8_t out[32], private_key[32]; - - memset(private_key, 0x11, sizeof(private_key)); - - if (X25519(out, private_key, kSmallOrderPoint)) { - ccprintf("X25519 returned success with a small-order input.\n"); - return 0; - } - - return 1; -} - -static int test_x25519_iterated(void) -{ - /* Taken from https://tools.ietf.org/html/rfc7748#section-5.2 */ - static const uint8_t expected_1K[32] = { - 0x68, 0x4c, 0xf5, 0x9b, 0xa8, 0x33, 0x09, 0x55, - 0x28, 0x00, 0xef, 0x56, 0x6f, 0x2f, 0x4d, 0x3c, - 0x1c, 0x38, 0x87, 0xc4, 0x93, 0x60, 0xe3, 0x87, - 0x5f, 0x2e, 0xb9, 0x4d, 0x99, 0x53, 0x2c, 0x51, - }; -#ifdef TEST_X25519_1M_ITERATIONS - static const uint8_t expected_1M[32] = { - 0x7c, 0x39, 0x11, 0xe0, 0xab, 0x25, 0x86, 0xfd, - 0x86, 0x44, 0x97, 0x29, 0x7e, 0x57, 0x5e, 0x6f, - 0x3b, 0xc6, 0x01, 0xc0, 0x88, 0x3c, 0x30, 0xdf, - 0x5f, 0x4d, 0xd2, 0xd2, 0x4f, 0x66, 0x54, 0x24 - }; -#endif - uint8_t scalar[32] = { 9 }, point[32] = { 9 }, out[32]; - unsigned i; - - for (i = 0; i < 1000; i++) { - watchdog_reload(); - X25519(out, scalar, point); - memcpy(point, scalar, sizeof(point)); - memcpy(scalar, out, sizeof(scalar)); - } - - if (memcmp(expected_1K, scalar, sizeof(expected_1K)) != 0) { - ccprintf("1,000 iterations X25519 test failed\n"); - return 0; - } - -#ifdef TEST_X25519_1M_ITERATIONS - for (; i < 1000000; i++) { - watchdog_reload(); - X25519(out, scalar, point); - memcpy(point, scalar, sizeof(point)); - memcpy(scalar, out, sizeof(scalar)); - if ((i % 10000) == 0) - ccprints("%d", i); - } - - if (memcmp(expected_1M, scalar, sizeof(expected_1M)) != 0) { - ccprintf("1,000,000 iterations X25519 test failed\n"); - return 0; - } -#endif - - return 1; -} - -static void test_x25519_speed(void) -{ - static const uint8_t scalar1[32] = { - 0xa5, 0x46, 0xe3, 0x6b, 0xf0, 0x52, 0x7c, 0x9d, - 0x3b, 0x16, 0x15, 0x4b, 0x82, 0x46, 0x5e, 0xdd, - 0x62, 0x14, 0x4c, 0x0a, 0xc1, 0xfc, 0x5a, 0x18, - 0x50, 0x6a, 0x22, 0x44, 0xba, 0x44, 0x9a, 0xc4, - }; - static const uint8_t point1[32] = { - 0xe6, 0xdb, 0x68, 0x67, 0x58, 0x30, 0x30, 0xdb, - 0x35, 0x94, 0xc1, 0xa4, 0x24, 0xb1, 0x5f, 0x7c, - 0x72, 0x66, 0x24, 0xec, 0x26, 0xb3, 0x35, 0x3b, - 0x10, 0xa9, 0x03, 0xa6, 0xd0, 0xab, 0x1c, 0x4c, - }; - uint8_t out[32]; - timestamp_t t0, t1; - - X25519(out, scalar1, point1); - t0 = get_time(); - X25519(out, scalar1, point1); - t1 = get_time(); - ccprintf("X25519 duration %lld us\n", (long long)(t1.val - t0.val)); -} - -void run_test(int argc, char **argv) -{ - watchdog_reload(); - /* do not check speed, just as a benchmark */ - test_x25519_speed(); - - watchdog_reload(); - if (!test_x25519() || !test_x25519_iterated() || - !test_x25519_small_order()) { - test_fail(); - return; - } - - test_pass(); -} diff --git a/test/x25519.c b/test/x25519.c new file mode 120000 index 0000000000..75aefa9842 --- /dev/null +++ b/test/x25519.c @@ -0,0 +1 @@ +../third_party/boringssl/test/x25519.c \ No newline at end of file -- cgit v1.2.1 From a63f39313801dfbd4eeeeac4ec3b8cb8c59f0545 Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Sat, 2 Jul 2022 02:07:57 +0000 Subject: TCPMV2: Gate Alert USB PD 3.1 fields on partner revision Extended alert events were added in USB PD 3.1, but will currently be sent to all USB PD 3.0 partners. This CL clears ADO fields added in USB PD 3.1 before sending alerts to USB PD 3.0 partners. If clearing the extended alert bits sets the ADO to 0, it will not send the alert. BUG=b:237336333 BRANCH=None TEST=Checked alert was not being sent to USB PD 3.0 parnter on power state change, and passing all unit tests (make runhosttests). Signed-off-by: Jameson Thies Change-Id: Ic6d9db0f0aff00b04e9c9ab892219bbcb6451f4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3741508 Reviewed-by: Diana Z --- common/usb_common.c | 17 +++++++++++++++++ include/usb_pd.h | 1 + 2 files changed, 18 insertions(+) diff --git a/common/usb_common.c b/common/usb_common.c index 022580af0d..372d55d2a0 100644 --- a/common/usb_common.c +++ b/common/usb_common.c @@ -1025,6 +1025,23 @@ int pd_send_alert_msg(int port, uint32_t ado) { #if defined(CONFIG_USB_PD_TCPMV2) && defined(CONFIG_USB_PE_SM) && \ !defined(CONFIG_USB_VPD) && !defined(CONFIG_USB_CTVPD) + struct rmdo partner_rmdo; + + /* + * The Alert Data Object (ADO) definition changed between USB PD + * Revision 3.0 and 3.1. Clear reserved bits from the USB PD 3.0 + * ADO before sending to a USB PD 3.0 partner and block the + * message if the ADO is empty. + */ + partner_rmdo = pe_get_partner_rmdo(port); + if (partner_rmdo.major_rev == 0) { + ado &= ~(ADO_EXTENDED_ALERT_EVENT | + ADO_EXTENDED_ALERT_EVENT_TYPE); + } + + if (!ado) + return EC_ERROR_INVAL; + if (pe_set_ado(port, ado) != EC_SUCCESS) return EC_ERROR_BUSY; diff --git a/include/usb_pd.h b/include/usb_pd.h index aaf365d389..4304c60c7a 100644 --- a/include/usb_pd.h +++ b/include/usb_pd.h @@ -1283,6 +1283,7 @@ enum pd_ext_msg_type { /* Alert Data Object fields for REV 3.1 */ #define ADO_EXTENDED_ALERT_EVENT (BIT(24) << 7) +#define ADO_EXTENDED_ALERT_EVENT_TYPE 0xf /* Alert Data Object fields for REV 3.0 */ #define ADO_OVP_EVENT (BIT(24) << 6) #define ADO_SOURCE_INPUT_CHANGE (BIT(24) << 5) -- cgit v1.2.1 From c1415ecc5fc7ace6e91115e73b97e7034b329d2b Mon Sep 17 00:00:00 2001 From: Andrea Grandi Date: Thu, 30 Jun 2022 10:12:40 -0700 Subject: test/test_config.h: Enable AES for crypto benchamrk Configure the build of AES and AES-GCM for crypto benchmark tests BUG=b:235476822 BRANCH=none TEST=none Cq-Depend: chrome-internal:4847231 Signed-off-by: Andrea Grandi Change-Id: I63ed76b21a33548e294389b4a14857e7409fb704 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3736984 Reviewed-by: Bobby Casey --- test/test_config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_config.h b/test/test_config.h index f4370cd80e..1a63db5de3 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -22,7 +22,7 @@ #undef CONFIG_VBOOT_HASH #undef CONFIG_USB_PD_LOGGING -#ifdef TEST_AES +#if defined(TEST_AES) || defined(TEST_CRYPTO_BENCHMARK) #define CONFIG_AES #define CONFIG_AES_GCM #endif -- cgit v1.2.1 From 738de2b575de93f71f3a95f9294b9006f4f7b008 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 17:15:14 -0700 Subject: trng: Rename rand to trng_rand The declaration for rand conflicts with the standard library declaration so rename it from "rand" to "trng_rand". This has the benefit of making it obvious when we're using the true random number generator. For consistency, this also renames init_trng/exit_trng to trng_init/trng_exit. This is a reland of commit a6b0b3554f59cc9b0c4aae9bff7dff075f2089a9. BRANCH=none BUG=b:234181908, b:237344361 TEST=./util/compare_build.sh -b all -j 120 => MATCH TEST=emerge-hatch ec-utils-test Signed-off-by: Tom Hughes Change-Id: Ic26890572cb9865275c866b65b0532c5ab029865 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3738978 Reviewed-by: Jack Rosenthal Reviewed-by: Bobby Casey --- chip/host/trng.c | 6 +++--- chip/stm32/trng.c | 22 +++++++++++----------- common/fpsensor/fpsensor.c | 26 +++++++++++++------------- common/rollback.c | 6 +++--- extra/rma_reset/rma_reset.c | 4 ++-- include/trng.h | 12 +++++------- third_party/boringssl/common/curve25519.c | 2 +- 7 files changed, 38 insertions(+), 40 deletions(-) diff --git a/chip/host/trng.c b/chip/host/trng.c index d54983f3a1..e2c13d7d14 100644 --- a/chip/host/trng.c +++ b/chip/host/trng.c @@ -21,17 +21,17 @@ static unsigned int seed; -test_mockable void init_trng(void) +test_mockable void trng_init(void) { seed = 0; srand(seed); } -test_mockable void exit_trng(void) +test_mockable void trng_exit(void) { } -test_mockable void rand_bytes(void *buffer, size_t len) +test_mockable void trng_rand_bytes(void *buffer, size_t len) { uint8_t *b, *end; diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 6927786c48..6538263add 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -15,7 +15,7 @@ #include "trng.h" #include "util.h" -uint32_t rand(void) +uint32_t trng_rand(void) { int tries = 300; /* Wait for a valid random number */ @@ -28,10 +28,10 @@ uint32_t rand(void) return STM32_RNG_DR; } -test_mockable void rand_bytes(void *buffer, size_t len) +test_mockable void trng_rand_bytes(void *buffer, size_t len) { while (len) { - uint32_t number = rand(); + uint32_t number = trng_rand(); size_t cnt = 4; /* deal with the lack of alignment guarantee in the API */ uintptr_t align = (uintptr_t)buffer & 3; @@ -47,7 +47,7 @@ test_mockable void rand_bytes(void *buffer, size_t len) } } -test_mockable void init_trng(void) +test_mockable void trng_init(void) { #ifdef CHIP_FAMILY_STM32L4 /* Enable the 48Mhz internal RC oscillator */ @@ -84,7 +84,7 @@ test_mockable void init_trng(void) STM32_RNG_CR |= STM32_RNG_CR_RNGEN; } -test_mockable void exit_trng(void) +test_mockable void trng_exit(void) { STM32_RNG_CR &= ~STM32_RNG_CR_RNGEN; STM32_RCC_AHB2ENR &= ~STM32_RCC_AHB2ENR_RNGEN; @@ -107,9 +107,9 @@ static int command_rand(int argc, char **argv) { uint8_t data[32]; - init_trng(); - rand_bytes(data, sizeof(data)); - exit_trng(); + trng_init(); + trng_rand_bytes(data, sizeof(data)); + trng_exit(); ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); @@ -130,9 +130,9 @@ static enum ec_status host_command_rand(struct host_cmd_handler_args *args) if (num_rand_bytes > args->response_max) return EC_RES_OVERFLOW; - init_trng(); - rand_bytes(r->rand, num_rand_bytes); - exit_trng(); + trng_init(); + trng_rand_bytes(r->rand, num_rand_bytes); + trng_exit(); args->response_size = num_rand_bytes; diff --git a/common/fpsensor/fpsensor.c b/common/fpsensor/fpsensor.c index 263a9d0888..101dd06a35 100644 --- a/common/fpsensor/fpsensor.c +++ b/common/fpsensor/fpsensor.c @@ -475,11 +475,11 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) */ enc_info = (void *)fp_enc_buffer; enc_info->struct_version = FP_TEMPLATE_FORMAT_VERSION; - init_trng(); - rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); - rand_bytes(enc_info->encryption_salt, - FP_CONTEXT_ENCRYPTION_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(enc_info->nonce, FP_CONTEXT_NONCE_BYTES); + trng_rand_bytes(enc_info->encryption_salt, + FP_CONTEXT_ENCRYPTION_SALT_BYTES); + trng_exit(); if (fgr == template_newly_enrolled) { /* @@ -488,10 +488,10 @@ static enum ec_status fp_command_frame(struct host_cmd_handler_args *args) * value. */ template_newly_enrolled = FP_NO_SUCH_TEMPLATE; - init_trng(); - rand_bytes(fp_positive_match_salt[fgr], - FP_POSITIVE_MATCH_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(fp_positive_match_salt[fgr], + FP_POSITIVE_MATCH_SALT_BYTES); + trng_exit(); } ret = derive_encryption_key(key, enc_info->encryption_salt); @@ -646,10 +646,10 @@ static enum ec_status fp_command_template(struct host_cmd_handler_args *args) sizeof(fp_template[0])); if (template_needs_validation_value(enc_info)) { CPRINTS("fgr%d: Generating positive match salt.", idx); - init_trng(); - rand_bytes(positive_match_salt, - FP_POSITIVE_MATCH_SALT_BYTES); - exit_trng(); + trng_init(); + trng_rand_bytes(positive_match_salt, + FP_POSITIVE_MATCH_SALT_BYTES); + trng_exit(); } if (bytes_are_trivial(positive_match_salt, sizeof(fp_positive_match_salt[0]))) { diff --git a/common/rollback.c b/common/rollback.c index 65779fc473..21a0273f12 100644 --- a/common/rollback.c +++ b/common/rollback.c @@ -398,9 +398,9 @@ static void add_entropy_deferred(void) if (add_entropy_action == ADD_ENTROPY_RESET_ASYNC) repeat = ROLLBACK_REGIONS; - init_trng(); + trng_init(); do { - rand_bytes(rand, sizeof(rand)); + trng_rand_bytes(rand, sizeof(rand)); if (rollback_add_entropy(rand, sizeof(rand)) != EC_SUCCESS) { add_entropy_rv = EC_RES_ERROR; goto out; @@ -409,7 +409,7 @@ static void add_entropy_deferred(void) add_entropy_rv = EC_RES_SUCCESS; out: - exit_trng(); + trng_exit(); } DECLARE_DEFERRED(add_entropy_deferred); diff --git a/extra/rma_reset/rma_reset.c b/extra/rma_reset/rma_reset.c index 950b1227fd..c5a4b4f647 100644 --- a/extra/rma_reset/rma_reset.c +++ b/extra/rma_reset/rma_reset.c @@ -97,7 +97,7 @@ static const struct option long_opts[] = { }; void panic_assert_fail(const char *fname, int linenum); -void rand_bytes(void *buffer, size_t len); +void trng_rand_bytes(void *buffer, size_t len); int safe_memcmp(const void *s1, const void *s2, size_t size); void panic_assert_fail(const char *fname, int linenum) @@ -120,7 +120,7 @@ int safe_memcmp(const void *s1, const void *s2, size_t size) return result != 0; } -void rand_bytes(void *buffer, size_t len) +void trng_rand_bytes(void *buffer, size_t len) { RAND_bytes(buffer, len); } diff --git a/include/trng.h b/include/trng.h index cea4555b41..969366ae8e 100644 --- a/include/trng.h +++ b/include/trng.h @@ -14,32 +14,30 @@ * * Not supported by all platforms. **/ -void init_trng(void); +void trng_init(void); /** * Shutdown the true random number generator. * - * The opposite operation of init_trng(), disable the hardware resources + * The opposite operation of trng_init(), disable the hardware resources * used by the TRNG to save power. * * Not supported by all platforms. **/ -void exit_trng(void); +void trng_exit(void); /** * Retrieve a 32 bit random value. * * Not supported on all platforms. **/ -#ifndef HIDE_EC_STDLIB -uint32_t rand(void); -#endif +uint32_t trng_rand(void); /** * Output len random bytes into buffer. * * Not supported on all platforms. **/ -void rand_bytes(void *buffer, size_t len); +void trng_rand_bytes(void *buffer, size_t len); #endif /* __EC_INCLUDE_TRNG_H */ diff --git a/third_party/boringssl/common/curve25519.c b/third_party/boringssl/common/curve25519.c index 2a7fad6509..b74d3c7d97 100644 --- a/third_party/boringssl/common/curve25519.c +++ b/third_party/boringssl/common/curve25519.c @@ -27,7 +27,7 @@ #ifdef CONFIG_RNG void X25519_keypair(uint8_t out_public_value[32], uint8_t out_private_key[32]) { - rand_bytes(out_private_key, 32); + trng_rand_bytes(out_private_key, 32); /* All X25519 implementations should decode scalars correctly (see * https://tools.ietf.org/html/rfc7748#section-5). However, if an -- cgit v1.2.1 From 8523520d17176c6903daa1c769637e154bc6ba67 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 1 Jul 2022 17:15:04 -0600 Subject: AMD: Remove S0ix interrupt enable/disable Initially, the S0ix interrupts were being enabled and disabled since they were copied from the Intel power sequencing code. However, this isn't necessary on AMD and causes problems on platforms which share the S3 and S0ix signaling. BRANCH=None BUG=b:237581881 TEST=on skyrim, ensure repeated boots and suspend work. On nipperkin, ensure suspend stress test runs well Signed-off-by: Diana Z Change-Id: I7119091064cfafe0ab7cfba756c95e9561ec362a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3741226 Reviewed-by: Raul Rangel --- power/amd_x86.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/power/amd_x86.c b/power/amd_x86.c index af426a567b..9b4300671d 100644 --- a/power/amd_x86.c +++ b/power/amd_x86.c @@ -300,7 +300,6 @@ power_chipset_handle_host_sleep_event(enum host_sleep_event state, sleep_set_notify(SLEEP_NOTIFY_SUSPEND); sleep_start_suspend(ctx); - power_signal_enable_interrupt(GPIO_PCH_SLP_S0_L); } else if (state == HOST_SLEEP_EVENT_S0IX_RESUME) { /* * Wake up chipset task and indicate to power state machine that @@ -309,7 +308,6 @@ power_chipset_handle_host_sleep_event(enum host_sleep_event state, sleep_set_notify(SLEEP_NOTIFY_RESUME); task_wake(TASK_ID_CHIPSET); lpc_s0ix_resume_restore_masks(); - power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L); sleep_complete_resume(ctx); /* * If the sleep signal timed out and never transitioned, then @@ -318,8 +316,6 @@ power_chipset_handle_host_sleep_event(enum host_sleep_event state, * mask to its S0 state now. */ power_update_wake_mask(); - } else if (state == HOST_SLEEP_EVENT_DEFAULT_RESET) { - power_signal_disable_interrupt(GPIO_PCH_SLP_S0_L); } #endif /* CONFIG_POWER_S0IX */ } -- cgit v1.2.1 From a669fb296e5b2824f6f5ba404f1ecd9015c191cf Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Mon, 4 Jul 2022 15:30:17 +1000 Subject: anx7483: Add default tuning to ANX7483 mux configuration Add the default tuning function for the ANX7483 devicetree USB mux configuration. BUG=b:233170580 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: I7cb7082e155a94380d7289187184eac0659954cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739110 Reviewed-by: Diana Z --- driver/retimer/anx7483.c | 4 ++-- include/driver/retimer/anx7483_public.h | 9 ++++++--- zephyr/shim/include/usbc/anx7483_usb_mux.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index beb1149715..ac0150179d 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -286,8 +286,8 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me, return EC_SUCCESS; } -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state) +int anx7483_set_default_tuning(const struct usb_mux *me, + mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index c578bdf618..bc7c6bbc0f 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -52,9 +52,12 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, enum anx7483_tune_pin pin, enum anx7483_eq_setting eq); -/* Configure datasheet defaults for tuning registers at this mux setting */ -enum ec_error_list anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state); +/* + * Configure datasheet defaults for tuning registers at this mux setting. + * Return int so function can be used directly for board_set. + */ +int anx7483_set_default_tuning(const struct usb_mux *me, + mux_state_t mux_state); extern const struct usb_mux_driver anx7483_usb_retimer_driver; #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */ diff --git a/zephyr/shim/include/usbc/anx7483_usb_mux.h b/zephyr/shim/include/usbc/anx7483_usb_mux.h index 35c859ff2e..a36f00671d 100644 --- a/zephyr/shim/include/usbc/anx7483_usb_mux.h +++ b/zephyr/shim/include/usbc/anx7483_usb_mux.h @@ -14,6 +14,7 @@ { \ USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ .driver = &anx7483_usb_retimer_driver, \ + .board_set = &anx7483_set_default_tuning, \ .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ .i2c_addr_flags = \ DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ -- cgit v1.2.1 From 35f1cc1f598df4dabbb418535cb99b6b4fb9ff85 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Mon, 4 Jul 2022 10:58:34 +1000 Subject: zephyr: Move AMD power signals to common include Move AMD power signal definition from gpio_map.h to common include file. This impacts the skyrim project, but guybrush has not been modified since it appears it is no longer maintained. BUG=b:237725681 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: Ifac429bc9a649de887ba759e9481b6f0cd81c271 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742839 Reviewed-by: Diana Z --- include/power/amd_x86.h | 29 +++++++++++++++++++++++++++++ power/amd_x86.c | 1 + power/common.c | 1 + zephyr/projects/skyrim/include/gpio_map.h | 12 ------------ zephyr/projects/skyrim/power_signals.c | 1 + 5 files changed, 32 insertions(+), 12 deletions(-) create mode 100644 include/power/amd_x86.h diff --git a/include/power/amd_x86.h b/include/power/amd_x86.h new file mode 100644 index 0000000000..58d73d6c3c --- /dev/null +++ b/include/power/amd_x86.h @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_POWER_AMD_X86_H_ +#define __CROS_EC_POWER_AMD_X86_H_ + +/* + * In legacy EC-OS, the power signals are defined as part of + * the board include headers, but with Zephyr, this is common. + */ +#if defined(CONFIG_ZEPHYR) && defined(CONFIG_AP_X86_AMD) + +/* Power input signals */ +enum power_signal { + X86_SLP_S3_N, /* SOC -> SLP_S3_L */ + X86_SLP_S5_N, /* SOC -> SLP_S5_L */ + + X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ + X86_S5_PGOOD, /* PMIC -> S5_PWROK */ + + /* Number of X86 signals */ + POWER_SIGNAL_COUNT, +}; + +#endif + +#endif /* __CROS_EC_POWER_AMD_X86_H_ */ diff --git a/power/amd_x86.c b/power/amd_x86.c index 9b4300671d..3a407dfdf5 100644 --- a/power/amd_x86.c +++ b/power/amd_x86.c @@ -13,6 +13,7 @@ #include "hooks.h" #include "lid_switch.h" #include "lpc.h" +#include "power/amd_x86.h" #include "power.h" #include "power_button.h" #include "system.h" diff --git a/power/common.c b/power/common.c index 8b807f8364..256a60d0b1 100644 --- a/power/common.c +++ b/power/common.c @@ -18,6 +18,7 @@ #include "host_command.h" #include "lpc.h" #include "power.h" +#include "power/amd_x86.h" #include "power/intel_x86.h" #include "power/qcom.h" #include "system.h" diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index 9d88da8056..336791982b 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -9,18 +9,6 @@ #include #include -/* Power input signals */ -enum power_signal { - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT, -}; - #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED #define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index 16847ba608..8de1c833c4 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -11,6 +11,7 @@ #include "hooks.h" #include "ioexpander.h" #include "power.h" +#include "power/amd_x86.h" #include "timer.h" /* Power Signal Input List */ -- cgit v1.2.1 From 2812e1d237ae63c4db42006bdff51df5fecf7a12 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Tue, 28 Jun 2022 10:30:52 -0600 Subject: zephyr: emul: Track number of DP entry attempts In the PD partner emulator, track the number of attempts by the TCPM to enter DisplayPort mode. This will support tests to verify that the TCPM does not retry DP mode entry forever. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I3cae20a37610194b60cba3c26d4b84cefa58c415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733068 Reviewed-by: Aaron Massey --- zephyr/emul/tcpc/emul_tcpci_partner_common.c | 4 ++++ zephyr/include/emul/tcpc/emul_tcpci_partner_common.h | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/zephyr/emul/tcpc/emul_tcpci_partner_common.c b/zephyr/emul/tcpc/emul_tcpci_partner_common.c index 9c9d3d8268..5f4b6c81a8 100644 --- a/zephyr/emul/tcpc/emul_tcpci_partner_common.c +++ b/zephyr/emul/tcpc/emul_tcpci_partner_common.c @@ -31,6 +31,7 @@ void tcpci_partner_common_hard_reset_as_role(struct tcpci_partner_data *data, data->data_role = power_role == PD_ROLE_SOURCE ? PD_ROLE_DFP : PD_ROLE_UFP; data->displayport_configured = false; + atomic_clear(&data->displayport_enter_attempts); } /** @@ -646,6 +647,7 @@ tcpci_partner_common_vdm_handler(struct tcpci_partner_data *data, data->dp_enter_mode_vdos, 0); } + atomic_inc(&data->displayport_enter_attempts); return TCPCI_PARTNER_COMMON_MSG_HANDLED; case CMD_EXIT_MODE: if (PD_VDO_VID(vdm_header) == USB_SID_DISPLAYPORT) { @@ -1024,6 +1026,7 @@ void tcpci_partner_common_disconnect(struct tcpci_partner_data *data) tcpci_partner_stop_sender_response_timer(data); data->tcpci_emul = NULL; data->displayport_configured = false; + atomic_clear(&data->displayport_enter_attempts); } int tcpci_partner_common_enable_pd_logging(struct tcpci_partner_data *data, @@ -1396,6 +1399,7 @@ void tcpci_partner_init(struct tcpci_partner_data *data, enum pd_rev_type rev) data->ops.control_change = NULL; data->ops.disconnect = tcpci_partner_disconnect_op; data->displayport_configured = false; + atomic_clear(&data->displayport_enter_attempts); /* Reset the data structure used to store battery capability responses */ diff --git a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h index f995246de6..795abcbd8c 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h +++ b/zephyr/include/emul/tcpc/emul_tcpci_partner_common.h @@ -14,6 +14,7 @@ #include #include +#include #include #include @@ -130,6 +131,10 @@ struct tcpci_partner_data { enum tcpci_emul_tx_status *received_msg_status; /** Whether port partner is configured in DisplayPort mode */ bool displayport_configured; + /** The number of DisplayPort Enter Mode REQs received since connection + * or the last Hard Reset, whichever was more recent. + */ + atomic_t displayport_enter_attempts; /* VDMs with which the partner responds to discovery REQs. The VDM * buffers include the VDM header, and the VDO counts include 1 for the -- cgit v1.2.1 From 0733c1f77f7331c499cdf89ab42e4a514ad2d789 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Fri, 24 Jun 2022 14:21:44 -0600 Subject: zephyr: test: Verify with dysfunctional DP adapter Configure a PD partner emulator to advertise support for DisplayPort but refuse to Enter Mode. Verify that triggering DP entry via host command does not result in infinite DP Enter Mode retries. BUG=b:235984702 TEST=zmake testall BRANCH=none Signed-off-by: Abe Levkoy Change-Id: If9e573c79a222fffde8d900a77b6e1bddc776dc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724163 Reviewed-by: Aaron Massey --- .../drivers/src/integration/usbc/usb_alt_mode.c | 98 ++++++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index ebc2816d1a..0e3c59a59b 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -29,6 +29,13 @@ struct usbc_alt_mode_fixture { struct tcpci_snk_emul_data snk_ext; }; +struct usbc_alt_mode_dp_unsupported_fixture { + const struct emul *tcpci_emul; + const struct emul *charger_emul; + struct tcpci_partner_data partner; + struct tcpci_snk_emul_data snk_ext; +}; + static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture) { const struct emul *tcpc_emul = fixture->tcpci_emul; @@ -154,6 +161,36 @@ static void *usbc_alt_mode_setup(void) return &fixture; } +static void *usbc_alt_mode_dp_unsupported_setup(void) +{ + static struct usbc_alt_mode_fixture fixture; + struct tcpci_partner_data *partner = &fixture.partner; + struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; + + tcpci_partner_init(partner, PD_REV20); + partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); + + /* Get references for the emulators */ + fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + /* The configured TCPCI rev must match the emulator's supported rev. */ + tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); + fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + /* + * Respond to discovery REQs to indicate DisplayPort support, but do not + * respond to DisplayPort alt mode VDMs, including Enter Mode. + */ + add_discovery_responses(partner); + + /* Sink 5V 3A. */ + snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + + return &fixture; +} + static void usbc_alt_mode_before(void *data) { /* Set chipset to ON, this will set TCPM to DRP */ @@ -274,3 +311,64 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, usbc_alt_mode_before, usbc_alt_mode_after, NULL); + +/* + * When the partner advertises DP mode support but refuses to enter, discovery + * should still work as if the partner were compliant. + */ +ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; + struct ec_response_typec_discovery *discovery = + (struct ec_response_typec_discovery *)response_buffer; + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, + response_buffer, sizeof(response_buffer)); + + /* The host command does not count the VDM header in identity_count. */ + zassert_equal(discovery->identity_count, + fixture->partner.identity_vdos - 1, + "Expected %d identity VDOs, got %d", + fixture->partner.identity_vdos - 1, + discovery->identity_count); + zassert_mem_equal(discovery->discovery_vdo, + fixture->partner.identity_vdm + 1, + discovery->identity_count * + sizeof(*discovery->discovery_vdo), + "Discovered SOP identity ACK did not match"); + zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", + discovery->svid_count); + zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, + "Expected SVID 0x%0000x, got 0x%0000x", + USB_SID_DISPLAYPORT, discovery->svids[0].svid); + zassert_equal(discovery->svids[0].mode_count, 1, + "Expected 1 DP mode, got %d", + discovery->svids[0].mode_count); + zassert_equal(discovery->svids[0].mode_vdo[0], + fixture->partner.modes_vdm[1], + "DP mode VDOs did not match"); +} + +/* + * When the partner advertises DP support but refuses to enter DP mode, the TCPM + * should try once and then give up. + */ +ZTEST_F(usbc_alt_mode_dp_unsupported, verify_displayport_mode_nonentry) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + zassert_false(fixture->partner.displayport_configured, NULL); + int dp_attempts = + atomic_get(&fixture->partner.displayport_enter_attempts); + zassert_equal(dp_attempts, 1, "Expected 1 DP attempt, got %d", + dp_attempts); +} + +ZTEST_SUITE(usbc_alt_mode_dp_unsupported, drivers_predicate_post_main, + usbc_alt_mode_dp_unsupported_setup, usbc_alt_mode_before, + usbc_alt_mode_after, NULL); -- cgit v1.2.1 From ebc002b2641a25b5c3a0b8733b9ceb5e7271a692 Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Mon, 4 Jul 2022 19:28:26 +0800 Subject: osiris: Update EN_PP5000_FAN init state Set EN_PP5000_FAN init low to prevent fan turn to full speed when ec boot. BUG=b:234545460 BRANCH=none TEST=check fan will not turn to full speed when ec reboot. Signed-off-by: Yu-An Chen Change-Id: Ic10a4c7247a3663028674cf59f3e3cb8faff0556 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742855 Commit-Queue: Boris Mittelberg Reviewed-by: Boris Mittelberg --- board/osiris/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc index 32d75fa81b..015647f995 100644 --- a/board/osiris/gpio.inc +++ b/board/osiris/gpio.inc @@ -59,7 +59,7 @@ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_R_ODL, PIN(C, 0), GPIO_ODR_HIGH) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) -GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_HIGH) +GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_LOW) GPIO(EN_PP5000_USBA_R, PIN(D, 7), GPIO_OUT_LOW) GPIO(EN_S5_RAILS, PIN(B, 6), GPIO_OUT_LOW) GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT) -- cgit v1.2.1 From 18f92b91999a3b21e723e1775239555726b5111a Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Wed, 6 Jul 2022 17:58:06 +0000 Subject: zephyr: Move tests requiring a USB PD 3.0 partner to usb_pd_rev3.c Currently a couple zephyr tests which require a USB PD 3.0 partner work by calling prl_set_rev to fake a USB PD 3.0 parnter. Instead, these tests should be in usb_pd_rev3.c where partner revision is set during test setup. BUG=b:236975670 BRANCH=None TEST=zmake test test-drivers Signed-off-by: Jameson Thies Change-Id: I9b74c7775ec33d4248d89b3d3ebe56fd23d4e88c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748617 Reviewed-by: Tristan Honscheid --- .../src/integration/usbc/usb_5v_3a_pd_sink.c | 32 ------------ .../src/integration/usbc/usb_5v_3a_pd_source.c | 60 ---------------------- .../drivers/src/integration/usbc/usb_pd_rev3.c | 57 ++++++++++++++++++-- 3 files changed, 54 insertions(+), 95 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c index f7f73d42b0..278a6508da 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_sink.c @@ -11,15 +11,10 @@ #include "emul/emul_smart_battery.h" #include "emul/tcpc/emul_tcpci_partner_snk.h" #include "tcpm/tcpci.h" -#include "test/drivers/stubs.h" #include "test/drivers/test_state.h" #include "test/drivers/utils.h" #include "timer.h" -#include "usb_common.h" #include "usb_pd.h" -#include "usb_prl_sm.h" - -#define TEST_USB_PORT USBC_PORT_C0 struct usb_attach_5v_3a_pd_sink_fixture { struct tcpci_partner_data sink_5v_3a; @@ -293,30 +288,3 @@ ZTEST_F(usb_attach_5v_3a_pd_sink, verify_ping_msg) zassert_true(fixture->snk_ext.ping_received, NULL); } - -/** - * @brief TestPurpose: Verify Alert message. - * - * @details - * - Clear alert_received in emulated partner - * - Broadcast PD Alert - * - Check pd_broadcast_alert_msg can set the ADO and run pd_dpm_request - * - Check that emulated partner received a PD_DATA_ALERT message - * - * Expected Results - * - EC_SUCCESS returned from pd_broadcast_alert_msg - * - sink_5v_3a.data.alert_received is true - */ -ZTEST_F(usb_attach_5v_3a_pd_sink, verify_alert_msg) -{ - /* Setting partner PD Rev to 3.0 to ungate Alert DPM request */ - /* TODO(b/236975670): move to dedicated USB PD Rev 3.0 test file */ - prl_set_rev(TEST_USB_PORT, TCPCI_MSG_SOP, PD_REV30); - - tcpci_snk_emul_clear_alert_received(&fixture->snk_ext); - zassert_false(fixture->snk_ext.alert_received, NULL); - zassert_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL); - - k_sleep(K_SECONDS(2)); - zassert_true(fixture->snk_ext.alert_received, NULL); -} diff --git a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c index be4fdc4982..2139c75af1 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_5v_3a_pd_source.c @@ -9,17 +9,12 @@ #include "emul/emul_isl923x.h" #include "emul/emul_smart_battery.h" #include "emul/tcpc/emul_tcpci_partner_src.h" -#include "hooks.h" -#include "test/drivers/stubs.h" #include "test/drivers/test_state.h" #include "test/drivers/utils.h" #include "usb_pd.h" -#include "usb_prl_sm.h" #define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) -#define TEST_USB_PORT USBC_PORT_C0 - struct usb_attach_5v_3a_pd_source_fixture { struct tcpci_partner_data source_5v_3a; struct tcpci_src_emul_data src_ext; @@ -212,58 +207,3 @@ ZTEST_F(usb_attach_5v_3a_pd_source, test_disconnect_power_info) "Expected the PD current limit to be >= 0, but got %dmA", power_info.meas.current_lim); } - -ZTEST_F(usb_attach_5v_3a_pd_source, verify_dock_with_power_button) -{ - /* Clear Alert and Status receive checks */ - tcpci_src_emul_clear_alert_received(&fixture->src_ext); - tcpci_src_emul_clear_status_received(&fixture->src_ext); - zassert_false(fixture->src_ext.alert_received, NULL); - zassert_false(fixture->src_ext.status_received, NULL); - - /* Setting up revision for the full Status message */ - prl_set_rev(TEST_USB_PORT, TCPCI_MSG_SOP, PD_REV30); - k_sleep(K_MSEC(10)); - pd_dpm_request(TEST_USB_PORT, DPM_REQUEST_GET_REVISION); - k_sleep(K_MSEC(10)); - - /* Suspend and check partner received Alert and Status messages */ - hook_notify(HOOK_CHIPSET_SUSPEND); - k_sleep(K_SECONDS(2)); - zassert_true(fixture->src_ext.alert_received, NULL); - zassert_true(fixture->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&fixture->src_ext); - tcpci_src_emul_clear_status_received(&fixture->src_ext); - zassert_false(fixture->src_ext.alert_received, NULL); - zassert_false(fixture->src_ext.status_received, NULL); - - /* Shutdown and check partner received Alert and Status messages */ - hook_notify(HOOK_CHIPSET_SHUTDOWN); - k_sleep(K_SECONDS(2)); - zassert_true(fixture->src_ext.alert_received, NULL); - zassert_true(fixture->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&fixture->src_ext); - tcpci_src_emul_clear_status_received(&fixture->src_ext); - zassert_false(fixture->src_ext.alert_received, NULL); - zassert_false(fixture->src_ext.status_received, NULL); - - /* Startup and check partner received Alert and Status messages */ - hook_notify(HOOK_CHIPSET_STARTUP); - k_sleep(K_SECONDS(2)); - zassert_true(fixture->src_ext.alert_received, NULL); - zassert_true(fixture->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&fixture->src_ext); - tcpci_src_emul_clear_status_received(&fixture->src_ext); - zassert_false(fixture->src_ext.alert_received, NULL); - zassert_false(fixture->src_ext.status_received, NULL); - - /* Resume and check partner received Alert and Status messages */ - hook_notify(HOOK_CHIPSET_RESUME); - k_sleep(K_SECONDS(2)); - zassert_true(fixture->src_ext.alert_received, NULL); - zassert_true(fixture->src_ext.status_received, NULL); - tcpci_src_emul_clear_alert_received(&fixture->src_ext); - tcpci_src_emul_clear_status_received(&fixture->src_ext); - zassert_false(fixture->src_ext.alert_received, NULL); - zassert_false(fixture->src_ext.status_received, NULL); -} diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c index a12521f19e..1d09daa36d 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c @@ -14,14 +14,12 @@ #include "test/drivers/stubs.h" #include "test/drivers/test_state.h" #include "test/drivers/utils.h" +#include "usb_common.h" #include "usb_pd.h" -#include "usb_prl_sm.h" #include "util.h" #define BATTERY_ORD DT_DEP_ORD(DT_NODELABEL(battery)) -#define TEST_USB_PORT USBC_PORT_C0 - struct usb_attach_5v_3a_pd_source_rev3_fixture { struct tcpci_partner_data source_5v_3a; struct tcpci_src_emul_data src_ext; @@ -46,6 +44,12 @@ static void *usb_attach_5v_3a_pd_source_setup(void) test_fixture.src_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + /* Clear Alert and Status receive checks */ + tcpci_src_emul_clear_alert_received(&test_fixture.src_ext); + tcpci_src_emul_clear_status_received(&test_fixture.src_ext); + zassume_false(test_fixture.src_ext.alert_received, NULL); + zassume_false(test_fixture.src_ext.status_received, NULL); + return &test_fixture; } @@ -156,3 +160,50 @@ ZTEST_F(usb_attach_5v_3a_pd_source_rev3, test_batt_cap_invalid) BIT(0), "Invalid battery ref bit should be set"); } + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_alert_msg) +{ + zassume_equal(pd_broadcast_alert_msg(ADO_OTP_EVENT), EC_SUCCESS, NULL); + + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); +} + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_dock_with_power_button) +{ + /* Suspend and check partner received Alert and Status messages */ + hook_notify(HOOK_CHIPSET_SUSPEND); + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); + + /* Shutdown and check partner received Alert and Status messages */ + hook_notify(HOOK_CHIPSET_SHUTDOWN); + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); + + /* Startup and check partner received Alert and Status messages */ + hook_notify(HOOK_CHIPSET_STARTUP); + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); + + /* Resume and check partner received Alert and Status messages */ + hook_notify(HOOK_CHIPSET_RESUME); + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); +} -- cgit v1.2.1 From 838855b22a8936c354de0a1da9a208dcf1556898 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Fri, 1 Jul 2022 15:41:27 +1000 Subject: zephyr: Allow GPIO enum name aliases for legacy code support Allow named-gpios enum names to have legacy aliases for common code. This supports the existing legacy code that uses generic names for GPIO references to alias these names to board specific enum names. BUG=b:237716584 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: Ia7acb47eabcab5e71c72190b5cae8ce13d36f1c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739987 Reviewed-by: Jack Rosenthal --- zephyr/dts/bindings/gpio/named-gpios.yaml | 8 ++++++++ zephyr/projects/brya/gpio.dts | 2 ++ zephyr/projects/brya/include/gpio_map.h | 7 ------- zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts | 1 + zephyr/projects/intelrvp/include/gpio_map.h | 1 - zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts | 1 + zephyr/projects/skyrim/gpio.dts | 1 + zephyr/projects/skyrim/include/gpio_map.h | 1 - zephyr/shim/include/zephyr_gpio_signal.h | 16 +++++++++++++++- 9 files changed, 28 insertions(+), 10 deletions(-) diff --git a/zephyr/dts/bindings/gpio/named-gpios.yaml b/zephyr/dts/bindings/gpio/named-gpios.yaml index 59ed404754..5c1e581509 100644 --- a/zephyr/dts/bindings/gpio/named-gpios.yaml +++ b/zephyr/dts/bindings/gpio/named-gpios.yaml @@ -27,5 +27,13 @@ child-binding: according to the flags in the gpios node. type: boolean required: false + alias: + description: + When set, defines an alias for this GPIO's enum-name. + + This is to allow common or generic names in legacy code to map + to the particular board's GPIO name. + type: string + required: false led-pin-cells: - value diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts index 7f7d5e77eb..517dea8ef4 100644 --- a/zephyr/projects/brya/gpio.dts +++ b/zephyr/projects/brya/gpio.dts @@ -132,10 +132,12 @@ gpio_pg_ec_dsw_pwrok: pg_ec_dsw_pwrok { gpios = <&gpioc 7 GPIO_INPUT>; enum-name = "GPIO_PG_EC_DSW_PWROK"; + alias = "GPIO_SEQ_EC_DSW_PWROK"; }; en_s5_rails { gpios = <&gpiob 6 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_S5_RAILS"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; sys_rst_odl { gpios = <&gpioc 5 GPIO_ODR_HIGH>; diff --git a/zephyr/projects/brya/include/gpio_map.h b/zephyr/projects/brya/include/gpio_map.h index 83d819d110..4ebfbe31b6 100644 --- a/zephyr/projects/brya/include/gpio_map.h +++ b/zephyr/projects/brya/include/gpio_map.h @@ -11,11 +11,4 @@ #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#define GPIO_SEQ_EC_DSW_PWROK GPIO_PG_EC_DSW_PWROK - -/* TODO(fabiobaltieri): make this a named-temp-sensors property, deprecate the - * Kconfig option. - */ -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_S5_RAILS - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index cab165cd33..6c3c965d66 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -124,6 +124,7 @@ ec-ds3 { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; pch-pwrok-ec { gpios = <&gpioa 0 GPIO_INPUT>; diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h index 01110dbe7d..3c723e21c8 100644 --- a/zephyr/projects/intelrvp/include/gpio_map.h +++ b/zephyr/projects/intelrvp/include/gpio_map.h @@ -7,7 +7,6 @@ #define __ZEPHYR_GPIO_MAP_H #define GPIO_EN_PP5000 GPIO_UNIMPLEMENTED -#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A /* TODO: Implement GPIO_ENTERING_RW in IOEX */ #ifdef CONFIG_BOARD_MTLRVP_NPCX diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts index 49a40c6a54..c3cd9e6abb 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -115,6 +115,7 @@ ec-ds3-r { gpios = <&gpioc 4 GPIO_OUTPUT_LOW>; enum-name = "GPIO_EN_PP3300_A"; + alias = "GPIO_TEMP_SENSOR_POWER"; }; pch-pwrok-ec-r { gpios = <&gpiod 3 GPIO_ODR_LOW>; diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index fd28d80df3..57097598ae 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -22,6 +22,7 @@ gpio_slp_s3_l: slp_s3_l { gpios = <&gpio6 1 GPIO_INPUT>; enum-name = "GPIO_PCH_SLP_S3_L"; + alias = "GPIO_PCH_SLP_S0_L"; }; gpio_slp_s5_l: slp_s5_l { gpios = <&gpio7 2 GPIO_INPUT>; diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index 336791982b..67ba4fa9ad 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -11,6 +11,5 @@ #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED #define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED -#define GPIO_PCH_SLP_S0_L GPIO_PCH_SLP_S3_L #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h index 3f56ccf259..e7514bfc5e 100644 --- a/zephyr/shim/include/zephyr_gpio_signal.h +++ b/zephyr/shim/include/zephyr_gpio_signal.h @@ -41,19 +41,33 @@ #define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id) #define GPIO_SIGNAL_WITH_COMMA(id) GPIO_SIGNAL(id), +/* + * Create a list of aliases to allow remapping of aliased names. + */ +#define GPIO_DT_MK_ALIAS(id) \ + DT_STRING_UPPER_TOKEN(id, alias) = DT_STRING_UPPER_TOKEN(id, enum_name), + +#define GPIO_DT_ALIAS_LIST(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, alias), (GPIO_DT_MK_ALIAS(id)), ()) + enum gpio_signal { GPIO_UNIMPLEMENTED = -1, #if DT_NODE_EXISTS(DT_PATH(named_gpios)) DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_SIGNAL_WITH_COMMA) #endif GPIO_COUNT, - GPIO_LIMIT = 0x0FFF, +#if DT_NODE_EXISTS(DT_PATH(named_gpios)) + DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_ALIAS_LIST) +#endif + GPIO_LIMIT = 0x0FFF, IOEX_SIGNAL_START = GPIO_LIMIT + 1, IOEX_SIGNAL_END = IOEX_SIGNAL_START, IOEX_LIMIT = 0x1FFF, }; #undef GPIO_SIGNAL_WITH_COMMA +#undef GPIO_DT_ALIAS_LIST +#undef GPIO_DT_MK_ALIAS BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT); -- cgit v1.2.1 From f78ba0618bfbdf408accfb208b6a6302edd3f2a5 Mon Sep 17 00:00:00 2001 From: Ivan Chen Date: Mon, 20 Jun 2022 21:34:06 +0800 Subject: beadrix: board_set_active_charge_port cleanup Skip unnecessarily port disabling to avoid PD timer expiration due to TCPC re-init BUG=b:234304246 TEST=emerge-dedede chromeos-ec, charging test with two beadrix setup BRANCH=none Change-Id: Iafbdb62abbc56880d20bcfb1492f378ca4f8c3f3 Signed-off-by: Ivan Chen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3714689 Reviewed-by: Diana Z --- board/beadrix/board.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/board/beadrix/board.c b/board/beadrix/board.c index 52d643ecd2..fc5a53b9ee 100644 --- a/board/beadrix/board.c +++ b/board/beadrix/board.c @@ -431,22 +431,23 @@ int board_set_active_charge_port(int port) * Turn off the other ports' sink path FETs, before enabling the * requested charge port. */ - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (i == port) - continue; - - if (tcpc_write(i, TCPC_REG_COMMAND, - TCPC_REG_COMMAND_SNK_CTRL_LOW)) - CPRINTS("p%d: sink path disable failed.", i); - raa489000_enable_asgate(i, false); - } + if (old_port != CHARGE_PORT_NONE && old_port != port) { + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; - /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) - */ - if (old_port != CHARGE_PORT_NONE) + if (tcpc_write(i, TCPC_REG_COMMAND, + TCPC_REG_COMMAND_SNK_CTRL_LOW)) + CPRINTS("p%d: sink path disable failed.", i); + raa489000_enable_asgate(i, false); + } + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ charger_discharge_on_ac(1); + } /* Enable requested charge port. */ if (raa489000_enable_asgate(port, true) || -- cgit v1.2.1 From 2e69ddb351b1ac56119bd14e13fe9466a94589a3 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Fri, 1 Jul 2022 12:05:22 +1000 Subject: corsola: Relocate GPIO definitions from gpio_map.h Relocate GPIO aliases from gpio_map.h to local include BUG=b:237716584 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: I24440c19ae78e0041f13e0ad08bcc104009118b6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739982 Reviewed-by: Eric Yilun Lin --- zephyr/projects/corsola/include/baseboard_usbc_config.h | 6 ++++++ zephyr/projects/corsola/include/gpio_map.h | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/zephyr/projects/corsola/include/baseboard_usbc_config.h b/zephyr/projects/corsola/include/baseboard_usbc_config.h index 865ca8b0d4..d0b3954242 100644 --- a/zephyr/projects/corsola/include/baseboard_usbc_config.h +++ b/zephyr/projects/corsola/include/baseboard_usbc_config.h @@ -8,6 +8,12 @@ #ifndef __CROS_EC_BASEBOARD_USBC_CONFIG_H #define __CROS_EC_BASEBOARD_USBC_CONFIG_H +#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S +#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1 +#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2 +#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 +#endif + void ppc_interrupt(enum gpio_signal signal); /* USB-A ports */ diff --git a/zephyr/projects/corsola/include/gpio_map.h b/zephyr/projects/corsola/include/gpio_map.h index 1bed290896..4ebfbe31b6 100644 --- a/zephyr/projects/corsola/include/gpio_map.h +++ b/zephyr/projects/corsola/include/gpio_map.h @@ -11,10 +11,4 @@ #define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_RT1718S -#define GPIO_EN_USB_C1_SINK RT1718S_GPIO1 -#define GPIO_EN_USB_C1_SOURCE RT1718S_GPIO2 -#define GPIO_EN_USB_C1_FRS RT1718S_GPIO3 -#endif - #endif /* __ZEPHYR_GPIO_MAP_H */ -- cgit v1.2.1 From fa3766d2e4a13c228caf88c122eb6dfc30bd1818 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 28 Jun 2022 13:54:35 -0700 Subject: prism: rgbkbd: Add rgb keyboard type field rgbkbd_type describes number of zones and LEDs supported. BRANCH=none BUG=b:232134905 TEST=make -j buildall Cq-Depend: chromium:3732802 Signed-off-by: Parth Malkan Change-Id: Idf4b9081e6510dcdbd4301d9d855aba2fe7e7499 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3732805 Reviewed-by: Daisuke Nojiri --- board/prism/board.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/prism/board.c b/board/prism/board.c index 752b614fc2..5a50a8c950 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -102,8 +102,11 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; +const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_PER_KEY; + #define LED(x, y) RGBKBD_COORD((x), (y)) #define DELM RGBKBD_DELM + const uint8_t rgbkbd_map[] = { DELM, /* 0: (null) */ LED(0, 1), DELM, /* 1: ~ ` */ -- cgit v1.2.1 From 785da78da7dfb37f9bdfb57f22a696a656a0b931 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Wed, 29 Jun 2022 14:39:49 -0700 Subject: ectool: rgbkbd: Add getconfig support Usage: ectool rgbkbd getconfig Returns RGB KB type - Number of LEDs and zones BUG=b:237592750 BRANCH=none TEST=Tested on Taniks and Vell Cq-Depend: chromium:3732802 Change-Id: Ia58c648865e8bca2f073770b54a3b0f529f35abf Signed-off-by: Parth Malkan Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735915 Reviewed-by: Zhuohao Lee --- util/ectool.c | 80 +++++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 53 insertions(+), 27 deletions(-) diff --git a/util/ectool.c b/util/ectool.c index d80a3404cf..24fc49763f 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -1288,22 +1288,25 @@ int cmd_reboot_ap_on_g3(int argc, char *argv[]) static void cmd_rgbkbd_help(char *cmd) { fprintf(stderr, - " Usage1: %s [ ...]\n" - " Set the color of to . Multiple colors for\n" - " adjacent keys can be set at once.\n" - "\n" - " Usage2: %s clear \n" - " Set the color of all keys to .\n" - "\n" - " Usage3: %s demo \n" - " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" - "\n" - " Usage4: %s scale \n" - " Set the scale parameter of key_ to .\n" - " is a 24-bit integer where scale values are encoded\n" - " as R=23:16, G=15:8, B=7:0.\n" - "\n", - cmd, cmd, cmd, cmd); + " Usage1: %s [ ...]\n" + " Set the color of to . Multiple colors for\n" + " adjacent keys can be set at once.\n" + "\n" + " Usage2: %s clear \n" + " Set the color of all keys to .\n" + "\n" + " Usage3: %s demo \n" + " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" + "\n" + " Usage4: %s scale \n" + " Set the scale parameter of key_ to .\n" + " is a 24-bit integer where scale values are encoded\n" + " as R=23:16, G=15:8, B=7:0.\n" + "\n" + " Usage5: %s getconfig\n" + " Get the HW config supported.\n" + "\n", + cmd, cmd, cmd, cmd, cmd); } static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color) @@ -1368,26 +1371,23 @@ static int cmd_rgbkbd(int argc, char *argv[]) int val; char *e; int rv = -1; - ; + struct ec_params_rgbkbd p; + struct ec_response_rgbkbd r; - if (argc < 3) { + if (argc < 2) { cmd_rgbkbd_help(argv[0]); return -1; } if (argc == 3 && !strcasecmp(argv[1], "clear")) { /* Usage 2 */ - struct ec_params_rgbkbd p; - p.subcmd = EC_RGBKBD_SUBCMD_CLEAR; if (cmd_rgbkbd_parse_rgb_text(argv[2], &p.color)) return -1; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); } else if (argc == 3 && !strcasecmp(argv[1], "demo")) { /* Usage 3 */ - struct ec_params_rgbkbd p; - val = strtol(argv[2], &e, 0); if ((e && *e) || val >= EC_RGBKBD_DEMO_COUNT) { fprintf(stderr, "Invalid demo id: %s\n", argv[2]); @@ -1395,11 +1395,9 @@ static int cmd_rgbkbd(int argc, char *argv[]) } p.subcmd = EC_RGBKBD_SUBCMD_DEMO; p.demo = val; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); } else if (argc == 4 && !strcasecmp(argv[1], "scale")) { /* Usage 4 */ - struct ec_params_rgbkbd p; - val = strtol(argv[2], &e, 0); if ((e && *e) || val > EC_RGBKBD_MAX_KEY_COUNT) { fprintf(stderr, "Invalid key number: %s\n", argv[2]); @@ -1411,7 +1409,35 @@ static int cmd_rgbkbd(int argc, char *argv[]) return -1; } p.subcmd = EC_RGBKBD_SUBCMD_SET_SCALE; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), NULL, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); + } else if (argc == 2 && !strcasecmp(argv[1], "getconfig")) { + /* Usage 5 */ + char *type; + + p.subcmd = EC_RGBKBD_SUBCMD_GET_CONFIG; + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r)); + + if (rv < 0) + return rv; + + switch ((enum ec_rgbkbd_type)r.rgbkbd_type) { + case EC_RGBKBD_TYPE_PER_KEY: + type = "EC_RGBKBD_TYPE_PER_KEY"; + break; + case EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS: + type = "EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS"; + break; + case EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS: + type = "EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS"; + break; + case EC_RGBKBD_TYPE_FOUR_ZONES_15_LEDS: + type = "EC_RGBKBD_TYPE_FOUR_ZONES_15_LEDS"; + break; + default: + type = "EC_RGBKBD_TYPE_UNKNOWN"; + } + + printf("RGBKBD_TYPE: %s\n", type); } else { /* Usage 1 */ rv = cmd_rgbkbd_set_color(argc, argv); -- cgit v1.2.1 From 8032d5761771d4f4d1f4b843263efc7aed1b59d0 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 28 Jun 2022 13:58:29 -0700 Subject: mithrax: rgbkbd: Add rgb keyboard type field rgbkbd_type describes number of zones and LEDs supported. BRANCH=none BUG=b:232134905 TEST=make -j buildall Cq-Depend: chromium:3732802 Signed-off-by: Parth Malkan Change-Id: I4274ad574b9725f783c8bb301db7f603df7ab254 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3732806 Reviewed-by: Daisuke Nojiri --- board/mithrax/keyboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/mithrax/keyboard.c b/board/mithrax/keyboard.c index 6d6fd3a4a6..02d16f2adc 100644 --- a/board/mithrax/keyboard.c +++ b/board/mithrax/keyboard.c @@ -61,8 +61,11 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; +const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS; + #define LED(x, y) RGBKBD_COORD((x), (y)) #define DELM RGBKBD_DELM + const uint8_t rgbkbd_map[] = { DELM, /* 0: (null) */ LED(0, 0), DELM, /* 1: ~ ` */ -- cgit v1.2.1 From 7c733a4c9ebef218365c2c084259f94dea7aaedc Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 28 Jun 2022 14:01:08 -0700 Subject: taniks: rgbkbd: Add rgb keyboard type field rgbkbd_type describes number of zones and LEDs supported. BRANCH=none BUG=b:232134905 TEST=make -j buildall Cq-Depend: chromium:3732802 Signed-off-by: Parth Malkan Change-Id: I3fa2ebede9aa077661199072480d28a65e5d1206 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733669 Reviewed-by: Daisuke Nojiri --- board/taniks/keyboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/taniks/keyboard.c b/board/taniks/keyboard.c index 58a5d54ad0..eebb330501 100644 --- a/board/taniks/keyboard.c +++ b/board/taniks/keyboard.c @@ -66,8 +66,11 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; +const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS; + #define LED(x, y) RGBKBD_COORD((x), (y)) #define DELM RGBKBD_DELM + const uint8_t rgbkbd_map[] = { DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0), DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0), -- cgit v1.2.1 From 0fedae4fe40f63ceca8467a8b3603a32d2cae7ef Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 28 Jun 2022 12:53:07 -0700 Subject: rgbkbd: Add get_config subcommand to rgbkbd host command Add a response struct to rgbkbd host command and add GET_CONFIG as a subcommand. This is used to return RGB keyboard type (number of zones and LEDs) to the host. BRANCH=none BUG=b:232134905 TEST=Test on Taniks and Vell using ectool rgbkbd getconfig command Cq-Depend: chromium:3732805, chromium:3733669 Cq-Depend: chromium:3732806, chromium:3733668 Cq-Depend: chromium:3735915 Change-Id: Ie5b18ed3be141f2a91326ff2a121649296ea1161 Signed-off-by: Parth Malkan Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3732802 Reviewed-by: Zhuohao Lee --- common/rgb_keyboard.c | 8 ++++++++ include/ec_commands.h | 18 ++++++++++++++++++ include/rgb_keyboard.h | 6 ++++++ test/rgb_keyboard.c | 2 ++ 4 files changed, 34 insertions(+) diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c index 95ed7a062b..2bb5464a7d 100644 --- a/common/rgb_keyboard.c +++ b/common/rgb_keyboard.c @@ -530,8 +530,12 @@ DECLARE_HOST_COMMAND(EC_CMD_RGBKBD_SET_COLOR, hc_rgbkbd_set_color, static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) { const struct ec_params_rgbkbd *p = args->params; + struct ec_response_rgbkbd *r = args->response; enum ec_status rv = EC_RES_SUCCESS; + /* Default value is 0 */ + args->response_size = 0; + if (rgbkbd_late_init()) return EC_RES_ERROR; @@ -548,6 +552,10 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) if (rgbkbd_set_scale(p->set_scale.scale, p->set_scale.key)) rv = EC_RES_ERROR; break; + case EC_RGBKBD_SUBCMD_GET_CONFIG: + args->response_size = sizeof(*r); + r->rgbkbd_type = rgbkbd_type; + break; default: rv = EC_RES_INVALID_PARAM; break; diff --git a/include/ec_commands.h b/include/ec_commands.h index 759cdca27b..0db33f802d 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -7158,6 +7158,7 @@ enum ec_rgbkbd_subcmd { EC_RGBKBD_SUBCMD_CLEAR = 1, EC_RGBKBD_SUBCMD_DEMO = 2, EC_RGBKBD_SUBCMD_SET_SCALE = 3, + EC_RGBKBD_SUBCMD_GET_CONFIG = 4, EC_RGBKBD_SUBCMD_COUNT }; @@ -7170,6 +7171,15 @@ enum ec_rgbkbd_demo { BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); +enum ec_rgbkbd_type { + EC_RGBKBD_TYPE_UNKNOWN = 0, + EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ + EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ + EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ + EC_RGBKBD_TYPE_FOUR_ZONES_15_LEDS = 4, /* e.g. Mithrax */ + EC_RGBKBD_TYPE_COUNT, +}; + struct ec_rgbkbd_set_scale { uint8_t key; struct rgb_s scale; @@ -7184,6 +7194,14 @@ struct ec_params_rgbkbd { }; } __ec_align1; +struct ec_response_rgbkbd { + /* + * RGBKBD type supported by the device. + */ + + uint8_t rgbkbd_type; /* enum ec_rgbkbd_type */ +} __ec_align1; + struct ec_params_rgbkbd_set_color { /* Specifies the starting key ID whose color is being changed. */ uint8_t start_key; diff --git a/include/rgb_keyboard.h b/include/rgb_keyboard.h index d1454b0af0..c02b29d5f3 100644 --- a/include/rgb_keyboard.h +++ b/include/rgb_keyboard.h @@ -153,6 +153,12 @@ extern const uint8_t rgbkbd_count; extern const uint8_t rgbkbd_hsize; extern const uint8_t rgbkbd_vsize; +/* + * rgbkbd_type describes the rgb kb type supported. + * i.e. Number of zones and number of LEDs + */ +extern const enum ec_rgbkbd_type rgbkbd_type; + /* * rgbkbd_map describes a mapping from key IDs to LED IDs. * diff --git a/test/rgb_keyboard.c b/test/rgb_keyboard.c index 8419b84ab4..6a4c4066cb 100644 --- a/test/rgb_keyboard.c +++ b/test/rgb_keyboard.c @@ -51,6 +51,8 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL + RGB_GRID1_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; +const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_UNKNOWN; + const uint8_t rgbkbd_map[] = { RGBKBD_DELM, RGBKBD_COORD(1, 2), RGBKBD_DELM, RGBKBD_COORD(3, 4), RGBKBD_COORD(5, 6), RGBKBD_DELM, RGBKBD_DELM, RGBKBD_DELM, -- cgit v1.2.1 From 7be23fa82e8bad96b0e6473f25b0f39273575ce3 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 28 Jun 2022 13:59:51 -0700 Subject: osiris: rgbkbd: Add rgb keyboard type field rgbkbd_type describes number of zones and LEDs supported. BRANCH=none BUG=b:232134905 TEST=make -j buildall Cq-Depend: chromium:3732802 Signed-off-by: Parth Malkan Change-Id: I400f38f45469874f8ea9bf75f45135e3baa21764 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3733668 Reviewed-by: Daisuke Nojiri --- board/osiris/keyboard.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c index 2c8a32c24f..5aaaae8a02 100644 --- a/board/osiris/keyboard.c +++ b/board/osiris/keyboard.c @@ -80,8 +80,11 @@ const uint8_t rgbkbd_count = ARRAY_SIZE(rgbkbds); const uint8_t rgbkbd_hsize = RGB_GRID0_COL; const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS; + +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM + const uint8_t rgbkbd_map[] = { DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0), DELM, LED(4, 0), DELM, LED(5, 0), DELM, LED(6, 0), DELM, LED(7, 0), -- cgit v1.2.1 From 1404a66875bcc78b139abb59244125de9420867f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:48 -0600 Subject: board/delbin/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic044da60ba9c4f577b7318770b539542977baf51 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748800 Reviewed-by: Jeremy Bettis --- board/delbin/board.h | 1 - 1 file changed, 1 deletion(-) diff --git a/board/delbin/board.h b/board/delbin/board.h index 0fc3d84e94..efdb2d503a 100644 --- a/board/delbin/board.h +++ b/board/delbin/board.h @@ -42,7 +42,6 @@ #define CONFIG_KEYBOARD_CUSTOMIZATION #define CONFIG_KEYBOARD_MULTIPLE - /* Sensors */ /* BMA253 accelerometer in base */ #define CONFIG_ACCEL_BMA255 -- cgit v1.2.1 From fe68d394d3e3e89177e1893177710511e1a65251 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:26 -0600 Subject: chip/stm32/registers-stm32f7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib4d19cefc76531cfbb5fdd8f9c86aa820abd802e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749463 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f7.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/chip/stm32/registers-stm32f7.h b/chip/stm32/registers-stm32f7.h index d48df6f894..f43b3b6828 100644 --- a/chip/stm32/registers-stm32f7.h +++ b/chip/stm32/registers-stm32f7.h @@ -403,8 +403,9 @@ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI \ - */ +#define STM32F4_USB_REQ \ + 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 -- cgit v1.2.1 From 1c62a5b8ec8d1de3a8e1877b4a970ff3211e11dd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:18 -0600 Subject: board/madoo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I9357c9d4d0df704b71c040db47952a5489311551 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749391 Reviewed-by: Jeremy Bettis --- board/madoo/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/madoo/board.h b/board/madoo/board.h index 701f168174..db6b27950d 100644 --- a/board/madoo/board.h +++ b/board/madoo/board.h @@ -15,8 +15,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP -- cgit v1.2.1 From 6a2ed162a91ab1672ec37c5901ac61b8a5a4b14a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:01 -0600 Subject: include/config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I088bbedad436104af22e6b51c13f087f14a393c6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749517 Reviewed-by: Jeremy Bettis --- include/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/config.h b/include/config.h index 1a4460032a..bcf070f82f 100644 --- a/include/config.h +++ b/include/config.h @@ -6877,4 +6877,4 @@ #define HAS_GPU_DRIVER #endif -#endif /* __CROS_EC_CONFIG_H */ +#endif /* __CROS_EC_CONFIG_H */ -- cgit v1.2.1 From f9723aa7ca78d3c71f4c6faa9e6b1a9445eaf4b3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:39 -0600 Subject: driver/nvidia_gpu.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib1e4882f9bb4b2f8f58bc21869c9a513127bfb7e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749474 Reviewed-by: Jeremy Bettis --- driver/nvidia_gpu.h | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/driver/nvidia_gpu.h b/driver/nvidia_gpu.h index 8991ec75c1..5b2e7e1b1d 100644 --- a/driver/nvidia_gpu.h +++ b/driver/nvidia_gpu.h @@ -8,7 +8,7 @@ #ifndef DRIVER_NVIDIA_GPU_H #define DRIVER_NVIDIA_GPU_H -#define NVIDIA_GPU_ACOFF_DURATION (100 * MSEC) +#define NVIDIA_GPU_ACOFF_DURATION (100 * MSEC) enum d_notify_level { D_NOTIFY_1 = 0, @@ -40,18 +40,19 @@ struct d_notify_policy { }; }; -#define AC_ATLEAST_W(W) { \ - .power_source = D_NOTIFY_AC, \ - .ac.min_charger_watts = (W), \ +#define AC_ATLEAST_W(W) \ + { \ + .power_source = D_NOTIFY_AC, .ac.min_charger_watts = (W), \ } -#define AC_DC { \ - .power_source = D_NOTIFY_AC_DC, \ +#define AC_DC \ + { \ + .power_source = D_NOTIFY_AC_DC, \ } -#define DC_ATLEAST_SOC(S) { \ - .power_source = D_NOTIFY_DC, \ - .dc.min_battery_soc = (S), \ +#define DC_ATLEAST_SOC(S) \ + { \ + .power_source = D_NOTIFY_DC, .dc.min_battery_soc = (S), \ } void nvidia_gpu_init_policy(const struct d_notify_policy *policies); -- cgit v1.2.1 From ba1d706516cf18a409e65c04aaf56d12901a5986 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:10 -0600 Subject: board/lantis/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I124cd0cc8caacb6238c87cd6439c8c8511d498e8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749390 Reviewed-by: Jeremy Bettis --- board/lantis/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/lantis/board.h b/board/lantis/board.h index a5f610eb3d..835de04391 100644 --- a/board/lantis/board.h +++ b/board/lantis/board.h @@ -29,8 +29,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From e68a546a56c0c21c44c058200522fc74c6ed0b6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:16 -0600 Subject: board/waddledee/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I5e871c061251cf7fc633576ac76c976862f40f90 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749425 Reviewed-by: Jeremy Bettis --- board/waddledee/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/waddledee/board.h b/board/waddledee/board.h index a7975e3f95..df0ea5e463 100644 --- a/board/waddledee/board.h +++ b/board/waddledee/board.h @@ -30,8 +30,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* * GPIO for C1 interrupts, for baseboard use -- cgit v1.2.1 From c202437313bf2e17ac832381023c6111e2ba007e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:06 -0600 Subject: board/lalala/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ie03dde5520b3fb9e4ed04b29af8a1cf09c17711b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749389 Reviewed-by: Jeremy Bettis --- board/lalala/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/lalala/board.h b/board/lalala/board.h index 13abae1101..9bdbb55d82 100644 --- a/board/lalala/board.h +++ b/board/lalala/board.h @@ -24,8 +24,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP -- cgit v1.2.1 From 9afb32b79032eb2666154bdf6872a99d7db7f7d2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:36 -0600 Subject: board/crota/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Idc3f17b61cd89fe16114fce6bf90bb901b9ae96f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748798 Reviewed-by: Jeremy Bettis --- board/crota/fans.c | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/board/crota/fans.c b/board/crota/fans.c index e09519385f..ccd89f16f9 100644 --- a/board/crota/fans.c +++ b/board/crota/fans.c @@ -106,19 +106,19 @@ static void fan_set_percent(int fan, int pct, bool fan_triggered) void board_override_fan_control(int fan, int *tmp) { /* - * Crota's fan speed is control by three sensors. - * - * Sensor SOC control high loading's speed. - * Sensor ambient control low loading's speed. - * Sensor charger control the speed when system's temperature - * is too high. - * - * When sensor charger is not triggered, the fan is control - * and choose the smaller speed between SOC and ambient. - * - * When sensor charger is triggered, the fan speed is only - * control by sensor charger, avoid heat damage to system. - */ + * Crota's fan speed is control by three sensors. + * + * Sensor SOC control high loading's speed. + * Sensor ambient control low loading's speed. + * Sensor charger control the speed when system's temperature + * is too high. + * + * When sensor charger is not triggered, the fan is control + * and choose the smaller speed between SOC and ambient. + * + * When sensor charger is triggered, the fan speed is only + * control by sensor charger, avoid heat damage to system. + */ int pct; int sensor_soc; @@ -127,20 +127,19 @@ void board_override_fan_control(int fan, int *tmp) bool fan_triggered; sensor_soc = thermal_fan_percent(thermal_params[0].temp_fan_off, - thermal_params[0].temp_fan_max, - C_TO_K(tmp[0])); + thermal_params[0].temp_fan_max, + C_TO_K(tmp[0])); sensor_ambient = thermal_fan_percent(thermal_params[3].temp_fan_off, - thermal_params[3].temp_fan_max, - C_TO_K(tmp[3])); + thermal_params[3].temp_fan_max, + C_TO_K(tmp[3])); sensor_charger = thermal_fan_percent(thermal_params[2].temp_fan_off, - thermal_params[2].temp_fan_max, - C_TO_K(tmp[2])); + thermal_params[2].temp_fan_max, + C_TO_K(tmp[2])); - if (sensor_charger){ + if (sensor_charger) { fan_triggered = true; pct = sensor_charger; - } - else{ + } else { fan_triggered = false; pct = MIN(sensor_soc, sensor_ambient); } -- cgit v1.2.1 From 6186f4534ace4ba6c5becf7832199ae632eccf27 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:51 -0600 Subject: board/kracko/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic500feb954f10e70c324421bff6f273cb7f52cab Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749386 Reviewed-by: Jeremy Bettis --- board/kracko/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kracko/board.h b/board/kracko/board.h index 79205a2933..01ef092132 100644 --- a/board/kracko/board.h +++ b/board/kracko/board.h @@ -29,8 +29,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From e752844663740858153894f47d7c66e7aa966adf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:55 -0600 Subject: board/kuldax/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I8e76be36fa0ef9f24b3ecf884f528dd1f57a4d6e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749387 Reviewed-by: Jeremy Bettis --- board/kuldax/board.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kuldax/board.h b/board/kuldax/board.h index 0e0c248cf9..1bf6f5cdcb 100644 --- a/board/kuldax/board.h +++ b/board/kuldax/board.h @@ -88,7 +88,7 @@ /* I2C Bus Configuration */ #define I2C_PORT_DP_REDRIVER NPCX_I2C_PORT0_0 -#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 +#define I2C_PORT_USB_C0_C2_TCPC NPCX_I2C_PORT1_0 #define I2C_PORT_USB_C0_C2_PPC NPCX_I2C_PORT2_0 #define I2C_PORT_USB_C1_PPC NPCX_I2C_PORT6_1 -- cgit v1.2.1 From cc3e74de8d7d237ca306a2c1c24c6ada715523bd Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:17 -0600 Subject: driver/charger/isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I102e8c21424f2082474f750d615643f126dfd0de Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749471 Reviewed-by: Jeremy Bettis --- driver/charger/isl9241.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/driver/charger/isl9241.c b/driver/charger/isl9241.c index 12d5a2d55a..e666aef802 100644 --- a/driver/charger/isl9241.c +++ b/driver/charger/isl9241.c @@ -42,7 +42,7 @@ #define AC_CURRENT_TO_REG(CUR) (((CUR)*BOARD_RS1) / ISL9241_DEFAULT_RS1) /* Console output macros */ -#define CPRINTS(format, args...) cprints(CC_CHARGER, "ISL9241 " format, ## args) +#define CPRINTS(format, args...) cprints(CC_CHARGER, "ISL9241 " format, ##args) static int learn_mode; -- cgit v1.2.1 From 5ca464591d8607676d2fd17355ad88d99544ff48 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:59 -0600 Subject: board/dingdong/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I3898d9ec05d7111b275ed72eea5ab87edf6b2d76 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748803 Reviewed-by: Jeremy Bettis --- board/dingdong/usb_pd_policy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/dingdong/usb_pd_policy.c b/board/dingdong/usb_pd_policy.c index c4054b1a18..2301e8280a 100644 --- a/board/dingdong/usb_pd_policy.c +++ b/board/dingdong/usb_pd_policy.c @@ -160,9 +160,10 @@ static int dp_status(int port, uint32_t *payload) 0, /* request exit DP */ 0, /* request exit USB */ 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power - low - */ + gpio_get_level(GPIO_PD_SBU_ENABLE), + 0, /* power + low + */ 0x2); return 2; } -- cgit v1.2.1 From a62ddeac0c82d945583aa89efaa881adaa92c109 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:30 -0600 Subject: chip/it83xx/config_chip_it8xxx2.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I759eeec588d8bbbd8edec6aff61576ea753aafa0 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749429 Reviewed-by: Jeremy Bettis --- chip/it83xx/config_chip_it8xxx2.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 45a92a3d82..e754c5ff6e 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -158,8 +158,9 @@ #define CHIP_RAMCODE_ILM0 (CONFIG_RAM_BASE + 0) /* base+0000h~base+0FFF */ #define CHIP_H2RAM_BASE (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */ -#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF \ - */ +#define CHIP_RAMCODE_BASE \ + (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF \ + */ #ifdef BASEBOARD_KUKUI /* -- cgit v1.2.1 From 7fff012b3c13c4e428f0e1f10c041c24ea6c715a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:14 -0600 Subject: chip/stm32/hwtimer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I2c84c1f8477b5299b3c398722eefa7a3c8dea709 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749460 Reviewed-by: Jeremy Bettis --- chip/stm32/hwtimer.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index 46c47f3c1e..652e822f09 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -419,11 +419,12 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) = { IRQ_WD, - 0 }; /* put the watchdog - at the highest - priority - */ + __attribute__((section(".rodata.irqprio"))) = { + IRQ_WD, 0 + }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { -- cgit v1.2.1 From 51c9837902b548b69640b8341114dfac645fe031 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:51 -0600 Subject: common/charge_state_v2.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I25e137f48e8e285dda78f104ad09f7b4806a8f7f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749465 Reviewed-by: Jeremy Bettis --- common/charge_state_v2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index ba46a4f194..957ecd3455 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -992,8 +992,8 @@ static int charge_request(int voltage, int current) * from nvdc + chrg will be done separately. */ should_bypass = board_should_charger_bypass(); - if ((should_bypass && !(curr.chg.status & CHARGER_BYPASS_MODE)) - || (!should_bypass && (curr.chg.status & CHARGER_BYPASS_MODE))) + if ((should_bypass && !(curr.chg.status & CHARGER_BYPASS_MODE)) || + (!should_bypass && (curr.chg.status & CHARGER_BYPASS_MODE))) charger_enable_bypass_mode(0, should_bypass); /* -- cgit v1.2.1 From a009125e53d12bf172bb43b163ce021d7abd86f7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:05 -0600 Subject: board/servo_v4p1/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iea73986ee0775438f4dd2f64fdfed2eb09a95850 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749422 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_pd_policy.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/board/servo_v4p1/usb_pd_policy.c b/board/servo_v4p1/usb_pd_policy.c index 9dd4d113a7..81ed23356f 100644 --- a/board/servo_v4p1/usb_pd_policy.c +++ b/board/servo_v4p1/usb_pd_policy.c @@ -1004,15 +1004,16 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS) return 0; /* NAK */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - hpd, /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF - pref - */ - dp_enabled, 0, /* power low */ - hpd ? 0x2 : 0); + payload[1] = + VDO_DP_STATUS(0, /* IRQ_HPD */ + hpd, /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF + pref + */ + dp_enabled, 0, /* power low */ + hpd ? 0x2 : 0); return 2; } -- cgit v1.2.1 From b423957615a79f3d745b2670f468cf64d61f2421 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:29 -0600 Subject: util/comm-host.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ied9a7419d93dfbc71d3f3a9302280de92d0890b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749523 Reviewed-by: Jeremy Bettis --- util/comm-host.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/util/comm-host.h b/util/comm-host.h index 17dd28d077..85661ec981 100644 --- a/util/comm-host.h +++ b/util/comm-host.h @@ -63,10 +63,11 @@ int comm_init_buffer(void); * Send a command to the EC. Returns the length of output data returned (0 if * none), or negative on error. */ -int ec_command(int command, int version, const void *outdata, int outsize, /* to - the - EC - */ +int ec_command(int command, int version, const void *outdata, + int outsize, /* to + the + EC + */ void *indata, int insize); /* from the EC */ /** -- cgit v1.2.1 From b8485072b8c8b06a58c73b4173d844f425b7ce2f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:38 -0600 Subject: chip/max32660/gcr_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I8c6682ee73a7e6b69ccd568d43f8decebe8a264d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749431 Reviewed-by: Jeremy Bettis --- chip/max32660/gcr_regs.h | 1341 +++++++++++++++++++++++++--------------------- 1 file changed, 735 insertions(+), 606 deletions(-) diff --git a/chip/max32660/gcr_regs.h b/chip/max32660/gcr_regs.h index 560029961d..84fd694bdf 100644 --- a/chip/max32660/gcr_regs.h +++ b/chip/max32660/gcr_regs.h @@ -126,18 +126,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SCON_SBUSARB_FIX \ ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ -#define MXC_S_GCR_SCON_SBUSARB_FIX \ - (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ - SCON_SBUSARB_FIX \ - Setting \ - */ +#define MXC_S_GCR_SCON_SBUSARB_FIX \ + (MXC_V_GCR_SCON_SBUSARB_FIX \ + << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ + SCON_SBUSARB_FIX \ + Setting \ + */ #define MXC_V_GCR_SCON_SBUSARB_ROUND \ ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ -#define MXC_S_GCR_SCON_SBUSARB_ROUND \ - (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ - SCON_SBUSARB_ROUND \ - Setting \ - */ +#define MXC_S_GCR_SCON_SBUSARB_ROUND \ + (MXC_V_GCR_SCON_SBUSARB_ROUND \ + << MXC_F_GCR_SCON_SBUSARB_POS) /**< \ + SCON_SBUSARB_ROUND \ + Setting \ + */ #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS \ 4 /**< SCON_FLASH_PAGE_FLIP Position */ @@ -167,18 +169,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SCON_FPU_DIS_ENABLE \ ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_ENABLE \ - (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ - SCON_FPU_DIS_ENABLE \ - Setting \ - */ +#define MXC_S_GCR_SCON_FPU_DIS_ENABLE \ + (MXC_V_GCR_SCON_FPU_DIS_ENABLE \ + << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ + SCON_FPU_DIS_ENABLE \ + Setting \ + */ #define MXC_V_GCR_SCON_FPU_DIS_DISABLE \ ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_FPU_DIS_DISABLE \ - (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ - SCON_FPU_DIS_DISABLE \ - Setting \ - */ +#define MXC_S_GCR_SCON_FPU_DIS_DISABLE \ + (MXC_V_GCR_SCON_FPU_DIS_DISABLE \ + << MXC_F_GCR_SCON_FPU_DIS_POS) /**< \ + SCON_FPU_DIS_DISABLE \ + Setting \ + */ #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ #define MXC_F_GCR_SCON_CCACHE_FLUSH \ @@ -205,18 +209,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SCON_SWD_DIS_ENABLE \ ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_ENABLE \ - (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ - SCON_SWD_DIS_ENABLE \ - Setting \ - */ +#define MXC_S_GCR_SCON_SWD_DIS_ENABLE \ + (MXC_V_GCR_SCON_SWD_DIS_ENABLE \ + << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ + SCON_SWD_DIS_ENABLE \ + Setting \ + */ #define MXC_V_GCR_SCON_SWD_DIS_DISABLE \ ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */ -#define MXC_S_GCR_SCON_SWD_DIS_DISABLE \ - (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ - SCON_SWD_DIS_DISABLE \ - Setting \ - */ +#define MXC_S_GCR_SCON_SWD_DIS_DISABLE \ + (MXC_V_GCR_SCON_SWD_DIS_DISABLE \ + << MXC_F_GCR_SCON_SWD_DIS_POS) /**< \ + SCON_SWD_DIS_DISABLE \ + Setting \ + */ /** * Reset Register 0. @@ -231,24 +237,27 @@ typedef struct { Setting */ #define MXC_V_GCR_RSTR0_DMA_RESET \ ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET \ - (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< \ - RSTR0_DMA_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_DMA_RESET \ + (MXC_V_GCR_RSTR0_DMA_RESET \ + << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_DMA_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ - (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< \ - RSTR0_DMA_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_DMA_RESET_DONE \ + (MXC_V_GCR_RSTR0_DMA_RESET_DONE \ + << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_DMA_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_DMA_BUSY \ - (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< \ - RSTR0_DMA_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_DMA_BUSY \ + (MXC_V_GCR_RSTR0_DMA_BUSY \ + << MXC_F_GCR_RSTR0_DMA_POS) /**< \ + RSTR0_DMA_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ #define MXC_F_GCR_RSTR0_WDT \ @@ -260,24 +269,27 @@ typedef struct { Setting */ #define MXC_V_GCR_RSTR0_WDT_RESET \ ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET \ - (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< \ - RSTR0_WDT_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_WDT_RESET \ + (MXC_V_GCR_RSTR0_WDT_RESET \ + << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_WDT_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_WDT_RESET_DONE \ - (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< \ - RSTR0_WDT_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_WDT_RESET_DONE \ + (MXC_V_GCR_RSTR0_WDT_RESET_DONE \ + << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_WDT_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_WDT_BUSY \ - (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< \ - RSTR0_WDT_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_WDT_BUSY \ + (MXC_V_GCR_RSTR0_WDT_BUSY \ + << MXC_F_GCR_RSTR0_WDT_POS) /**< \ + RSTR0_WDT_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ #define MXC_F_GCR_RSTR0_GPIO0 \ @@ -285,31 +297,35 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_GPIO0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RFU \ - (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ - RSTR0_GPIO0_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_GPIO0_RFU \ + (MXC_V_GCR_RSTR0_GPIO0_RFU \ + << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_GPIO0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET \ - (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ - RSTR0_GPIO0_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_GPIO0_RESET \ + (MXC_V_GCR_RSTR0_GPIO0_RESET \ + << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE \ - (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ - RSTR0_GPIO0_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE \ + (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE \ + << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_GPIO0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */ -#define MXC_S_GCR_RSTR0_GPIO0_BUSY \ - (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ - RSTR0_GPIO0_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_GPIO0_BUSY \ + (MXC_V_GCR_RSTR0_GPIO0_BUSY \ + << MXC_F_GCR_RSTR0_GPIO0_POS) /**< \ + RSTR0_GPIO0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ #define MXC_F_GCR_RSTR0_TIMER0 \ @@ -317,18 +333,20 @@ typedef struct { Mask */ #define MXC_V_GCR_RSTR0_TIMER0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RFU \ - (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ - RSTR0_TIMER0_RFU \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER0_RFU \ + (MXC_V_GCR_RSTR0_TIMER0_RFU \ + << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_RFU \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER0_RESET \ - (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ - RSTR0_TIMER0_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER0_RESET \ + (MXC_V_GCR_RSTR0_TIMER0_RESET \ + << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */ #define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE \ @@ -337,11 +355,12 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_TIMER0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER0_BUSY \ - (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ - RSTR0_TIMER0_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER0_BUSY \ + (MXC_V_GCR_RSTR0_TIMER0_BUSY \ + << MXC_F_GCR_RSTR0_TIMER0_POS) /**< \ + RSTR0_TIMER0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ #define MXC_F_GCR_RSTR0_TIMER1 \ @@ -349,18 +368,20 @@ typedef struct { Mask */ #define MXC_V_GCR_RSTR0_TIMER1_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RFU \ - (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ - RSTR0_TIMER1_RFU \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER1_RFU \ + (MXC_V_GCR_RSTR0_TIMER1_RFU \ + << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_RFU \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER1_RESET \ - (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ - RSTR0_TIMER1_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER1_RESET \ + (MXC_V_GCR_RSTR0_TIMER1_RESET \ + << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */ #define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE \ @@ -369,11 +390,12 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_TIMER1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER1_BUSY \ - (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ - RSTR0_TIMER1_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER1_BUSY \ + (MXC_V_GCR_RSTR0_TIMER1_BUSY \ + << MXC_F_GCR_RSTR0_TIMER1_POS) /**< \ + RSTR0_TIMER1_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ #define MXC_F_GCR_RSTR0_TIMER2 \ @@ -381,18 +403,20 @@ typedef struct { Mask */ #define MXC_V_GCR_RSTR0_TIMER2_RFU \ ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RFU \ - (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ - RSTR0_TIMER2_RFU \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER2_RFU \ + (MXC_V_GCR_RSTR0_TIMER2_RFU \ + << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_RFU \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER2_RESET \ ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */ -#define MXC_S_GCR_RSTR0_TIMER2_RESET \ - (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ - RSTR0_TIMER2_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER2_RESET \ + (MXC_V_GCR_RSTR0_TIMER2_RESET \ + << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */ #define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE \ @@ -401,11 +425,12 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_TIMER2_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */ -#define MXC_S_GCR_RSTR0_TIMER2_BUSY \ - (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ - RSTR0_TIMER2_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_TIMER2_BUSY \ + (MXC_V_GCR_RSTR0_TIMER2_BUSY \ + << MXC_F_GCR_RSTR0_TIMER2_POS) /**< \ + RSTR0_TIMER2_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ #define MXC_F_GCR_RSTR0_UART0 \ @@ -413,31 +438,35 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_UART0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */ -#define MXC_S_GCR_RSTR0_UART0_RFU \ - (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< \ - RSTR0_UART0_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_UART0_RFU \ + (MXC_V_GCR_RSTR0_UART0_RFU \ + << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_UART0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET \ - (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< \ - RSTR0_UART0_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART0_RESET \ + (MXC_V_GCR_RSTR0_UART0_RESET \ + << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_UART0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART0_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< \ - RSTR0_UART0_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART0_RESET_DONE \ + (MXC_V_GCR_RSTR0_UART0_RESET_DONE \ + << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_UART0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART0_BUSY \ - (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< \ - RSTR0_UART0_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART0_BUSY \ + (MXC_V_GCR_RSTR0_UART0_BUSY \ + << MXC_F_GCR_RSTR0_UART0_POS) /**< \ + RSTR0_UART0_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ #define MXC_F_GCR_RSTR0_UART1 \ @@ -445,31 +474,35 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_UART1_RFU \ ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */ -#define MXC_S_GCR_RSTR0_UART1_RFU \ - (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< \ - RSTR0_UART1_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_UART1_RFU \ + (MXC_V_GCR_RSTR0_UART1_RFU \ + << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_UART1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET \ - (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< \ - RSTR0_UART1_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART1_RESET \ + (MXC_V_GCR_RSTR0_UART1_RESET \ + << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_UART1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_UART1_RESET_DONE \ - (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< \ - RSTR0_UART1_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART1_RESET_DONE \ + (MXC_V_GCR_RSTR0_UART1_RESET_DONE \ + << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_UART1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */ -#define MXC_S_GCR_RSTR0_UART1_BUSY \ - (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< \ - RSTR0_UART1_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_UART1_BUSY \ + (MXC_V_GCR_RSTR0_UART1_BUSY \ + << MXC_F_GCR_RSTR0_UART1_POS) /**< \ + RSTR0_UART1_BUSY \ + Setting \ + */ #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ #define MXC_F_GCR_RSTR0_SPI0 \ @@ -478,29 +511,33 @@ typedef struct { #define MXC_V_GCR_RSTR0_SPI0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SPI0_RFU \ - (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ - RSTR0_SPI0_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI0_RFU \ + (MXC_V_GCR_RSTR0_SPI0_RFU \ + << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_SPI0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET \ - (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ - RSTR0_SPI0_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI0_RESET \ + (MXC_V_GCR_RSTR0_SPI0_RESET \ + << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ - RSTR0_SPI0_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE \ + (MXC_V_GCR_RSTR0_SPI0_RESET_DONE \ + << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_SPI0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI0_BUSY \ - (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ - RSTR0_SPI0_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI0_BUSY \ + (MXC_V_GCR_RSTR0_SPI0_BUSY \ + << MXC_F_GCR_RSTR0_SPI0_POS) /**< \ + RSTR0_SPI0_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ #define MXC_F_GCR_RSTR0_SPI1 \ @@ -509,29 +546,33 @@ typedef struct { #define MXC_V_GCR_RSTR0_SPI1_RFU \ ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SPI1_RFU \ - (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ - RSTR0_SPI1_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI1_RFU \ + (MXC_V_GCR_RSTR0_SPI1_RFU \ + << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_SPI1_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET \ - (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ - RSTR0_SPI1_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI1_RESET \ + (MXC_V_GCR_RSTR0_SPI1_RESET \ + << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE \ - (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ - RSTR0_SPI1_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE \ + (MXC_V_GCR_RSTR0_SPI1_RESET_DONE \ + << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_SPI1_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */ -#define MXC_S_GCR_RSTR0_SPI1_BUSY \ - (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ - RSTR0_SPI1_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_SPI1_BUSY \ + (MXC_V_GCR_RSTR0_SPI1_BUSY \ + << MXC_F_GCR_RSTR0_SPI1_POS) /**< \ + RSTR0_SPI1_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ #define MXC_F_GCR_RSTR0_I2C0 \ @@ -540,29 +581,33 @@ typedef struct { #define MXC_V_GCR_RSTR0_I2C0_RFU \ ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value \ */ -#define MXC_S_GCR_RSTR0_I2C0_RFU \ - (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ - RSTR0_I2C0_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_I2C0_RFU \ + (MXC_V_GCR_RSTR0_I2C0_RFU \ + << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_I2C0_RESET \ ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET \ - (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ - RSTR0_I2C0_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_I2C0_RESET \ + (MXC_V_GCR_RSTR0_I2C0_RESET \ + << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE \ - (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ - RSTR0_I2C0_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE \ + (MXC_V_GCR_RSTR0_I2C0_RESET_DONE \ + << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_I2C0_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */ -#define MXC_S_GCR_RSTR0_I2C0_BUSY \ - (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ - RSTR0_I2C0_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_I2C0_BUSY \ + (MXC_V_GCR_RSTR0_I2C0_BUSY \ + << MXC_F_GCR_RSTR0_I2C0_POS) /**< \ + RSTR0_I2C0_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ #define MXC_F_GCR_RSTR0_RTC \ @@ -574,24 +619,27 @@ typedef struct { Setting */ #define MXC_V_GCR_RSTR0_RTC_RESET \ ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET \ - (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< \ - RSTR0_RTC_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_RTC_RESET \ + (MXC_V_GCR_RSTR0_RTC_RESET \ + << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_RTC_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_RTC_RESET_DONE \ - (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< \ - RSTR0_RTC_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_RTC_RESET_DONE \ + (MXC_V_GCR_RSTR0_RTC_RESET_DONE \ + << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_RTC_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value \ */ -#define MXC_S_GCR_RSTR0_RTC_BUSY \ - (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< \ - RSTR0_RTC_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_RTC_BUSY \ + (MXC_V_GCR_RSTR0_RTC_BUSY \ + << MXC_F_GCR_RSTR0_RTC_POS) /**< \ + RSTR0_RTC_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ #define MXC_F_GCR_RSTR0_SRST \ @@ -600,29 +648,33 @@ typedef struct { #define MXC_V_GCR_RSTR0_SRST_RFU \ ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value \ */ -#define MXC_S_GCR_RSTR0_SRST_RFU \ - (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< \ - RSTR0_SRST_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_SRST_RFU \ + (MXC_V_GCR_RSTR0_SRST_RFU \ + << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_SRST_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET \ - (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< \ - RSTR0_SRST_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_SRST_RESET \ + (MXC_V_GCR_RSTR0_SRST_RESET \ + << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_SRST_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_SRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< \ - RSTR0_SRST_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SRST_RESET_DONE \ + (MXC_V_GCR_RSTR0_SRST_RESET_DONE \ + << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_SRST_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_SRST_BUSY \ - (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< \ - RSTR0_SRST_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_SRST_BUSY \ + (MXC_V_GCR_RSTR0_SRST_BUSY \ + << MXC_F_GCR_RSTR0_SRST_POS) /**< \ + RSTR0_SRST_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ #define MXC_F_GCR_RSTR0_PRST \ @@ -631,29 +683,33 @@ typedef struct { #define MXC_V_GCR_RSTR0_PRST_RFU \ ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value \ */ -#define MXC_S_GCR_RSTR0_PRST_RFU \ - (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< \ - RSTR0_PRST_RFU \ - Setting */ +#define MXC_S_GCR_RSTR0_PRST_RFU \ + (MXC_V_GCR_RSTR0_PRST_RFU \ + << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RFU \ + Setting */ #define MXC_V_GCR_RSTR0_PRST_RESET \ ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET \ - (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< \ - RSTR0_PRST_RESET \ - Setting */ +#define MXC_S_GCR_RSTR0_PRST_RESET \ + (MXC_V_GCR_RSTR0_PRST_RESET \ + << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RESET \ + Setting */ #define MXC_V_GCR_RSTR0_PRST_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */ -#define MXC_S_GCR_RSTR0_PRST_RESET_DONE \ - (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< \ - RSTR0_PRST_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_PRST_RESET_DONE \ + (MXC_V_GCR_RSTR0_PRST_RESET_DONE \ + << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR0_PRST_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */ -#define MXC_S_GCR_RSTR0_PRST_BUSY \ - (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< \ - RSTR0_PRST_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR0_PRST_BUSY \ + (MXC_V_GCR_RSTR0_PRST_BUSY \ + << MXC_F_GCR_RSTR0_PRST_POS) /**< \ + RSTR0_PRST_BUSY \ + Setting */ #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ #define MXC_F_GCR_RSTR0_SYSTEM \ @@ -661,18 +717,20 @@ typedef struct { Mask */ #define MXC_V_GCR_RSTR0_SYSTEM_RFU \ ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RFU \ - (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ - RSTR0_SYSTEM_RFU \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SYSTEM_RFU \ + (MXC_V_GCR_RSTR0_SYSTEM_RFU \ + << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_RFU \ + Setting \ + */ #define MXC_V_GCR_RSTR0_SYSTEM_RESET \ ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_RESET \ - (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ - RSTR0_SYSTEM_RESET \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SYSTEM_RESET \ + (MXC_V_GCR_RSTR0_SYSTEM_RESET \ + << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_RESET \ + Setting \ + */ #define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */ #define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE \ @@ -681,11 +739,12 @@ typedef struct { */ #define MXC_V_GCR_RSTR0_SYSTEM_BUSY \ ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */ -#define MXC_S_GCR_RSTR0_SYSTEM_BUSY \ - (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ - RSTR0_SYSTEM_BUSY \ - Setting \ - */ +#define MXC_S_GCR_RSTR0_SYSTEM_BUSY \ + (MXC_V_GCR_RSTR0_SYSTEM_BUSY \ + << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< \ + RSTR0_SYSTEM_BUSY \ + Setting \ + */ /** * Clock Control. @@ -696,55 +755,63 @@ typedef struct { #define MXC_V_GCR_CLKCN_PSC_DIV1 \ ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV1 \ - (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV1 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV1 \ + (MXC_V_GCR_CLKCN_PSC_DIV1 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV1 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV2 \ ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV2 \ - (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV2 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV2 \ + (MXC_V_GCR_CLKCN_PSC_DIV2 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV2 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV4 \ ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV4 \ - (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV4 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV4 \ + (MXC_V_GCR_CLKCN_PSC_DIV4 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV4 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV8 \ ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value \ */ -#define MXC_S_GCR_CLKCN_PSC_DIV8 \ - (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV8 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV8 \ + (MXC_V_GCR_CLKCN_PSC_DIV8 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV8 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV16 \ ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV16 \ - (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV16 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV16 \ + (MXC_V_GCR_CLKCN_PSC_DIV16 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV16 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV32 \ ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV32 \ - (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV32 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV32 \ + (MXC_V_GCR_CLKCN_PSC_DIV32 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV32 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV64 \ ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV64 \ - (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV64 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV64 \ + (MXC_V_GCR_CLKCN_PSC_DIV64 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV64 \ + Setting */ #define MXC_V_GCR_CLKCN_PSC_DIV128 \ ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ -#define MXC_S_GCR_CLKCN_PSC_DIV128 \ - (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< \ - CLKCN_PSC_DIV128 \ - Setting */ +#define MXC_S_GCR_CLKCN_PSC_DIV128 \ + (MXC_V_GCR_CLKCN_PSC_DIV128 \ + << MXC_F_GCR_CLKCN_PSC_POS) /**< \ + CLKCN_PSC_DIV128 \ + Setting */ #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ #define MXC_F_GCR_CLKCN_CLKSEL \ @@ -752,25 +819,28 @@ typedef struct { Mask */ #define MXC_V_GCR_CLKCN_CLKSEL_HIRC \ ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ - (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ - CLKCN_CLKSEL_HIRC \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_CLKSEL_HIRC \ + (MXC_V_GCR_CLKCN_CLKSEL_HIRC \ + << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_HIRC \ + Setting \ + */ #define MXC_V_GCR_CLKCN_CLKSEL_NANORING \ ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_NANORING \ - (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ - CLKCN_CLKSEL_NANORING \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_CLKSEL_NANORING \ + (MXC_V_GCR_CLKCN_CLKSEL_NANORING \ + << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_NANORING \ + Setting \ + */ #define MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */ -#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN \ - (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ - CLKCN_CLKSEL_HFXIN \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN \ + (MXC_V_GCR_CLKCN_CLKSEL_HFXIN \ + << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< \ + CLKCN_CLKSEL_HFXIN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ #define MXC_F_GCR_CLKCN_CKRDY \ @@ -778,18 +848,20 @@ typedef struct { */ #define MXC_V_GCR_CLKCN_CKRDY_BUSY \ ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ - (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ - CLKCN_CKRDY_BUSY \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_CKRDY_BUSY \ + (MXC_V_GCR_CLKCN_CKRDY_BUSY \ + << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ + CLKCN_CKRDY_BUSY \ + Setting \ + */ #define MXC_V_GCR_CLKCN_CKRDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ -#define MXC_S_GCR_CLKCN_CKRDY_READY \ - (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ - CLKCN_CKRDY_READY \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_CKRDY_READY \ + (MXC_V_GCR_CLKCN_CKRDY_READY \ + << MXC_F_GCR_CLKCN_CKRDY_POS) /**< \ + CLKCN_CKRDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ #define MXC_F_GCR_CLKCN_X32K_EN \ @@ -797,18 +869,20 @@ typedef struct { Mask */ #define MXC_V_GCR_CLKCN_X32K_EN_DIS \ ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_DIS \ - (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ - CLKCN_X32K_EN_DIS \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_X32K_EN_DIS \ + (MXC_V_GCR_CLKCN_X32K_EN_DIS \ + << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ + CLKCN_X32K_EN_DIS \ + Setting \ + */ #define MXC_V_GCR_CLKCN_X32K_EN_EN \ ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */ -#define MXC_S_GCR_CLKCN_X32K_EN_EN \ - (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ - CLKCN_X32K_EN_EN \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_X32K_EN_EN \ + (MXC_V_GCR_CLKCN_X32K_EN_EN \ + << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< \ + CLKCN_X32K_EN_EN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ #define MXC_F_GCR_CLKCN_HIRC_EN \ @@ -816,18 +890,20 @@ typedef struct { Mask */ #define MXC_V_GCR_CLKCN_HIRC_EN_DIS \ ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ - (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ - CLKCN_HIRC_EN_DIS \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_HIRC_EN_DIS \ + (MXC_V_GCR_CLKCN_HIRC_EN_DIS \ + << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ + CLKCN_HIRC_EN_DIS \ + Setting \ + */ #define MXC_V_GCR_CLKCN_HIRC_EN_EN \ ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ -#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ - (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ - CLKCN_HIRC_EN_EN \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_HIRC_EN_EN \ + (MXC_V_GCR_CLKCN_HIRC_EN_EN \ + << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< \ + CLKCN_HIRC_EN_EN \ + Setting \ + */ #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ #define MXC_F_GCR_CLKCN_X32K_RDY \ @@ -836,18 +912,20 @@ typedef struct { Mask */ #define MXC_V_GCR_CLKCN_X32K_RDY_NOT \ ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_NOT \ - (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ - CLKCN_X32K_RDY_NOT \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_X32K_RDY_NOT \ + (MXC_V_GCR_CLKCN_X32K_RDY_NOT \ + << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ + CLKCN_X32K_RDY_NOT \ + Setting \ + */ #define MXC_V_GCR_CLKCN_X32K_RDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_X32K_RDY_READY \ - (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ - CLKCN_X32K_RDY_READY \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_X32K_RDY_READY \ + (MXC_V_GCR_CLKCN_X32K_RDY_READY \ + << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< \ + CLKCN_X32K_RDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ #define MXC_F_GCR_CLKCN_HIRC_RDY \ @@ -856,18 +934,20 @@ typedef struct { Mask */ #define MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ - (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ - CLKCN_HIRC_RDY_NOT \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT \ + (MXC_V_GCR_CLKCN_HIRC_RDY_NOT \ + << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ + CLKCN_HIRC_RDY_NOT \ + Setting \ + */ #define MXC_V_GCR_CLKCN_HIRC_RDY_READY \ ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ -#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ - (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ - CLKCN_HIRC_RDY_READY \ - Setting \ - */ +#define MXC_S_GCR_CLKCN_HIRC_RDY_READY \ + (MXC_V_GCR_CLKCN_HIRC_RDY_READY \ + << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< \ + CLKCN_HIRC_RDY_READY \ + Setting \ + */ #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ #define MXC_F_GCR_CLKCN_LIRC8K_RDY \ @@ -902,10 +982,11 @@ typedef struct { Setting */ #define MXC_V_GCR_PM_MODE_SHUTDOWN \ ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ -#define MXC_S_GCR_PM_MODE_SHUTDOWN \ - (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< \ - PM_MODE_SHUTDOWN \ - Setting */ +#define MXC_S_GCR_PM_MODE_SHUTDOWN \ + (MXC_V_GCR_PM_MODE_SHUTDOWN \ + << MXC_F_GCR_PM_MODE_POS) /**< \ + PM_MODE_SHUTDOWN \ + Setting */ #define MXC_V_GCR_PM_MODE_BACKUP \ ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value \ */ @@ -920,17 +1001,19 @@ typedef struct { */ #define MXC_V_GCR_PM_GPIOWKEN_DIS \ ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ -#define MXC_S_GCR_PM_GPIOWKEN_DIS \ - (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ - PM_GPIOWKEN_DIS \ - Setting */ +#define MXC_S_GCR_PM_GPIOWKEN_DIS \ + (MXC_V_GCR_PM_GPIOWKEN_DIS \ + << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ + PM_GPIOWKEN_DIS \ + Setting */ #define MXC_V_GCR_PM_GPIOWKEN_EN \ ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value \ */ -#define MXC_S_GCR_PM_GPIOWKEN_EN \ - (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ - PM_GPIOWKEN_EN \ - Setting */ +#define MXC_S_GCR_PM_GPIOWKEN_EN \ + (MXC_V_GCR_PM_GPIOWKEN_EN \ + << MXC_F_GCR_PM_GPIOWKEN_POS) /**< \ + PM_GPIOWKEN_EN \ + Setting */ #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ #define MXC_F_GCR_PM_RTCWKEN \ @@ -939,10 +1022,11 @@ typedef struct { #define MXC_V_GCR_PM_RTCWKEN_DIS \ ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value \ */ -#define MXC_S_GCR_PM_RTCWKEN_DIS \ - (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< \ - PM_RTCWKEN_DIS \ - Setting */ +#define MXC_S_GCR_PM_RTCWKEN_DIS \ + (MXC_V_GCR_PM_RTCWKEN_DIS \ + << MXC_F_GCR_PM_RTCWKEN_POS) /**< \ + PM_RTCWKEN_DIS \ + Setting */ #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */ #define MXC_S_GCR_PM_RTCWKEN_EN \ (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< \ @@ -954,17 +1038,19 @@ typedef struct { ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ #define MXC_V_GCR_PM_HIRCPD_ACTIVE \ ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ -#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ - (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< \ - PM_HIRCPD_ACTIVE \ - Setting */ +#define MXC_S_GCR_PM_HIRCPD_ACTIVE \ + (MXC_V_GCR_PM_HIRCPD_ACTIVE \ + << MXC_F_GCR_PM_HIRCPD_POS) /**< \ + PM_HIRCPD_ACTIVE \ + Setting */ #define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ -#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ - (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< \ - PM_HIRCPD_DEEPSLEEP \ - Setting \ - */ +#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP \ + (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP \ + << MXC_F_GCR_PM_HIRCPD_POS) /**< \ + PM_HIRCPD_DEEPSLEEP \ + Setting \ + */ /** * Peripheral Clock Divider. @@ -975,32 +1061,36 @@ typedef struct { Mask */ #define MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ - PCKDIV_AONCD_DIV_4 \ - Setting \ - */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_4 \ + << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_4 \ + Setting \ + */ #define MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ - PCKDIV_AONCD_DIV_8 \ - Setting \ - */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_8 \ + << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_8 \ + Setting \ + */ #define MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ - PCKDIV_AONCD_DIV_16 \ - Setting \ - */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_16 \ + << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_16 \ + Setting \ + */ #define MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ -#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ - (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ - PCKDIV_AONCD_DIV_32 \ - Setting \ - */ +#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 \ + (MXC_V_GCR_PCKDIV_AONCD_DIV_32 \ + << MXC_F_GCR_PCKDIV_AONCD_POS) /**< \ + PCKDIV_AONCD_DIV_32 \ + Setting \ + */ /** * Peripheral Clock Disable. @@ -1012,18 +1102,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_GPIO0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ - (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ - PERCKCN0_GPIO0D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_GPIO0D_EN \ + (MXC_V_GCR_PERCKCN0_GPIO0D_EN \ + << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ + PERCKCN0_GPIO0D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ - (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ - PERCKCN0_GPIO0D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS \ + (MXC_V_GCR_PERCKCN0_GPIO0D_DIS \ + << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< \ + PERCKCN0_GPIO0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ #define MXC_F_GCR_PERCKCN0_DMAD \ @@ -1031,18 +1123,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_DMAD_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_EN \ - (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ - PERCKCN0_DMAD_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_DMAD_EN \ + (MXC_V_GCR_PERCKCN0_DMAD_EN \ + << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ + PERCKCN0_DMAD_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_DMAD_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */ -#define MXC_S_GCR_PERCKCN0_DMAD_DIS \ - (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ - PERCKCN0_DMAD_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_DMAD_DIS \ + (MXC_V_GCR_PERCKCN0_DMAD_DIS \ + << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< \ + PERCKCN0_DMAD_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ #define MXC_F_GCR_PERCKCN0_SPI0D \ @@ -1051,18 +1145,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_SPI0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_EN \ - (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ - PERCKCN0_SPI0D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_SPI0D_EN \ + (MXC_V_GCR_PERCKCN0_SPI0D_EN \ + << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ + PERCKCN0_SPI0D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_SPI0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI0D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ - PERCKCN0_SPI0D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_SPI0D_DIS \ + (MXC_V_GCR_PERCKCN0_SPI0D_DIS \ + << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< \ + PERCKCN0_SPI0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ #define MXC_F_GCR_PERCKCN0_SPI1D \ @@ -1071,18 +1167,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_SPI1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_EN \ - (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ - PERCKCN0_SPI1D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_SPI1D_EN \ + (MXC_V_GCR_PERCKCN0_SPI1D_EN \ + << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ + PERCKCN0_SPI1D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_SPI1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_SPI1D_DIS \ - (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ - PERCKCN0_SPI1D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_SPI1D_DIS \ + (MXC_V_GCR_PERCKCN0_SPI1D_DIS \ + << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< \ + PERCKCN0_SPI1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ #define MXC_F_GCR_PERCKCN0_UART0D \ @@ -1091,18 +1189,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_UART0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_EN \ - (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ - PERCKCN0_UART0D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_UART0D_EN \ + (MXC_V_GCR_PERCKCN0_UART0D_EN \ + << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ + PERCKCN0_UART0D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_UART0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART0D_DIS \ - (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ - PERCKCN0_UART0D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_UART0D_DIS \ + (MXC_V_GCR_PERCKCN0_UART0D_DIS \ + << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< \ + PERCKCN0_UART0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ #define MXC_F_GCR_PERCKCN0_UART1D \ @@ -1111,18 +1211,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_UART1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_EN \ - (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ - PERCKCN0_UART1D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_UART1D_EN \ + (MXC_V_GCR_PERCKCN0_UART1D_EN \ + << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ + PERCKCN0_UART1D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_UART1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_UART1D_DIS \ - (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ - PERCKCN0_UART1D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_UART1D_DIS \ + (MXC_V_GCR_PERCKCN0_UART1D_DIS \ + << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< \ + PERCKCN0_UART1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ #define MXC_F_GCR_PERCKCN0_I2C0D \ @@ -1131,18 +1233,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_I2C0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_EN \ - (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ - PERCKCN0_I2C0D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_I2C0D_EN \ + (MXC_V_GCR_PERCKCN0_I2C0D_EN \ + << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ + PERCKCN0_I2C0D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_I2C0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C0D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ - PERCKCN0_I2C0D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_I2C0D_DIS \ + (MXC_V_GCR_PERCKCN0_I2C0D_DIS \ + << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< \ + PERCKCN0_I2C0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ #define MXC_F_GCR_PERCKCN0_T0D \ @@ -1150,18 +1254,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_T0D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T0D_EN \ - (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ - PERCKCN0_T0D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T0D_EN \ + (MXC_V_GCR_PERCKCN0_T0D_EN \ + << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ + PERCKCN0_T0D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_T0D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T0D_DIS \ - (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ - PERCKCN0_T0D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T0D_DIS \ + (MXC_V_GCR_PERCKCN0_T0D_DIS \ + << MXC_F_GCR_PERCKCN0_T0D_POS) /**< \ + PERCKCN0_T0D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ #define MXC_F_GCR_PERCKCN0_T1D \ @@ -1169,18 +1275,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_T1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T1D_EN \ - (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ - PERCKCN0_T1D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T1D_EN \ + (MXC_V_GCR_PERCKCN0_T1D_EN \ + << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ + PERCKCN0_T1D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_T1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T1D_DIS \ - (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ - PERCKCN0_T1D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T1D_DIS \ + (MXC_V_GCR_PERCKCN0_T1D_DIS \ + << MXC_F_GCR_PERCKCN0_T1D_POS) /**< \ + PERCKCN0_T1D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ #define MXC_F_GCR_PERCKCN0_T2D \ @@ -1188,18 +1296,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_T2D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */ -#define MXC_S_GCR_PERCKCN0_T2D_EN \ - (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ - PERCKCN0_T2D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T2D_EN \ + (MXC_V_GCR_PERCKCN0_T2D_EN \ + << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ + PERCKCN0_T2D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_T2D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_T2D_DIS \ - (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ - PERCKCN0_T2D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_T2D_DIS \ + (MXC_V_GCR_PERCKCN0_T2D_DIS \ + << MXC_F_GCR_PERCKCN0_T2D_POS) /**< \ + PERCKCN0_T2D_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ #define MXC_F_GCR_PERCKCN0_I2C1D \ @@ -1208,18 +1318,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN0_I2C1D_EN \ ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_EN \ - (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ - PERCKCN0_I2C1D_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_I2C1D_EN \ + (MXC_V_GCR_PERCKCN0_I2C1D_EN \ + << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ + PERCKCN0_I2C1D_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN0_I2C1D_DIS \ ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */ -#define MXC_S_GCR_PERCKCN0_I2C1D_DIS \ - (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ - PERCKCN0_I2C1D_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN0_I2C1D_DIS \ + (MXC_V_GCR_PERCKCN0_I2C1D_DIS \ + << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< \ + PERCKCN0_I2C1D_DIS \ + Setting \ + */ /** * Memory Clock Control Register. @@ -1336,18 +1448,20 @@ typedef struct { Mask */ #define MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ - (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ - MEMZCN_SRAM0Z_NOP \ - Setting \ - */ +#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP \ + (MXC_V_GCR_MEMZCN_SRAM0Z_NOP \ + << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ + MEMZCN_SRAM0Z_NOP \ + Setting \ + */ #define MXC_V_GCR_MEMZCN_SRAM0Z_START \ ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ -#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ - (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ - MEMZCN_SRAM0Z_START \ - Setting \ - */ +#define MXC_S_GCR_MEMZCN_SRAM0Z_START \ + (MXC_V_GCR_MEMZCN_SRAM0Z_START \ + << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< \ + MEMZCN_SRAM0Z_START \ + Setting \ + */ #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */ #define MXC_F_GCR_MEMZCN_ICACHEZ \ @@ -1356,18 +1470,20 @@ typedef struct { Mask */ #define MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP \ - (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ - MEMZCN_ICACHEZ_NOP \ - Setting \ - */ +#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP \ + (MXC_V_GCR_MEMZCN_ICACHEZ_NOP \ + << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ + MEMZCN_ICACHEZ_NOP \ + Setting \ + */ #define MXC_V_GCR_MEMZCN_ICACHEZ_START \ ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */ -#define MXC_S_GCR_MEMZCN_ICACHEZ_START \ - (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ - MEMZCN_ICACHEZ_START \ - Setting \ - */ +#define MXC_S_GCR_MEMZCN_ICACHEZ_START \ + (MXC_V_GCR_MEMZCN_ICACHEZ_START \ + << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< \ + MEMZCN_ICACHEZ_START \ + Setting \ + */ /** * System Status Register. @@ -1414,18 +1530,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SYSST_SCMEMF_NORM \ ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */ -#define MXC_S_GCR_SYSST_SCMEMF_NORM \ - (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ - SYSST_SCMEMF_NORM \ - Setting \ - */ +#define MXC_S_GCR_SYSST_SCMEMF_NORM \ + (MXC_V_GCR_SYSST_SCMEMF_NORM \ + << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ + SYSST_SCMEMF_NORM \ + Setting \ + */ #define MXC_V_GCR_SYSST_SCMEMF_MEMORY \ ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */ -#define MXC_S_GCR_SYSST_SCMEMF_MEMORY \ - (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ - SYSST_SCMEMF_MEMORY \ - Setting \ - */ +#define MXC_S_GCR_SYSST_SCMEMF_MEMORY \ + (MXC_V_GCR_SYSST_SCMEMF_MEMORY \ + << MXC_F_GCR_SYSST_SCMEMF_POS) /**< \ + SYSST_SCMEMF_MEMORY \ + Setting \ + */ /** * Reset Register. @@ -1436,23 +1554,26 @@ typedef struct { */ #define MXC_V_GCR_RSTR1_I2C1_RESET \ ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET \ - (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ - RSTR1_I2C1_RESET \ - Setting */ +#define MXC_S_GCR_RSTR1_I2C1_RESET \ + (MXC_V_GCR_RSTR1_I2C1_RESET \ + << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_RESET \ + Setting */ #define MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */ -#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE \ - (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ - RSTR1_I2C1_RESET_DONE \ - Setting \ - */ +#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE \ + (MXC_V_GCR_RSTR1_I2C1_RESET_DONE \ + << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_RESET_DONE \ + Setting \ + */ #define MXC_V_GCR_RSTR1_I2C1_BUSY \ ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */ -#define MXC_S_GCR_RSTR1_I2C1_BUSY \ - (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ - RSTR1_I2C1_BUSY \ - Setting */ +#define MXC_S_GCR_RSTR1_I2C1_BUSY \ + (MXC_V_GCR_RSTR1_I2C1_BUSY \ + << MXC_F_GCR_RSTR1_I2C1_POS) /**< \ + RSTR1_I2C1_BUSY \ + Setting */ /** * Peripheral Clock Disable. @@ -1463,18 +1584,20 @@ typedef struct { Mask */ #define MXC_V_GCR_PERCKCN1_FLCD_EN \ ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_EN \ - (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ - PERCKCN1_FLCD_EN \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN1_FLCD_EN \ + (MXC_V_GCR_PERCKCN1_FLCD_EN \ + << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ + PERCKCN1_FLCD_EN \ + Setting \ + */ #define MXC_V_GCR_PERCKCN1_FLCD_DIS \ ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */ -#define MXC_S_GCR_PERCKCN1_FLCD_DIS \ - (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ - PERCKCN1_FLCD_DIS \ - Setting \ - */ +#define MXC_S_GCR_PERCKCN1_FLCD_DIS \ + (MXC_V_GCR_PERCKCN1_FLCD_DIS \ + << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< \ + PERCKCN1_FLCD_DIS \ + Setting \ + */ #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ #define MXC_F_GCR_PERCKCN1_ICACHED \ @@ -1528,18 +1651,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SYSSIE_ICEULIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ - (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ - SYSSIE_ICEULIE_DIS \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_ICEULIE_DIS \ + (MXC_V_GCR_SYSSIE_ICEULIE_DIS \ + << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ + SYSSIE_ICEULIE_DIS \ + Setting \ + */ #define MXC_V_GCR_SYSSIE_ICEULIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ -#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ - (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ - SYSSIE_ICEULIE_EN \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_ICEULIE_EN \ + (MXC_V_GCR_SYSSIE_ICEULIE_EN \ + << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< \ + SYSSIE_ICEULIE_EN \ + Setting \ + */ #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ #define MXC_F_GCR_SYSSIE_CIEIE \ @@ -1547,18 +1672,20 @@ typedef struct { Mask */ #define MXC_V_GCR_SYSSIE_CIEIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_DIS \ - (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ - SYSSIE_CIEIE_DIS \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_CIEIE_DIS \ + (MXC_V_GCR_SYSSIE_CIEIE_DIS \ + << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ + SYSSIE_CIEIE_DIS \ + Setting \ + */ #define MXC_V_GCR_SYSSIE_CIEIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */ -#define MXC_S_GCR_SYSSIE_CIEIE_EN \ - (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ - SYSSIE_CIEIE_EN \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_CIEIE_EN \ + (MXC_V_GCR_SYSSIE_CIEIE_EN \ + << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< \ + SYSSIE_CIEIE_EN \ + Setting \ + */ #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ #define MXC_F_GCR_SYSSIE_SCMFIE \ @@ -1566,17 +1693,19 @@ typedef struct { Mask */ #define MXC_V_GCR_SYSSIE_SCMFIE_DIS \ ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_DIS \ - (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ - SYSSIE_SCMFIE_DIS \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_SCMFIE_DIS \ + (MXC_V_GCR_SYSSIE_SCMFIE_DIS \ + << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ + SYSSIE_SCMFIE_DIS \ + Setting \ + */ #define MXC_V_GCR_SYSSIE_SCMFIE_EN \ ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */ -#define MXC_S_GCR_SYSSIE_SCMFIE_EN \ - (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ - SYSSIE_SCMFIE_EN \ - Setting \ - */ +#define MXC_S_GCR_SYSSIE_SCMFIE_EN \ + (MXC_V_GCR_SYSSIE_SCMFIE_EN \ + << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< \ + SYSSIE_SCMFIE_EN \ + Setting \ + */ #endif /* _GCR_REGS_H_ */ -- cgit v1.2.1 From 6eff324277b4467c372dc98ef1d7685942c2db42 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Sat, 2 Jul 2022 13:39:32 +1000 Subject: zephyr: Use optional gpios for remapping to unused GPIO Use missing 'gpios' property to indicate that a GPIO references a special unimplemented GPIO enum. This may be used instead of having to create new Kconfig options for conditionally compiling hardcoded references to these GPIOS. BUG=b:237716584 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: Ifc0799712b5787fd588bb096176a8ac51a7b00b7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3740391 Reviewed-by: Jack Rosenthal Reviewed-by: Peter Marheine --- zephyr/dts/bindings/gpio/named-gpios.yaml | 5 +++-- zephyr/dts/board-overlays/native_posix.dts | 2 +- zephyr/projects/brya/gpio.dts | 4 ++++ zephyr/projects/brya/include/gpio_map.h | 5 ----- zephyr/projects/corsola/gpio_kingler.dts | 5 ++++- zephyr/projects/corsola/gpio_steelix.dts | 5 ++++- zephyr/projects/corsola/include/gpio_map.h | 5 ----- zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts | 4 ++++ zephyr/projects/intelrvp/include/gpio_map.h | 7 ------- zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts | 4 ++++ zephyr/projects/it8xxx2_evb/gpio.dts | 4 ++++ zephyr/projects/it8xxx2_evb/include/gpio_map.h | 5 ----- zephyr/projects/minimal/include/gpio_map.h | 5 ----- zephyr/projects/minimal/it8xxx2.dts | 4 ++++ zephyr/projects/minimal/npcx9.dts | 4 ++++ zephyr/projects/skyrim/include/gpio_map.h | 6 ------ zephyr/projects/skyrim/skyrim.dts | 7 +++++++ zephyr/shim/include/zephyr_gpio_signal.h | 18 +++++++++++++----- zephyr/shim/src/gpio.c | 6 +++++- 19 files changed, 61 insertions(+), 44 deletions(-) diff --git a/zephyr/dts/bindings/gpio/named-gpios.yaml b/zephyr/dts/bindings/gpio/named-gpios.yaml index 5c1e581509..bf0ba7237e 100644 --- a/zephyr/dts/bindings/gpio/named-gpios.yaml +++ b/zephyr/dts/bindings/gpio/named-gpios.yaml @@ -10,10 +10,11 @@ child-binding: # Must name this property [..-]gpios which # is treated specially (looks for #gpio-cells # in referenced node so that cell properties can - # be specified). + # be specified). If this property does not exist, treat + # this GPIO as unimplemented. gpios: type: phandle-array - required: true + required: false "#led-pin-cells": type: int required: false diff --git a/zephyr/dts/board-overlays/native_posix.dts b/zephyr/dts/board-overlays/native_posix.dts index 7801997553..45712f57b5 100644 --- a/zephyr/dts/board-overlays/native_posix.dts +++ b/zephyr/dts/board-overlays/native_posix.dts @@ -9,7 +9,7 @@ named-gpios { compatible = "named-gpios"; - entering_rw { + entering-rw { gpios = <&gpio0 1 GPIO_OUTPUT_LOW>; enum-name = "GPIO_ENTERING_RW"; }; diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts index 517dea8ef4..aaf34861c8 100644 --- a/zephyr/projects/brya/gpio.dts +++ b/zephyr/projects/brya/gpio.dts @@ -302,6 +302,10 @@ enum-name = "IOEX_USB_C2_FRS_EN"; no-auto-init; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; usba-port-enable-list { diff --git a/zephyr/projects/brya/include/gpio_map.h b/zephyr/projects/brya/include/gpio_map.h index 4ebfbe31b6..c2b81fe5c6 100644 --- a/zephyr/projects/brya/include/gpio_map.h +++ b/zephyr/projects/brya/include/gpio_map.h @@ -6,9 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#include -#include - -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/corsola/gpio_kingler.dts b/zephyr/projects/corsola/gpio_kingler.dts index f117140ea7..db90258263 100644 --- a/zephyr/projects/corsola/gpio_kingler.dts +++ b/zephyr/projects/corsola/gpio_kingler.dts @@ -112,7 +112,6 @@ }; ec_entering_rw { gpios = <&gpio0 3 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; }; charger_prochot_odl { gpios = <&gpiob 1 GPIO_INPUT>; @@ -214,6 +213,10 @@ gpios = <&gpioe 5 GPIO_INPUT>; enum-name = "GPIO_CCD_MODE_ODL"; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; /* diff --git a/zephyr/projects/corsola/gpio_steelix.dts b/zephyr/projects/corsola/gpio_steelix.dts index 4d7b9a507c..c81f101af5 100644 --- a/zephyr/projects/corsola/gpio_steelix.dts +++ b/zephyr/projects/corsola/gpio_steelix.dts @@ -118,7 +118,6 @@ }; ec_entering_rw { gpios = <&gpio0 3 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; }; charger_prochot_odl { gpios = <&gpiob 1 GPIO_INPUT>; @@ -220,6 +219,10 @@ gpios = <&gpioe 5 GPIO_INPUT>; enum-name = "GPIO_CCD_MODE_ODL"; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; /* diff --git a/zephyr/projects/corsola/include/gpio_map.h b/zephyr/projects/corsola/include/gpio_map.h index 4ebfbe31b6..c2b81fe5c6 100644 --- a/zephyr/projects/corsola/include/gpio_map.h +++ b/zephyr/projects/corsola/include/gpio_map.h @@ -6,9 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#include -#include - -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 6c3c965d66..8b2adef564 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -336,5 +336,9 @@ gpios = <&ioex_c3_port 8 GPIO_OUTPUT_HIGH>; enum-name = "IOEX_USB_C2_C3_OC"; }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; }; }; diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h index 3c723e21c8..ac31d03926 100644 --- a/zephyr/projects/intelrvp/include/gpio_map.h +++ b/zephyr/projects/intelrvp/include/gpio_map.h @@ -6,11 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#define GPIO_EN_PP5000 GPIO_UNIMPLEMENTED - -/* TODO: Implement GPIO_ENTERING_RW in IOEX */ -#ifdef CONFIG_BOARD_MTLRVP_NPCX -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#endif /* CONFIG_BOARD_MTLRVP_NPCK */ - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts index c3cd9e6abb..924f508f5f 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -307,6 +307,10 @@ usb-c0-mux-sbu-sel-1 { gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>; }; + /* unimplemented GPIOs */ + en-pp5000 { + enum-name = "GPIO_EN_PP5000"; + }; }; def-lvol-io-list { diff --git a/zephyr/projects/it8xxx2_evb/gpio.dts b/zephyr/projects/it8xxx2_evb/gpio.dts index 51c6a45ca9..4376e7bd62 100644 --- a/zephyr/projects/it8xxx2_evb/gpio.dts +++ b/zephyr/projects/it8xxx2_evb/gpio.dts @@ -39,6 +39,10 @@ spi0_cs: spi0_cs { gpios = <&gpiom 5 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; hibernate-wake-pins { diff --git a/zephyr/projects/it8xxx2_evb/include/gpio_map.h b/zephyr/projects/it8xxx2_evb/include/gpio_map.h index 4ebfbe31b6..c2b81fe5c6 100644 --- a/zephyr/projects/it8xxx2_evb/include/gpio_map.h +++ b/zephyr/projects/it8xxx2_evb/include/gpio_map.h @@ -6,9 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#include -#include - -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/minimal/include/gpio_map.h b/zephyr/projects/minimal/include/gpio_map.h index e3009f49d5..886e7d1ebf 100644 --- a/zephyr/projects/minimal/include/gpio_map.h +++ b/zephyr/projects/minimal/include/gpio_map.h @@ -6,9 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -/* GPIO_ENTERING_RW implemented by GPIO emulator on native_posix */ -#ifndef CONFIG_BOARD_NATIVE_POSIX -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#endif - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/minimal/it8xxx2.dts b/zephyr/projects/minimal/it8xxx2.dts index f199cfa87e..46efc9ca56 100644 --- a/zephyr/projects/minimal/it8xxx2.dts +++ b/zephyr/projects/minimal/it8xxx2.dts @@ -14,5 +14,9 @@ ec_wp_l: write-protect { gpios = <&gpioa 0 GPIO_INPUT>; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; }; diff --git a/zephyr/projects/minimal/npcx9.dts b/zephyr/projects/minimal/npcx9.dts index b0184d769e..825e2db6db 100644 --- a/zephyr/projects/minimal/npcx9.dts +++ b/zephyr/projects/minimal/npcx9.dts @@ -14,6 +14,10 @@ ec_wp_l: write-protect { gpios = <&gpioa 0 GPIO_INPUT>; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; }; }; diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h index 67ba4fa9ad..c2b81fe5c6 100644 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ b/zephyr/projects/skyrim/include/gpio_map.h @@ -6,10 +6,4 @@ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H -#include -#include - -#define GPIO_ENTERING_RW GPIO_UNIMPLEMENTED -#define GPIO_PCH_SYS_PWROK GPIO_UNIMPLEMENTED - #endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index ebccda5eb9..dae7387ffb 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -81,6 +81,13 @@ gpio_accel_gyro_int_l: accel_gyro_int_l { gpios = <&gpioa 0 GPIO_INPUT>; }; + /* unimplemented GPIOs */ + entering-rw { + enum-name = "GPIO_ENTERING_RW"; + }; + pch-sys-prwok { + enum-name = "GPIO_PCH_SYS_PWROK"; + }; }; def-lvol-io-list { diff --git a/zephyr/shim/include/zephyr_gpio_signal.h b/zephyr/shim/include/zephyr_gpio_signal.h index e7514bfc5e..e15f55e74c 100644 --- a/zephyr/shim/include/zephyr_gpio_signal.h +++ b/zephyr/shim/include/zephyr_gpio_signal.h @@ -40,7 +40,13 @@ (GPIO_SIGNAL_NAME_FROM_ORD(id##_ORD))) #define GPIO_SIGNAL(id) GPIO_SIGNAL_NAME(id) -#define GPIO_SIGNAL_WITH_COMMA(id) GPIO_SIGNAL(id), + +#define GPIO_IMPL_SIGNAL(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_SIGNAL(id), ), ()) + +#define GPIO_UNIMPL_SIGNAL(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (), \ + (GPIO_SIGNAL_NAME(id) = GPIO_UNIMPLEMENTED, )) /* * Create a list of aliases to allow remapping of aliased names. */ @@ -53,21 +59,23 @@ enum gpio_signal { GPIO_UNIMPLEMENTED = -1, #if DT_NODE_EXISTS(DT_PATH(named_gpios)) - DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_SIGNAL_WITH_COMMA) + DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_IMPL_SIGNAL) #endif GPIO_COUNT, #if DT_NODE_EXISTS(DT_PATH(named_gpios)) - DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_ALIAS_LIST) + DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_UNIMPL_SIGNAL) + DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_DT_ALIAS_LIST) #endif - GPIO_LIMIT = 0x0FFF, + GPIO_LIMIT = 0x0FFF, IOEX_SIGNAL_START = GPIO_LIMIT + 1, IOEX_SIGNAL_END = IOEX_SIGNAL_START, IOEX_LIMIT = 0x1FFF, }; -#undef GPIO_SIGNAL_WITH_COMMA #undef GPIO_DT_ALIAS_LIST #undef GPIO_DT_MK_ALIAS +#undef GPIO_IMPL_SIGNAL +#undef GPIO_UNIMPL_SIGNAL BUILD_ASSERT(GPIO_COUNT < GPIO_LIMIT); diff --git a/zephyr/shim/src/gpio.c b/zephyr/shim/src/gpio.c index e0415a3961..cb94d01822 100644 --- a/zephyr/shim/src/gpio.c +++ b/zephyr/shim/src/gpio.c @@ -55,12 +55,16 @@ struct gpio_config { .init_flags = DT_GPIO_FLAGS(id, gpios), \ .no_auto_init = DT_PROP(id, no_auto_init), \ }, +#define GPIO_IMPL_CONFIG(id) \ + COND_CODE_1(DT_NODE_HAS_PROP(id, gpios), (GPIO_CONFIG(id)), ()) + static const struct gpio_config configs[] = { #if DT_NODE_EXISTS(DT_PATH(named_gpios)) - DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_CONFIG) + DT_FOREACH_CHILD(DT_PATH(named_gpios), GPIO_IMPL_CONFIG) #endif }; +#undef GPIO_IMPL_CONFIG #undef GPIO_CONFIG #undef OUR_DT_SPEC -- cgit v1.2.1 From ac352c63e5a8d4329f6d12e2beaf1c40cd6c0f59 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Thu, 7 Jul 2022 12:59:14 +1000 Subject: zephyr: Remove gpio_map.h legacy include file Remove gpio_map.h and update Kconfig references to it. BUG=b:237716584 TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: I4b21b53a4a63c6a934f9ab3bef3707e225bd01b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750267 Reviewed-by: Jack Rosenthal --- zephyr/Kconfig | 6 +++--- zephyr/Kconfig.battery | 8 +++---- zephyr/Kconfig.espi | 4 ++-- zephyr/Kconfig.keyboard | 4 ++-- zephyr/Kconfig.mkbp_event | 2 +- zephyr/Kconfig.powerseq | 4 ++-- zephyr/projects/brya/include/gpio_map.h | 9 -------- zephyr/projects/corsola/include/gpio_map.h | 9 -------- zephyr/projects/herobrine/include/gpio_map.h | 9 -------- zephyr/projects/intelrvp/include/gpio_map.h | 9 -------- zephyr/projects/it8xxx2_evb/include/gpio_map.h | 9 -------- zephyr/projects/minimal/include/gpio_map.h | 9 -------- zephyr/projects/nissa/include/gpio_map.h | 4 ---- zephyr/projects/npcx_evb/npcx7/include/gpio_map.h | 9 -------- zephyr/projects/npcx_evb/npcx9/include/gpio_map.h | 9 -------- zephyr/projects/skyrim/include/gpio_map.h | 9 -------- zephyr/projects/skyrim/include_guybrush/gpio_map.h | 25 ---------------------- zephyr/projects/trogdor/lazor/include/gpio_map.h | 9 -------- zephyr/shim/include/board.h | 5 ----- 19 files changed, 13 insertions(+), 139 deletions(-) delete mode 100644 zephyr/projects/brya/include/gpio_map.h delete mode 100644 zephyr/projects/corsola/include/gpio_map.h delete mode 100644 zephyr/projects/herobrine/include/gpio_map.h delete mode 100644 zephyr/projects/intelrvp/include/gpio_map.h delete mode 100644 zephyr/projects/it8xxx2_evb/include/gpio_map.h delete mode 100644 zephyr/projects/minimal/include/gpio_map.h delete mode 100644 zephyr/projects/nissa/include/gpio_map.h delete mode 100644 zephyr/projects/npcx_evb/npcx7/include/gpio_map.h delete mode 100644 zephyr/projects/npcx_evb/npcx9/include/gpio_map.h delete mode 100644 zephyr/projects/skyrim/include/gpio_map.h delete mode 100644 zephyr/projects/skyrim/include_guybrush/gpio_map.h delete mode 100644 zephyr/projects/trogdor/lazor/include/gpio_map.h diff --git a/zephyr/Kconfig b/zephyr/Kconfig index 6e17b9ed13..33176c4237 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -327,7 +327,7 @@ config PLATFORM_EC_EXTPOWER_GPIO Enable shimming the extpower_gpio module, which provides GPIO-based external power presence detection features. The project should define a GPIO pin named GPIO_AC_PRESENT, with - extpower_interrupt configured as the handler in gpio_map.h. + extpower_interrupt configured as the handler. config PLATFORM_EC_FLASH_CROS bool @@ -429,7 +429,7 @@ config PLATFORM_EC_LID_SWITCH behaviour. For example, when the lid is opened, the device may automatically power on. - This requires a GPIO named GPIO_LID_OPEN to be defined in gpio_map.h. + This requires a GPIO named GPIO_LID_OPEN to be defined or aliased. config PLATFORM_EC_MKBP_INPUT_DEVICES bool "Input devices via MKBP" @@ -540,7 +540,7 @@ config PLATFORM_EC_POWER_BUTTON commands in platform/ec. This is used to implement the Chromium OS shutdown sequence. - This requires a GPIO named GPIO_POWER_BUTTON_L in gpio_map.h. + This requires a GPIO named GPIO_POWER_BUTTON_L. config PLATFORM_EC_PWM_HC bool diff --git a/zephyr/Kconfig.battery b/zephyr/Kconfig.battery index 7b3f20da38..123c5eba58 100644 --- a/zephyr/Kconfig.battery +++ b/zephyr/Kconfig.battery @@ -57,19 +57,17 @@ config PLATFORM_EC_BATTERY_PRESENT_GPIO GPIO should read low if the battery is present, high if absent. The GPIO is hard-coded to GPIO_BATT_PRES_ODL so you should define this - in the device tree and GPIO map. The convention is to use the signal + in the device tree. The convention is to use the signal name from schematic as both the node name and label for the GPIO. For example: /* gpio.dts */ ec_batt_pres_odl { gpios = <&gpioe 5 GPIO_INPUT>; - label = "EC_BATT_PRES_ODL"; + enum-name = "EC_BATT_PRES_ODL"; + alias = "GPIO_BATT_PRES_ODL"; }; - /* gpio_map.h */ - #define GPIO_BATT_PRES_ODL NAMED_GPIO(ec_batt_pres_odl) - endchoice # PLATFORM_EC_BATTERY_PRESENT_MODE config PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY diff --git a/zephyr/Kconfig.espi b/zephyr/Kconfig.espi index 60ea99def7..d608a164ef 100644 --- a/zephyr/Kconfig.espi +++ b/zephyr/Kconfig.espi @@ -8,13 +8,13 @@ config PLATFORM_EC_ESPI_VW_SLP_S3 bool "SLP_S3 is an eSPI virtual wire instead of a GPIO" help For power sequencing, use an eSPI virtual wire instead of - defining GPIO_PCH_SLP_S3 in gpio_map.h. + defining GPIO_PCH_SLP_S3 in the GPIO device tree. config PLATFORM_EC_ESPI_VW_SLP_S4 bool "SLP_S4 is an eSPI virtual wire instead of a GPIO" help For power sequencing, use an eSPI virtual wire instead of - defining GPIO_PCH_SLP_S4 in gpio_map.h. + defining GPIO_PCH_SLP_S4 in the GPIO device tree. config PLATFORM_EC_ESPI_VW_SLP_S5 bool "SLP_S5 is an eSPI virtual wire instead of an alias for SLP_S4" diff --git a/zephyr/Kconfig.keyboard b/zephyr/Kconfig.keyboard index 8bcc32af8e..51cf7bf433 100644 --- a/zephyr/Kconfig.keyboard +++ b/zephyr/Kconfig.keyboard @@ -145,8 +145,8 @@ config PLATFORM_EC_VOLUME_BUTTONS These are buttons controlled by GPIOs and are not part of the keyboard matrix. - Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L in - gpio_map.h + Your board must define GPIO_VOLUME_UP_L and GPIO_VOLUME_DOWN_L as + GPIOs names or as aliases in the GPIO devicetree configuration. config PLATFORM_EC_BUTTONS_RUNTIME_CONFIG bool "Enable buttons runtime configuration" diff --git a/zephyr/Kconfig.mkbp_event b/zephyr/Kconfig.mkbp_event index e24cf370d2..66dc2e0690 100644 --- a/zephyr/Kconfig.mkbp_event +++ b/zephyr/Kconfig.mkbp_event @@ -14,7 +14,7 @@ config PLATFORM_EC_MKBP_USE_GPIO bool "Use GPIO" help Select to send MKBP events via GPIO. You should define GPIO_EC_INT_L - in gpio_map.h as output from the EC. The GPIO is used to indicate an + as a GPIO output from the EC. The GPIO is used to indicate an event is ready for serving by the AP. config PLATFORM_EC_MKBP_USE_HOST_EVENT diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq index f0db496082..dbc8187830 100644 --- a/zephyr/Kconfig.powerseq +++ b/zephyr/Kconfig.powerseq @@ -126,8 +126,8 @@ config PLATFORM_EC_POWERSEQ_RTC_RESET bool "Board has an RTC reset" help This project has a gpio named GPIO_PCH_RTCRST defined in - gpio_map.h, which can be used to reset the AP's RTC when set - high. + the GPIO configuration, which can be used to reset the AP's RTC when + set high. config PLATFORM_EC_POWERSEQ_S4 bool "Advertise S4 residency" diff --git a/zephyr/projects/brya/include/gpio_map.h b/zephyr/projects/brya/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/brya/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/corsola/include/gpio_map.h b/zephyr/projects/corsola/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/corsola/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/herobrine/include/gpio_map.h b/zephyr/projects/herobrine/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/herobrine/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/intelrvp/include/gpio_map.h b/zephyr/projects/intelrvp/include/gpio_map.h deleted file mode 100644 index ac31d03926..0000000000 --- a/zephyr/projects/intelrvp/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/it8xxx2_evb/include/gpio_map.h b/zephyr/projects/it8xxx2_evb/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/it8xxx2_evb/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/minimal/include/gpio_map.h b/zephyr/projects/minimal/include/gpio_map.h deleted file mode 100644 index 886e7d1ebf..0000000000 --- a/zephyr/projects/minimal/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/nissa/include/gpio_map.h b/zephyr/projects/nissa/include/gpio_map.h deleted file mode 100644 index e99bf2c131..0000000000 --- a/zephyr/projects/nissa/include/gpio_map.h +++ /dev/null @@ -1,4 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ diff --git a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/npcx_evb/npcx7/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h b/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/npcx_evb/npcx9/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/include/gpio_map.h b/zephyr/projects/skyrim/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/skyrim/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/skyrim/include_guybrush/gpio_map.h b/zephyr/projects/skyrim/include_guybrush/gpio_map.h deleted file mode 100644 index 22d0eb602e..0000000000 --- a/zephyr/projects/skyrim/include_guybrush/gpio_map.h +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#include -#include - -/* Power input signals */ -enum power_signal { - X86_SLP_S0_N, /* SOC -> SLP_S3_S0I3_L */ - X86_SLP_S3_N, /* SOC -> SLP_S3_L */ - X86_SLP_S5_N, /* SOC -> SLP_S5_L */ - - X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */ - X86_S5_PGOOD, /* PMIC -> S5_PWROK */ - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT, -}; - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/trogdor/lazor/include/gpio_map.h b/zephyr/projects/trogdor/lazor/include/gpio_map.h deleted file mode 100644 index c2b81fe5c6..0000000000 --- a/zephyr/projects/trogdor/lazor/include/gpio_map.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __ZEPHYR_GPIO_MAP_H -#define __ZEPHYR_GPIO_MAP_H - -#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/shim/include/board.h b/zephyr/shim/include/board.h index c1a391b56a..1175ad4a28 100644 --- a/zephyr/shim/include/board.h +++ b/zephyr/shim/include/board.h @@ -15,11 +15,6 @@ /* Include shimmed version of power signal */ #include "power/power.h" -/* Include board specific gpio mapping/aliases if named_pgios node exists */ -#if !defined(TEST_BUILD) && DT_NODE_EXISTS(DT_PATH(named_gpios)) -#include "gpio_map.h" -#endif - /* Include board specific i2c mapping if I2C is enabled. */ #if defined(CONFIG_I2C) #include "i2c/i2c.h" -- cgit v1.2.1 From 78d561694b9307ad6bb4eda65cc50c80300d0a54 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:58 -0600 Subject: board/servo_v4/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib378ce961b759abff7ce095412d9dfde99bb110f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749420 Reviewed-by: Jeremy Bettis --- board/servo_v4/usb_pd_policy.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/board/servo_v4/usb_pd_policy.c b/board/servo_v4/usb_pd_policy.c index 4e67d6ecf2..48e8ef43e9 100644 --- a/board/servo_v4/usb_pd_policy.c +++ b/board/servo_v4/usb_pd_policy.c @@ -878,15 +878,16 @@ static int dp_status(int port, uint32_t *payload) if (opos != OPOS) return 0; /* NAK */ - payload[1] = VDO_DP_STATUS(0, /* IRQ_HPD */ - hpd, /* HPD_HI|LOW */ - 0, /* request exit DP */ - 0, /* request exit USB */ - (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF - pref - */ - is_typec_dp_muxed(), 0, /* power low */ - hpd ? 0x2 : 0); + payload[1] = + VDO_DP_STATUS(0, /* IRQ_HPD */ + hpd, /* HPD_HI|LOW */ + 0, /* request exit DP */ + 0, /* request exit USB */ + (alt_dp_config & ALT_DP_MF_PREF) != 0, /* MF + pref + */ + is_typec_dp_muxed(), 0, /* power low */ + hpd ? 0x2 : 0); return 2; } -- cgit v1.2.1 From a61556c058a4c75a29f725c60f85c95a535b0c2b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:42 -0600 Subject: chip/max32660/gpio_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I93f395b8ceab89475b2af7956cb32a40dcd9fbed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749432 Reviewed-by: Jeremy Bettis --- chip/max32660/gpio_regs.h | 156 +++++++++++++++++++++++++--------------------- 1 file changed, 86 insertions(+), 70 deletions(-) diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h index 172d8f14c9..a6b7997d5f 100644 --- a/chip/max32660/gpio_regs.h +++ b/chip/max32660/gpio_regs.h @@ -283,18 +283,20 @@ typedef enum { Mask */ #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ -#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ - (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ - EN_GPIO_EN_ALTERNATE \ - Setting \ - */ +#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ + (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ + << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_ALTERNATE \ + Setting \ + */ #define MXC_V_GPIO_EN_GPIO_EN_GPIO \ ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ -#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ - (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ - EN_GPIO_EN_GPIO \ - Setting \ - */ +#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ + (MXC_V_GPIO_EN_GPIO_EN_GPIO \ + << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_GPIO \ + Setting \ + */ /** * GPIO Set Function Enable Register. Writing a 1 to one or more bits @@ -349,10 +351,11 @@ typedef enum { * GPIO_OUT_EN to 1, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ -#define MXC_F_GPIO_OUT_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< \ - OUT_EN_SET_ALL \ - Mask */ +#define MXC_F_GPIO_OUT_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< \ + OUT_EN_SET_ALL \ + Mask */ /** * GPIO Output Enable Clear Function Enable Register. Writing a 1 to @@ -360,10 +363,11 @@ typedef enum { * GPIO_OUT_EN to 0, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ -#define MXC_F_GPIO_OUT_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< \ - OUT_EN_CLR_ALL \ - Mask */ +#define MXC_F_GPIO_OUT_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< \ + OUT_EN_CLR_ALL \ + Mask */ /** * GPIO Output Register. Each bit controls the GPIO_OUT setting for @@ -371,24 +375,27 @@ typedef enum { * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. */ #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ -#define MXC_F_GPIO_OUT_GPIO_OUT \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< \ - OUT_GPIO_OUT \ - Mask */ +#define MXC_F_GPIO_OUT_GPIO_OUT \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< \ + OUT_GPIO_OUT \ + Mask */ #define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ - (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ - OUT_GPIO_OUT_LOW \ - Setting \ - */ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ + (MXC_V_GPIO_OUT_GPIO_OUT_LOW \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_LOW \ + Setting \ + */ #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ - (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ - OUT_GPIO_OUT_HIGH \ - Setting \ - */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ + (MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_HIGH \ + Setting \ + */ /** * GPIO Output Set. Writing a 1 to one or more bits in this register @@ -599,10 +606,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ -#define MXC_F_GPIO_INT_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< \ - INT_CLR_ALL \ - Mask */ +#define MXC_F_GPIO_INT_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< \ + INT_CLR_ALL \ + Mask */ /** * GPIO Wake Enable Register. Each bit in this register controls the @@ -749,17 +757,19 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ -#define MXC_F_GPIO_EN1_GPIO_EN1 \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< \ - EN1_GPIO_EN1 \ - Mask */ +#define MXC_F_GPIO_EN1_GPIO_EN1 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< \ + EN1_GPIO_EN1 \ + Mask */ #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< \ - EN1_GPIO_EN1_PRIMARY \ - Setting \ - */ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ + (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< \ + EN1_GPIO_EN1_PRIMARY \ + Setting \ + */ #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ @@ -773,10 +783,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ -#define MXC_F_GPIO_EN1_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< \ - EN1_SET_ALL \ - Mask */ +#define MXC_F_GPIO_EN1_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< \ + EN1_SET_ALL \ + Mask */ /** * GPIO Alternate Function Clear. Writing a 1 to one or more bits in @@ -784,10 +795,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ -#define MXC_F_GPIO_EN1_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< \ - EN1_CLR_ALL \ - Mask */ +#define MXC_F_GPIO_EN1_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< \ + EN1_CLR_ALL \ + Mask */ /** * GPIO Alternate Function Enable Register. Each bit in this register @@ -795,17 +807,19 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ -#define MXC_F_GPIO_EN2_GPIO_EN2 \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< \ - EN2_GPIO_EN2 \ - Mask */ +#define MXC_F_GPIO_EN2_GPIO_EN2 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< \ + EN2_GPIO_EN2 \ + Mask */ #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< \ - EN2_GPIO_EN2_PRIMARY \ - Setting \ - */ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ + (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< \ + EN2_GPIO_EN2_PRIMARY \ + Setting \ + */ #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ @@ -819,10 +833,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ -#define MXC_F_GPIO_EN2_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< \ - EN2_SET_ALL \ - Mask */ +#define MXC_F_GPIO_EN2_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< \ + EN2_SET_ALL \ + Mask */ /** * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits @@ -830,10 +845,11 @@ typedef enum { * without affecting other bits in that register. */ #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ -#define MXC_F_GPIO_EN2_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< \ - EN2_CLR_ALL \ - Mask */ +#define MXC_F_GPIO_EN2_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< \ + EN2_CLR_ALL \ + Mask */ /** * GPIO Drive Strength Register. Each bit in this register selects -- cgit v1.2.1 From 52a5bb7e14c05f88c66b7c7ef76b03dd1e261e1f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:35 -0600 Subject: board/hoho/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib0f8c01db3972461eb1e8baf08f2d124189a8f5b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749383 Reviewed-by: Jeremy Bettis --- board/hoho/usb_pd_policy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c index e291fca972..e9754d5cda 100644 --- a/board/hoho/usb_pd_policy.c +++ b/board/hoho/usb_pd_policy.c @@ -141,9 +141,10 @@ static int dp_status(int port, uint32_t *payload) 0, /* request exit DP */ 0, /* request exit USB */ 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power - low - */ + gpio_get_level(GPIO_PD_SBU_ENABLE), + 0, /* power + low + */ 0x2); return 2; } -- cgit v1.2.1 From 3422ecb9498857a6d07b4f2c2b1cbc1c0ab53f6a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:43 -0600 Subject: board/hyperdebug/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ie4e5e44a48717d729fd0a38c1ada555e80da6cb3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749385 Reviewed-by: Jeremy Bettis --- board/hyperdebug/board.h | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/board/hyperdebug/board.h b/board/hyperdebug/board.h index e58921e704..1924e740d2 100644 --- a/board/hyperdebug/board.h +++ b/board/hyperdebug/board.h @@ -44,7 +44,7 @@ * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a falling * voltage threshold of min:2.09V, max:2.27V. */ -#define PVD_THRESHOLD (1) +#define PVD_THRESHOLD (1) /* USB Configuration */ @@ -66,25 +66,25 @@ #define DEFAULT_SERIALNO "Uninitialized" /* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_SPI 1 -#define USB_IFACE_I2C 2 -#define USB_IFACE_USART1_STREAM 3 -#define USB_IFACE_USART2_STREAM 4 -#define USB_IFACE_USART4_STREAM 5 -#define USB_IFACE_USART9_STREAM 6 -#define USB_IFACE_COUNT 7 +#define USB_IFACE_CONSOLE 0 +#define USB_IFACE_SPI 1 +#define USB_IFACE_I2C 2 +#define USB_IFACE_USART1_STREAM 3 +#define USB_IFACE_USART2_STREAM 4 +#define USB_IFACE_USART4_STREAM 5 +#define USB_IFACE_USART9_STREAM 6 +#define USB_IFACE_COUNT 7 /* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_SPI 2 -#define USB_EP_I2C 3 -#define USB_EP_USART1_STREAM 4 -#define USB_EP_USART2_STREAM 5 -#define USB_EP_USART4_STREAM 6 -#define USB_EP_USART9_STREAM 7 -#define USB_EP_COUNT 8 +#define USB_EP_CONTROL 0 +#define USB_EP_CONSOLE 1 +#define USB_EP_SPI 2 +#define USB_EP_I2C 3 +#define USB_EP_USART1_STREAM 4 +#define USB_EP_USART2_STREAM 5 +#define USB_EP_USART4_STREAM 6 +#define USB_EP_USART9_STREAM 7 +#define USB_EP_COUNT 8 /* * Do not enable the common EC command gpioset for recasting of GPIO @@ -106,14 +106,13 @@ #define I2C_PORT_CONTROLLER 0 #define CONFIG_STM32_SPI1_CONTROLLER - /* See i2c_ite_flash_support.c for more information about these values */ /*#define CONFIG_ITE_FLASH_SUPPORT */ /*#define CONFIG_I2C_XFER_LARGE_TRANSFER */ #undef CONFIG_USB_I2C_MAX_WRITE_COUNT #undef CONFIG_USB_I2C_MAX_READ_COUNT -#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1<<9) - 4) -#define CONFIG_USB_I2C_MAX_READ_COUNT ((1<<9) - 6) +#define CONFIG_USB_I2C_MAX_WRITE_COUNT ((1 << 9) - 4) +#define CONFIG_USB_I2C_MAX_READ_COUNT ((1 << 9) - 6) /* This is not actually an EC so disable some features. */ #undef CONFIG_WATCHDOG_HELP -- cgit v1.2.1 From df6c7f601be7c4b66a07521279dd602fd26adc09 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:16 -0600 Subject: board/bugzzy/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I894ff9b363cac2ea6fffe8db91c716522445f662 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748794 Reviewed-by: Jeremy Bettis --- board/bugzzy/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/bugzzy/board.h b/board/bugzzy/board.h index 129e8baade..29c0ee0240 100644 --- a/board/bugzzy/board.h +++ b/board/bugzzy/board.h @@ -34,8 +34,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #define CONFIG_CHARGE_RAMP_HW #undef CONFIG_CHARGER_SINGLE_CHIP -- cgit v1.2.1 From 23afa0a0729e897a6736451aad25eded04b472f2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:57 -0600 Subject: zephyr/projects/nissa/src/xivu/charger.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I3393c9c0f766bc179b9e7c91d93a7a6ee1ecd8a8 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749527 Reviewed-by: Jeremy Bettis --- zephyr/projects/nissa/src/xivu/charger.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/nissa/src/xivu/charger.c b/zephyr/projects/nissa/src/xivu/charger.c index 123696746e..7f3933e578 100644 --- a/zephyr/projects/nissa/src/xivu/charger.c +++ b/zephyr/projects/nissa/src/xivu/charger.c @@ -43,11 +43,9 @@ __override void board_check_extpower(void) else extpower_present = 0; - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), extpower_present); - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), extpower_present); } -- cgit v1.2.1 From 167c8bbf0baca287be8cfe96168edafce5b89b2e Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:35 -0600 Subject: driver/nvidia_gpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic41b7577195397317ced3993d0680279f12d57b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749473 Reviewed-by: Jeremy Bettis --- driver/nvidia_gpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/driver/nvidia_gpu.c b/driver/nvidia_gpu.c index f549a03448..764a488ac8 100644 --- a/driver/nvidia_gpu.c +++ b/driver/nvidia_gpu.c @@ -19,8 +19,8 @@ #include "throttle_ap.h" #include "timer.h" -#define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ## args) -#define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ## args) +#define CPRINTS(fmt, args...) cprints(CC_GPU, "GPU: " fmt, ##args) +#define CPRINTF(fmt, args...) cprintf(CC_GPU, "GPU: " fmt, ##args) test_export_static enum d_notify_level d_notify_level = D_NOTIFY_1; test_export_static bool policy_initialized = false; @@ -54,8 +54,8 @@ static void set_d_notify_level(enum d_notify_level level) return; d_notify_level = level; - *memmap_gpu = (*memmap_gpu & ~EC_MEMMAP_GPU_D_NOTIFY_MASK) - | d_notify_level; + *memmap_gpu = (*memmap_gpu & ~EC_MEMMAP_GPU_D_NOTIFY_MASK) | + d_notify_level; host_set_single_event(EC_HOST_EVENT_GPU); CPRINTS("Set D-notify level to D%c", ('1' + (int)d_notify_level)); } @@ -139,8 +139,8 @@ DECLARE_HOOK(HOOK_BATTERY_SOC_CHANGE, handle_battery_soc_change, * is called whenever (and prior to) active port or active supplier or both * changes. */ -void throttle_gpu(enum throttle_level level, - enum throttle_type type, /* not used */ +void throttle_gpu(enum throttle_level level, enum throttle_type type, /* not + used */ enum throttle_sources source) { if (level == THROTTLE_ON) { -- cgit v1.2.1 From fa82a2ed84de0701bf7bb15cb58983ae7a292222 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:42 -0600 Subject: board/osiris/pwm.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Icace7ddb3c635b14b8b0c241dfa920b97cbd3a3e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749416 Reviewed-by: Jeremy Bettis --- board/osiris/pwm.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/board/osiris/pwm.c b/board/osiris/pwm.c index 803c8b0126..a922473361 100644 --- a/board/osiris/pwm.c +++ b/board/osiris/pwm.c @@ -11,15 +11,11 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_FAN] = { - .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, - [PWM_CH_FAN2] = { - .channel = 3, - .flags = PWM_CONFIG_OPEN_DRAIN, - .freq = 25000 - }, + [PWM_CH_FAN] = { .channel = 5, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, + [PWM_CH_FAN2] = { .channel = 3, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, }; BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); -- cgit v1.2.1 From 138d44d4c0b6ddc8915bc8c13ec44fd48c606b55 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:23 -0600 Subject: test/nvidia_gpu.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I16b3799036bd4d25d5bffa55b721c7c51bb8c630 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749521 Reviewed-by: Jeremy Bettis --- test/nvidia_gpu.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/test/nvidia_gpu.c b/test/nvidia_gpu.c index 03f9677578..d9136cf6c7 100644 --- a/test/nvidia_gpu.c +++ b/test/nvidia_gpu.c @@ -21,11 +21,8 @@ #include "driver/nvidia_gpu.h" struct d_notify_policy d_notify_policies[] = { - AC_ATLEAST_W(100), - AC_ATLEAST_W(65), - AC_DC, - DC_ATLEAST_SOC(20), - DC_ATLEAST_SOC(5), + AC_ATLEAST_W(100), AC_ATLEAST_W(65), AC_DC, + DC_ATLEAST_SOC(20), DC_ATLEAST_SOC(5), }; extern enum d_notify_level d_notify_level; -- cgit v1.2.1 From 8dc256efde636444031763198eebc1c237b40941 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:08 -0600 Subject: board/drawcia/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I5dcfb3c1e34c451fadffd39f3664e96bf7601a5c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749377 Reviewed-by: Jeremy Bettis --- board/drawcia/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/drawcia/board.h b/board/drawcia/board.h index 7f00767a10..7055f25d0b 100644 --- a/board/drawcia/board.h +++ b/board/drawcia/board.h @@ -29,8 +29,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From 228b84712689b27fe41c16cfabb2e4ac79d60a50 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:51 -0600 Subject: board/agah/charger_isl9241.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I1e08b68ae741b82c3b5e499fc27787bed5f7262e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748790 Reviewed-by: Jeremy Bettis --- board/agah/charger_isl9241.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/board/agah/charger_isl9241.c b/board/agah/charger_isl9241.c index 1bc77c0ee4..298110ba16 100644 --- a/board/agah/charger_isl9241.c +++ b/board/agah/charger_isl9241.c @@ -98,7 +98,7 @@ static int board_disable_other_vbus_sink(int except_port) */ r = ppc_vbus_sink_enable(i, 0); if (r) - CPRINTS("Failed to disable sink path C%d (%d)", i, r); + CPRINTS("Failed to disable sink path C%d (%d)", i, r); rv |= r; } @@ -116,8 +116,8 @@ int board_set_active_charge_port(int port) enum charge_supplier active_supplier = charge_manager_get_supplier(); int active_port = charge_manager_get_active_charge_port(); - CPRINTS("Switching charger from P%d (supplier=%d) to P%d", - active_port, active_supplier, port); + CPRINTS("Switching charger from P%d (supplier=%d) to P%d", active_port, + active_supplier, port); if (port == CHARGE_PORT_NONE) { CPRINTS("Disabling all charger ports"); @@ -146,8 +146,8 @@ int board_set_active_charge_port(int port) * If we're running currently on a battery (active_supplier == NONE), we * don't need to throttle because we're not disabling any port. */ - if (chipset_in_state(CHIPSET_STATE_ON) - && active_supplier != CHARGE_SUPPLIER_NONE) + if (chipset_in_state(CHIPSET_STATE_ON) && + active_supplier != CHARGE_SUPPLIER_NONE) board_throttle_ap_gpu(); /* @@ -251,7 +251,6 @@ void ac_change(void) } DECLARE_HOOK(HOOK_AC_CHANGE, ac_change, HOOK_PRIO_DEFAULT); - static void power_supply_changed(void) { /* -- cgit v1.2.1 From 4c441cbcb0b41f5f40c2963c0190a04ad5299396 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:26 -0600 Subject: util/cbi-util.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: If8fff21754e7046030e2d04e45d75113cbc8acd3 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749522 Reviewed-by: Jeremy Bettis --- util/cbi-util.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/util/cbi-util.c b/util/cbi-util.c index 20268e43a4..219412ae2c 100644 --- a/util/cbi-util.c +++ b/util/cbi-util.c @@ -60,7 +60,7 @@ static const struct option opts_create[] = { { "pcb_supplier", 1, 0, OPT_PCB_SUPPLIER }, { "ssfc", 1, 0, OPT_SSFC }, { "rework_id", 1, 0, OPT_REWORK_ID }, - { "factory_calibration_data", 1, 0, OPT_FACTORY_CALIBRATION_DATA}, + { "factory_calibration_data", 1, 0, OPT_FACTORY_CALIBRATION_DATA }, { "size", 1, 0, OPT_SIZE }, { "erase_byte", 1, 0, OPT_ERASE_BYTE }, { NULL, 0, 0, 0 } @@ -72,9 +72,17 @@ static const struct option opts_show[] = { { "file", 1, 0, OPT_FILENAME }, static const char *field_name[] = { /* Same order as enum cbi_data_tag */ - "BOARD_VERSION", "OEM_ID", "SKU_ID", "DRAM_PART_NUM", - "OEM_NAME", "MODEL_ID", "FW_CONFIG", "PCB_SUPPLIER", - "SSFC", "REWORK_ID", "FACTORY_CALIBRATION_DATA", + "BOARD_VERSION", + "OEM_ID", + "SKU_ID", + "DRAM_PART_NUM", + "OEM_NAME", + "MODEL_ID", + "FW_CONFIG", + "PCB_SUPPLIER", + "SSFC", + "REWORK_ID", + "FACTORY_CALIBRATION_DATA", }; BUILD_ASSERT(ARRAY_SIZE(field_name) == CBI_TAG_COUNT); -- cgit v1.2.1 From 5966dc452610bfc2c0a4904a8c7ae15ee4decdb3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:42 -0600 Subject: board/agah/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iac748bce29287c39be5177597ec3cbd12113c97c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748789 Reviewed-by: Jeremy Bettis --- board/agah/board.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board/agah/board.c b/board/agah/board.c index f37e1e504f..b5c5a505eb 100644 --- a/board/agah/board.c +++ b/board/agah/board.c @@ -37,11 +37,8 @@ static int block_sequence; struct d_notify_policy d_notify_policies[] = { - AC_ATLEAST_W(100), - AC_ATLEAST_W(65), - AC_DC, - DC_ATLEAST_SOC(20), - DC_ATLEAST_SOC(5), + AC_ATLEAST_W(100), AC_ATLEAST_W(65), AC_DC, + DC_ATLEAST_SOC(20), DC_ATLEAST_SOC(5), }; BUILD_ASSERT(ARRAY_SIZE(d_notify_policies) == D_NOTIFY_COUNT); -- cgit v1.2.1 From 12c679e06c60df9ab87327bef5c800f219854f3f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:23 -0600 Subject: board/waddledoo2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I58e7c3c81184c42c60f87460cdd8e53351da5055 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749427 Reviewed-by: Jeremy Bettis --- board/waddledoo2/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/waddledoo2/board.h b/board/waddledoo2/board.h index e9627704de..ad6cda0491 100644 --- a/board/waddledoo2/board.h +++ b/board/waddledoo2/board.h @@ -24,8 +24,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP -- cgit v1.2.1 From 1efaa0779b8ded4d8d2de1fe542b93291ea22470 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:46:09 -0600 Subject: zephyr/test/drivers/src/test_rules.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ice4a661eb9e77cc1fd7b7db14417d2486c528d98 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749529 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/test_rules.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/zephyr/test/drivers/src/test_rules.c b/zephyr/test/drivers/src/test_rules.c index d46aa9900d..5125f50d58 100644 --- a/zephyr/test/drivers/src/test_rules.c +++ b/zephyr/test/drivers/src/test_rules.c @@ -20,15 +20,14 @@ static void motion_sense_fifo_reset_before(const struct ztest_unit_test *test, ZTEST_RULE(motion_sense_fifo_reset, motion_sense_fifo_reset_before, NULL); static void tcpci_revision_reset_before(const struct ztest_unit_test *test, - void *data) + void *data) { ARG_UNUSED(test); ARG_UNUSED(data); const struct emul *tcpci_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); const struct emul *ps8xxx_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(ps8xxx_emul))); - + emul_get_binding(DT_LABEL(DT_NODELABEL(ps8xxx_emul))); /* Set TCPCI to revision 2 for both emulators */ tcpc_config[USBC_PORT_C0].flags |= TCPC_FLAGS_TCPCI_REV2_0; -- cgit v1.2.1 From 6a49a6f258ffa1cce20e213663ef8081e7e918ac Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:18 -0600 Subject: chip/stm32/hwtimer32.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I085e9b74837d56664bccd0135cbea052ecce5d77 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749461 Reviewed-by: Jeremy Bettis --- chip/stm32/hwtimer32.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index d53021d6a9..4a263e72d9 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -285,11 +285,12 @@ void IRQ_HANDLER(IRQ_WD)(void) "pop {r0,pc}\n"); } const struct irq_priority __keep IRQ_PRIORITY(IRQ_WD) - __attribute__((section(".rodata.irqprio"))) = { IRQ_WD, - 0 }; /* put the watchdog - at the highest - priority - */ + __attribute__((section(".rodata.irqprio"))) = { + IRQ_WD, 0 + }; /* put the watchdog + at the highest + priority + */ void hwtimer_setup_watchdog(void) { -- cgit v1.2.1 From b2d37e1c0c097b86e118bb22c69a3d45be74f386 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:51 -0600 Subject: chip/max32660/tmr_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I85905dc45d29bf481827a4547e4bc492f9784004 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749434 Reviewed-by: Jeremy Bettis --- chip/max32660/tmr_regs.h | 112 ++++++++++++++++++++++++++--------------------- 1 file changed, 62 insertions(+), 50 deletions(-) diff --git a/chip/max32660/tmr_regs.h b/chip/max32660/tmr_regs.h index 8292d1f9e7..e0e9b9965c 100644 --- a/chip/max32660/tmr_regs.h +++ b/chip/max32660/tmr_regs.h @@ -90,39 +90,44 @@ typedef struct { ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ #define MXC_V_TMR_CN_TMODE_ONESHOT \ ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ -#define MXC_S_TMR_CN_TMODE_ONESHOT \ - (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_ONESHOT \ - Setting */ +#define MXC_S_TMR_CN_TMODE_ONESHOT \ + (MXC_V_TMR_CN_TMODE_ONESHOT \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_ONESHOT \ + Setting */ #define MXC_V_TMR_CN_TMODE_CONTINUOUS \ ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ -#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ - (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_CONTINUOUS \ - Setting \ - */ +#define MXC_S_TMR_CN_TMODE_CONTINUOUS \ + (MXC_V_TMR_CN_TMODE_CONTINUOUS \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CONTINUOUS \ + Setting \ + */ #define MXC_V_TMR_CN_TMODE_COUNTER \ ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ -#define MXC_S_TMR_CN_TMODE_COUNTER \ - (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_COUNTER \ - Setting */ +#define MXC_S_TMR_CN_TMODE_COUNTER \ + (MXC_V_TMR_CN_TMODE_COUNTER \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COUNTER \ + Setting */ #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ #define MXC_S_TMR_CN_TMODE_PWM \ (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM \ Setting */ #define MXC_V_TMR_CN_TMODE_CAPTURE \ ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURE \ - (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_CAPTURE \ - Setting */ +#define MXC_S_TMR_CN_TMODE_CAPTURE \ + (MXC_V_TMR_CN_TMODE_CAPTURE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURE \ + Setting */ #define MXC_V_TMR_CN_TMODE_COMPARE \ ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ -#define MXC_S_TMR_CN_TMODE_COMPARE \ - (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_COMPARE \ - Setting */ +#define MXC_S_TMR_CN_TMODE_COMPARE \ + (MXC_V_TMR_CN_TMODE_COMPARE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_COMPARE \ + Setting */ #define MXC_V_TMR_CN_TMODE_GATED \ ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value \ */ @@ -132,11 +137,12 @@ typedef struct { Setting */ #define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ - (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< \ - CN_TMODE_CAPTURECOMPARE \ - Setting \ - */ +#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE \ + (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE \ + << MXC_F_TMR_CN_TMODE_POS) /**< \ + CN_TMODE_CAPTURECOMPARE \ + Setting \ + */ #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ #define MXC_F_TMR_CN_PRES \ @@ -182,16 +188,18 @@ typedef struct { ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ #define MXC_V_TMR_CN_TPOL_ACTIVEHI \ ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ - (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< \ - CN_TPOL_ACTIVEHI \ - Setting */ +#define MXC_S_TMR_CN_TPOL_ACTIVEHI \ + (MXC_V_TMR_CN_TPOL_ACTIVEHI \ + << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVEHI \ + Setting */ #define MXC_V_TMR_CN_TPOL_ACTIVELO \ ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ -#define MXC_S_TMR_CN_TPOL_ACTIVELO \ - (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< \ - CN_TPOL_ACTIVELO \ - Setting */ +#define MXC_S_TMR_CN_TPOL_ACTIVELO \ + (MXC_V_TMR_CN_TPOL_ACTIVELO \ + << MXC_F_TMR_CN_TPOL_POS) /**< \ + CN_TPOL_ACTIVELO \ + Setting */ #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ #define MXC_F_TMR_CN_TEN \ @@ -216,10 +224,11 @@ typedef struct { #define MXC_V_TMR_CN_PWMSYNC_DIS \ ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value \ */ -#define MXC_S_TMR_CN_PWMSYNC_DIS \ - (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ - CN_PWMSYNC_DIS \ - Setting */ +#define MXC_S_TMR_CN_PWMSYNC_DIS \ + (MXC_V_TMR_CN_PWMSYNC_DIS \ + << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ + CN_PWMSYNC_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ #define MXC_S_TMR_CN_PWMSYNC_EN \ (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< \ @@ -233,10 +242,11 @@ typedef struct { #define MXC_V_TMR_CN_NOLHPOL_DIS \ ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLHPOL_DIS \ - (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ - CN_NOLHPOL_DIS \ - Setting */ +#define MXC_S_TMR_CN_NOLHPOL_DIS \ + (MXC_V_TMR_CN_NOLHPOL_DIS \ + << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ + CN_NOLHPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ #define MXC_S_TMR_CN_NOLHPOL_EN \ (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< \ @@ -250,10 +260,11 @@ typedef struct { #define MXC_V_TMR_CN_NOLLPOL_DIS \ ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value \ */ -#define MXC_S_TMR_CN_NOLLPOL_DIS \ - (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ - CN_NOLLPOL_DIS \ - Setting */ +#define MXC_S_TMR_CN_NOLLPOL_DIS \ + (MXC_V_TMR_CN_NOLLPOL_DIS \ + << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ + CN_NOLLPOL_DIS \ + Setting */ #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ #define MXC_S_TMR_CN_NOLLPOL_EN \ (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< \ @@ -267,10 +278,11 @@ typedef struct { #define MXC_V_TMR_CN_PWMCKBD_DIS \ ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value \ */ -#define MXC_S_TMR_CN_PWMCKBD_DIS \ - (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ - CN_PWMCKBD_DIS \ - Setting */ +#define MXC_S_TMR_CN_PWMCKBD_DIS \ + (MXC_V_TMR_CN_PWMCKBD_DIS \ + << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ + CN_PWMCKBD_DIS \ + Setting */ #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ #define MXC_S_TMR_CN_PWMCKBD_EN \ (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< \ -- cgit v1.2.1 From f0dbd4e8aecd37621ff2371cdef6555365ac974b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:37 -0600 Subject: baseboard/volteer/cbi_ssfc.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I575c35d60abecda9d9094466a035c0f4cbacaab7 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748788 Reviewed-by: Jeremy Bettis --- baseboard/volteer/cbi_ssfc.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h index a9f39e17b0..125ecbcd0d 100644 --- a/baseboard/volteer/cbi_ssfc.h +++ b/baseboard/volteer/cbi_ssfc.h @@ -43,10 +43,7 @@ enum ec_ssfc_lightbar { /* * Keyboard Type (Bit 11) */ -enum ec_ssfc_keyboard { - SSFC_KEYBOARD_DEFAULT = 0, - SSFC_KEYBOARD_GAMING = 1 -}; +enum ec_ssfc_keyboard { SSFC_KEYBOARD_DEFAULT = 0, SSFC_KEYBOARD_GAMING = 1 }; union volteer_cbi_ssfc { struct { -- cgit v1.2.1 From 9ef29b0097a4a21df6da2f04efb2e1783879a06d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:42 -0600 Subject: zephyr/emul/tcpc/emul_ps8xxx.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iea81aa4f4291eeb7489de760b2384102e3ed9df5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749525 Reviewed-by: Jeremy Bettis --- zephyr/emul/tcpc/emul_ps8xxx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c index 5fe8828e31..43e7c2fdd7 100644 --- a/zephyr/emul/tcpc/emul_ps8xxx.c +++ b/zephyr/emul/tcpc/emul_ps8xxx.c @@ -579,8 +579,8 @@ static int ps8xxx_emul_init(const struct emul *emul, .write_byte = ps8xxx_emul_write_byte, \ .read_byte = ps8xxx_emul_read_byte, \ }, \ - }; \ - \ + }; \ + \ static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = { \ .p0_cfg = { \ .i2c_label = DT_INST_BUS_LABEL(n), \ @@ -600,8 +600,8 @@ static int ps8xxx_emul_init(const struct emul *emul, .data = &ps8xxx_emul_data_##n.gpio_data, \ .addr = DT_INST_PROP(n, gpio_i2c_addr), \ }, \ - }; \ - TCPCI_EMUL_DEFINE(n, ps8xxx_emul_init, &ps8xxx_emul_cfg_##n, \ + }; \ + TCPCI_EMUL_DEFINE(n, ps8xxx_emul_init, &ps8xxx_emul_cfg_##n, \ &ps8xxx_emul_data_##n) DT_INST_FOREACH_STATUS_OKAY(PS8XXX_EMUL) -- cgit v1.2.1 From 44a8304de10627ac977d8d56bdfe407caf0dc689 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:52 -0600 Subject: board/delbin/keyboard_customization.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I5dd7a7e8860fcf07e1d2994cfb439a31d5dd8765 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748801 Reviewed-by: Jeremy Bettis --- board/delbin/keyboard_customization.c | 72 +++++++++++++++++------------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/board/delbin/keyboard_customization.c b/board/delbin/keyboard_customization.c index 0ccda5ce70..1f6c71e4e9 100644 --- a/board/delbin/keyboard_customization.c +++ b/board/delbin/keyboard_customization.c @@ -16,59 +16,59 @@ static uint16_t (*scancode_set2)[KEYBOARD_ROWS]; static uint16_t KB2scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000}, - {0x0000, 0x0076, 0x0000, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016}, - {0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a}, - {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d}, - {0xe01f, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d}, - {0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043}, - {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c}, - {0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059}, - {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d}, - {0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a}, - {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, - {0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066}, - {0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d}, - {0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021}, - {0x0023, 0x005a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007D, 0x0069}, + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0x0000, 0x0000, 0x0000 }, + { 0x0000, 0x0076, 0x0000, 0x000e, 0x001c, 0x003a, 0x000d, 0x0016 }, + { 0x006c, 0x000c, 0x0004, 0x0006, 0x0005, 0xe071, 0x0026, 0x002a }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x0029, 0x0025, 0x002d }, + { 0xe01f, 0x0009, 0x0083, 0x000b, 0x0003, 0x0041, 0x001e, 0x001d }, + { 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0022, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x001b, 0x003d, 0x003c }, + { 0x0000, 0x0012, 0x0061, 0x0000, 0x0000, 0x0000, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x0024, 0x0044, 0x004d }, + { 0x0045, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x001a }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, + { 0xe07a, 0x005d, 0xe075, 0x006b, 0x005a, 0xe072, 0x004a, 0x0066 }, + { 0xe06b, 0xe074, 0xe069, 0x0067, 0xe06c, 0x0064, 0x0015, 0xe07d }, + { 0x0073, 0x007c, 0x007b, 0x0074, 0x0071, 0xe04a, 0x0070, 0x0021 }, + { 0x0023, 0x005a, 0x0075, 0x0079, 0x007a, 0x0072, 0x007D, 0x0069 }, }; /* The standard Chrome OS keyboard matrix table in scan code set 2. */ static uint16_t KB1scancode_set2[KEYBOARD_COLS_MAX][KEYBOARD_ROWS] = { - {0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000}, - {0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015}, - {0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024}, - {0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d}, - {0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d}, - {0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043}, - {0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c}, - {0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059}, - {0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d}, - {0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044}, - {0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000}, + { 0x0000, 0x0000, 0x0014, 0xe01f, 0xe014, 0xe007, 0x0000, 0x0000 }, + { 0xe01f, 0x0076, 0x000d, 0x000e, 0x001c, 0x001a, 0x0016, 0x0015 }, + { 0x0005, 0x000c, 0x0004, 0x0006, 0x0023, 0x0021, 0x0026, 0x0024 }, + { 0x0032, 0x0034, 0x002c, 0x002e, 0x002b, 0x002a, 0x0025, 0x002d }, + { 0x0009, 0x0083, 0x000b, 0x0003, 0x001b, 0x0022, 0x001e, 0x001d }, + { 0x0051, 0x0000, 0x005b, 0x0000, 0x0042, 0x0041, 0x003e, 0x0043 }, + { 0x0031, 0x0033, 0x0035, 0x0036, 0x003b, 0x003a, 0x003d, 0x003c }, + { 0x0000, 0x0000, 0x0061, 0x0000, 0x0000, 0x0012, 0x0000, 0x0059 }, + { 0x0055, 0x0052, 0x0054, 0x004e, 0x004c, 0x004a, 0x0045, 0x004d }, + { 0x0000, 0x0001, 0x000a, 0x002f, 0x004b, 0x0049, 0x0046, 0x0044 }, + { 0xe011, 0x0000, 0x006a, 0x0000, 0x005d, 0x0000, 0x0011, 0x0000 }, #ifndef CONFIG_KEYBOARD_KEYPAD - {0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, - {0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b}, + { 0x0000, 0x0066, 0x0000, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 }, + { 0x0000, 0x0064, 0x0000, 0x0067, 0x0000, 0x0000, 0xe074, 0xe06b }, #else - {0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075}, - {0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b}, - {0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070}, - {0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a}, + { 0x0000, 0x0066, 0xe071, 0x005d, 0x005a, 0x0029, 0xe072, 0xe075 }, + { 0xe06c, 0x0064, 0xe07d, 0x0067, 0xe069, 0xe07a, 0xe074, 0xe06b }, + { 0xe04a, 0x007c, 0x007b, 0x0074, 0x0071, 0x0073, 0x006b, 0x0070 }, + { 0x006c, 0x0075, 0x007d, 0x0079, 0x007a, 0x0072, 0x0069, 0xe05a }, #endif }; uint16_t get_scancode_set2(uint8_t row, uint8_t col) { - if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { - return *(*(scancode_set2 + col)+row); + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { + return *(*(scancode_set2 + col) + row); } return 0; } void set_scancode_set2(uint8_t row, uint8_t col, uint16_t val) { - if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { - *(*(scancode_set2 + col)+row) = val; + if (col < KEYBOARD_COLS_MAX && row < KEYBOARD_ROWS) { + *(*(scancode_set2 + col) + row) = val; } } -- cgit v1.2.1 From a75640a1b293e149438d342cfde36bdb4ec0094c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:59 -0600 Subject: board/beadrix/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: If53dc2662c215f19e841c700f8160eb2e7dd2f44 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748791 Reviewed-by: Jeremy Bettis --- board/beadrix/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/beadrix/board.h b/board/beadrix/board.h index 215bc6fff1..113c730de7 100644 --- a/board/beadrix/board.h +++ b/board/beadrix/board.h @@ -32,8 +32,9 @@ #define CONFIG_CHARGE_RAMP_HW #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ /* * GPIO for C1 interrupts, for baseboard use -- cgit v1.2.1 From e85b6009b13599d8efcde28afe69905f4aa87355 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:46 -0600 Subject: board/pirika/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I27122fc916b9ffef9fa7a0e07c2ae8ccc7686e58 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749417 Reviewed-by: Jeremy Bettis --- board/pirika/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/pirika/board.h b/board/pirika/board.h index d25bb17f33..066bd05cbb 100644 --- a/board/pirika/board.h +++ b/board/pirika/board.h @@ -30,8 +30,9 @@ #define CONFIG_CHARGER_SENSE_RESISTOR 10 #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) -- cgit v1.2.1 From 3873a070b476019794df40ad4b74720bbe2e7509 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:28 -0600 Subject: board/moli/thermal.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Id83d44c4f7afb9bbe72aac5d8c278b2f98c4721f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749394 Reviewed-by: Jeremy Bettis --- board/moli/thermal.c | 50 ++++++++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/board/moli/thermal.c b/board/moli/thermal.c index 67c112e3a8..b7a56095dc 100644 --- a/board/moli/thermal.c +++ b/board/moli/thermal.c @@ -14,7 +14,7 @@ #include "util.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_THERMAL, outstr) -#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ## args) +#define CPRINTS(format, args...) cprints(CC_THERMAL, format, ##args) struct fan_step { /* @@ -34,39 +34,39 @@ struct fan_step { static const struct fan_step fan_table[] = { { /* level 0 */ - .on = {-1, 47, -1}, - .off = {-1, 0, -1}, - .rpm = {1900}, + .on = { -1, 47, -1 }, + .off = { -1, 0, -1 }, + .rpm = { 1900 }, }, { /* level 1 */ - .on = {-1, 50, -1}, - .off = {-1, 47, -1}, - .rpm = {2500}, + .on = { -1, 50, -1 }, + .off = { -1, 47, -1 }, + .rpm = { 2500 }, }, { /* level 2 */ - .on = {-1, 60, -1}, - .off = {-1, 57, -1}, - .rpm = {3000}, + .on = { -1, 60, -1 }, + .off = { -1, 57, -1 }, + .rpm = { 3000 }, }, { /* level 3 */ - .on = {-1, 70, -1}, - .off = {-1, 67, -1}, - .rpm = {3500}, + .on = { -1, 70, -1 }, + .off = { -1, 67, -1 }, + .rpm = { 3500 }, }, { /* level 4 */ - .on = {-1, 80, -1}, - .off = {-1, 77, -1}, - .rpm = {4000}, + .on = { -1, 80, -1 }, + .off = { -1, 77, -1 }, + .rpm = { 4000 }, }, { /* level 5 */ - .on = {-1, 90, -1}, - .off = {-1, 87, -1}, - .rpm = {4500}, + .on = { -1, 90, -1 }, + .off = { -1, 87, -1 }, + .rpm = { 4500 }, }, }; const int num_fan_levels = ARRAY_SIZE(fan_table); @@ -91,17 +91,14 @@ int fan_table_to_rpm(int fan, int *temp, enum temp_sensor_id temp_sensor) */ if (temp[temp_sensor] < prev_temp[temp_sensor]) { for (i = current_level; i > 0; i--) { - if (temp[temp_sensor] < - fan_table[i].off[temp_sensor]) + if (temp[temp_sensor] < fan_table[i].off[temp_sensor]) current_level = i - 1; else break; } - } else if (temp[temp_sensor] > - prev_temp[temp_sensor]) { + } else if (temp[temp_sensor] > prev_temp[temp_sensor]) { for (i = current_level; i < num_fan_levels; i++) { - if (temp[temp_sensor] >= - fan_table[i].on[temp_sensor]) + if (temp[temp_sensor] >= fan_table[i].on[temp_sensor]) current_level = i; else break; @@ -136,7 +133,8 @@ void board_override_fan_control(int fan, int *temp) if (chipset_in_state(CHIPSET_STATE_ON)) { fan_set_rpm_mode(FAN_CH(fan), 1); fan_set_rpm_target(FAN_CH(fan), - fan_table_to_rpm(FAN_CH(fan), temp, TEMP_SENSOR_2_CPU_VR)); + fan_table_to_rpm(FAN_CH(fan), temp, + TEMP_SENSOR_2_CPU_VR)); } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { /* Stop fan when enter S0ix */ fan_set_rpm_mode(FAN_CH(fan), 1); -- cgit v1.2.1 From 4b39e50aafd6896f041ef04667a7d2fec0076d31 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:34 -0600 Subject: chip/max32660/flc_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic1a8f9d3a3a03e274d2bc88c402fc30f103ee59e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749430 Reviewed-by: Jeremy Bettis --- chip/max32660/flc_regs.h | 91 ++++++++++++++++++++++++++---------------------- 1 file changed, 50 insertions(+), 41 deletions(-) diff --git a/chip/max32660/flc_regs.h b/chip/max32660/flc_regs.h index 54ce7ff0bd..5603d55d5a 100644 --- a/chip/max32660/flc_regs.h +++ b/chip/max32660/flc_regs.h @@ -124,10 +124,11 @@ typedef struct { ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ #define MXC_V_FLC_CN_WDTH_SIZE128 \ ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ -#define MXC_S_FLC_CN_WDTH_SIZE128 \ - (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< \ - CN_WDTH_SIZE128 \ - Setting */ +#define MXC_S_FLC_CN_WDTH_SIZE128 \ + (MXC_V_FLC_CN_WDTH_SIZE128 \ + << MXC_F_FLC_CN_WDTH_POS) /**< \ + CN_WDTH_SIZE128 \ + Setting */ #define MXC_V_FLC_CN_WDTH_SIZE32 \ ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value \ */ @@ -142,11 +143,12 @@ typedef struct { Mask */ #define MXC_V_FLC_CN_ERASE_CODE_NOP \ ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ -#define MXC_S_FLC_CN_ERASE_CODE_NOP \ - (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< \ - CN_ERASE_CODE_NOP \ - Setting \ - */ +#define MXC_S_FLC_CN_ERASE_CODE_NOP \ + (MXC_V_FLC_CN_ERASE_CODE_NOP \ + << MXC_F_FLC_CN_ERASE_CODE_POS) /**< \ + CN_ERASE_CODE_NOP \ + Setting \ + */ #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE \ ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE \ @@ -189,10 +191,11 @@ typedef struct { ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ #define MXC_V_FLC_CN_BRST_DISABLE \ ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ -#define MXC_S_FLC_CN_BRST_DISABLE \ - (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< \ - CN_BRST_DISABLE \ - Setting */ +#define MXC_S_FLC_CN_BRST_DISABLE \ + (MXC_V_FLC_CN_BRST_DISABLE \ + << MXC_F_FLC_CN_BRST_POS) /**< \ + CN_BRST_DISABLE \ + Setting */ #define MXC_V_FLC_CN_BRST_ENABLE \ ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value \ */ @@ -206,11 +209,12 @@ typedef struct { ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ #define MXC_V_FLC_CN_UNLOCK_UNLOCKED \ ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ -#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ - (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< \ - CN_UNLOCK_UNLOCKED \ - Setting \ - */ +#define MXC_S_FLC_CN_UNLOCK_UNLOCKED \ + (MXC_V_FLC_CN_UNLOCK_UNLOCKED \ + << MXC_F_FLC_CN_UNLOCK_POS) /**< \ + CN_UNLOCK_UNLOCKED \ + Setting \ + */ /** * Flash Interrupt Register. @@ -220,27 +224,30 @@ typedef struct { ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ #define MXC_V_FLC_INTR_DONE_INACTIVE \ ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ -#define MXC_S_FLC_INTR_DONE_INACTIVE \ - (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< \ - INTR_DONE_INACTIVE \ - Setting \ - */ +#define MXC_S_FLC_INTR_DONE_INACTIVE \ + (MXC_V_FLC_INTR_DONE_INACTIVE \ + << MXC_F_FLC_INTR_DONE_POS) /**< \ + INTR_DONE_INACTIVE \ + Setting \ + */ #define MXC_V_FLC_INTR_DONE_PENDING \ ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ -#define MXC_S_FLC_INTR_DONE_PENDING \ - (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< \ - INTR_DONE_PENDING \ - Setting */ +#define MXC_S_FLC_INTR_DONE_PENDING \ + (MXC_V_FLC_INTR_DONE_PENDING \ + << MXC_F_FLC_INTR_DONE_POS) /**< \ + INTR_DONE_PENDING \ + Setting */ #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ #define MXC_F_FLC_INTR_AF \ ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ #define MXC_V_FLC_INTR_AF_NOERROR \ ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ -#define MXC_S_FLC_INTR_AF_NOERROR \ - (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< \ - INTR_AF_NOERROR \ - Setting */ +#define MXC_S_FLC_INTR_AF_NOERROR \ + (MXC_V_FLC_INTR_AF_NOERROR \ + << MXC_F_FLC_INTR_AF_POS) /**< \ + INTR_AF_NOERROR \ + Setting */ #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ #define MXC_S_FLC_INTR_AF_ERROR \ (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR \ @@ -252,18 +259,20 @@ typedef struct { */ #define MXC_V_FLC_INTR_DONEIE_DISABLE \ ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_DISABLE \ - (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< \ - INTR_DONEIE_DISABLE \ - Setting \ - */ +#define MXC_S_FLC_INTR_DONEIE_DISABLE \ + (MXC_V_FLC_INTR_DONEIE_DISABLE \ + << MXC_F_FLC_INTR_DONEIE_POS) /**< \ + INTR_DONEIE_DISABLE \ + Setting \ + */ #define MXC_V_FLC_INTR_DONEIE_ENABLE \ ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ -#define MXC_S_FLC_INTR_DONEIE_ENABLE \ - (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< \ - INTR_DONEIE_ENABLE \ - Setting \ - */ +#define MXC_S_FLC_INTR_DONEIE_ENABLE \ + (MXC_V_FLC_INTR_DONEIE_ENABLE \ + << MXC_F_FLC_INTR_DONEIE_POS) /**< \ + INTR_DONEIE_ENABLE \ + Setting \ + */ #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ #define MXC_F_FLC_INTR_AFIE \ -- cgit v1.2.1 From d6190d3bb049ab4ebae9a6a5255117a366a743bf Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:50 -0600 Subject: board/sasuke/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I65855a13c9043d68164ecacd174813c2ea8f3412 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749418 Reviewed-by: Jeremy Bettis --- board/sasuke/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/sasuke/board.h b/board/sasuke/board.h index 600c016c95..c3b12d6513 100644 --- a/board/sasuke/board.h +++ b/board/sasuke/board.h @@ -25,8 +25,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #define CONFIG_CHARGER_PROFILE_OVERRIDE #define CONFIG_CHARGE_RAMP_HW -- cgit v1.2.1 From d5f54cb45d0019f9d9931c9ba3f00f78d6b52566 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:55 -0600 Subject: board/delbin/keyboard_customization.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I1872592629daf562c9932b9f47224e1178c4011e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748802 Reviewed-by: Jeremy Bettis --- board/delbin/keyboard_customization.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/delbin/keyboard_customization.h b/board/delbin/keyboard_customization.h index 3c26193f9f..71d4a54ceb 100644 --- a/board/delbin/keyboard_customization.h +++ b/board/delbin/keyboard_customization.h @@ -94,8 +94,8 @@ extern uint8_t keyboard_cols; #define KEYBOARD2_COL_LEFT_ALT 10 #define KEYBOARD2_ROW_LEFT_ALT 6 #define KEYBOARD2_MASK_LEFT_ALT KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_LEFT_ALT) -#define KEYBOARD2_COL_REFRESH 2 -#define KEYBOARD2_ROW_REFRESH 3 +#define KEYBOARD2_COL_REFRESH 2 +#define KEYBOARD2_ROW_REFRESH 3 #define KEYBOARD2_MASK_REFRESH KEYBOARD_ROW_TO_MASK(KEYBOARD2_ROW_REFRESH) #define KEYBOARD2_COL_RIGHT_ALT 10 #define KEYBOARD2_ROW_RIGHT_ALT 0 -- cgit v1.2.1 From 1d52e542f10884962f238080eaf227c6e7278078 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:24 -0600 Subject: board/gooey/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ifebf7156ea750e68c0dd65d9b409a2b13ded96fb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749380 Reviewed-by: Jeremy Bettis --- board/gooey/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/gooey/board.h b/board/gooey/board.h index 417a5f6313..dd44c41491 100644 --- a/board/gooey/board.h +++ b/board/gooey/board.h @@ -26,8 +26,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) -- cgit v1.2.1 From 6f02a2dcc9b8443b4a48022e605f191939d3e25d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:43 -0600 Subject: chip/stm32/usart-stm32l5.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I5d2cc33dd442535ebf84e316993c4bd6b67950ed Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749464 Reviewed-by: Jeremy Bettis --- chip/stm32/usart-stm32l5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/chip/stm32/usart-stm32l5.c b/chip/stm32/usart-stm32l5.c index 3a8db09202..73f0c3c3cb 100644 --- a/chip/stm32/usart-stm32l5.c +++ b/chip/stm32/usart-stm32l5.c @@ -169,12 +169,12 @@ DECLARE_IRQ(STM32_IRQ_USART5, usart5_interrupt, 2); #if defined(CONFIG_STREAM_USART9) struct usart_hw_config const usart9_hw = { - .index = 5, - .base = STM32_USART9_BASE, - .irq = STM32_IRQ_USART9, + .index = 5, + .base = STM32_USART9_BASE, + .irq = STM32_IRQ_USART9, .clock_register = &STM32_RCC_APB1ENR2, - .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, - .ops = &usart_variant_hw_ops, + .clock_enable = STM32_RCC_APB1ENR2_LPUART1EN, + .ops = &usart_variant_hw_ops, }; static void usart9_interrupt(void) -- cgit v1.2.1 From 136fc6df19de668bc59f683fa41f5b13dbe03012 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:25 -0600 Subject: board/meep/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I81e6c50362382684ad1dffe6059a69a0b58f9012 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749393 Reviewed-by: Jeremy Bettis --- board/meep/board.h | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/board/meep/board.h b/board/meep/board.h index 008592c7f1..9418499efb 100644 --- a/board/meep/board.h +++ b/board/meep/board.h @@ -22,8 +22,8 @@ #define CONFIG_LED_COMMON /* Sensors */ -#define CONFIG_ACCEL_KX022 /* Lid accel */ -#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ +#define CONFIG_ACCEL_KX022 /* Lid accel */ +#define CONFIG_ACCELGYRO_LSM6DSM /* Base accel */ /* Sensors without hardware FIFO are in forced mode */ #define CONFIG_ACCEL_FORCE_MODE_MASK BIT(LID_ACCEL) @@ -66,10 +66,10 @@ #include "registers.h" enum adc_channel { - ADC_TEMP_SENSOR_AMB, /* ADC0 */ - ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ - ADC_VBUS_C0, /* ADC9 */ - ADC_VBUS_C1, /* ADC4 */ + ADC_TEMP_SENSOR_AMB, /* ADC0 */ + ADC_TEMP_SENSOR_CHARGER, /* ADC1 */ + ADC_VBUS_C0, /* ADC9 */ + ADC_VBUS_C1, /* ADC4 */ ADC_CH_COUNT }; @@ -80,18 +80,10 @@ enum temp_sensor_id { TEMP_SENSOR_COUNT }; -enum pwm_channel { - PWM_CH_KBLIGHT, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_KBLIGHT, PWM_CH_COUNT }; /* Motion sensors */ -enum sensor_id { - LID_ACCEL, - BASE_ACCEL, - BASE_GYRO, - SENSOR_COUNT -}; +enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT }; enum battery_type { BATTERY_DYNAPACK_COS, -- cgit v1.2.1 From 3ac50be6533db4ceb889c88a71ed38453f34e6d1 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:39 -0600 Subject: board/hyperdebug/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I413665c00996b674f0e837821fd76cbfe3194860 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749384 Reviewed-by: Jeremy Bettis --- board/hyperdebug/board.c | 177 ++++++++++++++++++----------------------------- 1 file changed, 69 insertions(+), 108 deletions(-) diff --git a/board/hyperdebug/board.c b/board/hyperdebug/board.c index ab822fc054..746a84aa7e 100644 --- a/board/hyperdebug/board.c +++ b/board/hyperdebug/board.c @@ -30,8 +30,8 @@ void board_config_pre_init(void) * Forward UARTs as a USB serial interface. */ -#define USB_STREAM_RX_SIZE 16 -#define USB_STREAM_TX_SIZE 16 +#define USB_STREAM_RX_SIZE 16 +#define USB_STREAM_TX_SIZE 16 /****************************************************************************** * Forward USART1 as a simple USB serial interface. @@ -40,28 +40,19 @@ void board_config_pre_init(void) static struct usart_config const usart1; struct usb_stream_config const usart1_usb; -static struct queue const usart1_to_usb = QUEUE_DIRECT(64, uint8_t, - usart1.producer, usart1_usb.consumer); -static struct queue const usb_to_usart1 = QUEUE_DIRECT(64, uint8_t, - usart1_usb.producer, usart1.consumer); +static struct queue const usart1_to_usb = + QUEUE_DIRECT(64, uint8_t, usart1.producer, usart1_usb.consumer); +static struct queue const usb_to_usart1 = + QUEUE_DIRECT(64, uint8_t, usart1_usb.producer, usart1.consumer); static struct usart_config const usart1 = - USART_CONFIG(usart1_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart1_to_usb, - usb_to_usart1); - -USB_STREAM_CONFIG(usart1_usb, - USB_IFACE_USART1_STREAM, - USB_STR_USART1_STREAM_NAME, - USB_EP_USART1_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart1, - usart1_to_usb) + USART_CONFIG(usart1_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart1_to_usb, usb_to_usart1); + +USB_STREAM_CONFIG(usart1_usb, USB_IFACE_USART1_STREAM, + USB_STR_USART1_STREAM_NAME, USB_EP_USART1_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart1, + usart1_to_usb) /****************************************************************************** * Forward USART2 as a simple USB serial interface. @@ -70,28 +61,19 @@ USB_STREAM_CONFIG(usart1_usb, static struct usart_config const usart2; struct usb_stream_config const usart2_usb; -static struct queue const usart2_to_usb = QUEUE_DIRECT(64, uint8_t, - usart2.producer, usart2_usb.consumer); -static struct queue const usb_to_usart2 = QUEUE_DIRECT(64, uint8_t, - usart2_usb.producer, usart2.consumer); +static struct queue const usart2_to_usb = + QUEUE_DIRECT(64, uint8_t, usart2.producer, usart2_usb.consumer); +static struct queue const usb_to_usart2 = + QUEUE_DIRECT(64, uint8_t, usart2_usb.producer, usart2.consumer); static struct usart_config const usart2 = - USART_CONFIG(usart2_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart2_to_usb, - usb_to_usart2); - -USB_STREAM_CONFIG(usart2_usb, - USB_IFACE_USART2_STREAM, - USB_STR_USART2_STREAM_NAME, - USB_EP_USART2_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart2, - usart2_to_usb) + USART_CONFIG(usart2_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart2_to_usb, usb_to_usart2); + +USB_STREAM_CONFIG(usart2_usb, USB_IFACE_USART2_STREAM, + USB_STR_USART2_STREAM_NAME, USB_EP_USART2_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart2, + usart2_to_usb) /****************************************************************************** * Forward USART4 as a simple USB serial interface. @@ -100,28 +82,19 @@ USB_STREAM_CONFIG(usart2_usb, static struct usart_config const usart4; struct usb_stream_config const usart4_usb; -static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t, - usart4.producer, usart4_usb.consumer); -static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t, - usart4_usb.producer, usart4.consumer); +static struct queue const usart4_to_usb = + QUEUE_DIRECT(64, uint8_t, usart4.producer, usart4_usb.consumer); +static struct queue const usb_to_usart4 = + QUEUE_DIRECT(64, uint8_t, usart4_usb.producer, usart4.consumer); static struct usart_config const usart4 = - USART_CONFIG(usart4_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart4_to_usb, - usb_to_usart4); - -USB_STREAM_CONFIG(usart4_usb, - USB_IFACE_USART4_STREAM, - USB_STR_USART4_STREAM_NAME, - USB_EP_USART4_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart4, - usart4_to_usb) + USART_CONFIG(usart4_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart4_to_usb, usb_to_usart4); + +USB_STREAM_CONFIG(usart4_usb, USB_IFACE_USART4_STREAM, + USB_STR_USART4_STREAM_NAME, USB_EP_USART4_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart4, + usart4_to_usb) /****************************************************************************** * Forward LPUART (USART9) as a simple USB serial interface. @@ -130,28 +103,19 @@ USB_STREAM_CONFIG(usart4_usb, static struct usart_config const usart9; struct usb_stream_config const usart9_usb; -static struct queue const usart9_to_usb = QUEUE_DIRECT(64, uint8_t, - usart9.producer, usart9_usb.consumer); -static struct queue const usb_to_usart9 = QUEUE_DIRECT(64, uint8_t, - usart9_usb.producer, usart9.consumer); +static struct queue const usart9_to_usb = + QUEUE_DIRECT(64, uint8_t, usart9.producer, usart9_usb.consumer); +static struct queue const usb_to_usart9 = + QUEUE_DIRECT(64, uint8_t, usart9_usb.producer, usart9.consumer); static struct usart_config const usart9 = - USART_CONFIG(usart9_hw, - usart_rx_interrupt, - usart_tx_interrupt, - 115200, - 0, - usart9_to_usb, - usb_to_usart9); - -USB_STREAM_CONFIG(usart9_usb, - USB_IFACE_USART9_STREAM, - USB_STR_USART9_STREAM_NAME, - USB_EP_USART9_STREAM, - USB_STREAM_RX_SIZE, - USB_STREAM_TX_SIZE, - usb_to_usart9, - usart9_to_usb) + USART_CONFIG(usart9_hw, usart_rx_interrupt, usart_tx_interrupt, 115200, + 0, usart9_to_usb, usb_to_usart9); + +USB_STREAM_CONFIG(usart9_usb, USB_IFACE_USART9_STREAM, + USB_STR_USART9_STREAM_NAME, USB_EP_USART9_STREAM, + USB_STREAM_RX_SIZE, USB_STREAM_TX_SIZE, usb_to_usart9, + usart9_to_usb) /****************************************************************************** * Support SPI bridging over USB, this requires usb_spi_board_enable and @@ -160,7 +124,7 @@ USB_STREAM_CONFIG(usart9_usb, /* SPI devices */ const struct spi_device_t spi_devices[] = { - { 1 /* SPI2 */, 7, GPIO_SPI2_CS}, + { 1 /* SPI2 */, 7, GPIO_SPI2_CS }, }; const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); @@ -204,35 +168,36 @@ USB_SPI_CONFIG(usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0); /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "controller", - .port = I2C_PORT_CONTROLLER, - .kbps = 100, - .scl = GPIO_TPM_I2C1_HOST_SCL, - .sda = GPIO_TPM_I2C1_HOST_SDA - }, + { .name = "controller", + .port = I2C_PORT_CONTROLLER, + .kbps = 100, + .scl = GPIO_TPM_I2C1_HOST_SCL, + .sda = GPIO_TPM_I2C1_HOST_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); -int usb_i2c_board_is_enabled(void) { return 1; } +int usb_i2c_board_is_enabled(void) +{ + return 1; +} /****************************************************************************** * Define the strings used in our USB descriptors. */ const void *const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("HyperDebug"), - [USB_STR_SERIALNO] = 0, - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), + [USB_STR_DESC] = usb_string_desc, + [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), + [USB_STR_PRODUCT] = USB_STRING_DESC("HyperDebug"), + [USB_STR_SERIALNO] = 0, + [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("HyperDebug Shell"), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), - [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("UART1"), - [USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("UART2"), - [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART4"), - [USB_STR_USART9_STREAM_NAME] = USB_STRING_DESC("UART9"), + [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), + [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), + [USB_STR_USART1_STREAM_NAME] = USB_STRING_DESC("UART1"), + [USB_STR_USART2_STREAM_NAME] = USB_STRING_DESC("UART2"), + [USB_STR_USART4_STREAM_NAME] = USB_STRING_DESC("UART4"), + [USB_STR_USART9_STREAM_NAME] = USB_STRING_DESC("UART9"), }; BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); @@ -327,9 +292,7 @@ static int command_gpio_mode(int argc, char **argv) } DECLARE_CONSOLE_COMMAND_FLAGS(gpiomode, command_gpio_mode, "name ", - "Set a GPIO mode", - CMD_FLAG_RESTRICTED -); + "Set a GPIO mode", CMD_FLAG_RESTRICTED); /* * Set the weak pulling of a GPIO pin: up/down/none. @@ -363,6 +326,4 @@ static int command_gpio_pull_mode(int argc, char **argv) } DECLARE_CONSOLE_COMMAND_FLAGS(gpiopullmode, command_gpio_pull_mode, "name ", - "Set a GPIO weak pull mode", - CMD_FLAG_RESTRICTED -); + "Set a GPIO weak pull mode", CMD_FLAG_RESTRICTED); -- cgit v1.2.1 From c2de76236f16fe2cc25b9c3999b6b4df8d3860c6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:28 -0600 Subject: board/haboki/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ieb82f949a57e5827c6e9d015cd9334dd94ed46c5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749381 Reviewed-by: Jeremy Bettis --- board/haboki/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/haboki/board.h b/board/haboki/board.h index fcb3015729..cfd36cd555 100644 --- a/board/haboki/board.h +++ b/board/haboki/board.h @@ -29,8 +29,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From 484252e707b1ead8ce16e3a0415365297eda4c76 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:09 -0600 Subject: board/shotzo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib1a08a07f36709f03c22decbe636e73566de4328 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749423 Reviewed-by: Jeremy Bettis --- board/shotzo/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/shotzo/board.h b/board/shotzo/board.h index df27eddb1f..ee014cb18d 100644 --- a/board/shotzo/board.h +++ b/board/shotzo/board.h @@ -29,8 +29,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From 9741d3be9e6c4018888eb5fa86b8f696b5bb3ce3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:35 -0600 Subject: board/osiris/fans.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I38e5ef11a3359db44755b554f4e7ed092d9d2013 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749395 Reviewed-by: Jeremy Bettis --- board/osiris/fans.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/osiris/fans.c b/board/osiris/fans.c index 4b7ae45598..fd6e64befd 100644 --- a/board/osiris/fans.c +++ b/board/osiris/fans.c @@ -37,7 +37,7 @@ static const struct fan_conf fan_conf_0 = { static const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, - .ch = MFT_CH_1, /* Use MFT id to control fan */ + .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, .enable_gpio = GPIO_EN_PP5000_FAN, }; -- cgit v1.2.1 From 13e3f7ed993e0fec4dd0022d768fb9b161263330 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:59 -0600 Subject: common/keyboard_scan.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I83a6ba63429a424d2cc4b6dbf1714eabe1ff1e18 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749467 Reviewed-by: Jeremy Bettis --- common/keyboard_scan.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c index f445efc33f..b35a90ac16 100644 --- a/common/keyboard_scan.c +++ b/common/keyboard_scan.c @@ -91,9 +91,9 @@ static const struct boot_key_entry boot_key_list[] = { }; #else struct boot_key_entry boot_key_list[] = { - {KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC}, /* Esc */ - {KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN}, /* Down-arrow */ - {KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT}, /* Left-Shift */ + { KEYBOARD_COL_ESC, KEYBOARD_ROW_ESC }, /* Esc */ + { KEYBOARD_COL_DOWN, KEYBOARD_ROW_DOWN }, /* Down-arrow */ + { KEYBOARD_COL_LEFT_SHIFT, KEYBOARD_ROW_LEFT_SHIFT }, /* Left-Shift */ }; #endif static uint32_t boot_key_value = BOOT_KEY_NONE; @@ -232,17 +232,17 @@ static int keyboard_read_adc_rows(void) */ static void keyboard_read_refresh_key(uint8_t *state) { - #ifndef CONFIG_KEYBOARD_MULTIPLE +#ifndef CONFIG_KEYBOARD_MULTIPLE if (!gpio_get_level(GPIO_RFR_KEY_L)) state[KEYBOARD_COL_REFRESH] |= BIT(KEYBOARD_ROW_REFRESH); else state[KEYBOARD_COL_REFRESH] &= ~BIT(KEYBOARD_ROW_REFRESH); - #else +#else if (!gpio_get_level(GPIO_RFR_KEY_L)) state[key_typ.col_refresh] |= BIT(key_typ.row_refresh); else state[key_typ.col_refresh] &= ~BIT(key_typ.row_refresh); - #endif +#endif } #endif @@ -448,15 +448,15 @@ static int check_runtime_keys(const uint8_t *state) if (state[key_vol_up_col] != KEYBOARD_ROW_TO_MASK(key_vol_up_row)) return 0; - #ifndef CONFIG_KEYBOARD_MULTIPLE +#ifndef CONFIG_KEYBOARD_MULTIPLE if (state[KEYBOARD_COL_RIGHT_ALT] != KEYBOARD_MASK_RIGHT_ALT && state[KEYBOARD_COL_LEFT_ALT] != KEYBOARD_MASK_LEFT_ALT) return 0; - #else +#else if (state[key_typ.col_right_alt] != KEYBOARD_MASK_RIGHT_ALT && state[key_typ.col_left_alt] != KEYBOARD_MASK_LEFT_ALT) return 0; - #endif +#endif /* * Count number of columns with keys pressed. We know two columns are @@ -471,7 +471,7 @@ static int check_runtime_keys(const uint8_t *state) if (num_press != 3) return 0; - #ifndef CONFIG_KEYBOARD_MULTIPLE +#ifndef CONFIG_KEYBOARD_MULTIPLE /* Check individual keys */ if (state[KEYBOARD_COL_KEY_R] == KEYBOARD_MASK_KEY_R) { /* R = reboot */ @@ -485,7 +485,7 @@ static int check_runtime_keys(const uint8_t *state) system_enter_hibernate(0, 0); return 1; } - #else +#else /* Check individual keys */ if (state[key_typ.col_key_r] == KEYBOARD_MASK_KEY_R) { /* R = reboot */ @@ -499,7 +499,7 @@ static int check_runtime_keys(const uint8_t *state) system_enter_hibernate(0, 0); return 1; } - #endif +#endif return 0; } @@ -713,11 +713,11 @@ static uint32_t check_key_list(const uint8_t *state) curr_state[c] &= ~KEYBOARD_MASK_PWRBTN; #endif - #ifndef CONFIG_KEYBOARD_MULTIPLE +#ifndef CONFIG_KEYBOARD_MULTIPLE curr_state[KEYBOARD_COL_REFRESH] &= ~keyboard_mask_refresh; - #else +#else curr_state[key_typ.col_refresh] &= ~keyboard_mask_refresh; - #endif +#endif /* Update mask with all boot keys that were pressed. */ k = boot_key_list; @@ -782,16 +782,16 @@ static uint32_t check_boot_key(const uint8_t *state) if (system_jumped_late()) return BOOT_KEY_NONE; - /* If reset was not caused by reset pin, refresh must be held down */ - #ifndef CONFIG_KEYBOARD_MULTIPLE +/* If reset was not caused by reset pin, refresh must be held down */ +#ifndef CONFIG_KEYBOARD_MULTIPLE if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) && !(state[KEYBOARD_COL_REFRESH] & keyboard_mask_refresh)) return BOOT_KEY_NONE; - #else +#else if (!(system_get_reset_flags() & EC_RESET_FLAG_RESET_PIN) && !(state[key_typ.col_refresh] & keyboard_mask_refresh)) return BOOT_KEY_NONE; - #endif +#endif return check_key_list(state); } -- cgit v1.2.1 From 38637a56a1534fa0b6a9f37d6f8f2f7bdb323993 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:38:33 -0600 Subject: baseboard/honeybuns/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I8b46e25b368675f7d37413bc4d244724a9cf3947 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748787 Reviewed-by: Jeremy Bettis --- baseboard/honeybuns/usb_pd_policy.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/baseboard/honeybuns/usb_pd_policy.c b/baseboard/honeybuns/usb_pd_policy.c index e40af6ea2e..a6a17c7ffb 100644 --- a/baseboard/honeybuns/usb_pd_policy.c +++ b/baseboard/honeybuns/usb_pd_policy.c @@ -469,10 +469,11 @@ static int svdm_response_svids(int port, uint32_t *payload) const uint32_t vdo_dp_modes[1] = { VDO_MODE_DP(/* Must support C and E. D is required for 2 lanes */ - MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, 0, /* DFP pin - cfg - supported - */ + MODE_DP_PIN_C | MODE_DP_PIN_D | MODE_DP_PIN_E, + 0, /* DFP pin + cfg + supported + */ 0, /* usb2.0 signalling in AMode may be req */ CABLE_RECEPTACLE, /* its a receptacle */ MODE_DP_V13, /* DPv1.3 Support, no Gen2 */ -- cgit v1.2.1 From aab80d446c4467f4b14a204ca2e409ba16174a00 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:53 -0600 Subject: zephyr/include/emul/tcpc/emul_tcpci.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ifa51b9bd05dc05f84416a1bd3162670639ee62a5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749526 Reviewed-by: Jeremy Bettis --- zephyr/include/emul/tcpc/emul_tcpci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h index b1bc8be926..f819a60567 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci.h +++ b/zephyr/include/emul/tcpc/emul_tcpci.h @@ -122,7 +122,7 @@ struct tcpc_emul_data { .data = &tcpci_ctx##n.common, \ .addr = DT_INST_REG_ADDR(n), \ }, \ - }; \ + }; \ EMUL_DEFINE(init, DT_DRV_INST(n), cfg_ptr, &tcpc_emul_data_##n) /** Response from TCPCI specific device operations */ -- cgit v1.2.1 From 782068a5f4d1b82c774b8c3bb66354d7bde60958 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:03 -0600 Subject: board/boten/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I6080b6e239ffc491a868e5d85506cd4c293f0203 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748792 Reviewed-by: Jeremy Bettis --- board/boten/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/boten/board.h b/board/boten/board.h index b1442fd5e2..92f41f4d0a 100644 --- a/board/boten/board.h +++ b/board/boten/board.h @@ -26,8 +26,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) -- cgit v1.2.1 From c36a2a6bf64e30b6f33dceb132d92e7bb5109662 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:20 -0600 Subject: board/waddledoo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I46ca548c8b63d24016fa18ec54739b7c22da4102 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749426 Reviewed-by: Jeremy Bettis --- board/waddledoo/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/waddledoo/board.h b/board/waddledoo/board.h index c7f892aaa9..90f4da23e8 100644 --- a/board/waddledoo/board.h +++ b/board/waddledoo/board.h @@ -37,8 +37,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -- cgit v1.2.1 From 3aa0b5a7206e295a8e9fdea41ce7bce3de6d44ec Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:21 -0600 Subject: driver/charger/isl9241.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iacffb6159b37fd7ec21a4b7029e1fcfe052a1abd Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749472 Reviewed-by: Jeremy Bettis --- driver/charger/isl9241.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/charger/isl9241.h b/driver/charger/isl9241.h index adddd1fc77..f9387d7df1 100644 --- a/driver/charger/isl9241.h +++ b/driver/charger/isl9241.h @@ -151,7 +151,7 @@ #define ISL9241_VIN_ADC_BIT_OFFSET 6 #define ISL9241_VIN_ADC_STEP_MV 96 -#define ISL9241_ADC_POLLING_TIME_US 400 +#define ISL9241_ADC_POLLING_TIME_US 400 /* * Used to reset ACOKref register to normal value to detect low voltage (5V or @@ -163,6 +163,6 @@ * Max wait time for Vsys to be close to Vin (Vadp) before turning on the bypass * gate. See 2.5.1 of application notes for details. */ -#define ISL9241_BYPASS_VSYS_TIMEOUT_MS 500 +#define ISL9241_BYPASS_VSYS_TIMEOUT_MS 500 #endif /* __CROS_EC_ISL9241_H */ -- cgit v1.2.1 From 5bbf7841fe66c56a540e65bc94b476e8a2b254c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:22 -0600 Subject: chip/stm32/registers-stm32f4.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I8bf57a3d4c493e5b2db0bee9b346892e359712cf Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749462 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32f4.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index cccc430fd2..37d9d88568 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -457,8 +457,9 @@ #define STM32F4_PLL_REQ 2000000 #define STM32F4_RTC_REQ 1000000 #define STM32F4_IO_CLOCK 45000000 -#define STM32F4_USB_REQ 45000000 /* not compatible with USB, will use PLLSAI \ - */ +#define STM32F4_USB_REQ \ + 45000000 /* not compatible with USB, will use PLLSAI \ + */ #define STM32F4_VCO_CLOCK 360000000 #define STM32F4_HSI_CLOCK 16000000 #define STM32F4_LSI_CLOCK 32000 -- cgit v1.2.1 From f846c0d8d9e6ee3c1fe5f0c890d897d7bb720262 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:01 -0600 Subject: board/servo_v4p1/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I1039c7385bab9d22f51c8a746a2c60d5880fc35e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749421 Reviewed-by: Jeremy Bettis --- board/servo_v4p1/usb_pd_config.h | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/board/servo_v4p1/usb_pd_config.h b/board/servo_v4p1/usb_pd_config.h index 0b21f2b063..2660d32963 100644 --- a/board/servo_v4p1/usb_pd_config.h +++ b/board/servo_v4p1/usb_pd_config.h @@ -189,23 +189,25 @@ static inline void pd_select_polarity(int port, int polarity) if (port == CHG) { /* CHG use the right comparator inverted input for COMP2 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | - (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: - C0_CC2 - */ - : - STM32_COMP_CMP2INSEL_INM6); /* PA2: - C0_CC1 - */ + (polarity ? + STM32_COMP_CMP2INSEL_INM4 /* PA4: + C0_CC2 + */ + : + STM32_COMP_CMP2INSEL_INM6); /* PA2: + C0_CC1 + */ } else { /* DUT use the right comparator inverted input for COMP1 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: - C1_CC2 - */ - : - STM32_COMP_CMP1INSEL_INM6); /* PA0: - C1_CC1 - */ + (polarity ? + STM32_COMP_CMP1INSEL_INM5 /* PA5: + C1_CC2 + */ + : + STM32_COMP_CMP1INSEL_INM6); /* PA0: + C1_CC1 + */ } } -- cgit v1.2.1 From 94c8071c83dd2b7badb5712367ff4ab35a6bd358 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:20 -0600 Subject: board/burnet/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Idd2b295c4bf95f16f508909b847a9b61c74dedf2 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3728111 Reviewed-by: Jeremy Bettis --- board/burnet/board.c | 100 ++++++++++++++++++++++----------------------------- 1 file changed, 42 insertions(+), 58 deletions(-) diff --git a/board/burnet/board.c b/board/burnet/board.c index 153625fb7d..f87ca7c837 100644 --- a/board/burnet/board.c +++ b/board/burnet/board.c @@ -48,8 +48,8 @@ #include "usb_pd_tcpm.h" #include "util.h" -#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args) static void tcpc_alert_event(enum gpio_signal signal) { @@ -61,40 +61,34 @@ static void tcpc_alert_event(enum gpio_signal signal) /******************************************************************************/ /* ADC channels. Must be in the exactly same order as in enum adc_channel. */ const struct adc_t adc_channels[] = { - [ADC_BOARD_ID] = {"BOARD_ID", 3300, 4096, 0, STM32_AIN(10)}, - [ADC_EC_SKU_ID] = {"EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8)}, + [ADC_BOARD_ID] = { "BOARD_ID", 3300, 4096, 0, STM32_AIN(10) }, + [ADC_EC_SKU_ID] = { "EC_SKU_ID", 3300, 4096, 0, STM32_AIN(8) }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); /******************************************************************************/ /* I2C ports */ const struct i2c_port_t i2c_ports[] = { - { - .name = "typec", - .port = 0, - .kbps = 400, - .scl = GPIO_I2C1_SCL, - .sda = GPIO_I2C1_SDA - }, - { - .name = "other", - .port = 1, - .kbps = 100, - .scl = GPIO_I2C2_SCL, - .sda = GPIO_I2C2_SDA - }, + { .name = "typec", + .port = 0, + .kbps = 400, + .scl = GPIO_I2C1_SCL, + .sda = GPIO_I2C1_SDA }, + { .name = "other", + .port = 1, + .kbps = 100, + .scl = GPIO_I2C2_SCL, + .sda = GPIO_I2C2_SDA }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); const struct i2c_port_t i2c_bitbang_ports[] = { - { - .name = "battery", - .port = 2, - .kbps = 100, - .scl = GPIO_I2C3_SCL, - .sda = GPIO_I2C3_SDA, - .drv = &bitbang_drv - }, + { .name = "battery", + .port = 2, + .kbps = 100, + .scl = GPIO_I2C3_SCL, + .sda = GPIO_I2C3_SDA, + .drv = &bitbang_drv }, }; const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); @@ -102,8 +96,8 @@ const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { - {GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L"}, - {GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, + { GPIO_AP_IN_SLEEP_L, POWER_SIGNAL_ACTIVE_LOW, "AP_IN_S3_L" }, + { GPIO_PMIC_EC_RESETB, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD" }, }; BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); @@ -159,8 +153,7 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -static void board_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, +static void board_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { /* This driver does not use host command ACKs */ @@ -225,12 +218,12 @@ int board_set_active_charge_port(int charge_port) return EC_SUCCESS; } -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_ma = (charge_ma * 95) / 100; - charge_set_input_current_limit(MAX(charge_ma, - CONFIG_CHARGER_INPUT_CURRENT), charge_mv); + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); } int board_discharge_on_ac(int enable) @@ -300,8 +293,7 @@ static void board_spi_enable(void) /* Pin mux spi peripheral toward the sensor. */ gpio_config_module(MODULE_SPI_CONTROLLER, 1); } -DECLARE_HOOK(HOOK_CHIPSET_STARTUP, - board_spi_enable, +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_spi_enable, MOTION_SENSE_HOOK_PRIO - 1); static void board_spi_disable(void) @@ -317,8 +309,7 @@ static void board_spi_disable(void) spi_enable(&spi_devices[0], 0); STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; } -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, - board_spi_disable, +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_spi_disable, MOTION_SENSE_HOOK_PRIO + 1); #endif /* !VARIANT_KUKUI_NO_SENSORS */ @@ -329,23 +320,17 @@ static struct mutex g_lid_mutex; static struct mutex g_base_mutex; /* Rotation matrixes */ -static const mat33_fp_t lid_standard_ref = { - {FLOAT_TO_FP(1), 0, 0}, - {0, FLOAT_TO_FP(-1), 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_bmi160_ref = { - {FLOAT_TO_FP(-1), 0, 0}, - {0, FLOAT_TO_FP(1), 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_bmi160_ref = { { FLOAT_TO_FP(-1), 0, 0 }, + { 0, FLOAT_TO_FP(1), 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; -static const mat33_fp_t base_icm426xx_ref = { - {0, FLOAT_TO_FP(-1), 0}, - {FLOAT_TO_FP(-1), 0, 0}, - {0, 0, FLOAT_TO_FP(-1)} -}; +static const mat33_fp_t base_icm426xx_ref = { { 0, FLOAT_TO_FP(-1), 0 }, + { FLOAT_TO_FP(-1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(-1) } }; /* sensor private data */ static struct accelgyro_saved_data_t g_bma253_data; @@ -518,8 +503,7 @@ static void board_update_config(void) enum ec_error_list rv; /* Ping for ack */ - rv = i2c_read8(I2C_PORT_SENSORS, - KX022_ADDR1_FLAGS, KX022_WHOAMI, &val); + rv = i2c_read8(I2C_PORT_SENSORS, KX022_ADDR1_FLAGS, KX022_WHOAMI, &val); if (rv == EC_SUCCESS) motion_sensors[LID_ACCEL] = lid_accel_kx022; @@ -555,7 +539,8 @@ static void board_init(void) motion_sensor_count = ARRAY_SIZE(motion_sensors); /* Enable interrupts from BMI160 sensor. */ gpio_enable_interrupt(GPIO_ACCEL_INT_ODL); - /* For some reason we have to do this again in case of sysjump */ + /* For some reason we have to do this again in case of sysjump + */ board_spi_enable(); board_update_config(); } else { @@ -565,8 +550,7 @@ static void board_init(void) /* Turn off GMR interrupt */ gmr_tablet_switch_disable(); /* Base accel is not stuffed, don't allow line to float */ - gpio_set_flags(GPIO_ACCEL_INT_ODL, - GPIO_INPUT | GPIO_PULL_DOWN); + gpio_set_flags(GPIO_ACCEL_INT_ODL, GPIO_INPUT | GPIO_PULL_DOWN); board_spi_disable(); } #endif /* !VARIANT_KUKUI_NO_SENSORS */ -- cgit v1.2.1 From 17a53ad03475954258ca144a44cc402e239099cc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:58 -0600 Subject: board/kuldax/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I37100a21a6cb9cea6d5b89828731f14531c00acc Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749388 Reviewed-by: Jeremy Bettis --- board/kuldax/usbc_config.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/kuldax/usbc_config.c b/board/kuldax/usbc_config.c index 437dc437c1..a048dcbe22 100644 --- a/board/kuldax/usbc_config.c +++ b/board/kuldax/usbc_config.c @@ -144,7 +144,6 @@ static void board_tcpc_init(void) /* Don't reset TCPCs after initial reset */ if (!system_jumped_late()) { board_reset_pd_mcu(); - } /* Enable PPC interrupts. */ -- cgit v1.2.1 From 188f8f89e75babd6fb3c7b5ffdb9a5b79d8819a0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:09 -0600 Subject: chip/npcx/gpio_chip-npcx9.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I27900d570c33c9413c25eb91ac66b3f339ab153c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749459 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx9.h | 207 +++++++++++++++++++++++--------------------- 1 file changed, 106 insertions(+), 101 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h index 93ac5aadba..56bee39942 100644 --- a/chip/npcx/gpio_chip-npcx9.h +++ b/chip/npcx/gpio_chip-npcx9.h @@ -237,16 +237,19 @@ #endif /* UART Module */ -#define NPCX_ALT_GPIO_6_4 ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \ - */ +#define NPCX_ALT_GPIO_6_4 \ + ALT(6, 4, NPCX_ALT(J, CR_SIN1_SL2)) /* CR_SIN1_SL2 \ + */ #define NPCX_ALT_GPIO_6_5 \ ALT(6, 5, NPCX_ALT(J, CR_SOUT1_SL2)) /* CR_SOUT1_SL2 */ #define NPCX_ALT_GPIO_7_5 ALT(7, 5, NPCX_ALT(J, CR_SIN2_SL)) /* CR_SIN2_SL */ -#define NPCX_ALT_GPIO_8_6 ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \ - */ +#define NPCX_ALT_GPIO_8_6 \ + ALT(8, 6, NPCX_ALT(J, CR_SOUT2_SL)) /* CR_SOUT2_SL \ + */ #define NPCX_ALT_GPIO_D_4 ALT(D, 4, NPCX_ALT(J, CR_SIN3_SL)) /* CR_SIN3_SL */ -#define NPCX_ALT_GPIO_D_6 ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \ - */ +#define NPCX_ALT_GPIO_D_6 \ + ALT(D, 6, NPCX_ALT(J, CR_SOUT3_SL)) /* CR_SOUT3_SL \ + */ /* PWM Module */ #define NPCX_ALT_GPIO_C_3 ALT(C, 3, NPCX_ALT(4, PWM0_SL)) /* PWM0 */ @@ -298,10 +301,12 @@ #define NPCX_ALT_GPIO_B_1 ALT(B, 1, NPCX_ALT_INV(A, NO_KSO17_SL)) /* KSO17 */ /* PSL module */ -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ - */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ - */ +#define NPCX_ALT_GPIO_D_2 \ + ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 \ + ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ #define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ #define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ #define NPCX_ALT_GPIO_D_7 ALT(D, 7, NPCX_ALT(G, PSL_GPO_SL)) /* PSL_GPO */ @@ -311,97 +316,97 @@ #define NPCX_ALT_GPIO_A_3 ALT(A, 3, NPCX_ALT(0, SPIP_SL)) /* SPIP_MOSI */ #define NPCX_ALT_GPIO_A_1 ALT(A, 1, NPCX_ALT(0, SPIP_SL)) /* SPIP_SCLK */ -#define NPCX_ALT_TABLE \ - { \ - NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ - NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ - NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 \ - */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ - NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ - NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ - NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ - NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_C_7 /* ADC11 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ - NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ - NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */ \ - NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */ \ - NPCX_ALT_GPIO_D_7 /* PSL_GPO */ \ - NPCX_ALT_GPIO_E_0 /* ADC10 */ \ - NPCX_ALT_GPIO_E_1 /* ADC7 */ \ - NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ - NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ - NPCX_ALT_GPIO_F_0 /* ADC9 */ \ - NPCX_ALT_GPIO_F_1 /* ADC8 */ \ - NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ - NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ - NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ - NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ + NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ + NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 \ + */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ + NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ + NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN1_SL2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT1_SL2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* CR_SIN2_SL */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_6 /* CR_SOUT2_SL */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ + NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ + NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_C_7 /* ADC11 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ + NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ + NPCX_ALT_GPIO_D_4 /* CR_SIN3_SL */ \ + NPCX_ALT_GPIO_D_6 /* CR_SOUT3_SL */ \ + NPCX_ALT_GPIO_D_7 /* PSL_GPO */ \ + NPCX_ALT_GPIO_E_0 /* ADC10 */ \ + NPCX_ALT_GPIO_E_1 /* ADC7 */ \ + NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ + NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ + NPCX_ALT_GPIO_F_0 /* ADC9 */ \ + NPCX_ALT_GPIO_F_1 /* ADC8 */ \ + NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ + NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ + NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ + NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ } /*****************************************************************************/ -- cgit v1.2.1 From 4f9467ce58b0ae7822eed24ffe8a825823cc2bb6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:27 -0600 Subject: chip/ish/dma.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I04972bcbdc517b7f4c2e7c1a5ca4bc571c517704 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749428 Reviewed-by: Jeremy Bettis --- chip/ish/dma.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/chip/ish/dma.c b/chip/ish/dma.c index a14e1284d6..e94909ea87 100644 --- a/chip/ish/dma.c +++ b/chip/ish/dma.c @@ -138,10 +138,11 @@ int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, transfer */ DMA_DAR(chan_reg) = dst; /* Destination address */ DMA_SAR(chan_reg) = src; /* Source address */ - DMA_EN_REG = DMA_CH_EN_BIT(chan) | DMA_CH_EN_WE_BIT(chan); /* Enable - the - channel - */ + DMA_EN_REG = DMA_CH_EN_BIT(chan) | + DMA_CH_EN_WE_BIT(chan); /* Enable + the + channel + */ interrupt_unlock(eflags); rc = ish_wait_for_dma_done(chan); /* Wait for trans completion -- cgit v1.2.1 From d2b4b99cd581c81766df5cdf2fe8d4fb9af6416f Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:55 -0600 Subject: common/ec_ec_comm_client.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I96dc22801c2fd1cdf754ffebeee1f2f9680cc774 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749466 Reviewed-by: Jeremy Bettis --- common/ec_ec_comm_client.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/common/ec_ec_comm_client.c b/common/ec_ec_comm_client.c index 8f59c5b65e..1f87ad96cf 100644 --- a/common/ec_ec_comm_client.c +++ b/common/ec_ec_comm_client.c @@ -138,9 +138,10 @@ static int write_command(uint16_t command, uint8_t *data, int req_len, memset(request_header, 0, sizeof(*request_header)); /* fields0: leave seq_dup and is_response as 0. */ - request_header->fields0 = EC_EC_HOSTCMD_VERSION | /* version */ - (cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num - */ + request_header->fields0 = + EC_EC_HOSTCMD_VERSION | /* version */ + (cur_seq << EC_PACKET4_0_SEQ_NUM_SHIFT); /* seq_num + */ /* fields1: leave command_version as 0. */ if (req_len > 0) request_header->fields1 |= EC_PACKET4_1_DATA_CRC_PRESENT_MASK; -- cgit v1.2.1 From 29dde077633148c8f38424466610839d1b45d927 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:12 -0600 Subject: board/storo/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Icc5cfee8f3fb5674c5b57e070f39d1fd55b28e5a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749424 Reviewed-by: Jeremy Bettis --- board/storo/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/storo/board.h b/board/storo/board.h index d74a7e775c..8be738fa7e 100644 --- a/board/storo/board.h +++ b/board/storo/board.h @@ -27,8 +27,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -- cgit v1.2.1 From 3c13e20a5b2715e1df8be51057ed1d7154f9d2e4 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:11 -0600 Subject: board/brya/usbc_config.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I0598d4903c0fafa8666afb60260dd84e4c64756c Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748793 Reviewed-by: Jeremy Bettis --- board/brya/usbc_config.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c index 7d0947ed19..192f564c1a 100644 --- a/board/brya/usbc_config.c +++ b/board/brya/usbc_config.c @@ -40,11 +40,7 @@ #define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #ifdef CONFIG_ZEPHYR -enum ioex_port { - IOEX_C0_NCT38XX = 0, - IOEX_C2_NCT38XX, - IOEX_PORT_COUNT -}; +enum ioex_port { IOEX_C0_NCT38XX = 0, IOEX_C2_NCT38XX, IOEX_PORT_COUNT }; #endif /* CONFIG_ZEPHYR */ #ifndef CONFIG_ZEPHYR -- cgit v1.2.1 From c7fb991323930fece16b670f15435d8763c36741 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:09 -0600 Subject: common/usbc/tbt_alt_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I1cedabb2cfeb949d06746e9a92c3fb68921a0fce Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749469 Reviewed-by: Jeremy Bettis --- common/usbc/tbt_alt_mode.c | 114 +++++++++++++++++++++------------------------ 1 file changed, 54 insertions(+), 60 deletions(-) diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index 2d4f8bf9fa..608e5be195 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -57,8 +57,8 @@ */ #ifdef CONFIG_COMMON_RUNTIME -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #else #define CPRINTF(format, args...) #define CPRINTS(format, args...) @@ -70,8 +70,8 @@ * with a partner. It may be fixed in b/159495742, in which case this * logic is unneeded. */ -#define TBT_FLAG_RETRY_DONE BIT(0) -#define TBT_FLAG_EXIT_DONE BIT(1) +#define TBT_FLAG_RETRY_DONE BIT(0) +#define TBT_FLAG_EXIT_DONE BIT(1) #define TBT_FLAG_CABLE_ENTRY_DONE BIT(2) static uint8_t tbt_flags[CONFIG_USB_PD_PORT_MAX_COUNT]; @@ -123,14 +123,12 @@ void tbt_init(int port) bool tbt_is_active(int port) { - return tbt_state[port] != TBT_INACTIVE && - tbt_state[port] != TBT_START; + return tbt_state[port] != TBT_INACTIVE && tbt_state[port] != TBT_START; } bool tbt_entry_is_done(int port) { - return tbt_state[port] == TBT_ACTIVE || - tbt_state[port] == TBT_INACTIVE; + return tbt_state[port] == TBT_ACTIVE || tbt_state[port] == TBT_INACTIVE; } bool tbt_cable_entry_is_done(int port) @@ -140,13 +138,15 @@ bool tbt_cable_entry_is_done(int port) static void tbt_exit_done(int port) { - /* - * If the EC exits an alt mode autonomously, don't try to enter it again. If - * the AP commands the EC to exit DP mode, it might command the EC to enter - * again later, so leave the state machine ready for that possibility. - */ - tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) - ? TBT_START : TBT_INACTIVE; + /* + * If the EC exits an alt mode autonomously, don't try to enter it + * again. If the AP commands the EC to exit DP mode, it might command + * the EC to enter again later, so leave the state machine ready for + * that possibility. + */ + tbt_state[port] = IS_ENABLED(CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY) ? + TBT_START : + TBT_INACTIVE; TBT_CLR_FLAG(port, TBT_FLAG_RETRY_DONE); TBT_CLR_FLAG(port, TBT_FLAG_CABLE_ENTRY_DONE); @@ -164,7 +164,7 @@ static bool tbt_is_lrd_active_cable(int port) union tbt_mode_resp_cable cable_mode_resp; cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); /* TODO(b:233402434 b:233429913) * Need to add the checking that cable is passive in Discover ID * Header VDO. @@ -184,7 +184,7 @@ static bool tbt_sop_prime_needed(int port) * an LRD cable (passive in DiscoverIdentity, active in TBT mode) */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE || - tbt_is_lrd_active_cable(port)) + tbt_is_lrd_active_cable(port)) return true; return false; } @@ -196,7 +196,7 @@ static bool tbt_sop_prime_prime_needed(int port) disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); if (disc->identity.product_t1.a_rev20.sop_p_p && - !tbt_is_lrd_active_cable(port)) + !tbt_is_lrd_active_cable(port)) return true; return false; } @@ -220,16 +220,18 @@ void tbt_exit_mode_request(int port) tbt_state[port] = /* TODO: replace with tbt_sop_prime_prime_needed */ tbt_is_lrd_active_cable(port) ? - TBT_EXIT_SOP_PRIME : TBT_EXIT_SOP_PRIME_PRIME; + TBT_EXIT_SOP_PRIME : + TBT_EXIT_SOP_PRIME_PRIME; } } -static bool tbt_response_valid(int port, enum tcpci_msg_type type, - char *cmdt, int vdm_cmd) +static bool tbt_response_valid(int port, enum tcpci_msg_type type, char *cmdt, + int vdm_cmd) { enum tbt_states st = tbt_state[port]; union tbt_mode_resp_cable cable_mode_resp = { - .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) }; + .raw_value = pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME) + }; /* * Check for an unexpected response. @@ -291,14 +293,14 @@ bool tbt_cable_entry_required_for_usb4(int port) disc_sop_prime = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); if (pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME) < VDM_VER20 || disc_sop_prime->identity.product_t1.a_rev30.vdo_ver < - VDO_VERSION_1_3) + VDO_VERSION_1_3) return true; } return false; } void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, - uint32_t *vdm) + uint32_t *vdm) { const uint8_t vdm_cmd = PD_VDO_CMD(vdm[0]); int opos_sop, opos_sop_prime; @@ -365,13 +367,12 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, * Exit mode process is complete; go to inactive state. */ tbt_exit_done(port); - opos_sop_prime = - pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL); + opos_sop_prime = pd_alt_mode(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); /* Clear Thunderbolt related signals */ pd_dfp_exit_mode(port, TCPCI_MSG_SOP_PRIME, - USB_VID_INTEL, opos_sop_prime); + USB_VID_INTEL, opos_sop_prime); set_usb_mux_with_current_data_role(port); } else { tbt_retry_enter_mode(port); @@ -386,8 +387,8 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, break; default: /* Invalid or unexpected negotiation state */ - CPRINTF("%s called with invalid state %d\n", - __func__, tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + tbt_state[port]); tbt_exit_done(port); break; } @@ -441,8 +442,8 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) } break; default: - CPRINTS("C%d: NAK for cmd %d in state %d", port, - vdm_cmd, tbt_state[port]); + CPRINTS("C%d: NAK for cmd %d in state %d", port, vdm_cmd, + tbt_state[port]); tbt_exit_done(port); break; } @@ -451,7 +452,7 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) static bool tbt_mode_is_supported(int port, int vdo_count) { const struct pd_discovery *disc = - pd_get_am_discovery(port, TCPCI_MSG_SOP); + pd_get_am_discovery(port, TCPCI_MSG_SOP); if (!disc->identity.idh.modal_support) return false; @@ -465,8 +466,8 @@ static bool tbt_mode_is_supported(int port, int vdo_count) * SVID USB_VID_INTEL to enter Thunderbolt alt mode */ if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE && - !pd_is_mode_discovered_for_svid( - port, TCPCI_MSG_SOP_PRIME, USB_VID_INTEL)) + !pd_is_mode_discovered_for_svid(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL)) return false; return true; @@ -516,14 +517,12 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, *tx_type = TCPCI_MSG_SOP_PRIME; break; case TBT_ENTER_SOP_PRIME_PRIME: - vdo_count_ret = - enter_tbt_compat_mode( - port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); + vdo_count_ret = enter_tbt_compat_mode( + port, TCPCI_MSG_SOP_PRIME_PRIME, vdm); *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_ENTER_SOP: - vdo_count_ret = - enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); + vdo_count_ret = enter_tbt_compat_mode(port, TCPCI_MSG_SOP, vdm); break; case TBT_ACTIVE: /* @@ -545,43 +544,38 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, return MSG_SETUP_MUX_WAIT; case TBT_EXIT_SOP: /* DPM will only call this after safe state set is done */ - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP, USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS( - pd_get_vdo_ver(port, TCPCI_MSG_SOP)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver(port, TCPCI_MSG_SOP)); vdo_count_ret = 1; break; case TBT_EXIT_SOP_PRIME_PRIME: - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver(port, - TCPCI_MSG_SOP_PRIME_PRIME)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS(pd_get_vdo_ver( + port, TCPCI_MSG_SOP_PRIME_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME_PRIME; break; case TBT_EXIT_SOP_PRIME: - modep = pd_get_amode_data(port, - TCPCI_MSG_SOP_PRIME, USB_VID_INTEL); + modep = pd_get_amode_data(port, TCPCI_MSG_SOP_PRIME, + USB_VID_INTEL); if (!(modep && modep->opos)) return MSG_SETUP_ERROR; vdm[0] = VDO(USB_VID_INTEL, 1, CMD_EXIT_MODE) | - VDO_OPOS(modep->opos) | - VDO_CMDT(CMDT_INIT) | - VDO_SVDM_VERS(pd_get_vdo_ver(port, - TCPCI_MSG_SOP_PRIME)); + VDO_OPOS(modep->opos) | VDO_CMDT(CMDT_INIT) | + VDO_SVDM_VERS( + pd_get_vdo_ver(port, TCPCI_MSG_SOP_PRIME)); vdo_count_ret = 1; *tx_type = TCPCI_MSG_SOP_PRIME; break; @@ -589,8 +583,8 @@ enum dpm_msg_setup_status tbt_setup_next_vdm(int port, int *vdo_count, /* Thunderbolt mode is inactive */ return MSG_SETUP_UNSUPPORTED; default: - CPRINTF("%s called with invalid state %d\n", - __func__, tbt_state[port]); + CPRINTF("%s called with invalid state %d\n", __func__, + tbt_state[port]); return MSG_SETUP_ERROR; } -- cgit v1.2.1 From 40201bf9dd6afa33f5b2fe8ac9fb0a47f94b0d84 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:19 -0600 Subject: test/cbi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I08e52af33263ff39a444a685c75a620dc8fcf37f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749520 Reviewed-by: Jeremy Bettis --- test/cbi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/test/cbi.c b/test/cbi.c index a5a38dcb10..a99774a913 100644 --- a/test/cbi.c +++ b/test/cbi.c @@ -186,7 +186,8 @@ DECLARE_EC_TEST(test_all_tags) EC_SUCCESS, NULL); count++; zassert_equal(cbi_set_board_info(CBI_TAG_FACTORY_CALIBRATION_DATA, &d8, - sizeof(d8)), EC_SUCCESS, NULL); + sizeof(d8)), + EC_SUCCESS, NULL); count++; /* Read out all */ -- cgit v1.2.1 From cf500f5ef89472f13571f420217185c53a1cbcab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:04 -0600 Subject: board/dojo/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I9b7140db82b9eb74643776e433b670260ee5051f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749376 Reviewed-by: Jeremy Bettis --- board/dojo/board.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/board/dojo/board.c b/board/dojo/board.c index fcb2db6d9b..5d2aa78f2b 100644 --- a/board/dojo/board.c +++ b/board/dojo/board.c @@ -119,20 +119,20 @@ static struct kionix_accel_data g_kx022_data; /* Matrix to rotate accelrator into standard reference frame */ static const mat33_fp_t base_standard_ref = { { 0, FLOAT_TO_FP(-1), 0 }, - { FLOAT_TO_FP(1), 0, 0 }, - { 0, 0, FLOAT_TO_FP(1) } }; + { FLOAT_TO_FP(1), 0, 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static const mat33_fp_t lid_standard_ref = { { FLOAT_TO_FP(1), 0, 0 }, { 0, FLOAT_TO_FP(-1), 0 }, { 0, 0, FLOAT_TO_FP(-1) } }; static const mat33_fp_t icm42607_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(-1), 0 }, - { 0, 0, FLOAT_TO_FP(1) } }; + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; static const mat33_fp_t icm426xx_standard_ref = { { FLOAT_TO_FP(-1), 0, 0 }, - { 0, FLOAT_TO_FP(-1), 0 }, - { 0, 0, FLOAT_TO_FP(1) } }; + { 0, FLOAT_TO_FP(-1), 0 }, + { 0, 0, FLOAT_TO_FP(1) } }; struct motion_sensor_t motion_sensors[] = { /* @@ -435,8 +435,8 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { /* Limit input current lower than 2944 mA for safety */ charge_ma = MIN(charge_ma, 2944); -- cgit v1.2.1 From 937c3cbbedf271cc101df8acbe460a348634e980 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:14 -0600 Subject: core/minute-ia/interrupts.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iafd5b2ee41f980ee448ff63b68dad19a70563903 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749470 Reviewed-by: Jeremy Bettis --- core/minute-ia/interrupts.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index cf16217062..872f9a73b3 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -386,20 +386,21 @@ __asm__(".section .text._lapic_error_handler\n" "movl $stack_end, %esp\n" "push %eax\n" #ifdef CONFIG_TASK_PROFILING - "push $" STRINGIFY(CONFIG_IRQ_COUNT) "\n" - "call task_start_irq_handler\n" - "addl $0x04, %esp\n" + "push $" STRINGIFY( + CONFIG_IRQ_COUNT) "\n" + "call task_start_irq_handler\n" + "addl $0x04, %esp\n" #endif - "call handle_lapic_lvt_error\n" - "pop %esp\n" - "movl $0x00, (0xFEE000B0)\n" /* Set - EOI - for - LAPIC - */ + "call handle_lapic_lvt_error\n" + "pop %esp\n" + "movl $0x00, (0xFEE000B0)\n" /* Set + EOI + for + LAPIC + */ ASM_LOCK_PREFIX "subl $1, __in_isr\n" - "popa\n" - "iret\n"); + "popa\n" + "iret\n"); /* Should only be called in interrupt context */ void unhandled_vector(void) -- cgit v1.2.1 From f7701717fe435e8cc1a4364bf3364b13cbd8d7d9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:31 -0600 Subject: board/hammer/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I326505b9a3e18ac8c9ee3e7ab4c3ef51cc20201d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749382 Reviewed-by: Jeremy Bettis --- board/hammer/board.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/board/hammer/board.h b/board/hammer/board.h index 6a5c14d9b9..871ad40c39 100644 --- a/board/hammer/board.h +++ b/board/hammer/board.h @@ -177,16 +177,19 @@ #undef CONFIG_USB_I2C_MAX_WRITE_COUNT #ifdef VARIANT_HAMMER_TP_LARGE_PAGE /* Zed requires 516 byte per packet for touchpad update */ -#define CONFIG_USB_I2C_MAX_WRITE_COUNT (1024 - 4) /* 4 is maximum header size \ - */ +#define CONFIG_USB_I2C_MAX_WRITE_COUNT \ + (1024 - 4) /* 4 is maximum header size \ + */ #else -#define CONFIG_USB_I2C_MAX_WRITE_COUNT (128 - 4) /* 4 is maximum header size \ - */ +#define CONFIG_USB_I2C_MAX_WRITE_COUNT \ + (128 - 4) /* 4 is maximum header size \ + */ #endif #undef CONFIG_USB_I2C_MAX_READ_COUNT -#define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) /* 6 is maximum header size \ - */ +#define CONFIG_USB_I2C_MAX_READ_COUNT \ + (1024 - 6) /* 6 is maximum header size \ + */ #define CONFIG_I2C_XFER_LARGE_TRANSFER -- cgit v1.2.1 From 2ce8183edf710c03b509aa08117c5c0919540768 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:05 -0600 Subject: include/keyboard_scan.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Id6ba479b696613d3dc2b9ad8850adab61d783ff5 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749518 Reviewed-by: Jeremy Bettis --- include/keyboard_scan.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h index 9b0bec1191..3ce1f74745 100644 --- a/include/keyboard_scan.h +++ b/include/keyboard_scan.h @@ -44,7 +44,6 @@ struct boot_key_entry { uint8_t row; }; - /** * Initializes the module. */ @@ -184,4 +183,4 @@ struct keyboard_type { extern struct keyboard_type key_typ; #endif -#endif /* __CROS_EC_KEYBOARD_SCAN_H */ +#endif /* __CROS_EC_KEYBOARD_SCAN_H */ -- cgit v1.2.1 From 2e9442b5181a9da9144d46023d58c9b45d5bcc54 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:57 -0600 Subject: chip/max32660/wdt_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ie06213a30b4102ea2b657b6c0e6ecc2b9bd19db9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749456 Reviewed-by: Jeremy Bettis --- chip/max32660/wdt_regs.h | 98 ++++++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 44 deletions(-) diff --git a/chip/max32660/wdt_regs.h b/chip/max32660/wdt_regs.h index fc2015696e..0ca8b0836c 100644 --- a/chip/max32660/wdt_regs.h +++ b/chip/max32660/wdt_regs.h @@ -258,17 +258,19 @@ typedef struct { */ #define MXC_V_WDT_CTRL_WDT_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_WDT_EN_DIS \ - (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ - CTRL_WDT_EN_DIS \ - Setting */ +#define MXC_S_WDT_CTRL_WDT_EN_DIS \ + (MXC_V_WDT_CTRL_WDT_EN_DIS \ + << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ + CTRL_WDT_EN_DIS \ + Setting */ #define MXC_V_WDT_CTRL_WDT_EN_EN \ ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_WDT_EN_EN \ - (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ - CTRL_WDT_EN_EN \ - Setting */ +#define MXC_S_WDT_CTRL_WDT_EN_EN \ + (MXC_V_WDT_CTRL_WDT_EN_EN \ + << MXC_F_WDT_CTRL_WDT_EN_POS) /**< \ + CTRL_WDT_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ #define MXC_F_WDT_CTRL_INT_FLAG \ @@ -282,11 +284,12 @@ typedef struct { */ #define MXC_V_WDT_CTRL_INT_FLAG_PENDING \ ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */ -#define MXC_S_WDT_CTRL_INT_FLAG_PENDING \ - (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< \ - CTRL_INT_FLAG_PENDING \ - Setting \ - */ +#define MXC_S_WDT_CTRL_INT_FLAG_PENDING \ + (MXC_V_WDT_CTRL_INT_FLAG_PENDING \ + << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< \ + CTRL_INT_FLAG_PENDING \ + Setting \ + */ #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ #define MXC_F_WDT_CTRL_INT_EN \ @@ -294,17 +297,19 @@ typedef struct { */ #define MXC_V_WDT_CTRL_INT_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */ -#define MXC_S_WDT_CTRL_INT_EN_DIS \ - (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ - CTRL_INT_EN_DIS \ - Setting */ +#define MXC_S_WDT_CTRL_INT_EN_DIS \ + (MXC_V_WDT_CTRL_INT_EN_DIS \ + << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ + CTRL_INT_EN_DIS \ + Setting */ #define MXC_V_WDT_CTRL_INT_EN_EN \ ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_INT_EN_EN \ - (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ - CTRL_INT_EN_EN \ - Setting */ +#define MXC_S_WDT_CTRL_INT_EN_EN \ + (MXC_V_WDT_CTRL_INT_EN_EN \ + << MXC_F_WDT_CTRL_INT_EN_POS) /**< \ + CTRL_INT_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ #define MXC_F_WDT_CTRL_RST_EN \ @@ -312,17 +317,19 @@ typedef struct { */ #define MXC_V_WDT_CTRL_RST_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */ -#define MXC_S_WDT_CTRL_RST_EN_DIS \ - (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ - CTRL_RST_EN_DIS \ - Setting */ +#define MXC_S_WDT_CTRL_RST_EN_DIS \ + (MXC_V_WDT_CTRL_RST_EN_DIS \ + << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ + CTRL_RST_EN_DIS \ + Setting */ #define MXC_V_WDT_CTRL_RST_EN_EN \ ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value \ */ -#define MXC_S_WDT_CTRL_RST_EN_EN \ - (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ - CTRL_RST_EN_EN \ - Setting */ +#define MXC_S_WDT_CTRL_RST_EN_EN \ + (MXC_V_WDT_CTRL_RST_EN_EN \ + << MXC_F_WDT_CTRL_RST_EN_POS) /**< \ + CTRL_RST_EN_EN \ + Setting */ #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ #define MXC_F_WDT_CTRL_RST_FLAG \ @@ -330,11 +337,12 @@ typedef struct { Mask */ #define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */ -#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT \ - (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< \ - CTRL_RST_FLAG_NOEVENT \ - Setting \ - */ +#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT \ + (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT \ + << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< \ + CTRL_RST_FLAG_NOEVENT \ + Setting \ + */ #define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED \ ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */ #define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED \ @@ -351,17 +359,19 @@ typedef struct { Mask */ #define MXC_V_WDT_RST_WDT_RST_SEQ0 \ ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ0 \ - (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< \ - RST_WDT_RST_SEQ0 \ - Setting \ - */ +#define MXC_S_WDT_RST_WDT_RST_SEQ0 \ + (MXC_V_WDT_RST_WDT_RST_SEQ0 \ + << MXC_F_WDT_RST_WDT_RST_POS) /**< \ + RST_WDT_RST_SEQ0 \ + Setting \ + */ #define MXC_V_WDT_RST_WDT_RST_SEQ1 \ ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ -#define MXC_S_WDT_RST_WDT_RST_SEQ1 \ - (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< \ - RST_WDT_RST_SEQ1 \ - Setting \ - */ +#define MXC_S_WDT_RST_WDT_RST_SEQ1 \ + (MXC_V_WDT_RST_WDT_RST_SEQ1 \ + << MXC_F_WDT_RST_WDT_RST_POS) /**< \ + RST_WDT_RST_SEQ1 \ + Setting \ + */ #endif /* _WDT_REGS_H_ */ -- cgit v1.2.1 From 4b09c6aefb6068a468a0d05f2dea9d741edc6b5a Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:45 -0600 Subject: driver/tcpm/ccgxxf.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ib95d23d30570be7f85ca66f8d6ea657130f0d096 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749475 Reviewed-by: Jeremy Bettis --- driver/tcpm/ccgxxf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/driver/tcpm/ccgxxf.h b/driver/tcpm/ccgxxf.h index 7d97962351..51cc7819a0 100644 --- a/driver/tcpm/ccgxxf.h +++ b/driver/tcpm/ccgxxf.h @@ -21,8 +21,8 @@ #define CCGXXF_REG_FW_VERSION_BUILD 0x96 /* Firmware update / reset control register */ -#define CCGXXF_REG_FWU_COMMAND 0x92 -#define CCGXXF_FWU_CMD_RESET 0x0077 +#define CCGXXF_REG_FWU_COMMAND 0x92 +#define CCGXXF_FWU_CMD_RESET 0x0077 /** * Reset CCGXXF chip -- cgit v1.2.1 From 9a7dc1582e05ade135f955e88c4d393e8d25a0f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:06 -0600 Subject: chip/npcx/gpio_chip-npcx7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iff535c58706ca8599e114c9af4ed53c44235effa Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749458 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx7.h | 214 +++++++++++++++++++++++--------------------- 1 file changed, 110 insertions(+), 104 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index f3098506d7..db3aa8cc71 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -82,8 +82,9 @@ #define NPCX_WUI_GPIO_F_0 WUI(0, MIWU_GROUP_8, 5) #define NPCX_WUI_GPIO_F_3 WUI(0, MIWU_GROUP_8, 6) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_E_7 WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \ - */ +#define NPCX_WUI_GPIO_E_7 \ + WUI(0, MIWU_GROUP_8, 7) /* Used as CLKIN if support \ + */ #endif /* MIWU1 */ @@ -152,8 +153,9 @@ #define NPCX_WUI_GPIO_6_3 WUI(1, MIWU_GROUP_7, 3) #define NPCX_WUI_GPIO_6_4 WUI(1, MIWU_GROUP_7, 4) #ifndef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_WUI_GPIO_7_1 WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \ - support*/ +#define NPCX_WUI_GPIO_7_1 \ + WUI(1, MIWU_GROUP_7, 7) /* Used as CLKOUT if \ + support*/ #endif /* Group H: NPCX_IRQ_WKINTH_1 */ @@ -318,10 +320,12 @@ /* PSL module (Optional) */ #ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_ALT_GPIO_D_2 ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ - */ -#define NPCX_ALT_GPIO_0_0 ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ - */ +#define NPCX_ALT_GPIO_D_2 \ + ALT(D, 2, NPCX_ALT_INV(D, NPSL_IN1_SL)) /* PSL_IN1 \ + */ +#define NPCX_ALT_GPIO_0_0 \ + ALT(0, 0, NPCX_ALT_INV(D, NPSL_IN2_SL)) /* PSL_IN2 \ + */ #define NPCX_ALT_GPIO_0_1 ALT(0, 1, NPCX_ALT(D, PSL_IN3_SL)) /* PSL_IN3 */ #define NPCX_ALT_GPIO_0_2 ALT(0, 2, NPCX_ALT(D, PSL_IN4_SL)) /* PSL_IN4 */ #else @@ -360,98 +364,98 @@ #define NPCX_ALT_GPIO_9_7 #endif -#define NPCX_ALT_TABLE \ - { \ - NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ - NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ - NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 \ - */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ - NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ - NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */ \ - NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_4 /* DMIC_CLK */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_9_7 /* DMIC_IN */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_0 /* I2S_DATA */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ - NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ - NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ - NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ - NPCX_ALT_GPIO_E_1 /* ADC7 */ \ - NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ - NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ - NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ - NPCX_ALT_GPIO_F_0 /* ADC9 */ \ - NPCX_ALT_GPIO_F_1 /* ADC8 */ \ - NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ - NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ - NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ - NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_0 /* PSL_IN2 */ \ + NPCX_ALT_GPIO_0_1 /* PSL_IN3 */ \ + NPCX_ALT_GPIO_0_2 /* PSL_IN4 */ \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 \ + */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 & CR_SIN */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SOUT */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_3 /* SMB5SCL0 */ \ + NPCX_ALT_GPIO_3_4 /* ADC6/PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_6 /* SMB5SDA0 */ \ + NPCX_ALT_GPIO_3_7 /* ADC5/PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN1 SEL2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT1 SEL2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* CR_SIN2 & 32KHZ_OUT */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_5 /* SMB4SCL0 */ \ + NPCX_ALT_GPIO_8_6 /* CR_SOUT2 & SMB4SDA0 */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA0 */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL0 */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA0 */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL0 */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_4 /* DMIC_CLK */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_9_7 /* DMIC_IN */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_5 /* SPIP_CS1 & I2S_SYNC */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* I2S_SCLK/PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_0 /* I2S_DATA */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB7SDA0 */ \ + NPCX_ALT_GPIO_B_3 /* SMB7SCL0 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_1 /* SMB6SDA0 */ \ + NPCX_ALT_GPIO_C_2 /* SMB6SCL0 & PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA0 */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL0 */ \ + NPCX_ALT_GPIO_D_2 /* PSL_IN1 */ \ + NPCX_ALT_GPIO_E_1 /* ADC7 */ \ + NPCX_ALT_GPIO_E_3 /* SMB6SDA1 */ \ + NPCX_ALT_GPIO_E_4 /* SMB6SCL1 */ \ + NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ + NPCX_ALT_GPIO_F_0 /* ADC9 */ \ + NPCX_ALT_GPIO_F_1 /* ADC8 */ \ + NPCX_ALT_GPIO_F_2 /* SMB4SDA1 */ \ + NPCX_ALT_GPIO_F_3 /* SMB4SCL1 */ \ + NPCX_ALT_GPIO_F_4 /* SMB5SDA1 */ \ + NPCX_ALT_GPIO_F_5 /* SMB5SCL1 */ \ } /*****************************************************************************/ @@ -491,8 +495,9 @@ #define NPCX_LVOL_CTRL_2_4 NPCX_GPIO(C, 1) #define NPCX_LVOL_CTRL_2_5 NPCX_GPIO(C, 7) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_2_6 NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \ - */ +#define NPCX_LVOL_CTRL_2_6 \ + NPCX_GPIO_NONE /* Remove 1.8V support since CLKIN \ + */ #else #define NPCX_LVOL_CTRL_2_6 NPCX_GPIO(E, 7) #endif @@ -503,8 +508,9 @@ #define NPCX_LVOL_CTRL_3_1 NPCX_GPIO(3, 7) #define NPCX_LVOL_CTRL_3_2 NPCX_GPIO(4, 0) #ifdef NPCX_EXT32K_OSC_SUPPORT -#define NPCX_LVOL_CTRL_3_3 NPCX_GPIO_NONE /* Remove 1.8V support since \ - CLKOUT*/ +#define NPCX_LVOL_CTRL_3_3 \ + NPCX_GPIO_NONE /* Remove 1.8V support since \ + CLKOUT*/ #else #define NPCX_LVOL_CTRL_3_3 NPCX_GPIO(7, 1) #endif -- cgit v1.2.1 From e6074b1eedc154f3bf93fbca9675e36dca51b0bc Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:46:02 -0600 Subject: zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I40311932a571aa0ec81f9314e3b6f050f0f1df23 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749528 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index 0e3c59a59b..a9ad3d43c9 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -243,8 +243,9 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) /* TODO(b/237553647): Test EC-driven mode entry (requires a separate * config). */ - host_cmd_typec_control(TEST_PORT, - TYPEC_CONTROL_COMMAND_ENTER_MODE, TYPEC_MODE_DP); k_sleep(K_SECONDS(1)); + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); /* Verify host command when VDOs are present. */ struct ec_params_usb_pd_get_mode_request params = { @@ -306,7 +307,6 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); zassert_equal(response.vdo[0], fixture->partner.modes_vdm[response.opos], NULL); - } ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, -- cgit v1.2.1 From 51ffd5057fcc8214b34de50bc4145e8bd9c3f74d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:44 -0600 Subject: board/delbin/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I71571ce92715d8245f0d4a5f2fea242182bab7b1 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748799 Reviewed-by: Jeremy Bettis --- board/delbin/board.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/board/delbin/board.c b/board/delbin/board.c index a015c87ed7..fe1c3f10ee 100644 --- a/board/delbin/board.c +++ b/board/delbin/board.c @@ -66,21 +66,21 @@ __override struct key { uint8_t row; uint8_t col; } vivaldi_keys[] = { - {.row = 0, .col = 2}, /* T1 */ - {.row = 3, .col = 2}, /* T2 */ - {.row = 2, .col = 2}, /* T3 */ - {.row = 1, .col = 2}, /* T4 */ - {.row = 3, .col = 4}, /* T5 */ - {.row = 2, .col = 4}, /* T6 */ - {.row = 1, .col = 4}, /* T7 */ - {.row = 2, .col = 9}, /* T8 */ - {.row = 1, .col = 9}, /* T9 */ - {.row = 0, .col = 4}, /* T10 */ - {.row = 0, .col = 1}, /* T11 */ - {.row = 1, .col = 5}, /* T12 */ - {.row = 3, .col = 5}, /* T13 */ - {.row = 0, .col = 9}, /* T14 */ - {.row = 0, .col = 11}, /* T15 */ + { .row = 0, .col = 2 }, /* T1 */ + { .row = 3, .col = 2 }, /* T2 */ + { .row = 2, .col = 2 }, /* T3 */ + { .row = 1, .col = 2 }, /* T4 */ + { .row = 3, .col = 4 }, /* T5 */ + { .row = 2, .col = 4 }, /* T6 */ + { .row = 1, .col = 4 }, /* T7 */ + { .row = 2, .col = 9 }, /* T8 */ + { .row = 1, .col = 9 }, /* T9 */ + { .row = 0, .col = 4 }, /* T10 */ + { .row = 0, .col = 1 }, /* T11 */ + { .row = 1, .col = 5 }, /* T12 */ + { .row = 3, .col = 5 }, /* T13 */ + { .row = 0, .col = 9 }, /* T14 */ + { .row = 0, .col = 11 }, /* T15 */ }; BUILD_ASSERT(ARRAY_SIZE(vivaldi_keys) == MAX_TOP_ROW_KEYS); -- cgit v1.2.1 From 9c181fc5fcb2426706308b7b579099d72e55dec0 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:12 -0600 Subject: board/drawcia_riscv/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I9d5343b4173a93ffe1fe9e018a26cf9c94bb01bb Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749378 Reviewed-by: Jeremy Bettis --- board/drawcia_riscv/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/drawcia_riscv/board.h b/board/drawcia_riscv/board.h index 921d2e066e..5bede28048 100644 --- a/board/drawcia_riscv/board.h +++ b/board/drawcia_riscv/board.h @@ -43,8 +43,9 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr \ + */ /* PWM */ #define CONFIG_PWM -- cgit v1.2.1 From 251c8c0b3da82030b2933c886fd0291b83e0a422 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:08 -0600 Subject: include/task_id.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Icadc80943da12a1d0bf49a4436e48fa9c3fabb19 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749519 Reviewed-by: Jeremy Bettis --- include/task_id.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/task_id.h b/include/task_id.h index 2cb57b59b3..431a1a9974 100644 --- a/include/task_id.h +++ b/include/task_id.h @@ -48,11 +48,11 @@ enum { CONFIG_TASK_LIST /* CONFIG_TEST_TASK_LIST is a macro from the TEST_TASK_LIST file */ - CONFIG_TEST_TASK_LIST - /* For CTS tasks */ - CONFIG_CTS_TASK_LIST + CONFIG_TEST_TASK_LIST + /* For CTS tasks */ + CONFIG_CTS_TASK_LIST #ifdef EMU_BUILD - TASK_ID_TEST_RUNNER, + TASK_ID_TEST_RUNNER, #endif /* Number of tasks */ TASK_ID_COUNT, -- cgit v1.2.1 From f5f9c8819f9ade8a885b80e9c06e197ccb62d66d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:54 -0600 Subject: board/servo_v4/usb_pd_config.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ice808816780fbf197a0ab9dcb671842e306ae373 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749419 Reviewed-by: Jeremy Bettis --- board/servo_v4/usb_pd_config.h | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/board/servo_v4/usb_pd_config.h b/board/servo_v4/usb_pd_config.h index 4b42bd6c29..aa4e150645 100644 --- a/board/servo_v4/usb_pd_config.h +++ b/board/servo_v4/usb_pd_config.h @@ -193,23 +193,25 @@ static inline void pd_select_polarity(int port, int polarity) if (port == 0) { /* CHG use the right comparator inverted input for COMP2 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) | - (polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: - C0_CC2 - */ - : - STM32_COMP_CMP2INSEL_INM6); /* PA2: - C0_CC1 - */ + (polarity ? + STM32_COMP_CMP2INSEL_INM4 /* PA4: + C0_CC2 + */ + : + STM32_COMP_CMP2INSEL_INM6); /* PA2: + C0_CC1 + */ } else { /* DUT use the right comparator inverted input for COMP1 */ STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) | - (polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: - C1_CC2 - */ - : - STM32_COMP_CMP1INSEL_INM6); /* PA0: - C1_CC1 - */ + (polarity ? + STM32_COMP_CMP1INSEL_INM5 /* PA5: + C1_CC2 + */ + : + STM32_COMP_CMP1INSEL_INM6); /* PA0: + C1_CC1 + */ } } -- cgit v1.2.1 From 030d876ce992a118db08ac66ea48fa65ccf934b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:46 -0600 Subject: chip/max32660/pwrseq_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I9b49beabcc3114cee29d67177e94a45466b77922 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749433 Reviewed-by: Jeremy Bettis --- chip/max32660/pwrseq_regs.h | 59 ++++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h index e84c814ef4..77971adabc 100644 --- a/chip/max32660/pwrseq_regs.h +++ b/chip/max32660/pwrseq_regs.h @@ -171,25 +171,28 @@ typedef struct { Mask */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_0_9V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_0_9V \ + Setting \ + */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_1_0V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_0V \ + Setting \ + */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_1_1V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_1V \ + Setting \ + */ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ @@ -378,12 +381,13 @@ typedef struct { * Low Power Mode Wakeup Flags for GPIO0 */ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ -#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ - ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ - LP_WAKEFL_WAKEST \ - \ \ - \ \ \ Mask \ - */ +#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ + LP_WAKEFL_WAKEST \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers @@ -391,12 +395,13 @@ typedef struct { * power wakeup functionality for GPIO0. */ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ -#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ - ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ - LPWK_EN_WAKEEN \ - \ \ - \ \ \ Mask \ - */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ + LPWK_EN_WAKEEN \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers -- cgit v1.2.1 From c9a76aa00b2447b50177068de26bf3cc3198ce6b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:32 -0600 Subject: board/corori2/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I5add6129c30e9f7b58e237054e06c87edb21319f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748797 Reviewed-by: Jeremy Bettis --- board/corori2/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/corori2/board.h b/board/corori2/board.h index 5ed39cf531..062ff4237e 100644 --- a/board/corori2/board.h +++ b/board/corori2/board.h @@ -37,8 +37,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE -- cgit v1.2.1 From 20c21fc4db6a51bbf69ade1da3a16c52973db480 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:28 -0600 Subject: board/coffeecake/usb_pd_policy.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I4b8f837e1cd4e0fa8230f1f3aea5ed0709d39b0d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748796 Reviewed-by: Jeremy Bettis --- board/coffeecake/usb_pd_policy.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/coffeecake/usb_pd_policy.c b/board/coffeecake/usb_pd_policy.c index aac1c9c45e..60ddf6240a 100644 --- a/board/coffeecake/usb_pd_policy.c +++ b/board/coffeecake/usb_pd_policy.c @@ -192,9 +192,10 @@ static int dp_status(int port, uint32_t *payload) 0, /* request exit DP */ 0, /* request exit USB */ 0, /* MF pref */ - gpio_get_level(GPIO_PD_SBU_ENABLE), 0, /* power - low - */ + gpio_get_level(GPIO_PD_SBU_ENABLE), + 0, /* power + low + */ 0x2); return 2; } -- cgit v1.2.1 From 2a8141fd97c0a03ddb8e70fa0f9b3dc8cb488ae6 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:41:21 -0600 Subject: board/magolor/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I08a8eeddbc4ef95621f714a9b5abf877b3ad202a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749392 Reviewed-by: Jeremy Bettis --- board/magolor/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/magolor/board.h b/board/magolor/board.h index afb30f3ad8..2e36b814c3 100644 --- a/board/magolor/board.h +++ b/board/magolor/board.h @@ -36,8 +36,9 @@ #define CONFIG_CHARGER_RAA489000 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 #define CONFIG_CHARGER_SENSE_RESISTOR 10 -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #define CONFIG_OCPC #undef CONFIG_CHARGER_SINGLE_CHIP #undef CONFIG_CMD_CHARGER_DUMP -- cgit v1.2.1 From b90de010a6107ac14a5841134480b2996c2fc3db Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:37 -0600 Subject: util/uut/l_com_port.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic03096cc17f9ba724863161b1c2296be8d85b8a9 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749524 Reviewed-by: Jeremy Bettis --- util/uut/l_com_port.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/util/uut/l_com_port.c b/util/uut/l_com_port.c index 448ffc1ac7..231d47cc04 100644 --- a/util/uut/l_com_port.c +++ b/util/uut/l_com_port.c @@ -177,9 +177,10 @@ bool com_config_uart(int h_dev_drv, struct comport_fields com_port_fields) tty.c_cc[VMIN] = 0; /* read doesn't block */ tty.c_cc[VTIME] = 5; /* 0.5 seconds read timeout */ - tty.c_iflag |= (com_port_fields.flow_control == 0x01) ? (IXON | IXOFF) : - 0x00; /* xon/xoff - ctrl */ + tty.c_iflag |= (com_port_fields.flow_control == 0x01) ? + (IXON | IXOFF) : + 0x00; /* xon/xoff + ctrl */ tty.c_cflag |= (CLOCAL | CREAD); /* ignore modem controls */ /* enable reading */ -- cgit v1.2.1 From 85e6cefcf815eed9a05b5985a06ba51845d0cd4b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:54 -0600 Subject: chip/max32660/uart_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I0dd604a8b62416a5b57708f9656bbbf9fd2b2e6a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749435 Reviewed-by: Jeremy Bettis --- chip/max32660/uart_regs.h | 348 +++++++++++++++++++++++++--------------------- 1 file changed, 190 insertions(+), 158 deletions(-) diff --git a/chip/max32660/uart_regs.h b/chip/max32660/uart_regs.h index d5e9f9bf0d..dd3c3c3bb6 100644 --- a/chip/max32660/uart_regs.h +++ b/chip/max32660/uart_regs.h @@ -88,19 +88,21 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_ENABLE_DIS \ ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ -#define MXC_S_UART_CTRL_ENABLE_DIS \ - (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< \ - CTRL_ENABLE_DIS \ - Setting \ - */ +#define MXC_S_UART_CTRL_ENABLE_DIS \ + (MXC_V_UART_CTRL_ENABLE_DIS \ + << MXC_F_UART_CTRL_ENABLE_POS) /**< \ + CTRL_ENABLE_DIS \ + Setting \ + */ #define MXC_V_UART_CTRL_ENABLE_EN \ ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value \ */ -#define MXC_S_UART_CTRL_ENABLE_EN \ - (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< \ - CTRL_ENABLE_EN \ - Setting \ - */ +#define MXC_S_UART_CTRL_ENABLE_EN \ + (MXC_V_UART_CTRL_ENABLE_EN \ + << MXC_F_UART_CTRL_ENABLE_POS) /**< \ + CTRL_ENABLE_EN \ + Setting \ + */ #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ #define MXC_F_UART_CTRL_PARITY_EN \ @@ -109,18 +111,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_PARITY_EN_DIS \ ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ -#define MXC_S_UART_CTRL_PARITY_EN_DIS \ - (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ - CTRL_PARITY_EN_DIS \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_EN_DIS \ + (MXC_V_UART_CTRL_PARITY_EN_DIS \ + << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ + CTRL_PARITY_EN_DIS \ + Setting \ + */ #define MXC_V_UART_CTRL_PARITY_EN_EN \ ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ -#define MXC_S_UART_CTRL_PARITY_EN_EN \ - (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ - CTRL_PARITY_EN_EN \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_EN_EN \ + (MXC_V_UART_CTRL_PARITY_EN_EN \ + << MXC_F_UART_CTRL_PARITY_EN_POS) /**< \ + CTRL_PARITY_EN_EN \ + Setting \ + */ #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ #define MXC_F_UART_CTRL_PARITY \ @@ -128,32 +132,36 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_PARITY_EVEN \ ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ -#define MXC_S_UART_CTRL_PARITY_EVEN \ - (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< \ - CTRL_PARITY_EVEN \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_EVEN \ + (MXC_V_UART_CTRL_PARITY_EVEN \ + << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_EVEN \ + Setting \ + */ #define MXC_V_UART_CTRL_PARITY_ODD \ ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ -#define MXC_S_UART_CTRL_PARITY_ODD \ - (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< \ - CTRL_PARITY_ODD \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_ODD \ + (MXC_V_UART_CTRL_PARITY_ODD \ + << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_ODD \ + Setting \ + */ #define MXC_V_UART_CTRL_PARITY_MARK \ ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ -#define MXC_S_UART_CTRL_PARITY_MARK \ - (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< \ - CTRL_PARITY_MARK \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_MARK \ + (MXC_V_UART_CTRL_PARITY_MARK \ + << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_MARK \ + Setting \ + */ #define MXC_V_UART_CTRL_PARITY_SPACE \ ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ -#define MXC_S_UART_CTRL_PARITY_SPACE \ - (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< \ - CTRL_PARITY_SPACE \ - Setting \ - */ +#define MXC_S_UART_CTRL_PARITY_SPACE \ + (MXC_V_UART_CTRL_PARITY_SPACE \ + << MXC_F_UART_CTRL_PARITY_POS) /**< \ + CTRL_PARITY_SPACE \ + Setting \ + */ #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ #define MXC_F_UART_CTRL_PARMD \ @@ -186,18 +194,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_BITACC_FRAME \ ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ -#define MXC_S_UART_CTRL_BITACC_FRAME \ - (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< \ - CTRL_BITACC_FRAME \ - Setting \ - */ +#define MXC_S_UART_CTRL_BITACC_FRAME \ + (MXC_V_UART_CTRL_BITACC_FRAME \ + << MXC_F_UART_CTRL_BITACC_POS) /**< \ + CTRL_BITACC_FRAME \ + Setting \ + */ #define MXC_V_UART_CTRL_BITACC_BIT \ ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ -#define MXC_S_UART_CTRL_BITACC_BIT \ - (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< \ - CTRL_BITACC_BIT \ - Setting \ - */ +#define MXC_S_UART_CTRL_BITACC_BIT \ + (MXC_V_UART_CTRL_BITACC_BIT \ + << MXC_F_UART_CTRL_BITACC_POS) /**< \ + CTRL_BITACC_BIT \ + Setting \ + */ #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ #define MXC_F_UART_CTRL_CHAR_SIZE \ @@ -206,32 +216,36 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_CHAR_SIZE_5 \ ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_5 \ - (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ - CTRL_CHAR_SIZE_5 \ - Setting \ - */ +#define MXC_S_UART_CTRL_CHAR_SIZE_5 \ + (MXC_V_UART_CTRL_CHAR_SIZE_5 \ + << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_5 \ + Setting \ + */ #define MXC_V_UART_CTRL_CHAR_SIZE_6 \ ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_6 \ - (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ - CTRL_CHAR_SIZE_6 \ - Setting \ - */ +#define MXC_S_UART_CTRL_CHAR_SIZE_6 \ + (MXC_V_UART_CTRL_CHAR_SIZE_6 \ + << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_6 \ + Setting \ + */ #define MXC_V_UART_CTRL_CHAR_SIZE_7 \ ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_7 \ - (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ - CTRL_CHAR_SIZE_7 \ - Setting \ - */ +#define MXC_S_UART_CTRL_CHAR_SIZE_7 \ + (MXC_V_UART_CTRL_CHAR_SIZE_7 \ + << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_7 \ + Setting \ + */ #define MXC_V_UART_CTRL_CHAR_SIZE_8 \ ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ -#define MXC_S_UART_CTRL_CHAR_SIZE_8 \ - (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ - CTRL_CHAR_SIZE_8 \ - Setting \ - */ +#define MXC_S_UART_CTRL_CHAR_SIZE_8 \ + (MXC_V_UART_CTRL_CHAR_SIZE_8 \ + << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< \ + CTRL_CHAR_SIZE_8 \ + Setting \ + */ #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ #define MXC_F_UART_CTRL_STOPBITS \ @@ -239,18 +253,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_STOPBITS_1 \ ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1 \ - (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ - CTRL_STOPBITS_1 \ - Setting \ - */ +#define MXC_S_UART_CTRL_STOPBITS_1 \ + (MXC_V_UART_CTRL_STOPBITS_1 \ + << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ + CTRL_STOPBITS_1 \ + Setting \ + */ #define MXC_V_UART_CTRL_STOPBITS_1_5 \ ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ -#define MXC_S_UART_CTRL_STOPBITS_1_5 \ - (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ - CTRL_STOPBITS_1_5 \ - Setting \ - */ +#define MXC_S_UART_CTRL_STOPBITS_1_5 \ + (MXC_V_UART_CTRL_STOPBITS_1_5 \ + << MXC_F_UART_CTRL_STOPBITS_POS) /**< \ + CTRL_STOPBITS_1_5 \ + Setting \ + */ #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ #define MXC_F_UART_CTRL_FLOW_CTRL \ @@ -259,18 +275,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_FLOW_CTRL_EN \ ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_EN \ - (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ - CTRL_FLOW_CTRL_EN \ - Setting \ - */ +#define MXC_S_UART_CTRL_FLOW_CTRL_EN \ + (MXC_V_UART_CTRL_FLOW_CTRL_EN \ + << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ + CTRL_FLOW_CTRL_EN \ + Setting \ + */ #define MXC_V_UART_CTRL_FLOW_CTRL_DIS \ ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ -#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \ - (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ - CTRL_FLOW_CTRL_DIS \ - Setting \ - */ +#define MXC_S_UART_CTRL_FLOW_CTRL_DIS \ + (MXC_V_UART_CTRL_FLOW_CTRL_DIS \ + << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< \ + CTRL_FLOW_CTRL_DIS \ + Setting \ + */ #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ #define MXC_F_UART_CTRL_FLOW_POL \ @@ -278,18 +296,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_FLOW_POL_0 \ ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_0 \ - (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ - CTRL_FLOW_POL_0 \ - Setting \ - */ +#define MXC_S_UART_CTRL_FLOW_POL_0 \ + (MXC_V_UART_CTRL_FLOW_POL_0 \ + << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ + CTRL_FLOW_POL_0 \ + Setting \ + */ #define MXC_V_UART_CTRL_FLOW_POL_1 \ ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ -#define MXC_S_UART_CTRL_FLOW_POL_1 \ - (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ - CTRL_FLOW_POL_1 \ - Setting \ - */ +#define MXC_S_UART_CTRL_FLOW_POL_1 \ + (MXC_V_UART_CTRL_FLOW_POL_1 \ + << MXC_F_UART_CTRL_FLOW_POL_POS) /**< \ + CTRL_FLOW_POL_1 \ + Setting \ + */ #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ #define MXC_F_UART_CTRL_NULL_MODEM \ @@ -315,15 +335,17 @@ typedef struct { #define MXC_V_UART_CTRL_BREAK_DIS \ ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value \ */ -#define MXC_S_UART_CTRL_BREAK_DIS \ - (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< \ - CTRL_BREAK_DIS \ - Setting */ +#define MXC_S_UART_CTRL_BREAK_DIS \ + (MXC_V_UART_CTRL_BREAK_DIS \ + << MXC_F_UART_CTRL_BREAK_POS) /**< \ + CTRL_BREAK_DIS \ + Setting */ #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ -#define MXC_S_UART_CTRL_BREAK_EN \ - (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< \ - CTRL_BREAK_EN \ - Setting */ +#define MXC_S_UART_CTRL_BREAK_EN \ + (MXC_V_UART_CTRL_BREAK_EN \ + << MXC_F_UART_CTRL_BREAK_POS) /**< \ + CTRL_BREAK_EN \ + Setting */ #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ #define MXC_F_UART_CTRL_CLKSEL \ @@ -331,18 +353,20 @@ typedef struct { Mask */ #define MXC_V_UART_CTRL_CLKSEL_SYSTEM \ ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ -#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \ - (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ - CTRL_CLKSEL_SYSTEM \ - Setting \ - */ +#define MXC_S_UART_CTRL_CLKSEL_SYSTEM \ + (MXC_V_UART_CTRL_CLKSEL_SYSTEM \ + << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ + CTRL_CLKSEL_SYSTEM \ + Setting \ + */ #define MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ -#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \ - (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ - CTRL_CLKSEL_ALTERNATE \ - Setting \ - */ +#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE \ + (MXC_V_UART_CTRL_CLKSEL_ALTERNATE \ + << MXC_F_UART_CTRL_CLKSEL_POS) /**< \ + CTRL_CLKSEL_ALTERNATE \ + Setting \ + */ #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ #define MXC_F_UART_CTRL_RX_TO \ @@ -614,32 +638,36 @@ typedef struct { Mask */ #define MXC_V_UART_BAUD0_FACTOR_128 \ ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ -#define MXC_S_UART_BAUD0_FACTOR_128 \ - (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ - BAUD0_FACTOR_128 \ - Setting \ - */ +#define MXC_S_UART_BAUD0_FACTOR_128 \ + (MXC_V_UART_BAUD0_FACTOR_128 \ + << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_128 \ + Setting \ + */ #define MXC_V_UART_BAUD0_FACTOR_64 \ ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ -#define MXC_S_UART_BAUD0_FACTOR_64 \ - (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ - BAUD0_FACTOR_64 \ - Setting \ - */ +#define MXC_S_UART_BAUD0_FACTOR_64 \ + (MXC_V_UART_BAUD0_FACTOR_64 \ + << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_64 \ + Setting \ + */ #define MXC_V_UART_BAUD0_FACTOR_32 \ ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ -#define MXC_S_UART_BAUD0_FACTOR_32 \ - (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ - BAUD0_FACTOR_32 \ - Setting \ - */ +#define MXC_S_UART_BAUD0_FACTOR_32 \ + (MXC_V_UART_BAUD0_FACTOR_32 \ + << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_32 \ + Setting \ + */ #define MXC_V_UART_BAUD0_FACTOR_16 \ ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ -#define MXC_S_UART_BAUD0_FACTOR_16 \ - (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ - BAUD0_FACTOR_16 \ - Setting \ - */ +#define MXC_S_UART_BAUD0_FACTOR_16 \ + (MXC_V_UART_BAUD0_FACTOR_16 \ + << MXC_F_UART_BAUD0_FACTOR_POS) /**< \ + BAUD0_FACTOR_16 \ + Setting \ + */ /** * Baud rate register. Decimal Setting. @@ -666,19 +694,21 @@ typedef struct { Mask */ #define MXC_V_UART_DMA_TDMA_EN_DIS \ ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_TDMA_EN_DIS \ - (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ - DMA_TDMA_EN_DIS \ - Setting \ - */ +#define MXC_S_UART_DMA_TDMA_EN_DIS \ + (MXC_V_UART_DMA_TDMA_EN_DIS \ + << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ + DMA_TDMA_EN_DIS \ + Setting \ + */ #define MXC_V_UART_DMA_TDMA_EN_EN \ ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value \ */ -#define MXC_S_UART_DMA_TDMA_EN_EN \ - (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ - DMA_TDMA_EN_EN \ - Setting \ - */ +#define MXC_S_UART_DMA_TDMA_EN_EN \ + (MXC_V_UART_DMA_TDMA_EN_EN \ + << MXC_F_UART_DMA_TDMA_EN_POS) /**< \ + DMA_TDMA_EN_EN \ + Setting \ + */ #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ #define MXC_F_UART_DMA_RXDMA_EN \ @@ -686,18 +716,20 @@ typedef struct { Mask */ #define MXC_V_UART_DMA_RXDMA_EN_DIS \ ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ -#define MXC_S_UART_DMA_RXDMA_EN_DIS \ - (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ - DMA_RXDMA_EN_DIS \ - Setting \ - */ +#define MXC_S_UART_DMA_RXDMA_EN_DIS \ + (MXC_V_UART_DMA_RXDMA_EN_DIS \ + << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ + DMA_RXDMA_EN_DIS \ + Setting \ + */ #define MXC_V_UART_DMA_RXDMA_EN_EN \ ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ -#define MXC_S_UART_DMA_RXDMA_EN_EN \ - (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ - DMA_RXDMA_EN_EN \ - Setting \ - */ +#define MXC_S_UART_DMA_RXDMA_EN_EN \ + (MXC_V_UART_DMA_RXDMA_EN_EN \ + << MXC_F_UART_DMA_RXDMA_EN_POS) /**< \ + DMA_RXDMA_EN_EN \ + Setting \ + */ #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ #define MXC_F_UART_DMA_TXDMA_LEVEL \ -- cgit v1.2.1 From c5e6696f08bf08d1d5c96bc1b5caae629b2ef2a5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:02 -0600 Subject: chip/npcx/gpio_chip-npcx5.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Id46ebca41fb1bd943277f5b037eefe2cfb45a804 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749457 Reviewed-by: Jeremy Bettis --- chip/npcx/gpio_chip-npcx5.h | 142 ++++++++++++++++++++++---------------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/chip/npcx/gpio_chip-npcx5.h b/chip/npcx/gpio_chip-npcx5.h index 5d6170affa..7335c902b1 100644 --- a/chip/npcx/gpio_chip-npcx5.h +++ b/chip/npcx/gpio_chip-npcx5.h @@ -261,77 +261,77 @@ #define NPCX_ALT_GPIO_A_7 #endif -#define NPCX_ALT_TABLE \ - { \ - NPCX_ALT_GPIO_0_3 /* KSO16 */ \ - NPCX_ALT_GPIO_0_4 /* KSO13 */ \ - NPCX_ALT_GPIO_0_5 /* KSO12 */ \ - NPCX_ALT_GPIO_0_6 /* KSO11 */ \ - NPCX_ALT_GPIO_0_7 /* KSO10 */ \ - NPCX_ALT_GPIO_1_0 /* KSO09 \ - & CR_SOUT */ \ - NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SIN */ \ - NPCX_ALT_GPIO_1_2 /* KSO07 */ \ - NPCX_ALT_GPIO_1_3 /* KSO06 */ \ - NPCX_ALT_GPIO_1_4 /* KSO05 */ \ - NPCX_ALT_GPIO_1_5 /* KSO04 */ \ - NPCX_ALT_GPIO_1_6 /* KSO03 */ \ - NPCX_ALT_GPIO_1_7 /* KSO02 */ \ - NPCX_ALT_GPIO_2_0 /* KSO01 */ \ - NPCX_ALT_GPIO_2_1 /* KSO00 */ \ - NPCX_ALT_GPIO_2_2 /* KSI7 */ \ - NPCX_ALT_GPIO_2_3 /* KSI6 */ \ - NPCX_ALT_GPIO_2_4 /* KSI5 */ \ - NPCX_ALT_GPIO_2_5 /* KSI4 */ \ - NPCX_ALT_GPIO_2_6 /* KSI3 */ \ - NPCX_ALT_GPIO_2_7 /* KSI2 */ \ - NPCX_ALT_GPIO_3_0 /* KSI1 */ \ - NPCX_ALT_GPIO_3_1 /* KSI0 */ \ - NPCX_ALT_GPIO_3_4 /* PS2_DAT2 */ \ - NPCX_ALT_GPIO_3_7 /* PS2_CLK2 */ \ - NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ - NPCX_ALT_GPIO_4_1 /* ADC4 */ \ - NPCX_ALT_GPIO_4_2 /* ADC3 */ \ - NPCX_ALT_GPIO_4_4 /* ADC1 */ \ - NPCX_ALT_GPIO_4_5 /* ADC0 */ \ - NPCX_ALT_GPIO_4_3 /* ADC2 */ \ - NPCX_ALT_GPIO_6_0 /* PWM7 */ \ - NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ - NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ - NPCX_ALT_GPIO_6_4 /* CR_SIN2 */ \ - NPCX_ALT_GPIO_6_5 /* CR_SOUT2 */ \ - NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ - NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ - NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ - NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */ \ - NPCX_ALT_GPIO_8_0 /* PWM3 */ \ - NPCX_ALT_GPIO_8_2 /* KSO14 */ \ - NPCX_ALT_GPIO_8_3 /* KSO15 */ \ - NPCX_ALT_GPIO_8_7 /* SMB1SDA */ \ - NPCX_ALT_GPIO_9_0 /* SMB1SCL */ \ - NPCX_ALT_GPIO_9_1 /* SMB2SDA */ \ - NPCX_ALT_GPIO_9_2 /* SMB2SCL */ \ - NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ - NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ - NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ - NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ - NPCX_ALT_GPIO_A_5 /* SPIP_CS1 */ \ - NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ - NPCX_ALT_GPIO_A_7 /* PS2_DAT3 */ \ - NPCX_ALT_GPIO_B_1 /* KSO17 */ \ - NPCX_ALT_GPIO_B_2 /* SMB0SDA1 */ \ - NPCX_ALT_GPIO_B_3 /* SMB0SCL1 */ \ - NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ - NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ - NPCX_ALT_GPIO_B_6 /* PWM4 */ \ - NPCX_ALT_GPIO_B_7 /* PWM5 */ \ - NPCX_ALT_GPIO_C_0 /* PWM6 */ \ - NPCX_ALT_GPIO_C_2 /* PWM1 */ \ - NPCX_ALT_GPIO_C_3 /* PWM0 */ \ - NPCX_ALT_GPIO_C_4 /* PWM2 */ \ - NPCX_ALT_GPIO_D_0 /* SMB3SDA */ \ - NPCX_ALT_GPIO_D_1 /* SMB3SCL */ \ - NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ +#define NPCX_ALT_TABLE \ + { \ + NPCX_ALT_GPIO_0_3 /* KSO16 */ \ + NPCX_ALT_GPIO_0_4 /* KSO13 */ \ + NPCX_ALT_GPIO_0_5 /* KSO12 */ \ + NPCX_ALT_GPIO_0_6 /* KSO11 */ \ + NPCX_ALT_GPIO_0_7 /* KSO10 */ \ + NPCX_ALT_GPIO_1_0 /* KSO09 \ + & CR_SOUT */ \ + NPCX_ALT_GPIO_1_1 /* KSO08 & CR_SIN */ \ + NPCX_ALT_GPIO_1_2 /* KSO07 */ \ + NPCX_ALT_GPIO_1_3 /* KSO06 */ \ + NPCX_ALT_GPIO_1_4 /* KSO05 */ \ + NPCX_ALT_GPIO_1_5 /* KSO04 */ \ + NPCX_ALT_GPIO_1_6 /* KSO03 */ \ + NPCX_ALT_GPIO_1_7 /* KSO02 */ \ + NPCX_ALT_GPIO_2_0 /* KSO01 */ \ + NPCX_ALT_GPIO_2_1 /* KSO00 */ \ + NPCX_ALT_GPIO_2_2 /* KSI7 */ \ + NPCX_ALT_GPIO_2_3 /* KSI6 */ \ + NPCX_ALT_GPIO_2_4 /* KSI5 */ \ + NPCX_ALT_GPIO_2_5 /* KSI4 */ \ + NPCX_ALT_GPIO_2_6 /* KSI3 */ \ + NPCX_ALT_GPIO_2_7 /* KSI2 */ \ + NPCX_ALT_GPIO_3_0 /* KSI1 */ \ + NPCX_ALT_GPIO_3_1 /* KSI0 */ \ + NPCX_ALT_GPIO_3_4 /* PS2_DAT2 */ \ + NPCX_ALT_GPIO_3_7 /* PS2_CLK2 */ \ + NPCX_ALT_GPIO_4_0 /* TA1_SEL1 */ \ + NPCX_ALT_GPIO_4_1 /* ADC4 */ \ + NPCX_ALT_GPIO_4_2 /* ADC3 */ \ + NPCX_ALT_GPIO_4_4 /* ADC1 */ \ + NPCX_ALT_GPIO_4_5 /* ADC0 */ \ + NPCX_ALT_GPIO_4_3 /* ADC2 */ \ + NPCX_ALT_GPIO_6_0 /* PWM7 */ \ + NPCX_ALT_GPIO_6_2 /* PS2_CLK1 */ \ + NPCX_ALT_GPIO_6_3 /* PS2_DAT1 */ \ + NPCX_ALT_GPIO_6_4 /* CR_SIN2 */ \ + NPCX_ALT_GPIO_6_5 /* CR_SOUT2 */ \ + NPCX_ALT_GPIO_6_7 /* PS2_CLK0 */ \ + NPCX_ALT_GPIO_7_0 /* PS2_DAT0 */ \ + NPCX_ALT_GPIO_7_3 /* TA2_SEL1 */ \ + NPCX_ALT_GPIO_7_5 /* 32KHZ_OUT */ \ + NPCX_ALT_GPIO_8_0 /* PWM3 */ \ + NPCX_ALT_GPIO_8_2 /* KSO14 */ \ + NPCX_ALT_GPIO_8_3 /* KSO15 */ \ + NPCX_ALT_GPIO_8_7 /* SMB1SDA */ \ + NPCX_ALT_GPIO_9_0 /* SMB1SCL */ \ + NPCX_ALT_GPIO_9_1 /* SMB2SDA */ \ + NPCX_ALT_GPIO_9_2 /* SMB2SCL */ \ + NPCX_ALT_GPIO_9_3 /* TA1_SEL2 */ \ + NPCX_ALT_GPIO_9_5 /* SPIP_MISO */ \ + NPCX_ALT_GPIO_A_1 /* SPIP_SCLK */ \ + NPCX_ALT_GPIO_A_3 /* SPIP_MOSI */ \ + NPCX_ALT_GPIO_A_5 /* SPIP_CS1 */ \ + NPCX_ALT_GPIO_A_6 /* TA2_SEL2/PS2_CLK3 */ \ + NPCX_ALT_GPIO_A_7 /* PS2_DAT3 */ \ + NPCX_ALT_GPIO_B_1 /* KSO17 */ \ + NPCX_ALT_GPIO_B_2 /* SMB0SDA1 */ \ + NPCX_ALT_GPIO_B_3 /* SMB0SCL1 */ \ + NPCX_ALT_GPIO_B_4 /* SMB0SDA0 */ \ + NPCX_ALT_GPIO_B_5 /* SMB0SCL0 */ \ + NPCX_ALT_GPIO_B_6 /* PWM4 */ \ + NPCX_ALT_GPIO_B_7 /* PWM5 */ \ + NPCX_ALT_GPIO_C_0 /* PWM6 */ \ + NPCX_ALT_GPIO_C_2 /* PWM1 */ \ + NPCX_ALT_GPIO_C_3 /* PWM0 */ \ + NPCX_ALT_GPIO_C_4 /* PWM2 */ \ + NPCX_ALT_GPIO_D_0 /* SMB3SDA */ \ + NPCX_ALT_GPIO_D_1 /* SMB3SCL */ \ + NPCX_ALT_GPIO_E_7 /* 32KCLKIN */ \ } /*****************************************************************************/ -- cgit v1.2.1 From 18f80aeb6f1ea27be3439e6ea964b4f5b4997616 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:40:16 -0600 Subject: board/galtic/board.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Icbc347a2f9aeb84608ccd416931676b15cee4136 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749379 Reviewed-by: Jeremy Bettis --- board/galtic/board.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/galtic/board.h b/board/galtic/board.h index 0d482844a3..56259148ac 100644 --- a/board/galtic/board.h +++ b/board/galtic/board.h @@ -27,8 +27,9 @@ #define CONFIG_CHARGER_SENSE_RESISTOR 10 #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ - */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS \ + 22 /* R_DS(on) 11.6mOhm + 10mOhm sns rstr \ + */ #undef CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE #define CONFIG_USB_PD_TCPC_LPM_EXIT_DEBOUNCE (100 * MSEC) -- cgit v1.2.1 From c426eac8c09f59a0e594c636c4178ff3f5b21dce Mon Sep 17 00:00:00 2001 From: lschyi Date: Wed, 6 Jul 2022 17:00:31 +0800 Subject: krabby: convert LED implementation into DTS Convert and adapt LED implementation in Krabby in to DTS. BUG=b:236796813 TEST=use `battfake` in EC console, set battery to different level and check LED behavior matches to the DTS settings. BRANCH=none Signed-off-by: lschyi Change-Id: I39be060c4fe0c7a3a46a2cfe6fc528cb2ce0896c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748016 Reviewed-by: Ting Shen Commit-Queue: Sung-Chi Li Reviewed-by: Eric Yilun Lin Tested-by: Sung-Chi Li --- zephyr/projects/corsola/CMakeLists.txt | 2 - zephyr/projects/corsola/led_krabby.dts | 131 ++++++++++++++++++++- zephyr/projects/corsola/prj_it81202_base.conf | 1 + zephyr/projects/corsola/src/krabby/led.c | 157 -------------------------- 4 files changed, 131 insertions(+), 160 deletions(-) delete mode 100644 zephyr/projects/corsola/src/krabby/led.c diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt index d9abeaca4d..4aec794c79 100644 --- a/zephyr/projects/corsola/CMakeLists.txt +++ b/zephyr/projects/corsola/CMakeLists.txt @@ -24,8 +24,6 @@ if(DEFINED CONFIG_BOARD_KRABBY) zephyr_library_sources("src/krabby/hooks.c" "src/krabby/charger_workaround.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON - "src/krabby/led.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/krabby/usb_pd_policy.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC diff --git a/zephyr/projects/corsola/led_krabby.dts b/zephyr/projects/corsola/led_krabby.dts index 9ee879b404..6cad04aace 100644 --- a/zephyr/projects/corsola/led_krabby.dts +++ b/zephyr/projects/corsola/led_krabby.dts @@ -2,21 +2,150 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include / { + led-colors { + compatible = "cros-ec,led-colors"; + + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + bat-power-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + + bat-power-state-discharge-s0-bat-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + batt-lvl = ; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; + + pwr-power-state-off { + color-0 { + led-color = <&color_power_off>; + }; + }; + + pwr-power-state-on { + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_power_white>; + }; + }; + + pwr-power-state-s3 { + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_power_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_power_off>; + period-ms = <3000>; + }; + }; + }; + pwmleds { - compatible = "pwm-leds"; + compatible = "cros-ec,pwm-pin-config"; + /* NOTE: &pwm number needs same with channel number */ led_power_white: ec_led1_odl { + #led-pin-cells = <1>; pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) PWM_POLARITY_INVERTED>; }; led_battery_amber: ec_led2_odl { + #led-pin-cells = <1>; pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) PWM_POLARITY_INVERTED>; }; led_battery_white: ec_led3_odl { + #led-pin-cells = <1>; pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) PWM_POLARITY_INVERTED>; }; }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + pwm-frequency = <324>; + + color_power_off: color-power-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; + }; + + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 100>; + }; + + color_battery_off: color-battery-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 0>; + }; + + color_battery_amber: color-battery-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 100>, + <&led_battery_white 0>; + }; + + color_battery_white: color-battery-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 100>; + }; + }; }; /* LED1 */ diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf index 34267c423e..7cef734904 100644 --- a/zephyr/projects/corsola/prj_it81202_base.conf +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -40,6 +40,7 @@ CONFIG_PLATFORM_EC_HOST_COMMAND_STATUS=y # LED CONFIG_PLATFORM_EC_LED_COMMON=y +CONFIG_PLATFORM_EC_LED_DT=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 diff --git a/zephyr/projects/corsola/src/krabby/led.c b/zephyr/projects/corsola/src/krabby/led.c deleted file mode 100644 index 0d45105ba0..0000000000 --- a/zephyr/projects/corsola/src/krabby/led.c +++ /dev/null @@ -1,157 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include - -#include "board_led.h" -#include "common.h" -#include "led_common.h" -#include "led_onoff_states.h" -#include "util.h" - -LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); - -/*If we need pwm output in ITE chip power saving mode, then we should set - * frequency <= 324Hz. - */ -#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(324) - -static const struct board_led_pwm_dt_channel board_led_power_white = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); -static const struct board_led_pwm_dt_channel board_led_battery_amber = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_amber)); -static const struct board_led_pwm_dt_channel board_led_battery_white = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_white)); - -__override const int led_charge_lvl_1 = 5; -__override const int led_charge_lvl_2 = 95; - -__override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S3] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 1 * LED_ONE_SEC } }, - [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, - 2 * LED_ONE_SEC }, - { EC_LED_COLOR_AMBER, - 2 * LED_ONE_SEC } }, - }; - -__override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, - [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, - 1 * LED_ONE_SEC }, - { LED_OFF, - 3 * LED_ONE_SEC } }, - [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, - }; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED, -}; - -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, - int percent) -{ - uint32_t pulse_ns; - int rv; - - if (!device_is_ready(ch->dev)) { - LOG_ERR("PWM device %s not ready", ch->dev->name); - return; - } - - pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); - - LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, - percent, pulse_ns); - - rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, - ch->flags); - if (rv) { - LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); - } -} - -__override void led_set_color_battery(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_AMBER: - board_led_pwm_set_duty(&board_led_battery_amber, 100); - board_led_pwm_set_duty(&board_led_battery_white, 0); - break; - case EC_LED_COLOR_WHITE: - board_led_pwm_set_duty(&board_led_battery_amber, 0); - board_led_pwm_set_duty(&board_led_battery_white, 100); - break; - default: - board_led_pwm_set_duty(&board_led_battery_amber, 0); - board_led_pwm_set_duty(&board_led_battery_white, 0); - break; - } -} - -__override void led_set_color_power(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_WHITE: - board_led_pwm_set_duty(&board_led_power_white, 100); - break; - default: - board_led_pwm_set_duty(&board_led_power_white, 0); - break; - } -} - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - brightness_range[EC_LED_COLOR_AMBER] = 1; - brightness_range[EC_LED_COLOR_WHITE] = 1; - } else if (led_id == EC_LED_ID_POWER_LED) { - brightness_range[EC_LED_COLOR_WHITE] = 1; - } -} - -int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - if (brightness[EC_LED_COLOR_AMBER] != 0) { - led_set_color_battery(EC_LED_COLOR_AMBER); - } else if (brightness[EC_LED_COLOR_WHITE] != 0) { - led_set_color_battery(EC_LED_COLOR_WHITE); - } else { - led_set_color_battery(LED_OFF); - } - } else if (led_id == EC_LED_ID_POWER_LED) { - if (brightness[EC_LED_COLOR_WHITE] != 0) { - led_set_color_power(EC_LED_COLOR_WHITE); - } else { - led_set_color_power(LED_OFF); - } - } - - return EC_SUCCESS; -} -- cgit v1.2.1 From c39eac58cfc60e6937eadc4dca1dbdd1762e6410 Mon Sep 17 00:00:00 2001 From: lschyi Date: Wed, 6 Jul 2022 17:15:04 +0800 Subject: tentacruel: extract LED dtsi shared with krabby Tentacruel and krabby shares the same LED DTS settings. Extract these settings as a base dtsi, and covert tentacruel to use DTS to control the LED behavior. BUG=b:236796813 TEST=use `battfake` in EC console, set battery to different level and check LED behavior matches to the DTS settings. BRANCH=none Signed-off-by: lschyi Change-Id: I1e09e5c7d05e91b919a113280c228ebab317b25d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748017 Tested-by: Sung-Chi Li Reviewed-by: Ting Shen Commit-Queue: Sung-Chi Li --- zephyr/projects/corsola/CMakeLists.txt | 2 - zephyr/projects/corsola/led_it81202_base.dtsi | 182 +++++++++++++++++++++ zephyr/projects/corsola/led_krabby.dts | 170 +------------------ zephyr/projects/corsola/led_tentacruel.dts | 76 +++++---- .../projects/corsola/src/krabby/led_tentacruel.c | 181 -------------------- 5 files changed, 225 insertions(+), 386 deletions(-) create mode 100644 zephyr/projects/corsola/led_it81202_base.dtsi delete mode 100644 zephyr/projects/corsola/src/krabby/led_tentacruel.c diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt index 4aec794c79..9cc9bd9451 100644 --- a/zephyr/projects/corsola/CMakeLists.txt +++ b/zephyr/projects/corsola/CMakeLists.txt @@ -54,8 +54,6 @@ elseif(DEFINED CONFIG_BOARD_TENTACRUEL) zephyr_library_sources("src/krabby/hooks.c" "src/krabby/charger_workaround.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C "src/krabby/i2c.c") - zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON - "src/krabby/led_tentacruel.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/krabby/usb_pd_policy.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC diff --git a/zephyr/projects/corsola/led_it81202_base.dtsi b/zephyr/projects/corsola/led_it81202_base.dtsi new file mode 100644 index 0000000000..24a0efd93e --- /dev/null +++ b/zephyr/projects/corsola/led_it81202_base.dtsi @@ -0,0 +1,182 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include + +/ { + led_colors: led-colors { + compatible = "cros-ec,led-colors"; + + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_battery_white>; + }; + }; + + bat-power-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; + + bat-power-state-discharge-s0-bat-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + batt-lvl = ; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; + + pwr-power-state-off { + color-0 { + led-color = <&color_power_off>; + }; + }; + + pwr-power-state-on { + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_power_white>; + }; + }; + + pwr-power-state-s3 { + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_power_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_power_off>; + period-ms = <3000>; + }; + }; + }; + + pwmleds { + compatible = "cros-ec,pwm-pin-config"; + + /* NOTE: &pwm number needs same with channel number */ + led_power_white: ec_led1_odl { + #led-pin-cells = <1>; + pwms = <&pwm0 + PWM_CHANNEL_0 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_amber: ec_led2_odl { + #led-pin-cells = <1>; + pwms = <&pwm1 + PWM_CHANNEL_1 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + led_battery_white: ec_led3_odl { + #led-pin-cells = <1>; + pwms = <&pwm2 + PWM_CHANNEL_2 + PWM_HZ(324) + PWM_POLARITY_INVERTED>; + }; + }; + + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; + pwm-frequency = <324>; + + color_power_off: color-power-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; + }; + + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 100>; + }; + + color_battery_off: color-battery-off { + led-color = "LED_OFF"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 0>; + }; + + color_battery_amber: color-battery-amber { + led-color = "LED_AMBER"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 100>, + <&led_battery_white 0>; + }; + + color_battery_white: color-battery-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&led_battery_amber 0>, + <&led_battery_white 100>; + }; + }; +}; + +/* LED1 */ +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +/* LED2 */ +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +/* LED3 */ +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/corsola/led_krabby.dts b/zephyr/projects/corsola/led_krabby.dts index 6cad04aace..aa7e3a5f7d 100644 --- a/zephyr/projects/corsola/led_krabby.dts +++ b/zephyr/projects/corsola/led_krabby.dts @@ -2,172 +2,4 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -#include - -/ { - led-colors { - compatible = "cros-ec,led-colors"; - - bat-power-state-charge { - charge-state = "PWR_STATE_CHARGE"; - - color-0 { - led-color = <&color_battery_amber>; - }; - }; - - bat-power-state-near-full { - charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; - - color-0 { - led-color = <&color_battery_white>; - }; - }; - - bat-power-state-discharge { - charge-state = "PWR_STATE_DISCHARGE"; - - color-0 { - led-color = <&color_battery_off>; - }; - }; - - bat-power-state-discharge-s0-bat-low { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S0"; - batt-lvl = ; - - color-0 { - led-color = <&color_battery_amber>; - period-ms = <1000>; - }; - - color-1 { - led-color = <&color_battery_off>; - period-ms = <3000>; - }; - }; - - bat-power-state-error { - charge-state = "PWR_STATE_ERROR"; - - color-0 { - led-color = <&color_battery_amber>; - period-ms = <1000>; - }; - - color-1 { - led-color = <&color_battery_off>; - period-ms = <1000>; - }; - }; - - pwr-power-state-off { - color-0 { - led-color = <&color_power_off>; - }; - }; - - pwr-power-state-on { - chipset-state = "POWER_S0"; - - color-0 { - led-color = <&color_power_white>; - }; - }; - - pwr-power-state-s3 { - chipset-state = "POWER_S3"; - - color-0 { - led-color = <&color_power_white>; - period-ms = <1000>; - }; - - color-1 { - led-color = <&color_power_off>; - period-ms = <3000>; - }; - }; - }; - - pwmleds { - compatible = "cros-ec,pwm-pin-config"; - - /* NOTE: &pwm number needs same with channel number */ - led_power_white: ec_led1_odl { - #led-pin-cells = <1>; - pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - led_battery_amber: ec_led2_odl { - #led-pin-cells = <1>; - pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - led_battery_white: ec_led3_odl { - #led-pin-cells = <1>; - pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) PWM_POLARITY_INVERTED>; - }; - }; - - pwm-led-pins { - compatible = "cros-ec,pwm-led-pins"; - pwm-frequency = <324>; - - color_power_off: color-power-off { - led-color = "LED_OFF"; - led-id = "EC_LED_ID_POWER_LED"; - led-pins = <&led_power_white 0>; - }; - - color_power_white: color-power-white { - led-color = "LED_WHITE"; - led-id = "EC_LED_ID_POWER_LED"; - led-pins = <&led_power_white 100>; - }; - - color_battery_off: color-battery-off { - led-color = "LED_OFF"; - led-id = "EC_LED_ID_BATTERY_LED"; - led-pins = <&led_battery_amber 0>, - <&led_battery_white 0>; - }; - - color_battery_amber: color-battery-amber { - led-color = "LED_AMBER"; - led-id = "EC_LED_ID_BATTERY_LED"; - led-pins = <&led_battery_amber 100>, - <&led_battery_white 0>; - }; - - color_battery_white: color-battery-white { - led-color = "LED_WHITE"; - led-id = "EC_LED_ID_BATTERY_LED"; - led-pins = <&led_battery_amber 0>, - <&led_battery_white 100>; - }; - }; -}; - -/* LED1 */ -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; - -/* LED2 */ -&pwm1 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm1_gpa1_default>; - pinctrl-names = "default"; -}; - -/* LED3 */ -&pwm2 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm2_gpa2_default>; - pinctrl-names = "default"; -}; +#include "led_it81202_base.dtsi" diff --git a/zephyr/projects/corsola/led_tentacruel.dts b/zephyr/projects/corsola/led_tentacruel.dts index 42843c6cb6..b2233033e0 100644 --- a/zephyr/projects/corsola/led_tentacruel.dts +++ b/zephyr/projects/corsola/led_tentacruel.dts @@ -2,46 +2,54 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ +#include "led_it81202_base.dtsi" -/ { - pwmleds { - compatible = "pwm-leds"; - /* NOTE: &pwm number needs same with channel number */ - led_power_white: ec_led1_odl { - pwms = <&pwm0 PWM_CHANNEL_0 PWM_HZ(324) - PWM_POLARITY_INVERTED>; +&led_colors { + bat-power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_battery_white>; }; - led_battery_amber: ec_led2_odl { - pwms = <&pwm1 PWM_CHANNEL_1 PWM_HZ(324) - PWM_POLARITY_INVERTED>; + }; + + bat-power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; }; - led_battery_white: ec_led3_odl { - pwms = <&pwm2 PWM_CHANNEL_2 PWM_HZ(324) - PWM_POLARITY_INVERTED>; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; }; }; -}; -/* LED1 */ -&pwm0 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm0_gpa0_default>; - pinctrl-names = "default"; -}; + bat-power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; -/* LED2 */ -&pwm1 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm1_gpa1_default>; - pinctrl-names = "default"; -}; + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; + }; -/* LED3 */ -&pwm2 { - status = "okay"; - prescaler-cx = ; - pinctrl-0 = <&pwm2_gpa2_default>; - pinctrl-names = "default"; + bat-power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_battery_off>; + }; + }; }; diff --git a/zephyr/projects/corsola/src/krabby/led_tentacruel.c b/zephyr/projects/corsola/src/krabby/led_tentacruel.c deleted file mode 100644 index 18a66752e2..0000000000 --- a/zephyr/projects/corsola/src/krabby/led_tentacruel.c +++ /dev/null @@ -1,181 +0,0 @@ -/* Copyright 2022 The ChromiumOS Authors. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include "board_led.h" -#include "chipset.h" -#include "common.h" -#include "led_common.h" -#include "led_onoff_states.h" -#include "util.h" - -LOG_MODULE_REGISTER(board_led, LOG_LEVEL_ERR); - -/*If we need pwm output in ITE chip power saving mode, then we should set - * frequency <= 324Hz. - */ -#define BOARD_LED_PWM_PERIOD_NS BOARD_LED_HZ_TO_PERIOD_NS(324) - -static const struct board_led_pwm_dt_channel board_led_power_white = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_power_white)); -static const struct board_led_pwm_dt_channel board_led_battery_amber = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_amber)); -static const struct board_led_pwm_dt_channel board_led_battery_white = - BOARD_LED_PWM_DT_CHANNEL_INITIALIZER(DT_NODELABEL(led_battery_white)); - -__override const int led_charge_lvl_1 = 5; -__override const int led_charge_lvl_2 = 95; - -__override struct led_descriptor - led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = { - [STATE_CHARGING_LVL_1] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_LVL_2] = { { EC_LED_COLOR_AMBER, - LED_INDEFINITE } }, - [STATE_CHARGING_FULL_CHARGE] = { { EC_LED_COLOR_WHITE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_WHITE, - LED_INDEFINITE } }, - [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_WHITE, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [STATE_DISCHARGE_S5] = { { LED_OFF, LED_INDEFINITE } }, - [STATE_BATTERY_ERROR] = { { EC_LED_COLOR_AMBER, - 1 * LED_ONE_SEC }, - { LED_OFF, 1 * LED_ONE_SEC } }, - [STATE_FACTORY_TEST] = { { EC_LED_COLOR_WHITE, - 2 * LED_ONE_SEC }, - { EC_LED_COLOR_AMBER, - 2 * LED_ONE_SEC } }, - }; - -__override const struct led_descriptor - led_pwr_state_table[PWR_LED_NUM_STATES][LED_NUM_PHASES] = { - [PWR_LED_STATE_ON] = { { EC_LED_COLOR_WHITE, LED_INDEFINITE } }, - [PWR_LED_STATE_SUSPEND_AC] = { { EC_LED_COLOR_WHITE, - 1 * LED_ONE_SEC }, - { LED_OFF, 3 * LED_ONE_SEC } }, - [PWR_LED_STATE_SUSPEND_NO_AC] = { { EC_LED_COLOR_WHITE, - 1 * LED_ONE_SEC }, - { LED_OFF, - 3 * LED_ONE_SEC } }, - [PWR_LED_STATE_OFF] = { { LED_OFF, LED_INDEFINITE } }, - }; - -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_BATTERY_LED, - EC_LED_ID_POWER_LED, -}; - -const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); - -static void board_led_pwm_set_duty(const struct board_led_pwm_dt_channel *ch, - int percent) -{ - uint32_t pulse_ns; - int rv; - - if (!device_is_ready(ch->dev)) { - LOG_ERR("PWM device %s not ready", ch->dev->name); - return; - } - - pulse_ns = DIV_ROUND_NEAREST(BOARD_LED_PWM_PERIOD_NS * percent, 100); - - LOG_DBG("Board LED PWM %s set percent (%d), pulse %d", ch->dev->name, - percent, pulse_ns); - - rv = pwm_set(ch->dev, ch->channel, BOARD_LED_PWM_PERIOD_NS, pulse_ns, - ch->flags); - if (rv) { - LOG_ERR("pwm_set() failed %s (%d)", ch->dev->name, rv); - } -} - -__override void led_set_color_battery(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_AMBER: - board_led_pwm_set_duty(&board_led_battery_amber, 100); - board_led_pwm_set_duty(&board_led_battery_white, 0); - break; - case EC_LED_COLOR_WHITE: - board_led_pwm_set_duty(&board_led_battery_amber, 0); - board_led_pwm_set_duty(&board_led_battery_white, 100); - break; - default: - board_led_pwm_set_duty(&board_led_battery_amber, 0); - board_led_pwm_set_duty(&board_led_battery_white, 0); - break; - } -} - -__override void led_set_color_power(enum ec_led_colors color) -{ - switch (color) { - case EC_LED_COLOR_WHITE: - board_led_pwm_set_duty(&board_led_power_white, 100); - break; - default: - board_led_pwm_set_duty(&board_led_power_white, 0); - break; - } -} - -void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - brightness_range[EC_LED_COLOR_AMBER] = 1; - brightness_range[EC_LED_COLOR_WHITE] = 1; - } else if (led_id == EC_LED_ID_POWER_LED) { - brightness_range[EC_LED_COLOR_WHITE] = 1; - } -} - -int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) -{ - if (led_id == EC_LED_ID_BATTERY_LED) { - if (brightness[EC_LED_COLOR_AMBER] != 0) { - led_set_color_battery(EC_LED_COLOR_AMBER); - } else if (brightness[EC_LED_COLOR_WHITE] != 0) { - led_set_color_battery(EC_LED_COLOR_WHITE); - } else { - led_set_color_battery(LED_OFF); - } - } else if (led_id == EC_LED_ID_POWER_LED) { - if (brightness[EC_LED_COLOR_WHITE] != 0) { - led_set_color_power(EC_LED_COLOR_WHITE); - } else { - led_set_color_power(LED_OFF); - } - } - - return EC_SUCCESS; -} - -__override enum led_states board_led_get_state(enum led_states desired_state) -{ - /* - * Battery error LED behavior as below: - * S0: Blinking Amber LED, 1s on/ 1s off - * S3/S5: following S3/S5 behavior - * Add function to let battery error LED follow S3/S5 behavior in S3/S5. - */ - - if (desired_state == STATE_BATTERY_ERROR) { - if (chipset_in_state(CHIPSET_STATE_ON)) { - return desired_state; - } else if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) { - return STATE_DISCHARGE_S3; - } else { - return STATE_DISCHARGE_S5; - } - } - return desired_state; -} -- cgit v1.2.1 From f13bdb1b0ccab042f11db99d2f1a3b7599684a5a Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Mon, 4 Jul 2022 16:27:39 +0800 Subject: zephyr/it8xxx2: increase the image size to 1MB Set CONFIG_FLASH_SIZE_BYTES back to 1MB to match the hard-coded number in tast. After this CL, the region mapping become: 384kB RO + PSTATE 384kB RW 256kB unused This CL doesn't increase the RO/RW region size, only adds a 256kB unallocated region at the end of FLASH. So the performance of software sync should be the same. BUG=b:237350549 TEST=1) size of zephyr.bin is still 768kB 2) `dut-control ec_flash_size` prints 1MB instead of 768kB 3) ec software sync and sysjump works 4) fw region macros doesn't change: CONFIG_FW_PSTATE_SIZE: 4096 CONFIG_FW_PSTATE_OFF: 389120 CONFIG_RO_MEM_OFF: 0 CONFIG_RO_STORAGE_OFF: 0 CONFIG_RO_SIZE: 393216 CONFIG_RW_MEM_OFF: 393216 CONFIG_RW_STORAGE_OFF: 0 CONFIG_RW_SIZE: 393216 CONFIG_EC_PROTECTED_STORAGE_OFF: 0 CONFIG_EC_PROTECTED_STORAGE_SIZE: 393216 CONFIG_EC_WRITABLE_STORAGE_OFF: 393216 CONFIG_EC_WRITABLE_STORAGE_SIZE: 393216 CONFIG_WP_STORAGE_OFF: 0 CONFIG_WP_STORAGE_SIZE: 393216 BRANCH=none Signed-off-by: Ting Shen Change-Id: I598186737cfef4db50c4eecfc846800e17dfd537 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742961 Commit-Queue: Ting Shen Tested-by: Ting Shen Reviewed-by: Eric Yilun Lin Reviewed-by: Dino Li --- zephyr/shim/chip/it8xxx2/include/flash_chip.h | 2 +- zephyr/shim/include/config_chip.h | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/zephyr/shim/chip/it8xxx2/include/flash_chip.h b/zephyr/shim/chip/it8xxx2/include/flash_chip.h index ce8cc326ff..06b33ee6e1 100644 --- a/zephyr/shim/chip/it8xxx2/include/flash_chip.h +++ b/zephyr/shim/chip/it8xxx2/include/flash_chip.h @@ -28,6 +28,6 @@ */ #define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE #define CONFIG_FW_PSTATE_OFF \ - (CONFIG_FLASH_SIZE_BYTES / 2 - CONFIG_FW_PSTATE_SIZE) + (CONFIG_RO_STORAGE_OFF + CONFIG_RO_SIZE - CONFIG_FW_PSTATE_SIZE) #endif /* __CROS_EC_FLASH_CHIP_H */ diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 05a927796f..102238be83 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -562,15 +562,7 @@ extern struct jump_data mock_jump_data; #undef CONFIG_FLASH_SIZE_BYTES #ifdef CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES -/* - * Flash size of IT81202 is 1MB. - * We use only 3/4 space of flash to save time of erasing RW image from flash. - */ -#ifdef CONFIG_SOC_IT8XXX2 -#define CONFIG_FLASH_SIZE_BYTES (CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES * 3 / 4) -#else #define CONFIG_FLASH_SIZE_BYTES CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES -#endif #endif /* CONFIG_PLATFORM_EC_FLASH_SIZE_BYTES */ #undef CONFIG_ADC -- cgit v1.2.1 From 1cbc1b5170afd28473330e385b7317d95b14d960 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 7 Jul 2022 11:29:00 +0800 Subject: mt8186: reports forcing shutdown by long pwrkey press When powerkey long pressed for 8(+-20%) seconds, the PMIC will enter forcing shutdown mode and turn off the rail. If PMIC enters the forcing shutdown process too fast, then the shutdown reason report will be canceled, and we won't know the exactly shutdown reason. This CL reports the shutdown reason when the power is going for S0S3, and hasn't reported the reason. BUG=none TEST=1. at S0, ensure the long powerkey press reports 0x8009 2. apshutdown works 3. shutdown from AP works 4. at S3, long press powerkey: S3->S0->S3->S5->G3 BRANCH=none Change-Id: I1ea8e710a81ed7267c7f87c6c6d711a045603b7e Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750273 Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen --- power/mt8186.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/power/mt8186.c b/power/mt8186.c index a9f871d3d6..c05e785418 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -146,10 +146,12 @@ void chipset_force_shutdown(enum chipset_shutdown_reason reason) * transitions to G3. */ GPIO_SET_LEVEL(GPIO_SYS_RST_ODL, 0); - CPRINTS("Forcing pmic off with long press."); - GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0); - hook_call_deferred(&release_power_button_data, - FORCED_SHUTDOWN_DELAY + SECOND); + if (reason != CHIPSET_SHUTDOWN_BUTTON) { + CPRINTS("Forcing pmic off with long press."); + GPIO_SET_LEVEL(GPIO_EC_PMIC_EN_ODL, 0); + hook_call_deferred(&release_power_button_data, + FORCED_SHUTDOWN_DELAY + SECOND); + } task_wake(TASK_ID_CHIPSET); } @@ -426,9 +428,16 @@ enum power_state power_handle_state(enum power_state state) * In case the power button is held awaiting power-off timeout, * power off immediately now that we're entering S3. */ - if (power_button_is_pressed()) + if (power_button_is_pressed()) { hook_call_deferred(&chipset_force_shutdown_button_data, -1); + /* + * if the ap is shutting down, but it doesn't report + * the reason, report it now. + */ + if (!is_shutdown) + chipset_force_shutdown_button(); + } return POWER_S3; -- cgit v1.2.1 From fffb8c13db96322b77673295c10a0a41fdf6530e Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 7 Jul 2022 11:41:28 +0800 Subject: mt8186: reports reset/shutdown reason in hex It's more readable if the reason is in hex format. BUG=none TEST=the reasons are reports in hex format BRANCH=none Change-Id: I95133806caad9047dcbbffc22b8c1f04033773d8 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750274 Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- power/mt8186.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/power/mt8186.c b/power/mt8186.c index c05e785418..53ea4670d8 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -137,7 +137,7 @@ DECLARE_DEFERRED(release_power_button); void chipset_force_shutdown(enum chipset_shutdown_reason reason) { - CPRINTS("%s(%d)", __func__, reason); + CPRINTS("%s: 0x%x", __func__, reason); report_ap_reset(reason); is_shutdown = true; @@ -194,7 +194,7 @@ DECLARE_DEFERRED(reset_flag_deferred); void chipset_reset(enum chipset_shutdown_reason reason) { - CPRINTS("%s: %d", __func__, reason); + CPRINTS("%s: 0x%x", __func__, reason); report_ap_reset(reason); is_resetting = true; -- cgit v1.2.1 From a77fc18cbd1a10f069597b73c2aa8a8c370fa303 Mon Sep 17 00:00:00 2001 From: Patrick Thompson Date: Wed, 6 Jul 2022 18:06:03 +0000 Subject: README: Emphasize with inline code instead of bold README.md has angle brackets that are supposed to be displayed but are not because bold (**) does not escape brackets. The rest of the file uses inline code (backtics) for emphasis so that's what I changed it to. BUG=b:231139247 BRANCH=None TEST=None Change-Id: I7b3c791c402fd7f7e270a4e340cb40bcca166ead Signed-off-by: Patrick Thompson Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749530 Reviewed-by: Tom Hughes --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 0a10859b93..10d169888c 100644 --- a/README.md +++ b/README.md @@ -179,7 +179,7 @@ cd ~/trunk/src/platform/ec make -j BOARD= ``` -Where **** is replaced by the name of the board you want to build an +Where `` is replaced by the name of the board you want to build an EC binary for. For example, the boardname for the Chromebook Pixel is “link”. The make command will generate an EC binary at `build//ec.bin`. The `-j` tells make to build multi-threaded which can be much faster on a multi-core -- cgit v1.2.1 From ad2968b5c65860d6c8e4808d37d6f7111ece1f6c Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Wed, 6 Jul 2022 13:08:40 -0600 Subject: cq: Merge in the legacy tests in the zephyr cov Just like in gitlab, merge in the legacy coverage data, and put that into the ALL_MERGED metric. BRANCH=None BUG=b:231639771 TEST=Ran locally. Signed-off-by: Jeremy Bettis Change-Id: I05128b0c07160ab6d5f3937216dd1797b2403f39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748852 Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis --- zephyr/firmware_builder.py | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index 21767d635a..c8c34f02ae 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -193,7 +193,7 @@ def test(opts): cmd = [ '/usr/bin/lcov', '-o', - build_dir / 'lcov.info', + build_dir / 'zephyr_merged.info', '--rc', 'lcov_branch_coverage=1', '-a', @@ -212,6 +212,32 @@ def test(opts): stdout=subprocess.PIPE, universal_newlines=True).stdout _extract_lcov_summary('EC_ZEPHYR_TESTS', metrics, output) + cmd = ['make', 'coverage', f'-j{opts.cpus}'] + print(f"# Running {' '.join(cmd)}.") + subprocess.run(cmd, cwd=platform_ec, check=True) + + output = subprocess.run( + ['/usr/bin/lcov', '--summary', platform_ec / 'build/coverage/lcov.info'], + cwd=pathlib.Path(__file__).parent, check=True, + stdout=subprocess.PIPE, universal_newlines=True).stdout + _extract_lcov_summary('EC_LEGACY_MERGED', metrics, output) + + cmd = [ + '/usr/bin/lcov', + '-o', + build_dir / 'lcov.info', + '--rc', + 'lcov_branch_coverage=1', + '-a', + build_dir / 'zephyr_merged.info', + '-a', + platform_ec / 'build/coverage/lcov.info', + ] + output = subprocess.run( + cmd, cwd=pathlib.Path(__file__).parent, check=True, + stdout=subprocess.PIPE, universal_newlines=True).stdout + _extract_lcov_summary('ALL_MERGED', metrics, output) + with open(opts.metrics, 'w') as file: file.write(json_format.MessageToJson(metrics)) return 0 -- cgit v1.2.1 From 92f620fa41c4fd08c420518a5bef201188b36f65 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Wed, 6 Jul 2022 16:17:29 -0600 Subject: ec: Don't convert coverage paths to relative The build_firmware recipe will take care of converting paths to absolute or relative as necessary, so leave the paths alone. BRANCH=None BUG=b:231639771 TEST=Ran locally Signed-off-by: Jeremy Bettis Change-Id: I2588f55fd3bcca81459846be8ae6228404f5e3f0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749799 Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis --- Makefile.rules | 3 --- 1 file changed, 3 deletions(-) diff --git a/Makefile.rules b/Makefile.rules index 7af36a3afe..484df79b4f 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -442,8 +442,6 @@ cmd_merge_cov=lcov --rc lcov_branch_coverage=1 -o build/coverage/lcov.info \ $(foreach info,$^,-a ${info}) cmd_report_cov=genhtml --branch-coverage -q -o build/coverage/coverage_rpt -t \ "EC Unittest "$(bldversion) -s $^ -cmd_strip_lcov=sed -i build/coverage/lcov.info \ - -e 's/\/mnt\/host\/source\/src\/platform\/ec\///' # Unless V is set to 0 we always want the 'size:' target to report its output, # there is no point in generating a short form command trace when calculating @@ -491,7 +489,6 @@ coverage: TEST_FLAG=TEST_COVERAGE=y coverage: $(cov-test-targets) $(cov-initial-targets) $(call quiet,merge_cov,MERGE ) $(call quiet,report_cov,REPORT ) - $(call quiet,strip_lcov,STRIP ) test-coverage: TEST_FLAG=TEST_COVERAGE=y test-coverage: $(cov-test-targets) $(call quiet,merge_cov,MERGE ) -- cgit v1.2.1 From c906c30b89afbb65a188faadec1f0ddc03bd7a60 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Tue, 21 Jun 2022 09:34:42 -0700 Subject: ccgxxf: Return cached CC state on I2C failure Once the PD negotiation completes, CCGXXF chip stops responding over I2C for about 10 seconds. As DRP is enabled, TCPM algorithm constantly looks for any CC status changes even after negotiation completes. Hence, cache the CC state and return the cached values in case of I2C failures. This workaround will be removed once the fix is added in the physical layer firmware of CCGXXF. BUG=b:236994474 BRANCH=none TEST=Able to negotiate USB/DP/TBT/USB4 on MTLRVP Change-Id: Ia51b6accca3e9fa0d49b9b27915c4f95c62e35be Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3715434 Reviewed-by: Diana Z Reviewed-by: RAJESH KUMAR --- driver/tcpm/ccgxxf.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/driver/tcpm/ccgxxf.c b/driver/tcpm/ccgxxf.c index 216b812e5e..2c8431f474 100644 --- a/driver/tcpm/ccgxxf.c +++ b/driver/tcpm/ccgxxf.c @@ -9,6 +9,50 @@ #include "console.h" #include "tcpm/tcpci.h" +/* + * TODO (b/236994474): Once the PD negotiation completes, CCGXXF chip stops + * responding over I2C for about 10 seconds. As DRP is enabled, TCPM algorithm + * constantly looks for any CC status changes even after negotiation completes. + * Hence, cache the CC state and return the cached values in case of I2C + * failures. This workaround will be removed once the fix is added in the + * physical layer firmware of CCGXXF. + */ + +struct ccgxxf_cc { + bool good_cc; + enum tcpc_cc_voltage_status cc1; + enum tcpc_cc_voltage_status cc2; +}; + +static struct ccgxxf_cc ccgxxf_cc_cache[CONFIG_USB_PD_PORT_MAX_COUNT]; + +static int ccgxxf_tcpci_tcpm_get_cc(int port, enum tcpc_cc_voltage_status *cc1, + enum tcpc_cc_voltage_status *cc2) +{ + int rv = tcpci_tcpm_get_cc(port, cc1, cc2); + + if (rv) { + if (!ccgxxf_cc_cache[port].good_cc) + return rv; + + *cc1 = ccgxxf_cc_cache[port].cc1; + *cc2 = ccgxxf_cc_cache[port].cc2; + } else { + ccgxxf_cc_cache[port].good_cc = true; + ccgxxf_cc_cache[port].cc1 = *cc1; + ccgxxf_cc_cache[port].cc2 = *cc2; + } + + return EC_SUCCESS; +} + +static int ccgxxf_tcpci_tcpm_init(int port) +{ + ccgxxf_cc_cache[port].good_cc = false; + + return tcpci_tcpm_init(port); +} + #ifdef CONFIG_USB_PD_TCPM_SBU static int ccgxxf_tcpc_set_sbu(int port, bool enable) { @@ -38,9 +82,9 @@ int ccgxxf_reset(int port) } const struct tcpm_drv ccgxxf_tcpm_drv = { - .init = &tcpci_tcpm_init, + .init = &ccgxxf_tcpci_tcpm_init, .release = &tcpci_tcpm_release, - .get_cc = &tcpci_tcpm_get_cc, + .get_cc = &ccgxxf_tcpci_tcpm_get_cc, #ifdef CONFIG_USB_PD_VBUS_DETECT_TCPC .check_vbus_level = &tcpci_tcpm_check_vbus_level, #endif -- cgit v1.2.1 From b554eb7345948d8c743341ec68580c804a6a84ab Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:57 -0600 Subject: include/btle_hci_int.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ief33fd9a5b8eed2264b143ebf1261835e9cc0230 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749516 Reviewed-by: Jeremy Bettis --- include/btle_hci_int.h | 90 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 36 deletions(-) diff --git a/include/btle_hci_int.h b/include/btle_hci_int.h index 286afb3b37..4271b4b57e 100644 --- a/include/btle_hci_int.h +++ b/include/btle_hci_int.h @@ -176,13 +176,15 @@ 0x0000000000004000ULL /* BT 4.0+ */ #define HCI_LE_STATE_DIRECT_ADV_w_ACTIVE_SCAN \ 0x0000000000008000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_NONCON_ADV_w_INITIATING 0x0000000000010000ULL /* BT 4.0+ \ - */ +#define HCI_LE_STATE_NONCON_ADV_w_INITIATING \ + 0x0000000000010000ULL /* BT 4.0+ \ + */ #define HCI_LE_STATE_SCANNABLE_ADV_w_INITIATING \ 0x0000000000020000ULL /* BT 4.0+ */ #define HCI_LE_STATE_NONCON_ADV_w_MASTER 0x0000000000040000ULL /* BT 4.0+ */ -#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER 0x0000000000080000ULL /* BT 4.0+ \ - */ +#define HCI_LE_STATE_SCANNABLE_ADV_w_MASTER \ + 0x0000000000080000ULL /* BT 4.0+ \ + */ #define HCI_LE_STATE_NONCON_ADV_w_SLAVE 0x0000000000100000ULL /* BT 4.0+ */ #define HCI_LE_STATE_SCANNABLE_ADV_w_SLAVE 0x0000000000200000ULL /* BT 4.0+ */ #define HCI_LE_STATE_PASSIVE_SCAN_w_INITIATING \ @@ -202,8 +204,9 @@ 0x0000000080000000ULL /* BT 4.1+ */ #define HCI_LE_STATE_CONNECTABLE_ADV_w_INITIATING \ 0x0000000100000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING 0x0000000200000000ULL /* BT 4.1+ \ - */ +#define HCI_LE_STATE_DIRECT_ADV_w_INITIATING \ + 0x0000000200000000ULL /* BT 4.1+ \ + */ #define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_INITIATING \ 0x0000000400000000ULL /* BT 4.1+ */ #define HCI_LE_STATE_CONNECTABLE_ADV_w_MASTER \ @@ -211,8 +214,9 @@ #define HCI_LE_STATE_DIRECT_ADV_w_MASTER 0x0000001000000000ULL /* BT 4.1+ */ #define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_MASTER \ 0x0000002000000000ULL /* BT 4.1+ */ -#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE 0x0000004000000000ULL /* BT 4.1+ \ - */ +#define HCI_LE_STATE_CONNECTABLE_ADV_w_SLAVE \ + 0x0000004000000000ULL /* BT 4.1+ \ + */ #define HCI_LE_STATE_DIRECT_ADV_w_SLAVE 0x0000008000000000ULL /* BT 4.1+ */ #define HCI_LE_STATE_LOW_DUTY_CYCLE_DIRECT_ADV_w_SLAVE \ 0x0000010000000000ULL /* BT 4.1+ */ @@ -246,8 +250,9 @@ #define HCI_LMP_FTR_ACL_2MBPS 0x0000000002000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_ACL_3MBPS 0x0000000004000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_ENHANCED_INQUIRY_SCAN 0x0000000008000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN 0x0000000010000000ULL /* BT 2.1+ \ - */ +#define HCI_LMP_FTR_INTERLACED_INQUIRY_SCAN \ + 0x0000000010000000ULL /* BT 2.1+ \ + */ #define HCI_LMP_FTR_INTERLACED_PAGE_SCAN 0x0000000020000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_RSSI_WITH_INQUIRY_RESULTS \ 0x0000000040000000ULL /* BT 2.1+ */ @@ -256,11 +261,13 @@ #define HCI_LMP_FTR_EV4_PACKETS 0x0000000100000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_EV5_PACKETS 0x0000000200000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_AFH_CAPABLE_SLAVE 0x0000000800000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE 0x0000001000000000ULL /* BT 2.1+ \ - */ +#define HCI_LMP_FTR_AFH_CLASSIFICATION_SLAVE \ + 0x0000001000000000ULL /* BT 2.1+ \ + */ #define HCI_LMP_FTR_BR_EDR_NOT_SUPPORTED 0x0000002000000000ULL /* BT 4.0+ */ -#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER 0x0000004000000000ULL /* BT 4.0+ \ - */ +#define HCI_LMP_FTR_LE_SUPPORTED_CONTROLLER \ + 0x0000004000000000ULL /* BT 4.0+ \ + */ #define HCI_LMP_FTR_3_SLOT_ACL_PACKETS 0x0000008000000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_5_SLOT_ACL_PACKETS 0x0000010000000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_SNIFF_SUBRATING 0x0000020000000000ULL /* BT 2.1+ */ @@ -275,8 +282,9 @@ 0x0001000000000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_SSP 0x0008000000000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_ENCAPSULATED_PDU 0x0010000000000000ULL /* BT 2.1+ */ -#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING 0x0020000000000000ULL /* BT 2.1+ \ - */ +#define HCI_LMP_FTR_ERRONEOUS_DATA_REPORTING \ + 0x0020000000000000ULL /* BT 2.1+ \ + */ #define HCI_LMP_FTR_NON_FLUSHABLE_PACKET_BOUNDARY_FLAG \ 0x0040000000000000ULL /* BT 2.1+ */ #define HCI_LMP_FTR_LINK_SUPERVISION_TIMEOUT_CHANGED_EVENT \ @@ -288,8 +296,9 @@ #define HCI_LMP_FTR_SIMUL_LE_EDR_CAPABLE_CONTROLLER \ 0x0002000000000000ULL /* BT 4.0+ */ -#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT 0x0000000000000001ULL /* BT 2.1+ \ - */ +#define HCI_LMP_EXT_FTR_P1_SSP_HOST_SUPPORT \ + 0x0000000000000001ULL /* BT 2.1+ \ + */ #define HCI_LMP_EXT_FTR_P1_LE_HOST_SUPPORT 0x0000000000000002ULL /* BT 4.0+ */ #define HCI_LMP_EXT_FTR_P1_SIMUL_LE_EDR_HOST_SUPPORT \ 0x0000000000000004ULL /* BT 4.0+ */ @@ -343,8 +352,9 @@ #define HCI_EVENT_LOOPBACK_COMMAND 0x0000000001000000ULL /* BT 1.1+ */ #define HCI_EVENT_DATA_BUFFER_OVERFLOW 0x0000000002000000ULL /* BT 1.1+ */ #define HCI_EVENT_MAX_SLOTS_CHANGE 0x0000000004000000ULL /* BT 1.1+ */ -#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE 0x0000000008000000ULL /* BT 1.1+ \ - */ +#define HCI_EVENT_READ_CLOCK_OFFSET_COMPLETE \ + 0x0000000008000000ULL /* BT 1.1+ \ + */ #define HCI_EVENT_CONN_PACKET_TYPE_CHANGED 0x0000000010000000ULL /* BT 1.1+ */ #define HCI_EVENT_QOS_VIOLATION 0x0000000020000000ULL /* BT 1.1+ */ #define HCI_EVENT_PAGE_SCAN_MODE_CHANGE \ @@ -363,21 +373,24 @@ 0x00001FFFFFFFFFFFULL /* also the default for BT 1.2+ */ #define HCI_EVENT_SNIFF_SUBRATING 0x0000200000000000ULL /* BT 2.1+ */ #define HCI_EVENT_EXTENDED_INQUIRY_RESULT 0x0000400000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE 0x0000800000000000ULL /* BT 2.1+ \ - */ +#define HCI_EVENT_ENCR_KEY_REFRESH_COMPLETE \ + 0x0000800000000000ULL /* BT 2.1+ \ + */ #define HCI_EVENT_IO_CAPABILITY_REQUEST 0x0001000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_IO_CAPABILITY_REQUEST_REPLY \ 0x0002000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_CONFIRMATION_REQUEST 0x0004000000000000ULL /* BT 2.1+ \ - */ +#define HCI_EVENT_USER_CONFIRMATION_REQUEST \ + 0x0004000000000000ULL /* BT 2.1+ \ + */ #define HCI_EVENT_USER_PASSKEY_REQUEST 0x0008000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_REMOTE_OOB_DATA_REQUEST 0x0010000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_SIMPLE_PAIRING_COMPLETE 0x0020000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_LINK_SUPERVISION_TIMOUT_CHANGED \ 0x0080000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_ENHANCED_FLUSH_COMPLETE 0x0100000000000000ULL /* BT 2.1+ */ -#define HCI_EVENT_USER_PASSKEY_NOTIFICATION 0x0400000000000000ULL /* BT 2.1+ \ - */ +#define HCI_EVENT_USER_PASSKEY_NOTIFICATION \ + 0x0400000000000000ULL /* BT 2.1+ \ + */ #define HCI_EVENT_KEYPRESS_NOTIFICATION 0x0800000000000000ULL /* BT 2.1+ */ #define HCI_EVENT_REMOTE_HOST_SUPPORTED_FEATURES \ 0x1000000000000000ULL /* BT 2.1+ */ @@ -393,8 +406,9 @@ 0x0000000000000004ULL /* BT 3.0+ */ #define HCI_EVENT_P2_PHYSICAL_LINK_LOSS_EARLY_WARNING \ 0x0000000000000008ULL /* BT 3.0+ */ -#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY 0x0000000000000010ULL /* BT 3.0+ \ - */ +#define HCI_EVENT_P2_PHYSICAL_LINK_RECOVERY \ + 0x0000000000000010ULL /* BT 3.0+ \ + */ #define HCI_EVENT_P2_LOGICAL_LINK_COMPLETE 0x0000000000000020ULL /* BT 3.0+ */ #define HCI_EVENT_P2_DISCONNECTION_LOGICAL_LINK_COMPLETE \ 0x0000000000000040ULL /* BT 3.0+ */ @@ -410,16 +424,18 @@ #define HCI_EVENT_P2_AMP_STATUS_CHANGE 0x0000000000002000ULL /* BT 3.0+ */ #define HCI_EVENT_P2_ALL_BT_3_0 0x0000000000003FFFULL #define HCI_EVENT_P2_ALL_BT_4_0 0x0000000000003FFFULL -#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE 0x0000000000004000ULL /* BT 4.1+ \ - */ +#define HCI_EVENT_P2_TRIGGERED_CLOCK_CAPTURE \ + 0x0000000000004000ULL /* BT 4.1+ \ + */ #define HCI_EVENT_P2_SYNCH_TRAIN_COMPLETE 0x0000000000008000ULL /* BT 4.1+ */ #define HCI_EVENT_P2_SYNCH_TRAIN_RECEIVED 0x0000000000010000ULL /* BT 4.1+ */ #define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_RXED \ 0x0000000000020000ULL /* BT 4.1+ */ #define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_TIMEOUT \ 0x0000000000040000ULL /* BT 4.1+ */ -#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE 0x0000000000080000ULL /* BT 4.1+ \ - */ +#define HCI_EVENT_P2_TRUNCATED_PAGE_COMPLETE \ + 0x0000000000080000ULL /* BT 4.1+ \ + */ #define HCI_EVENT_P2_SLAVE_PAGE_RESPONSE_TIMEOUT \ 0x0000000000100000ULL /* BT 4.1+ */ #define HCI_EVENT_P2_CONNLESS_SLAVE_BROADCAST_CHANNEL_MAP_CHANGE \ @@ -898,8 +914,9 @@ struct hciCmplSetConnectionlessSlaveBroadcast { uint16_t interval; } __packed; -#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive 0x0042 /* complete \ - */ +#define HCI_CMD_Set_Connectionless_Slave_Broadcast_Receive \ + 0x0042 /* complete \ + */ struct hciSetConnectionlessSlaveBroadcastReceive { uint8_t enabled; uint8_t mac[6]; /* add rof tranmitter */ @@ -1595,8 +1612,9 @@ struct hciCmplReadLocalOobData { uint8_t R[16]; } __packed; -#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level 0x0058 /* complete \ - */ +#define HCI_CMD_Read_Inquiry_Response_Transmit_Power_Level \ + 0x0058 /* complete \ + */ struct hciCmplReadInquiryTransmitPowerLevel { uint8_t status; uint8_t power; /* actually an int8_t */ -- cgit v1.2.1 From 4face99efd24596a0aa52cd3db99e5c33f960f51 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:32 -0600 Subject: driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Tricium: disable Change-Id: I2809c0731ce779a9dd87730a07940c7738eb4c83 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729946 Commit-Queue: Tom Hughes Reviewed-by: Jeremy Bettis Reviewed-by: Tom Hughes --- driver/fingerprint/fpc/libfp/fpc_sensor_pal.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h index 78376863f1..173de4045a 100644 --- a/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h +++ b/driver/fingerprint/fpc/libfp/fpc_sensor_pal.h @@ -14,8 +14,10 @@ typedef void *fpc_device_t; * @brief Used to describe an interrupt */ typedef enum { - IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast interrupt) **/ - IRQ_EXT_TRIG = 0x02 /**< Externally triggered by event outside sensor (may take long time) **/ + IRQ_INT_TRIG = 0x01, /**< Internally triggered by sensor (fast + interrupt) **/ + IRQ_EXT_TRIG = 0x02 /**< Externally triggered by event outside sensor + (may take long time) **/ } fpc_pal_irq_t; /** @@ -109,9 +111,9 @@ int fpc_pal_spi_get_speed_hz(fpc_device_t device, uint32_t *speed_hz); * @param[in] ... additional arguments. * */ -#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG (1) -#define FPC_SENSOR_SDK_LOG_LEVEL_INFO (2) -#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR (3) +#define FPC_SENSOR_SDK_LOG_LEVEL_DEBUG (1) +#define FPC_SENSOR_SDK_LOG_LEVEL_INFO (2) +#define FPC_SENSOR_SDK_LOG_LEVEL_ERROR (3) #define FPC_SENSOR_SDK_LOG_LEVEL_DISABLED (4) void fpc_pal_log_entry(const char *tag, int log_level, const char *format, ...); -- cgit v1.2.1 From 8555cea7793323c2a4b1b196de544318bdc81d92 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:39:24 -0600 Subject: board/cherry/board.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Iff6332e788eb710f1923ee4c7e40015c013bcb54 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748795 Reviewed-by: Jeremy Bettis --- board/cherry/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cherry/board.c b/board/cherry/board.c index d343f0d69e..77669173be 100644 --- a/board/cherry/board.c +++ b/board/cherry/board.c @@ -256,8 +256,8 @@ const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -void board_set_charge_limit(int port, int supplier, int charge_ma, - int max_ma, int charge_mv) +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) { charge_set_input_current_limit( MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -- cgit v1.2.1 From 25536f9a849838deb82bbf3c36746176fe65605d Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:28 -0600 Subject: driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=./util/compare_build.sh -b fp Tricium: disable Change-Id: I7307b5373977851db34cea9d5e02324f8a49cf65 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729972 Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes Reviewed-by: Jeremy Bettis --- driver/fingerprint/fpc/bep/fpc_sensor_spi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c index 225752bdb6..9e03ef7dce 100644 --- a/driver/fingerprint/fpc/bep/fpc_sensor_spi.c +++ b/driver/fingerprint/fpc/bep/fpc_sensor_spi.c @@ -22,10 +22,10 @@ #define CPRINTF(format, args...) cprintf(CC_FP, format, ##args) #define CPRINTS(format, args...) cprints(CC_FP, format, ##args) -#define SPI_BUF_SIZE (1024) +#define SPI_BUF_SIZE (1024) -#define FPC_RESULT_OK (0) -#define FPC_RESULT_IO_ERROR (-8) +#define FPC_RESULT_OK (0) +#define FPC_RESULT_IO_ERROR (-8) static uint8_t spi_buf[SPI_BUF_SIZE] FP_FRAME_SECTION __aligned(4); -- cgit v1.2.1 From 43fa6b4bf834803e23562a868dfba32e561ea96f Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Thu, 30 Jun 2022 14:44:17 -0700 Subject: docs/fingerprint: Update power numbers for latest bloonchipper release BRANCH=none BUG=none TEST=view in gitiles Signed-off-by: Tom Hughes Change-Id: I98667aeda2e380dd215bd0bb0bcfca781b03e996 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739314 Reviewed-by: Andrea Grandi Reviewed-by: Bobby Casey --- docs/fingerprint/fingerprint.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md index e1b1bd1f9a..a17472207d 100644 --- a/docs/fingerprint/fingerprint.md +++ b/docs/fingerprint/fingerprint.md @@ -332,7 +332,7 @@ disconnected.* ``` **Firmware Version**: -`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.7314-3dfc5ff6-RW.bin` +`bloonchipper_v2.0.4277-9f652bb3-RO_v2.0.14348-e5fb0b9-RW.bin` #### MCU is idle @@ -342,13 +342,13 @@ disconnected.* ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 465 129.06 22.68 396.32 94.61 -@@ pp1800_dx_fp_mv 465 1800.00 0.00 1800.00 1800.00 -@@ pp1800_dx_fp_mw 465 0.00 0.00 0.00 0.00 -@@ pp3300_dx_fp_mv 465 3280.02 0.37 3288.00 3280.00 -@@ pp3300_dx_fp_mw 465 0.01 0.04 0.26 0.00 -@@ pp3300_dx_mcu_mv 465 3280.00 0.00 3280.00 3280.00 -@@ pp3300_dx_mcu_mw 465 20.76 0.12 22.04 20.73 +@@ sample_msecs 478 125.49 26.02 431.96 92.23 +@@ pp1800_dx_fp_mv 478 1800.00 0.00 1800.00 1800.00 +@@ pp1800_dx_fp_mw 478 0.00 0.00 0.00 0.00 +@@ pp3300_dx_fp_mv 478 3280.00 0.00 3280.00 3280.00 +@@ pp3300_dx_fp_mw 478 0.00 0.03 0.26 0.00 +@@ pp3300_dx_mcu_mv 478 3280.00 0.00 3280.00 3280.00 +@@ pp3300_dx_mcu_mw 478 21.78 0.06 23.09 21.78 ``` #### MCU in low power mode (suspend) @@ -359,13 +359,13 @@ disconnected.* ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 462 129.89 15.65 381.76 97.02 -@@ pp1800_dx_fp_mv 462 1800.00 0.00 1800.00 1800.00 -@@ pp1800_dx_fp_mw 462 0.00 0.00 0.00 0.00 -@@ pp3300_dx_fp_mv 462 3287.65 1.63 3288.00 3280.00 -@@ pp3300_dx_fp_mw 462 0.00 0.03 0.26 0.00 -@@ pp3300_dx_mcu_mv 462 3283.31 3.94 3288.00 3280.00 -@@ pp3300_dx_mcu_mw 462 1.55 0.08 1.58 1.31 +@@ sample_msecs 488 122.99 26.37 458.47 92.69 +@@ pp1800_dx_fp_mv 488 1800.00 0.00 1800.00 1800.00 +@@ pp1800_dx_fp_mw 488 0.00 0.00 0.00 0.00 +@@ pp3300_dx_fp_mv 488 3287.79 1.29 3288.00 3280.00 +@@ pp3300_dx_fp_mw 488 0.01 0.04 0.26 0.00 +@@ pp3300_dx_mcu_mv 488 3283.38 3.95 3288.00 3280.00 +@@ pp3300_dx_mcu_mw 488 1.57 0.59 9.73 1.31 ``` ### Icetower v0.1 -- cgit v1.2.1 From 4dfe7f2a385d9ad3ca10064b29e4acb0f68c30a3 Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Tue, 28 Jun 2022 13:30:18 +0800 Subject: BB retimer: Set 'DP CONNECTION' bit only when mux_state gets HPD event For some chromebooks design, there are expanssion card (typeC to HDMI) communicate with TCPC through CC line, when the HDMI card connect to chromebook the DP CONNECTION bit would be enable even no connect HDMI moinitor. It will increase BBR power consumption, so set 'DP CONNECTION' bit only when mux_state gets HPD event. BUG=b:233975818 BRANCH=None TEST=Test on Banshee, measure BBR power consumption reduce from 143mW to 7mW. And the HDMI monitor can be output. Signed-off-by: johnwc_yeh Change-Id: I8a80235992cfa1bac28f03c3b6a7ec378e07ecf3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3726600 Reviewed-by: Diana Z Tested-by: Enzo Hong Commit-Queue: Diana Z --- driver/retimer/bb_retimer.c | 22 ++++++++++++++-------- zephyr/test/drivers/src/bb_retimer.c | 7 +++---- 2 files changed, 17 insertions(+), 12 deletions(-) diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index 3efbaaab6a..6b7dffa2cc 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -413,13 +413,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, set_retimer_con |= BB_RETIMER_USB_3_SPEED; } - /* - * Bit 8: DP_CONNECTION - * 0 – No DP connection - * 1 – DP connected - */ if (mux_state & USB_PD_MUX_DP_ENABLED) { - set_retimer_con |= BB_RETIMER_DP_CONNECTION; /* * Bit 11-10: DP_PIN_ASSIGNMENT (ignored if BIT8 = 0) @@ -498,14 +492,26 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, retimer_con_reg &= ~BB_RETIMER_IRQ_HPD; /* + * Bit 8: DP_CONNECTION + * 0 - No DP connection + * 1 - DP connected + * * Bit 15: HPD_LVL (ignored if BIT8 = 0) * 0 - HPD_State Low * 1 - HPD_State High + * + * HDMI card connect to chromebook the DP_CONNECTION bit + * would be enable. + * It will increase BBR power consumption, so enable the DP bit + * only when the HPD bit is set so that the retimer stays in + * low power mode until the external monitor is connected. */ if (mux_state & USB_PD_MUX_HPD_LVL) - retimer_con_reg |= BB_RETIMER_HPD_LVL; + retimer_con_reg |= (BB_RETIMER_HPD_LVL | + BB_RETIMER_DP_CONNECTION); else - retimer_con_reg &= ~BB_RETIMER_HPD_LVL; + retimer_con_reg &= ~(BB_RETIMER_HPD_LVL | + BB_RETIMER_DP_CONNECTION); /* Writing the register4 */ bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg); diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/src/bb_retimer.c index 7aab7b4dfa..dad3f14c2c 100644 --- a/zephyr/test/drivers/src/bb_retimer.c +++ b/zephyr/test/drivers/src/bb_retimer.c @@ -162,8 +162,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | - BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_DP_CONNECTION; + BB_RETIMER_DATA_CONNECTION_PRESENT; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -177,7 +176,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_DP_CONNECTION | BB_RETIMER_IRQ_HPD; + BB_RETIMER_IRQ_HPD; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -191,7 +190,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_DP_CONNECTION | BB_RETIMER_HPD_LVL; + BB_RETIMER_HPD_LVL; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); } -- cgit v1.2.1 From 12865c86276d642a526df5f7b053db62409fe421 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 12:00:53 -0700 Subject: tree: Move stdlib implementation to builtin directory Keeping all of the standard library implementation in a single directory makes it easier to choose between EC's implementation or the implementation from the toolchain. BRANCH=none BUG=b:234181908, b:172020503 TEST=make buildall -j TEST=Using icetower v0.1, Segger J-Trace, and servo micro: ./test/run_device_tests.py -b dartmonkey Test "aes": PASSED Test "cec": PASSED Test "cortexm_fpu": PASSED Test "crc": PASSED Test "flash_physical": PASSED Test "flash_write_protect": PASSED Test "fpsensor_hw": PASSED Test "fpsensor_spi_ro": PASSED Test "fpsensor_spi_rw": PASSED Test "fpsensor_uart_ro": PASSED Test "fpsensor_uart_rw": PASSED Test "mpu_ro": PASSED Test "mpu_rw": PASSED Test "mutex": PASSED Test "pingpong": PASSED Test "printf": PASSED Test "queue": PASSED Test "rollback_region0": PASSED Test "rollback_region1": PASSED Test "rollback_entropy": PASSED Test "rtc": PASSED Test "sha256": PASSED Test "sha256_unrolled": PASSED Test "static_if": PASSED Test "system_is_locked_wp_on": PASSED Test "system_is_locked_wp_off": PASSED Test "timer_dos": PASSED Test "utils": PASSED Test "utils_str": PASSED Test "panic_data_dartmonkey_v2.0.2887": PASSED Test "panic_data_nocturne_fp_v2.2.64": PASSED Test "panic_data_nami_fp_v2.2.144": PASSED Signed-off-by: Tom Hughes Change-Id: I75f8591e87a9076d47208eb598186a391c77966d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724488 Reviewed-by: Edward Hill --- Makefile | 3 + Makefile.toolchain | 2 +- builtin/build.mk | 6 + builtin/stdlib.c | 387 ++++++++++++++++++++++++++++++++++++++++++++++++++ chip/mchp/build.mk | 6 +- common/build.mk | 2 +- common/util_stdlib.c | 387 -------------------------------------------------- zephyr/CMakeLists.txt | 9 +- 8 files changed, 407 insertions(+), 395 deletions(-) create mode 100644 builtin/build.mk create mode 100644 builtin/stdlib.c delete mode 100644 common/util_stdlib.c diff --git a/Makefile b/Makefile index 0602fd4abf..cdf926daa8 100644 --- a/Makefile +++ b/Makefile @@ -268,6 +268,7 @@ include $(BASEDIR)/build.mk ifneq ($(BASEDIR),$(BDIR)) include $(BDIR)/build.mk endif +include builtin/build.mk include chip/$(CHIP)/build.mk include core/$(CORE)/build.mk include common/build.mk @@ -307,6 +308,7 @@ ifneq ($(PBDIR),) all-obj-$(1)+=$(call objs_from_dir_p,$(PBDIR),board-private,$(1)) endif all-obj-$(1)+=$(call objs_from_dir_p,common,common,$(1)) +all-obj-$(1)+=$(call objs_from_dir_p,builtin,builtin,$(1)) all-obj-$(1)+=$(call objs_from_dir_p,driver,driver,$(1)) all-obj-$(1)+=$(call objs_from_dir_p,power,power,$(1)) ifdef CTS_MODULE @@ -353,6 +355,7 @@ dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common fuzz power test \ dirs+= private private-kandou $(PDIR) $(PBDIR) dirs+=$(shell find common -type d) dirs+=$(shell find driver -type d) +dirs+=builtin common_dirs=util ifeq ($(custom-ro_objs-y),) diff --git a/Makefile.toolchain b/Makefile.toolchain index 6b82885522..2ce8f2ba5f 100644 --- a/Makefile.toolchain +++ b/Makefile.toolchain @@ -89,7 +89,7 @@ CFLAGS_WARN = $(COMMON_WARN) $(C_WARN) CXXFLAGS_WARN = $(COMMON_WARN) CFLAGS_DEBUG= -g CFLAGS_DEBUG+=$(CFLAGS_DEBUG_CHIP) -CFLAGS_INCLUDE=$(foreach i,$(includes),-I$(i) ) -I. +CFLAGS_INCLUDE=$(foreach i,$(filter-out builtin, $(includes)),-I$(i) ) -I. CFLAGS_TEST=$(if $(TEST_BUILD),-DTEST_BUILD=$(EMPTY) \ -DTEST_TASKFILE=$(PROJECT).tasklist,) \ $(if $(CTS_MODULE), $(CFLAGS_CTS)) \ diff --git a/builtin/build.mk b/builtin/build.mk new file mode 100644 index 0000000000..c4ec975e6b --- /dev/null +++ b/builtin/build.mk @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Build for EC's standard library implementation. +builtin-y=stdlib.o diff --git a/builtin/stdlib.c b/builtin/stdlib.c new file mode 100644 index 0000000000..e42788c4af --- /dev/null +++ b/builtin/stdlib.c @@ -0,0 +1,387 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Standard library utility functions for Chrome EC */ + +#include "common.h" +#include "console.h" +#include "util.h" + +/* + * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll + * use the EC implementation. + */ +__stdlib_compat int strcasecmp(const char *s1, const char *s2) +{ + int diff; + + do { + diff = tolower(*s1) - tolower(*s2); + if (diff) + return diff; + } while (*(s1++) && *(s2++)); + return 0; +} + +/* + * TODO(b/237712836): Remove this conditional once strcasecmp is added to + * Zephyr's libc. + */ +#ifndef CONFIG_ZEPHYR +__stdlib_compat size_t strlen(const char *s) +{ + int len = 0; + + while (*s++) + len++; + + return len; +} + +__stdlib_compat size_t strnlen(const char *s, size_t maxlen) +{ + size_t len = 0; + + while (len < maxlen && *s) { + s++; + len++; + } + return len; +} + +__stdlib_compat size_t strcspn(const char *s, const char *reject) +{ + size_t i; + size_t reject_len = strlen(reject); + + for (i = 0; s[i] != 0; i++) + for (size_t j = 0; j < reject_len; j++) + if (s[i] == reject[j]) + return i; + return i; +} + +__stdlib_compat int isspace(int c) +{ + return c == ' ' || c == '\t' || c == '\r' || c == '\n'; +} + +__stdlib_compat int isdigit(int c) +{ + return c >= '0' && c <= '9'; +} + +__stdlib_compat int isalpha(int c) +{ + return (c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z'); +} + +__stdlib_compat int isupper(int c) +{ + return c >= 'A' && c <= 'Z'; +} + +__stdlib_compat int isprint(int c) +{ + return c >= ' ' && c <= '~'; +} + +__stdlib_compat int tolower(int c) +{ + return c >= 'A' && c <= 'Z' ? c + 'a' - 'A' : c; +} + +__stdlib_compat int strncasecmp(const char *s1, const char *s2, size_t size) +{ + int diff; + + if (!size) + return 0; + + do { + diff = tolower(*s1) - tolower(*s2); + if (diff) + return diff; + } while (*(s1++) && *(s2++) && --size); + return 0; +} + +__stdlib_compat char *strstr(const char *s1, const char *s2) +{ + const char *p, *q, *r; + size_t len1 = strlen(s1); + size_t len2 = strlen(s2); + + if (len1 == 0 || len2 == 0 || len1 < len2) + return NULL; + + r = s1 + len1 - len2 + 1; + for (; s1 < r; s1++) { + if (*s1 == *s2) { + p = s1 + 1; + q = s2 + 1; + for (; q < s2 + len2;) { + if (*p++ != *q++) + break; + } + if (*q == '\0') + return (char *)s1; + } + } + return NULL; +} + +__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr, + int base) +{ + uint64_t result = 0; + int c = '\0'; + + while ((c = *nptr++) && isspace(c)) + ; + + if (c == '+') { + c = *nptr++; + } else if (c == '-') { + if (endptr) + *endptr = (char *)nptr - 1; + return result; + } + + base = find_base(base, &c, &nptr); + + while (c) { + if (c >= '0' && c < '0' + MIN(base, 10)) + result = result * base + (c - '0'); + else if (c >= 'A' && c < 'A' + base - 10) + result = result * base + (c - 'A' + 10); + else if (c >= 'a' && c < 'a' + base - 10) + result = result * base + (c - 'a' + 10); + else + break; + + c = *nptr++; + } + + if (endptr) + *endptr = (char *)nptr - 1; + return result; +} +BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t)); + +__stdlib_compat int atoi(const char *nptr) +{ + int result = 0; + int neg = 0; + char c = '\0'; + + while ((c = *nptr++) && isspace(c)) + ; + + if (c == '-') { + neg = 1; + c = *nptr++; + } + + while (isdigit(c)) { + result = result * 10 + (c - '0'); + c = *nptr++; + } + + return neg ? -result : result; +} + +__keep __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len) +{ + const char *sa = s1; + const char *sb = s2; + int diff = 0; + + while (len-- > 0) { + diff = *(sa++) - *(sb++); + if (diff) + return diff; + } + + return 0; +} + +#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) +__keep __stdlib_compat void *memcpy(void *dest, const void *src, size_t len) +{ + char *d = (char *)dest; + const char *s = (const char *)src; + uint32_t *dw; + const uint32_t *sw; + char *head; + char *const tail = (char *)dest + len; + /* Set 'body' to the last word boundary */ + uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); + + if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { + /* Misaligned. no body, no tail. */ + head = tail; + } else { + /* Aligned */ + if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3)) + /* len is shorter than the first word boundary */ + head = tail; + else + /* Set 'head' to the first word boundary */ + head = (char *)(((uintptr_t)d + 3) & ~3); + } + + /* Copy head */ + while (d < head) + *(d++) = *(s++); + + /* Copy body */ + dw = (uint32_t *)d; + sw = (uint32_t *)s; + while (dw < body) + *(dw++) = *(sw++); + + /* Copy tail */ + d = (char *)dw; + s = (const char *)sw; + while (d < tail) + *(d++) = *(s++); + + return dest; +} +#endif /* address_sanitizer || memory_sanitizer */ + +#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) +__keep __stdlib_compat __visible void *memset(void *dest, int c, size_t len) +{ + char *d = (char *)dest; + uint32_t cccc; + uint32_t *dw; + char *head; + char *const tail = (char *)dest + len; + /* Set 'body' to the last word boundary */ + uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); + + c &= 0xff; /* Clear upper bits before ORing below */ + cccc = c | (c << 8) | (c << 16) | (c << 24); + + if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3)) + /* len is shorter than the first word boundary */ + head = tail; + else + /* Set 'head' to the first word boundary */ + head = (char *)(((uintptr_t)d + 3) & ~3); + + /* Copy head */ + while (d < head) + *(d++) = c; + + /* Copy body */ + dw = (uint32_t *)d; + while (dw < body) + *(dw++) = cccc; + + /* Copy tail */ + d = (char *)dw; + while (d < tail) + *(d++) = c; + + return dest; +} +#endif /* address_sanitizer || memory_sanitizer */ + +#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) +__keep __stdlib_compat void *memmove(void *dest, const void *src, size_t len) +{ + if ((uintptr_t)dest <= (uintptr_t)src || + (uintptr_t)dest >= (uintptr_t)src + len) { + /* Start of destination doesn't overlap source, so just use + * memcpy(). + */ + return memcpy(dest, src, len); + } else { + /* Need to copy from tail because there is overlap. */ + char *d = (char *)dest + len; + const char *s = (const char *)src + len; + uint32_t *dw; + const uint32_t *sw; + char *head; + char *const tail = (char *)dest; + /* Set 'body' to the last word boundary */ + uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3); + + if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { + /* Misaligned. no body, no tail. */ + head = tail; + } else { + /* Aligned */ + if ((uintptr_t)tail > ((uintptr_t)d & ~3)) + /* Shorter than the first word boundary */ + head = tail; + else + /* Set 'head' to the first word boundary */ + head = (char *)((uintptr_t)d & ~3); + } + + /* Copy head */ + while (d > head) + *(--d) = *(--s); + + /* Copy body */ + dw = (uint32_t *)d; + sw = (uint32_t *)s; + while (dw > body) + *(--dw) = *(--sw); + + /* Copy tail */ + d = (char *)dw; + s = (const char *)sw; + while (d > tail) + *(--d) = *(--s); + + return dest; + } +} +#endif /* address_sanitizer || memory_sanitizer */ + +__stdlib_compat void *memchr(const void *buffer, int c, size_t n) +{ + char *current = (char *)buffer; + char *end = current + n; + + while (current != end) { + if (*current == c) + return current; + current++; + } + return NULL; +} + +__stdlib_compat char *strncpy(char *dest, const char *src, size_t n) +{ + char *d = dest; + + while (n && *src) { + *d++ = *src++; + n--; + } + if (n) + *d = '\0'; + return dest; +} + +__stdlib_compat int strncmp(const char *s1, const char *s2, size_t n) +{ + while (n--) { + if (*s1 != *s2) + return *s1 - *s2; + if (!*s1) + break; + s1++; + s2++; + } + return 0; +} +#endif /* !CONFIG_ZEPHYR */ diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk index 1e3de24d06..0ffb3a7c4a 100644 --- a/chip/mchp/build.mk +++ b/chip/mchp/build.mk @@ -81,9 +81,11 @@ chip-lfw-flat = $(out)/RW/$(chip-lfw)-lfw.flat # build these specifically for lfw with -lfw suffix objs_lfw = $(patsubst %, $(out)/RW/%-lfw.o, \ - $(addprefix common/, util util_stdlib gpio) \ + $(addprefix common/, util gpio) \ $(addprefix chip/$(CHIP)/, spi qmspi dma gpio clock hwtimer tfdp) \ - core/$(CORE)/cpu $(chip-lfw)) + core/$(CORE)/cpu $(chip-lfw) \ + builtin/stdlib \ + ) # reuse version.o (and its dependencies) from main board objs_lfw += $(out)/RW/common/version.o diff --git a/common/build.mk b/common/build.mk index 6473d53291..9f9bad8138 100644 --- a/common/build.mk +++ b/common/build.mk @@ -9,7 +9,7 @@ # Note that this variable includes the trailing "/" _common_dir:=$(dir $(lastword $(MAKEFILE_LIST))) -common-y=util.o util_stdlib.o +common-y=util.o common-y+=version.o printf.o queue.o queue_policies.o irq_locking.o common-$(CONFIG_ACCELGYRO_BMI160)+=math_util.o diff --git a/common/util_stdlib.c b/common/util_stdlib.c deleted file mode 100644 index e42788c4af..0000000000 --- a/common/util_stdlib.c +++ /dev/null @@ -1,387 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Standard library utility functions for Chrome EC */ - -#include "common.h" -#include "console.h" -#include "util.h" - -/* - * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll - * use the EC implementation. - */ -__stdlib_compat int strcasecmp(const char *s1, const char *s2) -{ - int diff; - - do { - diff = tolower(*s1) - tolower(*s2); - if (diff) - return diff; - } while (*(s1++) && *(s2++)); - return 0; -} - -/* - * TODO(b/237712836): Remove this conditional once strcasecmp is added to - * Zephyr's libc. - */ -#ifndef CONFIG_ZEPHYR -__stdlib_compat size_t strlen(const char *s) -{ - int len = 0; - - while (*s++) - len++; - - return len; -} - -__stdlib_compat size_t strnlen(const char *s, size_t maxlen) -{ - size_t len = 0; - - while (len < maxlen && *s) { - s++; - len++; - } - return len; -} - -__stdlib_compat size_t strcspn(const char *s, const char *reject) -{ - size_t i; - size_t reject_len = strlen(reject); - - for (i = 0; s[i] != 0; i++) - for (size_t j = 0; j < reject_len; j++) - if (s[i] == reject[j]) - return i; - return i; -} - -__stdlib_compat int isspace(int c) -{ - return c == ' ' || c == '\t' || c == '\r' || c == '\n'; -} - -__stdlib_compat int isdigit(int c) -{ - return c >= '0' && c <= '9'; -} - -__stdlib_compat int isalpha(int c) -{ - return (c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z'); -} - -__stdlib_compat int isupper(int c) -{ - return c >= 'A' && c <= 'Z'; -} - -__stdlib_compat int isprint(int c) -{ - return c >= ' ' && c <= '~'; -} - -__stdlib_compat int tolower(int c) -{ - return c >= 'A' && c <= 'Z' ? c + 'a' - 'A' : c; -} - -__stdlib_compat int strncasecmp(const char *s1, const char *s2, size_t size) -{ - int diff; - - if (!size) - return 0; - - do { - diff = tolower(*s1) - tolower(*s2); - if (diff) - return diff; - } while (*(s1++) && *(s2++) && --size); - return 0; -} - -__stdlib_compat char *strstr(const char *s1, const char *s2) -{ - const char *p, *q, *r; - size_t len1 = strlen(s1); - size_t len2 = strlen(s2); - - if (len1 == 0 || len2 == 0 || len1 < len2) - return NULL; - - r = s1 + len1 - len2 + 1; - for (; s1 < r; s1++) { - if (*s1 == *s2) { - p = s1 + 1; - q = s2 + 1; - for (; q < s2 + len2;) { - if (*p++ != *q++) - break; - } - if (*q == '\0') - return (char *)s1; - } - } - return NULL; -} - -__stdlib_compat unsigned long long int strtoull(const char *nptr, char **endptr, - int base) -{ - uint64_t result = 0; - int c = '\0'; - - while ((c = *nptr++) && isspace(c)) - ; - - if (c == '+') { - c = *nptr++; - } else if (c == '-') { - if (endptr) - *endptr = (char *)nptr - 1; - return result; - } - - base = find_base(base, &c, &nptr); - - while (c) { - if (c >= '0' && c < '0' + MIN(base, 10)) - result = result * base + (c - '0'); - else if (c >= 'A' && c < 'A' + base - 10) - result = result * base + (c - 'A' + 10); - else if (c >= 'a' && c < 'a' + base - 10) - result = result * base + (c - 'a' + 10); - else - break; - - c = *nptr++; - } - - if (endptr) - *endptr = (char *)nptr - 1; - return result; -} -BUILD_ASSERT(sizeof(unsigned long long int) == sizeof(uint64_t)); - -__stdlib_compat int atoi(const char *nptr) -{ - int result = 0; - int neg = 0; - char c = '\0'; - - while ((c = *nptr++) && isspace(c)) - ; - - if (c == '-') { - neg = 1; - c = *nptr++; - } - - while (isdigit(c)) { - result = result * 10 + (c - '0'); - c = *nptr++; - } - - return neg ? -result : result; -} - -__keep __stdlib_compat int memcmp(const void *s1, const void *s2, size_t len) -{ - const char *sa = s1; - const char *sb = s2; - int diff = 0; - - while (len-- > 0) { - diff = *(sa++) - *(sb++); - if (diff) - return diff; - } - - return 0; -} - -#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep __stdlib_compat void *memcpy(void *dest, const void *src, size_t len) -{ - char *d = (char *)dest; - const char *s = (const char *)src; - uint32_t *dw; - const uint32_t *sw; - char *head; - char *const tail = (char *)dest + len; - /* Set 'body' to the last word boundary */ - uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); - - if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { - /* Misaligned. no body, no tail. */ - head = tail; - } else { - /* Aligned */ - if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3)) - /* len is shorter than the first word boundary */ - head = tail; - else - /* Set 'head' to the first word boundary */ - head = (char *)(((uintptr_t)d + 3) & ~3); - } - - /* Copy head */ - while (d < head) - *(d++) = *(s++); - - /* Copy body */ - dw = (uint32_t *)d; - sw = (uint32_t *)s; - while (dw < body) - *(dw++) = *(sw++); - - /* Copy tail */ - d = (char *)dw; - s = (const char *)sw; - while (d < tail) - *(d++) = *(s++); - - return dest; -} -#endif /* address_sanitizer || memory_sanitizer */ - -#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep __stdlib_compat __visible void *memset(void *dest, int c, size_t len) -{ - char *d = (char *)dest; - uint32_t cccc; - uint32_t *dw; - char *head; - char *const tail = (char *)dest + len; - /* Set 'body' to the last word boundary */ - uint32_t *const body = (uint32_t *)((uintptr_t)tail & ~3); - - c &= 0xff; /* Clear upper bits before ORing below */ - cccc = c | (c << 8) | (c << 16) | (c << 24); - - if ((uintptr_t)tail < (((uintptr_t)d + 3) & ~3)) - /* len is shorter than the first word boundary */ - head = tail; - else - /* Set 'head' to the first word boundary */ - head = (char *)(((uintptr_t)d + 3) & ~3); - - /* Copy head */ - while (d < head) - *(d++) = c; - - /* Copy body */ - dw = (uint32_t *)d; - while (dw < body) - *(dw++) = cccc; - - /* Copy tail */ - d = (char *)dw; - while (d < tail) - *(d++) = c; - - return dest; -} -#endif /* address_sanitizer || memory_sanitizer */ - -#if !(__has_feature(address_sanitizer) || __has_feature(memory_sanitizer)) -__keep __stdlib_compat void *memmove(void *dest, const void *src, size_t len) -{ - if ((uintptr_t)dest <= (uintptr_t)src || - (uintptr_t)dest >= (uintptr_t)src + len) { - /* Start of destination doesn't overlap source, so just use - * memcpy(). - */ - return memcpy(dest, src, len); - } else { - /* Need to copy from tail because there is overlap. */ - char *d = (char *)dest + len; - const char *s = (const char *)src + len; - uint32_t *dw; - const uint32_t *sw; - char *head; - char *const tail = (char *)dest; - /* Set 'body' to the last word boundary */ - uint32_t *const body = (uint32_t *)(((uintptr_t)tail + 3) & ~3); - - if (((uintptr_t)dest & 3) != ((uintptr_t)src & 3)) { - /* Misaligned. no body, no tail. */ - head = tail; - } else { - /* Aligned */ - if ((uintptr_t)tail > ((uintptr_t)d & ~3)) - /* Shorter than the first word boundary */ - head = tail; - else - /* Set 'head' to the first word boundary */ - head = (char *)((uintptr_t)d & ~3); - } - - /* Copy head */ - while (d > head) - *(--d) = *(--s); - - /* Copy body */ - dw = (uint32_t *)d; - sw = (uint32_t *)s; - while (dw > body) - *(--dw) = *(--sw); - - /* Copy tail */ - d = (char *)dw; - s = (const char *)sw; - while (d > tail) - *(--d) = *(--s); - - return dest; - } -} -#endif /* address_sanitizer || memory_sanitizer */ - -__stdlib_compat void *memchr(const void *buffer, int c, size_t n) -{ - char *current = (char *)buffer; - char *end = current + n; - - while (current != end) { - if (*current == c) - return current; - current++; - } - return NULL; -} - -__stdlib_compat char *strncpy(char *dest, const char *src, size_t n) -{ - char *d = dest; - - while (n && *src) { - *d++ = *src++; - n--; - } - if (n) - *d = '\0'; - return dest; -} - -__stdlib_compat int strncmp(const char *s1, const char *s2, size_t n) -{ - while (n--) { - if (*s1 != *s2) - return *s1 - *s2; - if (!*s1) - break; - s1++; - s2++; - } - return 0; -} -#endif /* !CONFIG_ZEPHYR */ diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 444e320dad..b3eaefb2a3 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -134,7 +134,11 @@ configure_file(gcov.tmpl.sh ${CMAKE_BINARY_DIR}/gcov.sh) # included here, sorted by filename. This is common functionality which is # supported by all boards and emulators (including unit tests) using the shim # layer. -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c" +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC + # TODO(b/237712836): Remove once + # Zephyr's libc has strcasecmp. + "${PLATFORM_EC}/builtin/stdlib.c" + "${PLATFORM_EC}/common/base32.c" "${PLATFORM_EC}/common/console_output.c" "${PLATFORM_EC}/common/ec_features.c" "${PLATFORM_EC}/common/gpio_commands.c" @@ -145,9 +149,6 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c" "${PLATFORM_EC}/common/system.c" "${PLATFORM_EC}/common/uart_printf.c" "${PLATFORM_EC}/common/util.c" - # TODO(b/237712836): Remove once - # Zephyr's libc has strcasecmp. - "${PLATFORM_EC}/common/util_stdlib.c" "${PLATFORM_EC}/common/version.c") # Now include files that depend on or relate to other CONFIG options, sorted by -- cgit v1.2.1 From 54e603413f987e995486ede3ddccce1aebbe2c93 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 13:17:36 -0700 Subject: Move standard library tests to their own file The standard library functions are being consolidated in stdlib.c, so this test mirrors the same layout. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes Change-Id: I2d7f7671f23a0c4e5f09ef9e0d5d8c25688cd376 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724489 Reviewed-by: Edward Hill --- board/hatch_fp/build.mk | 1 + board/nocturne_fp/build.mk | 1 + board/nucleo-dartmonkey/build.mk | 1 + board/nucleo-f412zg/build.mk | 1 + board/nucleo-h743zi/build.mk | 1 + test/OWNERS | 3 + test/build.mk | 12 +- test/run_device_tests.py | 1 + test/stdlib.c | 393 +++++++++++++++++++++++++++++++++++++++ test/stdlib.tasklist | 9 + test/utils.c | 161 ---------------- test/utils_str.c | 207 --------------------- 12 files changed, 422 insertions(+), 369 deletions(-) create mode 100644 test/stdlib.c create mode 100644 test/stdlib.tasklist diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk index cffb093fc8..cdc2a59993 100644 --- a/board/hatch_fp/build.mk +++ b/board/hatch_fp/build.mk @@ -49,6 +49,7 @@ test-list-y=\ sha256 \ sha256_unrolled \ static_if \ + stdlib \ stm32f_rtc \ system_is_locked \ timer_dos \ diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk index cc985141d1..3401c92b8d 100644 --- a/board/nocturne_fp/build.mk +++ b/board/nocturne_fp/build.mk @@ -49,6 +49,7 @@ test-list-y=\ sha256 \ sha256_unrolled \ static_if \ + stdlib \ system_is_locked \ timer_dos \ utils \ diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk index 4bc677e7e0..67658498a0 100644 --- a/board/nucleo-dartmonkey/build.mk +++ b/board/nucleo-dartmonkey/build.mk @@ -32,6 +32,7 @@ test-list-y=\ sha256 \ sha256_unrolled \ static_if \ + stdlib \ timer_dos \ utils \ utils_str \ diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk index 6d46b6c289..6fa61ee41f 100644 --- a/board/nucleo-f412zg/build.mk +++ b/board/nucleo-f412zg/build.mk @@ -29,6 +29,7 @@ test-list-y=\ sha256 \ sha256_unrolled \ static_if \ + stdlib \ stm32f_rtc \ timer_dos \ utils \ diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk index 1230d9b334..2934125b32 100644 --- a/board/nucleo-h743zi/build.mk +++ b/board/nucleo-h743zi/build.mk @@ -29,6 +29,7 @@ test-list-y=\ sha256 \ sha256_unrolled \ static_if \ + stdlib \ timer_dos \ utils \ utils_str \ diff --git a/test/OWNERS b/test/OWNERS index 6b5302a0fc..7cf6de4ef0 100644 --- a/test/OWNERS +++ b/test/OWNERS @@ -68,6 +68,9 @@ per-file sha256_unrolled.*=file:../common/fpsensor/OWNERS per-file static_if.*=set noparent per-file static_if.*=file:../common/fpsensor/OWNERS +per-file stdlib.*=set noparent +per-file stdlib.*=file:../common/fpsensor/OWNERS + per-file stm32f_rtc.*=set noparent per-file stm32f_rtc.*=file:../common/fpsensor/OWNERS diff --git a/test/build.mk b/test/build.mk index 8c1b4b0d53..afe46453e0 100644 --- a/test/build.mk +++ b/test/build.mk @@ -4,7 +4,15 @@ # found in the LICENSE file. # Device test binaries -test-list-y ?= flash_write_protect pingpong timer_calib timer_dos timer_jump mutex utils utils_str +test-list-y ?= flash_write_protect \ + pingpong \ + stdlib \ + timer_calib \ + timer_dos \ + timer_jump \ + mutex \ + utils \ + utils_str #disable: powerdemo # Emulator tests @@ -83,6 +91,7 @@ test-list-host += sha256_unrolled test-list-host += shmalloc test-list-host += static_if test-list-host += static_if_error +test-list-host += stdlib test-list-host += system test-list-host += thermal test-list-host += timer_dos @@ -218,6 +227,7 @@ sha256-y=sha256.o sha256_unrolled-y=sha256.o shmalloc-y=shmalloc.o static_if-y=static_if.o +stdlib-y=stdlib.o stm32f_rtc-y=stm32f_rtc.o stress-y=stress.o system-y=system.o diff --git a/test/run_device_tests.py b/test/run_device_tests.py index 337e4e6693..8de2fa417c 100755 --- a/test/run_device_tests.py +++ b/test/run_device_tests.py @@ -215,6 +215,7 @@ class AllTests: TestConfig(test_name='sha256'), TestConfig(test_name='sha256_unrolled'), TestConfig(test_name='static_if'), + TestConfig(test_name='stdlib'), TestConfig(config_name='system_is_locked_wp_on', test_name='system_is_locked', test_args=['wp_on'], toggle_power=True, enable_hw_write_protect=True), diff --git a/test/stdlib.c b/test/stdlib.c new file mode 100644 index 0000000000..4d9a4d6f87 --- /dev/null +++ b/test/stdlib.c @@ -0,0 +1,393 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Test standard library functions. + */ + +#include "common.h" +#include "console.h" +#include "system.h" +#include "printf.h" +#include "shared_mem.h" +#include "test_util.h" +#include "timer.h" +#include "util.h" + +static int test_isalpha(void) +{ + TEST_CHECK(isalpha('a')); + TEST_CHECK(isalpha('z')); + TEST_CHECK(isalpha('A')); + TEST_CHECK(isalpha('Z')); + TEST_CHECK(!isalpha('0')); + TEST_CHECK(!isalpha('~')); + TEST_CHECK(!isalpha(' ')); + TEST_CHECK(!isalpha('\0')); + TEST_CHECK(!isalpha('\n')); +} + +static int test_isprint(void) +{ + TEST_CHECK(isprint('a')); + TEST_CHECK(isprint('z')); + TEST_CHECK(isprint('A')); + TEST_CHECK(isprint('Z')); + TEST_CHECK(isprint('0')); + TEST_CHECK(isprint('~')); + TEST_CHECK(isprint(' ')); + TEST_CHECK(!isprint('\0')); + TEST_CHECK(!isprint('\n')); +} + +static int test_strstr(void) +{ + const char s1[] = "abcde"; + + TEST_ASSERT(strstr(s1, "ab") == s1); + TEST_ASSERT(strstr(s1, "") == NULL); + TEST_ASSERT(strstr("", "ab") == NULL); + TEST_ASSERT(strstr("", "x") == NULL); + TEST_ASSERT(strstr(s1, "de") == &s1[3]); + TEST_ASSERT(strstr(s1, "def") == NULL); + + return EC_SUCCESS; +} + +static int test_strtoull(void) +{ + char *e; + + TEST_ASSERT(strtoull("10", &e, 0) == 10); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("010", &e, 0) == 8); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("+010", &e, 0) == 8); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("-010", &e, 0) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31); + TEST_ASSERT(e && (*e == ' ')); + TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31); + TEST_ASSERT(e && (*e == ' ')); + TEST_ASSERT(strtoull("10a", &e, 16) == 266); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("0x02C", &e, 16) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull("0x02C", &e, 0) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull("0X02C", &e, 16) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull("0X02C", &e, 0) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44); + TEST_ASSERT(e && (*e == '\0')); + TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull(" -12", &e, 0) == 0); + TEST_ASSERT(e && (*e == '-')); + TEST_ASSERT(strtoull("!", &e, 0) == 0); + TEST_ASSERT(e && (*e == '!')); + TEST_ASSERT(strtoull("+!", &e, 0) == 0); + TEST_ASSERT(e && (*e == '!')); + TEST_ASSERT(strtoull("+0!", &e, 0) == 0); + TEST_ASSERT(e && (*e == '!')); + TEST_ASSERT(strtoull("+0x!", &e, 0) == 0); + TEST_ASSERT(e && (*e == '!')); + TEST_ASSERT(strtoull("+0X!", &e, 0) == 0); + TEST_ASSERT(e && (*e == '!')); + + return EC_SUCCESS; +} + +static int test_strncpy(void) +{ + char dest[10]; + + strncpy(dest, "test", 10); + TEST_ASSERT_ARRAY_EQ("test", dest, 5); + strncpy(dest, "12345", 6); + TEST_ASSERT_ARRAY_EQ("12345", dest, 6); + strncpy(dest, "testtesttest", 10); + TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10); + + return EC_SUCCESS; +} + +static int test_strncmp(void) +{ + TEST_ASSERT(strncmp("123", "123", 8) == 0); + TEST_ASSERT(strncmp("789", "456", 8) > 0); + TEST_ASSERT(strncmp("abc", "abd", 4) < 0); + TEST_ASSERT(strncmp("abc", "abd", 2) == 0); + return EC_SUCCESS; +} + +static int test_strlen(void) +{ + TEST_CHECK(strlen("this is a string") == 16); +} + +static int test_strnlen(void) +{ + TEST_ASSERT(strnlen("this is a string", 17) == 16); + TEST_ASSERT(strnlen("this is a string", 16) == 16); + TEST_ASSERT(strnlen("this is a string", 5) == 5); + + return EC_SUCCESS; +} + +static int test_strcasecmp(void) +{ + TEST_CHECK(strcasecmp("test string", "TEST strIng") == 0); + TEST_CHECK(strcasecmp("test123!@#", "TesT123!@#") == 0); + TEST_CHECK(strcasecmp("lower", "UPPER") != 0); +} + +static int test_strncasecmp(void) +{ + TEST_CHECK(strncasecmp("test string", "TEST str", 4) == 0); + TEST_CHECK(strncasecmp("test string", "TEST str", 8) == 0); + TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 5) != 0); + TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 4) == 0); + TEST_CHECK(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0); + TEST_CHECK(strncasecmp("1test123", "teststr", 0) == 0); +} + +static int test_atoi(void) +{ + TEST_CHECK(atoi(" 901") == 901); + TEST_CHECK(atoi("-12c") == -12); + TEST_CHECK(atoi(" 0 ") == 0); + TEST_CHECK(atoi("\t111") == 111); +} + +static int test_snprintf(void) +{ + char buffer[32]; + + TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4); + TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer))); +} + +static int test_strcspn(void) +{ + const char str1[] = "abc"; + const char str2[] = "This is a string\nwith newlines!"; + + TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu"); + TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu"); + TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu"); + TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu"); + TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu"); + TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu"); + TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu"); + TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu"); + TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu"); + TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu"); + TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu"); + + TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu"); + TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu"); + TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu"); + TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu"); + TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu"); + TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu"); + + return EC_SUCCESS; +} + +static int test_memmove(void) +{ + int i; + timestamp_t t0, t1, t2, t3; + char *buf; + const int buf_size = 1000; + const int len = 400; + const int iteration = 1000; + + TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); + + for (i = 0; i < len; ++i) + buf[i] = i & 0x7f; + for (i = len; i < buf_size; ++i) + buf[i] = 0; + + t0 = get_time(); + for (i = 0; i < iteration; ++i) + memmove(buf + 101, buf, len); /* unaligned */ + t1 = get_time(); + TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); + + t2 = get_time(); + for (i = 0; i < iteration; ++i) + memmove(buf + 100, buf, len); /* aligned */ + t3 = get_time(); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); + TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len); + + if (!IS_ENABLED(EMU_BUILD)) + TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); + + /* Test small moves */ + memmove(buf + 1, buf, 1); + TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1); + memmove(buf + 5, buf, 4); + memmove(buf + 1, buf, 4); + TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4); + + shared_mem_release(buf); + return EC_SUCCESS; +} + +static int test_memcpy(void) +{ + int i; + timestamp_t t0, t1, t2, t3; + char *buf; + const int buf_size = 1000; + const int len = 400; + const int dest_offset = 500; + const int iteration = 1000; + + TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); + + for (i = 0; i < len; ++i) + buf[i] = i & 0x7f; + for (i = len; i < buf_size; ++i) + buf[i] = 0; + + t0 = get_time(); + for (i = 0; i < iteration; ++i) + memcpy(buf + dest_offset + 1, buf, len); /* unaligned */ + t1 = get_time(); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); + + t2 = get_time(); + for (i = 0; i < iteration; ++i) + memcpy(buf + dest_offset, buf, len); /* aligned */ + t3 = get_time(); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len); + + if (!IS_ENABLED(EMU_BUILD)) + TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); + + memcpy(buf + dest_offset + 1, buf + 1, len - 1); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1); + + /* Test small copies */ + memcpy(buf + dest_offset, buf, 1); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1); + memcpy(buf + dest_offset, buf, 4); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4); + memcpy(buf + dest_offset + 1, buf, 1); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1); + memcpy(buf + dest_offset + 1, buf, 4); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4); + + shared_mem_release(buf); + return EC_SUCCESS; +} + +/* Plain memset, used as a reference to measure speed gain */ +static void *dumb_memset(void *dest, int c, int len) +{ + char *d = (char *)dest; + while (len > 0) { + *(d++) = c; + len--; + } + return dest; +} + +static int test_memset(void) +{ + int i; + timestamp_t t0, t1, t2, t3; + char *buf; + const int buf_size = 1000; + const int len = 400; + const int iteration = 1000; + + TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); + + t0 = get_time(); + for (i = 0; i < iteration; ++i) + dumb_memset(buf, 1, len); + t1 = get_time(); + TEST_ASSERT_MEMSET(buf, (char)1, len); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); + + t2 = get_time(); + for (i = 0; i < iteration; ++i) + memset(buf, 1, len); + t3 = get_time(); + TEST_ASSERT_MEMSET(buf, (char)1, len); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); + + if (!IS_ENABLED(EMU_BUILD)) + TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); + + memset(buf, 128, len); + TEST_ASSERT_MEMSET(buf, (char)128, len); + + memset(buf, -2, len); + TEST_ASSERT_MEMSET(buf, (char)-2, len); + + memset(buf + 1, 1, len - 2); + TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2); + + shared_mem_release(buf); + return EC_SUCCESS; +} + +static int test_memchr(void) +{ + char *buf = "1234"; + + TEST_ASSERT(memchr("123567890", '4', 8) == NULL); + TEST_ASSERT(memchr("123", '3', 2) == NULL); + TEST_ASSERT(memchr(buf, '3', 4) == buf + 2); + TEST_ASSERT(memchr(buf, '4', 4) == buf + 3); + return EC_SUCCESS; +} + +void run_test(int argc, char **argv) +{ + test_reset(); + + RUN_TEST(test_isalpha); + RUN_TEST(test_isprint); + RUN_TEST(test_strstr); + RUN_TEST(test_strtoull); + RUN_TEST(test_strncpy); + RUN_TEST(test_strncmp); + RUN_TEST(test_strlen); + RUN_TEST(test_strnlen); + RUN_TEST(test_strcasecmp); + RUN_TEST(test_strncasecmp); + RUN_TEST(test_atoi); + RUN_TEST(test_snprintf); + RUN_TEST(test_strcspn); + RUN_TEST(test_memmove); + RUN_TEST(test_memcpy); + RUN_TEST(test_memset); + RUN_TEST(test_memchr); + + test_print_result(); +} diff --git a/test/stdlib.tasklist b/test/stdlib.tasklist new file mode 100644 index 0000000000..8131fdd3a2 --- /dev/null +++ b/test/stdlib.tasklist @@ -0,0 +1,9 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST /* No test task */ diff --git a/test/utils.c b/test/utils.c index 88d79d2e55..11298a40c9 100644 --- a/test/utils.c +++ b/test/utils.c @@ -14,163 +14,6 @@ #include "util.h" #include "watchdog.h" -static int test_memmove(void) -{ - int i; - timestamp_t t0, t1, t2, t3; - char *buf; - const int buf_size = 1000; - const int len = 400; - const int iteration = 1000; - - TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); - - for (i = 0; i < len; ++i) - buf[i] = i & 0x7f; - for (i = len; i < buf_size; ++i) - buf[i] = 0; - - t0 = get_time(); - for (i = 0; i < iteration; ++i) - memmove(buf + 101, buf, len); /* unaligned */ - t1 = get_time(); - TEST_ASSERT_ARRAY_EQ(buf + 101, buf, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); - - t2 = get_time(); - for (i = 0; i < iteration; ++i) - memmove(buf + 100, buf, len); /* aligned */ - t3 = get_time(); - ccprintf(" %" PRId64 " us) ", t3.val - t2.val); - TEST_ASSERT_ARRAY_EQ(buf + 100, buf, len); - - if (!IS_ENABLED(EMU_BUILD)) - TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); - - /* Test small moves */ - memmove(buf + 1, buf, 1); - TEST_ASSERT_ARRAY_EQ(buf + 1, buf, 1); - memmove(buf + 5, buf, 4); - memmove(buf + 1, buf, 4); - TEST_ASSERT_ARRAY_EQ(buf + 1, buf + 5, 4); - - shared_mem_release(buf); - return EC_SUCCESS; -} - -static int test_memcpy(void) -{ - int i; - timestamp_t t0, t1, t2, t3; - char *buf; - const int buf_size = 1000; - const int len = 400; - const int dest_offset = 500; - const int iteration = 1000; - - TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); - - for (i = 0; i < len; ++i) - buf[i] = i & 0x7f; - for (i = len; i < buf_size; ++i) - buf[i] = 0; - - t0 = get_time(); - for (i = 0; i < iteration; ++i) - memcpy(buf + dest_offset + 1, buf, len); /* unaligned */ - t1 = get_time(); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); - - t2 = get_time(); - for (i = 0; i < iteration; ++i) - memcpy(buf + dest_offset, buf, len); /* aligned */ - t3 = get_time(); - ccprintf(" %" PRId64 " us) ", t3.val - t2.val); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len); - - if (!IS_ENABLED(EMU_BUILD)) - TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); - - memcpy(buf + dest_offset + 1, buf + 1, len - 1); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf + 1, len - 1); - - /* Test small copies */ - memcpy(buf + dest_offset, buf, 1); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 1); - memcpy(buf + dest_offset, buf, 4); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, 4); - memcpy(buf + dest_offset + 1, buf, 1); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 1); - memcpy(buf + dest_offset + 1, buf, 4); - TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, 4); - - shared_mem_release(buf); - return EC_SUCCESS; -} - -/* Plain memset, used as a reference to measure speed gain */ -static void *dumb_memset(void *dest, int c, int len) -{ - char *d = (char *)dest; - while (len > 0) { - *(d++) = c; - len--; - } - return dest; -} - -static int test_memset(void) -{ - int i; - timestamp_t t0, t1, t2, t3; - char *buf; - const int buf_size = 1000; - const int len = 400; - const int iteration = 1000; - - TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); - - t0 = get_time(); - for (i = 0; i < iteration; ++i) - dumb_memset(buf, 1, len); - t1 = get_time(); - TEST_ASSERT_MEMSET(buf, (char)1, len); - ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); - - t2 = get_time(); - for (i = 0; i < iteration; ++i) - memset(buf, 1, len); - t3 = get_time(); - TEST_ASSERT_MEMSET(buf, (char)1, len); - ccprintf(" %" PRId64 " us) ", t3.val - t2.val); - - if (!IS_ENABLED(EMU_BUILD)) - TEST_ASSERT((t1.val - t0.val) > (t3.val - t2.val)); - - memset(buf, 128, len); - TEST_ASSERT_MEMSET(buf, (char)128, len); - - memset(buf, -2, len); - TEST_ASSERT_MEMSET(buf, (char)-2, len); - - memset(buf + 1, 1, len - 2); - TEST_ASSERT_MEMSET(buf + 1, (char)1, len - 2); - - shared_mem_release(buf); - return EC_SUCCESS; -} - -static int test_memchr(void) -{ - char *buf = "1234"; - - TEST_ASSERT(memchr("123567890", '4', 8) == NULL); - TEST_ASSERT(memchr("123", '3', 2) == NULL); - TEST_ASSERT(memchr(buf, '3', 4) == buf + 2); - TEST_ASSERT(memchr(buf, '4', 4) == buf + 3); - return EC_SUCCESS; -} static int test_uint64divmod_0(void) { @@ -480,10 +323,6 @@ void run_test(int argc, char **argv) { test_reset(); - RUN_TEST(test_memmove); - RUN_TEST(test_memcpy); - RUN_TEST(test_memset); - RUN_TEST(test_memchr); RUN_TEST(test_uint64divmod_0); RUN_TEST(test_uint64divmod_1); RUN_TEST(test_uint64divmod_2); diff --git a/test/utils_str.c b/test/utils_str.c index a855af1886..fa42ff0703 100644 --- a/test/utils_str.c +++ b/test/utils_str.c @@ -13,46 +13,6 @@ #include "timer.h" #include "util.h" -static int test_isalpha(void) -{ - TEST_CHECK(isalpha('a')); - TEST_CHECK(isalpha('z')); - TEST_CHECK(isalpha('A')); - TEST_CHECK(isalpha('Z')); - TEST_CHECK(!isalpha('0')); - TEST_CHECK(!isalpha('~')); - TEST_CHECK(!isalpha(' ')); - TEST_CHECK(!isalpha('\0')); - TEST_CHECK(!isalpha('\n')); -} - -static int test_isprint(void) -{ - TEST_CHECK(isprint('a')); - TEST_CHECK(isprint('z')); - TEST_CHECK(isprint('A')); - TEST_CHECK(isprint('Z')); - TEST_CHECK(isprint('0')); - TEST_CHECK(isprint('~')); - TEST_CHECK(isprint(' ')); - TEST_CHECK(!isprint('\0')); - TEST_CHECK(!isprint('\n')); -} - -static int test_strstr(void) -{ - const char s1[] = "abcde"; - - TEST_ASSERT(strstr(s1, "ab") == s1); - TEST_ASSERT(strstr(s1, "") == NULL); - TEST_ASSERT(strstr("", "ab") == NULL); - TEST_ASSERT(strstr("", "x") == NULL); - TEST_ASSERT(strstr(s1, "de") == &s1[3]); - TEST_ASSERT(strstr(s1, "def") == NULL); - - return EC_SUCCESS; -} - static int test_strtoi(void) { char *e; @@ -111,64 +71,6 @@ static int test_strtoi(void) return EC_SUCCESS; } -static int test_strtoull(void) -{ - char *e; - - TEST_ASSERT(strtoull("10", &e, 0) == 10); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("010", &e, 0) == 8); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("+010", &e, 0) == 8); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("-010", &e, 0) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull("0x1f z", &e, 0) == 31); - TEST_ASSERT(e && (*e == ' ')); - TEST_ASSERT(strtoull("0X1f z", &e, 0) == 31); - TEST_ASSERT(e && (*e == ' ')); - TEST_ASSERT(strtoull("10a", &e, 16) == 266); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("0x02C", &e, 16) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("+0x02C", &e, 16) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("-0x02C", &e, 16) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull("0x02C", &e, 0) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("+0x02C", &e, 0) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("-0x02C", &e, 0) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull("0X02C", &e, 16) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("+0X02C", &e, 16) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("-0X02C", &e, 16) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull("0X02C", &e, 0) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("+0X02C", &e, 0) == 44); - TEST_ASSERT(e && (*e == '\0')); - TEST_ASSERT(strtoull("-0X02C", &e, 0) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull(" -12", &e, 0) == 0); - TEST_ASSERT(e && (*e == '-')); - TEST_ASSERT(strtoull("!", &e, 0) == 0); - TEST_ASSERT(e && (*e == '!')); - TEST_ASSERT(strtoull("+!", &e, 0) == 0); - TEST_ASSERT(e && (*e == '!')); - TEST_ASSERT(strtoull("+0!", &e, 0) == 0); - TEST_ASSERT(e && (*e == '!')); - TEST_ASSERT(strtoull("+0x!", &e, 0) == 0); - TEST_ASSERT(e && (*e == '!')); - TEST_ASSERT(strtoull("+0X!", &e, 0) == 0); - TEST_ASSERT(e && (*e == '!')); - - return EC_SUCCESS; -} - static int test_parse_bool(void) { int v; @@ -202,123 +104,14 @@ static int test_strzcpy(void) return EC_SUCCESS; } -static int test_strncpy(void) -{ - char dest[10]; - - strncpy(dest, "test", 10); - TEST_ASSERT_ARRAY_EQ("test", dest, 5); - strncpy(dest, "12345", 6); - TEST_ASSERT_ARRAY_EQ("12345", dest, 6); - strncpy(dest, "testtesttest", 10); - TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10); - - return EC_SUCCESS; -} - -static int test_strncmp(void) -{ - TEST_ASSERT(strncmp("123", "123", 8) == 0); - TEST_ASSERT(strncmp("789", "456", 8) > 0); - TEST_ASSERT(strncmp("abc", "abd", 4) < 0); - TEST_ASSERT(strncmp("abc", "abd", 2) == 0); - return EC_SUCCESS; -} - -static int test_strlen(void) -{ - TEST_CHECK(strlen("this is a string") == 16); -} - -static int test_strnlen(void) -{ - TEST_ASSERT(strnlen("this is a string", 17) == 16); - TEST_ASSERT(strnlen("this is a string", 16) == 16); - TEST_ASSERT(strnlen("this is a string", 5) == 5); - - return EC_SUCCESS; -} - -static int test_strcasecmp(void) -{ - TEST_CHECK(strcasecmp("test string", "TEST strIng") == 0); - TEST_CHECK(strcasecmp("test123!@#", "TesT123!@#") == 0); - TEST_CHECK(strcasecmp("lower", "UPPER") != 0); -} - -static int test_strncasecmp(void) -{ - TEST_CHECK(strncasecmp("test string", "TEST str", 4) == 0); - TEST_CHECK(strncasecmp("test string", "TEST str", 8) == 0); - TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 5) != 0); - TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 4) == 0); - TEST_CHECK(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0); - TEST_CHECK(strncasecmp("1test123", "teststr", 0) == 0); -} - -static int test_atoi(void) -{ - TEST_CHECK(atoi(" 901") == 901); - TEST_CHECK(atoi("-12c") == -12); - TEST_CHECK(atoi(" 0 ") == 0); - TEST_CHECK(atoi("\t111") == 111); -} - -static int test_snprintf(void) -{ - char buffer[32]; - - TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4); - TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer))); -} - -static int test_strcspn(void) -{ - const char str1[] = "abc"; - const char str2[] = "This is a string\nwith newlines!"; - - TEST_EQ(strcspn(str1, "a"), (size_t)0, "%zu"); - TEST_EQ(strcspn(str1, "b"), (size_t)1, "%zu"); - TEST_EQ(strcspn(str1, "c"), (size_t)2, "%zu"); - TEST_EQ(strcspn(str1, "ccc"), (size_t)2, "%zu"); - TEST_EQ(strcspn(str1, "cba"), (size_t)0, "%zu"); - TEST_EQ(strcspn(str1, "cb"), (size_t)1, "%zu"); - TEST_EQ(strcspn(str1, "bc"), (size_t)1, "%zu"); - TEST_EQ(strcspn(str1, "cbc"), (size_t)1, "%zu"); - TEST_EQ(strcspn(str1, "z"), strlen(str1), "%zu"); - TEST_EQ(strcspn(str1, "xyz"), strlen(str1), "%zu"); - TEST_EQ(strcspn(str1, ""), strlen(str1), "%zu"); - - TEST_EQ(strcspn(str2, " "), (size_t)4, "%zu"); - TEST_EQ(strcspn(str2, "\n"), (size_t)16, "%zu"); - TEST_EQ(strcspn(str2, "\n "), (size_t)4, "%zu"); - TEST_EQ(strcspn(str2, "!"), strlen(str2) - 1, "%zu"); - TEST_EQ(strcspn(str2, "z"), strlen(str2), "%zu"); - TEST_EQ(strcspn(str2, "z!"), strlen(str2) - 1, "%zu"); - - return EC_SUCCESS; -} void run_test(int argc, char **argv) { test_reset(); - RUN_TEST(test_isalpha); - RUN_TEST(test_isprint); - RUN_TEST(test_strstr); RUN_TEST(test_strtoi); - RUN_TEST(test_strtoull); RUN_TEST(test_parse_bool); RUN_TEST(test_strzcpy); - RUN_TEST(test_strncpy); - RUN_TEST(test_strncmp); - RUN_TEST(test_strlen); - RUN_TEST(test_strnlen); - RUN_TEST(test_strcasecmp); - RUN_TEST(test_strncasecmp); - RUN_TEST(test_atoi); - RUN_TEST(test_snprintf); - RUN_TEST(test_strcspn); test_print_result(); } -- cgit v1.2.1 From ff355e3dc31830f70b5ad603c5fce17e1ca012ce Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 15:14:11 -0700 Subject: util: Move stdlib declarations to builtin directory The "builtin" directory is EC's copy of the C standard library headers. Move the declarations for functions that are provided by the standard library to the "builtin" directory. This change makes it easier for future changes to optionally build with the C standard library instead of the standalone EC subset. BRANCH=none BUG=b:172020503, b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I4822e49677e0c0e1b092711b533f2aaa762cb4e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712033 Reviewed-by: Abe Levkoy --- builtin/ctype.h | 16 ++++++++++++++++ builtin/stdlib.c | 10 ++++++++++ builtin/stdlib.h | 11 +++++++++++ builtin/string.h | 24 +++++++++++++++++++----- builtin/strings.h | 14 ++++++++++++++ include/util.h | 55 ++++++++----------------------------------------------- 6 files changed, 78 insertions(+), 52 deletions(-) create mode 100644 builtin/ctype.h create mode 100644 builtin/stdlib.h create mode 100644 builtin/strings.h diff --git a/builtin/ctype.h b/builtin/ctype.h new file mode 100644 index 0000000000..682cc05694 --- /dev/null +++ b/builtin/ctype.h @@ -0,0 +1,16 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CTYPE_H__ +#define __CROS_EC_CTYPE_H__ + +int isdigit(int c); +int isspace(int c); +int isalpha(int c); +int isupper(int c); +int isprint(int c); +int tolower(int c); + +#endif /* __CROS_EC_CTYPE_H__ */ diff --git a/builtin/stdlib.c b/builtin/stdlib.c index e42788c4af..1d07b64869 100644 --- a/builtin/stdlib.c +++ b/builtin/stdlib.c @@ -8,6 +8,16 @@ #include "common.h" #include "console.h" #include "util.h" +/* + * The following macros are defined in stdlib.h in the C standard library, which + * conflict with the definitions in this file. + */ +#undef isspace +#undef isdigit +#undef isalpha +#undef isupper +#undef isprint +#undef tolower /* * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll diff --git a/builtin/stdlib.h b/builtin/stdlib.h new file mode 100644 index 0000000000..fa62a18589 --- /dev/null +++ b/builtin/stdlib.h @@ -0,0 +1,11 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_STDLIB_H__ +#define __CROS_EC_STDLIB_H__ + +int atoi(const char *nptr); + +#endif /* __CROS_EC_STDLIB_H__ */ diff --git a/builtin/string.h b/builtin/string.h index 8c9a71bd75..1e4c45b082 100644 --- a/builtin/string.h +++ b/builtin/string.h @@ -3,10 +3,8 @@ * found in the LICENSE file. */ -/* This header is only needed for CR50 compatibility */ - -#ifndef __CROS_EC_STRINGS_H__ -#define __CROS_EC_STRINGS_H__ +#ifndef __CROS_EC_STRING_H__ +#define __CROS_EC_STRING_H__ #include @@ -20,12 +18,28 @@ void *memmove(void *dest, const void *src, size_t n); void *memset(void *dest, int c, size_t len); void *memchr(const void *buffer, int c, size_t n); +size_t strlen(const char *s); size_t strnlen(const char *s, size_t maxlen); char *strncpy(char *dest, const char *src, size_t n); int strncmp(const char *s1, const char *s2, size_t n); +/** + * Calculates the length of the initial segment of s which consists + * entirely of bytes not in reject. + */ +size_t strcspn(const char *s, const char *reject); + +/** + * Find the first occurrence of the substring in the string + * + * @param s1 String where is searched. + * @param s2 Substring to be located in + * @return Pointer to the located substring or NULL if not found. + */ +char *strstr(const char *s1, const char *s2); + #ifdef __cplusplus } #endif -#endif /* __CROS_EC_STRINGS_H__ */ +#endif /* __CROS_EC_STRING_H__ */ diff --git a/builtin/strings.h b/builtin/strings.h new file mode 100644 index 0000000000..767706d579 --- /dev/null +++ b/builtin/strings.h @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_STRINGS_H__ +#define __CROS_EC_STRINGS_H__ + +#include + +int strcasecmp(const char *s1, const char *s2); +int strncasecmp(const char *s1, const char *s2, size_t size); + +#endif /* __CROS_EC_STRINGS_H__ */ diff --git a/include/util.h b/include/util.h index 8339838abd..28fdb7b9fe 100644 --- a/include/util.h +++ b/include/util.h @@ -13,10 +13,18 @@ #include "panic.h" #include "builtin/assert.h" /* For ASSERT(). */ +#include #include #include +#include +#include +#include #ifdef CONFIG_ZEPHYR #include +/** + * TODO(b/237712836): Remove once Zephyr's libc has strcasecmp. + */ +#include "builtin/strings.h" #endif #ifdef __cplusplus @@ -101,52 +109,6 @@ extern "C" { b = __t__; \ } while (0) -#ifndef HIDE_EC_STDLIB - -/* Standard library functions */ -int atoi(const char *nptr); - -#ifdef CONFIG_ZEPHYR -#include -#include -#else -int isdigit(int c); -int isspace(int c); -int isalpha(int c); -int isupper(int c); -int isprint(int c); -int tolower(int c); - -int memcmp(const void *s1, const void *s2, size_t len); -void *memcpy(void *dest, const void *src, size_t len); -void *memset(void *dest, int c, size_t len); -void *memmove(void *dest, const void *src, size_t len); -void *memchr(const void *buffer, int c, size_t n); - -/** - * Find the first occurrence of the substring in the string - * - * @param s1 String where is searched. - * @param s2 Substring to be located in - * @return Pointer to the located substring or NULL if not found. - */ -char *strstr(const char *s1, const char *s2); - -/** - * Calculates the length of the initial segment of s which consists - * entirely of bytes not in reject. - */ -size_t strcspn(const char *s, const char *reject); - -size_t strlen(const char *s); -char *strncpy(char *dest, const char *src, size_t n); -int strncmp(const char *s1, const char *s2, size_t n); -#endif - -int strcasecmp(const char *s1, const char *s2); -int strncasecmp(const char *s1, const char *s2, size_t size); -size_t strnlen(const char *s, size_t maxlen); - /* Like strtol(), but for integers. */ int strtoi(const char *nptr, char **endptr, int base); @@ -173,7 +135,6 @@ char *strzcpy(char *dest, const char *src, int len); * Other strings return 0 and leave *dest unchanged. */ int parse_bool(const char *s, int *dest); -#endif /* !HIDE_EC_STDLIB */ /** * Constant time implementation of memcmp to avoid timing side channels. -- cgit v1.2.1 From a32330b63cbf94c2314fc7bf62534ba4c7717e0d Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 14:33:32 -0700 Subject: test/stdlib: Disable gcc stringop-truncation warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gcc warns: error: ‘__builtin_strncpy’ output truncated copying 10 bytes from a string of length 12 [-Werror=stringop-truncation] In this case the test is intentionally copying a subset of the string. Also, since it's not obvious, add a note that when building this test for the host we're actually testing the toolchain's C standard library, not the EC "builtin" version. BRANCH=none BUG=b:234181908, b:237823627 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I943de03ae62d7ae5e431809305ae68100e6da418 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3724490 Reviewed-by: Jack Rosenthal --- test/build.mk | 3 +++ test/stdlib.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/test/build.mk b/test/build.mk index afe46453e0..e7cc18d2e8 100644 --- a/test/build.mk +++ b/test/build.mk @@ -91,6 +91,9 @@ test-list-host += sha256_unrolled test-list-host += shmalloc test-list-host += static_if test-list-host += static_if_error +# TODO(b/237823627): When building for the host, we're linking against the +# toolchain's C standard library, so these tests are actually testing the +# toolchain's C standard library. test-list-host += stdlib test-list-host += system test-list-host += thermal diff --git a/test/stdlib.c b/test/stdlib.c index 4d9a4d6f87..cd018af09b 100644 --- a/test/stdlib.c +++ b/test/stdlib.c @@ -120,7 +120,15 @@ static int test_strncpy(void) TEST_ASSERT_ARRAY_EQ("test", dest, 5); strncpy(dest, "12345", 6); TEST_ASSERT_ARRAY_EQ("12345", dest, 6); + /* + * gcc complains: + * error: ‘__builtin_strncpy’ output truncated copying 10 bytes from a + * string of length 12 [-Werror=stringop-truncation] + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstringop-truncation" strncpy(dest, "testtesttest", 10); +#pragma GCC diagnostic pop TEST_ASSERT_ARRAY_EQ("testtestte", dest, 10); return EC_SUCCESS; -- cgit v1.2.1 From 9a3c514b45976907b9bb566cf8eabf1c53a3f040 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Thu, 30 Jun 2022 11:09:50 -0700 Subject: test: Add a test to check if the debugger is connected This is intended to make it easier to debug the behavior of is_debugger_connected(). With JLink we're seeing that C_DEBUGEN is still set even after disconnecting the JLink (see referenced bug). BRANCH=none BUG=b:180945056 TEST=On dragonclaw v0.2 with JLink and servo_micro, flash the "debug" test: Connect the debugger: JLinkExe -device STM32F412CG -if SWD -speed 4000 -autoconnect 1 J-Link>r J-Link>go Run the test on the FPMCU console: > runtest debugger => PASS Disconnect the debugger: J-Link>exit Run the test on the FPMCU console: > runtest no_debugger => PASS TEST=On icetower v0.1 with JLink and servo_micro, flash the "debug" test: Connect the debugger: JLinkExe -device STM32H743ZI -if SWD -speed 4000 -autoconnect 1 J-Link>r J-Link>go Run the test on the FPMCU console: > runtest debugger => PASS Physically disconnect the debugger and servo_micro. Then reconnect servo_micro and start servod. Run the test on the FPMCU console: > runtest no_debugger => PASS Signed-off-by: Tom Hughes Change-Id: I544cab5814a30310345d4337a818d7b48cc22a8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739316 Reviewed-by: Bobby Casey --- board/hatch_fp/build.mk | 1 + board/nocturne_fp/build.mk | 1 + board/nucleo-dartmonkey/build.mk | 1 + board/nucleo-f412zg/build.mk | 1 + board/nucleo-h743zi/build.mk | 1 + test/build.mk | 1 + test/debug.c | 48 ++++++++++++++++++++++++++++++++++++++++ test/debug.tasklist | 9 ++++++++ 8 files changed, 63 insertions(+) create mode 100644 test/debug.c create mode 100644 test/debug.tasklist diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk index cdc2a59993..caac6f5822 100644 --- a/board/hatch_fp/build.mk +++ b/board/hatch_fp/build.mk @@ -31,6 +31,7 @@ test-list-y=\ compile_time_macros \ cortexm_fpu \ crc \ + debug \ flash_physical \ flash_write_protect \ fpsensor \ diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk index 3401c92b8d..c24b9a0d0d 100644 --- a/board/nocturne_fp/build.mk +++ b/board/nocturne_fp/build.mk @@ -31,6 +31,7 @@ test-list-y=\ compile_time_macros \ cortexm_fpu \ crc \ + debug \ flash_physical \ flash_write_protect \ fpsensor \ diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk index 67658498a0..dc3f1139ef 100644 --- a/board/nucleo-dartmonkey/build.mk +++ b/board/nucleo-dartmonkey/build.mk @@ -15,6 +15,7 @@ test-list-y=\ cec \ compile_time_macros \ crc \ + debug \ flash_physical \ flash_write_protect \ fpsensor \ diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk index 6fa61ee41f..64a3472e5e 100644 --- a/board/nucleo-f412zg/build.mk +++ b/board/nucleo-f412zg/build.mk @@ -14,6 +14,7 @@ test-list-y=\ cec \ compile_time_macros \ crc \ + debug \ flash_physical \ flash_write_protect \ mpu \ diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk index 2934125b32..b961c4841e 100644 --- a/board/nucleo-h743zi/build.mk +++ b/board/nucleo-h743zi/build.mk @@ -14,6 +14,7 @@ test-list-y=\ cec \ compile_time_macros \ crc \ + debug \ flash_physical \ flash_write_protect \ mpu \ diff --git a/test/build.mk b/test/build.mk index e7cc18d2e8..10e8f720f1 100644 --- a/test/build.mk +++ b/test/build.mk @@ -174,6 +174,7 @@ compile_time_macros-y=compile_time_macros.o console_edit-y=console_edit.o cortexm_fpu-y=cortexm_fpu.o crc-y=crc.o +debug-y=debug.o entropy-y=entropy.o extpwr_gpio-y=extpwr_gpio.o fan-y=fan.o diff --git a/test/debug.c b/test/debug.c new file mode 100644 index 0000000000..0e4676b8b1 --- /dev/null +++ b/test/debug.c @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "debug.h" +#include "string.h" +#include "test_util.h" + +static bool debugger_connected; + +static void print_usage(void) +{ + ccprintf("usage: runtest [debugger|no_debugger]\n"); +} + +test_static int test_debugger_is_connected(void) +{ + ccprintf("debugger_is_connected: %d\n", debugger_connected); + TEST_EQ(debugger_is_connected(), debugger_connected, "%d"); + return EC_SUCCESS; +} + + +void run_test(int argc, char **argv) +{ + test_reset(); + + if (argc < 2) { + print_usage(); + test_fail(); + return; + } + + if (strncmp(argv[1], "debugger", sizeof("debugger")) == 0) + debugger_connected = true; + else if (strncmp(argv[1], "no_debugger", sizeof("no_debugger")) == 0) { + debugger_connected = false; + } else { + print_usage(); + test_fail(); + return; + } + + RUN_TEST(test_debugger_is_connected); + test_print_result(); +} diff --git a/test/debug.tasklist b/test/debug.tasklist new file mode 100644 index 0000000000..026dc51e90 --- /dev/null +++ b/test/debug.tasklist @@ -0,0 +1,9 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST -- cgit v1.2.1 From 7eab3811962cde5b5c66a5952a4f7d9b1b41cd67 Mon Sep 17 00:00:00 2001 From: Bobby Casey Date: Wed, 6 Jul 2022 15:03:00 -0400 Subject: test: Remove TEST_CHECK macro The TEST_CHECK macro returns a value (from the calling function) on either success or failure. This differs from all other TEST_* macros in test_util.h, which only return on failure. Returning on failure is appropriate and allows short circuiting a test on the first failure but returning on success results in short circuiting after the first successful check and bypassing subsequent checks. This behavior is somewhat confusing and easy to miss during review. BRANCH=none BUG=b:238120333 TEST=make runhosttests TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Bobby Casey Change-Id: I3777b427aa5e20a91689f86fc37daadffacf27f3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748830 Reviewed-by: Tom Hughes Reviewed-by: Jack Rosenthal --- docs/zephyr/ztest.md | 1 - include/test_util.h | 8 ------ test/console_edit.c | 33 +++++++++++++++-------- test/flash.c | 9 ++++--- test/kb_8042.c | 3 ++- test/kb_scan.c | 6 +++-- test/stdlib.c | 75 ++++++++++++++++++++++++++++------------------------ test/utils.c | 9 ++++--- 8 files changed, 80 insertions(+), 64 deletions(-) diff --git a/docs/zephyr/ztest.md b/docs/zephyr/ztest.md index 6bb121045d..d782631cc3 100644 --- a/docs/zephyr/ztest.md +++ b/docs/zephyr/ztest.md @@ -142,7 +142,6 @@ find-and-replace. * `TEST_BITS_CLEARED(a, bits)` to `zassert_true(a & (int)bits == 0, "%u, 0", a & (int)bits)` * `TEST_ASSERT_ARRAY_EQ(s, d, n)` to `zassert_mem_equal(s, d, b, NULL)` -* `TEST_CHECK(n)` to `zassert_true(n, NULL)` * `TEST_NEAR(a, b, epsilon, fmt)` to `zassert_within(a, b, epsilon, fmt, a)` * Currently, every usage of `TEST_NEAR` involves floating point values * `TEST_ASSERT_ABS_LESS(n, t)` to `zassert_true(abs(n) < t, "%d, %d", n, t)` diff --git a/include/test_util.h b/include/test_util.h index 03058fdaaf..66513f6513 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -107,14 +107,6 @@ } \ } while (0) -#define TEST_CHECK(n) \ - do { \ - if (n) \ - return EC_SUCCESS; \ - else \ - return EC_ERROR_UNKNOWN; \ - } while (0) - /* Mutlistep test states */ enum test_state_t { TEST_STATE_STEP_1 = 0, diff --git a/test/console_edit.c b/test/console_edit.c index e949073f16..fb49e9c41c 100644 --- a/test/console_edit.c +++ b/test/console_edit.c @@ -98,7 +98,8 @@ static int test_backspace(void) cmd_1_call_cnt = 0; UART_INJECT("testx\b1\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_insert_char(void) @@ -108,7 +109,8 @@ static int test_insert_char(void) arrow_key(ARROW_LEFT, 2); UART_INJECT("s\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_delete_char(void) @@ -118,7 +120,8 @@ static int test_delete_char(void) arrow_key(ARROW_LEFT, 1); UART_INJECT("\b\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_insert_delete_char(void) @@ -130,7 +133,8 @@ static int test_insert_delete_char(void) arrow_key(ARROW_RIGHT, 1); UART_INJECT("s\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_home_end_key(void) @@ -142,7 +146,8 @@ static int test_home_end_key(void) end_key(); UART_INJECT("1\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_ctrl_k(void) @@ -153,7 +158,8 @@ static int test_ctrl_k(void) ctrl_key('K'); UART_INJECT("\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1); + return EC_SUCCESS; } static int test_history_up(void) @@ -164,7 +170,8 @@ static int test_history_up(void) arrow_key(ARROW_UP, 1); UART_INJECT("\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 2); + TEST_ASSERT(cmd_1_call_cnt == 2); + return EC_SUCCESS; } static int test_history_up_up(void) @@ -178,7 +185,8 @@ static int test_history_up_up(void) arrow_key(ARROW_UP, 2); UART_INJECT("\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 2 && cmd_2_call_cnt == 1); + return EC_SUCCESS; } static int test_history_up_up_down(void) @@ -193,7 +201,8 @@ static int test_history_up_up_down(void) arrow_key(ARROW_DOWN, 1); UART_INJECT("\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2); + TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 2); + return EC_SUCCESS; } static int test_history_edit(void) @@ -205,7 +214,8 @@ static int test_history_edit(void) arrow_key(ARROW_UP, 1); UART_INJECT("\b2\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1); + return EC_SUCCESS; } static int test_history_stash(void) @@ -219,7 +229,8 @@ static int test_history_stash(void) arrow_key(ARROW_DOWN, 1); UART_INJECT("2\n"); msleep(30); - TEST_CHECK(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1); + TEST_ASSERT(cmd_1_call_cnt == 1 && cmd_2_call_cnt == 1); + return EC_SUCCESS; } static int test_history_list(void) diff --git a/test/flash.c b/test/flash.c index a5f25fb164..c571c4e05f 100644 --- a/test/flash.c +++ b/test/flash.c @@ -351,10 +351,11 @@ static int test_flash_info(void) TEST_ASSERT(test_send_host_command(EC_CMD_FLASH_INFO, 1, NULL, 0, &resp, sizeof(resp)) == EC_RES_SUCCESS); - TEST_CHECK((resp.flash_size == CONFIG_FLASH_SIZE_BYTES) && - (resp.write_block_size == CONFIG_FLASH_WRITE_SIZE) && - (resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE) && - (resp.protect_block_size == CONFIG_FLASH_BANK_SIZE)); + TEST_ASSERT(resp.flash_size == CONFIG_FLASH_SIZE_BYTES); + TEST_ASSERT(resp.write_block_size == CONFIG_FLASH_WRITE_SIZE); + TEST_ASSERT(resp.erase_block_size == CONFIG_FLASH_ERASE_SIZE); + TEST_ASSERT(resp.protect_block_size == CONFIG_FLASH_BANK_SIZE); + return EC_SUCCESS; } static int test_region_info(void) diff --git a/test/kb_8042.c b/test/kb_8042.c index 0bd0c273c4..1a3681aa28 100644 --- a/test/kb_8042.c +++ b/test/kb_8042.c @@ -114,7 +114,8 @@ static int __verify_no_char(void) { lpc_char_cnt = 0; msleep(30); - TEST_CHECK(lpc_char_cnt == 0); + TEST_ASSERT(lpc_char_cnt == 0); + return EC_SUCCESS; } #define VERIFY_NO_CHAR() TEST_ASSERT(__verify_no_char() == EC_SUCCESS) diff --git a/test/kb_scan.c b/test/kb_scan.c index b36f868b8e..57d16bc73d 100644 --- a/test/kb_scan.c +++ b/test/kb_scan.c @@ -544,12 +544,14 @@ static int lid_test(void) static int test_check_boot_esc(void) { - TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC); + TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_ESC); + return EC_SUCCESS; } static int test_check_boot_down(void) { - TEST_CHECK(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW); + TEST_ASSERT(keyboard_scan_get_boot_keys() == BOOT_KEY_DOWN_ARROW); + return EC_SUCCESS; } void test_init(void) diff --git a/test/stdlib.c b/test/stdlib.c index cd018af09b..89ba90b54d 100644 --- a/test/stdlib.c +++ b/test/stdlib.c @@ -16,28 +16,30 @@ static int test_isalpha(void) { - TEST_CHECK(isalpha('a')); - TEST_CHECK(isalpha('z')); - TEST_CHECK(isalpha('A')); - TEST_CHECK(isalpha('Z')); - TEST_CHECK(!isalpha('0')); - TEST_CHECK(!isalpha('~')); - TEST_CHECK(!isalpha(' ')); - TEST_CHECK(!isalpha('\0')); - TEST_CHECK(!isalpha('\n')); + TEST_ASSERT(isalpha('a')); + TEST_ASSERT(isalpha('z')); + TEST_ASSERT(isalpha('A')); + TEST_ASSERT(isalpha('Z')); + TEST_ASSERT(!isalpha('0')); + TEST_ASSERT(!isalpha('~')); + TEST_ASSERT(!isalpha(' ')); + TEST_ASSERT(!isalpha('\0')); + TEST_ASSERT(!isalpha('\n')); + return EC_SUCCESS; } static int test_isprint(void) { - TEST_CHECK(isprint('a')); - TEST_CHECK(isprint('z')); - TEST_CHECK(isprint('A')); - TEST_CHECK(isprint('Z')); - TEST_CHECK(isprint('0')); - TEST_CHECK(isprint('~')); - TEST_CHECK(isprint(' ')); - TEST_CHECK(!isprint('\0')); - TEST_CHECK(!isprint('\n')); + TEST_ASSERT(isprint('a')); + TEST_ASSERT(isprint('z')); + TEST_ASSERT(isprint('A')); + TEST_ASSERT(isprint('Z')); + TEST_ASSERT(isprint('0')); + TEST_ASSERT(isprint('~')); + TEST_ASSERT(isprint(' ')); + TEST_ASSERT(!isprint('\0')); + TEST_ASSERT(!isprint('\n')); + return EC_SUCCESS; } static int test_strstr(void) @@ -145,7 +147,8 @@ static int test_strncmp(void) static int test_strlen(void) { - TEST_CHECK(strlen("this is a string") == 16); + TEST_ASSERT(strlen("this is a string") == 16); + return EC_SUCCESS; } static int test_strnlen(void) @@ -159,35 +162,39 @@ static int test_strnlen(void) static int test_strcasecmp(void) { - TEST_CHECK(strcasecmp("test string", "TEST strIng") == 0); - TEST_CHECK(strcasecmp("test123!@#", "TesT123!@#") == 0); - TEST_CHECK(strcasecmp("lower", "UPPER") != 0); + TEST_ASSERT(strcasecmp("test string", "TEST strIng") == 0); + TEST_ASSERT(strcasecmp("test123!@#", "TesT123!@#") == 0); + TEST_ASSERT(strcasecmp("lower", "UPPER") != 0); + return EC_SUCCESS; } static int test_strncasecmp(void) { - TEST_CHECK(strncasecmp("test string", "TEST str", 4) == 0); - TEST_CHECK(strncasecmp("test string", "TEST str", 8) == 0); - TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 5) != 0); - TEST_CHECK(strncasecmp("test123!@#", "TesT321!@#", 4) == 0); - TEST_CHECK(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0); - TEST_CHECK(strncasecmp("1test123", "teststr", 0) == 0); + TEST_ASSERT(strncasecmp("test string", "TEST str", 4) == 0); + TEST_ASSERT(strncasecmp("test string", "TEST str", 8) == 0); + TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 5) != 0); + TEST_ASSERT(strncasecmp("test123!@#", "TesT321!@#", 4) == 0); + TEST_ASSERT(strncasecmp("1test123!@#", "1TesT321!@#", 5) == 0); + TEST_ASSERT(strncasecmp("1test123", "teststr", 0) == 0); + return EC_SUCCESS; } static int test_atoi(void) { - TEST_CHECK(atoi(" 901") == 901); - TEST_CHECK(atoi("-12c") == -12); - TEST_CHECK(atoi(" 0 ") == 0); - TEST_CHECK(atoi("\t111") == 111); + TEST_ASSERT(atoi(" 901") == 901); + TEST_ASSERT(atoi("-12c") == -12); + TEST_ASSERT(atoi(" 0 ") == 0); + TEST_ASSERT(atoi("\t111") == 111); + return EC_SUCCESS; } static int test_snprintf(void) { char buffer[32]; - TEST_CHECK(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4); - TEST_CHECK(strncmp(buffer, "1234", sizeof(buffer))); + TEST_ASSERT(snprintf(buffer, sizeof(buffer), "%u", 1234) == 4); + TEST_ASSERT(strncmp(buffer, "1234", sizeof(buffer)) == 0); + return EC_SUCCESS; } static int test_strcspn(void) diff --git a/test/utils.c b/test/utils.c index 11298a40c9..d5bdcf6b4e 100644 --- a/test/utils.c +++ b/test/utils.c @@ -21,7 +21,8 @@ static int test_uint64divmod_0(void) int d = 54870071; int r = uint64divmod(&n, d); - TEST_CHECK(r == 5991285 && n == 156134415ULL); + TEST_ASSERT(r == 5991285 && n == 156134415ULL); + return EC_SUCCESS; } static int test_uint64divmod_1(void) @@ -30,7 +31,8 @@ static int test_uint64divmod_1(void) int d = 2; int r = uint64divmod(&n, d); - TEST_CHECK(r == 0 && n == 4283553221292375ULL); + TEST_ASSERT(r == 0 && n == 4283553221292375ULL); + return EC_SUCCESS; } static int test_uint64divmod_2(void) @@ -39,7 +41,8 @@ static int test_uint64divmod_2(void) int d = 0; int r = uint64divmod(&n, d); - TEST_CHECK(r == 0 && n == 0ULL); + TEST_ASSERT(r == 0 && n == 0ULL); + return EC_SUCCESS; } static int test_get_next_bit(void) -- cgit v1.2.1 From c25ffdb3164b0421d73f5258a71f3d371bfea623 Mon Sep 17 00:00:00 2001 From: Bobby Casey Date: Thu, 16 Jun 2022 17:32:06 -0400 Subject: common: Conditionally support printf %l and %i modifiers The libfp library prints some values with PRIx32 or PRId32 format specifiers which, in their compilation environment, output "%lx" and "%ld". Unfortunately, support for printing any '%l' format in EC code was deprecated in issuetracker.google.com/issues/172210614 after changing it from it being treated as a hard-coded 64-bit length. There was concern that new code using %l with 32-bit values would be cherry-picked to older branches without the updated printf. In these cases, the older code would interpret that %l as 64-bit argument, causing it to over-ingest arguments and potentially behave in an undefined manner. Printing 32-bit values with "%l" or "%i" is safe as long as we can guarantee no legacy code will attempt to print using "%l" with a 64-bit value. The logic here is protected by a config flag that is only enabled for FPMCU and FPMCU doesn't use long running release branches. A printf test is also added to ensure that only dartmonkey and bloonchipper boards have long32 enabled. BRANCH=none BUG=b:234781655 BUG=b:234143158 TEST=./test/run_device_tests.py -b dartmonkey -t printf TEST=./test/run_device_tests.py -b bloonchipper -t printf TEST=make runhosttests Signed-off-by: Bobby Casey Change-Id: If432f507a31cc12a4c5c4bdcd07c6141407bd70d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3707743 Reviewed-by: Andrea Grandi Reviewed-by: Tom Hughes --- baseboard/nucleo-f412zg/base-board.h | 2 +- baseboard/nucleo-h743zi/base-board.h | 2 +- board/hatch_fp/board.h | 2 +- board/nocturne_fp/board.h | 2 +- builtin/stdint.h | 6 ++ common/printf.c | 26 ++++---- include/config.h | 8 ++- include/printf.h | 2 +- test/printf.c | 120 +++++++++++++++++++++++++++++++---- util/config_allowed.txt | 2 +- 10 files changed, 140 insertions(+), 32 deletions(-) diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h index b104621ec7..bd5710e247 100644 --- a/baseboard/nucleo-f412zg/base-board.h +++ b/baseboard/nucleo-f412zg/base-board.h @@ -164,7 +164,7 @@ #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_RNG #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED diff --git a/baseboard/nucleo-h743zi/base-board.h b/baseboard/nucleo-h743zi/base-board.h index 10f780505d..f96ba41bcc 100644 --- a/baseboard/nucleo-h743zi/base-board.h +++ b/baseboard/nucleo-h743zi/base-board.h @@ -92,7 +92,7 @@ #define CONFIG_LOW_POWER_IDLE #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_RNG #define CONFIG_RWSIG_TYPE_RWSIG #define CONFIG_SHA256 diff --git a/board/hatch_fp/board.h b/board/hatch_fp/board.h index 2702152576..a4c4e2923b 100644 --- a/board/hatch_fp/board.h +++ b/board/hatch_fp/board.h @@ -230,7 +230,7 @@ #define CONFIG_HOST_COMMAND_STATUS #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_RNG #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED diff --git a/board/nocturne_fp/board.h b/board/nocturne_fp/board.h index 5b12d05321..2d0f5586cf 100644 --- a/board/nocturne_fp/board.h +++ b/board/nocturne_fp/board.h @@ -106,7 +106,7 @@ #undef CONFIG_LID_SWITCH #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_GPIO -#define CONFIG_PRINTF_LEGACY_LI_FORMAT +#define CONFIG_PRINTF_LONG_IS_32BITS #define CONFIG_SHA256 #define CONFIG_SHA256_UNROLLED #define CONFIG_SPI diff --git a/builtin/stdint.h b/builtin/stdint.h index 87993d8e2d..f47c9e6422 100644 --- a/builtin/stdint.h +++ b/builtin/stdint.h @@ -67,6 +67,9 @@ typedef int64_t int_fast64_t; #ifndef INT32_MAX #define INT32_MAX (2147483647U) #endif +#ifndef INT32_MIN +#define INT32_MIN (-2147483648) +#endif #ifndef UINT64_C #define UINT64_C(c) c##ULL @@ -81,5 +84,8 @@ typedef int64_t int_fast64_t; #ifndef INT64_MAX #define INT64_MAX INT64_C(9223372036854775807) #endif +#ifndef INT64_MIN +#define INT64_MIN (INT64_C(-9223372036854775807) - 1) +#endif #endif /* __CROS_EC_STDINT_H__ */ diff --git a/common/printf.c b/common/printf.c index 9fbac19e20..5102dd8f20 100644 --- a/common/printf.c +++ b/common/printf.c @@ -224,7 +224,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, /* * Handle length: - * %l - DEPRECATED (see below) + * %l - supports 64-bit longs, 32-bit longs are + * supported with a config flag, see comment + * below for more details * %ll - long long * %z - size_t */ @@ -239,18 +241,23 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, } /* - * %l on 32-bit systems is deliberately - * deprecated. It was originally used as - * shorthand for 64-bit values. When + * The CONFIG_PRINTF_LONG_IS_32BITS flag is + * required to enable the %l flag on systems + * where it would signify a 32-bit value. + * Otherwise, %l on 32-bit systems is + * deliberately deprecated. %l was originally + * used as shorthand for 64-bit values. When * compile-time printf format checking was * enabled, it had to be cleaned up to be * sizeof(long), which is 32 bits on today's * ECs. This presents a mismatch which can be * dangerous if a new-style printf call is * cherry-picked into an old firmware branch. - * See crbug.com/984041 for more context. + * For more context, see + * https://issuetracker.google.com/issues/172210614 */ - if (!(flags & PF_64BIT)) { + if (!IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS) + && !(flags & PF_64BIT)) { format = error_str; continue; } @@ -336,12 +343,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, } switch (c) { -#ifdef CONFIG_PRINTF_LEGACY_LI_FORMAT +#ifdef CONFIG_PRINTF_LONG_IS_32BITS case 'i': - /* force 32-bit for compatibility */ - flags &= ~PF_64BIT; - /* fall-through */ -#endif /* CONFIG_PRINTF_LEGACY_LI_FORMAT */ +#endif /* CONFIG_PRINTF_LONG_IS_32BITS */ case 'd': if (flags & PF_64BIT) { if ((int64_t)v < 0) { diff --git a/include/config.h b/include/config.h index bcf070f82f..70dc284a8f 100644 --- a/include/config.h +++ b/include/config.h @@ -3639,10 +3639,12 @@ #undef CONFIG_POWER_TRACK_HOST_SLEEP_STATE /* - * Implement the '%li' printf format as a *32-bit* integer format, - * as it might be expected by non-EC code. + * Allow the use of the "long" printf length modifier ('l') to be in 32-bit + * systems along with any supported conversion specifiers. Note that this also + * reenables support for the 'i' printf format. This config will only take + * effect if sizeof(long) == sizeof(uint32_t). */ -#undef CONFIG_PRINTF_LEGACY_LI_FORMAT +#undef CONFIG_PRINTF_LONG_IS_32BITS /* * On x86 systems, define this option if the CPU_PROCHOT signal is active low. diff --git a/include/printf.h b/include/printf.h index 8eed1618f8..333e622b7b 100644 --- a/include/printf.h +++ b/include/printf.h @@ -51,7 +51,7 @@ * - 'c' - character * - 's' - null-terminated ASCII string * - 'd' - signed integer - * - 'i' - signed integer if CONFIG_PRINTF_LEGACY_LI_FORMAT is set (ignore l) + * - 'i' - signed integer (if CONFIG_PRINTF_LONG_IS_32BITS is enabled) * - 'u' - unsigned integer * - 'x' - unsigned integer, print as lower-case hexadecimal * - 'X' - unsigned integer, print as upper-case hexadecimal diff --git a/test/printf.c b/test/printf.c index 83d03c210f..388e0c7e80 100644 --- a/test/printf.c +++ b/test/printf.c @@ -171,23 +171,118 @@ test_static int test_vsnprintf_int(void) T(expect_success("5e", "%x", 0X5E)); T(expect_success("5E", "%X", 0X5E)); + return EC_SUCCESS; +} + +test_static int test_printf_long32_enabled(void) +{ + bool use_l32 = IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS); + + if (IS_ENABLED(BOARD_BLOONCHIPPER) || IS_ENABLED(BOARD_DARTMONKEY)) + TEST_ASSERT(use_l32); + else + TEST_ASSERT(!use_l32); + return EC_SUCCESS; +} + +test_static int test_vsnprintf_32bit_long_supported(void) +{ + long long_min = INT32_MIN; + long long_max = INT32_MAX; + unsigned long ulong_max = UINT32_MAX; + char const *long_min_str = "-2147483648"; + char const *long_max_str = "2147483647"; + char const *ulong_max_str = "4294967295"; + char const *long_min_hexstr = "80000000"; + char const *long_max_hexstr = "7fffffff"; + char const *ulong_max_hexstr = "ffffffff"; + + T(expect_success(long_min_str, "%ld", long_min)); + T(expect_success(long_min_hexstr, "%lx", long_min)); + T(expect_success(long_max_str, "%ld", long_max)); + T(expect_success(long_max_hexstr, "%lx", long_max)); + T(expect_success(ulong_max_str, "%lu", ulong_max)); + T(expect_success(ulong_max_hexstr, "%lx", ulong_max)); + T(expect_success(long_max_str, "%ld", long_max)); + + T(expect_success(" +123", "%+*ld", 5, 123)); + T(expect_success("00000123", "%08lu", 123)); + T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); + /* - * %l is deprecated on 32-bit systems (see crbug.com/984041), but is - * is still functional on 64-bit systems. + * %i and %li are only supported via the CONFIG_PRINTF_LONG_IS_32BITS + * configuration (see https://issuetracker.google.com/issues/172210614). */ - if (sizeof(long) == sizeof(uint32_t)) { - T(expect_success(err_str, "%lx", 0x7b)); - T(expect_success(err_str, "%08lu", 0x7b)); - T(expect_success("13ERROR", "%d%lu", 13, 14)); - } else { - T(expect_success("7b", "%lx", 0x7b)); - T(expect_success("00000123", "%08lu", 123)); - T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); - } + T(expect_success("123", "%i", 123)); + T(expect_success("123", "%li", 123)); + + return EC_SUCCESS; +} + +test_static int test_vsnprintf_64bit_long_supported(void) +{ + /* These lines are only executed when sizeof(long) is 64-bits but are + * still compiled by systems with 32-bit longs, so the casts are needed + * to avoid compilation errors. + */ + long long_min = (long)INT64_MIN; + long long_max = (long)INT64_MAX; + unsigned long ulong_max = (unsigned long)UINT64_MAX; + char const *long_min_str = "-9223372036854775808"; + char const *long_max_str = "9223372036854775807"; + char const *ulong_max_str = "18446744073709551615"; + char const *long_min_hexstr = "8000000000000000"; + char const *long_max_hexstr = "7fffffffffffffff"; + char const *ulong_max_hexstr = "ffffffffffffffff"; + + T(expect_success(long_min_str, "%ld", long_min)); + T(expect_success(long_min_hexstr, "%lx", long_min)); + T(expect_success(long_max_str, "%ld", long_max)); + T(expect_success(long_max_hexstr, "%lx", long_max)); + T(expect_success(ulong_max_str, "%lu", ulong_max)); + T(expect_success(ulong_max_hexstr, "%lx", ulong_max)); + T(expect_success(long_max_str, "%ld", long_max)); + + T(expect_success(" +123", "%+*ld", 5, 123)); + T(expect_success("00000123", "%08lu", 123)); + T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); + + T(expect_success(err_str, "%i", 123)); + T(expect_success(err_str, "%li", 123)); return EC_SUCCESS; } +test_static int test_vsnprintf_long_not_supported(void) +{ + T(expect_success(err_str, "%ld", 0x7b)); + T(expect_success(err_str, "%li", 0x7b)); + T(expect_success(err_str, "%lu", 0x7b)); + T(expect_success(err_str, "%lx", 0x7b)); + T(expect_success(err_str, "%08lu", 123)); + T(expect_success("13ERROR", "%d%lu%d", 13, 14L, 15)); + + T(expect_success(err_str, "%i", 123)); + T(expect_success(err_str, "%li", 123)); + + return EC_SUCCESS; +} + +test_static int test_vsnprintf_long(void) +{ + /* + * %l is functional on 64-bit systems but is not supported on 32-bit + * systems (see https://issuetracker.google.com/issues/172210614) unless + * explicitly enabled via configuration. + */ + if (IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS)) + return test_vsnprintf_32bit_long_supported(); + else if (sizeof(long) == sizeof(uint64_t)) + return test_vsnprintf_64bit_long_supported(); + else + return test_vsnprintf_long_not_supported(); +} + test_static int test_vsnprintf_pointers(void) { void *ptr = (void *)0x55005E00; @@ -288,12 +383,13 @@ void run_test(int argc, char **argv) RUN_TEST(test_vsnprintf_args); RUN_TEST(test_vsnprintf_int); + RUN_TEST(test_printf_long32_enabled); + RUN_TEST(test_vsnprintf_long); RUN_TEST(test_vsnprintf_pointers); RUN_TEST(test_vsnprintf_chars); RUN_TEST(test_vsnprintf_strings); RUN_TEST(test_vsnprintf_timestamps); RUN_TEST(test_vsnprintf_hexdump); RUN_TEST(test_vsnprintf_combined); - test_print_result(); } diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 58317b8384..0e352e7602 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -716,7 +716,7 @@ CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD CONFIG_POWER_SIGNAL_RUNTIME_CONFIG CONFIG_POWER_TRACK_HOST_SLEEP_STATE CONFIG_PRESERVE_LOGS -CONFIG_PRINTF_LEGACY_LI_FORMAT +CONFIG_PRINTF_LONG_IS_32BITS CONFIG_PRINT_IN_INT CONFIG_PROGRAM_MEMORY_BASE CONFIG_PROGRAM_MEMORY_BASE_LOAD -- cgit v1.2.1 From fae8d87d3a8802fa44ff548da191c60d8dbedeae Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:41 -0600 Subject: chip/stm32/registers.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic76151cfe4fd7b211b9a065befe67224bb8d6d64 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729535 Reviewed-by: Jeremy Bettis --- chip/stm32/registers.h | 649 ++++++++++++++++++++++++------------------------- 1 file changed, 322 insertions(+), 327 deletions(-) diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 320a3852f1..258c1b058e 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -46,74 +46,71 @@ #include "common.h" #include "compile_time_macros.h" - #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) +#define STM32_USART_BASE(n) CONCAT3(STM32_USART, n, _BASE) #define STM32_USART_REG(base, offset) REG32((base) + (offset)) -#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) +#define STM32_IRQ_USART(n) CONCAT2(STM32_IRQ_USART, n) /* --- TIMERS --- */ -#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) - -#define STM32_TIM_REG(n, offset) \ - REG16(STM32_TIM_BASE(n) + (offset)) -#define STM32_TIM_REG32(n, offset) \ - REG32(STM32_TIM_BASE(n) + (offset)) - -#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) -#define STM32_TIM_CR1_CEN BIT(0) -#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) -#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) -#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) -#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) -#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) -#define STM32_TIM_EGR_UG BIT(0) -#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) -#define STM32_TIM_CCMR1_OC1PE BIT(2) +#define STM32_TIM_BASE(n) CONCAT3(STM32_TIM, n, _BASE) + +#define STM32_TIM_REG(n, offset) REG16(STM32_TIM_BASE(n) + (offset)) +#define STM32_TIM_REG32(n, offset) REG32(STM32_TIM_BASE(n) + (offset)) + +#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00) +#define STM32_TIM_CR1_CEN BIT(0) +#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04) +#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08) +#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C) +#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10) +#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14) +#define STM32_TIM_EGR_UG BIT(0) +#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18) +#define STM32_TIM_CCMR1_OC1PE BIT(2) /* Use in place of TIM_CCMR1_OC1M_0 through 2 from STM documentation. */ -#define STM32_TIM_CCMR1_OC1M(n) (((n) & 0x7) << 4) -#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) -#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) -#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) +#define STM32_TIM_CCMR1_OC1M(n) (((n)&0x7) << 4) +#define STM32_TIM_CCMR1_OC1M_MASK STM32_TIM_CCMR1_OC1M(~0) +#define STM32_TIM_CCMR1_OC1M_FROZEN STM32_TIM_CCMR1_OC1M(0x0) +#define STM32_TIM_CCMR1_OC1M_ACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x1) #define STM32_TIM_CCMR1_OC1M_INACTIVE_ON_MATCH STM32_TIM_CCMR1_OC1M(0x2) -#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) -#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) -#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) -#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) -#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) -#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) -#define STM32_TIM_CCER_CC1E BIT(0) -#define STM32_TIM_CCER_CC1P BIT(1) -#define STM32_TIM_CCER_CC1NE BIT(2) -#define STM32_TIM_CCER_CC1NP BIT(3) -#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) -#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) -#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) -#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) -#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) -#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) -#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) -#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) -#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) -#define STM32_TIM_BDTR_MOE BIT(15) -#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) -#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) -#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) - -#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x) - 1) * 4) - -#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) -#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) -#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) -#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) -#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) -#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) +#define STM32_TIM_CCMR1_OC1M_TOGGLE STM32_TIM_CCMR1_OC1M(0x3) +#define STM32_TIM_CCMR1_OC1M_FORCE_INACTIVE STM32_TIM_CCMR1_OC1M(0x4) +#define STM32_TIM_CCMR1_OC1M_FORCE_ACTIVE STM32_TIM_CCMR1_OC1M(0x5) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_1 STM32_TIM_CCMR1_OC1M(0x6) +#define STM32_TIM_CCMR1_OC1M_PWM_MODE_2 STM32_TIM_CCMR1_OC1M(0x7) +#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C) +#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20) +#define STM32_TIM_CCER_CC1E BIT(0) +#define STM32_TIM_CCER_CC1P BIT(1) +#define STM32_TIM_CCER_CC1NE BIT(2) +#define STM32_TIM_CCER_CC1NP BIT(3) +#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24) +#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28) +#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C) +#define STM32_TIM_RCR(n) STM32_TIM_REG(n, 0x30) +#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34) +#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38) +#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C) +#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40) +#define STM32_TIM_BDTR(n) STM32_TIM_REG(n, 0x44) +#define STM32_TIM_BDTR_MOE BIT(15) +#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48) +#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C) +#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50) + +#define STM32_TIM_CCRx(n, x) STM32_TIM_REG(n, 0x34 + ((x)-1) * 4) + +#define STM32_TIM32_CNT(n) STM32_TIM_REG32(n, 0x24) +#define STM32_TIM32_ARR(n) STM32_TIM_REG32(n, 0x2C) +#define STM32_TIM32_CCR1(n) STM32_TIM_REG32(n, 0x34) +#define STM32_TIM32_CCR2(n) STM32_TIM_REG32(n, 0x38) +#define STM32_TIM32_CCR3(n) STM32_TIM_REG32(n, 0x3C) +#define STM32_TIM32_CCR4(n) STM32_TIM_REG32(n, 0x40) /* Timer registers as struct */ struct timer_ctlr { unsigned cr1; @@ -145,327 +142,325 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define IRQ_TIM(n) CONCAT2(STM32_IRQ_TIM, n) /* --- Low power timers --- */ -#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) - -#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) - -#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) -#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) -#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) -#define STM32_LPTIM_INT_DOWN BIT(6) -#define STM32_LPTIM_INT_UP BIT(5) -#define STM32_LPTIM_INT_ARROK BIT(4) -#define STM32_LPTIM_INT_CMPOK BIT(3) -#define STM32_LPTIM_INT_EXTTRIG BIT(2) -#define STM32_LPTIM_INT_ARRM BIT(1) -#define STM32_LPTIM_INT_CMPM BIT(0) -#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) -#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) -#define STM32_LPTIM_CR_RSTARE BIT(4) -#define STM32_LPTIM_CR_COUNTRST BIT(3) -#define STM32_LPTIM_CR_CNTSTRT BIT(2) -#define STM32_LPTIM_CR_SNGSTRT BIT(1) -#define STM32_LPTIM_CR_ENABLE BIT(0) -#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) -#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) -#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) -#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) +#define STM32_LPTIM_BASE(n) CONCAT3(STM32_LPTIM, n, _BASE) + +#define STM32_LPTIM_REG(n, offset) REG32(STM32_LPTIM_BASE(n) + (offset)) + +#define STM32_LPTIM_ISR(n) STM32_LPTIM_REG(n, 0x00) +#define STM32_LPTIM_ICR(n) STM32_LPTIM_REG(n, 0x04) +#define STM32_LPTIM_IER(n) STM32_LPTIM_REG(n, 0x08) +#define STM32_LPTIM_INT_DOWN BIT(6) +#define STM32_LPTIM_INT_UP BIT(5) +#define STM32_LPTIM_INT_ARROK BIT(4) +#define STM32_LPTIM_INT_CMPOK BIT(3) +#define STM32_LPTIM_INT_EXTTRIG BIT(2) +#define STM32_LPTIM_INT_ARRM BIT(1) +#define STM32_LPTIM_INT_CMPM BIT(0) +#define STM32_LPTIM_CFGR(n) STM32_LPTIM_REG(n, 0x0C) +#define STM32_LPTIM_CR(n) STM32_LPTIM_REG(n, 0x10) +#define STM32_LPTIM_CR_RSTARE BIT(4) +#define STM32_LPTIM_CR_COUNTRST BIT(3) +#define STM32_LPTIM_CR_CNTSTRT BIT(2) +#define STM32_LPTIM_CR_SNGSTRT BIT(1) +#define STM32_LPTIM_CR_ENABLE BIT(0) +#define STM32_LPTIM_CMP(n) STM32_LPTIM_REG(n, 0x14) +#define STM32_LPTIM_ARR(n) STM32_LPTIM_REG(n, 0x18) +#define STM32_LPTIM_CNT(n) STM32_LPTIM_REG(n, 0x1C) +#define STM32_LPTIM_CFGR2(n) STM32_LPTIM_REG(n, 0x24) /* --- GPIO --- */ -#define GPIO_A STM32_GPIOA_BASE -#define GPIO_B STM32_GPIOB_BASE -#define GPIO_C STM32_GPIOC_BASE -#define GPIO_D STM32_GPIOD_BASE -#define GPIO_E STM32_GPIOE_BASE -#define GPIO_F STM32_GPIOF_BASE -#define GPIO_G STM32_GPIOG_BASE -#define GPIO_H STM32_GPIOH_BASE -#define GPIO_I STM32_GPIOI_BASE -#define GPIO_J STM32_GPIOJ_BASE -#define GPIO_K STM32_GPIOK_BASE +#define GPIO_A STM32_GPIOA_BASE +#define GPIO_B STM32_GPIOB_BASE +#define GPIO_C STM32_GPIOC_BASE +#define GPIO_D STM32_GPIOD_BASE +#define GPIO_E STM32_GPIOE_BASE +#define GPIO_F STM32_GPIOF_BASE +#define GPIO_G STM32_GPIOG_BASE +#define GPIO_H STM32_GPIOH_BASE +#define GPIO_I STM32_GPIOI_BASE +#define GPIO_J STM32_GPIOJ_BASE +#define GPIO_K STM32_GPIOK_BASE #define UNIMPLEMENTED_GPIO_BANK GPIO_A - /* --- I2C --- */ -#define STM32_I2C1_PORT 0 -#define STM32_I2C2_PORT 1 -#define STM32_I2C3_PORT 2 -#define STM32_FMPI2C4_PORT 3 +#define STM32_I2C1_PORT 0 +#define STM32_I2C2_PORT 1 +#define STM32_I2C3_PORT 2 +#define STM32_FMPI2C4_PORT 3 #define stm32_i2c_reg(port, offset) \ - ((uint16_t *)((STM32_I2C1_BASE + ((port) * 0x400)) + (offset))) + ((uint16_t *)((STM32_I2C1_BASE + ((port)*0x400)) + (offset))) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) -#define STM32_PWR_CR_LPSDSR (1 << 0) -#define STM32_PWR_CR_FLPS (1 << 9) -#define STM32_PWR_CR_SVOS5 (1 << 14) -#define STM32_PWR_CR_SVOS4 (2 << 14) -#define STM32_PWR_CR_SVOS3 (3 << 14) -#define STM32_PWR_CR_SVOS_MASK (3 << 14) +#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00) +#define STM32_PWR_CR_LPSDSR (1 << 0) +#define STM32_PWR_CR_FLPS (1 << 9) +#define STM32_PWR_CR_SVOS5 (1 << 14) +#define STM32_PWR_CR_SVOS4 (2 << 14) +#define STM32_PWR_CR_SVOS3 (3 << 14) +#define STM32_PWR_CR_SVOS_MASK (3 << 14) /* RTC domain control register */ -#define STM32_RCC_BDCR_BDRST BIT(16) -#define STM32_RCC_BDCR_RTCEN BIT(15) -#define STM32_RCC_BDCR_LSERDY BIT(1) -#define STM32_RCC_BDCR_LSEON BIT(0) -#define BDCR_RTCSEL_MASK ((0x3) << 8) -#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) -#define BDCR_SRC_LSE 0x1 -#define BDCR_SRC_LSI 0x2 -#define BDCR_SRC_HSE 0x3 +#define STM32_RCC_BDCR_BDRST BIT(16) +#define STM32_RCC_BDCR_RTCEN BIT(15) +#define STM32_RCC_BDCR_LSERDY BIT(1) +#define STM32_RCC_BDCR_LSEON BIT(0) +#define BDCR_RTCSEL_MASK ((0x3) << 8) +#define BDCR_RTCSEL(source) (((source) << 8) & BDCR_RTCSEL_MASK) +#define BDCR_SRC_LSE 0x1 +#define BDCR_SRC_LSI 0x2 +#define BDCR_SRC_HSE 0x3 /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB1_TIM2 BIT(0) -#define STM32_RCC_PB1_TIM3 BIT(1) -#define STM32_RCC_PB1_TIM4 BIT(2) -#define STM32_RCC_PB1_TIM5 BIT(3) -#define STM32_RCC_PB1_TIM6 BIT(4) -#define STM32_RCC_PB1_TIM7 BIT(5) -#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ -#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ -#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ -#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ -#define STM32_RCC_PB1_WWDG BIT(11) -#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ -#define STM32_RCC_PB1_SPI2 BIT(14) -#define STM32_RCC_PB1_SPI3 BIT(15) -#define STM32_RCC_PB1_USART2 BIT(17) -#define STM32_RCC_PB1_USART3 BIT(18) -#define STM32_RCC_PB1_USART4 BIT(19) -#define STM32_RCC_PB1_USART5 BIT(20) -#define STM32_RCC_PB1_PWREN BIT(28) -#define STM32_RCC_PB2_SPI1 BIT(12) +#define STM32_RCC_PB1_TIM2 BIT(0) +#define STM32_RCC_PB1_TIM3 BIT(1) +#define STM32_RCC_PB1_TIM4 BIT(2) +#define STM32_RCC_PB1_TIM5 BIT(3) +#define STM32_RCC_PB1_TIM6 BIT(4) +#define STM32_RCC_PB1_TIM7 BIT(5) +#define STM32_RCC_PB1_TIM12 BIT(6) /* STM32H7 */ +#define STM32_RCC_PB1_TIM13 BIT(7) /* STM32H7 */ +#define STM32_RCC_PB1_TIM14 BIT(8) /* STM32H7 */ +#define STM32_RCC_PB1_RTC BIT(10) /* DBGMCU only */ +#define STM32_RCC_PB1_WWDG BIT(11) +#define STM32_RCC_PB1_IWDG BIT(12) /* DBGMCU only */ +#define STM32_RCC_PB1_SPI2 BIT(14) +#define STM32_RCC_PB1_SPI3 BIT(15) +#define STM32_RCC_PB1_USART2 BIT(17) +#define STM32_RCC_PB1_USART3 BIT(18) +#define STM32_RCC_PB1_USART4 BIT(19) +#define STM32_RCC_PB1_USART5 BIT(20) +#define STM32_RCC_PB1_PWREN BIT(28) +#define STM32_RCC_PB2_SPI1 BIT(12) /* Reset causes definitions */ /* --- Watchdogs --- */ -#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) -#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) -#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) - -#define STM32_WWDG_TB_8 (3 << 7) -#define STM32_WWDG_EWI BIT(9) - -#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) -#define STM32_IWDG_KR_UNLOCK 0x5555 -#define STM32_IWDG_KR_RELOAD 0xaaaa -#define STM32_IWDG_KR_START 0xcccc -#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) -#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) -#define STM32_IWDG_RLR_MAX 0x0fff -#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) -#define STM32_IWDG_SR_WVU BIT(2) -#define STM32_IWDG_SR_RVU BIT(1) -#define STM32_IWDG_SR_PVU BIT(0) -#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) +#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00) +#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04) +#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08) + +#define STM32_WWDG_TB_8 (3 << 7) +#define STM32_WWDG_EWI BIT(9) + +#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00) +#define STM32_IWDG_KR_UNLOCK 0x5555 +#define STM32_IWDG_KR_RELOAD 0xaaaa +#define STM32_IWDG_KR_START 0xcccc +#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04) +#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08) +#define STM32_IWDG_RLR_MAX 0x0fff +#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C) +#define STM32_IWDG_SR_WVU BIT(2) +#define STM32_IWDG_SR_RVU BIT(1) +#define STM32_IWDG_SR_PVU BIT(0) +#define STM32_IWDG_WINR REG32(STM32_IWDG_BASE + 0x10) /* --- Real-Time Clock --- */ /* --- Debug --- */ -#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) -#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) +#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00) +#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04) /* --- Routing interface --- */ /* STM32L1xx only */ -#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) -#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) -#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) -#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) -#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) -#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) -#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) -#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) -#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) -#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) -#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) -#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) -#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) -#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) -#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) -#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) -#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) -#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) -#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) -#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) -#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) +#define STM32_RI_ICR REG32(STM32_COMP_BASE + 0x04) +#define STM32_RI_ASCR1 REG32(STM32_COMP_BASE + 0x08) +#define STM32_RI_ASCR2 REG32(STM32_COMP_BASE + 0x0C) +#define STM32_RI_HYSCR1 REG32(STM32_COMP_BASE + 0x10) +#define STM32_RI_HYSCR2 REG32(STM32_COMP_BASE + 0x14) +#define STM32_RI_HYSCR3 REG32(STM32_COMP_BASE + 0x18) +#define STM32_RI_AMSR1 REG32(STM32_COMP_BASE + 0x1C) +#define STM32_RI_CMR1 REG32(STM32_COMP_BASE + 0x20) +#define STM32_RI_CICR1 REG32(STM32_COMP_BASE + 0x24) +#define STM32_RI_AMSR2 REG32(STM32_COMP_BASE + 0x28) +#define STM32_RI_CMR2 REG32(STM32_COMP_BASE + 0x30) +#define STM32_RI_CICR2 REG32(STM32_COMP_BASE + 0x34) +#define STM32_RI_AMSR3 REG32(STM32_COMP_BASE + 0x38) +#define STM32_RI_CMR3 REG32(STM32_COMP_BASE + 0x3C) +#define STM32_RI_CICR3 REG32(STM32_COMP_BASE + 0x40) +#define STM32_RI_AMSR4 REG32(STM32_COMP_BASE + 0x44) +#define STM32_RI_CMR4 REG32(STM32_COMP_BASE + 0x48) +#define STM32_RI_CICR4 REG32(STM32_COMP_BASE + 0x4C) +#define STM32_RI_AMSR5 REG32(STM32_COMP_BASE + 0x50) +#define STM32_RI_CMR5 REG32(STM32_COMP_BASE + 0x54) +#define STM32_RI_CICR5 REG32(STM32_COMP_BASE + 0x58) /* --- DAC --- */ -#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) -#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) -#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) -#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) -#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) -#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) -#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) -#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) -#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) -#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) -#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) -#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) -#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) -#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) - -#define STM32_DAC_CR_DMAEN2 BIT(28) -#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) -#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) -#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) -#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) -#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) -#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) -#define STM32_DAC_CR_TSEL2_MASK (7 << 19) -#define STM32_DAC_CR_TEN2 BIT(18) -#define STM32_DAC_CR_BOFF2 BIT(17) -#define STM32_DAC_CR_EN2 BIT(16) -#define STM32_DAC_CR_DMAEN1 BIT(12) -#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) -#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) -#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) -#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) -#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) -#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) -#define STM32_DAC_CR_TSEL1_MASK (7 << 3) -#define STM32_DAC_CR_TEN1 BIT(2) -#define STM32_DAC_CR_BOFF1 BIT(1) -#define STM32_DAC_CR_EN1 BIT(0) +#define STM32_DAC_CR REG32(STM32_DAC_BASE + 0x00) +#define STM32_DAC_SWTRIGR REG32(STM32_DAC_BASE + 0x04) +#define STM32_DAC_DHR12R1 REG32(STM32_DAC_BASE + 0x08) +#define STM32_DAC_DHR12L1 REG32(STM32_DAC_BASE + 0x0C) +#define STM32_DAC_DHR8R1 REG32(STM32_DAC_BASE + 0x10) +#define STM32_DAC_DHR12R2 REG32(STM32_DAC_BASE + 0x14) +#define STM32_DAC_DHR12L2 REG32(STM32_DAC_BASE + 0x18) +#define STM32_DAC_DHR8R2 REG32(STM32_DAC_BASE + 0x1C) +#define STM32_DAC_DHR12RD REG32(STM32_DAC_BASE + 0x20) +#define STM32_DAC_DHR12LD REG32(STM32_DAC_BASE + 0x24) +#define STM32_DAC_DHR8RD REG32(STM32_DAC_BASE + 0x28) +#define STM32_DAC_DOR1 REG32(STM32_DAC_BASE + 0x2C) +#define STM32_DAC_DOR2 REG32(STM32_DAC_BASE + 0x30) +#define STM32_DAC_SR REG32(STM32_DAC_BASE + 0x34) + +#define STM32_DAC_CR_DMAEN2 BIT(28) +#define STM32_DAC_CR_TSEL2_SWTRG (7 << 19) +#define STM32_DAC_CR_TSEL2_TMR4 (5 << 19) +#define STM32_DAC_CR_TSEL2_TMR2 (4 << 19) +#define STM32_DAC_CR_TSEL2_TMR9 (3 << 19) +#define STM32_DAC_CR_TSEL2_TMR7 (2 << 19) +#define STM32_DAC_CR_TSEL2_TMR6 (0 << 19) +#define STM32_DAC_CR_TSEL2_MASK (7 << 19) +#define STM32_DAC_CR_TEN2 BIT(18) +#define STM32_DAC_CR_BOFF2 BIT(17) +#define STM32_DAC_CR_EN2 BIT(16) +#define STM32_DAC_CR_DMAEN1 BIT(12) +#define STM32_DAC_CR_TSEL1_SWTRG (7 << 3) +#define STM32_DAC_CR_TSEL1_TMR4 (5 << 3) +#define STM32_DAC_CR_TSEL1_TMR2 (4 << 3) +#define STM32_DAC_CR_TSEL1_TMR9 (3 << 3) +#define STM32_DAC_CR_TSEL1_TMR7 (2 << 3) +#define STM32_DAC_CR_TSEL1_TMR6 (0 << 3) +#define STM32_DAC_CR_TSEL1_MASK (7 << 3) +#define STM32_DAC_CR_TEN1 BIT(2) +#define STM32_DAC_CR_BOFF1 BIT(1) +#define STM32_DAC_CR_EN1 BIT(0) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- USB --- */ -#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4) - -#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) - -#define STM32_USB_CNTR_FRES BIT(0) -#define STM32_USB_CNTR_PDWN BIT(1) -#define STM32_USB_CNTR_LP_MODE BIT(2) -#define STM32_USB_CNTR_FSUSP BIT(3) -#define STM32_USB_CNTR_RESUME BIT(4) -#define STM32_USB_CNTR_L1RESUME BIT(5) -#define STM32_USB_CNTR_L1REQM BIT(7) -#define STM32_USB_CNTR_ESOFM BIT(8) -#define STM32_USB_CNTR_SOFM BIT(9) -#define STM32_USB_CNTR_RESETM BIT(10) -#define STM32_USB_CNTR_SUSPM BIT(11) -#define STM32_USB_CNTR_WKUPM BIT(12) -#define STM32_USB_CNTR_ERRM BIT(13) -#define STM32_USB_CNTR_PMAOVRM BIT(14) -#define STM32_USB_CNTR_CTRM BIT(15) - -#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) - -#define STM32_USB_ISTR_EP_ID_MASK (0x000f) -#define STM32_USB_ISTR_DIR BIT(4) -#define STM32_USB_ISTR_L1REQ BIT(7) -#define STM32_USB_ISTR_ESOF BIT(8) -#define STM32_USB_ISTR_SOF BIT(9) -#define STM32_USB_ISTR_RESET BIT(10) -#define STM32_USB_ISTR_SUSP BIT(11) -#define STM32_USB_ISTR_WKUP BIT(12) -#define STM32_USB_ISTR_ERR BIT(13) -#define STM32_USB_ISTR_PMAOVR BIT(14) -#define STM32_USB_ISTR_CTR BIT(15) - -#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) +#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n)*4) + +#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40) + +#define STM32_USB_CNTR_FRES BIT(0) +#define STM32_USB_CNTR_PDWN BIT(1) +#define STM32_USB_CNTR_LP_MODE BIT(2) +#define STM32_USB_CNTR_FSUSP BIT(3) +#define STM32_USB_CNTR_RESUME BIT(4) +#define STM32_USB_CNTR_L1RESUME BIT(5) +#define STM32_USB_CNTR_L1REQM BIT(7) +#define STM32_USB_CNTR_ESOFM BIT(8) +#define STM32_USB_CNTR_SOFM BIT(9) +#define STM32_USB_CNTR_RESETM BIT(10) +#define STM32_USB_CNTR_SUSPM BIT(11) +#define STM32_USB_CNTR_WKUPM BIT(12) +#define STM32_USB_CNTR_ERRM BIT(13) +#define STM32_USB_CNTR_PMAOVRM BIT(14) +#define STM32_USB_CNTR_CTRM BIT(15) + +#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44) + +#define STM32_USB_ISTR_EP_ID_MASK (0x000f) +#define STM32_USB_ISTR_DIR BIT(4) +#define STM32_USB_ISTR_L1REQ BIT(7) +#define STM32_USB_ISTR_ESOF BIT(8) +#define STM32_USB_ISTR_SOF BIT(9) +#define STM32_USB_ISTR_RESET BIT(10) +#define STM32_USB_ISTR_SUSP BIT(11) +#define STM32_USB_ISTR_WKUP BIT(12) +#define STM32_USB_ISTR_ERR BIT(13) +#define STM32_USB_ISTR_PMAOVR BIT(14) +#define STM32_USB_ISTR_CTR BIT(15) + +#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48) #define STM32_USB_FNR_RXDP_RXDM_SHIFT (14) -#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) - -#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) -#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) -#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) -#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) - -#define STM32_USB_BCDR_BCDEN BIT(0) -#define STM32_USB_BCDR_DCDEN BIT(1) -#define STM32_USB_BCDR_PDEN BIT(2) -#define STM32_USB_BCDR_SDEN BIT(3) -#define STM32_USB_BCDR_DCDET BIT(4) -#define STM32_USB_BCDR_PDET BIT(5) -#define STM32_USB_BCDR_SDET BIT(6) -#define STM32_USB_BCDR_PS2DET BIT(7) - -#define EP_MASK 0x0F0F -#define EP_TX_DTOG 0x0040 -#define EP_TX_MASK 0x0030 +#define STM32_USB_FNR_RXDP_RXDM_MASK (3 << STM32_USB_FNR_RXDP_RXDM_SHIFT) + +#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C) +#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50) +#define STM32_USB_LPMCSR REG16(STM32_USB_FS_BASE + 0x54) +#define STM32_USB_BCDR REG16(STM32_USB_FS_BASE + 0x58) + +#define STM32_USB_BCDR_BCDEN BIT(0) +#define STM32_USB_BCDR_DCDEN BIT(1) +#define STM32_USB_BCDR_PDEN BIT(2) +#define STM32_USB_BCDR_SDEN BIT(3) +#define STM32_USB_BCDR_DCDET BIT(4) +#define STM32_USB_BCDR_PDET BIT(5) +#define STM32_USB_BCDR_SDET BIT(6) +#define STM32_USB_BCDR_PS2DET BIT(7) + +#define EP_MASK 0x0F0F +#define EP_TX_DTOG 0x0040 +#define EP_TX_MASK 0x0030 #define EP_TX_VALID 0x0030 -#define EP_TX_NAK 0x0020 +#define EP_TX_NAK 0x0020 #define EP_TX_STALL 0x0010 #define EP_TX_DISAB 0x0000 -#define EP_RX_DTOG 0x4000 -#define EP_RX_MASK 0x3000 +#define EP_RX_DTOG 0x4000 +#define EP_RX_MASK 0x3000 #define EP_RX_VALID 0x3000 -#define EP_RX_NAK 0x2000 +#define EP_RX_NAK 0x2000 #define EP_RX_STALL 0x1000 #define EP_RX_DISAB 0x0000 #define EP_STATUS_OUT 0x0100 -#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) +#define EP_TX_RX_MASK (EP_TX_MASK | EP_RX_MASK) #define EP_TX_RX_VALID (EP_TX_VALID | EP_RX_VALID) -#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK) +#define EP_TX_RX_NAK (EP_TX_NAK | EP_RX_NAK) #define STM32_TOGGLE_EP(n, mask, val, flags) \ - STM32_USB_EP(n) = (((STM32_USB_EP(n) & (EP_MASK | (mask))) \ - ^ (val)) | (flags)) + STM32_USB_EP(n) = \ + (((STM32_USB_EP(n) & (EP_MASK | (mask))) ^ (val)) | (flags)) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 0fb043e586c20325db51402e516a9e2e1b47be1c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:33 -0600 Subject: chip/stm32/registers-stm32h7.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I6336557f0869f177d1df82651b21f76d7f6a6e9b Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729532 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32h7.h | 1590 ++++++++++++++++++++-------------------- 1 file changed, 789 insertions(+), 801 deletions(-) diff --git a/chip/stm32/registers-stm32h7.h b/chip/stm32/registers-stm32h7.h index 2053a85830..09081751c7 100644 --- a/chip/stm32/registers-stm32h7.h +++ b/chip/stm32/registers-stm32h7.h @@ -19,591 +19,586 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - -#define STM32_IRQ_LPTIM1 93 -#define STM32_IRQ_TIM15 116 -#define STM32_IRQ_TIM16 117 -#define STM32_IRQ_TIM17 118 -#define STM32_IRQ_LPTIM2 138 -#define STM32_IRQ_LPTIM3 139 -#define STM32_IRQ_LPTIM4 140 -#define STM32_IRQ_LPTIM5 141 +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ + +#define STM32_IRQ_LPTIM1 93 +#define STM32_IRQ_TIM15 116 +#define STM32_IRQ_TIM16 117 +#define STM32_IRQ_TIM17 118 +#define STM32_IRQ_LPTIM2 138 +#define STM32_IRQ_LPTIM3 139 +#define STM32_IRQ_LPTIM4 140 +#define STM32_IRQ_LPTIM5 141 /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - /* * STM32F4 introduces a concept of DMA stream to allow * fine allocation of a stream to a channel. */ -#define STM32_IRQ_DMA1_STREAM0 11 -#define STM32_IRQ_DMA1_STREAM1 12 -#define STM32_IRQ_DMA1_STREAM2 13 -#define STM32_IRQ_DMA1_STREAM3 14 -#define STM32_IRQ_DMA1_STREAM4 15 -#define STM32_IRQ_DMA1_STREAM5 16 -#define STM32_IRQ_DMA1_STREAM6 17 -#define STM32_IRQ_DMA1_STREAM7 47 -#define STM32_IRQ_DMA2_STREAM0 56 -#define STM32_IRQ_DMA2_STREAM1 57 -#define STM32_IRQ_DMA2_STREAM2 58 -#define STM32_IRQ_DMA2_STREAM3 59 -#define STM32_IRQ_DMA2_STREAM4 60 -#define STM32_IRQ_DMA2_STREAM5 68 -#define STM32_IRQ_DMA2_STREAM6 69 -#define STM32_IRQ_DMA2_STREAM7 70 - -#define STM32_IRQ_OTG_HS_WKUP 76 -#define STM32_IRQ_OTG_HS_EP1_IN 75 -#define STM32_IRQ_OTG_HS_EP1_OUT 74 -#define STM32_IRQ_OTG_HS 77 -#define STM32_IRQ_OTG_FS 67 -#define STM32_IRQ_OTG_FS_WKUP 42 +#define STM32_IRQ_DMA1_STREAM0 11 +#define STM32_IRQ_DMA1_STREAM1 12 +#define STM32_IRQ_DMA1_STREAM2 13 +#define STM32_IRQ_DMA1_STREAM3 14 +#define STM32_IRQ_DMA1_STREAM4 15 +#define STM32_IRQ_DMA1_STREAM5 16 +#define STM32_IRQ_DMA1_STREAM6 17 +#define STM32_IRQ_DMA1_STREAM7 47 +#define STM32_IRQ_DMA2_STREAM0 56 +#define STM32_IRQ_DMA2_STREAM1 57 +#define STM32_IRQ_DMA2_STREAM2 58 +#define STM32_IRQ_DMA2_STREAM3 59 +#define STM32_IRQ_DMA2_STREAM4 60 +#define STM32_IRQ_DMA2_STREAM5 68 +#define STM32_IRQ_DMA2_STREAM6 69 +#define STM32_IRQ_DMA2_STREAM7 70 + +#define STM32_IRQ_OTG_HS_WKUP 76 +#define STM32_IRQ_OTG_HS_EP1_IN 75 +#define STM32_IRQ_OTG_HS_EP1_OUT 74 +#define STM32_IRQ_OTG_HS 77 +#define STM32_IRQ_OTG_FS 67 +#define STM32_IRQ_OTG_FS_WKUP 42 /* Peripheral base addresses */ -#define STM32_GPV_BASE 0x51000000 - -#define STM32_DBGMCU_BASE 0x5C001000 - -#define STM32_BDMA_BASE 0x58025400 -#define STM32_DMA1_BASE 0x40020000 -#define STM32_DMA2_BASE 0x40020400 -#define STM32_DMA2D_BASE 0x52001000 -#define STM32_DMAMUX1_BASE 0x40020800 -#define STM32_DMAMUX2_BASE 0x58025800 -#define STM32_MDMA_BASE 0x52000000 - -#define STM32_EXTI_BASE 0x58000000 - -#define STM32_FLASH_REGS_BASE 0x52002000 - -#define STM32_GPIOA_BASE 0x58020000 -#define STM32_GPIOB_BASE 0x58020400 -#define STM32_GPIOC_BASE 0x58020800 -#define STM32_GPIOD_BASE 0x58020C00 -#define STM32_GPIOE_BASE 0x58021000 -#define STM32_GPIOF_BASE 0x58021400 -#define STM32_GPIOG_BASE 0x58021800 -#define STM32_GPIOH_BASE 0x58021C00 -#define STM32_GPIOI_BASE 0x58022000 -#define STM32_GPIOJ_BASE 0x58022400 -#define STM32_GPIOK_BASE 0x58022800 - -#define STM32_IWDG_BASE 0x58004800 - -#define STM32_LPTIM1_BASE 0x40002400 -#define STM32_LPTIM2_BASE 0x58002400 -#define STM32_LPTIM3_BASE 0x58002800 -#define STM32_LPTIM4_BASE 0x58002C00 -#define STM32_LPTIM5_BASE 0x58003000 - -#define STM32_PWR_BASE 0x58024800 -#define STM32_RCC_BASE 0x58024400 -#define STM32_RNG_BASE 0x48021800 -#define STM32_RTC_BASE 0x58004000 - -#define STM32_SYSCFG_BASE 0x58000400 - -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 -#define STM32_SPI4_BASE 0x40013400 -#define STM32_SPI5_BASE 0x40015000 - -#define STM32_TIM1_BASE 0x40010000 -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM8_BASE 0x40010400 -#define STM32_TIM12_BASE 0x40001800 -#define STM32_TIM13_BASE 0x40001c00 -#define STM32_TIM14_BASE 0x40002000 -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 - -#define STM32_UNIQUE_ID_BASE 0x1ff1e800 - -#define STM32_USART1_BASE 0x40011000 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART5_BASE 0x40005000 -#define STM32_USART6_BASE 0x40011400 -#define STM32_USART7_BASE 0x40007800 -#define STM32_USART8_BASE 0x40007C00 +#define STM32_GPV_BASE 0x51000000 + +#define STM32_DBGMCU_BASE 0x5C001000 + +#define STM32_BDMA_BASE 0x58025400 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA2D_BASE 0x52001000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMAMUX2_BASE 0x58025800 +#define STM32_MDMA_BASE 0x52000000 + +#define STM32_EXTI_BASE 0x58000000 + +#define STM32_FLASH_REGS_BASE 0x52002000 + +#define STM32_GPIOA_BASE 0x58020000 +#define STM32_GPIOB_BASE 0x58020400 +#define STM32_GPIOC_BASE 0x58020800 +#define STM32_GPIOD_BASE 0x58020C00 +#define STM32_GPIOE_BASE 0x58021000 +#define STM32_GPIOF_BASE 0x58021400 +#define STM32_GPIOG_BASE 0x58021800 +#define STM32_GPIOH_BASE 0x58021C00 +#define STM32_GPIOI_BASE 0x58022000 +#define STM32_GPIOJ_BASE 0x58022400 +#define STM32_GPIOK_BASE 0x58022800 + +#define STM32_IWDG_BASE 0x58004800 + +#define STM32_LPTIM1_BASE 0x40002400 +#define STM32_LPTIM2_BASE 0x58002400 +#define STM32_LPTIM3_BASE 0x58002800 +#define STM32_LPTIM4_BASE 0x58002C00 +#define STM32_LPTIM5_BASE 0x58003000 + +#define STM32_PWR_BASE 0x58024800 +#define STM32_RCC_BASE 0x58024400 +#define STM32_RNG_BASE 0x48021800 +#define STM32_RTC_BASE 0x58004000 + +#define STM32_SYSCFG_BASE 0x58000400 + +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI4_BASE 0x40013400 +#define STM32_SPI5_BASE 0x40015000 + +#define STM32_TIM1_BASE 0x40010000 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM8_BASE 0x40010400 +#define STM32_TIM12_BASE 0x40001800 +#define STM32_TIM13_BASE 0x40001c00 +#define STM32_TIM14_BASE 0x40002000 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 + +#define STM32_UNIQUE_ID_BASE 0x1ff1e800 + +#define STM32_USART1_BASE 0x40011000 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART5_BASE 0x40005000 +#define STM32_USART6_BASE 0x40011400 +#define STM32_USART7_BASE 0x40007800 +#define STM32_USART8_BASE 0x40007C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_CR1_UE BIT(0) -#define STM32_USART_CR1_UESM BIT(1) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_OVER8 BIT(15) -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_CR2_SWAP BIT(15) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) -#define STM32_USART_CR3_OVRDIS BIT(12) -#define STM32_USART_CR3_WUS_START_BIT (2 << 20) -#define STM32_USART_CR3_WUFIE BIT(22) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) -#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) -#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) -#define STM32_USART_ICR_ORECF BIT(3) -#define STM32_USART_ICR_TCCF BIT(6) -#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) -#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) -#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_CR1_UE BIT(0) +#define STM32_USART_CR1_UESM BIT(1) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_OVER8 BIT(15) +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_CR2_SWAP BIT(15) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) +#define STM32_USART_CR3_OVRDIS BIT(12) +#define STM32_USART_CR3_WUS_START_BIT (2 << 20) +#define STM32_USART_CR3_WUFIE BIT(22) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_RTOR(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_RQR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_ISR(base) STM32_USART_REG(base, 0x1C) +#define STM32_USART_ICR(base) STM32_USART_REG(base, 0x20) +#define STM32_USART_ICR_ORECF BIT(3) +#define STM32_USART_ICR_TCCF BIT(6) +#define STM32_USART_RDR(base) STM32_USART_REG(base, 0x24) +#define STM32_USART_TDR(base) STM32_USART_REG(base, 0x28) +#define STM32_USART_PRESC(base) STM32_USART_REG(base, 0x2C) /* register alias */ -#define STM32_USART_SR(base) STM32_USART_ISR(base) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_SR(base) STM32_USART_ISR(base) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) /* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) -#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) -#define STM32_PWR_CR3_BYPASS BIT(0) -#define STM32_PWR_CR3_LDOEN BIT(1) -#define STM32_PWR_CR3_SCUEN BIT(2) -#define STM32_PWR_CR3_VBE BIT(8) -#define STM32_PWR_CR3_VBRS BIT(9) -#define STM32_PWR_CR3_USB33DEN BIT(24) -#define STM32_PWR_CR3_USBREGEN BIT(25) -#define STM32_PWR_CR3_USB33RDY BIT(26) -#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) -#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) -#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) -#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) -#define STM32_PWR_CPUCR_STOPF BIT(5) -#define STM32_PWR_CPUCR_SBF BIT(6) -#define STM32_PWR_CPUCR_SBF_D1 BIT(7) -#define STM32_PWR_CPUCR_SBF_D2 BIT(8) -#define STM32_PWR_CPUCR_CSSF BIT(9) -#define STM32_PWR_CPUCR_RUN_D3 BIT(11) -#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) -#define STM32_PWR_D3CR_VOS1 (3 << 14) -#define STM32_PWR_D3CR_VOS2 (2 << 14) -#define STM32_PWR_D3CR_VOS3 (1 << 14) -#define STM32_PWR_D3CR_VOSMASK (3 << 14) -#define STM32_PWR_D3CR_VOSRDY (1 << 13) -#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) -#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) -#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) -#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) -#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) -#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) -#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) -#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) -#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) -#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) -#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) -#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) -#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) -#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) -#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) -#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) -#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) -#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) -#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) -#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) -#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) -#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) -#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) - -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) - -#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) -#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) -#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) -#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) -#define STM32_RCC_AHB2ENR_RNGEN BIT(6) -#define STM32_RCC_AHB2ENR_HASHEN BIT(5) -#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) -#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) -#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff -#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) -#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) -#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) -#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) -#define STM32_RCC_SYSCFGEN BIT(1) -#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) -#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) -#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) -#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) -#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) -#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) -#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) -#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) +#define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) +#define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) +#define STM32_PWR_CR3_BYPASS BIT(0) +#define STM32_PWR_CR3_LDOEN BIT(1) +#define STM32_PWR_CR3_SCUEN BIT(2) +#define STM32_PWR_CR3_VBE BIT(8) +#define STM32_PWR_CR3_VBRS BIT(9) +#define STM32_PWR_CR3_USB33DEN BIT(24) +#define STM32_PWR_CR3_USBREGEN BIT(25) +#define STM32_PWR_CR3_USB33RDY BIT(26) +#define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) +#define STM32_PWR_CPUCR_PDDS_D1 BIT(0) +#define STM32_PWR_CPUCR_PDDS_D2 BIT(1) +#define STM32_PWR_CPUCR_PDDS_D3 BIT(2) +#define STM32_PWR_CPUCR_STOPF BIT(5) +#define STM32_PWR_CPUCR_SBF BIT(6) +#define STM32_PWR_CPUCR_SBF_D1 BIT(7) +#define STM32_PWR_CPUCR_SBF_D2 BIT(8) +#define STM32_PWR_CPUCR_CSSF BIT(9) +#define STM32_PWR_CPUCR_RUN_D3 BIT(11) +#define STM32_PWR_D3CR REG32(STM32_PWR_BASE + 0x18) +#define STM32_PWR_D3CR_VOS1 (3 << 14) +#define STM32_PWR_D3CR_VOS2 (2 << 14) +#define STM32_PWR_D3CR_VOS3 (1 << 14) +#define STM32_PWR_D3CR_VOSMASK (3 << 14) +#define STM32_PWR_D3CR_VOSRDY (1 << 13) +#define STM32_PWR_WKUPCR REG32(STM32_PWR_BASE + 0x20) +#define STM32_PWR_WKUPFR REG32(STM32_PWR_BASE + 0x24) +#define STM32_PWR_WKUPEPR REG32(STM32_PWR_BASE + 0x28) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x000) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x004) +#define STM32_RCC_CRRCR REG32(STM32_RCC_BASE + 0x008) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x010) +#define STM32_RCC_D1CFGR REG32(STM32_RCC_BASE + 0x018) +#define STM32_RCC_D2CFGR REG32(STM32_RCC_BASE + 0x01C) +#define STM32_RCC_D3CFGR REG32(STM32_RCC_BASE + 0x020) +#define STM32_RCC_PLLCKSELR REG32(STM32_RCC_BASE + 0x028) +#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x02C) +#define STM32_RCC_PLL1DIVR REG32(STM32_RCC_BASE + 0x030) +#define STM32_RCC_PLL1FRACR REG32(STM32_RCC_BASE + 0x034) +#define STM32_RCC_PLL2DIVR REG32(STM32_RCC_BASE + 0x038) +#define STM32_RCC_PLL2FRACR REG32(STM32_RCC_BASE + 0x03C) +#define STM32_RCC_PLL3DIVR REG32(STM32_RCC_BASE + 0x040) +#define STM32_RCC_PLL3FRACR REG32(STM32_RCC_BASE + 0x044) +#define STM32_RCC_D1CCIPR REG32(STM32_RCC_BASE + 0x04C) +#define STM32_RCC_D2CCIP1R REG32(STM32_RCC_BASE + 0x050) +#define STM32_RCC_D2CCIP2R REG32(STM32_RCC_BASE + 0x054) +#define STM32_RCC_D3CCIPR REG32(STM32_RCC_BASE + 0x058) +#define STM32_RCC_CIER REG32(STM32_RCC_BASE + 0x060) +#define STM32_RCC_CIFR REG32(STM32_RCC_BASE + 0x064) +#define STM32_RCC_CICR REG32(STM32_RCC_BASE + 0x068) +#define STM32_RCC_BDCR REG32(STM32_RCC_BASE + 0x070) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x074) + +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x098) + +#define STM32_RCC_RSR REG32(STM32_RCC_BASE + 0x0D0) +#define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x0D4) +#define STM32_RCC_AHB1ENR REG32(STM32_RCC_BASE + 0x0D8) +#define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x0DC) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) +#define STM32_RCC_AHB2ENR_HASHEN BIT(5) +#define STM32_RCC_AHB2ENR_CRYPTEN BIT(4) +#define STM32_RCC_AHB4ENR REG32(STM32_RCC_BASE + 0x0E0) +#define STM32_RCC_AHB4ENR_GPIOMASK 0x3ff +#define STM32_RCC_APB3ENR REG32(STM32_RCC_BASE + 0x0E4) +#define STM32_RCC_APB1LENR REG32(STM32_RCC_BASE + 0x0E8) +#define STM32_RCC_APB1HENR REG32(STM32_RCC_BASE + 0x0EC) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x0F0) +#define STM32_RCC_APB4ENR REG32(STM32_RCC_BASE + 0x0F4) +#define STM32_RCC_SYSCFGEN BIT(1) +#define STM32_RCC_AHB3LPENR REG32(STM32_RCC_BASE + 0x0FC) +#define STM32_RCC_AHB1LPENR REG32(STM32_RCC_BASE + 0x100) +#define STM32_RCC_AHB2LPENR REG32(STM32_RCC_BASE + 0x104) +#define STM32_RCC_AHB4LPENR REG32(STM32_RCC_BASE + 0x108) +#define STM32_RCC_APB3LPENR REG32(STM32_RCC_BASE + 0x10C) +#define STM32_RCC_APB1LLPENR REG32(STM32_RCC_BASE + 0x110) +#define STM32_RCC_APB1HLPENR REG32(STM32_RCC_BASE + 0x114) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x118) +#define STM32_RCC_APB4LPENR REG32(STM32_RCC_BASE + 0x11C) /* Aliases */ -#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR - -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(2) -#define STM32_RCC_CR_CSION BIT(7) -#define STM32_RCC_CR_CSIRDY BIT(8) -#define STM32_RCC_CR_HSI48ON BIT(12) -#define STM32_RCC_CR_HSI48RDY BIT(13) -#define STM32_RCC_CR_PLL1ON BIT(24) -#define STM32_RCC_CR_PLL1RDY BIT(25) -#define STM32_RCC_CR_PLL2ON BIT(26) -#define STM32_RCC_CR_PLL2RDY BIT(27) -#define STM32_RCC_CR_PLL3ON BIT(28) -#define STM32_RCC_CR_PLL3RDY BIT(29) -#define STM32_RCC_CFGR_SW_HSI (0 << 0) -#define STM32_RCC_CFGR_SW_CSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_HSI (0 << 3) -#define STM32_RCC_CFGR_SWS_CSI (1 << 3) -#define STM32_RCC_CFGR_SWS_HSE (2 << 3) -#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) -#define STM32_RCC_CFGR_SWS_MASK (3 << 3) -#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) -#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) -#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) -#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) -#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) -#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) -#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) -#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) -#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) -#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) -#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) -#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) -#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) -#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) -#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) -#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) -#define STM32_RCC_PLLDIV_DIVN(n) (((n) - 1) << 0) -#define STM32_RCC_PLLDIV_DIVP(p) (((p) - 1) << 9) -#define STM32_RCC_PLLDIV_DIVQ(q) (((q) - 1) << 16) -#define STM32_RCC_PLLDIV_DIVR(r) (((r) - 1) << 24) -#define STM32_RCC_PLLFRAC(n) ((n) << 3) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) -#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) -#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) -#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) -#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) +#define STM32_RCC_APB1ENR STM32_RCC_APB1LENR + +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(2) +#define STM32_RCC_CR_CSION BIT(7) +#define STM32_RCC_CR_CSIRDY BIT(8) +#define STM32_RCC_CR_HSI48ON BIT(12) +#define STM32_RCC_CR_HSI48RDY BIT(13) +#define STM32_RCC_CR_PLL1ON BIT(24) +#define STM32_RCC_CR_PLL1RDY BIT(25) +#define STM32_RCC_CR_PLL2ON BIT(26) +#define STM32_RCC_CR_PLL2RDY BIT(27) +#define STM32_RCC_CR_PLL3ON BIT(28) +#define STM32_RCC_CR_PLL3RDY BIT(29) +#define STM32_RCC_CFGR_SW_HSI (0 << 0) +#define STM32_RCC_CFGR_SW_CSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL1 (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_HSI (0 << 3) +#define STM32_RCC_CFGR_SWS_CSI (1 << 3) +#define STM32_RCC_CFGR_SWS_HSE (2 << 3) +#define STM32_RCC_CFGR_SWS_PLL1 (3 << 3) +#define STM32_RCC_CFGR_SWS_MASK (3 << 3) +#define STM32_RCC_D1CFGR_HPRE_DIV1 (0 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV2 (8 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV4 (9 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV8 (10 << 0) +#define STM32_RCC_D1CFGR_HPRE_DIV16 (11 << 0) +#define STM32_RCC_D1CFGR_D1PPRE_DIV1 (0 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV2 (4 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV4 (5 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV8 (6 << 4) +#define STM32_RCC_D1CFGR_D1PPRE_DIV16 (7 << 4) +#define STM32_RCC_D1CFGR_D1CPRE_DIV1 (0 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV2 (8 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV4 (9 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV8 (10 << 8) +#define STM32_RCC_D1CFGR_D1CPRE_DIV16 (1BIT(8)) +#define STM32_RCC_PLLCKSEL_PLLSRC_HSI (0 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_CSI (1 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_HSE (2 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_NONE (3 << 0) +#define STM32_RCC_PLLCKSEL_PLLSRC_MASK (3 << 0) +#define STM32_RCC_PLLCKSEL_DIVM1(m) ((m) << 4) +#define STM32_RCC_PLLCKSEL_DIVM2(m) ((m) << 12) +#define STM32_RCC_PLLCKSEL_DIVM3(m) ((m) << 20) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_FRACEN BIT(0) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_WIDE (0 << 1) +#define STM32_RCC_PLLCFG_PLL1VCOSEL_MEDIUM BIT(1) +#define STM32_RCC_PLLCFG_PLL1RGE_1M_2M (0 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_2M_4M (1 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_4M_8M (2 << 2) +#define STM32_RCC_PLLCFG_PLL1RGE_8M_16M (3 << 2) +#define STM32_RCC_PLLCFG_DIVP1EN BIT(16) +#define STM32_RCC_PLLCFG_DIVQ1EN BIT(17) +#define STM32_RCC_PLLCFG_DIVR1EN BIT(18) +#define STM32_RCC_PLLDIV_DIVN(n) (((n)-1) << 0) +#define STM32_RCC_PLLDIV_DIVP(p) (((p)-1) << 9) +#define STM32_RCC_PLLDIV_DIVQ(q) (((q)-1) << 16) +#define STM32_RCC_PLLDIV_DIVR(r) (((r)-1) << 24) +#define STM32_RCC_PLLFRAC(n) ((n) << 3) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL1Q (0 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL2P (1 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PLL3P (2 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_PERCK (4 << 12) +#define STM32_RCC_D2CCIP1R_SPI123SEL_MASK (7 << 12) +#define STM32_RCC_D2CCIP1R_SPI45SEL_APB (0 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL2Q (1 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_PLL3Q (2 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSI (3 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_CSI (4 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_HSE (5 << 16) +#define STM32_RCC_D2CCIP1R_SPI45SEL_MASK (7 << 16) +#define STM32_RCC_D2CCIP2_USART234578SEL_PCLK (0 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL2Q (1 << 0) #define STM32_RCC_D2CCIP2_USART234578SEL_PLL3Q (2 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) -#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) -#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) -#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) -#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) -#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) -#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) -#define STM32_RCC_CSR_LSION BIT(0) -#define STM32_RCC_CSR_LSIRDY BIT(1) - -#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) +#define STM32_RCC_D2CCIP2_USART234578SEL_HSI (3 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_CSI (4 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_LSE (5 << 0) +#define STM32_RCC_D2CCIP2_USART234578SEL_MASK (7 << 0) +#define STM32_RCC_D2CCIP2_USART16SEL_PCLK (0 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_PLL2Q (1 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_PLL3Q (2 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_HSI (3 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_CSI (4 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_LSE (5 << 3) +#define STM32_RCC_D2CCIP2_USART16SEL_MASK (7 << 3) +#define STM32_RCC_D2CCIP2_RNGSEL_HSI48 (0 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_PLL1Q (1 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_LSE (2 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_LSI (3 << 8) +#define STM32_RCC_D2CCIP2_RNGSEL_MASK (3 << 8) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PCLK (0 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL2 (1 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PLL3 (2 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSE (3 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_LSI (4 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_PER (5 << 28) +#define STM32_RCC_D2CCIP2_LPTIM1SEL_MASK (7 << 28) +#define STM32_RCC_CSR_LSION BIT(0) +#define STM32_RCC_CSR_LSIRDY BIT(1) + +#define STM32_SYSCFG_PMCR REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) /* Peripheral bits for APB1ENR regs */ -#define STM32_RCC_PB1_LPTIM1 BIT(9) +#define STM32_RCC_PB1_LPTIM1 BIT(9) /* Peripheral bits for APB2ENR regs */ -#define STM32_RCC_PB2_TIM1 BIT(0) -#define STM32_RCC_PB2_TIM2 BIT(1) -#define STM32_RCC_PB2_USART1 BIT(4) -#define STM32_RCC_PB2_SPI1 BIT(12) -#define STM32_RCC_PB2_SPI4 BIT(13) -#define STM32_RCC_PB2_TIM15 BIT(16) -#define STM32_RCC_PB2_TIM16 BIT(17) -#define STM32_RCC_PB2_TIM17 BIT(18) +#define STM32_RCC_PB2_TIM1 BIT(0) +#define STM32_RCC_PB2_TIM2 BIT(1) +#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_SPI1 BIT(12) +#define STM32_RCC_PB2_SPI4 BIT(13) +#define STM32_RCC_PB2_TIM15 BIT(16) +#define STM32_RCC_PB2_TIM16 BIT(17) +#define STM32_RCC_PB2_TIM17 BIT(18) /* Peripheral bits for AHB1/2/3/4ENR regs */ -#define STM32_RCC_HB1_DMA1 BIT(0) -#define STM32_RCC_HB1_DMA2 BIT(1) -#define STM32_RCC_HB3_MDMA BIT(0) -#define STM32_RCC_HB4_BDMA BIT(21) - +#define STM32_RCC_HB1_DMA1 BIT(0) +#define STM32_RCC_HB1_DMA2 BIT(1) +#define STM32_RCC_HB3_MDMA BIT(0) +#define STM32_RCC_HB4_BDMA BIT(21) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(4) +#define STM32_RCC_PB2_USART1 BIT(4) /* Reset causes definitions */ #define STM32_RCC_RESET_CAUSE STM32_RCC_RSR -#define RESET_CAUSE_WDG (BIT(28)|BIT(26)) -#define RESET_CAUSE_SFT BIT(24) -#define RESET_CAUSE_POR BIT(23) -#define RESET_CAUSE_PIN BIT(22) -#define RESET_CAUSE_OTHER (BIT(31)|BIT(30)|BIT(29)|BIT(28)| \ - BIT(27)|BIT(26)|BIT(25)|BIT(24)| \ - BIT(23)|BIT(22)|BIT(21)|BIT(20)| \ - BIT(19)|BIT(18)|BIT(17)) -#define RESET_CAUSE_RMVF BIT(16) +#define RESET_CAUSE_WDG (BIT(28) | BIT(26)) +#define RESET_CAUSE_SFT BIT(24) +#define RESET_CAUSE_POR BIT(23) +#define RESET_CAUSE_PIN BIT(22) +#define RESET_CAUSE_OTHER \ + (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27) | BIT(26) | BIT(25) | \ + BIT(24) | BIT(23) | BIT(22) | BIT(21) | BIT(20) | BIT(19) | BIT(18) | \ + BIT(17)) +#define RESET_CAUSE_RMVF BIT(16) /* Power cause in PWR CPUCR register (Standby&Stop modes) */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CPUCR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CPUCR -#define RESET_CAUSE_SBF BIT(6) -#define RESET_CAUSE_SBF_CLR BIT(9) +#define RESET_CAUSE_SBF BIT(6) +#define RESET_CAUSE_SBF_CLR BIT(9) /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 128 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 128 /* --- SPI --- */ @@ -634,163 +629,160 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_SPE BIT(0) -#define STM32_SPI_CR1_CSTART BIT(9) -#define STM32_SPI_CR1_SSI BIT(12) -#define STM32_SPI_CR1_DIV(div) ((div) << 28) -#define STM32_SPI_CFG1_DATASIZE(n) (((n) - 1) << 0) -#define STM32_SPI_CFG1_FTHLV(n) (((n) - 1) << 5) -#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) -#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) -#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) -#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) -#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) -#define STM32_SPI_CFG1_RXDMAEN BIT(14) -#define STM32_SPI_CFG1_TXDMAEN BIT(15) -#define STM32_SPI_CFG1_CRCSIZE(n) (((n) - 1) << 16) -#define STM32_SPI_CFG2_MSTR BIT(22) -#define STM32_SPI_CFG2_SSM BIT(26) -#define STM32_SPI_CFG2_AFCNTR BIT(31) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_UDR BIT(5) -#define STM32_SPI_SR_FRLVL (3 << 13) -#define STM32_SPI_SR_TXC BIT(12) +#define STM32_SPI_CR1_SPE BIT(0) +#define STM32_SPI_CR1_CSTART BIT(9) +#define STM32_SPI_CR1_SSI BIT(12) +#define STM32_SPI_CR1_DIV(div) ((div) << 28) +#define STM32_SPI_CFG1_DATASIZE(n) (((n)-1) << 0) +#define STM32_SPI_CFG1_FTHLV(n) (((n)-1) << 5) +#define STM32_SPI_CFG1_UDRCFG_CONST (0 << 9) +#define STM32_SPI_CFG1_UDRCFG_LAST_RX (1 << 9) +#define STM32_SPI_CFG1_UDRCFG_LAST_TX (2 << 9) +#define STM32_SPI_CFG1_UDRDET_BEGIN_FRM (0 << 11) +#define STM32_SPI_CFG1_UDRDET_END_FRM (1 << 11) +#define STM32_SPI_CFG1_UDRDET_BEGIN_SS (2 << 11) +#define STM32_SPI_CFG1_RXDMAEN BIT(14) +#define STM32_SPI_CFG1_TXDMAEN BIT(15) +#define STM32_SPI_CFG1_CRCSIZE(n) (((n)-1) << 16) +#define STM32_SPI_CFG2_MSTR BIT(22) +#define STM32_SPI_CFG2_SSM BIT(26) +#define STM32_SPI_CFG2_AFCNTR BIT(31) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_UDR BIT(5) +#define STM32_SPI_SR_FRLVL (3 << 13) +#define STM32_SPI_SR_TXC BIT(12) /* --- Debug --- */ -#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) -#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) -#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) -#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) +#define STM32_DBGMCU_APB3FZ REG32(STM32_DBGMCU_BASE + 0x34) +#define STM32_DBGMCU_APB1LFZ REG32(STM32_DBGMCU_BASE + 0x3C) +#define STM32_DBGMCU_APB1HFZ REG32(STM32_DBGMCU_BASE + 0x44) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x4C) +#define STM32_DBGMCU_APB4FZ REG32(STM32_DBGMCU_BASE + 0x54) /* Alias */ -#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ +#define STM32_DBGMCU_APB1FZ STM32_DBGMCU_APB1LFZ /* --- Flash --- */ -#define STM32_FLASH_REG(bank, offset) REG32(((bank) ? 0x100 : 0) + \ - STM32_FLASH_REGS_BASE + (offset)) +#define STM32_FLASH_REG(bank, offset) \ + REG32(((bank) ? 0x100 : 0) + STM32_FLASH_REGS_BASE + (offset)) -#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) +#define STM32_FLASH_ACR(bank) STM32_FLASH_REG(bank, 0x00) #define STM32_FLASH_ACR_LATENCY_SHIFT (0) -#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) -#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) +#define STM32_FLASH_ACR_LATENCY_MASK (7 << STM32_FLASH_ACR_LATENCY_SHIFT) +#define STM32_FLASH_ACR_WRHIGHFREQ_85MHZ (0 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_185MHZ (1 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_285MHZ (2 << 4) #define STM32_FLASH_ACR_WRHIGHFREQ_385MHZ (3 << 4) -#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) -#define FLASH_KEYR_KEY1 0x45670123 -#define FLASH_KEYR_KEY2 0xCDEF89AB -#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) -#define FLASH_OPTKEYR_KEY1 0x08192A3B -#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F -#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) -#define FLASH_CR_LOCK BIT(0) -#define FLASH_CR_PG BIT(1) -#define FLASH_CR_SER BIT(2) -#define FLASH_CR_BER BIT(3) -#define FLASH_CR_PSIZE_BYTE (0 << 4) -#define FLASH_CR_PSIZE_HWORD (1 << 4) -#define FLASH_CR_PSIZE_WORD (2 << 4) -#define FLASH_CR_PSIZE_DWORD (3 << 4) -#define FLASH_CR_PSIZE_MASK (3 << 4) -#define FLASH_CR_FW BIT(6) -#define FLASH_CR_STRT BIT(7) -#define FLASH_CR_SNB(sec) (((sec) & 0x7) << 8) -#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) -#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) -#define FLASH_SR_BUSY BIT(0) -#define FLASH_SR_WBNE BIT(1) -#define FLASH_SR_QW BIT(2) -#define FLASH_SR_CRC_BUSY BIT(3) -#define FLASH_SR_EOP BIT(16) -#define FLASH_SR_WRPERR BIT(17) -#define FLASH_SR_PGSERR BIT(18) -#define FLASH_SR_STRBERR BIT(19) -#define FLASH_SR_INCERR BIT(21) -#define FLASH_SR_OPERR BIT(22) -#define FLASH_SR_RDPERR BIT(23) -#define FLASH_SR_RDSERR BIT(24) -#define FLASH_SR_SNECCERR BIT(25) -#define FLASH_SR_DBECCERR BIT(26) -#define FLASH_SR_CRCEND BIT(27) -#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) -#define FLASH_CCR_ERR_MASK (FLASH_SR_WRPERR | FLASH_SR_PGSERR \ - | FLASH_SR_STRBERR | FLASH_SR_INCERR \ - | FLASH_SR_OPERR | FLASH_SR_RDPERR \ - | FLASH_SR_RDSERR | FLASH_SR_SNECCERR \ - | FLASH_SR_DBECCERR) -#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) -#define FLASH_OPTCR_OPTLOCK BIT(0) -#define FLASH_OPTCR_OPTSTART BIT(1) -#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) -#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) -#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ -#define FLASH_OPTSR_RDP_MASK (0xFF << 8) -#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) +#define STM32_FLASH_KEYR(bank) STM32_FLASH_REG(bank, 0x04) +#define FLASH_KEYR_KEY1 0x45670123 +#define FLASH_KEYR_KEY2 0xCDEF89AB +#define STM32_FLASH_OPTKEYR(bank) STM32_FLASH_REG(bank, 0x08) +#define FLASH_OPTKEYR_KEY1 0x08192A3B +#define FLASH_OPTKEYR_KEY2 0x4C5D6E7F +#define STM32_FLASH_CR(bank) STM32_FLASH_REG(bank, 0x0C) +#define FLASH_CR_LOCK BIT(0) +#define FLASH_CR_PG BIT(1) +#define FLASH_CR_SER BIT(2) +#define FLASH_CR_BER BIT(3) +#define FLASH_CR_PSIZE_BYTE (0 << 4) +#define FLASH_CR_PSIZE_HWORD (1 << 4) +#define FLASH_CR_PSIZE_WORD (2 << 4) +#define FLASH_CR_PSIZE_DWORD (3 << 4) +#define FLASH_CR_PSIZE_MASK (3 << 4) +#define FLASH_CR_FW BIT(6) +#define FLASH_CR_STRT BIT(7) +#define FLASH_CR_SNB(sec) (((sec)&0x7) << 8) +#define FLASH_CR_SNB_MASK FLASH_CR_SNB(0x7) +#define STM32_FLASH_SR(bank) STM32_FLASH_REG(bank, 0x10) +#define FLASH_SR_BUSY BIT(0) +#define FLASH_SR_WBNE BIT(1) +#define FLASH_SR_QW BIT(2) +#define FLASH_SR_CRC_BUSY BIT(3) +#define FLASH_SR_EOP BIT(16) +#define FLASH_SR_WRPERR BIT(17) +#define FLASH_SR_PGSERR BIT(18) +#define FLASH_SR_STRBERR BIT(19) +#define FLASH_SR_INCERR BIT(21) +#define FLASH_SR_OPERR BIT(22) +#define FLASH_SR_RDPERR BIT(23) +#define FLASH_SR_RDSERR BIT(24) +#define FLASH_SR_SNECCERR BIT(25) +#define FLASH_SR_DBECCERR BIT(26) +#define FLASH_SR_CRCEND BIT(27) +#define STM32_FLASH_CCR(bank) STM32_FLASH_REG(bank, 0x14) +#define FLASH_CCR_ERR_MASK \ + (FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \ + FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_RDPERR | \ + FLASH_SR_RDSERR | FLASH_SR_SNECCERR | FLASH_SR_DBECCERR) +#define STM32_FLASH_OPTCR(bank) STM32_FLASH_REG(bank, 0x18) +#define FLASH_OPTCR_OPTLOCK BIT(0) +#define FLASH_OPTCR_OPTSTART BIT(1) +#define STM32_FLASH_OPTSR_CUR(bank) STM32_FLASH_REG(bank, 0x1C) +#define STM32_FLASH_OPTSR_PRG(bank) STM32_FLASH_REG(bank, 0x20) +#define FLASH_OPTSR_BUSY BIT(0) /* only in OPTSR_CUR */ +#define FLASH_OPTSR_RDP_MASK (0xFF << 8) +#define FLASH_OPTSR_RDP_LEVEL_0 (0xAA << 8) /* RDP Level 1: Anything but 0xAA/0xCC */ -#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) -#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) -#define FLASH_OPTSR_RSS1 BIT(26) -#define FLASH_OPTSR_RSS2 BIT(27) -#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) -#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) -#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) -#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) -#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) -#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) -#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) -#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) -#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) -#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) -#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) -#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) -#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) -#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) +#define FLASH_OPTSR_RDP_LEVEL_1 (0x00 << 8) +#define FLASH_OPTSR_RDP_LEVEL_2 (0xCC << 8) +#define FLASH_OPTSR_RSS1 BIT(26) +#define FLASH_OPTSR_RSS2 BIT(27) +#define STM32_FLASH_OPTCCR(bank) STM32_FLASH_REG(bank, 0x24) +#define STM32_FLASH_PRAR_CUR(bank) STM32_FLASH_REG(bank, 0x28) +#define STM32_FLASH_PRAR_PRG(bank) STM32_FLASH_REG(bank, 0x2C) +#define STM32_FLASH_SCAR_CUR(bank) STM32_FLASH_REG(bank, 0x30) +#define STM32_FLASH_SCAR_PRG(bank) STM32_FLASH_REG(bank, 0x34) +#define STM32_FLASH_WPSN_CUR(bank) STM32_FLASH_REG(bank, 0x38) +#define STM32_FLASH_WPSN_PRG(bank) STM32_FLASH_REG(bank, 0x3C) +#define STM32_FLASH_BOOT_CUR(bank) STM32_FLASH_REG(bank, 0x40) +#define STM32_FLASH_BOOT_PRG(bank) STM32_FLASH_REG(bank, 0x44) +#define STM32_FLASH_CRC_CR(bank) STM32_FLASH_REG(bank, 0x50) +#define STM32_FLASH_CRC_SADDR(bank) STM32_FLASH_REG(bank, 0x54) +#define STM32_FLASH_CRC_EADDR(bank) STM32_FLASH_REG(bank, 0x58) +#define STM32_FLASH_CRC_DATA(bank) STM32_FLASH_REG(bank, 0x5C) +#define STM32_FLASH_ECC_FA(bank) STM32_FLASH_REG(bank, 0x60) /* --- External Interrupts --- */ -#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) -#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) -#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) -#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) -#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) -#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) -#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) -#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) -#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) -#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) -#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) -#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) -#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) -#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) -#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) -#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) -#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) -#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) -#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) -#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) -#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) -#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) -#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) +#define STM32_EXTI_RTSR1 REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_FTSR1 REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_SWIER1 REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_D3PMR1 REG32(STM32_EXTI_BASE + 0x0C) +#define STM32_EXTI_D3PCR1L REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_D3PCR1H REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) +#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) +#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) +#define STM32_EXTI_D3PMR2 REG32(STM32_EXTI_BASE + 0x2C) +#define STM32_EXTI_D3PCR2L REG32(STM32_EXTI_BASE + 0x30) +#define STM32_EXTI_D3PCR2H REG32(STM32_EXTI_BASE + 0x34) +#define STM32_EXTI_RTSR3 REG32(STM32_EXTI_BASE + 0x40) +#define STM32_EXTI_FTSR3 REG32(STM32_EXTI_BASE + 0x44) +#define STM32_EXTI_SWIER3 REG32(STM32_EXTI_BASE + 0x48) +#define STM32_EXTI_D3PMR3 REG32(STM32_EXTI_BASE + 0x4C) +#define STM32_EXTI_D3PCR3L REG32(STM32_EXTI_BASE + 0x50) +#define STM32_EXTI_D3PCR3H REG32(STM32_EXTI_BASE + 0x54) +#define STM32_EXTI_CPUIMR1 REG32(STM32_EXTI_BASE + 0x80) +#define STM32_EXTI_CPUIER1 REG32(STM32_EXTI_BASE + 0x84) +#define STM32_EXTI_CPUPR1 REG32(STM32_EXTI_BASE + 0x88) +#define STM32_EXTI_CPUIMR2 REG32(STM32_EXTI_BASE + 0x90) +#define STM32_EXTI_CPUIER2 REG32(STM32_EXTI_BASE + 0x94) +#define STM32_EXTI_CPUPR2 REG32(STM32_EXTI_BASE + 0x98) +#define STM32_EXTI_CPUIMR3 REG32(STM32_EXTI_BASE + 0xA0) +#define STM32_EXTI_CPUIER3 REG32(STM32_EXTI_BASE + 0xA4) +#define STM32_EXTI_CPUPR3 REG32(STM32_EXTI_BASE + 0xA8) /* Aliases */ -#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 -#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 -#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 -#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 -#define STM32_EXTI_PR STM32_EXTI_CPUPR1 - +#define STM32_EXTI_IMR STM32_EXTI_CPUIMR1 +#define STM32_EXTI_EMR STM32_EXTI_CPUIMR1 +#define STM32_EXTI_RTSR STM32_EXTI_RTSR1 +#define STM32_EXTI_FTSR STM32_EXTI_FTSR1 +#define STM32_EXTI_SWIER STM32_EXTI_SWIER1 +#define STM32_EXTI_PR STM32_EXTI_CPUPR1 /* --- ADC --- */ /* --- Comparators --- */ - /* --- DMA --- */ /* * Available DMA streams, numbered from 0. @@ -879,12 +871,12 @@ enum dma_channel { /* Registers for a single stream of a DMA controller */ struct stm32_dma_stream { - uint32_t scr; /* Control */ - uint32_t sndtr; /* Number of data to transfer */ - uint32_t spar; /* Peripheral address */ - uint32_t sm0ar; /* Memory address 0 */ - uint32_t sm1ar; /* address 1 for double buffer */ - uint32_t sfcr; /* FIFO control */ + uint32_t scr; /* Control */ + uint32_t sndtr; /* Number of data to transfer */ + uint32_t spar; /* Peripheral address */ + uint32_t sm0ar; /* Memory address 0 */ + uint32_t sm1ar; /* address 1 for double buffer */ + uint32_t sfcr; /* FIFO control */ }; /* Always use stm32_dma_stream_t so volatile keyword is included! */ @@ -893,12 +885,11 @@ typedef volatile struct stm32_dma_stream stm32_dma_stream_t; /* Common code and header file must use this */ typedef stm32_dma_stream_t dma_chan_t; struct stm32_dma_regs { - uint32_t isr[2]; - uint32_t ifcr[2]; + uint32_t isr[2]; + uint32_t ifcr[2]; stm32_dma_stream_t stream[STM32_DMAS_COUNT]; }; - /* Always use stm32_dma_regs_t so volatile keyword is included! */ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; @@ -909,87 +900,85 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA_REGS(channel) \ ((channel) < STM32_DMAS_COUNT ? STM32_DMA1_REGS : STM32_DMA2_REGS) -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_DMEIE BIT(1) -#define STM32_DMA_CCR_TEIE BIT(2) -#define STM32_DMA_CCR_HTIE BIT(3) -#define STM32_DMA_CCR_TCIE BIT(4) -#define STM32_DMA_CCR_PFCTRL BIT(5) -#define STM32_DMA_CCR_DIR_P2M (0 << 6) -#define STM32_DMA_CCR_DIR_M2P (1 << 6) -#define STM32_DMA_CCR_DIR_M2M (2 << 6) -#define STM32_DMA_CCR_CIRC BIT(8) -#define STM32_DMA_CCR_PINC BIT(9) -#define STM32_DMA_CCR_MINC BIT(10) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) -#define STM32_DMA_CCR_PINCOS BIT(15) -#define STM32_DMA_CCR_PL_LOW (0 << 16) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) -#define STM32_DMA_CCR_PL_HIGH (2 << 16) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) -#define STM32_DMA_CCR_DBM BIT(18) -#define STM32_DMA_CCR_CT BIT(19) -#define STM32_DMA_CCR_PBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_MBURST(b_len) ((((b_len) - 4) / 4) << 21) -#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) -#define STM32_DMA_CCR_CHANNEL(channel) (0) -#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) -#define STM32_DMA_SFCR_DMDIS BIT(2) -#define STM32_DMA_SFCR_FTH(level) (((level) - 1) << 0) - - -#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) -#define STM32_DMA_CH_LH(channel) \ - ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) -#define STM32_DMA_CH_OFFSET(channel) \ +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_DMEIE BIT(1) +#define STM32_DMA_CCR_TEIE BIT(2) +#define STM32_DMA_CCR_HTIE BIT(3) +#define STM32_DMA_CCR_TCIE BIT(4) +#define STM32_DMA_CCR_PFCTRL BIT(5) +#define STM32_DMA_CCR_DIR_P2M (0 << 6) +#define STM32_DMA_CCR_DIR_M2P (1 << 6) +#define STM32_DMA_CCR_DIR_M2M (2 << 6) +#define STM32_DMA_CCR_CIRC BIT(8) +#define STM32_DMA_CCR_PINC BIT(9) +#define STM32_DMA_CCR_MINC BIT(10) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 11) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 11) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 11) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 13) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 13) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 13) +#define STM32_DMA_CCR_PINCOS BIT(15) +#define STM32_DMA_CCR_PL_LOW (0 << 16) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 16) +#define STM32_DMA_CCR_PL_HIGH (2 << 16) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 16) +#define STM32_DMA_CCR_DBM BIT(18) +#define STM32_DMA_CCR_CT BIT(19) +#define STM32_DMA_CCR_PBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_MBURST(b_len) ((((b_len)-4) / 4) << 21) +#define STM32_DMA_CCR_CHANNEL_MASK (0 << 25) +#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_RSVD_MASK (0xF0100000) +#define STM32_DMA_SFCR_DMDIS BIT(2) +#define STM32_DMA_SFCR_FTH(level) (((level)-1) << 0) + +#define STM32_DMA_CH_LOCAL(channel) ((channel) % STM32_DMAS_COUNT) +#define STM32_DMA_CH_LH(channel) ((STM32_DMA_CH_LOCAL(channel) < 4) ? 0 : 1) +#define STM32_DMA_CH_OFFSET(channel) \ (((STM32_DMA_CH_LOCAL(channel) % 4) * 6) + \ - (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) + (((STM32_DMA_CH_LOCAL(channel) % 4) >= 2) ? 4 : 0)) #define STM32_DMA_CH_GETBITS(channel, val) \ (((val) >> STM32_DMA_CH_OFFSET(channel)) & 0x3f) -#define STM32_DMA_GET_IFCR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) -#define STM32_DMA_GET_ISR(channel) \ - (STM32_DMA_CH_GETBITS(channel, \ - STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) - -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ - (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ - ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & 0x3f) << STM32_DMA_CH_OFFSET(channel))) - -#define STM32_DMA_FEIF BIT(0) -#define STM32_DMA_DMEIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_HTIF BIT(4) -#define STM32_DMA_TCIF BIT(5) -#define STM32_DMA_ALL 0x3d - +#define STM32_DMA_GET_IFCR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)])) +#define STM32_DMA_GET_ISR(channel) \ + (STM32_DMA_CH_GETBITS( \ + channel, \ + STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)])) + +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->ifcr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] = \ + (STM32_DMA_REGS(channel)->isr[STM32_DMA_CH_LH(channel)] & \ + ~(0x3f << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&0x3f) << STM32_DMA_CH_OFFSET(channel))) + +#define STM32_DMA_FEIF BIT(0) +#define STM32_DMA_DMEIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_HTIF BIT(4) +#define STM32_DMA_TCIF BIT(5) +#define STM32_DMA_ALL 0x3d /* The requests for the DMA1/DMA2 controllers are routed through DMAMUX1. */ /* DMAMUX1/2 registers */ #define DMAMUX1 0 #define DMAMUX2 1 -#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE \ - : STM32_DMAMUX1_BASE) -#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) -#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) -#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) -#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) -#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) -#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) -#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) +#define STM32_DMAMUX_BASE(n) ((n) ? STM32_DMAMUX2_BASE : STM32_DMAMUX1_BASE) +#define STM32_DMAMUX_REG32(n, off) REG32(STM32_DMAMUX_BASE(n) + (off)) +#define STM2_DMAMUX_CxCR(n, x) STM32_DMAMUX_REG32(n, 4 * (x)) +#define STM2_DMAMUX_CSR(n) STM32_DMAMUX_REG32(n, 0x80) +#define STM2_DMAMUX_CFR(n) STM32_DMAMUX_REG32(n, 0x84) +#define STM2_DMAMUX_RGxCR(n, x) STM32_DMAMUX_REG32(n, 0x100 + 4 * (x)) +#define STM2_DMAMUX_RGSR(n) STM32_DMAMUX_REG32(n, 0x140) +#define STM2_DMAMUX_RGCFR(n) STM32_DMAMUX_REG32(n, 0x144) enum dmamux1_request { DMAMUX1_REQ_ADC1 = 9, @@ -1091,64 +1080,63 @@ enum dmamux1_request { }; /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 5500e4119154056314b401bbd6952b1c3f94eae2 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:43:37 -0600 Subject: chip/stm32/registers-stm32l.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Idcf30bc6916b729321e183a5d43e16afb6e2c12e Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729533 Reviewed-by: Jeremy Bettis --- chip/stm32/registers-stm32l.h | 1146 ++++++++++++++++++++--------------------- 1 file changed, 566 insertions(+), 580 deletions(-) diff --git a/chip/stm32/registers-stm32l.h b/chip/stm32/registers-stm32l.h index 033bbf44b0..25f69487e4 100644 --- a/chip/stm32/registers-stm32l.h +++ b/chip/stm32/registers-stm32l.h @@ -20,401 +20,393 @@ #endif /* --- IRQ numbers --- */ -#define STM32_IRQ_WWDG 0 -#define STM32_IRQ_PVD 1 -#define STM32_IRQ_TAMPER_STAMP 2 -#define STM32_IRQ_RTC_WAKEUP 3 -#define STM32_IRQ_FLASH 4 -#define STM32_IRQ_RCC 5 -#define STM32_IRQ_EXTI0 6 -#define STM32_IRQ_EXTI1 7 -#define STM32_IRQ_EXTI2 8 -#define STM32_IRQ_EXTI3 9 -#define STM32_IRQ_EXTI4 10 -#define STM32_IRQ_DMA_CHANNEL_1 11 -#define STM32_IRQ_DMA_CHANNEL_2 12 -#define STM32_IRQ_DMA_CHANNEL_3 13 -#define STM32_IRQ_DMA_CHANNEL_4 14 -#define STM32_IRQ_DMA_CHANNEL_5 15 -#define STM32_IRQ_DMA_CHANNEL_6 16 -#define STM32_IRQ_DMA_CHANNEL_7 17 -#define STM32_IRQ_USB_HP 19 -#define STM32_IRQ_USB_LP 20 - -#define STM32_IRQ_ADC1 18 /* STM32L4 only */ -#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ -#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ -#define STM32_IRQ_DAC 21 -#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ - -#define STM32_IRQ_COMP 22 - -#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ -#define STM32_IRQ_EXTI9_5 23 -#define STM32_IRQ_LCD 24 /* STM32L15X only */ -#define STM32_IRQ_TIM15 24 /* STM32F373 only */ -#define STM32_IRQ_TIM9 25 /* STM32L15X only */ -#define STM32_IRQ_TIM16 25 /* STM32F373 only */ -#define STM32_IRQ_TIM10 26 /* STM32L15X only */ -#define STM32_IRQ_TIM17 26 /* STM32F373 only */ -#define STM32_IRQ_TIM11 27 /* STM32L15X only */ -#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ -#define STM32_IRQ_TIM2 28 -#define STM32_IRQ_TIM3 29 -#define STM32_IRQ_TIM4 30 -#define STM32_IRQ_I2C1_EV 31 -#define STM32_IRQ_I2C1_ER 32 -#define STM32_IRQ_I2C2_EV 33 -#define STM32_IRQ_I2C2_ER 34 -#define STM32_IRQ_SPI1 35 -#define STM32_IRQ_SPI2 36 -#define STM32_IRQ_USART1 37 -#define STM32_IRQ_USART2 38 -#define STM32_IRQ_USART3 39 -#define STM32_IRQ_EXTI15_10 40 -#define STM32_IRQ_RTC_ALARM 41 -#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ -#define STM32_IRQ_CEC 42 /* STM32F373 only */ -#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ -#define STM32_IRQ_TIM12 43 /* STM32F373 only */ -#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ -#define STM32_IRQ_TIM13 44 /* STM32F373 only */ -#define STM32_IRQ_TIM14 45 /* STM32F373 only */ -#define STM32_IRQ_TIM5 50 /* STM32F373 */ -#define STM32_IRQ_SPI3 51 /* STM32F373 */ -#define STM32_IRQ_USART4 52 /* STM32F446 only */ -#define STM32_IRQ_USART5 53 /* STM32F446 only */ -#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ -#define STM32_IRQ_TIM7 55 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ -#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ +#define STM32_IRQ_WWDG 0 +#define STM32_IRQ_PVD 1 +#define STM32_IRQ_TAMPER_STAMP 2 +#define STM32_IRQ_RTC_WAKEUP 3 +#define STM32_IRQ_FLASH 4 +#define STM32_IRQ_RCC 5 +#define STM32_IRQ_EXTI0 6 +#define STM32_IRQ_EXTI1 7 +#define STM32_IRQ_EXTI2 8 +#define STM32_IRQ_EXTI3 9 +#define STM32_IRQ_EXTI4 10 +#define STM32_IRQ_DMA_CHANNEL_1 11 +#define STM32_IRQ_DMA_CHANNEL_2 12 +#define STM32_IRQ_DMA_CHANNEL_3 13 +#define STM32_IRQ_DMA_CHANNEL_4 14 +#define STM32_IRQ_DMA_CHANNEL_5 15 +#define STM32_IRQ_DMA_CHANNEL_6 16 +#define STM32_IRQ_DMA_CHANNEL_7 17 +#define STM32_IRQ_USB_HP 19 +#define STM32_IRQ_USB_LP 20 + +#define STM32_IRQ_ADC1 18 /* STM32L4 only */ +#define STM32_IRQ_CAN_TX 19 /* STM32F373 only */ +#define STM32_IRQ_USB_LP_CAN_RX 20 /* STM32F373 only */ +#define STM32_IRQ_DAC 21 +#define STM32_IRQ_CAN_RX1 21 /* STM32F373 only */ + +#define STM32_IRQ_COMP 22 + +#define STM32_IRQ_CAN_SCE 22 /* STM32F373 only */ +#define STM32_IRQ_EXTI9_5 23 +#define STM32_IRQ_LCD 24 /* STM32L15X only */ +#define STM32_IRQ_TIM15 24 /* STM32F373 only */ +#define STM32_IRQ_TIM9 25 /* STM32L15X only */ +#define STM32_IRQ_TIM16 25 /* STM32F373 only */ +#define STM32_IRQ_TIM10 26 /* STM32L15X only */ +#define STM32_IRQ_TIM17 26 /* STM32F373 only */ +#define STM32_IRQ_TIM11 27 /* STM32L15X only */ +#define STM32_IRQ_TIM18_DAC2 27 /* STM32F373 only */ +#define STM32_IRQ_TIM2 28 +#define STM32_IRQ_TIM3 29 +#define STM32_IRQ_TIM4 30 +#define STM32_IRQ_I2C1_EV 31 +#define STM32_IRQ_I2C1_ER 32 +#define STM32_IRQ_I2C2_EV 33 +#define STM32_IRQ_I2C2_ER 34 +#define STM32_IRQ_SPI1 35 +#define STM32_IRQ_SPI2 36 +#define STM32_IRQ_USART1 37 +#define STM32_IRQ_USART2 38 +#define STM32_IRQ_USART3 39 +#define STM32_IRQ_EXTI15_10 40 +#define STM32_IRQ_RTC_ALARM 41 +#define STM32_IRQ_USB_FS_WAKEUP 42 /* STM32L15X */ +#define STM32_IRQ_CEC 42 /* STM32F373 only */ +#define STM32_IRQ_TIM6_BASIC 43 /* STM32L15X only */ +#define STM32_IRQ_TIM12 43 /* STM32F373 only */ +#define STM32_IRQ_TIM7_BASIC 44 /* STM32L15X only */ +#define STM32_IRQ_TIM13 44 /* STM32F373 only */ +#define STM32_IRQ_TIM14 45 /* STM32F373 only */ +#define STM32_IRQ_TIM5 50 /* STM32F373 */ +#define STM32_IRQ_SPI3 51 /* STM32F373 */ +#define STM32_IRQ_USART4 52 /* STM32F446 only */ +#define STM32_IRQ_USART5 53 /* STM32F446 only */ +#define STM32_IRQ_TIM6_DAC 54 /* STM32F373 */ +#define STM32_IRQ_TIM7 55 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL1 56 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL2 57 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL3 58 /* STM32F373 */ +#define STM32_IRQ_DMA2_CHANNEL4 59 /* STM32F373 only */ /* if MISC_REMAP bits are set */ -#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ -#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ -#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ -#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ -#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ -#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ -#define STM32_IRQ_LPUART 70 /* STM32L4 only */ -#define STM32_IRQ_USART9 70 /* STM32L4 only */ -#define STM32_IRQ_USART6 71 /* STM32F446 only */ -#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ -#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ -#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ -#define STM32_IRQ_TIM19 78 /* STM32F373 only */ -#define STM32_IRQ_AES 79 /* STM32L4 only */ -#define STM32_IRQ_RNG 80 /* STM32L4 only */ -#define STM32_IRQ_FPU 81 /* STM32F373 only */ - +#define STM32_IRQ_DMA2_CHANNEL5 60 /* STM32F373 */ +#define STM32_IRQ_SDADC1 61 /* STM32F373 only */ +#define STM32_IRQ_SDADC2 62 /* STM32F373 only */ +#define STM32_IRQ_SDADC3 63 /* STM32F373 only */ +#define STM32_IRQ_DMA2_CHANNEL6 68 /* STM32L4 only */ +#define STM32_IRQ_DMA2_CHANNEL7 69 /* STM32L4 only */ +#define STM32_IRQ_LPUART 70 /* STM32L4 only */ +#define STM32_IRQ_USART9 70 /* STM32L4 only */ +#define STM32_IRQ_USART6 71 /* STM32F446 only */ +#define STM32_IRQ_I2C3_EV 72 /* STM32F446 only */ +#define STM32_IRQ_I2C3_ER 73 /* STM32F446 only */ +#define STM32_IRQ_USB_WAKEUP 76 /* STM32F373 only */ +#define STM32_IRQ_TIM19 78 /* STM32F373 only */ +#define STM32_IRQ_AES 79 /* STM32L4 only */ +#define STM32_IRQ_RNG 80 /* STM32L4 only */ +#define STM32_IRQ_FPU 81 /* STM32F373 only */ /* To simplify code generation, define DMA channel 9..10 */ -#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 -#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 -#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 -#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 +#define STM32_IRQ_DMA_CHANNEL_9 STM32_IRQ_DMA2_CHANNEL1 +#define STM32_IRQ_DMA_CHANNEL_10 STM32_IRQ_DMA2_CHANNEL2 +#define STM32_IRQ_DMA_CHANNEL_13 STM32_IRQ_DMA2_CHANNEL6 +#define STM32_IRQ_DMA_CHANNEL_14 STM32_IRQ_DMA2_CHANNEL7 /* aliases for easier code sharing */ #define STM32_IRQ_I2C1 STM32_IRQ_I2C1_EV #define STM32_IRQ_I2C2 STM32_IRQ_I2C2_EV #define STM32_IRQ_I2C3 STM32_IRQ_I2C3_EV - - /* Peripheral base addresses */ -#define STM32_ADC1_BASE 0x40012400 -#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ - -#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ -#define STM32_CRC_BASE 0x40023000 -#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ -#define STM32_DAC_BASE 0x40007400 +#define STM32_ADC1_BASE 0x40012400 +#define STM32_ADC_BASE 0x40012700 /* STM32L15X only */ -#define STM32_COMP_BASE 0x40007C00 +#define STM32_CEC_BASE 0x40007800 /* STM32F373 */ +#define STM32_CRC_BASE 0x40023000 +#define STM32_CRS_BASE 0x40006c00 /* STM32F0XX */ +#define STM32_DAC_BASE 0x40007400 -#define STM32_DBGMCU_BASE 0xE0042000 +#define STM32_COMP_BASE 0x40007C00 -#define STM32_DMA1_BASE 0x40026000 +#define STM32_DBGMCU_BASE 0xE0042000 -#define STM32_EXTI_BASE 0x40010400 +#define STM32_DMA1_BASE 0x40026000 -#define STM32_FLASH_REGS_BASE 0x40023c00 +#define STM32_EXTI_BASE 0x40010400 -#define STM32_GPIOA_BASE 0x40020000 -#define STM32_GPIOB_BASE 0x40020400 -#define STM32_GPIOC_BASE 0x40020800 -#define STM32_GPIOD_BASE 0x40020C00 -#define STM32_GPIOE_BASE 0x40021000 -#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ -#define STM32_GPIOG_BASE 0x40021C00 -#define STM32_GPIOH_BASE 0x40021400 +#define STM32_FLASH_REGS_BASE 0x40023c00 -#define STM32_I2C1_BASE 0x40005400 -#define STM32_I2C2_BASE 0x40005800 -#define STM32_I2C3_BASE 0x40005C00 -#define STM32_I2C4_BASE 0x40006000 +#define STM32_GPIOA_BASE 0x40020000 +#define STM32_GPIOB_BASE 0x40020400 +#define STM32_GPIOC_BASE 0x40020800 +#define STM32_GPIOD_BASE 0x40020C00 +#define STM32_GPIOE_BASE 0x40021000 +#define STM32_GPIOF_BASE 0x40021800 /* see RM0038 table 5 */ +#define STM32_GPIOG_BASE 0x40021C00 +#define STM32_GPIOH_BASE 0x40021400 -#define STM32_IWDG_BASE 0x40003000 -#define STM32_LCD_BASE 0x40002400 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C4_BASE 0x40006000 -#define STM32_OPTB_BASE 0x1ff80000 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_LCD_BASE 0x40002400 -#define STM32_PMSE_BASE 0x40013400 -#define STM32_PWR_BASE 0x40007000 +#define STM32_OPTB_BASE 0x1ff80000 -#define STM32_RCC_BASE 0x40023800 +#define STM32_PMSE_BASE 0x40013400 +#define STM32_PWR_BASE 0x40007000 -#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ -#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ -#define STM32_RTC_BASE 0x40002800 +#define STM32_RCC_BASE 0x40023800 -#define STM32_SPI1_BASE 0x40013000 -#define STM32_SPI2_BASE 0x40003800 -#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ +#define STM32_RI_BASE 0x40007C00 /* STM32L1xx only */ +#define STM32_RNG_BASE 0x50060800 /* STM32L4 */ +#define STM32_RTC_BASE 0x40002800 -#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_SPI3_BASE 0x40003c00 /* STM32F373, STM32L4, STM32F7 */ -#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ -#define STM32_TIM2_BASE 0x40000000 -#define STM32_TIM3_BASE 0x40000400 -#define STM32_TIM4_BASE 0x40000800 -#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ -#define STM32_TIM6_BASE 0x40001000 -#define STM32_TIM7_BASE 0x40001400 -#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ -#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ -#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ -#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ -#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ -#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ -#define STM32_TIM15_BASE 0x40014000 -#define STM32_TIM16_BASE 0x40014400 -#define STM32_TIM17_BASE 0x40014800 -#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ -#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ +#define STM32_SYSCFG_BASE 0x40010000 -#define STM32_UNIQUE_ID_BASE 0x1ffff7ac +#define STM32_TIM1_BASE 0x40012c00 /* STM32F373 */ +#define STM32_TIM2_BASE 0x40000000 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM5_BASE 0x40000c00 /* STM32F373 */ +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ +#define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ +#define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ +#define STM32_TIM12_BASE 0x40001800 /* STM32F373 */ +#define STM32_TIM13_BASE 0x40001c00 /* STM32F373 */ +#define STM32_TIM14_BASE 0x40002000 /* STM32F373 */ +#define STM32_TIM15_BASE 0x40014000 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM18_BASE 0x40009c00 /* STM32F373 only */ +#define STM32_TIM19_BASE 0x40015c00 /* STM32F373 only */ -#define STM32_USART1_BASE 0x40013800 -#define STM32_USART2_BASE 0x40004400 -#define STM32_USART3_BASE 0x40004800 -#define STM32_USART4_BASE 0x40004c00 -#define STM32_USART9_BASE 0x40008000 /* LPUART */ +#define STM32_UNIQUE_ID_BASE 0x1ffff7ac -#define STM32_USB_CAN_SRAM_BASE 0x40006000 -#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_USART1_BASE 0x40013800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART4_BASE 0x40004c00 +#define STM32_USART9_BASE 0x40008000 /* LPUART */ -#define STM32_WWDG_BASE 0x40002C00 +#define STM32_USB_CAN_SRAM_BASE 0x40006000 +#define STM32_USB_FS_BASE 0x40005C00 +#define STM32_WWDG_BASE 0x40002C00 #ifndef __ASSEMBLER__ /* Register definitions */ /* --- USART --- */ -#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) -#define STM32_USART_SR_ORE BIT(3) -#define STM32_USART_SR_RXNE BIT(5) -#define STM32_USART_SR_TC BIT(6) -#define STM32_USART_SR_TXE BIT(7) -#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) -#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) -#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) -#define STM32_USART_CR1_RE BIT(2) -#define STM32_USART_CR1_TE BIT(3) -#define STM32_USART_CR1_RXNEIE BIT(5) -#define STM32_USART_CR1_TCIE BIT(6) -#define STM32_USART_CR1_TXEIE BIT(7) -#define STM32_USART_CR1_PS BIT(9) -#define STM32_USART_CR1_PCE BIT(10) -#define STM32_USART_CR1_M BIT(12) -#define STM32_USART_CR1_UE BIT(13) -#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ -#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) -#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) -#define STM32_USART_CR3_EIE BIT(0) -#define STM32_USART_CR3_DMAR BIT(6) -#define STM32_USART_CR3_DMAT BIT(7) -#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ -#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) +#define STM32_USART_SR(base) STM32_USART_REG(base, 0x00) +#define STM32_USART_SR_ORE BIT(3) +#define STM32_USART_SR_RXNE BIT(5) +#define STM32_USART_SR_TC BIT(6) +#define STM32_USART_SR_TXE BIT(7) +#define STM32_USART_DR(base) STM32_USART_REG(base, 0x04) +#define STM32_USART_BRR(base) STM32_USART_REG(base, 0x08) +#define STM32_USART_CR1(base) STM32_USART_REG(base, 0x0C) +#define STM32_USART_CR1_RE BIT(2) +#define STM32_USART_CR1_TE BIT(3) +#define STM32_USART_CR1_RXNEIE BIT(5) +#define STM32_USART_CR1_TCIE BIT(6) +#define STM32_USART_CR1_TXEIE BIT(7) +#define STM32_USART_CR1_PS BIT(9) +#define STM32_USART_CR1_PCE BIT(10) +#define STM32_USART_CR1_M BIT(12) +#define STM32_USART_CR1_UE BIT(13) +#define STM32_USART_CR1_OVER8 BIT(15) /* STM32L only */ +#define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) +#define STM32_USART_CR3(base) STM32_USART_REG(base, 0x14) +#define STM32_USART_CR3_EIE BIT(0) +#define STM32_USART_CR3_DMAR BIT(6) +#define STM32_USART_CR3_DMAT BIT(7) +#define STM32_USART_CR3_ONEBIT BIT(11) /* STM32L only */ +#define STM32_USART_GTPR(base) STM32_USART_REG(base, 0x18) /* register aliases */ -#define STM32_USART_TDR(base) STM32_USART_DR(base) -#define STM32_USART_RDR(base) STM32_USART_DR(base) +#define STM32_USART_TDR(base) STM32_USART_DR(base) +#define STM32_USART_RDR(base) STM32_USART_DR(base) /* --- GPIO --- */ - -#define STM32_GPIO_MODER(b) REG32((b) + 0x00) -#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) -#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) -#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) -#define STM32_GPIO_IDR(b) REG16((b) + 0x10) -#define STM32_GPIO_ODR(b) REG16((b) + 0x14) -#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) -#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) -#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) -#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) - -#define GPIO_ALT_SYS 0x0 -#define GPIO_ALT_TIM2 0x1 -#define GPIO_ALT_TIM3_4 0x2 -#define GPIO_ALT_TIM9_11 0x3 -#define GPIO_ALT_I2C 0x4 -#define GPIO_ALT_SPI 0x5 -#define GPIO_ALT_SPI3 0x6 -#define GPIO_ALT_USART 0x7 -#define GPIO_ALT_I2C_23 0x9 -#define GPIO_ALT_USB 0xA -#define GPIO_ALT_LCD 0xB -#define GPIO_ALT_RI 0xE -#define GPIO_ALT_EVENTOUT 0xF +#define STM32_GPIO_MODER(b) REG32((b) + 0x00) +#define STM32_GPIO_OTYPER(b) REG16((b) + 0x04) +#define STM32_GPIO_OSPEEDR(b) REG32((b) + 0x08) +#define STM32_GPIO_PUPDR(b) REG32((b) + 0x0C) +#define STM32_GPIO_IDR(b) REG16((b) + 0x10) +#define STM32_GPIO_ODR(b) REG16((b) + 0x14) +#define STM32_GPIO_BSRR(b) REG32((b) + 0x18) +#define STM32_GPIO_LCKR(b) REG32((b) + 0x1C) +#define STM32_GPIO_AFRL(b) REG32((b) + 0x20) +#define STM32_GPIO_AFRH(b) REG32((b) + 0x24) + +#define GPIO_ALT_SYS 0x0 +#define GPIO_ALT_TIM2 0x1 +#define GPIO_ALT_TIM3_4 0x2 +#define GPIO_ALT_TIM9_11 0x3 +#define GPIO_ALT_I2C 0x4 +#define GPIO_ALT_SPI 0x5 +#define GPIO_ALT_SPI3 0x6 +#define GPIO_ALT_USART 0x7 +#define GPIO_ALT_I2C_23 0x9 +#define GPIO_ALT_USB 0xA +#define GPIO_ALT_LCD 0xB +#define GPIO_ALT_RI 0xE +#define GPIO_ALT_EVENTOUT 0xF /* --- I2C --- */ -#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) -#define STM32_I2C_CR1_PE BIT(0) -#define STM32_I2C_CR1_START BIT(8) -#define STM32_I2C_CR1_STOP BIT(9) -#define STM32_I2C_CR1_ACK BIT(10) -#define STM32_I2C_CR1_POS BIT(11) -#define STM32_I2C_CR1_SWRST BIT(15) -#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) -#define STM32_I2C_CR2_ITERREN BIT(8) -#define STM32_I2C_CR2_ITEVTEN BIT(9) -#define STM32_I2C_CR2_ITBUFEN BIT(10) -#define STM32_I2C_CR2_DMAEN BIT(11) -#define STM32_I2C_CR2_LAST BIT(12) -#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) -#define STM32_I2C_OAR1_B14 BIT(14) -#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) -#define STM32_I2C_OAR2_ENDUAL BIT(0) -#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) -#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) -#define STM32_I2C_SR1_SB BIT(0) -#define STM32_I2C_SR1_ADDR BIT(1) -#define STM32_I2C_SR1_BTF BIT(2) -#define STM32_I2C_SR1_STOPF BIT(4) -#define STM32_I2C_SR1_RXNE BIT(6) -#define STM32_I2C_SR1_TXE BIT(7) -#define STM32_I2C_SR1_BERR BIT(8) -#define STM32_I2C_SR1_ARLO BIT(9) -#define STM32_I2C_SR1_AF BIT(10) - -#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) -#define STM32_I2C_SR2_BUSY BIT(1) -#define STM32_I2C_SR2_TRA BIT(2) -#define STM32_I2C_SR2_DUALF BIT(7) - -#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) -#define STM32_I2C_CCR_DUTY BIT(14) -#define STM32_I2C_CCR_FM BIT(15) -#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) - +#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00)) +#define STM32_I2C_CR1_PE BIT(0) +#define STM32_I2C_CR1_START BIT(8) +#define STM32_I2C_CR1_STOP BIT(9) +#define STM32_I2C_CR1_ACK BIT(10) +#define STM32_I2C_CR1_POS BIT(11) +#define STM32_I2C_CR1_SWRST BIT(15) +#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04)) +#define STM32_I2C_CR2_ITERREN BIT(8) +#define STM32_I2C_CR2_ITEVTEN BIT(9) +#define STM32_I2C_CR2_ITBUFEN BIT(10) +#define STM32_I2C_CR2_DMAEN BIT(11) +#define STM32_I2C_CR2_LAST BIT(12) +#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08)) +#define STM32_I2C_OAR1_B14 BIT(14) +#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C)) +#define STM32_I2C_OAR2_ENDUAL BIT(0) +#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10)) +#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14)) +#define STM32_I2C_SR1_SB BIT(0) +#define STM32_I2C_SR1_ADDR BIT(1) +#define STM32_I2C_SR1_BTF BIT(2) +#define STM32_I2C_SR1_STOPF BIT(4) +#define STM32_I2C_SR1_RXNE BIT(6) +#define STM32_I2C_SR1_TXE BIT(7) +#define STM32_I2C_SR1_BERR BIT(8) +#define STM32_I2C_SR1_ARLO BIT(9) +#define STM32_I2C_SR1_AF BIT(10) + +#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18)) +#define STM32_I2C_SR2_BUSY BIT(1) +#define STM32_I2C_SR2_TRA BIT(2) +#define STM32_I2C_SR2_DUALF BIT(7) + +#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C)) +#define STM32_I2C_CCR_DUTY BIT(14) +#define STM32_I2C_CCR_FM BIT(15) +#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20)) /* --- Power / Reset / Clocks --- */ -#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) - - -#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) -#define STM32_RCC_CR_HSION BIT(0) -#define STM32_RCC_CR_HSIRDY BIT(1) -#define STM32_RCC_CR_MSION BIT(8) -#define STM32_RCC_CR_MSIRDY BIT(9) -#define STM32_RCC_CR_PLLON BIT(24) -#define STM32_RCC_CR_PLLRDY BIT(25) -#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) -#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) -#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) -#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) -#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) -#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) -#define STM32_RCC_CFGR_SW_MSI (0 << 0) -#define STM32_RCC_CFGR_SW_HSI (1 << 0) -#define STM32_RCC_CFGR_SW_HSE (2 << 0) -#define STM32_RCC_CFGR_SW_PLL (3 << 0) -#define STM32_RCC_CFGR_SW_MASK (3 << 0) -#define STM32_RCC_CFGR_SWS_MSI (0 << 2) -#define STM32_RCC_CFGR_SWS_HSI (1 << 2) -#define STM32_RCC_CFGR_SWS_HSE (2 << 2) -#define STM32_RCC_CFGR_SWS_PLL (3 << 2) -#define STM32_RCC_CFGR_SWS_MASK (3 << 2) -#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) -#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) -#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) -#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) -#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) -#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) -#define STM32_RCC_SYSCFGEN BIT(0) - -#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) -#define STM32_RCC_PWREN BIT(28) - -#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) -#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) -#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) -#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) - -#define STM32_RCC_HB_DMA1 BIT(24) -#define STM32_RCC_PB2_TIM9 BIT(2) -#define STM32_RCC_PB2_TIM10 BIT(3) -#define STM32_RCC_PB2_TIM11 BIT(4) -#define STM32_RCC_PB1_USB BIT(23) - -#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) -#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) - +#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) + +#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) +#define STM32_RCC_CR_HSION BIT(0) +#define STM32_RCC_CR_HSIRDY BIT(1) +#define STM32_RCC_CR_MSION BIT(8) +#define STM32_RCC_CR_MSIRDY BIT(9) +#define STM32_RCC_CR_PLLON BIT(24) +#define STM32_RCC_CR_PLLRDY BIT(25) +#define STM32_RCC_ICSCR REG32(STM32_RCC_BASE + 0x04) +#define STM32_RCC_ICSCR_MSIRANGE(n) ((n) << 13) +#define STM32_RCC_ICSCR_MSIRANGE_1MHZ STM32_RCC_ICSCR_MSIRANGE(4) +#define STM32_RCC_ICSCR_MSIRANGE_2MHZ STM32_RCC_ICSCR_MSIRANGE(5) +#define STM32_RCC_ICSCR_MSIRANGE_MASK STM32_RCC_ICSCR_MSIRANGE(7) +#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08) +#define STM32_RCC_CFGR_SW_MSI (0 << 0) +#define STM32_RCC_CFGR_SW_HSI (1 << 0) +#define STM32_RCC_CFGR_SW_HSE (2 << 0) +#define STM32_RCC_CFGR_SW_PLL (3 << 0) +#define STM32_RCC_CFGR_SW_MASK (3 << 0) +#define STM32_RCC_CFGR_SWS_MSI (0 << 2) +#define STM32_RCC_CFGR_SWS_HSI (1 << 2) +#define STM32_RCC_CFGR_SWS_HSE (2 << 2) +#define STM32_RCC_CFGR_SWS_PLL (3 << 2) +#define STM32_RCC_CFGR_SWS_MASK (3 << 2) +#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C) +#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10) +#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14) +#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18) +#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C) +#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20) +#define STM32_RCC_SYSCFGEN BIT(0) + +#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24) +#define STM32_RCC_PWREN BIT(28) + +#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28) +#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C) +#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30) +#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34) + +#define STM32_RCC_HB_DMA1 BIT(24) +#define STM32_RCC_PB2_TIM9 BIT(2) +#define STM32_RCC_PB2_TIM10 BIT(3) +#define STM32_RCC_PB2_TIM11 BIT(4) +#define STM32_RCC_PB1_USB BIT(23) + +#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00) +#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) +#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) /* Peripheral bits for RCC_APB/AHB and DBGMCU regs */ -#define STM32_RCC_PB2_USART1 BIT(14) +#define STM32_RCC_PB2_USART1 BIT(14) /* Reset causes definitions */ /* Reset causes in RCC CSR register */ #define STM32_RCC_RESET_CAUSE STM32_RCC_CSR -#define RESET_CAUSE_WDG 0x60000000 -#define RESET_CAUSE_SFT 0x10000000 -#define RESET_CAUSE_POR 0x08000000 -#define RESET_CAUSE_PIN 0x04000000 -#define RESET_CAUSE_OTHER 0xfe000000 -#define RESET_CAUSE_RMVF 0x01000000 +#define RESET_CAUSE_WDG 0x60000000 +#define RESET_CAUSE_SFT 0x10000000 +#define RESET_CAUSE_POR 0x08000000 +#define RESET_CAUSE_PIN 0x04000000 +#define RESET_CAUSE_OTHER 0xfe000000 +#define RESET_CAUSE_RMVF 0x01000000 /* Power cause in PWR CSR register */ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF 0x00000002 -#define RESET_CAUSE_SBF_CLR 0x00000004 +#define RESET_CAUSE_SBF 0x00000002 +#define RESET_CAUSE_SBF_CLR 0x00000004 /* --- Watchdogs --- */ /* --- Real-Time Clock --- */ -#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) -#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) -#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) -#define STM32_RTC_CR_BYPSHAD BIT(5) -#define STM32_RTC_CR_ALRAE BIT(8) -#define STM32_RTC_CR_ALRAIE BIT(12) -#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) -#define STM32_RTC_ISR_ALRAWF BIT(0) -#define STM32_RTC_ISR_RSF BIT(5) -#define STM32_RTC_ISR_INITF BIT(6) -#define STM32_RTC_ISR_INIT BIT(7) -#define STM32_RTC_ISR_ALRAF BIT(8) -#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) -#define STM32_RTC_PRER_A_MASK (0x7f << 16) -#define STM32_RTC_PRER_S_MASK (0x7fff << 0) -#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) -#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) -#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) -#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) -#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) -#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) -#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) -#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) -#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) -#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) -#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) - -#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) -#define STM32_BKP_BYTES 80 +#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) +#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) +#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) +#define STM32_RTC_CR_BYPSHAD BIT(5) +#define STM32_RTC_CR_ALRAE BIT(8) +#define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C) +#define STM32_RTC_ISR_ALRAWF BIT(0) +#define STM32_RTC_ISR_RSF BIT(5) +#define STM32_RTC_ISR_INITF BIT(6) +#define STM32_RTC_ISR_INIT BIT(7) +#define STM32_RTC_ISR_ALRAF BIT(8) +#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10) +#define STM32_RTC_PRER_A_MASK (0x7f << 16) +#define STM32_RTC_PRER_S_MASK (0x7fff << 0) +#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14) +#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18) +#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C) +#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20) +#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24) +#define STM32_RTC_SSR REG32(STM32_RTC_BASE + 0x28) +#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30) +#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34) +#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40) +#define STM32_RTC_ALRMASSR REG32(STM32_RTC_BASE + 0x44) +#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n)) + +#define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) +#define STM32_BKP_BYTES 80 /* --- SPI --- */ @@ -431,8 +423,8 @@ struct stm32_spi_regs { unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; - unsigned i2scfgr; /* STM32L only */ - unsigned i2spr; /* STM32L only */ + unsigned i2scfgr; /* STM32L only */ + unsigned i2spr; /* STM32L only */ }; /* Must be volatile, or compiler optimizes out repeated accesses */ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; @@ -442,146 +434,144 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_SPI3_REGS ((stm32_spi_regs_t *)STM32_SPI3_BASE) #define STM32_SPI4_REGS ((stm32_spi_regs_t *)STM32_SPI4_BASE) -#define STM32_SPI_CR1_BIDIMODE BIT(15) -#define STM32_SPI_CR1_BIDIOE BIT(14) -#define STM32_SPI_CR1_CRCEN BIT(13) -#define STM32_SPI_CR1_SSM BIT(9) -#define STM32_SPI_CR1_SSI BIT(8) -#define STM32_SPI_CR1_LSBFIRST BIT(7) -#define STM32_SPI_CR1_SPE BIT(6) -#define STM32_SPI_CR1_BR_DIV64R (5 << 3) -#define STM32_SPI_CR1_BR_DIV4R BIT(3) -#define STM32_SPI_CR1_MSTR BIT(2) -#define STM32_SPI_CR1_CPOL BIT(1) -#define STM32_SPI_CR1_CPHA BIT(0) -#define STM32_SPI_CR2_FRXTH BIT(12) -#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8) -#define STM32_SPI_CR2_TXEIE BIT(7) -#define STM32_SPI_CR2_RXNEIE BIT(6) -#define STM32_SPI_CR2_NSSP BIT(3) -#define STM32_SPI_CR2_SSOE BIT(2) -#define STM32_SPI_CR2_TXDMAEN BIT(1) -#define STM32_SPI_CR2_RXDMAEN BIT(0) - -#define STM32_SPI_SR_RXNE BIT(0) -#define STM32_SPI_SR_TXE BIT(1) -#define STM32_SPI_SR_CRCERR BIT(4) -#define STM32_SPI_SR_BSY BIT(7) -#define STM32_SPI_SR_FRLVL (3 << 9) -#define STM32_SPI_SR_FTLVL (3 << 11) +#define STM32_SPI_CR1_BIDIMODE BIT(15) +#define STM32_SPI_CR1_BIDIOE BIT(14) +#define STM32_SPI_CR1_CRCEN BIT(13) +#define STM32_SPI_CR1_SSM BIT(9) +#define STM32_SPI_CR1_SSI BIT(8) +#define STM32_SPI_CR1_LSBFIRST BIT(7) +#define STM32_SPI_CR1_SPE BIT(6) +#define STM32_SPI_CR1_BR_DIV64R (5 << 3) +#define STM32_SPI_CR1_BR_DIV4R BIT(3) +#define STM32_SPI_CR1_MSTR BIT(2) +#define STM32_SPI_CR1_CPOL BIT(1) +#define STM32_SPI_CR1_CPHA BIT(0) +#define STM32_SPI_CR2_FRXTH BIT(12) +#define STM32_SPI_CR2_DATASIZE(n) (((n)-1) << 8) +#define STM32_SPI_CR2_TXEIE BIT(7) +#define STM32_SPI_CR2_RXNEIE BIT(6) +#define STM32_SPI_CR2_NSSP BIT(3) +#define STM32_SPI_CR2_SSOE BIT(2) +#define STM32_SPI_CR2_TXDMAEN BIT(1) +#define STM32_SPI_CR2_RXDMAEN BIT(0) + +#define STM32_SPI_SR_RXNE BIT(0) +#define STM32_SPI_SR_TXE BIT(1) +#define STM32_SPI_SR_CRCERR BIT(4) +#define STM32_SPI_SR_BSY BIT(7) +#define STM32_SPI_SR_FRLVL (3 << 9) +#define STM32_SPI_SR_FTLVL (3 << 11) /* --- Debug --- */ -#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) -#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) +#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08) +#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C) /* --- Flash --- */ -#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) -#define STM32_FLASH_ACR_LATENCY BIT(0) -#define STM32_FLASH_ACR_PRFTEN BIT(1) -#define STM32_FLASH_ACR_ACC64 BIT(2) -#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) -#define STM32_FLASH_PECR_PE_LOCK BIT(0) -#define STM32_FLASH_PECR_PRG_LOCK BIT(1) -#define STM32_FLASH_PECR_OPT_LOCK BIT(2) -#define STM32_FLASH_PECR_PROG BIT(3) -#define STM32_FLASH_PECR_ERASE BIT(9) -#define STM32_FLASH_PECR_FPRG BIT(10) -#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) -#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) -#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) -#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF -#define STM32_FLASH_PEKEYR_KEY2 0x02030405 -#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) -#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF -#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 -#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) -#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 -#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 -#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) -#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) -#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) - -#define STM32_OPTB_RDP 0x00 -#define STM32_OPTB_USER 0x04 -#define STM32_OPTB_WRP1L 0x08 -#define STM32_OPTB_WRP1H 0x0c -#define STM32_OPTB_WRP2L 0x10 -#define STM32_OPTB_WRP2H 0x14 -#define STM32_OPTB_WRP3L 0x18 -#define STM32_OPTB_WRP3H 0x1c +#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) +#define STM32_FLASH_ACR_LATENCY BIT(0) +#define STM32_FLASH_ACR_PRFTEN BIT(1) +#define STM32_FLASH_ACR_ACC64 BIT(2) +#define STM32_FLASH_PECR REG32(STM32_FLASH_REGS_BASE + 0x04) +#define STM32_FLASH_PECR_PE_LOCK BIT(0) +#define STM32_FLASH_PECR_PRG_LOCK BIT(1) +#define STM32_FLASH_PECR_OPT_LOCK BIT(2) +#define STM32_FLASH_PECR_PROG BIT(3) +#define STM32_FLASH_PECR_ERASE BIT(9) +#define STM32_FLASH_PECR_FPRG BIT(10) +#define STM32_FLASH_PECR_OBL_LAUNCH BIT(18) +#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x08) +#define STM32_FLASH_PEKEYR REG32(STM32_FLASH_REGS_BASE + 0x0c) +#define STM32_FLASH_PEKEYR_KEY1 0x89ABCDEF +#define STM32_FLASH_PEKEYR_KEY2 0x02030405 +#define STM32_FLASH_PRGKEYR REG32(STM32_FLASH_REGS_BASE + 0x10) +#define STM32_FLASH_PRGKEYR_KEY1 0x8C9DAEBF +#define STM32_FLASH_PRGKEYR_KEY2 0x13141516 +#define STM32_FLASH_OPTKEYR REG32(STM32_FLASH_REGS_BASE + 0x14) +#define STM32_FLASH_OPTKEYR_KEY1 0xFBEAD9C8 +#define STM32_FLASH_OPTKEYR_KEY2 0x24252627 +#define STM32_FLASH_SR REG32(STM32_FLASH_REGS_BASE + 0x18) +#define STM32_FLASH_OBR REG32(STM32_FLASH_REGS_BASE + 0x1c) +#define STM32_FLASH_WRPR REG32(STM32_FLASH_REGS_BASE + 0x20) + +#define STM32_OPTB_RDP 0x00 +#define STM32_OPTB_USER 0x04 +#define STM32_OPTB_WRP1L 0x08 +#define STM32_OPTB_WRP1H 0x0c +#define STM32_OPTB_WRP2L 0x10 +#define STM32_OPTB_WRP2H 0x14 +#define STM32_OPTB_WRP3L 0x18 +#define STM32_OPTB_WRP3H 0x1c /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) - +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) /* --- ADC --- */ -#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) -#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) -#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) -#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) -#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) -#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) -#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) -#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) -#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) -#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) -#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) -#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) -#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n) * 4) -#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) -#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) -#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) -#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) -#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) -#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) -#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) -#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) -#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) -#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) -#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) - -#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) +#define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) +#define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) +#define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) +#define STM32_ADC_SMPR1 REG32(STM32_ADC1_BASE + 0x0C) +#define STM32_ADC_SMPR2 REG32(STM32_ADC1_BASE + 0x10) +#define STM32_ADC_SMPR3 REG32(STM32_ADC1_BASE + 0x14) +#define STM32_ADC_JOFR1 REG32(STM32_ADC1_BASE + 0x18) +#define STM32_ADC_JOFR2 REG32(STM32_ADC1_BASE + 0x1C) +#define STM32_ADC_JOFR3 REG32(STM32_ADC1_BASE + 0x20) +#define STM32_ADC_JOFR4 REG32(STM32_ADC1_BASE + 0x24) +#define STM32_ADC_HTR REG32(STM32_ADC1_BASE + 0x28) +#define STM32_ADC_LTR REG32(STM32_ADC1_BASE + 0x2C) +#define STM32_ADC_SQR(n) REG32(STM32_ADC1_BASE + 0x2C + (n)*4) +#define STM32_ADC_SQR1 REG32(STM32_ADC1_BASE + 0x30) +#define STM32_ADC_SQR2 REG32(STM32_ADC1_BASE + 0x34) +#define STM32_ADC_SQR3 REG32(STM32_ADC1_BASE + 0x38) +#define STM32_ADC_SQR4 REG32(STM32_ADC1_BASE + 0x3C) +#define STM32_ADC_SQR5 REG32(STM32_ADC1_BASE + 0x40) +#define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x44) +#define STM32_ADC_JDR1 REG32(STM32_ADC1_BASE + 0x48) +#define STM32_ADC_JDR2 REG32(STM32_ADC1_BASE + 0x4C) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR3 REG32(STM32_ADC1_BASE + 0x50) +#define STM32_ADC_JDR4 REG32(STM32_ADC1_BASE + 0x54) +#define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x58) +#define STM32_ADC_SMPR0 REG32(STM32_ADC1_BASE + 0x5C) + +#define STM32_ADC_CCR REG32(STM32_ADC_BASE + 0x04) /* --- Comparators --- */ -#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) - -#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) -#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) -#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) -#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) -#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) -#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) +#define STM32_COMP_CSR REG32(STM32_COMP_BASE + 0x00) + +#define STM32_COMP_OUTSEL_TIM2_IC4 (0 << 21) +#define STM32_COMP_OUTSEL_TIM2_OCR (1 << 21) +#define STM32_COMP_OUTSEL_TIM3_IC4 (2 << 21) +#define STM32_COMP_OUTSEL_TIM3_OCR (3 << 21) +#define STM32_COMP_OUTSEL_TIM4_IC4 (4 << 21) +#define STM32_COMP_OUTSEL_TIM4_OCR (5 << 21) #define STM32_COMP_OUTSEL_TIM10_IC1 (6 << 21) -#define STM32_COMP_OUTSEL_NONE (7 << 21) - -#define STM32_COMP_INSEL_NONE (0 << 18) -#define STM32_COMP_INSEL_PB3 (1 << 18) -#define STM32_COMP_INSEL_VREF (2 << 18) -#define STM32_COMP_INSEL_VREF34 (3 << 18) -#define STM32_COMP_INSEL_VREF12 (4 << 18) -#define STM32_COMP_INSEL_VREF14 (5 << 18) -#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) -#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) - -#define STM32_COMP_WNDWE BIT(17) -#define STM32_COMP_VREFOUTEN BIT(16) -#define STM32_COMP_CMP2OUT BIT(13) -#define STM32_COMP_SPEED_FAST BIT(12) - -#define STM32_COMP_CMP1OUT BIT(7) -#define STM32_COMP_CMP1EN BIT(4) - -#define STM32_COMP_400KPD BIT(3) -#define STM32_COMP_10KPD BIT(2) -#define STM32_COMP_400KPU BIT(1) -#define STM32_COMP_10KPU BIT(0) - +#define STM32_COMP_OUTSEL_NONE (7 << 21) + +#define STM32_COMP_INSEL_NONE (0 << 18) +#define STM32_COMP_INSEL_PB3 (1 << 18) +#define STM32_COMP_INSEL_VREF (2 << 18) +#define STM32_COMP_INSEL_VREF34 (3 << 18) +#define STM32_COMP_INSEL_VREF12 (4 << 18) +#define STM32_COMP_INSEL_VREF14 (5 << 18) +#define STM32_COMP_INSEL_DAC_OUT1 (6 << 18) +#define STM32_COMP_INSEL_DAC_OUT2 (7 << 18) + +#define STM32_COMP_WNDWE BIT(17) +#define STM32_COMP_VREFOUTEN BIT(16) +#define STM32_COMP_CMP2OUT BIT(13) +#define STM32_COMP_SPEED_FAST BIT(12) + +#define STM32_COMP_CMP1OUT BIT(7) +#define STM32_COMP_CMP1EN BIT(4) + +#define STM32_COMP_400KPD BIT(3) +#define STM32_COMP_10KPD BIT(2) +#define STM32_COMP_400KPU BIT(1) +#define STM32_COMP_10KPU BIT(0) /* --- DMA --- */ @@ -642,11 +632,11 @@ enum dma_channel { /* Registers for a single channel of the DMA controller */ struct stm32_dma_chan { - uint32_t ccr; /* Control */ - uint32_t cndtr; /* Number of data to transfer */ - uint32_t cpar; /* Peripheral address */ - uint32_t cmar; /* Memory address */ - uint32_t reserved; + uint32_t ccr; /* Control */ + uint32_t cndtr; /* Number of data to transfer */ + uint32_t cpar; /* Peripheral address */ + uint32_t cmar; /* Memory address */ + uint32_t reserved; }; /* Always use stm32_dma_chan_t so volatile keyword is included! */ @@ -657,8 +647,8 @@ typedef stm32_dma_chan_t dma_chan_t; /* Registers for the DMA controller */ struct stm32_dma_regs { - uint32_t isr; - uint32_t ifcr; + uint32_t isr; + uint32_t ifcr; stm32_dma_chan_t chan[STM32_DMAC_COUNT]; }; @@ -667,128 +657,124 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t; #define STM32_DMA1_REGS ((stm32_dma_regs_t *)STM32_DMA1_BASE) - -#define STM32_DMA_CCR_CHANNEL(channel) (0) +#define STM32_DMA_CCR_CHANNEL(channel) (0) #define STM32_DMA_REGS(channel) STM32_DMA1_REGS /* Bits for DMA controller regs (isr and ifcr) */ -#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) +#define STM32_DMA_CH_OFFSET(channel) (4 * ((channel) % STM32_DMAC_PER_CTLR)) #define STM32_DMA_ISR_MASK(channel, mask) \ ((mask) << STM32_DMA_CH_OFFSET(channel)) -#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) -#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) -#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) -#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) -#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) - -#define STM32_DMA_GIF BIT(0) -#define STM32_DMA_TCIF BIT(1) -#define STM32_DMA_HTIF BIT(2) -#define STM32_DMA_TEIF BIT(3) -#define STM32_DMA_ALL 0xf - -#define STM32_DMA_GET_ISR(channel) \ - ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_ISR(channel, val) \ - (STM32_DMA_REGS(channel)->isr = \ - ((STM32_DMA_REGS(channel)->isr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) -#define STM32_DMA_GET_IFCR(channel) \ - ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) \ - & STM32_DMA_ALL) -#define STM32_DMA_SET_IFCR(channel, val) \ - (STM32_DMA_REGS(channel)->ifcr = \ - ((STM32_DMA_REGS(channel)->ifcr & \ - ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ - (((val) & STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) - +#define STM32_DMA_ISR_GIF(channel) STM32_DMA_ISR_MASK(channel, BIT(0)) +#define STM32_DMA_ISR_TCIF(channel) STM32_DMA_ISR_MASK(channel, BIT(1)) +#define STM32_DMA_ISR_HTIF(channel) STM32_DMA_ISR_MASK(channel, BIT(2)) +#define STM32_DMA_ISR_TEIF(channel) STM32_DMA_ISR_MASK(channel, BIT(3)) +#define STM32_DMA_ISR_ALL(channel) STM32_DMA_ISR_MASK(channel, 0x0f) + +#define STM32_DMA_GIF BIT(0) +#define STM32_DMA_TCIF BIT(1) +#define STM32_DMA_HTIF BIT(2) +#define STM32_DMA_TEIF BIT(3) +#define STM32_DMA_ALL 0xf + +#define STM32_DMA_GET_ISR(channel) \ + ((STM32_DMA_REGS(channel)->isr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_ISR(channel, val) \ + (STM32_DMA_REGS(channel)->isr = \ + ((STM32_DMA_REGS(channel)->isr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) +#define STM32_DMA_GET_IFCR(channel) \ + ((STM32_DMA_REGS(channel)->ifcr >> STM32_DMA_CH_OFFSET(channel)) & \ + STM32_DMA_ALL) +#define STM32_DMA_SET_IFCR(channel, val) \ + (STM32_DMA_REGS(channel)->ifcr = \ + ((STM32_DMA_REGS(channel)->ifcr & \ + ~(STM32_DMA_ALL << STM32_DMA_CH_OFFSET(channel))) | \ + (((val)&STM32_DMA_ALL) << STM32_DMA_CH_OFFSET(channel)))) /* Bits for DMA channel regs */ -#define STM32_DMA_CCR_EN BIT(0) -#define STM32_DMA_CCR_TCIE BIT(1) -#define STM32_DMA_CCR_HTIE BIT(2) -#define STM32_DMA_CCR_TEIE BIT(3) -#define STM32_DMA_CCR_DIR BIT(4) -#define STM32_DMA_CCR_CIRC BIT(5) -#define STM32_DMA_CCR_PINC BIT(6) -#define STM32_DMA_CCR_MINC BIT(7) -#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) -#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) -#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) -#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) -#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) -#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) -#define STM32_DMA_CCR_PL_LOW (0 << 12) -#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) -#define STM32_DMA_CCR_PL_HIGH (2 << 12) -#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) -#define STM32_DMA_CCR_MEM2MEM BIT(14) - +#define STM32_DMA_CCR_EN BIT(0) +#define STM32_DMA_CCR_TCIE BIT(1) +#define STM32_DMA_CCR_HTIE BIT(2) +#define STM32_DMA_CCR_TEIE BIT(3) +#define STM32_DMA_CCR_DIR BIT(4) +#define STM32_DMA_CCR_CIRC BIT(5) +#define STM32_DMA_CCR_PINC BIT(6) +#define STM32_DMA_CCR_MINC BIT(7) +#define STM32_DMA_CCR_PSIZE_8_BIT (0 << 8) +#define STM32_DMA_CCR_PSIZE_16_BIT (1 << 8) +#define STM32_DMA_CCR_PSIZE_32_BIT (2 << 8) +#define STM32_DMA_CCR_MSIZE_8_BIT (0 << 10) +#define STM32_DMA_CCR_MSIZE_16_BIT (1 << 10) +#define STM32_DMA_CCR_MSIZE_32_BIT (2 << 10) +#define STM32_DMA_CCR_PL_LOW (0 << 12) +#define STM32_DMA_CCR_PL_MEDIUM (1 << 12) +#define STM32_DMA_CCR_PL_HIGH (2 << 12) +#define STM32_DMA_CCR_PL_VERY_HIGH (3 << 12) +#define STM32_DMA_CCR_MEM2MEM BIT(14) /* --- CRC --- */ -#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) -#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) - -#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) -#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) -#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) -#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) - -#define STM32_CRC_CR_RESET BIT(0) -#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) -#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) -#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) -#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) -#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) -#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) -#define STM32_CRC_CR_REV_IN_WORD (3 << 5) -#define STM32_CRC_CR_REV_OUT BIT(7) +#define STM32_CRC_DR REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR32 REG32(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR16 REG16(STM32_CRC_BASE + 0x0) +#define STM32_CRC_DR8 REG8(STM32_CRC_BASE + 0x0) + +#define STM32_CRC_IDR REG32(STM32_CRC_BASE + 0x4) +#define STM32_CRC_CR REG32(STM32_CRC_BASE + 0x8) +#define STM32_CRC_INIT REG32(STM32_CRC_BASE + 0x10) +#define STM32_CRC_POL REG32(STM32_CRC_BASE + 0x14) + +#define STM32_CRC_CR_RESET BIT(0) +#define STM32_CRC_CR_POLYSIZE_32 (0 << 3) +#define STM32_CRC_CR_POLYSIZE_16 (1 << 3) +#define STM32_CRC_CR_POLYSIZE_8 (2 << 3) +#define STM32_CRC_CR_POLYSIZE_7 (3 << 3) +#define STM32_CRC_CR_REV_IN_BYTE (1 << 5) +#define STM32_CRC_CR_REV_IN_HWORD (2 << 5) +#define STM32_CRC_CR_REV_IN_WORD (3 << 5) +#define STM32_CRC_CR_REV_OUT BIT(7) /* --- PMSE --- */ -#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) -#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) -#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) -#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) -#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) -#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) -#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) -#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x) * 4) -#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) -#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) -#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) -#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) -#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) -#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) -#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) -#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) -#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) -#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) -#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) +#define STM32_PMSE_ARCR REG32(STM32_PMSE_BASE + 0x0) +#define STM32_PMSE_ACCR REG32(STM32_PMSE_BASE + 0x4) +#define STM32_PMSE_CR REG32(STM32_PMSE_BASE + 0x8) +#define STM32_PMSE_CRTDR REG32(STM32_PMSE_BASE + 0x14) +#define STM32_PMSE_IER REG32(STM32_PMSE_BASE + 0x18) +#define STM32_PMSE_SR REG32(STM32_PMSE_BASE + 0x1c) +#define STM32_PMSE_IFCR REG32(STM32_PMSE_BASE + 0x20) +#define STM32_PMSE_PxPMR(x) REG32(STM32_PMSE_BASE + 0x2c + (x)*4) +#define STM32_PMSE_PAPMR REG32(STM32_PMSE_BASE + 0x2c) +#define STM32_PMSE_PBPMR REG32(STM32_PMSE_BASE + 0x30) +#define STM32_PMSE_PCPMR REG32(STM32_PMSE_BASE + 0x34) +#define STM32_PMSE_PDPMR REG32(STM32_PMSE_BASE + 0x38) +#define STM32_PMSE_PEPMR REG32(STM32_PMSE_BASE + 0x3c) +#define STM32_PMSE_PFPMR REG32(STM32_PMSE_BASE + 0x40) +#define STM32_PMSE_PGPMR REG32(STM32_PMSE_BASE + 0x44) +#define STM32_PMSE_PHPMR REG32(STM32_PMSE_BASE + 0x48) +#define STM32_PMSE_PIPMR REG32(STM32_PMSE_BASE + 0x4c) +#define STM32_PMSE_MRCR REG32(STM32_PMSE_BASE + 0x100) +#define STM32_PMSE_MCCR REG32(STM32_PMSE_BASE + 0x104) /* --- TRNG --- */ -#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) -#define STM32_RNG_CR_RNGEN BIT(2) -#define STM32_RNG_CR_IE BIT(3) -#define STM32_RNG_CR_CED BIT(5) -#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) -#define STM32_RNG_SR_DRDY BIT(0) -#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) +#define STM32_RNG_CR REG32(STM32_RNG_BASE + 0x0) +#define STM32_RNG_CR_RNGEN BIT(2) +#define STM32_RNG_CR_IE BIT(3) +#define STM32_RNG_CR_CED BIT(5) +#define STM32_RNG_SR REG32(STM32_RNG_BASE + 0x4) +#define STM32_RNG_SR_DRDY BIT(0) +#define STM32_RNG_DR REG32(STM32_RNG_BASE + 0x8) /* --- AXI interconnect --- */ /* STM32H7: AXI_TARGx_FN_MOD exists for masters x = 1, 2 and 7 */ -#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + \ - 0x1000 * (x)) -#define WRITE_ISS_OVERRIDE BIT(1) -#define READ_ISS_OVERRIDE BIT(0) +#define STM32_AXI_TARG_FN_MOD(x) REG32(STM32_GPV_BASE + 0x1108 + 0x1000 * (x)) +#define WRITE_ISS_OVERRIDE BIT(1) +#define READ_ISS_OVERRIDE BIT(0) /* --- MISC --- */ -#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) -#define STM32_UNIQUE_ID_LENGTH (3 * 4) +#define STM32_UNIQUE_ID_ADDRESS REG32_ADDR(STM32_UNIQUE_ID_BASE) +#define STM32_UNIQUE_ID_LENGTH (3 * 4) #endif /* !__ASSEMBLER__ */ -- cgit v1.2.1 From 0c40e309a77b9041a8415da4c4a18a2ebe5f3003 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:44:11 -0600 Subject: common/usbc/usb_pd_timer.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: Ic49d027ee6bcf2ab1d52215af4146beeee284081 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729788 Reviewed-by: Jeremy Bettis --- common/usbc/usb_pd_timer.c | 126 ++++++++++++++++++++++----------------------- 1 file changed, 62 insertions(+), 64 deletions(-) diff --git a/common/usbc/usb_pd_timer.c b/common/usbc/usb_pd_timer.c index a1859ac9e9..3522bc04bc 100644 --- a/common/usbc/usb_pd_timer.c +++ b/common/usbc/usb_pd_timer.c @@ -14,36 +14,35 @@ #include "usb_pd_timer.h" #include "usb_tc_sm.h" -#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT -#define MAX_PD_TIMERS PD_TIMER_COUNT +#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT +#define MAX_PD_TIMERS PD_TIMER_COUNT #define PD_TIMERS_ALL_MASK (UINT64_MAX >> (64 - PD_TIMER_COUNT)) -#define MAX_EXPIRE (0x7FFFFFFF) -#define NO_TIMEOUT (-1) -#define EXPIRE_NOW (0) +#define MAX_EXPIRE (0x7FFFFFFF) +#define NO_TIMEOUT (-1) +#define EXPIRE_NOW (0) #define PD_SET_ACTIVE(p, bit) \ - atomic_set_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_ACTIVE(p, bit) \ - atomic_clear_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_ACTIVE(p, bit) \ - atomic_test_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_SET_DISABLED(p, bit) \ - atomic_set_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_DISABLED(p, bit) \ - atomic_clear_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_DISABLED(p, bit) \ - atomic_test_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) -test_mockable_static -ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT * MAX_PD_PORTS); -test_mockable_static -ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT * MAX_PD_PORTS); +test_mockable_static ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS); +test_mockable_static ATOMIC_DEFINE(timer_disabled, + PD_TIMER_COUNT *MAX_PD_PORTS); static uint64_t timer_expires[MAX_PD_PORTS][PD_TIMER_COUNT]; /* @@ -52,42 +51,42 @@ static uint64_t timer_expires[MAX_PD_PORTS][PD_TIMER_COUNT]; static int count[MAX_PD_PORTS]; static int max_count[MAX_PD_PORTS]; -__maybe_unused static __const_data const char * const pd_timer_names[] = { - [PE_TIMER_BIST_CONT_MODE] = "PE-BIST_CONT_MODE", +__maybe_unused static __const_data const char *const pd_timer_names[] = { + [PE_TIMER_BIST_CONT_MODE] = "PE-BIST_CONT_MODE", [PE_TIMER_CHUNKING_NOT_SUPPORTED] = "PE-CHUNKING_NOT_SUPPORTED", - [PE_TIMER_DISCOVER_IDENTITY] = "PE-DISCOVER_IDENTITY", - [PE_TIMER_NO_RESPONSE] = "PE-NO_RESPONSE", - [PE_TIMER_PR_SWAP_WAIT] = "PE-PR_SWAP_WAIT", - [PE_TIMER_PS_HARD_RESET] = "PE-PS_HARD_RESET", - [PE_TIMER_PS_SOURCE] = "PE-PS_SOURCE", - [PE_TIMER_PS_TRANSITION] = "PE-PS_TRANSITION", - [PE_TIMER_SENDER_RESPONSE] = "PE-SENDER_RESPONSE", - [PE_TIMER_SINK_REQUEST] = "PE-SINK_REQUEST", - [PE_TIMER_SOURCE_CAP] = "PE-SOURCE_CAP", - [PE_TIMER_SRC_TRANSITION] = "PE-SRC_TRANSITION", - [PE_TIMER_SWAP_SOURCE_START] = "PE-SWAP_SOURCE_START", - [PE_TIMER_TIMEOUT] = "PE-TIMEOUT", - [PE_TIMER_VCONN_ON] = "PE-VCONN_ON", - [PE_TIMER_VDM_RESPONSE] = "PE-VDM_RESPONSE", - [PE_TIMER_WAIT_AND_ADD_JITTER] = "PE-WAIT_AND_ADD_JITTER", - [PE_TIMER_VCONN_DISCHARGE] = "PE-VCONN_DISCHARGE", - [PE_TIMER_VCONN_REAPPLIED] = "PE-VCONN_REAPPLIED", - [PE_TIMER_DATA_RESET_FAIL] = "PE-DATA_RESET_FAIL", - - [PR_TIMER_CHUNK_SENDER_REQUEST] = "PR-CHUNK_SENDER_REQUEST", + [PE_TIMER_DISCOVER_IDENTITY] = "PE-DISCOVER_IDENTITY", + [PE_TIMER_NO_RESPONSE] = "PE-NO_RESPONSE", + [PE_TIMER_PR_SWAP_WAIT] = "PE-PR_SWAP_WAIT", + [PE_TIMER_PS_HARD_RESET] = "PE-PS_HARD_RESET", + [PE_TIMER_PS_SOURCE] = "PE-PS_SOURCE", + [PE_TIMER_PS_TRANSITION] = "PE-PS_TRANSITION", + [PE_TIMER_SENDER_RESPONSE] = "PE-SENDER_RESPONSE", + [PE_TIMER_SINK_REQUEST] = "PE-SINK_REQUEST", + [PE_TIMER_SOURCE_CAP] = "PE-SOURCE_CAP", + [PE_TIMER_SRC_TRANSITION] = "PE-SRC_TRANSITION", + [PE_TIMER_SWAP_SOURCE_START] = "PE-SWAP_SOURCE_START", + [PE_TIMER_TIMEOUT] = "PE-TIMEOUT", + [PE_TIMER_VCONN_ON] = "PE-VCONN_ON", + [PE_TIMER_VDM_RESPONSE] = "PE-VDM_RESPONSE", + [PE_TIMER_WAIT_AND_ADD_JITTER] = "PE-WAIT_AND_ADD_JITTER", + [PE_TIMER_VCONN_DISCHARGE] = "PE-VCONN_DISCHARGE", + [PE_TIMER_VCONN_REAPPLIED] = "PE-VCONN_REAPPLIED", + [PE_TIMER_DATA_RESET_FAIL] = "PE-DATA_RESET_FAIL", + + [PR_TIMER_CHUNK_SENDER_REQUEST] = "PR-CHUNK_SENDER_REQUEST", [PR_TIMER_CHUNK_SENDER_RESPONSE] = "PR-CHUNK_SENDER_RESPONSE", - [PR_TIMER_HARD_RESET_COMPLETE] = "PR-HARD_RESET_COMPLETE", - [PR_TIMER_SINK_TX] = "PR-SINK_TX", - [PR_TIMER_TCPC_TX_TIMEOUT] = "PR-TCPC_TX_TIMEOUT", - - [TC_TIMER_CC_DEBOUNCE] = "TC-CC_DEBOUNCE", - [TC_TIMER_LOW_POWER_EXIT_TIME] = "TC-LOW_POWER_EXIT_TIME", - [TC_TIMER_LOW_POWER_TIME] = "TC-LOW_POWER_TIME", - [TC_TIMER_NEXT_ROLE_SWAP] = "TC-NEXT_ROLE_SWAP", - [TC_TIMER_PD_DEBOUNCE] = "TC-PD_DEBOUNCE", - [TC_TIMER_TIMEOUT] = "TC-TIMEOUT", - [TC_TIMER_TRY_WAIT_DEBOUNCE] = "TC-TRY_WAIT_DEBOUNCE", - [TC_TIMER_VBUS_DEBOUNCE] = "TC-VBUS_DEBOUNCE", + [PR_TIMER_HARD_RESET_COMPLETE] = "PR-HARD_RESET_COMPLETE", + [PR_TIMER_SINK_TX] = "PR-SINK_TX", + [PR_TIMER_TCPC_TX_TIMEOUT] = "PR-TCPC_TX_TIMEOUT", + + [TC_TIMER_CC_DEBOUNCE] = "TC-CC_DEBOUNCE", + [TC_TIMER_LOW_POWER_EXIT_TIME] = "TC-LOW_POWER_EXIT_TIME", + [TC_TIMER_LOW_POWER_TIME] = "TC-LOW_POWER_TIME", + [TC_TIMER_NEXT_ROLE_SWAP] = "TC-NEXT_ROLE_SWAP", + [TC_TIMER_PD_DEBOUNCE] = "TC-PD_DEBOUNCE", + [TC_TIMER_TIMEOUT] = "TC-TIMEOUT", + [TC_TIMER_TRY_WAIT_DEBOUNCE] = "TC-TRY_WAIT_DEBOUNCE", + [TC_TIMER_VBUS_DEBOUNCE] = "TC-VBUS_DEBOUNCE", }; /***************************************************************************** @@ -172,16 +171,16 @@ void pd_timer_disable_range(int port, enum pd_timer_range range) switch (range) { case PE_TIMER_RANGE: - start = PE_TIMER_START; - end = PE_TIMER_END; + start = PE_TIMER_START; + end = PE_TIMER_END; break; case PR_TIMER_RANGE: - start = PR_TIMER_START; - end = PR_TIMER_END; + start = PR_TIMER_START; + end = PR_TIMER_END; break; case TC_TIMER_RANGE: - start = TC_TIMER_START; - end = TC_TIMER_END; + start = TC_TIMER_START; + end = TC_TIMER_END; break; default: return; @@ -253,8 +252,8 @@ test_mockable_static void pd_timer_dump(int port) int timer; uint64_t now = get_time().val; - ccprints("Timers(%d): cur=%d max=%d", - port, count[port], max_count[port]); + ccprints("Timers(%d): cur=%d max=%d", port, count[port], + max_count[port]); for (timer = 0; timer < PD_TIMER_COUNT; ++timer) { if (pd_timer_is_disabled(port, timer)) { @@ -265,14 +264,13 @@ test_mockable_static void pd_timer_dump(int port) if (now < timer_expires[port][timer]) delta = timer_expires[port][timer] - now; - ccprints("[%2d] Active: %s (%d%s)", - timer, pd_timer_names[timer], (uint32_t)delta, - tc_event_loop_is_paused(port) - ? "-PAUSED" - : ""); + ccprints("[%2d] Active: %s (%d%s)", timer, + pd_timer_names[timer], (uint32_t)delta, + tc_event_loop_is_paused(port) ? "-PAUSED" : + ""); } else { - ccprints("[%2d] Inactive: %s", - timer, pd_timer_names[timer]); + ccprints("[%2d] Inactive: %s", timer, + pd_timer_names[timer]); } } } -- cgit v1.2.1 From 66c01d8932b262fd3ceec80a1320d793668baae9 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:14 -0600 Subject: include/usb_pd_timer.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I7d4ef8e73349c70bde48f0af285a2812d8f36dba Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730445 Reviewed-by: Jeremy Bettis --- include/usb_pd_timer.h | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h index 3a3f388b22..b4f8946780 100644 --- a/include/usb_pd_timer.h +++ b/include/usb_pd_timer.h @@ -167,7 +167,6 @@ enum pd_task_timer { */ PE_TIMER_WAIT_AND_ADD_JITTER, - /* Chunk Sender Response timer */ PR_TIMER_CHUNK_SENDER_RESPONSE, @@ -183,7 +182,6 @@ enum pd_task_timer { /* timeout to limit waiting on TCPC response (not in spec) */ PR_TIMER_TCPC_TX_TIMEOUT, - /* Time a port shall wait before it can determine it is attached */ TC_TIMER_CC_DEBOUNCE, @@ -226,14 +224,14 @@ enum pd_timer_range { PR_TIMER_RANGE, TC_TIMER_RANGE, }; -#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE -#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER +#define PE_TIMER_START PE_TIMER_BIST_CONT_MODE +#define PE_TIMER_END PE_TIMER_WAIT_AND_ADD_JITTER -#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE -#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT +#define PR_TIMER_START PR_TIMER_CHUNK_SENDER_RESPONSE +#define PR_TIMER_END PR_TIMER_TCPC_TX_TIMEOUT -#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE -#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE +#define TC_TIMER_START TC_TIMER_CC_DEBOUNCE +#define TC_TIMER_END TC_TIMER_VBUS_DEBOUNCE /* * pd_timer_init @@ -311,7 +309,6 @@ void pd_timer_manage_expired(int port); */ int pd_timer_next_expiration(int port); - /* * pd_timer_dump * Debug display of the timers for a given port @@ -333,30 +330,30 @@ void pd_timer_dump(int port); */ /* exported: number of USB-C ports */ -#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT +#define MAX_PD_PORTS CONFIG_USB_PD_PORT_MAX_COUNT /* PD timers have three possible states: Active, Inactive and Disabled */ /* exported: timer_active indicates if a timer is currently active */ -extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT * MAX_PD_PORTS); +extern ATOMIC_DEFINE(timer_active, PD_TIMER_COUNT *MAX_PD_PORTS); /* exported: timer_disabled indicates if a timer is currently disabled */ -extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT * MAX_PD_PORTS); +extern ATOMIC_DEFINE(timer_disabled, PD_TIMER_COUNT *MAX_PD_PORTS); /* exported: set/clear/check the current timer_active for a timer */ #define PD_SET_ACTIVE(p, bit) \ - atomic_set_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_ACTIVE(p, bit) \ - atomic_clear_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_ACTIVE(p, bit) \ - atomic_test_bit(timer_active, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_active, (p)*PD_TIMER_COUNT + (bit)) /* exported: set/clear/check the current timer_disabled for a timer */ #define PD_SET_DISABLED(p, bit) \ - atomic_set_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_set_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CLR_DISABLED(p, bit) \ - atomic_clear_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_clear_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #define PD_CHK_DISABLED(p, bit) \ - atomic_test_bit(timer_disabled, (p) * PD_TIMER_COUNT + (bit)) + atomic_test_bit(timer_disabled, (p)*PD_TIMER_COUNT + (bit)) #endif /* TEST_BUILD */ -#endif /* __CROS_EC_USB_PD_TIMER_H */ +#endif /* __CROS_EC_USB_PD_TIMER_H */ -- cgit v1.2.1 From 96813e7de867f8a0bb755c17fd3be02ec5bc3f6c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:45:50 -0600 Subject: zephyr/include/drivers/cros_flash.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I69345692daf01e56e98cb2e57d3420aee62ec574 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730711 Reviewed-by: Jeremy Bettis --- zephyr/include/drivers/cros_flash.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/zephyr/include/drivers/cros_flash.h b/zephyr/include/drivers/cros_flash.h index 1bad6bb682..caef62528d 100644 --- a/zephyr/include/drivers/cros_flash.h +++ b/zephyr/include/drivers/cros_flash.h @@ -45,8 +45,8 @@ typedef int (*cros_flash_api_physical_erase)(const struct device *dev, typedef int (*cros_flash_api_physical_get_protect)(const struct device *dev, int bank); -typedef uint32_t -(*cros_flash_api_physical_get_protect_flags)(const struct device *dev); +typedef uint32_t (*cros_flash_api_physical_get_protect_flags)( + const struct device *dev); typedef int (*cros_flash_api_physical_protect_at_boot)(const struct device *dev, uint32_t new_flags); @@ -55,12 +55,11 @@ typedef int (*cros_flash_api_physical_protect_now)(const struct device *dev, int all); typedef int (*cros_flash_api_physical_get_jedec_id)(const struct device *dev, - uint8_t *manufacturer, - uint16_t *device); + uint8_t *manufacturer, + uint16_t *device); typedef int (*cros_flash_api_physical_get_status)(const struct device *dev, - uint8_t *sr1, - uint8_t *sr2); + uint8_t *sr1, uint8_t *sr2); __subsystem struct cros_flash_driver_api { cros_flash_api_init init; @@ -183,6 +182,7 @@ z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank) return api->physical_get_protect(dev, bank); } +/* clang-format off */ /** * @brief Return flash protect state flags from the physical layer. * @@ -192,6 +192,7 @@ z_impl_cros_flash_physical_get_protect(const struct device *dev, int bank) */ __syscall uint32_t cros_flash_physical_get_protect_flags(const struct device *dev); +/* clang-format on */ static inline uint32_t z_impl_cros_flash_physical_get_protect_flags(const struct device *dev) @@ -269,13 +270,12 @@ z_impl_cros_flash_physical_protect_now(const struct device *dev, int all) * @retval -ENOTSUP Not supported api function. */ __syscall int cros_flash_physical_get_jedec_id(const struct device *dev, - uint8_t *manufacturer, - uint16_t *device); + uint8_t *manufacturer, + uint16_t *device); static inline int z_impl_cros_flash_physical_get_jedec_id(const struct device *dev, - uint8_t *manufacturer, - uint16_t *device) + uint8_t *manufacturer, uint16_t *device) { const struct cros_flash_driver_api *api = (const struct cros_flash_driver_api *)dev->api; @@ -297,11 +297,11 @@ z_impl_cros_flash_physical_get_jedec_id(const struct device *dev, * @retval -ENOTSUP Not supported api function. */ __syscall int cros_flash_physical_get_status(const struct device *dev, - uint8_t *sr1, uint8_t *sr2); + uint8_t *sr1, uint8_t *sr2); static inline int -z_impl_cros_flash_physical_get_status(const struct device *dev, - uint8_t *sr1, uint8_t *sr2) +z_impl_cros_flash_physical_get_status(const struct device *dev, uint8_t *sr1, + uint8_t *sr2) { const struct cros_flash_driver_api *api = (const struct cros_flash_driver_api *)dev->api; -- cgit v1.2.1 From 075079e03f909bd366a64301ea07c7d9d5844d7b Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Thu, 7 Jul 2022 15:21:30 -0600 Subject: clang-format: Enable enforcement during pre-upload Enable the clang_format_check hook for pre-upload. BUG=b:236386294 BRANCH=none TEST=Run ~/chromiumos/src/repohooks/pre-upload.py on recent commits Only legitimate formatting errors are caught. Signed-off-by: Jack Rosenthal Change-Id: Id00fd8a7acce4105cb8f4a445067393616df5ae4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751770 Reviewed-by: Jeremy Bettis Commit-Queue: Jeremy Bettis --- PRESUBMIT.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg index eac83bb0c5..531a74fad9 100644 --- a/PRESUBMIT.cfg +++ b/PRESUBMIT.cfg @@ -1,4 +1,5 @@ [Hook Overrides] +clang_format_check: true branch_check: true checkpatch_check: true kerneldoc_check: true -- cgit v1.2.1 From 5cfa5b9e0bcafd19eb8109db95b23a2082d611b5 Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Thu, 7 Jul 2022 20:14:53 +0000 Subject: docs: Add note about removing history to reduce EC image size src/platform/ec/docs/reducing_ec_image_size.md includes a small section stating that the help command can be removed from the EC console free up flash space in the EC. Similarly, the history command can be removed. This CL updates the reducing_ec_image_size.md doc to note that both help and history can be removed to save EC space. BRANCH=None BUG=None TEST=None Signed-off-by: Jameson Thies Change-Id: Iee566ea574c85607eca8a481fec6d2ffdd332405 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750112 Reviewed-by: Abe Levkoy --- docs/reducing_ec_image_size.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/reducing_ec_image_size.md b/docs/reducing_ec_image_size.md index 5e09c99e51..fc5d0c1500 100644 --- a/docs/reducing_ec_image_size.md +++ b/docs/reducing_ec_image_size.md @@ -347,13 +347,14 @@ Disable all debug from ASSERT() calls.
EC is reset using a software breakpoi It is not recommended to disable `CONFIG_PLATFORM_EC_DEBUG_ASSERT_REBOOTS` on shipping firmware. -### Disable console help +### Disable console help and history The help strings can be removed from the final build, saving about 5000 bytes of -flash space. +flash space. The history command can also be disabled to save another 200 bytes +of flash space. -For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` to the -board.h/baseboard.h file. +For cros-ec builds, add `#undef CONFIG_CONSOLE_CMDHELP` and `#undef +CONFIG_CONSOLE_HISTORY` to the board.h/baseboard.h file. zephyr-ec builds use Zephyr's shell subsystem and by default enable the `CONFIG_SHELL_MINIMAL` option. This option already disables shell help along -- cgit v1.2.1 From a2abb573b512400ff6f2f93e2af2851aa1dd3281 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Thu, 7 Jul 2022 12:45:51 +1000 Subject: sm5803: slow clocks last when enabling LPM Silicon Mitus say that slowing clocks before disabling GPADCs can cause spurious readings, which may cause unexpected behavior. We don't currently disable GPADCs, but in the same spirit change the order of operations to slow the clocks last when going into low-power mode. BUG=b:168591511,b:237697900 TEST=sinking and sourcing still work on Nereid and ports enter runtime LPM as expected. BRANCH=none Signed-off-by: Peter Marheine Change-Id: Ideac273cf39b6d1b13cc8336701774595e49df41 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750542 Reviewed-by: Andrew McRae --- driver/charger/sm5803.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/driver/charger/sm5803.c b/driver/charger/sm5803.c index d90294b8c9..c5684f2732 100644 --- a/driver/charger/sm5803.c +++ b/driver/charger/sm5803.c @@ -942,10 +942,6 @@ static void sm5803_enable_runtime_low_power_mode(void) chgnum); return; } - /* Slow the clock speed */ - rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, ®); - reg |= SM5803_CLOCK_SEL_LOW; - rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg); /* Disable ADC sigma delta */ rv |= chg_read8(chgnum, SM5803_REG_CC_CONFIG1, ®); @@ -960,6 +956,11 @@ static void sm5803_enable_runtime_low_power_mode(void) rv |= chg_write8(chgnum, SM5803_REG_PHOT1, reg); } + /* Slow the clock speed */ + rv |= main_read8(chgnum, SM5803_REG_CLOCK_SEL, ®); + reg |= SM5803_CLOCK_SEL_LOW; + rv |= main_write8(chgnum, SM5803_REG_CLOCK_SEL, reg); + if (rv) CPRINTS("%s %d: Failed to set in enable runtime LPM", CHARGER_NAME, chgnum); -- cgit v1.2.1 From f3ee256dc0ca5b8c74b7dacad18c20e22fe180b4 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 7 Jul 2022 14:25:39 +0800 Subject: tcpc: add comma separator in tcpc shim for a better format Move the comma from header to the dts binding. BUG=none TEST=zmake --goma testall --clobber BRANCH=none Change-Id: Ic5ee1a8b83bc9690354546402cc74f097176fe36 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750550 Auto-Submit: Eric Yilun Lin Reviewed-by: Ting Shen Reviewed-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/shim/include/usbc/tcpc_ccgxxf.h | 2 +- zephyr/shim/include/usbc/tcpc_fusb302.h | 2 +- zephyr/shim/include/usbc/tcpc_it8xxx2.h | 2 +- zephyr/shim/include/usbc/tcpc_nct38xx.h | 2 +- zephyr/shim/include/usbc/tcpc_ps8xxx.h | 2 +- zephyr/shim/include/usbc/tcpci.h | 2 +- zephyr/shim/src/tcpc.c | 33 +++++++++++++-------------------- 7 files changed, 19 insertions(+), 26 deletions(-) diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h index 0825007100..3671aa96f1 100644 --- a/zephyr/shim/include/usbc/tcpc_ccgxxf.h +++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h @@ -18,4 +18,4 @@ }, \ .drv = &ccgxxf_tcpm_drv, \ .flags = TCPC_FLAGS_TCPCI_REV2_0, \ - }, + } diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h index 74532767d0..39ff776803 100644 --- a/zephyr/shim/include/usbc/tcpc_fusb302.h +++ b/zephyr/shim/include/usbc/tcpc_fusb302.h @@ -17,4 +17,4 @@ id, i2c_addr_flags), \ }, \ .drv = &fusb302_tcpm_drv, \ - }, + } diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h index f8f77a6d18..82893c2978 100644 --- a/zephyr/shim/include/usbc/tcpc_it8xxx2.h +++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h @@ -13,4 +13,4 @@ .bus_type = EC_BUS_TYPE_EMBEDDED, \ .drv = &it8xxx2_tcpm_drv, \ .flags = 0, \ - }, + } diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h index cf71122589..dd3716f085 100644 --- a/zephyr/shim/include/usbc/tcpc_nct38xx.h +++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h @@ -21,7 +21,7 @@ }, \ .drv = &nct38xx_tcpm_drv, \ .flags = DT_PROP(id, tcpc_flags), \ - }, + } /** * @brief Get the NCT38XX GPIO device from the TCPC port enumeration diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h index 379b041e8e..bfe20eb6a5 100644 --- a/zephyr/shim/include/usbc/tcpc_ps8xxx.h +++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h @@ -18,4 +18,4 @@ }, \ .drv = &ps8xxx_tcpm_drv, \ .flags = DT_PROP(id, tcpc_flags), \ - }, + } diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h index f65b6b7717..1247eb8d01 100644 --- a/zephyr/shim/include/usbc/tcpci.h +++ b/zephyr/shim/include/usbc/tcpci.h @@ -17,4 +17,4 @@ .addr_flags = DT_PROP(id, i2c_addr_flags), \ }, \ .drv = &tcpci_tcpm_drv, \ - }, + } diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index aef3a05b3c..a3598cafc4 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -27,25 +27,18 @@ #define MAYBE_CONST \ COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const)) -MAYBE_CONST struct tcpc_config_t tcpc_config[] = { - DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_CCGXXF) - DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_FUSB302) - DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_IT8XXX2) - DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_PS8XXX) - DT_FOREACH_STATUS_OKAY_VARGS( - NCT38XX_TCPC_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_NCT38XX) - DT_FOREACH_STATUS_OKAY_VARGS( - TCPCI_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_TCPCI) -}; +#define MAYBE_EMPTY(compat, config) \ + COND_CODE_1( \ + DT_HAS_STATUS_OKAY(compat), \ + (DT_FOREACH_STATUS_OKAY_VARGS(compat, TCPC_CONFIG, config)), \ + (EMPTY)) + +MAYBE_CONST struct tcpc_config_t tcpc_config[] = { LIST_DROP_EMPTY( + MAYBE_EMPTY(CCGXXF_TCPC_COMPAT, TCPC_CONFIG_CCGXXF), + MAYBE_EMPTY(FUSB302_TCPC_COMPAT, TCPC_CONFIG_FUSB302), + MAYBE_EMPTY(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG_IT8XXX2), + MAYBE_EMPTY(PS8XXX_COMPAT, TCPC_CONFIG_PS8XXX), + MAYBE_EMPTY(NCT38XX_TCPC_COMPAT, TCPC_CONFIG_NCT38XX), + MAYBE_EMPTY(TCPCI_COMPAT, TCPC_CONFIG_TCPCI)) }; #endif /* DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 59ddcfc2cf71e0c0f72ce5db583f5536d1aa73c0 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 7 Jul 2022 14:32:23 +0800 Subject: bc12: add comma separator in bc12 shim for a better format Move the comma from header to the dts binding. BUG=none TEST=zmake --goma testall --clobber BRANCH=none Signed-off-by: Eric Yilun Lin Change-Id: If7cd0d3947cc73c9b2ef8ad378d58fce5e8fe833 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750554 Commit-Queue: Eric Yilun Lin Reviewed-by: Jeremy Bettis Auto-Submit: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/shim/include/usbc/bc12_pi3usb9201.h | 2 +- zephyr/shim/include/usbc/bc12_rt1739.h | 2 +- zephyr/shim/include/usbc/bc12_rt9490.h | 2 +- zephyr/shim/src/bc12.c | 18 +++++++++--------- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/zephyr/shim/include/usbc/bc12_pi3usb9201.h b/zephyr/shim/include/usbc/bc12_pi3usb9201.h index 85b1c00443..552fe828b1 100644 --- a/zephyr/shim/include/usbc/bc12_pi3usb9201.h +++ b/zephyr/shim/include/usbc/bc12_pi3usb9201.h @@ -10,4 +10,4 @@ #define BC12_CHIP_PI3USB9201(id) \ { \ .drv = &pi3usb9201_drv, \ - }, + } diff --git a/zephyr/shim/include/usbc/bc12_rt1739.h b/zephyr/shim/include/usbc/bc12_rt1739.h index 15df73857a..efe6d42412 100644 --- a/zephyr/shim/include/usbc/bc12_rt1739.h +++ b/zephyr/shim/include/usbc/bc12_rt1739.h @@ -10,4 +10,4 @@ #define BC12_CHIP_RT1739(id) \ { \ .drv = &rt1739_bc12_drv, \ - }, + } diff --git a/zephyr/shim/include/usbc/bc12_rt9490.h b/zephyr/shim/include/usbc/bc12_rt9490.h index fe57e42524..acdcdd562c 100644 --- a/zephyr/shim/include/usbc/bc12_rt9490.h +++ b/zephyr/shim/include/usbc/bc12_rt9490.h @@ -10,4 +10,4 @@ #define BC12_CHIP_RT9490(id) \ { \ .drv = &rt9490_bc12_drv, \ - }, + } diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c index 4f1fd2db01..19cabfc83e 100644 --- a/zephyr/shim/src/bc12.c +++ b/zephyr/shim/src/bc12.c @@ -16,15 +16,15 @@ #define BC12_CHIP(id, fn) [USBC_PORT(id)] = fn(id) +#define MAYBE_EMPTY(compat, config) \ + COND_CODE_1(DT_HAS_STATUS_OKAY(compat), \ + (DT_FOREACH_STATUS_OKAY_VARGS(compat, BC12_CHIP, config)), \ + (EMPTY)) + /* Power Path Controller */ -struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { - DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP, - BC12_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, - BC12_CHIP_RT9490) - DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, - BC12_CHIP, - BC12_CHIP_PI3USB9201) -}; +struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { LIST_DROP_EMPTY( + MAYBE_EMPTY(RT1739_BC12_COMPAT, BC12_CHIP_RT1739), + MAYBE_EMPTY(RT9490_BC12_COMPAT, BC12_CHIP_RT9490), + MAYBE_EMPTY(PI3USB9201_COMPAT, BC12_CHIP_PI3USB9201)) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 5ebc252cce3c6ab4e8ce69696162f93790c8f811 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Thu, 7 Jul 2022 16:02:43 +0800 Subject: ppc: add comma separator in ppc shim for a better format Move the comma from header to the dts binding. BUG=none TEST=zmake --goma testall --clobber BRANCH=none Change-Id: Ife8651cc58f43cdd9e6f6088fd860dec4d03237a Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750555 Commit-Queue: Eric Yilun Lin Auto-Submit: Eric Yilun Lin Tested-by: Eric Yilun Lin Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/ppc_rt1739.h | 2 +- zephyr/shim/include/usbc/ppc_sn5s330.h | 2 +- zephyr/shim/include/usbc/ppc_syv682x.h | 2 +- zephyr/shim/src/ppc.c | 29 +++++++++++++---------------- 4 files changed, 16 insertions(+), 19 deletions(-) diff --git a/zephyr/shim/include/usbc/ppc_rt1739.h b/zephyr/shim/include/usbc/ppc_rt1739.h index 19e169a436..f8788e505e 100644 --- a/zephyr/shim/include/usbc/ppc_rt1739.h +++ b/zephyr/shim/include/usbc/ppc_rt1739.h @@ -15,4 +15,4 @@ .frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, irq), \ (GPIO_SIGNAL(DT_PHANDLE(id, irq))), \ (0)), \ - }, + } diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h index 7ec9b434a8..cbf129cd99 100644 --- a/zephyr/shim/include/usbc/ppc_sn5s330.h +++ b/zephyr/shim/include/usbc/ppc_sn5s330.h @@ -10,4 +10,4 @@ #define PPC_CHIP_SN5S330(id) \ { .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ - .drv = &sn5s330_drv }, + .drv = &sn5s330_drv } diff --git a/zephyr/shim/include/usbc/ppc_syv682x.h b/zephyr/shim/include/usbc/ppc_syv682x.h index f177aebe8b..d45a9862f1 100644 --- a/zephyr/shim/include/usbc/ppc_syv682x.h +++ b/zephyr/shim/include/usbc/ppc_syv682x.h @@ -15,4 +15,4 @@ .frs_en = COND_CODE_1( \ DT_NODE_HAS_PROP(id, frs_en_gpio), \ (GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)), \ - }, + } diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c index 936367ca78..f301c50e09 100644 --- a/zephyr/shim/src/ppc.c +++ b/zephyr/shim/src/ppc.c @@ -26,25 +26,22 @@ #define PPC_CHIP_ELE_ALT(id, fn) [PPC_ID(id)] = fn(id) +#define MAYBE_EMPTY(compat, type, config) \ + COND_CODE_1(DT_HAS_STATUS_OKAY(compat), \ + (DT_FOREACH_STATUS_OKAY_VARGS(compat, type, config)), \ + (EMPTY)) + /* Power Path Controller */ -struct ppc_config_t ppc_chips[] = { - DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, - PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS( - SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X) -}; +struct ppc_config_t ppc_chips[] = { LIST_DROP_EMPTY( + MAYBE_EMPTY(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_RT1739), + MAYBE_EMPTY(SN5S330_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SN5S330), + MAYBE_EMPTY(SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X)) }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* Alt Power Path Controllers */ -struct ppc_config_t ppc_chips_alt[] = { - DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT, - PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS( - SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X) -}; +struct ppc_config_t ppc_chips_alt[] = { LIST_DROP_EMPTY( + MAYBE_EMPTY(RT1739_PPC_COMPAT, PPC_CHIP_ALT, PPC_CHIP_RT1739), + MAYBE_EMPTY(SN5S330_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SN5S330), + MAYBE_EMPTY(SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X)) }; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 6e3150f30fc5e79728899d080f631fb8c9253f4b Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 24 Jun 2022 15:50:06 +0800 Subject: bindings/usb_mux: forward declaration of board_init/board_set Forward declares usb_mux callback board_init and board_set to silent the compile error. BUG=b:227359727 TEST=define board_init/board_set function in dts and ensure it's called BRANCH=none Change-Id: I11ba4b56d1c3ffbaec20c2adb7f538b693169093 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721939 Reviewed-by: Keith Short Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- zephyr/shim/include/usbc/usb_muxes.h | 71 ++++++++++++++++++++++++++++++++++++ zephyr/shim/src/usb_muxes.c | 10 +++++ 2 files changed, 81 insertions(+) diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h index 1986114a2a..40c9ad53c8 100644 --- a/zephyr/shim/include/usbc/usb_muxes.h +++ b/zephyr/shim/include/usbc/usb_muxes.h @@ -74,6 +74,29 @@ #define USB_MUX_STRUCT_DECLARE(mux_id) \ MAYBE_CONST struct usb_mux USB_MUX_STRUCT_NAME(mux_id) +/** + * @brief Declaration of USB mux board_init function + * + * @param mux_id USB mux node ID + * @param port_id USBC node ID + * @param idx Position of USB mux in chain + * @param conf Driver configuration function + */ +#define USB_MUX_CB_BOARD_INIT_DECLARE(mux_id, port_id, idx, conf) \ + int DT_STRING_TOKEN(mux_id, board_init)(const struct usb_mux *); + +/** + * @brief Declaration of USB mux board_set function + * + * @param mux_id USB mux node ID + * @param port_id USBC node ID + * @param idx Position of USB mux in chain + * @param conf Driver configuration function + */ +#define USB_MUX_CB_BOARD_SET_DECLARE(mux_id, port_id, idx, conf) \ + int DT_STRING_TOKEN(mux_id, board_set)(const struct usb_mux *, \ + mux_state_t); + /** * @brief Get pointer by referencing @p name or NULL if @p name is EMPTY * @@ -266,6 +289,54 @@ DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, USB_MUX_DO_SKIP_FIRST, \ op) +/** + * @brief Call USB_MUX_DO if @p cb is not empty + * + * @param port_id USBC node ID + * @param mux_id USB mux node ID + * @param idx Position of USB mux in chain + * @param cb The callback name + * @param op Operation to perform on USB muxes + */ +#define USB_MUX_DO_SKIP_NO_CB(port_id, mux_id, idx, cb, op) \ + COND_CODE_0(IS_EMPTY(DT_STRING_TOKEN(mux_id, cb)), \ + (USB_MUX_DO(port_id, idx, op)), ()) + +/** + * @brief If usb_muxes property of @p port_id has callback property @p cb + * + * @param port_id USBC node ID + * @param cb The callback name + * @param op Operation to perform on USB muxes. Needs to accept USB mux node + * ID, USBC port node ID, position in chain, and driver config as + * arguments. + */ +#define USB_MUX_HAS_CB(port_id, cb, op) \ + DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, \ + USB_MUX_DO_SKIP_NO_CB, cb, op) + +/** + * @brief If usb_muxes property of @p port_id has callback board_init + * + * @param port_id USBC node ID + * @param op Operation to perform on USB muxes. Needs to accept USB mux node + * ID, USBC port node ID, position in chain, and driver config as + * arguments. + */ +#define USB_MUX_HAS_CB_BOARD_INIT(port_id, op) \ + USB_MUX_HAS_CB(port_id, board_init, op) + +/** + * @brief If usb_muxes property of @p port_id has callback board_set + * + * @param port_id USBC node ID + * @param op Operation to perform on USB muxes. Needs to accept USB mux node + * ID, USBC port node ID, position in chain, and driver config as + * arguments. + */ +#define USB_MUX_HAS_CB_BOARD_SET(port_id, op) \ + USB_MUX_HAS_CB(port_id, board_set, op) + /** * @brief Call @p op if @p idx mux in chain has BB retimer compatible * diff --git a/zephyr/shim/src/usb_muxes.c b/zephyr/shim/src/usb_muxes.c index d4361b8620..d74ba67d2b 100644 --- a/zephyr/shim/src/usb_muxes.c +++ b/zephyr/shim/src/usb_muxes.c @@ -26,6 +26,16 @@ */ #if USB_MUX_FOREACH_USBC_PORT(USB_MUX_PORT_HAS_MUX, _) 0 +/** + * Forward declarations for board_init and board_set callbacks. e.g. + * int c0_mux0_board_init(const struct usb_mux *); + * int c1_mux0_board_set(const struct usb_mux *, mux_state_t); + */ +USB_MUX_FOREACH_USBC_PORT(USB_MUX_HAS_CB_BOARD_INIT, + USB_MUX_CB_BOARD_INIT_DECLARE) +USB_MUX_FOREACH_USBC_PORT(USB_MUX_HAS_CB_BOARD_SET, + USB_MUX_CB_BOARD_SET_DECLARE) + /** * Define root of each USB muxes chain e.g. * [0] = { -- cgit v1.2.1 From a673a273a6a84d6b1df141c3d74d43a0624762f2 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 24 Jun 2022 16:28:25 +0800 Subject: nx20p348x: expose public header move i2c device register address and function declarations into public header. BUG=b:227359727 TEST=zmake BRANCH=none Change-Id: I51c967c53c3052196bc51964a7ca2f7d104a1781 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721942 Commit-Queue: Eric Yilun Lin Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin --- driver/ppc/nx20p348x.h | 21 +-------------------- include/driver/ppc/nx20p348x_public.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 20 deletions(-) create mode 100644 include/driver/ppc/nx20p348x_public.h diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h index ebda50da39..5188ea3f76 100644 --- a/driver/ppc/nx20p348x.h +++ b/driver/ppc/nx20p348x.h @@ -9,16 +9,7 @@ #define __CROS_EC_NX20P348X_H #include "common.h" - -#define NX20P3483_ADDR0_FLAGS 0x70 -#define NX20P3483_ADDR1_FLAGS 0x71 -#define NX20P3483_ADDR2_FLAGS 0x72 -#define NX20P3483_ADDR3_FLAGS 0x73 - -#define NX20P3481_ADDR0_FLAGS 0x74 -#define NX20P3481_ADDR1_FLAGS 0x75 -#define NX20P3481_ADDR2_FLAGS 0x76 -#define NX20P3481_ADDR3_FLAGS 0x77 +#include "ppc/nx20p348x_public.h" /* * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery @@ -121,16 +112,6 @@ #define NX20P348X_INT2_OC_HVSRC BIT(1) #define NX20P348X_INT2_OV_HVSRC BIT(0) -struct ppc_drv; -extern const struct ppc_drv nx20p348x_drv; - -/** - * Interrupt Handler for the NX20P348x. - * - * @param port: The Type-C port which triggered the interrupt. - */ -void nx20p348x_interrupt(int port); - /** * Board override for NX20P348X init. * diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h new file mode 100644 index 0000000000..e08f010c83 --- /dev/null +++ b/include/driver/ppc/nx20p348x_public.h @@ -0,0 +1,33 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TI NX20P348X USB-C Power Path Controller */ + +#ifndef __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H +#define __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H + +#include "usbc_ppc.h" + +#define NX20P3483_ADDR0_FLAGS 0x70 +#define NX20P3483_ADDR1_FLAGS 0x71 +#define NX20P3483_ADDR2_FLAGS 0x72 +#define NX20P3483_ADDR3_FLAGS 0x73 + +#define NX20P3481_ADDR0_FLAGS 0x74 +#define NX20P3481_ADDR1_FLAGS 0x75 +#define NX20P3481_ADDR2_FLAGS 0x76 +#define NX20P3481_ADDR3_FLAGS 0x77 + +extern const struct ppc_drv nx20p348x_drv; + + +/** + * Interrupt Handler for the NX20P348x. + * + * @param port: The Type-C port which triggered the interrupt. + */ +void nx20p348x_interrupt(int port); + +#endif /* __CROS_EC_DRIVER_PPC_NX20P348X_PUBLIC_H */ -- cgit v1.2.1 From ff6603b54621276b7236139c050504c74e7ee4cb Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 24 Jun 2022 16:37:50 +0800 Subject: anx7447: expose public header move i2c device register address and function declarations into public header. BUG=b:227359727 TEST=zmake BRANCH=none Change-Id: I6abf44ed35c48a5a8ff087130867b67c1cc5ec8c Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721943 Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- driver/tcpm/anx7447.h | 13 +------------ include/driver/tcpm/anx7447_public.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 12 deletions(-) create mode 100644 include/driver/tcpm/anx7447_public.h diff --git a/driver/tcpm/anx7447.h b/driver/tcpm/anx7447.h index e2752142d8..761c0e7cbf 100644 --- a/driver/tcpm/anx7447.h +++ b/driver/tcpm/anx7447.h @@ -4,6 +4,7 @@ */ #include "usb_mux.h" +#include "driver/tcpm/anx7447_public.h" /* USB Power delivery port management */ @@ -150,16 +151,6 @@ struct anx7447_i2c_addr { uint16_t spi_addr_flags; }; -#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C -#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B -#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A -#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 - -#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F -#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 -#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 -#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 - /* * Time TEST_R must be held high for a reset */ @@ -176,8 +167,6 @@ int anx7447_board_charging_enable(int port, int enable); void anx7447_hpd_mode_en(int port); void anx7447_hpd_output_en(int port); -extern const struct tcpm_drv anx7447_tcpm_drv; -extern const struct usb_mux_driver anx7447_usb_mux_driver; void anx7447_tcpc_clear_hpd_status(int port); void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h new file mode 100644 index 0000000000..7944707ba9 --- /dev/null +++ b/include/driver/tcpm/anx7447_public.h @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Analogix Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H + +#include "usb_mux.h" + +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 + +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 + +extern const struct tcpm_drv anx7447_tcpm_drv; +extern const struct usb_mux_driver anx7447_usb_mux_driver; + +void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, + mux_state_t mux_state, + bool *ack_required); +#endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */ -- cgit v1.2.1 From 0e3fa7b8aa981586db664c5a83912759ad31d1ee Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Thu, 7 Jul 2022 17:56:36 +0800 Subject: steelix: fix typo from -> form BUG=none TEST=zmake build steelix BRANCH=none Signed-off-by: Ting Shen Change-Id: Ic1bfed029c5aeb0906b9bb1a08f7f6b87ac22398 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751016 Auto-Submit: Ting Shen Commit-Queue: Eric Yilun Lin Reviewed-by: Eric Yilun Lin Tested-by: Ting Shen --- zephyr/projects/corsola/cbi_steelix.dts | 4 ++-- zephyr/projects/corsola/src/kingler/led_steelix.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/corsola/cbi_steelix.dts b/zephyr/projects/corsola/cbi_steelix.dts index 052bf23b5d..bd511e5427 100644 --- a/zephyr/projects/corsola/cbi_steelix.dts +++ b/zephyr/projects/corsola/cbi_steelix.dts @@ -11,8 +11,8 @@ * FW_CONFIG field to indicate the device is clamshell * or convertible. */ - from_factor { - enum-name = "FROM_FACTOR"; + form_factor { + enum-name = "FORM_FACTOR"; start = <13>; size = <3>; diff --git a/zephyr/projects/corsola/src/kingler/led_steelix.c b/zephyr/projects/corsola/src/kingler/led_steelix.c index 8a97253557..986203eaa9 100644 --- a/zephyr/projects/corsola/src/kingler/led_steelix.c +++ b/zephyr/projects/corsola/src/kingler/led_steelix.c @@ -95,9 +95,9 @@ static bool device_is_clamshell(void) int ret; uint32_t val; - ret = cros_cbi_get_fw_config(FROM_FACTOR, &val); + ret = cros_cbi_get_fw_config(FORM_FACTOR, &val); if (ret != 0) { - LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FROM_FACTOR); + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FORM_FACTOR); return false; } -- cgit v1.2.1 From bdb3302723e1f3beed8abe77dc2d84a920a87100 Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Thu, 7 Jul 2022 10:03:45 +0800 Subject: tentacruel: add ps8743 device binding add PS8743 USBC MUX device binding BUG=b:237955258 TEST=enable on tentacruel BRANCH=none Signed-off-by: jeffrey_lin Change-Id: Ie059aabb362da5fe390155dda2907c03cbfca176 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750261 Reviewed-by: Eric Yilun Lin --- zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml | 25 +++++++++++++++++++++++++ zephyr/shim/include/usbc/ps8743_usb_mux.h | 22 ++++++++++++++++++++++ zephyr/shim/include/usbc/usb_muxes.h | 2 ++ 3 files changed, 49 insertions(+) create mode 100644 zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml create mode 100644 zephyr/shim/include/usbc/ps8743_usb_mux.h diff --git a/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml new file mode 100644 index 0000000000..003f3ce13c --- /dev/null +++ b/zephyr/dts/bindings/usbc/mux/parade,ps8743.yaml @@ -0,0 +1,25 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: Parade PS8743 USB Type-C alternate mode MUX + +include: cros-ec,usbc-mux.yaml + +compatible: "parade,ps8743" + +properties: + port: + type: phandle + required: true + description: phandle to the named i2c port + + i2c-addr-flags: + type: string + required: true + description: I2C address of chip + enum: + - PS8743_I2C_ADDR0_FLAG + - PS8743_I2C_ADDR1_FLAG + - PS8743_I2C_ADDR2_FLAG + - PS8743_I2C_ADDR3_FLAG diff --git a/zephyr/shim/include/usbc/ps8743_usb_mux.h b/zephyr/shim/include/usbc/ps8743_usb_mux.h new file mode 100644 index 0000000000..9630abe447 --- /dev/null +++ b/zephyr/shim/include/usbc/ps8743_usb_mux.h @@ -0,0 +1,22 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_SHIM_PS8743_USB_MUX_H +#define __ZEPHYR_SHIM_PS8743_USB_MUX_H + +#include "usb_mux/ps8743_public.h" + +#define PS8743_USB_MUX_COMPAT parade_ps8743 + +#define USB_MUX_CONFIG_PS8743(mux_id, port_id, idx) \ + { \ + USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ + .driver = &ps8743_usb_mux_driver, \ + .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ + .i2c_addr_flags = \ + DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ + } + +#endif /* __ZEPHYR_SHIM_PS8743_USB_MUX_H */ diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h index 40c9ad53c8..f704cad51e 100644 --- a/zephyr/shim/include/usbc/usb_muxes.h +++ b/zephyr/shim/include/usbc/usb_muxes.h @@ -12,6 +12,7 @@ #include "usbc/anx7483_usb_mux.h" #include "usbc/bb_retimer_usb_mux.h" #include "usbc/it5205_usb_mux.h" +#include "usbc/ps8743_usb_mux.h" #include "usbc/tcpci_usb_mux.h" #include "usbc/tusb1064_usb_mux.h" #include "usbc/virtual_usb_mux.h" @@ -24,6 +25,7 @@ (ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483), \ (BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \ (IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205), \ + (PS8743_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8743), \ (PS8XXX_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ (TCPCI_TCPM_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ (TUSB1064_USB_MUX_COMPAT, USB_MUX_CONFIG_TUSB1064), \ -- cgit v1.2.1 From 63f8aface4fc2a59a3125e4ffd0ad459b326576b Mon Sep 17 00:00:00 2001 From: Kyle Lin Date: Thu, 7 Jul 2022 11:03:05 +0000 Subject: pompom: Update for inclusive terminology Replace 'slave' with 'target' for more inclusive terminology. BUG=none BRANCH=none TEST=The modified source file builds successfully. Change-Id: I1bd12697b811683898251045f6818869371b09ce Signed-off-by: Kyle Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750967 Reviewed-by: Marco Chen --- board/pompom/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/pompom/board.c b/board/pompom/board.c index e0b5c70588..6a21a57b10 100644 --- a/board/pompom/board.c +++ b/board/pompom/board.c @@ -607,7 +607,7 @@ static void board_detect_motionsensor(void) int val = 0; /* - * BMA253 and LIS2DWL have same slave address, so we check the + * BMA253 and LIS2DWL have same target address, so we check the * LIS2DWL WHO AM I register to check the lid accel type */ i2c_read8(I2C_PORT_SENSOR, LIS2DWL_ADDR0_FLAGS, LIS2DW12_WHO_AM_I_REG, -- cgit v1.2.1 From 97e7110972c274e1b8fbe804030f31422755e4fc Mon Sep 17 00:00:00 2001 From: Kyle Lin Date: Thu, 7 Jul 2022 11:20:50 +0000 Subject: pdeval-stm32f072: Update for inclusive terminology Replace 'slave' with 'target' for more inclusive terminology. BUG=none BRANCH=none TEST=none Change-Id: I290a3616ddfdcd9993acfd1fbb2eb585d07c1f54 Signed-off-by: Kyle Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750968 Reviewed-by: Marco Chen --- board/pdeval-stm32f072/PD_evaluation.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/pdeval-stm32f072/PD_evaluation.md b/board/pdeval-stm32f072/PD_evaluation.md index 4f1c8636c6..fd4763a849 100644 --- a/board/pdeval-stm32f072/PD_evaluation.md +++ b/board/pdeval-stm32f072/PD_evaluation.md @@ -43,12 +43,12 @@ also need to create/delete the corresponding `PD_Cx` tasks in [board/pdeval-stm32f072/ec.tasklist](ec.tasklist). By default, the firmware is using I2C1 with SCL/SDA on pins PB6 and PB7, running -with a 100kHz clock, and tries to talk to TCPCs at i2c slave addresses 0x9c and +with a 100kHz clock, and tries to talk to TCPCs at i2c target addresses 0x9c and 0x9e. To change the pins or speed, you need to edit `i2c_ports` in [board/pdeval-stm32f072/board.c](board.c), update `I2C_PORT_TCPC` in [board/pdeval-stm32f072/board.h](board.h) with the right controller number, and change the pin mux in [board/pdeval-stm32f072/gpio.inc](gpio.inc). To change -TCPC i2c slave addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in +TCPC i2c target addresses, update `TCPC1_I2C_ADDR` and `TCPC2_I2C_ADDR` in [board/pdeval-stm32f072/board.h](board.h). The I2C bus needs pull-up resistors on SCL/SDA. If your setup doesn't have -- cgit v1.2.1 From ccefe066ef68608c41c1356faf72fae79afe2391 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Thu, 23 Jun 2022 17:12:23 -0700 Subject: TCPMv2: correct LRD cable checking According to USB Type-C Cable and Connector Spec R2.1 The USB4 active cable types are: 1. Re-timer-based active cable 2. Linear re-driver-based (LRD-based) active cable 3. Linear optical active cable The LRD-based Active Cables were added to the USB ecosystem in a late phase. It aligns to the passive cable spec. It has product type as passive cable in ID Header VDO; but in TBT Cable Discover Mode VDO bit 25 is set as active cable. Cable SOP' should enter TBT mode while port partner enter USB4/TBT. Current code doesn't check product type when query if it's LRD cable. And this causes problem for new released Apple Pro Active cable, which has bit 25 set with product type as active cable. It is mistakenly identified as LRD cable, and goes to wrong path to set USB4/TBT mode. This patch adds the checking for product type in LRD cable query. And issues with Apple Pro cable are fixed. BUG=b:233402434 b:233429913 BRANCH=none TEST=On Voxel, tested Apple TBT4 Pro cable, SOP', SOP" and SOP all enter USB4 mode with USB4 Gatkex Creek board; with TBT3 dock, SOP', SOP" and SOP all enter TBT mode. Also tested passive/CBR/LRD/DBR/Apple TBT3 pro cables, verified working. Signed-off-by: Li Feng Change-Id: Id6aa61001a3e6010418071223f9bb5a208114739 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3722796 Reviewed-by: Abe Levkoy --- common/usbc/tbt_alt_mode.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index 608e5be195..60f9b94ae6 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -164,12 +164,9 @@ static bool tbt_is_lrd_active_cable(int port) union tbt_mode_resp_cable cable_mode_resp; cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); - /* TODO(b:233402434 b:233429913) - * Need to add the checking that cable is passive in Discover ID - * Header VDO. - */ - if (cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE && + cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) return true; return false; -- cgit v1.2.1 From ee16f4d3ff4290a484af888062c4629aeefab68c Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Wed, 6 Jul 2022 16:02:50 +0800 Subject: tentacruel: Modify USBC mux from tusb546 to ps8743 for tentacruel Modify USBC mux from tusb546 to ps8743 BUG=b:237955258 TEST=zmake build tentacruel --clobber BRANCH=None Signed-off-by: jeffrey_lin Change-Id: Ifd0ba3dd7ce7f3738cc8716aeb6e8a55d13f5467 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3747169 Reviewed-by: Eric Yilun Lin --- zephyr/projects/corsola/BUILD.py | 2 +- zephyr/projects/corsola/CMakeLists.txt | 2 +- zephyr/projects/corsola/prj_tentacruel.conf | 4 + .../corsola/src/krabby/usbc_config_tentacruel.c | 180 +++++++++++++++++++++ zephyr/projects/corsola/usbc_tentacruel.dts | 76 +++++++++ 5 files changed, 262 insertions(+), 2 deletions(-) create mode 100644 zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c create mode 100644 zephyr/projects/corsola/usbc_tentacruel.dts diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index baa595a0ca..ab3b8481f3 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -111,7 +111,7 @@ register_corsola_project( here / "cbi_eeprom.dts", here / "led_tentacruel.dts", here / "motionsense_krabby.dts", - here / "usbc_krabby.dts", + here / "usbc_tentacruel.dts", ], extra_kconfig_files=[ here / "prj_it81202_base.conf", diff --git a/zephyr/projects/corsola/CMakeLists.txt b/zephyr/projects/corsola/CMakeLists.txt index 9cc9bd9451..a506b0d384 100644 --- a/zephyr/projects/corsola/CMakeLists.txt +++ b/zephyr/projects/corsola/CMakeLists.txt @@ -57,6 +57,6 @@ elseif(DEFINED CONFIG_BOARD_TENTACRUEL) zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/krabby/usb_pd_policy.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC - "src/krabby/usbc_config.c") + "src/krabby/usbc_config_tentacruel.c") endif() diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf index 9d05fd5bfb..9d12bfb15d 100644 --- a/zephyr/projects/corsola/prj_tentacruel.conf +++ b/zephyr/projects/corsola/prj_tentacruel.conf @@ -4,3 +4,7 @@ # Variant config CONFIG_BOARD_TENTACRUEL=y + +# USB-C +CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n +CONFIG_PLATFORM_EC_USB_MUX_PS8743=y diff --git a/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c new file mode 100644 index 0000000000..5e83288088 --- /dev/null +++ b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c @@ -0,0 +1,180 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Krabby board-specific USB-C configuration */ + +#include "adc.h" +#include "baseboard_usbc_config.h" +#include "bc12/pi3usb9201_public.h" +#include "charge_manager.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/rt9490.h" +#include "driver/ppc/rt1739.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/usb_mux/ps8743.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "ppc/syv682x_public.h" +#include "usb_mux/it5205_public.h" +#include "usbc_ppc.h" + +#include "variant_db_detection.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) + +void c0_bc12_interrupt(enum gpio_signal signal) +{ + rt1739_interrupt(0); +} + +static void board_sub_bc12_init(void) +{ + if (corsola_get_db_type() == CORSOLA_DB_HDMI) { + /* If this is not a Type-C subboard, disable the task. */ + task_disable_task(TASK_ID_USB_CHG_P1); + } +} +/* Must be done after I2C and subboard */ +DECLARE_HOOK(HOOK_INIT, board_sub_bc12_init, HOOK_PRIO_POST_I2C); + +static void board_usbc_init(void) +{ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc_bc12)); +} +DECLARE_HOOK(HOOK_INIT, board_usbc_init, HOOK_PRIO_POST_DEFAULT); + +void ppc_interrupt(enum gpio_signal signal) +{ + if (signal == GPIO_SIGNAL(DT_ALIAS(gpio_usb_c1_ppc_int_odl))) { + syv682x_interrupt(1); + } +} + +int ppc_get_alert_status(int port) +{ + if (port == 0) { + return gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(usb_c0_ppc_bc12_int_odl)) == 0; + } + if (port == 1 && corsola_get_db_type() == CORSOLA_DB_TYPEC) { + return gpio_pin_get_dt( + GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl)) == 0; + } + + return 0; +} + +const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) +{ + const static struct cc_para_t + cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { + { + .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; + + return &cc_parameter[port]; +} + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* TODO: check correct operation for Corsola */ +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * C0 & C1: TCPC is embedded in the EC and processes interrupts in the + * chip code (it83xx/intc.c) + */ + return 0; +} + +void board_reset_pd_mcu(void) +{ + /* + * C0 & C1: TCPC is embedded in the EC and processes interrupts in the + * chip code (it83xx/intc.c) + */ +} + +int board_set_active_charge_port(int port) +{ + int i; + int is_valid_port = (port >= 0 && port < board_get_usb_pd_port_count()); + + if (!is_valid_port && port != CHARGE_PORT_NONE) { + return EC_ERROR_INVAL; + } + + if (port == CHARGE_PORT_NONE) { + CPRINTS("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("Disabling C%d as sink failed.", i); + } + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTS("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTS("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) { + continue; + } + + if (ppc_vbus_sink_enable(i, 0)) { + CPRINTS("C%d: sink path disable failed.", i); + } + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTS("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +#ifdef CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT +enum adc_channel board_get_vbus_adc(int port) +{ + if (port == 0) { + return ADC_VBUS_C0; + } + if (port == 1) { + return ADC_VBUS_C1; + } + CPRINTSUSB("Unknown vbus adc port id: %d", port); + return ADC_VBUS_C0; +} +#endif /* CONFIG_USB_PD_VBUS_MEASURE_ADC_EACH_PORT */ diff --git a/zephyr/projects/corsola/usbc_tentacruel.dts b/zephyr/projects/corsola/usbc_tentacruel.dts new file mode 100644 index 0000000000..adb955b8ab --- /dev/null +++ b/zephyr/projects/corsola/usbc_tentacruel.dts @@ -0,0 +1,76 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 { + compatible = "richtek,rt1739-bc12"; + status = "okay"; + }; + ppc { + compatible = "richtek,rt1739-ppc"; + status = "okay"; + port = <&i2c_usb_c0>; + i2c-addr-flags = "RT1739_ADDR1_FLAGS"; + }; + tcpc { + compatible = "ite,it8xxx2-tcpc"; + }; + chg { + compatible = "richtek,rt9490"; + status = "okay"; + port = <&i2c_charger>; + }; + usb-muxes = <&it5205_mux_0 &virtual_mux_0>; + }; + port0-muxes { + it5205_mux_0: it5205-mux-0 { + compatible = "ite,it5205"; + port = <&i2c_usb_mux0>; + i2c-addr-flags = "IT5205_I2C_ADDR1_FLAGS"; + }; + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 { + compatible = "richtek,rt9490-bc12"; + status = "okay"; + irq = <&int_usb_c1_bc12_charger>; + }; + ppc { + compatible = "silergy,syv682x"; + status = "okay"; + port = <&i2c_usb_c1>; + i2c-addr-flags = "SYV682X_ADDR0_FLAGS"; + frs_en_gpio = <&gpio_ec_x_gpio1>; + }; + tcpc { + compatible = "ite,it8xxx2-tcpc"; + }; + usb-muxes = <&ps8743_mux_1 &virtual_mux_1>; + }; + port1-muxes { + ps8743_mux_1: ps8743-mux-1 { + compatible = "parade,ps8743"; + port = <&i2c_usb_mux1>; + i2c-addr-flags = "PS8743_I2C_ADDR0_FLAG"; + }; + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; -- cgit v1.2.1 From 4ffc7b64738f524173135a1f758dd1a6123d3ac1 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 24 Jun 2022 16:42:18 +0800 Subject: rt1718s: expose public header move i2c device register address and function declarations into public header. BUG=b:227359727 TEST=zmake BRANCH=none Change-Id: I2fa6cf979a94d5b459e2b50bd1f37d14e44bc204 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721944 Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Eric Yilun Lin --- driver/tcpm/rt1718s.h | 14 +------------- include/driver/tcpm/rt1718s_public.h | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 13 deletions(-) create mode 100644 include/driver/tcpm/rt1718s_public.h diff --git a/driver/tcpm/rt1718s.h b/driver/tcpm/rt1718s.h index 0ac6ab4587..26acb41934 100644 --- a/driver/tcpm/rt1718s.h +++ b/driver/tcpm/rt1718s.h @@ -5,21 +5,12 @@ #ifndef __CROS_EC_USB_PD_TCPM_RT1718S_H #define __CROS_EC_USB_PD_TCPM_RT1718S_H +#include "tcpm/rt1718s_public.h" #include "util.h" #include "usb_charge.h" #include "usb_pd_tcpm.h" /* RT1718S Private RegMap */ -#define RT1718S_I2C_ADDR1_FLAGS 0x43 -#define RT1718S_I2C_ADDR2_FLAGS 0x40 - -#define RT1718S_VID 0x29CF -#define RT1718S_PID 0x1718 - -#define RT1718S_DEVICE_ID 0x04 -#define RT1718S_DEVICE_ID_ES1 0x4511 -#define RT1718S_DEVICE_ID_ES2 0x4513 - #define RT1718S_PHYCTRL1 0x80 #define RT1718S_PHYCTRL2 0x81 #define RT1718S_PHYCTRL3 0x82 @@ -184,9 +175,6 @@ #define RT1718S_ADC_CHX_VOL_L(ch) (0xF2A6 + (ch)*2) #define RT1718S_ADC_CHX_VOL_H(ch) (0xF2A7 + (ch)*2) -extern const struct tcpm_drv rt1718s_tcpm_drv; -extern const struct bc12_drv rt1718s_bc12_drv; - int rt1718s_write8(int port, int reg, int val); int rt1718s_read8(int port, int reg, int *val); int rt1718s_update_bits8(int port, int reg, int mask, int val); diff --git a/include/driver/tcpm/rt1718s_public.h b/include/driver/tcpm/rt1718s_public.h new file mode 100644 index 0000000000..e30f6ddeba --- /dev/null +++ b/include/driver/tcpm/rt1718s_public.h @@ -0,0 +1,24 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Richtek Type-C port controller */ + +#ifndef __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H +#define __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H + +#define RT1718S_I2C_ADDR1_FLAGS 0x43 +#define RT1718S_I2C_ADDR2_FLAGS 0x40 + +#define RT1718S_VID 0x29CF +#define RT1718S_PID 0x1718 + +#define RT1718S_DEVICE_ID 0x04 +#define RT1718S_DEVICE_ID_ES1 0x4511 +#define RT1718S_DEVICE_ID_ES2 0x4513 + +extern const struct tcpm_drv rt1718s_tcpm_drv; +extern const struct bc12_drv rt1718s_bc12_drv; + +#endif /* __CROS_EC_DRIVER_TCPM_RT1718S_PUBLIC_H */ -- cgit v1.2.1 From 819cfe07d00fec4bae2643ee5dcb5e0bc2ec8cb9 Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Fri, 8 Jul 2022 15:55:49 +0800 Subject: tentacruel: define CONFIG_KEYBOARD_REFRESH_ROW3 Select this config since refresh key is on Row 3. BUG=b:238064331 TEST=zmake build tentacruel --clobber BRANCH=none Signed-off-by: jeffrey_lin Change-Id: I6bb9fb8a2c08c275e38749b77d3e4b6e1cb74ce6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752429 Reviewed-by: Ting Shen --- zephyr/projects/corsola/prj_tentacruel.conf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/zephyr/projects/corsola/prj_tentacruel.conf b/zephyr/projects/corsola/prj_tentacruel.conf index 9d12bfb15d..918fb6c446 100644 --- a/zephyr/projects/corsola/prj_tentacruel.conf +++ b/zephyr/projects/corsola/prj_tentacruel.conf @@ -8,3 +8,6 @@ CONFIG_BOARD_TENTACRUEL=y # USB-C CONFIG_PLATFORM_EC_USB_MUX_TUSB546=n CONFIG_PLATFORM_EC_USB_MUX_PS8743=y + +# Keyboard +CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y -- cgit v1.2.1 From fcc48e7fcad6e32d009c79324b700d2abb1a9bde Mon Sep 17 00:00:00 2001 From: ben chen Date: Thu, 7 Jul 2022 13:17:44 +0800 Subject: kuldax: adjust Fan PWM frequence Modify fan PWM frequence to 25k for meet fan spec BUG=b:238260272 BRANCH=cros/main TEST=build BOARD PASS and thermal check is PASS. Change-Id: I23a0d9fafbbc60d3a0930b88a061a021ed817789 Signed-off-by: Ben Chen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750544 Reviewed-by: Zhuohao Lee --- board/kuldax/pwm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/kuldax/pwm.c b/board/kuldax/pwm.c index 6d66ad7c31..15cb430fcf 100644 --- a/board/kuldax/pwm.c +++ b/board/kuldax/pwm.c @@ -16,8 +16,8 @@ const struct pwm_t pwm_channels[] = { PWM_CONFIG_DSLEEP, .freq = 2000 }, [PWM_CH_FAN] = { .channel = 5, - .flags = PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_DSLEEP, - .freq = 1000 }, + .flags = PWM_CONFIG_OPEN_DRAIN, + .freq = 25000 }, [PWM_CH_LED_RED] = { .channel = 2, .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, .freq = 2000 }, -- cgit v1.2.1 From b64c96a2798bf56c69356e8a7b056998e4f6fb38 Mon Sep 17 00:00:00 2001 From: Patryk Duda Date: Mon, 4 Jul 2022 15:20:26 +0200 Subject: flash_fp_mcu: Remove double reset when leaving bootloader If write protect on RO sectors (EC_FLASH_PROTECT_RO_NOW) is enabled and hardware write protect pin is disabled, FPMCU will disable WP on RO sectors while booting (crec_flash_pre_init() in chip/stm32/flash-f.c). When stm32mon finishes, we reboot FPMCU using nRST pin to leave bootloader and later we power cycle FPMCU (workaround for dartmonkey write protect bug). Running 'flash_fp_mcu --hello' doesn't change any read/write protection settings, so RO is still protected. After first reset, FPMCU tries to disable WP, but during that it could be power cycled which leaves internal flash settings in a bad state. The solution for this problem is that we should reboot FPMCU only once at the end. BUG=b:233276135 BRANCH=none TEST=On Zork, enable WP on flash sectors the run 'flash_fp_mcu --hello'. Reboot DUT. Make sure 'ectool --name=cros_fp version' works TEST=tast run firmware.Fp{AddEntropy,BioWash,CheckWriteProtect, \ FlashFpMcuHello,RDP0,RDP1,ROOnlyBootsValidRW,RWNoUpdateRO, \ ReadFlash,RebootToRO,SoftwareWriteProtect,SystemIsLocked,TpmSeed, Updater} on hatch, strongbad, nocturne, nami, zork. Change-Id: Ia818edd342e1a1c3351ad261ea3b5241348e3667 Signed-off-by: Patryk Duda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3743366 Reviewed-by: Tom Hughes Tested-by: Patryk Duda Commit-Queue: Patryk Duda --- util/flash_fp_mcu | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index d31e3a836d..7be55e9475 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -430,19 +430,7 @@ flash_fp_mcu_stm32() { fi # Go back to normal mode - gpio out "${gpio_nrst}" - gpio 0 "${gpio_boot0}" "${gpio_nrst}" - gpio 1 "${gpio_nrst}" - - # Give up GPIO control, unless we need to keep these driving as - # outputs because they're not open-drain signals. - # TODO(b/179839337): Make this the default and properly support - # open-drain outputs on other platforms. - if [[ "${PLATFORM_BASE_NAME}" != "strongbad" ]] && - [[ "${PLATFORM_BASE_NAME}" != "herobrine" ]]; then - gpio in "${gpio_boot0}" "${gpio_nrst}" - fi - gpio unexport "${gpio_boot0}" "${gpio_nrst}" + gpio 0 "${gpio_boot0}" # Dartmonkey's RO has a flashprotect logic issue that forces reboot loops # when SW-WP is enabled and HW-WP is disabled. It is avoided if a POR is @@ -458,8 +446,25 @@ flash_fp_mcu_stm32() { gpio 1 "${gpio_pwren}" # Power enable line is externally pulled down, so leave as output-high. gpio unexport "${gpio_pwren}" + else + echo "Reset the FPMCU." + gpio out "${gpio_nrst}" + gpio 0 "${gpio_nrst}" + # Make sure that we keep nRST line low long enough. + sleep 0.01 + gpio 1 "${gpio_nrst}" fi + # Give up GPIO control, unless we need to keep these driving as + # outputs because they're not open-drain signals. + # TODO(b/179839337): Make this the default and properly support + # open-drain outputs on other platforms. + if [[ "${PLATFORM_BASE_NAME}" != "strongbad" ]] && + [[ "${PLATFORM_BASE_NAME}" != "herobrine" ]]; then + gpio in "${gpio_boot0}" "${gpio_nrst}" + fi + gpio unexport "${gpio_boot0}" "${gpio_nrst}" + # Put back cros_fp driver if transport is SPI if [[ "${transport}" != "UART" ]]; then # wait for FP MCU to come back up (including RWSIG delay) -- cgit v1.2.1 From ee5dcc9ae08f0fafced7f2b54720928cbe273b2b Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Wed, 6 Jul 2022 09:27:55 +0200 Subject: zephyr: tests: fix bmi160 flaky tests Add before and after test routines to initialize the bmi160 emulator properly. It includes: -reenabling sensors -setting a correct chip ID -disabling a rotation vector -clearing the I2C fail register It should fix every flaky bmi160 test. BUG=b:233104376 TEST=enable the test shuffling; make sure there is no "bmi160.c" string in the output BRANCH=main Signed-off-by: Dawid Niedzwiecki Change-Id: I6769f91e10b147a0c28730469c85cda8f128931f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748784 Reviewed-by: Tomasz Michalec Commit-Queue: Yuval Peress Reviewed-by: Yuval Peress --- zephyr/test/drivers/src/bmi160.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/bmi160.c b/zephyr/test/drivers/src/bmi160.c index 473858f5ea..39144bd9e6 100644 --- a/zephyr/test/drivers/src/bmi160.c +++ b/zephyr/test/drivers/src/bmi160.c @@ -2080,4 +2080,40 @@ ZTEST_USER(bmi160, test_bmi_init_chip_id) i2c_common_emul_set_write_func(emul, NULL, NULL); } -ZTEST_SUITE(bmi160, drivers_predicate_post_main, NULL, NULL, NULL, NULL); +static void bmi160_before(void *fixture) +{ + ARG_UNUSED(fixture); + struct i2c_emul *emul = bmi_emul_get(BMI_ORD); + struct motion_sensor_t *acc_ms; + struct motion_sensor_t *gyr_ms; + + acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID]; + gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID]; + + i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); + bmi_emul_set_reg(emul, BMI160_CHIP_ID, 0xd1); + + /* Disable rotation */ + gyr_ms->rot_standard_ref = NULL; + acc_ms->rot_standard_ref = NULL; + + zassume_equal(EC_SUCCESS, acc_ms->drv->set_data_rate(acc_ms, 50000, 0), + NULL); + zassume_equal(EC_SUCCESS, gyr_ms->drv->set_data_rate(gyr_ms, 50000, 0), + NULL); +} + +static void bmi160_after(void *state) +{ + ARG_UNUSED(state); + struct motion_sensor_t *acc_ms, *gyr_ms; + + acc_ms = &motion_sensors[BMI_ACC_SENSOR_ID]; + gyr_ms = &motion_sensors[BMI_GYR_SENSOR_ID]; + + acc_ms->drv->set_data_rate(acc_ms, 0, 0); + gyr_ms->drv->set_data_rate(gyr_ms, 0, 0); +} + +ZTEST_SUITE(bmi160, drivers_predicate_post_main, NULL, bmi160_before, + bmi160_after, NULL); -- cgit v1.2.1 From 2c4345a9eeb1665327dafaa3ac2a1060d34ff452 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 6 Jul 2022 13:17:39 -0700 Subject: tree: Fix -Wstrict-prototypes warning The latest clang complains about missing 'void' in function definition if it's specified in the declaration: core/cortex-m/vecttable.c:23:21: error: a function declaration without a prototype is deprecated in all versions of C [-Werror,-Wstrict-prototypes] void default_handler() ^ void BRANCH=none BUG=b:230345382, b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I5a3d95203cc6cbb59676f4a66876a4a6f2946e31 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750108 Reviewed-by: Ting Shen --- chip/npcx/system.c | 2 +- chip/stm32/bkpdata.c | 2 +- core/cortex-m/vecttable.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/chip/npcx/system.c b/chip/npcx/system.c index d85dc3cdde..47909a5f54 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -1374,7 +1374,7 @@ void system_jump_to_booter(void) #endif } -uint32_t system_get_lfw_address() +uint32_t system_get_lfw_address(void) { /* * In A3 version, we don't use little FW anymore diff --git a/chip/stm32/bkpdata.c b/chip/stm32/bkpdata.c index 5a51128fc3..65fedae3f8 100644 --- a/chip/stm32/bkpdata.c +++ b/chip/stm32/bkpdata.c @@ -65,7 +65,7 @@ int bkpdata_index_lookup(enum system_bbram_idx idx, int *msb) return -1; } -uint32_t bkpdata_read_reset_flags() +uint32_t bkpdata_read_reset_flags(void) { uint32_t flags = bkpdata_read(BKPDATA_INDEX_SAVED_RESET_FLAGS); diff --git a/core/cortex-m/vecttable.c b/core/cortex-m/vecttable.c index e89eca17c0..6f57deb603 100644 --- a/core/cortex-m/vecttable.c +++ b/core/cortex-m/vecttable.c @@ -20,7 +20,7 @@ typedef void (*func)(void); #if PASS == 1 /* Default exception handler */ void __attribute__((used, naked)) default_handler(void); -void default_handler() +void default_handler(void) { asm(".thumb_func\n" " b exception_panic"); @@ -58,7 +58,7 @@ void weak_with_default svc_handler(int desched, task_id_t resched); * it only loads r0 (desched) and r1 (resched) for svc_handler. */ void __attribute__((used, naked)) svc_helper_handler(void); -void svc_helper_handler() +void svc_helper_handler(void) { asm(".thumb_func\n" " tst lr, #4 /* see if called from supervisor mode */\n" -- cgit v1.2.1 From 42692e6c86c6258b921d1a22a146a4b7f9d28345 Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Mon, 13 Jun 2022 11:30:52 -0700 Subject: zephyr: Enable USB Type-C on Nuvoton Ports for MTL This patch will enable the Type-C functionality on ports 0 and 1 for Meteorlake RVP. BUG=none BRANCH=none TEST=zmake mtlrvpp_npcx flashed and tested USB, DP, TBT, and USB4 Signed-off-by: Brandon Breitenstein Change-Id: I11e7fe1b8aeb7ae4a7ddf0b55dcddd2ac37c9100 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3573470 Tested-by: Vijay P Hiremath Reviewed-by: Fabio Baltieri Commit-Queue: Jack Rosenthal --- zephyr/dts/bindings/gpio/gpio-enum-name.yaml | 6 + zephyr/projects/intelrvp/BUILD.py | 1 + zephyr/projects/intelrvp/CMakeLists.txt | 3 + .../projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts | 80 +++++++---- .../intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts | 20 +++ .../intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts | 2 +- zephyr/projects/intelrvp/mtlrvp/prj.conf | 33 ++++- zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c | 151 +++++++++++++++++++++ zephyr/projects/intelrvp/mtlrvp/usbc.dts | 70 ++++++++++ zephyr/projects/intelrvp/src/chg_usb_pd.c | 129 ++++++++++++++++++ zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c | 92 +++++++++++++ .../projects/intelrvp/src/usb_pd_policy_mecc_1_1.c | 106 +++++++++++++++ 12 files changed, 661 insertions(+), 32 deletions(-) create mode 100644 zephyr/projects/intelrvp/mtlrvp/usbc.dts create mode 100644 zephyr/projects/intelrvp/src/chg_usb_pd.c create mode 100644 zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c create mode 100644 zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml index f4b5d0a89e..0984e1cdf2 100644 --- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml +++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml @@ -136,6 +136,10 @@ properties: - IOEX_USB_C0_BB_RETIMER_RST - IOEX_USB_C0_C1_OC - IOEX_USB_C0_FRS_EN + - IOEX_USB_C0_HBR_LS_EN + - IOEX_USB_C0_HBR_RST + - IOEX_USB_C0_MUX_SBU_SEL_0 + - IOEX_USB_C0_MUX_SBU_SEL_1 - IOEX_USB_C0_PPC_ILIM_3A_EN - IOEX_USB_C0_SBU_FLIP - IOEX_USB_C0_TCPC_FASTSW_CTL_EN @@ -144,6 +148,8 @@ properties: - IOEX_USB_C1_BB_RETIMER_LS_EN - IOEX_USB_C1_BB_RETIMER_RST - IOEX_USB_C1_FAULT_ODL + - IOEX_USB_C1_HBR_LS_EN + - IOEX_USB_C1_HBR_RST - IOEX_USB_C1_HPD - IOEX_USB_C1_HPD_IN_DB - IOEX_USB_C1_PPC_ILIM_3A_EN diff --git a/zephyr/projects/intelrvp/BUILD.py b/zephyr/projects/intelrvp/BUILD.py index 93e0b64c4a..3fa9bd256e 100644 --- a/zephyr/projects/intelrvp/BUILD.py +++ b/zephyr/projects/intelrvp/BUILD.py @@ -71,6 +71,7 @@ register_intelrvp_project( here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts", here / "mtlrvp/mtlrvpp_npcx/mtlrvp_npcx_power_signals.dts", here / "adlrvp/adlrvp_npcx/temp_sensor.dts", + here / "mtlrvp/usbc.dts", ], extra_kconfig_files=[ here / "zephyr_ap_pwrseq.conf", diff --git a/zephyr/projects/intelrvp/CMakeLists.txt b/zephyr/projects/intelrvp/CMakeLists.txt index f8a76be55d..9abde95f34 100644 --- a/zephyr/projects/intelrvp/CMakeLists.txt +++ b/zephyr/projects/intelrvp/CMakeLists.txt @@ -26,4 +26,7 @@ endif() if(DEFINED CONFIG_BOARD_MTLRVP_NPCX) add_subdirectory(mtlrvp) zephyr_library_sources("src/intelrvp.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/usb_pd_policy_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd_mecc_1_1.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/chg_usb_pd.c") endif() diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts index 924f508f5f..86143fdd7a 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -53,32 +53,33 @@ gpio_wp: wp-l { gpios = <&gpiod 5 GPIO_INPUT>; }; - std-adp-prsnt { + std_adp_prsnt: std-adp-prsnt { gpios = <&gpioc 6 GPIO_INPUT>; + enum-name = "GPIO_DC_JACK_PRESENT"; }; bc_acok: bc-acok-ec { gpios = <&gpio0 2 GPIO_INPUT>; enum-name = "GPIO_AC_PRESENT"; }; - usbc-tcpc-alrt-p0 { + usbc_tcpc_alrt_p0: usbc-tcpc-alrt-p0 { gpios = <&gpio4 0 GPIO_INPUT>; }; /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P0 */ - usb-c0-c1-tcpc-rst-odl { + usb_c0_c1_tcpc_rst_odl: usb-c0-c1-tcpc-rst-odl { gpios = <&gpiod 0 GPIO_ODR_HIGH>; }; /* NOTE: Netname is USBC_TCPC_ALRT_P1 */ - usbc-tcpc-ppc-alrt-p0 { + usbc_tcpc_ppc_alrt_p0: usbc-tcpc-ppc-alrt-p0 { gpios = <&gpiod 1 GPIO_INPUT>; }; - usbc-tcpc-ppc-alrt-p1 { + usbc_tcpc_ppc_alrt_p1: usbc-tcpc-ppc-alrt-p1 { gpios = <&gpioe 4 GPIO_INPUT>; }; - usbc-tcpc-alrt-p2 { + usbc_tcpc_alrt_p2: usbc-tcpc-alrt-p2 { gpios = <&gpio9 1 GPIO_INPUT>; }; /* NOTE: Netname is USBC_TCPC_PPC_ALRT_P3 */ - usbc-tcpc-ppc-alrt-p3 { + usbc_tcpc_alrt_p3: usbc-tcpc-alrt-p3 { gpios = <&gpiof 3 GPIO_INPUT>; }; gpio_ec_pch_wake_odl: pch-wake-n { @@ -143,8 +144,9 @@ gpios = <&gpioc 0 GPIO_OUTPUT_LOW>; }; /* NOTE: Netname is USBC_TCPC_ALRT_P3 */ - ccd-mode-odl { + ccd_mode_odl: ccd-mode-odl { gpios = <&gpio9 2 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; }; smb-bs-clk { gpios = <&gpiob 3 GPIO_INPUT>; @@ -256,7 +258,7 @@ tp-gpiof1 { gpios = <&gpiof 1 GPIO_INPUT>; }; - usbc-tcpc-ppc-alrt-p2 { + usbc_tcpc_ppc_alrt_p2: usbc-tcpc-ppc-alrt-p2 { gpios = <&gpiof 2 GPIO_INPUT>; }; tp-gpiof4 { @@ -286,26 +288,43 @@ }; /* USB C IOEX configuration */ - usb-c0-hbr-ls-en { + usb_c0_hb_retimer_ls_en: usb-c0-hbr-ls-en { gpios = <&ioex_c0 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_LS_EN"; + no-auto-init; }; - usb-c0-hbr-rst { + usb_c0_hb_retimer_rst: usb-c0-hbr-rst { gpios = <&ioex_c0 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_HBR_RST"; + no-auto-init; }; - usb-c1-hbr-ls-en { + usb_c1_hb_retimer_ls_en: usb-c1-hbr-ls-en { gpios = <&ioex_c1 2 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_LS_EN"; + no-auto-init; }; - usb-c1-hbr-rst { + usb_c1_hb_retimer_rst: usb-c1-hbr-rst { gpios = <&ioex_c1 3 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C1_HBR_RST"; + no-auto-init; }; usb-c0-mux-oe-n { gpios = <&ioex_c0 4 GPIO_OUTPUT_LOW>; + no-auto-init; }; usb-c0-mux-sbu-sel-0 { gpios = <&ioex_c0 6 GPIO_OUTPUT_HIGH>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_0"; + no-auto-init; }; usb-c0-mux-sbu-sel-1 { gpios = <&ioex_c1 4 GPIO_OUTPUT_LOW>; + enum-name = "IOEX_USB_C0_MUX_SBU_SEL_1"; + no-auto-init; + }; + usb-c0-c1-prochot-n { + gpios = <&ioex_c1 6 GPIO_INPUT>; + no-auto-init; }; /* unimplemented GPIOs */ en-pp5000 { @@ -329,30 +348,32 @@ }; &i2c0_0 { - nct38xx_C0:nct38xx_C0@70 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; - label = "NCT38XX_C0"; + status = "okay"; - ioex_c0:gpio@0 { + nct38xx_c0: nct38xx_c0@73 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,nct38xx-gpio"; + reg = <0x73>; + label = "NCT38XX_C0"; + + ioex_c0:gpio@0 { compatible = "nuvoton,nct38xx-gpio-port"; reg = <0x0>; label = "NCT38XX_C0_GPIO0"; gpio-controller; #gpio-cells = <2>; ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; }; }; - nct38xx_C1:nct38xx_C1@70 { + nct38xx_c1: nct38xx_c1@77 { #address-cells = <1>; #size-cells = <0>; compatible = "nuvoton,nct38xx-gpio"; - reg = <0x70>; + reg = <0x77>; label = "NCT38XX_C1"; ioex_c1:gpio@0 { @@ -362,8 +383,15 @@ gpio-controller; #gpio-cells = <2>; ngpios = <8>; - pin_mask = <0xff>; - pinmux_mask = <0xf7>; + pin_mask = <0xdc>; + pinmux_mask = <0xff>; }; }; + + nct38xx_alert_0 { + compatible = "nuvoton,nct38xx-gpio-alert"; + irq-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + nct38xx-dev = <&nct38xx_c0 &nct38xx_c1>; + label = "NCT38XX_ALERT_1"; + }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts index acf1630a71..9d081527fb 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts @@ -26,5 +26,25 @@ flags = ; handler = "io_expander_it8801_interrupt"; }; + int_usb_c0_c1_tcpc: usb_c0_tcpc { + irq-pin = <&usbc_tcpc_alrt_p0>; + flags = ; + handler = "tcpc_alert_event"; + }; + int_usb_c0_ppc: usb_c0_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p0>; + flags = ; + handler = "ppc_interrupt"; + }; + int_usb_c1_ppc: usb_c1_ppc { + irq-pin = <&usbc_tcpc_ppc_alrt_p1>; + flags = ; + handler = "ppc_interrupt"; + }; + int_ccd_mode: ccd_mode { + irq-pin = <&ccd_mode_odl>; + flags = ; + handler = "board_connect_c0_sbu"; + }; }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts index 8ff2efd460..4c2e18c2ba 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts @@ -24,7 +24,7 @@ i2c-port = <&i2c7_0>; enum-name = "I2C_PORT_BATTERY"; }; - charger { + i2c_charger: charger { i2c-port = <&i2c7_0>; enum-name = "I2C_PORT_CHARGER"; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf index e89098701b..04397c8fc9 100644 --- a/zephyr/projects/intelrvp/mtlrvp/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -10,6 +10,7 @@ CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL=n # Battery CONFIG_PLATFORM_EC_BATTERY_TYPE_NO_AUTO_DETECT=y +CONFIG_PLATFORM_EC_BATTERY_V2=y # CBI CONFIG_EEPROM=y @@ -19,11 +20,17 @@ CONFIG_PLATFORM_EC_CBI_EEPROM=y CONFIG_PLATFORM_EC_BYPASS_CBI_EEPROM_WP_CHECK=y CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y -# USB-C and charging -# Below config are disabled to successfully compile battery conf -# This will be enabled in upcoming CL -CONFIG_PLATFORM_EC_USBC=n -CONFIG_PLATFORM_EC_CHARGER=n +# Disable BC1.2 +CONFIG_PLATFORM_EC_USB_CHARGER=n + +# Charger +CONFIG_PLATFORM_EC_CHARGER=y +CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=5 +CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=10 +CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=n +CONFIG_PLATFORM_EC_CHARGER_ISL9241=y +CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y # IOEX CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y @@ -41,8 +48,24 @@ CONFIG_PLATFORM_EC_THERMISTOR=y CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y # USB CONFIG +CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y +CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y +CONFIG_PLATFORM_EC_USB_MUX_TASK=y +CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USB_PD_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y +CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y +CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y +CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y +CONFIG_PLATFORM_EC_USBC_VCONN=y +CONFIG_PLATFORM_EC_USB_PD_TBT_COMPAT_MODE=y +CONFIG_PLATFORM_EC_USB_PD_USB4=y +CONFIG_PLATFORM_EC_USB_PD_INT_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_0_SHARED=y +CONFIG_PLATFORM_EC_USB_PD_PORT_1_SHARED=y # 7-Segment Display CONFIG_PLATFORM_EC_MAX695X_SEVEN_SEGMENT_DISPLAY=y diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c index 6bac6d1302..7d382da318 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c @@ -3,18 +3,135 @@ * found in the LICENSE file. */ +#include "battery.h" +#include "battery_fuel_gauge.h" +#include "charger.h" #include "common.h" #include "console.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/nct38xx.h" +#include "extpower.h" #include "gpio.h" +#include "gpio/gpio_int.h" +#include "hooks.h" #include "i2c.h" #include "intelrvp.h" #include "intel_rvp_board_id.h" +#include "ioexpander.h" +#include "isl9241.h" #include "keyboard_raw.h" #include "power/meteorlake.h" +#include "sn5s330.h" +#include "system.h" +#include "task.h" +#include "tusb1064.h" +#include "usb_mux.h" +#include "usbc_ppc.h" +#include "util.h" #define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ##args) #define CPRINTS(format, args...) cprints(CC_COMMAND, format, ##args) +/*******************************************************************/ +/* USB-C Configuration Start */ + +/* PPC */ +#define I2C_ADDR_SN5S330_P0 0x40 +#define I2C_ADDR_SN5S330_P1 0x41 + +/* USB-C ports */ +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* USB-C PPC configuration */ +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P0, + .drv = &sn5s330_drv, + }, + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_TYPEC_AIC_1, + .i2c_addr_flags = I2C_ADDR_SN5S330_P1, + .drv = &sn5s330_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* TCPC AIC GPIO Configuration */ +const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { + [USBC_PORT_C0] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p0)), + .ppc_intr_handler = sn5s330_interrupt, + }, + [USBC_PORT_C1] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p0)), + .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)), + .ppc_intr_handler = sn5s330_interrupt, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void board_connect_c0_sbu_deferred(void) +{ + enum pd_power_role prole; + + if (gpio_get_level(GPIO_CCD_MODE_ODL)) { + CPRINTS("Default AUX line connected"); + /* Default set the SBU lines to AUX mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + prole = pd_get_power_role(USBC_PORT_C0); + CPRINTS("%s debug device is attached", + prole == PD_ROLE_SINK ? "Servo V4C/SuzyQ" : "Intel"); + + if (prole == PD_ROLE_SINK) { + /* Set the SBU lines to Google CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 1); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 1); + } else { + /* Set the SBU lines to Intel CCD mode */ + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_1, 0); + ioex_set_level(IOEX_USB_C0_MUX_SBU_SEL_0, 0); + } + } +} +DECLARE_DEFERRED(board_connect_c0_sbu_deferred); + +void board_overcurrent_event(int port, int is_overcurrented) +{ + /* + * TODO: Meteorlake PCH does not use Physical GPIO for over current + * error, hence Send 'Over Current Virtual Wire' eSPI signal. + */ +} + +void board_reset_pd_mcu(void) +{ + /* Reset NCT38XX TCPC */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(usb_c0_c1_tcpc_rst_odl), 1); + nct38xx_reset_notify(0); + nct38xx_reset_notify(1); + + if (NCT3807_RESET_POST_DELAY_MS != 0) { + msleep(NCT3807_RESET_POST_DELAY_MS); + } + + /* NCT38XX chip uses gpio ioex */ + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0))); + gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1))); +} + +void board_connect_c0_sbu(enum gpio_signal signal) +{ + hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0); +} + /******************************************************************************/ /* KSO mapping for discrete keyboard */ __override const uint8_t it8801_kso_mapping[] = { @@ -106,3 +223,37 @@ __override int board_get_version(void) mtlrvp_board_id = board_id | (fab_id << 8); return mtlrvp_board_id; } + +static void board_int_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc)); + + /* Enable CCD Mode interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode)); +} + +static int board_pre_task_peripheral_init(const struct device *unused) +{ + ARG_UNUSED(unused); + + /* Only reset tcpc/pd if not sysjump */ + if (!system_jumped_late()) { + /* Initialize tcpc and all ioex */ + board_reset_pd_mcu(); + } + + /* Initialize all interrupts */ + board_int_init(); + + /* Make sure SBU are routed to CCD or AUX based on CCD status at init */ + board_connect_c0_sbu_deferred(); + + return 0; +} +SYS_INIT(board_pre_task_peripheral_init, APPLICATION, + CONFIG_APPLICATION_INIT_PRIORITY); diff --git a/zephyr/projects/intelrvp/mtlrvp/usbc.dts b/zephyr/projects/intelrvp/mtlrvp/usbc.dts new file mode 100644 index 0000000000..a07c3853aa --- /dev/null +++ b/zephyr/projects/intelrvp/mtlrvp/usbc.dts @@ -0,0 +1,70 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + + #include + +/ { + usbc { + #address-cells = <1>; + #size-cells = <0>; + + usbc_port0: port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + tcpc { + compatible = "nuvoton,nct38xx"; + gpio-dev = <&nct38xx_c0>; + port = <&typec_aic1>; + i2c-addr-flags = "NCT38XX_I2C_ADDR1_4_FLAGS"; + tcpc-flags = <( + TCPC_FLAGS_TCPCI_REV2_0 | + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL)>; + }; + chg { + compatible = "intersil,isl9241"; + status = "okay"; + port = <&i2c_charger>; + }; + usb-muxes = <&usb_c0_hb_retimer &virtual_mux_c0>; + }; + port0-muxes { + usb_c0_hb_retimer: jhl8040r-c0 { + compatible = "intel,jhl8040r"; + port = <&typec_aic1>; + i2c-addr-flags = <0x56>; + reset-pin = <&usb_c0_hb_retimer_rst>; + ls-en-pin = <&usb_c0_hb_retimer_ls_en>; + }; + virtual_mux_c0: virtual-mux-c0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port1: port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + tcpc { + compatible = "nuvoton,nct38xx"; + gpio-dev = <&nct38xx_c1>; + port = <&typec_aic1>; + i2c-addr-flags = "NCT38XX_I2C_ADDR2_4_FLAGS"; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; + usb-muxes = <&usb_c1_hb_retimer &virtual_mux_c1>; + }; + port1-muxes { + usb_c1_hb_retimer: jhl8040r-c1 { + compatible = "intel,jhl8040r"; + port = <&typec_aic1>; + i2c-addr-flags = <0x57>; + reset-pin = <&usb_c1_hb_retimer_rst>; + ls-en-pin = <&usb_c1_hb_retimer_ls_en>; + }; + virtual_mux_c1: virtual-mux-c1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + }; +}; diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd.c b/zephyr/projects/intelrvp/src/chg_usb_pd.c new file mode 100644 index 0000000000..9919602877 --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd.c @@ -0,0 +1,129 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Common USB PD charge configuration */ + +#include "charge_manager.h" +#include "charge_state_v2.h" +#include "gpio.h" +#include "hooks.h" +#include "intelrvp.h" +#include "tcpm/tcpci.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +bool is_typec_port(int port) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return !(port == DEDICATED_CHARGE_PORT || port == CHARGE_PORT_NONE); +#else + return !(port == CHARGE_PORT_NONE); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static inline int board_dc_jack_present(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + return gpio_get_level(GPIO_DC_JACK_PRESENT); +#else + return 0; +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +static void board_dc_jack_handle(void) +{ +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + struct charge_port_info charge_dc_jack; + + /* System is booted from DC Jack */ + if (board_dc_jack_present()) { + charge_dc_jack.current = + (PD_MAX_POWER_MW * 1000) / DC_JACK_MAX_VOLTAGE_MV; + charge_dc_jack.voltage = DC_JACK_MAX_VOLTAGE_MV; + } else { + charge_dc_jack.current = 0; + charge_dc_jack.voltage = USB_CHARGER_VOLTAGE_MV; + } + + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, &charge_dc_jack); +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 */ +} + +void board_dc_jack_interrupt(enum gpio_signal signal) +{ + board_dc_jack_handle(); +} + +static void board_charge_init(void) +{ + int port, supplier; + struct charge_port_info charge_init = { + .current = 0, + .voltage = USB_CHARGER_VOLTAGE_MV, + }; + + /* Initialize all charge suppliers to seed the charge manager */ + for (port = 0; port < CHARGE_PORT_COUNT; port++) { + for (supplier = 0; supplier < CHARGE_SUPPLIER_COUNT; + supplier++) { + charge_manager_update_charge(supplier, port, + &charge_init); + } + } + + board_dc_jack_handle(); +} +DECLARE_HOOK(HOOK_INIT, board_charge_init, HOOK_PRIO_DEFAULT); + +int board_set_active_charge_port(int port) +{ + int i; + /* charge port is a realy physical port */ + int is_real_port = (port >= 0 && port < CHARGE_PORT_COUNT); + /* check if we are source vbus on that port */ + int source = board_vbus_source_enabled(port); + + if (is_real_port && source) { + CPRINTS("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + +#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 + /* + * Do not enable Type-C port if the DC Jack is present. + * When the Type-C is active port, hardware circuit will + * block DC jack from enabling +VADP_OUT. + */ + if (port != DEDICATED_CHARGE_PORT && board_dc_jack_present()) { + CPRINTS("DC Jack present, Skip enable p%d", port); + return EC_ERROR_INVAL; + } +#endif /* CONFIG_DEDICATED_CHARGE_PORT_COUNT */ + + /* Make sure non-charging ports are disabled */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (i != port) { + board_charging_enable(i, 0); + } + } + + /* Enable charging port */ + if (is_typec_port(port)) { + board_charging_enable(port, 1); + } + + CPRINTS("New chg p%d", port); + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} diff --git a/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c new file mode 100644 index 0000000000..203803e663 --- /dev/null +++ b/zephyr/projects/intelrvp/src/chg_usb_pd_mecc_1_1.c @@ -0,0 +1,92 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Intel-RVP family-specific configuration */ + +#include "console.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "include/gpio.h" +#include "intelrvp.h" +#include "ioexpander.h" +#include "system.h" +#include "tcpm/tcpci.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +void tcpc_alert_event(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embedded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (signal == tcpc_aic_gpios[i].tcpc_alert) { + schedule_deferred_pd_interrupt(i); + break; + } + } +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + int i; + + /* Check which port has the ALERT line set */ + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + /* No alerts for embdeded TCPC */ + if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED) { + continue; + } + + if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert)) { + status |= PD_STATUS_TCPC_ALERT_0 << i; + } + } + + return status; +} + +int ppc_get_alert_status(int port) +{ + return tcpc_aic_gpios[port].ppc_intr_handler && + !gpio_get_level(tcpc_aic_gpios[port].ppc_alert); +} + +/* PPC support routines */ +void ppc_interrupt(enum gpio_signal signal) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (tcpc_aic_gpios[i].ppc_intr_handler && + signal == tcpc_aic_gpios[i].ppc_alert) { + tcpc_aic_gpios[i].ppc_intr_handler(i); + break; + } + } +} + +void board_charging_enable(int port, int enable) +{ + int rv; + + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, enable); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, enable); + } + + if (rv) { + CPRINTS("C%d: sink path %s failed", port, + enable ? "en" : "dis"); + } +} diff --git a/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c new file mode 100644 index 0000000000..946521c3a5 --- /dev/null +++ b/zephyr/projects/intelrvp/src/usb_pd_policy_mecc_1_1.c @@ -0,0 +1,106 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "console.h" +#include "gpio.h" +#include "intelrvp.h" +#include "usb_mux.h" +#include "usbc_ppc.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) + +static inline void board_pd_set_vbus_discharge(int port, bool enable) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_discharge_vbus(port, enable); + } else { + tcpc_discharge_vbus(port, enable); + } +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_sink_enable(port, 0); + } else { + rv = tcpc_config[port].drv->set_snk_ctrl(port, 0); + } + + if (rv) { + return rv; + } + + board_pd_set_vbus_discharge(port, false); + + /* Provide Vbus. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + rv = ppc_vbus_source_enable(port, 1); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 1); + } + + if (rv) { + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = board_vbus_source_enabled(port); + + /* Disable VBUS. */ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + ppc_vbus_source_enable(port, 0); + } else { + tcpc_config[port].drv->set_src_ctrl(port, 0); + } + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) { + board_pd_set_vbus_discharge(port, true); + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_check_vconn_swap(int port) +{ + /* Only allow vconn swap if PP3300 rail is enabled */ + return gpio_get_level(GPIO_EN_PP3300_A); +} + +int pd_snk_is_vbus_provided(int port) +{ + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_vbus_present(port); + } else { + return tcpc_config[port].drv->check_vbus_level(port, + VBUS_PRESENT); + } +} + +int board_vbus_source_enabled(int port) +{ + if (is_typec_port(port)) { + if (tcpc_aic_gpios[port].ppc_intr_handler) { + return ppc_is_sourcing_vbus(port); + } else { + return tcpc_config[port].drv->get_src_ctrl(port); + } + } + return 0; +} -- cgit v1.2.1 From a103b8df46557cda86911ac36a084f08e600ad02 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Thu, 7 Jul 2022 17:43:17 -0600 Subject: util: Correct shuffle_test false positive errors The shuffle_test.sh Zephyr test utility script greps for a user provided failure string. When the script doesn't find such failure string via grep it erroneously reports this as "Error/timeout". Make the utility script only report "Error/timeout" after finding the user provided failure string. BRANCH=none BUG=b:236726670 TEST=shuffle tests with and without failures Signed-off-by: Aaron Massey Change-Id: I989bc89cf8877e29aafea1a0f5c7f279ba1bd356 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751777 Reviewed-by: Yuval Peress --- util/shuffle_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh index 69a6f694f3..662aaa7bce 100755 --- a/util/shuffle_test.sh +++ b/util/shuffle_test.sh @@ -28,7 +28,7 @@ while [ "${loop_count}" -gt 0 ]; do if [ "${status}" -eq 124 ]; then echo " Timeout" result="timed-out" - elif [ "${status}" -ne 0 ]; then + elif [ "${status}" -eq 0 ]; then echo " Error/timeout" result="exit-code-${status}" fi -- cgit v1.2.1 From 94f92cd7f12736e9b59e0fd399d5663789019b22 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Fri, 8 Jul 2022 10:58:21 -0700 Subject: clang-format: Ran clang-format on all files again A number of files have had non-compliant changes uploaded since all files were formatted. Likely, the changes were uploaded before CL:3751770, so the author would not have seen any pre-upload failures. Re-format these files. This CL was generated via: clang-format -i $(find -name '*.[ch]' -type f -not -path '*third_party*') BUG=b:236386294 BRANCH=none TEST=none Signed-off-by: Jack Rosenthal Change-Id: Iedad17d13c29f45c7601d43f7fa2ce3215cc678e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751462 Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes --- board/beadrix/board.c | 5 +- board/osiris/keyboard.c | 4 +- common/printf.c | 4 +- common/usbc/tbt_alt_mode.c | 4 +- driver/retimer/anx7483.c | 3 +- driver/retimer/bb_retimer.c | 9 +- include/driver/ppc/nx20p348x_public.h | 1 - include/driver/retimer/anx7483_public.h | 3 +- include/driver/tcpm/anx7447_public.h | 19 ++- include/ec_commands.h | 8 +- test/debug.c | 1 - test/utils.c | 1 - test/utils_str.c | 1 - util/ectool.c | 38 ++--- .../corsola/src/krabby/usbc_config_tentacruel.c | 40 ++--- zephyr/shim/include/usbc/anx7483_usb_mux.h | 2 +- zephyr/shim/include/usbc/ppc_sn5s330.h | 10 +- zephyr/shim/include/usbc/tcpc_ccgxxf.h | 6 +- zephyr/shim/include/usbc/tcpc_fusb302.h | 6 +- zephyr/shim/include/usbc/tcpc_it8xxx2.h | 9 +- zephyr/shim/include/usbc/tcpc_nct38xx.h | 6 +- zephyr/shim/include/usbc/tcpc_ps8xxx.h | 6 +- zephyr/shim/include/usbc/tcpci.h | 6 +- zephyr/shim/include/usbc/usb_muxes.h | 20 +-- zephyr/test/drivers/src/bb_retimer.c | 6 +- .../drivers/src/integration/usbc/usb_alt_mode.c | 15 +- zephyr/test/drivers/src/ps8xxx.c | 179 +++++++++++---------- 27 files changed, 206 insertions(+), 206 deletions(-) diff --git a/board/beadrix/board.c b/board/beadrix/board.c index fc5a53b9ee..dd6f1146a2 100644 --- a/board/beadrix/board.c +++ b/board/beadrix/board.c @@ -443,8 +443,9 @@ int board_set_active_charge_port(int port) } /* - * Stop the charger IC from switching while changing ports. Otherwise, - * we can overcurrent the adapter we're switching to. (crbug.com/926056) + * Stop the charger IC from switching while changing ports. + * Otherwise, we can overcurrent the adapter we're switching to. + * (crbug.com/926056) */ charger_discharge_on_ac(1); } diff --git a/board/osiris/keyboard.c b/board/osiris/keyboard.c index 5aaaae8a02..647fcf8eca 100644 --- a/board/osiris/keyboard.c +++ b/board/osiris/keyboard.c @@ -82,8 +82,8 @@ const uint8_t rgbkbd_vsize = RGB_GRID0_ROW; const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS; -#define LED(x, y) RGBKBD_COORD((x), (y)) -#define DELM RGBKBD_DELM +#define LED(x, y) RGBKBD_COORD((x), (y)) +#define DELM RGBKBD_DELM const uint8_t rgbkbd_map[] = { DELM, LED(0, 0), DELM, LED(1, 0), DELM, LED(2, 0), DELM, LED(3, 0), diff --git a/common/printf.c b/common/printf.c index 5102dd8f20..610a2da94f 100644 --- a/common/printf.c +++ b/common/printf.c @@ -256,8 +256,8 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, * For more context, see * https://issuetracker.google.com/issues/172210614 */ - if (!IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS) - && !(flags & PF_64BIT)) { + if (!IS_ENABLED(CONFIG_PRINTF_LONG_IS_32BITS) && + !(flags & PF_64BIT)) { format = error_str; continue; } diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index 60f9b94ae6..a7640fcfe6 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -164,9 +164,9 @@ static bool tbt_is_lrd_active_cable(int port) union tbt_mode_resp_cable cable_mode_resp; cable_mode_resp.raw_value = - pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); + pd_get_tbt_mode_vdo(port, TCPCI_MSG_SOP_PRIME); if (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE && - cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) + cable_mode_resp.tbt_active_passive == TBT_CABLE_ACTIVE) return true; return false; diff --git a/driver/retimer/anx7483.c b/driver/retimer/anx7483.c index ac0150179d..302d12c701 100644 --- a/driver/retimer/anx7483.c +++ b/driver/retimer/anx7483.c @@ -286,8 +286,7 @@ static enum ec_error_list anx7483_apply_tuning(const struct usb_mux *me, return EC_SUCCESS; } -int anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state) +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state) { bool flipped = mux_state & USB_PD_MUX_POLARITY_INVERTED; diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index 6b7dffa2cc..d57c1318e5 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -414,7 +414,6 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, } if (mux_state & USB_PD_MUX_DP_ENABLED) { - /* * Bit 11-10: DP_PIN_ASSIGNMENT (ignored if BIT8 = 0) * 00 – Pin assignments E/E’ @@ -507,11 +506,11 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, * low power mode until the external monitor is connected. */ if (mux_state & USB_PD_MUX_HPD_LVL) - retimer_con_reg |= (BB_RETIMER_HPD_LVL | - BB_RETIMER_DP_CONNECTION); + retimer_con_reg |= + (BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION); else - retimer_con_reg &= ~(BB_RETIMER_HPD_LVL | - BB_RETIMER_DP_CONNECTION); + retimer_con_reg &= + ~(BB_RETIMER_HPD_LVL | BB_RETIMER_DP_CONNECTION); /* Writing the register4 */ bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg); diff --git a/include/driver/ppc/nx20p348x_public.h b/include/driver/ppc/nx20p348x_public.h index e08f010c83..382dceb949 100644 --- a/include/driver/ppc/nx20p348x_public.h +++ b/include/driver/ppc/nx20p348x_public.h @@ -22,7 +22,6 @@ extern const struct ppc_drv nx20p348x_drv; - /** * Interrupt Handler for the NX20P348x. * diff --git a/include/driver/retimer/anx7483_public.h b/include/driver/retimer/anx7483_public.h index bc7c6bbc0f..07596ff5a5 100644 --- a/include/driver/retimer/anx7483_public.h +++ b/include/driver/retimer/anx7483_public.h @@ -56,8 +56,7 @@ enum ec_error_list anx7483_set_eq(const struct usb_mux *me, * Configure datasheet defaults for tuning registers at this mux setting. * Return int so function can be used directly for board_set. */ -int anx7483_set_default_tuning(const struct usb_mux *me, - mux_state_t mux_state); +int anx7483_set_default_tuning(const struct usb_mux *me, mux_state_t mux_state); extern const struct usb_mux_driver anx7483_usb_retimer_driver; #endif /* __CROS_EC_USB_RETIMER_ANX7483_PUBLIC_H */ diff --git a/include/driver/tcpm/anx7447_public.h b/include/driver/tcpm/anx7447_public.h index 7944707ba9..f8ac990d42 100644 --- a/include/driver/tcpm/anx7447_public.h +++ b/include/driver/tcpm/anx7447_public.h @@ -10,20 +10,19 @@ #include "usb_mux.h" -#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C -#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B -#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A -#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 +#define AN7447_TCPC0_I2C_ADDR_FLAGS 0x2C +#define AN7447_TCPC1_I2C_ADDR_FLAGS 0x2B +#define AN7447_TCPC2_I2C_ADDR_FLAGS 0x2A +#define AN7447_TCPC3_I2C_ADDR_FLAGS 0x29 -#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F -#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 -#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 -#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 +#define AN7447_SPI0_I2C_ADDR_FLAGS 0x3F +#define AN7447_SPI1_I2C_ADDR_FLAGS 0x37 +#define AN7447_SPI2_I2C_ADDR_FLAGS 0x32 +#define AN7447_SPI3_I2C_ADDR_FLAGS 0x31 extern const struct tcpm_drv anx7447_tcpm_drv; extern const struct usb_mux_driver anx7447_usb_mux_driver; void anx7447_tcpc_update_hpd_status(const struct usb_mux *me, - mux_state_t mux_state, - bool *ack_required); + mux_state_t mux_state, bool *ack_required); #endif /* __CROS_EC_DRIVER_TCPM_ANX7447_PUBLIC_H */ diff --git a/include/ec_commands.h b/include/ec_commands.h index 0db33f802d..3d23c678ee 100644 --- a/include/ec_commands.h +++ b/include/ec_commands.h @@ -7173,10 +7173,10 @@ BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255); enum ec_rgbkbd_type { EC_RGBKBD_TYPE_UNKNOWN = 0, - EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ - EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ - EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ - EC_RGBKBD_TYPE_FOUR_ZONES_15_LEDS = 4, /* e.g. Mithrax */ + EC_RGBKBD_TYPE_PER_KEY = 1, /* e.g. Vell */ + EC_RGBKBD_TYPE_FOUR_ZONES_40_LEDS = 2, /* e.g. Taniks */ + EC_RGBKBD_TYPE_FOUR_ZONES_12_LEDS = 3, /* e.g. Osiris */ + EC_RGBKBD_TYPE_FOUR_ZONES_15_LEDS = 4, /* e.g. Mithrax */ EC_RGBKBD_TYPE_COUNT, }; diff --git a/test/debug.c b/test/debug.c index 0e4676b8b1..0a742ff773 100644 --- a/test/debug.c +++ b/test/debug.c @@ -22,7 +22,6 @@ test_static int test_debugger_is_connected(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); diff --git a/test/utils.c b/test/utils.c index d5bdcf6b4e..bc78ce8beb 100644 --- a/test/utils.c +++ b/test/utils.c @@ -14,7 +14,6 @@ #include "util.h" #include "watchdog.h" - static int test_uint64divmod_0(void) { uint64_t n = 8567106442584750ULL; diff --git a/test/utils_str.c b/test/utils_str.c index fa42ff0703..7607b071f2 100644 --- a/test/utils_str.c +++ b/test/utils_str.c @@ -104,7 +104,6 @@ static int test_strzcpy(void) return EC_SUCCESS; } - void run_test(int argc, char **argv) { test_reset(); diff --git a/util/ectool.c b/util/ectool.c index 24fc49763f..9a74cf207e 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -1288,25 +1288,25 @@ int cmd_reboot_ap_on_g3(int argc, char *argv[]) static void cmd_rgbkbd_help(char *cmd) { fprintf(stderr, - " Usage1: %s [ ...]\n" - " Set the color of to . Multiple colors for\n" - " adjacent keys can be set at once.\n" - "\n" - " Usage2: %s clear \n" - " Set the color of all keys to .\n" - "\n" - " Usage3: %s demo \n" - " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" - "\n" - " Usage4: %s scale \n" - " Set the scale parameter of key_ to .\n" - " is a 24-bit integer where scale values are encoded\n" - " as R=23:16, G=15:8, B=7:0.\n" - "\n" - " Usage5: %s getconfig\n" - " Get the HW config supported.\n" - "\n", - cmd, cmd, cmd, cmd, cmd); + " Usage1: %s [ ...]\n" + " Set the color of to . Multiple colors for\n" + " adjacent keys can be set at once.\n" + "\n" + " Usage2: %s clear \n" + " Set the color of all keys to .\n" + "\n" + " Usage3: %s demo \n" + " Run demo-. 0: Off, 1: Flow, 2: Dot.\n" + "\n" + " Usage4: %s scale \n" + " Set the scale parameter of key_ to .\n" + " is a 24-bit integer where scale values are encoded\n" + " as R=23:16, G=15:8, B=7:0.\n" + "\n" + " Usage5: %s getconfig\n" + " Get the HW config supported.\n" + "\n", + cmd, cmd, cmd, cmd, cmd); } static int cmd_rgbkbd_parse_rgb_text(const char *text, struct rgb_s *color) diff --git a/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c index 5e83288088..a83a7a0072 100644 --- a/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c +++ b/zephyr/projects/corsola/src/krabby/usbc_config_tentacruel.c @@ -23,9 +23,9 @@ #include "variant_db_detection.h" -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args) -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args) +#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args) void c0_bc12_interrupt(enum gpio_signal signal) { @@ -58,12 +58,12 @@ void ppc_interrupt(enum gpio_signal signal) int ppc_get_alert_status(int port) { if (port == 0) { - return gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(usb_c0_ppc_bc12_int_odl)) == 0; + return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + usb_c0_ppc_bc12_int_odl)) == 0; } if (port == 1 && corsola_get_db_type() == CORSOLA_DB_TYPEC) { - return gpio_pin_get_dt( - GPIO_DT_FROM_ALIAS(gpio_usb_c1_ppc_int_odl)) == 0; + return gpio_pin_get_dt(GPIO_DT_FROM_ALIAS( + gpio_usb_c1_ppc_int_odl)) == 0; } return 0; @@ -73,15 +73,19 @@ const struct cc_para_t *board_get_cc_tuning_parameter(enum usbpd_port port) { const static struct cc_para_t cc_parameter[CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT] = { - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - { - .rising_time = IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, - .falling_time = IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, - }, - }; + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + { + .rising_time = + IT83XX_TX_PRE_DRIVING_TIME_1_UNIT, + .falling_time = + IT83XX_TX_PRE_DRIVING_TIME_2_UNIT, + }, + }; return &cc_parameter[port]; } @@ -169,10 +173,10 @@ int board_set_active_charge_port(int port) enum adc_channel board_get_vbus_adc(int port) { if (port == 0) { - return ADC_VBUS_C0; + return ADC_VBUS_C0; } if (port == 1) { - return ADC_VBUS_C1; + return ADC_VBUS_C1; } CPRINTSUSB("Unknown vbus adc port id: %d", port); return ADC_VBUS_C0; diff --git a/zephyr/shim/include/usbc/anx7483_usb_mux.h b/zephyr/shim/include/usbc/anx7483_usb_mux.h index a36f00671d..80585ce9ab 100644 --- a/zephyr/shim/include/usbc/anx7483_usb_mux.h +++ b/zephyr/shim/include/usbc/anx7483_usb_mux.h @@ -14,7 +14,7 @@ { \ USB_MUX_COMMON_FIELDS(mux_id, port_id, idx), \ .driver = &anx7483_usb_retimer_driver, \ - .board_set = &anx7483_set_default_tuning, \ + .board_set = &anx7483_set_default_tuning, \ .i2c_port = I2C_PORT(DT_PHANDLE(mux_id, port)), \ .i2c_addr_flags = \ DT_STRING_UPPER_TOKEN(mux_id, i2c_addr_flags), \ diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h index cbf129cd99..f42039da7a 100644 --- a/zephyr/shim/include/usbc/ppc_sn5s330.h +++ b/zephyr/shim/include/usbc/ppc_sn5s330.h @@ -7,7 +7,9 @@ #define SN5S330_COMPAT ti_sn5s330 -#define PPC_CHIP_SN5S330(id) \ - { .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ - .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ - .drv = &sn5s330_drv } +#define PPC_CHIP_SN5S330(id) \ + { \ + .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ + .drv = &sn5s330_drv \ + } diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h index 3671aa96f1..db2dbe10fc 100644 --- a/zephyr/shim/include/usbc/tcpc_ccgxxf.h +++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h @@ -8,8 +8,8 @@ #define CCGXXF_TCPC_COMPAT cypress_ccgxxf -#define TCPC_CONFIG_CCGXXF(id) \ - { \ +#define TCPC_CONFIG_CCGXXF(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ @@ -17,5 +17,5 @@ id, i2c_addr_flags), \ }, \ .drv = &ccgxxf_tcpm_drv, \ - .flags = TCPC_FLAGS_TCPCI_REV2_0, \ + .flags = TCPC_FLAGS_TCPCI_REV2_0, \ } diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h index 39ff776803..d9f80a2ac6 100644 --- a/zephyr/shim/include/usbc/tcpc_fusb302.h +++ b/zephyr/shim/include/usbc/tcpc_fusb302.h @@ -8,13 +8,13 @@ #define FUSB302_TCPC_COMPAT fairchild_fusb302 -#define TCPC_CONFIG_FUSB302(id) \ - { \ +#define TCPC_CONFIG_FUSB302(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ .addr_flags = DT_STRING_UPPER_TOKEN( \ id, i2c_addr_flags), \ }, \ - .drv = &fusb302_tcpm_drv, \ + .drv = &fusb302_tcpm_drv, \ } diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h index 82893c2978..9ec7d05a8a 100644 --- a/zephyr/shim/include/usbc/tcpc_it8xxx2.h +++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h @@ -8,9 +8,8 @@ #define IT8XXX2_TCPC_COMPAT ite_it8xxx2_tcpc -#define TCPC_CONFIG_IT8XXX2(id) \ - { \ - .bus_type = EC_BUS_TYPE_EMBEDDED, \ - .drv = &it8xxx2_tcpm_drv, \ - .flags = 0, \ +#define TCPC_CONFIG_IT8XXX2(id) \ + { \ + .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it8xxx2_tcpm_drv, \ + .flags = 0, \ } diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h index dd3716f085..2dc6d32286 100644 --- a/zephyr/shim/include/usbc/tcpc_nct38xx.h +++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h @@ -11,8 +11,8 @@ #define NCT38XX_TCPC_COMPAT nuvoton_nct38xx -#define TCPC_CONFIG_NCT38XX(id) \ - { \ +#define TCPC_CONFIG_NCT38XX(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ @@ -20,7 +20,7 @@ id, i2c_addr_flags), \ }, \ .drv = &nct38xx_tcpm_drv, \ - .flags = DT_PROP(id, tcpc_flags), \ + .flags = DT_PROP(id, tcpc_flags), \ } /** diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h index bfe20eb6a5..ca121fbde2 100644 --- a/zephyr/shim/include/usbc/tcpc_ps8xxx.h +++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h @@ -8,8 +8,8 @@ #define PS8XXX_COMPAT parade_ps8xxx -#define TCPC_CONFIG_PS8XXX(id) \ - { \ +#define TCPC_CONFIG_PS8XXX(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ @@ -17,5 +17,5 @@ id, i2c_addr_flags), \ }, \ .drv = &ps8xxx_tcpm_drv, \ - .flags = DT_PROP(id, tcpc_flags), \ + .flags = DT_PROP(id, tcpc_flags), \ } diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h index 1247eb8d01..17d535e04f 100644 --- a/zephyr/shim/include/usbc/tcpci.h +++ b/zephyr/shim/include/usbc/tcpci.h @@ -9,12 +9,12 @@ #define TCPCI_COMPAT cros_ec_tcpci -#define TCPC_CONFIG_TCPCI(id) \ - { \ +#define TCPC_CONFIG_TCPCI(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ .addr_flags = DT_PROP(id, i2c_addr_flags), \ }, \ - .drv = &tcpci_tcpm_drv, \ + .drv = &tcpci_tcpm_drv, \ } diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h index f704cad51e..250b3dd329 100644 --- a/zephyr/shim/include/usbc/usb_muxes.h +++ b/zephyr/shim/include/usbc/usb_muxes.h @@ -84,7 +84,7 @@ * @param idx Position of USB mux in chain * @param conf Driver configuration function */ -#define USB_MUX_CB_BOARD_INIT_DECLARE(mux_id, port_id, idx, conf) \ +#define USB_MUX_CB_BOARD_INIT_DECLARE(mux_id, port_id, idx, conf) \ int DT_STRING_TOKEN(mux_id, board_init)(const struct usb_mux *); /** @@ -95,8 +95,8 @@ * @param idx Position of USB mux in chain * @param conf Driver configuration function */ -#define USB_MUX_CB_BOARD_SET_DECLARE(mux_id, port_id, idx, conf) \ - int DT_STRING_TOKEN(mux_id, board_set)(const struct usb_mux *, \ +#define USB_MUX_CB_BOARD_SET_DECLARE(mux_id, port_id, idx, conf) \ + int DT_STRING_TOKEN(mux_id, board_set)(const struct usb_mux *, \ mux_state_t); /** @@ -300,8 +300,8 @@ * @param cb The callback name * @param op Operation to perform on USB muxes */ -#define USB_MUX_DO_SKIP_NO_CB(port_id, mux_id, idx, cb, op) \ - COND_CODE_0(IS_EMPTY(DT_STRING_TOKEN(mux_id, cb)), \ +#define USB_MUX_DO_SKIP_NO_CB(port_id, mux_id, idx, cb, op) \ + COND_CODE_0(IS_EMPTY(DT_STRING_TOKEN(mux_id, cb)), \ (USB_MUX_DO(port_id, idx, op)), ()) /** @@ -313,9 +313,9 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_HAS_CB(port_id, cb, op) \ - DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, \ - USB_MUX_DO_SKIP_NO_CB, cb, op) +#define USB_MUX_HAS_CB(port_id, cb, op) \ + DT_FOREACH_PROP_ELEM_VARGS(port_id, usb_muxes, USB_MUX_DO_SKIP_NO_CB, \ + cb, op) /** * @brief If usb_muxes property of @p port_id has callback board_init @@ -325,7 +325,7 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_HAS_CB_BOARD_INIT(port_id, op) \ +#define USB_MUX_HAS_CB_BOARD_INIT(port_id, op) \ USB_MUX_HAS_CB(port_id, board_init, op) /** @@ -336,7 +336,7 @@ * ID, USBC port node ID, position in chain, and driver config as * arguments. */ -#define USB_MUX_HAS_CB_BOARD_SET(port_id, op) \ +#define USB_MUX_HAS_CB_BOARD_SET(port_id, op) \ USB_MUX_HAS_CB(port_id, board_set, op) /** diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/src/bb_retimer.c index dad3f14c2c..97dc621948 100644 --- a/zephyr/test/drivers/src/bb_retimer.c +++ b/zephyr/test/drivers/src/bb_retimer.c @@ -175,8 +175,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | - BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_IRQ_HPD; + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_IRQ_HPD; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); @@ -189,8 +188,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) zassert_false(ack_required, "ACK is never required for BB retimer"); conn = bb_emul_get_reg(emul, BB_RETIMER_REG_CONNECTION_STATE); exp_conn = BB_RETIMER_USB_DATA_ROLE | - BB_RETIMER_DATA_CONNECTION_PRESENT | - BB_RETIMER_HPD_LVL; + BB_RETIMER_DATA_CONNECTION_PRESENT | BB_RETIMER_HPD_LVL; zassert_equal(exp_conn, conn, "Expected state 0x%lx, got 0x%lx", exp_conn, conn); } diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c index a9ad3d43c9..7724ac993f 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c @@ -319,14 +319,14 @@ ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery) { host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); + TYPEC_MODE_DP); k_sleep(K_SECONDS(1)); uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; struct ec_response_typec_discovery *discovery = (struct ec_response_typec_discovery *)response_buffer; - host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, - response_buffer, sizeof(response_buffer)); + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, + sizeof(response_buffer)); /* The host command does not count the VDM header in identity_count. */ zassert_equal(discovery->identity_count, @@ -334,11 +334,10 @@ ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery) "Expected %d identity VDOs, got %d", fixture->partner.identity_vdos - 1, discovery->identity_count); - zassert_mem_equal(discovery->discovery_vdo, - fixture->partner.identity_vdm + 1, - discovery->identity_count * - sizeof(*discovery->discovery_vdo), - "Discovered SOP identity ACK did not match"); + zassert_mem_equal( + discovery->discovery_vdo, fixture->partner.identity_vdm + 1, + discovery->identity_count * sizeof(*discovery->discovery_vdo), + "Discovered SOP identity ACK did not match"); zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", discovery->svid_count); zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, diff --git a/zephyr/test/drivers/src/ps8xxx.c b/zephyr/test/drivers/src/ps8xxx.c index 303be071ea..3cec82dc93 100644 --- a/zephyr/test/drivers/src/ps8xxx.c +++ b/zephyr/test/drivers/src/ps8xxx.c @@ -20,7 +20,7 @@ #include "driver/tcpm/ps8xxx_public.h" #include "test/drivers/test_state.h" -#define PS8XXX_EMUL_LABEL DT_LABEL(DT_NODELABEL(ps8xxx_emul)) +#define PS8XXX_EMUL_LABEL DT_LABEL(DT_NODELABEL(ps8xxx_emul)) /** Test PS8xxx init fail conditions common for all PS8xxx devices */ static void test_ps8xxx_init_fail(void) @@ -79,16 +79,14 @@ ZTEST(ps8805, test_ps8805_init) /* Test fail on read I2C debug reg */ i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_I2C_DEBUGGING_ENABLE); - zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), - NULL); + zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test fail on read DCI reg */ i2c_common_emul_set_read_fail_reg(p1_i2c_emul, PS8XXX_P1_REG_MUX_USB_DCI_CFG); - zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), - NULL); + zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); i2c_common_emul_set_read_fail_reg(p1_i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -98,7 +96,8 @@ ZTEST(ps8805, test_ps8805_init) PS8XXX_REG_I2C_DEBUGGING_ENABLE_ON); zassert_equal(PS8XXX_REG_MUX_USB_DCI_CFG_MODE_OFF, ps8xxx_emul_get_dci_cfg(ps8xxx_emul) & - PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK, NULL); + PS8XXX_REG_MUX_USB_DCI_CFG_MODE_MASK, + NULL); } /** Test PS8815 init */ @@ -116,8 +115,7 @@ ZTEST(ps8815, test_ps8815_init) /* Test fail on reading HW revision register */ i2c_common_emul_set_read_fail_reg(p1_i2c_emul, PS8815_P1_REG_HW_REVISION); - zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), - NULL); + zassert_equal(EC_ERROR_INVAL, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); i2c_common_emul_set_read_fail_reg(p1_i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); @@ -134,16 +132,14 @@ static void test_ps8xxx_release(void) /* Test successful release with correct FW reg read */ start_ms = k_uptime_get(); - zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), - NULL); + zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), NULL); zassert_true(k_uptime_get() - start_ms < 10, "release on correct FW reg read shouldn't wait for chip"); /* Test delay on FW reg read fail */ i2c_common_emul_set_read_fail_reg(tcpci_i2c_emul, PS8XXX_REG_FW_REV); start_ms = k_uptime_get(); - zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), - NULL); + zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.release(USBC_PORT_C1), NULL); zassert_true(k_uptime_get() - start_ms >= 10, "release on FW reg read fail should wait for chip"); } @@ -250,8 +246,8 @@ ZTEST(ps8815, test_ps8815_set_cc) check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0, "delay on HW rev 0x0a00"); delay = k_uptime_delta(&start_time); - zassert_true(delay >= 1, - "expected delay on HW rev 0x0a00 (delay %lld)", delay); + zassert_true(delay >= 1, "expected delay on HW rev 0x0a00 (delay %lld)", + delay); /* * Set hw revision 0x0a01 to enable workaround for b/171430855 (delay @@ -263,8 +259,8 @@ ZTEST(ps8815, test_ps8815_set_cc) check_ps8815_set_cc(TYPEC_RP_1A5, TYPEC_CC_RP, 0, "delay on HW rev 0x0a01"); delay = k_uptime_delta(&start_time); - zassert_true(delay >= 1, - "expected delay on HW rev 0x0a01 (delay %lld)", delay); + zassert_true(delay >= 1, "expected delay on HW rev 0x0a01 (delay %lld)", + delay); /* * Set other hw revision to disable workaround for b/171430855 (delay @@ -325,18 +321,18 @@ static void test_ps8xxx_transmit(void) /* Test fail on transmitting BIST MODE 2 message */ i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, TCPC_REG_TRANSMIT); zassert_equal(EC_ERROR_INVAL, - ps8xxx_tcpm_drv.transmit(USBC_PORT_C1, - TCPCI_MSG_TX_BIST_MODE_2, 0, - NULL), NULL); + ps8xxx_tcpm_drv.transmit( + USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL), + NULL); i2c_common_emul_set_write_fail_reg(tcpci_i2c_emul, I2C_COMMON_EMUL_NO_FAIL_REG); /* Test sending BIST MODE 2 message */ exp_cnt = PS8751_BIST_COUNTER; zassert_equal(EC_SUCCESS, - ps8xxx_tcpm_drv.transmit(USBC_PORT_C1, - TCPCI_MSG_TX_BIST_MODE_2, 0, - NULL), NULL); + ps8xxx_tcpm_drv.transmit( + USBC_PORT_C1, TCPCI_MSG_TX_BIST_MODE_2, 0, NULL), + NULL); check_tcpci_reg(ps8xxx_emul, PS8XXX_REG_BIST_CONT_MODE_CTR, 0); zassert_equal(TCPCI_MSG_TX_BIST_MODE_2, msg->type, NULL); @@ -668,27 +664,29 @@ ZTEST(ps8805, test_ps8805_get_chip_info_fix_dev_id) ps8xxx_emul_set_chip_rev(ps8xxx_emul, test_param[i].chip_rev); /* Test correct device id after fixing */ - zassert_equal(EC_SUCCESS, - ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, - &info), - "Failed to get chip info in test case %d (chip_rev 0x%x)", - i, test_param[i].chip_rev); - zassert_equal(vendor, info.vendor_id, - "0x%x != (vendor = 0x%x) in test case %d (chip_rev 0x%x)", - vendor, info.vendor_id, - i, test_param[i].chip_rev); - zassert_equal(product, info.product_id, - "0x%x != (product = 0x%x) in test case %d (chip_rev 0x%x)", - product, info.product_id, - i, test_param[i].chip_rev); - zassert_equal(test_param[i].exp_dev_id, info.device_id, - "0x%x != (device = 0x%x) in test case %d (chip_rev 0x%x)", - test_param[i].exp_dev_id, info.device_id, - i, test_param[i].chip_rev); - zassert_equal(fw_rev, info.fw_version_number, - "0x%x != (FW rev = 0x%x) in test case %d (chip_rev 0x%x)", - fw_rev, info.fw_version_number, - i, test_param[i].chip_rev); + zassert_equal( + EC_SUCCESS, + ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info), + "Failed to get chip info in test case %d (chip_rev 0x%x)", + i, test_param[i].chip_rev); + zassert_equal( + vendor, info.vendor_id, + "0x%x != (vendor = 0x%x) in test case %d (chip_rev 0x%x)", + vendor, info.vendor_id, i, test_param[i].chip_rev); + zassert_equal( + product, info.product_id, + "0x%x != (product = 0x%x) in test case %d (chip_rev 0x%x)", + product, info.product_id, i, test_param[i].chip_rev); + zassert_equal( + test_param[i].exp_dev_id, info.device_id, + "0x%x != (device = 0x%x) in test case %d (chip_rev 0x%x)", + test_param[i].exp_dev_id, info.device_id, i, + test_param[i].chip_rev); + zassert_equal( + fw_rev, info.fw_version_number, + "0x%x != (FW rev = 0x%x) in test case %d (chip_rev 0x%x)", + fw_rev, info.fw_version_number, i, + test_param[i].chip_rev); } } @@ -759,26 +757,29 @@ ZTEST(ps8815, test_ps8815_get_chip_info_fix_dev_id) ps8xxx_emul_set_hw_rev(ps8xxx_emul, test_param[i].hw_rev); /* Test correct device id after fixing */ - zassert_equal(EC_SUCCESS, - ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, - &info), - "Failed to get chip info in test case %d (hw_rev 0x%x)", - i, test_param[i].hw_rev); - zassert_equal(vendor, info.vendor_id, - "0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)", - vendor, info.vendor_id, i, test_param[i].hw_rev); - zassert_equal(product, info.product_id, - "0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)", - product, info.product_id, - i, test_param[i].hw_rev); - zassert_equal(test_param[i].exp_dev_id, info.device_id, - "0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)", - test_param[i].exp_dev_id, info.device_id, - i, test_param[i].hw_rev); - zassert_equal(fw_rev, info.fw_version_number, - "0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)", - fw_rev, info.fw_version_number, - i, test_param[i].hw_rev); + zassert_equal( + EC_SUCCESS, + ps8xxx_tcpm_drv.get_chip_info(USBC_PORT_C1, 1, &info), + "Failed to get chip info in test case %d (hw_rev 0x%x)", + i, test_param[i].hw_rev); + zassert_equal( + vendor, info.vendor_id, + "0x%x != (vendor = 0x%x) in test case %d (hw_rev 0x%x)", + vendor, info.vendor_id, i, test_param[i].hw_rev); + zassert_equal( + product, info.product_id, + "0x%x != (product = 0x%x) in test case %d (hw_rev 0x%x)", + product, info.product_id, i, test_param[i].hw_rev); + zassert_equal( + test_param[i].exp_dev_id, info.device_id, + "0x%x != (device = 0x%x) in test case %d (hw_rev 0x%x)", + test_param[i].exp_dev_id, info.device_id, i, + test_param[i].hw_rev); + zassert_equal( + fw_rev, info.fw_version_number, + "0x%x != (FW rev = 0x%x) in test case %d (hw_rev 0x%x)", + fw_rev, info.fw_version_number, i, + test_param[i].hw_rev); } } @@ -855,7 +856,8 @@ ZTEST(ps8805, test_ps8805_gpio) NULL); zassert_equal(EC_ERROR_INVAL, ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_NUM, - &level), NULL); + &level), + NULL); /* Setup fail on gpio control reg read */ i2c_common_emul_set_read_fail_reg(gpio_i2c_emul, @@ -867,7 +869,8 @@ ZTEST(ps8805, test_ps8805_gpio) NULL); zassert_equal(EC_ERROR_INVAL, ps8805_gpio_get_level(USBC_PORT_C1, PS8805_GPIO_0, - &level), NULL); + &level), + NULL); /* Do not fail on gpio control reg read */ i2c_common_emul_set_read_fail_reg(gpio_i2c_emul, @@ -893,27 +896,30 @@ ZTEST(ps8805, test_ps8805_gpio) } else { exp_ctrl &= ~test_param[i].gpio_reg; } - zassert_equal(EC_SUCCESS, - ps8805_gpio_set_level(USBC_PORT_C1, - test_param[i].signal, - test_param[i].level), - "Failed gpio_set in test case %d (gpio %d, level %d)", - i, test_param[i].signal, test_param[i].level); - zassert_equal(EC_SUCCESS, - ps8805_gpio_get_level(USBC_PORT_C1, - test_param[i].signal, - &level), - "Failed gpio_get in test case %d (gpio %d, level %d)", - i, test_param[i].signal, test_param[i].level); - zassert_equal(test_param[i].level, level, - "%d != (gpio_get_level = %d) in test case %d (gpio %d, level %d)", - test_param[i].level, level, i, - test_param[i].signal, test_param[i].level); + zassert_equal( + EC_SUCCESS, + ps8805_gpio_set_level(USBC_PORT_C1, + test_param[i].signal, + test_param[i].level), + "Failed gpio_set in test case %d (gpio %d, level %d)", + i, test_param[i].signal, test_param[i].level); + zassert_equal( + EC_SUCCESS, + ps8805_gpio_get_level(USBC_PORT_C1, + test_param[i].signal, &level), + "Failed gpio_get in test case %d (gpio %d, level %d)", + i, test_param[i].signal, test_param[i].level); + zassert_equal( + test_param[i].level, level, + "%d != (gpio_get_level = %d) in test case %d (gpio %d, level %d)", + test_param[i].level, level, i, test_param[i].signal, + test_param[i].level); gpio_ctrl = ps8xxx_emul_get_gpio_ctrl(ps8xxx_emul); - zassert_equal(exp_ctrl, gpio_ctrl, - "0x%x != (gpio_ctrl = 0x%x) in test case %d (gpio %d, level %d)", - exp_ctrl, gpio_ctrl, i, test_param[i].signal, - test_param[i].level); + zassert_equal( + exp_ctrl, gpio_ctrl, + "0x%x != (gpio_ctrl = 0x%x) in test case %d (gpio %d, level %d)", + exp_ctrl, gpio_ctrl, i, test_param[i].signal, + test_param[i].level); } } @@ -1125,7 +1131,7 @@ static void test_ps8xxx_tcpci_low_power_mode(void) * don't have it. Stub it out for PS8751/PS8815. */ if (board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8751_PRODUCT_ID || - board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID) + board_get_ps8xxx_product_id(USBC_PORT_C1) == PS8815_PRODUCT_ID) return; test_tcpci_low_power_mode(ps8xxx_emul, USBC_PORT_C1); } @@ -1225,7 +1231,6 @@ static void ps8815_before(void *state) setup_no_fail_all(); } - ZTEST_SUITE(ps8805, drivers_predicate_post_main, NULL, ps8805_before, NULL, NULL); -- cgit v1.2.1 From d2c45a29c38195a7bc9ae63073eec699805fab7b Mon Sep 17 00:00:00 2001 From: Brandon Breitenstein Date: Thu, 23 Jun 2022 15:41:45 -0700 Subject: zephyr: mtlrvp: Enable USB Type-C on Cypress AIC MTLRVP has a USB addin card that utilizes Cypress TCPC. Enable the I/O Expander ports and GPIO needed for Cypress ports to function. BUG=b:229073490 BRANCH=none TEST=zmake mtlrvpp_npcx verified USB4, TBT, USB, and DP Signed-off-by: Brandon Breitenstein Change-Id: Ib3d058c09ed3b49779a769460c2276f1b0713811 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3600141 Tested-by: Vijay P Hiremath Reviewed-by: Aaron Massey Commit-Queue: Aaron Massey --- zephyr/dts/bindings/gpio/gpio-enum-name.yaml | 4 ++ zephyr/projects/intelrvp/mtlrvp/ioex.dts | 38 +++++++++++ .../projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts | 32 +++++++++ .../intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts | 10 +++ .../intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts | 8 +-- zephyr/projects/intelrvp/mtlrvp/prj.conf | 8 +++ zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c | 76 +++++++++++++++++++++- zephyr/projects/intelrvp/mtlrvp/usbc.dts | 46 +++++++++++++ 8 files changed, 216 insertions(+), 6 deletions(-) diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml index 0984e1cdf2..8252ca75e1 100644 --- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml +++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml @@ -157,7 +157,11 @@ properties: - IOEX_USB_C1_TCPC_FASTSW_CTL_EN - IOEX_USB_C2_BB_RETIMER_LS_EN - IOEX_USB_C2_BB_RETIMER_RST + - IOEX_USB_C2_HBR_RST + - IOEX_USB_C2_HBR_LS_EN - IOEX_USB_C2_C3_OC - IOEX_USB_C2_FRS_EN - IOEX_USB_C3_BB_RETIMER_LS_EN - IOEX_USB_C3_BB_RETIMER_RST + - IOEX_USB_C3_HBR_RST + - IOEX_USB_C3_HBR_LS_EN diff --git a/zephyr/projects/intelrvp/mtlrvp/ioex.dts b/zephyr/projects/intelrvp/mtlrvp/ioex.dts index bf79b12570..ea957d02b9 100644 --- a/zephyr/projects/intelrvp/mtlrvp/ioex.dts +++ b/zephyr/projects/intelrvp/mtlrvp/ioex.dts @@ -30,4 +30,42 @@ ngpios = <8>; }; }; + /* IOEX_C2_CCGXXF */ + ioex-c2 { + compatible = "cros,ioex-chip"; + i2c-port = <&typec_aic2>; + i2c-addr = <0x0B>; + drv = "ccgxxf_ioexpander_drv"; + flags = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + ioex_c2_port0: ioex-c2-port@0 { + compatible = "cros,ioex-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port1: ioex-c2-port@1 { + compatible = "cros,ioex-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port2: ioex-c2-port@2 { + compatible = "cros,ioex-port"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + ioex_c2_port3: ioex-c2-port@3 { + compatible = "cros,ioex-port"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts index 86143fdd7a..ea05776d70 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/gpio.dts @@ -326,6 +326,38 @@ gpios = <&ioex_c1 6 GPIO_INPUT>; no-auto-init; }; + dg-bssb-sbu-sel { + gpios = <&ioex_c2_port1 4 GPIO_INPUT>; + no-auto-init; + }; + usb_c2_hb_retimer_rst: usb-c2-hbr-rst { + gpios = <&ioex_c2_port1 1 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_RST"; + no-auto-init; + }; + usb_c2_hb_retimer_ls_en: usb-c2-hbr-ls-en { + gpios = <&ioex_c2_port2 0 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C2_HBR_LS_EN"; + no-auto-init; + }; + usb_c3_hb_retimer_rst: usb-c3-hbr-rst { + gpios = <&ioex_c2_port1 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_RST"; + no-auto-init; + }; + usb_c3_hb_retimer_ls_en: usb-c3-hbr-ls-en { + gpios = <&ioex_c2_port3 3 (GPIO_ODR_LOW | \ + GPIO_VOLTAGE_1P8)>; + enum-name = "IOEX_USB_C3_HBR_LS_EN"; + no-auto-init; + }; + usb-c2-c3-prochot-n { + gpios = <&ioex_c2_port0 0 GPIO_INPUT>; + no-auto-init; + }; /* unimplemented GPIOs */ en-pp5000 { enum-name = "GPIO_EN_PP5000"; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts index 9d081527fb..dcbfa9e93e 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/interrupts.dts @@ -41,6 +41,16 @@ flags = ; handler = "ppc_interrupt"; }; + int_usb_c2_tcpc: usb_c2_tcpc { + irq-pin = <&usbc_tcpc_alrt_p2>; + flags = ; + handler = "tcpc_alert_event"; + }; + int_usb_c3_tcpc: usb_c3_tcpc { + irq-pin = <&usbc_tcpc_alrt_p3>; + flags = ; + handler = "tcpc_alert_event"; + }; int_ccd_mode: ccd_mode { irq-pin = <&ccd_mode_odl>; flags = ; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts index 4c2e18c2ba..6c41c67b4f 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts @@ -45,7 +45,7 @@ enum-name = "I2C_PORT_TYPEC_AIC_1"; }; typec_aic2: typec-aic2{ - i2c-port = <&i2c2_0>; + i2c-port = <&i2c1_0>; enum-name = "I2C_PORT_TYPEC_AIC_2"; }; }; @@ -150,14 +150,14 @@ }; /* typec_aic2 */ -&i2c2_0 { +&i2c1_0 { status = "okay"; clock-frequency = ; - pinctrl-0 = <&i2c2_0_sda_scl_gp91_92>; + pinctrl-0 = <&i2c1_0_sda_scl_gp87_90>; pinctrl-names = "default"; }; -&i2c_ctrl2 { +&i2c_ctrl1 { status = "okay"; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/prj.conf b/zephyr/projects/intelrvp/mtlrvp/prj.conf index 04397c8fc9..714ae7764e 100644 --- a/zephyr/projects/intelrvp/mtlrvp/prj.conf +++ b/zephyr/projects/intelrvp/mtlrvp/prj.conf @@ -34,6 +34,7 @@ CONFIG_PLATFORM_EC_DEDICATED_CHARGE_PORT=y # IOEX CONFIG_PLATFORM_EC_IOEX_CROS_DRV=y +CONFIG_PLATFORM_EC_IOEX_CCGXXF=y CONFIG_GPIO_PCA95XX=y CONFIG_GPIO_NCT38XX=y CONFIG_PLATFORM_EC_IOEX_IT8801=y @@ -52,12 +53,19 @@ CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y CONFIG_PLATFORM_EC_USB_MUX_VIRTUAL=y CONFIG_PLATFORM_EC_USB_MUX_TASK=y CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y +CONFIG_PLATFORM_EC_USBC_PPC=y CONFIG_PLATFORM_EC_USB_PD_PPC=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_PPC=y +CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y +CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_TCPC=y +CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_TCPCI=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF=y CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX=y CONFIG_PLATFORM_EC_USB_PD_TCPM_MUX=y CONFIG_PLATFORM_EC_USB_PD_TRY_SRC=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_SBU=y CONFIG_PLATFORM_EC_USB_PD_DUAL_ROLE_AUTO_TOGGLE=y CONFIG_PLATFORM_EC_USBC_RETIMER_INTEL_HB=y CONFIG_PLATFORM_EC_USBC_VCONN=y diff --git a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c index 7d382da318..50dffef90b 100644 --- a/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c +++ b/zephyr/projects/intelrvp/mtlrvp/src/mtlrvp.c @@ -9,7 +9,9 @@ #include "common.h" #include "console.h" #include "driver/retimer/bb_retimer_public.h" +#include "driver/tcpm/ccgxxf.h" #include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/tcpci.h" #include "extpower.h" #include "gpio.h" #include "gpio/gpio_int.h" @@ -39,8 +41,25 @@ #define I2C_ADDR_SN5S330_P0 0x40 #define I2C_ADDR_SN5S330_P1 0x41 +/* IOEX ports */ +enum ioex_port { + IOEX_KBD = 0, +#if defined(HAS_TASK_PD_C2) + IOEX_C2_CCGXXF, +#endif + IOEX_COUNT +}; + /* USB-C ports */ -enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +enum usbc_port { + USBC_PORT_C0 = 0, + USBC_PORT_C1, +#if defined(HAS_TASK_PD_C2) + USBC_PORT_C2, + USBC_PORT_C3, +#endif + USBC_PORT_COUNT +}; BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); /* USB-C PPC configuration */ @@ -56,7 +75,6 @@ struct ppc_config_t ppc_chips[] = { .drv = &sn5s330_drv, }, }; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* TCPC AIC GPIO Configuration */ @@ -71,6 +89,16 @@ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = { .ppc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_ppc_alrt_p1)), .ppc_intr_handler = sn5s330_interrupt, }, +#if defined(HAS_TASK_PD_C2) + [USBC_PORT_C2] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p2)), + /* No PPC alert for CCGXXF */ + }, + [USBC_PORT_C3] = { + .tcpc_alert = GPIO_SIGNAL(DT_NODELABEL(usbc_tcpc_alrt_p3)), + /* No PPC alert for CCGXXF */ + }, +#endif }; BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT); @@ -125,6 +153,14 @@ void board_reset_pd_mcu(void) /* NCT38XX chip uses gpio ioex */ gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c0))); gpio_reset_port(DEVICE_DT_GET(DT_NODELABEL(ioex_c1))); + +#if defined(HAS_TASK_PD_C2) + /* Reset the ccgxxf ports only resetting 1 is required */ + ccgxxf_reset(USBC_PORT_C2); + + /* CCGXXF has ioex on port 2 */ + ioex_init(IOEX_C2_CCGXXF); +#endif } void board_connect_c0_sbu(enum gpio_signal signal) @@ -232,6 +268,10 @@ static void board_int_init(void) /* Enable TCPC interrupts. */ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_tcpc)); +#if defined(HAS_TASK_PD_C2) + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c2_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c3_tcpc)); +#endif /* Enable CCD Mode interrupt */ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_ccd_mode)); @@ -257,3 +297,35 @@ static int board_pre_task_peripheral_init(const struct device *unused) } SYS_INIT(board_pre_task_peripheral_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY); + +/* + * Since MTLRVP has both PPC and TCPC ports override to check if the port + * is a PPC or non PPC port + */ +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + if (!board_port_has_ppc(port)) { + return tcpm_check_vbus_level(port, level); + } else if (level == VBUS_PRESENT) { + return pd_snk_is_vbus_provided(port); + } else { + return !pd_snk_is_vbus_provided(port); + } +} + +__override bool board_port_has_ppc(int port) +{ + bool ppc_port; + + switch (port) { + case USBC_PORT_C0: + case USBC_PORT_C1: + ppc_port = true; + break; + default: + ppc_port = false; + break; + } + + return ppc_port; +} diff --git a/zephyr/projects/intelrvp/mtlrvp/usbc.dts b/zephyr/projects/intelrvp/mtlrvp/usbc.dts index a07c3853aa..60831a043c 100644 --- a/zephyr/projects/intelrvp/mtlrvp/usbc.dts +++ b/zephyr/projects/intelrvp/mtlrvp/usbc.dts @@ -66,5 +66,51 @@ compatible = "cros-ec,usbc-mux-virtual"; }; }; + + usbc_port2: port2@2 { + compatible = "named-usbc-port"; + reg = <2>; + tcpc { + compatible = "cypress,ccgxxf"; + port = <&typec_aic2>; + i2c-addr-flags = "CCGXXF_I2C_ADDR1_FLAGS"; + }; + usb-muxes = <&usb_c2_hb_retimer &virtual_mux_c2>; + }; + port2-muxes { + usb_c2_hb_retimer: jhl8040r-c2 { + compatible = "intel,jhl8040r"; + port = <&typec_aic2>; + i2c-addr-flags = <0x58>; + reset-pin = <&usb_c2_hb_retimer_rst>; + ls-en-pin = <&usb_c2_hb_retimer_ls_en>; + }; + virtual_mux_c2: virtual-mux-c2 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + + usbc_port3: port3@3 { + compatible = "named-usbc-port"; + reg = <3>; + tcpc { + compatible = "cypress,ccgxxf"; + port = <&typec_aic2>; + i2c-addr-flags = "CCGXXF_I2C_ADDR2_FLAGS"; + }; + usb-muxes = <&usb_c3_hb_retimer &virtual_mux_c3>; + }; + port3-muxes { + usb_c3_hb_retimer: jhl8040r-c3 { + compatible = "intel,jhl8040r"; + port = <&typec_aic2>; + i2c-addr-flags = <0x59>; + reset-pin = <&usb_c3_hb_retimer_rst>; + ls-en-pin = <&usb_c3_hb_retimer_ls_en>; + }; + virtual_mux_c3: virtual-mux-c3 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; }; }; -- cgit v1.2.1 From 27ace7a6a83eb44bd153a02fe0dd5c339dd0b955 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 8 Jul 2022 10:51:16 -0600 Subject: ec: Adjust config files for python formatting To support formatting all python files with black, isort, and flake8, move some settings from the zmake dir to the root dir. Removed isort from zmake/run_tests.sh, because moving the .isort.cfg confused it, and it needs to be removed anyway. BRANCH=None BUG=b:238434058 TEST=None Signed-off-by: Jeremy Bettis Change-Id: I30d98015a56022ad9f95fdb3b0a7ed6c4bf24094 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749241 Auto-Submit: Jeremy Bettis Commit-Queue: Jack Rosenthal Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis Tested-by: Jeremy Bettis --- .flake8 | 9 ++ .isort.cfg | 2 + pylintrc | 354 +--------------------------------------------- zephyr/projects/.pylintrc | 10 +- zephyr/test/.pylintrc | 10 +- zephyr/zmake/.flake8 | 9 -- zephyr/zmake/.isort.cfg | 2 - zephyr/zmake/.pylintrc | 7 +- zephyr/zmake/run_tests.sh | 3 - 9 files changed, 19 insertions(+), 387 deletions(-) create mode 100644 .flake8 create mode 100644 .isort.cfg delete mode 100644 zephyr/zmake/.flake8 delete mode 100644 zephyr/zmake/.isort.cfg diff --git a/.flake8 b/.flake8 new file mode 100644 index 0000000000..0a0a9c29ab --- /dev/null +++ b/.flake8 @@ -0,0 +1,9 @@ +[flake8] +max-line-length = 88 +extend-ignore = E203 +exclude = + .hypothesis, + .pytest_cache, + __pycache__, + build, + dist diff --git a/.isort.cfg b/.isort.cfg new file mode 100644 index 0000000000..b9fb3f3e8c --- /dev/null +++ b/.isort.cfg @@ -0,0 +1,2 @@ +[settings] +profile=black diff --git a/pylintrc b/pylintrc index 9ec7f3c61a..51f1236221 100644 --- a/pylintrc +++ b/pylintrc @@ -1,358 +1,14 @@ # Copyright 2021 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# This file is copied Chromium OS platform2, as seen in the following link: -# https://chromium.googlesource.com/chromiumos/platform2/+/HEAD/pylintrc -# Please keep in sync. - -# NB: This is a fork of chromite/pylintrc with indent set to 4. -# Everything else is kept the same. - -[MASTER] - -# Add files or directories matching the regex patterns to the ignore list. -# The regex matches against base names, not paths. -ignore-patterns= - .*_pb2\.py$, - .*third_party\/.*.py$ - - -# List of plugins (as comma separated values of python modules names) to load, -# usually to register additional checkers. -load-plugins= - chromite.cli.cros.lint, - pylint.extensions.bad_builtin, - pylint.extensions.docstyle, - pylint.extensions.redefined_variable_type, - pylint.extensions.overlapping_exceptions, - -# Configure quote preferences. -string-quote = single-avoid-escape -triple-quote = double -docstring-quote = double +# Changes to make pylint and black agree on the formatting. [MESSAGES CONTROL] -# Enable the message, report, category or checker with the given id(s). You can -# either give multiple identifier separated by comma (,) or put this option -# multiple times. -# eq-without-hash: We omit this as we don't require all objects be hashable. -# We'll wait for unittest coverage to detect missing __hash__ on objects. -# no-absolute-import: We don't seem to rely on this behavior, so don't enforce -# using this future import everywhere. -# round-builtin: We omit this as all our usage of round() is OK with either -# Python 2 or 3 behavior (and probably leans towards 3 anyways). -enable= - apply-builtin, - backtick, - bad-python3-import, - basestring-builtin, - buffer-builtin, - cmp-builtin, - cmp-method, - coerce-builtin, - coerce-method, - delslice-method, - deprecated-itertools-function, - deprecated-str-translate-call, - deprecated-string-function, - deprecated-types-field, - dict-items-not-iterating, - dict-iter-method, - dict-keys-not-iterating, - dict-values-not-iterating, - dict-view-method, - div-method, - exception-message-attribute, - execfile-builtin, - file-builtin, - filter-builtin-not-iterating, - getslice-method, - hex-method, - idiv-method, - import-star-module-level, - indexing-exception, - intern-builtin, - invalid-str-codec, - long-builtin, - long-suffix, - map-builtin-not-iterating, - metaclass-assignment, - next-method-called, - next-method-defined, - nonzero-method, - oct-method, - old-ne-operator, - old-octal-literal, - old-raise-syntax, - parameter-unpacking, - print-statement, - raising-string, - range-builtin-not-iterating, - raw_input-builtin, - rdiv-method, - reduce-builtin, - reload-builtin, - setslice-method, - standarderror-builtin, - sys-max-int, - unichr-builtin, - unicode-builtin, - unpacking-in-except, - using-cmp-argument, - xrange-builtin, - zip-builtin-not-iterating, - - -# Disable the message, report, category or checker with the given id(s). You -# can either give multiple identifiers separated by comma (,) or put this -# option multiple times (only on the command line, not in the configuration -# file where it should appear only once). You can also use "--disable=all" to -# disable everything first and then reenable specific checks. For example, if -# you want to run only the similarities checker, you can use "--disable=all -# --enable=similarities". If you want to run only the classes checker, but have -# no Warning level messages displayed, use "--disable=all --enable=classes -# --disable=W". -# We leave many of the style warnings to judgement/peer review. -# TODO: We need to re-enable broad-except, but requires cleaning up our code. -# TODO: Re-enable redefined-variable-type. -# TODO: Re-enable inconsistent-return-statements. -# TODO: Re-enable keyword-arg-before-vararg once we're on Python 3-only. -# TODO: Re-enable useless-object-inheritance once we're on Python 3-only and -# we update the style guide. -# TODO: Re-enable import-outside-toplevel. -# TODO: Re-enable unnecessary-comprehension. -# TODO: Re-enable consider-using-dict-comprehension. -# TODO: Re-enable consider-using-set-comprehension. -# TODO: Re-enable consider-using-in. -# TODO: Re-enable try-except-raise. -# TODO: Re-enable chained-comparison. -disable= - broad-except, - chained-comparison, - consider-iterating-dictionary, - consider-using-dict-comprehension, - consider-using-in, - consider-using-set-comprehension, - fixme, - file-ignored, - keyword-arg-before-vararg, - import-outside-toplevel, - inconsistent-return-statements, - invalid-name, - locally-disabled, - locally-enabled, - missing-docstring, - no-member, - no-else-break, - no-else-continue, - no-else-raise, - no-else-return, - no-self-use, - raise-missing-from, - redefined-variable-type, - relative-import, - super-with-arguments, - too-few-public-methods, - too-many-arguments, - too-many-boolean-expressions, - too-many-branches, - too-many-instance-attributes, - too-many-lines, - too-many-locals, - too-many-nested-blocks, - too-many-public-methods, - too-many-return-statements, - too-many-statements, - try-except-raise, - unnecessary-comprehension, - useless-object-inheritance, - - -[REPORTS] - -# Tells whether to display a full report or only the messages -# CHANGE: No report. -reports=no - -# Activate the evaluation score. -score=no - - -[FORMAT] - -# Maximum number of characters on a single line. -max-line-length=80 - -# Disable line length enforcement for import statements or comment lines -# containing URLs. -ignore-long-lines=(^(import|from))|(^\s*(# )??$) - -# Maximum number of lines in a module -#max-module-lines=1000 - -# String used as indentation unit. This is usually " " (4 spaces) or "\t" (1 -# tab). -indent-string=' ' - - -[TYPECHECK] - -# List of classes names for which member attributes should not be checked -# (useful for classes with attributes dynamically set). -ignored-classes=hashlib,numpy - -# List of members which are set dynamically and missed by pylint inference -# system, and so shouldn't trigger E0201 when accessed. -# CHANGE: Added tempdir for @osutils.TempDirDecorator. -generated-members=REQUEST,acl_users,aq_parent,tempdir - -# List of modules for which member attributes should not be checked. -# Modules listed here will not trigger import errors even if the linter can't -# import them. -# -# pytest: Made available by our testing virtualenv and can be assumed exists. -ignored-modules=pytest - -[BASIC] - -# List of builtins function names that should not be used, separated by a comma. -# exit & quit are for the interactive interpreter shell only. -# https://docs.python.org/3/library/constants.html#constants-added-by-the-site-module -bad-functions= - apply, - exit, - filter, - map, - quit, - reduce, - -# Regular expression which should only match correct function names -# -# CHANGE: The ChromiumOS standard is different than PEP-8, so we need to -# redefine this. -# -# Common exceptions to ChromiumOS standard: -# - main: Standard for main function -function-rgx=([A-Z_][a-zA-Z0-9]{2,30}|main)$ - -# Regular expression which should only match correct method names -# -# CHANGE: The ChromiumOS standard is different than PEP-8, so we need to -# redefine this. Here's what we allow: -# - CamelCaps, starting with a capital letter. No underscores in function -# names. Can also have a "_" prefix (private method) or a "test" prefix -# (unit test). -# - Methods that look like __xyz__, which are used to do things like -# __init__, __del__, etc. -# - setUp, tearDown: For unit tests. -method-rgx=((_|test)?[A-Z][a-zA-Z0-9]{2,30}|__[a-z]+__|setUp|tearDown)$ - - -[SIMILARITIES] - -# Minimum lines number of a similarity. -min-similarity-lines=20 - - -[VARIABLES] - -# A regular expression matching the beginning of the name of dummy variables -# (i.e. not used). -dummy-variables-rgx=_|unused_ - - -[DESIGN] - -# Maximum number of parents for a class (see R0901). -max-parents=10 - - -[IMPORTS] - -# Deprecated modules which should not be used, separated by a comma. -# __builtin__: Use the 'six.moves.builtins' module instead -# (or 'builtins' in Python 3). -# apiclient: Use the 'googleapiclient' module instead. -# Bastion: Dropped in Python 3. -# ConfigParser: Use the 'six.moves.configparser' module instead -# (or 'configparser' in Python 3). -# cookielib: Use the 'six.moves.http_cookiejar' module instead -# (or 'http.cookiejar' in Python 3). -# cPickle: Use the 'pickle' module instead. -# cStringIO: Use 'io.StringIO' or 'io.BytesIO' instead. -# exceptions: Dropped in Python 3. -# HTMLParser: Use the 'six.moves.html_parser' module instead -# (or 'html.parser' in Python 3). -# httplib: Use the 'six.moves.http_client' module instead -# (or 'http.client' in Python 3). -# md5: Use the 'hashlib' module instead. -# mox: Use the 'mock' module instead. -# optparse: Use the 'argparse' module instead. -# Queue: Use the 'six.moves.queue' module instead (or 'queue' in Python 3). -# regsub: Use the 're' module instead. -# rexec: Dropped in Python 3. -# StringIO: Use 'io.StringIO' or 'io.BytesIO' instead. -# TERMIOS: Use the 'termios' module instead. -# urllib2: Use the 'six.moves.urllib' module instead -# (or 'urllib.request' in Python 3). -# urlparse: Use the 'six.moves.urllib' module instead -# (or 'urllib.parse' in Python 3). -deprecated-modules= - __builtin__, - apiclient, - Bastion, - ConfigParser, - cookielib, - cPickle, - cStringIO, - exceptions, - HTMLParser, - httplib, - md5, - mock, - mox, - optparse, - Queue, - regsub, - rexec, - StringIO, - TERMIOS, - urllib2, - urlparse, - -# Force import order to recognize a module as part of the standard -# compatibility libraries. -known-standard-library= - -# Force import order to recognize a module as part of a third party library. -known-third-party= - _emerge, - apiclient, - elftools, - gcloud, - google, - googleapiclient, - httplib2, - jinja2, - jsonschema, - lddtree, - magic, - mock, - oauth2client, - portage, - pylint, - pytest, - requests, - six, - sqlalchemy, - yaml, - +disable=bad-continuation,bad-whitespace -[LOGGING] +[format] -# Apply logging string format checks to calls on these modules. -logging-modules= - logging, +max-line-length=88 +string-quote=double diff --git a/zephyr/projects/.pylintrc b/zephyr/projects/.pylintrc index 9ca0b5f8c9..62896b8eae 100644 --- a/zephyr/projects/.pylintrc +++ b/zephyr/projects/.pylintrc @@ -1,14 +1,6 @@ -[MASTER] -init-hook='import sys; sys.path.append("/usr/lib64/python3.6/site-packages")' - [MESSAGES CONTROL] -disable=bad-continuation,bad-whitespace,format,fixme - -[format] - -max-line-length=88 -string-quote=double +disable=format,fixme [BASIC] additional-builtins= diff --git a/zephyr/test/.pylintrc b/zephyr/test/.pylintrc index 9ca0b5f8c9..62896b8eae 100644 --- a/zephyr/test/.pylintrc +++ b/zephyr/test/.pylintrc @@ -1,14 +1,6 @@ -[MASTER] -init-hook='import sys; sys.path.append("/usr/lib64/python3.6/site-packages")' - [MESSAGES CONTROL] -disable=bad-continuation,bad-whitespace,format,fixme - -[format] - -max-line-length=88 -string-quote=double +disable=format,fixme [BASIC] additional-builtins= diff --git a/zephyr/zmake/.flake8 b/zephyr/zmake/.flake8 deleted file mode 100644 index 0a0a9c29ab..0000000000 --- a/zephyr/zmake/.flake8 +++ /dev/null @@ -1,9 +0,0 @@ -[flake8] -max-line-length = 88 -extend-ignore = E203 -exclude = - .hypothesis, - .pytest_cache, - __pycache__, - build, - dist diff --git a/zephyr/zmake/.isort.cfg b/zephyr/zmake/.isort.cfg deleted file mode 100644 index b9fb3f3e8c..0000000000 --- a/zephyr/zmake/.isort.cfg +++ /dev/null @@ -1,2 +0,0 @@ -[settings] -profile=black diff --git a/zephyr/zmake/.pylintrc b/zephyr/zmake/.pylintrc index a33a1fde1c..1f6856615d 100644 --- a/zephyr/zmake/.pylintrc +++ b/zephyr/zmake/.pylintrc @@ -3,12 +3,7 @@ init-hook='import sys; sys.path.extend(["zephyr/zmake"])' [MESSAGES CONTROL] -disable=bad-continuation,bad-whitespace,format,fixme,wrong-import-order - -[format] - -max-line-length=88 -string-quote=double +disable=format,fixme,wrong-import-order [BASIC] good-names= diff --git a/zephyr/zmake/run_tests.sh b/zephyr/zmake/run_tests.sh index 4796704440..0015614c23 100755 --- a/zephyr/zmake/run_tests.sh +++ b/zephyr/zmake/run_tests.sh @@ -25,9 +25,6 @@ export PYTHONPATH="${PWD}" # happens. Remove this flag. pytest --hypothesis-profile=cq . -# Check import sorting. -isort --check . - # Check black formatting. black --check --diff . -- cgit v1.2.1 From 25be7c7b289e92d97d30af146ea99c66e698f1c5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Fri, 8 Jul 2022 14:26:59 -0600 Subject: firmware_builder: Enforce clang-format in CQ Add a new helper script to run clang-format on all files, and call it in the firmware builder scripts. BUG=b:236386294 BRANCH=none TEST=Ran util/check_clang_format.py ~> On ToT: no errors reported ~> Intentionally mess up a file: errors reported Signed-off-by: Jack Rosenthal Change-Id: Ibde2a4993527fd6f8f30dc25378fdd5f48416d7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751463 Reviewed-by: Jeremy Bettis --- firmware_builder.py | 3 +++ util/check_clang_format.py | 66 ++++++++++++++++++++++++++++++++++++++++++++++ zephyr/firmware_builder.py | 6 +++-- 3 files changed, 73 insertions(+), 2 deletions(-) create mode 100755 util/check_clang_format.py diff --git a/firmware_builder.py b/firmware_builder.py index 6b5d094edf..78b7614190 100755 --- a/firmware_builder.py +++ b/firmware_builder.py @@ -55,6 +55,9 @@ def build(opts): f.write(json_format.MessageToJson(metric_list)) return + ec_dir = pathlib.Path(__file__).parent + subprocess.run([ec_dir / "util" / "check_clang_format.py"], check=True) + cmd = ['make', 'buildall_only', f'-j{opts.cpus}'] print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) diff --git a/util/check_clang_format.py b/util/check_clang_format.py new file mode 100755 index 0000000000..72e30b46e0 --- /dev/null +++ b/util/check_clang_format.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Validate all C source is formatted with clang-format. + +This isn't very useful to users to call directly, but it is run it the +CQ. Most users will likely find out they forgot to clang-format by +the pre-upload checks. +""" + +import logging +import pathlib +import subprocess +import sys + +from chromite.lib import commandline + + +def main(argv=None): + parser = commandline.ArgumentParser() + parser.parse_args(argv) + + logging.info("Validating all code is formatted with clang-format.") + ec_dir = pathlib.Path(__file__).parent.parent + all_files = [ + ec_dir / path + for path in subprocess.run( + ["git", "ls-files", "-z"], + check=True, + cwd=ec_dir, + stdout=subprocess.PIPE, + encoding="utf-8", + ).stdout.split("\0") + if path + ] + + clang_format_files = [] + for path in all_files: + if not path.is_file() or path.is_symlink(): + continue + if "third_party" in path.parts: + continue + if path.name.endswith(".c") or path.name.endswith(".h"): + clang_format_files.append(path) + + result = subprocess.run( + ["clang-format", "--dry-run", *clang_format_files], + check=True, + cwd=ec_dir, + stderr=subprocess.PIPE, + encoding="utf-8", + ) + if result.stderr: + logging.error("All C source must be formatted with clang-format!") + for line in result.stderr.splitlines(): + logging.error("%s", line) + return 1 + + logging.info("No clang-format issues found!") + return 0 + + +if __name__ == "__main__": + sys.exit(main(sys.argv[1:])) diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index c8c34f02ae..f77e51d6c4 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -29,13 +29,15 @@ def build(opts): """Builds all Zephyr firmware targets""" metric_list = firmware_pb2.FwBuildMetricList() + zephyr_dir = pathlib.Path(__file__).parent + platform_ec = zephyr_dir.resolve().parent + subprocess.run([platform_ec / "util" / "check_clang_format.py"], check=True) + cmd = ['zmake', '-D', 'build', '-a'] if opts.code_coverage: cmd.append('--coverage') subprocess.run(cmd, cwd=pathlib.Path(__file__).parent, check=True) if not opts.code_coverage: - zephyr_dir = pathlib.Path(__file__).parent - platform_ec = zephyr_dir.resolve().parent for project in zmake.project.find_projects(zephyr_dir).values(): if project.config.is_test: continue -- cgit v1.2.1 From 7330f3feee15e93053e2794f22cc5f57517933f8 Mon Sep 17 00:00:00 2001 From: Jacky_Wang Date: Mon, 11 Jul 2022 14:45:55 +0800 Subject: Delbing: fix typo Correct the bit definition of Keyboard Type in cbi_ssfc.h. BUG=None BRANCH=firmware-volteer-13672.B TEST=make BOARD=delbin Signed-off-by: Jacky_Wang Change-Id: Ia6ff13ca72603608dbc969c274aefd2f42daffe1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752271 Reviewed-by: Kenny Pan Commit-Queue: Kenny Pan --- baseboard/volteer/cbi_ssfc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/baseboard/volteer/cbi_ssfc.h b/baseboard/volteer/cbi_ssfc.h index 125ecbcd0d..830c430f4a 100644 --- a/baseboard/volteer/cbi_ssfc.h +++ b/baseboard/volteer/cbi_ssfc.h @@ -41,7 +41,7 @@ enum ec_ssfc_lightbar { }; /* - * Keyboard Type (Bit 11) + * Keyboard Type (Bit 12) */ enum ec_ssfc_keyboard { SSFC_KEYBOARD_DEFAULT = 0, SSFC_KEYBOARD_GAMING = 1 }; -- cgit v1.2.1 From eb17561232434bacb156f35b4f07e041634c65a3 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Mon, 4 Jul 2022 16:50:27 +0800 Subject: zephyr: cleanup: it8xxx2: Remove the redefined configurations These configurations have been defined in: third_party/zephyr/ main/soc/riscv/riscv-ite/it8xxx2/Kconfig.defconfig.series https://github.com/zephyrproject-rtos/zephyr/blob/main/soc/riscv/riscv-ite/it8xxx2/Kconfig.defconfig.series Note: Clock driver has not been implemented yet, disable CONFIG_CLOCK_CONTROL. BUG=none BRANCH=none TEST=zmake build it8xxx2_evb --clobber zmake build krabby --clobber zmake build nereid --clobber Signed-off-by: Tim Lin Change-Id: I3c4b7dc559ef62fc9c32d83d1e949f7417d92bbf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3745104 Reviewed-by: Ting Shen --- zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig index 740910d5ab..8566c9cb5c 100644 --- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig @@ -17,14 +17,12 @@ CONFIG_PM_POLICY_CUSTOM=y # Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_UART_NS16550=y CONFIG_SHELL_TAB=y CONFIG_SHELL_TAB_AUTOCOMPLETION=y CONFIG_SHELL_HISTORY=y # GPIO Controller CONFIG_GPIO=y -CONFIG_GPIO_ITE_IT8XXX2=y # For IT81202, the GPIO group k/l are not brought out to pins, # so by default they can be set to pull down inputs. # However with the IT81302, they are available on pins, @@ -32,12 +30,13 @@ CONFIG_GPIO_ITE_IT8XXX2=y CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN=n # ADC Driver -CONFIG_ADC_ITE_IT8XXX2=y CONFIG_PLATFORM_EC_ADC=y CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 -# Clock configuration -CONFIG_CLOCK_CONTROL=y +# Clock Controller +CONFIG_CLOCK_CONTROL=n + +# Timer configuration CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 @@ -46,11 +45,9 @@ CONFIG_CROS_EC_HOOK_TICK_INTERVAL=500000 # Flash CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y -CONFIG_SOC_FLASH_ITE_IT8XXX2=y # I2C CONFIG_I2C=y -CONFIG_I2C_ITE_IT8XXX2=y # Power Button CONFIG_PLATFORM_EC_POWER_BUTTON=y @@ -58,15 +55,11 @@ CONFIG_PLATFORM_EC_POWER_BUTTON=y # PWM CONFIG_PWM=y CONFIG_PWM_SHELL=n -CONFIG_PWM_ITE_IT8XXX2=y # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# Timer configuration -CONFIG_ITE_IT8XXX2_TIMER=y - # WATCHDOG configuration CONFIG_WATCHDOG=y CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500 @@ -75,4 +68,3 @@ CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME=y # BBRAM CONFIG_BBRAM=y -CONFIG_BBRAM_IT8XXX2=y -- cgit v1.2.1 From dbdfbfc45b2b07ad85d834d32375fb7e8bdaa2a8 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Tue, 5 Jul 2022 15:18:55 +0800 Subject: zephyr: board: Move the configs to the project These configs should be declared by the project. Note: CONFIG_I2C and CONFIG_PLATFORM_EC_POWER_BUTTON have been declared in corsola\prj.conf and nissa\prj.conf CONFIG_PWM and CONFIG_PWM_SHELL have been declared in nissa\prj.conf BUG=none BRANCH=none TEST=zmake build it8xxx2_evb --clobber zmake build krabby --clobber zmake build nereid --clobber Signed-off-by: Tim Lin Change-Id: I10025248a7e842138b6f72787344037cb2a4d06b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3745105 Reviewed-by: Peter Marheine Reviewed-by: Eric Yilun Lin --- zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig | 10 ---------- zephyr/projects/corsola/prj_it81202_base.conf | 4 ++++ zephyr/projects/it8xxx2_evb/prj.conf | 10 ++++++++++ 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig index 8566c9cb5c..a0cbbf4046 100644 --- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig @@ -46,16 +46,6 @@ CONFIG_CROS_EC_HOOK_TICK_INTERVAL=500000 # Flash CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y -# I2C -CONFIG_I2C=y - -# Power Button -CONFIG_PLATFORM_EC_POWER_BUTTON=y - -# PWM -CONFIG_PWM=y -CONFIG_PWM_SHELL=n - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/zephyr/projects/corsola/prj_it81202_base.conf b/zephyr/projects/corsola/prj_it81202_base.conf index 7cef734904..a72fe30fdb 100644 --- a/zephyr/projects/corsola/prj_it81202_base.conf +++ b/zephyr/projects/corsola/prj_it81202_base.conf @@ -44,6 +44,10 @@ CONFIG_PLATFORM_EC_LED_DT=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y CONFIG_PLATFORM_EC_LED_ONOFF_STATES_BAT_LOW=10 +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + # Sensors CONFIG_PLATFORM_EC_MOTIONSENSE=y CONFIG_PLATFORM_EC_ACCEL_FIFO=y diff --git a/zephyr/projects/it8xxx2_evb/prj.conf b/zephyr/projects/it8xxx2_evb/prj.conf index bb9fb95d8f..43cf2ad996 100644 --- a/zephyr/projects/it8xxx2_evb/prj.conf +++ b/zephyr/projects/it8xxx2_evb/prj.conf @@ -19,6 +19,16 @@ CONFIG_LOG=y # Fan CONFIG_SENSOR=y +# I2C +CONFIG_I2C=y + +# PWM +CONFIG_PWM=y +CONFIG_PWM_SHELL=n + +# Power Button +CONFIG_PLATFORM_EC_POWER_BUTTON=y + # TODO(b:185202623): bring these features up CONFIG_PLATFORM_EC_BACKLIGHT_LID=n CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=n -- cgit v1.2.1 From 959e3100ec08be6ef5f78762e7d7e44347f91482 Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Thu, 7 Jul 2022 15:05:20 -0600 Subject: zephyr:test: Fix flaky tcs3400 test suite TCS3400 driver data needs to be restored before and after each test BUG=b:236967124 BRANCH=none TEST=zmake test test-drivers (shuffled) Signed-off-by: Al Semjonovs Change-Id: I1b523a3d2552862db6fde1689adcdb9c27ad6c47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751768 Reviewed-by: Yuval Peress --- zephyr/test/drivers/src/tcs3400.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/tcs3400.c b/zephyr/test/drivers/src/tcs3400.c index 33c476c4d1..d7fcface36 100644 --- a/zephyr/test/drivers/src/tcs3400.c +++ b/zephyr/test/drivers/src/tcs3400.c @@ -602,4 +602,35 @@ ZTEST_USER(tcs3400, test_tcs_set_range) zassert_equal(0x10000, ms->current_range, NULL); } -ZTEST_SUITE(tcs3400, drivers_predicate_post_main, NULL, NULL, NULL, NULL); +struct tcs3400_test_fixture { + struct als_drv_data_t drv_data; + struct tcs3400_rgb_drv_data_t rgb_drv_data; +}; + +static void tcs3400_before(void *state) +{ + struct tcs3400_test_fixture *f = state; + + f->drv_data = *TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]); + f->rgb_drv_data = + *TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]); +} + +static void tcs3400_after(void *state) +{ + struct tcs3400_test_fixture *f = state; + + *TCS3400_DRV_DATA(&motion_sensors[TCS_CLR_SENSOR_ID]) = f->drv_data; + *TCS3400_RGB_DRV_DATA(&motion_sensors[TCS_RGB_SENSOR_ID]) = + f->rgb_drv_data; +} + +static void *tcs3400_setup(void) +{ + static struct tcs3400_test_fixture tcs3400_fixture = { 0 }; + + return &tcs3400_fixture; +} + +ZTEST_SUITE(tcs3400, drivers_predicate_post_main, tcs3400_setup, tcs3400_before, + tcs3400_after, NULL); -- cgit v1.2.1 From 97b861dc7f994a20f7abacf4a2de7df7c7213c81 Mon Sep 17 00:00:00 2001 From: Firas Sammoura Date: Fri, 8 Jul 2022 20:43:06 +0000 Subject: util: Fix Resource Leak in parse_vidpid() Add a goto statement at the leak locations that transfers control to a cleanup label in parse_vidpid(). The cleanup label deallocates the momory that was previously allocated to the variable copy and returns the correct integer. BUG=b:233237490 BRANCH=None TEST=make buildall -j Signed-off-by: Firas Sammoura Change-Id: Ic6fe79f579450a121c63a9efabaeff803deec47a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749250 Commit-Queue: Tom Hughes Reviewed-by: Tom Hughes --- util/comm-usb.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/util/comm-usb.c b/util/comm-usb.c index 43ad95648f..232d39fe9e 100644 --- a/util/comm-usb.c +++ b/util/comm-usb.c @@ -138,24 +138,33 @@ int parse_vidpid(const char *input, uint16_t *vid_ptr, uint16_t *pid_ptr) { char *copy, *s, *e; + int ret = 1; + copy = strdup(input); s = strchr(copy, ':'); - if (!s) - return 0; + if (!s) { + ret = 0; + goto cleanup; + } *s++ = '\0'; e = NULL; *vid_ptr = strtoul(copy, &e, 16); - if (e && *e) - return 0; + if (e && *e) { + ret = 0; + goto cleanup; + } e = NULL; *pid_ptr = strtoul(s, &e, 16); - if (e && *e) - return 0; - - return 1; + if (e && *e) { + ret = 0; + goto cleanup; + } +cleanup: + free(copy); + return ret; } static libusb_device_handle *check_device(libusb_device *dev, uint16_t vid, -- cgit v1.2.1 From 93c2fd7df981f28e4de62de0f347a6706264368c Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Mon, 4 Jul 2022 14:22:48 +0800 Subject: osiris: Remove unused gpio define Remove GPIO73 input define BUG=b:235020065 BRANCH=none TEST=HW team confirmed IO voltage as expected Signed-off-by: Yu-An Chen Change-Id: Id0ae99bb4bb84f93d700f402826cac0fdec7d58d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742846 Reviewed-by: Boris Mittelberg Commit-Queue: Boris Mittelberg --- board/osiris/gpio.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc index 015647f995..ccea91cf28 100644 --- a/board/osiris/gpio.inc +++ b/board/osiris/gpio.inc @@ -74,7 +74,6 @@ GPIO(LED_1_L, PIN(C, 4), GPIO_OUT_HIGH) GPIO(LED_2_L, PIN(C, 3), GPIO_OUT_HIGH) GPIO(KYBL_EN, PIN(A, 7), GPIO_OUT_LOW) GPIO(AMP_PWR_EN, PIN(5, 7), GPIO_OUT_LOW) -GPIO(EC_FAN_TACH_2, PIN(7, 3), GPIO_INPUT) GPIO(RGB_KB_INT, PIN(5, 6), GPIO_INPUT) /* UART alternate functions */ -- cgit v1.2.1 From dadbc645d10330e5584aa3f569add4c9f7e13a1f Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Thu, 7 Jul 2022 20:45:40 +0000 Subject: usb_ppc: Add Config to Remove CPRINTS from ppc_prints This CL adds a config which can be used to remove the CPRINTS call from ppc_prints and ppc_err_prints which will reduce EC image size. BRANCH=None BUG=b:238348526 TEST=make try_build_boards Signed-off-by: Jameson Thies Change-Id: I5ba2d92c3cd09c4fb1172194ac0c6e33d19044aa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751769 Reviewed-by: Abe Levkoy --- common/usbc_ppc.c | 16 ++++++++-------- include/config.h | 3 +++ zephyr/Kconfig.usbc | 10 ++++++++++ zephyr/shim/include/config_chip.h | 5 +++++ 4 files changed, 26 insertions(+), 8 deletions(-) diff --git a/common/usbc_ppc.c b/common/usbc_ppc.c index aa462e3743..c22d3b862f 100644 --- a/common/usbc_ppc.c +++ b/common/usbc_ppc.c @@ -24,20 +24,20 @@ int ppc_prints(const char *string, int port) { -#ifndef TEST_BUILD - return CPRINTS("ppc p%d %s", port, string); -#else +#if defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) return 0; -#endif +#else + return CPRINTS("ppc p%d %s", port, string); +#endif /* defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */ } int ppc_err_prints(const char *string, int port, int error) { -#ifndef TEST_BUILD - return CPRINTS("ppc p%d %s (%d)", port, string, error); -#else +#if defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) return 0; -#endif +#else + return CPRINTS("ppc p%d %s (%d)", port, string, error); +#endif /* defined(TEST_BUILD) || !defined(CONFIG_USBC_PPC_LOGGING) */ } __overridable bool board_port_has_ppc(int port) diff --git a/include/config.h b/include/config.h index 70dc284a8f..0792391d7e 100644 --- a/include/config.h +++ b/include/config.h @@ -5071,6 +5071,9 @@ /* PPC has level interrupts and has a dedicated interrupt pin to check */ #undef CONFIG_USBC_PPC_DEDICATED_INT +/* Enable logging related to the PPC. Undefine to reduce EC image size */ +#define CONFIG_USBC_PPC_LOGGING + /* Support for USB type-c superspeed mux */ #undef CONFIG_USBC_SS_MUX diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc index cfee1172f4..1f5e0f2388 100644 --- a/zephyr/Kconfig.usbc +++ b/zephyr/Kconfig.usbc @@ -133,6 +133,16 @@ config PLATFORM_EC_CONSOLE_CMD_PPC_DUMP reference to the datasheet for the part this can help you figure out what is going on. +config PLATFORM_EC_USBC_PPC_LOGGING + bool "Enable PPC Related logging" + depends on PLATFORM_EC_USBC_PPC + default y + help + PPC drivers use two print functions for logging error messages + (ppc_prints and ppc_err_prints). Setting this config adds the + CPRINTS call to both of these function which will enable PPC + related logging but increase EC image size. + config PLATFORM_EC_USB_PD_TCPM_DRIVER_IT83XX bool "Enable IT83XX driver" depends on PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 102238be83..a47063f712 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -962,6 +962,11 @@ extern struct jump_data mock_jump_data; #define CONFIG_CMD_PPC_DUMP #endif +#undef CONFIG_USBC_PPC_LOGGING +#ifdef CONFIG_PLATFORM_EC_USBC_PPC_LOGGING +#define CONFIG_USBC_PPC_LOGGING +#endif + #undef CONFIG_CMD_TCPC_DUMP #ifdef CONFIG_PLATFORM_EC_CONSOLE_CMD_TCPC_DUMP #define CONFIG_CMD_TCPC_DUMP -- cgit v1.2.1 From 15e5211a4fddf5e472a8bc6688d2e4c5e0ee7dfc Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Fri, 8 Jul 2022 00:40:34 +0000 Subject: volteer: Free up flash space Volteer is currently running out of flash space which prevents new changes from landing in ToT. This CL will change remove PPC logging and the history command from the EC to save space which saves about 1,450 bytes Before 96 bytes in flash and 21600 bytes in RAM still available on volteer RO 204 bytes in flash and 21600 bytes in RAM still available on volteer RW After 1568 bytes in flash and 22272 bytes in RAM still available on volteer RO 1736 bytes in flash and 22272 bytes in RAM still available on volteer RW BRANCH=None BUG=b:238327657 TEST=make try_build_boards Signed-off-by: Jameson Thies Change-Id: I135ad8983eccf953e707182f63e60bdcbd47b7d8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3751555 Reviewed-by: Abe Levkoy --- board/volteer/board.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/volteer/board.h b/board/volteer/board.h index 473b3ad2eb..181e3c0667 100644 --- a/board/volteer/board.h +++ b/board/volteer/board.h @@ -98,6 +98,9 @@ #define CONFIG_USBC_PPC_SYV682X /* USBC port C1 */ #define CONFIG_USB_PD_FRS_PPC +/* Disable PPC logging to reduce EC image size */ +#undef CONFIG_USBC_PPC_LOGGING + /* BC 1.2 */ /* Volume Button feature */ @@ -176,6 +179,7 @@ #undef CONFIG_CMD_REGULATOR #undef CONFIG_CMD_USB_PD_CABLE #undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CONSOLE_HISTORY /* Disable volume button in ectool */ #undef CONFIG_HOSTCMD_BUTTON -- cgit v1.2.1 From c783d1ea2970421e3cd3527bf95279c55d10dfa4 Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Tue, 7 Jun 2022 12:47:00 -0600 Subject: flash_fp_mcu: fix FPMCU flashing on hatch-kernelnext Check kernel version and adjust GPIO pin numbers accordingly. BUG=b:232379446 BRANCH=None TEST= test on helios flashed with hatch-kernelnext scp util/flash_fp_mcu root@${DUT_HOSTNAME}:/usr/local/bin/flash_fp_mcu ssh ${DUT_HOSTNAME} flash_fp_mcu Signed-off-by: Josie Nordrum Change-Id: I19b4ee361a34e80b941be0cbe0e3b877fd96052d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3693056 Reviewed-by: Craig Hesling --- util/flash_fp_mcu | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index 7be55e9475..e61382c935 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -498,13 +498,25 @@ config_hatch() { # for pin name to number mapping. # Examine `cat /sys/kernel/debug/pinctrl/INT34BB:00/gpio-ranges` on a hatch # device to determine gpio number from pin number. - readonly GPIO_CHIP="gpiochip200" - # FPMCU RST_ODL is on GPP_A12 = 200 + 12 = 212 - readonly GPIO_NRST=212 - # FPMCU BOOT0 is on GPP_A22 = 200 + 22 = 222 - readonly GPIO_BOOT0=222 - # FP_PWR_EN is on GPP_C11 = 456 + (192 - 181) = 456 + 11 = 467 - readonly GPIO_PWREN=467 + + local gpiochip="gpiochip712" + # Support kernel version 4.x, 5.4 and 5.10 during transition to 5.15+ + match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && gpiochip="gpiochip200" + readonly GPIO_CHIP="${gpiochip}" + local offset=0 + # Support kernel version 4.x, 5.4 and 5.10 during transition to 5.15+ + # v4.4 has GPIOs that are offset by -512 + match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && offset=512 + + # FPMCU RST_ODL is on GPP_A12 = 712 + 12 = 724 + local gpionrst=724 + readonly GPIO_NRST=$(( gpionrst - offset )) + # FPMCU BOOT0 is on GPP_A22 = 712 + 22 = 734 + local gpioboot=734 + readonly GPIO_BOOT0=$(( gpioboot - offset )) + # FP_PWR_EN is on GPP_C11 = 968 + (192 - 181) = 968 + 11 = 979 + local gpiopwren=979 + readonly GPIO_PWREN=$(( gpiopwren - offset )) } config_herobrine() { -- cgit v1.2.1 From f877b4b8a462df91c4d1f9a526c5f7103edf37ea Mon Sep 17 00:00:00 2001 From: Josie Nordrum Date: Tue, 7 Jun 2022 16:12:24 -0600 Subject: flash_fp_mcu: fix FPMCU flashing on volteer-kernelnext Check kernel version and set GPIO numbers accordingly. BUG=b:234856729 BRANCH=None TEST= test on volteer flashed with volteer-kernelnext scp util/flash_fp_mcu root@${DUT_HOSTNAME}:/usr/local/bin/flash_fp_mcu ssh ${DUT_HOSTNAME} flash_fp_mcu Signed-off-by: Josie Nordrum Change-Id: I4558b0d7f5d39913c6fe744b2ce84407db9fa58e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3693868 Reviewed-by: Craig Hesling Reviewed-by: Bobby Casey --- util/flash_fp_mcu | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index e61382c935..5268f5e9ba 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -623,15 +623,26 @@ config_volteer() { # volteer device to determine gpio number from pin number. # For example: GPP_C23 is UART2_CTS which can be queried from EDS # the pin number is 194. From the gpio-ranges, the gpio value is - # 408 + (194-171) = 431 + # 920 + (194-171) = 943 - readonly GPIO_CHIP="gpiochip152" - # FPMCU RST_ODL is on GPP_C23 = 408 + (194 - 171) = 431 - readonly GPIO_NRST=431 - # FPMCU BOOT0 is on GPP_C22 = 408 + (193 - 171) = 430 - readonly GPIO_BOOT0=430 - # FP_PWR_EN is on GPP_A21 = 216 + (63 - 42) = 237 - readonly GPIO_PWREN=237 + local gpiochip="gpiochip664" + # Support kernel version 4.x, 5.4, 5.10 during transition to 5.15+ + match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\..))" && gpiochip="gpiochip152" + readonly GPIO_CHIP="${gpiochip}" + local offset=0 + # Support kernel version 4.x, 5.4, 5.10 during transition to 5.15+ + # v4.4 has GPIOs that are offset by -512 + match_kernel_regex "^((4\..)|(5\.4\.)|(5\.10\.))" && offset=512 + + # FPMCU RST_ODL is on GPP_C23 = 920 + (194 - 171) = 943 + local gpionrst=943 + readonly GPIO_NRST=$(( gpionrst - offset )) + # FPMCU BOOT0 is on GPP_C22 = 920 + (193 - 171) = 942 + local gpioboot=942 + readonly GPIO_BOOT0=$(( gpioboot - offset )) + # FP_PWR_EN is on GPP_A21 = 728 + (63 - 42) = 749 + local gpiopwren=749 + readonly GPIO_PWREN=$(( gpiopwren - offset )) } config_brya() { -- cgit v1.2.1 From e0fad9b5ffcaf2bc1b80771198bc1f6972191234 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Mon, 11 Jul 2022 15:37:14 -0700 Subject: rgbkbd: Fix response size for rgbkbd host command Default response size is set to 0 which breaks libec. Set the response size to sizeof(ec_response_rgbkbd) BRANCH=none BUG=none TEST=Test on Taniks Signed-off-by: Parth Malkan Change-Id: I6a4fc9795a920e3823372b252e2e4d073013c3d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756734 Reviewed-by: YH Lin Commit-Queue: YH Lin --- common/rgb_keyboard.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/common/rgb_keyboard.c b/common/rgb_keyboard.c index 2bb5464a7d..5d92da688c 100644 --- a/common/rgb_keyboard.c +++ b/common/rgb_keyboard.c @@ -533,8 +533,7 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) struct ec_response_rgbkbd *r = args->response; enum ec_status rv = EC_RES_SUCCESS; - /* Default value is 0 */ - args->response_size = 0; + args->response_size = sizeof(*r); if (rgbkbd_late_init()) return EC_RES_ERROR; @@ -553,7 +552,6 @@ static enum ec_status hc_rgbkbd(struct host_cmd_handler_args *args) rv = EC_RES_ERROR; break; case EC_RGBKBD_SUBCMD_GET_CONFIG: - args->response_size = sizeof(*r); r->rgbkbd_type = rgbkbd_type; break; default: -- cgit v1.2.1 From 3e58b71d7ad9417907f8bf02842f4e931b27f4c8 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Fri, 8 Jul 2022 11:40:51 +1000 Subject: ps8xxx: simplify Kconfig options for driver selection Introduce a PLATFORM_EC_USB_PD_TCPM_PS8XXX option that enables the ps8xxx driver, and have the options for individual chips select it. This reduces the number of statements for each chip, and makes it clear that the multi-chip support option is only relevant if at least one chip is enabled. BUG=b:236761058,b:237593618 TEST=Verified ps8xxx.c is still built on Nereid, and selected/implied options remain enabled with the PS8815 driver. BRANCH=none Change-Id: I6a2215e7496613fc5daada154497c2ba2ac5c44b Signed-off-by: Peter Marheine Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752184 Reviewed-by: Keith Short --- zephyr/CMakeLists.txt | 6 +---- zephyr/Kconfig.tcpm | 63 +++++++++++++++++++++++++++++---------------------- 2 files changed, 37 insertions(+), 32 deletions(-) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index b3eaefb2a3..60985762d4 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -481,11 +481,7 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_CCGXXF "${PLATFORM_EC}/driver/tcpm/ccgxxf.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_NCT38XX "${PLATFORM_EC}/driver/tcpm/nct38xx.c") -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751 - "${PLATFORM_EC}/driver/tcpm/ps8xxx.c") -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805 - "${PLATFORM_EC}/driver/tcpm/ps8xxx.c") -zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815 +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8XXX "${PLATFORM_EC}/driver/tcpm/ps8xxx.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USB_PD_TCPM_RAA489000 "${PLATFORM_EC}/driver/tcpm/raa489000.c") diff --git a/zephyr/Kconfig.tcpm b/zephyr/Kconfig.tcpm index 1e7d52358a..6aeb7cf3bb 100644 --- a/zephyr/Kconfig.tcpm +++ b/zephyr/Kconfig.tcpm @@ -79,27 +79,6 @@ config PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG factory. Without this, multiple EC images would need to be installed depending on the board. -config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX - bool "Support multiple PS8xxx devices" - help - PS8XXX-series chips are all supported by a single driver. Enable - this If a board with the same EC firmware is expected to support - multiple products here. Then enable the required PS8xxx options - below. - - In this case the board must provide a function to return the correct - product ID actually used by a particular board: - - uint16_t board_get_ps8xxx_product_id(int port) - - Supported return values are: - - PS8705_PRODUCT_ID - PS8751_PRODUCT_ID - PS8755_PRODUCT_ID - PS8805_PRODUCT_ID - PS8815_PRODUCT_ID - config PLATFORM_EC_USB_PD_TCPM_ANX7447 bool "Analogix ANX7447 USB-C Gen 2 Type-C Port Controller" select PLATFORM_EC_USB_PD_TCPM_MUX @@ -150,10 +129,42 @@ config PLATFORM_EC_USB_PD_TCPM_NCT38XX (TCPC). It incorporates a Power Delivery (PD) PHY with BMC encoding, Protocol logic and USB Type-C Configuration Channel (CC) logic. +config PLATFORM_EC_USB_PD_TCPM_PS8XXX + bool + select PLATFORM_EC_USB_PD_TCPM_MUX + imply PLATFORM_EC_HOSTCMD_I2C_CONTROL + help + Enable the driver for PS8xxx active retimer/redrivers with integrated + USB Type-C Port Controller (TCPC) for USB Type-C Host and DisplayPort + applications. They support Power Delivery and the DisplayPort Alt Mode. + + Support for specific devices in the driver (below) must also be enabled. + +if PLATFORM_EC_USB_PD_TCPM_PS8XXX +config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX + bool "Support multiple PS8xxx devices" + help + PS8XXX-series chips are all supported by a single driver. Enable + this if a board with the same EC firmware is expected to support + multiple products here. + + In this case the board must provide a function to return the correct + product ID actually used by a particular board: + + uint16_t board_get_ps8xxx_product_id(int port) + + Supported return values are: + + PS8705_PRODUCT_ID + PS8751_PRODUCT_ID + PS8755_PRODUCT_ID + PS8805_PRODUCT_ID + PS8815_PRODUCT_ID +endif # PLATFORM_EC_USB_PD_TCPM_PS8XXX + config PLATFORM_EC_USB_PD_TCPM_PS8751 bool "Parade PS8751 USB-C Gen 2 Type-C Port Controller" - select PLATFORM_EC_USB_PD_TCPM_MUX - imply PLATFORM_EC_HOSTCMD_I2C_CONTROL + select PLATFORM_EC_USB_PD_TCPM_PS8XXX help The Parade Technologies PS8751 is a USB Type-C Port Controller (TCPC) for USB Type-C Host and DisplayPort applications. It supports @@ -161,8 +172,7 @@ config PLATFORM_EC_USB_PD_TCPM_PS8751 config PLATFORM_EC_USB_PD_TCPM_PS8805 bool "Parade PS8805 USB-C Gen 2 Type-C Port Controller" - select PLATFORM_EC_USB_PD_TCPM_MUX - imply PLATFORM_EC_HOSTCMD_I2C_CONTROL + select PLATFORM_EC_USB_PD_TCPM_PS8XXX help The Parade Technologies PS8805 is an active retiming/redriving (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated @@ -182,8 +192,7 @@ endif # PLATFORM_EC_USB_PD_TCPM_PS8805 config PLATFORM_EC_USB_PD_TCPM_PS8815 bool "Parade PS8815 USB-C Gen 2 Type-C Port Controller" - select PLATFORM_EC_USB_PD_TCPM_MUX - imply PLATFORM_EC_HOSTCMD_I2C_CONTROL + select PLATFORM_EC_USB_PD_TCPM_PS8XXX help The Parade Technologies PS8815 is an active retiming/redriving (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated -- cgit v1.2.1 From 08d0bcd729748ff77074713c84c0d333203c85c9 Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Fri, 20 May 2022 14:51:00 -0600 Subject: zephyr: Move ec_version.h generation logic from zmake to CMake (This CL needs further testing to make sure it works in all conditions) * Add a new Python script that allows generating the ec_version.h header while being somewhat separated from zmake. * Call this new script from CMake so builds can be initiated through Twister without needing zmake to create the header as a pre-build step. BRANCH=None BUG=None TEST=zmake test test-drivers (--clobber); zephyr/zmake/run_tests.sh Signed-off-by: Tristan Honscheid Change-Id: Iccb670fecd2c40ecc6360521d65259f411b3c7e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3656258 Reviewed-by: Yuval Peress Reviewed-by: Keith Short --- zephyr/CMakeLists.txt | 17 +++ zephyr/zmake/setup.py | 2 +- zephyr/zmake/tests/test_version.py | 28 ++-- zephyr/zmake/zephyr_build_tools/__init__.py | 0 .../zephyr_build_tools/generate_ec_version.py | 161 +++++++++++++++++++++ zephyr/zmake/zmake/version.py | 11 +- zephyr/zmake/zmake/zmake.py | 5 +- 7 files changed, 205 insertions(+), 19 deletions(-) create mode 100644 zephyr/zmake/zephyr_build_tools/__init__.py create mode 100755 zephyr/zmake/zephyr_build_tools/generate_ec_version.py diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 60985762d4..1388ad9a06 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -547,3 +547,20 @@ add_subdirectory("app") add_subdirectory("drivers") add_subdirectory("emul") add_subdirectory_ifdef(CONFIG_PLATFORM_EC "shim") + +# Use external script to generate the ec_version.h header and add as +# a dependency to the EC application library. +add_custom_target( + ec_version_header + VERBATIM COMMAND + "PYTHONPATH=${PLATFORM_EC}/zephyr/zmake/" ${PYTHON_EXECUTABLE} + "${PLATFORM_EC}/zephyr/zmake/zephyr_build_tools/generate_ec_version.py" + "${CMAKE_CURRENT_BINARY_DIR}/include/ec_version.h" + "--base" "${ZEPHYR_BASE}" + "--name" "${CMAKE_PROJECT_NAME}" + "--module" "${ZEPHYR_MODULES}" +) +add_dependencies(app ec_version_header) + +# Include the directory containing the generated header. +zephyr_include_directories("${CMAKE_CURRENT_BINARY_DIR}/include") diff --git a/zephyr/zmake/setup.py b/zephyr/zmake/setup.py index 3786335f19..97c126d424 100644 --- a/zephyr/zmake/setup.py +++ b/zephyr/zmake/setup.py @@ -18,7 +18,7 @@ setuptools.setup( keywords="chromeos", # You can just specify the packages manually here if your project is # simple. Or you can use find_packages(). - packages=["zmake"], + packages=["zmake", "zephyr_build_tools"], python_requires=">=3.6, <4", # List run-time dependencies here. These will be installed by pip when # your project is installed. For an analysis of "install_requires" vs pip's diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py index 9e00473752..a81d682b77 100644 --- a/zephyr/zmake/tests/test_version.py +++ b/zephyr/zmake/tests/test_version.py @@ -8,7 +8,7 @@ import datetime import subprocess import unittest.mock as mock -import pytest +import pytest # pylint: disable=import-error import zmake.output_packers import zmake.project @@ -95,7 +95,7 @@ def test_version_string(tmp_path): """Test a that version string is as expected.""" project, zephyr_base, modules = _setup_example_repos(tmp_path) assert ( - version.get_version_string(project, zephyr_base, modules) + version.get_version_string(project.config.project_name, zephyr_base, modules) == "prj_v2.6.4-ec:b5991f,os:377d26,mod1:02fd7a" ) @@ -104,7 +104,9 @@ def test_version_string_static(tmp_path): """Test a that version string with no git hashes.""" project, zephyr_base, modules = _setup_example_repos(tmp_path) assert ( - version.get_version_string(project, zephyr_base, modules, static=True) + version.get_version_string( + project.config.project_name, zephyr_base, modules, static=True + ) == "prj_v2.6.0-STATIC" ) @@ -128,7 +130,7 @@ def fake_date(): HEADER_VERSION_STR = "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da" EXPECTED_HEADER = ( - "/* This file is automatically generated by zmake */\n" + "/* This file is automatically generated by zmake_tests */\n" '#define VERSION "trogdor_v2.6.1004-cmsis:0dead0,hal_stm32:0beef0,os:ad00da"\n' '#define CROS_EC_VERSION32 "trogdor_v2.6.1004-cmsis:0dead0,"\n' '#define BUILDER "toukmond@pokey"\n' @@ -137,7 +139,7 @@ EXPECTED_HEADER = ( ) HEADER_VERSION_STR_STATIC = "trogdor_v2.6.0-STATIC" EXPECTED_HEADER_STATIC = ( - "/* This file is automatically generated by zmake */\n" + "/* This file is automatically generated by zmake_tests */\n" '#define VERSION "trogdor_v2.6.0-STATIC"\n' '#define CROS_EC_VERSION32 "trogdor_v2.6.0-STATIC"\n' '#define BUILDER "reproducible@build"\n' @@ -150,7 +152,7 @@ def test_header_gen(fake_user_hostname, fake_date, tmp_path): """Test generating the version header.""" # Test the simple case (static=False, no existing header). output_file = tmp_path / "ec_version.h" - version.write_version_header(HEADER_VERSION_STR, output_file) + version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests") assert output_file.read_text() == EXPECTED_HEADER @@ -158,7 +160,9 @@ def test_header_gen_reproducible_build(tmp_path): """Test that reproducible builds produce the right header.""" # With static=True this time. output_file = tmp_path / "ec_version.h" - version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True) + version.write_version_header( + HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True + ) assert output_file.read_text() == EXPECTED_HEADER_STATIC @@ -168,11 +172,11 @@ def test_header_gen_exists_not_changed(fake_user_hostname, fake_date, tmp_path): output_file = tmp_path / "ec_version.h" # First time, write and record mtime. - version.write_version_header(HEADER_VERSION_STR, output_file) + version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests") expected_mtime = output_file.stat().st_mtime # Do another write (contents should be unchanged). - version.write_version_header(HEADER_VERSION_STR, output_file) + version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests") # Assert we didn't write again. assert output_file.stat().st_mtime == expected_mtime @@ -184,11 +188,13 @@ def test_header_gen_exists_needs_changes(fake_user_hostname, fake_date, tmp_path output_file = tmp_path / "ec_version.h" # First time, write and save contents. - version.write_version_header(HEADER_VERSION_STR, output_file) + version.write_version_header(HEADER_VERSION_STR, output_file, "zmake_tests") original_contents = output_file.read_text() # Do another write (contents should be changed). - version.write_version_header(HEADER_VERSION_STR_STATIC, output_file, static=True) + version.write_version_header( + HEADER_VERSION_STR_STATIC, output_file, "zmake_tests", static=True + ) # Assert we overwrote. assert output_file.read_text() != original_contents diff --git a/zephyr/zmake/zephyr_build_tools/__init__.py b/zephyr/zmake/zephyr_build_tools/__init__.py new file mode 100644 index 0000000000..e69de29bb2 diff --git a/zephyr/zmake/zephyr_build_tools/generate_ec_version.py b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py new file mode 100755 index 0000000000..96f9013ca4 --- /dev/null +++ b/zephyr/zmake/zephyr_build_tools/generate_ec_version.py @@ -0,0 +1,161 @@ +#!/usr/bin/env python3 + +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Code to generate the ec_version.h file.""" + +import argparse +import logging +import os.path +import pathlib +import sys + +import zmake.version + + +def convert_module_list_to_dict(modules: list) -> dict: + """Convert a list of string paths to modules in to a dict of module + names to paths.""" + + if not modules: + return {} + + dict_out = {} + for mod in modules: + if not mod.is_dir(): + raise FileNotFoundError(f"Module '{mod}' not found") + + dict_out[mod.name] = mod + + return dict_out + + +def main(): + """CLI entry point for generating the ec_version.h header""" + logging.basicConfig(level=logging.INFO, stream=sys.stderr) + + parser = argparse.ArgumentParser() + + parser.add_argument("header_path", help="Path to write ec_version.h to") + parser.add_argument( + "-s", + "--static", + action="store_true", + help="If set, generate a header which does not include information " + "like the username, hostname, or date, allowing the build to be" + "reproducible.", + ) + parser.add_argument( + "--base", + default=os.environ.get("ZEPHYR_BASE"), + help="Path to Zephyr base directory. Uses ZEPHYR_BASE env var if unset.", + ) + parser.add_argument( + "-m", + "--module", + action="append", + help="Specify modules paths to include in version hash. Uses " + "ZEPHYR_MODULES env var if unset", + ) + parser.add_argument("-n", "--name", required=True, type=str, help="Project name") + + args = parser.parse_args() + + if args.base is None: + logging.error( + "No Zephyr base is defined. Pass --base or set env var ZEPHYR_BASE" + ) + return 1 + + logging.info("Zephyr Base: %s", args.base) + + if args.static: + logging.info("Using a static version string") + + # Make a dict of modules from the list. Modules can be added one at a time + # by repeating the -m flag, or once as a semicolon-separated list. In the + # later case, we need to expand the modules list. + + if args.module is None: + # No modules specified on command line. Default to environment variable. + env_modules = os.environ.get("ZEPHYR_MODULES") + args.module = env_modules.split(";") if env_modules else [] + logging.info("No modules passed via CLI. Getting list from ZEPHYR_MODULES") + + elif len(args.module) == 1: + # In case of a single -m flag, treat value as a semicolon-delimited + # list. + args.module = args.module[0].split(";") + + try: + module_dict = convert_module_list_to_dict(map(pathlib.Path, args.module)) + except FileNotFoundError as err: + logging.error("Cannot find module: %s", str(err)) + return 1 + + logging.info("Including modules: [%s]", ", ".join(args.module)) + + # Generate the version string that gets inserted in to the header. Will get + # commit IDs from Git + ver = zmake.version.get_version_string( + args.name, args.base, module_dict, args.static + ) + logging.info("Version string: %s", ver) + + # Now write the actual header file or put version string in stdout + if args.header_path == "-": + print(ver) + else: + output_path = pathlib.Path(args.header_path) + output_path.parent.mkdir(parents=True, exist_ok=True) + + logging.info("Writing header to %s", args.header_path) + zmake.version.write_version_header(ver, output_path, sys.argv[0], args.static) + + return 0 + + +def maybe_reexec(): + """Re-exec using the zmake package from the EC source tree, as + opposed to the system's copy of zmake. This is useful for + development when engineers need to make changes to zmake. This + script relies on the zmake package for version string generation + logic. + + Returns: + None, if the re-exec did not happen, or never returns if the + re-exec did happen. + """ + # We only re-exec if we are inside of a chroot (since if installed + # standalone using pip, there's already an "editable install" + # feature for that in pip.) + env = dict(os.environ) + srcroot = env.get("CROS_WORKON_SRCROOT") + if not srcroot: + return + + # If for some reason we decide to move zmake in the future, then + # we don't want to use the re-exec logic. + zmake_path = ( + pathlib.Path(srcroot) / "src" / "platform" / "ec" / "zephyr" / "zmake" + ).resolve() + if not zmake_path.is_dir(): + return + + # If PYTHONPATH is set, it is either because we just did a + # re-exec, or because the user wants to run a specific copy of + # zmake. In either case, we don't want to re-exec. + if "PYTHONPATH" in env: + return + + # Set PYTHONPATH so that we run zmake from source. + env["PYTHONPATH"] = str(zmake_path) + + os.execve(sys.argv[0], sys.argv, env) + + +if __name__ == "__main__": + maybe_reexec() + sys.exit(main()) diff --git a/zephyr/zmake/zmake/version.py b/zephyr/zmake/zmake/version.py index 5ac060f23b..76d9777eda 100644 --- a/zephyr/zmake/zmake/version.py +++ b/zephyr/zmake/zmake/version.py @@ -80,7 +80,7 @@ def get_version_string(project, zephyr_base, modules, static=False): """Get the version string associated with a build. Args: - project: a zmake.project.Project object + project: a string project name zephyr_base: the path to the zephyr directory modules: a dictionary mapping module names to module paths static: if set, create a version string not dependent on git @@ -117,7 +117,7 @@ def get_version_string(project, zephyr_base, modules, static=False): ) return "{}_v{}.{}.{}-{}".format( - project.config.project_name, + project, major_version, minor_version, num_commits, @@ -125,7 +125,7 @@ def get_version_string(project, zephyr_base, modules, static=False): ) -def write_version_header(version_str, output_path, static=False): +def write_version_header(version_str, output_path, tool, static=False): """Generate a version header and write it to the specified path. Generate a version header in the format expected by the EC build @@ -139,12 +139,15 @@ def write_version_header(version_str, output_path, static=False): as one generated by get_version_string. output_path: The file path to write at (a pathlib.Path object). + tool: Name of the tool that is invoking this function ("zmake", + "generate_ec_version.py", etc). Included in a comment in the + header. static: If true, generate a header which does not include information like the username, hostname, or date, allowing the build to be reproducible. """ output = io.StringIO() - output.write("/* This file is automatically generated by zmake */\n") + output.write(f"/* This file is automatically generated by {tool} */\n") def add_def(name, value): output.write("#define {} {}\n".format(name, util.c_str(value))) diff --git a/zephyr/zmake/zmake/zmake.py b/zephyr/zmake/zmake/zmake.py index 698cf40b2b..71fef5f16b 100644 --- a/zephyr/zmake/zmake/zmake.py +++ b/zephyr/zmake/zmake/zmake.py @@ -691,7 +691,7 @@ class Zmake: # Compute the version string. version_string = zmake.version.get_version_string( - project, + project.config.project_name, build_dir / "zephyr_base", zmake.modules.locate_from_directory(build_dir / "modules"), ) @@ -700,8 +700,7 @@ class Zmake: # instead of configure, as the tree may have changed since # configure was run. zmake.version.write_version_header( - version_string, - build_dir / "include" / "ec_version.h", + version_string, build_dir / "include" / "ec_version.h", "zmake" ) gcov = "gcov.sh-not-found" -- cgit v1.2.1 From a16876cb2bbdb426ccfac7bb69f5b9a76c76ac63 Mon Sep 17 00:00:00 2001 From: lschyi Date: Mon, 20 Jun 2022 14:27:38 +0800 Subject: zephyr: Allow project to config usb c power via Kconfig Make PD_OPERATING_POWER_MW, PD_MAX_POWER_MW, PD_MAX_CURRENT_MA, PD_MAX_VOLTAGE_MV, PD_POWER_SUPPLY_TURN_ON_DELAY, and PD_POWER_SUPPLY_TURN_OFF_DELAY configurable via Kconfig so that projects can update settings. BUG=b:235258222, b:236712633 TEST=make -j buildall BRANCH=none Change-Id: If9a648a4cbcdbbc7c30735bd1b1c673a38df5612 Signed-off-by: lschyi Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711516 Reviewed-by: Eric Yilun Lin Commit-Queue: Sung-Chi Li Tested-by: Sung-Chi Li Reviewed-by: Keith Short --- zephyr/Kconfig.usbc | 51 +++++++++++++++++++++++++++++++++++++++ zephyr/shim/include/config_chip.h | 19 +++++++++------ 2 files changed, 62 insertions(+), 8 deletions(-) diff --git a/zephyr/Kconfig.usbc b/zephyr/Kconfig.usbc index 1f5e0f2388..1cb4088475 100644 --- a/zephyr/Kconfig.usbc +++ b/zephyr/Kconfig.usbc @@ -173,4 +173,55 @@ config PLATFORM_EC_USB_PD_ONLY_FIXED_PDOS Ignore all non-fixed PDOs received from a src_caps message. Enable this for boards (like servo_v4) which only support FIXED PDO types. +# Define power related settings here for now to allow projects to overwrite +# them. Ideally they would be defined in the devicetree. +config PLATFORM_EC_PD_OPERATING_POWER_MW + int "PD operating power in milliwatt" + default 15000 + help + Base configuration for PD power operating power value, which is used + in PD negotiation. The final PD parameter used in negotiation is + affected by PLATFORM_EC_PD_MAX_POWER_MW, + PLATFORM_EC_PD_MAX_CURRENT_MA, and PLATFORM_EC_PD_MAX_VOLTAGE_MV. + Increase this value is the system requires more than 15 watts to boot + without a battery. + +config PLATFORM_EC_PD_MAX_POWER_MW + int "PD maximum power in milliwatt" + default 60000 + help + The maximum PD negotiated power for the system. The value should match + with configured PLATFORM_EC_PD_MAX_CURRENT_MA and + PLATFORM_EC_PD_MAX_VOLTAGE_MV. + +config PLATFORM_EC_PD_MAX_CURRENT_MA + int "PD maximum current in milliampere" + default 3000 + help + The maximum PD negotiated current for the system. The value should + match with configured PLATFORM_EC_PD_MAX_POWER_MW and + PLATFORM_EC_PD_MAX_VOLTAGE_MV. + +config PLATFORM_EC_PD_MAX_VOLTAGE_MV + int "PD maximum voltage in millivolt" + default 20000 + help + The maximum PD negotiated voltage for the system. The value should + match with configured PLATFORM_EC_PD_MAX_POWER_MW and + PLATFORM_EC_PD_MAX_CURRENT_MA. + +config PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY + int "Power supply turn on delay in us" + default 30000 + help + Each platform could have different power sequencing and transition + timing for turning on the power on the PD port. + +config PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY + int "Power supply turn off delay in us" + default 30000 + help + Each platform could have different power sequencing and transition + timing for turning off the power on the PD port. + endif # PLATFORM_EC_USBC diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index a47063f712..14814897be 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -943,18 +943,21 @@ extern struct jump_data mock_jump_data; /* * Define these here for now. They are not actually CONFIG options in the EC * code base. Ideally they would be defined in the devicetree (perhaps for a - * 'board' driver if not in the USB chip driver itself). + * 'board' driver if not in the USB chip driver itself). Use Kconfig to allow + * projects to overwrite the power configurations. * * SN5S30 PPC supports up to 24V VBUS source and sink, however passive USB-C * cables only support up to 60W. */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_POWER_MW 60000 -#define PD_MAX_CURRENT_MA 3000 -#define PD_MAX_VOLTAGE_MV 20000 - -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ -#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_OPERATING_POWER_MW CONFIG_PLATFORM_EC_PD_OPERATING_POWER_MW +#define PD_MAX_POWER_MW CONFIG_PLATFORM_EC_PD_MAX_POWER_MW +#define PD_MAX_CURRENT_MA CONFIG_PLATFORM_EC_PD_MAX_CURRENT_MA +#define PD_MAX_VOLTAGE_MV CONFIG_PLATFORM_EC_PD_MAX_VOLTAGE_MV + +#define PD_POWER_SUPPLY_TURN_ON_DELAY \ + CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_ON_DELAY +#define PD_POWER_SUPPLY_TURN_OFF_DELAY \ + CONFIG_PLATFORM_EC_PD_POWER_SUPPLY_TURN_OFF_DELAY #endif #undef CONFIG_CMD_PPC_DUMP -- cgit v1.2.1 From 40d02d8f89b73a92e4d4a2208a095a057fcbc2da Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Thu, 9 Jun 2022 03:19:03 -0700 Subject: zephyr: cros_system: npcx: implement hibernate with power control device This CL uses a power control device with pinctrl mechanism instead of npcx soc-specific utilities for hibernating functionality via PSL circuit. BUG=b:232543902 BRANCH=none TEST=zmake testall --clobber Signed-off-by: Mulin Chao Change-Id: I4f4991bd9e62fa9c7f8d7c6e894613f6904b618c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3697271 Reviewed-by: Fabio Baltieri Reviewed-by: Keith Short --- zephyr/boards/arm/npcx7/npcx7.dts | 5 +++ zephyr/boards/arm/npcx9/npcx9.dtsi | 5 +++ zephyr/boards/arm/npcx_evb/npcx7_evb.dts | 5 +++ zephyr/boards/arm/npcx_evb/npcx9_evb.dts | 5 +++ zephyr/drivers/cros_system/cros_system_npcx.c | 54 ++++++++++++++++++++++----- 5 files changed, 65 insertions(+), 9 deletions(-) diff --git a/zephyr/boards/arm/npcx7/npcx7.dts b/zephyr/boards/arm/npcx7/npcx7.dts index 551c3fe3af..282dc07762 100644 --- a/zephyr/boards/arm/npcx7/npcx7.dts +++ b/zephyr/boards/arm/npcx7/npcx7.dts @@ -88,3 +88,8 @@ >; pinctrl-names = "default"; }; + +/* PSL_OUT is fixed to GPIO85 in npcx7 series. */ +&power_ctrl_psl { + enable-gpios = <&gpio8 5 0>; +}; diff --git a/zephyr/boards/arm/npcx9/npcx9.dtsi b/zephyr/boards/arm/npcx9/npcx9.dtsi index 27ece8cdd6..97ea1ad407 100644 --- a/zephyr/boards/arm/npcx9/npcx9.dtsi +++ b/zephyr/boards/arm/npcx9/npcx9.dtsi @@ -56,3 +56,8 @@ pinmux-gpio; }; }; + +/* PSL_OUT is fixed to GPIO85 in npcx9 series. */ +&power_ctrl_psl { + enable-gpios = <&gpio8 5 0>; +}; diff --git a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts index 1780495feb..7d6eee1359 100644 --- a/zephyr/boards/arm/npcx_evb/npcx7_evb.dts +++ b/zephyr/boards/arm/npcx_evb/npcx7_evb.dts @@ -22,3 +22,8 @@ pinctrl-0 = <&uart1_2_sin_sout_gp64_65>; pinctrl-names = "default"; }; + +/* PSL_OUT is fixed to GPIO85 in npcx7 series. */ +&power_ctrl_psl { + enable-gpios = <&gpio8 5 0>; +}; diff --git a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts index 6669575466..e9e010833b 100644 --- a/zephyr/boards/arm/npcx_evb/npcx9_evb.dts +++ b/zephyr/boards/arm/npcx_evb/npcx9_evb.dts @@ -23,3 +23,8 @@ &uart1_2_sout_gp65>; pinctrl-names = "default"; }; + +/* PSL_OUT is fixed to GPIO85 in npcx9 series. */ +&power_ctrl_psl { + enable-gpios = <&gpio8 5 0>; +}; diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index 0767a2d230..a4885ed9da 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -412,11 +412,42 @@ static const char *cros_system_npcx_get_chip_revision(const struct device *dev) return rev; } +#define PSL_NODE DT_INST(0, nuvoton_npcx_power_psl) +#if DT_NODE_HAS_STATUS(PSL_NODE, okay) +PINCTRL_DT_DEFINE(PSL_NODE); +static int cros_system_npcx_configure_psl_in(void) +{ + const struct pinctrl_dev_config *pcfg = + PINCTRL_DT_DEV_CONFIG_GET(PSL_NODE); + + return pinctrl_apply_state(pcfg, PINCTRL_STATE_SLEEP); +} + +static void cros_system_npcx_psl_out_inactive(void) +{ + struct gpio_dt_spec enable = GPIO_DT_SPEC_GET(PSL_NODE, enable_gpios); + + gpio_pin_set_dt(&enable, 1); +} +#else +static int cros_system_npcx_configure_psl_in(void) +{ + return -EINVAL; +} + +static void cros_system_npcx_psl_out_inactive(void) +{ + return; +} +#endif + static void system_npcx_hibernate_by_psl(const struct device *dev, uint32_t seconds, uint32_t microseconds) { ARG_UNUSED(dev); + int ret; + /* * TODO(b/178230662): RTC wake-up in PSL mode only support in npcx9 * series. Nuvoton will introduce CLs for it later. @@ -424,11 +455,12 @@ static void system_npcx_hibernate_by_psl(const struct device *dev, ARG_UNUSED(seconds); ARG_UNUSED(microseconds); - /* - * Configure PSL input pads from "psl-in-pads" property in device tree - * file. - */ - npcx_pinctrl_psl_input_configure(); + /* Configure detection settings of PSL_IN pads first */ + ret = cros_system_npcx_configure_psl_in(); + if (ret < 0) { + LOG_ERR("PSL_IN pinctrl setup failed (%d)", ret); + return; + } /* * Give the board a chance to do any late stage hibernation work. This @@ -439,8 +471,12 @@ static void system_npcx_hibernate_by_psl(const struct device *dev, if (board_hibernate_late) board_hibernate_late(); - /* Turn off VCC1 to enter ultra-low-power mode for hibernating */ - npcx_pinctrl_psl_output_set_inactive(); + /* + * A transition from 0 to 1 of specific IO (GPIO85) data-out bit + * set PSL_OUT to inactive state. Then, it will turn Core Domain + * power supply (VCC1) off for better power consumption. + */ + cros_system_npcx_psl_out_inactive(); } static int cros_system_npcx_get_reset_cause(const struct device *dev) @@ -526,8 +562,8 @@ static int cros_system_npcx_soc_reset(const struct device *dev) #error "cros-ec,hibernate-wake-pins cannot be used with HIBERNATE_PSL" #endif #else -#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_pslctrl_def) -#error "vsby-psl-in-list cannot be used with non-HIBERNATE_PSL" +#if DT_NODE_HAS_STATUS(PSL_NODE, okay) +#error "power_ctrl_psl cannot be used with non-HIBERNATE_PSL" #endif #endif -- cgit v1.2.1 From 27afedd70ab55675cfeab08aa27a6954998919c9 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Thu, 9 Jun 2022 03:21:49 -0700 Subject: zephyr: npcx9: implement hibernate via PSL power control device This CL enables 'power control device' and set related DT node configurations in npcx9 board dts file to support wake up via PSL_IN pads after hibernating. BUG=b:232543902 BRANCH=none TEST='hibernate' & wake-up ec by PSL_IN2. Signed-off-by: Mulin Chao Change-Id: I990e54c9e4621eaff0e5c67b584e8102db94dbc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3698178 Reviewed-by: Fabio Baltieri Reviewed-by: Keith Short --- zephyr/projects/npcx_evb/npcx9/gpio.dts | 20 ++++++++++++-------- zephyr/projects/npcx_evb/npcx9/prj.conf | 3 +++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/zephyr/projects/npcx_evb/npcx9/gpio.dts b/zephyr/projects/npcx_evb/npcx9/gpio.dts index d0aa642673..54e1db5495 100644 --- a/zephyr/projects/npcx_evb/npcx9/gpio.dts +++ b/zephyr/projects/npcx_evb/npcx9/gpio.dts @@ -56,13 +56,17 @@ enum-name = "GPIO_BOARD_VERSION3"; }; }; +}; - hibernate-wake-pins { - compatible = "cros-ec,hibernate-wake-pins"; - wakeup-irqs = < - &int_ac_present - &int_power_button - &int_lid_open - >; - }; +/* A falling edge detection type for PSL_IN2 */ +&psl_in2_gp00 { + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in2_gp00>; }; diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf index aa7e36a7a6..22b32b1de1 100644 --- a/zephyr/projects/npcx_evb/npcx9/prj.conf +++ b/zephyr/projects/npcx_evb/npcx9/prj.conf @@ -57,4 +57,7 @@ CONFIG_LOG=y # Avoid underflow info from tachometer CONFIG_SENSOR_LOG_LEVEL_ERR=y +# Hibernate and wake +CONFIG_PLATFORM_EC_HIBERNATE_PSL=y + CONFIG_SYSCON=y -- cgit v1.2.1 From 1c02a4abb2635617a526c8b1e53e569dabe710ee Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Mon, 20 Jun 2022 03:19:57 -0700 Subject: zephyr: brya: implement hibernate via PSL power control device This CL enables 'power control device' and set related DT node configurations in brya gpio dts file to support wake up via PSL_IN pads after hibernating. BUG=b:232543902 BRANCH=none TEST=zmake build brya --clobber. Signed-off-by: Mulin Chao Change-Id: Id0a65afaa504903661238ec5472c222029166899 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716178 Reviewed-by: Keith Short Reviewed-by: Fabio Baltieri Reviewed-by: Jack Rosenthal --- zephyr/projects/brya/gpio.dts | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/zephyr/projects/brya/gpio.dts b/zephyr/projects/brya/gpio.dts index aaf34861c8..d6473784d0 100644 --- a/zephyr/projects/brya/gpio.dts +++ b/zephyr/projects/brya/gpio.dts @@ -312,12 +312,6 @@ compatible = "cros-ec,usba-port-enable-pins"; enable-pins = <&gpio_en_pp5000_usba_r>; }; - - vsby-psl-in-list { - /* Use PSL_IN1/2/3 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3>; - status = "okay"; - }; }; &i2c1_0 { @@ -373,16 +367,26 @@ /* Power switch logic input pads */ /* LID_OPEN_OD */ -&psl_in1 { - flag = ; +&psl_in1_gpd2 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; /* ACOK_EC_OD */ -&psl_in2 { - flag = ; +&psl_in2_gp00 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; /* GSC_EC_PWR_BTN_ODL */ -&psl_in3 { - flag = ; +&psl_in3_gp01 { + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01>; }; -- cgit v1.2.1 From fff6b01da23314dc9fb1cb796865d16b5178e5e1 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Mon, 20 Jun 2022 03:30:40 -0700 Subject: zephyr: herobrine/hoglin/villager: add PSL power control device support This CL enables 'power control device' and set related DT node configurations in herobrine, hoglin and villager gpio dts files to support wake up via PSL_IN pads after hibernating. BUG=b:232543902 BRANCH=none TEST=zmake build herobrine/hoglin/villager --clobber. Eneter 'hibernate' on cros console. Then, wake up by pressing PSL_IN pads on herobrine. Signed-off-by: Mulin Chao Change-Id: I7bf5131c6068188aea197d0722d39712ed4051ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716179 Reviewed-by: Jack Rosenthal Reviewed-by: Fabio Baltieri Reviewed-by: Keith Short --- zephyr/projects/herobrine/gpio.dts | 33 +++++++++++++++++------------ zephyr/projects/herobrine/gpio_hoglin.dts | 33 +++++++++++++++++------------ zephyr/projects/herobrine/gpio_villager.dts | 33 +++++++++++++++++------------ 3 files changed, 57 insertions(+), 42 deletions(-) diff --git a/zephyr/projects/herobrine/gpio.dts b/zephyr/projects/herobrine/gpio.dts index ba958150e0..b73c83937c 100644 --- a/zephyr/projects/herobrine/gpio.dts +++ b/zephyr/projects/herobrine/gpio.dts @@ -245,12 +245,6 @@ >; }; - vsby-psl-in-list { - /* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>; - status = "okay"; - }; - sku { compatible = "cros-ec,gpio-id"; @@ -305,22 +299,33 @@ }; /* Power switch logic input pads */ -&psl_in1 { +&psl_in1_gpd2 { /* ACOK_OD */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in2 { +&psl_in2_gp00 { /* EC_PWR_BTN_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; -&psl_in3 { +&psl_in3_gp01 { /* LID_OPEN_EC */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in4 { +&psl_in4_gp02 { /* RTC_EC_WAKE_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; +}; \ No newline at end of file diff --git a/zephyr/projects/herobrine/gpio_hoglin.dts b/zephyr/projects/herobrine/gpio_hoglin.dts index f0b8a43586..2f8a780094 100644 --- a/zephyr/projects/herobrine/gpio_hoglin.dts +++ b/zephyr/projects/herobrine/gpio_hoglin.dts @@ -243,12 +243,6 @@ >; }; - vsby-psl-in-list { - /* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>; - status = "okay"; - }; - sku { compatible = "cros-ec,gpio-id"; @@ -303,22 +297,33 @@ }; /* Power switch logic input pads */ -&psl_in1 { +&psl_in1_gpd2 { /* ACOK_OD */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in2 { +&psl_in2_gp00 { /* EC_PWR_BTN_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; -&psl_in3 { +&psl_in3_gp01 { /* LID_OPEN_EC */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in4 { +&psl_in4_gp02 { /* RTC_EC_WAKE_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; }; diff --git a/zephyr/projects/herobrine/gpio_villager.dts b/zephyr/projects/herobrine/gpio_villager.dts index 7b8d2adcb5..00e9c66b53 100644 --- a/zephyr/projects/herobrine/gpio_villager.dts +++ b/zephyr/projects/herobrine/gpio_villager.dts @@ -237,12 +237,6 @@ >; }; - vsby-psl-in-list { - /* Use PSL_IN1/2/3/4 as detection pins from hibernate mode */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>; - status = "okay"; - }; - sku { compatible = "cros-ec,gpio-id"; @@ -299,22 +293,33 @@ }; /* Power switch logic input pads */ -&psl_in1 { +&psl_in1_gpd2 { /* ACOK_OD */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in2 { +&psl_in2_gp00 { /* EC_PWR_BTN_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; -&psl_in3 { +&psl_in3_gp01 { /* LID_OPEN_EC */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in4 { +&psl_in4_gp02 { /* RTC_EC_WAKE_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in3_gp01 &psl_in4_gp02>; }; -- cgit v1.2.1 From 2610179cea1700e21e576e614c3dbfeb2a5d70b5 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Tue, 21 Jun 2022 19:18:58 -0700 Subject: zephyr: skyrim: implement hibernate via PSL power control device This CL enables 'power control device' and set related DT node configurations in skyrim gpio dts file to support wake up via PSL_IN pads after hibernating. BUG=b:232543902 BRANCH=none TEST=zmake build skyrim --clobber. Signed-off-by: Mulin Chao Change-Id: Ic84b6d96eea3bbdad14b9e1f3b0a28af6c582bd6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3716180 Reviewed-by: Fabio Baltieri Reviewed-by: Keith Short Reviewed-by: Jack Rosenthal --- zephyr/projects/skyrim/gpio.dts | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/zephyr/projects/skyrim/gpio.dts b/zephyr/projects/skyrim/gpio.dts index 57097598ae..12e7187a8e 100644 --- a/zephyr/projects/skyrim/gpio.dts +++ b/zephyr/projects/skyrim/gpio.dts @@ -254,28 +254,32 @@ enable-pins = <&ioex_en_pp5000_usb_a0_vbus &ioex_en_pp5000_usb_a1_vbus>; }; - - vsby-psl-in-list { - /* PSL_IN1/2/4 are used to wake */ - psl-in-pads = <&psl_in1 &psl_in2 &psl_in4>; - status = "okay"; - }; }; /* PSL input pads*/ -&psl_in1 { +&psl_in1_gpd2 { /* MECH_PWR_BTN_ODL */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; }; -&psl_in2 { +&psl_in2_gp00 { /* ACOK_OD */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; }; -&psl_in4 { +&psl_in4_gp02 { /* LID_OPEN */ - flag = ; + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>; }; &i2c0_0 { -- cgit v1.2.1 From f43ad912a1548fd50f4044bb370490ae2b99bf07 Mon Sep 17 00:00:00 2001 From: Zick Wei Date: Mon, 4 Jul 2022 10:39:37 +0800 Subject: agah: implement LED behavior agah only has 1 LED with white and amber 2 colors, behavior list below: DC mode: default: off Suspend: blink slow white battery low(< 10%): blink slow amber battery error: blink quickly amber AC mode: Charging: amber Fully charged: white Fully charged and suspend: blink slow white battery error: blink quickly amber blink slow: 1 second On, 1 second Off blink quickly: 0.5 second On, 0.5 second Off BUG=b:238055898 BRANCH=none TEST=confirmed LED behavior intended, with "ectool led battery white|amber|off|auto" work intended. Signed-off-by: Zick Wei Change-Id: I34f2ecaaf9ec1f0dfcee487e0bb77c89dc67038e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3621999 Reviewed-by: Boris Mittelberg --- board/agah/board.h | 16 +--- board/agah/ec.tasklist | 1 + board/agah/gpio.inc | 3 +- board/agah/led.c | 219 +++++++++++++++++++++++++++++++++++++------------ board/agah/pwm.c | 14 ---- 5 files changed, 171 insertions(+), 82 deletions(-) diff --git a/board/agah/board.h b/board/agah/board.h index 28f9423b5f..68a8890c7f 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -29,18 +29,6 @@ */ #undef CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 -/* LED */ -#define CONFIG_LED_PWM -#define CONFIG_LED_PWM_COUNT 1 -#undef CONFIG_LED_PWM_NEAR_FULL_COLOR -#undef CONFIG_LED_PWM_SOC_ON_COLOR -#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR -#undef CONFIG_LED_PWM_LOW_BATT_COLOR -#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_WHITE -#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_WHITE -#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_WHITE -#define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER - /* Sensors */ #undef CONFIG_TABLET_MODE #undef CONFIG_TABLET_MODE_SWITCH @@ -187,9 +175,7 @@ enum battery_type { }; enum pwm_channel { - PWM_CH_LED2 = 0, /* PWM0 (white charger) */ - PWM_CH_LED1, /* PWM2 (orange charger) */ - PWM_CH_KBLIGHT, /* PWM3 */ + PWM_CH_KBLIGHT = 0, /* PWM3 */ PWM_CH_FAN, /* PWM5 */ PWM_CH_FAN2, /* PWM4 */ PWM_CH_COUNT diff --git a/board/agah/ec.tasklist b/board/agah/ec.tasklist index 7286caf6c6..187609f36e 100644 --- a/board/agah/ec.tasklist +++ b/board/agah/ec.tasklist @@ -12,6 +12,7 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \ + TASK_ALWAYS(LED, led_task, NULL, TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(CHARGER, charger_task, NULL, BASEBOARD_CHARGER_TASK_STACK_SIZE) \ diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index f382863952..c912c1b1df 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -69,6 +69,8 @@ GPIO(EN_USB_A_LOW_POWER, PIN(9, 3), GPIO_OUT_LOW) GPIO(PG_PP3300_S5_EC_SEQ_OD, PIN(B, 5), GPIO_OUT_LOW) GPIO(USB_C2_FRS_EN, PIN(D, 4), GPIO_OUT_LOW) GPIO(NVIDIA_GPU_ACOFF_ODL, PIN(9, 5), GPIO_ODR_HIGH) +GPIO(LED_2_L, PIN(C, 3), GPIO_OUT_LOW) +GPIO(LED_1_L, PIN(C, 4), GPIO_OUT_LOW) /* * Barrel-jack adapter enable switch. When starting up on a depleted battery, @@ -101,7 +103,6 @@ ALTERNATE(PIN_MASK(4, 0x01), 0, MODULE_PWM, 0) /* GPIO40/TA1 */ ALTERNATE(PIN_MASK(7, 0x08), 0, MODULE_PWM, 0) /* GPIO73/TA2 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* GPIO80/PWM3 */ ALTERNATE(PIN_MASK(B, 0xC0), 0, MODULE_PWM, 0) /* GPIOB7/PWM5, GPIOB6/PWM4 */ -ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) /* GPIOC4/PWM2, GPIOC3/PWM0 */ /* ADC alternate functions */ ALTERNATE(PIN_MASK(3, 0x10), 0, MODULE_ADC, 0) /* GPIO34/PS2_DAT2/ADC6 */ diff --git a/board/agah/led.c b/board/agah/led.c index 1a979ddd8d..d81bc1b0ab 100644 --- a/board/agah/led.c +++ b/board/agah/led.c @@ -1,80 +1,195 @@ /* Copyright 2021 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. - */ - -/* Agah specific PWM LED settings: there are 2 LEDs on each side of the board, - * each one can be controlled separately. The LED colors are white or amber, - * and the default behavior is tied to the charging process: both sides are - * amber while charging the battery and white when the battery is charged. + * + * Battery LED control for Agah */ #include -#include "common.h" -#include "compile_time_macros.h" +#include "battery.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "chipset.h" #include "ec_commands.h" -#include "led_pwm.h" -#include "pwm.h" -#include "util.h" +#include "gpio.h" +#include "host_command.h" +#include "led_common.h" +#include "task.h" -const enum ec_led_id supported_led_ids[] = { - EC_LED_ID_LEFT_LED, - EC_LED_ID_RIGHT_LED, -}; +#define BAT_LED_ON 0 +#define BAT_LED_OFF 1 + +#define BATT_LOW_BCT 10 + +#define LED_TICK_INTERVAL_MS (500 * MSEC) +#define LED_CYCLE_TIME_MS (2000 * MSEC) +#define LED_TICKS_PER_CYCLE (LED_CYCLE_TIME_MS / LED_TICK_INTERVAL_MS) +#define LED_ON_TIME_MS (1000 * MSEC) +#define LED_ON_TICKS (LED_ON_TIME_MS / LED_TICK_INTERVAL_MS) + +const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED }; const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); -/* - * We only have a white and an amber LED, so setting any other color results in - * both LEDs being off. Cap at 50% to save power. - */ -struct pwm_led_color_map led_color_map[EC_LED_COLOR_COUNT] = { - /* Amber, White */ - [EC_LED_COLOR_RED] = { 0, 0 }, [EC_LED_COLOR_GREEN] = { 0, 0 }, - [EC_LED_COLOR_BLUE] = { 0, 0 }, [EC_LED_COLOR_YELLOW] = { 0, 0 }, - [EC_LED_COLOR_WHITE] = { 0, 50 }, [EC_LED_COLOR_AMBER] = { 50, 0 }, +enum led_color { + LED_OFF = 0, + LED_AMBER, + LED_WHITE, + LED_COLOR_COUNT /* Number of colors, not a color itself */ }; -/* Two logical LEDs with amber and white channels. */ -struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = { - { - .ch0 = PWM_CH_LED1, - .ch1 = PWM_CH_LED2, - .ch2 = PWM_LED_NO_CHANNEL, - .enable = &pwm_enable, - .set_duty = &pwm_set_duty, - }, -}; +static void led_set_color_battery(enum led_color color) +{ + enum gpio_signal amber_led, white_led; + + amber_led = GPIO_LED_1_L; + white_led = GPIO_LED_2_L; + + switch (color) { + case LED_WHITE: + gpio_set_level(white_led, BAT_LED_ON); + gpio_set_level(amber_led, BAT_LED_OFF); + break; + case LED_AMBER: + gpio_set_level(white_led, BAT_LED_OFF); + gpio_set_level(amber_led, BAT_LED_ON); + break; + case LED_OFF: + gpio_set_level(white_led, BAT_LED_OFF); + gpio_set_level(amber_led, BAT_LED_OFF); + break; + default: + break; + } +} void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) { - memset(brightness_range, '\0', - sizeof(*brightness_range) * EC_LED_COLOR_COUNT); - brightness_range[EC_LED_COLOR_AMBER] = 100; - brightness_range[EC_LED_COLOR_WHITE] = 100; + switch (led_id) { + case EC_LED_ID_BATTERY_LED: + brightness_range[EC_LED_COLOR_WHITE] = 1; + brightness_range[EC_LED_COLOR_AMBER] = 1; + break; + default: + break; + } } int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) { - enum pwm_led_id pwm_id; - - /* Convert ec_led_id to pwm_led_id. */ switch (led_id) { - case EC_LED_ID_LEFT_LED: - pwm_id = PWM_LED0; + case EC_LED_ID_BATTERY_LED: + if (brightness[EC_LED_COLOR_WHITE] != 0) + led_set_color_battery(LED_WHITE); + else if (brightness[EC_LED_COLOR_AMBER] != 0) + led_set_color_battery(LED_AMBER); + else + led_set_color_battery(LED_OFF); break; default: - return EC_ERROR_UNKNOWN; + return EC_ERROR_PARAM1; } - if (brightness[EC_LED_COLOR_WHITE]) - set_pwm_led_color(pwm_id, EC_LED_COLOR_WHITE); - else if (brightness[EC_LED_COLOR_AMBER]) - set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER); - else - /* Otherwise, the "color" is "off". */ - set_pwm_led_color(pwm_id, -1); - return EC_SUCCESS; } + +/* + * Set active charge port color to the parameter, turn off all others. + * If no port is active (-1), turn off all LEDs. + */ +static void set_active_port_color(enum led_color color) +{ + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) + led_set_color_battery(color); +} + +static void led_set_battery(void) +{ + static unsigned int battery_ticks; + static unsigned int suspend_ticks; + + uint32_t chflags = charge_get_flags(); + + battery_ticks++; + + if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND) && + charge_get_state() != PWR_STATE_CHARGE) { + suspend_ticks++; + + led_set_color_battery( + (suspend_ticks % LED_TICKS_PER_CYCLE < LED_ON_TICKS) ? + LED_WHITE : + LED_OFF); + + return; + } + + switch (charge_get_state()) { + case PWR_STATE_CHARGE: + /* Always indicate when charging, even in suspend. */ + set_active_port_color(LED_AMBER); + break; + case PWR_STATE_DISCHARGE: + /* + * Blinking amber LEDs slowly if battery is lower 10 + * percentage. + */ + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + if (charge_get_percent() < BATT_LOW_BCT) + led_set_color_battery( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); + else + led_set_color_battery(LED_OFF); + } + + break; + case PWR_STATE_ERROR: + if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED)) { + led_set_color_battery( + (battery_ticks & 0x1) ? LED_AMBER : LED_OFF); + } + + break; + case PWR_STATE_CHARGE_NEAR_FULL: + set_active_port_color(LED_WHITE); + break; + case PWR_STATE_IDLE: /* External power connected in IDLE */ + if (chflags & CHARGE_FLAG_FORCE_IDLE) + set_active_port_color( + (battery_ticks % LED_TICKS_PER_CYCLE < + LED_ON_TICKS) ? + LED_AMBER : + LED_OFF); + else + set_active_port_color(LED_WHITE); + break; + default: + /* Other states don't alter LED behavior */ + break; + } +} + +void led_task(void *u) +{ + uint32_t start_time; + uint32_t task_duration; + + while (1) { + start_time = get_time().le.lo; + + led_set_battery(); + + /* Compute time for this iteration */ + task_duration = get_time().le.lo - start_time; + /* + * Compute wait time required to for next desired LED tick. If + * the duration exceeds the tick time, then don't sleep. + */ + if (task_duration < LED_TICK_INTERVAL_MS) + usleep(LED_TICK_INTERVAL_MS - task_duration); + } +} diff --git a/board/agah/pwm.c b/board/agah/pwm.c index 1b704bc71e..69616f6f04 100644 --- a/board/agah/pwm.c +++ b/board/agah/pwm.c @@ -11,16 +11,6 @@ #include "pwm_chip.h" const struct pwm_t pwm_channels[] = { - [PWM_CH_LED2] = { - .channel = 0, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 4800, - }, - [PWM_CH_LED1] = { - .channel = 2, - .flags = PWM_CONFIG_ACTIVE_LOW | PWM_CONFIG_DSLEEP, - .freq = 4800, - }, [PWM_CH_KBLIGHT] = { .channel = 3, .flags = 0, @@ -51,10 +41,6 @@ static void board_pwm_init(void) * Turn off all the LEDs. * Turn on the fan at 100%. */ - pwm_enable(PWM_CH_LED1, 1); - pwm_set_duty(PWM_CH_LED1, 0); - pwm_enable(PWM_CH_LED2, 1); - pwm_set_duty(PWM_CH_LED2, 0); pwm_enable(PWM_CH_KBLIGHT, 1); pwm_set_duty(PWM_CH_KBLIGHT, 50); -- cgit v1.2.1 From 8af8056eb320293c0d3368666bc39af3e8420cf7 Mon Sep 17 00:00:00 2001 From: Zick Wei Date: Mon, 20 Jun 2022 13:54:11 +0800 Subject: agah: set EN_PP5000_FAN to initial low BUG=b:238505283 BRANCH=none TEST=make sure fan work after system power on. Signed-off-by: Zick Wei Change-Id: I50393da9bbdf78eb5998c1c92981c4f1d2a9bd1f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3711515 Reviewed-by: Boris Mittelberg --- board/agah/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/agah/gpio.inc b/board/agah/gpio.inc index c912c1b1df..3715dcf14b 100644 --- a/board/agah/gpio.inc +++ b/board/agah/gpio.inc @@ -55,7 +55,7 @@ GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_R_ODL, PIN(C, 0), GPIO_ODR_HIGH) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) -GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_HIGH) +GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_LOW) GPIO(EN_PP5000_USBA_R, PIN(D, 7), GPIO_OUT_LOW) GPIO(EN_S5_RAILS, PIN(9, 6), GPIO_OUT_LOW) GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT) -- cgit v1.2.1 From 64c61107a4fbfc2de2a03ccfbb5674fb0ef21538 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Tue, 12 Jul 2022 09:23:11 +0800 Subject: nissa: Enable Joxer fan support Enable Joxer fan support, gated by FW_CONFIG fan flag. - GPL4 for FAN_ENABLE. - GPA7/ PWM7 for FAN PWM. - GPD7/ TACH1A for FAN TACH. BUG=b:234683955 TEST=zmake build joxer BRANCH=none Signed-off-by: Scott Chao Change-Id: I4078ca4fc2b9fd581ee5d37eac6f6bfc61de1caa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3755242 Reviewed-by: Andrew McRae Reviewed-by: Peter Marheine --- zephyr/projects/nissa/CMakeLists.txt | 1 + zephyr/projects/nissa/joxer_overlay.dts | 34 ++++++++++++++++++++++++++ zephyr/projects/nissa/prj_joxer.conf | 2 +- zephyr/projects/nissa/src/joxer/fan.c | 43 +++++++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 zephyr/projects/nissa/src/joxer/fan.c diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 4bfc879758..258dbfdc3a 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -66,4 +66,5 @@ if(DEFINED CONFIG_BOARD_JOXER) zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/joxer/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/joxer/charger.c") + zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/joxer/fan.c") endif() diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index 9f8cd1b864..1960283135 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -117,6 +117,10 @@ gpios = <&gpioe 0 0>; no-auto-init; }; + gpio_fan_enable: fan-enable { + gpios = <&gpiol 4 GPIO_OUTPUT>; + no-auto-init; + }; }; /* @@ -253,6 +257,19 @@ }; }; }; + fans { + compatible = "cros-ec,fans"; + + fan_0 { + pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; + pwm-frequency = <30000>; + tach = <&tach0>; + rpm_min = <1500>; + rpm_start = <1500>; + rpm_max = <6500>; + enable_gpio = <&gpio_fan_enable>; + }; + }; }; &thermistor_3V3_51K1_47K_4050B { @@ -339,3 +356,20 @@ &i2c5_data_gpa5_default>; pinctrl-names = "default"; }; + +/* pwm for fan */ +&pwm7 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm7_gpa7_default>; + pinctrl-names = "default"; +}; + +/* fan tachometer sensor */ +&tach0 { + status = "okay"; + channel = ; + pulses-per-round = <2>; + pinctrl-0 = <&tach1a_gpd7_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/nissa/prj_joxer.conf b/zephyr/projects/nissa/prj_joxer.conf index d067a1bb33..7537e75f51 100644 --- a/zephyr/projects/nissa/prj_joxer.conf +++ b/zephyr/projects/nissa/prj_joxer.conf @@ -7,6 +7,7 @@ CONFIG_BOARD_JOXER=y CONFIG_CROS_FLASH_IT8XXX2=y CONFIG_CROS_SYSTEM_IT8XXX2=y CONFIG_ESPI_IT8XXX2=y +CONFIG_TACH_IT8XXX2=y # Allow more time for the charger to stabilise CONFIG_PLATFORM_EC_POWER_BUTTON_INIT_TIMEOUT=5 @@ -55,4 +56,3 @@ CONFIG_PLATFORM_EC_OCPC_DEF_RBATT_MOHMS=21 CONFIG_VCMP_IT8XXX2=y CONFIG_SENSOR=y CONFIG_SENSOR_SHELL=n -CONFIG_TACH_IT8XXX2=n diff --git a/zephyr/projects/nissa/src/joxer/fan.c b/zephyr/projects/nissa/src/joxer/fan.c new file mode 100644 index 0000000000..8abeb95b39 --- /dev/null +++ b/zephyr/projects/nissa/src/joxer/fan.c @@ -0,0 +1,43 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include + +#include "cros_cbi.h" +#include "fan.h" +#include "gpio/gpio.h" +#include "hooks.h" + +#include "nissa_common.h" + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* + * Joxer fan support + */ +static void fan_init(void) +{ + int ret; + uint32_t val; + /* + * Retrieve the fan config. + */ + ret = cros_cbi_get_fw_config(FW_FAN, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_FAN); + return; + } + if (val != FW_FAN_PRESENT) { + /* Disable the fan */ + fan_set_count(0); + } else { + /* Configure the fan enable GPIO */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_fan_enable), + GPIO_OUTPUT); + } +} +DECLARE_HOOK(HOOK_INIT, fan_init, HOOK_PRIO_POST_FIRST); -- cgit v1.2.1 From 50b0a701664a8d804b5c26114b08bc8a87ec4214 Mon Sep 17 00:00:00 2001 From: "arthur.lin" Date: Tue, 5 Jul 2022 13:15:06 +0800 Subject: Revert "Taniks: Disable RGB keyboard in RO" Revert CL for BL keep light issue after press 3 key enter recovery. BUG=b:237745790 BRANCH=none TEST=make buildall -j This reverts commit 76c71c30927516ebc06029d37a8e66ecb62eb46a. Cq-Depend: chromium:3755243 Signed-off-by: arthur.lin Change-Id: Ice5ed727a5de4ac7c5f63a8fb37668ffffcd1512 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3745101 Tested-by: Parth Malkan Commit-Queue: Parth Malkan Reviewed-by: Parth Malkan --- board/taniks/board.h | 4 ++-- board/taniks/ec.tasklist | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/taniks/board.h b/board/taniks/board.h index 645dde7992..5806765524 100644 --- a/board/taniks/board.h +++ b/board/taniks/board.h @@ -236,10 +236,10 @@ /* RGB Keyboard */ #define GPIO_RGBKBD_SDB_L GPIO_KBMCU_INT_ODL -#ifdef SECTION_IS_RW + #define CONFIG_RGB_KEYBOARD #define CONFIG_LED_DRIVER_AW20198 /* Awinic AW20198 on I2C */ -#endif + #define RGB_GRID0_COL 8 #define RGB_GRID0_ROW 6 diff --git a/board/taniks/ec.tasklist b/board/taniks/ec.tasklist index 13a5229984..12beb39a23 100644 --- a/board/taniks/ec.tasklist +++ b/board/taniks/ec.tasklist @@ -12,7 +12,7 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, HOOKS_TASK_STACK_SIZE) \ - TASK_ALWAYS_RW(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \ + TASK_ALWAYS(RGBKBD, rgbkbd_task, NULL, BASEBOARD_RGBKBD_TASK_STACK_SIZE) \ TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, BASEBOARD_CHG_RAMP_TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 0, TASK_STACK_SIZE) \ -- cgit v1.2.1 From 262627097854b564194376107cc47217fdb87a74 Mon Sep 17 00:00:00 2001 From: "arthur.lin" Date: Tue, 12 Jul 2022 14:00:04 +0800 Subject: taniks: Remove "SECTION_IS_RW" in board_init Remove "SECTION_IS_RW" for BL keep light issue after press 3 key enter recovery. BUG=b:237745790 BRANCH=none TEST=make buildall -j Cq-Depend: chromium:3745101 Signed-off-by: arthur.lin Change-Id: I0ee48b5647265534f47dd2159f4efb91f32ed934 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3755243 Commit-Queue: Parth Malkan Reviewed-by: Parth Malkan --- board/taniks/board.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/board/taniks/board.c b/board/taniks/board.c index 98775a10fd..44e1617545 100644 --- a/board/taniks/board.c +++ b/board/taniks/board.c @@ -60,9 +60,7 @@ __override void board_cbi_init(void) void board_init(void) { -#ifdef SECTION_IS_RW rgbkbd_register_init_setting(&rgbkbd_init_taniks); -#endif } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From c0f4b8bec7ccb755fb1151b01816d6cf5d26fdfa Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Mon, 11 Jul 2022 09:40:53 -0700 Subject: test/printf: Fix invalid %p format test When the size passed to crec_vsnprintf is 0, the function will immediately return with -EC_ERROR_INVAL, which is not testing the code path that these tests were intending. Change the size to the size of the output buffer so the code in vfnprintf is executed. Note that crec_vsnprintf always adds a terminating NUL, so the buffer is modified even though the format was incorrect. BRANCH=none BUG=b:238433667, b:234181908 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: Iade22f224f7f946c3c345f47e0496cd3f1754b63 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756175 Reviewed-by: Denis Brockus --- test/printf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/printf.c b/test/printf.c index 388e0c7e80..8ad84f46c4 100644 --- a/test/printf.c +++ b/test/printf.c @@ -291,11 +291,11 @@ test_static int test_vsnprintf_pointers(void) T(expect_success("55005e00", "%pP", ptr)); T(expect_success(err_str, "%P", ptr)); /* %p by itself is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%p")); + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%p")); /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%p ")); + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%p ")); /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, NO_BYTES_TOUCHED, false, 0, "%pQ")); + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pQ")); /* Test %pb, binary format */ T(expect_success("0", "%pb", BINARY_VALUE(val, 0))); -- cgit v1.2.1 From ebbbdf1a29296004acaa87b57de2059c146e3a3e Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 8 Jul 2022 13:14:15 -0700 Subject: tree: Remove non-standard %pb printf format The binary printf format doesn't provide much over printing hex, so change existing binary prints to hex. Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I55153f0ea1a4864e7819cee0e0f35368baa3f682 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756176 Reviewed-by: Abe Levkoy --- common/charger.c | 2 +- common/printf.c | 14 ++------------ driver/charger/sy21612.c | 2 +- driver/led/is31fl3743b.c | 2 +- driver/nfc/ctn730.c | 1 - driver/temp_sensor/adt7481.c | 11 +++++------ driver/temp_sensor/g753.c | 7 +++---- driver/temp_sensor/g78x.c | 9 ++++----- driver/temp_sensor/tmp411.c | 7 +++---- driver/temp_sensor/tmp432.c | 9 ++++----- include/console.h | 14 -------------- test/printf.c | 19 ++++++------------- 12 files changed, 30 insertions(+), 67 deletions(-) diff --git a/common/charger.c b/common/charger.c index c3f032f908..307e04dd8c 100644 --- a/common/charger.c +++ b/common/charger.c @@ -146,7 +146,7 @@ void print_charger_debug(int chgnum) /* option */ print_item_name("Option:"); if (check_print_error(charger_get_option(&d))) - ccprintf("%pb (0x%04x)\n", BINARY_VALUE(d, 16), d); + ccprintf("(0x%04x)\n", d); /* manufacturer id */ print_item_name("Man id:"); diff --git a/common/printf.c b/common/printf.c index 610a2da94f..f19e6d3b21 100644 --- a/common/printf.c +++ b/common/printf.c @@ -273,8 +273,8 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, ptrspec = *format++; ptrval = va_arg(args, void *); /* - * Avoid null pointer dereference for %ph and - * %pb. %pT and %pP can accept null. + * Avoid null pointer dereference for %ph. + * %pT and %pP can accept null. */ if (ptrval == NULL && ptrspec != 'T' && ptrspec != 'P') @@ -322,16 +322,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, sizeof(uint64_t)) flags |= PF_64BIT; - } else if (ptrspec == 'b') { - /* %pb - Print a binary integer */ - struct binary_print_params *binary = - ptrval; - - v = binary->value; - pad_width = binary->count; - flags |= PF_PADZERO; - base = 2; - } else { return EC_ERROR_INVAL; } diff --git a/driver/charger/sy21612.c b/driver/charger/sy21612.c index 394be47fdc..6089de1ee7 100644 --- a/driver/charger/sy21612.c +++ b/driver/charger/sy21612.c @@ -195,7 +195,7 @@ static int command_sy21612(int argc, char **argv) if (rv) ccprintf(" x (%d)\n", rv); else - ccprintf("%02x - %pb\n", val, BINARY_VALUE(val, 8)); + ccprintf("%02x\n", val); } ccprintf("vbat voltage: %d mV\n", sy21612_get_vbat_voltage()); diff --git a/driver/led/is31fl3743b.c b/driver/led/is31fl3743b.c index eed9c80acc..f9c86284d1 100644 --- a/driver/led/is31fl3743b.c +++ b/driver/led/is31fl3743b.c @@ -83,7 +83,7 @@ static int is31fl3743b_enable(struct rgbkbd *ctx, bool enable) { uint8_t u8 = IS31FL3743B_CONFIG(IS31FL3743B_CFG_SWS_1_11, 0, enable ? 1 : 0); - CPRINTS("Setting config register to 0b%pb", BINARY_VALUE(u8, 8)); + CPRINTS("Setting config register to 0x%x", u8); return is31fl3743b_write(ctx, IS31FL3743B_REG_CONFIG, u8); } diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c index 45598f76b9..16ab40d025 100644 --- a/driver/nfc/ctn730.c +++ b/driver/nfc/ctn730.c @@ -40,7 +40,6 @@ BUILD_ASSERT(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__); static const char *_text_instruction(uint8_t instruction) { - /* TODO: For normal build, use %pb and BINARY_VALUE(res->inst, 6) */ switch (instruction) { case WLC_HOST_CTRL_RESET: return "RESET"; diff --git a/driver/temp_sensor/adt7481.c b/driver/temp_sensor/adt7481.c index f9f771271f..c26247f80c 100644 --- a/driver/temp_sensor/adt7481.c +++ b/driver/temp_sensor/adt7481.c @@ -240,16 +240,16 @@ static int print_status(void) ccprintf("\n"); if (raw_read8(ADT7481_STATUS1_R, &value) == EC_SUCCESS) - ccprintf("STATUS1: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS1: 0x%x\n", value); if (raw_read8(ADT7481_STATUS2_R, &value) == EC_SUCCESS) - ccprintf("STATUS2: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS2: 0x%x\n", value); if (raw_read8(ADT7481_CONFIGURATION1_R, &value) == EC_SUCCESS) - ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG1: 0x%x\n", value); if (raw_read8(ADT7481_CONFIGURATION2, &value) == EC_SUCCESS) - ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG2: 0x%x\n", value); return EC_SUCCESS; } @@ -299,8 +299,7 @@ static int command_adt7481(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", offset, - BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data); return rv; } diff --git a/driver/temp_sensor/g753.c b/driver/temp_sensor/g753.c index c98c54bd3d..5dbc47064a 100644 --- a/driver/temp_sensor/g753.c +++ b/driver/temp_sensor/g753.c @@ -120,10 +120,10 @@ static int print_status(void) ccprintf("\n"); if (raw_read8(G753_STATUS, &value) == EC_SUCCESS) - ccprintf("STATUS: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS: 0x%x\n", value); if (raw_read8(G753_CONFIGURATION_R, &value) == EC_SUCCESS) - ccprintf("CONFIG: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG: 0x%x\n", value); return EC_SUCCESS; } @@ -157,8 +157,7 @@ static int command_g753(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", offset, - BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data); return rv; } diff --git a/driver/temp_sensor/g78x.c b/driver/temp_sensor/g78x.c index 84bddfe719..22af57c2d8 100644 --- a/driver/temp_sensor/g78x.c +++ b/driver/temp_sensor/g78x.c @@ -158,15 +158,15 @@ static int print_status(void) ccprintf("\n"); if (raw_read8(G78X_STATUS, &value) == EC_SUCCESS) - ccprintf("STATUS: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS: 0x%x\n", value); #ifdef CONFIG_TEMP_SENSOR_G782 if (raw_read8(G78X_STATUS1, &value) == EC_SUCCESS) - ccprintf("STATUS1: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS1: 0x%x\n", value); #endif if (raw_read8(G78X_CONFIGURATION_R, &value) == EC_SUCCESS) - ccprintf("CONFIG: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG: 0x%x\n", value); return EC_SUCCESS; } @@ -200,8 +200,7 @@ static int command_g78x(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", offset, - BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data); return rv; } diff --git a/driver/temp_sensor/tmp411.c b/driver/temp_sensor/tmp411.c index 482f31a9c6..804fa30644 100644 --- a/driver/temp_sensor/tmp411.c +++ b/driver/temp_sensor/tmp411.c @@ -225,10 +225,10 @@ static int print_status(void) ccprintf("\n"); if (raw_read8(TMP411_STATUS_R, &value) == EC_SUCCESS) - ccprintf("STATUS: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS: 0x%x\n", value); if (raw_read8(TMP411_CONFIGURATION1_R, &value) == EC_SUCCESS) - ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG1: 0x%x\n", value); return EC_SUCCESS; } @@ -278,8 +278,7 @@ static int command_tmp411(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", offset, - BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data); return rv; } diff --git a/driver/temp_sensor/tmp432.c b/driver/temp_sensor/tmp432.c index b05e986ade..54414a2f3e 100644 --- a/driver/temp_sensor/tmp432.c +++ b/driver/temp_sensor/tmp432.c @@ -286,13 +286,13 @@ static int print_status(void) ccprintf("\n"); if (raw_read8(TMP432_STATUS, &value) == EC_SUCCESS) - ccprintf("STATUS: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("STATUS: 0x%x\n", value); if (raw_read8(TMP432_CONFIGURATION1_R, &value) == EC_SUCCESS) - ccprintf("CONFIG1: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG1: 0x%x\n", value); if (raw_read8(TMP432_CONFIGURATION2_R, &value) == EC_SUCCESS) - ccprintf("CONFIG2: %pb\n", BINARY_VALUE(value, 8)); + ccprintf("CONFIG2: 0x%x\n", value); return EC_SUCCESS; } @@ -342,8 +342,7 @@ static int command_tmp432(int argc, char **argv) rv = raw_read8(offset, &data); if (rv < 0) return rv; - ccprintf("Byte at offset 0x%02x is %pb\n", offset, - BINARY_VALUE(data, 8)); + ccprintf("Byte at offset 0x%02x is 0x%x\n", offset, data); return rv; } diff --git a/include/console.h b/include/console.h index addee30386..7adbb1d77c 100644 --- a/include/console.h +++ b/include/console.h @@ -58,20 +58,6 @@ struct hex_buffer_params { (&(const struct hex_buffer_params){ .buffer = (_buffer), \ .size = (_size) }) -/* - * Define parameters to printing in binary: the value to print, and the number - * of digits to print. - */ - -struct binary_print_params { - unsigned int value; - uint8_t count; -}; - -#define BINARY_VALUE(_value, _count) \ - (&(const struct binary_print_params){ .value = (_value), \ - .count = (_count) }) - #define PRINTF_TIMESTAMP_NOW NULL /* Console command; used by DECLARE_CONSOLE_COMMAND macro. */ diff --git a/test/printf.c b/test/printf.c index 8ad84f46c4..90d146b45d 100644 --- a/test/printf.c +++ b/test/printf.c @@ -286,7 +286,6 @@ test_static int test_vsnprintf_long(void) test_static int test_vsnprintf_pointers(void) { void *ptr = (void *)0x55005E00; - unsigned int val = 0; T(expect_success("55005e00", "%pP", ptr)); T(expect_success(err_str, "%P", ptr)); @@ -297,18 +296,12 @@ test_static int test_vsnprintf_pointers(void) /* %p with an unknown suffix is invalid */ T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pQ")); - /* Test %pb, binary format */ - T(expect_success("0", "%pb", BINARY_VALUE(val, 0))); - val = 0x5E; - T(expect_success("1011110", "%pb", BINARY_VALUE(val, 0))); - T(expect_success("0000000001011110", "%pb", BINARY_VALUE(val, 16))); - val = 0x12345678; - T(expect_success("10010001101000101011001111000", "%pb", - BINARY_VALUE(val, 0))); - val = 0xFEDCBA90; - /* Test a number that makes the longest string possible */ - T(expect_success("11111110110111001011101010010000", "%pb", - BINARY_VALUE(val, 0))); + /* + * Test %pb, which used to print binary, but is non-standard and no + * longer supported. + */ + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pb", 0xff)); + return EC_SUCCESS; } -- cgit v1.2.1 From 5f359117fa1973413c88420bf3d81a79e541a47b Mon Sep 17 00:00:00 2001 From: Josh Tsai Date: Fri, 8 Jul 2022 08:28:31 +0800 Subject: banshee: keyboard init fix Define the CONFIG_I2C_BITBANG to read the cbi board version early. BRANCH=none BUG=b:231265647;b:238683420 TEST=manually triggering recovery on banshee id1 Signed-off-by: Josh Tsai Change-Id: I19a8915f0b89aebf48ac3f166a80751a499db514 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750970 Reviewed-by: Boris Mittelberg Reviewed-by: Jeremy Lin Commit-Queue: Boris Mittelberg Reviewed-by: Elthan Huang --- board/banshee/board.c | 30 +++++++++++++++++++++++++----- board/banshee/board.h | 9 +++++++++ board/banshee/i2c.c | 14 ++++++++++++++ 3 files changed, 48 insertions(+), 5 deletions(-) diff --git a/board/banshee/board.c b/board/banshee/board.c index adb233c85f..c751400d79 100644 --- a/board/banshee/board.c +++ b/board/banshee/board.c @@ -10,6 +10,7 @@ #include "common.h" #include "compile_time_macros.h" #include "console.h" +#include "cros_board_info.h" #include "gpio.h" #include "gpio_signal.h" #include "hooks.h" @@ -75,12 +76,19 @@ void battery_present_interrupt(enum gpio_signal signal) hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0); } -void board_init(void) +static void configure_keyboard(void) { - int board_id = get_board_id(); + uint32_t cbi_val; + uint32_t board_id = 1; - gpio_enable_interrupt(GPIO_EC_BATT_PRES_ODL); - hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0); + /* Board ID */ + if (cbi_get_board_version(&cbi_val) != EC_SUCCESS || + cbi_val > UINT8_MAX) + CPRINTS("CBI: Read Board ID failed"); + else + board_id = cbi_val; + + CPRINTS("Read Board ID: %d", board_id); if (board_id == 0) { /* keyboard_col2_inverted on board id 0 */ @@ -102,6 +110,18 @@ void board_init(void) GPIO_ALT_FUNC_DEFAULT); } - board_id_keyboard_col_inverted(board_id); + board_id_keyboard_col_inverted((int)board_id); +} + +void board_init(void) +{ + gpio_enable_interrupt(GPIO_EC_BATT_PRES_ODL); + hook_call_deferred(&board_set_charger_current_limit_deferred_data, 0); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + +__override void board_pre_task_i2c_peripheral_init(void) +{ + /* Configure board specific keyboard */ + configure_keyboard(); +} diff --git a/board/banshee/board.h b/board/banshee/board.h index e90e1f84f0..2627ce7556 100644 --- a/board/banshee/board.h +++ b/board/banshee/board.h @@ -194,6 +194,15 @@ #include "registers.h" #include "usbc_config.h" +/* I2C access in polling mode before task is initialized */ +#define CONFIG_I2C_BITBANG + +enum banshee_bitbang_i2c_channel { + I2C_BITBANG_CHAN_BRD_ID, + I2C_BITBANG_CHAN_COUNT +}; +#define I2C_BITBANG_PORT_COUNT I2C_BITBANG_CHAN_COUNT + enum adc_channel { ADC_TEMP_SENSOR_1_DDR_SOC, ADC_TEMP_SENSOR_2_AMBIENT, diff --git a/board/banshee/i2c.c b/board/banshee/i2c.c index 17dc4cc400..556f27822e 100644 --- a/board/banshee/i2c.c +++ b/board/banshee/i2c.c @@ -7,6 +7,7 @@ #include "compile_time_macros.h" #include "hooks.h" #include "i2c.h" +#include "i2c_bitbang.h" #define BOARD_ID_FAST_PLUS_CAPABLE 2 @@ -78,3 +79,16 @@ const struct i2c_port_t i2c_ports[] = { }, }; const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +const struct i2c_port_t i2c_bitbang_ports[] = { + [I2C_BITBANG_CHAN_BRD_ID] = { + .name = "bitbang_brd_id", + .port = I2C_PORT_EEPROM, + .kbps = 100, + .scl = GPIO_EC_I2C_MISC_SCL_R, + .sda = GPIO_EC_I2C_MISC_SDA_R, + .drv = &bitbang_drv, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(i2c_bitbang_ports) == I2C_BITBANG_CHAN_COUNT); +const unsigned int i2c_bitbang_ports_used = ARRAY_SIZE(i2c_bitbang_ports); -- cgit v1.2.1 From 9c452e6150265a652b36cfa0a5d67775ca442b17 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Mon, 11 Jul 2022 11:46:15 -0700 Subject: tree: remove unused P9221 wireless charger BRANCH=none BUG=none TEST=Add 20 blank lines to common/charge_manager.c and 5 blank lines to common/usb_charger.c ./util/compare_build.sh -b all -j 120 = MATCH Signed-off-by: Tom Hughes Change-Id: I0e1364f64fa9f749830cbaa4833fc856eed9abef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756173 Reviewed-by: Keith Short --- common/charge_manager.c | 20 -- common/usb_charger.c | 5 - driver/charger/rt946x.c | 9 - driver/wpc/p9221.c | 799 ----------------------------------------------- include/charge_manager.h | 12 - include/config.h | 1 - util/config_allowed.txt | 1 - 7 files changed, 847 deletions(-) delete mode 100644 driver/wpc/p9221.c diff --git a/common/charge_manager.c b/common/charge_manager.c index cad4123cb8..676c4d283e 100644 --- a/common/charge_manager.c +++ b/common/charge_manager.c @@ -70,11 +70,6 @@ __overridable const int supplier_priority[] = { [CHARGE_SUPPLIER_OTHER] = 4, [CHARGE_SUPPLIER_VBUS] = 4, #endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - [CHARGE_SUPPLIER_WPC_BPP] = 5, - [CHARGE_SUPPLIER_WPC_EPP] = 5, - [CHARGE_SUPPLIER_WPC_GPP] = 5, -#endif }; BUILD_ASSERT(ARRAY_SIZE(supplier_priority) == CHARGE_SUPPLIER_COUNT); @@ -499,28 +494,13 @@ charge_manager_fill_power_info(int port, r->type = USB_CHG_TYPE_VBUS; break; #endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - /* - * Todo:need kernel add wpc device node in power_supply - * before that use USB_CHG_TYPE_PROPRIETARY to present WPC. - */ - case CHARGE_SUPPLIER_WPC_BPP: - case CHARGE_SUPPLIER_WPC_EPP: - case CHARGE_SUPPLIER_WPC_GPP: - r->type = USB_CHG_TYPE_PROPRIETARY; - break; -#endif #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 case CHARGE_SUPPLIER_DEDICATED: r->type = USB_CHG_TYPE_DEDICATED; break; #endif default: -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - r->type = USB_CHG_TYPE_VBUS; -#else r->type = USB_CHG_TYPE_OTHER; -#endif } if (IS_ENABLED(CONFIG_USB_PD_DPS) && dps_is_enabled() && diff --git a/common/usb_charger.c b/common/usb_charger.c index 3e4b66a412..3933634cbf 100644 --- a/common/usb_charger.c +++ b/common/usb_charger.c @@ -120,11 +120,6 @@ void usb_charger_reset_charge(int port) #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, port, NULL); #endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_BPP, port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_EPP, port, NULL); - charge_manager_update_charge(CHARGE_SUPPLIER_WPC_GPP, port, NULL); -#endif } void usb_charger_task_set_event(int port, uint8_t event) diff --git a/driver/charger/rt946x.c b/driver/charger/rt946x.c index 9949cfa12a..15c90721e2 100644 --- a/driver/charger/rt946x.c +++ b/driver/charger/rt946x.c @@ -1567,12 +1567,6 @@ static void rt946x_usb_charger_task_init(const int unused_port) CPRINTS("BC12 type %d", bc12_type); if (bc12_type == CHARGE_SUPPLIER_NONE) goto bc12_none; - if (IS_ENABLED(CONFIG_WIRELESS_CHARGER_P9221_R7) && - bc12_type == CHARGE_SUPPLIER_BC12_SDP && - wpc_chip_is_online()) { - p9221_notify_vbus_change(1); - CPRINTS("WPC ON"); - } if (bc12_type == CHARGE_SUPPLIER_BC12_SDP && ++bc12_cnt < max_bc12_cnt) { /* @@ -1594,9 +1588,6 @@ static void rt946x_usb_charger_task_init(const int unused_port) bc12_type != CHARGE_SUPPLIER_NONE) { CPRINTS("VBUS detached"); bc12_cnt = 0; -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - p9221_notify_vbus_change(0); -#endif charge_manager_update_charge(bc12_type, 0, NULL); } diff --git a/driver/wpc/p9221.c b/driver/wpc/p9221.c deleted file mode 100644 index 951b7b0f38..0000000000 --- a/driver/wpc/p9221.c +++ /dev/null @@ -1,799 +0,0 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * IDT P9221-R7 Wireless Power Receiver driver. - */ - -#include "p9221.h" -#include "charge_manager.h" -#include "chipset.h" -#include "common.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "power.h" -#include "tcpm/tcpm.h" -#include "timer.h" -#include "usb_charge.h" -#include "usb_pd.h" -#include "util.h" -#include -#include "printf.h" - -#define CPRINTS(format, args...) cprints(CC_USBPD, "WPC " format, ##args) - -#define P9221_TX_TIMEOUT_MS (20 * 1000 * 1000) -#define P9221_DCIN_TIMEOUT_MS (2 * 1000 * 1000) -#define P9221_VRECT_TIMEOUT_MS (2 * 1000 * 1000) -#define P9221_NOTIFIER_DELAY_MS (80 * 1000) -#define P9221R7_ILIM_MAX_UA (1600 * 1000) -#define P9221R7_OVER_CHECK_NUM 3 - -#define OVC_LIMIT 1 -#define OVC_THRESHOLD 1400000 -#define OVC_BACKOFF_LIMIT 900000 -#define OVC_BACKOFF_AMOUNT 100000 - -/* P9221 parameters */ -static struct wpc_charger_info p9221_charger_info = { - .online = false, - .i2c_port = I2C_PORT_WPC, - .pp_buf_valid = false, -}; - -static struct wpc_charger_info *wpc = &p9221_charger_info; - -static void p9221_set_offline(void); - -static const uint32_t p9221_ov_set_lut[] = { 17000000, 20000000, 15000000, - 13000000, 11000000, 11000000, - 11000000, 11000000 }; - -static int p9221_reg_is_8_bit(uint16_t reg) -{ - switch (reg) { - case P9221_CHIP_REVISION_REG: - case P9221R7_VOUT_SET_REG: - case P9221R7_ILIM_SET_REG: - case P9221R7_CHARGE_STAT_REG: - case P9221R7_EPT_REG: - case P9221R7_SYSTEM_MODE_REG: - case P9221R7_COM_CHAN_RESET_REG: - case P9221R7_COM_CHAN_SEND_SIZE_REG: - case P9221R7_COM_CHAN_SEND_IDX_REG: - case P9221R7_COM_CHAN_RECV_SIZE_REG: - case P9221R7_COM_CHAN_RECV_IDX_REG: - case P9221R7_DEBUG_REG: - case P9221R7_EPP_Q_FACTOR_REG: - case P9221R7_EPP_TX_GUARANTEED_POWER_REG: - case P9221R7_EPP_TX_POTENTIAL_POWER_REG: - case P9221R7_EPP_TX_CAPABILITY_FLAGS_REG: - case P9221R7_EPP_RENEGOTIATION_REG: - case P9221R7_EPP_CUR_RPP_HEADER_REG: - case P9221R7_EPP_CUR_NEGOTIATED_POWER_REG: - case P9221R7_EPP_CUR_MAXIMUM_POWER_REG: - case P9221R7_EPP_CUR_FSK_MODULATION_REG: - case P9221R7_EPP_REQ_RPP_HEADER_REG: - case P9221R7_EPP_REQ_NEGOTIATED_POWER_REG: - case P9221R7_EPP_REQ_MAXIMUM_POWER_REG: - case P9221R7_EPP_REQ_FSK_MODULATION_REG: - case P9221R7_VRECT_TARGET_REG: - case P9221R7_VRECT_KNEE_REG: - case P9221R7_FOD_SECTION_REG: - case P9221R7_VRECT_ADJ_REG: - case P9221R7_ALIGN_X_ADC_REG: - case P9221R7_ALIGN_Y_ADC_REG: - case P9221R7_ASK_MODULATION_DEPTH_REG: - case P9221R7_OVSET_REG: - case P9221R7_EPP_TX_SPEC_REV_REG: - return true; - default: - return false; - } -} - -static int p9221_read8(uint16_t reg, int *val) -{ - return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, - 1); -} - -static int p9221_write8(uint16_t reg, int val) -{ - return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, - 1); -} - -static int p9221_read16(uint16_t reg, int *val) -{ - return i2c_read_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, - 2); -} - -static int p9221_write16(uint16_t reg, int val) -{ - return i2c_write_offset16(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, val, - 2); -} - -static int p9221_block_read(uint16_t reg, uint8_t *data, int len) -{ - return i2c_read_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, - data, len); -} - -static int p9221_block_write(uint16_t reg, uint8_t *data, int len) -{ - return i2c_write_offset16_block(wpc->i2c_port, P9221_R7_ADDR_FLAGS, reg, - data, len); -} - -static int p9221_set_cmd_reg(uint8_t cmd) -{ - int cur_cmd; - int retry; - int ret; - - for (retry = 0; retry < P9221_COM_CHAN_RETRIES; retry++) { - ret = p9221_read8(P9221_COM_REG, &cur_cmd); - if (ret == EC_SUCCESS && cur_cmd == 0) - break; - msleep(25); - } - - if (retry >= P9221_COM_CHAN_RETRIES) { - CPRINTS("Failed to wait for cmd free %02x", cur_cmd); - return EC_ERROR_TIMEOUT; - } - - ret = p9221_write8(P9221_COM_REG, cmd); - if (ret) - CPRINTS("Failed to set cmd reg %02x: %d", cmd, ret); - - return ret; -} - -/* Convert a register value to uV, Hz, or uA */ -static int p9221_convert_reg_r7(uint16_t reg, uint16_t raw_data, uint32_t *val) -{ - switch (reg) { - case P9221R7_ALIGN_X_ADC_REG: /* raw */ - case P9221R7_ALIGN_Y_ADC_REG: /* raw */ - *val = raw_data; - break; - case P9221R7_VOUT_ADC_REG: /* 12-bit ADC raw */ - case P9221R7_IOUT_ADC_REG: /* 12-bit ADC raw */ - case P9221R7_DIE_TEMP_ADC_REG: /* 12-bit ADC raw */ - case P9221R7_EXT_TEMP_REG: - *val = raw_data & 0xFFF; - break; - case P9221R7_VOUT_SET_REG: /* 0.1V -> uV */ - *val = raw_data * 100 * 1000; - break; - case P9221R7_IOUT_REG: /* mA -> uA */ - case P9221R7_VRECT_REG: /* mV -> uV */ - case P9221R7_VOUT_REG: /* mV -> uV */ - case P9221R7_OP_FREQ_REG: /* kHz -> Hz */ - case P9221R7_TX_PINGFREQ_REG: /* kHz -> Hz */ - *val = raw_data * 1000; - break; - case P9221R7_ILIM_SET_REG: /* 100mA -> uA, 200mA offset */ - *val = ((raw_data * 100) + 200) * 1000; - break; - case P9221R7_OVSET_REG: /* uV */ - raw_data &= P9221R7_OVSET_MASK; - *val = p9221_ov_set_lut[raw_data]; - break; - default: - return -2; - } - - return 0; -} - -static int p9221_reg_read_converted(uint16_t reg, uint32_t *val) -{ - int ret; - int data; - - if (p9221_reg_is_8_bit(reg)) - ret = p9221_read8(reg, &data); - else - ret = p9221_read16(reg, &data); - - if (ret) - return ret; - - return p9221_convert_reg_r7(reg, data, val); -} - -static int p9221_is_online(void) -{ - int chip_id; - - if (p9221_read16(P9221_CHIP_ID_REG, &chip_id) || - chip_id != P9221_CHIP_ID) - return false; - else - return true; -} - -int wpc_chip_is_online(void) -{ - return p9221_is_online(); -} - -void p9221_interrupt(enum gpio_signal signal) -{ - task_wake(TASK_ID_WPC); -} - -static int p9221r7_clear_interrupts(uint16_t mask) -{ - int ret; - - ret = p9221_write16(P9221R7_INT_CLEAR_REG, mask); - if (ret) { - CPRINTS("Failed to clear INT reg: %d", ret); - return ret; - } - - ret = p9221_set_cmd_reg(P9221_COM_CLEAR_INT_MASK); - if (ret) - CPRINTS("Failed to reset INT: %d", ret); - - return ret; -} - -/* - * Enable interrupts on the P9221 R7, note we don't really need to disable - * interrupts since when the device goes out of field, the P9221 is reset. - */ -static int p9221_enable_interrupts_r7(void) -{ - uint16_t mask = 0; - int ret; - - CPRINTS("Enable interrupts"); - - mask = P9221R7_STAT_LIMIT_MASK | P9221R7_STAT_CC_MASK | - P9221_STAT_VRECT; - - p9221r7_clear_interrupts(mask); - - ret = p9221_write8(P9221_INT_ENABLE_REG, mask); - if (ret) - CPRINTS("Failed to enable INTs: %d", ret); - return ret; -} - -static int p9221_send_csp(uint8_t status) -{ - int ret; - - CPRINTS("Send CSP=%d", status); - mutex_lock(&wpc->cmd_lock); - - ret = p9221_write8(P9221R7_CHARGE_STAT_REG, status); - if (ret == EC_SUCCESS) - ret = p9221_set_cmd_reg(P9221R7_COM_SENDCSP); - - mutex_unlock(&wpc->cmd_lock); - return ret; -} - -static int p9221_send_eop(uint8_t reason) -{ - int rv; - - CPRINTS("Send EOP reason=%d", reason); - mutex_lock(&wpc->cmd_lock); - - rv = p9221_write8(P9221R7_EPT_REG, reason); - if (rv == EC_SUCCESS) - rv = p9221_set_cmd_reg(P9221R7_COM_SENDEPT); - - mutex_unlock(&wpc->cmd_lock); - return rv; -} - -static void print_current_samples(uint32_t *iout_val, int count) -{ - int i; - char temp[P9221R7_OVER_CHECK_NUM * 9 + 1] = { 0 }; - - for (i = 0; i < count; i++) - snprintf(temp + i * 9, sizeof(temp) - i * 9, "%08x ", - iout_val[i]); - CPRINTS("OVER IOUT_SAMPLES: %s", temp); -} - -/* - * Number of times to poll the status to see if the current limit condition - * was transient or not. - */ -static void p9221_limit_handler_r7(uint16_t orign_irq_src) -{ - uint8_t reason; - int i; - int ret; - int ovc_count = 0; - uint32_t iout_val[P9221R7_OVER_CHECK_NUM] = { 0 }; - int irq_src = (int)orign_irq_src; - - CPRINTS("OVER INT: %02x", irq_src); - - if (irq_src & P9221R7_STAT_OVV) { - reason = P9221_EOP_OVER_VOLT; - goto send_eop; - } - - if (irq_src & P9221R7_STAT_OVT) { - reason = P9221_EOP_OVER_TEMP; - goto send_eop; - } - - if ((irq_src & P9221R7_STAT_UV) && !(irq_src & P9221R7_STAT_OVC)) - return; - - reason = P9221_EOP_OVER_CURRENT; - for (i = 0; i < P9221R7_OVER_CHECK_NUM; i++) { - ret = p9221r7_clear_interrupts(irq_src & - P9221R7_STAT_LIMIT_MASK); - msleep(50); - if (ret) - continue; - - ret = p9221_reg_read_converted(P9221R7_IOUT_REG, &iout_val[i]); - if (ret) { - CPRINTS("Failed to read IOUT[%d]: %d", i, ret); - continue; - } else if (iout_val[i] > OVC_THRESHOLD) { - ovc_count++; - } - - ret = p9221_read16(P9221_STATUS_REG, &irq_src); - if (ret) { - CPRINTS("Failed to read status: %d", ret); - continue; - } - - if ((irq_src & P9221R7_STAT_OVC) == 0) { - print_current_samples(iout_val, i + 1); - CPRINTS("OVER condition %04x cleared after %d tries", - irq_src, i); - return; - } - - CPRINTS("OVER status is still %04x, retry", irq_src); - } - - if (ovc_count < OVC_LIMIT) { - print_current_samples(iout_val, P9221R7_OVER_CHECK_NUM); - CPRINTS("ovc_threshold=%d, ovc_count=%d, ovc_limit=%d", - OVC_THRESHOLD, ovc_count, OVC_LIMIT); - return; - } - -send_eop: - CPRINTS("OVER is %04x, sending EOP %d", irq_src, reason); - - ret = p9221_send_eop(reason); - if (ret) - CPRINTS("Failed to send EOP %d: %d", reason, ret); -} - -static void p9221_abort_transfers(void) -{ - wpc->tx_busy = false; - wpc->tx_done = true; - wpc->rx_done = true; - wpc->rx_len = 0; -} - -/* Handler for r7 and R7 chips */ -static void p9221r7_irq_handler(uint16_t irq_src) -{ - int res; - - if (irq_src & P9221R7_STAT_LIMIT_MASK) - p9221_limit_handler_r7(irq_src); - - /* Receive complete */ - if (irq_src & P9221R7_STAT_CCDATARCVD) { - int rxlen = 0; - - res = p9221_read8(P9221R7_COM_CHAN_RECV_SIZE_REG, &rxlen); - if (res) - CPRINTS("Failed to read len: %d", res); - - if (rxlen) { - res = p9221_block_read(P9221R7_DATA_RECV_BUF_START, - wpc->rx_buf, rxlen); - if (res) { - CPRINTS("Failed to read CC data: %d", res); - rxlen = 0; - } - - wpc->rx_len = rxlen; - wpc->rx_done = true; - } - } - - /* Send complete */ - if (irq_src & P9221R7_STAT_CCSENDBUSY) { - wpc->tx_busy = false; - wpc->tx_done = true; - } - - /* Proprietary packet */ - if (irq_src & P9221R7_STAT_PPRCVD) { - res = p9221_block_read(P9221R7_DATA_RECV_BUF_START, wpc->pp_buf, - sizeof(wpc->pp_buf)); - if (res) { - CPRINTS("Failed to read PP: %d", res); - wpc->pp_buf_valid = false; - return; - } - - /* We only care about PP which come with 0x4F header */ - wpc->pp_buf_valid = (wpc->pp_buf[0] == 0x4F); - - hexdump(wpc->pp_buf, sizeof(wpc->pp_buf)); - } - - /* CC Reset complete */ - if (irq_src & P9221R7_STAT_CCRESET) - p9221_abort_transfers(); -} - -static int p9221_is_epp(void) -{ - int ret, reg; - uint32_t vout_uv; - - if (p9221_read8(P9221R7_SYSTEM_MODE_REG, ®) == EC_SUCCESS) - return reg & P9221R7_SYSTEM_MODE_EXTENDED_MASK; - - /* Check based on power supply voltage */ - ret = p9221_reg_read_converted(P9221R7_VOUT_ADC_REG, &vout_uv); - if (ret) { - CPRINTS("Failed to read VOUT_ADC: %d", ret); - return false; - } - - CPRINTS("Voltage is %duV", vout_uv); - if (vout_uv > P9221_EPP_THRESHOLD_UV) - return true; - - return false; -} - -static void p9221_config_fod(void) -{ - int epp; - uint8_t *fod; - int fod_len; - int ret; - int retries = 3; - - CPRINTS("Config FOD"); - - epp = p9221_is_epp(); - fod_len = epp ? board_get_epp_fod(&fod) : board_get_fod(&fod); - if (!fod_len || !fod) { - CPRINTS("FOD data not found"); - return; - } - - while (retries) { - uint8_t fod_read[fod_len]; - - CPRINTS("Writing %s FOD (n=%d try=%d)", epp ? "EPP" : "BPP", - fod_len, retries); - - ret = p9221_block_write(P9221R7_FOD_REG, fod, fod_len); - if (ret) - goto no_fod; - - /* Verify the FOD has been written properly */ - ret = p9221_block_read(P9221R7_FOD_REG, fod_read, fod_len); - if (ret) - goto no_fod; - - if (memcmp(fod, fod_read, fod_len) == 0) - return; - - hexdump(fod_read, fod_len); - - retries--; - msleep(100); - } - -no_fod: - CPRINTS("Failed to set FOD. retries:%d ret:%d", retries, ret); -} - -static void p9221_set_online(void) -{ - int ret; - - CPRINTS("Set online"); - - wpc->online = true; - - wpc->tx_busy = false; - wpc->tx_done = true; - wpc->rx_done = false; - wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP; - - ret = p9221_enable_interrupts_r7(); - if (ret) - CPRINTS("Failed to enable INT: %d", ret); - - /* NOTE: depends on _is_epp() which is not valid until DC_IN */ - p9221_config_fod(); -} - -static void p9221_vbus_check_timeout(void) -{ - CPRINTS("Timeout VBUS, online=%d", wpc->online); - if (wpc->online) - p9221_set_offline(); -} -DECLARE_DEFERRED(p9221_vbus_check_timeout); - -static void p9221_set_offline(void) -{ - CPRINTS("Set offline"); - - wpc->online = false; - /* Reset PP buf so we can get a new serial number next time around */ - wpc->pp_buf_valid = false; - - p9221_abort_transfers(); - - hook_call_deferred(&p9221_vbus_check_timeout_data, -1); -} - -/* P9221_NOTIFIER_DELAY_MS from VRECTON */ -static int p9221_notifier_check_det(void) -{ - if (wpc->online) - goto done; - - /* send out a FOD but is_epp() is still invalid */ - p9221_set_online(); - - /* Give the vbus 2 seconds to come up. */ - CPRINTS("Waiting VBUS"); - hook_call_deferred(&p9221_vbus_check_timeout_data, -1); - hook_call_deferred(&p9221_vbus_check_timeout_data, - P9221_DCIN_TIMEOUT_MS); - -done: - wpc->p9221_check_det = false; - return 0; -} - -static int p9221_get_charge_supplier(void) -{ - if (!wpc->online) - return EC_ERROR_UNKNOWN; - - if (p9221_is_epp()) { - uint32_t tx_id; - int txmf_id; - int ret; - - wpc->charge_supplier = CHARGE_SUPPLIER_WPC_EPP; - - ret = p9221_read16(P9221R7_EPP_TX_MFG_CODE_REG, &txmf_id); - if (ret || txmf_id != P9221_GPP_TX_MF_ID) - return ret; - - ret = p9221_block_read(P9221R7_PROP_TX_ID_REG, - (uint8_t *)&tx_id, - P9221R7_PROP_TX_ID_SIZE); - if (ret) - return ret; - - if (tx_id & P9221R7_PROP_TX_ID_GPP_MASK) - wpc->charge_supplier = CHARGE_SUPPLIER_WPC_GPP; - - CPRINTS("txmf_id=0x%04x tx_id=0x%08x supplier=%d", txmf_id, - tx_id, wpc->charge_supplier); - } else { - wpc->charge_supplier = CHARGE_SUPPLIER_WPC_BPP; - CPRINTS("supplier=%d", wpc->charge_supplier); - } - - return EC_SUCCESS; -} - -static int p9221_get_icl(int charge_supplier) -{ - switch (charge_supplier) { - case CHARGE_SUPPLIER_WPC_EPP: - case CHARGE_SUPPLIER_WPC_GPP: - return P9221_DC_ICL_EPP_MA; - case CHARGE_SUPPLIER_WPC_BPP: - default: - return P9221_DC_ICL_BPP_MA; - } -} - -static int p9221_get_ivl(int charge_supplier) -{ - switch (charge_supplier) { - case CHARGE_SUPPLIER_WPC_EPP: - case CHARGE_SUPPLIER_WPC_GPP: - return P9221_DC_IVL_EPP_MV; - case CHARGE_SUPPLIER_WPC_BPP: - default: - return P9221_DC_IVL_BPP_MV; - } -} - -static void p9221_update_charger(int type, struct charge_port_info *chg) -{ - if (!chg) - charge_manager_update_dualrole(0, CAP_UNKNOWN); - else - charge_manager_update_dualrole(0, CAP_DEDICATED); - - charge_manager_update_charge(type, 0, chg); -} - -static int p9221_reg_write_converted_r7(uint16_t reg, uint32_t val) -{ - int ret = 0; - uint16_t data; - int i; - /* Do the appropriate conversion */ - switch (reg) { - case P9221R7_ILIM_SET_REG: - /* uA -> 0.1A, offset 0.2A */ - if ((val < 200000) || (val > 1600000)) - return -EC_ERROR_INVAL; - data = (val / (100 * 1000)) - 2; - break; - case P9221R7_VOUT_SET_REG: - /* uV -> 0.1V */ - val /= 1000; - if (val < 3500 || val > 9000) - return -EC_ERROR_INVAL; - data = val / 100; - break; - case P9221R7_OVSET_REG: - /* uV */ - for (i = 0; i < ARRAY_SIZE(p9221_ov_set_lut); i++) { - if (val == p9221_ov_set_lut[i]) - break; - } - if (i == ARRAY_SIZE(p9221_ov_set_lut)) - return -EC_ERROR_INVAL; - data = i; - break; - default: - return -EC_ERROR_INVAL; - } - if (p9221_reg_is_8_bit(reg)) - ret = p9221_write8(reg, data); - else - ret = p9221_write16(reg, data); - return ret; -} - -static int p9221_set_dc_icl(void) -{ - /* Increase the IOUT limit */ - if (p9221_reg_write_converted_r7(P9221R7_ILIM_SET_REG, - P9221R7_ILIM_MAX_UA)) - CPRINTS("%s set rx_iout limit fail.", __func__); - - return EC_SUCCESS; -} - -static void p9221_notifier_check_vbus(void) -{ - struct charge_port_info chg; - - wpc->p9221_check_vbus = false; - - CPRINTS("%s online:%d vbus:%d", __func__, wpc->online, - wpc->vbus_status); - - /* - * We now have confirmation from DC_IN, kill the timer, p9221_online - * will be set by this function. - */ - hook_call_deferred(&p9221_vbus_check_timeout_data, -1); - - if (wpc->vbus_status) { - /* WPC VBUS on ,Always write FOD, check dc_icl, send CSP */ - p9221_set_dc_icl(); - p9221_config_fod(); - - p9221_send_csp(1); - - /* when wpc vbus attached after 2s, set wpc online */ - if (!wpc->online) - p9221_set_online(); - - /* WPC VBUS on , update charge voltage and current */ - p9221_get_charge_supplier(); - chg.voltage = p9221_get_ivl(wpc->charge_supplier); - chg.current = p9221_get_icl(wpc->charge_supplier); - - p9221_update_charger(wpc->charge_supplier, &chg); - } else { - /* - * Vbus detached, set wpc offline and update wpc charge voltage - * and current to zero. - */ - if (wpc->online) { - p9221_set_offline(); - p9221_update_charger(wpc->charge_supplier, NULL); - } - } - - CPRINTS("check_vbus changed on:%d vbus:%d", wpc->online, - wpc->vbus_status); -} - -static void p9221_detect_work(void) -{ - CPRINTS("%s online:%d check_vbus:%d check_det:%d vbus:%d", __func__, - wpc->online, wpc->p9221_check_vbus, wpc->p9221_check_det, - wpc->vbus_status); - - /* Step 1 */ - if (wpc->p9221_check_det) - p9221_notifier_check_det(); - - /* Step 2 */ - if (wpc->p9221_check_vbus) - p9221_notifier_check_vbus(); -} -DECLARE_DEFERRED(p9221_detect_work); - -void p9221_notify_vbus_change(int vbus) -{ - wpc->p9221_check_vbus = true; - wpc->vbus_status = vbus; - hook_call_deferred(&p9221_detect_work_data, P9221_NOTIFIER_DELAY_MS); -} - -void wireless_power_charger_task(void *u) -{ - while (1) { - int ret, irq_src; - task_wait_event(-1); - - ret = p9221_read16(P9221_INT_REG, &irq_src); - if (ret) { - CPRINTS("Failed to read INT REG"); - continue; - } - - CPRINTS("INT SRC 0x%04x", irq_src); - - if (p9221r7_clear_interrupts(irq_src)) - continue; - - if (irq_src & P9221_STAT_VRECT) { - CPRINTS("VRECTON, online=%d", wpc->online); - if (!wpc->online) { - wpc->p9221_check_det = true; - hook_call_deferred(&p9221_detect_work_data, - P9221_NOTIFIER_DELAY_MS); - } - } - - p9221r7_irq_handler(irq_src); - } -} diff --git a/include/charge_manager.h b/include/charge_manager.h index 0545be594c..a7eb373089 100644 --- a/include/charge_manager.h +++ b/include/charge_manager.h @@ -50,11 +50,6 @@ enum charge_supplier { #endif /* CHARGE_MANAGER_BC12 */ #if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0 CHARGE_SUPPLIER_DEDICATED, -#endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 - CHARGE_SUPPLIER_WPC_BPP, - CHARGE_SUPPLIER_WPC_EPP, - CHARGE_SUPPLIER_WPC_GPP, #endif CHARGE_SUPPLIER_COUNT }; @@ -76,14 +71,7 @@ enum charge_supplier { #else #define CHARGE_SUPPLIER_NAME_DEDICATED #endif -#ifdef CONFIG_WIRELESS_CHARGER_P9221_R7 -#define CHARGE_SUPPLIER_NAME_QI \ - [CHARGE_SUPPLIER_WPC_BPP] = "QI_BPP", \ - [CHARGE_SUPPLIER_WPC_EPP] = "QI_EPP", \ - [CHARGE_SUPPLIER_WPC_GPP] = "QI_GPP", -#else #define CHARGE_SUPPLIER_NAME_QI -#endif #define CHARGE_SUPPLIER_NAME \ [CHARGE_SUPPLIER_PD] = "PD", [CHARGE_SUPPLIER_TYPEC] = "USBC", \ diff --git a/include/config.h b/include/config.h index 0792391d7e..059ea59891 100644 --- a/include/config.h +++ b/include/config.h @@ -1333,7 +1333,6 @@ #undef CONFIG_TRICKLE_CHARGING /* Wireless chargers */ -#undef CONFIG_WIRELESS_CHARGER_P9221_R7 #undef CONFIG_CPS8100 /*****************************************************************************/ diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 0e352e7602..0496f77aa6 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -1076,7 +1076,6 @@ CONFIG_WATCHDOG_HELP CONFIG_WATCHDOG_MAX_RETRIES CONFIG_WEBUSB_URL CONFIG_WIRELESS -CONFIG_WIRELESS_CHARGER_P9221_R7 CONFIG_WIRELESS_SUSPEND CONFIG_WLAN_POWER_ACTIVE_LOW CONFIG_WOV_FIFO_THRESH_WORDS -- cgit v1.2.1 From 9cb8e24e9ad0fb6f9daa5fbc1f4b81e3002d0afc Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 7 Jul 2022 11:49:51 -0600 Subject: cq: Remove instructions for ec-cov I removed firmware-ec-cov-cq, so no need to manually test it. BRANCH=None BUG=b:231639771 TEST=None Signed-off-by: Jeremy Bettis Change-Id: Id26f4ad36779d2132c84bada320f21c9a8f29fed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3755963 Commit-Queue: Jack Rosenthal Tested-by: Jeremy Bettis Auto-Submit: Jeremy Bettis Reviewed-by: Jack Rosenthal --- README.md | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/README.md b/README.md index 10d169888c..3d326e394c 100644 --- a/README.md +++ b/README.md @@ -677,18 +677,3 @@ cat /tmp/artifact_bundle_metadata cat /tmp/metrics_build ls -l /tmp/artifact_bundles/ ``` - -### firmware-ec-cov-cq -``` -rm -rf /tmp/artifact_bundles-cov /tmp/artifact_bundle_metadata-cov \ - ~/chromiumos/src/platform/ec/build -./firmware_builder.py --metrics /tmp/metrics_build_cov --code-coverage build && \ -./firmware_builder.py --metrics /tmp/metrics_test_cov --code-coverage test && \ -./firmware_builder.py --metrics /tmp/metrics_bundle_cov --code-coverage \ - --output-dir=/tmp/artifact_bundles-cov \ - --metadata=/tmp/artifact_bundle_metadata-cov bundle && \ -echo PASSED -cat /tmp/artifact_bundle_metadata-cov -ls -l /tmp/artifact_bundles-cov -``` - -- cgit v1.2.1 From c020eb91f162c7d77aa6ffba0f0b97412e371f30 Mon Sep 17 00:00:00 2001 From: Jameson Thies Date: Tue, 14 Jun 2022 20:18:39 +0000 Subject: TCPMV2: Add USB PD Power Button Support Introduced in USB PD 3.1, Alert messages can now carry information about power button presses and releases. This CL updates the EC to receive button press alert messages from the partner and use them to trigger startup when the device is off. BUG=b:236022894 TEST=make try_build_boards, make runhosttests and zmake test test-drivers. Also working interactively with a dock that supports sending alerts on button presses. BRANCH=None Signed-off-by: Jameson Thies Change-Id: I425babb537e1fa47962791c0debb7b622fe3c5bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3703163 Reviewed-by: Diana Z Reviewed-by: Abe Levkoy --- common/mock/usb_pd_dpm_mock.c | 4 + common/usbc/usb_pd_dpm.c | 84 +++++++++++++++++++- common/usbc/usb_pd_timer.c | 2 +- common/usbc/usb_pe_drp_sm.c | 32 ++++++++ include/config.h | 3 + include/usb_pd_dpm.h | 14 ++++ include/usb_pd_timer.h | 6 ++ test/fake_usbc.c | 4 + zephyr/Kconfig.pd | 11 +++ zephyr/shim/include/config_chip.h | 6 ++ .../drivers/src/integration/usbc/usb_pd_rev3.c | 91 ++++++++++++++++++++-- 11 files changed, 248 insertions(+), 9 deletions(-) diff --git a/common/mock/usb_pd_dpm_mock.c b/common/mock/usb_pd_dpm_mock.c index e46815ff75..4c0495f7b2 100644 --- a/common/mock/usb_pd_dpm_mock.c +++ b/common/mock/usb_pd_dpm_mock.c @@ -83,3 +83,7 @@ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len) { return EC_SUCCESS; } + +void dpm_handle_alert(int port, uint32_t ado) +{ +} diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 8bce6b9bc3..793206b623 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -9,6 +9,7 @@ */ #include "charge_state.h" +#include "chipset.h" #include "compile_time_macros.h" #include "console.h" #include "ec_commands.h" @@ -23,8 +24,9 @@ #include "usb_mux.h" #include "usb_pd.h" #include "usb_pd_dpm.h" -#include "usb_pd_tcpm.h" #include "usb_pd_pdo.h" +#include "usb_pd_tcpm.h" +#include "usb_pd_timer.h" #include "usb_pe_sm.h" #include "usb_tbt_alt_mode.h" @@ -48,6 +50,7 @@ static struct { uint32_t vdm_attention[DPM_ATTENION_MAX_VDO]; int vdm_cnt; mutex_t vdm_attention_mutex; + enum dpm_pd_button_state pd_button_state; } dpm[CONFIG_USB_PD_PORT_MAX_COUNT]; #define DPM_SET_FLAG(port, flag) atomic_or(&dpm[(port)].flags, (flag)) @@ -65,6 +68,8 @@ static struct { #define DPM_FLAG_SEND_ATTENTION BIT(5) #define DPM_FLAG_DATA_RESET_REQUESTED BIT(6) #define DPM_FLAG_DATA_RESET_DONE BIT(7) +#define DPM_FLAG_PD_BUTTON_PRESSED BIT(8) +#define DPM_FLAG_PD_BUTTON_RELEASED BIT(9) #ifdef CONFIG_ZEPHYR static int init_vdm_attention_mutex(const struct device *dev) @@ -154,6 +159,7 @@ enum ec_status pd_request_enter_mode(int port, enum typec_mode mode) void dpm_init(int port) { dpm[port].flags = 0; + dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE; } void dpm_mode_exit_complete(int port) @@ -492,6 +498,79 @@ static void dpm_send_attention_vdm(int port) DPM_CLR_FLAG(port, DPM_FLAG_SEND_ATTENTION); } +void dpm_handle_alert(int port, uint32_t ado) +{ + if (ado & ADO_EXTENDED_ALERT_EVENT) { + /* Extended Alert */ + if (pd_get_data_role(port) == PD_ROLE_DFP && + (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) == + ADO_POWER_BUTTON_PRESS) { + DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED); + } else if (pd_get_data_role(port) == PD_ROLE_DFP && + (ADO_EXTENDED_ALERT_EVENT_TYPE & ado) == + ADO_POWER_BUTTON_RELEASE) { + DPM_SET_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED); + } + } +} + +static void dpm_run_pd_button_sm(int port) +{ + /* + * Check for invalid flag combination. Alerts can only send a press or + * release event at once and only one flag should be set. If press and + * release flags are both set, we cannot know the order they were + * received. Clear the flags, disable the timer and return to an idle + * state. + */ + if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED) && + DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) { + DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED | + DPM_FLAG_PD_BUTTON_RELEASED); + pd_timer_disable(port, DPM_TIMER_PD_BUTTON_PRESS); + dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE; + return; + } + + switch (dpm[port].pd_button_state) { + case DPM_PD_BUTTON_IDLE: + if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) { + pd_timer_enable(port, DPM_TIMER_PD_BUTTON_PRESS, + CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC); + dpm[port].pd_button_state = DPM_PD_BUTTON_PRESSED; + } + break; + case DPM_PD_BUTTON_PRESSED: + if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED)) { + pd_timer_enable(port, DPM_TIMER_PD_BUTTON_PRESS, + CONFIG_USB_PD_LONG_PRESS_MAX_MS * MSEC); + } else if (DPM_CHK_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED)) { + pd_timer_disable(port, DPM_TIMER_PD_BUTTON_PRESS); + dpm[port].pd_button_state = DPM_PD_BUTTON_RELEASED; + } else if (pd_timer_is_expired(port, + DPM_TIMER_PD_BUTTON_PRESS)) { + pd_timer_disable(port, DPM_TIMER_PD_BUTTON_PRESS); + dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE; + } + break; + case DPM_PD_BUTTON_RELEASED: +#ifdef CONFIG_AP_POWER_CONTROL + if (IS_ENABLED(CONFIG_POWER_BUTTON_X86) || + IS_ENABLED(CONFIG_CHIPSET_SC7180) || + IS_ENABLED(CONFIG_CHIPSET_SC7280)) { + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + chipset_power_on(); + } +#endif + dpm[port].pd_button_state = DPM_PD_BUTTON_IDLE; + break; + } + + /* After checking flags, clear them. */ + DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_PRESSED); + DPM_CLR_FLAG(port, DPM_FLAG_PD_BUTTON_RELEASED); +} + void dpm_run(int port) { if (pd_get_data_role(port) == PD_ROLE_DFP) { @@ -500,6 +579,9 @@ void dpm_run(int port) dpm_attempt_mode_exit(port); else if (!DPM_CHK_FLAG(port, DPM_FLAG_MODE_ENTRY_DONE)) dpm_attempt_mode_entry(port); + + /* Run USB PD Power button state machine */ + dpm_run_pd_button_sm(port); } else { /* Run UFP related DPM requests */ if (DPM_CHK_FLAG(port, DPM_FLAG_SEND_ATTENTION)) diff --git a/common/usbc/usb_pd_timer.c b/common/usbc/usb_pd_timer.c index 3522bc04bc..83f1be0d29 100644 --- a/common/usbc/usb_pd_timer.c +++ b/common/usbc/usb_pd_timer.c @@ -78,7 +78,6 @@ __maybe_unused static __const_data const char *const pd_timer_names[] = { [PR_TIMER_HARD_RESET_COMPLETE] = "PR-HARD_RESET_COMPLETE", [PR_TIMER_SINK_TX] = "PR-SINK_TX", [PR_TIMER_TCPC_TX_TIMEOUT] = "PR-TCPC_TX_TIMEOUT", - [TC_TIMER_CC_DEBOUNCE] = "TC-CC_DEBOUNCE", [TC_TIMER_LOW_POWER_EXIT_TIME] = "TC-LOW_POWER_EXIT_TIME", [TC_TIMER_LOW_POWER_TIME] = "TC-LOW_POWER_TIME", @@ -87,6 +86,7 @@ __maybe_unused static __const_data const char *const pd_timer_names[] = { [TC_TIMER_TIMEOUT] = "TC-TIMEOUT", [TC_TIMER_TRY_WAIT_DEBOUNCE] = "TC-TRY_WAIT_DEBOUNCE", [TC_TIMER_VBUS_DEBOUNCE] = "TC-VBUS_DEBOUNCE", + [DPM_TIMER_PD_BUTTON_PRESS] = "DPM-PD_BUTTON_PRESS", }; /***************************************************************************** diff --git a/common/usbc/usb_pe_drp_sm.c b/common/usbc/usb_pe_drp_sm.c index 8d537a0e68..d63c5dd656 100644 --- a/common/usbc/usb_pe_drp_sm.c +++ b/common/usbc/usb_pe_drp_sm.c @@ -15,6 +15,7 @@ #include "ec_commands.h" #include "hooks.h" #include "host_command.h" +#include "power_button.h" #include "stdbool.h" #include "system.h" #include "task.h" @@ -281,6 +282,7 @@ enum usb_pe_state { PE_GIVE_BATTERY_STATUS, PE_GIVE_STATUS, PE_SEND_ALERT, + PE_ALERT_RECEIVED, PE_SRC_CHUNK_RECEIVED, PE_SNK_CHUNK_RECEIVED, PE_VCS_FORCE_VCONN, @@ -405,6 +407,7 @@ __maybe_unused static __const_data const char *const pe_state_names[] = { [PE_GIVE_BATTERY_STATUS] = "PE_Give_Battery_Status", [PE_GIVE_STATUS] = "PE_Give_Status", [PE_SEND_ALERT] = "PE_Send_Alert", + [PE_ALERT_RECEIVED] = "PE_Alert_Received", #else [PE_SRC_CHUNK_RECEIVED] = "PE_SRC_Chunk_Received", [PE_SNK_CHUNK_RECEIVED] = "PE_SNK_Chunk_Received", @@ -453,6 +456,8 @@ GEN_NOT_SUPPORTED(PE_SNK_CHUNK_RECEIVED); #define PE_SNK_CHUNK_RECEIVED PE_SNK_CHUNK_RECEIVED_NOT_SUPPORTED GEN_NOT_SUPPORTED(PE_GET_REVISION); #define PE_GET_REVISION PE_GET_REVISION_NOT_SUPPORTED +GEN_NOT_SUPPORTED(PE_ALERT_RECEIVED); +#define PE_ALERT_RECEIVED PE_ALERT_RECEIVED_NOT_SUPPORTED #endif /* CONFIG_USB_PD_REV30 */ #if !defined(CONFIG_USBC_VCONN) || !defined(CONFIG_USB_PD_REV30) @@ -2773,6 +2778,11 @@ static void pe_src_ready_run(int port) case PD_DATA_BIST: set_state_pe(port, PE_BIST_TX); return; +#ifdef CONFIG_USB_PD_REV30 + case PD_DATA_ALERT: + set_state_pe(port, PE_ALERT_RECEIVED); + return; +#endif /* CONFIG_USB_PD_REV30 */ default: set_state_pe(port, PE_SEND_NOT_SUPPORTED); return; @@ -3619,6 +3629,11 @@ static void pe_snk_ready_run(int port) case PD_DATA_BIST: set_state_pe(port, PE_BIST_TX); break; +#ifdef CONFIG_USB_PD_REV30 + case PD_DATA_ALERT: + set_state_pe(port, PE_ALERT_RECEIVED); + return; +#endif /* CONFIG_USB_PD_REV30 */ default: set_state_pe(port, PE_SEND_NOT_SUPPORTED); } @@ -4405,6 +4420,20 @@ static void pe_send_alert_run(int port) pe_set_ready_state(port); } } + +/** + * PE_SNK_Source_Alert_Received and + * PE_SRC_Sink_Alert_Received + */ +static void pe_alert_received_entry(int port) +{ + uint32_t *ado = (uint32_t *)rx_emsg[port].buf; + + print_current_state(port); + dpm_handle_alert(port, *ado); + pe_set_ready_state(port); +} + #endif /* CONFIG_USB_PD_EXTENDED_MESSAGES */ /** @@ -8161,6 +8190,9 @@ static __const_data const struct usb_state pe_states[] = { .entry = pe_send_alert_entry, .run = pe_send_alert_run, }, + [PE_ALERT_RECEIVED] = { + .entry = pe_alert_received_entry, + }, #else [PE_SRC_CHUNK_RECEIVED] = { .entry = pe_chunk_received_entry, diff --git a/include/config.h b/include/config.h index 059ea59891..d22bb985cc 100644 --- a/include/config.h +++ b/include/config.h @@ -4974,6 +4974,9 @@ /* Index for temperature sensor used in PD messages. Defaults to 0. */ #define CONFIG_USB_PD_TEMP_SENSOR 0 +/* Time limit in ms for a USB PD power button press to be considered valid. */ +#define CONFIG_USB_PD_LONG_PRESS_MAX_MS 8000 + /* * Set the minimum battery percentage to allow a PD port to send resets as a * sink (and risk a hard reset, losing Vbus). Note this may cause a high-power diff --git a/include/usb_pd_dpm.h b/include/usb_pd_dpm.h index d977bdfdca..47c8db3cb7 100644 --- a/include/usb_pd_dpm.h +++ b/include/usb_pd_dpm.h @@ -139,6 +139,14 @@ int dpm_get_source_current(const int port); */ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len); +/* + * DPM function to handle a received alert message + * + * @param port USB-C port number + * @param ado Alert Data Object (ado) received from partner + */ +void dpm_handle_alert(int port, uint32_t ado); + /* Enum for modules to describe to the DPM their setup status */ enum dpm_msg_setup_status { MSG_SETUP_SUCCESS, @@ -147,4 +155,10 @@ enum dpm_msg_setup_status { MSG_SETUP_MUX_WAIT, }; +/* Enum to describe current state of connected USB PD buttons */ +enum dpm_pd_button_state { + DPM_PD_BUTTON_IDLE, + DPM_PD_BUTTON_PRESSED, + DPM_PD_BUTTON_RELEASED, +}; #endif /* __CROS_EC_USB_DPM_H */ diff --git a/include/usb_pd_timer.h b/include/usb_pd_timer.h index b4f8946780..ebcf6c6e7c 100644 --- a/include/usb_pd_timer.h +++ b/include/usb_pd_timer.h @@ -17,6 +17,12 @@ * List of all timers that will be managed by usb_pd_timer */ enum pd_task_timer { + /* + * Timer to wait for a button release alert after receiving a button + * press alert. + */ + DPM_TIMER_PD_BUTTON_PRESS, + /* * In BIST_TX mode, this timer is used by a UUT to ensure that a * Continuous BIST Mode (i.e. BIST Carrier Mode) is exited in a timely diff --git a/test/fake_usbc.c b/test/fake_usbc.c index 1e98e78426..510370ed2e 100644 --- a/test/fake_usbc.c +++ b/test/fake_usbc.c @@ -339,6 +339,10 @@ int dpm_get_status_msg(int port, uint8_t *msg, uint32_t *len) return EC_SUCCESS; } +void dpm_handle_alert(int port, uint32_t ado) +{ +} + static enum tcpc_rp_value lcl_rp; __overridable void typec_select_src_current_limit_rp(int port, enum tcpc_rp_value rp) diff --git a/zephyr/Kconfig.pd b/zephyr/Kconfig.pd index e1ca76a298..431c676bd7 100644 --- a/zephyr/Kconfig.pd +++ b/zephyr/Kconfig.pd @@ -343,6 +343,17 @@ config PLATFORM_EC_USB_PD_TEMP_SENSOR one temperature. But, Chromebooks can have multiple temperature sensors. This option selects which temperature sensor is used for USB PD. +config PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS + int "Time limit in ms for valid presses with a USB PD power button" + default 8000 + help + USB PD supports power buttons over USB-C using button press and button + release alerts. If a USB PD partner sends a press but never a release alert, + the EC should time out while waiting for the release and return to an idle + state. This value sets how long the EC waits for a release alert from the + partner in ms. Any press longer than this will not be considered a valid USB + PD button press. + endif # PLATFORM_EC_USB_POWER_DELIVERY endif # PLATFORM_EC_USBC diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 14814897be..0dbbc5d678 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -1752,6 +1752,12 @@ extern struct jump_data mock_jump_data; #define CONFIG_USB_PD_TEMP_SENSOR CONFIG_PLATFORM_EC_USB_PD_TEMP_SENSOR #endif +#undef CONFIG_USB_PD_LONG_PRESS_MAX_MS +#ifdef CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS +#define CONFIG_USB_PD_LONG_PRESS_MAX_MS \ + CONFIG_PLATFORM_EC_USB_PD_LONG_PRESS_MAX_MS +#endif + #undef CONFIG_USBC_VCONN #ifdef CONFIG_PLATFORM_EC_USBC_VCONN #define CONFIG_USBC_VCONN diff --git a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c index 1d09daa36d..b18d443cab 100644 --- a/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c +++ b/zephyr/test/drivers/src/integration/usbc/usb_pd_rev3.c @@ -44,12 +44,6 @@ static void *usb_attach_5v_3a_pd_source_setup(void) test_fixture.src_ext.pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); - /* Clear Alert and Status receive checks */ - tcpci_src_emul_clear_alert_received(&test_fixture.src_ext); - tcpci_src_emul_clear_status_received(&test_fixture.src_ext); - zassume_false(test_fixture.src_ext.alert_received, NULL); - zassume_false(test_fixture.src_ext.status_received, NULL); - return &test_fixture; } @@ -59,6 +53,12 @@ static void usb_attach_5v_3a_pd_source_before(void *data) connect_source_to_port(&fixture->source_5v_3a, &fixture->src_ext, 1, fixture->tcpci_emul, fixture->charger_emul); + + /* Clear Alert and Status receive checks */ + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); } static void usb_attach_5v_3a_pd_source_after(void *data) @@ -169,7 +169,7 @@ ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_alert_msg) zassert_true(fixture->src_ext.alert_received, NULL); } -ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_dock_with_power_button) +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_alert_on_power_state_change) { /* Suspend and check partner received Alert and Status messages */ hook_notify(HOOK_CHIPSET_SUSPEND); @@ -207,3 +207,80 @@ ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_dock_with_power_button) zassert_true(fixture->src_ext.alert_received, NULL); zassert_true(fixture->src_ext.status_received, NULL); } + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, + verify_inaction_on_pd_button_press_while_awake) +{ + uint32_t ado; + + /* While awake expect nothing on valid press */ + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(2)); + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(2)); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); +} + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, + verify_inaction_on_invalid_pd_button_press) +{ + uint32_t ado; + + /* Shutdown device to test wake from USB PD power button */ + chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON); + k_sleep(K_SECONDS(10)); + + /* Clear alert and status flags set during shutdown */ + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); + + /* While in S5/G3 expect nothing on invalid (too long) press */ + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(10)); + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(2)); + zassert_false(fixture->src_ext.alert_received, NULL); + zassert_false(fixture->src_ext.status_received, NULL); + + /* Wake device to setup for subsequent tests */ + chipset_power_on(); + k_sleep(K_SECONDS(10)); +} + +ZTEST_F(usb_attach_5v_3a_pd_source_rev3, verify_startup_on_pd_button_press) +{ + uint32_t ado; + + /* Shutdown device to test wake from USB PD power button */ + chipset_force_shutdown(CHIPSET_SHUTDOWN_BUTTON); + k_sleep(K_SECONDS(10)); + + /* Clear alert and status flags set during shutdown */ + tcpci_src_emul_clear_alert_received(&fixture->src_ext); + tcpci_src_emul_clear_status_received(&fixture->src_ext); + zassume_false(fixture->src_ext.alert_received, NULL); + zassume_false(fixture->src_ext.status_received, NULL); + + /* While in S5/G3 expect Alert->Get_Status->Status on valid press */ + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_PRESS; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(2)); + ado = ADO_EXTENDED_ALERT_EVENT | ADO_POWER_BUTTON_RELEASE; + tcpci_partner_send_data_msg(&fixture->source_5v_3a, PD_DATA_ALERT, &ado, + 1, 0); + k_sleep(K_SECONDS(2)); + zassert_true(fixture->src_ext.alert_received, NULL); + zassert_true(fixture->src_ext.status_received, NULL); +} -- cgit v1.2.1 From 7c114b8e1a3bb29991da70b9de394ac5d4f6c909 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Barna=C5=9B?= Date: Tue, 12 Jul 2022 14:59:48 +0000 Subject: Revert "tcpc: add comma separator in tcpc shim for a better format" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit f3ee256dc0ca5b8c74b7dacad18c20e22fe180b4. Reason for revert: It caused the lazor (and probably skyrim) to fall into boot-loop BUG=b:238574488 BRANCH=main TEST=build&flash lazor, no bootloop should be visible Original change's description: > tcpc: add comma separator in tcpc shim for a better format > > Move the comma from header to the dts binding. > > Change-Id: Ic5ee1a8b83bc9690354546402cc74f097176fe36 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750550 Change-Id: Id5e21e05fd608936694607ba7c02835369592ad7 Signed-off-by: Michał Barnaś Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3758145 Commit-Queue: Diana Z Reviewed-by: Jack Rosenthal Reviewed-by: Jeremy Bettis --- zephyr/shim/include/usbc/tcpc_ccgxxf.h | 6 +++--- zephyr/shim/include/usbc/tcpc_fusb302.h | 6 +++--- zephyr/shim/include/usbc/tcpc_it8xxx2.h | 11 ++++++----- zephyr/shim/include/usbc/tcpc_nct38xx.h | 6 +++--- zephyr/shim/include/usbc/tcpc_ps8xxx.h | 8 ++++---- zephyr/shim/include/usbc/tcpci.h | 8 ++++---- zephyr/shim/src/tcpc.c | 33 ++++++++++++++++++++------------- 7 files changed, 43 insertions(+), 35 deletions(-) diff --git a/zephyr/shim/include/usbc/tcpc_ccgxxf.h b/zephyr/shim/include/usbc/tcpc_ccgxxf.h index db2dbe10fc..e19220d40e 100644 --- a/zephyr/shim/include/usbc/tcpc_ccgxxf.h +++ b/zephyr/shim/include/usbc/tcpc_ccgxxf.h @@ -8,7 +8,7 @@ #define CCGXXF_TCPC_COMPAT cypress_ccgxxf -#define TCPC_CONFIG_CCGXXF(id) \ +#define TCPC_CONFIG_CCGXXF(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ @@ -17,5 +17,5 @@ id, i2c_addr_flags), \ }, \ .drv = &ccgxxf_tcpm_drv, \ - .flags = TCPC_FLAGS_TCPCI_REV2_0, \ - } + .flags = TCPC_FLAGS_TCPCI_REV2_0, \ + }, diff --git a/zephyr/shim/include/usbc/tcpc_fusb302.h b/zephyr/shim/include/usbc/tcpc_fusb302.h index d9f80a2ac6..5333361929 100644 --- a/zephyr/shim/include/usbc/tcpc_fusb302.h +++ b/zephyr/shim/include/usbc/tcpc_fusb302.h @@ -8,7 +8,7 @@ #define FUSB302_TCPC_COMPAT fairchild_fusb302 -#define TCPC_CONFIG_FUSB302(id) \ +#define TCPC_CONFIG_FUSB302(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ @@ -16,5 +16,5 @@ .addr_flags = DT_STRING_UPPER_TOKEN( \ id, i2c_addr_flags), \ }, \ - .drv = &fusb302_tcpm_drv, \ - } + .drv = &fusb302_tcpm_drv, \ + }, diff --git a/zephyr/shim/include/usbc/tcpc_it8xxx2.h b/zephyr/shim/include/usbc/tcpc_it8xxx2.h index 9ec7d05a8a..f8f77a6d18 100644 --- a/zephyr/shim/include/usbc/tcpc_it8xxx2.h +++ b/zephyr/shim/include/usbc/tcpc_it8xxx2.h @@ -8,8 +8,9 @@ #define IT8XXX2_TCPC_COMPAT ite_it8xxx2_tcpc -#define TCPC_CONFIG_IT8XXX2(id) \ - { \ - .bus_type = EC_BUS_TYPE_EMBEDDED, .drv = &it8xxx2_tcpm_drv, \ - .flags = 0, \ - } +#define TCPC_CONFIG_IT8XXX2(id) \ + { \ + .bus_type = EC_BUS_TYPE_EMBEDDED, \ + .drv = &it8xxx2_tcpm_drv, \ + .flags = 0, \ + }, diff --git a/zephyr/shim/include/usbc/tcpc_nct38xx.h b/zephyr/shim/include/usbc/tcpc_nct38xx.h index 2dc6d32286..377e19e63d 100644 --- a/zephyr/shim/include/usbc/tcpc_nct38xx.h +++ b/zephyr/shim/include/usbc/tcpc_nct38xx.h @@ -11,7 +11,7 @@ #define NCT38XX_TCPC_COMPAT nuvoton_nct38xx -#define TCPC_CONFIG_NCT38XX(id) \ +#define TCPC_CONFIG_NCT38XX(id) \ { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ @@ -20,8 +20,8 @@ id, i2c_addr_flags), \ }, \ .drv = &nct38xx_tcpm_drv, \ - .flags = DT_PROP(id, tcpc_flags), \ - } + .flags = DT_PROP(id, tcpc_flags), \ + }, /** * @brief Get the NCT38XX GPIO device from the TCPC port enumeration diff --git a/zephyr/shim/include/usbc/tcpc_ps8xxx.h b/zephyr/shim/include/usbc/tcpc_ps8xxx.h index ca121fbde2..379b041e8e 100644 --- a/zephyr/shim/include/usbc/tcpc_ps8xxx.h +++ b/zephyr/shim/include/usbc/tcpc_ps8xxx.h @@ -8,8 +8,8 @@ #define PS8XXX_COMPAT parade_ps8xxx -#define TCPC_CONFIG_PS8XXX(id) \ - { \ +#define TCPC_CONFIG_PS8XXX(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ @@ -17,5 +17,5 @@ id, i2c_addr_flags), \ }, \ .drv = &ps8xxx_tcpm_drv, \ - .flags = DT_PROP(id, tcpc_flags), \ - } + .flags = DT_PROP(id, tcpc_flags), \ + }, diff --git a/zephyr/shim/include/usbc/tcpci.h b/zephyr/shim/include/usbc/tcpci.h index 17d535e04f..f65b6b7717 100644 --- a/zephyr/shim/include/usbc/tcpci.h +++ b/zephyr/shim/include/usbc/tcpci.h @@ -9,12 +9,12 @@ #define TCPCI_COMPAT cros_ec_tcpci -#define TCPC_CONFIG_TCPCI(id) \ - { \ +#define TCPC_CONFIG_TCPCI(id) \ + { \ .bus_type = EC_BUS_TYPE_I2C, \ .i2c_info = { \ .port = I2C_PORT(DT_PHANDLE(id, port)), \ .addr_flags = DT_PROP(id, i2c_addr_flags), \ }, \ - .drv = &tcpci_tcpm_drv, \ - } + .drv = &tcpci_tcpm_drv, \ + }, diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index a3598cafc4..aef3a05b3c 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -27,18 +27,25 @@ #define MAYBE_CONST \ COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const)) -#define MAYBE_EMPTY(compat, config) \ - COND_CODE_1( \ - DT_HAS_STATUS_OKAY(compat), \ - (DT_FOREACH_STATUS_OKAY_VARGS(compat, TCPC_CONFIG, config)), \ - (EMPTY)) - -MAYBE_CONST struct tcpc_config_t tcpc_config[] = { LIST_DROP_EMPTY( - MAYBE_EMPTY(CCGXXF_TCPC_COMPAT, TCPC_CONFIG_CCGXXF), - MAYBE_EMPTY(FUSB302_TCPC_COMPAT, TCPC_CONFIG_FUSB302), - MAYBE_EMPTY(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG_IT8XXX2), - MAYBE_EMPTY(PS8XXX_COMPAT, TCPC_CONFIG_PS8XXX), - MAYBE_EMPTY(NCT38XX_TCPC_COMPAT, TCPC_CONFIG_NCT38XX), - MAYBE_EMPTY(TCPCI_COMPAT, TCPC_CONFIG_TCPCI)) }; +MAYBE_CONST struct tcpc_config_t tcpc_config[] = { + DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_CCGXXF) + DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_FUSB302) + DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_IT8XXX2) + DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_PS8XXX) + DT_FOREACH_STATUS_OKAY_VARGS( + NCT38XX_TCPC_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_NCT38XX) + DT_FOREACH_STATUS_OKAY_VARGS( + TCPCI_COMPAT, + TCPC_CONFIG, + TCPC_CONFIG_TCPCI) +}; #endif /* DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 7540e7b47b55447475bb8191fb3520dd67cf7998 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 8 Jul 2022 10:58:19 -0600 Subject: ec: Format all python files with black and isort find . \( -path ./private -prune \) -o -name '*.py' -print | xargs black find . \( -path ./private -prune \) -o -name '*.py' -print | xargs ~/chromiumos/chromite/scripts/isort --settings-file=.isort.cfg BRANCH=None BUG=b:238434058 TEST=None Signed-off-by: Jeremy Bettis Change-Id: I63462d6f15d1eaf3db84eb20d1404ee976be8382 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749242 Commit-Queue: Jeremy Bettis Reviewed-by: Tom Hughes Tested-by: Jeremy Bettis Commit-Queue: Jack Rosenthal Auto-Submit: Jeremy Bettis Reviewed-by: Jack Rosenthal --- chip/ish/util/pack_ec.py | 155 +- chip/mchp/util/pack_ec.py | 885 +++--- chip/mchp/util/pack_ec_mec152x.py | 1132 +++---- chip/mchp/util/pack_ec_mec172x.py | 1178 ++++---- chip/mec1322/util/pack_ec.py | 479 +-- cts/common/board.py | 698 ++--- cts/cts.py | 804 ++--- extra/cr50_rma_open/cr50_rma_open.py | 418 +-- extra/stack_analyzer/stack_analyzer.py | 3562 ++++++++++++----------- extra/stack_analyzer/stack_analyzer_unittest.py | 1708 ++++++----- extra/tigertool/ecusb/__init__.py | 2 +- extra/tigertool/ecusb/pty_driver.py | 545 ++-- extra/tigertool/ecusb/stm32uart.py | 438 +-- extra/tigertool/ecusb/stm32usb.py | 207 +- extra/tigertool/ecusb/tiny_servo_common.py | 343 +-- extra/tigertool/ecusb/tiny_servod.py | 83 +- extra/tigertool/tigertest.py | 97 +- extra/tigertool/tigertool.py | 505 ++-- extra/usb_power/convert_power_log_board.py | 35 +- extra/usb_power/convert_servo_ina.py | 86 +- extra/usb_power/powerlog.py | 1762 +++++------ extra/usb_power/powerlog_unittest.py | 74 +- extra/usb_power/stats_manager.py | 745 ++--- extra/usb_power/stats_manager_unittest.py | 595 ++-- extra/usb_serial/console.py | 435 +-- extra/usb_updater/fw_update.py | 762 ++--- extra/usb_updater/servo_updater.py | 767 ++--- firmware_builder.py | 129 +- setup.py | 39 +- test/run_device_tests.py | 543 ++-- test/timer_calib.py | 78 +- test/timer_jump.py | 37 +- util/build_with_clang.py | 42 +- util/chargen | 25 +- util/config_option_check.py | 693 ++--- util/ec3po/console.py | 2231 +++++++------- util/ec3po/console_unittest.py | 2954 ++++++++++--------- util/ec3po/interpreter.py | 818 +++--- util/ec3po/interpreter_unittest.py | 728 ++--- util/ec3po/threadproc_shim.py | 31 +- util/ec_openocd.py | 24 +- util/flash_jlink.py | 144 +- util/fptool.py | 17 +- util/inject-keys.py | 149 +- util/kconfig_check.py | 230 +- util/kconfiglib.py | 1581 +++++----- util/run_ects.py | 144 +- util/test_kconfig_check.py | 181 +- util/uart_stress_tester.py | 1015 ++++--- util/unpack_ftb.py | 124 +- util/update_release_branch.py | 251 +- zephyr/firmware_builder.py | 209 +- zephyr/zmake/tests/conftest.py | 1 - zephyr/zmake/tests/test_build_config.py | 1 - zephyr/zmake/tests/test_generate_readme.py | 1 - zephyr/zmake/tests/test_modules.py | 1 - zephyr/zmake/tests/test_packers.py | 1 - zephyr/zmake/tests/test_project.py | 1 - zephyr/zmake/tests/test_reexec.py | 1 - zephyr/zmake/tests/test_toolchains.py | 1 - zephyr/zmake/tests/test_util.py | 1 - zephyr/zmake/tests/test_zmake.py | 3 +- 62 files changed, 16388 insertions(+), 14541 deletions(-) diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py index bd9b823cab..8dde6ab6a9 100755 --- a/chip/ish/util/pack_ec.py +++ b/chip/ish/util/pack_ec.py @@ -28,85 +28,100 @@ MANIFEST_ENTRY_SIZE = 0x80 HEADER_SIZE = 0x1000 PAGE_SIZE = 0x1000 + def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument("-k", "--kernel", - help="EC kernel binary to pack, \ + parser = argparse.ArgumentParser() + parser.add_argument( + "-k", + "--kernel", + help="EC kernel binary to pack, \ usually ec.RW.bin or ec.RW.flat.", - required=True) - parser.add_argument("--kernel-size", type=int, - help="Size of EC kernel image", - required=True) - parser.add_argument("-a", "--aon", - help="EC aontask binary to pack, \ + required=True, + ) + parser.add_argument( + "--kernel-size", type=int, help="Size of EC kernel image", required=True + ) + parser.add_argument( + "-a", + "--aon", + help="EC aontask binary to pack, \ usually ish_aontask.bin.", - required=False) - parser.add_argument("--aon-size", type=int, - help="Size of EC aontask image", - required=False) - parser.add_argument("-o", "--output", - help="Output flash binary file") + required=False, + ) + parser.add_argument( + "--aon-size", type=int, help="Size of EC aontask image", required=False + ) + parser.add_argument("-o", "--output", help="Output flash binary file") + + return parser.parse_args() - return parser.parse_args() def gen_manifest(ext_id, comp_app_name, code_offset, module_size): - """Returns a binary blob that represents a manifest entry""" - m = bytearray(MANIFEST_ENTRY_SIZE) + """Returns a binary blob that represents a manifest entry""" + m = bytearray(MANIFEST_ENTRY_SIZE) - # 4 bytes of ASCII encode ID (little endian) - struct.pack_into('<4s', m, 0, ext_id) - # 8 bytes of ASCII encode ID (little endian) - struct.pack_into('<8s', m, 32, comp_app_name) - # 4 bytes of code offset (little endian) - struct.pack_into(' 0) + """Returns roundup-ed page size from size of bytes""" + return int(size / PAGE_SIZE) + (size % PAGE_SIZE > 0) + def main(): - args = parseargs() - print(" Packing EC image file for ISH") - - with open(args.output, 'wb') as f: - print(" kernel binary size:", args.kernel_size) - kern_rdup_pg_size = roundup_page(args.kernel_size) - # Add manifest for main ISH binary - f.write(gen_manifest(b'ISHM', b'ISH_KERN', HEADER_SIZE, kern_rdup_pg_size)) - - if args.aon is not None: - print(" AON binary size: ", args.aon_size) - aon_rdup_pg_size = roundup_page(args.aon_size) - # Add manifest for aontask binary - f.write(gen_manifest(b'ISHM', b'AON_TASK', - (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE - - MANIFEST_ENTRY_SIZE), aon_rdup_pg_size)) - - # Add manifest that signals end of manifests - f.write(gen_manifest(b'ISHE', b'', 0, 0)) - - # Pad the remaining HEADER with 0s - if args.aon is not None: - f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3))) - else: - f.write(b'\x00' * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2))) - - # Append original kernel image - with open(args.kernel, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write(b'\x00' * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size)) - - if args.aon is not None: - # Append original aon image - with open(args.aon, 'rb') as in_file: - f.write(in_file.read()) - # Filling padings due to size round up as pages - f.write(b'\x00' * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size)) - -if __name__ == '__main__': - main() + args = parseargs() + print(" Packing EC image file for ISH") + + with open(args.output, "wb") as f: + print(" kernel binary size:", args.kernel_size) + kern_rdup_pg_size = roundup_page(args.kernel_size) + # Add manifest for main ISH binary + f.write(gen_manifest(b"ISHM", b"ISH_KERN", HEADER_SIZE, kern_rdup_pg_size)) + + if args.aon is not None: + print(" AON binary size: ", args.aon_size) + aon_rdup_pg_size = roundup_page(args.aon_size) + # Add manifest for aontask binary + f.write( + gen_manifest( + b"ISHM", + b"AON_TASK", + (HEADER_SIZE + kern_rdup_pg_size * PAGE_SIZE - MANIFEST_ENTRY_SIZE), + aon_rdup_pg_size, + ) + ) + + # Add manifest that signals end of manifests + f.write(gen_manifest(b"ISHE", b"", 0, 0)) + + # Pad the remaining HEADER with 0s + if args.aon is not None: + f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 3))) + else: + f.write(b"\x00" * (HEADER_SIZE - (MANIFEST_ENTRY_SIZE * 2))) + + # Append original kernel image + with open(args.kernel, "rb") as in_file: + f.write(in_file.read()) + # Filling padings due to size round up as pages + f.write(b"\x00" * (kern_rdup_pg_size * PAGE_SIZE - args.kernel_size)) + + if args.aon is not None: + # Append original aon image + with open(args.aon, "rb") as in_file: + f.write(in_file.read()) + # Filling padings due to size round up as pages + f.write(b"\x00" * (aon_rdup_pg_size * PAGE_SIZE - args.aon_size)) + + +if __name__ == "__main__": + main() diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py index 7908b0bf37..15be16c0d4 100755 --- a/chip/mchp/util/pack_ec.py +++ b/chip/mchp/util/pack_ec.py @@ -16,7 +16,7 @@ import os import struct import subprocess import tempfile -import zlib # CRC32 +import zlib # CRC32 # MEC1701 has 256KB SRAM from 0xE0000 - 0x120000 # SRAM is divided into contiguous CODE & DATA @@ -30,165 +30,199 @@ LOAD_ADDR = 0x0E0000 LOAD_ADDR_RW = 0xE1000 HEADER_SIZE = 0x40 SPI_CLOCK_LIST = [48, 24, 16, 12] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] +SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B] + +CRC_TABLE = [ + 0x00, + 0x07, + 0x0E, + 0x09, + 0x1C, + 0x1B, + 0x12, + 0x15, + 0x38, + 0x3F, + 0x36, + 0x31, + 0x24, + 0x23, + 0x2A, + 0x2D, +] -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] def mock_print(*args, **kwargs): - pass + pass + debug_print = mock_print + def Crc8(crc, data): - """Update CRC8 value.""" - for v in data: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 + """Update CRC8 value.""" + for v in data: + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]) + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)]) + return crc ^ 0x55 + def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return struct.unpack('> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - # bytes 0x14 - 0x17 - header.extend(struct.pack('> 6) & 0xFF) + header.append((payload_len >> 14) & 0xFF) + PadZeroTo(header, 0x14) + # bytes 0x14 - 0x17 + header.extend(struct.pack("> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - # bytes 0x14 - 0x17 - header.extend(struct.pack('> 6) & 0xFF) + header.append((payload_len >> 14) & 0xFF) + PadZeroTo(header, 0x14) + # bytes 0x14 - 0x17 + header.extend(struct.pack("> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - tag.append(Crc8(0, tag)) - return tag + tag = bytearray( + [ + (args.header_loc >> 8) & 0xFF, + (args.header_loc >> 16) & 0xFF, + (args.header_loc >> 24) & 0xFF, + ] + ) + tag.append(Crc8(0, tag)) + return tag + def BuildTagFromHdrAddr(header_loc): - tag = bytearray([(header_loc >> 8) & 0xff, - (header_loc >> 16) & 0xff, - (header_loc >> 24) & 0xff]) + tag = bytearray( + [(header_loc >> 8) & 0xFF, (header_loc >> 16) & 0xFF, (header_loc >> 24) & 0xFF] + ) tag.append(Crc8(0, tag)) return tag @@ -224,20 +263,21 @@ def BuildTagFromHdrAddr(header_loc): # Returns temporary file name # def PacklfwRoImage(rorw_file, loader_file, image_size): - """Create a temp file with the - first image_size bytes from the loader file and append bytes - from the rorw file. - return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: # read 4KB loader file - pro = fin1.read() - fo.write(pro) # write 4KB loader data to temp file - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - - fo.write(ro) - fo.close() - return fo.name + """Create a temp file with the + first image_size bytes from the loader file and append bytes + from the rorw file. + return the filename""" + fo = tempfile.NamedTemporaryFile(delete=False) # Need to keep file around + with open(loader_file, "rb") as fin1: # read 4KB loader file + pro = fin1.read() + fo.write(pro) # write 4KB loader data to temp file + with open(rorw_file, "rb") as fin: + ro = fin.read(image_size) + + fo.write(ro) + fo.close() + return fo.name + # # Generate a test EC_RW image of same size @@ -248,105 +288,145 @@ def PacklfwRoImage(rorw_file, loader_file, image_size): # process hash generation. # def gen_test_ecrw(pldrw): - debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) - debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) - cookie1_pos = pldrw.find(b'\x99\x88\x77\xce') - cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4) - t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: - for i in range(0, cookie1_pos): - pldrw[i] = 0xA5 - for i in range(cookie2_pos+4, len(pldrw)): - pldrw[i] = 0xA5 - - with open("ec_RW_test.bin", "wb") as fecrw: - fecrw.write(pldrw[:size]) + debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) + debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) + cookie1_pos = pldrw.find(b"\x99\x88\x77\xce") + cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4) + t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: + for i in range(0, cookie1_pos): + pldrw[i] = 0xA5 + for i in range(cookie2_pos + 4, len(pldrw)): + pldrw[i] = 0xA5 + + with open("ec_RW_test.bin", "wb") as fecrw: + fecrw.write(pldrw[:size]) + def parseargs(): - rpath = os.path.dirname(os.path.relpath(__file__)) - - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in KB", - default=512) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash", - default=0x1000) - parser.add_argument("-p", "--payload_offset", type=int, - help="The offset of payload from the start of header", - default=0x80) - parser.add_argument("-r", "--rw_loc", type=int, - help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", - default=-1) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image. Default 220KB", - default=(220 * 1024)) - parser.add_argument("--test_spi", action='store_true', - help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", - default=False) - parser.add_argument("--test_ecrw", action='store_true', - help="Use fixed pattern for EC_RW but preserve image_data", - default=False) - parser.add_argument("--verbose", action='store_true', - help="Enable verbose output", - default=False) - - return parser.parse_args() + rpath = os.path.dirname(os.path.relpath(__file__)) + + parser = argparse.ArgumentParser() + parser.add_argument( + "-i", + "--input", + help="EC binary to pack, usually ec.bin or ec.RO.flat.", + metavar="EC_BIN", + default="ec.bin", + ) + parser.add_argument( + "-o", + "--output", + help="Output flash binary file", + metavar="EC_SPI_FLASH", + default="ec.packed.bin", + ) + parser.add_argument( + "--loader_file", help="EC loader binary", default="ecloader.bin" + ) + parser.add_argument( + "-s", "--spi_size", type=int, help="Size of the SPI flash in KB", default=512 + ) + parser.add_argument( + "-l", + "--header_loc", + type=int, + help="Location of header in SPI flash", + default=0x1000, + ) + parser.add_argument( + "-p", + "--payload_offset", + type=int, + help="The offset of payload from the start of header", + default=0x80, + ) + parser.add_argument( + "-r", + "--rw_loc", + type=int, + help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", + default=-1, + ) + parser.add_argument( + "--spi_clock", + type=int, + help="SPI clock speed. 8, 12, 24, or 48 MHz.", + default=24, + ) + parser.add_argument( + "--spi_read_cmd", + type=int, + help="SPI read command. 0x3, 0xB, or 0x3B.", + default=0xB, + ) + parser.add_argument( + "--image_size", + type=int, + help="Size of a single image. Default 220KB", + default=(220 * 1024), + ) + parser.add_argument( + "--test_spi", + action="store_true", + help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", + default=False, + ) + parser.add_argument( + "--test_ecrw", + action="store_true", + help="Use fixed pattern for EC_RW but preserve image_data", + default=False, + ) + parser.add_argument( + "--verbose", action="store_true", help="Enable verbose output", default=False + ) + + return parser.parse_args() + # Debug helper routine def dumpsects(spi_list): - debug_print("spi_list has {0} entries".format(len(spi_list))) - for s in spi_list: - debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2])) + debug_print("spi_list has {0} entries".format(len(spi_list))) + for s in spi_list: + debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2])) + def printByteArrayAsHex(ba, title): - debug_print(title,"= ") - count = 0 - for b in ba: - count = count + 1 - debug_print("0x{0:02x}, ".format(b),end="") - if (count % 8) == 0: - debug_print("") - debug_print("\n") + debug_print(title, "= ") + count = 0 + for b in ba: + count = count + 1 + debug_print("0x{0:02x}, ".format(b), end="") + if (count % 8) == 0: + debug_print("") + debug_print("\n") + def print_args(args): - debug_print("parsed arguments:") - debug_print(".input = ", args.input) - debug_print(".output = ", args.output) - debug_print(".loader_file = ", args.loader_file) - debug_print(".spi_size (KB) = ", hex(args.spi_size)) - debug_print(".image_size = ", hex(args.image_size)) - debug_print(".header_loc = ", hex(args.header_loc)) - debug_print(".payload_offset = ", hex(args.payload_offset)) - if args.rw_loc < 0: - debug_print(".rw_loc = ", args.rw_loc) - else: - debug_print(".rw_loc = ", hex(args.rw_loc)) - debug_print(".spi_clock = ", args.spi_clock) - debug_print(".spi_read_cmd = ", args.spi_read_cmd) - debug_print(".test_spi = ", args.test_spi) - debug_print(".verbose = ", args.verbose) + debug_print("parsed arguments:") + debug_print(".input = ", args.input) + debug_print(".output = ", args.output) + debug_print(".loader_file = ", args.loader_file) + debug_print(".spi_size (KB) = ", hex(args.spi_size)) + debug_print(".image_size = ", hex(args.image_size)) + debug_print(".header_loc = ", hex(args.header_loc)) + debug_print(".payload_offset = ", hex(args.payload_offset)) + if args.rw_loc < 0: + debug_print(".rw_loc = ", args.rw_loc) + else: + debug_print(".rw_loc = ", hex(args.rw_loc)) + debug_print(".spi_clock = ", args.spi_clock) + debug_print(".spi_read_cmd = ", args.spi_read_cmd) + debug_print(".test_spi = ", args.test_spi) + debug_print(".verbose = ", args.verbose) + # # Handle quiet mode build from Makefile @@ -354,183 +434,188 @@ def print_args(args): # Verbose mode when V=1 # def main(): - global debug_print - - args = parseargs() - - if args.verbose: - debug_print = print - - debug_print("Begin MEC17xx pack_ec.py script") - - - # MEC17xx maximum 192KB each for RO & RW - # mec1701 chip Makefile sets args.spi_size = 512 - # Tags at offset 0 - # - print_args(args) - - spi_size = args.spi_size * 1024 - debug_print("SPI Flash image size in bytes =", hex(spi_size)) - - # !!! IMPORTANT !!! - # These values MUST match chip/mec1701/config_flash_layout.h - # defines. - # MEC17xx Boot-ROM TAGs are at offset 0 and 4. - # lfw + EC_RO starts at beginning of second 4KB sector - # EC_RW starts at offset 0x40000 (256KB) - - spi_list = [] - - debug_print("args.input = ",args.input) - debug_print("args.loader_file = ",args.loader_file) - debug_print("args.image_size = ",hex(args.image_size)) - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - - payload = GetPayload(rorofile) - payload_len = len(payload) - # debug - debug_print("EC_LFW + EC_RO length = ",hex(payload_len)) - - # SPI image integrity test - # compute CRC32 of EC_RO except for last 4 bytes - # skip over 4KB LFW - # Store CRC32 in last 4 bytes - if args.test_spi == True: - crc = zlib.crc32(bytes(payload[LFW_SIZE:(payload_len - 4)])) - crc_ofs = payload_len - 4 - debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs)) - for i in range(4): - payload[crc_ofs + i] = crc & 0xff - crc = crc >> 8 - - # Chromebooks are not using MEC BootROM ECDSA. - # We implemented the ECDSA disabled case where - # the 64-byte signature contains a SHA-256 of the binary plus - # 32 zeros bytes. - payload_signature = SignByteArray(payload) - # debug - printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature") - - # MEC17xx Header is 0x80 bytes with an 64 byte signature - # (32 byte SHA256 + 32 zero bytes) - header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile) - # debug - printByteArrayAsHex(header, "Header LFW + EC_RO") - - # MEC17xx payload ECDSA not used, 64 byte signature is - # SHA256 + 32 zero bytes - header_signature = SignByteArray(header) - # debug - printByteArrayAsHex(header_signature, "header_signature") - - tag = BuildTag(args) - # MEC17xx truncate RW length to args.image_size to not overwrite LFW - # offset may be different due to Header size and other changes - # MCHP we want to append a SHA-256 to the end of the actual payload - # to test SPI read routines. - debug_print("Call to GetPayloadFromOffset") - debug_print("args.input = ", args.input) - debug_print("args.image_size = ", hex(args.image_size)) - - payload_rw = GetPayloadFromOffset(args.input, args.image_size) - debug_print("type(payload_rw) is ", type(payload_rw)) - debug_print("len(payload_rw) is ", hex(len(payload_rw))) - - # truncate to args.image_size - rw_len = args.image_size - payload_rw = payload_rw[:rw_len] - payload_rw_len = len(payload_rw) - debug_print("Truncated size of EC_RW = ", hex(payload_rw_len)) - - payload_entry_tuple = struct.unpack_from('> 8 - - payload_rw_sig = SignByteArray(payload_rw) - # debug - printByteArrayAsHex(payload_rw_sig, "payload_rw_sig") - - os.remove(rorofile) # clean up the temp file - - # MEC170x Boot-ROM Tags are located at SPI offset 0 - spi_list.append((0, tag, "tag")) - - spi_list.append((args.header_loc, header, "header(lwf + ro)")) - spi_list.append((args.header_loc + HEADER_SIZE, header_signature, - "header(lwf + ro) signature")) - spi_list.append((args.header_loc + args.payload_offset, payload, - "payload(lfw + ro)")) - - offset = args.header_loc + args.payload_offset + payload_len - - # No SPI Header for EC_RW as its not loaded by BootROM - spi_list.append((offset, payload_signature, - "payload(lfw_ro) signature")) - - # EC_RW location - rw_offset = int(spi_size // 2) - if args.rw_loc >= 0: - rw_offset = args.rw_loc - - debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) - - if rw_offset < offset + len(payload_signature): - print("ERROR: EC_RW overlaps EC_RO") - - spi_list.append((rw_offset, payload_rw, "payload(rw)")) - - # don't add to EC_RW. We don't know if Google will process - # EC SPI flash binary with other tools during build of - # coreboot and OS. - #offset = rw_offset + payload_rw_len - #spi_list.append((offset, payload_rw_sig, "payload(rw) signature")) - - spi_list = sorted(spi_list) - - dumpsects(spi_list) - - # - # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI. - # - with open(args.output, 'wb') as f: - debug_print("Write spi list to file", args.output) - addr = 0 - for s in spi_list: - if addr < s[0]: - debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr), - "fill with 0xff") - f.write(b'\xff' * (s[0] - addr)) - addr = s[0] - debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data") - - f.write(s[1]) - addr += len(s[1]) - - if addr < spi_size: - debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr), - "fill with 0xff") - f.write(b'\xff' * (spi_size - addr)) - - f.flush() - -if __name__ == '__main__': - main() + global debug_print + + args = parseargs() + + if args.verbose: + debug_print = print + + debug_print("Begin MEC17xx pack_ec.py script") + + # MEC17xx maximum 192KB each for RO & RW + # mec1701 chip Makefile sets args.spi_size = 512 + # Tags at offset 0 + # + print_args(args) + + spi_size = args.spi_size * 1024 + debug_print("SPI Flash image size in bytes =", hex(spi_size)) + + # !!! IMPORTANT !!! + # These values MUST match chip/mec1701/config_flash_layout.h + # defines. + # MEC17xx Boot-ROM TAGs are at offset 0 and 4. + # lfw + EC_RO starts at beginning of second 4KB sector + # EC_RW starts at offset 0x40000 (256KB) + + spi_list = [] + + debug_print("args.input = ", args.input) + debug_print("args.loader_file = ", args.loader_file) + debug_print("args.image_size = ", hex(args.image_size)) + + rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) + + payload = GetPayload(rorofile) + payload_len = len(payload) + # debug + debug_print("EC_LFW + EC_RO length = ", hex(payload_len)) + + # SPI image integrity test + # compute CRC32 of EC_RO except for last 4 bytes + # skip over 4KB LFW + # Store CRC32 in last 4 bytes + if args.test_spi == True: + crc = zlib.crc32(bytes(payload[LFW_SIZE : (payload_len - 4)])) + crc_ofs = payload_len - 4 + debug_print("EC_RO CRC32 = 0x{0:08x} @ 0x{1:08x}".format(crc, crc_ofs)) + for i in range(4): + payload[crc_ofs + i] = crc & 0xFF + crc = crc >> 8 + + # Chromebooks are not using MEC BootROM ECDSA. + # We implemented the ECDSA disabled case where + # the 64-byte signature contains a SHA-256 of the binary plus + # 32 zeros bytes. + payload_signature = SignByteArray(payload) + # debug + printByteArrayAsHex(payload_signature, "LFW + EC_RO payload_signature") + + # MEC17xx Header is 0x80 bytes with an 64 byte signature + # (32 byte SHA256 + 32 zero bytes) + header = BuildHeader(args, payload_len, LOAD_ADDR, rorofile) + # debug + printByteArrayAsHex(header, "Header LFW + EC_RO") + + # MEC17xx payload ECDSA not used, 64 byte signature is + # SHA256 + 32 zero bytes + header_signature = SignByteArray(header) + # debug + printByteArrayAsHex(header_signature, "header_signature") + + tag = BuildTag(args) + # MEC17xx truncate RW length to args.image_size to not overwrite LFW + # offset may be different due to Header size and other changes + # MCHP we want to append a SHA-256 to the end of the actual payload + # to test SPI read routines. + debug_print("Call to GetPayloadFromOffset") + debug_print("args.input = ", args.input) + debug_print("args.image_size = ", hex(args.image_size)) + + payload_rw = GetPayloadFromOffset(args.input, args.image_size) + debug_print("type(payload_rw) is ", type(payload_rw)) + debug_print("len(payload_rw) is ", hex(len(payload_rw))) + + # truncate to args.image_size + rw_len = args.image_size + payload_rw = payload_rw[:rw_len] + payload_rw_len = len(payload_rw) + debug_print("Truncated size of EC_RW = ", hex(payload_rw_len)) + + payload_entry_tuple = struct.unpack_from("> 8 + + payload_rw_sig = SignByteArray(payload_rw) + # debug + printByteArrayAsHex(payload_rw_sig, "payload_rw_sig") + + os.remove(rorofile) # clean up the temp file + + # MEC170x Boot-ROM Tags are located at SPI offset 0 + spi_list.append((0, tag, "tag")) + + spi_list.append((args.header_loc, header, "header(lwf + ro)")) + spi_list.append( + (args.header_loc + HEADER_SIZE, header_signature, "header(lwf + ro) signature") + ) + spi_list.append( + (args.header_loc + args.payload_offset, payload, "payload(lfw + ro)") + ) + + offset = args.header_loc + args.payload_offset + payload_len + + # No SPI Header for EC_RW as its not loaded by BootROM + spi_list.append((offset, payload_signature, "payload(lfw_ro) signature")) + + # EC_RW location + rw_offset = int(spi_size // 2) + if args.rw_loc >= 0: + rw_offset = args.rw_loc + + debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) + + if rw_offset < offset + len(payload_signature): + print("ERROR: EC_RW overlaps EC_RO") + + spi_list.append((rw_offset, payload_rw, "payload(rw)")) + + # don't add to EC_RW. We don't know if Google will process + # EC SPI flash binary with other tools during build of + # coreboot and OS. + # offset = rw_offset + payload_rw_len + # spi_list.append((offset, payload_rw_sig, "payload(rw) signature")) + + spi_list = sorted(spi_list) + + dumpsects(spi_list) + + # + # MEC17xx Boot-ROM locates TAG at SPI offset 0 instead of end of SPI. + # + with open(args.output, "wb") as f: + debug_print("Write spi list to file", args.output) + addr = 0 + for s in spi_list: + if addr < s[0]: + debug_print( + "Offset ", hex(addr), " Length", hex(s[0] - addr), "fill with 0xff" + ) + f.write(b"\xff" * (s[0] - addr)) + addr = s[0] + debug_print( + "Offset ", hex(addr), " Length", hex(len(s[1])), "write data" + ) + + f.write(s[1]) + addr += len(s[1]) + + if addr < spi_size: + debug_print( + "Offset ", hex(addr), " Length", hex(spi_size - addr), "fill with 0xff" + ) + f.write(b"\xff" * (spi_size - addr)) + + f.flush() + + +if __name__ == "__main__": + main() diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py index 34846cd6ba..89f90f5394 100755 --- a/chip/mchp/util/pack_ec_mec152x.py +++ b/chip/mchp/util/pack_ec_mec152x.py @@ -16,7 +16,7 @@ import os import struct import subprocess import tempfile -import zlib # CRC32 +import zlib # CRC32 # MEC152xH has 256KB SRAM from 0xE0000 - 0x120000 # SRAM is divided into contiguous CODE & DATA @@ -29,119 +29,157 @@ LOAD_ADDR = 0x0E0000 LOAD_ADDR_RW = 0xE1000 MEC152X_HEADER_SIZE = 0x140 MEC152X_HEADER_VERSION = 0x02 -PAYLOAD_PAD_BYTE = b'\xff' +PAYLOAD_PAD_BYTE = b"\xff" SPI_ERASE_BLOCK_SIZE = 0x1000 SPI_CLOCK_LIST = [48, 24, 16, 12] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] -SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3} +SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B] +SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3} CHIP_MAX_CODE_SRAM_KB = 224 MEC152X_DICT = { - "HEADER_SIZE":0x140, - "HEADER_VER":0x02, - "PAYLOAD_OFFSET":0x140, - "PAYLOAD_GRANULARITY":128, - "EC_INFO_BLK_SZ":128, - "ENCR_KEY_HDR_SZ":128, - "COSIG_SZ":96, - "TRAILER_SZ":160, - "TAILER_PAD_BYTE":b'\xff', - "PAD_SIZE":128 - } - -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] + "HEADER_SIZE": 0x140, + "HEADER_VER": 0x02, + "PAYLOAD_OFFSET": 0x140, + "PAYLOAD_GRANULARITY": 128, + "EC_INFO_BLK_SZ": 128, + "ENCR_KEY_HDR_SZ": 128, + "COSIG_SZ": 96, + "TRAILER_SZ": 160, + "TAILER_PAD_BYTE": b"\xff", + "PAD_SIZE": 128, +} + +CRC_TABLE = [ + 0x00, + 0x07, + 0x0E, + 0x09, + 0x1C, + 0x1B, + 0x12, + 0x15, + 0x38, + 0x3F, + 0x36, + 0x31, + 0x24, + 0x23, + 0x2A, + 0x2D, +] + def mock_print(*args, **kwargs): - pass + pass + debug_print = mock_print # Debug helper routine def dumpsects(spi_list): - debug_print("spi_list has {0} entries".format(len(spi_list))) - for s in spi_list: - debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2])) + debug_print("spi_list has {0} entries".format(len(spi_list))) + for s in spi_list: + debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2])) + def printByteArrayAsHex(ba, title): - debug_print(title,"= ") - if ba == None: - debug_print("None") - return - - count = 0 - for b in ba: - count = count + 1 - debug_print("0x{0:02x}, ".format(b),end="") - if (count % 8) == 0: - debug_print("") - debug_print("") + debug_print(title, "= ") + if ba == None: + debug_print("None") + return + + count = 0 + for b in ba: + count = count + 1 + debug_print("0x{0:02x}, ".format(b), end="") + if (count % 8) == 0: + debug_print("") + debug_print("") + def Crc8(crc, data): - """Update CRC8 value.""" - for v in data: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 + """Update CRC8 value.""" + for v in data: + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]) + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)]) + return crc ^ 0x55 + def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return int.from_bytes(s, byteorder='little') + """Read entry point from payload EC image.""" + with open(payload_file, "rb") as f: + f.seek(4) + s = f.read(4) + return int.from_bytes(s, byteorder="little") + def GetPayloadFromOffset(payload_file, offset, padsize): - """Read payload and pad it to padsize.""" - with open(payload_file, 'rb') as f: - f.seek(offset) - payload = bytearray(f.read()) - rem_len = len(payload) % padsize - debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len)) + """Read payload and pad it to padsize.""" + with open(payload_file, "rb") as f: + f.seek(offset) + payload = bytearray(f.read()) + rem_len = len(payload) % padsize + debug_print( + "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format( + padsize, len(payload), rem_len + ) + ) + + if rem_len: + payload += PAYLOAD_PAD_BYTE * (padsize - rem_len) + debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len)) - if rem_len: - payload += PAYLOAD_PAD_BYTE * (padsize - rem_len) - debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len)) + return payload - return payload def GetPayload(payload_file, padsize): - """Read payload and pad it to padsize""" - return GetPayloadFromOffset(payload_file, 0, padsize) + """Read payload and pad it to padsize""" + return GetPayloadFromOffset(payload_file, 0, padsize) + def GetPublicKey(pem_file): - """Extract public exponent and modulus from PEM file.""" - result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text', - '-noout'], stdout=subprocess.PIPE, encoding='utf-8') - modulus_raw = [] - in_modulus = False - for line in result.stdout.splitlines(): - if line.startswith('modulus'): - in_modulus = True - elif not line.startswith(' '): - in_modulus = False - elif in_modulus: - modulus_raw.extend(line.strip().strip(':').split(':')) - if line.startswith('publicExponent'): - exp = int(line.split(' ')[1], 10) - modulus_raw.reverse() - modulus = bytearray((int(x, 16) for x in modulus_raw[:256])) - return struct.pack('> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - tag.append(Crc8(0, tag)) - return tag + tag = bytearray( + [ + (args.header_loc >> 8) & 0xFF, + (args.header_loc >> 16) & 0xFF, + (args.header_loc >> 24) & 0xFF, + ] + ) + tag.append(Crc8(0, tag)) + return tag + def BuildTagFromHdrAddr(header_loc): - tag = bytearray([(header_loc >> 8) & 0xff, - (header_loc >> 16) & 0xff, - (header_loc >> 24) & 0xff]) + tag = bytearray( + [(header_loc >> 8) & 0xFF, (header_loc >> 16) & 0xFF, (header_loc >> 24) & 0xFF] + ) tag.append(Crc8(0, tag)) return tag @@ -388,12 +443,13 @@ def BuildTagFromHdrAddr(header_loc): # Output: # bytearray of length 4 def BuildFlashMap(secondSpiFlashBaseAddr): - flashmap = bytearray(4) - flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff - flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff - flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff - flashmap[3] = Crc8(0, flashmap) - return flashmap + flashmap = bytearray(4) + flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF + flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF + flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF + flashmap[3] = Crc8(0, flashmap) + return flashmap + # # Creates temporary file for read/write @@ -404,21 +460,22 @@ def BuildFlashMap(secondSpiFlashBaseAddr): # Returns temporary file name # def PacklfwRoImage(rorw_file, loader_file, image_size): - """Create a temp file with the - first image_size bytes from the loader file and append bytes - from the rorw file. - return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: # read 4KB loader file - pro = fin1.read() - fo.write(pro) # write 4KB loader data to temp file - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - - fo.write(ro) - fo.close() - - return fo.name + """Create a temp file with the + first image_size bytes from the loader file and append bytes + from the rorw file. + return the filename""" + fo = tempfile.NamedTemporaryFile(delete=False) # Need to keep file around + with open(loader_file, "rb") as fin1: # read 4KB loader file + pro = fin1.read() + fo.write(pro) # write 4KB loader data to temp file + with open(rorw_file, "rb") as fin: + ro = fin.read(image_size) + + fo.write(ro) + fo.close() + + return fo.name + # # Generate a test EC_RW image of same size @@ -429,129 +486,184 @@ def PacklfwRoImage(rorw_file, loader_file, image_size): # process hash generation. # def gen_test_ecrw(pldrw): - debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) - debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) - cookie1_pos = pldrw.find(b'\x99\x88\x77\xce') - cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4) - t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: - for i in range(0, cookie1_pos): - pldrw[i] = 0xA5 - for i in range(cookie2_pos+4, len(pldrw)): - pldrw[i] = 0xA5 - - with open("ec_RW_test.bin", "wb") as fecrw: - fecrw.write(pldrw[:size]) + debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) + debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) + cookie1_pos = pldrw.find(b"\x99\x88\x77\xce") + cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4) + t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: + for i in range(0, cookie1_pos): + pldrw[i] = 0xA5 + for i in range(cookie2_pos + 4, len(pldrw)): + pldrw[i] = 0xA5 + + with open("ec_RW_test.bin", "wb") as fecrw: + fecrw.write(pldrw[:size]) + def parseargs(): - #TODO I commented this out. Why? - rpath = os.path.dirname(os.path.relpath(__file__)) - - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in KB", - default=512) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash", - default=0x1000) - parser.add_argument("-r", "--rw_loc", type=int, - help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", - default=-1) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image. Default 220KB", - default=(220 * 1024)) - parser.add_argument("--test_spi", action='store_true', - help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", - default=False) - parser.add_argument("--test_ecrw", action='store_true', - help="Use fixed pattern for EC_RW but preserve image_data", - default=False) - parser.add_argument("--verbose", action='store_true', - help="Enable verbose output", - default=False) - parser.add_argument("--tag0_loc", type=int, - help="MEC152X TAG0 SPI offset", - default=0) - parser.add_argument("--tag1_loc", type=int, - help="MEC152X TAG1 SPI offset", - default=4) - parser.add_argument("--spi_drive_str", type=int, - help="Chip SPI drive strength in mA: 2, 4, 8, or 12", - default=4) - parser.add_argument("--spi_slew_fast", action='store_true', - help="SPI use fast slew rate. Default is False", - default=False) - parser.add_argument("--spi_cpol", type=int, - help="SPI clock polarity when idle. Defealt is 0(low)", - default=0) - parser.add_argument("--spi_cpha_mosi", type=int, - help="""SPI clock phase master drives data. + # TODO I commented this out. Why? + rpath = os.path.dirname(os.path.relpath(__file__)) + + parser = argparse.ArgumentParser() + parser.add_argument( + "-i", + "--input", + help="EC binary to pack, usually ec.bin or ec.RO.flat.", + metavar="EC_BIN", + default="ec.bin", + ) + parser.add_argument( + "-o", + "--output", + help="Output flash binary file", + metavar="EC_SPI_FLASH", + default="ec.packed.bin", + ) + parser.add_argument( + "--loader_file", help="EC loader binary", default="ecloader.bin" + ) + parser.add_argument( + "-s", "--spi_size", type=int, help="Size of the SPI flash in KB", default=512 + ) + parser.add_argument( + "-l", + "--header_loc", + type=int, + help="Location of header in SPI flash", + default=0x1000, + ) + parser.add_argument( + "-r", + "--rw_loc", + type=int, + help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", + default=-1, + ) + parser.add_argument( + "--spi_clock", + type=int, + help="SPI clock speed. 8, 12, 24, or 48 MHz.", + default=24, + ) + parser.add_argument( + "--spi_read_cmd", + type=int, + help="SPI read command. 0x3, 0xB, or 0x3B.", + default=0xB, + ) + parser.add_argument( + "--image_size", + type=int, + help="Size of a single image. Default 220KB", + default=(220 * 1024), + ) + parser.add_argument( + "--test_spi", + action="store_true", + help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", + default=False, + ) + parser.add_argument( + "--test_ecrw", + action="store_true", + help="Use fixed pattern for EC_RW but preserve image_data", + default=False, + ) + parser.add_argument( + "--verbose", action="store_true", help="Enable verbose output", default=False + ) + parser.add_argument( + "--tag0_loc", type=int, help="MEC152X TAG0 SPI offset", default=0 + ) + parser.add_argument( + "--tag1_loc", type=int, help="MEC152X TAG1 SPI offset", default=4 + ) + parser.add_argument( + "--spi_drive_str", + type=int, + help="Chip SPI drive strength in mA: 2, 4, 8, or 12", + default=4, + ) + parser.add_argument( + "--spi_slew_fast", + action="store_true", + help="SPI use fast slew rate. Default is False", + default=False, + ) + parser.add_argument( + "--spi_cpol", + type=int, + help="SPI clock polarity when idle. Defealt is 0(low)", + default=0, + ) + parser.add_argument( + "--spi_cpha_mosi", + type=int, + help="""SPI clock phase master drives data. 0=Data driven on active to inactive clock edge, 1=Data driven on inactive to active clock edge""", - default=0) - parser.add_argument("--spi_cpha_miso", type=int, - help="""SPI clock phase master samples data. + default=0, + ) + parser.add_argument( + "--spi_cpha_miso", + type=int, + help="""SPI clock phase master samples data. 0=Data sampled on inactive to active clock edge, 1=Data sampled on active to inactive clock edge""", - default=0) + default=0, + ) + + parser.add_argument( + "--vtr2_V18", + action="store_true", + help="Chip VTR2 rail is 1.8V. Default is False(3.3V)", + default=False, + ) - parser.add_argument("--vtr2_V18", action='store_true', - help="Chip VTR2 rail is 1.8V. Default is False(3.3V)", - default=False) + parser.add_argument( + "--vtr3_V18", + action="store_true", + help="Chip VTR3 rail is 1.8V. Default is False(3.3V)", + default=False, + ) - parser.add_argument("--vtr3_V18", action='store_true', - help="Chip VTR3 rail is 1.8V. Default is False(3.3V)", - default=False) + return parser.parse_args() - return parser.parse_args() def print_args(args): - debug_print("parsed arguments:") - debug_print(".input = ", args.input) - debug_print(".output = ", args.output) - debug_print(".loader_file = ", args.loader_file) - debug_print(".spi_size (KB) = ", hex(args.spi_size)) - debug_print(".image_size = ", hex(args.image_size)) - debug_print(".tag0_loc = ", hex(args.tag0_loc)) - debug_print(".tag1_loc = ", hex(args.tag1_loc)) - debug_print(".header_loc = ", hex(args.header_loc)) - if args.rw_loc < 0: - debug_print(".rw_loc = ", args.rw_loc) - else: - debug_print(".rw_loc = ", hex(args.rw_loc)) - debug_print(".spi_clock (MHz) = ", args.spi_clock) - debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd)) - debug_print(".test_spi = ", args.test_spi) - debug_print(".test_ecrw = ", args.test_ecrw) - debug_print(".verbose = ", args.verbose) - debug_print(".spi_drive_str = ", args.spi_drive_str) - debug_print(".spi_slew_fast = ", args.spi_slew_fast) - debug_print(".spi_cpol = ", args.spi_cpol) - debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi) - debug_print(".spi_cpha_miso = ", args.spi_cpha_miso) - debug_print(".vtr2_V18 = ", args.vtr2_V18) - debug_print(".vtr3_V18 = ", args.vtr3_V18) + debug_print("parsed arguments:") + debug_print(".input = ", args.input) + debug_print(".output = ", args.output) + debug_print(".loader_file = ", args.loader_file) + debug_print(".spi_size (KB) = ", hex(args.spi_size)) + debug_print(".image_size = ", hex(args.image_size)) + debug_print(".tag0_loc = ", hex(args.tag0_loc)) + debug_print(".tag1_loc = ", hex(args.tag1_loc)) + debug_print(".header_loc = ", hex(args.header_loc)) + if args.rw_loc < 0: + debug_print(".rw_loc = ", args.rw_loc) + else: + debug_print(".rw_loc = ", hex(args.rw_loc)) + debug_print(".spi_clock (MHz) = ", args.spi_clock) + debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd)) + debug_print(".test_spi = ", args.test_spi) + debug_print(".test_ecrw = ", args.test_ecrw) + debug_print(".verbose = ", args.verbose) + debug_print(".spi_drive_str = ", args.spi_drive_str) + debug_print(".spi_slew_fast = ", args.spi_slew_fast) + debug_print(".spi_cpol = ", args.spi_cpol) + debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi) + debug_print(".spi_cpha_miso = ", args.spi_cpha_miso) + debug_print(".vtr2_V18 = ", args.vtr2_V18) + debug_print(".vtr3_V18 = ", args.vtr3_V18) + # # Handle quiet mode build from Makefile @@ -589,215 +701,229 @@ def print_args(args): # || 48 * [0] # def main(): - global debug_print + global debug_print + + args = parseargs() + + if args.verbose: + debug_print = print - args = parseargs() - - if args.verbose: - debug_print = print + debug_print("Begin pack_ec_mec152x.py script") + + print_args(args) + + chip_dict = MEC152X_DICT + + # Boot-ROM requires header location aligned >= 256 bytes. + # CrOS EC flash image update code requires EC_RO/RW location to be aligned + # on a flash erase size boundary and EC_RO/RW size to be a multiple of + # the smallest flash erase block size. + # + assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, ( + "Header location %d is not on a flash erase block boundary boundary" + % args.header_loc + ) + + max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE + if args.test_spi: + max_image_size -= 32 # SHA256 digest + + assert args.image_size > max_image_size, ( + "Image size exceeds maximum" % args.image_size + ) + + spi_size = args.spi_size * 1024 + debug_print("SPI Flash image size in bytes =", hex(spi_size)) + + # !!! IMPORTANT !!! + # These values MUST match chip/mchp/config_flash_layout.h + # defines. + # MEC152x Boot-ROM TAGs are at offset 0 and 4. + # lfw + EC_RO starts at beginning of second 4KB sector + # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash. + + spi_list = [] + + debug_print("args.input = ", args.input) + debug_print("args.loader_file = ", args.loader_file) + debug_print("args.image_size = ", hex(args.image_size)) + + rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) + debug_print("Temporary file containing LFW + EC_RO is ", rorofile) + + lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"]) + lfw_ecro_len = len(lfw_ecro) + debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len)) + + # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes + if args.test_spi: + crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4])) + crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little") + lfw_ecro[-4:] = crc32_ecro_bytes + debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE)) + debug_print("CRC32(ecro-4) = ", hex(crc32_ecro)) + + # Reads entry point from offset 4 of file. + # This assumes binary has Cortex-M4 vector table at offset 0. + # 32-bit word at offset 0x0 initial stack pointer value + # 32-bit word at offset 0x4 address of reset handler + # NOTE: reset address will have bit[0]=1 to ensure thumb mode. + lfw_ecro_entry = GetEntryPoint(rorofile) + + # Chromebooks are not using MEC BootROM SPI header/payload authentication + # or payload encryption. In this case the header authentication signature + # is filled with the hash digest of the respective entity. + # BuildHeader2 computes the hash digest and stores it in the correct + # header location. + header = BuildHeader2(args, chip_dict, lfw_ecro_len, LOAD_ADDR, lfw_ecro_entry) + printByteArrayAsHex(header, "Header(lfw_ecro)") + + # If payload encryption used then encrypt payload and + # generate Payload Key Header. If encryption not used + # payload is not modified and the method returns None + encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) + printByteArrayAsHex(encryption_key_header, "LFW + EC_RO encryption_key_header") + + ec_info_block = GenEcInfoBlock(args, chip_dict) + printByteArrayAsHex(ec_info_block, "EC Info Block") + + cosignature = GenCoSignature(args, chip_dict, lfw_ecro) + printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") + + trailer = GenTrailer( + args, chip_dict, lfw_ecro, encryption_key_header, ec_info_block, cosignature + ) + + printByteArrayAsHex(trailer, "LFW + EC_RO trailer") + + # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only. + tag0 = BuildTag(args) + tag1 = tag0 + + debug_print("Call to GetPayloadFromOffset") + debug_print("args.input = ", args.input) + debug_print("args.image_size = ", hex(args.image_size)) + + ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict["PAD_SIZE"]) + debug_print("type(ecrw) is ", type(ecrw)) + debug_print("len(ecrw) is ", hex(len(ecrw))) + + # truncate to args.image_size + ecrw_len = len(ecrw) + if ecrw_len > args.image_size: + debug_print( + "Truncate EC_RW len={0:0x} to image_size={1:0x}".format( + ecrw_len, args.image_size + ) + ) + ecrw = ecrw[: args.image_size] + ecrw_len = len(ecrw) + + debug_print("len(EC_RW) = ", hex(ecrw_len)) + + # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes + if args.test_spi: + crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4])) + crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little") + ecrw[-4:] = crc32_ecrw_bytes + debug_print("ecrw len = ", hex(len(ecrw))) + debug_print("CRC32(ecrw) = ", hex(crc32_ecrw)) + + # Assume FW layout is standard Cortex-M style with vector + # table at start of binary. + # 32-bit word at offset 0x0 = Initial stack pointer + # 32-bit word at offset 0x4 = Address of reset handler + ecrw_entry_tuple = struct.unpack_from("= 256 bytes. - # CrOS EC flash image update code requires EC_RO/RW location to be aligned - # on a flash erase size boundary and EC_RO/RW size to be a multiple of - # the smallest flash erase block size. - # - assert (args.header_loc % SPI_ERASE_BLOCK_SIZE) == 0, \ - "Header location %d is not on a flash erase block boundary boundary" % args.header_loc - - max_image_size = CHIP_MAX_CODE_SRAM_KB - LFW_SIZE - if args.test_spi: - max_image_size -= 32 # SHA256 digest - - assert args.image_size > max_image_size, \ - "Image size exceeds maximum" % args.image_size - - spi_size = args.spi_size * 1024 - debug_print("SPI Flash image size in bytes =", hex(spi_size)) - - # !!! IMPORTANT !!! - # These values MUST match chip/mchp/config_flash_layout.h - # defines. - # MEC152x Boot-ROM TAGs are at offset 0 and 4. - # lfw + EC_RO starts at beginning of second 4KB sector - # EC_RW starts at (flash size / 2) i.e. 0x40000 for a 512KB flash. - - spi_list = [] - - debug_print("args.input = ",args.input) - debug_print("args.loader_file = ",args.loader_file) - debug_print("args.image_size = ",hex(args.image_size)) - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - debug_print("Temporary file containing LFW + EC_RO is ", rorofile) - - lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"]) - lfw_ecro_len = len(lfw_ecro) - debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len)) - - # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes - if args.test_spi: - crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4])) - crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little') - lfw_ecro[-4:] = crc32_ecro_bytes - debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE)) - debug_print("CRC32(ecro-4) = ", hex(crc32_ecro)) - - # Reads entry point from offset 4 of file. - # This assumes binary has Cortex-M4 vector table at offset 0. - # 32-bit word at offset 0x0 initial stack pointer value - # 32-bit word at offset 0x4 address of reset handler - # NOTE: reset address will have bit[0]=1 to ensure thumb mode. - lfw_ecro_entry = GetEntryPoint(rorofile) - - # Chromebooks are not using MEC BootROM SPI header/payload authentication - # or payload encryption. In this case the header authentication signature - # is filled with the hash digest of the respective entity. - # BuildHeader2 computes the hash digest and stores it in the correct - # header location. - header = BuildHeader2(args, chip_dict, lfw_ecro_len, - LOAD_ADDR, lfw_ecro_entry) - printByteArrayAsHex(header, "Header(lfw_ecro)") - - # If payload encryption used then encrypt payload and - # generate Payload Key Header. If encryption not used - # payload is not modified and the method returns None - encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) - printByteArrayAsHex(encryption_key_header, - "LFW + EC_RO encryption_key_header") - - ec_info_block = GenEcInfoBlock(args, chip_dict) - printByteArrayAsHex(ec_info_block, "EC Info Block") - - cosignature = GenCoSignature(args, chip_dict, lfw_ecro) - printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") - - trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header, - ec_info_block, cosignature) - - printByteArrayAsHex(trailer, "LFW + EC_RO trailer") - - # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only. - tag0 = BuildTag(args) - tag1 = tag0 - - debug_print("Call to GetPayloadFromOffset") - debug_print("args.input = ", args.input) - debug_print("args.image_size = ", hex(args.image_size)) - - ecrw = GetPayloadFromOffset(args.input, args.image_size, - chip_dict["PAD_SIZE"]) - debug_print("type(ecrw) is ", type(ecrw)) - debug_print("len(ecrw) is ", hex(len(ecrw))) - - # truncate to args.image_size - ecrw_len = len(ecrw) - if ecrw_len > args.image_size: - debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size)) - ecrw = ecrw[:args.image_size] - ecrw_len = len(ecrw) - - debug_print("len(EC_RW) = ", hex(ecrw_len)) - - # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes - if args.test_spi: - crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4])) - crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder='little') - ecrw[-4:] = crc32_ecrw_bytes - debug_print("ecrw len = ", hex(len(ecrw))) - debug_print("CRC32(ecrw) = ", hex(crc32_ecrw)) - - # Assume FW layout is standard Cortex-M style with vector - # table at start of binary. - # 32-bit word at offset 0x0 = Initial stack pointer - # 32-bit word at offset 0x4 = Address of reset handler - ecrw_entry_tuple = struct.unpack_from('= 0: - rw_offset = args.rw_loc - - debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) - - assert rw_offset >= offset, \ - print("""Offset of EC_RW at {0:08x} overlaps end - of EC_RO at {0:08x}""".format(rw_offset, offset)) - - spi_list.append((rw_offset, ecrw, "ecrw")) - offset = rw_offset + len(ecrw) - - spi_list = sorted(spi_list) - - dumpsects(spi_list) - - # - # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0 - # instead of end of SPI. - # - with open(args.output, 'wb') as f: - debug_print("Write spi list to file", args.output) - addr = 0 - for s in spi_list: - if addr < s[0]: - debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr), - "fill with 0xff") - f.write(b'\xff' * (s[0] - addr)) - addr = s[0] - debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data") - - f.write(s[1]) - addr += len(s[1]) - - if addr < spi_size: - debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr), - "fill with 0xff") - f.write(b'\xff' * (spi_size - addr)) - - f.flush() + if ec_info_block != None: + spi_list.append((offset, ec_info_block, "EC Info Block")) + offset += len(ec_info_block) -if __name__ == '__main__': - main() + if cosignature != None: + spi_list.append((offset, cosignature, "ECRO Cosignature")) + offset += len(cosignature) + + if trailer != None: + spi_list.append((offset, trailer, "ECRO Trailer")) + offset += len(trailer) + + # EC_RW location + rw_offset = int(spi_size // 2) + if args.rw_loc >= 0: + rw_offset = args.rw_loc + + debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) + + assert rw_offset >= offset, print( + """Offset of EC_RW at {0:08x} overlaps end + of EC_RO at {0:08x}""".format( + rw_offset, offset + ) + ) + + spi_list.append((rw_offset, ecrw, "ecrw")) + offset = rw_offset + len(ecrw) + + spi_list = sorted(spi_list) + + dumpsects(spi_list) + + # + # MEC152X Boot-ROM locates TAG0/1 at SPI offset 0 + # instead of end of SPI. + # + with open(args.output, "wb") as f: + debug_print("Write spi list to file", args.output) + addr = 0 + for s in spi_list: + if addr < s[0]: + debug_print( + "Offset ", hex(addr), " Length", hex(s[0] - addr), "fill with 0xff" + ) + f.write(b"\xff" * (s[0] - addr)) + addr = s[0] + debug_print( + "Offset ", hex(addr), " Length", hex(len(s[1])), "write data" + ) + + f.write(s[1]) + addr += len(s[1]) + + if addr < spi_size: + debug_print( + "Offset ", hex(addr), " Length", hex(spi_size - addr), "fill with 0xff" + ) + f.write(b"\xff" * (spi_size - addr)) + + f.flush() + + +if __name__ == "__main__": + main() diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py index 32747d3d9a..bd5ff6edba 100755 --- a/chip/mchp/util/pack_ec_mec172x.py +++ b/chip/mchp/util/pack_ec_mec172x.py @@ -16,7 +16,7 @@ import os import struct import subprocess import tempfile -import zlib # CRC32 +import zlib # CRC32 # MEC172x has 416KB SRAM from 0xC0000 - 0x127FFF # SRAM is divided into contiguous CODE & DATA @@ -28,8 +28,8 @@ import zlib # CRC32 # SPI_ERASE_BLOCK_SIZE = 0x1000 SPI_CLOCK_LIST = [48, 24, 16, 12, 96] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] -SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3} +SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B, 0x6B] +SPI_DRIVE_STR_DICT = {2: 0, 4: 1, 8: 2, 12: 3} # Maximum EC_RO/EC_RW code size is based upon SPI flash erase # sector size, MEC172x Boot-ROM TAG, Header, Footer. # SPI Offset Description @@ -38,118 +38,156 @@ SPI_DRIVE_STR_DICT = {2:0, 4:1, 8:2, 12:3} # 0x1140 - 0x213F 4KB LFW # 0x2040 - 0x3EFFF # 0x3F000 - 0x3FFFF BootROM EC_INFO_BLK || COSIG || ENCR_KEY_HDR(optional) || TRAILER -CHIP_MAX_CODE_SRAM_KB = (256 - 12) +CHIP_MAX_CODE_SRAM_KB = 256 - 12 MEC172X_DICT = { - "LFW_SIZE": 0x1000, - "LOAD_ADDR": 0xC0000, - "TAG_SIZE": 4, - "KEY_BLOB_SIZE": 1584, - "HEADER_SIZE":0x140, - "HEADER_VER":0x03, - "PAYLOAD_GRANULARITY":128, - "PAYLOAD_PAD_BYTE":b'\xff', - "EC_INFO_BLK_SZ":128, - "ENCR_KEY_HDR_SZ":128, - "COSIG_SZ":96, - "TRAILER_SZ":160, - "TAILER_PAD_BYTE":b'\xff', - "PAD_SIZE":128 - } - -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] + "LFW_SIZE": 0x1000, + "LOAD_ADDR": 0xC0000, + "TAG_SIZE": 4, + "KEY_BLOB_SIZE": 1584, + "HEADER_SIZE": 0x140, + "HEADER_VER": 0x03, + "PAYLOAD_GRANULARITY": 128, + "PAYLOAD_PAD_BYTE": b"\xff", + "EC_INFO_BLK_SZ": 128, + "ENCR_KEY_HDR_SZ": 128, + "COSIG_SZ": 96, + "TRAILER_SZ": 160, + "TAILER_PAD_BYTE": b"\xff", + "PAD_SIZE": 128, +} + +CRC_TABLE = [ + 0x00, + 0x07, + 0x0E, + 0x09, + 0x1C, + 0x1B, + 0x12, + 0x15, + 0x38, + 0x3F, + 0x36, + 0x31, + 0x24, + 0x23, + 0x2A, + 0x2D, +] + def mock_print(*args, **kwargs): - pass + pass + debug_print = mock_print # Debug helper routine def dumpsects(spi_list): - debug_print("spi_list has {0} entries".format(len(spi_list))) - for s in spi_list: - debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0],len(s[1]),s[2])) + debug_print("spi_list has {0} entries".format(len(spi_list))) + for s in spi_list: + debug_print("0x{0:x} 0x{1:x} {2:s}".format(s[0], len(s[1]), s[2])) + def printByteArrayAsHex(ba, title): - debug_print(title,"= ") - if ba == None: - debug_print("None") - return - - count = 0 - for b in ba: - count = count + 1 - debug_print("0x{0:02x}, ".format(b),end="") - if (count % 8) == 0: - debug_print("") - debug_print("") + debug_print(title, "= ") + if ba == None: + debug_print("None") + return + + count = 0 + for b in ba: + count = count + 1 + debug_print("0x{0:02x}, ".format(b), end="") + if (count % 8) == 0: + debug_print("") + debug_print("") + def Crc8(crc, data): - """Update CRC8 value.""" - for v in data: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 + """Update CRC8 value.""" + for v in data: + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]) + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)]) + return crc ^ 0x55 + def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return int.from_bytes(s, byteorder='little') + """Read entry point from payload EC image.""" + with open(payload_file, "rb") as f: + f.seek(4) + s = f.read(4) + return int.from_bytes(s, byteorder="little") + def GetPayloadFromOffset(payload_file, offset, padsize): - """Read payload and pad it to padsize.""" - with open(payload_file, 'rb') as f: - f.seek(offset) - payload = bytearray(f.read()) - rem_len = len(payload) % padsize - debug_print("GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format(padsize,len(payload),rem_len)) + """Read payload and pad it to padsize.""" + with open(payload_file, "rb") as f: + f.seek(offset) + payload = bytearray(f.read()) + rem_len = len(payload) % padsize + debug_print( + "GetPayload: padsize={0:0x} len(payload)={1:0x} rem={2:0x}".format( + padsize, len(payload), rem_len + ) + ) - if rem_len: - payload += PAYLOAD_PAD_BYTE * (padsize - rem_len) - debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len)) + if rem_len: + payload += PAYLOAD_PAD_BYTE * (padsize - rem_len) + debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len)) + + return payload - return payload def GetPayload(payload_file, padsize): - """Read payload and pad it to padsize""" - return GetPayloadFromOffset(payload_file, 0, padsize) + """Read payload and pad it to padsize""" + return GetPayloadFromOffset(payload_file, 0, padsize) + def GetPublicKey(pem_file): - """Extract public exponent and modulus from PEM file.""" - result = subprocess.run(['openssl', 'rsa', '-in', pem_file, '-text', - '-noout'], stdout=subprocess.PIPE, encoding='utf-8') - modulus_raw = [] - in_modulus = False - for line in result.stdout.splitlines(): - if line.startswith('modulus'): - in_modulus = True - elif not line.startswith(' '): - in_modulus = False - elif in_modulus: - modulus_raw.extend(line.strip().strip(':').split(':')) - if line.startswith('publicExponent'): - exp = int(line.split(' ')[1], 10) - modulus_raw.reverse() - modulus = bytearray((int(x, 16) for x in modulus_raw[:256])) - return struct.pack(' 3: - header[6] |= 0x01 - else: - header[5] = spiFreqIndex - - header[5] |= ((GetEncodedSpiDriveStrength(args) & 0x03) << 2) - header[5] |= ((GetSpiSlewRate(args) & 0x01) << 4) - header[5] |= ((GetSpiCpol(args) & 0x01) << 5) - header[5] |= ((GetSpiCphaMosi(args) & 0x01) << 6) - header[5] |= ((GetSpiCphaMiso(args) & 0x01) << 7) - - # header[6] - # b[0] value set above - # b[2:1] = 00b, b[5:3]=111b - # b[7]=0 No encryption of FW payload - header[6] |= 0x7 << 3 - - # SPI read command set same for both chips - header[7] = GetSpiReadCmdParameter(args) & 0xFF - - # bytes 0x08 - 0x0b - header[0x08:0x0C] = load_addr.to_bytes(4, byteorder='little') - # bytes 0x0c - 0x0f - header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder='little') - - # bytes 0x10 - 0x11 payload length in units of 128 bytes - assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, \ - print("Payload size not a multiple of {0}".format(chip_dict["PAYLOAD_GRANULARITY"])) - - payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"]) - assert payload_units < 0x10000, \ - print("Payload too large: len={0} units={1}".format(payload_len, payload_units)) - - header[0x10:0x12] = payload_units.to_bytes(2, 'little') - - # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be - # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO). - # LFW location provided on the command line. - assert (args.lfw_loc % 4096 == 0), \ - print("LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc)) - - assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), \ - print("LFW location not greater than header location + header size") - - lfw_ofs = args.lfw_loc - args.header_loc - header[0x14:0x18] = lfw_ofs.to_bytes(4, 'little') - - # MEC172x: authentication key select. Authentication not used, set to 0. - header[0x18] = 0 - - # header[0x19], header[0x20:0x28] - # header[0x1A:0x20] reserved 0 - # MEC172x: supports SPI flash devices with drive strength settings - # TODO leave these fields at 0 for now. We must add 6 command line - # arguments. - - # header[0x28:0x48] reserve can be any value - # header[0x48:0x50] Customer use. TODO - # authentication disabled, leave these 0. - # header[0x50:0x80] ECDSA P384 Authentication Public key Rx - # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry - - # header[0xB0:0xE0] = SHA384(header[0:0xB0]) - header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest() - # When ECDSA authentication is disabled MCHP SPI image generator - # is filling the last 48 bytes of the Header with 0xff - header[-48:] = b'\xff' * 48 - - debug_print("After hash: len(header) = ", len(header)) - - return header + header_size = chip_dict["HEADER_SIZE"] + + # allocate zero filled header + header = bytearray(b"\x00" * header_size) + debug_print("len(header) = ", len(header)) + + # Identifier and header version + header[0:4] = b"PHCM" + header[4] = chip_dict["HEADER_VER"] + + # SPI frequency, drive strength, CPOL/CPHA encoding same for both chips + spiFreqIndex = GetSpiClockParameter(args) + if spiFreqIndex > 3: + header[6] |= 0x01 + else: + header[5] = spiFreqIndex + + header[5] |= (GetEncodedSpiDriveStrength(args) & 0x03) << 2 + header[5] |= (GetSpiSlewRate(args) & 0x01) << 4 + header[5] |= (GetSpiCpol(args) & 0x01) << 5 + header[5] |= (GetSpiCphaMosi(args) & 0x01) << 6 + header[5] |= (GetSpiCphaMiso(args) & 0x01) << 7 + + # header[6] + # b[0] value set above + # b[2:1] = 00b, b[5:3]=111b + # b[7]=0 No encryption of FW payload + header[6] |= 0x7 << 3 + + # SPI read command set same for both chips + header[7] = GetSpiReadCmdParameter(args) & 0xFF + + # bytes 0x08 - 0x0b + header[0x08:0x0C] = load_addr.to_bytes(4, byteorder="little") + # bytes 0x0c - 0x0f + header[0x0C:0x10] = payload_entry.to_bytes(4, byteorder="little") + + # bytes 0x10 - 0x11 payload length in units of 128 bytes + assert payload_len % chip_dict["PAYLOAD_GRANULARITY"] == 0, print( + "Payload size not a multiple of {0}".format(chip_dict["PAYLOAD_GRANULARITY"]) + ) + + payload_units = int(payload_len // chip_dict["PAYLOAD_GRANULARITY"]) + assert payload_units < 0x10000, print( + "Payload too large: len={0} units={1}".format(payload_len, payload_units) + ) + + header[0x10:0x12] = payload_units.to_bytes(2, "little") + + # bytes 0x14 - 0x17 TODO offset from start of payload to FW payload to be + # loaded by Boot-ROM. We ask Boot-ROM to load (LFW || EC_RO). + # LFW location provided on the command line. + assert args.lfw_loc % 4096 == 0, print( + "LFW location not on a 4KB boundary! 0x{0:0x}".format(args.lfw_loc) + ) + + assert args.lfw_loc >= (args.header_loc + chip_dict["HEADER_SIZE"]), print( + "LFW location not greater than header location + header size" + ) + + lfw_ofs = args.lfw_loc - args.header_loc + header[0x14:0x18] = lfw_ofs.to_bytes(4, "little") + + # MEC172x: authentication key select. Authentication not used, set to 0. + header[0x18] = 0 + + # header[0x19], header[0x20:0x28] + # header[0x1A:0x20] reserved 0 + # MEC172x: supports SPI flash devices with drive strength settings + # TODO leave these fields at 0 for now. We must add 6 command line + # arguments. + + # header[0x28:0x48] reserve can be any value + # header[0x48:0x50] Customer use. TODO + # authentication disabled, leave these 0. + # header[0x50:0x80] ECDSA P384 Authentication Public key Rx + # header[0x80:0xB0] ECDSA P384 Authentication Public key Ry + + # header[0xB0:0xE0] = SHA384(header[0:0xB0]) + header[0xB0:0xE0] = hashlib.sha384(header[0:0xB0]).digest() + # When ECDSA authentication is disabled MCHP SPI image generator + # is filling the last 48 bytes of the Header with 0xff + header[-48:] = b"\xff" * 48 + + debug_print("After hash: len(header) = ", len(header)) + + return header + # # MEC172x 128-byte EC Info Block appended to end of padded FW binary. @@ -361,9 +410,10 @@ def BuildHeader2(args, chip_dict, payload_len, load_addr, payload_entry): # byte[0x7f] = current imeage revision # def GenEcInfoBlock(args, chip_dict): - # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"]) - ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"]) - return ecinfo + # ecinfo = bytearray([0xff] * chip_dict["EC_INFO_BLK_SZ"]) + ecinfo = bytearray(chip_dict["EC_INFO_BLK_SZ"]) + return ecinfo + # # Generate SPI FW image co-signature. @@ -376,7 +426,8 @@ def GenEcInfoBlock(args, chip_dict): # signature. # def GenCoSignature(args, chip_dict, payload): - return bytearray(b'\xff' * chip_dict["COSIG_SZ"]) + return bytearray(b"\xff" * chip_dict["COSIG_SZ"]) + # # Generate SPI FW Image trailer. @@ -387,27 +438,33 @@ def GenCoSignature(args, chip_dict, payload): # trailer[144:160] = 0xFF. Boot-ROM spec. says these bytes should be random. # Authentication & encryption are not used therefore random data # is not necessary. -def GenTrailer(args, chip_dict, payload, encryption_key_header, - ec_info_block, cosignature): +def GenTrailer( + args, chip_dict, payload, encryption_key_header, ec_info_block, cosignature +): debug_print("GenTrailer SHA384 computation") trailer = bytearray(chip_dict["TAILER_PAD_BYTE"] * chip_dict["TRAILER_SZ"]) hasher = hashlib.sha384() hasher.update(payload) debug_print(" Update: payload len=0x{0:0x}".format(len(payload))) if ec_info_block != None: - hasher.update(ec_info_block) - debug_print(" Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block))) + hasher.update(ec_info_block) + debug_print(" Update: ec_info_block len=0x{0:0x}".format(len(ec_info_block))) if encryption_key_header != None: - hasher.update(encryption_key_header) - debug_print(" Update: encryption_key_header len=0x{0:0x}".format(len(encryption_key_header))) + hasher.update(encryption_key_header) + debug_print( + " Update: encryption_key_header len=0x{0:0x}".format( + len(encryption_key_header) + ) + ) if cosignature != None: - hasher.update(cosignature) - debug_print(" Update: cosignature len=0x{0:0x}".format(len(cosignature))) + hasher.update(cosignature) + debug_print(" Update: cosignature len=0x{0:0x}".format(len(cosignature))) trailer[0:48] = hasher.digest() - trailer[-16:] = 16 * b'\xff' + trailer[-16:] = 16 * b"\xff" return trailer + # MEC172x supports two 32-bit Tags located at offsets 0x0 and 0x4 # in the SPI flash. # Tag format: @@ -418,16 +475,21 @@ def GenTrailer(args, chip_dict, payload, encryption_key_header, # to the same flash part. # def BuildTag(args): - tag = bytearray([(args.header_loc >> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - tag.append(Crc8(0, tag)) - return tag + tag = bytearray( + [ + (args.header_loc >> 8) & 0xFF, + (args.header_loc >> 16) & 0xFF, + (args.header_loc >> 24) & 0xFF, + ] + ) + tag.append(Crc8(0, tag)) + return tag + def BuildTagFromHdrAddr(header_loc): - tag = bytearray([(header_loc >> 8) & 0xff, - (header_loc >> 16) & 0xff, - (header_loc >> 24) & 0xff]) + tag = bytearray( + [(header_loc >> 8) & 0xFF, (header_loc >> 16) & 0xFF, (header_loc >> 24) & 0xFF] + ) tag.append(Crc8(0, tag)) return tag @@ -444,12 +506,13 @@ def BuildTagFromHdrAddr(header_loc): # Output: # bytearray of length 4 def BuildFlashMap(secondSpiFlashBaseAddr): - flashmap = bytearray(4) - flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xff - flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xff - flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xff - flashmap[3] = Crc8(0, flashmap) - return flashmap + flashmap = bytearray(4) + flashmap[0] = (secondSpiFlashBaseAddr >> 12) & 0xFF + flashmap[1] = (secondSpiFlashBaseAddr >> 20) & 0xFF + flashmap[2] = (secondSpiFlashBaseAddr >> 28) & 0xFF + flashmap[3] = Crc8(0, flashmap) + return flashmap + # # Creates temporary file for read/write @@ -460,21 +523,22 @@ def BuildFlashMap(secondSpiFlashBaseAddr): # Returns temporary file name # def PacklfwRoImage(rorw_file, loader_file, image_size): - """Create a temp file with the - first image_size bytes from the loader file and append bytes - from the rorw file. - return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: # read 4KB loader file - pro = fin1.read() - fo.write(pro) # write 4KB loader data to temp file - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - - fo.write(ro) - fo.close() - - return fo.name + """Create a temp file with the + first image_size bytes from the loader file and append bytes + from the rorw file. + return the filename""" + fo = tempfile.NamedTemporaryFile(delete=False) # Need to keep file around + with open(loader_file, "rb") as fin1: # read 4KB loader file + pro = fin1.read() + fo.write(pro) # write 4KB loader data to temp file + with open(rorw_file, "rb") as fin: + ro = fin.read(image_size) + + fo.write(ro) + fo.close() + + return fo.name + # # Generate a test EC_RW image of same size @@ -485,136 +549,193 @@ def PacklfwRoImage(rorw_file, loader_file, image_size): # process hash generation. # def gen_test_ecrw(pldrw): - debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) - debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) - cookie1_pos = pldrw.find(b'\x99\x88\x77\xce') - cookie2_pos = pldrw.find(b'\xdd\xbb\xaa\xce', cookie1_pos+4) - t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: - for i in range(0, cookie1_pos): - pldrw[i] = 0xA5 - for i in range(cookie2_pos+4, len(pldrw)): - pldrw[i] = 0xA5 - - with open("ec_RW_test.bin", "wb") as fecrw: - fecrw.write(pldrw[:size]) + debug_print("gen_test_ecrw: pldrw type =", type(pldrw)) + debug_print("len pldrw =", len(pldrw), " = ", hex(len(pldrw))) + cookie1_pos = pldrw.find(b"\x99\x88\x77\xce") + cookie2_pos = pldrw.find(b"\xdd\xbb\xaa\xce", cookie1_pos + 4) + t = struct.unpack(" 0 and cookie2_pos > cookie1_pos: + for i in range(0, cookie1_pos): + pldrw[i] = 0xA5 + for i in range(cookie2_pos + 4, len(pldrw)): + pldrw[i] = 0xA5 + + with open("ec_RW_test.bin", "wb") as fecrw: + fecrw.write(pldrw[:size]) + def parseargs(): - rpath = os.path.dirname(os.path.relpath(__file__)) - - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("--load_addr", type=int, - help="EC SRAM load address", - default=0xC0000) - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in KB", - default=512) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash. Must be on a 256 byte boundary", - default=0x0100) - parser.add_argument("--lfw_loc", type=int, - help="Location of LFW in SPI flash. Must be on a 4KB boundary", - default=0x1000) - parser.add_argument("--lfw_size", type=int, - help="LFW size in bytes", - default=0x1000) - parser.add_argument("-r", "--rw_loc", type=int, - help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", - default=-1) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image. Default 244KB", - default=(244 * 1024)) - parser.add_argument("--test_spi", action='store_true', - help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", - default=False) - parser.add_argument("--test_ecrw", action='store_true', - help="Use fixed pattern for EC_RW but preserve image_data", - default=False) - parser.add_argument("--verbose", action='store_true', - help="Enable verbose output", - default=False) - parser.add_argument("--tag0_loc", type=int, - help="MEC172x TAG0 SPI offset", - default=0) - parser.add_argument("--tag1_loc", type=int, - help="MEC172x TAG1 SPI offset", - default=4) - parser.add_argument("--spi_drive_str", type=int, - help="Chip SPI drive strength in mA: 2, 4, 8, or 12", - default=4) - parser.add_argument("--spi_slew_fast", action='store_true', - help="SPI use fast slew rate. Default is False", - default=False) - parser.add_argument("--spi_cpol", type=int, - help="SPI clock polarity when idle. Defealt is 0(low)", - default=0) - parser.add_argument("--spi_cpha_mosi", type=int, - help="""SPI clock phase controller drives data. + rpath = os.path.dirname(os.path.relpath(__file__)) + + parser = argparse.ArgumentParser() + parser.add_argument( + "-i", + "--input", + help="EC binary to pack, usually ec.bin or ec.RO.flat.", + metavar="EC_BIN", + default="ec.bin", + ) + parser.add_argument( + "-o", + "--output", + help="Output flash binary file", + metavar="EC_SPI_FLASH", + default="ec.packed.bin", + ) + parser.add_argument( + "--loader_file", help="EC loader binary", default="ecloader.bin" + ) + parser.add_argument( + "--load_addr", type=int, help="EC SRAM load address", default=0xC0000 + ) + parser.add_argument( + "-s", "--spi_size", type=int, help="Size of the SPI flash in KB", default=512 + ) + parser.add_argument( + "-l", + "--header_loc", + type=int, + help="Location of header in SPI flash. Must be on a 256 byte boundary", + default=0x0100, + ) + parser.add_argument( + "--lfw_loc", + type=int, + help="Location of LFW in SPI flash. Must be on a 4KB boundary", + default=0x1000, + ) + parser.add_argument( + "--lfw_size", type=int, help="LFW size in bytes", default=0x1000 + ) + parser.add_argument( + "-r", + "--rw_loc", + type=int, + help="Start offset of EC_RW. Default is -1 meaning 1/2 flash size", + default=-1, + ) + parser.add_argument( + "--spi_clock", + type=int, + help="SPI clock speed. 8, 12, 24, or 48 MHz.", + default=24, + ) + parser.add_argument( + "--spi_read_cmd", + type=int, + help="SPI read command. 0x3, 0xB, 0x3B, or 0x6B.", + default=0xB, + ) + parser.add_argument( + "--image_size", + type=int, + help="Size of a single image. Default 244KB", + default=(244 * 1024), + ) + parser.add_argument( + "--test_spi", + action="store_true", + help="Test SPI data integrity by adding CRC32 in last 4-bytes of RO/RW binaries", + default=False, + ) + parser.add_argument( + "--test_ecrw", + action="store_true", + help="Use fixed pattern for EC_RW but preserve image_data", + default=False, + ) + parser.add_argument( + "--verbose", action="store_true", help="Enable verbose output", default=False + ) + parser.add_argument( + "--tag0_loc", type=int, help="MEC172x TAG0 SPI offset", default=0 + ) + parser.add_argument( + "--tag1_loc", type=int, help="MEC172x TAG1 SPI offset", default=4 + ) + parser.add_argument( + "--spi_drive_str", + type=int, + help="Chip SPI drive strength in mA: 2, 4, 8, or 12", + default=4, + ) + parser.add_argument( + "--spi_slew_fast", + action="store_true", + help="SPI use fast slew rate. Default is False", + default=False, + ) + parser.add_argument( + "--spi_cpol", + type=int, + help="SPI clock polarity when idle. Defealt is 0(low)", + default=0, + ) + parser.add_argument( + "--spi_cpha_mosi", + type=int, + help="""SPI clock phase controller drives data. 0=Data driven on active to inactive clock edge, 1=Data driven on inactive to active clock edge""", - default=0) - parser.add_argument("--spi_cpha_miso", type=int, - help="""SPI clock phase controller samples data. + default=0, + ) + parser.add_argument( + "--spi_cpha_miso", + type=int, + help="""SPI clock phase controller samples data. 0=Data sampled on inactive to active clock edge, 1=Data sampled on active to inactive clock edge""", - default=0) + default=0, + ) + + return parser.parse_args() - return parser.parse_args() def print_args(args): - debug_print("parsed arguments:") - debug_print(".input = ", args.input) - debug_print(".output = ", args.output) - debug_print(".loader_file = ", args.loader_file) - debug_print(".spi_size (KB) = ", hex(args.spi_size)) - debug_print(".image_size = ", hex(args.image_size)) - debug_print(".load_addr", hex(args.load_addr)) - debug_print(".tag0_loc = ", hex(args.tag0_loc)) - debug_print(".tag1_loc = ", hex(args.tag1_loc)) - debug_print(".header_loc = ", hex(args.header_loc)) - debug_print(".lfw_loc = ", hex(args.lfw_loc)) - debug_print(".lfw_size = ", hex(args.lfw_size)) - if args.rw_loc < 0: - debug_print(".rw_loc = ", args.rw_loc) - else: - debug_print(".rw_loc = ", hex(args.rw_loc)) - debug_print(".spi_clock (MHz) = ", args.spi_clock) - debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd)) - debug_print(".test_spi = ", args.test_spi) - debug_print(".test_ecrw = ", args.test_ecrw) - debug_print(".verbose = ", args.verbose) - debug_print(".spi_drive_str = ", args.spi_drive_str) - debug_print(".spi_slew_fast = ", args.spi_slew_fast) - debug_print(".spi_cpol = ", args.spi_cpol) - debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi) - debug_print(".spi_cpha_miso = ", args.spi_cpha_miso) + debug_print("parsed arguments:") + debug_print(".input = ", args.input) + debug_print(".output = ", args.output) + debug_print(".loader_file = ", args.loader_file) + debug_print(".spi_size (KB) = ", hex(args.spi_size)) + debug_print(".image_size = ", hex(args.image_size)) + debug_print(".load_addr", hex(args.load_addr)) + debug_print(".tag0_loc = ", hex(args.tag0_loc)) + debug_print(".tag1_loc = ", hex(args.tag1_loc)) + debug_print(".header_loc = ", hex(args.header_loc)) + debug_print(".lfw_loc = ", hex(args.lfw_loc)) + debug_print(".lfw_size = ", hex(args.lfw_size)) + if args.rw_loc < 0: + debug_print(".rw_loc = ", args.rw_loc) + else: + debug_print(".rw_loc = ", hex(args.rw_loc)) + debug_print(".spi_clock (MHz) = ", args.spi_clock) + debug_print(".spi_read_cmd = ", hex(args.spi_read_cmd)) + debug_print(".test_spi = ", args.test_spi) + debug_print(".test_ecrw = ", args.test_ecrw) + debug_print(".verbose = ", args.verbose) + debug_print(".spi_drive_str = ", args.spi_drive_str) + debug_print(".spi_slew_fast = ", args.spi_slew_fast) + debug_print(".spi_cpol = ", args.spi_cpol) + debug_print(".spi_cpha_mosi = ", args.spi_cpha_mosi) + debug_print(".spi_cpha_miso = ", args.spi_cpha_miso) + def spi_list_append(mylist, loc, data, description): - """Append SPI data block tuple to list""" - t = (loc, data, description) - mylist.append(t) - debug_print("Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format(loc, len(data), description)) + """Append SPI data block tuple to list""" + t = (loc, data, description) + mylist.append(t) + debug_print( + "Add SPI entry: offset=0x{0:08x} len=0x{1:0x} descr={2}".format( + loc, len(data), description + ) + ) + # # Handle quiet mode build from Makefile @@ -652,200 +773,207 @@ def spi_list_append(mylist, loc, data, description): # || 48 * [0] # def main(): - global debug_print - - args = parseargs() - - if args.verbose: - debug_print = print - - debug_print("Begin pack_ec_mec172x.py script") - - print_args(args) - - chip_dict = MEC172X_DICT - - # Boot-ROM requires header location aligned >= 256 bytes. - # CrOS EC flash image update code requires EC_RO/RW location to be aligned - # on a flash erase size boundary and EC_RO/RW size to be a multiple of - # the smallest flash erase block size. - - spi_size = args.spi_size * 1024 - spi_image_size = spi_size // 2 - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - debug_print("Temporary file containing LFW + EC_RO is ", rorofile) - - lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"]) - lfw_ecro_len = len(lfw_ecro) - debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len)) - - # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes - if args.test_spi: - crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4])) - crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder='little') - lfw_ecro[-4:] = crc32_ecro_bytes - debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE)) - debug_print("CRC32(ecro-4) = ", hex(crc32_ecro)) - - # Reads entry point from offset 4 of file. - # This assumes binary has Cortex-M4 vector table at offset 0. - # 32-bit word at offset 0x0 initial stack pointer value - # 32-bit word at offset 0x4 address of reset handler - # NOTE: reset address will have bit[0]=1 to ensure thumb mode. - lfw_ecro_entry = GetEntryPoint(rorofile) - debug_print("LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry)) - - # Chromebooks are not using MEC BootROM SPI header/payload authentication - # or payload encryption. In this case the header authentication signature - # is filled with the hash digest of the respective entity. - # BuildHeader2 computes the hash digest and stores it in the correct - # header location. - header = BuildHeader2(args, chip_dict, lfw_ecro_len, - args.load_addr, lfw_ecro_entry) - printByteArrayAsHex(header, "Header(lfw_ecro)") - - # If payload encryption used then encrypt payload and - # generate Payload Key Header. If encryption not used - # payload is not modified and the method returns None - encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) - printByteArrayAsHex(encryption_key_header, - "LFW + EC_RO encryption_key_header") - - ec_info_block = GenEcInfoBlock(args, chip_dict) - printByteArrayAsHex(ec_info_block, "EC Info Block") - - cosignature = GenCoSignature(args, chip_dict, lfw_ecro) - printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") - - trailer = GenTrailer(args, chip_dict, lfw_ecro, encryption_key_header, - ec_info_block, cosignature) - - printByteArrayAsHex(trailer, "LFW + EC_RO trailer") - - # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only. - tag0 = BuildTag(args) - tag1 = tag0 - - debug_print("Call to GetPayloadFromOffset") - debug_print("args.input = ", args.input) - debug_print("args.image_size = ", hex(args.image_size)) - - ecrw = GetPayloadFromOffset(args.input, args.image_size, - chip_dict["PAD_SIZE"]) - debug_print("type(ecrw) is ", type(ecrw)) - debug_print("len(ecrw) is ", hex(len(ecrw))) - - # truncate to args.image_size - ecrw_len = len(ecrw) - if ecrw_len > args.image_size: - debug_print("Truncate EC_RW len={0:0x} to image_size={1:0x}".format(ecrw_len,args.image_size)) - ecrw = ecrw[:args.image_size] - ecrw_len = len(ecrw) + global debug_print + + args = parseargs() + + if args.verbose: + debug_print = print + + debug_print("Begin pack_ec_mec172x.py script") + + print_args(args) + + chip_dict = MEC172X_DICT + + # Boot-ROM requires header location aligned >= 256 bytes. + # CrOS EC flash image update code requires EC_RO/RW location to be aligned + # on a flash erase size boundary and EC_RO/RW size to be a multiple of + # the smallest flash erase block size. + + spi_size = args.spi_size * 1024 + spi_image_size = spi_size // 2 + + rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) + debug_print("Temporary file containing LFW + EC_RO is ", rorofile) + + lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"]) + lfw_ecro_len = len(lfw_ecro) + debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len)) + + # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes + if args.test_spi: + crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4])) + crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little") + lfw_ecro[-4:] = crc32_ecro_bytes + debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE)) + debug_print("CRC32(ecro-4) = ", hex(crc32_ecro)) + + # Reads entry point from offset 4 of file. + # This assumes binary has Cortex-M4 vector table at offset 0. + # 32-bit word at offset 0x0 initial stack pointer value + # 32-bit word at offset 0x4 address of reset handler + # NOTE: reset address will have bit[0]=1 to ensure thumb mode. + lfw_ecro_entry = GetEntryPoint(rorofile) + debug_print("LFW Entry point from GetEntryPoint = 0x{0:08x}".format(lfw_ecro_entry)) + + # Chromebooks are not using MEC BootROM SPI header/payload authentication + # or payload encryption. In this case the header authentication signature + # is filled with the hash digest of the respective entity. + # BuildHeader2 computes the hash digest and stores it in the correct + # header location. + header = BuildHeader2(args, chip_dict, lfw_ecro_len, args.load_addr, lfw_ecro_entry) + printByteArrayAsHex(header, "Header(lfw_ecro)") + + # If payload encryption used then encrypt payload and + # generate Payload Key Header. If encryption not used + # payload is not modified and the method returns None + encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) + printByteArrayAsHex(encryption_key_header, "LFW + EC_RO encryption_key_header") + + ec_info_block = GenEcInfoBlock(args, chip_dict) + printByteArrayAsHex(ec_info_block, "EC Info Block") + + cosignature = GenCoSignature(args, chip_dict, lfw_ecro) + printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") + + trailer = GenTrailer( + args, chip_dict, lfw_ecro, encryption_key_header, ec_info_block, cosignature + ) + + printByteArrayAsHex(trailer, "LFW + EC_RO trailer") + + # Build TAG0. Set TAG1=TAG0 Boot-ROM is allowed to load EC-RO only. + tag0 = BuildTag(args) + tag1 = tag0 + + debug_print("Call to GetPayloadFromOffset") + debug_print("args.input = ", args.input) + debug_print("args.image_size = ", hex(args.image_size)) + + ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict["PAD_SIZE"]) + debug_print("type(ecrw) is ", type(ecrw)) + debug_print("len(ecrw) is ", hex(len(ecrw))) + + # truncate to args.image_size + ecrw_len = len(ecrw) + if ecrw_len > args.image_size: + debug_print( + "Truncate EC_RW len={0:0x} to image_size={1:0x}".format( + ecrw_len, args.image_size + ) + ) + ecrw = ecrw[: args.image_size] + ecrw_len = len(ecrw) + + debug_print("len(EC_RW) = ", hex(ecrw_len)) + + # SPI test mode compute CRC32 of EC_RW and store in last 4 bytes + if args.test_spi: + crc32_ecrw = zlib.crc32(bytes(ecrw[0:-4])) + crc32_ecrw_bytes = crc32_ecrw.to_bytes(4, byteorder="little") + ecrw[-4:] = crc32_ecrw_bytes + debug_print("ecrw len = ", hex(len(ecrw))) + debug_print("CRC32(ecrw) = ", hex(crc32_ecrw)) + + # Assume FW layout is standard Cortex-M style with vector + # table at start of binary. + # 32-bit word at offset 0x0 = Initial stack pointer + # 32-bit word at offset 0x4 = Address of reset handler + ecrw_entry_tuple = struct.unpack_from("= 0: - rw_offset = args.rw_loc - - debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) - - #spi_list.append((rw_offset, ecrw, "ecrw")) - spi_list_append(spi_list, rw_offset, ecrw, "EC_RW") - offset = rw_offset + len(ecrw) - - spi_list = sorted(spi_list) - - debug_print("Display spi_list:") - dumpsects(spi_list) - - # - # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0 - # instead of end of SPI. - # - with open(args.output, 'wb') as f: - debug_print("Write spi list to file", args.output) - addr = 0 - for s in spi_list: - if addr < s[0]: - debug_print("Offset ",hex(addr)," Length", hex(s[0]-addr), - "fill with 0xff") - f.write(b'\xff' * (s[0] - addr)) - addr = s[0] - debug_print("Offset ",hex(addr), " Length", hex(len(s[1])), "write data") - - f.write(s[1]) - addr += len(s[1]) - - if addr < spi_size: - debug_print("Offset ",hex(addr), " Length", hex(spi_size - addr), - "fill with 0xff") - f.write(b'\xff' * (spi_size - addr)) + if ec_info_block != None: + spi_list_append(spi_list, offset, ec_info_block, "LFW-EC_RO Info Block") + offset += len(ec_info_block) - f.flush() + debug_print("SPI offset after ec_info_block = 0x{0:08x}".format(offset)) -if __name__ == '__main__': - main() + if cosignature != None: + # spi_list.append((offset, co-signature, "ECRO Co-signature")) + spi_list_append(spi_list, offset, cosignature, "LFW-EC_RO Co-signature") + offset += len(cosignature) + + debug_print("SPI offset after co-signature = 0x{0:08x}".format(offset)) + + if trailer != None: + # spi_list.append((offset, trailer, "ECRO Trailer")) + spi_list_append(spi_list, offset, trailer, "LFW-EC_RO trailer") + offset += len(trailer) + + debug_print("SPI offset after trailer = 0x{0:08x}".format(offset)) + + # EC_RW location + rw_offset = int(spi_size // 2) + if args.rw_loc >= 0: + rw_offset = args.rw_loc + + debug_print("rw_offset = 0x{0:08x}".format(rw_offset)) + + # spi_list.append((rw_offset, ecrw, "ecrw")) + spi_list_append(spi_list, rw_offset, ecrw, "EC_RW") + offset = rw_offset + len(ecrw) + + spi_list = sorted(spi_list) + + debug_print("Display spi_list:") + dumpsects(spi_list) + + # + # MEC172x Boot-ROM locates TAG0/1 at SPI offset 0 + # instead of end of SPI. + # + with open(args.output, "wb") as f: + debug_print("Write spi list to file", args.output) + addr = 0 + for s in spi_list: + if addr < s[0]: + debug_print( + "Offset ", hex(addr), " Length", hex(s[0] - addr), "fill with 0xff" + ) + f.write(b"\xff" * (s[0] - addr)) + addr = s[0] + debug_print( + "Offset ", hex(addr), " Length", hex(len(s[1])), "write data" + ) + + f.write(s[1]) + addr += len(s[1]) + + if addr < spi_size: + debug_print( + "Offset ", hex(addr), " Length", hex(spi_size - addr), "fill with 0xff" + ) + f.write(b"\xff" * (spi_size - addr)) + + f.flush() + + +if __name__ == "__main__": + main() diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py index 9783ffb2d5..736f9efcac 100755 --- a/chip/mec1322/util/pack_ec.py +++ b/chip/mec1322/util/pack_ec.py @@ -21,228 +21,325 @@ import tempfile LOAD_ADDR = 0x100000 HEADER_SIZE = 0x140 SPI_CLOCK_LIST = [48, 24, 12, 8] -SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b] +SPI_READ_CMD_LIST = [0x3, 0xB, 0x3B] + +CRC_TABLE = [ + 0x00, + 0x07, + 0x0E, + 0x09, + 0x1C, + 0x1B, + 0x12, + 0x15, + 0x38, + 0x3F, + 0x36, + 0x31, + 0x24, + 0x23, + 0x2A, + 0x2D, +] -CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, - 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] def Crc8(crc, data): - """Update CRC8 value.""" - for v in data: - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]); - crc = ((crc << 4) & 0xff) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xf)]); - return crc ^ 0x55 + """Update CRC8 value.""" + for v in data: + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v >> 4)]) + crc = ((crc << 4) & 0xFF) ^ (CRC_TABLE[(crc >> 4) ^ (v & 0xF)]) + return crc ^ 0x55 + def GetEntryPoint(payload_file): - """Read entry point from payload EC image.""" - with open(payload_file, 'rb') as f: - f.seek(4) - s = f.read(4) - return struct.unpack('> 6) & 0xFF) + header.append((payload_len >> 14) & 0xFF) + PadZeroTo(header, 0x14) + header.extend(struct.pack("> 6) & 0xff) - header.append((payload_len >> 14) & 0xff) - PadZeroTo(header, 0x14) - header.extend(struct.pack('> 8) & 0xff, - (args.header_loc >> 16) & 0xff, - (args.header_loc >> 24) & 0xff]) - if args.chip_select != 0: - tag[2] |= 0x80 - tag.append(Crc8(0, tag)) - return tag + tag = bytearray( + [ + (args.header_loc >> 8) & 0xFF, + (args.header_loc >> 16) & 0xFF, + (args.header_loc >> 24) & 0xFF, + ] + ) + if args.chip_select != 0: + tag[2] |= 0x80 + tag.append(Crc8(0, tag)) + return tag + def PacklfwRoImage(rorw_file, loader_file, image_size): - """TODO:Clean up to get rid of Temp file and just use memory - to save data""" - """Create a temp file with the + """TODO:Clean up to get rid of Temp file and just use memory + to save data""" + """Create a temp file with the first image_size bytes from the rorw file and the bytes from the loader_file appended return the filename""" - fo=tempfile.NamedTemporaryFile(delete=False) # Need to keep file around - with open(loader_file,'rb') as fin1: - pro = fin1.read() - fo.write(pro) - with open(rorw_file, 'rb') as fin: - ro = fin.read(image_size) - fo.write(ro) - fo.close() - return fo.name + fo = tempfile.NamedTemporaryFile(delete=False) # Need to keep file around + with open(loader_file, "rb") as fin1: + pro = fin1.read() + fo.write(pro) + with open(rorw_file, "rb") as fin: + ro = fin.read(image_size) + fo.write(ro) + fo.close() + return fo.name + def parseargs(): - parser = argparse.ArgumentParser() - parser.add_argument("-i", "--input", - help="EC binary to pack, usually ec.bin or ec.RO.flat.", - metavar="EC_BIN", default="ec.bin") - parser.add_argument("-o", "--output", - help="Output flash binary file", - metavar="EC_SPI_FLASH", default="ec.packed.bin") - parser.add_argument("--header_key", - help="PEM key file for signing header", - default="rsakey_sign_header.pem") - parser.add_argument("--payload_key", - help="PEM key file for signing payload", - default="rsakey_sign_payload.pem") - parser.add_argument("--loader_file", - help="EC loader binary", - default="ecloader.bin") - parser.add_argument("-s", "--spi_size", type=int, - help="Size of the SPI flash in MB", - default=4) - parser.add_argument("-l", "--header_loc", type=int, - help="Location of header in SPI flash", - default=0x170000) - parser.add_argument("-p", "--payload_offset", type=int, - help="The offset of payload from the header", - default=0x240) - parser.add_argument("-r", "--rwpayload_loc", type=int, - help="The offset of payload from the header", - default=0x190000) - parser.add_argument("-z", "--romstart", type=int, - help="The first location to output of the rom", - default=0) - parser.add_argument("-c", "--chip_select", type=int, - help="Chip select signal to use, either 0 or 1.", - default=0) - parser.add_argument("--spi_clock", type=int, - help="SPI clock speed. 8, 12, 24, or 48 MHz.", - default=24) - parser.add_argument("--spi_read_cmd", type=int, - help="SPI read command. 0x3, 0xB, or 0x3B.", - default=0xb) - parser.add_argument("--image_size", type=int, - help="Size of a single image.", - default=(96 * 1024)) - return parser.parse_args() + parser = argparse.ArgumentParser() + parser.add_argument( + "-i", + "--input", + help="EC binary to pack, usually ec.bin or ec.RO.flat.", + metavar="EC_BIN", + default="ec.bin", + ) + parser.add_argument( + "-o", + "--output", + help="Output flash binary file", + metavar="EC_SPI_FLASH", + default="ec.packed.bin", + ) + parser.add_argument( + "--header_key", + help="PEM key file for signing header", + default="rsakey_sign_header.pem", + ) + parser.add_argument( + "--payload_key", + help="PEM key file for signing payload", + default="rsakey_sign_payload.pem", + ) + parser.add_argument( + "--loader_file", help="EC loader binary", default="ecloader.bin" + ) + parser.add_argument( + "-s", "--spi_size", type=int, help="Size of the SPI flash in MB", default=4 + ) + parser.add_argument( + "-l", + "--header_loc", + type=int, + help="Location of header in SPI flash", + default=0x170000, + ) + parser.add_argument( + "-p", + "--payload_offset", + type=int, + help="The offset of payload from the header", + default=0x240, + ) + parser.add_argument( + "-r", + "--rwpayload_loc", + type=int, + help="The offset of payload from the header", + default=0x190000, + ) + parser.add_argument( + "-z", + "--romstart", + type=int, + help="The first location to output of the rom", + default=0, + ) + parser.add_argument( + "-c", + "--chip_select", + type=int, + help="Chip select signal to use, either 0 or 1.", + default=0, + ) + parser.add_argument( + "--spi_clock", + type=int, + help="SPI clock speed. 8, 12, 24, or 48 MHz.", + default=24, + ) + parser.add_argument( + "--spi_read_cmd", + type=int, + help="SPI read command. 0x3, 0xB, or 0x3B.", + default=0xB, + ) + parser.add_argument( + "--image_size", type=int, help="Size of a single image.", default=(96 * 1024) + ) + return parser.parse_args() + def main(): - args = parseargs() - - spi_size = args.spi_size * 1024 - args.header_loc = spi_size - (128 * 1024) - args.rwpayload_loc = spi_size - (256 * 1024) - args.romstart = spi_size - (256 * 1024) - - spi_list = [] - - rorofile=PacklfwRoImage(args.input, args.loader_file, args.image_size) - payload = GetPayload(rorofile) - payload_len = len(payload) - payload_signature = SignByteArray(payload, args.payload_key) - header = BuildHeader(args, payload_len, rorofile) - header_signature = SignByteArray(header, args.header_key) - tag = BuildTag(args) - # truncate the RW to 128k - payloadrw = GetPayloadFromOffset(args.input,args.image_size)[:128*1024] - os.remove(rorofile) # clean up the temp file - - spi_list.append((args.header_loc, header, "header")) - spi_list.append((args.header_loc + HEADER_SIZE, header_signature, "header_signature")) - spi_list.append((args.header_loc + args.payload_offset, payload, "payload")) - spi_list.append((args.header_loc + args.payload_offset + payload_len, - payload_signature, "payload_signature")) - spi_list.append((spi_size - 256, tag, "tag")) - spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw")) - - - spi_list = sorted(spi_list) - - with open(args.output, 'wb') as f: - addr = args.romstart - for s in spi_list: - assert addr <= s[0] - if addr < s[0]: - f.write(b'\xff' * (s[0] - addr)) - addr = s[0] - f.write(s[1]) - addr += len(s[1]) - if addr < spi_size: - f.write(b'\xff' * (spi_size - addr)) - -if __name__ == '__main__': - main() + args = parseargs() + + spi_size = args.spi_size * 1024 + args.header_loc = spi_size - (128 * 1024) + args.rwpayload_loc = spi_size - (256 * 1024) + args.romstart = spi_size - (256 * 1024) + + spi_list = [] + + rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) + payload = GetPayload(rorofile) + payload_len = len(payload) + payload_signature = SignByteArray(payload, args.payload_key) + header = BuildHeader(args, payload_len, rorofile) + header_signature = SignByteArray(header, args.header_key) + tag = BuildTag(args) + # truncate the RW to 128k + payloadrw = GetPayloadFromOffset(args.input, args.image_size)[: 128 * 1024] + os.remove(rorofile) # clean up the temp file + + spi_list.append((args.header_loc, header, "header")) + spi_list.append( + (args.header_loc + HEADER_SIZE, header_signature, "header_signature") + ) + spi_list.append((args.header_loc + args.payload_offset, payload, "payload")) + spi_list.append( + ( + args.header_loc + args.payload_offset + payload_len, + payload_signature, + "payload_signature", + ) + ) + spi_list.append((spi_size - 256, tag, "tag")) + spi_list.append((args.rwpayload_loc, payloadrw, "payloadrw")) + + spi_list = sorted(spi_list) + + with open(args.output, "wb") as f: + addr = args.romstart + for s in spi_list: + assert addr <= s[0] + if addr < s[0]: + f.write(b"\xff" * (s[0] - addr)) + addr = s[0] + f.write(s[1]) + addr += len(s[1]) + if addr < spi_size: + f.write(b"\xff" * (spi_size - addr)) + + +if __name__ == "__main__": + main() diff --git a/cts/common/board.py b/cts/common/board.py index d2c8e02b04..f62d7bdfc5 100644 --- a/cts/common/board.py +++ b/cts/common/board.py @@ -10,379 +10,401 @@ from __future__ import print_function -from abc import ABCMeta -from abc import abstractmethod import os import shutil import subprocess as sp -import serial +from abc import ABCMeta, abstractmethod +import serial import six - -OCD_SCRIPT_DIR = '/usr/share/openocd/scripts' +OCD_SCRIPT_DIR = "/usr/share/openocd/scripts" OPENOCD_CONFIGS = { - 'stm32l476g-eval': 'board/stm32l4discovery.cfg', - 'nucleo-f072rb': 'board/st_nucleo_f0.cfg', - 'nucleo-f411re': 'board/st_nucleo_f4.cfg', + "stm32l476g-eval": "board/stm32l4discovery.cfg", + "nucleo-f072rb": "board/st_nucleo_f0.cfg", + "nucleo-f411re": "board/st_nucleo_f4.cfg", } FLASH_OFFSETS = { - 'stm32l476g-eval': '0x08000000', - 'nucleo-f072rb': '0x08000000', - 'nucleo-f411re': '0x08000000', + "stm32l476g-eval": "0x08000000", + "nucleo-f072rb": "0x08000000", + "nucleo-f411re": "0x08000000", } -REBOOT_MARKER = 'UART initialized after reboot' +REBOOT_MARKER = "UART initialized after reboot" def get_subprocess_args(): - if six.PY3: - return {'encoding': 'utf-8'} - return {} + if six.PY3: + return {"encoding": "utf-8"} + return {} class Board(six.with_metaclass(ABCMeta, object)): - """Class representing a single board connected to a host machine. - - Attributes: - board: String containing actual type of board, i.e. nucleo-f072rb - config: Directory of board config file relative to openocd's - scripts directory - hla_serial: String containing board's hla_serial number (if board - is an stm32 board) - tty_port: String that is the path to the tty port which board's - UART outputs to - tty: String of file descriptor for tty_port - """ - - def __init__(self, board, module, hla_serial=None): - """Initializes a board object with given attributes. - - Args: - board: String containing board name - module: String of the test module you are building, - i.e. gpio, timer, etc. - hla_serial: Serial number if board's adaptor is an HLA - - Raises: - RuntimeError: Board is not supported - """ - if board not in OPENOCD_CONFIGS: - msg = 'OpenOcd configuration not found for ' + board - raise RuntimeError(msg) - if board not in FLASH_OFFSETS: - msg = 'Flash offset not found for ' + board - raise RuntimeError(msg) - self.board = board - self.flash_offset = FLASH_OFFSETS[self.board] - self.openocd_config = OPENOCD_CONFIGS[self.board] - self.module = module - self.hla_serial = hla_serial - self.tty_port = None - self.tty = None - - def reset_log_dir(self): - """Reset log directory.""" - if os.path.isdir(self.log_dir): - shutil.rmtree(self.log_dir) - os.makedirs(self.log_dir) - - @staticmethod - def get_stlink_serials(): - """Gets serial numbers of all st-link v2.1 board attached to host. - - Returns: - List of serials + """Class representing a single board connected to a host machine. + + Attributes: + board: String containing actual type of board, i.e. nucleo-f072rb + config: Directory of board config file relative to openocd's + scripts directory + hla_serial: String containing board's hla_serial number (if board + is an stm32 board) + tty_port: String that is the path to the tty port which board's + UART outputs to + tty: String of file descriptor for tty_port """ - usb_args = ['sudo', 'lsusb', '-v', '-d', '0x0483:0x374b'] - st_link_info = sp.check_output(usb_args, **get_subprocess_args()) - st_serials = [] - for line in st_link_info.split('\n'): - if 'iSerial' not in line: - continue - words = line.split() - if len(words) <= 2: - continue - st_serials.append(words[2].strip()) - return st_serials - - @abstractmethod - def get_serial(self): - """Subclass should implement this.""" - pass - - def send_openocd_commands(self, commands): - """Send a command to the board via openocd. - - Args: - commands: A list of commands to send - - Returns: - True if execution is successful or False otherwise. - """ - args = ['sudo', 'openocd', '-s', OCD_SCRIPT_DIR, - '-f', self.openocd_config, '-c', 'hla_serial ' + self.hla_serial] - - for cmd in commands: - args += ['-c', cmd] - args += ['-c', 'shutdown'] - - rv = 1 - with open(self.openocd_log, 'a') as output: - rv = sp.call(args, stdout=output, stderr=sp.STDOUT) - if rv != 0: - self.dump_openocd_log() - - return rv == 0 - - def dump_openocd_log(self): - with open(self.openocd_log) as log: - print(log.read()) + def __init__(self, board, module, hla_serial=None): + """Initializes a board object with given attributes. + + Args: + board: String containing board name + module: String of the test module you are building, + i.e. gpio, timer, etc. + hla_serial: Serial number if board's adaptor is an HLA + + Raises: + RuntimeError: Board is not supported + """ + if board not in OPENOCD_CONFIGS: + msg = "OpenOcd configuration not found for " + board + raise RuntimeError(msg) + if board not in FLASH_OFFSETS: + msg = "Flash offset not found for " + board + raise RuntimeError(msg) + self.board = board + self.flash_offset = FLASH_OFFSETS[self.board] + self.openocd_config = OPENOCD_CONFIGS[self.board] + self.module = module + self.hla_serial = hla_serial + self.tty_port = None + self.tty = None + + def reset_log_dir(self): + """Reset log directory.""" + if os.path.isdir(self.log_dir): + shutil.rmtree(self.log_dir) + os.makedirs(self.log_dir) + + @staticmethod + def get_stlink_serials(): + """Gets serial numbers of all st-link v2.1 board attached to host. + + Returns: + List of serials + """ + usb_args = ["sudo", "lsusb", "-v", "-d", "0x0483:0x374b"] + st_link_info = sp.check_output(usb_args, **get_subprocess_args()) + st_serials = [] + for line in st_link_info.split("\n"): + if "iSerial" not in line: + continue + words = line.split() + if len(words) <= 2: + continue + st_serials.append(words[2].strip()) + return st_serials + + @abstractmethod + def get_serial(self): + """Subclass should implement this.""" + pass + + def send_openocd_commands(self, commands): + """Send a command to the board via openocd. + + Args: + commands: A list of commands to send + + Returns: + True if execution is successful or False otherwise. + """ + args = [ + "sudo", + "openocd", + "-s", + OCD_SCRIPT_DIR, + "-f", + self.openocd_config, + "-c", + "hla_serial " + self.hla_serial, + ] + + for cmd in commands: + args += ["-c", cmd] + args += ["-c", "shutdown"] + + rv = 1 + with open(self.openocd_log, "a") as output: + rv = sp.call(args, stdout=output, stderr=sp.STDOUT) + + if rv != 0: + self.dump_openocd_log() + + return rv == 0 + + def dump_openocd_log(self): + with open(self.openocd_log) as log: + print(log.read()) + + def build(self, ec_dir): + """Builds test suite module for board. + + Args: + ec_dir: String of the ec directory path + + Returns: + True if build is successful or False otherwise. + """ + cmds = [ + "make", + "--directory=" + ec_dir, + "BOARD=" + self.board, + "CTS_MODULE=" + self.module, + "-j", + ] + + rv = 1 + with open(self.build_log, "a") as output: + rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT) + + if rv != 0: + self.dump_build_log() + + return rv == 0 + + def dump_build_log(self): + with open(self.build_log) as log: + print(log.read()) + + def flash(self, image_path): + """Flashes board with most recent build ec.bin.""" + cmd = [ + "reset_config connect_assert_srst", + "init", + "reset init", + "flash write_image erase %s %s" % (image_path, self.flash_offset), + ] + return self.send_openocd_commands(cmd) + + def to_string(self): + s = ( + "Type: Board\n" + "board: " + self.board + "\n" + "hla_serial: " + self.hla_serial + "\n" + "openocd_config: " + self.openocd_config + "\n" + "tty_port: " + self.tty_port + "\n" + "tty: " + str(self.tty) + "\n" + ) + return s + + def reset_halt(self): + """Reset then halt board.""" + return self.send_openocd_commands(["init", "reset halt"]) + + def resume(self): + """Resume halting board.""" + return self.send_openocd_commands(["init", "resume"]) + + def setup_tty(self): + """Call this before calling read_tty for the first time. + + This is not in the initialization because caller only should call + this function after serial numbers are setup + """ + self.get_serial() + self.reset_halt() + self.identify_tty_port() + + tty = None + try: + tty = serial.Serial(self.tty_port, 115200, timeout=1) + except serial.SerialException: + raise ValueError( + "Failed to open " + + self.tty_port + + " of " + + self.board + + ". Please make sure the port is available and you have" + + " permission to read it. Create dialout group and run:" + + " sudo usermod -a -G dialout ." + ) + self.tty = tty + + def read_tty(self, max_boot_count=1): + """Read info from a serial port described by a file descriptor. + + Args: + max_boot_count: Stop reading if boot count exceeds this number + + Returns: + result: characters read from tty + boot: boot counts + """ + buf = [] + line = [] + boot = 0 + while True: + c = self.tty.read().decode("utf-8") + if not c: + break + line.append(c) + if c == "\n": + l = "".join(line) + buf.append(l) + if REBOOT_MARKER in l: + boot += 1 + line = [] + if boot > max_boot_count: + break + + l = "".join(line) + buf.append(l) + result = "".join(buf) - def build(self, ec_dir): - """Builds test suite module for board. + return result, boot - Args: - ec_dir: String of the ec directory path + def identify_tty_port(self): + """Saves this board's serial port.""" + dev_dir = "/dev" + id_prefix = "ID_SERIAL_SHORT=" + com_devices = [f for f in os.listdir(dev_dir) if f.startswith("ttyACM")] - Returns: - True if build is successful or False otherwise. - """ - cmds = ['make', - '--directory=' + ec_dir, - 'BOARD=' + self.board, - 'CTS_MODULE=' + self.module, - '-j'] - - rv = 1 - with open(self.build_log, 'a') as output: - rv = sp.call(cmds, stdout=output, stderr=sp.STDOUT) - - if rv != 0: - self.dump_build_log() - - return rv == 0 - - def dump_build_log(self): - with open(self.build_log) as log: - print(log.read()) - - def flash(self, image_path): - """Flashes board with most recent build ec.bin.""" - cmd = ['reset_config connect_assert_srst', - 'init', - 'reset init', - 'flash write_image erase %s %s' % (image_path, self.flash_offset)] - return self.send_openocd_commands(cmd) - - def to_string(self): - s = ('Type: Board\n' - 'board: ' + self.board + '\n' - 'hla_serial: ' + self.hla_serial + '\n' - 'openocd_config: ' + self.openocd_config + '\n' - 'tty_port: ' + self.tty_port + '\n' - 'tty: ' + str(self.tty) + '\n') - return s - - def reset_halt(self): - """Reset then halt board.""" - return self.send_openocd_commands(['init', 'reset halt']) - - def resume(self): - """Resume halting board.""" - return self.send_openocd_commands(['init', 'resume']) - - def setup_tty(self): - """Call this before calling read_tty for the first time. - - This is not in the initialization because caller only should call - this function after serial numbers are setup - """ - self.get_serial() - self.reset_halt() - self.identify_tty_port() - - tty = None - try: - tty = serial.Serial(self.tty_port, 115200, timeout=1) - except serial.SerialException: - raise ValueError('Failed to open ' + self.tty_port + ' of ' + self.board + - '. Please make sure the port is available and you have' + - ' permission to read it. Create dialout group and run:' + - ' sudo usermod -a -G dialout .') - self.tty = tty - - def read_tty(self, max_boot_count=1): - """Read info from a serial port described by a file descriptor. - - Args: - max_boot_count: Stop reading if boot count exceeds this number - - Returns: - result: characters read from tty - boot: boot counts - """ - buf = [] - line = [] - boot = 0 - while True: - c = self.tty.read().decode('utf-8') - if not c: - break - line.append(c) - if c == '\n': - l = ''.join(line) - buf.append(l) - if REBOOT_MARKER in l: - boot += 1 - line = [] - if boot > max_boot_count: - break - - l = ''.join(line) - buf.append(l) - result = ''.join(buf) - - return result, boot - - def identify_tty_port(self): - """Saves this board's serial port.""" - dev_dir = '/dev' - id_prefix = 'ID_SERIAL_SHORT=' - com_devices = [f for f in os.listdir(dev_dir) if f.startswith('ttyACM')] - - for device in com_devices: - self.tty_port = os.path.join(dev_dir, device) - properties = sp.check_output( - ['udevadm', 'info', '-a', '-n', self.tty_port, '--query=property'], - **get_subprocess_args()) - for line in [l.strip() for l in properties.split('\n')]: - if line.startswith(id_prefix): - if self.hla_serial == line[len(id_prefix):]: - return + for device in com_devices: + self.tty_port = os.path.join(dev_dir, device) + properties = sp.check_output( + ["udevadm", "info", "-a", "-n", self.tty_port, "--query=property"], + **get_subprocess_args() + ) + for line in [l.strip() for l in properties.split("\n")]: + if line.startswith(id_prefix): + if self.hla_serial == line[len(id_prefix) :]: + return - # If we get here without returning, something is wrong - raise RuntimeError('The device dev path could not be found') + # If we get here without returning, something is wrong + raise RuntimeError("The device dev path could not be found") - def close_tty(self): - """Close tty.""" - self.tty.close() + def close_tty(self): + """Close tty.""" + self.tty.close() class TestHarness(Board): - """Subclass of Board representing a Test Harness. + """Subclass of Board representing a Test Harness. - Attributes: - serial_path: Path to file containing serial number - """ - - def __init__(self, board, module, log_dir, serial_path): - """Initializes a board object with given attributes. - - Args: - board: board name - module: module name - log_dir: Directory where log file is stored + Attributes: serial_path: Path to file containing serial number """ - Board.__init__(self, board, module) - self.log_dir = log_dir - self.openocd_log = os.path.join(log_dir, 'openocd_th.log') - self.build_log = os.path.join(log_dir, 'build_th.log') - self.serial_path = serial_path - self.reset_log_dir() - - def get_serial(self): - """Loads serial number from saved location.""" - if self.hla_serial: - return # serial was already loaded - try: - with open(self.serial_path, mode='r') as f: - s = f.read() - self.hla_serial = s.strip() + + def __init__(self, board, module, log_dir, serial_path): + """Initializes a board object with given attributes. + + Args: + board: board name + module: module name + log_dir: Directory where log file is stored + serial_path: Path to file containing serial number + """ + Board.__init__(self, board, module) + self.log_dir = log_dir + self.openocd_log = os.path.join(log_dir, "openocd_th.log") + self.build_log = os.path.join(log_dir, "build_th.log") + self.serial_path = serial_path + self.reset_log_dir() + + def get_serial(self): + """Loads serial number from saved location.""" + if self.hla_serial: + return # serial was already loaded + try: + with open(self.serial_path, mode="r") as f: + s = f.read() + self.hla_serial = s.strip() + return + except IOError: + msg = ( + "Your TH board has not been identified.\n" + "Connect only TH and run the script --setup, then try again." + ) + raise RuntimeError(msg) + + def save_serial(self): + """Saves the TH serial number to a file.""" + serials = Board.get_stlink_serials() + if len(serials) > 1: + msg = ( + "There are more than one test board connected to the host." + "\nConnect only the test harness and remove other boards." + ) + raise RuntimeError(msg) + if len(serials) < 1: + msg = "No test boards were found.\n" "Check boards are connected." + raise RuntimeError(msg) + + s = serials[0] + serial_dir = os.path.dirname(self.serial_path) + if not os.path.exists(serial_dir): + os.makedirs(serial_dir) + with open(self.serial_path, mode="w") as f: + f.write(s) + self.hla_serial = s + + print("Your TH serial", s, "has been saved as", self.serial_path) return - except IOError: - msg = ('Your TH board has not been identified.\n' - 'Connect only TH and run the script --setup, then try again.') - raise RuntimeError(msg) - - def save_serial(self): - """Saves the TH serial number to a file.""" - serials = Board.get_stlink_serials() - if len(serials) > 1: - msg = ('There are more than one test board connected to the host.' - '\nConnect only the test harness and remove other boards.') - raise RuntimeError(msg) - if len(serials) < 1: - msg = ('No test boards were found.\n' - 'Check boards are connected.') - raise RuntimeError(msg) - - s = serials[0] - serial_dir = os.path.dirname(self.serial_path) - if not os.path.exists(serial_dir): - os.makedirs(serial_dir) - with open(self.serial_path, mode='w') as f: - f.write(s) - self.hla_serial = s - - print('Your TH serial', s, 'has been saved as', self.serial_path) - return class DeviceUnderTest(Board): - """Subclass of Board representing a DUT board. + """Subclass of Board representing a DUT board. - Attributes: - th: Reference to test harness board to which this DUT is attached - """ - - def __init__(self, board, th, module, log_dir, hla_ser=None): - """Initializes a DUT object. - - Args: - board: String containing board name + Attributes: th: Reference to test harness board to which this DUT is attached - module: module name - log_dir: Directory where log file is stored - hla_ser: Serial number if board uses an HLA adaptor """ - Board.__init__(self, board, module, hla_serial=hla_ser) - self.th = th - self.log_dir = log_dir - self.openocd_log = os.path.join(log_dir, 'openocd_dut.log') - self.build_log = os.path.join(log_dir, 'build_dut.log') - self.reset_log_dir() - - def get_serial(self): - """Get serial number. - Precondition: The DUT and TH must both be connected, and th.hla_serial - must hold the correct value (the th's serial #) + def __init__(self, board, th, module, log_dir, hla_ser=None): + """Initializes a DUT object. + + Args: + board: String containing board name + th: Reference to test harness board to which this DUT is attached + module: module name + log_dir: Directory where log file is stored + hla_ser: Serial number if board uses an HLA adaptor + """ + Board.__init__(self, board, module, hla_serial=hla_ser) + self.th = th + self.log_dir = log_dir + self.openocd_log = os.path.join(log_dir, "openocd_dut.log") + self.build_log = os.path.join(log_dir, "build_dut.log") + self.reset_log_dir() + + def get_serial(self): + """Get serial number. + + Precondition: The DUT and TH must both be connected, and th.hla_serial + must hold the correct value (the th's serial #) + + Raises: + RuntimeError: DUT isn't found or multiple DUTs are found. + """ + if self.hla_serial is not None: + # serial was already set ('' is a valid serial) + return - Raises: - RuntimeError: DUT isn't found or multiple DUTs are found. - """ - if self.hla_serial is not None: - # serial was already set ('' is a valid serial) - return - - serials = Board.get_stlink_serials() - dut = [s for s in serials if self.th.hla_serial != s] - - # If len(dut) is 0 then your dut doesn't use an st-link device, so we - # don't have to worry about its serial number - if not dut: - msg = ('Failed to find serial for DUT.\n' - 'Is ' + self.board + ' connected?') - raise RuntimeError(msg) - if len(dut) > 1: - msg = ('Found multiple DUTs.\n' - 'You can connect only one DUT at a time. This may be caused by\n' - 'an incorrect TH serial. Check if ' + self.th.serial_path + '\n' - 'contains a correct serial.') - raise RuntimeError(msg) - - # Found your other st-link device serial! - self.hla_serial = dut[0] - return + serials = Board.get_stlink_serials() + dut = [s for s in serials if self.th.hla_serial != s] + + # If len(dut) is 0 then your dut doesn't use an st-link device, so we + # don't have to worry about its serial number + if not dut: + msg = "Failed to find serial for DUT.\n" "Is " + self.board + " connected?" + raise RuntimeError(msg) + if len(dut) > 1: + msg = ( + "Found multiple DUTs.\n" + "You can connect only one DUT at a time. This may be caused by\n" + "an incorrect TH serial. Check if " + self.th.serial_path + "\n" + "contains a correct serial." + ) + raise RuntimeError(msg) + + # Found your other st-link device serial! + self.hla_serial = dut[0] + return diff --git a/cts/cts.py b/cts/cts.py index c3e0335cab..ebc526c701 100755 --- a/cts/cts.py +++ b/cts/cts.py @@ -28,416 +28,424 @@ import argparse import os import shutil import time -import common.board as board +import common.board as board -CTS_RC_PREFIX = 'CTS_RC_' -DEFAULT_TH = 'stm32l476g-eval' -DEFAULT_DUT = 'nucleo-f072rb' +CTS_RC_PREFIX = "CTS_RC_" +DEFAULT_TH = "stm32l476g-eval" +DEFAULT_DUT = "nucleo-f072rb" MAX_SUITE_TIME_SEC = 5 -CTS_TEST_RESULT_DIR = '/tmp/ects' +CTS_TEST_RESULT_DIR = "/tmp/ects" # Host only return codes. Make sure they match values in cts.rc -CTS_RC_DID_NOT_START = -1 # test did not run. -CTS_RC_DID_NOT_END = -2 # test did not run. -CTS_RC_DUPLICATE_RUN = -3 # test was run multiple times. -CTS_RC_INVALID_RETURN_CODE = -4 # failed to parse return code +CTS_RC_DID_NOT_START = -1 # test did not run. +CTS_RC_DID_NOT_END = -2 # test did not run. +CTS_RC_DUPLICATE_RUN = -3 # test was run multiple times. +CTS_RC_INVALID_RETURN_CODE = -4 # failed to parse return code class Cts(object): - """Class that represents a eCTS run. - - Attributes: - dut: DeviceUnderTest object representing DUT - th: TestHarness object representing a test harness - module: Name of module to build/run tests for - testlist: List of strings of test names contained in given module - return_codes: Dict of strings of return codes, with a code's integer - value being the index for the corresponding string representation - """ - - def __init__(self, ec_dir, th, dut, module): - """Initializes cts class object with given arguments. - - Args: - ec_dir: Path to ec directory - th: Name of the test harness board - dut: Name of the device under test board - module: Name of module to build/run tests for (e.g. gpio, interrupt) - """ - self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module) - if os.path.isdir(self.results_dir): - shutil.rmtree(self.results_dir) - else: - os.makedirs(self.results_dir) - self.ec_dir = ec_dir - self.module = module - serial_path = os.path.join(CTS_TEST_RESULT_DIR, 'th_serial') - self.th = board.TestHarness(th, module, self.results_dir, serial_path) - self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir) - cts_dir = os.path.join(self.ec_dir, 'cts') - testlist_path = os.path.join(cts_dir, self.module, 'cts.testlist') - return_codes_path = os.path.join(cts_dir, 'common', 'cts.rc') - self.get_return_codes(return_codes_path) - self.testlist = self.get_macro_args(testlist_path, 'CTS_TEST') - - def build(self): - """Build images for DUT and TH.""" - print('Building DUT image...') - if not self.dut.build(self.ec_dir): - raise RuntimeError('Building module %s for DUT failed' % (self.module)) - print('Building TH image...') - if not self.th.build(self.ec_dir): - raise RuntimeError('Building module %s for TH failed' % (self.module)) - - def flash_boards(self): - """Flashes TH and DUT with their most recently built ec.bin.""" - cts_module = 'cts_' + self.module - image_path = os.path.join('build', self.th.board, cts_module, 'ec.bin') - self.identify_boards() - print('Flashing TH with', image_path) - if not self.th.flash(image_path): - raise RuntimeError('Flashing TH failed') - image_path = os.path.join('build', self.dut.board, cts_module, 'ec.bin') - print('Flashing DUT with', image_path) - if not self.dut.flash(image_path): - raise RuntimeError('Flashing DUT failed') - - def setup(self): - """Setup boards.""" - self.th.save_serial() - - def identify_boards(self): - """Updates serials of TH and DUT in that order (order matters).""" - self.th.get_serial() - self.dut.get_serial() - - def get_macro_args(self, filepath, macro): - """Get list of args of a macro in a file when macro. - - Args: - filepath: String containing absolute path to the file - macro: String containing text of macro to get args of - - Returns: - List of dictionaries where each entry is: - 'name': Test name, - 'th_string': Expected string from TH, - 'dut_string': Expected string from DUT, - """ - tests = [] - with open(filepath, 'r') as f: - lines = f.readlines() - joined = ''.join(lines).replace('\\\n', '').splitlines() - for l in joined: - if not l.strip().startswith(macro): - continue - d = {} - l = l.strip()[len(macro):] - l = l.strip('()').split(',') - d['name'] = l[0].strip() - d['th_rc'] = self.get_return_code_value(l[1].strip().strip('"')) - d['th_string'] = l[2].strip().strip('"') - d['dut_rc'] = self.get_return_code_value(l[3].strip().strip('"')) - d['dut_string'] = l[4].strip().strip('"') - tests.append(d) - return tests - - def get_return_codes(self, filepath): - """Read return code names from the return code definition file.""" - self.return_codes = {} - val = 0 - with open(filepath, 'r') as f: - for line in f: - line = line.strip() - if not line.startswith(CTS_RC_PREFIX): - continue - line = line.split(',')[0] - if '=' in line: - tokens = line.split('=') - line = tokens[0].strip() - val = int(tokens[1].strip()) - self.return_codes[line] = val - val += 1 - - def parse_output(self, output): - """Parse console output from DUT or TH. - - Args: - output: String containing consoule output - - Returns: - List of dictionaries where each key and value are: - name = 'ects_test_x', - started = True/False, - ended = True/False, - rc = CTS_RC_*, - output = All text between 'ects_test_x start' and 'ects_test_x end' - """ - results = [] - i = 0 - for test in self.testlist: - results.append({}) - results[i]['name'] = test['name'] - results[i]['started'] = False - results[i]['rc'] = CTS_RC_DID_NOT_START - results[i]['string'] = False - results[i]['output'] = [] - i += 1 - - i = 0 - for ln in [ln.strip() for ln in output.split('\n')]: - if i + 1 > len(results): - break - tokens = ln.split() - if len(tokens) >= 2: - if tokens[0].strip() == results[i]['name']: - if tokens[1].strip() == 'start': - # start line found - if results[i]['started']: # Already started - results[i]['rc'] = CTS_RC_DUPLICATE_RUN - else: - results[i]['rc'] = CTS_RC_DID_NOT_END - results[i]['started'] = True - continue - elif results[i]['started'] and tokens[1].strip() == 'end': - # end line found - results[i]['rc'] = CTS_RC_INVALID_RETURN_CODE - if len(tokens) == 3: - try: - results[i]['rc'] = int(tokens[2].strip()) - except ValueError: - pass - # Since index is incremented when 'end' is encountered, we don't - # need to check duplicate 'end'. - i += 1 - continue - if results[i]['started']: - results[i]['output'].append(ln) - - return results - - def get_return_code_name(self, code, strip_prefix=False): - name = '' - for k, v in self.return_codes.items(): - if v == code: - if strip_prefix: - name = k[len(CTS_RC_PREFIX):] - else: - name = k - return name - - def get_return_code_value(self, name): - if name: - return self.return_codes[name] - return 0 - - def evaluate_run(self, dut_output, th_output): - """Parse outputs to derive test results. - - Args: - dut_output: String output of DUT - th_output: String output of TH - - Returns: - th_results: list of test results for TH - dut_results: list of test results for DUT + """Class that represents a eCTS run. + + Attributes: + dut: DeviceUnderTest object representing DUT + th: TestHarness object representing a test harness + module: Name of module to build/run tests for + testlist: List of strings of test names contained in given module + return_codes: Dict of strings of return codes, with a code's integer + value being the index for the corresponding string representation """ - th_results = self.parse_output(th_output) - dut_results = self.parse_output(dut_output) - # Search for expected string in each output - for i, v in enumerate(self.testlist): - if v['th_string'] in th_results[i]['output'] or not v['th_string']: - th_results[i]['string'] = True - if v['dut_string'] in dut_results[i]['output'] or not v['dut_string']: - dut_results[i]['string'] = True + def __init__(self, ec_dir, th, dut, module): + """Initializes cts class object with given arguments. + + Args: + ec_dir: Path to ec directory + th: Name of the test harness board + dut: Name of the device under test board + module: Name of module to build/run tests for (e.g. gpio, interrupt) + """ + self.results_dir = os.path.join(CTS_TEST_RESULT_DIR, dut, module) + if os.path.isdir(self.results_dir): + shutil.rmtree(self.results_dir) + else: + os.makedirs(self.results_dir) + self.ec_dir = ec_dir + self.module = module + serial_path = os.path.join(CTS_TEST_RESULT_DIR, "th_serial") + self.th = board.TestHarness(th, module, self.results_dir, serial_path) + self.dut = board.DeviceUnderTest(dut, self.th, module, self.results_dir) + cts_dir = os.path.join(self.ec_dir, "cts") + testlist_path = os.path.join(cts_dir, self.module, "cts.testlist") + return_codes_path = os.path.join(cts_dir, "common", "cts.rc") + self.get_return_codes(return_codes_path) + self.testlist = self.get_macro_args(testlist_path, "CTS_TEST") + + def build(self): + """Build images for DUT and TH.""" + print("Building DUT image...") + if not self.dut.build(self.ec_dir): + raise RuntimeError("Building module %s for DUT failed" % (self.module)) + print("Building TH image...") + if not self.th.build(self.ec_dir): + raise RuntimeError("Building module %s for TH failed" % (self.module)) + + def flash_boards(self): + """Flashes TH and DUT with their most recently built ec.bin.""" + cts_module = "cts_" + self.module + image_path = os.path.join("build", self.th.board, cts_module, "ec.bin") + self.identify_boards() + print("Flashing TH with", image_path) + if not self.th.flash(image_path): + raise RuntimeError("Flashing TH failed") + image_path = os.path.join("build", self.dut.board, cts_module, "ec.bin") + print("Flashing DUT with", image_path) + if not self.dut.flash(image_path): + raise RuntimeError("Flashing DUT failed") + + def setup(self): + """Setup boards.""" + self.th.save_serial() + + def identify_boards(self): + """Updates serials of TH and DUT in that order (order matters).""" + self.th.get_serial() + self.dut.get_serial() + + def get_macro_args(self, filepath, macro): + """Get list of args of a macro in a file when macro. + + Args: + filepath: String containing absolute path to the file + macro: String containing text of macro to get args of + + Returns: + List of dictionaries where each entry is: + 'name': Test name, + 'th_string': Expected string from TH, + 'dut_string': Expected string from DUT, + """ + tests = [] + with open(filepath, "r") as f: + lines = f.readlines() + joined = "".join(lines).replace("\\\n", "").splitlines() + for l in joined: + if not l.strip().startswith(macro): + continue + d = {} + l = l.strip()[len(macro) :] + l = l.strip("()").split(",") + d["name"] = l[0].strip() + d["th_rc"] = self.get_return_code_value(l[1].strip().strip('"')) + d["th_string"] = l[2].strip().strip('"') + d["dut_rc"] = self.get_return_code_value(l[3].strip().strip('"')) + d["dut_string"] = l[4].strip().strip('"') + tests.append(d) + return tests + + def get_return_codes(self, filepath): + """Read return code names from the return code definition file.""" + self.return_codes = {} + val = 0 + with open(filepath, "r") as f: + for line in f: + line = line.strip() + if not line.startswith(CTS_RC_PREFIX): + continue + line = line.split(",")[0] + if "=" in line: + tokens = line.split("=") + line = tokens[0].strip() + val = int(tokens[1].strip()) + self.return_codes[line] = val + val += 1 + + def parse_output(self, output): + """Parse console output from DUT or TH. + + Args: + output: String containing consoule output + + Returns: + List of dictionaries where each key and value are: + name = 'ects_test_x', + started = True/False, + ended = True/False, + rc = CTS_RC_*, + output = All text between 'ects_test_x start' and 'ects_test_x end' + """ + results = [] + i = 0 + for test in self.testlist: + results.append({}) + results[i]["name"] = test["name"] + results[i]["started"] = False + results[i]["rc"] = CTS_RC_DID_NOT_START + results[i]["string"] = False + results[i]["output"] = [] + i += 1 - return th_results, dut_results + i = 0 + for ln in [ln.strip() for ln in output.split("\n")]: + if i + 1 > len(results): + break + tokens = ln.split() + if len(tokens) >= 2: + if tokens[0].strip() == results[i]["name"]: + if tokens[1].strip() == "start": + # start line found + if results[i]["started"]: # Already started + results[i]["rc"] = CTS_RC_DUPLICATE_RUN + else: + results[i]["rc"] = CTS_RC_DID_NOT_END + results[i]["started"] = True + continue + elif results[i]["started"] and tokens[1].strip() == "end": + # end line found + results[i]["rc"] = CTS_RC_INVALID_RETURN_CODE + if len(tokens) == 3: + try: + results[i]["rc"] = int(tokens[2].strip()) + except ValueError: + pass + # Since index is incremented when 'end' is encountered, we don't + # need to check duplicate 'end'. + i += 1 + continue + if results[i]["started"]: + results[i]["output"].append(ln) + + return results + + def get_return_code_name(self, code, strip_prefix=False): + name = "" + for k, v in self.return_codes.items(): + if v == code: + if strip_prefix: + name = k[len(CTS_RC_PREFIX) :] + else: + name = k + return name + + def get_return_code_value(self, name): + if name: + return self.return_codes[name] + return 0 + + def evaluate_run(self, dut_output, th_output): + """Parse outputs to derive test results. + + Args: + dut_output: String output of DUT + th_output: String output of TH + + Returns: + th_results: list of test results for TH + dut_results: list of test results for DUT + """ + th_results = self.parse_output(th_output) + dut_results = self.parse_output(dut_output) + + # Search for expected string in each output + for i, v in enumerate(self.testlist): + if v["th_string"] in th_results[i]["output"] or not v["th_string"]: + th_results[i]["string"] = True + if v["dut_string"] in dut_results[i]["output"] or not v["dut_string"]: + dut_results[i]["string"] = True + + return th_results, dut_results + + def print_result(self, th_results, dut_results): + """Print results to the screen. + + Args: + th_results: list of test results for TH + dut_results: list of test results for DUT + """ + len_test_name = max(len(s["name"]) for s in self.testlist) + len_code_name = max( + len(self.get_return_code_name(v, True)) for v in self.return_codes.values() + ) + + head = "{:^" + str(len_test_name) + "} " + head += "{:^" + str(len_code_name) + "} " + head += "{:^" + str(len_code_name) + "}" + head += "{:^" + str(len(" TH_STR")) + "}" + head += "{:^" + str(len(" DUT_STR")) + "}" + head += "{:^" + str(len(" RESULT")) + "}\n" + fmt = "{:" + str(len_test_name) + "} " + fmt += "{:>" + str(len_code_name) + "} " + fmt += "{:>" + str(len_code_name) + "}" + fmt += "{:>" + str(len(" TH_STR")) + "}" + fmt += "{:>" + str(len(" DUT_STR")) + "}" + fmt += "{:>" + str(len(" RESULT")) + "}\n" + + self.formatted_results = head.format( + "TEST NAME", "TH_RC", "DUT_RC", " TH_STR", " DUT_STR", " RESULT" + ) + for i, d in enumerate(dut_results): + th_cn = self.get_return_code_name(th_results[i]["rc"], True) + dut_cn = self.get_return_code_name(dut_results[i]["rc"], True) + th_res = self.evaluate_result( + th_results[i], self.testlist[i]["th_rc"], self.testlist[i]["th_string"] + ) + dut_res = self.evaluate_result( + dut_results[i], + self.testlist[i]["dut_rc"], + self.testlist[i]["dut_string"], + ) + self.formatted_results += fmt.format( + d["name"], + th_cn, + dut_cn, + "YES" if th_results[i]["string"] else "NO", + "YES" if dut_results[i]["string"] else "NO", + "PASS" if th_res and dut_res else "FAIL", + ) + + def evaluate_result(self, result, expected_rc, expected_string): + if result["rc"] != expected_rc: + return False + if expected_string and expected_string not in result["output"]: + return False + return True + + def run(self): + """Resets boards, records test results in results dir.""" + print("Reading serials...") + self.identify_boards() + print("Opening DUT tty...") + self.dut.setup_tty() + print("Opening TH tty...") + self.th.setup_tty() + + # Boards might be still writing to tty. Wait a few seconds before flashing. + time.sleep(3) + + # clear buffers + print("Clearing DUT tty...") + self.dut.read_tty() + print("Clearing TH tty...") + self.th.read_tty() + + # Resets the boards and allows them to run tests + # Due to current (7/27/16) version of sync function, + # both boards must be rest and halted, with the th + # resuming first, in order for the test suite to run in sync + print("Halting TH...") + if not self.th.reset_halt(): + raise RuntimeError("Failed to halt TH") + print("Halting DUT...") + if not self.dut.reset_halt(): + raise RuntimeError("Failed to halt DUT") + print("Resuming TH...") + if not self.th.resume(): + raise RuntimeError("Failed to resume TH") + print("Resuming DUT...") + if not self.dut.resume(): + raise RuntimeError("Failed to resume DUT") + + time.sleep(MAX_SUITE_TIME_SEC) + + print("Reading DUT tty...") + dut_output, _ = self.dut.read_tty() + self.dut.close_tty() + print("Reading TH tty...") + th_output, _ = self.th.read_tty() + self.th.close_tty() + + print("Halting TH...") + if not self.th.reset_halt(): + raise RuntimeError("Failed to halt TH") + print("Halting DUT...") + if not self.dut.reset_halt(): + raise RuntimeError("Failed to halt DUT") + + if not dut_output or not th_output: + raise ValueError( + "Output missing from boards. If you have a process " + "reading ttyACMx, please kill that process and try " + "again." + ) + + print("Pursing results...") + th_results, dut_results = self.evaluate_run(dut_output, th_output) + + # Print out results + self.print_result(th_results, dut_results) + + # Write results + dest = os.path.join(self.results_dir, "results.log") + with open(dest, "w") as fl: + fl.write(self.formatted_results) + + # Write UART outputs + dest = os.path.join(self.results_dir, "uart_th.log") + with open(dest, "w") as fl: + fl.write(th_output) + dest = os.path.join(self.results_dir, "uart_dut.log") + with open(dest, "w") as fl: + fl.write(dut_output) + + print(self.formatted_results) + + # TODO(chromium:735652): Should set exit code for the shell - def print_result(self, th_results, dut_results): - """Print results to the screen. - Args: - th_results: list of test results for TH - dut_results: list of test results for DUT - """ - len_test_name = max(len(s['name']) for s in self.testlist) - len_code_name = max(len(self.get_return_code_name(v, True)) - for v in self.return_codes.values()) - - head = '{:^' + str(len_test_name) + '} ' - head += '{:^' + str(len_code_name) + '} ' - head += '{:^' + str(len_code_name) + '}' - head += '{:^' + str(len(' TH_STR')) + '}' - head += '{:^' + str(len(' DUT_STR')) + '}' - head += '{:^' + str(len(' RESULT')) + '}\n' - fmt = '{:' + str(len_test_name) + '} ' - fmt += '{:>' + str(len_code_name) + '} ' - fmt += '{:>' + str(len_code_name) + '}' - fmt += '{:>' + str(len(' TH_STR')) + '}' - fmt += '{:>' + str(len(' DUT_STR')) + '}' - fmt += '{:>' + str(len(' RESULT')) + '}\n' - - self.formatted_results = head.format( - 'TEST NAME', 'TH_RC', 'DUT_RC', - ' TH_STR', ' DUT_STR', ' RESULT') - for i, d in enumerate(dut_results): - th_cn = self.get_return_code_name(th_results[i]['rc'], True) - dut_cn = self.get_return_code_name(dut_results[i]['rc'], True) - th_res = self.evaluate_result(th_results[i], - self.testlist[i]['th_rc'], - self.testlist[i]['th_string']) - dut_res = self.evaluate_result(dut_results[i], - self.testlist[i]['dut_rc'], - self.testlist[i]['dut_string']) - self.formatted_results += fmt.format( - d['name'], th_cn, dut_cn, - 'YES' if th_results[i]['string'] else 'NO', - 'YES' if dut_results[i]['string'] else 'NO', - 'PASS' if th_res and dut_res else 'FAIL') - - def evaluate_result(self, result, expected_rc, expected_string): - if result['rc'] != expected_rc: - return False - if expected_string and expected_string not in result['output']: - return False - return True - - def run(self): - """Resets boards, records test results in results dir.""" - print('Reading serials...') - self.identify_boards() - print('Opening DUT tty...') - self.dut.setup_tty() - print('Opening TH tty...') - self.th.setup_tty() - - # Boards might be still writing to tty. Wait a few seconds before flashing. - time.sleep(3) - - # clear buffers - print('Clearing DUT tty...') - self.dut.read_tty() - print('Clearing TH tty...') - self.th.read_tty() - - # Resets the boards and allows them to run tests - # Due to current (7/27/16) version of sync function, - # both boards must be rest and halted, with the th - # resuming first, in order for the test suite to run in sync - print('Halting TH...') - if not self.th.reset_halt(): - raise RuntimeError('Failed to halt TH') - print('Halting DUT...') - if not self.dut.reset_halt(): - raise RuntimeError('Failed to halt DUT') - print('Resuming TH...') - if not self.th.resume(): - raise RuntimeError('Failed to resume TH') - print('Resuming DUT...') - if not self.dut.resume(): - raise RuntimeError('Failed to resume DUT') - - time.sleep(MAX_SUITE_TIME_SEC) - - print('Reading DUT tty...') - dut_output, _ = self.dut.read_tty() - self.dut.close_tty() - print('Reading TH tty...') - th_output, _ = self.th.read_tty() - self.th.close_tty() - - print('Halting TH...') - if not self.th.reset_halt(): - raise RuntimeError('Failed to halt TH') - print('Halting DUT...') - if not self.dut.reset_halt(): - raise RuntimeError('Failed to halt DUT') - - if not dut_output or not th_output: - raise ValueError('Output missing from boards. If you have a process ' - 'reading ttyACMx, please kill that process and try ' - 'again.') - - print('Pursing results...') - th_results, dut_results = self.evaluate_run(dut_output, th_output) - - # Print out results - self.print_result(th_results, dut_results) - - # Write results - dest = os.path.join(self.results_dir, 'results.log') - with open(dest, 'w') as fl: - fl.write(self.formatted_results) - - # Write UART outputs - dest = os.path.join(self.results_dir, 'uart_th.log') - with open(dest, 'w') as fl: - fl.write(th_output) - dest = os.path.join(self.results_dir, 'uart_dut.log') - with open(dest, 'w') as fl: - fl.write(dut_output) - - print(self.formatted_results) - - # TODO(chromium:735652): Should set exit code for the shell +def main(): + ec_dir = os.path.realpath( + os.path.join(os.path.dirname(os.path.abspath(__file__)), "..") + ) + os.chdir(ec_dir) + + dut = DEFAULT_DUT + module = "meta" + + parser = argparse.ArgumentParser(description="Used to build/flash boards") + parser.add_argument("-d", "--dut", help="Specify DUT you want to build/flash") + parser.add_argument("-m", "--module", help="Specify module you want to build/flash") + parser.add_argument( + "-s", + "--setup", + action="store_true", + help="Connect only the TH to save its serial", + ) + parser.add_argument( + "-b", "--build", action="store_true", help="Build test suite (no flashing)" + ) + parser.add_argument( + "-f", + "--flash", + action="store_true", + help="Flash boards with most recent images", + ) + parser.add_argument( + "-r", "--run", action="store_true", help="Run tests without flashing" + ) + + args = parser.parse_args() + + if args.module: + module = args.module + + if args.dut: + dut = args.dut + + cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module) + + if args.setup: + cts.setup() + elif args.build: + cts.build() + elif args.flash: + cts.flash_boards() + elif args.run: + cts.run() + else: + cts.build() + cts.flash_boards() + cts.run() -def main(): - ec_dir = os.path.realpath(os.path.join( - os.path.dirname(os.path.abspath(__file__)), '..')) - os.chdir(ec_dir) - - dut = DEFAULT_DUT - module = 'meta' - - parser = argparse.ArgumentParser(description='Used to build/flash boards') - parser.add_argument('-d', - '--dut', - help='Specify DUT you want to build/flash') - parser.add_argument('-m', - '--module', - help='Specify module you want to build/flash') - parser.add_argument('-s', - '--setup', - action='store_true', - help='Connect only the TH to save its serial') - parser.add_argument('-b', - '--build', - action='store_true', - help='Build test suite (no flashing)') - parser.add_argument('-f', - '--flash', - action='store_true', - help='Flash boards with most recent images') - parser.add_argument('-r', - '--run', - action='store_true', - help='Run tests without flashing') - - args = parser.parse_args() - - if args.module: - module = args.module - - if args.dut: - dut = args.dut - - cts = Cts(ec_dir, DEFAULT_TH, dut=dut, module=module) - - if args.setup: - cts.setup() - elif args.build: - cts.build() - elif args.flash: - cts.flash_boards() - elif args.run: - cts.run() - else: - cts.build() - cts.flash_boards() - cts.run() - -if __name__ == '__main__': - main() +if __name__ == "__main__": + main() diff --git a/extra/cr50_rma_open/cr50_rma_open.py b/extra/cr50_rma_open/cr50_rma_open.py index 42ddbbac2d..b77b8f3dbb 100755 --- a/extra/cr50_rma_open/cr50_rma_open.py +++ b/extra/cr50_rma_open/cr50_rma_open.py @@ -57,16 +57,17 @@ CCD_IS_UNRESTRICTED = 1 << 0 WP_IS_DISABLED = 1 << 1 TESTLAB_IS_ENABLED = 1 << 2 RMA_OPENED = CCD_IS_UNRESTRICTED | WP_IS_DISABLED -URL = ('https://www.google.com/chromeos/partner/console/cr50reset?' - 'challenge=%s&hwid=%s') -RMA_SUPPORT_PROD = '0.3.3' -RMA_SUPPORT_PREPVT = '0.4.5' -DEV_MODE_OPEN_PROD = '0.3.9' -DEV_MODE_OPEN_PREPVT = '0.4.7' -TESTLAB_PROD = '0.3.10' -CR50_USB = '18d1:5014' -CR50_LSUSB_CMD = ['lsusb', '-vd', CR50_USB] -ERASED_BID = 'ffffffff' +URL = ( + "https://www.google.com/chromeos/partner/console/cr50reset?" "challenge=%s&hwid=%s" +) +RMA_SUPPORT_PROD = "0.3.3" +RMA_SUPPORT_PREPVT = "0.4.5" +DEV_MODE_OPEN_PROD = "0.3.9" +DEV_MODE_OPEN_PREPVT = "0.4.7" +TESTLAB_PROD = "0.3.10" +CR50_USB = "18d1:5014" +CR50_LSUSB_CMD = ["lsusb", "-vd", CR50_USB] +ERASED_BID = "ffffffff" DEBUG_MISSING_USB = """ Unable to find Cr50 Device 18d1:5014 @@ -128,13 +129,14 @@ DEBUG_DUT_CONTROL_OSERROR = """ Run from chroot if you are trying to use a /dev/pts ccd servo console """ + class RMAOpen(object): """Used to find the cr50 console and run RMA open""" - ENABLE_TESTLAB_CMD = 'ccd testlab enabled\n' + ENABLE_TESTLAB_CMD = "ccd testlab enabled\n" def __init__(self, device=None, usb_serial=None, servo_port=None, ip=None): - self.servo_port = servo_port if servo_port else '9999' + self.servo_port = servo_port if servo_port else "9999" self.ip = ip if device: self.set_cr50_device(device) @@ -142,18 +144,18 @@ class RMAOpen(object): self.find_cr50_servo_uart() else: self.find_cr50_device(usb_serial) - logging.info('DEVICE: %s', self.device) + logging.info("DEVICE: %s", self.device) self.check_version() self.print_platform_info() - logging.info('Cr50 setup ok') + logging.info("Cr50 setup ok") self.update_ccd_state() self.using_ccd = self.device_is_running_with_servo_ccd() def _dut_control(self, control): """Run dut-control and return the response""" try: - cmd = ['dut-control', '-p', self.servo_port, control] - return subprocess.check_output(cmd, encoding='utf-8').strip() + cmd = ["dut-control", "-p", self.servo_port, control] + return subprocess.check_output(cmd, encoding="utf-8").strip() except OSError: logging.warning(DEBUG_DUT_CONTROL_OSERROR) raise @@ -163,8 +165,8 @@ class RMAOpen(object): Find the console and configure it, so it can be used with this script. """ - self._dut_control('cr50_uart_timestamp:off') - self.device = self._dut_control('cr50_uart_pty').split(':')[-1] + self._dut_control("cr50_uart_timestamp:off") + self.device = self._dut_control("cr50_uart_pty").split(":")[-1] def set_cr50_device(self, device): """Save the device used for the console""" @@ -183,38 +185,38 @@ class RMAOpen(object): try: ser = serial.Serial(self.device, timeout=1) except OSError: - logging.warning('Permission denied %s', self.device) - logging.warning('Try running cr50_rma_open with sudo') + logging.warning("Permission denied %s", self.device) + logging.warning("Try running cr50_rma_open with sudo") raise - write_cmd = cmd + '\n\n' - ser.write(write_cmd.encode('utf-8')) + write_cmd = cmd + "\n\n" + ser.write(write_cmd.encode("utf-8")) if nbytes: output = ser.read(nbytes) else: output = ser.readall() ser.close() - output = output.decode('utf-8').strip() if output else '' + output = output.decode("utf-8").strip() if output else "" # Return only the command output - split_cmd = cmd + '\r' + split_cmd = cmd + "\r" if cmd and split_cmd in output: - return ''.join(output.rpartition(split_cmd)[1::]).split('>')[0] + return "".join(output.rpartition(split_cmd)[1::]).split(">")[0] return output def device_is_running_with_servo_ccd(self): """Return True if the device is a servod ccd console""" # servod uses /dev/pts consoles. Non-servod uses /dev/ttyUSBX - if '/dev/pts' not in self.device: + if "/dev/pts" not in self.device: return False # If cr50 doesn't show rdd is connected, cr50 the device must not be # a ccd device - if 'Rdd: connected' not in self.send_cmd_get_output('ccdstate'): + if "Rdd: connected" not in self.send_cmd_get_output("ccdstate"): return False # Check if the servod is running with ccd. This requires the script # is run in the chroot, so run it last. - if 'ccd_cr50' not in self._dut_control('servo_type'): + if "ccd_cr50" not in self._dut_control("servo_type"): return False - logging.info('running through servod ccd') + logging.info("running through servod ccd") return True def get_rma_challenge(self): @@ -239,14 +241,14 @@ class RMAOpen(object): Returns: The RMA challenge with all whitespace removed. """ - output = self.send_cmd_get_output('rma_auth').strip() - logging.info('rma_auth output:\n%s', output) + output = self.send_cmd_get_output("rma_auth").strip() + logging.info("rma_auth output:\n%s", output) # Extract the challenge from the console output - if 'generated challenge:' in output: - return output.split('generated challenge:')[-1].strip() - challenge = ''.join(re.findall(r' \S{5}' * 4, output)) + if "generated challenge:" in output: + return output.split("generated challenge:")[-1].strip() + challenge = "".join(re.findall(r" \S{5}" * 4, output)) # Remove all whitespace - return re.sub(r'\s', '', challenge) + return re.sub(r"\s", "", challenge) def generate_challenge_url(self, hwid): """Get the rma_auth challenge @@ -257,12 +259,14 @@ class RMAOpen(object): challenge = self.get_rma_challenge() self.print_platform_info() - logging.info('CHALLENGE: %s', challenge) - logging.info('HWID: %s', hwid) + logging.info("CHALLENGE: %s", challenge) + logging.info("HWID: %s", hwid) url = URL % (challenge, hwid) - logging.info('GOTO:\n %s', url) - logging.info('If the server fails to debug the challenge make sure the ' - 'RLZ is allowlisted') + logging.info("GOTO:\n %s", url) + logging.info( + "If the server fails to debug the challenge make sure the " + "RLZ is allowlisted" + ) def try_authcode(self, authcode): """Try opening cr50 with the authcode @@ -272,48 +276,48 @@ class RMAOpen(object): """ # rma_auth may cause the system to reboot. Don't wait to read all that # output. Read the first 300 bytes and call it a day. - output = self.send_cmd_get_output('rma_auth ' + authcode, nbytes=300) - logging.info('CR50 RESPONSE: %s', output) - logging.info('waiting for cr50 reboot') + output = self.send_cmd_get_output("rma_auth " + authcode, nbytes=300) + logging.info("CR50 RESPONSE: %s", output) + logging.info("waiting for cr50 reboot") # Cr50 may be rebooting. Wait a bit time.sleep(5) if self.using_ccd: # After reboot, reset the ccd endpoints - self._dut_control('power_state:ccd_reset') + self._dut_control("power_state:ccd_reset") # Update the ccd state after the authcode attempt self.update_ccd_state() - authcode_match = 'process_response: success!' in output + authcode_match = "process_response: success!" in output if not self.check(CCD_IS_UNRESTRICTED): if not authcode_match: logging.warning(DEBUG_AUTHCODE_MISMATCH) - message = 'Authcode mismatch. Check args and url' + message = "Authcode mismatch. Check args and url" else: - message = 'Could not set all capability privileges to Always' + message = "Could not set all capability privileges to Always" raise ValueError(message) def wp_is_force_disabled(self): """Returns True if write protect is forced disabled""" - output = self.send_cmd_get_output('wp') - wp_state = output.split('Flash WP:', 1)[-1].split('\n', 1)[0].strip() - logging.info('wp: %s', wp_state) - return wp_state == 'forced disabled' + output = self.send_cmd_get_output("wp") + wp_state = output.split("Flash WP:", 1)[-1].split("\n", 1)[0].strip() + logging.info("wp: %s", wp_state) + return wp_state == "forced disabled" def testlab_is_enabled(self): """Returns True if testlab mode is enabled""" - output = self.send_cmd_get_output('ccd testlab') - testlab_state = output.split('mode')[-1].strip().lower() - logging.info('testlab: %s', testlab_state) - return testlab_state == 'enabled' + output = self.send_cmd_get_output("ccd testlab") + testlab_state = output.split("mode")[-1].strip().lower() + logging.info("testlab: %s", testlab_state) + return testlab_state == "enabled" def ccd_is_restricted(self): """Returns True if any of the capabilities are still restricted""" - output = self.send_cmd_get_output('ccd') - if 'Capabilities' not in output: - raise ValueError('Could not get ccd output') - logging.debug('CURRENT CCD SETTINGS:\n%s', output) - restricted = 'IfOpened' in output or 'IfUnlocked' in output - logging.info('ccd: %srestricted', '' if restricted else 'Un') + output = self.send_cmd_get_output("ccd") + if "Capabilities" not in output: + raise ValueError("Could not get ccd output") + logging.debug("CURRENT CCD SETTINGS:\n%s", output) + restricted = "IfOpened" in output or "IfUnlocked" in output + logging.info("ccd: %srestricted", "" if restricted else "Un") return restricted def update_ccd_state(self): @@ -339,9 +343,10 @@ class RMAOpen(object): def _capabilities_allow_open_from_console(self): """Return True if ccd open is Always allowed from usb""" - output = self.send_cmd_get_output('ccd') - return (re.search('OpenNoDevMode.*Always', output) and - re.search('OpenFromUSB.*Always', output)) + output = self.send_cmd_get_output("ccd") + return re.search("OpenNoDevMode.*Always", output) and re.search( + "OpenFromUSB.*Always", output + ) def _requires_dev_mode_open(self): """Return True if the image requires dev mode to open""" @@ -354,78 +359,81 @@ class RMAOpen(object): def _run_on_dut(self, command): """Run the command on the DUT.""" - return subprocess.check_output(['ssh', self.ip, command], - encoding='utf-8') + return subprocess.check_output(["ssh", self.ip, command], encoding="utf-8") def _open_in_dev_mode(self): """Open Cr50 when it's in dev mode""" - output = self.send_cmd_get_output('ccd') + output = self.send_cmd_get_output("ccd") # If the device is already open, nothing needs to be done. - if 'State: Open' not in output: + if "State: Open" not in output: # Verify the device is in devmode before trying to run open. - if 'dev_mode' not in output: - logging.warning('Enter dev mode to open ccd or update to %s', - TESTLAB_PROD) - raise ValueError('DUT not in dev mode') + if "dev_mode" not in output: + logging.warning( + "Enter dev mode to open ccd or update to %s", TESTLAB_PROD + ) + raise ValueError("DUT not in dev mode") if not self.ip: - logging.warning("If your DUT doesn't have ssh support, run " - "'gsctool -a -o' from the AP") - raise ValueError('Cannot run ccd open without dut ip') - self._run_on_dut('gsctool -a -o') + logging.warning( + "If your DUT doesn't have ssh support, run " + "'gsctool -a -o' from the AP" + ) + raise ValueError("Cannot run ccd open without dut ip") + self._run_on_dut("gsctool -a -o") # Wait >1 second for cr50 to update ccd state time.sleep(3) - output = self.send_cmd_get_output('ccd') - if 'State: Open' not in output: - raise ValueError('Could not open cr50') - logging.info('ccd is open') + output = self.send_cmd_get_output("ccd") + if "State: Open" not in output: + raise ValueError("Could not open cr50") + logging.info("ccd is open") def enable_testlab(self): """Disable write protect""" if not self._has_testlab_support(): - logging.warning('Testlab mode is not supported in prod iamges') + logging.warning("Testlab mode is not supported in prod iamges") return # Some cr50 images need to be in dev mode before they can be opened. if self._requires_dev_mode_open(): self._open_in_dev_mode() else: - self.send_cmd_get_output('ccd open') - logging.info('Enabling testlab mode reqires pressing the power button.') - logging.info('Once the process starts keep tapping the power button ' - 'for 10 seconds.') + self.send_cmd_get_output("ccd open") + logging.info("Enabling testlab mode reqires pressing the power button.") + logging.info( + "Once the process starts keep tapping the power button " "for 10 seconds." + ) input("Press Enter when you're ready to start...") end_time = time.time() + 15 ser = serial.Serial(self.device, timeout=1) - printed_lines = '' - output = '' + printed_lines = "" + output = "" # start ccd testlab enable - ser.write(self.ENABLE_TESTLAB_CMD.encode('utf-8')) - logging.info('start pressing the power button\n\n') + ser.write(self.ENABLE_TESTLAB_CMD.encode("utf-8")) + logging.info("start pressing the power button\n\n") # Print all of the cr50 output as we get it, so the user will have more # information about pressing the power button. Tapping the power button # a couple of times should do it, but this will give us more confidence # the process is still running/worked. try: while time.time() < end_time: - output += ser.read(100).decode('utf-8') - full_lines = output.rsplit('\n', 1)[0] + output += ser.read(100).decode("utf-8") + full_lines = output.rsplit("\n", 1)[0] new_lines = full_lines if printed_lines: new_lines = full_lines.split(printed_lines, 1)[-1].strip() - logging.info('\n%s', new_lines) + logging.info("\n%s", new_lines) printed_lines = full_lines # Make sure the process hasn't ended. If it has, print the last # of the output and exit. new_lines = output.split(printed_lines, 1)[-1] - if 'CCD test lab mode enabled' in output: + if "CCD test lab mode enabled" in output: # print the last of the ou logging.info(new_lines) break - elif 'Physical presence check timeout' in output: + elif "Physical presence check timeout" in output: logging.info(new_lines) - logging.warning('Did not detect power button press in time') - raise ValueError('Could not enable testlab mode try again') + logging.warning("Did not detect power button press in time") + raise ValueError("Could not enable testlab mode try again") finally: ser.close() # Wait for the ccd hook to update things @@ -433,44 +441,48 @@ class RMAOpen(object): # Update the state after attempting to disable write protect self.update_ccd_state() if not self.check(TESTLAB_IS_ENABLED): - raise ValueError('Could not enable testlab mode try again') + raise ValueError("Could not enable testlab mode try again") def wp_disable(self): """Disable write protect""" - logging.info('Disabling write protect') - self.send_cmd_get_output('wp disable') + logging.info("Disabling write protect") + self.send_cmd_get_output("wp disable") # Update the state after attempting to disable write protect self.update_ccd_state() if not self.check(WP_IS_DISABLED): - raise ValueError('Could not disable write protect') + raise ValueError("Could not disable write protect") def check_version(self): """Make sure cr50 is running a version that supports RMA Open""" - output = self.send_cmd_get_output('version') + output = self.send_cmd_get_output("version") if not output.strip(): logging.warning(DEBUG_DEVICE, self.device) - raise ValueError('Could not communicate with %s' % self.device) + raise ValueError("Could not communicate with %s" % self.device) - version = re.search(r'RW.*\* ([\d\.]+)/', output).group(1) - logging.info('Running Cr50 Version: %s', version) - self.running_ver_fields = [int(field) for field in version.split('.')] + version = re.search(r"RW.*\* ([\d\.]+)/", output).group(1) + logging.info("Running Cr50 Version: %s", version) + self.running_ver_fields = [int(field) for field in version.split(".")] # prePVT images have even major versions. Prod have odd self.is_prepvt = self.running_ver_fields[1] % 2 == 0 rma_support = RMA_SUPPORT_PREPVT if self.is_prepvt else RMA_SUPPORT_PROD - logging.info('%s RMA support added in: %s', - 'prePVT' if self.is_prepvt else 'prod', rma_support) + logging.info( + "%s RMA support added in: %s", + "prePVT" if self.is_prepvt else "prod", + rma_support, + ) if not self.is_prepvt and self._running_version_is_older(TESTLAB_PROD): - raise ValueError('Update cr50. No testlab support in old prod ' - 'images.') + raise ValueError("Update cr50. No testlab support in old prod " "images.") if self._running_version_is_older(rma_support): - raise ValueError('%s does not have RMA support. Update to at ' - 'least %s' % (version, rma_support)) + raise ValueError( + "%s does not have RMA support. Update to at " + "least %s" % (version, rma_support) + ) def _running_version_is_older(self, target_ver): """Returns True if running version is older than target_ver.""" - target_ver_fields = [int(field) for field in target_ver.split('.')] + target_ver_fields = [int(field) for field in target_ver.split(".")] for i, field in enumerate(self.running_ver_fields): if field > int(target_ver_fields[i]): return False @@ -486,11 +498,11 @@ class RMAOpen(object): is no output or sysinfo doesn't contain the devid. """ self.set_cr50_device(device) - sysinfo = self.send_cmd_get_output('sysinfo') + sysinfo = self.send_cmd_get_output("sysinfo") # Make sure there is some output, and it shows it's from Cr50 - if not sysinfo or 'cr50' not in sysinfo: + if not sysinfo or "cr50" not in sysinfo: return False - logging.debug('Sysinfo output: %s', sysinfo) + logging.debug("Sysinfo output: %s", sysinfo) # The cr50 device id should be in the sysinfo output, if we found # the right console. Make sure it is return devid in sysinfo @@ -508,104 +520,137 @@ class RMAOpen(object): ValueError if the console can't be found with the given serialname """ usb_serial = self.find_cr50_usb(usb_serial) - logging.info('SERIALNAME: %s', usb_serial) - devid = '0x' + ' 0x'.join(usb_serial.lower().split('-')) - logging.info('DEVID: %s', devid) + logging.info("SERIALNAME: %s", usb_serial) + devid = "0x" + " 0x".join(usb_serial.lower().split("-")) + logging.info("DEVID: %s", devid) # Get all the usb devices - devices = glob.glob('/dev/ttyUSB*') + devices = glob.glob("/dev/ttyUSB*") # Typically Cr50 has the lowest number. Sort the devices, so we're more # likely to try the cr50 console first. devices.sort() # Find the one that is the cr50 console for device in devices: - logging.info('testing %s', device) + logging.info("testing %s", device) if self.device_matches_devid(devid, device): - logging.info('found device: %s', device) + logging.info("found device: %s", device) return logging.warning(DEBUG_CONNECTION) - raise ValueError('Found USB device, but could not communicate with ' - 'cr50 console') + raise ValueError( + "Found USB device, but could not communicate with " "cr50 console" + ) def print_platform_info(self): """Print the cr50 BID RLZ code""" - bid_output = self.send_cmd_get_output('bid') - bid = re.search(r'Board ID: (\S+?)[:,]', bid_output).group(1) + bid_output = self.send_cmd_get_output("bid") + bid = re.search(r"Board ID: (\S+?)[:,]", bid_output).group(1) if bid == ERASED_BID: logging.warning(DEBUG_ERASED_BOARD_ID) - raise ValueError('Cannot run RMA Open when board id is erased') + raise ValueError("Cannot run RMA Open when board id is erased") bid = int(bid, 16) - chrs = [chr((bid >> (8 * i)) & 0xff) for i in range(4)] - logging.info('RLZ: %s', ''.join(chrs[::-1])) + chrs = [chr((bid >> (8 * i)) & 0xFF) for i in range(4)] + logging.info("RLZ: %s", "".join(chrs[::-1])) @staticmethod def find_cr50_usb(usb_serial): """Make sure the Cr50 USB device exists""" try: - output = subprocess.check_output(CR50_LSUSB_CMD, encoding='utf-8') + output = subprocess.check_output(CR50_LSUSB_CMD, encoding="utf-8") except: logging.warning(DEBUG_MISSING_USB) - raise ValueError('Could not find Cr50 USB device') - serialnames = re.findall(r'iSerial +\d+ (\S+)\s', output) + raise ValueError("Could not find Cr50 USB device") + serialnames = re.findall(r"iSerial +\d+ (\S+)\s", output) if usb_serial: if usb_serial not in serialnames: logging.warning(DEBUG_SERIALNAME) raise ValueError('Could not find usb device "%s"' % usb_serial) return usb_serial if len(serialnames) > 1: - logging.info('Found Cr50 device serialnames %s', - ', '.join(serialnames)) + logging.info("Found Cr50 device serialnames %s", ", ".join(serialnames)) logging.warning(DEBUG_TOO_MANY_USB_DEVICES) - raise ValueError('Too many cr50 usb devices') + raise ValueError("Too many cr50 usb devices") return serialnames[0] def print_dut_state(self): """Print CCD RMA and testlab mode state.""" if not self.check(CCD_IS_UNRESTRICTED): - logging.info('CCD is still restricted.') - logging.info('Run cr50_rma_open.py -g -i $HWID to generate a url') - logging.info('Run cr50_rma_open.py -a $AUTHCODE to open cr50 with ' - 'an authcode') + logging.info("CCD is still restricted.") + logging.info("Run cr50_rma_open.py -g -i $HWID to generate a url") + logging.info( + "Run cr50_rma_open.py -a $AUTHCODE to open cr50 with " "an authcode" + ) elif not self.check(WP_IS_DISABLED): - logging.info('WP is still enabled.') - logging.info('Run cr50_rma_open.py -w to disable write protect') + logging.info("WP is still enabled.") + logging.info("Run cr50_rma_open.py -w to disable write protect") if self.check(RMA_OPENED): - logging.info('RMA Open complete') + logging.info("RMA Open complete") if not self.check(TESTLAB_IS_ENABLED) and self.is_prepvt: - logging.info('testlab mode is disabled.') - logging.info('If you are prepping a device for the testlab, you ' - 'should enable testlab mode.') - logging.info('Run cr50_rma_open.py -t to enable testlab mode') + logging.info("testlab mode is disabled.") + logging.info( + "If you are prepping a device for the testlab, you " + "should enable testlab mode." + ) + logging.info("Run cr50_rma_open.py -t to enable testlab mode") def parse_args(argv): """Get cr50_rma_open args.""" parser = argparse.ArgumentParser( - description=__doc__, formatter_class=argparse.RawTextHelpFormatter) - parser.add_argument('-g', '--generate_challenge', action='store_true', - help='Generate Cr50 challenge. Must be used with -i') - parser.add_argument('-t', '--enable_testlab', action='store_true', - help='enable testlab mode') - parser.add_argument('-w', '--wp_disable', action='store_true', - help='Disable write protect') - parser.add_argument('-c', '--check_connection', action='store_true', - help='Check cr50 console connection works') - parser.add_argument('-s', '--serialname', type=str, default='', - help='The cr50 usb serialname') - parser.add_argument('-D', '--debug', action='store_true', - help='print debug messages') - parser.add_argument('-d', '--device', type=str, default='', - help='cr50 console device ex /dev/ttyUSB0') - parser.add_argument('-i', '--hwid', type=str, default='', - help='The board hwid. Needed to generate a challenge') - parser.add_argument('-a', '--authcode', type=str, default='', - help='The authcode string from the challenge url') - parser.add_argument('-P', '--servo_port', type=str, default='', - help='the servo port') - parser.add_argument('-I', '--ip', type=str, default='', - help='The DUT IP. Necessary to do ccd open') + description=__doc__, formatter_class=argparse.RawTextHelpFormatter + ) + parser.add_argument( + "-g", + "--generate_challenge", + action="store_true", + help="Generate Cr50 challenge. Must be used with -i", + ) + parser.add_argument( + "-t", "--enable_testlab", action="store_true", help="enable testlab mode" + ) + parser.add_argument( + "-w", "--wp_disable", action="store_true", help="Disable write protect" + ) + parser.add_argument( + "-c", + "--check_connection", + action="store_true", + help="Check cr50 console connection works", + ) + parser.add_argument( + "-s", "--serialname", type=str, default="", help="The cr50 usb serialname" + ) + parser.add_argument( + "-D", "--debug", action="store_true", help="print debug messages" + ) + parser.add_argument( + "-d", + "--device", + type=str, + default="", + help="cr50 console device ex /dev/ttyUSB0", + ) + parser.add_argument( + "-i", + "--hwid", + type=str, + default="", + help="The board hwid. Needed to generate a challenge", + ) + parser.add_argument( + "-a", + "--authcode", + type=str, + default="", + help="The authcode string from the challenge url", + ) + parser.add_argument( + "-P", "--servo_port", type=str, default="", help="the servo port" + ) + parser.add_argument( + "-I", "--ip", type=str, default="", help="The DUT IP. Necessary to do ccd open" + ) return parser.parse_args(argv) @@ -614,52 +659,53 @@ def main(argv): opts = parse_args(argv) loglevel = logging.INFO - log_format = '%(levelname)7s' + log_format = "%(levelname)7s" if opts.debug: loglevel = logging.DEBUG - log_format += ' - %(lineno)3d:%(funcName)-15s' - log_format += ' - %(message)s' + log_format += " - %(lineno)3d:%(funcName)-15s" + log_format += " - %(message)s" logging.basicConfig(level=loglevel, format=log_format) tried_authcode = False - logging.info('Running cr50_rma_open version %s', SCRIPT_VERSION) + logging.info("Running cr50_rma_open version %s", SCRIPT_VERSION) - cr50_rma_open = RMAOpen(opts.device, opts.serialname, opts.servo_port, - opts.ip) + cr50_rma_open = RMAOpen(opts.device, opts.serialname, opts.servo_port, opts.ip) if opts.check_connection: sys.exit(0) if not cr50_rma_open.check(CCD_IS_UNRESTRICTED): if opts.generate_challenge: if not opts.hwid: - logging.warning('--hwid necessary to generate challenge url') + logging.warning("--hwid necessary to generate challenge url") sys.exit(0) cr50_rma_open.generate_challenge_url(opts.hwid) sys.exit(0) elif opts.authcode: - logging.info('Using authcode: %s', opts.authcode) + logging.info("Using authcode: %s", opts.authcode) cr50_rma_open.try_authcode(opts.authcode) tried_authcode = True - if not cr50_rma_open.check(WP_IS_DISABLED) and (tried_authcode or - opts.wp_disable): + if not cr50_rma_open.check(WP_IS_DISABLED) and (tried_authcode or opts.wp_disable): if not cr50_rma_open.check(CCD_IS_UNRESTRICTED): - raise ValueError("Can't disable write protect unless ccd is " - "open. Run through the rma open process first") + raise ValueError( + "Can't disable write protect unless ccd is " + "open. Run through the rma open process first" + ) if tried_authcode: - logging.warning('RMA Open did not disable write protect. File a ' - 'bug') - logging.warning('Trying to disable it manually') + logging.warning("RMA Open did not disable write protect. File a " "bug") + logging.warning("Trying to disable it manually") cr50_rma_open.wp_disable() if not cr50_rma_open.check(TESTLAB_IS_ENABLED) and opts.enable_testlab: if not cr50_rma_open.check(CCD_IS_UNRESTRICTED): - raise ValueError("Can't enable testlab mode unless ccd is open." - "Run through the rma open process first") + raise ValueError( + "Can't enable testlab mode unless ccd is open." + "Run through the rma open process first" + ) cr50_rma_open.enable_testlab() cr50_rma_open.print_dut_state() -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/extra/stack_analyzer/stack_analyzer.py b/extra/stack_analyzer/stack_analyzer.py index 77d16d5450..17b2651972 100755 --- a/extra/stack_analyzer/stack_analyzer.py +++ b/extra/stack_analyzer/stack_analyzer.py @@ -25,1848 +25,1992 @@ import ctypes import os import re import subprocess -import yaml +import yaml -SECTION_RO = 'RO' -SECTION_RW = 'RW' +SECTION_RO = "RO" +SECTION_RW = "RW" # Default size of extra stack frame needed by exception context switch. # This value is for cortex-m with FPU enabled. DEFAULT_EXCEPTION_FRAME_SIZE = 224 class StackAnalyzerError(Exception): - """Exception class for stack analyzer utility.""" + """Exception class for stack analyzer utility.""" class TaskInfo(ctypes.Structure): - """Taskinfo ctypes structure. + """Taskinfo ctypes structure. - The structure definition is corresponding to the "struct taskinfo" - in "util/export_taskinfo.so.c". - """ - _fields_ = [('name', ctypes.c_char_p), - ('routine', ctypes.c_char_p), - ('stack_size', ctypes.c_uint32)] + The structure definition is corresponding to the "struct taskinfo" + in "util/export_taskinfo.so.c". + """ + _fields_ = [ + ("name", ctypes.c_char_p), + ("routine", ctypes.c_char_p), + ("stack_size", ctypes.c_uint32), + ] -class Task(object): - """Task information. - Attributes: - name: Task name. - routine_name: Routine function name. - stack_max_size: Max stack size. - routine_address: Resolved routine address. None if it hasn't been resolved. - """ - - def __init__(self, name, routine_name, stack_max_size, routine_address=None): - """Constructor. +class Task(object): + """Task information. - Args: + Attributes: name: Task name. routine_name: Routine function name. stack_max_size: Max stack size. - routine_address: Resolved routine address. + routine_address: Resolved routine address. None if it hasn't been resolved. """ - self.name = name - self.routine_name = routine_name - self.stack_max_size = stack_max_size - self.routine_address = routine_address - def __eq__(self, other): - """Task equality. + def __init__(self, name, routine_name, stack_max_size, routine_address=None): + """Constructor. - Args: - other: The compared object. + Args: + name: Task name. + routine_name: Routine function name. + stack_max_size: Max stack size. + routine_address: Resolved routine address. + """ + self.name = name + self.routine_name = routine_name + self.stack_max_size = stack_max_size + self.routine_address = routine_address - Returns: - True if equal, False if not. - """ - if not isinstance(other, Task): - return False + def __eq__(self, other): + """Task equality. - return (self.name == other.name and - self.routine_name == other.routine_name and - self.stack_max_size == other.stack_max_size and - self.routine_address == other.routine_address) + Args: + other: The compared object. + Returns: + True if equal, False if not. + """ + if not isinstance(other, Task): + return False -class Symbol(object): - """Symbol information. + return ( + self.name == other.name + and self.routine_name == other.routine_name + and self.stack_max_size == other.stack_max_size + and self.routine_address == other.routine_address + ) - Attributes: - address: Symbol address. - symtype: Symbol type, 'O' (data, object) or 'F' (function). - size: Symbol size. - name: Symbol name. - """ - def __init__(self, address, symtype, size, name): - """Constructor. +class Symbol(object): + """Symbol information. - Args: + Attributes: address: Symbol address. - symtype: Symbol type. + symtype: Symbol type, 'O' (data, object) or 'F' (function). size: Symbol size. name: Symbol name. """ - assert symtype in ['O', 'F'] - self.address = address - self.symtype = symtype - self.size = size - self.name = name - def __eq__(self, other): - """Symbol equality. - - Args: - other: The compared object. - - Returns: - True if equal, False if not. - """ - if not isinstance(other, Symbol): - return False - - return (self.address == other.address and - self.symtype == other.symtype and - self.size == other.size and - self.name == other.name) + def __init__(self, address, symtype, size, name): + """Constructor. + + Args: + address: Symbol address. + symtype: Symbol type. + size: Symbol size. + name: Symbol name. + """ + assert symtype in ["O", "F"] + self.address = address + self.symtype = symtype + self.size = size + self.name = name + + def __eq__(self, other): + """Symbol equality. + + Args: + other: The compared object. + + Returns: + True if equal, False if not. + """ + if not isinstance(other, Symbol): + return False + + return ( + self.address == other.address + and self.symtype == other.symtype + and self.size == other.size + and self.name == other.name + ) class Callsite(object): - """Function callsite. - - Attributes: - address: Address of callsite location. None if it is unknown. - target: Callee address. None if it is unknown. - is_tail: A bool indicates that it is a tailing call. - callee: Resolved callee function. None if it hasn't been resolved. - """ - - def __init__(self, address, target, is_tail, callee=None): - """Constructor. + """Function callsite. - Args: + Attributes: address: Address of callsite location. None if it is unknown. target: Callee address. None if it is unknown. - is_tail: A bool indicates that it is a tailing call. (function jump to - another function without restoring the stack frame) - callee: Resolved callee function. + is_tail: A bool indicates that it is a tailing call. + callee: Resolved callee function. None if it hasn't been resolved. """ - # It makes no sense that both address and target are unknown. - assert not (address is None and target is None) - self.address = address - self.target = target - self.is_tail = is_tail - self.callee = callee - - def __eq__(self, other): - """Callsite equality. - - Args: - other: The compared object. - Returns: - True if equal, False if not. - """ - if not isinstance(other, Callsite): - return False - - if not (self.address == other.address and - self.target == other.target and - self.is_tail == other.is_tail): - return False - - if self.callee is None: - return other.callee is None - elif other.callee is None: - return False - - # Assume the addresses of functions are unique. - return self.callee.address == other.callee.address + def __init__(self, address, target, is_tail, callee=None): + """Constructor. + + Args: + address: Address of callsite location. None if it is unknown. + target: Callee address. None if it is unknown. + is_tail: A bool indicates that it is a tailing call. (function jump to + another function without restoring the stack frame) + callee: Resolved callee function. + """ + # It makes no sense that both address and target are unknown. + assert not (address is None and target is None) + self.address = address + self.target = target + self.is_tail = is_tail + self.callee = callee + + def __eq__(self, other): + """Callsite equality. + + Args: + other: The compared object. + + Returns: + True if equal, False if not. + """ + if not isinstance(other, Callsite): + return False + + if not ( + self.address == other.address + and self.target == other.target + and self.is_tail == other.is_tail + ): + return False + + if self.callee is None: + return other.callee is None + elif other.callee is None: + return False + + # Assume the addresses of functions are unique. + return self.callee.address == other.callee.address class Function(object): - """Function. - - Attributes: - address: Address of function. - name: Name of function from its symbol. - stack_frame: Size of stack frame. - callsites: Callsite list. - stack_max_usage: Max stack usage. None if it hasn't been analyzed. - stack_max_path: Max stack usage path. None if it hasn't been analyzed. - """ + """Function. - def __init__(self, address, name, stack_frame, callsites): - """Constructor. - - Args: + Attributes: address: Address of function. name: Name of function from its symbol. stack_frame: Size of stack frame. callsites: Callsite list. + stack_max_usage: Max stack usage. None if it hasn't been analyzed. + stack_max_path: Max stack usage path. None if it hasn't been analyzed. """ - self.address = address - self.name = name - self.stack_frame = stack_frame - self.callsites = callsites - self.stack_max_usage = None - self.stack_max_path = None - - def __eq__(self, other): - """Function equality. - - Args: - other: The compared object. - - Returns: - True if equal, False if not. - """ - if not isinstance(other, Function): - return False - - if not (self.address == other.address and - self.name == other.name and - self.stack_frame == other.stack_frame and - self.callsites == other.callsites and - self.stack_max_usage == other.stack_max_usage): - return False - if self.stack_max_path is None: - return other.stack_max_path is None - elif other.stack_max_path is None: - return False + def __init__(self, address, name, stack_frame, callsites): + """Constructor. + + Args: + address: Address of function. + name: Name of function from its symbol. + stack_frame: Size of stack frame. + callsites: Callsite list. + """ + self.address = address + self.name = name + self.stack_frame = stack_frame + self.callsites = callsites + self.stack_max_usage = None + self.stack_max_path = None + + def __eq__(self, other): + """Function equality. + + Args: + other: The compared object. + + Returns: + True if equal, False if not. + """ + if not isinstance(other, Function): + return False + + if not ( + self.address == other.address + and self.name == other.name + and self.stack_frame == other.stack_frame + and self.callsites == other.callsites + and self.stack_max_usage == other.stack_max_usage + ): + return False + + if self.stack_max_path is None: + return other.stack_max_path is None + elif other.stack_max_path is None: + return False + + if len(self.stack_max_path) != len(other.stack_max_path): + return False + + for self_func, other_func in zip(self.stack_max_path, other.stack_max_path): + # Assume the addresses of functions are unique. + if self_func.address != other_func.address: + return False + + return True + + def __hash__(self): + return id(self) - if len(self.stack_max_path) != len(other.stack_max_path): - return False - - for self_func, other_func in zip(self.stack_max_path, other.stack_max_path): - # Assume the addresses of functions are unique. - if self_func.address != other_func.address: - return False - - return True - - def __hash__(self): - return id(self) class AndesAnalyzer(object): - """Disassembly analyzer for Andes architecture. - - Public Methods: - AnalyzeFunction: Analyze stack frame and callsites of the function. - """ - - GENERAL_PURPOSE_REGISTER_SIZE = 4 - - # Possible condition code suffixes. - CONDITION_CODES = [ 'eq', 'eqz', 'gez', 'gtz', 'lez', 'ltz', 'ne', 'nez', - 'eqc', 'nec', 'nezs', 'nes', 'eqs'] - CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES)) - - IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>' - # Branch instructions. - JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$' \ - .format(CONDITION_CODES_RE)) - # Call instructions. - CALL_OPCODE_RE = re.compile \ - (r'^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$') - CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE)) - # Ignore lp register because it's for return. - INDIRECT_CALL_OPERAND_RE = re.compile \ - (r'^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$') - # TODO: Handle other kinds of store instructions. - PUSH_OPCODE_RE = re.compile(r'^push(\d{1,})$') - PUSH_OPERAND_RE = re.compile(r'^\$r\d{1,}, \#\d{1,} \! \{([^\]]+)\}') - SMW_OPCODE_RE = re.compile(r'^smw(\.\w\w|\.\w\w\w)$') - SMW_OPERAND_RE = re.compile(r'^(\$r\d{1,}|\$\wp), \[\$\wp\], ' - r'(\$r\d{1,}|\$\wp), \#\d\w\d \! \{([^\]]+)\}') - OPERANDGROUP_RE = re.compile(r'^\$r\d{1,}\~\$r\d{1,}') - - LWI_OPCODE_RE = re.compile(r'^lwi(\.\w\w)$') - LWI_PC_OPERAND_RE = re.compile(r'^\$pc, \[([^\]]+)\]') - # Example: "34280: 3f c8 0f ec addi.gp $fp, #0xfec" - # Assume there is always a "\t" after the hex data. - DISASM_REGEX_RE = re.compile(r'^(?P
[0-9A-Fa-f]+):\s+' - r'(?P[0-9A-Fa-f ]+)' - r'\t\s*(?P\S+)(\s+(?P[^;]*))?') - - def ParseInstruction(self, line, function_end): - """Parse the line of instruction. + """Disassembly analyzer for Andes architecture. - Args: - line: Text of disassembly. - function_end: End address of the current function. None if unknown. - - Returns: - (address, words, opcode, operand_text): The instruction address, words, - opcode, and the text of operands. - None if it isn't an instruction line. + Public Methods: + AnalyzeFunction: Analyze stack frame and callsites of the function. """ - result = self.DISASM_REGEX_RE.match(line) - if result is None: - return None - - address = int(result.group('address'), 16) - # Check if it's out of bound. - if function_end is not None and address >= function_end: - return None - - opcode = result.group('opcode').strip() - operand_text = result.group('operand') - words = result.group('words') - if operand_text is None: - operand_text = '' - else: - operand_text = operand_text.strip() - - return (address, words, opcode, operand_text) - - def AnalyzeFunction(self, function_symbol, instructions): - - stack_frame = 0 - callsites = [] - for address, words, opcode, operand_text in instructions: - is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None - is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None - - if is_jump_opcode or is_call_opcode: - is_tail = is_jump_opcode - - result = self.CALL_OPERAND_RE.match(operand_text) + GENERAL_PURPOSE_REGISTER_SIZE = 4 + + # Possible condition code suffixes. + CONDITION_CODES = [ + "eq", + "eqz", + "gez", + "gtz", + "lez", + "ltz", + "ne", + "nez", + "eqc", + "nec", + "nezs", + "nes", + "eqs", + ] + CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES)) + + IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>" + # Branch instructions. + JUMP_OPCODE_RE = re.compile( + r"^(b{0}|j|jr|jr.|jrnez)(\d?|\d\d)$".format(CONDITION_CODES_RE) + ) + # Call instructions. + CALL_OPCODE_RE = re.compile(r"^(jal|jral|jral.|jralnez|beqzal|bltzal|bgezal)(\d)?$") + CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE)) + # Ignore lp register because it's for return. + INDIRECT_CALL_OPERAND_RE = re.compile(r"^\$r\d{1,}$|\$fp$|\$gp$|\$ta$|\$sp$|\$pc$") + # TODO: Handle other kinds of store instructions. + PUSH_OPCODE_RE = re.compile(r"^push(\d{1,})$") + PUSH_OPERAND_RE = re.compile(r"^\$r\d{1,}, \#\d{1,} \! \{([^\]]+)\}") + SMW_OPCODE_RE = re.compile(r"^smw(\.\w\w|\.\w\w\w)$") + SMW_OPERAND_RE = re.compile( + r"^(\$r\d{1,}|\$\wp), \[\$\wp\], " + r"(\$r\d{1,}|\$\wp), \#\d\w\d \! \{([^\]]+)\}" + ) + OPERANDGROUP_RE = re.compile(r"^\$r\d{1,}\~\$r\d{1,}") + + LWI_OPCODE_RE = re.compile(r"^lwi(\.\w\w)$") + LWI_PC_OPERAND_RE = re.compile(r"^\$pc, \[([^\]]+)\]") + # Example: "34280: 3f c8 0f ec addi.gp $fp, #0xfec" + # Assume there is always a "\t" after the hex data. + DISASM_REGEX_RE = re.compile( + r"^(?P
[0-9A-Fa-f]+):\s+" + r"(?P[0-9A-Fa-f ]+)" + r"\t\s*(?P\S+)(\s+(?P[^;]*))?" + ) + + def ParseInstruction(self, line, function_end): + """Parse the line of instruction. + + Args: + line: Text of disassembly. + function_end: End address of the current function. None if unknown. + + Returns: + (address, words, opcode, operand_text): The instruction address, words, + opcode, and the text of operands. + None if it isn't an instruction line. + """ + result = self.DISASM_REGEX_RE.match(line) if result is None: - if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None): - # Found an indirect call. - callsites.append(Callsite(address, None, is_tail)) - + return None + + address = int(result.group("address"), 16) + # Check if it's out of bound. + if function_end is not None and address >= function_end: + return None + + opcode = result.group("opcode").strip() + operand_text = result.group("operand") + words = result.group("words") + if operand_text is None: + operand_text = "" else: - target_address = int(result.group(1), 16) - # Filter out the in-function target (branches and in-function calls, - # which are actually branches). - if not (function_symbol.size > 0 and - function_symbol.address < target_address < - (function_symbol.address + function_symbol.size)): - # Maybe it is a callsite. - callsites.append(Callsite(address, target_address, is_tail)) - - elif self.LWI_OPCODE_RE.match(opcode) is not None: - result = self.LWI_PC_OPERAND_RE.match(operand_text) - if result is not None: - # Ignore "lwi $pc, [$sp], xx" because it's usually a return. - if result.group(1) != '$sp': - # Found an indirect call. - callsites.append(Callsite(address, None, True)) - - elif self.PUSH_OPCODE_RE.match(opcode) is not None: - # Example: fc 20 push25 $r8, #0 ! {$r6~$r8, $fp, $gp, $lp} - if self.PUSH_OPERAND_RE.match(operand_text) is not None: - # capture fc 20 - imm5u = int(words.split(' ')[1], 16) - # sp = sp - (imm5u << 3) - imm8u = (imm5u<<3) & 0xff - stack_frame += imm8u - - result = self.PUSH_OPERAND_RE.match(operand_text) - operandgroup_text = result.group(1) - # capture $rx~$ry - if self.OPERANDGROUP_RE.match(operandgroup_text) is not None: - # capture number & transfer string to integer - oprandgrouphead = operandgroup_text.split(',')[0] - rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0]))) - ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1]))) - - stack_frame += ((len(operandgroup_text.split(','))+ry-rx) * - self.GENERAL_PURPOSE_REGISTER_SIZE) - else: - stack_frame += (len(operandgroup_text.split(',')) * - self.GENERAL_PURPOSE_REGISTER_SIZE) - - elif self.SMW_OPCODE_RE.match(opcode) is not None: - # Example: smw.adm $r6, [$sp], $r10, #0x2 ! {$r6~$r10, $lp} - if self.SMW_OPERAND_RE.match(operand_text) is not None: - result = self.SMW_OPERAND_RE.match(operand_text) - operandgroup_text = result.group(3) - # capture $rx~$ry - if self.OPERANDGROUP_RE.match(operandgroup_text) is not None: - # capture number & transfer string to integer - oprandgrouphead = operandgroup_text.split(',')[0] - rx=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[0]))) - ry=int(''.join(filter(str.isdigit, oprandgrouphead.split('~')[1]))) - - stack_frame += ((len(operandgroup_text.split(','))+ry-rx) * - self.GENERAL_PURPOSE_REGISTER_SIZE) - else: - stack_frame += (len(operandgroup_text.split(',')) * - self.GENERAL_PURPOSE_REGISTER_SIZE) - - return (stack_frame, callsites) - -class ArmAnalyzer(object): - """Disassembly analyzer for ARM architecture. - - Public Methods: - AnalyzeFunction: Analyze stack frame and callsites of the function. - """ - - GENERAL_PURPOSE_REGISTER_SIZE = 4 - - # Possible condition code suffixes. - CONDITION_CODES = ['', 'eq', 'ne', 'cs', 'hs', 'cc', 'lo', 'mi', 'pl', 'vs', - 'vc', 'hi', 'ls', 'ge', 'lt', 'gt', 'le'] - CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES)) - # Assume there is no function name containing ">". - IMM_ADDRESS_RE = r'([0-9A-Fa-f]+)\s+<([^>]+)>' - - # Fuzzy regular expressions for instruction and operand parsing. - # Branch instructions. - JUMP_OPCODE_RE = re.compile( - r'^(b{0}|bx{0})(\.\w)?$'.format(CONDITION_CODES_RE)) - # Call instructions. - CALL_OPCODE_RE = re.compile( - r'^(bl{0}|blx{0})(\.\w)?$'.format(CONDITION_CODES_RE)) - CALL_OPERAND_RE = re.compile(r'^{}$'.format(IMM_ADDRESS_RE)) - CBZ_CBNZ_OPCODE_RE = re.compile(r'^(cbz|cbnz)(\.\w)?$') - # Example: "r0, 1009bcbe " - CBZ_CBNZ_OPERAND_RE = re.compile(r'^[^,]+,\s+{}$'.format(IMM_ADDRESS_RE)) - # Ignore lr register because it's for return. - INDIRECT_CALL_OPERAND_RE = re.compile(r'^r\d+|sb|sl|fp|ip|sp|pc$') - # TODO(cheyuw): Handle conditional versions of following - # instructions. - # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc). - LDR_OPCODE_RE = re.compile(r'^ldr(\.\w)?$') - # Example: "pc, [sp], #4" - LDR_PC_OPERAND_RE = re.compile(r'^pc, \[([^\]]+)\]') - # TODO(cheyuw): Handle other kinds of stm instructions. - PUSH_OPCODE_RE = re.compile(r'^push$') - STM_OPCODE_RE = re.compile(r'^stmdb$') - # Stack subtraction instructions. - SUB_OPCODE_RE = re.compile(r'^sub(s|w)?(\.\w)?$') - SUB_OPERAND_RE = re.compile(r'^sp[^#]+#(\d+)') - # Example: "44d94: f893 0068 ldrb.w r0, [r3, #104] ; 0x68" - # Assume there is always a "\t" after the hex data. - DISASM_REGEX_RE = re.compile(r'^(?P
[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+' - r'\t\s*(?P\S+)(\s+(?P[^;]*))?') - - def ParseInstruction(self, line, function_end): - """Parse the line of instruction. + operand_text = operand_text.strip() + + return (address, words, opcode, operand_text) + + def AnalyzeFunction(self, function_symbol, instructions): + + stack_frame = 0 + callsites = [] + for address, words, opcode, operand_text in instructions: + is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None + is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None + + if is_jump_opcode or is_call_opcode: + is_tail = is_jump_opcode + + result = self.CALL_OPERAND_RE.match(operand_text) + + if result is None: + if self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None: + # Found an indirect call. + callsites.append(Callsite(address, None, is_tail)) + + else: + target_address = int(result.group(1), 16) + # Filter out the in-function target (branches and in-function calls, + # which are actually branches). + if not ( + function_symbol.size > 0 + and function_symbol.address + < target_address + < (function_symbol.address + function_symbol.size) + ): + # Maybe it is a callsite. + callsites.append(Callsite(address, target_address, is_tail)) + + elif self.LWI_OPCODE_RE.match(opcode) is not None: + result = self.LWI_PC_OPERAND_RE.match(operand_text) + if result is not None: + # Ignore "lwi $pc, [$sp], xx" because it's usually a return. + if result.group(1) != "$sp": + # Found an indirect call. + callsites.append(Callsite(address, None, True)) + + elif self.PUSH_OPCODE_RE.match(opcode) is not None: + # Example: fc 20 push25 $r8, #0 ! {$r6~$r8, $fp, $gp, $lp} + if self.PUSH_OPERAND_RE.match(operand_text) is not None: + # capture fc 20 + imm5u = int(words.split(" ")[1], 16) + # sp = sp - (imm5u << 3) + imm8u = (imm5u << 3) & 0xFF + stack_frame += imm8u + + result = self.PUSH_OPERAND_RE.match(operand_text) + operandgroup_text = result.group(1) + # capture $rx~$ry + if self.OPERANDGROUP_RE.match(operandgroup_text) is not None: + # capture number & transfer string to integer + oprandgrouphead = operandgroup_text.split(",")[0] + rx = int( + "".join(filter(str.isdigit, oprandgrouphead.split("~")[0])) + ) + ry = int( + "".join(filter(str.isdigit, oprandgrouphead.split("~")[1])) + ) + + stack_frame += ( + len(operandgroup_text.split(",")) + ry - rx + ) * self.GENERAL_PURPOSE_REGISTER_SIZE + else: + stack_frame += ( + len(operandgroup_text.split(",")) + * self.GENERAL_PURPOSE_REGISTER_SIZE + ) + + elif self.SMW_OPCODE_RE.match(opcode) is not None: + # Example: smw.adm $r6, [$sp], $r10, #0x2 ! {$r6~$r10, $lp} + if self.SMW_OPERAND_RE.match(operand_text) is not None: + result = self.SMW_OPERAND_RE.match(operand_text) + operandgroup_text = result.group(3) + # capture $rx~$ry + if self.OPERANDGROUP_RE.match(operandgroup_text) is not None: + # capture number & transfer string to integer + oprandgrouphead = operandgroup_text.split(",")[0] + rx = int( + "".join(filter(str.isdigit, oprandgrouphead.split("~")[0])) + ) + ry = int( + "".join(filter(str.isdigit, oprandgrouphead.split("~")[1])) + ) + + stack_frame += ( + len(operandgroup_text.split(",")) + ry - rx + ) * self.GENERAL_PURPOSE_REGISTER_SIZE + else: + stack_frame += ( + len(operandgroup_text.split(",")) + * self.GENERAL_PURPOSE_REGISTER_SIZE + ) + + return (stack_frame, callsites) - Args: - line: Text of disassembly. - function_end: End address of the current function. None if unknown. - Returns: - (address, opcode, operand_text): The instruction address, opcode, - and the text of operands. None if it - isn't an instruction line. - """ - result = self.DISASM_REGEX_RE.match(line) - if result is None: - return None - - address = int(result.group('address'), 16) - # Check if it's out of bound. - if function_end is not None and address >= function_end: - return None - - opcode = result.group('opcode').strip() - operand_text = result.group('operand') - if operand_text is None: - operand_text = '' - else: - operand_text = operand_text.strip() - - return (address, opcode, operand_text) - - def AnalyzeFunction(self, function_symbol, instructions): - """Analyze function, resolve the size of stack frame and callsites. - - Args: - function_symbol: Function symbol. - instructions: Instruction list. +class ArmAnalyzer(object): + """Disassembly analyzer for ARM architecture. - Returns: - (stack_frame, callsites): Size of stack frame, callsite list. + Public Methods: + AnalyzeFunction: Analyze stack frame and callsites of the function. """ - stack_frame = 0 - callsites = [] - for address, opcode, operand_text in instructions: - is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None - is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None - is_cbz_cbnz_opcode = self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None - if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode: - is_tail = is_jump_opcode or is_cbz_cbnz_opcode - - if is_cbz_cbnz_opcode: - result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text) - else: - result = self.CALL_OPERAND_RE.match(operand_text) + GENERAL_PURPOSE_REGISTER_SIZE = 4 + + # Possible condition code suffixes. + CONDITION_CODES = [ + "", + "eq", + "ne", + "cs", + "hs", + "cc", + "lo", + "mi", + "pl", + "vs", + "vc", + "hi", + "ls", + "ge", + "lt", + "gt", + "le", + ] + CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES)) + # Assume there is no function name containing ">". + IMM_ADDRESS_RE = r"([0-9A-Fa-f]+)\s+<([^>]+)>" + + # Fuzzy regular expressions for instruction and operand parsing. + # Branch instructions. + JUMP_OPCODE_RE = re.compile(r"^(b{0}|bx{0})(\.\w)?$".format(CONDITION_CODES_RE)) + # Call instructions. + CALL_OPCODE_RE = re.compile(r"^(bl{0}|blx{0})(\.\w)?$".format(CONDITION_CODES_RE)) + CALL_OPERAND_RE = re.compile(r"^{}$".format(IMM_ADDRESS_RE)) + CBZ_CBNZ_OPCODE_RE = re.compile(r"^(cbz|cbnz)(\.\w)?$") + # Example: "r0, 1009bcbe " + CBZ_CBNZ_OPERAND_RE = re.compile(r"^[^,]+,\s+{}$".format(IMM_ADDRESS_RE)) + # Ignore lr register because it's for return. + INDIRECT_CALL_OPERAND_RE = re.compile(r"^r\d+|sb|sl|fp|ip|sp|pc$") + # TODO(cheyuw): Handle conditional versions of following + # instructions. + # TODO(cheyuw): Handle other kinds of pc modifying instructions (e.g. mov pc). + LDR_OPCODE_RE = re.compile(r"^ldr(\.\w)?$") + # Example: "pc, [sp], #4" + LDR_PC_OPERAND_RE = re.compile(r"^pc, \[([^\]]+)\]") + # TODO(cheyuw): Handle other kinds of stm instructions. + PUSH_OPCODE_RE = re.compile(r"^push$") + STM_OPCODE_RE = re.compile(r"^stmdb$") + # Stack subtraction instructions. + SUB_OPCODE_RE = re.compile(r"^sub(s|w)?(\.\w)?$") + SUB_OPERAND_RE = re.compile(r"^sp[^#]+#(\d+)") + # Example: "44d94: f893 0068 ldrb.w r0, [r3, #104] ; 0x68" + # Assume there is always a "\t" after the hex data. + DISASM_REGEX_RE = re.compile( + r"^(?P
[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+" + r"\t\s*(?P\S+)(\s+(?P[^;]*))?" + ) + + def ParseInstruction(self, line, function_end): + """Parse the line of instruction. + + Args: + line: Text of disassembly. + function_end: End address of the current function. None if unknown. + + Returns: + (address, opcode, operand_text): The instruction address, opcode, + and the text of operands. None if it + isn't an instruction line. + """ + result = self.DISASM_REGEX_RE.match(line) if result is None: - # Failed to match immediate address, maybe it is an indirect call. - # CBZ and CBNZ can't be indirect calls. - if (not is_cbz_cbnz_opcode and - self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None): - # Found an indirect call. - callsites.append(Callsite(address, None, is_tail)) + return None - else: - target_address = int(result.group(1), 16) - # Filter out the in-function target (branches and in-function calls, - # which are actually branches). - if not (function_symbol.size > 0 and - function_symbol.address < target_address < - (function_symbol.address + function_symbol.size)): - # Maybe it is a callsite. - callsites.append(Callsite(address, target_address, is_tail)) - - elif self.LDR_OPCODE_RE.match(opcode) is not None: - result = self.LDR_PC_OPERAND_RE.match(operand_text) - if result is not None: - # Ignore "ldr pc, [sp], xx" because it's usually a return. - if result.group(1) != 'sp': - # Found an indirect call. - callsites.append(Callsite(address, None, True)) - - elif self.PUSH_OPCODE_RE.match(opcode) is not None: - # Example: "{r4, r5, r6, r7, lr}" - stack_frame += (len(operand_text.split(',')) * - self.GENERAL_PURPOSE_REGISTER_SIZE) - elif self.SUB_OPCODE_RE.match(opcode) is not None: - result = self.SUB_OPERAND_RE.match(operand_text) - if result is not None: - stack_frame += int(result.group(1)) - else: - # Unhandled stack register subtraction. - assert not operand_text.startswith('sp') + address = int(result.group("address"), 16) + # Check if it's out of bound. + if function_end is not None and address >= function_end: + return None - elif self.STM_OPCODE_RE.match(opcode) is not None: - if operand_text.startswith('sp!'): - # Subtract and writeback to stack register. - # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}" - # Get the text of pushed register list. - unused_sp, unused_sep, parameter_text = operand_text.partition(',') - stack_frame += (len(parameter_text.split(',')) * - self.GENERAL_PURPOSE_REGISTER_SIZE) + opcode = result.group("opcode").strip() + operand_text = result.group("operand") + if operand_text is None: + operand_text = "" + else: + operand_text = operand_text.strip() + + return (address, opcode, operand_text) + + def AnalyzeFunction(self, function_symbol, instructions): + """Analyze function, resolve the size of stack frame and callsites. + + Args: + function_symbol: Function symbol. + instructions: Instruction list. + + Returns: + (stack_frame, callsites): Size of stack frame, callsite list. + """ + stack_frame = 0 + callsites = [] + for address, opcode, operand_text in instructions: + is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None + is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None + is_cbz_cbnz_opcode = self.CBZ_CBNZ_OPCODE_RE.match(opcode) is not None + if is_jump_opcode or is_call_opcode or is_cbz_cbnz_opcode: + is_tail = is_jump_opcode or is_cbz_cbnz_opcode + + if is_cbz_cbnz_opcode: + result = self.CBZ_CBNZ_OPERAND_RE.match(operand_text) + else: + result = self.CALL_OPERAND_RE.match(operand_text) + + if result is None: + # Failed to match immediate address, maybe it is an indirect call. + # CBZ and CBNZ can't be indirect calls. + if ( + not is_cbz_cbnz_opcode + and self.INDIRECT_CALL_OPERAND_RE.match(operand_text) + is not None + ): + # Found an indirect call. + callsites.append(Callsite(address, None, is_tail)) + + else: + target_address = int(result.group(1), 16) + # Filter out the in-function target (branches and in-function calls, + # which are actually branches). + if not ( + function_symbol.size > 0 + and function_symbol.address + < target_address + < (function_symbol.address + function_symbol.size) + ): + # Maybe it is a callsite. + callsites.append(Callsite(address, target_address, is_tail)) + + elif self.LDR_OPCODE_RE.match(opcode) is not None: + result = self.LDR_PC_OPERAND_RE.match(operand_text) + if result is not None: + # Ignore "ldr pc, [sp], xx" because it's usually a return. + if result.group(1) != "sp": + # Found an indirect call. + callsites.append(Callsite(address, None, True)) + + elif self.PUSH_OPCODE_RE.match(opcode) is not None: + # Example: "{r4, r5, r6, r7, lr}" + stack_frame += ( + len(operand_text.split(",")) * self.GENERAL_PURPOSE_REGISTER_SIZE + ) + elif self.SUB_OPCODE_RE.match(opcode) is not None: + result = self.SUB_OPERAND_RE.match(operand_text) + if result is not None: + stack_frame += int(result.group(1)) + else: + # Unhandled stack register subtraction. + assert not operand_text.startswith("sp") + + elif self.STM_OPCODE_RE.match(opcode) is not None: + if operand_text.startswith("sp!"): + # Subtract and writeback to stack register. + # Example: "sp!, {r4, r5, r6, r7, r8, r9, lr}" + # Get the text of pushed register list. + unused_sp, unused_sep, parameter_text = operand_text.partition(",") + stack_frame += ( + len(parameter_text.split(",")) + * self.GENERAL_PURPOSE_REGISTER_SIZE + ) + + return (stack_frame, callsites) - return (stack_frame, callsites) class RiscvAnalyzer(object): - """Disassembly analyzer for RISC-V architecture. - - Public Methods: - AnalyzeFunction: Analyze stack frame and callsites of the function. - """ - - # Possible condition code suffixes. - CONDITION_CODES = [ 'eqz', 'nez', 'lez', 'gez', 'ltz', 'gtz', 'gt', 'le', - 'gtu', 'leu', 'eq', 'ne', 'ge', 'lt', 'ltu', 'geu'] - CONDITION_CODES_RE = '({})'.format('|'.join(CONDITION_CODES)) - # Branch instructions. - JUMP_OPCODE_RE = re.compile(r'^(b{0}|j|jr)$'.format(CONDITION_CODES_RE)) - # Call instructions. - CALL_OPCODE_RE = re.compile(r'^(jal|jalr)$') - # Example: "j 8009b318 " or - # "jal ra,800a4394 " or - # "bltu t0,t1,80080300 " - JUMP_ADDRESS_RE = r'((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>' - CALL_OPERAND_RE = re.compile(r'^{}$'.format(JUMP_ADDRESS_RE)) - # Capture address, Example: 800a4394 - CAPTURE_ADDRESS = re.compile(r'[0-9A-Fa-f]{8}') - # Indirect jump, Example: jalr a5 - INDIRECT_CALL_OPERAND_RE = re.compile(r'^t\d+|s\d+|a\d+$') - # Example: addi - ADDI_OPCODE_RE = re.compile(r'^addi$') - # Allocate stack instructions. - ADDI_OPERAND_RE = re.compile(r'^(sp,sp,-\d+)$') - # Example: "800804b6: 1101 addi sp,sp,-32" - DISASM_REGEX_RE = re.compile(r'^(?P
[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+' - r'\t\s*(?P\S+)(\s+(?P[^;]*))?') - - def ParseInstruction(self, line, function_end): - """Parse the line of instruction. + """Disassembly analyzer for RISC-V architecture. - Args: - line: Text of disassembly. - function_end: End address of the current function. None if unknown. - - Returns: - (address, opcode, operand_text): The instruction address, opcode, - and the text of operands. None if it - isn't an instruction line. + Public Methods: + AnalyzeFunction: Analyze stack frame and callsites of the function. """ - result = self.DISASM_REGEX_RE.match(line) - if result is None: - return None - - address = int(result.group('address'), 16) - # Check if it's out of bound. - if function_end is not None and address >= function_end: - return None - - opcode = result.group('opcode').strip() - operand_text = result.group('operand') - if operand_text is None: - operand_text = '' - else: - operand_text = operand_text.strip() - - return (address, opcode, operand_text) - - def AnalyzeFunction(self, function_symbol, instructions): - - stack_frame = 0 - callsites = [] - for address, opcode, operand_text in instructions: - is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None - is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None - if is_jump_opcode or is_call_opcode: - is_tail = is_jump_opcode - - result = self.CALL_OPERAND_RE.match(operand_text) + # Possible condition code suffixes. + CONDITION_CODES = [ + "eqz", + "nez", + "lez", + "gez", + "ltz", + "gtz", + "gt", + "le", + "gtu", + "leu", + "eq", + "ne", + "ge", + "lt", + "ltu", + "geu", + ] + CONDITION_CODES_RE = "({})".format("|".join(CONDITION_CODES)) + # Branch instructions. + JUMP_OPCODE_RE = re.compile(r"^(b{0}|j|jr)$".format(CONDITION_CODES_RE)) + # Call instructions. + CALL_OPCODE_RE = re.compile(r"^(jal|jalr)$") + # Example: "j 8009b318 " or + # "jal ra,800a4394 " or + # "bltu t0,t1,80080300 " + JUMP_ADDRESS_RE = r"((\w(\w|\d\d),){0,2})([0-9A-Fa-f]+)\s+<([^>]+)>" + CALL_OPERAND_RE = re.compile(r"^{}$".format(JUMP_ADDRESS_RE)) + # Capture address, Example: 800a4394 + CAPTURE_ADDRESS = re.compile(r"[0-9A-Fa-f]{8}") + # Indirect jump, Example: jalr a5 + INDIRECT_CALL_OPERAND_RE = re.compile(r"^t\d+|s\d+|a\d+$") + # Example: addi + ADDI_OPCODE_RE = re.compile(r"^addi$") + # Allocate stack instructions. + ADDI_OPERAND_RE = re.compile(r"^(sp,sp,-\d+)$") + # Example: "800804b6: 1101 addi sp,sp,-32" + DISASM_REGEX_RE = re.compile( + r"^(?P
[0-9A-Fa-f]+):\s+[0-9A-Fa-f ]+" + r"\t\s*(?P\S+)(\s+(?P[^;]*))?" + ) + + def ParseInstruction(self, line, function_end): + """Parse the line of instruction. + + Args: + line: Text of disassembly. + function_end: End address of the current function. None if unknown. + + Returns: + (address, opcode, operand_text): The instruction address, opcode, + and the text of operands. None if it + isn't an instruction line. + """ + result = self.DISASM_REGEX_RE.match(line) if result is None: - if (self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None): - # Found an indirect call. - callsites.append(Callsite(address, None, is_tail)) - - else: - # Capture address form operand_text and then convert to string - address_str = "".join(self.CAPTURE_ADDRESS.findall(operand_text)) - # String to integer - target_address = int(address_str, 16) - # Filter out the in-function target (branches and in-function calls, - # which are actually branches). - if not (function_symbol.size > 0 and - function_symbol.address < target_address < - (function_symbol.address + function_symbol.size)): - # Maybe it is a callsite. - callsites.append(Callsite(address, target_address, is_tail)) - - elif self.ADDI_OPCODE_RE.match(opcode) is not None: - # Example: sp,sp,-32 - if self.ADDI_OPERAND_RE.match(operand_text) is not None: - stack_frame += abs(int(operand_text.split(",")[2])) - - return (stack_frame, callsites) - -class StackAnalyzer(object): - """Class to analyze stack usage. - - Public Methods: - Analyze: Run the stack analysis. - """ - - C_FUNCTION_NAME = r'_A-Za-z0-9' - - # Assume there is no ":" in the path. - # Example: "driver/accel_kionix.c:321 (discriminator 3)" - ADDRTOLINE_RE = re.compile( - r'^(?P[^:]+):(?P\d+)(\s+\(discriminator\s+\d+\))?$') - # To eliminate the suffix appended by compilers, try to extract the - # C function name from the prefix of symbol name. - # Example: "SHA256_transform.constprop.28" - FUNCTION_PREFIX_NAME_RE = re.compile( - r'^(?P[{0}]+)([^{0}].*)?$'.format(C_FUNCTION_NAME)) - - # Errors of annotation resolving. - ANNOTATION_ERROR_INVALID = 'invalid signature' - ANNOTATION_ERROR_NOTFOUND = 'function is not found' - ANNOTATION_ERROR_AMBIGUOUS = 'signature is ambiguous' - - def __init__(self, options, symbols, rodata, tasklist, annotation): - """Constructor. - - Args: - options: Namespace from argparse.parse_args(). - symbols: Symbol list. - rodata: Content of .rodata section (offset, data) - tasklist: Task list. - annotation: Annotation config. - """ - self.options = options - self.symbols = symbols - self.rodata_offset = rodata[0] - self.rodata = rodata[1] - self.tasklist = tasklist - self.annotation = annotation - self.address_to_line_cache = {} - - def AddressToLine(self, address, resolve_inline=False): - """Convert address to line. - - Args: - address: Target address. - resolve_inline: Output the stack of inlining. - - Returns: - lines: List of the corresponding lines. - - Raises: - StackAnalyzerError: If addr2line is failed. - """ - cache_key = (address, resolve_inline) - if cache_key in self.address_to_line_cache: - return self.address_to_line_cache[cache_key] - - try: - args = [self.options.addr2line, - '-f', - '-e', - self.options.elf_path, - '{:x}'.format(address)] - if resolve_inline: - args.append('-i') - - line_text = subprocess.check_output(args, encoding='utf-8') - except subprocess.CalledProcessError: - raise StackAnalyzerError('addr2line failed to resolve lines.') - except OSError: - raise StackAnalyzerError('Failed to run addr2line.') - - lines = [line.strip() for line in line_text.splitlines()] - # Assume the output has at least one pair like "function\nlocation\n", and - # they always show up in pairs. - # Example: "handle_request\n - # common/usb_pd_protocol.c:1191\n" - assert len(lines) >= 2 and len(lines) % 2 == 0 - - line_infos = [] - for index in range(0, len(lines), 2): - (function_name, line_text) = lines[index:index + 2] - if line_text in ['??:0', ':?']: - line_infos.append(None) - else: - result = self.ADDRTOLINE_RE.match(line_text) - # Assume the output is always well-formed. - assert result is not None - line_infos.append((function_name.strip(), - os.path.realpath(result.group('path').strip()), - int(result.group('linenum')))) - - self.address_to_line_cache[cache_key] = line_infos - return line_infos - - def AnalyzeDisassembly(self, disasm_text): - """Parse the disassembly text, analyze, and build a map of all functions. - - Args: - disasm_text: Disassembly text. - - Returns: - function_map: Dict of functions. - """ - disasm_lines = [line.strip() for line in disasm_text.splitlines()] - - if 'nds' in disasm_lines[1]: - analyzer = AndesAnalyzer() - elif 'arm' in disasm_lines[1]: - analyzer = ArmAnalyzer() - elif 'riscv' in disasm_lines[1]: - analyzer = RiscvAnalyzer() - else: - raise StackAnalyzerError('Unsupported architecture.') - - # Example: "08028c8c :" - function_signature_regex = re.compile( - r'^(?P
[0-9A-Fa-f]+)\s+<(?P[^>]+)>:$') - - def DetectFunctionHead(line): - """Check if the line is a function head. - - Args: - line: Text of disassembly. - - Returns: - symbol: Function symbol. None if it isn't a function head. - """ - result = function_signature_regex.match(line) - if result is None: - return None - - address = int(result.group('address'), 16) - symbol = symbol_map.get(address) - - # Check if the function exists and matches. - if symbol is None or symbol.symtype != 'F': - return None - - return symbol - - # Build symbol map, indexed by symbol address. - symbol_map = {} - for symbol in self.symbols: - # If there are multiple symbols with same address, keeping any of them is - # good enough. - symbol_map[symbol.address] = symbol - - # Parse the disassembly text. We update the variable "line" to next line - # when needed. There are two steps of parser: - # - # Step 1: Searching for the function head. Once reach the function head, - # move to the next line, which is the first line of function body. - # - # Step 2: Parsing each instruction line of function body. Once reach a - # non-instruction line, stop parsing and analyze the parsed instructions. - # - # Finally turn back to the step 1 without updating the line, because the - # current non-instruction line can be another function head. - function_map = {} - # The following three variables are the states of the parsing processing. - # They will be initialized properly during the state changes. - function_symbol = None - function_end = None - instructions = [] - - # Remove heading and tailing spaces for each line. - line_index = 0 - while line_index < len(disasm_lines): - # Get the current line. - line = disasm_lines[line_index] - - if function_symbol is None: - # Step 1: Search for the function head. - - function_symbol = DetectFunctionHead(line) - if function_symbol is not None: - # Assume there is no empty function. If the function head is followed - # by EOF, it is an empty function. - assert line_index + 1 < len(disasm_lines) - - # Found the function head, initialize and turn to the step 2. - instructions = [] - # If symbol size exists, use it as a hint of function size. - if function_symbol.size > 0: - function_end = function_symbol.address + function_symbol.size - else: - function_end = None - - else: - # Step 2: Parse the function body. - - instruction = analyzer.ParseInstruction(line, function_end) - if instruction is not None: - instructions.append(instruction) - - if instruction is None or line_index + 1 == len(disasm_lines): - # Either the invalid instruction or EOF indicates the end of the - # function, finalize the function analysis. - - # Assume there is no empty function. - assert len(instructions) > 0 - - (stack_frame, callsites) = analyzer.AnalyzeFunction(function_symbol, - instructions) - # Assume the function addresses are unique in the disassembly. - assert function_symbol.address not in function_map - function_map[function_symbol.address] = Function( - function_symbol.address, - function_symbol.name, - stack_frame, - callsites) - - # Initialize and turn back to the step 1. - function_symbol = None - - # If the current line isn't an instruction, it can be another function - # head, skip moving to the next line. - if instruction is None: - continue - - # Move to the next line. - line_index += 1 + return None - # Resolve callees of functions. - for function in function_map.values(): - for callsite in function.callsites: - if callsite.target is not None: - # Remain the callee as None if we can't resolve it. - callsite.callee = function_map.get(callsite.target) + address = int(result.group("address"), 16) + # Check if it's out of bound. + if function_end is not None and address >= function_end: + return None - return function_map + opcode = result.group("opcode").strip() + operand_text = result.group("operand") + if operand_text is None: + operand_text = "" + else: + operand_text = operand_text.strip() + + return (address, opcode, operand_text) + + def AnalyzeFunction(self, function_symbol, instructions): + + stack_frame = 0 + callsites = [] + for address, opcode, operand_text in instructions: + is_jump_opcode = self.JUMP_OPCODE_RE.match(opcode) is not None + is_call_opcode = self.CALL_OPCODE_RE.match(opcode) is not None + + if is_jump_opcode or is_call_opcode: + is_tail = is_jump_opcode + + result = self.CALL_OPERAND_RE.match(operand_text) + if result is None: + if self.INDIRECT_CALL_OPERAND_RE.match(operand_text) is not None: + # Found an indirect call. + callsites.append(Callsite(address, None, is_tail)) + + else: + # Capture address form operand_text and then convert to string + address_str = "".join(self.CAPTURE_ADDRESS.findall(operand_text)) + # String to integer + target_address = int(address_str, 16) + # Filter out the in-function target (branches and in-function calls, + # which are actually branches). + if not ( + function_symbol.size > 0 + and function_symbol.address + < target_address + < (function_symbol.address + function_symbol.size) + ): + # Maybe it is a callsite. + callsites.append(Callsite(address, target_address, is_tail)) + + elif self.ADDI_OPCODE_RE.match(opcode) is not None: + # Example: sp,sp,-32 + if self.ADDI_OPERAND_RE.match(operand_text) is not None: + stack_frame += abs(int(operand_text.split(",")[2])) + + return (stack_frame, callsites) - def MapAnnotation(self, function_map, signature_set): - """Map annotation signatures to functions. - Args: - function_map: Function map. - signature_set: Set of annotation signatures. +class StackAnalyzer(object): + """Class to analyze stack usage. - Returns: - Map of signatures to functions, map of signatures which can't be resolved. + Public Methods: + Analyze: Run the stack analysis. """ - # Build the symbol map indexed by symbol name. If there are multiple symbols - # with the same name, add them into a set. (e.g. symbols of static function - # with the same name) - symbol_map = collections.defaultdict(set) - for symbol in self.symbols: - if symbol.symtype == 'F': - # Function symbol. - result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name) - if result is not None: - function = function_map.get(symbol.address) - # Ignore the symbol not in disassembly. - if function is not None: - # If there are multiple symbol with the same name and point to the - # same function, the set will deduplicate them. - symbol_map[result.group('name').strip()].add(function) - - # Build the signature map indexed by annotation signature. - signature_map = {} - sig_error_map = {} - symbol_path_map = {} - for sig in signature_set: - (name, path, _) = sig - - functions = symbol_map.get(name) - if functions is None: - sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND - continue - - if name not in symbol_path_map: - # Lazy symbol path resolving. Since the addr2line isn't fast, only - # resolve needed symbol paths. - group_map = collections.defaultdict(list) - for function in functions: - line_info = self.AddressToLine(function.address)[0] - if line_info is None: - continue - (_, symbol_path, _) = line_info + C_FUNCTION_NAME = r"_A-Za-z0-9" - # Group the functions with the same symbol signature (symbol name + - # symbol path). Assume they are the same copies and do the same - # annotation operations of them because we don't know which copy is - # indicated by the users. - group_map[symbol_path].append(function) + # Assume there is no ":" in the path. + # Example: "driver/accel_kionix.c:321 (discriminator 3)" + ADDRTOLINE_RE = re.compile( + r"^(?P[^:]+):(?P\d+)(\s+\(discriminator\s+\d+\))?$" + ) + # To eliminate the suffix appended by compilers, try to extract the + # C function name from the prefix of symbol name. + # Example: "SHA256_transform.constprop.28" + FUNCTION_PREFIX_NAME_RE = re.compile( + r"^(?P[{0}]+)([^{0}].*)?$".format(C_FUNCTION_NAME) + ) + + # Errors of annotation resolving. + ANNOTATION_ERROR_INVALID = "invalid signature" + ANNOTATION_ERROR_NOTFOUND = "function is not found" + ANNOTATION_ERROR_AMBIGUOUS = "signature is ambiguous" + + def __init__(self, options, symbols, rodata, tasklist, annotation): + """Constructor. + + Args: + options: Namespace from argparse.parse_args(). + symbols: Symbol list. + rodata: Content of .rodata section (offset, data) + tasklist: Task list. + annotation: Annotation config. + """ + self.options = options + self.symbols = symbols + self.rodata_offset = rodata[0] + self.rodata = rodata[1] + self.tasklist = tasklist + self.annotation = annotation + self.address_to_line_cache = {} + + def AddressToLine(self, address, resolve_inline=False): + """Convert address to line. + + Args: + address: Target address. + resolve_inline: Output the stack of inlining. + + Returns: + lines: List of the corresponding lines. + + Raises: + StackAnalyzerError: If addr2line is failed. + """ + cache_key = (address, resolve_inline) + if cache_key in self.address_to_line_cache: + return self.address_to_line_cache[cache_key] + + try: + args = [ + self.options.addr2line, + "-f", + "-e", + self.options.elf_path, + "{:x}".format(address), + ] + if resolve_inline: + args.append("-i") + + line_text = subprocess.check_output(args, encoding="utf-8") + except subprocess.CalledProcessError: + raise StackAnalyzerError("addr2line failed to resolve lines.") + except OSError: + raise StackAnalyzerError("Failed to run addr2line.") + + lines = [line.strip() for line in line_text.splitlines()] + # Assume the output has at least one pair like "function\nlocation\n", and + # they always show up in pairs. + # Example: "handle_request\n + # common/usb_pd_protocol.c:1191\n" + assert len(lines) >= 2 and len(lines) % 2 == 0 + + line_infos = [] + for index in range(0, len(lines), 2): + (function_name, line_text) = lines[index : index + 2] + if line_text in ["??:0", ":?"]: + line_infos.append(None) + else: + result = self.ADDRTOLINE_RE.match(line_text) + # Assume the output is always well-formed. + assert result is not None + line_infos.append( + ( + function_name.strip(), + os.path.realpath(result.group("path").strip()), + int(result.group("linenum")), + ) + ) + + self.address_to_line_cache[cache_key] = line_infos + return line_infos + + def AnalyzeDisassembly(self, disasm_text): + """Parse the disassembly text, analyze, and build a map of all functions. + + Args: + disasm_text: Disassembly text. + + Returns: + function_map: Dict of functions. + """ + disasm_lines = [line.strip() for line in disasm_text.splitlines()] + + if "nds" in disasm_lines[1]: + analyzer = AndesAnalyzer() + elif "arm" in disasm_lines[1]: + analyzer = ArmAnalyzer() + elif "riscv" in disasm_lines[1]: + analyzer = RiscvAnalyzer() + else: + raise StackAnalyzerError("Unsupported architecture.") - symbol_path_map[name] = group_map + # Example: "08028c8c :" + function_signature_regex = re.compile( + r"^(?P
[0-9A-Fa-f]+)\s+<(?P[^>]+)>:$" + ) - # Symbol matching. - function_group = None - group_map = symbol_path_map[name] - if len(group_map) > 0: - if path is None: - if len(group_map) > 1: - # There is ambiguity but the path isn't specified. - sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS - continue + def DetectFunctionHead(line): + """Check if the line is a function head. - # No path signature but all symbol signatures of functions are same. - # Assume they are the same functions, so there is no ambiguity. - (function_group,) = group_map.values() - else: - function_group = group_map.get(path) + Args: + line: Text of disassembly. - if function_group is None: - sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND - continue + Returns: + symbol: Function symbol. None if it isn't a function head. + """ + result = function_signature_regex.match(line) + if result is None: + return None - # The function_group is a list of all the same functions (according to - # our assumption) which should be annotated together. - signature_map[sig] = function_group + address = int(result.group("address"), 16) + symbol = symbol_map.get(address) - return (signature_map, sig_error_map) + # Check if the function exists and matches. + if symbol is None or symbol.symtype != "F": + return None - def LoadAnnotation(self): - """Load annotation rules. + return symbol - Returns: - Map of add rules, set of remove rules, set of text signatures which can't - be parsed. - """ - # Assume there is no ":" in the path. - # Example: "get_range.lto.2501[driver/accel_kionix.c:327]" - annotation_signature_regex = re.compile( - r'^(?P[^\[]+)(\[(?P[^:]+)(:(?P\d+))?\])?$') - - def NormalizeSignature(signature_text): - """Parse and normalize the annotation signature. - - Args: - signature_text: Text of the annotation signature. - - Returns: - (function name, path, line number) of the signature. The path and line - number can be None if not exist. None if failed to parse. - """ - result = annotation_signature_regex.match(signature_text.strip()) - if result is None: - return None - - name_result = self.FUNCTION_PREFIX_NAME_RE.match( - result.group('name').strip()) - if name_result is None: - return None - - path = result.group('path') - if path is not None: - path = os.path.realpath(path.strip()) - - linenum = result.group('linenum') - if linenum is not None: - linenum = int(linenum.strip()) - - return (name_result.group('name').strip(), path, linenum) - - def ExpandArray(dic): - """Parse and expand a symbol array - - Args: - dic: Dictionary for the array annotation - - Returns: - array of (symbol name, None, None). - """ - # TODO(drinkcat): This function is quite inefficient, as it goes through - # the symbol table multiple times. - - begin_name = dic['name'] - end_name = dic['name'] + "_end" - offset = dic['offset'] if 'offset' in dic else 0 - stride = dic['stride'] - - begin_address = None - end_address = None - - for symbol in self.symbols: - if (symbol.name == begin_name): - begin_address = symbol.address - if (symbol.name == end_name): - end_address = symbol.address - - if (not begin_address or not end_address): - return None - - output = [] - # TODO(drinkcat): This is inefficient as we go from address to symbol - # object then to symbol name, and later on we'll go back from symbol name - # to symbol object. - for addr in range(begin_address+offset, end_address, stride): - # TODO(drinkcat): Not all architectures need to drop the first bit. - val = self.rodata[(addr-self.rodata_offset) // 4] & 0xfffffffe - name = None + # Build symbol map, indexed by symbol address. + symbol_map = {} for symbol in self.symbols: - if (symbol.address == val): - result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name) - name = result.group('name') - break - - if not name: - raise StackAnalyzerError('Cannot find function for address %s.', - hex(val)) - - output.append((name, None, None)) - - return output - - add_rules = collections.defaultdict(set) - remove_rules = list() - invalid_sigtxts = set() - - if 'add' in self.annotation and self.annotation['add'] is not None: - for src_sigtxt, dst_sigtxts in self.annotation['add'].items(): - src_sig = NormalizeSignature(src_sigtxt) - if src_sig is None: - invalid_sigtxts.add(src_sigtxt) - continue - - for dst_sigtxt in dst_sigtxts: - if isinstance(dst_sigtxt, dict): - dst_sig = ExpandArray(dst_sigtxt) - if dst_sig is None: - invalid_sigtxts.add(str(dst_sigtxt)) + # If there are multiple symbols with same address, keeping any of them is + # good enough. + symbol_map[symbol.address] = symbol + + # Parse the disassembly text. We update the variable "line" to next line + # when needed. There are two steps of parser: + # + # Step 1: Searching for the function head. Once reach the function head, + # move to the next line, which is the first line of function body. + # + # Step 2: Parsing each instruction line of function body. Once reach a + # non-instruction line, stop parsing and analyze the parsed instructions. + # + # Finally turn back to the step 1 without updating the line, because the + # current non-instruction line can be another function head. + function_map = {} + # The following three variables are the states of the parsing processing. + # They will be initialized properly during the state changes. + function_symbol = None + function_end = None + instructions = [] + + # Remove heading and tailing spaces for each line. + line_index = 0 + while line_index < len(disasm_lines): + # Get the current line. + line = disasm_lines[line_index] + + if function_symbol is None: + # Step 1: Search for the function head. + + function_symbol = DetectFunctionHead(line) + if function_symbol is not None: + # Assume there is no empty function. If the function head is followed + # by EOF, it is an empty function. + assert line_index + 1 < len(disasm_lines) + + # Found the function head, initialize and turn to the step 2. + instructions = [] + # If symbol size exists, use it as a hint of function size. + if function_symbol.size > 0: + function_end = function_symbol.address + function_symbol.size + else: + function_end = None + else: - add_rules[src_sig].update(dst_sig) - else: - dst_sig = NormalizeSignature(dst_sigtxt) - if dst_sig is None: - invalid_sigtxts.add(dst_sigtxt) + # Step 2: Parse the function body. + + instruction = analyzer.ParseInstruction(line, function_end) + if instruction is not None: + instructions.append(instruction) + + if instruction is None or line_index + 1 == len(disasm_lines): + # Either the invalid instruction or EOF indicates the end of the + # function, finalize the function analysis. + + # Assume there is no empty function. + assert len(instructions) > 0 + + (stack_frame, callsites) = analyzer.AnalyzeFunction( + function_symbol, instructions + ) + # Assume the function addresses are unique in the disassembly. + assert function_symbol.address not in function_map + function_map[function_symbol.address] = Function( + function_symbol.address, + function_symbol.name, + stack_frame, + callsites, + ) + + # Initialize and turn back to the step 1. + function_symbol = None + + # If the current line isn't an instruction, it can be another function + # head, skip moving to the next line. + if instruction is None: + continue + + # Move to the next line. + line_index += 1 + + # Resolve callees of functions. + for function in function_map.values(): + for callsite in function.callsites: + if callsite.target is not None: + # Remain the callee as None if we can't resolve it. + callsite.callee = function_map.get(callsite.target) + + return function_map + + def MapAnnotation(self, function_map, signature_set): + """Map annotation signatures to functions. + + Args: + function_map: Function map. + signature_set: Set of annotation signatures. + + Returns: + Map of signatures to functions, map of signatures which can't be resolved. + """ + # Build the symbol map indexed by symbol name. If there are multiple symbols + # with the same name, add them into a set. (e.g. symbols of static function + # with the same name) + symbol_map = collections.defaultdict(set) + for symbol in self.symbols: + if symbol.symtype == "F": + # Function symbol. + result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name) + if result is not None: + function = function_map.get(symbol.address) + # Ignore the symbol not in disassembly. + if function is not None: + # If there are multiple symbol with the same name and point to the + # same function, the set will deduplicate them. + symbol_map[result.group("name").strip()].add(function) + + # Build the signature map indexed by annotation signature. + signature_map = {} + sig_error_map = {} + symbol_path_map = {} + for sig in signature_set: + (name, path, _) = sig + + functions = symbol_map.get(name) + if functions is None: + sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND + continue + + if name not in symbol_path_map: + # Lazy symbol path resolving. Since the addr2line isn't fast, only + # resolve needed symbol paths. + group_map = collections.defaultdict(list) + for function in functions: + line_info = self.AddressToLine(function.address)[0] + if line_info is None: + continue + + (_, symbol_path, _) = line_info + + # Group the functions with the same symbol signature (symbol name + + # symbol path). Assume they are the same copies and do the same + # annotation operations of them because we don't know which copy is + # indicated by the users. + group_map[symbol_path].append(function) + + symbol_path_map[name] = group_map + + # Symbol matching. + function_group = None + group_map = symbol_path_map[name] + if len(group_map) > 0: + if path is None: + if len(group_map) > 1: + # There is ambiguity but the path isn't specified. + sig_error_map[sig] = self.ANNOTATION_ERROR_AMBIGUOUS + continue + + # No path signature but all symbol signatures of functions are same. + # Assume they are the same functions, so there is no ambiguity. + (function_group,) = group_map.values() + else: + function_group = group_map.get(path) + + if function_group is None: + sig_error_map[sig] = self.ANNOTATION_ERROR_NOTFOUND + continue + + # The function_group is a list of all the same functions (according to + # our assumption) which should be annotated together. + signature_map[sig] = function_group + + return (signature_map, sig_error_map) + + def LoadAnnotation(self): + """Load annotation rules. + + Returns: + Map of add rules, set of remove rules, set of text signatures which can't + be parsed. + """ + # Assume there is no ":" in the path. + # Example: "get_range.lto.2501[driver/accel_kionix.c:327]" + annotation_signature_regex = re.compile( + r"^(?P[^\[]+)(\[(?P[^:]+)(:(?P\d+))?\])?$" + ) + + def NormalizeSignature(signature_text): + """Parse and normalize the annotation signature. + + Args: + signature_text: Text of the annotation signature. + + Returns: + (function name, path, line number) of the signature. The path and line + number can be None if not exist. None if failed to parse. + """ + result = annotation_signature_regex.match(signature_text.strip()) + if result is None: + return None + + name_result = self.FUNCTION_PREFIX_NAME_RE.match( + result.group("name").strip() + ) + if name_result is None: + return None + + path = result.group("path") + if path is not None: + path = os.path.realpath(path.strip()) + + linenum = result.group("linenum") + if linenum is not None: + linenum = int(linenum.strip()) + + return (name_result.group("name").strip(), path, linenum) + + def ExpandArray(dic): + """Parse and expand a symbol array + + Args: + dic: Dictionary for the array annotation + + Returns: + array of (symbol name, None, None). + """ + # TODO(drinkcat): This function is quite inefficient, as it goes through + # the symbol table multiple times. + + begin_name = dic["name"] + end_name = dic["name"] + "_end" + offset = dic["offset"] if "offset" in dic else 0 + stride = dic["stride"] + + begin_address = None + end_address = None + + for symbol in self.symbols: + if symbol.name == begin_name: + begin_address = symbol.address + if symbol.name == end_name: + end_address = symbol.address + + if not begin_address or not end_address: + return None + + output = [] + # TODO(drinkcat): This is inefficient as we go from address to symbol + # object then to symbol name, and later on we'll go back from symbol name + # to symbol object. + for addr in range(begin_address + offset, end_address, stride): + # TODO(drinkcat): Not all architectures need to drop the first bit. + val = self.rodata[(addr - self.rodata_offset) // 4] & 0xFFFFFFFE + name = None + for symbol in self.symbols: + if symbol.address == val: + result = self.FUNCTION_PREFIX_NAME_RE.match(symbol.name) + name = result.group("name") + break + + if not name: + raise StackAnalyzerError( + "Cannot find function for address %s.", hex(val) + ) + + output.append((name, None, None)) + + return output + + add_rules = collections.defaultdict(set) + remove_rules = list() + invalid_sigtxts = set() + + if "add" in self.annotation and self.annotation["add"] is not None: + for src_sigtxt, dst_sigtxts in self.annotation["add"].items(): + src_sig = NormalizeSignature(src_sigtxt) + if src_sig is None: + invalid_sigtxts.add(src_sigtxt) + continue + + for dst_sigtxt in dst_sigtxts: + if isinstance(dst_sigtxt, dict): + dst_sig = ExpandArray(dst_sigtxt) + if dst_sig is None: + invalid_sigtxts.add(str(dst_sigtxt)) + else: + add_rules[src_sig].update(dst_sig) + else: + dst_sig = NormalizeSignature(dst_sigtxt) + if dst_sig is None: + invalid_sigtxts.add(dst_sigtxt) + else: + add_rules[src_sig].add(dst_sig) + + if "remove" in self.annotation and self.annotation["remove"] is not None: + for sigtxt_path in self.annotation["remove"]: + if isinstance(sigtxt_path, str): + # The path has only one vertex. + sigtxt_path = [sigtxt_path] + + if len(sigtxt_path) == 0: + continue + + # Generate multiple remove paths from all the combinations of the + # signatures of each vertex. + sig_paths = [[]] + broken_flag = False + for sigtxt_node in sigtxt_path: + if isinstance(sigtxt_node, str): + # The vertex has only one signature. + sigtxt_set = {sigtxt_node} + elif isinstance(sigtxt_node, list): + # The vertex has multiple signatures. + sigtxt_set = set(sigtxt_node) + else: + # Assume the format of annotation is verified. There should be no + # invalid case. + assert False + + sig_set = set() + for sigtxt in sigtxt_set: + sig = NormalizeSignature(sigtxt) + if sig is None: + invalid_sigtxts.add(sigtxt) + broken_flag = True + elif not broken_flag: + sig_set.add(sig) + + if broken_flag: + continue + + # Append each signature of the current node to the all previous + # remove paths. + sig_paths = [path + [sig] for path in sig_paths for sig in sig_set] + + if not broken_flag: + # All signatures are normalized. The remove path has no error. + remove_rules.extend(sig_paths) + + return (add_rules, remove_rules, invalid_sigtxts) + + def ResolveAnnotation(self, function_map): + """Resolve annotation. + + Args: + function_map: Function map. + + Returns: + Set of added call edges, list of remove paths, set of eliminated + callsite addresses, set of annotation signatures which can't be resolved. + """ + + def StringifySignature(signature): + """Stringify the tupled signature. + + Args: + signature: Tupled signature. + + Returns: + Signature string. + """ + (name, path, linenum) = signature + bracket_text = "" + if path is not None: + path = os.path.relpath(path) + if linenum is None: + bracket_text = "[{}]".format(path) + else: + bracket_text = "[{}:{}]".format(path, linenum) + + return name + bracket_text + + (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation() + + signature_set = set() + for src_sig, dst_sigs in add_rules.items(): + signature_set.add(src_sig) + signature_set.update(dst_sigs) + + for remove_sigs in remove_rules: + signature_set.update(remove_sigs) + + # Map signatures to functions. + (signature_map, sig_error_map) = self.MapAnnotation(function_map, signature_set) + + # Build the indirect callsite map indexed by callsite signature. + indirect_map = collections.defaultdict(set) + for function in function_map.values(): + for callsite in function.callsites: + if callsite.target is not None: + continue + + # Found an indirect callsite. + line_info = self.AddressToLine(callsite.address)[0] + if line_info is None: + continue + + (name, path, linenum) = line_info + result = self.FUNCTION_PREFIX_NAME_RE.match(name) + if result is None: + continue + + indirect_map[(result.group("name").strip(), path, linenum)].add( + (function, callsite.address) + ) + + # Generate the annotation sets. + add_set = set() + remove_list = list() + eliminated_addrs = set() + + for src_sig, dst_sigs in add_rules.items(): + src_funcs = set(signature_map.get(src_sig, [])) + # Try to match the source signature to the indirect callsites. Even if it + # can't be found in disassembly. + indirect_calls = indirect_map.get(src_sig) + if indirect_calls is not None: + for function, callsite_address in indirect_calls: + # Add the caller of the indirect callsite to the source functions. + src_funcs.add(function) + # Assume each callsite can be represented by a unique address. + eliminated_addrs.add(callsite_address) + + if src_sig in sig_error_map: + # Assume the error is always the not found error. Since the signature + # found in indirect callsite map must be a full signature, it can't + # happen the ambiguous error. + assert sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND + # Found in inline stack, remove the not found error. + del sig_error_map[src_sig] + + for dst_sig in dst_sigs: + dst_funcs = signature_map.get(dst_sig) + if dst_funcs is None: + continue + + # Duplicate the call edge for all the same source and destination + # functions. + for src_func in src_funcs: + for dst_func in dst_funcs: + add_set.add((src_func, dst_func)) + + for remove_sigs in remove_rules: + # Since each signature can be mapped to multiple functions, generate + # multiple remove paths from all the combinations of these functions. + remove_paths = [[]] + skip_flag = False + for remove_sig in remove_sigs: + # Transform each signature to the corresponding functions. + remove_funcs = signature_map.get(remove_sig) + if remove_funcs is None: + # There is an unresolved signature in the remove path. Ignore the + # whole broken remove path. + skip_flag = True + break + else: + # Append each function of the current signature to the all previous + # remove paths. + remove_paths = [p + [f] for p in remove_paths for f in remove_funcs] + + if skip_flag: + # Ignore the broken remove path. + continue + + for remove_path in remove_paths: + # Deduplicate the remove paths. + if remove_path not in remove_list: + remove_list.append(remove_path) + + # Format the error messages. + failed_sigtxts = set() + for sigtxt in invalid_sigtxts: + failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID)) + + for sig, error in sig_error_map.items(): + failed_sigtxts.add((StringifySignature(sig), error)) + + return (add_set, remove_list, eliminated_addrs, failed_sigtxts) + + def PreprocessAnnotation( + self, function_map, add_set, remove_list, eliminated_addrs + ): + """Preprocess the annotation and callgraph. + + Add the missing call edges, and delete simple remove paths (the paths have + one or two vertices) from the function_map. + + Eliminate the annotated indirect callsites. + + Return the remaining remove list. + + Args: + function_map: Function map. + add_set: Set of missing call edges. + remove_list: List of remove paths. + eliminated_addrs: Set of eliminated callsite addresses. + + Returns: + List of remaining remove paths. + """ + + def CheckEdge(path): + """Check if all edges of the path are on the callgraph. + + Args: + path: Path. + + Returns: + True or False. + """ + for index in range(len(path) - 1): + if (path[index], path[index + 1]) not in edge_set: + return False + + return True + + for src_func, dst_func in add_set: + # TODO(cheyuw): Support tailing call annotation. + src_func.callsites.append(Callsite(None, dst_func.address, False, dst_func)) + + # Delete simple remove paths. + remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2) + edge_set = set() + for function in function_map.values(): + cleaned_callsites = [] + for callsite in function.callsites: + if (callsite.callee,) in remove_simple or ( + function, + callsite.callee, + ) in remove_simple: + continue + + if callsite.target is None and callsite.address in eliminated_addrs: + continue + + cleaned_callsites.append(callsite) + if callsite.callee is not None: + edge_set.add((function, callsite.callee)) + + function.callsites = cleaned_callsites + + return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)] + + def AnalyzeCallGraph(self, function_map, remove_list): + """Analyze callgraph. + + It will update the max stack size and path for each function. + + Args: + function_map: Function map. + remove_list: List of remove paths. + + Returns: + List of function cycles. + """ + + def Traverse(curr_state): + """Traverse the callgraph and calculate the max stack usages of functions. + + Args: + curr_state: Current state. + + Returns: + SCC lowest link. + """ + scc_index = scc_index_counter[0] + scc_index_counter[0] += 1 + scc_index_map[curr_state] = scc_index + scc_lowlink = scc_index + scc_stack.append(curr_state) + # Push the current state in the stack. We can use a set to maintain this + # because the stacked states are unique; otherwise we will find a cycle + # first. + stacked_states.add(curr_state) + + (curr_address, curr_positions) = curr_state + curr_func = function_map[curr_address] + + invalid_flag = False + new_positions = list(curr_positions) + for index, position in enumerate(curr_positions): + remove_path = remove_list[index] + + # The position of each remove path in the state is the length of the + # longest matching path between the prefix of the remove path and the + # suffix of the current traversing path. We maintain this length when + # appending the next callee to the traversing path. And it can be used + # to check if the remove path appears in the traversing path. + + # TODO(cheyuw): Implement KMP algorithm to match remove paths + # efficiently. + if remove_path[position] is curr_func: + # Matches the current function, extend the length. + new_positions[index] = position + 1 + if new_positions[index] == len(remove_path): + # The length of the longest matching path is equal to the length of + # the remove path, which means the suffix of the current traversing + # path matches the remove path. + invalid_flag = True + break + + else: + # We can't get the new longest matching path by extending the previous + # one directly. Fallback to search the new longest matching path. + + # If we can't find any matching path in the following search, reset + # the matching length to 0. + new_positions[index] = 0 + + # We want to find the new longest matching prefix of remove path with + # the suffix of the current traversing path. Because the new longest + # matching path won't be longer than the prevous one now, and part of + # the suffix matches the prefix of remove path, we can get the needed + # suffix from the previous matching prefix of the invalid path. + suffix = remove_path[:position] + [curr_func] + for offset in range(1, len(suffix)): + length = position - offset + if remove_path[:length] == suffix[offset:]: + new_positions[index] = length + break + + new_positions = tuple(new_positions) + + # If the current suffix is invalid, set the max stack usage to 0. + max_stack_usage = 0 + max_callee_state = None + self_loop = False + + if not invalid_flag: + # Max stack usage is at least equal to the stack frame. + max_stack_usage = curr_func.stack_frame + for callsite in curr_func.callsites: + callee = callsite.callee + if callee is None: + continue + + callee_state = (callee.address, new_positions) + if callee_state not in scc_index_map: + # Unvisited state. + scc_lowlink = min(scc_lowlink, Traverse(callee_state)) + elif callee_state in stacked_states: + # The state is shown in the stack. There is a cycle. + sub_stack_usage = 0 + scc_lowlink = min(scc_lowlink, scc_index_map[callee_state]) + if callee_state == curr_state: + self_loop = True + + done_result = done_states.get(callee_state) + if done_result is not None: + # Already done this state and use its result. If the state reaches a + # cycle, reusing the result will cause inaccuracy (the stack usage + # of cycle depends on where the entrance is). But it's fine since we + # can't get accurate stack usage under this situation, and we rely + # on user-provided annotations to break the cycle, after which the + # result will be accurate again. + (sub_stack_usage, _) = done_result + + if callsite.is_tail: + # For tailing call, since the callee reuses the stack frame of the + # caller, choose the larger one directly. + stack_usage = max(curr_func.stack_frame, sub_stack_usage) + else: + stack_usage = curr_func.stack_frame + sub_stack_usage + + if stack_usage > max_stack_usage: + max_stack_usage = stack_usage + max_callee_state = callee_state + + if scc_lowlink == scc_index: + group = [] + while scc_stack[-1] != curr_state: + scc_state = scc_stack.pop() + stacked_states.remove(scc_state) + group.append(scc_state) + + scc_stack.pop() + stacked_states.remove(curr_state) + + # If the cycle is not empty, record it. + if len(group) > 0 or self_loop: + group.append(curr_state) + cycle_groups.append(group) + + # Store the done result. + done_states[curr_state] = (max_stack_usage, max_callee_state) + + if curr_positions == initial_positions: + # If the current state is initial state, we traversed the callgraph by + # using the current function as start point. Update the stack usage of + # the function. + # If the function matches a single vertex remove path, this will set its + # max stack usage to 0, which is not expected (we still calculate its + # max stack usage, but prevent any function from calling it). However, + # all the single vertex remove paths have been preprocessed and removed. + curr_func.stack_max_usage = max_stack_usage + + # Reconstruct the max stack path by traversing the state transitions. + max_stack_path = [curr_func] + callee_state = max_callee_state + while callee_state is not None: + # The first element of state tuple is function address. + max_stack_path.append(function_map[callee_state[0]]) + done_result = done_states.get(callee_state) + # All of the descendants should be done. + assert done_result is not None + (_, callee_state) = done_result + + curr_func.stack_max_path = max_stack_path + + return scc_lowlink + + # The state is the concatenation of the current function address and the + # state of matching position. + initial_positions = (0,) * len(remove_list) + done_states = {} + stacked_states = set() + scc_index_counter = [0] + scc_index_map = {} + scc_stack = [] + cycle_groups = [] + for function in function_map.values(): + if function.stack_max_usage is None: + Traverse((function.address, initial_positions)) + + cycle_functions = [] + for group in cycle_groups: + cycle = set(function_map[state[0]] for state in group) + if cycle not in cycle_functions: + cycle_functions.append(cycle) + + return cycle_functions + + def Analyze(self): + """Run the stack analysis. + + Raises: + StackAnalyzerError: If disassembly fails. + """ + + def OutputInlineStack(address, prefix=""): + """Output beautiful inline stack. + + Args: + address: Address. + prefix: Prefix of each line. + + Returns: + Key for sorting, output text + """ + line_infos = self.AddressToLine(address, True) + + if line_infos[0] is None: + order_key = (None, None) else: - add_rules[src_sig].add(dst_sig) - - if 'remove' in self.annotation and self.annotation['remove'] is not None: - for sigtxt_path in self.annotation['remove']: - if isinstance(sigtxt_path, str): - # The path has only one vertex. - sigtxt_path = [sigtxt_path] - - if len(sigtxt_path) == 0: - continue - - # Generate multiple remove paths from all the combinations of the - # signatures of each vertex. - sig_paths = [[]] - broken_flag = False - for sigtxt_node in sigtxt_path: - if isinstance(sigtxt_node, str): - # The vertex has only one signature. - sigtxt_set = {sigtxt_node} - elif isinstance(sigtxt_node, list): - # The vertex has multiple signatures. - sigtxt_set = set(sigtxt_node) - else: - # Assume the format of annotation is verified. There should be no - # invalid case. - assert False - - sig_set = set() - for sigtxt in sigtxt_set: - sig = NormalizeSignature(sigtxt) - if sig is None: - invalid_sigtxts.add(sigtxt) - broken_flag = True - elif not broken_flag: - sig_set.add(sig) - - if broken_flag: - continue - - # Append each signature of the current node to the all previous - # remove paths. - sig_paths = [path + [sig] for path in sig_paths for sig in sig_set] - - if not broken_flag: - # All signatures are normalized. The remove path has no error. - remove_rules.extend(sig_paths) - - return (add_rules, remove_rules, invalid_sigtxts) + (_, path, linenum) = line_infos[0] + order_key = (linenum, path) + + line_texts = [] + for line_info in reversed(line_infos): + if line_info is None: + (function_name, path, linenum) = ("??", "??", 0) + else: + (function_name, path, linenum) = line_info + + line_texts.append( + "{}[{}:{}]".format(function_name, os.path.relpath(path), linenum) + ) + + output = "{}-> {} {:x}\n".format(prefix, line_texts[0], address) + for depth, line_text in enumerate(line_texts[1:]): + output += "{} {}- {}\n".format(prefix, " " * depth, line_text) + + # Remove the last newline character. + return (order_key, output.rstrip("\n")) + + # Analyze disassembly. + try: + disasm_text = subprocess.check_output( + [self.options.objdump, "-d", self.options.elf_path], encoding="utf-8" + ) + except subprocess.CalledProcessError: + raise StackAnalyzerError("objdump failed to disassemble.") + except OSError: + raise StackAnalyzerError("Failed to run objdump.") + + function_map = self.AnalyzeDisassembly(disasm_text) + result = self.ResolveAnnotation(function_map) + (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result + remove_list = self.PreprocessAnnotation( + function_map, add_set, remove_list, eliminated_addrs + ) + cycle_functions = self.AnalyzeCallGraph(function_map, remove_list) + + # Print the results of task-aware stack analysis. + extra_stack_frame = self.annotation.get( + "exception_frame_size", DEFAULT_EXCEPTION_FRAME_SIZE + ) + for task in self.tasklist: + routine_func = function_map[task.routine_address] + print( + "Task: {}, Max size: {} ({} + {}), Allocated size: {}".format( + task.name, + routine_func.stack_max_usage + extra_stack_frame, + routine_func.stack_max_usage, + extra_stack_frame, + task.stack_max_size, + ) + ) + + print("Call Trace:") + max_stack_path = routine_func.stack_max_path + # Assume the routine function is resolved. + assert max_stack_path is not None + for depth, curr_func in enumerate(max_stack_path): + line_info = self.AddressToLine(curr_func.address)[0] + if line_info is None: + (path, linenum) = ("??", 0) + else: + (_, path, linenum) = line_info + + print( + " {} ({}) [{}:{}] {:x}".format( + curr_func.name, + curr_func.stack_frame, + os.path.relpath(path), + linenum, + curr_func.address, + ) + ) + + if depth + 1 < len(max_stack_path): + succ_func = max_stack_path[depth + 1] + text_list = [] + for callsite in curr_func.callsites: + if callsite.callee is succ_func: + indent_prefix = " " + if callsite.address is None: + order_text = ( + None, + "{}-> [annotation]".format(indent_prefix), + ) + else: + order_text = OutputInlineStack( + callsite.address, indent_prefix + ) + + text_list.append(order_text) + + for _, text in sorted(text_list, key=lambda item: item[0]): + print(text) + + print("Unresolved indirect callsites:") + for function in function_map.values(): + indirect_callsites = [] + for callsite in function.callsites: + if callsite.target is None: + indirect_callsites.append(callsite.address) + + if len(indirect_callsites) > 0: + print(" In function {}:".format(function.name)) + text_list = [] + for address in indirect_callsites: + text_list.append(OutputInlineStack(address, " ")) + + for _, text in sorted(text_list, key=lambda item: item[0]): + print(text) + + print("Unresolved annotation signatures:") + for sigtxt, error in failed_sigtxts: + print(" {}: {}".format(sigtxt, error)) + + if len(cycle_functions) > 0: + print("There are cycles in the following function sets:") + for functions in cycle_functions: + print("[{}]".format(", ".join(function.name for function in functions))) - def ResolveAnnotation(self, function_map): - """Resolve annotation. - Args: - function_map: Function map. +def ParseArgs(): + """Parse commandline arguments. Returns: - Set of added call edges, list of remove paths, set of eliminated - callsite addresses, set of annotation signatures which can't be resolved. + options: Namespace from argparse.parse_args(). """ - def StringifySignature(signature): - """Stringify the tupled signature. - - Args: - signature: Tupled signature. - - Returns: - Signature string. - """ - (name, path, linenum) = signature - bracket_text = '' - if path is not None: - path = os.path.relpath(path) - if linenum is None: - bracket_text = '[{}]'.format(path) - else: - bracket_text = '[{}:{}]'.format(path, linenum) - - return name + bracket_text - - (add_rules, remove_rules, invalid_sigtxts) = self.LoadAnnotation() - - signature_set = set() - for src_sig, dst_sigs in add_rules.items(): - signature_set.add(src_sig) - signature_set.update(dst_sigs) - - for remove_sigs in remove_rules: - signature_set.update(remove_sigs) - - # Map signatures to functions. - (signature_map, sig_error_map) = self.MapAnnotation(function_map, - signature_set) - - # Build the indirect callsite map indexed by callsite signature. - indirect_map = collections.defaultdict(set) - for function in function_map.values(): - for callsite in function.callsites: - if callsite.target is not None: - continue - - # Found an indirect callsite. - line_info = self.AddressToLine(callsite.address)[0] - if line_info is None: - continue - - (name, path, linenum) = line_info - result = self.FUNCTION_PREFIX_NAME_RE.match(name) - if result is None: - continue - - indirect_map[(result.group('name').strip(), path, linenum)].add( - (function, callsite.address)) - - # Generate the annotation sets. - add_set = set() - remove_list = list() - eliminated_addrs = set() - - for src_sig, dst_sigs in add_rules.items(): - src_funcs = set(signature_map.get(src_sig, [])) - # Try to match the source signature to the indirect callsites. Even if it - # can't be found in disassembly. - indirect_calls = indirect_map.get(src_sig) - if indirect_calls is not None: - for function, callsite_address in indirect_calls: - # Add the caller of the indirect callsite to the source functions. - src_funcs.add(function) - # Assume each callsite can be represented by a unique address. - eliminated_addrs.add(callsite_address) - - if src_sig in sig_error_map: - # Assume the error is always the not found error. Since the signature - # found in indirect callsite map must be a full signature, it can't - # happen the ambiguous error. - assert sig_error_map[src_sig] == self.ANNOTATION_ERROR_NOTFOUND - # Found in inline stack, remove the not found error. - del sig_error_map[src_sig] - - for dst_sig in dst_sigs: - dst_funcs = signature_map.get(dst_sig) - if dst_funcs is None: - continue - - # Duplicate the call edge for all the same source and destination - # functions. - for src_func in src_funcs: - for dst_func in dst_funcs: - add_set.add((src_func, dst_func)) - - for remove_sigs in remove_rules: - # Since each signature can be mapped to multiple functions, generate - # multiple remove paths from all the combinations of these functions. - remove_paths = [[]] - skip_flag = False - for remove_sig in remove_sigs: - # Transform each signature to the corresponding functions. - remove_funcs = signature_map.get(remove_sig) - if remove_funcs is None: - # There is an unresolved signature in the remove path. Ignore the - # whole broken remove path. - skip_flag = True - break - else: - # Append each function of the current signature to the all previous - # remove paths. - remove_paths = [p + [f] for p in remove_paths for f in remove_funcs] - - if skip_flag: - # Ignore the broken remove path. - continue - - for remove_path in remove_paths: - # Deduplicate the remove paths. - if remove_path not in remove_list: - remove_list.append(remove_path) - - # Format the error messages. - failed_sigtxts = set() - for sigtxt in invalid_sigtxts: - failed_sigtxts.add((sigtxt, self.ANNOTATION_ERROR_INVALID)) - - for sig, error in sig_error_map.items(): - failed_sigtxts.add((StringifySignature(sig), error)) - - return (add_set, remove_list, eliminated_addrs, failed_sigtxts) - - def PreprocessAnnotation(self, function_map, add_set, remove_list, - eliminated_addrs): - """Preprocess the annotation and callgraph. + parser = argparse.ArgumentParser(description="EC firmware stack analyzer.") + parser.add_argument("elf_path", help="the path of EC firmware ELF") + parser.add_argument( + "--export_taskinfo", + required=True, + help="the path of export_taskinfo.so utility", + ) + parser.add_argument( + "--section", + required=True, + help="the section.", + choices=[SECTION_RO, SECTION_RW], + ) + parser.add_argument("--objdump", default="objdump", help="the path of objdump") + parser.add_argument( + "--addr2line", default="addr2line", help="the path of addr2line" + ) + parser.add_argument( + "--annotation", default=None, help="the path of annotation file" + ) + + # TODO(cheyuw): Add an option for dumping stack usage of all functions. + + return parser.parse_args() - Add the missing call edges, and delete simple remove paths (the paths have - one or two vertices) from the function_map. - Eliminate the annotated indirect callsites. - - Return the remaining remove list. +def ParseSymbolText(symbol_text): + """Parse the content of the symbol text. Args: - function_map: Function map. - add_set: Set of missing call edges. - remove_list: List of remove paths. - eliminated_addrs: Set of eliminated callsite addresses. + symbol_text: Text of the symbols. Returns: - List of remaining remove paths. + symbols: Symbol list. """ - def CheckEdge(path): - """Check if all edges of the path are on the callgraph. - - Args: - path: Path. - - Returns: - True or False. - """ - for index in range(len(path) - 1): - if (path[index], path[index + 1]) not in edge_set: - return False - - return True - - for src_func, dst_func in add_set: - # TODO(cheyuw): Support tailing call annotation. - src_func.callsites.append( - Callsite(None, dst_func.address, False, dst_func)) - - # Delete simple remove paths. - remove_simple = set(tuple(p) for p in remove_list if len(p) <= 2) - edge_set = set() - for function in function_map.values(): - cleaned_callsites = [] - for callsite in function.callsites: - if ((callsite.callee,) in remove_simple or - (function, callsite.callee) in remove_simple): - continue - - if callsite.target is None and callsite.address in eliminated_addrs: - continue - - cleaned_callsites.append(callsite) - if callsite.callee is not None: - edge_set.add((function, callsite.callee)) + # Example: "10093064 g F .text 0000015c .hidden hook_task" + symbol_regex = re.compile( + r"^(?P
[0-9A-Fa-f]+)\s+[lwg]\s+" + r"((?P[OF])\s+)?\S+\s+" + r"(?P[0-9A-Fa-f]+)\s+" + r"(\S+\s+)?(?P\S+)$" + ) + + symbols = [] + for line in symbol_text.splitlines(): + line = line.strip() + result = symbol_regex.match(line) + if result is not None: + address = int(result.group("address"), 16) + symtype = result.group("type") + if symtype is None: + symtype = "O" - function.callsites = cleaned_callsites + size = int(result.group("size"), 16) + name = result.group("name") + symbols.append(Symbol(address, symtype, size, name)) - return [p for p in remove_list if len(p) >= 3 and CheckEdge(p)] + return symbols - def AnalyzeCallGraph(self, function_map, remove_list): - """Analyze callgraph. - It will update the max stack size and path for each function. +def ParseRoDataText(rodata_text): + """Parse the content of rodata Args: - function_map: Function map. - remove_list: List of remove paths. + symbol_text: Text of the rodata dump. Returns: - List of function cycles. + symbols: Symbol list. """ - def Traverse(curr_state): - """Traverse the callgraph and calculate the max stack usages of functions. - - Args: - curr_state: Current state. - - Returns: - SCC lowest link. - """ - scc_index = scc_index_counter[0] - scc_index_counter[0] += 1 - scc_index_map[curr_state] = scc_index - scc_lowlink = scc_index - scc_stack.append(curr_state) - # Push the current state in the stack. We can use a set to maintain this - # because the stacked states are unique; otherwise we will find a cycle - # first. - stacked_states.add(curr_state) - - (curr_address, curr_positions) = curr_state - curr_func = function_map[curr_address] - - invalid_flag = False - new_positions = list(curr_positions) - for index, position in enumerate(curr_positions): - remove_path = remove_list[index] - - # The position of each remove path in the state is the length of the - # longest matching path between the prefix of the remove path and the - # suffix of the current traversing path. We maintain this length when - # appending the next callee to the traversing path. And it can be used - # to check if the remove path appears in the traversing path. - - # TODO(cheyuw): Implement KMP algorithm to match remove paths - # efficiently. - if remove_path[position] is curr_func: - # Matches the current function, extend the length. - new_positions[index] = position + 1 - if new_positions[index] == len(remove_path): - # The length of the longest matching path is equal to the length of - # the remove path, which means the suffix of the current traversing - # path matches the remove path. - invalid_flag = True - break - - else: - # We can't get the new longest matching path by extending the previous - # one directly. Fallback to search the new longest matching path. - - # If we can't find any matching path in the following search, reset - # the matching length to 0. - new_positions[index] = 0 - - # We want to find the new longest matching prefix of remove path with - # the suffix of the current traversing path. Because the new longest - # matching path won't be longer than the prevous one now, and part of - # the suffix matches the prefix of remove path, we can get the needed - # suffix from the previous matching prefix of the invalid path. - suffix = remove_path[:position] + [curr_func] - for offset in range(1, len(suffix)): - length = position - offset - if remove_path[:length] == suffix[offset:]: - new_positions[index] = length - break - - new_positions = tuple(new_positions) - - # If the current suffix is invalid, set the max stack usage to 0. - max_stack_usage = 0 - max_callee_state = None - self_loop = False - - if not invalid_flag: - # Max stack usage is at least equal to the stack frame. - max_stack_usage = curr_func.stack_frame - for callsite in curr_func.callsites: - callee = callsite.callee - if callee is None: + # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108 ...H........K... + # 100a7294 00000000 00000000 01000000 ............ + + base_offset = None + offset = None + rodata = [] + for line in rodata_text.splitlines(): + line = line.strip() + space = line.find(" ") + if space < 0: + continue + try: + address = int(line[0:space], 16) + except ValueError: continue - callee_state = (callee.address, new_positions) - if callee_state not in scc_index_map: - # Unvisited state. - scc_lowlink = min(scc_lowlink, Traverse(callee_state)) - elif callee_state in stacked_states: - # The state is shown in the stack. There is a cycle. - sub_stack_usage = 0 - scc_lowlink = min(scc_lowlink, scc_index_map[callee_state]) - if callee_state == curr_state: - self_loop = True - - done_result = done_states.get(callee_state) - if done_result is not None: - # Already done this state and use its result. If the state reaches a - # cycle, reusing the result will cause inaccuracy (the stack usage - # of cycle depends on where the entrance is). But it's fine since we - # can't get accurate stack usage under this situation, and we rely - # on user-provided annotations to break the cycle, after which the - # result will be accurate again. - (sub_stack_usage, _) = done_result - - if callsite.is_tail: - # For tailing call, since the callee reuses the stack frame of the - # caller, choose the larger one directly. - stack_usage = max(curr_func.stack_frame, sub_stack_usage) - else: - stack_usage = curr_func.stack_frame + sub_stack_usage - - if stack_usage > max_stack_usage: - max_stack_usage = stack_usage - max_callee_state = callee_state - - if scc_lowlink == scc_index: - group = [] - while scc_stack[-1] != curr_state: - scc_state = scc_stack.pop() - stacked_states.remove(scc_state) - group.append(scc_state) - - scc_stack.pop() - stacked_states.remove(curr_state) - - # If the cycle is not empty, record it. - if len(group) > 0 or self_loop: - group.append(curr_state) - cycle_groups.append(group) - - # Store the done result. - done_states[curr_state] = (max_stack_usage, max_callee_state) - - if curr_positions == initial_positions: - # If the current state is initial state, we traversed the callgraph by - # using the current function as start point. Update the stack usage of - # the function. - # If the function matches a single vertex remove path, this will set its - # max stack usage to 0, which is not expected (we still calculate its - # max stack usage, but prevent any function from calling it). However, - # all the single vertex remove paths have been preprocessed and removed. - curr_func.stack_max_usage = max_stack_usage - - # Reconstruct the max stack path by traversing the state transitions. - max_stack_path = [curr_func] - callee_state = max_callee_state - while callee_state is not None: - # The first element of state tuple is function address. - max_stack_path.append(function_map[callee_state[0]]) - done_result = done_states.get(callee_state) - # All of the descendants should be done. - assert done_result is not None - (_, callee_state) = done_result - - curr_func.stack_max_path = max_stack_path - - return scc_lowlink - - # The state is the concatenation of the current function address and the - # state of matching position. - initial_positions = (0,) * len(remove_list) - done_states = {} - stacked_states = set() - scc_index_counter = [0] - scc_index_map = {} - scc_stack = [] - cycle_groups = [] - for function in function_map.values(): - if function.stack_max_usage is None: - Traverse((function.address, initial_positions)) - - cycle_functions = [] - for group in cycle_groups: - cycle = set(function_map[state[0]] for state in group) - if cycle not in cycle_functions: - cycle_functions.append(cycle) - - return cycle_functions - - def Analyze(self): - """Run the stack analysis. - - Raises: - StackAnalyzerError: If disassembly fails. - """ - def OutputInlineStack(address, prefix=''): - """Output beautiful inline stack. - - Args: - address: Address. - prefix: Prefix of each line. - - Returns: - Key for sorting, output text - """ - line_infos = self.AddressToLine(address, True) - - if line_infos[0] is None: - order_key = (None, None) - else: - (_, path, linenum) = line_infos[0] - order_key = (linenum, path) - - line_texts = [] - for line_info in reversed(line_infos): - if line_info is None: - (function_name, path, linenum) = ('??', '??', 0) - else: - (function_name, path, linenum) = line_info - - line_texts.append('{}[{}:{}]'.format(function_name, - os.path.relpath(path), - linenum)) - - output = '{}-> {} {:x}\n'.format(prefix, line_texts[0], address) - for depth, line_text in enumerate(line_texts[1:]): - output += '{} {}- {}\n'.format(prefix, ' ' * depth, line_text) - - # Remove the last newline character. - return (order_key, output.rstrip('\n')) - - # Analyze disassembly. - try: - disasm_text = subprocess.check_output([self.options.objdump, - '-d', - self.options.elf_path], - encoding='utf-8') - except subprocess.CalledProcessError: - raise StackAnalyzerError('objdump failed to disassemble.') - except OSError: - raise StackAnalyzerError('Failed to run objdump.') - - function_map = self.AnalyzeDisassembly(disasm_text) - result = self.ResolveAnnotation(function_map) - (add_set, remove_list, eliminated_addrs, failed_sigtxts) = result - remove_list = self.PreprocessAnnotation(function_map, - add_set, - remove_list, - eliminated_addrs) - cycle_functions = self.AnalyzeCallGraph(function_map, remove_list) - - # Print the results of task-aware stack analysis. - extra_stack_frame = self.annotation.get('exception_frame_size', - DEFAULT_EXCEPTION_FRAME_SIZE) - for task in self.tasklist: - routine_func = function_map[task.routine_address] - print('Task: {}, Max size: {} ({} + {}), Allocated size: {}'.format( - task.name, - routine_func.stack_max_usage + extra_stack_frame, - routine_func.stack_max_usage, - extra_stack_frame, - task.stack_max_size)) - - print('Call Trace:') - max_stack_path = routine_func.stack_max_path - # Assume the routine function is resolved. - assert max_stack_path is not None - for depth, curr_func in enumerate(max_stack_path): - line_info = self.AddressToLine(curr_func.address)[0] - if line_info is None: - (path, linenum) = ('??', 0) - else: - (_, path, linenum) = line_info - - print(' {} ({}) [{}:{}] {:x}'.format(curr_func.name, - curr_func.stack_frame, - os.path.relpath(path), - linenum, - curr_func.address)) - - if depth + 1 < len(max_stack_path): - succ_func = max_stack_path[depth + 1] - text_list = [] - for callsite in curr_func.callsites: - if callsite.callee is succ_func: - indent_prefix = ' ' - if callsite.address is None: - order_text = (None, '{}-> [annotation]'.format(indent_prefix)) - else: - order_text = OutputInlineStack(callsite.address, indent_prefix) - - text_list.append(order_text) - - for _, text in sorted(text_list, key=lambda item: item[0]): - print(text) - - print('Unresolved indirect callsites:') - for function in function_map.values(): - indirect_callsites = [] - for callsite in function.callsites: - if callsite.target is None: - indirect_callsites.append(callsite.address) - - if len(indirect_callsites) > 0: - print(' In function {}:'.format(function.name)) - text_list = [] - for address in indirect_callsites: - text_list.append(OutputInlineStack(address, ' ')) - - for _, text in sorted(text_list, key=lambda item: item[0]): - print(text) - - print('Unresolved annotation signatures:') - for sigtxt, error in failed_sigtxts: - print(' {}: {}'.format(sigtxt, error)) - - if len(cycle_functions) > 0: - print('There are cycles in the following function sets:') - for functions in cycle_functions: - print('[{}]'.format(', '.join(function.name for function in functions))) - - -def ParseArgs(): - """Parse commandline arguments. - - Returns: - options: Namespace from argparse.parse_args(). - """ - parser = argparse.ArgumentParser(description="EC firmware stack analyzer.") - parser.add_argument('elf_path', help="the path of EC firmware ELF") - parser.add_argument('--export_taskinfo', required=True, - help="the path of export_taskinfo.so utility") - parser.add_argument('--section', required=True, help='the section.', - choices=[SECTION_RO, SECTION_RW]) - parser.add_argument('--objdump', default='objdump', - help='the path of objdump') - parser.add_argument('--addr2line', default='addr2line', - help='the path of addr2line') - parser.add_argument('--annotation', default=None, - help='the path of annotation file') - - # TODO(cheyuw): Add an option for dumping stack usage of all functions. - - return parser.parse_args() - - -def ParseSymbolText(symbol_text): - """Parse the content of the symbol text. - - Args: - symbol_text: Text of the symbols. - - Returns: - symbols: Symbol list. - """ - # Example: "10093064 g F .text 0000015c .hidden hook_task" - symbol_regex = re.compile(r'^(?P
[0-9A-Fa-f]+)\s+[lwg]\s+' - r'((?P[OF])\s+)?\S+\s+' - r'(?P[0-9A-Fa-f]+)\s+' - r'(\S+\s+)?(?P\S+)$') - - symbols = [] - for line in symbol_text.splitlines(): - line = line.strip() - result = symbol_regex.match(line) - if result is not None: - address = int(result.group('address'), 16) - symtype = result.group('type') - if symtype is None: - symtype = 'O' - - size = int(result.group('size'), 16) - name = result.group('name') - symbols.append(Symbol(address, symtype, size, name)) - - return symbols - - -def ParseRoDataText(rodata_text): - """Parse the content of rodata - - Args: - symbol_text: Text of the rodata dump. - - Returns: - symbols: Symbol list. - """ - # Examples: 8018ab0 00040048 00010000 10020000 4b8e0108 ...H........K... - # 100a7294 00000000 00000000 01000000 ............ - - base_offset = None - offset = None - rodata = [] - for line in rodata_text.splitlines(): - line = line.strip() - space = line.find(' ') - if space < 0: - continue - try: - address = int(line[0:space], 16) - except ValueError: - continue - - if not base_offset: - base_offset = address - offset = address - elif address != offset: - raise StackAnalyzerError('objdump of rodata not contiguous.') + if not base_offset: + base_offset = address + offset = address + elif address != offset: + raise StackAnalyzerError("objdump of rodata not contiguous.") - for i in range(0, 4): - num = line[(space + 1 + i*9):(space + 9 + i*9)] - if len(num.strip()) > 0: - val = int(num, 16) - else: - val = 0 - # TODO(drinkcat): Not all platforms are necessarily big-endian - rodata.append((val & 0x000000ff) << 24 | - (val & 0x0000ff00) << 8 | - (val & 0x00ff0000) >> 8 | - (val & 0xff000000) >> 24) + for i in range(0, 4): + num = line[(space + 1 + i * 9) : (space + 9 + i * 9)] + if len(num.strip()) > 0: + val = int(num, 16) + else: + val = 0 + # TODO(drinkcat): Not all platforms are necessarily big-endian + rodata.append( + (val & 0x000000FF) << 24 + | (val & 0x0000FF00) << 8 + | (val & 0x00FF0000) >> 8 + | (val & 0xFF000000) >> 24 + ) - offset = offset + 4*4 + offset = offset + 4 * 4 - return (base_offset, rodata) + return (base_offset, rodata) def LoadTasklist(section, export_taskinfo, symbols): - """Load the task information. + """Load the task information. - Args: - section: Section (RO | RW). - export_taskinfo: Handle of export_taskinfo.so. - symbols: Symbol list. + Args: + section: Section (RO | RW). + export_taskinfo: Handle of export_taskinfo.so. + symbols: Symbol list. - Returns: - tasklist: Task list. - """ + Returns: + tasklist: Task list. + """ - TaskInfoPointer = ctypes.POINTER(TaskInfo) - taskinfos = TaskInfoPointer() - if section == SECTION_RO: - get_taskinfos_func = export_taskinfo.get_ro_taskinfos - else: - get_taskinfos_func = export_taskinfo.get_rw_taskinfos + TaskInfoPointer = ctypes.POINTER(TaskInfo) + taskinfos = TaskInfoPointer() + if section == SECTION_RO: + get_taskinfos_func = export_taskinfo.get_ro_taskinfos + else: + get_taskinfos_func = export_taskinfo.get_rw_taskinfos - taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos)) + taskinfo_num = get_taskinfos_func(ctypes.pointer(taskinfos)) - tasklist = [] - for index in range(taskinfo_num): - taskinfo = taskinfos[index] - tasklist.append(Task(taskinfo.name.decode('utf-8'), - taskinfo.routine.decode('utf-8'), - taskinfo.stack_size)) + tasklist = [] + for index in range(taskinfo_num): + taskinfo = taskinfos[index] + tasklist.append( + Task( + taskinfo.name.decode("utf-8"), + taskinfo.routine.decode("utf-8"), + taskinfo.stack_size, + ) + ) - # Resolve routine address for each task. It's more efficient to resolve all - # routine addresses of tasks together. - routine_map = dict((task.routine_name, None) for task in tasklist) + # Resolve routine address for each task. It's more efficient to resolve all + # routine addresses of tasks together. + routine_map = dict((task.routine_name, None) for task in tasklist) - for symbol in symbols: - # Resolve task routine address. - if symbol.name in routine_map: - # Assume the symbol of routine is unique. - assert routine_map[symbol.name] is None - routine_map[symbol.name] = symbol.address + for symbol in symbols: + # Resolve task routine address. + if symbol.name in routine_map: + # Assume the symbol of routine is unique. + assert routine_map[symbol.name] is None + routine_map[symbol.name] = symbol.address - for task in tasklist: - address = routine_map[task.routine_name] - # Assume we have resolved all routine addresses. - assert address is not None - task.routine_address = address + for task in tasklist: + address = routine_map[task.routine_name] + # Assume we have resolved all routine addresses. + assert address is not None + task.routine_address = address - return tasklist + return tasklist def main(): - """Main function.""" - try: - options = ParseArgs() - - # Load annotation config. - if options.annotation is None: - annotation = {} - elif not os.path.exists(options.annotation): - print('Warning: Annotation file {} does not exist.' - .format(options.annotation)) - annotation = {} - else: - try: - with open(options.annotation, 'r') as annotation_file: - annotation = yaml.safe_load(annotation_file) - - except yaml.YAMLError: - raise StackAnalyzerError('Failed to parse annotation file {}.' - .format(options.annotation)) - except IOError: - raise StackAnalyzerError('Failed to open annotation file {}.' - .format(options.annotation)) - - # TODO(cheyuw): Do complete annotation format verification. - if not isinstance(annotation, dict): - raise StackAnalyzerError('Invalid annotation file {}.' - .format(options.annotation)) - - # Generate and parse the symbols. + """Main function.""" try: - symbol_text = subprocess.check_output([options.objdump, - '-t', - options.elf_path], - encoding='utf-8') - rodata_text = subprocess.check_output([options.objdump, - '-s', - '-j', '.rodata', - options.elf_path], - encoding='utf-8') - except subprocess.CalledProcessError: - raise StackAnalyzerError('objdump failed to dump symbol table or rodata.') - except OSError: - raise StackAnalyzerError('Failed to run objdump.') - - symbols = ParseSymbolText(symbol_text) - rodata = ParseRoDataText(rodata_text) - - # Load the tasklist. - try: - export_taskinfo = ctypes.CDLL(options.export_taskinfo) - except OSError: - raise StackAnalyzerError('Failed to load export_taskinfo.') - - tasklist = LoadTasklist(options.section, export_taskinfo, symbols) - - analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation) - analyzer.Analyze() - except StackAnalyzerError as e: - print('Error: {}'.format(e)) - - -if __name__ == '__main__': - main() + options = ParseArgs() + + # Load annotation config. + if options.annotation is None: + annotation = {} + elif not os.path.exists(options.annotation): + print( + "Warning: Annotation file {} does not exist.".format(options.annotation) + ) + annotation = {} + else: + try: + with open(options.annotation, "r") as annotation_file: + annotation = yaml.safe_load(annotation_file) + + except yaml.YAMLError: + raise StackAnalyzerError( + "Failed to parse annotation file {}.".format(options.annotation) + ) + except IOError: + raise StackAnalyzerError( + "Failed to open annotation file {}.".format(options.annotation) + ) + + # TODO(cheyuw): Do complete annotation format verification. + if not isinstance(annotation, dict): + raise StackAnalyzerError( + "Invalid annotation file {}.".format(options.annotation) + ) + + # Generate and parse the symbols. + try: + symbol_text = subprocess.check_output( + [options.objdump, "-t", options.elf_path], encoding="utf-8" + ) + rodata_text = subprocess.check_output( + [options.objdump, "-s", "-j", ".rodata", options.elf_path], + encoding="utf-8", + ) + except subprocess.CalledProcessError: + raise StackAnalyzerError("objdump failed to dump symbol table or rodata.") + except OSError: + raise StackAnalyzerError("Failed to run objdump.") + + symbols = ParseSymbolText(symbol_text) + rodata = ParseRoDataText(rodata_text) + + # Load the tasklist. + try: + export_taskinfo = ctypes.CDLL(options.export_taskinfo) + except OSError: + raise StackAnalyzerError("Failed to load export_taskinfo.") + + tasklist = LoadTasklist(options.section, export_taskinfo, symbols) + + analyzer = StackAnalyzer(options, symbols, rodata, tasklist, annotation) + analyzer.Analyze() + except StackAnalyzerError as e: + print("Error: {}".format(e)) + + +if __name__ == "__main__": + main() diff --git a/extra/stack_analyzer/stack_analyzer_unittest.py b/extra/stack_analyzer/stack_analyzer_unittest.py index c36fa9da45..ad2837a8a4 100755 --- a/extra/stack_analyzer/stack_analyzer_unittest.py +++ b/extra/stack_analyzer/stack_analyzer_unittest.py @@ -11,820 +11,924 @@ from __future__ import print_function -import mock import os import subprocess import unittest +import mock import stack_analyzer as sa class ObjectTest(unittest.TestCase): - """Tests for classes of basic objects.""" - - def testTask(self): - task_a = sa.Task('a', 'a_task', 1234) - task_b = sa.Task('b', 'b_task', 5678, 0x1000) - self.assertEqual(task_a, task_a) - self.assertNotEqual(task_a, task_b) - self.assertNotEqual(task_a, None) - - def testSymbol(self): - symbol_a = sa.Symbol(0x1234, 'F', 32, 'a') - symbol_b = sa.Symbol(0x234, 'O', 42, 'b') - self.assertEqual(symbol_a, symbol_a) - self.assertNotEqual(symbol_a, symbol_b) - self.assertNotEqual(symbol_a, None) - - def testCallsite(self): - callsite_a = sa.Callsite(0x1002, 0x3000, False) - callsite_b = sa.Callsite(0x1002, 0x3000, True) - self.assertEqual(callsite_a, callsite_a) - self.assertNotEqual(callsite_a, callsite_b) - self.assertNotEqual(callsite_a, None) - - def testFunction(self): - func_a = sa.Function(0x100, 'a', 0, []) - func_b = sa.Function(0x200, 'b', 0, []) - self.assertEqual(func_a, func_a) - self.assertNotEqual(func_a, func_b) - self.assertNotEqual(func_a, None) + """Tests for classes of basic objects.""" + + def testTask(self): + task_a = sa.Task("a", "a_task", 1234) + task_b = sa.Task("b", "b_task", 5678, 0x1000) + self.assertEqual(task_a, task_a) + self.assertNotEqual(task_a, task_b) + self.assertNotEqual(task_a, None) + + def testSymbol(self): + symbol_a = sa.Symbol(0x1234, "F", 32, "a") + symbol_b = sa.Symbol(0x234, "O", 42, "b") + self.assertEqual(symbol_a, symbol_a) + self.assertNotEqual(symbol_a, symbol_b) + self.assertNotEqual(symbol_a, None) + + def testCallsite(self): + callsite_a = sa.Callsite(0x1002, 0x3000, False) + callsite_b = sa.Callsite(0x1002, 0x3000, True) + self.assertEqual(callsite_a, callsite_a) + self.assertNotEqual(callsite_a, callsite_b) + self.assertNotEqual(callsite_a, None) + + def testFunction(self): + func_a = sa.Function(0x100, "a", 0, []) + func_b = sa.Function(0x200, "b", 0, []) + self.assertEqual(func_a, func_a) + self.assertNotEqual(func_a, func_b) + self.assertNotEqual(func_a, None) class ArmAnalyzerTest(unittest.TestCase): - """Tests for class ArmAnalyzer.""" - - def AppendConditionCode(self, opcodes): - rets = [] - for opcode in opcodes: - rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES) - - return rets - - def testInstructionMatching(self): - jump_list = self.AppendConditionCode(['b', 'bx']) - jump_list += (list(opcode + '.n' for opcode in jump_list) + - list(opcode + '.w' for opcode in jump_list)) - for opcode in jump_list: - self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode)) - - self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('bl')) - self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match('blx')) - - cbz_list = ['cbz', 'cbnz', 'cbz.n', 'cbnz.n', 'cbz.w', 'cbnz.w'] - for opcode in cbz_list: - self.assertIsNotNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode)) - - self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match('cbn')) - - call_list = self.AppendConditionCode(['bl', 'blx']) - call_list += list(opcode + '.n' for opcode in call_list) - for opcode in call_list: - self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode)) - - self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match('ble')) - - result = sa.ArmAnalyzer.CALL_OPERAND_RE.match('53f90 ') - self.assertIsNotNone(result) - self.assertEqual(result.group(1), '53f90') - self.assertEqual(result.group(2), 'get_time+0x18') - - result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match('r6, 53f90 ') - self.assertIsNotNone(result) - self.assertEqual(result.group(1), '53f90') - self.assertEqual(result.group(2), 'get+0x0') - - self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('push')) - self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match('pushal')) - self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('stmdb')) - self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match('lstm')) - self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub')) - self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs')) - self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subw')) - self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('sub.w')) - self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match('subs.w')) - - result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, sp, #1668 ; 0x684') - self.assertIsNotNone(result) - self.assertEqual(result.group(1), '1668') - result = sa.ArmAnalyzer.SUB_OPERAND_RE.match('sp, #1668') - self.assertIsNotNone(result) - self.assertEqual(result.group(1), '1668') - self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match('sl, #1668')) - - def testAnalyzeFunction(self): - analyzer = sa.ArmAnalyzer() - symbol = sa.Symbol(0x10, 'F', 0x100, 'foo') - instructions = [ - (0x10, 'push', '{r4, r5, r6, r7, lr}'), - (0x12, 'subw', 'sp, sp, #16 ; 0x10'), - (0x16, 'movs', 'lr, r1'), - (0x18, 'beq.n', '26 '), - (0x1a, 'bl', '30 '), - (0x1e, 'bl', 'deadbeef '), - (0x22, 'blx', '0 '), - (0x26, 'push', '{r1}'), - (0x28, 'stmdb', 'sp!, {r4, r5, r6, r7, r8, r9, lr}'), - (0x2c, 'stmdb', 'sp!, {r4}'), - (0x30, 'stmdb', 'sp, {r4}'), - (0x34, 'bx.n', '10 '), - (0x36, 'bx.n', 'r3'), - (0x38, 'ldr', 'pc, [r10]'), - ] - (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions) - self.assertEqual(size, 72) - expect_callsites = [sa.Callsite(0x1e, 0xdeadbeef, False), - sa.Callsite(0x22, 0x0, False), - sa.Callsite(0x34, 0x10, True), - sa.Callsite(0x36, None, True), - sa.Callsite(0x38, None, True)] - self.assertEqual(callsites, expect_callsites) + """Tests for class ArmAnalyzer.""" + + def AppendConditionCode(self, opcodes): + rets = [] + for opcode in opcodes: + rets.extend(opcode + cc for cc in sa.ArmAnalyzer.CONDITION_CODES) + + return rets + + def testInstructionMatching(self): + jump_list = self.AppendConditionCode(["b", "bx"]) + jump_list += list(opcode + ".n" for opcode in jump_list) + list( + opcode + ".w" for opcode in jump_list + ) + for opcode in jump_list: + self.assertIsNotNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match(opcode)) + + self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("bl")) + self.assertIsNone(sa.ArmAnalyzer.JUMP_OPCODE_RE.match("blx")) + + cbz_list = ["cbz", "cbnz", "cbz.n", "cbnz.n", "cbz.w", "cbnz.w"] + for opcode in cbz_list: + self.assertIsNotNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match(opcode)) + + self.assertIsNone(sa.ArmAnalyzer.CBZ_CBNZ_OPCODE_RE.match("cbn")) + + call_list = self.AppendConditionCode(["bl", "blx"]) + call_list += list(opcode + ".n" for opcode in call_list) + for opcode in call_list: + self.assertIsNotNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match(opcode)) + + self.assertIsNone(sa.ArmAnalyzer.CALL_OPCODE_RE.match("ble")) + + result = sa.ArmAnalyzer.CALL_OPERAND_RE.match("53f90 ") + self.assertIsNotNone(result) + self.assertEqual(result.group(1), "53f90") + self.assertEqual(result.group(2), "get_time+0x18") + + result = sa.ArmAnalyzer.CBZ_CBNZ_OPERAND_RE.match("r6, 53f90 ") + self.assertIsNotNone(result) + self.assertEqual(result.group(1), "53f90") + self.assertEqual(result.group(2), "get+0x0") + + self.assertIsNotNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("push")) + self.assertIsNone(sa.ArmAnalyzer.PUSH_OPCODE_RE.match("pushal")) + self.assertIsNotNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("stmdb")) + self.assertIsNone(sa.ArmAnalyzer.STM_OPCODE_RE.match("lstm")) + self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub")) + self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs")) + self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subw")) + self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("sub.w")) + self.assertIsNotNone(sa.ArmAnalyzer.SUB_OPCODE_RE.match("subs.w")) + + result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, sp, #1668 ; 0x684") + self.assertIsNotNone(result) + self.assertEqual(result.group(1), "1668") + result = sa.ArmAnalyzer.SUB_OPERAND_RE.match("sp, #1668") + self.assertIsNotNone(result) + self.assertEqual(result.group(1), "1668") + self.assertIsNone(sa.ArmAnalyzer.SUB_OPERAND_RE.match("sl, #1668")) + + def testAnalyzeFunction(self): + analyzer = sa.ArmAnalyzer() + symbol = sa.Symbol(0x10, "F", 0x100, "foo") + instructions = [ + (0x10, "push", "{r4, r5, r6, r7, lr}"), + (0x12, "subw", "sp, sp, #16 ; 0x10"), + (0x16, "movs", "lr, r1"), + (0x18, "beq.n", "26 "), + (0x1A, "bl", "30 "), + (0x1E, "bl", "deadbeef "), + (0x22, "blx", "0 "), + (0x26, "push", "{r1}"), + (0x28, "stmdb", "sp!, {r4, r5, r6, r7, r8, r9, lr}"), + (0x2C, "stmdb", "sp!, {r4}"), + (0x30, "stmdb", "sp, {r4}"), + (0x34, "bx.n", "10 "), + (0x36, "bx.n", "r3"), + (0x38, "ldr", "pc, [r10]"), + ] + (size, callsites) = analyzer.AnalyzeFunction(symbol, instructions) + self.assertEqual(size, 72) + expect_callsites = [ + sa.Callsite(0x1E, 0xDEADBEEF, False), + sa.Callsite(0x22, 0x0, False), + sa.Callsite(0x34, 0x10, True), + sa.Callsite(0x36, None, True), + sa.Callsite(0x38, None, True), + ] + self.assertEqual(callsites, expect_callsites) class StackAnalyzerTest(unittest.TestCase): - """Tests for class StackAnalyzer.""" - - def setUp(self): - symbols = [sa.Symbol(0x1000, 'F', 0x15C, 'hook_task'), - sa.Symbol(0x2000, 'F', 0x51C, 'console_task'), - sa.Symbol(0x3200, 'O', 0x124, '__just_data'), - sa.Symbol(0x4000, 'F', 0x11C, 'touchpad_calc'), - sa.Symbol(0x5000, 'F', 0x12C, 'touchpad_calc.constprop.42'), - sa.Symbol(0x12000, 'F', 0x13C, 'trackpad_range'), - sa.Symbol(0x13000, 'F', 0x200, 'inlined_mul'), - sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul'), - sa.Symbol(0x13100, 'F', 0x200, 'inlined_mul_alias'), - sa.Symbol(0x20000, 'O', 0x0, '__array'), - sa.Symbol(0x20010, 'O', 0x0, '__array_end'), - ] - tasklist = [sa.Task('HOOKS', 'hook_task', 2048, 0x1000), - sa.Task('CONSOLE', 'console_task', 460, 0x2000)] - # Array at 0x20000 that contains pointers to hook_task and console_task, - # with stride=8, offset=4 - rodata = (0x20000, [ 0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000 ]) - options = mock.MagicMock(elf_path='./ec.RW.elf', - export_taskinfo='fake', - section='RW', - objdump='objdump', - addr2line='addr2line', - annotation=None) - self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {}) - - def testParseSymbolText(self): - symbol_text = ( - '0 g F .text e8 Foo\n' - '0000dead w F .text 000000e8 .hidden Bar\n' - 'deadbeef l O .bss 00000004 .hidden Woooo\n' - 'deadbee g O .rodata 00000008 __Hooo_ooo\n' - 'deadbee g .rodata 00000000 __foo_doo_coo_end\n' - ) - symbols = sa.ParseSymbolText(symbol_text) - expect_symbols = [sa.Symbol(0x0, 'F', 0xe8, 'Foo'), - sa.Symbol(0xdead, 'F', 0xe8, 'Bar'), - sa.Symbol(0xdeadbeef, 'O', 0x4, 'Woooo'), - sa.Symbol(0xdeadbee, 'O', 0x8, '__Hooo_ooo'), - sa.Symbol(0xdeadbee, 'O', 0x0, '__foo_doo_coo_end')] - self.assertEqual(symbols, expect_symbols) - - def testParseRoData(self): - rodata_text = ( - '\n' - 'Contents of section .rodata:\n' - ' 20000 dead1000 00100000 dead2000 00200000 He..f.He..s.\n' - ) - rodata = sa.ParseRoDataText(rodata_text) - expect_rodata = (0x20000, - [ 0x0010adde, 0x00001000, 0x0020adde, 0x00002000 ]) - self.assertEqual(rodata, expect_rodata) - - def testLoadTasklist(self): - def tasklist_to_taskinfos(pointer, tasklist): - taskinfos = [] - for task in tasklist: - taskinfos.append(sa.TaskInfo(name=task.name.encode('utf-8'), - routine=task.routine_name.encode('utf-8'), - stack_size=task.stack_max_size)) - - TaskInfoArray = sa.TaskInfo * len(taskinfos) - pointer.contents.contents = TaskInfoArray(*taskinfos) - return len(taskinfos) - - def ro_taskinfos(pointer): - return tasklist_to_taskinfos(pointer, expect_ro_tasklist) - - def rw_taskinfos(pointer): - return tasklist_to_taskinfos(pointer, expect_rw_tasklist) - - expect_ro_tasklist = [ - sa.Task('HOOKS', 'hook_task', 2048, 0x1000), - ] - - expect_rw_tasklist = [ - sa.Task('HOOKS', 'hook_task', 2048, 0x1000), - sa.Task('WOOKS', 'hook_task', 4096, 0x1000), - sa.Task('CONSOLE', 'console_task', 460, 0x2000), - ] - - export_taskinfo = mock.MagicMock( - get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos), - get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos)) - - tasklist = sa.LoadTasklist('RO', export_taskinfo, self.analyzer.symbols) - self.assertEqual(tasklist, expect_ro_tasklist) - tasklist = sa.LoadTasklist('RW', export_taskinfo, self.analyzer.symbols) - self.assertEqual(tasklist, expect_rw_tasklist) - - def testResolveAnnotation(self): - self.analyzer.annotation = {} - (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() - self.assertEqual(add_rules, {}) - self.assertEqual(remove_rules, []) - self.assertEqual(invalid_sigtxts, set()) - - self.analyzer.annotation = {'add': None, 'remove': None} - (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() - self.assertEqual(add_rules, {}) - self.assertEqual(remove_rules, []) - self.assertEqual(invalid_sigtxts, set()) - - self.analyzer.annotation = { - 'add': None, - 'remove': [ - [['a', 'b'], ['0', '[', '2'], 'x'], - [['a', 'b[x:3]'], ['0', '1', '2'], 'x'], - ], - } - (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() - self.assertEqual(add_rules, {}) - self.assertEqual(list.sort(remove_rules), list.sort([ - [('a', None, None), ('1', None, None), ('x', None, None)], - [('a', None, None), ('0', None, None), ('x', None, None)], - [('a', None, None), ('2', None, None), ('x', None, None)], - [('b', os.path.abspath('x'), 3), ('1', None, None), ('x', None, None)], - [('b', os.path.abspath('x'), 3), ('0', None, None), ('x', None, None)], - [('b', os.path.abspath('x'), 3), ('2', None, None), ('x', None, None)], - ])) - self.assertEqual(invalid_sigtxts, {'['}) - - self.analyzer.annotation = { - 'add': { - 'touchpad_calc': [ dict(name='__array', stride=8, offset=4) ], + """Tests for class StackAnalyzer.""" + + def setUp(self): + symbols = [ + sa.Symbol(0x1000, "F", 0x15C, "hook_task"), + sa.Symbol(0x2000, "F", 0x51C, "console_task"), + sa.Symbol(0x3200, "O", 0x124, "__just_data"), + sa.Symbol(0x4000, "F", 0x11C, "touchpad_calc"), + sa.Symbol(0x5000, "F", 0x12C, "touchpad_calc.constprop.42"), + sa.Symbol(0x12000, "F", 0x13C, "trackpad_range"), + sa.Symbol(0x13000, "F", 0x200, "inlined_mul"), + sa.Symbol(0x13100, "F", 0x200, "inlined_mul"), + sa.Symbol(0x13100, "F", 0x200, "inlined_mul_alias"), + sa.Symbol(0x20000, "O", 0x0, "__array"), + sa.Symbol(0x20010, "O", 0x0, "__array_end"), + ] + tasklist = [ + sa.Task("HOOKS", "hook_task", 2048, 0x1000), + sa.Task("CONSOLE", "console_task", 460, 0x2000), + ] + # Array at 0x20000 that contains pointers to hook_task and console_task, + # with stride=8, offset=4 + rodata = (0x20000, [0xDEAD1000, 0x00001000, 0xDEAD2000, 0x00002000]) + options = mock.MagicMock( + elf_path="./ec.RW.elf", + export_taskinfo="fake", + section="RW", + objdump="objdump", + addr2line="addr2line", + annotation=None, + ) + self.analyzer = sa.StackAnalyzer(options, symbols, rodata, tasklist, {}) + + def testParseSymbolText(self): + symbol_text = ( + "0 g F .text e8 Foo\n" + "0000dead w F .text 000000e8 .hidden Bar\n" + "deadbeef l O .bss 00000004 .hidden Woooo\n" + "deadbee g O .rodata 00000008 __Hooo_ooo\n" + "deadbee g .rodata 00000000 __foo_doo_coo_end\n" + ) + symbols = sa.ParseSymbolText(symbol_text) + expect_symbols = [ + sa.Symbol(0x0, "F", 0xE8, "Foo"), + sa.Symbol(0xDEAD, "F", 0xE8, "Bar"), + sa.Symbol(0xDEADBEEF, "O", 0x4, "Woooo"), + sa.Symbol(0xDEADBEE, "O", 0x8, "__Hooo_ooo"), + sa.Symbol(0xDEADBEE, "O", 0x0, "__foo_doo_coo_end"), + ] + self.assertEqual(symbols, expect_symbols) + + def testParseRoData(self): + rodata_text = ( + "\n" + "Contents of section .rodata:\n" + " 20000 dead1000 00100000 dead2000 00200000 He..f.He..s.\n" + ) + rodata = sa.ParseRoDataText(rodata_text) + expect_rodata = (0x20000, [0x0010ADDE, 0x00001000, 0x0020ADDE, 0x00002000]) + self.assertEqual(rodata, expect_rodata) + + def testLoadTasklist(self): + def tasklist_to_taskinfos(pointer, tasklist): + taskinfos = [] + for task in tasklist: + taskinfos.append( + sa.TaskInfo( + name=task.name.encode("utf-8"), + routine=task.routine_name.encode("utf-8"), + stack_size=task.stack_max_size, + ) + ) + + TaskInfoArray = sa.TaskInfo * len(taskinfos) + pointer.contents.contents = TaskInfoArray(*taskinfos) + return len(taskinfos) + + def ro_taskinfos(pointer): + return tasklist_to_taskinfos(pointer, expect_ro_tasklist) + + def rw_taskinfos(pointer): + return tasklist_to_taskinfos(pointer, expect_rw_tasklist) + + expect_ro_tasklist = [ + sa.Task("HOOKS", "hook_task", 2048, 0x1000), + ] + + expect_rw_tasklist = [ + sa.Task("HOOKS", "hook_task", 2048, 0x1000), + sa.Task("WOOKS", "hook_task", 4096, 0x1000), + sa.Task("CONSOLE", "console_task", 460, 0x2000), + ] + + export_taskinfo = mock.MagicMock( + get_ro_taskinfos=mock.MagicMock(side_effect=ro_taskinfos), + get_rw_taskinfos=mock.MagicMock(side_effect=rw_taskinfos), + ) + + tasklist = sa.LoadTasklist("RO", export_taskinfo, self.analyzer.symbols) + self.assertEqual(tasklist, expect_ro_tasklist) + tasklist = sa.LoadTasklist("RW", export_taskinfo, self.analyzer.symbols) + self.assertEqual(tasklist, expect_rw_tasklist) + + def testResolveAnnotation(self): + self.analyzer.annotation = {} + (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() + self.assertEqual(add_rules, {}) + self.assertEqual(remove_rules, []) + self.assertEqual(invalid_sigtxts, set()) + + self.analyzer.annotation = {"add": None, "remove": None} + (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() + self.assertEqual(add_rules, {}) + self.assertEqual(remove_rules, []) + self.assertEqual(invalid_sigtxts, set()) + + self.analyzer.annotation = { + "add": None, + "remove": [ + [["a", "b"], ["0", "[", "2"], "x"], + [["a", "b[x:3]"], ["0", "1", "2"], "x"], + ], + } + (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() + self.assertEqual(add_rules, {}) + self.assertEqual( + list.sort(remove_rules), + list.sort( + [ + [("a", None, None), ("1", None, None), ("x", None, None)], + [("a", None, None), ("0", None, None), ("x", None, None)], + [("a", None, None), ("2", None, None), ("x", None, None)], + [ + ("b", os.path.abspath("x"), 3), + ("1", None, None), + ("x", None, None), + ], + [ + ("b", os.path.abspath("x"), 3), + ("0", None, None), + ("x", None, None), + ], + [ + ("b", os.path.abspath("x"), 3), + ("2", None, None), + ("x", None, None), + ], + ] + ), + ) + self.assertEqual(invalid_sigtxts, {"["}) + + self.analyzer.annotation = { + "add": { + "touchpad_calc": [dict(name="__array", stride=8, offset=4)], + } + } + (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() + self.assertEqual( + add_rules, + { + ("touchpad_calc", None, None): set( + [("console_task", None, None), ("hook_task", None, None)] + ) + }, + ) + + funcs = { + 0x1000: sa.Function(0x1000, "hook_task", 0, []), + 0x2000: sa.Function(0x2000, "console_task", 0, []), + 0x4000: sa.Function(0x4000, "touchpad_calc", 0, []), + 0x5000: sa.Function(0x5000, "touchpad_calc.constprop.42", 0, []), + 0x13000: sa.Function(0x13000, "inlined_mul", 0, []), + 0x13100: sa.Function(0x13100, "inlined_mul", 0, []), + } + funcs[0x1000].callsites = [sa.Callsite(0x1002, None, False, None)] + # Set address_to_line_cache to fake the results of addr2line. + self.analyzer.address_to_line_cache = { + (0x1000, False): [("hook_task", os.path.abspath("a.c"), 10)], + (0x1002, False): [("toot_calc", os.path.abspath("t.c"), 1234)], + (0x2000, False): [("console_task", os.path.abspath("b.c"), 20)], + (0x4000, False): [("toudhpad_calc", os.path.abspath("a.c"), 20)], + (0x5000, False): [ + ("touchpad_calc.constprop.42", os.path.abspath("b.c"), 40) + ], + (0x12000, False): [("trackpad_range", os.path.abspath("t.c"), 10)], + (0x13000, False): [("inlined_mul", os.path.abspath("x.c"), 12)], + (0x13100, False): [("inlined_mul", os.path.abspath("x.c"), 12)], + } + self.analyzer.annotation = { + "add": { + "hook_task.lto.573": ["touchpad_calc.lto.2501[a.c]"], + "console_task": ["touchpad_calc[b.c]", "inlined_mul_alias"], + "hook_task[q.c]": ["hook_task"], + "inlined_mul[x.c]": ["inlined_mul"], + "toot_calc[t.c:1234]": ["hook_task"], + }, + "remove": [ + ["touchpad?calc["], + "touchpad_calc", + ["touchpad_calc[a.c]"], + ["task_unk[a.c]"], + ["touchpad_calc[x/a.c]"], + ["trackpad_range"], + ["inlined_mul"], + ["inlined_mul", "console_task", "touchpad_calc[a.c]"], + ["inlined_mul", "inlined_mul_alias", "console_task"], + ["inlined_mul", "inlined_mul_alias", "console_task"], + ], + } + (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() + self.assertEqual(invalid_sigtxts, {"touchpad?calc["}) + + signature_set = set() + for src_sig, dst_sigs in add_rules.items(): + signature_set.add(src_sig) + signature_set.update(dst_sigs) + + for remove_sigs in remove_rules: + signature_set.update(remove_sigs) + + (signature_map, failed_sigs) = self.analyzer.MapAnnotation(funcs, signature_set) + result = self.analyzer.ResolveAnnotation(funcs) + (add_set, remove_list, eliminated_addrs, failed_sigs) = result + + expect_signature_map = { + ("hook_task", None, None): {funcs[0x1000]}, + ("touchpad_calc", os.path.abspath("a.c"), None): {funcs[0x4000]}, + ("touchpad_calc", os.path.abspath("b.c"), None): {funcs[0x5000]}, + ("console_task", None, None): {funcs[0x2000]}, + ("inlined_mul_alias", None, None): {funcs[0x13100]}, + ("inlined_mul", os.path.abspath("x.c"), None): { + funcs[0x13000], + funcs[0x13100], + }, + ("inlined_mul", None, None): {funcs[0x13000], funcs[0x13100]}, + } + self.assertEqual(len(signature_map), len(expect_signature_map)) + for sig, funclist in signature_map.items(): + self.assertEqual(set(funclist), expect_signature_map[sig]) + + self.assertEqual( + add_set, + { + (funcs[0x1000], funcs[0x4000]), + (funcs[0x1000], funcs[0x1000]), + (funcs[0x2000], funcs[0x5000]), + (funcs[0x2000], funcs[0x13100]), + (funcs[0x13000], funcs[0x13000]), + (funcs[0x13000], funcs[0x13100]), + (funcs[0x13100], funcs[0x13000]), + (funcs[0x13100], funcs[0x13100]), + }, + ) + expect_remove_list = [ + [funcs[0x4000]], + [funcs[0x13000]], + [funcs[0x13100]], + [funcs[0x13000], funcs[0x2000], funcs[0x4000]], + [funcs[0x13100], funcs[0x2000], funcs[0x4000]], + [funcs[0x13000], funcs[0x13100], funcs[0x2000]], + [funcs[0x13100], funcs[0x13100], funcs[0x2000]], + ] + self.assertEqual(len(remove_list), len(expect_remove_list)) + for remove_path in remove_list: + self.assertTrue(remove_path in expect_remove_list) + + self.assertEqual(eliminated_addrs, {0x1002}) + self.assertEqual( + failed_sigs, + { + ("touchpad?calc[", sa.StackAnalyzer.ANNOTATION_ERROR_INVALID), + ("touchpad_calc", sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS), + ("hook_task[q.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), + ("task_unk[a.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), + ("touchpad_calc[x/a.c]", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), + ("trackpad_range", sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), + }, + ) + + def testPreprocessAnnotation(self): + funcs = { + 0x1000: sa.Function(0x1000, "hook_task", 0, []), + 0x2000: sa.Function(0x2000, "console_task", 0, []), + 0x4000: sa.Function(0x4000, "touchpad_calc", 0, []), + } + funcs[0x1000].callsites = [sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])] + funcs[0x2000].callsites = [ + sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]), + sa.Callsite(0x2006, None, True, None), + ] + add_set = { + (funcs[0x2000], funcs[0x2000]), + (funcs[0x2000], funcs[0x4000]), + (funcs[0x4000], funcs[0x1000]), + (funcs[0x4000], funcs[0x2000]), } - } - (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() - self.assertEqual(add_rules, { - ('touchpad_calc', None, None): - set([('console_task', None, None), ('hook_task', None, None)])}) - - funcs = { - 0x1000: sa.Function(0x1000, 'hook_task', 0, []), - 0x2000: sa.Function(0x2000, 'console_task', 0, []), - 0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []), - 0x5000: sa.Function(0x5000, 'touchpad_calc.constprop.42', 0, []), - 0x13000: sa.Function(0x13000, 'inlined_mul', 0, []), - 0x13100: sa.Function(0x13100, 'inlined_mul', 0, []), - } - funcs[0x1000].callsites = [ - sa.Callsite(0x1002, None, False, None)] - # Set address_to_line_cache to fake the results of addr2line. - self.analyzer.address_to_line_cache = { - (0x1000, False): [('hook_task', os.path.abspath('a.c'), 10)], - (0x1002, False): [('toot_calc', os.path.abspath('t.c'), 1234)], - (0x2000, False): [('console_task', os.path.abspath('b.c'), 20)], - (0x4000, False): [('toudhpad_calc', os.path.abspath('a.c'), 20)], - (0x5000, False): [ - ('touchpad_calc.constprop.42', os.path.abspath('b.c'), 40)], - (0x12000, False): [('trackpad_range', os.path.abspath('t.c'), 10)], - (0x13000, False): [('inlined_mul', os.path.abspath('x.c'), 12)], - (0x13100, False): [('inlined_mul', os.path.abspath('x.c'), 12)], - } - self.analyzer.annotation = { - 'add': { - 'hook_task.lto.573': ['touchpad_calc.lto.2501[a.c]'], - 'console_task': ['touchpad_calc[b.c]', 'inlined_mul_alias'], - 'hook_task[q.c]': ['hook_task'], - 'inlined_mul[x.c]': ['inlined_mul'], - 'toot_calc[t.c:1234]': ['hook_task'], - }, - 'remove': [ - ['touchpad?calc['], - 'touchpad_calc', - ['touchpad_calc[a.c]'], - ['task_unk[a.c]'], - ['touchpad_calc[x/a.c]'], - ['trackpad_range'], - ['inlined_mul'], - ['inlined_mul', 'console_task', 'touchpad_calc[a.c]'], - ['inlined_mul', 'inlined_mul_alias', 'console_task'], - ['inlined_mul', 'inlined_mul_alias', 'console_task'], - ], - } - (add_rules, remove_rules, invalid_sigtxts) = self.analyzer.LoadAnnotation() - self.assertEqual(invalid_sigtxts, {'touchpad?calc['}) - - signature_set = set() - for src_sig, dst_sigs in add_rules.items(): - signature_set.add(src_sig) - signature_set.update(dst_sigs) - - for remove_sigs in remove_rules: - signature_set.update(remove_sigs) - - (signature_map, failed_sigs) = self.analyzer.MapAnnotation(funcs, - signature_set) - result = self.analyzer.ResolveAnnotation(funcs) - (add_set, remove_list, eliminated_addrs, failed_sigs) = result - - expect_signature_map = { - ('hook_task', None, None): {funcs[0x1000]}, - ('touchpad_calc', os.path.abspath('a.c'), None): {funcs[0x4000]}, - ('touchpad_calc', os.path.abspath('b.c'), None): {funcs[0x5000]}, - ('console_task', None, None): {funcs[0x2000]}, - ('inlined_mul_alias', None, None): {funcs[0x13100]}, - ('inlined_mul', os.path.abspath('x.c'), None): {funcs[0x13000], - funcs[0x13100]}, - ('inlined_mul', None, None): {funcs[0x13000], funcs[0x13100]}, - } - self.assertEqual(len(signature_map), len(expect_signature_map)) - for sig, funclist in signature_map.items(): - self.assertEqual(set(funclist), expect_signature_map[sig]) - - self.assertEqual(add_set, { - (funcs[0x1000], funcs[0x4000]), - (funcs[0x1000], funcs[0x1000]), - (funcs[0x2000], funcs[0x5000]), - (funcs[0x2000], funcs[0x13100]), - (funcs[0x13000], funcs[0x13000]), - (funcs[0x13000], funcs[0x13100]), - (funcs[0x13100], funcs[0x13000]), - (funcs[0x13100], funcs[0x13100]), - }) - expect_remove_list = [ - [funcs[0x4000]], - [funcs[0x13000]], - [funcs[0x13100]], - [funcs[0x13000], funcs[0x2000], funcs[0x4000]], - [funcs[0x13100], funcs[0x2000], funcs[0x4000]], - [funcs[0x13000], funcs[0x13100], funcs[0x2000]], - [funcs[0x13100], funcs[0x13100], funcs[0x2000]], - ] - self.assertEqual(len(remove_list), len(expect_remove_list)) - for remove_path in remove_list: - self.assertTrue(remove_path in expect_remove_list) - - self.assertEqual(eliminated_addrs, {0x1002}) - self.assertEqual(failed_sigs, { - ('touchpad?calc[', sa.StackAnalyzer.ANNOTATION_ERROR_INVALID), - ('touchpad_calc', sa.StackAnalyzer.ANNOTATION_ERROR_AMBIGUOUS), - ('hook_task[q.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), - ('task_unk[a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), - ('touchpad_calc[x/a.c]', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), - ('trackpad_range', sa.StackAnalyzer.ANNOTATION_ERROR_NOTFOUND), - }) - - def testPreprocessAnnotation(self): - funcs = { - 0x1000: sa.Function(0x1000, 'hook_task', 0, []), - 0x2000: sa.Function(0x2000, 'console_task', 0, []), - 0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []), - } - funcs[0x1000].callsites = [ - sa.Callsite(0x1002, 0x1000, False, funcs[0x1000])] - funcs[0x2000].callsites = [ - sa.Callsite(0x2002, 0x1000, False, funcs[0x1000]), - sa.Callsite(0x2006, None, True, None), - ] - add_set = { - (funcs[0x2000], funcs[0x2000]), - (funcs[0x2000], funcs[0x4000]), - (funcs[0x4000], funcs[0x1000]), - (funcs[0x4000], funcs[0x2000]), - } - remove_list = [ - [funcs[0x1000]], - [funcs[0x2000], funcs[0x2000]], - [funcs[0x4000], funcs[0x1000]], - [funcs[0x2000], funcs[0x4000], funcs[0x2000]], - [funcs[0x4000], funcs[0x1000], funcs[0x4000]], - ] - eliminated_addrs = {0x2006} - - remaining_remove_list = self.analyzer.PreprocessAnnotation(funcs, - add_set, - remove_list, - eliminated_addrs) - - expect_funcs = { - 0x1000: sa.Function(0x1000, 'hook_task', 0, []), - 0x2000: sa.Function(0x2000, 'console_task', 0, []), - 0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []), - } - expect_funcs[0x2000].callsites = [ - sa.Callsite(None, 0x4000, False, expect_funcs[0x4000])] - expect_funcs[0x4000].callsites = [ - sa.Callsite(None, 0x2000, False, expect_funcs[0x2000])] - self.assertEqual(funcs, expect_funcs) - self.assertEqual(remaining_remove_list, [ - [funcs[0x2000], funcs[0x4000], funcs[0x2000]], - ]) - - def testAndesAnalyzeDisassembly(self): - disasm_text = ( - '\n' - 'build/{BOARD}/RW/ec.RW.elf: file format elf32-nds32le' - '\n' - 'Disassembly of section .text:\n' - '\n' - '00000900 :\n' - ' ...\n' - '00001000 :\n' - ' 1000: fc 42\tpush25 $r10, #16 ! {$r6~$r10, $fp, $gp, $lp}\n' - ' 1004: 47 70\t\tmovi55 $r0, #1\n' - ' 1006: b1 13\tbnezs8 100929de \n' - ' 1008: 00 01 5c fc\tbne $r6, $r0, 2af6a\n' - '00002000 :\n' - ' 2000: fc 00\t\tpush25 $r6, #0 ! {$r6, $fp, $gp, $lp} \n' - ' 2002: f0 0e fc c5\tjal 1000 \n' - ' 2006: f0 0e bd 3b\tj 53968 \n' - ' 200a: de ad be ef\tswi.gp $r0, [ + #-11036]\n' - '00004000 :\n' - ' 4000: 47 70\t\tmovi55 $r0, #1\n' - '00010000 :' - ) - function_map = self.analyzer.AnalyzeDisassembly(disasm_text) - func_hook_task = sa.Function(0x1000, 'hook_task', 48, [ - sa.Callsite(0x1006, 0x100929de, True, None)]) - expect_funcmap = { - 0x1000: func_hook_task, - 0x2000: sa.Function(0x2000, 'console_task', 16, - [sa.Callsite(0x2002, 0x1000, False, func_hook_task), - sa.Callsite(0x2006, 0x53968, True, None)]), - 0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []), - } - self.assertEqual(function_map, expect_funcmap) - - def testArmAnalyzeDisassembly(self): - disasm_text = ( - '\n' - 'build/{BOARD}/RW/ec.RW.elf: file format elf32-littlearm' - '\n' - 'Disassembly of section .text:\n' - '\n' - '00000900 :\n' - ' ...\n' - '00001000 :\n' - ' 1000: dead beef\tfake\n' - ' 1004: 4770\t\tbx lr\n' - ' 1006: b113\tcbz r3, 100929de \n' - ' 1008: 00015cfc\t.word 0x00015cfc\n' - '00002000 :\n' - ' 2000: b508\t\tpush {r3, lr} ; malformed comments,; r0, r1 \n' - ' 2002: f00e fcc5\tbl 1000 \n' - ' 2006: f00e bd3b\tb.w 53968 \n' - ' 200a: dead beef\tfake\n' - '00004000 :\n' - ' 4000: 4770\t\tbx lr\n' - '00010000 :' - ) - function_map = self.analyzer.AnalyzeDisassembly(disasm_text) - func_hook_task = sa.Function(0x1000, 'hook_task', 0, [ - sa.Callsite(0x1006, 0x100929de, True, None)]) - expect_funcmap = { - 0x1000: func_hook_task, - 0x2000: sa.Function(0x2000, 'console_task', 8, - [sa.Callsite(0x2002, 0x1000, False, func_hook_task), - sa.Callsite(0x2006, 0x53968, True, None)]), - 0x4000: sa.Function(0x4000, 'touchpad_calc', 0, []), - } - self.assertEqual(function_map, expect_funcmap) - - def testAnalyzeCallGraph(self): - funcs = { - 0x1000: sa.Function(0x1000, 'hook_task', 0, []), - 0x2000: sa.Function(0x2000, 'console_task', 8, []), - 0x3000: sa.Function(0x3000, 'task_a', 12, []), - 0x4000: sa.Function(0x4000, 'task_b', 96, []), - 0x5000: sa.Function(0x5000, 'task_c', 32, []), - 0x6000: sa.Function(0x6000, 'task_d', 100, []), - 0x7000: sa.Function(0x7000, 'task_e', 24, []), - 0x8000: sa.Function(0x8000, 'task_f', 20, []), - 0x9000: sa.Function(0x9000, 'task_g', 20, []), - 0x10000: sa.Function(0x10000, 'task_x', 16, []), - } - funcs[0x1000].callsites = [ - sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]), - sa.Callsite(0x1006, 0x4000, False, funcs[0x4000])] - funcs[0x2000].callsites = [ - sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]), - sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]), - sa.Callsite(0x200a, 0x10000, False, funcs[0x10000])] - funcs[0x3000].callsites = [ - sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]), - sa.Callsite(0x3006, 0x1000, False, funcs[0x1000])] - funcs[0x4000].callsites = [ - sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]), - sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]), - sa.Callsite(0x400a, 0x8000, False, funcs[0x8000])] - funcs[0x5000].callsites = [ - sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])] - funcs[0x7000].callsites = [ - sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])] - funcs[0x8000].callsites = [ - sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])] - funcs[0x9000].callsites = [ - sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])] - funcs[0x10000].callsites = [ - sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])] - - cycles = self.analyzer.AnalyzeCallGraph(funcs, [ - [funcs[0x2000]] * 2, - [funcs[0x10000], funcs[0x2000]] * 3, - [funcs[0x1000], funcs[0x3000], funcs[0x1000]] - ]) - - expect_func_stack = { - 0x1000: (268, [funcs[0x1000], - funcs[0x3000], - funcs[0x4000], - funcs[0x8000], - funcs[0x9000], - funcs[0x4000], - funcs[0x7000]]), - 0x2000: (208, [funcs[0x2000], - funcs[0x10000], - funcs[0x2000], - funcs[0x10000], - funcs[0x2000], - funcs[0x5000], - funcs[0x4000], - funcs[0x7000]]), - 0x3000: (280, [funcs[0x3000], - funcs[0x1000], - funcs[0x3000], - funcs[0x4000], - funcs[0x8000], - funcs[0x9000], - funcs[0x4000], - funcs[0x7000]]), - 0x4000: (120, [funcs[0x4000], funcs[0x7000]]), - 0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]), - 0x6000: (100, [funcs[0x6000]]), - 0x7000: (24, [funcs[0x7000]]), - 0x8000: (160, [funcs[0x8000], - funcs[0x9000], - funcs[0x4000], - funcs[0x7000]]), - 0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]), - 0x10000: (200, [funcs[0x10000], - funcs[0x2000], - funcs[0x10000], - funcs[0x2000], - funcs[0x5000], - funcs[0x4000], - funcs[0x7000]]), - } - expect_cycles = [ - {funcs[0x4000], funcs[0x8000], funcs[0x9000]}, - {funcs[0x7000]}, - ] - for func in funcs.values(): - (stack_max_usage, stack_max_path) = expect_func_stack[func.address] - self.assertEqual(func.stack_max_usage, stack_max_usage) - self.assertEqual(func.stack_max_path, stack_max_path) - - self.assertEqual(len(cycles), len(expect_cycles)) - for cycle in cycles: - self.assertTrue(cycle in expect_cycles) - - @mock.patch('subprocess.check_output') - def testAddressToLine(self, checkoutput_mock): - checkoutput_mock.return_value = 'fake_func\n/test.c:1' - self.assertEqual(self.analyzer.AddressToLine(0x1234), - [('fake_func', '/test.c', 1)]) - checkoutput_mock.assert_called_once_with( - ['addr2line', '-f', '-e', './ec.RW.elf', '1234'], encoding='utf-8') - checkoutput_mock.reset_mock() - - checkoutput_mock.return_value = 'fake_func\n/a.c:1\nbake_func\n/b.c:2\n' - self.assertEqual(self.analyzer.AddressToLine(0x1234, True), - [('fake_func', '/a.c', 1), ('bake_func', '/b.c', 2)]) - checkoutput_mock.assert_called_once_with( - ['addr2line', '-f', '-e', './ec.RW.elf', '1234', '-i'], - encoding='utf-8') - checkoutput_mock.reset_mock() - - checkoutput_mock.return_value = 'fake_func\n/test.c:1 (discriminator 128)' - self.assertEqual(self.analyzer.AddressToLine(0x12345), - [('fake_func', '/test.c', 1)]) - checkoutput_mock.assert_called_once_with( - ['addr2line', '-f', '-e', './ec.RW.elf', '12345'], encoding='utf-8') - checkoutput_mock.reset_mock() - - checkoutput_mock.return_value = '??\n:?\nbake_func\n/b.c:2\n' - self.assertEqual(self.analyzer.AddressToLine(0x123456), - [None, ('bake_func', '/b.c', 2)]) - checkoutput_mock.assert_called_once_with( - ['addr2line', '-f', '-e', './ec.RW.elf', '123456'], encoding='utf-8') - checkoutput_mock.reset_mock() - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'addr2line failed to resolve lines.'): - checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '') - self.analyzer.AddressToLine(0x5678) - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'Failed to run addr2line.'): - checkoutput_mock.side_effect = OSError() - self.analyzer.AddressToLine(0x9012) - - @mock.patch('subprocess.check_output') - @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine') - def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock): - disasm_text = ( - '\n' - 'build/{BOARD}/RW/ec.RW.elf: file format elf32-nds32le' - '\n' - 'Disassembly of section .text:\n' - '\n' - '00000900 :\n' - ' ...\n' - '00001000 :\n' - ' 1000: fc 00\t\tpush25 $r10, #16 ! {$r6~$r10, $fp, $gp, $lp}\n' - ' 1002: 47 70\t\tmovi55 $r0, #1\n' - ' 1006: 00 01 5c fc\tbne $r6, $r0, 2af6a\n' - '00002000 :\n' - ' 2000: fc 00\t\tpush25 $r6, #0 ! {$r6, $fp, $gp, $lp} \n' - ' 2002: f0 0e fc c5\tjal 1000 \n' - ' 2006: f0 0e bd 3b\tj 53968 \n' - ' 200a: 12 34 56 78\tjral5 $r0\n' - ) - - addrtoline_mock.return_value = [('??', '??', 0)] - self.analyzer.annotation = { - 'exception_frame_size': 64, - 'remove': [['fake_func']], - } - - with mock.patch('builtins.print') as print_mock: - checkoutput_mock.return_value = disasm_text - self.analyzer.Analyze() - print_mock.assert_has_calls([ - mock.call( - 'Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048'), - mock.call('Call Trace:'), - mock.call(' hook_task (32) [??:0] 1000'), - mock.call( - 'Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460'), - mock.call('Call Trace:'), - mock.call(' console_task (16) [??:0] 2000'), - mock.call(' -> ??[??:0] 2002'), - mock.call(' hook_task (32) [??:0] 1000'), - mock.call('Unresolved indirect callsites:'), - mock.call(' In function console_task:'), - mock.call(' -> ??[??:0] 200a'), - mock.call('Unresolved annotation signatures:'), - mock.call(' fake_func: function is not found'), - ]) - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'Failed to run objdump.'): - checkoutput_mock.side_effect = OSError() - self.analyzer.Analyze() - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'objdump failed to disassemble.'): - checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '') - self.analyzer.Analyze() - - @mock.patch('subprocess.check_output') - @mock.patch('stack_analyzer.StackAnalyzer.AddressToLine') - def testArmAnalyze(self, addrtoline_mock, checkoutput_mock): - disasm_text = ( - '\n' - 'build/{BOARD}/RW/ec.RW.elf: file format elf32-littlearm' - '\n' - 'Disassembly of section .text:\n' - '\n' - '00000900 :\n' - ' ...\n' - '00001000 :\n' - ' 1000: b508\t\tpush {r3, lr}\n' - ' 1002: 4770\t\tbx lr\n' - ' 1006: 00015cfc\t.word 0x00015cfc\n' - '00002000 :\n' - ' 2000: b508\t\tpush {r3, lr}\n' - ' 2002: f00e fcc5\tbl 1000 \n' - ' 2006: f00e bd3b\tb.w 53968 \n' - ' 200a: 1234 5678\tb.w sl\n' - ) - - addrtoline_mock.return_value = [('??', '??', 0)] - self.analyzer.annotation = { - 'exception_frame_size': 64, - 'remove': [['fake_func']], - } - - with mock.patch('builtins.print') as print_mock: - checkoutput_mock.return_value = disasm_text - self.analyzer.Analyze() - print_mock.assert_has_calls([ - mock.call( - 'Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048'), - mock.call('Call Trace:'), - mock.call(' hook_task (8) [??:0] 1000'), - mock.call( - 'Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460'), - mock.call('Call Trace:'), - mock.call(' console_task (8) [??:0] 2000'), - mock.call(' -> ??[??:0] 2002'), - mock.call(' hook_task (8) [??:0] 1000'), - mock.call('Unresolved indirect callsites:'), - mock.call(' In function console_task:'), - mock.call(' -> ??[??:0] 200a'), - mock.call('Unresolved annotation signatures:'), - mock.call(' fake_func: function is not found'), - ]) - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'Failed to run objdump.'): - checkoutput_mock.side_effect = OSError() - self.analyzer.Analyze() - - with self.assertRaisesRegexp(sa.StackAnalyzerError, - 'objdump failed to disassemble.'): - checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '') - self.analyzer.Analyze() - - @mock.patch('subprocess.check_output') - @mock.patch('stack_analyzer.ParseArgs') - def testMain(self, parseargs_mock, checkoutput_mock): - symbol_text = ('1000 g F .text 0000015c .hidden hook_task\n' - '2000 g F .text 0000051c .hidden console_task\n') - rodata_text = ( - '\n' - 'Contents of section .rodata:\n' - ' 20000 dead1000 00100000 dead2000 00200000 He..f.He..s.\n' - ) - - args = mock.MagicMock(elf_path='./ec.RW.elf', - export_taskinfo='fake', - section='RW', - objdump='objdump', - addr2line='addr2line', - annotation='fake') - parseargs_mock.return_value = args - - with mock.patch('os.path.exists') as path_mock: - path_mock.return_value = False - with mock.patch('builtins.print') as print_mock: - with mock.patch('builtins.open', mock.mock_open()) as open_mock: - sa.main() - print_mock.assert_any_call( - 'Warning: Annotation file fake does not exist.') - - with mock.patch('os.path.exists') as path_mock: - path_mock.return_value = True - with mock.patch('builtins.print') as print_mock: - with mock.patch('builtins.open', mock.mock_open()) as open_mock: - open_mock.side_effect = IOError() - sa.main() - print_mock.assert_called_once_with( - 'Error: Failed to open annotation file fake.') - - with mock.patch('builtins.print') as print_mock: - with mock.patch('builtins.open', mock.mock_open()) as open_mock: - open_mock.return_value.read.side_effect = ['{', ''] - sa.main() - open_mock.assert_called_once_with('fake', 'r') - print_mock.assert_called_once_with( - 'Error: Failed to parse annotation file fake.') - - with mock.patch('builtins.print') as print_mock: - with mock.patch('builtins.open', - mock.mock_open(read_data='')) as open_mock: - sa.main() - print_mock.assert_called_once_with( - 'Error: Invalid annotation file fake.') - - args.annotation = None - - with mock.patch('builtins.print') as print_mock: - checkoutput_mock.side_effect = [symbol_text, rodata_text] - sa.main() - print_mock.assert_called_once_with( - 'Error: Failed to load export_taskinfo.') - - with mock.patch('builtins.print') as print_mock: - checkoutput_mock.side_effect = subprocess.CalledProcessError(1, '') - sa.main() - print_mock.assert_called_once_with( - 'Error: objdump failed to dump symbol table or rodata.') - - with mock.patch('builtins.print') as print_mock: - checkoutput_mock.side_effect = OSError() - sa.main() - print_mock.assert_called_once_with('Error: Failed to run objdump.') - - -if __name__ == '__main__': - unittest.main() + remove_list = [ + [funcs[0x1000]], + [funcs[0x2000], funcs[0x2000]], + [funcs[0x4000], funcs[0x1000]], + [funcs[0x2000], funcs[0x4000], funcs[0x2000]], + [funcs[0x4000], funcs[0x1000], funcs[0x4000]], + ] + eliminated_addrs = {0x2006} + + remaining_remove_list = self.analyzer.PreprocessAnnotation( + funcs, add_set, remove_list, eliminated_addrs + ) + + expect_funcs = { + 0x1000: sa.Function(0x1000, "hook_task", 0, []), + 0x2000: sa.Function(0x2000, "console_task", 0, []), + 0x4000: sa.Function(0x4000, "touchpad_calc", 0, []), + } + expect_funcs[0x2000].callsites = [ + sa.Callsite(None, 0x4000, False, expect_funcs[0x4000]) + ] + expect_funcs[0x4000].callsites = [ + sa.Callsite(None, 0x2000, False, expect_funcs[0x2000]) + ] + self.assertEqual(funcs, expect_funcs) + self.assertEqual( + remaining_remove_list, + [ + [funcs[0x2000], funcs[0x4000], funcs[0x2000]], + ], + ) + + def testAndesAnalyzeDisassembly(self): + disasm_text = ( + "\n" + "build/{BOARD}/RW/ec.RW.elf: file format elf32-nds32le" + "\n" + "Disassembly of section .text:\n" + "\n" + "00000900 :\n" + " ...\n" + "00001000 :\n" + " 1000: fc 42\tpush25 $r10, #16 ! {$r6~$r10, $fp, $gp, $lp}\n" + " 1004: 47 70\t\tmovi55 $r0, #1\n" + " 1006: b1 13\tbnezs8 100929de \n" + " 1008: 00 01 5c fc\tbne $r6, $r0, 2af6a\n" + "00002000 :\n" + " 2000: fc 00\t\tpush25 $r6, #0 ! {$r6, $fp, $gp, $lp} \n" + " 2002: f0 0e fc c5\tjal 1000 \n" + " 2006: f0 0e bd 3b\tj 53968 \n" + " 200a: de ad be ef\tswi.gp $r0, [ + #-11036]\n" + "00004000 :\n" + " 4000: 47 70\t\tmovi55 $r0, #1\n" + "00010000 :" + ) + function_map = self.analyzer.AnalyzeDisassembly(disasm_text) + func_hook_task = sa.Function( + 0x1000, "hook_task", 48, [sa.Callsite(0x1006, 0x100929DE, True, None)] + ) + expect_funcmap = { + 0x1000: func_hook_task, + 0x2000: sa.Function( + 0x2000, + "console_task", + 16, + [ + sa.Callsite(0x2002, 0x1000, False, func_hook_task), + sa.Callsite(0x2006, 0x53968, True, None), + ], + ), + 0x4000: sa.Function(0x4000, "touchpad_calc", 0, []), + } + self.assertEqual(function_map, expect_funcmap) + + def testArmAnalyzeDisassembly(self): + disasm_text = ( + "\n" + "build/{BOARD}/RW/ec.RW.elf: file format elf32-littlearm" + "\n" + "Disassembly of section .text:\n" + "\n" + "00000900 :\n" + " ...\n" + "00001000 :\n" + " 1000: dead beef\tfake\n" + " 1004: 4770\t\tbx lr\n" + " 1006: b113\tcbz r3, 100929de \n" + " 1008: 00015cfc\t.word 0x00015cfc\n" + "00002000 :\n" + " 2000: b508\t\tpush {r3, lr} ; malformed comments,; r0, r1 \n" + " 2002: f00e fcc5\tbl 1000 \n" + " 2006: f00e bd3b\tb.w 53968 \n" + " 200a: dead beef\tfake\n" + "00004000 :\n" + " 4000: 4770\t\tbx lr\n" + "00010000 :" + ) + function_map = self.analyzer.AnalyzeDisassembly(disasm_text) + func_hook_task = sa.Function( + 0x1000, "hook_task", 0, [sa.Callsite(0x1006, 0x100929DE, True, None)] + ) + expect_funcmap = { + 0x1000: func_hook_task, + 0x2000: sa.Function( + 0x2000, + "console_task", + 8, + [ + sa.Callsite(0x2002, 0x1000, False, func_hook_task), + sa.Callsite(0x2006, 0x53968, True, None), + ], + ), + 0x4000: sa.Function(0x4000, "touchpad_calc", 0, []), + } + self.assertEqual(function_map, expect_funcmap) + + def testAnalyzeCallGraph(self): + funcs = { + 0x1000: sa.Function(0x1000, "hook_task", 0, []), + 0x2000: sa.Function(0x2000, "console_task", 8, []), + 0x3000: sa.Function(0x3000, "task_a", 12, []), + 0x4000: sa.Function(0x4000, "task_b", 96, []), + 0x5000: sa.Function(0x5000, "task_c", 32, []), + 0x6000: sa.Function(0x6000, "task_d", 100, []), + 0x7000: sa.Function(0x7000, "task_e", 24, []), + 0x8000: sa.Function(0x8000, "task_f", 20, []), + 0x9000: sa.Function(0x9000, "task_g", 20, []), + 0x10000: sa.Function(0x10000, "task_x", 16, []), + } + funcs[0x1000].callsites = [ + sa.Callsite(0x1002, 0x3000, False, funcs[0x3000]), + sa.Callsite(0x1006, 0x4000, False, funcs[0x4000]), + ] + funcs[0x2000].callsites = [ + sa.Callsite(0x2002, 0x5000, False, funcs[0x5000]), + sa.Callsite(0x2006, 0x2000, False, funcs[0x2000]), + sa.Callsite(0x200A, 0x10000, False, funcs[0x10000]), + ] + funcs[0x3000].callsites = [ + sa.Callsite(0x3002, 0x4000, False, funcs[0x4000]), + sa.Callsite(0x3006, 0x1000, False, funcs[0x1000]), + ] + funcs[0x4000].callsites = [ + sa.Callsite(0x4002, 0x6000, True, funcs[0x6000]), + sa.Callsite(0x4006, 0x7000, False, funcs[0x7000]), + sa.Callsite(0x400A, 0x8000, False, funcs[0x8000]), + ] + funcs[0x5000].callsites = [sa.Callsite(0x5002, 0x4000, False, funcs[0x4000])] + funcs[0x7000].callsites = [sa.Callsite(0x7002, 0x7000, False, funcs[0x7000])] + funcs[0x8000].callsites = [sa.Callsite(0x8002, 0x9000, False, funcs[0x9000])] + funcs[0x9000].callsites = [sa.Callsite(0x9002, 0x4000, False, funcs[0x4000])] + funcs[0x10000].callsites = [sa.Callsite(0x10002, 0x2000, False, funcs[0x2000])] + + cycles = self.analyzer.AnalyzeCallGraph( + funcs, + [ + [funcs[0x2000]] * 2, + [funcs[0x10000], funcs[0x2000]] * 3, + [funcs[0x1000], funcs[0x3000], funcs[0x1000]], + ], + ) + + expect_func_stack = { + 0x1000: ( + 268, + [ + funcs[0x1000], + funcs[0x3000], + funcs[0x4000], + funcs[0x8000], + funcs[0x9000], + funcs[0x4000], + funcs[0x7000], + ], + ), + 0x2000: ( + 208, + [ + funcs[0x2000], + funcs[0x10000], + funcs[0x2000], + funcs[0x10000], + funcs[0x2000], + funcs[0x5000], + funcs[0x4000], + funcs[0x7000], + ], + ), + 0x3000: ( + 280, + [ + funcs[0x3000], + funcs[0x1000], + funcs[0x3000], + funcs[0x4000], + funcs[0x8000], + funcs[0x9000], + funcs[0x4000], + funcs[0x7000], + ], + ), + 0x4000: (120, [funcs[0x4000], funcs[0x7000]]), + 0x5000: (152, [funcs[0x5000], funcs[0x4000], funcs[0x7000]]), + 0x6000: (100, [funcs[0x6000]]), + 0x7000: (24, [funcs[0x7000]]), + 0x8000: (160, [funcs[0x8000], funcs[0x9000], funcs[0x4000], funcs[0x7000]]), + 0x9000: (140, [funcs[0x9000], funcs[0x4000], funcs[0x7000]]), + 0x10000: ( + 200, + [ + funcs[0x10000], + funcs[0x2000], + funcs[0x10000], + funcs[0x2000], + funcs[0x5000], + funcs[0x4000], + funcs[0x7000], + ], + ), + } + expect_cycles = [ + {funcs[0x4000], funcs[0x8000], funcs[0x9000]}, + {funcs[0x7000]}, + ] + for func in funcs.values(): + (stack_max_usage, stack_max_path) = expect_func_stack[func.address] + self.assertEqual(func.stack_max_usage, stack_max_usage) + self.assertEqual(func.stack_max_path, stack_max_path) + + self.assertEqual(len(cycles), len(expect_cycles)) + for cycle in cycles: + self.assertTrue(cycle in expect_cycles) + + @mock.patch("subprocess.check_output") + def testAddressToLine(self, checkoutput_mock): + checkoutput_mock.return_value = "fake_func\n/test.c:1" + self.assertEqual( + self.analyzer.AddressToLine(0x1234), [("fake_func", "/test.c", 1)] + ) + checkoutput_mock.assert_called_once_with( + ["addr2line", "-f", "-e", "./ec.RW.elf", "1234"], encoding="utf-8" + ) + checkoutput_mock.reset_mock() + + checkoutput_mock.return_value = "fake_func\n/a.c:1\nbake_func\n/b.c:2\n" + self.assertEqual( + self.analyzer.AddressToLine(0x1234, True), + [("fake_func", "/a.c", 1), ("bake_func", "/b.c", 2)], + ) + checkoutput_mock.assert_called_once_with( + ["addr2line", "-f", "-e", "./ec.RW.elf", "1234", "-i"], encoding="utf-8" + ) + checkoutput_mock.reset_mock() + + checkoutput_mock.return_value = "fake_func\n/test.c:1 (discriminator 128)" + self.assertEqual( + self.analyzer.AddressToLine(0x12345), [("fake_func", "/test.c", 1)] + ) + checkoutput_mock.assert_called_once_with( + ["addr2line", "-f", "-e", "./ec.RW.elf", "12345"], encoding="utf-8" + ) + checkoutput_mock.reset_mock() + + checkoutput_mock.return_value = "??\n:?\nbake_func\n/b.c:2\n" + self.assertEqual( + self.analyzer.AddressToLine(0x123456), [None, ("bake_func", "/b.c", 2)] + ) + checkoutput_mock.assert_called_once_with( + ["addr2line", "-f", "-e", "./ec.RW.elf", "123456"], encoding="utf-8" + ) + checkoutput_mock.reset_mock() + + with self.assertRaisesRegexp( + sa.StackAnalyzerError, "addr2line failed to resolve lines." + ): + checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "") + self.analyzer.AddressToLine(0x5678) + + with self.assertRaisesRegexp(sa.StackAnalyzerError, "Failed to run addr2line."): + checkoutput_mock.side_effect = OSError() + self.analyzer.AddressToLine(0x9012) + + @mock.patch("subprocess.check_output") + @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine") + def testAndesAnalyze(self, addrtoline_mock, checkoutput_mock): + disasm_text = ( + "\n" + "build/{BOARD}/RW/ec.RW.elf: file format elf32-nds32le" + "\n" + "Disassembly of section .text:\n" + "\n" + "00000900 :\n" + " ...\n" + "00001000 :\n" + " 1000: fc 00\t\tpush25 $r10, #16 ! {$r6~$r10, $fp, $gp, $lp}\n" + " 1002: 47 70\t\tmovi55 $r0, #1\n" + " 1006: 00 01 5c fc\tbne $r6, $r0, 2af6a\n" + "00002000 :\n" + " 2000: fc 00\t\tpush25 $r6, #0 ! {$r6, $fp, $gp, $lp} \n" + " 2002: f0 0e fc c5\tjal 1000 \n" + " 2006: f0 0e bd 3b\tj 53968 \n" + " 200a: 12 34 56 78\tjral5 $r0\n" + ) + + addrtoline_mock.return_value = [("??", "??", 0)] + self.analyzer.annotation = { + "exception_frame_size": 64, + "remove": [["fake_func"]], + } + + with mock.patch("builtins.print") as print_mock: + checkoutput_mock.return_value = disasm_text + self.analyzer.Analyze() + print_mock.assert_has_calls( + [ + mock.call( + "Task: HOOKS, Max size: 96 (32 + 64), Allocated size: 2048" + ), + mock.call("Call Trace:"), + mock.call(" hook_task (32) [??:0] 1000"), + mock.call( + "Task: CONSOLE, Max size: 112 (48 + 64), Allocated size: 460" + ), + mock.call("Call Trace:"), + mock.call(" console_task (16) [??:0] 2000"), + mock.call(" -> ??[??:0] 2002"), + mock.call(" hook_task (32) [??:0] 1000"), + mock.call("Unresolved indirect callsites:"), + mock.call(" In function console_task:"), + mock.call(" -> ??[??:0] 200a"), + mock.call("Unresolved annotation signatures:"), + mock.call(" fake_func: function is not found"), + ] + ) + + with self.assertRaisesRegexp(sa.StackAnalyzerError, "Failed to run objdump."): + checkoutput_mock.side_effect = OSError() + self.analyzer.Analyze() + + with self.assertRaisesRegexp( + sa.StackAnalyzerError, "objdump failed to disassemble." + ): + checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "") + self.analyzer.Analyze() + + @mock.patch("subprocess.check_output") + @mock.patch("stack_analyzer.StackAnalyzer.AddressToLine") + def testArmAnalyze(self, addrtoline_mock, checkoutput_mock): + disasm_text = ( + "\n" + "build/{BOARD}/RW/ec.RW.elf: file format elf32-littlearm" + "\n" + "Disassembly of section .text:\n" + "\n" + "00000900 :\n" + " ...\n" + "00001000 :\n" + " 1000: b508\t\tpush {r3, lr}\n" + " 1002: 4770\t\tbx lr\n" + " 1006: 00015cfc\t.word 0x00015cfc\n" + "00002000 :\n" + " 2000: b508\t\tpush {r3, lr}\n" + " 2002: f00e fcc5\tbl 1000 \n" + " 2006: f00e bd3b\tb.w 53968 \n" + " 200a: 1234 5678\tb.w sl\n" + ) + + addrtoline_mock.return_value = [("??", "??", 0)] + self.analyzer.annotation = { + "exception_frame_size": 64, + "remove": [["fake_func"]], + } + + with mock.patch("builtins.print") as print_mock: + checkoutput_mock.return_value = disasm_text + self.analyzer.Analyze() + print_mock.assert_has_calls( + [ + mock.call( + "Task: HOOKS, Max size: 72 (8 + 64), Allocated size: 2048" + ), + mock.call("Call Trace:"), + mock.call(" hook_task (8) [??:0] 1000"), + mock.call( + "Task: CONSOLE, Max size: 80 (16 + 64), Allocated size: 460" + ), + mock.call("Call Trace:"), + mock.call(" console_task (8) [??:0] 2000"), + mock.call(" -> ??[??:0] 2002"), + mock.call(" hook_task (8) [??:0] 1000"), + mock.call("Unresolved indirect callsites:"), + mock.call(" In function console_task:"), + mock.call(" -> ??[??:0] 200a"), + mock.call("Unresolved annotation signatures:"), + mock.call(" fake_func: function is not found"), + ] + ) + + with self.assertRaisesRegexp(sa.StackAnalyzerError, "Failed to run objdump."): + checkoutput_mock.side_effect = OSError() + self.analyzer.Analyze() + + with self.assertRaisesRegexp( + sa.StackAnalyzerError, "objdump failed to disassemble." + ): + checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "") + self.analyzer.Analyze() + + @mock.patch("subprocess.check_output") + @mock.patch("stack_analyzer.ParseArgs") + def testMain(self, parseargs_mock, checkoutput_mock): + symbol_text = ( + "1000 g F .text 0000015c .hidden hook_task\n" + "2000 g F .text 0000051c .hidden console_task\n" + ) + rodata_text = ( + "\n" + "Contents of section .rodata:\n" + " 20000 dead1000 00100000 dead2000 00200000 He..f.He..s.\n" + ) + + args = mock.MagicMock( + elf_path="./ec.RW.elf", + export_taskinfo="fake", + section="RW", + objdump="objdump", + addr2line="addr2line", + annotation="fake", + ) + parseargs_mock.return_value = args + + with mock.patch("os.path.exists") as path_mock: + path_mock.return_value = False + with mock.patch("builtins.print") as print_mock: + with mock.patch("builtins.open", mock.mock_open()) as open_mock: + sa.main() + print_mock.assert_any_call( + "Warning: Annotation file fake does not exist." + ) + + with mock.patch("os.path.exists") as path_mock: + path_mock.return_value = True + with mock.patch("builtins.print") as print_mock: + with mock.patch("builtins.open", mock.mock_open()) as open_mock: + open_mock.side_effect = IOError() + sa.main() + print_mock.assert_called_once_with( + "Error: Failed to open annotation file fake." + ) + + with mock.patch("builtins.print") as print_mock: + with mock.patch("builtins.open", mock.mock_open()) as open_mock: + open_mock.return_value.read.side_effect = ["{", ""] + sa.main() + open_mock.assert_called_once_with("fake", "r") + print_mock.assert_called_once_with( + "Error: Failed to parse annotation file fake." + ) + + with mock.patch("builtins.print") as print_mock: + with mock.patch( + "builtins.open", mock.mock_open(read_data="") + ) as open_mock: + sa.main() + print_mock.assert_called_once_with( + "Error: Invalid annotation file fake." + ) + + args.annotation = None + + with mock.patch("builtins.print") as print_mock: + checkoutput_mock.side_effect = [symbol_text, rodata_text] + sa.main() + print_mock.assert_called_once_with("Error: Failed to load export_taskinfo.") + + with mock.patch("builtins.print") as print_mock: + checkoutput_mock.side_effect = subprocess.CalledProcessError(1, "") + sa.main() + print_mock.assert_called_once_with( + "Error: objdump failed to dump symbol table or rodata." + ) + + with mock.patch("builtins.print") as print_mock: + checkoutput_mock.side_effect = OSError() + sa.main() + print_mock.assert_called_once_with("Error: Failed to run objdump.") + + +if __name__ == "__main__": + unittest.main() diff --git a/extra/tigertool/ecusb/__init__.py b/extra/tigertool/ecusb/__init__.py index fe4dbc6749..7a48fdb360 100644 --- a/extra/tigertool/ecusb/__init__.py +++ b/extra/tigertool/ecusb/__init__.py @@ -6,4 +6,4 @@ # pylint: disable=bad-indentation,docstring-section-indent # pylint: disable=docstring-trailing-quotes -__all__ = ['tiny_servo_common', 'stm32usb', 'stm32uart', 'pty_driver'] +__all__ = ["tiny_servo_common", "stm32usb", "stm32uart", "pty_driver"] diff --git a/extra/tigertool/ecusb/pty_driver.py b/extra/tigertool/ecusb/pty_driver.py index 09ef8c42e4..037ff8d529 100644 --- a/extra/tigertool/ecusb/pty_driver.py +++ b/extra/tigertool/ecusb/pty_driver.py @@ -17,8 +17,9 @@ import ast import errno import fcntl import os -import pexpect import time + +import pexpect from pexpect import fdpexpect # Expecting a result in 3 seconds is plenty even for slow platforms. @@ -27,281 +28,285 @@ FLUSH_UART_TIMEOUT = 1 class ptyError(Exception): - """Exception class for pty errors.""" + """Exception class for pty errors.""" UART_PARAMS = { - 'uart_cmd': None, - 'uart_multicmd': None, - 'uart_regexp': None, - 'uart_timeout': DEFAULT_UART_TIMEOUT, + "uart_cmd": None, + "uart_multicmd": None, + "uart_regexp": None, + "uart_timeout": DEFAULT_UART_TIMEOUT, } class ptyDriver(object): - """Automate interactive commands on a pty interface.""" - def __init__(self, interface, params, fast=False): - """Init class variables.""" - self._child = None - self._fd = None - self._interface = interface - self._pty_path = self._interface.get_pty() - self._dict = UART_PARAMS.copy() - self._fast = fast - - def __del__(self): - self.close() - - def close(self): - """Close any open files and interfaces.""" - if self._fd: - self._close() - self._interface.close() - - def _open(self): - """Connect to serial device and create pexpect interface.""" - assert self._fd is None - self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK) - # Don't allow forked processes to access. - fcntl.fcntl(self._fd, fcntl.F_SETFD, - fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC) - self._child = fdpexpect.fdspawn(self._fd) - # pexpect defaults to a 100ms delay before sending characters, to - # work around race conditions in ssh. We don't need this feature - # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up. - if self._fast: - self._child.delaybeforesend = 0.001 - - def _close(self): - """Close serial device connection.""" - os.close(self._fd) - self._fd = None - self._child = None - - def _flush(self): - """Flush device output to prevent previous messages interfering.""" - if self._child.sendline('') != 1: - raise ptyError('Failed to send newline.') - # Have a maximum timeout for the flush operation. We should have cleared - # all data from the buffer, but if data is regularly being generated, we - # can't guarantee it will ever stop. - flush_end_time = time.time() + FLUSH_UART_TIMEOUT - while time.time() <= flush_end_time: - try: - self._child.expect('.', timeout=0.01) - except (pexpect.TIMEOUT, pexpect.EOF): - break - except OSError as e: - # EAGAIN indicates no data available, maybe we didn't wait long enough. - if e.errno != errno.EAGAIN: - raise - break - - def _send(self, cmds): - """Send command to EC. - - This function always flushes serial device before sending, and is used as - a wrapper function to make sure the channel is always flushed before - sending commands. - - Args: - cmds: The commands to send to the device, either a list or a string. - - Raises: - ptyError: Raised when writing to the device fails. - """ - self._flush() - if not isinstance(cmds, list): - cmds = [cmds] - for cmd in cmds: - if self._child.sendline(cmd) != len(cmd) + 1: - raise ptyError('Failed to send command.') - - def _issue_cmd(self, cmds): - """Send command to the device and do not wait for response. - - Args: - cmds: The commands to send to the device, either a list or a string. - """ - self._issue_cmd_get_results(cmds, []) - - def _issue_cmd_get_results(self, cmds, - regex_list, timeout=DEFAULT_UART_TIMEOUT): - """Send command to the device and wait for response. - - This function waits for response message matching a regular - expressions. - - Args: - cmds: The commands issued, either a list or a string. - regex_list: List of Regular expressions used to match response message. - Note1, list must be ordered. - Note2, empty list sends and returns. - timeout: time to wait for matching results before failing. - - Returns: - List of tuples, each of which contains the entire matched string and - all the subgroups of the match. None if not matched. - For example: - response of the given command: - High temp: 37.2 - Low temp: 36.4 - regex_list: - ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)'] - returns: - [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')] - - Raises: - ptyError: If timed out waiting for a response - """ - result_list = [] - self._open() - try: - self._send(cmds) - for regex in regex_list: - self._child.expect(regex, timeout) - match = self._child.match - lastindex = match.lastindex if match and match.lastindex else 0 - # Create a tuple which contains the entire matched string and all - # the subgroups of the match. - result = match.group(*range(lastindex + 1)) if match else None - if result: - result = tuple(res.decode('utf-8') for res in result) - result_list.append(result) - except pexpect.TIMEOUT: - raise ptyError('Timeout waiting for response.') - finally: - if not regex_list: - # Must be longer than delaybeforesend - time.sleep(0.1) - self._close() - return result_list - - def _issue_cmd_get_multi_results(self, cmd, regex): - """Send command to the device and wait for multiple response. - - This function waits for arbitrary number of response message - matching a regular expression. - - Args: - cmd: The command issued. - regex: Regular expression used to match response message. - - Returns: - List of tuples, each of which contains the entire matched string and - all the subgroups of the match. None if not matched. - """ - result_list = [] - self._open() - try: - self._send(cmd) - while True: + """Automate interactive commands on a pty interface.""" + + def __init__(self, interface, params, fast=False): + """Init class variables.""" + self._child = None + self._fd = None + self._interface = interface + self._pty_path = self._interface.get_pty() + self._dict = UART_PARAMS.copy() + self._fast = fast + + def __del__(self): + self.close() + + def close(self): + """Close any open files and interfaces.""" + if self._fd: + self._close() + self._interface.close() + + def _open(self): + """Connect to serial device and create pexpect interface.""" + assert self._fd is None + self._fd = os.open(self._pty_path, os.O_RDWR | os.O_NONBLOCK) + # Don't allow forked processes to access. + fcntl.fcntl( + self._fd, + fcntl.F_SETFD, + fcntl.fcntl(self._fd, fcntl.F_GETFD) | fcntl.FD_CLOEXEC, + ) + self._child = fdpexpect.fdspawn(self._fd) + # pexpect defaults to a 100ms delay before sending characters, to + # work around race conditions in ssh. We don't need this feature + # so we'll change delaybeforesend from 0.1 to 0.001 to speed things up. + if self._fast: + self._child.delaybeforesend = 0.001 + + def _close(self): + """Close serial device connection.""" + os.close(self._fd) + self._fd = None + self._child = None + + def _flush(self): + """Flush device output to prevent previous messages interfering.""" + if self._child.sendline("") != 1: + raise ptyError("Failed to send newline.") + # Have a maximum timeout for the flush operation. We should have cleared + # all data from the buffer, but if data is regularly being generated, we + # can't guarantee it will ever stop. + flush_end_time = time.time() + FLUSH_UART_TIMEOUT + while time.time() <= flush_end_time: + try: + self._child.expect(".", timeout=0.01) + except (pexpect.TIMEOUT, pexpect.EOF): + break + except OSError as e: + # EAGAIN indicates no data available, maybe we didn't wait long enough. + if e.errno != errno.EAGAIN: + raise + break + + def _send(self, cmds): + """Send command to EC. + + This function always flushes serial device before sending, and is used as + a wrapper function to make sure the channel is always flushed before + sending commands. + + Args: + cmds: The commands to send to the device, either a list or a string. + + Raises: + ptyError: Raised when writing to the device fails. + """ + self._flush() + if not isinstance(cmds, list): + cmds = [cmds] + for cmd in cmds: + if self._child.sendline(cmd) != len(cmd) + 1: + raise ptyError("Failed to send command.") + + def _issue_cmd(self, cmds): + """Send command to the device and do not wait for response. + + Args: + cmds: The commands to send to the device, either a list or a string. + """ + self._issue_cmd_get_results(cmds, []) + + def _issue_cmd_get_results(self, cmds, regex_list, timeout=DEFAULT_UART_TIMEOUT): + """Send command to the device and wait for response. + + This function waits for response message matching a regular + expressions. + + Args: + cmds: The commands issued, either a list or a string. + regex_list: List of Regular expressions used to match response message. + Note1, list must be ordered. + Note2, empty list sends and returns. + timeout: time to wait for matching results before failing. + + Returns: + List of tuples, each of which contains the entire matched string and + all the subgroups of the match. None if not matched. + For example: + response of the given command: + High temp: 37.2 + Low temp: 36.4 + regex_list: + ['High temp: (\d+)\.(\d+)', 'Low temp: (\d+)\.(\d+)'] + returns: + [('High temp: 37.2', '37', '2'), ('Low temp: 36.4', '36', '4')] + + Raises: + ptyError: If timed out waiting for a response + """ + result_list = [] + self._open() try: - self._child.expect(regex, timeout=0.1) - match = self._child.match - lastindex = match.lastindex if match and match.lastindex else 0 - # Create a tuple which contains the entire matched string and all - # the subgroups of the match. - result = match.group(*range(lastindex + 1)) if match else None - if result: - result = tuple(res.decode('utf-8') for res in result) - result_list.append(result) + self._send(cmds) + for regex in regex_list: + self._child.expect(regex, timeout) + match = self._child.match + lastindex = match.lastindex if match and match.lastindex else 0 + # Create a tuple which contains the entire matched string and all + # the subgroups of the match. + result = match.group(*range(lastindex + 1)) if match else None + if result: + result = tuple(res.decode("utf-8") for res in result) + result_list.append(result) except pexpect.TIMEOUT: - break - finally: - self._close() - return result_list - - def _Set_uart_timeout(self, timeout): - """Set timeout value for waiting for the device response. - - Args: - timeout: Timeout value in second. - """ - self._dict['uart_timeout'] = timeout - - def _Get_uart_timeout(self): - """Get timeout value for waiting for the device response. - - Returns: - Timeout value in second. - """ - return self._dict['uart_timeout'] - - def _Set_uart_regexp(self, regexp): - """Set the list of regular expressions which matches the command response. - - Args: - regexp: A string which contains a list of regular expressions. - """ - if not isinstance(regexp, str): - raise ptyError('The argument regexp should be a string.') - self._dict['uart_regexp'] = ast.literal_eval(regexp) - - def _Get_uart_regexp(self): - """Get the list of regular expressions which matches the command response. - - Returns: - A string which contains a list of regular expressions. - """ - return str(self._dict['uart_regexp']) - - def _Set_uart_cmd(self, cmd): - """Set the UART command and send it to the device. - - If ec_uart_regexp is 'None', the command is just sent and it doesn't care - about its response. - - If ec_uart_regexp is not 'None', the command is send and its response, - which matches the regular expression of ec_uart_regexp, will be kept. - Use its getter to obtain this result. If no match after ec_uart_timeout - seconds, a timeout error will be raised. - - Args: - cmd: A string of UART command. - """ - if self._dict['uart_regexp']: - self._dict['uart_cmd'] = self._issue_cmd_get_results( - cmd, self._dict['uart_regexp'], self._dict['uart_timeout']) - else: - self._dict['uart_cmd'] = None - self._issue_cmd(cmd) - - def _Set_uart_multicmd(self, cmds): - """Set multiple UART commands and send them to the device. - - Note that ec_uart_regexp is not supported to match the results. - - Args: - cmds: A semicolon-separated string of UART commands. - """ - self._issue_cmd(cmds.split(';')) - - def _Get_uart_cmd(self): - """Get the result of the latest UART command. - - Returns: - A string which contains a list of tuples, each of which contains the - entire matched string and all the subgroups of the match. 'None' if - the ec_uart_regexp is 'None'. - """ - return str(self._dict['uart_cmd']) - - def _Set_uart_capture(self, cmd): - """Set UART capture mode (on or off). - - Once capture is enabled, UART output could be collected periodically by - invoking _Get_uart_stream() below. - - Args: - cmd: True for on, False for off - """ - self._interface.set_capture_active(cmd) - - def _Get_uart_capture(self): - """Get the UART capture mode (on or off).""" - return self._interface.get_capture_active() - - def _Get_uart_stream(self): - """Get uart stream generated since last time.""" - return self._interface.get_stream() + raise ptyError("Timeout waiting for response.") + finally: + if not regex_list: + # Must be longer than delaybeforesend + time.sleep(0.1) + self._close() + return result_list + + def _issue_cmd_get_multi_results(self, cmd, regex): + """Send command to the device and wait for multiple response. + + This function waits for arbitrary number of response message + matching a regular expression. + + Args: + cmd: The command issued. + regex: Regular expression used to match response message. + + Returns: + List of tuples, each of which contains the entire matched string and + all the subgroups of the match. None if not matched. + """ + result_list = [] + self._open() + try: + self._send(cmd) + while True: + try: + self._child.expect(regex, timeout=0.1) + match = self._child.match + lastindex = match.lastindex if match and match.lastindex else 0 + # Create a tuple which contains the entire matched string and all + # the subgroups of the match. + result = match.group(*range(lastindex + 1)) if match else None + if result: + result = tuple(res.decode("utf-8") for res in result) + result_list.append(result) + except pexpect.TIMEOUT: + break + finally: + self._close() + return result_list + + def _Set_uart_timeout(self, timeout): + """Set timeout value for waiting for the device response. + + Args: + timeout: Timeout value in second. + """ + self._dict["uart_timeout"] = timeout + + def _Get_uart_timeout(self): + """Get timeout value for waiting for the device response. + + Returns: + Timeout value in second. + """ + return self._dict["uart_timeout"] + + def _Set_uart_regexp(self, regexp): + """Set the list of regular expressions which matches the command response. + + Args: + regexp: A string which contains a list of regular expressions. + """ + if not isinstance(regexp, str): + raise ptyError("The argument regexp should be a string.") + self._dict["uart_regexp"] = ast.literal_eval(regexp) + + def _Get_uart_regexp(self): + """Get the list of regular expressions which matches the command response. + + Returns: + A string which contains a list of regular expressions. + """ + return str(self._dict["uart_regexp"]) + + def _Set_uart_cmd(self, cmd): + """Set the UART command and send it to the device. + + If ec_uart_regexp is 'None', the command is just sent and it doesn't care + about its response. + + If ec_uart_regexp is not 'None', the command is send and its response, + which matches the regular expression of ec_uart_regexp, will be kept. + Use its getter to obtain this result. If no match after ec_uart_timeout + seconds, a timeout error will be raised. + + Args: + cmd: A string of UART command. + """ + if self._dict["uart_regexp"]: + self._dict["uart_cmd"] = self._issue_cmd_get_results( + cmd, self._dict["uart_regexp"], self._dict["uart_timeout"] + ) + else: + self._dict["uart_cmd"] = None + self._issue_cmd(cmd) + + def _Set_uart_multicmd(self, cmds): + """Set multiple UART commands and send them to the device. + + Note that ec_uart_regexp is not supported to match the results. + + Args: + cmds: A semicolon-separated string of UART commands. + """ + self._issue_cmd(cmds.split(";")) + + def _Get_uart_cmd(self): + """Get the result of the latest UART command. + + Returns: + A string which contains a list of tuples, each of which contains the + entire matched string and all the subgroups of the match. 'None' if + the ec_uart_regexp is 'None'. + """ + return str(self._dict["uart_cmd"]) + + def _Set_uart_capture(self, cmd): + """Set UART capture mode (on or off). + + Once capture is enabled, UART output could be collected periodically by + invoking _Get_uart_stream() below. + + Args: + cmd: True for on, False for off + """ + self._interface.set_capture_active(cmd) + + def _Get_uart_capture(self): + """Get the UART capture mode (on or off).""" + return self._interface.get_capture_active() + + def _Get_uart_stream(self): + """Get uart stream generated since last time.""" + return self._interface.get_stream() diff --git a/extra/tigertool/ecusb/stm32uart.py b/extra/tigertool/ecusb/stm32uart.py index 95219455a9..5794bd091b 100644 --- a/extra/tigertool/ecusb/stm32uart.py +++ b/extra/tigertool/ecusb/stm32uart.py @@ -17,232 +17,244 @@ import termios import threading import time import tty + import usb from . import stm32usb class SuartError(Exception): - """Class for exceptions of Suart.""" - def __init__(self, msg, value=0): - """SuartError constructor. + """Class for exceptions of Suart.""" - Args: - msg: string, message describing error in detail - value: integer, value of error when non-zero status returned. Default=0 - """ - super(SuartError, self).__init__(msg, value) - self.msg = msg - self.value = value + def __init__(self, msg, value=0): + """SuartError constructor. + Args: + msg: string, message describing error in detail + value: integer, value of error when non-zero status returned. Default=0 + """ + super(SuartError, self).__init__(msg, value) + self.msg = msg + self.value = value -class Suart(object): - """Provide interface to stm32 serial usb endpoint.""" - def __init__(self, vendor=0x18d1, product=0x501a, interface=0, - serialname=None, debuglog=False): - """Suart contstructor. - - Initializes stm32 USB stream interface. - - Args: - vendor: usb vendor id of stm32 device - product: usb product id of stm32 device - interface: interface number of stm32 device to use - serialname: serial name to target. Defaults to None. - debuglog: chatty output. Defaults to False. - - Raises: - SuartError: If init fails - """ - self._ptym = None - self._ptys = None - self._ptyname = None - self._rx_thread = None - self._tx_thread = None - self._debuglog = debuglog - self._susb = stm32usb.Susb(vendor=vendor, product=product, - interface=interface, serialname=serialname) - self._running = False - - def __del__(self): - """Suart destructor.""" - self.close() - - def close(self): - """Stop all running threads.""" - self._running = False - if self._rx_thread: - self._rx_thread.join(2) - self._rx_thread = None - if self._tx_thread: - self._tx_thread.join(2) - self._tx_thread = None - self._susb.close() - - def run_rx_thread(self): - """Background loop to pass data from USB to pty.""" - ep = select.epoll() - ep.register(self._ptym, select.EPOLLHUP) - try: - while self._running: - events = ep.poll(0) - # Check if the pty is connected to anything, or hungup. - if not events: - try: - r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS) - if r: - if self._debuglog: - print(''.join([chr(x) for x in r]), end='') - os.write(self._ptym, r) - - # If we miss some characters on pty disconnect, that's fine. - # ep.read() also throws USBError on timeout, which we discard. - except OSError: - pass - except usb.core.USBError: - pass - else: - time.sleep(.1) - except Exception as e: - raise e - - def run_tx_thread(self): - """Background loop to pass data from pty to USB.""" - ep = select.epoll() - ep.register(self._ptym, select.EPOLLHUP) - try: - while self._running: - events = ep.poll(0) - # Check if the pty is connected to anything, or hungup. - if not events: - try: - r = os.read(self._ptym, 64) - # TODO(crosbug.com/936182): Remove when the servo v4/micro console - # issues are fixed. - time.sleep(0.001) - if r: - self._susb._write_ep.write(r, self._susb.TIMEOUT_MS) - - except OSError: - pass - except usb.core.USBError: - pass - else: - time.sleep(.1) - except Exception as e: - raise e - - def run(self): - """Creates pthreads to poll stm32 & PTY for data.""" - m, s = os.openpty() - self._ptyname = os.ttyname(s) - - self._ptym = m - self._ptys = s - - os.fchmod(s, 0o660) - - # Change the owner and group of the PTY to the user who started servod. - try: - uid = int(os.environ.get('SUDO_UID', -1)) - except TypeError: - uid = -1 - try: - gid = int(os.environ.get('SUDO_GID', -1)) - except TypeError: - gid = -1 - os.fchown(s, uid, gid) - - tty.setraw(self._ptym, termios.TCSADRAIN) - - # Generate a HUP flag on pty slave fd. - os.fdopen(s).close() - - self._running = True - - self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[]) - self._rx_thread.daemon = True - self._rx_thread.start() - - self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[]) - self._tx_thread.daemon = True - self._tx_thread.start() - - def get_uart_props(self): - """Get the uart's properties. - - Returns: - dict where: - baudrate: integer of uarts baudrate - bits: integer, number of bits of data Can be 5|6|7|8 inclusive - parity: integer, parity of 0-2 inclusive where: - 0: no parity - 1: odd parity - 2: even parity - sbits: integer, number of stop bits. Can be 0|1|2 inclusive where: - 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits - """ - return { - 'baudrate': 115200, - 'bits': 8, - 'parity': 0, - 'sbits': 1, - } - - def set_uart_props(self, line_props): - """Set the uart's properties. - - Note that Suart cannot set properties - and will fail if the properties are not the default 115200,8n1. - - Args: - line_props: dict where: - baudrate: integer of uarts baudrate - bits: integer, number of bits of data ( prior to stop bit) - parity: integer, parity of 0-2 inclusive where - 0: no parity - 1: odd parity - 2: even parity - sbits: integer, number of stop bits. Can be 0|1|2 inclusive where: - 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits - - Raises: - SuartError: If requested line properties are not the default. - """ - curr_props = self.get_uart_props() - for prop in line_props: - if line_props[prop] != curr_props[prop]: - raise SuartError('Line property %s cannot be set from %s to %s' % ( - prop, curr_props[prop], line_props[prop])) - return True - - def get_pty(self): - """Gets path to pty for communication to/from uart. - - Returns: - String path to the pty connected to the uart - """ - return self._ptyname +class Suart(object): + """Provide interface to stm32 serial usb endpoint.""" + + def __init__( + self, + vendor=0x18D1, + product=0x501A, + interface=0, + serialname=None, + debuglog=False, + ): + """Suart contstructor. + + Initializes stm32 USB stream interface. + + Args: + vendor: usb vendor id of stm32 device + product: usb product id of stm32 device + interface: interface number of stm32 device to use + serialname: serial name to target. Defaults to None. + debuglog: chatty output. Defaults to False. + + Raises: + SuartError: If init fails + """ + self._ptym = None + self._ptys = None + self._ptyname = None + self._rx_thread = None + self._tx_thread = None + self._debuglog = debuglog + self._susb = stm32usb.Susb( + vendor=vendor, product=product, interface=interface, serialname=serialname + ) + self._running = False + + def __del__(self): + """Suart destructor.""" + self.close() + + def close(self): + """Stop all running threads.""" + self._running = False + if self._rx_thread: + self._rx_thread.join(2) + self._rx_thread = None + if self._tx_thread: + self._tx_thread.join(2) + self._tx_thread = None + self._susb.close() + + def run_rx_thread(self): + """Background loop to pass data from USB to pty.""" + ep = select.epoll() + ep.register(self._ptym, select.EPOLLHUP) + try: + while self._running: + events = ep.poll(0) + # Check if the pty is connected to anything, or hungup. + if not events: + try: + r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS) + if r: + if self._debuglog: + print("".join([chr(x) for x in r]), end="") + os.write(self._ptym, r) + + # If we miss some characters on pty disconnect, that's fine. + # ep.read() also throws USBError on timeout, which we discard. + except OSError: + pass + except usb.core.USBError: + pass + else: + time.sleep(0.1) + except Exception as e: + raise e + + def run_tx_thread(self): + """Background loop to pass data from pty to USB.""" + ep = select.epoll() + ep.register(self._ptym, select.EPOLLHUP) + try: + while self._running: + events = ep.poll(0) + # Check if the pty is connected to anything, or hungup. + if not events: + try: + r = os.read(self._ptym, 64) + # TODO(crosbug.com/936182): Remove when the servo v4/micro console + # issues are fixed. + time.sleep(0.001) + if r: + self._susb._write_ep.write(r, self._susb.TIMEOUT_MS) + + except OSError: + pass + except usb.core.USBError: + pass + else: + time.sleep(0.1) + except Exception as e: + raise e + + def run(self): + """Creates pthreads to poll stm32 & PTY for data.""" + m, s = os.openpty() + self._ptyname = os.ttyname(s) + + self._ptym = m + self._ptys = s + + os.fchmod(s, 0o660) + + # Change the owner and group of the PTY to the user who started servod. + try: + uid = int(os.environ.get("SUDO_UID", -1)) + except TypeError: + uid = -1 + + try: + gid = int(os.environ.get("SUDO_GID", -1)) + except TypeError: + gid = -1 + os.fchown(s, uid, gid) + + tty.setraw(self._ptym, termios.TCSADRAIN) + + # Generate a HUP flag on pty slave fd. + os.fdopen(s).close() + + self._running = True + + self._rx_thread = threading.Thread(target=self.run_rx_thread, args=[]) + self._rx_thread.daemon = True + self._rx_thread.start() + + self._tx_thread = threading.Thread(target=self.run_tx_thread, args=[]) + self._tx_thread.daemon = True + self._tx_thread.start() + + def get_uart_props(self): + """Get the uart's properties. + + Returns: + dict where: + baudrate: integer of uarts baudrate + bits: integer, number of bits of data Can be 5|6|7|8 inclusive + parity: integer, parity of 0-2 inclusive where: + 0: no parity + 1: odd parity + 2: even parity + sbits: integer, number of stop bits. Can be 0|1|2 inclusive where: + 0: 1 stop bit + 1: 1.5 stop bits + 2: 2 stop bits + """ + return { + "baudrate": 115200, + "bits": 8, + "parity": 0, + "sbits": 1, + } + + def set_uart_props(self, line_props): + """Set the uart's properties. + + Note that Suart cannot set properties + and will fail if the properties are not the default 115200,8n1. + + Args: + line_props: dict where: + baudrate: integer of uarts baudrate + bits: integer, number of bits of data ( prior to stop bit) + parity: integer, parity of 0-2 inclusive where + 0: no parity + 1: odd parity + 2: even parity + sbits: integer, number of stop bits. Can be 0|1|2 inclusive where: + 0: 1 stop bit + 1: 1.5 stop bits + 2: 2 stop bits + + Raises: + SuartError: If requested line properties are not the default. + """ + curr_props = self.get_uart_props() + for prop in line_props: + if line_props[prop] != curr_props[prop]: + raise SuartError( + "Line property %s cannot be set from %s to %s" + % (prop, curr_props[prop], line_props[prop]) + ) + return True + + def get_pty(self): + """Gets path to pty for communication to/from uart. + + Returns: + String path to the pty connected to the uart + """ + return self._ptyname def main(): - """Run a suart test with the default parameters.""" - try: - sobj = Suart() - sobj.run() + """Run a suart test with the default parameters.""" + try: + sobj = Suart() + sobj.run() - # run() is a thread so just busy wait to mimic server. - while True: - # Ours sleeps to eleven! - time.sleep(11) - except KeyboardInterrupt: - sys.exit(0) + # run() is a thread so just busy wait to mimic server. + while True: + # Ours sleeps to eleven! + time.sleep(11) + except KeyboardInterrupt: + sys.exit(0) -if __name__ == '__main__': - main() +if __name__ == "__main__": + main() diff --git a/extra/tigertool/ecusb/stm32usb.py b/extra/tigertool/ecusb/stm32usb.py index bfd5fbb1fb..4b2b23fbac 100644 --- a/extra/tigertool/ecusb/stm32usb.py +++ b/extra/tigertool/ecusb/stm32usb.py @@ -12,108 +12,115 @@ import usb class SusbError(Exception): - """Class for exceptions of Susb.""" - def __init__(self, msg, value=0): - """SusbError constructor. + """Class for exceptions of Susb.""" - Args: - msg: string, message describing error in detail - value: integer, value of error when non-zero status returned. Default=0 - """ - super(SusbError, self).__init__(msg, value) - self.msg = msg - self.value = value + def __init__(self, msg, value=0): + """SusbError constructor. + + Args: + msg: string, message describing error in detail + value: integer, value of error when non-zero status returned. Default=0 + """ + super(SusbError, self).__init__(msg, value) + self.msg = msg + self.value = value class Susb(object): - """Provide stm32 USB functionality. - - Instance Variables: - _read_ep: pyUSB read endpoint for this interface - _write_ep: pyUSB write endpoint for this interface - """ - READ_ENDPOINT = 0x81 - WRITE_ENDPOINT = 0x1 - TIMEOUT_MS = 100 - - def __init__(self, vendor=0x18d1, - product=0x5027, interface=1, serialname=None, logger=None): - """Susb constructor. - - Discovers and connects to stm32 USB endpoints. - - Args: - vendor: usb vendor id of stm32 device. - product: usb product id of stm32 device. - interface: interface number ( 1 - 4 ) of stm32 device to use. - serialname: string of device serialname. - logger: none - - Raises: - SusbError: An error accessing Susb object + """Provide stm32 USB functionality. + + Instance Variables: + _read_ep: pyUSB read endpoint for this interface + _write_ep: pyUSB write endpoint for this interface """ - self._vendor = vendor - self._product = product - self._interface = interface - self._serialname = serialname - self._find_device() - - def _find_device(self): - """Set up the usb endpoint""" - # Find the stm32. - dev_g = usb.core.find(idVendor=self._vendor, idProduct=self._product, - find_all=True) - dev_list = list(dev_g) - - if not dev_list: - raise SusbError('USB device not found') - - # Check if we have multiple stm32s and we've specified the serial. - dev = None - if self._serialname: - for d in dev_list: - dev_serial = usb.util.get_string(d, d.iSerialNumber) - if dev_serial == self._serialname: - dev = d - break - if dev is None: - raise SusbError('USB device(%s) not found' % self._serialname) - else: - try: - dev = dev_list[0] - except StopIteration: - raise SusbError('USB device %04x:%04x not found' % ( - self._vendor, self._product)) - - # If we can't set configuration, it's already been set. - try: - dev.set_configuration() - except usb.core.USBError: - pass - - self._dev = dev - - # Get an endpoint instance. - cfg = dev.get_active_configuration() - intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface) - self._intf = intf - if not intf: - raise SusbError('Interface %04x:%04x - 0x%x not found' % ( - self._vendor, self._product, self._interface)) - - # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel - # module driver that produces a ttyUSB, or direct endpoint access, but - # can't do both at the same time. - if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True: - dev.detach_kernel_driver(intf.bInterfaceNumber) - - read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT - read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number) - self._read_ep = read_ep - - write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT - write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number) - self._write_ep = write_ep - - def close(self): - usb.util.dispose_resources(self._dev) + + READ_ENDPOINT = 0x81 + WRITE_ENDPOINT = 0x1 + TIMEOUT_MS = 100 + + def __init__( + self, vendor=0x18D1, product=0x5027, interface=1, serialname=None, logger=None + ): + """Susb constructor. + + Discovers and connects to stm32 USB endpoints. + + Args: + vendor: usb vendor id of stm32 device. + product: usb product id of stm32 device. + interface: interface number ( 1 - 4 ) of stm32 device to use. + serialname: string of device serialname. + logger: none + + Raises: + SusbError: An error accessing Susb object + """ + self._vendor = vendor + self._product = product + self._interface = interface + self._serialname = serialname + self._find_device() + + def _find_device(self): + """Set up the usb endpoint""" + # Find the stm32. + dev_g = usb.core.find( + idVendor=self._vendor, idProduct=self._product, find_all=True + ) + dev_list = list(dev_g) + + if not dev_list: + raise SusbError("USB device not found") + + # Check if we have multiple stm32s and we've specified the serial. + dev = None + if self._serialname: + for d in dev_list: + dev_serial = usb.util.get_string(d, d.iSerialNumber) + if dev_serial == self._serialname: + dev = d + break + if dev is None: + raise SusbError("USB device(%s) not found" % self._serialname) + else: + try: + dev = dev_list[0] + except StopIteration: + raise SusbError( + "USB device %04x:%04x not found" % (self._vendor, self._product) + ) + + # If we can't set configuration, it's already been set. + try: + dev.set_configuration() + except usb.core.USBError: + pass + + self._dev = dev + + # Get an endpoint instance. + cfg = dev.get_active_configuration() + intf = usb.util.find_descriptor(cfg, bInterfaceNumber=self._interface) + self._intf = intf + if not intf: + raise SusbError( + "Interface %04x:%04x - 0x%x not found" + % (self._vendor, self._product, self._interface) + ) + + # Detach raiden.ko if it is loaded. CCD endpoints support either a kernel + # module driver that produces a ttyUSB, or direct endpoint access, but + # can't do both at the same time. + if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True: + dev.detach_kernel_driver(intf.bInterfaceNumber) + + read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT + read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number) + self._read_ep = read_ep + + write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT + write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number) + self._write_ep = write_ep + + def close(self): + usb.util.dispose_resources(self._dev) diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py index 726e2e64b7..599bae80dc 100644 --- a/extra/tigertool/ecusb/tiny_servo_common.py +++ b/extra/tigertool/ecusb/tiny_servo_common.py @@ -17,215 +17,224 @@ import time import six import usb -from . import pty_driver -from . import stm32uart +from . import pty_driver, stm32uart def get_subprocess_args(): - if six.PY3: - return {'encoding': 'utf-8'} - return {} + if six.PY3: + return {"encoding": "utf-8"} + return {} class TinyServoError(Exception): - """Exceptions.""" + """Exceptions.""" def log(output): - """Print output to console, logfiles can be added here. + """Print output to console, logfiles can be added here. + + Args: + output: string to output. + """ + sys.stdout.write(output) + sys.stdout.write("\n") + sys.stdout.flush() - Args: - output: string to output. - """ - sys.stdout.write(output) - sys.stdout.write('\n') - sys.stdout.flush() def check_usb(vidpid, serialname=None): - """Check if |vidpid| is present on the system's USB. + """Check if |vidpid| is present on the system's USB. + + Args: + vidpid: string representation of the usb vid:pid, eg. '18d1:2001' + serialname: serialname if specified. - Args: - vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - serialname: serialname if specified. + Returns: + True if found, False, otherwise. + """ + if get_usb_dev(vidpid, serialname): + return True - Returns: - True if found, False, otherwise. - """ - if get_usb_dev(vidpid, serialname): - return True + return False - return False def check_usb_sn(vidpid): - """Return the serial number + """Return the serial number - Return the serial number of the first USB device with VID:PID vidpid, - or None if no device is found. This will not work well with two of - the same device attached. + Return the serial number of the first USB device with VID:PID vidpid, + or None if no device is found. This will not work well with two of + the same device attached. - Args: - vidpid: string representation of the usb vid:pid, eg. '18d1:2001' + Args: + vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - Returns: - string serial number if found, None otherwise. - """ - dev = get_usb_dev(vidpid) + Returns: + string serial number if found, None otherwise. + """ + dev = get_usb_dev(vidpid) - if dev: - dev_serial = usb.util.get_string(dev, dev.iSerialNumber) + if dev: + dev_serial = usb.util.get_string(dev, dev.iSerialNumber) - return dev_serial + return dev_serial + + return None - return None def get_usb_dev(vidpid, serialname=None): - """Return the USB pyusb devie struct + """Return the USB pyusb devie struct + + Return the dev struct of the first USB device with VID:PID vidpid, + or None if no device is found. If more than one device check serial + if supplied. + + Args: + vidpid: string representation of the usb vid:pid, eg. '18d1:2001' + serialname: serialname if specified. + + Returns: + pyusb device if found, None otherwise. + """ + vidpidst = vidpid.split(":") + vid = int(vidpidst[0], 16) + pid = int(vidpidst[1], 16) + + dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True) + dev_list = list(dev_g) + + if not dev_list: + return None + + # Check if we have multiple devices and we've specified the serial. + dev = None + if serialname: + for d in dev_list: + dev_serial = usb.util.get_string(d, d.iSerialNumber) + if dev_serial == serialname: + dev = d + break + if dev is None: + return None + else: + try: + dev = dev_list[0] + except StopIteration: + return None + + return dev + - Return the dev struct of the first USB device with VID:PID vidpid, - or None if no device is found. If more than one device check serial - if supplied. +def check_usb_dev(vidpid, serialname=None): + """Return the USB dev number + + Return the dev number of the first USB device with VID:PID vidpid, + or None if no device is found. If more than one device check serial + if supplied. - Args: - vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - serialname: serialname if specified. + Args: + vidpid: string representation of the usb vid:pid, eg. '18d1:2001' + serialname: serialname if specified. - Returns: - pyusb device if found, None otherwise. - """ - vidpidst = vidpid.split(':') - vid = int(vidpidst[0], 16) - pid = int(vidpidst[1], 16) + Returns: + usb device number if found, None otherwise. + """ + dev = get_usb_dev(vidpid, serialname=serialname) - dev_g = usb.core.find(idVendor=vid, idProduct=pid, find_all=True) - dev_list = list(dev_g) + if dev: + return dev.address - if not dev_list: return None - # Check if we have multiple devices and we've specified the serial. - dev = None - if serialname: - for d in dev_list: - dev_serial = usb.util.get_string(d, d.iSerialNumber) - if dev_serial == serialname: - dev = d - break - if dev is None: - return None - else: - try: - dev = dev_list[0] - except StopIteration: - return None - - return dev -def check_usb_dev(vidpid, serialname=None): - """Return the USB dev number +def wait_for_usb_remove(vidpid, serialname=None, timeout=None): + """Wait for USB device with vidpid to be removed. - Return the dev number of the first USB device with VID:PID vidpid, - or None if no device is found. If more than one device check serial - if supplied. + Wrapper for wait_for_usb below + """ + wait_for_usb(vidpid, serialname=serialname, timeout=timeout, desiredpresence=False) - Args: - vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - serialname: serialname if specified. - Returns: - usb device number if found, None otherwise. - """ - dev = get_usb_dev(vidpid, serialname=serialname) +def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True): + """Wait for usb device with vidpid to be present/absent. - if dev: - return dev.address + Args: + vidpid: string representation of the usb vid:pid, eg. '18d1:2001' + serialname: serialname if specificed. + timeout: timeout in seconds, None for no timeout. + desiredpresence: True for present, False for not present. - return None + Raises: + TinyServoError: on timeout. + """ + if timeout: + finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout) + while check_usb(vidpid, serialname) != desiredpresence: + time.sleep(0.1) + if timeout: + if datetime.datetime.now() > finish: + raise TinyServoError("Timeout", "Timeout waiting for USB %s" % vidpid) -def wait_for_usb_remove(vidpid, serialname=None, timeout=None): - """Wait for USB device with vidpid to be removed. +def do_serialno(serialno, pty): + """Set serialnumber 'serialno' via ec console 'pty'. - Wrapper for wait_for_usb below - """ - wait_for_usb(vidpid, serialname=serialname, - timeout=timeout, desiredpresence=False) + Commands are: + # > serialno set 1234 + # Saving serial number + # Serial number: 1234 -def wait_for_usb(vidpid, serialname=None, timeout=None, desiredpresence=True): - """Wait for usb device with vidpid to be present/absent. - - Args: - vidpid: string representation of the usb vid:pid, eg. '18d1:2001' - serialname: serialname if specificed. - timeout: timeout in seconds, None for no timeout. - desiredpresence: True for present, False for not present. - - Raises: - TinyServoError: on timeout. - """ - if timeout: - finish = datetime.datetime.now() + datetime.timedelta(seconds=timeout) - while check_usb(vidpid, serialname) != desiredpresence: - time.sleep(.1) - if timeout: - if datetime.datetime.now() > finish: - raise TinyServoError('Timeout', 'Timeout waiting for USB %s' % vidpid) + Args: + serialno: string serial number to set. + pty: tinyservo console to send commands. + + Raises: + TinyServoError: on failure to set. + ptyError: on command interface error. + """ + cmd = r"serialno set %s" % serialno + regex = r"Serial number:\s+(\S+)" + + results = pty._issue_cmd_get_results(cmd, [regex])[0] + sn = results[1].strip().strip("\n\r") + + if sn == serialno: + log("Success !") + log("Serial set to %s" % sn) + else: + log("Serial number set to %s but saved as %s." % (serialno, sn)) + raise TinyServoError( + "Serial Number", "Serial number set to %s but saved as %s." % (serialno, sn) + ) -def do_serialno(serialno, pty): - """Set serialnumber 'serialno' via ec console 'pty'. - - Commands are: - # > serialno set 1234 - # Saving serial number - # Serial number: 1234 - - Args: - serialno: string serial number to set. - pty: tinyservo console to send commands. - - Raises: - TinyServoError: on failure to set. - ptyError: on command interface error. - """ - cmd = r'serialno set %s' % serialno - regex = r'Serial number:\s+(\S+)' - - results = pty._issue_cmd_get_results(cmd, [regex])[0] - sn = results[1].strip().strip('\n\r') - - if sn == serialno: - log('Success !') - log('Serial set to %s' % sn) - else: - log('Serial number set to %s but saved as %s.' % (serialno, sn)) - raise TinyServoError( - 'Serial Number', - 'Serial number set to %s but saved as %s.' % (serialno, sn)) def setup_tinyservod(vidpid, interface, serialname=None, debuglog=False): - """Set up a pty - - Set up a pty to the ec console in order - to send commands. Returns a pty_driver object. - - Args: - vidpid: string vidpid of device to access. - interface: not used. - serialname: string serial name of device requested, optional. - debuglog: chatty printout (boolean) - - Returns: - pty object - - Raises: - UsbError, SusbError: on device not found - """ - vidstr, pidstr = vidpid.split(':') - vid = int(vidstr, 16) - pid = int(pidstr, 16) - suart = stm32uart.Suart(vendor=vid, product=pid, - interface=interface, serialname=serialname, - debuglog=debuglog) - suart.run() - pty = pty_driver.ptyDriver(suart, []) - - return pty + """Set up a pty + + Set up a pty to the ec console in order + to send commands. Returns a pty_driver object. + + Args: + vidpid: string vidpid of device to access. + interface: not used. + serialname: string serial name of device requested, optional. + debuglog: chatty printout (boolean) + + Returns: + pty object + + Raises: + UsbError, SusbError: on device not found + """ + vidstr, pidstr = vidpid.split(":") + vid = int(vidstr, 16) + pid = int(pidstr, 16) + suart = stm32uart.Suart( + vendor=vid, + product=pid, + interface=interface, + serialname=serialname, + debuglog=debuglog, + ) + suart.run() + pty = pty_driver.ptyDriver(suart, []) + + return pty diff --git a/extra/tigertool/ecusb/tiny_servod.py b/extra/tigertool/ecusb/tiny_servod.py index 632d9c3a20..ca5ca63f31 100644 --- a/extra/tigertool/ecusb/tiny_servod.py +++ b/extra/tigertool/ecusb/tiny_servod.py @@ -8,47 +8,48 @@ """Helper class to facilitate communication to servo ec console.""" -from ecusb import pty_driver -from ecusb import stm32uart +from ecusb import pty_driver, stm32uart class TinyServod(object): - """Helper class to wrap a pty_driver with interface.""" - - def __init__(self, vid, pid, interface, serialname=None, debug=False): - """Build the driver and interface. - - Args: - vid: servo device vid - pid: servo device pid - interface: which usb interface the servo console is on - serialname: the servo device serial (if available) - """ - self._vid = vid - self._pid = pid - self._interface = interface - self._serial = serialname - self._debug = debug - self._init() - - def _init(self): - self.suart = stm32uart.Suart(vendor=self._vid, - product=self._pid, - interface=self._interface, - serialname=self._serial, - debuglog=self._debug) - self.suart.run() - self.pty = pty_driver.ptyDriver(self.suart, []) - - def reinitialize(self): - """Reinitialize the connect after a reset/disconnect/etc.""" - self.close() - self._init() - - def close(self): - """Close out the connection and release resources. - - Note: if another TinyServod process or servod itself needs the same device - it's necessary to call this to ensure the usb device is available. - """ - self.suart.close() + """Helper class to wrap a pty_driver with interface.""" + + def __init__(self, vid, pid, interface, serialname=None, debug=False): + """Build the driver and interface. + + Args: + vid: servo device vid + pid: servo device pid + interface: which usb interface the servo console is on + serialname: the servo device serial (if available) + """ + self._vid = vid + self._pid = pid + self._interface = interface + self._serial = serialname + self._debug = debug + self._init() + + def _init(self): + self.suart = stm32uart.Suart( + vendor=self._vid, + product=self._pid, + interface=self._interface, + serialname=self._serial, + debuglog=self._debug, + ) + self.suart.run() + self.pty = pty_driver.ptyDriver(self.suart, []) + + def reinitialize(self): + """Reinitialize the connect after a reset/disconnect/etc.""" + self.close() + self._init() + + def close(self): + """Close out the connection and release resources. + + Note: if another TinyServod process or servod itself needs the same device + it's necessary to call this to ensure the usb device is available. + """ + self.suart.close() diff --git a/extra/tigertool/tigertest.py b/extra/tigertool/tigertest.py index 0cd31c8cce..8f8b2c7f03 100755 --- a/extra/tigertool/tigertest.py +++ b/extra/tigertool/tigertest.py @@ -13,7 +13,6 @@ import argparse import subprocess import sys - # Script to control tigertail USB-C Mux board. # # optional arguments: @@ -35,58 +34,60 @@ import sys def testCmd(cmd, expected_results): - """Run command on console, check for success. - - Args: - cmd: shell command to run. - expected_results: a list object of strings expected in the result. - - Raises: - Exception on fail. - """ - print('run: ' + cmd) - try: - p = subprocess.run(cmd, shell=True, check=False, capture_output=True) - output = p.stdout.decode('utf-8') - error = p.stderr.decode('utf-8') - assert p.returncode == 0 - for result in expected_results: - output.index(result) - except Exception as e: - print('FAIL') - print('cmd: ' + cmd) - print('error: ' + str(e)) - print('stdout:\n' + output) - print('stderr:\n' + error) - print('expected: ' + str(expected_results)) - print('RC: ' + str(p.returncode)) - raise e + """Run command on console, check for success. + + Args: + cmd: shell command to run. + expected_results: a list object of strings expected in the result. + + Raises: + Exception on fail. + """ + print("run: " + cmd) + try: + p = subprocess.run(cmd, shell=True, check=False, capture_output=True) + output = p.stdout.decode("utf-8") + error = p.stderr.decode("utf-8") + assert p.returncode == 0 + for result in expected_results: + output.index(result) + except Exception as e: + print("FAIL") + print("cmd: " + cmd) + print("error: " + str(e)) + print("stdout:\n" + output) + print("stderr:\n" + error) + print("expected: " + str(expected_results)) + print("RC: " + str(p.returncode)) + raise e + def test_sequence(): - testCmd('./tigertool.py --reboot', ['PASS']) - testCmd('./tigertool.py --setserialno test', ['PASS']) - testCmd('./tigertool.py --check_serial', ['test', 'PASS']) - testCmd('./tigertool.py -s test --check_serial', ['test', 'PASS']) - testCmd('./tigertool.py -m A', ['Mux set to A', 'PASS']) - testCmd('./tigertool.py -m B', ['Mux set to B', 'PASS']) - testCmd('./tigertool.py -m off', ['Mux set to off', 'PASS']) - testCmd('./tigertool.py -p', ['PASS']) - testCmd('./tigertool.py -r rw', ['PASS']) - testCmd('./tigertool.py -r ro', ['PASS']) - testCmd('./tigertool.py --check_version', ['RW', 'RO', 'PASS']) - - print('PASS') + testCmd("./tigertool.py --reboot", ["PASS"]) + testCmd("./tigertool.py --setserialno test", ["PASS"]) + testCmd("./tigertool.py --check_serial", ["test", "PASS"]) + testCmd("./tigertool.py -s test --check_serial", ["test", "PASS"]) + testCmd("./tigertool.py -m A", ["Mux set to A", "PASS"]) + testCmd("./tigertool.py -m B", ["Mux set to B", "PASS"]) + testCmd("./tigertool.py -m off", ["Mux set to off", "PASS"]) + testCmd("./tigertool.py -p", ["PASS"]) + testCmd("./tigertool.py -r rw", ["PASS"]) + testCmd("./tigertool.py -r ro", ["PASS"]) + testCmd("./tigertool.py --check_version", ["RW", "RO", "PASS"]) + + print("PASS") + def main(argv): - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument('-c', '--count', type=int, default=1, - help='loops to run') + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument("-c", "--count", type=int, default=1, help="loops to run") + + opts = parser.parse_args(argv) - opts = parser.parse_args(argv) + for i in range(1, opts.count + 1): + print("Iteration: %d" % i) + test_sequence() - for i in range(1, opts.count + 1): - print('Iteration: %d' % i) - test_sequence() -if __name__ == '__main__': +if __name__ == "__main__": main(sys.argv[1:]) diff --git a/extra/tigertool/tigertool.py b/extra/tigertool/tigertool.py index 6baae8abdf..37b7b01495 100755 --- a/extra/tigertool/tigertool.py +++ b/extra/tigertool/tigertool.py @@ -17,287 +17,308 @@ import time import ecusb.tiny_servo_common as c -STM_VIDPID = '18d1:5027' -serialno = 'Uninitialized' +STM_VIDPID = "18d1:5027" +serialno = "Uninitialized" + def do_mux(mux, pty): - """Set mux via ec console 'pty'. + """Set mux via ec console 'pty'. + + Args: + mux: mux to connect to DUT, 'A', 'B', or 'off' + pty: a pty object connected to tigertail - Args: - mux: mux to connect to DUT, 'A', 'B', or 'off' - pty: a pty object connected to tigertail + Commands are: + # > mux A + # TYPE-C mux is A + """ + validmux = ["A", "B", "off"] + if mux not in validmux: + c.log("Mux setting %s invalid, try one of %s" % (mux, validmux)) + return False - Commands are: - # > mux A - # TYPE-C mux is A - """ - validmux = ['A', 'B', 'off'] - if mux not in validmux: - c.log('Mux setting %s invalid, try one of %s' % (mux, validmux)) - return False + cmd = "mux %s" % mux + regex = "TYPE\-C mux is ([^\s\r\n]*)\r" - cmd = 'mux %s' % mux - regex = 'TYPE\-C mux is ([^\s\r\n]*)\r' + results = pty._issue_cmd_get_results(cmd, [regex])[0] + result = results[1].strip().strip("\n\r") - results = pty._issue_cmd_get_results(cmd, [regex])[0] - result = results[1].strip().strip('\n\r') + if result != mux: + c.log("Mux set to %s but saved as %s." % (mux, result)) + return False + c.log("Mux set to %s" % result) + return True - if result != mux: - c.log('Mux set to %s but saved as %s.' % (mux, result)) - return False - c.log('Mux set to %s' % result) - return True def do_version(pty): - """Check version via ec console 'pty'. - - Args: - pty: a pty object connected to tigertail - - Commands are: - # > version - # Chip: stm stm32f07x - # Board: 0 - # RO: tigertail_v1.1.6749-74d1a312e - # RW: tigertail_v1.1.6749-74d1a312e - # Build: tigertail_v1.1.6749-74d1a312e - # 2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com - """ - cmd = 'version' - regex = r'RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+' \ - r'(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)' - - results = pty._issue_cmd_get_results(cmd, [regex])[0] - c.log('Version is %s' % results[3]) - c.log('RO: %s' % results[1]) - c.log('RW: %s' % results[2]) - c.log('Date: %s' % results[4]) - c.log('Src: %s' % results[5]) - - return True + """Check version via ec console 'pty'. + + Args: + pty: a pty object connected to tigertail + + Commands are: + # > version + # Chip: stm stm32f07x + # Board: 0 + # RO: tigertail_v1.1.6749-74d1a312e + # RW: tigertail_v1.1.6749-74d1a312e + # Build: tigertail_v1.1.6749-74d1a312e + # 2017-07-25 20:08:34 nsanders@meatball.mtv.corp.google.com + """ + cmd = "version" + regex = ( + r"RO:\s+(\S+)\s+RW:\s+(\S+)\s+Build:\s+(\S+)\s+" + r"(\d\d\d\d-\d\d-\d\d \d\d:\d\d:\d\d) (\S+)" + ) + + results = pty._issue_cmd_get_results(cmd, [regex])[0] + c.log("Version is %s" % results[3]) + c.log("RO: %s" % results[1]) + c.log("RW: %s" % results[2]) + c.log("Date: %s" % results[4]) + c.log("Src: %s" % results[5]) + + return True + def do_check_serial(pty): - """Check serial via ec console 'pty'. + """Check serial via ec console 'pty'. - Args: - pty: a pty object connected to tigertail + Args: + pty: a pty object connected to tigertail - Commands are: - # > serialno - # Serial number: number - """ - cmd = 'serialno' - regex = r'Serial number: ([^\n\r]+)' + Commands are: + # > serialno + # Serial number: number + """ + cmd = "serialno" + regex = r"Serial number: ([^\n\r]+)" - results = pty._issue_cmd_get_results(cmd, [regex])[0] - c.log('Serial is %s' % results[1]) + results = pty._issue_cmd_get_results(cmd, [regex])[0] + c.log("Serial is %s" % results[1]) - return True + return True def do_power(count, bus, pty): - """Check power usage via ec console 'pty'. - - Args: - count: number of samples to capture - bus: rail to monitor, 'vbus', 'cc1', or 'cc2' - pty: a pty object connected to tigertail - - Commands are: - # > ina 0 - # Configuration: 4127 - # Shunt voltage: 02c4 => 1770 uV - # Bus voltage : 1008 => 5130 mV - # Power : 0019 => 625 mW - # Current : 0082 => 130 mA - # Calibration : 0155 - # Mask/Enable : 0008 - # Alert limit : 0000 - """ - if bus == 'vbus': - ina = 0 - if bus == 'cc1': - ina = 4 - if bus == 'cc2': - ina = 1 - - start = time.time() - - c.log('time,\tmV,\tmW,\tmA') - - cmd = 'ina %s' % ina - regex = r'Bus voltage : \S+ \S+ (\d+) mV\s+' \ - r'Power : \S+ \S+ (\d+) mW\s+' \ - r'Current : \S+ \S+ (\d+) mA' - - for i in range(0, count): - results = pty._issue_cmd_get_results(cmd, [regex])[0] - c.log('%.2f,\t%s,\t%s\t%s' % ( - time.time() - start, - results[1], results[2], results[3])) + """Check power usage via ec console 'pty'. + + Args: + count: number of samples to capture + bus: rail to monitor, 'vbus', 'cc1', or 'cc2' + pty: a pty object connected to tigertail + + Commands are: + # > ina 0 + # Configuration: 4127 + # Shunt voltage: 02c4 => 1770 uV + # Bus voltage : 1008 => 5130 mV + # Power : 0019 => 625 mW + # Current : 0082 => 130 mA + # Calibration : 0155 + # Mask/Enable : 0008 + # Alert limit : 0000 + """ + if bus == "vbus": + ina = 0 + if bus == "cc1": + ina = 4 + if bus == "cc2": + ina = 1 + + start = time.time() + + c.log("time,\tmV,\tmW,\tmA") + + cmd = "ina %s" % ina + regex = ( + r"Bus voltage : \S+ \S+ (\d+) mV\s+" + r"Power : \S+ \S+ (\d+) mW\s+" + r"Current : \S+ \S+ (\d+) mA" + ) + + for i in range(0, count): + results = pty._issue_cmd_get_results(cmd, [regex])[0] + c.log( + "%.2f,\t%s,\t%s\t%s" + % (time.time() - start, results[1], results[2], results[3]) + ) + + return True - return True def do_reboot(pty, serialname): - """Reboot via ec console pty - - Args: - pty: a pty object connected to tigertail - serialname: serial name, can be None. - - Command is: reboot. - """ - cmd = 'reboot' - - # Check usb dev number on current instance. - devno = c.check_usb_dev(STM_VIDPID, serialname=serialname) - if not devno: - c.log('Device not found') - return False - - try: - pty._issue_cmd(cmd) - except Exception as e: - c.log('Failed to send command: ' + str(e)) - return False - - try: - c.wait_for_usb_remove(STM_VIDPID, timeout=3., serialname=serialname) - except Exception as e: - # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds - # it's not going to. This step just goes faster if it's detected. - pass - - try: - c.wait_for_usb(STM_VIDPID, timeout=3., serialname=serialname) - except Exception as e: - c.log('Failed to return from reboot: ' + str(e)) - return False - - # Check that the device had a new device number, i.e. it's - # disconnected and reconnected. - newdevno = c.check_usb_dev(STM_VIDPID, serialname=serialname) - if newdevno == devno: - c.log("Device didn't reboot") - return False - - return True + """Reboot via ec console pty + + Args: + pty: a pty object connected to tigertail + serialname: serial name, can be None. + + Command is: reboot. + """ + cmd = "reboot" + + # Check usb dev number on current instance. + devno = c.check_usb_dev(STM_VIDPID, serialname=serialname) + if not devno: + c.log("Device not found") + return False + + try: + pty._issue_cmd(cmd) + except Exception as e: + c.log("Failed to send command: " + str(e)) + return False + + try: + c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname) + except Exception as e: + # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds + # it's not going to. This step just goes faster if it's detected. + pass + + try: + c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname) + except Exception as e: + c.log("Failed to return from reboot: " + str(e)) + return False + + # Check that the device had a new device number, i.e. it's + # disconnected and reconnected. + newdevno = c.check_usb_dev(STM_VIDPID, serialname=serialname) + if newdevno == devno: + c.log("Device didn't reboot") + return False + + return True + def do_sysjump(region, pty, serialname): - """Set region via ec console 'pty'. - - Args: - region: ec code region to execute, 'ro' or 'rw' - pty: a pty object connected to tigertail - serialname: serial name, can be None. - - Commands are: - # > sysjump rw - """ - validregion = ['ro', 'rw'] - if region not in validregion: - c.log('Region setting %s invalid, try one of %s' % ( - region, validregion)) - return False - - cmd = 'sysjump %s' % region - try: - pty._issue_cmd(cmd) - except Exception as e: - c.log('Exception: ' + str(e)) - return False - - try: - c.wait_for_usb_remove(STM_VIDPID, timeout=3., serialname=serialname) - except Exception as e: - # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds - # it's not going to. This step just goes faster if it's detected. - pass - - try: - c.wait_for_usb(STM_VIDPID, timeout=3., serialname=serialname) - except Exception as e: - c.log('Failed to return from restart: ' + str(e)) - return False - - c.log('Region requested %s' % region) - return True + """Set region via ec console 'pty'. + + Args: + region: ec code region to execute, 'ro' or 'rw' + pty: a pty object connected to tigertail + serialname: serial name, can be None. + + Commands are: + # > sysjump rw + """ + validregion = ["ro", "rw"] + if region not in validregion: + c.log("Region setting %s invalid, try one of %s" % (region, validregion)) + return False + + cmd = "sysjump %s" % region + try: + pty._issue_cmd(cmd) + except Exception as e: + c.log("Exception: " + str(e)) + return False + + try: + c.wait_for_usb_remove(STM_VIDPID, timeout=3.0, serialname=serialname) + except Exception as e: + # Polling for reboot isn't reliable but if it hasn't happened in 3 seconds + # it's not going to. This step just goes faster if it's detected. + pass + + try: + c.wait_for_usb(STM_VIDPID, timeout=3.0, serialname=serialname) + except Exception as e: + c.log("Failed to return from restart: " + str(e)) + return False + + c.log("Region requested %s" % region) + return True + def get_parser(): - parser = argparse.ArgumentParser( - description=__doc__) - parser.add_argument('-s', '--serialno', type=str, default=None, - help='serial number of board to use') - parser.add_argument('-b', '--bus', type=str, default='vbus', - help='Which rail to log: [vbus|cc1|cc2]') - group = parser.add_mutually_exclusive_group() - group.add_argument('--setserialno', type=str, default=None, - help='serial number to set on the board.') - group.add_argument('--check_serial', action='store_true', - help='check serial number set on the board.') - group.add_argument('-m', '--mux', type=str, default=None, - help='mux selection') - group.add_argument('-p', '--power', action='store_true', - help='check VBUS') - group.add_argument('-l', '--powerlog', type=int, default=None, - help='log VBUS') - group.add_argument('-r', '--sysjump', type=str, default=None, - help='region selection') - group.add_argument('--reboot', action='store_true', - help='reboot tigertail') - group.add_argument('--check_version', action='store_true', - help='check tigertail version') - return parser + parser = argparse.ArgumentParser(description=__doc__) + parser.add_argument( + "-s", "--serialno", type=str, default=None, help="serial number of board to use" + ) + parser.add_argument( + "-b", + "--bus", + type=str, + default="vbus", + help="Which rail to log: [vbus|cc1|cc2]", + ) + group = parser.add_mutually_exclusive_group() + group.add_argument( + "--setserialno", + type=str, + default=None, + help="serial number to set on the board.", + ) + group.add_argument( + "--check_serial", + action="store_true", + help="check serial number set on the board.", + ) + group.add_argument("-m", "--mux", type=str, default=None, help="mux selection") + group.add_argument("-p", "--power", action="store_true", help="check VBUS") + group.add_argument("-l", "--powerlog", type=int, default=None, help="log VBUS") + group.add_argument( + "-r", "--sysjump", type=str, default=None, help="region selection" + ) + group.add_argument("--reboot", action="store_true", help="reboot tigertail") + group.add_argument( + "--check_version", action="store_true", help="check tigertail version" + ) + return parser + def main(argv): - parser = get_parser() - opts = parser.parse_args(argv) + parser = get_parser() + opts = parser.parse_args(argv) - result = True + result = True - # Let's make sure there's a tigertail - # If nothing found in 5 seconds, fail. - c.wait_for_usb(STM_VIDPID, timeout=5., serialname=opts.serialno) + # Let's make sure there's a tigertail + # If nothing found in 5 seconds, fail. + c.wait_for_usb(STM_VIDPID, timeout=5.0, serialname=opts.serialno) - pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno) + pty = c.setup_tinyservod(STM_VIDPID, 0, serialname=opts.serialno) - if opts.bus not in ('vbus', 'cc1', 'cc2'): - c.log('Try --bus [vbus|cc1|cc2]') - result = False + if opts.bus not in ("vbus", "cc1", "cc2"): + c.log("Try --bus [vbus|cc1|cc2]") + result = False - elif opts.setserialno: - try: - c.do_serialno(opts.setserialno, pty) - except Exception: - result = False + elif opts.setserialno: + try: + c.do_serialno(opts.setserialno, pty) + except Exception: + result = False - elif opts.mux: - result &= do_mux(opts.mux, pty) + elif opts.mux: + result &= do_mux(opts.mux, pty) - elif opts.sysjump: - result &= do_sysjump(opts.sysjump, pty, serialname=opts.serialno) + elif opts.sysjump: + result &= do_sysjump(opts.sysjump, pty, serialname=opts.serialno) - elif opts.reboot: - result &= do_reboot(pty, serialname=opts.serialno) + elif opts.reboot: + result &= do_reboot(pty, serialname=opts.serialno) - elif opts.check_version: - result &= do_version(pty) + elif opts.check_version: + result &= do_version(pty) - elif opts.check_serial: - result &= do_check_serial(pty) + elif opts.check_serial: + result &= do_check_serial(pty) - elif opts.power: - result &= do_power(1, opts.bus, pty) + elif opts.power: + result &= do_power(1, opts.bus, pty) - elif opts.powerlog: - result &= do_power(opts.powerlog, opts.bus, pty) + elif opts.powerlog: + result &= do_power(opts.powerlog, opts.bus, pty) - if result: - c.log('PASS') - else: - c.log('FAIL') - sys.exit(-1) + if result: + c.log("PASS") + else: + c.log("FAIL") + sys.exit(-1) -if __name__ == '__main__': - sys.exit(main(sys.argv[1:])) +if __name__ == "__main__": + sys.exit(main(sys.argv[1:])) diff --git a/extra/usb_power/convert_power_log_board.py b/extra/usb_power/convert_power_log_board.py index 8aab77ee4c..c1b25f57db 100644 --- a/extra/usb_power/convert_power_log_board.py +++ b/extra/usb_power/convert_power_log_board.py @@ -14,6 +14,7 @@ Program to convert sweetberry config to servod config template. # Note: This is a py2/3 compatible file. from __future__ import print_function + import json import os import sys @@ -48,21 +49,25 @@ def write_to_file(file, sweetberry, inas): inas: list of inas read from board file. """ - with open(file, 'w') as pyfile: + with open(file, "w") as pyfile: - pyfile.write('inas = [\n') + pyfile.write("inas = [\n") for rec in inas: - if rec['sweetberry'] != sweetberry: + if rec["sweetberry"] != sweetberry: continue # EX : ('sweetberry', 0x40, 'SB_FW_CAM_2P8', 5.0, 1.000, 3, False), - channel, i2c_addr = Spower.CHMAP[rec['channel']] - record = (" ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')" - ",\n" % (i2c_addr, rec['name'], rec['rs'], channel)) + channel, i2c_addr = Spower.CHMAP[rec["channel"]] + record = " ('sweetberry', 0x%02x, '%s', 5.0, %f, %d, 'True')" ",\n" % ( + i2c_addr, + rec["name"], + rec["rs"], + channel, + ) pyfile.write(record) - pyfile.write(']\n') + pyfile.write("]\n") def main(argv): @@ -76,16 +81,18 @@ def main(argv): inas = fetch_records(inputf) - sweetberry = set(rec['sweetberry'] for rec in inas) + sweetberry = set(rec["sweetberry"] for rec in inas) if len(sweetberry) == 2: - print("Converting %s to %s and %s" % (inputf, basename + '_a.py', - basename + '_b.py')) - write_to_file(basename + '_a.py', 'A', inas) - write_to_file(basename + '_b.py', 'B', inas) + print( + "Converting %s to %s and %s" + % (inputf, basename + "_a.py", basename + "_b.py") + ) + write_to_file(basename + "_a.py", "A", inas) + write_to_file(basename + "_b.py", "B", inas) else: - print("Converting %s to %s" % (inputf, basename + '.py')) - write_to_file(basename + '.py', sweetberry.pop(), inas) + print("Converting %s to %s" % (inputf, basename + ".py")) + write_to_file(basename + ".py", sweetberry.pop(), inas) if __name__ == "__main__": diff --git a/extra/usb_power/convert_servo_ina.py b/extra/usb_power/convert_servo_ina.py index 1c70f31aeb..6ccd474e6c 100755 --- a/extra/usb_power/convert_servo_ina.py +++ b/extra/usb_power/convert_servo_ina.py @@ -14,67 +14,71 @@ # Note: This is a py2/3 compatible file. from __future__ import print_function + import os import sys def fetch_records(basename): - """Import records from servo_ina file. + """Import records from servo_ina file. - servo_ina files are python imports, and have a list of tuples with - the INA data. - (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True) + servo_ina files are python imports, and have a list of tuples with + the INA data. + (inatype, i2caddr, rail name, bus voltage, shunt ohms, mux, True) - Args: - basename: python import name (filename -.py) + Args: + basename: python import name (filename -.py) - Returns: - list of tuples as described above. - """ - ina_desc = __import__(basename) - return ina_desc.inas + Returns: + list of tuples as described above. + """ + ina_desc = __import__(basename) + return ina_desc.inas def main(argv): - if len(argv) != 2: - print("usage:") - print(" %s input.py" % argv[0]) - return + if len(argv) != 2: + print("usage:") + print(" %s input.py" % argv[0]) + return - inputf = argv[1] - basename = os.path.splitext(inputf)[0] - outputf = basename + '.board' - outputs = basename + '.scenario' + inputf = argv[1] + basename = os.path.splitext(inputf)[0] + outputf = basename + ".board" + outputs = basename + ".scenario" - print("Converting %s to %s, %s" % (inputf, outputf, outputs)) + print("Converting %s to %s, %s" % (inputf, outputf, outputs)) - inas = fetch_records(basename) + inas = fetch_records(basename) + boardfile = open(outputf, "w") + scenario = open(outputs, "w") - boardfile = open(outputf, 'w') - scenario = open(outputs, 'w') + boardfile.write("[\n") + scenario.write("[\n") + start = True - boardfile.write('[\n') - scenario.write('[\n') - start = True + for rec in inas: + if start: + start = False + else: + boardfile.write(",\n") + scenario.write(",\n") - for rec in inas: - if start: - start = False - else: - boardfile.write(',\n') - scenario.write(',\n') + record = ' {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}' % ( + rec[2], + rec[4], + rec[1] - 64, + ) + boardfile.write(record) + scenario.write('"%s"' % rec[2]) - record = ' {"name": "%s", "rs": %f, "sweetberry": "A", "channel": %d}' % ( - rec[2], rec[4], rec[1] - 64) - boardfile.write(record) - scenario.write('"%s"' % rec[2]) + boardfile.write("\n") + boardfile.write("]") - boardfile.write('\n') - boardfile.write(']') + scenario.write("\n") + scenario.write("]") - scenario.write('\n') - scenario.write(']') if __name__ == "__main__": - main(sys.argv) + main(sys.argv) diff --git a/extra/usb_power/powerlog.py b/extra/usb_power/powerlog.py index 82cce3daed..d893e5c6b9 100755 --- a/extra/usb_power/powerlog.py +++ b/extra/usb_power/powerlog.py @@ -14,9 +14,9 @@ # Note: This is a py2/3 compatible file. from __future__ import print_function + import argparse import array -from distutils import sysconfig import json import logging import os @@ -25,884 +25,988 @@ import struct import sys import time import traceback +from distutils import sysconfig import usb - from stats_manager import StatsManager # Directory where hdctools installs configuration files into. -LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), 'servo', - 'data') +LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), "servo", "data") # Potential config file locations: current working directory, the same directory # as powerlog.py file or LIB_DIR. -CONFIG_LOCATIONS = [os.getcwd(), os.path.dirname(os.path.realpath(__file__)), - LIB_DIR] - -def logoutput(msg): - print(msg) - sys.stdout.flush() - -def process_filename(filename): - """Find the file path from the filename. - - If filename is already the complete path, return that directly. If filename is - just the short name, look for the file in the current working directory, in - the directory of the current .py file, and then in the directory installed by - hdctools. If the file is found, return the complete path of the file. - - Args: - filename: complete file path or short file name. - - Returns: - a complete file path. - - Raises: - IOError if filename does not exist. - """ - # Check if filename is absolute path. - if os.path.isabs(filename) and os.path.isfile(filename): - return filename - # Check if filename is relative to a known config location. - for dirname in CONFIG_LOCATIONS: - file_at_dir = os.path.join(dirname, filename) - if os.path.isfile(file_at_dir): - return file_at_dir - raise IOError('No such file or directory: \'%s\'' % filename) - - -class Spower(object): - """Power class to access devices on the bus. - - Usage: - bus = Spower() - - Instance Variables: - _dev: pyUSB device object - _read_ep: pyUSB read endpoint for this interface - _write_ep: pyUSB write endpoint for this interface - """ - - # INA interface type. - INA_POWER = 1 - INA_BUSV = 2 - INA_CURRENT = 3 - INA_SHUNTV = 4 - # INA_SUFFIX is used to differentiate multiple ina types for the same power - # rail. No suffix for when ina type is 0 (non-existent) and when ina type is 1 - # (power, no suffix for backward compatibility). - INA_SUFFIX = ['', '', '_busv', '_cur', '_shuntv'] - - # usb power commands - CMD_RESET = 0x0000 - CMD_STOP = 0x0001 - CMD_ADDINA = 0x0002 - CMD_START = 0x0003 - CMD_NEXT = 0x0004 - CMD_SETTIME = 0x0005 - - # Map between header channel number (0-47) - # and INA I2C bus/addr on sweetberry. - CHMAP = { - 0: (3, 0x40), - 1: (1, 0x40), - 2: (2, 0x40), - 3: (0, 0x40), - 4: (3, 0x41), - 5: (1, 0x41), - 6: (2, 0x41), - 7: (0, 0x41), - 8: (3, 0x42), - 9: (1, 0x42), - 10: (2, 0x42), - 11: (0, 0x42), - 12: (3, 0x43), - 13: (1, 0x43), - 14: (2, 0x43), - 15: (0, 0x43), - 16: (3, 0x44), - 17: (1, 0x44), - 18: (2, 0x44), - 19: (0, 0x44), - 20: (3, 0x45), - 21: (1, 0x45), - 22: (2, 0x45), - 23: (0, 0x45), - 24: (3, 0x46), - 25: (1, 0x46), - 26: (2, 0x46), - 27: (0, 0x46), - 28: (3, 0x47), - 29: (1, 0x47), - 30: (2, 0x47), - 31: (0, 0x47), - 32: (3, 0x48), - 33: (1, 0x48), - 34: (2, 0x48), - 35: (0, 0x48), - 36: (3, 0x49), - 37: (1, 0x49), - 38: (2, 0x49), - 39: (0, 0x49), - 40: (3, 0x4a), - 41: (1, 0x4a), - 42: (2, 0x4a), - 43: (0, 0x4a), - 44: (3, 0x4b), - 45: (1, 0x4b), - 46: (2, 0x4b), - 47: (0, 0x4b), - } - - def __init__(self, board, vendor=0x18d1, - product=0x5020, interface=1, serialname=None): - self._logger = logging.getLogger(__name__) - self._board = board - - # Find the stm32. - dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) - dev_list = list(dev_g) - if dev_list is None: - raise Exception("Power", "USB device not found") - - # Check if we have multiple stm32s and we've specified the serial. - dev = None - if serialname: - for d in dev_list: - dev_serial = "PyUSB dioesn't have a stable interface" - try: - dev_serial = usb.util.get_string(d, 256, d.iSerialNumber) - except ValueError: - # Incompatible pyUsb version. - dev_serial = usb.util.get_string(d, d.iSerialNumber) - if dev_serial == serialname: - dev = d - break - if dev is None: - raise Exception("Power", "USB device(%s) not found" % serialname) - else: - try: - dev = dev_list[0] - except TypeError: - # Incompatible pyUsb version. - dev = dev_list.next() - - self._logger.debug("Found USB device: %04x:%04x", vendor, product) - self._dev = dev - - # Get an endpoint instance. - try: - dev.set_configuration() - except usb.USBError: - pass - cfg = dev.get_active_configuration() - - intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \ - i.bInterfaceClass==255 and i.bInterfaceSubClass==0x54) - - self._intf = intf - self._logger.debug("InterfaceNumber: %s", intf.bInterfaceNumber) - - read_ep = usb.util.find_descriptor( - intf, - # match the first IN endpoint - custom_match = \ - lambda e: \ - usb.util.endpoint_direction(e.bEndpointAddress) == \ - usb.util.ENDPOINT_IN - ) - - self._read_ep = read_ep - self._logger.debug("Reader endpoint: 0x%x", read_ep.bEndpointAddress) - - write_ep = usb.util.find_descriptor( - intf, - # match the first OUT endpoint - custom_match = \ - lambda e: \ - usb.util.endpoint_direction(e.bEndpointAddress) == \ - usb.util.ENDPOINT_OUT - ) - - self._write_ep = write_ep - self._logger.debug("Writer endpoint: 0x%x", write_ep.bEndpointAddress) - - self.clear_ina_struct() - - self._logger.debug("Found power logging USB endpoint.") - - def clear_ina_struct(self): - """ Clear INA description struct.""" - self._inas = [] +CONFIG_LOCATIONS = [os.getcwd(), os.path.dirname(os.path.realpath(__file__)), LIB_DIR] - def append_ina_struct(self, name, rs, port, addr, - data=None, ina_type=INA_POWER): - """Add an INA descriptor into the list of active INAs. - Args: - name: Readable name of this channel. - rs: Sense resistor value in ohms, floating point. - port: I2C channel this INA is connected to. - addr: I2C addr of this INA. - data: Misc data for special handling, board specific. - ina_type: INA function to use, power, voltage, etc. - """ - ina = {} - ina['name'] = name - ina['rs'] = rs - ina['port'] = port - ina['addr'] = addr - ina['type'] = ina_type - # Calculate INA231 Calibration register - # (see INA231 spec p.15) - # CurrentLSB = uA per div = 80mV / (Rsh * 2^15) - # CurrentLSB uA = 80000000nV / (Rsh mOhm * 0x8000) - ina['uAscale'] = 80000000. / (rs * 0x8000); - ina['uWscale'] = 25. * ina['uAscale']; - ina['mVscale'] = 1.25 - ina['uVscale'] = 2.5 - ina['data'] = data - self._inas.append(ina) - - def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=1000): - """Write command to logger logic. - - This function writes byte command values list to stm, then reads - byte status. - - Args: - write_list: list of command byte values [0~255]. - read_count: number of status byte values to read. - - Interface: - write: [command, data ... ] - read: [status ] - - Returns: - bytes read, or None on failure. - """ - self._logger.debug("Spower.wr_command(write_list=[%s] (%d), read_count=%s)", - list(bytearray(write_list)), len(write_list), read_count) - - # Clean up args from python style to correct types. - write_length = 0 - if write_list: - write_length = len(write_list) - if not read_count: - read_count = 0 - - # Send command to stm32. - if write_list: - cmd = write_list - ret = self._write_ep.write(cmd, wtimeout) - - self._logger.debug("RET: %s ", ret) - - # Read back response if necessary. - if read_count: - bytesread = self._read_ep.read(512, rtimeout) - self._logger.debug("BYTES: [%s]", bytesread) - - if len(bytesread) != read_count: - pass - - self._logger.debug("STATUS: 0x%02x", int(bytesread[0])) - if read_count == 1: - return bytesread[0] - else: - return bytesread - - return None - - def clear(self): - """Clear pending reads on the stm32""" - try: - while True: - ret = self.wr_command(b"", read_count=512, rtimeout=100, wtimeout=50) - self._logger.debug("Try Clear: read %s", - "success" if ret == 0 else "failure") - except: - pass - - def send_reset(self): - """Reset the power interface on the stm32""" - cmd = struct.pack(" time.time(): - if (integration_us > 5000): - time.sleep((integration_us / 1000000.) * sync_speed) for key in self._pwr: - records = self._pwr[key].read_line() - if not records: - continue - - for record in records: - pending_records.append(record) - - pending_records.sort(key=lambda r: r['ts']) - - aggregate_record = {"boards": set()} - for record in pending_records: - if record["berry"] not in aggregate_record["boards"]: - for rkey in record.keys(): - aggregate_record[rkey] = record[rkey] - aggregate_record["boards"].add(record["berry"]) - else: - self._logger.info("break %s, %s", record["berry"], - aggregate_record["boards"]) - break - - if aggregate_record["boards"] == set(self._pwr.keys()): - csv = "%f" % aggregate_record["ts"] - for name in self._names: - if name in aggregate_record: - multiplier = 0.001 if (self._use_mW and - name[1]==Spower.INA_POWER) else 1 - value = aggregate_record[name] * multiplier - csv += ", %.2f" % value - name_type = name[0] + Spower.INA_SUFFIX[name[1]] - self._data.AddSample(name_type, value) - else: - csv += ", " - csv += ", %d" % aggregate_record["status"] - if self._print_raw_data: - logoutput(csv) - - aggregate_record = {"boards": set()} - for r in range(0, len(self._pwr)): - pending_records.pop(0) - - except KeyboardInterrupt: - self._logger.info('\nCTRL+C caught.') - - finally: - for key in self._pwr: - self._pwr[key].stop() - self._data.CalculateStats() - if self._print_stats: - print(self._data.SummaryToString()) - save_dir = 'sweetberry%s' % time.time() - if self._stats_dir: - stats_dir = os.path.join(self._stats_dir, save_dir) - self._data.SaveSummary(stats_dir) - if self._stats_json_dir: - stats_json_dir = os.path.join(self._stats_json_dir, save_dir) - self._data.SaveSummaryJSON(stats_json_dir) - if self._raw_data_dir: - raw_data_dir = os.path.join(self._raw_data_dir, save_dir) - self._data.SaveRawData(raw_data_dir) + self._pwr[key].load_board(brdfile) + self._pwr[key].reset() + + # Allocate the rails to the appropriate boards. + used_boards = [] + for name in self._names: + success = False + for key in self._pwr.keys(): + if self._pwr[key].add_ina_name(name): + success = True + if key not in used_boards: + used_boards.append(key) + if not success: + raise Exception( + "Failed to add %s (maybe missing " + "sweetberry, or bad board file?)" % name + ) + + # Evict unused boards. + for key in list(self._pwr.keys()): + if key not in used_boards: + self._pwr.pop(key) + + for key in self._pwr.keys(): + if sync_date: + self._pwr[key].set_time(time.time() * 1000000) + else: + self._pwr[key].set_time(0) + + def process_scenario(self, name_list): + """Return list of tuples indicating name and type. + + Args: + json originated list of names, or [name, type] + Returns: + list of tuples of (name, type) defaulting to type "POWER" + Raises: exception, invalid INA type. + """ + names = [] + for entry in name_list: + if isinstance(entry, list): + name = entry[0] + if entry[1] == "POWER": + type = Spower.INA_POWER + elif entry[1] == "BUSV": + type = Spower.INA_BUSV + elif entry[1] == "CURRENT": + type = Spower.INA_CURRENT + elif entry[1] == "SHUNTV": + type = Spower.INA_SHUNTV + else: + raise Exception( + "Invalid INA type", + "Type of %s [%s] not recognized," + " try one of POWER, BUSV, CURRENT" % (entry[0], entry[1]), + ) + else: + name = entry + type = Spower.INA_POWER + + names.append((name, type)) + return names + + def start(self, integration_us_request, seconds, sync_speed=0.8): + """Starts sampling. + + Args: + integration_us_request: requested interval between sample values. + seconds: time until exit, or None to run until cancel. + sync_speed: A usb request is sent every [.8] * integration_us. + """ + # We will get back the actual integration us. + # It should be the same for all devices. + integration_us = None + for key in self._pwr: + integration_us_new = self._pwr[key].start(integration_us_request) + if integration_us: + if integration_us != integration_us_new: + raise Exception( + "FAIL", + "Integration on A: %dus != integration on B %dus" + % (integration_us, integration_us_new), + ) + integration_us = integration_us_new + + # CSV header + title = "ts:%dus" % integration_us + for name_tuple in self._names: + name, ina_type = name_tuple + + if ina_type == Spower.INA_POWER: + unit = "mW" if self._use_mW else "uW" + elif ina_type == Spower.INA_BUSV: + unit = "mV" + elif ina_type == Spower.INA_CURRENT: + unit = "uA" + elif ina_type == Spower.INA_SHUNTV: + unit = "uV" + + title += ", %s %s" % (name, unit) + name_type = name + Spower.INA_SUFFIX[ina_type] + self._data.SetUnit(name_type, unit) + title += ", status" + if self._print_raw_data: + logoutput(title) + + forever = False + if not seconds: + forever = True + end_time = time.time() + seconds + try: + pending_records = [] + while forever or end_time > time.time(): + if integration_us > 5000: + time.sleep((integration_us / 1000000.0) * sync_speed) + for key in self._pwr: + records = self._pwr[key].read_line() + if not records: + continue + + for record in records: + pending_records.append(record) + + pending_records.sort(key=lambda r: r["ts"]) + + aggregate_record = {"boards": set()} + for record in pending_records: + if record["berry"] not in aggregate_record["boards"]: + for rkey in record.keys(): + aggregate_record[rkey] = record[rkey] + aggregate_record["boards"].add(record["berry"]) + else: + self._logger.info( + "break %s, %s", record["berry"], aggregate_record["boards"] + ) + break + + if aggregate_record["boards"] == set(self._pwr.keys()): + csv = "%f" % aggregate_record["ts"] + for name in self._names: + if name in aggregate_record: + multiplier = ( + 0.001 + if (self._use_mW and name[1] == Spower.INA_POWER) + else 1 + ) + value = aggregate_record[name] * multiplier + csv += ", %.2f" % value + name_type = name[0] + Spower.INA_SUFFIX[name[1]] + self._data.AddSample(name_type, value) + else: + csv += ", " + csv += ", %d" % aggregate_record["status"] + if self._print_raw_data: + logoutput(csv) + + aggregate_record = {"boards": set()} + for r in range(0, len(self._pwr)): + pending_records.pop(0) + + except KeyboardInterrupt: + self._logger.info("\nCTRL+C caught.") + + finally: + for key in self._pwr: + self._pwr[key].stop() + self._data.CalculateStats() + if self._print_stats: + print(self._data.SummaryToString()) + save_dir = "sweetberry%s" % time.time() + if self._stats_dir: + stats_dir = os.path.join(self._stats_dir, save_dir) + self._data.SaveSummary(stats_dir) + if self._stats_json_dir: + stats_json_dir = os.path.join(self._stats_json_dir, save_dir) + self._data.SaveSummaryJSON(stats_json_dir) + if self._raw_data_dir: + raw_data_dir = os.path.join(self._raw_data_dir, save_dir) + self._data.SaveRawData(raw_data_dir) def main(argv=None): - if argv is None: - argv = sys.argv[1:] - # Command line argument description. - parser = argparse.ArgumentParser( - description="Gather CSV data from sweetberry") - parser.add_argument('-b', '--board', type=str, - help="Board configuration file, eg. my.board", default="") - parser.add_argument('-c', '--config', type=str, - help="Rail config to monitor, eg my.scenario", default="") - parser.add_argument('-A', '--serial', type=str, - help="Serial number of sweetberry A", default="") - parser.add_argument('-B', '--serial_b', type=str, - help="Serial number of sweetberry B", default="") - parser.add_argument('-t', '--integration_us', type=int, - help="Target integration time for samples", default=100000) - parser.add_argument('-s', '--seconds', type=float, - help="Seconds to run capture", default=0.) - parser.add_argument('--date', default=False, - help="Sync logged timestamp to host date", action="store_true") - parser.add_argument('--ms', default=False, - help="Print timestamp as milliseconds", action="store_true") - parser.add_argument('--mW', default=False, - help="Print power as milliwatts, otherwise default to microwatts", - action="store_true") - parser.add_argument('--slow', default=False, - help="Intentionally overflow", action="store_true") - parser.add_argument('--print_stats', default=False, action="store_true", - help="Print statistics for sweetberry readings at the end") - parser.add_argument('--save_stats', type=str, nargs='?', - dest='stats_dir', metavar='STATS_DIR', - const=os.path.dirname(os.path.abspath(__file__)), default=None, - help="Save statistics for sweetberry readings to %(metavar)s if " - "%(metavar)s is specified, %(metavar)s will be created if it does " - "not exist; if %(metavar)s is not specified but the flag is set, " - "stats will be saved to where %(prog)s is located; if this flag is " - "not set, then do not save stats") - parser.add_argument('--save_stats_json', type=str, nargs='?', - dest='stats_json_dir', metavar='STATS_JSON_DIR', - const=os.path.dirname(os.path.abspath(__file__)), default=None, - help="Save means for sweetberry readings in json to %(metavar)s if " - "%(metavar)s is specified, %(metavar)s will be created if it does " - "not exist; if %(metavar)s is not specified but the flag is set, " - "stats will be saved to where %(prog)s is located; if this flag is " - "not set, then do not save stats") - parser.add_argument('--no_print_raw_data', - dest='print_raw_data', default=True, action="store_false", - help="Not print raw sweetberry readings at real time, default is to " - "print") - parser.add_argument('--save_raw_data', type=str, nargs='?', - dest='raw_data_dir', metavar='RAW_DATA_DIR', - const=os.path.dirname(os.path.abspath(__file__)), default=None, - help="Save raw data for sweetberry readings to %(metavar)s if " - "%(metavar)s is specified, %(metavar)s will be created if it does " - "not exist; if %(metavar)s is not specified but the flag is set, " - "raw data will be saved to where %(prog)s is located; if this flag " - "is not set, then do not save raw data") - parser.add_argument('-v', '--verbose', default=False, - help="Very chatty printout", action="store_true") - - args = parser.parse_args(argv) - - root_logger = logging.getLogger(__name__) - if args.verbose: - root_logger.setLevel(logging.DEBUG) - else: - root_logger.setLevel(logging.INFO) - - # if powerlog is used through main, log to sys.stdout - if __name__ == "__main__": - stdout_handler = logging.StreamHandler(sys.stdout) - stdout_handler.setFormatter(logging.Formatter('%(levelname)s: %(message)s')) - root_logger.addHandler(stdout_handler) - - integration_us_request = args.integration_us - if not args.board: - raise Exception("Power", "No board file selected, see board.README") - if not args.config: - raise Exception("Power", "No config file selected, see board.README") - - brdfile = args.board - cfgfile = args.config - seconds = args.seconds - serial_a = args.serial - serial_b = args.serial_b - sync_date = args.date - use_ms = args.ms - use_mW = args.mW - print_stats = args.print_stats - stats_dir = args.stats_dir - stats_json_dir = args.stats_json_dir - print_raw_data = args.print_raw_data - raw_data_dir = args.raw_data_dir - - boards = [] - - sync_speed = .8 - if args.slow: - sync_speed = 1.2 - - # Set up logging interface. - powerlogger = powerlog(brdfile, cfgfile, serial_a=serial_a, serial_b=serial_b, - sync_date=sync_date, use_ms=use_ms, use_mW=use_mW, - print_stats=print_stats, stats_dir=stats_dir, - stats_json_dir=stats_json_dir, - print_raw_data=print_raw_data,raw_data_dir=raw_data_dir) - - # Start logging. - powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed) + if argv is None: + argv = sys.argv[1:] + # Command line argument description. + parser = argparse.ArgumentParser(description="Gather CSV data from sweetberry") + parser.add_argument( + "-b", + "--board", + type=str, + help="Board configuration file, eg. my.board", + default="", + ) + parser.add_argument( + "-c", + "--config", + type=str, + help="Rail config to monitor, eg my.scenario", + default="", + ) + parser.add_argument( + "-A", "--serial", type=str, help="Serial number of sweetberry A", default="" + ) + parser.add_argument( + "-B", "--serial_b", type=str, help="Serial number of sweetberry B", default="" + ) + parser.add_argument( + "-t", + "--integration_us", + type=int, + help="Target integration time for samples", + default=100000, + ) + parser.add_argument( + "-s", "--seconds", type=float, help="Seconds to run capture", default=0.0 + ) + parser.add_argument( + "--date", + default=False, + help="Sync logged timestamp to host date", + action="store_true", + ) + parser.add_argument( + "--ms", + default=False, + help="Print timestamp as milliseconds", + action="store_true", + ) + parser.add_argument( + "--mW", + default=False, + help="Print power as milliwatts, otherwise default to microwatts", + action="store_true", + ) + parser.add_argument( + "--slow", default=False, help="Intentionally overflow", action="store_true" + ) + parser.add_argument( + "--print_stats", + default=False, + action="store_true", + help="Print statistics for sweetberry readings at the end", + ) + parser.add_argument( + "--save_stats", + type=str, + nargs="?", + dest="stats_dir", + metavar="STATS_DIR", + const=os.path.dirname(os.path.abspath(__file__)), + default=None, + help="Save statistics for sweetberry readings to %(metavar)s if " + "%(metavar)s is specified, %(metavar)s will be created if it does " + "not exist; if %(metavar)s is not specified but the flag is set, " + "stats will be saved to where %(prog)s is located; if this flag is " + "not set, then do not save stats", + ) + parser.add_argument( + "--save_stats_json", + type=str, + nargs="?", + dest="stats_json_dir", + metavar="STATS_JSON_DIR", + const=os.path.dirname(os.path.abspath(__file__)), + default=None, + help="Save means for sweetberry readings in json to %(metavar)s if " + "%(metavar)s is specified, %(metavar)s will be created if it does " + "not exist; if %(metavar)s is not specified but the flag is set, " + "stats will be saved to where %(prog)s is located; if this flag is " + "not set, then do not save stats", + ) + parser.add_argument( + "--no_print_raw_data", + dest="print_raw_data", + default=True, + action="store_false", + help="Not print raw sweetberry readings at real time, default is to " "print", + ) + parser.add_argument( + "--save_raw_data", + type=str, + nargs="?", + dest="raw_data_dir", + metavar="RAW_DATA_DIR", + const=os.path.dirname(os.path.abspath(__file__)), + default=None, + help="Save raw data for sweetberry readings to %(metavar)s if " + "%(metavar)s is specified, %(metavar)s will be created if it does " + "not exist; if %(metavar)s is not specified but the flag is set, " + "raw data will be saved to where %(prog)s is located; if this flag " + "is not set, then do not save raw data", + ) + parser.add_argument( + "-v", + "--verbose", + default=False, + help="Very chatty printout", + action="store_true", + ) + + args = parser.parse_args(argv) + + root_logger = logging.getLogger(__name__) + if args.verbose: + root_logger.setLevel(logging.DEBUG) + else: + root_logger.setLevel(logging.INFO) + + # if powerlog is used through main, log to sys.stdout + if __name__ == "__main__": + stdout_handler = logging.StreamHandler(sys.stdout) + stdout_handler.setFormatter(logging.Formatter("%(levelname)s: %(message)s")) + root_logger.addHandler(stdout_handler) + + integration_us_request = args.integration_us + if not args.board: + raise Exception("Power", "No board file selected, see board.README") + if not args.config: + raise Exception("Power", "No config file selected, see board.README") + + brdfile = args.board + cfgfile = args.config + seconds = args.seconds + serial_a = args.serial + serial_b = args.serial_b + sync_date = args.date + use_ms = args.ms + use_mW = args.mW + print_stats = args.print_stats + stats_dir = args.stats_dir + stats_json_dir = args.stats_json_dir + print_raw_data = args.print_raw_data + raw_data_dir = args.raw_data_dir + + boards = [] + + sync_speed = 0.8 + if args.slow: + sync_speed = 1.2 + + # Set up logging interface. + powerlogger = powerlog( + brdfile, + cfgfile, + serial_a=serial_a, + serial_b=serial_b, + sync_date=sync_date, + use_ms=use_ms, + use_mW=use_mW, + print_stats=print_stats, + stats_dir=stats_dir, + stats_json_dir=stats_json_dir, + print_raw_data=print_raw_data, + raw_data_dir=raw_data_dir, + ) + + # Start logging. + powerlogger.start(integration_us_request, seconds, sync_speed=sync_speed) if __name__ == "__main__": - main() + main() diff --git a/extra/usb_power/powerlog_unittest.py b/extra/usb_power/powerlog_unittest.py index 1d0718530e..693826c16d 100644 --- a/extra/usb_power/powerlog_unittest.py +++ b/extra/usb_power/powerlog_unittest.py @@ -15,40 +15,42 @@ import unittest import powerlog + class TestPowerlog(unittest.TestCase): - """Test to verify powerlog util methods work as expected.""" - - def setUp(self): - """Set up data and create a temporary directory to save data and stats.""" - self.tempdir = tempfile.mkdtemp() - self.filename = 'testfile' - self.filepath = os.path.join(self.tempdir, self.filename) - with open(self.filepath, 'w') as f: - f.write('') - - def tearDown(self): - """Delete the temporary directory and its content.""" - shutil.rmtree(self.tempdir) - - def test_ProcessFilenameAbsoluteFilePath(self): - """Absolute file path is returned unchanged.""" - processed_fname = powerlog.process_filename(self.filepath) - self.assertEqual(self.filepath, processed_fname) - - def test_ProcessFilenameRelativeFilePath(self): - """Finds relative file path inside a known config location.""" - original = powerlog.CONFIG_LOCATIONS - powerlog.CONFIG_LOCATIONS = [self.tempdir] - processed_fname = powerlog.process_filename(self.filename) - try: - self.assertEqual(self.filepath, processed_fname) - finally: - powerlog.CONFIG_LOCATIONS = original - - def test_ProcessFilenameInvalid(self): - """IOError is raised when file cannot be found by any of the four ways.""" - with self.assertRaises(IOError): - powerlog.process_filename(self.filename) - -if __name__ == '__main__': - unittest.main() + """Test to verify powerlog util methods work as expected.""" + + def setUp(self): + """Set up data and create a temporary directory to save data and stats.""" + self.tempdir = tempfile.mkdtemp() + self.filename = "testfile" + self.filepath = os.path.join(self.tempdir, self.filename) + with open(self.filepath, "w") as f: + f.write("") + + def tearDown(self): + """Delete the temporary directory and its content.""" + shutil.rmtree(self.tempdir) + + def test_ProcessFilenameAbsoluteFilePath(self): + """Absolute file path is returned unchanged.""" + processed_fname = powerlog.process_filename(self.filepath) + self.assertEqual(self.filepath, processed_fname) + + def test_ProcessFilenameRelativeFilePath(self): + """Finds relative file path inside a known config location.""" + original = powerlog.CONFIG_LOCATIONS + powerlog.CONFIG_LOCATIONS = [self.tempdir] + processed_fname = powerlog.process_filename(self.filename) + try: + self.assertEqual(self.filepath, processed_fname) + finally: + powerlog.CONFIG_LOCATIONS = original + + def test_ProcessFilenameInvalid(self): + """IOError is raised when file cannot be found by any of the four ways.""" + with self.assertRaises(IOError): + powerlog.process_filename(self.filename) + + +if __name__ == "__main__": + unittest.main() diff --git a/extra/usb_power/stats_manager.py b/extra/usb_power/stats_manager.py index 0f8c3fcb15..633312311d 100644 --- a/extra/usb_power/stats_manager.py +++ b/extra/usb_power/stats_manager.py @@ -20,382 +20,391 @@ import os import numpy -STATS_PREFIX = '@@' -NAN_TAG = '*' -NAN_DESCRIPTION = '%s domains contain NaN samples' % NAN_TAG +STATS_PREFIX = "@@" +NAN_TAG = "*" +NAN_DESCRIPTION = "%s domains contain NaN samples" % NAN_TAG LONG_UNIT = { - '': 'N/A', - 'mW': 'milliwatt', - 'uW': 'microwatt', - 'mV': 'millivolt', - 'uA': 'microamp', - 'uV': 'microvolt' + "": "N/A", + "mW": "milliwatt", + "uW": "microwatt", + "mV": "millivolt", + "uA": "microamp", + "uV": "microvolt", } class StatsManagerError(Exception): - """Errors in StatsManager class.""" - pass + """Errors in StatsManager class.""" + pass -class StatsManager(object): - """Calculates statistics for several lists of data(float). - - Example usage: - - >>> stats = StatsManager(title='Title Banner') - >>> stats.AddSample(TIME_KEY, 50.0) - >>> stats.AddSample(TIME_KEY, 25.0) - >>> stats.AddSample(TIME_KEY, 40.0) - >>> stats.AddSample(TIME_KEY, 10.0) - >>> stats.AddSample(TIME_KEY, 10.0) - >>> stats.AddSample('frobnicate', 11.5) - >>> stats.AddSample('frobnicate', 9.0) - >>> stats.AddSample('foobar', 11111.0) - >>> stats.AddSample('foobar', 22222.0) - >>> stats.CalculateStats() - >>> print(stats.SummaryToString()) - ` @@-------------------------------------------------------------- - ` @@ Title Banner - @@-------------------------------------------------------------- - @@ NAME COUNT MEAN STDDEV MAX MIN - @@ sample_msecs 4 31.25 15.16 50.00 10.00 - @@ foobar 2 16666.50 5555.50 22222.00 11111.00 - @@ frobnicate 2 10.25 1.25 11.50 9.00 - ` @@-------------------------------------------------------------- - - Attributes: - _data: dict of list of readings for each domain(key) - _unit: dict of unit for each domain(key) - _smid: id supplied to differentiate data output to other StatsManager - instances that potentially save to the same directory - if smid all output files will be named |smid|_|fname| - _title: title to add as banner to formatted summary. If no title, - no banner gets added - _order: list of formatting order for domains. Domains not listed are - displayed in sorted order - _hide_domains: collection of domains to hide when formatting summary string - _accept_nan: flag to indicate if NaN samples are acceptable - _nan_domains: set to keep track of which domains contain NaN samples - _summary: dict of stats per domain (key): min, max, count, mean, stddev - _logger = StatsManager logger - - Note: - _summary is empty until CalculateStats() is called, and is updated when - CalculateStats() is called. - """ - - # pylint: disable=W0102 - def __init__(self, smid='', title='', order=[], hide_domains=[], - accept_nan=True): - """Initialize infrastructure for data and their statistics.""" - self._title = title - self._data = collections.defaultdict(list) - self._unit = collections.defaultdict(str) - self._smid = smid - self._order = order - self._hide_domains = hide_domains - self._accept_nan = accept_nan - self._nan_domains = set() - self._summary = {} - self._logger = logging.getLogger(type(self).__name__) - - def AddSample(self, domain, sample): - """Add one sample for a domain. - - Args: - domain: the domain name for the sample. - sample: one time sample for domain, expect type float. - - Raises: - StatsManagerError: if trying to add NaN and |_accept_nan| is false - """ - try: - sample = float(sample) - except ValueError: - # if we don't accept nan this will be caught below - self._logger.debug('sample %s for domain %s is not a number. Making NaN', - sample, domain) - sample = float('NaN') - if not self._accept_nan and math.isnan(sample): - raise StatsManagerError('accept_nan is false. Cannot add NaN sample.') - self._data[domain].append(sample) - if math.isnan(sample): - self._nan_domains.add(domain) - - def SetUnit(self, domain, unit): - """Set the unit for a domain. - - There can be only one unit for each domain. Setting unit twice will - overwrite the original unit. - - Args: - domain: the domain name. - unit: unit of the domain. - """ - if domain in self._unit: - self._logger.warning('overwriting the unit of %s, old unit is %s, new ' - 'unit is %s.', domain, self._unit[domain], unit) - self._unit[domain] = unit - def CalculateStats(self): - """Calculate stats for all domain-data pairs. - - First erases all previous stats, then calculate stats for all data. - """ - self._summary = {} - for domain, data in self._data.items(): - data_np = numpy.array(data) - self._summary[domain] = { - 'mean': numpy.nanmean(data_np), - 'min': numpy.nanmin(data_np), - 'max': numpy.nanmax(data_np), - 'stddev': numpy.nanstd(data_np), - 'count': data_np.size, - } - - @property - def DomainsToDisplay(self): - """List of domains that the manager will output in summaries.""" - return set(self._summary.keys()) - set(self._hide_domains) - - @property - def NanInOutput(self): - """Return whether any of the domains to display have NaN values.""" - return bool(len(set(self._nan_domains) & self.DomainsToDisplay)) - - def _SummaryTable(self): - """Generate the matrix to output as a summary. - - Returns: - A 2d matrix of headers and their data for each domain - e.g. - [[NAME, COUNT, MEAN, STDDEV, MAX, MIN], - [pp5000_mw, 10, 50, 0, 50, 50]] - """ - headers = ('NAME', 'COUNT', 'MEAN', 'STDDEV', 'MAX', 'MIN') - table = [headers] - # determine what domains to display & and the order - domains_to_display = self.DomainsToDisplay - display_order = [key for key in self._order if key in domains_to_display] - domains_to_display -= set(display_order) - display_order.extend(sorted(domains_to_display)) - for domain in display_order: - stats = self._summary[domain] - if not domain.endswith(self._unit[domain]): - domain = '%s_%s' % (domain, self._unit[domain]) - if domain in self._nan_domains: - domain = '%s%s' % (domain, NAN_TAG) - row = [domain] - row.append(str(stats['count'])) - for entry in headers[2:]: - row.append('%.2f' % stats[entry.lower()]) - table.append(row) - return table - - def SummaryToMarkdownString(self): - """Format the summary into a b/ compatible markdown table string. - - This requires this sort of output format - - | header1 | header2 | header3 | ... - | --------- | --------- | --------- | ... - | sample1h1 | sample1h2 | sample1h3 | ... - . - . - . - - Returns: - formatted summary string. - """ - # All we need to do before processing is insert a row of '-' between - # the headers, and the data - table = self._SummaryTable() - columns = len(table[0]) - # Using '-:' to allow the numbers to be right aligned - sep_row = ['-'] + ['-:'] * (columns - 1) - table.insert(1, sep_row) - text_rows = ['|'.join(r) for r in table] - body = '\n'.join(['|%s|' % r for r in text_rows]) - if self._title: - title_section = '**%s** \n\n' % self._title - body = title_section + body - # Make sure that the body is terminated with a newline. - return body + '\n' - - def SummaryToString(self, prefix=STATS_PREFIX): - """Format summary into a string, ready for pretty print. - - See class description for format example. - - Args: - prefix: start every row in summary string with prefix, for easier reading. - - Returns: - formatted summary string. - """ - table = self._SummaryTable() - max_col_width = [] - for col_idx in range(len(table[0])): - col_item_widths = [len(row[col_idx]) for row in table] - max_col_width.append(max(col_item_widths)) - - formatted_lines = [] - for row in table: - formatted_row = prefix + ' ' - for i in range(len(row)): - formatted_row += row[i].rjust(max_col_width[i] + 2) - formatted_lines.append(formatted_row) - if self.NanInOutput: - formatted_lines.append('%s %s' % (prefix, NAN_DESCRIPTION)) - - if self._title: - line_length = len(formatted_lines[0]) - dec_length = len(prefix) - # trim title to be at most as long as the longest line without the prefix - title = self._title[:(line_length - dec_length)] - # line is a seperator line consisting of ----- - line = '%s%s' % (prefix, '-' * (line_length - dec_length)) - # prepend the prefix to the centered title - padded_title = '%s%s' % (prefix, title.center(line_length)[dec_length:]) - formatted_lines = [line, padded_title, line] + formatted_lines + [line] - formatted_output = '\n'.join(formatted_lines) - return formatted_output - - def GetSummary(self): - """Getter for summary.""" - return self._summary - - def _MakeUniqueFName(self, fname): - """prepend |_smid| to fname & rotate fname to ensure uniqueness. - - Before saving a file through the StatsManager, make sure that the filename - is unique, first by prepending the smid if any and otherwise by appending - increasing integer suffixes until the filename is unique. - - If |smid| is defined /path/to/example/file.txt becomes - /path/to/example/{smid}_file.txt. - - The rotation works by changing /path/to/example/somename.txt to - /path/to/example/somename1.txt if the first one already exists on the - system. - - Note: this is not thread-safe. While it makes sense to use StatsManager - in a threaded data-collection, the data retrieval should happen in a - single threaded environment to ensure files don't get potentially clobbered. - - Args: - fname: filename to ensure uniqueness. - - Returns: - {smid_}fname{tag}.[b].ext - the smid portion gets prepended if |smid| is defined - the tag portion gets appended if necessary to ensure unique fname - """ - fdir = os.path.dirname(fname) - base, ext = os.path.splitext(os.path.basename(fname)) - if self._smid: - base = '%s_%s' % (self._smid, base) - unique_fname = os.path.join(fdir, '%s%s' % (base, ext)) - tag = 0 - while os.path.exists(unique_fname): - old_fname = unique_fname - unique_fname = os.path.join(fdir, '%s%d%s' % (base, tag, ext)) - self._logger.warning('Attempted to store stats information at %s, but ' - 'file already exists. Attempting to store at %s ' - 'now.', old_fname, unique_fname) - tag += 1 - return unique_fname - - def SaveSummary(self, directory, fname='summary.txt', prefix=STATS_PREFIX): - """Save summary to file. - - Args: - directory: directory to save the summary in. - fname: filename to save summary under. - prefix: start every row in summary string with prefix, for easier reading. - - Returns: - full path of summary save location - """ - summary_str = self.SummaryToString(prefix=prefix) + '\n' - return self._SaveSummary(summary_str, directory, fname) - - def SaveSummaryJSON(self, directory, fname='summary.json'): - """Save summary (only MEAN) into a JSON file. - - Args: - directory: directory to save the JSON summary in. - fname: filename to save summary under. - - Returns: - full path of summary save location - """ - data = {} - for domain in self._summary: - unit = LONG_UNIT.get(self._unit[domain], self._unit[domain]) - data_entry = {'mean': self._summary[domain]['mean'], 'unit': unit} - data[domain] = data_entry - summary_str = json.dumps(data, indent=2) - return self._SaveSummary(summary_str, directory, fname) - - def SaveSummaryMD(self, directory, fname='summary.md'): - """Save summary into a MD file to paste into b/. - - Args: - directory: directory to save the MD summary in. - fname: filename to save summary under. - - Returns: - full path of summary save location +class StatsManager(object): + """Calculates statistics for several lists of data(float). + + Example usage: + + >>> stats = StatsManager(title='Title Banner') + >>> stats.AddSample(TIME_KEY, 50.0) + >>> stats.AddSample(TIME_KEY, 25.0) + >>> stats.AddSample(TIME_KEY, 40.0) + >>> stats.AddSample(TIME_KEY, 10.0) + >>> stats.AddSample(TIME_KEY, 10.0) + >>> stats.AddSample('frobnicate', 11.5) + >>> stats.AddSample('frobnicate', 9.0) + >>> stats.AddSample('foobar', 11111.0) + >>> stats.AddSample('foobar', 22222.0) + >>> stats.CalculateStats() + >>> print(stats.SummaryToString()) + ` @@-------------------------------------------------------------- + ` @@ Title Banner + @@-------------------------------------------------------------- + @@ NAME COUNT MEAN STDDEV MAX MIN + @@ sample_msecs 4 31.25 15.16 50.00 10.00 + @@ foobar 2 16666.50 5555.50 22222.00 11111.00 + @@ frobnicate 2 10.25 1.25 11.50 9.00 + ` @@-------------------------------------------------------------- + + Attributes: + _data: dict of list of readings for each domain(key) + _unit: dict of unit for each domain(key) + _smid: id supplied to differentiate data output to other StatsManager + instances that potentially save to the same directory + if smid all output files will be named |smid|_|fname| + _title: title to add as banner to formatted summary. If no title, + no banner gets added + _order: list of formatting order for domains. Domains not listed are + displayed in sorted order + _hide_domains: collection of domains to hide when formatting summary string + _accept_nan: flag to indicate if NaN samples are acceptable + _nan_domains: set to keep track of which domains contain NaN samples + _summary: dict of stats per domain (key): min, max, count, mean, stddev + _logger = StatsManager logger + + Note: + _summary is empty until CalculateStats() is called, and is updated when + CalculateStats() is called. """ - summary_str = self.SummaryToMarkdownString() - return self._SaveSummary(summary_str, directory, fname) - def _SaveSummary(self, output_str, directory, fname): - """Wrote |output_str| to |fname|. - - Args: - output_str: formatted output string - directory: directory to save the summary in. - fname: filename to save summary under. - - Returns: - full path of summary save location - """ - if not os.path.exists(directory): - os.makedirs(directory) - fname = self._MakeUniqueFName(os.path.join(directory, fname)) - with open(fname, 'w') as f: - f.write(output_str) - return fname - - def GetRawData(self): - """Getter for all raw_data.""" - return self._data - - def SaveRawData(self, directory, dirname='raw_data'): - """Save raw data to file. - - Args: - directory: directory to create the raw data folder in. - dirname: folder in which raw data live. - - Returns: - list of full path of each domain's raw data save location - """ - if not os.path.exists(directory): - os.makedirs(directory) - dirname = os.path.join(directory, dirname) - if not os.path.exists(dirname): - os.makedirs(dirname) - fnames = [] - for domain, data in self._data.items(): - if not domain.endswith(self._unit[domain]): - domain = '%s_%s' % (domain, self._unit[domain]) - fname = self._MakeUniqueFName(os.path.join(dirname, '%s.txt' % domain)) - with open(fname, 'w') as f: - f.write('\n'.join('%.2f' % sample for sample in data) + '\n') - fnames.append(fname) - return fnames + # pylint: disable=W0102 + def __init__(self, smid="", title="", order=[], hide_domains=[], accept_nan=True): + """Initialize infrastructure for data and their statistics.""" + self._title = title + self._data = collections.defaultdict(list) + self._unit = collections.defaultdict(str) + self._smid = smid + self._order = order + self._hide_domains = hide_domains + self._accept_nan = accept_nan + self._nan_domains = set() + self._summary = {} + self._logger = logging.getLogger(type(self).__name__) + + def AddSample(self, domain, sample): + """Add one sample for a domain. + + Args: + domain: the domain name for the sample. + sample: one time sample for domain, expect type float. + + Raises: + StatsManagerError: if trying to add NaN and |_accept_nan| is false + """ + try: + sample = float(sample) + except ValueError: + # if we don't accept nan this will be caught below + self._logger.debug( + "sample %s for domain %s is not a number. Making NaN", sample, domain + ) + sample = float("NaN") + if not self._accept_nan and math.isnan(sample): + raise StatsManagerError("accept_nan is false. Cannot add NaN sample.") + self._data[domain].append(sample) + if math.isnan(sample): + self._nan_domains.add(domain) + + def SetUnit(self, domain, unit): + """Set the unit for a domain. + + There can be only one unit for each domain. Setting unit twice will + overwrite the original unit. + + Args: + domain: the domain name. + unit: unit of the domain. + """ + if domain in self._unit: + self._logger.warning( + "overwriting the unit of %s, old unit is %s, new " "unit is %s.", + domain, + self._unit[domain], + unit, + ) + self._unit[domain] = unit + + def CalculateStats(self): + """Calculate stats for all domain-data pairs. + + First erases all previous stats, then calculate stats for all data. + """ + self._summary = {} + for domain, data in self._data.items(): + data_np = numpy.array(data) + self._summary[domain] = { + "mean": numpy.nanmean(data_np), + "min": numpy.nanmin(data_np), + "max": numpy.nanmax(data_np), + "stddev": numpy.nanstd(data_np), + "count": data_np.size, + } + + @property + def DomainsToDisplay(self): + """List of domains that the manager will output in summaries.""" + return set(self._summary.keys()) - set(self._hide_domains) + + @property + def NanInOutput(self): + """Return whether any of the domains to display have NaN values.""" + return bool(len(set(self._nan_domains) & self.DomainsToDisplay)) + + def _SummaryTable(self): + """Generate the matrix to output as a summary. + + Returns: + A 2d matrix of headers and their data for each domain + e.g. + [[NAME, COUNT, MEAN, STDDEV, MAX, MIN], + [pp5000_mw, 10, 50, 0, 50, 50]] + """ + headers = ("NAME", "COUNT", "MEAN", "STDDEV", "MAX", "MIN") + table = [headers] + # determine what domains to display & and the order + domains_to_display = self.DomainsToDisplay + display_order = [key for key in self._order if key in domains_to_display] + domains_to_display -= set(display_order) + display_order.extend(sorted(domains_to_display)) + for domain in display_order: + stats = self._summary[domain] + if not domain.endswith(self._unit[domain]): + domain = "%s_%s" % (domain, self._unit[domain]) + if domain in self._nan_domains: + domain = "%s%s" % (domain, NAN_TAG) + row = [domain] + row.append(str(stats["count"])) + for entry in headers[2:]: + row.append("%.2f" % stats[entry.lower()]) + table.append(row) + return table + + def SummaryToMarkdownString(self): + """Format the summary into a b/ compatible markdown table string. + + This requires this sort of output format + + | header1 | header2 | header3 | ... + | --------- | --------- | --------- | ... + | sample1h1 | sample1h2 | sample1h3 | ... + . + . + . + + Returns: + formatted summary string. + """ + # All we need to do before processing is insert a row of '-' between + # the headers, and the data + table = self._SummaryTable() + columns = len(table[0]) + # Using '-:' to allow the numbers to be right aligned + sep_row = ["-"] + ["-:"] * (columns - 1) + table.insert(1, sep_row) + text_rows = ["|".join(r) for r in table] + body = "\n".join(["|%s|" % r for r in text_rows]) + if self._title: + title_section = "**%s** \n\n" % self._title + body = title_section + body + # Make sure that the body is terminated with a newline. + return body + "\n" + + def SummaryToString(self, prefix=STATS_PREFIX): + """Format summary into a string, ready for pretty print. + + See class description for format example. + + Args: + prefix: start every row in summary string with prefix, for easier reading. + + Returns: + formatted summary string. + """ + table = self._SummaryTable() + max_col_width = [] + for col_idx in range(len(table[0])): + col_item_widths = [len(row[col_idx]) for row in table] + max_col_width.append(max(col_item_widths)) + + formatted_lines = [] + for row in table: + formatted_row = prefix + " " + for i in range(len(row)): + formatted_row += row[i].rjust(max_col_width[i] + 2) + formatted_lines.append(formatted_row) + if self.NanInOutput: + formatted_lines.append("%s %s" % (prefix, NAN_DESCRIPTION)) + + if self._title: + line_length = len(formatted_lines[0]) + dec_length = len(prefix) + # trim title to be at most as long as the longest line without the prefix + title = self._title[: (line_length - dec_length)] + # line is a seperator line consisting of ----- + line = "%s%s" % (prefix, "-" * (line_length - dec_length)) + # prepend the prefix to the centered title + padded_title = "%s%s" % (prefix, title.center(line_length)[dec_length:]) + formatted_lines = [line, padded_title, line] + formatted_lines + [line] + formatted_output = "\n".join(formatted_lines) + return formatted_output + + def GetSummary(self): + """Getter for summary.""" + return self._summary + + def _MakeUniqueFName(self, fname): + """prepend |_smid| to fname & rotate fname to ensure uniqueness. + + Before saving a file through the StatsManager, make sure that the filename + is unique, first by prepending the smid if any and otherwise by appending + increasing integer suffixes until the filename is unique. + + If |smid| is defined /path/to/example/file.txt becomes + /path/to/example/{smid}_file.txt. + + The rotation works by changing /path/to/example/somename.txt to + /path/to/example/somename1.txt if the first one already exists on the + system. + + Note: this is not thread-safe. While it makes sense to use StatsManager + in a threaded data-collection, the data retrieval should happen in a + single threaded environment to ensure files don't get potentially clobbered. + + Args: + fname: filename to ensure uniqueness. + + Returns: + {smid_}fname{tag}.[b].ext + the smid portion gets prepended if |smid| is defined + the tag portion gets appended if necessary to ensure unique fname + """ + fdir = os.path.dirname(fname) + base, ext = os.path.splitext(os.path.basename(fname)) + if self._smid: + base = "%s_%s" % (self._smid, base) + unique_fname = os.path.join(fdir, "%s%s" % (base, ext)) + tag = 0 + while os.path.exists(unique_fname): + old_fname = unique_fname + unique_fname = os.path.join(fdir, "%s%d%s" % (base, tag, ext)) + self._logger.warning( + "Attempted to store stats information at %s, but " + "file already exists. Attempting to store at %s " + "now.", + old_fname, + unique_fname, + ) + tag += 1 + return unique_fname + + def SaveSummary(self, directory, fname="summary.txt", prefix=STATS_PREFIX): + """Save summary to file. + + Args: + directory: directory to save the summary in. + fname: filename to save summary under. + prefix: start every row in summary string with prefix, for easier reading. + + Returns: + full path of summary save location + """ + summary_str = self.SummaryToString(prefix=prefix) + "\n" + return self._SaveSummary(summary_str, directory, fname) + + def SaveSummaryJSON(self, directory, fname="summary.json"): + """Save summary (only MEAN) into a JSON file. + + Args: + directory: directory to save the JSON summary in. + fname: filename to save summary under. + + Returns: + full path of summary save location + """ + data = {} + for domain in self._summary: + unit = LONG_UNIT.get(self._unit[domain], self._unit[domain]) + data_entry = {"mean": self._summary[domain]["mean"], "unit": unit} + data[domain] = data_entry + summary_str = json.dumps(data, indent=2) + return self._SaveSummary(summary_str, directory, fname) + + def SaveSummaryMD(self, directory, fname="summary.md"): + """Save summary into a MD file to paste into b/. + + Args: + directory: directory to save the MD summary in. + fname: filename to save summary under. + + Returns: + full path of summary save location + """ + summary_str = self.SummaryToMarkdownString() + return self._SaveSummary(summary_str, directory, fname) + + def _SaveSummary(self, output_str, directory, fname): + """Wrote |output_str| to |fname|. + + Args: + output_str: formatted output string + directory: directory to save the summary in. + fname: filename to save summary under. + + Returns: + full path of summary save location + """ + if not os.path.exists(directory): + os.makedirs(directory) + fname = self._MakeUniqueFName(os.path.join(directory, fname)) + with open(fname, "w") as f: + f.write(output_str) + return fname + + def GetRawData(self): + """Getter for all raw_data.""" + return self._data + + def SaveRawData(self, directory, dirname="raw_data"): + """Save raw data to file. + + Args: + directory: directory to create the raw data folder in. + dirname: folder in which raw data live. + + Returns: + list of full path of each domain's raw data save location + """ + if not os.path.exists(directory): + os.makedirs(directory) + dirname = os.path.join(directory, dirname) + if not os.path.exists(dirname): + os.makedirs(dirname) + fnames = [] + for domain, data in self._data.items(): + if not domain.endswith(self._unit[domain]): + domain = "%s_%s" % (domain, self._unit[domain]) + fname = self._MakeUniqueFName(os.path.join(dirname, "%s.txt" % domain)) + with open(fname, "w") as f: + f.write("\n".join("%.2f" % sample for sample in data) + "\n") + fnames.append(fname) + return fnames diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py index beb9984b93..37a472af98 100644 --- a/extra/usb_power/stats_manager_unittest.py +++ b/extra/usb_power/stats_manager_unittest.py @@ -9,6 +9,7 @@ """Unit tests for StatsManager.""" from __future__ import print_function + import json import os import re @@ -20,296 +21,304 @@ import stats_manager class TestStatsManager(unittest.TestCase): - """Test to verify StatsManager methods work as expected. - - StatsManager should collect raw data, calculate their statistics, and save - them in expected format. - """ - - def _populate_mock_stats(self): - """Create a populated & processed StatsManager to test data retrieval.""" - self.data.AddSample('A', 99999.5) - self.data.AddSample('A', 100000.5) - self.data.SetUnit('A', 'uW') - self.data.SetUnit('A', 'mW') - self.data.AddSample('B', 1.5) - self.data.AddSample('B', 2.5) - self.data.AddSample('B', 3.5) - self.data.SetUnit('B', 'mV') - self.data.CalculateStats() - - def _populate_mock_stats_no_unit(self): - self.data.AddSample('B', 1000) - self.data.AddSample('A', 200) - self.data.SetUnit('A', 'blue') - - def setUp(self): - """Set up StatsManager and create a temporary directory for test.""" - self.tempdir = tempfile.mkdtemp() - self.data = stats_manager.StatsManager() - - def tearDown(self): - """Delete the temporary directory and its content.""" - shutil.rmtree(self.tempdir) - - def test_AddSample(self): - """Adding a sample successfully adds a sample.""" - self.data.AddSample('Test', 1000) - self.data.SetUnit('Test', 'test') - self.data.CalculateStats() - summary = self.data.GetSummary() - self.assertEqual(1, summary['Test']['count']) - - def test_AddSampleNoFloatAcceptNaN(self): - """Adding a non-number adds 'NaN' and doesn't raise an exception.""" - self.data.AddSample('Test', 10) - self.data.AddSample('Test', 20) - # adding a fake NaN: one that gets converted into NaN internally - self.data.AddSample('Test', 'fiesta') - # adding a real NaN - self.data.AddSample('Test', float('NaN')) - self.data.SetUnit('Test', 'test') - self.data.CalculateStats() - summary = self.data.GetSummary() - # assert that 'NaN' as added. - self.assertEqual(4, summary['Test']['count']) - # assert that mean, min, and max calculatings ignore the 'NaN' - self.assertEqual(10, summary['Test']['min']) - self.assertEqual(20, summary['Test']['max']) - self.assertEqual(15, summary['Test']['mean']) - - def test_AddSampleNoFloatNotAcceptNaN(self): - """Adding a non-number raises a StatsManagerError if accept_nan is False.""" - self.data = stats_manager.StatsManager(accept_nan=False) - with self.assertRaisesRegexp(stats_manager.StatsManagerError, - 'accept_nan is false. Cannot add NaN sample.'): - # adding a fake NaN: one that gets converted into NaN internally - self.data.AddSample('Test', 'fiesta') - with self.assertRaisesRegexp(stats_manager.StatsManagerError, - 'accept_nan is false. Cannot add NaN sample.'): - # adding a real NaN - self.data.AddSample('Test', float('NaN')) - - def test_AddSampleNoUnit(self): - """Not adding a unit does not cause an exception on CalculateStats().""" - self.data.AddSample('Test', 17) - self.data.CalculateStats() - summary = self.data.GetSummary() - self.assertEqual(1, summary['Test']['count']) - - def test_UnitSuffix(self): - """Unit gets appended as a suffix in the displayed summary.""" - self.data.AddSample('test', 250) - self.data.SetUnit('test', 'mw') - self.data.CalculateStats() - summary_str = self.data.SummaryToString() - self.assertIn('test_mw', summary_str) - - def test_DoubleUnitSuffix(self): - """If domain already ends in unit, verify that unit doesn't get appended.""" - self.data.AddSample('test_mw', 250) - self.data.SetUnit('test_mw', 'mw') - self.data.CalculateStats() - summary_str = self.data.SummaryToString() - self.assertIn('test_mw', summary_str) - self.assertNotIn('test_mw_mw', summary_str) - - def test_GetRawData(self): - """GetRawData returns exact same data as fed in.""" - self._populate_mock_stats() - raw_data = self.data.GetRawData() - self.assertListEqual([99999.5, 100000.5], raw_data['A']) - self.assertListEqual([1.5, 2.5, 3.5], raw_data['B']) - - def test_GetSummary(self): - """GetSummary returns expected stats about the data fed in.""" - self._populate_mock_stats() - summary = self.data.GetSummary() - self.assertEqual(2, summary['A']['count']) - self.assertAlmostEqual(100000.5, summary['A']['max']) - self.assertAlmostEqual(99999.5, summary['A']['min']) - self.assertAlmostEqual(0.5, summary['A']['stddev']) - self.assertAlmostEqual(100000.0, summary['A']['mean']) - self.assertEqual(3, summary['B']['count']) - self.assertAlmostEqual(3.5, summary['B']['max']) - self.assertAlmostEqual(1.5, summary['B']['min']) - self.assertAlmostEqual(0.81649658092773, summary['B']['stddev']) - self.assertAlmostEqual(2.5, summary['B']['mean']) - - def test_SaveRawData(self): - """SaveRawData stores same data as fed in.""" - self._populate_mock_stats() - dirname = 'unittest_raw_data' - expected_files = set(['A_mW.txt', 'B_mV.txt']) - fnames = self.data.SaveRawData(self.tempdir, dirname) - files_returned = set([os.path.basename(f) for f in fnames]) - # Assert that only the expected files got returned. - self.assertEqual(expected_files, files_returned) - # Assert that only the returned files are in the outdir. - self.assertEqual(set(os.listdir(os.path.join(self.tempdir, dirname))), - files_returned) - for fname in fnames: - with open(fname, 'r') as f: - if 'A_mW' in fname: - self.assertEqual('99999.50', f.readline().strip()) - self.assertEqual('100000.50', f.readline().strip()) - if 'B_mV' in fname: - self.assertEqual('1.50', f.readline().strip()) - self.assertEqual('2.50', f.readline().strip()) - self.assertEqual('3.50', f.readline().strip()) - - def test_SaveRawDataNoUnit(self): - """SaveRawData appends no unit suffix if the unit is not specified.""" - self._populate_mock_stats_no_unit() - self.data.CalculateStats() - outdir = 'unittest_raw_data' - files = self.data.SaveRawData(self.tempdir, outdir) - files = [os.path.basename(f) for f in files] - # Verify nothing gets appended to domain for filename if no unit exists. - self.assertIn('B.txt', files) - - def test_SaveRawDataSMID(self): - """SaveRawData uses the smid when creating output filename.""" - identifier = 'ec' - self.data = stats_manager.StatsManager(smid=identifier) - self._populate_mock_stats() - files = self.data.SaveRawData(self.tempdir) - for fname in files: - self.assertTrue(os.path.basename(fname).startswith(identifier)) - - def test_SummaryToStringNaNHelp(self): - """NaN containing row gets tagged with *, help banner gets added.""" - help_banner_exp = '%s %s' % (stats_manager.STATS_PREFIX, - stats_manager.NAN_DESCRIPTION) - nan_domain = 'A-domain' - nan_domain_exp = '%s%s' % (nan_domain, stats_manager.NAN_TAG) - # NaN helper banner is added when a NaN domain is found & domain gets tagged - data = stats_manager.StatsManager() - data.AddSample(nan_domain, float('NaN')) - data.AddSample(nan_domain, 17) - data.AddSample('B-domain', 17) - data.CalculateStats() - summarystr = data.SummaryToString() - self.assertIn(help_banner_exp, summarystr) - self.assertIn(nan_domain_exp, summarystr) - # NaN helper banner is not added when no NaN domain output, no tagging - data = stats_manager.StatsManager() - # nan_domain in this scenario does not contain any NaN - data.AddSample(nan_domain, 19) - data.AddSample('B-domain', 17) - data.CalculateStats() - summarystr = data.SummaryToString() - self.assertNotIn(help_banner_exp, summarystr) - self.assertNotIn(nan_domain_exp, summarystr) - - def test_SummaryToStringTitle(self): - """Title shows up in SummaryToString if title specified.""" - title = 'titulo' - data = stats_manager.StatsManager(title=title) - self._populate_mock_stats() - summary_str = data.SummaryToString() - self.assertIn(title, summary_str) - - def test_SummaryToStringHideDomains(self): - """Keys indicated in hide_domains are not printed in the summary.""" - data = stats_manager.StatsManager(hide_domains=['A-domain']) - data.AddSample('A-domain', 17) - data.AddSample('B-domain', 17) - data.CalculateStats() - summary_str = data.SummaryToString() - self.assertIn('B-domain', summary_str) - self.assertNotIn('A-domain', summary_str) - - def test_SummaryToStringOrder(self): - """Order passed into StatsManager is honoured when formatting summary.""" - # StatsManager that should print D & B first, and the subsequent elements - # are sorted. - d_b_a_c_regexp = re.compile('D-domain.*B-domain.*A-domain.*C-domain', - re.DOTALL) - data = stats_manager.StatsManager(order=['D-domain', 'B-domain']) - data.AddSample('A-domain', 17) - data.AddSample('B-domain', 17) - data.AddSample('C-domain', 17) - data.AddSample('D-domain', 17) - data.CalculateStats() - summary_str = data.SummaryToString() - self.assertRegexpMatches(summary_str, d_b_a_c_regexp) - - def test_MakeUniqueFName(self): - data = stats_manager.StatsManager() - testfile = os.path.join(self.tempdir, 'testfile.txt') - with open(testfile, 'w') as f: - f.write('') - expected_fname = os.path.join(self.tempdir, 'testfile0.txt') - self.assertEqual(expected_fname, data._MakeUniqueFName(testfile)) - - def test_SaveSummary(self): - """SaveSummary properly dumps the summary into a file.""" - self._populate_mock_stats() - fname = 'unittest_summary.txt' - expected_fname = os.path.join(self.tempdir, fname) - fname = self.data.SaveSummary(self.tempdir, fname) - # Assert the reported fname is the same as the expected fname - self.assertEqual(expected_fname, fname) - # Assert only the reported fname is output (in the tempdir) - self.assertEqual(set([os.path.basename(fname)]), - set(os.listdir(self.tempdir))) - with open(fname, 'r') as f: - self.assertEqual( - '@@ NAME COUNT MEAN STDDEV MAX MIN\n', - f.readline()) - self.assertEqual( - '@@ A_mW 2 100000.00 0.50 100000.50 99999.50\n', - f.readline()) - self.assertEqual( - '@@ B_mV 3 2.50 0.82 3.50 1.50\n', - f.readline()) - - def test_SaveSummarySMID(self): - """SaveSummary uses the smid when creating output filename.""" - identifier = 'ec' - self.data = stats_manager.StatsManager(smid=identifier) - self._populate_mock_stats() - fname = os.path.basename(self.data.SaveSummary(self.tempdir)) - self.assertTrue(fname.startswith(identifier)) - - def test_SaveSummaryJSON(self): - """SaveSummaryJSON saves the added data properly in JSON format.""" - self._populate_mock_stats() - fname = 'unittest_summary.json' - expected_fname = os.path.join(self.tempdir, fname) - fname = self.data.SaveSummaryJSON(self.tempdir, fname) - # Assert the reported fname is the same as the expected fname - self.assertEqual(expected_fname, fname) - # Assert only the reported fname is output (in the tempdir) - self.assertEqual(set([os.path.basename(fname)]), - set(os.listdir(self.tempdir))) - with open(fname, 'r') as f: - summary = json.load(f) - self.assertAlmostEqual(100000.0, summary['A']['mean']) - self.assertEqual('milliwatt', summary['A']['unit']) - self.assertAlmostEqual(2.5, summary['B']['mean']) - self.assertEqual('millivolt', summary['B']['unit']) - - def test_SaveSummaryJSONSMID(self): - """SaveSummaryJSON uses the smid when creating output filename.""" - identifier = 'ec' - self.data = stats_manager.StatsManager(smid=identifier) - self._populate_mock_stats() - fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir)) - self.assertTrue(fname.startswith(identifier)) - - def test_SaveSummaryJSONNoUnit(self): - """SaveSummaryJSON marks unknown units properly as N/A.""" - self._populate_mock_stats_no_unit() - self.data.CalculateStats() - fname = 'unittest_summary.json' - fname = self.data.SaveSummaryJSON(self.tempdir, fname) - with open(fname, 'r') as f: - summary = json.load(f) - self.assertEqual('blue', summary['A']['unit']) - # if no unit is specified, JSON should save 'N/A' as the unit. - self.assertEqual('N/A', summary['B']['unit']) - -if __name__ == '__main__': - unittest.main() + """Test to verify StatsManager methods work as expected. + + StatsManager should collect raw data, calculate their statistics, and save + them in expected format. + """ + + def _populate_mock_stats(self): + """Create a populated & processed StatsManager to test data retrieval.""" + self.data.AddSample("A", 99999.5) + self.data.AddSample("A", 100000.5) + self.data.SetUnit("A", "uW") + self.data.SetUnit("A", "mW") + self.data.AddSample("B", 1.5) + self.data.AddSample("B", 2.5) + self.data.AddSample("B", 3.5) + self.data.SetUnit("B", "mV") + self.data.CalculateStats() + + def _populate_mock_stats_no_unit(self): + self.data.AddSample("B", 1000) + self.data.AddSample("A", 200) + self.data.SetUnit("A", "blue") + + def setUp(self): + """Set up StatsManager and create a temporary directory for test.""" + self.tempdir = tempfile.mkdtemp() + self.data = stats_manager.StatsManager() + + def tearDown(self): + """Delete the temporary directory and its content.""" + shutil.rmtree(self.tempdir) + + def test_AddSample(self): + """Adding a sample successfully adds a sample.""" + self.data.AddSample("Test", 1000) + self.data.SetUnit("Test", "test") + self.data.CalculateStats() + summary = self.data.GetSummary() + self.assertEqual(1, summary["Test"]["count"]) + + def test_AddSampleNoFloatAcceptNaN(self): + """Adding a non-number adds 'NaN' and doesn't raise an exception.""" + self.data.AddSample("Test", 10) + self.data.AddSample("Test", 20) + # adding a fake NaN: one that gets converted into NaN internally + self.data.AddSample("Test", "fiesta") + # adding a real NaN + self.data.AddSample("Test", float("NaN")) + self.data.SetUnit("Test", "test") + self.data.CalculateStats() + summary = self.data.GetSummary() + # assert that 'NaN' as added. + self.assertEqual(4, summary["Test"]["count"]) + # assert that mean, min, and max calculatings ignore the 'NaN' + self.assertEqual(10, summary["Test"]["min"]) + self.assertEqual(20, summary["Test"]["max"]) + self.assertEqual(15, summary["Test"]["mean"]) + + def test_AddSampleNoFloatNotAcceptNaN(self): + """Adding a non-number raises a StatsManagerError if accept_nan is False.""" + self.data = stats_manager.StatsManager(accept_nan=False) + with self.assertRaisesRegexp( + stats_manager.StatsManagerError, + "accept_nan is false. Cannot add NaN sample.", + ): + # adding a fake NaN: one that gets converted into NaN internally + self.data.AddSample("Test", "fiesta") + with self.assertRaisesRegexp( + stats_manager.StatsManagerError, + "accept_nan is false. Cannot add NaN sample.", + ): + # adding a real NaN + self.data.AddSample("Test", float("NaN")) + + def test_AddSampleNoUnit(self): + """Not adding a unit does not cause an exception on CalculateStats().""" + self.data.AddSample("Test", 17) + self.data.CalculateStats() + summary = self.data.GetSummary() + self.assertEqual(1, summary["Test"]["count"]) + + def test_UnitSuffix(self): + """Unit gets appended as a suffix in the displayed summary.""" + self.data.AddSample("test", 250) + self.data.SetUnit("test", "mw") + self.data.CalculateStats() + summary_str = self.data.SummaryToString() + self.assertIn("test_mw", summary_str) + + def test_DoubleUnitSuffix(self): + """If domain already ends in unit, verify that unit doesn't get appended.""" + self.data.AddSample("test_mw", 250) + self.data.SetUnit("test_mw", "mw") + self.data.CalculateStats() + summary_str = self.data.SummaryToString() + self.assertIn("test_mw", summary_str) + self.assertNotIn("test_mw_mw", summary_str) + + def test_GetRawData(self): + """GetRawData returns exact same data as fed in.""" + self._populate_mock_stats() + raw_data = self.data.GetRawData() + self.assertListEqual([99999.5, 100000.5], raw_data["A"]) + self.assertListEqual([1.5, 2.5, 3.5], raw_data["B"]) + + def test_GetSummary(self): + """GetSummary returns expected stats about the data fed in.""" + self._populate_mock_stats() + summary = self.data.GetSummary() + self.assertEqual(2, summary["A"]["count"]) + self.assertAlmostEqual(100000.5, summary["A"]["max"]) + self.assertAlmostEqual(99999.5, summary["A"]["min"]) + self.assertAlmostEqual(0.5, summary["A"]["stddev"]) + self.assertAlmostEqual(100000.0, summary["A"]["mean"]) + self.assertEqual(3, summary["B"]["count"]) + self.assertAlmostEqual(3.5, summary["B"]["max"]) + self.assertAlmostEqual(1.5, summary["B"]["min"]) + self.assertAlmostEqual(0.81649658092773, summary["B"]["stddev"]) + self.assertAlmostEqual(2.5, summary["B"]["mean"]) + + def test_SaveRawData(self): + """SaveRawData stores same data as fed in.""" + self._populate_mock_stats() + dirname = "unittest_raw_data" + expected_files = set(["A_mW.txt", "B_mV.txt"]) + fnames = self.data.SaveRawData(self.tempdir, dirname) + files_returned = set([os.path.basename(f) for f in fnames]) + # Assert that only the expected files got returned. + self.assertEqual(expected_files, files_returned) + # Assert that only the returned files are in the outdir. + self.assertEqual( + set(os.listdir(os.path.join(self.tempdir, dirname))), files_returned + ) + for fname in fnames: + with open(fname, "r") as f: + if "A_mW" in fname: + self.assertEqual("99999.50", f.readline().strip()) + self.assertEqual("100000.50", f.readline().strip()) + if "B_mV" in fname: + self.assertEqual("1.50", f.readline().strip()) + self.assertEqual("2.50", f.readline().strip()) + self.assertEqual("3.50", f.readline().strip()) + + def test_SaveRawDataNoUnit(self): + """SaveRawData appends no unit suffix if the unit is not specified.""" + self._populate_mock_stats_no_unit() + self.data.CalculateStats() + outdir = "unittest_raw_data" + files = self.data.SaveRawData(self.tempdir, outdir) + files = [os.path.basename(f) for f in files] + # Verify nothing gets appended to domain for filename if no unit exists. + self.assertIn("B.txt", files) + + def test_SaveRawDataSMID(self): + """SaveRawData uses the smid when creating output filename.""" + identifier = "ec" + self.data = stats_manager.StatsManager(smid=identifier) + self._populate_mock_stats() + files = self.data.SaveRawData(self.tempdir) + for fname in files: + self.assertTrue(os.path.basename(fname).startswith(identifier)) + + def test_SummaryToStringNaNHelp(self): + """NaN containing row gets tagged with *, help banner gets added.""" + help_banner_exp = "%s %s" % ( + stats_manager.STATS_PREFIX, + stats_manager.NAN_DESCRIPTION, + ) + nan_domain = "A-domain" + nan_domain_exp = "%s%s" % (nan_domain, stats_manager.NAN_TAG) + # NaN helper banner is added when a NaN domain is found & domain gets tagged + data = stats_manager.StatsManager() + data.AddSample(nan_domain, float("NaN")) + data.AddSample(nan_domain, 17) + data.AddSample("B-domain", 17) + data.CalculateStats() + summarystr = data.SummaryToString() + self.assertIn(help_banner_exp, summarystr) + self.assertIn(nan_domain_exp, summarystr) + # NaN helper banner is not added when no NaN domain output, no tagging + data = stats_manager.StatsManager() + # nan_domain in this scenario does not contain any NaN + data.AddSample(nan_domain, 19) + data.AddSample("B-domain", 17) + data.CalculateStats() + summarystr = data.SummaryToString() + self.assertNotIn(help_banner_exp, summarystr) + self.assertNotIn(nan_domain_exp, summarystr) + + def test_SummaryToStringTitle(self): + """Title shows up in SummaryToString if title specified.""" + title = "titulo" + data = stats_manager.StatsManager(title=title) + self._populate_mock_stats() + summary_str = data.SummaryToString() + self.assertIn(title, summary_str) + + def test_SummaryToStringHideDomains(self): + """Keys indicated in hide_domains are not printed in the summary.""" + data = stats_manager.StatsManager(hide_domains=["A-domain"]) + data.AddSample("A-domain", 17) + data.AddSample("B-domain", 17) + data.CalculateStats() + summary_str = data.SummaryToString() + self.assertIn("B-domain", summary_str) + self.assertNotIn("A-domain", summary_str) + + def test_SummaryToStringOrder(self): + """Order passed into StatsManager is honoured when formatting summary.""" + # StatsManager that should print D & B first, and the subsequent elements + # are sorted. + d_b_a_c_regexp = re.compile("D-domain.*B-domain.*A-domain.*C-domain", re.DOTALL) + data = stats_manager.StatsManager(order=["D-domain", "B-domain"]) + data.AddSample("A-domain", 17) + data.AddSample("B-domain", 17) + data.AddSample("C-domain", 17) + data.AddSample("D-domain", 17) + data.CalculateStats() + summary_str = data.SummaryToString() + self.assertRegexpMatches(summary_str, d_b_a_c_regexp) + + def test_MakeUniqueFName(self): + data = stats_manager.StatsManager() + testfile = os.path.join(self.tempdir, "testfile.txt") + with open(testfile, "w") as f: + f.write("") + expected_fname = os.path.join(self.tempdir, "testfile0.txt") + self.assertEqual(expected_fname, data._MakeUniqueFName(testfile)) + + def test_SaveSummary(self): + """SaveSummary properly dumps the summary into a file.""" + self._populate_mock_stats() + fname = "unittest_summary.txt" + expected_fname = os.path.join(self.tempdir, fname) + fname = self.data.SaveSummary(self.tempdir, fname) + # Assert the reported fname is the same as the expected fname + self.assertEqual(expected_fname, fname) + # Assert only the reported fname is output (in the tempdir) + self.assertEqual(set([os.path.basename(fname)]), set(os.listdir(self.tempdir))) + with open(fname, "r") as f: + self.assertEqual( + "@@ NAME COUNT MEAN STDDEV MAX MIN\n", + f.readline(), + ) + self.assertEqual( + "@@ A_mW 2 100000.00 0.50 100000.50 99999.50\n", + f.readline(), + ) + self.assertEqual( + "@@ B_mV 3 2.50 0.82 3.50 1.50\n", + f.readline(), + ) + + def test_SaveSummarySMID(self): + """SaveSummary uses the smid when creating output filename.""" + identifier = "ec" + self.data = stats_manager.StatsManager(smid=identifier) + self._populate_mock_stats() + fname = os.path.basename(self.data.SaveSummary(self.tempdir)) + self.assertTrue(fname.startswith(identifier)) + + def test_SaveSummaryJSON(self): + """SaveSummaryJSON saves the added data properly in JSON format.""" + self._populate_mock_stats() + fname = "unittest_summary.json" + expected_fname = os.path.join(self.tempdir, fname) + fname = self.data.SaveSummaryJSON(self.tempdir, fname) + # Assert the reported fname is the same as the expected fname + self.assertEqual(expected_fname, fname) + # Assert only the reported fname is output (in the tempdir) + self.assertEqual(set([os.path.basename(fname)]), set(os.listdir(self.tempdir))) + with open(fname, "r") as f: + summary = json.load(f) + self.assertAlmostEqual(100000.0, summary["A"]["mean"]) + self.assertEqual("milliwatt", summary["A"]["unit"]) + self.assertAlmostEqual(2.5, summary["B"]["mean"]) + self.assertEqual("millivolt", summary["B"]["unit"]) + + def test_SaveSummaryJSONSMID(self): + """SaveSummaryJSON uses the smid when creating output filename.""" + identifier = "ec" + self.data = stats_manager.StatsManager(smid=identifier) + self._populate_mock_stats() + fname = os.path.basename(self.data.SaveSummaryJSON(self.tempdir)) + self.assertTrue(fname.startswith(identifier)) + + def test_SaveSummaryJSONNoUnit(self): + """SaveSummaryJSON marks unknown units properly as N/A.""" + self._populate_mock_stats_no_unit() + self.data.CalculateStats() + fname = "unittest_summary.json" + fname = self.data.SaveSummaryJSON(self.tempdir, fname) + with open(fname, "r") as f: + summary = json.load(f) + self.assertEqual("blue", summary["A"]["unit"]) + # if no unit is specified, JSON should save 'N/A' as the unit. + self.assertEqual("N/A", summary["B"]["unit"]) + + +if __name__ == "__main__": + unittest.main() diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py index 7211dceff6..c08cb72092 100755 --- a/extra/usb_serial/console.py +++ b/extra/usb_serial/console.py @@ -12,6 +12,7 @@ # Note: This is a py2/3 compatible file. from __future__ import print_function + import argparse import array import os @@ -20,23 +21,24 @@ import termios import threading import time import tty + try: - import usb + import usb except ModuleNotFoundError: - print('import usb failed') - print('try running these commands:') - print(' sudo apt-get install python-pip') - print(' sudo pip install --pre pyusb') - print() - sys.exit(-1) + print("import usb failed") + print("try running these commands:") + print(" sudo apt-get install python-pip") + print(" sudo pip install --pre pyusb") + print() + sys.exit(-1) import six def GetBuffer(stream): - if six.PY3: - return stream.buffer - return stream + if six.PY3: + return stream.buffer + return stream """Class Susb covers USB device discovery and initialization. @@ -45,99 +47,104 @@ def GetBuffer(stream): and interface number. """ + class SusbError(Exception): - """Class for exceptions of Susb.""" - def __init__(self, msg, value=0): - """SusbError constructor. + """Class for exceptions of Susb.""" - Args: - msg: string, message describing error in detail - value: integer, value of error when non-zero status returned. Default=0 - """ - super(SusbError, self).__init__(msg, value) - self.msg = msg - self.value = value - -class Susb(): - """Provide USB functionality. - - Instance Variables: - _read_ep: pyUSB read endpoint for this interface - _write_ep: pyUSB write endpoint for this interface - """ - READ_ENDPOINT = 0x81 - WRITE_ENDPOINT = 0x1 - TIMEOUT_MS = 100 - - def __init__(self, vendor=0x18d1, - product=0x500f, interface=1, serialname=None): - """Susb constructor. - - Discovers and connects to USB endpoints. - - Args: - vendor: usb vendor id of device - product: usb product id of device - interface: interface number ( 1 - 8 ) of device to use - serialname: string of device serialnumber. - - Raises: - SusbError: An error accessing Susb object + def __init__(self, msg, value=0): + """SusbError constructor. + + Args: + msg: string, message describing error in detail + value: integer, value of error when non-zero status returned. Default=0 + """ + super(SusbError, self).__init__(msg, value) + self.msg = msg + self.value = value + + +class Susb: + """Provide USB functionality. + + Instance Variables: + _read_ep: pyUSB read endpoint for this interface + _write_ep: pyUSB write endpoint for this interface """ - # Find the device. - dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) - dev_list = list(dev_g) - if dev_list is None: - raise SusbError('USB device not found') - - # Check if we have multiple devices. - dev = None - if serialname: - for d in dev_list: - dev_serial = "PyUSB doesn't have a stable interface" - try: - dev_serial = usb.util.get_string(d, 256, d.iSerialNumber) - except: - dev_serial = usb.util.get_string(d, d.iSerialNumber) - if dev_serial == serialname: - dev = d - break - if dev is None: - raise SusbError('USB device(%s) not found' % (serialname,)) - else: - try: - dev = dev_list[0] - except: - try: - dev = dev_list.next() - except: - raise SusbError('USB device %04x:%04x not found' % (vendor, product)) - # If we can't set configuration, it's already been set. - try: - dev.set_configuration() - except usb.core.USBError: - pass + READ_ENDPOINT = 0x81 + WRITE_ENDPOINT = 0x1 + TIMEOUT_MS = 100 + + def __init__(self, vendor=0x18D1, product=0x500F, interface=1, serialname=None): + """Susb constructor. + + Discovers and connects to USB endpoints. + + Args: + vendor: usb vendor id of device + product: usb product id of device + interface: interface number ( 1 - 8 ) of device to use + serialname: string of device serialnumber. + + Raises: + SusbError: An error accessing Susb object + """ + # Find the device. + dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) + dev_list = list(dev_g) + if dev_list is None: + raise SusbError("USB device not found") + + # Check if we have multiple devices. + dev = None + if serialname: + for d in dev_list: + dev_serial = "PyUSB doesn't have a stable interface" + try: + dev_serial = usb.util.get_string(d, 256, d.iSerialNumber) + except: + dev_serial = usb.util.get_string(d, d.iSerialNumber) + if dev_serial == serialname: + dev = d + break + if dev is None: + raise SusbError("USB device(%s) not found" % (serialname,)) + else: + try: + dev = dev_list[0] + except: + try: + dev = dev_list.next() + except: + raise SusbError( + "USB device %04x:%04x not found" % (vendor, product) + ) + + # If we can't set configuration, it's already been set. + try: + dev.set_configuration() + except usb.core.USBError: + pass - # Get an endpoint instance. - cfg = dev.get_active_configuration() - intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface) - self._intf = intf + # Get an endpoint instance. + cfg = dev.get_active_configuration() + intf = usb.util.find_descriptor(cfg, bInterfaceNumber=interface) + self._intf = intf - if not intf: - raise SusbError('Interface not found') + if not intf: + raise SusbError("Interface not found") - # Detach raiden.ko if it is loaded. - if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True: + # Detach raiden.ko if it is loaded. + if dev.is_kernel_driver_active(intf.bInterfaceNumber) is True: dev.detach_kernel_driver(intf.bInterfaceNumber) - read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT - read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number) - self._read_ep = read_ep + read_ep_number = intf.bInterfaceNumber + self.READ_ENDPOINT + read_ep = usb.util.find_descriptor(intf, bEndpointAddress=read_ep_number) + self._read_ep = read_ep - write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT - write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number) - self._write_ep = write_ep + write_ep_number = intf.bInterfaceNumber + self.WRITE_ENDPOINT + write_ep = usb.util.find_descriptor(intf, bEndpointAddress=write_ep_number) + self._write_ep = write_ep """Suart class implements a stream interface, to access Google's USB class. @@ -146,89 +153,91 @@ class Susb(): and forwards them across. This particular class is hardcoded to stdin/out. """ -class SuartError(Exception): - """Class for exceptions of Suart.""" - def __init__(self, msg, value=0): - """SuartError constructor. - - Args: - msg: string, message describing error in detail - value: integer, value of error when non-zero status returned. Default=0 - """ - super(SuartError, self).__init__(msg, value) - self.msg = msg - self.value = value - - -class Suart(): - """Provide interface to serial usb endpoint.""" - def __init__(self, vendor=0x18d1, product=0x501c, interface=0, - serialname=None): - """Suart contstructor. +class SuartError(Exception): + """Class for exceptions of Suart.""" - Initializes USB stream interface. + def __init__(self, msg, value=0): + """SuartError constructor. - Args: - vendor: usb vendor id of device - product: usb product id of device - interface: interface number of device to use - serialname: Defaults to None. + Args: + msg: string, message describing error in detail + value: integer, value of error when non-zero status returned. Default=0 + """ + super(SuartError, self).__init__(msg, value) + self.msg = msg + self.value = value - Raises: - SuartError: If init fails - """ - self._done = threading.Event() - self._susb = Susb(vendor=vendor, product=product, - interface=interface, serialname=serialname) - def wait_until_done(self, timeout=None): - return self._done.wait(timeout=timeout) +class Suart: + """Provide interface to serial usb endpoint.""" - def run_rx_thread(self): - try: - while True: - try: - r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS) - if r: - GetBuffer(sys.stdout).write(r.tobytes()) - GetBuffer(sys.stdout).flush() - - except Exception as e: - # If we miss some characters on pty disconnect, that's fine. - # ep.read() also throws USBError on timeout, which we discard. - if not isinstance(e, (OSError, usb.core.USBError)): - print('rx %s' % e) - finally: - self._done.set() + def __init__(self, vendor=0x18D1, product=0x501C, interface=0, serialname=None): + """Suart contstructor. - def run_tx_thread(self): - try: - while True: - try: - r = GetBuffer(sys.stdin).read(1) - if not r or r == b'\x03': - break - if r: - self._susb._write_ep.write(array.array('B', r), - self._susb.TIMEOUT_MS) - except Exception as e: - print('tx %s' % e) - finally: - self._done.set() + Initializes USB stream interface. - def run(self): - """Creates pthreads to poll USB & PTY for data.""" - self._exit = False + Args: + vendor: usb vendor id of device + product: usb product id of device + interface: interface number of device to use + serialname: Defaults to None. - self._rx_thread = threading.Thread(target=self.run_rx_thread) - self._rx_thread.daemon = True - self._rx_thread.start() + Raises: + SuartError: If init fails + """ + self._done = threading.Event() + self._susb = Susb( + vendor=vendor, product=product, interface=interface, serialname=serialname + ) - self._tx_thread = threading.Thread(target=self.run_tx_thread) - self._tx_thread.daemon = True - self._tx_thread.start() + def wait_until_done(self, timeout=None): + return self._done.wait(timeout=timeout) + def run_rx_thread(self): + try: + while True: + try: + r = self._susb._read_ep.read(64, self._susb.TIMEOUT_MS) + if r: + GetBuffer(sys.stdout).write(r.tobytes()) + GetBuffer(sys.stdout).flush() + + except Exception as e: + # If we miss some characters on pty disconnect, that's fine. + # ep.read() also throws USBError on timeout, which we discard. + if not isinstance(e, (OSError, usb.core.USBError)): + print("rx %s" % e) + finally: + self._done.set() + + def run_tx_thread(self): + try: + while True: + try: + r = GetBuffer(sys.stdin).read(1) + if not r or r == b"\x03": + break + if r: + self._susb._write_ep.write( + array.array("B", r), self._susb.TIMEOUT_MS + ) + except Exception as e: + print("tx %s" % e) + finally: + self._done.set() + + def run(self): + """Creates pthreads to poll USB & PTY for data.""" + self._exit = False + + self._rx_thread = threading.Thread(target=self.run_rx_thread) + self._rx_thread.daemon = True + self._rx_thread.start() + + self._tx_thread = threading.Thread(target=self.run_tx_thread) + self._tx_thread.daemon = True + self._tx_thread.start() """Command line functionality @@ -237,59 +246,67 @@ class Suart(): Ctrl-C exits. """ -parser = argparse.ArgumentParser(description='Open a console to a USB device') -parser.add_argument('-d', '--device', type=str, - help='vid:pid of target device', default='18d1:501c') -parser.add_argument('-i', '--interface', type=int, - help='interface number of console', default=0) -parser.add_argument('-s', '--serialno', type=str, - help='serial number of device', default='') -parser.add_argument('-S', '--notty-exit-sleep', type=float, default=0.2, - help='When stdin is *not* a TTY, wait this many seconds ' - 'after EOF from stdin before exiting, to give time for ' - 'receiving a reply from the USB device.') +parser = argparse.ArgumentParser(description="Open a console to a USB device") +parser.add_argument( + "-d", "--device", type=str, help="vid:pid of target device", default="18d1:501c" +) +parser.add_argument( + "-i", "--interface", type=int, help="interface number of console", default=0 +) +parser.add_argument( + "-s", "--serialno", type=str, help="serial number of device", default="" +) +parser.add_argument( + "-S", + "--notty-exit-sleep", + type=float, + default=0.2, + help="When stdin is *not* a TTY, wait this many seconds " + "after EOF from stdin before exiting, to give time for " + "receiving a reply from the USB device.", +) + def runconsole(): - """Run the usb console code + """Run the usb console code - Starts the pty thread, and idles until a ^C is caught. - """ - args = parser.parse_args() + Starts the pty thread, and idles until a ^C is caught. + """ + args = parser.parse_args() - vidstr, pidstr = args.device.split(':') - vid = int(vidstr, 16) - pid = int(pidstr, 16) + vidstr, pidstr = args.device.split(":") + vid = int(vidstr, 16) + pid = int(pidstr, 16) - serialno = args.serialno - interface = args.interface + serialno = args.serialno + interface = args.interface - sobj = Suart(vendor=vid, product=pid, interface=interface, - serialname=serialno) - if sys.stdin.isatty(): - tty.setraw(sys.stdin.fileno()) - sobj.run() - sobj.wait_until_done() - if not sys.stdin.isatty() and args.notty_exit_sleep > 0: - time.sleep(args.notty_exit_sleep) + sobj = Suart(vendor=vid, product=pid, interface=interface, serialname=serialno) + if sys.stdin.isatty(): + tty.setraw(sys.stdin.fileno()) + sobj.run() + sobj.wait_until_done() + if not sys.stdin.isatty() and args.notty_exit_sleep > 0: + time.sleep(args.notty_exit_sleep) def main(): - stdin_isatty = sys.stdin.isatty() - if stdin_isatty: - fd = sys.stdin.fileno() - os.system('stty -echo') - old_settings = termios.tcgetattr(fd) - - try: - runconsole() - finally: + stdin_isatty = sys.stdin.isatty() if stdin_isatty: - termios.tcsetattr(fd, termios.TCSADRAIN, old_settings) - os.system('stty echo') - # Avoid having the user's shell prompt start mid-line after the final output - # from this program. - print() + fd = sys.stdin.fileno() + os.system("stty -echo") + old_settings = termios.tcgetattr(fd) + + try: + runconsole() + finally: + if stdin_isatty: + termios.tcsetattr(fd, termios.TCSADRAIN, old_settings) + os.system("stty echo") + # Avoid having the user's shell prompt start mid-line after the final output + # from this program. + print() -if __name__ == '__main__': - main() +if __name__ == "__main__": + main() diff --git a/extra/usb_updater/fw_update.py b/extra/usb_updater/fw_update.py index 0d7a570fc3..f05797bfb6 100755 --- a/extra/usb_updater/fw_update.py +++ b/extra/usb_updater/fw_update.py @@ -20,407 +20,425 @@ import struct import sys import time from pprint import pprint -import usb +import usb debug = False -def debuglog(msg): - if debug: - print(msg) - -def log(msg): - print(msg) - sys.stdout.flush() - - -"""Sends firmware update to CROS EC usb endpoint.""" - -class Supdate(object): - """Class to access firmware update endpoints. - - Usage: - d = Supdate() - Instance Variables: - _dev: pyUSB device object - _read_ep: pyUSB read endpoint for this interface - _write_ep: pyUSB write endpoint for this interface - """ - USB_SUBCLASS_GOOGLE_UPDATE = 0x53 - USB_CLASS_VENDOR = 0xFF - def __init__(self): - pass - - - def connect_usb(self, serialname=None): - """Initial discovery and connection to USB endpoint. - - This searches for a USB device matching the VID:PID specified - in the config file, optionally matching a specified serialname. - - Args: - serialname: Find the device with this serial, in case multiple - devices are attached. - - Returns: - True on success. - Raises: - Exception on error. - """ - # Find the stm32. - vendor = self._brdcfg['vid'] - product = self._brdcfg['pid'] - - dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) - dev_list = list(dev_g) - if dev_list is None: - raise Exception("Update", "USB device not found") - - # Check if we have multiple stm32s and we've specified the serial. - dev = None - if serialname: - for d in dev_list: - if usb.util.get_string(d, d.iSerialNumber) == serialname: - dev = d - break - if dev is None: - raise SusbError("USB device(%s) not found" % serialname) - else: - try: - dev = dev_list[0] - except: - dev = dev_list.next() - - debuglog("Found stm32: %04x:%04x" % (vendor, product)) - self._dev = dev - - # Get an endpoint instance. - try: - dev.set_configuration() - except: - pass - cfg = dev.get_active_configuration() - - intf = usb.util.find_descriptor(cfg, custom_match=lambda i: \ - i.bInterfaceClass==self.USB_CLASS_VENDOR and \ - i.bInterfaceSubClass==self.USB_SUBCLASS_GOOGLE_UPDATE) - - self._intf = intf - debuglog("Interface: %s" % intf) - debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber) - - read_ep = usb.util.find_descriptor( - intf, - # match the first IN endpoint - custom_match = \ - lambda e: \ - usb.util.endpoint_direction(e.bEndpointAddress) == \ - usb.util.ENDPOINT_IN - ) - - self._read_ep = read_ep - debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress) - - write_ep = usb.util.find_descriptor( - intf, - # match the first OUT endpoint - custom_match = \ - lambda e: \ - usb.util.endpoint_direction(e.bEndpointAddress) == \ - usb.util.ENDPOINT_OUT - ) - - self._write_ep = write_ep - debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress) - - return True - - - def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000): - """Write command to logger logic.. - - This function writes byte command values list to stm, then reads - byte status. - - Args: - write_list: list of command byte values [0~255]. - read_count: number of status byte values to read. - wtimeout: mS to wait for write success - rtimeout: mS to wait for read success - - Returns: - status byte, if one byte is read, - byte list, if multiple bytes are read, - None, if no bytes are read. - - Interface: - write: [command, data ... ] - read: [status ] - """ - debuglog("wr_command(write_list=[%s] (%d), read_count=%s)" % ( - list(bytearray(write_list)), len(write_list), read_count)) - - # Clean up args from python style to correct types. - write_length = 0 - if write_list: - write_length = len(write_list) - if not read_count: - read_count = 0 - - # Send command to stm32. - if write_list: - cmd = write_list - ret = self._write_ep.write(cmd, wtimeout) - debuglog("RET: %s " % ret) - - # Read back response if necessary. - if read_count: - bytesread = self._read_ep.read(512, rtimeout) - debuglog("BYTES: [%s]" % bytesread) - - if len(bytesread) != read_count: - debuglog("Unexpected bytes read: %d, expected: %d" % (len(bytesread), read_count)) - pass - - debuglog("STATUS: 0x%02x" % int(bytesread[0])) - if read_count == 1: - return bytesread[0] - else: - return bytesread - - return None +def debuglog(msg): + if debug: + print(msg) - def stop(self): - """Finalize system flash and exit.""" - cmd = struct.pack(">I", 0xB007AB1E) - read = self.wr_command(cmd, read_count=4) - if len(read) == 4: - log("Finished flashing") - return +def log(msg): + print(msg) + sys.stdout.flush() - raise Exception("Update", "Stop failed [%s]" % read) +"""Sends firmware update to CROS EC usb endpoint.""" - def write_file(self): - """Write the update region packet by packet to USB - This sends write packets of size 128B out, in 32B chunks. - Overall, this will write all data in the inactive code region. +class Supdate(object): + """Class to access firmware update endpoints. - Raises: - Exception if write failed or address out of bounds. - """ - region = self._region - flash_base = self._brdcfg["flash"] - offset = self._base - flash_base - if offset != self._brdcfg['regions'][region][0]: - raise Exception("Update", "Region %s offset 0x%x != available offset 0x%x" % ( - region, self._brdcfg['regions'][region][0], offset)) - - length = self._brdcfg['regions'][region][1] - log("Sending") - - # Go to the correct region in the ec.bin file. - self._binfile.seek(offset) - - # Send 32 bytes at a time. Must be less than the endpoint's max packet size. - maxpacket = 32 - - # While data is left, create update packets. - while length > 0: - # Update packets are 128B. We can use any number - # but the micro must malloc this memory. - pagesize = min(length, 128) - - # Packet is: - # packet size: page bytes transferred plus 3 x 32b values header. - # cmd: n/a - # base: flash address to write this packet. - # data: 128B of data to write into flash_base - cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base) - read = self.wr_command(cmd, read_count=0) - - # Push 'todo' bytes out the pipe. - todo = pagesize - while todo > 0: - packetsize = min(maxpacket, todo) - data = self._binfile.read(packetsize) - if len(data) != packetsize: - raise Exception("Update", "No more data from file") - for i in range(0, 10): - try: - self.wr_command(data, read_count=0) - break - except: - log("Timeout fail") - todo -= packetsize - # Done with this packet, move to the next one. - length -= pagesize - offset += pagesize - - # Validate that the micro thinks it successfully wrote the data. - read = self.wr_command(''.encode(), read_count=4) - result = struct.unpack("II", read) - log("Update protocol v. %d" % version) - log("Available flash region base: %x" % base) - else: - raise Exception("Update", "Start command returned %d bytes" % len(read)) - - if base < 256: - raise Exception("Update", "Start returned error code 0x%x" % base) - - self._base = base - flash_base = self._brdcfg["flash"] - self._offset = self._base - flash_base - - # Find our active region. - for region in self._brdcfg['regions']: - if (self._offset >= self._brdcfg['regions'][region][0]) and \ - (self._offset < (self._brdcfg['regions'][region][0] + \ - self._brdcfg['regions'][region][1])): - log("Active region: %s" % region) - self._region = region - - - def load_board(self, brdfile): - """Load firmware layout file. - - example as follows: - { - "board": "servo micro", - "vid": 6353, - "pid": 20506, - "flash": 134217728, - "regions": { - "RW": [65536, 65536], - "PSTATE": [61440, 4096], - "RO": [0, 61440] - } - } - - Args: - brdfile: path to board description file. + Instance Variables: + _dev: pyUSB device object + _read_ep: pyUSB read endpoint for this interface + _write_ep: pyUSB write endpoint for this interface """ - with open(brdfile) as data_file: - data = json.load(data_file) - - # TODO(nsanders): validate this data before moving on. - self._brdcfg = data; - if debug: - pprint(data) - - log("Board is %s" % self._brdcfg['board']) - # Cast hex strings to int. - self._brdcfg['flash'] = int(self._brdcfg['flash'], 0) - self._brdcfg['vid'] = int(self._brdcfg['vid'], 0) - self._brdcfg['pid'] = int(self._brdcfg['pid'], 0) - log("Flash Base is %x" % self._brdcfg['flash']) - self._flashsize = 0 - for region in self._brdcfg['regions']: - base = int(self._brdcfg['regions'][region][0], 0) - length = int(self._brdcfg['regions'][region][1], 0) - log("region %s\tbase:0x%08x size:0x%08x" % ( - region, base, length)) - self._flashsize += length + USB_SUBCLASS_GOOGLE_UPDATE = 0x53 + USB_CLASS_VENDOR = 0xFF - # Convert these to int because json doesn't support hex. - self._brdcfg['regions'][region][0] = base - self._brdcfg['regions'][region][1] = length - - log("Flash Size: 0x%x" % self._flashsize) - - def load_file(self, binfile): - """Open and verify size of the target ec.bin file. - - Args: - binfile: path to ec.bin - - Raises: - Exception on file not found or filesize not matching. - """ - self._filesize = os.path.getsize(binfile) - self._binfile = open(binfile, 'rb') - - if self._filesize != self._flashsize: - raise Exception("Update", "Flash size 0x%x != file size 0x%x" % (self._flashsize, self._filesize)) + def __init__(self): + pass + def connect_usb(self, serialname=None): + """Initial discovery and connection to USB endpoint. + + This searches for a USB device matching the VID:PID specified + in the config file, optionally matching a specified serialname. + + Args: + serialname: Find the device with this serial, in case multiple + devices are attached. + + Returns: + True on success. + Raises: + Exception on error. + """ + # Find the stm32. + vendor = self._brdcfg["vid"] + product = self._brdcfg["pid"] + + dev_g = usb.core.find(idVendor=vendor, idProduct=product, find_all=True) + dev_list = list(dev_g) + if dev_list is None: + raise Exception("Update", "USB device not found") + + # Check if we have multiple stm32s and we've specified the serial. + dev = None + if serialname: + for d in dev_list: + if usb.util.get_string(d, d.iSerialNumber) == serialname: + dev = d + break + if dev is None: + raise SusbError("USB device(%s) not found" % serialname) + else: + try: + dev = dev_list[0] + except: + dev = dev_list.next() + + debuglog("Found stm32: %04x:%04x" % (vendor, product)) + self._dev = dev + + # Get an endpoint instance. + try: + dev.set_configuration() + except: + pass + cfg = dev.get_active_configuration() + + intf = usb.util.find_descriptor( + cfg, + custom_match=lambda i: i.bInterfaceClass == self.USB_CLASS_VENDOR + and i.bInterfaceSubClass == self.USB_SUBCLASS_GOOGLE_UPDATE, + ) + + self._intf = intf + debuglog("Interface: %s" % intf) + debuglog("InterfaceNumber: %s" % intf.bInterfaceNumber) + + read_ep = usb.util.find_descriptor( + intf, + # match the first IN endpoint + custom_match=lambda e: usb.util.endpoint_direction(e.bEndpointAddress) + == usb.util.ENDPOINT_IN, + ) + + self._read_ep = read_ep + debuglog("Reader endpoint: 0x%x" % read_ep.bEndpointAddress) + + write_ep = usb.util.find_descriptor( + intf, + # match the first OUT endpoint + custom_match=lambda e: usb.util.endpoint_direction(e.bEndpointAddress) + == usb.util.ENDPOINT_OUT, + ) + + self._write_ep = write_ep + debuglog("Writer endpoint: 0x%x" % write_ep.bEndpointAddress) + + return True + + def wr_command(self, write_list, read_count=1, wtimeout=100, rtimeout=2000): + """Write command to logger logic.. + + This function writes byte command values list to stm, then reads + byte status. + + Args: + write_list: list of command byte values [0~255]. + read_count: number of status byte values to read. + wtimeout: mS to wait for write success + rtimeout: mS to wait for read success + + Returns: + status byte, if one byte is read, + byte list, if multiple bytes are read, + None, if no bytes are read. + + Interface: + write: [command, data ... ] + read: [status ] + """ + debuglog( + "wr_command(write_list=[%s] (%d), read_count=%s)" + % (list(bytearray(write_list)), len(write_list), read_count) + ) + + # Clean up args from python style to correct types. + write_length = 0 + if write_list: + write_length = len(write_list) + if not read_count: + read_count = 0 + + # Send command to stm32. + if write_list: + cmd = write_list + ret = self._write_ep.write(cmd, wtimeout) + debuglog("RET: %s " % ret) + + # Read back response if necessary. + if read_count: + bytesread = self._read_ep.read(512, rtimeout) + debuglog("BYTES: [%s]" % bytesread) + + if len(bytesread) != read_count: + debuglog( + "Unexpected bytes read: %d, expected: %d" + % (len(bytesread), read_count) + ) + pass + + debuglog("STATUS: 0x%02x" % int(bytesread[0])) + if read_count == 1: + return bytesread[0] + else: + return bytesread + + return None + + def stop(self): + """Finalize system flash and exit.""" + cmd = struct.pack(">I", 0xB007AB1E) + read = self.wr_command(cmd, read_count=4) + + if len(read) == 4: + log("Finished flashing") + return + + raise Exception("Update", "Stop failed [%s]" % read) + + def write_file(self): + """Write the update region packet by packet to USB + + This sends write packets of size 128B out, in 32B chunks. + Overall, this will write all data in the inactive code region. + + Raises: + Exception if write failed or address out of bounds. + """ + region = self._region + flash_base = self._brdcfg["flash"] + offset = self._base - flash_base + if offset != self._brdcfg["regions"][region][0]: + raise Exception( + "Update", + "Region %s offset 0x%x != available offset 0x%x" + % (region, self._brdcfg["regions"][region][0], offset), + ) + + length = self._brdcfg["regions"][region][1] + log("Sending") + + # Go to the correct region in the ec.bin file. + self._binfile.seek(offset) + + # Send 32 bytes at a time. Must be less than the endpoint's max packet size. + maxpacket = 32 + + # While data is left, create update packets. + while length > 0: + # Update packets are 128B. We can use any number + # but the micro must malloc this memory. + pagesize = min(length, 128) + + # Packet is: + # packet size: page bytes transferred plus 3 x 32b values header. + # cmd: n/a + # base: flash address to write this packet. + # data: 128B of data to write into flash_base + cmd = struct.pack(">III", pagesize + 12, 0, offset + flash_base) + read = self.wr_command(cmd, read_count=0) + + # Push 'todo' bytes out the pipe. + todo = pagesize + while todo > 0: + packetsize = min(maxpacket, todo) + data = self._binfile.read(packetsize) + if len(data) != packetsize: + raise Exception("Update", "No more data from file") + for i in range(0, 10): + try: + self.wr_command(data, read_count=0) + break + except: + log("Timeout fail") + todo -= packetsize + # Done with this packet, move to the next one. + length -= pagesize + offset += pagesize + + # Validate that the micro thinks it successfully wrote the data. + read = self.wr_command("".encode(), read_count=4) + result = struct.unpack("II", read) + log("Update protocol v. %d" % version) + log("Available flash region base: %x" % base) + else: + raise Exception("Update", "Start command returned %d bytes" % len(read)) + + if base < 256: + raise Exception("Update", "Start returned error code 0x%x" % base) + + self._base = base + flash_base = self._brdcfg["flash"] + self._offset = self._base - flash_base + + # Find our active region. + for region in self._brdcfg["regions"]: + if (self._offset >= self._brdcfg["regions"][region][0]) and ( + self._offset + < ( + self._brdcfg["regions"][region][0] + + self._brdcfg["regions"][region][1] + ) + ): + log("Active region: %s" % region) + self._region = region + + def load_board(self, brdfile): + """Load firmware layout file. + + example as follows: + { + "board": "servo micro", + "vid": 6353, + "pid": 20506, + "flash": 134217728, + "regions": { + "RW": [65536, 65536], + "PSTATE": [61440, 4096], + "RO": [0, 61440] + } + } + + Args: + brdfile: path to board description file. + """ + with open(brdfile) as data_file: + data = json.load(data_file) + + # TODO(nsanders): validate this data before moving on. + self._brdcfg = data + if debug: + pprint(data) + + log("Board is %s" % self._brdcfg["board"]) + # Cast hex strings to int. + self._brdcfg["flash"] = int(self._brdcfg["flash"], 0) + self._brdcfg["vid"] = int(self._brdcfg["vid"], 0) + self._brdcfg["pid"] = int(self._brdcfg["pid"], 0) + + log("Flash Base is %x" % self._brdcfg["flash"]) + self._flashsize = 0 + for region in self._brdcfg["regions"]: + base = int(self._brdcfg["regions"][region][0], 0) + length = int(self._brdcfg["regions"][region][1], 0) + log("region %s\tbase:0x%08x size:0x%08x" % (region, base, length)) + self._flashsize += length + + # Convert these to int because json doesn't support hex. + self._brdcfg["regions"][region][0] = base + self._brdcfg["regions"][region][1] = length + + log("Flash Size: 0x%x" % self._flashsize) + + def load_file(self, binfile): + """Open and verify size of the target ec.bin file. + + Args: + binfile: path to ec.bin + + Raises: + Exception on file not found or filesize not matching. + """ + self._filesize = os.path.getsize(binfile) + self._binfile = open(binfile, "rb") + + if self._filesize != self._flashsize: + raise Exception( + "Update", + "Flash size 0x%x != file size 0x%x" % (self._flashsize, self._filesize), + ) # Generate command line arguments parser = argparse.ArgumentParser(description="Update firmware over usb") -parser.add_argument('-b', '--board', type=str, help="Board configuration json file", default="board.json") -parser.add_argument('-f', '--file', type=str, help="Complete ec.bin file", default="ec.bin") -parser.add_argument('-s', '--serial', type=str, help="Serial number", default="") -parser.add_argument('-l', '--list', action="store_true", help="List regions") -parser.add_argument('-v', '--verbose', action="store_true", help="Chatty output") +parser.add_argument( + "-b", + "--board", + type=str, + help="Board configuration json file", + default="board.json", +) +parser.add_argument( + "-f", "--file", type=str, help="Complete ec.bin file", default="ec.bin" +) +parser.add_argument("-s", "--serial", type=str, help="Serial number", default="") +parser.add_argument("-l", "--list", action="store_true", help="List regions") +parser.add_argument("-v", "--verbose", action="store_true", help="Chatty output") + def main(): - global debug - args = parser.parse_args() + global debug + args = parser.parse_args() + brdfile = args.board + serial = args.serial + binfile = args.file + if args.verbose: + debug = True - brdfile = args.board - serial = args.serial - binfile = args.file - if args.verbose: - debug = True + with open(brdfile) as data_file: + names = json.load(data_file) - with open(brdfile) as data_file: - names = json.load(data_file) + p = Supdate() + p.load_board(brdfile) + p.connect_usb(serialname=serial) + p.load_file(binfile) - p = Supdate() - p.load_board(brdfile) - p.connect_usb(serialname=serial) - p.load_file(binfile) + # List solely prints the config. + if args.list: + return - # List solely prints the config. - if (args.list): - return + # Start transfer and erase. + p.start() + # Upload the bin file + log("Uploading %s" % binfile) + p.write_file() - # Start transfer and erase. - p.start() - # Upload the bin file - log("Uploading %s" % binfile) - p.write_file() + # Finalize + log("Done. Finalizing.") + p.stop() - # Finalize - log("Done. Finalizing.") - p.stop() if __name__ == "__main__": - main() - - + main() diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py index 432ee120de..5402af70aa 100755 --- a/extra/usb_updater/servo_updater.py +++ b/extra/usb_updater/servo_updater.py @@ -14,40 +14,46 @@ from __future__ import print_function import argparse +import json import os import re import subprocess import time -import json - -import fw_update import ecusb.tiny_servo_common as c +import fw_update from ecusb import tiny_servod + class ServoUpdaterException(Exception): - """Raised on exceptions generated by servo_updater.""" + """Raised on exceptions generated by servo_updater.""" -BOARD_C2D2 = 'c2d2' -BOARD_SERVO_MICRO = 'servo_micro' -BOARD_SERVO_V4 = 'servo_v4' -BOARD_SERVO_V4P1 = 'servo_v4p1' -BOARD_SWEETBERRY = 'sweetberry' + +BOARD_C2D2 = "c2d2" +BOARD_SERVO_MICRO = "servo_micro" +BOARD_SERVO_V4 = "servo_v4" +BOARD_SERVO_V4P1 = "servo_v4p1" +BOARD_SWEETBERRY = "sweetberry" DEFAULT_BOARD = BOARD_SERVO_V4 # These lists are to facilitate exposing choices in the command-line tool # below. -BOARDS = [BOARD_C2D2, BOARD_SERVO_MICRO, BOARD_SERVO_V4, BOARD_SERVO_V4P1, - BOARD_SWEETBERRY] +BOARDS = [ + BOARD_C2D2, + BOARD_SERVO_MICRO, + BOARD_SERVO_V4, + BOARD_SERVO_V4P1, + BOARD_SWEETBERRY, +] # Servo firmware bundles four channels of firmware. We need to make sure the # user does not request a non-existing channel, so keep the lists around to # guard on command-line usage. -DEFAULT_CHANNEL = STABLE_CHANNEL = 'stable' +DEFAULT_CHANNEL = STABLE_CHANNEL = "stable" -PREV_CHANNEL = 'prev' +PREV_CHANNEL = "prev" # The ordering here matters. From left to right it's the channel that the user # is most likely to be running. This is used to inform and warn the user if @@ -55,403 +61,436 @@ PREV_CHANNEL = 'prev' # user know they are running the 'stable' version before letting them know they # are running 'dev' or even 'alpah' which (while true) might cause confusion. -CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, 'dev', 'alpha'] +CHANNELS = [DEFAULT_CHANNEL, PREV_CHANNEL, "dev", "alpha"] -DEFAULT_BASE_PATH = '/usr/' -TEST_IMAGE_BASE_PATH = '/usr/local/' +DEFAULT_BASE_PATH = "/usr/" +TEST_IMAGE_BASE_PATH = "/usr/local/" -COMMON_PATH = 'share/servo_updater' +COMMON_PATH = "share/servo_updater" -FIRMWARE_DIR = 'firmware/' -CONFIGS_DIR = 'configs/' +FIRMWARE_DIR = "firmware/" +CONFIGS_DIR = "configs/" RETRIES_COUNT = 10 RETRIES_DELAY = 1 + def do_with_retries(func, *args): - """Try a function several times - - Call function passed as argument and check if no error happened. - If exception was raised by function, - it will be retried up to RETRIES_COUNT times. - - Args: - func: function that will be called - args: arguments passed to 'func' - - Returns: - If call to function was successful, its result will be returned. - If retries count was exceeded, exception will be raised. - """ - - retry = 0 - while retry < RETRIES_COUNT: - try: - return func(*args) - except Exception as e: - print('Retrying function %s: %s' % (func.__name__, e)) - retry = retry + 1 - time.sleep(RETRIES_DELAY) - continue - - raise Exception("'{}' failed after {} retries".format( - func.__name__, RETRIES_COUNT)) + """Try a function several times + + Call function passed as argument and check if no error happened. + If exception was raised by function, + it will be retried up to RETRIES_COUNT times. + + Args: + func: function that will be called + args: arguments passed to 'func' + + Returns: + If call to function was successful, its result will be returned. + If retries count was exceeded, exception will be raised. + """ + + retry = 0 + while retry < RETRIES_COUNT: + try: + return func(*args) + except Exception as e: + print("Retrying function %s: %s" % (func.__name__, e)) + retry = retry + 1 + time.sleep(RETRIES_DELAY) + continue + + raise Exception("'{}' failed after {} retries".format(func.__name__, RETRIES_COUNT)) + def flash(brdfile, serialno, binfile): - """Call fw_update to upload to updater USB endpoint. + """Call fw_update to upload to updater USB endpoint. + + Args: + brdfile: path to board configuration file + serialno: device serial number + binfile: firmware file + """ - Args: - brdfile: path to board configuration file - serialno: device serial number - binfile: firmware file - """ + p = fw_update.Supdate() + p.load_board(brdfile) + p.connect_usb(serialname=serialno) + p.load_file(binfile) - p = fw_update.Supdate() - p.load_board(brdfile) - p.connect_usb(serialname=serialno) - p.load_file(binfile) + # Start transfer and erase. + p.start() + # Upload the bin file + print("Uploading %s" % binfile) + p.write_file() - # Start transfer and erase. - p.start() - # Upload the bin file - print('Uploading %s' % binfile) - p.write_file() + # Finalize + print("Done. Finalizing.") + p.stop() - # Finalize - print('Done. Finalizing.') - p.stop() def flash2(vidpid, serialno, binfile): - """Call fw update via usb_updater2 commandline. - - Args: - vidpid: vendor id and product id of device - serialno: device serial number (optional) - binfile: firmware file - """ - - tool = 'usb_updater2' - cmd = '%s -d %s' % (tool, vidpid) - if serialno: - cmd += ' -S %s' % serialno - cmd += ' -n' - cmd += ' %s' % binfile - - print(cmd) - help_cmd = '%s --help' % tool - with open('/dev/null') as devnull: - valid_check = subprocess.call(help_cmd.split(), stdout=devnull, - stderr=devnull) - if valid_check: - raise ServoUpdaterException('%s exit with res = %d. Make sure the tool ' - 'is available on the device.' % (help_cmd, - valid_check)) - res = subprocess.call(cmd.split()) - - if res in (0, 1, 2): - return res - else: - raise ServoUpdaterException('%s exit with res = %d' % (cmd, res)) + """Call fw update via usb_updater2 commandline. + + Args: + vidpid: vendor id and product id of device + serialno: device serial number (optional) + binfile: firmware file + """ + + tool = "usb_updater2" + cmd = "%s -d %s" % (tool, vidpid) + if serialno: + cmd += " -S %s" % serialno + cmd += " -n" + cmd += " %s" % binfile + + print(cmd) + help_cmd = "%s --help" % tool + with open("/dev/null") as devnull: + valid_check = subprocess.call(help_cmd.split(), stdout=devnull, stderr=devnull) + if valid_check: + raise ServoUpdaterException( + "%s exit with res = %d. Make sure the tool " + "is available on the device." % (help_cmd, valid_check) + ) + res = subprocess.call(cmd.split()) + + if res in (0, 1, 2): + return res + else: + raise ServoUpdaterException("%s exit with res = %d" % (cmd, res)) + def select(tinys, region): - """Jump to specified boot region + """Jump to specified boot region - Ensure the servo is in the expected ro/rw region. - This function jumps to the required region and verify if jump was - successful by executing 'sysinfo' command and reading current region. - If response was not received or region is invalid, exception is raised. + Ensure the servo is in the expected ro/rw region. + This function jumps to the required region and verify if jump was + successful by executing 'sysinfo' command and reading current region. + If response was not received or region is invalid, exception is raised. - Args: - tinys: TinyServod object - region: region to jump to, only "rw" and "ro" is allowed - """ + Args: + tinys: TinyServod object + region: region to jump to, only "rw" and "ro" is allowed + """ - if region not in ['rw', 'ro']: - raise Exception('Region must be ro or rw') + if region not in ["rw", "ro"]: + raise Exception("Region must be ro or rw") - if region == 'ro': - cmd = 'reboot' - else: - cmd = 'sysjump %s' % region + if region == "ro": + cmd = "reboot" + else: + cmd = "sysjump %s" % region - tinys.pty._issue_cmd(cmd) + tinys.pty._issue_cmd(cmd) - tinys.close() - time.sleep(2) - tinys.reinitialize() + tinys.close() + time.sleep(2) + tinys.reinitialize() + + res = tinys.pty._issue_cmd_get_results("sysinfo", [r"Copy:[\s]+(RO|RW)"]) + current_region = res[0][1].lower() + if current_region != region: + raise Exception("Invalid region: %s/%s" % (current_region, region)) - res = tinys.pty._issue_cmd_get_results('sysinfo', [r'Copy:[\s]+(RO|RW)']) - current_region = res[0][1].lower() - if current_region != region: - raise Exception('Invalid region: %s/%s' % (current_region, region)) def do_version(tinys): - """Check version via ec console 'pty'. + """Check version via ec console 'pty'. + + Args: + tinys: TinyServod object - Args: - tinys: TinyServod object + Returns: + detected version number - Returns: - detected version number + Commands are: + # > version + # ... + # Build: tigertail_v1.1.6749-74d1a312e + """ + cmd = "version" + regex = r"Build:\s+(\S+)[\r\n]+" - Commands are: - # > version - # ... - # Build: tigertail_v1.1.6749-74d1a312e - """ - cmd = 'version' - regex = r'Build:\s+(\S+)[\r\n]+' + results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0] - results = tinys.pty._issue_cmd_get_results(cmd, [regex])[0] + return results[1].strip(" \t\r\n\0") - return results[1].strip(' \t\r\n\0') def do_updater_version(tinys): - """Check whether this uses python updater or c++ updater - - Args: - tinys: TinyServod object - - Returns: - updater version number. 2 or 6. - """ - vers = do_version(tinys) - - # Servo versions below 58 are from servo-9040.B. Versions starting with _v2 - # are newer than anything _v1, no need to check the exact number. Updater - # version is not directly queryable. - if re.search(r'_v[2-9]\.\d', vers): - return 6 - m = re.search(r'_v1\.1\.(\d\d\d\d)', vers) - if m: - version_number = int(m.group(1)) - if version_number < 5800: - return 2 - else: - return 6 - raise ServoUpdaterException( - "Can't determine updater target from vers: [%s]" % vers) + """Check whether this uses python updater or c++ updater -def _extract_version(boardname, binfile): - """Find the version string from |binfile|. + Args: + tinys: TinyServod object - Args: - boardname: the name of the board, eg. "servo_micro" - binfile: path to the binary to search + Returns: + updater version number. 2 or 6. + """ + vers = do_version(tinys) - Returns: - the version string. - """ - if boardname is None: - # cannot extract the version if the name is None - return None - rawstrings = subprocess.check_output( - ['cbfstool', binfile, 'read', '-r', 'RO_FRID', '-f', '/dev/stdout'], - **c.get_subprocess_args()) - m = re.match(r'%s_v\S+' % boardname, rawstrings) - if m: - newvers = m.group(0).strip(' \t\r\n\0') - else: - raise ServoUpdaterException("Can't find version from file: %s." % binfile) + # Servo versions below 58 are from servo-9040.B. Versions starting with _v2 + # are newer than anything _v1, no need to check the exact number. Updater + # version is not directly queryable. + if re.search(r"_v[2-9]\.\d", vers): + return 6 + m = re.search(r"_v1\.1\.(\d\d\d\d)", vers) + if m: + version_number = int(m.group(1)) + if version_number < 5800: + return 2 + else: + return 6 + raise ServoUpdaterException("Can't determine updater target from vers: [%s]" % vers) + + +def _extract_version(boardname, binfile): + """Find the version string from |binfile|. + + Args: + boardname: the name of the board, eg. "servo_micro" + binfile: path to the binary to search + + Returns: + the version string. + """ + if boardname is None: + # cannot extract the version if the name is None + return None + rawstrings = subprocess.check_output( + ["cbfstool", binfile, "read", "-r", "RO_FRID", "-f", "/dev/stdout"], + **c.get_subprocess_args() + ) + m = re.match(r"%s_v\S+" % boardname, rawstrings) + if m: + newvers = m.group(0).strip(" \t\r\n\0") + else: + raise ServoUpdaterException("Can't find version from file: %s." % binfile) + + return newvers - return newvers def get_firmware_channel(bname, version): - """Find out which channel |version| for |bname| came from. - - Args: - bname: board name - version: current version string - - Returns: - one of the channel names if |version| came from one of those, or None - """ - for channel in CHANNELS: - # Pass |bname| as cname to find the board specific file, and pass None as - # fname to ensure the default directory is searched - _, _, vers = get_files_and_version(bname, None, channel=channel) - if version == vers: - return channel - # None of the channels matched. This firmware is currently unknown. - return None + """Find out which channel |version| for |bname| came from. + + Args: + bname: board name + version: current version string + + Returns: + one of the channel names if |version| came from one of those, or None + """ + for channel in CHANNELS: + # Pass |bname| as cname to find the board specific file, and pass None as + # fname to ensure the default directory is searched + _, _, vers = get_files_and_version(bname, None, channel=channel) + if version == vers: + return channel + # None of the channels matched. This firmware is currently unknown. + return None + def get_files_and_version(cname, fname=None, channel=DEFAULT_CHANNEL): - """Select config and firmware binary files. - - This checks default file names and paths. - In: /usr/share/servo_updater/[firmware|configs] - check for board.json, board.bin - - Args: - cname: board name, or config name. eg. "servo_v4" or "servo_v4.json" - fname: firmware binary name. Can be None to try default. - channel: the channel requested for servo firmware. See |CHANNELS| above. - - Returns: - cname, fname, version: validated filenames selected from the path. - """ - for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH): - updater_path = os.path.join(p, COMMON_PATH) - if os.path.exists(updater_path): - break - else: - raise ServoUpdaterException('servo_updater/ dir not found in known spots.') - - firmware_path = os.path.join(updater_path, FIRMWARE_DIR) - configs_path = os.path.join(updater_path, CONFIGS_DIR) - - for p in (firmware_path, configs_path): - if not os.path.exists(p): - raise ServoUpdaterException('Could not find required path %r' % p) - - if not os.path.isfile(cname): - # If not an existing file, try checking on the default path. - newname = os.path.join(configs_path, cname) - if os.path.isfile(newname): - cname = newname + """Select config and firmware binary files. + + This checks default file names and paths. + In: /usr/share/servo_updater/[firmware|configs] + check for board.json, board.bin + + Args: + cname: board name, or config name. eg. "servo_v4" or "servo_v4.json" + fname: firmware binary name. Can be None to try default. + channel: the channel requested for servo firmware. See |CHANNELS| above. + + Returns: + cname, fname, version: validated filenames selected from the path. + """ + for p in (DEFAULT_BASE_PATH, TEST_IMAGE_BASE_PATH): + updater_path = os.path.join(p, COMMON_PATH) + if os.path.exists(updater_path): + break else: - # Try appending ".json" to convert board name to config file. - cname = newname + '.json' + raise ServoUpdaterException("servo_updater/ dir not found in known spots.") + + firmware_path = os.path.join(updater_path, FIRMWARE_DIR) + configs_path = os.path.join(updater_path, CONFIGS_DIR) + + for p in (firmware_path, configs_path): + if not os.path.exists(p): + raise ServoUpdaterException("Could not find required path %r" % p) + if not os.path.isfile(cname): - raise ServoUpdaterException("Can't find config file: %s." % cname) - - # Always retrieve the boardname - with open(cname) as data_file: - data = json.load(data_file) - boardname = data['board'] - - if not fname: - # If no |fname| supplied, look for the default locations with the board - # and channel requested. - binary_file = '%s.%s.bin' % (boardname, channel) - newname = os.path.join(firmware_path, binary_file) - if os.path.isfile(newname): - fname = newname - else: - raise ServoUpdaterException("Can't find firmware binary: %s." % - binary_file) - elif not os.path.isfile(fname): - # If a name is specified but not found, try the default path. - newname = os.path.join(firmware_path, fname) - if os.path.isfile(newname): - fname = newname + # If not an existing file, try checking on the default path. + newname = os.path.join(configs_path, cname) + if os.path.isfile(newname): + cname = newname + else: + # Try appending ".json" to convert board name to config file. + cname = newname + ".json" + if not os.path.isfile(cname): + raise ServoUpdaterException("Can't find config file: %s." % cname) + + # Always retrieve the boardname + with open(cname) as data_file: + data = json.load(data_file) + boardname = data["board"] + + if not fname: + # If no |fname| supplied, look for the default locations with the board + # and channel requested. + binary_file = "%s.%s.bin" % (boardname, channel) + newname = os.path.join(firmware_path, binary_file) + if os.path.isfile(newname): + fname = newname + else: + raise ServoUpdaterException("Can't find firmware binary: %s." % binary_file) + elif not os.path.isfile(fname): + # If a name is specified but not found, try the default path. + newname = os.path.join(firmware_path, fname) + if os.path.isfile(newname): + fname = newname + else: + raise ServoUpdaterException("Can't find file: %s." % fname) + + # Lastly, retrieve the version as well for decision making, debug, and + # informational purposes. + binvers = _extract_version(boardname, fname) + + return cname, fname, binvers + + +def main(): + parser = argparse.ArgumentParser(description="Image a servo device") + parser.add_argument( + "-p", + "--print", + dest="print_only", + action="store_true", + default=False, + help="only print available firmware for board/channel", + ) + parser.add_argument( + "-s", "--serialno", type=str, help="serial number to program", default=None + ) + parser.add_argument( + "-b", + "--board", + type=str, + help="Board configuration json file", + default=DEFAULT_BOARD, + choices=BOARDS, + ) + parser.add_argument( + "-c", + "--channel", + type=str, + help="Firmware channel to use", + default=DEFAULT_CHANNEL, + choices=CHANNELS, + ) + parser.add_argument( + "-f", "--file", type=str, help="Complete ec.bin file", default=None + ) + parser.add_argument( + "--force", + action="store_true", + help="Update even if version match", + default=False, + ) + parser.add_argument("-v", "--verbose", action="store_true", help="Chatty output") + parser.add_argument( + "-r", "--reboot", action="store_true", help="Always reboot, even after probe." + ) + + args = parser.parse_args() + + brdfile, binfile, newvers = get_files_and_version( + args.board, args.file, args.channel + ) + + # If the user only cares about the information then just print it here, + # and exit. + if args.print_only: + output = ("board: %s\n" "channel: %s\n" "firmware: %s") % ( + args.board, + args.channel, + newvers, + ) + print(output) + return + + serialno = args.serialno + + with open(brdfile) as data_file: + data = json.load(data_file) + vid, pid = int(data["vid"], 0), int(data["pid"], 0) + vidpid = "%04x:%04x" % (vid, pid) + iface = int(data["console"], 0) + boardname = data["board"] + + # Make sure device is up. + print("===== Waiting for USB device =====") + c.wait_for_usb(vidpid, serialname=serialno) + # We need a tiny_servod to query some information. Set it up first. + tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose) + + if not args.force: + vers = do_version(tinys) + print("Current %s version is %s" % (boardname, vers)) + print("Available %s version is %s" % (boardname, newvers)) + + if newvers == vers: + print("No version update needed") + if args.reboot: + select(tinys, "ro") + return + else: + print("Updating to recommended version.") + + # Make sure the servo MCU is in RO + print("===== Jumping to RO =====") + do_with_retries(select, tinys, "ro") + + print("===== Flashing RW =====") + vers = do_with_retries(do_updater_version, tinys) + # To make sure that the tiny_servod here does not interfere with other + # processes, close it out. + tinys.close() + + if vers == 2: + flash(brdfile, serialno, binfile) + elif vers == 6: + do_with_retries(flash2, vidpid, serialno, binfile) else: - raise ServoUpdaterException("Can't find file: %s." % fname) + raise ServoUpdaterException("Can't detect updater version") - # Lastly, retrieve the version as well for decision making, debug, and - # informational purposes. - binvers = _extract_version(boardname, fname) + # Make sure device is up. + c.wait_for_usb(vidpid, serialname=serialno) + # After we have made sure that it's back/available, reconnect the tiny servod. + tinys.reinitialize() - return cname, fname, binvers + # Make sure the servo MCU is in RW + print("===== Jumping to RW =====") + do_with_retries(select, tinys, "rw") -def main(): - parser = argparse.ArgumentParser(description='Image a servo device') - parser.add_argument('-p', '--print', dest='print_only', action='store_true', - default=False, - help='only print available firmware for board/channel') - parser.add_argument('-s', '--serialno', type=str, - help='serial number to program', default=None) - parser.add_argument('-b', '--board', type=str, - help='Board configuration json file', - default=DEFAULT_BOARD, choices=BOARDS) - parser.add_argument('-c', '--channel', type=str, - help='Firmware channel to use', - default=DEFAULT_CHANNEL, choices=CHANNELS) - parser.add_argument('-f', '--file', type=str, - help='Complete ec.bin file', default=None) - parser.add_argument('--force', action='store_true', - help='Update even if version match', default=False) - parser.add_argument('-v', '--verbose', action='store_true', - help='Chatty output') - parser.add_argument('-r', '--reboot', action='store_true', - help='Always reboot, even after probe.') - - args = parser.parse_args() - - brdfile, binfile, newvers = get_files_and_version(args.board, args.file, - args.channel) - - # If the user only cares about the information then just print it here, - # and exit. - if args.print_only: - output = ('board: %s\n' - 'channel: %s\n' - 'firmware: %s') % (args.board, args.channel, newvers) - print(output) - return - - serialno = args.serialno - - with open(brdfile) as data_file: - data = json.load(data_file) - vid, pid = int(data['vid'], 0), int(data['pid'], 0) - vidpid = '%04x:%04x' % (vid, pid) - iface = int(data['console'], 0) - boardname = data['board'] - - # Make sure device is up. - print('===== Waiting for USB device =====') - c.wait_for_usb(vidpid, serialname=serialno) - # We need a tiny_servod to query some information. Set it up first. - tinys = tiny_servod.TinyServod(vid, pid, iface, serialno, args.verbose) - - if not args.force: - vers = do_version(tinys) - print('Current %s version is %s' % (boardname, vers)) - print('Available %s version is %s' % (boardname, newvers)) - - if newvers == vers: - print('No version update needed') - if args.reboot: - select(tinys, 'ro') - return + print("===== Flashing RO =====") + vers = do_with_retries(do_updater_version, tinys) + + if vers == 2: + flash(brdfile, serialno, binfile) + elif vers == 6: + do_with_retries(flash2, vidpid, serialno, binfile) else: - print('Updating to recommended version.') - - # Make sure the servo MCU is in RO - print('===== Jumping to RO =====') - do_with_retries(select, tinys, 'ro') - - print('===== Flashing RW =====') - vers = do_with_retries(do_updater_version, tinys) - # To make sure that the tiny_servod here does not interfere with other - # processes, close it out. - tinys.close() - - if vers == 2: - flash(brdfile, serialno, binfile) - elif vers == 6: - do_with_retries(flash2, vidpid, serialno, binfile) - else: - raise ServoUpdaterException("Can't detect updater version") - - # Make sure device is up. - c.wait_for_usb(vidpid, serialname=serialno) - # After we have made sure that it's back/available, reconnect the tiny servod. - tinys.reinitialize() - - # Make sure the servo MCU is in RW - print('===== Jumping to RW =====') - do_with_retries(select, tinys, 'rw') - - print('===== Flashing RO =====') - vers = do_with_retries(do_updater_version, tinys) - - if vers == 2: - flash(brdfile, serialno, binfile) - elif vers == 6: - do_with_retries(flash2, vidpid, serialno, binfile) - else: - raise ServoUpdaterException("Can't detect updater version") - - # Make sure the servo MCU is in RO - print('===== Rebooting =====') - do_with_retries(select, tinys, 'ro') - # Perform additional reboot to free USB/UART resources, taken by tiny servod. - # See https://issuetracker.google.com/196021317 for background. - tinys.pty._issue_cmd('reboot') - - print('===== Finished =====') - -if __name__ == '__main__': - main() + raise ServoUpdaterException("Can't detect updater version") + + # Make sure the servo MCU is in RO + print("===== Rebooting =====") + do_with_retries(select, tinys, "ro") + # Perform additional reboot to free USB/UART resources, taken by tiny servod. + # See https://issuetracker.google.com/196021317 for background. + tinys.pty._issue_cmd("reboot") + + print("===== Finished =====") + + +if __name__ == "__main__": + main() diff --git a/firmware_builder.py b/firmware_builder.py index 78b7614190..d2548c3f5f 100755 --- a/firmware_builder.py +++ b/firmware_builder.py @@ -16,21 +16,20 @@ import pathlib import subprocess import sys -# pylint: disable=import-error -from google.protobuf import json_format - from chromite.api.gen_sdk.chromite.api import firmware_pb2 +# pylint: disable=import-error +from google.protobuf import json_format -DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles' -DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata' +DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles" +DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata" # The the list of boards whose on-device unit tests we will verify compilation. # TODO(b/172501728) On-device unit tests should build for all boards, but # they've bit rotted, so we only build the ones that compile. BOARDS_UNIT_TEST = [ - 'bloonchipper', - 'dartmonkey', + "bloonchipper", + "dartmonkey", ] @@ -51,59 +50,57 @@ def build(opts): "When --code-coverage is selected, 'build' is a no-op. " "Run 'test' with --code-coverage instead." ) - with open(opts.metrics, 'w') as f: + with open(opts.metrics, "w") as f: f.write(json_format.MessageToJson(metric_list)) return ec_dir = pathlib.Path(__file__).parent subprocess.run([ec_dir / "util" / "check_clang_format.py"], check=True) - cmd = ['make', 'buildall_only', f'-j{opts.cpus}'] + cmd = ["make", "buildall_only", f"-j{opts.cpus}"] print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) ec_dir = os.path.dirname(__file__) - build_dir = os.path.join(ec_dir, 'build') + build_dir = os.path.join(ec_dir, "build") for build_target in sorted(os.listdir(build_dir)): metric = metric_list.value.add() metric.target_name = build_target - metric.platform_name = 'ec' - for variant in ['RO', 'RW']: + metric.platform_name = "ec" + for variant in ["RO", "RW"]: memsize_file = ( pathlib.Path(build_dir) / build_target / variant - / f'ec.{variant}.elf.memsize.txt' + / f"ec.{variant}.elf.memsize.txt" ) if memsize_file.exists(): parse_memsize(memsize_file, metric, variant) - with open(opts.metrics, 'w') as f: + with open(opts.metrics, "w") as f: f.write(json_format.MessageToJson(metric_list)) # Ensure that there are no regressions for boards that build successfully # with clang: b/172020503. - cmd = ['./util/build_with_clang.py'] + cmd = ["./util/build_with_clang.py"] print(f'# Running {" ".join(cmd)}.') - subprocess.run(cmd, - cwd=os.path.dirname(__file__), - check=True) + subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) UNITS = { - 'B': 1, - 'KB': 1024, - 'MB': 1024 * 1024, - 'GB': 1024 * 1024 * 1024, + "B": 1, + "KB": 1024, + "MB": 1024 * 1024, + "GB": 1024 * 1024 * 1024, } def parse_memsize(filename, metric, variant): - with open(filename, 'r') as infile: + with open(filename, "r") as infile: # Skip header line infile.readline() for line in infile.readlines(): parts = line.split() fw_section = metric.fw_section.add() - fw_section.region = variant + '_' + parts[0][:-1] + fw_section.region = variant + "_" + parts[0][:-1] fw_section.used = int(parts[1]) * UNITS[parts[2]] fw_section.total = int(parts[3]) * UNITS[parts[4]] fw_section.track_on_gerrit = False @@ -135,7 +132,7 @@ def write_metadata(opts, info): bundle_metadata_file = ( opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE ) - with open(bundle_metadata_file, 'w') as f: + with open(bundle_metadata_file, "w") as f: f.write(json_format.MessageToJson(info)) @@ -145,10 +142,10 @@ def bundle_coverage(opts): info.bcs_version_info.version_string = opts.bcs_version bundle_dir = get_bundle_dir(opts) ec_dir = os.path.dirname(__file__) - tarball_name = 'coverage.tbz2' + tarball_name = "coverage.tbz2" tarball_path = os.path.join(bundle_dir, tarball_name) - cmd = ['tar', 'cvfj', tarball_path, 'lcov.info'] - subprocess.run(cmd, cwd=os.path.join(ec_dir, 'build/coverage'), check=True) + cmd = ["tar", "cvfj", tarball_path, "lcov.info"] + subprocess.run(cmd, cwd=os.path.join(ec_dir, "build/coverage"), check=True) meta = info.objects.add() meta.file_name = tarball_name meta.lcov_info.type = ( @@ -164,16 +161,20 @@ def bundle_firmware(opts): info.bcs_version_info.version_string = opts.bcs_version bundle_dir = get_bundle_dir(opts) ec_dir = os.path.dirname(__file__) - for build_target in sorted(os.listdir(os.path.join(ec_dir, 'build'))): - tarball_name = ''.join([build_target, '.firmware.tbz2']) + for build_target in sorted(os.listdir(os.path.join(ec_dir, "build"))): + tarball_name = "".join([build_target, ".firmware.tbz2"]) tarball_path = os.path.join(bundle_dir, tarball_name) cmd = [ - 'tar', 'cvfj', tarball_path, - '--exclude=*.o.d', '--exclude=*.o', '.', + "tar", + "cvfj", + tarball_path, + "--exclude=*.o.d", + "--exclude=*.o", + ".", ] subprocess.run( cmd, - cwd=os.path.join(ec_dir, 'build', build_target), + cwd=os.path.join(ec_dir, "build", build_target), check=True, ) meta = info.objects.add() @@ -191,7 +192,7 @@ def test(opts): """Runs all of the unit tests for EC firmware""" # TODO(b/169178847): Add appropriate metric information metrics = firmware_pb2.FwTestMetricList() - with open(opts.metrics, 'w') as f: + with open(opts.metrics, "w") as f: f.write(json_format.MessageToJson(metrics)) # If building for code coverage, build the 'coverage' target, which @@ -200,8 +201,8 @@ def test(opts): # # Otherwise, build the 'runtests' target, which verifies all # posix-based unit tests build and pass. - target = 'coverage' if opts.code_coverage else 'runtests' - cmd = ['make', target, f'-j{opts.cpus}'] + target = "coverage" if opts.code_coverage else "runtests" + cmd = ["make", target, f"-j{opts.cpus}"] print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) @@ -209,13 +210,13 @@ def test(opts): # Verify compilation of the on-device unit test binaries. # TODO(b/172501728) These should build for all boards, but they've bit # rotted, so we only build the ones that compile. - cmd = ['make', f'-j{opts.cpus}'] - cmd.extend(['tests-' + b for b in BOARDS_UNIT_TEST]) + cmd = ["make", f"-j{opts.cpus}"] + cmd.extend(["tests-" + b for b in BOARDS_UNIT_TEST]) print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) # Verify the tests pass with ASan also - cmd = ['make', 'TEST_ASAN=y', target, f'-j{opts.cpus}'] + cmd = ["make", "TEST_ASAN=y", target, f"-j{opts.cpus}"] print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=os.path.dirname(__file__), check=True) @@ -227,8 +228,8 @@ def main(args): """ opts = parse_args(args) - if not hasattr(opts, 'func'): - print('Must select a valid sub command!') + if not hasattr(opts, "func"): + print("Must select a valid sub command!") return -1 # Run selected sub command function @@ -244,66 +245,64 @@ def parse_args(args): parser = argparse.ArgumentParser(description=__doc__) parser.add_argument( - '--cpus', + "--cpus", default=multiprocessing.cpu_count(), - help='The number of cores to use.', + help="The number of cores to use.", ) parser.add_argument( - '--metrics', - dest='metrics', + "--metrics", + dest="metrics", required=True, - help='File to write the json-encoded MetricsList proto message.', + help="File to write the json-encoded MetricsList proto message.", ) parser.add_argument( - '--metadata', + "--metadata", required=False, - help='Full pathname for the file in which to write build artifact ' - 'metadata.', + help="Full pathname for the file in which to write build artifact " "metadata.", ) parser.add_argument( - '--output-dir', + "--output-dir", required=False, - help='Full pathanme for the directory in which to bundle build ' - 'artifacts.', + help="Full pathanme for the directory in which to bundle build " "artifacts.", ) parser.add_argument( - '--code-coverage', + "--code-coverage", required=False, - action='store_true', - help='Build host-based unit tests for code coverage.', + action="store_true", + help="Build host-based unit tests for code coverage.", ) parser.add_argument( - '--bcs-version', - dest='bcs_version', - default='', + "--bcs-version", + dest="bcs_version", + default="", required=False, # TODO(b/180008931): make this required=True. - help='BCS version to include in metadata.', + help="BCS version to include in metadata.", ) # Would make this required=True, but not available until 3.7 sub_cmds = parser.add_subparsers() - build_cmd = sub_cmds.add_parser('build', help='Builds all firmware targets') + build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets") build_cmd.set_defaults(func=build) build_cmd = sub_cmds.add_parser( - 'bundle', - help='Creates a tarball containing build ' - 'artifacts from all firmware targets', + "bundle", + help="Creates a tarball containing build " + "artifacts from all firmware targets", ) build_cmd.set_defaults(func=bundle) - test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests') + test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests") test_cmd.set_defaults(func=test) return parser.parse_args(args) -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/setup.py b/setup.py index fc6c5d396b..2274d95c2f 100644 --- a/setup.py +++ b/setup.py @@ -10,7 +10,7 @@ setup( author="Aseda Aboagye", author_email="aaboagye@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "util"}, + package_dir={"": "util"}, packages=["ec3po"], py_modules=["ec3po.console", "ec3po.interpreter"], description="EC console interpreter.", @@ -22,7 +22,7 @@ setup( author="Nick Sanders", author_email="nsanders@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "extra/tigertool"}, + package_dir={"": "extra/tigertool"}, packages=["ecusb"], description="Tiny implementation of servod.", ) @@ -33,17 +33,23 @@ setup( author="Nick Sanders", author_email="nsanders@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "extra/usb_updater"}, + package_dir={"": "extra/usb_updater"}, py_modules=["servo_updater", "fw_update"], - entry_points = { + entry_points={ "console_scripts": ["servo_updater=servo_updater:main"], }, - data_files=[("share/servo_updater/configs", - ["extra/usb_updater/c2d2.json", - "extra/usb_updater/servo_v4.json", - "extra/usb_updater/servo_v4p1.json", - "extra/usb_updater/servo_micro.json", - "extra/usb_updater/sweetberry.json"])], + data_files=[ + ( + "share/servo_updater/configs", + [ + "extra/usb_updater/c2d2.json", + "extra/usb_updater/servo_v4.json", + "extra/usb_updater/servo_v4p1.json", + "extra/usb_updater/servo_micro.json", + "extra/usb_updater/sweetberry.json", + ], + ) + ], description="Servo usb updater.", ) @@ -53,9 +59,9 @@ setup( author="Nick Sanders", author_email="nsanders@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "extra/usb_power"}, + package_dir={"": "extra/usb_power"}, py_modules=["powerlog", "stats_manager"], - entry_points = { + entry_points={ "console_scripts": ["powerlog=powerlog:main"], }, description="Sweetberry power logger.", @@ -67,9 +73,9 @@ setup( author="Nick Sanders", author_email="nsanders@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "extra/usb_serial"}, + package_dir={"": "extra/usb_serial"}, py_modules=["console"], - entry_points = { + entry_points={ "console_scripts": ["usb_console=console:main"], }, description="Tool to open the usb console on servo, cr50.", @@ -81,11 +87,10 @@ setup( author="Wei-Han Chen", author_email="stimim@chromium.org", url="https://www.chromium.org/chromium-os/ec-development", - package_dir={"" : "util"}, + package_dir={"": "util"}, py_modules=["unpack_ftb"], - entry_points = { + entry_points={ "console_scripts": ["unpack_ftb=unpack_ftb:main"], }, description="Tool to convert ST touchpad .ftb file to .bin", ) - diff --git a/test/run_device_tests.py b/test/run_device_tests.py index 8de2fa417c..09f255f43e 100755 --- a/test/run_device_tests.py +++ b/test/run_device_tests.py @@ -51,63 +51,74 @@ import time from concurrent.futures.thread import ThreadPoolExecutor from enum import Enum from pathlib import Path -from typing import Optional, BinaryIO, List +from typing import BinaryIO, List, Optional # pylint: disable=import-error import colorama # type: ignore[import] -from contextlib2 import ExitStack import fmap +from contextlib2 import ExitStack + # pylint: enable=import-error EC_DIR = Path(os.path.dirname(os.path.realpath(__file__))).parent -JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_jlink.py') -SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, 'util/flash_ec') +JTRACE_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_jlink.py") +SERVO_MICRO_FLASH_SCRIPT = os.path.join(EC_DIR, "util/flash_ec") -ALL_TESTS_PASSED_REGEX = re.compile(r'Pass!\r\n') -ALL_TESTS_FAILED_REGEX = re.compile(r'Fail! \(\d+ tests\)\r\n') +ALL_TESTS_PASSED_REGEX = re.compile(r"Pass!\r\n") +ALL_TESTS_FAILED_REGEX = re.compile(r"Fail! \(\d+ tests\)\r\n") -SINGLE_CHECK_PASSED_REGEX = re.compile(r'Pass: .*') -SINGLE_CHECK_FAILED_REGEX = re.compile(r'.*failed:.*') +SINGLE_CHECK_PASSED_REGEX = re.compile(r"Pass: .*") +SINGLE_CHECK_FAILED_REGEX = re.compile(r".*failed:.*") -ASSERTION_FAILURE_REGEX = re.compile(r'ASSERTION FAILURE.*') +ASSERTION_FAILURE_REGEX = re.compile(r"ASSERTION FAILURE.*") DATA_ACCESS_VIOLATION_8020000_REGEX = re.compile( - r'Data access violation, mfar = 8020000\r\n') + r"Data access violation, mfar = 8020000\r\n" +) DATA_ACCESS_VIOLATION_8040000_REGEX = re.compile( - r'Data access violation, mfar = 8040000\r\n') + r"Data access violation, mfar = 8040000\r\n" +) DATA_ACCESS_VIOLATION_80C0000_REGEX = re.compile( - r'Data access violation, mfar = 80c0000\r\n') + r"Data access violation, mfar = 80c0000\r\n" +) DATA_ACCESS_VIOLATION_80E0000_REGEX = re.compile( - r'Data access violation, mfar = 80e0000\r\n') + r"Data access violation, mfar = 80e0000\r\n" +) DATA_ACCESS_VIOLATION_20000000_REGEX = re.compile( - r'Data access violation, mfar = 20000000\r\n') + r"Data access violation, mfar = 20000000\r\n" +) DATA_ACCESS_VIOLATION_24000000_REGEX = re.compile( - r'Data access violation, mfar = 24000000\r\n') + r"Data access violation, mfar = 24000000\r\n" +) -BLOONCHIPPER = 'bloonchipper' -DARTMONKEY = 'dartmonkey' +BLOONCHIPPER = "bloonchipper" +DARTMONKEY = "dartmonkey" -JTRACE = 'jtrace' -SERVO_MICRO = 'servo_micro' +JTRACE = "jtrace" +SERVO_MICRO = "servo_micro" -GCC = 'gcc' -CLANG = 'clang' +GCC = "gcc" +CLANG = "clang" -TEST_ASSETS_BUCKET = 'gs://chromiumos-test-assets-public/fpmcu/RO' +TEST_ASSETS_BUCKET = "gs://chromiumos-test-assets-public/fpmcu/RO" DARTMONKEY_IMAGE_PATH = os.path.join( - TEST_ASSETS_BUCKET, 'dartmonkey_v2.0.2887-311310808.bin') + TEST_ASSETS_BUCKET, "dartmonkey_v2.0.2887-311310808.bin" +) NOCTURNE_FP_IMAGE_PATH = os.path.join( - TEST_ASSETS_BUCKET, 'nocturne_fp_v2.2.64-58cf5974e.bin') -NAMI_FP_IMAGE_PATH = os.path.join( - TEST_ASSETS_BUCKET, 'nami_fp_v2.2.144-7a08e07eb.bin') + TEST_ASSETS_BUCKET, "nocturne_fp_v2.2.64-58cf5974e.bin" +) +NAMI_FP_IMAGE_PATH = os.path.join(TEST_ASSETS_BUCKET, "nami_fp_v2.2.144-7a08e07eb.bin") BLOONCHIPPER_V4277_IMAGE_PATH = os.path.join( - TEST_ASSETS_BUCKET, 'bloonchipper_v2.0.4277-9f652bb3.bin') + TEST_ASSETS_BUCKET, "bloonchipper_v2.0.4277-9f652bb3.bin" +) BLOONCHIPPER_V5938_IMAGE_PATH = os.path.join( - TEST_ASSETS_BUCKET, 'bloonchipper_v2.0.5938-197506c1.bin') + TEST_ASSETS_BUCKET, "bloonchipper_v2.0.5938-197506c1.bin" +) class ImageType(Enum): """EC Image type to use for the test.""" + RO = 1 RW = 2 @@ -115,9 +126,16 @@ class ImageType(Enum): class BoardConfig: """Board-specific configuration.""" - def __init__(self, name, servo_uart_name, servo_power_enable, - rollback_region0_regex, rollback_region1_regex, mpu_regex, - variants): + def __init__( + self, + name, + servo_uart_name, + servo_power_enable, + rollback_region0_regex, + rollback_region1_regex, + mpu_regex, + variants, + ): self.name = name self.servo_uart_name = servo_uart_name self.servo_power_enable = servo_power_enable @@ -130,18 +148,31 @@ class BoardConfig: class TestConfig: """Configuration for a given test.""" - def __init__(self, test_name, image_to_use=ImageType.RW, - finish_regexes=None, fail_regexes=None, toggle_power=False, - test_args=None, num_flash_attempts=2, timeout_secs=10, - enable_hw_write_protect=False, ro_image=None, build_board=None, - config_name=None): + def __init__( + self, + test_name, + image_to_use=ImageType.RW, + finish_regexes=None, + fail_regexes=None, + toggle_power=False, + test_args=None, + num_flash_attempts=2, + timeout_secs=10, + enable_hw_write_protect=False, + ro_image=None, + build_board=None, + config_name=None, + ): if test_args is None: test_args = [] if finish_regexes is None: finish_regexes = [ALL_TESTS_PASSED_REGEX, ALL_TESTS_FAILED_REGEX] if fail_regexes is None: - fail_regexes = [SINGLE_CHECK_FAILED_REGEX, ALL_TESTS_FAILED_REGEX, - ASSERTION_FAILURE_REGEX] + fail_regexes = [ + SINGLE_CHECK_FAILED_REGEX, + ALL_TESTS_FAILED_REGEX, + ASSERTION_FAILURE_REGEX, + ] if config_name is None: config_name = test_name @@ -177,68 +208,104 @@ class AllTests: @staticmethod def get_public_tests(board_config: BoardConfig) -> List[TestConfig]: tests = [ - TestConfig(test_name='aes'), - TestConfig(test_name='cec'), - TestConfig(test_name='cortexm_fpu'), - TestConfig(test_name='crc'), - TestConfig(test_name='flash_physical', image_to_use=ImageType.RO, - toggle_power=True), - TestConfig(test_name='flash_write_protect', - image_to_use=ImageType.RO, - toggle_power=True, enable_hw_write_protect=True), - TestConfig(test_name='fpsensor_hw'), - TestConfig(config_name='fpsensor_spi_ro', test_name='fpsensor', - image_to_use=ImageType.RO, test_args=['spi']), - TestConfig(config_name='fpsensor_spi_rw', test_name='fpsensor', - test_args=['spi']), - TestConfig(config_name='fpsensor_uart_ro', test_name='fpsensor', - image_to_use=ImageType.RO, test_args=['uart']), - TestConfig(config_name='fpsensor_uart_rw', test_name='fpsensor', - test_args=['uart']), - TestConfig(config_name='mpu_ro', test_name='mpu', - image_to_use=ImageType.RO, - finish_regexes=[board_config.mpu_regex]), - TestConfig(config_name='mpu_rw', test_name='mpu', - finish_regexes=[board_config.mpu_regex]), - TestConfig(test_name='mutex'), - TestConfig(test_name='pingpong'), - TestConfig(test_name='printf'), - TestConfig(test_name='queue'), - TestConfig(config_name='rollback_region0', test_name='rollback', - finish_regexes=[board_config.rollback_region0_regex], - test_args=['region0']), - TestConfig(config_name='rollback_region1', test_name='rollback', - finish_regexes=[board_config.rollback_region1_regex], - test_args=['region1']), - TestConfig(test_name='rollback_entropy', image_to_use=ImageType.RO), - TestConfig(test_name='rtc'), - TestConfig(test_name='sha256'), - TestConfig(test_name='sha256_unrolled'), - TestConfig(test_name='static_if'), - TestConfig(test_name='stdlib'), - TestConfig(config_name='system_is_locked_wp_on', - test_name='system_is_locked', test_args=['wp_on'], - toggle_power=True, enable_hw_write_protect=True), - TestConfig(config_name='system_is_locked_wp_off', - test_name='system_is_locked', test_args=['wp_off'], - toggle_power=True, enable_hw_write_protect=False), - TestConfig(test_name='timer_dos'), - TestConfig(test_name='utils', timeout_secs=20), - TestConfig(test_name='utils_str'), + TestConfig(test_name="aes"), + TestConfig(test_name="cec"), + TestConfig(test_name="cortexm_fpu"), + TestConfig(test_name="crc"), + TestConfig( + test_name="flash_physical", image_to_use=ImageType.RO, toggle_power=True + ), + TestConfig( + test_name="flash_write_protect", + image_to_use=ImageType.RO, + toggle_power=True, + enable_hw_write_protect=True, + ), + TestConfig(test_name="fpsensor_hw"), + TestConfig( + config_name="fpsensor_spi_ro", + test_name="fpsensor", + image_to_use=ImageType.RO, + test_args=["spi"], + ), + TestConfig( + config_name="fpsensor_spi_rw", test_name="fpsensor", test_args=["spi"] + ), + TestConfig( + config_name="fpsensor_uart_ro", + test_name="fpsensor", + image_to_use=ImageType.RO, + test_args=["uart"], + ), + TestConfig( + config_name="fpsensor_uart_rw", test_name="fpsensor", test_args=["uart"] + ), + TestConfig( + config_name="mpu_ro", + test_name="mpu", + image_to_use=ImageType.RO, + finish_regexes=[board_config.mpu_regex], + ), + TestConfig( + config_name="mpu_rw", + test_name="mpu", + finish_regexes=[board_config.mpu_regex], + ), + TestConfig(test_name="mutex"), + TestConfig(test_name="pingpong"), + TestConfig(test_name="printf"), + TestConfig(test_name="queue"), + TestConfig( + config_name="rollback_region0", + test_name="rollback", + finish_regexes=[board_config.rollback_region0_regex], + test_args=["region0"], + ), + TestConfig( + config_name="rollback_region1", + test_name="rollback", + finish_regexes=[board_config.rollback_region1_regex], + test_args=["region1"], + ), + TestConfig(test_name="rollback_entropy", image_to_use=ImageType.RO), + TestConfig(test_name="rtc"), + TestConfig(test_name="sha256"), + TestConfig(test_name="sha256_unrolled"), + TestConfig(test_name="static_if"), + TestConfig(test_name="stdlib"), + TestConfig( + config_name="system_is_locked_wp_on", + test_name="system_is_locked", + test_args=["wp_on"], + toggle_power=True, + enable_hw_write_protect=True, + ), + TestConfig( + config_name="system_is_locked_wp_off", + test_name="system_is_locked", + test_args=["wp_off"], + toggle_power=True, + enable_hw_write_protect=False, + ), + TestConfig(test_name="timer_dos"), + TestConfig(test_name="utils", timeout_secs=20), + TestConfig(test_name="utils_str"), ] if board_config.name == BLOONCHIPPER: - tests.append(TestConfig(test_name='stm32f_rtc')) + tests.append(TestConfig(test_name="stm32f_rtc")) # Run panic data tests for all boards and RO versions. for variant_name, variant_info in board_config.variants.items(): tests.append( - TestConfig(config_name='panic_data_' + variant_name, - test_name='panic_data', - fail_regexes=[SINGLE_CHECK_FAILED_REGEX, - ALL_TESTS_FAILED_REGEX], - ro_image=variant_info.get('ro_image_path'), - build_board=variant_info.get('build_board'))) + TestConfig( + config_name="panic_data_" + variant_name, + test_name="panic_data", + fail_regexes=[SINGLE_CHECK_FAILED_REGEX, ALL_TESTS_FAILED_REGEX], + ro_image=variant_info.get("ro_image_path"), + build_board=variant_info.get("build_board"), + ) + ) return tests @@ -248,75 +315,72 @@ class AllTests: tests = [] try: current_dir = os.path.dirname(__file__) - private_dir = os.path.join(current_dir, os.pardir, 'private/test') + private_dir = os.path.join(current_dir, os.pardir, "private/test") have_private = os.path.isdir(private_dir) if not have_private: return [] sys.path.append(private_dir) import private_tests # pylint: disable=import-error + for test_args in private_tests.tests: tests.append(TestConfig(**test_args)) # Catch all exceptions to avoid disruptions in public repo except BaseException as e: - logging.debug('Failed to get list of private tests: %s', str(e)) - logging.debug('Ignore error and continue.') + logging.debug("Failed to get list of private tests: %s", str(e)) + logging.debug("Ignore error and continue.") return [] return tests BLOONCHIPPER_CONFIG = BoardConfig( name=BLOONCHIPPER, - servo_uart_name='raw_fpmcu_console_uart_pty', - servo_power_enable='fpmcu_pp3300', + servo_uart_name="raw_fpmcu_console_uart_pty", + servo_power_enable="fpmcu_pp3300", rollback_region0_regex=DATA_ACCESS_VIOLATION_8020000_REGEX, rollback_region1_regex=DATA_ACCESS_VIOLATION_8040000_REGEX, mpu_regex=DATA_ACCESS_VIOLATION_20000000_REGEX, variants={ - 'bloonchipper_v2.0.4277': { - 'ro_image_path': BLOONCHIPPER_V4277_IMAGE_PATH - }, - 'bloonchipper_v2.0.5938': { - 'ro_image_path': BLOONCHIPPER_V5938_IMAGE_PATH - } - } + "bloonchipper_v2.0.4277": {"ro_image_path": BLOONCHIPPER_V4277_IMAGE_PATH}, + "bloonchipper_v2.0.5938": {"ro_image_path": BLOONCHIPPER_V5938_IMAGE_PATH}, + }, ) DARTMONKEY_CONFIG = BoardConfig( name=DARTMONKEY, - servo_uart_name='raw_fpmcu_console_uart_pty', - servo_power_enable='fpmcu_pp3300', + servo_uart_name="raw_fpmcu_console_uart_pty", + servo_power_enable="fpmcu_pp3300", rollback_region0_regex=DATA_ACCESS_VIOLATION_80C0000_REGEX, rollback_region1_regex=DATA_ACCESS_VIOLATION_80E0000_REGEX, mpu_regex=DATA_ACCESS_VIOLATION_24000000_REGEX, # For dartmonkey board, run panic data test also on nocturne_fp and # nami_fp boards with appropriate RO image. variants={ - 'dartmonkey_v2.0.2887': { - 'ro_image_path': DARTMONKEY_IMAGE_PATH + "dartmonkey_v2.0.2887": {"ro_image_path": DARTMONKEY_IMAGE_PATH}, + "nocturne_fp_v2.2.64": { + "ro_image_path": NOCTURNE_FP_IMAGE_PATH, + "build_board": "nocturne_fp", }, - 'nocturne_fp_v2.2.64': { - 'ro_image_path': NOCTURNE_FP_IMAGE_PATH, - 'build_board': 'nocturne_fp' + "nami_fp_v2.2.144": { + "ro_image_path": NAMI_FP_IMAGE_PATH, + "build_board": "nami_fp", }, - 'nami_fp_v2.2.144': { - 'ro_image_path': NAMI_FP_IMAGE_PATH, - 'build_board': 'nami_fp' - } - } + }, ) BOARD_CONFIGS = { - 'bloonchipper': BLOONCHIPPER_CONFIG, - 'dartmonkey': DARTMONKEY_CONFIG, + "bloonchipper": BLOONCHIPPER_CONFIG, + "dartmonkey": DARTMONKEY_CONFIG, } def read_file_gsutil(path: str) -> bytes: """Get data from bucket, using gsutil tool""" - cmd = ['gsutil', 'cat', path] + cmd = ["gsutil", "cat", path] - logging.debug('Running command: "%s"', ' '.join(cmd)) - gsutil = subprocess.run(cmd, stdout=subprocess.PIPE) # pylint: disable=subprocess-run-check + logging.debug('Running command: "%s"', " ".join(cmd)) + gsutil = subprocess.run( + cmd, stdout=subprocess.PIPE + ) # pylint: disable=subprocess-run-check gsutil.check_returncode() return gsutil.stdout @@ -324,9 +388,9 @@ def read_file_gsutil(path: str) -> bytes: def find_section_offset_size(section: str, image: bytes) -> (int, int): """Get offset and size of the section in image""" - areas = fmap.fmap_decode(image)['areas'] - area = next(area for area in areas if area['name'] == section) - return area['offset'], area['size'] + areas = fmap.fmap_decode(image)["areas"] + area = next(area for area in areas if area["name"] == section) + return area["offset"], area["size"] def read_section(src: bytes, section: str) -> bytes: @@ -341,10 +405,10 @@ def write_section(data: bytes, image: bytearray, section: str): (section_start, section_size) = find_section_offset_size(section, image) if section_size < len(data): - raise ValueError(section + ' section size is not enough to store data') + raise ValueError(section + " section size is not enough to store data") section_end = section_start + section_size - filling = bytes([0xff for _ in range(section_size - len(data))]) + filling = bytes([0xFF for _ in range(section_size - len(data))]) image[section_start:section_end] = data + filling @@ -355,12 +419,14 @@ def copy_section(src: bytes, dst: bytearray, section: str): (dst_start, dst_size) = find_section_offset_size(section, dst) if dst_size < src_size: - raise ValueError('Section ' + section + ' from source image has ' - 'greater size than the section in destination image') + raise ValueError( + "Section " + section + " from source image has " + "greater size than the section in destination image" + ) src_end = src_start + src_size dst_end = dst_start + dst_size - filling = bytes([0xff for _ in range(dst_size - src_size)]) + filling = bytes([0xFF for _ in range(dst_size - src_size)]) dst[dst_start:dst_end] = src[src_start:src_end] + filling @@ -368,28 +434,28 @@ def copy_section(src: bytes, dst: bytearray, section: str): def replace_ro(image: bytearray, ro: bytes): """Replace RO in image with provided one""" # Backup RO public key since its private part was used to sign RW. - ro_pubkey = read_section(image, 'KEY_RO') + ro_pubkey = read_section(image, "KEY_RO") # Copy RO part of the firmware to the image. Please note that RO public key # is copied too since EC_RO area includes KEY_RO area. - copy_section(ro, image, 'EC_RO') + copy_section(ro, image, "EC_RO") # Restore RO public key. - write_section(ro_pubkey, image, 'KEY_RO') + write_section(ro_pubkey, image, "KEY_RO") def get_console(board_config: BoardConfig) -> Optional[str]: """Get the name of the console for a given board.""" cmd = [ - 'dut-control', + "dut-control", board_config.servo_uart_name, ] - logging.debug('Running command: "%s"', ' '.join(cmd)) + logging.debug('Running command: "%s"', " ".join(cmd)) with subprocess.Popen(cmd, stdout=subprocess.PIPE) as proc: for line in io.TextIOWrapper(proc.stdout): # type: ignore[arg-type] logging.debug(line) - pty = line.split(':') + pty = line.split(":") if len(pty) == 2 and pty[0] == board_config.servo_uart_name: return pty[1].strip() @@ -399,77 +465,82 @@ def get_console(board_config: BoardConfig) -> Optional[str]: def power(board_config: BoardConfig, on: bool) -> None: """Turn power to board on/off.""" if on: - state = 'pp3300' + state = "pp3300" else: - state = 'off' + state = "off" cmd = [ - 'dut-control', - board_config.servo_power_enable + ':' + state, + "dut-control", + board_config.servo_power_enable + ":" + state, ] - logging.debug('Running command: "%s"', ' '.join(cmd)) + logging.debug('Running command: "%s"', " ".join(cmd)) subprocess.run(cmd).check_returncode() # pylint: disable=subprocess-run-check def hw_write_protect(enable: bool) -> None: """Enable/disable hardware write protect.""" if enable: - state = 'force_on' + state = "force_on" else: - state = 'force_off' + state = "force_off" cmd = [ - 'dut-control', - 'fw_wp_state:' + state, - ] - logging.debug('Running command: "%s"', ' '.join(cmd)) + "dut-control", + "fw_wp_state:" + state, + ] + logging.debug('Running command: "%s"', " ".join(cmd)) subprocess.run(cmd).check_returncode() # pylint: disable=subprocess-run-check def build(test_name: str, board_name: str, compiler: str) -> None: """Build specified test for specified board.""" - cmd = ['make'] + cmd = ["make"] if compiler == CLANG: - cmd = cmd + ['CC=arm-none-eabi-clang'] + cmd = cmd + ["CC=arm-none-eabi-clang"] cmd = cmd + [ - 'BOARD=' + board_name, - 'test-' + test_name, - '-j', + "BOARD=" + board_name, + "test-" + test_name, + "-j", ] - logging.debug('Running command: "%s"', ' '.join(cmd)) + logging.debug('Running command: "%s"', " ".join(cmd)) subprocess.run(cmd).check_returncode() # pylint: disable=subprocess-run-check -def flash(image_path: str, board: str, flasher: str, remote_ip: str, - remote_port: int) -> bool: +def flash( + image_path: str, board: str, flasher: str, remote_ip: str, remote_port: int +) -> bool: """Flash specified test to specified board.""" - logging.info('Flashing test') + logging.info("Flashing test") cmd = [] if flasher == JTRACE: cmd.append(JTRACE_FLASH_SCRIPT) if remote_ip: - cmd.extend(['--remote', remote_ip + ':' + str(remote_port)]) + cmd.extend(["--remote", remote_ip + ":" + str(remote_port)]) elif flasher == SERVO_MICRO: cmd.append(SERVO_MICRO_FLASH_SCRIPT) else: logging.error('Unknown flasher: "%s"', flasher) return False - cmd.extend([ - '--board', board, - '--image', image_path, - ]) - logging.debug('Running command: "%s"', ' '.join(cmd)) + cmd.extend( + [ + "--board", + board, + "--image", + image_path, + ] + ) + logging.debug('Running command: "%s"', " ".join(cmd)) completed_process = subprocess.run(cmd) # pylint: disable=subprocess-run-check return completed_process.returncode == 0 def patch_image(test: TestConfig, image_path: str): """Replace RO part of the firmware with provided one.""" - with open(image_path, 'rb+') as f: + with open(image_path, "rb+") as f: image = bytearray(f.read()) ro = read_file_gsutil(test.ro_image) replace_ro(image, ro) @@ -478,8 +549,9 @@ def patch_image(test: TestConfig, image_path: str): f.truncate() -def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \ - Optional[bytes]: +def readline( + executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int +) -> Optional[bytes]: """Read a line with timeout.""" a = executor.submit(f.readline) try: @@ -488,8 +560,7 @@ def readline(executor: ThreadPoolExecutor, f: BinaryIO, timeout_secs: int) -> \ return None -def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> \ - List[bytes]: +def readlines_until_timeout(executor, f: BinaryIO, timeout_secs: int) -> List[bytes]: """Continuously read lines for timeout_secs.""" lines: List[bytes] = [] while True: @@ -519,19 +590,20 @@ def process_console_output_line(line: bytes, test: TestConfig): return None -def run_test(test: TestConfig, console: io.FileIO, - executor: ThreadPoolExecutor) -> bool: +def run_test( + test: TestConfig, console: io.FileIO, executor: ThreadPoolExecutor +) -> bool: """Run specified test.""" start = time.time() # Wait for boot to finish time.sleep(1) - console.write('\n'.encode()) + console.write("\n".encode()) if test.image_to_use == ImageType.RO: - console.write('reboot ro\n'.encode()) + console.write("reboot ro\n".encode()) time.sleep(1) - test_cmd = 'runtest ' + ' '.join(test.test_args) + '\n' + test_cmd = "runtest " + " ".join(test.test_args) + "\n" console.write(test_cmd.encode()) while True: @@ -540,7 +612,7 @@ def run_test(test: TestConfig, console: io.FileIO, if not line: now = time.time() if now - start > test.timeout_secs: - logging.debug('Test timed out') + logging.debug("Test timed out") return False continue @@ -569,15 +641,18 @@ def run_test(test: TestConfig, console: io.FileIO, def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]: """Get a list of tests to run.""" - if test_args == 'all': + if test_args == "all": return AllTests.get(config) test_list = [] for t in test_args: - logging.debug('test: %s', t) + logging.debug("test: %s", t) test_regex = re.compile(t) - tests = [test for test in AllTests.get(config) - if test_regex.fullmatch(test.config_name)] + tests = [ + test + for test in AllTests.get(config) + if test_regex.fullmatch(test.config_name) + ] if not tests: logging.error('Unable to find test config for "%s"', t) sys.exit(1) @@ -588,7 +663,7 @@ def get_test_list(config: BoardConfig, test_args) -> List[TestConfig]: def parse_remote_arg(remote: str) -> str: if not remote: - return '' + return "" try: ip = socket.gethostbyname(remote) @@ -601,67 +676,69 @@ def parse_remote_arg(remote: str) -> str: def main(): parser = argparse.ArgumentParser() - default_board = 'bloonchipper' - parser.add_argument( - '--board', '-b', - help='Board (default: ' + default_board + ')', - default=default_board) - - default_tests = 'all' + default_board = "bloonchipper" parser.add_argument( - '--tests', '-t', - nargs='+', - help='Tests (default: ' + default_tests + ')', - default=default_tests) + "--board", + "-b", + help="Board (default: " + default_board + ")", + default=default_board, + ) - log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] + default_tests = "all" parser.add_argument( - '--log_level', '-l', - choices=log_level_choices, - default='DEBUG' + "--tests", + "-t", + nargs="+", + help="Tests (default: " + default_tests + ")", + default=default_tests, ) + log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"] + parser.add_argument("--log_level", "-l", choices=log_level_choices, default="DEBUG") + flasher_choices = [SERVO_MICRO, JTRACE] - parser.add_argument( - '--flasher', '-f', - choices=flasher_choices, - default=JTRACE - ) + parser.add_argument("--flasher", "-f", choices=flasher_choices, default=JTRACE) compiler_options = [GCC, CLANG] - parser.add_argument('--compiler', '-c', - choices=compiler_options, - default=GCC) + parser.add_argument("--compiler", "-c", choices=compiler_options, default=GCC) # This might be expanded to serve as a "remote" for flash_ec also, so # we will leave it generic. parser.add_argument( - '--remote', '-n', - help='The remote host connected to one or both of: J-Link and Servo.', + "--remote", + "-n", + help="The remote host connected to one or both of: J-Link and Servo.", ) - parser.add_argument('--jlink_port', '-j', - type=int, - help='The port to use when connecting to JLink.') - parser.add_argument('--console_port', '-p', - type=int, - help='The port connected to the FPMCU console.') + parser.add_argument( + "--jlink_port", "-j", type=int, help="The port to use when connecting to JLink." + ) + parser.add_argument( + "--console_port", + "-p", + type=int, + help="The port connected to the FPMCU console.", + ) args = parser.parse_args() logging.basicConfig(level=args.log_level) if args.jlink_port and not args.flasher == JTRACE: - logging.error('jlink_port specified, but flasher is not set to J-Link.') + logging.error("jlink_port specified, but flasher is not set to J-Link.") sys.exit(1) if args.remote and not (args.jlink_port or args.console_port): - logging.error('jlink_port or console_port must be specified when using ' - 'the remote option.') + logging.error( + "jlink_port or console_port must be specified when using " + "the remote option." + ) sys.exit(1) if (args.jlink_port or args.console_port) and not args.remote: - logging.error('The remote option must be specified when using the ' - 'jlink_port or console_port options.') + logging.error( + "The remote option must be specified when using the " + "jlink_port or console_port options." + ) sys.exit(1) if args.board not in BOARD_CONFIGS: @@ -675,9 +752,7 @@ def main(): e = ThreadPoolExecutor(max_workers=1) test_list = get_test_list(board_config, args.tests) - logging.debug( - 'Running tests: %s', [ - test.config_name for test in test_list]) + logging.debug("Running tests: %s", [test.config_name for test in test_list]) for test in test_list: build_board = args.board @@ -689,15 +764,17 @@ def main(): # build test binary build(test.test_name, build_board, args.compiler) - image_path = os.path.join(EC_DIR, 'build', build_board, test.test_name, - test.test_name + '.bin') + image_path = os.path.join( + EC_DIR, "build", build_board, test.test_name, test.test_name + ".bin" + ) if test.ro_image is not None: try: patch_image(test, image_path) except Exception as exception: - logging.warning('An exception occurred while patching ' - 'image: %s', exception) + logging.warning( + "An exception occurred while patching " "image: %s", exception + ) test.passed = False continue @@ -706,16 +783,16 @@ def main(): # flash_write_protect test is run; works after second attempt. flash_succeeded = False for i in range(0, test.num_flash_attempts): - logging.debug('Flash attempt %d', i + 1) - if flash(image_path, args.board, args.flasher, remote_ip, - args.jlink_port): + logging.debug("Flash attempt %d", i + 1) + if flash(image_path, args.board, args.flasher, remote_ip, args.jlink_port): flash_succeeded = True break time.sleep(1) if not flash_succeeded: - logging.debug('Flashing failed after max attempts: %d', - test.num_flash_attempts) + logging.debug( + "Flashing failed after max attempts: %d", test.num_flash_attempts + ) test.passed = False continue @@ -733,11 +810,11 @@ def main(): if remote_ip and args.console_port: s = socket.socket(socket.AF_INET, socket.SOCK_STREAM) s.connect((remote_ip, args.console_port)) - console = stack.enter_context( - s.makefile(mode='rwb', buffering=0)) + console = stack.enter_context(s.makefile(mode="rwb", buffering=0)) else: console = stack.enter_context( - open(get_console(board_config), 'wb+', buffering=0)) + open(get_console(board_config), "wb+", buffering=0) + ) test.passed = run_test(test, console, executor=e) @@ -745,11 +822,11 @@ def main(): exit_code = 0 for test in test_list: # print results - print('Test "' + test.config_name + '": ', end='') + print('Test "' + test.config_name + '": ', end="") if test.passed: - print(colorama.Fore.GREEN + 'PASSED') + print(colorama.Fore.GREEN + "PASSED") else: - print(colorama.Fore.RED + 'FAILED') + print(colorama.Fore.RED + "FAILED") exit_code = 1 print(colorama.Style.RESET_ALL) @@ -758,5 +835,5 @@ def main(): sys.exit(exit_code) -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main()) diff --git a/test/timer_calib.py b/test/timer_calib.py index 2a625d80c7..c7ac9fc23b 100644 --- a/test/timer_calib.py +++ b/test/timer_calib.py @@ -7,48 +7,52 @@ import time -def one_pass(helper): - helper.wait_output("=== Timer calibration ===") - res = helper.wait_output("back-to-back get_time : (?P[0-9]+) us", - use_re=True)["lat"] - minlat = int(res) - helper.trace("get_time latency %d us\n" % minlat) - - helper.wait_output("sleep 1s") - t0 = time.time() - second = helper.wait_output("done. delay = (?P[0-9]+) us", - use_re=True)["second"] - t1 = time.time() - secondreal = t1 - t0 - secondlat = int(second) - 1000000 - helper.trace("1s timer latency %d us / real time %f s\n" % (secondlat, - secondreal)) - - us = {} - for pow2 in range(7): - delay = 1 << (7-pow2) - us[delay] = helper.wait_output("%d us => (?P[0-9]+) us" % delay, - use_re=True)["us"] - helper.wait_output("Done.") - - return minlat, secondlat, secondreal +def one_pass(helper): + helper.wait_output("=== Timer calibration ===") + res = helper.wait_output("back-to-back get_time : (?P[0-9]+) us", use_re=True)[ + "lat" + ] + minlat = int(res) + helper.trace("get_time latency %d us\n" % minlat) + + helper.wait_output("sleep 1s") + t0 = time.time() + second = helper.wait_output("done. delay = (?P[0-9]+) us", use_re=True)[ + "second" + ] + t1 = time.time() + secondreal = t1 - t0 + secondlat = int(second) - 1000000 + helper.trace("1s timer latency %d us / real time %f s\n" % (secondlat, secondreal)) + + us = {} + for pow2 in range(7): + delay = 1 << (7 - pow2) + us[delay] = helper.wait_output( + "%d us => (?P[0-9]+) us" % delay, use_re=True + )["us"] + helper.wait_output("Done.") + + return minlat, secondlat, secondreal def test(helper): - one_pass(helper) + one_pass(helper) - helper.ec_command("reboot") - helper.wait_output("--- UART initialized") + helper.ec_command("reboot") + helper.wait_output("--- UART initialized") - # get the timing results on the second pass - # to avoid binary translation overhead - minlat, secondlat, secondreal = one_pass(helper) + # get the timing results on the second pass + # to avoid binary translation overhead + minlat, secondlat, secondreal = one_pass(helper) - # check that the timings somewhat make sense - if minlat > 220 or secondlat > 500 or abs(secondreal-1.0) > 0.200: - helper.fail("imprecise timings " + - "(get_time %d us sleep %d us / real time %.3f s)" % - (minlat, secondlat, secondreal)) + # check that the timings somewhat make sense + if minlat > 220 or secondlat > 500 or abs(secondreal - 1.0) > 0.200: + helper.fail( + "imprecise timings " + + "(get_time %d us sleep %d us / real time %.3f s)" + % (minlat, secondlat, secondreal) + ) - return True # PASS ! + return True # PASS ! diff --git a/test/timer_jump.py b/test/timer_jump.py index f506a69fcf..2801c3b3fa 100644 --- a/test/timer_jump.py +++ b/test/timer_jump.py @@ -10,22 +10,25 @@ import time DELAY = 5 ERROR_MARGIN = 0.5 + def test(helper): - helper.wait_output("idle task started") - helper.ec_command("sysinfo") - copy = helper.wait_output("Copy:\s+(?P\S+)", use_re=True)["c"] - if copy != "RO": - helper.ec_command("sysjump ro") - helper.wait_output("idle task started") - helper.ec_command("gettime") - ec_start_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P[\d\.]+) s", - use_re=True)["t"] - time.sleep(DELAY) - helper.ec_command("sysjump a") - helper.wait_output("idle task started") - helper.ec_command("gettime") - ec_end_time = helper.wait_output("Time: 0x[0-9a-f]* = (?P[\d\.]+) s", - use_re=True)["t"] + helper.wait_output("idle task started") + helper.ec_command("sysinfo") + copy = helper.wait_output("Copy:\s+(?P\S+)", use_re=True)["c"] + if copy != "RO": + helper.ec_command("sysjump ro") + helper.wait_output("idle task started") + helper.ec_command("gettime") + ec_start_time = helper.wait_output( + "Time: 0x[0-9a-f]* = (?P[\d\.]+) s", use_re=True + )["t"] + time.sleep(DELAY) + helper.ec_command("sysjump a") + helper.wait_output("idle task started") + helper.ec_command("gettime") + ec_end_time = helper.wait_output( + "Time: 0x[0-9a-f]* = (?P[\d\.]+) s", use_re=True + )["t"] - time_diff = float(ec_end_time) - float(ec_start_time) - return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN + time_diff = float(ec_end_time) - float(ec_start_time) + return time_diff >= DELAY and time_diff <= DELAY + ERROR_MARGIN diff --git a/util/build_with_clang.py b/util/build_with_clang.py index a38ade2cb8..98da942152 100755 --- a/util/build_with_clang.py +++ b/util/build_with_clang.py @@ -12,15 +12,14 @@ import multiprocessing import os import subprocess import sys - from concurrent.futures import ThreadPoolExecutor # Add to this list as compilation errors are fixed for boards. BOARDS_THAT_COMPILE_SUCCESSFULLY_WITH_CLANG = [ - 'dartmonkey', - 'bloonchipper', - 'nucleo-f412zg', - 'nucleo-h743zi', + "dartmonkey", + "bloonchipper", + "nucleo-f412zg", + "nucleo-h743zi", ] @@ -29,35 +28,29 @@ def build(board_name: str) -> None: logging.debug('Building board: "%s"', board_name) cmd = [ - 'make', - 'BOARD=' + board_name, - '-j', + "make", + "BOARD=" + board_name, + "-j", ] - logging.debug('Running command: "%s"', ' '.join(cmd)) - subprocess.run(cmd, env=dict(os.environ, CC='clang'), check=True) + logging.debug('Running command: "%s"', " ".join(cmd)) + subprocess.run(cmd, env=dict(os.environ, CC="clang"), check=True) def main() -> int: parser = argparse.ArgumentParser() - log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] - parser.add_argument( - '--log_level', '-l', - choices=log_level_choices, - default='DEBUG' - ) + log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"] + parser.add_argument("--log_level", "-l", choices=log_level_choices, default="DEBUG") parser.add_argument( - '--num_threads', '-j', - type=int, - default=multiprocessing.cpu_count() + "--num_threads", "-j", type=int, default=multiprocessing.cpu_count() ) args = parser.parse_args() logging.basicConfig(level=args.log_level) - logging.debug('Building with %d threads', args.num_threads) + logging.debug("Building with %d threads", args.num_threads) failed_boards = [] with ThreadPoolExecutor(max_workers=args.num_threads) as executor: @@ -73,13 +66,14 @@ def main() -> int: failed_boards.append(board) if len(failed_boards) > 0: - logging.error('The following boards failed to compile:\n%s', - '\n'.join(failed_boards)) + logging.error( + "The following boards failed to compile:\n%s", "\n".join(failed_boards) + ) return 1 - logging.info('All boards compiled successfully!') + logging.info("All boards compiled successfully!") return 0 -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main()) diff --git a/util/chargen b/util/chargen index 9ba14d3d6a..a1f7947a14 100644 --- a/util/chargen +++ b/util/chargen @@ -5,6 +5,7 @@ import sys + def chargen(modulo, max_chars): """Generate a stream of characters on the console. @@ -18,7 +19,7 @@ def chargen(modulo, max_chars): zero, if zero - print indefinitely """ - base = '0' + base = "0" c = base counter = 0 while True: @@ -26,25 +27,25 @@ def chargen(modulo, max_chars): counter = counter + 1 if (max_chars != 0) and (counter == max_chars): - sys.stdout.write('\n') + sys.stdout.write("\n") return if modulo and ((counter % modulo) == 0): c = base continue - if c == 'z': + if c == "z": c = base - elif c == 'Z': - c = 'a' - elif c == '9': - c = 'A' + elif c == "Z": + c = "a" + elif c == "9": + c = "A" else: - c = '%c' % (ord(c) + 1) + c = "%c" % (ord(c) + 1) def main(args): - '''Process command line arguments and invoke chargen if args are valid''' + """Process command line arguments and invoke chargen if args are valid""" modulo = 0 max_chars = 0 @@ -55,8 +56,7 @@ def main(args): if len(args) > 1: max_chars = int(args[1]) except ValueError: - sys.stderr.write('usage %s:' - "['seq_length' ['max_chars']]\n") + sys.stderr.write("usage %s:" "['seq_length' ['max_chars']]\n") sys.exit(1) try: @@ -64,6 +64,7 @@ def main(args): except KeyboardInterrupt: print() -if __name__ == '__main__': + +if __name__ == "__main__": main(sys.argv[1:]) sys.exit(0) diff --git a/util/config_option_check.py b/util/config_option_check.py index 8bd8ecb1f0..0b05b64091 100755 --- a/util/config_option_check.py +++ b/util/config_option_check.py @@ -13,6 +13,7 @@ Script to ensure that all configuration options for the Chrome EC are defined in config.h. """ from __future__ import print_function + import enum import os import re @@ -21,368 +22,392 @@ import sys class Line(object): - """Class for each changed line in diff output. + """Class for each changed line in diff output. - Attributes: - line_num: The integer line number that this line appears in the file. - string: The literal string of this line. - line_type: '+' or '-' indicating if this line was an addition or - deletion. - """ + Attributes: + line_num: The integer line number that this line appears in the file. + string: The literal string of this line. + line_type: '+' or '-' indicating if this line was an addition or + deletion. + """ - def __init__(self, line_num, string, line_type): - """Inits Line with the line number and the actual string.""" - self.line_num = line_num - self.string = string - self.line_type = line_type + def __init__(self, line_num, string, line_type): + """Inits Line with the line number and the actual string.""" + self.line_num = line_num + self.string = string + self.line_type = line_type class Hunk(object): - """Class for a git diff hunk. + """Class for a git diff hunk. - Attributes: - filename: The name of the file that this hunk belongs to. - lines: A list of Line objects that are a part of this hunk. - """ + Attributes: + filename: The name of the file that this hunk belongs to. + lines: A list of Line objects that are a part of this hunk. + """ - def __init__(self, filename, lines): - """Inits Hunk with the filename and the list of lines of the hunk.""" - self.filename = filename - self.lines = lines + def __init__(self, filename, lines): + """Inits Hunk with the filename and the list of lines of the hunk.""" + self.filename = filename + self.lines = lines # Master file which is supposed to include all CONFIG_xxxx descriptions. -CONFIG_FILE = 'include/config.h' +CONFIG_FILE = "include/config.h" # Specific files which the checker should ignore. -ALLOWLIST = [CONFIG_FILE, 'util/config_option_check.py'] +ALLOWLIST = [CONFIG_FILE, "util/config_option_check.py"] # Specific directories which the checker should ignore. -ALLOW_PATTERN = re.compile('zephyr/.*') +ALLOW_PATTERN = re.compile("zephyr/.*") # Specific CONFIG_* flags which the checker should ignore. -ALLOWLIST_CONFIGS = ['CONFIG_ZTEST'] +ALLOWLIST_CONFIGS = ["CONFIG_ZTEST"] + def obtain_current_config_options(): - """Obtains current config options from include/config.h. - - Scans through the main config file defined in CONFIG_FILE for all CONFIG_* - options. - - Returns: - config_options: A list of all the config options in the main CONFIG_FILE. - """ - - config_options = [] - config_option_re = re.compile(r'^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)') - with open(CONFIG_FILE, 'r') as config_file: - for line in config_file: - result = config_option_re.search(line) - if not result: - continue - word = result.groups()[1] - if word not in config_options: - config_options.append(word) - return config_options + """Obtains current config options from include/config.h. + + Scans through the main config file defined in CONFIG_FILE for all CONFIG_* + options. + + Returns: + config_options: A list of all the config options in the main CONFIG_FILE. + """ + + config_options = [] + config_option_re = re.compile(r"^#(define|undef)\s+(CONFIG_[A-Z0-9_]+)") + with open(CONFIG_FILE, "r") as config_file: + for line in config_file: + result = config_option_re.search(line) + if not result: + continue + word = result.groups()[1] + if word not in config_options: + config_options.append(word) + return config_options + def obtain_config_options_in_use(): - """Obtains all the config options in use in the repo. - - Scans through the entire repo looking for all CONFIG_* options actively used. - - Returns: - options_in_use: A set of all the config options in use in the repo. - """ - file_list = [] - cwd = os.getcwd() - config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)') - config_debug_option_re = re.compile(r'\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)') - options_in_use = set() - for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True): - # Ignore the build and private directories (taken from .gitignore) - if 'build' in dirnames: - dirnames.remove('build') - if 'private' in dirnames: - dirnames.remove('private') - for f in filenames: - # Ignore hidden files. - if f.startswith('.'): - continue - # Only consider C source, assembler, and Make-style files. - if (os.path.splitext(f)[1] in ('.c', '.h', '.inc', '.S', '.mk') or - 'Makefile' in f): - file_list.append(os.path.join(dirpath, f)) - - # Search through each file and build a set of the CONFIG_* options being - # used. - - for f in file_list: - if CONFIG_FILE in f: - continue - with open(f, 'r') as cur_file: - for line in cur_file: - match = config_option_re.findall(line) - if match: - for option in match: - if not in_comment(f, line, option): - if option not in options_in_use: - options_in_use.add(option) - - # Since debug options can be turned on at any time, assume that they are - # always in use in case any aren't being used. - - with open(CONFIG_FILE, 'r') as config_file: - for line in config_file: - match = config_debug_option_re.findall(line) - if match: - for option in match: - if not in_comment(CONFIG_FILE, line, option): - if option not in options_in_use: - options_in_use.add(option) - - return options_in_use + """Obtains all the config options in use in the repo. + + Scans through the entire repo looking for all CONFIG_* options actively used. + + Returns: + options_in_use: A set of all the config options in use in the repo. + """ + file_list = [] + cwd = os.getcwd() + config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)") + config_debug_option_re = re.compile(r"\b(CONFIG_DEBUG_[a-zA-Z0-9_]+)") + options_in_use = set() + for (dirpath, dirnames, filenames) in os.walk(cwd, topdown=True): + # Ignore the build and private directories (taken from .gitignore) + if "build" in dirnames: + dirnames.remove("build") + if "private" in dirnames: + dirnames.remove("private") + for f in filenames: + # Ignore hidden files. + if f.startswith("."): + continue + # Only consider C source, assembler, and Make-style files. + if ( + os.path.splitext(f)[1] in (".c", ".h", ".inc", ".S", ".mk") + or "Makefile" in f + ): + file_list.append(os.path.join(dirpath, f)) + + # Search through each file and build a set of the CONFIG_* options being + # used. + + for f in file_list: + if CONFIG_FILE in f: + continue + with open(f, "r") as cur_file: + for line in cur_file: + match = config_option_re.findall(line) + if match: + for option in match: + if not in_comment(f, line, option): + if option not in options_in_use: + options_in_use.add(option) + + # Since debug options can be turned on at any time, assume that they are + # always in use in case any aren't being used. + + with open(CONFIG_FILE, "r") as config_file: + for line in config_file: + match = config_debug_option_re.findall(line) + if match: + for option in match: + if not in_comment(CONFIG_FILE, line, option): + if option not in options_in_use: + options_in_use.add(option) + + return options_in_use + def print_missing_config_options(hunks, config_options): - """Searches thru all the changes in hunks for missing options and prints them. - - Args: - hunks: A list of Hunk objects which represent the hunks from the git - diff output. - config_options: A list of all the config options in the main CONFIG_FILE. - - Returns: - missing_config_option: A boolean indicating if any CONFIG_* options - are missing from the main CONFIG_FILE in this commit or if any CONFIG_* - options removed are no longer being used in the repo. - """ - missing_config_option = False - print_banner = True - deprecated_options = set() - # Determine longest CONFIG_* length to be used for formatting. - max_option_length = max(len(option) for option in config_options) - config_option_re = re.compile(r'\b(CONFIG_[a-zA-Z0-9_]+)') - - # Search for all CONFIG_* options in use in the repo. - options_in_use = obtain_config_options_in_use() - - # Check each hunk's line for a missing config option. - for h in hunks: - for l in h.lines: - # Check for the existence of a CONFIG_* in the line. - match = filter(lambda opt: opt in ALLOWLIST_CONFIGS, - config_option_re.findall(l.string)) - if not match: - continue - - # At this point, an option was found in the line. However, we need to - # verify that it is not within a comment. - violations = set() - - for option in match: - if not in_comment(h.filename, l.string, option): - # Since the CONFIG_* option is not within a comment, we've found a - # violation. We now need to determine if this line is a deletion or - # not. For deletions, we will need to verify if this CONFIG_* option - # is no longer being used in the entire repo. - - if l.line_type == '-': - if option not in options_in_use and option in config_options: - deprecated_options.add(option) - else: - violations.add(option) - - # Check to see if the CONFIG_* option is in the config file and print the - # violations. - for option in match: - if option not in config_options and option in violations: - # Print the banner once. - if print_banner: - print('The following config options were found to be missing ' - 'from %s.\n' - 'Please add new config options there along with ' - 'descriptions.\n\n' % CONFIG_FILE) - print_banner = False + """Searches thru all the changes in hunks for missing options and prints them. + + Args: + hunks: A list of Hunk objects which represent the hunks from the git + diff output. + config_options: A list of all the config options in the main CONFIG_FILE. + + Returns: + missing_config_option: A boolean indicating if any CONFIG_* options + are missing from the main CONFIG_FILE in this commit or if any CONFIG_* + options removed are no longer being used in the repo. + """ + missing_config_option = False + print_banner = True + deprecated_options = set() + # Determine longest CONFIG_* length to be used for formatting. + max_option_length = max(len(option) for option in config_options) + config_option_re = re.compile(r"\b(CONFIG_[a-zA-Z0-9_]+)") + + # Search for all CONFIG_* options in use in the repo. + options_in_use = obtain_config_options_in_use() + + # Check each hunk's line for a missing config option. + for h in hunks: + for l in h.lines: + # Check for the existence of a CONFIG_* in the line. + match = filter( + lambda opt: opt in ALLOWLIST_CONFIGS, config_option_re.findall(l.string) + ) + if not match: + continue + + # At this point, an option was found in the line. However, we need to + # verify that it is not within a comment. + violations = set() + + for option in match: + if not in_comment(h.filename, l.string, option): + # Since the CONFIG_* option is not within a comment, we've found a + # violation. We now need to determine if this line is a deletion or + # not. For deletions, we will need to verify if this CONFIG_* option + # is no longer being used in the entire repo. + + if l.line_type == "-": + if option not in options_in_use and option in config_options: + deprecated_options.add(option) + else: + violations.add(option) + + # Check to see if the CONFIG_* option is in the config file and print the + # violations. + for option in match: + if option not in config_options and option in violations: + # Print the banner once. + if print_banner: + print( + "The following config options were found to be missing " + "from %s.\n" + "Please add new config options there along with " + "descriptions.\n\n" % CONFIG_FILE + ) + print_banner = False + missing_config_option = True + # Print the misssing config option. + print( + "> %-*s %s:%s" + % (max_option_length, option, h.filename, l.line_num) + ) + + if deprecated_options: + print( + "\n\nThe following config options are being removed and also appear" + " to be the last uses\nof that option. Please remove these " + "options from %s.\n\n" % CONFIG_FILE + ) + for option in deprecated_options: + print("> %s" % option) missing_config_option = True - # Print the misssing config option. - print('> %-*s %s:%s' % (max_option_length, option, - h.filename, - l.line_num)) - if deprecated_options: - print('\n\nThe following config options are being removed and also appear' - ' to be the last uses\nof that option. Please remove these ' - 'options from %s.\n\n' % CONFIG_FILE) - for option in deprecated_options: - print('> %s' % option) - missing_config_option = True + return missing_config_option - return missing_config_option def in_comment(filename, line, substr): - """Checks if given substring appears in a comment. - - Args: - filename: The filename where this line is from. This is used to determine - what kind of comments to look for. - line: String of line to search in. - substr: Substring to search for in the line. - - Returns: - is_in_comment: Boolean indicating if substr was in a comment. - """ - - c_style_ext = ('.c', '.h', '.inc', '.S') - make_style_ext = ('.mk') - is_in_comment = False - - extension = os.path.splitext(filename)[1] - substr_idx = line.find(substr) - - # Different files have different comment syntax; Handle appropriately. - if extension in c_style_ext: - beg_comment_idx = line.find('/*') - end_comment_idx = line.find('*/') - if end_comment_idx == -1: - end_comment_idx = len(line) - - if beg_comment_idx == -1: - # Check to see if this line is from a multi-line comment. - if line.lstrip().startswith('* '): - # It _seems_ like it is. - is_in_comment = True - else: - # Check to see if its actually inside the comment. - if beg_comment_idx < substr_idx < end_comment_idx: - is_in_comment = True - elif extension in make_style_ext or 'Makefile' in filename: - beg_comment_idx = line.find('#') - # Ignore everything to the right of the hash. - if beg_comment_idx < substr_idx and beg_comment_idx != -1: - is_in_comment = True - return is_in_comment + """Checks if given substring appears in a comment. + + Args: + filename: The filename where this line is from. This is used to determine + what kind of comments to look for. + line: String of line to search in. + substr: Substring to search for in the line. + + Returns: + is_in_comment: Boolean indicating if substr was in a comment. + """ + + c_style_ext = (".c", ".h", ".inc", ".S") + make_style_ext = ".mk" + is_in_comment = False + + extension = os.path.splitext(filename)[1] + substr_idx = line.find(substr) + + # Different files have different comment syntax; Handle appropriately. + if extension in c_style_ext: + beg_comment_idx = line.find("/*") + end_comment_idx = line.find("*/") + if end_comment_idx == -1: + end_comment_idx = len(line) + + if beg_comment_idx == -1: + # Check to see if this line is from a multi-line comment. + if line.lstrip().startswith("* "): + # It _seems_ like it is. + is_in_comment = True + else: + # Check to see if its actually inside the comment. + if beg_comment_idx < substr_idx < end_comment_idx: + is_in_comment = True + elif extension in make_style_ext or "Makefile" in filename: + beg_comment_idx = line.find("#") + # Ignore everything to the right of the hash. + if beg_comment_idx < substr_idx and beg_comment_idx != -1: + is_in_comment = True + return is_in_comment + def get_hunks(): - """Gets the hunks of the most recent commit. - - States: - new_file: Searching for a new file in the git diff. - filename_search: Searching for the filename of this hunk. - hunk: Searching for the beginning of a new hunk. - lines: Counting line numbers and searching for changes. - - Returns: - hunks: A list of Hunk objects which represent the hunks in the git diff - output. - """ - - diff = [] - hunks = [] - hunk_lines = [] - line = '' - filename = '' - i = 0 - line_num = 0 - - # Regex patterns - new_file_re = re.compile(r'^diff --git') - filename_re = re.compile(r'^[+]{3} (.*)') - hunk_line_num_re = re.compile(r'^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*') - line_re = re.compile(r'^([+| |-])(.*)') - - # Get the diff output. - proc = subprocess.run(['git', 'diff', '--cached', '-GCONFIG_*', '--no-prefix', - '--no-ext-diff', 'HEAD~1'], - stdout=subprocess.PIPE, - encoding='utf-8', - check=True) - diff = proc.stdout.splitlines() - if not diff: - return [] - line = diff[0] - - state = enum.Enum('state', 'NEW_FILE FILENAME_SEARCH HUNK LINES') - current_state = state.NEW_FILE - - while True: - # Search for the beginning of a new file. - if current_state is state.NEW_FILE: - match = new_file_re.search(line) - if match: - current_state = state.FILENAME_SEARCH - - # Search the diff output for a file name. - elif current_state is state.FILENAME_SEARCH: - # Search for a file name. - match = filename_re.search(line) - if match: - filename = match.groups(1)[0] - if filename in ALLOWLIST or ALLOW_PATTERN.match(filename): - # Skip the file if it's allowlisted. - current_state = state.NEW_FILE - else: - current_state = state.HUNK - - # Search for a hunk. Each hunk starts with a line describing the line - # numbers in the file. - elif current_state is state.HUNK: - hunk_lines = [] - match = hunk_line_num_re.search(line) - if match: - # Extract the line number offset. - line_num = int(match.groups(1)[0]) - current_state = state.LINES - - # Start looking for changes. - elif current_state is state.LINES: - # Check if state needs updating. - new_hunk = hunk_line_num_re.search(line) - new_file = new_file_re.search(line) - if new_hunk: - current_state = state.HUNK - hunks.append(Hunk(filename, hunk_lines)) - continue - elif new_file: - current_state = state.NEW_FILE - hunks.append(Hunk(filename, hunk_lines)) - continue - - match = line_re.search(line) - if match: - line_type = match.groups(1)[0] - # We only care about modifications. - if line_type != ' ': - hunk_lines.append(Line(line_num, match.groups(2)[1], line_type)) - # Deletions don't count towards the line numbers. - if line_type != '-': - line_num += 1 - - # Advance to the next line - try: - i += 1 - line = diff[i] - except IndexError: - # We've reached the end of the diff. Return what we have. - if hunk_lines: - hunks.append(Hunk(filename, hunk_lines)) - return hunks + """Gets the hunks of the most recent commit. + + States: + new_file: Searching for a new file in the git diff. + filename_search: Searching for the filename of this hunk. + hunk: Searching for the beginning of a new hunk. + lines: Counting line numbers and searching for changes. + + Returns: + hunks: A list of Hunk objects which represent the hunks in the git diff + output. + """ + + diff = [] + hunks = [] + hunk_lines = [] + line = "" + filename = "" + i = 0 + line_num = 0 + + # Regex patterns + new_file_re = re.compile(r"^diff --git") + filename_re = re.compile(r"^[+]{3} (.*)") + hunk_line_num_re = re.compile(r"^@@ -[0-9]+,[0-9]+ \+([0-9]+),[0-9]+ @@.*") + line_re = re.compile(r"^([+| |-])(.*)") + + # Get the diff output. + proc = subprocess.run( + [ + "git", + "diff", + "--cached", + "-GCONFIG_*", + "--no-prefix", + "--no-ext-diff", + "HEAD~1", + ], + stdout=subprocess.PIPE, + encoding="utf-8", + check=True, + ) + diff = proc.stdout.splitlines() + if not diff: + return [] + line = diff[0] + + state = enum.Enum("state", "NEW_FILE FILENAME_SEARCH HUNK LINES") + current_state = state.NEW_FILE + + while True: + # Search for the beginning of a new file. + if current_state is state.NEW_FILE: + match = new_file_re.search(line) + if match: + current_state = state.FILENAME_SEARCH + + # Search the diff output for a file name. + elif current_state is state.FILENAME_SEARCH: + # Search for a file name. + match = filename_re.search(line) + if match: + filename = match.groups(1)[0] + if filename in ALLOWLIST or ALLOW_PATTERN.match(filename): + # Skip the file if it's allowlisted. + current_state = state.NEW_FILE + else: + current_state = state.HUNK + + # Search for a hunk. Each hunk starts with a line describing the line + # numbers in the file. + elif current_state is state.HUNK: + hunk_lines = [] + match = hunk_line_num_re.search(line) + if match: + # Extract the line number offset. + line_num = int(match.groups(1)[0]) + current_state = state.LINES + + # Start looking for changes. + elif current_state is state.LINES: + # Check if state needs updating. + new_hunk = hunk_line_num_re.search(line) + new_file = new_file_re.search(line) + if new_hunk: + current_state = state.HUNK + hunks.append(Hunk(filename, hunk_lines)) + continue + elif new_file: + current_state = state.NEW_FILE + hunks.append(Hunk(filename, hunk_lines)) + continue + + match = line_re.search(line) + if match: + line_type = match.groups(1)[0] + # We only care about modifications. + if line_type != " ": + hunk_lines.append(Line(line_num, match.groups(2)[1], line_type)) + # Deletions don't count towards the line numbers. + if line_type != "-": + line_num += 1 + + # Advance to the next line + try: + i += 1 + line = diff[i] + except IndexError: + # We've reached the end of the diff. Return what we have. + if hunk_lines: + hunks.append(Hunk(filename, hunk_lines)) + return hunks + def main(): - """Searches through committed changes for missing config options. - - Checks through committed changes for CONFIG_* options. Then checks to make - sure that all CONFIG_* options used are defined in include/config.h. Finally, - reports any missing config options. - """ - # Obtain the hunks of the commit to search through. - hunks = get_hunks() - # Obtain config options from include/config.h. - config_options = obtain_current_config_options() - # Find any missing config options from the hunks and print them. - missing_opts = print_missing_config_options(hunks, config_options) - - if missing_opts: - print('\nIt may also be possible that you have a typo.') - sys.exit(1) - -if __name__ == '__main__': - main() + """Searches through committed changes for missing config options. + + Checks through committed changes for CONFIG_* options. Then checks to make + sure that all CONFIG_* options used are defined in include/config.h. Finally, + reports any missing config options. + """ + # Obtain the hunks of the commit to search through. + hunks = get_hunks() + # Obtain config options from include/config.h. + config_options = obtain_current_config_options() + # Find any missing config options from the hunks and print them. + missing_opts = print_missing_config_options(hunks, config_options) + + if missing_opts: + print("\nIt may also be possible that you have a typo.") + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/util/ec3po/console.py b/util/ec3po/console.py index e71216e3f2..33fa5a6775 100755 --- a/util/ec3po/console.py +++ b/util/ec3po/console.py @@ -17,7 +17,6 @@ from __future__ import print_function import argparse import binascii import ctypes -from datetime import datetime import logging import os import pty @@ -26,26 +25,25 @@ import select import stat import sys import traceback +from datetime import datetime import six +from ec3po import interpreter, threadproc_shim -from ec3po import interpreter -from ec3po import threadproc_shim - - -PROMPT = b'> ' +PROMPT = b"> " CONSOLE_INPUT_LINE_SIZE = 80 # Taken from the CONFIG_* with the same name. CONSOLE_MAX_READ = 100 # Max bytes to read at a time from the user. LOOK_BUFFER_SIZE = 256 # Size of search window when looking for the enhanced EC - # image string. +# image string. # In console_init(), the EC will print a string saying that the EC console is # enabled. Enhanced images will print a slightly different string. These # regular expressions are used to determine at reboot whether the EC image is # enhanced or not. -ENHANCED_IMAGE_RE = re.compile(br'Enhanced Console is enabled ' - br'\(v([0-9]+\.[0-9]+\.[0-9]+)\)') -NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ') +ENHANCED_IMAGE_RE = re.compile( + rb"Enhanced Console is enabled " rb"\(v([0-9]+\.[0-9]+\.[0-9]+)\)" +) +NON_ENHANCED_IMAGE_RE = re.compile(rb"Console is enabled; ") # The timeouts are really only useful for enhanced EC images, but otherwise just # serve as a delay for non-enhanced EC images. Therefore, we can keep this @@ -54,1118 +52,1173 @@ NON_ENHANCED_IMAGE_RE = re.compile(br'Console is enabled; ') # EC image, we can increase the timeout for stability just in case it takes a # bit longer to receive an ACK for some reason. NON_ENHANCED_EC_INTERROGATION_TIMEOUT = 0.3 # Maximum number of seconds to wait - # for a response to an - # interrogation of a non-enhanced - # EC image. +# for a response to an +# interrogation of a non-enhanced +# EC image. ENHANCED_EC_INTERROGATION_TIMEOUT = 1.0 # Maximum number of seconds to wait for - # a response to an interrogation of an - # enhanced EC image. +# a response to an interrogation of an +# enhanced EC image. # List of modes which control when interrogations are performed with the EC. -INTERROGATION_MODES = [b'never', b'always', b'auto'] +INTERROGATION_MODES = [b"never", b"always", b"auto"] # Format for printing host timestamp -HOST_STRFTIME="%y-%m-%d %H:%M:%S.%f" +HOST_STRFTIME = "%y-%m-%d %H:%M:%S.%f" class EscState(object): - """Class which contains an enumeration for states of ESC sequences.""" - ESC_START = 1 - ESC_BRACKET = 2 - ESC_BRACKET_1 = 3 - ESC_BRACKET_3 = 4 - ESC_BRACKET_8 = 5 - + """Class which contains an enumeration for states of ESC sequences.""" -class ControlKey(object): - """Class which contains codes for various control keys.""" - BACKSPACE = 0x08 - CTRL_A = 0x01 - CTRL_B = 0x02 - CTRL_D = 0x04 - CTRL_E = 0x05 - CTRL_F = 0x06 - CTRL_K = 0x0b - CTRL_N = 0xe - CTRL_P = 0x10 - CARRIAGE_RETURN = 0x0d - ESC = 0x1b + ESC_START = 1 + ESC_BRACKET = 2 + ESC_BRACKET_1 = 3 + ESC_BRACKET_3 = 4 + ESC_BRACKET_8 = 5 -class Console(object): - """Class which provides the console interface between the EC and the user. - - This class essentially represents the console interface between the user and - the EC. It handles all of the console editing behaviour - - Attributes: - logger: A logger for this module. - controller_pty: File descriptor to the controller side of the PTY. Used for - driving output to the user and receiving user input. - user_pty: A string representing the PTY name of the served console. - cmd_pipe: A socket.socket or multiprocessing.Connection object which - represents the console side of the command pipe. This must be a - bidirectional pipe. Console commands and responses utilize this pipe. - dbg_pipe: A socket.socket or multiprocessing.Connection object which - represents the console's read-only side of the debug pipe. This must be a - unidirectional pipe attached to the intepreter. EC debug messages use - this pipe. - oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of - band management for the interactive console. - input_buffer: A string representing the current input command. - input_buffer_pos: An integer representing the current position in the buffer - to insert a char. - partial_cmd: A string representing the command entered on a line before - pressing the up arrow keys. - esc_state: An integer represeting the current state within an escape - sequence. - line_limit: An integer representing the maximum number of characters on a - line. - history: A list of strings containing the past entered console commands. - history_pos: An integer representing the current history buffer position. - This index is used to show previous commands. - prompt: A string representing the console prompt displayed to the user. - enhanced_ec: A boolean indicating if the EC image that we are currently - communicating with is enhanced or not. Enhanced EC images will support - packed commands and host commands over the UART. This defaults to False - until we perform some handshaking. - interrogation_timeout: A float representing the current maximum seconds to - wait for a response to an interrogation. - receiving_oobm_cmd: A boolean indicating whether or not the console is in - the middle of receiving an out of band command. - pending_oobm_cmd: A string containing the pending OOBM command. - interrogation_mode: A string containing the current mode of whether - interrogations are performed with the EC or not and how often. - raw_debug: Flag to indicate whether per interrupt data should be logged to - debug - output_line_log_buffer: buffer for lines coming from the EC to log to debug - """ - - def __init__(self, controller_pty, user_pty, interface_pty, cmd_pipe, dbg_pipe, - name=None): - """Initalises a Console object with the provided arguments. +class ControlKey(object): + """Class which contains codes for various control keys.""" - Args: - controller_pty: File descriptor to the controller side of the PTY. Used for - driving output to the user and receiving user input. - user_pty: A string representing the PTY name of the served console. - interface_pty: A string representing the PTY name of the served command - interface. - cmd_pipe: A socket.socket or multiprocessing.Connection object which - represents the console side of the command pipe. This must be a - bidirectional pipe. Console commands and responses utilize this pipe. - dbg_pipe: A socket.socket or multiprocessing.Connection object which - represents the console's read-only side of the debug pipe. This must be a - unidirectional pipe attached to the intepreter. EC debug messages use - this pipe. - name: the console source name - """ - # Create a unique logger based on the console name - console_prefix = ('%s - ' % name) if name else '' - logger = logging.getLogger('%sEC3PO.Console' % console_prefix) - self.logger = interpreter.LoggerAdapter(logger, {'pty': user_pty}) - self.controller_pty = controller_pty - self.user_pty = user_pty - self.interface_pty = interface_pty - self.cmd_pipe = cmd_pipe - self.dbg_pipe = dbg_pipe - self.oobm_queue = threadproc_shim.Queue() - self.input_buffer = b'' - self.input_buffer_pos = 0 - self.partial_cmd = b'' - self.esc_state = 0 - self.line_limit = CONSOLE_INPUT_LINE_SIZE - self.history = [] - self.history_pos = 0 - self.prompt = PROMPT - self.enhanced_ec = False - self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT - self.receiving_oobm_cmd = False - self.pending_oobm_cmd = b'' - self.interrogation_mode = b'auto' - self.timestamp_enabled = True - self.look_buffer = b'' - self.raw_debug = False - self.output_line_log_buffer = [] - - def __str__(self): - """Show internal state of Console object as a string.""" - string = [] - string.append('controller_pty: %s' % self.controller_pty) - string.append('user_pty: %s' % self.user_pty) - string.append('interface_pty: %s' % self.interface_pty) - string.append('cmd_pipe: %s' % self.cmd_pipe) - string.append('dbg_pipe: %s' % self.dbg_pipe) - string.append('oobm_queue: %s' % self.oobm_queue) - string.append('input_buffer: %s' % self.input_buffer) - string.append('input_buffer_pos: %d' % self.input_buffer_pos) - string.append('esc_state: %d' % self.esc_state) - string.append('line_limit: %d' % self.line_limit) - string.append('history: %r' % self.history) - string.append('history_pos: %d' % self.history_pos) - string.append('prompt: %r' % self.prompt) - string.append('partial_cmd: %r'% self.partial_cmd) - string.append('interrogation_mode: %r' % self.interrogation_mode) - string.append('look_buffer: %r' % self.look_buffer) - return '\n'.join(string) - - def LogConsoleOutput(self, data): - """Log to debug user MCU output to controller_pty when line is filled. - - The logging also suppresses the Cr50 spinner lines by removing characters - when it sees backspaces. + BACKSPACE = 0x08 + CTRL_A = 0x01 + CTRL_B = 0x02 + CTRL_D = 0x04 + CTRL_E = 0x05 + CTRL_F = 0x06 + CTRL_K = 0x0B + CTRL_N = 0xE + CTRL_P = 0x10 + CARRIAGE_RETURN = 0x0D + ESC = 0x1B - Args: - data: bytes - string received from MCU - """ - data = list(data) - # For compatibility with python2 and python3, standardize on the data - # being a list of integers. This requires one more transformation in py2 - if not isinstance(data[0], int): - data = [ord(c) for c in data] - - # This is a list of already filtered characters (or placeholders). - line = self.output_line_log_buffer - - # TODO(b/177480273): use raw strings here - symbols = { - ord(b'\n'): u'\\n', - ord(b'\r'): u'\\r', - ord(b'\t'): u'\\t' - } - # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data)) - while data: - # Recall, data is a list of integers, namely the byte values sent by - # the MCU. - byte = data.pop(0) - # This means that |byte| is an int. - if byte == ord('\n'): - line.append(symbols[byte]) - if line: - self.logger.debug(u'%s', ''.join(line)) - line = [] - elif byte == ord('\b'): - # Backspace: trim the last character off the buffer - if line: - line.pop(-1) - elif byte in symbols: - line.append(symbols[byte]) - elif byte < ord(' ') or byte > ord('~'): - # Turn any character that isn't printable ASCII into escaped hex. - # ' ' is chr(20), and 0-19 are unprintable control characters. - # '~' is chr(126), and 127 is DELETE. 128-255 are control and Latin-1. - line.append(u'\\x%02x' % byte) - else: - # byte is printable. Thus it is safe to use chr() to get the printable - # character out of it again. - line.append(u'%s' % chr(byte)) - self.output_line_log_buffer = line - - def PrintHistory(self): - """Print the history of entered commands.""" - fd = self.controller_pty - # Make it pretty by figuring out how wide to pad the numbers. - wide = (len(self.history) // 10) + 1 - for i in range(len(self.history)): - line = b' %*d %s\r\n' % (wide, i, self.history[i]) - os.write(fd, line) - - def ShowPreviousCommand(self): - """Shows the previous command from the history list.""" - # There's nothing to do if there's no history at all. - if not self.history: - self.logger.debug('No history to print.') - return - - # Don't do anything if there's no more history to show. - if self.history_pos == 0: - self.logger.debug('No more history to show.') - return - - self.logger.debug('current history position: %d.', self.history_pos) - - # Decrement the history buffer position. - self.history_pos -= 1 - self.logger.debug('new history position.: %d', self.history_pos) - - # Save the text entered on the console if any. - if self.history_pos == len(self.history)-1: - self.logger.debug('saving partial_cmd: %r', self.input_buffer) - self.partial_cmd = self.input_buffer - - # Backspace the line. - for _ in range(self.input_buffer_pos): - self.SendBackspace() - - # Print the last entry in the history buffer. - self.logger.debug('printing previous entry %d - %s', self.history_pos, - self.history[self.history_pos]) - fd = self.controller_pty - prev_cmd = self.history[self.history_pos] - os.write(fd, prev_cmd) - # Update the input buffer. - self.input_buffer = prev_cmd - self.input_buffer_pos = len(prev_cmd) - - def ShowNextCommand(self): - """Shows the next command from the history list.""" - # Don't do anything if there's no history at all. - if not self.history: - self.logger.debug('History buffer is empty.') - return - - fd = self.controller_pty - - self.logger.debug('current history position: %d', self.history_pos) - # Increment the history position. - self.history_pos += 1 - - # Restore the partial cmd. - if self.history_pos == len(self.history): - self.logger.debug('Restoring partial command of %r', self.partial_cmd) - # Backspace the line. - for _ in range(self.input_buffer_pos): - self.SendBackspace() - # Print the partially entered command if any. - os.write(fd, self.partial_cmd) - self.input_buffer = self.partial_cmd - self.input_buffer_pos = len(self.input_buffer) - # Now that we've printed it, clear the partial cmd storage. - self.partial_cmd = b'' - # Reset history position. - self.history_pos = len(self.history) - return - - self.logger.debug('new history position: %d', self.history_pos) - if self.history_pos > len(self.history)-1: - self.logger.debug('No more history to show.') - self.history_pos -= 1 - self.logger.debug('Reset history position to %d', self.history_pos) - return - - # Backspace the line. - for _ in range(self.input_buffer_pos): - self.SendBackspace() - - # Print the newer entry from the history buffer. - self.logger.debug('printing next entry %d - %s', self.history_pos, - self.history[self.history_pos]) - next_cmd = self.history[self.history_pos] - os.write(fd, next_cmd) - # Update the input buffer. - self.input_buffer = next_cmd - self.input_buffer_pos = len(next_cmd) - self.logger.debug('new history position: %d.', self.history_pos) - - def SliceOutChar(self): - """Remove a char from the line and shift everything over 1 column.""" - fd = self.controller_pty - # Remove the character at the input_buffer_pos by slicing it out. - self.input_buffer = self.input_buffer[0:self.input_buffer_pos] + \ - self.input_buffer[self.input_buffer_pos+1:] - # Write the rest of the line - moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos:]) - # Write a space to clear out the last char - moved_col += os.write(fd, b' ') - # Update the input buffer position. - self.input_buffer_pos += moved_col - # Reset the cursor - self.MoveCursor('left', moved_col) - - def HandleEsc(self, byte): - """HandleEsc processes escape sequences. - Args: - byte: An integer representing the current byte in the sequence. +class Console(object): + """Class which provides the console interface between the EC and the user. + + This class essentially represents the console interface between the user and + the EC. It handles all of the console editing behaviour + + Attributes: + logger: A logger for this module. + controller_pty: File descriptor to the controller side of the PTY. Used for + driving output to the user and receiving user input. + user_pty: A string representing the PTY name of the served console. + cmd_pipe: A socket.socket or multiprocessing.Connection object which + represents the console side of the command pipe. This must be a + bidirectional pipe. Console commands and responses utilize this pipe. + dbg_pipe: A socket.socket or multiprocessing.Connection object which + represents the console's read-only side of the debug pipe. This must be a + unidirectional pipe attached to the intepreter. EC debug messages use + this pipe. + oobm_queue: A queue.Queue or multiprocessing.Queue which is used for out of + band management for the interactive console. + input_buffer: A string representing the current input command. + input_buffer_pos: An integer representing the current position in the buffer + to insert a char. + partial_cmd: A string representing the command entered on a line before + pressing the up arrow keys. + esc_state: An integer represeting the current state within an escape + sequence. + line_limit: An integer representing the maximum number of characters on a + line. + history: A list of strings containing the past entered console commands. + history_pos: An integer representing the current history buffer position. + This index is used to show previous commands. + prompt: A string representing the console prompt displayed to the user. + enhanced_ec: A boolean indicating if the EC image that we are currently + communicating with is enhanced or not. Enhanced EC images will support + packed commands and host commands over the UART. This defaults to False + until we perform some handshaking. + interrogation_timeout: A float representing the current maximum seconds to + wait for a response to an interrogation. + receiving_oobm_cmd: A boolean indicating whether or not the console is in + the middle of receiving an out of band command. + pending_oobm_cmd: A string containing the pending OOBM command. + interrogation_mode: A string containing the current mode of whether + interrogations are performed with the EC or not and how often. + raw_debug: Flag to indicate whether per interrupt data should be logged to + debug + output_line_log_buffer: buffer for lines coming from the EC to log to debug """ - # We shouldn't be handling an escape sequence if we haven't seen one. - assert self.esc_state != 0 - - if self.esc_state is EscState.ESC_START: - self.logger.debug('ESC_START') - if byte == ord('['): - self.esc_state = EscState.ESC_BRACKET - return - else: - self.logger.error('Unexpected sequence. %c', byte) - self.esc_state = 0 - - elif self.esc_state is EscState.ESC_BRACKET: - self.logger.debug('ESC_BRACKET') - # Left Arrow key was pressed. - if byte == ord('D'): - self.logger.debug('Left arrow key pressed.') - self.MoveCursor('left', 1) - self.esc_state = 0 # Reset the state. - return - - # Right Arrow key. - elif byte == ord('C'): - self.logger.debug('Right arrow key pressed.') - self.MoveCursor('right', 1) - self.esc_state = 0 # Reset the state. - return - - # Up Arrow key. - elif byte == ord('A'): - self.logger.debug('Up arrow key pressed.') - self.ShowPreviousCommand() - # Reset the state. - self.esc_state = 0 # Reset the state. - return - - # Down Arrow key. - elif byte == ord('B'): - self.logger.debug('Down arrow key pressed.') - self.ShowNextCommand() - # Reset the state. - self.esc_state = 0 # Reset the state. - return - - # For some reason, minicom sends a 1 instead of 7. /shrug - # TODO(aaboagye): Figure out why this happens. - elif byte == ord('1') or byte == ord('7'): - self.esc_state = EscState.ESC_BRACKET_1 - - elif byte == ord('3'): - self.esc_state = EscState.ESC_BRACKET_3 - - elif byte == ord('8'): - self.esc_state = EscState.ESC_BRACKET_8 - - else: - self.logger.error(r'Bad or unhandled escape sequence. got ^[%c\(%d)', - chr(byte), byte) - self.esc_state = 0 - return - - elif self.esc_state is EscState.ESC_BRACKET_1: - self.logger.debug('ESC_BRACKET_1') - # HOME key. - if byte == ord('~'): - self.logger.debug('Home key pressed.') - self.MoveCursor('left', self.input_buffer_pos) - self.esc_state = 0 # Reset the state. - self.logger.debug('ESC sequence complete.') - return - - elif self.esc_state is EscState.ESC_BRACKET_3: - self.logger.debug('ESC_BRACKET_3') - # DEL key. - if byte == ord('~'): - self.logger.debug('Delete key pressed.') - if self.input_buffer_pos != len(self.input_buffer): - self.SliceOutChar() - self.esc_state = 0 # Reset the state. - - elif self.esc_state is EscState.ESC_BRACKET_8: - self.logger.debug('ESC_BRACKET_8') - # END key. - if byte == ord('~'): - self.logger.debug('End key pressed.') - self.MoveCursor('right', - len(self.input_buffer) - self.input_buffer_pos) - self.esc_state = 0 # Reset the state. - self.logger.debug('ESC sequence complete.') - return - - else: - self.logger.error('Unexpected sequence. %c', byte) + def __init__( + self, controller_pty, user_pty, interface_pty, cmd_pipe, dbg_pipe, name=None + ): + """Initalises a Console object with the provided arguments. + + Args: + controller_pty: File descriptor to the controller side of the PTY. Used for + driving output to the user and receiving user input. + user_pty: A string representing the PTY name of the served console. + interface_pty: A string representing the PTY name of the served command + interface. + cmd_pipe: A socket.socket or multiprocessing.Connection object which + represents the console side of the command pipe. This must be a + bidirectional pipe. Console commands and responses utilize this pipe. + dbg_pipe: A socket.socket or multiprocessing.Connection object which + represents the console's read-only side of the debug pipe. This must be a + unidirectional pipe attached to the intepreter. EC debug messages use + this pipe. + name: the console source name + """ + # Create a unique logger based on the console name + console_prefix = ("%s - " % name) if name else "" + logger = logging.getLogger("%sEC3PO.Console" % console_prefix) + self.logger = interpreter.LoggerAdapter(logger, {"pty": user_pty}) + self.controller_pty = controller_pty + self.user_pty = user_pty + self.interface_pty = interface_pty + self.cmd_pipe = cmd_pipe + self.dbg_pipe = dbg_pipe + self.oobm_queue = threadproc_shim.Queue() + self.input_buffer = b"" + self.input_buffer_pos = 0 + self.partial_cmd = b"" self.esc_state = 0 + self.line_limit = CONSOLE_INPUT_LINE_SIZE + self.history = [] + self.history_pos = 0 + self.prompt = PROMPT + self.enhanced_ec = False + self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT + self.receiving_oobm_cmd = False + self.pending_oobm_cmd = b"" + self.interrogation_mode = b"auto" + self.timestamp_enabled = True + self.look_buffer = b"" + self.raw_debug = False + self.output_line_log_buffer = [] + + def __str__(self): + """Show internal state of Console object as a string.""" + string = [] + string.append("controller_pty: %s" % self.controller_pty) + string.append("user_pty: %s" % self.user_pty) + string.append("interface_pty: %s" % self.interface_pty) + string.append("cmd_pipe: %s" % self.cmd_pipe) + string.append("dbg_pipe: %s" % self.dbg_pipe) + string.append("oobm_queue: %s" % self.oobm_queue) + string.append("input_buffer: %s" % self.input_buffer) + string.append("input_buffer_pos: %d" % self.input_buffer_pos) + string.append("esc_state: %d" % self.esc_state) + string.append("line_limit: %d" % self.line_limit) + string.append("history: %r" % self.history) + string.append("history_pos: %d" % self.history_pos) + string.append("prompt: %r" % self.prompt) + string.append("partial_cmd: %r" % self.partial_cmd) + string.append("interrogation_mode: %r" % self.interrogation_mode) + string.append("look_buffer: %r" % self.look_buffer) + return "\n".join(string) + + def LogConsoleOutput(self, data): + """Log to debug user MCU output to controller_pty when line is filled. + + The logging also suppresses the Cr50 spinner lines by removing characters + when it sees backspaces. + + Args: + data: bytes - string received from MCU + """ + data = list(data) + # For compatibility with python2 and python3, standardize on the data + # being a list of integers. This requires one more transformation in py2 + if not isinstance(data[0], int): + data = [ord(c) for c in data] + + # This is a list of already filtered characters (or placeholders). + line = self.output_line_log_buffer + + # TODO(b/177480273): use raw strings here + symbols = {ord(b"\n"): "\\n", ord(b"\r"): "\\r", ord(b"\t"): "\\t"} + # self.logger.debug(u'%s + %r', u''.join(line), ''.join(data)) + while data: + # Recall, data is a list of integers, namely the byte values sent by + # the MCU. + byte = data.pop(0) + # This means that |byte| is an int. + if byte == ord("\n"): + line.append(symbols[byte]) + if line: + self.logger.debug("%s", "".join(line)) + line = [] + elif byte == ord("\b"): + # Backspace: trim the last character off the buffer + if line: + line.pop(-1) + elif byte in symbols: + line.append(symbols[byte]) + elif byte < ord(" ") or byte > ord("~"): + # Turn any character that isn't printable ASCII into escaped hex. + # ' ' is chr(20), and 0-19 are unprintable control characters. + # '~' is chr(126), and 127 is DELETE. 128-255 are control and Latin-1. + line.append("\\x%02x" % byte) + else: + # byte is printable. Thus it is safe to use chr() to get the printable + # character out of it again. + line.append("%s" % chr(byte)) + self.output_line_log_buffer = line + + def PrintHistory(self): + """Print the history of entered commands.""" + fd = self.controller_pty + # Make it pretty by figuring out how wide to pad the numbers. + wide = (len(self.history) // 10) + 1 + for i in range(len(self.history)): + line = b" %*d %s\r\n" % (wide, i, self.history[i]) + os.write(fd, line) + + def ShowPreviousCommand(self): + """Shows the previous command from the history list.""" + # There's nothing to do if there's no history at all. + if not self.history: + self.logger.debug("No history to print.") + return + + # Don't do anything if there's no more history to show. + if self.history_pos == 0: + self.logger.debug("No more history to show.") + return + + self.logger.debug("current history position: %d.", self.history_pos) + + # Decrement the history buffer position. + self.history_pos -= 1 + self.logger.debug("new history position.: %d", self.history_pos) + + # Save the text entered on the console if any. + if self.history_pos == len(self.history) - 1: + self.logger.debug("saving partial_cmd: %r", self.input_buffer) + self.partial_cmd = self.input_buffer + + # Backspace the line. + for _ in range(self.input_buffer_pos): + self.SendBackspace() + + # Print the last entry in the history buffer. + self.logger.debug( + "printing previous entry %d - %s", + self.history_pos, + self.history[self.history_pos], + ) + fd = self.controller_pty + prev_cmd = self.history[self.history_pos] + os.write(fd, prev_cmd) + # Update the input buffer. + self.input_buffer = prev_cmd + self.input_buffer_pos = len(prev_cmd) + + def ShowNextCommand(self): + """Shows the next command from the history list.""" + # Don't do anything if there's no history at all. + if not self.history: + self.logger.debug("History buffer is empty.") + return + + fd = self.controller_pty + + self.logger.debug("current history position: %d", self.history_pos) + # Increment the history position. + self.history_pos += 1 + + # Restore the partial cmd. + if self.history_pos == len(self.history): + self.logger.debug("Restoring partial command of %r", self.partial_cmd) + # Backspace the line. + for _ in range(self.input_buffer_pos): + self.SendBackspace() + # Print the partially entered command if any. + os.write(fd, self.partial_cmd) + self.input_buffer = self.partial_cmd + self.input_buffer_pos = len(self.input_buffer) + # Now that we've printed it, clear the partial cmd storage. + self.partial_cmd = b"" + # Reset history position. + self.history_pos = len(self.history) + return + + self.logger.debug("new history position: %d", self.history_pos) + if self.history_pos > len(self.history) - 1: + self.logger.debug("No more history to show.") + self.history_pos -= 1 + self.logger.debug("Reset history position to %d", self.history_pos) + return + + # Backspace the line. + for _ in range(self.input_buffer_pos): + self.SendBackspace() + + # Print the newer entry from the history buffer. + self.logger.debug( + "printing next entry %d - %s", + self.history_pos, + self.history[self.history_pos], + ) + next_cmd = self.history[self.history_pos] + os.write(fd, next_cmd) + # Update the input buffer. + self.input_buffer = next_cmd + self.input_buffer_pos = len(next_cmd) + self.logger.debug("new history position: %d.", self.history_pos) + + def SliceOutChar(self): + """Remove a char from the line and shift everything over 1 column.""" + fd = self.controller_pty + # Remove the character at the input_buffer_pos by slicing it out. + self.input_buffer = ( + self.input_buffer[0 : self.input_buffer_pos] + + self.input_buffer[self.input_buffer_pos + 1 :] + ) + # Write the rest of the line + moved_col = os.write(fd, self.input_buffer[self.input_buffer_pos :]) + # Write a space to clear out the last char + moved_col += os.write(fd, b" ") + # Update the input buffer position. + self.input_buffer_pos += moved_col + # Reset the cursor + self.MoveCursor("left", moved_col) + + def HandleEsc(self, byte): + """HandleEsc processes escape sequences. + + Args: + byte: An integer representing the current byte in the sequence. + """ + # We shouldn't be handling an escape sequence if we haven't seen one. + assert self.esc_state != 0 + + if self.esc_state is EscState.ESC_START: + self.logger.debug("ESC_START") + if byte == ord("["): + self.esc_state = EscState.ESC_BRACKET + return + + else: + self.logger.error("Unexpected sequence. %c", byte) + self.esc_state = 0 + + elif self.esc_state is EscState.ESC_BRACKET: + self.logger.debug("ESC_BRACKET") + # Left Arrow key was pressed. + if byte == ord("D"): + self.logger.debug("Left arrow key pressed.") + self.MoveCursor("left", 1) + self.esc_state = 0 # Reset the state. + return + + # Right Arrow key. + elif byte == ord("C"): + self.logger.debug("Right arrow key pressed.") + self.MoveCursor("right", 1) + self.esc_state = 0 # Reset the state. + return + + # Up Arrow key. + elif byte == ord("A"): + self.logger.debug("Up arrow key pressed.") + self.ShowPreviousCommand() + # Reset the state. + self.esc_state = 0 # Reset the state. + return + + # Down Arrow key. + elif byte == ord("B"): + self.logger.debug("Down arrow key pressed.") + self.ShowNextCommand() + # Reset the state. + self.esc_state = 0 # Reset the state. + return + + # For some reason, minicom sends a 1 instead of 7. /shrug + # TODO(aaboagye): Figure out why this happens. + elif byte == ord("1") or byte == ord("7"): + self.esc_state = EscState.ESC_BRACKET_1 + + elif byte == ord("3"): + self.esc_state = EscState.ESC_BRACKET_3 + + elif byte == ord("8"): + self.esc_state = EscState.ESC_BRACKET_8 + + else: + self.logger.error( + r"Bad or unhandled escape sequence. got ^[%c\(%d)", chr(byte), byte + ) + self.esc_state = 0 + return + + elif self.esc_state is EscState.ESC_BRACKET_1: + self.logger.debug("ESC_BRACKET_1") + # HOME key. + if byte == ord("~"): + self.logger.debug("Home key pressed.") + self.MoveCursor("left", self.input_buffer_pos) + self.esc_state = 0 # Reset the state. + self.logger.debug("ESC sequence complete.") + return + + elif self.esc_state is EscState.ESC_BRACKET_3: + self.logger.debug("ESC_BRACKET_3") + # DEL key. + if byte == ord("~"): + self.logger.debug("Delete key pressed.") + if self.input_buffer_pos != len(self.input_buffer): + self.SliceOutChar() + self.esc_state = 0 # Reset the state. + + elif self.esc_state is EscState.ESC_BRACKET_8: + self.logger.debug("ESC_BRACKET_8") + # END key. + if byte == ord("~"): + self.logger.debug("End key pressed.") + self.MoveCursor("right", len(self.input_buffer) - self.input_buffer_pos) + self.esc_state = 0 # Reset the state. + self.logger.debug("ESC sequence complete.") + return + + else: + self.logger.error("Unexpected sequence. %c", byte) + self.esc_state = 0 + + else: + self.logger.error("Unexpected sequence. %c", byte) + self.esc_state = 0 + + def ProcessInput(self): + """Captures the input determines what actions to take.""" + # There's nothing to do if the input buffer is empty. + if len(self.input_buffer) == 0: + return + + # Don't store 2 consecutive identical commands in the history. + if self.history and self.history[-1] != self.input_buffer or not self.history: + self.history.append(self.input_buffer) + + # Split the command up by spaces. + line = self.input_buffer.split(b" ") + self.logger.debug("cmd: %s", self.input_buffer) + cmd = line[0].lower() + + # The 'history' command is a special case that we handle locally. + if cmd == "history": + self.PrintHistory() + return + + # Send the command to the interpreter. + self.logger.debug("Sending command to interpreter.") + self.cmd_pipe.send(self.input_buffer) + + def CheckForEnhancedECImage(self): + """Performs an interrogation of the EC image. + + Send a SYN and expect an ACK. If no ACK or the response is incorrect, then + assume that the current EC image that we are talking to is not enhanced. + + Returns: + is_enhanced: A boolean indicating whether the EC responded to the + interrogation correctly. + + Raises: + EOFError: Allowed to propagate through from self.dbg_pipe.recv(). + """ + # Send interrogation byte and wait for the response. + self.logger.debug("Performing interrogation.") + self.cmd_pipe.send(interpreter.EC_SYN) + + response = "" + if self.dbg_pipe.poll(self.interrogation_timeout): + response = self.dbg_pipe.recv() + self.logger.debug("response: %r", binascii.hexlify(response)) + else: + self.logger.debug("Timed out waiting for EC_ACK") + + # Verify the acknowledgment. + is_enhanced = response == interpreter.EC_ACK + + if is_enhanced: + # Increase the interrogation timeout for stability purposes. + self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT + self.logger.debug( + "Increasing interrogation timeout to %rs.", self.interrogation_timeout + ) + else: + # Reduce the timeout in order to reduce the perceivable delay. + self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT + self.logger.debug( + "Reducing interrogation timeout to %rs.", self.interrogation_timeout + ) + + return is_enhanced + + def HandleChar(self, byte): + """HandleChar does a certain action when it receives a character. + + Args: + byte: An integer representing the character received from the user. + + Raises: + EOFError: Allowed to propagate through from self.CheckForEnhancedECImage() + i.e. from self.dbg_pipe.recv(). + """ + fd = self.controller_pty + + # Enter the OOBM prompt mode if the user presses '%'. + if byte == ord("%"): + self.logger.debug("Begin OOBM command.") + self.receiving_oobm_cmd = True + # Print a "prompt". + os.write(self.controller_pty, b"\r\n% ") + return + + # Add chars to the pending OOBM command if we're currently receiving one. + if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN: + tmp_bytes = six.int2byte(byte) + self.pending_oobm_cmd += tmp_bytes + self.logger.debug("%s", tmp_bytes) + os.write(self.controller_pty, tmp_bytes) + return + + if byte == ControlKey.CARRIAGE_RETURN: + if self.receiving_oobm_cmd: + # Terminate the command and place it in the OOBM queue. + self.logger.debug("End OOBM command.") + if self.pending_oobm_cmd: + self.oobm_queue.put(self.pending_oobm_cmd) + self.logger.debug( + "Placed %r into OOBM command queue.", self.pending_oobm_cmd + ) + + # Reset the state. + os.write(self.controller_pty, b"\r\n" + self.prompt) + self.input_buffer = b"" + self.input_buffer_pos = 0 + self.receiving_oobm_cmd = False + self.pending_oobm_cmd = b"" + return + + if self.interrogation_mode == b"never": + self.logger.debug( + "Skipping interrogation because interrogation mode" + " is set to never." + ) + elif self.interrogation_mode == b"always": + # Only interrogate the EC if the interrogation mode is set to 'always'. + self.enhanced_ec = self.CheckForEnhancedECImage() + self.logger.debug("Enhanced EC image? %r", self.enhanced_ec) + + if not self.enhanced_ec: + # Send everything straight to the EC to handle. + self.cmd_pipe.send(six.int2byte(byte)) + # Reset the input buffer. + self.input_buffer = b"" + self.input_buffer_pos = 0 + self.logger.log(1, "Reset input buffer.") + return + + # Keep handling the ESC sequence if we're in the middle of it. + if self.esc_state != 0: + self.HandleEsc(byte) + return + + # When we're at the end of the line, we should only allow going backwards, + # backspace, carriage return, up, or down. The arrow keys are escape + # sequences, so we let the escape...escape. + if self.input_buffer_pos >= self.line_limit and byte not in [ + ControlKey.CTRL_B, + ControlKey.ESC, + ControlKey.BACKSPACE, + ControlKey.CTRL_A, + ControlKey.CARRIAGE_RETURN, + ControlKey.CTRL_P, + ControlKey.CTRL_N, + ]: + return + + # If the input buffer is full we can't accept new chars. + buffer_full = len(self.input_buffer) >= self.line_limit + + # Carriage_Return/Enter + if byte == ControlKey.CARRIAGE_RETURN: + self.logger.debug("Enter key pressed.") + # Put a carriage return/newline and the print the prompt. + os.write(fd, b"\r\n") + + # TODO(aaboagye): When we control the printing of all output, print the + # prompt AFTER printing all the output. We can't do it yet because we + # don't know how much is coming from the EC. + + # Print the prompt. + os.write(fd, self.prompt) + # Process the input. + self.ProcessInput() + # Now, clear the buffer. + self.input_buffer = b"" + self.input_buffer_pos = 0 + # Reset history buffer pos. + self.history_pos = len(self.history) + # Clear partial command. + self.partial_cmd = b"" + + # Backspace + elif byte == ControlKey.BACKSPACE: + self.logger.debug("Backspace pressed.") + if self.input_buffer_pos > 0: + # Move left 1 column. + self.MoveCursor("left", 1) + # Remove the character at the input_buffer_pos by slicing it out. + self.SliceOutChar() + + self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos) + + # Ctrl+A. Move cursor to beginning of the line + elif byte == ControlKey.CTRL_A: + self.logger.debug("Control+A pressed.") + self.MoveCursor("left", self.input_buffer_pos) + + # Ctrl+B. Move cursor left 1 column. + elif byte == ControlKey.CTRL_B: + self.logger.debug("Control+B pressed.") + self.MoveCursor("left", 1) + + # Ctrl+D. Delete a character. + elif byte == ControlKey.CTRL_D: + self.logger.debug("Control+D pressed.") + if self.input_buffer_pos != len(self.input_buffer): + # Remove the character by slicing it out. + self.SliceOutChar() + + # Ctrl+E. Move cursor to end of the line. + elif byte == ControlKey.CTRL_E: + self.logger.debug("Control+E pressed.") + self.MoveCursor("right", len(self.input_buffer) - self.input_buffer_pos) + + # Ctrl+F. Move cursor right 1 column. + elif byte == ControlKey.CTRL_F: + self.logger.debug("Control+F pressed.") + self.MoveCursor("right", 1) + + # Ctrl+K. Kill line. + elif byte == ControlKey.CTRL_K: + self.logger.debug("Control+K pressed.") + self.KillLine() + + # Ctrl+N. Next line. + elif byte == ControlKey.CTRL_N: + self.logger.debug("Control+N pressed.") + self.ShowNextCommand() + + # Ctrl+P. Previous line. + elif byte == ControlKey.CTRL_P: + self.logger.debug("Control+P pressed.") + self.ShowPreviousCommand() + + # ESC sequence + elif byte == ControlKey.ESC: + # Starting an ESC sequence + self.esc_state = EscState.ESC_START + + # Only print printable chars. + elif IsPrintable(byte): + # Drop the character if we're full. + if buffer_full: + self.logger.debug("Dropped char: %c(%d)", byte, byte) + return + # Print the character. + os.write(fd, six.int2byte(byte)) + # Print the rest of the line (if any). + extra_bytes_written = os.write( + fd, self.input_buffer[self.input_buffer_pos :] + ) + + # Recreate the input buffer. + self.input_buffer = ( + self.input_buffer[0 : self.input_buffer_pos] + + six.int2byte(byte) + + self.input_buffer[self.input_buffer_pos :] + ) + # Update the input buffer position. + self.input_buffer_pos += 1 + extra_bytes_written + + # Reset the cursor if we wrote any extra bytes. + if extra_bytes_written: + self.MoveCursor("left", extra_bytes_written) + + self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos) + + def MoveCursor(self, direction, count): + """MoveCursor moves the cursor left or right by count columns. + + Args: + direction: A string that should be either 'left' or 'right' representing + the direction to move the cursor on the console. + count: An integer representing how many columns the cursor should be + moved. + + Raises: + AssertionError: If the direction is not equal to 'left' or 'right'. + """ + # If there's nothing to move, we're done. + if not count: + return + fd = self.controller_pty + seq = b"\033[" + str(count).encode("ascii") + if direction == "left": + # Bind the movement. + if count > self.input_buffer_pos: + count = self.input_buffer_pos + seq += b"D" + self.logger.debug("move cursor left %d", count) + self.input_buffer_pos -= count + + elif direction == "right": + # Bind the movement. + if (count + self.input_buffer_pos) > len(self.input_buffer): + count = 0 + seq += b"C" + self.logger.debug("move cursor right %d", count) + self.input_buffer_pos += count + + else: + raise AssertionError( + ("The only valid directions are 'left' and " "'right'") + ) + + self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos) + # Move the cursor. + if count != 0: + os.write(fd, seq) + + def KillLine(self): + """Kill the rest of the line based on the input buffer position.""" + # Killing the line is killing all the text to the right. + diff = len(self.input_buffer) - self.input_buffer_pos + self.logger.debug("diff: %d", diff) + # Diff shouldn't be negative, but if it is for some reason, let's try to + # correct the cursor. + if diff < 0: + self.logger.warning( + "Resetting input buffer position to %d...", len(self.input_buffer) + ) + self.MoveCursor("left", -diff) + return + if diff: + self.MoveCursor("right", diff) + for _ in range(diff): + self.SendBackspace() + self.input_buffer_pos -= diff + self.input_buffer = self.input_buffer[0 : self.input_buffer_pos] + + def SendBackspace(self): + """Backspace a character on the console.""" + os.write(self.controller_pty, b"\033[1D \033[1D") + + def ProcessOOBMQueue(self): + """Retrieve an item from the OOBM queue and process it.""" + item = self.oobm_queue.get() + self.logger.debug("OOBM cmd: %r", item) + cmd = item.split(b" ") + + if cmd[0] == b"loglevel": + # An integer is required in order to set the log level. + if len(cmd) < 2: + self.logger.debug("Insufficient args") + self.PrintOOBMHelp() + return + try: + self.logger.debug("Log level change request.") + new_log_level = int(cmd[1]) + self.logger.logger.setLevel(new_log_level) + self.logger.info("Log level changed to %d.", new_log_level) + + # Forward the request to the interpreter as well. + self.cmd_pipe.send(item) + except ValueError: + # Ignoring the request if an integer was not provided. + self.PrintOOBMHelp() + + elif cmd[0] == b"timestamp": + mode = cmd[1].lower() + self.timestamp_enabled = mode == b"on" + self.logger.info( + "%sabling uart timestamps.", "En" if self.timestamp_enabled else "Dis" + ) + + elif cmd[0] == b"rawdebug": + mode = cmd[1].lower() + self.raw_debug = mode == b"on" + self.logger.info( + "%sabling per interrupt debug logs.", "En" if self.raw_debug else "Dis" + ) + + elif cmd[0] == b"interrogate" and len(cmd) >= 2: + enhanced = False + mode = cmd[1] + if len(cmd) >= 3 and cmd[2] == b"enhanced": + enhanced = True + + # Set the mode if correct. + if mode in INTERROGATION_MODES: + self.interrogation_mode = mode + self.logger.debug("Updated interrogation mode to %s.", mode) + + # Update the assumptions of the EC image. + self.enhanced_ec = enhanced + self.logger.debug("Enhanced EC image is now %r", self.enhanced_ec) + + # Send command to interpreter as well. + self.cmd_pipe.send(b"enhanced " + str(self.enhanced_ec).encode("ascii")) + else: + self.PrintOOBMHelp() + + else: + self.PrintOOBMHelp() + + def PrintOOBMHelp(self): + """Prints out the OOBM help.""" + # Print help syntax. + os.write(self.controller_pty, b"\r\n" + b"Known OOBM commands:\r\n") + os.write( + self.controller_pty, + b" interrogate " b"[enhanced]\r\n", + ) + os.write(self.controller_pty, b" loglevel \r\n") + + def CheckBufferForEnhancedImage(self, data): + """Adds data to a look buffer and checks to see for enhanced EC image. + + The EC's console task prints a string upon initialization which says that + "Console is enabled; type HELP for help.". The enhanced EC images print a + different string as a part of their init. This function searches through a + "look" buffer, scanning for the presence of either of those strings and + updating the enhanced_ec state accordingly. + + Args: + data: A string containing the data sent from the interpreter. + """ + self.look_buffer += data + + # Search the buffer for any of the EC image strings. + enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer) + non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer) + + # Update the state if any matches were found. + if enhanced_match or non_enhanced_match: + if enhanced_match: + self.enhanced_ec = True + elif non_enhanced_match: + self.enhanced_ec = False + + # Inform the interpreter of the result. + self.cmd_pipe.send(b"enhanced " + str(self.enhanced_ec).encode("ascii")) + self.logger.debug("Enhanced EC image? %r", self.enhanced_ec) + + # Clear look buffer since a match was found. + self.look_buffer = b"" + + # Move the sliding window. + self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:] - else: - self.logger.error('Unexpected sequence. %c', byte) - self.esc_state = 0 - - def ProcessInput(self): - """Captures the input determines what actions to take.""" - # There's nothing to do if the input buffer is empty. - if len(self.input_buffer) == 0: - return - - # Don't store 2 consecutive identical commands in the history. - if (self.history and self.history[-1] != self.input_buffer - or not self.history): - self.history.append(self.input_buffer) - - # Split the command up by spaces. - line = self.input_buffer.split(b' ') - self.logger.debug('cmd: %s', self.input_buffer) - cmd = line[0].lower() - - # The 'history' command is a special case that we handle locally. - if cmd == 'history': - self.PrintHistory() - return - - # Send the command to the interpreter. - self.logger.debug('Sending command to interpreter.') - self.cmd_pipe.send(self.input_buffer) - def CheckForEnhancedECImage(self): - """Performs an interrogation of the EC image. +def CanonicalizeTimeString(timestr): + """Canonicalize the timestamp string. - Send a SYN and expect an ACK. If no ACK or the response is incorrect, then - assume that the current EC image that we are talking to is not enhanced. + Args: + timestr: A timestamp string ended with 6 digits msec. Returns: - is_enhanced: A boolean indicating whether the EC responded to the - interrogation correctly. - - Raises: - EOFError: Allowed to propagate through from self.dbg_pipe.recv(). + A string with 3 digits msec and an extra space. """ - # Send interrogation byte and wait for the response. - self.logger.debug('Performing interrogation.') - self.cmd_pipe.send(interpreter.EC_SYN) - - response = '' - if self.dbg_pipe.poll(self.interrogation_timeout): - response = self.dbg_pipe.recv() - self.logger.debug('response: %r', binascii.hexlify(response)) - else: - self.logger.debug('Timed out waiting for EC_ACK') + return timestr[:-3].encode("ascii") + b" " - # Verify the acknowledgment. - is_enhanced = response == interpreter.EC_ACK - - if is_enhanced: - # Increase the interrogation timeout for stability purposes. - self.interrogation_timeout = ENHANCED_EC_INTERROGATION_TIMEOUT - self.logger.debug('Increasing interrogation timeout to %rs.', - self.interrogation_timeout) - else: - # Reduce the timeout in order to reduce the perceivable delay. - self.interrogation_timeout = NON_ENHANCED_EC_INTERROGATION_TIMEOUT - self.logger.debug('Reducing interrogation timeout to %rs.', - self.interrogation_timeout) - - return is_enhanced - - def HandleChar(self, byte): - """HandleChar does a certain action when it receives a character. - - Args: - byte: An integer representing the character received from the user. - Raises: - EOFError: Allowed to propagate through from self.CheckForEnhancedECImage() - i.e. from self.dbg_pipe.recv(). - """ - fd = self.controller_pty - - # Enter the OOBM prompt mode if the user presses '%'. - if byte == ord('%'): - self.logger.debug('Begin OOBM command.') - self.receiving_oobm_cmd = True - # Print a "prompt". - os.write(self.controller_pty, b'\r\n% ') - return - - # Add chars to the pending OOBM command if we're currently receiving one. - if self.receiving_oobm_cmd and byte != ControlKey.CARRIAGE_RETURN: - tmp_bytes = six.int2byte(byte) - self.pending_oobm_cmd += tmp_bytes - self.logger.debug('%s', tmp_bytes) - os.write(self.controller_pty, tmp_bytes) - return - - if byte == ControlKey.CARRIAGE_RETURN: - if self.receiving_oobm_cmd: - # Terminate the command and place it in the OOBM queue. - self.logger.debug('End OOBM command.') - if self.pending_oobm_cmd: - self.oobm_queue.put(self.pending_oobm_cmd) - self.logger.debug('Placed %r into OOBM command queue.', - self.pending_oobm_cmd) - - # Reset the state. - os.write(self.controller_pty, b'\r\n' + self.prompt) - self.input_buffer = b'' - self.input_buffer_pos = 0 - self.receiving_oobm_cmd = False - self.pending_oobm_cmd = b'' - return - - if self.interrogation_mode == b'never': - self.logger.debug('Skipping interrogation because interrogation mode' - ' is set to never.') - elif self.interrogation_mode == b'always': - # Only interrogate the EC if the interrogation mode is set to 'always'. - self.enhanced_ec = self.CheckForEnhancedECImage() - self.logger.debug('Enhanced EC image? %r', self.enhanced_ec) - - if not self.enhanced_ec: - # Send everything straight to the EC to handle. - self.cmd_pipe.send(six.int2byte(byte)) - # Reset the input buffer. - self.input_buffer = b'' - self.input_buffer_pos = 0 - self.logger.log(1, 'Reset input buffer.') - return - - # Keep handling the ESC sequence if we're in the middle of it. - if self.esc_state != 0: - self.HandleEsc(byte) - return - - # When we're at the end of the line, we should only allow going backwards, - # backspace, carriage return, up, or down. The arrow keys are escape - # sequences, so we let the escape...escape. - if (self.input_buffer_pos >= self.line_limit and - byte not in [ControlKey.CTRL_B, ControlKey.ESC, ControlKey.BACKSPACE, - ControlKey.CTRL_A, ControlKey.CARRIAGE_RETURN, - ControlKey.CTRL_P, ControlKey.CTRL_N]): - return - - # If the input buffer is full we can't accept new chars. - buffer_full = len(self.input_buffer) >= self.line_limit - - - # Carriage_Return/Enter - if byte == ControlKey.CARRIAGE_RETURN: - self.logger.debug('Enter key pressed.') - # Put a carriage return/newline and the print the prompt. - os.write(fd, b'\r\n') - - # TODO(aaboagye): When we control the printing of all output, print the - # prompt AFTER printing all the output. We can't do it yet because we - # don't know how much is coming from the EC. - - # Print the prompt. - os.write(fd, self.prompt) - # Process the input. - self.ProcessInput() - # Now, clear the buffer. - self.input_buffer = b'' - self.input_buffer_pos = 0 - # Reset history buffer pos. - self.history_pos = len(self.history) - # Clear partial command. - self.partial_cmd = b'' - - # Backspace - elif byte == ControlKey.BACKSPACE: - self.logger.debug('Backspace pressed.') - if self.input_buffer_pos > 0: - # Move left 1 column. - self.MoveCursor('left', 1) - # Remove the character at the input_buffer_pos by slicing it out. - self.SliceOutChar() - - self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos) - - # Ctrl+A. Move cursor to beginning of the line - elif byte == ControlKey.CTRL_A: - self.logger.debug('Control+A pressed.') - self.MoveCursor('left', self.input_buffer_pos) - - # Ctrl+B. Move cursor left 1 column. - elif byte == ControlKey.CTRL_B: - self.logger.debug('Control+B pressed.') - self.MoveCursor('left', 1) - - # Ctrl+D. Delete a character. - elif byte == ControlKey.CTRL_D: - self.logger.debug('Control+D pressed.') - if self.input_buffer_pos != len(self.input_buffer): - # Remove the character by slicing it out. - self.SliceOutChar() - - # Ctrl+E. Move cursor to end of the line. - elif byte == ControlKey.CTRL_E: - self.logger.debug('Control+E pressed.') - self.MoveCursor('right', - len(self.input_buffer) - self.input_buffer_pos) - - # Ctrl+F. Move cursor right 1 column. - elif byte == ControlKey.CTRL_F: - self.logger.debug('Control+F pressed.') - self.MoveCursor('right', 1) - - # Ctrl+K. Kill line. - elif byte == ControlKey.CTRL_K: - self.logger.debug('Control+K pressed.') - self.KillLine() - - # Ctrl+N. Next line. - elif byte == ControlKey.CTRL_N: - self.logger.debug('Control+N pressed.') - self.ShowNextCommand() - - # Ctrl+P. Previous line. - elif byte == ControlKey.CTRL_P: - self.logger.debug('Control+P pressed.') - self.ShowPreviousCommand() - - # ESC sequence - elif byte == ControlKey.ESC: - # Starting an ESC sequence - self.esc_state = EscState.ESC_START - - # Only print printable chars. - elif IsPrintable(byte): - # Drop the character if we're full. - if buffer_full: - self.logger.debug('Dropped char: %c(%d)', byte, byte) - return - # Print the character. - os.write(fd, six.int2byte(byte)) - # Print the rest of the line (if any). - extra_bytes_written = os.write(fd, - self.input_buffer[self.input_buffer_pos:]) - - # Recreate the input buffer. - self.input_buffer = (self.input_buffer[0:self.input_buffer_pos] + - six.int2byte(byte) + - self.input_buffer[self.input_buffer_pos:]) - # Update the input buffer position. - self.input_buffer_pos += 1 + extra_bytes_written - - # Reset the cursor if we wrote any extra bytes. - if extra_bytes_written: - self.MoveCursor('left', extra_bytes_written) - - self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos) - - def MoveCursor(self, direction, count): - """MoveCursor moves the cursor left or right by count columns. +def IsPrintable(byte): + """Determines if a byte is printable. Args: - direction: A string that should be either 'left' or 'right' representing - the direction to move the cursor on the console. - count: An integer representing how many columns the cursor should be - moved. + byte: An integer potentially representing a printable character. - Raises: - AssertionError: If the direction is not equal to 'left' or 'right'. + Returns: + A boolean indicating whether the byte is a printable character. """ - # If there's nothing to move, we're done. - if not count: - return - fd = self.controller_pty - seq = b'\033[' + str(count).encode('ascii') - if direction == 'left': - # Bind the movement. - if count > self.input_buffer_pos: - count = self.input_buffer_pos - seq += b'D' - self.logger.debug('move cursor left %d', count) - self.input_buffer_pos -= count - - elif direction == 'right': - # Bind the movement. - if (count + self.input_buffer_pos) > len(self.input_buffer): - count = 0 - seq += b'C' - self.logger.debug('move cursor right %d', count) - self.input_buffer_pos += count - - else: - raise AssertionError(('The only valid directions are \'left\' and ' - '\'right\'')) - - self.logger.debug('input_buffer_pos: %d', self.input_buffer_pos) - # Move the cursor. - if count != 0: - os.write(fd, seq) - - def KillLine(self): - """Kill the rest of the line based on the input buffer position.""" - # Killing the line is killing all the text to the right. - diff = len(self.input_buffer) - self.input_buffer_pos - self.logger.debug('diff: %d', diff) - # Diff shouldn't be negative, but if it is for some reason, let's try to - # correct the cursor. - if diff < 0: - self.logger.warning('Resetting input buffer position to %d...', - len(self.input_buffer)) - self.MoveCursor('left', -diff) - return - if diff: - self.MoveCursor('right', diff) - for _ in range(diff): - self.SendBackspace() - self.input_buffer_pos -= diff - self.input_buffer = self.input_buffer[0:self.input_buffer_pos] - - def SendBackspace(self): - """Backspace a character on the console.""" - os.write(self.controller_pty, b'\033[1D \033[1D') - - def ProcessOOBMQueue(self): - """Retrieve an item from the OOBM queue and process it.""" - item = self.oobm_queue.get() - self.logger.debug('OOBM cmd: %r', item) - cmd = item.split(b' ') - - if cmd[0] == b'loglevel': - # An integer is required in order to set the log level. - if len(cmd) < 2: - self.logger.debug('Insufficient args') - self.PrintOOBMHelp() - return - try: - self.logger.debug('Log level change request.') - new_log_level = int(cmd[1]) - self.logger.logger.setLevel(new_log_level) - self.logger.info('Log level changed to %d.', new_log_level) - - # Forward the request to the interpreter as well. - self.cmd_pipe.send(item) - except ValueError: - # Ignoring the request if an integer was not provided. - self.PrintOOBMHelp() - - elif cmd[0] == b'timestamp': - mode = cmd[1].lower() - self.timestamp_enabled = (mode == b'on') - self.logger.info('%sabling uart timestamps.', - 'En' if self.timestamp_enabled else 'Dis') - - elif cmd[0] == b'rawdebug': - mode = cmd[1].lower() - self.raw_debug = (mode == b'on') - self.logger.info('%sabling per interrupt debug logs.', - 'En' if self.raw_debug else 'Dis') - - elif cmd[0] == b'interrogate' and len(cmd) >= 2: - enhanced = False - mode = cmd[1] - if len(cmd) >= 3 and cmd[2] == b'enhanced': - enhanced = True - - # Set the mode if correct. - if mode in INTERROGATION_MODES: - self.interrogation_mode = mode - self.logger.debug('Updated interrogation mode to %s.', mode) - - # Update the assumptions of the EC image. - self.enhanced_ec = enhanced - self.logger.debug('Enhanced EC image is now %r', self.enhanced_ec) - - # Send command to interpreter as well. - self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii')) - else: - self.PrintOOBMHelp() - - else: - self.PrintOOBMHelp() + return byte >= ord(" ") and byte <= ord("~") - def PrintOOBMHelp(self): - """Prints out the OOBM help.""" - # Print help syntax. - os.write(self.controller_pty, b'\r\n' + b'Known OOBM commands:\r\n') - os.write(self.controller_pty, b' interrogate ' - b'[enhanced]\r\n') - os.write(self.controller_pty, b' loglevel \r\n') - def CheckBufferForEnhancedImage(self, data): - """Adds data to a look buffer and checks to see for enhanced EC image. - - The EC's console task prints a string upon initialization which says that - "Console is enabled; type HELP for help.". The enhanced EC images print a - different string as a part of their init. This function searches through a - "look" buffer, scanning for the presence of either of those strings and - updating the enhanced_ec state accordingly. +def StartLoop(console, command_active, shutdown_pipe=None): + """Starts the infinite loop of console processing. Args: - data: A string containing the data sent from the interpreter. + console: A Console object that has been properly initialzed. + command_active: ctypes data object or multiprocessing.Value indicating if + servod owns the console, or user owns the console. This prevents input + collisions. + shutdown_pipe: A file object for a pipe or equivalent that becomes readable + (not blocked) to indicate that the loop should exit. Can be None to never + exit the loop. """ - self.look_buffer += data - - # Search the buffer for any of the EC image strings. - enhanced_match = re.search(ENHANCED_IMAGE_RE, self.look_buffer) - non_enhanced_match = re.search(NON_ENHANCED_IMAGE_RE, self.look_buffer) - - # Update the state if any matches were found. - if enhanced_match or non_enhanced_match: - if enhanced_match: - self.enhanced_ec = True - elif non_enhanced_match: - self.enhanced_ec = False - - # Inform the interpreter of the result. - self.cmd_pipe.send(b'enhanced ' + str(self.enhanced_ec).encode('ascii')) - self.logger.debug('Enhanced EC image? %r', self.enhanced_ec) - - # Clear look buffer since a match was found. - self.look_buffer = b'' - - # Move the sliding window. - self.look_buffer = self.look_buffer[-LOOK_BUFFER_SIZE:] - - -def CanonicalizeTimeString(timestr): - """Canonicalize the timestamp string. - - Args: - timestr: A timestamp string ended with 6 digits msec. - - Returns: - A string with 3 digits msec and an extra space. - """ - return timestr[:-3].encode('ascii') + b' ' - - -def IsPrintable(byte): - """Determines if a byte is printable. - - Args: - byte: An integer potentially representing a printable character. - - Returns: - A boolean indicating whether the byte is a printable character. - """ - return byte >= ord(' ') and byte <= ord('~') - - -def StartLoop(console, command_active, shutdown_pipe=None): - """Starts the infinite loop of console processing. - - Args: - console: A Console object that has been properly initialzed. - command_active: ctypes data object or multiprocessing.Value indicating if - servod owns the console, or user owns the console. This prevents input - collisions. - shutdown_pipe: A file object for a pipe or equivalent that becomes readable - (not blocked) to indicate that the loop should exit. Can be None to never - exit the loop. - """ - try: - console.logger.debug('Console is being served on %s.', console.user_pty) - console.logger.debug('Console controller is on %s.', console.controller_pty) - console.logger.debug('Command interface is being served on %s.', - console.interface_pty) - console.logger.debug(console) - - # This checks for HUP to indicate if the user has connected to the pty. - ep = select.epoll() - ep.register(console.controller_pty, select.EPOLLHUP) - - # This is used instead of "break" to avoid exiting the loop in the middle of - # an iteration. - continue_looping = True - - # Used for determining when to print host timestamps - tm_req = True - - while continue_looping: - # Check to see if pts is connected to anything - events = ep.poll(0) - controller_connected = not events - - # Check to see if pipes or the console are ready for reading. - read_list = [console.interface_pty, - console.cmd_pipe, console.dbg_pipe] - if controller_connected: - read_list.append(console.controller_pty) - if shutdown_pipe is not None: - read_list.append(shutdown_pipe) - - # Check if any input is ready, or wait for .1 sec and re-poll if - # a user has connected to the pts. - select_output = select.select(read_list, [], [], .1) - if not select_output: - continue - ready_for_reading = select_output[0] - - for obj in ready_for_reading: - if obj is console.controller_pty: - if not command_active.value: - # Convert to bytes so we can look for non-printable chars such as - # Ctrl+A, Ctrl+E, etc. - try: - line = bytearray(os.read(console.controller_pty, CONSOLE_MAX_READ)) - console.logger.debug('Input from user: %s, locked:%s', - str(line).strip(), command_active.value) - for i in line: - try: - # Handle each character as it arrives. - console.HandleChar(i) - except EOFError: - console.logger.debug( - 'ec3po console received EOF from dbg_pipe in HandleChar()' - ' while reading console.controller_pty') - continue_looping = False - break - except OSError: - console.logger.debug('Ptm read failed, probably user disconnect.') - - elif obj is console.interface_pty: - if command_active.value: - # Convert to bytes so we can look for non-printable chars such as - # Ctrl+A, Ctrl+E, etc. - line = bytearray(os.read(console.interface_pty, CONSOLE_MAX_READ)) - console.logger.debug('Input from interface: %s, locked:%s', - str(line).strip(), command_active.value) - for i in line: - try: - # Handle each character as it arrives. - console.HandleChar(i) - except EOFError: - console.logger.debug( - 'ec3po console received EOF from dbg_pipe in HandleChar()' - ' while reading console.interface_pty') - continue_looping = False - break - - elif obj is console.cmd_pipe: - try: - data = console.cmd_pipe.recv() - except EOFError: - console.logger.debug('ec3po console received EOF from cmd_pipe') - continue_looping = False - else: - # Write it to the user console. - if console.raw_debug: - console.logger.debug('|CMD|-%s->%r', - ('u' if controller_connected else '') + - ('i' if command_active.value else ''), - data.strip()) + try: + console.logger.debug("Console is being served on %s.", console.user_pty) + console.logger.debug("Console controller is on %s.", console.controller_pty) + console.logger.debug( + "Command interface is being served on %s.", console.interface_pty + ) + console.logger.debug(console) + + # This checks for HUP to indicate if the user has connected to the pty. + ep = select.epoll() + ep.register(console.controller_pty, select.EPOLLHUP) + + # This is used instead of "break" to avoid exiting the loop in the middle of + # an iteration. + continue_looping = True + + # Used for determining when to print host timestamps + tm_req = True + + while continue_looping: + # Check to see if pts is connected to anything + events = ep.poll(0) + controller_connected = not events + + # Check to see if pipes or the console are ready for reading. + read_list = [console.interface_pty, console.cmd_pipe, console.dbg_pipe] if controller_connected: - os.write(console.controller_pty, data) - if command_active.value: - os.write(console.interface_pty, data) - - elif obj is console.dbg_pipe: - try: - data = console.dbg_pipe.recv() - except EOFError: - console.logger.debug('ec3po console received EOF from dbg_pipe') - continue_looping = False - else: - if console.interrogation_mode == b'auto': - # Search look buffer for enhanced EC image string. - console.CheckBufferForEnhancedImage(data) - # Write it to the user console. - if len(data) > 1 and console.raw_debug: - console.logger.debug('|DBG|-%s->%r', - ('u' if controller_connected else '') + - ('i' if command_active.value else ''), - data.strip()) - console.LogConsoleOutput(data) - if controller_connected: - end = len(data) - 1 - if console.timestamp_enabled: - # A timestamp is required at the beginning of this line - if tm_req is True: - now = datetime.now() - tm = CanonicalizeTimeString(now.strftime(HOST_STRFTIME)) - os.write(console.controller_pty, tm) - tm_req = False - - # Insert timestamps into the middle where appropriate - # except if the last character is a newline - nls_found = data.count(b'\n', 0, end) - now = datetime.now() - tm = CanonicalizeTimeString(now.strftime('\n' + HOST_STRFTIME)) - data_tm = data.replace(b'\n', tm, nls_found) - else: - data_tm = data - - # timestamp required on next input - if data[end] == b'\n'[0]: - tm_req = True - os.write(console.controller_pty, data_tm) - if command_active.value: - os.write(console.interface_pty, data) - - elif obj is shutdown_pipe: - console.logger.debug( - 'ec3po console received shutdown pipe unblocked notification') - continue_looping = False - - while not console.oobm_queue.empty(): - console.logger.debug('OOBM queue ready for reading.') - console.ProcessOOBMQueue() - - except KeyboardInterrupt: - pass - - finally: - ep.unregister(console.controller_pty) - console.dbg_pipe.close() - console.cmd_pipe.close() - os.close(console.controller_pty) - os.close(console.interface_pty) - if shutdown_pipe is not None: - shutdown_pipe.close() - console.logger.debug('Exit ec3po console loop for %s', console.user_pty) + read_list.append(console.controller_pty) + if shutdown_pipe is not None: + read_list.append(shutdown_pipe) + + # Check if any input is ready, or wait for .1 sec and re-poll if + # a user has connected to the pts. + select_output = select.select(read_list, [], [], 0.1) + if not select_output: + continue + ready_for_reading = select_output[0] + + for obj in ready_for_reading: + if obj is console.controller_pty: + if not command_active.value: + # Convert to bytes so we can look for non-printable chars such as + # Ctrl+A, Ctrl+E, etc. + try: + line = bytearray( + os.read(console.controller_pty, CONSOLE_MAX_READ) + ) + console.logger.debug( + "Input from user: %s, locked:%s", + str(line).strip(), + command_active.value, + ) + for i in line: + try: + # Handle each character as it arrives. + console.HandleChar(i) + except EOFError: + console.logger.debug( + "ec3po console received EOF from dbg_pipe in HandleChar()" + " while reading console.controller_pty" + ) + continue_looping = False + break + except OSError: + console.logger.debug( + "Ptm read failed, probably user disconnect." + ) + + elif obj is console.interface_pty: + if command_active.value: + # Convert to bytes so we can look for non-printable chars such as + # Ctrl+A, Ctrl+E, etc. + line = bytearray( + os.read(console.interface_pty, CONSOLE_MAX_READ) + ) + console.logger.debug( + "Input from interface: %s, locked:%s", + str(line).strip(), + command_active.value, + ) + for i in line: + try: + # Handle each character as it arrives. + console.HandleChar(i) + except EOFError: + console.logger.debug( + "ec3po console received EOF from dbg_pipe in HandleChar()" + " while reading console.interface_pty" + ) + continue_looping = False + break + + elif obj is console.cmd_pipe: + try: + data = console.cmd_pipe.recv() + except EOFError: + console.logger.debug("ec3po console received EOF from cmd_pipe") + continue_looping = False + else: + # Write it to the user console. + if console.raw_debug: + console.logger.debug( + "|CMD|-%s->%r", + ("u" if controller_connected else "") + + ("i" if command_active.value else ""), + data.strip(), + ) + if controller_connected: + os.write(console.controller_pty, data) + if command_active.value: + os.write(console.interface_pty, data) + + elif obj is console.dbg_pipe: + try: + data = console.dbg_pipe.recv() + except EOFError: + console.logger.debug("ec3po console received EOF from dbg_pipe") + continue_looping = False + else: + if console.interrogation_mode == b"auto": + # Search look buffer for enhanced EC image string. + console.CheckBufferForEnhancedImage(data) + # Write it to the user console. + if len(data) > 1 and console.raw_debug: + console.logger.debug( + "|DBG|-%s->%r", + ("u" if controller_connected else "") + + ("i" if command_active.value else ""), + data.strip(), + ) + console.LogConsoleOutput(data) + if controller_connected: + end = len(data) - 1 + if console.timestamp_enabled: + # A timestamp is required at the beginning of this line + if tm_req is True: + now = datetime.now() + tm = CanonicalizeTimeString( + now.strftime(HOST_STRFTIME) + ) + os.write(console.controller_pty, tm) + tm_req = False + + # Insert timestamps into the middle where appropriate + # except if the last character is a newline + nls_found = data.count(b"\n", 0, end) + now = datetime.now() + tm = CanonicalizeTimeString( + now.strftime("\n" + HOST_STRFTIME) + ) + data_tm = data.replace(b"\n", tm, nls_found) + else: + data_tm = data + + # timestamp required on next input + if data[end] == b"\n"[0]: + tm_req = True + os.write(console.controller_pty, data_tm) + if command_active.value: + os.write(console.interface_pty, data) + + elif obj is shutdown_pipe: + console.logger.debug( + "ec3po console received shutdown pipe unblocked notification" + ) + continue_looping = False + + while not console.oobm_queue.empty(): + console.logger.debug("OOBM queue ready for reading.") + console.ProcessOOBMQueue() + + except KeyboardInterrupt: + pass + + finally: + ep.unregister(console.controller_pty) + console.dbg_pipe.close() + console.cmd_pipe.close() + os.close(console.controller_pty) + os.close(console.interface_pty) + if shutdown_pipe is not None: + shutdown_pipe.close() + console.logger.debug("Exit ec3po console loop for %s", console.user_pty) def main(argv): - """Kicks off the EC-3PO interactive console interface and interpreter. - - We create some pipes to communicate with an interpreter, instantiate an - interpreter, create a PTY pair, and begin serving the console interface. - - Args: - argv: A list of strings containing the arguments this module was called - with. - """ - # Set up argument parser. - parser = argparse.ArgumentParser(description=('Start interactive EC console ' - 'and interpreter.')) - parser.add_argument('ec_uart_pty', - help=('The full PTY name that the EC UART' - ' is present on. eg: /dev/pts/12')) - parser.add_argument('--log-level', - default='info', - help='info, debug, warning, error, or critical') - - # Parse arguments. - opts = parser.parse_args(argv) - - # Set logging level. - opts.log_level = opts.log_level.lower() - if opts.log_level == 'info': - log_level = logging.INFO - elif opts.log_level == 'debug': - log_level = logging.DEBUG - elif opts.log_level == 'warning': - log_level = logging.WARNING - elif opts.log_level == 'error': - log_level = logging.ERROR - elif opts.log_level == 'critical': - log_level = logging.CRITICAL - else: - parser.error('Invalid log level. (info, debug, warning, error, critical)') - - # Start logging with a timestamp, module, and log level shown in each log - # entry. - logging.basicConfig(level=log_level, format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - - # Create some pipes to communicate between the interpreter and the console. - # The command pipe is bidirectional. - cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe() - # The debug pipe is unidirectional from interpreter to console only. - dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False) - - # Create an interpreter instance. - itpr = interpreter.Interpreter(opts.ec_uart_pty, cmd_pipe_interp, - dbg_pipe_interp, log_level) - - # Spawn an interpreter process. - itpr_process = threadproc_shim.ThreadOrProcess( - target=interpreter.StartLoop, args=(itpr,)) - # Make sure to kill the interpreter when we terminate. - itpr_process.daemon = True - # Start the interpreter. - itpr_process.start() - - # Open a new pseudo-terminal pair - (controller_pty, user_pty) = pty.openpty() - # Set the permissions to 660. - os.chmod(os.ttyname(user_pty), (stat.S_IRGRP | stat.S_IWGRP | - stat.S_IRUSR | stat.S_IWUSR)) - # Create a console. - console = Console(controller_pty, os.ttyname(user_pty), cmd_pipe_interactive, - dbg_pipe_interactive) - # Start serving the console. - v = threadproc_shim.Value(ctypes.c_bool, False) - StartLoop(console, v) - - -if __name__ == '__main__': - main(sys.argv[1:]) + """Kicks off the EC-3PO interactive console interface and interpreter. + + We create some pipes to communicate with an interpreter, instantiate an + interpreter, create a PTY pair, and begin serving the console interface. + + Args: + argv: A list of strings containing the arguments this module was called + with. + """ + # Set up argument parser. + parser = argparse.ArgumentParser( + description=("Start interactive EC console " "and interpreter.") + ) + parser.add_argument( + "ec_uart_pty", + help=("The full PTY name that the EC UART" " is present on. eg: /dev/pts/12"), + ) + parser.add_argument( + "--log-level", default="info", help="info, debug, warning, error, or critical" + ) + + # Parse arguments. + opts = parser.parse_args(argv) + + # Set logging level. + opts.log_level = opts.log_level.lower() + if opts.log_level == "info": + log_level = logging.INFO + elif opts.log_level == "debug": + log_level = logging.DEBUG + elif opts.log_level == "warning": + log_level = logging.WARNING + elif opts.log_level == "error": + log_level = logging.ERROR + elif opts.log_level == "critical": + log_level = logging.CRITICAL + else: + parser.error("Invalid log level. (info, debug, warning, error, critical)") + + # Start logging with a timestamp, module, and log level shown in each log + # entry. + logging.basicConfig( + level=log_level, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + + # Create some pipes to communicate between the interpreter and the console. + # The command pipe is bidirectional. + cmd_pipe_interactive, cmd_pipe_interp = threadproc_shim.Pipe() + # The debug pipe is unidirectional from interpreter to console only. + dbg_pipe_interactive, dbg_pipe_interp = threadproc_shim.Pipe(duplex=False) + + # Create an interpreter instance. + itpr = interpreter.Interpreter( + opts.ec_uart_pty, cmd_pipe_interp, dbg_pipe_interp, log_level + ) + + # Spawn an interpreter process. + itpr_process = threadproc_shim.ThreadOrProcess( + target=interpreter.StartLoop, args=(itpr,) + ) + # Make sure to kill the interpreter when we terminate. + itpr_process.daemon = True + # Start the interpreter. + itpr_process.start() + + # Open a new pseudo-terminal pair + (controller_pty, user_pty) = pty.openpty() + # Set the permissions to 660. + os.chmod( + os.ttyname(user_pty), + (stat.S_IRGRP | stat.S_IWGRP | stat.S_IRUSR | stat.S_IWUSR), + ) + # Create a console. + console = Console( + controller_pty, os.ttyname(user_pty), cmd_pipe_interactive, dbg_pipe_interactive + ) + # Start serving the console. + v = threadproc_shim.Value(ctypes.c_bool, False) + StartLoop(console, v) + + +if __name__ == "__main__": + main(sys.argv[1:]) diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py index 7e341e7e8d..41ae324ef4 100755 --- a/util/ec3po/console_unittest.py +++ b/util/ec3po/console_unittest.py @@ -11,1262 +11,1310 @@ from __future__ import print_function import binascii import logging -import mock import tempfile import unittest +import mock import six - -from ec3po import console -from ec3po import interpreter -from ec3po import threadproc_shim +from ec3po import console, interpreter, threadproc_shim ESC_STRING = six.int2byte(console.ControlKey.ESC) + class Keys(object): - """A class that contains the escape sequences for special keys.""" - LEFT_ARROW = [console.ControlKey.ESC, ord('['), ord('D')] - RIGHT_ARROW = [console.ControlKey.ESC, ord('['), ord('C')] - UP_ARROW = [console.ControlKey.ESC, ord('['), ord('A')] - DOWN_ARROW = [console.ControlKey.ESC, ord('['), ord('B')] - HOME = [console.ControlKey.ESC, ord('['), ord('1'), ord('~')] - END = [console.ControlKey.ESC, ord('['), ord('8'), ord('~')] - DEL = [console.ControlKey.ESC, ord('['), ord('3'), ord('~')] + """A class that contains the escape sequences for special keys.""" + + LEFT_ARROW = [console.ControlKey.ESC, ord("["), ord("D")] + RIGHT_ARROW = [console.ControlKey.ESC, ord("["), ord("C")] + UP_ARROW = [console.ControlKey.ESC, ord("["), ord("A")] + DOWN_ARROW = [console.ControlKey.ESC, ord("["), ord("B")] + HOME = [console.ControlKey.ESC, ord("["), ord("1"), ord("~")] + END = [console.ControlKey.ESC, ord("["), ord("8"), ord("~")] + DEL = [console.ControlKey.ESC, ord("["), ord("3"), ord("~")] + class OutputStream(object): - """A class that has methods which return common console output.""" + """A class that has methods which return common console output.""" - @staticmethod - def MoveCursorLeft(count): - """Produces what would be printed to the console if the cursor moved left. + @staticmethod + def MoveCursorLeft(count): + """Produces what would be printed to the console if the cursor moved left. - Args: - count: An integer representing how many columns to move left. + Args: + count: An integer representing how many columns to move left. - Returns: - string: A string which contains what would be printed to the console if - the cursor moved left. - """ - string = ESC_STRING - string += b'[' + str(count).encode('ascii') + b'D' - return string + Returns: + string: A string which contains what would be printed to the console if + the cursor moved left. + """ + string = ESC_STRING + string += b"[" + str(count).encode("ascii") + b"D" + return string - @staticmethod - def MoveCursorRight(count): - """Produces what would be printed to the console if the cursor moved right. + @staticmethod + def MoveCursorRight(count): + """Produces what would be printed to the console if the cursor moved right. - Args: - count: An integer representing how many columns to move right. + Args: + count: An integer representing how many columns to move right. - Returns: - string: A string which contains what would be printed to the console if - the cursor moved right. - """ - string = ESC_STRING - string += b'[' + str(count).encode('ascii') + b'C' - return string + Returns: + string: A string which contains what would be printed to the console if + the cursor moved right. + """ + string = ESC_STRING + string += b"[" + str(count).encode("ascii") + b"C" + return string -BACKSPACE_STRING = b'' + +BACKSPACE_STRING = b"" # Move cursor left 1 column. BACKSPACE_STRING += OutputStream.MoveCursorLeft(1) # Write a space. -BACKSPACE_STRING += b' ' +BACKSPACE_STRING += b" " # Move cursor left 1 column. BACKSPACE_STRING += OutputStream.MoveCursorLeft(1) + def BytesToByteList(string): - """Converts a bytes string to list of bytes. + """Converts a bytes string to list of bytes. + + Args: + string: A literal bytes to turn into a list of bytes. - Args: - string: A literal bytes to turn into a list of bytes. + Returns: + A list of integers representing the byte value of each character in the + string. + """ + if six.PY3: + return [c for c in string] + return [ord(c) for c in string] - Returns: - A list of integers representing the byte value of each character in the - string. - """ - if six.PY3: - return [c for c in string] - return [ord(c) for c in string] def CheckConsoleOutput(test_case, exp_console_out): - """Verify what was sent out the console matches what we expect. + """Verify what was sent out the console matches what we expect. - Args: - test_case: A unittest.TestCase object representing the current unit test. - exp_console_out: A string representing the console output stream. - """ - # Read what was sent out the console. - test_case.tempfile.seek(0) - console_out = test_case.tempfile.read() + Args: + test_case: A unittest.TestCase object representing the current unit test. + exp_console_out: A string representing the console output stream. + """ + # Read what was sent out the console. + test_case.tempfile.seek(0) + console_out = test_case.tempfile.read() - test_case.assertEqual(exp_console_out, console_out) + test_case.assertEqual(exp_console_out, console_out) -def CheckInputBuffer(test_case, exp_input_buffer): - """Verify that the input buffer contains what we expect. - - Args: - test_case: A unittest.TestCase object representing the current unit test. - exp_input_buffer: A string containing the contents of the current input - buffer. - """ - test_case.assertEqual(exp_input_buffer, test_case.console.input_buffer, - (b'input buffer does not match expected.\n' - b'expected: |' + exp_input_buffer + b'|\n' - b'got: |' + test_case.console.input_buffer + - b'|\n' + str(test_case.console).encode('ascii'))) -def CheckInputBufferPosition(test_case, exp_pos): - """Verify the input buffer position. +def CheckInputBuffer(test_case, exp_input_buffer): + """Verify that the input buffer contains what we expect. - Args: - test_case: A unittest.TestCase object representing the current unit test. - exp_pos: An integer representing the expected input buffer position. - """ - test_case.assertEqual(exp_pos, test_case.console.input_buffer_pos, - 'input buffer position is incorrect.\ngot: ' + - str(test_case.console.input_buffer_pos) + '\nexp: ' + - str(exp_pos) + '\n' + str(test_case.console)) + Args: + test_case: A unittest.TestCase object representing the current unit test. + exp_input_buffer: A string containing the contents of the current input + buffer. + """ + test_case.assertEqual( + exp_input_buffer, + test_case.console.input_buffer, + ( + b"input buffer does not match expected.\n" + b"expected: |" + exp_input_buffer + b"|\n" + b"got: |" + + test_case.console.input_buffer + + b"|\n" + + str(test_case.console).encode("ascii") + ), + ) -def CheckHistoryBuffer(test_case, exp_history): - """Verify that the items in the history buffer are what we expect. - - Args: - test_case: A unittest.TestCase object representing the current unit test. - exp_history: A list of strings representing the expected contents of the - history buffer. - """ - # First, check to see if the length is what we expect. - test_case.assertEqual(len(exp_history), len(test_case.console.history), - ('The number of items in the history is unexpected.\n' - 'exp: ' + str(len(exp_history)) + '\n' - 'got: ' + str(len(test_case.console.history)) + '\n' - 'internal state:\n' + str(test_case.console))) - - # Next, check the actual contents of the history buffer. - for i in range(len(exp_history)): - test_case.assertEqual(exp_history[i], test_case.console.history[i], - (b'history buffer contents are incorrect.\n' - b'exp: ' + exp_history[i] + b'\n' - b'got: ' + test_case.console.history[i] + b'\n' - b'internal state:\n' + - str(test_case.console).encode('ascii'))) +def CheckInputBufferPosition(test_case, exp_pos): + """Verify the input buffer position. -class TestConsoleEditingMethods(unittest.TestCase): - """Test case to verify all console editing methods.""" - - def setUp(self): - """Setup the test harness.""" - # Setup logging with a timestamp, the module, and the log level. - logging.basicConfig(level=logging.DEBUG, - format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - - # Create a temp file and set both the controller and peripheral PTYs to the - # file to create a loopback. - self.tempfile = tempfile.TemporaryFile() - - # Create some mock pipes. These won't be used since we'll mock out sends - # to the interpreter. - mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe() - self.console = console.Console(self.tempfile.fileno(), self.tempfile, - tempfile.TemporaryFile(), - mock_pipe_end_0, mock_pipe_end_1, "EC") - - # Console editing methods are only valid for enhanced EC images, therefore - # we have to assume that the "EC" we're talking to is enhanced. By default, - # the console believes that the EC it's communicating with is NOT enhanced - # which is why we have to override it here. - self.console.enhanced_ec = True - self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True) - - def test_EnteringChars(self): - """Verify that characters are echoed onto the console.""" - test_str = b'abc' - input_stream = BytesToByteList(test_str) - - # Send the characters in. - for byte in input_stream: - self.console.HandleChar(byte) - - # Check the input position. - exp_pos = len(test_str) - CheckInputBufferPosition(self, exp_pos) - - # Verify that the input buffer is correct. - expected_buffer = test_str - CheckInputBuffer(self, expected_buffer) - - # Check console output - exp_console_out = test_str - CheckConsoleOutput(self, exp_console_out) - - def test_EnteringDeletingMoreCharsThanEntered(self): - """Verify that we can press backspace more than we have entered chars.""" - test_str = b'spamspam' - input_stream = BytesToByteList(test_str) - - # Send the characters in. - for byte in input_stream: - self.console.HandleChar(byte) - - # Now backspace 1 more than what we sent. - input_stream = [] - for _ in range(len(test_str) + 1): - input_stream.append(console.ControlKey.BACKSPACE) - - # Send that sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, verify that input buffer position is 0. - CheckInputBufferPosition(self, 0) - - # Next, examine the output stream for the correct sequence. - exp_console_out = test_str - for _ in range(len(test_str)): - exp_console_out += BACKSPACE_STRING - - # Now, verify that we got what we expected. - CheckConsoleOutput(self, exp_console_out) - - def test_EnteringMoreThanCharLimit(self): - """Verify that we drop characters when the line is too long.""" - test_str = self.console.line_limit * b'o' # All allowed. - test_str += 5 * b'x' # All should be dropped. - input_stream = BytesToByteList(test_str) - - # Send the characters in. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, we expect that input buffer position should be equal to the line - # limit. - exp_pos = self.console.line_limit - CheckInputBufferPosition(self, exp_pos) - - # The input buffer should only hold until the line limit. - exp_buffer = test_str[0:self.console.line_limit] - CheckInputBuffer(self, exp_buffer) - - # Lastly, check that the extra characters are not printed. - exp_console_out = exp_buffer - CheckConsoleOutput(self, exp_console_out) - - def test_ValidKeysOnLongLine(self): - """Verify that we can still press valid keys if the line is too long.""" - # Fill the line. - test_str = self.console.line_limit * b'o' - exp_console_out = test_str - # Try to fill it even more; these should all be dropped. - test_str += 5 * b'x' - input_stream = BytesToByteList(test_str) - - # We should be able to press the following keys: - # - Backspace - # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N - # - Delete - # - Home/CTRL+A - # - End/CTRL+E - # - Carriage Return - - # Backspace 1 character - input_stream.append(console.ControlKey.BACKSPACE) - exp_console_out += BACKSPACE_STRING - # Refill the line. - input_stream.extend(BytesToByteList(b'o')) - exp_console_out += b'o' - - # Left arrow key. - input_stream.extend(Keys.LEFT_ARROW) - exp_console_out += OutputStream.MoveCursorLeft(1) - - # Right arrow key. - input_stream.extend(Keys.RIGHT_ARROW) - exp_console_out += OutputStream.MoveCursorRight(1) - - # CTRL+B - input_stream.append(console.ControlKey.CTRL_B) - exp_console_out += OutputStream.MoveCursorLeft(1) - - # CTRL+F - input_stream.append(console.ControlKey.CTRL_F) - exp_console_out += OutputStream.MoveCursorRight(1) - - # Let's press enter now so we can test up and down. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - exp_console_out += b'\r\n' + self.console.prompt - - # Up arrow key. - input_stream.extend(Keys.UP_ARROW) - exp_console_out += test_str[:self.console.line_limit] - - # Down arrow key. - input_stream.extend(Keys.DOWN_ARROW) - # Since the line was blank, we have to backspace the entire line. - exp_console_out += self.console.line_limit * BACKSPACE_STRING - - # CTRL+P - input_stream.append(console.ControlKey.CTRL_P) - exp_console_out += test_str[:self.console.line_limit] - - # CTRL+N - input_stream.append(console.ControlKey.CTRL_N) - # Since the line was blank, we have to backspace the entire line. - exp_console_out += self.console.line_limit * BACKSPACE_STRING - - # Press the Up arrow key to reprint the long line. - input_stream.extend(Keys.UP_ARROW) - exp_console_out += test_str[:self.console.line_limit] - - # Press the Home key to jump to the beginning of the line. - input_stream.extend(Keys.HOME) - exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit) - - # Press the End key to jump to the end of the line. - input_stream.extend(Keys.END) - exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit) - - # Press CTRL+A to jump to the beginning of the line. - input_stream.append(console.ControlKey.CTRL_A) - exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit) - - # Press CTRL+E to jump to the end of the line. - input_stream.extend(Keys.END) - exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit) - - # Move left one column so we can delete a character. - input_stream.extend(Keys.LEFT_ARROW) - exp_console_out += OutputStream.MoveCursorLeft(1) - - # Press the delete key. - input_stream.extend(Keys.DEL) - # This should look like a space, and then move cursor left 1 column since - # we're at the end of line. - exp_console_out += b' ' + OutputStream.MoveCursorLeft(1) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify everything happened correctly. - CheckConsoleOutput(self, exp_console_out) - - def test_BackspaceOnEmptyLine(self): - """Verify that we can backspace on an empty line with no bad effects.""" - # Send a single backspace. - test_str = [console.ControlKey.BACKSPACE] - - # Send the characters in. - for byte in test_str: - self.console.HandleChar(byte) - - # Check the input position. - exp_pos = 0 - CheckInputBufferPosition(self, exp_pos) - - # Check that buffer is empty. - exp_input_buffer = b'' - CheckInputBuffer(self, exp_input_buffer) - - # Check that the console output is empty. - exp_console_out = b'' - CheckConsoleOutput(self, exp_console_out) - - def test_BackspaceWithinLine(self): - """Verify that we shift the chars over when backspacing within a line.""" - # Misspell 'help' - test_str = b'heelp' - input_stream = BytesToByteList(test_str) - # Use the arrow key to go back to fix it. - # Move cursor left 1 column. - input_stream.extend(2*Keys.LEFT_ARROW) - # Backspace once to remove the extra 'e'. - input_stream.append(console.ControlKey.BACKSPACE) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify the input buffer - exp_input_buffer = b'help' - CheckInputBuffer(self, exp_input_buffer) - - # Verify the input buffer position. It should be at 2 (cursor over the 'l') - CheckInputBufferPosition(self, 2) - - # We expect the console output to be the test string, with two moves to the - # left, another move left, and then the rest of the line followed by a - # space. - exp_console_out = test_str - exp_console_out += 2 * OutputStream.MoveCursorLeft(1) - - # Move cursor left 1 column. - exp_console_out += OutputStream.MoveCursorLeft(1) - # Rest of the line and a space. (test_str in this case) - exp_console_out += b'lp ' - # Reset the cursor 2 + 1 to the left. - exp_console_out += OutputStream.MoveCursorLeft(3) - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - def test_JumpToBeginningOfLineViaCtrlA(self): - """Verify that we can jump to the beginning of a line with Ctrl+A.""" - # Enter some chars and press CTRL+A - test_str = b'abc' - input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A] - - # Send the characters in. - for byte in input_stream: - self.console.HandleChar(byte) - - # We expect to see our test string followed by a move cursor left. - exp_console_out = test_str - exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) - - # Check to see what whas printed on the console. - CheckConsoleOutput(self, exp_console_out) - - # Check that the input buffer position is now 0. - CheckInputBufferPosition(self, 0) - - # Check input buffer still contains our test string. - CheckInputBuffer(self, test_str) - - def test_JumpToBeginningOfLineViaHomeKey(self): - """Jump to beginning of line via HOME key.""" - test_str = b'version' - input_stream = BytesToByteList(test_str) - input_stream.extend(Keys.HOME) - - # Send out the stream. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, verify that input buffer position is now 0. - CheckInputBufferPosition(self, 0) - - # Next, verify that the input buffer did not change. - CheckInputBuffer(self, test_str) - - # Lastly, check that the cursor moved correctly. - exp_console_out = test_str - exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) - CheckConsoleOutput(self, exp_console_out) - - def test_JumpToEndOfLineViaEndKey(self): - """Jump to the end of the line using the END key.""" - test_str = b'version' - input_stream = BytesToByteList(test_str) - input_stream += [console.ControlKey.CTRL_A] - # Now, jump to the end of the line. - input_stream.extend(Keys.END) - - # Send out the stream. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the input buffer position is correct. This should be at the - # end of the test string. - CheckInputBufferPosition(self, len(test_str)) - - # The expected output should be the test string, followed by a jump to the - # beginning of the line, and lastly a jump to the end of the line. - exp_console_out = test_str - exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) - # Now the jump back to the end of the line. - exp_console_out += OutputStream.MoveCursorRight(len(test_str)) - - # Verify console output stream. - CheckConsoleOutput(self, exp_console_out) - - def test_JumpToEndOfLineViaCtrlE(self): - """Enter some chars and then try to jump to the end. (Should be a no-op)""" - test_str = b'sysinfo' - input_stream = BytesToByteList(test_str) - input_stream.append(console.ControlKey.CTRL_E) - - # Send out the stream - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the input buffer position isn't any further than we expect. - # At this point, the position should be at the end of the test string. - CheckInputBufferPosition(self, len(test_str)) - - # Now, let's try to jump to the beginning and then jump back to the end. - input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E] - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Perform the same verification. - CheckInputBufferPosition(self, len(test_str)) - - # Lastly try to jump again, beyond the end. - input_stream = [console.ControlKey.CTRL_E] - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Perform the same verification. - CheckInputBufferPosition(self, len(test_str)) - - # We expect to see the test string, a jump to the beginning of the line, and - # one jump to the end of the line. - exp_console_out = test_str - # Jump to beginning. - exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) - # Jump back to end. - exp_console_out += OutputStream.MoveCursorRight(len(test_str)) - - # Verify the console output. - CheckConsoleOutput(self, exp_console_out) - - def test_MoveLeftWithArrowKey(self): - """Move cursor left one column with arrow key.""" - test_str = b'tastyspam' - input_stream = BytesToByteList(test_str) - input_stream.extend(Keys.LEFT_ARROW) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the input buffer position is 1 less than the length. - CheckInputBufferPosition(self, len(test_str) - 1) - - # Also, verify that the input buffer is not modified. - CheckInputBuffer(self, test_str) - - # We expect the test string, followed by a one column move left. - exp_console_out = test_str + OutputStream.MoveCursorLeft(1) - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - def test_MoveLeftWithCtrlB(self): - """Move cursor back one column with Ctrl+B.""" - test_str = b'tastyspam' - input_stream = BytesToByteList(test_str) - input_stream.append(console.ControlKey.CTRL_B) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the input buffer position is 1 less than the length. - CheckInputBufferPosition(self, len(test_str) - 1) + Args: + test_case: A unittest.TestCase object representing the current unit test. + exp_pos: An integer representing the expected input buffer position. + """ + test_case.assertEqual( + exp_pos, + test_case.console.input_buffer_pos, + "input buffer position is incorrect.\ngot: " + + str(test_case.console.input_buffer_pos) + + "\nexp: " + + str(exp_pos) + + "\n" + + str(test_case.console), + ) - # Also, verify that the input buffer is not modified. - CheckInputBuffer(self, test_str) - # We expect the test string, followed by a one column move left. - exp_console_out = test_str + OutputStream.MoveCursorLeft(1) +def CheckHistoryBuffer(test_case, exp_history): + """Verify that the items in the history buffer are what we expect. - # Verify console output. - CheckConsoleOutput(self, exp_console_out) + Args: + test_case: A unittest.TestCase object representing the current unit test. + exp_history: A list of strings representing the expected contents of the + history buffer. + """ + # First, check to see if the length is what we expect. + test_case.assertEqual( + len(exp_history), + len(test_case.console.history), + ( + "The number of items in the history is unexpected.\n" + "exp: " + str(len(exp_history)) + "\n" + "got: " + str(len(test_case.console.history)) + "\n" + "internal state:\n" + str(test_case.console) + ), + ) + + # Next, check the actual contents of the history buffer. + for i in range(len(exp_history)): + test_case.assertEqual( + exp_history[i], + test_case.console.history[i], + ( + b"history buffer contents are incorrect.\n" + b"exp: " + exp_history[i] + b"\n" + b"got: " + test_case.console.history[i] + b"\n" + b"internal state:\n" + str(test_case.console).encode("ascii") + ), + ) - def test_MoveRightWithArrowKey(self): - """Move cursor one column to the right with the arrow key.""" - test_str = b'version' - input_stream = BytesToByteList(test_str) - # Jump to beginning of line. - input_stream.append(console.ControlKey.CTRL_A) - # Press right arrow key. - input_stream.extend(Keys.RIGHT_ARROW) - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) +class TestConsoleEditingMethods(unittest.TestCase): + """Test case to verify all console editing methods.""" + + def setUp(self): + """Setup the test harness.""" + # Setup logging with a timestamp, the module, and the log level. + logging.basicConfig( + level=logging.DEBUG, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + + # Create a temp file and set both the controller and peripheral PTYs to the + # file to create a loopback. + self.tempfile = tempfile.TemporaryFile() + + # Create some mock pipes. These won't be used since we'll mock out sends + # to the interpreter. + mock_pipe_end_0, mock_pipe_end_1 = threadproc_shim.Pipe() + self.console = console.Console( + self.tempfile.fileno(), + self.tempfile, + tempfile.TemporaryFile(), + mock_pipe_end_0, + mock_pipe_end_1, + "EC", + ) + + # Console editing methods are only valid for enhanced EC images, therefore + # we have to assume that the "EC" we're talking to is enhanced. By default, + # the console believes that the EC it's communicating with is NOT enhanced + # which is why we have to override it here. + self.console.enhanced_ec = True + self.console.CheckForEnhancedECImage = mock.MagicMock(return_value=True) + + def test_EnteringChars(self): + """Verify that characters are echoed onto the console.""" + test_str = b"abc" + input_stream = BytesToByteList(test_str) + + # Send the characters in. + for byte in input_stream: + self.console.HandleChar(byte) + + # Check the input position. + exp_pos = len(test_str) + CheckInputBufferPosition(self, exp_pos) + + # Verify that the input buffer is correct. + expected_buffer = test_str + CheckInputBuffer(self, expected_buffer) + + # Check console output + exp_console_out = test_str + CheckConsoleOutput(self, exp_console_out) + + def test_EnteringDeletingMoreCharsThanEntered(self): + """Verify that we can press backspace more than we have entered chars.""" + test_str = b"spamspam" + input_stream = BytesToByteList(test_str) + + # Send the characters in. + for byte in input_stream: + self.console.HandleChar(byte) + + # Now backspace 1 more than what we sent. + input_stream = [] + for _ in range(len(test_str) + 1): + input_stream.append(console.ControlKey.BACKSPACE) + + # Send that sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, verify that input buffer position is 0. + CheckInputBufferPosition(self, 0) + + # Next, examine the output stream for the correct sequence. + exp_console_out = test_str + for _ in range(len(test_str)): + exp_console_out += BACKSPACE_STRING + + # Now, verify that we got what we expected. + CheckConsoleOutput(self, exp_console_out) + + def test_EnteringMoreThanCharLimit(self): + """Verify that we drop characters when the line is too long.""" + test_str = self.console.line_limit * b"o" # All allowed. + test_str += 5 * b"x" # All should be dropped. + input_stream = BytesToByteList(test_str) + + # Send the characters in. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, we expect that input buffer position should be equal to the line + # limit. + exp_pos = self.console.line_limit + CheckInputBufferPosition(self, exp_pos) + + # The input buffer should only hold until the line limit. + exp_buffer = test_str[0 : self.console.line_limit] + CheckInputBuffer(self, exp_buffer) + + # Lastly, check that the extra characters are not printed. + exp_console_out = exp_buffer + CheckConsoleOutput(self, exp_console_out) + + def test_ValidKeysOnLongLine(self): + """Verify that we can still press valid keys if the line is too long.""" + # Fill the line. + test_str = self.console.line_limit * b"o" + exp_console_out = test_str + # Try to fill it even more; these should all be dropped. + test_str += 5 * b"x" + input_stream = BytesToByteList(test_str) + + # We should be able to press the following keys: + # - Backspace + # - Arrow Keys/CTRL+B/CTRL+F/CTRL+P/CTRL+N + # - Delete + # - Home/CTRL+A + # - End/CTRL+E + # - Carriage Return + + # Backspace 1 character + input_stream.append(console.ControlKey.BACKSPACE) + exp_console_out += BACKSPACE_STRING + # Refill the line. + input_stream.extend(BytesToByteList(b"o")) + exp_console_out += b"o" + + # Left arrow key. + input_stream.extend(Keys.LEFT_ARROW) + exp_console_out += OutputStream.MoveCursorLeft(1) + + # Right arrow key. + input_stream.extend(Keys.RIGHT_ARROW) + exp_console_out += OutputStream.MoveCursorRight(1) + + # CTRL+B + input_stream.append(console.ControlKey.CTRL_B) + exp_console_out += OutputStream.MoveCursorLeft(1) + + # CTRL+F + input_stream.append(console.ControlKey.CTRL_F) + exp_console_out += OutputStream.MoveCursorRight(1) + + # Let's press enter now so we can test up and down. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + exp_console_out += b"\r\n" + self.console.prompt + + # Up arrow key. + input_stream.extend(Keys.UP_ARROW) + exp_console_out += test_str[: self.console.line_limit] + + # Down arrow key. + input_stream.extend(Keys.DOWN_ARROW) + # Since the line was blank, we have to backspace the entire line. + exp_console_out += self.console.line_limit * BACKSPACE_STRING + + # CTRL+P + input_stream.append(console.ControlKey.CTRL_P) + exp_console_out += test_str[: self.console.line_limit] + + # CTRL+N + input_stream.append(console.ControlKey.CTRL_N) + # Since the line was blank, we have to backspace the entire line. + exp_console_out += self.console.line_limit * BACKSPACE_STRING + + # Press the Up arrow key to reprint the long line. + input_stream.extend(Keys.UP_ARROW) + exp_console_out += test_str[: self.console.line_limit] + + # Press the Home key to jump to the beginning of the line. + input_stream.extend(Keys.HOME) + exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit) + + # Press the End key to jump to the end of the line. + input_stream.extend(Keys.END) + exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit) + + # Press CTRL+A to jump to the beginning of the line. + input_stream.append(console.ControlKey.CTRL_A) + exp_console_out += OutputStream.MoveCursorLeft(self.console.line_limit) + + # Press CTRL+E to jump to the end of the line. + input_stream.extend(Keys.END) + exp_console_out += OutputStream.MoveCursorRight(self.console.line_limit) + + # Move left one column so we can delete a character. + input_stream.extend(Keys.LEFT_ARROW) + exp_console_out += OutputStream.MoveCursorLeft(1) + + # Press the delete key. + input_stream.extend(Keys.DEL) + # This should look like a space, and then move cursor left 1 column since + # we're at the end of line. + exp_console_out += b" " + OutputStream.MoveCursorLeft(1) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify everything happened correctly. + CheckConsoleOutput(self, exp_console_out) + + def test_BackspaceOnEmptyLine(self): + """Verify that we can backspace on an empty line with no bad effects.""" + # Send a single backspace. + test_str = [console.ControlKey.BACKSPACE] + + # Send the characters in. + for byte in test_str: + self.console.HandleChar(byte) + + # Check the input position. + exp_pos = 0 + CheckInputBufferPosition(self, exp_pos) + + # Check that buffer is empty. + exp_input_buffer = b"" + CheckInputBuffer(self, exp_input_buffer) + + # Check that the console output is empty. + exp_console_out = b"" + CheckConsoleOutput(self, exp_console_out) + + def test_BackspaceWithinLine(self): + """Verify that we shift the chars over when backspacing within a line.""" + # Misspell 'help' + test_str = b"heelp" + input_stream = BytesToByteList(test_str) + # Use the arrow key to go back to fix it. + # Move cursor left 1 column. + input_stream.extend(2 * Keys.LEFT_ARROW) + # Backspace once to remove the extra 'e'. + input_stream.append(console.ControlKey.BACKSPACE) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify the input buffer + exp_input_buffer = b"help" + CheckInputBuffer(self, exp_input_buffer) + + # Verify the input buffer position. It should be at 2 (cursor over the 'l') + CheckInputBufferPosition(self, 2) + + # We expect the console output to be the test string, with two moves to the + # left, another move left, and then the rest of the line followed by a + # space. + exp_console_out = test_str + exp_console_out += 2 * OutputStream.MoveCursorLeft(1) + + # Move cursor left 1 column. + exp_console_out += OutputStream.MoveCursorLeft(1) + # Rest of the line and a space. (test_str in this case) + exp_console_out += b"lp " + # Reset the cursor 2 + 1 to the left. + exp_console_out += OutputStream.MoveCursorLeft(3) + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + def test_JumpToBeginningOfLineViaCtrlA(self): + """Verify that we can jump to the beginning of a line with Ctrl+A.""" + # Enter some chars and press CTRL+A + test_str = b"abc" + input_stream = BytesToByteList(test_str) + [console.ControlKey.CTRL_A] + + # Send the characters in. + for byte in input_stream: + self.console.HandleChar(byte) + + # We expect to see our test string followed by a move cursor left. + exp_console_out = test_str + exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) + + # Check to see what whas printed on the console. + CheckConsoleOutput(self, exp_console_out) + + # Check that the input buffer position is now 0. + CheckInputBufferPosition(self, 0) + + # Check input buffer still contains our test string. + CheckInputBuffer(self, test_str) + + def test_JumpToBeginningOfLineViaHomeKey(self): + """Jump to beginning of line via HOME key.""" + test_str = b"version" + input_stream = BytesToByteList(test_str) + input_stream.extend(Keys.HOME) + + # Send out the stream. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, verify that input buffer position is now 0. + CheckInputBufferPosition(self, 0) + + # Next, verify that the input buffer did not change. + CheckInputBuffer(self, test_str) + + # Lastly, check that the cursor moved correctly. + exp_console_out = test_str + exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) + CheckConsoleOutput(self, exp_console_out) + + def test_JumpToEndOfLineViaEndKey(self): + """Jump to the end of the line using the END key.""" + test_str = b"version" + input_stream = BytesToByteList(test_str) + input_stream += [console.ControlKey.CTRL_A] + # Now, jump to the end of the line. + input_stream.extend(Keys.END) + + # Send out the stream. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the input buffer position is correct. This should be at the + # end of the test string. + CheckInputBufferPosition(self, len(test_str)) + + # The expected output should be the test string, followed by a jump to the + # beginning of the line, and lastly a jump to the end of the line. + exp_console_out = test_str + exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) + # Now the jump back to the end of the line. + exp_console_out += OutputStream.MoveCursorRight(len(test_str)) + + # Verify console output stream. + CheckConsoleOutput(self, exp_console_out) + + def test_JumpToEndOfLineViaCtrlE(self): + """Enter some chars and then try to jump to the end. (Should be a no-op)""" + test_str = b"sysinfo" + input_stream = BytesToByteList(test_str) + input_stream.append(console.ControlKey.CTRL_E) + + # Send out the stream + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the input buffer position isn't any further than we expect. + # At this point, the position should be at the end of the test string. + CheckInputBufferPosition(self, len(test_str)) + + # Now, let's try to jump to the beginning and then jump back to the end. + input_stream = [console.ControlKey.CTRL_A, console.ControlKey.CTRL_E] + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Perform the same verification. + CheckInputBufferPosition(self, len(test_str)) + + # Lastly try to jump again, beyond the end. + input_stream = [console.ControlKey.CTRL_E] + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Perform the same verification. + CheckInputBufferPosition(self, len(test_str)) + + # We expect to see the test string, a jump to the beginning of the line, and + # one jump to the end of the line. + exp_console_out = test_str + # Jump to beginning. + exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) + # Jump back to end. + exp_console_out += OutputStream.MoveCursorRight(len(test_str)) + + # Verify the console output. + CheckConsoleOutput(self, exp_console_out) + + def test_MoveLeftWithArrowKey(self): + """Move cursor left one column with arrow key.""" + test_str = b"tastyspam" + input_stream = BytesToByteList(test_str) + input_stream.extend(Keys.LEFT_ARROW) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the input buffer position is 1 less than the length. + CheckInputBufferPosition(self, len(test_str) - 1) + + # Also, verify that the input buffer is not modified. + CheckInputBuffer(self, test_str) + + # We expect the test string, followed by a one column move left. + exp_console_out = test_str + OutputStream.MoveCursorLeft(1) + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + def test_MoveLeftWithCtrlB(self): + """Move cursor back one column with Ctrl+B.""" + test_str = b"tastyspam" + input_stream = BytesToByteList(test_str) + input_stream.append(console.ControlKey.CTRL_B) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the input buffer position is 1 less than the length. + CheckInputBufferPosition(self, len(test_str) - 1) - # Verify that the input buffer position is 1. - CheckInputBufferPosition(self, 1) + # Also, verify that the input buffer is not modified. + CheckInputBuffer(self, test_str) - # Also, verify that the input buffer is not modified. - CheckInputBuffer(self, test_str) + # We expect the test string, followed by a one column move left. + exp_console_out = test_str + OutputStream.MoveCursorLeft(1) - # We expect the test string, followed by a jump to the beginning of the - # line, and finally a move right 1. - exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str))) - - # A move right 1 column. - exp_console_out += OutputStream.MoveCursorRight(1) - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - def test_MoveRightWithCtrlF(self): - """Move cursor forward one column with Ctrl+F.""" - test_str = b'panicinfo' - input_stream = BytesToByteList(test_str) - input_stream.append(console.ControlKey.CTRL_A) - # Now, move right one column. - input_stream.append(console.ControlKey.CTRL_F) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the input buffer position is 1. - CheckInputBufferPosition(self, 1) - - # Also, verify that the input buffer is not modified. - CheckInputBuffer(self, test_str) - - # We expect the test string, followed by a jump to the beginning of the - # line, and finally a move right 1. - exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str))) - - # A move right 1 column. - exp_console_out += OutputStream.MoveCursorRight(1) - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - def test_ImpossibleMoveLeftWithArrowKey(self): - """Verify that we can't move left at the beginning of the line.""" - # We shouldn't be able to move left if we're at the beginning of the line. - input_stream = Keys.LEFT_ARROW - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Nothing should have been output. - exp_console_output = b'' - CheckConsoleOutput(self, exp_console_output) - - # The input buffer position should still be 0. - CheckInputBufferPosition(self, 0) - - # The input buffer itself should be empty. - CheckInputBuffer(self, b'') - - def test_ImpossibleMoveRightWithArrowKey(self): - """Verify that we can't move right at the end of the line.""" - # We shouldn't be able to move right if we're at the end of the line. - input_stream = Keys.RIGHT_ARROW - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Nothing should have been output. - exp_console_output = b'' - CheckConsoleOutput(self, exp_console_output) - - # The input buffer position should still be 0. - CheckInputBufferPosition(self, 0) - - # The input buffer itself should be empty. - CheckInputBuffer(self, b'') - - def test_KillEntireLine(self): - """Verify that we can kill an entire line with Ctrl+K.""" - test_str = b'accelinfo on' - input_stream = BytesToByteList(test_str) - # Jump to beginning of line and then kill it with Ctrl+K. - input_stream.extend([console.ControlKey.CTRL_A, console.ControlKey.CTRL_K]) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, we expect that the input buffer is empty. - CheckInputBuffer(self, b'') - - # The buffer position should be 0. - CheckInputBufferPosition(self, 0) - - # What we expect to see on the console stream should be the following. The - # test string, a jump to the beginning of the line, then jump back to the - # end of the line and replace the line with spaces. - exp_console_out = test_str - # Jump to beginning of line. - exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) - # Jump to end of line. - exp_console_out += OutputStream.MoveCursorRight(len(test_str)) - # Replace line with spaces, which looks like backspaces. - for _ in range(len(test_str)): - exp_console_out += BACKSPACE_STRING - - # Verify the console output. - CheckConsoleOutput(self, exp_console_out) - - def test_KillPartialLine(self): - """Verify that we can kill a portion of a line.""" - test_str = b'accelread 0 1' - input_stream = BytesToByteList(test_str) - len_to_kill = 5 - for _ in range(len_to_kill): - # Move cursor left - input_stream.extend(Keys.LEFT_ARROW) - # Now kill - input_stream.append(console.ControlKey.CTRL_K) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, check that the input buffer was truncated. - exp_input_buffer = test_str[:-len_to_kill] - CheckInputBuffer(self, exp_input_buffer) - - # Verify the input buffer position. - CheckInputBufferPosition(self, len(test_str) - len_to_kill) - - # The console output stream that we expect is the test string followed by a - # move left of len_to_kill, then a jump to the end of the line and backspace - # of len_to_kill. - exp_console_out = test_str - for _ in range(len_to_kill): - # Move left 1 column. - exp_console_out += OutputStream.MoveCursorLeft(1) - # Then jump to the end of the line - exp_console_out += OutputStream.MoveCursorRight(len_to_kill) - # Backspace of len_to_kill - for _ in range(len_to_kill): - exp_console_out += BACKSPACE_STRING - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - def test_InsertingCharacters(self): - """Verify that we can insert characters within the line.""" - test_str = b'accel 0 1' # Here we forgot the 'read' part in 'accelread' - input_stream = BytesToByteList(test_str) - # We need to move over to the 'l' and add read. - insertion_point = test_str.find(b'l') + 1 - for i in range(len(test_str) - insertion_point): - # Move cursor left. - input_stream.extend(Keys.LEFT_ARROW) - # Now, add in 'read' - added_str = b'read' - input_stream.extend(BytesToByteList(added_str)) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # First, verify that the input buffer is correct. - exp_input_buffer = test_str[:insertion_point] + added_str - exp_input_buffer += test_str[insertion_point:] - CheckInputBuffer(self, exp_input_buffer) - - # Verify that the input buffer position is correct. - exp_input_buffer_pos = insertion_point + len(added_str) - CheckInputBufferPosition(self, exp_input_buffer_pos) - - # The console output stream that we expect is the test string, followed by - # move cursor left until the 'l' was found, the added test string while - # shifting characters around. - exp_console_out = test_str - for i in range(len(test_str) - insertion_point): - # Move cursor left. - exp_console_out += OutputStream.MoveCursorLeft(1) - - # Now for each character, write the rest of the line will be shifted to the - # right one column. - for i in range(len(added_str)): - # Printed character. - exp_console_out += added_str[i:i+1] - # The rest of the line - exp_console_out += test_str[insertion_point:] - # Reset the cursor back left - reset_dist = len(test_str[insertion_point:]) - exp_console_out += OutputStream.MoveCursorLeft(reset_dist) - - # Verify the console output. - CheckConsoleOutput(self, exp_console_out) - - def test_StoreCommandHistory(self): - """Verify that entered commands are stored in the history.""" - test_commands = [] - test_commands.append(b'help') - test_commands.append(b'version') - test_commands.append(b'accelread 0 1') - input_stream = [] - for c in test_commands: - input_stream.extend(BytesToByteList(c)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # We expect to have the test commands in the history buffer. - exp_history_buf = test_commands - CheckHistoryBuffer(self, exp_history_buf) - - def test_CycleUpThruCommandHistory(self): - """Verify that the UP arrow key will print itmes in the history buffer.""" - # Enter some commands. - test_commands = [b'version', b'accelrange 0', b'battery', b'gettime'] - input_stream = [] - for command in test_commands: - input_stream.extend(BytesToByteList(command)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Now, hit the UP arrow key to print the previous entries. - for i in range(len(test_commands)): - input_stream.extend(Keys.UP_ARROW) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The expected output should be test commands with prompts printed in - # between, followed by line kills with the previous test commands printed. - exp_console_out = b'' - for i in range(len(test_commands)): - exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt - - # When we press up, the line should be cleared and print the previous buffer - # entry. - for i in range(len(test_commands)-1, 0, -1): - exp_console_out += test_commands[i] - # Backspace to the beginning. - for i in range(len(test_commands[i])): - exp_console_out += BACKSPACE_STRING + # Verify console output. + CheckConsoleOutput(self, exp_console_out) - # The last command should just be printed out with no backspacing. - exp_console_out += test_commands[0] - - # Now, verify. - CheckConsoleOutput(self, exp_console_out) - - def test_UpArrowOnEmptyHistory(self): - """Ensure nothing happens if the history is empty.""" - # Press the up arrow key twice. - input_stream = 2 * Keys.UP_ARROW - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # We expect nothing to have happened. - exp_console_out = b'' - exp_input_buffer = b'' - exp_input_buffer_pos = 0 - exp_history_buf = [] - - # Verify. - CheckConsoleOutput(self, exp_console_out) - CheckInputBufferPosition(self, exp_input_buffer_pos) - CheckInputBuffer(self, exp_input_buffer) - CheckHistoryBuffer(self, exp_history_buf) - - def test_UpArrowDoesNotGoOutOfBounds(self): - """Verify that pressing the up arrow many times won't go out of bounds.""" - # Enter one command. - test_str = b'help version' - input_stream = BytesToByteList(test_str) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - # Then press the up arrow key twice. - input_stream.extend(2 * Keys.UP_ARROW) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the history buffer is correct. - exp_history_buf = [test_str] - CheckHistoryBuffer(self, exp_history_buf) - - # We expect that the console output should only contain our entered command, - # a new prompt, and then our command aggain. - exp_console_out = test_str + b'\r\n' + self.console.prompt - # Pressing up should reprint the command we entered. - exp_console_out += test_str - - # Verify. - CheckConsoleOutput(self, exp_console_out) - - def test_CycleDownThruCommandHistory(self): - """Verify that we can select entries by hitting the down arrow.""" - # Enter at least 4 commands. - test_commands = [b'version', b'accelrange 0', b'battery', b'gettime'] - input_stream = [] - for command in test_commands: - input_stream.extend(BytesToByteList(command)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Now, hit the UP arrow key twice to print the previous two entries. - for i in range(2): - input_stream.extend(Keys.UP_ARROW) - - # Now, hit the DOWN arrow key twice to print the newer entries. - input_stream.extend(2*Keys.DOWN_ARROW) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The expected output should be commands that we entered, followed by - # prompts, then followed by our last two commands in reverse. Then, we - # should see the last entry in the list, followed by the saved partial cmd - # of a blank line. - exp_console_out = b'' - for i in range(len(test_commands)): - exp_console_out += test_commands[i] + b'\r\n' + self.console.prompt - - # When we press up, the line should be cleared and print the previous buffer - # entry. - for i in range(len(test_commands)-1, 1, -1): - exp_console_out += test_commands[i] - # Backspace to the beginning. - for i in range(len(test_commands[i])): - exp_console_out += BACKSPACE_STRING + def test_MoveRightWithArrowKey(self): + """Move cursor one column to the right with the arrow key.""" + test_str = b"version" + input_stream = BytesToByteList(test_str) + # Jump to beginning of line. + input_stream.append(console.ControlKey.CTRL_A) + # Press right arrow key. + input_stream.extend(Keys.RIGHT_ARROW) - # When we press down, it should have cleared the last command (which we - # covered with the previous for loop), and then prints the next command. - exp_console_out += test_commands[3] - for i in range(len(test_commands[3])): - exp_console_out += BACKSPACE_STRING - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - # Verify input buffer. - exp_input_buffer = b'' # Empty because our partial command was empty. - exp_input_buffer_pos = len(exp_input_buffer) - CheckInputBuffer(self, exp_input_buffer) - CheckInputBufferPosition(self, exp_input_buffer_pos) - - def test_SavingPartialCommandWhenNavigatingHistory(self): - """Verify that partial commands are saved when navigating history.""" - # Enter a command. - test_str = b'accelinfo' - input_stream = BytesToByteList(test_str) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Enter a partial command. - partial_cmd = b'ver' - input_stream.extend(BytesToByteList(partial_cmd)) - - # Hit the UP arrow key. - input_stream.extend(Keys.UP_ARROW) - # Then, the DOWN arrow key. - input_stream.extend(Keys.DOWN_ARROW) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The expected output should be the command we entered, a prompt, the - # partial command, clearing of the partial command, the command entered, - # clearing of the command entered, and then the partial command. - exp_console_out = test_str + b'\r\n' + self.console.prompt - exp_console_out += partial_cmd - for _ in range(len(partial_cmd)): - exp_console_out += BACKSPACE_STRING - exp_console_out += test_str - for _ in range(len(test_str)): - exp_console_out += BACKSPACE_STRING - exp_console_out += partial_cmd - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - # Verify input buffer. - exp_input_buffer = partial_cmd - exp_input_buffer_pos = len(exp_input_buffer) - CheckInputBuffer(self, exp_input_buffer) - CheckInputBufferPosition(self, exp_input_buffer_pos) - - def test_DownArrowOnEmptyHistory(self): - """Ensure nothing happens if the history is empty.""" - # Then press the up down arrow twice. - input_stream = 2 * Keys.DOWN_ARROW - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # We expect nothing to have happened. - exp_console_out = b'' - exp_input_buffer = b'' - exp_input_buffer_pos = 0 - exp_history_buf = [] - - # Verify. - CheckConsoleOutput(self, exp_console_out) - CheckInputBufferPosition(self, exp_input_buffer_pos) - CheckInputBuffer(self, exp_input_buffer) - CheckHistoryBuffer(self, exp_history_buf) - - def test_DeleteCharsUsingDELKey(self): - """Verify that we can delete characters using the DEL key.""" - test_str = b'version' - input_stream = BytesToByteList(test_str) - - # Hit the left arrow key 2 times. - input_stream.extend(2 * Keys.LEFT_ARROW) - - # Press the DEL key. - input_stream.extend(Keys.DEL) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The expected output should be the command we entered, 2 individual cursor - # moves to the left, and then removing a char and shifting everything to the - # left one column. - exp_console_out = test_str - exp_console_out += 2 * OutputStream.MoveCursorLeft(1) - - # Remove the char by shifting everything to the left one, slicing out the - # remove char. - exp_console_out += test_str[-1:] + b' ' - - # Reset the cursor by moving back 2 columns because of the 'n' and space. - exp_console_out += OutputStream.MoveCursorLeft(2) - - # Verify console output. - CheckConsoleOutput(self, exp_console_out) - - # Verify input buffer. The input buffer should have the char sliced out and - # be positioned where the char was removed. - exp_input_buffer = test_str[:-2] + test_str[-1:] - exp_input_buffer_pos = len(exp_input_buffer) - 1 - CheckInputBuffer(self, exp_input_buffer) - CheckInputBufferPosition(self, exp_input_buffer_pos) - - def test_RepeatedCommandInHistory(self): - """Verify that we don't store 2 consecutive identical commands in history""" - # Enter a few commands. - test_commands = [b'version', b'accelrange 0', b'battery', b'gettime'] - # Repeat the last command. - test_commands.append(test_commands[len(test_commands)-1]) - - input_stream = [] - for command in test_commands: - input_stream.extend(BytesToByteList(command)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Verify that the history buffer is correct. The last command, since - # it was repeated, should not have been added to the history. - exp_history_buf = test_commands[0:len(test_commands)-1] - CheckHistoryBuffer(self, exp_history_buf) + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + # Verify that the input buffer position is 1. + CheckInputBufferPosition(self, 1) -class TestConsoleCompatibility(unittest.TestCase): - """Verify that console can speak to enhanced and non-enhanced EC images.""" - def setUp(self): - """Setup the test harness.""" - # Setup logging with a timestamp, the module, and the log level. - logging.basicConfig(level=logging.DEBUG, - format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - # Create a temp file and set both the controller and peripheral PTYs to the - # file to create a loopback. - self.tempfile = tempfile.TemporaryFile() - - # Mock out the pipes. - mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() - self.console = console.Console(self.tempfile.fileno(), self.tempfile, - tempfile.TemporaryFile(), - mock_pipe_end_0, mock_pipe_end_1, "EC") - - @mock.patch('ec3po.console.Console.CheckForEnhancedECImage') - def test_ActAsPassThruInNonEnhancedMode(self, mock_check): - """Verify we simply pass everything thru to non-enhanced ECs. + # Also, verify that the input buffer is not modified. + CheckInputBuffer(self, test_str) - Args: - mock_check: A MagicMock object replacing the CheckForEnhancedECImage() - method. - """ - # Set the interrogation mode to always so that we actually interrogate. - self.console.interrogation_mode = b'always' - - # Assume EC interrogations indicate that the image is non-enhanced. - mock_check.return_value = False - - # Press enter, followed by the command, and another enter. - input_stream = [] - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - test_command = b'version' - input_stream.extend(BytesToByteList(test_command)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Expected calls to send down the pipe would be each character of the test - # command. - expected_calls = [] - expected_calls.append(mock.call( - six.int2byte(console.ControlKey.CARRIAGE_RETURN))) - for char in test_command: - if six.PY3: - expected_calls.append(mock.call(bytes([char]))) - else: - expected_calls.append(mock.call(char)) - expected_calls.append(mock.call( - six.int2byte(console.ControlKey.CARRIAGE_RETURN))) - - # Verify that the calls happened. - self.console.cmd_pipe.send.assert_has_calls(expected_calls) - - # Since we're acting as a pass-thru, the input buffer should be empty and - # input_buffer_pos is 0. - CheckInputBuffer(self, b'') - CheckInputBufferPosition(self, 0) - - @mock.patch('ec3po.console.Console.CheckForEnhancedECImage') - def test_TransitionFromNonEnhancedToEnhanced(self, mock_check): - """Verify that we transition correctly to enhanced mode. + # We expect the test string, followed by a jump to the beginning of the + # line, and finally a move right 1. + exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str))) + + # A move right 1 column. + exp_console_out += OutputStream.MoveCursorRight(1) + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + def test_MoveRightWithCtrlF(self): + """Move cursor forward one column with Ctrl+F.""" + test_str = b"panicinfo" + input_stream = BytesToByteList(test_str) + input_stream.append(console.ControlKey.CTRL_A) + # Now, move right one column. + input_stream.append(console.ControlKey.CTRL_F) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the input buffer position is 1. + CheckInputBufferPosition(self, 1) + + # Also, verify that the input buffer is not modified. + CheckInputBuffer(self, test_str) + + # We expect the test string, followed by a jump to the beginning of the + # line, and finally a move right 1. + exp_console_out = test_str + OutputStream.MoveCursorLeft(len((test_str))) + + # A move right 1 column. + exp_console_out += OutputStream.MoveCursorRight(1) + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + def test_ImpossibleMoveLeftWithArrowKey(self): + """Verify that we can't move left at the beginning of the line.""" + # We shouldn't be able to move left if we're at the beginning of the line. + input_stream = Keys.LEFT_ARROW + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Nothing should have been output. + exp_console_output = b"" + CheckConsoleOutput(self, exp_console_output) + + # The input buffer position should still be 0. + CheckInputBufferPosition(self, 0) + + # The input buffer itself should be empty. + CheckInputBuffer(self, b"") + + def test_ImpossibleMoveRightWithArrowKey(self): + """Verify that we can't move right at the end of the line.""" + # We shouldn't be able to move right if we're at the end of the line. + input_stream = Keys.RIGHT_ARROW + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Nothing should have been output. + exp_console_output = b"" + CheckConsoleOutput(self, exp_console_output) + + # The input buffer position should still be 0. + CheckInputBufferPosition(self, 0) + + # The input buffer itself should be empty. + CheckInputBuffer(self, b"") + + def test_KillEntireLine(self): + """Verify that we can kill an entire line with Ctrl+K.""" + test_str = b"accelinfo on" + input_stream = BytesToByteList(test_str) + # Jump to beginning of line and then kill it with Ctrl+K. + input_stream.extend([console.ControlKey.CTRL_A, console.ControlKey.CTRL_K]) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, we expect that the input buffer is empty. + CheckInputBuffer(self, b"") + + # The buffer position should be 0. + CheckInputBufferPosition(self, 0) + + # What we expect to see on the console stream should be the following. The + # test string, a jump to the beginning of the line, then jump back to the + # end of the line and replace the line with spaces. + exp_console_out = test_str + # Jump to beginning of line. + exp_console_out += OutputStream.MoveCursorLeft(len(test_str)) + # Jump to end of line. + exp_console_out += OutputStream.MoveCursorRight(len(test_str)) + # Replace line with spaces, which looks like backspaces. + for _ in range(len(test_str)): + exp_console_out += BACKSPACE_STRING + + # Verify the console output. + CheckConsoleOutput(self, exp_console_out) + + def test_KillPartialLine(self): + """Verify that we can kill a portion of a line.""" + test_str = b"accelread 0 1" + input_stream = BytesToByteList(test_str) + len_to_kill = 5 + for _ in range(len_to_kill): + # Move cursor left + input_stream.extend(Keys.LEFT_ARROW) + # Now kill + input_stream.append(console.ControlKey.CTRL_K) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, check that the input buffer was truncated. + exp_input_buffer = test_str[:-len_to_kill] + CheckInputBuffer(self, exp_input_buffer) + + # Verify the input buffer position. + CheckInputBufferPosition(self, len(test_str) - len_to_kill) + + # The console output stream that we expect is the test string followed by a + # move left of len_to_kill, then a jump to the end of the line and backspace + # of len_to_kill. + exp_console_out = test_str + for _ in range(len_to_kill): + # Move left 1 column. + exp_console_out += OutputStream.MoveCursorLeft(1) + # Then jump to the end of the line + exp_console_out += OutputStream.MoveCursorRight(len_to_kill) + # Backspace of len_to_kill + for _ in range(len_to_kill): + exp_console_out += BACKSPACE_STRING + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + def test_InsertingCharacters(self): + """Verify that we can insert characters within the line.""" + test_str = b"accel 0 1" # Here we forgot the 'read' part in 'accelread' + input_stream = BytesToByteList(test_str) + # We need to move over to the 'l' and add read. + insertion_point = test_str.find(b"l") + 1 + for i in range(len(test_str) - insertion_point): + # Move cursor left. + input_stream.extend(Keys.LEFT_ARROW) + # Now, add in 'read' + added_str = b"read" + input_stream.extend(BytesToByteList(added_str)) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # First, verify that the input buffer is correct. + exp_input_buffer = test_str[:insertion_point] + added_str + exp_input_buffer += test_str[insertion_point:] + CheckInputBuffer(self, exp_input_buffer) + + # Verify that the input buffer position is correct. + exp_input_buffer_pos = insertion_point + len(added_str) + CheckInputBufferPosition(self, exp_input_buffer_pos) + + # The console output stream that we expect is the test string, followed by + # move cursor left until the 'l' was found, the added test string while + # shifting characters around. + exp_console_out = test_str + for i in range(len(test_str) - insertion_point): + # Move cursor left. + exp_console_out += OutputStream.MoveCursorLeft(1) + + # Now for each character, write the rest of the line will be shifted to the + # right one column. + for i in range(len(added_str)): + # Printed character. + exp_console_out += added_str[i : i + 1] + # The rest of the line + exp_console_out += test_str[insertion_point:] + # Reset the cursor back left + reset_dist = len(test_str[insertion_point:]) + exp_console_out += OutputStream.MoveCursorLeft(reset_dist) + + # Verify the console output. + CheckConsoleOutput(self, exp_console_out) + + def test_StoreCommandHistory(self): + """Verify that entered commands are stored in the history.""" + test_commands = [] + test_commands.append(b"help") + test_commands.append(b"version") + test_commands.append(b"accelread 0 1") + input_stream = [] + for c in test_commands: + input_stream.extend(BytesToByteList(c)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # We expect to have the test commands in the history buffer. + exp_history_buf = test_commands + CheckHistoryBuffer(self, exp_history_buf) + + def test_CycleUpThruCommandHistory(self): + """Verify that the UP arrow key will print itmes in the history buffer.""" + # Enter some commands. + test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"] + input_stream = [] + for command in test_commands: + input_stream.extend(BytesToByteList(command)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Now, hit the UP arrow key to print the previous entries. + for i in range(len(test_commands)): + input_stream.extend(Keys.UP_ARROW) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The expected output should be test commands with prompts printed in + # between, followed by line kills with the previous test commands printed. + exp_console_out = b"" + for i in range(len(test_commands)): + exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt + + # When we press up, the line should be cleared and print the previous buffer + # entry. + for i in range(len(test_commands) - 1, 0, -1): + exp_console_out += test_commands[i] + # Backspace to the beginning. + for i in range(len(test_commands[i])): + exp_console_out += BACKSPACE_STRING + + # The last command should just be printed out with no backspacing. + exp_console_out += test_commands[0] + + # Now, verify. + CheckConsoleOutput(self, exp_console_out) + + def test_UpArrowOnEmptyHistory(self): + """Ensure nothing happens if the history is empty.""" + # Press the up arrow key twice. + input_stream = 2 * Keys.UP_ARROW + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # We expect nothing to have happened. + exp_console_out = b"" + exp_input_buffer = b"" + exp_input_buffer_pos = 0 + exp_history_buf = [] + + # Verify. + CheckConsoleOutput(self, exp_console_out) + CheckInputBufferPosition(self, exp_input_buffer_pos) + CheckInputBuffer(self, exp_input_buffer) + CheckHistoryBuffer(self, exp_history_buf) + + def test_UpArrowDoesNotGoOutOfBounds(self): + """Verify that pressing the up arrow many times won't go out of bounds.""" + # Enter one command. + test_str = b"help version" + input_stream = BytesToByteList(test_str) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + # Then press the up arrow key twice. + input_stream.extend(2 * Keys.UP_ARROW) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the history buffer is correct. + exp_history_buf = [test_str] + CheckHistoryBuffer(self, exp_history_buf) + + # We expect that the console output should only contain our entered command, + # a new prompt, and then our command aggain. + exp_console_out = test_str + b"\r\n" + self.console.prompt + # Pressing up should reprint the command we entered. + exp_console_out += test_str + + # Verify. + CheckConsoleOutput(self, exp_console_out) + + def test_CycleDownThruCommandHistory(self): + """Verify that we can select entries by hitting the down arrow.""" + # Enter at least 4 commands. + test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"] + input_stream = [] + for command in test_commands: + input_stream.extend(BytesToByteList(command)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Now, hit the UP arrow key twice to print the previous two entries. + for i in range(2): + input_stream.extend(Keys.UP_ARROW) + + # Now, hit the DOWN arrow key twice to print the newer entries. + input_stream.extend(2 * Keys.DOWN_ARROW) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The expected output should be commands that we entered, followed by + # prompts, then followed by our last two commands in reverse. Then, we + # should see the last entry in the list, followed by the saved partial cmd + # of a blank line. + exp_console_out = b"" + for i in range(len(test_commands)): + exp_console_out += test_commands[i] + b"\r\n" + self.console.prompt + + # When we press up, the line should be cleared and print the previous buffer + # entry. + for i in range(len(test_commands) - 1, 1, -1): + exp_console_out += test_commands[i] + # Backspace to the beginning. + for i in range(len(test_commands[i])): + exp_console_out += BACKSPACE_STRING + + # When we press down, it should have cleared the last command (which we + # covered with the previous for loop), and then prints the next command. + exp_console_out += test_commands[3] + for i in range(len(test_commands[3])): + exp_console_out += BACKSPACE_STRING + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + # Verify input buffer. + exp_input_buffer = b"" # Empty because our partial command was empty. + exp_input_buffer_pos = len(exp_input_buffer) + CheckInputBuffer(self, exp_input_buffer) + CheckInputBufferPosition(self, exp_input_buffer_pos) + + def test_SavingPartialCommandWhenNavigatingHistory(self): + """Verify that partial commands are saved when navigating history.""" + # Enter a command. + test_str = b"accelinfo" + input_stream = BytesToByteList(test_str) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Enter a partial command. + partial_cmd = b"ver" + input_stream.extend(BytesToByteList(partial_cmd)) + + # Hit the UP arrow key. + input_stream.extend(Keys.UP_ARROW) + # Then, the DOWN arrow key. + input_stream.extend(Keys.DOWN_ARROW) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The expected output should be the command we entered, a prompt, the + # partial command, clearing of the partial command, the command entered, + # clearing of the command entered, and then the partial command. + exp_console_out = test_str + b"\r\n" + self.console.prompt + exp_console_out += partial_cmd + for _ in range(len(partial_cmd)): + exp_console_out += BACKSPACE_STRING + exp_console_out += test_str + for _ in range(len(test_str)): + exp_console_out += BACKSPACE_STRING + exp_console_out += partial_cmd + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + # Verify input buffer. + exp_input_buffer = partial_cmd + exp_input_buffer_pos = len(exp_input_buffer) + CheckInputBuffer(self, exp_input_buffer) + CheckInputBufferPosition(self, exp_input_buffer_pos) + + def test_DownArrowOnEmptyHistory(self): + """Ensure nothing happens if the history is empty.""" + # Then press the up down arrow twice. + input_stream = 2 * Keys.DOWN_ARROW + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # We expect nothing to have happened. + exp_console_out = b"" + exp_input_buffer = b"" + exp_input_buffer_pos = 0 + exp_history_buf = [] + + # Verify. + CheckConsoleOutput(self, exp_console_out) + CheckInputBufferPosition(self, exp_input_buffer_pos) + CheckInputBuffer(self, exp_input_buffer) + CheckHistoryBuffer(self, exp_history_buf) + + def test_DeleteCharsUsingDELKey(self): + """Verify that we can delete characters using the DEL key.""" + test_str = b"version" + input_stream = BytesToByteList(test_str) + + # Hit the left arrow key 2 times. + input_stream.extend(2 * Keys.LEFT_ARROW) + + # Press the DEL key. + input_stream.extend(Keys.DEL) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The expected output should be the command we entered, 2 individual cursor + # moves to the left, and then removing a char and shifting everything to the + # left one column. + exp_console_out = test_str + exp_console_out += 2 * OutputStream.MoveCursorLeft(1) + + # Remove the char by shifting everything to the left one, slicing out the + # remove char. + exp_console_out += test_str[-1:] + b" " + + # Reset the cursor by moving back 2 columns because of the 'n' and space. + exp_console_out += OutputStream.MoveCursorLeft(2) + + # Verify console output. + CheckConsoleOutput(self, exp_console_out) + + # Verify input buffer. The input buffer should have the char sliced out and + # be positioned where the char was removed. + exp_input_buffer = test_str[:-2] + test_str[-1:] + exp_input_buffer_pos = len(exp_input_buffer) - 1 + CheckInputBuffer(self, exp_input_buffer) + CheckInputBufferPosition(self, exp_input_buffer_pos) + + def test_RepeatedCommandInHistory(self): + """Verify that we don't store 2 consecutive identical commands in history""" + # Enter a few commands. + test_commands = [b"version", b"accelrange 0", b"battery", b"gettime"] + # Repeat the last command. + test_commands.append(test_commands[len(test_commands) - 1]) + + input_stream = [] + for command in test_commands: + input_stream.extend(BytesToByteList(command)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Verify that the history buffer is correct. The last command, since + # it was repeated, should not have been added to the history. + exp_history_buf = test_commands[0 : len(test_commands) - 1] + CheckHistoryBuffer(self, exp_history_buf) - Args: - mock_check: A MagicMock object replacing the CheckForEnhancedECImage() - method. - """ - # Set the interrogation mode to always so that we actually interrogate. - self.console.interrogation_mode = b'always' - - # First, assume that the EC interrogations indicate an enhanced EC image. - mock_check.return_value = True - # But our current knowledge of the EC image (which was actually the - # 'previous' EC) was a non-enhanced image. - self.console.enhanced_ec = False - - test_command = b'sysinfo' - input_stream = [] - input_stream.extend(BytesToByteList(test_command)) - - expected_calls = [] - # All keystrokes to the console should be directed straight through to the - # EC until we press the enter key. - for char in test_command: - if six.PY3: - expected_calls.append(mock.call(bytes([char]))) - else: - expected_calls.append(mock.call(char)) - - # Press the enter key. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - # The enter key should not be sent to the pipe since we should negotiate - # to an enhanced EC image. - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # At this point, we should have negotiated to enhanced. - self.assertTrue(self.console.enhanced_ec, msg=('Did not negotiate to ' - 'enhanced EC image.')) - - # The command would have been dropped however, so verify this... - CheckInputBuffer(self, b'') - CheckInputBufferPosition(self, 0) - # ...and repeat the command. - input_stream = BytesToByteList(test_command) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Since we're enhanced now, we should have sent the entire command as one - # string with no trailing carriage return - expected_calls.append(mock.call(test_command)) - - # Verify all of the calls. - self.console.cmd_pipe.send.assert_has_calls(expected_calls) - - @mock.patch('ec3po.console.Console.CheckForEnhancedECImage') - def test_TransitionFromEnhancedToNonEnhanced(self, mock_check): - """Verify that we transition correctly to non-enhanced mode. - Args: - mock_check: A MagicMock object replacing the CheckForEnhancedECImage() - method. - """ - # Set the interrogation mode to always so that we actually interrogate. - self.console.interrogation_mode = b'always' - - # First, assume that the EC interrogations indicate an non-enhanced EC - # image. - mock_check.return_value = False - # But our current knowledge of the EC image (which was actually the - # 'previous' EC) was an enhanced image. - self.console.enhanced_ec = True - - test_command = b'sysinfo' - input_stream = [] - input_stream.extend(BytesToByteList(test_command)) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # But, we will negotiate to non-enhanced however, dropping this command. - # Verify this. - self.assertFalse(self.console.enhanced_ec, msg=('Did not negotiate to' - 'non-enhanced EC image.')) - CheckInputBuffer(self, b'') - CheckInputBufferPosition(self, 0) - - # The carriage return should have passed through though. - expected_calls = [] - expected_calls.append(mock.call( - six.int2byte(console.ControlKey.CARRIAGE_RETURN))) - - # Since the command was dropped, repeat the command. - input_stream = BytesToByteList(test_command) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # Since we're not enhanced now, we should have sent each character in the - # entire command separately and a carriage return. - for char in test_command: - if six.PY3: - expected_calls.append(mock.call(bytes([char]))) - else: - expected_calls.append(mock.call(char)) - expected_calls.append(mock.call( - six.int2byte(console.ControlKey.CARRIAGE_RETURN))) - - # Verify all of the calls. - self.console.cmd_pipe.send.assert_has_calls(expected_calls) - - def test_EnhancedCheckIfTimedOut(self): - """Verify that the check returns false if it times out.""" - # Make the debug pipe "time out". - self.console.dbg_pipe.poll.return_value = False - self.assertFalse(self.console.CheckForEnhancedECImage()) - - def test_EnhancedCheckIfACKReceived(self): - """Verify that the check returns true if the ACK is received.""" - # Make the debug pipe return EC_ACK. - self.console.dbg_pipe.poll.return_value = True - self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK - self.assertTrue(self.console.CheckForEnhancedECImage()) - - def test_EnhancedCheckIfWrong(self): - """Verify that the check returns false if byte received is wrong.""" - # Make the debug pipe return the wrong byte. - self.console.dbg_pipe.poll.return_value = True - self.console.dbg_pipe.recv.return_value = b'\xff' - self.assertFalse(self.console.CheckForEnhancedECImage()) - - def test_EnhancedCheckUsingBuffer(self): - """Verify that given reboot output, enhanced EC images are detected.""" - enhanced_output_stream = b""" +class TestConsoleCompatibility(unittest.TestCase): + """Verify that console can speak to enhanced and non-enhanced EC images.""" + + def setUp(self): + """Setup the test harness.""" + # Setup logging with a timestamp, the module, and the log level. + logging.basicConfig( + level=logging.DEBUG, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + # Create a temp file and set both the controller and peripheral PTYs to the + # file to create a loopback. + self.tempfile = tempfile.TemporaryFile() + + # Mock out the pipes. + mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() + self.console = console.Console( + self.tempfile.fileno(), + self.tempfile, + tempfile.TemporaryFile(), + mock_pipe_end_0, + mock_pipe_end_1, + "EC", + ) + + @mock.patch("ec3po.console.Console.CheckForEnhancedECImage") + def test_ActAsPassThruInNonEnhancedMode(self, mock_check): + """Verify we simply pass everything thru to non-enhanced ECs. + + Args: + mock_check: A MagicMock object replacing the CheckForEnhancedECImage() + method. + """ + # Set the interrogation mode to always so that we actually interrogate. + self.console.interrogation_mode = b"always" + + # Assume EC interrogations indicate that the image is non-enhanced. + mock_check.return_value = False + + # Press enter, followed by the command, and another enter. + input_stream = [] + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + test_command = b"version" + input_stream.extend(BytesToByteList(test_command)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Expected calls to send down the pipe would be each character of the test + # command. + expected_calls = [] + expected_calls.append( + mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN)) + ) + for char in test_command: + if six.PY3: + expected_calls.append(mock.call(bytes([char]))) + else: + expected_calls.append(mock.call(char)) + expected_calls.append( + mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN)) + ) + + # Verify that the calls happened. + self.console.cmd_pipe.send.assert_has_calls(expected_calls) + + # Since we're acting as a pass-thru, the input buffer should be empty and + # input_buffer_pos is 0. + CheckInputBuffer(self, b"") + CheckInputBufferPosition(self, 0) + + @mock.patch("ec3po.console.Console.CheckForEnhancedECImage") + def test_TransitionFromNonEnhancedToEnhanced(self, mock_check): + """Verify that we transition correctly to enhanced mode. + + Args: + mock_check: A MagicMock object replacing the CheckForEnhancedECImage() + method. + """ + # Set the interrogation mode to always so that we actually interrogate. + self.console.interrogation_mode = b"always" + + # First, assume that the EC interrogations indicate an enhanced EC image. + mock_check.return_value = True + # But our current knowledge of the EC image (which was actually the + # 'previous' EC) was a non-enhanced image. + self.console.enhanced_ec = False + + test_command = b"sysinfo" + input_stream = [] + input_stream.extend(BytesToByteList(test_command)) + + expected_calls = [] + # All keystrokes to the console should be directed straight through to the + # EC until we press the enter key. + for char in test_command: + if six.PY3: + expected_calls.append(mock.call(bytes([char]))) + else: + expected_calls.append(mock.call(char)) + + # Press the enter key. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + # The enter key should not be sent to the pipe since we should negotiate + # to an enhanced EC image. + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # At this point, we should have negotiated to enhanced. + self.assertTrue( + self.console.enhanced_ec, msg=("Did not negotiate to " "enhanced EC image.") + ) + + # The command would have been dropped however, so verify this... + CheckInputBuffer(self, b"") + CheckInputBufferPosition(self, 0) + # ...and repeat the command. + input_stream = BytesToByteList(test_command) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Since we're enhanced now, we should have sent the entire command as one + # string with no trailing carriage return + expected_calls.append(mock.call(test_command)) + + # Verify all of the calls. + self.console.cmd_pipe.send.assert_has_calls(expected_calls) + + @mock.patch("ec3po.console.Console.CheckForEnhancedECImage") + def test_TransitionFromEnhancedToNonEnhanced(self, mock_check): + """Verify that we transition correctly to non-enhanced mode. + + Args: + mock_check: A MagicMock object replacing the CheckForEnhancedECImage() + method. + """ + # Set the interrogation mode to always so that we actually interrogate. + self.console.interrogation_mode = b"always" + + # First, assume that the EC interrogations indicate an non-enhanced EC + # image. + mock_check.return_value = False + # But our current knowledge of the EC image (which was actually the + # 'previous' EC) was an enhanced image. + self.console.enhanced_ec = True + + test_command = b"sysinfo" + input_stream = [] + input_stream.extend(BytesToByteList(test_command)) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # But, we will negotiate to non-enhanced however, dropping this command. + # Verify this. + self.assertFalse( + self.console.enhanced_ec, + msg=("Did not negotiate to" "non-enhanced EC image."), + ) + CheckInputBuffer(self, b"") + CheckInputBufferPosition(self, 0) + + # The carriage return should have passed through though. + expected_calls = [] + expected_calls.append( + mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN)) + ) + + # Since the command was dropped, repeat the command. + input_stream = BytesToByteList(test_command) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # Since we're not enhanced now, we should have sent each character in the + # entire command separately and a carriage return. + for char in test_command: + if six.PY3: + expected_calls.append(mock.call(bytes([char]))) + else: + expected_calls.append(mock.call(char)) + expected_calls.append( + mock.call(six.int2byte(console.ControlKey.CARRIAGE_RETURN)) + ) + + # Verify all of the calls. + self.console.cmd_pipe.send.assert_has_calls(expected_calls) + + def test_EnhancedCheckIfTimedOut(self): + """Verify that the check returns false if it times out.""" + # Make the debug pipe "time out". + self.console.dbg_pipe.poll.return_value = False + self.assertFalse(self.console.CheckForEnhancedECImage()) + + def test_EnhancedCheckIfACKReceived(self): + """Verify that the check returns true if the ACK is received.""" + # Make the debug pipe return EC_ACK. + self.console.dbg_pipe.poll.return_value = True + self.console.dbg_pipe.recv.return_value = interpreter.EC_ACK + self.assertTrue(self.console.CheckForEnhancedECImage()) + + def test_EnhancedCheckIfWrong(self): + """Verify that the check returns false if byte received is wrong.""" + # Make the debug pipe return the wrong byte. + self.console.dbg_pipe.poll.return_value = True + self.console.dbg_pipe.recv.return_value = b"\xff" + self.assertFalse(self.console.CheckForEnhancedECImage()) + + def test_EnhancedCheckUsingBuffer(self): + """Verify that given reboot output, enhanced EC images are detected.""" + enhanced_output_stream = b""" --- UART initialized after reboot --- [Reset cause: reset-pin soft] [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:26:20 aaboagye@lithium.mtv.corp.google.com] @@ -1295,19 +1343,19 @@ Enhanced Console is enabled (v1.0.0); type HELP for help. [0.224060 hash done 41dac382e3a6e3d2ea5b4d789c1bc46525cae7cc5ff6758f0de8d8369b506f57] [0.375150 POWER_GOOD seen] """ - for line in enhanced_output_stream.split(b'\n'): - self.console.CheckBufferForEnhancedImage(line) + for line in enhanced_output_stream.split(b"\n"): + self.console.CheckBufferForEnhancedImage(line) - # Since the enhanced console string was present in the output, the console - # should have caught it. - self.assertTrue(self.console.enhanced_ec) + # Since the enhanced console string was present in the output, the console + # should have caught it. + self.assertTrue(self.console.enhanced_ec) - # Also should check that the command was sent to the interpreter. - self.console.cmd_pipe.send.assert_called_once_with(b'enhanced True') + # Also should check that the command was sent to the interpreter. + self.console.cmd_pipe.send.assert_called_once_with(b"enhanced True") - # Now test the non-enhanced EC image. - self.console.cmd_pipe.reset_mock() - non_enhanced_output_stream = b""" + # Now test the non-enhanced EC image. + self.console.cmd_pipe.reset_mock() + non_enhanced_output_stream = b""" --- UART initialized after reboot --- [Reset cause: reset-pin soft] [Image: RO, jerry_v1.1.4363-2af8572-dirty 2016-02-23 13:03:15 aaboagye@lithium.mtv.corp.google.com] @@ -1331,239 +1379,253 @@ Console is enabled; type HELP for help. [0.010285 power on 2] [0.010385 power state 5 = S5->S3, in 0x0000] """ - for line in non_enhanced_output_stream.split(b'\n'): - self.console.CheckBufferForEnhancedImage(line) + for line in non_enhanced_output_stream.split(b"\n"): + self.console.CheckBufferForEnhancedImage(line) - # Since the default console string is present in the output, it should be - # determined to be non enhanced now. - self.assertFalse(self.console.enhanced_ec) + # Since the default console string is present in the output, it should be + # determined to be non enhanced now. + self.assertFalse(self.console.enhanced_ec) - # Check that command was also sent to the interpreter. - self.console.cmd_pipe.send.assert_called_once_with(b'enhanced False') + # Check that command was also sent to the interpreter. + self.console.cmd_pipe.send.assert_called_once_with(b"enhanced False") class TestOOBMConsoleCommands(unittest.TestCase): - """Verify that OOBM console commands work correctly.""" - def setUp(self): - """Setup the test harness.""" - # Setup logging with a timestamp, the module, and the log level. - logging.basicConfig(level=logging.DEBUG, - format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - # Create a temp file and set both the controller and peripheral PTYs to the - # file to create a loopback. - self.tempfile = tempfile.TemporaryFile() - - # Mock out the pipes. - mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() - self.console = console.Console(self.tempfile.fileno(), self.tempfile, - tempfile.TemporaryFile(), - mock_pipe_end_0, mock_pipe_end_1, "EC") - self.console.oobm_queue = mock.MagicMock() - - @mock.patch('ec3po.console.Console.CheckForEnhancedECImage') - def test_InterrogateCommand(self, mock_check): - """Verify that 'interrogate' command works as expected. - - Args: - mock_check: A MagicMock object replacing the CheckForEnhancedECIMage() - method. - """ - input_stream = [] - expected_calls = [] - mock_check.side_effect = [False] - - # 'interrogate never' should disable the interrogation from happening at - # all. - cmd = b'interrogate never' - # Enter the OOBM prompt. - input_stream.extend(BytesToByteList(b'%')) - # Type the command - input_stream.extend(BytesToByteList(cmd)) - # Press enter. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - input_stream = [] - - # The OOBM queue should have been called with the command being put. - expected_calls.append(mock.call.put(cmd)) - self.console.oobm_queue.assert_has_calls(expected_calls) - - # Process the OOBM queue. - self.console.oobm_queue.get.side_effect = [cmd] - self.console.ProcessOOBMQueue() - - # Type out a few commands. - input_stream.extend(BytesToByteList(b'version')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'flashinfo')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'sysinfo')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The Check function should NOT have been called at all. - mock_check.assert_not_called() - - # The EC image should be assumed to be not enhanced. - self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to' - ' be NOT enhanced.') - - # Reset the mocks. - mock_check.reset_mock() - self.console.oobm_queue.reset_mock() - - # 'interrogate auto' should not interrogate at all. It should only be - # scanning the output stream for the 'console is enabled' strings. - cmd = b'interrogate auto' - # Enter the OOBM prompt. - input_stream.extend(BytesToByteList(b'%')) - # Type the command - input_stream.extend(BytesToByteList(cmd)) - # Press enter. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - input_stream = [] - expected_calls = [] - - # The OOBM queue should have been called with the command being put. - expected_calls.append(mock.call.put(cmd)) - self.console.oobm_queue.assert_has_calls(expected_calls) - - # Process the OOBM queue. - self.console.oobm_queue.get.side_effect = [cmd] - self.console.ProcessOOBMQueue() - - # Type out a few commands. - input_stream.extend(BytesToByteList(b'version')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'flashinfo')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'sysinfo')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The Check function should NOT have been called at all. - mock_check.assert_not_called() - - # The EC image should be assumed to be not enhanced. - self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to' - ' be NOT enhanced.') - - # Reset the mocks. - mock_check.reset_mock() - self.console.oobm_queue.reset_mock() - - # 'interrogate always' should, like its name implies, interrogate always - # after each press of the enter key. This was the former way of doing - # interrogation. - cmd = b'interrogate always' - # Enter the OOBM prompt. - input_stream.extend(BytesToByteList(b'%')) - # Type the command - input_stream.extend(BytesToByteList(cmd)) - # Press enter. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - input_stream = [] - expected_calls = [] - - # The OOBM queue should have been called with the command being put. - expected_calls.append(mock.call.put(cmd)) - self.console.oobm_queue.assert_has_calls(expected_calls) - - # Process the OOBM queue. - self.console.oobm_queue.get.side_effect = [cmd] - self.console.ProcessOOBMQueue() - - # The Check method should be called 3 times here. - mock_check.side_effect = [False, False, False] - - # Type out a few commands. - input_stream.extend(BytesToByteList(b'help list')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'taskinfo')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'hibdelay')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The Check method should have been called 3 times here. - expected_calls = [mock.call(), mock.call(), mock.call()] - mock_check.assert_has_calls(expected_calls) - - # The EC image should be assumed to be not enhanced. - self.assertFalse(self.console.enhanced_ec, 'The image should be assumed to' - ' be NOT enhanced.') - - # Now, let's try to assume that the image is enhanced while still disabling - # interrogation. - mock_check.reset_mock() - self.console.oobm_queue.reset_mock() - input_stream = [] - cmd = b'interrogate never enhanced' - # Enter the OOBM prompt. - input_stream.extend(BytesToByteList(b'%')) - # Type the command - input_stream.extend(BytesToByteList(cmd)) - # Press enter. - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - input_stream = [] - expected_calls = [] - - # The OOBM queue should have been called with the command being put. - expected_calls.append(mock.call.put(cmd)) - self.console.oobm_queue.assert_has_calls(expected_calls) - - # Process the OOBM queue. - self.console.oobm_queue.get.side_effect = [cmd] - self.console.ProcessOOBMQueue() - - # Type out a few commands. - input_stream.extend(BytesToByteList(b'chgstate')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'hash')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - input_stream.extend(BytesToByteList(b'sysjump rw')) - input_stream.append(console.ControlKey.CARRIAGE_RETURN) - - # Send the sequence out. - for byte in input_stream: - self.console.HandleChar(byte) - - # The check method should have never been called. - mock_check.assert_not_called() - - # The EC image should be assumed to be enhanced. - self.assertTrue(self.console.enhanced_ec, 'The image should be' - ' assumed to be enhanced.') - - -if __name__ == '__main__': - unittest.main() + """Verify that OOBM console commands work correctly.""" + + def setUp(self): + """Setup the test harness.""" + # Setup logging with a timestamp, the module, and the log level. + logging.basicConfig( + level=logging.DEBUG, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + # Create a temp file and set both the controller and peripheral PTYs to the + # file to create a loopback. + self.tempfile = tempfile.TemporaryFile() + + # Mock out the pipes. + mock_pipe_end_0, mock_pipe_end_1 = mock.MagicMock(), mock.MagicMock() + self.console = console.Console( + self.tempfile.fileno(), + self.tempfile, + tempfile.TemporaryFile(), + mock_pipe_end_0, + mock_pipe_end_1, + "EC", + ) + self.console.oobm_queue = mock.MagicMock() + + @mock.patch("ec3po.console.Console.CheckForEnhancedECImage") + def test_InterrogateCommand(self, mock_check): + """Verify that 'interrogate' command works as expected. + + Args: + mock_check: A MagicMock object replacing the CheckForEnhancedECIMage() + method. + """ + input_stream = [] + expected_calls = [] + mock_check.side_effect = [False] + + # 'interrogate never' should disable the interrogation from happening at + # all. + cmd = b"interrogate never" + # Enter the OOBM prompt. + input_stream.extend(BytesToByteList(b"%")) + # Type the command + input_stream.extend(BytesToByteList(cmd)) + # Press enter. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + input_stream = [] + + # The OOBM queue should have been called with the command being put. + expected_calls.append(mock.call.put(cmd)) + self.console.oobm_queue.assert_has_calls(expected_calls) + + # Process the OOBM queue. + self.console.oobm_queue.get.side_effect = [cmd] + self.console.ProcessOOBMQueue() + + # Type out a few commands. + input_stream.extend(BytesToByteList(b"version")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"flashinfo")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"sysinfo")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The Check function should NOT have been called at all. + mock_check.assert_not_called() + + # The EC image should be assumed to be not enhanced. + self.assertFalse( + self.console.enhanced_ec, + "The image should be assumed to" " be NOT enhanced.", + ) + + # Reset the mocks. + mock_check.reset_mock() + self.console.oobm_queue.reset_mock() + + # 'interrogate auto' should not interrogate at all. It should only be + # scanning the output stream for the 'console is enabled' strings. + cmd = b"interrogate auto" + # Enter the OOBM prompt. + input_stream.extend(BytesToByteList(b"%")) + # Type the command + input_stream.extend(BytesToByteList(cmd)) + # Press enter. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + input_stream = [] + expected_calls = [] + + # The OOBM queue should have been called with the command being put. + expected_calls.append(mock.call.put(cmd)) + self.console.oobm_queue.assert_has_calls(expected_calls) + + # Process the OOBM queue. + self.console.oobm_queue.get.side_effect = [cmd] + self.console.ProcessOOBMQueue() + + # Type out a few commands. + input_stream.extend(BytesToByteList(b"version")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"flashinfo")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"sysinfo")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The Check function should NOT have been called at all. + mock_check.assert_not_called() + + # The EC image should be assumed to be not enhanced. + self.assertFalse( + self.console.enhanced_ec, + "The image should be assumed to" " be NOT enhanced.", + ) + + # Reset the mocks. + mock_check.reset_mock() + self.console.oobm_queue.reset_mock() + + # 'interrogate always' should, like its name implies, interrogate always + # after each press of the enter key. This was the former way of doing + # interrogation. + cmd = b"interrogate always" + # Enter the OOBM prompt. + input_stream.extend(BytesToByteList(b"%")) + # Type the command + input_stream.extend(BytesToByteList(cmd)) + # Press enter. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + input_stream = [] + expected_calls = [] + + # The OOBM queue should have been called with the command being put. + expected_calls.append(mock.call.put(cmd)) + self.console.oobm_queue.assert_has_calls(expected_calls) + + # Process the OOBM queue. + self.console.oobm_queue.get.side_effect = [cmd] + self.console.ProcessOOBMQueue() + + # The Check method should be called 3 times here. + mock_check.side_effect = [False, False, False] + + # Type out a few commands. + input_stream.extend(BytesToByteList(b"help list")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"taskinfo")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"hibdelay")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The Check method should have been called 3 times here. + expected_calls = [mock.call(), mock.call(), mock.call()] + mock_check.assert_has_calls(expected_calls) + + # The EC image should be assumed to be not enhanced. + self.assertFalse( + self.console.enhanced_ec, + "The image should be assumed to" " be NOT enhanced.", + ) + + # Now, let's try to assume that the image is enhanced while still disabling + # interrogation. + mock_check.reset_mock() + self.console.oobm_queue.reset_mock() + input_stream = [] + cmd = b"interrogate never enhanced" + # Enter the OOBM prompt. + input_stream.extend(BytesToByteList(b"%")) + # Type the command + input_stream.extend(BytesToByteList(cmd)) + # Press enter. + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + input_stream = [] + expected_calls = [] + + # The OOBM queue should have been called with the command being put. + expected_calls.append(mock.call.put(cmd)) + self.console.oobm_queue.assert_has_calls(expected_calls) + + # Process the OOBM queue. + self.console.oobm_queue.get.side_effect = [cmd] + self.console.ProcessOOBMQueue() + + # Type out a few commands. + input_stream.extend(BytesToByteList(b"chgstate")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"hash")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + input_stream.extend(BytesToByteList(b"sysjump rw")) + input_stream.append(console.ControlKey.CARRIAGE_RETURN) + + # Send the sequence out. + for byte in input_stream: + self.console.HandleChar(byte) + + # The check method should have never been called. + mock_check.assert_not_called() + + # The EC image should be assumed to be enhanced. + self.assertTrue( + self.console.enhanced_ec, "The image should be" " assumed to be enhanced." + ) + + +if __name__ == "__main__": + unittest.main() diff --git a/util/ec3po/interpreter.py b/util/ec3po/interpreter.py index 4e151083bd..591603e038 100644 --- a/util/ec3po/interpreter.py +++ b/util/ec3po/interpreter.py @@ -25,443 +25,447 @@ import traceback import six - COMMAND_RETRIES = 3 # Number of attempts to retry a command. EC_MAX_READ = 1024 # Max bytes to read at a time from the EC. -EC_SYN = b'\xec' # Byte indicating EC interrogation. -EC_ACK = b'\xc0' # Byte representing correct EC response to interrogation. +EC_SYN = b"\xec" # Byte indicating EC interrogation. +EC_ACK = b"\xc0" # Byte representing correct EC response to interrogation. class LoggerAdapter(logging.LoggerAdapter): - """Class which provides a small adapter for the logger.""" + """Class which provides a small adapter for the logger.""" - def process(self, msg, kwargs): - """Prepends the served PTY to the beginning of the log message.""" - return '%s - %s' % (self.extra['pty'], msg), kwargs + def process(self, msg, kwargs): + """Prepends the served PTY to the beginning of the log message.""" + return "%s - %s" % (self.extra["pty"], msg), kwargs class Interpreter(object): - """Class which provides the interpretation layer between the EC and user. - - This class essentially performs all of the intepretation for the EC and the - user. It handles all of the automatic command retrying as well as the - formation of commands for EC images which support that. - - Attributes: - logger: A logger for this module. - ec_uart_pty: An opened file object to the raw EC UART PTY. - ec_uart_pty_name: A string containing the name of the raw EC UART PTY. - cmd_pipe: A socket.socket or multiprocessing.Connection object which - represents the Interpreter side of the command pipe. This must be a - bidirectional pipe. Commands and responses will utilize this pipe. - dbg_pipe: A socket.socket or multiprocessing.Connection object which - represents the Interpreter side of the debug pipe. This must be a - unidirectional pipe with write capabilities. EC debug output will utilize - this pipe. - cmd_retries: An integer representing the number of attempts the console - should retry commands if it receives an error. - log_level: An integer representing the numeric value of the log level. - inputs: A list of objects that the intpreter selects for reading. - Initially, these are the EC UART and the command pipe. - outputs: A list of objects that the interpreter selects for writing. - ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART. - last_cmd: A string that represents the last command sent to the EC. If an - error is encountered, the interpreter will attempt to retry this command - up to COMMAND_RETRIES. - enhanced_ec: A boolean indicating if the EC image that we are currently - communicating with is enhanced or not. Enhanced EC images will support - packed commands and host commands over the UART. This defaults to False - and is changed depending on the result of an interrogation. - interrogating: A boolean indicating if we are in the middle of interrogating - the EC. - connected: A boolean indicating if the interpreter is actually connected to - the UART and listening. - """ - def __init__(self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO, - name=None): - """Intializes an Interpreter object with the provided args. + """Class which provides the interpretation layer between the EC and user. - Args: - ec_uart_pty: A string representing the EC UART to connect to. + This class essentially performs all of the intepretation for the EC and the + user. It handles all of the automatic command retrying as well as the + formation of commands for EC images which support that. + + Attributes: + logger: A logger for this module. + ec_uart_pty: An opened file object to the raw EC UART PTY. + ec_uart_pty_name: A string containing the name of the raw EC UART PTY. cmd_pipe: A socket.socket or multiprocessing.Connection object which represents the Interpreter side of the command pipe. This must be a bidirectional pipe. Commands and responses will utilize this pipe. dbg_pipe: A socket.socket or multiprocessing.Connection object which represents the Interpreter side of the debug pipe. This must be a - unidirectional pipe with write capabilities. EC debug output will - utilize this pipe. + unidirectional pipe with write capabilities. EC debug output will utilize + this pipe. cmd_retries: An integer representing the number of attempts the console should retry commands if it receives an error. - log_level: An optional integer representing the numeric value of the log - level. By default, the log level will be logging.INFO (20). - name: the console source name - """ - # Create a unique logger based on the interpreter name - interpreter_prefix = ('%s - ' % name) if name else '' - logger = logging.getLogger('%sEC3PO.Interpreter' % interpreter_prefix) - self.logger = LoggerAdapter(logger, {'pty': ec_uart_pty}) - # TODO(https://crbug.com/1162189): revist the 2 TODOs below - # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+ - # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when - # that gets fixed, or keep two pty: one for reading and one for writing - self.ec_uart_pty = open(ec_uart_pty, 'r+b', buffering=0) - self.ec_uart_pty_name = ec_uart_pty - self.cmd_pipe = cmd_pipe - self.dbg_pipe = dbg_pipe - self.cmd_retries = COMMAND_RETRIES - self.log_level = log_level - self.inputs = [self.ec_uart_pty, self.cmd_pipe] - self.outputs = [] - self.ec_cmd_queue = six.moves.queue.Queue() - self.last_cmd = b'' - self.enhanced_ec = False - self.interrogating = False - self.connected = True - - def __str__(self): - """Show internal state of the Interpreter object. - - Returns: - A string that shows the values of the attributes. - """ - string = [] - string.append('%r' % self) - string.append('ec_uart_pty: %s' % self.ec_uart_pty) - string.append('cmd_pipe: %r' % self.cmd_pipe) - string.append('dbg_pipe: %r' % self.dbg_pipe) - string.append('cmd_retries: %d' % self.cmd_retries) - string.append('log_level: %d' % self.log_level) - string.append('inputs: %r' % self.inputs) - string.append('outputs: %r' % self.outputs) - string.append('ec_cmd_queue: %r' % self.ec_cmd_queue) - string.append('last_cmd: \'%s\'' % self.last_cmd) - string.append('enhanced_ec: %r' % self.enhanced_ec) - string.append('interrogating: %r' % self.interrogating) - return '\n'.join(string) - - def EnqueueCmd(self, command): - """Enqueue a command to be sent to the EC UART. - - Args: - command: A string which contains the command to be sent. + log_level: An integer representing the numeric value of the log level. + inputs: A list of objects that the intpreter selects for reading. + Initially, these are the EC UART and the command pipe. + outputs: A list of objects that the interpreter selects for writing. + ec_cmd_queue: A FIFO queue used for sending commands down to the EC UART. + last_cmd: A string that represents the last command sent to the EC. If an + error is encountered, the interpreter will attempt to retry this command + up to COMMAND_RETRIES. + enhanced_ec: A boolean indicating if the EC image that we are currently + communicating with is enhanced or not. Enhanced EC images will support + packed commands and host commands over the UART. This defaults to False + and is changed depending on the result of an interrogation. + interrogating: A boolean indicating if we are in the middle of interrogating + the EC. + connected: A boolean indicating if the interpreter is actually connected to + the UART and listening. """ - self.ec_cmd_queue.put(command) - self.logger.log(1, 'Commands now in queue: %d', self.ec_cmd_queue.qsize()) - # Add the EC UART as an output to be serviced. - if self.connected and self.ec_uart_pty not in self.outputs: - self.outputs.append(self.ec_uart_pty) - - def PackCommand(self, raw_cmd): - r"""Packs a command for use with error checking. - - For error checking, we pack console commands in a particular format. The - format is as follows: - - &&[x][x][x][x]&{cmd}\n\n - ^ ^ ^^ ^^ ^ ^-- 2 newlines. - | | || || |-- the raw console command. - | | || ||-- 1 ampersand. - | | ||____|--- 2 hex digits representing the CRC8 of cmd. - | |____|-- 2 hex digits reprsenting the length of cmd. - |-- 2 ampersands - - Args: - raw_cmd: A pre-packed string which contains the raw command. - - Returns: - A string which contains the packed command. - """ - # Don't pack a single carriage return. - if raw_cmd != b'\r': - # The command format is as follows. - # &&[x][x][x][x]&{cmd}\n\n - packed_cmd = [] - packed_cmd.append(b'&&') - # The first pair of hex digits are the length of the command. - packed_cmd.append(b'%02x' % len(raw_cmd)) - # Then the CRC8 of cmd. - packed_cmd.append(b'%02x' % Crc8(raw_cmd)) - packed_cmd.append(b'&') - # Now, the raw command followed by 2 newlines. - packed_cmd.append(raw_cmd) - packed_cmd.append(b'\n\n') - return b''.join(packed_cmd) - else: - return raw_cmd - - def ProcessCommand(self, command): - """Captures the input determines what actions to take. - - Args: - command: A string representing the command sent by the user. - """ - if command == b'disconnect': - if self.connected: - self.logger.debug('UART disconnect request.') - # Drop all pending commands if any. - while not self.ec_cmd_queue.empty(): - c = self.ec_cmd_queue.get() - self.logger.debug('dropped: \'%s\'', c) - if self.enhanced_ec: - # Reset retry state. - self.cmd_retries = COMMAND_RETRIES - self.last_cmd = b'' - # Get the UART that the interpreter is attached to. - fileobj = self.ec_uart_pty - self.logger.debug('fileobj: %r', fileobj) - # Remove the descriptor from the inputs and outputs. - self.inputs.remove(fileobj) - if fileobj in self.outputs: - self.outputs.remove(fileobj) - self.logger.debug('Removed fileobj. Remaining inputs: %r', self.inputs) - # Close the file. - fileobj.close() - # Mark the interpreter as disconnected now. - self.connected = False - self.logger.debug('Disconnected from %s.', self.ec_uart_pty_name) - return - - elif command == b'reconnect': - if not self.connected: - self.logger.debug('UART reconnect request.') - # Reopen the PTY. + def __init__( + self, ec_uart_pty, cmd_pipe, dbg_pipe, log_level=logging.INFO, name=None + ): + """Intializes an Interpreter object with the provided args. + + Args: + ec_uart_pty: A string representing the EC UART to connect to. + cmd_pipe: A socket.socket or multiprocessing.Connection object which + represents the Interpreter side of the command pipe. This must be a + bidirectional pipe. Commands and responses will utilize this pipe. + dbg_pipe: A socket.socket or multiprocessing.Connection object which + represents the Interpreter side of the debug pipe. This must be a + unidirectional pipe with write capabilities. EC debug output will + utilize this pipe. + cmd_retries: An integer representing the number of attempts the console + should retry commands if it receives an error. + log_level: An optional integer representing the numeric value of the log + level. By default, the log level will be logging.INFO (20). + name: the console source name + """ + # Create a unique logger based on the interpreter name + interpreter_prefix = ("%s - " % name) if name else "" + logger = logging.getLogger("%sEC3PO.Interpreter" % interpreter_prefix) + self.logger = LoggerAdapter(logger, {"pty": ec_uart_pty}) + # TODO(https://crbug.com/1162189): revist the 2 TODOs below # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+ # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when # that gets fixed, or keep two pty: one for reading and one for writing - fileobj = open(self.ec_uart_pty_name, 'r+b', buffering=0) - self.logger.debug('fileobj: %r', fileobj) - self.ec_uart_pty = fileobj - # Add the descriptor to the inputs. - self.inputs.append(fileobj) - self.logger.debug('fileobj added. curr inputs: %r', self.inputs) - # Mark the interpreter as connected now. - self.connected = True - self.logger.debug('Connected to %s.', self.ec_uart_pty_name) - return - - elif command.startswith(b'enhanced'): - self.enhanced_ec = command.split(b' ')[1] == b'True' - return - - # Ignore any other commands while in the disconnected state. - self.logger.log(1, 'command: \'%s\'', command) - if not self.connected: - self.logger.debug('Ignoring command because currently disconnected.') - return - - # Remove leading and trailing spaces only if this is an enhanced EC image. - # For non-enhanced EC images, commands will be single characters at a time - # and can be spaces. - if self.enhanced_ec: - command = command.strip(b' ') - - # There's nothing to do if the command is empty. - if len(command) == 0: - return - - # Handle log level change requests. - if command.startswith(b'loglevel'): - self.logger.debug('Log level change request.') - new_log_level = int(command.split(b' ')[1]) - self.logger.logger.setLevel(new_log_level) - self.logger.info('Log level changed to %d.', new_log_level) - return - - # Check for interrogation command. - if command == EC_SYN: - # User is requesting interrogation. Send SYN as is. - self.logger.debug('User requesting interrogation.') - self.interrogating = True - # Assume the EC isn't enhanced until we get a response. - self.enhanced_ec = False - elif self.enhanced_ec: - # Enhanced EC images require the plaintext commands to be packed. - command = self.PackCommand(command) - # TODO(aaboagye): Make a dict of commands and keys and eventually, - # handle partial matching based on unique prefixes. - - self.EnqueueCmd(command) - - def HandleCmdRetries(self): - """Attempts to retry commands if possible.""" - if self.cmd_retries > 0: - # The EC encountered an error. We'll have to retry again. - self.logger.warning('Retrying command...') - self.cmd_retries -= 1 - self.logger.warning('Retries remaining: %d', self.cmd_retries) - # Retry the command and add the EC UART to the writers again. - self.EnqueueCmd(self.last_cmd) - self.outputs.append(self.ec_uart_pty) - else: - # We're out of retries, so just give up. - self.logger.error('Command failed. No retries left.') - # Clear the command in progress. - self.last_cmd = b'' - # Reset the retry count. - self.cmd_retries = COMMAND_RETRIES - - def SendCmdToEC(self): - """Sends a command to the EC.""" - # If we're retrying a command, just try to send it again. - if self.cmd_retries < COMMAND_RETRIES: - cmd = self.last_cmd - else: - # If we're not retrying, we should not be writing to the EC if we have no - # items in our command queue. - assert not self.ec_cmd_queue.empty() - # Get the command to send. - cmd = self.ec_cmd_queue.get() - - # Send the command. - self.ec_uart_pty.write(cmd) - self.ec_uart_pty.flush() - self.logger.log(1, 'Sent command to EC.') - - if self.enhanced_ec and cmd != EC_SYN: - # Now, that we've sent the command, store the current command as the last - # command sent. If we encounter an error string, we will attempt to retry - # this command. - if cmd != self.last_cmd: - self.last_cmd = cmd - # Reset the retry count. + self.ec_uart_pty = open(ec_uart_pty, "r+b", buffering=0) + self.ec_uart_pty_name = ec_uart_pty + self.cmd_pipe = cmd_pipe + self.dbg_pipe = dbg_pipe self.cmd_retries = COMMAND_RETRIES + self.log_level = log_level + self.inputs = [self.ec_uart_pty, self.cmd_pipe] + self.outputs = [] + self.ec_cmd_queue = six.moves.queue.Queue() + self.last_cmd = b"" + self.enhanced_ec = False + self.interrogating = False + self.connected = True - # If no command is pending to be sent, then we can remove the EC UART from - # writers. Might need better checking for command retry logic in here. - if self.ec_cmd_queue.empty(): - # Remove the EC UART from the writers while we wait for a response. - self.logger.debug('Removing EC UART from writers.') - self.outputs.remove(self.ec_uart_pty) - - def HandleECData(self): - """Handle any debug prints from the EC.""" - self.logger.log(1, 'EC has data') - # Read what the EC sent us. - data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ) - self.logger.log(1, 'got: \'%s\'', binascii.hexlify(data)) - if b'&E' in data and self.enhanced_ec: - # We received an error, so we should retry it if possible. - self.logger.warning('Error string found in data.') - self.HandleCmdRetries() - return - - # If we were interrogating, check the response and update our knowledge - # of the current EC image. - if self.interrogating: - self.enhanced_ec = data == EC_ACK - if self.enhanced_ec: - self.logger.debug('The current EC image seems enhanced.') - else: - self.logger.debug('The current EC image does NOT seem enhanced.') - # Done interrogating. - self.interrogating = False - # For now, just forward everything the EC sends us. - self.logger.log(1, 'Forwarding to user...') - self.dbg_pipe.send(data) - - def HandleUserData(self): - """Handle any incoming commands from the user. - - Raises: - EOFError: Allowed to propagate through from self.cmd_pipe.recv(). - """ - self.logger.log(1, 'Command data available. Begin processing.') - data = self.cmd_pipe.recv() - # Process the command. - self.ProcessCommand(data) + def __str__(self): + """Show internal state of the Interpreter object. + + Returns: + A string that shows the values of the attributes. + """ + string = [] + string.append("%r" % self) + string.append("ec_uart_pty: %s" % self.ec_uart_pty) + string.append("cmd_pipe: %r" % self.cmd_pipe) + string.append("dbg_pipe: %r" % self.dbg_pipe) + string.append("cmd_retries: %d" % self.cmd_retries) + string.append("log_level: %d" % self.log_level) + string.append("inputs: %r" % self.inputs) + string.append("outputs: %r" % self.outputs) + string.append("ec_cmd_queue: %r" % self.ec_cmd_queue) + string.append("last_cmd: '%s'" % self.last_cmd) + string.append("enhanced_ec: %r" % self.enhanced_ec) + string.append("interrogating: %r" % self.interrogating) + return "\n".join(string) + + def EnqueueCmd(self, command): + """Enqueue a command to be sent to the EC UART. + + Args: + command: A string which contains the command to be sent. + """ + self.ec_cmd_queue.put(command) + self.logger.log(1, "Commands now in queue: %d", self.ec_cmd_queue.qsize()) + + # Add the EC UART as an output to be serviced. + if self.connected and self.ec_uart_pty not in self.outputs: + self.outputs.append(self.ec_uart_pty) + + def PackCommand(self, raw_cmd): + r"""Packs a command for use with error checking. + + For error checking, we pack console commands in a particular format. The + format is as follows: + + &&[x][x][x][x]&{cmd}\n\n + ^ ^ ^^ ^^ ^ ^-- 2 newlines. + | | || || |-- the raw console command. + | | || ||-- 1 ampersand. + | | ||____|--- 2 hex digits representing the CRC8 of cmd. + | |____|-- 2 hex digits reprsenting the length of cmd. + |-- 2 ampersands + + Args: + raw_cmd: A pre-packed string which contains the raw command. + + Returns: + A string which contains the packed command. + """ + # Don't pack a single carriage return. + if raw_cmd != b"\r": + # The command format is as follows. + # &&[x][x][x][x]&{cmd}\n\n + packed_cmd = [] + packed_cmd.append(b"&&") + # The first pair of hex digits are the length of the command. + packed_cmd.append(b"%02x" % len(raw_cmd)) + # Then the CRC8 of cmd. + packed_cmd.append(b"%02x" % Crc8(raw_cmd)) + packed_cmd.append(b"&") + # Now, the raw command followed by 2 newlines. + packed_cmd.append(raw_cmd) + packed_cmd.append(b"\n\n") + return b"".join(packed_cmd) + else: + return raw_cmd + + def ProcessCommand(self, command): + """Captures the input determines what actions to take. + + Args: + command: A string representing the command sent by the user. + """ + if command == b"disconnect": + if self.connected: + self.logger.debug("UART disconnect request.") + # Drop all pending commands if any. + while not self.ec_cmd_queue.empty(): + c = self.ec_cmd_queue.get() + self.logger.debug("dropped: '%s'", c) + if self.enhanced_ec: + # Reset retry state. + self.cmd_retries = COMMAND_RETRIES + self.last_cmd = b"" + # Get the UART that the interpreter is attached to. + fileobj = self.ec_uart_pty + self.logger.debug("fileobj: %r", fileobj) + # Remove the descriptor from the inputs and outputs. + self.inputs.remove(fileobj) + if fileobj in self.outputs: + self.outputs.remove(fileobj) + self.logger.debug("Removed fileobj. Remaining inputs: %r", self.inputs) + # Close the file. + fileobj.close() + # Mark the interpreter as disconnected now. + self.connected = False + self.logger.debug("Disconnected from %s.", self.ec_uart_pty_name) + return + + elif command == b"reconnect": + if not self.connected: + self.logger.debug("UART reconnect request.") + # Reopen the PTY. + # TODO(https://bugs.python.org/issue27805, python3.7+): revert to ab+ + # TODO(https://bugs.python.org/issue20074): removing buffering=0 if/when + # that gets fixed, or keep two pty: one for reading and one for writing + fileobj = open(self.ec_uart_pty_name, "r+b", buffering=0) + self.logger.debug("fileobj: %r", fileobj) + self.ec_uart_pty = fileobj + # Add the descriptor to the inputs. + self.inputs.append(fileobj) + self.logger.debug("fileobj added. curr inputs: %r", self.inputs) + # Mark the interpreter as connected now. + self.connected = True + self.logger.debug("Connected to %s.", self.ec_uart_pty_name) + return + + elif command.startswith(b"enhanced"): + self.enhanced_ec = command.split(b" ")[1] == b"True" + return + + # Ignore any other commands while in the disconnected state. + self.logger.log(1, "command: '%s'", command) + if not self.connected: + self.logger.debug("Ignoring command because currently disconnected.") + return + + # Remove leading and trailing spaces only if this is an enhanced EC image. + # For non-enhanced EC images, commands will be single characters at a time + # and can be spaces. + if self.enhanced_ec: + command = command.strip(b" ") + + # There's nothing to do if the command is empty. + if len(command) == 0: + return + + # Handle log level change requests. + if command.startswith(b"loglevel"): + self.logger.debug("Log level change request.") + new_log_level = int(command.split(b" ")[1]) + self.logger.logger.setLevel(new_log_level) + self.logger.info("Log level changed to %d.", new_log_level) + return + + # Check for interrogation command. + if command == EC_SYN: + # User is requesting interrogation. Send SYN as is. + self.logger.debug("User requesting interrogation.") + self.interrogating = True + # Assume the EC isn't enhanced until we get a response. + self.enhanced_ec = False + elif self.enhanced_ec: + # Enhanced EC images require the plaintext commands to be packed. + command = self.PackCommand(command) + # TODO(aaboagye): Make a dict of commands and keys and eventually, + # handle partial matching based on unique prefixes. + + self.EnqueueCmd(command) + + def HandleCmdRetries(self): + """Attempts to retry commands if possible.""" + if self.cmd_retries > 0: + # The EC encountered an error. We'll have to retry again. + self.logger.warning("Retrying command...") + self.cmd_retries -= 1 + self.logger.warning("Retries remaining: %d", self.cmd_retries) + # Retry the command and add the EC UART to the writers again. + self.EnqueueCmd(self.last_cmd) + self.outputs.append(self.ec_uart_pty) + else: + # We're out of retries, so just give up. + self.logger.error("Command failed. No retries left.") + # Clear the command in progress. + self.last_cmd = b"" + # Reset the retry count. + self.cmd_retries = COMMAND_RETRIES + + def SendCmdToEC(self): + """Sends a command to the EC.""" + # If we're retrying a command, just try to send it again. + if self.cmd_retries < COMMAND_RETRIES: + cmd = self.last_cmd + else: + # If we're not retrying, we should not be writing to the EC if we have no + # items in our command queue. + assert not self.ec_cmd_queue.empty() + # Get the command to send. + cmd = self.ec_cmd_queue.get() + + # Send the command. + self.ec_uart_pty.write(cmd) + self.ec_uart_pty.flush() + self.logger.log(1, "Sent command to EC.") + + if self.enhanced_ec and cmd != EC_SYN: + # Now, that we've sent the command, store the current command as the last + # command sent. If we encounter an error string, we will attempt to retry + # this command. + if cmd != self.last_cmd: + self.last_cmd = cmd + # Reset the retry count. + self.cmd_retries = COMMAND_RETRIES + + # If no command is pending to be sent, then we can remove the EC UART from + # writers. Might need better checking for command retry logic in here. + if self.ec_cmd_queue.empty(): + # Remove the EC UART from the writers while we wait for a response. + self.logger.debug("Removing EC UART from writers.") + self.outputs.remove(self.ec_uart_pty) + + def HandleECData(self): + """Handle any debug prints from the EC.""" + self.logger.log(1, "EC has data") + # Read what the EC sent us. + data = os.read(self.ec_uart_pty.fileno(), EC_MAX_READ) + self.logger.log(1, "got: '%s'", binascii.hexlify(data)) + if b"&E" in data and self.enhanced_ec: + # We received an error, so we should retry it if possible. + self.logger.warning("Error string found in data.") + self.HandleCmdRetries() + return + + # If we were interrogating, check the response and update our knowledge + # of the current EC image. + if self.interrogating: + self.enhanced_ec = data == EC_ACK + if self.enhanced_ec: + self.logger.debug("The current EC image seems enhanced.") + else: + self.logger.debug("The current EC image does NOT seem enhanced.") + # Done interrogating. + self.interrogating = False + # For now, just forward everything the EC sends us. + self.logger.log(1, "Forwarding to user...") + self.dbg_pipe.send(data) + + def HandleUserData(self): + """Handle any incoming commands from the user. + + Raises: + EOFError: Allowed to propagate through from self.cmd_pipe.recv(). + """ + self.logger.log(1, "Command data available. Begin processing.") + data = self.cmd_pipe.recv() + # Process the command. + self.ProcessCommand(data) def Crc8(data): - """Calculates the CRC8 of data. + """Calculates the CRC8 of data. - The generator polynomial used is: x^8 + x^2 + x + 1. - This is the same implementation that is used in the EC. + The generator polynomial used is: x^8 + x^2 + x + 1. + This is the same implementation that is used in the EC. - Args: - data: A string of data that we wish to calculate the CRC8 on. + Args: + data: A string of data that we wish to calculate the CRC8 on. - Returns: - crc >> 8: An integer representing the CRC8 value. - """ - crc = 0 - for byte in six.iterbytes(data): - crc ^= (byte << 8) - for _ in range(8): - if crc & 0x8000: - crc ^= (0x1070 << 3) - crc <<= 1 - return crc >> 8 + Returns: + crc >> 8: An integer representing the CRC8 value. + """ + crc = 0 + for byte in six.iterbytes(data): + crc ^= byte << 8 + for _ in range(8): + if crc & 0x8000: + crc ^= 0x1070 << 3 + crc <<= 1 + return crc >> 8 def StartLoop(interp, shutdown_pipe=None): - """Starts an infinite loop of servicing the user and the EC. - - StartLoop checks to see if there are any commands to process, processing them - if any, and forwards EC output to the user. - - When sending a command to the EC, we send the command once and check the - response to see if the EC encountered an error when receiving the command. An - error condition is reported to the interpreter by a string with at least one - '&' and 'E'. The full string is actually '&&EE', however it's possible that - the leading ampersand or trailing 'E' could be dropped. If an error is - encountered, the interpreter will retry up to the amount configured. - - Args: - interp: An Interpreter object that has been properly initialised. - shutdown_pipe: A file object for a pipe or equivalent that becomes readable - (not blocked) to indicate that the loop should exit. Can be None to never - exit the loop. - """ - try: - # This is used instead of "break" to avoid exiting the loop in the middle of - # an iteration. - continue_looping = True - - while continue_looping: - # The inputs list is created anew in each loop iteration because the - # Interpreter class sometimes modifies the interp.inputs list. - if shutdown_pipe is None: - inputs = interp.inputs - else: - inputs = list(interp.inputs) - inputs.append(shutdown_pipe) - - readable, writeable, _ = select.select(inputs, interp.outputs, []) - - for obj in readable: - # Handle any debug prints from the EC. - if obj is interp.ec_uart_pty: - interp.HandleECData() - - # Handle any commands from the user. - elif obj is interp.cmd_pipe: - try: - interp.HandleUserData() - except EOFError: - interp.logger.debug( - 'ec3po interpreter received EOF from cmd_pipe in ' - 'HandleUserData()') - continue_looping = False - - elif obj is shutdown_pipe: - interp.logger.debug( - 'ec3po interpreter received shutdown pipe unblocked notification') - continue_looping = False - - for obj in writeable: - # Send a command to the EC. - if obj is interp.ec_uart_pty: - interp.SendCmdToEC() - - except KeyboardInterrupt: - pass - - finally: - interp.cmd_pipe.close() - interp.dbg_pipe.close() - interp.ec_uart_pty.close() - if shutdown_pipe is not None: - shutdown_pipe.close() - interp.logger.debug('Exit ec3po interpreter loop for %s', - interp.ec_uart_pty_name) + """Starts an infinite loop of servicing the user and the EC. + + StartLoop checks to see if there are any commands to process, processing them + if any, and forwards EC output to the user. + + When sending a command to the EC, we send the command once and check the + response to see if the EC encountered an error when receiving the command. An + error condition is reported to the interpreter by a string with at least one + '&' and 'E'. The full string is actually '&&EE', however it's possible that + the leading ampersand or trailing 'E' could be dropped. If an error is + encountered, the interpreter will retry up to the amount configured. + + Args: + interp: An Interpreter object that has been properly initialised. + shutdown_pipe: A file object for a pipe or equivalent that becomes readable + (not blocked) to indicate that the loop should exit. Can be None to never + exit the loop. + """ + try: + # This is used instead of "break" to avoid exiting the loop in the middle of + # an iteration. + continue_looping = True + + while continue_looping: + # The inputs list is created anew in each loop iteration because the + # Interpreter class sometimes modifies the interp.inputs list. + if shutdown_pipe is None: + inputs = interp.inputs + else: + inputs = list(interp.inputs) + inputs.append(shutdown_pipe) + + readable, writeable, _ = select.select(inputs, interp.outputs, []) + + for obj in readable: + # Handle any debug prints from the EC. + if obj is interp.ec_uart_pty: + interp.HandleECData() + + # Handle any commands from the user. + elif obj is interp.cmd_pipe: + try: + interp.HandleUserData() + except EOFError: + interp.logger.debug( + "ec3po interpreter received EOF from cmd_pipe in " + "HandleUserData()" + ) + continue_looping = False + + elif obj is shutdown_pipe: + interp.logger.debug( + "ec3po interpreter received shutdown pipe unblocked notification" + ) + continue_looping = False + + for obj in writeable: + # Send a command to the EC. + if obj is interp.ec_uart_pty: + interp.SendCmdToEC() + + except KeyboardInterrupt: + pass + + finally: + interp.cmd_pipe.close() + interp.dbg_pipe.close() + interp.ec_uart_pty.close() + if shutdown_pipe is not None: + shutdown_pipe.close() + interp.logger.debug( + "Exit ec3po interpreter loop for %s", interp.ec_uart_pty_name + ) diff --git a/util/ec3po/interpreter_unittest.py b/util/ec3po/interpreter_unittest.py index fe4d43c351..509b90f667 100755 --- a/util/ec3po/interpreter_unittest.py +++ b/util/ec3po/interpreter_unittest.py @@ -10,371 +10,389 @@ from __future__ import print_function import logging -import mock import tempfile import unittest +import mock import six - -from ec3po import interpreter -from ec3po import threadproc_shim +from ec3po import interpreter, threadproc_shim def GetBuiltins(func): - if six.PY2: - return '__builtin__.' + func - return 'builtins.' + func + if six.PY2: + return "__builtin__." + func + return "builtins." + func class TestEnhancedECBehaviour(unittest.TestCase): - """Test case to verify all enhanced EC interpretation tasks.""" - def setUp(self): - """Setup the test harness.""" - # Setup logging with a timestamp, the module, and the log level. - logging.basicConfig(level=logging.DEBUG, - format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - - # Create a tempfile that would represent the EC UART PTY. - self.tempfile = tempfile.NamedTemporaryFile() - - # Create the pipes that the interpreter will use. - self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe() - self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False) - - # Mock the open() function so we can inspect reads/writes to the EC. - self.ec_uart_pty = mock.mock_open() - - with mock.patch(GetBuiltins('open'), self.ec_uart_pty): - # Create an interpreter. - self.itpr = interpreter.Interpreter(self.tempfile.name, - self.cmd_pipe_itpr, - self.dbg_pipe_itpr, - log_level=logging.DEBUG, - name="EC") - - @mock.patch('ec3po.interpreter.os') - def test_HandlingCommandsThatProduceNoOutput(self, mock_os): - """Verify that the Interpreter correctly handles non-output commands. - - Args: - mock_os: MagicMock object replacing the 'os' module for this test - case. - """ - # The interpreter init should open the EC UART PTY. - expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)] - # Have a command come in the command pipe. The first command will be an - # interrogation to determine if the EC is enhanced or not. - self.cmd_pipe_user.send(interpreter.EC_SYN) - self.itpr.HandleUserData() - # At this point, the command should be queued up waiting to be sent, so - # let's actually send it to the EC. - self.itpr.SendCmdToEC() - expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN), - mock.call().flush()]) - # Now, assume that the EC sends only 1 response back of EC_ACK. - mock_os.read.side_effect = [interpreter.EC_ACK] - # When reading the EC, the interpreter will call file.fileno() to pass to - # os.read(). - expected_ec_calls.append(mock.call().fileno()) - # Simulate the response. - self.itpr.HandleECData() - - # Now that the interrogation was complete, it's time to send down the real - # command. - test_cmd = b'chan save' - # Send the test command down the pipe. - self.cmd_pipe_user.send(test_cmd) - self.itpr.HandleUserData() - self.itpr.SendCmdToEC() - # Since the EC image is enhanced, we should have sent a packed command. - expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd))) - expected_ec_calls.append(mock.call().flush()) - - # Now that the first command was sent, we should send another command which - # produces no output. The console would send another interrogation. - self.cmd_pipe_user.send(interpreter.EC_SYN) - self.itpr.HandleUserData() - self.itpr.SendCmdToEC() - expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN), - mock.call().flush()]) - # Again, assume that the EC sends only 1 response back of EC_ACK. - mock_os.read.side_effect = [interpreter.EC_ACK] - # When reading the EC, the interpreter will call file.fileno() to pass to - # os.read(). - expected_ec_calls.append(mock.call().fileno()) - # Simulate the response. - self.itpr.HandleECData() - - # Now send the second test command. - test_cmd = b'chan 0' - self.cmd_pipe_user.send(test_cmd) - self.itpr.HandleUserData() - self.itpr.SendCmdToEC() - # Since the EC image is enhanced, we should have sent a packed command. - expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd))) - expected_ec_calls.append(mock.call().flush()) - - # Finally, verify that the appropriate writes were actually sent to the EC. - self.ec_uart_pty.assert_has_calls(expected_ec_calls) - - @mock.patch('ec3po.interpreter.os') - def test_CommandRetryingOnError(self, mock_os): - """Verify that commands are retried if an error is encountered. - - Args: - mock_os: MagicMock object replacing the 'os' module for this test - case. - """ - # The interpreter init should open the EC UART PTY. - expected_ec_calls = [mock.call(self.tempfile.name, 'r+b', buffering=0)] - # Have a command come in the command pipe. The first command will be an - # interrogation to determine if the EC is enhanced or not. - self.cmd_pipe_user.send(interpreter.EC_SYN) - self.itpr.HandleUserData() - # At this point, the command should be queued up waiting to be sent, so - # let's actually send it to the EC. - self.itpr.SendCmdToEC() - expected_ec_calls.extend([mock.call().write(interpreter.EC_SYN), - mock.call().flush()]) - # Now, assume that the EC sends only 1 response back of EC_ACK. - mock_os.read.side_effect = [interpreter.EC_ACK] - # When reading the EC, the interpreter will call file.fileno() to pass to - # os.read(). - expected_ec_calls.append(mock.call().fileno()) - # Simulate the response. - self.itpr.HandleECData() - - # Let's send a command that is received on the EC-side with an error. - test_cmd = b'accelinfo' - self.cmd_pipe_user.send(test_cmd) - self.itpr.HandleUserData() - self.itpr.SendCmdToEC() - packed_cmd = self.itpr.PackCommand(test_cmd) - expected_ec_calls.extend([mock.call().write(packed_cmd), - mock.call().flush()]) - # Have the EC return the error string twice. - mock_os.read.side_effect = [b'&&EE', b'&&EE'] - for i in range(2): - # When reading the EC, the interpreter will call file.fileno() to pass to - # os.read(). - expected_ec_calls.append(mock.call().fileno()) - # Simulate the response. - self.itpr.HandleECData() - - # Since an error was received, the EC should attempt to retry the command. - expected_ec_calls.extend([mock.call().write(packed_cmd), - mock.call().flush()]) - # Verify that the retry count was decremented. - self.assertEqual(interpreter.COMMAND_RETRIES-i-1, self.itpr.cmd_retries, - 'Unexpected cmd_remaining count.') - # Actually retry the command. - self.itpr.SendCmdToEC() - - # Now assume that the last one goes through with no trouble. - expected_ec_calls.extend([mock.call().write(packed_cmd), - mock.call().flush()]) - self.itpr.SendCmdToEC() - - # Verify all the calls. - self.ec_uart_pty.assert_has_calls(expected_ec_calls) - - def test_PackCommandsForEnhancedEC(self): - """Verify that the interpreter packs commands for enhanced EC images.""" - # Assume current EC image is enhanced. - self.itpr.enhanced_ec = True - # Receive a command from the user. - test_cmd = b'gettime' - self.cmd_pipe_user.send(test_cmd) - # Mock out PackCommand to see if it was called. - self.itpr.PackCommand = mock.MagicMock() - # Have the interpreter handle the command. - self.itpr.HandleUserData() - # Verify that PackCommand() was called. - self.itpr.PackCommand.assert_called_once_with(test_cmd) - - def test_DontPackCommandsForNonEnhancedEC(self): - """Verify the interpreter doesn't pack commands for non-enhanced images.""" - # Assume current EC image is not enhanced. - self.itpr.enhanced_ec = False - # Receive a command from the user. - test_cmd = b'gettime' - self.cmd_pipe_user.send(test_cmd) - # Mock out PackCommand to see if it was called. - self.itpr.PackCommand = mock.MagicMock() - # Have the interpreter handle the command. - self.itpr.HandleUserData() - # Verify that PackCommand() was called. - self.itpr.PackCommand.assert_not_called() - - @mock.patch('ec3po.interpreter.os') - def test_KeepingTrackOfInterrogation(self, mock_os): - """Verify that the interpreter can track the state of the interrogation. - - Args: - mock_os: MagicMock object replacing the 'os' module. for this test - case. - """ - # Upon init, the interpreter should assume that the current EC image is not - # enhanced. - self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec upon' - ' init is not False.')) - - # Assume an interrogation request comes in from the user. - self.cmd_pipe_user.send(interpreter.EC_SYN) - self.itpr.HandleUserData() - - # Verify the state is now within an interrogation. - self.assertTrue(self.itpr.interrogating, 'interrogating should be True') - # The state of enhanced_ec should not be changed yet because we haven't - # received a valid response yet. - self.assertFalse(self.itpr.enhanced_ec, msg=('State of enhanced_ec is ' - 'not False.')) - - # Assume that the EC responds with an EC_ACK. - mock_os.read.side_effect = [interpreter.EC_ACK] - self.itpr.HandleECData() - - # Now, the interrogation should be complete and we should know that the - # current EC image is enhanced. - self.assertFalse(self.itpr.interrogating, msg=('interrogating should be ' - 'False')) - self.assertTrue(self.itpr.enhanced_ec, msg='enhanced_ec sholud be True') - - # Now let's perform another interrogation, but pretend that the EC ignores - # it. - self.cmd_pipe_user.send(interpreter.EC_SYN) - self.itpr.HandleUserData() - - # Verify interrogating state. - self.assertTrue(self.itpr.interrogating, 'interrogating sholud be True') - # We should assume that the image is not enhanced until we get the valid - # response. - self.assertFalse(self.itpr.enhanced_ec, 'enhanced_ec should be False now.') - - # Let's pretend that we get a random debug print. This should clear the - # interrogating flag. - mock_os.read.side_effect = [b'[1660.593076 HC 0x103]'] - self.itpr.HandleECData() - - # Verify that interrogating flag is cleared and enhanced_ec is still False. - self.assertFalse(self.itpr.interrogating, 'interrogating should be False.') - self.assertFalse(self.itpr.enhanced_ec, - 'enhanced_ec should still be False.') + """Test case to verify all enhanced EC interpretation tasks.""" + + def setUp(self): + """Setup the test harness.""" + # Setup logging with a timestamp, the module, and the log level. + logging.basicConfig( + level=logging.DEBUG, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + + # Create a tempfile that would represent the EC UART PTY. + self.tempfile = tempfile.NamedTemporaryFile() + + # Create the pipes that the interpreter will use. + self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe() + self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False) + + # Mock the open() function so we can inspect reads/writes to the EC. + self.ec_uart_pty = mock.mock_open() + + with mock.patch(GetBuiltins("open"), self.ec_uart_pty): + # Create an interpreter. + self.itpr = interpreter.Interpreter( + self.tempfile.name, + self.cmd_pipe_itpr, + self.dbg_pipe_itpr, + log_level=logging.DEBUG, + name="EC", + ) + + @mock.patch("ec3po.interpreter.os") + def test_HandlingCommandsThatProduceNoOutput(self, mock_os): + """Verify that the Interpreter correctly handles non-output commands. + + Args: + mock_os: MagicMock object replacing the 'os' module for this test + case. + """ + # The interpreter init should open the EC UART PTY. + expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)] + # Have a command come in the command pipe. The first command will be an + # interrogation to determine if the EC is enhanced or not. + self.cmd_pipe_user.send(interpreter.EC_SYN) + self.itpr.HandleUserData() + # At this point, the command should be queued up waiting to be sent, so + # let's actually send it to the EC. + self.itpr.SendCmdToEC() + expected_ec_calls.extend( + [mock.call().write(interpreter.EC_SYN), mock.call().flush()] + ) + # Now, assume that the EC sends only 1 response back of EC_ACK. + mock_os.read.side_effect = [interpreter.EC_ACK] + # When reading the EC, the interpreter will call file.fileno() to pass to + # os.read(). + expected_ec_calls.append(mock.call().fileno()) + # Simulate the response. + self.itpr.HandleECData() + + # Now that the interrogation was complete, it's time to send down the real + # command. + test_cmd = b"chan save" + # Send the test command down the pipe. + self.cmd_pipe_user.send(test_cmd) + self.itpr.HandleUserData() + self.itpr.SendCmdToEC() + # Since the EC image is enhanced, we should have sent a packed command. + expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd))) + expected_ec_calls.append(mock.call().flush()) + + # Now that the first command was sent, we should send another command which + # produces no output. The console would send another interrogation. + self.cmd_pipe_user.send(interpreter.EC_SYN) + self.itpr.HandleUserData() + self.itpr.SendCmdToEC() + expected_ec_calls.extend( + [mock.call().write(interpreter.EC_SYN), mock.call().flush()] + ) + # Again, assume that the EC sends only 1 response back of EC_ACK. + mock_os.read.side_effect = [interpreter.EC_ACK] + # When reading the EC, the interpreter will call file.fileno() to pass to + # os.read(). + expected_ec_calls.append(mock.call().fileno()) + # Simulate the response. + self.itpr.HandleECData() + + # Now send the second test command. + test_cmd = b"chan 0" + self.cmd_pipe_user.send(test_cmd) + self.itpr.HandleUserData() + self.itpr.SendCmdToEC() + # Since the EC image is enhanced, we should have sent a packed command. + expected_ec_calls.append(mock.call().write(self.itpr.PackCommand(test_cmd))) + expected_ec_calls.append(mock.call().flush()) + + # Finally, verify that the appropriate writes were actually sent to the EC. + self.ec_uart_pty.assert_has_calls(expected_ec_calls) + + @mock.patch("ec3po.interpreter.os") + def test_CommandRetryingOnError(self, mock_os): + """Verify that commands are retried if an error is encountered. + + Args: + mock_os: MagicMock object replacing the 'os' module for this test + case. + """ + # The interpreter init should open the EC UART PTY. + expected_ec_calls = [mock.call(self.tempfile.name, "r+b", buffering=0)] + # Have a command come in the command pipe. The first command will be an + # interrogation to determine if the EC is enhanced or not. + self.cmd_pipe_user.send(interpreter.EC_SYN) + self.itpr.HandleUserData() + # At this point, the command should be queued up waiting to be sent, so + # let's actually send it to the EC. + self.itpr.SendCmdToEC() + expected_ec_calls.extend( + [mock.call().write(interpreter.EC_SYN), mock.call().flush()] + ) + # Now, assume that the EC sends only 1 response back of EC_ACK. + mock_os.read.side_effect = [interpreter.EC_ACK] + # When reading the EC, the interpreter will call file.fileno() to pass to + # os.read(). + expected_ec_calls.append(mock.call().fileno()) + # Simulate the response. + self.itpr.HandleECData() + + # Let's send a command that is received on the EC-side with an error. + test_cmd = b"accelinfo" + self.cmd_pipe_user.send(test_cmd) + self.itpr.HandleUserData() + self.itpr.SendCmdToEC() + packed_cmd = self.itpr.PackCommand(test_cmd) + expected_ec_calls.extend([mock.call().write(packed_cmd), mock.call().flush()]) + # Have the EC return the error string twice. + mock_os.read.side_effect = [b"&&EE", b"&&EE"] + for i in range(2): + # When reading the EC, the interpreter will call file.fileno() to pass to + # os.read(). + expected_ec_calls.append(mock.call().fileno()) + # Simulate the response. + self.itpr.HandleECData() + + # Since an error was received, the EC should attempt to retry the command. + expected_ec_calls.extend( + [mock.call().write(packed_cmd), mock.call().flush()] + ) + # Verify that the retry count was decremented. + self.assertEqual( + interpreter.COMMAND_RETRIES - i - 1, + self.itpr.cmd_retries, + "Unexpected cmd_remaining count.", + ) + # Actually retry the command. + self.itpr.SendCmdToEC() + + # Now assume that the last one goes through with no trouble. + expected_ec_calls.extend([mock.call().write(packed_cmd), mock.call().flush()]) + self.itpr.SendCmdToEC() + + # Verify all the calls. + self.ec_uart_pty.assert_has_calls(expected_ec_calls) + + def test_PackCommandsForEnhancedEC(self): + """Verify that the interpreter packs commands for enhanced EC images.""" + # Assume current EC image is enhanced. + self.itpr.enhanced_ec = True + # Receive a command from the user. + test_cmd = b"gettime" + self.cmd_pipe_user.send(test_cmd) + # Mock out PackCommand to see if it was called. + self.itpr.PackCommand = mock.MagicMock() + # Have the interpreter handle the command. + self.itpr.HandleUserData() + # Verify that PackCommand() was called. + self.itpr.PackCommand.assert_called_once_with(test_cmd) + + def test_DontPackCommandsForNonEnhancedEC(self): + """Verify the interpreter doesn't pack commands for non-enhanced images.""" + # Assume current EC image is not enhanced. + self.itpr.enhanced_ec = False + # Receive a command from the user. + test_cmd = b"gettime" + self.cmd_pipe_user.send(test_cmd) + # Mock out PackCommand to see if it was called. + self.itpr.PackCommand = mock.MagicMock() + # Have the interpreter handle the command. + self.itpr.HandleUserData() + # Verify that PackCommand() was called. + self.itpr.PackCommand.assert_not_called() + + @mock.patch("ec3po.interpreter.os") + def test_KeepingTrackOfInterrogation(self, mock_os): + """Verify that the interpreter can track the state of the interrogation. + + Args: + mock_os: MagicMock object replacing the 'os' module. for this test + case. + """ + # Upon init, the interpreter should assume that the current EC image is not + # enhanced. + self.assertFalse( + self.itpr.enhanced_ec, + msg=("State of enhanced_ec upon" " init is not False."), + ) + + # Assume an interrogation request comes in from the user. + self.cmd_pipe_user.send(interpreter.EC_SYN) + self.itpr.HandleUserData() + + # Verify the state is now within an interrogation. + self.assertTrue(self.itpr.interrogating, "interrogating should be True") + # The state of enhanced_ec should not be changed yet because we haven't + # received a valid response yet. + self.assertFalse( + self.itpr.enhanced_ec, msg=("State of enhanced_ec is " "not False.") + ) + + # Assume that the EC responds with an EC_ACK. + mock_os.read.side_effect = [interpreter.EC_ACK] + self.itpr.HandleECData() + + # Now, the interrogation should be complete and we should know that the + # current EC image is enhanced. + self.assertFalse( + self.itpr.interrogating, msg=("interrogating should be " "False") + ) + self.assertTrue(self.itpr.enhanced_ec, msg="enhanced_ec sholud be True") + + # Now let's perform another interrogation, but pretend that the EC ignores + # it. + self.cmd_pipe_user.send(interpreter.EC_SYN) + self.itpr.HandleUserData() + + # Verify interrogating state. + self.assertTrue(self.itpr.interrogating, "interrogating sholud be True") + # We should assume that the image is not enhanced until we get the valid + # response. + self.assertFalse(self.itpr.enhanced_ec, "enhanced_ec should be False now.") + + # Let's pretend that we get a random debug print. This should clear the + # interrogating flag. + mock_os.read.side_effect = [b"[1660.593076 HC 0x103]"] + self.itpr.HandleECData() + + # Verify that interrogating flag is cleared and enhanced_ec is still False. + self.assertFalse(self.itpr.interrogating, "interrogating should be False.") + self.assertFalse(self.itpr.enhanced_ec, "enhanced_ec should still be False.") class TestUARTDisconnection(unittest.TestCase): - """Test case to verify interpreter disconnection/reconnection.""" - def setUp(self): - """Setup the test harness.""" - # Setup logging with a timestamp, the module, and the log level. - logging.basicConfig(level=logging.DEBUG, - format=('%(asctime)s - %(module)s -' - ' %(levelname)s - %(message)s')) - - # Create a tempfile that would represent the EC UART PTY. - self.tempfile = tempfile.NamedTemporaryFile() - - # Create the pipes that the interpreter will use. - self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe() - self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False) - - # Mock the open() function so we can inspect reads/writes to the EC. - self.ec_uart_pty = mock.mock_open() - - with mock.patch(GetBuiltins('open'), self.ec_uart_pty): - # Create an interpreter. - self.itpr = interpreter.Interpreter(self.tempfile.name, - self.cmd_pipe_itpr, - self.dbg_pipe_itpr, - log_level=logging.DEBUG, - name="EC") - - # First, check that interpreter is initialized to connected. - self.assertTrue(self.itpr.connected, ('The interpreter should be' - ' initialized in a connected state')) - - def test_DisconnectStopsECTraffic(self): - """Verify that when in disconnected state, no debug prints are sent.""" - # Let's send a disconnect command through the command pipe. - self.cmd_pipe_user.send(b'disconnect') - self.itpr.HandleUserData() - - # Verify interpreter is disconnected from EC. - self.assertFalse(self.itpr.connected, ('The interpreter should be' - 'disconnected.')) - # Verify that the EC UART is no longer a member of the inputs. The - # interpreter will never pull data from the EC if it's not a member of the - # inputs list. - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) - - def test_CommandsDroppedWhenDisconnected(self): - """Verify that when in disconnected state, commands are dropped.""" - # Send a command, followed by 'disconnect'. - self.cmd_pipe_user.send(b'taskinfo') - self.itpr.HandleUserData() - self.cmd_pipe_user.send(b'disconnect') - self.itpr.HandleUserData() - - # Verify interpreter is disconnected from EC. - self.assertFalse(self.itpr.connected, ('The interpreter should be' - 'disconnected.')) - # Verify that the EC UART is no longer a member of the inputs nor outputs. - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) - - # Have the user send a few more commands in the disconnected state. - command = 'help\n' - for char in command: - self.cmd_pipe_user.send(char.encode('utf-8')) - self.itpr.HandleUserData() - - # The command queue should be empty. - self.assertEqual(0, self.itpr.ec_cmd_queue.qsize()) - - # Now send the reconnect command. - self.cmd_pipe_user.send(b'reconnect') - - with mock.patch(GetBuiltins('open'), mock.mock_open()): - self.itpr.HandleUserData() - - # Verify interpreter is connected. - self.assertTrue(self.itpr.connected) - # Verify that EC UART is a member of the inputs. - self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs) - # Since no command was sent after reconnection, verify that the EC UART is - # not a member of the outputs. - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) - - def test_ReconnectAllowsECTraffic(self): - """Verify that when connected, EC UART traffic is allowed.""" - # Let's send a disconnect command through the command pipe. - self.cmd_pipe_user.send(b'disconnect') - self.itpr.HandleUserData() - - # Verify interpreter is disconnected. - self.assertFalse(self.itpr.connected, ('The interpreter should be' - 'disconnected.')) - # Verify that the EC UART is no longer a member of the inputs nor outputs. - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) - - # Issue reconnect command through the command pipe. - self.cmd_pipe_user.send(b'reconnect') - - with mock.patch(GetBuiltins('open'), mock.mock_open()): - self.itpr.HandleUserData() - - # Verify interpreter is connected. - self.assertTrue(self.itpr.connected, ('The interpreter should be' - 'connected.')) - # Verify that the EC UART is now a member of the inputs. - self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs) - # Since we have issued no commands during the disconnected state, no - # commands are pending and therefore the PTY should not be added to the - # outputs. - self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) - - -if __name__ == '__main__': - unittest.main() + """Test case to verify interpreter disconnection/reconnection.""" + + def setUp(self): + """Setup the test harness.""" + # Setup logging with a timestamp, the module, and the log level. + logging.basicConfig( + level=logging.DEBUG, + format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + ) + + # Create a tempfile that would represent the EC UART PTY. + self.tempfile = tempfile.NamedTemporaryFile() + + # Create the pipes that the interpreter will use. + self.cmd_pipe_user, self.cmd_pipe_itpr = threadproc_shim.Pipe() + self.dbg_pipe_user, self.dbg_pipe_itpr = threadproc_shim.Pipe(duplex=False) + + # Mock the open() function so we can inspect reads/writes to the EC. + self.ec_uart_pty = mock.mock_open() + + with mock.patch(GetBuiltins("open"), self.ec_uart_pty): + # Create an interpreter. + self.itpr = interpreter.Interpreter( + self.tempfile.name, + self.cmd_pipe_itpr, + self.dbg_pipe_itpr, + log_level=logging.DEBUG, + name="EC", + ) + + # First, check that interpreter is initialized to connected. + self.assertTrue( + self.itpr.connected, + ("The interpreter should be" " initialized in a connected state"), + ) + + def test_DisconnectStopsECTraffic(self): + """Verify that when in disconnected state, no debug prints are sent.""" + # Let's send a disconnect command through the command pipe. + self.cmd_pipe_user.send(b"disconnect") + self.itpr.HandleUserData() + + # Verify interpreter is disconnected from EC. + self.assertFalse( + self.itpr.connected, ("The interpreter should be" "disconnected.") + ) + # Verify that the EC UART is no longer a member of the inputs. The + # interpreter will never pull data from the EC if it's not a member of the + # inputs list. + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) + + def test_CommandsDroppedWhenDisconnected(self): + """Verify that when in disconnected state, commands are dropped.""" + # Send a command, followed by 'disconnect'. + self.cmd_pipe_user.send(b"taskinfo") + self.itpr.HandleUserData() + self.cmd_pipe_user.send(b"disconnect") + self.itpr.HandleUserData() + + # Verify interpreter is disconnected from EC. + self.assertFalse( + self.itpr.connected, ("The interpreter should be" "disconnected.") + ) + # Verify that the EC UART is no longer a member of the inputs nor outputs. + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) + + # Have the user send a few more commands in the disconnected state. + command = "help\n" + for char in command: + self.cmd_pipe_user.send(char.encode("utf-8")) + self.itpr.HandleUserData() + + # The command queue should be empty. + self.assertEqual(0, self.itpr.ec_cmd_queue.qsize()) + + # Now send the reconnect command. + self.cmd_pipe_user.send(b"reconnect") + + with mock.patch(GetBuiltins("open"), mock.mock_open()): + self.itpr.HandleUserData() + + # Verify interpreter is connected. + self.assertTrue(self.itpr.connected) + # Verify that EC UART is a member of the inputs. + self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs) + # Since no command was sent after reconnection, verify that the EC UART is + # not a member of the outputs. + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) + + def test_ReconnectAllowsECTraffic(self): + """Verify that when connected, EC UART traffic is allowed.""" + # Let's send a disconnect command through the command pipe. + self.cmd_pipe_user.send(b"disconnect") + self.itpr.HandleUserData() + + # Verify interpreter is disconnected. + self.assertFalse( + self.itpr.connected, ("The interpreter should be" "disconnected.") + ) + # Verify that the EC UART is no longer a member of the inputs nor outputs. + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) + + # Issue reconnect command through the command pipe. + self.cmd_pipe_user.send(b"reconnect") + + with mock.patch(GetBuiltins("open"), mock.mock_open()): + self.itpr.HandleUserData() + + # Verify interpreter is connected. + self.assertTrue(self.itpr.connected, ("The interpreter should be" "connected.")) + # Verify that the EC UART is now a member of the inputs. + self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs) + # Since we have issued no commands during the disconnected state, no + # commands are pending and therefore the PTY should not be added to the + # outputs. + self.assertFalse(self.itpr.ec_uart_pty in self.itpr.outputs) + + +if __name__ == "__main__": + unittest.main() diff --git a/util/ec3po/threadproc_shim.py b/util/ec3po/threadproc_shim.py index da5440b1f3..c0b3ce0bf4 100644 --- a/util/ec3po/threadproc_shim.py +++ b/util/ec3po/threadproc_shim.py @@ -34,33 +34,34 @@ wait until after completing the TODO above to stop using multiprocessing.Pipe! # Imports to bring objects into this namespace for users of this module. from multiprocessing import Pipe -from six.moves.queue import Queue from threading import Thread as ThreadOrProcess +from six.moves.queue import Queue + # True if this module has ec3po using subprocesses, False if using threads. USING_SUBPROCS = False def _DoNothing(): - """Do-nothing function for use as a callback with DoIf().""" + """Do-nothing function for use as a callback with DoIf().""" def DoIf(subprocs=_DoNothing, threads=_DoNothing): - """Return a callback or not based on ec3po use of subprocesses or threads. + """Return a callback or not based on ec3po use of subprocesses or threads. - Args: - subprocs: callback that does not require any args - This will be returned - (not called!) if and only if ec3po is using subprocesses. This is - OPTIONAL, the default value is a do-nothing callback that returns None. - threads: callback that does not require any args - This will be returned - (not called!) if and only if ec3po is using threads. This is OPTIONAL, - the default value is a do-nothing callback that returns None. + Args: + subprocs: callback that does not require any args - This will be returned + (not called!) if and only if ec3po is using subprocesses. This is + OPTIONAL, the default value is a do-nothing callback that returns None. + threads: callback that does not require any args - This will be returned + (not called!) if and only if ec3po is using threads. This is OPTIONAL, + the default value is a do-nothing callback that returns None. - Returns: - Either the subprocs or threads argument will be returned. - """ - return subprocs if USING_SUBPROCS else threads + Returns: + Either the subprocs or threads argument will be returned. + """ + return subprocs if USING_SUBPROCS else threads def Value(ctype, *args): - return ctype(*args) + return ctype(*args) diff --git a/util/ec_openocd.py b/util/ec_openocd.py index a84c00643c..11956ffa1c 100755 --- a/util/ec_openocd.py +++ b/util/ec_openocd.py @@ -16,6 +16,7 @@ import time Flashes and debugs the EC through openocd """ + @dataclasses.dataclass class BoardInfo: gdb_variant: str @@ -24,9 +25,7 @@ class BoardInfo: # Debuggers for each board, OpenOCD currently only supports GDB -boards = { - "skyrim": BoardInfo("arm-none-eabi-gdb", 6, 4) -} +boards = {"skyrim": BoardInfo("arm-none-eabi-gdb", 6, 4)} def create_openocd_args(interface, board): @@ -36,9 +35,12 @@ def create_openocd_args(interface, board): board_info = boards[board] args = [ "openocd", - "-f", f"interface/{interface}.cfg", - "-c", "add_script_search_dir openocd", - "-f", f"board/{board}.cfg", + "-f", + f"interface/{interface}.cfg", + "-c", + "add_script_search_dir openocd", + "-f", + f"board/{board}.cfg", ] return args @@ -53,11 +55,13 @@ def create_gdb_args(board, port, executable): board_info.gdb_variant, executable, # GDB can't autodetect these according to OpenOCD - "-ex", f"set remote hardware-breakpoint-limit {board_info.num_breakpoints}", - "-ex", f"set remote hardware-watchpoint-limit {board_info.num_watchpoints}", - + "-ex", + f"set remote hardware-breakpoint-limit {board_info.num_breakpoints}", + "-ex", + f"set remote hardware-watchpoint-limit {board_info.num_watchpoints}", # Connect to OpenOCD - "-ex", f"target extended-remote localhost:{port}", + "-ex", + f"target extended-remote localhost:{port}", ] return args diff --git a/util/flash_jlink.py b/util/flash_jlink.py index 26c3c2e709..50a0bfca20 100755 --- a/util/flash_jlink.py +++ b/util/flash_jlink.py @@ -25,7 +25,6 @@ import sys import tempfile import time - DEFAULT_SEGGER_REMOTE_PORT = 19020 # Commands are documented here: https://wiki.segger.com/J-Link_Commander @@ -41,27 +40,34 @@ exit class BoardConfig: """Board configuration.""" + def __init__(self, interface, device, flash_address): self.interface = interface self.device = device self.flash_address = flash_address -SWD_INTERFACE = 'SWD' -STM32_DEFAULT_FLASH_ADDRESS = '0x8000000' -DRAGONCLAW_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32F412CG', - flash_address=STM32_DEFAULT_FLASH_ADDRESS) -ICETOWER_CONFIG = BoardConfig(interface=SWD_INTERFACE, device='STM32H743ZI', - flash_address=STM32_DEFAULT_FLASH_ADDRESS) +SWD_INTERFACE = "SWD" +STM32_DEFAULT_FLASH_ADDRESS = "0x8000000" +DRAGONCLAW_CONFIG = BoardConfig( + interface=SWD_INTERFACE, + device="STM32F412CG", + flash_address=STM32_DEFAULT_FLASH_ADDRESS, +) +ICETOWER_CONFIG = BoardConfig( + interface=SWD_INTERFACE, + device="STM32H743ZI", + flash_address=STM32_DEFAULT_FLASH_ADDRESS, +) BOARD_CONFIGS = { - 'dragonclaw': DRAGONCLAW_CONFIG, - 'bloonchipper': DRAGONCLAW_CONFIG, - 'nucleo-f412zg': DRAGONCLAW_CONFIG, - 'dartmonkey': ICETOWER_CONFIG, - 'icetower': ICETOWER_CONFIG, - 'nucleo-dartmonkey': ICETOWER_CONFIG, - 'nucleo-h743zi': ICETOWER_CONFIG, + "dragonclaw": DRAGONCLAW_CONFIG, + "bloonchipper": DRAGONCLAW_CONFIG, + "nucleo-f412zg": DRAGONCLAW_CONFIG, + "dartmonkey": ICETOWER_CONFIG, + "icetower": ICETOWER_CONFIG, + "nucleo-dartmonkey": ICETOWER_CONFIG, + "nucleo-h743zi": ICETOWER_CONFIG, } @@ -93,9 +99,11 @@ def is_tcp_port_open(host: str, tcp_port: int) -> bool: def create_jlink_command_file(firmware_file, config): tmp = tempfile.NamedTemporaryFile() - tmp.write(JLINK_COMMANDS.format(FIRMWARE=firmware_file, - FLASH_ADDRESS=config.flash_address).encode( - 'utf-8')) + tmp.write( + JLINK_COMMANDS.format( + FIRMWARE=firmware_file, FLASH_ADDRESS=config.flash_address + ).encode("utf-8") + ) tmp.flush() return tmp @@ -106,8 +114,8 @@ def flash(jlink_exe, remote, device, interface, cmd_file): ] if remote: - logging.debug(f'Connecting to J-Link over TCP/IP {remote}.') - remote_components = remote.split(':') + logging.debug(f"Connecting to J-Link over TCP/IP {remote}.") + remote_components = remote.split(":") if len(remote_components) not in [1, 2]: logging.debug(f'Given remote "{remote}" is malformed.') return 1 @@ -118,7 +126,7 @@ def flash(jlink_exe, remote, device, interface, cmd_file): except socket.gaierror as e: logging.error(f'Failed to resolve host "{host}": {e}.') return 1 - logging.debug(f'Resolved {host} as {ip}.') + logging.debug(f"Resolved {host} as {ip}.") port = DEFAULT_SEGGER_REMOTE_PORT if len(remote_components) == 2: @@ -126,29 +134,36 @@ def flash(jlink_exe, remote, device, interface, cmd_file): port = int(remote_components[1]) except ValueError: logging.error( - f'Given remote port "{remote_components[1]}" is malformed.') + f'Given remote port "{remote_components[1]}" is malformed.' + ) return 1 - remote = f'{ip}:{port}' + remote = f"{ip}:{port}" - logging.debug(f'Checking connection to {remote}.') + logging.debug(f"Checking connection to {remote}.") if not is_tcp_port_open(ip, port): - logging.error( - f"JLink server doesn't seem to be listening on {remote}.") - logging.error('Ensure that JLinkRemoteServerCLExe is running.') + logging.error(f"JLink server doesn't seem to be listening on {remote}.") + logging.error("Ensure that JLinkRemoteServerCLExe is running.") return 1 - cmd.extend(['-ip', remote]) - - cmd.extend([ - '-device', device, - '-if', interface, - '-speed', 'auto', - '-autoconnect', '1', - '-CommandFile', cmd_file, - ]) - logging.debug('Running command: "%s"', ' '.join(cmd)) + cmd.extend(["-ip", remote]) + + cmd.extend( + [ + "-device", + device, + "-if", + interface, + "-speed", + "auto", + "-autoconnect", + "1", + "-CommandFile", + cmd_file, + ] + ) + logging.debug('Running command: "%s"', " ".join(cmd)) completed_process = subprocess.run(cmd) # pylint: disable=subprocess-run-check - logging.debug('JLink return code: %d', completed_process.returncode) + logging.debug("JLink return code: %d", completed_process.returncode) return completed_process.returncode @@ -156,38 +171,42 @@ def main(argv: list): parser = argparse.ArgumentParser() - default_jlink = './JLink_Linux_V684a_x86_64/JLinkExe' + default_jlink = "./JLink_Linux_V684a_x86_64/JLinkExe" if shutil.which(default_jlink) is None: - default_jlink = 'JLinkExe' - parser.add_argument( - '--jlink', '-j', - help='JLinkExe path (default: ' + default_jlink + ')', - default=default_jlink) - + default_jlink = "JLinkExe" parser.add_argument( - '--remote', '-n', - help='Use TCP/IP host[:port] to connect to a J-Link or ' - 'JLinkRemoteServerCLExe. If unspecified, connect over USB.') + "--jlink", + "-j", + help="JLinkExe path (default: " + default_jlink + ")", + default=default_jlink, + ) - default_board = 'bloonchipper' parser.add_argument( - '--board', '-b', - help='Board (default: ' + default_board + ')', - default=default_board) + "--remote", + "-n", + help="Use TCP/IP host[:port] to connect to a J-Link or " + "JLinkRemoteServerCLExe. If unspecified, connect over USB.", + ) - default_firmware = os.path.join('./build', default_board, 'ec.bin') + default_board = "bloonchipper" parser.add_argument( - '--image', '-i', - help='Firmware binary (default: ' + default_firmware + ')', - default=default_firmware) + "--board", + "-b", + help="Board (default: " + default_board + ")", + default=default_board, + ) - log_level_choices = ['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'] + default_firmware = os.path.join("./build", default_board, "ec.bin") parser.add_argument( - '--log_level', '-l', - choices=log_level_choices, - default='DEBUG' + "--image", + "-i", + help="Firmware binary (default: " + default_firmware + ")", + default=default_firmware, ) + log_level_choices = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"] + parser.add_argument("--log_level", "-l", choices=log_level_choices, default="DEBUG") + args = parser.parse_args(argv) logging.basicConfig(level=args.log_level) @@ -201,11 +220,12 @@ def main(argv: list): args.jlink = args.jlink cmd_file = create_jlink_command_file(args.image, config) - ret_code = flash(args.jlink, args.remote, config.device, config.interface, - cmd_file.name) + ret_code = flash( + args.jlink, args.remote, config.device, config.interface, cmd_file.name + ) cmd_file.close() return ret_code -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/util/fptool.py b/util/fptool.py index 5d73302bbc..b7f2150289 100755 --- a/util/fptool.py +++ b/util/fptool.py @@ -19,14 +19,14 @@ def cmd_flash(args: argparse.Namespace) -> int: disabled. """ - if not shutil.which('flash_fp_mcu'): - print('Error - The flash_fp_mcu utility does not exist.') + if not shutil.which("flash_fp_mcu"): + print("Error - The flash_fp_mcu utility does not exist.") return 1 - cmd = ['flash_fp_mcu'] + cmd = ["flash_fp_mcu"] if args.image: if not os.path.isfile(args.image): - print(f'Error - image {args.image} is not a file.') + print(f"Error - image {args.image} is not a file.") return 1 cmd.append(args.image) @@ -38,18 +38,17 @@ def cmd_flash(args: argparse.Namespace) -> int: def main(argv: list) -> int: parser = argparse.ArgumentParser(description=__doc__) - subparsers = parser.add_subparsers(dest='subcommand', title='subcommands') + subparsers = parser.add_subparsers(dest="subcommand", title="subcommands") # This method of setting required is more compatible with older python. subparsers.required = True # Parser for "flash" subcommand. - parser_decrypt = subparsers.add_parser('flash', help=cmd_flash.__doc__) - parser_decrypt.add_argument( - 'image', nargs='?', help='Path to the firmware image') + parser_decrypt = subparsers.add_parser("flash", help=cmd_flash.__doc__) + parser_decrypt.add_argument("image", nargs="?", help="Path to the firmware image") parser_decrypt.set_defaults(func=cmd_flash) opts = parser.parse_args(argv) return opts.func(opts) -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/util/inject-keys.py b/util/inject-keys.py index bd10b693ad..d05d4fbed7 100755 --- a/util/inject-keys.py +++ b/util/inject-keys.py @@ -8,50 +8,124 @@ # Note: This is a py2/3 compatible file. from __future__ import print_function + import string import subprocess import sys - -KEYMATRIX = {'`': (3, 1), '1': (6, 1), '2': (6, 4), '3': (6, 2), '4': (6, 3), - '5': (3, 3), '6': (3, 6), '7': (6, 6), '8': (6, 5), '9': (6, 9), - '0': (6, 8), '-': (3, 8), '=': (0, 8), 'q': (7, 1), 'w': (7, 4), - 'e': (7, 2), 'r': (7, 3), 't': (2, 3), 'y': (2, 6), 'u': (7, 6), - 'i': (7, 5), 'o': (7, 9), 'p': (7, 8), '[': (2, 8), ']': (2, 5), - '\\': (3, 11), 'a': (4, 1), 's': (4, 4), 'd': (4, 2), 'f': (4, 3), - 'g': (1, 3), 'h': (1, 6), 'j': (4, 6), 'k': (4, 5), 'l': (4, 9), - ';': (4, 8), '\'': (1, 8), 'z': (5, 1), 'x': (5, 4), 'c': (5, 2), - 'v': (5, 3), 'b': (0, 3), 'n': (0, 6), 'm': (5, 6), ',': (5, 5), - '.': (5, 9), '/': (5, 8), ' ': (5, 11), '': (6, 12), - '': (0, 10), '': (6, 11), '': (2, 1), - '': (0, 4), '': (7, 7), '': (4, 0), - '': (1, 1), '': (1, 11), '': (3, 2), - '': (6, 10), '': (2, 0), '': (0, 2), - '': (0, 1), '': (2, 2), '': (1, 2), '': (3, 4), - '': (2, 4), '': (1, 4), '': (2, 9), '': (1, 9), - '': (7, 11), '': (5, 7), '': (4, 11), - '': (7, 12)} - - -UNSHIFT_TABLE = { '~': '`', '!': '1', '@': '2', '#': '3', '$': '4', - '%': '5', '^': '6', '&': '7', '*': '8', '(': '9', - ')': '0', '_': '-', '+': '=', '{': '[', '}': ']', - '|': '\\', - ':': ';', '"': "'", '<': ',', '>': '.', '?': '/'} +KEYMATRIX = { + "`": (3, 1), + "1": (6, 1), + "2": (6, 4), + "3": (6, 2), + "4": (6, 3), + "5": (3, 3), + "6": (3, 6), + "7": (6, 6), + "8": (6, 5), + "9": (6, 9), + "0": (6, 8), + "-": (3, 8), + "=": (0, 8), + "q": (7, 1), + "w": (7, 4), + "e": (7, 2), + "r": (7, 3), + "t": (2, 3), + "y": (2, 6), + "u": (7, 6), + "i": (7, 5), + "o": (7, 9), + "p": (7, 8), + "[": (2, 8), + "]": (2, 5), + "\\": (3, 11), + "a": (4, 1), + "s": (4, 4), + "d": (4, 2), + "f": (4, 3), + "g": (1, 3), + "h": (1, 6), + "j": (4, 6), + "k": (4, 5), + "l": (4, 9), + ";": (4, 8), + "'": (1, 8), + "z": (5, 1), + "x": (5, 4), + "c": (5, 2), + "v": (5, 3), + "b": (0, 3), + "n": (0, 6), + "m": (5, 6), + ",": (5, 5), + ".": (5, 9), + "/": (5, 8), + " ": (5, 11), + "": (6, 12), + "": (0, 10), + "": (6, 11), + "": (2, 1), + "": (0, 4), + "": (7, 7), + "": (4, 0), + "": (1, 1), + "": (1, 11), + "": (3, 2), + "": (6, 10), + "": (2, 0), + "": (0, 2), + "": (0, 1), + "": (2, 2), + "": (1, 2), + "": (3, 4), + "": (2, 4), + "": (1, 4), + "": (2, 9), + "": (1, 9), + "": (7, 11), + "": (5, 7), + "": (4, 11), + "": (7, 12), +} + + +UNSHIFT_TABLE = { + "~": "`", + "!": "1", + "@": "2", + "#": "3", + "$": "4", + "%": "5", + "^": "6", + "&": "7", + "*": "8", + "(": "9", + ")": "0", + "_": "-", + "+": "=", + "{": "[", + "}": "]", + "|": "\\", + ":": ";", + '"': "'", + "<": ",", + ">": ".", + "?": "/", +} for c in string.ascii_lowercase: UNSHIFT_TABLE[c.upper()] = c def inject_event(key, press): - if len(key) >= 2 and key[0] != '<': - key = '<' + key + '>' + if len(key) >= 2 and key[0] != "<": + key = "<" + key + ">" if key not in KEYMATRIX: print("%s: invalid key: %s" % (this_script, key)) sys.exit(1) (row, col) = KEYMATRIX[key] - subprocess.call(["ectool", "kbpress", str(row), str(col), - "1" if press else "0"]) + subprocess.call(["ectool", "kbpress", str(row), str(col), "1" if press else "0"]) def inject_key(key): @@ -73,8 +147,10 @@ def inject_string(string): def usage(): - print("Usage: %s [-s ] [-k ]" % this_script, - "[-p ] [-r ] ...") + print( + "Usage: %s [-s ] [-k ]" % this_script, + "[-p ] [-r ] ...", + ) print("Examples:") print("%s -s MyPassw0rd -k enter" % this_script) print("%s -p ctrl_l -p alt_l -k f3 -r alt_l -r ctrl_l" % this_script) @@ -85,7 +161,7 @@ def help(): print("Valid keys are:") i = 0 for key in KEYMATRIX: - print("%12s" % key, end='') + print("%12s" % key, end="") i += 1 if i % 4 == 0: print() @@ -114,12 +190,13 @@ usage_check(arg_len > 1, "not enough arguments") usage_check(arg_len % 2 == 1, "mismatched arguments") for i in range(1, arg_len, 2): - usage_check(sys.argv[i] in ("-s", "-k", "-p", "-r"), - "unknown flag: %s" % sys.argv[i]) + usage_check( + sys.argv[i] in ("-s", "-k", "-p", "-r"), "unknown flag: %s" % sys.argv[i] + ) for i in range(1, arg_len, 2): flag = sys.argv[i] - arg = sys.argv[i+1] + arg = sys.argv[i + 1] if flag == "-s": inject_string(arg) elif flag == "-k": diff --git a/util/kconfig_check.py b/util/kconfig_check.py index d1eba8e62b..04cdf9a990 100755 --- a/util/kconfig_check.py +++ b/util/kconfig_check.py @@ -32,12 +32,13 @@ import sys USE_KCONFIGLIB = False try: import kconfiglib + USE_KCONFIGLIB = True except ImportError: pass # Where we put the new config_allowed file -NEW_ALLOWED_FNAME = pathlib.Path('/tmp/new_config_allowed.txt') +NEW_ALLOWED_FNAME = pathlib.Path("/tmp/new_config_allowed.txt") def parse_args(argv): @@ -49,38 +50,72 @@ def parse_args(argv): Returns: argparse.Namespace object containing the results """ - epilog = '''Checks that new ad-hoc CONFIG options are not introduced without -a corresponding Kconfig option for Zephyr''' + epilog = """Checks that new ad-hoc CONFIG options are not introduced without +a corresponding Kconfig option for Zephyr""" parser = argparse.ArgumentParser(epilog=epilog) - parser.add_argument('-a', '--allowed', type=str, - default='util/config_allowed.txt', - help='File containing list of allowed ad-hoc CONFIGs') - parser.add_argument('-c', '--configs', type=str, default='.config', - help='File containing CONFIG options to check') - parser.add_argument('-d', '--use-defines', action='store_true', - help='Lines in the configs file use #define') parser.add_argument( - '-D', '--debug', action='store_true', - help='Enabling debugging (provides a full traceback on error)') + "-a", + "--allowed", + type=str, + default="util/config_allowed.txt", + help="File containing list of allowed ad-hoc CONFIGs", + ) + parser.add_argument( + "-c", + "--configs", + type=str, + default=".config", + help="File containing CONFIG options to check", + ) + parser.add_argument( + "-d", + "--use-defines", + action="store_true", + help="Lines in the configs file use #define", + ) + parser.add_argument( + "-D", + "--debug", + action="store_true", + help="Enabling debugging (provides a full traceback on error)", + ) + parser.add_argument( + "-i", + "--ignore", + action="append", + help="Kconfig options to ignore (without CONFIG_ prefix)", + ) parser.add_argument( - '-i', '--ignore', action='append', - help='Kconfig options to ignore (without CONFIG_ prefix)') - parser.add_argument('-I', '--search-path', type=str, action='append', - help='Search paths to look for Kconfigs') - parser.add_argument('-p', '--prefix', type=str, default='PLATFORM_EC_', - help='Prefix to string from Kconfig options') - parser.add_argument('-s', '--srctree', type=str, default='zephyr/', - help='Path to source tree to look for Kconfigs') + "-I", + "--search-path", + type=str, + action="append", + help="Search paths to look for Kconfigs", + ) + parser.add_argument( + "-p", + "--prefix", + type=str, + default="PLATFORM_EC_", + help="Prefix to string from Kconfig options", + ) + parser.add_argument( + "-s", + "--srctree", + type=str, + default="zephyr/", + help="Path to source tree to look for Kconfigs", + ) # TODO(sjg@chromium.org): The chroot uses a very old Python. Once it moves # to 3.7 or later we can use this instead: # subparsers = parser.add_subparsers(dest='cmd', required=True) - subparsers = parser.add_subparsers(dest='cmd') + subparsers = parser.add_subparsers(dest="cmd") subparsers.required = True - subparsers.add_parser('build', help='Build new list of ad-hoc CONFIGs') - subparsers.add_parser('check', help='Check for new ad-hoc CONFIGs') + subparsers.add_parser("build", help="Build new list of ad-hoc CONFIGs") + subparsers.add_parser("check", help="Check for new ad-hoc CONFIGs") return parser.parse_args(argv) @@ -107,6 +142,7 @@ class KconfigCheck: the user is exhorted to add a new Kconfig. This helps avoid adding new ad-hoc CONFIG options, eventually returning the number to zero. """ + @classmethod def find_new_adhoc(cls, configs, kconfigs, allowed): """Get a list of new ad-hoc CONFIG options @@ -172,11 +208,12 @@ class KconfigCheck: List of CONFIG_xxx options found in the file, with the 'CONFIG_' prefix removed """ - with open(configs_file, 'r') as inf: - configs = re.findall('%sCONFIG_([A-Za-z0-9_]*)%s' % - ((use_defines and '#define ' or ''), - (use_defines and ' ' or '')), - inf.read()) + with open(configs_file, "r") as inf: + configs = re.findall( + "%sCONFIG_([A-Za-z0-9_]*)%s" + % ((use_defines and "#define " or ""), (use_defines and " " or "")), + inf.read(), + ) return configs @classmethod @@ -190,8 +227,8 @@ class KconfigCheck: List of CONFIG_xxx options found in the file, with the 'CONFIG_' prefix removed """ - with open(allowed_file, 'r') as inf: - configs = re.findall('CONFIG_([A-Za-z0-9_]*)', inf.read()) + with open(allowed_file, "r") as inf: + configs = re.findall("CONFIG_([A-Za-z0-9_]*)", inf.read()) return configs @classmethod @@ -209,15 +246,17 @@ class KconfigCheck: """ kconfig_files = [] for root, dirs, files in os.walk(srcdir): - kconfig_files += [os.path.join(root, fname) - for fname in files if fname.startswith('Kconfig')] - if 'Kconfig' in dirs: - dirs.remove('Kconfig') + kconfig_files += [ + os.path.join(root, fname) + for fname in files + if fname.startswith("Kconfig") + ] + if "Kconfig" in dirs: + dirs.remove("Kconfig") return kconfig_files @classmethod - def scan_kconfigs(cls, srcdir, prefix='', search_paths=None, - try_kconfiglib=True): + def scan_kconfigs(cls, srcdir, prefix="", search_paths=None, try_kconfiglib=True): """Scan a source tree for Kconfig options Args: @@ -231,31 +270,40 @@ class KconfigCheck: List of config and menuconfig options found """ if USE_KCONFIGLIB and try_kconfiglib: - os.environ['srctree'] = srcdir - kconf = kconfiglib.Kconfig('Kconfig', warn=False, - search_paths=search_paths, - allow_empty_macros=True) + os.environ["srctree"] = srcdir + kconf = kconfiglib.Kconfig( + "Kconfig", + warn=False, + search_paths=search_paths, + allow_empty_macros=True, + ) # There is always a MODULES config, since kconfiglib is designed for # linux, but we don't want it - kconfigs = [name for name in kconf.syms if name != 'MODULES'] + kconfigs = [name for name in kconf.syms if name != "MODULES"] if prefix: - re_drop_prefix = re.compile(r'^%s' % prefix) - kconfigs = [re_drop_prefix.sub('', name) for name in kconfigs] + re_drop_prefix = re.compile(r"^%s" % prefix) + kconfigs = [re_drop_prefix.sub("", name) for name in kconfigs] else: kconfigs = [] # Remove the prefix if present - expr = re.compile(r'\n(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n' % - prefix) + expr = re.compile(r"\n(config|menuconfig) (%s)?([A-Za-z0-9_]*)\n" % prefix) for fname in cls.find_kconfigs(srcdir): with open(fname) as inf: found = re.findall(expr, inf.read()) kconfigs += [name for kctype, _, name in found] return sorted(kconfigs) - def check_adhoc_configs(self, configs_file, srcdir, allowed_file, - prefix='', use_defines=False, search_paths=None): + def check_adhoc_configs( + self, + configs_file, + srcdir, + allowed_file, + prefix="", + use_defines=False, + search_paths=None, + ): """Find new and unneeded ad-hoc configs in the configs_file Args: @@ -283,8 +331,9 @@ class KconfigCheck: except kconfiglib.KconfigError: # If we don't actually have access to the full Kconfig then we may # get an error. Fall back to using manual methods. - kconfigs = self.scan_kconfigs(srcdir, prefix, search_paths, - try_kconfiglib=False) + kconfigs = self.scan_kconfigs( + srcdir, prefix, search_paths, try_kconfiglib=False + ) allowed = self.read_allowed(allowed_file) new_adhoc = self.find_new_adhoc(configs, kconfigs, allowed) @@ -292,8 +341,16 @@ class KconfigCheck: updated_adhoc = self.get_updated_adhoc(unneeded_adhoc, allowed) return new_adhoc, unneeded_adhoc, updated_adhoc - def do_check(self, configs_file, srcdir, allowed_file, prefix, use_defines, - search_paths, ignore=None): + def do_check( + self, + configs_file, + srcdir, + allowed_file, + prefix, + use_defines, + search_paths, + ignore=None, + ): """Find new ad-hoc configs in the configs_file Args: @@ -313,11 +370,12 @@ class KconfigCheck: Exit code: 0 if OK, 1 if a problem was found """ new_adhoc, unneeded_adhoc, updated_adhoc = self.check_adhoc_configs( - configs_file, srcdir, allowed_file, prefix, use_defines, - search_paths) + configs_file, srcdir, allowed_file, prefix, use_defines, search_paths + ) if new_adhoc: - file_list = '\n'.join(['CONFIG_%s' % name for name in new_adhoc]) - print(f'''Error:\tThe EC is in the process of migrating to Zephyr. + file_list = "\n".join(["CONFIG_%s" % name for name in new_adhoc]) + print( + f"""Error:\tThe EC is in the process of migrating to Zephyr. \tZephyr uses Kconfig for configuration rather than ad-hoc #defines. \tAny new EC CONFIG options must ALSO be added to Zephyr so that new \tfunctionality is available in Zephyr also. The following new ad-hoc @@ -330,19 +388,21 @@ file in zephyr/ and add a 'config' or 'menuconfig' option. Also see details in http://issuetracker.google.com/181253613 To temporarily disable this, use: ALLOW_CONFIG=1 make ... -''', file=sys.stderr) +""", + file=sys.stderr, + ) return 1 if not ignore: ignore = [] unneeded_adhoc = [name for name in unneeded_adhoc if name not in ignore] if unneeded_adhoc: - with open(NEW_ALLOWED_FNAME, 'w') as out: + with open(NEW_ALLOWED_FNAME, "w") as out: for config in updated_adhoc: - print('CONFIG_%s' % config, file=out) - now_in_kconfig = '\n'.join( - ['CONFIG_%s' % name for name in unneeded_adhoc]) - print(f'''The following options are now in Kconfig: + print("CONFIG_%s" % config, file=out) + now_in_kconfig = "\n".join(["CONFIG_%s" % name for name in unneeded_adhoc]) + print( + f"""The following options are now in Kconfig: {now_in_kconfig} @@ -350,12 +410,14 @@ Please run this to update the list of allowed ad-hoc CONFIGs and include this update in your CL: cp {NEW_ALLOWED_FNAME} util/config_allowed.txt -''') +""" + ) return 1 return 0 - def do_build(self, configs_file, srcdir, allowed_file, prefix, use_defines, - search_paths): + def do_build( + self, configs_file, srcdir, allowed_file, prefix, use_defines, search_paths + ): """Find new ad-hoc configs in the configs_file Args: @@ -372,13 +434,14 @@ update in your CL: Exit code: 0 if OK, 1 if a problem was found """ new_adhoc, _, updated_adhoc = self.check_adhoc_configs( - configs_file, srcdir, allowed_file, prefix, use_defines, - search_paths) - with open(NEW_ALLOWED_FNAME, 'w') as out: + configs_file, srcdir, allowed_file, prefix, use_defines, search_paths + ) + with open(NEW_ALLOWED_FNAME, "w") as out: combined = sorted(new_adhoc + updated_adhoc) for config in combined: - print(f'CONFIG_{config}', file=out) - print(f'New list is in {NEW_ALLOWED_FNAME}') + print(f"CONFIG_{config}", file=out) + print(f"New list is in {NEW_ALLOWED_FNAME}") + def main(argv): """Main function""" @@ -386,18 +449,27 @@ def main(argv): if not args.debug: sys.tracebacklimit = 0 checker = KconfigCheck() - if args.cmd == 'check': + if args.cmd == "check": return checker.do_check( - configs_file=args.configs, srcdir=args.srctree, - allowed_file=args.allowed, prefix=args.prefix, - use_defines=args.use_defines, search_paths=args.search_path, - ignore=args.ignore) - elif args.cmd == 'build': - return checker.do_build(configs_file=args.configs, srcdir=args.srctree, - allowed_file=args.allowed, prefix=args.prefix, - use_defines=args.use_defines, search_paths=args.search_path) + configs_file=args.configs, + srcdir=args.srctree, + allowed_file=args.allowed, + prefix=args.prefix, + use_defines=args.use_defines, + search_paths=args.search_path, + ignore=args.ignore, + ) + elif args.cmd == "build": + return checker.do_build( + configs_file=args.configs, + srcdir=args.srctree, + allowed_file=args.allowed, + prefix=args.prefix, + use_defines=args.use_defines, + search_paths=args.search_path, + ) return 2 -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/util/kconfiglib.py b/util/kconfiglib.py index 0e05aaaeac..a0033bba2d 100644 --- a/util/kconfiglib.py +++ b/util/kconfiglib.py @@ -553,7 +553,6 @@ import sys from glob import iglob from os.path import dirname, exists, expandvars, islink, join, realpath - VERSION = (14, 1, 0) @@ -810,6 +809,7 @@ class Kconfig(object): The current parsing location, for use in Python preprocessor functions. See the module docstring. """ + __slots__ = ( "_encoding", "_functions", @@ -848,7 +848,6 @@ class Kconfig(object): "warn_to_stderr", "warnings", "y", - # Parsing-related "_parsing_kconfigs", "_readline", @@ -866,9 +865,16 @@ class Kconfig(object): # Public interface # - def __init__(self, filename="Kconfig", warn=True, warn_to_stderr=True, - encoding="utf-8", suppress_traceback=False, search_paths=None, - allow_empty_macros=False): + def __init__( + self, + filename="Kconfig", + warn=True, + warn_to_stderr=True, + encoding="utf-8", + suppress_traceback=False, + search_paths=None, + allow_empty_macros=False, + ): """ Creates a new Kconfig object by parsing Kconfig files. Note that Kconfig files are not the same as .config files (which store @@ -972,8 +978,14 @@ class Kconfig(object): Pass True here to allow empty / undefined macros. """ try: - self._init(filename, warn, warn_to_stderr, encoding, search_paths, - allow_empty_macros) + self._init( + filename, + warn, + warn_to_stderr, + encoding, + search_paths, + allow_empty_macros, + ) except (EnvironmentError, KconfigError) as e: if suppress_traceback: cmd = sys.argv[0] # Empty string if missing @@ -985,8 +997,9 @@ class Kconfig(object): sys.exit(cmd + str(e).strip()) raise - def _init(self, filename, warn, warn_to_stderr, encoding, search_paths, - allow_empty_macros): + def _init( + self, filename, warn, warn_to_stderr, encoding, search_paths, allow_empty_macros + ): # See __init__() self._encoding = encoding @@ -1011,8 +1024,9 @@ class Kconfig(object): self.config_prefix = os.getenv("CONFIG_", "CONFIG_") # Regular expressions for parsing .config files self._set_match = _re_match(self.config_prefix + r"([^=]+)=(.*)") - self._unset_match = _re_match(r"# {}([^ ]+) is not set".format( - self.config_prefix)) + self._unset_match = _re_match( + r"# {}([^ ]+) is not set".format(self.config_prefix) + ) self.config_header = os.getenv("KCONFIG_CONFIG_HEADER", "") self.header_header = os.getenv("KCONFIG_AUTOHEADER_HEADER", "") @@ -1050,11 +1064,11 @@ class Kconfig(object): # Predefined preprocessor functions, with min/max number of arguments self._functions = { - "info": (_info_fn, 1, 1), - "error-if": (_error_if_fn, 2, 2), - "filename": (_filename_fn, 0, 0), - "lineno": (_lineno_fn, 0, 0), - "shell": (_shell_fn, 1, 1), + "info": (_info_fn, 1, 1), + "error-if": (_error_if_fn, 2, 2), + "filename": (_filename_fn, 0, 0), + "lineno": (_lineno_fn, 0, 0), + "shell": (_shell_fn, 1, 1), "warning-if": (_warning_if_fn, 2, 2), } @@ -1063,7 +1077,8 @@ class Kconfig(object): self._functions.update( importlib.import_module( os.getenv("KCONFIG_FUNCTIONS", "kconfigfunctions") - ).functions) + ).functions + ) except ImportError: pass @@ -1138,8 +1153,7 @@ class Kconfig(object): # KCONFIG_STRICT is an older alias for KCONFIG_WARN_UNDEF, supported # for backwards compatibility - if os.getenv("KCONFIG_WARN_UNDEF") == "y" or \ - os.getenv("KCONFIG_STRICT") == "y": + if os.getenv("KCONFIG_WARN_UNDEF") == "y" or os.getenv("KCONFIG_STRICT") == "y": self._check_undef_syms() @@ -1247,15 +1261,14 @@ class Kconfig(object): msg = None if filename is None: filename = standard_config_filename() - if not exists(filename) and \ - not exists(join(self.srctree, filename)): + if not exists(filename) and not exists(join(self.srctree, filename)): defconfig = self.defconfig_filename if defconfig is None: - return "Using default symbol values (no '{}')" \ - .format(filename) + return "Using default symbol values (no '{}')".format(filename) - msg = " default configuration '{}' (no '{}')" \ - .format(defconfig, filename) + msg = " default configuration '{}' (no '{}')".format( + defconfig, filename + ) filename = defconfig if not msg: @@ -1313,15 +1326,20 @@ class Kconfig(object): if sym.orig_type in _BOOL_TRISTATE: # The C implementation only checks the first character # to the right of '=', for whatever reason - if not (sym.orig_type is BOOL - and val.startswith(("y", "n")) or - sym.orig_type is TRISTATE - and val.startswith(("y", "m", "n"))): - self._warn("'{}' is not a valid value for the {} " - "symbol {}. Assignment ignored." - .format(val, TYPE_TO_STR[sym.orig_type], - sym.name_and_loc), - filename, linenr) + if not ( + sym.orig_type is BOOL + and val.startswith(("y", "n")) + or sym.orig_type is TRISTATE + and val.startswith(("y", "m", "n")) + ): + self._warn( + "'{}' is not a valid value for the {} " + "symbol {}. Assignment ignored.".format( + val, TYPE_TO_STR[sym.orig_type], sym.name_and_loc + ), + filename, + linenr, + ) continue val = val[0] @@ -1332,12 +1350,14 @@ class Kconfig(object): # to the choice symbols prev_mode = sym.choice.user_value - if prev_mode is not None and \ - TRI_TO_STR[prev_mode] != val: + if prev_mode is not None and TRI_TO_STR[prev_mode] != val: - self._warn("both m and y assigned to symbols " - "within the same choice", - filename, linenr) + self._warn( + "both m and y assigned to symbols " + "within the same choice", + filename, + linenr, + ) # Set the choice's mode sym.choice.set_value(val) @@ -1345,10 +1365,14 @@ class Kconfig(object): elif sym.orig_type is STRING: match = _conf_string_match(val) if not match: - self._warn("malformed string literal in " - "assignment to {}. Assignment ignored." - .format(sym.name_and_loc), - filename, linenr) + self._warn( + "malformed string literal in " + "assignment to {}. Assignment ignored.".format( + sym.name_and_loc + ), + filename, + linenr, + ) continue val = unescape(match.group(1)) @@ -1361,9 +1385,11 @@ class Kconfig(object): # lines or comments. 'line' has already been # rstrip()'d, so blank lines show up as "" here. if line and not line.lstrip().startswith("#"): - self._warn("ignoring malformed line '{}'" - .format(line), - filename, linenr) + self._warn( + "ignoring malformed line '{}'".format(line), + filename, + linenr, + ) continue @@ -1403,8 +1429,12 @@ class Kconfig(object): self.missing_syms.append((name, val)) if self.warn_assign_undef: self._warn( - "attempt to assign the value '{}' to the undefined symbol {}" - .format(val, name), filename, linenr) + "attempt to assign the value '{}' to the undefined symbol {}".format( + val, name + ), + filename, + linenr, + ) def _assigned_twice(self, sym, new_val, filename, linenr): # Called when a symbol is assigned more than once in a .config file @@ -1416,7 +1446,8 @@ class Kconfig(object): user_val = sym.user_value msg = '{} set more than once. Old value "{}", new value "{}".'.format( - sym.name_and_loc, user_val, new_val) + sym.name_and_loc, user_val, new_val + ) if user_val == new_val: if self.warn_assign_redun: @@ -1482,8 +1513,7 @@ class Kconfig(object): in tools, which can do e.g. print(kconf.write_autoconf()). """ if filename is None: - filename = os.getenv("KCONFIG_AUTOHEADER", - "include/generated/autoconf.h") + filename = os.getenv("KCONFIG_AUTOHEADER", "include/generated/autoconf.h") if self._write_if_changed(filename, self._autoconf_contents(header)): return "Kconfig header saved to '{}'".format(filename) @@ -1512,28 +1542,26 @@ class Kconfig(object): if sym.orig_type in _BOOL_TRISTATE: if val == "y": - add("#define {}{} 1\n" - .format(self.config_prefix, sym.name)) + add("#define {}{} 1\n".format(self.config_prefix, sym.name)) elif val == "m": - add("#define {}{}_MODULE 1\n" - .format(self.config_prefix, sym.name)) + add("#define {}{}_MODULE 1\n".format(self.config_prefix, sym.name)) elif sym.orig_type is STRING: - add('#define {}{} "{}"\n' - .format(self.config_prefix, sym.name, escape(val))) + add( + '#define {}{} "{}"\n'.format( + self.config_prefix, sym.name, escape(val) + ) + ) else: # sym.orig_type in _INT_HEX: - if sym.orig_type is HEX and \ - not val.startswith(("0x", "0X")): + if sym.orig_type is HEX and not val.startswith(("0x", "0X")): val = "0x" + val - add("#define {}{} {}\n" - .format(self.config_prefix, sym.name, val)) + add("#define {}{} {}\n".format(self.config_prefix, sym.name, val)) return "".join(chunks) - def write_config(self, filename=None, header=None, save_old=True, - verbose=None): + def write_config(self, filename=None, header=None, save_old=True, verbose=None): r""" Writes out symbol values in the .config format. The format matches the C implementation, including ordering. @@ -1647,9 +1675,12 @@ class Kconfig(object): node = node.parent # Add a comment when leaving visible menus - if node.item is MENU and expr_value(node.dep) and \ - expr_value(node.visibility) and \ - node is not self.top_node: + if ( + node.item is MENU + and expr_value(node.dep) + and expr_value(node.visibility) + and node is not self.top_node + ): add("# end of {}\n".format(node.prompt[0])) after_end_comment = True @@ -1680,9 +1711,9 @@ class Kconfig(object): add("\n") add(conf_string) - elif expr_value(node.dep) and \ - ((item is MENU and expr_value(node.visibility)) or - item is COMMENT): + elif expr_value(node.dep) and ( + (item is MENU and expr_value(node.visibility)) or item is COMMENT + ): add("\n#\n# {}\n#\n".format(node.prompt[0])) after_end_comment = False @@ -1738,8 +1769,7 @@ class Kconfig(object): # Skip symbols that cannot be changed. Only check # non-choice symbols, as selects don't affect choice # symbols. - if not sym.choice and \ - sym.visibility <= expr_value(sym.rev_dep): + if not sym.choice and sym.visibility <= expr_value(sym.rev_dep): continue # Skip symbols whose value matches their default @@ -1750,11 +1780,13 @@ class Kconfig(object): # choice, unless the choice is optional or the symbol type # isn't bool (it might be possible to set the choice mode # to n or the symbol to m in those cases). - if sym.choice and \ - not sym.choice.is_optional and \ - sym.choice._selection_from_defaults() is sym and \ - sym.orig_type is BOOL and \ - sym.tri_value == 2: + if ( + sym.choice + and not sym.choice.is_optional + and sym.choice._selection_from_defaults() is sym + and sym.orig_type is BOOL + and sym.tri_value == 2 + ): continue add(sym.config_string) @@ -1842,9 +1874,11 @@ class Kconfig(object): # making a missing symbol logically equivalent to n if sym._write_to_conf: - if sym._old_val is None and \ - sym.orig_type in _BOOL_TRISTATE and \ - val == "n": + if ( + sym._old_val is None + and sym.orig_type in _BOOL_TRISTATE + and val == "n" + ): # No old value (the symbol was missing or n), new value n. # No change. continue @@ -1924,17 +1958,20 @@ class Kconfig(object): # by passing a flag to it, plus we only need to look at symbols here. self._write_if_changed( - os.path.join(path, "auto.conf"), - self._old_vals_contents()) + os.path.join(path, "auto.conf"), self._old_vals_contents() + ) def _old_vals_contents(self): # _write_old_vals() helper. Returns the contents to write as a string. # Temporary list instead of generator makes this a bit faster - return "".join([ - sym.config_string for sym in self.unique_defined_syms + return "".join( + [ + sym.config_string + for sym in self.unique_defined_syms if not (sym.orig_type in _BOOL_TRISTATE and not sym.tri_value) - ]) + ] + ) def node_iter(self, unique_syms=False): """ @@ -2112,30 +2149,35 @@ class Kconfig(object): Returns a string with information about the Kconfig object when it is evaluated on e.g. the interactive Python prompt. """ + def status(flag): return "enabled" if flag else "disabled" - return "<{}>".format(", ".join(( - "configuration with {} symbols".format(len(self.syms)), - 'main menu prompt "{}"'.format(self.mainmenu_text), - "srctree is current directory" if not self.srctree else - 'srctree "{}"'.format(self.srctree), - 'config symbol prefix "{}"'.format(self.config_prefix), - "warnings " + status(self.warn), - "printing of warnings to stderr " + status(self.warn_to_stderr), - "undef. symbol assignment warnings " + - status(self.warn_assign_undef), - "overriding symbol assignment warnings " + - status(self.warn_assign_override), - "redundant symbol assignment warnings " + - status(self.warn_assign_redun) - ))) + return "<{}>".format( + ", ".join( + ( + "configuration with {} symbols".format(len(self.syms)), + 'main menu prompt "{}"'.format(self.mainmenu_text), + "srctree is current directory" + if not self.srctree + else 'srctree "{}"'.format(self.srctree), + 'config symbol prefix "{}"'.format(self.config_prefix), + "warnings " + status(self.warn), + "printing of warnings to stderr " + status(self.warn_to_stderr), + "undef. symbol assignment warnings " + + status(self.warn_assign_undef), + "overriding symbol assignment warnings " + + status(self.warn_assign_override), + "redundant symbol assignment warnings " + + status(self.warn_assign_redun), + ) + ) + ) # # Private methods # - # # File reading # @@ -2160,11 +2202,17 @@ class Kconfig(object): e = e2 raise _KconfigIOError( - e, "Could not open '{}' ({}: {}). Check that the $srctree " - "environment variable ({}) is set correctly." - .format(filename, errno.errorcode[e.errno], e.strerror, - "set to '{}'".format(self.srctree) if self.srctree - else "unset or blank")) + e, + "Could not open '{}' ({}: {}). Check that the $srctree " + "environment variable ({}) is set correctly.".format( + filename, + errno.errorcode[e.errno], + e.strerror, + "set to '{}'".format(self.srctree) + if self.srctree + else "unset or blank", + ), + ) def _enter_file(self, filename): # Jumps to the beginning of a sourced Kconfig file, saving the previous @@ -2179,7 +2227,7 @@ class Kconfig(object): if filename.startswith(self._srctree_prefix): # Relative path (or a redundant absolute path to within $srctree, # but it's probably fine to reduce those too) - rel_filename = filename[len(self._srctree_prefix):] + rel_filename = filename[len(self._srctree_prefix) :] else: # Absolute path rel_filename = filename @@ -2212,20 +2260,32 @@ class Kconfig(object): raise KconfigError( "\n{}:{}: recursive 'source' of '{}' detected. Check that " "environment variables are set correctly.\n" - "Include path:\n{}" - .format(self.filename, self.linenr, rel_filename, - "\n".join("{}:{}".format(name, linenr) - for name, linenr in self._include_path))) + "Include path:\n{}".format( + self.filename, + self.linenr, + rel_filename, + "\n".join( + "{}:{}".format(name, linenr) + for name, linenr in self._include_path + ), + ) + ) try: self._readline = self._open(filename, "r").readline except EnvironmentError as e: # We already know that the file exists raise _KconfigIOError( - e, "{}:{}: Could not open '{}' (in '{}') ({}: {})" - .format(self.filename, self.linenr, filename, - self._line.strip(), - errno.errorcode[e.errno], e.strerror)) + e, + "{}:{}: Could not open '{}' (in '{}') ({}: {})".format( + self.filename, + self.linenr, + filename, + self._line.strip(), + errno.errorcode[e.errno], + e.strerror, + ), + ) self.filename = rel_filename self.linenr = 0 @@ -2438,8 +2498,11 @@ class Kconfig(object): else: i = match.end() - token = self.const_syms[name] if name in STR_TO_TRI else \ - self._lookup_sym(name) + token = ( + self.const_syms[name] + if name in STR_TO_TRI + else self._lookup_sym(name) + ) else: # It's a case of missing quotes. For example, the @@ -2455,9 +2518,13 @@ class Kconfig(object): # Named choices ('choice FOO') also end up here. if token is not _T_CHOICE: - self._warn("style: quotes recommended around '{}' in '{}'" - .format(name, self._line.strip()), - self.filename, self.linenr) + self._warn( + "style: quotes recommended around '{}' in '{}'".format( + name, self._line.strip() + ), + self.filename, + self.linenr, + ) token = name i = match.end() @@ -2476,7 +2543,7 @@ class Kconfig(object): end_i = s.find(c, i + 1) + 1 if not end_i: self._parse_error("unterminated string") - val = s[i + 1:end_i - 1] + val = s[i + 1 : end_i - 1] i = end_i else: # Slow path @@ -2489,18 +2556,22 @@ class Kconfig(object): # # The preprocessor functionality changed how # environment variables are referenced, to $(FOO). - val = expandvars(s[i + 1:end_i - 1] - .replace("$UNAME_RELEASE", - _UNAME_RELEASE)) + val = expandvars( + s[i + 1 : end_i - 1].replace( + "$UNAME_RELEASE", _UNAME_RELEASE + ) + ) i = end_i # This is the only place where we don't survive with a # single token of lookback: 'option env="FOO"' does not # refer to a constant symbol named "FOO". - token = \ - val if token in _STRING_LEX or tokens[0] is _T_OPTION \ + token = ( + val + if token in _STRING_LEX or tokens[0] is _T_OPTION else self._lookup_const_sym(val) + ) elif s.startswith("&&", i): token = _T_AND @@ -2533,7 +2604,6 @@ class Kconfig(object): elif c == "#": break - # Very rare elif s.startswith("<=", i): @@ -2552,16 +2622,13 @@ class Kconfig(object): token = _T_GREATER i += 1 - else: self._parse_error("unknown tokens in line") - # Skip trailing whitespace while i < len(s) and s[i].isspace(): i += 1 - # Add the token tokens.append(token) @@ -2652,7 +2719,6 @@ class Kconfig(object): # Assigned variable name = s[:i] - # Extract assignment operator (=, :=, or +=) and value rhs_match = _assignment_rhs_match(s, i) if not rhs_match: @@ -2660,7 +2726,6 @@ class Kconfig(object): op, val = rhs_match.groups() - if name in self.variables: # Already seen variable var = self.variables[name] @@ -2686,8 +2751,9 @@ class Kconfig(object): else: # op == "+=" # += does immediate expansion if the variable was last set # with := - var.value += " " + (val if var.is_recursive else - self._expand_whole(val, ())) + var.value += " " + ( + val if var.is_recursive else self._expand_whole(val, ()) + ) def _expand_whole(self, s, args): # Expands preprocessor macros in all of 's'. Used whenever we don't @@ -2753,7 +2819,6 @@ class Kconfig(object): if not match: self._parse_error("unterminated string") - if match.group() == quote: # Found the end of the string return (s, match.end()) @@ -2762,7 +2827,7 @@ class Kconfig(object): # Replace '\x' with 'x'. 'i' ends up pointing to the character # after 'x', which allows macros to be canceled with '\$(foo)'. i = match.end() - s = s[:match.start()] + s[i:] + s = s[: match.start()] + s[i:] elif match.group() == "$(": # A macro call within the string @@ -2792,7 +2857,6 @@ class Kconfig(object): if not match: self._parse_error("missing end parenthesis in macro expansion") - if match.group() == "(": nesting += 1 i = match.end() @@ -2805,7 +2869,7 @@ class Kconfig(object): # Found the end of the macro - new_args.append(s[arg_start:match.start()]) + new_args.append(s[arg_start : match.start()]) # $(1) is replaced by the first argument to the function, etc., # provided at least that many arguments were passed @@ -2819,7 +2883,7 @@ class Kconfig(object): # and also go through the function value path res += self._fn_val(new_args) - return (res + s[match.end():], len(res)) + return (res + s[match.end() :], len(res)) elif match.group() == ",": i = match.end() @@ -2827,7 +2891,7 @@ class Kconfig(object): continue # Found the end of a macro argument - new_args.append(s[arg_start:match.start()]) + new_args.append(s[arg_start : match.start()]) arg_start = i else: # match.group() == "$(" @@ -2847,13 +2911,17 @@ class Kconfig(object): if len(args) == 1: # Plain variable if var._n_expansions: - self._parse_error("Preprocessor variable {} recursively " - "references itself".format(var.name)) + self._parse_error( + "Preprocessor variable {} recursively " + "references itself".format(var.name) + ) elif var._n_expansions > 100: # Allow functions to call themselves, but guess that functions # that are overly recursive are stuck - self._parse_error("Preprocessor function {} seems stuck " - "in infinite recursion".format(var.name)) + self._parse_error( + "Preprocessor function {} seems stuck " + "in infinite recursion".format(var.name) + ) var._n_expansions += 1 res = self._expand_whole(self.variables[fn].value, args) @@ -2865,8 +2933,9 @@ class Kconfig(object): py_fn, min_arg, max_arg = self._functions[fn] - if len(args) - 1 < min_arg or \ - (max_arg is not None and len(args) - 1 > max_arg): + if len(args) - 1 < min_arg or ( + max_arg is not None and len(args) - 1 > max_arg + ): if min_arg == max_arg: expected_args = min_arg @@ -2875,10 +2944,12 @@ class Kconfig(object): else: expected_args = "{}-{}".format(min_arg, max_arg) - raise KconfigError("{}:{}: bad number of arguments in call " - "to {}, expected {}, got {}" - .format(self.filename, self.linenr, fn, - expected_args, len(args) - 1)) + raise KconfigError( + "{}:{}: bad number of arguments in call " + "to {}, expected {}, got {}".format( + self.filename, self.linenr, fn, expected_args, len(args) - 1 + ) + ) return py_fn(self, *args) @@ -2962,7 +3033,7 @@ class Kconfig(object): node = MenuNode() node.kconfig = self node.item = sym - node.is_menuconfig = (t0 is _T_MENUCONFIG) + node.is_menuconfig = t0 is _T_MENUCONFIG node.prompt = node.help = node.list = None node.parent = parent node.filename = self.filename @@ -2974,8 +3045,11 @@ class Kconfig(object): self._parse_props(node) if node.is_menuconfig and not node.prompt: - self._warn("the menuconfig symbol {} has no prompt" - .format(sym.name_and_loc)) + self._warn( + "the menuconfig symbol {} has no prompt".format( + sym.name_and_loc + ) + ) # Equivalent to # @@ -3014,11 +3088,16 @@ class Kconfig(object): "{}:{}: '{}' not found (in '{}'). Check that " "environment variables are set correctly (e.g. " "$srctree, which is {}). Also note that unset " - "environment variables expand to the empty string." - .format(self.filename, self.linenr, pattern, - self._line.strip(), - "set to '{}'".format(self.srctree) - if self.srctree else "unset or blank")) + "environment variables expand to the empty string.".format( + self.filename, + self.linenr, + pattern, + self._line.strip(), + "set to '{}'".format(self.srctree) + if self.srctree + else "unset or blank", + ) + ) for filename in filenames: self._enter_file(filename) @@ -3125,20 +3204,28 @@ class Kconfig(object): # A valid endchoice/endif/endmenu is caught by the 'end_token' # check above self._parse_error( - "no corresponding 'choice'" if t0 is _T_ENDCHOICE else - "no corresponding 'if'" if t0 is _T_ENDIF else - "no corresponding 'menu'" if t0 is _T_ENDMENU else - "unrecognized construct") + "no corresponding 'choice'" + if t0 is _T_ENDCHOICE + else "no corresponding 'if'" + if t0 is _T_ENDIF + else "no corresponding 'menu'" + if t0 is _T_ENDMENU + else "unrecognized construct" + ) # End of file reached. Return the last node. if end_token: raise KconfigError( - "error: expected '{}' at end of '{}'" - .format("endchoice" if end_token is _T_ENDCHOICE else - "endif" if end_token is _T_ENDIF else - "endmenu", - self.filename)) + "error: expected '{}' at end of '{}'".format( + "endchoice" + if end_token is _T_ENDCHOICE + else "endif" + if end_token is _T_ENDIF + else "endmenu", + self.filename, + ) + ) return prev @@ -3187,8 +3274,7 @@ class Kconfig(object): if not self._check_token(_T_ON): self._parse_error("expected 'on' after 'depends'") - node.dep = self._make_and(node.dep, - self._expect_expr_and_eol()) + node.dep = self._make_and(node.dep, self._expect_expr_and_eol()) elif t0 is _T_HELP: self._parse_help(node) @@ -3197,42 +3283,40 @@ class Kconfig(object): if node.item.__class__ is not Symbol: self._parse_error("only symbols can select") - node.selects.append((self._expect_nonconst_sym(), - self._parse_cond())) + node.selects.append((self._expect_nonconst_sym(), self._parse_cond())) elif t0 is None: # Blank line continue elif t0 is _T_DEFAULT: - node.defaults.append((self._parse_expr(False), - self._parse_cond())) + node.defaults.append((self._parse_expr(False), self._parse_cond())) elif t0 in _DEF_TOKEN_TO_TYPE: self._set_type(node.item, _DEF_TOKEN_TO_TYPE[t0]) - node.defaults.append((self._parse_expr(False), - self._parse_cond())) + node.defaults.append((self._parse_expr(False), self._parse_cond())) elif t0 is _T_PROMPT: self._parse_prompt(node) elif t0 is _T_RANGE: - node.ranges.append((self._expect_sym(), self._expect_sym(), - self._parse_cond())) + node.ranges.append( + (self._expect_sym(), self._expect_sym(), self._parse_cond()) + ) elif t0 is _T_IMPLY: if node.item.__class__ is not Symbol: self._parse_error("only symbols can imply") - node.implies.append((self._expect_nonconst_sym(), - self._parse_cond())) + node.implies.append((self._expect_nonconst_sym(), self._parse_cond())) elif t0 is _T_VISIBLE: if not self._check_token(_T_IF): self._parse_error("expected 'if' after 'visible'") - node.visibility = self._make_and(node.visibility, - self._expect_expr_and_eol()) + node.visibility = self._make_and( + node.visibility, self._expect_expr_and_eol() + ) elif t0 is _T_OPTION: if self._check_token(_T_ENV): @@ -3244,33 +3328,42 @@ class Kconfig(object): if env_var in os.environ: node.defaults.append( - (self._lookup_const_sym(os.environ[env_var]), - self.y)) + (self._lookup_const_sym(os.environ[env_var]), self.y) + ) else: - self._warn("{1} has 'option env=\"{0}\"', " - "but the environment variable {0} is not " - "set".format(node.item.name, env_var), - self.filename, self.linenr) + self._warn( + "{1} has 'option env=\"{0}\"', " + "but the environment variable {0} is not " + "set".format(node.item.name, env_var), + self.filename, + self.linenr, + ) if env_var != node.item.name: - self._warn("Kconfiglib expands environment variables " - "in strings directly, meaning you do not " - "need 'option env=...' \"bounce\" symbols. " - "For compatibility with the C tools, " - "rename {} to {} (so that the symbol name " - "matches the environment variable name)." - .format(node.item.name, env_var), - self.filename, self.linenr) + self._warn( + "Kconfiglib expands environment variables " + "in strings directly, meaning you do not " + "need 'option env=...' \"bounce\" symbols. " + "For compatibility with the C tools, " + "rename {} to {} (so that the symbol name " + "matches the environment variable name).".format( + node.item.name, env_var + ), + self.filename, + self.linenr, + ) elif self._check_token(_T_DEFCONFIG_LIST): if not self.defconfig_list: self.defconfig_list = node.item else: - self._warn("'option defconfig_list' set on multiple " - "symbols ({0} and {1}). Only {0} will be " - "used.".format(self.defconfig_list.name, - node.item.name), - self.filename, self.linenr) + self._warn( + "'option defconfig_list' set on multiple " + "symbols ({0} and {1}). Only {0} will be " + "used.".format(self.defconfig_list.name, node.item.name), + self.filename, + self.linenr, + ) elif self._check_token(_T_MODULES): # To reduce warning spam, only warn if 'option modules' is @@ -3279,20 +3372,24 @@ class Kconfig(object): # modules besides the kernel yet, and there it's likely to # keep being called "MODULES". if node.item is not self.modules: - self._warn("the 'modules' option is not supported. " - "Let me know if this is a problem for you, " - "as it wouldn't be that hard to implement. " - "Note that modules are supported -- " - "Kconfiglib just assumes the symbol name " - "MODULES, like older versions of the C " - "implementation did when 'option modules' " - "wasn't used.", - self.filename, self.linenr) + self._warn( + "the 'modules' option is not supported. " + "Let me know if this is a problem for you, " + "as it wouldn't be that hard to implement. " + "Note that modules are supported -- " + "Kconfiglib just assumes the symbol name " + "MODULES, like older versions of the C " + "implementation did when 'option modules' " + "wasn't used.", + self.filename, + self.linenr, + ) elif self._check_token(_T_ALLNOCONFIG_Y): if node.item.__class__ is not Symbol: - self._parse_error("the 'allnoconfig_y' option is only " - "valid for symbols") + self._parse_error( + "the 'allnoconfig_y' option is only " "valid for symbols" + ) node.item.is_allnoconfig_y = True @@ -3315,8 +3412,11 @@ class Kconfig(object): # UNKNOWN is falsy if sc.orig_type and sc.orig_type is not new_type: - self._warn("{} defined with multiple types, {} will be used" - .format(sc.name_and_loc, TYPE_TO_STR[new_type])) + self._warn( + "{} defined with multiple types, {} will be used".format( + sc.name_and_loc, TYPE_TO_STR[new_type] + ) + ) sc.orig_type = new_type @@ -3326,8 +3426,10 @@ class Kconfig(object): # multiple times if node.prompt: - self._warn(node.item.name_and_loc + - " defined with multiple prompts in single location") + self._warn( + node.item.name_and_loc + + " defined with multiple prompts in single location" + ) prompt = self._tokens[1] self._tokens_i = 2 @@ -3336,8 +3438,10 @@ class Kconfig(object): self._parse_error("expected prompt string") if prompt != prompt.strip(): - self._warn(node.item.name_and_loc + - " has leading or trailing whitespace in its prompt") + self._warn( + node.item.name_and_loc + + " has leading or trailing whitespace in its prompt" + ) # This avoid issues for e.g. reStructuredText documentation, where # '*prompt *' is invalid @@ -3347,8 +3451,10 @@ class Kconfig(object): def _parse_help(self, node): if node.help is not None: - self._warn(node.item.name_and_loc + " defined with more than " - "one help text -- only the last one will be used") + self._warn( + node.item.name_and_loc + " defined with more than " + "one help text -- only the last one will be used" + ) # Micro-optimization. This code is pretty hot. readline = self._readline @@ -3403,8 +3509,7 @@ class Kconfig(object): self._line_after_help(line) def _empty_help(self, node, line): - self._warn(node.item.name_and_loc + - " has 'help' but empty help text") + self._warn(node.item.name_and_loc + " has 'help' but empty help text") node.help = "" if line: self._line_after_help(line) @@ -3447,8 +3552,11 @@ class Kconfig(object): # Return 'and_expr' directly if we have a "single-operand" OR. # Otherwise, parse the expression on the right and make an OR node. # This turns A || B || C || D into (OR, A, (OR, B, (OR, C, D))). - return and_expr if not self._check_token(_T_OR) else \ - (OR, and_expr, self._parse_expr(transform_m)) + return ( + and_expr + if not self._check_token(_T_OR) + else (OR, and_expr, self._parse_expr(transform_m)) + ) def _parse_and_expr(self, transform_m): factor = self._parse_factor(transform_m) @@ -3456,8 +3564,11 @@ class Kconfig(object): # Return 'factor' directly if we have a "single-operand" AND. # Otherwise, parse the right operand and make an AND node. This turns # A && B && C && D into (AND, A, (AND, B, (AND, C, D))). - return factor if not self._check_token(_T_AND) else \ - (AND, factor, self._parse_and_expr(transform_m)) + return ( + factor + if not self._check_token(_T_AND) + else (AND, factor, self._parse_and_expr(transform_m)) + ) def _parse_factor(self, transform_m): token = self._tokens[self._tokens_i] @@ -3481,8 +3592,7 @@ class Kconfig(object): # _T_EQUAL, _T_UNEQUAL, etc., deliberately have the same values as # EQUAL, UNEQUAL, etc., so we can just use the token directly self._tokens_i += 1 - return (self._tokens[self._tokens_i - 1], token, - self._expect_sym()) + return (self._tokens[self._tokens_i - 1], token, self._expect_sym()) if token is _T_NOT: # token == _T_NOT == NOT @@ -3689,36 +3799,43 @@ class Kconfig(object): if cur.item.__class__ in _SYMBOL_CHOICE: # Propagate 'visible if' and dependencies to the prompt if cur.prompt: - cur.prompt = (cur.prompt[0], - self._make_and( - cur.prompt[1], - self._make_and(visible_if, dep))) + cur.prompt = ( + cur.prompt[0], + self._make_and(cur.prompt[1], self._make_and(visible_if, dep)), + ) # Propagate dependencies to defaults if cur.defaults: - cur.defaults = [(default, self._make_and(cond, dep)) - for default, cond in cur.defaults] + cur.defaults = [ + (default, self._make_and(cond, dep)) + for default, cond in cur.defaults + ] # Propagate dependencies to ranges if cur.ranges: - cur.ranges = [(low, high, self._make_and(cond, dep)) - for low, high, cond in cur.ranges] + cur.ranges = [ + (low, high, self._make_and(cond, dep)) + for low, high, cond in cur.ranges + ] # Propagate dependencies to selects if cur.selects: - cur.selects = [(target, self._make_and(cond, dep)) - for target, cond in cur.selects] + cur.selects = [ + (target, self._make_and(cond, dep)) + for target, cond in cur.selects + ] # Propagate dependencies to implies if cur.implies: - cur.implies = [(target, self._make_and(cond, dep)) - for target, cond in cur.implies] + cur.implies = [ + (target, self._make_and(cond, dep)) + for target, cond in cur.implies + ] elif cur.prompt: # Not a symbol/choice # Propagate dependencies to the prompt. 'visible if' is only # propagated to symbols/choices. - cur.prompt = (cur.prompt[0], - self._make_and(cur.prompt[1], dep)) + cur.prompt = (cur.prompt[0], self._make_and(cur.prompt[1], dep)) cur = cur.next @@ -3744,16 +3861,14 @@ class Kconfig(object): # Modify the reverse dependencies of the selected symbol for target, cond in node.selects: - target.rev_dep = self._make_or( - target.rev_dep, - self._make_and(sym, cond)) + target.rev_dep = self._make_or(target.rev_dep, self._make_and(sym, cond)) # Modify the weak reverse dependencies of the implied # symbol for target, cond in node.implies: target.weak_rev_dep = self._make_or( - target.weak_rev_dep, - self._make_and(sym, cond)) + target.weak_rev_dep, self._make_and(sym, cond) + ) # # Misc. @@ -3781,82 +3896,106 @@ class Kconfig(object): for target_sym, _ in sym.selects: if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN: - self._warn("{} selects the {} symbol {}, which is not " - "bool or tristate" - .format(sym.name_and_loc, - TYPE_TO_STR[target_sym.orig_type], - target_sym.name_and_loc)) + self._warn( + "{} selects the {} symbol {}, which is not " + "bool or tristate".format( + sym.name_and_loc, + TYPE_TO_STR[target_sym.orig_type], + target_sym.name_and_loc, + ) + ) for target_sym, _ in sym.implies: if target_sym.orig_type not in _BOOL_TRISTATE_UNKNOWN: - self._warn("{} implies the {} symbol {}, which is not " - "bool or tristate" - .format(sym.name_and_loc, - TYPE_TO_STR[target_sym.orig_type], - target_sym.name_and_loc)) + self._warn( + "{} implies the {} symbol {}, which is not " + "bool or tristate".format( + sym.name_and_loc, + TYPE_TO_STR[target_sym.orig_type], + target_sym.name_and_loc, + ) + ) elif sym.orig_type: # STRING/INT/HEX for default, _ in sym.defaults: if default.__class__ is not Symbol: raise KconfigError( "the {} symbol {} has a malformed default {} -- " - "expected a single symbol" - .format(TYPE_TO_STR[sym.orig_type], - sym.name_and_loc, expr_str(default))) + "expected a single symbol".format( + TYPE_TO_STR[sym.orig_type], + sym.name_and_loc, + expr_str(default), + ) + ) if sym.orig_type is STRING: - if not default.is_constant and not default.nodes and \ - not default.name.isupper(): + if ( + not default.is_constant + and not default.nodes + and not default.name.isupper() + ): # 'default foo' on a string symbol could be either a symbol # reference or someone leaving out the quotes. Guess that # the quotes were left out if 'foo' isn't all-uppercase # (and no symbol named 'foo' exists). - self._warn("style: quotes recommended around " - "default value for string symbol " - + sym.name_and_loc) + self._warn( + "style: quotes recommended around " + "default value for string symbol " + sym.name_and_loc + ) elif not num_ok(default, sym.orig_type): # INT/HEX - self._warn("the {0} symbol {1} has a non-{0} default {2}" - .format(TYPE_TO_STR[sym.orig_type], - sym.name_and_loc, - default.name_and_loc)) + self._warn( + "the {0} symbol {1} has a non-{0} default {2}".format( + TYPE_TO_STR[sym.orig_type], + sym.name_and_loc, + default.name_and_loc, + ) + ) if sym.selects or sym.implies: - self._warn("the {} symbol {} has selects or implies" - .format(TYPE_TO_STR[sym.orig_type], - sym.name_and_loc)) + self._warn( + "the {} symbol {} has selects or implies".format( + TYPE_TO_STR[sym.orig_type], sym.name_and_loc + ) + ) else: # UNKNOWN - self._warn("{} defined without a type" - .format(sym.name_and_loc)) - + self._warn("{} defined without a type".format(sym.name_and_loc)) if sym.ranges: if sym.orig_type not in _INT_HEX: self._warn( - "the {} symbol {} has ranges, but is not int or hex" - .format(TYPE_TO_STR[sym.orig_type], - sym.name_and_loc)) + "the {} symbol {} has ranges, but is not int or hex".format( + TYPE_TO_STR[sym.orig_type], sym.name_and_loc + ) + ) else: for low, high, _ in sym.ranges: - if not num_ok(low, sym.orig_type) or \ - not num_ok(high, sym.orig_type): - - self._warn("the {0} symbol {1} has a non-{0} " - "range [{2}, {3}]" - .format(TYPE_TO_STR[sym.orig_type], - sym.name_and_loc, - low.name_and_loc, - high.name_and_loc)) + if not num_ok(low, sym.orig_type) or not num_ok( + high, sym.orig_type + ): + + self._warn( + "the {0} symbol {1} has a non-{0} " + "range [{2}, {3}]".format( + TYPE_TO_STR[sym.orig_type], + sym.name_and_loc, + low.name_and_loc, + high.name_and_loc, + ) + ) def _check_choice_sanity(self): # Checks various choice properties that are handiest to check after # parsing. Only generates errors and warnings. def warn_select_imply(sym, expr, expr_type): - msg = "the choice symbol {} is {} by the following symbols, but " \ - "select/imply has no effect on choice symbols" \ - .format(sym.name_and_loc, expr_type) + msg = ( + "the choice symbol {} is {} by the following symbols, but " + "select/imply has no effect on choice symbols".format( + sym.name_and_loc, expr_type + ) + ) # si = select/imply for si in split_expr(expr, OR): @@ -3866,9 +4005,11 @@ class Kconfig(object): for choice in self.unique_choices: if choice.orig_type not in _BOOL_TRISTATE: - self._warn("{} defined with type {}" - .format(choice.name_and_loc, - TYPE_TO_STR[choice.orig_type])) + self._warn( + "{} defined with type {}".format( + choice.name_and_loc, TYPE_TO_STR[choice.orig_type] + ) + ) for node in choice.nodes: if node.prompt: @@ -3879,20 +4020,26 @@ class Kconfig(object): for default, _ in choice.defaults: if default.__class__ is not Symbol: raise KconfigError( - "{} has a malformed default {}" - .format(choice.name_and_loc, expr_str(default))) + "{} has a malformed default {}".format( + choice.name_and_loc, expr_str(default) + ) + ) if default.choice is not choice: - self._warn("the default selection {} of {} is not " - "contained in the choice" - .format(default.name_and_loc, - choice.name_and_loc)) + self._warn( + "the default selection {} of {} is not " + "contained in the choice".format( + default.name_and_loc, choice.name_and_loc + ) + ) for sym in choice.syms: if sym.defaults: - self._warn("default on the choice symbol {} will have " - "no effect, as defaults do not affect choice " - "symbols".format(sym.name_and_loc)) + self._warn( + "default on the choice symbol {} will have " + "no effect, as defaults do not affect choice " + "symbols".format(sym.name_and_loc) + ) if sym.rev_dep is not sym.kconfig.n: warn_select_imply(sym, sym.rev_dep, "selected") @@ -3903,19 +4050,28 @@ class Kconfig(object): for node in sym.nodes: if node.parent.item is choice: if not node.prompt: - self._warn("the choice symbol {} has no prompt" - .format(sym.name_and_loc)) + self._warn( + "the choice symbol {} has no prompt".format( + sym.name_and_loc + ) + ) elif node.prompt: - self._warn("the choice symbol {} is defined with a " - "prompt outside the choice" - .format(sym.name_and_loc)) + self._warn( + "the choice symbol {} is defined with a " + "prompt outside the choice".format(sym.name_and_loc) + ) def _parse_error(self, msg): - raise KconfigError("{}error: couldn't parse '{}': {}".format( - "" if self.filename is None else - "{}:{}: ".format(self.filename, self.linenr), - self._line.strip(), msg)) + raise KconfigError( + "{}error: couldn't parse '{}': {}".format( + "" + if self.filename is None + else "{}:{}: ".format(self.filename, self.linenr), + self._line.strip(), + msg, + ) + ) def _trailing_tokens_error(self): self._parse_error("extra tokens at end of line") @@ -3954,8 +4110,11 @@ class Kconfig(object): # - For Python 3, force the encoding. Forcing the encoding on Python 2 # turns strings into Unicode strings, which gets messy. Python 2 # doesn't decode regular strings anyway. - return open(filename, "rU" if mode == "r" else mode) if _IS_PY2 else \ - open(filename, mode, encoding=self._encoding) + return ( + open(filename, "rU" if mode == "r" else mode) + if _IS_PY2 + else open(filename, mode, encoding=self._encoding) + ) def _check_undef_syms(self): # Prints warnings for all references to undefined symbols within the @@ -3992,14 +4151,14 @@ class Kconfig(object): # symbols, but shouldn't be flagged # # - The MODULES symbol always exists - if not sym.nodes and not is_num(sym.name) and \ - sym.name != "MODULES": + if not sym.nodes and not is_num(sym.name) and sym.name != "MODULES": msg = "undefined symbol {}:".format(sym.name) for node in self.node_iter(): if sym in node.referenced: - msg += "\n\n- Referenced at {}:{}:\n\n{}" \ - .format(node.filename, node.linenr, node) + msg += "\n\n- Referenced at {}:{}:\n\n{}".format( + node.filename, node.linenr, node + ) self._warn(msg) def _warn(self, msg, filename=None, linenr=None): @@ -4274,6 +4433,7 @@ class Symbol(object): kconfig: The Kconfig instance this symbol is from. """ + __slots__ = ( "_cached_assignable", "_cached_str_val", @@ -4311,9 +4471,11 @@ class Symbol(object): """ See the class documentation. """ - if self.orig_type is TRISTATE and \ - (self.choice and self.choice.tri_value == 2 or - not self.kconfig.modules.tri_value): + if self.orig_type is TRISTATE and ( + self.choice + and self.choice.tri_value == 2 + or not self.kconfig.modules.tri_value + ): return BOOL @@ -4344,7 +4506,7 @@ class Symbol(object): # function call (property magic) vis = self.visibility - self._write_to_conf = (vis != 0) + self._write_to_conf = vis != 0 if self.orig_type in _INT_HEX: # The C implementation checks the user value against the range in a @@ -4361,10 +4523,16 @@ class Symbol(object): # The zeros are from the C implementation running strtoll() # on empty strings - low = int(low_expr.str_value, base) if \ - _is_base_n(low_expr.str_value, base) else 0 - high = int(high_expr.str_value, base) if \ - _is_base_n(high_expr.str_value, base) else 0 + low = ( + int(low_expr.str_value, base) + if _is_base_n(low_expr.str_value, base) + else 0 + ) + high = ( + int(high_expr.str_value, base) + if _is_base_n(high_expr.str_value, base) + else 0 + ) break else: @@ -4381,10 +4549,14 @@ class Symbol(object): self.kconfig._warn( "user value {} on the {} symbol {} ignored due to " "being outside the active range ([{}, {}]) -- falling " - "back on defaults" - .format(num2str(user_val), TYPE_TO_STR[self.orig_type], - self.name_and_loc, - num2str(low), num2str(high))) + "back on defaults".format( + num2str(user_val), + TYPE_TO_STR[self.orig_type], + self.name_and_loc, + num2str(low), + num2str(high), + ) + ) else: # If the user value is well-formed and satisfies range # contraints, it is stored in exactly the same form as @@ -4424,18 +4596,20 @@ class Symbol(object): if clamp is not None: # The value is rewritten to a standard form if it is # clamped - val = str(clamp) \ - if self.orig_type is INT else \ - hex(clamp) + val = str(clamp) if self.orig_type is INT else hex(clamp) if has_default: num2str = str if base == 10 else hex self.kconfig._warn( "default value {} on {} clamped to {} due to " - "being outside the active range ([{}, {}])" - .format(val_num, self.name_and_loc, - num2str(clamp), num2str(low), - num2str(high))) + "being outside the active range ([{}, {}])".format( + val_num, + self.name_and_loc, + num2str(clamp), + num2str(low), + num2str(high), + ) + ) elif self.orig_type is STRING: if vis and self.user_value is not None: @@ -4473,8 +4647,10 @@ class Symbol(object): # Would take some work to give the location here self.kconfig._warn( "The {} symbol {} is being evaluated in a logical context " - "somewhere. It will always evaluate to n." - .format(TYPE_TO_STR[self.orig_type], self.name_and_loc)) + "somewhere. It will always evaluate to n.".format( + TYPE_TO_STR[self.orig_type], self.name_and_loc + ) + ) self._cached_tri_val = 0 return 0 @@ -4482,7 +4658,7 @@ class Symbol(object): # Warning: See Symbol._rec_invalidate(), and note that this is a hidden # function call (property magic) vis = self.visibility - self._write_to_conf = (vis != 0) + self._write_to_conf = vis != 0 val = 0 @@ -4523,8 +4699,7 @@ class Symbol(object): # m is promoted to y for (1) bool symbols and (2) symbols with a # weak_rev_dep (from imply) of y - if val == 1 and \ - (self.type is BOOL or expr_value(self.weak_rev_dep) == 2): + if val == 1 and (self.type is BOOL or expr_value(self.weak_rev_dep) == 2): val = 2 elif vis == 2: @@ -4570,19 +4745,17 @@ class Symbol(object): return "" if self.orig_type in _BOOL_TRISTATE: - return "{}{}={}\n" \ - .format(self.kconfig.config_prefix, self.name, val) \ - if val != "n" else \ - "# {}{} is not set\n" \ - .format(self.kconfig.config_prefix, self.name) + return ( + "{}{}={}\n".format(self.kconfig.config_prefix, self.name, val) + if val != "n" + else "# {}{} is not set\n".format(self.kconfig.config_prefix, self.name) + ) if self.orig_type in _INT_HEX: - return "{}{}={}\n" \ - .format(self.kconfig.config_prefix, self.name, val) + return "{}{}={}\n".format(self.kconfig.config_prefix, self.name, val) # sym.orig_type is STRING - return '{}{}="{}"\n' \ - .format(self.kconfig.config_prefix, self.name, escape(val)) + return '{}{}="{}"\n'.format(self.kconfig.config_prefix, self.name, escape(val)) @property def name_and_loc(self): @@ -4646,21 +4819,31 @@ class Symbol(object): return True # Check if the value is valid for our type - if not (self.orig_type is BOOL and value in (2, 0) or - self.orig_type is TRISTATE and value in TRI_TO_STR or - value.__class__ is str and - (self.orig_type is STRING or - self.orig_type is INT and _is_base_n(value, 10) or - self.orig_type is HEX and _is_base_n(value, 16) - and int(value, 16) >= 0)): + if not ( + self.orig_type is BOOL + and value in (2, 0) + or self.orig_type is TRISTATE + and value in TRI_TO_STR + or value.__class__ is str + and ( + self.orig_type is STRING + or self.orig_type is INT + and _is_base_n(value, 10) + or self.orig_type is HEX + and _is_base_n(value, 16) + and int(value, 16) >= 0 + ) + ): # Display tristate values as n, m, y in the warning self.kconfig._warn( "the value {} is invalid for {}, which has type {} -- " - "assignment ignored" - .format(TRI_TO_STR[value] if value in TRI_TO_STR else - "'{}'".format(value), - self.name_and_loc, TYPE_TO_STR[self.orig_type])) + "assignment ignored".format( + TRI_TO_STR[value] if value in TRI_TO_STR else "'{}'".format(value), + self.name_and_loc, + TYPE_TO_STR[self.orig_type], + ) + ) return False @@ -4738,17 +4921,28 @@ class Symbol(object): add('"{}"'.format(node.prompt[0])) # Only add quotes for non-bool/tristate symbols - add("value " + (self.str_value if self.orig_type in _BOOL_TRISTATE - else '"{}"'.format(self.str_value))) + add( + "value " + + ( + self.str_value + if self.orig_type in _BOOL_TRISTATE + else '"{}"'.format(self.str_value) + ) + ) if not self.is_constant: # These aren't helpful to show for constant symbols if self.user_value is not None: # Only add quotes for non-bool/tristate symbols - add("user value " + (TRI_TO_STR[self.user_value] - if self.orig_type in _BOOL_TRISTATE - else '"{}"'.format(self.user_value))) + add( + "user value " + + ( + TRI_TO_STR[self.user_value] + if self.orig_type in _BOOL_TRISTATE + else '"{}"'.format(self.user_value) + ) + ) add("visibility " + TRI_TO_STR[self.visibility]) @@ -4798,8 +4992,7 @@ class Symbol(object): Works like Symbol.__str__(), but allows a custom format to be used for all symbol/choice references. See expr_str(). """ - return "\n\n".join(node.custom_str(sc_expr_str_fn) - for node in self.nodes) + return "\n\n".join(node.custom_str(sc_expr_str_fn) for node in self.nodes) # # Private methods @@ -4830,18 +5023,18 @@ class Symbol(object): self.implies = [] self.ranges = [] - self.user_value = \ - self.choice = \ - self.env_var = \ - self._cached_str_val = self._cached_tri_val = self._cached_vis = \ - self._cached_assignable = None + self.user_value = ( + self.choice + ) = ( + self.env_var + ) = ( + self._cached_str_val + ) = self._cached_tri_val = self._cached_vis = self._cached_assignable = None # _write_to_conf is calculated along with the value. If True, the # Symbol gets a .config entry. - self.is_allnoconfig_y = \ - self._was_set = \ - self._write_to_conf = False + self.is_allnoconfig_y = self._was_set = self._write_to_conf = False # See Kconfig._build_dep() self._dependents = set() @@ -4895,8 +5088,9 @@ class Symbol(object): def _invalidate(self): # Marks the symbol as needing to be recalculated - self._cached_str_val = self._cached_tri_val = self._cached_vis = \ - self._cached_assignable = None + self._cached_str_val = ( + self._cached_tri_val + ) = self._cached_vis = self._cached_assignable = None def _rec_invalidate(self): # Invalidates the symbol and all items that (possibly) depend on it @@ -4948,8 +5142,10 @@ class Symbol(object): return if self.kconfig._warn_assign_no_prompt: - self.kconfig._warn(self.name_and_loc + " has no prompt, meaning " - "user values have no effect on it") + self.kconfig._warn( + self.name_and_loc + " has no prompt, meaning " + "user values have no effect on it" + ) def _str_default(self): # write_min_config() helper function. Returns the value the symbol @@ -4968,9 +5164,7 @@ class Symbol(object): val = min(expr_value(default), cond_val) break - val = max(expr_value(self.rev_dep), - expr_value(self.weak_rev_dep), - val) + val = max(expr_value(self.rev_dep), expr_value(self.weak_rev_dep), val) # Transpose mod to yes if type is bool (possibly due to modules # being disabled) @@ -4992,11 +5186,15 @@ class Symbol(object): # and menus) is selected by some other symbol. Also warn if a symbol # whose direct dependencies evaluate to m is selected to y. - msg = "{} has direct dependencies {} with value {}, but is " \ - "currently being {}-selected by the following symbols:" \ - .format(self.name_and_loc, expr_str(self.direct_dep), - TRI_TO_STR[expr_value(self.direct_dep)], - TRI_TO_STR[expr_value(self.rev_dep)]) + msg = ( + "{} has direct dependencies {} with value {}, but is " + "currently being {}-selected by the following symbols:".format( + self.name_and_loc, + expr_str(self.direct_dep), + TRI_TO_STR[expr_value(self.direct_dep)], + TRI_TO_STR[expr_value(self.rev_dep)], + ) + ) # The reverse dependencies from each select are ORed together for select in split_expr(self.rev_dep, OR): @@ -5010,17 +5208,20 @@ class Symbol(object): # In both cases, we can split on AND and pick the first operand selecting_sym = split_expr(select, AND)[0] - msg += "\n - {}, with value {}, direct dependencies {} " \ - "(value: {})" \ - .format(selecting_sym.name_and_loc, - selecting_sym.str_value, - expr_str(selecting_sym.direct_dep), - TRI_TO_STR[expr_value(selecting_sym.direct_dep)]) + msg += ( + "\n - {}, with value {}, direct dependencies {} " + "(value: {})".format( + selecting_sym.name_and_loc, + selecting_sym.str_value, + expr_str(selecting_sym.direct_dep), + TRI_TO_STR[expr_value(selecting_sym.direct_dep)], + ) + ) if select.__class__ is tuple: - msg += ", and select condition {} (value: {})" \ - .format(expr_str(select[2]), - TRI_TO_STR[expr_value(select[2])]) + msg += ", and select condition {} (value: {})".format( + expr_str(select[2]), TRI_TO_STR[expr_value(select[2])] + ) self.kconfig._warn(msg) @@ -5182,6 +5383,7 @@ class Choice(object): kconfig: The Kconfig instance this choice is from. """ + __slots__ = ( "_cached_assignable", "_cached_selection", @@ -5299,16 +5501,22 @@ class Choice(object): self._was_set = True return True - if not (self.orig_type is BOOL and value in (2, 0) or - self.orig_type is TRISTATE and value in TRI_TO_STR): + if not ( + self.orig_type is BOOL + and value in (2, 0) + or self.orig_type is TRISTATE + and value in TRI_TO_STR + ): # Display tristate values as n, m, y in the warning self.kconfig._warn( "the value {} is invalid for {}, which has type {} -- " - "assignment ignored" - .format(TRI_TO_STR[value] if value in TRI_TO_STR else - "'{}'".format(value), - self.name_and_loc, TYPE_TO_STR[self.orig_type])) + "assignment ignored".format( + TRI_TO_STR[value] if value in TRI_TO_STR else "'{}'".format(value), + self.name_and_loc, + TYPE_TO_STR[self.orig_type], + ) + ) return False @@ -5346,8 +5554,10 @@ class Choice(object): Returns a string with information about the choice when it is evaluated on e.g. the interactive Python prompt. """ - fields = ["choice " + self.name if self.name else "choice", - TYPE_TO_STR[self.type]] + fields = [ + "choice " + self.name if self.name else "choice", + TYPE_TO_STR[self.type], + ] add = fields.append for node in self.nodes: @@ -5357,14 +5567,13 @@ class Choice(object): add("mode " + self.str_value) if self.user_value is not None: - add('user mode {}'.format(TRI_TO_STR[self.user_value])) + add("user mode {}".format(TRI_TO_STR[self.user_value])) if self.selection: add("{} selected".format(self.selection.name)) if self.user_selection: - user_sel_str = "{} selected by user" \ - .format(self.user_selection.name) + user_sel_str = "{} selected by user".format(self.user_selection.name) if self.selection is not self.user_selection: user_sel_str += " (overridden)" @@ -5399,8 +5608,7 @@ class Choice(object): Works like Choice.__str__(), but allows a custom format to be used for all symbol/choice references. See expr_str(). """ - return "\n\n".join(node.custom_str(sc_expr_str_fn) - for node in self.nodes) + return "\n\n".join(node.custom_str(sc_expr_str_fn) for node in self.nodes) # # Private methods @@ -5425,9 +5633,9 @@ class Choice(object): self.syms = [] self.defaults = [] - self.name = \ - self.user_value = self.user_selection = \ - self._cached_vis = self._cached_assignable = None + self.name = ( + self.user_value + ) = self.user_selection = self._cached_vis = self._cached_assignable = None self._cached_selection = _NO_CACHED_SELECTION @@ -5644,6 +5852,7 @@ class MenuNode(object): kconfig: The Kconfig instance the menu node is from. """ + __slots__ = ( "dep", "filename", @@ -5658,7 +5867,6 @@ class MenuNode(object): "parent", "prompt", "visibility", - # Properties "defaults", "selects", @@ -5689,32 +5897,28 @@ class MenuNode(object): """ See the class documentation. """ - return [(default, self._strip_dep(cond)) - for default, cond in self.defaults] + return [(default, self._strip_dep(cond)) for default, cond in self.defaults] @property def orig_selects(self): """ See the class documentation. """ - return [(select, self._strip_dep(cond)) - for select, cond in self.selects] + return [(select, self._strip_dep(cond)) for select, cond in self.selects] @property def orig_implies(self): """ See the class documentation. """ - return [(imply, self._strip_dep(cond)) - for imply, cond in self.implies] + return [(imply, self._strip_dep(cond)) for imply, cond in self.implies] @property def orig_ranges(self): """ See the class documentation. """ - return [(low, high, self._strip_dep(cond)) - for low, high, cond in self.ranges] + return [(low, high, self._strip_dep(cond)) for low, high, cond in self.ranges] @property def referenced(self): @@ -5774,8 +5978,11 @@ class MenuNode(object): add("menu node for comment") if self.prompt: - add('prompt "{}" (visibility {})'.format( - self.prompt[0], TRI_TO_STR[expr_value(self.prompt[1])])) + add( + 'prompt "{}" (visibility {})'.format( + self.prompt[0], TRI_TO_STR[expr_value(self.prompt[1])] + ) + ) if self.item.__class__ is Symbol and self.is_menuconfig: add("is menuconfig") @@ -5822,20 +6029,20 @@ class MenuNode(object): Works like MenuNode.__str__(), but allows a custom format to be used for all symbol/choice references. See expr_str(). """ - return self._menu_comment_node_str(sc_expr_str_fn) \ - if self.item in _MENU_COMMENT else \ - self._sym_choice_node_str(sc_expr_str_fn) + return ( + self._menu_comment_node_str(sc_expr_str_fn) + if self.item in _MENU_COMMENT + else self._sym_choice_node_str(sc_expr_str_fn) + ) def _menu_comment_node_str(self, sc_expr_str_fn): - s = '{} "{}"'.format("menu" if self.item is MENU else "comment", - self.prompt[0]) + s = '{} "{}"'.format("menu" if self.item is MENU else "comment", self.prompt[0]) if self.dep is not self.kconfig.y: s += "\n\tdepends on {}".format(expr_str(self.dep, sc_expr_str_fn)) if self.item is MENU and self.visibility is not self.kconfig.y: - s += "\n\tvisible if {}".format(expr_str(self.visibility, - sc_expr_str_fn)) + s += "\n\tvisible if {}".format(expr_str(self.visibility, sc_expr_str_fn)) return s @@ -5851,8 +6058,7 @@ class MenuNode(object): sc = self.item if sc.__class__ is Symbol: - lines = [("menuconfig " if self.is_menuconfig else "config ") - + sc.name] + lines = [("menuconfig " if self.is_menuconfig else "config ") + sc.name] else: lines = ["choice " + sc.name if sc.name else "choice"] @@ -5868,8 +6074,9 @@ class MenuNode(object): # Symbol defined without a type (which generates a warning) prefix = "prompt" - indent_add_cond(prefix + ' "{}"'.format(escape(self.prompt[0])), - self.orig_prompt[1]) + indent_add_cond( + prefix + ' "{}"'.format(escape(self.prompt[0])), self.orig_prompt[1] + ) if sc.__class__ is Symbol: if sc.is_allnoconfig_y: @@ -5886,13 +6093,12 @@ class MenuNode(object): for low, high, cond in self.orig_ranges: indent_add_cond( - "range {} {}".format(sc_expr_str_fn(low), - sc_expr_str_fn(high)), - cond) + "range {} {}".format(sc_expr_str_fn(low), sc_expr_str_fn(high)), + cond, + ) for default, cond in self.orig_defaults: - indent_add_cond("default " + expr_str(default, sc_expr_str_fn), - cond) + indent_add_cond("default " + expr_str(default, sc_expr_str_fn), cond) if sc.__class__ is Choice and sc.is_optional: indent_add("optional") @@ -5954,6 +6160,7 @@ class Variable(object): is_recursive: True if the variable is recursive (defined with =). """ + __slots__ = ( "_n_expansions", "is_recursive", @@ -5979,10 +6186,9 @@ class Variable(object): return self.kconfig._fn_val((self.name,) + args) def __repr__(self): - return "" \ - .format(self.name, - "recursive" if self.is_recursive else "immediate", - self.value) + return "".format( + self.name, "recursive" if self.is_recursive else "immediate", self.value + ) class KconfigError(Exception): @@ -5993,6 +6199,7 @@ class KconfigError(Exception): KconfigSyntaxError alias is only maintained for backwards compatibility. """ + KconfigSyntaxError = KconfigError # Backwards compatibility @@ -6010,7 +6217,8 @@ class _KconfigIOError(IOError): def __init__(self, ioerror, msg): self.msg = msg super(_KconfigIOError, self).__init__( - ioerror.errno, ioerror.strerror, ioerror.filename) + ioerror.errno, ioerror.strerror, ioerror.filename + ) def __str__(self): return self.msg @@ -6070,12 +6278,19 @@ def expr_value(expr): # parse as numbers comp = _strcmp(v1.str_value, v2.str_value) - return 2*(comp == 0 if rel is EQUAL else - comp != 0 if rel is UNEQUAL else - comp < 0 if rel is LESS else - comp <= 0 if rel is LESS_EQUAL else - comp > 0 if rel is GREATER else - comp >= 0) + return 2 * ( + comp == 0 + if rel is EQUAL + else comp != 0 + if rel is UNEQUAL + else comp < 0 + if rel is LESS + else comp <= 0 + if rel is LESS_EQUAL + else comp > 0 + if rel is GREATER + else comp >= 0 + ) def standard_sc_expr_str(sc): @@ -6115,14 +6330,18 @@ def expr_str(expr, sc_expr_str_fn=standard_sc_expr_str): return sc_expr_str_fn(expr) if expr[0] is AND: - return "{} && {}".format(_parenthesize(expr[1], OR, sc_expr_str_fn), - _parenthesize(expr[2], OR, sc_expr_str_fn)) + return "{} && {}".format( + _parenthesize(expr[1], OR, sc_expr_str_fn), + _parenthesize(expr[2], OR, sc_expr_str_fn), + ) if expr[0] is OR: # This turns A && B || C && D into "(A && B) || (C && D)", which is # redundant, but more readable - return "{} || {}".format(_parenthesize(expr[1], AND, sc_expr_str_fn), - _parenthesize(expr[2], AND, sc_expr_str_fn)) + return "{} || {}".format( + _parenthesize(expr[1], AND, sc_expr_str_fn), + _parenthesize(expr[2], AND, sc_expr_str_fn), + ) if expr[0] is NOT: if expr[1].__class__ is tuple: @@ -6133,8 +6352,9 @@ def expr_str(expr, sc_expr_str_fn=standard_sc_expr_str): # # Relation operands are always symbols (quoted strings are constant # symbols) - return "{} {} {}".format(sc_expr_str_fn(expr[1]), REL_TO_STR[expr[0]], - sc_expr_str_fn(expr[2])) + return "{} {} {}".format( + sc_expr_str_fn(expr[1]), REL_TO_STR[expr[0]], sc_expr_str_fn(expr[2]) + ) def expr_items(expr): @@ -6216,7 +6436,7 @@ def escape(s): replaced by \" and \\, respectively. """ # \ must be escaped before " to avoid double escaping - return s.replace("\\", r"\\").replace('"', r'\"') + return s.replace("\\", r"\\").replace('"', r"\"") def unescape(s): @@ -6226,6 +6446,7 @@ def unescape(s): """ return _unescape_sub(r"\1", s) + # unescape() helper _unescape_sub = re.compile(r"\\(.)").sub @@ -6245,15 +6466,16 @@ def standard_kconfig(description=None): import argparse parser = argparse.ArgumentParser( - formatter_class=argparse.RawDescriptionHelpFormatter, - description=description) + formatter_class=argparse.RawDescriptionHelpFormatter, description=description + ) parser.add_argument( "kconfig", metavar="KCONFIG", default="Kconfig", nargs="?", - help="Top-level Kconfig file (default: Kconfig)") + help="Top-level Kconfig file (default: Kconfig)", + ) return Kconfig(parser.parse_args().kconfig, suppress_traceback=True) @@ -6299,16 +6521,20 @@ def load_allconfig(kconf, filename): try: print(kconf.load_config("all.config", False)) except EnvironmentError as e2: - sys.exit("error: KCONFIG_ALLCONFIG is set, but neither {} " - "nor all.config could be opened: {}, {}" - .format(filename, std_msg(e1), std_msg(e2))) + sys.exit( + "error: KCONFIG_ALLCONFIG is set, but neither {} " + "nor all.config could be opened: {}, {}".format( + filename, std_msg(e1), std_msg(e2) + ) + ) else: try: print(kconf.load_config(allconfig, False)) except EnvironmentError as e: - sys.exit("error: KCONFIG_ALLCONFIG is set to '{}', which " - "could not be opened: {}" - .format(allconfig, std_msg(e))) + sys.exit( + "error: KCONFIG_ALLCONFIG is set to '{}', which " + "could not be opened: {}".format(allconfig, std_msg(e)) + ) kconf.warn_assign_override = old_warn_assign_override kconf.warn_assign_redun = old_warn_assign_redun @@ -6332,8 +6558,11 @@ def _visibility(sc): vis = max(vis, expr_value(node.prompt[1])) if sc.__class__ is Symbol and sc.choice: - if sc.choice.orig_type is TRISTATE and \ - sc.orig_type is not TRISTATE and sc.choice.tri_value != 2: + if ( + sc.choice.orig_type is TRISTATE + and sc.orig_type is not TRISTATE + and sc.choice.tri_value != 2 + ): # Non-tristate choice symbols are only visible in y mode return 0 @@ -6407,8 +6636,11 @@ def _sym_to_num(sym): # For BOOL and TRISTATE, n/m/y count as 0/1/2. This mirrors 9059a3493ef # ("kconfig: fix relational operators for bool and tristate symbols") in # the C implementation. - return sym.tri_value if sym.orig_type in _BOOL_TRISTATE else \ - int(sym.str_value, _TYPE_TO_BASE[sym.orig_type]) + return ( + sym.tri_value + if sym.orig_type in _BOOL_TRISTATE + else int(sym.str_value, _TYPE_TO_BASE[sym.orig_type]) + ) def _touch_dep_file(path, sym_name): @@ -6421,8 +6653,7 @@ def _touch_dep_file(path, sym_name): os.makedirs(sym_path_dir, 0o755) # A kind of truncating touch, mirroring the C tools - os.close(os.open( - sym_path, os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0o644)) + os.close(os.open(sym_path, os.O_WRONLY | os.O_CREAT | os.O_TRUNC, 0o644)) def _save_old(path): @@ -6431,6 +6662,7 @@ def _save_old(path): def copy(src, dst): # Import as needed, to save some startup time import shutil + shutil.copyfile(src, dst) if islink(path): @@ -6463,8 +6695,8 @@ def _locs(sc): if sc.nodes: return "(defined at {})".format( - ", ".join("{0.filename}:{0.linenr}".format(node) - for node in sc.nodes)) + ", ".join("{0.filename}:{0.linenr}".format(node) for node in sc.nodes) + ) return "(undefined)" @@ -6491,13 +6723,13 @@ def _expr_depends_on(expr, sym): elif left is not sym: return False - return (expr[0] is EQUAL and right is sym.kconfig.m or - right is sym.kconfig.y) or \ - (expr[0] is UNEQUAL and right is sym.kconfig.n) + return ( + expr[0] is EQUAL and right is sym.kconfig.m or right is sym.kconfig.y + ) or (expr[0] is UNEQUAL and right is sym.kconfig.n) - return expr[0] is AND and \ - (_expr_depends_on(expr[1], sym) or - _expr_depends_on(expr[2], sym)) + return expr[0] is AND and ( + _expr_depends_on(expr[1], sym) or _expr_depends_on(expr[2], sym) + ) def _auto_menu_dep(node1, node2): @@ -6505,8 +6737,7 @@ def _auto_menu_dep(node1, node2): # node2 has a prompt, we check its condition. Otherwise, we look directly # at node2.dep. - return _expr_depends_on(node2.prompt[1] if node2.prompt else node2.dep, - node1.item) + return _expr_depends_on(node2.prompt[1] if node2.prompt else node2.dep, node1.item) def _flatten(node): @@ -6521,8 +6752,7 @@ def _flatten(node): # you enter the choice at some location with a prompt. while node: - if node.list and not node.prompt and \ - node.item.__class__ is not Choice: + if node.list and not node.prompt and node.item.__class__ is not Choice: last_node = node.list while 1: @@ -6637,9 +6867,11 @@ def _check_dep_loop_sym(sym, ignore_choice): # # Since we aren't entering the choice via a choice symbol, all # choice symbols need to be checked, hence the None. - loop = _check_dep_loop_choice(dep, None) \ - if dep.__class__ is Choice \ - else _check_dep_loop_sym(dep, False) + loop = ( + _check_dep_loop_choice(dep, None) + if dep.__class__ is Choice + else _check_dep_loop_sym(dep, False) + ) if loop: # Dependency loop found @@ -6711,8 +6943,7 @@ def _found_dep_loop(loop, cur): # Yep, we have the entire loop. Throw an exception that shows it. - msg = "\nDependency loop\n" \ - "===============\n\n" + msg = "\nDependency loop\n" "===============\n\n" for item in loop: if item is not loop[0]: @@ -6720,8 +6951,7 @@ def _found_dep_loop(loop, cur): if item.__class__ is Symbol and item.choice: msg += "the choice symbol " - msg += "{}, with definition...\n\n{}\n\n" \ - .format(item.name_and_loc, item) + msg += "{}, with definition...\n\n{}\n\n".format(item.name_and_loc, item) # Small wart: Since we reuse the already calculated # Symbol/Choice._dependents sets for recursive dependency detection, we @@ -6738,12 +6968,14 @@ def _found_dep_loop(loop, cur): if item.__class__ is Symbol: if item.rev_dep is not item.kconfig.n: - msg += "(select-related dependencies: {})\n\n" \ - .format(expr_str(item.rev_dep)) + msg += "(select-related dependencies: {})\n\n".format( + expr_str(item.rev_dep) + ) if item.weak_rev_dep is not item.kconfig.n: - msg += "(imply-related dependencies: {})\n\n" \ - .format(expr_str(item.rev_dep)) + msg += "(imply-related dependencies: {})\n\n".format( + expr_str(item.rev_dep) + ) msg += "...depends again on " + loop[0].name_and_loc @@ -6765,11 +6997,14 @@ def _decoding_error(e, filename, macro_linenr=None): "Problematic data: {}\n" "Reason: {}".format( e.encoding, - "'{}'".format(filename) if macro_linenr is None else - "output from macro at {}:{}".format(filename, macro_linenr), - e.object[max(e.start - 40, 0):e.end + 40], - e.object[e.start:e.end], - e.reason)) + "'{}'".format(filename) + if macro_linenr is None + else "output from macro at {}:{}".format(filename, macro_linenr), + e.object[max(e.start - 40, 0) : e.end + 40], + e.object[e.start : e.end], + e.reason, + ) + ) def _warn_verbose_deprecated(fn_name): @@ -6779,7 +7014,8 @@ def _warn_verbose_deprecated(fn_name): "and is always generated. Do e.g. print(kconf.{0}()) if you want to " "want to show a message like \"Loaded configuration '.config'\" on " "stdout. The old API required ugly hacks to reuse messages in " - "configuration interfaces.\n".format(fn_name)) + "configuration interfaces.\n".format(fn_name) + ) # Predefined preprocessor functions @@ -6808,8 +7044,7 @@ def _warning_if_fn(kconf, _, cond, msg): def _error_if_fn(kconf, _, cond, msg): if cond == "y": - raise KconfigError("{}:{}: {}".format( - kconf.filename, kconf.linenr, msg)) + raise KconfigError("{}:{}: {}".format(kconf.filename, kconf.linenr, msg)) return "" @@ -6829,9 +7064,11 @@ def _shell_fn(kconf, _, command): _decoding_error(e, kconf.filename, kconf.linenr) if stderr: - kconf._warn("'{}' wrote to stderr: {}".format( - command, "\n".join(stderr.splitlines())), - kconf.filename, kconf.linenr) + kconf._warn( + "'{}' wrote to stderr: {}".format(command, "\n".join(stderr.splitlines())), + kconf.filename, + kconf.linenr, + ) # Universal newlines with splitlines() (to prevent e.g. stray \r's in # command output on Windows), trailing newline removal, and @@ -6842,6 +7079,7 @@ def _shell_fn(kconf, _, command): # parameter was added in 3.6), so we do this manual version instead. return "\n".join(stdout.splitlines()).rstrip("\n").replace("\n", " ") + # # Global constants # @@ -6871,6 +7109,7 @@ try: except AttributeError: # Only import as needed, to save some startup time import platform + _UNAME_RELEASE = platform.uname()[2] # The token and type constants below are safe to test with 'is', which is a bit @@ -6940,112 +7179,112 @@ except AttributeError: # Keyword to token map, with the get() method assigned directly as a small # optimization _get_keyword = { - "---help---": _T_HELP, - "allnoconfig_y": _T_ALLNOCONFIG_Y, - "bool": _T_BOOL, - "boolean": _T_BOOL, - "choice": _T_CHOICE, - "comment": _T_COMMENT, - "config": _T_CONFIG, - "def_bool": _T_DEF_BOOL, - "def_hex": _T_DEF_HEX, - "def_int": _T_DEF_INT, - "def_string": _T_DEF_STRING, - "def_tristate": _T_DEF_TRISTATE, - "default": _T_DEFAULT, + "---help---": _T_HELP, + "allnoconfig_y": _T_ALLNOCONFIG_Y, + "bool": _T_BOOL, + "boolean": _T_BOOL, + "choice": _T_CHOICE, + "comment": _T_COMMENT, + "config": _T_CONFIG, + "def_bool": _T_DEF_BOOL, + "def_hex": _T_DEF_HEX, + "def_int": _T_DEF_INT, + "def_string": _T_DEF_STRING, + "def_tristate": _T_DEF_TRISTATE, + "default": _T_DEFAULT, "defconfig_list": _T_DEFCONFIG_LIST, - "depends": _T_DEPENDS, - "endchoice": _T_ENDCHOICE, - "endif": _T_ENDIF, - "endmenu": _T_ENDMENU, - "env": _T_ENV, - "grsource": _T_ORSOURCE, # Backwards compatibility - "gsource": _T_OSOURCE, # Backwards compatibility - "help": _T_HELP, - "hex": _T_HEX, - "if": _T_IF, - "imply": _T_IMPLY, - "int": _T_INT, - "mainmenu": _T_MAINMENU, - "menu": _T_MENU, - "menuconfig": _T_MENUCONFIG, - "modules": _T_MODULES, - "on": _T_ON, - "option": _T_OPTION, - "optional": _T_OPTIONAL, - "orsource": _T_ORSOURCE, - "osource": _T_OSOURCE, - "prompt": _T_PROMPT, - "range": _T_RANGE, - "rsource": _T_RSOURCE, - "select": _T_SELECT, - "source": _T_SOURCE, - "string": _T_STRING, - "tristate": _T_TRISTATE, - "visible": _T_VISIBLE, + "depends": _T_DEPENDS, + "endchoice": _T_ENDCHOICE, + "endif": _T_ENDIF, + "endmenu": _T_ENDMENU, + "env": _T_ENV, + "grsource": _T_ORSOURCE, # Backwards compatibility + "gsource": _T_OSOURCE, # Backwards compatibility + "help": _T_HELP, + "hex": _T_HEX, + "if": _T_IF, + "imply": _T_IMPLY, + "int": _T_INT, + "mainmenu": _T_MAINMENU, + "menu": _T_MENU, + "menuconfig": _T_MENUCONFIG, + "modules": _T_MODULES, + "on": _T_ON, + "option": _T_OPTION, + "optional": _T_OPTIONAL, + "orsource": _T_ORSOURCE, + "osource": _T_OSOURCE, + "prompt": _T_PROMPT, + "range": _T_RANGE, + "rsource": _T_RSOURCE, + "select": _T_SELECT, + "source": _T_SOURCE, + "string": _T_STRING, + "tristate": _T_TRISTATE, + "visible": _T_VISIBLE, }.get # The constants below match the value of the corresponding tokens to remove the # need for conversion # Node types -MENU = _T_MENU +MENU = _T_MENU COMMENT = _T_COMMENT # Expression types -AND = _T_AND -OR = _T_OR -NOT = _T_NOT -EQUAL = _T_EQUAL -UNEQUAL = _T_UNEQUAL -LESS = _T_LESS -LESS_EQUAL = _T_LESS_EQUAL -GREATER = _T_GREATER +AND = _T_AND +OR = _T_OR +NOT = _T_NOT +EQUAL = _T_EQUAL +UNEQUAL = _T_UNEQUAL +LESS = _T_LESS +LESS_EQUAL = _T_LESS_EQUAL +GREATER = _T_GREATER GREATER_EQUAL = _T_GREATER_EQUAL REL_TO_STR = { - EQUAL: "=", - UNEQUAL: "!=", - LESS: "<", - LESS_EQUAL: "<=", - GREATER: ">", + EQUAL: "=", + UNEQUAL: "!=", + LESS: "<", + LESS_EQUAL: "<=", + GREATER: ">", GREATER_EQUAL: ">=", } # Symbol/choice types. UNKNOWN is 0 (falsy) to simplify some checks. # Client code shouldn't rely on it though, as it was non-zero in # older versions. -UNKNOWN = 0 -BOOL = _T_BOOL +UNKNOWN = 0 +BOOL = _T_BOOL TRISTATE = _T_TRISTATE -STRING = _T_STRING -INT = _T_INT -HEX = _T_HEX +STRING = _T_STRING +INT = _T_INT +HEX = _T_HEX TYPE_TO_STR = { - UNKNOWN: "unknown", - BOOL: "bool", + UNKNOWN: "unknown", + BOOL: "bool", TRISTATE: "tristate", - STRING: "string", - INT: "int", - HEX: "hex", + STRING: "string", + INT: "int", + HEX: "hex", } # Used in comparisons. 0 means the base is inferred from the format of the # string. _TYPE_TO_BASE = { - HEX: 16, - INT: 10, - STRING: 0, - UNKNOWN: 0, + HEX: 16, + INT: 10, + STRING: 0, + UNKNOWN: 0, } # def_bool -> BOOL, etc. _DEF_TOKEN_TO_TYPE = { - _T_DEF_BOOL: BOOL, - _T_DEF_HEX: HEX, - _T_DEF_INT: INT, - _T_DEF_STRING: STRING, + _T_DEF_BOOL: BOOL, + _T_DEF_HEX: HEX, + _T_DEF_INT: INT, + _T_DEF_STRING: STRING, _T_DEF_TRISTATE: TRISTATE, } @@ -7056,91 +7295,115 @@ _DEF_TOKEN_TO_TYPE = { # Identifier-like lexemes ("missing quotes") are also treated as strings after # these tokens. _T_CHOICE is included to avoid symbols being registered for # named choices. -_STRING_LEX = frozenset({ - _T_BOOL, - _T_CHOICE, - _T_COMMENT, - _T_HEX, - _T_INT, - _T_MAINMENU, - _T_MENU, - _T_ORSOURCE, - _T_OSOURCE, - _T_PROMPT, - _T_RSOURCE, - _T_SOURCE, - _T_STRING, - _T_TRISTATE, -}) +_STRING_LEX = frozenset( + { + _T_BOOL, + _T_CHOICE, + _T_COMMENT, + _T_HEX, + _T_INT, + _T_MAINMENU, + _T_MENU, + _T_ORSOURCE, + _T_OSOURCE, + _T_PROMPT, + _T_RSOURCE, + _T_SOURCE, + _T_STRING, + _T_TRISTATE, + } +) # Various sets for quick membership tests. Gives a single global lookup and # avoids creating temporary dicts/tuples. -_TYPE_TOKENS = frozenset({ - _T_BOOL, - _T_TRISTATE, - _T_INT, - _T_HEX, - _T_STRING, -}) - -_SOURCE_TOKENS = frozenset({ - _T_SOURCE, - _T_RSOURCE, - _T_OSOURCE, - _T_ORSOURCE, -}) - -_REL_SOURCE_TOKENS = frozenset({ - _T_RSOURCE, - _T_ORSOURCE, -}) +_TYPE_TOKENS = frozenset( + { + _T_BOOL, + _T_TRISTATE, + _T_INT, + _T_HEX, + _T_STRING, + } +) + +_SOURCE_TOKENS = frozenset( + { + _T_SOURCE, + _T_RSOURCE, + _T_OSOURCE, + _T_ORSOURCE, + } +) + +_REL_SOURCE_TOKENS = frozenset( + { + _T_RSOURCE, + _T_ORSOURCE, + } +) # Obligatory (non-optional) sources -_OBL_SOURCE_TOKENS = frozenset({ - _T_SOURCE, - _T_RSOURCE, -}) - -_BOOL_TRISTATE = frozenset({ - BOOL, - TRISTATE, -}) - -_BOOL_TRISTATE_UNKNOWN = frozenset({ - BOOL, - TRISTATE, - UNKNOWN, -}) - -_INT_HEX = frozenset({ - INT, - HEX, -}) - -_SYMBOL_CHOICE = frozenset({ - Symbol, - Choice, -}) - -_MENU_COMMENT = frozenset({ - MENU, - COMMENT, -}) - -_EQUAL_UNEQUAL = frozenset({ - EQUAL, - UNEQUAL, -}) - -_RELATIONS = frozenset({ - EQUAL, - UNEQUAL, - LESS, - LESS_EQUAL, - GREATER, - GREATER_EQUAL, -}) +_OBL_SOURCE_TOKENS = frozenset( + { + _T_SOURCE, + _T_RSOURCE, + } +) + +_BOOL_TRISTATE = frozenset( + { + BOOL, + TRISTATE, + } +) + +_BOOL_TRISTATE_UNKNOWN = frozenset( + { + BOOL, + TRISTATE, + UNKNOWN, + } +) + +_INT_HEX = frozenset( + { + INT, + HEX, + } +) + +_SYMBOL_CHOICE = frozenset( + { + Symbol, + Choice, + } +) + +_MENU_COMMENT = frozenset( + { + MENU, + COMMENT, + } +) + +_EQUAL_UNEQUAL = frozenset( + { + EQUAL, + UNEQUAL, + } +) + +_RELATIONS = frozenset( + { + EQUAL, + UNEQUAL, + LESS, + LESS_EQUAL, + GREATER, + GREATER_EQUAL, + } +) # Helper functions for getting compiled regular expressions, with the needed # matching function returned directly as a small optimization. @@ -7189,7 +7452,7 @@ _string_special_search = _re_search(r'"|\'|\\|\$\(') # Special characters/strings while expanding a symbol name. Also includes # end-of-line, in case the macro is the last thing on the line. -_name_special_search = _re_search(r'[^A-Za-z0-9_$/.-]|\$\(|$') +_name_special_search = _re_search(r"[^A-Za-z0-9_$/.-]|\$\(|$") # A valid right-hand side for an assignment to a string symbol in a .config # file, including escaped characters. Extracts the contents. diff --git a/util/run_ects.py b/util/run_ects.py index 9178328e5f..9293f60779 100644 --- a/util/run_ects.py +++ b/util/run_ects.py @@ -16,81 +16,81 @@ import subprocess import sys # List of tests to run. -TESTS = ['meta', 'gpio', 'hook', 'i2c', 'interrupt', 'mutex', 'task', 'timer'] +TESTS = ["meta", "gpio", "hook", "i2c", "interrupt", "mutex", "task", "timer"] class CtsRunner(object): - """Class running eCTS tests.""" - - def __init__(self, ec_dir, dryrun): - self.ec_dir = ec_dir - self.cts_py = [] - if dryrun: - self.cts_py += ['echo'] - self.cts_py += [os.path.join(ec_dir, 'cts/cts.py')] - - def run_cmd(self, cmd): - try: - rc = subprocess.call(cmd) - if rc != 0: - return False - except OSError: - return False - return True - - def run_test(self, test): - cmd = self.cts_py + ['-m', test] - self.run_cmd(cmd) - - def run(self, tests): - for test in tests: - logging.info('Running', test, 'test.') - self.run_test(test) - - def sync(self): - logging.info('Syncing tree...') - os.chdir(self.ec_dir) - cmd = ['repo', 'sync', '.'] - return self.run_cmd(cmd) - - def upload(self): - logging.info('Uploading results...') + """Class running eCTS tests.""" + + def __init__(self, ec_dir, dryrun): + self.ec_dir = ec_dir + self.cts_py = [] + if dryrun: + self.cts_py += ["echo"] + self.cts_py += [os.path.join(ec_dir, "cts/cts.py")] + + def run_cmd(self, cmd): + try: + rc = subprocess.call(cmd) + if rc != 0: + return False + except OSError: + return False + return True + + def run_test(self, test): + cmd = self.cts_py + ["-m", test] + self.run_cmd(cmd) + + def run(self, tests): + for test in tests: + logging.info("Running", test, "test.") + self.run_test(test) + + def sync(self): + logging.info("Syncing tree...") + os.chdir(self.ec_dir) + cmd = ["repo", "sync", "."] + return self.run_cmd(cmd) + + def upload(self): + logging.info("Uploading results...") def main(): - if not os.path.exists('/etc/cros_chroot_version'): - logging.error('This script has to run inside chroot.') - sys.exit(-1) - - ec_dir = os.path.realpath(os.path.dirname(__file__) + '/..') - - parser = argparse.ArgumentParser(description='Run eCTS and report results.') - parser.add_argument('-d', - '--dryrun', - action='store_true', - help='Echo commands to be executed without running them.') - parser.add_argument('-s', - '--sync', - action='store_true', - help='Sync tree before running tests.') - parser.add_argument('-u', - '--upload', - action='store_true', - help='Upload test results.') - args = parser.parse_args() - - runner = CtsRunner(ec_dir, args.dryrun) - - if args.sync: - if not runner.sync(): - logging.error('Failed to sync.') - sys.exit(-1) - - runner.run(TESTS) - - if args.upload: - runner.upload() - - -if __name__ == '__main__': - main() + if not os.path.exists("/etc/cros_chroot_version"): + logging.error("This script has to run inside chroot.") + sys.exit(-1) + + ec_dir = os.path.realpath(os.path.dirname(__file__) + "/..") + + parser = argparse.ArgumentParser(description="Run eCTS and report results.") + parser.add_argument( + "-d", + "--dryrun", + action="store_true", + help="Echo commands to be executed without running them.", + ) + parser.add_argument( + "-s", "--sync", action="store_true", help="Sync tree before running tests." + ) + parser.add_argument( + "-u", "--upload", action="store_true", help="Upload test results." + ) + args = parser.parse_args() + + runner = CtsRunner(ec_dir, args.dryrun) + + if args.sync: + if not runner.sync(): + logging.error("Failed to sync.") + sys.exit(-1) + + runner.run(TESTS) + + if args.upload: + runner.upload() + + +if __name__ == "__main__": + main() diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py index cd1b9bf098..db73e7ee71 100644 --- a/util/test_kconfig_check.py +++ b/util/test_kconfig_check.py @@ -16,7 +16,8 @@ import kconfig_check # Prefix that we strip from each Kconfig option, when considering whether it is # equivalent to a CONFIG option with the same name -PREFIX = 'PLATFORM_EC_' +PREFIX = "PLATFORM_EC_" + @contextlib.contextmanager def capture_sys_output(): @@ -39,38 +40,49 @@ def capture_sys_output(): # directly from Python. You can still run this test with 'pytest' if you like. class KconfigCheck(unittest.TestCase): """Tests for the KconfigCheck class""" + def test_simple_check(self): """Check it detected a new ad-hoc CONFIG""" checker = kconfig_check.KconfigCheck() - self.assertEqual(['NEW_ONE'], checker.find_new_adhoc( - configs=['NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'], - kconfigs=['IN_KCONFIG'], - allowed=['OLD_ONE'])) + self.assertEqual( + ["NEW_ONE"], + checker.find_new_adhoc( + configs=["NEW_ONE", "OLD_ONE", "IN_KCONFIG"], + kconfigs=["IN_KCONFIG"], + allowed=["OLD_ONE"], + ), + ) def test_sorted_check(self): """Check it sorts the results in order""" checker = kconfig_check.KconfigCheck() self.assertSequenceEqual( - ['ANOTHER_NEW_ONE', 'NEW_ONE'], + ["ANOTHER_NEW_ONE", "NEW_ONE"], checker.find_new_adhoc( - configs=['NEW_ONE', 'ANOTHER_NEW_ONE', 'OLD_ONE', 'IN_KCONFIG'], - kconfigs=['IN_KCONFIG'], - allowed=['OLD_ONE'])) + configs=["NEW_ONE", "ANOTHER_NEW_ONE", "OLD_ONE", "IN_KCONFIG"], + kconfigs=["IN_KCONFIG"], + allowed=["OLD_ONE"], + ), + ) def check_read_configs(self, use_defines): checker = kconfig_check.KconfigCheck() with tempfile.NamedTemporaryFile() as configs: - with open(configs.name, 'w') as out: - prefix = '#define ' if use_defines else '' - suffix = ' ' if use_defines else '=' - out.write(f'''{prefix}CONFIG_OLD_ONE{suffix}y + with open(configs.name, "w") as out: + prefix = "#define " if use_defines else "" + suffix = " " if use_defines else "=" + out.write( + f"""{prefix}CONFIG_OLD_ONE{suffix}y {prefix}NOT_A_CONFIG{suffix} {prefix}CONFIG_STRING{suffix}"something" {prefix}CONFIG_INT{suffix}123 {prefix}CONFIG_HEX{suffix}45ab -''') - self.assertEqual(['OLD_ONE', 'STRING', 'INT', 'HEX'], - checker.read_configs(configs.name, use_defines)) +""" + ) + self.assertEqual( + ["OLD_ONE", "STRING", "INT", "HEX"], + checker.read_configs(configs.name, use_defines), + ) def test_read_configs(self): """Test KconfigCheck.read_configs()""" @@ -87,22 +99,24 @@ class KconfigCheck(unittest.TestCase): Args: srctree: Directory to write to """ - with open(os.path.join(srctree, 'Kconfig'), 'w') as out: - out.write(f'''config {PREFIX}MY_KCONFIG + with open(os.path.join(srctree, "Kconfig"), "w") as out: + out.write( + f"""config {PREFIX}MY_KCONFIG \tbool "my kconfig" rsource "subdir/Kconfig.wibble" -''') - subdir = os.path.join(srctree, 'subdir') +""" + ) + subdir = os.path.join(srctree, "subdir") os.mkdir(subdir) - with open(os.path.join(subdir, 'Kconfig.wibble'), 'w') as out: - out.write('menuconfig %sMENU_KCONFIG\n' % PREFIX) + with open(os.path.join(subdir, "Kconfig.wibble"), "w") as out: + out.write("menuconfig %sMENU_KCONFIG\n" % PREFIX) # Add a directory which should be ignored - bad_subdir = os.path.join(subdir, 'Kconfig') + bad_subdir = os.path.join(subdir, "Kconfig") os.mkdir(bad_subdir) - with open(os.path.join(bad_subdir, 'Kconfig.bad'), 'w') as out: - out.write('menuconfig %sBAD_KCONFIG' % PREFIX) + with open(os.path.join(bad_subdir, "Kconfig.bad"), "w") as out: + out.write("menuconfig %sBAD_KCONFIG" % PREFIX) def test_find_kconfigs(self): """Test KconfigCheck.find_kconfigs()""" @@ -110,20 +124,20 @@ rsource "subdir/Kconfig.wibble" with tempfile.TemporaryDirectory() as srctree: self.setup_srctree(srctree) files = checker.find_kconfigs(srctree) - fnames = [fname[len(srctree):] for fname in files] - self.assertEqual(['/Kconfig', '/subdir/Kconfig.wibble'], fnames) + fnames = [fname[len(srctree) :] for fname in files] + self.assertEqual(["/Kconfig", "/subdir/Kconfig.wibble"], fnames) def test_scan_kconfigs(self): """Test KconfigCheck.scan_configs()""" checker = kconfig_check.KconfigCheck() with tempfile.TemporaryDirectory() as srctree: self.setup_srctree(srctree) - self.assertEqual(['MENU_KCONFIG', 'MY_KCONFIG'], - checker.scan_kconfigs(srctree, PREFIX)) + self.assertEqual( + ["MENU_KCONFIG", "MY_KCONFIG"], checker.scan_kconfigs(srctree, PREFIX) + ) @classmethod - def setup_allowed_and_configs(cls, allowed_fname, configs_fname, - add_new_one=True): + def setup_allowed_and_configs(cls, allowed_fname, configs_fname, add_new_one=True): """Set up the 'allowed' and 'configs' files for tests Args: @@ -131,14 +145,14 @@ rsource "subdir/Kconfig.wibble" configs_fname: Filename to which CONFIGs to check should be written add_new_one: True to add CONFIG_NEW_ONE to the configs_fname file """ - with open(allowed_fname, 'w') as out: - out.write('CONFIG_OLD_ONE\n') - out.write('CONFIG_MENU_KCONFIG\n') - with open(configs_fname, 'w') as out: - to_add = ['CONFIG_OLD_ONE', 'CONFIG_MY_KCONFIG'] + with open(allowed_fname, "w") as out: + out.write("CONFIG_OLD_ONE\n") + out.write("CONFIG_MENU_KCONFIG\n") + with open(configs_fname, "w") as out: + to_add = ["CONFIG_OLD_ONE", "CONFIG_MY_KCONFIG"] if add_new_one: - to_add.append('CONFIG_NEW_ONE') - out.write('\n'.join(to_add)) + to_add.append("CONFIG_NEW_ONE") + out.write("\n".join(to_add)) def test_check_adhoc_configs(self): """Test KconfigCheck.check_adhoc_configs()""" @@ -148,12 +162,16 @@ rsource "subdir/Kconfig.wibble" with tempfile.NamedTemporaryFile() as allowed: with tempfile.NamedTemporaryFile() as configs: self.setup_allowed_and_configs(allowed.name, configs.name) - new_adhoc, unneeded_adhoc, updated_adhoc = ( - checker.check_adhoc_configs( - configs.name, srctree, allowed.name, PREFIX)) - self.assertEqual(['NEW_ONE'], new_adhoc) - self.assertEqual(['MENU_KCONFIG'], unneeded_adhoc) - self.assertEqual(['OLD_ONE'], updated_adhoc) + ( + new_adhoc, + unneeded_adhoc, + updated_adhoc, + ) = checker.check_adhoc_configs( + configs.name, srctree, allowed.name, PREFIX + ) + self.assertEqual(["NEW_ONE"], new_adhoc) + self.assertEqual(["MENU_KCONFIG"], unneeded_adhoc) + self.assertEqual(["OLD_ONE"], updated_adhoc) def test_check(self): """Test running the 'check' subcommand""" @@ -162,29 +180,39 @@ rsource "subdir/Kconfig.wibble" self.setup_srctree(srctree) with tempfile.NamedTemporaryFile() as allowed: with tempfile.NamedTemporaryFile() as configs: - self.setup_allowed_and_configs(allowed.name, - configs.name) + self.setup_allowed_and_configs(allowed.name, configs.name) ret_code = kconfig_check.main( - ['-c', configs.name, '-s', srctree, - '-a', allowed.name, '-p', PREFIX, 'check']) + [ + "-c", + configs.name, + "-s", + srctree, + "-a", + allowed.name, + "-p", + PREFIX, + "check", + ] + ) self.assertEqual(1, ret_code) - self.assertEqual('', stdout.getvalue()) - found = re.findall('(CONFIG_.*)', stderr.getvalue()) - self.assertEqual(['CONFIG_NEW_ONE'], found) + self.assertEqual("", stdout.getvalue()) + found = re.findall("(CONFIG_.*)", stderr.getvalue()) + self.assertEqual(["CONFIG_NEW_ONE"], found) def test_real_kconfig(self): """Same Kconfig should be returned for kconfiglib / adhoc""" if not kconfig_check.USE_KCONFIGLIB: - self.skipTest('No kconfiglib available') - zephyr_path = pathlib.Path('../../third_party/zephyr/main').resolve() + self.skipTest("No kconfiglib available") + zephyr_path = pathlib.Path("../../third_party/zephyr/main").resolve() if not zephyr_path.exists(): - self.skipTest('No zephyr tree available') + self.skipTest("No zephyr tree available") checker = kconfig_check.KconfigCheck() - srcdir = 'zephyr' + srcdir = "zephyr" search_paths = [zephyr_path] kc_version = checker.scan_kconfigs( - srcdir, search_paths=search_paths, try_kconfiglib=True) + srcdir, search_paths=search_paths, try_kconfiglib=True + ) adhoc_version = checker.scan_kconfigs(srcdir, try_kconfiglib=False) # List of things missing from the Kconfig @@ -192,15 +220,17 @@ rsource "subdir/Kconfig.wibble" # The Kconfig is disjoint in some places, e.g. the boards have their # own Kconfig files which are not included from the main Kconfig - missing = [item for item in missing - if not item.startswith('BOARD') and - not item.startswith('VARIANT')] + missing = [ + item + for item in missing + if not item.startswith("BOARD") and not item.startswith("VARIANT") + ] # Similarly, some other items are defined in files that are not included # in all cases, only for particular values of $(ARCH) self.assertEqual( - ['FLASH_LOAD_OFFSET', 'NPCX_HEADER', 'SYS_CLOCK_HW_CYCLES_PER_SEC'], - missing) + ["FLASH_LOAD_OFFSET", "NPCX_HEADER", "SYS_CLOCK_HW_CYCLES_PER_SEC"], missing + ) def test_check_unneeded(self): """Test running the 'check' subcommand with unneeded ad-hoc configs""" @@ -209,18 +239,29 @@ rsource "subdir/Kconfig.wibble" self.setup_srctree(srctree) with tempfile.NamedTemporaryFile() as allowed: with tempfile.NamedTemporaryFile() as configs: - self.setup_allowed_and_configs(allowed.name, - configs.name, False) + self.setup_allowed_and_configs( + allowed.name, configs.name, False + ) ret_code = kconfig_check.main( - ['-c', configs.name, '-s', srctree, - '-a', allowed.name, '-p', PREFIX, 'check']) + [ + "-c", + configs.name, + "-s", + srctree, + "-a", + allowed.name, + "-p", + PREFIX, + "check", + ] + ) self.assertEqual(1, ret_code) - self.assertEqual('', stderr.getvalue()) - found = re.findall('(CONFIG_.*)', stdout.getvalue()) - self.assertEqual(['CONFIG_MENU_KCONFIG'], found) + self.assertEqual("", stderr.getvalue()) + found = re.findall("(CONFIG_.*)", stdout.getvalue()) + self.assertEqual(["CONFIG_MENU_KCONFIG"], found) allowed = kconfig_check.NEW_ALLOWED_FNAME.read_text().splitlines() - self.assertEqual(['CONFIG_OLD_ONE'], allowed) + self.assertEqual(["CONFIG_OLD_ONE"], allowed) -if __name__ == '__main__': +if __name__ == "__main__": unittest.main() diff --git a/util/uart_stress_tester.py b/util/uart_stress_tester.py index b3db60060e..a89fe730c9 100755 --- a/util/uart_stress_tester.py +++ b/util/uart_stress_tester.py @@ -21,9 +21,7 @@ Prerequisite: e.g. dut-control cr50_uart_timestamp:off """ -from __future__ import absolute_import -from __future__ import division -from __future__ import print_function +from __future__ import absolute_import, division, print_function import argparse import atexit @@ -36,472 +34,501 @@ import time import serial -BAUDRATE = 115200 # Default baudrate setting for UART port -CROS_USERNAME = 'root' # Account name to login to ChromeOS -CROS_PASSWORD = 'test0000' # Password to login to ChromeOS -CHARGEN_TXT = '0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz' - # The result of 'chargen 62 62' +BAUDRATE = 115200 # Default baudrate setting for UART port +CROS_USERNAME = "root" # Account name to login to ChromeOS +CROS_PASSWORD = "test0000" # Password to login to ChromeOS +CHARGEN_TXT = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz" +# The result of 'chargen 62 62' CHARGEN_TXT_LEN = len(CHARGEN_TXT) -CR = '\r' # Carriage Return -LF = '\n' # Line Feed +CR = "\r" # Carriage Return +LF = "\n" # Line Feed CRLF = CR + LF -FLAG_FILENAME = '/tmp/chargen_testing' -TPM_CMD = ('trunks_client --key_create --rsa=2048 --usage=sign' - ' --key_blob=/tmp/blob &> /dev/null') - # A ChromeOS TPM command for the cr50 stress - # purpose. -CR50_LOAD_GEN_CMD = ('while [[ -f %s ]]; do %s; done &' - % (FLAG_FILENAME, TPM_CMD)) - # A command line to run TPM_CMD in background - # infinitely. +FLAG_FILENAME = "/tmp/chargen_testing" +TPM_CMD = ( + "trunks_client --key_create --rsa=2048 --usage=sign" + " --key_blob=/tmp/blob &> /dev/null" +) +# A ChromeOS TPM command for the cr50 stress +# purpose. +CR50_LOAD_GEN_CMD = "while [[ -f %s ]]; do %s; done &" % (FLAG_FILENAME, TPM_CMD) +# A command line to run TPM_CMD in background +# infinitely. class ChargenTestError(Exception): - """Exception for Uart Stress Test Error""" - pass + """Exception for Uart Stress Test Error""" + pass -class UartSerial(object): - """Test Object for a single UART serial device - - Attributes: - UART_DEV_PROFILES - char_loss_occurrences: Number that character loss happens - cleanup_cli: Command list to perform before the test exits - cr50_workload: True if cr50 should be stressed, or False otherwise - usb_output: True if output should be generated to USB channel - dev_prof: Dictionary of device profile - duration: Time to keep chargen running - eol: Characters to add at the end of input - logger: object that store the log - num_ch_exp: Expected number of characters in output - num_ch_cap: Number of captured characters in output - test_cli: Command list to run for chargen test - test_thread: Thread object that captures the UART output - serial: serial.Serial object - """ - UART_DEV_PROFILES = ( - # Kernel - { - 'prompt':'localhost login:', - 'device_type':'AP', - 'prepare_cmd':[ - CROS_USERNAME, # Login - CROS_PASSWORD, # Password - 'dmesg -D', # Disable console message - 'touch ' + FLAG_FILENAME, # Create a temp file - ], - 'cleanup_cmd':[ - 'rm -f ' + FLAG_FILENAME, # Remove the temp file - 'dmesg -E', # Enable console message - 'logout', # Logout - ], - 'end_of_input':LF, - }, - # EC - { - 'prompt':'> ', - 'device_type':'EC', - 'prepare_cmd':[ - 'chan save', - 'chan 0' # Disable console message - ], - 'cleanup_cmd':['', 'chan restore'], - 'end_of_input':CRLF, - }, - ) - - def __init__(self, port, duration, timeout=1, - baudrate=BAUDRATE, cr50_workload=False, - usb_output=False): - """Initialize UartSerial - - Args: - port: UART device path. e.g. /dev/ttyUSB0 - duration: Time to test, in seconds - timeout: Read timeout value. - baudrate: Baud rate such as 9600 or 115200. - cr50_workload: True if a workload should be generated on cr50 - usb_output: True if a workload should be generated to USB channel - """ - - # Initialize serial object - self.serial = serial.Serial() - self.serial.port = port - self.serial.timeout = timeout - self.serial.baudrate = baudrate - - self.duration = duration - self.cr50_workload = cr50_workload - self.usb_output = usb_output - - self.logger = logging.getLogger(type(self).__name__ + '| ' + port) - self.test_thread = threading.Thread(target=self.stress_test_thread) - self.dev_prof = {} - self.cleanup_cli = [] - self.test_cli = [] - self.eol = CRLF - self.num_ch_exp = 0 - self.num_ch_cap = 0 - self.char_loss_occurrences = 0 - atexit.register(self.cleanup) - - def run_command(self, command_lines, delay=0): - """Run command(s) at UART prompt - - Args: - command_lines: list of commands to run. - delay: delay after a command in second +class UartSerial(object): + """Test Object for a single UART serial device + + Attributes: + UART_DEV_PROFILES + char_loss_occurrences: Number that character loss happens + cleanup_cli: Command list to perform before the test exits + cr50_workload: True if cr50 should be stressed, or False otherwise + usb_output: True if output should be generated to USB channel + dev_prof: Dictionary of device profile + duration: Time to keep chargen running + eol: Characters to add at the end of input + logger: object that store the log + num_ch_exp: Expected number of characters in output + num_ch_cap: Number of captured characters in output + test_cli: Command list to run for chargen test + test_thread: Thread object that captures the UART output + serial: serial.Serial object """ - for cli in command_lines: - self.logger.debug('run %r', cli) - - self.serial.write((cli + self.eol).encode()) - self.serial.flush() - if delay: - time.sleep(delay) - - def cleanup(self): - """Before termination, clean up the UART device.""" - self.logger.debug('Closing...') - - self.serial.open() - self.run_command(self.cleanup_cli) # Run cleanup commands - self.serial.close() - self.logger.debug('Cleanup done') + UART_DEV_PROFILES = ( + # Kernel + { + "prompt": "localhost login:", + "device_type": "AP", + "prepare_cmd": [ + CROS_USERNAME, # Login + CROS_PASSWORD, # Password + "dmesg -D", # Disable console message + "touch " + FLAG_FILENAME, # Create a temp file + ], + "cleanup_cmd": [ + "rm -f " + FLAG_FILENAME, # Remove the temp file + "dmesg -E", # Enable console message + "logout", # Logout + ], + "end_of_input": LF, + }, + # EC + { + "prompt": "> ", + "device_type": "EC", + "prepare_cmd": ["chan save", "chan 0"], # Disable console message + "cleanup_cmd": ["", "chan restore"], + "end_of_input": CRLF, + }, + ) + + def __init__( + self, + port, + duration, + timeout=1, + baudrate=BAUDRATE, + cr50_workload=False, + usb_output=False, + ): + """Initialize UartSerial + + Args: + port: UART device path. e.g. /dev/ttyUSB0 + duration: Time to test, in seconds + timeout: Read timeout value. + baudrate: Baud rate such as 9600 or 115200. + cr50_workload: True if a workload should be generated on cr50 + usb_output: True if a workload should be generated to USB channel + """ + + # Initialize serial object + self.serial = serial.Serial() + self.serial.port = port + self.serial.timeout = timeout + self.serial.baudrate = baudrate + + self.duration = duration + self.cr50_workload = cr50_workload + self.usb_output = usb_output + + self.logger = logging.getLogger(type(self).__name__ + "| " + port) + self.test_thread = threading.Thread(target=self.stress_test_thread) + + self.dev_prof = {} + self.cleanup_cli = [] + self.test_cli = [] + self.eol = CRLF + self.num_ch_exp = 0 + self.num_ch_cap = 0 + self.char_loss_occurrences = 0 + atexit.register(self.cleanup) + + def run_command(self, command_lines, delay=0): + """Run command(s) at UART prompt + + Args: + command_lines: list of commands to run. + delay: delay after a command in second + """ + for cli in command_lines: + self.logger.debug("run %r", cli) + + self.serial.write((cli + self.eol).encode()) + self.serial.flush() + if delay: + time.sleep(delay) + + def cleanup(self): + """Before termination, clean up the UART device.""" + self.logger.debug("Closing...") + + self.serial.open() + self.run_command(self.cleanup_cli) # Run cleanup commands + self.serial.close() + + self.logger.debug("Cleanup done") + + def get_output(self): + """Capture the UART output + + Args: + stop_char: Read output buffer until it reads stop_char. + + Returns: + text from UART output. + """ + if self.serial.inWaiting() == 0: + time.sleep(1) + + return self.serial.read(self.serial.inWaiting()).decode() + + def prepare(self): + """Prepare the test: + + Identify the type of UART device (EC or Kernel?), then + decide what kind of commands to use to generate stress loads. + + Raises: + ChargenTestError if UART source can't be identified. + """ + try: + self.logger.info("Preparing...") + + self.serial.open() + + # Prepare the device for test + self.serial.flushInput() + self.serial.flushOutput() + + self.get_output() # drain data + + # Give a couple of line feeds, and capture the prompt text + self.run_command(["", ""]) + prompt_txt = self.get_output() + + # Detect the device source: EC or AP? + # Detect if the device is AP or EC console based on the captured. + for dev_prof in self.UART_DEV_PROFILES: + if dev_prof["prompt"] in prompt_txt: + self.dev_prof = dev_prof + break + else: + # No prompt patterns were found. UART seems not responding or in + # an undesirable status. + if prompt_txt: + raise ChargenTestError( + "%s: Got an unknown prompt text: %s\n" + "Check manually whether %s is available." + % (self.serial.port, prompt_txt, self.serial.port) + ) + else: + raise ChargenTestError( + "%s: Got no input. Close any other connections" + " to this port, and try it again." % self.serial.port + ) + + self.logger.info("Detected as %s UART", self.dev_prof["device_type"]) + # Log displays the UART type (AP|EC) instead of device filename. + self.logger = logging.getLogger( + type(self).__name__ + "| " + self.dev_prof["device_type"] + ) + + # Either login to AP or run some commands to prepare the device + # for test + self.eol = self.dev_prof["end_of_input"] + self.run_command(self.dev_prof["prepare_cmd"], delay=2) + self.cleanup_cli += self.dev_prof["cleanup_cmd"] + + # 'chargen' of AP does not have option for USB output. + # Force it work on UART. + if self.dev_prof["device_type"] == "AP": + self.usb_output = False + + # Check whether the command 'chargen' is available in the device. + # 'chargen 1 4' is supposed to print '0000' + self.get_output() # drain data + + chargen_cmd = "chargen 1 4" + if self.usb_output: + chargen_cmd += " usb" + self.run_command([chargen_cmd]) + tmp_txt = self.get_output() + + # Check whether chargen command is available. + if "0000" not in tmp_txt: + raise ChargenTestError( + "%s: Chargen got an unexpected result: %s" + % (self.dev_prof["device_type"], tmp_txt) + ) + + self.num_ch_exp = int(self.serial.baudrate * self.duration / 10) + chargen_cmd = "chargen " + str(CHARGEN_TXT_LEN) + " " + str(self.num_ch_exp) + if self.usb_output: + chargen_cmd += " usb" + self.test_cli = [chargen_cmd] + + self.logger.info("Ready to test") + finally: + self.serial.close() + + def stress_test_thread(self): + """Test thread + + Raises: + ChargenTestError: if broken character is found. + """ + try: + self.serial.open() + self.serial.flushInput() + self.serial.flushOutput() + + # Run TPM command in background to burden cr50. + if self.dev_prof["device_type"] == "AP" and self.cr50_workload: + self.run_command([CR50_LOAD_GEN_CMD]) + self.logger.debug("run TPM job while %s exists", FLAG_FILENAME) + + # Run the command 'chargen', one time + self.run_command([""]) # Give a line feed + self.get_output() # Drain the output + self.run_command(self.test_cli) + self.serial.readline() # Drain the echoed command line. + + err_msg = "%s: Expected %r but got %s after %d char received" + + # Keep capturing the output until the test timer is expired. + self.num_ch_cap = 0 + self.char_loss_occurrences = 0 + data_starve_count = 0 + + total_num_ch = self.num_ch_exp # Expected number of characters in total + ch_exp = CHARGEN_TXT[0] + ch_cap = "z" # any character value is ok for loop initial condition. + while self.num_ch_cap < total_num_ch: + captured = self.get_output() + + if captured: + # There is some output data. Reset the data starvation count. + data_starve_count = 0 + else: + data_starve_count += 1 + if data_starve_count > 1: + # If nothing was captured more than once, then terminate the test. + self.logger.debug("No more output") + break + + for ch_cap in captured: + if ch_cap not in CHARGEN_TXT: + # If it is not alpha-numeric, terminate the test. + if ch_cap not in CRLF: + # If it is neither a CR nor LF, then it is an error case. + self.logger.error("Whole captured characters: %r", captured) + raise ChargenTestError( + err_msg + % ( + "Broken char captured", + ch_exp, + hex(ord(ch_cap)), + self.num_ch_cap, + ) + ) + + # Set the loop termination condition true. + total_num_ch = self.num_ch_cap + + if self.num_ch_cap >= total_num_ch: + break + + if ch_exp != ch_cap: + # If it is alpha-numeric but not continuous, then some characters + # are lost. + self.logger.error( + err_msg, + "Char loss detected", + ch_exp, + repr(ch_cap), + self.num_ch_cap, + ) + self.char_loss_occurrences += 1 + + # Recalculate the expected number of characters to adjust + # termination condition. The loss might be bigger than this + # adjustment, but it is okay since it will terminates by either + # CR/LF detection or by data starvation. + idx_ch_exp = CHARGEN_TXT.find(ch_exp) + idx_ch_cap = CHARGEN_TXT.find(ch_cap) + if idx_ch_cap < idx_ch_exp: + idx_ch_cap += len(CHARGEN_TXT) + total_num_ch -= idx_ch_cap - idx_ch_exp + + self.num_ch_cap += 1 + + # Determine What character is expected next? + ch_exp = CHARGEN_TXT[ + (CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN + ] + + finally: + self.serial.close() + + def start_test(self): + """Start the test thread""" + self.logger.info("Test thread starts") + self.test_thread.start() + + def wait_test_done(self): + """Wait until the test thread get done and join""" + self.test_thread.join() + self.logger.info("Test thread is done") + + def get_result(self): + """Display the result + + Returns: + Integer = the number of lost character + + Raises: + ChargenTestError: if the capture is corrupted. + """ + # If more characters than expected are captured, it means some messages + # from other than chargen are mixed. Stop processing further. + if self.num_ch_exp < self.num_ch_cap: + raise ChargenTestError( + "%s: UART output is corrupted." % self.dev_prof["device_type"] + ) + + # Get the count difference between the expected to the captured + # as the number of lost character. + char_lost = self.num_ch_exp - self.num_ch_cap + self.logger.info( + "%8d char lost / %10d (%.1f %%)", + char_lost, + self.num_ch_exp, + char_lost * 100.0 / self.num_ch_exp, + ) + + return char_lost, self.num_ch_exp, self.char_loss_occurrences - def get_output(self): - """Capture the UART output - Args: - stop_char: Read output buffer until it reads stop_char. +class ChargenTest(object): + """UART stress tester - Returns: - text from UART output. + Attributes: + logger: logging object + serials: Dictionary where key is filename of UART device, and the value is + UartSerial object """ - if self.serial.inWaiting() == 0: - time.sleep(1) - - return self.serial.read(self.serial.inWaiting()).decode() - def prepare(self): - """Prepare the test: - - Identify the type of UART device (EC or Kernel?), then - decide what kind of commands to use to generate stress loads. - - Raises: - ChargenTestError if UART source can't be identified. - """ - try: - self.logger.info('Preparing...') - - self.serial.open() - - # Prepare the device for test - self.serial.flushInput() - self.serial.flushOutput() - - self.get_output() # drain data - - # Give a couple of line feeds, and capture the prompt text - self.run_command(['', '']) - prompt_txt = self.get_output() - - # Detect the device source: EC or AP? - # Detect if the device is AP or EC console based on the captured. - for dev_prof in self.UART_DEV_PROFILES: - if dev_prof['prompt'] in prompt_txt: - self.dev_prof = dev_prof - break - else: - # No prompt patterns were found. UART seems not responding or in - # an undesirable status. - if prompt_txt: - raise ChargenTestError('%s: Got an unknown prompt text: %s\n' - 'Check manually whether %s is available.' % - (self.serial.port, prompt_txt, - self.serial.port)) - else: - raise ChargenTestError('%s: Got no input. Close any other connections' - ' to this port, and try it again.' % - self.serial.port) - - self.logger.info('Detected as %s UART', self.dev_prof['device_type']) - # Log displays the UART type (AP|EC) instead of device filename. - self.logger = logging.getLogger(type(self).__name__ + '| ' + - self.dev_prof['device_type']) - - # Either login to AP or run some commands to prepare the device - # for test - self.eol = self.dev_prof['end_of_input'] - self.run_command(self.dev_prof['prepare_cmd'], delay=2) - self.cleanup_cli += self.dev_prof['cleanup_cmd'] - - # 'chargen' of AP does not have option for USB output. - # Force it work on UART. - if self.dev_prof['device_type'] == 'AP': - self.usb_output = False - - # Check whether the command 'chargen' is available in the device. - # 'chargen 1 4' is supposed to print '0000' - self.get_output() # drain data - - chargen_cmd = 'chargen 1 4' - if self.usb_output: - chargen_cmd += ' usb' - self.run_command([chargen_cmd]) - tmp_txt = self.get_output() - - # Check whether chargen command is available. - if '0000' not in tmp_txt: - raise ChargenTestError('%s: Chargen got an unexpected result: %s' % - (self.dev_prof['device_type'], tmp_txt)) - - self.num_ch_exp = int(self.serial.baudrate * self.duration / 10) - chargen_cmd = 'chargen ' + str(CHARGEN_TXT_LEN) + ' ' + \ - str(self.num_ch_exp) - if self.usb_output: - chargen_cmd += ' usb' - self.test_cli = [chargen_cmd] - - self.logger.info('Ready to test') - finally: - self.serial.close() - - def stress_test_thread(self): - """Test thread - - Raises: - ChargenTestError: if broken character is found. - """ - try: - self.serial.open() - self.serial.flushInput() - self.serial.flushOutput() - - # Run TPM command in background to burden cr50. - if self.dev_prof['device_type'] == 'AP' and self.cr50_workload: - self.run_command([CR50_LOAD_GEN_CMD]) - self.logger.debug('run TPM job while %s exists', FLAG_FILENAME) - - # Run the command 'chargen', one time - self.run_command(['']) # Give a line feed - self.get_output() # Drain the output - self.run_command(self.test_cli) - self.serial.readline() # Drain the echoed command line. - - err_msg = '%s: Expected %r but got %s after %d char received' - - # Keep capturing the output until the test timer is expired. - self.num_ch_cap = 0 - self.char_loss_occurrences = 0 - data_starve_count = 0 - - total_num_ch = self.num_ch_exp # Expected number of characters in total - ch_exp = CHARGEN_TXT[0] - ch_cap = 'z' # any character value is ok for loop initial condition. - while self.num_ch_cap < total_num_ch: - captured = self.get_output() - - if captured: - # There is some output data. Reset the data starvation count. - data_starve_count = 0 + def __init__(self, ports, duration, cr50_workload=False, usb_output=False): + """Initialize UART stress tester + + Args: + ports: List of UART ports to test. + duration: Time to keep testing in seconds. + cr50_workload: True if a workload should be generated on cr50 + usb_output: True if a workload should be generated to USB channel + + Raises: + ChargenTestError: if any of ports is not a valid character device. + """ + + # Save the arguments + for port in ports: + try: + mode = os.stat(port).st_mode + except OSError as e: + raise ChargenTestError(e) + if not stat.S_ISCHR(mode): + raise ChargenTestError("%s is not a character device." % port) + + if duration <= 0: + raise ChargenTestError("Input error: duration is not positive.") + + # Initialize logging object + self.logger = logging.getLogger(type(self).__name__) + + # Create an UartSerial object per UART port + self.serials = {} # UartSerial objects + for port in ports: + self.serials[port] = UartSerial( + port=port, + duration=duration, + cr50_workload=cr50_workload, + usb_output=usb_output, + ) + + def prepare(self): + """Prepare the test for each UART port""" + self.logger.info("Prepare ports for test") + for _, ser in self.serials.items(): + ser.prepare() + self.logger.info("Ports are ready to test") + + def print_result(self): + """Display the test result for each UART port + + Returns: + char_lost: Total number of characters lost + """ + char_lost = 0 + for _, ser in self.serials.items(): + (tmp_lost, _, _) = ser.get_result() + char_lost += tmp_lost + + # If any characters are lost, then test fails. + msg = "lost %d character(s) from the test" % char_lost + if char_lost > 0: + self.logger.error("FAIL: %s", msg) else: - data_starve_count += 1 - if data_starve_count > 1: - # If nothing was captured more than once, then terminate the test. - self.logger.debug('No more output') - break - - for ch_cap in captured: - if ch_cap not in CHARGEN_TXT: - # If it is not alpha-numeric, terminate the test. - if ch_cap not in CRLF: - # If it is neither a CR nor LF, then it is an error case. - self.logger.error('Whole captured characters: %r', captured) - raise ChargenTestError(err_msg % ('Broken char captured', ch_exp, - hex(ord(ch_cap)), - self.num_ch_cap)) - - # Set the loop termination condition true. - total_num_ch = self.num_ch_cap - - if self.num_ch_cap >= total_num_ch: - break - - if ch_exp != ch_cap: - # If it is alpha-numeric but not continuous, then some characters - # are lost. - self.logger.error(err_msg, 'Char loss detected', - ch_exp, repr(ch_cap), self.num_ch_cap) - self.char_loss_occurrences += 1 - - # Recalculate the expected number of characters to adjust - # termination condition. The loss might be bigger than this - # adjustment, but it is okay since it will terminates by either - # CR/LF detection or by data starvation. - idx_ch_exp = CHARGEN_TXT.find(ch_exp) - idx_ch_cap = CHARGEN_TXT.find(ch_cap) - if idx_ch_cap < idx_ch_exp: - idx_ch_cap += len(CHARGEN_TXT) - total_num_ch -= (idx_ch_cap - idx_ch_exp) - - self.num_ch_cap += 1 - - # Determine What character is expected next? - ch_exp = CHARGEN_TXT[(CHARGEN_TXT.find(ch_cap) + 1) % CHARGEN_TXT_LEN] - - finally: - self.serial.close() - - def start_test(self): - """Start the test thread""" - self.logger.info('Test thread starts') - self.test_thread.start() - - def wait_test_done(self): - """Wait until the test thread get done and join""" - self.test_thread.join() - self.logger.info('Test thread is done') - - def get_result(self): - """Display the result + self.logger.info("PASS: %s", msg) - Returns: - Integer = the number of lost character + return char_lost - Raises: - ChargenTestError: if the capture is corrupted. - """ - # If more characters than expected are captured, it means some messages - # from other than chargen are mixed. Stop processing further. - if self.num_ch_exp < self.num_ch_cap: - raise ChargenTestError('%s: UART output is corrupted.' % - self.dev_prof['device_type']) + def run(self): + """Run the stress test on UART port(s) - # Get the count difference between the expected to the captured - # as the number of lost character. - char_lost = self.num_ch_exp - self.num_ch_cap - self.logger.info('%8d char lost / %10d (%.1f %%)', - char_lost, self.num_ch_exp, - char_lost * 100.0 / self.num_ch_exp) + Raises: + ChargenTestError: If any characters are lost. + """ - return char_lost, self.num_ch_exp, self.char_loss_occurrences + # Detect UART source type, and decide which command to test. + self.prepare() + # Run the test on each UART port in thread. + self.logger.info("Test starts") + for _, ser in self.serials.items(): + ser.start_test() -class ChargenTest(object): - """UART stress tester + # Wait all tests to finish. + for _, ser in self.serials.items(): + ser.wait_test_done() - Attributes: - logger: logging object - serials: Dictionary where key is filename of UART device, and the value is - UartSerial object - """ + # Print the result. + char_lost = self.print_result() + if char_lost: + raise ChargenTestError("Test failed: lost %d character(s)" % char_lost) - def __init__(self, ports, duration, cr50_workload=False, - usb_output=False): - """Initialize UART stress tester + self.logger.info("Test is done") - Args: - ports: List of UART ports to test. - duration: Time to keep testing in seconds. - cr50_workload: True if a workload should be generated on cr50 - usb_output: True if a workload should be generated to USB channel - Raises: - ChargenTestError: if any of ports is not a valid character device. - """ +def parse_args(cmdline): + """Parse command line arguments. - # Save the arguments - for port in ports: - try: - mode = os.stat(port).st_mode - except OSError as e: - raise ChargenTestError(e) - if not stat.S_ISCHR(mode): - raise ChargenTestError('%s is not a character device.' % port) - - if duration <= 0: - raise ChargenTestError('Input error: duration is not positive.') - - # Initialize logging object - self.logger = logging.getLogger(type(self).__name__) - - # Create an UartSerial object per UART port - self.serials = {} # UartSerial objects - for port in ports: - self.serials[port] = UartSerial(port=port, duration=duration, - cr50_workload=cr50_workload, - usb_output=usb_output) - - def prepare(self): - """Prepare the test for each UART port""" - self.logger.info('Prepare ports for test') - for _, ser in self.serials.items(): - ser.prepare() - self.logger.info('Ports are ready to test') - - def print_result(self): - """Display the test result for each UART port + Args: + cmdline: list to be parsed Returns: - char_lost: Total number of characters lost - """ - char_lost = 0 - for _, ser in self.serials.items(): - (tmp_lost, _, _) = ser.get_result() - char_lost += tmp_lost - - # If any characters are lost, then test fails. - msg = 'lost %d character(s) from the test' % char_lost - if char_lost > 0: - self.logger.error('FAIL: %s', msg) - else: - self.logger.info('PASS: %s', msg) - - return char_lost - - def run(self): - """Run the stress test on UART port(s) - - Raises: - ChargenTestError: If any characters are lost. + tuple (options, args) where args is a list of cmdline arguments that the + parser was unable to match i.e. they're servod controls, not options. """ - - # Detect UART source type, and decide which command to test. - self.prepare() - - # Run the test on each UART port in thread. - self.logger.info('Test starts') - for _, ser in self.serials.items(): - ser.start_test() - - # Wait all tests to finish. - for _, ser in self.serials.items(): - ser.wait_test_done() - - # Print the result. - char_lost = self.print_result() - if char_lost: - raise ChargenTestError('Test failed: lost %d character(s)' % - char_lost) - - self.logger.info('Test is done') - -def parse_args(cmdline): - """Parse command line arguments. - - Args: - cmdline: list to be parsed - - Returns: - tuple (options, args) where args is a list of cmdline arguments that the - parser was unable to match i.e. they're servod controls, not options. - """ - description = """%(prog)s repeats sending a uart console command + description = """%(prog)s repeats sending a uart console command to each UART device for a given time, and check if output has any missing characters. @@ -511,52 +538,70 @@ Examples: %(prog)s /dev/ttyUSB1 /dev/ttyUSB2 --cr50 """ - parser = argparse.ArgumentParser(description=description, - formatter_class=argparse.RawTextHelpFormatter - ) - parser.add_argument('port', type=str, nargs='*', - help='UART device path to test') - parser.add_argument('-c', '--cr50', action='store_true', default=False, - help='generate TPM workload on cr50') - parser.add_argument('-d', '--debug', action='store_true', default=False, - help='enable debug messages') - parser.add_argument('-t', '--time', type=int, - help='Test duration in second', default=300) - parser.add_argument('-u', '--usb', action='store_true', default=False, - help='Generate output to USB channel instead') - return parser.parse_known_args(cmdline) + parser = argparse.ArgumentParser( + description=description, formatter_class=argparse.RawTextHelpFormatter + ) + parser.add_argument("port", type=str, nargs="*", help="UART device path to test") + parser.add_argument( + "-c", + "--cr50", + action="store_true", + default=False, + help="generate TPM workload on cr50", + ) + parser.add_argument( + "-d", + "--debug", + action="store_true", + default=False, + help="enable debug messages", + ) + parser.add_argument( + "-t", "--time", type=int, help="Test duration in second", default=300 + ) + parser.add_argument( + "-u", + "--usb", + action="store_true", + default=False, + help="Generate output to USB channel instead", + ) + return parser.parse_known_args(cmdline) def main(): - """Main function wrapper""" - try: - (options, _) = parse_args(sys.argv[1:]) - - # Set Log format - log_format = '%(asctime)s %(levelname)-6s | %(name)-25s' - date_format = '%Y-%m-%d %H:%M:%S' - if options.debug: - log_format += ' | %(filename)s:%(lineno)4d:%(funcName)-18s' - loglevel = logging.DEBUG - else: - loglevel = logging.INFO - log_format += ' | %(message)s' - - logging.basicConfig(level=loglevel, format=log_format, - datefmt=date_format) - - # Create a ChargenTest object - utest = ChargenTest(options.port, options.time, - cr50_workload=options.cr50, - usb_output=options.usb) - utest.run() # Run - - except KeyboardInterrupt: - sys.exit(0) - - except ChargenTestError as e: - logging.error(str(e)) - sys.exit(1) - -if __name__ == '__main__': - main() + """Main function wrapper""" + try: + (options, _) = parse_args(sys.argv[1:]) + + # Set Log format + log_format = "%(asctime)s %(levelname)-6s | %(name)-25s" + date_format = "%Y-%m-%d %H:%M:%S" + if options.debug: + log_format += " | %(filename)s:%(lineno)4d:%(funcName)-18s" + loglevel = logging.DEBUG + else: + loglevel = logging.INFO + log_format += " | %(message)s" + + logging.basicConfig(level=loglevel, format=log_format, datefmt=date_format) + + # Create a ChargenTest object + utest = ChargenTest( + options.port, + options.time, + cr50_workload=options.cr50, + usb_output=options.usb, + ) + utest.run() # Run + + except KeyboardInterrupt: + sys.exit(0) + + except ChargenTestError as e: + logging.error(str(e)) + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/util/unpack_ftb.py b/util/unpack_ftb.py index 03127a7089..a68662d82b 100755 --- a/util/unpack_ftb.py +++ b/util/unpack_ftb.py @@ -10,26 +10,28 @@ # Note: This is a py2/3 compatible file. from __future__ import print_function + import argparse import ctypes import os class Header(ctypes.Structure): - _pack_ = 1 - _fields_ = [ - ('signature', ctypes.c_uint32), - ('ftb_ver', ctypes.c_uint32), - ('chip_id', ctypes.c_uint32), - ('svn_ver', ctypes.c_uint32), - ('fw_ver', ctypes.c_uint32), - ('config_id', ctypes.c_uint32), - ('config_ver', ctypes.c_uint32), - ('reserved', ctypes.c_uint8 * 8), - ('release_info', ctypes.c_ulonglong), - ('sec_size', ctypes.c_uint32 * 4), - ('crc', ctypes.c_uint32), - ] + _pack_ = 1 + _fields_ = [ + ("signature", ctypes.c_uint32), + ("ftb_ver", ctypes.c_uint32), + ("chip_id", ctypes.c_uint32), + ("svn_ver", ctypes.c_uint32), + ("fw_ver", ctypes.c_uint32), + ("config_id", ctypes.c_uint32), + ("config_ver", ctypes.c_uint32), + ("reserved", ctypes.c_uint8 * 8), + ("release_info", ctypes.c_ulonglong), + ("sec_size", ctypes.c_uint32 * 4), + ("crc", ctypes.c_uint32), + ] + FW_HEADER_SIZE = 64 FW_HEADER_SIGNATURE = 0xAA55AA55 @@ -44,7 +46,7 @@ FLASH_SEC_ADDR = [ 0x0000 * 4, # CODE 0x7C00 * 4, # CONFIG 0x7000 * 4, # CX - None # This section shouldn't exist + None, # This section shouldn't exist ] UPDATE_PDU_SIZE = 4096 @@ -59,64 +61,66 @@ OUTPUT_FILE_SIZE = UPDATE_PDU_SIZE + 128 * 1024 def main(): - parser = argparse.ArgumentParser() - parser.add_argument('--input', '-i', required=True) - parser.add_argument('--output', '-o', required=True) - args = parser.parse_args() + parser = argparse.ArgumentParser() + parser.add_argument("--input", "-i", required=True) + parser.add_argument("--output", "-o", required=True) + args = parser.parse_args() - with open(args.input, 'rb') as f: - bs = f.read() + with open(args.input, "rb") as f: + bs = f.read() - size = len(bs) - if size < FW_HEADER_SIZE + FW_BYTES_ALIGN: - raise Exception('FW size too small') + size = len(bs) + if size < FW_HEADER_SIZE + FW_BYTES_ALIGN: + raise Exception("FW size too small") - print('FTB file size:', size) + print("FTB file size:", size) - header = Header() - assert ctypes.sizeof(header) == FW_HEADER_SIZE + header = Header() + assert ctypes.sizeof(header) == FW_HEADER_SIZE - ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header)) - if (header.signature != FW_HEADER_SIGNATURE or - header.ftb_ver != FW_FTB_VER or - header.chip_id != FW_CHIP_ID): - raise Exception('Invalid header') + ctypes.memmove(ctypes.addressof(header), bs, ctypes.sizeof(header)) + if ( + header.signature != FW_HEADER_SIGNATURE + or header.ftb_ver != FW_FTB_VER + or header.chip_id != FW_CHIP_ID + ): + raise Exception("Invalid header") - for key, _ in header._fields_: - v = getattr(header, key) - if isinstance(v, ctypes.Array): - print(key, list(map(hex, v))) - else: - print(key, hex(v)) + for key, _ in header._fields_: + v = getattr(header, key) + if isinstance(v, ctypes.Array): + print(key, list(map(hex, v))) + else: + print(key, hex(v)) - dimension = sum(header.sec_size) + dimension = sum(header.sec_size) - assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size - data = bs[FW_HEADER_SIZE:FW_HEADER_SIZE + dimension] + assert dimension + FW_HEADER_SIZE + FW_BYTES_ALIGN == size + data = bs[FW_HEADER_SIZE : FW_HEADER_SIZE + dimension] - with open(args.output, 'wb') as f: - # ensure the file size - f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET) - f.write(b'\x00') + with open(args.output, "wb") as f: + # ensure the file size + f.seek(OUTPUT_FILE_SIZE - 1, os.SEEK_SET) + f.write(b"\x00") - f.seek(0, os.SEEK_SET) - f.write(bs[0 : ctypes.sizeof(header)]) + f.seek(0, os.SEEK_SET) + f.write(bs[0 : ctypes.sizeof(header)]) - offset = 0 - # write each sections - for i, addr in enumerate(FLASH_SEC_ADDR): - size = header.sec_size[i] - assert addr is not None or size == 0 + offset = 0 + # write each sections + for i, addr in enumerate(FLASH_SEC_ADDR): + size = header.sec_size[i] + assert addr is not None or size == 0 - if size == 0: - continue + if size == 0: + continue - f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET) - f.write(data[offset : offset + size]) - offset += size + f.seek(UPDATE_PDU_SIZE + addr, os.SEEK_SET) + f.write(data[offset : offset + size]) + offset += size - f.flush() + f.flush() -if __name__ == '__main__': - main() +if __name__ == "__main__": + main() diff --git a/util/update_release_branch.py b/util/update_release_branch.py index b9063d4970..4d9c89df4a 100755 --- a/util/update_release_branch.py +++ b/util/update_release_branch.py @@ -19,8 +19,7 @@ import subprocess import sys import textwrap - -BUG_NONE_PATTERN = re.compile('none', flags=re.IGNORECASE) +BUG_NONE_PATTERN = re.compile("none", flags=re.IGNORECASE) def git_commit_msg(branch, head, merge_head, rel_paths, cmd): @@ -42,18 +41,17 @@ def git_commit_msg(branch, head, merge_head, rel_paths, cmd): A String containing the git commit message with the exception of the Signed-Off-By field and Change-ID field. """ - relevant_commits_cmd, relevant_commits = get_relevant_commits(head, - merge_head, - '--oneline', - rel_paths) + relevant_commits_cmd, relevant_commits = get_relevant_commits( + head, merge_head, "--oneline", rel_paths + ) - _, relevant_bugs = get_relevant_commits(head, merge_head, '', rel_paths) - relevant_bugs = set(re.findall('BUG=(.*)', relevant_bugs)) + _, relevant_bugs = get_relevant_commits(head, merge_head, "", rel_paths) + relevant_bugs = set(re.findall("BUG=(.*)", relevant_bugs)) # Filter out "none" from set of bugs filtered = [] for bug_line in relevant_bugs: - bug_line = bug_line.replace(',', ' ') - bugs = bug_line.split(' ') + bug_line = bug_line.replace(",", " ") + bugs = bug_line.split(" ") for bug in bugs: if bug and not BUG_NONE_PATTERN.match(bug): filtered.append(bug) @@ -82,18 +80,20 @@ Cq-Include-Trybots: chromeos/cq:cq-orchestrator # 72 cols. relevant_commits_cmd = textwrap.fill(relevant_commits_cmd, width=72) # Wrap at 68 cols to save room for 'BUG=' - bugs = textwrap.wrap(' '.join(relevant_bugs), width=68) - bug_field = '' + bugs = textwrap.wrap(" ".join(relevant_bugs), width=68) + bug_field = "" for line in bugs: - bug_field += 'BUG=' + line + '\n' + bug_field += "BUG=" + line + "\n" # Remove the final newline since the template adds it for us. bug_field = bug_field[:-1] - return COMMIT_MSG_TEMPLATE.format(BRANCH=branch, - RELEVANT_COMMITS_CMD=relevant_commits_cmd, - RELEVANT_COMMITS=relevant_commits, - BUG_FIELD=bug_field, - COMMAND_LINE=cmd) + return COMMIT_MSG_TEMPLATE.format( + BRANCH=branch, + RELEVANT_COMMITS_CMD=relevant_commits_cmd, + RELEVANT_COMMITS=relevant_commits, + BUG_FIELD=bug_field, + COMMAND_LINE=cmd, + ) def get_relevant_boards(baseboard): @@ -105,15 +105,16 @@ def get_relevant_boards(baseboard): Returns: A list of strings containing the boards based off of the baseboard. """ - proc = subprocess.run(['git', 'grep', 'BASEBOARD:=' + baseboard, '--', - 'board/'], - stdout=subprocess.PIPE, - encoding='utf-8', - check=True) + proc = subprocess.run( + ["git", "grep", "BASEBOARD:=" + baseboard, "--", "board/"], + stdout=subprocess.PIPE, + encoding="utf-8", + check=True, + ) boards = [] res = proc.stdout.splitlines() for line in res: - boards.append(line.split('/')[1]) + boards.append(line.split("/")[1]) return boards @@ -135,21 +136,18 @@ def get_relevant_commits(head, merge_head, fmt, relevant_paths): stdout. """ if fmt: - cmd = ['git', 'log', fmt, head + '..' + merge_head, '--', - relevant_paths] + cmd = ["git", "log", fmt, head + ".." + merge_head, "--", relevant_paths] else: - cmd = ['git', 'log', head + '..' + merge_head, '--', relevant_paths] + cmd = ["git", "log", head + ".." + merge_head, "--", relevant_paths] # Pass cmd as a string to subprocess.run() since we need to run with shell # equal to True. The reason we are using shell equal to True is to take # advantage of the glob expansion for the relevant paths. - cmd = ' '.join(cmd) - proc = subprocess.run(cmd, - stdout=subprocess.PIPE, - encoding='utf-8', - check=True, - shell=True) - return ''.join(proc.args), proc.stdout + cmd = " ".join(cmd) + proc = subprocess.run( + cmd, stdout=subprocess.PIPE, encoding="utf-8", check=True, shell=True + ) + return "".join(proc.args), proc.stdout def main(argv): @@ -165,46 +163,61 @@ def main(argv): argv: A list of the command line arguments passed to this script. """ # Set up argument parser. - parser = argparse.ArgumentParser(description=('A script that generates a ' - 'merge commit from cros/main' - ' to a desired release ' - 'branch. By default, the ' - '"recursive" merge strategy ' - 'with the "theirs" strategy ' - 'option is used.')) - parser.add_argument('--baseboard') - parser.add_argument('--board') - parser.add_argument('release_branch', help=('The name of the target release' - ' branch')) - parser.add_argument('--relevant_paths_file', - help=('A path to a text file which includes other ' - 'relevant paths of interest for this board ' - 'or baseboard')) - parser.add_argument('--merge_strategy', '-s', default='recursive', - help='The merge strategy to pass to `git merge -s`') - parser.add_argument('--strategy_option', '-X', - help=('The strategy option for the chosen merge ' - 'strategy')) + parser = argparse.ArgumentParser( + description=( + "A script that generates a " + "merge commit from cros/main" + " to a desired release " + "branch. By default, the " + '"recursive" merge strategy ' + 'with the "theirs" strategy ' + "option is used." + ) + ) + parser.add_argument("--baseboard") + parser.add_argument("--board") + parser.add_argument( + "release_branch", help=("The name of the target release" " branch") + ) + parser.add_argument( + "--relevant_paths_file", + help=( + "A path to a text file which includes other " + "relevant paths of interest for this board " + "or baseboard" + ), + ) + parser.add_argument( + "--merge_strategy", + "-s", + default="recursive", + help="The merge strategy to pass to `git merge -s`", + ) + parser.add_argument( + "--strategy_option", + "-X", + help=("The strategy option for the chosen merge " "strategy"), + ) opts = parser.parse_args(argv[1:]) - baseboard_dir = '' - board_dir = '' + baseboard_dir = "" + board_dir = "" if opts.baseboard: # Dereference symlinks so "git log" works as expected. - baseboard_dir = os.path.relpath('baseboard/' + opts.baseboard) + baseboard_dir = os.path.relpath("baseboard/" + opts.baseboard) baseboard_dir = os.path.relpath(os.path.realpath(baseboard_dir)) boards = get_relevant_boards(opts.baseboard) elif opts.board: - board_dir = os.path.relpath('board/' + opts.board) + board_dir = os.path.relpath("board/" + opts.board) board_dir = os.path.relpath(os.path.realpath(board_dir)) boards = [opts.board] else: - parser.error('You must specify a board OR a baseboard') + parser.error("You must specify a board OR a baseboard") - print('Gathering relevant paths...') + print("Gathering relevant paths...") relevant_paths = [] if opts.baseboard: relevant_paths.append(baseboard_dir) @@ -212,65 +225,91 @@ def main(argv): relevant_paths.append(board_dir) for board in boards: - relevant_paths.append('board/' + board) + relevant_paths.append("board/" + board) # Check for the existence of a file that has other paths of interest. if opts.relevant_paths_file and os.path.exists(opts.relevant_paths_file): - with open(opts.relevant_paths_file, 'r') as relevant_paths_file: + with open(opts.relevant_paths_file, "r") as relevant_paths_file: for line in relevant_paths_file: - if not line.startswith('#'): + if not line.startswith("#"): relevant_paths.append(line.rstrip()) - relevant_paths.append('util/getversion.sh') - relevant_paths = ' '.join(relevant_paths) + relevant_paths.append("util/getversion.sh") + relevant_paths = " ".join(relevant_paths) # Check if we are already in merge process - result = subprocess.run(['git', 'rev-parse', '--quiet', '--verify', - 'MERGE_HEAD'], stdout=subprocess.DEVNULL, - stderr=subprocess.DEVNULL, check=False) + result = subprocess.run( + ["git", "rev-parse", "--quiet", "--verify", "MERGE_HEAD"], + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL, + check=False, + ) if result.returncode: # Let's perform the merge - print('Updating remote...') - subprocess.run(['git', 'remote', 'update'], check=True) - subprocess.run(['git', 'checkout', '-B', opts.release_branch, 'cros/' + - opts.release_branch], check=True) - print('Attempting git merge...') - if opts.merge_strategy == 'recursive' and not opts.strategy_option: - opts.strategy_option = 'theirs' - print('Using "%s" merge strategy' % opts.merge_strategy, - ("with strategy option '%s'" % opts.strategy_option - if opts.strategy_option else '')) - arglist = ['git', 'merge', '--no-ff', '--no-commit', 'cros/main', '-s', - opts.merge_strategy] + print("Updating remote...") + subprocess.run(["git", "remote", "update"], check=True) + subprocess.run( + [ + "git", + "checkout", + "-B", + opts.release_branch, + "cros/" + opts.release_branch, + ], + check=True, + ) + print("Attempting git merge...") + if opts.merge_strategy == "recursive" and not opts.strategy_option: + opts.strategy_option = "theirs" + print( + 'Using "%s" merge strategy' % opts.merge_strategy, + ( + "with strategy option '%s'" % opts.strategy_option + if opts.strategy_option + else "" + ), + ) + arglist = [ + "git", + "merge", + "--no-ff", + "--no-commit", + "cros/main", + "-s", + opts.merge_strategy, + ] if opts.strategy_option: - arglist.append('-X' + opts.strategy_option) + arglist.append("-X" + opts.strategy_option) subprocess.run(arglist, check=True) else: - print('We have already started merge process.', - 'Attempt to generate commit.') - - print('Generating commit message...') - branch = subprocess.run(['git', 'rev-parse', '--abbrev-ref', 'HEAD'], - stdout=subprocess.PIPE, - encoding='utf-8', - check=True).stdout.rstrip() - head = subprocess.run(['git', 'rev-parse', '--short', 'HEAD'], - stdout=subprocess.PIPE, - encoding='utf-8', - check=True).stdout.rstrip() - merge_head = subprocess.run(['git', 'rev-parse', '--short', - 'MERGE_HEAD'], - stdout=subprocess.PIPE, - encoding='utf-8', - check=True).stdout.rstrip() - - cmd = ' '.join(argv) - print('Typing as fast as I can...') + print("We have already started merge process.", "Attempt to generate commit.") + + print("Generating commit message...") + branch = subprocess.run( + ["git", "rev-parse", "--abbrev-ref", "HEAD"], + stdout=subprocess.PIPE, + encoding="utf-8", + check=True, + ).stdout.rstrip() + head = subprocess.run( + ["git", "rev-parse", "--short", "HEAD"], + stdout=subprocess.PIPE, + encoding="utf-8", + check=True, + ).stdout.rstrip() + merge_head = subprocess.run( + ["git", "rev-parse", "--short", "MERGE_HEAD"], + stdout=subprocess.PIPE, + encoding="utf-8", + check=True, + ).stdout.rstrip() + + cmd = " ".join(argv) + print("Typing as fast as I can...") commit_msg = git_commit_msg(branch, head, merge_head, relevant_paths, cmd) - subprocess.run(['git', 'commit', '--signoff', '-m', commit_msg], check=True) - subprocess.run(['git', 'commit', '--amend'], check=True) - print(("Finished! **Please review the commit to see if it's to your " - 'liking.**')) + subprocess.run(["git", "commit", "--signoff", "-m", commit_msg], check=True) + subprocess.run(["git", "commit", "--amend"], check=True) + print(("Finished! **Please review the commit to see if it's to your " "liking.**")) -if __name__ == '__main__': +if __name__ == "__main__": main(sys.argv) diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index f77e51d6c4..c0963a84db 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -15,14 +15,12 @@ import re import subprocess import sys -from google.protobuf import json_format # pylint: disable=import-error import zmake.project - from chromite.api.gen_sdk.chromite.api import firmware_pb2 +from google.protobuf import json_format # pylint: disable=import-error - -DEFAULT_BUNDLE_DIRECTORY = '/tmp/artifact_bundles' -DEFAULT_BUNDLE_METADATA_FILE = '/tmp/artifact_bundle_metadata' +DEFAULT_BUNDLE_DIRECTORY = "/tmp/artifact_bundles" +DEFAULT_BUNDLE_METADATA_FILE = "/tmp/artifact_bundle_metadata" def build(opts): @@ -33,54 +31,52 @@ def build(opts): platform_ec = zephyr_dir.resolve().parent subprocess.run([platform_ec / "util" / "check_clang_format.py"], check=True) - cmd = ['zmake', '-D', 'build', '-a'] + cmd = ["zmake", "-D", "build", "-a"] if opts.code_coverage: - cmd.append('--coverage') + cmd.append("--coverage") subprocess.run(cmd, cwd=pathlib.Path(__file__).parent, check=True) if not opts.code_coverage: for project in zmake.project.find_projects(zephyr_dir).values(): if project.config.is_test: continue - build_dir = ( - platform_ec / 'build' / 'zephyr' / project.config.project_name - ) + build_dir = platform_ec / "build" / "zephyr" / project.config.project_name metric = metric_list.value.add() metric.target_name = project.config.project_name metric.platform_name = project.config.zephyr_board for (variant, _) in project.iter_builds(): - build_log = build_dir / f'build-{variant}' / 'build.log' + build_log = build_dir / f"build-{variant}" / "build.log" parse_buildlog(build_log, metric, variant.upper()) - with open(opts.metrics, 'w') as file: + with open(opts.metrics, "w") as file: file.write(json_format.MessageToJson(metric_list)) return 0 UNITS = { - 'B': 1, - 'KB': 1024, - 'MB': 1024 * 1024, - 'GB': 1024 * 1024 * 1024, + "B": 1, + "KB": 1024, + "MB": 1024 * 1024, + "GB": 1024 * 1024 * 1024, } def parse_buildlog(filename, metric, variant): """Parse the build.log generated by zmake to find the size of the image.""" - with open(filename, 'r') as infile: + with open(filename, "r") as infile: # Skip over all lines until the memory report is found while True: line = infile.readline() if not line: return - if line.startswith('Memory region'): + if line.startswith("Memory region"): break for line in infile.readlines(): # Skip any lines that are not part of the report - if not line.startswith(' '): + if not line.startswith(" "): continue parts = line.split() fw_section = metric.fw_section.add() - fw_section.region = variant + '_' + parts[0][:-1] + fw_section.region = variant + "_" + parts[0][:-1] fw_section.used = int(parts[1]) * UNITS[parts[2]] fw_section.total = int(parts[3]) * UNITS[parts[4]] fw_section.track_on_gerrit = False @@ -114,7 +110,7 @@ def write_metadata(opts, info): bundle_metadata_file = ( opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE ) - with open(bundle_metadata_file, 'w') as file: + with open(bundle_metadata_file, "w") as file: file.write(json_format.MessageToJson(info)) @@ -125,10 +121,10 @@ def bundle_coverage(opts): bundle_dir = get_bundle_dir(opts) zephyr_dir = pathlib.Path(__file__).parent platform_ec = zephyr_dir.resolve().parent - build_dir = platform_ec / 'build' / 'zephyr' - tarball_name = 'coverage.tbz2' + build_dir = platform_ec / "build" / "zephyr" + tarball_name = "coverage.tbz2" tarball_path = bundle_dir / tarball_name - cmd = ['tar', 'cvfj', tarball_path, 'lcov.info'] + cmd = ["tar", "cvfj", tarball_path, "lcov.info"] subprocess.run(cmd, cwd=build_dir, check=True) meta = info.objects.add() meta.file_name = tarball_name @@ -149,13 +145,11 @@ def bundle_firmware(opts): for project in zmake.project.find_projects(zephyr_dir).values(): if project.config.is_test: continue - build_dir = ( - platform_ec / 'build' / 'zephyr' / project.config.project_name - ) - artifacts_dir = build_dir / 'output' - tarball_name = f'{project.config.project_name}.firmware.tbz2' + build_dir = platform_ec / "build" / "zephyr" / project.config.project_name + artifacts_dir = build_dir / "output" + tarball_name = f"{project.config.project_name}.firmware.tbz2" tarball_path = bundle_dir.joinpath(tarball_name) - cmd = ['tar', 'cvfj', tarball_path, '.'] + cmd = ["tar", "cvfj", tarball_path, "."] subprocess.run(cmd, cwd=artifacts_dir, check=True) meta = info.objects.add() meta.file_name = tarball_name @@ -176,76 +170,92 @@ def test(opts): # Run zmake tests to ensure we have a fully working zmake before # proceeding. - subprocess.run([zephyr_dir / 'zmake' / 'run_tests.sh'], check=True) + subprocess.run([zephyr_dir / "zmake" / "run_tests.sh"], check=True) # Run formatting checks on all BUILD.py files. - config_files = zephyr_dir.rglob('**/BUILD.py') - subprocess.run(['black', '--diff', '--check', *config_files], check=True) + config_files = zephyr_dir.rglob("**/BUILD.py") + subprocess.run(["black", "--diff", "--check", *config_files], check=True) - cmd = ['zmake', '-D', 'test', '-a', '--no-rebuild'] + cmd = ["zmake", "-D", "test", "-a", "--no-rebuild"] if opts.code_coverage: - cmd.append('--coverage') + cmd.append("--coverage") ret = subprocess.run(cmd, check=True).returncode if ret: return ret if opts.code_coverage: platform_ec = zephyr_dir.parent - build_dir = platform_ec / 'build' / 'zephyr' + build_dir = platform_ec / "build" / "zephyr" # Merge lcov files here because bundle failures are "infra" failures. cmd = [ - '/usr/bin/lcov', - '-o', - build_dir / 'zephyr_merged.info', - '--rc', - 'lcov_branch_coverage=1', - '-a', - build_dir / 'all_tests.info', - '-a', - build_dir / 'all_builds.info', + "/usr/bin/lcov", + "-o", + build_dir / "zephyr_merged.info", + "--rc", + "lcov_branch_coverage=1", + "-a", + build_dir / "all_tests.info", + "-a", + build_dir / "all_builds.info", ] output = subprocess.run( - cmd, cwd=pathlib.Path(__file__).parent, check=True, - stdout=subprocess.PIPE, universal_newlines=True).stdout - _extract_lcov_summary('EC_ZEPHYR_MERGED', metrics, output) + cmd, + cwd=pathlib.Path(__file__).parent, + check=True, + stdout=subprocess.PIPE, + universal_newlines=True, + ).stdout + _extract_lcov_summary("EC_ZEPHYR_MERGED", metrics, output) output = subprocess.run( - ['/usr/bin/lcov', '--summary', build_dir / 'all_tests.info'], - cwd=pathlib.Path(__file__).parent, check=True, - stdout=subprocess.PIPE, universal_newlines=True).stdout - _extract_lcov_summary('EC_ZEPHYR_TESTS', metrics, output) - - cmd = ['make', 'coverage', f'-j{opts.cpus}'] + ["/usr/bin/lcov", "--summary", build_dir / "all_tests.info"], + cwd=pathlib.Path(__file__).parent, + check=True, + stdout=subprocess.PIPE, + universal_newlines=True, + ).stdout + _extract_lcov_summary("EC_ZEPHYR_TESTS", metrics, output) + + cmd = ["make", "coverage", f"-j{opts.cpus}"] print(f"# Running {' '.join(cmd)}.") subprocess.run(cmd, cwd=platform_ec, check=True) output = subprocess.run( - ['/usr/bin/lcov', '--summary', platform_ec / 'build/coverage/lcov.info'], - cwd=pathlib.Path(__file__).parent, check=True, - stdout=subprocess.PIPE, universal_newlines=True).stdout - _extract_lcov_summary('EC_LEGACY_MERGED', metrics, output) + ["/usr/bin/lcov", "--summary", platform_ec / "build/coverage/lcov.info"], + cwd=pathlib.Path(__file__).parent, + check=True, + stdout=subprocess.PIPE, + universal_newlines=True, + ).stdout + _extract_lcov_summary("EC_LEGACY_MERGED", metrics, output) cmd = [ - '/usr/bin/lcov', - '-o', - build_dir / 'lcov.info', - '--rc', - 'lcov_branch_coverage=1', - '-a', - build_dir / 'zephyr_merged.info', - '-a', - platform_ec / 'build/coverage/lcov.info', + "/usr/bin/lcov", + "-o", + build_dir / "lcov.info", + "--rc", + "lcov_branch_coverage=1", + "-a", + build_dir / "zephyr_merged.info", + "-a", + platform_ec / "build/coverage/lcov.info", ] output = subprocess.run( - cmd, cwd=pathlib.Path(__file__).parent, check=True, - stdout=subprocess.PIPE, universal_newlines=True).stdout - _extract_lcov_summary('ALL_MERGED', metrics, output) - - with open(opts.metrics, 'w') as file: + cmd, + cwd=pathlib.Path(__file__).parent, + check=True, + stdout=subprocess.PIPE, + universal_newlines=True, + ).stdout + _extract_lcov_summary("ALL_MERGED", metrics, output) + + with open(opts.metrics, "w") as file: file.write(json_format.MessageToJson(metrics)) return 0 -COVERAGE_RE = re.compile(r'lines\.*: *([0-9\.]+)% \(([0-9]+) of ([0-9]+) lines\)') +COVERAGE_RE = re.compile(r"lines\.*: *([0-9\.]+)% \(([0-9]+) of ([0-9]+) lines\)") + + def _extract_lcov_summary(name, metrics, output): re_match = COVERAGE_RE.search(output) if re_match: @@ -255,12 +265,13 @@ def _extract_lcov_summary(name, metrics, output): metric.covered_lines = int(re_match.group(2)) metric.total_lines = int(re_match.group(3)) + def main(args): """Builds and tests all of the Zephyr targets and reports build metrics""" opts = parse_args(args) - if not hasattr(opts, 'func'): - print('Must select a valid sub command!') + if not hasattr(opts, "func"): + print("Must select a valid sub command!") return -1 # Run selected sub command function @@ -272,70 +283,66 @@ def parse_args(args): parser = argparse.ArgumentParser(description=__doc__) parser.add_argument( - '--cpus', + "--cpus", default=multiprocessing.cpu_count(), - help='The number of cores to use.', + help="The number of cores to use.", ) parser.add_argument( - '--metrics', - dest='metrics', + "--metrics", + dest="metrics", required=True, - help='File to write the json-encoded MetricsList proto message.', + help="File to write the json-encoded MetricsList proto message.", ) parser.add_argument( - '--metadata', + "--metadata", required=False, help=( - 'Full pathname for the file in which to write build artifact ' - 'metadata.' + "Full pathname for the file in which to write build artifact " "metadata." ), ) parser.add_argument( - '--output-dir', + "--output-dir", required=False, - help=( - 'Full pathname for the directory in which to bundle build ' - 'artifacts.' - ), + help=("Full pathname for the directory in which to bundle build " "artifacts."), ) parser.add_argument( - '--code-coverage', + "--code-coverage", required=False, - action='store_true', - help='Build host-based unit tests for code coverage.', + action="store_true", + help="Build host-based unit tests for code coverage.", ) parser.add_argument( - '--bcs-version', - dest='bcs_version', - default='', + "--bcs-version", + dest="bcs_version", + default="", required=False, # TODO(b/180008931): make this required=True. - help='BCS version to include in metadata.', + help="BCS version to include in metadata.", ) # Would make this required=True, but not available until 3.7 sub_cmds = parser.add_subparsers() - build_cmd = sub_cmds.add_parser('build', help='Builds all firmware targets') + build_cmd = sub_cmds.add_parser("build", help="Builds all firmware targets") build_cmd.set_defaults(func=build) build_cmd = sub_cmds.add_parser( - 'bundle', - help='Creates a tarball containing build ' - 'artifacts from all firmware targets', + "bundle", + help="Creates a tarball containing build " + "artifacts from all firmware targets", ) build_cmd.set_defaults(func=bundle) - test_cmd = sub_cmds.add_parser('test', help='Runs all firmware unit tests') + test_cmd = sub_cmds.add_parser("test", help="Runs all firmware unit tests") test_cmd.set_defaults(func=test) return parser.parse_args(args) -if __name__ == '__main__': +if __name__ == "__main__": sys.exit(main(sys.argv[1:])) diff --git a/zephyr/zmake/tests/conftest.py b/zephyr/zmake/tests/conftest.py index 38e34bef56..be1de01401 100644 --- a/zephyr/zmake/tests/conftest.py +++ b/zephyr/zmake/tests/conftest.py @@ -9,7 +9,6 @@ import pathlib import hypothesis import pytest - import zmake.zmake as zm hypothesis.settings.register_profile( diff --git a/zephyr/zmake/tests/test_build_config.py b/zephyr/zmake/tests/test_build_config.py index 76cc0a2028..f79ed1f8a0 100644 --- a/zephyr/zmake/tests/test_build_config.py +++ b/zephyr/zmake/tests/test_build_config.py @@ -13,7 +13,6 @@ import tempfile import hypothesis import hypothesis.strategies as st import pytest - import zmake.jobserver import zmake.util as util from zmake.build_config import BuildConfig diff --git a/zephyr/zmake/tests/test_generate_readme.py b/zephyr/zmake/tests/test_generate_readme.py index cb4bcf6cc1..2149b3fc6e 100644 --- a/zephyr/zmake/tests/test_generate_readme.py +++ b/zephyr/zmake/tests/test_generate_readme.py @@ -7,7 +7,6 @@ Tests for the generate_readme.py file. """ import pytest - import zmake.generate_readme as gen_readme diff --git a/zephyr/zmake/tests/test_modules.py b/zephyr/zmake/tests/test_modules.py index 600544d2e7..9446e54f1c 100644 --- a/zephyr/zmake/tests/test_modules.py +++ b/zephyr/zmake/tests/test_modules.py @@ -9,7 +9,6 @@ import tempfile import hypothesis import hypothesis.strategies as st - import zmake.modules module_lists = st.lists( diff --git a/zephyr/zmake/tests/test_packers.py b/zephyr/zmake/tests/test_packers.py index 43b63a908f..402cee690e 100644 --- a/zephyr/zmake/tests/test_packers.py +++ b/zephyr/zmake/tests/test_packers.py @@ -10,7 +10,6 @@ import tempfile import hypothesis import hypothesis.strategies as st import pytest - import zmake.output_packers as packers # Strategies for use with hypothesis diff --git a/zephyr/zmake/tests/test_project.py b/zephyr/zmake/tests/test_project.py index b5facbc331..5b5ca12583 100644 --- a/zephyr/zmake/tests/test_project.py +++ b/zephyr/zmake/tests/test_project.py @@ -11,7 +11,6 @@ import tempfile import hypothesis import hypothesis.strategies as st import pytest - import zmake.modules import zmake.output_packers import zmake.project diff --git a/zephyr/zmake/tests/test_reexec.py b/zephyr/zmake/tests/test_reexec.py index 5d7905cd8f..08943909b2 100644 --- a/zephyr/zmake/tests/test_reexec.py +++ b/zephyr/zmake/tests/test_reexec.py @@ -8,7 +8,6 @@ import sys import unittest.mock as mock import pytest - import zmake.__main__ as main diff --git a/zephyr/zmake/tests/test_toolchains.py b/zephyr/zmake/tests/test_toolchains.py index 910a5faa78..f210bb7511 100644 --- a/zephyr/zmake/tests/test_toolchains.py +++ b/zephyr/zmake/tests/test_toolchains.py @@ -8,7 +8,6 @@ import os import pathlib import pytest - import zmake.output_packers import zmake.project as project import zmake.toolchains as toolchains diff --git a/zephyr/zmake/tests/test_util.py b/zephyr/zmake/tests/test_util.py index 1ec0076162..4a6c39f904 100644 --- a/zephyr/zmake/tests/test_util.py +++ b/zephyr/zmake/tests/test_util.py @@ -10,7 +10,6 @@ import tempfile import hypothesis import hypothesis.strategies as st import pytest - import zmake.util as util # Strategies for use with hypothesis diff --git a/zephyr/zmake/tests/test_zmake.py b/zephyr/zmake/tests/test_zmake.py index 4ca1d7f077..1c892ca2e4 100644 --- a/zephyr/zmake/tests/test_zmake.py +++ b/zephyr/zmake/tests/test_zmake.py @@ -11,14 +11,13 @@ import re import unittest.mock import pytest -from testfixtures import LogCapture - import zmake.build_config import zmake.jobserver import zmake.multiproc as multiproc import zmake.output_packers import zmake.project import zmake.toolchains +from testfixtures import LogCapture OUR_PATH = os.path.dirname(os.path.realpath(__file__)) -- cgit v1.2.1 From fa9398743f429539cbd2d987790bb2af4a9e6517 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Tue, 12 Jul 2022 13:00:40 -0700 Subject: rgbkbd: ectool: fix response size for rgbkbd host command This patch fixes ioctl size error for rgbkbd host command "ioctl -1, errno 90 (Message too long), EC result 255" BRANCH=none BUG=none TEST=Run ectool rgb commands on Vell Signed-off-by: Parth Malkan Change-Id: Ia03745db5207e5f4400d9a73a8f8a96f14e55460 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759264 Commit-Queue: YH Lin Reviewed-by: YH Lin --- util/ectool.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/ectool.c b/util/ectool.c index 9a74cf207e..ba85e821df 100644 --- a/util/ectool.c +++ b/util/ectool.c @@ -1385,7 +1385,7 @@ static int cmd_rgbkbd(int argc, char *argv[]) if (cmd_rgbkbd_parse_rgb_text(argv[2], &p.color)) return -1; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r)); } else if (argc == 3 && !strcasecmp(argv[1], "demo")) { /* Usage 3 */ val = strtol(argv[2], &e, 0); @@ -1395,7 +1395,7 @@ static int cmd_rgbkbd(int argc, char *argv[]) } p.subcmd = EC_RGBKBD_SUBCMD_DEMO; p.demo = val; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r)); } else if (argc == 4 && !strcasecmp(argv[1], "scale")) { /* Usage 4 */ val = strtol(argv[2], &e, 0); @@ -1409,7 +1409,7 @@ static int cmd_rgbkbd(int argc, char *argv[]) return -1; } p.subcmd = EC_RGBKBD_SUBCMD_SET_SCALE; - rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, 0); + rv = ec_command(EC_CMD_RGBKBD, 0, &p, sizeof(p), &r, sizeof(r)); } else if (argc == 2 && !strcasecmp(argv[1], "getconfig")) { /* Usage 5 */ char *type; -- cgit v1.2.1 From 78e9ba59a54e358804bf7f857f6446a46d60c7c0 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 7 Jul 2022 14:42:35 -0600 Subject: cq: Upload code coverage html report as artifact Run genhtml to create a code coverage report and upload it as an artifact. BRANCH=None BUG=b:231639771 TEST=None Signed-off-by: Jeremy Bettis Change-Id: I2de2f9ac8fcd93227fe3ab55ebda301f087d02db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3755964 Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Yuval Peress --- zephyr/README.md | 15 +++++++++++---- zephyr/firmware_builder.py | 23 +++++++++++++++++++++++ 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/zephyr/README.md b/zephyr/README.md index 1a4967a8b2..0954af073a 100644 --- a/zephyr/README.md +++ b/zephyr/README.md @@ -25,10 +25,13 @@ See the piplines [here](https://gitlab.com/zephyr-ec/ec/-/pipelines). To test the cq builder script run these commands: ### firmware-zephyr-cq +Build this in the /mnt/host/source/src/platform/ec dir not +~/chromiumos/src/platform/ec so that the paths come out the same as the CQ. + ``` rm -rf /tmp/artifact_bundles /tmp/artifact_bundle_metadata \ - ~/chromiumos/src/platform/ec/build -( cd ~/chromiumos/src/platform/ec/zephyr ; \ + /mnt/host/source//src/platform/ec/build +( cd /mnt/host/source/src/platform/ec/zephyr ; \ ./firmware_builder.py --metrics /tmp/metrics-build build && \ ./firmware_builder.py --metrics /tmp/metrics-test test && \ ./firmware_builder.py --metrics /tmp/metrics-bundle bundle && \ @@ -39,10 +42,14 @@ ls -l /tmp/artifact_bundles/ ``` ### firmware-zephyr-cov-cq + +Build this in the /mnt/host/source/src/platform/ec dir not +~/chromiumos/src/platform/ec so that the paths come out the same as the CQ. + ``` rm -rf /tmp/artifact_bundles-cov /tmp/artifact_bundle_metadata-cov \ - ~/chromiumos/src/platform/ec/build && \ -cd ~/chromiumos/src/platform/ec/zephyr && \ + /mnt/host/source/src/platform/ec/build && \ +cd /mnt/host/source/src/platform/ec/zephyr && \ ./firmware_builder.py --metrics /tmp/metrics --code-coverage build && \ ./firmware_builder.py --metrics /tmp/metrics --code-coverage test && \ ./firmware_builder.py --metrics /tmp/metrics --code-coverage \ diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index c0963a84db..a9f7b61345 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -131,6 +131,13 @@ def bundle_coverage(opts): meta.lcov_info.type = ( firmware_pb2.FirmwareArtifactInfo.LcovTarballInfo.LcovType.LCOV ) + tarball_name = "html.tbz2" + tarball_path = bundle_dir / tarball_name + cmd = ["tar", "cvfj", tarball_path, "lcov_rpt"] + subprocess.run(cmd, cwd=build_dir, check=True) + meta = info.objects.add() + meta.file_name = tarball_name + meta.coverage_html.SetInParent() write_metadata(opts, info) @@ -248,6 +255,22 @@ def test(opts): ).stdout _extract_lcov_summary("ALL_MERGED", metrics, output) + subprocess.run( + [ + "/usr/bin/genhtml", + "--branch-coverage", + "-q", + "-o", + build_dir / "lcov_rpt", + "-t", + "All boards and tests merged", + "-s", + build_dir / "lcov.info", + ], + cwd=pathlib.Path(__file__).parent, + check=True, + ) + with open(opts.metrics, "w") as file: file.write(json_format.MessageToJson(metrics)) return 0 -- cgit v1.2.1 From 0ed9052bc706efd3fe55a6f5d813d8a7459c9d9b Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Tue, 12 Jul 2022 17:04:11 -0600 Subject: ec: Shim PLATFORM_EC_PERIPHERAL_CHARGER Shim CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER in zephyr to CONFIG_PERIPHERAL_CHARGER in legacy ec. BRANCH=None BUG=b:238773780,b:181253613 TEST=make -j40 buildall && util/run_tests.sh Change-Id: Iedfc6f7eb89fd7018892f9e467c163c453cfcdc6 Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759273 Commit-Queue: Keith Short Tested-by: Jeremy Bettis Auto-Submit: Jeremy Bettis Reviewed-by: Keith Short Commit-Queue: Jeremy Bettis --- zephyr/CMakeLists.txt | 2 ++ zephyr/Kconfig | 1 + zephyr/shim/include/config_chip.h | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 1388ad9a06..2f8b214abb 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -325,6 +325,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE "${PLATFORM_EC}/common/motion_sense.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MP2964 "${PLATFORM_EC}/driver/mp2964.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER + "${PLATFORM_EC}/common/peripheral_charger.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_PORT80 "${PLATFORM_EC}/common/port80.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON diff --git a/zephyr/Kconfig b/zephyr/Kconfig index 33176c4237..42c6a8220c 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -72,6 +72,7 @@ rsource "Kconfig.throttle_ap" rsource "Kconfig.usba" rsource "Kconfig.usbc" rsource "Kconfig.watchdog" +rsource "Kconfig.wireless_charger" # Define PLATFORM_EC_... options to enable EC features. Each Kconfig should be # matched by a line in zephyr/shim/include/config_chip.h which #defines the diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 0dbbc5d678..deb6340dd5 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -2604,4 +2604,9 @@ extern struct jump_data mock_jump_data; #define CONFIG_IO_EXPANDER_CCGXXF #endif +#undef CONFIG_PERIPHERAL_CHARGER +#ifdef CONFIG_PLATFORM_EC_PERIPHERAL_CHARGER +#define CONFIG_PERIPHERAL_CHARGER +#endif + #endif /* __CROS_EC_CONFIG_CHIP_H */ -- cgit v1.2.1 From 884bd065e7b260cd8689b6ac7d8a9d059102aeef Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Tue, 12 Jul 2022 15:41:27 +1000 Subject: it8xxx2: generate a 1MB firmware binary https://crrev.com/c/3742961 changed IT8xxx2 to report 1MB flash rather than 768k, but this breaks flashing the EC with flashrom because flashrom refuses to flash an image that is not the same size as the destination. Because the image size and reported size must be the same and it seems most correct to report a size that accurately reflects the physical flash size (1MB), pad the EC binary image to 1MB. BUG=b:238566735 TEST=zephyr.bin for Nereid is now 1MB BRANCH=none Signed-off-by: Peter Marheine Change-Id: Icb1c2ce32f22918cdaf93e802ff296a9aa9ae77c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756996 Reviewed-by: Ting Shen --- zephyr/include/cros/ite/it8xxx2.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi index 4631e64f6f..26060c5ed4 100644 --- a/zephyr/include/cros/ite/it8xxx2.dtsi +++ b/zephyr/include/cros/ite/it8xxx2.dtsi @@ -108,5 +108,7 @@ offset = <0x60000>; size = <0x60000>; }; + pad-byte = <0xff>; + pad-after = <0x40000>; }; }; -- cgit v1.2.1 From ee9dc345f7903980e8b438aa25b9d1c11c00fc5e Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Tue, 12 Jul 2022 09:30:06 +0800 Subject: Xivu : Correct board_check_extpower function. This patch correct board_check_extpower function. Base on c0/c1 port detected, control ec_acok_otg_c0/c1 separately. BUG=none BRANCH=none TEST=zmake build xivu success Change-Id: I4fce95551932d7b80c8386fc931ffe7c9b8c9257 Signed-off-by: Logan_Liao Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756992 Reviewed-by: Elthan Huang Reviewed-by: Logan Liao Reviewed-by: Peter Marheine Commit-Queue: Logan Liao Tested-by: Logan Liao --- zephyr/projects/nissa/src/xivu/charger.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/zephyr/projects/nissa/src/xivu/charger.c b/zephyr/projects/nissa/src/xivu/charger.c index 7f3933e578..459f6f1cff 100644 --- a/zephyr/projects/nissa/src/xivu/charger.c +++ b/zephyr/projects/nissa/src/xivu/charger.c @@ -36,17 +36,18 @@ int extpower_is_present(void) */ __override void board_check_extpower(void) { - int extpower_present; + int extpower_present_p0; + int extpower_present_p1; if (pd_is_connected(0)) - extpower_present = extpower_is_present(); - else - extpower_present = 0; + extpower_present_p0 = extpower_is_present(); + else if (pd_is_connected(1)) + extpower_present_p1 = extpower_is_present(); gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c0), - extpower_present); + extpower_present_p0); gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_acok_otg_c1), - extpower_present); + extpower_present_p1); } __override void board_hibernate(void) -- cgit v1.2.1 From c7f783e9b31b1091c0b9f43bfcb86425052895c4 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Mon, 11 Jul 2022 11:17:04 +0800 Subject: kinox: modify fan table setting Modify fan table setting. BUG=b:238277632 BRANCH=none TEST=The THM team member test success.make BOARD=kinox passed. Signed-off-by: Matt Wang Change-Id: I50f2fce224a976f145e858bdc0f0060515f875d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754782 Reviewed-by: Ricky Chang --- board/kinox/fans.c | 6 +++--- board/kinox/sensors.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/kinox/fans.c b/board/kinox/fans.c index 4c5dbfc8c1..60cf5878d6 100644 --- a/board/kinox/fans.c +++ b/board/kinox/fans.c @@ -37,9 +37,9 @@ static const struct fan_conf fan_conf_0 = { * Set minimum at around 30% PWM. */ static const struct fan_rpm fan_rpm_0 = { - .rpm_min = 750, - .rpm_start = 750, - .rpm_max = 5200, + .rpm_min = 1000, + .rpm_start = 1000, + .rpm_max = 4200, }; const struct fan_t fans[FAN_CH_COUNT] = { diff --git a/board/kinox/sensors.c b/board/kinox/sensors.c index ccd2855f3d..3441d2621e 100644 --- a/board/kinox/sensors.c +++ b/board/kinox/sensors.c @@ -104,8 +104,8 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); [EC_TEMP_THRESH_HIGH] = C_TO_K(90), \ [EC_TEMP_THRESH_HALT] = C_TO_K(90), \ }, \ - .temp_fan_off = C_TO_K(35), \ - .temp_fan_max = C_TO_K(65), \ + .temp_fan_off = C_TO_K(25), \ + .temp_fan_max = C_TO_K(75), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; -- cgit v1.2.1 From f787fdccf55f060000516497da46e857ea935e68 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Fri, 8 Jul 2022 21:00:41 +0800 Subject: kinox: set the default 65w when barrel jack present The barrel jack needs almost 1.1 secnods to get the voltage and current. It will cause get the wrong charge port. So set the default 65w when BJ_ADP_PRESENT_ODL is present on board init. BUG=b:236202586 BRANCH=none TEST=The PPVAR_SYS not drop and the EN_PPVAR_BJ_ADP_L not set to high when EC do reboot. Signed-off-by: Matt Wang Change-Id: I0c473377a8bfdc2ea3ac4dc51649fa10faecd907 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752439 Reviewed-by: Elthan Huang Reviewed-by: Ricky Chang --- board/kinox/power_detection.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c index b48333b82c..5723777973 100644 --- a/board/kinox/power_detection.c +++ b/board/kinox/power_detection.c @@ -384,10 +384,19 @@ void adp_id_deferred(void) static void barrel_jack_setting(void) { + struct charge_port_info pi = { 0 }; /* Check ADP_ID when barrel jack is present */ - if (!gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) + if (!gpio_get_level(GPIO_BJ_ADP_PRESENT_ODL)) { + /* Set the default 65w adaptor */ + pi.voltage = 20000; + pi.current = 3250; + + charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, + DEDICATED_CHARGE_PORT, &pi); + /* Delay 220ms to get the first ADP_ID value */ hook_call_deferred(&adp_id_deferred_data, 220 * MSEC); + } } DECLARE_HOOK(HOOK_INIT, barrel_jack_setting, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From b871c0c7268d82c7a5dde6c670566d3becd2186c Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Thu, 7 Jul 2022 14:49:53 +0530 Subject: zephyr: switchcap power off delay Some switchcaps do not have power good signal which can give an indication to EC when system is power on or off. Due to lack of this feedback path, there isn't any way for EC to determine when the switchcap can be turned on reliably after power off. This patch introduces a delay parameter which can be used to wait for a specified amount of time, determined experimentally before turning on switchcap after switchcap is turned off. BRANCH=None BUG=b:212222920 TEST=Tested image on hoglin board for following after adding delay 1) dut-control warm_reset:on; dut-control warm_reset:off 2) quick power off and power on from ec console In both the cases device can boot up without complaining AP POWER NOT READY. Signed-off-by: Kshitiz Godara Change-Id: I97be7fbde7261a408c530710972770f7c66609d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750958 Reviewed-by: Wai-Hong Tam Commit-Queue: Wai-Hong Tam --- zephyr/dts/bindings/switchcap/switchcap-gpio.yaml | 6 ++++++ zephyr/shim/src/switchcap_gpio.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml b/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml index 5d1a25bf94..0016401835 100644 --- a/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml +++ b/zephyr/dts/bindings/switchcap/switchcap-gpio.yaml @@ -14,3 +14,9 @@ properties: required: false description: | GPIO used to read if power is good + + poff-delay-ms: + type: int + required: false + description: | + Additional power off delay required for some systems diff --git a/zephyr/shim/src/switchcap_gpio.c b/zephyr/shim/src/switchcap_gpio.c index 30fdae788c..6944055fb8 100644 --- a/zephyr/shim/src/switchcap_gpio.c +++ b/zephyr/shim/src/switchcap_gpio.c @@ -24,9 +24,17 @@ #define SC_PIN_POWER_GOOD_EXISTS DT_NODE_EXISTS(SC_PIN_POWER_GOOD_PHANDLE) #define SC_PIN_POWER_GOOD GPIO_DT_FROM_NODE(SC_PIN_POWER_GOOD_PHANDLE) +#if DT_NODE_HAS_PROP(DT_PATH(switchcap), poff_delay_ms) +static const int32_t poff_delay_ms = DT_PROP(DT_PATH(switchcap), poff_delay_ms); +#else +static const int32_t poff_delay_ms; +#endif + void board_set_switchcap_power(int enable) { gpio_pin_set_dt(SC_PIN_ENABLE, enable); + if (!enable && poff_delay_ms > 0) + k_msleep(poff_delay_ms); } int board_is_switchcap_enabled(void) -- cgit v1.2.1 From f1addb9d960dd94827f3eeb53e9654b963cd0f54 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 13 Jul 2022 03:24:11 +0000 Subject: Revert "bc12: add comma separator in bc12 shim for a better format" This reverts commit 59ddcfc2cf71e0c0f72ce5db583f5536d1aa73c0. Reason for revert: The generated config is empty Original change's description: > bc12: add comma separator in bc12 shim for a better format > > Move the comma from header to the dts binding. > > BUG=none > TEST=zmake --goma testall --clobber > BRANCH=none > > Signed-off-by: Eric Yilun Lin > Change-Id: If7cd0d3947cc73c9b2ef8ad378d58fce5e8fe833 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750554 > Commit-Queue: Eric Yilun Lin > Reviewed-by: Jeremy Bettis > Auto-Submit: Eric Yilun Lin > Tested-by: Eric Yilun Lin Bug: none Change-Id: I1e3935b750e127ed1e117710fa9772e065b7bb84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759829 Reviewed-by: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/shim/include/usbc/bc12_pi3usb9201.h | 2 +- zephyr/shim/include/usbc/bc12_rt1739.h | 2 +- zephyr/shim/include/usbc/bc12_rt9490.h | 2 +- zephyr/shim/src/bc12.c | 18 +++++++++--------- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/zephyr/shim/include/usbc/bc12_pi3usb9201.h b/zephyr/shim/include/usbc/bc12_pi3usb9201.h index 552fe828b1..85b1c00443 100644 --- a/zephyr/shim/include/usbc/bc12_pi3usb9201.h +++ b/zephyr/shim/include/usbc/bc12_pi3usb9201.h @@ -10,4 +10,4 @@ #define BC12_CHIP_PI3USB9201(id) \ { \ .drv = &pi3usb9201_drv, \ - } + }, diff --git a/zephyr/shim/include/usbc/bc12_rt1739.h b/zephyr/shim/include/usbc/bc12_rt1739.h index efe6d42412..15df73857a 100644 --- a/zephyr/shim/include/usbc/bc12_rt1739.h +++ b/zephyr/shim/include/usbc/bc12_rt1739.h @@ -10,4 +10,4 @@ #define BC12_CHIP_RT1739(id) \ { \ .drv = &rt1739_bc12_drv, \ - } + }, diff --git a/zephyr/shim/include/usbc/bc12_rt9490.h b/zephyr/shim/include/usbc/bc12_rt9490.h index acdcdd562c..fe57e42524 100644 --- a/zephyr/shim/include/usbc/bc12_rt9490.h +++ b/zephyr/shim/include/usbc/bc12_rt9490.h @@ -10,4 +10,4 @@ #define BC12_CHIP_RT9490(id) \ { \ .drv = &rt9490_bc12_drv, \ - } + }, diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c index 19cabfc83e..4f1fd2db01 100644 --- a/zephyr/shim/src/bc12.c +++ b/zephyr/shim/src/bc12.c @@ -16,15 +16,15 @@ #define BC12_CHIP(id, fn) [USBC_PORT(id)] = fn(id) -#define MAYBE_EMPTY(compat, config) \ - COND_CODE_1(DT_HAS_STATUS_OKAY(compat), \ - (DT_FOREACH_STATUS_OKAY_VARGS(compat, BC12_CHIP, config)), \ - (EMPTY)) - /* Power Path Controller */ -struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { LIST_DROP_EMPTY( - MAYBE_EMPTY(RT1739_BC12_COMPAT, BC12_CHIP_RT1739), - MAYBE_EMPTY(RT9490_BC12_COMPAT, BC12_CHIP_RT9490), - MAYBE_EMPTY(PI3USB9201_COMPAT, BC12_CHIP_PI3USB9201)) }; +struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { + DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP, + BC12_CHIP_RT1739) + DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, + BC12_CHIP_RT9490) + DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, + BC12_CHIP, + BC12_CHIP_PI3USB9201) +}; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From b5a837bd83d52a51c49dc552b29f30c219b4ff7e Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Thu, 7 Jul 2022 21:08:02 +0530 Subject: ap_pwrseq: all_sys_pwrgd_timeout handling API all_sys_pwrgd_handler() implements sleep for "all_sys_pwrgd_handler" time value always. Change will avoid this sleep if all_sys_pwrgd gpio is already high. BUG=b:236664113 BRANCH=none TEST=Verify boot on nivviks Change-Id: I1aecb021ae37129d07f58b07b148a84282d73f84 Signed-off-by: Deepti Deshatty Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750835 Reviewed-by: Andrew McRae Reviewed-by: Li1 Feng Reviewed-by: Bernardo Perez Priego --- zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c index f7d34b5712..4d1425588f 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c @@ -38,7 +38,8 @@ int all_sys_pwrgd_handler(void) int retry = 0; /* TODO: Add condition for no power sequencer */ - k_msleep(AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout)); + power_wait_signals_timeout(POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD), + AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout)); if (power_signal_get(PWR_DSW_PWROK) == 0) { /* Todo: Remove workaround for the retry -- cgit v1.2.1 From b6435b22c43379fed2b9922d5345d97c77888e41 Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Tue, 12 Jul 2022 18:12:51 +0530 Subject: zephyr: hoglin: Increase power off delay Hoglin switchcap requires more time for shutdown to complete. The additional delay measured by experiments is ~450 ms (varying from 430 ms to 470 ms). This patch increases the shutdown delay for Hoglin to 500 ms. BRANCH=None BUG=b:212222920 TEST=Tested image on hoglin board for following 1) dut-control warm_reset:on; dut-control warm_reset:off 2) quick power off and power on from ec console In both the cases device can boot up without complaining AP POWER NOT READY. Signed-off-by: Kshitiz Godara Change-Id: I76ed544983b5cb84525f26a64f589fa6512d51fc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3757284 Reviewed-by: Wai-Hong Tam --- zephyr/projects/herobrine/switchcap_hoglin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/projects/herobrine/switchcap_hoglin.dts b/zephyr/projects/herobrine/switchcap_hoglin.dts index 37e1a27e2c..a59f5721b8 100644 --- a/zephyr/projects/herobrine/switchcap_hoglin.dts +++ b/zephyr/projects/herobrine/switchcap_hoglin.dts @@ -7,5 +7,6 @@ switchcap { compatible = "switchcap-gpio"; enable-pin = <&gpio_switchcap_on>; + poff-delay-ms = <500>; }; }; -- cgit v1.2.1 From aad57590800fb60dee40c3db33e19272c4e5afb4 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Wed, 13 Jul 2022 09:40:07 +0800 Subject: fusb307bgevb: Free some flash size Undefine CONFIG_CMD_GETTIME to save some flash size BUG=none BRANCH=none TEST=make BOARD=fusb307bgevb Before commit: *** 92 bytes in flash and 5324 bytes in RAM still available on fusb307bgevb RO **** *** 4588 bytes in flash and 5324 bytes in RAM still available on fusb307bgevb RW **** After commit: *** 220 bytes in flash and 5324 bytes in RAM still available on fusb307bgevb RO **** *** 4696 bytes in flash and 5324 bytes in RAM still available on fusb307bgevb RW **** Signed-off-by: Devin Lu Change-Id: Iec3ddbb59af1d01d7849cd2f84a57ee86b51b81b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759824 Tested-by: Devin Lu Reviewed-by: Ting Shen Commit-Queue: Devin Lu --- board/fusb307bgevb/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h index c678238e6b..df34096283 100644 --- a/board/fusb307bgevb/board.h +++ b/board/fusb307bgevb/board.h @@ -85,6 +85,7 @@ /* Enable control of GPIOs over USB */ #define CONFIG_USB_GPIO +#undef CONFIG_CMD_GETTIME #undef CONFIG_WATCHDOG_HELP #undef CONFIG_LID_SWITCH -- cgit v1.2.1 From 44031c6e382eb02ecef93280a5c54b4416f678fe Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 13 Jul 2022 03:25:14 +0000 Subject: Revert "ppc: add comma separator in ppc shim for a better format" This reverts commit 5ebc252cce3c6ab4e8ce69696162f93790c8f811. Reason for revert: The generated config is empty Original change's description: > ppc: add comma separator in ppc shim for a better format > > Move the comma from header to the dts binding. > > BUG=none > TEST=zmake --goma testall --clobber > BRANCH=none > > Change-Id: Ife8651cc58f43cdd9e6f6088fd860dec4d03237a > Signed-off-by: Eric Yilun Lin > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750555 > Commit-Queue: Eric Yilun Lin > Auto-Submit: Eric Yilun Lin > Tested-by: Eric Yilun Lin > Reviewed-by: Jeremy Bettis Bug: none Change-Id: Icf223b8feed366aefadd8cc36bd98361b2fc95a0 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759830 Auto-Submit: Eric Yilun Lin Commit-Queue: Eric Yilun Lin Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin --- zephyr/shim/include/usbc/ppc_rt1739.h | 2 +- zephyr/shim/include/usbc/ppc_sn5s330.h | 10 ++++------ zephyr/shim/include/usbc/ppc_syv682x.h | 2 +- zephyr/shim/src/ppc.c | 29 ++++++++++++++++------------- 4 files changed, 22 insertions(+), 21 deletions(-) diff --git a/zephyr/shim/include/usbc/ppc_rt1739.h b/zephyr/shim/include/usbc/ppc_rt1739.h index f8788e505e..19e169a436 100644 --- a/zephyr/shim/include/usbc/ppc_rt1739.h +++ b/zephyr/shim/include/usbc/ppc_rt1739.h @@ -15,4 +15,4 @@ .frs_en = COND_CODE_1(DT_NODE_HAS_PROP(id, irq), \ (GPIO_SIGNAL(DT_PHANDLE(id, irq))), \ (0)), \ - } + }, diff --git a/zephyr/shim/include/usbc/ppc_sn5s330.h b/zephyr/shim/include/usbc/ppc_sn5s330.h index f42039da7a..7ec9b434a8 100644 --- a/zephyr/shim/include/usbc/ppc_sn5s330.h +++ b/zephyr/shim/include/usbc/ppc_sn5s330.h @@ -7,9 +7,7 @@ #define SN5S330_COMPAT ti_sn5s330 -#define PPC_CHIP_SN5S330(id) \ - { \ - .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ - .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ - .drv = &sn5s330_drv \ - } +#define PPC_CHIP_SN5S330(id) \ + { .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ + .drv = &sn5s330_drv }, diff --git a/zephyr/shim/include/usbc/ppc_syv682x.h b/zephyr/shim/include/usbc/ppc_syv682x.h index d45a9862f1..f177aebe8b 100644 --- a/zephyr/shim/include/usbc/ppc_syv682x.h +++ b/zephyr/shim/include/usbc/ppc_syv682x.h @@ -15,4 +15,4 @@ .frs_en = COND_CODE_1( \ DT_NODE_HAS_PROP(id, frs_en_gpio), \ (GPIO_SIGNAL(DT_PHANDLE(id, frs_en_gpio))), (0)), \ - } + }, diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c index f301c50e09..936367ca78 100644 --- a/zephyr/shim/src/ppc.c +++ b/zephyr/shim/src/ppc.c @@ -26,22 +26,25 @@ #define PPC_CHIP_ELE_ALT(id, fn) [PPC_ID(id)] = fn(id) -#define MAYBE_EMPTY(compat, type, config) \ - COND_CODE_1(DT_HAS_STATUS_OKAY(compat), \ - (DT_FOREACH_STATUS_OKAY_VARGS(compat, type, config)), \ - (EMPTY)) - /* Power Path Controller */ -struct ppc_config_t ppc_chips[] = { LIST_DROP_EMPTY( - MAYBE_EMPTY(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_RT1739), - MAYBE_EMPTY(SN5S330_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SN5S330), - MAYBE_EMPTY(SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X)) }; +struct ppc_config_t ppc_chips[] = { + DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_RT1739) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS( + SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X) +}; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* Alt Power Path Controllers */ -struct ppc_config_t ppc_chips_alt[] = { LIST_DROP_EMPTY( - MAYBE_EMPTY(RT1739_PPC_COMPAT, PPC_CHIP_ALT, PPC_CHIP_RT1739), - MAYBE_EMPTY(SN5S330_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SN5S330), - MAYBE_EMPTY(SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X)) }; +struct ppc_config_t ppc_chips_alt[] = { + DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_RT1739) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS( + SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X) +}; #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 7c6d8dab8fd7958e0334c665d6a922eecea670f8 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Tue, 12 Jul 2022 12:44:16 +1000 Subject: ap_pwrseq: Use common ESPI init and callback Use common ESPI init and callback for power signals ESPI callback so that signal changes are guaranteed to be received by the power signal VW handler. BUG=b:237449433 TEST=zmake build nivviks; flash & run BRANCH=none Signed-off-by: Andrew McRae Change-Id: I1dfbc45bd1944ab124bec42897617463190b6853 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756994 Reviewed-by: Peter Marheine --- zephyr/include/ap_power/ap_power_espi.h | 35 +++++++++++++++++++++++++++++++++ zephyr/shim/src/espi.c | 27 +++++++++++++++---------- zephyr/subsys/ap_pwrseq/signal_vw.c | 22 ++++++++++----------- 3 files changed, 63 insertions(+), 21 deletions(-) create mode 100644 zephyr/include/ap_power/ap_power_espi.h diff --git a/zephyr/include/ap_power/ap_power_espi.h b/zephyr/include/ap_power/ap_power_espi.h new file mode 100644 index 0000000000..53bd3811eb --- /dev/null +++ b/zephyr/include/ap_power/ap_power_espi.h @@ -0,0 +1,35 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * @file + * @brief API for power signal ESPI callback. + */ + +#ifndef __AP_POWER_AP_POWER_ESPI_H__ +#define __AP_POWER_AP_POWER_ESPI_H__ + +#include + +/** + * @brief ESPI callback for power signal handling. + * + * This callback must be registered for the bus events indicated below + * as part of the common ESPI initialisation and configuration. + * + * @param dev ESPI device + * @param cb Callback structure + * @param event ESPI event data + */ +void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb, + struct espi_event event); + +/* + * The ESPI bus events required for the power signal ESPI callback. + */ +#define POWER_SIGNAL_ESPI_BUS_EVENTS \ + (ESPI_BUS_EVENT_CHANNEL_READY | ESPI_BUS_EVENT_VWIRE_RECEIVED) + +#endif /* __AP_POWER_AP_POWER_ESPI_H__ */ diff --git a/zephyr/shim/src/espi.c b/zephyr/shim/src/espi.c index d67dba87d9..0232e0850f 100644 --- a/zephyr/shim/src/espi.c +++ b/zephyr/shim/src/espi.c @@ -14,6 +14,7 @@ #include #include +#include #include "acpi.h" #include "chipset.h" #include "common.h" @@ -583,8 +584,7 @@ static void espi_peripheral_handler(const struct device *dev, static int zephyr_shim_setup_espi(const struct device *unused) { - static struct { - struct espi_callback cb; + static const struct { espi_callback_handler_t handler; enum espi_bus_event event_type; } callbacks[] = { @@ -599,7 +599,14 @@ static int zephyr_shim_setup_espi(const struct device *unused) .handler = espi_peripheral_handler, .event_type = ESPI_BUS_PERIPHERAL_NOTIFICATION, }, +#if defined(CONFIG_AP_PWRSEQ) && DT_HAS_COMPAT_STATUS_OKAY(intel_ap_pwrseq_vw) + { + .handler = power_signal_espi_cb, + .event_type = POWER_SIGNAL_ESPI_BUS_EVENTS, + }, +#endif }; + static struct espi_callback cb[ARRAY_SIZE(callbacks)]; struct espi_cfg cfg = { .io_caps = ESPI_IO_MODE_QUAD_LINES, @@ -611,17 +618,17 @@ static int zephyr_shim_setup_espi(const struct device *unused) if (!device_is_ready(espi_dev)) k_oops(); - /* Configure eSPI */ - if (espi_config(espi_dev, &cfg)) { - LOG_ERR("Failed to configure eSPI device"); - return -1; - } - /* Setup callbacks */ for (size_t i = 0; i < ARRAY_SIZE(callbacks); i++) { - espi_init_callback(&callbacks[i].cb, callbacks[i].handler, + espi_init_callback(&cb[i], callbacks[i].handler, callbacks[i].event_type); - espi_add_callback(espi_dev, &callbacks[i].cb); + espi_add_callback(espi_dev, &cb[i]); + } + + /* Configure eSPI after callbacks are registered */ + if (espi_config(espi_dev, &cfg)) { + LOG_ERR("Failed to configure eSPI device"); + return -1; } return 0; diff --git a/zephyr/subsys/ap_pwrseq/signal_vw.c b/zephyr/subsys/ap_pwrseq/signal_vw.c index d2c3c0a8d1..2836a31f20 100644 --- a/zephyr/subsys/ap_pwrseq/signal_vw.c +++ b/zephyr/subsys/ap_pwrseq/signal_vw.c @@ -13,6 +13,15 @@ #if HAS_VW_SIGNALS +/* + * A callback must be registered on the ESPI device (for the + * bus events that are required to be handled) that calls + * power_signal_espi_cb(). + * + * This registration is done in a common ESPI initialisation module so + * that there is no possibility of missing events. + */ + LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); #define INIT_ESPI_SIGNAL(id) \ @@ -48,8 +57,8 @@ static atomic_t signal_valid; BUILD_ASSERT(ARRAY_SIZE(vw_config) <= (sizeof(atomic_t) * 8)); -static void espi_handler(const struct device *dev, struct espi_callback *cb, - struct espi_event event) +void power_signal_espi_cb(const struct device *dev, struct espi_callback *cb, + struct espi_event event) { LOG_DBG("ESPI event type 0x%x %d:%d", event.evt_type, event.evt_details, event.evt_data); @@ -94,15 +103,6 @@ int power_signal_vw_get(enum pwr_sig_vw vw) void power_signal_vw_init(void) { - static struct espi_callback espi_cb; - - /* Assumes ESPI device is already configured. */ - - /* Configure handler for eSPI events */ - espi_init_callback(&espi_cb, espi_handler, - ESPI_BUS_EVENT_CHANNEL_READY | - ESPI_BUS_EVENT_VWIRE_RECEIVED); - espi_add_callback(espi_dev, &espi_cb); /* * Check whether the bus is ready, and if so, * initialise the current values of the signals. -- cgit v1.2.1 From 304061cded5d718485bfa973e24b703371d6dbfc Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Thu, 7 Jul 2022 19:13:56 +0800 Subject: Mithrax : Add control normal keyboard backlight for Mithrax. Mithrax have two keyboard, normal keyboard and RGB keyboard. This patch add keyboard backlight with PWM control. BUG=b:223526803 BRANCH=none TEST=make BOARD=mithrax success, TEST pass that RGB keyboard and normal keyboard in Mithrax. Change-Id: I05ed743ef6ed684e0ca6d42627681df144185bc5 Signed-off-by: Logan_Liao Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750964 Tested-by: Logan Liao Commit-Queue: Logan Liao Reviewed-by: Logan Liao Reviewed-by: Ricky Chang --- board/mithrax/board.c | 12 ++++++++++++ board/mithrax/board.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/board/mithrax/board.c b/board/mithrax/board.c index 57d9039053..ca29e68fbf 100644 --- a/board/mithrax/board.c +++ b/board/mithrax/board.c @@ -25,6 +25,8 @@ #include "tablet_mode.h" #include "throttle_ap.h" #include "usbc_config.h" +#include "keyboard_backlight.h" +#include "rgb_keyboard.h" #include "gpio_list.h" /* Must come after other header files. */ @@ -180,3 +182,13 @@ static void rgb_backlight_config(void) else gpio_set_level(GPIO_EN_PP5000_LED, 0); } + +void board_kblight_init(void) +{ + if ((IS_ENABLED(CONFIG_PWM_KBLIGHT)) && + (ec_cfg_kb_backlight() == SOLID_COLOR)) + kblight_register(&kblight_pwm); + else if ((IS_ENABLED(CONFIG_RGB_KEYBOARD)) && + (ec_cfg_kb_backlight() == RGB)) + kblight_register(&kblight_rgbkbd); +} diff --git a/board/mithrax/board.h b/board/mithrax/board.h index 0660757d38..4e1fe54851 100644 --- a/board/mithrax/board.h +++ b/board/mithrax/board.h @@ -195,6 +195,8 @@ #define RGB_GRID0_COL 4 #define RGB_GRID0_ROW 1 +#define CONFIG_PWM_KBLIGHT + #ifndef __ASSEMBLER__ #include "gpio_signal.h" /* needed by registers.h */ -- cgit v1.2.1 From cce493a388878334a65af95c4313ee051ef8a546 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Mon, 11 Jul 2022 18:13:25 +0800 Subject: kinox: enable barrel jack switch at CHIPSET_STATE_ANY_OFF Add back the original function about the chromebox can swutch the barrel jack from type-c adapter at CHIPSET_STATE_ANY_OFF BUG=b:225769067 BRANCH=none TEST=Power type can switch to barrel jack in S5/G3 but can not switch in the others mode. Signed-off-by: Matt Wang Change-Id: I3427df6860ef5d282ceab1f842452b12fb0be01a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754820 Reviewed-by: Ricky Chang --- board/kinox/board.c | 1 + board/kinox/board.h | 2 ++ board/kinox/gpio.inc | 2 +- board/kinox/power_detection.c | 7 +++++++ 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/board/kinox/board.c b/board/kinox/board.c index 59aaee817b..6384f0d1a6 100644 --- a/board/kinox/board.c +++ b/board/kinox/board.c @@ -120,5 +120,6 @@ DECLARE_HOOK(HOOK_INIT, adp_state_init, HOOK_PRIO_INIT_CHARGE_MANAGER + 1); static void board_init(void) { + gpio_enable_interrupt(GPIO_BJ_ADP_PRESENT_ODL); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); diff --git a/board/kinox/board.h b/board/kinox/board.h index 490d5e8fae..0ae0507b43 100644 --- a/board/kinox/board.h +++ b/board/kinox/board.h @@ -177,6 +177,8 @@ enum fan_channel { FAN_CH_0 = 0, FAN_CH_COUNT }; enum mft_channel { MFT_CH_0 = 0, MFT_CH_COUNT }; +extern void adp_connect_interrupt(enum gpio_signal signal); + #endif /* !__ASSEMBLER__ */ #endif /* __CROS_EC_BOARD_H */ diff --git a/board/kinox/gpio.inc b/board/kinox/gpio.inc index d21782ba37..efe9e37eeb 100644 --- a/board/kinox/gpio.inc +++ b/board/kinox/gpio.inc @@ -19,6 +19,7 @@ GPIO_INT(SYS_SLP_S0IX_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_inte GPIO_INT(USB_C0_BC12_INT_ODL, PIN(C, 6), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(USB_C0_PPC_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, ppc_interrupt) GPIO_INT(USB_C0_TCPC_INT_ODL, PIN(A, 2), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(BJ_ADP_PRESENT_ODL, PIN(8, 2), GPIO_INT_BOTH | GPIO_PULL_UP, adp_connect_interrupt) GPIO_INT(EC_RECOVERY_BTN_OD, PIN(2, 3), GPIO_INT_BOTH, button_interrupt) /* CCD */ @@ -37,7 +38,6 @@ GPIO(HDMI_CONN_OC_ODL, PIN(2, 4), GPIO_INPUT) /* BarrelJack */ GPIO(EN_PPVAR_BJ_ADP_L, PIN(0, 7), GPIO_OUT_LOW) -GPIO(BJ_ADP_PRESENT_ODL, PIN(8, 2), GPIO_INPUT) /* Chipset PCH */ GPIO(EC_PCHHOT_ODL, PIN(7, 4), GPIO_INPUT) diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c index 5723777973..fdd88f1d4e 100644 --- a/board/kinox/power_detection.c +++ b/board/kinox/power_detection.c @@ -424,3 +424,10 @@ static void typec_adapter_setting(void) } } DECLARE_HOOK(HOOK_CHIPSET_RESUME, typec_adapter_setting, HOOK_PRIO_DEFAULT); + +/* IRQ for BJ plug/unplug. It shouldn't be called if BJ is the power source. */ +void adp_connect_interrupt(enum gpio_signal signal) +{ + if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) + hook_call_deferred(&adp_id_deferred_data, 0); +} -- cgit v1.2.1 From c8282f61e105490ed50120ec2d6a83a1e2ec1e08 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Mon, 11 Jul 2022 10:21:49 -0700 Subject: tree: Check return value from snprintf snprintf returns a negative value on failure. The return value should be checked to make sure that there were no errors. BRANCH=none BUG=b:238433667, b:234181908 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I64e2e69df7fa22c94f19acbbca8c6afbe6cf1ff1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756174 Reviewed-by: Denis Brockus --- board/fusb307bgevb/board.c | 29 ++++++++++++++++++++--------- board/hammer/board.c | 4 +++- board/prism/board.c | 4 +++- chip/host/persistence.c | 14 ++++++++++---- common/battery_v1.c | 7 +++++-- common/battery_v2.c | 5 +++-- common/fan.c | 4 +++- driver/battery/max17055.c | 9 ++++++--- include/common.h | 6 ++++++ include/printf.h | 7 ++++--- 10 files changed, 63 insertions(+), 26 deletions(-) diff --git a/board/fusb307bgevb/board.c b/board/fusb307bgevb/board.c index 853b38c0a3..3e8771a63b 100644 --- a/board/fusb307bgevb/board.c +++ b/board/fusb307bgevb/board.c @@ -72,10 +72,13 @@ static void button_refresh_event_deferred(void) /* Display supply voltage on first page. */ lcd_clear(); for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) { + int rv; pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused); - snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma); - lcd_set_cursor(0, i); - lcd_print_string(c); + rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma); + if (rv > 0) { + lcd_set_cursor(0, i); + lcd_print_string(c); + } } /* Display selector */ @@ -107,21 +110,29 @@ static void button_down_event_deferred(void) if (count == 0) { lcd_clear(); for (i = 0; i < MIN(pd_get_src_cap_cnt(0), 4); i++) { + int rv; pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused); - snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma); - lcd_set_cursor(0, i); - lcd_print_string(c); + rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, + ma); + if (rv > 0) { + lcd_set_cursor(0, i); + lcd_print_string(c); + } } } if (count == 4) { lcd_clear(); for (i = 4; i < pd_get_src_cap_cnt(0); i++) { + int rv; pd_extract_pdo_power(pd_get_src_caps(0)[i], &ma, &mv, &unused); - snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, ma); - lcd_set_cursor(0, i - 4); - lcd_print_string(c); + rv = snprintf(c, ARRAY_SIZE(c), "[%d] %dmV %dmA", i, mv, + ma); + if (rv > 0) { + lcd_set_cursor(0, i - 4); + lcd_print_string(c); + } } } diff --git a/board/hammer/board.c b/board/hammer/board.c index 12cf41e910..76a4df7eeb 100644 --- a/board/hammer/board.c +++ b/board/hammer/board.c @@ -322,7 +322,9 @@ __override const char *board_read_serial(void) int i; for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) { - snprintf(&str[pos], sizeof(str) - pos, "%02x", id[i]); + if (snprintf(&str[pos], sizeof(str) - pos, "%02x", + id[i]) < 0) + return NULL; } } diff --git a/board/prism/board.c b/board/prism/board.c index 5a50a8c950..5ff237317f 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -350,7 +350,9 @@ __override const char *board_read_serial(void) int i; for (i = 0; i < idlen && pos < sizeof(str); i++, pos += 2) { - snprintf(&str[pos], sizeof(str) - pos, "%02x", id[i]); + if (snprintf(&str[pos], sizeof(str) - pos, "%02x", + id[i]) < 0) + return NULL; } } diff --git a/chip/host/persistence.c b/chip/host/persistence.c index b2ab19f97e..d23615d1ec 100644 --- a/chip/host/persistence.c +++ b/chip/host/persistence.c @@ -62,6 +62,8 @@ static void get_storage_path(char *out) sz = snprintf(out, PATH_MAX - 1, "/dev/shm/EC_persist_%.*s", max_len, buf); + ASSERT(sz > 0); + out[PATH_MAX - 1] = '\0'; ASSERT(sz <= max_len + max_prefix_len); @@ -71,6 +73,7 @@ FILE *get_persistent_storage(const char *tag, const char *mode) { char buf[PATH_MAX]; char path[PATH_MAX]; + int sz; /* There's no longer tag in use right now, and there shouldn't be. */ ASSERT(strlen(tag) < 32); @@ -80,8 +83,9 @@ FILE *get_persistent_storage(const char *tag, const char *mode) * be named 'bar_persist_foo' */ get_storage_path(buf); - snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, buf, - tag); + sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, + buf, tag); + ASSERT(sz > 0); path[PATH_MAX - 1] = '\0'; return fopen(path, mode); @@ -96,13 +100,15 @@ void remove_persistent_storage(const char *tag) { char buf[PATH_MAX]; char path[PATH_MAX]; + int sz; /* There's no longer tag in use right now, and there shouldn't be. */ ASSERT(strlen(tag) < 32); get_storage_path(buf); - snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, buf, - tag); + sz = snprintf(path, PATH_MAX - 1, "%.*s_%32s", max_len + max_prefix_len, + buf, tag); + ASSERT(sz > 0); path[PATH_MAX - 1] = '\0'; unlink(path); diff --git a/common/battery_v1.c b/common/battery_v1.c index d0920d30b4..b53e57df8a 100644 --- a/common/battery_v1.c +++ b/common/battery_v1.c @@ -34,8 +34,11 @@ int update_static_battery_info(void) batt_str = (char *)host_get_memmap(EC_MEMMAP_BATT_SERIAL); memset(batt_str, 0, EC_MEMMAP_TEXT_MAX); rv = battery_serial_number(&batt_serial); - if (!rv) - snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X", batt_serial); + if (!rv) { + if (snprintf(batt_str, EC_MEMMAP_TEXT_MAX, "%04X", + batt_serial) <= 0) + rv |= EC_ERROR_UNKNOWN; + } /* Design Capacity of Full */ rv |= battery_design_capacity( diff --git a/common/battery_v2.c b/common/battery_v2.c index 1ed7205b65..4d4a14e113 100644 --- a/common/battery_v2.c +++ b/common/battery_v2.c @@ -220,8 +220,9 @@ int update_static_battery_info(void) /* Smart battery serial number is 16 bits */ rv = battery_serial_number(&batt_serial); if (!rv) - snprintf(bs->serial_ext, sizeof(bs->serial_ext), "%04X", - batt_serial); + if (snprintf(bs->serial_ext, sizeof(bs->serial_ext), "%04X", + batt_serial) <= 0) + rv |= EC_ERROR_UNKNOWN; /* Design Capacity of Full */ ret = battery_design_capacity(&val); diff --git a/common/fan.c b/common/fan.c index ee324b5031..1dfc9e1af5 100644 --- a/common/fan.c +++ b/common/fan.c @@ -183,7 +183,9 @@ static int cc_faninfo(int argc, char **argv) char leader[20] = ""; for (fan = 0; fan < fan_count; fan++) { if (fan_count > 1) - snprintf(leader, sizeof(leader), "Fan %d ", fan); + if (snprintf(leader, sizeof(leader), "Fan %d ", fan) < + 0) + leader[0] = '\0'; if (fan) ccprintf("\n"); ccprintf("%sActual: %4d rpm\n", leader, diff --git a/driver/battery/max17055.c b/driver/battery/max17055.c index 382995d0df..88d58eb659 100644 --- a/driver/battery/max17055.c +++ b/driver/battery/max17055.c @@ -92,10 +92,13 @@ int battery_device_name(char *device_name, int buf_size) int rv; rv = max17055_read(REG_DEVICE_NAME, &dev_id); - if (!rv) - snprintf(device_name, buf_size, "0x%04x", dev_id); + if (rv != EC_SUCCESS) + return rv; - return rv; + if (snprintf(device_name, buf_size, "0x%04x", dev_id) <= 0) + return EC_ERROR_UNKNOWN; + + return EC_SUCCESS; } int battery_state_of_charge_abs(int *percent) diff --git a/include/common.h b/include/common.h index 74c229261c..7a549a6d55 100644 --- a/include/common.h +++ b/include/common.h @@ -186,6 +186,12 @@ #define __override #define __overridable __attribute__((weak)) +/* + * Attribute that will generate a compiler warning if the return value is not + * used. + */ +#define __warn_unused_result __attribute__((warn_unused_result)) + /* * Macros for combining bytes into larger integers. _LE and _BE signify little * and big endian versions respectively. diff --git a/include/printf.h b/include/printf.h index 333e622b7b..370675ca46 100644 --- a/include/printf.h +++ b/include/printf.h @@ -99,7 +99,8 @@ __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c), * @param format Format string * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated. */ -__attribute__((__format__(__printf__, 3, 4))) __stdlib_compat int +__attribute__((__format__(__printf__, 3, 4))) +__warn_unused_result __stdlib_compat int crec_snprintf(char *str, size_t size, const char *format, ...); /** @@ -114,8 +115,8 @@ crec_snprintf(char *str, size_t size, const char *format, ...); * @return The string length written to str, or a negative value on error. * The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW. */ -__stdlib_compat int crec_vsnprintf(char *str, size_t size, const char *format, - va_list args); +__warn_unused_result __stdlib_compat int +crec_vsnprintf(char *str, size_t size, const char *format, va_list args); #endif /* !HIDE_EC_STDLIB */ -- cgit v1.2.1 From 36581192c7529332bea5663bed93dfae33f70666 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 8 Jul 2022 10:59:13 -0600 Subject: ec: Enforce black in presubmit Enforce black, isort formatting in presubmit for all python files. Do not enforce flake8, because it has errors on most of the files, and it seems to be basically the same as pylint, which is already run on pre-submit. Do not enforce it in the zmake unit test script. Do enforce the formatting in the firmware_builder.py script, and do it early for faster failures in CQ runs. BRANCH=None BUG=b:238434058 TEST=None Signed-off-by: Jeremy Bettis Change-Id: If3c42b2af41fd2e68accbe2867999dc931e88872 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749243 Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis --- PRESUBMIT.cfg | 2 +- firmware_builder.py | 30 ++++++++++++++--- util/python-pre-upload.sh | 49 +++++++++++++++++++++++++++ zephyr/firmware_builder.py | 4 --- zephyr/zmake/pre-upload.sh | 68 -------------------------------------- zephyr/zmake/run_tests.sh | 6 ---- zephyr/zmake/tests/test_version.py | 1 - 7 files changed, 76 insertions(+), 84 deletions(-) create mode 100755 util/python-pre-upload.sh delete mode 100755 zephyr/zmake/pre-upload.sh diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg index 531a74fad9..c9d0887b23 100644 --- a/PRESUBMIT.cfg +++ b/PRESUBMIT.cfg @@ -29,5 +29,5 @@ presubmit_check = util/presubmit_check.sh config_option_check = util/config_option_check.py host_command_check = util/host_command_check.sh ec_commands_h = util/linux_ec_commands_h_check.sh -zmake_preupload = zephyr/zmake/pre-upload.sh ${PRESUBMIT_FILES} +python_preupload = util/python-pre-upload.sh ${PRESUBMIT_FILES} migrated_files = util/migrated_files.sh ${PRESUBMIT_FILES} diff --git a/firmware_builder.py b/firmware_builder.py index d2548c3f5f..a4842cd454 100755 --- a/firmware_builder.py +++ b/firmware_builder.py @@ -45,6 +45,21 @@ def build(opts): """ metric_list = firmware_pb2.FwBuildMetricList() + # Run formatting checks on all python files. + subprocess.run(["black", "--check", "."], cwd=os.path.dirname(__file__), check=True) + subprocess.run( + [ + "isort", + "--settings-file=.isort.cfg", + "--check", + "--gitignore", + "--dont-follow-links", + ".", + ], + cwd=os.path.dirname(__file__), + check=True, + ) + if opts.code_coverage: print( "When --code-coverage is selected, 'build' is a no-op. " @@ -195,6 +210,14 @@ def test(opts): with open(opts.metrics, "w") as f: f.write(json_format.MessageToJson(metrics)) + # Run python unit tests. + subprocess.run( + ["util/ec3po/run_tests.sh"], cwd=os.path.dirname(__file__), check=True + ) + subprocess.run( + ["extra/stack_analyzer/run_tests.sh"], cwd=os.path.dirname(__file__), check=True + ) + # If building for code coverage, build the 'coverage' target, which # builds the posix-based unit tests for code coverage and assembles # the LCOV information. @@ -260,13 +283,13 @@ def parse_args(args): parser.add_argument( "--metadata", required=False, - help="Full pathname for the file in which to write build artifact " "metadata.", + help="Full pathname for the file in which to write build artifact metadata.", ) parser.add_argument( "--output-dir", required=False, - help="Full pathanme for the directory in which to bundle build " "artifacts.", + help="Full pathanme for the directory in which to bundle build artifacts.", ) parser.add_argument( @@ -293,8 +316,7 @@ def parse_args(args): build_cmd = sub_cmds.add_parser( "bundle", - help="Creates a tarball containing build " - "artifacts from all firmware targets", + help="Creates a tarball containing build artifacts from all firmware targets", ) build_cmd.set_defaults(func=bundle) diff --git a/util/python-pre-upload.sh b/util/python-pre-upload.sh new file mode 100755 index 0000000000..d560e7b6af --- /dev/null +++ b/util/python-pre-upload.sh @@ -0,0 +1,49 @@ +#!/bin/bash +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +set -e + +PYTHON_FILES=() + +for path in "$@"; do + case "${path}" in + *.py|*.pyi) + PYTHON_FILES+=("${path}") + ;; + util/chargen) + PYTHON_FILES+=("${path}") + ;; + esac +done + +if [ "${#PYTHON_FILES}" -eq 0 ]; then + # No python changes made, do nothing. + exit 0 +fi + +EXIT_STATUS=0 + +# Wraps a black/isort command and reports how to fix it. +wrap_fix_msg() { + local cmd="$1" + shift + + if ! "${cmd}" "$@"; then + cat <&2 +Looks like the ${cmd} formatter detected that formatting changes +need applied. Fix by running this command from the platform/ec +directory and amending your changes: + + ${cmd} ${PYTHON_FILES[*]} + +EOF + EXIT_STATUS=1 + fi +} + +# black and isort are provided by repo_tools +wrap_fix_msg black --check "${PYTHON_FILES[@]}" +wrap_fix_msg isort --check "${PYTHON_FILES[@]}" + +exit "${EXIT_STATUS}" diff --git a/zephyr/firmware_builder.py b/zephyr/firmware_builder.py index a9f7b61345..60a716d170 100755 --- a/zephyr/firmware_builder.py +++ b/zephyr/firmware_builder.py @@ -179,10 +179,6 @@ def test(opts): # proceeding. subprocess.run([zephyr_dir / "zmake" / "run_tests.sh"], check=True) - # Run formatting checks on all BUILD.py files. - config_files = zephyr_dir.rglob("**/BUILD.py") - subprocess.run(["black", "--diff", "--check", *config_files], check=True) - cmd = ["zmake", "-D", "test", "-a", "--no-rebuild"] if opts.code_coverage: cmd.append("--coverage") diff --git a/zephyr/zmake/pre-upload.sh b/zephyr/zmake/pre-upload.sh deleted file mode 100755 index 15b6637f44..0000000000 --- a/zephyr/zmake/pre-upload.sh +++ /dev/null @@ -1,68 +0,0 @@ -#!/bin/bash -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -set -e - -ZMAKE_FILES=() -BUILD_PY_FILES=() - -for path in "$@"; do - case "${path}" in - *zephyr/zmake/*.py ) - ZMAKE_FILES+=("${path}") - ;; - */BUILD.py ) - BUILD_PY_FILES+=("${path}") - ;; - esac -done - -AFFECTED_FILES=("${ZMAKE_FILES[@]}" "${BUILD_PY_FILES[@]}") - -if [ "${#AFFECTED_FILES}" -eq 0 ]; then - # No zmake changes made, do nothing. - exit 0 -fi - -EXIT_STATUS=0 - -# Wraps a black/isort command and reports how to fix it. -wrap_fix_msg() { - local cmd="$1" - shift - - if ! "${cmd}" "$@"; then - cat <&2 -Looks like zmake's ${cmd} formatter detected that formatting changes -need applied. Fix by running this command from the zephyr/zmake -directory and amending your changes: - - ${cmd} . - -EOF - EXIT_STATUS=1 - fi -} - -# We only want to run black, flake8, and isort inside of the chroot, -# as these are formatting tools which we want the specific versions -# provided by the chroot. -if [ -f /etc/cros_chroot_version ]; then - cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")" - wrap_fix_msg black --check --diff "${AFFECTED_FILES[@]}" - wrap_fix_msg isort --check "${AFFECTED_FILES[@]}" - if [ "${#ZMAKE_FILES[@]}" -gt 0 ]; then - flake8 "${ZMAKE_FILES[@]}" || EXIT_STATUS=1 - fi - exit "${EXIT_STATUS}" -else - cat <&2 -WARNING: It looks like you made zmake changes, but I'm running outside -of the chroot, and can't run zmake's auto-formatters. - -It is recommended that you run repo upload from inside the chroot, or -you may see formatting errors during your CQ run. -EOF - exit 1 -fi diff --git a/zephyr/zmake/run_tests.sh b/zephyr/zmake/run_tests.sh index 0015614c23..49736c81da 100755 --- a/zephyr/zmake/run_tests.sh +++ b/zephyr/zmake/run_tests.sh @@ -25,11 +25,5 @@ export PYTHONPATH="${PWD}" # happens. Remove this flag. pytest --hypothesis-profile=cq . -# Check black formatting. -black --check --diff . - -# Check flake8 reports no issues. -flake8 . - # Check auto-generated README.md is as expected. python -m zmake generate-readme --diff diff --git a/zephyr/zmake/tests/test_version.py b/zephyr/zmake/tests/test_version.py index a81d682b77..37d4fd8d67 100644 --- a/zephyr/zmake/tests/test_version.py +++ b/zephyr/zmake/tests/test_version.py @@ -9,7 +9,6 @@ import subprocess import unittest.mock as mock import pytest # pylint: disable=import-error - import zmake.output_packers import zmake.project import zmake.version as version -- cgit v1.2.1 From 8e66887419fa9d0e9040a1dd909ae675a0f963aa Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Tue, 12 Jul 2022 16:15:06 -0600 Subject: zephyr: test: Separate usbc_alt_mode binary Build the USB-C alt mode tests as a separate binary to reduce flakiness. BUG=b:233100881 TEST=shuffle_test.sh test-drivers-usbc_alt_mode \ "Expected 4 identify VDOs, got 0" BRANCH=none Signed-off-by: Abe Levkoy Change-Id: I95518691746e3c395cfc1b58aa17ff2a865514b9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759269 Reviewed-by: Yuval Peress --- zephyr/test/drivers/BUILD.py | 4 + zephyr/test/drivers/CMakeLists.txt | 1 - .../drivers/src/integration/usbc/usb_alt_mode.c | 373 --------------------- zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt | 12 + .../test/drivers/usbc_alt_mode/src/usbc_alt_mode.c | 373 +++++++++++++++++++++ 5 files changed, 389 insertions(+), 374 deletions(-) delete mode 100644 zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c create mode 100644 zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt create mode 100644 zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py index 3c94b7d55e..e619faad6c 100644 --- a/zephyr/test/drivers/BUILD.py +++ b/zephyr/test/drivers/BUILD.py @@ -19,6 +19,10 @@ isl923x = drivers.variant( project_name="test-drivers-isl923x", ) +usbc_alt_mode = drivers.variant( + project_name="test-drivers-usbc_alt_mode", +) + led_driver = drivers.variant( project_name="test-drivers-led_driver", dts_overlays=[ diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index 4cfecb9224..dc763c4b14 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -53,7 +53,6 @@ if(subproject_path STREQUAL "") src/integration/usbc/usb_20v_3a_pd_charger.c src/integration/usbc/usb_5v_3a_pd_sink.c src/integration/usbc/usb_5v_3a_pd_source.c - src/integration/usbc/usb_alt_mode.c src/integration/usbc/usb_attach_src_snk.c src/integration/usbc/usb_pd_ctrl_msg.c src/integration/usbc/usb_pd_rev3.c diff --git a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c b/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c deleted file mode 100644 index 7724ac993f..0000000000 --- a/zephyr/test/drivers/src/integration/usbc/usb_alt_mode.c +++ /dev/null @@ -1,373 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include -#include - -#include "ec_commands.h" -#include "ec_tasks.h" -#include "emul/emul_isl923x.h" -#include "emul/tcpc/emul_ps8xxx.h" -#include "emul/tcpc/emul_tcpci.h" -#include "emul/tcpc/emul_tcpci_partner_snk.h" -#include "host_command.h" -#include "test/drivers/stubs.h" -#include "tcpm/tcpci.h" -#include "test/drivers/utils.h" -#include "test/drivers/test_state.h" - -#define TEST_PORT USBC_PORT_C0 - -struct usbc_alt_mode_fixture { - const struct emul *tcpci_emul; - const struct emul *charger_emul; - struct tcpci_partner_data partner; - struct tcpci_snk_emul_data snk_ext; -}; - -struct usbc_alt_mode_dp_unsupported_fixture { - const struct emul *tcpci_emul; - const struct emul *charger_emul; - struct tcpci_partner_data partner; - struct tcpci_snk_emul_data snk_ext; -}; - -static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture) -{ - const struct emul *tcpc_emul = fixture->tcpci_emul; - struct tcpci_partner_data *partner_emul = &fixture->partner; - - /* - * TODO(b/221439302) Updating the TCPCI emulator registers, updating the - * vbus, as well as alerting should all be a part of the connect - * function. - */ - /* Set VBUS to vSafe0V initially. */ - isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); - tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS, - TCPC_REG_POWER_STATUS_VBUS_DET); - tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS, - TCPC_REG_EXT_STATUS_SAFE0V); - tcpci_tcpc_alert(0); - k_sleep(K_SECONDS(1)); - zassume_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul), - NULL); - - /* Wait for PD negotiation and current ramp. */ - k_sleep(K_SECONDS(10)); -} - -static void disconnect_partner_from_port(struct usbc_alt_mode_fixture *fixture) -{ - zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); - isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); - k_sleep(K_SECONDS(1)); -} - -static void add_discovery_responses(struct tcpci_partner_data *partner) -{ - /* Add Discover Identity response */ - partner->identity_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_PD, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT); - partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH( - /* USB host */ false, /* USB device */ false, IDH_PTYPE_AMA, - /* modal operation */ true, USB_VID_GOOGLE); - partner->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd; - partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678); - /* Hardware version 1, firmware version 2 */ - partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000; - partner->identity_vdos = VDO_INDEX_AMA + 1; - - /* Add Discover Modes response */ - /* Support one mode for DisplayPort VID. Copied from Hoho. */ - partner->modes_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES); - partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP( - 0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK); - partner->modes_vdos = VDO_INDEX_HDR + 2; - - /* Add Discover SVIDs response */ - /* Support DisplayPort VID. */ - partner->svids_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_PD, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID); - partner->svids_vdm[VDO_INDEX_HDR + 1] = - VDO_SVID(USB_SID_DISPLAYPORT, 0); - partner->svids_vdos = VDO_INDEX_HDR + 2; -} - -static void add_displayport_mode_responses(struct tcpci_partner_data *partner) -{ - /* DisplayPort alt mode setup remains in the same suite as discovery - * setup because DisplayPort is picked from the Discovery VDOs offered. - */ - - /* Add DisplayPort EnterMode response */ - partner->dp_enter_mode_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE); - partner->dp_enter_mode_vdos = VDO_INDEX_HDR + 1; - - /* Add DisplayPort StatusUpdate response */ - partner->dp_status_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS); - partner->dp_status_vdm[VDO_INDEX_HDR + 1] = - /* Mainly copied from hoho */ - VDO_DP_STATUS(0, /* IRQ_HPD */ - false, /* HPD_HI|LOW - Changed*/ - 0, /* request exit DP */ - 0, /* request exit USB */ - 0, /* MF pref */ - true, /* DP Enabled */ - 0, /* power low e.g. normal */ - 0x2 /* Connected as Sink */); - partner->dp_status_vdos = VDO_INDEX_HDR + 2; - - /* Add DisplayPort Configure Response */ - partner->dp_config_vdm[VDO_INDEX_HDR] = - VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, - VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG); - partner->dp_config_vdos = VDO_INDEX_HDR + 1; -} - -static void *usbc_alt_mode_setup(void) -{ - static struct usbc_alt_mode_fixture fixture; - struct tcpci_partner_data *partner = &fixture.partner; - struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; - - tcpci_partner_init(partner, PD_REV20); - partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); - - /* Get references for the emulators */ - fixture.tcpci_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); - fixture.charger_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - - add_discovery_responses(partner); - add_displayport_mode_responses(partner); - - /* Sink 5V 3A. */ - snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); - - return &fixture; -} - -static void *usbc_alt_mode_dp_unsupported_setup(void) -{ - static struct usbc_alt_mode_fixture fixture; - struct tcpci_partner_data *partner = &fixture.partner; - struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; - - tcpci_partner_init(partner, PD_REV20); - partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); - - /* Get references for the emulators */ - fixture.tcpci_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); - /* The configured TCPCI rev must match the emulator's supported rev. */ - tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; - tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); - fixture.charger_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - - /* - * Respond to discovery REQs to indicate DisplayPort support, but do not - * respond to DisplayPort alt mode VDMs, including Enter Mode. - */ - add_discovery_responses(partner); - - /* Sink 5V 3A. */ - snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); - - return &fixture; -} - -static void usbc_alt_mode_before(void *data) -{ - /* Set chipset to ON, this will set TCPM to DRP */ - test_set_chipset_to_s0(); - - /* TODO(b/214401892): Check why need to give time TCPM to spin */ - k_sleep(K_SECONDS(1)); - - connect_partner_to_port((struct usbc_alt_mode_fixture *)data); -} - -static void usbc_alt_mode_after(void *data) -{ - disconnect_partner_from_port((struct usbc_alt_mode_fixture *)data); -} - -ZTEST_F(usbc_alt_mode, verify_discovery) -{ - uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; - struct ec_response_typec_discovery *discovery = - (struct ec_response_typec_discovery *)response_buffer; - host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, - sizeof(response_buffer)); - - /* The host command does not count the VDM header in identity_count. */ - zassert_equal(discovery->identity_count, - fixture->partner.identity_vdos - 1, - "Expected %d identity VDOs, got %d", - fixture->partner.identity_vdos - 1, - discovery->identity_count); - zassert_mem_equal( - discovery->discovery_vdo, fixture->partner.identity_vdm + 1, - discovery->identity_count * sizeof(*discovery->discovery_vdo), - "Discovered SOP identity ACK did not match"); - zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", - discovery->svid_count); - zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, - "Expected SVID 0x%0000x, got 0x%0000x", - USB_SID_DISPLAYPORT, discovery->svids[0].svid); - zassert_equal(discovery->svids[0].mode_count, 1, - "Expected 1 DP mode, got %d", - discovery->svids[0].mode_count); - zassert_equal(discovery->svids[0].mode_vdo[0], - fixture->partner.modes_vdm[1], - "DP mode VDOs did not match"); -} - -ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) -{ - /* TODO(b/237553647): Test EC-driven mode entry (requires a separate - * config). - */ - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); - k_sleep(K_SECONDS(1)); - - /* Verify host command when VDOs are present. */ - struct ec_params_usb_pd_get_mode_request params = { - .port = TEST_PORT, - .svid_idx = 0, - }; - struct ec_params_usb_pd_get_mode_response response; - struct host_cmd_handler_args args = BUILD_HOST_COMMAND( - EC_CMD_USB_PD_GET_AMODE, 0, response, params); - - zassume_ok(host_command_process(&args), NULL); - zassume_ok(args.result, NULL); - - /* Response should be populated with a DisplayPort VDO */ - zassert_equal(args.response_size, sizeof(response), NULL); - zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); - zassert_equal(response.vdo[0], - fixture->partner.modes_vdm[response.opos], NULL); - - /* DPM configures the partner on DP mode entry */ - /* Verify port partner thinks its configured for DisplayPort */ - zassert_true(fixture->partner.displayport_configured, NULL); -} - -ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) -{ - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); - k_sleep(K_SECONDS(1)); - - /* DPM configures the partner on DP mode entry */ - /* Verify port partner thinks its configured for DisplayPort */ - zassert_true(fixture->partner.displayport_configured, NULL); - - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_EXIT_MODES, 0); - k_sleep(K_SECONDS(1)); - zassert_false(fixture->partner.displayport_configured, NULL); - - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); - k_sleep(K_SECONDS(1)); - zassert_true(fixture->partner.displayport_configured, NULL); - - /* Verify that DisplayPort is the active alternate mode. */ - /* TODO(b/235984702): Wrap EC_CMD_USB_PD_GET_AMODE in a function. */ - struct ec_params_usb_pd_get_mode_request params = { - .port = TEST_PORT, - .svid_idx = 0, - }; - struct ec_params_usb_pd_get_mode_response response; - struct host_cmd_handler_args args = BUILD_HOST_COMMAND( - EC_CMD_USB_PD_GET_AMODE, 0, response, params); - - zassume_ok(host_command_process(&args), NULL); - zassume_ok(args.result, NULL); - - /* Response should be populated with a DisplayPort VDO */ - zassert_equal(args.response_size, sizeof(response), NULL); - zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); - zassert_equal(response.vdo[0], - fixture->partner.modes_vdm[response.opos], NULL); -} - -ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, - usbc_alt_mode_before, usbc_alt_mode_after, NULL); - -/* - * When the partner advertises DP mode support but refuses to enter, discovery - * should still work as if the partner were compliant. - */ -ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery) -{ - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); - k_sleep(K_SECONDS(1)); - - uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; - struct ec_response_typec_discovery *discovery = - (struct ec_response_typec_discovery *)response_buffer; - host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, - sizeof(response_buffer)); - - /* The host command does not count the VDM header in identity_count. */ - zassert_equal(discovery->identity_count, - fixture->partner.identity_vdos - 1, - "Expected %d identity VDOs, got %d", - fixture->partner.identity_vdos - 1, - discovery->identity_count); - zassert_mem_equal( - discovery->discovery_vdo, fixture->partner.identity_vdm + 1, - discovery->identity_count * sizeof(*discovery->discovery_vdo), - "Discovered SOP identity ACK did not match"); - zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", - discovery->svid_count); - zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, - "Expected SVID 0x%0000x, got 0x%0000x", - USB_SID_DISPLAYPORT, discovery->svids[0].svid); - zassert_equal(discovery->svids[0].mode_count, 1, - "Expected 1 DP mode, got %d", - discovery->svids[0].mode_count); - zassert_equal(discovery->svids[0].mode_vdo[0], - fixture->partner.modes_vdm[1], - "DP mode VDOs did not match"); -} - -/* - * When the partner advertises DP support but refuses to enter DP mode, the TCPM - * should try once and then give up. - */ -ZTEST_F(usbc_alt_mode_dp_unsupported, verify_displayport_mode_nonentry) -{ - host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, - TYPEC_MODE_DP); - k_sleep(K_SECONDS(1)); - - zassert_false(fixture->partner.displayport_configured, NULL); - int dp_attempts = - atomic_get(&fixture->partner.displayport_enter_attempts); - zassert_equal(dp_attempts, 1, "Expected 1 DP attempt, got %d", - dp_attempts); -} - -ZTEST_SUITE(usbc_alt_mode_dp_unsupported, drivers_predicate_post_main, - usbc_alt_mode_dp_unsupported_setup, usbc_alt_mode_before, - usbc_alt_mode_after, NULL); diff --git a/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt new file mode 100644 index 0000000000..f8f265c021 --- /dev/null +++ b/zephyr/test/drivers/usbc_alt_mode/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name) +zephyr_interface_library_named(${lib_name}) + +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}") +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") +zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/usbc_alt_mode.c") + +zephyr_library_link_libraries(${lib_name}) diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c new file mode 100644 index 0000000000..7724ac993f --- /dev/null +++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c @@ -0,0 +1,373 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include +#include + +#include "ec_commands.h" +#include "ec_tasks.h" +#include "emul/emul_isl923x.h" +#include "emul/tcpc/emul_ps8xxx.h" +#include "emul/tcpc/emul_tcpci.h" +#include "emul/tcpc/emul_tcpci_partner_snk.h" +#include "host_command.h" +#include "test/drivers/stubs.h" +#include "tcpm/tcpci.h" +#include "test/drivers/utils.h" +#include "test/drivers/test_state.h" + +#define TEST_PORT USBC_PORT_C0 + +struct usbc_alt_mode_fixture { + const struct emul *tcpci_emul; + const struct emul *charger_emul; + struct tcpci_partner_data partner; + struct tcpci_snk_emul_data snk_ext; +}; + +struct usbc_alt_mode_dp_unsupported_fixture { + const struct emul *tcpci_emul; + const struct emul *charger_emul; + struct tcpci_partner_data partner; + struct tcpci_snk_emul_data snk_ext; +}; + +static void connect_partner_to_port(struct usbc_alt_mode_fixture *fixture) +{ + const struct emul *tcpc_emul = fixture->tcpci_emul; + struct tcpci_partner_data *partner_emul = &fixture->partner; + + /* + * TODO(b/221439302) Updating the TCPCI emulator registers, updating the + * vbus, as well as alerting should all be a part of the connect + * function. + */ + /* Set VBUS to vSafe0V initially. */ + isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); + tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS, + TCPC_REG_POWER_STATUS_VBUS_DET); + tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS, + TCPC_REG_EXT_STATUS_SAFE0V); + tcpci_tcpc_alert(0); + k_sleep(K_SECONDS(1)); + zassume_ok(tcpci_partner_connect_to_tcpci(partner_emul, tcpc_emul), + NULL); + + /* Wait for PD negotiation and current ramp. */ + k_sleep(K_SECONDS(10)); +} + +static void disconnect_partner_from_port(struct usbc_alt_mode_fixture *fixture) +{ + zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); + isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); + k_sleep(K_SECONDS(1)); +} + +static void add_discovery_responses(struct tcpci_partner_data *partner) +{ + /* Add Discover Identity response */ + partner->identity_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_PD, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_IDENT); + partner->identity_vdm[VDO_INDEX_IDH] = VDO_IDH( + /* USB host */ false, /* USB device */ false, IDH_PTYPE_AMA, + /* modal operation */ true, USB_VID_GOOGLE); + partner->identity_vdm[VDO_INDEX_CSTAT] = 0xabcdabcd; + partner->identity_vdm[VDO_INDEX_PRODUCT] = VDO_PRODUCT(0x1234, 0x5678); + /* Hardware version 1, firmware version 2 */ + partner->identity_vdm[VDO_INDEX_AMA] = 0x12000000; + partner->identity_vdos = VDO_INDEX_AMA + 1; + + /* Add Discover Modes response */ + /* Support one mode for DisplayPort VID. Copied from Hoho. */ + partner->modes_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_MODES); + partner->modes_vdm[VDO_INDEX_HDR + 1] = VDO_MODE_DP( + 0, MODE_DP_PIN_C, 1, CABLE_PLUG, MODE_DP_V13, MODE_DP_SNK); + partner->modes_vdos = VDO_INDEX_HDR + 2; + + /* Add Discover SVIDs response */ + /* Support DisplayPort VID. */ + partner->svids_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_PD, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DISCOVER_SVID); + partner->svids_vdm[VDO_INDEX_HDR + 1] = + VDO_SVID(USB_SID_DISPLAYPORT, 0); + partner->svids_vdos = VDO_INDEX_HDR + 2; +} + +static void add_displayport_mode_responses(struct tcpci_partner_data *partner) +{ + /* DisplayPort alt mode setup remains in the same suite as discovery + * setup because DisplayPort is picked from the Discovery VDOs offered. + */ + + /* Add DisplayPort EnterMode response */ + partner->dp_enter_mode_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_ENTER_MODE); + partner->dp_enter_mode_vdos = VDO_INDEX_HDR + 1; + + /* Add DisplayPort StatusUpdate response */ + partner->dp_status_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_STATUS); + partner->dp_status_vdm[VDO_INDEX_HDR + 1] = + /* Mainly copied from hoho */ + VDO_DP_STATUS(0, /* IRQ_HPD */ + false, /* HPD_HI|LOW - Changed*/ + 0, /* request exit DP */ + 0, /* request exit USB */ + 0, /* MF pref */ + true, /* DP Enabled */ + 0, /* power low e.g. normal */ + 0x2 /* Connected as Sink */); + partner->dp_status_vdos = VDO_INDEX_HDR + 2; + + /* Add DisplayPort Configure Response */ + partner->dp_config_vdm[VDO_INDEX_HDR] = + VDO(USB_SID_DISPLAYPORT, /* structured VDM */ true, + VDO_CMDT(CMDT_RSP_ACK) | CMD_DP_CONFIG); + partner->dp_config_vdos = VDO_INDEX_HDR + 1; +} + +static void *usbc_alt_mode_setup(void) +{ + static struct usbc_alt_mode_fixture fixture; + struct tcpci_partner_data *partner = &fixture.partner; + struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; + + tcpci_partner_init(partner, PD_REV20); + partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); + + /* Get references for the emulators */ + fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + add_discovery_responses(partner); + add_displayport_mode_responses(partner); + + /* Sink 5V 3A. */ + snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + + return &fixture; +} + +static void *usbc_alt_mode_dp_unsupported_setup(void) +{ + static struct usbc_alt_mode_fixture fixture; + struct tcpci_partner_data *partner = &fixture.partner; + struct tcpci_snk_emul_data *snk_ext = &fixture.snk_ext; + + tcpci_partner_init(partner, PD_REV20); + partner->extensions = tcpci_snk_emul_init(snk_ext, partner, NULL); + + /* Get references for the emulators */ + fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + /* The configured TCPCI rev must match the emulator's supported rev. */ + tcpc_config[TEST_PORT].flags |= TCPC_FLAGS_TCPCI_REV2_0; + tcpci_emul_set_rev(fixture.tcpci_emul, TCPCI_EMUL_REV2_0_VER1_1); + fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + /* + * Respond to discovery REQs to indicate DisplayPort support, but do not + * respond to DisplayPort alt mode VDMs, including Enter Mode. + */ + add_discovery_responses(partner); + + /* Sink 5V 3A. */ + snk_ext->pdo[1] = PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + + return &fixture; +} + +static void usbc_alt_mode_before(void *data) +{ + /* Set chipset to ON, this will set TCPM to DRP */ + test_set_chipset_to_s0(); + + /* TODO(b/214401892): Check why need to give time TCPM to spin */ + k_sleep(K_SECONDS(1)); + + connect_partner_to_port((struct usbc_alt_mode_fixture *)data); +} + +static void usbc_alt_mode_after(void *data) +{ + disconnect_partner_from_port((struct usbc_alt_mode_fixture *)data); +} + +ZTEST_F(usbc_alt_mode, verify_discovery) +{ + uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; + struct ec_response_typec_discovery *discovery = + (struct ec_response_typec_discovery *)response_buffer; + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, + sizeof(response_buffer)); + + /* The host command does not count the VDM header in identity_count. */ + zassert_equal(discovery->identity_count, + fixture->partner.identity_vdos - 1, + "Expected %d identity VDOs, got %d", + fixture->partner.identity_vdos - 1, + discovery->identity_count); + zassert_mem_equal( + discovery->discovery_vdo, fixture->partner.identity_vdm + 1, + discovery->identity_count * sizeof(*discovery->discovery_vdo), + "Discovered SOP identity ACK did not match"); + zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", + discovery->svid_count); + zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, + "Expected SVID 0x%0000x, got 0x%0000x", + USB_SID_DISPLAYPORT, discovery->svids[0].svid); + zassert_equal(discovery->svids[0].mode_count, 1, + "Expected 1 DP mode, got %d", + discovery->svids[0].mode_count); + zassert_equal(discovery->svids[0].mode_vdo[0], + fixture->partner.modes_vdm[1], + "DP mode VDOs did not match"); +} + +ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) +{ + /* TODO(b/237553647): Test EC-driven mode entry (requires a separate + * config). + */ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + /* Verify host command when VDOs are present. */ + struct ec_params_usb_pd_get_mode_request params = { + .port = TEST_PORT, + .svid_idx = 0, + }; + struct ec_params_usb_pd_get_mode_response response; + struct host_cmd_handler_args args = BUILD_HOST_COMMAND( + EC_CMD_USB_PD_GET_AMODE, 0, response, params); + + zassume_ok(host_command_process(&args), NULL); + zassume_ok(args.result, NULL); + + /* Response should be populated with a DisplayPort VDO */ + zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); + zassert_equal(response.vdo[0], + fixture->partner.modes_vdm[response.opos], NULL); + + /* DPM configures the partner on DP mode entry */ + /* Verify port partner thinks its configured for DisplayPort */ + zassert_true(fixture->partner.displayport_configured, NULL); +} + +ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + /* DPM configures the partner on DP mode entry */ + /* Verify port partner thinks its configured for DisplayPort */ + zassert_true(fixture->partner.displayport_configured, NULL); + + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_EXIT_MODES, 0); + k_sleep(K_SECONDS(1)); + zassert_false(fixture->partner.displayport_configured, NULL); + + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + zassert_true(fixture->partner.displayport_configured, NULL); + + /* Verify that DisplayPort is the active alternate mode. */ + /* TODO(b/235984702): Wrap EC_CMD_USB_PD_GET_AMODE in a function. */ + struct ec_params_usb_pd_get_mode_request params = { + .port = TEST_PORT, + .svid_idx = 0, + }; + struct ec_params_usb_pd_get_mode_response response; + struct host_cmd_handler_args args = BUILD_HOST_COMMAND( + EC_CMD_USB_PD_GET_AMODE, 0, response, params); + + zassume_ok(host_command_process(&args), NULL); + zassume_ok(args.result, NULL); + + /* Response should be populated with a DisplayPort VDO */ + zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); + zassert_equal(response.vdo[0], + fixture->partner.modes_vdm[response.opos], NULL); +} + +ZTEST_SUITE(usbc_alt_mode, drivers_predicate_post_main, usbc_alt_mode_setup, + usbc_alt_mode_before, usbc_alt_mode_after, NULL); + +/* + * When the partner advertises DP mode support but refuses to enter, discovery + * should still work as if the partner were compliant. + */ +ZTEST_F(usbc_alt_mode_dp_unsupported, verify_discovery) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + uint8_t response_buffer[EC_LPC_HOST_PACKET_SIZE]; + struct ec_response_typec_discovery *discovery = + (struct ec_response_typec_discovery *)response_buffer; + host_cmd_typec_discovery(TEST_PORT, TYPEC_PARTNER_SOP, response_buffer, + sizeof(response_buffer)); + + /* The host command does not count the VDM header in identity_count. */ + zassert_equal(discovery->identity_count, + fixture->partner.identity_vdos - 1, + "Expected %d identity VDOs, got %d", + fixture->partner.identity_vdos - 1, + discovery->identity_count); + zassert_mem_equal( + discovery->discovery_vdo, fixture->partner.identity_vdm + 1, + discovery->identity_count * sizeof(*discovery->discovery_vdo), + "Discovered SOP identity ACK did not match"); + zassert_equal(discovery->svid_count, 1, "Expected 1 SVID, got %d", + discovery->svid_count); + zassert_equal(discovery->svids[0].svid, USB_SID_DISPLAYPORT, + "Expected SVID 0x%0000x, got 0x%0000x", + USB_SID_DISPLAYPORT, discovery->svids[0].svid); + zassert_equal(discovery->svids[0].mode_count, 1, + "Expected 1 DP mode, got %d", + discovery->svids[0].mode_count); + zassert_equal(discovery->svids[0].mode_vdo[0], + fixture->partner.modes_vdm[1], + "DP mode VDOs did not match"); +} + +/* + * When the partner advertises DP support but refuses to enter DP mode, the TCPM + * should try once and then give up. + */ +ZTEST_F(usbc_alt_mode_dp_unsupported, verify_displayport_mode_nonentry) +{ + host_cmd_typec_control(TEST_PORT, TYPEC_CONTROL_COMMAND_ENTER_MODE, + TYPEC_MODE_DP); + k_sleep(K_SECONDS(1)); + + zassert_false(fixture->partner.displayport_configured, NULL); + int dp_attempts = + atomic_get(&fixture->partner.displayport_enter_attempts); + zassert_equal(dp_attempts, 1, "Expected 1 DP attempt, got %d", + dp_attempts); +} + +ZTEST_SUITE(usbc_alt_mode_dp_unsupported, drivers_predicate_post_main, + usbc_alt_mode_dp_unsupported_setup, usbc_alt_mode_before, + usbc_alt_mode_after, NULL); -- cgit v1.2.1 From b330c438eed93c2dddecfe767a1bacfca4883227 Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Tue, 12 Jul 2022 16:30:16 -0600 Subject: shuffle_test.sh: Parameterize test target Allow shuffling tests other than test-drivers. Perform minimal argument validation. BUG=none TEST=shuffle_test.sh test-drivers-usbc_alt-mode # Success shuffle_test.sh test-drivers # Error BRANCH=none Signed-off-by: Abe Levkoy Change-Id: Iae5da2accb1d770b449df3392806bf8bd6acf79e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759270 Reviewed-by: Yuval Peress --- util/shuffle_test.sh | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/util/shuffle_test.sh b/util/shuffle_test.sh index 662aaa7bce..6605d35e12 100755 --- a/util/shuffle_test.sh +++ b/util/shuffle_test.sh @@ -6,14 +6,22 @@ set +x -zmake build --clobber test-drivers || exit 1 +if [ $# -ne 2 ]; then + echo "Usage: $0 " + exit 1 +fi + +target=$1 +pattern=$2 + +zmake build --clobber "${target}" || exit 1 -echo "Searching for '${1}'..." +echo "Searching for '${pattern}'..." found_errors=0 loop_count=100 start_time=$(date +%Y-%m-%d_%H.%M.%S) log_dir="/tmp" -EXECUTABLE=./build/zephyr/test-drivers/build-singleimage/zephyr/zephyr.exe +EXECUTABLE=./build/zephyr/${target}/build-singleimage/zephyr/zephyr.exe while [ "${loop_count}" -gt 0 ]; do seed=${RANDOM} log_file_prefix="${log_dir}"/shuffle_"${start_time}"_"${seed}" @@ -21,7 +29,7 @@ while [ "${loop_count}" -gt 0 ]; do echo "[$((100 - loop_count))] Using seed=${seed}" error_count=$(timeout 150s "${EXECUTABLE}" -seed="${seed}" 2>&1 | tee "${log_file_prefix}".log | - grep -c "${1}") + grep -c "${pattern}") status=$? result="0-matches" @@ -33,7 +41,7 @@ while [ "${loop_count}" -gt 0 ]; do result="exit-code-${status}" fi if [ "${error_count}" -gt 0 ]; then - echo " Found ${error_count} errors matching '${1}'" + echo " Found ${error_count} errors matching '${pattern}'" result="${error_count}-matches" fi -- cgit v1.2.1 From 331ea002e16c1209e1eddf57c01400b7ff4ac02e Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 8 Jul 2022 14:22:19 -0600 Subject: ec: Fix some bad formatting and warnings The black formatting revealed some odd formatting. Fixed all errors from cros lint. find . \( -path ./private -prune \) -o -name '*.py' -print | \ xargs cros lint -v |& grep ": E" BRANCH=None BUG=b:238434058 TEST=None Signed-off-by: Jeremy Bettis Change-Id: Ia1d2e9cfb0cd2b7000d15b3b918d24881987673e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749249 Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis --- chip/ish/util/pack_ec.py | 10 ++---- chip/mchp/util/pack_ec.py | 4 --- chip/mchp/util/pack_ec_mec152x.py | 26 ++------------- chip/mchp/util/pack_ec_mec172x.py | 42 +++++++------------------ chip/mec1322/util/pack_ec.py | 4 --- cts/common/board.py | 18 +++++------ cts/cts.py | 4 --- extra/cr50_rma_open/cr50_rma_open.py | 20 ++++++------ extra/stack_analyzer/stack_analyzer.py | 8 ++--- extra/stack_analyzer/stack_analyzer_unittest.py | 6 +--- extra/tigertool/ecusb/__init__.py | 4 --- extra/tigertool/ecusb/pty_driver.py | 8 ++--- extra/tigertool/ecusb/stm32uart.py | 6 +--- extra/tigertool/ecusb/stm32usb.py | 6 +--- extra/tigertool/ecusb/tiny_servo_common.py | 6 +--- extra/tigertool/ecusb/tiny_servod.py | 4 --- extra/tigertool/tigertest.py | 4 --- extra/tigertool/tigertool.py | 4 --- extra/usb_power/convert_power_log_board.py | 6 +--- extra/usb_power/convert_servo_ina.py | 4 --- extra/usb_power/powerlog.py | 15 +++------ extra/usb_power/powerlog_unittest.py | 6 +--- extra/usb_power/stats_manager.py | 6 +--- extra/usb_power/stats_manager_unittest.py | 6 +--- extra/usb_serial/console.py | 13 ++------ extra/usb_updater/fw_update.py | 12 ++----- extra/usb_updater/servo_updater.py | 6 +--- util/config_option_check.py | 4 --- util/ec3po/console.py | 16 +++++----- util/ec3po/console_unittest.py | 20 ++++++------ util/ec3po/interpreter_unittest.py | 24 +++++++------- util/kconfiglib.py | 3 ++ util/run_ects.py | 6 +--- util/uart_stress_tester.py | 6 +--- util/unpack_ftb.py | 4 --- zephyr/zmake/tests/conftest.py | 4 +-- zephyr/zmake/tests/test_build_config.py | 6 ++-- zephyr/zmake/tests/test_generate_readme.py | 2 +- zephyr/zmake/tests/test_modules.py | 4 +-- zephyr/zmake/tests/test_packers.py | 6 ++-- zephyr/zmake/tests/test_project.py | 6 ++-- zephyr/zmake/tests/test_reexec.py | 2 +- zephyr/zmake/tests/test_toolchains.py | 2 +- zephyr/zmake/tests/test_util.py | 6 ++-- zephyr/zmake/tests/test_zmake.py | 4 +-- 45 files changed, 112 insertions(+), 271 deletions(-) diff --git a/chip/ish/util/pack_ec.py b/chip/ish/util/pack_ec.py index 8dde6ab6a9..e7bb0ce74b 100755 --- a/chip/ish/util/pack_ec.py +++ b/chip/ish/util/pack_ec.py @@ -4,10 +4,6 @@ # Copyright 2019 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary with manifest header according to # Based on 607297_Host_ISH_Firmware_Load_Chrome_OS_SAS_Rev0p5.pdf, @@ -34,8 +30,7 @@ def parseargs(): parser.add_argument( "-k", "--kernel", - help="EC kernel binary to pack, \ - usually ec.RW.bin or ec.RW.flat.", + help="EC kernel binary to pack, usually ec.RW.bin or ec.RW.flat.", required=True, ) parser.add_argument( @@ -44,8 +39,7 @@ def parseargs(): parser.add_argument( "-a", "--aon", - help="EC aontask binary to pack, \ - usually ish_aontask.bin.", + help="EC aontask binary to pack, usually ish_aontask.bin.", required=False, ) parser.add_argument( diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py index 15be16c0d4..85aad94bd6 100755 --- a/chip/mchp/util/pack_ec.py +++ b/chip/mchp/util/pack_ec.py @@ -3,10 +3,6 @@ # Copyright 2013 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary into SPI flash image for MEC17xx # Based on MEC170x_ROM_Description.pdf DS00002225C (07-28-17). diff --git a/chip/mchp/util/pack_ec_mec152x.py b/chip/mchp/util/pack_ec_mec152x.py index 89f90f5394..8ef7b3992c 100755 --- a/chip/mchp/util/pack_ec_mec152x.py +++ b/chip/mchp/util/pack_ec_mec152x.py @@ -3,10 +3,6 @@ # Copyright 2021 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary into SPI flash image for MEC152x # Based on MEC1521/MEC1523_ROM_Description.pdf @@ -217,13 +213,6 @@ def PadZeroTo(data, size): data.extend(b"\0" * (size - len(data))) -# -# Boot-ROM SPI image encryption not used with Chromebooks -# -def EncryptPayload(args, chip_dict, payload): - return None - - # # Build SPI image header for MEC152x # MEC152x image header size = 320(0x140) bytes @@ -508,9 +497,6 @@ def gen_test_ecrw(pldrw): def parseargs(): - # TODO I commented this out. Why? - rpath = os.path.dirname(os.path.relpath(__file__)) - parser = argparse.ArgumentParser() parser.add_argument( "-i", @@ -778,21 +764,13 @@ def main(): header = BuildHeader2(args, chip_dict, lfw_ecro_len, LOAD_ADDR, lfw_ecro_entry) printByteArrayAsHex(header, "Header(lfw_ecro)") - # If payload encryption used then encrypt payload and - # generate Payload Key Header. If encryption not used - # payload is not modified and the method returns None - encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) - printByteArrayAsHex(encryption_key_header, "LFW + EC_RO encryption_key_header") - ec_info_block = GenEcInfoBlock(args, chip_dict) printByteArrayAsHex(ec_info_block, "EC Info Block") cosignature = GenCoSignature(args, chip_dict, lfw_ecro) printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") - trailer = GenTrailer( - args, chip_dict, lfw_ecro, encryption_key_header, ec_info_block, cosignature - ) + trailer = GenTrailer(args, chip_dict, lfw_ecro, None, ec_info_block, cosignature) printByteArrayAsHex(trailer, "LFW + EC_RO trailer") @@ -883,7 +861,7 @@ def main(): assert rw_offset >= offset, print( """Offset of EC_RW at {0:08x} overlaps end - of EC_RO at {0:08x}""".format( + of EC_RO at {1:08x}""".format( rw_offset, offset ) ) diff --git a/chip/mchp/util/pack_ec_mec172x.py b/chip/mchp/util/pack_ec_mec172x.py index bd5ff6edba..25a4cb7ed1 100755 --- a/chip/mchp/util/pack_ec_mec172x.py +++ b/chip/mchp/util/pack_ec_mec172x.py @@ -3,10 +3,6 @@ # Copyright 2021 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary into SPI flash image for MEC172x # Based on MEC172x_ROM_Description.pdf revision 6/8/2020 @@ -121,8 +117,9 @@ def GetEntryPoint(payload_file): return int.from_bytes(s, byteorder="little") -def GetPayloadFromOffset(payload_file, offset, padsize): - """Read payload and pad it to padsize.""" +def GetPayloadFromOffset(payload_file, offset, chip_dict): + """Read payload and pad it to chip_dict["PAD_SIZE"].""" + padsize = chip_dict["PAD_SIZE"] with open(payload_file, "rb") as f: f.seek(offset) payload = bytearray(f.read()) @@ -134,15 +131,15 @@ def GetPayloadFromOffset(payload_file, offset, padsize): ) if rem_len: - payload += PAYLOAD_PAD_BYTE * (padsize - rem_len) + payload += chip_dict["PAYLOAD_PAD_BYTE"] * (padsize - rem_len) debug_print("GetPayload: Added {0} padding bytes".format(padsize - rem_len)) return payload -def GetPayload(payload_file, padsize): - """Read payload and pad it to padsize""" - return GetPayloadFromOffset(payload_file, 0, padsize) +def GetPayload(payload_file, chip_dict): + """Read payload and pad it to chip_dict["PAD_SIZE"]""" + return GetPayloadFromOffset(payload_file, 0, chip_dict) def GetPublicKey(pem_file): @@ -225,13 +222,6 @@ def PadZeroTo(data, size): data.extend(b"\0" * (size - len(data))) -# -# Boot-ROM SPI image encryption not used with Chromebooks -# -def EncryptPayload(args, chip_dict, payload): - return None - - # # Build SPI image header for MEC172x # MEC172x image header size = 320(0x140) bytes @@ -797,16 +787,16 @@ def main(): rorofile = PacklfwRoImage(args.input, args.loader_file, args.image_size) debug_print("Temporary file containing LFW + EC_RO is ", rorofile) - lfw_ecro = GetPayload(rorofile, chip_dict["PAD_SIZE"]) + lfw_ecro = GetPayload(rorofile, chip_dict) lfw_ecro_len = len(lfw_ecro) debug_print("Padded LFW + EC_RO length = ", hex(lfw_ecro_len)) # SPI test mode compute CRC32 of EC_RO and store in last 4 bytes if args.test_spi: - crc32_ecro = zlib.crc32(bytes(lfw_ecro[LFW_SIZE:-4])) + crc32_ecro = zlib.crc32(bytes(lfw_ecro[args.lfw_size : -4])) crc32_ecro_bytes = crc32_ecro.to_bytes(4, byteorder="little") lfw_ecro[-4:] = crc32_ecro_bytes - debug_print("ecro len = ", hex(len(lfw_ecro) - LFW_SIZE)) + debug_print("ecro len = ", hex(len(lfw_ecro) - args.lfw_size)) debug_print("CRC32(ecro-4) = ", hex(crc32_ecro)) # Reads entry point from offset 4 of file. @@ -825,21 +815,13 @@ def main(): header = BuildHeader2(args, chip_dict, lfw_ecro_len, args.load_addr, lfw_ecro_entry) printByteArrayAsHex(header, "Header(lfw_ecro)") - # If payload encryption used then encrypt payload and - # generate Payload Key Header. If encryption not used - # payload is not modified and the method returns None - encryption_key_header = EncryptPayload(args, chip_dict, lfw_ecro) - printByteArrayAsHex(encryption_key_header, "LFW + EC_RO encryption_key_header") - ec_info_block = GenEcInfoBlock(args, chip_dict) printByteArrayAsHex(ec_info_block, "EC Info Block") cosignature = GenCoSignature(args, chip_dict, lfw_ecro) printByteArrayAsHex(cosignature, "LFW + EC_RO cosignature") - trailer = GenTrailer( - args, chip_dict, lfw_ecro, encryption_key_header, ec_info_block, cosignature - ) + trailer = GenTrailer(args, chip_dict, lfw_ecro, None, ec_info_block, cosignature) printByteArrayAsHex(trailer, "LFW + EC_RO trailer") @@ -851,7 +833,7 @@ def main(): debug_print("args.input = ", args.input) debug_print("args.image_size = ", hex(args.image_size)) - ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict["PAD_SIZE"]) + ecrw = GetPayloadFromOffset(args.input, args.image_size, chip_dict) debug_print("type(ecrw) is ", type(ecrw)) debug_print("len(ecrw) is ", hex(len(ecrw))) diff --git a/chip/mec1322/util/pack_ec.py b/chip/mec1322/util/pack_ec.py index 736f9efcac..44ba6e7854 100755 --- a/chip/mec1322/util/pack_ec.py +++ b/chip/mec1322/util/pack_ec.py @@ -3,10 +3,6 @@ # Copyright 2013 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script to pack EC binary into SPI flash image for MEC1322 # Based on MEC1322_ROM_Doc_Rev0.5.pdf. diff --git a/cts/common/board.py b/cts/common/board.py index f62d7bdfc5..68071f0b28 100644 --- a/cts/common/board.py +++ b/cts/common/board.py @@ -1,10 +1,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # Note: This is a py2/3 compatible file. @@ -15,7 +11,7 @@ import shutil import subprocess as sp from abc import ABCMeta, abstractmethod -import serial +import serial # pylint:disable=import-error import six OCD_SCRIPT_DIR = "/usr/share/openocd/scripts" @@ -77,12 +73,16 @@ class Board(six.with_metaclass(ABCMeta, object)): self.hla_serial = hla_serial self.tty_port = None self.tty = None + self.log_dir = None + self.openocd_log = os.devnull + self.build_log = os.devnull def reset_log_dir(self): """Reset log directory.""" - if os.path.isdir(self.log_dir): - shutil.rmtree(self.log_dir) - os.makedirs(self.log_dir) + if self.log_dir: + if os.path.isdir(self.log_dir): + shutil.rmtree(self.log_dir) + os.makedirs(self.log_dir) @staticmethod def get_stlink_serials(): @@ -394,7 +394,7 @@ class DeviceUnderTest(Board): # If len(dut) is 0 then your dut doesn't use an st-link device, so we # don't have to worry about its serial number if not dut: - msg = "Failed to find serial for DUT.\n" "Is " + self.board + " connected?" + msg = "Failed to find serial for DUT.\nIs " + self.board + " connected?" raise RuntimeError(msg) if len(dut) > 1: msg = ( diff --git a/cts/cts.py b/cts/cts.py index ebc526c701..b29c849c0c 100755 --- a/cts/cts.py +++ b/cts/cts.py @@ -3,10 +3,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # A script which builds, flashes, and runs EC CTS # diff --git a/extra/cr50_rma_open/cr50_rma_open.py b/extra/cr50_rma_open/cr50_rma_open.py index b77b8f3dbb..47cb7cd6e3 100755 --- a/extra/cr50_rma_open/cr50_rma_open.py +++ b/extra/cr50_rma_open/cr50_rma_open.py @@ -50,16 +50,14 @@ import subprocess import sys import time -import serial +import serial # pylint:disable=import-error SCRIPT_VERSION = 5 CCD_IS_UNRESTRICTED = 1 << 0 WP_IS_DISABLED = 1 << 1 TESTLAB_IS_ENABLED = 1 << 2 RMA_OPENED = CCD_IS_UNRESTRICTED | WP_IS_DISABLED -URL = ( - "https://www.google.com/chromeos/partner/console/cr50reset?" "challenge=%s&hwid=%s" -) +URL = "https://www.google.com/chromeos/partner/console/cr50reset?challenge=%s&hwid=%s" RMA_SUPPORT_PROD = "0.3.3" RMA_SUPPORT_PREPVT = "0.4.5" DEV_MODE_OPEN_PROD = "0.3.9" @@ -398,7 +396,7 @@ class RMAOpen(object): self.send_cmd_get_output("ccd open") logging.info("Enabling testlab mode reqires pressing the power button.") logging.info( - "Once the process starts keep tapping the power button " "for 10 seconds." + "Once the process starts keep tapping the power button for 10 seconds." ) input("Press Enter when you're ready to start...") end_time = time.time() + 15 @@ -473,11 +471,11 @@ class RMAOpen(object): rma_support, ) if not self.is_prepvt and self._running_version_is_older(TESTLAB_PROD): - raise ValueError("Update cr50. No testlab support in old prod " "images.") + raise ValueError("Update cr50. No testlab support in old prod images.") if self._running_version_is_older(rma_support): raise ValueError( - "%s does not have RMA support. Update to at " - "least %s" % (version, rma_support) + "%s does not have RMA support. Update to at least %s" + % (version, rma_support) ) def _running_version_is_older(self, target_ver): @@ -538,7 +536,7 @@ class RMAOpen(object): return logging.warning(DEBUG_CONNECTION) raise ValueError( - "Found USB device, but could not communicate with " "cr50 console" + "Found USB device, but could not communicate with cr50 console" ) def print_platform_info(self): @@ -578,7 +576,7 @@ class RMAOpen(object): logging.info("CCD is still restricted.") logging.info("Run cr50_rma_open.py -g -i $HWID to generate a url") logging.info( - "Run cr50_rma_open.py -a $AUTHCODE to open cr50 with " "an authcode" + "Run cr50_rma_open.py -a $AUTHCODE to open cr50 with an authcode" ) elif not self.check(WP_IS_DISABLED): logging.info("WP is still enabled.") @@ -692,7 +690,7 @@ def main(argv): "open. Run through the rma open process first" ) if tried_authcode: - logging.warning("RMA Open did not disable write protect. File a " "bug") + logging.warning("RMA Open did not disable write protect. File a bug") logging.warning("Trying to disable it manually") cr50_rma_open.wp_disable() diff --git a/extra/stack_analyzer/stack_analyzer.py b/extra/stack_analyzer/stack_analyzer.py index 17b2651972..9feb2423c9 100755 --- a/extra/stack_analyzer/stack_analyzer.py +++ b/extra/stack_analyzer/stack_analyzer.py @@ -2,10 +2,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Statically analyze stack usage of EC firmware. @@ -26,7 +22,7 @@ import os import re import subprocess -import yaml +import yaml # pylint:disable=import-error SECTION_RO = "RO" SECTION_RW = "RW" @@ -1165,7 +1161,7 @@ class StackAnalyzer(object): if not name: raise StackAnalyzerError( - "Cannot find function for address %s.", hex(val) + "Cannot find function for address %s." % hex(val) ) output.append((name, None, None)) diff --git a/extra/stack_analyzer/stack_analyzer_unittest.py b/extra/stack_analyzer/stack_analyzer_unittest.py index ad2837a8a4..228b7e010e 100755 --- a/extra/stack_analyzer/stack_analyzer_unittest.py +++ b/extra/stack_analyzer/stack_analyzer_unittest.py @@ -2,10 +2,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Tests for Stack Analyzer classes and functions.""" @@ -15,7 +11,7 @@ import os import subprocess import unittest -import mock +import mock # pylint:disable=import-error import stack_analyzer as sa diff --git a/extra/tigertool/ecusb/__init__.py b/extra/tigertool/ecusb/__init__.py index 7a48fdb360..7228f2b911 100644 --- a/extra/tigertool/ecusb/__init__.py +++ b/extra/tigertool/ecusb/__init__.py @@ -1,9 +1,5 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes __all__ = ["tiny_servo_common", "stm32usb", "stm32uart", "pty_driver"] diff --git a/extra/tigertool/ecusb/pty_driver.py b/extra/tigertool/ecusb/pty_driver.py index 037ff8d529..c87378b94d 100644 --- a/extra/tigertool/ecusb/pty_driver.py +++ b/extra/tigertool/ecusb/pty_driver.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """ptyDriver class @@ -19,8 +15,8 @@ import fcntl import os import time -import pexpect -from pexpect import fdpexpect +import pexpect # pylint:disable=import-error +from pexpect import fdpexpect # pylint:disable=import-error # Expecting a result in 3 seconds is plenty even for slow platforms. DEFAULT_UART_TIMEOUT = 3 diff --git a/extra/tigertool/ecusb/stm32uart.py b/extra/tigertool/ecusb/stm32uart.py index 5794bd091b..a6fa73970d 100644 --- a/extra/tigertool/ecusb/stm32uart.py +++ b/extra/tigertool/ecusb/stm32uart.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Allow creation of uart/console interface via stm32 usb endpoint.""" @@ -18,7 +14,7 @@ import threading import time import tty -import usb +import usb # pylint:disable=import-error from . import stm32usb diff --git a/extra/tigertool/ecusb/stm32usb.py b/extra/tigertool/ecusb/stm32usb.py index 4b2b23fbac..e8a0bc4f9b 100644 --- a/extra/tigertool/ecusb/stm32usb.py +++ b/extra/tigertool/ecusb/stm32usb.py @@ -1,14 +1,10 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Allows creation of an interface via stm32 usb.""" -import usb +import usb # pylint:disable=import-error class SusbError(Exception): diff --git a/extra/tigertool/ecusb/tiny_servo_common.py b/extra/tigertool/ecusb/tiny_servo_common.py index 599bae80dc..889abcc0a0 100644 --- a/extra/tigertool/ecusb/tiny_servo_common.py +++ b/extra/tigertool/ecusb/tiny_servo_common.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Utilities for using lightweight console functions.""" @@ -15,7 +11,7 @@ import sys import time import six -import usb +import usb # pylint:disable=import-error from . import pty_driver, stm32uart diff --git a/extra/tigertool/ecusb/tiny_servod.py b/extra/tigertool/ecusb/tiny_servod.py index ca5ca63f31..d5d092c996 100644 --- a/extra/tigertool/ecusb/tiny_servod.py +++ b/extra/tigertool/ecusb/tiny_servod.py @@ -1,10 +1,6 @@ # Copyright 2020 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Helper class to facilitate communication to servo ec console.""" diff --git a/extra/tigertool/tigertest.py b/extra/tigertool/tigertest.py index 8f8b2c7f03..924ec8c97c 100755 --- a/extra/tigertool/tigertest.py +++ b/extra/tigertool/tigertest.py @@ -2,10 +2,6 @@ # Copyright 2022 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Smoke test of tigertool binary.""" diff --git a/extra/tigertool/tigertool.py b/extra/tigertool/tigertool.py index 37b7b01495..241e7fe155 100755 --- a/extra/tigertool/tigertool.py +++ b/extra/tigertool/tigertool.py @@ -2,10 +2,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Script to control tigertail USB-C Mux board.""" diff --git a/extra/usb_power/convert_power_log_board.py b/extra/usb_power/convert_power_log_board.py index c1b25f57db..159b4621d7 100644 --- a/extra/usb_power/convert_power_log_board.py +++ b/extra/usb_power/convert_power_log_board.py @@ -2,10 +2,6 @@ # Copyright 2018 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """ Program to convert sweetberry config to servod config template. @@ -19,7 +15,7 @@ import json import os import sys -from powerlog import Spower +from powerlog import Spower # pylint:disable=import-error def fetch_records(board_file): diff --git a/extra/usb_power/convert_servo_ina.py b/extra/usb_power/convert_servo_ina.py index 6ccd474e6c..c18b7368dc 100755 --- a/extra/usb_power/convert_servo_ina.py +++ b/extra/usb_power/convert_servo_ina.py @@ -2,10 +2,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Program to convert power logging config from a servo_ina device to a sweetberry config. diff --git a/extra/usb_power/powerlog.py b/extra/usb_power/powerlog.py index d893e5c6b9..44dd6ec12f 100755 --- a/extra/usb_power/powerlog.py +++ b/extra/usb_power/powerlog.py @@ -2,10 +2,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Program to fetch power logging data from a sweetberry device or other usb device that exports a USB power logging interface. @@ -27,8 +23,8 @@ import time import traceback from distutils import sysconfig -import usb -from stats_manager import StatsManager +import usb # pylint:disable=import-error +from stats_manager import StatsManager # pylint:disable=import-error # Directory where hdctools installs configuration files into. LIB_DIR = os.path.join(sysconfig.get_python_lib(standard_lib=False), "servo", "data") @@ -182,11 +178,7 @@ class Spower(object): if dev is None: raise Exception("Power", "USB device(%s) not found" % serialname) else: - try: - dev = dev_list[0] - except TypeError: - # Incompatible pyUsb version. - dev = dev_list.next() + dev = dev_list[0] self._logger.debug("Found USB device: %04x:%04x", vendor, product) self._dev = dev @@ -728,6 +720,7 @@ class powerlog(object): if integration_us != integration_us_new: raise Exception( "FAIL", + # pylint:disable=bad-string-format-type "Integration on A: %dus != integration on B %dus" % (integration_us, integration_us_new), ) diff --git a/extra/usb_power/powerlog_unittest.py b/extra/usb_power/powerlog_unittest.py index 693826c16d..220ff350d2 100644 --- a/extra/usb_power/powerlog_unittest.py +++ b/extra/usb_power/powerlog_unittest.py @@ -1,10 +1,6 @@ # Copyright 2018 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Unit tests for powerlog.""" @@ -13,7 +9,7 @@ import shutil import tempfile import unittest -import powerlog +from usb_power import powerlog class TestPowerlog(unittest.TestCase): diff --git a/extra/usb_power/stats_manager.py b/extra/usb_power/stats_manager.py index 633312311d..0f92916251 100644 --- a/extra/usb_power/stats_manager.py +++ b/extra/usb_power/stats_manager.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Calculates statistics for lists of data and pretty print them.""" @@ -18,7 +14,7 @@ import logging import math import os -import numpy +import numpy # pylint:disable=import-error STATS_PREFIX = "@@" NAN_TAG = "*" diff --git a/extra/usb_power/stats_manager_unittest.py b/extra/usb_power/stats_manager_unittest.py index 37a472af98..2a7317546c 100644 --- a/extra/usb_power/stats_manager_unittest.py +++ b/extra/usb_power/stats_manager_unittest.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Unit tests for StatsManager.""" @@ -17,7 +13,7 @@ import shutil import tempfile import unittest -import stats_manager +import stats_manager # pylint:disable=import-error class TestStatsManager(unittest.TestCase): diff --git a/extra/usb_serial/console.py b/extra/usb_serial/console.py index c08cb72092..839330d86a 100755 --- a/extra/usb_serial/console.py +++ b/extra/usb_serial/console.py @@ -2,10 +2,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Allow creation of uart/console interface via usb google serial endpoint.""" @@ -23,7 +19,7 @@ import time import tty try: - import usb + import usb # pylint:disable=import-error except ModuleNotFoundError: print("import usb failed") print("try running these commands:") @@ -113,12 +109,7 @@ class Susb: try: dev = dev_list[0] except: - try: - dev = dev_list.next() - except: - raise SusbError( - "USB device %04x:%04x not found" % (vendor, product) - ) + raise SusbError("USB device %04x:%04x not found" % (vendor, product)) # If we can't set configuration, it's already been set. try: diff --git a/extra/usb_updater/fw_update.py b/extra/usb_updater/fw_update.py index f05797bfb6..8658d92c48 100755 --- a/extra/usb_updater/fw_update.py +++ b/extra/usb_updater/fw_update.py @@ -2,10 +2,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # Upload firmware over USB # Note: This is a py2/3 compatible file. @@ -21,7 +17,8 @@ import sys import time from pprint import pprint -import usb +import usb # pylint:disable=import-error +from ecusb.stm32usb import SusbError debug = False @@ -91,10 +88,7 @@ class Supdate(object): if dev is None: raise SusbError("USB device(%s) not found" % serialname) else: - try: - dev = dev_list[0] - except: - dev = dev_list.next() + dev = dev_list[0] debuglog("Found stm32: %04x:%04x" % (vendor, product)) self._dev = dev diff --git a/extra/usb_updater/servo_updater.py b/extra/usb_updater/servo_updater.py index 5402af70aa..7fa4608289 100755 --- a/extra/usb_updater/servo_updater.py +++ b/extra/usb_updater/servo_updater.py @@ -2,10 +2,6 @@ # Copyright 2016 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # Note: This is a py2/3 compatible file. @@ -410,7 +406,7 @@ def main(): # If the user only cares about the information then just print it here, # and exit. if args.print_only: - output = ("board: %s\n" "channel: %s\n" "firmware: %s") % ( + output = ("board: %s\nchannel: %s\nfirmware: %s") % ( args.board, args.channel, newvers, diff --git a/util/config_option_check.py b/util/config_option_check.py index 0b05b64091..8263e61709 100755 --- a/util/config_option_check.py +++ b/util/config_option_check.py @@ -2,10 +2,6 @@ # Copyright 2015 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Configuration Option Checker. diff --git a/util/ec3po/console.py b/util/ec3po/console.py index 33fa5a6775..3b3c1c89f5 100755 --- a/util/ec3po/console.py +++ b/util/ec3po/console.py @@ -776,9 +776,7 @@ class Console(object): self.input_buffer_pos += count else: - raise AssertionError( - ("The only valid directions are 'left' and " "'right'") - ) + raise AssertionError(("The only valid directions are 'left' and 'right'")) self.logger.debug("input_buffer_pos: %d", self.input_buffer_pos) # Move the cursor. @@ -1149,11 +1147,11 @@ def main(argv): """ # Set up argument parser. parser = argparse.ArgumentParser( - description=("Start interactive EC console " "and interpreter.") + description=("Start interactive EC console and interpreter.") ) parser.add_argument( "ec_uart_pty", - help=("The full PTY name that the EC UART" " is present on. eg: /dev/pts/12"), + help=("The full PTY name that the EC UART is present on. eg: /dev/pts/12"), ) parser.add_argument( "--log-level", default="info", help="info, debug, warning, error, or critical" @@ -1181,7 +1179,7 @@ def main(argv): # entry. logging.basicConfig( level=log_level, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create some pipes to communicate between the interpreter and the console. @@ -1213,7 +1211,11 @@ def main(argv): ) # Create a console. console = Console( - controller_pty, os.ttyname(user_pty), cmd_pipe_interactive, dbg_pipe_interactive + controller_pty, + os.ttyname(user_pty), + os.ttyname(controller_pty), + cmd_pipe_interactive, + dbg_pipe_interactive, ) # Start serving the console. v = threadproc_shim.Value(ctypes.c_bool, False) diff --git a/util/ec3po/console_unittest.py b/util/ec3po/console_unittest.py index 41ae324ef4..45ab2ff44c 100755 --- a/util/ec3po/console_unittest.py +++ b/util/ec3po/console_unittest.py @@ -14,7 +14,7 @@ import logging import tempfile import unittest -import mock +import mock # pylint:disable=import-error import six from ec3po import console, interpreter, threadproc_shim @@ -188,7 +188,7 @@ class TestConsoleEditingMethods(unittest.TestCase): # Setup logging with a timestamp, the module, and the log level. logging.basicConfig( level=logging.DEBUG, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create a temp file and set both the controller and peripheral PTYs to the @@ -1101,7 +1101,7 @@ class TestConsoleCompatibility(unittest.TestCase): # Setup logging with a timestamp, the module, and the log level. logging.basicConfig( level=logging.DEBUG, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create a temp file and set both the controller and peripheral PTYs to the # file to create a loopback. @@ -1207,7 +1207,7 @@ class TestConsoleCompatibility(unittest.TestCase): # At this point, we should have negotiated to enhanced. self.assertTrue( - self.console.enhanced_ec, msg=("Did not negotiate to " "enhanced EC image.") + self.console.enhanced_ec, msg=("Did not negotiate to enhanced EC image.") ) # The command would have been dropped however, so verify this... @@ -1259,7 +1259,7 @@ class TestConsoleCompatibility(unittest.TestCase): # Verify this. self.assertFalse( self.console.enhanced_ec, - msg=("Did not negotiate to" "non-enhanced EC image."), + msg=("Did not negotiate to non-enhanced EC image."), ) CheckInputBuffer(self, b"") CheckInputBufferPosition(self, 0) @@ -1398,7 +1398,7 @@ class TestOOBMConsoleCommands(unittest.TestCase): # Setup logging with a timestamp, the module, and the log level. logging.basicConfig( level=logging.DEBUG, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create a temp file and set both the controller and peripheral PTYs to the # file to create a loopback. @@ -1470,7 +1470,7 @@ class TestOOBMConsoleCommands(unittest.TestCase): # The EC image should be assumed to be not enhanced. self.assertFalse( self.console.enhanced_ec, - "The image should be assumed to" " be NOT enhanced.", + "The image should be assumed to be NOT enhanced.", ) # Reset the mocks. @@ -1520,7 +1520,7 @@ class TestOOBMConsoleCommands(unittest.TestCase): # The EC image should be assumed to be not enhanced. self.assertFalse( self.console.enhanced_ec, - "The image should be assumed to" " be NOT enhanced.", + "The image should be assumed to be NOT enhanced.", ) # Reset the mocks. @@ -1575,7 +1575,7 @@ class TestOOBMConsoleCommands(unittest.TestCase): # The EC image should be assumed to be not enhanced. self.assertFalse( self.console.enhanced_ec, - "The image should be assumed to" " be NOT enhanced.", + "The image should be assumed to be NOT enhanced.", ) # Now, let's try to assume that the image is enhanced while still disabling @@ -1623,7 +1623,7 @@ class TestOOBMConsoleCommands(unittest.TestCase): # The EC image should be assumed to be enhanced. self.assertTrue( - self.console.enhanced_ec, "The image should be" " assumed to be enhanced." + self.console.enhanced_ec, "The image should be assumed to be enhanced." ) diff --git a/util/ec3po/interpreter_unittest.py b/util/ec3po/interpreter_unittest.py index 509b90f667..73188fab9f 100755 --- a/util/ec3po/interpreter_unittest.py +++ b/util/ec3po/interpreter_unittest.py @@ -13,7 +13,7 @@ import logging import tempfile import unittest -import mock +import mock # pylint:disable=import-error import six from ec3po import interpreter, threadproc_shim @@ -32,7 +32,7 @@ class TestEnhancedECBehaviour(unittest.TestCase): # Setup logging with a timestamp, the module, and the log level. logging.basicConfig( level=logging.DEBUG, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create a tempfile that would represent the EC UART PTY. @@ -226,7 +226,7 @@ class TestEnhancedECBehaviour(unittest.TestCase): # enhanced. self.assertFalse( self.itpr.enhanced_ec, - msg=("State of enhanced_ec upon" " init is not False."), + msg=("State of enhanced_ec upon init is not False."), ) # Assume an interrogation request comes in from the user. @@ -238,7 +238,7 @@ class TestEnhancedECBehaviour(unittest.TestCase): # The state of enhanced_ec should not be changed yet because we haven't # received a valid response yet. self.assertFalse( - self.itpr.enhanced_ec, msg=("State of enhanced_ec is " "not False.") + self.itpr.enhanced_ec, msg=("State of enhanced_ec is not False.") ) # Assume that the EC responds with an EC_ACK. @@ -247,9 +247,7 @@ class TestEnhancedECBehaviour(unittest.TestCase): # Now, the interrogation should be complete and we should know that the # current EC image is enhanced. - self.assertFalse( - self.itpr.interrogating, msg=("interrogating should be " "False") - ) + self.assertFalse(self.itpr.interrogating, msg=("interrogating should be False")) self.assertTrue(self.itpr.enhanced_ec, msg="enhanced_ec sholud be True") # Now let's perform another interrogation, but pretend that the EC ignores @@ -281,7 +279,7 @@ class TestUARTDisconnection(unittest.TestCase): # Setup logging with a timestamp, the module, and the log level. logging.basicConfig( level=logging.DEBUG, - format=("%(asctime)s - %(module)s -" " %(levelname)s - %(message)s"), + format=("%(asctime)s - %(module)s - %(levelname)s - %(message)s"), ) # Create a tempfile that would represent the EC UART PTY. @@ -307,7 +305,7 @@ class TestUARTDisconnection(unittest.TestCase): # First, check that interpreter is initialized to connected. self.assertTrue( self.itpr.connected, - ("The interpreter should be" " initialized in a connected state"), + ("The interpreter should be initialized in a connected state"), ) def test_DisconnectStopsECTraffic(self): @@ -318,7 +316,7 @@ class TestUARTDisconnection(unittest.TestCase): # Verify interpreter is disconnected from EC. self.assertFalse( - self.itpr.connected, ("The interpreter should be" "disconnected.") + self.itpr.connected, ("The interpreter should be disconnected.") ) # Verify that the EC UART is no longer a member of the inputs. The # interpreter will never pull data from the EC if it's not a member of the @@ -335,7 +333,7 @@ class TestUARTDisconnection(unittest.TestCase): # Verify interpreter is disconnected from EC. self.assertFalse( - self.itpr.connected, ("The interpreter should be" "disconnected.") + self.itpr.connected, ("The interpreter should be disconnected.") ) # Verify that the EC UART is no longer a member of the inputs nor outputs. self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) @@ -372,7 +370,7 @@ class TestUARTDisconnection(unittest.TestCase): # Verify interpreter is disconnected. self.assertFalse( - self.itpr.connected, ("The interpreter should be" "disconnected.") + self.itpr.connected, ("The interpreter should be disconnected.") ) # Verify that the EC UART is no longer a member of the inputs nor outputs. self.assertFalse(self.itpr.ec_uart_pty in self.itpr.inputs) @@ -385,7 +383,7 @@ class TestUARTDisconnection(unittest.TestCase): self.itpr.HandleUserData() # Verify interpreter is connected. - self.assertTrue(self.itpr.connected, ("The interpreter should be" "connected.")) + self.assertTrue(self.itpr.connected, ("The interpreter should be connected.")) # Verify that the EC UART is now a member of the inputs. self.assertTrue(self.itpr.ec_uart_pty in self.itpr.inputs) # Since we have issued no commands during the disconnected state, no diff --git a/util/kconfiglib.py b/util/kconfiglib.py index a0033bba2d..dabd03d8ca 100644 --- a/util/kconfiglib.py +++ b/util/kconfiglib.py @@ -1,6 +1,9 @@ # Copyright (c) 2011-2019, Ulf Magnusson # SPDX-License-Identifier: ISC +# Third-party code, ignore pylint problems +# pylint:disable=all + """ Overview ======== diff --git a/util/run_ects.py b/util/run_ects.py index 9293f60779..cf32184462 100644 --- a/util/run_ects.py +++ b/util/run_ects.py @@ -1,10 +1,6 @@ # Copyright 2017 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """Run all eCTS tests and publish results.""" @@ -44,7 +40,7 @@ class CtsRunner(object): def run(self, tests): for test in tests: - logging.info("Running", test, "test.") + logging.info("Running %s test.", test) self.run_test(test) def sync(self): diff --git a/util/uart_stress_tester.py b/util/uart_stress_tester.py index a89fe730c9..c44262016c 100755 --- a/util/uart_stress_tester.py +++ b/util/uart_stress_tester.py @@ -3,10 +3,6 @@ # Copyright 2019 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes """ChromeOS Uart Stress Test @@ -32,7 +28,7 @@ import sys import threading import time -import serial +import serial # pylint:disable=import-error BAUDRATE = 115200 # Default baudrate setting for UART port CROS_USERNAME = "root" # Account name to login to ChromeOS diff --git a/util/unpack_ftb.py b/util/unpack_ftb.py index a68662d82b..04ba0ed538 100755 --- a/util/unpack_ftb.py +++ b/util/unpack_ftb.py @@ -2,10 +2,6 @@ # Copyright 2018 The Chromium OS Authors. All rights reserved. # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -# -# Ignore indention messages, since legacy scripts use 2 spaces instead of 4. -# pylint: disable=bad-indentation,docstring-section-indent -# pylint: disable=docstring-trailing-quotes # Note: This is a py2/3 compatible file. diff --git a/zephyr/zmake/tests/conftest.py b/zephyr/zmake/tests/conftest.py index be1de01401..9c10c88b31 100644 --- a/zephyr/zmake/tests/conftest.py +++ b/zephyr/zmake/tests/conftest.py @@ -7,8 +7,8 @@ import os import pathlib -import hypothesis -import pytest +import hypothesis # pylint:disable=import-error +import pytest # pylint:disable=import-error import zmake.zmake as zm hypothesis.settings.register_profile( diff --git a/zephyr/zmake/tests/test_build_config.py b/zephyr/zmake/tests/test_build_config.py index f79ed1f8a0..88291cbd05 100644 --- a/zephyr/zmake/tests/test_build_config.py +++ b/zephyr/zmake/tests/test_build_config.py @@ -10,9 +10,9 @@ import pathlib import string import tempfile -import hypothesis -import hypothesis.strategies as st -import pytest +import hypothesis # pylint:disable=import-error +import hypothesis.strategies as st # pylint:disable=import-error +import pytest # pylint:disable=import-error import zmake.jobserver import zmake.util as util from zmake.build_config import BuildConfig diff --git a/zephyr/zmake/tests/test_generate_readme.py b/zephyr/zmake/tests/test_generate_readme.py index 2149b3fc6e..882b9c81ca 100644 --- a/zephyr/zmake/tests/test_generate_readme.py +++ b/zephyr/zmake/tests/test_generate_readme.py @@ -6,7 +6,7 @@ Tests for the generate_readme.py file. """ -import pytest +import pytest # pylint:disable=import-error import zmake.generate_readme as gen_readme diff --git a/zephyr/zmake/tests/test_modules.py b/zephyr/zmake/tests/test_modules.py index 9446e54f1c..8fdbd3cb43 100644 --- a/zephyr/zmake/tests/test_modules.py +++ b/zephyr/zmake/tests/test_modules.py @@ -7,8 +7,8 @@ import pathlib import tempfile -import hypothesis -import hypothesis.strategies as st +import hypothesis # pylint:disable=import-error +import hypothesis.strategies as st # pylint:disable=import-error import zmake.modules module_lists = st.lists( diff --git a/zephyr/zmake/tests/test_packers.py b/zephyr/zmake/tests/test_packers.py index 402cee690e..a038b51abd 100644 --- a/zephyr/zmake/tests/test_packers.py +++ b/zephyr/zmake/tests/test_packers.py @@ -7,9 +7,9 @@ import pathlib import tempfile -import hypothesis -import hypothesis.strategies as st -import pytest +import hypothesis # pylint:disable=import-error +import hypothesis.strategies as st # pylint:disable=import-error +import pytest # pylint:disable=import-error import zmake.output_packers as packers # Strategies for use with hypothesis diff --git a/zephyr/zmake/tests/test_project.py b/zephyr/zmake/tests/test_project.py index 5b5ca12583..2d98aaf32b 100644 --- a/zephyr/zmake/tests/test_project.py +++ b/zephyr/zmake/tests/test_project.py @@ -8,9 +8,9 @@ import pathlib import string import tempfile -import hypothesis -import hypothesis.strategies as st -import pytest +import hypothesis # pylint:disable=import-error +import hypothesis.strategies as st # pylint:disable=import-error +import pytest # pylint:disable=import-error import zmake.modules import zmake.output_packers import zmake.project diff --git a/zephyr/zmake/tests/test_reexec.py b/zephyr/zmake/tests/test_reexec.py index 08943909b2..d36b873506 100644 --- a/zephyr/zmake/tests/test_reexec.py +++ b/zephyr/zmake/tests/test_reexec.py @@ -7,7 +7,7 @@ import os import sys import unittest.mock as mock -import pytest +import pytest # pylint:disable=import-error import zmake.__main__ as main diff --git a/zephyr/zmake/tests/test_toolchains.py b/zephyr/zmake/tests/test_toolchains.py index f210bb7511..3773fac13d 100644 --- a/zephyr/zmake/tests/test_toolchains.py +++ b/zephyr/zmake/tests/test_toolchains.py @@ -7,7 +7,7 @@ import os import pathlib -import pytest +import pytest # pylint:disable=import-error import zmake.output_packers import zmake.project as project import zmake.toolchains as toolchains diff --git a/zephyr/zmake/tests/test_util.py b/zephyr/zmake/tests/test_util.py index 4a6c39f904..824e38d045 100644 --- a/zephyr/zmake/tests/test_util.py +++ b/zephyr/zmake/tests/test_util.py @@ -7,9 +7,9 @@ import pathlib import tempfile -import hypothesis -import hypothesis.strategies as st -import pytest +import hypothesis # pylint:disable=import-error +import hypothesis.strategies as st # pylint:disable=import-error +import pytest # pylint:disable=import-error import zmake.util as util # Strategies for use with hypothesis diff --git a/zephyr/zmake/tests/test_zmake.py b/zephyr/zmake/tests/test_zmake.py index 1c892ca2e4..db7189a2e8 100644 --- a/zephyr/zmake/tests/test_zmake.py +++ b/zephyr/zmake/tests/test_zmake.py @@ -10,14 +10,14 @@ import pathlib import re import unittest.mock -import pytest +import pytest # pylint:disable=import-error import zmake.build_config import zmake.jobserver import zmake.multiproc as multiproc import zmake.output_packers import zmake.project import zmake.toolchains -from testfixtures import LogCapture +from testfixtures import LogCapture # pylint:disable=import-error OUR_PATH = os.path.dirname(os.path.realpath(__file__)) -- cgit v1.2.1 From 87b4a3f45158b0710dec4ddb395360a8e405267c Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 8 Jul 2022 16:05:51 -0600 Subject: ec: Update vscode settings to use black and 88 col Use 88 characters for python and black as the formatter in vscode. BRANCH=None BUG=b:238434058 TEST=None Signed-off-by: Jeremy Bettis Change-Id: If46eda7f4e4622f7da6d39e12824dda07968eb07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749251 Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis Tested-by: Jeremy Bettis --- .vscode/settings.json.default | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.vscode/settings.json.default b/.vscode/settings.json.default index 1868e4f3af..100ef251d2 100644 --- a/.vscode/settings.json.default +++ b/.vscode/settings.json.default @@ -6,6 +6,7 @@ /* C, Makefiles, ASM, Linkerfiles, Properties */ "editor.insertSpaces": false, "editor.tabSize": 8, + "python.formatting.provider": "black", /* Some exceptions based on current trends */ "[markdown]": { "editor.insertSpaces": true, @@ -14,6 +15,9 @@ "[python]": { "editor.insertSpaces": true, "editor.tabSize": 2 + "editor.rulers": [ + 88 + ], }, "[shellscript]": { "editor.insertSpaces": true, -- cgit v1.2.1 From 3ee8dd3d69a467e695f4263d0aee1ebb26fced76 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Tue, 12 Jul 2022 13:27:00 -0600 Subject: ec: Fix kconfig_check and run unit test in cq Changed the unit test to fail if it can't find zephyr or the kconfiglib instead of skipping, and make it pass. Run the unit test in the CQ. In the process, I discovered that it never used kconfiglib because of errors with ZEPHYR_BASE not being set. Changed kconfig_check to output the error when it falls back to no kconfiglib. This exposed that there were missing configs in util/config_allowed.txt BRANCH=None BUG=b:238773780,b:181253613 TEST=make -j40 buildall && util/run_tests.sh Change-Id: I28a050d448a40df034dd9f2305a2d17cd0797468 Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759263 Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis Reviewed-by: Keith Short Tested-by: Jeremy Bettis --- Makefile.rules | 4 +++- firmware_builder.py | 1 + util/config_allowed.txt | 21 +-------------------- util/kconfig_check.py | 3 +++ util/run_tests.sh | 19 +++++++++++++++++++ util/test_kconfig_check.py | 16 ++++++++++++---- 6 files changed, 39 insertions(+), 25 deletions(-) create mode 100755 util/run_tests.sh diff --git a/Makefile.rules b/Makefile.rules index 484df79b4f..ab3281a0b7 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -254,7 +254,9 @@ conflicting_options := \ SPI \ UART_CONSOLE -cmd_check_allowed = ./util/kconfig_check.py -c ${config} \ +cmd_check_allowed = \ + ZEPHYR_BASE=$(abspath ../../../src/third_party/zephyr/main) \ + ./util/kconfig_check.py -c ${config} \ -a util/config_allowed.txt -p PLATFORM_EC_ -s zephyr/ \ -I $(abspath ../../../src/third_party/zephyr/main) \ $(foreach opt,$(conflicting_options),-i $(opt)) check diff --git a/firmware_builder.py b/firmware_builder.py index a4842cd454..6c74bf8409 100755 --- a/firmware_builder.py +++ b/firmware_builder.py @@ -217,6 +217,7 @@ def test(opts): subprocess.run( ["extra/stack_analyzer/run_tests.sh"], cwd=os.path.dirname(__file__), check=True ) + subprocess.run(["util/run_tests.sh"], cwd=os.path.dirname(__file__), check=True) # If building for code coverage, build the 'coverage' target, which # builds the posix-based unit tests for code coverage and assembles diff --git a/util/config_allowed.txt b/util/config_allowed.txt index 0496f77aa6..e5c0c6aac5 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -59,7 +59,6 @@ CONFIG_AP_HANG_DETECT CONFIG_AP_WARM_RESET_INTERRUPT CONFIG_ARMV7M_CACHE CONFIG_ASSEMBLY_MULA32 -CONFIG_AUDIO_CODEC CONFIG_AUDIO_CODEC_ CONFIG_AUDIO_CODEC_CAP_WOV_AUDIO_SHM CONFIG_AUDIO_CODEC_CAP_WOV_LANG_SHM @@ -202,8 +201,8 @@ CONFIG_CHIPSET_SKYLAKE CONFIG_CHIPSET_SLP_S3_L_OVERRIDE CONFIG_CHIPSET_STONEY CONFIG_CHIPSET_TIGERLAKE -CONFIG_CHIPSET_X86_RSMRST_DELAY CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 +CONFIG_CHIPSET_X86_RSMRST_DELAY CONFIG_CHIP_DATA_IN_INIT_ROM CONFIG_CHIP_LFW_USE_ROM_SPI CONFIG_CHIP_MEMORY_REGIONS @@ -345,7 +344,6 @@ CONFIG_CTN730 CONFIG_CTS_TASK_LIST CONFIG_CURVE25519 CONFIG_CUSTOM_FAN_CONTROL -CONFIG_DAC CONFIG_DATA_RAM_SIZE CONFIG_DEBUG_BRINGUP CONFIG_DEBUG_DISABLE_WRITE_BUFFER @@ -364,7 +362,6 @@ CONFIG_DFU_BOOTMANAGER_MAIN CONFIG_DFU_BOOTMANAGER_MAX_REBOOT_COUNT CONFIG_DFU_BOOTMANAGER_SHARED CONFIG_DFU_RUNTIME -CONFIG_DMA CONFIG_DMA_DEFAULT_HANDLERS CONFIG_DMA_HELP CONFIG_DMA_PAGING @@ -387,7 +384,6 @@ CONFIG_EC_PROTECTED_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_SIZE CONFIG_EC_WRITABLE_STORAGE_OFF CONFIG_EC_WRITABLE_STORAGE_SIZE -CONFIG_EEPROM CONFIG_ENABLE_JTAG_SELECTION CONFIG_EVENT_LOG_SIZE CONFIG_EXPERIMENTAL_CONSOLE @@ -510,7 +506,6 @@ CONFIG_HOSYCMD_BATTERY_V2 CONFIG_HWTIMER_64BIT CONFIG_HW_CRC CONFIG_HW_SPECIFIC_UDELAY -CONFIG_I2C_BITBANG CONFIG_I2C_BUS_MAY_BE_UNPOWERED CONFIG_I2C_CHIP_MAX_TRANSFER_SIZE CONFIG_I2C_CONTROLLER @@ -526,7 +521,6 @@ CONFIG_I2C_SCL_GATE_PORT CONFIG_I2C_UPDATE_IF_CHANGED CONFIG_I2C_XFER_BOARD_CALLBACK CONFIG_I2C_XFER_LARGE_TRANSFER -CONFIG_INA219 CONFIG_INA231 CONFIG_INA3221 CONFIG_INDUCTIVE_CHARGING @@ -618,7 +612,6 @@ CONFIG_LN9310 CONFIG_LOADER_MEM_OFF CONFIG_LOADER_SIZE CONFIG_LOADER_STORAGE_OFF -CONFIG_LOG_MAX_LEVEL CONFIG_LOW_POWER_IDLE_LIMITED CONFIG_LOW_POWER_S0 CONFIG_LOW_POWER_USE_LFIOSC @@ -694,7 +687,6 @@ CONFIG_PANIC_DRAM_SIZE CONFIG_PANIC_STRIP_GPR CONFIG_PD_RETRY_COUNT CONFIG_PD_USE_DAC_AS_REF -CONFIG_PECI CONFIG_PECI_COMMON CONFIG_PECI_TJMAX CONFIG_PLATFORM_EC_ @@ -720,10 +712,8 @@ CONFIG_PRINTF_LONG_IS_32BITS CONFIG_PRINT_IN_INT CONFIG_PROGRAM_MEMORY_BASE CONFIG_PROGRAM_MEMORY_BASE_LOAD -CONFIG_PS2 CONFIG_PSTORE CONFIG_PVD -CONFIG_PWM CONFIG_PWM_INPUT_LFCLK CONFIG_PWR_STATE_DISCHARGE_FULL CONFIG_RAM_BANKS @@ -800,16 +790,12 @@ CONFIG_SHAREDLIB_SIZE CONFIG_SHAREDLIB_STORAGE_OFF CONFIG_SHAREDMEM_MINIMUM_SIZE CONFIG_SHAREDMEM_MINIMUM_SIZE_RWSIG -CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL -CONFIG_SHELL_HELP CONFIG_SIMULATED_BUTTON CONFIG_SLEEP_TIMEOUT_MS CONFIG_SMBUS -CONFIG_SOC CONFIG_SOFTWARE_CLZ CONFIG_SOFTWARE_CTZ CONFIG_SOMETHING -CONFIG_SPI CONFIG_SPI_ACCEL_PORT CONFIG_SPI_CONTROLLER CONFIG_SPI_CS_GPIO @@ -899,8 +885,6 @@ CONFIG_TEST_TASK_LIST CONFIG_TEST_USB_PD_TIMER CONFIG_TEST_USB_PE_SM CONFIG_THERMISTOR_NCP15WB -CONFIG_THREAD_MONITOR -CONFIG_THREAD_NAME CONFIG_THROTTLE_AP_ON_BAT_OLTAGE CONFIG_THROTTLE_AP_ON_BAT_VOLTAGE CONFIG_TICK @@ -917,7 +901,6 @@ CONFIG_TOUCHPAD_VIRTUAL_SIZE CONFIG_TRICKLE_CHARGING CONFIG_TUSB544_EQ_BY_REGISTER CONFIG_UART_BAUD_RATE -CONFIG_UART_CONSOLE CONFIG_UART_HOST CONFIG_UART_HOST_COMMAND_BAUD_RATE CONFIG_UART_HOST_COMMAND_HW @@ -1064,7 +1047,6 @@ CONFIG_USB_RAM_ACCESS_TYPE CONFIG_USB_RAM_BASE CONFIG_USB_RAM_SIZE CONFIG_USB_REMOTE_WAKEUP -CONFIG_USB_SELF_POWERED CONFIG_USB_SERIALNO CONFIG_USB_SPI CONFIG_USB_SPI_BUFFER_SIZE @@ -1084,6 +1066,5 @@ CONFIG_WP_ACTIVE_HIGH CONFIG_WP_ALWAYS CONFIG_WP_STORAGE_OFF CONFIG_WP_STORAGE_SIZE -CONFIG_X86_64 CONFIG_ZEPHYR CONFIG_xxx diff --git a/util/kconfig_check.py b/util/kconfig_check.py index 04cdf9a990..db2bc09a5b 100755 --- a/util/kconfig_check.py +++ b/util/kconfig_check.py @@ -25,6 +25,7 @@ import os import pathlib import re import sys +import traceback # Try to use kconfiglib if available, but fall back to a simple recursive grep. # This is used by U-Boot in some situations so we keep it to avoid forking this @@ -331,6 +332,8 @@ class KconfigCheck: except kconfiglib.KconfigError: # If we don't actually have access to the full Kconfig then we may # get an error. Fall back to using manual methods. + print("WARNING: kconfiglib failed", file=sys.stderr) + traceback.print_exc() kconfigs = self.scan_kconfigs( srcdir, prefix, search_paths, try_kconfiglib=False ) diff --git a/util/run_tests.sh b/util/run_tests.sh new file mode 100755 index 0000000000..0ecd77207b --- /dev/null +++ b/util/run_tests.sh @@ -0,0 +1,19 @@ +#!/bin/bash +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Runs all the unit tests in the util dir. Uses relative paths, so don't run +# from any ebuild. + +# Show commands being run. +set -x + +# Exit if any command exits non-zero. +set -e + +# cd to the ec directory. +cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/.. + +# Run pytest +pytest util "$@" diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py index db73e7ee71..3b6a80fc81 100644 --- a/util/test_kconfig_check.py +++ b/util/test_kconfig_check.py @@ -202,10 +202,11 @@ rsource "subdir/Kconfig.wibble" def test_real_kconfig(self): """Same Kconfig should be returned for kconfiglib / adhoc""" if not kconfig_check.USE_KCONFIGLIB: - self.skipTest("No kconfiglib available") - zephyr_path = pathlib.Path("../../third_party/zephyr/main").resolve() + self.fail("No kconfiglib available") + zephyr_path = pathlib.Path("../../../src/third_party/zephyr/main").resolve() if not zephyr_path.exists(): - self.skipTest("No zephyr tree available") + self.fail("No zephyr tree available") + os.environ["ZEPHYR_BASE"] = str(zephyr_path) checker = kconfig_check.KconfigCheck() srcdir = "zephyr" @@ -229,7 +230,14 @@ rsource "subdir/Kconfig.wibble" # Similarly, some other items are defined in files that are not included # in all cases, only for particular values of $(ARCH) self.assertEqual( - ["FLASH_LOAD_OFFSET", "NPCX_HEADER", "SYS_CLOCK_HW_CYCLES_PER_SEC"], missing + [ + "BUG209907615", + "FLASH_LOAD_OFFSET", + "NPCX_HEADER", + "SYS_CLOCK_HW_CYCLES_PER_SEC", + "TRAP_UNALIGNED_ACCESS", + ], + missing, ) def test_check_unneeded(self): -- cgit v1.2.1 From 96a0bee80d70e04f499f548a0b20a604cba485d8 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Tue, 12 Jul 2022 17:01:17 -0600 Subject: util: Add test-inject-keys.sh to run_tests Add the shell test test-inject-keys.sh to util/run_tests.sh BRANCH=None BUG=None TEST=./util/run_tests.sh Signed-off-by: Jeremy Bettis Change-Id: I5608b81cd4d0faa1688a3d62035eb7af360ac4a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759274 Tested-by: Jeremy Bettis Commit-Queue: Jeremy Bettis Reviewed-by: Tristan Honscheid Reviewed-by: Jack Rosenthal --- util/run_tests.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/run_tests.sh b/util/run_tests.sh index 0ecd77207b..9ec2523e89 100755 --- a/util/run_tests.sh +++ b/util/run_tests.sh @@ -17,3 +17,7 @@ cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/.. # Run pytest pytest util "$@" + +# Run shell tests +cd util +./test-inject-keys.sh -- cgit v1.2.1 From f19de5dbca8a76c68667b6fe5abcc0daf4e57ef9 Mon Sep 17 00:00:00 2001 From: madhurimaparuchuri Date: Wed, 13 Jul 2022 16:34:18 +0530 Subject: zephyr: shim: fan: Use 'period' from PWM spec inplace of 'pwm-frequency' Update driver to use 'period' from PWM spec inplace of 'pwm-frequency' BUG=b:230093078 BRANCH=none TEST=zmake testall TEST=check if fan_config structure has correct 'period_ns' value using gdb: gdb ./build/zephyr/${BOARD}/build-ro/zephyr/zephyr.elf p fan_config Signed-off-by: Madhurima Paruchuri Change-Id: Icc56287133002731df8af4d72b455d4db2401a08 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752438 Reviewed-by: Fabio Baltieri --- zephyr/shim/src/fan.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c index 48a452fc13..1d3f418c17 100644 --- a/zephyr/shim/src/fan.c +++ b/zephyr/shim/src/fan.c @@ -51,13 +51,13 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, .rpm = &node_id##_rpm, \ }, -#define FAN_CONTROL_INST(node_id) \ - [node_id] = { \ - .pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ - .channel = DT_PWMS_CHANNEL(node_id), \ - .flags = DT_PWMS_FLAGS(node_id), \ - .period_ns = (NSEC_PER_SEC / DT_PROP(node_id, pwm_frequency)), \ - .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ +#define FAN_CONTROL_INST(node_id) \ + [node_id] = { \ + .pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ + .channel = DT_PWMS_CHANNEL(node_id), \ + .flags = DT_PWMS_FLAGS(node_id), \ + .period_ns = (NSEC_PER_SEC / DT_PWMS_PERIOD(node_id)), \ + .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ }, DT_INST_FOREACH_CHILD(0, FAN_CONFIGS) -- cgit v1.2.1 From 89734d2adca466daa5ce0332db8944e5ce6a2a3c Mon Sep 17 00:00:00 2001 From: Kshitiz Godara Date: Wed, 13 Jul 2022 21:15:56 +0530 Subject: zephyr: hoglin: Increase power off delay from 500 to 550 ms Hoglin switchcap requires more time for shutdown to complete. The additional delay measured by experiments is ~450 ms (varying from 430 ms to 470 ms). This patch increases the shutdown delay for Hoglin to 550 ms. BRANCH=None BUG=b:212222920 TEST=Tested image on hoglin board for following 1) dut-control warm_reset:on; dut-control warm_reset:off 2) quick power off and power on from ec console In both the cases device can boot up without complaining AP POWER NOT READY. Signed-off-by: Kshitiz Godara Change-Id: Ia4bda7af9172c98f154c0986116b99949fbc3b43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760794 Reviewed-by: Wai-Hong Tam Commit-Queue: Wai-Hong Tam --- zephyr/projects/herobrine/switchcap_hoglin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/herobrine/switchcap_hoglin.dts b/zephyr/projects/herobrine/switchcap_hoglin.dts index a59f5721b8..555be373e5 100644 --- a/zephyr/projects/herobrine/switchcap_hoglin.dts +++ b/zephyr/projects/herobrine/switchcap_hoglin.dts @@ -7,6 +7,6 @@ switchcap { compatible = "switchcap-gpio"; enable-pin = <&gpio_switchcap_on>; - poff-delay-ms = <500>; + poff-delay-ms = <550>; }; }; -- cgit v1.2.1 From d7c224c401e08a9caf136654c07fc869e88eec01 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Thu, 2 Jun 2022 13:36:54 -0600 Subject: tests: Add host cmd wrapper for alternative mode To facilitate easier testing of alternate modes, such as display-port, add a host command wrapper for the EC_CMD_USB_PD_GET_AMODE host command. BRANCH=none BUG=b:219562077 TEST=zmake test test-drivers Signed-off-by: Aaron Massey Change-Id: I78bcc3031907971a600d0c43e2239875c32be0a4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3687083 Reviewed-by: Wai-Hong Tam --- zephyr/test/drivers/include/test/drivers/utils.h | 11 ++++++++++ zephyr/test/drivers/src/espi.c | 2 -- zephyr/test/drivers/src/utils.c | 17 +++++++++++++++ .../test/drivers/usbc_alt_mode/src/usbc_alt_mode.c | 25 ++++++---------------- 4 files changed, 34 insertions(+), 21 deletions(-) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index 6e57d2171a..435c20c1ff 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -356,6 +356,17 @@ int host_cmd_motion_sense_spoof(uint8_t sensor_num, uint8_t enable, */ void host_cmd_typec_discovery(int port, enum typec_partner_type partner_type, void *response, size_t response_size); +/** + * @brief Run the host command to get the PD alternative mode response. + * + * @param port The USB-C port number + * @param response Destination for command response. + * @param response_size Destination of response size from request params. + */ +void host_cmd_usb_pd_get_amode( + uint8_t port, uint16_t svid_idx, + struct ec_params_usb_pd_get_mode_response *response, + int *response_size); /** * Run the host command to control PD port behavior. For now, this function only diff --git a/zephyr/test/drivers/src/espi.c b/zephyr/test/drivers/src/espi.c index 1b7c1d9b70..f0e7a1e9e3 100644 --- a/zephyr/test/drivers/src/espi.c +++ b/zephyr/test/drivers/src/espi.c @@ -71,8 +71,6 @@ ZTEST_USER(espi, test_host_command_usb_pd_get_amode) zassert_ok(args.result, NULL); /* Note: with no SVIDs the response size is the size of the svid field. * See the usb alt mode test for verifying larger struct sizes - * - * TODO(b/219562077): Add the above described test. */ zassert_equal(args.response_size, sizeof(response.svid), NULL); } diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/src/utils.c index e7c4e2d145..2d443832d9 100644 --- a/zephyr/test/drivers/src/utils.c +++ b/zephyr/test/drivers/src/utils.c @@ -380,6 +380,23 @@ void host_cmd_typec_control(int port, enum typec_control_command command, "Failed to send Type-C control for port %d", port); } +void host_cmd_usb_pd_get_amode( + uint8_t port, uint16_t svid_idx, + struct ec_params_usb_pd_get_mode_response *response, int *response_size) +{ + struct ec_params_usb_pd_get_mode_request params = { + .port = port, + .svid_idx = svid_idx, + }; + struct host_cmd_handler_args args = + BUILD_HOST_COMMAND_PARAMS(EC_CMD_USB_PD_GET_AMODE, 0, params); + args.response = response; + + zassume_ok(host_command_process(&args), + "Failed to get alternate-mode info for port %d", port); + *response_size = args.response_size; +} + K_HEAP_DEFINE(test_heap, 2048); void *test_malloc(size_t bytes) diff --git a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c index 7724ac993f..4e9911ea5b 100644 --- a/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c +++ b/zephyr/test/drivers/usbc_alt_mode/src/usbc_alt_mode.c @@ -248,19 +248,13 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_entry) k_sleep(K_SECONDS(1)); /* Verify host command when VDOs are present. */ - struct ec_params_usb_pd_get_mode_request params = { - .port = TEST_PORT, - .svid_idx = 0, - }; struct ec_params_usb_pd_get_mode_response response; - struct host_cmd_handler_args args = BUILD_HOST_COMMAND( - EC_CMD_USB_PD_GET_AMODE, 0, response, params); + int response_size; - zassume_ok(host_command_process(&args), NULL); - zassume_ok(args.result, NULL); + host_cmd_usb_pd_get_amode(TEST_PORT, 0, &response, &response_size); /* Response should be populated with a DisplayPort VDO */ - zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response_size, sizeof(response), NULL); zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); zassert_equal(response.vdo[0], fixture->partner.modes_vdm[response.opos], NULL); @@ -290,20 +284,13 @@ ZTEST_F(usbc_alt_mode, verify_displayport_mode_reentry) zassert_true(fixture->partner.displayport_configured, NULL); /* Verify that DisplayPort is the active alternate mode. */ - /* TODO(b/235984702): Wrap EC_CMD_USB_PD_GET_AMODE in a function. */ - struct ec_params_usb_pd_get_mode_request params = { - .port = TEST_PORT, - .svid_idx = 0, - }; struct ec_params_usb_pd_get_mode_response response; - struct host_cmd_handler_args args = BUILD_HOST_COMMAND( - EC_CMD_USB_PD_GET_AMODE, 0, response, params); + int response_size; - zassume_ok(host_command_process(&args), NULL); - zassume_ok(args.result, NULL); + host_cmd_usb_pd_get_amode(TEST_PORT, 0, &response, &response_size); /* Response should be populated with a DisplayPort VDO */ - zassert_equal(args.response_size, sizeof(response), NULL); + zassert_equal(response_size, sizeof(response), NULL); zassert_equal(response.svid, USB_SID_DISPLAYPORT, NULL); zassert_equal(response.vdo[0], fixture->partner.modes_vdm[response.opos], NULL); -- cgit v1.2.1 From 78ecef45bb5106eb24b9c39beacbf90fefa41d28 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Thu, 30 Jun 2022 16:49:10 -0600 Subject: tests: Fix chargesplash within-suite-OD failure The chargesplash test helper function force_chipset_off restarts the chipset state in order to test the lid opening triggering the chargesplash screen. However, not enough ramp-up time seems to be happening afterwards for GPIO interrupts to properly fire. Abstract the helper as a common utility function with an additional virtual sleep inserted at the end so that future test-writers do not run into the same problem. BRANCH=none BUG=b:236726670 TEST=zmake test-drivers TEST=zmake test-drivers-chargesplash shuffled with shuffle_test.sh Signed-off-by: Aaron Massey Change-Id: Idbcfd65a7ec66ebbd759d1a85447127d570d0099 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739317 Reviewed-by: Yuval Peress --- zephyr/test/drivers/include/test/drivers/utils.h | 7 +++++ zephyr/test/drivers/src/chargesplash.c | 39 +++--------------------- zephyr/test/drivers/src/utils.c | 33 ++++++++++++++++++++ 3 files changed, 45 insertions(+), 34 deletions(-) diff --git a/zephyr/test/drivers/include/test/drivers/utils.h b/zephyr/test/drivers/include/test/drivers/utils.h index 435c20c1ff..24927e2bf0 100644 --- a/zephyr/test/drivers/include/test/drivers/utils.h +++ b/zephyr/test/drivers/include/test/drivers/utils.h @@ -450,4 +450,11 @@ void *test_malloc(size_t bytes); */ void test_free(void *mem); +/** + * @brief Force the chipset to state G3 and then transition to S3 and finally + * S5. + * + */ +void test_set_chipset_to_g3_then_transition_to_s5(void); + #endif /* ZEPHYR_TEST_DRIVERS_INCLUDE_UTILS_H_ */ diff --git a/zephyr/test/drivers/src/chargesplash.c b/zephyr/test/drivers/src/chargesplash.c index 3eec11bbe4..76ab921a70 100644 --- a/zephyr/test/drivers/src/chargesplash.c +++ b/zephyr/test/drivers/src/chargesplash.c @@ -44,35 +44,6 @@ static bool is_chargesplash_requested(void) return response.requested; } -static struct k_poll_signal shutdown_complete_signal = - K_POLL_SIGNAL_INITIALIZER(shutdown_complete_signal); -static struct k_poll_event shutdown_complete_event = K_POLL_EVENT_INITIALIZER( - K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &shutdown_complete_signal); - -static void handle_chipset_shutdown_complete_event(void) -{ - k_poll_signal_raise(&shutdown_complete_signal, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, - handle_chipset_shutdown_complete_event, HOOK_PRIO_LAST); - -static void force_chipset_off(void) -{ - if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) { - k_poll_signal_reset(&shutdown_complete_signal); - chipset_force_shutdown(CHIPSET_RESET_INIT); - k_poll(&shutdown_complete_event, 1, K_MSEC(1000)); - } - - /* - * Signal will trigger during S3->S5, but we want to wait until we're - * actually at S5. Give it a quick sleep if required. - */ - while (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) { - msleep(5); - } -} - static struct k_poll_signal s0_signal = K_POLL_SIGNAL_INITIALIZER(s0_signal); static struct k_poll_event s0_event = K_POLL_EVENT_INITIALIZER( K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &s0_signal); @@ -124,7 +95,7 @@ static void set_lid(bool open, bool inhibit_boot) if (inhibit_boot) { wait_for_chipset_startup(); - force_chipset_off(); + test_set_chipset_to_g3_then_transition_to_s5(); } } @@ -136,7 +107,7 @@ static void pulse_power_button(void) static void reset_state(void *unused) { - force_chipset_off(); + test_set_chipset_to_g3_then_transition_to_s5(); if (lid_is_open()) { set_lid(false, false); @@ -213,7 +184,7 @@ ZTEST_USER(chargesplash, test_lockout) wait_for_chipset_startup(); set_ac_enabled(false); - force_chipset_off(); + test_set_chipset_to_g3_then_transition_to_s5(); } set_ac_enabled(true); @@ -260,7 +231,7 @@ ZTEST_USER(chargesplash, test_manual_lockout_via_console) zassert_true(is_chargesplash_requested(), "chargesplash should be requested"); wait_for_chipset_startup(); - force_chipset_off(); + test_set_chipset_to_g3_then_transition_to_s5(); zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash lockout"), NULL); @@ -288,7 +259,7 @@ ZTEST_USER(chargesplash, test_manual_lockout_via_hostcmd) zassert_true(is_chargesplash_requested(), "chargesplash should be requested"); wait_for_chipset_startup(); - force_chipset_off(); + test_set_chipset_to_g3_then_transition_to_s5(); zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_LOCKOUT, &response), NULL); diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/src/utils.c index 2d443832d9..3785ecf2e4 100644 --- a/zephyr/test/drivers/src/utils.c +++ b/zephyr/test/drivers/src/utils.c @@ -416,3 +416,36 @@ void test_free(void *mem) { k_heap_free(&test_heap, mem); } + +static struct k_poll_signal shutdown_complete_signal = + K_POLL_SIGNAL_INITIALIZER(shutdown_complete_signal); +static struct k_poll_event shutdown_complete_event = K_POLL_EVENT_INITIALIZER( + K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &shutdown_complete_signal); + +static void handle_chipset_shutdown_complete_event(void) +{ + k_poll_signal_raise(&shutdown_complete_signal, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN_COMPLETE, + handle_chipset_shutdown_complete_event, HOOK_PRIO_LAST); + +void test_set_chipset_to_g3_then_transition_to_s5(void) +{ + if (!chipset_in_state(CHIPSET_STATE_ANY_OFF)) { + k_poll_signal_reset(&shutdown_complete_signal); + chipset_force_shutdown(CHIPSET_RESET_INIT); + k_poll(&shutdown_complete_event, 1, K_MSEC(1000)); + } + + /* + * Signal will trigger during S3->S5, but we want to wait until we're + * actually at S5. Give it a quick sleep if required. + */ + WAIT_FOR(!chipset_in_state(CHIPSET_STATE_ANY_OFF), 1000000 /* 1s */, + k_msleep(5)); + + /* + * TODO(b/236726670): Why do we need to sleep after restarting chipset? + */ + k_sleep(K_SECONDS(1)); +} -- cgit v1.2.1 From 6c36907fb5e3127a70e8c31eb1ecdd0b64352539 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Wed, 13 Jul 2022 14:06:03 -0700 Subject: prism: rgbkbd: Fix tab and tilde keys LED mapping LED mapping for Tab and tilde were off which didn't light up both the LEDs present under the keys. This patch fixes the mapping. BRANCH=none BUG=b:238899691 TEST=ectool --device 18d1:5022 1 0xff0000, ectool --device 18d1:5022 16 0xff0000 Signed-off-by: Parth Malkan Change-Id: I89d1c93603772584e883e722cebef91dff01c599 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761219 Commit-Queue: YH Lin Reviewed-by: YH Lin --- board/prism/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/prism/board.c b/board/prism/board.c index 5ff237317f..a19ea1221f 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -109,7 +109,7 @@ const enum ec_rgbkbd_type rgbkbd_type = EC_RGBKBD_TYPE_PER_KEY; const uint8_t rgbkbd_map[] = { DELM, /* 0: (null) */ - LED(0, 1), DELM, /* 1: ~ ` */ + LED(0, 1), LED(0, 2), DELM, /* 1: ~ ` */ LED(1, 1), LED(1, 2), DELM, /* 2: ! 1 */ LED(2, 1), LED(2, 2), DELM, /* 3: @ 2 */ LED(3, 1), LED(3, 2), DELM, /* 4: # 3 */ @@ -124,7 +124,7 @@ const uint8_t rgbkbd_map[] = { LED(12, 1), LED(12, 2), DELM, /* 13: + = */ DELM, /* 14: (null) */ LED(13, 1), LED(13, 2), DELM, /* 15: backspace */ - LED(0, 3), DELM, /* 16: tab */ + LED(0, 3), LED(15, 2), DELM, /* 16: tab */ LED(1, 3), DELM, /* 17: q */ LED(2, 3), DELM, /* 18: w */ LED(3, 3), DELM, /* 19: e */ -- cgit v1.2.1 From 2715d7491fbeb43185ab81986e325f1929294158 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Mon, 11 Jul 2022 16:56:06 -0600 Subject: test: Add implementation of interrupt_generator To prevent flaky coverage in core/host/task.c, implement interrupt_generator() in one of the 5 tests where the coverage results are inconsistent. The fan test is good because it doesn't use interrupts. BRANCH=None BUG=b:213374060 TEST=TEST=fan ; make clobber ; \ make TEST_COVERAGE=y build/coverage/${TEST}.info >&/dev/null && \ lcov --summary build/coverage/${TEST}.info && \ lcov --list build/coverage/${TEST}.info | grep core/host/task.c Change-Id: I76b662eef9f70d339e609264dca251168dbdd0ea Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756737 Commit-Queue: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Abe Levkoy --- test/fan.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/test/fan.c b/test/fan.c index 683610fd31..a3d53f470c 100644 --- a/test/fan.c +++ b/test/fan.c @@ -10,7 +10,6 @@ #include "fan.h" #include "hooks.h" #include "host_command.h" -#include "printf.h" #include "temp_sensor.h" #include "test_util.h" #include "thermal.h" @@ -111,3 +110,10 @@ void run_test(int argc, char **argv) test_print_result(); } + +/* Doesn't do anything, but it makes this test stop intermittently covering + * some code in core/host/task.c:fast_forward(). + */ +void interrupt_generator(void) +{ +} -- cgit v1.2.1 From 44becd517fb02228e4099f9f030b83a30bed82e0 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Mon, 11 Jul 2022 15:51:57 -0600 Subject: ec: Increase sleep in stillness_detector test The sleep at the end of the test wasn't enough to eliminate the flakes, so increase to 4s. BRANCH=None BUG=b:213374060,b:234225228 TEST=Ran this command many times make clobber ; \ make TEST_COVERAGE=y build/coverage/stillness_detector.info \ >&/dev/null && lcov --summary build/coverage/stillness_detector.info \ && lcov --list build/coverage/stillness_detector.info \ | grep common/mkbp_event.c Change-Id: I7bd9ba522105406742048c15be4b1034f0e3dc86 Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756736 Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Aaron Massey Commit-Queue: Aaron Massey --- test/stillness_detector.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/stillness_detector.c b/test/stillness_detector.c index ce28c76eb1..c8a7a22b50 100644 --- a/test/stillness_detector.c +++ b/test/stillness_detector.c @@ -132,6 +132,6 @@ void run_test(int argc, char **argv) RUN_TEST(test_resets); /* Wait for all background tasks to start. */ - sleep(2); + sleep(4); test_print_result(); } -- cgit v1.2.1 From 920430206d970071ec70319331e0c2ca80211d2e Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Thu, 30 Jun 2022 17:12:00 -0600 Subject: tests: Factor chargesplash tests out as a library In order to be able to easily build a test-drivers variant with only chargesplash test suite, split the chargesplash test as its own library that can be linked into its own binary or as part of the test-drivers. BRANCH=none BUG=b:236726670 TEST=zmake test-drivers-chargesplash TEST=zmake test-drivers # does not contain chargesplash test TEST=shuffle tests-drivers-chargesplash Signed-off-by: Aaron Massey Change-Id: Ic320b00943d4d5e113a81d7b6d4f0cff59ef2202 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739318 Reviewed-by: Yuval Peress --- zephyr/test/drivers/BUILD.py | 6 + zephyr/test/drivers/CMakeLists.txt | 1 - zephyr/test/drivers/chargesplash/CMakeLists.txt | 19 ++ .../test/drivers/chargesplash/src/chargesplash.c | 297 +++++++++++++++++++++ zephyr/test/drivers/src/chargesplash.c | 297 --------------------- 5 files changed, 322 insertions(+), 298 deletions(-) create mode 100644 zephyr/test/drivers/chargesplash/CMakeLists.txt create mode 100644 zephyr/test/drivers/chargesplash/src/chargesplash.c delete mode 100644 zephyr/test/drivers/src/chargesplash.c diff --git a/zephyr/test/drivers/BUILD.py b/zephyr/test/drivers/BUILD.py index e619faad6c..5d8bde6668 100644 --- a/zephyr/test/drivers/BUILD.py +++ b/zephyr/test/drivers/BUILD.py @@ -15,6 +15,12 @@ drivers = register_host_test( ], ) +# Per Suite Builds + +chargesplash = drivers.variant( + project_name="test-drivers-chargesplash", +) + isl923x = drivers.variant( project_name="test-drivers-isl923x", ) diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index dc763c4b14..55c824b44f 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -33,7 +33,6 @@ if(subproject_path STREQUAL "") src/bmi160.c src/bmi260.c src/charge_manager.c - src/chargesplash.c src/console_cmd/charge_manager.c src/console_cmd/charge_state.c src/console_cmd/accelinit.c diff --git a/zephyr/test/drivers/chargesplash/CMakeLists.txt b/zephyr/test/drivers/chargesplash/CMakeLists.txt new file mode 100644 index 0000000000..aa8de2c683 --- /dev/null +++ b/zephyr/test/drivers/chargesplash/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Create library name based on current directory +zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name) + +# Create interface library +zephyr_interface_library_named(${lib_name}) + +# Add include paths +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}") +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") + +# Add source files +zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/chargesplash.c") + +# Link in the library +zephyr_library_link_libraries(${lib_name}) diff --git a/zephyr/test/drivers/chargesplash/src/chargesplash.c b/zephyr/test/drivers/chargesplash/src/chargesplash.c new file mode 100644 index 0000000000..76ab921a70 --- /dev/null +++ b/zephyr/test/drivers/chargesplash/src/chargesplash.c @@ -0,0 +1,297 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "chipset.h" +#include "config.h" +#include "ec_commands.h" +#include "extpower.h" +#include "hooks.h" +#include "host_command.h" +#include "lid_switch.h" +#include "timer.h" +#include "test/drivers/test_state.h" +#include "test/drivers/utils.h" + +/* Do a chargesplash host cmd */ +static enum ec_status +chargesplash_hostcmd(enum ec_chargesplash_cmd cmd, + struct ec_response_chargesplash *response) +{ + struct ec_params_chargesplash params = { .cmd = cmd }; + struct host_cmd_handler_args args = + BUILD_HOST_COMMAND(EC_CMD_CHARGESPLASH, 0, *response, params); + + return host_command_process(&args); +} + +static bool is_chargesplash_requested(void) +{ + struct ec_response_chargesplash response; + + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_GET_STATE, &response), + NULL); + + return response.requested; +} + +static struct k_poll_signal s0_signal = K_POLL_SIGNAL_INITIALIZER(s0_signal); +static struct k_poll_event s0_event = K_POLL_EVENT_INITIALIZER( + K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &s0_signal); + +static void handle_chipset_s0_event(void) +{ + k_poll_signal_raise(&s0_signal, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, handle_chipset_s0_event, HOOK_PRIO_LAST); + +static void wait_for_chipset_startup(void) +{ + if (!chipset_in_state(CHIPSET_STATE_ON)) { + k_poll_signal_reset(&s0_signal); + k_poll(&s0_event, 1, K_FOREVER); + } + + /* + * TODO(b/230362548): We need to give the EC a bit to "calm down" + * after reaching S0. + */ + msleep(2000); +} + +#define GPIO_LID_OPEN_EC_NODE DT_NODELABEL(gpio_lid_open_ec) +#define GPIO_LID_OPEN_EC_CTLR DT_GPIO_CTLR(GPIO_LID_OPEN_EC_NODE, gpios) +#define GPIO_LID_OPEN_EC_PORT DT_GPIO_PIN(GPIO_LID_OPEN_EC_NODE, gpios) + +static void set_lid(bool open, bool inhibit_boot) +{ + const struct device *lid_switch_dev = + DEVICE_DT_GET(GPIO_LID_OPEN_EC_CTLR); + + __ASSERT(lid_is_open() != open, + "Lid change was requested, but it's already in that state"); + + if (!open) { + __ASSERT(!inhibit_boot, + "inhibit_boot should not be used with a lid close"); + } + + zassume_ok(gpio_emul_input_set(lid_switch_dev, GPIO_LID_OPEN_EC_PORT, + open), + "Failed to set lid switch GPIO"); + + while (lid_is_open() != open) { + usleep(LID_DEBOUNCE_US + 1); + } + + if (inhibit_boot) { + wait_for_chipset_startup(); + test_set_chipset_to_g3_then_transition_to_s5(); + } +} + +/* Simulate a regular power button press */ +static void pulse_power_button(void) +{ + zassert_ok(shell_execute_cmd(get_ec_shell(), "powerbtn"), NULL); +} + +static void reset_state(void *unused) +{ + test_set_chipset_to_g3_then_transition_to_s5(); + + if (lid_is_open()) { + set_lid(false, false); + } + + if (extpower_is_present()) { + set_ac_enabled(false); + } + + zassume_ok(shell_execute_cmd(get_ec_shell(), "chargesplash reset"), + "'chargesplash reset' shell command failed"); +} + +ZTEST_SUITE(chargesplash, drivers_predicate_post_main, NULL, reset_state, NULL, + reset_state); + +/* + * When the lid is open and AC is connected, the chargesplash should + * be requested. + */ +ZTEST_USER(chargesplash, test_connect_ac) +{ + set_lid(true, true); + + set_ac_enabled(true); + zassert_true(is_chargesplash_requested(), + "chargesplash should be requested"); + wait_for_chipset_startup(); +} + +/* + * When AC is not connected and we open the lid, the chargesplash + * should not be requested. + */ +ZTEST_USER(chargesplash, test_no_connect_ac) +{ + set_lid(true, false); + zassert_false(is_chargesplash_requested(), + "chargesplash should not be requested"); + wait_for_chipset_startup(); +} + +/* + * When we connect AC with the lid closed, the chargesplash should not + * be requested. + */ +ZTEST_USER(chargesplash, test_ac_connect_when_lid_closed) +{ + set_ac_enabled(true); + zassert_false(is_chargesplash_requested(), + "chargesplash should not be requested"); +} + +/* + * Test that, after many repeated requests, the chargesplash + * feature becomes locked and non-functional. This condition + * replicates a damaged charger or port which cannot maintain a + * reliable connection. + * + * Then, ensure the lockout clears after the chargesplash period + * passes. + */ +ZTEST_USER(chargesplash, test_lockout) +{ + int i; + + set_lid(true, true); + + for (i = 0; i < CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD; i++) { + set_ac_enabled(true); + + zassert_true(is_chargesplash_requested(), + "chargesplash should be requested"); + wait_for_chipset_startup(); + + set_ac_enabled(false); + test_set_chipset_to_g3_then_transition_to_s5(); + } + + set_ac_enabled(true); + zassert_false(is_chargesplash_requested(), + "chargesplash should be locked out"); + set_ac_enabled(false); + + sleep(CONFIG_CHARGESPLASH_PERIOD); + + set_ac_enabled(true); + zassert_true(is_chargesplash_requested(), + "lockout should have cleared"); + wait_for_chipset_startup(); +} + +/* Test cancel chargesplash request by power button push */ +ZTEST_USER(chargesplash, test_power_button) +{ + set_lid(true, true); + + set_ac_enabled(true); + zassert_true(is_chargesplash_requested(), + "chargesplash should be requested"); + wait_for_chipset_startup(); + zassert_true(is_chargesplash_requested(), + "chargesplash should still be requested"); + + pulse_power_button(); + zassert_false(is_chargesplash_requested(), + "chargesplash should be canceled by power button push"); + zassert_true(chipset_in_state(CHIPSET_STATE_ON), + "chipset should be on"); +} + +/* Manually lockout the feature via the shell */ +ZTEST_USER(chargesplash, test_manual_lockout_via_console) +{ + /* + * Put an entry in the request log so the lockout has + * something to wait on to clear. + */ + zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), + NULL); + zassert_true(is_chargesplash_requested(), + "chargesplash should be requested"); + wait_for_chipset_startup(); + test_set_chipset_to_g3_then_transition_to_s5(); + + zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash lockout"), + NULL); + zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), + NULL); + zassert_false(is_chargesplash_requested(), + "chargesplash should be not requested due to lockout"); + + sleep(CONFIG_CHARGESPLASH_PERIOD); + + zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), + NULL); + zassert_true(is_chargesplash_requested(), + "lockout should have cleared"); + wait_for_chipset_startup(); +} + +/* Manually lockout the feature via host command */ +ZTEST_USER(chargesplash, test_manual_lockout_via_hostcmd) +{ + struct ec_response_chargesplash response; + + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), + NULL); + zassert_true(is_chargesplash_requested(), + "chargesplash should be requested"); + wait_for_chipset_startup(); + test_set_chipset_to_g3_then_transition_to_s5(); + + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_LOCKOUT, &response), + NULL); + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), + NULL); + zassert_false(is_chargesplash_requested(), + "chargesplash should be not requested due to lockout"); + + sleep(CONFIG_CHARGESPLASH_PERIOD); + + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), + NULL); + zassert_true(is_chargesplash_requested(), + "lockout should have cleared"); + wait_for_chipset_startup(); +} + +/* Simulate an actual run of the display loop */ +ZTEST_USER(chargesplash, test_display_loop) +{ + struct ec_response_chargesplash response; + + set_lid(true, true); + set_ac_enabled(true); + zassert_true(is_chargesplash_requested(), NULL); + wait_for_chipset_startup(); + + zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_DISPLAY_READY, + &response), + NULL); + + zassert_true(is_chargesplash_requested(), NULL); + pulse_power_button(); + zassert_false(is_chargesplash_requested(), NULL); +} diff --git a/zephyr/test/drivers/src/chargesplash.c b/zephyr/test/drivers/src/chargesplash.c deleted file mode 100644 index 76ab921a70..0000000000 --- a/zephyr/test/drivers/src/chargesplash.c +++ /dev/null @@ -1,297 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "chipset.h" -#include "config.h" -#include "ec_commands.h" -#include "extpower.h" -#include "hooks.h" -#include "host_command.h" -#include "lid_switch.h" -#include "timer.h" -#include "test/drivers/test_state.h" -#include "test/drivers/utils.h" - -/* Do a chargesplash host cmd */ -static enum ec_status -chargesplash_hostcmd(enum ec_chargesplash_cmd cmd, - struct ec_response_chargesplash *response) -{ - struct ec_params_chargesplash params = { .cmd = cmd }; - struct host_cmd_handler_args args = - BUILD_HOST_COMMAND(EC_CMD_CHARGESPLASH, 0, *response, params); - - return host_command_process(&args); -} - -static bool is_chargesplash_requested(void) -{ - struct ec_response_chargesplash response; - - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_GET_STATE, &response), - NULL); - - return response.requested; -} - -static struct k_poll_signal s0_signal = K_POLL_SIGNAL_INITIALIZER(s0_signal); -static struct k_poll_event s0_event = K_POLL_EVENT_INITIALIZER( - K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &s0_signal); - -static void handle_chipset_s0_event(void) -{ - k_poll_signal_raise(&s0_signal, 0); -} -DECLARE_HOOK(HOOK_CHIPSET_RESUME, handle_chipset_s0_event, HOOK_PRIO_LAST); - -static void wait_for_chipset_startup(void) -{ - if (!chipset_in_state(CHIPSET_STATE_ON)) { - k_poll_signal_reset(&s0_signal); - k_poll(&s0_event, 1, K_FOREVER); - } - - /* - * TODO(b/230362548): We need to give the EC a bit to "calm down" - * after reaching S0. - */ - msleep(2000); -} - -#define GPIO_LID_OPEN_EC_NODE DT_NODELABEL(gpio_lid_open_ec) -#define GPIO_LID_OPEN_EC_CTLR DT_GPIO_CTLR(GPIO_LID_OPEN_EC_NODE, gpios) -#define GPIO_LID_OPEN_EC_PORT DT_GPIO_PIN(GPIO_LID_OPEN_EC_NODE, gpios) - -static void set_lid(bool open, bool inhibit_boot) -{ - const struct device *lid_switch_dev = - DEVICE_DT_GET(GPIO_LID_OPEN_EC_CTLR); - - __ASSERT(lid_is_open() != open, - "Lid change was requested, but it's already in that state"); - - if (!open) { - __ASSERT(!inhibit_boot, - "inhibit_boot should not be used with a lid close"); - } - - zassume_ok(gpio_emul_input_set(lid_switch_dev, GPIO_LID_OPEN_EC_PORT, - open), - "Failed to set lid switch GPIO"); - - while (lid_is_open() != open) { - usleep(LID_DEBOUNCE_US + 1); - } - - if (inhibit_boot) { - wait_for_chipset_startup(); - test_set_chipset_to_g3_then_transition_to_s5(); - } -} - -/* Simulate a regular power button press */ -static void pulse_power_button(void) -{ - zassert_ok(shell_execute_cmd(get_ec_shell(), "powerbtn"), NULL); -} - -static void reset_state(void *unused) -{ - test_set_chipset_to_g3_then_transition_to_s5(); - - if (lid_is_open()) { - set_lid(false, false); - } - - if (extpower_is_present()) { - set_ac_enabled(false); - } - - zassume_ok(shell_execute_cmd(get_ec_shell(), "chargesplash reset"), - "'chargesplash reset' shell command failed"); -} - -ZTEST_SUITE(chargesplash, drivers_predicate_post_main, NULL, reset_state, NULL, - reset_state); - -/* - * When the lid is open and AC is connected, the chargesplash should - * be requested. - */ -ZTEST_USER(chargesplash, test_connect_ac) -{ - set_lid(true, true); - - set_ac_enabled(true); - zassert_true(is_chargesplash_requested(), - "chargesplash should be requested"); - wait_for_chipset_startup(); -} - -/* - * When AC is not connected and we open the lid, the chargesplash - * should not be requested. - */ -ZTEST_USER(chargesplash, test_no_connect_ac) -{ - set_lid(true, false); - zassert_false(is_chargesplash_requested(), - "chargesplash should not be requested"); - wait_for_chipset_startup(); -} - -/* - * When we connect AC with the lid closed, the chargesplash should not - * be requested. - */ -ZTEST_USER(chargesplash, test_ac_connect_when_lid_closed) -{ - set_ac_enabled(true); - zassert_false(is_chargesplash_requested(), - "chargesplash should not be requested"); -} - -/* - * Test that, after many repeated requests, the chargesplash - * feature becomes locked and non-functional. This condition - * replicates a damaged charger or port which cannot maintain a - * reliable connection. - * - * Then, ensure the lockout clears after the chargesplash period - * passes. - */ -ZTEST_USER(chargesplash, test_lockout) -{ - int i; - - set_lid(true, true); - - for (i = 0; i < CONFIG_CHARGESPLASH_MAX_REQUESTS_PER_PERIOD; i++) { - set_ac_enabled(true); - - zassert_true(is_chargesplash_requested(), - "chargesplash should be requested"); - wait_for_chipset_startup(); - - set_ac_enabled(false); - test_set_chipset_to_g3_then_transition_to_s5(); - } - - set_ac_enabled(true); - zassert_false(is_chargesplash_requested(), - "chargesplash should be locked out"); - set_ac_enabled(false); - - sleep(CONFIG_CHARGESPLASH_PERIOD); - - set_ac_enabled(true); - zassert_true(is_chargesplash_requested(), - "lockout should have cleared"); - wait_for_chipset_startup(); -} - -/* Test cancel chargesplash request by power button push */ -ZTEST_USER(chargesplash, test_power_button) -{ - set_lid(true, true); - - set_ac_enabled(true); - zassert_true(is_chargesplash_requested(), - "chargesplash should be requested"); - wait_for_chipset_startup(); - zassert_true(is_chargesplash_requested(), - "chargesplash should still be requested"); - - pulse_power_button(); - zassert_false(is_chargesplash_requested(), - "chargesplash should be canceled by power button push"); - zassert_true(chipset_in_state(CHIPSET_STATE_ON), - "chipset should be on"); -} - -/* Manually lockout the feature via the shell */ -ZTEST_USER(chargesplash, test_manual_lockout_via_console) -{ - /* - * Put an entry in the request log so the lockout has - * something to wait on to clear. - */ - zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), - NULL); - zassert_true(is_chargesplash_requested(), - "chargesplash should be requested"); - wait_for_chipset_startup(); - test_set_chipset_to_g3_then_transition_to_s5(); - - zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash lockout"), - NULL); - zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), - NULL); - zassert_false(is_chargesplash_requested(), - "chargesplash should be not requested due to lockout"); - - sleep(CONFIG_CHARGESPLASH_PERIOD); - - zassert_ok(shell_execute_cmd(get_ec_shell(), "chargesplash request"), - NULL); - zassert_true(is_chargesplash_requested(), - "lockout should have cleared"); - wait_for_chipset_startup(); -} - -/* Manually lockout the feature via host command */ -ZTEST_USER(chargesplash, test_manual_lockout_via_hostcmd) -{ - struct ec_response_chargesplash response; - - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), - NULL); - zassert_true(is_chargesplash_requested(), - "chargesplash should be requested"); - wait_for_chipset_startup(); - test_set_chipset_to_g3_then_transition_to_s5(); - - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_LOCKOUT, &response), - NULL); - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), - NULL); - zassert_false(is_chargesplash_requested(), - "chargesplash should be not requested due to lockout"); - - sleep(CONFIG_CHARGESPLASH_PERIOD); - - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_REQUEST, &response), - NULL); - zassert_true(is_chargesplash_requested(), - "lockout should have cleared"); - wait_for_chipset_startup(); -} - -/* Simulate an actual run of the display loop */ -ZTEST_USER(chargesplash, test_display_loop) -{ - struct ec_response_chargesplash response; - - set_lid(true, true); - set_ac_enabled(true); - zassert_true(is_chargesplash_requested(), NULL); - wait_for_chipset_startup(); - - zassert_ok(chargesplash_hostcmd(EC_CHARGESPLASH_DISPLAY_READY, - &response), - NULL); - - zassert_true(is_chargesplash_requested(), NULL); - pulse_power_button(); - zassert_false(is_chargesplash_requested(), NULL); -} -- cgit v1.2.1 From bd685855f63a8f92bc9078acae89702454692b3a Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Tue, 7 Jun 2022 20:41:58 -0700 Subject: zephyr: npcx: rename pinctrl-0 property in def-io-conf-list DT node Rename `pinctrl-0` property to 'pinmux' in def-io-conf-list DT node for better understanding. BUG=b:234861079 BRANCH=none TEST=zmake testall --clobber Signed-off-by: Mulin Chao Change-Id: Id936093009076915a4d0ad1c9382e01bbf932294 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3686727 Reviewed-by: Fabio Baltieri Reviewed-by: Yuval Peress Reviewed-by: Jack Rosenthal Reviewed-by: Keith Short --- .../corsola/default_gpio_pinctrl_kingler.dts | 72 +++++++++++----------- zephyr/projects/herobrine/default_gpio_pinctrl.dts | 72 +++++++++++----------- .../trogdor/lazor/default_gpio_pinctrl.dts | 70 ++++++++++----------- 3 files changed, 107 insertions(+), 107 deletions(-) diff --git a/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts index d25b388726..a6f61cb3ed 100644 --- a/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts +++ b/zephyr/projects/corsola/default_gpio_pinctrl_kingler.dts @@ -5,40 +5,40 @@ /* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */ &{/def-io-conf-list} { - pinctrl-0 = <&alt0_gpio_no_spip - &alt0_gpio_no_fpip - &alt1_no_pwrgd - &alt1_no_lpc_espi - &alta_no_peci_en - &altd_npsl_in1_sl - &altd_npsl_in2_sl - &altd_psl_in3_sl - &altd_psl_in4_sl - &alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - &alt9_no_kso15_sl - &alta_no_kso16_sl - &alta_no_kso17_sl - &altg_psl_gpo_sl>; + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl + &altg_psl_gpo_sl>; }; diff --git a/zephyr/projects/herobrine/default_gpio_pinctrl.dts b/zephyr/projects/herobrine/default_gpio_pinctrl.dts index d25b388726..a6f61cb3ed 100644 --- a/zephyr/projects/herobrine/default_gpio_pinctrl.dts +++ b/zephyr/projects/herobrine/default_gpio_pinctrl.dts @@ -5,40 +5,40 @@ /* Adds the &alt1_no_lpc_espi setting over the NPCX9 default setting. */ &{/def-io-conf-list} { - pinctrl-0 = <&alt0_gpio_no_spip - &alt0_gpio_no_fpip - &alt1_no_pwrgd - &alt1_no_lpc_espi - &alta_no_peci_en - &altd_npsl_in1_sl - &altd_npsl_in2_sl - &altd_psl_in3_sl - &altd_psl_in4_sl - &alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - &alt9_no_kso15_sl - &alta_no_kso16_sl - &alta_no_kso17_sl - &altg_psl_gpo_sl>; + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl + &altg_psl_gpo_sl>; }; diff --git a/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts index 64da26a672..7c752f634d 100644 --- a/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts +++ b/zephyr/projects/trogdor/lazor/default_gpio_pinctrl.dts @@ -5,39 +5,39 @@ /* Adds the &alt1_no_lpc_espi setting over the NPCX7 default setting. */ &{/def-io-conf-list} { - pinctrl-0 = <&alt0_gpio_no_spip - &alt0_gpio_no_fpip - &alt1_no_pwrgd - &alt1_no_lpc_espi - &alta_no_peci_en - &altd_npsl_in1_sl - &altd_npsl_in2_sl - &altd_psl_in3_sl - &altd_psl_in4_sl - &alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - &alt9_no_kso15_sl - &alta_no_kso16_sl - &alta_no_kso17_sl >; + pinmux = <&alt0_gpio_no_spip + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alt1_no_lpc_espi + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl >; }; -- cgit v1.2.1 From 4c0ae8814a68f2c2655ebb0b3b80ec4529d07cb3 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Mon, 11 Jul 2022 20:16:18 -0700 Subject: zephyr: npcx: hibernate_psl: make this option relies on dt node's status Make the Kconfig hibernate_psl option enable automatically if the 'nuvoton,npcx-power-psl' DT node's status is 'okay'. The CL also removes this option in the prj.conf files since we needn't enable it explicitly. BRANCH=none BUG=none TEST=Compared the .config on herobrine, skyrim, and nivviks. Passed 'hibernate' console command on npcx9 evb. Signed-off-by: Mulin Chao Change-Id: Ic2aa6ea091a5b108237307884531a32d4107885d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3757281 Reviewed-by: Keith Short Reviewed-by: Fabio Baltieri Reviewed-by: Jack Rosenthal --- zephyr/Kconfig.system | 3 +++ zephyr/projects/brya/prj.conf | 3 --- zephyr/projects/herobrine/prj.conf | 3 --- zephyr/projects/npcx_evb/npcx9/prj.conf | 3 --- zephyr/projects/skyrim/prj.conf | 1 - 5 files changed, 3 insertions(+), 10 deletions(-) diff --git a/zephyr/Kconfig.system b/zephyr/Kconfig.system index c9b67a6ab7..66586b6e2d 100644 --- a/zephyr/Kconfig.system +++ b/zephyr/Kconfig.system @@ -2,6 +2,8 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. +DT_COMPAT_NUVOTON_NPCX_POWER_PSL := nuvoton,npcx-power-psl + if PLATFORM_EC config PLATFORM_EC_CONSOLE_CMD_SCRATCHPAD @@ -20,6 +22,7 @@ config PLATFORM_EC_CONSOLE_CMD_SYSINFO config PLATFORM_EC_HIBERNATE_PSL bool "System hibernating with PSL (Power Switch Logic) mechanism" + default $(dt_compat_enabled,$(DT_COMPAT_NUVOTON_NPCX_POWER_PSL)) depends on SOC_FAMILY_NPCX help Use PSL (Power Switch Logic) for hibernating. It turns off VCC power diff --git a/zephyr/projects/brya/prj.conf b/zephyr/projects/brya/prj.conf index 7ce897ae5f..fc2b87e1c5 100644 --- a/zephyr/projects/brya/prj.conf +++ b/zephyr/projects/brya/prj.conf @@ -86,9 +86,6 @@ CONFIG_PLATFORM_EC_TEMP_SENSOR=y CONFIG_PLATFORM_EC_THERMISTOR=y CONFIG_PLATFORM_EC_TEMP_SENSOR_POWER=y -# Miscellaneous configs -CONFIG_PLATFORM_EC_HIBERNATE_PSL=y - # MKBP event CONFIG_PLATFORM_EC_MKBP_EVENT=y CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y diff --git a/zephyr/projects/herobrine/prj.conf b/zephyr/projects/herobrine/prj.conf index e16d5c7899..81b2718803 100644 --- a/zephyr/projects/herobrine/prj.conf +++ b/zephyr/projects/herobrine/prj.conf @@ -26,9 +26,6 @@ CONFIG_SHELL_HISTORY=y CONFIG_SHELL_TAB=y CONFIG_SHELL_TAB_AUTOCOMPLETION=y -# Miscellaneous configs -CONFIG_PLATFORM_EC_HIBERNATE_PSL=y - # LED CONFIG_PLATFORM_EC_LED_COMMON=n CONFIG_PLATFORM_EC_LED_DT=y diff --git a/zephyr/projects/npcx_evb/npcx9/prj.conf b/zephyr/projects/npcx_evb/npcx9/prj.conf index 22b32b1de1..aa7e36a7a6 100644 --- a/zephyr/projects/npcx_evb/npcx9/prj.conf +++ b/zephyr/projects/npcx_evb/npcx9/prj.conf @@ -57,7 +57,4 @@ CONFIG_LOG=y # Avoid underflow info from tachometer CONFIG_SENSOR_LOG_LEVEL_ERR=y -# Hibernate and wake -CONFIG_PLATFORM_EC_HIBERNATE_PSL=y - CONFIG_SYSCON=y diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index 47e9c1d096..c6b5d3a537 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -133,7 +133,6 @@ CONFIG_GPIO_NCT38XX=y # Hibernate and wake CONFIG_PLATFORM_EC_BOARD_RESET_AFTER_POWER_ON=y -CONFIG_PLATFORM_EC_HIBERNATE_PSL=y # Motion sense CONFIG_PLATFORM_EC_MOTIONSENSE=y -- cgit v1.2.1 From 004d06ad7631ec995168add25df31926d0540593 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Fri, 8 Jul 2022 16:38:55 +1000 Subject: ps8xxx: add support for PS8745 The PS8745 is broadly identical to the PS8815, to the point that some firmware versions of PS8745.A2 claim to be PS8815.A2. A workaround is included to check whether a device is PS8815 or PS8745 and correct the device IDs if needed. BUG=b:236761058,b:237593618 TEST=PS8745-A2 now reports correct IDs on Nereid and USB port still works. BRANCH=none Signed-off-by: Peter Marheine Change-Id: I5d0542ef00956414854e6a38b1d127294cb3df0b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752425 Reviewed-by: Andrew McRae --- driver/build.mk | 1 + driver/tcpm/ps8xxx.c | 81 +++++++++++++++++++++++++++++++++---- driver/tcpm/ps8xxx.h | 5 +++ include/config.h | 1 + include/driver/tcpm/ps8xxx_public.h | 1 + zephyr/Kconfig.tcpm | 21 ++++++++++ zephyr/shim/include/config_chip.h | 10 +++++ 7 files changed, 112 insertions(+), 8 deletions(-) diff --git a/driver/build.mk b/driver/build.mk index 81955294eb..feef1ccc6c 100644 --- a/driver/build.mk +++ b/driver/build.mk @@ -165,6 +165,7 @@ endif driver-$(CONFIG_USB_PD_TCPM_ANX74XX)+=tcpm/anx74xx.o driver-$(CONFIG_USB_PD_TCPM_ANX7688)+=tcpm/anx7688.o driver-$(CONFIG_USB_PD_TCPM_ANX7447)+=tcpm/anx7447.o +driver-$(CONFIG_USB_PD_TCPM_PS8745)+=tcpm/ps8xxx.o driver-$(CONFIG_USB_PD_TCPM_PS8751)+=tcpm/ps8xxx.o driver-$(CONFIG_USB_PD_TCPM_PS8755)+=tcpm/ps8xxx.o driver-$(CONFIG_USB_PD_TCPM_PS8705)+=tcpm/ps8xxx.o diff --git a/driver/tcpm/ps8xxx.c b/driver/tcpm/ps8xxx.c index 0ffd69364a..9c51fbc910 100644 --- a/driver/tcpm/ps8xxx.c +++ b/driver/tcpm/ps8xxx.c @@ -8,6 +8,7 @@ * * Supported TCPCs: * - PS8705 + * - PS8745 * - PS8751 * - PS8755 * - PS8805 @@ -24,6 +25,7 @@ #include "usb_pd.h" #if !defined(CONFIG_USB_PD_TCPM_PS8705) && \ + !defined(CONFIG_USB_PD_TCPM_PS8745) && \ !defined(CONFIG_USB_PD_TCPM_PS8751) && \ !defined(CONFIG_USB_PD_TCPM_PS8755) && \ !defined(CONFIG_USB_PD_TCPM_PS8805) && \ @@ -165,13 +167,13 @@ static int ps8751_dci_disable(int port) } #endif /* CONFIG_USB_PD_TCPM_PS8751 */ -#ifdef CONFIG_USB_PD_TCPM_PS8815 +#if defined(CONFIG_USB_PD_TCPM_PS8815) || defined(CONFIG_USB_PD_TCPM_PS8745) static int ps8815_dci_disable(int port) { - /* DCI is disabled on the ps8815 */ + /* DCI is disabled on the ps8815 and ps8745 */ return EC_SUCCESS; } -#endif /* CONFIG_USB_PD_TCPM_PS8815 */ +#endif /* CONFIG_USB_PD_TCPM_PS8815 || CONFIG_USB_PD_TCPM_PS8745 */ #ifdef CONFIG_USB_PD_TCPM_PS8805 static int ps8805_gpio_mask[] = { @@ -250,6 +252,9 @@ static struct ps8xxx_variant_map variant_map[] = { [REG_FW_VER] = 0x82, } }, #endif +#ifdef CONFIG_USB_PD_TCPM_PS8745 + { PS8745_PRODUCT_ID, ps8815_dci_disable, { [REG_FW_VER] = 0x82 } }, +#endif #ifdef CONFIG_USB_PD_TCPM_PS8751 { PS8751_PRODUCT_ID, ps8751_dci_disable, @@ -341,6 +346,8 @@ __overridable uint16_t board_get_ps8xxx_product_id(int port) return 0; } else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8705)) { return PS8705_PRODUCT_ID; + } else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745)) { + return PS8745_PRODUCT_ID; } else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8751)) { return PS8751_PRODUCT_ID; } else if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8755)) { @@ -480,12 +487,13 @@ static int ps8xxx_tcpc_drp_toggle(int port) int opposite_pull; /* - * Workaround for PS8805/PS8815, which can't restart Connection + * Workaround for PS8805/PS8815/PS8745, which can't restart Connection * Detection if the partner already presents pull. Now starts with * the opposite pull. Check b/149570002. */ if (product_id[port] == PS8805_PRODUCT_ID || - product_id[port] == PS8815_PRODUCT_ID) { + product_id[port] == PS8815_PRODUCT_ID || + product_id[port] == PS8745_PRODUCT_ID) { if (ps8815_disable_rp_detect[port]) { CPRINTS("TCPC%d: rearm Rp disable detect on connect", port); @@ -587,6 +595,44 @@ static int ps8815_make_device_id(int port, int *id) } #endif +#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID +/* + * Some PS8745 firmwares report the same product/device ID and chip rev as + * PS8815-A2. This function probes vendor-specific registers to determine + * whether the device is a PS8815 or PS8745 and updates the IDs pointed to by + * the parameters to be the correct IDs for the detected chip. + * + * See b/236761058 and the PS8xxx TCPC Family Chip Revision Guide (v0.2) + */ +static int ps8745_make_device_id(int port, uint16_t *pid, uint16_t *did) +{ + int status; + int val; + + status = tcpc_addr_read( + port, + PS8751_P3_TO_P0_FLAGS(tcpc_config[port].i2c_info.addr_flags), + PS8815_P0_REG_ID, &val); + if (status != EC_SUCCESS) + return status; + + if (*pid == PS8815_PRODUCT_ID && (val & BIT(1)) != 0) { + /* PS8815 with this bit set is actually PS8745 */ + *pid = PS8745_PRODUCT_ID; + } + + if (*pid == PS8745_PRODUCT_ID && *did == 0x0003) { + /* + * Some versions report the correct product ID but the + * device ID is still for PS8815-A2. + */ + *did = 0x0006; + } + + return EC_SUCCESS; +} +#endif + /* * The ps8815 can take up to 50ms (FW_INIT_DELAY_MS) to fully wake up * from sleep/low power mode - specially when it contains an application @@ -654,6 +700,20 @@ static int ps8xxx_get_chip_info(int port, int live, chip_info->product_id = product_id[port]; } +#ifdef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID + /* device ID 3 is PS8815 and might be misreported */ + if (chip_info->product_id == PS8815_PRODUCT_ID || + chip_info->device_id == 0x0003) { + uint16_t pid = chip_info->product_id; + uint16_t did = chip_info->device_id; + + rv = ps8745_make_device_id(port, &pid, &did); + chip_info->product_id = pid; + chip_info->device_id = did; + if (rv != EC_SUCCESS) + return rv; + } +#endif #ifdef CONFIG_USB_PD_TCPM_PS8805_FORCE_DID if (chip_info->product_id == PS8805_PRODUCT_ID && chip_info->device_id == 0x0001) { @@ -702,12 +762,13 @@ static int ps8xxx_get_chip_info(int port, int live, static int ps8xxx_enter_low_power_mode(int port) { /* - * PS8751/PS8815 has the auto sleep function that enters + * PS8751/PS8815/PS8745 has the auto sleep function that enters * low power mode on its own in ~2 seconds. Other chips * don't have it. Stub it out for PS8751/PS8815. */ if (product_id[port] == PS8751_PRODUCT_ID || - product_id[port] == PS8815_PRODUCT_ID) + product_id[port] == PS8815_PRODUCT_ID || + product_id[port] == PS8745_PRODUCT_ID) return EC_SUCCESS; return tcpci_enter_low_power_mode(port); @@ -823,7 +884,10 @@ static int ps8xxx_tcpm_init(int port) status = ps8815_disable_rp_detect_workaround_check(port); if (status != EC_SUCCESS) return status; + } + if (IS_ENABLED(CONFIG_USB_PD_TCPM_PS8745) || + IS_ENABLED(CONFIG_USB_PD_TCPM_PS8815)) { /* * NOTE(b/183127346): Enable FRS sequence: * @@ -973,7 +1037,8 @@ const struct tcpm_drv ps8xxx_tcpm_drv = { .enter_low_power_mode = ps8xxx_enter_low_power_mode, #endif .set_bist_test_mode = tcpci_set_bist_test_mode, -#if defined(CONFIG_USB_PD_FRS) && defined(CONFIG_USB_PD_TCPM_PS8815) +#if defined(CONFIG_USB_PD_FRS) && (defined(CONFIG_USB_PD_TCPM_PS8815) || \ + defined(CONFIG_USB_PD_TCPM_PS8745)) .set_frs_enable = ps8815_tcpc_fast_role_swap_enable, #endif }; diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index 571b2d4ccb..82772e4a5e 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -99,6 +99,11 @@ * bit 7-4: 1010b is A3 chip, 0000b is A2 chip */ #define PS8805_P0_REG_CHIP_REVISION 0x62 +/* + * PS8815 register to differentiate with PS8745: bit 1 = 0 is a PS8815-A2, + * 1 is a PS8745-A2. + */ +#define PS8815_P0_REG_ID 0x2C /* * PS8805 GPIO control register. Note the device I2C address of 0x1A is diff --git a/include/config.h b/include/config.h index d22bb985cc..0d73dbe03a 100644 --- a/include/config.h +++ b/include/config.h @@ -4811,6 +4811,7 @@ * to provide the product id per port. */ #undef CONFIG_USB_PD_TCPM_MULTI_PS8XXX +#undef CONFIG_USB_PD_TCPM_PS8745 #undef CONFIG_USB_PD_TCPM_PS8751 #undef CONFIG_USB_PD_TCPM_PS8755 #undef CONFIG_USB_PD_TCPM_PS8705 diff --git a/include/driver/tcpm/ps8xxx_public.h b/include/driver/tcpm/ps8xxx_public.h index 0c0e7951c5..05823a7b42 100644 --- a/include/driver/tcpm/ps8xxx_public.h +++ b/include/driver/tcpm/ps8xxx_public.h @@ -56,6 +56,7 @@ struct usb_mux; * 8705, 8755 and 8805. */ #define PS8705_PRODUCT_ID 0x8705 +#define PS8745_PRODUCT_ID 0x8745 #define PS8751_PRODUCT_ID 0x8751 #define PS8755_PRODUCT_ID 0x8755 #define PS8805_PRODUCT_ID 0x8805 diff --git a/zephyr/Kconfig.tcpm b/zephyr/Kconfig.tcpm index 6aeb7cf3bb..ebd6e3b49a 100644 --- a/zephyr/Kconfig.tcpm +++ b/zephyr/Kconfig.tcpm @@ -156,12 +156,33 @@ config PLATFORM_EC_USB_PD_TCPM_MULTI_PS8XXX Supported return values are: PS8705_PRODUCT_ID + PS8745_PRODUCT_ID PS8751_PRODUCT_ID PS8755_PRODUCT_ID PS8805_PRODUCT_ID PS8815_PRODUCT_ID endif # PLATFORM_EC_USB_PD_TCPM_PS8XXX +config PLATFORM_EC_USB_PD_TCPM_PS8745 + bool "Parade PS8745 USB-C Gen 2 Type-C Port Controller" + select PLATFORM_EC_USB_PD_TCPM_PS8XXX + help + The Parade Technologies PS8815 is an active retiming/redriving + (respectively for USB 3.1 Gen 2 / DisplayPort 1.4a HBR3) integrated + with a USB Type-C Port Controller (TCPC) for USB Type-C Host and + DisplayPort applications. It supports Power Delivery and the + DisplayPort Alt Mode. + +if PLATFORM_EC_USB_PD_TCPM_PS8745 +config PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID + bool "Disambiguate PS8745 and PS8815" + default y + help + Some firmware versions of the PS8745 report incorrect product and device + IDs. Enable this option to check vendor-specific registers and force the + correct device and product IDs. +endif # PLATFORM_EC_USB_PD_TCPM_PS8745 + config PLATFORM_EC_USB_PD_TCPM_PS8751 bool "Parade PS8751 USB-C Gen 2 Type-C Port Controller" select PLATFORM_EC_USB_PD_TCPM_PS8XXX diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index deb6340dd5..f2864dddb3 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -1307,6 +1307,16 @@ extern struct jump_data mock_jump_data; #define CONFIG_USB_PD_TCPM_NCT38XX #endif +#undef CONFIG_USB_PD_TCPM_PS8745 +#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745 +#define CONFIG_USB_PD_TCPM_PS8745 +#endif + +#undef CONFIG_USB_PD_TCPM_PS8745_FORCE_ID +#ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745_FORCE_ID +#define CONFIG_USB_PD_TCPM_PS8745_FORCE_ID +#endif + #undef CONFIG_USB_PD_TCPM_PS8751 #ifdef CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8751 #define CONFIG_USB_PD_TCPM_PS8751 -- cgit v1.2.1 From 70a992c882a0f628483fe3f5bcf3443b1e5a2617 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Fri, 8 Jul 2022 09:53:29 +1000 Subject: nissa: use PS8745 support instead of PS8815 The PS8745 is mostly the same as the PS8815, but technically a different chip. EC driver support has been added for the 8745, so switch to using the driver in that mode. BUG=b:236761058,b:237593618 TEST=Sub-board USB port still works on Nereid, correct IDs are reported in `ectool usbpdinfo`. BRANCH=none Signed-off-by: Peter Marheine Change-Id: Ia9fd6aa1acdbf2559a661822be54af22ddfa0dee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752426 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/prj_joxer.conf | 2 +- zephyr/projects/nissa/prj_nereid.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/nissa/prj_joxer.conf b/zephyr/projects/nissa/prj_joxer.conf index 7537e75f51..03cccf3113 100644 --- a/zephyr/projects/nissa/prj_joxer.conf +++ b/zephyr/projects/nissa/prj_joxer.conf @@ -33,7 +33,7 @@ CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y # TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y # SM5803 controls power path on both ports CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y diff --git a/zephyr/projects/nissa/prj_nereid.conf b/zephyr/projects/nissa/prj_nereid.conf index 4b0db30556..c5913a5cdf 100644 --- a/zephyr/projects/nissa/prj_nereid.conf +++ b/zephyr/projects/nissa/prj_nereid.conf @@ -32,7 +32,7 @@ CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y # TCPC+PPC: ITE on-chip for C0, PS8745 for optional C1 CONFIG_PLATFORM_EC_USB_PD_TCPM_ITE_ON_CHIP=y CONFIG_PLATFORM_EC_USB_PD_TCPM_DRIVER_IT8XXX2=y -CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8815=y +CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8745=y CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_CHARGER=y # SM5803 controls power path on both ports CONFIG_PLATFORM_EC_USB_PD_5V_CHARGER_CTRL=y -- cgit v1.2.1 From 191d117f59f8e7a4ea8ad40111e703a2942aea1c Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Wed, 13 Jul 2022 18:10:53 +0800 Subject: power/mt8186: add CHIPSET_SUSPEND_COMPLETE hook CHIPSET_RESUME_INIT is usually paired with SUSPEND_COMPLETE (for example: chip/npcx/shi.c). Since we enabled RESUME_INIT on MT8186, we must invoke CHIPSET_SUSPEND_COMPLETE callback when entering S3 too. BUG=b:215659327 TEST=EC power consumption back to 4mw BRANCH=none Signed-off-by: Ting Shen Change-Id: I649b7f50aedbd77ea1954fc31295910f08e24cb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759110 Commit-Queue: Ting Shen Tested-by: Ting Shen Reviewed-by: Eric Yilun Lin Reviewed-by: Joyce Lee Tested-by: Joyce Lee --- power/mt8186.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/power/mt8186.c b/power/mt8186.c index 53ea4670d8..71de42a3a6 100644 --- a/power/mt8186.c +++ b/power/mt8186.c @@ -439,6 +439,8 @@ enum power_state power_handle_state(enum power_state state) chipset_force_shutdown_button(); } + hook_notify(HOOK_CHIPSET_SUSPEND_COMPLETE); + return POWER_S3; case POWER_S3S5: -- cgit v1.2.1 From 32ab922518bdb8e37f30ee8dd47b190a8c66353d Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Wed, 13 Jul 2022 15:04:16 -0600 Subject: zephyr: tests: Fix flaky BMI260 tests Add a before function and fix up some setup bugs in BMI260 unit tests. With these fixes, I was able to run the test executable 20 times with random seeds and not hit any BMI260 errors. BRANCH=None BUG=b:233100454,b:233099844,b:233099880 TEST=util/shuffle_test.sh "TESTSUITE bmi260 failed" Signed-off-by: Tristan Honscheid Change-Id: I77db0682c467424033d7984240db13ae7b3d9fba Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761060 Reviewed-by: Jeremy Bettis --- zephyr/test/drivers/src/bmi260.c | 47 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/zephyr/test/drivers/src/bmi260.c b/zephyr/test/drivers/src/bmi260.c index f4e62535a1..a4c713a7fb 100644 --- a/zephyr/test/drivers/src/bmi260.c +++ b/zephyr/test/drivers/src/bmi260.c @@ -152,6 +152,7 @@ static void bmi_init_emul(void) struct motion_sensor_t *ms_acc; struct motion_sensor_t *ms_gyr; struct i2c_emul *emul; + int ret; emul = bmi_emul_get(BMI_ORD); ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID]; @@ -163,8 +164,13 @@ static void bmi_init_emul(void) * which clears value set in this register before test. */ i2c_common_emul_set_read_func(emul, emul_init_ok, NULL); - zassert_equal(EC_RES_SUCCESS, ms_acc->drv->init(ms_acc), NULL); - zassert_equal(EC_RES_SUCCESS, ms_gyr->drv->init(ms_gyr), NULL); + + ret = ms_acc->drv->init(ms_acc); + zassert_equal(EC_RES_SUCCESS, ret, "Got accel init error %d", ret); + + ret = ms_gyr->drv->init(ms_gyr); + zassert_equal(EC_RES_SUCCESS, ret, "Got gyro init error %d", ret); + /* Remove custom emulator read function */ i2c_common_emul_set_read_func(emul, NULL, NULL); } @@ -1405,7 +1411,7 @@ ZTEST_USER(bmi260, test_bmi_gyr_read) ms->rot_standard_ref = NULL; } -/** Test acceleromtere calibration */ +/** Test accelerometer calibration */ ZTEST_USER(bmi260, test_bmi_acc_perform_calib) { struct motion_sensor_t *ms; @@ -1515,6 +1521,8 @@ ZTEST_USER(bmi260, test_bmi_gyr_perform_calib) emul = bmi_emul_get(BMI_ORD); ms = &motion_sensors[BMI_GYR_SENSOR_ID]; + bmi_init_emul(); + /* Range and rate cannot change after calibration */ range = 125; rate = 50000; @@ -2189,4 +2197,35 @@ ZTEST_USER(bmi260, test_init_config_status_timeout) EC_ERROR_INVALID_CONFIG, ret); } -ZTEST_SUITE(bmi260, drivers_predicate_post_main, NULL, NULL, NULL, NULL); +/** + * @brief Put the driver and emulator in to a consistent state before each test. + * + * @param arg Test fixture (unused) + */ +static void bmi260_test_before(void *arg) +{ + ARG_UNUSED(arg); + + struct i2c_emul *emul = bmi_emul_get(BMI_ORD); + struct motion_sensor_t *ms_acc = &motion_sensors[BMI_ACC_SENSOR_ID]; + struct motion_sensor_t *ms_gyr = &motion_sensors[BMI_GYR_SENSOR_ID]; + + /* Reset I2C */ + i2c_common_emul_set_read_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); + i2c_common_emul_set_write_fail_reg(emul, I2C_COMMON_EMUL_NO_FAIL_REG); + i2c_common_emul_set_read_func(emul, NULL, NULL); + i2c_common_emul_set_write_func(emul, NULL, NULL); + + /* Reset local fakes(s) */ + RESET_FAKE(bmi_config_load_no_mapped_flash_mock_read_fn); + + /* Clear rotation matrices */ + ms_acc->rot_standard_ref = NULL; + ms_gyr->rot_standard_ref = NULL; + + /* Set Chip ID register to BMI260 (required for init() to succeed) */ + bmi_emul_set_reg(emul, BMI260_CHIP_ID, BMI260_CHIP_ID_MAJOR); +} + +ZTEST_SUITE(bmi260, drivers_predicate_post_main, NULL, bmi260_test_before, NULL, + NULL); -- cgit v1.2.1 From 8350649cc3c82eb2d92f50c9e7eb03379fe2896b Mon Sep 17 00:00:00 2001 From: Sue Chen Date: Thu, 14 Jul 2022 09:17:04 +0800 Subject: Nissa: modify Amber LED RGB setting for Craask = <90, 10, 0> It's close to desired color of Amber LED. BUG=b:232656911 BRANCH=none TEST=the color of Amber LED on the Craask machine is desired color. Signed-off-by: Sue Chen Change-Id: I36964537f9c0e55a6119616896a3da9fc31f3fa0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760798 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/craask_pwm_leds.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/craask_pwm_leds.dts b/zephyr/projects/nissa/craask_pwm_leds.dts index c922d36f2f..bf0b24f312 100644 --- a/zephyr/projects/nissa/craask_pwm_leds.dts +++ b/zephyr/projects/nissa/craask_pwm_leds.dts @@ -25,7 +25,7 @@ color-map-blue = < 0 0 100>; color-map-yellow = < 0 50 50>; color-map-white = <100 100 100>; - color-map-amber = < 70 30 0>; + color-map-amber = < 90 10 0>; brightness-range = <100 100 100 0 0 0>; -- cgit v1.2.1 From 031615bd2a13cceabd3ad5e6660bb2e7bf53c2d8 Mon Sep 17 00:00:00 2001 From: madhurimaparuchuri Date: Thu, 14 Jul 2022 17:47:48 +0530 Subject: zephyr: shim: fan: Remove 'pwm-frequency' from device tree Remove 'pwm-frequency' from device tree as driver is consuming that information from 'period' of PWM spec BUG=b:230093078 BRANCH=none TEST=zmake testall TEST=check if fan_config structure has correct 'period_ns' value using gdb: gdb ./build/zephyr/${BOARD}/build-ro/zephyr/zephyr.elf p fan_config Signed-off-by: Madhurima Paruchuri Change-Id: I67d98f150330a950d4284df98a13e1048ef4aa57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759842 Reviewed-by: Fabio Baltieri --- zephyr/dts/bindings/fan/cros-ec,fans.yaml | 4 ---- zephyr/projects/brya/fan.dts | 1 - zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts | 1 - zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts | 1 - zephyr/projects/it8xxx2_evb/fan.dts | 1 - zephyr/projects/nissa/joxer_overlay.dts | 1 - zephyr/projects/nissa/nivviks_overlay.dts | 1 - zephyr/projects/nissa/pujjo_overlay.dts | 1 - zephyr/projects/npcx_evb/npcx7/fan.dts | 1 - zephyr/projects/npcx_evb/npcx9/fan.dts | 1 - zephyr/projects/skyrim/fan.dts | 1 - 11 files changed, 14 deletions(-) diff --git a/zephyr/dts/bindings/fan/cros-ec,fans.yaml b/zephyr/dts/bindings/fan/cros-ec,fans.yaml index ee1d8be891..5ca8071818 100644 --- a/zephyr/dts/bindings/fan/cros-ec,fans.yaml +++ b/zephyr/dts/bindings/fan/cros-ec,fans.yaml @@ -29,10 +29,6 @@ child-binding: required: true description: PWM channel to control the fan - pwm-frequency: - type: int - description: - PWM frequency in Hz. tach: type: phandle required: false diff --git a/zephyr/projects/brya/fan.dts b/zephyr/projects/brya/fan.dts index e67845757f..cc4e1fd6f8 100644 --- a/zephyr/projects/brya/fan.dts +++ b/zephyr/projects/brya/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm5 0 PWM_KHZ(1) PWM_POLARITY_NORMAL>; - pwm-frequency = <1000>; rpm_min = <2200>; rpm_start = <2200>; rpm_max = <4200>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts index 23f72dde94..87b83c0fd9 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; rpm_min = <3000>; rpm_start = <3000>; rpm_max = <10000>; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts index 99c2cf10d0..179091a343 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm3 0 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; rpm_min = <3200>; rpm_start = <2200>; rpm_max = <6600>; diff --git a/zephyr/projects/it8xxx2_evb/fan.dts b/zephyr/projects/it8xxx2_evb/fan.dts index faa659e6ad..39b02d9a98 100644 --- a/zephyr/projects/it8xxx2_evb/fan.dts +++ b/zephyr/projects/it8xxx2_evb/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; tach = <&tach0>; rpm_min = <1500>; rpm_start = <1500>; diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index 1960283135..93fa888404 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -262,7 +262,6 @@ fan_0 { pwms = <&pwm7 PWM_CHANNEL_7 PWM_KHZ(30) PWM_POLARITY_NORMAL>; - pwm-frequency = <30000>; tach = <&tach0>; rpm_min = <1500>; rpm_start = <1500>; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts index 7d9fb6008e..6ac2600dbe 100644 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ b/zephyr/projects/nissa/nivviks_overlay.dts @@ -245,7 +245,6 @@ fan_0 { pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; - pwm-frequency = <1000>; rpm_min = <2200>; rpm_start = <2200>; rpm_max = <4200>; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts index afa0b0b1c4..78e0522e9a 100644 --- a/zephyr/projects/nissa/pujjo_overlay.dts +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -245,7 +245,6 @@ fan_0 { pwms = <&pwm5 5 PWM_KHZ(1) PWM_POLARITY_NORMAL>; - pwm-frequency = <1000>; rpm_min = <2200>; rpm_start = <2200>; rpm_max = <4200>; diff --git a/zephyr/projects/npcx_evb/npcx7/fan.dts b/zephyr/projects/npcx_evb/npcx7/fan.dts index adfd71c95d..65653aa7df 100644 --- a/zephyr/projects/npcx_evb/npcx7/fan.dts +++ b/zephyr/projects/npcx_evb/npcx7/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; - pwm-frequency = <25000>; rpm_min = <1000>; rpm_start = <1000>; rpm_max = <5200>; diff --git a/zephyr/projects/npcx_evb/npcx9/fan.dts b/zephyr/projects/npcx_evb/npcx9/fan.dts index adfd71c95d..65653aa7df 100644 --- a/zephyr/projects/npcx_evb/npcx9/fan.dts +++ b/zephyr/projects/npcx_evb/npcx9/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; - pwm-frequency = <25000>; rpm_min = <1000>; rpm_start = <1000>; rpm_max = <5200>; diff --git a/zephyr/projects/skyrim/fan.dts b/zephyr/projects/skyrim/fan.dts index 042b9399dc..0b4c56e4c3 100644 --- a/zephyr/projects/skyrim/fan.dts +++ b/zephyr/projects/skyrim/fan.dts @@ -9,7 +9,6 @@ fan_0 { pwms = <&pwm0 0 PWM_KHZ(25) PWM_POLARITY_NORMAL>; - pwm-frequency = <25000>; rpm_min = <3100>; rpm_start = <3100>; rpm_max = <8000>; -- cgit v1.2.1 From 9ab0c7173ec74a13a8f96249d82e199adc700409 Mon Sep 17 00:00:00 2001 From: Dawid Niedzwiecki Date: Thu, 30 Jun 2022 14:33:39 +0200 Subject: zephyr: tests: restore firmware revision of PS8XXX Restore the firmware revision of PS8XXX emulator after changing it. BUG=b:233104826 TEST=zmake testall BRANCH=main Signed-off-by: Dawid Niedzwiecki Change-Id: Ie69a03f0ee033a85627f0d2579bbb58ee560b5ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3735404 Commit-Queue: Dawid Niedzwiecki Reviewed-by: Yuval Peress --- zephyr/test/drivers/src/ps8xxx.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/zephyr/test/drivers/src/ps8xxx.c b/zephyr/test/drivers/src/ps8xxx.c index 3cec82dc93..e376d4b671 100644 --- a/zephyr/test/drivers/src/ps8xxx.c +++ b/zephyr/test/drivers/src/ps8xxx.c @@ -1217,6 +1217,15 @@ static void ps8805_before(void *state) setup_no_fail_all(); } +static void ps8805_after(void *state) +{ + const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); + ARG_UNUSED(state); + + /* Set correct firmware revision */ + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); +} + /** * Setup PS8xxx emulator to mimic PS8815 and setup no fail for all I2C devices * associated with PS8xxx emulator @@ -1231,8 +1240,17 @@ static void ps8815_before(void *state) setup_no_fail_all(); } -ZTEST_SUITE(ps8805, drivers_predicate_post_main, NULL, ps8805_before, NULL, - NULL); +static void ps8815_after(void *state) +{ + const struct emul *ps8xxx_emul = emul_get_binding(PS8XXX_EMUL_LABEL); + ARG_UNUSED(state); + + /* Set correct firmware revision */ + tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x31); +} + +ZTEST_SUITE(ps8805, drivers_predicate_post_main, NULL, ps8805_before, + ps8805_after, NULL); -ZTEST_SUITE(ps8815, drivers_predicate_post_main, NULL, ps8815_before, NULL, - NULL); +ZTEST_SUITE(ps8815, drivers_predicate_post_main, NULL, ps8815_before, + ps8815_after, NULL); -- cgit v1.2.1 From bb424dba670a2ecf01635f590bc8adc915b9f329 Mon Sep 17 00:00:00 2001 From: Al Semjonovs Date: Wed, 13 Jul 2022 10:00:13 -0600 Subject: zephyr:test: Setup lpc_event_mask with correct events for CLEAR commands lpc_event_mask is missing appropriate mask to allow proper setup to validate the CLEAR command. BUG=b:238768443 BRANCH=none TEST=zmake test test-drivers (shuffled) Signed-off-by: Al Semjonovs Change-Id: Iecd3425c4f1c6496b7d8d35265364349d171cc9d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760656 Reviewed-by: Fabio Baltieri --- zephyr/test/drivers/src/host_cmd/host_event_commands.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/zephyr/test/drivers/src/host_cmd/host_event_commands.c b/zephyr/test/drivers/src/host_cmd/host_event_commands.c index 48b4d1a059..8efcd6b302 100644 --- a/zephyr/test/drivers/src/host_cmd/host_event_commands.c +++ b/zephyr/test/drivers/src/host_cmd/host_event_commands.c @@ -211,8 +211,12 @@ ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear__cmd) enum ec_status ret_val; host_event_t events; host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + host_event_t lpc_event_mask; struct ec_response_host_event_mask response = { 0 }; + lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI); + lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask); + host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY); events = host_get_events(); @@ -236,10 +240,13 @@ ZTEST_USER(host_cmd_host_event_commands, test_host_event_clear_b_cmd) enum ec_status ret_val; host_event_t events_b; host_event_t mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); - + host_event_t lpc_event_mask; struct ec_response_host_event_mask response = { 0 }; struct ec_response_host_event result = { 0 }; + lpc_event_mask = lpc_get_host_event_mask(LPC_HOST_EVENT_SMI); + lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, lpc_event_mask | mask); + host_set_single_event(EC_HOST_EVENT_KEYBOARD_RECOVERY); host_event_cmd_helper(EC_HOST_EVENT_GET, EC_HOST_EVENT_B, &result); -- cgit v1.2.1 From d9e025d3d3965e448ea73f7d8e1d3fc374c8f67e Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 14 Jul 2022 09:36:29 -0600 Subject: ec: Remove util pytests from CQ This is a partial revert of 3ee8dd3d69a467e695f4263d0aee1ebb26fced76 Remove the python unit tests from util/run_tests.sh because test_kconfig_check is flaky. BRANCH=None BUG=b:238773780 TEST=util/run_tests.sh Signed-off-by: Jeremy Bettis Change-Id: I8b3038e53d9767cd49a54ad0e1b94f417d6ff20d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763780 Reviewed-by: Keith Short Tested-by: Jeremy Bettis Commit-Queue: Jack Rosenthal Auto-Submit: Jeremy Bettis Commit-Queue: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Keith Short --- util/run_tests.sh | 3 --- 1 file changed, 3 deletions(-) diff --git a/util/run_tests.sh b/util/run_tests.sh index 9ec2523e89..8d6e87943b 100755 --- a/util/run_tests.sh +++ b/util/run_tests.sh @@ -15,9 +15,6 @@ set -e # cd to the ec directory. cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/.. -# Run pytest -pytest util "$@" - # Run shell tests cd util ./test-inject-keys.sh -- cgit v1.2.1 From f0d1b9dc2869e9d25cdfc7134216dea700794965 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 12 Jul 2022 15:47:42 -0700 Subject: printf: Remove NO_UINT64_SUPPORT The NO_UINT64_SUPPORT changes were added in commit 686a23585e2bc8a357842bd30ea3cae0cc5648da with the purpose of reducing size of the generated code. Now that we are using LTO, we have more headroom, so simplify the code by removing this define. BRANCH=none BUG=b:238433667, b:234181908 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: Ia126decf45f33c30581c42482f0ceb7b6453bd86 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760662 Reviewed-by: Eric Yilun Lin --- common/printf.c | 33 +++------------------------------ 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/common/printf.c b/common/printf.c index f19e6d3b21..b44ffdbafd 100644 --- a/common/printf.c +++ b/common/printf.c @@ -14,23 +14,6 @@ static const char error_str[] = "ERROR"; #define MAX_FORMAT 1024 /* Maximum chars in a single format field */ -#ifndef CONFIG_DEBUG_PRINTF -static inline int divmod(uint64_t *n, int d) -{ - return uint64divmod(n, d); -} - -#else /* CONFIG_DEBUG_PRINTF */ -/* if we are optimizing for size, remove the 64-bit support */ -#define NO_UINT64_SUPPORT -static inline int divmod(uint32_t *n, int d) -{ - int r = *n % d; - *n /= d; - return r; -} -#endif - /** * Convert the lowest nibble of a number to hex * @@ -50,13 +33,7 @@ static int hexdigit(int c) #define PF_LEFT BIT(0) /* Left-justify */ #define PF_PADZERO BIT(1) /* Pad with 0's not spaces */ #define PF_SIGN BIT(2) /* Add sign (+) for a positive number */ - -/* Deactivate the PF_64BIT flag is 64-bit support is disabled. */ -#ifdef NO_UINT64_SUPPORT -#define PF_64BIT 0 -#else #define PF_64BIT BIT(3) /* Number is 64-bit */ -#endif /* * Print the buffer as a string of bytes in hex. @@ -214,11 +191,8 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, } else { int base = 10; -#ifdef NO_UINT64_SUPPORT - uint32_t v; -#else uint64_t v; -#endif + int ptrspec; void *ptrval; @@ -281,7 +255,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, continue; /* %pT - print a timestamp. */ if (ptrspec == 'T' && - !IS_ENABLED(NO_UINT64_SUPPORT) && (!IS_ENABLED(CONFIG_ZEPHYR) || IS_ENABLED(CONFIG_PLATFORM_EC_TIMER))) { flags |= PF_64BIT; @@ -391,7 +364,7 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, * numbers. */ for (vlen = 0; vlen < precision; vlen++) - *(--vstr) = '0' + divmod(&v, 10); + *(--vstr) = '0' + uint64divmod(&v, 10); if (precision >= 0) *(--vstr) = '.'; @@ -399,7 +372,7 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, *(--vstr) = '0'; while (v) { - int digit = divmod(&v, base); + int digit = uint64divmod(&v, base); if (digit < 10) *(--vstr) = '0' + digit; else if (c == 'X') -- cgit v1.2.1 From 28ba9af251f448140f2e6cc224b2566052f326e8 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 14:30:00 -0700 Subject: baseboard/intelrvp: Enable LTO We're running low on flash space, so enable LTO. Before LTO: RO: 36 bytes in flash and 34972 bytes in RAM still available RW: 20 bytes in flash and 34972 bytes in RAM still available After LTO: RO: 8684 bytes in flash and 35268 bytes in RAM still available RW: 8604 bytes in flash and 35268 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I229e7532672f3bdc3040d6b428049a80144cc1e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761356 Reviewed-by: Keith Short --- baseboard/intelrvp/baseboard.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 035d7150ec..b003c5a785 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -21,6 +21,8 @@ #error "Define EC chip variant" #endif +#define CONFIG_LTO + /* * Allow dangerous commands. * TODO: Remove this config before production. -- cgit v1.2.1 From 0185e458d5371d38800fc17e1fa9297077f58e2c Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 15:06:46 -0700 Subject: baseboard/dedede: Enable LTO Before LTO (corori2): RO: 224 bytes in flash and 24704 bytes in RAM still available RW: 404 bytes in flash and 24704 bytes in RAM still available After LTO (corori2): RO: 8160 bytes in flash and 24896 bytes in RAM still available RW: 8296 bytes in flash and 24896 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I8a5e8118eefcb7b117ebefea5f15105bf4068fd5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761357 Reviewed-by: Ting Shen --- baseboard/dedede/baseboard.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index dff4cd5e7f..5c267f08bc 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_BASEBOARD_H #define __CROS_EC_BASEBOARD_H +#define CONFIG_LTO + /* * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. -- cgit v1.2.1 From a43baabc0bda3c1928fbdd075ccb323b75fb0f4b Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 15:06:55 -0700 Subject: baseboard/octopus: Enable LTO Before LTO (dood): RO: 360 bytes in flash and 30400 bytes in RAM still available RW: 404 bytes in flash and 30400 bytes in RAM still available After LTO (dood): RO: 12000 bytes in flash and 30944 bytes in RAM still available RW: 12116 bytes in flash and 30944 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: If66fd043259864ffa05d73a758a78e3ca2184334 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761358 Reviewed-by: Diana Z --- baseboard/octopus/baseboard.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index d29ae38170..0a54f0efac 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -12,6 +12,8 @@ * EC Config */ +#define CONFIG_LTO + /* * By default, enable all console messages excepted HC, ACPI and event: * The sensor stack is generating a lot of activity. -- cgit v1.2.1 From b769c8078f5ebb421e2a9deb64f67814697054af Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 15:14:31 -0700 Subject: board/fusb307bgevb: Enable LTO Before: RO: 220 bytes in flash and 5324 bytes in RAM still available RW: 4692 bytes in flash and 5324 bytes in RAM still available After: RO: 5596 bytes in flash and 5732 bytes in RAM still available RW: 10080 bytes in flash and 5732 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I1f28c5b8a876e72b169a60bc10557e02537d5bbb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761360 Reviewed-by: Keith Short --- board/fusb307bgevb/board.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/fusb307bgevb/board.h b/board/fusb307bgevb/board.h index df34096283..762ba5bed0 100644 --- a/board/fusb307bgevb/board.h +++ b/board/fusb307bgevb/board.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_BOARD_H #define __CROS_EC_BOARD_H +#define CONFIG_LTO + /* 48 MHz SYSCLK clock frequency */ #define CPU_CLOCK 48000000 -- cgit v1.2.1 From e76bc83b9ab25b0c3646c8c52b10c00daaacca51 Mon Sep 17 00:00:00 2001 From: Tomasz Michalec Date: Mon, 11 Jul 2022 17:56:48 +0200 Subject: zephyr: tests: reset flags of USB mux proxies Some tests set USB_MUX_FLAG_SET_WITHOUT_FLIP flag and do not clear it. This may result in fail in future test that doesn't expect the flag to be set. To prevent that, flags are cleared after each test. BUG=b:238860999 TEST=zmake test test-drivers BRANCH=None Signed-off-by: Tomasz Michalec Change-Id: Ic6269b6d3507daa4ce6399d77bf9d196ad3270c0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3758219 Reviewed-by: Abe Levkoy Tested-by: Tomasz Michalec Commit-Queue: Tomasz Michalec --- zephyr/test/drivers/src/usb_mux.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/zephyr/test/drivers/src/usb_mux.c b/zephyr/test/drivers/src/usb_mux.c index 0a8dbcf38f..8c899c1bd7 100644 --- a/zephyr/test/drivers/src/usb_mux.c +++ b/zephyr/test/drivers/src/usb_mux.c @@ -334,6 +334,11 @@ static void setup_usb_mux_proxy_chain(void) static void restore_usb_mux_chain(void) { memcpy(&usb_muxes[USBC_PORT_C1], &usb_mux_c1, sizeof(struct usb_mux)); + + /* Reset flags to default */ + proxy_chain_0.flags = 0; + proxy_chain_1.flags = 0; + proxy_chain_2.flags = 0; } /** -- cgit v1.2.1 From 4e0d43e882678663262d1036bbf89d22336e58b0 Mon Sep 17 00:00:00 2001 From: Tomasz Michalec Date: Wed, 13 Jul 2022 15:42:29 +0200 Subject: zephyr: tests: Disable ack_required in proxy_usb_mux Set ack_required to false in proxy_hpd_update and proxy_set functions. In test environment there is not possible to get ACK from AP which is not emulated, so returning ack_required == true, actually only introduce delay. During this delay, other thread may perform operation on USB mux which disturb test. To prevent that, ack_required is forced to false by proxy_usb_mux. BUG=b:238860999 TEST=zmake test test-drivers BRANCH=None Signed-off-by: Tomasz Michalec Change-Id: I6817e99461498beeacf639e3f457c64e5ddde874 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3758220 Commit-Queue: Tomasz Michalec Reviewed-by: Wai-Hong Tam Tested-by: Tomasz Michalec --- zephyr/test/drivers/src/usb_mux.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/zephyr/test/drivers/src/usb_mux.c b/zephyr/test/drivers/src/usb_mux.c index 8c899c1bd7..8fdadd5cde 100644 --- a/zephyr/test/drivers/src/usb_mux.c +++ b/zephyr/test/drivers/src/usb_mux.c @@ -74,6 +74,8 @@ static int proxy_set_custom(const struct usb_mux *me, mux_state_t mux_state, if (org_mux[i] != NULL && org_mux[i]->driver->set != NULL) { ec = org_mux[i]->driver->set(org_mux[i], mux_state, ack_required); + /* Disable waiting for ACK in tests */ + *ack_required = false; } if (task_get_current() == TASK_ID_TEST_RUNNER) { @@ -193,6 +195,8 @@ static void proxy_hpd_update_custom(const struct usb_mux *me, if (org_mux[i] != NULL && org_mux[i]->hpd_update != NULL) { org_mux[i]->hpd_update(org_mux[i], mux_state, ack_required); + /* Disable waiting for ACK in tests */ + *ack_required = false; } if (task_get_current() != TASK_ID_TEST_RUNNER) { -- cgit v1.2.1 From 635e718723d6d07e1fc590958679457249801e26 Mon Sep 17 00:00:00 2001 From: Tomasz Michalec Date: Wed, 13 Jul 2022 13:24:33 +0200 Subject: zephyr: tests: Fix test_ps8815_set_cc HW revision PS8815 set cc test requires specific HW revision to be set in PS8xxx emulator at the beginning. Some HW revisions introduces delay which may disturb flow of the test by allowing other tasks to execute at the same time. BUG=b:233105090 BRANCH=None TEST=zmake -D test test-drivers Signed-off-by: Tomasz Michalec Change-Id: I63f197e60d96ee488a3bedddc69de6ba34d069cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3758212 Tested-by: Tomasz Michalec Reviewed-by: Aaron Massey Commit-Queue: Tomasz Michalec --- zephyr/test/drivers/src/ps8xxx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/zephyr/test/drivers/src/ps8xxx.c b/zephyr/test/drivers/src/ps8xxx.c index e376d4b671..9832c53ce0 100644 --- a/zephyr/test/drivers/src/ps8xxx.c +++ b/zephyr/test/drivers/src/ps8xxx.c @@ -196,6 +196,13 @@ ZTEST(ps8815, test_ps8815_set_cc) int64_t start_time; int64_t delay; + /* + * Set other hw revision to disable workaround for b/171430855 (delay + * 1 ms on role control reg update). Delay could introduce thread switch + * which may disturb this test. + */ + ps8xxx_emul_set_hw_rev(ps8xxx_emul, 0x0a02); + /* Set firmware version <= 0x10 to set "disable rp detect" workaround */ tcpci_emul_set_reg(ps8xxx_emul, PS8XXX_REG_FW_REV, 0x8); zassert_equal(EC_SUCCESS, ps8xxx_tcpm_drv.init(USBC_PORT_C1), NULL); -- cgit v1.2.1 From 4e38e0394f6c60120198a3bca08585562a3697cf Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Mon, 4 Jul 2022 18:40:45 +0800 Subject: zephyr: board: Move common configs to Kconfig.defconfig Move common configs to Kconfig.defconfig. BUG=none BRANCH=none TEST=zmake build it8xxx2_evb --clobber zmake build krabby --clobber zmake build nereid --clobber Signed-off-by: Tim Lin Change-Id: I4890296d7a80ab9b06f1b65e227bd14dd0082b7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3745106 Commit-Queue: Jeremy Bettis Reviewed-by: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Keith Short --- zephyr/boards/riscv/it8xxx2/Kconfig.defconfig | 48 +++++++++++++++++++++++++++ zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig | 22 ------------ 2 files changed, 48 insertions(+), 22 deletions(-) diff --git a/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig index 6cf9bd039b..b21d0f2d7f 100644 --- a/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig +++ b/zephyr/boards/riscv/it8xxx2/Kconfig.defconfig @@ -11,4 +11,52 @@ choice PLATFORM_EC_HOSTCMD_DEBUG_MODE default HCDEBUG_OFF endchoice # PLATFORM_EC_HOSTCMD_DEBUG_MODE +config CROS_EC_HOOK_TICK_INTERVAL + default 500000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +if ADC +config PLATFORM_EC_ADC_RESOLUTION + default 10 +endif # ADC + +if CONSOLE +config UART_CONSOLE + default y + depends on SERIAL +endif # CONSOLE + +if FLASH +config PLATFORM_EC_CONSOLE_CMD_FLASH + default y +endif # FLASH + +if SERIAL +config UART_INTERRUPT_DRIVEN + default y +endif # SERIAL + +if SHELL +config SHELL_TAB + default y +config SHELL_TAB_AUTOCOMPLETION + default y +config SHELL_HISTORY + default y +endif # SHELL + +if WATCHDOG +config PLATFORM_EC_WATCHDOG_PERIOD_MS + default 2500 +config WDT_ITE_WARNING_LEADING_TIME_MS + default 500 +config WDT_ITE_REDUCE_WARNING_LEADING_TIME + default y +endif # WATCHDOG + endif # BOARD_IT8XXX2 diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig index a0cbbf4046..34612e9b42 100644 --- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig @@ -16,10 +16,6 @@ CONFIG_PM_POLICY_CUSTOM=y # Console CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SHELL_TAB=y -CONFIG_SHELL_TAB_AUTOCOMPLETION=y -CONFIG_SHELL_HISTORY=y # GPIO Controller CONFIG_GPIO=y @@ -29,32 +25,14 @@ CONFIG_GPIO=y # and should not be set to pull down inputs by default. CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN=n -# ADC Driver -CONFIG_PLATFORM_EC_ADC=y -CONFIG_PLATFORM_EC_ADC_RESOLUTION=10 - # Clock Controller CONFIG_CLOCK_CONTROL=n -# Timer configuration -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32768 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=32768 - -# Hook tick -CONFIG_CROS_EC_HOOK_TICK_INTERVAL=500000 - -# Flash -CONFIG_PLATFORM_EC_CONSOLE_CMD_FLASH=y - # Serial Drivers CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y # WATCHDOG configuration CONFIG_WATCHDOG=y -CONFIG_PLATFORM_EC_WATCHDOG_PERIOD_MS=2500 -CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS=500 -CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME=y # BBRAM CONFIG_BBRAM=y -- cgit v1.2.1 From 1225fa58f96396781e6895bce2dc3e80d86d0f1c Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Thu, 14 Jul 2022 11:26:34 -0600 Subject: kconfig_check: Exclude board, project, test files Instead of ignoring BOARD_ and VARIANT_ configs from the list of CONFIGs allowed to use in legacy EC, just don't parse the Kconfig files from board, test, project, or chip dirs. That gives better parity between the kconfiglib based logic and the grep based logic. This also prevents simple refactors like crrev/c/3745106 from breaking the unit test. BRANCH=None BUG=b:238773780 TEST=util/run_tests.sh && make -j40 buildall Signed-off-by: Jeremy Bettis Change-Id: Idf1d6a2ede86c587c092df1cf060200d178a881b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763781 Reviewed-by: Keith Short Tested-by: Jeremy Bettis Commit-Queue: Jeremy Bettis --- util/config_allowed.txt | 1 - util/kconfig_check.py | 8 ++++++++ util/run_tests.sh | 3 +++ util/test_kconfig_check.py | 14 +------------- 4 files changed, 12 insertions(+), 14 deletions(-) diff --git a/util/config_allowed.txt b/util/config_allowed.txt index e5c0c6aac5..c87d468053 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -855,7 +855,6 @@ CONFIG_SYNC_COMMAND CONFIG_SYNC_INT_EVENT CONFIG_SYNC_QUEUE_SIZE CONFIG_SYSTEM_UNLOCK -CONFIG_SYS_CLOCK_TICKS_PER_SEC CONFIG_SYV682X_HV_ILIM CONFIG_TASK_LIST CONFIG_TASK_PROFILING diff --git a/util/kconfig_check.py b/util/kconfig_check.py index db2bc09a5b..74dfcf183d 100755 --- a/util/kconfig_check.py +++ b/util/kconfig_check.py @@ -254,6 +254,14 @@ class KconfigCheck: ] if "Kconfig" in dirs: dirs.remove("Kconfig") + if "boards" in dirs: + dirs.remove("boards") + if "projects" in dirs: + dirs.remove("projects") + if "test" in dirs: + dirs.remove("test") + if "chip" in dirs: + dirs.remove("chip") return kconfig_files @classmethod diff --git a/util/run_tests.sh b/util/run_tests.sh index 8d6e87943b..9ec2523e89 100755 --- a/util/run_tests.sh +++ b/util/run_tests.sh @@ -15,6 +15,9 @@ set -e # cd to the ec directory. cd "$(dirname "$(realpath -e "${BASH_SOURCE[0]}")")"/.. +# Run pytest +pytest util "$@" + # Run shell tests cd util ./test-inject-keys.sh diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py index 3b6a80fc81..4c5a287ab6 100644 --- a/util/test_kconfig_check.py +++ b/util/test_kconfig_check.py @@ -219,22 +219,10 @@ rsource "subdir/Kconfig.wibble" # List of things missing from the Kconfig missing = sorted(list(set(adhoc_version) - set(kc_version))) - # The Kconfig is disjoint in some places, e.g. the boards have their - # own Kconfig files which are not included from the main Kconfig - missing = [ - item - for item in missing - if not item.startswith("BOARD") and not item.startswith("VARIANT") - ] - - # Similarly, some other items are defined in files that are not included + # Some items are defined in files that are not included # in all cases, only for particular values of $(ARCH) self.assertEqual( [ - "BUG209907615", - "FLASH_LOAD_OFFSET", - "NPCX_HEADER", - "SYS_CLOCK_HW_CYCLES_PER_SEC", "TRAP_UNALIGNED_ACCESS", ], missing, -- cgit v1.2.1 From 56d045e6d7af9bb93a8a7389e37b1410c48a1283 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Tue, 12 Jul 2022 17:16:48 -0600 Subject: py: Fix pylint errors discovered by cros lint Resolve all pylint warnings in these files. Disable fixme and too-many-arguments globally, because they are very common, and aren't really problems. BRANCH=None BUG=b:238434058 TEST=cros lint Change-Id: I94c410330d6d576d3cc9518503699a514a28758d Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760093 Tested-by: Jeremy Bettis Reviewed-by: Jack Rosenthal Commit-Queue: Jeremy Bettis --- firmware_builder.py | 19 +++++++++++-------- pylintrc | 7 ++++++- util/kconfig_check.py | 2 +- util/test_kconfig_check.py | 1 + 4 files changed, 19 insertions(+), 10 deletions(-) diff --git a/firmware_builder.py b/firmware_builder.py index 6c74bf8409..1a8f52df56 100755 --- a/firmware_builder.py +++ b/firmware_builder.py @@ -65,8 +65,8 @@ def build(opts): "When --code-coverage is selected, 'build' is a no-op. " "Run 'test' with --code-coverage instead." ) - with open(opts.metrics, "w") as f: - f.write(json_format.MessageToJson(metric_list)) + with open(opts.metrics, "w") as file: + file.write(json_format.MessageToJson(metric_list)) return ec_dir = pathlib.Path(__file__).parent @@ -90,8 +90,8 @@ def build(opts): ) if memsize_file.exists(): parse_memsize(memsize_file, metric, variant) - with open(opts.metrics, "w") as f: - f.write(json_format.MessageToJson(metric_list)) + with open(opts.metrics, "w") as file: + file.write(json_format.MessageToJson(metric_list)) # Ensure that there are no regressions for boards that build successfully # with clang: b/172020503. @@ -109,6 +109,7 @@ UNITS = { def parse_memsize(filename, metric, variant): + """Parse the output of the build to extract the image size.""" with open(filename, "r") as infile: # Skip header line infile.readline() @@ -122,6 +123,7 @@ def parse_memsize(filename, metric, variant): def bundle(opts): + """Bundle the artifacts.""" if opts.code_coverage: bundle_coverage(opts) else: @@ -147,8 +149,8 @@ def write_metadata(opts, info): bundle_metadata_file = ( opts.metadata if opts.metadata else DEFAULT_BUNDLE_METADATA_FILE ) - with open(bundle_metadata_file, "w") as f: - f.write(json_format.MessageToJson(info)) + with open(bundle_metadata_file, "w") as file: + file.write(json_format.MessageToJson(info)) def bundle_coverage(opts): @@ -207,8 +209,8 @@ def test(opts): """Runs all of the unit tests for EC firmware""" # TODO(b/169178847): Add appropriate metric information metrics = firmware_pb2.FwTestMetricList() - with open(opts.metrics, "w") as f: - f.write(json_format.MessageToJson(metrics)) + with open(opts.metrics, "w") as file: + file.write(json_format.MessageToJson(metrics)) # Run python unit tests. subprocess.run( @@ -266,6 +268,7 @@ def main(args): def parse_args(args): + """Parse all command line args and return opts dict.""" parser = argparse.ArgumentParser(description=__doc__) parser.add_argument( diff --git a/pylintrc b/pylintrc index 51f1236221..5af5f4e4dd 100644 --- a/pylintrc +++ b/pylintrc @@ -6,7 +6,12 @@ [MESSAGES CONTROL] -disable=bad-continuation,bad-whitespace +disable= + bad-continuation, + bad-whitespace, + # These have nothing to do with black, they are just annoying + fixme, + too-many-arguments [format] diff --git a/util/kconfig_check.py b/util/kconfig_check.py index 74dfcf183d..651078448d 100755 --- a/util/kconfig_check.py +++ b/util/kconfig_check.py @@ -470,7 +470,7 @@ def main(argv): search_paths=args.search_path, ignore=args.ignore, ) - elif args.cmd == "build": + if args.cmd == "build": return checker.do_build( configs_file=args.configs, srcdir=args.srctree, diff --git a/util/test_kconfig_check.py b/util/test_kconfig_check.py index 4c5a287ab6..d4942821ae 100644 --- a/util/test_kconfig_check.py +++ b/util/test_kconfig_check.py @@ -66,6 +66,7 @@ class KconfigCheck(unittest.TestCase): ) def check_read_configs(self, use_defines): + """Check that kconfigs can be read.""" checker = kconfig_check.KconfigCheck() with tempfile.NamedTemporaryFile() as configs: with open(configs.name, "w") as out: -- cgit v1.2.1 From 76bcd5c321529938f08fec8568b069965bbb547b Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Wed, 13 Jul 2022 19:21:39 +0800 Subject: adlrvpp_mchp1521: Free some flash size Undefine CONFIG_CMD_GETTIME to save some flash size BUG=none BRANCH=none TEST=make BOARD=adlrvpp_mchp1521 Before commit: *** 36 bytes in flash and 34972 bytes in RAM still available on adlrvpp_mchp1521 RO **** *** 16 bytes in flash and 34972 bytes in RAM still available on adlrvpp_mchp1521 RW **** After commit: *** 164 bytes in flash and 34972 bytes in RAM still available on adlrvpp_mchp1521 RO **** *** 124 bytes in flash and 34972 bytes in RAM still available on adlrvpp_mchp1521 RW **** Signed-off-by: Devin Lu Change-Id: Ia49d3443e65a0d6b0729c6e08a19bf954c33580a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759841 Tested-by: Devin Lu Reviewed-by: Diana Z Commit-Queue: Diana Z --- board/adlrvpp_mchp1521/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h index 7a4f3ba728..94dd27fe81 100644 --- a/board/adlrvpp_mchp1521/board.h +++ b/board/adlrvpp_mchp1521/board.h @@ -20,6 +20,7 @@ #undef CONFIG_CMD_ADC #undef CONFIG_CMD_APTHROTTLE #undef CONFIG_CMD_BATTFAKE +#undef CONFIG_CMD_GETTIME /* * Macros for GPIO signals used in common code that don't match the -- cgit v1.2.1 From 64c42ed1907d5e66b827e1bf74b0892f5cb10c4c Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 15:08:43 -0700 Subject: board/terrador: Free up more flash space Before: RO: 160 bytes in flash and 21632 bytes in RAM still available RW: 312 bytes in flash and 21632 bytes in RAM still available After: RO: 480 bytes in flash and 21664 bytes in RAM still available RW: 672 bytes in flash and 21664 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=none Signed-off-by: Tom Hughes Change-Id: I5bcf28877a5e093a29c2eef0cf755f6f66308849 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761359 Reviewed-by: Abe Levkoy --- board/terrador/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/terrador/board.h b/board/terrador/board.h index 617d8737b3..59c86e0139 100644 --- a/board/terrador/board.h +++ b/board/terrador/board.h @@ -14,6 +14,7 @@ /* Free flash space */ #define CONFIG_USB_PD_DEBUG_LEVEL 2 #undef CONFIG_CONSOLE_CMDHELP +#undef CONFIG_CMD_BATTFAKE /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ -- cgit v1.2.1 From f9bbc1f59586878d9bbb9eac25e959e306661e67 Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Thu, 14 Jul 2022 12:12:10 -0600 Subject: Skyrim: Remove guybrush support Skyrim hardware is available now, so remove guybrush as a skyrim "variant". BUG=b:231996904 TEST=emerge-skyrim chromeos-zephyr BRANCH=None Change-Id: Id8084000b112fe38a8f9556688e4d9c8edd68b10 Signed-off-by: Tim Van Patten Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763782 Reviewed-by: Diana Z --- zephyr/projects/skyrim/BUILD.py | 3 - zephyr/projects/skyrim/CMakeLists.txt | 4 - zephyr/projects/skyrim/Kconfig | 6 - zephyr/projects/skyrim/guybrush.dts | 198 -------- zephyr/projects/skyrim/power_signals_guybrush.c | 127 ----- zephyr/projects/skyrim/prj_guybrush.conf | 9 - zephyr/projects/skyrim/usbc_config_guybrush.c | 599 ------------------------ 7 files changed, 946 deletions(-) delete mode 100644 zephyr/projects/skyrim/guybrush.dts delete mode 100644 zephyr/projects/skyrim/power_signals_guybrush.c delete mode 100644 zephyr/projects/skyrim/prj_guybrush.conf delete mode 100644 zephyr/projects/skyrim/usbc_config_guybrush.c diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py index 3d43b3676b..a8b2da3716 100644 --- a/zephyr/projects/skyrim/BUILD.py +++ b/zephyr/projects/skyrim/BUILD.py @@ -33,6 +33,3 @@ def register_variant(project_name): register_variant(project_name="skyrim") - -# TODO: Deprecate guybrush build after skyrim hardware is readily available. -# register_variant(project_name="guybrush") diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt index b364421eb4..09a6afd130 100644 --- a/zephyr/projects/skyrim/CMakeLists.txt +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -5,16 +5,12 @@ cmake_minimum_required(VERSION 3.13.1) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(guybrush) cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) -cros_ec_library_include_directories_ifdef(CONFIG_BOARD_GUYBRUSH include_guybrush) zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "power_signals.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "power_signals_guybrush.c") zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "usbc_config.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "usbc_config_guybrush.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "usb_pd_policy.c") diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig index ea68baf71b..6da27ee2d0 100644 --- a/zephyr/projects/skyrim/Kconfig +++ b/zephyr/projects/skyrim/Kconfig @@ -2,12 +2,6 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -config BOARD_GUYBRUSH - bool "Google Guybrush Board" - help - Build Google Guybrush reference board. This board build is a - prototype rather than a releasing product. - config BOARD_SKYRIM bool "Google Skyrim Board" help diff --git a/zephyr/projects/skyrim/guybrush.dts b/zephyr/projects/skyrim/guybrush.dts deleted file mode 100644 index 6c5c72d061..0000000000 --- a/zephyr/projects/skyrim/guybrush.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - aliases { - gpio-wp = &gpio_wp; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - named-gpios { - /* Guybrush-specific GPIO customizations */ - gpio_wp: ec_wp_l { - gpios = <&gpio5 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { - gpios = <&gpio0 1 GPIO_INPUT>; - }; - gpio_slp_s3_s0i3_l: slp_s3_s0i3_l { - gpios = <&gpio7 4 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S0_L"; - }; - gpio_ec_pcore_int_odl: ec_pcore_int_odl { - gpios = <&gpiof 0 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_groupc_s0_od: pg_groupc_s0_od { - gpios = <&gpioa 3 GPIO_INPUT>; - }; - gpio_pg_lpddr4x_s3_od: pg_lpddr4x_s3_od { - gpios = <&gpio9 5 GPIO_INPUT>; - }; - ec_soc_pwr_good { - gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_PCH_SYS_PWROK"; - }; - ec_entering_rw { - gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; - }; - ec_clr_cmos { - gpios = <&gpioa 1 GPIO_OUTPUT_LOW>; - }; - ec_mem_event { - gpios = <&gpioa 5 GPIO_OUTPUT_LOW>; - }; - gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { - gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - ec_soc_int_l { - gpios = <&gpio8 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - soc_thermtrip_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - }; - gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl { - gpios = <&gpio7 3 GPIO_ODR_HIGH>; - }; - 3axis_int_l { - gpios = <&gpioa 2 GPIO_INPUT_PULL_DOWN>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - ec_ps2_clk { - gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_dat { - gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_rst { - gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; - }; - ec_gpiob0 { - gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; - }; - ec_gpio81 { - gpios = <&gpio8 1 GPIO_INPUT_PULL_UP>; - }; - ec_psl_gpo { - gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>; - }; - ec_pwm7 { - gpios = <&gpio6 0 GPIO_INPUT_PULL_UP>; - }; - gpio_accel_gyro_int_l: accel_gyro_int_l { - gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* Low voltage on I2C6_1 */ - lvol-io-pads = <&lvol_ioe4 &lvol_ioe3>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_temp_soc: temp-soc { - label = "SOC"; - enum-name = "ADC_TEMP_SENSOR_SOC"; - io-channels = <&adc0 0>; - }; - }; - - named-temp-sensors { - soc-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "SOC"; - enum-name = "TEMP_SENSOR_SOC"; - tmp112-name = "TMP112_SOC"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS0"; - temp_host_high = <100>; - temp_host_halt = <105>; - temp_host_release_high = <80>; - temp_fan_off = <0>; - temp_fan_max = <70>; - }; - amb-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "Ambient"; - enum-name = "TEMP_SENSOR_AMB"; - tmp112-name = "TMP112_AMB"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS1"; - }; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_pg_lpddr4x_s3: pg_lpddr4x_s3 { - irq-pin = <&gpio_pg_lpddr4x_s3_od>; - flags = ; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_slp_s3_s0i3: slp_s3_s0i3 { - irq-pin = <&gpio_slp_s3_s0i3_l>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_ec_pwr_btn: ec_pwr_btn { - irq-pin = <&gpio_ec_pwr_btn_odl>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_ec_pcore: ec_pcore { - irq-pin = <&gpio_ec_pcore_int_odl>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_pg_groupc_s0: pg_groupc_s0 { - irq-pin = <&gpio_pg_groupc_s0_od>; - flags = ; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_s0_pgood: s0_pgood { - irq-pin = <&gpio_s0_pgood>; - flags = ; - handler = "power_signal_interrupt"; - }; - }; - - /* Rotation matrices for motion sensors. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 - 0 0 (-1)>; - }; - }; -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c deleted file mode 100644 index ba9eb1a92f..0000000000 --- a/zephyr/projects/skyrim/power_signals_guybrush.c +++ /dev/null @@ -1,127 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "chipset.h" -#include "config.h" -#include "gpio_signal.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "power.h" -#include "timer.h" - -/* Wake Sources */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* Power Signal Input List */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S0_N] = { - .gpio = GPIO_PCH_SLP_S0_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S0_DEASSERTED", - }, - [X86_SLP_S3_N] = { - .gpio = GPIO_PCH_SLP_S3_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S3_DEASSERTED", - }, - [X86_SLP_S5_N] = { - .gpio = GPIO_PCH_SLP_S5_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S5_DEASSERTED", - }, - [X86_S0_PGOOD] = { - .gpio = GPIO_S0_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S0_PGOOD", - }, - [X86_S5_PGOOD] = { - .gpio = GPIO_S5_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S5_PGOOD", - }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -static void baseboard_interrupt_init(void) -{ - /* Enable Power Group interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr4x_s3)); -} -DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_POST_I2C); - -/** - * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting - * PCH_PWRBTN_L. - */ -void board_pwrbtn_to_pch(int level) -{ - timestamp_t start; - const uint32_t timeout_rsmrst_rise_us = 30 * MSEC; - - /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ - if (!level && - !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) { - start = get_time(); - do { - usleep(200); - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_ec_soc_rsmrst_l))) - break; - } while (time_since32(start) < timeout_rsmrst_rise_us); - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) - ccprints("Error pwrbtn: RSMRST_L still low"); - - msleep(16); - } - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level); -} - -void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) -{ - /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_pg_lpddr4x_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_pg_groupc_s0_od))); -} - -void baseboard_en_pwr_s0(enum gpio_signal signal) -{ - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); - - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} - -void baseboard_s5_pgood(enum gpio_signal signal) -{ - baseboard_en_pwr_s0(signal); -} - -void baseboard_set_en_pwr_s3(enum gpio_signal signal) -{ - /* EC has no EN_PWR_S3 on this board */ - - /* Chain off the normal power signal interrupt handler */ - power_signal_interrupt(signal); -} diff --git a/zephyr/projects/skyrim/prj_guybrush.conf b/zephyr/projects/skyrim/prj_guybrush.conf deleted file mode 100644 index 0ca57174a4..0000000000 --- a/zephyr/projects/skyrim/prj_guybrush.conf +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Guybrush board-specific Kconfig settings. -CONFIG_BOARD_GUYBRUSH=y - -# Only Guybrush has TMP112 -CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112=y \ No newline at end of file diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c deleted file mode 100644 index ef9a47e52c..0000000000 --- a/zephyr/projects/skyrim/usbc_config_guybrush.c +++ /dev/null @@ -1,599 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush family-specific USB-C configuration */ - -#include "cros_board_info.h" -#include "battery_fuel_gauge.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state_v2.h" -#include "charge_state.h" -#include "charger.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/retimer/anx7491.h" -#include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" -#include "driver/tcpm/nct38xx.h" -#include "driver/usb_mux/anx7451.h" -#include "driver/usb_mux/amd_fp6.h" -#include "gpio.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "ioexpander.h" -#include "power.h" -#include "usb_mux.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) - -/* USB-A ports */ -enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; - -/* USB-C ports */ -enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; -BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); - -static void reset_nct38xx_port(int port); - -static void usbc_interrupt_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); - - /* Enable TCPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); - - /* Enable BC 1.2 interrupts */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); - - /* TODO: Enable SBU fault interrupts (io expander )*/ -} -DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); - -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* - * .init is not necessary here because it has nothing - * to do. Primary mux will handle mux state so .get is - * not needed as well. usb_mux.c can handle the situation - * properly. - */ -static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t, bool *); -struct usb_mux_driver usbc0_sbu_mux_driver = { - .set = fsusb42umx_set_mux, -}; - -/* - * Since FSUSB42UMX is not a i2c device, .i2c_port and - * .i2c_addr_flags are not required here. - */ -struct usb_mux usbc0_sbu_mux = { - .usb_port = USBC_PORT_C0, - .driver = &usbc0_sbu_mux_driver, -}; - -__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: PS8818 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_c1_ps8818_mux_set, -}; - -/* - * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default - * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c - * address to 0x2A. ANX7491(A1) will stay at the default 0x29. - */ -uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me) -{ - ASSERT(me->usb_port == USBC_PORT_C1); - return 0x2a; -} - -__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: ANX7451 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_anx7451 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS, - .driver = &anx7451_usb_mux_driver, - .board_set = &board_c1_anx7451_mux_set, -}; - -struct usb_mux usb_muxes[] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .next_mux = &usbc0_sbu_mux, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ - } -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* - * USB C0 port SBU mux use standalone FSUSB42UMX - * chip and it needs a board specific driver. - * Overall, it will use chained mux framework. - */ -static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state, - bool *ack_required) -{ - /* This driver does not use host command ACKs */ - *ack_required = false; - - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); - - return EC_SUCCESS; -} - -static void setup_mux(void) -{ - /* TODO: Fill in C1 mux based on CBI */ - CPRINTSUSB("C1: Setting ANX7451 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; -} -DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int rv; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * If this port had booted in dead battery mode, go - * ahead and reset it so EN_SNK responds properly. - */ - if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } - - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - /* - * Check if we can reset any ports in dead battery mode - * - * The NCT3807 may continue to keep EN_SNK low on the dead battery port - * and allow a dangerous level of voltage to pass through to the initial - * charge port (see b/183660105). We must reset the ports if we have - * sufficient battery to do so, which will bring EN_SNK back under - * normal control. - */ - rv = EC_SUCCESS; - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { - CPRINTSUSB("Found dead battery on %d", i); - /* - * If we have battery, get this port reset ASAP. - * This means temporarily rejecting charge manager - * sets to it. - */ - if (pd_is_battery_capable()) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - - if (port == i) - rv = EC_ERROR_INVAL; - } else if (port != i) { - /* - * If other port is selected and in dead battery - * mode, reset this port. Otherwise, reject - * change because we'll brown out. - */ - if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } else { - rv = EC_ERROR_INVAL; - } - } - } - } - - if (rv != EC_SUCCESS) - return rv; - - /* Check if the port is sourcing VBUS. */ - if (tcpm_get_src_ctrl(port)) { - CPRINTSUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) -{ - int rv = EC_SUCCESS; - - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); - - return rv; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, - int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - -/* TODO: sbu_fault_interrupt from io expander */ - -/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 -static void set_ac_prochot(void) -{ - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); -} -DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -static void reset_nct38xx_port(int port) -{ - const struct gpio_dt_spec *reset_gpio_l; - - /* TODO: Save and restore ioex signals */ - if (port == USBC_PORT_C0) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l); - else if (port == USBC_PORT_C1) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l); - else - /* Invalid port: do nothing */ - return; - - gpio_pin_set_dt(reset_gpio_l, 0); - msleep(NCT38XX_RESET_HOLD_DELAY_MS); - gpio_pin_set_dt(reset_gpio_l, 1); - nct38xx_reset_notify(port); - if (NCT3807_RESET_POST_DELAY_MS != 0) - msleep(NCT3807_RESET_POST_DELAY_MS); -} - -void board_reset_pd_mcu(void) -{ - /* Reset TCPC0 */ - reset_nct38xx_port(USBC_PORT_C0); - - /* Reset TCPC1 */ - reset_nct38xx_port(USBC_PORT_C1); -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_usb_c0_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_usb_c1_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_INT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/** - * Return if VBUS is sagging too low - * - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current - * until voltage drops to 4.5V. Don't go lower than this to be kind to the - * charger (see b/67964166). - */ -#define BC12_MIN_VOLTAGE 4500 -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage = 0; - int rv; - - rv = charger_get_vbus_voltage(port, &voltage); - - if (rv) { - CPRINTSUSB("%s rv=%d", __func__, rv); - return 0; - } - - /* - * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown - * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. - * This partly defeats the point of ramping, but will still catch - * VBUS below 4.5V and above 0V. - */ - if (voltage == 0) { - CPRINTSUSB("%s vbus=0", __func__); - return 0; - } - - if (voltage < BC12_MIN_VOLTAGE) - CPRINTSUSB("%s vbus=%d", __func__, voltage); - - return voltage < BC12_MIN_VOLTAGE; -} - -#define SAFE_RESET_VBUS_DELAY_MS 900 -#define SAFE_RESET_VBUS_MV 5000 -void board_hibernate(void) -{ - int port; - enum ec_error_list ret; - - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851, b/143778351, b/147007265) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) { - pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); - - /* Give PD task and PPC chip time to get to 5V */ - msleep(SAFE_RESET_VBUS_DELAY_MS); - } - - /* Try to put our battery fuel gauge into sleep mode */ - ret = battery_sleep_fuel_gauge(); - if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED)) - cprints(CC_SYSTEM, "Failed to send battery sleep command"); -} - -__overridable enum ec_error_list -board_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); - } while (rv && --tries); - - if (rv) { - CPRINTSUSB("A1: PS8811 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: PS8811 retimer detected"); - rv = board_a1_ps8811_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv); - return rv; -} - -/* - * PS8811 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_ps8811 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3, - .board_init = &baseboard_a1_ps8811_retimer_init, -}; - -__overridable enum ec_error_list -board_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val); - } while (rv && --tries); - if (rv) { - CPRINTSUSB("A1: ANX7491 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: ANX7491 retimer detected"); - rv = board_a1_anx7491_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv); - return rv; -} - -/* - * ANX7491 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_anx7491 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS, - .board_init = &baseboard_a1_anx7491_retimer_init, -}; - -void baseboard_a1_retimer_setup(void) -{ - struct usb_mux a1_retimer; - - /* TODO: Support PS8811 retimer through CBI */ - a1_retimer = usba1_anx7491; - a1_retimer.board_init(&a1_retimer); -} -DECLARE_DEFERRED(baseboard_a1_retimer_setup); - -/* TODO: Remove when guybrush is no longer supported */ -#ifdef CONFIG_BOARD_GUYBRUSH -void board_overcurrent_event(int port, int is_overcurrented) -{ - switch (port) { - case USBC_PORT_C0: - case USBC_PORT_C1: - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_c1_fault_odl), - !is_overcurrented); - break; - - default: - break; - } -} -#endif -- cgit v1.2.1 From 30a6f0b700ef21b73abf79ea0245977ae7f29234 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Thu, 14 Jul 2022 14:00:09 -0600 Subject: SB RMI: Add timer header Add timer.h to ensure the driver can compile with zephyr. BRANCH=None BUG=b:231994602 TEST=zmake testall Signed-off-by: Diana Z Change-Id: Ia7b32978c3bb619239efc8a7fc01a6b7d3778212 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3764068 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- driver/sb_rmi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/driver/sb_rmi.c b/driver/sb_rmi.c index 44bf4b9f42..4dc8e1684c 100644 --- a/driver/sb_rmi.c +++ b/driver/sb_rmi.c @@ -12,6 +12,7 @@ #include "sb_rmi.h" #include "stdbool.h" #include "time.h" +#include "timer.h" #include "util.h" /* Console output macros */ -- cgit v1.2.1 From 0af6883ab3c5e60466ca4a5e64503b6298b237e9 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Thu, 14 Jul 2022 13:58:55 -0600 Subject: Zephyr: Enable STT driver build Enable the STT and related SB RMI driver to build in zephyr. BRANCH=None BUG=b:231994602 TEST=zmake testall Signed-off-by: Diana Z Change-Id: I4ca6672f0cf5addc47a4e1187a4e74fad15d40c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3764069 Commit-Queue: Robert Zieba Reviewed-by: Robert Zieba --- zephyr/CMakeLists.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 2f8b214abb..8e42570a6f 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -189,6 +189,10 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ALS_CM32183 "${PLATFORM_EC}/driver/als_cm32183.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACPI "${PLATFORM_EC}/common/acpi.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_SB_RMI + "${PLATFORM_EC}/driver/sb_rmi.c") +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT + "${PLATFORM_EC}/driver/amd_stt.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BACKLIGHT_LID "${PLATFORM_EC}/common/backlight_lid.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_BATTERY -- cgit v1.2.1 From b05bf8a1c165139b64aea7279320c9bca3b1b9fa Mon Sep 17 00:00:00 2001 From: Diana Z Date: Thu, 14 Jul 2022 14:01:08 -0600 Subject: Skyrim: Enable STT reporting Enable the EC to send temperatures to the AP to support the STT feature. BRANCH=None BUG=b:231994602 TEST=on skyrim A2, boot up and ensure transactions with the AP succeed once the AP has booted enough Signed-off-by: Diana Z Change-Id: I42b631b55e0ab295501a3cea3e5336008dfef681 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3764070 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/CMakeLists.txt | 3 +++ zephyr/projects/skyrim/prj.conf | 2 ++ zephyr/projects/skyrim/stt.c | 26 ++++++++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 zephyr/projects/skyrim/stt.c diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt index 09a6afd130..bc4c51b40a 100644 --- a/zephyr/projects/skyrim/CMakeLists.txt +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -17,3 +17,6 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON "led.c") + +zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT + "stt.c") diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index c6b5d3a537..9717aa9d2c 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -41,6 +41,8 @@ CONFIG_PLATFORM_EC_BOARD_VERSION_CBI=y CONFIG_PLATFORM_EC_CBI_EEPROM=y # Temperature Sensors +CONFIG_PLATFORM_EC_AMD_SB_RMI=y +CONFIG_PLATFORM_EC_AMD_STT=y CONFIG_PLATFORM_EC_TEMP_SENSOR=y CONFIG_PLATFORM_EC_TEMP_SENSOR_SB_TSI=y CONFIG_PLATFORM_EC_THERMISTOR=y diff --git a/zephyr/projects/skyrim/stt.c b/zephyr/projects/skyrim/stt.c new file mode 100644 index 0000000000..e78e712737 --- /dev/null +++ b/zephyr/projects/skyrim/stt.c @@ -0,0 +1,26 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Support code for STT temperature reporting */ + +#include "chipset.h" +#include "temp_sensor/pct2075.h" +#include "temp_sensor/temp_sensor.h" + +int board_get_soc_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_SOC, temp_mk); +} + +int board_get_ambient_temp_mk(int *temp_mk) +{ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) + return EC_ERROR_NOT_POWERED; + + return pct2075_get_val_mk(PCT2075_AMB, temp_mk); +} -- cgit v1.2.1 From 440ae3333ac2431686b01316a6cc3650cbb5580d Mon Sep 17 00:00:00 2001 From: Diana Z Date: Wed, 13 Jul 2022 14:15:00 -0600 Subject: Skyrim: Enable SoC thermtrip interrupt Enable the SoC thermtrip interrupt, logging and shutting down the system if it occurs. Note this separates the thermtrip from the OCP interrupt, which had previously been enabled together. BRANCH=None BUG=b:237563166 TEST=on skyrim A2 and D1, boot and shut down without seeing any interrupt trip Signed-off-by: Diana Z Change-Id: Ic190c00d7a9649328f40344222b92db93df716d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761364 Commit-Queue: Robert Zieba Reviewed-by: Robert Zieba --- zephyr/projects/skyrim/interrupts.dts | 5 +++++ zephyr/projects/skyrim/power_signals.c | 9 +++++++++ zephyr/projects/skyrim/skyrim.dts | 3 +-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/zephyr/projects/skyrim/interrupts.dts b/zephyr/projects/skyrim/interrupts.dts index 14a01c8402..b53fabe207 100644 --- a/zephyr/projects/skyrim/interrupts.dts +++ b/zephyr/projects/skyrim/interrupts.dts @@ -42,6 +42,11 @@ flags = ; handler = "baseboard_set_en_pwr_pcore"; }; + int_soc_thermtrip: soc_thermtrip { + irq-pin = <&gpio_soc_thermtrip_odl>; + flags = ; + handler = "baseboard_soc_thermtrip"; + }; int_volume_up: volume_up { irq-pin = <&gpio_volup_btn_odl>; flags = ; diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index 8de1c833c4..c3d1826d78 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -77,6 +77,9 @@ static void baseboard_init(void) gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3)); + + /* Enable thermtrip interrupt */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip)); } DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C); @@ -193,3 +196,9 @@ void baseboard_set_en_pwr_s3(enum gpio_signal signal) /* Chain off the normal power signal interrupt handler */ power_signal_interrupt(signal); } + +void baseboard_soc_thermtrip(enum gpio_signal signal) +{ + ccprints("SoC thermtrip reported, shutting down"); + chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL); +} diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index dae7387ffb..84b8e364c4 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -24,8 +24,7 @@ gpio_ec_i2c_usbc_pd_int: ec_i2c_usbc_pd_int { gpios = <&gpioa 3 GPIO_INPUT>; }; - /* TODO: Add interrupt handler */ - soc_thermtrip_odl { + gpio_soc_thermtrip_odl: soc_thermtrip_odl { gpios = <&gpio9 5 GPIO_INPUT>; }; gpio_hub_rst: hub_rst { -- cgit v1.2.1 From 26e3fe318448df383d5decf09f76a6c04786afc4 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Mon, 6 Jun 2022 19:06:49 +0800 Subject: TCPCI: nct38xx: Only restore mask registers during hard reset Currently the mask registers will be reseted after hard reset received. TCPM did full initialization and restore the mask registers as well. However, full initialization will cause tPSHardReset time to worse. To improve tPSHardReset time during hard reset, so only restore the mask registers during hard reset. BUG=b:232326002 BRANCH=none TEST=On Vell. Check tPSHardReset time. Signed-off-by: Devin Lu Change-Id: I2ae250af7cb06fe5102c8ba4dce98e5d467a2d93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3702883 Tested-by: Devin Lu Reviewed-by: Abe Levkoy Reviewed-by: Diana Z Commit-Queue: Diana Z --- driver/tcpm/nct38xx.c | 1 + driver/tcpm/tcpci.c | 18 ++++++++++++++++++ include/driver/tcpm/tcpci.h | 2 ++ include/driver/tcpm/tcpm.h | 7 +++++++ include/usb_pd_tcpm.h | 13 +++++++++++++ 5 files changed, 41 insertions(+) diff --git a/driver/tcpm/nct38xx.c b/driver/tcpm/nct38xx.c index 16e0866ca6..810f92c6f8 100644 --- a/driver/tcpm/nct38xx.c +++ b/driver/tcpm/nct38xx.c @@ -393,4 +393,5 @@ const struct tcpm_drv nct38xx_tcpm_drv = { .set_frs_enable = &nct38xx_set_frs_enable, #endif .handle_fault = &nct3807_handle_fault, + .hard_reset_reinit = &tcpci_hard_reset_reinit, }; diff --git a/driver/tcpm/tcpci.c b/driver/tcpm/tcpci.c index 51451041ee..4775da6db3 100644 --- a/driver/tcpm/tcpci.c +++ b/driver/tcpm/tcpci.c @@ -1080,6 +1080,21 @@ static int tcpci_handle_fault(int port, int fault) return rv; } +int tcpci_hard_reset_reinit(int port) +{ + int rv; + + /* Initialize power_status_mask */ + rv = init_power_status_mask(port); + /* Initialize alert_mask */ + rv |= init_alert_mask(port); + + CPRINTS("C%d: Hard Reset re-initialize %s", port, + rv ? "failed" : "success"); + + return rv; +} + enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable) { int rv; @@ -1270,6 +1285,9 @@ void tcpci_tcpc_alert(int port) if (alert & TCPC_REG_ALERT_RX_HARD_RST) { /* hard reset received */ CPRINTS("C%d Hard Reset received", port); + + tcpm_hard_reset_reinit(port); + pd_event |= PD_EVENT_RX_HARD_RESET; } diff --git a/include/driver/tcpm/tcpci.h b/include/driver/tcpm/tcpci.h index 50fcb6ed64..aa81a0b409 100644 --- a/include/driver/tcpm/tcpci.h +++ b/include/driver/tcpm/tcpci.h @@ -327,6 +327,8 @@ int tcpci_tcpc_drp_toggle(int port); int tcpci_enter_low_power_mode(int port); void tcpci_wake_low_power_mode(int port); #endif +int tcpci_hard_reset_reinit(int port); + enum ec_error_list tcpci_set_bist_test_mode(const int port, const bool enable); void tcpci_tcpc_discharge_vbus(int port, int enable); void tcpci_tcpc_enable_auto_discharge_disconnect(int port, int enable); diff --git a/include/driver/tcpm/tcpm.h b/include/driver/tcpm/tcpm.h index 52ddba9e7e..24f3c6af89 100644 --- a/include/driver/tcpm/tcpm.h +++ b/include/driver/tcpm/tcpm.h @@ -382,6 +382,13 @@ static inline int tcpm_get_chip_info(int port, int live, return EC_ERROR_UNIMPLEMENTED; } +static inline int tcpm_hard_reset_reinit(int port) +{ + if (tcpc_config[port].drv->hard_reset_reinit) + return tcpc_config[port].drv->hard_reset_reinit(port); + return EC_ERROR_UNIMPLEMENTED; +} + static inline enum ec_error_list tcpc_set_bist_test_mode(int port, bool enable) { const struct tcpm_drv *tcpc; diff --git a/include/usb_pd_tcpm.h b/include/usb_pd_tcpm.h index 29f27c655c..b0338f6962 100644 --- a/include/usb_pd_tcpm.h +++ b/include/usb_pd_tcpm.h @@ -491,6 +491,19 @@ struct tcpm_drv { */ int (*handle_fault)(int port, int fault); + /** + * Re-initialize registers during hard reset + * + * NOTE: If the function alters the alert mask and power status mask, + * this indicates the chip does not require a full TCPCI re-init after + * a hard reset. + * + * @param port Type-C port number + * + * @return EC_SUCCESS or error + */ + int (*hard_reset_reinit)(int port); + /** * Controls BIST Test Mode (or analogous functionality) in the TCPC and * associated behavior changes. Disables message Rx alerts while the -- cgit v1.2.1 From fd2f9f554ecc9f729708f216153edff49715a828 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 12 Jul 2022 15:31:34 -0700 Subject: printf: Create separate function for converting uint64_t to string Move the logic for converting a uint64_t to a string into a separate function so that it can be used in a followup commit for converting timestamps. The printf logic should behave exactly as before, although there is additional error checking. BRANCH=none BUG=b:238433667, b:234181908 TEST=make run-printf Signed-off-by: Tom Hughes Change-Id: I1f8fd92859d8a7b4b97dbddd1a1009a0e6500047 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760663 Reviewed-by: Jack Rosenthal --- common/printf.c | 96 +++++++++++++++++++++++++++++++------------------ include/printf.h | 24 +++++++++++++ test/printf.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 35 deletions(-) diff --git a/common/printf.c b/common/printf.c index b44ffdbafd..d16c561f5f 100644 --- a/common/printf.c +++ b/common/printf.c @@ -35,6 +35,64 @@ static int hexdigit(int c) #define PF_SIGN BIT(2) /* Add sign (+) for a positive number */ #define PF_64BIT BIT(3) /* Number is 64-bit */ +test_export_static char *uint64_to_str(char *buf, int buf_len, uint64_t val, + int precision, int base, bool uppercase) +{ + int i; + char *str; + + if (buf_len <= 1) + return NULL; + + if (base <= 1) + return NULL; + + /* + * Convert integer to string, starting at end of + * buffer and working backwards. + */ + str = buf + buf_len - 1; + *(str) = '\0'; + + /* + * Fixed-point precision must fit in our buffer. + * Leave space for "0." and the terminating null. + */ + if (precision > buf_len - 3) { + precision = buf_len - 3; + if (precision < 0) + return NULL; + } + + /* + * Handle digits to right of decimal for fixed point numbers. + */ + for (i = 0; i < precision; i++) + *(--str) = '0' + uint64divmod(&val, 10); + if (precision >= 0) + *(--str) = '.'; + + if (!val) + *(--str) = '0'; + + while (val) { + int digit; + + if (str <= buf) + return NULL; + + digit = uint64divmod(&val, base); + if (digit < 10) + *(--str) = '0' + digit; + else if (uppercase) + *(--str) = 'A' + digit - 10; + else + *(--str) = 'a' + digit - 10; + } + + return str; +} + /* * Print the buffer as a string of bytes in hex. * Returns 0 on success or an error on failure. @@ -345,41 +403,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, if (format == error_str) continue; /* Bad format specifier */ - /* - * Convert integer to string, starting at end of - * buffer and working backwards. - */ - vstr = intbuf + sizeof(intbuf) - 1; - *(vstr) = '\0'; - - /* - * Fixed-point precision must fit in our buffer. - * Leave space for "0." and the terminating null. - */ - if (precision > (int)(sizeof(intbuf) - 3)) - precision = sizeof(intbuf) - 3; - - /* - * Handle digits to right of decimal for fixed point - * numbers. - */ - for (vlen = 0; vlen < precision; vlen++) - *(--vstr) = '0' + uint64divmod(&v, 10); - if (precision >= 0) - *(--vstr) = '.'; - - if (!v) - *(--vstr) = '0'; - - while (v) { - int digit = uint64divmod(&v, base); - if (digit < 10) - *(--vstr) = '0' + digit; - else if (c == 'X') - *(--vstr) = 'A' + digit - 10; - else - *(--vstr) = 'a' + digit - 10; - } + vstr = uint64_to_str(intbuf, sizeof(intbuf), v, + precision, base, c == 'X'); + ASSERT(vstr); if (sign) *(--vstr) = sign; diff --git a/include/printf.h b/include/printf.h index 370675ca46..43968ad752 100644 --- a/include/printf.h +++ b/include/printf.h @@ -9,6 +9,7 @@ #define __CROS_EC_PRINTF_H #include /* For va_list */ +#include #include /* For size_t */ #include "common.h" @@ -120,4 +121,27 @@ crec_vsnprintf(char *str, size_t size, const char *format, va_list args); #endif /* !HIDE_EC_STDLIB */ +#ifdef TEST_BUILD +/** + * Converts @val to a string written in @buf. The value is converted from + * least-significant digit to most-significant digit, so the pointer returned + * does not necessarily point to the start of @buf. + * + * This function shouldn't be used directly; it's a helper function for other + * printf functions and only exposed for testing. + * + * @param[out] buf Destination buffer + * @param[in] buf_len Length of @buf in bytes + * @param[in] val Value to convert + * @param[in] precision Fixed point precision; -1 disables fixed point + * @param[in] base Base + * @param[in] uppercase true to print hex characters uppercase + * @return pointer to start of string on success (not necessarily the start of + * @buf). + * @return NULL on error + */ +char *uint64_to_str(char *buf, int buf_len, uint64_t val, int precision, + int base, bool uppercase); +#endif /* TEST_BUILD */ + #endif /* __CROS_EC_PRINTF_H */ diff --git a/test/printf.c b/test/printf.c index 90d146b45d..01f785d708 100644 --- a/test/printf.c +++ b/test/printf.c @@ -370,6 +370,111 @@ test_static int test_vsnprintf_combined(void) return EC_SUCCESS; } +test_static int test_uint64_to_str(void) +{ + /* Longest uin64 in decimal = 20, plus terminating NUL. */ + char buf[21]; + char *str; + + str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0")); + + str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX, + /*precision=*/-1, /*base=*/10, + /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "18446744073709551615", + sizeof("18446744073709551615")); + + /* Buffer too small by 1. */ + str = uint64_to_str(buf, /*buf_len=*/20, /*val=*/UINT64_MAX, + /*precision=*/-1, /*base=*/10, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* lower case hex */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1, + /*base=*/16, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0")); + + /* lower case hex */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX, + /*precision=*/-1, /*base=*/16, + /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "ffffffffffffffff", + sizeof("fffffffffffffff")); + + /* upper case hex */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1, + /*base=*/16, /*uppercase=*/true); + TEST_ASSERT_ARRAY_EQ(str, "0", sizeof("0")); + + str = uint64_to_str(buf, sizeof(buf), /*val=*/UINT64_MAX, + /*precision=*/-1, /*base=*/16, + /*uppercase=*/true); + TEST_ASSERT_ARRAY_EQ(str, "FFFFFFFFFFFFFFFF", + sizeof("FFFFFFFFFFFFFFF")); + + /* precision 0 */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/0, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1.")); + + /* precision 6 */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/6, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "0.000001", sizeof("0.000001")); + + /* Reduced precision due to buffer that is too small. */ + str = uint64_to_str(buf, /*buf_len=*/8, /*val=*/1, /*precision=*/6, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "0.00001", sizeof("0.00001")); + + /* + * Reduced precision due to buffer that is too small, so precision + * gets changed to 0. + */ + str = uint64_to_str(buf, /*buf_len=*/3, /*val=*/1, /*precision=*/6, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT_ARRAY_EQ(str, "1.", sizeof("1.")); + + /* Precision is unable to fit in provided buffer. */ + str = uint64_to_str(buf, /*buf_len=*/2, /*val=*/1, /*precision=*/6, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Negative base. */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/0, /*precision=*/-1, + /*base=*/-1, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Base zero. */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1, + /*base=*/0, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Base one. */ + str = uint64_to_str(buf, sizeof(buf), /*val=*/1, /*precision=*/-1, + /*base=*/1, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Buffer size 1. */ + str = uint64_to_str(buf, /*buf_len=*/1, /*val=*/0, /*precision=*/-1, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Buffer size 0. */ + str = uint64_to_str(buf, /*buf_len=*/0, /*val=*/0, /*precision=*/-1, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + /* Buffer size -1. */ + str = uint64_to_str(buf, /*buf_len=*/-1, /*val=*/0, /*precision=*/-1, + /*base=*/10, /*uppercase=*/false); + TEST_ASSERT(str == NULL); + + return EC_SUCCESS; +} + void run_test(int argc, char **argv) { test_reset(); @@ -384,5 +489,7 @@ void run_test(int argc, char **argv) RUN_TEST(test_vsnprintf_timestamps); RUN_TEST(test_vsnprintf_hexdump); RUN_TEST(test_vsnprintf_combined); + RUN_TEST(test_uint64_to_str); + test_print_result(); } -- cgit v1.2.1 From bc70d8d06b8038e0d06ced247e039c1237a14a7f Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 12 Jul 2022 15:37:26 -0700 Subject: printf: Add snprintf_timestamp and snprintf_timestamp_now These functions replicate the behavior of the non-standard timestamp format "%pT" used in EC and make it possible to replace "%pT" by printing the timestamp string into a buffer and then printing the resulting string with "%s". A followup commit will replace usage of "%pT" with these functions. Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=make run-printf Signed-off-by: Tom Hughes Change-Id: I54c0425a0f08741fa7d3b5d594eea065ee66ab47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756177 Reviewed-by: Paul Fagerburg --- common/printf.c | 40 ++++++++++++++++++++++++++++++++++++ include/printf.h | 34 +++++++++++++++++++++++++++++++ test/printf.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 136 insertions(+) diff --git a/common/printf.c b/common/printf.c index d16c561f5f..d538ec0f03 100644 --- a/common/printf.c +++ b/common/printf.c @@ -93,6 +93,46 @@ test_export_static char *uint64_to_str(char *buf, int buf_len, uint64_t val, return str; } +int snprintf_timestamp_now(char *str, size_t size) +{ + return snprintf_timestamp(str, size, get_time().val); +} + +int snprintf_timestamp(char *str, size_t size, uint64_t timestamp) +{ + int len; + int precision; + char *tmp_str; + char tmp_buf[PRINTF_TIMESTAMP_BUF_SIZE]; + int base = 10; + + if (size == 0) + return -EC_ERROR_INVAL; + + /* Ensure string has terminating '\0' in error cases. */ + str[0] = '\0'; + + if (IS_ENABLED(CONFIG_CONSOLE_VERBOSE)) { + precision = 6; + } else { + precision = 3; + timestamp /= 1000; + } + + tmp_str = uint64_to_str(tmp_buf, sizeof(tmp_buf), timestamp, precision, + base, false); + if (!tmp_str) + return -EC_ERROR_OVERFLOW; + + len = strlen(tmp_str); + if (len + 1 > size) + return -EC_ERROR_OVERFLOW; + + memcpy(str, tmp_str, len + 1); + + return len; +} + /* * Print the buffer as a string of bytes in hex. * Returns 0 on success or an error on failure. diff --git a/include/printf.h b/include/printf.h index 43968ad752..b6f065b3ba 100644 --- a/include/printf.h +++ b/include/printf.h @@ -20,6 +20,11 @@ #include #endif +/** + * Buffer size in bytes large enough to hold the largest possible timestamp. + */ +#define PRINTF_TIMESTAMP_BUF_SIZE 22 + /* * Printf formatting: % [flags] [width] [.precision] [length] [type] * @@ -144,4 +149,33 @@ char *uint64_to_str(char *buf, int buf_len, uint64_t val, int precision, int base, bool uppercase); #endif /* TEST_BUILD */ +/** + * Print timestamp as string to the provided buffer. + * + * Guarantees NUL-termination if size != 0. + * + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @param[in] timestamp Timestamp + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0] + * is set to '\0'. + * @return -EC_ERROR_INVAL when @size is 0. + */ +int snprintf_timestamp(char *str, size_t size, uint64_t timestamp); + +/** + * Print the current time as a string to the provided buffer. + * + * Guarantees NUL-termination if size != 0. + * + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. @str[0] + * is set to '\0'. + * @return -EC_ERROR_INVAL when @size is 0. + */ +int snprintf_timestamp_now(char *str, size_t size); + #endif /* __CROS_EC_PRINTF_H */ diff --git a/test/printf.c b/test/printf.c index 01f785d708..3eeead1875 100644 --- a/test/printf.c +++ b/test/printf.c @@ -350,6 +350,67 @@ test_static int test_vsnprintf_timestamps(void) T(expect_success("0.123456", "%pT", &ts)); ts = 9999999000000; T(expect_success("9999999.000000", "%pT", &ts)); + ts = UINT64_MAX; + T(expect_success("18446744073709.551615", "%pT", &ts)); + + return EC_SUCCESS; +} + +test_static int test_snprintf_timestamp(void) +{ + char str[PRINTF_TIMESTAMP_BUF_SIZE]; + int size; + int ret; + uint64_t ts = 0; + + /* Success cases. */ + + ret = snprintf_timestamp(str, sizeof(str), ts); + TEST_EQ(ret, 8, "%d"); + TEST_ASSERT_ARRAY_EQ(str, "0.000000", sizeof("0.000000")); + + ts = 123456; + ret = snprintf_timestamp(str, sizeof(str), ts); + TEST_EQ(ret, 8, "%d"); + TEST_ASSERT_ARRAY_EQ(str, "0.123456", sizeof("0.123456")); + + ts = 9999999000000; + ret = snprintf_timestamp(str, sizeof(str), ts); + TEST_EQ(ret, 14, "%d"); + TEST_ASSERT_ARRAY_EQ(str, "9999999.000000", sizeof("9999999.000000")); + + ts = UINT64_MAX; + ret = snprintf_timestamp(str, sizeof(str), ts); + TEST_EQ(ret, 21, "%d"); + TEST_ASSERT_ARRAY_EQ(str, "18446744073709.551615", + sizeof("18446744073709.551615")); + + /* Error cases. */ + + /* Buffer is too small by one. */ + size = 21; + ts = UINT64_MAX; + str[0] = 'f'; + ret = snprintf_timestamp(str, size, ts); + TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d"); + TEST_EQ(str[0], '\0', "%d"); + + /* Size is zero. */ + size = 0; + ts = UINT64_MAX; + str[0] = 'f'; + ret = snprintf_timestamp(str, size, ts); + TEST_EQ(ret, -EC_ERROR_INVAL, "%d"); + TEST_EQ(str[0], 'f', "%d"); + + /* Size is one. */ + size = 1; + ts = UINT64_MAX; + str[0] = 'f'; + ret = snprintf_timestamp(str, size, ts); + TEST_EQ(ret, -EC_ERROR_OVERFLOW, "%d"); + TEST_EQ(str[0], '\0', "%d"); + return EC_SUCCESS; } @@ -490,6 +551,7 @@ void run_test(int argc, char **argv) RUN_TEST(test_vsnprintf_hexdump); RUN_TEST(test_vsnprintf_combined); RUN_TEST(test_uint64_to_str); + RUN_TEST(test_snprintf_timestamp); test_print_result(); } -- cgit v1.2.1 From 078ce31b33405582d5b1c3229a135300609d7d40 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 8 Jul 2022 10:33:14 -0700 Subject: printf: Add snprintf_hex_buffer This function replicate the behavior of the non-standard hex buffer format "%ph" used in EC and make it possible to replace "%ph" by printing the bytes into a buffer and then printing the resulting string with "%s". A followup commit will replace usage of "%ph" with these functions. Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=make run-printf Signed-off-by: Tom Hughes Change-Id: I46135b25c84abe4ca7fb16ebb78af535622f50c8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756179 Reviewed-by: Scott Collyer --- common/printf.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/printf.h | 23 +++++++++++++++++++++++ test/printf.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 121 insertions(+) diff --git a/common/printf.c b/common/printf.c index d538ec0f03..01e9d0f544 100644 --- a/common/printf.c +++ b/common/printf.c @@ -174,6 +174,54 @@ static int print_hex_buffer(int (*addchar)(void *context, int c), void *context, return EC_SUCCESS; } +struct hex_char_context { + struct hex_buffer_params hex_buf_params; + char *str; + size_t size; +}; + +int add_hex_char(void *context, int c) +{ + struct hex_char_context *ctx = context; + + if (ctx->size == 0) + return EC_ERROR_OVERFLOW; + + *(ctx->str++) = c; + ctx->size--; + + return EC_SUCCESS; +} + +size_t hex_str_buf_size(size_t num_bytes) +{ + return 2 * num_bytes + 1; +} + +int snprintf_hex_buffer(char *str, size_t size, + const struct hex_buffer_params *params) +{ + int rv; + struct hex_char_context context = { + .hex_buf_params = *params, + .str = str, + /* + * Reserve space for terminating '\0'. + */ + .size = size - 1, + }; + + if (size == 0) + return -EC_ERROR_INVAL; + + rv = print_hex_buffer(add_hex_char, &context, params->buffer, + params->size, 0, 0); + + *context.str = '\0'; + + return (rv == EC_SUCCESS) ? (context.str - str) : -rv; +} + int vfnprintf(int (*addchar)(void *context, int c), void *context, const char *format, va_list args) { diff --git a/include/printf.h b/include/printf.h index b6f065b3ba..6df6405503 100644 --- a/include/printf.h +++ b/include/printf.h @@ -12,6 +12,7 @@ #include #include /* For size_t */ #include "common.h" +#include "console.h" /* The declaration of snprintf is changed to crec_snprintf for Zephyr, * so include stdio.h from Zephyr. @@ -178,4 +179,26 @@ int snprintf_timestamp(char *str, size_t size, uint64_t timestamp); */ int snprintf_timestamp_now(char *str, size_t size); +/** + * Prints bytes as a hex string in the provided buffer. + * + * Guarantees NUL-termination if size != 0. + * + * @param[out] str Destination string + * @param[in] size Size of @str in bytes + * @param[in] params Data to print + * @return Length of string written to @str, not including terminating NUL. + * @return -EC_ERROR_OVERFLOW when @str buffer is not large enough. + * @return -EC_ERROR_INVAL when @size is 0. + */ +int snprintf_hex_buffer(char *str, size_t size, + const struct hex_buffer_params *params); + +/** + * @param[in] num_bytes + * @return number of bytes needed to store @num_bytes as a string (including + * terminating '\0'). + */ +size_t hex_str_buf_size(size_t num_bytes); + #endif /* __CROS_EC_PRINTF_H */ diff --git a/test/printf.c b/test/printf.c index 3eeead1875..87059c30dc 100644 --- a/test/printf.c +++ b/test/printf.c @@ -424,6 +424,55 @@ test_static int test_vsnprintf_hexdump(void) return EC_SUCCESS; } +test_static int test_snprintf_hex_buffer(void) +{ + const uint8_t bytes[] = { 0xAB, 0x5E }; + char str_buf[5]; + int rv; + + /* Success cases. */ + + memset(str_buf, 0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 2)); + TEST_ASSERT_ARRAY_EQ(str_buf, "ab5e", sizeof("ab5e")); + TEST_EQ(rv, 4, "%d"); + + memset(str_buf, 0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 0)); + TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof("")); + TEST_EQ(rv, 0, "%d"); + + memset(str_buf, 0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, sizeof(str_buf), HEX_BUF(bytes, 1)); + TEST_ASSERT_ARRAY_EQ(str_buf, "ab", sizeof("ab")); + TEST_EQ(rv, 2, "%d"); + + /* Error cases. */ + + /* Zero for buffer size argument is an error. */ + memset(str_buf, 0xff, sizeof(str_buf)); + TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, 0, HEX_BUF(bytes, 2)); + TEST_EQ(rv, -EC_ERROR_INVAL, "%d"); + TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf)); + + /* Buffer only has space for terminating '\0'. */ + memset(str_buf, 0xff, sizeof(str_buf)); + TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, 1, HEX_BUF(bytes, 1)); + TEST_ASSERT_ARRAY_EQ(str_buf, "", sizeof("")); + TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d"); + + /* Buffer only has space for one character and '\0'. */ + memset(str_buf, 0xff, sizeof(str_buf)); + TEST_ASSERT_MEMSET(str_buf, (char)0xff, sizeof(str_buf)); + rv = snprintf_hex_buffer(str_buf, 2, HEX_BUF(bytes, 1)); + TEST_ASSERT_ARRAY_EQ(str_buf, "a", sizeof("a")); + TEST_EQ(rv, -EC_ERROR_OVERFLOW, "%d"); + + return EC_SUCCESS; +} + test_static int test_vsnprintf_combined(void) { T(expect_success("abc", "%c%s", 'a', "bc")); @@ -552,6 +601,7 @@ void run_test(int argc, char **argv) RUN_TEST(test_vsnprintf_combined); RUN_TEST(test_uint64_to_str); RUN_TEST(test_snprintf_timestamp); + RUN_TEST(test_snprintf_hex_buffer); test_print_result(); } -- cgit v1.2.1 From 9a9c80ddff5ef695f4fc80ec4242f61593e54cf1 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Wed, 13 Jul 2022 13:35:09 -0600 Subject: tests: Split usb_malfunction_test tests out as lib In order to be able to easily create a test-drivers variant with only usb_malfunction_sink test suite, split the usb_malfunction_sink test as its own library that can be linked into its own binary or as part of the test-drivers. BRANCH=none BUG=b:233103160 TEST=zmake test-drivers # still contains usb_malfunction_sink test Signed-off-by: Aaron Massey Change-Id: Ia49fc6fa5279a6c3d2e6e6e799529465f47a02a4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761215 Reviewed-by: Yuval Peress --- zephyr/test/drivers/CMakeLists.txt | 3 +- .../src/integration/usbc/usb_malfunction_sink.c | 255 --------------------- .../drivers/usb_malfunction_sink/CMakeLists.txt | 19 ++ .../src/usb_malfunction_sink.c | 255 +++++++++++++++++++++ 4 files changed, 276 insertions(+), 256 deletions(-) delete mode 100644 zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c create mode 100644 zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt create mode 100644 zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c diff --git a/zephyr/test/drivers/CMakeLists.txt b/zephyr/test/drivers/CMakeLists.txt index 55c824b44f..91b90a9dc4 100644 --- a/zephyr/test/drivers/CMakeLists.txt +++ b/zephyr/test/drivers/CMakeLists.txt @@ -55,7 +55,6 @@ if(subproject_path STREQUAL "") src/integration/usbc/usb_attach_src_snk.c src/integration/usbc/usb_pd_ctrl_msg.c src/integration/usbc/usb_pd_rev3.c - src/integration/usbc/usb_malfunction_sink.c src/i2c_passthru.c src/isl923x.c src/keyboard_scan.c @@ -81,6 +80,8 @@ if(subproject_path STREQUAL "") src/vboot_hash.c src/watchdog.c ) + + add_subdirectory(usb_malfunction_sink) else() add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}${subproject_path}) endif() diff --git a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c b/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c deleted file mode 100644 index 2f1fd572c0..0000000000 --- a/zephyr/test/drivers/src/integration/usbc/usb_malfunction_sink.c +++ /dev/null @@ -1,255 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include - -#include "battery_smart.h" -#include "emul/emul_isl923x.h" -#include "emul/emul_smart_battery.h" -#include "emul/tcpc/emul_tcpci_partner_faulty_snk.h" -#include "emul/tcpc/emul_tcpci_partner_snk.h" -#include "tcpm/tcpci.h" -#include "test/drivers/test_state.h" -#include "test/drivers/utils.h" -#include "usb_pd.h" - -struct usb_malfunction_sink_fixture { - struct tcpci_partner_data sink; - struct tcpci_faulty_snk_emul_data faulty_snk_ext; - struct tcpci_snk_emul_data snk_ext; - const struct emul *tcpci_emul; - const struct emul *charger_emul; - struct tcpci_faulty_snk_action actions[2]; -}; - -static void connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture) -{ - /* - * TODO(b/221439302) Updating the TCPCI emulator registers, updating the - * vbus, as well as alerting should all be a part of the connect - * function. - */ - isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); - tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS, - TCPC_REG_POWER_STATUS_VBUS_DET); - tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS, - TCPC_REG_EXT_STATUS_SAFE0V); - tcpci_tcpc_alert(0); - /* - * TODO(b/226567798) Wait for TCPC init and DRPToggle. It is required, - * because tcpci_emul_reset_rule_before reset registers including - * Looking4Connection bit in CC_STATUS register. - */ - k_sleep(K_SECONDS(1)); - zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->sink, - fixture->tcpci_emul), - NULL); - - /* Wait for PD negotiation and current ramp. - * TODO(b/213906889): Check message timing and contents. - */ - k_sleep(K_SECONDS(10)); -} - -static inline void -disconnect_sink_from_port(struct usb_malfunction_sink_fixture *fixture) -{ - zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); - k_sleep(K_SECONDS(1)); -} - -static void *usb_malfunction_sink_setup(void) -{ - static struct usb_malfunction_sink_fixture test_fixture; - - /* Get references for the emulators */ - test_fixture.tcpci_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); - test_fixture.charger_emul = - emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); - - /* Initialized the sink to request 5V and 3A */ - tcpci_partner_init(&test_fixture.sink, PD_REV20); - test_fixture.sink.extensions = tcpci_faulty_snk_emul_init( - &test_fixture.faulty_snk_ext, &test_fixture.sink, - tcpci_snk_emul_init(&test_fixture.snk_ext, &test_fixture.sink, - NULL)); - test_fixture.snk_ext.pdo[1] = - PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); - - return &test_fixture; -} - -static void usb_malfunction_sink_before(void *data) -{ - /* Set chipset to ON, this will set TCPM to DRP */ - test_set_chipset_to_s0(); - - /* TODO(b/214401892): Check why need to give time TCPM to spin */ - k_sleep(K_SECONDS(1)); -} - -static void usb_malfunction_sink_after(void *data) -{ - struct usb_malfunction_sink_fixture *fixture = data; - - tcpci_faulty_snk_emul_clear_actions_list(&fixture->faulty_snk_ext); - disconnect_sink_from_port(fixture); - tcpci_partner_common_clear_logged_msgs(&fixture->sink); -} - -ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main, - usb_malfunction_sink_setup, usb_malfunction_sink_before, - usb_malfunction_sink_after, NULL); - -ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable) -{ - struct ec_response_typec_status typec_status; - - /* - * Fail on SourceCapabilities message to make TCPM change PD port state - * to disabled - */ - fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; - fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, - &fixture->actions[0]); - - connect_sink_to_port(fixture); - - typec_status = host_cmd_typec_status(0); - - /* Device is connected, but PD wasn't able to establish contract */ - zassert_true(typec_status.pd_enabled, NULL); - zassert_true(typec_status.dev_connected, NULL); - zassert_false(typec_status.sop_connected, NULL); -} - -ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect) -{ - struct ec_response_usb_pd_power_info info; - struct ec_response_typec_status typec_status; - - /* - * Fail only few times on SourceCapabilities message to prevent entering - * PE_SRC_Disabled state by TCPM - */ - fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; - fixture->actions[0].count = 3; - tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, - &fixture->actions[0]); - - connect_sink_to_port(fixture); - - typec_status = host_cmd_typec_status(0); - - zassert_true(typec_status.pd_enabled, NULL); - zassert_true(typec_status.dev_connected, NULL); - zassert_true(typec_status.sop_connected, NULL); - - info = host_cmd_power_info(0); - - zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE, - "Expected role to be %d, but got %d", - USB_PD_PORT_POWER_SOURCE, info.role); - zassert_equal(info.type, USB_CHG_TYPE_NONE, - "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE, - info.type); - zassert_equal(info.meas.voltage_max, 0, - "Expected charge voltage max of 0mV, but got %dmV", - info.meas.voltage_max); - zassert_within( - info.meas.voltage_now, 5000, 500, - "Charging voltage expected to be near 5000mV, but was %dmV", - info.meas.voltage_now); - zassert_equal(info.meas.current_max, 1500, - "Current max expected to be 1500mV, but was %dmV", - info.meas.current_max); - zassert_equal(info.meas.current_lim, 0, - "VBUS max is set to 0mA, but PD is reporting %dmA", - info.meas.current_lim); - zassert_equal(info.max_power, 0, - "Charging expected to be at %duW, but PD max is %duW", 0, - info.max_power); -} - -ZTEST_F(usb_malfunction_sink, test_ignore_source_cap) -{ - struct tcpci_partner_log_msg *msg; - uint16_t header; - bool expect_hard_reset = false; - int msg_cnt = 0; - - fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; - fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, - &fixture->actions[0]); - - tcpci_partner_common_enable_pd_logging(&fixture->sink, true); - connect_sink_to_port(fixture); - tcpci_partner_common_enable_pd_logging(&fixture->sink, false); - - /* - * If test is failing, printing logged message may be useful to diagnose - * problem: - * tcpci_partner_common_print_logged_msgs(&fixture->sink); - */ - - /* Check if SourceCapability message alternate with HardReset */ - SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node) - { - if (expect_hard_reset) { - zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET, - "Expected message %d to be hard reset", - msg_cnt); - } else { - header = sys_get_le16(msg->buf); - zassert_equal( - msg->sop, TCPCI_MSG_SOP, - "Expected message %d to be SOP message, not 0x%x", - msg_cnt, msg->sop); - zassert_not_equal( - PD_HEADER_CNT(header), 0, - "Expected message %d to has at least one data object", - msg_cnt); - zassert_equal( - PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, - "Expected message %d to be SourceCapabilities, not 0x%x", - msg_cnt, PD_HEADER_TYPE(header)); - } - - msg_cnt++; - expect_hard_reset = !expect_hard_reset; - } -} - -ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable) -{ - struct ec_response_typec_status typec_status; - - /* - * Ignore first SourceCapabilities message and discard others by sending - * different messages. This will lead to PD disable. - */ - fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; - fixture->actions[0].count = 1; - tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, - &fixture->actions[0]); - fixture->actions[1].action_mask = TCPCI_FAULTY_SNK_DISCARD_SRC_CAP; - fixture->actions[1].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; - tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, - &fixture->actions[1]); - - connect_sink_to_port(fixture); - - typec_status = host_cmd_typec_status(0); - - /* Device is connected, but PD wasn't able to establish contract */ - zassert_true(typec_status.pd_enabled, NULL); - zassert_true(typec_status.dev_connected, NULL); - zassert_false(typec_status.sop_connected, NULL); -} diff --git a/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt new file mode 100644 index 0000000000..770f01b6d9 --- /dev/null +++ b/zephyr/test/drivers/usb_malfunction_sink/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Create library name based on current directory +zephyr_library_get_current_dir_lib_name(${ZEPHYR_BASE} lib_name) + +# Create interface library +zephyr_interface_library_named(${lib_name}) + +# Add include paths +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}") +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") + +# Add source files +zephyr_library_sources("${CMAKE_CURRENT_SOURCE_DIR}/src/usb_malfunction_sink.c") + +# Link in the library +zephyr_library_link_libraries(${lib_name}) diff --git a/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c new file mode 100644 index 0000000000..2f1fd572c0 --- /dev/null +++ b/zephyr/test/drivers/usb_malfunction_sink/src/usb_malfunction_sink.c @@ -0,0 +1,255 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include +#include + +#include "battery_smart.h" +#include "emul/emul_isl923x.h" +#include "emul/emul_smart_battery.h" +#include "emul/tcpc/emul_tcpci_partner_faulty_snk.h" +#include "emul/tcpc/emul_tcpci_partner_snk.h" +#include "tcpm/tcpci.h" +#include "test/drivers/test_state.h" +#include "test/drivers/utils.h" +#include "usb_pd.h" + +struct usb_malfunction_sink_fixture { + struct tcpci_partner_data sink; + struct tcpci_faulty_snk_emul_data faulty_snk_ext; + struct tcpci_snk_emul_data snk_ext; + const struct emul *tcpci_emul; + const struct emul *charger_emul; + struct tcpci_faulty_snk_action actions[2]; +}; + +static void connect_sink_to_port(struct usb_malfunction_sink_fixture *fixture) +{ + /* + * TODO(b/221439302) Updating the TCPCI emulator registers, updating the + * vbus, as well as alerting should all be a part of the connect + * function. + */ + isl923x_emul_set_adc_vbus(fixture->charger_emul, 0); + tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_POWER_STATUS, + TCPC_REG_POWER_STATUS_VBUS_DET); + tcpci_emul_set_reg(fixture->tcpci_emul, TCPC_REG_EXT_STATUS, + TCPC_REG_EXT_STATUS_SAFE0V); + tcpci_tcpc_alert(0); + /* + * TODO(b/226567798) Wait for TCPC init and DRPToggle. It is required, + * because tcpci_emul_reset_rule_before reset registers including + * Looking4Connection bit in CC_STATUS register. + */ + k_sleep(K_SECONDS(1)); + zassume_ok(tcpci_partner_connect_to_tcpci(&fixture->sink, + fixture->tcpci_emul), + NULL); + + /* Wait for PD negotiation and current ramp. + * TODO(b/213906889): Check message timing and contents. + */ + k_sleep(K_SECONDS(10)); +} + +static inline void +disconnect_sink_from_port(struct usb_malfunction_sink_fixture *fixture) +{ + zassume_ok(tcpci_emul_disconnect_partner(fixture->tcpci_emul), NULL); + k_sleep(K_SECONDS(1)); +} + +static void *usb_malfunction_sink_setup(void) +{ + static struct usb_malfunction_sink_fixture test_fixture; + + /* Get references for the emulators */ + test_fixture.tcpci_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(tcpci_emul))); + test_fixture.charger_emul = + emul_get_binding(DT_LABEL(DT_NODELABEL(isl923x_emul))); + + /* Initialized the sink to request 5V and 3A */ + tcpci_partner_init(&test_fixture.sink, PD_REV20); + test_fixture.sink.extensions = tcpci_faulty_snk_emul_init( + &test_fixture.faulty_snk_ext, &test_fixture.sink, + tcpci_snk_emul_init(&test_fixture.snk_ext, &test_fixture.sink, + NULL)); + test_fixture.snk_ext.pdo[1] = + PDO_FIXED(5000, 3000, PDO_FIXED_UNCONSTRAINED); + + return &test_fixture; +} + +static void usb_malfunction_sink_before(void *data) +{ + /* Set chipset to ON, this will set TCPM to DRP */ + test_set_chipset_to_s0(); + + /* TODO(b/214401892): Check why need to give time TCPM to spin */ + k_sleep(K_SECONDS(1)); +} + +static void usb_malfunction_sink_after(void *data) +{ + struct usb_malfunction_sink_fixture *fixture = data; + + tcpci_faulty_snk_emul_clear_actions_list(&fixture->faulty_snk_ext); + disconnect_sink_from_port(fixture); + tcpci_partner_common_clear_logged_msgs(&fixture->sink); +} + +ZTEST_SUITE(usb_malfunction_sink, drivers_predicate_post_main, + usb_malfunction_sink_setup, usb_malfunction_sink_before, + usb_malfunction_sink_after, NULL); + +ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_disable) +{ + struct ec_response_typec_status typec_status; + + /* + * Fail on SourceCapabilities message to make TCPM change PD port state + * to disabled + */ + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; + fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); + + connect_sink_to_port(fixture); + + typec_status = host_cmd_typec_status(0); + + /* Device is connected, but PD wasn't able to establish contract */ + zassert_true(typec_status.pd_enabled, NULL); + zassert_true(typec_status.dev_connected, NULL); + zassert_false(typec_status.sop_connected, NULL); +} + +ZTEST_F(usb_malfunction_sink, test_fail_source_cap_and_pd_connect) +{ + struct ec_response_usb_pd_power_info info; + struct ec_response_typec_status typec_status; + + /* + * Fail only few times on SourceCapabilities message to prevent entering + * PE_SRC_Disabled state by TCPM + */ + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_FAIL_SRC_CAP; + fixture->actions[0].count = 3; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); + + connect_sink_to_port(fixture); + + typec_status = host_cmd_typec_status(0); + + zassert_true(typec_status.pd_enabled, NULL); + zassert_true(typec_status.dev_connected, NULL); + zassert_true(typec_status.sop_connected, NULL); + + info = host_cmd_power_info(0); + + zassert_equal(info.role, USB_PD_PORT_POWER_SOURCE, + "Expected role to be %d, but got %d", + USB_PD_PORT_POWER_SOURCE, info.role); + zassert_equal(info.type, USB_CHG_TYPE_NONE, + "Expected type to be %d, but got %d", USB_CHG_TYPE_NONE, + info.type); + zassert_equal(info.meas.voltage_max, 0, + "Expected charge voltage max of 0mV, but got %dmV", + info.meas.voltage_max); + zassert_within( + info.meas.voltage_now, 5000, 500, + "Charging voltage expected to be near 5000mV, but was %dmV", + info.meas.voltage_now); + zassert_equal(info.meas.current_max, 1500, + "Current max expected to be 1500mV, but was %dmV", + info.meas.current_max); + zassert_equal(info.meas.current_lim, 0, + "VBUS max is set to 0mA, but PD is reporting %dmA", + info.meas.current_lim); + zassert_equal(info.max_power, 0, + "Charging expected to be at %duW, but PD max is %duW", 0, + info.max_power); +} + +ZTEST_F(usb_malfunction_sink, test_ignore_source_cap) +{ + struct tcpci_partner_log_msg *msg; + uint16_t header; + bool expect_hard_reset = false; + int msg_cnt = 0; + + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; + fixture->actions[0].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); + + tcpci_partner_common_enable_pd_logging(&fixture->sink, true); + connect_sink_to_port(fixture); + tcpci_partner_common_enable_pd_logging(&fixture->sink, false); + + /* + * If test is failing, printing logged message may be useful to diagnose + * problem: + * tcpci_partner_common_print_logged_msgs(&fixture->sink); + */ + + /* Check if SourceCapability message alternate with HardReset */ + SYS_SLIST_FOR_EACH_CONTAINER(&fixture->sink.msg_log, msg, node) + { + if (expect_hard_reset) { + zassert_equal(msg->sop, TCPCI_MSG_TX_HARD_RESET, + "Expected message %d to be hard reset", + msg_cnt); + } else { + header = sys_get_le16(msg->buf); + zassert_equal( + msg->sop, TCPCI_MSG_SOP, + "Expected message %d to be SOP message, not 0x%x", + msg_cnt, msg->sop); + zassert_not_equal( + PD_HEADER_CNT(header), 0, + "Expected message %d to has at least one data object", + msg_cnt); + zassert_equal( + PD_HEADER_TYPE(header), PD_DATA_SOURCE_CAP, + "Expected message %d to be SourceCapabilities, not 0x%x", + msg_cnt, PD_HEADER_TYPE(header)); + } + + msg_cnt++; + expect_hard_reset = !expect_hard_reset; + } +} + +ZTEST_F(usb_malfunction_sink, test_ignore_source_cap_and_pd_disable) +{ + struct ec_response_typec_status typec_status; + + /* + * Ignore first SourceCapabilities message and discard others by sending + * different messages. This will lead to PD disable. + */ + fixture->actions[0].action_mask = TCPCI_FAULTY_SNK_IGNORE_SRC_CAP; + fixture->actions[0].count = 1; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[0]); + fixture->actions[1].action_mask = TCPCI_FAULTY_SNK_DISCARD_SRC_CAP; + fixture->actions[1].count = TCPCI_FAULTY_SNK_INFINITE_ACTION; + tcpci_faulty_snk_emul_append_action(&fixture->faulty_snk_ext, + &fixture->actions[1]); + + connect_sink_to_port(fixture); + + typec_status = host_cmd_typec_status(0); + + /* Device is connected, but PD wasn't able to establish contract */ + zassert_true(typec_status.pd_enabled, NULL); + zassert_true(typec_status.dev_connected, NULL); + zassert_false(typec_status.sop_connected, NULL); +} -- cgit v1.2.1 From 890b66539a63114179bcabee52f18d05fc5e2146 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Wed, 13 Jul 2022 13:37:46 -0600 Subject: test: Fix test_set_chipset_to_s0 flaky OD failure The smart battery driver and other tests may change the smart battery "capacity" and "full capacity" parameters without resetting them. This can lead to bad state later on represented as flaky tests. Add a ZTEST_RULE to reset the capacity and full_capacity values to their defaults defined in devicetree after each test. BRANCH=none BUG=b:233103160 TEST=zmake test-drivers TEST=shuffle_test.sh Signed-off-by: Aaron Massey Change-Id: If7bfb364a0398b5121eb935e2394d0940e04f27f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761216 Reviewed-by: Yuval Peress --- zephyr/emul/emul_smart_battery.c | 22 ++++++++++++++++++++++ zephyr/include/emul/emul_smart_battery.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c index 1300e7da0a..8ba61c56c4 100644 --- a/zephyr/emul/emul_smart_battery.c +++ b/zephyr/emul/emul_smart_battery.c @@ -13,6 +13,7 @@ LOG_MODULE_REGISTER(smart_battery); #include #include #include +#include #include "emul/emul_common_i2c.h" #include "emul/emul_smart_battery.h" @@ -832,7 +833,9 @@ static int sbat_emul_init(const struct emul *emul, const struct device *parent) .avg_cur = DT_INST_PROP(n, avg_cur), \ .max_error = DT_INST_PROP(n, max_error), \ .cap = DT_INST_PROP(n, cap), \ + .default_cap = DT_INST_PROP(n, cap), \ .full_cap = DT_INST_PROP(n, full_cap), \ + .default_full_cap = DT_INST_PROP(n, full_cap), \ .desired_charg_cur = DT_INST_PROP(n, \ desired_charg_cur), \ .desired_charg_volt = DT_INST_PROP(n, \ @@ -895,3 +898,22 @@ struct i2c_emul *sbat_emul_get_ptr(int ord) return NULL; } } + +static void emul_smart_battery_reset_capacity(struct sbat_emul_data *bat_data) +{ + bat_data->bat.cap = bat_data->bat.default_cap; + bat_data->bat.full_cap = bat_data->bat.default_full_cap; +} + +#define SBAT_EMUL_RESET_RULE_AFTER(n) \ + emul_smart_battery_reset_capacity(&sbat_emul_data_##n) + +static void emul_sbat_reset(const struct ztest_unit_test *test, void *data) +{ + ARG_UNUSED(test); + ARG_UNUSED(data); + + DT_INST_FOREACH_STATUS_OKAY(SBAT_EMUL_RESET_RULE_AFTER); +} + +ZTEST_RULE(emul_smart_battery_reset, NULL, emul_sbat_reset); diff --git a/zephyr/include/emul/emul_smart_battery.h b/zephyr/include/emul/emul_smart_battery.h index f5eab1524d..fa55f23fa9 100644 --- a/zephyr/include/emul/emul_smart_battery.h +++ b/zephyr/include/emul/emul_smart_battery.h @@ -77,8 +77,12 @@ struct sbat_emul_bat_data { uint16_t max_error; /** Capacity of the battery at the moment in mAh */ uint16_t cap; + /** Default capacity of the battery at the moment in mAh */ + const uint16_t default_cap; /** Full capacity of the battery in mAh */ uint16_t full_cap; + /** Default full capacity of the battery at the moment in mAh */ + const uint16_t default_full_cap; /** Design battery capacity in mAh */ uint16_t design_cap; /** Charging current requested by battery */ -- cgit v1.2.1 From 6bbe76ff8b057d62f0f84dd2e9a36a7f525d25f0 Mon Sep 17 00:00:00 2001 From: Andrea Grandi Date: Thu, 14 Jul 2022 22:32:52 +0000 Subject: run_device_tests: Error out when using remote servo_micro The remote option only supports flashing with J-Link. Add an explicit error message when user attempts to use a remote servo micro to flash the EC. BUG=none TEST=./test/run_device_tests.py --flasher=servo_micro \ --remote=localhost --console_port=4567 => Error message is printed BRANCH=none Signed-off-by: Andrea Grandi Change-Id: Ib651ecaec88cb2b124a34b0d6fd0399912d3cbdc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3764642 Reviewed-by: Tom Hughes Commit-Queue: Tom Hughes --- test/run_device_tests.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/test/run_device_tests.py b/test/run_device_tests.py index 09f255f43e..7bde2b8a87 100755 --- a/test/run_device_tests.py +++ b/test/run_device_tests.py @@ -741,6 +741,13 @@ def main(): ) sys.exit(1) + if args.remote and args.flasher == SERVO_MICRO: + logging.error( + "The remote option is not supported when flashing with servo " + "micro. Use J-Link instead or flash with a local servo micro." + ) + sys.exit(1) + if args.board not in BOARD_CONFIGS: logging.error('Unable to find a config for board: "%s"', args.board) sys.exit(1) -- cgit v1.2.1 From d6d63d208d734097b75d9d66c1bfc657b6176db9 Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Thu, 7 Jul 2022 10:23:49 +1000 Subject: ap_pwrseq: add an explicit "uninitialized" state It's possible for callers to request the AP state before the power state machine is ready, which without an UNINIT state can cause incorrect behavior because the initial (zero-initialized) state is G3. BUG=none TEST=zmake build nereid BRANCH=none Signed-off-by: Peter Marheine Change-Id: Ib6e9158214c321943a63fff05e0f69224c5f9ae9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750257 Reviewed-by: Andrew McRae --- zephyr/include/ap_power/ap_power_interface.h | 2 ++ zephyr/subsys/ap_pwrseq/ap_power_interface.c | 10 ++++++++++ zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c | 5 ++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/zephyr/include/ap_power/ap_power_interface.h b/zephyr/include/ap_power/ap_power_interface.h index f834779fb9..d3d31f6ecb 100644 --- a/zephyr/include/ap_power/ap_power_interface.h +++ b/zephyr/include/ap_power/ap_power_interface.h @@ -34,6 +34,8 @@ * is hibernated or all the VRs are turned off. */ enum power_states_ndsx { + /* Power state machine is not ready; AP state is unknown. */ + SYS_POWER_STATE_UNINIT, /* * Actual power states */ diff --git a/zephyr/subsys/ap_pwrseq/ap_power_interface.c b/zephyr/subsys/ap_pwrseq/ap_power_interface.c index 69b2ddab9e..6186e299dd 100644 --- a/zephyr/subsys/ap_pwrseq/ap_power_interface.c +++ b/zephyr/subsys/ap_pwrseq/ap_power_interface.c @@ -6,11 +6,17 @@ #include #include +LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); + bool ap_power_in_state(enum ap_power_state_mask state_mask) { int need_mask = 0; switch (pwr_sm_get_state()) { + case SYS_POWER_STATE_UNINIT: + LOG_WRN("%s: init not yet complete; AP state is unknown", + __func__); + return false; case SYS_POWER_STATE_G3: need_mask = AP_POWER_STATE_HARD_OFF; break; @@ -59,6 +65,10 @@ bool ap_power_in_state(enum ap_power_state_mask state_mask) bool ap_power_in_or_transitioning_to_state(enum ap_power_state_mask state_mask) { switch (pwr_sm_get_state()) { + case SYS_POWER_STATE_UNINIT: + LOG_WRN("%s: init not yet complete; AP state is unknown", + __func__); + return 0; case SYS_POWER_STATE_G3: case SYS_POWER_STATE_S5G3: return state_mask & AP_POWER_STATE_HARD_OFF; diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index 2bbcce4d39..dd4b2e4e66 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -10,7 +10,9 @@ static K_KERNEL_STACK_DEFINE(pwrseq_thread_stack, CONFIG_AP_PWRSEQ_STACK_SIZE); static struct k_thread pwrseq_thread_data; -static struct pwrseq_context pwrseq_ctx; +static struct pwrseq_context pwrseq_ctx = { + .power_state = SYS_POWER_STATE_UNINIT, +}; /* S5 inactive timer*/ K_TIMER_DEFINE(s5_inactive_timer, NULL, NULL); /* @@ -31,6 +33,7 @@ LOG_MODULE_REGISTER(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL); * @brief power_state names for debug */ static const char *const pwrsm_dbg[] = { + [SYS_POWER_STATE_UNINIT] = "Unknown", [SYS_POWER_STATE_G3] = "G3", [SYS_POWER_STATE_S5] = "S5", [SYS_POWER_STATE_S4] = "S4", -- cgit v1.2.1 From 7645cdcb06fff0d0e0b156c0cfe6e951248beff4 Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Wed, 13 Jul 2022 14:14:59 -0600 Subject: test: Fix race-condition in test_set_chipset_to_s0 The test_set_chipset_to_s0 sets the smart battery's capacity to 75% before attempting to set the chipset in S0. However, the charge state task may not reread battery capacity information in time before the attempt to power on. This results in the power state remaining in G3 causing a safety check failure in the test utils code. This was revealed by shuffling the test order execution. Make test_set_chipset_to_s0 wait for the charge task to reread the parameters before initiating a startup to S0. BRANCH=none BUG=b:233103160 TEST=zmake test test-drivers TEST=utils/shuffle.sh Signed-off-by: Aaron Massey Change-Id: Ia2e948498710061f6757235470da59a61acbf66c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761217 Reviewed-by: Yuval Peress --- zephyr/test/drivers/src/utils.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/zephyr/test/drivers/src/utils.c b/zephyr/test/drivers/src/utils.c index 3785ecf2e4..8375bf1d77 100644 --- a/zephyr/test/drivers/src/utils.c +++ b/zephyr/test/drivers/src/utils.c @@ -10,6 +10,7 @@ #include "battery.h" #include "battery_smart.h" +#include "charge_state.h" #include "emul/emul_isl923x.h" #include "emul/emul_smart_battery.h" #include "emul/tcpc/emul_tcpci_partner_src.h" @@ -50,6 +51,10 @@ void test_set_chipset_to_s0(void) GPIO_BATT_PRES_ODL_PORT, 0), NULL); + /* We need to wait for the charge task to re-read battery parameters */ + WAIT_FOR(!charge_want_shutdown(), CHARGE_MAX_SLEEP_USEC + 1, + k_sleep(K_SECONDS(1))); + /* The easiest way to power on seems to be the shell command. */ zassert_equal(EC_SUCCESS, shell_execute_cmd(get_ec_shell(), "power on"), NULL); -- cgit v1.2.1 From 8eae0fbea14a4d386a483b30816cf1e58e0b2e06 Mon Sep 17 00:00:00 2001 From: "jimmy.wu" Date: Thu, 14 Jul 2022 17:55:24 +0800 Subject: pujjo: Add gyro/lid accel sensor code Add gyro/lid accel sensor main source code. BUG=b:238984390 TEST=zmake build pujjo BRANCH=none Signed-off-by: jimmy.wu Change-Id: I7d6f31c9cc66b8d61eaf6f22d146189ccc0e987d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3762590 Reviewed-by: Andrew McRae Reviewed-by: Peter Marheine --- zephyr/projects/nissa/prj_pujjo.conf | 5 ++-- zephyr/projects/nissa/pujjo_motionsense.dts | 39 ++++++++++++----------------- zephyr/projects/nissa/pujjo_overlay.dts | 2 +- 3 files changed, 20 insertions(+), 26 deletions(-) diff --git a/zephyr/projects/nissa/prj_pujjo.conf b/zephyr/projects/nissa/prj_pujjo.conf index e7e9cbd357..5ad45f7773 100644 --- a/zephyr/projects/nissa/prj_pujjo.conf +++ b/zephyr/projects/nissa/prj_pujjo.conf @@ -13,8 +13,9 @@ CONFIG_TACH_NPCX=y CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=256 # Sensor drivers -CONFIG_PLATFORM_EC_ACCELGYRO_LSM6DSO=y -CONFIG_PLATFORM_EC_ACCEL_LIS2DW12=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y # Keyboard CONFIG_CROS_KB_RAW_NPCX=y diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts index baeafe04ee..a5a1756c89 100644 --- a/zephyr/projects/nissa/pujjo_motionsense.dts +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -11,8 +11,7 @@ /* * Interrupt bindings for sensor devices. */ - lsm6dso-int = &base_accel; - lis2dw12-int = &lid_accel; + bmi3xx-int = &base_accel; }; /* @@ -37,14 +36,14 @@ motionsense-rotation-ref { compatible = "cros-ec,motionsense-rotation-ref"; lid_rot_ref: lid-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 + mat33 = <0 (-1) 0 + (-1) 0 0 0 0 (-1)>; }; - base_rot_ref: base-rot-ref { - mat33 = <(-1) 0 0 - 0 (-1) 0 + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 0 0 1>; }; }; @@ -59,13 +58,13 @@ * "struct als_drv_data_t" in accelgyro.h */ motionsense-sensor-data { - lsm6dso_data: lsm6dso-drv-data { - compatible = "cros-ec,drvdata-lsm6dso"; + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; status = "okay"; }; - lis2dw12_data: lis2dw12-drv-data { - compatible = "cros-ec,drvdata-lis2dw12"; + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; status = "okay"; }; }; @@ -80,7 +79,7 @@ */ motionsense-sensor { lid_accel: lid-accel { - compatible = "cros-ec,lis2dw12"; + compatible = "cros-ec,bma4xx"; status = "okay"; label = "Lid Accel"; @@ -90,8 +89,7 @@ port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&lid_rot_ref>; default-range = <2>; - drv-data = <&lis2dw12_data>; - i2c-spi-addr-flags = "LIS2DWL_ADDR0_FLAGS"; + drv-data = <&bma422_data>; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -107,7 +105,7 @@ }; base_accel: base-accel { - compatible = "cros-ec,lsm6dso-accel"; + compatible = "cros-ec,bmi3xx-accel"; status = "okay"; label = "Base Accel"; @@ -115,12 +113,8 @@ location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; - /* - * May be replaced by alternate depending - * on board config. - */ rot-standard-ref = <&base_rot_ref>; - drv-data = <&lsm6dso_data>; + drv-data = <&bmi323_data>; configs { compatible = "cros-ec,motionsense-sensor-config"; @@ -136,7 +130,7 @@ }; base_gyro: base-gyro { - compatible = "cros-ec,lsm6dso-gyro"; + compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; label = "Base Gyro"; @@ -145,8 +139,7 @@ mutex = <&base_mutex>; port = <&i2c_ec_i2c_sensor>; rot-standard-ref = <&base_rot_ref>; - default-range = <(1000 | ROUND_UP_FLAG)>; /* dps */ - drv-data = <&lsm6dso_data>; + drv-data = <&bmi323_data>; }; }; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts index 78e0522e9a..cbeaaa6d60 100644 --- a/zephyr/projects/nissa/pujjo_overlay.dts +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -58,7 +58,7 @@ int_imu: ec_imu { irq-pin = <&gpio_imu_int_l>; flags = ; - handler = "lsm6dso_interrupt"; + handler = "bmi3xx_interrupt"; }; int_vol_down: vol_down { irq-pin = <&gpio_voldn_btn_odl>; -- cgit v1.2.1 From 206b8c67919c3d00dcfc493388093989af1c6ff8 Mon Sep 17 00:00:00 2001 From: Tim Lin Date: Thu, 7 Jul 2022 13:06:08 +0800 Subject: zephyr: boards: support chip variants of it81202bx and it81302bx We divide baseboard into it81202bx and it81302bx, which is convenient for maintenance. BUG=none BRANCH=none TEST=zmake build it8xxx2_evb --clobber zmake build krabby --clobber zmake build tentacruel --clobber zmake build nereid --clobber zmake build joxer --clobber zmake build minimal-it8xxx2 --clobber TEST=zmake testall TEST=Make sure gpiok(0xf01690-0xf01697) and gpiol(0xf01698-0xf0169f) group are set as input and pull-down in krabby project and do not be set in nereid project. Change-Id: I5a12e9f97aef2ef14193491cfad46a6614969c8a Signed-off-by: Tim Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3650301 Commit-Queue: Dino Li Tested-by: Dino Li Reviewed-by: Andrew McRae Reviewed-by: Keith Short --- zephyr/boards/riscv/it8xxx2/it81202bx.dts | 8 ++++++ zephyr/boards/riscv/it8xxx2/it81202bx_defconfig | 34 ++++++++++++++++++++++ zephyr/boards/riscv/it8xxx2/it81302bx.dts | 8 ++++++ zephyr/boards/riscv/it8xxx2/it81302bx_defconfig | 34 ++++++++++++++++++++++ zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig | 38 ------------------------- zephyr/projects/corsola/BUILD.py | 4 +-- zephyr/projects/it8xxx2_evb/BUILD.py | 2 +- zephyr/projects/minimal/BUILD.py | 2 +- zephyr/projects/nissa/BUILD.py | 6 ++-- 9 files changed, 91 insertions(+), 45 deletions(-) create mode 100644 zephyr/boards/riscv/it8xxx2/it81202bx.dts create mode 100644 zephyr/boards/riscv/it8xxx2/it81202bx_defconfig create mode 100644 zephyr/boards/riscv/it8xxx2/it81302bx.dts create mode 100644 zephyr/boards/riscv/it8xxx2/it81302bx_defconfig delete mode 100644 zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx.dts b/zephyr/boards/riscv/it8xxx2/it81202bx.dts new file mode 100644 index 0000000000..76080c0a80 --- /dev/null +++ b/zephyr/boards/riscv/it8xxx2/it81202bx.dts @@ -0,0 +1,8 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/dts-v1/; + +#include "it8xxx2.dts" diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig new file mode 100644 index 0000000000..59fc3a1eaf --- /dev/null +++ b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig @@ -0,0 +1,34 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y +CONFIG_SOC_IT8XXX2=y +CONFIG_SOC_IT81202_BX=y + +# Platform Configuration +CONFIG_BOARD_IT8XXX2=y + +# Power Management +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_POLICY_CUSTOM=y + +# Console +CONFIG_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Controller +CONFIG_CLOCK_CONTROL=n + +# Serial Drivers +CONFIG_SERIAL=y + +# WATCHDOG configuration +CONFIG_WATCHDOG=y + +# BBRAM +CONFIG_BBRAM=y diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx.dts b/zephyr/boards/riscv/it8xxx2/it81302bx.dts new file mode 100644 index 0000000000..76080c0a80 --- /dev/null +++ b/zephyr/boards/riscv/it8xxx2/it81302bx.dts @@ -0,0 +1,8 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/dts-v1/; + +#include "it8xxx2.dts" diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig new file mode 100644 index 0000000000..ae66217f86 --- /dev/null +++ b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig @@ -0,0 +1,34 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Zephyr Kernel Configuration +CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y +CONFIG_SOC_IT8XXX2=y +CONFIG_SOC_IT81302_BX=y + +# Platform Configuration +CONFIG_BOARD_IT8XXX2=y + +# Power Management +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_POLICY_CUSTOM=y + +# Console +CONFIG_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Controller +CONFIG_CLOCK_CONTROL=n + +# Serial Drivers +CONFIG_SERIAL=y + +# WATCHDOG configuration +CONFIG_WATCHDOG=y + +# BBRAM +CONFIG_BBRAM=y diff --git a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig b/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig deleted file mode 100644 index 34612e9b42..0000000000 --- a/zephyr/boards/riscv/it8xxx2/it8xxx2_defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_RISCV32_IT8XXX2=y -CONFIG_SOC_IT8XXX2=y - -# Platform Configuration -CONFIG_BOARD_IT8XXX2=y - -# Power Management -CONFIG_PM=y -CONFIG_PM_DEVICE=y -CONFIG_PM_POLICY_CUSTOM=y - -# Console -CONFIG_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y -# For IT81202, the GPIO group k/l are not brought out to pins, -# so by default they can be set to pull down inputs. -# However with the IT81302, they are available on pins, -# and should not be set to pull down inputs by default. -CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN=n - -# Clock Controller -CONFIG_CLOCK_CONTROL=n - -# Serial Drivers -CONFIG_SERIAL=y - -# WATCHDOG configuration -CONFIG_WATCHDOG=y - -# BBRAM -CONFIG_BBRAM=y diff --git a/zephyr/projects/corsola/BUILD.py b/zephyr/projects/corsola/BUILD.py index ab3b8481f3..be01d46fec 100644 --- a/zephyr/projects/corsola/BUILD.py +++ b/zephyr/projects/corsola/BUILD.py @@ -4,12 +4,12 @@ """Define zmake projects for corsola.""" -# Default chip is it8xxx2, some variants will use NPCX9X. +# Default chip is it81202bx, some variants will use NPCX9X. def register_corsola_project( project_name, - chip="it8xxx2", + chip="it81202bx", extra_dts_overlays=(), extra_kconfig_files=(), ): diff --git a/zephyr/projects/it8xxx2_evb/BUILD.py b/zephyr/projects/it8xxx2_evb/BUILD.py index 2f4b87886b..19206183c3 100644 --- a/zephyr/projects/it8xxx2_evb/BUILD.py +++ b/zephyr/projects/it8xxx2_evb/BUILD.py @@ -6,7 +6,7 @@ register_raw_project( project_name="it8xxx2_evb", - zephyr_board="it8xxx2", + zephyr_board="it81302bx", dts_overlays=[ "adc.dts", "fan.dts", diff --git a/zephyr/projects/minimal/BUILD.py b/zephyr/projects/minimal/BUILD.py index bd79e32adb..f67064c70f 100644 --- a/zephyr/projects/minimal/BUILD.py +++ b/zephyr/projects/minimal/BUILD.py @@ -17,6 +17,6 @@ register_npcx_project( register_binman_project( project_name="minimal-it8xxx2", - zephyr_board="it8xxx2", + zephyr_board="it81302bx", dts_overlays=[here / "it8xxx2.dts"], ) diff --git a/zephyr/projects/nissa/BUILD.py b/zephyr/projects/nissa/BUILD.py index cfbeab0dda..31ae0c2ee0 100644 --- a/zephyr/projects/nissa/BUILD.py +++ b/zephyr/projects/nissa/BUILD.py @@ -9,7 +9,7 @@ def register_nissa_project( project_name, - chip="it8xxx2", + chip="it81302bx", extra_dts_overlays=(), extra_kconfig_files=(), ): @@ -43,7 +43,7 @@ nivviks = register_nissa_project( nereid = register_nissa_project( project_name="nereid", - chip="it8xxx2", + chip="it81302bx", extra_dts_overlays=[ here / "nereid_generated.dts", here / "nereid_overlay.dts", @@ -100,7 +100,7 @@ xivu = register_nissa_project( joxer = register_nissa_project( project_name="joxer", - chip="it8xxx2", + chip="it81302bx", extra_dts_overlays=[ here / "joxer_generated.dts", here / "joxer_overlay.dts", -- cgit v1.2.1 From 00217da2382ece25159e91e74b50b05a89eb83a5 Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Tue, 12 Jul 2022 17:11:56 +0800 Subject: BB retimer: Add bb retimer usb3 state enable The bb retimer usb3 state can be set to enable/disable. Add mutexing access to the BB_RETIMER_REG_CONNECTION_STATE register. BUG=b:233975818 BRANCH=None TEST=build make -j BOARD=Banshee pass Signed-off-by: johnwc_yeh Change-Id: Ie59223ac23d5380a52de0189b27fd12eeb81ec89 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756998 Reviewed-by: Diana Z --- driver/retimer/bb_retimer.c | 47 +++++++++++++++++++++++++++--- include/driver/retimer/bb_retimer_public.h | 8 +++++ 2 files changed, 51 insertions(+), 4 deletions(-) diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index d57c1318e5..add245cb08 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -37,6 +37,12 @@ #define BB_RETIMER_I2C_RETRY 5 +/* + * Mutex for BB_RETIMER_REG_CONNECTION_STATE register, which can be + * accessed from multiple tasks. + */ +K_MUTEX_DEFINE(bb_retimer_state_mutex); + /** * Utility functions */ @@ -376,10 +382,13 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, uint32_t set_retimer_con = 0; uint8_t dp_pin_mode; int port = me->usb_port; + int rv = 0; /* This driver does not use host command ACKs */ *ack_required = false; + mutex_lock(&bb_retimer_state_mutex); + /* * Bit 0: DATA_CONNECTION_PRESENT * 0 - No connection present @@ -464,8 +473,10 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, retimer_set_state_ufp(port, mux_state, &set_retimer_con); /* Writing the register4 */ - return bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, - set_retimer_con); + rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, + set_retimer_con); + mutex_unlock(&bb_retimer_state_mutex); + return rv; } void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, @@ -476,10 +487,13 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; + mutex_lock(&bb_retimer_state_mutex); + if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, - &retimer_con_reg) != EC_SUCCESS) + &retimer_con_reg) != EC_SUCCESS) { + mutex_unlock(&bb_retimer_state_mutex); return; - + } /* * Bit 14: IRQ_HPD (ignored if BIT8 = 0) * 0 - No IRQ_HPD @@ -514,6 +528,31 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, /* Writing the register4 */ bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg); + + mutex_unlock(&bb_retimer_state_mutex); +} + +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable) +{ + int rv; + uint32_t reg_val = 0; + + mutex_lock(&bb_retimer_state_mutex); + + rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, ®_val); + if (rv != EC_SUCCESS) { + mutex_unlock(&bb_retimer_state_mutex); + return; + } + /* Bit 5: USB_3_CONNECTION */ + WRITE_BIT(reg_val, 5, enable); + rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val); + if (rv != EC_SUCCESS) { + mutex_unlock(&bb_retimer_state_mutex); + return; + } + + mutex_unlock(&bb_retimer_state_mutex); } static int retimer_low_power_mode(const struct usb_mux *me) diff --git a/include/driver/retimer/bb_retimer_public.h b/include/driver/retimer/bb_retimer_public.h index d79b051504..133c733330 100644 --- a/include/driver/retimer/bb_retimer_public.h +++ b/include/driver/retimer/bb_retimer_public.h @@ -56,4 +56,12 @@ __override_proto int bb_retimer_power_enable(const struct usb_mux *me, void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required); +/** + * Enable/disable the USB3 state of BB retimer + * + * @param me Pointer to USB mux + * @param enable BB retimer USB3 state to be changed + */ +void bb_retimer_set_usb3(const struct usb_mux *me, bool enable); + #endif /* __CROS_EC_DRIVER_RETIMER_BB_RETIMER_PUBLIC_H */ -- cgit v1.2.1 From 1f105c3a3ad8c5f8bd807c27e6962860bed29cbb Mon Sep 17 00:00:00 2001 From: Leila Lin Date: Wed, 13 Jul 2022 09:36:32 +0800 Subject: Xivu: Bypass the HDMI function Xivu project has no HDMI port, but still need sub-board.c to do board init. Otherwise, the dut will not power on with AC only. Add the sub-board.c file but bypass the HDMI settings if the HDMI relate pin is not use. BUG=b:237432830 BRANCH=none TEST=zmake build xivu, and check dut can power on with AC only. Signed-off-by: Leila Lin Change-Id: I2ed0f827e6ca83d422e188241d69201595b95fad Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759828 Reviewed-by: Elmo Lan Reviewed-by: Andrew McRae Tested-by: LeilaCY Lin Commit-Queue: LeilaCY Lin Reviewed-by: Peter Marheine --- zephyr/projects/nissa/CMakeLists.txt | 6 +----- zephyr/projects/nissa/src/sub_board.c | 5 +++++ 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 258dbfdc3a..84d7ca57c1 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -8,6 +8,7 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) zephyr_include_directories(include) zephyr_library_sources("src/common.c") +zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_AP_PWRSEQ "src/board_power.c") if(DEFINED CONFIG_BOARD_NIVVIKS) @@ -17,7 +18,6 @@ if(DEFINED CONFIG_BOARD_NIVVIKS) "src/nivviks/form_factor.c" "src/nivviks/keyboard.c" ) - zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/nivviks/fan.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nivviks/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nivviks/charger.c") @@ -28,7 +28,6 @@ if(DEFINED CONFIG_BOARD_NEREID) "src/led.c" "src/nereid/keyboard.c" ) - zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/nereid/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/nereid/charger.c") endif() @@ -37,7 +36,6 @@ if(DEFINED CONFIG_BOARD_CRAASK) "src/craask/led.c" ) project(craask) - zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/craask/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/craask/charger.c") endif() @@ -47,7 +45,6 @@ if(DEFINED CONFIG_BOARD_PUJJO) "src/led.c" "src/pujjo/keyboard.c" ) - zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/pujjo/fan.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/pujjo/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/pujjo/charger.c") @@ -63,7 +60,6 @@ if(DEFINED CONFIG_BOARD_JOXER) "src/led.c" "src/joxer/keyboard.c" ) - zephyr_library_sources("src/sub_board.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "src/joxer/usbc.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_CHARGER "src/joxer/charger.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_FAN "src/joxer/fan.c") diff --git a/zephyr/projects/nissa/src/sub_board.c b/zephyr/projects/nissa/src/sub_board.c index 688fce0584..20c0e5185f 100644 --- a/zephyr/projects/nissa/src/sub_board.c +++ b/zephyr/projects/nissa/src/sub_board.c @@ -23,6 +23,8 @@ LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); +#define BOARD_HAS_HDMI_SUPPORT DT_NODE_EXISTS(DT_NODELABEL(gpio_hdmi_sel)) +#if BOARD_HAS_HDMI_SUPPORT static void hdmi_power_handler(struct ap_power_ev_callback *cb, struct ap_power_ev_data data) { @@ -65,6 +67,7 @@ static void hdmi_hpd_interrupt(const struct device *device, gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_hdmi_hpd), state); LOG_DBG("HDMI HPD changed state to %d", state); } +#endif static void lte_power_handler(struct ap_power_ev_callback *cb, struct ap_power_ev_data data) @@ -159,6 +162,7 @@ static void nereid_subboard_config(void) } switch (sb) { +#if BOARD_HAS_HDMI_SUPPORT case NISSA_SB_HDMI_A: { /* * HDMI: two outputs control power which must be configured to @@ -213,6 +217,7 @@ static void nereid_subboard_config(void) irq_unlock(irq_key); break; } +#endif case NISSA_SB_C_LTE: /* * LTE: Set up callbacks for enabling/disabling -- cgit v1.2.1 From 2dc06afe0e53e8db331275e9ed1a71bac5ab03b8 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Fri, 15 Jul 2022 12:02:23 +1000 Subject: ap_pwrseq: Send an INITIALIZED event when the pwrseq code is ready Send an event when the AP power sequence code is initialized and ready, for any clients that rely on knowing the state of the AP for their own initialization. BUG=none TEST=zmake testall BRANCH=none Signed-off-by: Andrew McRae Change-Id: Iab07e2489be1937780c3070c493fc08675785ad8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763024 Reviewed-by: Peter Marheine --- zephyr/include/ap_power/ap_power.h | 22 ++++++++++++++++++++-- .../x86_non_dsx_common_pwrseq_sm_handler.c | 7 ++++++- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/zephyr/include/ap_power/ap_power.h b/zephyr/include/ap_power/ap_power.h index 7959604ae0..efcdc46e96 100644 --- a/zephyr/include/ap_power/ap_power.h +++ b/zephyr/include/ap_power/ap_power.h @@ -9,7 +9,16 @@ * * Defines the API for AP event notification, * the API to register and receive notification callbacks when - * application processor (AP) events happen + * application processor (AP) events happen. + * + * When the Zephyr based AP power sequence config is enabled, + * the callbacks are almost all invoked within the context + * of the power sequence task, so the state is stable + * during the callback. The only exception to this is AP_POWER_RESET, which is + * invoked as a result of receiving a PLTRST# virtual wire signal (if enabled). + * + * When the legacy power sequence config is enabled, the callbacks are invoked + * from the HOOK_CHIPSET notifications. */ #ifndef __AP_POWER_AP_POWER_H__ @@ -87,6 +96,15 @@ enum ap_power_events { AP_POWER_HARD_OFF = BIT(8), /** Software reset occurred */ AP_POWER_RESET = BIT(9), + /** + * AP power state is now known. + * + * Prior to this event, the state of the AP is unknown + * and invalid. When this event is sent, the state is known + * and can be queried. Used by clients when their + * initialization depends upon the initial state of the AP. + */ + AP_POWER_INITIALIZED = BIT(10), }; /** @@ -113,7 +131,7 @@ typedef void (*ap_power_ev_callback_handler_t)(struct ap_power_ev_callback *cb, * are unique pointers of struct ap_power_ev_callback. * The storage must be static. * - * ap_power_ev_init_callback can be used to initialise this structure. + * ap_power_ev_init_callback can be used to initialize this structure. */ struct ap_power_ev_callback { sys_snode_t node; /* Only usable by AP power event code */ diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c index dd4b2e4e66..302d3cc16e 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c @@ -526,6 +526,11 @@ static void pwrseq_loop_thread(void *p1, void *p2, void *p3) power_signal_mask_t last_in_signals = 0; enum power_states_ndsx last_state = -1; + /* + * Let clients know that the AP power state is now + * initialized and ready. + */ + ap_power_ev_send_callbacks(AP_POWER_INITIALIZED); while (1) { curr_state = pwr_sm_get_state(); @@ -612,7 +617,7 @@ static int pwrseq_init(const struct device *dev) } /* - * The initialisation must occur after system I/O initialisation that + * The initialization must occur after system I/O initialization that * the signals depend upon, such as GPIO, ADC etc. */ SYS_INIT(pwrseq_init, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY); -- cgit v1.2.1 From 94267c1ed64c800ae5e4103fb415521749424675 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 13 Jul 2022 13:34:53 +0800 Subject: zephyr/shim/src/tcpc.c: disable clang-format The format is hard to read. Disable the format temporarily until the issue is resolved. BUG=none TEST=clang-format BRANCH=none Change-Id: I99dd40011652e3b2fa79cd980a6c506db60b294e Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759833 Tested-by: Eric Yilun Lin Auto-Submit: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Ting Shen --- zephyr/shim/src/tcpc.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index aef3a05b3c..26b913c645 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -27,25 +27,22 @@ #define MAYBE_CONST \ COND_CODE_1(CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG, (), (const)) +/* Enable clang-format when the formatted code is readable. */ +/* clang-format off */ MAYBE_CONST struct tcpc_config_t tcpc_config[] = { DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG, TCPC_CONFIG_CCGXXF) - DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, - TCPC_CONFIG_FUSB302) - DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_IT8XXX2) - DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_PS8XXX) - DT_FOREACH_STATUS_OKAY_VARGS( - NCT38XX_TCPC_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_NCT38XX) - DT_FOREACH_STATUS_OKAY_VARGS( - TCPCI_COMPAT, - TCPC_CONFIG, - TCPC_CONFIG_TCPCI) + DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_FUSB302) + DT_FOREACH_STATUS_OKAY_VARGS(IT8XXX2_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_IT8XXX2) + DT_FOREACH_STATUS_OKAY_VARGS(PS8XXX_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_PS8XXX) + DT_FOREACH_STATUS_OKAY_VARGS(NCT38XX_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_NCT38XX) + DT_FOREACH_STATUS_OKAY_VARGS(TCPCI_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_TCPCI) }; +/* clang-format on */ #endif /* DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 6d333ac4535c99728eea4c3a4b675feffb124701 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 13 Jul 2022 13:40:37 +0800 Subject: zephyr/shim/src/bc12.c: disable clang-format The format is hard to read. Disable the format temporarily until the issue is resolved. BUG=none TEST=clang-format BRANCH=none Change-Id: Ia457b765b625a9f7483aa89e44e98dad8ad6d201 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759834 Reviewed-by: Ting Shen Auto-Submit: Eric Yilun Lin Commit-Queue: Ting Shen Tested-by: Eric Yilun Lin --- zephyr/shim/src/bc12.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c index 4f1fd2db01..9ed57b6310 100644 --- a/zephyr/shim/src/bc12.c +++ b/zephyr/shim/src/bc12.c @@ -17,14 +17,16 @@ #define BC12_CHIP(id, fn) [USBC_PORT(id)] = fn(id) /* Power Path Controller */ +/* Enable clang-format when the formatted code is readable. */ +/* clang-format off */ struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP, BC12_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, - BC12_CHIP_RT9490) - DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, - BC12_CHIP, - BC12_CHIP_PI3USB9201) + DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, + BC12_CHIP_RT9490) + DT_FOREACH_STATUS_OKAY_VARGS(PI3USB9201_COMPAT, BC12_CHIP, + BC12_CHIP_PI3USB9201) }; +/* clang-format on */ #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 5e30bc0ea5d23f895efb1d068df1a98d944ebcfb Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Wed, 13 Jul 2022 14:49:23 +0800 Subject: zephyr/shim/src/ppc.c: disable clang-format The format is hard to read. Disable the format temporarily until the issue is resolved. BUG=none TEST=clang-format BRANCH=none Change-Id: Icc6c566792b22c19b13bc912ec622f6e1effe239 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759835 Tested-by: Eric Yilun Lin Auto-Submit: Eric Yilun Lin Commit-Queue: Ting Shen Reviewed-by: Ting Shen --- zephyr/shim/src/ppc.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c index 936367ca78..48a382174b 100644 --- a/zephyr/shim/src/ppc.c +++ b/zephyr/shim/src/ppc.c @@ -27,24 +27,29 @@ #define PPC_CHIP_ELE_ALT(id, fn) [PPC_ID(id)] = fn(id) /* Power Path Controller */ +/* Enable clang-format when the formatted code is readable. */ +/* clang-format off */ struct ppc_config_t ppc_chips[] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS( - SYV682X_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_SYV682X) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_SYV682X) }; +/* clang-format on */ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* Alt Power Path Controllers */ +/* clang-format off */ struct ppc_config_t ppc_chips_alt[] = { DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT, PPC_CHIP_RT1739) - DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, - PPC_CHIP_SN5S330) - DT_FOREACH_STATUS_OKAY_VARGS( - SYV682X_COMPAT, PPC_CHIP_ALT, PPC_CHIP_SYV682X) + DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_SN5S330) + DT_FOREACH_STATUS_OKAY_VARGS(SYV682X_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_SYV682X) }; +/* clang-format on */ #endif /* #if DT_HAS_COMPAT_STATUS_OKAY */ -- cgit v1.2.1 From 354bd338fd59a76cf3cf6ff84cbcb3dec828f0c3 Mon Sep 17 00:00:00 2001 From: Elsie Shih Date: Fri, 15 Jul 2022 15:09:33 +0800 Subject: moli: remove set fan pwm duty 100% in board_pwm_init() Remove set fan pwm duty 100% in board_pwm_init(), since moli has thermal table implemented. BUG=b:236294162 BRANCH=none TEST=make BOARD=moli Signed-off-by: Elsie Shih Change-Id: I8559293c8a639aee71418d45eb2b900d86c83786 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765106 Reviewed-by: Zhuohao Lee --- board/moli/pwm.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/board/moli/pwm.c b/board/moli/pwm.c index bba4f8cac9..f7dde565bf 100644 --- a/board/moli/pwm.c +++ b/board/moli/pwm.c @@ -27,14 +27,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); static void board_pwm_init(void) { - /* - * TODO(b/197478860): Turn on the fan at 100% by default - * We need to find tune the fan speed according to the - * thermal sensor value. - */ pwm_enable(PWM_CH_FAN, 1); - pwm_set_duty(PWM_CH_FAN, 100); - pwm_enable(PWM_CH_LED_BLUE, 1); pwm_enable(PWM_CH_LED_AMBER, 1); } -- cgit v1.2.1 From 75ea31b7dda9f4fd1dc902f26957c59fe1553d74 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 24 Jun 2022 16:56:26 +0800 Subject: rt1718s: support device binding for TCPC and BC1.2 support RichTek RT1718S BC1.2 and TCPC device binding BUG=b:227359727 TEST=zmake build -a BRANCH=none Change-Id: I3c13781e9bc53fa269295d900903d38ac91b1f0d Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3721945 Commit-Queue: Eric Yilun Lin Reviewed-by: Ting Shen Reviewed-by: Keith Short Tested-by: Eric Yilun Lin --- docs/zephyr/zephyr_bc12.md | 6 +++++ zephyr/dts/bindings/usbc/richtek,rt1718s-bc12.yaml | 7 +++++ zephyr/dts/bindings/usbc/richtek,rt1718s-tcpc.yaml | 30 ++++++++++++++++++++++ zephyr/shim/include/usbc/bc12_rt1718s.h | 13 ++++++++++ zephyr/shim/include/usbc/tcpc_rt1718s.h | 27 +++++++++++++++++++ zephyr/shim/src/bc12.c | 12 ++++++++- zephyr/shim/src/tcpc.c | 4 +++ 7 files changed, 98 insertions(+), 1 deletion(-) create mode 100644 zephyr/dts/bindings/usbc/richtek,rt1718s-bc12.yaml create mode 100644 zephyr/dts/bindings/usbc/richtek,rt1718s-tcpc.yaml create mode 100644 zephyr/shim/include/usbc/bc12_rt1718s.h create mode 100644 zephyr/shim/include/usbc/tcpc_rt1718s.h diff --git a/docs/zephyr/zephyr_bc12.md b/docs/zephyr/zephyr_bc12.md index 6fffc16358..b74d369eb7 100644 --- a/docs/zephyr/zephyr_bc12.md +++ b/docs/zephyr/zephyr_bc12.md @@ -22,6 +22,12 @@ A BC1.2 device node should be child of an USBC port node with a compatible property equals to "named-usbc-port". The USBC port node should have only one BC1.2 device node. +### Richtek RT1718S + +There are two nodes describing the Richtek RT1718, one for BC1.2 +[richtek,rt1718-bc12.yaml] and one for TCPC[richtek,rt1718s-tcpc.yaml]. The node +for the TCPC contains information about I2C bus and address. + ### Richtek RT1739 There are two nodes describing the Richtek RT1739, one for BC1.2 diff --git a/zephyr/dts/bindings/usbc/richtek,rt1718s-bc12.yaml b/zephyr/dts/bindings/usbc/richtek,rt1718s-bc12.yaml new file mode 100644 index 0000000000..6898d9ccd5 --- /dev/null +++ b/zephyr/dts/bindings/usbc/richtek,rt1718s-bc12.yaml @@ -0,0 +1,7 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: USBC RT1718S BC1.2 + +compatible: "richtek,rt1718s-bc12" diff --git a/zephyr/dts/bindings/usbc/richtek,rt1718s-tcpc.yaml b/zephyr/dts/bindings/usbc/richtek,rt1718s-tcpc.yaml new file mode 100644 index 0000000000..c82eed0e22 --- /dev/null +++ b/zephyr/dts/bindings/usbc/richtek,rt1718s-tcpc.yaml @@ -0,0 +1,30 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: USBC RT1718S TCPC + +compatible: "richtek,rt1718s-tcpc" + +properties: + port: + type: phandle + required: true + description: | + I2C port used to communicate with controller + + i2c-addr-flags: + type: string + default: "RT1718S_I2C_ADDR1_FLAGS" + enum: + - "RT1718S_I2C_ADDR1_FLAGS" + - "RT1718S_I2C_ADDR2_FLAGS" + description: | + I2C address of controller + + tcpc-flags: + type: int + default: 0 + description: | + TCPC configuration flags + diff --git a/zephyr/shim/include/usbc/bc12_rt1718s.h b/zephyr/shim/include/usbc/bc12_rt1718s.h new file mode 100644 index 0000000000..578d0dab5a --- /dev/null +++ b/zephyr/shim/include/usbc/bc12_rt1718s.h @@ -0,0 +1,13 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "tcpm/rt1718s_public.h" + +#define RT1718S_BC12_COMPAT richtek_rt1718s_bc12 + +#define BC12_CHIP_RT1718S(id) \ + { \ + .drv = &rt1718s_bc12_drv, \ + } diff --git a/zephyr/shim/include/usbc/tcpc_rt1718s.h b/zephyr/shim/include/usbc/tcpc_rt1718s.h new file mode 100644 index 0000000000..acab65b6e5 --- /dev/null +++ b/zephyr/shim/include/usbc/tcpc_rt1718s.h @@ -0,0 +1,27 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include "tcpm/rt1718s_public.h" + +#define RT1718S_TCPC_COMPAT richtek_rt1718s_tcpc + +/* + * Currently, the clang-format will force the back-slash at col:81. Enable + * format after we fix the issue. + */ +/* clang-format off */ +#define TCPC_CONFIG_RT1718S(id) \ + { \ + .bus_type = EC_BUS_TYPE_I2C, \ + .i2c_info = { \ + .port = I2C_PORT(DT_PHANDLE(id, port)), \ + .addr_flags = DT_STRING_UPPER_TOKEN( \ + id, i2c_addr_flags), \ + }, \ + .drv = &rt1718s_tcpm_drv, \ + .flags = DT_PROP(id, tcpc_flags), \ + } +/* clang-format on */ diff --git a/zephyr/shim/src/bc12.c b/zephyr/shim/src/bc12.c index 9ed57b6310..539e441949 100644 --- a/zephyr/shim/src/bc12.c +++ b/zephyr/shim/src/bc12.c @@ -5,21 +5,31 @@ #include #include "usbc/bc12_pi3usb9201.h" +#include "usbc/bc12_rt1718s.h" #include "usbc/bc12_rt1739.h" #include "usbc/bc12_rt9490.h" +#include "usbc/tcpc_rt1718s.h" #include "usbc/utils.h" #include "usb_charge.h" -#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \ +#if DT_HAS_COMPAT_STATUS_OKAY(RT1718S_BC12_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(RT1739_BC12_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(RT9490_BC12_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(PI3USB9201_COMPAT) +/* Check RT1718S dependency. BC12 node must be dependent on TCPC node. */ +#if DT_HAS_COMPAT_STATUS_OKAY(RT1718S_BC12_COMPAT) +BUILD_ASSERT(DT_HAS_COMPAT_STATUS_OKAY(RT1718S_TCPC_COMPAT)); +#endif + #define BC12_CHIP(id, fn) [USBC_PORT(id)] = fn(id) /* Power Path Controller */ /* Enable clang-format when the formatted code is readable. */ /* clang-format off */ struct bc12_config bc12_ports[CHARGE_PORT_COUNT] = { + DT_FOREACH_STATUS_OKAY_VARGS(RT1718S_BC12_COMPAT, BC12_CHIP, + BC12_CHIP_RT1718S) DT_FOREACH_STATUS_OKAY_VARGS(RT1739_BC12_COMPAT, BC12_CHIP, BC12_CHIP_RT1739) DT_FOREACH_STATUS_OKAY_VARGS(RT9490_BC12_COMPAT, BC12_CHIP, diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index 26b913c645..02cecdd70f 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -12,6 +12,7 @@ #include "usbc/tcpc_it8xxx2.h" #include "usbc/tcpc_nct38xx.h" #include "usbc/tcpc_ps8xxx.h" +#include "usbc/tcpc_rt1718s.h" #include "usbc/tcpci.h" #include "usbc/utils.h" @@ -20,6 +21,7 @@ DT_HAS_COMPAT_STATUS_OKAY(IT8XXX2_TCPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(PS8XXX_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(NCT38XX_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(RT1718S_TCPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(TCPCI_COMPAT) #define TCPC_CONFIG(id, fn) [USBC_PORT(id)] = fn(id) @@ -40,6 +42,8 @@ MAYBE_CONST struct tcpc_config_t tcpc_config[] = { TCPC_CONFIG_PS8XXX) DT_FOREACH_STATUS_OKAY_VARGS(NCT38XX_TCPC_COMPAT, TCPC_CONFIG, TCPC_CONFIG_NCT38XX) + DT_FOREACH_STATUS_OKAY_VARGS(RT1718S_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_RT1718S) DT_FOREACH_STATUS_OKAY_VARGS(TCPCI_COMPAT, TCPC_CONFIG, TCPC_CONFIG_TCPCI) }; -- cgit v1.2.1 From 8c001c5ab9b1216bfbc2b7f50f1f6fa95a225f7a Mon Sep 17 00:00:00 2001 From: Li Feng Date: Fri, 8 Jul 2022 15:54:34 -0700 Subject: retimer: require AP to ack TCSS mux config Enable AP mux ack with Hayden Bridge retimer. BUG=none BRANCH=none TEST=on MTL RVP, enter USB4 mode, receives MUX_ACK host command from AP when setting USB MUX. Signed-off-by: Li Feng Change-Id: If829a9bc8faba67a67f32bb329aae7d91ab94acf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3753330 Reviewed-by: Vijay P Hiremath Reviewed-by: Al Semjonovs --- include/config.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/config.h b/include/config.h index 0d73dbe03a..c633654484 100644 --- a/include/config.h +++ b/include/config.h @@ -6501,11 +6501,13 @@ /* * By default, enable a request for an ACK from AP, on setting the mux, if the - * board supports Burnside Bridge retimer. + * board supports Intel retimer. */ -#if defined(CONFIG_USBC_RETIMER_INTEL_BB) && defined(CONFIG_USB_MUX_VIRTUAL) +#if (defined(CONFIG_USBC_RETIMER_INTEL_BB) || \ + defined(CONFIG_USBC_RETIMER_INTEL_HB)) && \ + defined(CONFIG_USB_MUX_VIRTUAL) #define CONFIG_USB_MUX_AP_ACK_REQUEST -#endif /* CONFIG_USBC_RETIMER_INTEL_BB */ +#endif /* CONFIG_USBC_RETIMER_INTEL_BB || CONFIG_USBC_RETIMER_INTEL_HB */ /*****************************************************************************/ -- cgit v1.2.1 From 171fe207e672191cc9dbec722999e24d81798f16 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 8 Jul 2022 15:16:42 -0700 Subject: tree: Replace %pT with snprintf_timestamp Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=On icetower v0.1 with servo_micro and J-Trace attached: > reboot observe console shows timestamps Signed-off-by: Tom Hughes Change-Id: I6660ff22ebc6ba74f1245ff83026f5919b356a02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756178 Reviewed-by: Ting Shen --- baseboard/zork/baseboard.c | 5 ++++- board/twinkie/simpletrace.c | 19 +++++++++++++------ board/zinger/usb_pd_policy.c | 6 ++++-- common/acpi.c | 6 ++++-- common/capsense.c | 6 ++++-- common/console_output.c | 5 ++++- common/host_command.c | 5 ++++- common/keyboard_scan.c | 10 ++++++++-- common/lb_common.c | 5 ++++- common/motion_sense.c | 7 +++++-- common/port80.c | 11 ++++++++--- common/printf.c | 25 +++---------------------- include/console.h | 2 +- include/printf.h | 3 --- test/printf.c | 12 +++++------- zephyr/shim/src/console.c | 3 +-- 16 files changed, 72 insertions(+), 58 deletions(-) diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c index d10f8a4190..28cc8e69bd 100644 --- a/baseboard/zork/baseboard.c +++ b/baseboard/zork/baseboard.c @@ -31,6 +31,7 @@ #include "motion_sense.h" #include "power.h" #include "power_button.h" +#include "printf.h" #include "pwm.h" #include "pwm_chip.h" #include "registers.h" @@ -262,8 +263,10 @@ void board_print_temps(void) { int t, i; int rv; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; - cprintf(CC_THERMAL, "[%pT ", PRINTF_TIMESTAMP_NOW); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + cprintf(CC_THERMAL, "[%s ", ts_str); for (i = 0; i < TEMP_SENSOR_COUNT; ++i) { rv = temp_sensor_read(i, &t); if (rv == EC_SUCCESS) diff --git a/board/twinkie/simpletrace.c b/board/twinkie/simpletrace.c index 6f9e6d1da3..fdad25fff9 100644 --- a/board/twinkie/simpletrace.c +++ b/board/twinkie/simpletrace.c @@ -11,6 +11,7 @@ #include "hooks.h" #include "hwtimer.h" #include "injector.h" +#include "printf.h" #include "registers.h" #include "system.h" #include "task.h" @@ -105,9 +106,11 @@ static void print_packet(int head, uint32_t *payload) int id = PD_HEADER_ID(head); const char *name; const char *prole; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; if (trace_mode == TRACE_MODE_RAW) { - ccprintf("%pT[%04x]", PRINTF_TIMESTAMP_NOW, head); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + ccprintf("%s[%04x]", ts_str, head); for (i = 0; i < cnt; i++) ccprintf(" %08x", payload[i]); ccputs("\n"); @@ -115,8 +118,8 @@ static void print_packet(int head, uint32_t *payload) } name = cnt ? data_msg_name[typ] : ctrl_msg_name[typ]; prole = head & (PD_ROLE_SOURCE << 8) ? "SRC" : "SNK"; - ccprintf("%pT %s/%d [%04x]%s", PRINTF_TIMESTAMP_NOW, prole, id, head, - name); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + ccprintf("%s %s/%d [%04x]%s", ts_str, prole, id, head, name); if (!cnt) { /* Control message : we are done */ ccputs("\n"); return; @@ -146,12 +149,16 @@ static void print_packet(int head, uint32_t *payload) static void print_error(enum pd_rx_errors err) { + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; + + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + if (err == PD_RX_ERR_INVAL) - ccprintf("%pT TMOUT\n", PRINTF_TIMESTAMP_NOW); + ccprintf("%s TMOUT\n", ts_str); else if (err == PD_RX_ERR_HARD_RESET) - ccprintf("%pT HARD-RST\n", PRINTF_TIMESTAMP_NOW); + ccprintf("%s HARD-RST\n", ts_str); else if (err == PD_RX_ERR_UNSUPPORTED_SOP) - ccprintf("%pT SOP*\n", PRINTF_TIMESTAMP_NOW); + ccprintf("%s SOP*\n", ts_str); else ccprintf("ERR %d\n", err); } diff --git a/board/zinger/usb_pd_policy.c b/board/zinger/usb_pd_policy.c index 0bc884003b..084b7fc051 100644 --- a/board/zinger/usb_pd_policy.c +++ b/board/zinger/usb_pd_policy.c @@ -9,6 +9,7 @@ #include "debug_printf.h" #include "ec_commands.h" #include "hooks.h" +#include "printf.h" #include "registers.h" #include "system.h" #include "task.h" @@ -492,12 +493,13 @@ __override int pd_custom_vdm(int port, int cnt, uint32_t *payload, { int cmd = PD_VDO_CMD(payload[0]); int rsize; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; if (PD_VDO_VID(payload[0]) != USB_VID_GOOGLE || !gfu_mode) return 0; - debug_printf("%pT] VDM/%d [%d] %08x\n", PRINTF_TIMESTAMP_NOW, cnt, cmd, - payload[0]); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + debug_printf("%s] VDM/%d [%d] %08x\n", ts_str, cnt, cmd, payload[0]); *rpayload = payload; rsize = pd_custom_flash_vdm(port, cnt, payload); diff --git a/common/acpi.c b/common/acpi.c index ffb6acbc22..c6fe21f248 100644 --- a/common/acpi.c +++ b/common/acpi.c @@ -15,6 +15,7 @@ #include "host_command.h" #include "keyboard_backlight.h" #include "lpc.h" +#include "printf.h" #include "pwm.h" #include "timer.h" #include "tablet_mode.h" @@ -315,13 +316,14 @@ int acpi_ap_to_ec(int is_cmd, uint8_t value, uint8_t *resultptr) #endif #ifdef CONFIG_KEYBOARD_BACKLIGHT case EC_ACPI_MEM_KEYBOARD_BACKLIGHT: + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; /* * Debug output with CR not newline, because the host * does a lot of keyboard backlights and it scrolls the * debug console. */ - CPRINTF("\r[%pT ACPI kblight %d]", PRINTF_TIMESTAMP_NOW, - data); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("\r[%s ACPI kblight %d]", ts_str, data); kblight_set(data); kblight_enable(data > 0); break; diff --git a/common/capsense.c b/common/capsense.c index e5c3880e2a..ede5a05190 100644 --- a/common/capsense.c +++ b/common/capsense.c @@ -9,6 +9,7 @@ #include "hooks.h" #include "i2c.h" #include "keyboard_protocol.h" +#include "printf.h" #include "timer.h" /* Console output macro */ @@ -48,11 +49,12 @@ static void capsense_change_deferred(void) static uint8_t cur_val; uint8_t new_val; int i, n, c; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; new_val = capsense_read_bitmask(); if (new_val != cur_val) { - CPRINTF("[%pT capsense 0x%02x: ", PRINTF_TIMESTAMP_NOW, - new_val); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s capsense 0x%02x: ", ts_str, new_val); for (i = 0; i < CAPSENSE_MASK_BITS; i++) { /* See what changed */ n = (new_val >> i) & 0x01; diff --git a/common/console_output.c b/common/console_output.c index 4cd45127c9..0471559838 100644 --- a/common/console_output.c +++ b/common/console_output.c @@ -6,6 +6,7 @@ /* Console output module for Chrome EC */ #include "console.h" +#include "printf.h" #include "uart.h" #include "usb_console.h" #include "util.h" @@ -114,12 +115,14 @@ int cprints(enum console_channel channel, const char *format, ...) { int r, rv; va_list args; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; /* Filter out inactive channels */ if (console_channel_is_disabled(channel)) return EC_SUCCESS; - rv = cprintf(channel, "[%pT ", PRINTF_TIMESTAMP_NOW); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + rv = cprintf(channel, "[%s ", ts_str); va_start(args, format); r = uart_vprintf(format, args); diff --git a/common/host_command.c b/common/host_command.c index 775632c3bf..417a2f3465 100644 --- a/common/host_command.c +++ b/common/host_command.c @@ -12,6 +12,7 @@ #include "host_command.h" #include "link_defs.h" #include "lpc.h" +#include "printf.h" #include "shared_mem.h" #include "system.h" #include "task.h" @@ -588,11 +589,13 @@ static void dump_host_command_suppressed(int force) { #ifdef CONFIG_SUPPRESSED_HOST_COMMANDS int i; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; if (!force && !timestamp_expired(suppressed_cmd_deadline, NULL)) return; - CPRINTF("[%pT HC Suppressed:", PRINTF_TIMESTAMP_NOW); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s HC Suppressed:", ts_str); for (i = 0; i < ARRAY_SIZE(hc_suppressed_cmd); i++) { CPRINTF(" 0x%x=%d", hc_suppressed_cmd[i], hc_suppressed_cnt[i]); hc_suppressed_cnt[i] = 0; diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c index b35a90ac16..d9f9e16417 100644 --- a/common/keyboard_scan.c +++ b/common/keyboard_scan.c @@ -19,6 +19,7 @@ #include "keyboard_scan.h" #include "keyboard_test.h" #include "lid_switch.h" +#include "printf.h" #include "switch.h" #include "system.h" #include "tablet_mode.h" @@ -166,8 +167,10 @@ void keyboard_scan_enable(int enable, enum kb_scan_disable_masks mask) static void print_state(const uint8_t *state, const char *msg) { int c; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; - CPRINTF("[%pT KB %s:", PRINTF_TIMESTAMP_NOW, msg); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s KB %s:", ts_str, msg); for (c = 0; c < keyboard_cols; c++) { if (state[c]) CPRINTF(" %02x", state[c]); @@ -647,7 +650,10 @@ static int check_keys_changed(uint8_t *state) #ifdef CONFIG_KEYBOARD_PRINT_SCAN_TIMES /* Print delta times from now back to each previous scan */ - CPRINTF("[%pT kb deltaT", PRINTF_TIMESTAMP_NOW); + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; + + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s kb deltaT", ts_str); for (i = 0; i < SCAN_TIME_COUNT; i++) { int tnew = scan_time[(SCAN_TIME_COUNT + scan_time_index - i) % diff --git a/common/lb_common.c b/common/lb_common.c index 7cdd0067dd..5d565bb77f 100644 --- a/common/lb_common.c +++ b/common/lb_common.c @@ -97,6 +97,7 @@ #include "ec_commands.h" #include "i2c.h" #include "lb_common.h" +#include "printf.h" #include "util.h" /* Console output macros */ @@ -274,8 +275,10 @@ uint8_t lb_get_brightness(void) void lb_init(int use_lock) { int i; + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; - CPRINTF("[%pT LB_init_vals ", PRINTF_TIMESTAMP_NOW); + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s LB_init_vals ", ts_str); for (i = 0; i < ARRAY_SIZE(init_vals); i++) { CPRINTF("%c", '0' + i % 10); if (use_lock) diff --git a/common/motion_sense.c b/common/motion_sense.c index 776949b8aa..c47105a480 100644 --- a/common/motion_sense.c +++ b/common/motion_sense.c @@ -24,6 +24,7 @@ #include "motion_lid.h" #include "motion_orientation.h" #include "online_calibration.h" +#include "printf.h" #include "power.h" #include "queue.h" #include "tablet_mode.h" @@ -933,8 +934,10 @@ void motion_sense_task(void *u) } } if (IS_ENABLED(CONFIG_CMD_ACCEL_INFO) && (accel_disp)) { - CPRINTF("[%pT event 0x%08x ", PRINTF_TIMESTAMP_NOW, - event); + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; + + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("[%s event 0x%08x ", ts_str, event); for (i = 0; i < motion_sensor_count; ++i) { sensor = &motion_sensors[i]; CPRINTF("%s=%-5d, %-5d, %-5d ", sensor->name, diff --git a/common/port80.c b/common/port80.c index c7c9d714ff..66ad48be5e 100644 --- a/common/port80.c +++ b/common/port80.c @@ -11,6 +11,7 @@ #include "hooks.h" #include "host_command.h" #include "port80.h" +#include "printf.h" #include "task.h" #include "timer.h" #include "util.h" @@ -39,6 +40,8 @@ DECLARE_DEFERRED(port80_dump_buffer); void port_80_write(int data) { + char ts_str[PRINTF_TIMESTAMP_BUF_SIZE]; + /* * By default print_in_int is disabled if: * 1. CONFIG_BRINGUP is not defined @@ -53,9 +56,11 @@ void port_80_write(int data) * dump the current port80 buffer to EC console. This is to allow * developers to help debug BIOS progress by tracing port80 messages. */ - if (print_in_int) - CPRINTF("%c[%pT Port 80: 0x%02x]", scroll ? '\n' : '\r', - PRINTF_TIMESTAMP_NOW, data); + if (print_in_int) { + snprintf_timestamp_now(ts_str, sizeof(ts_str)); + CPRINTF("%c[%s Port 80: 0x%02x]", scroll ? '\n' : '\r', ts_str, + data); + } hook_call_deferred(&port80_dump_buffer_data, 4 * SECOND); diff --git a/common/printf.c b/common/printf.c index 01e9d0f544..b3e9d45109 100644 --- a/common/printf.c +++ b/common/printf.c @@ -394,30 +394,11 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, ptrval = va_arg(args, void *); /* * Avoid null pointer dereference for %ph. - * %pT and %pP can accept null. + * %pP can accept null. */ - if (ptrval == NULL && ptrspec != 'T' && - ptrspec != 'P') + if (ptrval == NULL && ptrspec != 'P') continue; - /* %pT - print a timestamp. */ - if (ptrspec == 'T' && - (!IS_ENABLED(CONFIG_ZEPHYR) || - IS_ENABLED(CONFIG_PLATFORM_EC_TIMER))) { - flags |= PF_64BIT; - if (ptrval == PRINTF_TIMESTAMP_NOW) - v = get_time().val; - else - v = *(uint64_t *)ptrval; - - if (IS_ENABLED( - CONFIG_CONSOLE_VERBOSE)) { - precision = 6; - } else { - precision = 3; - v /= 1000; - } - - } else if (ptrspec == 'h') { + else if (ptrspec == 'h') { /* %ph - Print a hex byte buffer. */ struct hex_buffer_params *hexbuf = ptrval; diff --git a/include/console.h b/include/console.h index 7adbb1d77c..192e24e8f9 100644 --- a/include/console.h +++ b/include/console.h @@ -167,7 +167,7 @@ cprintf(enum console_channel channel, const char *format, ...); /** * Print formatted output with timestamp. This is like: - * cprintf(channel, "[%pT " + format + "]\n", PRINTF_TIMESTAMP_NOW, ...) + * cprintf(channel, "[ " + format + "]\n", ...) * * @param channel Output channel * @param format Format string; see printf.h for valid formatting codes diff --git a/include/printf.h b/include/printf.h index 6df6405503..e5afb7f2d1 100644 --- a/include/printf.h +++ b/include/printf.h @@ -68,9 +68,6 @@ * - '%ph' - binary data, print as hex; Use HEX_BUF(buffer, size) to encode * parameters. * - '%pP' - raw pointer. - * - "%pT" - current time in seconds - interpreted as "%.6T" for precision. - * Supply PRINTF_TIMESTAMP_NOW to use the current time, or supply a - * pointer to a 64-bit timestamp to print. */ #ifndef HIDE_EC_STDLIB diff --git a/test/printf.c b/test/printf.c index 87059c30dc..0ef24d1acd 100644 --- a/test/printf.c +++ b/test/printf.c @@ -345,13 +345,11 @@ test_static int test_vsnprintf_timestamps(void) { uint64_t ts = 0; - T(expect_success("0.000000", "%pT", &ts)); - ts = 123456; - T(expect_success("0.123456", "%pT", &ts)); - ts = 9999999000000; - T(expect_success("9999999.000000", "%pT", &ts)); - ts = UINT64_MAX; - T(expect_success("18446744073709.551615", "%pT", &ts)); + /* + * Test %pT, which used to print timestamps, but is non-standard and no + * longer supported. + */ + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pT", &ts)); return EC_SUCCESS; } diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c index a37b96ab58..8dafaf9803 100644 --- a/zephyr/shim/src/console.c +++ b/zephyr/shim/src/console.c @@ -408,8 +408,7 @@ int cprints(enum console_channel channel, const char *format, ...) if (console_channel_is_disabled(channel)) return EC_SUCCESS; - rv = crec_snprintf(buff, CONFIG_SHELL_PRINTF_BUFF_SIZE, "[%pT ", - PRINTF_TIMESTAMP_NOW); + rv = snprintf_timestamp_now(buff, sizeof(buff)); handle_sprintf_rv(rv, &len); va_start(args, format); -- cgit v1.2.1 From ce12b52b10b973cfe75c8999c45dc6593f1f139b Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Tue, 12 Jul 2022 11:15:38 +0800 Subject: osiris: Move second fan enable pin to gpio97 Move second fan enable pin to gpio97 BUG=b:234545460 BRANCH=none TEST=make BOARD=osiris Signed-off-by: Yu-An Chen Change-Id: I9cba1ba97dd2d2f9e323aa6c9ff645d73645727c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756995 Reviewed-by: Boris Mittelberg Reviewed-by: Parth Malkan Commit-Queue: Boris Mittelberg --- board/osiris/fans.c | 2 +- board/osiris/gpio.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/osiris/fans.c b/board/osiris/fans.c index fd6e64befd..e5ea507099 100644 --- a/board/osiris/fans.c +++ b/board/osiris/fans.c @@ -39,7 +39,7 @@ static const struct fan_conf fan_conf_1 = { .flags = FAN_USE_RPM_MODE, .ch = MFT_CH_1, /* Use MFT id to control fan */ .pgood_gpio = -1, - .enable_gpio = GPIO_EN_PP5000_FAN, + .enable_gpio = GPIO_EN_PP5000_FAN2, }; /* diff --git a/board/osiris/gpio.inc b/board/osiris/gpio.inc index ccea91cf28..10172befa4 100644 --- a/board/osiris/gpio.inc +++ b/board/osiris/gpio.inc @@ -60,6 +60,7 @@ GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_R_ODL, PIN(C, 0), GPIO_ODR_HIGH) GPIO(EC_PROCHOT_ODL, PIN(6, 3), GPIO_ODR_HIGH) GPIO(EN_PP5000_FAN, PIN(6, 1), GPIO_OUT_LOW) +GPIO(EN_PP5000_FAN2, PIN(9, 7), GPIO_OUT_LOW) GPIO(EN_PP5000_USBA_R, PIN(D, 7), GPIO_OUT_LOW) GPIO(EN_S5_RAILS, PIN(B, 6), GPIO_OUT_LOW) GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT) @@ -122,7 +123,6 @@ UNUSED(PIN(8, 3)) /* GPIO83 */ UNUSED(PIN(7, 0)) /* GPIO70 */ UNUSED(PIN(8, 1)) /* GPIO81 */ UNUSED(PIN(9, 3)) /* GPIO93 */ -UNUSED(PIN(9, 7)) /* GPIO97 */ UNUSED(PIN(D, 0)) /* GPIOD0/I2C3_SDA0 */ UNUSED(PIN(D, 1)) /* GPIOD1/I2C3_SCL0 */ -- cgit v1.2.1 From 053549018ff686d1763b9d86992bee5d49a34593 Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Fri, 15 Jul 2022 16:06:07 +0000 Subject: Revert "Skyrim: Remove guybrush support" This reverts commit f9bbc1f59586878d9bbb9eac25e959e306661e67. Reason for revert: Breaks gitlab: https://gitlab.com/zephyr-ec/ec/-/jobs/2724604404 Original change's description: > Skyrim: Remove guybrush support > > Skyrim hardware is available now, so remove guybrush as a skyrim > "variant". > > BUG=b:231996904 > TEST=emerge-skyrim chromeos-zephyr > BRANCH=None > > Change-Id: Id8084000b112fe38a8f9556688e4d9c8edd68b10 > Signed-off-by: Tim Van Patten > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763782 > Reviewed-by: Diana Z Bug: b:231996904 Change-Id: I046926c82ad9fdcd4c8835bf22227dbf70afed95 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765443 Reviewed-by: Tim Van Patten Tested-by: Tim Van Patten Reviewed-by: Jeremy Bettis Commit-Queue: Tim Van Patten --- zephyr/projects/skyrim/BUILD.py | 3 + zephyr/projects/skyrim/CMakeLists.txt | 4 + zephyr/projects/skyrim/Kconfig | 6 + zephyr/projects/skyrim/guybrush.dts | 198 ++++++++ zephyr/projects/skyrim/power_signals_guybrush.c | 127 +++++ zephyr/projects/skyrim/prj_guybrush.conf | 9 + zephyr/projects/skyrim/usbc_config_guybrush.c | 599 ++++++++++++++++++++++++ 7 files changed, 946 insertions(+) create mode 100644 zephyr/projects/skyrim/guybrush.dts create mode 100644 zephyr/projects/skyrim/power_signals_guybrush.c create mode 100644 zephyr/projects/skyrim/prj_guybrush.conf create mode 100644 zephyr/projects/skyrim/usbc_config_guybrush.c diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py index a8b2da3716..3d43b3676b 100644 --- a/zephyr/projects/skyrim/BUILD.py +++ b/zephyr/projects/skyrim/BUILD.py @@ -33,3 +33,6 @@ def register_variant(project_name): register_variant(project_name="skyrim") + +# TODO: Deprecate guybrush build after skyrim hardware is readily available. +# register_variant(project_name="guybrush") diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt index bc4c51b40a..54039ecab8 100644 --- a/zephyr/projects/skyrim/CMakeLists.txt +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -5,12 +5,16 @@ cmake_minimum_required(VERSION 3.13.1) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(guybrush) cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) +cros_ec_library_include_directories_ifdef(CONFIG_BOARD_GUYBRUSH include_guybrush) zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "power_signals.c") +zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "power_signals_guybrush.c") zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "usbc_config.c") +zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "usbc_config_guybrush.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "usb_pd_policy.c") diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig index 6da27ee2d0..ea68baf71b 100644 --- a/zephyr/projects/skyrim/Kconfig +++ b/zephyr/projects/skyrim/Kconfig @@ -2,6 +2,12 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. +config BOARD_GUYBRUSH + bool "Google Guybrush Board" + help + Build Google Guybrush reference board. This board build is a + prototype rather than a releasing product. + config BOARD_SKYRIM bool "Google Skyrim Board" help diff --git a/zephyr/projects/skyrim/guybrush.dts b/zephyr/projects/skyrim/guybrush.dts new file mode 100644 index 0000000000..6c5c72d061 --- /dev/null +++ b/zephyr/projects/skyrim/guybrush.dts @@ -0,0 +1,198 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_wp; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; + + named-gpios { + /* Guybrush-specific GPIO customizations */ + gpio_wp: ec_wp_l { + gpios = <&gpio5 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { + gpios = <&gpio0 1 GPIO_INPUT>; + }; + gpio_slp_s3_s0i3_l: slp_s3_s0i3_l { + gpios = <&gpio7 4 GPIO_INPUT>; + enum-name = "GPIO_PCH_SLP_S0_L"; + }; + gpio_ec_pcore_int_odl: ec_pcore_int_odl { + gpios = <&gpiof 0 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_groupc_s0_od: pg_groupc_s0_od { + gpios = <&gpioa 3 GPIO_INPUT>; + }; + gpio_pg_lpddr4x_s3_od: pg_lpddr4x_s3_od { + gpios = <&gpio9 5 GPIO_INPUT>; + }; + ec_soc_pwr_good { + gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_PCH_SYS_PWROK"; + }; + ec_entering_rw { + gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; + enum-name = "GPIO_ENTERING_RW"; + }; + ec_clr_cmos { + gpios = <&gpioa 1 GPIO_OUTPUT_LOW>; + }; + ec_mem_event { + gpios = <&gpioa 5 GPIO_OUTPUT_LOW>; + }; + gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { + gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + ec_soc_int_l { + gpios = <&gpio8 3 GPIO_OUTPUT_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + soc_thermtrip_odl { + gpios = <&gpioe 5 GPIO_INPUT>; + }; + gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl { + gpios = <&gpio7 3 GPIO_ODR_HIGH>; + }; + 3axis_int_l { + gpios = <&gpioa 2 GPIO_INPUT_PULL_DOWN>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioa 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + ec_ps2_clk { + gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; + }; + ec_ps2_dat { + gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; + }; + ec_ps2_rst { + gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; + }; + ec_gpiob0 { + gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; + }; + ec_gpio81 { + gpios = <&gpio8 1 GPIO_INPUT_PULL_UP>; + }; + ec_psl_gpo { + gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>; + }; + ec_pwm7 { + gpios = <&gpio6 0 GPIO_INPUT_PULL_UP>; + }; + gpio_accel_gyro_int_l: accel_gyro_int_l { + gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>; + }; + }; + + def-lvol-io-list { + compatible = "nuvoton,npcx-lvolctrl-def"; + + /* Low voltage on I2C6_1 */ + lvol-io-pads = <&lvol_ioe4 &lvol_ioe3>; + }; + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_temp_soc: temp-soc { + label = "SOC"; + enum-name = "ADC_TEMP_SENSOR_SOC"; + io-channels = <&adc0 0>; + }; + }; + + named-temp-sensors { + soc-tmp112 { + compatible = "cros-ec,temp-sensor-tmp112", + "cros-ec,temp-sensor"; + label = "SOC"; + enum-name = "TEMP_SENSOR_SOC"; + tmp112-name = "TMP112_SOC"; + port = <&i2c_sensor>; + i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS0"; + temp_host_high = <100>; + temp_host_halt = <105>; + temp_host_release_high = <80>; + temp_fan_off = <0>; + temp_fan_max = <70>; + }; + amb-tmp112 { + compatible = "cros-ec,temp-sensor-tmp112", + "cros-ec,temp-sensor"; + label = "Ambient"; + enum-name = "TEMP_SENSOR_AMB"; + tmp112-name = "TMP112_AMB"; + port = <&i2c_sensor>; + i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS1"; + }; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_pg_lpddr4x_s3: pg_lpddr4x_s3 { + irq-pin = <&gpio_pg_lpddr4x_s3_od>; + flags = ; + handler = "baseboard_en_pwr_pcore_s0"; + }; + int_slp_s3_s0i3: slp_s3_s0i3 { + irq-pin = <&gpio_slp_s3_s0i3_l>; + flags = ; + handler = "power_signal_interrupt"; + }; + int_ec_pwr_btn: ec_pwr_btn { + irq-pin = <&gpio_ec_pwr_btn_odl>; + flags = ; + handler = "power_signal_interrupt"; + }; + int_ec_pcore: ec_pcore { + irq-pin = <&gpio_ec_pcore_int_odl>; + flags = ; + handler = "power_signal_interrupt"; + }; + int_pg_groupc_s0: pg_groupc_s0 { + irq-pin = <&gpio_pg_groupc_s0_od>; + flags = ; + handler = "baseboard_en_pwr_pcore_s0"; + }; + int_s0_pgood: s0_pgood { + irq-pin = <&gpio_s0_pgood>; + flags = ; + handler = "power_signal_interrupt"; + }; + }; + + /* Rotation matrices for motion sensors. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <(-1) 0 0 + 0 1 0 + 0 0 (-1)>; + }; + }; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c new file mode 100644 index 0000000000..ba9eb1a92f --- /dev/null +++ b/zephyr/projects/skyrim/power_signals_guybrush.c @@ -0,0 +1,127 @@ +/* Copyright 2021 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + +#include "chipset.h" +#include "config.h" +#include "gpio_signal.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "power.h" +#include "timer.h" + +/* Wake Sources */ +/* TODO: b/218904113: Convert to using Zephyr GPIOs */ +const enum gpio_signal hibernate_wake_pins[] = { + GPIO_LID_OPEN, + GPIO_AC_PRESENT, + GPIO_POWER_BUTTON_L, +}; +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + +/* Power Signal Input List */ +/* TODO: b/218904113: Convert to using Zephyr GPIOs */ +const struct power_signal_info power_signal_list[] = { + [X86_SLP_S0_N] = { + .gpio = GPIO_PCH_SLP_S0_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S0_DEASSERTED", + }, + [X86_SLP_S3_N] = { + .gpio = GPIO_PCH_SLP_S3_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S3_DEASSERTED", + }, + [X86_SLP_S5_N] = { + .gpio = GPIO_PCH_SLP_S5_L, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "SLP_S5_DEASSERTED", + }, + [X86_S0_PGOOD] = { + .gpio = GPIO_S0_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S0_PGOOD", + }, + [X86_S5_PGOOD] = { + .gpio = GPIO_S5_PGOOD, + .flags = POWER_SIGNAL_ACTIVE_HIGH, + .name = "S5_PGOOD", + }, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +static void baseboard_interrupt_init(void) +{ + /* Enable Power Group interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr4x_s3)); +} +DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_POST_I2C); + +/** + * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting + * PCH_PWRBTN_L. + */ +void board_pwrbtn_to_pch(int level) +{ + timestamp_t start; + const uint32_t timeout_rsmrst_rise_us = 30 * MSEC; + + /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ + if (!level && + !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) { + start = get_time(); + do { + usleep(200); + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_ec_soc_rsmrst_l))) + break; + } while (time_since32(start) < timeout_rsmrst_rise_us); + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) + ccprints("Error pwrbtn: RSMRST_L still low"); + + msleep(16); + } + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level); +} + +void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) +{ + /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_pg_lpddr4x_s3_od)) && + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_pg_groupc_s0_od))); +} + +void baseboard_en_pwr_s0(enum gpio_signal signal) +{ + /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), + gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && + gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); + + /* Now chain off to the normal power signal interrupt handler. */ + power_signal_interrupt(signal); +} + +void baseboard_s5_pgood(enum gpio_signal signal) +{ + baseboard_en_pwr_s0(signal); +} + +void baseboard_set_en_pwr_s3(enum gpio_signal signal) +{ + /* EC has no EN_PWR_S3 on this board */ + + /* Chain off the normal power signal interrupt handler */ + power_signal_interrupt(signal); +} diff --git a/zephyr/projects/skyrim/prj_guybrush.conf b/zephyr/projects/skyrim/prj_guybrush.conf new file mode 100644 index 0000000000..0ca57174a4 --- /dev/null +++ b/zephyr/projects/skyrim/prj_guybrush.conf @@ -0,0 +1,9 @@ +# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Guybrush board-specific Kconfig settings. +CONFIG_BOARD_GUYBRUSH=y + +# Only Guybrush has TMP112 +CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112=y \ No newline at end of file diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c new file mode 100644 index 0000000000..ef9a47e52c --- /dev/null +++ b/zephyr/projects/skyrim/usbc_config_guybrush.c @@ -0,0 +1,599 @@ +/* Copyright 2022 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Guybrush family-specific USB-C configuration */ + +#include "cros_board_info.h" +#include "battery_fuel_gauge.h" +#include "charge_manager.h" +#include "charge_ramp.h" +#include "charge_state_v2.h" +#include "charge_state.h" +#include "charger.h" +#include "driver/bc12/pi3usb9201.h" +#include "driver/charger/isl9241.h" +#include "driver/ppc/aoz1380.h" +#include "driver/ppc/nx20p348x.h" +#include "driver/retimer/anx7491.h" +#include "driver/retimer/ps8811.h" +#include "driver/retimer/ps8818.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/usb_mux/anx7451.h" +#include "driver/usb_mux/amd_fp6.h" +#include "gpio.h" +#include "gpio/gpio_int.h" +#include "hooks.h" +#include "ioexpander.h" +#include "power.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "usbc_ppc.h" + +#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) +#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) + +/* USB-A ports */ +enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; + +/* USB-C ports */ +enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; +BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); + +static void reset_nct38xx_port(int port); + +static void usbc_interrupt_init(void) +{ + /* Enable PPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); + + /* Enable TCPC interrupts. */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); + + /* Enable BC 1.2 interrupts */ + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); + gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); + + /* TODO: Enable SBU fault interrupts (io expander )*/ +} +DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); + +struct ppc_config_t ppc_chips[] = { + [USBC_PORT_C0] = { + /* Device does not talk I2C */ + .drv = &aoz1380_drv + }, + + [USBC_PORT_C1] = { + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, + .drv = &nx20p348x_drv + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +/* + * .init is not necessary here because it has nothing + * to do. Primary mux will handle mux state so .get is + * not needed as well. usb_mux.c can handle the situation + * properly. + */ +static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t, bool *); +struct usb_mux_driver usbc0_sbu_mux_driver = { + .set = fsusb42umx_set_mux, +}; + +/* + * Since FSUSB42UMX is not a i2c device, .i2c_port and + * .i2c_addr_flags are not required here. + */ +struct usb_mux usbc0_sbu_mux = { + .usb_port = USBC_PORT_C0, + .driver = &usbc0_sbu_mux_driver, +}; + +__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + CPRINTSUSB("C1: PS8818 mux using default tuning"); + return 0; +} + +struct usb_mux usbc1_ps8818 = { + .usb_port = USBC_PORT_C1, + .i2c_port = I2C_PORT_TCPC1, + .flags = USB_MUX_FLAG_RESETS_IN_G3, + .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, + .driver = &ps8818_usb_retimer_driver, + .board_set = &board_c1_ps8818_mux_set, +}; + +/* + * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default + * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c + * address to 0x2A. ANX7491(A1) will stay at the default 0x29. + */ +uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me) +{ + ASSERT(me->usb_port == USBC_PORT_C1); + return 0x2a; +} + +__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, + mux_state_t mux_state) +{ + CPRINTSUSB("C1: ANX7451 mux using default tuning"); + return 0; +} + +struct usb_mux usbc1_anx7451 = { + .usb_port = USBC_PORT_C1, + .i2c_port = I2C_PORT_TCPC1, + .flags = USB_MUX_FLAG_RESETS_IN_G3, + .i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS, + .driver = &anx7451_usb_mux_driver, + .board_set = &board_c1_anx7451_mux_set, +}; + +struct usb_mux usb_muxes[] = { + [USBC_PORT_C0] = { + .usb_port = USBC_PORT_C0, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, + .driver = &amd_fp6_usb_mux_driver, + .next_mux = &usbc0_sbu_mux, + }, + [USBC_PORT_C1] = { + .usb_port = USBC_PORT_C1, + .i2c_port = I2C_PORT_USB_MUX, + .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, + .driver = &amd_fp6_usb_mux_driver, + /* .next_mux = filled in by setup_mux based on fw_config */ + } +}; +BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); + +/* + * USB C0 port SBU mux use standalone FSUSB42UMX + * chip and it needs a board specific driver. + * Overall, it will use chained mux framework. + */ +static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state, + bool *ack_required) +{ + /* This driver does not use host command ACKs */ + *ack_required = false; + + if (mux_state & USB_PD_MUX_POLARITY_INVERTED) + ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); + else + ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); + + return EC_SUCCESS; +} + +static void setup_mux(void) +{ + /* TODO: Fill in C1 mux based on CBI */ + CPRINTSUSB("C1: Setting ANX7451 mux"); + usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; +} +DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); + +int board_set_active_charge_port(int port) +{ + int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); + int i; + int rv; + + if (port == CHARGE_PORT_NONE) { + CPRINTSUSB("Disabling all charger ports"); + + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + /* + * If this port had booted in dead battery mode, go + * ahead and reset it so EN_SNK responds properly. + */ + if (nct38xx_get_boot_type(i) == + NCT38XX_BOOT_DEAD_BATTERY) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + } + + /* + * Do not return early if one fails otherwise we can + * get into a boot loop assertion failure. + */ + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("Disabling C%d as sink failed.", i); + } + + return EC_SUCCESS; + } else if (!is_valid_port) { + return EC_ERROR_INVAL; + } + + /* + * Check if we can reset any ports in dead battery mode + * + * The NCT3807 may continue to keep EN_SNK low on the dead battery port + * and allow a dangerous level of voltage to pass through to the initial + * charge port (see b/183660105). We must reset the ports if we have + * sufficient battery to do so, which will bring EN_SNK back under + * normal control. + */ + rv = EC_SUCCESS; + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { + CPRINTSUSB("Found dead battery on %d", i); + /* + * If we have battery, get this port reset ASAP. + * This means temporarily rejecting charge manager + * sets to it. + */ + if (pd_is_battery_capable()) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + + if (port == i) + rv = EC_ERROR_INVAL; + } else if (port != i) { + /* + * If other port is selected and in dead battery + * mode, reset this port. Otherwise, reject + * change because we'll brown out. + */ + if (nct38xx_get_boot_type(port) == + NCT38XX_BOOT_DEAD_BATTERY) { + reset_nct38xx_port(i); + pd_set_error_recovery(i); + } else { + rv = EC_ERROR_INVAL; + } + } + } + } + + if (rv != EC_SUCCESS) + return rv; + + /* Check if the port is sourcing VBUS. */ + if (tcpm_get_src_ctrl(port)) { + CPRINTSUSB("Skip enable C%d", port); + return EC_ERROR_INVAL; + } + + CPRINTSUSB("New charge port: C%d", port); + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTSUSB("C%d: sink path disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTSUSB("C%d: sink path enable failed.", port); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +/* + * In the AOZ1380 PPC, there are no programmable features. We use + * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 + * current limits. + */ +int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv = EC_SUCCESS; + + rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, + (rp == TYPEC_RP_3A0) ? 1 : 0); + + return rv; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, + int charge_mv) +{ + charge_set_input_current_limit( + MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); +} + +/* TODO: sbu_fault_interrupt from io expander */ + +/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ +#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 +static void set_ac_prochot(void) +{ + isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); +} +DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); + +void tcpc_alert_event(enum gpio_signal signal) +{ + int port; + + switch (signal) { + case GPIO_USB_C0_TCPC_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_TCPC_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +static void reset_nct38xx_port(int port) +{ + const struct gpio_dt_spec *reset_gpio_l; + + /* TODO: Save and restore ioex signals */ + if (port == USBC_PORT_C0) + reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l); + else if (port == USBC_PORT_C1) + reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l); + else + /* Invalid port: do nothing */ + return; + + gpio_pin_set_dt(reset_gpio_l, 0); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); + gpio_pin_set_dt(reset_gpio_l, 1); + nct38xx_reset_notify(port); + if (NCT3807_RESET_POST_DELAY_MS != 0) + msleep(NCT3807_RESET_POST_DELAY_MS); +} + +void board_reset_pd_mcu(void) +{ + /* Reset TCPC0 */ + reset_nct38xx_port(USBC_PORT_C0); + + /* Reset TCPC1 */ + reset_nct38xx_port(USBC_PORT_C1); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + /* + * Check which port has the ALERT line set and ignore if that TCPC has + * its reset line active. + */ + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c0_tcpc_rst_l)) != 0) + status |= PD_STATUS_TCPC_ALERT_0; + } + + if (!gpio_pin_get_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( + gpio_usb_c1_tcpc_rst_l)) != 0) + status |= PD_STATUS_TCPC_ALERT_1; + } + + return status; +} + +void ppc_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_PPC_INT_ODL: + aoz1380_interrupt(USBC_PORT_C0); + break; + + case GPIO_USB_C1_PPC_INT_ODL: + nx20p348x_interrupt(USBC_PORT_C1); + break; + + default: + break; + } +} + +void bc12_interrupt(enum gpio_signal signal) +{ + switch (signal) { + case GPIO_USB_C0_BC12_INT_ODL: + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + break; + + case GPIO_USB_C1_BC12_INT_ODL: + usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); + break; + + default: + break; + } +} + +/** + * Return if VBUS is sagging too low + * + * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current + * until voltage drops to 4.5V. Don't go lower than this to be kind to the + * charger (see b/67964166). + */ +#define BC12_MIN_VOLTAGE 4500 +int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) +{ + int voltage = 0; + int rv; + + rv = charger_get_vbus_voltage(port, &voltage); + + if (rv) { + CPRINTSUSB("%s rv=%d", __func__, rv); + return 0; + } + + /* + * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown + * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. + * This partly defeats the point of ramping, but will still catch + * VBUS below 4.5V and above 0V. + */ + if (voltage == 0) { + CPRINTSUSB("%s vbus=0", __func__); + return 0; + } + + if (voltage < BC12_MIN_VOLTAGE) + CPRINTSUSB("%s vbus=%d", __func__, voltage); + + return voltage < BC12_MIN_VOLTAGE; +} + +#define SAFE_RESET_VBUS_DELAY_MS 900 +#define SAFE_RESET_VBUS_MV 5000 +void board_hibernate(void) +{ + int port; + enum ec_error_list ret; + + /* + * If we are charging, then drop the Vbus level down to 5V to ensure + * that we don't get locked out of the 6.8V OVLO for our PPCs in + * dead-battery mode. This is needed when the TCPC/PPC rails go away. + * (b/79218851, b/143778351, b/147007265) + */ + port = charge_manager_get_active_charge_port(); + if (port != CHARGE_PORT_NONE) { + pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); + + /* Give PD task and PPC chip time to get to 5V */ + msleep(SAFE_RESET_VBUS_DELAY_MS); + } + + /* Try to put our battery fuel gauge into sleep mode */ + ret = battery_sleep_fuel_gauge(); + if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED)) + cprints(CC_SYSTEM, "Failed to send battery sleep command"); +} + +__overridable enum ec_error_list +board_a1_ps8811_retimer_init(const struct usb_mux *me) +{ + return EC_SUCCESS; +} + +static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me) +{ + int rv; + int tries = 2; + + do { + int val; + + rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, + PS8811_REG1_USB_BEQ_LEVEL, &val); + } while (rv && --tries); + + if (rv) { + CPRINTSUSB("A1: PS8811 retimer not detected!"); + return rv; + } + CPRINTSUSB("A1: PS8811 retimer detected"); + rv = board_a1_ps8811_retimer_init(me); + if (rv) + CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv); + return rv; +} + +/* + * PS8811 is just a type-A USB retimer, reusing mux structure for + * convenience. + */ +const struct usb_mux usba1_ps8811 = { + .usb_port = USBA_PORT_A1, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3, + .board_init = &baseboard_a1_ps8811_retimer_init, +}; + +__overridable enum ec_error_list +board_a1_anx7491_retimer_init(const struct usb_mux *me) +{ + return EC_SUCCESS; +} + +static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me) +{ + int rv; + int tries = 2; + + do { + int val; + + rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val); + } while (rv && --tries); + if (rv) { + CPRINTSUSB("A1: ANX7491 retimer not detected!"); + return rv; + } + CPRINTSUSB("A1: ANX7491 retimer detected"); + rv = board_a1_anx7491_retimer_init(me); + if (rv) + CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv); + return rv; +} + +/* + * ANX7491 is just a type-A USB retimer, reusing mux structure for + * convenience. + */ +const struct usb_mux usba1_anx7491 = { + .usb_port = USBA_PORT_A1, + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS, + .board_init = &baseboard_a1_anx7491_retimer_init, +}; + +void baseboard_a1_retimer_setup(void) +{ + struct usb_mux a1_retimer; + + /* TODO: Support PS8811 retimer through CBI */ + a1_retimer = usba1_anx7491; + a1_retimer.board_init(&a1_retimer); +} +DECLARE_DEFERRED(baseboard_a1_retimer_setup); + +/* TODO: Remove when guybrush is no longer supported */ +#ifdef CONFIG_BOARD_GUYBRUSH +void board_overcurrent_event(int port, int is_overcurrented) +{ + switch (port) { + case USBC_PORT_C0: + case USBC_PORT_C1: + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_usb_c0_c1_fault_odl), + !is_overcurrented); + break; + + default: + break; + } +} +#endif -- cgit v1.2.1 From fa214ce48494643a07d2ad2ab91836532d98bbf2 Mon Sep 17 00:00:00 2001 From: Li Feng Date: Sat, 2 Jul 2022 22:38:29 -0700 Subject: TCPMv2: TBT cable entry/exit should be symmetrical If SOP'/SOP'' enters TBT alt mode; then the code should have exit logic for SOP'/SOP'' too. With LRD cable, there is SOP' enter mode, but no SOP' exit mode. The LRD cable SOP' exit mode logic is added. Also only check SOP'' field in the active cable identity VDO when the cable reports it's active. BUG=none BRANCH=none TEST=on Brya, connect TBT dock with LRD cable, SOP' exit mode is sent when exit TBT alt mode. Signed-off-by: Li Feng Change-Id: Idef5a381ea3b51b4b5a5e102bd321eb8fb87dca4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3746291 Reviewed-by: Abe Levkoy Commit-Queue: Keith Short Reviewed-by: Vijay P Hiremath --- common/usbc/tbt_alt_mode.c | 46 ++++++++++++++++------------------------------ 1 file changed, 16 insertions(+), 30 deletions(-) diff --git a/common/usbc/tbt_alt_mode.c b/common/usbc/tbt_alt_mode.c index a7640fcfe6..bd14b7669d 100644 --- a/common/usbc/tbt_alt_mode.c +++ b/common/usbc/tbt_alt_mode.c @@ -192,8 +192,8 @@ static bool tbt_sop_prime_prime_needed(int port) const struct pd_discovery *disc; disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); - if (disc->identity.product_t1.a_rev20.sop_p_p && - !tbt_is_lrd_active_cable(port)) + if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE && + disc->identity.product_t1.a_rev20.sop_p_p) return true; return false; } @@ -214,11 +214,9 @@ void tbt_exit_mode_request(int port) * with Thunderbolt mode for SOP prime. Hence, on request to * exit, only exit Thunderbolt mode SOP prime */ - tbt_state[port] = - /* TODO: replace with tbt_sop_prime_prime_needed */ - tbt_is_lrd_active_cable(port) ? - TBT_EXIT_SOP_PRIME : - TBT_EXIT_SOP_PRIME_PRIME; + tbt_state[port] = tbt_sop_prime_prime_needed(port) ? + TBT_EXIT_SOP_PRIME_PRIME : + TBT_EXIT_SOP_PRIME; } } @@ -253,19 +251,6 @@ static void tbt_retry_enter_mode(int port) TBT_SET_FLAG(port, TBT_FLAG_RETRY_DONE); } -/* Send Exit Mode to SOP''(if supported), or SOP' */ -static void tbt_active_cable_exit_mode(int port) -{ - const struct pd_discovery *disc; - - disc = pd_get_am_discovery(port, TCPCI_MSG_SOP_PRIME); - - if (disc->identity.product_t1.a_rev20.sop_p_p) - tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME; - else - tbt_state[port] = TBT_EXIT_SOP_PRIME; -} - bool tbt_cable_entry_required_for_usb4(int port) { const struct pd_discovery *disc_sop_prime; @@ -337,13 +322,11 @@ void intel_vdm_acked(int port, enum tcpci_msg_type type, int vdo_count, if (opos_sop > 0) pd_dfp_exit_mode(port, TCPCI_MSG_SOP, USB_VID_INTEL, opos_sop); - /* - * TODO: - * Replace with tbt_sop_prime_prime_needed() and - * tbt_sop_prime_prime_needed(). - */ - if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) { - tbt_active_cable_exit_mode(port); + + if (tbt_sop_prime_prime_needed(port)) { + tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME; + } else if (tbt_sop_prime_needed(port)) { + tbt_state[port] = TBT_EXIT_SOP_PRIME; } else { set_usb_mux_with_current_data_role(port); if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) @@ -411,9 +394,12 @@ void intel_vdm_naked(int port, enum tcpci_msg_type type, uint8_t vdm_cmd) case TBT_EXIT_SOP: /* Exit SOP got NAK'ed */ tbt_prints("exit mode SOP failed", port); - if (get_usb_pd_cable_type(port) == IDH_PTYPE_ACABLE) - tbt_active_cable_exit_mode(port); - else { + + if (tbt_sop_prime_prime_needed(port)) { + tbt_state[port] = TBT_EXIT_SOP_PRIME_PRIME; + } else if (tbt_sop_prime_needed(port)) { + tbt_state[port] = TBT_EXIT_SOP_PRIME; + } else { set_usb_mux_with_current_data_role(port); if (TBT_CHK_FLAG(port, TBT_FLAG_RETRY_DONE)) /* Retried enter mode, still failed, give up */ -- cgit v1.2.1 From 249ddf4fc34d5b3cfd849f93d31da86e1ed4caee Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 15 Jul 2022 10:01:04 -0700 Subject: board/garg: Free up more flash space Before: RO: 192 bytes in flash and 30848 bytes in RAM still available RW: 284 bytes in flash and 30848 bytes in RAM still available After: RO: 736 bytes in flash and 30880 bytes in RAM still available RW: 860 bytes in flash and 30880 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I0d940ab2124f657f8b70c7d96f7dd24bf67622c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765446 Reviewed-by: Diana Z --- board/garg/board.h | 1 + 1 file changed, 1 insertion(+) diff --git a/board/garg/board.h b/board/garg/board.h index e35baef6c8..b7ded81827 100644 --- a/board/garg/board.h +++ b/board/garg/board.h @@ -10,6 +10,7 @@ /* Free up flash space */ #define CONFIG_LTO +#undef CONFIG_CMD_BATTFAKE /* Select Baseboard features */ #define VARIANT_OCTOPUS_EC_NPCX796FB -- cgit v1.2.1 From fa0c23cc9be08fdb6b7d11d0ca6c19621fb37816 Mon Sep 17 00:00:00 2001 From: Tim Van Patten Date: Thu, 14 Jul 2022 12:12:10 -0600 Subject: Skyrim: Remove guybrush support Skyrim hardware is available now, so remove guybrush as a skyrim "variant". BUG=b:231996904 TEST=emerge-skyrim chromeos-zephyr TEST=zmake build skyrim BRANCH=None Signed-off-by: Tim Van Patten Change-Id: I3da3b7a8b67664f3e076a90c570c74302b22d528 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765445 Reviewed-by: Diana Z --- zephyr/projects/skyrim/BUILD.py | 3 - zephyr/projects/skyrim/CMakeLists.txt | 5 +- zephyr/projects/skyrim/Kconfig | 6 - zephyr/projects/skyrim/guybrush.dts | 198 -------- zephyr/projects/skyrim/power_signals_guybrush.c | 127 ----- zephyr/projects/skyrim/prj_guybrush.conf | 9 - zephyr/projects/skyrim/usbc_config_guybrush.c | 599 ------------------------ 7 files changed, 1 insertion(+), 946 deletions(-) delete mode 100644 zephyr/projects/skyrim/guybrush.dts delete mode 100644 zephyr/projects/skyrim/power_signals_guybrush.c delete mode 100644 zephyr/projects/skyrim/prj_guybrush.conf delete mode 100644 zephyr/projects/skyrim/usbc_config_guybrush.c diff --git a/zephyr/projects/skyrim/BUILD.py b/zephyr/projects/skyrim/BUILD.py index 3d43b3676b..a8b2da3716 100644 --- a/zephyr/projects/skyrim/BUILD.py +++ b/zephyr/projects/skyrim/BUILD.py @@ -33,6 +33,3 @@ def register_variant(project_name): register_variant(project_name="skyrim") - -# TODO: Deprecate guybrush build after skyrim hardware is readily available. -# register_variant(project_name="guybrush") diff --git a/zephyr/projects/skyrim/CMakeLists.txt b/zephyr/projects/skyrim/CMakeLists.txt index 54039ecab8..b1573a81ab 100644 --- a/zephyr/projects/skyrim/CMakeLists.txt +++ b/zephyr/projects/skyrim/CMakeLists.txt @@ -5,16 +5,13 @@ cmake_minimum_required(VERSION 3.13.1) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(guybrush) +project(skyrim) cros_ec_library_include_directories_ifdef(CONFIG_BOARD_SKYRIM include) -cros_ec_library_include_directories_ifdef(CONFIG_BOARD_GUYBRUSH include_guybrush) zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "power_signals.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "power_signals_guybrush.c") zephyr_library_sources_ifdef(CONFIG_BOARD_SKYRIM "usbc_config.c") -zephyr_library_sources_ifdef(CONFIG_BOARD_GUYBRUSH "usbc_config_guybrush.c") zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC "usb_pd_policy.c") diff --git a/zephyr/projects/skyrim/Kconfig b/zephyr/projects/skyrim/Kconfig index ea68baf71b..6da27ee2d0 100644 --- a/zephyr/projects/skyrim/Kconfig +++ b/zephyr/projects/skyrim/Kconfig @@ -2,12 +2,6 @@ # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. -config BOARD_GUYBRUSH - bool "Google Guybrush Board" - help - Build Google Guybrush reference board. This board build is a - prototype rather than a releasing product. - config BOARD_SKYRIM bool "Google Skyrim Board" help diff --git a/zephyr/projects/skyrim/guybrush.dts b/zephyr/projects/skyrim/guybrush.dts deleted file mode 100644 index 6c5c72d061..0000000000 --- a/zephyr/projects/skyrim/guybrush.dts +++ /dev/null @@ -1,198 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/ { - aliases { - gpio-wp = &gpio_wp; - gpio-kbd-kso2 = &gpio_ec_kso_02_inv; - }; - - named-gpios { - /* Guybrush-specific GPIO customizations */ - gpio_wp: ec_wp_l { - gpios = <&gpio5 0 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; - }; - gpio_ec_pwr_btn_odl: ec_pwr_btn_odl { - gpios = <&gpio0 1 GPIO_INPUT>; - }; - gpio_slp_s3_s0i3_l: slp_s3_s0i3_l { - gpios = <&gpio7 4 GPIO_INPUT>; - enum-name = "GPIO_PCH_SLP_S0_L"; - }; - gpio_ec_pcore_int_odl: ec_pcore_int_odl { - gpios = <&gpiof 0 GPIO_INPUT_PULL_UP>; - }; - gpio_pg_groupc_s0_od: pg_groupc_s0_od { - gpios = <&gpioa 3 GPIO_INPUT>; - }; - gpio_pg_lpddr4x_s3_od: pg_lpddr4x_s3_od { - gpios = <&gpio9 5 GPIO_INPUT>; - }; - ec_soc_pwr_good { - gpios = <&gpiod 3 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_PCH_SYS_PWROK"; - }; - ec_entering_rw { - gpios = <&gpio6 6 GPIO_OUTPUT_LOW>; - enum-name = "GPIO_ENTERING_RW"; - }; - ec_clr_cmos { - gpios = <&gpioa 1 GPIO_OUTPUT_LOW>; - }; - ec_mem_event { - gpios = <&gpioa 5 GPIO_OUTPUT_LOW>; - }; - gpio_ec_soc_pwr_btn_l: ec_soc_pwr_btn_l { - gpios = <&gpio6 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_PCH_PWRBTN_L"; - }; - ec_soc_int_l { - gpios = <&gpio8 3 GPIO_OUTPUT_HIGH>; - enum-name = "GPIO_EC_INT_L"; - }; - soc_thermtrip_odl { - gpios = <&gpioe 5 GPIO_INPUT>; - }; - gpio_usb_c0_c1_fault_odl: usb_c0_c1_fault_odl { - gpios = <&gpio7 3 GPIO_ODR_HIGH>; - }; - 3axis_int_l { - gpios = <&gpioa 2 GPIO_INPUT_PULL_DOWN>; - }; - gpio_voldn_btn_odl: voldn_btn_odl { - gpios = <&gpioa 7 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_DOWN_L"; - }; - gpio_volup_btn_odl: volup_btn_odl { - gpios = <&gpio9 3 GPIO_INPUT_PULL_UP>; - enum-name = "GPIO_VOLUME_UP_L"; - }; - ec_ps2_clk { - gpios = <&gpio6 7 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_dat { - gpios = <&gpio7 0 GPIO_INPUT_PULL_UP>; - }; - ec_ps2_rst { - gpios = <&gpio6 2 GPIO_INPUT_PULL_UP>; - }; - ec_gpiob0 { - gpios = <&gpiob 0 GPIO_INPUT_PULL_UP>; - }; - ec_gpio81 { - gpios = <&gpio8 1 GPIO_INPUT_PULL_UP>; - }; - ec_psl_gpo { - gpios = <&gpiod 7 GPIO_INPUT_PULL_UP>; - }; - ec_pwm7 { - gpios = <&gpio6 0 GPIO_INPUT_PULL_UP>; - }; - gpio_accel_gyro_int_l: accel_gyro_int_l { - gpios = <&gpioa 0 GPIO_INPUT_PULL_UP>; - }; - }; - - def-lvol-io-list { - compatible = "nuvoton,npcx-lvolctrl-def"; - - /* Low voltage on I2C6_1 */ - lvol-io-pads = <&lvol_ioe4 &lvol_ioe3>; - }; - - named-adc-channels { - compatible = "named-adc-channels"; - - adc_temp_soc: temp-soc { - label = "SOC"; - enum-name = "ADC_TEMP_SENSOR_SOC"; - io-channels = <&adc0 0>; - }; - }; - - named-temp-sensors { - soc-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "SOC"; - enum-name = "TEMP_SENSOR_SOC"; - tmp112-name = "TMP112_SOC"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS0"; - temp_host_high = <100>; - temp_host_halt = <105>; - temp_host_release_high = <80>; - temp_fan_off = <0>; - temp_fan_max = <70>; - }; - amb-tmp112 { - compatible = "cros-ec,temp-sensor-tmp112", - "cros-ec,temp-sensor"; - label = "Ambient"; - enum-name = "TEMP_SENSOR_AMB"; - tmp112-name = "TMP112_AMB"; - port = <&i2c_sensor>; - i2c-addr-flags = "TMP112_I2C_ADDR_FLAGS1"; - }; - }; - - gpio-interrupts { - compatible = "cros-ec,gpio-interrupts"; - - int_pg_lpddr4x_s3: pg_lpddr4x_s3 { - irq-pin = <&gpio_pg_lpddr4x_s3_od>; - flags = ; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_slp_s3_s0i3: slp_s3_s0i3 { - irq-pin = <&gpio_slp_s3_s0i3_l>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_ec_pwr_btn: ec_pwr_btn { - irq-pin = <&gpio_ec_pwr_btn_odl>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_ec_pcore: ec_pcore { - irq-pin = <&gpio_ec_pcore_int_odl>; - flags = ; - handler = "power_signal_interrupt"; - }; - int_pg_groupc_s0: pg_groupc_s0 { - irq-pin = <&gpio_pg_groupc_s0_od>; - flags = ; - handler = "baseboard_en_pwr_pcore_s0"; - }; - int_s0_pgood: s0_pgood { - irq-pin = <&gpio_s0_pgood>; - flags = ; - handler = "power_signal_interrupt"; - }; - }; - - /* Rotation matrices for motion sensors. */ - motionsense-rotation-ref { - compatible = "cros-ec,motionsense-rotation-ref"; - lid_rot_ref: lid-rotation-ref { - mat33 = <0 (-1) 0 - (-1) 0 0 - 0 0 (-1)>; - }; - - base_rot_ref: base-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 - 0 0 (-1)>; - }; - }; -}; - -/* host interface */ -&espi0 { - status = "okay"; - pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; - pinctrl-names = "default"; -}; diff --git a/zephyr/projects/skyrim/power_signals_guybrush.c b/zephyr/projects/skyrim/power_signals_guybrush.c deleted file mode 100644 index ba9eb1a92f..0000000000 --- a/zephyr/projects/skyrim/power_signals_guybrush.c +++ /dev/null @@ -1,127 +0,0 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include - -#include "chipset.h" -#include "config.h" -#include "gpio_signal.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "power.h" -#include "timer.h" - -/* Wake Sources */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const enum gpio_signal hibernate_wake_pins[] = { - GPIO_LID_OPEN, - GPIO_AC_PRESENT, - GPIO_POWER_BUTTON_L, -}; -const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); - -/* Power Signal Input List */ -/* TODO: b/218904113: Convert to using Zephyr GPIOs */ -const struct power_signal_info power_signal_list[] = { - [X86_SLP_S0_N] = { - .gpio = GPIO_PCH_SLP_S0_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S0_DEASSERTED", - }, - [X86_SLP_S3_N] = { - .gpio = GPIO_PCH_SLP_S3_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S3_DEASSERTED", - }, - [X86_SLP_S5_N] = { - .gpio = GPIO_PCH_SLP_S5_L, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "SLP_S5_DEASSERTED", - }, - [X86_S0_PGOOD] = { - .gpio = GPIO_S0_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S0_PGOOD", - }, - [X86_S5_PGOOD] = { - .gpio = GPIO_S5_PGOOD, - .flags = POWER_SIGNAL_ACTIVE_HIGH, - .name = "S5_PGOOD", - }, -}; -BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); - -static void baseboard_interrupt_init(void) -{ - /* Enable Power Group interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr4x_s3)); -} -DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_POST_I2C); - -/** - * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting - * PCH_PWRBTN_L. - */ -void board_pwrbtn_to_pch(int level) -{ - timestamp_t start; - const uint32_t timeout_rsmrst_rise_us = 30 * MSEC; - - /* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */ - if (!level && - !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) { - start = get_time(); - do { - usleep(200); - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_ec_soc_rsmrst_l))) - break; - } while (time_since32(start) < timeout_rsmrst_rise_us); - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) - ccprints("Error pwrbtn: RSMRST_L still low"); - - msleep(16); - } - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_btn_l), level); -} - -void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) -{ - /* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */ - gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_en_pwr_pcore_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_pg_lpddr4x_s3_od)) && - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_pg_groupc_s0_od))); -} - -void baseboard_en_pwr_s0(enum gpio_signal signal) -{ - /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0_r), - gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) && - gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5))); - - /* Now chain off to the normal power signal interrupt handler. */ - power_signal_interrupt(signal); -} - -void baseboard_s5_pgood(enum gpio_signal signal) -{ - baseboard_en_pwr_s0(signal); -} - -void baseboard_set_en_pwr_s3(enum gpio_signal signal) -{ - /* EC has no EN_PWR_S3 on this board */ - - /* Chain off the normal power signal interrupt handler */ - power_signal_interrupt(signal); -} diff --git a/zephyr/projects/skyrim/prj_guybrush.conf b/zephyr/projects/skyrim/prj_guybrush.conf deleted file mode 100644 index 0ca57174a4..0000000000 --- a/zephyr/projects/skyrim/prj_guybrush.conf +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. - -# Guybrush board-specific Kconfig settings. -CONFIG_BOARD_GUYBRUSH=y - -# Only Guybrush has TMP112 -CONFIG_PLATFORM_EC_TEMP_SENSOR_TMP112=y \ No newline at end of file diff --git a/zephyr/projects/skyrim/usbc_config_guybrush.c b/zephyr/projects/skyrim/usbc_config_guybrush.c deleted file mode 100644 index ef9a47e52c..0000000000 --- a/zephyr/projects/skyrim/usbc_config_guybrush.c +++ /dev/null @@ -1,599 +0,0 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Guybrush family-specific USB-C configuration */ - -#include "cros_board_info.h" -#include "battery_fuel_gauge.h" -#include "charge_manager.h" -#include "charge_ramp.h" -#include "charge_state_v2.h" -#include "charge_state.h" -#include "charger.h" -#include "driver/bc12/pi3usb9201.h" -#include "driver/charger/isl9241.h" -#include "driver/ppc/aoz1380.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/retimer/anx7491.h" -#include "driver/retimer/ps8811.h" -#include "driver/retimer/ps8818.h" -#include "driver/tcpm/nct38xx.h" -#include "driver/usb_mux/anx7451.h" -#include "driver/usb_mux/amd_fp6.h" -#include "gpio.h" -#include "gpio/gpio_int.h" -#include "hooks.h" -#include "ioexpander.h" -#include "power.h" -#include "usb_mux.h" -#include "usb_pd_tcpm.h" -#include "usbc_ppc.h" - -#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args) -#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args) - -/* USB-A ports */ -enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT }; - -/* USB-C ports */ -enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT }; -BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT); - -static void reset_nct38xx_port(int port); - -static void usbc_interrupt_init(void) -{ - /* Enable PPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc)); - - /* Enable TCPC interrupts. */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_tcpc)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_tcpc)); - - /* Enable BC 1.2 interrupts */ - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_bc12)); - gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_bc12)); - - /* TODO: Enable SBU fault interrupts (io expander )*/ -} -DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C); - -struct ppc_config_t ppc_chips[] = { - [USBC_PORT_C0] = { - /* Device does not talk I2C */ - .drv = &aoz1380_drv - }, - - [USBC_PORT_C1] = { - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = NX20P3483_ADDR1_FLAGS, - .drv = &nx20p348x_drv - }, -}; -BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT); -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - -/* - * .init is not necessary here because it has nothing - * to do. Primary mux will handle mux state so .get is - * not needed as well. usb_mux.c can handle the situation - * properly. - */ -static int fsusb42umx_set_mux(const struct usb_mux *, mux_state_t, bool *); -struct usb_mux_driver usbc0_sbu_mux_driver = { - .set = fsusb42umx_set_mux, -}; - -/* - * Since FSUSB42UMX is not a i2c device, .i2c_port and - * .i2c_addr_flags are not required here. - */ -struct usb_mux usbc0_sbu_mux = { - .usb_port = USBC_PORT_C0, - .driver = &usbc0_sbu_mux_driver, -}; - -__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: PS8818 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_ps8818 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = PS8818_I2C_ADDR_FLAGS, - .driver = &ps8818_usb_retimer_driver, - .board_set = &board_c1_ps8818_mux_set, -}; - -/* - * ANX7491(A1) and ANX7451(C1) are on the same i2c bus. Both default - * to 0x29 for the USB i2c address. This moves ANX7451(C1) USB i2c - * address to 0x2A. ANX7491(A1) will stay at the default 0x29. - */ -uint16_t board_anx7451_get_usb_i2c_addr(const struct usb_mux *me) -{ - ASSERT(me->usb_port == USBC_PORT_C1); - return 0x2a; -} - -__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me, - mux_state_t mux_state) -{ - CPRINTSUSB("C1: ANX7451 mux using default tuning"); - return 0; -} - -struct usb_mux usbc1_anx7451 = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_TCPC1, - .flags = USB_MUX_FLAG_RESETS_IN_G3, - .i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS, - .driver = &anx7451_usb_mux_driver, - .board_set = &board_c1_anx7451_mux_set, -}; - -struct usb_mux usb_muxes[] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - .next_mux = &usbc0_sbu_mux, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_MUX, - .i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR, - .driver = &amd_fp6_usb_mux_driver, - /* .next_mux = filled in by setup_mux based on fw_config */ - } -}; -BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT); - -/* - * USB C0 port SBU mux use standalone FSUSB42UMX - * chip and it needs a board specific driver. - * Overall, it will use chained mux framework. - */ -static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state, - bool *ack_required) -{ - /* This driver does not use host command ACKs */ - *ack_required = false; - - if (mux_state & USB_PD_MUX_POLARITY_INVERTED) - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1); - else - ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0); - - return EC_SUCCESS; -} - -static void setup_mux(void) -{ - /* TODO: Fill in C1 mux based on CBI */ - CPRINTSUSB("C1: Setting ANX7451 mux"); - usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451; -} -DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C); - -int board_set_active_charge_port(int port) -{ - int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); - int i; - int rv; - - if (port == CHARGE_PORT_NONE) { - CPRINTSUSB("Disabling all charger ports"); - - /* Disable all ports. */ - for (i = 0; i < ppc_cnt; i++) { - /* - * If this port had booted in dead battery mode, go - * ahead and reset it so EN_SNK responds properly. - */ - if (nct38xx_get_boot_type(i) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } - - /* - * Do not return early if one fails otherwise we can - * get into a boot loop assertion failure. - */ - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("Disabling C%d as sink failed.", i); - } - - return EC_SUCCESS; - } else if (!is_valid_port) { - return EC_ERROR_INVAL; - } - - /* - * Check if we can reset any ports in dead battery mode - * - * The NCT3807 may continue to keep EN_SNK low on the dead battery port - * and allow a dangerous level of voltage to pass through to the initial - * charge port (see b/183660105). We must reset the ports if we have - * sufficient battery to do so, which will bring EN_SNK back under - * normal control. - */ - rv = EC_SUCCESS; - for (i = 0; i < board_get_usb_pd_port_count(); i++) { - if (nct38xx_get_boot_type(i) == NCT38XX_BOOT_DEAD_BATTERY) { - CPRINTSUSB("Found dead battery on %d", i); - /* - * If we have battery, get this port reset ASAP. - * This means temporarily rejecting charge manager - * sets to it. - */ - if (pd_is_battery_capable()) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - - if (port == i) - rv = EC_ERROR_INVAL; - } else if (port != i) { - /* - * If other port is selected and in dead battery - * mode, reset this port. Otherwise, reject - * change because we'll brown out. - */ - if (nct38xx_get_boot_type(port) == - NCT38XX_BOOT_DEAD_BATTERY) { - reset_nct38xx_port(i); - pd_set_error_recovery(i); - } else { - rv = EC_ERROR_INVAL; - } - } - } - } - - if (rv != EC_SUCCESS) - return rv; - - /* Check if the port is sourcing VBUS. */ - if (tcpm_get_src_ctrl(port)) { - CPRINTSUSB("Skip enable C%d", port); - return EC_ERROR_INVAL; - } - - CPRINTSUSB("New charge port: C%d", port); - - /* - * Turn off the other ports' sink path FETs, before enabling the - * requested charge port. - */ - for (i = 0; i < ppc_cnt; i++) { - if (i == port) - continue; - - if (ppc_vbus_sink_enable(i, 0)) - CPRINTSUSB("C%d: sink path disable failed.", i); - } - - /* Enable requested charge port. */ - if (ppc_vbus_sink_enable(port, 1)) { - CPRINTSUSB("C%d: sink path enable failed.", port); - return EC_ERROR_UNKNOWN; - } - - return EC_SUCCESS; -} - -/* - * In the AOZ1380 PPC, there are no programmable features. We use - * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0 - * current limits. - */ -int board_aoz1380_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) -{ - int rv = EC_SUCCESS; - - rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN, - (rp == TYPEC_RP_3A0) ? 1 : 0); - - return rv; -} - -void board_set_charge_limit(int port, int supplier, int charge_ma, int max_ma, - int charge_mv) -{ - charge_set_input_current_limit( - MAX(charge_ma, CONFIG_CHARGER_INPUT_CURRENT), charge_mv); -} - -/* TODO: sbu_fault_interrupt from io expander */ - -/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */ -#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328 -static void set_ac_prochot(void) -{ - isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA); -} -DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT); - -void tcpc_alert_event(enum gpio_signal signal) -{ - int port; - - switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: - port = 0; - break; - case GPIO_USB_C1_TCPC_INT_ODL: - port = 1; - break; - default: - return; - } - - schedule_deferred_pd_interrupt(port); -} - -static void reset_nct38xx_port(int port) -{ - const struct gpio_dt_spec *reset_gpio_l; - - /* TODO: Save and restore ioex signals */ - if (port == USBC_PORT_C0) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_rst_l); - else if (port == USBC_PORT_C1) - reset_gpio_l = GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_rst_l); - else - /* Invalid port: do nothing */ - return; - - gpio_pin_set_dt(reset_gpio_l, 0); - msleep(NCT38XX_RESET_HOLD_DELAY_MS); - gpio_pin_set_dt(reset_gpio_l, 1); - nct38xx_reset_notify(port); - if (NCT3807_RESET_POST_DELAY_MS != 0) - msleep(NCT3807_RESET_POST_DELAY_MS); -} - -void board_reset_pd_mcu(void) -{ - /* Reset TCPC0 */ - reset_nct38xx_port(USBC_PORT_C0); - - /* Reset TCPC1 */ - reset_nct38xx_port(USBC_PORT_C1); -} - -uint16_t tcpc_get_alert_status(void) -{ - uint16_t status = 0; - - /* - * Check which port has the ALERT line set and ignore if that TCPC has - * its reset line active. - */ - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_tcpc_int_odl))) { - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_usb_c0_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_0; - } - - if (!gpio_pin_get_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c1_tcpc_int_odl))) { - if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL( - gpio_usb_c1_tcpc_rst_l)) != 0) - status |= PD_STATUS_TCPC_ALERT_1; - } - - return status; -} - -void ppc_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_PPC_INT_ODL: - aoz1380_interrupt(USBC_PORT_C0); - break; - - case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); - break; - - default: - break; - } -} - -void bc12_interrupt(enum gpio_signal signal) -{ - switch (signal) { - case GPIO_USB_C0_BC12_INT_ODL: - usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); - break; - - case GPIO_USB_C1_BC12_INT_ODL: - usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); - break; - - default: - break; - } -} - -/** - * Return if VBUS is sagging too low - * - * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current - * until voltage drops to 4.5V. Don't go lower than this to be kind to the - * charger (see b/67964166). - */ -#define BC12_MIN_VOLTAGE 4500 -int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state) -{ - int voltage = 0; - int rv; - - rv = charger_get_vbus_voltage(port, &voltage); - - if (rv) { - CPRINTSUSB("%s rv=%d", __func__, rv); - return 0; - } - - /* - * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown - * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0. - * This partly defeats the point of ramping, but will still catch - * VBUS below 4.5V and above 0V. - */ - if (voltage == 0) { - CPRINTSUSB("%s vbus=0", __func__); - return 0; - } - - if (voltage < BC12_MIN_VOLTAGE) - CPRINTSUSB("%s vbus=%d", __func__, voltage); - - return voltage < BC12_MIN_VOLTAGE; -} - -#define SAFE_RESET_VBUS_DELAY_MS 900 -#define SAFE_RESET_VBUS_MV 5000 -void board_hibernate(void) -{ - int port; - enum ec_error_list ret; - - /* - * If we are charging, then drop the Vbus level down to 5V to ensure - * that we don't get locked out of the 6.8V OVLO for our PPCs in - * dead-battery mode. This is needed when the TCPC/PPC rails go away. - * (b/79218851, b/143778351, b/147007265) - */ - port = charge_manager_get_active_charge_port(); - if (port != CHARGE_PORT_NONE) { - pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); - - /* Give PD task and PPC chip time to get to 5V */ - msleep(SAFE_RESET_VBUS_DELAY_MS); - } - - /* Try to put our battery fuel gauge into sleep mode */ - ret = battery_sleep_fuel_gauge(); - if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED)) - cprints(CC_SYSTEM, "Failed to send battery sleep command"); -} - -__overridable enum ec_error_list -board_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = ps8811_i2c_read(me, PS8811_REG_PAGE1, - PS8811_REG1_USB_BEQ_LEVEL, &val); - } while (rv && --tries); - - if (rv) { - CPRINTSUSB("A1: PS8811 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: PS8811 retimer detected"); - rv = board_a1_ps8811_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv); - return rv; -} - -/* - * PS8811 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_ps8811 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3, - .board_init = &baseboard_a1_ps8811_retimer_init, -}; - -__overridable enum ec_error_list -board_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - return EC_SUCCESS; -} - -static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me) -{ - int rv; - int tries = 2; - - do { - int val; - - rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val); - } while (rv && --tries); - if (rv) { - CPRINTSUSB("A1: ANX7491 retimer not detected!"); - return rv; - } - CPRINTSUSB("A1: ANX7491 retimer detected"); - rv = board_a1_anx7491_retimer_init(me); - if (rv) - CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv); - return rv; -} - -/* - * ANX7491 is just a type-A USB retimer, reusing mux structure for - * convenience. - */ -const struct usb_mux usba1_anx7491 = { - .usb_port = USBA_PORT_A1, - .i2c_port = I2C_PORT_TCPC1, - .i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS, - .board_init = &baseboard_a1_anx7491_retimer_init, -}; - -void baseboard_a1_retimer_setup(void) -{ - struct usb_mux a1_retimer; - - /* TODO: Support PS8811 retimer through CBI */ - a1_retimer = usba1_anx7491; - a1_retimer.board_init(&a1_retimer); -} -DECLARE_DEFERRED(baseboard_a1_retimer_setup); - -/* TODO: Remove when guybrush is no longer supported */ -#ifdef CONFIG_BOARD_GUYBRUSH -void board_overcurrent_event(int port, int is_overcurrented) -{ - switch (port) { - case USBC_PORT_C0: - case USBC_PORT_C1: - gpio_pin_set_dt( - GPIO_DT_FROM_NODELABEL(gpio_usb_c0_c1_fault_odl), - !is_overcurrented); - break; - - default: - break; - } -} -#endif -- cgit v1.2.1 From b680d4103a842eb1d92b0ba1a7f6a7362b3c9a6c Mon Sep 17 00:00:00 2001 From: Li Feng Date: Tue, 24 May 2022 22:42:10 -0700 Subject: retimer: firmware update retry online This CL implements error recovery for case as below. In NDA ports retimer firmware update, when NVM is updated and issued authentication, retimer takes about 5 seconds to come back. After this, host can bring the port online. Online means EC disconnects the USB mux and resumes PD port. If user requests EC to put port online without waiting 5 seconds, The operation will fail. The PD port couldn't get out of suspended state. It's disabled. This CL adds a deferred call to check if PD port is online successfully; if not, retry online again to enable the PD port. Also if the port is requested to be online but not resumed yet, except RESUME_PD, no other host requests will be allowed. As soon as port is resumed, the port can accept requestes again. BUG=b:212235056 b:211790542 BRANCH=none TEST=On Redrix NDA PD port, echo 1 > offline update NVM and authenticate; not waiting 5 seconds. echo 0 > offline The port failed to be online, after delay, deferred call is triggered. Online is tried again; port is enabled. Signed-off-by: Li Feng Change-Id: I7ec96a4dfb81e8ed2422e459a098defa4c8acf92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3666378 Commit-Queue: Keith Short Reviewed-by: Keith Short --- common/usbc/usb_retimer_fw_update.c | 166 +++++++++++++++++++++++++++++++++--- 1 file changed, 152 insertions(+), 14 deletions(-) diff --git a/common/usbc/usb_retimer_fw_update.c b/common/usbc/usb_retimer_fw_update.c index 1b8c2c288b..a70ba18a11 100644 --- a/common/usbc/usb_retimer_fw_update.c +++ b/common/usbc/usb_retimer_fw_update.c @@ -22,6 +22,12 @@ #endif /* + * Update retimer firmware of no device attached (NDA) ports + * + * https://docs.kernel.org/admin-guide/thunderbolt.html# + * upgrading-on-board-retimer-nvm-when-there-is-no-cable-connected + * + * On EC side: * Retimer firmware update is initiated by AP. * The operations requested by AP are: * 0 - USB_RETIMER_FW_UPDATE_QUERY_PORT @@ -43,18 +49,60 @@ * If 4/5/6/7 is received, TC_FLAGS_USB_RETIMER_FW_UPDATE_LTD_RUN is * set, PD task should be in suspended mode and process it. * + * On host side: + * 1. Put NDA ports into offline mode. + * This forces retimer to power on, and requests EC to suspend + * PD port, set USB mux to USB, Safe then TBT. + * 2. Scan for retimers + * 3. Update retimer NVM firmware. + * 4. Authenticate. + * 5. Wait 5 or more seconds for retimer to come back. + * 6. Put NDA ports into online mode -- the functional state. + * This requestes EC to disconnect(set USB mux to 0), resume PD port. + * + * Error recovery: + * As mentioned above, to put port online, host sends two requests to EC + * 1. Disconnect USB MUX: USB_RETIMER_FW_UPDATE_DISCONNECT + * if step 1 is successful, then + * 2. Resume PD port: USB_RETIMER_FW_UPDATE_RESUME_PD + * + * If step 1 fails, host will not send step 2. This means no + * resume request from host. PD port stays in suspended state. + * EC needs an error recovery to resume PD port by itself. + * + * Below is how error recovery works: + * PD port state is set to RETIMER_ONLINE_REQUESTED when receives + * "Disconnect USB MUX"; a deferred call is set up too. When EC resumes + * port upon host's request, port state will be set to RETIMER_ONLINE; + * or port state stays RETIMER_ONLINE_REQUESTED if host doesn't request. + * By the time the deferrred call is fired, it will check if any port is + * still in RETIMER_ONLINE_REQUESTED state. If true, EC will put the + * port online by itself. That is, retry disconnect and unconditionally + * resume the port. */ #define SUSPEND 1 #define RESUME 0 +enum retimer_port_state { + RETIMER_ONLINE, + RETIMER_OFFLINE, + RETIMER_ONLINE_REQUESTED +}; + +/* + * Two seconds buffer is added on top of required 5 seconds; + * to cover the time to disconnect and resume. + */ +#define RETIMTER_ONLINE_DELAY (7 * SECOND) + /* Track current port AP requested to update retimer firmware */ static int cur_port; static int last_op; /* Operation received from AP via ACPI_WRITE */ /* Operation result returned to ACPI_READ */ static int last_result; /* Track port state: SUSPEND or RESUME */ -static int port_state[CONFIG_USB_PD_PORT_MAX_COUNT]; +static enum retimer_port_state port_state[CONFIG_USB_PD_PORT_MAX_COUNT]; int usb_retimer_fw_update_get_result(void) { @@ -87,12 +135,13 @@ int usb_retimer_fw_update_get_result(void) return result; } -static void retimer_fw_update_set_port_state(int port, int state) +static void retimer_fw_update_set_port_state(int port, + enum retimer_port_state state) { port_state[port] = state; } -static int retimer_fw_update_get_port_state(int port) +static enum retimer_port_state retimer_fw_update_get_port_state(int port) { return port_state[port]; } @@ -101,16 +150,16 @@ static int retimer_fw_update_get_port_state(int port) * @brief Suspend or resume PD task and update the state of the port. * * @param port PD port - * @param state - * SUSPEND: suspend PD task for firmware update; and set state to SUSPEND - * RESUME: resume PD task after firmware update is done; and set state - * to RESUME. + * @param suspend + * SUSPEND: suspend PD task; set state to RETIMER_OFFLINE + * RESUME: resume PD task; set state to RETIMER_ONLINE. * */ -static void retimer_fw_update_port_handler(int port, int state) +static void retimer_fw_update_port_handler(int port, bool suspend) { - pd_set_suspend(port, state); - retimer_fw_update_set_port_state(port, state); + pd_set_suspend(port, suspend); + retimer_fw_update_set_port_state( + port, suspend == SUSPEND ? RETIMER_OFFLINE : RETIMER_ONLINE); } static void deferred_pd_suspend(void) @@ -124,14 +173,74 @@ static inline mux_state_t retimer_fw_update_usb_mux_get(int port) return usb_mux_get(port) & USB_RETIMER_FW_UPDATE_MUX_MASK; } +/* + * Host will wait maximum 300ms for result; otherwise it's error. + * so the polling takes 300ms too. + */ +#define POLLING_CYCLE 15 +#define POLLING_TIME_MS 20 + +static bool query_usb_mux_set_completed_timeout(int port) +{ + int i; + + for (i = 0; i < POLLING_CYCLE; i++) { + if (!usb_mux_set_completed(port)) + msleep(POLLING_TIME_MS); + else + return false; + } + + return true; +} + +static void retry_online(int port) +{ + usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, + pd_get_polarity(port)); + /* Wait maximum 300 ms for USB mux to be set */ + query_usb_mux_set_completed_timeout(port); + /* Resume the port unconditionally */ + retimer_fw_update_port_handler(port, RESUME); +} + +/* + * After NVM update, if AP skips step 5, not wait 5+ seconds for retimer + * to come back; then do step 6 immediately, requesting EC to put + * retimer online. Step 6 will fail; port is still offline afterwards. + * + * This deferred function monitors if any port has this problem and retry + * online one more time. + */ +static void retimer_check_online(void) +{ + int i; + + for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + if (retimer_fw_update_get_port_state(i) == + RETIMER_ONLINE_REQUESTED) { + /* + * Now the time has passed RETIMTER_ONLINE_DELAY; + * retry online. + * The port is suspended; if the port is not + * suspended, DISCONNECT request won't go through, + * we couldn't be here. + */ + retry_online(i); + /* PD port is resumed */ + } + } +} +DECLARE_DEFERRED(retimer_check_online); + /* Allow mux results to be filled in during HOOKS if needed */ static void last_result_mux_get(void); DECLARE_DEFERRED(last_result_mux_get); static void last_result_mux_get(void) { - if (!usb_mux_set_completed(cur_port)) { - hook_call_deferred(&last_result_mux_get_data, 20 * MSEC); + if (query_usb_mux_set_completed_timeout(cur_port)) { + last_result = USB_RETIMER_FW_UPDATE_ERR; return; } @@ -192,6 +301,14 @@ void usb_retimer_fw_update_process_op_cb(int port) usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_DISCONNECT, pd_get_polarity(port)); result_mux_get = true; + /* + * Host decides to put retimer online; now disconnects USB MUX + * and sets port state to "RETIMER_ONLINE_REQUESTED". + */ + retimer_fw_update_set_port_state(port, + RETIMER_ONLINE_REQUESTED); + hook_call_deferred(&retimer_check_online_data, + RETIMTER_ONLINE_DELAY); break; default: break; @@ -210,12 +327,32 @@ void usb_retimer_fw_update_process_op(int port, int op) ASSERT(port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT); /* - * TODO(b/179220036): check not overlapping requests; - * not change cur_port if retimer scan is in progress + * The order of requests from host are: + * + * Port 0 offline + * Port 0 rescan retimers + * Port 1 offline + * Port 1 rescan retimers + * ... + * Port 0 online + * Port 1 online + * ... */ last_op = op; cur_port = port; + /* + * Host has requested to put this port back online, and haven't + * finished online process. During this period, don't accept any + * requests, except USB_RETIMER_FW_UPDATE_RESUME_PD. + */ + if (port_state[port] == RETIMER_ONLINE_REQUESTED) { + if (op != USB_RETIMER_FW_UPDATE_RESUME_PD) { + last_result = USB_RETIMER_FW_UPDATE_ERR; + return; + } + } + switch (op) { case USB_RETIMER_FW_UPDATE_QUERY_PORT: break; @@ -259,3 +396,4 @@ static void restore_port(void) } } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, restore_port, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_CHIPSET_RESET, restore_port, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From c23d2848ac11829a22bb60533ffc5572de573262 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 15 Jul 2022 12:57:10 -0700 Subject: common/util: Add casts When compiling against the standard library, clang complains: common/util.c:66:6: error: array subscript is of type 'char' [-Werror,-Wchar-subscripts] tolower(*s) == 'f' || tolower(*s) == 'n') { ^~~~~~~~~~~ According to POSIX: The tolower() and tolower_l() functions have as a domain a type int, the value of which is representable as an unsigned char or the value of EOF. If the argument has any other value, the behavior is undefined. https://pubs.opengroup.org/onlinepubs/9699919799/functions/tolower.html BRANCH=none BUG=b:234181908 TEST=make utils-str Signed-off-by: Tom Hughes Change-Id: I84f4bfb647f29b24b1c3bd7f5d222275354c4698 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765458 Reviewed-by: Paul Fagerburg --- common/util.c | 6 ++++-- test/utils.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 2 deletions(-) diff --git a/common/util.c b/common/util.c index c911a83ce9..c89770f161 100644 --- a/common/util.c +++ b/common/util.c @@ -63,14 +63,16 @@ int parse_bool(const char *s, int *dest) { /* off, disable, false, no */ if (!strcasecmp(s, "off") || !strncasecmp(s, "dis", 3) || - tolower(*s) == 'f' || tolower(*s) == 'n') { + tolower((unsigned char)*s) == 'f' || + tolower((unsigned char)*s) == 'n') { *dest = 0; return 1; } /* on, enable, true, yes */ if (!strcasecmp(s, "on") || !strncasecmp(s, "ena", 3) || - tolower(*s) == 't' || tolower(*s) == 'y') { + tolower((unsigned char)*s) == 't' || + tolower((unsigned char)*s) == 'y') { *dest = 1; return 1; } diff --git a/test/utils.c b/test/utils.c index bc78ce8beb..042e3a1ac0 100644 --- a/test/utils.c +++ b/test/utils.c @@ -321,6 +321,64 @@ test_static int test_binary_first_base3_from_bits(void) return EC_SUCCESS; } +test_static int test_parse_bool(void) +{ + int bool_val; + int rv; + + /* False cases. */ + + bool_val = 1; + rv = parse_bool("off", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 0, "%d"); + + bool_val = 1; + rv = parse_bool("dis", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 0, "%d"); + + bool_val = 1; + rv = parse_bool("f", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 0, "%d"); + + bool_val = 1; + rv = parse_bool("n", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 0, "%d"); + + /* True cases. */ + + bool_val = 0; + rv = parse_bool("on", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 1, "%d"); + + bool_val = 0; + rv = parse_bool("ena", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 1, "%d"); + + bool_val = 0; + rv = parse_bool("t", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 1, "%d"); + + bool_val = 0; + rv = parse_bool("y", &bool_val); + TEST_EQ(rv, 1, "%d"); + TEST_EQ(bool_val, 1, "%d"); + + /* Error case. */ + bool_val = -1; + rv = parse_bool("a", &bool_val); + TEST_EQ(rv, 0, "%d"); + TEST_EQ(bool_val, -1, "%d"); + + return EC_SUCCESS; +} + void run_test(int argc, char **argv) { test_reset(); @@ -339,6 +397,7 @@ void run_test(int argc, char **argv) RUN_TEST(test_safe_memcmp); RUN_TEST(test_alignment_log2); RUN_TEST(test_binary_first_base3_from_bits); + RUN_TEST(test_parse_bool); test_print_result(); } -- cgit v1.2.1 From 345d62ebd1084c0df11e74f7036ee6e8b046c72d Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Thu, 30 Jun 2022 14:54:34 -0700 Subject: docs/fingerprint: Update power numbers for latest dartmonkey release BRANCH=none BUG=none TEST=view in gitiles Signed-off-by: Tom Hughes Change-Id: Ibd83afbb767ad90641a95822119c2eee291c5844 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3739315 Reviewed-by: Bobby Casey Reviewed-by: Andrea Grandi --- docs/fingerprint/fingerprint.md | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/docs/fingerprint/fingerprint.md b/docs/fingerprint/fingerprint.md index a17472207d..8d4995a0fa 100644 --- a/docs/fingerprint/fingerprint.md +++ b/docs/fingerprint/fingerprint.md @@ -386,7 +386,7 @@ measure releases before that point. ``` **Firmware Version**: -`dartmonkey_v2.0.2887-311310808-RO_v2.0.7304-441100b93-RW.bin` +`dartmonkey_v2.0.2887-311310808-RO_v2.0.14340-6c1587ca7-RW.bin` #### MCU is idle @@ -396,11 +396,11 @@ measure releases before that point. ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 178 337.13 20.91 404.32 289.82 -@@ pp3300_dx_fp_mv 178 3256.00 0.00 3256.00 3256.00 -@@ pp3300_dx_fp_mw 178 0.00 0.00 0.00 0.00 -@@ pp3300_dx_mcu_mv 178 3248.00 0.00 3248.00 3248.00 -@@ pp3300_dx_mcu_mw 178 45.17 0.09 45.21 44.95 +@@ sample_msecs 523 114.85 18.33 386.55 88.95 +@@ pp3300_dx_fp_mv 523 3256.00 0.00 3256.00 3256.00 +@@ pp3300_dx_fp_mw 523 0.00 0.00 0.00 0.00 +@@ pp3300_dx_mcu_mv 523 3248.00 0.00 3248.00 3248.00 +@@ pp3300_dx_mcu_mw 523 43.86 0.10 43.91 43.65 ``` #### MCU in low power mode (suspend) @@ -411,11 +411,11 @@ measure releases before that point. ``` @@ NAME COUNT AVERAGE STDDEV MAX MIN -@@ sample_msecs 174 345.60 31.93 457.62 283.00 -@@ pp3300_dx_fp_mv 174 3264.00 0.00 3264.00 3264.00 -@@ pp3300_dx_fp_mw 174 0.00 0.00 0.00 0.00 -@@ pp3300_dx_mcu_mv 174 3260.69 3.94 3264.00 3256.00 -@@ pp3300_dx_mcu_mw 174 5.47 0.10 5.48 4.17 +@@ sample_msecs 501 119.79 14.72 381.92 89.22 +@@ pp3300_dx_fp_mv 501 3256.00 0.00 3256.00 3256.00 +@@ pp3300_dx_fp_mw 501 0.00 0.00 0.00 0.00 +@@ pp3300_dx_mcu_mv 501 3256.00 0.00 3256.00 3256.00 +@@ pp3300_dx_mcu_mw 501 5.74 0.28 11.98 5.73 ``` ## ChromeOS Build (portage / ebuild) -- cgit v1.2.1 From 8b45852648d272dfa017ace85d338b5b7ce4c47e Mon Sep 17 00:00:00 2001 From: Madhurima Paruchuri Date: Sat, 16 Jul 2022 00:40:01 +0530 Subject: zephyr: shim: fan: Replace multiple members of 'fan_config' structure with 'pwm_dt_spec' Add 'pwm_dt_spec' as a member in 'fan_config' structure, replacing existing members 'pwm', 'channel', 'flags' and 'period_ns' BUG=b:230093078 BRANCH=none TEST=zmake testall TEST=check if fan_config structure has correct 'period_ns' value using gdb: gdb ./build/zephyr/${BOARD}/build-ro/zephyr/zephyr.elf p fan_config Signed-off-by: Madhurima Paruchuri Change-Id: Idc306517629cd7140aa1bb162027cf566131cff2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763021 Reviewed-by: Fabio Baltieri --- zephyr/shim/src/fan.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/zephyr/shim/src/fan.c b/zephyr/shim/src/fan.c index 1d3f418c17..a36061626f 100644 --- a/zephyr/shim/src/fan.c +++ b/zephyr/shim/src/fan.c @@ -51,13 +51,10 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, .rpm = &node_id##_rpm, \ }, -#define FAN_CONTROL_INST(node_id) \ - [node_id] = { \ - .pwm = DEVICE_DT_GET(DT_PWMS_CTLR(node_id)), \ - .channel = DT_PWMS_CHANNEL(node_id), \ - .flags = DT_PWMS_FLAGS(node_id), \ - .period_ns = (NSEC_PER_SEC / DT_PWMS_PERIOD(node_id)), \ - .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ +#define FAN_CONTROL_INST(node_id) \ + [node_id] = { \ + .pwm = PWM_DT_SPEC_GET(node_id), \ + .tach = DEVICE_DT_GET(DT_PHANDLE(node_id, tach)), \ }, DT_INST_FOREACH_CHILD(0, FAN_CONFIGS) @@ -102,10 +99,7 @@ struct fan_data { /* Data structure to define PWM and tachometer. */ struct fan_config { - const struct device *pwm; - uint32_t channel; - pwm_flags_t flags; - uint32_t period_ns; + struct pwm_dt_spec pwm; const struct device *tach; }; @@ -119,28 +113,28 @@ static void fan_pwm_update(int ch) { const struct fan_config *cfg = &fan_config[ch]; struct fan_data *data = &fan_data[ch]; + const struct device *pwm_dev = cfg->pwm.dev; uint32_t pulse_ns; int ret; - if (!device_is_ready(cfg->pwm)) { - LOG_ERR("PWM device %s not ready", cfg->pwm->name); + if (!device_is_ready(pwm_dev)) { + LOG_ERR("PWM device %s not ready", pwm_dev->name); return; } if (data->pwm_enabled) { - pulse_ns = DIV_ROUND_NEAREST(cfg->period_ns * data->pwm_percent, - 100); + pulse_ns = DIV_ROUND_NEAREST( + cfg->pwm.period * data->pwm_percent, 100); } else { pulse_ns = 0; } - LOG_DBG("FAN PWM %s set percent (%d), pulse %d", cfg->pwm->name, + LOG_DBG("FAN PWM %s set percent (%d), pulse %d", pwm_dev->name, data->pwm_percent, pulse_ns); - ret = pwm_set(cfg->pwm, cfg->channel, cfg->period_ns, pulse_ns, - cfg->flags); + ret = pwm_set_dt(&cfg->pwm, cfg->pwm.period, pulse_ns); if (ret) { - LOG_ERR("pwm_set() failed %s (%d)", cfg->pwm->name, ret); + LOG_ERR("pwm_set() failed %s (%d)", pwm_dev->name, ret); } } -- cgit v1.2.1 From 1f73e9e2be4b87ced0cfabdbdc35def427d0ad30 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Wed, 13 Jul 2022 16:35:39 +0800 Subject: kinox: disable fan full on when board initial Remove fan pwm duty 100 when board initial. BUG=b:238284556 BRANCH=none TEST=Fan not rotating when board initial. Signed-off-by: Matt Wang Change-Id: Id03d958fa3badfe4e36e79ed4b2f8f12ed8230c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759837 Reviewed-by: Ricky Chang --- board/kinox/gpio.inc | 2 +- board/kinox/pwm.c | 7 ------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/board/kinox/gpio.inc b/board/kinox/gpio.inc index efe9e37eeb..5c5f52ecc1 100644 --- a/board/kinox/gpio.inc +++ b/board/kinox/gpio.inc @@ -30,7 +30,7 @@ GPIO(EC_ENTERING_RW, PIN(0, 3), GPIO_OUT_LOW) GPIO(EC_GSC_PACKET_MODE, PIN(7, 5), GPIO_OUT_LOW) /* Fan */ -GPIO(EN_PP12000_FAN, PIN(6, 1), GPIO_OUT_HIGH) +GPIO(EN_PP12000_FAN, PIN(6, 1), GPIO_OUT_LOW) /* Display */ GPIO(DP_CONN_OC_ODL, PIN(2, 5), GPIO_INPUT) diff --git a/board/kinox/pwm.c b/board/kinox/pwm.c index 519ba751b1..f47008ceb9 100644 --- a/board/kinox/pwm.c +++ b/board/kinox/pwm.c @@ -27,14 +27,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); static void board_pwm_init(void) { - /* - * TODO(b/197478860): Turn on the fan at 100% by default - * We need to find tune the fan speed according to the - * thermal sensor value. - */ pwm_enable(PWM_CH_FAN, 1); - pwm_set_duty(PWM_CH_FAN, 100); - pwm_enable(PWM_CH_LED_RED, 1); pwm_enable(PWM_CH_LED_GREEN, 1); } -- cgit v1.2.1 From 6b6780c3159a2e3830bb5794260eba8b37413f03 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Wed, 13 Jul 2022 18:13:15 +0800 Subject: Nereid: enable 1.8v input for 1.8v I/O Since the I/O voltage of the following signals is 1.8 V, the 1.8V input selection is enabled. - IMU_INT_L - ACC_INT_L - EC_I2C_SENSOR_SCL - EC_I2C_SENSOR_SDA - VCCIN_AUX_VID0 - VCCIN_AUX_VID1 Note: I/O voltage of EC_PROCHOT_ODL and EC_SOC_VCCST_PWRGD_OD are 1.05V. Chose the closest voltage configuration for them. BRANCH=none BUG=b:236668079, b:237717730 TEST=The corresponding 1.8v input control bit is set to 1. Saved ~2mW on Nereid in S0/S0ix state. Signed-off-by: Dino Li Change-Id: I05a406c6cc21ff651c594fe7a64be1d91a9416cd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765107 Reviewed-by: Andrew McRae Reviewed-by: Peter Marheine --- zephyr/projects/nissa/nereid_overlay.dts | 23 +++++++++++++++++++++++ zephyr/projects/nissa/nereid_power_signals.dts | 2 +- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index 95bfe2fa03..b7faf96ada 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -255,6 +255,23 @@ }; }; +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + &thermistor_3V3_51K1_47K_4050B { status = "okay"; }; @@ -287,6 +304,12 @@ i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; }; + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; }; &i2c0 { diff --git a/zephyr/projects/nissa/nereid_power_signals.dts b/zephyr/projects/nissa/nereid_power_signals.dts index 0a3ead778b..0f10bba52f 100644 --- a/zephyr/projects/nissa/nereid_power_signals.dts +++ b/zephyr/projects/nissa/nereid_power_signals.dts @@ -75,7 +75,7 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "VCCST_PWRGD output to PCH"; enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioe 5 GPIO_OPEN_DRAIN>; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; output; }; pwr-imvp9-vrrdy-od { -- cgit v1.2.1 From 546fc64f509d55b2608b10f808562e913eaf2ffd Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 14:46:59 +0800 Subject: ps8xxx: move ps8xxx_tcpc_update_hpd_status binding out of tcpci It's more reasonable to place ps8xxx_tcpc_update_hpd_status in parade,usbc-mux-ps8xxx.yaml. BUG=none TEST=zmake testall BRANCH=none Change-Id: I950276f7d44093c602ba80940f5522d8a47dda26 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725849 Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Eric Yilun Lin --- zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml | 2 -- zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml index 9b986a5942..f7dda3042c 100644 --- a/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml +++ b/zephyr/dts/bindings/usbc/mux/cros-ec,usbc-mux-tcpci.yaml @@ -14,8 +14,6 @@ properties: required: false description: | Name of function used as hpd_update callback - enum: - - ps8xxx_tcpc_update_hpd_status port: type: phandle diff --git a/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml index 685544cbf4..53a0d03738 100644 --- a/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml +++ b/zephyr/dts/bindings/usbc/mux/parade,usbc-mux-ps8xxx.yaml @@ -13,3 +13,5 @@ properties: description: | PS8xxx USB MUX almost always use this hdp_update callback default: "ps8xxx_tcpc_update_hpd_status" + enum: + - ps8xxx_tcpc_update_hpd_status -- cgit v1.2.1 From 830b6f897fd70f8d9c845723737c7027bbc13591 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 14:53:35 +0800 Subject: anx7447: add device binding for TCPC and USB_MUX add anx7447 dt-bindings for TCPC and USBC MUX. BUG=b:227359727 TEST=enable on kingler, and TCPC/USBC works BRANCH=none Change-Id: Ib248d8b4bd0eee447193be0de28605da9aa8b1c9 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725850 Reviewed-by: Keith Short Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin Reviewed-by: Diana Z --- .../dts/bindings/usbc/anologix,anx7447-tcpc.yaml | 27 ++++++++++++++++++++++ .../usbc/mux/analogix,usbc-mux-anx7447.yaml | 15 ++++++++++++ zephyr/shim/include/usbc/tcpc_anx7447.h | 21 +++++++++++++++++ zephyr/shim/include/usbc/tcpci_usb_mux.h | 2 ++ zephyr/shim/include/usbc/usb_muxes.h | 3 ++- zephyr/shim/src/tcpc.c | 6 ++++- 6 files changed, 72 insertions(+), 2 deletions(-) create mode 100644 zephyr/dts/bindings/usbc/anologix,anx7447-tcpc.yaml create mode 100644 zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml create mode 100644 zephyr/shim/include/usbc/tcpc_anx7447.h diff --git a/zephyr/dts/bindings/usbc/anologix,anx7447-tcpc.yaml b/zephyr/dts/bindings/usbc/anologix,anx7447-tcpc.yaml new file mode 100644 index 0000000000..48543c808d --- /dev/null +++ b/zephyr/dts/bindings/usbc/anologix,anx7447-tcpc.yaml @@ -0,0 +1,27 @@ +description: Anologix ANX7447 USBC TCPC binding + +compatible: "anologix,anx7447-tcpc" + +properties: + port: + type: phandle + required: true + description: | + I2C port used to communicate with controller + + i2c-addr-flags: + type: string + default: "AN7447_TCPC0_I2C_ADDR_FLAGS" + enum: + - "AN7447_TCPC0_I2C_ADDR_FLAGS" + - "AN7447_TCPC1_I2C_ADDR_FLAGS" + - "AN7447_TCPC2_I2C_ADDR_FLAGS" + - "AN7447_TCPC3_I2C_ADDR_FLAGS" + description: | + I2C address of controller + + tcpc-flags: + type: int + default: 0 + description: | + TCPC configuration flags diff --git a/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml new file mode 100644 index 0000000000..17ad0fcb04 --- /dev/null +++ b/zephyr/dts/bindings/usbc/mux/analogix,usbc-mux-anx7447.yaml @@ -0,0 +1,15 @@ +# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: USBC ANX7447 USB MUX + +include: cros-ec,usbc-mux-tcpci.yaml + +compatible: "analogix,usbc-mux-anx7447" + +properties: + hpd-update: + required: false + enum: + - anx7447_tcpc_update_hpd_status diff --git a/zephyr/shim/include/usbc/tcpc_anx7447.h b/zephyr/shim/include/usbc/tcpc_anx7447.h new file mode 100644 index 0000000000..7f5c0891f9 --- /dev/null +++ b/zephyr/shim/include/usbc/tcpc_anx7447.h @@ -0,0 +1,21 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include "tcpm/anx7447_public.h" + +#define ANX7447_TCPC_COMPAT anologix_anx7447_tcpc + +#define TCPC_CONFIG_ANX7447(id) \ + { \ + .bus_type = EC_BUS_TYPE_I2C, \ + .i2c_info = { \ + .port = I2C_PORT(DT_PHANDLE(id, port)), \ + .addr_flags = DT_STRING_UPPER_TOKEN( \ + id, i2c_addr_flags), \ + }, \ + .drv = &anx7447_tcpm_drv, \ + .flags = DT_PROP(id, tcpc_flags), \ + }, diff --git a/zephyr/shim/include/usbc/tcpci_usb_mux.h b/zephyr/shim/include/usbc/tcpci_usb_mux.h index 74a2fe8ffc..1f98bafc23 100644 --- a/zephyr/shim/include/usbc/tcpci_usb_mux.h +++ b/zephyr/shim/include/usbc/tcpci_usb_mux.h @@ -7,9 +7,11 @@ #define __ZEPHYR_SHIM_TCPCI_USB_MUX_H #include "dt-bindings/usbc_mux.h" +#include "tcpm/anx7447_public.h" #include "tcpm/ps8xxx_public.h" #include "tcpm/tcpci.h" +#define ANX7447_USB_MUX_COMPAT analogix_usbc_mux_anx7447 #define TCPCI_TCPM_USB_MUX_COMPAT cros_ec_usbc_mux_tcpci #define PS8XXX_USB_MUX_COMPAT parade_usbc_mux_ps8xxx diff --git a/zephyr/shim/include/usbc/usb_muxes.h b/zephyr/shim/include/usbc/usb_muxes.h index 250b3dd329..61422a743b 100644 --- a/zephyr/shim/include/usbc/usb_muxes.h +++ b/zephyr/shim/include/usbc/usb_muxes.h @@ -22,7 +22,8 @@ * element of list has to have (compatible, config) format. */ #define USB_MUX_DRIVERS \ - (ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483), \ + (ANX7447_USB_MUX_COMPAT, USB_MUX_CONFIG_TCPCI_TCPM), \ + (ANX7483_USB_MUX_COMPAT, USB_MUX_CONFIG_ANX7483), \ (BB_RETIMER_USB_MUX_COMPAT, USB_MUX_CONFIG_BB_RETIMER), \ (IT5205_USB_MUX_COMPAT, USB_MUX_CONFIG_IT5205), \ (PS8743_USB_MUX_COMPAT, USB_MUX_CONFIG_PS8743), \ diff --git a/zephyr/shim/src/tcpc.c b/zephyr/shim/src/tcpc.c index 02cecdd70f..98237044b7 100644 --- a/zephyr/shim/src/tcpc.c +++ b/zephyr/shim/src/tcpc.c @@ -7,6 +7,7 @@ #include #include "usb_pd_tcpm.h" #include "usb_pd.h" +#include "usbc/tcpc_anx7447.h" #include "usbc/tcpc_ccgxxf.h" #include "usbc/tcpc_fusb302.h" #include "usbc/tcpc_it8xxx2.h" @@ -16,7 +17,8 @@ #include "usbc/tcpci.h" #include "usbc/utils.h" -#if DT_HAS_COMPAT_STATUS_OKAY(CCGXXF_TCPC_COMPAT) || \ +#if DT_HAS_COMPAT_STATUS_OKAY(ANX7447_TCPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(CCGXXF_TCPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(FUSB302_TCPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(IT8XXX2_TCPC_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(PS8XXX_COMPAT) || \ @@ -32,6 +34,8 @@ /* Enable clang-format when the formatted code is readable. */ /* clang-format off */ MAYBE_CONST struct tcpc_config_t tcpc_config[] = { + DT_FOREACH_STATUS_OKAY_VARGS(ANX7447_TCPC_COMPAT, TCPC_CONFIG, + TCPC_CONFIG_ANX7447) DT_FOREACH_STATUS_OKAY_VARGS(CCGXXF_TCPC_COMPAT, TCPC_CONFIG, TCPC_CONFIG_CCGXXF) DT_FOREACH_STATUS_OKAY_VARGS(FUSB302_TCPC_COMPAT, TCPC_CONFIG, -- cgit v1.2.1 From e002a7a8f9935e693226446fd17c98ce5bc4c0a9 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 15:08:32 +0800 Subject: nx20p348x: add device binding for PPC add NXP NX20P348X PPC device binding BUG=b:227359727 TEST=enable on kingler BRANCH=none Change-Id: Id050a0cb5fccf3dd0b868f374bf2849087ec6505 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725851 Reviewed-by: Paul Fagerburg Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/dts/bindings/usbc/nxp,nx20p348x.yaml | 22 ++++++++++++++++++++++ zephyr/shim/include/usbc/ppc.h | 11 +++++++---- zephyr/shim/include/usbc/ppc_nx20p348x.h | 13 +++++++++++++ zephyr/shim/src/ppc.c | 10 ++++++++-- 4 files changed, 50 insertions(+), 6 deletions(-) create mode 100644 zephyr/dts/bindings/usbc/nxp,nx20p348x.yaml create mode 100644 zephyr/shim/include/usbc/ppc_nx20p348x.h diff --git a/zephyr/dts/bindings/usbc/nxp,nx20p348x.yaml b/zephyr/dts/bindings/usbc/nxp,nx20p348x.yaml new file mode 100644 index 0000000000..bc721a8eb9 --- /dev/null +++ b/zephyr/dts/bindings/usbc/nxp,nx20p348x.yaml @@ -0,0 +1,22 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: NXP NX20P348X USBC PPC binding + +compatible: "nxp,nx20p348x" + +include: ppc-chip.yaml + +properties: + i2c-addr-flags: + default: "NX20P3483_ADDR2_FLAGS" + enum: + - "NX20P3483_ADDR0_FLAGS" + - "NX20P3483_ADDR1_FLAGS" + - "NX20P3483_ADDR2_FLAGS" + - "NX20P3483_ADDR3_FLAGS" + - "NX20P3481_ADDR0_FLAGS" + - "NX20P3481_ADDR1_FLAGS" + - "NX20P3481_ADDR2_FLAGS" + - "NX20P3481_ADDR3_FLAGS" diff --git a/zephyr/shim/include/usbc/ppc.h b/zephyr/shim/include/usbc/ppc.h index 9d7dfdd824..f6fe6e884b 100644 --- a/zephyr/shim/include/usbc/ppc.h +++ b/zephyr/shim/include/usbc/ppc.h @@ -9,6 +9,7 @@ #include #include #include "usbc/ppc_rt1739.h" +#include "usbc/ppc_nx20p348x.h" #include "usbc/ppc_sn5s330.h" #include "usbc/ppc_syv682x.h" #include "usbc/utils.h" @@ -23,10 +24,12 @@ (PPC_ID_WITH_COMMA(id)), ()) enum ppc_chips_alt_id { - DT_FOREACH_STATUS_OKAY(RT1739_PPC_COMPAT, PPC_ALT_ENUM) - DT_FOREACH_STATUS_OKAY(SN5S330_COMPAT, PPC_ALT_ENUM) - DT_FOREACH_STATUS_OKAY(SYV682X_COMPAT, PPC_ALT_ENUM) - PPC_CHIP_ALT_COUNT + DT_FOREACH_STATUS_OKAY(NX20P348X_COMPAT, PPC_ALT_ENUM) + DT_FOREACH_STATUS_OKAY(RT1739_PPC_COMPAT, PPC_ALT_ENUM) + DT_FOREACH_STATUS_OKAY(SN5S330_COMPAT, PPC_ALT_ENUM) + DT_FOREACH_STATUS_OKAY(SYV682X_COMPAT, + PPC_ALT_ENUM) + PPC_CHIP_ALT_COUNT }; extern struct ppc_config_t ppc_chips_alt[]; diff --git a/zephyr/shim/include/usbc/ppc_nx20p348x.h b/zephyr/shim/include/usbc/ppc_nx20p348x.h new file mode 100644 index 0000000000..162a937a99 --- /dev/null +++ b/zephyr/shim/include/usbc/ppc_nx20p348x.h @@ -0,0 +1,13 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ppc/nx20p348x_public.h" + +#define NX20P348X_COMPAT nxp_nx20p348x + +#define PPC_CHIP_NX20P348X(id) \ + { .i2c_port = I2C_PORT(DT_PHANDLE(id, port)), \ + .i2c_addr_flags = DT_STRING_UPPER_TOKEN(id, i2c_addr_flags), \ + .drv = &nx20p348x_drv }, diff --git a/zephyr/shim/src/ppc.c b/zephyr/shim/src/ppc.c index 48a382174b..ebfcb393ab 100644 --- a/zephyr/shim/src/ppc.c +++ b/zephyr/shim/src/ppc.c @@ -5,13 +5,15 @@ #include #include "usbc_ppc.h" +#include "usbc/ppc_nx20p348x.h" #include "usbc/ppc_rt1739.h" #include "usbc/ppc_sn5s330.h" #include "usbc/ppc_syv682x.h" #include "usbc/ppc.h" -#if DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \ - DT_HAS_COMPAT_STATUS_OKAY(SN5S330_COMPAT) || \ +#if DT_HAS_COMPAT_STATUS_OKAY(NX20P348X_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(RT1739_PPC_COMPAT) || \ + DT_HAS_COMPAT_STATUS_OKAY(SN5S330_COMPAT) || \ DT_HAS_COMPAT_STATUS_OKAY(SYV682X_COMPAT) #define PPC_CHIP_PRIM(id, fn) \ @@ -30,6 +32,8 @@ /* Enable clang-format when the formatted code is readable. */ /* clang-format off */ struct ppc_config_t ppc_chips[] = { + DT_FOREACH_STATUS_OKAY_VARGS(NX20P348X_COMPAT, PPC_CHIP_PRIM, + PPC_CHIP_NX20P348X) DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_PRIM, PPC_CHIP_RT1739) DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_PRIM, @@ -43,6 +47,8 @@ unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); /* Alt Power Path Controllers */ /* clang-format off */ struct ppc_config_t ppc_chips_alt[] = { + DT_FOREACH_STATUS_OKAY_VARGS(NX20P348X_COMPAT, PPC_CHIP_ALT, + PPC_CHIP_NX20P348X) DT_FOREACH_STATUS_OKAY_VARGS(RT1739_PPC_COMPAT, PPC_CHIP_ALT, PPC_CHIP_RT1739) DT_FOREACH_STATUS_OKAY_VARGS(SN5S330_COMPAT, PPC_CHIP_ALT, -- cgit v1.2.1 From b39ff158e7d3e1142160d0d4d8664c3edeea11db Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 18 Jul 2022 10:42:29 +0800 Subject: rt1718s: suffix comma at config definition macro The comma is needed after f1addb9d960dd94827f3eeb53e9654b963cd0f54, 7c114b8e1a3bb29991da70b9de394ac5d4f6c909 reverted. BUG=b:227359727 TEST=zmake build kingler BRANCH=none Change-Id: I3b35ccc0e4b1fc8620dcb876a23fa32a1b415ffb Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768126 Tested-by: Eric Yilun Lin Auto-Submit: Eric Yilun Lin Commit-Queue: Eric Yilun Lin Reviewed-by: Sung-Chi Li --- zephyr/shim/include/usbc/bc12_rt1718s.h | 2 +- zephyr/shim/include/usbc/tcpc_rt1718s.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/include/usbc/bc12_rt1718s.h b/zephyr/shim/include/usbc/bc12_rt1718s.h index 578d0dab5a..f6860268a3 100644 --- a/zephyr/shim/include/usbc/bc12_rt1718s.h +++ b/zephyr/shim/include/usbc/bc12_rt1718s.h @@ -10,4 +10,4 @@ #define BC12_CHIP_RT1718S(id) \ { \ .drv = &rt1718s_bc12_drv, \ - } + }, diff --git a/zephyr/shim/include/usbc/tcpc_rt1718s.h b/zephyr/shim/include/usbc/tcpc_rt1718s.h index acab65b6e5..7da7427a98 100644 --- a/zephyr/shim/include/usbc/tcpc_rt1718s.h +++ b/zephyr/shim/include/usbc/tcpc_rt1718s.h @@ -23,5 +23,5 @@ }, \ .drv = &rt1718s_tcpm_drv, \ .flags = DT_PROP(id, tcpc_flags), \ - } + }, /* clang-format on */ -- cgit v1.2.1 From 40f01ebc88f35e20001bc23b7c33bd8ee39a0438 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 15:50:39 +0800 Subject: kingler: migrate tcpc config to dts BUG=b:227359727 TEST=kingler TCPC works BRANCH=none Change-Id: I38a6efecd9bc2a2b1aea34874e6a2babed4158c1 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725853 Reviewed-by: Ting Shen Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/projects/corsola/src/kingler/usbc_config.c | 25 ----------------------- zephyr/projects/corsola/usbc_kingler.dts | 22 +++++++++++++++++++- 2 files changed, 21 insertions(+), 26 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index 4b48d9fd96..d9300d3f44 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -34,31 +34,6 @@ #define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) -struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C0, - .addr_flags = AN7447_TCPC0_I2C_ADDR_FLAGS, - }, - .drv = &anx7447_tcpm_drv, - /* Alert is active-low, open-drain */ - .flags = TCPC_FLAGS_ALERT_OD | TCPC_FLAGS_VBUS_MONITOR | - TCPC_FLAGS_CONTROL_FRS, - }, - [USBC_PORT_C1] = { - .bus_type = EC_BUS_TYPE_I2C, - .i2c_info = { - .port = I2C_PORT_USB_C1, - .addr_flags = RT1718S_I2C_ADDR2_FLAGS, - }, - .drv = &rt1718s_tcpm_drv, - /* Alert is active-low, open-drain */ - .flags = TCPC_FLAGS_ALERT_OD | TCPC_FLAGS_VBUS_MONITOR | - TCPC_FLAGS_CONTROL_FRS, - } -}; - struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0, .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts index 6703498ad5..d35abf3955 100644 --- a/zephyr/projects/corsola/usbc_kingler.dts +++ b/zephyr/projects/corsola/usbc_kingler.dts @@ -3,6 +3,8 @@ * found in the LICENSE file. */ +#include + / { usbc { #address-cells = <1>; @@ -14,7 +16,16 @@ port0@0 { compatible = "named-usbc-port"; reg = <0>; - + tcpc { + compatible = "anologix,anx7447-tcpc"; + status = "okay"; + port = <&i2c_usb_c0>; + i2c-addr-flags = "AN7447_TCPC0_I2C_ADDR_FLAGS"; + tcpc-flags = <( + TCPC_FLAGS_ALERT_OD | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; chg { compatible = "intersil,isl923x"; status = "okay"; @@ -25,6 +36,15 @@ port1@1 { compatible = "named-usbc-port"; reg = <1>; + tcpc { + compatible = "richtek,rt1718s-tcpc"; + port = <&i2c_usb_c1>; + i2c-addr-flags = "RT1718S_I2C_ADDR2_FLAGS"; + tcpc-flags = <( + TCPC_FLAGS_ALERT_OD | + TCPC_FLAGS_CONTROL_VCONN | + TCPC_FLAGS_CONTROL_FRS)>; + }; }; }; }; -- cgit v1.2.1 From df1e8c840d1c8707c2f26e041040c77d5c1007dd Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 16:00:18 +0800 Subject: kingler: migrate bc12 config to dts BUG=b:227359727 TEST=enable on kingler BRANCH=none Change-Id: I9230593a557e7abfa8e886abf454c5a32f6026aa Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725854 Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen Commit-Queue: Eric Yilun Lin --- zephyr/projects/corsola/src/kingler/usbc_config.c | 18 ------------------ zephyr/projects/corsola/usbc_kingler.dts | 12 ++++++++++++ 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index d9300d3f44..0f4fa32e49 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -95,24 +95,6 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { }, }; -struct bc12_config bc12_ports[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { - .drv = &pi3usb9201_drv, - }, - [USBC_PORT_C1] = { - .drv = &rt1718s_bc12_drv, - } -}; - -const struct pi3usb9201_config_t - pi3usb9201_bc12_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, - }, - [USBC_PORT_C1] = { /* unused */ } -}; - void board_tcpc_init(void) { /* Only reset TCPC if not sysjump */ diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts index d35abf3955..ac8dd5057a 100644 --- a/zephyr/projects/corsola/usbc_kingler.dts +++ b/zephyr/projects/corsola/usbc_kingler.dts @@ -16,6 +16,13 @@ port0@0 { compatible = "named-usbc-port"; reg = <0>; + bc12 { + compatible = "pericom,pi3usb9201"; + port = <&i2c_usb_c0>; + irq = <&int_usb_c0_bc12>; + i2c-addr-flags = "PI3USB9201_I2C_ADDR_3_FLAGS"; + status = "okay"; + }; tcpc { compatible = "anologix,anx7447-tcpc"; status = "okay"; @@ -36,6 +43,11 @@ port1@1 { compatible = "named-usbc-port"; reg = <1>; + bc12 { + compatible = "richtek,rt1718s-bc12"; + port = <&i2c_usb_c1>; + status = "okay"; + }; tcpc { compatible = "richtek,rt1718s-tcpc"; port = <&i2c_usb_c1>; -- cgit v1.2.1 From 7b24d758acfa2bfe0292b30b4db42927898936ef Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 16:05:08 +0800 Subject: kingler: migrate ppc config to dts BUG=b:227359727 TEST=enable on kingler BRANCH=none Change-Id: I5bd68c298c5c3820ae5ba62c602729e8993017d2 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725855 Reviewed-by: Ting Shen Tested-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- zephyr/projects/corsola/src/kingler/usbc_config.c | 10 ---------- zephyr/projects/corsola/usbc_kingler.dts | 12 ++++++++++++ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index 0f4fa32e49..7d93838dcb 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -34,16 +34,6 @@ #define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) -struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { .i2c_port = I2C_PORT_USB_C0, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv }, - [USBC_PORT_C1] = { .i2c_port = I2C_PORT_USB_C1, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv } -}; -unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); - /* USB Mux */ /* USB Mux C1 : board_init of PS8743 */ diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts index ac8dd5057a..74859a69fb 100644 --- a/zephyr/projects/corsola/usbc_kingler.dts +++ b/zephyr/projects/corsola/usbc_kingler.dts @@ -33,6 +33,12 @@ TCPC_FLAGS_CONTROL_VCONN | TCPC_FLAGS_CONTROL_FRS)>; }; + ppc { + compatible = "nxp,nx20p348x"; + status = "okay"; + port = <&i2c_usb_c0>; + i2c-addr-flags = "NX20P3483_ADDR2_FLAGS"; + }; chg { compatible = "intersil,isl923x"; status = "okay"; @@ -57,6 +63,12 @@ TCPC_FLAGS_CONTROL_VCONN | TCPC_FLAGS_CONTROL_FRS)>; }; + ppc { + compatible = "nxp,nx20p348x"; + status = "okay"; + port = <&i2c_usb_c1>; + i2c-addr-flags = "NX20P3483_ADDR2_FLAGS"; + }; }; }; }; -- cgit v1.2.1 From f22c1a18ec5bc683d8ee0eca6bd0964860955450 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Mon, 27 Jun 2022 16:07:34 +0800 Subject: kingler: migrate usb_mux config to dts BUG=b:227359727 TEST=enable on kingler BRANCH=none Change-Id: I97e19ce15aebcd4fc8b17e67a0bc04c55127372e Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3725856 Reviewed-by: Sung-Chi Li Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- zephyr/projects/corsola/src/kingler/usbc_config.c | 31 +---------------------- zephyr/projects/corsola/usbc_kingler.dts | 26 ++++++++++++++++--- 2 files changed, 24 insertions(+), 33 deletions(-) diff --git a/zephyr/projects/corsola/src/kingler/usbc_config.c b/zephyr/projects/corsola/src/kingler/usbc_config.c index 7d93838dcb..625524f1d6 100644 --- a/zephyr/projects/corsola/src/kingler/usbc_config.c +++ b/zephyr/projects/corsola/src/kingler/usbc_config.c @@ -37,7 +37,7 @@ /* USB Mux */ /* USB Mux C1 : board_init of PS8743 */ -static int ps8743_tune_mux(const struct usb_mux *me) +int ps8743_mux_1_board_init(const struct usb_mux *me) { ps8743_tune_usb_eq(me, PS8743_USB_EQ_TX_3_6_DB, PS8743_USB_EQ_RX_16_0_DB); @@ -56,35 +56,6 @@ void board_usb_mux_init(void) } DECLARE_HOOK(HOOK_INIT, board_usb_mux_init, HOOK_PRIO_INIT_I2C + 1); -const struct usb_mux usbc0_virtual_mux = { - .usb_port = USBC_PORT_C0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -const struct usb_mux usbc1_virtual_mux = { - .usb_port = USBC_PORT_C1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, -}; - -struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = { - [USBC_PORT_C0] = { - .usb_port = USBC_PORT_C0, - .driver = &anx7447_usb_mux_driver, - .hpd_update = &anx7447_tcpc_update_hpd_status, - .next_mux = &usbc0_virtual_mux, - }, - [USBC_PORT_C1] = { - .usb_port = USBC_PORT_C1, - .i2c_port = I2C_PORT_USB_C1, - .i2c_addr_flags = PS8743_I2C_ADDR0_FLAG, - .driver = &ps8743_usb_mux_driver, - .next_mux = &usbc1_virtual_mux, - .board_init = &ps8743_tune_mux, - }, -}; - void board_tcpc_init(void) { /* Only reset TCPC if not sysjump */ diff --git a/zephyr/projects/corsola/usbc_kingler.dts b/zephyr/projects/corsola/usbc_kingler.dts index 74859a69fb..53a7f402e3 100644 --- a/zephyr/projects/corsola/usbc_kingler.dts +++ b/zephyr/projects/corsola/usbc_kingler.dts @@ -10,9 +10,6 @@ #address-cells = <1>; #size-cells = <0>; - /* TODO(b/227359727): kingler: convert USB-C configuration to - * devicetree - */ port0@0 { compatible = "named-usbc-port"; reg = <0>; @@ -39,6 +36,7 @@ port = <&i2c_usb_c0>; i2c-addr-flags = "NX20P3483_ADDR2_FLAGS"; }; + usb-muxes = <&anx7447_mux_0 &virtual_mux_0>; chg { compatible = "intersil,isl923x"; status = "okay"; @@ -46,6 +44,15 @@ }; }; + port0-muxes { + anx7447_mux_0: anx7447-mux-0 { + compatible = "analogix,usbc-mux-anx7447"; + }; + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { compatible = "named-usbc-port"; reg = <1>; @@ -69,6 +76,19 @@ port = <&i2c_usb_c1>; i2c-addr-flags = "NX20P3483_ADDR2_FLAGS"; }; + usb-muxes = <&ps8743_mux_1 &virtual_mux_1>; + }; + + port1-muxes { + ps8743_mux_1: ps8743-mux-1 { + compatible = "parade,ps8743"; + port = <&i2c_usb_c1>; + i2c-addr-flags = "PS8743_I2C_ADDR0_FLAG"; + board-init = "ps8743_mux_1_board_init"; + }; + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; }; }; }; -- cgit v1.2.1 From b5f0e68ae441132d8aa1811513a07a27d5ae5709 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Mon, 18 Jul 2022 13:15:27 +0800 Subject: Joxer: enable 1.8v input for 1.8v I/O Follow CL:3765107 to enable 1.8v input for 1.8v I/O on joxer BRANCH=none BUG=b:236668079, b:237717730 TEST=zmake build joxer Signed-off-by: Scott Chao Change-Id: I9fe95b3c76e5255d4eece570106f1b73ab1bed39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768129 Reviewed-by: Peter Marheine Reviewed-by: Andrew McRae --- zephyr/projects/nissa/joxer_overlay.dts | 27 +++++++++++++++++++++++++++ zephyr/projects/nissa/joxer_power_signals.dts | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index 93fa888404..1c6e1a3185 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -271,6 +271,23 @@ }; }; +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + &thermistor_3V3_51K1_47K_4050B { status = "okay"; }; @@ -296,6 +313,16 @@ pinctrl-names = "default"; }; +&pinctrl { + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + + &i2c0 { label = "I2C_EEPROM"; clock-frequency = ; diff --git a/zephyr/projects/nissa/joxer_power_signals.dts b/zephyr/projects/nissa/joxer_power_signals.dts index 0a3ead778b..0f10bba52f 100644 --- a/zephyr/projects/nissa/joxer_power_signals.dts +++ b/zephyr/projects/nissa/joxer_power_signals.dts @@ -75,7 +75,7 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "VCCST_PWRGD output to PCH"; enum-name = "PWR_VCCST_PWRGD"; - gpios = <&gpioe 5 GPIO_OPEN_DRAIN>; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; output; }; pwr-imvp9-vrrdy-od { -- cgit v1.2.1 From 524cba08cceb373050cf79c41e4f6f92ff519c5e Mon Sep 17 00:00:00 2001 From: Ting Shen Date: Fri, 15 Jul 2022 17:34:53 +0800 Subject: mkbp: don't queue mkbp events in S3 In S3, if a mkbp event is not a wake source, we should not queue it in the mkbp fifo, otherwise the system will see a bunch of outdated event after resume. mkbp_fifo_add() uses the return value from mkbp_send_event() to decide if it needs to queue the event. So we need to pass the decision through the path activate_mkbp_with_events() -> mkbp_send_event() -> mkbp_fifo_add(). BUG=b:238057993 TEST=suspend -> lidclose -> lidopen(=resume) verify that powerd does not see the lid close event. BRANCH=cherry Signed-off-by: Ting Shen Change-Id: I3e1c58f97020d7ee2e3b4b56f14c4cadf51bef64 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765440 Reviewed-by: Jett Rink Commit-Queue: Ting Shen Reviewed-by: Mengqi Guo Tested-by: Ting Shen --- common/mkbp_event.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/common/mkbp_event.c b/common/mkbp_event.c index b499789e04..71ce7f8a05 100644 --- a/common/mkbp_event.c +++ b/common/mkbp_event.c @@ -201,7 +201,10 @@ static inline int host_is_sleeping(void) static void force_mkbp_if_events(void); DECLARE_DEFERRED(force_mkbp_if_events); -static void activate_mkbp_with_events(uint32_t events_to_add) +/* + * Send events to AP, return true if succeeded to generate host interrupt. + */ +static bool activate_mkbp_with_events(uint32_t events_to_add) { int interrupt_id = -1; int skip_interrupt = 0; @@ -243,7 +246,7 @@ static void activate_mkbp_with_events(uint32_t events_to_add) /* If we don't need to send an interrupt we are done */ if (interrupt_id < 0) - return; + return false; /* Send a rising edge MKBP interrupt */ rv = mkbp_set_host_active(1, &mkbp_last_event_time); @@ -266,6 +269,8 @@ static void activate_mkbp_with_events(uint32_t events_to_add) if (rv != EC_SUCCESS) CPRINTS("Could not activate MKBP (%d). Deferring", rv); } + + return rv == EC_SUCCESS; } /* @@ -338,9 +343,7 @@ static void force_mkbp_if_events(void) test_mockable int mkbp_send_event(uint8_t event_type) { - activate_mkbp_with_events(BIT(event_type)); - - return 1; + return activate_mkbp_with_events(BIT(event_type)); } static int set_inactive_if_no_events(void) -- cgit v1.2.1 From 79f3b8d7cd788ce78966ff76e1c7112c27136ce9 Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Mon, 11 Jul 2022 15:13:33 +0530 Subject: ap_pwrseq: set VCCST_PWRGD_OD low early in power down sequence In power down sequence or in S0 to S3 transition, VCCST_PWRGD_OD is set to low in S0S3 state. This do not meet the timing requirements. Hence change sets VCCST_PWRGD_OD set to low in S0 state when SLP_S3 is found low. PWR_VCCST_PWRGD declared as open-drain signal, measures 1.05v when set to high. Hence gpio read of PWR_VCCST_PWRGD always returns 0. Use api power_signals_on() to monitor the signal status correctly. BUG=b:236664113 BRANCH=none TEST=Verify boot and S3 on nivviks Change-Id: I422cf78ba6d086af67a8e4b1ac275aa25772b430 Signed-off-by: Deepti Deshatty Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754819 Reviewed-by: Li1 Feng Reviewed-by: Andrew McRae --- zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c index 4d1425588f..50325240fb 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c @@ -37,6 +37,12 @@ int all_sys_pwrgd_handler(void) { int retry = 0; + /* SLP_S3 is off */ + if (power_signal_get(PWR_SLP_S3) == 1) { + ap_off(); + return 1; + } + /* TODO: Add condition for no power sequencer */ power_wait_signals_timeout(POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD), AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout)); @@ -58,7 +64,7 @@ int all_sys_pwrgd_handler(void) /* PG_EC_ALL_SYS_PWRGD is asserted, enable VCCST_PWRGD_OD. */ - if (power_signal_get(PWR_VCCST_PWRGD) == 0) { + if (!power_signals_on(POWER_SIGNAL_MASK(PWR_VCCST_PWRGD))) { k_msleep(AP_PWRSEQ_DT_VALUE(vccst_pwrgd_delay)); power_signal_set(PWR_VCCST_PWRGD, 1); } -- cgit v1.2.1 From 9564b007664735636fcb6767ec1734a7dbda828d Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Mon, 18 Jul 2022 15:38:34 +0800 Subject: Joxer: modify tablet mode GPIO We use GPIOJ7 as TABLET_MODE_L. BUG=b:234683955 BRANCH=none TEST=zmake build joxer Signed-off-by: Scott Chao Change-Id: I9d59097b2da231ac9426e26fb4471a38685f376e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768136 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/joxer_generated.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/projects/nissa/joxer_generated.dts b/zephyr/projects/nissa/joxer_generated.dts index a588937f3c..d5d32a0e4e 100644 --- a/zephyr/projects/nissa/joxer_generated.dts +++ b/zephyr/projects/nissa/joxer_generated.dts @@ -185,7 +185,7 @@ gpios = <&gpiod 1 GPIO_ODR_HIGH>; }; gpio_tablet_mode_l: tablet_mode_l { - gpios = <&gpioa 7 GPIO_INPUT>; + gpios = <&gpioj 7 GPIO_INPUT>; enum-name = "GPIO_TABLET_MODE_L"; }; gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { -- cgit v1.2.1 From 2a05849cedd96a49497444f97159811db34643ce Mon Sep 17 00:00:00 2001 From: Peter Chi Date: Tue, 12 Jul 2022 16:09:05 +0800 Subject: crota: switch both volume buttons GPIO BUG=b:238713881 BRANCH=none TEST=make -j BOARD=crota Signed-off-by: Peter Chi Change-Id: If4869c06edf8b8d7134001a1fee1499c3050c023 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756997 Reviewed-by: Zhuohao Lee --- board/crota/gpio.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/crota/gpio.inc b/board/crota/gpio.inc index 655fc68060..4af9cf7138 100644 --- a/board/crota/gpio.inc +++ b/board/crota/gpio.inc @@ -12,8 +12,8 @@ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAK GPIO_INT(EC_ACCEL_INT_R_L, PIN(8, 1), GPIO_SEL_1P8V | GPIO_INT_FALLING, lis2dw12_interrupt) GPIO_INT(EC_IMU_INT_R_L, PIN(5, 6), GPIO_SEL_1P8V | GPIO_INT_FALLING, lsm6dso_interrupt) GPIO_INT(EC_PROCHOT_IN_L, PIN(F, 0), GPIO_INT_BOTH, throttle_ap_prochot_input_interrupt) -GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_WP_ODL, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) GPIO_INT(GSC_EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) -- cgit v1.2.1 From 7caea3df4a0f2cda387137a41e9f25dfa751c205 Mon Sep 17 00:00:00 2001 From: Madhurima Paruchuri Date: Mon, 18 Jul 2022 13:59:25 +0530 Subject: zephyr: drivers: displight: Use 'period' from PWM spec inplace of 'frequency' Update driver to use 'period' from PWM spec inplace of 'frequency' BUG=b:230093078 BRANCH=none TEST=zmake testall Signed-off-by: Madhurima Paruchuri Change-Id: I440a8b49bc3179d9f2b1462b64499374b0a9ab01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3769708 Reviewed-by: Fabio Baltieri --- zephyr/drivers/cros_displight/cros_displight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/drivers/cros_displight/cros_displight.c b/zephyr/drivers/cros_displight/cros_displight.c index 3dcfd35480..6f4697e36c 100644 --- a/zephyr/drivers/cros_displight/cros_displight.c +++ b/zephyr/drivers/cros_displight/cros_displight.c @@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define DISPLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0) #define DISPLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0) #define DISPLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0) -#define DISPLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC / DT_INST_PROP(0, frequency)) +#define DISPLIGHT_PWM_PERIOD_NS DT_INST_PWMS_PERIOD(0) static int displight_percent; -- cgit v1.2.1 From 1974301833fcb70e8809aa940263d8b2fe93c0ba Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 13:34:01 +0000 Subject: zephyr: adc: drop label usage for ADC channels Zephyr is moving in the direction of reemoving the label property, for the ADC usage it's redundant as we can use the node name directly. Change the shim ADC driver to use the node name and drop the label property from the binding, nodes and documentation. BRANCH=none BUG=b:239165779 TEST=zmake testall TEST=flash brya, ran the "adc" console command Signed-off-by: Fabio Baltieri Change-Id: I245abe11647c0f15ff5bee3ae42cc20e1fa9faa0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763907 Reviewed-by: Al Semjonovs --- docs/zephyr/zephyr_adc.md | 5 ----- zephyr/boards/arm/mec1727/mec1727.dts | 4 ---- zephyr/boards/arm/npcx_evb/npcx_evb.dtsi | 5 ----- zephyr/dts/bindings/adc/named-adc.yaml | 5 ----- zephyr/projects/brya/adc.dts | 4 ---- zephyr/projects/corsola/adc_kingler.dts | 4 ---- zephyr/projects/corsola/adc_krabby.dts | 4 ---- zephyr/projects/herobrine/adc.dts | 3 --- zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts | 4 ---- zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts | 4 ---- zephyr/projects/it8xxx2_evb/adc.dts | 6 ------ zephyr/projects/nissa/craask_generated.dts | 4 ---- zephyr/projects/nissa/joxer_generated.dts | 5 ----- zephyr/projects/nissa/nereid_generated.dts | 5 ----- zephyr/projects/nissa/nivviks_generated.dts | 4 ---- zephyr/projects/nissa/pujjo_generated.dts | 4 ---- zephyr/projects/nissa/xivu_generated.dts | 4 ---- zephyr/projects/skyrim/adc.dts | 4 ---- zephyr/projects/trogdor/lazor/adc.dts | 3 --- zephyr/shim/src/adc.c | 4 ++-- zephyr/test/drivers/overlay.dts | 6 ------ 21 files changed, 2 insertions(+), 89 deletions(-) diff --git a/docs/zephyr/zephyr_adc.md b/docs/zephyr/zephyr_adc.md index c57f4bd3a6..dfc913971e 100644 --- a/docs/zephyr/zephyr_adc.md +++ b/docs/zephyr/zephyr_adc.md @@ -56,7 +56,6 @@ enumeration and the Zephyr ADC driver's channel_id. named-adc-channels { compatible = "named-adc-channels"; vbus { - label = "VBUS"; enum-name = "ADC_VBUS"; io-channels = <&adc0 1>; /* Measure VBUS through a 1/10 voltage divider */ @@ -158,22 +157,18 @@ named-adc-channels { compatible = "named-adc-channels"; adc_charger: charger { - label = "TEMP_CHARGER"; enum-name = "ADC_TEMP_SENSOR_CHARGER"; io-channels = <&adc0 0>; }; adc_pp3300_regulator: pp3300_regulator { - label = "TEMP_PP3300_REGULATOR"; enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; io-channels = <&adc0 1>; }; adc_ddr_soc: ddr_soc { - label = "TEMP_DDR_SOC"; enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; io-channels = <&adc0 8>; }; adc_fan: fan { - label = "TEMP_FAN"; enum-name = "ADC_TEMP_SENSOR_FAN"; io-channels = <&adc0 3>; }; diff --git a/zephyr/boards/arm/mec1727/mec1727.dts b/zephyr/boards/arm/mec1727/mec1727.dts index d371f8a2dc..84d61bfee7 100644 --- a/zephyr/boards/arm/mec1727/mec1727.dts +++ b/zephyr/boards/arm/mec1727/mec1727.dts @@ -58,22 +58,18 @@ compatible = "named-adc-channels"; adc_ddr_soc: ddr_soc { - label = "TEMP_DDR_SOC"; enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC"; io-channels = <&adc0 5>; }; adc_ambient: ambient { - label = "TEMP_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_2_AMBIENT"; io-channels = <&adc0 3>; }; adc_charger: charger { - label = "TEMP_CHARGER"; enum-name = "ADC_TEMP_SENSOR_3_CHARGER"; io-channels = <&adc0 0>; }; adc_wwan: wwan { - label = "TEMP_WWAN"; enum-name = "ADC_TEMP_SENSOR_4_WWAN"; io-channels = <&adc0 4>; }; diff --git a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi index 9a9f221bfc..51005e47c5 100644 --- a/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi +++ b/zephyr/boards/arm/npcx_evb/npcx_evb.dtsi @@ -46,27 +46,22 @@ compatible = "named-adc-channels"; adc_ch_0 { - label = "ADC0"; enum-name = "ADC_EVB_CH_0"; io-channels = <&adc0 0>; }; adc_ch_1 { - label = "ADC1"; enum-name = "ADC_EVB_CH_1"; io-channels = <&adc0 1>; }; adc_ch_2 { - label = "ADC2"; enum-name = "ADC_EVB_CH_2"; io-channels = <&adc0 2>; }; adc_ch_3 { - label = "ADC3"; enum-name = "ADC_EVB_CH_3"; io-channels = <&adc0 3>; }; adc_ch_4 { - label = "ADC4"; enum-name = "ADC_EVB_CH_4"; io-channels = <&adc0 4>; }; diff --git a/zephyr/dts/bindings/adc/named-adc.yaml b/zephyr/dts/bindings/adc/named-adc.yaml index 80ae9d145f..f67588c0d5 100644 --- a/zephyr/dts/bindings/adc/named-adc.yaml +++ b/zephyr/dts/bindings/adc/named-adc.yaml @@ -9,11 +9,6 @@ compatible: "named-adc-channels" child-binding: description: Named ADCs child node properties: - label: - required: true - type: string - description: - String used to describe an ADC channel in the 'adc' console command. io-channels: required: true type: phandle-array diff --git a/zephyr/projects/brya/adc.dts b/zephyr/projects/brya/adc.dts index e1502b2389..c12c95df60 100644 --- a/zephyr/projects/brya/adc.dts +++ b/zephyr/projects/brya/adc.dts @@ -8,22 +8,18 @@ compatible = "named-adc-channels"; adc_ddr_soc: ddr_soc { - label = "TEMP_DDR_SOC"; enum-name = "ADC_TEMP_SENSOR_1_DDR_SOC"; io-channels = <&adc0 0>; }; adc_ambient: ambient { - label = "TEMP_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_2_AMBIENT"; io-channels = <&adc0 1>; }; adc_charger: charger { - label = "TEMP_CHARGER"; enum-name = "ADC_TEMP_SENSOR_3_CHARGER"; io-channels = <&adc0 6>; }; adc_wwan: wwan { - label = "TEMP_WWAN"; enum-name = "ADC_TEMP_SENSOR_4_WWAN"; io-channels = <&adc0 7>; }; diff --git a/zephyr/projects/corsola/adc_kingler.dts b/zephyr/projects/corsola/adc_kingler.dts index e7e70caa70..eed01c0512 100644 --- a/zephyr/projects/corsola/adc_kingler.dts +++ b/zephyr/projects/corsola/adc_kingler.dts @@ -12,7 +12,6 @@ compatible = "named-adc-channels"; adc_charger_pmon_r { - label = "ADC_CHARGER_PMON_R"; enum-name = "ADC_PSYS"; io-channels = <&adc0 0>; /* @@ -21,17 +20,14 @@ mul = <21043>; }; adc_ec_id0 { - label = "ADC_EC_ID0"; enum-name = "ADC_ID_0"; io-channels = <&adc0 1>; }; adc_ec_id1 { - label = "ADC_EC_ID1"; enum-name = "ADC_ID_1"; io-channels = <&adc0 2>; }; adc_charger_amon_r { - label = "ADC_AMON_R"; enum-name = "ADC_AMON_BMON"; io-channels = <&adc0 3>; mul = <1000>; diff --git a/zephyr/projects/corsola/adc_krabby.dts b/zephyr/projects/corsola/adc_krabby.dts index 68336f0a70..677091d54a 100644 --- a/zephyr/projects/corsola/adc_krabby.dts +++ b/zephyr/projects/corsola/adc_krabby.dts @@ -8,23 +8,19 @@ compatible = "named-adc-channels"; adc_vbus_c0 { - label = "VBUS_C0"; enum-name = "ADC_VBUS_C0"; io-channels = <&adc0 0>; mul = <10>; }; adc_board_id0 { - label = "BOARD_ID_0"; enum-name = "ADC_BOARD_ID_0"; io-channels = <&adc0 1>; }; adc_board_id1 { - label = "BOARD_ID_1"; enum-name = "ADC_BOARD_ID_1"; io-channels = <&adc0 2>; }; adc_vbus_c1 { - label = "VBUS_C1"; enum-name = "ADC_VBUS_C1"; io-channels = <&adc0 7>; mul = <10>; diff --git a/zephyr/projects/herobrine/adc.dts b/zephyr/projects/herobrine/adc.dts index bbb50cccab..e18ec88741 100644 --- a/zephyr/projects/herobrine/adc.dts +++ b/zephyr/projects/herobrine/adc.dts @@ -10,14 +10,12 @@ compatible = "named-adc-channels"; vbus { - label = "VBUS"; enum-name = "ADC_VBUS"; io-channels = <&adc0 1>; /* Measure VBUS through a 1/10 voltage divider */ mul = <10>; }; amon_bmon { - label = "AMON_BMON"; enum-name = "ADC_AMON_BMON"; io-channels = <&adc0 2>; /* @@ -29,7 +27,6 @@ div = <18>; }; psys { - label = "PSYS"; enum-name = "ADC_PSYS"; io-channels = <&adc0 3>; /* diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts index 418b68a8d7..e81c3b3c2d 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/adlrvp_npcx.dts @@ -58,22 +58,18 @@ compatible = "named-adc-channels"; adc_ambient: ambient { - label = "ADC_TEMP_SNS_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 3>; }; adc_ddr: ddr { - label = "ADC_TEMP_SNS_DDR"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 4>; }; adc_skin: skin { - label = "ADC_TEMP_SNS_SKIN"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 2>; }; adc_vr: vr { - label = "ADC_TEMP_SNS_VR"; enum-name = "ADC_TEMP_SENSOR_4"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts index 6c41c67b4f..ddf6233a8b 100644 --- a/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts +++ b/zephyr/projects/intelrvp/mtlrvp/mtlrvpp_npcx/mtlrvp_npcx.dts @@ -54,22 +54,18 @@ compatible = "named-adc-channels"; adc_ambient: ambient { - label = "ADC_TEMP_SNS_AMBIENT"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 3>; }; adc_ddr: ddr { - label = "ADC_TEMP_SNS_DDR"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 4>; }; adc_skin: skin { - label = "ADC_TEMP_SNS_SKIN"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 2>; }; adc_vr: vr { - label = "ADC_TEMP_SNS_VR"; enum-name = "ADC_TEMP_SENSOR_4"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/it8xxx2_evb/adc.dts b/zephyr/projects/it8xxx2_evb/adc.dts index b72a38b110..fb34b54986 100644 --- a/zephyr/projects/it8xxx2_evb/adc.dts +++ b/zephyr/projects/it8xxx2_evb/adc.dts @@ -8,32 +8,26 @@ compatible = "named-adc-channels"; adc_vbussa: vbussa { - label = "ADC_VBUSSA"; enum-name = "ADC_VBUS"; io-channels = <&adc0 0>; }; adc_vbussb: vbussb { - label = "ADC_VBUSSB"; enum-name = "ADC_PSYS"; io-channels = <&adc0 1>; }; adc_evb_ch_13: evb_ch_13 { - label = "ADC_EVB_CH_13"; enum-name = "ADC_AMON_BMON"; io-channels = <&adc0 2>; }; adc_evb_ch_14: evb_ch_14 { - label = "ADC_EVB_CH_14"; enum-name = "ADC_TEMP_SENSOR_FAN"; io-channels = <&adc0 3>; }; adc_evb_ch_15: evb_ch_15 { - label = "ADC_EVB_CH_15"; enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; io-channels = <&adc0 4>; }; adc_evb_ch_16: evb_ch_16 { - label = "ADC_EVB_CH_16"; enum-name = "ADC_TEMP_SENSOR_CHARGER"; io-channels = <&adc0 5>; }; diff --git a/zephyr/projects/nissa/craask_generated.dts b/zephyr/projects/nissa/craask_generated.dts index 1a4d5f044f..bf463035d6 100644 --- a/zephyr/projects/nissa/craask_generated.dts +++ b/zephyr/projects/nissa/craask_generated.dts @@ -11,22 +11,18 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 4>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 6>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 0>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/nissa/joxer_generated.dts b/zephyr/projects/nissa/joxer_generated.dts index d5d32a0e4e..1042486420 100644 --- a/zephyr/projects/nissa/joxer_generated.dts +++ b/zephyr/projects/nissa/joxer_generated.dts @@ -11,27 +11,22 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 14>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 0>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 2>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 3>; }; adc_temp_sensor_3: temp_sensor_3 { - label = "TEMP_SENSOR_3"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 13>; }; diff --git a/zephyr/projects/nissa/nereid_generated.dts b/zephyr/projects/nissa/nereid_generated.dts index a588937f3c..c969923ba0 100644 --- a/zephyr/projects/nissa/nereid_generated.dts +++ b/zephyr/projects/nissa/nereid_generated.dts @@ -11,27 +11,22 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 14>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 0>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 2>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 3>; }; adc_temp_sensor_3: temp_sensor_3 { - label = "TEMP_SENSOR_3"; enum-name = "ADC_TEMP_SENSOR_3"; io-channels = <&adc0 13>; }; diff --git a/zephyr/projects/nissa/nivviks_generated.dts b/zephyr/projects/nissa/nivviks_generated.dts index 1c429ae32c..11a0ef2315 100644 --- a/zephyr/projects/nissa/nivviks_generated.dts +++ b/zephyr/projects/nissa/nivviks_generated.dts @@ -11,22 +11,18 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 4>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 6>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 0>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/nissa/pujjo_generated.dts b/zephyr/projects/nissa/pujjo_generated.dts index 1c429ae32c..11a0ef2315 100644 --- a/zephyr/projects/nissa/pujjo_generated.dts +++ b/zephyr/projects/nissa/pujjo_generated.dts @@ -11,22 +11,18 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 4>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 6>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 0>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/nissa/xivu_generated.dts b/zephyr/projects/nissa/xivu_generated.dts index df10058274..28b76a7680 100644 --- a/zephyr/projects/nissa/xivu_generated.dts +++ b/zephyr/projects/nissa/xivu_generated.dts @@ -11,22 +11,18 @@ compatible = "named-adc-channels"; adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { - label = "EC_VSENSE_PP1050_PROC"; enum-name = "ADC_PP1050_PROC"; io-channels = <&adc0 4>; }; adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { - label = "EC_VSENSE_PP3300_S5"; enum-name = "ADC_PP3300_S5"; io-channels = <&adc0 6>; }; adc_temp_sensor_1: temp_sensor_1 { - label = "TEMP_SENSOR_1"; enum-name = "ADC_TEMP_SENSOR_1"; io-channels = <&adc0 0>; }; adc_temp_sensor_2: temp_sensor_2 { - label = "TEMP_SENSOR_2"; enum-name = "ADC_TEMP_SENSOR_2"; io-channels = <&adc0 1>; }; diff --git a/zephyr/projects/skyrim/adc.dts b/zephyr/projects/skyrim/adc.dts index 40fe146a06..4bd847a879 100644 --- a/zephyr/projects/skyrim/adc.dts +++ b/zephyr/projects/skyrim/adc.dts @@ -10,22 +10,18 @@ compatible = "named-adc-channels"; adc_temp_charger: temp-charger { - label = "CHARGER"; enum-name = "ADC_TEMP_SENSOR_CHARGER"; io-channels = <&adc0 1>; }; adc_temp_memory: temp-memory { - label = "MEMORY"; enum-name = "ADC_TEMP_SENSOR_MEMORY"; io-channels = <&adc0 2>; }; adc_core_imon1: core-imon1 { - label = "CORE_I"; enum-name = "ADC_CORE_IMON1"; io-channels = <&adc0 3>; }; adc_core_imon2: core-imon2 { - label = "SOC_I"; enum-name = "ADC_SOC_IMON2"; io-channels = <&adc0 4>; }; diff --git a/zephyr/projects/trogdor/lazor/adc.dts b/zephyr/projects/trogdor/lazor/adc.dts index 6f0208a1bd..4253952872 100644 --- a/zephyr/projects/trogdor/lazor/adc.dts +++ b/zephyr/projects/trogdor/lazor/adc.dts @@ -10,14 +10,12 @@ compatible = "named-adc-channels"; vbus { - label = "VBUS"; enum-name = "ADC_VBUS"; io-channels = <&adc0 1>; /* Measure VBUS through a 1/10 voltage divider */ mul = <10>; }; amon_bmon { - label = "AMON_BMON"; enum-name = "ADC_AMON_BMON"; io-channels = <&adc0 2>; /* @@ -29,7 +27,6 @@ div = <18>; }; psys { - label = "PSYS"; enum-name = "ADC_PSYS"; io-channels = <&adc0 3>; /* diff --git a/zephyr/shim/src/adc.c b/zephyr/shim/src/adc.c index aafc97cec0..5b5fb8e6fc 100644 --- a/zephyr/shim/src/adc.c +++ b/zephyr/shim/src/adc.c @@ -20,8 +20,8 @@ LOG_MODULE_REGISTER(shim_adc, LOG_LEVEL_ERR); #if HAS_NAMED_ADC_CHANNELS #define ADC_CHANNEL_COMMA(node_id) \ [ZSHIM_ADC_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ - .dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)), \ + .name = DT_NODE_FULL_NAME(node_id), \ + .dev = DEVICE_DT_GET(DT_IO_CHANNELS_CTLR(node_id)), \ .input_ch = DT_IO_CHANNELS_INPUT(node_id), \ .factor_mul = DT_PROP(node_id, mul), \ .factor_div = DT_PROP(node_id, div), \ diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index 1944fd32fa..3577acdb6f 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -343,34 +343,28 @@ compatible = "named-adc-channels"; adc_charger: charger { - label = "ADC_TEMP_SENSOR_CHARGER"; enum-name = "ADC_TEMP_SENSOR_CHARGER"; io-channels = <&adc0 0>; }; adc_pp3300_regulator: pp3300-regulator { - label = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; enum-name = "ADC_TEMP_SENSOR_PP3300_REGULATOR"; io-channels = <&adc0 1>; }; adc_ddr_soc: ddr-soc { - label = "ADC_TEMP_SENSOR_DDR_SOC"; enum-name = "ADC_TEMP_SENSOR_DDR_SOC"; io-channels = <&adc0 2>; }; adc_fan: fan { - label = "ADC_TEMP_SENSOR_FAN"; enum-name = "ADC_TEMP_SENSOR_FAN"; io-channels = <&adc0 3>; }; amon_bmon { - label = "AMON_BMON"; enum-name = "ADC_AMON_BMON"; io-channels = <&adc0 4>; mul = <1000>; div = <20>; }; psys { - label = "PSYS"; enum-name = "ADC_PSYS"; io-channels = <&adc0 5>; mul = <124000>; -- cgit v1.2.1 From b2c378e2b3295913d1d42d6ed98b8618920f205b Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 13:44:33 +0000 Subject: pinmap: drop labels from adc nodes These are not needed anymore. BRANCH=none BUG=b:239165779 TEST=go test ./... Signed-off-by: Fabio Baltieri Change-Id: I140056197db8ad692b139525cc92087bfc2ab2db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763908 Reviewed-by: Abe Levkoy --- util/pinmap/pm/generate.go | 1 - util/pinmap/pm/generate_test.go | 1 - 2 files changed, 2 deletions(-) diff --git a/util/pinmap/pm/generate.go b/util/pinmap/pm/generate.go index 835206ad7b..2a5b4c14eb 100644 --- a/util/pinmap/pm/generate.go +++ b/util/pinmap/pm/generate.go @@ -87,7 +87,6 @@ func adcConfig(out io.Writer, pin *Pin, chip Chip) { } lc := strings.ToLower(pin.Signal) fmt.Fprintf(out, "\t\tadc_%s: %s {\n", lc, lc) - fmt.Fprintf(out, "\t\t\tlabel = \"%s\";\n", pin.Signal) if len(pin.Enum) > 0 { fmt.Fprintf(out, "\t\t\tenum-name = \"%s\";\n", pin.Enum) } diff --git a/util/pinmap/pm/generate_test.go b/util/pinmap/pm/generate_test.go index 3903180b1b..bb67b957c5 100644 --- a/util/pinmap/pm/generate_test.go +++ b/util/pinmap/pm/generate_test.go @@ -85,7 +85,6 @@ func TestGenerate(t *testing.T) { compatible = "named-adc-channels"; adc_ec_adc_1: ec_adc_1 { - label = "EC_ADC_1"; enum-name = "ENUM_ADC_1"; io-channels = <&adc0 A1>; }; -- cgit v1.2.1 From 71cfa4bb71cd5f15ea9ef222d4f0c9022d0caa61 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 13:59:02 +0000 Subject: pinmap: fix lint warning Fix: /mnt/host/source/src/platform/ec/util/pinmap/pm/generate.go:195:10: should omit 2nd value from range; this loop is equivalent to `for gc := range ...` BRANCH=none BUG=none TEST=lint is happy Signed-off-by: Fabio Baltieri Change-Id: Ia11992c73e75e823a95660affdd6aff219a22361 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763909 Reviewed-by: Yuval Peress --- util/pinmap/pm/generate.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/pinmap/pm/generate.go b/util/pinmap/pm/generate.go index 2a5b4c14eb..138817dc8c 100644 --- a/util/pinmap/pm/generate.go +++ b/util/pinmap/pm/generate.go @@ -192,7 +192,7 @@ func generateEnabledNodes(out io.Writer, nodes []string) { func generateLineNames(out io.Writer, gpios map[string][]lineName) { // Sort the GPIO controller names. var gcList []string - for gc, _ := range gpios { + for gc := range gpios { gcList = append(gcList, gc) } sort.Strings(gcList) -- cgit v1.2.1 From 3f06eaf773f2c763390a06d64a6ce423795edeca Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 13:57:20 +0000 Subject: zephyr: flash: drop the label property Does not look like this was used anywhere. BRANCH=none BUG=b:239165779 TEST=zmake testall Signed-off-by: Fabio Baltieri Change-Id: Ia196dbea753f8790fd4e52a3ee505815ebd3afd5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763910 Reviewed-by: Jack Rosenthal --- zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml | 4 ---- zephyr/emul/emul_flash.c | 3 --- zephyr/include/cros/ite/it8xxx2.dtsi | 1 - zephyr/include/cros/microchip/mec1727.dtsi | 1 - zephyr/include/cros/microchip/mec172x.dtsi | 3 +-- zephyr/include/cros/nuvoton/npcx.dtsi | 3 +-- zephyr/test/drivers/overlay.dts | 1 - 7 files changed, 2 insertions(+), 14 deletions(-) diff --git a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml index b9c8a9f149..9469a02004 100644 --- a/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml +++ b/zephyr/dts/bindings/cros_flash/cros-flash-controller.yaml @@ -6,7 +6,3 @@ include: base.yaml bus: crosflash - -properties: - label: - required: true diff --git a/zephyr/emul/emul_flash.c b/zephyr/emul/emul_flash.c index 0d1b691bca..e3c72c1c3d 100644 --- a/zephyr/emul/emul_flash.c +++ b/zephyr/emul/emul_flash.c @@ -17,8 +17,6 @@ LOG_MODULE_REGISTER(emul_flash); struct flash_emul_data {}; struct flash_emul_cfg { - /** Label of the device being emulated */ - const char *dev_label; /** Pointer to run-time data */ struct flash_emul_data *data; }; @@ -121,7 +119,6 @@ static int flash_emul_init(const struct device *dev) static struct flash_emul_data flash_emul_data_##n = {}; \ \ static const struct flash_emul_cfg flash_emul_cfg_##n = { \ - .dev_label = DT_INST_LABEL(n), \ .data = &flash_emul_data_##n, \ }; \ DEVICE_DT_INST_DEFINE(n, flash_emul_init, NULL, &flash_emul_data_##n, \ diff --git a/zephyr/include/cros/ite/it8xxx2.dtsi b/zephyr/include/cros/ite/it8xxx2.dtsi index 26060c5ed4..1d54ee5e4c 100644 --- a/zephyr/include/cros/ite/it8xxx2.dtsi +++ b/zephyr/include/cros/ite/it8xxx2.dtsi @@ -77,7 +77,6 @@ fiu0: cros-flash@80000000 { compatible = "ite,it8xxx2-cros-flash"; reg = <0x80000000 0x100000>; - label = "FLASH"; }; cros_kb_raw: cros-kb-raw@f01d00 { diff --git a/zephyr/include/cros/microchip/mec1727.dtsi b/zephyr/include/cros/microchip/mec1727.dtsi index 340cff1956..f436709daa 100644 --- a/zephyr/include/cros/microchip/mec1727.dtsi +++ b/zephyr/include/cros/microchip/mec1727.dtsi @@ -75,6 +75,5 @@ fiu0: cros-flash { compatible = "microchip,xec-cros-flash"; - label = "INTERNAL_FLASH"; }; }; diff --git a/zephyr/include/cros/microchip/mec172x.dtsi b/zephyr/include/cros/microchip/mec172x.dtsi index 6833fa57d0..6dcc563f34 100644 --- a/zephyr/include/cros/microchip/mec172x.dtsi +++ b/zephyr/include/cros/microchip/mec172x.dtsi @@ -69,9 +69,8 @@ }; }; - fiu0: cros-flash{ + fiu0: cros-flash { compatible = "microchip,xec-cros-flash"; - label = "INTERNAL_FLASH"; }; /* diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi index 094f5ff901..0ccb6a7ebe 100644 --- a/zephyr/include/cros/nuvoton/npcx.dtsi +++ b/zephyr/include/cros/nuvoton/npcx.dtsi @@ -68,9 +68,8 @@ }; }; - fiu0: cros-flash{ + fiu0: cros-flash { compatible = "nuvoton,npcx-cros-flash"; - label = "INTERNAL_FLASH"; }; soc { diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index 3577acdb6f..d3686be4c8 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -765,7 +765,6 @@ cros_flash: cros-flash { compatible = "cros-ec,flash-emul"; - label = "FLASH"; }; }; -- cgit v1.2.1 From a3034288113626a86f7335925d507ea8a39e4ba0 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 14:28:06 +0000 Subject: zephyr: temp: drop label usage for temperature senors Zephyr is moving in the direction of reemoving the label property, for identifying the temperature sensor we can use the node name directly. BRANCH=none BUG=b:239165779 TEST=zmake testall TEST=flash brya, ran the "temps" console command Signed-off-by: Fabio Baltieri Change-Id: I75e47f79c74787067fe4040ba6fccb7734a33d17 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763913 Reviewed-by: Keith Short --- docs/zephyr/zephyr_temperature_sensor.md | 1 - zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml | 7 ------- zephyr/projects/brya/temp_sensors.dts | 4 ---- zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts | 5 ----- zephyr/projects/nissa/craask_overlay.dts | 2 -- zephyr/projects/nissa/joxer_overlay.dts | 3 --- zephyr/projects/nissa/nereid_overlay.dts | 3 --- zephyr/projects/nissa/nivviks_overlay.dts | 2 -- zephyr/projects/nissa/pujjo_overlay.dts | 2 -- zephyr/projects/nissa/xivu_overlay.dts | 2 -- zephyr/projects/skyrim/adc.dts | 5 +---- zephyr/projects/skyrim/skyrim.dts | 2 -- zephyr/shim/src/temp_sensors.c | 8 ++++---- zephyr/test/drivers/overlay.dts | 4 ---- 14 files changed, 5 insertions(+), 45 deletions(-) diff --git a/docs/zephyr/zephyr_temperature_sensor.md b/docs/zephyr/zephyr_temperature_sensor.md index 15e93e1e4e..e1865a2f2b 100644 --- a/docs/zephyr/zephyr_temperature_sensor.md +++ b/docs/zephyr/zephyr_temperature_sensor.md @@ -82,7 +82,6 @@ tree. This example is from [zephyr/boards/arm/brya/brya.dts](../../zephyr/boards ddr_soc { compatible = "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1_DDR_SOC"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml b/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml index 393cb1be78..66bb5b637c 100644 --- a/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml +++ b/zephyr/dts/bindings/temp/cros_ec_temp_sensor.yaml @@ -10,13 +10,6 @@ description: > compatible: cros-ec,temp-sensor properties: - label: - required: true - type: string - description: - Human-readable string describing the device (used as - device_get_binding() argument) - enum-name: type: string required: true diff --git a/zephyr/projects/brya/temp_sensors.dts b/zephyr/projects/brya/temp_sensors.dts index f4505a3bc1..559a741d43 100644 --- a/zephyr/projects/brya/temp_sensors.dts +++ b/zephyr/projects/brya/temp_sensors.dts @@ -11,7 +11,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1_DDR_SOC"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -24,7 +23,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Ambient"; enum-name = "TEMP_SENSOR_2_AMBIENT"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -37,7 +35,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_3_CHARGER"; temp_fan_off = <35>; temp_fan_max = <65>; @@ -50,7 +47,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "WWAN"; enum-name = "TEMP_SENSOR_4_WWAN"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts index a2fcacc1e1..e6a194b362 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/temp_sensor.dts @@ -11,7 +11,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Ambient"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <15>; temp_fan_max = <50>; @@ -30,7 +29,6 @@ * compatible = "cros-ec,temp-sensor-thermistor", * "cros-ec,temp-sensor"; * thermistor = < >; - * label = "Battery"; * enum-name = ""; * temp_fan_off = <15>; * temp_fan_max = <50>; @@ -45,7 +43,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "DDR"; enum-name = "TEMP_SENSOR_2"; temp_fan_off = <15>; temp_fan_max = <50>; @@ -58,7 +55,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "Skin"; enum-name = "TEMP_SENSOR_3"; temp_fan_off = <15>; temp_fan_max = <50>; @@ -71,7 +67,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V0_22K6_47K_4050B>; - label = "VR"; enum-name = "TEMP_SENSOR_4"; temp_fan_off = <15>; temp_fan_max = <50>; diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask_overlay.dts index f6d95db207..c1dac85956 100644 --- a/zephyr/projects/nissa/craask_overlay.dts +++ b/zephyr/projects/nissa/craask_overlay.dts @@ -133,7 +133,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -147,7 +146,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_2"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/nissa/joxer_overlay.dts b/zephyr/projects/nissa/joxer_overlay.dts index 1c6e1a3185..39b871129d 100644 --- a/zephyr/projects/nissa/joxer_overlay.dts +++ b/zephyr/projects/nissa/joxer_overlay.dts @@ -152,7 +152,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -166,7 +165,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_CHARGER"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -180,7 +178,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Ambient"; enum-name = "TEMP_SENSOR_AMB"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/nissa/nereid_overlay.dts b/zephyr/projects/nissa/nereid_overlay.dts index b7faf96ada..9d72da1b37 100644 --- a/zephyr/projects/nissa/nereid_overlay.dts +++ b/zephyr/projects/nissa/nereid_overlay.dts @@ -148,7 +148,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -162,7 +161,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_CHARGER"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -176,7 +174,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Ambient"; enum-name = "TEMP_SENSOR_AMB"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/nissa/nivviks_overlay.dts b/zephyr/projects/nissa/nivviks_overlay.dts index 6ac2600dbe..3929d62c3d 100644 --- a/zephyr/projects/nissa/nivviks_overlay.dts +++ b/zephyr/projects/nissa/nivviks_overlay.dts @@ -137,7 +137,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -151,7 +150,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_2"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/nissa/pujjo_overlay.dts b/zephyr/projects/nissa/pujjo_overlay.dts index cbeaaa6d60..fd75c0d083 100644 --- a/zephyr/projects/nissa/pujjo_overlay.dts +++ b/zephyr/projects/nissa/pujjo_overlay.dts @@ -137,7 +137,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -151,7 +150,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_2"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/nissa/xivu_overlay.dts b/zephyr/projects/nissa/xivu_overlay.dts index 7099b2e05a..969e327801 100644 --- a/zephyr/projects/nissa/xivu_overlay.dts +++ b/zephyr/projects/nissa/xivu_overlay.dts @@ -118,7 +118,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "DDR and SOC"; enum-name = "TEMP_SENSOR_1"; temp_fan_off = <35>; temp_fan_max = <60>; @@ -132,7 +131,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_51K1_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_2"; temp_fan_off = <35>; temp_fan_max = <60>; diff --git a/zephyr/projects/skyrim/adc.dts b/zephyr/projects/skyrim/adc.dts index 4bd847a879..3f044cecc8 100644 --- a/zephyr/projects/skyrim/adc.dts +++ b/zephyr/projects/skyrim/adc.dts @@ -32,7 +32,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Charger"; enum-name = "TEMP_SENSOR_CHARGER"; temp_host_high = <100>; temp_host_halt = <105>; @@ -43,7 +42,6 @@ compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; thermistor = <&thermistor_3V3_30K9_47K_4050B>; - label = "Memory"; enum-name = "TEMP_SENSOR_MEMORY"; temp_host_high = <100>; temp_host_halt = <105>; @@ -51,10 +49,9 @@ adc = <&adc_temp_memory>; power-good-pin = <&gpio_pg_pwr_s5>; }; - sb-tsi-sensor { + cpu { compatible = "cros-ec,temp-sensor-sb-tsi", "cros-ec,temp-sensor"; - label = "CPU"; enum-name = "TEMP_SENSOR_CPU"; port = <&i2c_soc_thermal>; temp_host_high = <100>; diff --git a/zephyr/projects/skyrim/skyrim.dts b/zephyr/projects/skyrim/skyrim.dts index 84b8e364c4..51aebe8d1d 100644 --- a/zephyr/projects/skyrim/skyrim.dts +++ b/zephyr/projects/skyrim/skyrim.dts @@ -103,7 +103,6 @@ soc-pct2075 { compatible = "cros-ec,temp-sensor-pct2075", "cros-ec,temp-sensor"; - label = "SOC"; enum-name = "TEMP_SENSOR_SOC"; pct2075-name = "PCT2075_SOC"; port = <&i2c_sensor>; @@ -119,7 +118,6 @@ amb-pct2075 { compatible = "cros-ec,temp-sensor-pct2075", "cros-ec,temp-sensor"; - label = "Ambient"; enum-name = "TEMP_SENSOR_AMB"; pct2075-name = "PCT2075_AMB"; port = <&i2c_sensor>; diff --git a/zephyr/shim/src/temp_sensors.c b/zephyr/shim/src/temp_sensors.c index e8332c16e5..11224882dd 100644 --- a/zephyr/shim/src/temp_sensors.c +++ b/zephyr/shim/src/temp_sensors.c @@ -65,7 +65,7 @@ static int thermistor_get_temp(const struct temp_sensor_t *sensor, #define TEMP_THERMISTOR(node_id) \ [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ + .name = DT_NODE_FULL_NAME(node_id), \ .idx = ZSHIM_ADC_ID(DT_PHANDLE(node_id, adc)), \ .type = TEMP_SENSOR_TYPE_BOARD, \ .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_THERMISTOR(node_id), \ @@ -93,7 +93,7 @@ static int pct2075_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) #define TEMP_PCT2075(node_id) \ [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ + .name = DT_NODE_FULL_NAME(node_id), \ .idx = ZSHIM_PCT2075_SENSOR_ID(node_id), \ .type = TEMP_SENSOR_TYPE_BOARD, \ .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_PCT2075(node_id), \ @@ -123,7 +123,7 @@ static int sb_tsi_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) #define TEMP_SB_TSI(node_id) \ [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ + .name = DT_NODE_FULL_NAME(node_id), \ .idx = 0, \ .type = TEMP_SENSOR_TYPE_CPU, \ .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_SB_TSI(node_id), \ @@ -149,7 +149,7 @@ static int tmp112_get_temp(const struct temp_sensor_t *sensor, int *temp_ptr) #define TEMP_TMP112(node_id) \ [ZSHIM_TEMP_SENSOR_ID(node_id)] = { \ - .name = DT_LABEL(node_id), \ + .name = DT_NODE_FULL_NAME(node_id), \ .idx = ZSHIM_TMP112_SENSOR_ID(node_id), \ .type = TEMP_SENSOR_TYPE_BOARD, \ .zephyr_info = GET_ZEPHYR_TEMP_SENSOR_TMP112(node_id), \ diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index d3686be4c8..7e4820dab6 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -377,7 +377,6 @@ status = "okay"; compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; - label = "TEMP_SENSOR_CHARGER"; enum-name = "TEMP_SENSOR_CHARGER"; temp_fan_off = <40>; temp_fan_max = <55>; @@ -391,7 +390,6 @@ status = "okay"; compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; - label = "TEMP_SENSOR_PP3300_REGULATOR"; enum-name = "TEMP_SENSOR_PP3300_REGULATOR"; temp_fan_off = <40>; temp_fan_max = <55>; @@ -405,7 +403,6 @@ status = "okay"; compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; - label = "TEMP_SENSOR_DDR_SOC"; enum-name = "TEMP_SENSOR_DDR_SOC"; temp_fan_off = <35>; temp_fan_max = <50>; @@ -419,7 +416,6 @@ status = "okay"; compatible = "cros-ec,temp-sensor-thermistor", "cros-ec,temp-sensor"; - label = "TEMP_SENSOR_FAN"; enum-name = "TEMP_SENSOR_FAN"; temp_fan_off = <35>; temp_fan_max = <50>; -- cgit v1.2.1 From 55450dc91a6f3cde3cd425435a62b965077f1bdc Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Fri, 15 Jul 2022 14:41:17 +0000 Subject: zephyr: motionsense: drop few label properties Drop label property from motionsensor bindings, replace it with the node name where it was used. BRANCH=none BUG=b:239165779 TEST=zmake testall Signed-off-by: Fabio Baltieri Change-Id: Ie28a25feafd4e063e0c9bd90a4a2be1b815e181d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763914 Reviewed-by: Aaron Massey --- .../motionsense/cros-ec,motionsense-mutex.yaml | 10 ---------- .../motionsense/cros-ec,motionsense-sensor-config.yaml | 9 --------- .../bindings/motionsense/motionsense-sensor-base.yaml | 8 -------- zephyr/projects/brya/motionsense.dts | 14 +------------- zephyr/projects/corsola/motionsense_kingler.dts | 11 +---------- zephyr/projects/corsola/motionsense_krabby.dts | 11 +---------- zephyr/projects/herobrine/motionsense.dts | 14 +------------- zephyr/projects/herobrine/motionsense_hoglin.dts | 14 +------------- zephyr/projects/herobrine/motionsense_villager.dts | 11 +---------- zephyr/projects/nissa/craask_motionsense.dts | 11 +---------- zephyr/projects/nissa/joxer_motionsense.dts | 11 +---------- zephyr/projects/nissa/nereid_motionsense.dts | 11 +---------- zephyr/projects/nissa/nivviks_motionsense.dts | 11 +---------- zephyr/projects/nissa/pujjo_motionsense.dts | 11 +---------- zephyr/projects/nissa/xivu_motionsense.dts | 11 +---------- zephyr/projects/skyrim/motionsense.dts | 11 +---------- zephyr/projects/trogdor/lazor/motionsense.dts | 14 +------------- zephyr/shim/src/motionsense_sensors.c | 13 +++++++------ zephyr/test/drivers/overlay.dts | 18 +----------------- 19 files changed, 22 insertions(+), 202 deletions(-) diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml index c988af258d..71413ffd26 100644 --- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml +++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-mutex.yaml @@ -9,14 +9,6 @@ child-binding: description: A mutex node is used to create an instance of mutex_t. A mutex node is referenced by one or more sensor nodes in "/motionsense-sensors" node. - properties: - label: - required: true - type: string - description: Human readable string describing the mutex. - This is a brief explanation about the mutex. - The property is not actually used in code. - # # examples: @@ -24,11 +16,9 @@ child-binding: # motionsense-mutex { # compatible = "cros-ec,motionsense-mutex"; # mutex_bma255: bma255-mutex { -# label = "BMA255_MUTEX"; # }; # # mutex_bmi260: bmi260-mutex { -# label = "BMI260_MUTEX"; # }; # }; # diff --git a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml index 68cdd15637..35e0242348 100644 --- a/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml +++ b/zephyr/dts/bindings/motionsense/cros-ec,motionsense-sensor-config.yaml @@ -26,17 +26,10 @@ child-binding: and it is used to indicate one of the 4 configurations. For example, node name ec-s0 is for SENSOR_CONFIG_EC_S0. ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; ec_rate = <1000>; }; properties: - label: - type: string - required: false - description: | - Human-readable string describing the config. - see the example the above. odr: type: int required: false @@ -55,11 +48,9 @@ child-binding: # compatible = # "cros-ec,motionsense-sensor-config"; # ec-s0 { -# label = "SENSOR_CONFIG_EC_S0"; # odr = <(10000 | ROUND_UP_FLAG)>; # }; # ec-s3 { -# label = "SENSOR_CONFIG_EC_S3"; # odr = <(10000 | ROUND_UP_FLAG)>; # }; # }; diff --git a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml index 9e4aa8e3f7..4b60ec7288 100644 --- a/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml +++ b/zephyr/dts/bindings/motionsense/motionsense-sensor-base.yaml @@ -9,13 +9,6 @@ include: base.yaml properties: status: required: true - label: - type: string - required: true - description: | - Human readable string describing the motion sensor. - This is used as the name of the motion sensor. - e.g) label = "Lid Accel"; active-mask: type: string description: indicates system power state for sensor to be active @@ -73,7 +66,6 @@ properties: # compatible = "cros-ec,bma255"; # status = "okay"; # -# label = "Lid Accel"; # active-mask = "SENSOR_ACTIVE_S0_S3"; # location = "MOTIONSENSE_LOC_LID"; # mutex = <&mutex_bma255>; diff --git a/zephyr/projects/brya/motionsense.dts b/zephyr/projects/brya/motionsense.dts index dd3f479042..2888e7082a 100644 --- a/zephyr/projects/brya/motionsense.dts +++ b/zephyr/projects/brya/motionsense.dts @@ -29,11 +29,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; mutex_lis2dw12: lis2dw12-mutex { - label = "LIS2DW12_MUTEX"; }; mutex_lsm6dso: lsm6dso-mutex { - label = "LSM6DSO_MUTEX"; }; }; @@ -139,7 +137,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -147,7 +145,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&mutex_lis2dw12>; @@ -160,11 +157,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -174,7 +169,6 @@ compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_lsm6dso>; @@ -187,12 +181,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(13000 | ROUND_UP_FLAG)>; ec-rate = <(100 * USEC_PER_MSEC)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; ec-rate = <(100 * USEC_PER_MSEC)>; }; @@ -203,7 +195,6 @@ compatible = "cros-ec,lsm6dso-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_lsm6dso>; @@ -218,7 +209,6 @@ compatible = "cros-ec,tcs3400-clear"; status = "okay"; - label = "Clear Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; port = <&i2c_sensor>; @@ -230,7 +220,6 @@ "cros-ec,motionsense-sensor-config"; ec-s0 { /* Run ALS sensor in S0 */ - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; }; }; @@ -240,7 +229,6 @@ compatible = "cros-ec,tcs3400-rgb"; status = "okay"; - label = "RGB Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; default-range = <0x10000>; /* scale = 1x, uscale = 0 */ diff --git a/zephyr/projects/corsola/motionsense_kingler.dts b/zephyr/projects/corsola/motionsense_kingler.dts index 4667635da0..354eb88c6b 100644 --- a/zephyr/projects/corsola/motionsense_kingler.dts +++ b/zephyr/projects/corsola/motionsense_kingler.dts @@ -29,10 +29,8 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -73,7 +71,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -81,7 +79,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -93,11 +90,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; }; }; @@ -107,7 +102,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -118,12 +112,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <(100 * USEC_PER_MSEC)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <0>; }; @@ -134,7 +126,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/corsola/motionsense_krabby.dts b/zephyr/projects/corsola/motionsense_krabby.dts index d369db460a..1a09b5ae40 100644 --- a/zephyr/projects/corsola/motionsense_krabby.dts +++ b/zephyr/projects/corsola/motionsense_krabby.dts @@ -27,11 +27,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: icm42607-mutex { - label = "ICM42607_MUTEX"; }; }; @@ -74,7 +72,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -82,7 +80,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -94,11 +91,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -108,7 +103,6 @@ compatible = "cros-ec,icm42607-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -119,11 +113,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -133,7 +125,6 @@ compatible = "cros-ec,icm42607-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/herobrine/motionsense.dts b/zephyr/projects/herobrine/motionsense.dts index 1d36fcbf47..ee55fa4afd 100644 --- a/zephyr/projects/herobrine/motionsense.dts +++ b/zephyr/projects/herobrine/motionsense.dts @@ -27,11 +27,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi260: bmi260-mutex { - label = "BMI260_MUTEX"; }; }; @@ -134,7 +132,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -142,7 +140,6 @@ compatible = "cros-ec,bma255"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -155,11 +152,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -169,7 +164,6 @@ compatible = "cros-ec,bmi260-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; @@ -180,11 +174,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -194,7 +186,6 @@ compatible = "cros-ec,bmi260-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; @@ -207,7 +198,6 @@ compatible = "cros-ec,tcs3400-clear"; status = "okay"; - label = "Clear Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; port = <&i2c_sensor>; @@ -219,7 +209,6 @@ "cros-ec,motionsense-sensor-config"; ec-s0 { /* Run ALS sensor in S0 */ - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; }; }; @@ -229,7 +218,6 @@ compatible = "cros-ec,tcs3400-rgb"; status = "okay"; - label = "RGB Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; default-range = <0x10000>; /* scale = 1x, uscale = 0 */ diff --git a/zephyr/projects/herobrine/motionsense_hoglin.dts b/zephyr/projects/herobrine/motionsense_hoglin.dts index 3f67347e10..17a0f0f37f 100644 --- a/zephyr/projects/herobrine/motionsense_hoglin.dts +++ b/zephyr/projects/herobrine/motionsense_hoglin.dts @@ -27,11 +27,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi260: bmi260-mutex { - label = "BMI260_MUTEX"; }; }; @@ -134,7 +132,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -142,7 +140,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -155,11 +152,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -169,7 +164,6 @@ compatible = "cros-ec,bmi260-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; @@ -180,11 +174,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -194,7 +186,6 @@ compatible = "cros-ec,bmi260-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; @@ -207,7 +198,6 @@ compatible = "cros-ec,tcs3400-clear"; status = "okay"; - label = "Clear Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; port = <&i2c_sensor>; @@ -219,7 +209,6 @@ "cros-ec,motionsense-sensor-config"; ec-s0 { /* Run ALS sensor in S0 */ - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; }; }; @@ -229,7 +218,6 @@ compatible = "cros-ec,tcs3400-rgb"; status = "okay"; - label = "RGB Light"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_CAMERA"; default-range = <0x10000>; /* scale = 1x, uscale = 0 */ diff --git a/zephyr/projects/herobrine/motionsense_villager.dts b/zephyr/projects/herobrine/motionsense_villager.dts index 92cc051a8e..1c2541c902 100644 --- a/zephyr/projects/herobrine/motionsense_villager.dts +++ b/zephyr/projects/herobrine/motionsense_villager.dts @@ -26,11 +26,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi260: bmi260-mutex { - label = "BMI260_MUTEX"; }; }; @@ -73,7 +71,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -81,7 +79,6 @@ compatible = "cros-ec,kx022"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -94,11 +91,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -108,7 +103,6 @@ compatible = "cros-ec,bmi260-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; @@ -119,11 +113,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -133,7 +125,6 @@ compatible = "cros-ec,bmi260-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; diff --git a/zephyr/projects/nissa/craask_motionsense.dts b/zephyr/projects/nissa/craask_motionsense.dts index 8f217aa945..276fc14ff2 100644 --- a/zephyr/projects/nissa/craask_motionsense.dts +++ b/zephyr/projects/nissa/craask_motionsense.dts @@ -25,11 +25,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -72,7 +70,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -83,7 +81,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -96,11 +93,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -110,7 +105,6 @@ compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -121,11 +115,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -135,7 +127,6 @@ compatible = "cros-ec,lsm6dso-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/nissa/joxer_motionsense.dts b/zephyr/projects/nissa/joxer_motionsense.dts index a5a1756c89..3f589d132f 100644 --- a/zephyr/projects/nissa/joxer_motionsense.dts +++ b/zephyr/projects/nissa/joxer_motionsense.dts @@ -24,11 +24,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -71,7 +69,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -82,7 +80,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -94,11 +91,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -108,7 +103,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -119,11 +113,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -133,7 +125,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/nissa/nereid_motionsense.dts b/zephyr/projects/nissa/nereid_motionsense.dts index a5a1756c89..3f589d132f 100644 --- a/zephyr/projects/nissa/nereid_motionsense.dts +++ b/zephyr/projects/nissa/nereid_motionsense.dts @@ -24,11 +24,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -71,7 +69,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -82,7 +80,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -94,11 +91,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -108,7 +103,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -119,11 +113,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -133,7 +125,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/nissa/nivviks_motionsense.dts b/zephyr/projects/nissa/nivviks_motionsense.dts index 662ca949ec..fc2a3e2fe4 100644 --- a/zephyr/projects/nissa/nivviks_motionsense.dts +++ b/zephyr/projects/nissa/nivviks_motionsense.dts @@ -25,11 +25,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -78,7 +76,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -89,7 +87,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -102,11 +99,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -116,7 +111,6 @@ compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -131,11 +125,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -145,7 +137,6 @@ compatible = "cros-ec,lsm6dso-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/nissa/pujjo_motionsense.dts b/zephyr/projects/nissa/pujjo_motionsense.dts index a5a1756c89..3f589d132f 100644 --- a/zephyr/projects/nissa/pujjo_motionsense.dts +++ b/zephyr/projects/nissa/pujjo_motionsense.dts @@ -24,11 +24,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -71,7 +69,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -82,7 +80,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -94,11 +91,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -108,7 +103,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -119,11 +113,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -133,7 +125,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts index 8f217aa945..276fc14ff2 100644 --- a/zephyr/projects/nissa/xivu_motionsense.dts +++ b/zephyr/projects/nissa/xivu_motionsense.dts @@ -25,11 +25,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; base_mutex: base-mutex { - label = "BASE_MUTEX"; }; }; @@ -72,7 +70,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. * TODO(b/238139272): The first entries of the array must be * accelerometers,then gyroscope. Fix this dependency in the DTS @@ -83,7 +81,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -96,11 +93,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -110,7 +105,6 @@ compatible = "cros-ec,lsm6dso-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; @@ -121,11 +115,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -135,7 +127,6 @@ compatible = "cros-ec,lsm6dso-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&base_mutex>; diff --git a/zephyr/projects/skyrim/motionsense.dts b/zephyr/projects/skyrim/motionsense.dts index 642a1cddf8..dd140bd971 100644 --- a/zephyr/projects/skyrim/motionsense.dts +++ b/zephyr/projects/skyrim/motionsense.dts @@ -26,11 +26,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi3xx: bmi3xx-mutex { - label = "BMI3XX_MUTEX"; }; }; @@ -57,7 +55,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -65,7 +63,6 @@ compatible = "cros-ec,bma4xx"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -77,12 +74,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <100>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; }; }; @@ -92,7 +87,6 @@ compatible = "cros-ec,bmi3xx-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi3xx>; @@ -104,12 +98,10 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(12500 | ROUND_UP_FLAG)>; ec-rate = <100>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(12500 | ROUND_UP_FLAG)>; }; }; @@ -119,7 +111,6 @@ compatible = "cros-ec,bmi3xx-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi3xx>; diff --git a/zephyr/projects/trogdor/lazor/motionsense.dts b/zephyr/projects/trogdor/lazor/motionsense.dts index adae7a736b..583444daec 100644 --- a/zephyr/projects/trogdor/lazor/motionsense.dts +++ b/zephyr/projects/trogdor/lazor/motionsense.dts @@ -26,11 +26,9 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; lid_mutex: lid-mutex { - label = "LID_MUTEX"; }; mutex_bmi160: bmi160-mutex { - label = "BMI160_MUTEX"; }; }; @@ -78,7 +76,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -86,7 +84,6 @@ compatible = "cros-ec,bma255"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -99,11 +96,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -113,7 +108,6 @@ compatible = "cros-ec,bmi160-accel"; status = "okay"; - label = "Base Accel"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi160>; @@ -124,11 +118,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; @@ -138,7 +130,6 @@ compatible = "cros-ec,bmi160-gyro"; status = "okay"; - label = "Base Gyro"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi160>; @@ -156,7 +147,6 @@ alt_lid_accel { compatible = "cros-ec,kx022"; status = "okay"; - label = "Lid Accel"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_LID"; mutex = <&lid_mutex>; @@ -168,11 +158,9 @@ compatible = "cros-ec,motionsense-sensor-config"; ec-s0 { - label = "SENSOR_CONFIG_EC_S0"; odr = <(10000 | ROUND_UP_FLAG)>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <(10000 | ROUND_UP_FLAG)>; }; }; diff --git a/zephyr/shim/src/motionsense_sensors.c b/zephyr/shim/src/motionsense_sensors.c index c9ab9ab85e..2480aa8477 100644 --- a/zephyr/shim/src/motionsense_sensors.c +++ b/zephyr/shim/src/motionsense_sensors.c @@ -206,12 +206,13 @@ DT_FOREACH_CHILD(SENSOR_ROT_REF_NODE, DECLARE_SENSOR_ROT_REF) (CREATE_SENSOR_CONFIG(DT_CHILD(id, configs)), )) /* Get and assign the basic information for a motion sensor */ -#define SENSOR_BASIC_INFO(id) \ - .name = DT_LABEL(id), .active_mask = DT_STRING_TOKEN(id, active_mask), \ - .location = DT_STRING_TOKEN(id, location), \ - .default_range = DT_PROP(id, default_range), \ - SENSOR_I2C_SPI_ADDR_FLAGS(id) SENSOR_MUTEX(id) SENSOR_I2C_PORT(id) \ - SENSOR_ROT_STD_REF(id) SENSOR_DRV_DATA(id) SENSOR_CONFIG(id) \ +#define SENSOR_BASIC_INFO(id) \ + .name = DT_NODE_FULL_NAME(id), \ + .active_mask = DT_STRING_TOKEN(id, active_mask), \ + .location = DT_STRING_TOKEN(id, location), \ + .default_range = DT_PROP(id, default_range), \ + SENSOR_I2C_SPI_ADDR_FLAGS(id) SENSOR_MUTEX(id) SENSOR_I2C_PORT(id) \ + SENSOR_ROT_STD_REF(id) SENSOR_DRV_DATA(id) SENSOR_CONFIG(id) \ SENSOR_INT_SIGNAL(id) SENSOR_FLAGS(id) /* Create motion sensor node with node ID */ diff --git a/zephyr/test/drivers/overlay.dts b/zephyr/test/drivers/overlay.dts index 7e4820dab6..d7eaaf1116 100644 --- a/zephyr/test/drivers/overlay.dts +++ b/zephyr/test/drivers/overlay.dts @@ -436,19 +436,15 @@ motionsense-mutex { compatible = "cros-ec,motionsense-mutex"; mutex_bma255: bma255-mutex { - label = "BMA255_MUTEX"; }; mutex_bmi260: bmi260-mutex { - label = "BMI260_MUTEX"; }; mutex_bmi160: bmi160-mutex { - label = "BMI160_MUTEX"; }; mutex_lis2dw12: lis2dw12-mutex { - label = "LIS2DW12_MUTEX"; }; }; @@ -544,7 +540,7 @@ /* * List of motion sensors that creates motion_sensors array. - * The label "lid_accel" and "base_accel" are used to indicate + * The nodelabel "lid_accel" and "base_accel" are used to indicate * motion sensor IDs for lid angle calculation. */ motionsense-sensor { @@ -552,7 +548,6 @@ compatible = "cros-ec,bma255"; status = "okay"; - label = "BMA255"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_LID"; mutex = <&mutex_bma255>; @@ -565,15 +560,12 @@ "cros-ec,motionsense-sensor-config"; ec-s0 { /* Run ALS sensor in S0 */ - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; }; ec-s3 { - label = "SENSOR_CONFIG_EC_S3"; odr = <10000>; }; ec-s5 { - label = "SENSOR_CONFIG_EC_S5"; odr = <10000>; }; }; @@ -582,7 +574,6 @@ compatible = "cros-ec,bmi260-accel"; status = "okay"; - label = "BMI260 emul accel"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; port = <&i2c_accel>; @@ -595,7 +586,6 @@ compatible = "cros-ec,bmi260-gyro"; status = "okay"; - label = "BMI260 emul gyro"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi260>; port = <&i2c_accel>; @@ -608,7 +598,6 @@ compatible = "cros-ec,bmi160-accel"; status = "okay"; - label = "BMI160 emul accel"; active-mask = "SENSOR_ACTIVE_S0_S3_S5"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi160>; @@ -622,7 +611,6 @@ compatible = "cros-ec,bmi160-gyro"; status = "okay"; - label = "BMI160 emul gyro"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_bmi160>; port = <&i2c_sensor>; @@ -635,7 +623,6 @@ compatible = "cros-ec,lis2dw12"; status = "okay"; - label = "LIS2DW12"; location = "MOTIONSENSE_LOC_BASE"; mutex = <&mutex_lis2dw12>; port = <&i2c_accel>; @@ -648,7 +635,6 @@ compatible = "cros-ec,tcs3400-clear"; status = "okay"; - label = "Clear Light"; location = "MOTIONSENSE_LOC_BASE"; port = <&i2c_sensor>; default-range = <0x10000>; @@ -659,7 +645,6 @@ "cros-ec,motionsense-sensor-config"; ec-s0 { /* Run ALS sensor in S0 */ - label = "SENSOR_CONFIG_EC_S0"; odr = <1000>; }; }; @@ -669,7 +654,6 @@ compatible = "cros-ec,tcs3400-rgb"; status = "okay"; - label = "RGB Light"; location = "MOTIONSENSE_LOC_BASE"; default-range = <0x10000>; /* scale = 1x, uscale = 0 */ drv-data = <&tcs_rgb_data>; -- cgit v1.2.1 From 2fa3b7d9b5d436d9ba8aa9d2c3128dd1444116a4 Mon Sep 17 00:00:00 2001 From: Madhurima Paruchuri Date: Mon, 18 Jul 2022 14:04:02 +0530 Subject: zephyr: drivers: displight: Remove 'frequency' from device tree Remove 'frequency' from device tree as driver is consuming that information from 'period' of PWM spec BUG=b:230093078 BRANCH=none TEST=zmake testall Signed-off-by: Madhurima Paruchuri Change-Id: Iac921a7d6aef079fce0f0315433a63d3925e7ea6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3769709 Reviewed-by: Fabio Baltieri --- zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml | 5 ----- zephyr/projects/herobrine/display.dts | 1 - zephyr/projects/trogdor/lazor/display.dts | 1 - 3 files changed, 7 deletions(-) diff --git a/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml index df51bf19dc..4c174c14cd 100644 --- a/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml +++ b/zephyr/dts/bindings/cros_displight/cros-ec,displight.yaml @@ -14,11 +14,6 @@ properties: required: true description: PWM controlling the display backlight level. - frequency: - type: int - required: true - description: PWM frequency in Hz. - generic-pwm-channel: type: int required: false diff --git a/zephyr/projects/herobrine/display.dts b/zephyr/projects/herobrine/display.dts index 6f28e7e81a..94a95193e2 100644 --- a/zephyr/projects/herobrine/display.dts +++ b/zephyr/projects/herobrine/display.dts @@ -7,7 +7,6 @@ displight { compatible = "cros-ec,displight"; pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>; - frequency = <4800>; generic-pwm-channel = <1>; }; }; diff --git a/zephyr/projects/trogdor/lazor/display.dts b/zephyr/projects/trogdor/lazor/display.dts index 6f28e7e81a..94a95193e2 100644 --- a/zephyr/projects/trogdor/lazor/display.dts +++ b/zephyr/projects/trogdor/lazor/display.dts @@ -7,7 +7,6 @@ displight { compatible = "cros-ec,displight"; pwms = <&pwm5 0 PWM_HZ(4800) PWM_POLARITY_NORMAL>; - frequency = <4800>; generic-pwm-channel = <1>; }; }; -- cgit v1.2.1 From c66c42bf01446a9d3418f5e69bcbee953ad9d3e3 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Wed, 13 Jul 2022 17:02:53 -0600 Subject: Skyrim: Apply MP2845A workaround Apply a workaround for a MP2845A problem. BRANCH=None BUG=b:238879278 TEST=on skyrim, dump register in S0 to ensure the bit is cleared Signed-off-by: Diana Z Change-Id: Id21004a165afa934e13d75ca54280bed274d0e6f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761365 Reviewed-by: Robert Zieba Commit-Queue: Robert Zieba --- zephyr/projects/skyrim/power_signals.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index c3d1826d78..ec0364519e 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -4,11 +4,14 @@ */ #include "ap_power/ap_power.h" +#include "charger.h" #include "chipset.h" #include "config.h" +#include "cros_board_info.h" #include "gpio_signal.h" #include "gpio/gpio_int.h" #include "hooks.h" +#include "i2c.h" #include "ioexpander.h" #include "power.h" #include "power/amd_x86.h" @@ -126,12 +129,36 @@ void baseboard_set_soc_pwr_pgood(enum gpio_signal unused) gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); } +/* TODO: Remove when board versions are no longer supported */ +#define MP2845A_I2C_ADDR_FLAGS 0x20 +#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69 +#define MP2854A_MFR_LOW_PWR_SEL BIT(12) + +static void setup_mp2845(void) +{ + int version; + + /* TODO: Remove when board versions are no longer supported */ + if ((cbi_get_board_version(&version) == EC_SUCCESS) && version > 3) + return; + + if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port, + MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG, + MP2854A_MFR_LOW_PWR_SEL, MASK_CLR)) + ccprints("Failed to send mp2845 workaround"); +} +DECLARE_DEFERRED(setup_mp2845); + void baseboard_s0_pgood(enum gpio_signal signal) { baseboard_set_soc_pwr_pgood(signal); /* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */ power_signal_interrupt(signal); + + /* Set up the MP2845, which is powered in S0 */ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))) + hook_call_deferred(&setup_mp2845_data, 50 * MSEC); } /* Note: signal parameter unused */ -- cgit v1.2.1 From 98cc714b48aacafa022307590b765666f45a5251 Mon Sep 17 00:00:00 2001 From: Madhurima Paruchuri Date: Mon, 18 Jul 2022 16:58:23 +0530 Subject: zephyr: drivers: kblight: Use 'period' from PWM spec inplace of 'frequency' Update driver to use 'period' from PWM spec inplace of 'frequency' BUG=b:230093078 BRANCH=none TEST=zmake testall Signed-off-by: Madhurima Paruchuri Change-Id: I260e38cb1b5eb58127a8bd617b7404ef4d037670 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768139 Reviewed-by: Fabio Baltieri --- zephyr/drivers/cros_kblight/pwm_kblight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/drivers/cros_kblight/pwm_kblight.c b/zephyr/drivers/cros_kblight/pwm_kblight.c index b6695bbecf..3d56ec1dc1 100644 --- a/zephyr/drivers/cros_kblight/pwm_kblight.c +++ b/zephyr/drivers/cros_kblight/pwm_kblight.c @@ -21,7 +21,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, #define KBLIGHT_PWM_NODE DT_INST_PWMS_CTLR(0) #define KBLIGHT_PWM_CHANNEL DT_INST_PWMS_CHANNEL(0) #define KBLIGHT_PWM_FLAGS DT_INST_PWMS_FLAGS(0) -#define KBLIGHT_PWM_PERIOD_NS (NSEC_PER_SEC / DT_INST_PROP(0, frequency)) +#define KBLIGHT_PWM_PERIOD_NS DT_INST_PWMS_PERIOD(0) static bool kblight_enabled; static int kblight_percent; -- cgit v1.2.1 From 2d7c0960c54039d474baf865d93aad0286455a5e Mon Sep 17 00:00:00 2001 From: Madhurima Paruchuri Date: Mon, 18 Jul 2022 17:04:56 +0530 Subject: zephyr: drivers: kblight: Remove 'frequency' from device tree Remove 'frequency' from device tree as driver is consuming that information from 'period' of PWM spec BUG=b:230093078 BRANCH=none TEST=zmake testall Signed-off-by: Madhurima Paruchuri Change-Id: I8c6d3728b3c4e550f4e8969f0c440d11b9595d20 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768140 Reviewed-by: Fabio Baltieri --- zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml | 5 ----- zephyr/projects/brya/keyboard.dts | 1 - zephyr/projects/herobrine/keyboard.dts | 1 - zephyr/projects/nissa/craask_overlay.dts | 3 +-- zephyr/projects/nissa/joxer_keyboard.dts | 1 - zephyr/projects/nissa/nereid_keyboard.dts | 1 - zephyr/projects/nissa/nivviks_keyboard.dts | 1 - zephyr/projects/nissa/pujjo_keyboard.dts | 1 - zephyr/projects/npcx_evb/npcx7/keyboard.dts | 1 - zephyr/projects/npcx_evb/npcx9/keyboard.dts | 1 - zephyr/projects/skyrim/keyboard.dts | 1 - zephyr/projects/trogdor/lazor/keyboard.dts | 1 - 12 files changed, 1 insertion(+), 17 deletions(-) diff --git a/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml index 33607729cd..9a57e74cba 100644 --- a/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml +++ b/zephyr/dts/bindings/keyboard/cros-ec,kblight-pwm.yaml @@ -14,11 +14,6 @@ properties: required: true description: PWM controlling the Keyboard backlight level. - frequency: - type: int - required: true - description: PWM frequency in Hz. - generic-pwm-channel: type: int required: false diff --git a/zephyr/projects/brya/keyboard.dts b/zephyr/projects/brya/keyboard.dts index 4f06764810..07dd6cd188 100644 --- a/zephyr/projects/brya/keyboard.dts +++ b/zephyr/projects/brya/keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm3 0 PWM_HZ(2400) PWM_POLARITY_NORMAL>; - frequency = <2400>; }; }; diff --git a/zephyr/projects/herobrine/keyboard.dts b/zephyr/projects/herobrine/keyboard.dts index 202b61bb4f..810763629c 100644 --- a/zephyr/projects/herobrine/keyboard.dts +++ b/zephyr/projects/herobrine/keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; generic-pwm-channel = <0>; }; }; diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask_overlay.dts index c1dac85956..e0143669a5 100644 --- a/zephyr/projects/nissa/craask_overlay.dts +++ b/zephyr/projects/nissa/craask_overlay.dts @@ -236,8 +236,7 @@ kblight { compatible = "cros-ec,kblight-pwm"; - pwms = <&pwm6 6 0 PWM_POLARITY_NORMAL>; - frequency = <10000>; + pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; }; /* diff --git a/zephyr/projects/nissa/joxer_keyboard.dts b/zephyr/projects/nissa/joxer_keyboard.dts index ae104b1ead..b9e9c21707 100644 --- a/zephyr/projects/nissa/joxer_keyboard.dts +++ b/zephyr/projects/nissa/joxer_keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/nissa/nereid_keyboard.dts b/zephyr/projects/nissa/nereid_keyboard.dts index ae104b1ead..b9e9c21707 100644 --- a/zephyr/projects/nissa/nereid_keyboard.dts +++ b/zephyr/projects/nissa/nereid_keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm0 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/nissa/nivviks_keyboard.dts b/zephyr/projects/nissa/nivviks_keyboard.dts index 71cb49ce65..fd18e1de99 100644 --- a/zephyr/projects/nissa/nivviks_keyboard.dts +++ b/zephyr/projects/nissa/nivviks_keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/nissa/pujjo_keyboard.dts b/zephyr/projects/nissa/pujjo_keyboard.dts index 71cb49ce65..fd18e1de99 100644 --- a/zephyr/projects/nissa/pujjo_keyboard.dts +++ b/zephyr/projects/nissa/pujjo_keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm6 6 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/npcx_evb/npcx7/keyboard.dts b/zephyr/projects/npcx_evb/npcx7/keyboard.dts index e2a5010952..038c2e3cce 100644 --- a/zephyr/projects/npcx_evb/npcx7/keyboard.dts +++ b/zephyr/projects/npcx_evb/npcx7/keyboard.dts @@ -32,7 +32,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/npcx_evb/npcx9/keyboard.dts b/zephyr/projects/npcx_evb/npcx9/keyboard.dts index e3ce1b1e20..55a4124b93 100644 --- a/zephyr/projects/npcx_evb/npcx9/keyboard.dts +++ b/zephyr/projects/npcx_evb/npcx9/keyboard.dts @@ -32,7 +32,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm2 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; }; }; diff --git a/zephyr/projects/skyrim/keyboard.dts b/zephyr/projects/skyrim/keyboard.dts index 216ea97045..1b6045ce6b 100644 --- a/zephyr/projects/skyrim/keyboard.dts +++ b/zephyr/projects/skyrim/keyboard.dts @@ -7,7 +7,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm1 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; - frequency = <100>; }; }; diff --git a/zephyr/projects/trogdor/lazor/keyboard.dts b/zephyr/projects/trogdor/lazor/keyboard.dts index 83cd6bced4..4e3003f6cf 100644 --- a/zephyr/projects/trogdor/lazor/keyboard.dts +++ b/zephyr/projects/trogdor/lazor/keyboard.dts @@ -27,7 +27,6 @@ kblight { compatible = "cros-ec,kblight-pwm"; pwms = <&pwm3 0 PWM_KHZ(10) PWM_POLARITY_NORMAL>; - frequency = <10000>; generic-pwm-channel = <0>; }; }; -- cgit v1.2.1 From ab4c9142a68bd64754a7239d74efc00207fee87e Mon Sep 17 00:00:00 2001 From: Patryk Duda Date: Mon, 18 Jul 2022 18:33:33 +0200 Subject: flash_fp_mcu: Add support for 5.19 kernel for brya Brya-kernelnext uses 5.19 kernel which has different name for gpio chip ('gpiochip664' instead of 'gpiochip152') and uses different gpio numbers. Update config_brya() accordingly. BUG=b:239429127 BRANCH=none TEST=Run `tast run firmware.FpFlashFpMcuHello` on brya-kernelnext and brya make sure test passes on both platforms. Change-Id: I6955f208a8a7b797e339e775a3480ff7af80e842 Signed-off-by: Patryk Duda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3770326 Reviewed-by: Tom Hughes Tested-by: Patryk Duda Commit-Queue: Patryk Duda --- util/flash_fp_mcu | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/util/flash_fp_mcu b/util/flash_fp_mcu index 5268f5e9ba..fc147aa541 100644 --- a/util/flash_fp_mcu +++ b/util/flash_fp_mcu @@ -655,15 +655,27 @@ config_brya() { # brya device to determine gpio number from pin number. # For example: GPP_D1 is ISH_GP_1 which can be queried from EDS # the pin number is 100 from the pinctrl-tigerlake.c. - # From the gpio-ranges, the gpio value is 312 + (100-99) = 313 - - readonly GPIO_CHIP="gpiochip152" - # FPMCU RST_ODL is on GPP_D1 = 312 + (100 - 99) = 313 - readonly GPIO_NRST=313 - # FPMCU BOOT0 is on GPP_D0 = 312 + (99 - 99) = 312 - readonly GPIO_BOOT0=312 - # FP_PWR_EN is on GPP_D2 = 312 + (101 - 99) = 314 - readonly GPIO_PWREN=314 + # From the gpio-ranges, the gpio value is 824 + (100-99) = 825 + + local gpiochip="gpiochip664" + # Support kernel version 5.10 during transition to 5.15+ + match_kernel_regex "^5\.10\." && gpiochip="gpiochip152" + readonly GPIO_CHIP="${gpiochip}" + + local offset=0 + # Support kernel version 5.10 during transition to 5.15+ + # v5.10 has GPIOs that are offset by -512 + match_kernel_regex "^5\.10\." && offset=512 + + # FPMCU RST_ODL is on GPP_D1 = 824 + (100 - 99) = 825 + local gpionrst=825 + readonly GPIO_NRST=$(( gpionrst - offset )) + # FPMCU BOOT0 is on GPP_D0 = 824 + (99 - 99) = 824 + local gpioboot=824 + readonly GPIO_BOOT0=$(( gpioboot - offset )) + # FP_PWR_EN is on GPP_D2 = 824 + (101 - 99) = 826 + local gpiopwren=826 + readonly GPIO_PWREN=$(( gpiopwren - offset )) } config_brask() { -- cgit v1.2.1 From 41bf79a1ae9a4c107fbf364aa1ab0f833e4b94b9 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 15 Jul 2022 15:18:08 -0700 Subject: core: Add "end" to linker scripts _sbrk in newlib (embedded C standard library implementation) expects the "end" symbol to point to the start of free memory. BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I9f206e2ed5f050d92b579e0b65b05be40f929093 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3766504 Reviewed-by: Abe Levkoy --- core/cortex-m/ec.lds.S | 6 ++++++ core/cortex-m0/ec.lds.S | 6 ++++++ core/minute-ia/ec.lds.S | 6 ++++++ core/nds32/ec.lds.S | 6 ++++++ core/riscv-rv32i/ec.lds.S | 6 ++++++ 5 files changed, 30 insertions(+) diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 896e49097b..ac3442cafe 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -460,6 +460,12 @@ SECTIONS #endif __data_end = .; + /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + /* * Shared memory buffer must be at the end of preallocated * RAM, so it can expand to use all the remaining RAM. diff --git a/core/cortex-m0/ec.lds.S b/core/cortex-m0/ec.lds.S index 3321dd1b08..80c30b8d38 100644 --- a/core/cortex-m0/ec.lds.S +++ b/core/cortex-m0/ec.lds.S @@ -294,6 +294,12 @@ SECTIONS . = ALIGN(4); __data_end = .; + /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + /* * Shared memory buffer must be at the end of preallocated * RAM, so it can expand to use all the remaining RAM. diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S index 60239d3680..253badd9b5 100644 --- a/core/minute-ia/ec.lds.S +++ b/core/minute-ia/ec.lds.S @@ -220,6 +220,12 @@ SECTIONS __bss_end = .; __bss_size_words = ABSOLUTE((__bss_end - __bss_start) / 4); + /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + /* * Shared memory buffer must be at the end of * preallocated RAM, so it can expand to use all the diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 084c6f6b64..87e87709de 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -266,6 +266,12 @@ SECTIONS . = ALIGN(4); __bss_end = .; + /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + /* * Shared memory buffer must be at the end of preallocated RAM, * so it can expand to use all the remaining RAM. diff --git a/core/riscv-rv32i/ec.lds.S b/core/riscv-rv32i/ec.lds.S index 24b2fb68ef..c42ec29df8 100644 --- a/core/riscv-rv32i/ec.lds.S +++ b/core/riscv-rv32i/ec.lds.S @@ -337,6 +337,12 @@ SECTIONS . = ALIGN(4); __bss_end = .; + /* + * _sbrk in newlib expects "end" symbol to point to start of + * free memory. + */ + end = .; + /* * Shared memory buffer must be at the end of preallocated RAM, * so it can expand to use all the remaining RAM. -- cgit v1.2.1 From f5b5e93e2f246bb5eec2d20c0ffd7a064de96d50 Mon Sep 17 00:00:00 2001 From: Andrew McRae Date: Mon, 18 Jul 2022 17:13:13 +1000 Subject: pwrseq: gpio: Use output state for GPIO get on outputs When retrieving the state of an output GPIO, do not read the physical level on the pin, but instead read the configured state (by reading the GPIO configuration). Open drain outputs sometimes use low voltages, and so reading the physical level on the pin may indicate a 0 for an output that has been set to 1. The stored configuration of the GPIO does not include the GPIO_ACTIVE_LOW flag, so this is explicitly checked, and the state inverted if necessary. BUG=none TEST=zmake build nivviks; flash & run BRANCH=none Signed-off-by: Andrew McRae Change-Id: Idb2cb1c6b1b0902189e1fd1471cf9ca30c2711dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3769706 Reviewed-by: Peter Marheine --- zephyr/subsys/ap_pwrseq/Kconfig | 3 +++ zephyr/subsys/ap_pwrseq/signal_gpio.c | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/zephyr/subsys/ap_pwrseq/Kconfig b/zephyr/subsys/ap_pwrseq/Kconfig index 6f39906bf2..1845baa2bd 100644 --- a/zephyr/subsys/ap_pwrseq/Kconfig +++ b/zephyr/subsys/ap_pwrseq/Kconfig @@ -5,12 +5,15 @@ menuconfig AP_PWRSEQ bool "AP Power sequencing support" select HAS_TASK_POWERBTN + select GPIO_GET_CONFIG help Enables AP power sequencing support with embedded controller. This includes normal shutdown, critical shutdown and reset handling. Enabling this automatically enables HAS_TASK_POWERBTN since this task is required to handle power button pressed/released by user. + Enabling this also enables retrieving the GPIO config feature + so that the value of output GPIOs can be determined. if AP_PWRSEQ diff --git a/zephyr/subsys/ap_pwrseq/signal_gpio.c b/zephyr/subsys/ap_pwrseq/signal_gpio.c index f4b74fd3be..4d21657624 100644 --- a/zephyr/subsys/ap_pwrseq/signal_gpio.c +++ b/zephyr/subsys/ap_pwrseq/signal_gpio.c @@ -100,6 +100,28 @@ int power_signal_gpio_get(enum pwr_sig_gpio index) if (index < 0 || index >= ARRAY_SIZE(gpio_config)) { return -EINVAL; } + /* + * Getting the current value of an output is + * done by retrieving the config and checking what the + * output state has been set to, not by reading the + * physical level of the pin (open drain outputs + * may have a low voltage). + */ + if (gpio_config[index].output) { + int rv; + gpio_flags_t flags; + + rv = gpio_pin_get_config_dt(&spec[index], &flags); + if (rv != 0) { + return rv; + } + rv = (flags & GPIO_OUTPUT_INIT_HIGH) ? 1 : 0; + /* If active low signal, invert it */ + if (spec[index].dt_flags & GPIO_ACTIVE_LOW) { + rv = !rv; + } + return rv; + } return gpio_pin_get_dt(&spec[index]); } -- cgit v1.2.1 From 1804103b5899ea2897ba12e589d931467f67dbc9 Mon Sep 17 00:00:00 2001 From: Parth Malkan Date: Mon, 18 Jul 2022 17:39:40 -0700 Subject: prism: rgbkbd: Fix space key LED mapping LED mapping for space key is off, which makes the right most LED on the space key doesn't change color. This patch fixes the mapping. BRANCH=none BUG=b:238899691 TEST=ectool --device 18d1:5022 61 0xff0000 Signed-off-by: Parth Malkan Change-Id: Ibe4fcc68a34bb5b366882bce43c2c7e2250c60da Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3770682 Reviewed-by: YH Lin Commit-Queue: YH Lin --- board/prism/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/prism/board.c b/board/prism/board.c index a19ea1221f..29a2a92027 100644 --- a/board/prism/board.c +++ b/board/prism/board.c @@ -170,7 +170,7 @@ const uint8_t rgbkbd_map[] = { LED(15, 0), DELM, /* 59: power */ LED(17, 2), LED(18, 2), LED(19, 2), DELM, /* 60: L-alt */ LED(17, 3), LED(18, 3), LED(19, 3), LED(20, 3), - LED(21, 3), DELM, /* 61: space */ + LED(21, 3), LED(16, 2), DELM, /* 61: space */ LED(20, 2), DELM, /* 62: R-alt */ DELM, /* 63: (null) */ LED(21, 2), DELM, /* 64: R-ctrl */ -- cgit v1.2.1 From 573f2f4020d93b93f05e9b5ad01dad81c05ba983 Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Mon, 18 Jul 2022 14:34:21 +0800 Subject: BB retimer: Modify bb retimer mutex Modify mutexing access to the BB_RETIMER_REG_CONNECTION_STATE register. BUG=b:233975818 BRANCH=None TEST=build make -j BOARD=Banshee pass Signed-off-by: johnwc_yeh Change-Id: If92c5e989ee9bc9e26305807383fac63db2d09ca Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768134 Reviewed-by: Elthan Huang Reviewed-by: Diana Z --- driver/retimer/bb_retimer.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/driver/retimer/bb_retimer.c b/driver/retimer/bb_retimer.c index add245cb08..10607a4a58 100644 --- a/driver/retimer/bb_retimer.c +++ b/driver/retimer/bb_retimer.c @@ -10,6 +10,7 @@ #include "common.h" #include "console.h" #include "gpio.h" +#include "hooks.h" #include "i2c.h" #include "task.h" #include "timer.h" @@ -41,7 +42,7 @@ * Mutex for BB_RETIMER_REG_CONNECTION_STATE register, which can be * accessed from multiple tasks. */ -K_MUTEX_DEFINE(bb_retimer_state_mutex); +static mutex_t bb_retimer_lock[CONFIG_USB_PD_PORT_MAX_COUNT]; /** * Utility functions @@ -387,7 +388,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, /* This driver does not use host command ACKs */ *ack_required = false; - mutex_lock(&bb_retimer_state_mutex); + mutex_lock(&bb_retimer_lock[port]); /* * Bit 0: DATA_CONNECTION_PRESENT @@ -475,7 +476,7 @@ static int retimer_set_state(const struct usb_mux *me, mux_state_t mux_state, /* Writing the register4 */ rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, set_retimer_con); - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); return rv; } @@ -483,15 +484,16 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, bool *ack_required) { uint32_t retimer_con_reg = 0; + int port = me->usb_port; /* This driver does not use host command ACKs */ *ack_required = false; - mutex_lock(&bb_retimer_state_mutex); + mutex_lock(&bb_retimer_lock[port]); if (bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, &retimer_con_reg) != EC_SUCCESS) { - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); return; } /* @@ -529,31 +531,44 @@ void bb_retimer_hpd_update(const struct usb_mux *me, mux_state_t mux_state, /* Writing the register4 */ bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, retimer_con_reg); - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); } void bb_retimer_set_usb3(const struct usb_mux *me, bool enable) { int rv; uint32_t reg_val = 0; + int port = me->usb_port; - mutex_lock(&bb_retimer_state_mutex); + mutex_lock(&bb_retimer_lock[port]); rv = bb_retimer_read(me, BB_RETIMER_REG_CONNECTION_STATE, ®_val); if (rv != EC_SUCCESS) { - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); return; } /* Bit 5: USB_3_CONNECTION */ WRITE_BIT(reg_val, 5, enable); rv = bb_retimer_write(me, BB_RETIMER_REG_CONNECTION_STATE, reg_val); if (rv != EC_SUCCESS) { - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); return; } - mutex_unlock(&bb_retimer_state_mutex); + mutex_unlock(&bb_retimer_lock[port]); +} + +#ifdef CONFIG_ZEPHYR +static void init_retimer_mutexes(void) +{ + int port; + + for (port = 0; port < CONFIG_USB_PD_PORT_MAX_COUNT; port++) { + k_mutex_init(&bb_retimer_lock[port]); + } } +DECLARE_HOOK(HOOK_INIT, init_retimer_mutexes, HOOK_PRIO_FIRST); +#endif static int retimer_low_power_mode(const struct usb_mux *me) { -- cgit v1.2.1 From 4eed38ea2d34c19934334c205ae0328067d0228b Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Fri, 8 Jul 2022 17:00:45 +0800 Subject: usb_pd_dpm: fix sink_max_pdo_requested The operator should be a '&' for testing if the port provides max current of the PDO. BUG=b:236430560 TEST=pass TDA.2.3.1 POW SRC LOAD PC sub item: Tester could not increase the load current, Please check the UUT VBUS voltage behavior in the capture BRANCH=none Change-Id: I8e7b4662550be2eab84adcffe2bc68923e66347c Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3752433 Reviewed-by: Diana Z Commit-Queue: Eric Yilun Lin Tested-by: Eric Yilun Lin --- common/usbc/usb_pd_dpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/usbc/usb_pd_dpm.c b/common/usbc/usb_pd_dpm.c index 793206b623..91b4286d59 100644 --- a/common/usbc/usb_pd_dpm.c +++ b/common/usbc/usb_pd_dpm.c @@ -822,7 +822,7 @@ void dpm_evaluate_request_rdo(int port, uint32_t rdo) return; op_ma = (rdo >> 10) & 0x3FF; - if ((BIT(port) && sink_max_pdo_requested) && (op_ma <= 150)) { + if ((BIT(port) & sink_max_pdo_requested) && (op_ma <= 150)) { /* * sink_max_pdo_requested will be set when we get 5V/3A sink * capability from port partner. If port partner only request -- cgit v1.2.1 From e8c32a46aff3cc81751979ff46df4bfb3277f53b Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Wed, 6 Jul 2022 18:44:44 -0700 Subject: rex: minimal starting project This CL is mostly a copy of the minimal zephyr project as a starting point for the Rex EC project. BRANCH=none BUG=b:239451279 TEST=zmake build rex Signed-off-by: Scott Collyer Change-Id: I48e87e216859deace5d52faad4d6a84bf8dcf800 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3767858 Tested-by: Scott Collyer Reviewed-by: Fabio Baltieri Commit-Queue: Scott Collyer --- zephyr/projects/rex/BUILD.py | 30 ++++++++++++++++++++++++++++++ zephyr/projects/rex/CMakeLists.txt | 9 +++++++++ zephyr/projects/rex/Kconfig | 11 +++++++++++ zephyr/projects/rex/include/gpio_map.h | 9 +++++++++ zephyr/projects/rex/prj.conf | 18 ++++++++++++++++++ zephyr/projects/rex/prj_rex.conf | 6 ++++++ zephyr/projects/rex/rex.dts | 28 ++++++++++++++++++++++++++++ 7 files changed, 111 insertions(+) create mode 100644 zephyr/projects/rex/BUILD.py create mode 100644 zephyr/projects/rex/CMakeLists.txt create mode 100644 zephyr/projects/rex/Kconfig create mode 100644 zephyr/projects/rex/include/gpio_map.h create mode 100644 zephyr/projects/rex/prj.conf create mode 100644 zephyr/projects/rex/prj_rex.conf create mode 100644 zephyr/projects/rex/rex.dts diff --git a/zephyr/projects/rex/BUILD.py b/zephyr/projects/rex/BUILD.py new file mode 100644 index 0000000000..caa4854935 --- /dev/null +++ b/zephyr/projects/rex/BUILD.py @@ -0,0 +1,30 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Rex Projects.""" + + +def register_variant(project_name, extra_kconfig_files=()): + """Register a variant of rex.""" + register_npcx_project( + project_name=project_name, + zephyr_board="npcx9m3f", + dts_overlays=[ + # Common to all projects. + here + / "rex.dts" + ], + kconfig_files=[ + # Common to all projects. + here / "prj.conf", + # Project-specific KConfig customization. + *extra_kconfig_files, + ], + ) + + +register_variant( + project_name="rex", + extra_kconfig_files=[here / "prj_rex.conf"], +) diff --git a/zephyr/projects/rex/CMakeLists.txt b/zephyr/projects/rex/CMakeLists.txt new file mode 100644 index 0000000000..8a0349bb24 --- /dev/null +++ b/zephyr/projects/rex/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +cmake_minimum_required(VERSION 3.20.5) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(ec) + +zephyr_include_directories("${CMAKE_CURRENT_SOURCE_DIR}/include") diff --git a/zephyr/projects/rex/Kconfig b/zephyr/projects/rex/Kconfig new file mode 100644 index 0000000000..4fc561ab4f --- /dev/null +++ b/zephyr/projects/rex/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +config BOARD_REX + bool "Google Rex Baseboard" + help + Build Google Rex reference board. The board uses Nuvoton + NPCX9 chip as the EC. + +source "Kconfig.zephyr" diff --git a/zephyr/projects/rex/include/gpio_map.h b/zephyr/projects/rex/include/gpio_map.h new file mode 100644 index 0000000000..886e7d1ebf --- /dev/null +++ b/zephyr/projects/rex/include/gpio_map.h @@ -0,0 +1,9 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __ZEPHYR_GPIO_MAP_H +#define __ZEPHYR_GPIO_MAP_H + +#endif /* __ZEPHYR_GPIO_MAP_H */ diff --git a/zephyr/projects/rex/prj.conf b/zephyr/projects/rex/prj.conf new file mode 100644 index 0000000000..0b810096b4 --- /dev/null +++ b/zephyr/projects/rex/prj.conf @@ -0,0 +1,18 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_PLATFORM_EC=y +CONFIG_CROS_EC=y +CONFIG_SHIMMED_TASKS=y +CONFIG_SYSCON=y + +# Disable default features we don't want in a minimal example. +CONFIG_ADC=n +CONFIG_I2C=n +CONFIG_PWM=n +CONFIG_PLATFORM_EC_BACKLIGHT_LID=n +CONFIG_PLATFORM_EC_KEYBOARD=n +CONFIG_PLATFORM_EC_POWER_BUTTON=n +CONFIG_PLATFORM_EC_SWITCH=n +CONFIG_PLATFORM_EC_VBOOT_EFS2=n diff --git a/zephyr/projects/rex/prj_rex.conf b/zephyr/projects/rex/prj_rex.conf new file mode 100644 index 0000000000..05c9c27d11 --- /dev/null +++ b/zephyr/projects/rex/prj_rex.conf @@ -0,0 +1,6 @@ +# Copyright 2022 The ChromiumOS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +# Rex reference-board-specific Kconfig settings. +CONFIG_BOARD_REX=y diff --git a/zephyr/projects/rex/rex.dts b/zephyr/projects/rex/rex.dts new file mode 100644 index 0000000000..d3f4c7f27b --- /dev/null +++ b/zephyr/projects/rex/rex.dts @@ -0,0 +1,28 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &ec_wp_l; + }; + + named-gpios { + compatible = "named-gpios"; + + ec_wp_l: write-protect { + gpios = <&gpioa 0 GPIO_INPUT>; + }; + + gpio_ec_entering_rw: ec_entering_rw { + enum-name = "GPIO_ENTERING_RW"; + }; + }; +}; + +&cros_kb_raw { + status = "okay"; + pinctrl-0 = <>; + pinctrl-names = "default"; +}; -- cgit v1.2.1 From 2911d8fd06d986916a0b7a2329c473c54ae5297d Mon Sep 17 00:00:00 2001 From: johnwc_yeh Date: Mon, 11 Jul 2022 10:26:01 +0800 Subject: Banshee: Config BBR USB3 bit for USB card port in suspend/resume For some chromebooks design, there are expansion card (typeC to typeA) communicate with TCPC through CC line, when the TypeA card connect to chromebook the USB3_Connection bit would be enable even no connect USBA device. It will increase BBR power consumption, so clear 'USB3_Connection' bit in S0ix and enable when return S0. Suspend -> Set BBR USB3 connection bit to 0 for port that is in USB3 connection. Resume -> Unplug any type-c device in suspend will wake up the system in current Chrome OS, so enable USB3_Connection bit should be perfromed for another resume case which is USB3 device still in connection. BUG=b:233975818 BRANCH=None TEST=Test on Banshee, BBR USB3 connection bit is correct in S0/S0ix state. Signed-off-by: johnwc_yeh Change-Id: Ie6cb5d64578663a8e93378e3c78359e7cdd19327 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754781 Reviewed-by: Elthan Huang Reviewed-by: Elmo Lan Reviewed-by: Diana Z --- board/banshee/board.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/board/banshee/board.c b/board/banshee/board.c index c751400d79..0814f35a9b 100644 --- a/board/banshee/board.c +++ b/board/banshee/board.c @@ -16,6 +16,7 @@ #include "hooks.h" #include "driver/als_tcs3400.h" #include "driver/charger/isl9241.h" +#include "driver/retimer/bb_retimer.h" #include "fw_config.h" #include "hooks.h" #include "keyboard_customization.h" @@ -33,15 +34,38 @@ #define CPRINTF(format, args...) cprintf(CC_CHARGER, format, ##args) #define CPRINTS(format, args...) cprints(CC_CHARGER, format, ##args) +/* + * USBA card connect to chromebook the USB_3_CONNECTION + * bit would be enable. + * It will increase BBR power consumption, so clear + * USB3_Connection bit in S0ix and enable when return S0. + */ +void set_bb_retimer_usb3_state(bool enable) +{ + mux_state_t mux_state = 0; + + for (int i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) { + const struct usb_mux *mux = &usb_muxes[i]; + + mux_state = usb_mux_get(i); + + if ((mux_state & USB_PD_MUX_USB_ENABLED)) { + bb_retimer_set_usb3(mux, enable); + } + } +} + /* Called on AP S3 -> S0 transition */ static void board_chipset_resume(void) { + set_bb_retimer_usb3_state(true); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); /* Called on AP S0 -> S3 transition */ static void board_chipset_suspend(void) { + set_bb_retimer_usb3_state(false); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); -- cgit v1.2.1 From cb73a82a286ee3ecf241e2845570025b356072dc Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Tue, 12 Jul 2022 14:58:06 +0800 Subject: volmar: Update thermal policy Modify thermal and fan configuration BUG=b:221094660 BRANCH=none TEST=Thermal team verified thermal policy is expected. Signed-off-by: Yu-An Chen Change-Id: I9b8901d5932e843bb52bc9b0e32a97060aa3a36b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3755244 Reviewed-by: caveh jalali Commit-Queue: caveh jalali --- board/volmar/fans.c | 6 +++--- board/volmar/sensors.c | 26 +++++++++++++------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/board/volmar/fans.c b/board/volmar/fans.c index 7cc1737775..46d64727e2 100644 --- a/board/volmar/fans.c +++ b/board/volmar/fans.c @@ -38,9 +38,9 @@ static const struct fan_conf fan_conf_0 = { * boards as well. */ static const struct fan_rpm fan_rpm_0 = { - .rpm_min = 0, - .rpm_start = 5000, - .rpm_max = 6500, + .rpm_min = 3000, + .rpm_start = 3000, + .rpm_max = 6000, }; const struct fan_t fans[FAN_CH_COUNT] = { diff --git a/board/volmar/sensors.c b/board/volmar/sensors.c index 8b5dbb987c..b6c2a39a45 100644 --- a/board/volmar/sensors.c +++ b/board/volmar/sensors.c @@ -77,10 +77,10 @@ BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ + [EC_TEMP_THRESH_HIGH] = C_TO_K(70), \ }, \ - .temp_fan_off = C_TO_K(25), \ - .temp_fan_max = C_TO_K(50), \ + .temp_fan_off = C_TO_K(30), \ + .temp_fan_max = C_TO_K(84), \ } __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; @@ -103,14 +103,14 @@ __maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU; #define THERMAL_FAN \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ + [EC_TEMP_THRESH_HIGH] = 0, \ + [EC_TEMP_THRESH_HALT] = 0, \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ + [EC_TEMP_THRESH_HIGH] = 0, \ }, \ - .temp_fan_off = C_TO_K(25), \ - .temp_fan_max = C_TO_K(50), \ + .temp_fan_off = 0, \ + .temp_fan_max = 0, \ } __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; @@ -131,14 +131,14 @@ __maybe_unused static const struct ec_thermal_config thermal_fan = THERMAL_FAN; #define THERMAL_CHARGER \ { \ .temp_host = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(75), \ - [EC_TEMP_THRESH_HALT] = C_TO_K(85), \ + [EC_TEMP_THRESH_HIGH] = 0, \ + [EC_TEMP_THRESH_HALT] = 0, \ }, \ .temp_host_release = { \ - [EC_TEMP_THRESH_HIGH] = C_TO_K(65), \ + [EC_TEMP_THRESH_HIGH] = 0, \ }, \ - .temp_fan_off = C_TO_K(25), \ - .temp_fan_max = C_TO_K(50), \ + .temp_fan_off = 0, \ + .temp_fan_max = 0, \ } __maybe_unused static const struct ec_thermal_config thermal_charger = THERMAL_CHARGER; -- cgit v1.2.1 From 158bd971cc91dd115241155a8dd5af076381b0ef Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Tue, 19 Jul 2022 14:24:23 +1000 Subject: it8xxx2: temporarily disable I2C CQ mode The Zephyr change that added support for CQ mode has a bug that causes errors in some transaction types. Disable CQ mode until the fix for that bug lands. BUG=b:227415000 TEST=I2C errors stopped occurring BRANCH=none Signed-off-by: Peter Marheine Change-Id: I57e67cc592d25935494cd7a239c583b22b056568 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3771362 Commit-Queue: Andrew McRae Reviewed-by: Andrew McRae --- zephyr/boards/riscv/it8xxx2/it81202bx_defconfig | 4 ++++ zephyr/boards/riscv/it8xxx2/it81302bx_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig index 59fc3a1eaf..3cc784551b 100644 --- a/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it81202bx_defconfig @@ -32,3 +32,7 @@ CONFIG_WATCHDOG=y # BBRAM CONFIG_BBRAM=y + +# TODO(b:227415000) re-enable once +# https://github.com/zephyrproject-rtos/zephyr/pull/47934 is merged. +CONFIG_I2C_IT8XXX2_CQ_MODE=n diff --git a/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig index ae66217f86..2941f2abe8 100644 --- a/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig +++ b/zephyr/boards/riscv/it8xxx2/it81302bx_defconfig @@ -32,3 +32,7 @@ CONFIG_WATCHDOG=y # BBRAM CONFIG_BBRAM=y + +# TODO(b:227415000) re-enable once +# https://github.com/zephyrproject-rtos/zephyr/pull/47934 is merged. +CONFIG_I2C_IT8XXX2_CQ_MODE=n -- cgit v1.2.1 From b5c920ef94202c7092c1cd1176c03f214f58909a Mon Sep 17 00:00:00 2001 From: Leila Lin Date: Mon, 18 Jul 2022 14:06:00 +0800 Subject: Xivu: Modify motionsense rotation matrix Modify motionsense rotation matrix for xivu project. BUG=b:237432830 BRANCH=none TEST=zmake build xivu success. Signed-off-by: Leila Lin Change-Id: I98722fd685ea46c24f7bc8e674699f7c1fb1c886 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768132 Reviewed-by: Elmo Lan Reviewed-by: Peter Marheine Commit-Queue: LeilaCY Lin Tested-by: LeilaCY Lin --- zephyr/projects/nissa/xivu_motionsense.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/zephyr/projects/nissa/xivu_motionsense.dts b/zephyr/projects/nissa/xivu_motionsense.dts index 276fc14ff2..1230cc98bc 100644 --- a/zephyr/projects/nissa/xivu_motionsense.dts +++ b/zephyr/projects/nissa/xivu_motionsense.dts @@ -35,14 +35,14 @@ motionsense-rotation-ref { compatible = "cros-ec,motionsense-rotation-ref"; lid_rot_ref: lid-rotation-ref { - mat33 = <(-1) 0 0 - 0 1 0 + mat33 = <0 1 0 + 1 0 0 0 0 (-1)>; }; base_rot_ref: base-rotation-ref { - mat33 = <(-1) 0 0 - 0 (-1) 0 + mat33 = <0 (-1) 0 + 1 0 0 0 0 1>; }; }; -- cgit v1.2.1 From 944a72069d8efd7f2d53ea3a1dd32d0dcae011f9 Mon Sep 17 00:00:00 2001 From: jeffrey_lin Date: Mon, 18 Jul 2022 10:50:25 +0800 Subject: tentacruel: Implement LED behavior with LED DTS settings. Implement LED DTS settings. BUG=b:237593733 TEST=use `battfake` in EC console, set battery to different level and check LED behavior matches to the DTS settings. BRANCH=None Signed-off-by: jeffrey_lin Change-Id: I0fdd4427dd2f4455e54f7a6f6f865fd621f2d12f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3768127 Reviewed-by: Ting Shen --- zephyr/projects/corsola/led_tentacruel.dts | 127 +++++++++++++++++++++-------- 1 file changed, 95 insertions(+), 32 deletions(-) diff --git a/zephyr/projects/corsola/led_tentacruel.dts b/zephyr/projects/corsola/led_tentacruel.dts index b2233033e0..8912609eab 100644 --- a/zephyr/projects/corsola/led_tentacruel.dts +++ b/zephyr/projects/corsola/led_tentacruel.dts @@ -1,55 +1,118 @@ -/* Copyright 2022 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The ChromiumOS Authors. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #include "led_it81202_base.dtsi" -&led_colors { - bat-power-state-discharge-s0 { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S0"; +/ { + led_colors: led-colors { + compatible = "cros-ec,led-colors"; - color-0 { - led-color = <&color_battery_white>; + /* Tentacruel LED bat charge */ + bat-power-state-charge { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= Empty, <= 94%) */ + batt-lvl = ; + color-0 { + led-color = <&color_battery_amber>; + }; + }; + + bat-power-state-charge-near-full { + charge-state = "PWR_STATE_CHARGE"; + /* Battery percent range (>= 95%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_NEAR_FULL - 2) + BATTERY_LEVEL_FULL>; + color-0 { + led-color = <&color_battery_white>; + }; }; - }; - bat-power-state-discharge-s3 { - charge-state = "PWR_STATE_DISCHARGE"; - chipset-state = "POWER_S3"; + /* Tentacruel LED bat discharge */ + bat-power-state-discharge { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery percent range (>= 11%, <= Full) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; - color-0 { - led-color = <&color_battery_white>; - period-ms = <1000>; + color-0 { + led-color = <&color_battery_white>; + }; }; - color-1 { - led-color = <&color_battery_off>; - period-ms = <3000>; + bat-power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; }; - }; - bat-power-state-error-s3 { - charge-state = "PWR_STATE_ERROR"; - chipset-state = "POWER_S3"; + bat-power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + color-0 { + led-color = <&color_battery_off>; + }; + }; + + /* Tentacruel LED bat error */ + bat-power-state-error { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + + color-0 { + led-color = <&color_battery_amber>; + period-ms = <1000>; + }; - color-0 { - led-color = <&color_battery_white>; - period-ms = <1000>; + color-1 { + led-color = <&color_battery_off>; + period-ms = <1000>; + }; }; - color-1 { - led-color = <&color_battery_off>; - period-ms = <1000>; + bat-power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + + color-0 { + led-color = <&color_battery_white>; + period-ms = <1000>; + }; + + color-1 { + led-color = <&color_battery_off>; + period-ms = <3000>; + }; + }; + + bat-power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_battery_off>; + }; }; }; - bat-power-state-error-s5 { - charge-state = "PWR_STATE_ERROR"; - chipset-state = "POWER_S5"; + pwm-led-pins { + compatible = "cros-ec,pwm-led-pins"; - color-0 { - led-color = <&color_battery_off>; + /* Overwrite Power LED white to off */ + color_power_white: color-power-white { + led-color = "LED_WHITE"; + led-id = "EC_LED_ID_POWER_LED"; + led-pins = <&led_power_white 0>; }; }; }; -- cgit v1.2.1 From 29791a4f18afed00ee11c76febc48808bccfbda7 Mon Sep 17 00:00:00 2001 From: Tomasz Michalec Date: Fri, 15 Jul 2022 12:46:34 +0200 Subject: zephyr: tests: Fix bb_retimer test conflict with PD task Some bb_retimer tests require to set a PD data role. When the PD task is running, it is possible that the data role changes after the test sets it. To prevent that bb_retimer tests that require specific PD data role are run before tasks are started. BUG=b:238880607 TEST=zmake -D test test-drivers BRANCH=None Signed-off-by: Tomasz Michalec Change-Id: Ia5f59a5c63f5089eeb4984672a786b96b0845877 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3763902 Tested-by: Tomasz Michalec Reviewed-by: Al Semjonovs Commit-Queue: Tomasz Michalec --- zephyr/test/drivers/src/bb_retimer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/zephyr/test/drivers/src/bb_retimer.c b/zephyr/test/drivers/src/bb_retimer.c index 97dc621948..a9db2eb052 100644 --- a/zephyr/test/drivers/src/bb_retimer.c +++ b/zephyr/test/drivers/src/bb_retimer.c @@ -40,7 +40,7 @@ ZTEST_USER(bb_retimer, test_bb_is_fw_update_capable) } /** Test is retimer fw update capable function. */ -ZTEST_USER(bb_retimer, test_bb_set_state) +ZTEST_USER(bb_retimer_no_tasks, test_bb_set_state) { struct pd_discovery *disc; uint32_t conn, exp_conn; @@ -67,6 +67,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) /* Set UFP role for whole test */ tc_set_data_role(USBC_PORT_C1, PD_ROLE_UFP); + zassume_equal(PD_ROLE_UFP, pd_get_data_role(USBC_PORT_C1), NULL); /* Test none mode */ bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678); @@ -194,7 +195,7 @@ ZTEST_USER(bb_retimer, test_bb_set_state) } /** Test setting different options for DFP role */ -ZTEST_USER(bb_retimer, test_bb_set_dfp_state) +ZTEST_USER(bb_retimer_no_tasks, test_bb_set_dfp_state) { union tbt_mode_resp_device device_resp; union tbt_mode_resp_cable cable_resp; @@ -208,6 +209,7 @@ ZTEST_USER(bb_retimer, test_bb_set_dfp_state) set_test_runner_tid(); tc_set_data_role(USBC_PORT_C1, PD_ROLE_DFP); + zassume_equal(PD_ROLE_DFP, pd_get_data_role(USBC_PORT_C1), NULL); /* Test PD mux none mode with DFP should clear all bits in state */ bb_emul_set_reg(emul, BB_RETIMER_REG_CONNECTION_STATE, 0x12144678); @@ -569,4 +571,7 @@ ZTEST_USER(bb_retimer, test_bb_console_cmd) zassert_equal(EC_ERROR_PARAM4, rv, "rv=%d", rv); } +ZTEST_SUITE(bb_retimer_no_tasks, drivers_predicate_pre_main, NULL, NULL, NULL, + NULL); + ZTEST_SUITE(bb_retimer, drivers_predicate_post_main, NULL, NULL, NULL, NULL); -- cgit v1.2.1 From 4cec658bea5f64226db0ba91ebb3c2bd573c02f2 Mon Sep 17 00:00:00 2001 From: Sue Chen Date: Tue, 19 Jul 2022 14:33:01 +0800 Subject: Nissa/Craask: adjust keyboard top row Adjust keyboard top row. BUG=none BRANCH=none TEST=the function of top row keys is good. Signed-off-by: Sue Chen Change-Id: Ibee146ad5ade5b52ec998110e7b2efa6e92c8696 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3771323 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/CMakeLists.txt | 1 + zephyr/projects/nissa/src/craask/keyboard.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 zephyr/projects/nissa/src/craask/keyboard.c diff --git a/zephyr/projects/nissa/CMakeLists.txt b/zephyr/projects/nissa/CMakeLists.txt index 84d7ca57c1..f63db78631 100644 --- a/zephyr/projects/nissa/CMakeLists.txt +++ b/zephyr/projects/nissa/CMakeLists.txt @@ -33,6 +33,7 @@ if(DEFINED CONFIG_BOARD_NEREID) endif() if(DEFINED CONFIG_BOARD_CRAASK) zephyr_library_sources( + "src/craask/keyboard.c" "src/craask/led.c" ) project(craask) diff --git a/zephyr/projects/nissa/src/craask/keyboard.c b/zephyr/projects/nissa/src/craask/keyboard.c new file mode 100644 index 0000000000..449e7b16b2 --- /dev/null +++ b/zephyr/projects/nissa/src/craask/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config craask_kb = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_REFRESH, /* T2 */ + TK_FULLSCREEN, /* T3 */ + TK_OVERVIEW, /* T4 */ + TK_SNAPSHOT, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &craask_kb; +} -- cgit v1.2.1 From 27a8d5d45065533e2835ecbd435841c4dbb5c19a Mon Sep 17 00:00:00 2001 From: Sue Chen Date: Tue, 19 Jul 2022 09:55:58 +0800 Subject: Nissa: Add new battery for Craask New battery: AP20CBL BUG=b:230427330 BRANCH=none TEST=battery cut off test, battery detection Signed-off-by: Sue Chen Change-Id: I9468168301a00ca2cce46dff3e44c058ab2e4eb2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3771360 Reviewed-by: Andrew McRae --- zephyr/dts/bindings/battery/battery-smart.yaml | 1 + zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml | 57 ++++++++++++++++++++++++++ zephyr/projects/nissa/craask_overlay.dts | 3 ++ 3 files changed, 61 insertions(+) create mode 100644 zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index 62ef63c99d..e2df650137 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -16,6 +16,7 @@ properties: - "as3gxxe3ka,c140254" - "byd,l22b3pg0" - "celxpert,l22c3pg0" + - "cosmx,ap20cbl" - "cosmx,l22x3pg0" - "ganfeng,7c01" - "getac,bq40z50-R3-S3" diff --git a/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml new file mode 100644 index 0000000000..193ef649f1 --- /dev/null +++ b/zephyr/dts/bindings/battery/cosmx,ap20cbl.yaml @@ -0,0 +1,57 @@ +description: "COSMX AP20CBL" +compatible: "cosmx,ap20cbl" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "cosmx,ap20cbl" + + # Fuel gauge + manuf_name: + default: "COSMX KT0030B002" + device_name: + default: "AP20CBL" + ship_mode_reg_addr: + default: 0x3A + ship_mode_reg_data: + default: [ 0xC574, 0xC574 ] + # Documentation: b/230427330 + # Manufacturer Access 0x00 + # b14: Charging Disabled (0: Off, 1: On) + # b13: Discharging Disabled (0: Off, 1: On) + fet_mfgacc_support: + default: 1 + fet_reg_addr: + default: 0x0 + fet_reg_mask: + default: 0x2000 + fet_disconnect_val: + default: 0x2000 + fet_cfet_mask: + default: 0x4000 + fet_cfet_off_val: + default: 0x4000 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11550 + voltage_min: + default: 9000 + precharge_current: + default: 256 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: 0 + charging_max_c: + default: 60 + discharging_min_c: + default: -20 + discharging_max_c: + default: 75 diff --git a/zephyr/projects/nissa/craask_overlay.dts b/zephyr/projects/nissa/craask_overlay.dts index e0143669a5..6a83ee70ad 100644 --- a/zephyr/projects/nissa/craask_overlay.dts +++ b/zephyr/projects/nissa/craask_overlay.dts @@ -22,6 +22,9 @@ default_battery: lgc { compatible = "lgc,ap18c8k", "battery-smart"; }; + cosmx { + compatible = "cosmx,ap20cbl", "battery-smart"; + }; }; hibernate-wake-pins { -- cgit v1.2.1 From 3112d66701c5984a40343536fbf710fe9fa77748 Mon Sep 17 00:00:00 2001 From: Eric Yilun Lin Date: Tue, 19 Jul 2022 10:43:58 +0800 Subject: corsola: set HPD level at DPStatus Corsola skipped the post-config for HPD level, so we have to set HPD level pin to high when the DPStatus has informed. BUG=b:238170235 TEST=able to DP out when plug a hub with HDMI port attached. BRANCH=none Change-Id: I07c2d2fe9a64497b0b82bbd0fabdea6c47aab864 Signed-off-by: Eric Yilun Lin Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3771680 Auto-Submit: Eric Yilun Lin Commit-Queue: Ting Shen Tested-by: Eric Yilun Lin Reviewed-by: Ting Shen --- zephyr/projects/corsola/src/usb_pd_policy.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/zephyr/projects/corsola/src/usb_pd_policy.c b/zephyr/projects/corsola/src/usb_pd_policy.c index 9f4c4ee5ae..9643aefa23 100644 --- a/zephyr/projects/corsola/src/usb_pd_policy.c +++ b/zephyr/projects/corsola/src/usb_pd_policy.c @@ -181,14 +181,6 @@ __override int svdm_dp_attention(int port, uint32_t *payload) } } - /* Its initial DP status message prior to config */ - if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { - if (lvl) { - dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; - } - return 1; - } - #ifdef CONFIG_USB_PD_DP_HPD_GPIO if (irq && !lvl) { /* -- cgit v1.2.1 From 26944b35448a9171219ee5e25a0ae7ccd64e8b3d Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Wed, 13 Jul 2022 15:26:40 +0800 Subject: kinox: modify the SIO_LEGO_EN_L for AIO button Add the SIO_LEGO_EN_L control when using the AIO device. SIO_LEGO_EN_L set to 0 can use the AIO power button. SIO_LEGO_EN_L set to 1 cannot use the AIO power button. BUG=b:238157622 BRANCH=none TEST=Has been confirmed that the AIO power button has a function. Signed-off-by: Matt Wang Change-Id: I036a7e177de440f9cf056a778589d97ad5cc1dd8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759836 Reviewed-by: Elmo Lan Reviewed-by: Ricky Chang Commit-Queue: Ricky Chang --- board/kinox/gpio.inc | 2 +- board/kinox/power_detection.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/kinox/gpio.inc b/board/kinox/gpio.inc index 5c5f52ecc1..6e2784e081 100644 --- a/board/kinox/gpio.inc +++ b/board/kinox/gpio.inc @@ -58,7 +58,7 @@ GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) GPIO(GSC_EC_RECOVERY_BTN_OD, PIN(2, 2), GPIO_INPUT) -GPIO(SIO_LEGO_EN, PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP) +GPIO(SIO_LEGO_EN_L, PIN(9, 6), GPIO_OUT_LOW) /* HDMI CEC */ /* TODO(b/197474873): Enable HDMI CEC */ diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c index fdd88f1d4e..d930a7846e 100644 --- a/board/kinox/power_detection.c +++ b/board/kinox/power_detection.c @@ -291,11 +291,13 @@ void set_the_obp(int power_type_index, int adp_type) switch (adp_type) { case TIO1: case TIO2: + gpio_set_level(GPIO_SIO_LEGO_EN_L, 0); charge_manager_update_charge( CHARGE_SUPPLIER_PROPRIETARY, DEDICATED_CHARGE_PORT, &pi); break; case TINY: + gpio_set_level(GPIO_SIO_LEGO_EN_L, 1); charge_manager_update_charge(CHARGE_SUPPLIER_DEDICATED, DEDICATED_CHARGE_PORT, &pi); -- cgit v1.2.1 From e97b3e407b786e95cabef7977d42998f0ed13be8 Mon Sep 17 00:00:00 2001 From: Matt Wang Date: Thu, 14 Jul 2022 14:58:57 +0800 Subject: kinox: modify detect ADP_ID formula Modify the comparison value is volage to voltage. Delete the ADP_ID factor_div's +1 method to make sure the method can to get max 2816 value(2.816v). BUG=b:211806236,b:238157622 BRANCH=none TEST=Can get the TIO and Tiny adapter watt. Signed-off-by: Matt Wang Change-Id: I1be5b834c40465664a79d50fa8c09603c8b2c94f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760805 Commit-Queue: Ricky Chang Reviewed-by: Ricky Chang --- board/kinox/power_detection.c | 23 +++++++++++++---------- board/kinox/sensors.c | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/board/kinox/power_detection.c b/board/kinox/power_detection.c index d930a7846e..679c76dea8 100644 --- a/board/kinox/power_detection.c +++ b/board/kinox/power_detection.c @@ -29,8 +29,8 @@ static const char *const adp_id_names[] = { /* ADP_ID control */ struct adpater_id_params tio1_power[] = { { - .min_voltage = 3300, - .max_voltage = 3300, + .min_voltage = 2816, + .max_voltage = 2816, .charge_voltage = 20000, .charge_current = 6000, .watt = 120, @@ -96,7 +96,7 @@ struct adpater_id_params tio2_power[] = { }, { .min_voltage = 2816, - .max_voltage = 3300, + .max_voltage = 2816, .charge_voltage = 20000, .charge_current = 6000, .watt = 120, @@ -321,10 +321,10 @@ void set_the_obp(int power_type_index, int adp_type) * | | | * |---220 ms---|-----400 ms-----| * - * Tiny: Twice adapter ADC values are less than 0x3FF. - * TIO1: Twice adapter ADC values are 0x3FF. - * TIO2: First adapter ADC value less than 0x3FF. - * Second adpater ADC value is 0x3FF. + * Tiny: Twice adapter ADC values are less than 2.816v. + * TIO1: Twice adapter ADC values are 2.816v. + * TIO2: First adapter ADC value less than 2.816v. + * Second adpater ADC value is 2.816v. */ static void adp_id_deferred(void); DECLARE_DEFERRED(adp_id_deferred); @@ -342,13 +342,16 @@ void adp_id_deferred(void) adp_id_value_debounce = adp_id_value; /* for delay the 400ms to get the next APD_ID value */ hook_call_deferred(&adp_id_deferred_data, 400 * MSEC); - } else if (adp_id_value_debounce == 0x3FF && adp_id_value == 0x3FF) { + } else if (adp_id_value_debounce == ADC_MAX_VOLT && + adp_id_value == ADC_MAX_VOLT) { adp_finial_adc_value = adp_id_value; adp_type = TIO1; - } else if (adp_id_value_debounce < 0x3FF && adp_id_value == 0x3FF) { + } else if (adp_id_value_debounce < ADC_MAX_VOLT && + adp_id_value == ADC_MAX_VOLT) { adp_finial_adc_value = adp_id_value_debounce; adp_type = TIO2; - } else if (adp_id_value_debounce < 0x3FF && adp_id_value < 0x3FF) { + } else if (adp_id_value_debounce < ADC_MAX_VOLT && + adp_id_value < ADC_MAX_VOLT) { adp_finial_adc_value = adp_id_value; adp_type = TINY; } else { diff --git a/board/kinox/sensors.c b/board/kinox/sensors.c index 3441d2621e..7272e1b711 100644 --- a/board/kinox/sensors.c +++ b/board/kinox/sensors.c @@ -56,7 +56,7 @@ const struct adc_t adc_channels[] = { .name = "ADP_ID", .input_ch = NPCX_ADC_CH4, .factor_mul = ADC_MAX_VOLT, - .factor_div = ADC_READ_MAX + 1, + .factor_div = ADC_READ_MAX, }, }; BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); -- cgit v1.2.1 From 8d30a05ed74730fece3ebf0fd617426c565541ce Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Tue, 12 Jul 2022 10:01:23 -0700 Subject: tree: Remove non-standard "%ph" printf format The non-standard "%ph" format is replaced with snprintf_hex_buffer and then using "%s" to print the resulting buffer. Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=Enable CONFIG_CMD_RAND in nocturne_fp/board.h On icetower v0.1 with servo_micro and J-Trace: Before change: > rand rand 8ab8b15090ca5ae83bdad671c906d51a5f2b98a359a4106054ee6b54a4087190 After change: > rand rand 2a8645235a31936a28b8d1b9c4948f46d39662e7fcb10a185ddb14c6a998e2eb Signed-off-by: Tom Hughes Change-Id: I3bff928d32579440d7cdb27a75899e45159accfb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3759123 Reviewed-by: Denis Brockus --- chip/it83xx/i2c_peripheral.c | 7 ++++++- chip/stm32/trng.c | 6 +++++- common/host_command.c | 34 +++++++++++++++++++++++----------- common/i2c_controller.c | 20 +++++++++++++++----- common/peci.c | 11 +++++++++-- common/printf.c | 21 +-------------------- common/spi_commands.c | 10 ++++++++-- common/usb_host_command.c | 10 ++++++++-- common/vboot_hash.c | 24 +++++++++++++++++++----- driver/nfc/ctn730.c | 19 +++++++++++++++---- driver/touchpad_st.c | 31 ++++++++++++++++++------------- fuzz/host_command_fuzz.c | 8 ++++++-- include/printf.h | 2 -- test/host_command.c | 17 ++++++++++++----- test/printf.c | 9 ++++++--- 15 files changed, 151 insertions(+), 78 deletions(-) diff --git a/chip/it83xx/i2c_peripheral.c b/chip/it83xx/i2c_peripheral.c index c5455327a0..e12173c690 100644 --- a/chip/it83xx/i2c_peripheral.c +++ b/chip/it83xx/i2c_peripheral.c @@ -10,6 +10,7 @@ #include "gpio.h" #include "hooks.h" #include "i2c_peripheral.h" +#include "printf.h" #include "registers.h" #include #include @@ -178,13 +179,17 @@ void i2c_peripheral_read_write_data(int port) /* Peripheral finish */ if (periph_status & IT83XX_I2C_P_CLR) { if (wr_done[idx]) { + char str_buf[hex_str_buf_size( + I2C_MAX_BUFFER_SIZE)]; /* * TODO(b:129360157): Handle controller * write data by "in_data" array. */ - CPRINTS("WData: %ph", + snprintf_hex_buffer( + str_buf, sizeof(str_buf), HEX_BUF(in_data[idx], I2C_MAX_BUFFER_SIZE)); + CPRINTS("WData: %s", str_buf); wr_done[idx] = 0; } } diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 6538263add..a975c4c584 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -9,6 +9,7 @@ #include "console.h" #include "host_command.h" #include "panic.h" +#include "printf.h" #include "registers.h" #include "system.h" #include "task.h" @@ -106,12 +107,15 @@ test_mockable void trng_exit(void) static int command_rand(int argc, char **argv) { uint8_t data[32]; + char str_buf[hex_str_buf_size(sizeof(data))]; trng_init(); trng_rand_bytes(data, sizeof(data)); trng_exit(); - ccprintf("rand %ph\n", HEX_BUF(data, sizeof(data))); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(data, sizeof(data))); + ccprintf("rand %s\n", str_buf); return EC_SUCCESS; } diff --git a/common/host_command.c b/common/host_command.c index 417a2f3465..a2d8defbef 100644 --- a/common/host_command.c +++ b/common/host_command.c @@ -655,10 +655,14 @@ static void host_command_debug_request(struct host_cmd_handler_args *args) hc_prev_cmd = args->command; } - if (hcdebug >= HCDEBUG_PARAMS && args->params_size) - CPRINTS("HC 0x%04x.%d:%ph", args->command, args->version, - HEX_BUF(args->params, args->params_size)); - else + if (hcdebug >= HCDEBUG_PARAMS && args->params_size) { + char str_buf[hex_str_buf_size(args->params_size)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(args->params, args->params_size)); + CPRINTS("HC 0x%04x.%d:%s", args->command, args->version, + str_buf); + } else CPRINTS("HC 0x%04x", args->command); } @@ -714,9 +718,14 @@ uint16_t host_command_process(struct host_cmd_handler_args *args) if (rv != EC_RES_SUCCESS) CPRINTS("HC 0x%04x err %d", args->command, rv); - if (hcdebug >= HCDEBUG_PARAMS && args->response_size) - CPRINTS("HC resp:%ph", - HEX_BUF(args->response, args->response_size)); + if (hcdebug >= HCDEBUG_PARAMS && args->response_size) { + char str_buf[hex_str_buf_size(args->response_size)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(args->response, + args->response_size)); + CPRINTS("HC resp:%s", str_buf); + } return rv; } @@ -878,10 +887,13 @@ static int command_host_command(int argc, char **argv) if (res != EC_RES_SUCCESS) ccprintf("Command returned %d\n", res); - else if (args.response_size) - ccprintf("Response: %ph\n", - HEX_BUF(cmd_params, args.response_size)); - else + else if (args.response_size) { + char str_buf[hex_str_buf_size(args.response_size)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(cmd_params, args.response_size)); + ccprintf("Response: %s\n", str_buf); + } else ccprintf("Command succeeded; no response.\n"); shared_mem_release(cmd_params); diff --git a/common/i2c_controller.c b/common/i2c_controller.c index ea85f80a14..cc7dad9bed 100644 --- a/common/i2c_controller.c +++ b/common/i2c_controller.c @@ -15,6 +15,7 @@ #include "i2c.h" #include "i2c_bitbang.h" #include "i2c_private.h" +#include "printf.h" #include "system.h" #include "task.h" #include "usb_pd.h" @@ -1710,8 +1711,13 @@ static int command_i2cxfer(int argc, char **argv) rv = i2c_xfer(port, addr_flags, (uint8_t *)&offset, 1, data, v); - if (!rv) - ccprintf("Data: %ph\n", HEX_BUF(data, v)); + if (!rv) { + char str_buf[hex_str_buf_size(v)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(data, v)); + ccprintf("Data: %s\n", str_buf); + } } else if (strcasecmp(argv[1], "w") == 0) { /* 8-bit write */ @@ -1780,9 +1786,13 @@ static int command_i2cxfer(int argc, char **argv) read_count, I2C_XFER_START | I2C_XFER_STOP); i2c_lock(port, 0); - if (!rv) - ccprintf("Data: %ph\n", - HEX_BUF(data, read_count)); + if (!rv) { + char str_buf[hex_str_buf_size(read_count)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(data, read_count)); + ccprintf("Data: %s\n", str_buf); + } } #endif /* CONFIG_CMD_I2C_XFER_RAW */ } else { diff --git a/common/peci.c b/common/peci.c index dc17f86a56..5acc49dfd2 100644 --- a/common/peci.c +++ b/common/peci.c @@ -8,6 +8,7 @@ #include "chipset.h" #include "console.h" #include "peci.h" +#include "printf.h" #include "util.h" static int peci_get_cpu_temp(int *cpu_temp) @@ -139,9 +140,15 @@ static int peci_cmd(int argc, char **argv) if (peci_transaction(&peci)) { ccprintf("PECI transaction error\n"); return EC_ERROR_UNKNOWN; + } else { + char str_buf[hex_str_buf_size(peci.r_len)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(r_buf, sizeof(str_buf))); + ccprintf("PECI read data: %s\n", str_buf); + + return EC_SUCCESS; } - ccprintf("PECI read data: %ph\n", HEX_BUF(r_buf, peci.r_len)); - return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(peci, peci_cmd, "addr wlen rlen cmd timeout(us)", "PECI command"); diff --git a/common/printf.c b/common/printf.c index b3e9d45109..f25a5ac0b2 100644 --- a/common/printf.c +++ b/common/printf.c @@ -393,28 +393,9 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, ptrspec = *format++; ptrval = va_arg(args, void *); /* - * Avoid null pointer dereference for %ph. * %pP can accept null. */ - if (ptrval == NULL && ptrspec != 'P') - continue; - else if (ptrspec == 'h') { - /* %ph - Print a hex byte buffer. */ - struct hex_buffer_params *hexbuf = - ptrval; - int rc; - - rc = print_hex_buffer(addchar, context, - hexbuf->buffer, - hexbuf->size, 0, - 0); - - if (rc != EC_SUCCESS) - return rc; - - continue; - - } else if (ptrspec == 'P') { + if (ptrspec == 'P') { /* %pP - Print a raw pointer. */ v = (unsigned long)ptrval; base = 16; diff --git a/common/spi_commands.c b/common/spi_commands.c index 45c2f3ce70..b51609d257 100644 --- a/common/spi_commands.c +++ b/common/spi_commands.c @@ -8,6 +8,7 @@ #include "common.h" #include "console.h" +#include "printf.h" #include "spi.h" #include "timer.h" #include "util.h" @@ -45,8 +46,13 @@ static int command_spixfer(int argc, char **argv) rv = spi_transaction(&spi_devices[dev_id], &cmd, 1, data, v); - if (!rv) - ccprintf("Data: %ph\n", HEX_BUF(data, v)); + if (!rv) { + char str_buf[hex_str_buf_size(v)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(data, v)); + ccprintf("Data: %s\n", str_buf); + } } else if (strcasecmp(argv[1], "w") == 0) { /* 8-bit write */ diff --git a/common/usb_host_command.c b/common/usb_host_command.c index e4872750dd..697885a1f7 100644 --- a/common/usb_host_command.c +++ b/common/usb_host_command.c @@ -9,6 +9,7 @@ #include "ec_commands.h" #include "queue_policies.h" #include "host_command.h" +#include "printf.h" #include "system.h" #include "usb_api.h" #include "usb_hw.h" @@ -161,8 +162,13 @@ static void usbhc_written(struct consumer const *consumer, size_t count) block_index = 0; /* Only version 3 is supported. Using in_msg as a courtesy. */ QUEUE_REMOVE_UNITS(consumer->queue, in_msg, count); - if (IS_ENABLED(DEBUG)) - CPRINTS("%ph", HEX_BUF(in_msg, count)); + if (IS_ENABLED(DEBUG)) { + char str_buf[hex_str_buf_size(count)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(in_msg, count)); + CPRINTS("%s", str_buf); + } if (in_msg[0] != EC_HOST_REQUEST_VERSION) { CPRINTS("Unsupported version: %u", in_msg[0]); return; diff --git a/common/vboot_hash.c b/common/vboot_hash.c index fe32f774eb..bb51858374 100644 --- a/common/vboot_hash.c +++ b/common/vboot_hash.c @@ -11,6 +11,7 @@ #include "flash.h" #include "hooks.h" #include "host_command.h" +#include "printf.h" #include "sha256.h" #include "shared_mem.h" #include "stdbool.h" @@ -130,6 +131,8 @@ static void hash_next_chunk(size_t size) static void vboot_hash_all_chunks(void) { + char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)]; + do { size_t size = MIN(CHUNK_SIZE, data_size - curr_pos); hash_next_chunk(size); @@ -137,7 +140,9 @@ static void vboot_hash_all_chunks(void) } while (curr_pos < data_size); hash = SHA256_final(&ctx); - CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE)); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(hash, SHA256_PRINT_SIZE)); + CPRINTS("hash done %s", str_buf); in_progress = 0; clock_enable_module(MODULE_FAST_CPU, 0); @@ -165,9 +170,14 @@ static void vboot_hash_next_chunk(void) curr_pos += size; if (curr_pos >= data_size) { + char str_buf[hex_str_buf_size(SHA256_PRINT_SIZE)]; + /* Store the final hash */ hash = SHA256_final(&ctx); - CPRINTS("hash done %ph", HEX_BUF(hash, SHA256_PRINT_SIZE)); + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(hash, SHA256_PRINT_SIZE)); + CPRINTS("hash done %s", str_buf); in_progress = 0; @@ -343,9 +353,13 @@ static int command_hash(int argc, char **argv) ccprintf("(aborting)\n"); else if (in_progress) ccprintf("(in progress)\n"); - else if (hash) - ccprintf("%ph\n", HEX_BUF(hash, SHA256_DIGEST_SIZE)); - else + else if (hash) { + char str_buf[hex_str_buf_size(SHA256_DIGEST_SIZE)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(hash, SHA256_DIGEST_SIZE)); + ccprintf("%s\n", str_buf); + } else ccprintf("(invalid)\n"); return EC_SUCCESS; diff --git a/driver/nfc/ctn730.c b/driver/nfc/ctn730.c index 16ab40d025..ea7eeb29df 100644 --- a/driver/nfc/ctn730.c +++ b/driver/nfc/ctn730.c @@ -10,6 +10,7 @@ #include "gpio.h" #include "i2c.h" #include "peripheral_charger.h" +#include "printf.h" #include "timer.h" #include "util.h" #include "watchdog.h" @@ -256,8 +257,13 @@ static int _process_payload_response(struct pchg *ctx, struct ctn730_msg *res) int rv = _i2c_read(ctx->cfg->i2c_port, buf, len); if (rv) return rv; - if (IS_ENABLED(CTN730_DEBUG)) - CPRINTS("Payload: %ph", HEX_BUF(buf, len)); + if (IS_ENABLED(CTN730_DEBUG)) { + char str_buf[hex_str_buf_size(len)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(buf, len)); + CPRINTS("Payload: %s", str_buf); + } } ctx->event = PCHG_EVENT_NONE; @@ -357,8 +363,13 @@ static int _process_payload_event(struct pchg *ctx, struct ctn730_msg *res) int rv = _i2c_read(ctx->cfg->i2c_port, buf, len); if (rv) return rv; - if (IS_ENABLED(CTN730_DEBUG)) - CPRINTS("Payload: %ph", HEX_BUF(buf, len)); + if (IS_ENABLED(CTN730_DEBUG)) { + char str_buf[hex_str_buf_size(len)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(buf, len)); + CPRINTS("Payload: %s", str_buf); + } } ctx->event = PCHG_EVENT_NONE; diff --git a/driver/touchpad_st.c b/driver/touchpad_st.c index db45b951c6..e5fab5ef7d 100644 --- a/driver/touchpad_st.c +++ b/driver/touchpad_st.c @@ -11,6 +11,7 @@ #include "hwtimer.h" #include "hooks.h" #include "i2c.h" +#include "printf.h" #include "registers.h" #include "spi.h" #include "task.h" @@ -578,7 +579,7 @@ static void dump_error(void) static void dump_memory(void) { uint32_t size = 0x10000, rx_len = 512 + ST_TP_EXTRA_BYTE; - uint32_t offset, i; + uint32_t offset, i, j; uint8_t cmd[] = { 0xFB, 0x00, 0x10, 0x00, 0x00 }; if (!dump_memory_on_error) @@ -591,16 +592,16 @@ static void dump_memory(void) rx_len); for (i = 0; i < rx_len - ST_TP_EXTRA_BYTE; i += 32) { - CPRINTF("%ph %ph %ph %ph " - "%ph %ph %ph %ph\n", - HEX_BUF(rx_buf.bytes + i + 4 * 0, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 1, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 2, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 3, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 4, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 5, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 6, 4), - HEX_BUF(rx_buf.bytes + i + 4 * 7, 4)); + for (j = 0; j < 8; j++) { + char str_buf[hex_str_buf_size(4)]; + + snprintf_hex_buffer( + str_buf, sizeof(str_buf), + HEX_BUF(rx_buf.bytes + i + 4 * j, 4)); + + CPRINTF("%s ", str_buf); + } + CPRINTF("\n"); msleep(8); } } @@ -1235,13 +1236,17 @@ int touchpad_debug(const uint8_t *param, unsigned int param_size, *data_size = 0; st_tp_stop_scan(); return EC_SUCCESS; - case ST_TP_DEBUG_CMD_READ_BUF_HEADER: + case ST_TP_DEBUG_CMD_READ_BUF_HEADER: { + char str_buf[hex_str_buf_size(8)]; *data = buf; *data_size = 8; st_tp_read_host_buffer_header(); memcpy(buf, rx_buf.bytes, *data_size); - CPRINTS("header: %ph", HEX_BUF(buf, *data_size)); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(buf, *data_size)); + CPRINTS("header: %s", str_buf); return EC_SUCCESS; + } case ST_TP_DEBUG_CMD_READ_EVENTS: num_events = st_tp_read_all_events(0); if (num_events) { diff --git a/fuzz/host_command_fuzz.c b/fuzz/host_command_fuzz.c index 856310db2b..b6c4c4685f 100644 --- a/fuzz/host_command_fuzz.c +++ b/fuzz/host_command_fuzz.c @@ -12,6 +12,7 @@ #include "console.h" #include "host_command.h" #include "host_test.h" +#include "printf.h" #include "task.h" #include "test_util.h" #include "timer.h" @@ -112,8 +113,11 @@ static int hostcmd_fill(const uint8_t *data, size_t size) * issues. */ if (first) { - ccprintf("Request: cmd=%04x data=%ph\n", req->command, - HEX_BUF(req_buf, req_size)); + char str_buf[hex_str_buf_size(req_size)]; + + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(req_buf, req_size)); + ccprintf("Request: cmd=%04x data=%s\n", req->command, str_buf); first = 0; } diff --git a/include/printf.h b/include/printf.h index e5afb7f2d1..48117042f9 100644 --- a/include/printf.h +++ b/include/printf.h @@ -65,8 +65,6 @@ * - 'b' - unsigned integer, print as binary * * Special format codes: - * - '%ph' - binary data, print as hex; Use HEX_BUF(buffer, size) to encode - * parameters. * - '%pP' - raw pointer. */ diff --git a/test/host_command.c b/test/host_command.c index 5c13e2b4cf..17637b52de 100644 --- a/test/host_command.c +++ b/test/host_command.c @@ -8,6 +8,7 @@ #include "common.h" #include "console.h" #include "host_command.h" +#include "printf.h" #include "task.h" #include "test_util.h" #include "timer.h" @@ -177,6 +178,7 @@ static int test_hostcmd_reuse_response_buffer(void) struct ec_host_request *h = (struct ec_host_request *)resp_buf; struct ec_params_hello *d = (struct ec_params_hello *)(resp_buf + sizeof(*h)); + char str_buf[hex_str_buf_size(BUFFER_SIZE)]; h->struct_version = 3; h->checksum = 0; @@ -201,13 +203,15 @@ static int test_hostcmd_reuse_response_buffer(void) h->checksum = calculate_checksum(resp_buf, pkt.request_size); - ccprintf("\nBuffer contents before process 0x%ph\n", - HEX_BUF(resp_buf, BUFFER_SIZE)); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(resp_buf, BUFFER_SIZE)); + ccprintf("\nBuffer contents before process 0x%s\n", str_buf); host_packet_receive(&pkt); task_wait_event(-1); - ccprintf("\nBuffer contents after process 0x%ph\n", - HEX_BUF(resp_buf, BUFFER_SIZE)); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(resp_buf, BUFFER_SIZE)); + ccprintf("\nBuffer contents after process 0x%s\n", str_buf); TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0, "%d"); @@ -239,6 +243,7 @@ static void hostcmd_fill_chip_info(void) static int test_hostcmd_clears_unused_data(void) { int i, found_null; + char str_buf[hex_str_buf_size(BUFFER_SIZE)]; /* Set the buffer to junk and ensure that is gets cleared */ memset(resp_buf, 0xAA, BUFFER_SIZE); @@ -246,7 +251,9 @@ static int test_hostcmd_clears_unused_data(void) hostcmd_send(); - ccprintf("\nBuffer contents 0x%ph\n", HEX_BUF(resp_buf, BUFFER_SIZE)); + snprintf_hex_buffer(str_buf, sizeof(str_buf), + HEX_BUF(resp_buf, BUFFER_SIZE)); + ccprintf("\nBuffer contents 0x%s\n", str_buf); TEST_EQ(calculate_checksum(resp_buf, sizeof(*resp) + resp->data_len), 0, "%d"); diff --git a/test/printf.c b/test/printf.c index 0ef24d1acd..5b7f3de99e 100644 --- a/test/printf.c +++ b/test/printf.c @@ -416,9 +416,12 @@ test_static int test_vsnprintf_hexdump(void) { const char bytes[] = { 0x00, 0x5E }; - T(expect_success("005e", "%ph", HEX_BUF(bytes, 2))); - T(expect_success("", "%ph", HEX_BUF(bytes, 0))); - T(expect_success("00", "%ph", HEX_BUF(bytes, 1))); + /* + * Test %ph, which used to print buffers as hex, but is non-standard + * and no longer supported. + */ + T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%ph", + HEX_BUF(bytes, 2))); return EC_SUCCESS; } -- cgit v1.2.1 From 4869e6f485ff4d1eb44d5c3148f0e6b7167a1148 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 8 Jul 2022 12:50:29 -0700 Subject: tree: Change non-standard "%pP" printf format to "%p" This is the last non-standard format overloading "%p", so we can change it to the standard "%p" format. Using standard format specifiers makes it easier to switch between the "builtin" EC standard library and the C standard library provided by the toolchain (or Zephyr). BRANCH=none BUG=b:238433667, b:234181908 TEST=On icetower v0.1 with servo_micro and J-Trace attached: Before change: > rw 536870912 read 0x20000000 = 0x45dbfce2 After change: > rw 536870912 read 0x20000000 = 0x45dbfce2 Signed-off-by: Tom Hughes Change-Id: Id5680ab07af5352d463df42daadff1619c06c9af Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3756180 Reviewed-by: Eric Yilun Lin --- board/servo_v4p1/usb_sm.c | 2 +- common/bluetooth_le.c | 6 +++--- common/btle_hci_controller.c | 6 +++--- common/btle_ll.c | 2 +- common/hooks.c | 2 +- common/memory_commands.c | 12 ++++++------ common/printf.c | 21 ++++----------------- common/system.c | 2 +- common/usbc/usb_sm.c | 2 +- core/host/stack_trace.c | 1 - include/printf.h | 4 +--- test/printf.c | 43 +------------------------------------------ test/shmalloc.c | 8 ++++---- zephyr/shim/src/hooks.c | 2 +- 14 files changed, 28 insertions(+), 85 deletions(-) diff --git a/board/servo_v4p1/usb_sm.c b/board/servo_v4p1/usb_sm.c index 1c94749c47..2016484bdd 100644 --- a/board/servo_v4p1/usb_sm.c +++ b/board/servo_v4p1/usb_sm.c @@ -115,7 +115,7 @@ void set_state(const int port, struct sm_ctx *const ctx, * intended state to transition into. */ if (internal->exit) { - CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", port, + CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port, new_state, ctx->current); return; } diff --git a/common/bluetooth_le.c b/common/bluetooth_le.c index 4dc1aade45..631ab5d0e0 100644 --- a/common/bluetooth_le.c +++ b/common/bluetooth_le.c @@ -139,7 +139,7 @@ static void mem_dump(uint8_t *mem, int len) for (i = 0; i < len; i++) { value = mem[i]; if (i % 8 == 0) - CPRINTF("\n%pP: %02x", &mem[i], value); + CPRINTF("\n%p: %02x", &mem[i], value); else CPRINTF(" %02x", value); } @@ -160,7 +160,7 @@ void dump_ble_packet(struct ble_pdu *ble_p) int curr_offs; if (ble_p->header_type_adv) { - CPRINTF("BLE packet @ %pP: type %d, len %d, %s %s\n", ble_p, + CPRINTF("BLE packet @ %p: type %d, len %d, %s %s\n", ble_p, ble_p->header.adv.type, ble_p->header.adv.length, (ble_p->header.adv.txaddr ? " TXADDR" : ""), (ble_p->header.adv.rxaddr ? " RXADDR" : "")); @@ -187,7 +187,7 @@ void dump_ble_packet(struct ble_pdu *ble_p) mem_dump(ble_p->payload + curr_offs, ble_p->header.adv.length - curr_offs); } else { /* Data PDUs */ - CPRINTF("BLE data packet @%pP: LLID %d," + CPRINTF("BLE data packet @%p: LLID %d," " nesn %d, sn %d, md %d, length %d\n", ble_p, ble_p->header.data.llid, ble_p->header.data.nesn, ble_p->header.data.sn, ble_p->header.data.md, diff --git a/common/btle_hci_controller.c b/common/btle_hci_controller.c index 806eb7a2fa..72ffe26d63 100644 --- a/common/btle_hci_controller.c +++ b/common/btle_hci_controller.c @@ -467,7 +467,7 @@ static int command_ble_hci_cmd(int argc, char **argv) hci_cmd(hci_buf); - CPRINTS("hci cmd @%pP", hci_buf); + CPRINTS("hci cmd @%p", hci_buf); return EC_SUCCESS; } @@ -507,7 +507,7 @@ static int command_hcitool(int argc, char **argv) hci_cmd(hci_buf); - CPRINTS("hci cmd @%pP", hci_buf); + CPRINTS("hci cmd @%p", hci_buf); return EC_SUCCESS; } @@ -552,7 +552,7 @@ static int command_ble_hci_acl(int argc, char **argv) hci_cmd(hci_buf); - CPRINTS("hci acl @%pP", hci_buf); + CPRINTS("hci acl @%p", hci_buf); return EC_SUCCESS; } diff --git a/common/btle_ll.c b/common/btle_ll.c index 0ae0531c2d..d167541efc 100644 --- a/common/btle_ll.c +++ b/common/btle_ll.c @@ -765,7 +765,7 @@ void bluetooth_ll_task(void) case ADVERTISING: if (deadline.val == 0) { - CPRINTS("ADV @%pP", &ll_adv_pdu); + CPRINTS("ADV @%p", &ll_adv_pdu); deadline.val = get_time().val + (uint32_t)ll_adv_timeout_us; ll_adv_events = 0; diff --git a/common/hooks.c b/common/hooks.c index 61904eea59..d5e45a5324 100644 --- a/common/hooks.c +++ b/common/hooks.c @@ -196,7 +196,7 @@ void hook_task(void *u) */ __deferred_until[i] = 0; interrupt_enable(); - CPRINTS("hook call deferred 0x%pP", + CPRINTS("hook call deferred 0x%p", __deferred_funcs[i].routine); __deferred_funcs[i].routine(); interrupt_disable(); diff --git a/common/memory_commands.c b/common/memory_commands.c index 4a4812b696..506b385626 100644 --- a/common/memory_commands.c +++ b/common/memory_commands.c @@ -147,16 +147,16 @@ static int command_read_word(int argc, char **argv) if ((argc - argc_offs) < 3) { switch (access_size) { case 1: - ccprintf("read 0x%pP = 0x%02x\n", address, + ccprintf("read 0x%p = 0x%02x\n", address, *((uint8_t *)address)); break; case 2: - ccprintf("read 0x%pP = 0x%04x\n", address, + ccprintf("read 0x%p = 0x%04x\n", address, *((uint16_t *)address)); break; default: - ccprintf("read 0x%pP = 0x%08x\n", address, *address); + ccprintf("read 0x%p = 0x%08x\n", address, *address); break; } return EC_SUCCESS; @@ -169,17 +169,17 @@ static int command_read_word(int argc, char **argv) switch (access_size) { case 1: - ccprintf("write 0x%pP = 0x%02x\n", address, (uint8_t)value); + ccprintf("write 0x%p = 0x%02x\n", address, (uint8_t)value); cflush(); /* Flush before writing in case this crashes */ *((uint8_t *)address) = (uint8_t)value; break; case 2: - ccprintf("write 0x%pP = 0x%04x\n", address, (uint16_t)value); + ccprintf("write 0x%p = 0x%04x\n", address, (uint16_t)value); cflush(); *((uint16_t *)address) = (uint16_t)value; break; default: - ccprintf("write 0x%pP = 0x%02x\n", address, value); + ccprintf("write 0x%p = 0x%02x\n", address, value); cflush(); *address = value; break; diff --git a/common/printf.c b/common/printf.c index f25a5ac0b2..9a3e593cba 100644 --- a/common/printf.c +++ b/common/printf.c @@ -339,7 +339,6 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, int base = 10; uint64_t v; - int ptrspec; void *ptrval; /* @@ -390,23 +389,11 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, if (c == 'p') { c = -1; - ptrspec = *format++; ptrval = va_arg(args, void *); - /* - * %pP can accept null. - */ - if (ptrspec == 'P') { - /* %pP - Print a raw pointer. */ - v = (unsigned long)ptrval; - base = 16; - if (sizeof(unsigned long) == - sizeof(uint64_t)) - flags |= PF_64BIT; - - } else { - return EC_ERROR_INVAL; - } - + v = (unsigned long)ptrval; + base = 16; + if (sizeof(unsigned long) == sizeof(uint64_t)) + flags |= PF_64BIT; } else if (flags & PF_64BIT) { v = va_arg(args, uint64_t); } else { diff --git a/common/system.c b/common/system.c index 5e215a0b4f..1961f192e5 100644 --- a/common/system.c +++ b/common/system.c @@ -414,7 +414,7 @@ void system_disable_jump(void) */ ret = mpu_protect_data_ram(); if (ret == EC_SUCCESS) { - CPRINTS("data RAM locked. Exclusion %pP-%pP", + CPRINTS("data RAM locked. Exclusion %p-%p", &__iram_text_start, &__iram_text_end); } else { CPRINTS("Failed to lock data RAM (%d)", ret); diff --git a/common/usbc/usb_sm.c b/common/usbc/usb_sm.c index 11b2e604af..004a64321c 100644 --- a/common/usbc/usb_sm.c +++ b/common/usbc/usb_sm.c @@ -116,7 +116,7 @@ void set_state(const int port, struct sm_ctx *const ctx, * intended state to transition into. */ if (internal->exit) { - CPRINTF("C%d: Ignoring set state to 0x%pP within 0x%pP", port, + CPRINTF("C%d: Ignoring set state to 0x%p within 0x%p", port, new_state, ctx->current); return; } diff --git a/core/host/stack_trace.c b/core/host/stack_trace.c index 54163c66ad..41392e0e70 100644 --- a/core/host/stack_trace.c +++ b/core/host/stack_trace.c @@ -44,7 +44,6 @@ static void __attribute__((noinline)) _task_dump_trace_impl(int offset) for (i = 0; i < sz - offset; ++i) { fprintf(stderr, "#%-2d %s\n", i, messages[i]); - /* %p is correct (as opposed to %pP) since this is the host */ sprintf(buf, "addr2line %p -e %s", trace[i + offset], __get_prog_name()); file = popen(buf, "r"); diff --git a/include/printf.h b/include/printf.h index 48117042f9..b63208f84d 100644 --- a/include/printf.h +++ b/include/printf.h @@ -63,9 +63,7 @@ * - 'x' - unsigned integer, print as lower-case hexadecimal * - 'X' - unsigned integer, print as upper-case hexadecimal * - 'b' - unsigned integer, print as binary - * - * Special format codes: - * - '%pP' - raw pointer. + * - 'p' - pointer */ #ifndef HIDE_EC_STDLIB diff --git a/test/printf.c b/test/printf.c index 5b7f3de99e..3928185918 100644 --- a/test/printf.c +++ b/test/printf.c @@ -287,20 +287,7 @@ test_static int test_vsnprintf_pointers(void) { void *ptr = (void *)0x55005E00; - T(expect_success("55005e00", "%pP", ptr)); - T(expect_success(err_str, "%P", ptr)); - /* %p by itself is invalid */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%p")); - /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%p ")); - /* %p with an unknown suffix is invalid */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pQ")); - - /* - * Test %pb, which used to print binary, but is non-standard and no - * longer supported. - */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pb", 0xff)); + T(expect_success("55005e00", "%p", ptr)); return EC_SUCCESS; } @@ -341,19 +328,6 @@ test_static int test_vsnprintf_strings(void) return EC_SUCCESS; } -test_static int test_vsnprintf_timestamps(void) -{ - uint64_t ts = 0; - - /* - * Test %pT, which used to print timestamps, but is non-standard and no - * longer supported. - */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%pT", &ts)); - - return EC_SUCCESS; -} - test_static int test_snprintf_timestamp(void) { char str[PRINTF_TIMESTAMP_BUF_SIZE]; @@ -412,19 +386,6 @@ test_static int test_snprintf_timestamp(void) return EC_SUCCESS; } -test_static int test_vsnprintf_hexdump(void) -{ - const char bytes[] = { 0x00, 0x5E }; - - /* - * Test %ph, which used to print buffers as hex, but is non-standard - * and no longer supported. - */ - T(expect(EC_ERROR_INVAL, "", false, sizeof(output), "%ph", - HEX_BUF(bytes, 2))); - return EC_SUCCESS; -} - test_static int test_snprintf_hex_buffer(void) { const uint8_t bytes[] = { 0xAB, 0x5E }; @@ -597,8 +558,6 @@ void run_test(int argc, char **argv) RUN_TEST(test_vsnprintf_pointers); RUN_TEST(test_vsnprintf_chars); RUN_TEST(test_vsnprintf_strings); - RUN_TEST(test_vsnprintf_timestamps); - RUN_TEST(test_vsnprintf_hexdump); RUN_TEST(test_vsnprintf_combined); RUN_TEST(test_uint64_to_str); RUN_TEST(test_snprintf_timestamp); diff --git a/test/shmalloc.c b/test/shmalloc.c index b77f720ac9..31696b2a27 100644 --- a/test/shmalloc.c +++ b/test/shmalloc.c @@ -111,7 +111,7 @@ static int check_for_overlaps(void) } } if (!allocation_match) { - ccprintf("missing match %pP!\n", allocations[i].buf); + ccprintf("missing match %p!\n", allocations[i].buf); return 0; } } @@ -136,7 +136,7 @@ static int shmem_is_ok(int line) struct shm_buffer *pbuf = free_buf_chain; if (pbuf && pbuf->prev_buffer) { - ccprintf("Bad free buffer list start %pP\n", pbuf); + ccprintf("Bad free buffer list start %p\n", pbuf); goto bailout; } @@ -152,13 +152,13 @@ static int shmem_is_ok(int line) if (pbuf->next_buffer) { if (top >= pbuf->next_buffer) { ccprintf("%s:%d" - " - inconsistent buffer size at %pP\n", + " - inconsistent buffer size at %p\n", __func__, __LINE__, pbuf); goto bailout; } if (pbuf->next_buffer->prev_buffer != pbuf) { ccprintf("%s:%d" - " - inconsistent next buffer at %pP\n", + " - inconsistent next buffer at %p\n", __func__, __LINE__, pbuf); goto bailout; } diff --git a/zephyr/shim/src/hooks.c b/zephyr/shim/src/hooks.c index 392f046c85..ddb48278b5 100644 --- a/zephyr/shim/src/hooks.c +++ b/zephyr/shim/src/hooks.c @@ -52,7 +52,7 @@ static void work_queue_error(const void *data, int rv) { cprints(CC_HOOK, "Warning: deferred call not submitted, " - "deferred_data=0x%pP, err=%d", + "deferred_data=0x%p, err=%d", data, rv); } -- cgit v1.2.1 From 3f497875d8f0e5f19962f22ab78157aa3a0c2e85 Mon Sep 17 00:00:00 2001 From: Tomasz Michalec Date: Tue, 19 Jul 2022 17:05:35 +0200 Subject: zephyr: tests: Clear PD disabled by policy flag While testing pd console command, PD_DISABLED_BY_POLICY flag is set. Because of that some other tests may fail. Clear PD_DISABLE_BY_POLICY flag after pd console command tests. BUG=b:233102631 TEST=zmake -D test test-drivers BRANCH=None Signed-off-by: Tomasz Michalec Change-Id: I1cb898f1f680238eb4e14dc640690a8412806b27 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3773853 Tested-by: Tomasz Michalec Reviewed-by: Aaron Massey Commit-Queue: Tomasz Michalec --- zephyr/test/drivers/src/console_cmd/usb_pd_console.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/zephyr/test/drivers/src/console_cmd/usb_pd_console.c b/zephyr/test/drivers/src/console_cmd/usb_pd_console.c index 4902591c67..36f3402378 100644 --- a/zephyr/test/drivers/src/console_cmd/usb_pd_console.c +++ b/zephyr/test/drivers/src/console_cmd/usb_pd_console.c @@ -20,6 +20,9 @@ static void console_cmd_usb_pd_after(void *fixture) k_sleep(K_SECONDS(1)); test_set_chipset_to_s0(); k_sleep(K_SECONDS(10)); + + /* Keep port used by testsuite enabled (default state) */ + pd_comm_enable(0, 1); } ZTEST_SUITE(console_cmd_usb_pd, drivers_predicate_post_main, NULL, NULL, -- cgit v1.2.1 From b6f385a4492b61ab171dcb97e352cf13e3a21b05 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 18 Jul 2022 13:10:36 -0600 Subject: PRESUBMIT.cfg: Enable black_check and drop custom script Enable the global PRESUBMIT.cfg option for black pre-upload checks, and drop our custom script. isort checks are done by cros lint, so this was redundant in the custom script. BUG=b:238434058 BRANCH=none TEST=Run pre-upload on some recent commits Signed-off-by: Jack Rosenthal Change-Id: Ib624b619621654949019541f03ffe35ba69f78b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3770681 Commit-Queue: Jeremy Bettis Reviewed-by: Jeremy Bettis --- PRESUBMIT.cfg | 3 ++- util/python-pre-upload.sh | 49 ----------------------------------------------- 2 files changed, 2 insertions(+), 50 deletions(-) delete mode 100755 util/python-pre-upload.sh diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg index c9d0887b23..3aabbe3bb3 100644 --- a/PRESUBMIT.cfg +++ b/PRESUBMIT.cfg @@ -1,4 +1,5 @@ [Hook Overrides] +black_check: true clang_format_check: true branch_check: true checkpatch_check: true @@ -10,6 +11,7 @@ signoff_check: true tab_check: false [Hook Overrides Options] +black_check: --include_regex=^util/chargen$ checkpatch_check: --no-tree --ignore=MSLEEP,VOLATILE,SPDX_LICENSE_TAG kerneldoc_check: --include_regex=\bec_commands\.h$ @@ -29,5 +31,4 @@ presubmit_check = util/presubmit_check.sh config_option_check = util/config_option_check.py host_command_check = util/host_command_check.sh ec_commands_h = util/linux_ec_commands_h_check.sh -python_preupload = util/python-pre-upload.sh ${PRESUBMIT_FILES} migrated_files = util/migrated_files.sh ${PRESUBMIT_FILES} diff --git a/util/python-pre-upload.sh b/util/python-pre-upload.sh deleted file mode 100755 index d560e7b6af..0000000000 --- a/util/python-pre-upload.sh +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/bash -# Copyright 2022 The ChromiumOS Authors. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -set -e - -PYTHON_FILES=() - -for path in "$@"; do - case "${path}" in - *.py|*.pyi) - PYTHON_FILES+=("${path}") - ;; - util/chargen) - PYTHON_FILES+=("${path}") - ;; - esac -done - -if [ "${#PYTHON_FILES}" -eq 0 ]; then - # No python changes made, do nothing. - exit 0 -fi - -EXIT_STATUS=0 - -# Wraps a black/isort command and reports how to fix it. -wrap_fix_msg() { - local cmd="$1" - shift - - if ! "${cmd}" "$@"; then - cat <&2 -Looks like the ${cmd} formatter detected that formatting changes -need applied. Fix by running this command from the platform/ec -directory and amending your changes: - - ${cmd} ${PYTHON_FILES[*]} - -EOF - EXIT_STATUS=1 - fi -} - -# black and isort are provided by repo_tools -wrap_fix_msg black --check "${PYTHON_FILES[@]}" -wrap_fix_msg isort --check "${PYTHON_FILES[@]}" - -exit "${EXIT_STATUS}" -- cgit v1.2.1 From 3eb29b6aa5a4e5e8c85046be789c6dd8d38afbaa Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 15 Jul 2022 10:31:26 -0700 Subject: builtin: Move ssize_t to sys/types.h According to POSIX ssize_t should be defined in sys/types.h, not stddef.h: https://pubs.opengroup.org/onlinepubs/9699919799.2018edition/basedefs/sys_types.h.html BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -b all => MATCH Signed-off-by: Tom Hughes Change-Id: I027a2b26dc183c506d691d483c86644d04db9282 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765450 Reviewed-by: Jack Rosenthal --- builtin/stddef.h | 6 ------ builtin/sys/types.h | 7 +++++++ driver/accelgyro_icm_common.h | 2 ++ driver/fingerprint/fpc/libfp/fpc_private.c | 1 + 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/builtin/stddef.h b/builtin/stddef.h index de8a67688e..d93a8c7f9f 100644 --- a/builtin/stddef.h +++ b/builtin/stddef.h @@ -11,12 +11,6 @@ #endif typedef __SIZE_TYPE__ size_t; -/* There is a GCC macro for a size_t type, but not for a ssize_t type. - * The following construct convinces GCC to make __SIZE_TYPE__ signed. - */ -#define unsigned signed -typedef __SIZE_TYPE__ ssize_t; -#undef unsigned #ifndef NULL #define NULL ((void *)0) diff --git a/builtin/sys/types.h b/builtin/sys/types.h index 3f8de955e0..57dd4ac479 100644 --- a/builtin/sys/types.h +++ b/builtin/sys/types.h @@ -9,4 +9,11 @@ /* Data type for POSIX style clock() implementation */ typedef long clock_t; +/* There is a GCC macro for a size_t type, but not for a ssize_t type. + * The following construct convinces GCC to make __SIZE_TYPE__ signed. + */ +#define unsigned signed +typedef __SIZE_TYPE__ ssize_t; +#undef unsigned + #endif /* __CROS_EC_SYS_TYPES_H__ */ diff --git a/driver/accelgyro_icm_common.h b/driver/accelgyro_icm_common.h index 89586a482f..7845f68177 100644 --- a/driver/accelgyro_icm_common.h +++ b/driver/accelgyro_icm_common.h @@ -8,6 +8,8 @@ #ifndef __CROS_EC_ACCELGYRO_ICM_COMMON_H #define __CROS_EC_ACCELGYRO_ICM_COMMON_H +#include + #include "accelgyro.h" #include "hwtimer.h" #include "timer.h" diff --git a/driver/fingerprint/fpc/libfp/fpc_private.c b/driver/fingerprint/fpc/libfp/fpc_private.c index e383bb14d9..0af7297119 100644 --- a/driver/fingerprint/fpc/libfp/fpc_private.c +++ b/driver/fingerprint/fpc/libfp/fpc_private.c @@ -4,6 +4,7 @@ */ #include +#include #include "common.h" #include "console.h" #include "fpc_bio_algorithm.h" -- cgit v1.2.1 From 1bc7945394c90dd2b00d8ea7c9201dc368904718 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 17 Jun 2022 15:47:18 -0700 Subject: tree: Move printf declarations to stdio.h The "builtin" directory is EC's copy of the C standard library headers. Move the declarations for printf functions that are provided by the standard library to the "builtin" directory. This change makes it easier for future changes to optionally build with the C standard library instead of the standalone EC subset. BRANCH=none BUG=b:172020503, b:234181908, b:237823627 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I4a5b4f8b98b972e86c4cca65d4910b5aa07ec524 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712034 Reviewed-by: Jack Rosenthal --- builtin/stdio.h | 61 ++++++++++++++++++++++++++++++++++++++++++ builtin/stdlib.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++ common/printf.c | 56 -------------------------------------- include/printf.h | 46 +------------------------------- test/printf.c | 10 ++++++- zephyr/shim/src/console.c | 6 +++++ 6 files changed, 145 insertions(+), 102 deletions(-) create mode 100644 builtin/stdio.h diff --git a/builtin/stdio.h b/builtin/stdio.h new file mode 100644 index 0000000000..b8b6949c45 --- /dev/null +++ b/builtin/stdio.h @@ -0,0 +1,61 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_STDIO_H__ +#define __CROS_EC_STDIO_H__ + +#include +#include + +#include "common.h" + +/** + * Print formatted outut to a string. + * + * Guarantees null-termination if size!=0. + * + * @param str Destination string + * @param size Size of destination in bytes + * @param format Format string + * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated. + */ +__attribute__((__format__(__printf__, 3, 4))) +__warn_unused_result __stdlib_compat int +crec_snprintf(char *str, size_t size, const char *format, ...); + +/** + * Print formatted output to a string. + * + * Guarantees null-termination if size!=0. + * + * @param str Destination string + * @param size Size of destination in bytes + * @param format Format string + * @param args Parameters + * @return The string length written to str, or a negative value on error. + * The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW. + */ +__warn_unused_result __stdlib_compat int +crec_vsnprintf(char *str, size_t size, const char *format, va_list args); + +/* + * Create weak aliases to the crec_* printf functions. This lets us call the + * crec_* printf functions in tests that link the C standard library. + */ + +/** + * Alias to crec_snprintf. + */ +__attribute__((__format__(__printf__, 3, 4))) +__warn_unused_result __stdlib_compat int +snprintf(char *str, size_t size, const char *format, ...); + +/** + * Alias to crec_vsnprintf. + */ +__warn_unused_result __stdlib_compat int +vsnprintf(char *str, size_t size, const char *format, va_list args); + +#endif /* __CROS_EC_STDIO_H__ */ diff --git a/builtin/stdlib.c b/builtin/stdlib.c index 1d07b64869..b3229f4f63 100644 --- a/builtin/stdlib.c +++ b/builtin/stdlib.c @@ -7,7 +7,11 @@ #include "common.h" #include "console.h" +#include "printf.h" #include "util.h" + +#include + /* * The following macros are defined in stdlib.h in the C standard library, which * conflict with the definitions in this file. @@ -19,6 +23,70 @@ #undef isprint #undef tolower +/* Context for snprintf() */ +struct snprintf_context { + char *str; + int size; +}; + +/** + * Add a character to the string context. + * + * @param context Context receiving character + * @param c Character to add + * @return 0 if character added, 1 if character dropped because no space. + */ +static int snprintf_addchar(void *context, int c) +{ + struct snprintf_context *ctx = (struct snprintf_context *)context; + + if (!ctx->size) + return 1; + + *(ctx->str++) = c; + ctx->size--; + return 0; +} + +int crec_vsnprintf(char *str, size_t size, const char *format, va_list args) +{ + struct snprintf_context ctx; + int rv; + + if (!str || !format || size <= 0) + return -EC_ERROR_INVAL; + + ctx.str = str; + ctx.size = size - 1; /* Reserve space for terminating '\0' */ + + rv = vfnprintf(snprintf_addchar, &ctx, format, args); + + /* Terminate string */ + *ctx.str = '\0'; + + return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv; +} +#ifndef CONFIG_ZEPHYR +int vsnprintf(char *str, size_t size, const char *format, va_list args) + __attribute__((weak, alias("crec_vsnprintf"))); +#endif /* CONFIG_ZEPHYR */ + +int crec_snprintf(char *str, size_t size, const char *format, ...) +{ + va_list args; + int rv; + + va_start(args, format); + rv = crec_vsnprintf(str, size, format, args); + va_end(args); + + return rv; +} +#ifndef CONFIG_ZEPHYR +int snprintf(char *str, size_t size, const char *format, ...) + __attribute__((weak, alias("crec_snprintf"))); +#endif /* CONFIG_ZEPHYR */ + /* * TODO(b/237712836): Zephyr's libc should provide strcasecmp. For now we'll * use the EC implementation. diff --git a/common/printf.c b/common/printf.c index 9a3e593cba..91e4e722b0 100644 --- a/common/printf.c +++ b/common/printf.c @@ -488,59 +488,3 @@ int vfnprintf(int (*addchar)(void *context, int c), void *context, /* If we're still here, we consumed all output */ return EC_SUCCESS; } - -/* Context for snprintf() */ -struct snprintf_context { - char *str; - int size; -}; - -/** - * Add a character to the string context. - * - * @param context Context receiving character - * @param c Character to add - * @return 0 if character added, 1 if character dropped because no space. - */ -static int snprintf_addchar(void *context, int c) -{ - struct snprintf_context *ctx = (struct snprintf_context *)context; - - if (!ctx->size) - return 1; - - *(ctx->str++) = c; - ctx->size--; - return 0; -} - -int crec_snprintf(char *str, size_t size, const char *format, ...) -{ - va_list args; - int rv; - - va_start(args, format); - rv = crec_vsnprintf(str, size, format, args); - va_end(args); - - return rv; -} - -int crec_vsnprintf(char *str, size_t size, const char *format, va_list args) -{ - struct snprintf_context ctx; - int rv; - - if (!str || !format || size <= 0) - return -EC_ERROR_INVAL; - - ctx.str = str; - ctx.size = size - 1; /* Reserve space for terminating '\0' */ - - rv = vfnprintf(snprintf_addchar, &ctx, format, args); - - /* Terminate string */ - *ctx.str = '\0'; - - return (rv == EC_SUCCESS) ? (ctx.str - str) : -rv; -} diff --git a/include/printf.h b/include/printf.h index b63208f84d..f6330ff9c3 100644 --- a/include/printf.h +++ b/include/printf.h @@ -11,15 +11,9 @@ #include /* For va_list */ #include #include /* For size_t */ -#include "common.h" #include "console.h" - -/* The declaration of snprintf is changed to crec_snprintf for Zephyr, - * so include stdio.h from Zephyr. - */ -#ifdef CONFIG_ZEPHYR #include -#endif +#include "common.h" /** * Buffer size in bytes large enough to hold the largest possible timestamp. @@ -66,8 +60,6 @@ * - 'p' - pointer */ -#ifndef HIDE_EC_STDLIB - /** * Print formatted output to a function, like vfprintf() * @@ -84,42 +76,6 @@ __stdlib_compat int vfnprintf(int (*addchar)(void *context, int c), void *context, const char *format, va_list args); -#ifndef CONFIG_ZEPHYR -#define snprintf crec_snprintf -#define vsnprintf crec_vsnprintf -#endif - -/** - * Print formatted outut to a string. - * - * Guarantees null-termination if size!=0. - * - * @param str Destination string - * @param size Size of destination in bytes - * @param format Format string - * @return EC_SUCCESS, or EC_ERROR_OVERFLOW if the output was truncated. - */ -__attribute__((__format__(__printf__, 3, 4))) -__warn_unused_result __stdlib_compat int -crec_snprintf(char *str, size_t size, const char *format, ...); - -/** - * Print formatted output to a string. - * - * Guarantees null-termination if size!=0. - * - * @param str Destination string - * @param size Size of destination in bytes - * @param format Format string - * @param args Parameters - * @return The string length written to str, or a negative value on error. - * The negative values can be -EC_ERROR_INVAL or -EC_ERROR_OVERFLOW. - */ -__warn_unused_result __stdlib_compat int -crec_vsnprintf(char *str, size_t size, const char *format, va_list args); - -#endif /* !HIDE_EC_STDLIB */ - #ifdef TEST_BUILD /** * Converts @val to a string written in @buf. The value is converted from diff --git a/test/printf.c b/test/printf.c index 3928185918..69c0d76281 100644 --- a/test/printf.c +++ b/test/printf.c @@ -12,6 +12,13 @@ #include "test_util.h" #include "util.h" +/* + * This file is intended to test the EC printf implementation. We need to + * include the builtin header file directly so that we can call the EC + * version (crec_vsnprintf) when linking with the standard library on the host. + */ +#include "builtin/stdio.h" + #define INIT_VALUE 0x5E #define NO_BYTES_TOUCHED NULL @@ -33,7 +40,8 @@ int run(int expect_ret, const char *expect, bool output_null, size_t size_limit, TEST_ASSERT(expect_size <= size_limit); memset(output, INIT_VALUE, sizeof(output)); - rv = vsnprintf(output_null ? NULL : output, size_limit, format, args); + rv = crec_vsnprintf(output_null ? NULL : output, size_limit, format, + args); ccprintf("received='%.*s' | ret =%d\n", 30, output, rv); TEST_ASSERT_ARRAY_EQ(output, expect, expect_size); diff --git a/zephyr/shim/src/console.c b/zephyr/shim/src/console.c index 8dafaf9803..e9b0c72790 100644 --- a/zephyr/shim/src/console.c +++ b/zephyr/shim/src/console.c @@ -17,6 +17,12 @@ #include #include +/* + * TODO(b/238433667): Include EC printf functions + * (crec_vsnprintf/crec_snprintf) until we switch to the standard + * vsnprintf/snprintf. + */ +#include "builtin/stdio.h" #include "console.h" #include "printf.h" #include "task.h" -- cgit v1.2.1 From f8a5f4dd4e57a5c76a4f6f6b0b9a7b2178017376 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 6 Jul 2022 15:05:20 -0700 Subject: test/printf: Account for differences in the builtin printf EC's printf implementation has some bugs, which results in different output when compared to printf from the standard library. Account for these with a conditional until they are fixed. BRANCH=none BUG=b:234181908, b:238433667, b:239233116 TEST=make BOARD=dartmonkey test-printf TEST=make run-printf Signed-off-by: Tom Hughes Change-Id: Ie8006a128f5cc1c32f1248c004697c61f4ac001a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750110 Reviewed-by: Ting Shen --- test/printf.c | 178 ++++++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 123 insertions(+), 55 deletions(-) diff --git a/test/printf.c b/test/printf.c index 69c0d76281..0d96472122 100644 --- a/test/printf.c +++ b/test/printf.c @@ -12,12 +12,21 @@ #include "test_util.h" #include "util.h" +#ifdef USE_BUILTIN_STDLIB /* - * This file is intended to test the EC printf implementation. We need to - * include the builtin header file directly so that we can call the EC - * version (crec_vsnprintf) when linking with the standard library on the host. + * When USE_BUILTIN_STDLIB is defined, we want to test the EC printf + * implementation. We need to include the builtin header file directly so + * that we can call the EC version (crec_vsnprintf) when linking with the + * standard library on the host. */ #include "builtin/stdio.h" +#define VSNPRINTF crec_vsnprintf +static const bool use_builtin_stdlib = true; +#else +#include +#define VSNPRINTF vsnprintf +static const bool use_builtin_stdlib = false; +#endif #define INIT_VALUE 0x5E #define NO_BYTES_TOUCHED NULL @@ -40,8 +49,7 @@ int run(int expect_ret, const char *expect, bool output_null, size_t size_limit, TEST_ASSERT(expect_size <= size_limit); memset(output, INIT_VALUE, sizeof(output)); - rv = crec_vsnprintf(output_null ? NULL : output, size_limit, format, - args); + rv = VSNPRINTF(output_null ? NULL : output, size_limit, format, args); ccprintf("received='%.*s' | ret =%d\n", 30, output, rv); TEST_ASSERT_ARRAY_EQ(output, expect, expect_size); @@ -95,27 +103,33 @@ test_static int test_vsnprintf_args(void) T(expect_success("", "")); T(expect_success("a", "a")); - T(expect(/* expect an invalid args error */ - EC_ERROR_INVAL, NO_BYTES_TOUCHED, - /* given 0 as output size limit */ - false, 0, "")); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This differs from the C standard library + * behavior and should probably be changed. + */ + T(expect(/* expect an invalid args error */ + EC_ERROR_INVAL, NO_BYTES_TOUCHED, + /* given 0 as output size limit */ + false, 0, "")); + T(expect(/* expect an overflow error */ + EC_ERROR_OVERFLOW, "", + /* given 1 as output size limit with a non-blank format + */ + false, 1, "a")); + T(expect(/* expect an invalid args error */ + EC_ERROR_INVAL, NO_BYTES_TOUCHED, + /* given NULL as the output buffer */ + true, sizeof(output), "")); + T(expect(/* expect an invalid args error */ + EC_ERROR_INVAL, NO_BYTES_TOUCHED, + /* given a NULL format string */ + false, sizeof(output), NULL)); + } T(expect(/* expect SUCCESS */ EC_SUCCESS, "", /* given 1 as output size limit and a blank format */ false, 1, "")); - T(expect(/* expect an overflow error */ - EC_ERROR_OVERFLOW, "", - /* given 1 as output size limit with a non-blank format */ - false, 1, "a")); - - T(expect(/* expect an invalid args error */ - EC_ERROR_INVAL, NO_BYTES_TOUCHED, - /* given NULL as the output buffer */ - true, sizeof(output), "")); - T(expect(/* expect an invalid args error */ - EC_ERROR_INVAL, NO_BYTES_TOUCHED, - /* given a NULL format string */ - false, sizeof(output), NULL)); return EC_SUCCESS; } @@ -133,42 +147,79 @@ test_static int test_vsnprintf_int(void) T(expect_success(" +123", "%+5d", 123)); T(expect_success("00123", "%05d", 123)); T(expect_success("00123", "%005d", 123)); - /* - * TODO(crbug.com/974084): This odd behavior should be fixed. - * T(expect_success("+0123", "%+05d", 123)); - * Actual: "0+123" - * T(expect_success("+0123", "%+005d", 123)); - * Actual: "0+123" - */ + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): These are incorrect and should be fixed. + */ + T(expect_success("0+123", "%+05d", 123)); + T(expect_success("0+123", "%+005d", 123)); + } else { + T(expect_success("+0123", "%+05d", 123)); + T(expect_success("+0123", "%+005d", 123)); + } T(expect_success(" 123", "%*d", 5, 123)); T(expect_success(" +123", "%+*d", 5, 123)); T(expect_success("00123", "%0*d", 5, 123)); - /* - * TODO(crbug.com/974084): This odd behavior should be fixed. - * T(expect_success("00123", "%00*d", 5, 123)); - * Actual: "ERROR" - */ - T(expect_success("0+123", "%+0*d", 5, 123)); - /* - * TODO(crbug.com/974084): This odd behavior should be fixed. - * T(expect_success("0+123", "%+00*d", 5, 123)); - * Actual: "ERROR" - */ + + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This incorrect and should be fixed. + */ + T(expect_success(err_str, "%00*d", 5, 123)); + } else { + T(expect_success("00123", "%00*d", 5, 123)); + } + + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This is incorrect and should be fixed. + */ + T(expect_success("0+123", "%+0*d", 5, 123)); + } else { + T(expect_success("+0123", "%+0*d", 5, 123)); + } + + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This is incorrect and should be fixed. + */ + T(expect_success(err_str, "%+00*d", 5, 123)); + } else { + T(expect_success("+0123", "%+00*d", 5, 123)); + } T(expect_success("123 ", "%-5d", 123)); T(expect_success("+123 ", "%-+5d", 123)); - T(expect_success(err_str, "%+-5d", 123)); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This incorrect and should be fixed. + */ + T(expect_success(err_str, "%+-5d", 123)); + } else { + T(expect_success("+123 ", "%+-5d", 123)); + } T(expect_success("123 ", "%-05d", 123)); T(expect_success("123 ", "%-005d", 123)); T(expect_success("+123 ", "%-+05d", 123)); T(expect_success("+123 ", "%-+005d", 123)); - T(expect_success("0.00123", "%.5d", 123)); - T(expect_success("+0.00123", "%+.5d", 123)); - T(expect_success("0.00123", "%7.5d", 123)); - T(expect_success(" 0.00123", "%9.5d", 123)); - T(expect_success(" +0.00123", "%+9.5d", 123)); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): These are incorrect and should be fixed. + */ + T(expect_success("0.00123", "%.5d", 123)); + T(expect_success("+0.00123", "%+.5d", 123)); + T(expect_success("0.00123", "%7.5d", 123)); + T(expect_success(" 0.00123", "%9.5d", 123)); + T(expect_success(" +0.00123", "%+9.5d", 123)); + } else { + T(expect_success("00123", "%.5d", 123)); + T(expect_success("+00123", "%+.5d", 123)); + T(expect_success(" 00123", "%7.5d", 123)); + T(expect_success(" 00123", "%9.5d", 123)); + T(expect_success(" +00123", "%+9.5d", 123)); + } T(expect_success("123", "%u", 123)); T(expect_success("4294967295", "%u", -1)); @@ -255,8 +306,16 @@ test_static int test_vsnprintf_64bit_long_supported(void) T(expect_success("00000123", "%08lu", 123)); T(expect_success("131415", "%d%lu%d", 13, 14L, 15)); - T(expect_success(err_str, "%i", 123)); - T(expect_success(err_str, "%li", 123)); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): These are incorrect and should be fixed. + */ + T(expect_success(err_str, "%i", 123)); + T(expect_success(err_str, "%li", 123)); + } else { + T(expect_success("123", "%i", 123)); + T(expect_success("123", "%li", 123)); + } return EC_SUCCESS; } @@ -295,7 +354,14 @@ test_static int test_vsnprintf_pointers(void) { void *ptr = (void *)0x55005E00; - T(expect_success("55005e00", "%p", ptr)); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This incorrect and should be fixed. + */ + T(expect_success("55005e00", "%p", ptr)); + } else { + T(expect_success("0x55005e00", "%p", ptr)); + } return EC_SUCCESS; } @@ -318,12 +384,14 @@ test_static int test_vsnprintf_strings(void) T(expect_success("a", "%.*s", 1, "abc")); T(expect_success("", "%.0s", "abc")); T(expect_success("", "%.*s", 0, "abc")); - /* - * TODO(crbug.com/974084): - * Ignoring the padding parameter is slightly - * odd behavior and could use a review. - */ - T(expect_success("ab", "%5.2s", "abc")); + if (use_builtin_stdlib) { + /* + * TODO(b/239233116): This incorrect and should be fixed. + */ + T(expect_success("ab", "%5.2s", "abc")); + } else { + T(expect_success(" ab", "%5.2s", "abc")); + } T(expect_success("abc", "%.4s", "abc")); /* -- cgit v1.2.1 From fd972cd0bcf2695949f3f6818f249e532e280695 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 6 Jul 2022 16:09:44 -0700 Subject: tree: Remove HIDE_EC_STDLIB HIDE_EC_STDLIB is no longer needed now that the stdlib code has been separated out from the EC code. BRANCH=none BUG=b:234181908 TEST=make runfuzztests Signed-off-by: Tom Hughes Change-Id: Id47327c5061239b97b2e2f82791719f01b4e9ad8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3750109 Reviewed-by: Keith Short --- fuzz/pchg_fuzz.c | 1 - fuzz/usb_pd_fuzz.c | 1 - fuzz/usb_tcpm_v2_rev20_fuzz.c | 1 - include/common.h | 3 +-- 4 files changed, 1 insertion(+), 5 deletions(-) diff --git a/fuzz/pchg_fuzz.c b/fuzz/pchg_fuzz.c index eced90bb5e..e4a7cdd3fa 100644 --- a/fuzz/pchg_fuzz.c +++ b/fuzz/pchg_fuzz.c @@ -5,7 +5,6 @@ * Test peripheral device charger module. */ -#define HIDE_EC_STDLIB #include "common.h" #include "compile_time_macros.h" #include "driver/nfc/ctn730.h" diff --git a/fuzz/usb_pd_fuzz.c b/fuzz/usb_pd_fuzz.c index f92c7905ba..4d67780a71 100644 --- a/fuzz/usb_pd_fuzz.c +++ b/fuzz/usb_pd_fuzz.c @@ -4,7 +4,6 @@ * * Test USB PD module. */ -#define HIDE_EC_STDLIB #include "common.h" #include "task.h" #include "tcpm/tcpm.h" diff --git a/fuzz/usb_tcpm_v2_rev20_fuzz.c b/fuzz/usb_tcpm_v2_rev20_fuzz.c index 2f0129464a..8c2f6c7eff 100644 --- a/fuzz/usb_tcpm_v2_rev20_fuzz.c +++ b/fuzz/usb_tcpm_v2_rev20_fuzz.c @@ -5,7 +5,6 @@ * Stubs needed for fuzz testing the USB TCPMv2 state machines. */ -#define HIDE_EC_STDLIB #include "charge_manager.h" #include "mock/usb_mux_mock.h" #include "usb_pd.h" diff --git a/include/common.h b/include/common.h index 7a549a6d55..dc20787e5b 100644 --- a/include/common.h +++ b/include/common.h @@ -372,8 +372,7 @@ enum ec_error_list { /* * Mark functions that collide with stdlib so they can be hidden when linking - * against libraries that require stdlib. HIDE_EC_STDLIB should be defined - * before including common.h from code that links to cstdlib. + * against libraries that require stdlib. */ #ifdef TEST_FUZZ #define __stdlib_compat __attribute__((visibility("hidden"))) -- cgit v1.2.1 From 05612223ba9bfb08e47b374fc4a81b1e65e5f35e Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Fri, 24 Jun 2022 12:04:25 -0700 Subject: Makefile: Add option to compile with the C standard library Add the USE_BUILTIN_STDLIB variable, which defaults to 1 and will use the EC standard library implementation (the "builtin" directory). When USE_BUILTIN_STDLIB is set to 0, the toolchain's C standard library will be used instead. BRANCH=none BUG=b:234181908 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes Change-Id: I63285569205b9c560655dfead6a260c270a92494 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3712035 Reviewed-by: Eric Yilun Lin --- Makefile | 6 ++++++ Makefile.toolchain | 21 +++++++++++++++++++-- third_party/rules.mk | 2 ++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index cdf926daa8..3e07f151f4 100644 --- a/Makefile +++ b/Makefile @@ -268,7 +268,9 @@ include $(BASEDIR)/build.mk ifneq ($(BASEDIR),$(BDIR)) include $(BDIR)/build.mk endif +ifeq ($(USE_BUILTIN_STDLIB), 1) include builtin/build.mk +endif include chip/$(CHIP)/build.mk include core/$(CORE)/build.mk include common/build.mk @@ -308,7 +310,9 @@ ifneq ($(PBDIR),) all-obj-$(1)+=$(call objs_from_dir_p,$(PBDIR),board-private,$(1)) endif all-obj-$(1)+=$(call objs_from_dir_p,common,common,$(1)) +ifeq ($(USE_BUILTIN_STDLIB), 1) all-obj-$(1)+=$(call objs_from_dir_p,builtin,builtin,$(1)) +endif all-obj-$(1)+=$(call objs_from_dir_p,driver,driver,$(1)) all-obj-$(1)+=$(call objs_from_dir_p,power,power,$(1)) ifdef CTS_MODULE @@ -355,7 +359,9 @@ dirs=core/$(CORE) chip/$(CHIP) $(BASEDIR) $(BDIR) common fuzz power test \ dirs+= private private-kandou $(PDIR) $(PBDIR) dirs+=$(shell find common -type d) dirs+=$(shell find driver -type d) +ifeq ($(USE_BUILTIN_STDLIB), 1) dirs+=builtin +endif common_dirs=util ifeq ($(custom-ro_objs-y),) diff --git a/Makefile.toolchain b/Makefile.toolchain index 2ce8f2ba5f..fcb2dd4b00 100644 --- a/Makefile.toolchain +++ b/Makefile.toolchain @@ -23,6 +23,12 @@ ifneq ($(TEST_FUZZ)$(TEST_ASAN)$(TEST_MSAN)$(TEST_UBSAN),) CC=clang endif +# When set to 1, use the subset of the C standard library implemented in EC +# (the "builtin" directory). +# When set to 0, link against the toolchain's implementation of the C standard +# library. +USE_BUILTIN_STDLIB:=1 + # Extract cc-name cc-name:=$(shell $(CC) -v 2>&1 | grep -q "clang version" && echo clang || echo gcc) @@ -124,8 +130,11 @@ HOST_CPPFLAGS=$(CFLAGS_DEFINE) $(CFLAGS_INCLUDE) $(CFLAGS_TEST) \ $(EXTRA_CFLAGS) $(CFLAGS_COVERAGE) $(CFLAGS_HOSTTEST) $(LATE_CFLAGS_DEFINE) \ -DSECTION_IS_$(BLD)=$(EMPTY) -DSECTION=$(BLD) $(CPPFLAGS_$(BLD)) ifneq ($(BOARD),host) -CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib -fno-PIC +CPPFLAGS+=-fno-PIC +ifeq ($(USE_BUILTIN_STDLIB), 1) +CPPFLAGS+=-ffreestanding -fno-builtin -nostdinc -nostdlib CPPFLAGS+=-Ibuiltin/ +endif else CPPFLAGS+=-Og endif @@ -139,6 +148,9 @@ CFLAGS+= -ffat-lto-objects CFLAGS+= -fconserve-stack endif CXXFLAGS+=-DPROTOBUF_INLINE_NOT_IN_HEADERS=0 +ifeq ($(USE_BUILTIN_STDLIB), 1) +CPPFLAGS+=-DUSE_BUILTIN_STDLIB +endif ifeq ($(LIBFTDI_NAME),) FTDIVERSION:=$(shell $(PKG_CONFIG) --modversion libftdi1 2>/dev/null) @@ -173,8 +185,13 @@ HOST_CXXFLAGS=$(HOST_CFLAGS) ifneq (${SYSROOT},) LDFLAGS_EXTRA+=--sysroot=${SYSROOT} endif -LDFLAGS=-nostdlib -g -no-pie -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \ +LDFLAGS=-g -no-pie -Wl,-X -Wl,--gc-sections -Wl,--build-id=none \ $(LDFLAGS_EXTRA) $(CFLAGS_CPU) +ifeq ($(USE_BUILTIN_STDLIB), 1) +LDFLAGS+=-nostdlib +else +LDFLAGS+=-lnosys +endif MEMSIZE_FLAGS= ifeq ($(cc-name),gcc) MEMSIZE_FLAGS+=-Wl,--print-memory-usage diff --git a/third_party/rules.mk b/third_party/rules.mk index 16fd1e52e3..c729aa24ef 100644 --- a/third_party/rules.mk +++ b/third_party/rules.mk @@ -23,8 +23,10 @@ cmd_libcryptoc = $(MAKE) -C $(CRYPTOC_DIR) \ cmd_libcryptoc_clean = $(cmd_libcryptoc) -q && echo clean ifneq ($(BOARD),host) +ifeq ($(USE_BUILTIN_STDLIB), 1) CPPFLAGS += -I$(abspath ./builtin) endif +endif CPPFLAGS += -I$(CRYPTOC_DIR)/include CRYPTOC_LDFLAGS := -L$(out)/cryptoc -lcryptoc -- cgit v1.2.1 From 3f5963fd7c75715f168cc757329b4a4761729491 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Fri, 15 Jul 2022 10:08:24 -0600 Subject: zephyr: Fix some warnings in zmake build When you run zmake build skyrim there are some warnings printed. Explicitly disable some Kconfigs that are implicitly disabled. BRANCH=None BUG=None TEST=zmake build skyrim Signed-off-by: Jeremy Bettis Change-Id: I8aff2701bd81c9d337242af6ed68ff654fe6860c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3765444 Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis Commit-Queue: Diana Z Reviewed-by: Diana Z --- zephyr/projects/skyrim/prj.conf | 5 ----- zephyr/projects/skyrim/prj_skyrim.conf | 1 - 2 files changed, 6 deletions(-) diff --git a/zephyr/projects/skyrim/prj.conf b/zephyr/projects/skyrim/prj.conf index 9717aa9d2c..3d61e400b3 100644 --- a/zephyr/projects/skyrim/prj.conf +++ b/zephyr/projects/skyrim/prj.conf @@ -61,11 +61,6 @@ CONFIG_SENSOR_SHELL=n # Fan CONFIG_TACH_NPCX=y -# LEDs -CONFIG_PLATFORM_EC_LED_COMMON=y -CONFIG_PLATFORM_EC_LED_ONOFF_STATES=y -CONFIG_PLATFORM_EC_LED_PWM=y - # Lid switch CONFIG_PLATFORM_EC_LID_ANGLE=y CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y diff --git a/zephyr/projects/skyrim/prj_skyrim.conf b/zephyr/projects/skyrim/prj_skyrim.conf index 4f9696887b..f5aff6b474 100644 --- a/zephyr/projects/skyrim/prj_skyrim.conf +++ b/zephyr/projects/skyrim/prj_skyrim.conf @@ -10,7 +10,6 @@ CONFIG_PLATFORM_EC_EEPROM_CBI_WP=y CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=y # LED -CONFIG_PLATFORM_EC_LED_COMMON=n CONFIG_PLATFORM_EC_LED_DT=y # Only Skyrim has the PCT2075 -- cgit v1.2.1 From 7ae9a8daffde9b5451dff964646323a6aa9a0f9a Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Mon, 18 Jul 2022 13:24:51 -0600 Subject: emul: Remove DT_INST_BUS_LABEL(n) usage Zephyr upstream deprecated DT_BUS_LABEL(node_id) and DT_INST_BUS_LABEL(inst) macros causing a CQ build failure and blocking Zephyr downstreaming. Replace code occurrences of DT_INST_BUS_LABEL(inst) with DT_LABEL(DT_BUS(DT_DRV_INST(inst))). This macro was only used in emulators. BRANCH=none BUG=b:239447869 TEST=zmake test test-drivers # With breaking commit in downstreamed Zephyr Signed-off-by: Aaron Massey Change-Id: If745caeb1273c7e51331bd45b17dc28960c7f8da Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3767857 Reviewed-by: Jack Rosenthal Reviewed-by: Fabio Baltieri Reviewed-by: Tristan Honscheid --- zephyr/emul/emul_bb_retimer.c | 2 +- zephyr/emul/emul_bma255.c | 2 +- zephyr/emul/emul_bmi.c | 2 +- zephyr/emul/emul_isl923x.c | 2 +- zephyr/emul/emul_lis2dw12.c | 2 +- zephyr/emul/emul_ln9310.c | 2 +- zephyr/emul/emul_pi3usb9201.c | 2 +- zephyr/emul/emul_smart_battery.c | 2 +- zephyr/emul/emul_sn5s330.c | 2 +- zephyr/emul/emul_syv682x.c | 2 +- zephyr/emul/emul_tcs3400.c | 2 +- zephyr/emul/i2c_mock.c | 2 +- zephyr/emul/tcpc/emul_ps8xxx.c | 6 +++--- zephyr/include/emul/tcpc/emul_tcpci.h | 2 +- 14 files changed, 16 insertions(+), 16 deletions(-) diff --git a/zephyr/emul/emul_bb_retimer.c b/zephyr/emul/emul_bb_retimer.c index 8a9d8b5633..54402555bb 100644 --- a/zephyr/emul/emul_bb_retimer.c +++ b/zephyr/emul/emul_bb_retimer.c @@ -334,7 +334,7 @@ static int bb_emul_init(const struct emul *emul, const struct device *parent) }; \ \ static const struct i2c_common_emul_cfg bb_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &bb_emul_data_##n.common, \ .addr = DT_INST_REG_ADDR(n), \ diff --git a/zephyr/emul/emul_bma255.c b/zephyr/emul/emul_bma255.c index afd9f5fb7b..ca75442156 100644 --- a/zephyr/emul/emul_bma255.c +++ b/zephyr/emul/emul_bma255.c @@ -1010,7 +1010,7 @@ static int bma_emul_init(const struct emul *emul, const struct device *parent) }; \ \ static const struct i2c_common_emul_cfg bma_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &bma_emul_data_##n.common, \ .addr = DT_INST_REG_ADDR(n), \ diff --git a/zephyr/emul/emul_bmi.c b/zephyr/emul/emul_bmi.c index bdc440a36f..23f0bfddeb 100644 --- a/zephyr/emul/emul_bmi.c +++ b/zephyr/emul/emul_bmi.c @@ -1087,7 +1087,7 @@ static int bmi_emul_init(const struct emul *emul, const struct device *parent) }; \ \ static const struct i2c_common_emul_cfg bmi_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &bmi_emul_data_##n.common, \ .addr = DT_INST_REG_ADDR(n), \ diff --git a/zephyr/emul/emul_isl923x.c b/zephyr/emul/emul_isl923x.c index cb6abd849e..8a49f569dc 100644 --- a/zephyr/emul/emul_isl923x.c +++ b/zephyr/emul/emul_isl923x.c @@ -434,7 +434,7 @@ static int emul_isl923x_init(const struct emul *emul, }; \ static struct isl923x_emul_cfg isl923x_emul_cfg_##n = { \ .common = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ diff --git a/zephyr/emul/emul_lis2dw12.c b/zephyr/emul/emul_lis2dw12.c index 0d99585b8e..b0e85f50b5 100644 --- a/zephyr/emul/emul_lis2dw12.c +++ b/zephyr/emul/emul_lis2dw12.c @@ -304,7 +304,7 @@ void lis2dw12_emul_clear_accel_reading(const struct emul *emul) }; \ static const struct lis2dw12_emul_cfg lis2dw12_emul_cfg_##n = { \ .common = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ diff --git a/zephyr/emul/emul_ln9310.c b/zephyr/emul/emul_ln9310.c index ae213ddebf..d66f23a1a5 100644 --- a/zephyr/emul/emul_ln9310.c +++ b/zephyr/emul/emul_ln9310.c @@ -506,7 +506,7 @@ static int emul_ln9310_init(const struct emul *emul, .gpio_int_pin = LN9310_GET_GPIO_INT_PIN(n), \ }; \ static const struct i2c_common_emul_cfg ln9310_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }; \ diff --git a/zephyr/emul/emul_pi3usb9201.c b/zephyr/emul/emul_pi3usb9201.c index ee33152b84..d98db3b3e8 100644 --- a/zephyr/emul/emul_pi3usb9201.c +++ b/zephyr/emul/emul_pi3usb9201.c @@ -171,7 +171,7 @@ static int pi3usb9201_emul_init(const struct emul *emul, #define PI3USB9201_EMUL(n) \ static struct pi3usb9201_emul_data pi3usb9201_emul_data_##n = {}; \ static const struct pi3usb9201_emul_cfg pi3usb9201_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .data = &pi3usb9201_emul_data_##n, \ .addr = DT_INST_REG_ADDR(n), \ }; \ diff --git a/zephyr/emul/emul_smart_battery.c b/zephyr/emul/emul_smart_battery.c index 8ba61c56c4..fd20997049 100644 --- a/zephyr/emul/emul_smart_battery.c +++ b/zephyr/emul/emul_smart_battery.c @@ -874,7 +874,7 @@ static int sbat_emul_init(const struct emul *emul, const struct device *parent) }; \ \ static const struct i2c_common_emul_cfg sbat_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &sbat_emul_data_##n.common, \ .addr = DT_INST_REG_ADDR(n), \ diff --git a/zephyr/emul/emul_sn5s330.c b/zephyr/emul/emul_sn5s330.c index 1b58e8e9ad..b515b832a1 100644 --- a/zephyr/emul/emul_sn5s330.c +++ b/zephyr/emul/emul_sn5s330.c @@ -359,7 +359,7 @@ static int emul_sn5s330_init(const struct emul *emul, }; \ static struct sn5s330_emul_cfg sn5s330_emul_cfg_##n = { \ .common = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ diff --git a/zephyr/emul/emul_syv682x.c b/zephyr/emul/emul_syv682x.c index 870b51dd52..ab7ba9ff91 100644 --- a/zephyr/emul/emul_syv682x.c +++ b/zephyr/emul/emul_syv682x.c @@ -279,7 +279,7 @@ static int syv682x_emul_init(const struct emul *emul, }; \ static const struct syv682x_emul_cfg syv682x_emul_cfg_##n = { \ .common = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }, \ diff --git a/zephyr/emul/emul_tcs3400.c b/zephyr/emul/emul_tcs3400.c index fe5d605232..0bb48fccd1 100644 --- a/zephyr/emul/emul_tcs3400.c +++ b/zephyr/emul/emul_tcs3400.c @@ -621,7 +621,7 @@ static int tcs_emul_init(const struct emul *emul, const struct device *parent) }; \ \ static const struct i2c_common_emul_cfg tcs_emul_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &tcs_emul_data_##n.common, \ .addr = DT_INST_REG_ADDR(n), \ diff --git a/zephyr/emul/i2c_mock.c b/zephyr/emul/i2c_mock.c index ecacf95369..207151ef6c 100644 --- a/zephyr/emul/i2c_mock.c +++ b/zephyr/emul/i2c_mock.c @@ -58,7 +58,7 @@ static int i2c_mock_init(const struct emul *emul, const struct device *parent) #define INIT_I2C_MOCK(n) \ static const struct i2c_common_emul_cfg i2c_mock_cfg_##n = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .addr = DT_INST_REG_ADDR(n), \ }; \ diff --git a/zephyr/emul/tcpc/emul_ps8xxx.c b/zephyr/emul/tcpc/emul_ps8xxx.c index 43e7c2fdd7..477070460f 100644 --- a/zephyr/emul/tcpc/emul_ps8xxx.c +++ b/zephyr/emul/tcpc/emul_ps8xxx.c @@ -583,19 +583,19 @@ static int ps8xxx_emul_init(const struct emul *emul, \ static const struct ps8xxx_emul_cfg ps8xxx_emul_cfg_##n = { \ .p0_cfg = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &ps8xxx_emul_data_##n.p0_data, \ .addr = DT_INST_PROP(n, p0_i2c_addr), \ }, \ .p1_cfg = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &ps8xxx_emul_data_##n.p1_data, \ .addr = DT_INST_PROP(n, p1_i2c_addr), \ }, \ .gpio_cfg = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &ps8xxx_emul_data_##n.gpio_data, \ .addr = DT_INST_PROP(n, gpio_i2c_addr), \ diff --git a/zephyr/include/emul/tcpc/emul_tcpci.h b/zephyr/include/emul/tcpc/emul_tcpci.h index f819a60567..9841915d1e 100644 --- a/zephyr/include/emul/tcpc/emul_tcpci.h +++ b/zephyr/include/emul/tcpc/emul_tcpci.h @@ -117,7 +117,7 @@ struct tcpc_emul_data { .tcpci_ctx = &tcpci_ctx##n, \ .chip_data = chip_data_ptr, \ .i2c_cfg = { \ - .i2c_label = DT_INST_BUS_LABEL(n), \ + .i2c_label = DT_LABEL(DT_BUS(DT_DRV_INST(n))), \ .dev_label = DT_INST_LABEL(n), \ .data = &tcpci_ctx##n.common, \ .addr = DT_INST_REG_ADDR(n), \ -- cgit v1.2.1 From b7792695c5120a488c8eec5a734716fe2942838a Mon Sep 17 00:00:00 2001 From: Aaron Massey Date: Tue, 19 Jul 2022 10:23:35 -0600 Subject: zephyr: Remove DT_GPIO_LABEL_BY_IDX usage Zephyr upstream deprecated the DT_GPIO_LABEL_BY_IDX macro used by downstream UNUSED_GPIO_CONFIG_BY_IDX macro causing a CQ build failure and blocking Zephyr downstreaming. Replace use of DT_GPIO_LABEL_BY_IDX with DT_GPIO_CTLR_BY_IDX. Note: This change also includes a switch from using DT_LABEL to DEVICE_DT_NAME which is less likely to be deprecated and evaluates to the same result if a LABEL property is present. BRANCH=none BUG=b:239447869 TEST=zmake test build -a # With breaking commit in downstreamed Zephyr Signed-off-by: Aaron Massey Change-Id: I8af3f21dbf5b8ab05cd1c1d9cfc483fa3c25b850 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3773935 Reviewed-by: Tristan Honscheid Reviewed-by: Jack Rosenthal --- zephyr/shim/include/gpio/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/zephyr/shim/include/gpio/gpio.h b/zephyr/shim/include/gpio/gpio.h index 6f92ed5795..cae87ec859 100644 --- a/zephyr/shim/include/gpio/gpio.h +++ b/zephyr/shim/include/gpio/gpio.h @@ -74,8 +74,8 @@ int gpio_config_unused_pins(void) __attribute__((weak)); */ #define UNUSED_GPIO_CONFIG_BY_IDX(i, _) \ { \ - .dev_name = DT_GPIO_LABEL_BY_IDX(UNUSED_PINS_LIST, \ - unused_gpios, i), \ + .dev_name = DEVICE_DT_NAME(DT_GPIO_CTLR_BY_IDX( \ + UNUSED_PINS_LIST, unused_gpios, i)), \ .pin = DT_GPIO_PIN_BY_IDX(UNUSED_PINS_LIST, unused_gpios, i), \ .flags = DT_GPIO_FLAGS_BY_IDX(UNUSED_PINS_LIST, unused_gpios, \ i), \ -- cgit v1.2.1 From dc7d08fc7daaf04b84c31a1652f01e47cc6a9c20 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Wed, 13 Jul 2022 10:26:00 -0600 Subject: util: Delete kconfiglib.py The missing code has been applied to the ebuild, so this copy is no longer needed. BRANCH=None BUG=b:238773780 FIXED=b:238773780 TEST=util/run_tests.sh Cq-Depend: chromium:3763390 Change-Id: I4f774c5ca4f2ae67eac07be06f06fee93fe1dbb3 Signed-off-by: Jeremy Bettis Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3760659 Reviewed-by: Jack Rosenthal Tested-by: Jeremy Bettis Commit-Queue: Jeremy Bettis --- util/kconfiglib.py | 7462 ---------------------------------------------------- 1 file changed, 7462 deletions(-) delete mode 100644 util/kconfiglib.py diff --git a/util/kconfiglib.py b/util/kconfiglib.py deleted file mode 100644 index dabd03d8ca..0000000000 --- a/util/kconfiglib.py +++ /dev/null @@ -1,7462 +0,0 @@ -# Copyright (c) 2011-2019, Ulf Magnusson -# SPDX-License-Identifier: ISC - -# Third-party code, ignore pylint problems -# pylint:disable=all - -""" -Overview -======== - -Kconfiglib is a Python 2/3 library for scripting and extracting information -from Kconfig (https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt) -configuration systems. - -See the homepage at https://github.com/ulfalizer/Kconfiglib for a longer -overview. - -Since Kconfiglib 12.0.0, the library version is available in -kconfiglib.VERSION, which is a (, , ) tuple, e.g. -(12, 0, 0). - - -Using Kconfiglib on the Linux kernel with the Makefile targets -============================================================== - -For the Linux kernel, a handy interface is provided by the -scripts/kconfig/Makefile patch, which can be applied with either 'git am' or -the 'patch' utility: - - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | git am - $ wget -qO- https://raw.githubusercontent.com/ulfalizer/Kconfiglib/master/makefile.patch | patch -p1 - -Warning: Not passing -p1 to patch will cause the wrong file to be patched. - -Please tell me if the patch does not apply. It should be trivial to apply -manually, as it's just a block of text that needs to be inserted near the other -*conf: targets in scripts/kconfig/Makefile. - -Look further down for a motivation for the Makefile patch and for instructions -on how you can use Kconfiglib without it. - -If you do not wish to install Kconfiglib via pip, the Makefile patch is set up -so that you can also just clone Kconfiglib into the kernel root: - - $ git clone git://github.com/ulfalizer/Kconfiglib.git - $ git am Kconfiglib/makefile.patch (or 'patch -p1 < Kconfiglib/makefile.patch') - -Warning: The directory name Kconfiglib/ is significant in this case, because -it's added to PYTHONPATH by the new targets in makefile.patch. - -The targets added by the Makefile patch are described in the following -sections. - - -make kmenuconfig ----------------- - -This target runs the curses menuconfig interface with Python 3. As of -Kconfiglib 12.2.0, both Python 2 and Python 3 are supported (previously, only -Python 3 was supported, so this was a backport). - - -make guiconfig --------------- - -This target runs the Tkinter menuconfig interface. Both Python 2 and Python 3 -are supported. To change the Python interpreter used, pass -PYTHONCMD= to 'make'. The default is 'python'. - - -make [ARCH=] iscriptconfig --------------------------------- - -This target gives an interactive Python prompt where a Kconfig instance has -been preloaded and is available in 'kconf'. To change the Python interpreter -used, pass PYTHONCMD= to 'make'. The default is 'python'. - -To get a feel for the API, try evaluating and printing the symbols in -kconf.defined_syms, and explore the MenuNode menu tree starting at -kconf.top_node by following 'next' and 'list' pointers. - -The item contained in a menu node is found in MenuNode.item (note that this can -be one of the constants kconfiglib.MENU and kconfiglib.COMMENT), and all -symbols and choices have a 'nodes' attribute containing their menu nodes -(usually only one). Printing a menu node will print its item, in Kconfig -format. - -If you want to look up a symbol by name, use the kconf.syms dictionary. - - -make scriptconfig SCRIPT=